diff --git a/.clang-format b/.clang-format
index 940f22994b8..11054457bc3 100644
--- a/.clang-format
+++ b/.clang-format
@@ -99,6 +99,7 @@ IndentCaseLabels: false
 IndentGotoLabels: false
 IndentWidth: 8
 InsertBraces: true
+InsertNewlineAtEOF: true
 SpaceBeforeInheritanceColon: False
 SpaceBeforeParens: ControlStatementsExceptControlMacros
 SortIncludes: Never
diff --git a/.github/ISSUE_TEMPLATE/007_ext-source.md b/.github/ISSUE_TEMPLATE/007_ext-source.md
index 835450cd507..2b6eb4cebb9 100644
--- a/.github/ISSUE_TEMPLATE/007_ext-source.md
+++ b/.github/ISSUE_TEMPLATE/007_ext-source.md
@@ -49,6 +49,15 @@ required to maintain ...)
 Why is this the right component to solve it (e.g., SQLite is small,
 easy to use, and has a very liberal license.)
 
+## Security
+
+Does this component include any cryptographic functionality?
+If so, please describe the cryptographic algorithms and protocols used.
+
+How does this component handle security vulnerabilities and updates?
+Are there any known vulnerabilities in this component? If so, please
+provide details and references to any CVEs or security advisories.
+
 ## Dependencies
 
 What other components does this package depend on?
diff --git a/.github/SECURITY.md b/.github/SECURITY.md
index ba2dedb99e4..ffbaf1a6b62 100644
--- a/.github/SECURITY.md
+++ b/.github/SECURITY.md
@@ -11,9 +11,9 @@ updates:
 At this time, with the latest release of v4.0, the supported
 versions are:
 
-  - v4.0: Current release
-  - v3.7: Prior release and Current LTS
-  - v2.7: Prior LTS
+  - v4.1: Current release
+  - v4.0: Prior release
+  - v3.7: Current LTS
 
 ## Reporting process
 
diff --git a/.github/codeql/codeql-actions-config.yml b/.github/codeql/codeql-actions-config.yml
new file mode 100644
index 00000000000..4076bfd99c5
--- /dev/null
+++ b/.github/codeql/codeql-actions-config.yml
@@ -0,0 +1,2 @@
+paths:
+  - .github
diff --git a/.github/codeql/codeql-js-config.yml b/.github/codeql/codeql-js-config.yml
new file mode 100644
index 00000000000..6503a1fa80c
--- /dev/null
+++ b/.github/codeql/codeql-js-config.yml
@@ -0,0 +1,2 @@
+paths:
+  - doc
diff --git a/.github/dependabot.yml b/.github/dependabot.yml
new file mode 100644
index 00000000000..fc85287baa7
--- /dev/null
+++ b/.github/dependabot.yml
@@ -0,0 +1,26 @@
+version: 2
+enable-beta-ecosystems: true
+updates:
+  - package-ecosystem: "github-actions"
+    directory: "/"
+    schedule:
+      interval: "weekly"
+    commit-message:
+      prefix: "ci: github: "
+    labels: []
+    groups:
+      actions-deps:
+        patterns:
+          - "*"
+
+  - package-ecosystem: "uv"
+    directory: "/doc"
+    schedule:
+      interval: "weekly"
+    commit-message:
+      prefix: "ci: doc: "
+    labels: []
+    groups:
+      doc-deps:
+        patterns:
+          - "*"
diff --git a/.github/workflows/assigner.yml b/.github/workflows/assigner.yml
index be3696c4d30..3e5988fc698 100644
--- a/.github/workflows/assigner.yml
+++ b/.github/workflows/assigner.yml
@@ -15,23 +15,36 @@ on:
     types:
     - labeled
 
+permissions:
+  contents: read
+
 jobs:
   assignment:
     name: Pull Request Assignment
     if: github.event.pull_request.draft == false
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
+    permissions:
+      pull-requests: write # to add assignees to pull requests
+      issues: write        # to add assignees to issues
 
     steps:
-    - name: Install Python dependencies
-      run: |
-        pip install -U PyGithub>=1.55 west
-
     - name: Check out source code
-      uses: actions/checkout@v4
+      uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+
+    - name: Set up Python
+      uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
+      with:
+        python-version: 3.12
+        cache: pip
+        cache-dependency-path: scripts/requirements-actions.txt
+
+    - name: Install Python packages
+      run: |
+        pip install -r scripts/requirements-actions.txt --require-hashes
 
     - name: Run assignment script
       env:
-        GITHUB_TOKEN: ${{ secrets.ZB_GITHUB_TOKEN }}
+        GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
       run: |
         FLAGS="-v"
         FLAGS+=" -o ${{ github.event.repository.owner.login }}"
diff --git a/.github/workflows/backport.yml b/.github/workflows/backport.yml
index 5e28332c2a2..3ecf66b17da 100644
--- a/.github/workflows/backport.yml
+++ b/.github/workflows/backport.yml
@@ -7,10 +7,17 @@ on:
     branches:
       - main
 
+permissions:
+  contents: read
+
 jobs:
   backport:
     name: Backport
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
+    permissions:
+      contents: write       # to create/push backport branches
+      pull-requests: write  # to create backport PRs
+      issues: write         # to add labels to issue created if backport fails
     # Only react to merged PRs for security reasons.
     # See https://docs.github.com/en/actions/using-workflows/events-that-trigger-workflows#pull_request_target.
     if: >
@@ -24,8 +31,8 @@ jobs:
       )
     steps:
       - name: Backport
-        uses: zephyrproject-rtos/action-backport@v2.0.3-3
+        uses: zephyrproject-rtos/action-backport@7e74f601d11eaca577742445e87775b5651a965f # v2.0.3-3
         with:
-          github_token: ${{ secrets.ZB_GITHUB_TOKEN }}
+          github_token: ${{ secrets.GITHUB_TOKEN }}
           issue_labels: Backport
           labels_template: '["Backport"]'
diff --git a/.github/workflows/backport_issue_check.yml b/.github/workflows/backport_issue_check.yml
index 2d2c4fda6a8..a285113aad2 100644
--- a/.github/workflows/backport_issue_check.yml
+++ b/.github/workflows/backport_issue_check.yml
@@ -10,29 +10,41 @@ on:
     branches:
       - v*-branch
 
+permissions:
+  contents: read
+
 jobs:
   backport:
     name: Backport Issue Check
     concurrency:
       group: backport-issue-check-${{ github.ref }}
       cancel-in-progress: true
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     if: github.repository == 'zephyrproject-rtos/zephyr'
+    permissions:
+      issues: read # to check if associated issue exists for backport
 
     steps:
       - name: Check out source code
-        uses: actions/checkout@v4
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+
+      - name: Set up Python
+        uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
+        with:
+          python-version: 3.12
+          cache: pip
+          cache-dependency-path: scripts/requirements-actions.txt
 
-      - name: Install Python dependencies
+      - name: Install Python packages
         run: |
-          pip install -U pygithub
+          pip install -r scripts/requirements-actions.txt --require-hashes
 
       - name: Run backport issue checker
         env:
-          GITHUB_TOKEN: ${{ secrets.ZB_GITHUB_TOKEN }}
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
         run: |
           ./scripts/release/list_backports.py \
-            -o ${{ github.event.repository.owner.login }} \
-            -r ${{ github.event.repository.name }} \
-            -b ${{ github.event.pull_request.base.ref }} \
-            -p ${{ github.event.pull_request.number }}
+          -o ${{ github.event.repository.owner.login }} \
+          -r ${{ github.event.repository.name }} \
+          -b ${{ github.event.pull_request.base.ref }} \
+          -p ${{ github.event.pull_request.number }}
diff --git a/.github/workflows/bsim-tests-publish.yaml b/.github/workflows/bsim-tests-publish.yaml
index 72608b36b24..1cb30f2cfa9 100644
--- a/.github/workflows/bsim-tests-publish.yaml
+++ b/.github/workflows/bsim-tests-publish.yaml
@@ -5,20 +5,26 @@ on:
     workflows: ["BabbleSim Tests"]
     types:
       - completed
+
+permissions:
+  contents: read
+
 jobs:
   bsim-test-results:
     name: "Publish BabbleSim Test Results"
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     if: github.event.workflow_run.conclusion != 'skipped'
+    permissions:
+      checks: write # to create the check run entry with test results
 
     steps:
       - name: Download artifacts
-        uses: dawidd6/action-download-artifact@v6
+        uses: dawidd6/action-download-artifact@07ab29fd4a977ae4d2b275087cf67563dfdf0295 # v9
         with:
           run_id: ${{ github.event.workflow_run.id }}
 
       - name: Publish BabbleSim Test Results
-        uses: EnricoMi/publish-unit-test-result-action@v2
+        uses: EnricoMi/publish-unit-test-result-action@170bf24d20d201b842d7a52403b73ed297e6645b # v2.18.0
         with:
           check_name: BabbleSim Test Results
           comment_mode: off
diff --git a/.github/workflows/bsim-tests.yaml b/.github/workflows/bsim-tests.yaml
index 66d47c68a1c..951adc4d267 100644
--- a/.github/workflows/bsim-tests.yaml
+++ b/.github/workflows/bsim-tests.yaml
@@ -27,6 +27,10 @@ on:
       - "include/zephyr/net/ieee802154*"
       - "drivers/serial/*nrfx*"
       - "tests/drivers/uart/**"
+      - '!**.rst'
+
+permissions:
+  contents: read
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.event_name }}-${{ github.head_ref || github.ref }}
@@ -45,6 +49,9 @@ jobs:
       BSIM_OUT_PATH: /opt/bsim/
       BSIM_COMPONENTS_PATH: /opt/bsim/components
       EDTT_PATH: ../tools/edtt
+    permissions:
+      checks: write # to create the check run entry with test results
+
     steps:
       - name: Apply container owner mismatch workaround
         run: |
@@ -67,7 +74,7 @@ jobs:
           git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY}
 
       - name: Checkout
-        uses: actions/checkout@v4
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
         with:
           fetch-depth: 0
 
@@ -91,7 +98,7 @@ jobs:
           echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV
 
       - name: Check common triggering files
-        uses: tj-actions/changed-files@v45
+        uses: tj-actions/changed-files@823fcebdb31bb35fdf2229d9f769b400309430d0 # v46.0.3
         id: check-common-files
         with:
           files: |
@@ -110,16 +117,17 @@ jobs:
             modules/hal_nordic/**
 
       - name: Check if Bluethooth files changed
-        uses: tj-actions/changed-files@v45
+        uses: tj-actions/changed-files@823fcebdb31bb35fdf2229d9f769b400309430d0 # v46.0.3
         id: check-bluetooth-files
         with:
           files: |
-            tests/bsim/bluetooth/
             samples/bluetooth/
             subsys/bluetooth/
+            tests/bluetooth/common/testlib/
+            tests/bsim/bluetooth/
 
       - name: Check if Networking files changed
-        uses: tj-actions/changed-files@v45
+        uses: tj-actions/changed-files@823fcebdb31bb35fdf2229d9f769b400309430d0 # v46.0.3
         id: check-networking-files
         with:
           files: |
@@ -132,7 +140,7 @@ jobs:
             include/zephyr/net/ieee802154*
 
       - name: Check if UART files changed
-        uses: tj-actions/changed-files@v45
+        uses: tj-actions/changed-files@823fcebdb31bb35fdf2229d9f769b400309430d0 # v46.0.3
         id: check-uart-files
         with:
           files: |
@@ -172,13 +180,12 @@ jobs:
 
       - name: Merge Test Results
         run: |
-          pip install junitparser junit2html
           junitparser merge --glob "./bsim_*/*bsim_results.*.xml" "./twister-out/twister.xml" junit.xml
           junit2html junit.xml junit.html
 
       - name: Upload Unit Test Results in HTML
         if: always()
-        uses: actions/upload-artifact@v4
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: HTML Unit Test Results
           if-no-files-found: ignore
@@ -186,7 +193,7 @@ jobs:
             junit.html
 
       - name: Publish Unit Test Results
-        uses: EnricoMi/publish-unit-test-result-action@v2
+        uses: EnricoMi/publish-unit-test-result-action@170bf24d20d201b842d7a52403b73ed297e6645b # v2.18.0
         with:
           check_name: Bsim Test Results
           files: "junit.xml"
@@ -194,7 +201,7 @@ jobs:
 
       - name: Upload Event Details
         if: always()
-        uses: actions/upload-artifact@v4
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: event
           path: |
diff --git a/.github/workflows/bug_snapshot.yaml b/.github/workflows/bug_snapshot.yaml
index f10dc718b6e..e4cc5b7fdda 100644
--- a/.github/workflows/bug_snapshot.yaml
+++ b/.github/workflows/bug_snapshot.yaml
@@ -13,19 +13,30 @@ on:
   # Run daily at 14:05
   - cron: '5 14 * * *'
 
+permissions:
+  contents: read
+
 jobs:
   make_bugs_pickle:
     name: Make bugs pickle
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     if: github.repository_owner == 'zephyrproject-rtos'
 
     steps:
     - name: Checkout
-      uses: actions/checkout@v4
+      uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+
+    - name: Set up Python
+      uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
+      with:
+        python-version: 3.12
+        cache: pip
+        cache-dependency-path: scripts/requirements-actions.txt
 
-    - name: Install Python dependencies
+    - name: Install Python packages
       run: |
-        pip install -U pygithub
+        pip install -r scripts/requirements-actions.txt --require-hashes
+
 
     - name: Snapshot bugs
       env:
@@ -41,7 +52,7 @@ jobs:
         echo "BUGS_PICKLE_PATH=${BUGS_PICKLE_PATH}" >> ${GITHUB_ENV}
 
     - name: Configure AWS Credentials
-      uses: aws-actions/configure-aws-credentials@v4
+      uses: aws-actions/configure-aws-credentials@ececac1a45f3b08a01d2dd070d28d111c5fe6722 # v4.1.0
       with:
         aws-access-key-id: ${{ vars.AWS_BUILDS_ZEPHYR_BUG_SNAPSHOT_ACCESS_KEY_ID }}
         aws-secret-access-key: ${{ secrets.AWS_BUILDS_ZEPHYR_BUG_SNAPSHOT_SECRET_ACCESS_KEY }}
diff --git a/.github/workflows/clang.yaml b/.github/workflows/clang.yaml
index 11d249cd937..2e085c2bb36 100644
--- a/.github/workflows/clang.yaml
+++ b/.github/workflows/clang.yaml
@@ -1,6 +1,12 @@
 name: Build with Clang/LLVM
-
-on: pull_request_target
+on:
+  push:
+    branches:
+      - main
+      - v*-branch
+      - collab-*
+permissions:
+  contents: read
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.event_name }}-${{ github.head_ref || github.ref }}
@@ -17,16 +23,14 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
-        platform: ["native_sim"]
+        subset: [1, 2]
     env:
       CCACHE_DIR: /node-cache/ccache-zephyr
       CCACHE_REMOTE_STORAGE: "redis://cache-*.keydb-cache.svc.cluster.local|shards=1,2,3"
       CCACHE_REMOTE_ONLY: "true"
+      CCACHE_IGNOREOPTIONS: '-specs=* --specs=*'
       LLVM_TOOLCHAIN_PATH: /usr/lib/llvm-16
-      COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }}
       BASE_REF: ${{ github.base_ref }}
-    outputs:
-      report_needed: ${{ steps.twister.outputs.report_needed }}
     steps:
       - name: Apply container owner mismatch workaround
         run: |
@@ -49,9 +53,8 @@ jobs:
           git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY}
 
       - name: Checkout
-        uses: actions/checkout@v4
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
         with:
-          ref: ${{ github.event.pull_request.head.sha }}
           fetch-depth: 0
           persist-credentials: false
 
@@ -62,7 +65,6 @@ jobs:
           git config --global user.name "Zephyr Bot"
           rm -fr ".git/rebase-apply"
           rm -fr ".git/rebase-merge"
-          git rebase origin/${BASE_REF}
           git clean -f -d
           git log  --pretty=oneline | head -n 10
           west init -l . || true
@@ -107,18 +109,8 @@ jobs:
           export ZEPHYR_BASE=${PWD}
           export ZEPHYR_TOOLCHAIN_VARIANT=llvm
 
-          # check if we need to run a full twister or not based on files changed
-          python3 ./scripts/ci/test_plan.py --no-detailed-test-id --platform ${{ matrix.platform }} -c origin/${BASE_REF}..
-
-          # We can limit scope to just what has changed
-          if [ -s testplan.json ]; then
-            echo "report_needed=1" >> $GITHUB_OUTPUT
-            # Full twister but with options based on changes
-            ./scripts/twister --no-detailed-test-id --force-color --inline-logs -M -N -v --load-tests testplan.json --retry-failed 2
-          else
-            # if nothing is run, skip reporting step
-            echo "report_needed=0" >> $GITHUB_OUTPUT
-          fi
+          ./scripts/twister -p native_sim --no-detailed-test-id --force-color --inline-logs -M -N -v --retry-failed 2 \
+            -T tests --subset ${{matrix.subset}}/2 -j 16
 
       - name: Print ccache stats
         if: always()
@@ -126,31 +118,53 @@ jobs:
           ccache -s -vv
 
       - name: Upload Unit Test Results
-        if: always() && steps.twister.outputs.report_needed != 0
-        uses: actions/upload-artifact@v4
+        if: always()
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
-          name: Unit Test Results (Subset ${{ matrix.platform }})
-          path: twister-out/twister.xml
+          name: Unit Test Results (Subset ${{ matrix.subset }})
+          path: |
+            twister-out/twister.xml
+            twister-out/twister.json
+          if-no-files-found: ignore
 
   clang-build-results:
     name: "Publish Unit Tests Results"
     needs: clang-build
-    runs-on: ubuntu-22.04
-    if: (success() || failure() ) && needs.clang-build.outputs.report_needed != 0
+    runs-on: ubuntu-24.04
+    permissions:
+      checks: write # to create GitHub annotations
+    if: (success() || failure())
     steps:
+      - name: Checkout
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          fetch-depth: 0
+          persist-credentials: false
+
       - name: Download Artifacts
-        uses: actions/download-artifact@v4
+        uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1
         with:
           path: artifacts
+
+      - name: Set up Python
+        uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
+        with:
+          python-version: 3.12
+          cache: pip
+          cache-dependency-path: scripts/requirements-actions.txt
+
+      - name: Install Python packages
+        run: |
+          pip install -r scripts/requirements-actions.txt --require-hashes
+
       - name: Merge Test Results
         run: |
-          pip install junitparser junit2html
           junitparser merge artifacts/*/twister.xml junit.xml
           junit2html junit.xml junit-clang.html
 
       - name: Upload Unit Test Results in HTML
         if: always()
-        uses: actions/upload-artifact@v4
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: HTML Unit Test Results
           if-no-files-found: ignore
@@ -158,7 +172,7 @@ jobs:
             junit-clang.html
 
       - name: Publish Unit Test Results
-        uses: EnricoMi/publish-unit-test-result-action@v2
+        uses: EnricoMi/publish-unit-test-result-action@170bf24d20d201b842d7a52403b73ed297e6645b # v2.18.0
         if: always()
         with:
           check_name: Unit Test Results
diff --git a/.github/workflows/codecov.yaml b/.github/workflows/codecov.yaml
index d03ced6e474..74ca259c91f 100644
--- a/.github/workflows/codecov.yaml
+++ b/.github/workflows/codecov.yaml
@@ -4,6 +4,9 @@ on:
   schedule:
     - cron: '25 06,18 * * *'
 
+permissions:
+  contents: read
+
 concurrency:
   group: ${{ github.workflow }}-${{ github.event_name }}-${{ github.head_ref || github.ref }}
   cancel-in-progress: true
@@ -61,10 +64,21 @@ jobs:
           git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY}
 
       - name: checkout
-        uses: actions/checkout@v4
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
         with:
           fetch-depth: 0
 
+      - name: Set up Python
+        uses: actions/setup-python@42375524e23c412d93fb67b49958b491fce71c38 # v5.4.0
+        with:
+          python-version: 3.12
+          cache: pip
+          cache-dependency-path: scripts/requirements-actions.txt
+
+      - name: Install Python packages
+        run: |
+          pip install -r scripts/requirements-actions.txt --require-hashes
+
       - name: west setup
         run: |
           west init -l . || true
@@ -85,24 +99,13 @@ jobs:
           ccache -p
           ccache -z -s -vv
 
-      - name: Update BabbleSim to manifest revision
-        run: |
-          export BSIM_VERSION=$( west list bsim -f {revision} )
-          echo "Manifest points to bsim sha $BSIM_VERSION"
-          cd /opt/bsim_west/bsim
-          git fetch -n origin ${BSIM_VERSION}
-          git -c advice.detachedHead=false checkout ${BSIM_VERSION}
-          west update
-          make everything -s -j 8
-
       - name: Run Tests with Twister (Push)
         continue-on-error: true
         run: |
           export ZEPHYR_BASE=${PWD}
           export ZEPHYR_TOOLCHAIN_VARIANT=zephyr
           mkdir -p coverage/reports
-          pip install gcovr==6.0
-          ./scripts/twister -E ${{matrix.normalized}}-testplan.json
+          ./scripts/twister --save-tests ${{matrix.normalized}}-testplan.json
           ls -la
           ./scripts/twister \
             -i --force-color -N -v --filter runnable -p ${{ matrix.platform }} --coverage \
@@ -121,7 +124,7 @@ jobs:
 
       - name: Upload Coverage Results
         if: always()
-        uses: actions/upload-artifact@v4
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: Coverage Data (Subset ${{ matrix.normalized }})
           path: |
@@ -131,18 +134,29 @@ jobs:
   codecov-results:
     name: "Publish Coverage Results"
     needs: codecov
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     # the codecov job might be skipped, we don't need to run this job then
     if: success() || failure()
 
     steps:
       - name: checkout
-        uses: actions/checkout@v4
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
         with:
           fetch-depth: 0
 
+      - name: Set up Python
+        uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
+        with:
+          python-version: 3.12
+          cache: pip
+          cache-dependency-path: scripts/requirements-actions.txt
+
+      - name: Install Python packages
+        run: |
+          pip install -r scripts/requirements-actions.txt --require-hashes
+
       - name: Download Artifacts
-        uses: actions/download-artifact@v4
+        uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1
         with:
           path: coverage/reports
 
@@ -182,7 +196,6 @@ jobs:
       - name: Merge coverage files
         run: |
           pushd ./coverage/reports
-          pip install gcovr==6.0
           gcovr ${{ steps.get-coverage-files.outputs.mergefiles }}  --merge-mode-functions=separate --json merged.json
           gcovr ${{ steps.get-coverage-files.outputs.mergefiles }} --merge-mode-functions=separate --cobertura merged.xml
           popd
@@ -198,7 +211,6 @@ jobs:
       - name: Generate Coverage Report
         if: always()
         run: |
-          pip install xlsxwriter ijson
           python3 ./scripts/ci/coverage/coverage_analysis.py \
             -t native_sim-testplan.json \
             -m MAINTAINERS.yml \
@@ -209,7 +221,7 @@ jobs:
 
       - name: Upload Merged Coverage Results and Report
         if: always()
-        uses: actions/upload-artifact@v4
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: Coverage Data and report
           path: |
@@ -220,7 +232,7 @@ jobs:
 
       - name: Upload coverage to Codecov
         if: always()
-        uses: codecov/codecov-action@v4
+        uses: codecov/codecov-action@0565863a31f2c772f9f0395002a31e3f06189574 # v5.4.0
         with:
           env_vars: OS,PYTHON
           fail_ci_if_error: false
diff --git a/.github/workflows/codeql.yml b/.github/workflows/codeql.yml
new file mode 100644
index 00000000000..f9295f68cd7
--- /dev/null
+++ b/.github/workflows/codeql.yml
@@ -0,0 +1,58 @@
+name: "CodeQL"
+
+on:
+  push:
+    branches:
+      - main
+      - v*-branch
+      - collab-*
+  schedule:
+    - cron: '34 16 * * 3'
+  pull_request:
+    branches:
+      - main
+      - v*-branch
+      - collab-*
+
+permissions:
+  contents: read
+jobs:
+  analyze:
+    name: Analyze (${{ matrix.language }})
+    runs-on: ubuntu-24.04
+    permissions:
+      security-events: write
+    strategy:
+      fail-fast: false
+      matrix:
+        include:
+          - language: python
+            build-mode: none
+          - language: actions
+            build-mode: none
+            config: ./.github/codeql/codeql-actions-config.yml
+          - language: javascript-typescript
+            build-mode: none
+            config: ./.github/codeql/codeql-js-config.yml
+    steps:
+      - name: Checkout
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+
+      - name: Initialize CodeQL
+        uses: github/codeql-action/init@1b549b9259bda1cb5ddde3b41741a82a2d15a841 # v3.28.13
+        with:
+          languages: ${{ matrix.language }}
+          build-mode: ${{ matrix.build-mode }}
+          queries: security-extended
+          config-file: ${{ matrix.config }}
+
+      - if: matrix.build-mode == 'manual'
+        shell: bash
+        run: |
+          echo "nothing yet"
+          exit 0
+
+      - name: Perform CodeQL Analysis
+        uses: github/codeql-action/analyze@1b549b9259bda1cb5ddde3b41741a82a2d15a841 # v3.28.13
+        with:
+          category: "/language:${{matrix.language}}"
diff --git a/.github/workflows/coding_guidelines.yml b/.github/workflows/coding_guidelines.yml
index 9ab2bc974b1..cf3d7182f18 100644
--- a/.github/workflows/coding_guidelines.yml
+++ b/.github/workflows/coding_guidelines.yml
@@ -2,34 +2,37 @@ name: Coding Guidelines
 
 on: pull_request
 
+permissions:
+  contents: read
+
 jobs:
   compliance_job:
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     name: Run coding guidelines checks on patch series (PR)
     steps:
     - name: Checkout the code
-      uses: actions/checkout@v4
+      uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
       with:
         ref: ${{ github.event.pull_request.head.sha }}
         fetch-depth: 0
 
-    - name: cache-pip
-      uses: actions/cache@v4
+    - name: Set up Python
+      uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
       with:
-        path: ~/.cache/pip
-        key: ${{ runner.os }}-pip-${{ hashFiles('.github/workflows/coding_guidelines.yml') }}
+        python-version: 3.12
+        cache: pip
+        cache-dependency-path: scripts/requirements-actions.txt
 
-    - name: Install python dependencies
+    - name: Install Python packages
       run: |
-        pip install unidiff
-        pip install sh
+        pip install -r scripts/requirements-actions.txt --require-hashes
 
     - name: Install Packages
       run: |
         sudo apt-get update
         sudo apt-get install coccinelle
 
-    - name: Run Coding Guildeines Checks
+    - name: Run Coding Guidelines Checks
       continue-on-error: true
       id: coding_guidelines
       env:
diff --git a/.github/workflows/compliance.yml b/.github/workflows/compliance.yml
index 56927365550..0b80da96965 100644
--- a/.github/workflows/compliance.yml
+++ b/.github/workflows/compliance.yml
@@ -8,9 +8,12 @@ on:
     - reopened
     - synchronize
 
+permissions:
+  contents: read
+
 jobs:
   check_compliance:
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     name: Run compliance checks on patch series (PR)
     steps:
     - name: Update PATH for west
@@ -18,7 +21,7 @@ jobs:
         echo "$HOME/.local/bin" >> $GITHUB_PATH
 
     - name: Checkout the code
-      uses: actions/checkout@v4
+      uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
       with:
         ref: ${{ github.event.pull_request.head.sha }}
         fetch-depth: 0
@@ -41,20 +44,15 @@ jobs:
         git log  --pretty=oneline | head -n 10
 
     - name: Set up Python
-      uses: actions/setup-python@v5
-      with:
-        python-version: 3.11
-
-    - name: cache-pip
-      uses: actions/cache@v4
+      uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
       with:
-        path: ~/.cache/pip
-        key: ${{ runner.os }}-pip-${{ hashFiles('.github/workflows/compliance.yml') }}
+        python-version: 3.12
+        cache: pip
+        cache-dependency-path: scripts/requirements-actions.txt
 
-    - name: Install python dependencies
+    - name: Install Python packages
       run: |
-        pip install -r scripts/requirements-compliance.txt
-        pip install west
+        pip install -r scripts/requirements-actions.txt --require-hashes
 
     - name: west setup
       run: |
@@ -62,14 +60,6 @@ jobs:
         west config manifest.group-filter -- +ci,-optional
         west update -o=--depth=1 -n 2>&1 1> west.update.log || west update -o=--depth=1 -n 2>&1 1> west.update2.log
 
-    - name: Check for PR description
-      if: ${{ github.event.pull_request.body == '' }}
-      continue-on-error: true
-      id: pr_description
-      run: |
-        echo "Pull request description cannot be empty."
-        exit 1
-
     - name: Run Compliance Tests
       continue-on-error: true
       id: compliance
@@ -82,11 +72,11 @@ jobs:
         git log  --pretty=oneline | head -n 10
         # Increase rename limit to allow for large PRs
         git config diff.renameLimit 10000
-        ./scripts/ci/check_compliance.py --annotate -e KconfigBasic -e ClangFormat \
+        ./scripts/ci/check_compliance.py --annotate -e KconfigBasic -e SysbuildKconfigBasic -e ClangFormat \
         -e Kconfig -e KconfigBasicNoModules -e ModulesMaintainers -c origin/${BASE_REF}..
 
     - name: upload-results
-      uses: actions/upload-artifact@v4
+      uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
       continue-on-error: true
       with:
         name: compliance.xml
diff --git a/.github/workflows/daily_test_version.yml b/.github/workflows/daily_test_version.yml
index 3a43ac64300..02eef3c776f 100644
--- a/.github/workflows/daily_test_version.yml
+++ b/.github/workflows/daily_test_version.yml
@@ -10,28 +10,38 @@ on:
     branches:
     - refs/tags/*
 
+permissions:
+  contents: read
+
 jobs:
   get_version:
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     if: github.repository == 'zephyrproject-rtos/zephyr'
 
     steps:
     - name: Configure AWS Credentials
-      uses: aws-actions/configure-aws-credentials@v4
+      uses: aws-actions/configure-aws-credentials@ececac1a45f3b08a01d2dd070d28d111c5fe6722 # v4.1.0
       with:
         aws-access-key-id: ${{ vars.AWS_TESTING_ACCESS_KEY_ID }}
         aws-secret-access-key: ${{ secrets.AWS_TESTING_SECRET_ACCESS_KEY }}
         aws-region: us-east-1
 
-    - name: install-pip
-      run: |
-        pip install gitpython
-
     - name: checkout
-      uses: actions/checkout@v4
+      uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
       with:
         fetch-depth: 0
 
+    - name: Set up Python
+      uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
+      with:
+        python-version: 3.12
+        cache: pip
+        cache-dependency-path: scripts/requirements-actions.txt
+
+    - name: Install Python packages
+      run: |
+        pip install -r scripts/requirements-actions.txt --require-hashes
+
     - name: Upload to AWS S3
       run: |
         python3 scripts/ci/version_mgr.py --update .
diff --git a/.github/workflows/devicetree_checks.yml b/.github/workflows/devicetree_checks.yml
index 345eb5b7db0..00a498bbc45 100644
--- a/.github/workflows/devicetree_checks.yml
+++ b/.github/workflows/devicetree_checks.yml
@@ -20,6 +20,9 @@ on:
     - 'scripts/dts/**'
     - '.github/workflows/devicetree_checks.yml'
 
+permissions:
+  contents: read
+
 jobs:
   devicetree-checks:
     name: Devicetree script tests
@@ -30,39 +33,19 @@ jobs:
         os: [ubuntu-22.04, macos-14, windows-2022]
     steps:
     - name: checkout
-      uses: actions/checkout@v4
+      uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+
     - name: Set up Python ${{ matrix.python-version }}
-      uses: actions/setup-python@v5
+      uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
       with:
         python-version: ${{ matrix.python-version }}
-    - name: cache-pip-linux
-      if: startsWith(runner.os, 'Linux')
-      uses: actions/cache@v4
-      with:
-        path: ~/.cache/pip
-        key: ${{ runner.os }}-pip-${{ matrix.python-version }}
-        restore-keys: |
-          ${{ runner.os }}-pip-${{ matrix.python-version }}
-    - name: cache-pip-mac
-      if: startsWith(runner.os, 'macOS')
-      uses: actions/cache@v4
-      with:
-        path: ~/Library/Caches/pip
-        # Trailing '-' was just to get a different cache name
-        key: ${{ runner.os }}-pip-${{ matrix.python-version }}-
-        restore-keys: |
-          ${{ runner.os }}-pip-${{ matrix.python-version }}-
-    - name: cache-pip-win
-      if: startsWith(runner.os, 'Windows')
-      uses: actions/cache@v4
-      with:
-        path: ~\AppData\Local\pip\Cache
-        key: ${{ runner.os }}-pip-${{ matrix.python-version }}
-        restore-keys: |
-          ${{ runner.os }}-pip-${{ matrix.python-version }}
-    - name: install python dependencies
+        cache: pip
+        cache-dependency-path: scripts/requirements-actions.txt
+
+    - name: Install Python packages
       run: |
-        pip install pytest pyyaml tox
+        pip install -r scripts/requirements-actions.txt --require-hashes
+
     - name: run tox
       working-directory: scripts/dts/python-devicetree
       run: |
diff --git a/.github/workflows/do_not_merge.yml b/.github/workflows/do_not_merge.yml
deleted file mode 100644
index b2bbefdc6fe..00000000000
--- a/.github/workflows/do_not_merge.yml
+++ /dev/null
@@ -1,20 +0,0 @@
-name: Do Not Merge
-
-on:
-  pull_request:
-    types: [synchronize, opened, reopened, labeled, unlabeled]
-
-jobs:
-  do-not-merge:
-    name: Prevent Merging
-    runs-on: ubuntu-22.04
-    steps:
-      - name: Check for label
-        if: ${{ contains(github.event.*.labels.*.name, 'DNM') ||
-                contains(github.event.*.labels.*.name, 'TSC') ||
-                contains(github.event.*.labels.*.name, 'Architecture Review') ||
-                contains(github.event.*.labels.*.name, 'dev-review') }}
-        run: |
-          echo "Pull request is labeled as 'DNM', 'TSC', 'Architecture Review' or 'dev-review'."
-          echo "This workflow fails so that the pull request cannot be merged."
-          exit 1
diff --git a/.github/workflows/doc-build.yml b/.github/workflows/doc-build.yml
index 69c7b787c45..144f872e5f5 100644
--- a/.github/workflows/doc-build.yml
+++ b/.github/workflows/doc-build.yml
@@ -11,33 +11,28 @@ on:
     - v*
   pull_request:
 
+permissions:
+  contents: read
+
 env:
-  # NOTE: west docstrings will be extracted from the version listed here
-  WEST_VERSION: 1.2.0
-  # The latest CMake available directly with apt is 3.18, but we need >=3.20
-  # so we fetch that through pip.
-  CMAKE_VERSION: 3.20.5
   DOXYGEN_VERSION: 1.12.0
-  # Job count is set to 2 less than the vCPU count of 16 because the total available RAM is 32GiB
-  # and each sphinx-build process may use more than 2GiB of RAM.
-  JOB_COUNT: 14
+  DOXYGEN_MD5SUM: fd96a5defa535dfe2e987b46540844a4
+  JOB_COUNT: 4
 
 jobs:
   doc-file-check:
     name: Check for doc changes
-    runs-on: ubuntu-22.04
-    if: >
-      github.repository_owner == 'zephyrproject-rtos'
+    runs-on: ubuntu-24.04
     outputs:
       file_check: ${{ steps.check-doc-files.outputs.any_modified }}
     steps:
     - name: checkout
-      uses: actions/checkout@v4
+      uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
       with:
         ref: ${{ github.event.pull_request.head.sha }}
         fetch-depth: 0
     - name: Check if Documentation related files changed
-      uses: tj-actions/changed-files@v45
+      uses: tj-actions/changed-files@823fcebdb31bb35fdf2229d9f769b400309430d0 # v46.0.3
       id: check-doc-files
       with:
         files: |
@@ -48,7 +43,6 @@ jobs:
           kernel/include/kernel_arch_interface.h
           lib/libc/**
           subsys/testsuite/ztest/include/**
-          tests/
           **/Kconfig*
           west.yml
           scripts/dts/
@@ -61,9 +55,8 @@ jobs:
     name: "Documentation Build (HTML)"
     needs: [doc-file-check]
     if: >
-      github.repository_owner == 'zephyrproject-rtos' &&
-        ( needs.doc-file-check.outputs.file_check == 'true' || github.event_name != 'pull_request' )
-    runs-on: ubuntu-22.04
+      needs.doc-file-check.outputs.file_check == 'true' || github.event_name != 'pull_request'
+    runs-on: ubuntu-24.04
     timeout-minutes: 90
     concurrency:
       group: doc-build-html-${{ github.ref }}
@@ -75,15 +68,21 @@ jobs:
         sudo apt-get update
         sudo apt-get install -y wget python3-pip git ninja-build graphviz lcov
         wget --no-verbose "https://github.com/doxygen/doxygen/releases/download/Release_${DOXYGEN_VERSION//./_}/doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz"
+        echo "${DOXYGEN_MD5SUM}  doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz" | md5sum -c
+        if [ $? -ne 0 ]; then
+          echo "Failed to verify doxygen tarball"
+          exit 1
+        fi
         sudo tar xf doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz -C /opt
         echo "/opt/doxygen-${DOXYGEN_VERSION}/bin" >> $GITHUB_PATH
         echo "${HOME}/.local/bin" >> $GITHUB_PATH
 
     - name: checkout
-      uses: actions/checkout@v4
+      uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
       with:
         ref: ${{ github.event.pull_request.head.sha }}
         fetch-depth: 0
+        path: zephyr
 
     - name: Rebase
       if: github.event_name == 'pull_request'
@@ -91,6 +90,7 @@ jobs:
       env:
         BASE_REF: ${{ github.base_ref }}
         PR_HEAD: ${{ github.event.pull_request.head.sha }}
+      working-directory: zephyr
       run: |
         git config --global user.email "actions@zephyrproject.org"
         git config --global user.name "Github Actions"
@@ -100,25 +100,27 @@ jobs:
         git clean -f -d
         git log --graph --oneline HEAD...${PR_HEAD}
 
-    - name: cache-pip
-      uses: actions/cache@v4
+    - name: Set up Python
+      uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
       with:
-        path: ~/.cache/pip
-        key: pip-${{ hashFiles('doc/requirements.txt') }}
+        python-version: 3.12
+        cache: pip
+        cache-dependency-path: doc/requirements.txt
 
-    - name: install-pip
-      run: |
-        pip install -r doc/requirements.txt
-        pip install west==${WEST_VERSION}
-        pip install cmake==${CMAKE_VERSION}
-        pip install coverxygen
+    - name: Setup Zephyr project
+      uses: zephyrproject-rtos/action-zephyr-setup@f7b70269a8eb01f70c8e710891e4c94972a2f6b4 # v1.0.6
+      with:
+        app-path: zephyr
+        toolchains: 'all'
 
-    - name: west setup
+    - name: install-pip
+      working-directory: zephyr
       run: |
-        west init -l .
+        pip install -r doc/requirements.txt --require-hashes
 
     - name: build-docs
       shell: bash
+      working-directory: zephyr
       run: |
         if [[ "$GITHUB_REF" =~ "refs/tags/v" ]]; then
           DOC_TAG="release"
@@ -144,22 +146,23 @@ jobs:
         genhtml --no-function-coverage --no-branch-coverage new.info -o coverage-report
 
     - name: compress-docs
+      working-directory: zephyr
       run: |
-        tar --use-compress-program="xz -T0" -cf html-output.tar.xz --directory=doc/_build html
+        tar --use-compress-program="xz -T0" -cf html-output.tar.xz --exclude html/_sources --exclude html/doxygen/xml --directory=doc/_build html
         tar --use-compress-program="xz -T0" -cf api-output.tar.xz --directory=doc/_build html/doxygen/html
         tar --use-compress-program="xz -T0" -cf api-coverage.tar.xz coverage-report
 
     - name: upload-build
-      uses: actions/upload-artifact@v4
+      uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
       with:
         name: html-output
-        path: html-output.tar.xz
+        path: zephyr/html-output.tar.xz
 
     - name: upload-api-coverage
-      uses: actions/upload-artifact@v4
+      uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
       with:
         name: api-coverage
-        path: api-coverage.tar.xz
+        path: zephyr/api-coverage.tar.xz
 
     - name: process-pr
       if: github.event_name == 'pull_request'
@@ -176,7 +179,7 @@ jobs:
         echo "API Coverage Report will be available shortly at: ${API_COVERAGE_URL}" >> $GITHUB_STEP_SUMMARY
 
     - name: upload-pr-number
-      uses: actions/upload-artifact@v4
+      uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
       if: github.event_name == 'pull_request'
       with:
         name: pr_num
@@ -186,52 +189,56 @@ jobs:
     name: "Documentation Build (PDF)"
     needs: [doc-file-check]
     if: |
-      github.event_name != 'pull_request' &&
-      github.repository_owner == 'zephyrproject-rtos'
-    runs-on: ubuntu-22.04
-    container: texlive/texlive:latest
+      github.event_name != 'pull_request'
+    runs-on: ubuntu-24.04
     timeout-minutes: 120
     concurrency:
       group: doc-build-pdf-${{ github.ref }}
       cancel-in-progress: true
 
     steps:
-    - name: Apply container owner mismatch workaround
-      run: |
-        git config --global --add safe.directory ${GITHUB_WORKSPACE}
-
     - name: checkout
-      uses: actions/checkout@v4
-
-    - name: install-pkgs
-      run: |
-        apt-get update
-        apt-get install -y python3-pip python3-venv ninja-build doxygen graphviz librsvg2-bin imagemagick
+      uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+      with:
+        path: zephyr
 
-    - name: cache-pip
-      uses: actions/cache@v4
+    - name: Set up Python
+      uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
       with:
-        path: ~/.cache/pip
-        key: pip-${{ hashFiles('doc/requirements.txt') }}
+        python-version: 3.12
+        cache: pip
+        cache-dependency-path: doc/requirements.txt
 
-    - name: setup-venv
+    - name: install-pkgs
       run: |
-        python3 -m venv .venv
-        . .venv/bin/activate
-        echo PATH=$PATH >> $GITHUB_ENV
+        sudo apt-get update
+        sudo apt-get install --no-install-recommends graphviz librsvg2-bin \
+          texlive-latex-base texlive-latex-extra latexmk \
+          texlive-fonts-recommended texlive-fonts-extra texlive-xetex \
+          imagemagick fonts-noto xindy
+        wget --no-verbose "https://github.com/doxygen/doxygen/releases/download/Release_${DOXYGEN_VERSION//./_}/doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz"
+        echo "${DOXYGEN_MD5SUM}  doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz" | md5sum -c
+        if [ $? -ne 0 ]; then
+          echo "Failed to verify doxygen tarball"
+          exit 1
+        fi
+        sudo tar xf doxygen-${DOXYGEN_VERSION}.linux.bin.tar.gz -C /opt
+        echo "/opt/doxygen-${DOXYGEN_VERSION}/bin" >> $GITHUB_PATH
 
-    - name: install-pip
-      run: |
-        pip install -r doc/requirements.txt
-        pip install west==${WEST_VERSION}
-        pip install cmake==${CMAKE_VERSION}
+    - name: Setup Zephyr project
+      uses: zephyrproject-rtos/action-zephyr-setup@f7b70269a8eb01f70c8e710891e4c94972a2f6b4 # v1.0.6
+      with:
+        app-path: zephyr
+        toolchains: 'arm-zephyr-eabi'
 
-    - name: west setup
+    - name: install-pip-pkgs
+      working-directory: zephyr
       run: |
-        west init -l .
+        pip install -r doc/requirements.txt --require-hashes
 
     - name: build-docs
       shell: bash
+      working-directory: zephyr
       continue-on-error: true
       run: |
         if [[ "$GITHUB_REF" =~ "refs/tags/v" ]]; then
@@ -247,13 +254,13 @@ jobs:
 
     - name: upload-build
       if: always()
-      uses: actions/upload-artifact@v4
+      uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
       with:
         name: pdf-output
         if-no-files-found: ignore
         path: |
-          doc/_build/latex/zephyr.pdf
-          doc/_build/latex/zephyr.log
+          zephyr/doc/_build/latex/zephyr.pdf
+          zephyr/doc/_build/latex/zephyr.log
 
   doc-build-status-check:
     if: always()
diff --git a/.github/workflows/doc-publish-pr.yml b/.github/workflows/doc-publish-pr.yml
index 786bd14aed2..54ac20d6ad4 100644
--- a/.github/workflows/doc-publish-pr.yml
+++ b/.github/workflows/doc-publish-pr.yml
@@ -10,10 +10,13 @@ on:
     types:
     - completed
 
+permissions:
+  contents: read
+
 jobs:
   doc-publish:
     name: Publish Documentation
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     if: |
       github.event.workflow_run.event == 'pull_request' &&
       github.event.workflow_run.conclusion == 'success' &&
@@ -22,7 +25,7 @@ jobs:
     steps:
     - name: Download artifacts
       id: download-artifacts
-      uses: dawidd6/action-download-artifact@v6
+      uses: dawidd6/action-download-artifact@07ab29fd4a977ae4d2b275087cf67563dfdf0295 # v9
       with:
         workflow: doc-build.yml
         run_id: ${{ github.event.workflow_run.id }}
@@ -30,7 +33,7 @@ jobs:
 
     - name: Load PR number
       if: steps.download-artifacts.outputs.found_artifact == 'true'
-      uses: actions/github-script@v7
+      uses: actions/github-script@60a0d83039c74a4aee543508d2ffcb1c3799cdea # v7.0.1
       with:
         script: |
           let fs = require("fs");
@@ -40,7 +43,7 @@ jobs:
     - name: Check PR number
       if: steps.download-artifacts.outputs.found_artifact == 'true'
       id: check-pr
-      uses: carpentries/actions/check-valid-pr@v0.14.0
+      uses: carpentries/actions/check-valid-pr@e27aa6c531dadd357d2aa4c9a21e90849e23e963 # v0.14.0
       with:
         pr: ${{ env.PR_NUM }}
         sha: ${{ github.event.workflow_run.head_sha }}
@@ -63,7 +66,7 @@ jobs:
 
     - name: Configure AWS Credentials
       if: steps.download-artifacts.outputs.found_artifact == 'true'
-      uses: aws-actions/configure-aws-credentials@v4
+      uses: aws-actions/configure-aws-credentials@ececac1a45f3b08a01d2dd070d28d111c5fe6722 # v4.1.0
       with:
         aws-access-key-id: ${{ vars.AWS_BUILDS_ZEPHYR_PR_ACCESS_KEY_ID }}
         aws-secret-access-key: ${{ secrets.AWS_BUILDS_ZEPHYR_PR_SECRET_ACCESS_KEY }}
diff --git a/.github/workflows/doc-publish.yml b/.github/workflows/doc-publish.yml
index 51c451c75ea..89afeb4ed1b 100644
--- a/.github/workflows/doc-publish.yml
+++ b/.github/workflows/doc-publish.yml
@@ -13,10 +13,13 @@ on:
     types:
     - completed
 
+permissions:
+  contents: read
+
 jobs:
   doc-publish:
     name: Publish Documentation
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     if: |
       github.event.workflow_run.event != 'pull_request' &&
       github.event.workflow_run.conclusion == 'success' &&
@@ -24,7 +27,7 @@ jobs:
 
     steps:
     - name: Download artifacts
-      uses: dawidd6/action-download-artifact@v6
+      uses: dawidd6/action-download-artifact@07ab29fd4a977ae4d2b275087cf67563dfdf0295 # v9
       with:
         workflow: doc-build.yml
         run_id: ${{ github.event.workflow_run.id }}
@@ -37,7 +40,7 @@ jobs:
         fi
 
     - name: Configure AWS Credentials
-      uses: aws-actions/configure-aws-credentials@v4
+      uses: aws-actions/configure-aws-credentials@ececac1a45f3b08a01d2dd070d28d111c5fe6722 # v4.1.0
       with:
         aws-access-key-id: ${{ vars.AWS_DOCS_ACCESS_KEY_ID }}
         aws-secret-access-key: ${{ secrets.AWS_DOCS_SECRET_ACCESS_KEY }}
diff --git a/.github/workflows/errno.yml b/.github/workflows/errno.yml
index d3fe1b0dcae..a035936216f 100644
--- a/.github/workflows/errno.yml
+++ b/.github/workflows/errno.yml
@@ -6,9 +6,12 @@ on:
       - 'lib/libc/minimal/include/errno.h'
       - 'scripts/ci/errno.py'
 
+permissions:
+  contents: read
+
 jobs:
   check-errno:
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     container:
       image: ghcr.io/zephyrproject-rtos/ci:v0.27.4
 
@@ -22,7 +25,7 @@ jobs:
           git config --global --add safe.directory ${GITHUB_WORKSPACE}
 
       - name: checkout
-        uses: actions/checkout@v4
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
 
       - name: Environment Setup
         run: |
diff --git a/.github/workflows/footprint-tracking.yml b/.github/workflows/footprint-tracking.yml
index 78f761cb545..c974b0ded25 100644
--- a/.github/workflows/footprint-tracking.yml
+++ b/.github/workflows/footprint-tracking.yml
@@ -16,6 +16,9 @@ on:
       # same commit
       - 'v*'
 
+permissions:
+  contents: read
+
 concurrency:
   group: ${{ github.workflow }}-${{ github.event_name }}-${{ github.head_ref || github.ref }}
   cancel-in-progress: true
@@ -58,14 +61,24 @@ jobs:
         run: |
           sudo apt-get update
           sudo apt-get install -y python3-venv
-          pip install -U gitpython
 
       - name: checkout
-        uses: actions/checkout@v4
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
         with:
           ref: ${{ github.event.pull_request.head.sha }}
           fetch-depth: 0
 
+      - name: Set up Python
+        uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
+        with:
+          python-version: 3.12
+          cache: pip
+          cache-dependency-path: scripts/requirements-actions.txt
+
+      - name: Install Python packages
+        run: |
+            pip install -r scripts/requirements-actions.txt --require-hashes
+
       - name: Environment Setup
         run: |
           echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV
@@ -77,7 +90,7 @@ jobs:
           west update 2>&1 1> west.update.log || west update 2>&1 1> west.update2.log
 
       - name: Configure AWS Credentials
-        uses: aws-actions/configure-aws-credentials@v4
+        uses: aws-actions/configure-aws-credentials@ececac1a45f3b08a01d2dd070d28d111c5fe6722 # v4.1.0
         with:
           aws-access-key-id: ${{ vars.AWS_TESTING_ACCESS_KEY_ID }}
           aws-secret-access-key: ${{ secrets.AWS_TESTING_SECRET_ACCESS_KEY }}
@@ -94,7 +107,6 @@ jobs:
         run: |
           python3 -m venv .venv
           . .venv/bin/activate
-          pip install awscli
           aws s3 sync  --quiet footprint_data/ s3://testing.zephyrproject.org/footprint_data/
 
       - name: Transform Footprint data to Twister JSON reports
@@ -113,7 +125,6 @@ jobs:
           ELASTICSEARCH_INDEX: ${{ vars.FOOTPRINT_TRACKING_INDEX }}
         run: |
           shopt -s globstar
-          pip install -U elasticsearch
           run_date=`date --iso-8601=minutes`
           python3 ./scripts/ci/upload_test_results_es.py -r ${run_date} \
             --flatten footprint \
diff --git a/.github/workflows/greet_first_time_contributor.yml b/.github/workflows/greet_first_time_contributor.yml
index 5f62c03d6de..ae69fd5cc01 100644
--- a/.github/workflows/greet_first_time_contributor.yml
+++ b/.github/workflows/greet_first_time_contributor.yml
@@ -6,14 +6,20 @@ on:
   pull_request_target:
     types: [opened, closed]
 
+permissions:
+  contents: read
+
 jobs:
   check_for_first_interaction:
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     if: github.repository == 'zephyrproject-rtos/zephyr'
+    permissions:
+      pull-requests: write # to comment on pull requests
+      issues: write        # to comment on issues
 
     steps:
-      - uses: actions/checkout@v4
-      - uses: zephyrproject-rtos/action-first-interaction@v1.1.1-zephyr-5
+      - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+      - uses: zephyrproject-rtos/action-first-interaction@58853996b1ac504b8e0f6964301f369d2bb22e5c # v1.1.1+zephyr.6
         with:
           repo-token: ${{ secrets.GITHUB_TOKEN }}
 
diff --git a/.github/workflows/hello_world_multiplatform.yaml b/.github/workflows/hello_world_multiplatform.yaml
index 59d622149a2..8fb8b11597b 100644
--- a/.github/workflows/hello_world_multiplatform.yaml
+++ b/.github/workflows/hello_world_multiplatform.yaml
@@ -16,6 +16,9 @@ on:
       - '.github/workflows/hello_world_multiplatform.yaml'
       - 'SDK_VERSION'
 
+permissions:
+  contents: read
+
 concurrency:
   group: ${{ github.workflow }}-${{ github.event_name }}-${{ github.head_ref || github.ref }}
   cancel-in-progress: true
@@ -29,7 +32,7 @@ jobs:
     runs-on: ${{ matrix.os }}
     steps:
       - name: Checkout
-        uses: actions/checkout@v4
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
         with:
           path: zephyr
           fetch-depth: 0
@@ -51,12 +54,12 @@ jobs:
           git log --graph --oneline HEAD...${PR_HEAD}
 
       - name: Set up Python
-        uses: actions/setup-python@v5
+        uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
         with:
           python-version: 3.11
 
       - name: Setup Zephyr project
-        uses: zephyrproject-rtos/action-zephyr-setup@v1
+        uses: zephyrproject-rtos/action-zephyr-setup@f7b70269a8eb01f70c8e710891e4c94972a2f6b4 # v1.0.6
         with:
           app-path: zephyr
           toolchains: all
@@ -70,11 +73,11 @@ jobs:
           elif [ "${{ runner.os }}" = "Windows" ]; then
             EXTRA_TWISTER_FLAGS="-P native_sim --short-build-path -O/tmp/twister-out"
           fi
-          ./scripts/twister --force-color --inline-logs -T samples/hello_world -T samples/cpp/hello_world -v $EXTRA_TWISTER_FLAGS
+          ./scripts/twister --runtime-artifact-cleanup --force-color --inline-logs -T samples/hello_world -T samples/cpp/hello_world -v $EXTRA_TWISTER_FLAGS
 
       - name: Upload artifacts
         if: failure()
-        uses: actions/upload-artifact@v4
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           if-no-files-found: ignore
           path:
diff --git a/.github/workflows/issue_count.yml b/.github/workflows/issue_count.yml
index 7d6ed6dfc3e..0ab24ef5f64 100644
--- a/.github/workflows/issue_count.yml
+++ b/.github/workflows/issue_count.yml
@@ -4,6 +4,9 @@ on:
   schedule:
   - cron: '*/10 * * * *'
 
+permissions:
+  contents: read
+
 env:
   OUTPUT_FILE_NAME: IssuesReport.md
   COMMITTER_EMAIL: actions@github.com
@@ -14,7 +17,7 @@ env:
 jobs:
   track-issues:
     name: "Collect Issue Stats"
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     if: github.repository == 'zephyrproject-rtos/zephyr'
 
     steps:
@@ -27,7 +30,7 @@ jobs:
         sudo apt-get update
         sudo apt-get install discount
 
-    - uses: brcrista/summarize-issues@v4
+    - uses: brcrista/summarize-issues@54c549b7d38b7db39e5c6e06fd9617e12e5c3491 # v4
       with:
         title: 'Issues Report for ${{ github.repository }}'
         configPath: 'issues-report-config.json'
@@ -35,14 +38,14 @@ jobs:
         token: ${{ secrets.GITHUB_TOKEN }}
 
     - name: upload-stats
-      uses: actions/upload-artifact@v4
+      uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
       continue-on-error: true
       with:
         name: ${{ env.OUTPUT_FILE_NAME }}
         path: ${{ env.OUTPUT_FILE_NAME }}
 
     - name: Configure AWS Credentials
-      uses: aws-actions/configure-aws-credentials@v4
+      uses: aws-actions/configure-aws-credentials@ececac1a45f3b08a01d2dd070d28d111c5fe6722 # v4.1.0
       with:
         aws-access-key-id: ${{ vars.AWS_TESTING_ACCESS_KEY_ID }}
         aws-secret-access-key: ${{ secrets.AWS_TESTING_SECRET_ACCESS_KEY }}
diff --git a/.github/workflows/license_check.yml b/.github/workflows/license_check.yml
index 7d2d083faae..212c7636659 100644
--- a/.github/workflows/license_check.yml
+++ b/.github/workflows/license_check.yml
@@ -2,22 +2,25 @@ name: Scancode
 
 on: [pull_request]
 
+permissions:
+  contents: read
+
 jobs:
   scancode_job:
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     name: Scan code for licenses
     steps:
     - name: Checkout the code
-      uses: actions/checkout@v4
+      uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
       with:
         fetch-depth: 0
     - name: Scan the code
       id: scancode
-      uses: zephyrproject-rtos/action_scancode@v4
+      uses: zephyrproject-rtos/action_scancode@23ef91ce31cd4b954366a7b71eea47520da9b380 # v4
       with:
         directory-to-scan: 'scan/'
     - name: Artifact Upload
-      uses: actions/upload-artifact@v4
+      uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
       with:
         name: scancode
         path: ./artifacts
diff --git a/.github/workflows/manifest.yml b/.github/workflows/manifest.yml
index c3bdc4ff6c8..fdd6f75e38c 100644
--- a/.github/workflows/manifest.yml
+++ b/.github/workflows/manifest.yml
@@ -2,33 +2,49 @@ name: Manifest
 on:
   pull_request_target:
 
+permissions:
+  contents: read
+
 jobs:
   contribs:
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
+    permissions:
+      pull-requests: write # to create/update pull request comments
     name: Manifest
     steps:
       - name: Checkout the code
-        uses: actions/checkout@v4
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
         with:
           path: zephyrproject/zephyr
           ref: ${{ github.event.pull_request.head.sha }}
           fetch-depth: 0
           persist-credentials: false
 
+      - name: Set up Python
+        uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
+        with:
+          python-version: 3.12
+          cache: pip
+          cache-dependency-path: scripts/requirements-actions.txt
+
+      - name: Install Python packages
+        run: |
+          cd zephyrproject/zephyr
+          pip install -r scripts/requirements-actions.txt --require-hashes
+
       - name: west setup
         env:
           BASE_REF: ${{ github.base_ref }}
         working-directory: zephyrproject/zephyr
         run: |
-          pip install west
           git config --global user.email "you@example.com"
           git config --global user.name "Your Name"
           west init -l . || true
 
       - name: Manifest
-        uses: zephyrproject-rtos/action-manifest@v1.7.0
+        uses: zephyrproject-rtos/action-manifest@cb8f6fba6f20b5f8649bd573e80a7583a239894c # v1.7.0
         with:
-          github-token: ${{ secrets.ZB_GITHUB_TOKEN }}
+          github-token: ${{ secrets.GITHUB_TOKEN }}
           manifest-path: 'west.yml'
           checkout-path: 'zephyrproject/zephyr'
           use-tree-checkout: 'true'
@@ -36,4 +52,4 @@ jobs:
           label-prefix: 'manifest-'
           verbosity-level: '1'
           labels: 'manifest'
-          dnm-labels: 'DNM'
+          dnm-labels: 'DNM (manifest)'
diff --git a/.github/workflows/pinned-gh-actions.yml b/.github/workflows/pinned-gh-actions.yml
new file mode 100644
index 00000000000..12ca5963221
--- /dev/null
+++ b/.github/workflows/pinned-gh-actions.yml
@@ -0,0 +1,19 @@
+name: Check SHA-pinned GitHub Actions
+
+on:
+  pull_request:
+    paths:
+      - '.github/workflows/**'
+
+permissions:
+  contents: read
+
+jobs:
+  check-sha-pinned-actions:
+    name: Verify GitHub Actions
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout code
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+      - name: Ensure SHA pinned actions
+        uses: zgosalvez/github-actions-ensure-sha-pinned-actions@4830be28ce81da52ec70d65c552a7403821d98d4 # v3.0.23
diff --git a/.github/workflows/pr_metadata_check.yml b/.github/workflows/pr_metadata_check.yml
new file mode 100644
index 00000000000..3564c6352c8
--- /dev/null
+++ b/.github/workflows/pr_metadata_check.yml
@@ -0,0 +1,40 @@
+name: PR Metadata Check
+
+on:
+  pull_request:
+    types:
+      - synchronize
+      - opened
+      - reopened
+      - labeled
+      - unlabeled
+      - edited
+
+permissions:
+  contents: read
+
+jobs:
+  do-not-merge:
+    name: Prevent Merging
+    runs-on: ubuntu-24.04
+    steps:
+      - name: Check for label
+        if: ${{ contains(github.event.*.labels.*.name, 'DNM') ||
+                contains(github.event.*.labels.*.name, 'DNM (manifest)') ||
+                contains(github.event.*.labels.*.name, 'TSC') ||
+                contains(github.event.*.labels.*.name, 'Architecture Review') ||
+                contains(github.event.*.labels.*.name, 'dev-review') }}
+        run: |
+          echo "Pull request is labeled as 'DNM', 'TSC', 'Architecture Review' or 'dev-review'."
+          echo "This workflow fails so that the pull request cannot be merged."
+          exit 1
+
+  empty_pr_description:
+    if: ${{ github.event.pull_request.body == '' }}
+    name: PR Description
+    runs-on: ubuntu-24.04
+    steps:
+      - name: Check for PR description
+        run: |
+          echo "Pull request description cannot be empty."
+          exit 1
diff --git a/.github/workflows/pylib_tests.yml b/.github/workflows/pylib_tests.yml
index bf9d8289212..29cfd1a5273 100644
--- a/.github/workflows/pylib_tests.yml
+++ b/.github/workflows/pylib_tests.yml
@@ -19,6 +19,9 @@ on:
     - 'scripts/pylib/build_helpers/**'
     - '.github/workflows/pylib_tests.yml'
 
+permissions:
+  contents: read
+
 jobs:
   pylib-tests:
     name: Misc. Pylib Unit Tests
@@ -26,25 +29,21 @@ jobs:
     strategy:
       matrix:
         python-version: ['3.10', '3.11', '3.12', '3.13']
-        os: [ubuntu-22.04]
+        os: [ubuntu-24.04]
     steps:
     - name: checkout
-      uses: actions/checkout@v4
+      uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+
     - name: Set up Python ${{ matrix.python-version }}
-      uses: actions/setup-python@v5
+      uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
       with:
         python-version: ${{ matrix.python-version }}
-    - name: cache-pip-linux
-      if: startsWith(runner.os, 'Linux')
-      uses: actions/cache@v4
-      with:
-        path: ~/.cache/pip
-        key: ${{ runner.os }}-pip-${{ matrix.python-version }}
-        restore-keys: |
-          ${{ runner.os }}-pip-${{ matrix.python-version }}
-    - name: install-packages
+        cache: pip
+        cache-dependency-path: scripts/requirements-actions.txt
+
+    - name: Install Python packages
       run: |
-        pip install -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt
+        pip install -r scripts/requirements-actions.txt --require-hashes
     - name: Run pytest for build_helpers
       env:
         ZEPHYR_BASE: ./
diff --git a/.github/workflows/ready-to-merge.yml b/.github/workflows/ready-to-merge.yml
index 897a6044522..01f08e8a4b6 100644
--- a/.github/workflows/ready-to-merge.yml
+++ b/.github/workflows/ready-to-merge.yml
@@ -7,6 +7,9 @@ on:
         type: string
         required: true
 
+permissions:
+  contents: read
+
 jobs:
   all_jobs_passed:
     name: all jobs passed
diff --git a/.github/workflows/release.yml b/.github/workflows/release.yml
index 002485b9d80..91f4037a2e2 100644
--- a/.github/workflows/release.yml
+++ b/.github/workflows/release.yml
@@ -6,11 +6,16 @@ on:
       - 'v*'
       - '!v*rc*'
 
+permissions:
+  contents: read
+
 jobs:
   release:
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
+    permissions:
+      contents: write # to create GitHub release entry
     steps:
-      - uses: actions/checkout@v4
+      - uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
         with:
           fetch-depth: 0
 
@@ -21,12 +26,12 @@ jobs:
           echo "TRIMMED_VERSION=${GITHUB_REF#refs/tags/v}" >> $GITHUB_OUTPUT
 
       - name: REUSE Compliance Check
-        uses: fsfe/reuse-action@v4
+        uses: fsfe/reuse-action@bb774aa972c2a89ff34781233d275075cbddf542 # v5.0.0
         with:
           args: spdx -o zephyr-${{ steps.get_version.outputs.VERSION }}.spdx
 
       - name: upload-results
-        uses: actions/upload-artifact@v4
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         continue-on-error: true
         with:
           name: zephyr-${{ steps.get_version.outputs.VERSION }}.spdx
@@ -38,7 +43,7 @@ jobs:
 
       - name: Create Release
         id: create_release
-        uses: actions/create-release@v1
+        uses: actions/create-release@0cb9c9b65d5d1901c1f53e5e66eaf4afd303e70e # v1.1.4
         env:
           GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
         with:
@@ -50,7 +55,7 @@ jobs:
 
       - name: Upload Release Assets
         id: upload-release-asset
-        uses: actions/upload-release-asset@v1
+        uses: actions/upload-release-asset@e8f9f06c4b078e705bd2ea027f0926603fc9b4d5 # v1.0.2
         env:
           GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
         with:
diff --git a/.github/workflows/scorecards.yml b/.github/workflows/scorecards.yml
index e2325da0a4a..d54e76cdcb8 100644
--- a/.github/workflows/scorecards.yml
+++ b/.github/workflows/scorecards.yml
@@ -29,12 +29,12 @@ jobs:
 
     steps:
       - name: "Checkout code"
-        uses: actions/checkout@692973e3d937129bcbf40652eb9f2f61becf3332 # v4.1.7
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
         with:
           persist-credentials: false
 
       - name: "Run analysis"
-        uses: ossf/scorecard-action@62b2cac7ed8198b15735ed49ab1e5cf35480ba46 # v2.4.0
+        uses: ossf/scorecard-action@f49aabe0b5af0936a0987cfb85d86b75731b0186 # v2.4.1
         with:
           results_file: results.sarif
           results_format: sarif
@@ -47,7 +47,7 @@ jobs:
       # uploads of run results in SARIF format to the repository Actions tab.
       # https://docs.github.com/en/actions/advanced-guides/storing-workflow-data-as-artifacts
       - name: "Upload artifact"
-        uses: actions/upload-artifact@89ef406dd8d7e03cfd12d9e0a4a378f454709029 # v4.3.5
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: SARIF file
           path: results.sarif
@@ -56,6 +56,6 @@ jobs:
       # Upload the results to GitHub's code scanning dashboard (optional).
       # Commenting out will disable upload of results to your repo's Code Scanning dashboard
       - name: "Upload to code-scanning"
-        uses: github/codeql-action/upload-sarif@afb54ba388a7dca6ecae48f608c4ff05ff4cc77a # v3.25.15
+        uses: github/codeql-action/upload-sarif@1b549b9259bda1cb5ddde3b41741a82a2d15a841 # v3.28.13
         with:
           sarif_file: results.sarif
diff --git a/.github/workflows/scripts_tests.yml b/.github/workflows/scripts_tests.yml
index 06e12ada528..0664dbcebc5 100644
--- a/.github/workflows/scripts_tests.yml
+++ b/.github/workflows/scripts_tests.yml
@@ -19,6 +19,9 @@ on:
       - 'scripts/build/**'
       - '.github/workflows/scripts_tests.yml'
 
+permissions:
+  contents: read
+
 jobs:
   scripts-tests:
     name: Scripts tests
@@ -26,10 +29,10 @@ jobs:
     strategy:
       matrix:
         python-version: ['3.10', '3.11', '3.12', '3.13']
-        os: [ubuntu-20.04]
+        os: [ubuntu-24.04]
     steps:
       - name: checkout
-        uses: actions/checkout@v4
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
         with:
           ref: ${{ github.event.pull_request.head.sha }}
           fetch-depth: 0
@@ -49,22 +52,15 @@ jobs:
           git log --graph --oneline HEAD...${PR_HEAD}
 
       - name: Set up Python ${{ matrix.python-version }}
-        uses: actions/setup-python@v5
+        uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
         with:
           python-version: ${{ matrix.python-version }}
+          cache: pip
+          cache-dependency-path: scripts/requirements-actions.txt
 
-      - name: cache-pip-linux
-        if: startsWith(runner.os, 'Linux')
-        uses: actions/cache@v4
-        with:
-          path: ~/.cache/pip
-          key: ${{ runner.os }}-pip-${{ matrix.python-version }}
-          restore-keys: |
-            ${{ runner.os }}-pip-${{ matrix.python-version }}
-
-      - name: install-packages
+      - name: Install Python packages
         run: |
-          pip install -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt
+          pip install -r scripts/requirements-actions.txt --require-hashes
 
       - name: Run pytest
         env:
diff --git a/.github/workflows/stale-workflow-queue-cleanup.yml b/.github/workflows/stale-workflow-queue-cleanup.yml
index ec1a4cc716f..f40d5b928da 100644
--- a/.github/workflows/stale-workflow-queue-cleanup.yml
+++ b/.github/workflows/stale-workflow-queue-cleanup.yml
@@ -7,6 +7,9 @@ on:
   # everyday at 15:00
   - cron: '0 15 * * *'
 
+permissions:
+  contents: read
+
 concurrency:
   group: stale-workflow-queue-cleanup
   cancel-in-progress: true
@@ -14,11 +17,13 @@ concurrency:
 jobs:
   cleanup:
     name: Cleanup
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
+    permissions:
+      actions: write # to delete stale workflow runs
 
     steps:
     - name: Delete stale queued workflow runs
-      uses: MajorScruffy/delete-old-workflow-runs@v0.3.0
+      uses: MajorScruffy/delete-old-workflow-runs@78b5af714fefaefdf74862181c467b061782719e # v0.3.0
       with:
         repository: ${{ github.repository }}
         # Remove any workflow runs in "queued" state for more than 1 day
diff --git a/.github/workflows/stale_issue.yml b/.github/workflows/stale_issue.yml
index f71e485ff8e..ec59d2641d9 100644
--- a/.github/workflows/stale_issue.yml
+++ b/.github/workflows/stale_issue.yml
@@ -3,13 +3,20 @@ on:
   schedule:
   - cron: "16 00 * * *"
 
+permissions:
+  contents: read
+
 jobs:
   stale:
     name: Find Stale issues and PRs
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     if: github.repository == 'zephyrproject-rtos/zephyr'
+    permissions:
+      pull-requests: write # to comment on stale pull requests
+      issues: write        # to comment on stale issues
+
     steps:
-    - uses: actions/stale@v9
+    - uses: actions/stale@5bef64f19d7facfb25b37b414482c7164d639639 # v9.1.0
       with:
         stale-pr-message: 'This pull request has been marked as stale because it has been open (more
           than) 60 days with no activity. Remove the stale label or add a comment saying that you
diff --git a/.github/workflows/stats_merged_prs.yml b/.github/workflows/stats_merged_prs.yml
index 0f86958e47b..bb79f772801 100644
--- a/.github/workflows/stats_merged_prs.yml
+++ b/.github/workflows/stats_merged_prs.yml
@@ -6,13 +6,28 @@ on:
       - main
       - v*-branch
     types: [closed]
+
+permissions:
+  contents: read
+
 jobs:
   record_merged:
     if: github.event.pull_request.merged == true && github.repository == 'zephyrproject-rtos/zephyr'
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     steps:
       - name: checkout
-        uses: actions/checkout@v4
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+
+      - name: Set up Python
+        uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
+        with:
+          python-version: 3.12
+          cache: pip
+          cache-dependency-path: scripts/requirements-actions.txt
+      - name: Install Python packages
+        run: |
+          pip install -r scripts/requirements-actions.txt --require-hashes
+
       - name: PR event
         env:
           GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
@@ -20,5 +35,4 @@ jobs:
           ELASTICSEARCH_SERVER: "https://elasticsearch.zephyrproject.io:443"
           PR_STAT_ES_INDEX: ${{ vars.PR_STAT_ES_INDEX }}
         run: |
-          pip install pygithub elasticsearch
           python3 ./scripts/ci/stats/merged_prs.py --pull-request ${{ github.event.pull_request.number }} --repo ${{ github.repository }}
diff --git a/.github/workflows/twister-prep.yaml b/.github/workflows/twister-prep.yaml
deleted file mode 100644
index 51bc771059d..00000000000
--- a/.github/workflows/twister-prep.yaml
+++ /dev/null
@@ -1,147 +0,0 @@
-name: Prepare For a Twister Run
-
-on:
-  workflow_call:
-    outputs:
-      subset:
-        description: subset
-        value: ${{ jobs.prep_push.outputs.subset != '' && jobs.prep_push.outputs.subset ||  jobs.prep_pr.outputs.subset }}
-      size:
-        description: size
-        value: ${{ jobs.prep_push.outputs.size != '' && jobs.prep_push.outputs.size || jobs.prep_pr.outputs.size }}
-      fullrun:
-        description: fullrun
-        value: ${{ jobs.prep_push.outputs.fullrun != '' && jobs.prep_push.outputs.fullrun || jobs.prep_pr.outputs.size }}
-
-jobs:
-  prep_pr:
-    if: github.repository_owner == 'zephyrproject-rtos' && github.event_name == 'pull_request_target'
-    runs-on:
-      group: zephyr-runner-v2-linux-x64-4xlarge
-    container:
-      image: ghcr.io/zephyrproject-rtos/ci-repo-cache:v0.27.4.20241026
-      options: '--entrypoint /bin/bash'
-    outputs:
-      subset: ${{ steps.output-services.outputs.subset }}
-      size: ${{ steps.output-services.outputs.size }}
-      fullrun: ${{ steps.output-services.outputs.fullrun }}
-    env:
-      MATRIX_SIZE: 10
-      PUSH_MATRIX_SIZE: 20
-      DAILY_MATRIX_SIZE: 80
-      BSIM_OUT_PATH: /opt/bsim/
-      BSIM_COMPONENTS_PATH: /opt/bsim/components
-      TESTS_PER_BUILDER: 700
-      COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }}
-      BASE_REF: ${{ github.base_ref }}
-    steps:
-      - name: Apply container owner mismatch workaround
-        run: |
-          # FIXME: The owner UID of the GITHUB_WORKSPACE directory may not
-          #        match the container user UID because of the way GitHub
-          #        Actions runner is implemented. Remove this workaround when
-          #        GitHub comes up with a fundamental fix for this problem.
-          git config --global --add safe.directory ${GITHUB_WORKSPACE}
-
-      - name: Print cloud service information
-        run: |
-          echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}"
-          echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}"
-          echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}"
-
-      - name: Clone cached Zephyr repository
-        continue-on-error: true
-        run: |
-          git clone --shared /repo-cache/zephyrproject/zephyr .
-          git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY}
-
-      - name: Checkout
-        uses: actions/checkout@v4
-        with:
-          ref: ${{ github.event.pull_request.head.sha }}
-          fetch-depth: 0
-          persist-credentials: false
-
-      - name: Environment Setup
-        run: |
-          git config --global user.email "bot@zephyrproject.org"
-          git config --global user.name "Zephyr Bot"
-          rm -fr ".git/rebase-apply"
-          rm -fr ".git/rebase-merge"
-          git rebase origin/${BASE_REF}
-          git clean -f -d
-          git log  --pretty=oneline | head -n 10
-          west init -l . || true
-          west config manifest.group-filter -- +ci,+optional
-          west config --global update.narrow true
-          west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || west update --path-cache /repo-cache/zephyrproject 2>&1 1> west.update.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /repo-cache/zephyrproject)
-          west forall -c 'git reset --hard HEAD'
-
-          echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV
-
-      - name: Generate Test Plan with Twister
-        id: test-plan
-        run: |
-          export ZEPHYR_BASE=${PWD}
-          export ZEPHYR_TOOLCHAIN_VARIANT=zephyr
-          python3 ./scripts/ci/test_plan.py -c origin/${BASE_REF}.. --no-detailed-test-id --pull-request -t $TESTS_PER_BUILDER
-          if [ -s .testplan ]; then
-            cat .testplan >> $GITHUB_ENV
-          else
-            echo "TWISTER_NODES=${MATRIX_SIZE}" >> $GITHUB_ENV
-          fi
-          rm -f testplan.json .testplan
-
-      - name: Determine matrix size
-        id: output-services
-        run: |
-          if [ -n "${TWISTER_NODES}" ]; then
-            subset="[$(seq -s',' 1 ${TWISTER_NODES})]"
-          else
-            subset="[$(seq -s',' 1 ${MATRIX_SIZE})]"
-          fi
-          size=${TWISTER_NODES}
-
-          echo "subset=${subset}" >> $GITHUB_OUTPUT
-          echo "size=${size}" >> $GITHUB_OUTPUT
-          echo "fullrun=${TWISTER_FULL}" >> $GITHUB_OUTPUT
-
-  prep_push:
-    if: github.repository_owner == 'zephyrproject-rtos' && (github.event_name == 'push' || github.event_name == 'schedule')
-    runs-on: ubuntu-22.04
-    outputs:
-      subset: ${{ steps.output-services.outputs.subset }}
-      size: ${{ steps.output-services.outputs.size }}
-      fullrun: ${{ steps.output-services.outputs.fullrun }}
-    env:
-      MATRIX_SIZE: 10
-      PUSH_MATRIX_SIZE: 20
-      DAILY_MATRIX_SIZE: 80
-      BSIM_OUT_PATH: /opt/bsim/
-      BSIM_COMPONENTS_PATH: /opt/bsim/components
-      TESTS_PER_BUILDER: 700
-      COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }}
-      BASE_REF: ${{ github.base_ref }}
-    steps:
-      - name: Print cloud service information
-        run: |
-          echo "ZEPHYR_RUNNER_CLOUD_PROVIDER = ${ZEPHYR_RUNNER_CLOUD_PROVIDER}"
-          echo "ZEPHYR_RUNNER_CLOUD_NODE = ${ZEPHYR_RUNNER_CLOUD_NODE}"
-          echo "ZEPHYR_RUNNER_CLOUD_POD = ${ZEPHYR_RUNNER_CLOUD_POD}"
-
-      - name: Determine matrix size
-        id: output-services
-        run: |
-          if [ "${{github.event_name}}" = "push" ]; then
-            subset="[$(seq -s',' 1 ${PUSH_MATRIX_SIZE})]"
-            size=${MATRIX_SIZE}
-          elif [ "${{github.event_name}}" = "schedule" -a "${{github.repository}}" = "zephyrproject-rtos/zephyr" ]; then
-            subset="[$(seq -s',' 1 ${DAILY_MATRIX_SIZE})]"
-            size=${DAILY_MATRIX_SIZE}
-          else
-            size=0
-          fi
-
-          echo "subset=${subset}" >> $GITHUB_OUTPUT
-          echo "size=${size}" >> $GITHUB_OUTPUT
-          echo "fullrun=${TWISTER_FULL}" >> $GITHUB_OUTPUT
diff --git a/.github/workflows/twister-publish.yaml b/.github/workflows/twister-publish.yaml
index 3695d060726..ceac5a7736b 100644
--- a/.github/workflows/twister-publish.yaml
+++ b/.github/workflows/twister-publish.yaml
@@ -8,26 +8,38 @@ on:
     types:
       - completed
 
+permissions:
+  contents: read
+
 jobs:
   upload-to-elasticsearch:
     if: |
       github.repository == 'zephyrproject-rtos/zephyr' &&
-      github.event.workflow_run.event != 'pull_request_target'
+      github.event.workflow_run.event != 'pull_request'
     env:
       ELASTICSEARCH_KEY: ${{ secrets.ELASTICSEARCH_KEY }}
       ELASTICSEARCH_SERVER: "https://elasticsearch.zephyrproject.io:443"
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
     steps:
       # Needed for elasticearch and upload script
       - name: Checkout
-        uses: actions/checkout@v4
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
         with:
           fetch-depth: 0
           persist-credentials: false
+      - name: Set up Python
+        uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
+        with:
+          python-version: 3.12
+          cache: pip
+          cache-dependency-path: scripts/requirements-actions.txt
+      - name: Install Python packages
+        run: |
+          pip install -r scripts/requirements-actions.txt --require-hashes
 
       - name: Download Artifacts
         id: download-artifacts
-        uses: dawidd6/action-download-artifact@v6
+        uses: dawidd6/action-download-artifact@07ab29fd4a977ae4d2b275087cf67563dfdf0295 # v9
         with:
           path: artifacts
           workflow: twister.yml
@@ -37,7 +49,6 @@ jobs:
       - name: Upload to elasticsearch
         if: steps.download-artifacts.outputs.found_artifact == 'true'
         run: |
-          pip install elasticsearch
           # set run date on upload to get consistent and unified data across the matrix.
           run_date=`date --iso-8601=minutes`
           if [ "${{github.event.workflow_run.event}}" = "push" ]; then
diff --git a/.github/workflows/twister.yaml b/.github/workflows/twister.yaml
index 8d3b29fa433..946cfff778e 100644
--- a/.github/workflows/twister.yaml
+++ b/.github/workflows/twister.yaml
@@ -6,14 +6,17 @@ on:
       - main
       - v*-branch
       - collab-*
-  pull_request_target:
+  pull_request:
     branches:
       - main
       - v*-branch
       - collab-*
   schedule:
-    # Run at 03:00 UTC on every Sunday
-    - cron: '0 3 * * 0'
+    # Run at 17:00 UTC on every Saturday
+    - cron: '0 17 * * 6'
+
+permissions:
+  contents: read
 
 concurrency:
   group: ${{ github.workflow }}-${{ github.event_name }}-${{ github.head_ref || github.ref }}
@@ -21,7 +24,102 @@ concurrency:
 
 jobs:
   twister-build-prep:
-    uses: ./.github/workflows/twister-prep.yaml
+    if: github.repository_owner == 'zephyrproject-rtos'
+    runs-on: ubuntu-24.04
+    outputs:
+      subset: ${{ steps.output-services.outputs.subset }}
+      size: ${{ steps.output-services.outputs.size }}
+      fullrun: ${{ steps.output-services.outputs.fullrun }}
+    env:
+      MATRIX_SIZE: 10
+      PUSH_MATRIX_SIZE: 20
+      WEEKLY_MATRIX_SIZE: 200
+      BSIM_OUT_PATH: /opt/bsim/
+      BSIM_COMPONENTS_PATH: /opt/bsim/components
+      TESTS_PER_BUILDER: 900
+      COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }}
+      BASE_REF: ${{ github.base_ref }}
+    steps:
+      - name: Checkout
+        if: github.event_name == 'pull_request'
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          ref: ${{ github.event.pull_request.head.sha }}
+          fetch-depth: 0
+          path: zephyr
+          persist-credentials: false
+
+      - name: Set up Python
+        if: github.event_name == 'pull_request'
+        uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
+        with:
+          python-version: 3.12
+          cache: pip
+          cache-dependency-path: scripts/requirements-actions.txt
+
+      - name: install-packages
+        working-directory: zephyr
+        if: github.event_name == 'pull_request'
+        run: |
+          pip install -r scripts/requirements-actions.txt --require-hashes
+
+      - name: Setup Zephyr project
+        if: github.event_name == 'pull_request'
+        uses: zephyrproject-rtos/action-zephyr-setup@f7b70269a8eb01f70c8e710891e4c94972a2f6b4 # v1.0.6
+        with:
+          app-path: zephyr
+          toolchains: all
+
+      - name: Environment Setup
+        working-directory: zephyr
+        if: github.event_name == 'pull_request'
+        run: |
+          git config --global user.email "bot@zephyrproject.org"
+          git config --global user.name "Zephyr Bot"
+          rm -fr ".git/rebase-apply"
+          rm -fr ".git/rebase-merge"
+          git rebase origin/${BASE_REF}
+          git clean -f -d
+          git log  --pretty=oneline | head -n 10
+
+      - name: Generate Test Plan with Twister
+        working-directory: zephyr
+        if: github.event_name == 'pull_request'
+        id: test-plan
+        run: |
+          export ZEPHYR_BASE=${PWD}
+          export ZEPHYR_TOOLCHAIN_VARIANT=zephyr
+          python3 ./scripts/ci/test_plan.py -c origin/${BASE_REF}.. --no-detailed-test-id --pull-request -t $TESTS_PER_BUILDER
+          if [ -s .testplan ]; then
+            cat .testplan >> $GITHUB_ENV
+          else
+            echo "TWISTER_NODES=${MATRIX_SIZE}" >> $GITHUB_ENV
+          fi
+          rm -f testplan.json .testplan
+
+      - name: Determine matrix size
+        id: output-services
+        run: |
+          if [ "${{github.event_name}}" = "push" ]; then
+            subset="[$(seq -s',' 1 ${PUSH_MATRIX_SIZE})]"
+            size=${MATRIX_SIZE}
+          elif [ "${{github.event_name}}" = "pull_request" ]; then
+            if [ -n "${TWISTER_NODES}" ]; then
+              subset="[$(seq -s',' 1 ${TWISTER_NODES})]"
+            else
+              subset="[$(seq -s',' 1 ${MATRIX_SIZE})]"
+            fi
+            size=${TWISTER_NODES}
+          elif [ "${{github.event_name}}" = "schedule" -a "${{github.repository}}" = "zephyrproject-rtos/zephyr" ]; then
+            subset="[$(seq -s',' 1 ${WEEKLY_MATRIX_SIZE})]"
+            size=${WEEKLY_MATRIX_SIZE}
+          else
+            size=0
+          fi
+
+          echo "subset=${subset}" >> $GITHUB_OUTPUT
+          echo "size=${size}" >> $GITHUB_OUTPUT
+          echo "fullrun=${TWISTER_FULL}" >> $GITHUB_OUTPUT
 
   twister-build:
     runs-on:
@@ -44,10 +142,10 @@ jobs:
       CCACHE_IGNOREOPTIONS: '-specs=* --specs=*'
       BSIM_OUT_PATH: /opt/bsim/
       BSIM_COMPONENTS_PATH: /opt/bsim/components
-      TWISTER_COMMON: '--no-detailed-test-id --force-color --inline-logs -v -N -M --retry-failed 3 --timeout-multiplier 2 '
-      WEEKLY_OPTIONS: ' -M --build-only --all --show-footprint --report-filtered'
-      PR_OPTIONS: ' --clobber-output --integration'
-      PUSH_OPTIONS: ' --clobber-output -M --show-footprint --report-filtered'
+      TWISTER_COMMON: ' --test-config tests/test_config_ci.yaml --no-detailed-test-id --force-color --inline-logs -v -N -M --retry-failed 3 --timeout-multiplier 2 '
+      WEEKLY_OPTIONS: ' -M --build-only --all --show-footprint --report-filtered -j 32'
+      PR_OPTIONS: ' --clobber-output --integration -j 16'
+      PUSH_OPTIONS: ' --clobber-output -M --show-footprint --report-filtered -j 16'
       COMMIT_RANGE: ${{ github.event.pull_request.base.sha }}..${{ github.event.pull_request.head.sha }}
       BASE_REF: ${{ github.base_ref }}
       LLVM_TOOLCHAIN_PATH: /usr/lib/llvm-16
@@ -73,7 +171,7 @@ jobs:
           git remote set-url origin ${GITHUB_SERVER_URL}/${GITHUB_REPOSITORY}
 
       - name: Checkout
-        uses: actions/checkout@v4
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
         with:
           ref: ${{ github.event.pull_request.head.sha }}
           fetch-depth: 0
@@ -81,7 +179,7 @@ jobs:
 
       - name: Environment Setup
         run: |
-          if [ "${{github.event_name}}" = "pull_request_target" ]; then
+          if [ "${{github.event_name}}" = "pull_request" ]; then
             git config --global user.email "bot@zephyrproject.org"
             git config --global user.name "Zephyr Builder"
             rm -fr ".git/rebase-apply"
@@ -143,7 +241,7 @@ jobs:
             fi
           fi
 
-      - if: github.event_name == 'pull_request_target'
+      - if: github.event_name == 'pull_request'
         name: Run Tests with Twister (Pull Request)
         id: run_twister_pr
         run: |
@@ -160,7 +258,7 @@ jobs:
           fi
 
       - if: github.event_name == 'schedule'
-        name: Run Tests with Twister (Daily)
+        name: Run Tests with Twister (Weekly)
         id: run_twister_sched
         run: |
           export ZEPHYR_BASE=${PWD}
@@ -180,7 +278,7 @@ jobs:
 
       - name: Upload Unit Test Results
         if: always()
-        uses: actions/upload-artifact@v4
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: Unit Test Results (Subset ${{ matrix.subset }})
           if-no-files-found: ignore
@@ -202,7 +300,7 @@ jobs:
 
       - if: matrix.subset == 1 && github.event_name == 'push'
         name: Upload the list of Python packages
-        uses: actions/upload-artifact@v4
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
           name: Frozen PIP package set
           path: |
@@ -212,37 +310,76 @@ jobs:
     name: "Publish Unit Tests Results"
     needs:
       - twister-build
-    runs-on: ubuntu-22.04
+    runs-on: ubuntu-24.04
+    permissions:
+      checks: write # to create the check run entry with Twister test results
     # the build-and-test job might be skipped, we don't need to run this job then
     if: success() || failure()
 
     steps:
+      - name: Check out source code
+        uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+        with:
+          ref: ${{ github.event.pull_request.head.sha }}
+          fetch-depth: 0
+          persist-credentials: false
+
+      - name: Set up Python
+        uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
+        with:
+          python-version: 3.12
+          cache: pip
+          cache-dependency-path: scripts/requirements-actions.txt
+
+      - name: Install Python packages
+        run: |
+          pip install -r scripts/requirements-actions.txt --require-hashes
+
       - name: Download Artifacts
-        uses: actions/download-artifact@v4
+        uses: actions/download-artifact@95815c38cf2ff2164869cbab79da8d1f422bc89e # v4.2.1
         with:
           path: artifacts
 
       - name: Merge Test Results
         run: |
-          pip install junitparser junit2html
           junitparser merge artifacts/*/*/twister.xml junit.xml
           junit2html junit.xml junit.html
 
-      - name: Upload Unit Test Results in HTML
+      - name: Upload Unit Test Results
         if: always()
-        uses: actions/upload-artifact@v4
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
         with:
-          name: HTML Unit Test Results
+          name: Unit Test Results
           if-no-files-found: ignore
           path: |
             junit.html
+            junit.xml
 
       - name: Publish Unit Test Results
-        uses: EnricoMi/publish-unit-test-result-action@v2
+        uses: EnricoMi/publish-unit-test-result-action@170bf24d20d201b842d7a52403b73ed297e6645b # v2.18.0
         with:
           check_name: Unit Test Results
           files: "**/twister.xml"
           comment_mode: off
+
+      - name: Analyze Twister Reports
+        if: needs.twister-build.result == 'failure'
+        run: |
+          ./scripts/ci/twister_report_analyzer.py artifacts/*/*/twister.json --long-summary --platforms --output-md errors.md
+          if [[ -s "errors.md" ]]; then
+            echo '### Error Summary! 🚀' >> $GITHUB_STEP_SUMMARY
+            cat errors.md  >> $GITHUB_STEP_SUMMARY
+          fi
+
+      - name: Upload Twister Analysis Results
+        if: needs.twister-build.result == 'failure'
+        uses: actions/upload-artifact@ea165f8d65b6e75b540449e92b4886f43607fa02 # v4.6.2
+        with:
+          name: Twister Analysis Results
+          if-no-files-found: ignore
+          path: |
+            twister_report_summary.json
+
   twister-status-check:
     if: always()
     name: "Check Twister Status"
diff --git a/.github/workflows/twister_tests.yml b/.github/workflows/twister_tests.yml
index 66409bce876..394936a29aa 100644
--- a/.github/workflows/twister_tests.yml
+++ b/.github/workflows/twister_tests.yml
@@ -26,6 +26,9 @@ on:
     - '.github/workflows/twister_tests.yml'
     - 'scripts/schemas/twister/'
 
+permissions:
+  contents: read
+
 jobs:
   twister-tests:
     name: Twister Unit Tests
@@ -33,25 +36,22 @@ jobs:
     strategy:
       matrix:
         python-version: ['3.10', '3.11', '3.12', '3.13']
-        os: [ubuntu-22.04]
+        os: [ubuntu-24.04]
     steps:
     - name: checkout
-      uses: actions/checkout@v4
+      uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+
     - name: Set up Python ${{ matrix.python-version }}
-      uses: actions/setup-python@v5
+      uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
       with:
         python-version: ${{ matrix.python-version }}
-    - name: cache-pip-linux
-      if: startsWith(runner.os, 'Linux')
-      uses: actions/cache@v4
-      with:
-        path: ~/.cache/pip
-        key: ${{ runner.os }}-pip-${{ matrix.python-version }}
-        restore-keys: |
-          ${{ runner.os }}-pip-${{ matrix.python-version }}
-    - name: install-packages
+        cache: pip
+        cache-dependency-path: scripts/requirements-actions.txt
+
+    - name: Install Python packages
       run: |
-        pip install -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt -r scripts/requirements-run-test.txt
+        pip install -r scripts/requirements-actions.txt --require-hashes
+
     - name: Run pytest for twisterlib
       env:
         ZEPHYR_BASE: ./
diff --git a/.github/workflows/twister_tests_blackbox.yml b/.github/workflows/twister_tests_blackbox.yml
index cd24a2a39ae..1e9303e24dd 100644
--- a/.github/workflows/twister_tests_blackbox.yml
+++ b/.github/workflows/twister_tests_blackbox.yml
@@ -15,66 +15,51 @@ on:
     - 'scripts/tests/twister_blackbox/**'
     - '.github/workflows/twister_tests_blackbox.yml'
 
+permissions:
+  contents: read
+
 jobs:
   twister-tests:
     name: Twister Black Box Tests
-    runs-on: ${{ matrix.os }}
+    runs-on: ubuntu-24.04
     strategy:
       matrix:
         python-version: ['3.10', '3.11', '3.12', '3.13']
-        os: [ubuntu-22.04]
-    container:
-      image: ghcr.io/zephyrproject-rtos/ci:v0.27.4
-
     steps:
-    - name: Apply Container Owner Mismatch Workaround
-      run: |
-        # FIXME: The owner UID of the GITHUB_WORKSPACE directory may not
-        #        match the container user UID because of the way GitHub
-        #        Actions runner is implemented. Remove this workaround when
-        #        GitHub comes up with a fundamental fix for this problem.
-        git config --global --add safe.directory ${GITHUB_WORKSPACE}
-
     - name: Checkout
-      uses: actions/checkout@v4
-
-    - name: Environment Setup
-      run: |
-        echo "$HOME/.local/bin" >> $GITHUB_PATH
-
-        west init -l . || true
-        # we do not depend on any hals, tools or bootloader, save some time and space...
-        west config manifest.group-filter -- -hal,-tools,-bootloader,-babblesim
-        west config manifest.project-filter -- -nrf_hw_models
-        west config --global update.narrow true
-        west update --path-cache /github/cache/zephyrproject 2>&1 1> west.update.log || west update --path-cache /github/cache/zephyrproject 2>&1 1> west.update.log || ( rm -rf ../modules ../bootloader ../tools && west update --path-cache /github/cache/zephyrproject)
-        west forall -c 'git reset --hard HEAD'
-
-        echo "ZEPHYR_SDK_INSTALL_DIR=/opt/toolchains/zephyr-sdk-$( cat SDK_VERSION )" >> $GITHUB_ENV
+      uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+      with:
+        path: zephyr
+        fetch-depth: 0
 
     - name: Set Up Python ${{ matrix.python-version }}
-      uses: actions/setup-python@v5
+      uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
       with:
         python-version: ${{ matrix.python-version }}
+        cache: pip
+        cache-dependency-path: scripts/requirements-actions.txt
 
-    - name: Go Into Venv
-      shell: bash
+    - name: install-packages
+      working-directory: zephyr
       run: |
-        python3 -m pip install --user virtualenv
-        python3 -m venv env
-        source env/bin/activate
-        echo "$(which python)"
+        pip install -r scripts/requirements-actions.txt --require-hashes
+        sudo apt-get update -y
+        sudo apt-get install -y lcov
 
-    - name: Install Packages
-      run: |
-        python3 -m pip install -U -r scripts/requirements-base.txt -r scripts/requirements-build-test.txt -r scripts/requirements-run-test.txt
+    - name: Setup Zephyr project
+      uses: zephyrproject-rtos/action-zephyr-setup@f7b70269a8eb01f70c8e710891e4c94972a2f6b4 # v1.0.6
+      with:
+        app-path: zephyr
+        toolchains: all
 
     - name: Run Pytest For Twister Black Box Tests
+      working-directory: zephyr
       shell: bash
       env:
         ZEPHYR_BASE: ./
         ZEPHYR_TOOLCHAIN_VARIANT: zephyr
       run: |
+        export ZEPHYR_SDK_INSTALL_DIR=${{ github.workspace }}/zephyr-sdk
         echo "Run twister tests"
         source zephyr-env.sh
-        PYTHONPATH="./scripts/tests" pytest ./scripts/tests/twister_blackbox
+        PYTHONPATH="./scripts/tests" pytest ./scripts/tests/twister_blackbox/
diff --git a/.github/workflows/west_cmds.yml b/.github/workflows/west_cmds.yml
index 3d4802f0170..1756664303d 100644
--- a/.github/workflows/west_cmds.yml
+++ b/.github/workflows/west_cmds.yml
@@ -23,8 +23,11 @@ on:
     - 'scripts/west_commands/**'
     - '.github/workflows/west_cmds.yml'
 
+permissions:
+  contents: read
+
 jobs:
-  west-commnads:
+  west-commands:
     name: West Command Tests
     runs-on: ${{ matrix.os }}
     strategy:
@@ -33,43 +36,24 @@ jobs:
         os: [ubuntu-22.04, macos-14, windows-2022]
     steps:
     - name: checkout
-      uses: actions/checkout@v4
+      uses: actions/checkout@11bd71901bbe5b1630ceea73d27597364c9af683 # v4.2.2
+
     - name: Set up Python ${{ matrix.python-version }}
-      uses: actions/setup-python@v5
+      uses: actions/setup-python@8d9ed9ac5c53483de85588cdf95a591a75ab9f55 # v5.5.0
       with:
         python-version: ${{ matrix.python-version }}
-    - name: cache-pip-linux
-      if: startsWith(runner.os, 'Linux')
-      uses: actions/cache@v4
-      with:
-        path: ~/.cache/pip
-        key: ${{ runner.os }}-pip-${{ matrix.python-version }}
-        restore-keys: |
-          ${{ runner.os }}-pip-${{ matrix.python-version }}
-    - name: cache-pip-mac
-      if: startsWith(runner.os, 'macOS')
-      uses: actions/cache@v4
-      with:
-        path: ~/Library/Caches/pip
-        # Trailing '-' was just to get a different cache name
-        key: ${{ runner.os }}-pip-${{ matrix.python-version }}-
-        restore-keys: |
-          ${{ runner.os }}-pip-${{ matrix.python-version }}-
-    - name: cache-pip-win
-      if: startsWith(runner.os, 'Windows')
-      uses: actions/cache@v4
-      with:
-        path: ~\AppData\Local\pip\Cache
-        key: ${{ runner.os }}-pip-${{ matrix.python-version }}
-        restore-keys: |
-          ${{ runner.os }}-pip-${{ matrix.python-version }}
-    - name: install pytest
+        cache: pip
+        cache-dependency-path: scripts/requirements-actions.txt
+
+    - name: Install Python packages
       run: |
-        pip install pytest west pyelftools canopen natsort progress mypy intelhex psutil ply pyserial anytree
+        pip install -r scripts/requirements-actions.txt --require-hashes
+
     - name: run pytest-win
       if: runner.os == 'Windows'
       run: |
         python ./scripts/west_commands/run_tests.py
+
     - name: run pytest-mac-linux
       if: runner.os != 'Windows'
       run: |
diff --git a/.gitignore b/.gitignore
index b545443db31..aab3981f52f 100644
--- a/.gitignore
+++ b/.gitignore
@@ -104,5 +104,8 @@ Nits.txt
 Pylint.txt
 Ruff.txt
 SphinxLint.txt
+SysbuildKconfig.txt
+SysbuildKconfigBasic.txt
+SysbuildKconfigBasicNoModules.txt
 TextEncoding.txt
 YAMLLint.txt
diff --git a/.gitlint b/.gitlint
index e83edce6b6e..16e9bdca9aa 100644
--- a/.gitlint
+++ b/.gitlint
@@ -59,3 +59,7 @@ ignore-merge-commits=false
 # By specifying this rule, developers can only change the file when they explicitly reference
 # it in the commit message.
 #files=gitlint/rules.py,README.md
+
+[ignore-by-author-name]
+regex=^dependabot\[bot\]$
+ignore=all
diff --git a/.mailmap b/.mailmap
index 050d05cce9f..27cc2a560e3 100644
--- a/.mailmap
+++ b/.mailmap
@@ -1,14 +1,14 @@
 Alexandr Kolosov <rikorsev@gmail.com>
 Alexandre d'Alton <alexandre.dalton@intel.com>
-Amir Kaplan <amir.kaplan@intel.com> <amir.kaplan@intel.com>
-Anas Nashif <anas.nashif@intel.com> <anas.nashif@intel.com>
+Amir Kaplan <amir.kaplan@intel.com>
+Anas Nashif <anas.nashif@intel.com>
 Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
 Anthony Smigielski <thebasti0ncode@gmail.com>
 Armand Ciejak <armand@riedonetworks.com>  <armandciejak@users.noreply.github.com>
 Aska Wu <aska.wu@linaro.org>
-Bit Pathe <bitpathe@gmail.com> <bitpathe@gmail.com>
+Bit Pathe <bitpathe@gmail.com>
 Bjarki Arge Andreasen <baa@trackunit.com>
-Carles Cufi <carles.cufi@nordicsemi.no> <carles.cufi@nordicsemi.no>
+Carles Cufi <carles.cufi@nordicsemi.no>
 chao an <anchao@xiaomi.com>
 Charles E. Youse <charles.youse@intel.com>
 Chen Xingyu <hi@xingrz.me>
@@ -16,32 +16,32 @@ Christoph Schnetzler <christoph.schnetzler@husqvarnagroup.com>
 Christoph Schramm <schramm@makaio.com>
 Christopher Friedt <cfriedt@meta.com>
 Christopher Friedt <cfriedt@meta.com> <cfriedt@fb.com>
-Chuck Jordan <cjordan@synopsys.com> <cjordan@synopsys.com>
+Chuck Jordan <cjordan@synopsys.com>
 Chunlin Han <chunlin.han@linaro.org> <chunlin.han@acer.com>
 David B. Kinder <david.b.kinder@intel.com>
 David Komel <a8961713@gmail.com>
 David Leach <david.leach@nxp.com>
-Dirk Brandewie <dirk.j.brandewie@intel.com> <dirk.j.brandewie@intel.com>
-Douglas Su <d0u9.su@outlook.com> <d0u9.su@outlook.com>
+Dirk Brandewie <dirk.j.brandewie@intel.com>
+Douglas Su <d0u9.su@outlook.com>
 Enjia Mai <enjia.mai@intel.com>
-Enjia Mai <enjia.mai@intel.com> <enjiax.mai@intel.com>
-Evan Couzens <evanx.couzens@intel.com> <evanx.couzens@intel.com>
+Enjia Mai <enjia.mai@intel.com>
+Evan Couzens <evanx.couzens@intel.com>
 Evgeniy Paltsev <PaltsevEvgeniy@gmail.com>
 Evgeniy Paltsev <PaltsevEvgeniy@gmail.com> <Eugeniy.Paltsev@synopsys.com>
-Felipe Neves <ryukokki.felipe@gmail.com> <ryukokki.felipe@gmail.com>
+Felipe Neves <ryukokki.felipe@gmail.com>
 Findlay Feng <i@fengch.me>
 Flavio Arieta Netto <flavio@exati.com.br>
 Francois Ramu <francois.ramu@st.com>
-Gerardo Aceves <gerardo.aceves@intel.com> <gerardo.aceves@intel.com>
+Gerardo Aceves <gerardo.aceves@intel.com>
 Gregory Shue <gregory.shue@legrand.com>
 Gregory Shue <gregory.shue@legrand.com> <gregory.shue@legrand.us>
 HaiLong Yang <cameledyang@pm.me>
 James Johnson <james.johnson672@t-mobile.com>
 Jarno Lämsä <jarno.lamsa@nordicsemi.no>
 Jędrzej Ciupis <jedrzej.ciupis@nordicsemi.no>
-Jeremie Garcia <jeremie.garcia@intel.com> <jeremie.garcia@intel.com>
+Jeremie Garcia <jeremie.garcia@intel.com>
 Jim Benjamin Luther <jilu@oticon.com>
-Johan Kruger <johan.kruger@windriver.com> <johan.kruger@windriver.com>
+Johan Kruger <johan.kruger@windriver.com>
 Johann Fischer <j.fischer@phytec.de>
 Jørgen Kvalvaag <jorgen.kvalvaag@nordicsemi.no>
 Juan Manuel Cruz Alcaraz <juan.m.cruz.alcaraz@intel.com>
@@ -51,11 +51,11 @@ Jun Li <jun.r.li@intel.com>
 Justin Watson <jwatson5@gmail.com>
 Kamil Sroka <kamil.sroka@nordicsemi.no>
 Katarzyna Giądła <katarzyna.giadla@nordicsemi.no>
-Keren Siman-Tov <keren.siman-tov@intel.com> <keren.siman-tov@intel.com>
+Keren Siman-Tov <keren.siman-tov@intel.com>
 Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
-Kuo-Lang Tseng <kuo-lang.tseng@intel.com> <kuo-lang.tseng@intel.com>
-Lei Liu <lei.a.liu@intel.com> <lei.a.liu@intel.com>
-Leona Cook <leonax.cook@intel.com> <leonax.cook@intel.com>
+Kuo-Lang Tseng <kuo-lang.tseng@intel.com>
+Lei Liu <lei.a.liu@intel.com>
+Leona Cook <leonax.cook@intel.com>
 Leona Cook <leonax.cook@intel.com> <lsc@hackeress.com>
 Lixin Guo <lixinx.guo@intel.com>
 Łukasz Mazur <lukasz.mazur@hidglobal.com>
@@ -72,14 +72,14 @@ Martí Bolívar <marti.bolivar@nordicsemi.no> <marti.bolivar@linaro.org>
 Martí Bolívar <marti.bolivar@nordicsemi.no> <marti.f.bolivar@gmail.com>
 Martí Bolívar <marti.bolivar@nordicsemi.no> <marti@foundries.io>
 Martí Bolívar <marti.bolivar@nordicsemi.no> <marti@opensourcefoundries.com>
-Martin Jäger <martin@libre.solar>  <17674105+martinjaeger@users.noreply.github.com>
+Martin Jäger <martin@libre.solar> <17674105+martinjaeger@users.noreply.github.com>
 Mateusz Hołenko <mholenko@antmicro.com>
 Michael Rosen <michael.r.rosen@intel.com>
 Michal Narajowski <michal.narajowski@codecoup.pl>
-Mike Hirst <michael.hirst@windriver.com> <michael.hirst@windriver.com>
+Mike Hirst <michael.hirst@windriver.com>
 Ming Shao <ming.shao@intel.com>
 Mohan Kumar Kumar <mohankm@fb.com>
-Naga Raja Rao Tulasi <tulasi.r@tcs.com> <tulasi.r@tcs.com>
+Naga Raja Rao Tulasi <tulasi.r@tcs.com>
 Navin Sankar Velliangiri <navin@linumiz.com>
 NingX Zhao <ningx.zhao@intel.com>
 Nishikant Nayak <nishikantax.nayak@intel.com>
@@ -100,21 +100,23 @@ Radosław Koppel <radoslaw.koppel@nordicsemi.no> <r.koppel@k-el.com>
 Raja D. Singh <rdsingh@iotwizards.com>
 Ricardo Salveti <ricardo@opensourcefoundries.com>
 Ricardo Salveti <ricardo@opensourcefoundries.com> <ricardo.salveti@linaro.org>
-Ruud Derwig <Ruud.Derwig@synopsys.com> <Ruud.Derwig@synopsys.com>
+Ruud Derwig <Ruud.Derwig@synopsys.com>
 Saku Rautio <saku.rautio@nordicsemi.no>
 Scott Worley <scott.worley@microchip.com>
 Sean Nyekjaer <sean@geanix.com> <sean.nyekjaer@prevas.dk>
 Sean Nyekjaer <sean@geanix.com> <sean@nyekjaer.dk>
 Sharron Liu <sharron.liu@intel.com>
 Shilpashree L C <shilpashree.lc@intel.com>
-Shuang He <shuang.he@intel.com> <shuang.he@intel.com>
+Shuang He <shuang.he@intel.com>
 Sigvart Hovland <sigvart.hovland@nordicsemi.no>
 Stéphane D'Alu <sdalu@sdalu.com>
 Stine Åkredalen <stine.akredalen@nordicsemi.no>
-Thomas Heeley <thomas.heeley@intel.com> <thomas.heeley@intel.com>
+Thomas Heeley <thomas.heeley@intel.com>
 Tim Sørensen <tims@demant.com>
 Tim Sørensen <tims@demant.com> <tims@oticon.com>
-Vinayak Kariappa Chettimada <vinayak.kariappa.chettimada@nordicsemi.no> <vinayak.kariappa.chettimada@nordicsemi.no> <vich@nordicsemi.no> <vinayak.kariappa@gmail.com>
+Vinayak Kariappa Chettimada <vinayak.kariappa.chettimada@nordicsemi.no>
+Vinayak Kariappa Chettimada <vinayak.kariappa.chettimada@nordicsemi.no> <vich@nordicsemi.no>
+Vinayak Kariappa Chettimada <vinayak.kariappa.chettimada@nordicsemi.no> <vinayak.kariappa@gmail.com>
 Xiaorui Hu <xiaorui.hu@linaro.org>
 Yannis Damigos <giannis.damigos@gmail.com> <ydamigos@iccs.gr>
 Yonattan Louise <yonattan.a.louise.mendoza@intel.com>
diff --git a/.ruff-excludes.toml b/.ruff-excludes.toml
index ac26af8b3c8..276bdcdd546 100644
--- a/.ruff-excludes.toml
+++ b/.ruff-excludes.toml
@@ -436,26 +436,10 @@
     "UP035",    # https://docs.astral.sh/ruff/rules/deprecated-import
 ]
 "./scripts/dts/python-devicetree/src/devicetree/dtlib.py" = [
-    "E701",     # https://docs.astral.sh/ruff/rules/multiple-statements-on-one-line-colon
-    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
-    "SIM201",   # https://docs.astral.sh/ruff/rules/negate-equal-op
     "UP007",    # https://docs.astral.sh/ruff/rules/non-pep604-annotation
-    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
-    "UP035",    # https://docs.astral.sh/ruff/rules/deprecated-import
-    "UP037",    # https://docs.astral.sh/ruff/rules/quoted-annotation
 ]
 "./scripts/dts/python-devicetree/src/devicetree/edtlib.py" = [
-    "B904",     # https://docs.astral.sh/ruff/rules/raise-without-from-inside-except
-    "B905",     # https://docs.astral.sh/ruff/rules/zip-without-explicit-strict
-    "E713",     # https://docs.astral.sh/ruff/rules/not-in-test
-    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
-    "SIM102",   # https://docs.astral.sh/ruff/rules/collapsible-if
-    "SIM118",   # https://docs.astral.sh/ruff/rules/in-dict-keys
     "UP007",    # https://docs.astral.sh/ruff/rules/non-pep604-annotation
-    "UP015",    # https://docs.astral.sh/ruff/rules/redundant-open-modes
-    "UP032",    # https://docs.astral.sh/ruff/rules/f-string
-    "UP035",    # https://docs.astral.sh/ruff/rules/deprecated-import
-    "UP037",    # https://docs.astral.sh/ruff/rules/quoted-annotation
 ]
 "./scripts/dts/python-devicetree/src/devicetree/grutils.py" = [
     "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
@@ -830,14 +814,6 @@
     "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
     "UP026",    # https://docs.astral.sh/ruff/rules/deprecated-mock-import
 ]
-"./scripts/tests/twister/test_config_parser.py" = [
-    "B017",     # https://docs.astral.sh/ruff/rules/assert-raises-exception
-    "B033",     # https://docs.astral.sh/ruff/rules/duplicate-value
-    "E501",     # https://docs.astral.sh/ruff/rules/line-too-long
-    "I001",     # https://docs.astral.sh/ruff/rules/unsorted-imports
-    "SIM117",   # https://docs.astral.sh/ruff/rules/multiple-with-statements
-    "UP026",    # https://docs.astral.sh/ruff/rules/deprecated-mock-import
-]
 "./scripts/tests/twister/test_data/mixins/test_to_ignore.py" = [
     "B011",     # https://docs.astral.sh/ruff/rules/assert-false
 ]
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 5bd9348cb57..196a87294ea 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -71,6 +71,15 @@ set(ZEPHYR_CURRENT_LINKER_PASS 0)
 set(ZEPHYR_CURRENT_LINKER_CMD    linker_zephyr_pre${ZEPHYR_CURRENT_LINKER_PASS}.cmd)
 set(ZEPHYR_LINK_STAGE_EXECUTABLE zephyr_pre${ZEPHYR_CURRENT_LINKER_PASS})
 
+# Make kconfig variables available to the linker script generator
+zephyr_linker_include_generated(KCONFIG ${CMAKE_CURRENT_BINARY_DIR}/.config)
+
+# The linker generator also needs sections.h to be able to access e.g. _APP_SMEM_SECTION_NAME
+# for linkerscripts that do not support c-preprocessing.
+zephyr_linker_include_generated(HEADER ${ZEPHYR_BASE}/include/zephyr/linker/sections.h)
+
+zephyr_linker_include_var(VAR CMAKE_VERBOSE_MAKEFILE VALUE ${CMAKE_VERBOSE_MAKEFILE})
+
 # ZEPHYR_PREBUILT_EXECUTABLE is used outside of this file, therefore keep the
 # existing variable to allow slowly cleanup of linking stage handling.
 # Three stage linking active: pre0 -> pre1 -> final, this will correspond to `pre1`
@@ -174,13 +183,17 @@ endif()
 
 # @Intent: Set compiler flags to detect general stack overflows across all functions
 if(CONFIG_STACK_CANARIES)
-  zephyr_compile_options($<TARGET_PROPERTY:compiler,security_canaries>)
+  zephyr_compile_options("$<$<COMPILE_LANGUAGE:C>:$<TARGET_PROPERTY:compiler,security_canaries>>")
+  zephyr_compile_options("$<$<COMPILE_LANGUAGE:CXX>:$<TARGET_PROPERTY:compiler,security_canaries>>")
 elseif(CONFIG_STACK_CANARIES_STRONG)
-  zephyr_compile_options($<TARGET_PROPERTY:compiler,security_canaries_strong>)
+  zephyr_compile_options("$<$<COMPILE_LANGUAGE:C>:$<TARGET_PROPERTY:compiler,security_canaries_strong>>")
+  zephyr_compile_options("$<$<COMPILE_LANGUAGE:CXX>:$<TARGET_PROPERTY:compiler,security_canaries_strong>>")
 elseif(CONFIG_STACK_CANARIES_ALL)
-  zephyr_compile_options($<TARGET_PROPERTY:compiler,security_canaries_all>)
+  zephyr_compile_options("$<$<COMPILE_LANGUAGE:C>:$<TARGET_PROPERTY:compiler,security_canaries_all>>")
+  zephyr_compile_options("$<$<COMPILE_LANGUAGE:CXX>:$<TARGET_PROPERTY:compiler,security_canaries_all>>")
 elseif(CONFIG_STACK_CANARIES_EXPLICIT)
-  zephyr_compile_options($<TARGET_PROPERTY:compiler,security_canaries_explicit>)
+  zephyr_compile_options("$<$<COMPILE_LANGUAGE:C>:$<TARGET_PROPERTY:compiler,security_canaries_explicit>>")
+  zephyr_compile_options("$<$<COMPILE_LANGUAGE:CXX>:$<TARGET_PROPERTY:compiler,security_canaries_explicit>>")
 endif()
 
 # @Intent: Obtain compiler optimizations flags and store in variables
@@ -227,7 +240,8 @@ SOC_* symbol.")
 endif()
 
 # Apply the final optimization flag(s)
-zephyr_compile_options(${OPTIMIZATION_FLAG})
+zephyr_compile_options($<$<COMPILE_LANGUAGE:C>:${OPTIMIZATION_FLAG}>)
+zephyr_compile_options($<$<COMPILE_LANGUAGE:CXX>:${OPTIMIZATION_FLAG}>)
 
 if(CONFIG_LTO)
   zephyr_compile_options($<TARGET_PROPERTY:compiler,optimization_lto>)
@@ -315,7 +329,9 @@ if(CONFIG_CODING_GUIDELINE_CHECK)
 endif()
 
 # @Intent: Set compiler specific macro inclusion of AUTOCONF_H
-zephyr_compile_options("SHELL: $<TARGET_PROPERTY:compiler,imacros> ${AUTOCONF_H}")
+zephyr_compile_options("SHELL: $<$<COMPILE_LANGUAGE:C>:$<TARGET_PROPERTY:compiler,imacros> ${AUTOCONF_H}>")
+zephyr_compile_options("SHELL: $<$<COMPILE_LANGUAGE:CXX>:$<TARGET_PROPERTY:compiler,imacros> ${AUTOCONF_H}>")
+zephyr_compile_options("SHELL: $<$<COMPILE_LANGUAGE:ASM>:$<TARGET_PROPERTY:asm,imacros> ${AUTOCONF_H}>")
 
 if(CONFIG_COMPILER_FREESTANDING)
   # @Intent: Set compiler specific flag for bare metal freestanding option
@@ -360,7 +376,9 @@ zephyr_compile_options($<$<COMPILE_LANGUAGE:ASM>:$<TARGET_PROPERTY:asm,required>
 # @Intent: Enforce standard integer type correspondence to match Zephyr usage.
 # (must be after compiler specific flags)
 if(CONFIG_ENFORCE_ZEPHYR_STDINT)
-  zephyr_compile_options("SHELL: $<TARGET_PROPERTY:compiler,imacros> ${ZEPHYR_BASE}/include/zephyr/toolchain/zephyr_stdint.h")
+  zephyr_compile_options("SHELL:$<$<COMPILE_LANGUAGE:C>:$<TARGET_PROPERTY:compiler,imacros> ${ZEPHYR_BASE}/include/zephyr/toolchain/zephyr_stdint.h>")
+  zephyr_compile_options("SHELL:$<$<COMPILE_LANGUAGE:CXX>:$<TARGET_PROPERTY:compiler,imacros> ${ZEPHYR_BASE}/include/zephyr/toolchain/zephyr_stdint.h>")
+  zephyr_compile_options("SHELL:$<$<COMPILE_LANGUAGE:ASM>:$<TARGET_PROPERTY:asm,imacros> ${ZEPHYR_BASE}/include/zephyr/toolchain/zephyr_stdint.h>")
 endif()
 
 # Common toolchain-agnostic assembly flags
@@ -926,6 +944,8 @@ add_custom_target(${DEVICE_API_LD_TARGET}
                           ${DEVICE_API_LINKER_SECTIONS_CMAKE}
 )
 
+zephyr_linker_include_generated(CMAKE ${DEVICE_API_LINKER_SECTIONS_CMAKE})
+
 # Add a pseudo-target that is up-to-date when all generated headers
 # are up-to-date.
 
@@ -1109,17 +1129,15 @@ set_ifndef(  TOPT "${COMPILER_TOPT}")
 set_ifndef(  TOPT -Wl,-T) # Use this if the compiler driver doesn't set a value
 
 if(CONFIG_HAVE_CUSTOM_LINKER_SCRIPT)
-  set(LINKER_SCRIPT ${APPLICATION_SOURCE_DIR}/${CONFIG_CUSTOM_LINKER_SCRIPT})
+  string(CONFIGURE ${APPLICATION_SOURCE_DIR}/${CONFIG_CUSTOM_LINKER_SCRIPT} LINKER_SCRIPT)
   if(NOT EXISTS ${LINKER_SCRIPT})
-    set(LINKER_SCRIPT ${CONFIG_CUSTOM_LINKER_SCRIPT})
-    assert_exists(CONFIG_CUSTOM_LINKER_SCRIPT)
+    string(CONFIGURE ${CONFIG_CUSTOM_LINKER_SCRIPT} LINKER_SCRIPT)
+    assert_exists(LINKER_SCRIPT)
   endif()
 elseif(DEFINED BOARD_LINKER_SCRIPT)
   set(LINKER_SCRIPT ${BOARD_LINKER_SCRIPT})
 elseif(DEFINED SOC_LINKER_SCRIPT)
   set(LINKER_SCRIPT ${SOC_LINKER_SCRIPT})
-else()
-  find_package(Deprecated COMPONENTS SEARCHED_LINKER_SCRIPT)
 endif()
 
 if(NOT EXISTS ${LINKER_SCRIPT})
@@ -1127,14 +1145,20 @@ if(NOT EXISTS ${LINKER_SCRIPT})
 endif()
 
 if(CONFIG_USERSPACE)
-  set(APP_SMEM_ALIGNED_LD "${PROJECT_BINARY_DIR}/include/generated/app_smem_aligned.ld")
-  set(APP_SMEM_UNALIGNED_LD "${PROJECT_BINARY_DIR}/include/generated/app_smem_unaligned.ld")
+  if(CONFIG_CMAKE_LINKER_GENERATOR)
+    set(APP_SMEM_LD_EXT "cmake")
+  else()
+    set(APP_SMEM_LD_EXT "ld")
+  endif()
+
+  set(APP_SMEM_ALIGNED_LD "${PROJECT_BINARY_DIR}/include/generated/app_smem_aligned.${APP_SMEM_LD_EXT}")
+  set(APP_SMEM_UNALIGNED_LD "${PROJECT_BINARY_DIR}/include/generated/app_smem_unaligned.${APP_SMEM_LD_EXT}")
 
   if(CONFIG_LINKER_USE_PINNED_SECTION)
     set(APP_SMEM_PINNED_ALIGNED_LD
-        "${PROJECT_BINARY_DIR}/include/generated/app_smem_pinned_aligned.ld")
+        "${PROJECT_BINARY_DIR}/include/generated/app_smem_pinned_aligned.${APP_SMEM_LD_EXT}")
     set(APP_SMEM_PINNED_UNALIGNED_LD
-        "${PROJECT_BINARY_DIR}/include/generated/app_smem_pinned_unaligned.ld")
+        "${PROJECT_BINARY_DIR}/include/generated/app_smem_pinned_unaligned.${APP_SMEM_LD_EXT}")
 
     if(NOT CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT)
       # The libc partition may hold symbols that are required during boot process,
@@ -1199,9 +1223,11 @@ if(CONFIG_USERSPACE)
 
   set(APP_SMEM_UNALIGNED_LIB app_smem_unaligned_output_obj_renamed_lib)
   list(APPEND LINKER_PASS_${ZEPHYR_CURRENT_LINKER_PASS}_DEFINE "LINKER_APP_SMEM_UNALIGNED")
-endif()
 
-if (CONFIG_USERSPACE)
+  foreach(dep ${APP_SMEM_UNALIGNED_LD} ${APP_SMEM_PINNED_UNALIGNED_LD})
+    zephyr_linker_include_generated(CMAKE ${dep} PASS LINKER_APP_SMEM_UNALIGNED)
+  endforeach()
+
   add_custom_command(
     OUTPUT ${APP_SMEM_ALIGNED_LD} ${APP_SMEM_PINNED_ALIGNED_LD}
     COMMAND ${PYTHON_EXECUTABLE}
@@ -1221,6 +1247,9 @@ if (CONFIG_USERSPACE)
     COMMAND_EXPAND_LISTS
     COMMENT "Generating app_smem_aligned linker section"
     )
+    foreach(dep ${APP_SMEM_ALIGNED_LD} ${APP_SMEM_PINNED_ALIGNED_LD})
+      zephyr_linker_include_generated(CMAKE ${dep} PASS NOT LINKER_APP_SMEM_UNALIGNED)
+    endforeach()
 endif()
 
 if(CONFIG_USERSPACE)
@@ -1328,6 +1357,13 @@ if(CONFIG_USERSPACE)
     DEPENDS
     ${KOBJECT_LINKER_HEADER_DATA}
   )
+
+  # gen_kobject_placeholders.py generates linker-kobject-prebuild-data.h,
+  # linker-kobject-prebuild-priv-stacks.h and linker-kobject-prebuild-rodata.h
+  foreach(ext "-data.h" "-priv-stacks.h" "-rodata.h")
+    string(REGEX REPLACE "-data.h$" ${ext} file ${KOBJECT_LINKER_HEADER_DATA})
+    zephyr_linker_include_generated(HEADER ${file} PASS LINKER_ZEPHYR_PREBUILT LINKER_ZEPHYR_FINAL)
+  endforeach()
 endif()
 
 if(CONFIG_USERSPACE OR CONFIG_DEVICE_DEPS)
@@ -1990,7 +2026,6 @@ if (CONFIG_LLEXT AND CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID)
     --elf-file ${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME}
     --slid-listing ${PROJECT_BINARY_DIR}/slid_listing.txt
   )
-
 endif()
 
 if(NOT CMAKE_C_COMPILER_ID STREQUAL "ARMClang")
@@ -2221,51 +2256,57 @@ if((CMAKE_BUILD_TYPE IN_LIST build_types) AND (NOT NO_BUILD_TYPE_WARNING))
 endif()
 
 # Extension Development Kit (EDK) generation.
-set(llext_edk_file ${PROJECT_BINARY_DIR}/${CONFIG_LLEXT_EDK_NAME}.tar.xz)
+if(CONFIG_LLEXT_EDK)
+  if(CONFIG_LLEXT_EDK_FORMAT_TAR_XZ)
+    set(llext_edk_extension "tar.xz")
+  elseif(CONFIG_LLEXT_EDK_FORMAT_TAR_ZSTD)
+    set(llext_edk_extension "tar.Z")
+  elseif(CONFIG_LLEXT_EDK_FORMAT_ZIP)
+    set(llext_edk_extension "zip")
+  else()
+    message(FATAL_ERROR "Unsupported LLEXT_EDK_FORMAT choice")
+  endif()
+  set(llext_edk_file ${PROJECT_BINARY_DIR}/${CONFIG_LLEXT_EDK_NAME}.${llext_edk_extension})
 
-# TODO maybe generate flags for C CXX ASM
-zephyr_get_compile_definitions_for_lang(C zephyr_defs)
-zephyr_get_compile_options_for_lang(C zephyr_flags)
+  # TODO maybe generate flags for C CXX ASM
+  zephyr_get_compile_definitions_for_lang(C zephyr_defs)
+  zephyr_get_compile_options_for_lang(C zephyr_flags)
 
-# Filter out non LLEXT and LLEXT_EDK flags - and add required ones
-llext_filter_zephyr_flags(LLEXT_REMOVE_FLAGS ${zephyr_flags} llext_filt_flags)
-llext_filter_zephyr_flags(LLEXT_EDK_REMOVE_FLAGS ${llext_filt_flags} llext_filt_flags)
+  # Filter out non LLEXT and LLEXT_EDK flags - and add required ones
+  llext_filter_zephyr_flags(LLEXT_REMOVE_FLAGS ${zephyr_flags} llext_filt_flags)
+  llext_filter_zephyr_flags(LLEXT_EDK_REMOVE_FLAGS ${llext_filt_flags} llext_filt_flags)
 
-set(llext_edk_cflags ${zephyr_defs} -DLL_EXTENSION_BUILD)
-list(APPEND llext_edk_cflags ${llext_filt_flags})
-list(APPEND llext_edk_cflags ${LLEXT_APPEND_FLAGS})
-list(APPEND llext_edk_cflags ${LLEXT_EDK_APPEND_FLAGS})
+  set(llext_edk_cflags ${zephyr_defs} -DLL_EXTENSION_BUILD)
+  list(APPEND llext_edk_cflags ${llext_filt_flags})
+  list(APPEND llext_edk_cflags ${LLEXT_APPEND_FLAGS})
+  list(APPEND llext_edk_cflags ${LLEXT_EDK_APPEND_FLAGS})
 
-add_custom_command(
+  build_info(llext-edk file PATH ${llext_edk_file})
+  build_info(llext-edk cflags VALUE ${llext_edk_cflags})
+  build_info(llext-edk include-dirs VALUE "$<TARGET_PROPERTY:zephyr_interface,INTERFACE_INCLUDE_DIRECTORIES>")
+
+  add_custom_command(
     OUTPUT ${llext_edk_file}
     # Regenerate syscalls in case CONFIG_LLEXT_EDK_USERSPACE_ONLY
     COMMAND ${CMAKE_COMMAND}
-        -E make_directory edk/include/generated/zephyr
+      -E make_directory edk/include/generated/zephyr
     COMMAND
-        ${PYTHON_EXECUTABLE}
-        ${ZEPHYR_BASE}/scripts/build/gen_syscalls.py
-        --json-file        ${syscalls_json}                     # Read this file
-        --base-output      edk/include/generated/zephyr/syscalls           # Write to this dir
-        --syscall-dispatch edk/include/generated/zephyr/syscall_dispatch.c # Write this file
-        --syscall-list     ${edk_syscall_list_h}
-        $<$<BOOL:${CONFIG_LLEXT_EDK_USERSPACE_ONLY}>:--userspace-only>
-        ${SYSCALL_LONG_REGISTERS_ARG}
-        ${SYSCALL_SPLIT_TIMEOUT_ARG}
+      ${PYTHON_EXECUTABLE}
+      ${ZEPHYR_BASE}/scripts/build/gen_syscalls.py
+      --json-file        ${syscalls_json}                     # Read this file
+      --base-output      edk/include/generated/zephyr/syscalls           # Write to this dir
+      --syscall-dispatch edk/include/generated/zephyr/syscall_dispatch.c # Write this file
+      --syscall-list     ${edk_syscall_list_h}
+      $<$<BOOL:${CONFIG_LLEXT_EDK_USERSPACE_ONLY}>:--userspace-only>
+      ${SYSCALL_LONG_REGISTERS_ARG}
+      ${SYSCALL_SPLIT_TIMEOUT_ARG}
     COMMAND ${CMAKE_COMMAND}
-        -DPROJECT_BINARY_DIR=${PROJECT_BINARY_DIR}
-        -DAPPLICATION_SOURCE_DIR=${APPLICATION_SOURCE_DIR}
-        -DINTERFACE_INCLUDE_DIRECTORIES="$<TARGET_PROPERTY:zephyr_interface,INTERFACE_INCLUDE_DIRECTORIES>"
-        -Dllext_edk_file=${llext_edk_file}
-        -Dllext_edk_cflags="${llext_edk_cflags}"
-        -Dllext_edk_name=${CONFIG_LLEXT_EDK_NAME}
-        -DWEST_TOPDIR=${WEST_TOPDIR}
-        -DZEPHYR_BASE=${ZEPHYR_BASE}
-        -DCONFIG_LLEXT_EDK_USERSPACE_ONLY=${CONFIG_LLEXT_EDK_USERSPACE_ONLY}
         -P ${ZEPHYR_BASE}/cmake/llext-edk.cmake
-    DEPENDS ${logical_target_for_zephyr_elf}
+    DEPENDS ${logical_target_for_zephyr_elf} build_info_yaml_saved
     COMMAND_EXPAND_LISTS
-)
-add_custom_target(llext-edk DEPENDS ${llext_edk_file})
+  )
+  add_custom_target(llext-edk DEPENDS ${llext_edk_file})
+endif()
 
 # @Intent: Set compiler specific flags for standard C/C++ includes
 # Done at the very end, so any other system includes which may
@@ -2286,9 +2327,8 @@ add_subdirectory_ifdef(
 
 toolchain_linker_finalize()
 
-yaml_context(EXISTS NAME build_info result)
-if(result)
-  build_info(zephyr version VALUE ${PROJECT_VERSION_STR})
-  build_info(zephyr zephyr-base VALUE ${ZEPHYR_BASE})
-  yaml_save(NAME build_info)
-endif()
+# export build information
+build_info(zephyr version VALUE ${PROJECT_VERSION_STR})
+build_info(zephyr zephyr-base VALUE ${ZEPHYR_BASE})
+
+yaml_save(NAME build_info)
diff --git a/CODEOWNERS b/CODEOWNERS
new file mode 100644
index 00000000000..54110c3f9a5
--- /dev/null
+++ b/CODEOWNERS
@@ -0,0 +1,4 @@
+# Instead of the CODEOWNERS file, The Zephyr Project uses a custom format.
+# See MAINTAINERS.yml for details.
+#
+# DO NOT EDIT THIS FILE.
diff --git a/Kconfig.zephyr b/Kconfig.zephyr
index 2d8031260ce..23f7507b432 100644
--- a/Kconfig.zephyr
+++ b/Kconfig.zephyr
@@ -215,12 +215,6 @@ config LINKER_SORT_BY_ALIGNMENT
 	  in decreasing size of symbols. This helps to minimize
 	  padding between symbols.
 
-config SRAM_VECTOR_TABLE
-	bool "Place the vector table in SRAM instead of flash"
-	help
-	  The option specifies that the vector table should be placed at the
-	  start of SRAM instead of the start of flash.
-
 config HAS_SRAM_OFFSET
 	bool
 	help
@@ -621,6 +615,13 @@ config MISRA_SANE
 	  standard for safety reasons.  Specifically variable length
 	  arrays are not permitted (and gcc will enforce this).
 
+config TOOLCHAIN_SUPPORTS_VLA_IN_STATEMENTS
+	bool
+	default y
+	help
+	  Hidden symbol to state if the toolchain can handle vla in
+	  statements.
+
 endmenu
 
 choice
diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml
index 5eed35c70da..1d6ce194239 100644
--- a/MAINTAINERS.yml
+++ b/MAINTAINERS.yml
@@ -126,6 +126,20 @@ ACPI:
   tests:
     - acpi
 
+Antmicro platforms:
+  status: maintained
+  maintainers:
+    - fkokosinski
+    - tgorochowik
+  collaborators:
+    - kgugala
+  files:
+    - boards/antmicro/
+    - soc/antmicro/
+    - dts/arm/antmicro/
+  labels:
+    - "platform: Antmicro"
+
 ARC arch:
   status: maintained
   maintainers:
@@ -148,10 +162,19 @@ ARC arch:
   tests:
     - arch.arc
 
+Arduino Platforms:
+  status: maintained
+  maintainers:
+    - pillo79
+  collaborators:
+    - facchinm
+  files:
+    - boards/arduino/
+
 ARM arch:
   status: maintained
   maintainers:
-    - ithinuel
+    - wearyzen
   collaborators:
     - microbuilder
     - carlocaione
@@ -159,7 +182,7 @@ ARM arch:
     - MaureenHelm
     - stephanosio
     - bbolen
-    - wearyzen
+    - ithinuel
   files:
     - arch/arm/
     - arch/arm/core/offsets/
@@ -180,6 +203,9 @@ ARM64 arch:
     - npitre
     - povergoing
     - sgrrzhf
+    - wearyzen
+    - ithinuel
+    - JiafeiPan
   files:
     - arch/arm64/
     - include/zephyr/arch/arm64/
@@ -195,9 +221,9 @@ ARM64 arch:
 ARM Platforms:
   status: maintained
   maintainers:
-    - ithinuel
-  collaborators:
     - wearyzen
+  collaborators:
+    - ithinuel
   files:
     - boards/arm/mps*/
     - boards/arm/v2m_*/
@@ -265,6 +291,21 @@ Ambiq Platforms:
   labels:
     - "platform: Ambiq"
 
+AndesTech Platforms:
+  status: maintained
+  maintainers:
+    - jimmyzhe
+  collaborators:
+    - kevinwang821020
+  files:
+    - boards/andestech/
+    - drivers/*/*andes*
+    - dts/bindings/*/*andestech*
+    - dts/riscv/andes/
+    - soc/andestech/
+  labels:
+    - "platform: Andes Technology"
+
 BeagleBoard Platforms:
   status: maintained
   maintainers:
@@ -273,6 +314,7 @@ BeagleBoard Platforms:
     - ayush1325
     - con-pax
     - vaishnavachath
+    - glneo
   files:
     - boards/beagle/
   labels:
@@ -338,9 +380,9 @@ Bluetooth Controller:
     - carlescufi
     - thoh-ot
     - ppryga
-    - mtpr-ot
     - wopu-ot
     - erbr-ot
+    - Tronil
   files:
     - doc/connectivity/bluetooth/bluetooth-ctlr-arch.rst
     - doc/connectivity/bluetooth/img/ctlr*
@@ -408,11 +450,11 @@ Bluetooth Host:
     - samples/bluetooth/tmap*/
     - samples/bluetooth/iso_*/
     - samples/bluetooth/mesh*/
-    - subsys/bluetooth/Kconfig.iso
     - subsys/bluetooth/host/iso.c
     - subsys/bluetooth/host/iso_internal.h
     - subsys/bluetooth/host/shell/iso.c
     - tests/bluetooth/audio/
+    - tests/bluetooth/classic/
     - tests/bluetooth/controller/
     - tests/bluetooth/mesh*/
     - tests/bluetooth/qualification/
@@ -501,11 +543,15 @@ Bluetooth Classic:
     - lylezhu2012
   collaborators:
     - jhedberg
+    - MarkWangChinese
+    - gzh-terry
+    - makeshi
   files:
     - doc/connectivity/bluetooth/shell/classic/a2dp.rst
     - subsys/bluetooth/common/
     - subsys/bluetooth/host/classic/
     - include/zephyr/bluetooth/classic/
+    - tests/bluetooth/classic/
   labels:
     - "area: Bluetooth Classic"
     - "area: Bluetooth"
@@ -524,7 +570,6 @@ Bluetooth ISO:
     - include/zephyr/bluetooth/iso.h
     - doc/connectivity/bluetooth/shell/host/iso.rst
     - samples/bluetooth/iso_*/
-    - subsys/bluetooth/Kconfig.iso
     - subsys/bluetooth/host/iso.c
     - subsys/bluetooth/host/iso_internal.h
     - subsys/bluetooth/host/shell/iso.c
@@ -856,7 +901,6 @@ Demand Paging:
 Device Driver Model:
   status: maintained
   maintainers:
-    - gmarull
     - tbursztyka
   collaborators:
     - dcpleung
@@ -889,7 +933,9 @@ DFU:
     - dfu
 
 Devicetree:
-  status: odd fixes
+  status: maintained
+  maintainers:
+    - mbolivar
   collaborators:
     - decsny
     - galak
@@ -946,6 +992,7 @@ Display drivers:
   collaborators:
     - jfischer-no
     - danieldegrasse
+    - VynDragon
   files:
     - drivers/display/
     - dts/bindings/display/
@@ -1000,9 +1047,9 @@ Documentation:
 Documentation Infrastructure:
   status: maintained
   maintainers:
-    - gmarull
     - kartben
   collaborators:
+    - gmarull
     - carlescufi
     - nashif
   files:
@@ -1017,8 +1064,8 @@ Documentation Infrastructure:
 Release Notes:
   status: maintained
   maintainers:
-    - fabiobaltieri
-    - kartben
+    - danieldegrasse
+    - dkalowsk
   collaborators:
     - kartben
   files:
@@ -1231,6 +1278,8 @@ Release Notes:
   status: maintained
   maintainers:
     - ceolin
+  collaborators:
+    - valeriosetti
   files:
     - drivers/crypto/
     - dts/bindings/crypto/
@@ -1385,12 +1434,14 @@ Release Notes:
     - drivers.espi
 
 "Drivers: Ethernet":
-  status: odd fixes
+  status: maintained
+  maintainers:
+    - maass-hamburg
   collaborators:
     - decsny
     - lmajewski
     - pdgendt
-    - maass-hamburg
+    - clamattia
   files:
     - drivers/ethernet/
     - include/zephyr/dt-bindings/ethernet/
@@ -1492,6 +1543,7 @@ Release Notes:
   files:
     - doc/hardware/peripherals/gnss.rst
     - drivers/gnss/
+    - include/zephyr/data/navigation.h
     - include/zephyr/drivers/gnss.h
     - include/zephyr/drivers/gnss/
     - dts/bindings/gnss/
@@ -1618,6 +1670,9 @@ Release Notes:
   status: maintained
   maintainers:
     - carlocaione
+  collaborators:
+    - wearyzen
+    - ithinuel
   files:
     - include/zephyr/drivers/mbox.h
     - drivers/mbox/
@@ -1740,31 +1795,11 @@ Release Notes:
   tests:
     - drivers.ipm
 
-"Drivers: kscan":
-  status: maintained
-  maintainers:
-    - albertofloyd
-  collaborators:
-    - VenkatKotakonda
-  files:
-    - drivers/kscan/
-    - include/zephyr/drivers/kscan.h
-    - samples/drivers/kscan/
-    - tests/drivers/kscan/
-    - dts/bindings/kscan/
-    - doc/hardware/peripherals/kscan.rst
-  labels:
-    - "area: Kscan"
-  tests:
-    - drivers.kscan
-
 "Drivers: LED":
   status: maintained
   maintainers:
     - Mani-Sadhasivam
     - simonguinot
-  collaborators:
-    - bbilas
   files:
     - drivers/led/
     - include/zephyr/drivers/led/
@@ -1801,7 +1836,6 @@ Release Notes:
 "Drivers: MFD":
   status: odd fixes
   collaborators:
-    - gmarull
     - aasinclair
   files:
     - drivers/mfd/
@@ -1912,8 +1946,8 @@ Release Notes:
     - samples.drivers.peci
 
 "Drivers: Pin Control":
-  status: maintained
-  maintainers:
+  status: odd fixes
+  collaborators:
     - gmarull
   files:
     - doc/hardware/pinctrl/
@@ -2049,7 +2083,7 @@ Release Notes:
   labels:
     - "area: Sensors"
   tests:
-    - drivers.sensors
+    - drivers.sensor
 
 "Drivers: SMBus":
   status: maintained
@@ -2094,12 +2128,15 @@ Release Notes:
     - dipakgmx
     - fabiobaltieri
     - faxe1008
+    - jbehrensnx
   files:
     - drivers/stepper/
     - include/zephyr/drivers/stepper.h
     - dts/bindings/stepper/
     - doc/hardware/peripherals/stepper.rst
+    - samples/drivers/stepper/
     - tests/drivers/build_all/stepper/
+    - tests/drivers/stepper/
   labels:
     - "area: Stepper"
   tests:
@@ -2226,16 +2263,6 @@ Release Notes:
   labels:
     - "area: Wi-Fi"
 
-"Drivers: Wi-Fi NXP":
-  status: maintained
-  maintainers:
-    - dleach02
-    - MaochenWang1
-  files:
-    - drivers/wifi/nxp/
-  labels:
-    - "platform: NXP Drivers"
-
 "Drivers: Memory Management":
   status: maintained
   maintainers:
@@ -2295,11 +2322,9 @@ EC Host Commands:
 Xen Platform:
   status: maintained
   maintainers:
-    - povergoing
+    - firscity
   collaborators:
-    - SgrrZhf
     - lorc
-    - firscity
     - luca-fancellu
   files:
     - include/zephyr/xen/
@@ -2380,8 +2405,6 @@ Input:
   status: maintained
   maintainers:
     - fabiobaltieri
-  collaborators:
-    - gmarull
   files:
     - doc/services/input/
     - drivers/input/
@@ -2432,7 +2455,8 @@ JSON Web Token:
     - sir-branch
   files:
     - subsys/jwt/
-    - include/zephyr/data/
+    - include/zephyr/data/json.h
+    - include/zephyr/data/jwt.h
     - lib/utils/json.c
     - tests/subsys/jwt/
     - tests/lib/json/
@@ -2738,6 +2762,21 @@ Modem:
   tests:
     - modem
 
+NEORV32 platform:
+  status: maintained
+  maintainers:
+    - henrikbrixandersen
+  files:
+    - boards/others/neorv32/
+    - drivers/*/*neorv32*
+    - dts/bindings/*/*neorv32*
+    - soc/neorv32/
+    - tests/boards/neorv32/
+  labels:
+    - "platform: NEORV32"
+  tests:
+    - boards.neorv32
+
 OSDP:
   status: maintained
   maintainers:
@@ -2783,7 +2822,7 @@ hawkBit:
   tests:
     - sample.net.updatehub
 
-Native POSIX/Sim and POSIX arch:
+Native_sim and POSIX arch:
   status: maintained
   maintainers:
     - aescolar
@@ -2806,7 +2845,7 @@ Native POSIX/Sim and POSIX arch:
   labels:
     - "area: native port"
   description: >-
-    POSIX architecture and SOC, native_posix & native_sim boards, and related drivers
+    POSIX architecture and SOC, native_sim boards, and related drivers
   tests:
     - boards.native_sim
 
@@ -2838,7 +2877,6 @@ Networking:
     - include/zephyr/net/ieee802154*.h
     - include/zephyr/net/ptp.h
     - include/zephyr/net/wifi*.h
-    - include/zephyr/net/buf.h
     - include/zephyr/net/dhcpv4*.h
     - include/zephyr/net/http/
     - samples/net/gptp/
@@ -2891,7 +2929,6 @@ Networking:
     - jukkar
   files:
     - doc/services/net_buf/
-    - include/zephyr/net/buf.h
     - include/zephyr/net_buf.h
     - lib/net_buf/
     - tests/lib/net_buf/
@@ -3048,7 +3085,7 @@ Networking:
   collaborators:
     - pdgendt
     - canisLupus1313
-    - mariuszpos
+    - kkasperczyk-no
     - edmont
     - maciejbaczmanski
   files:
@@ -3141,6 +3178,9 @@ Open AMP:
   status: maintained
   maintainers:
     - carlocaione
+  collaborators:
+    - uLipe
+    - iuliana-prodan
   files:
     - lib/open-amp/
     - samples/subsys/ipc/openamp/
@@ -3163,6 +3203,20 @@ PHYTEC Platforms:
   labels:
     - "platform: PHYTEC"
 
+PMCI:
+  status: maintained
+  maintainers:
+    - teburd
+  collaborators:
+    - nashif
+    - inteljiangwe1
+    - kehintel
+  files:
+    - subsys/pmci/
+    - samples/modules/pmci/
+  labels:
+    - "area: PMCI"
+
 POSIX API layer:
   status: maintained
   maintainers:
@@ -3227,6 +3281,7 @@ RISCV arch:
     - carlocaione
     - npitre
     - ycsin
+    - VynDragon
   files:
     - arch/riscv/
     - boards/enjoydigital/litex_vexriscv/
@@ -3336,7 +3391,7 @@ Settings:
     - subsys/settings/
     - tests/subsys/settings/
     - samples/subsys/settings/
-    - doc/services/settings/
+    - doc/services/storage/settings/
   labels:
     - "area: Settings"
   tests:
@@ -3424,26 +3479,44 @@ ADI Platforms:
   collaborators:
     - ozersa
     - ttmut
+    - yasinustunerg
     - galak
     - microbuilder
   files:
     - boards/adi/
+    - boards/shields/eval*ardz/
     - boards/shields/pmod_acl/
     - drivers/*/*max*
     - drivers/*/*max*/
     - drivers/dac/dac_ltc*
     - drivers/ethernet/eth_adin*
+    - drivers/ethernet/phy/phy_adin*
     - drivers/mdio/mdio_adin*
-    - drivers/regulator/regulator_adp5360*
     - drivers/sensor/adi/
+    - drivers/stepper/adi_tmc/
     - dts/arm/adi/
     - dts/bindings/*/adi,*
     - dts/bindings/*/lltc,*
     - dts/bindings/*/maxim,*
     - soc/adi/
+  files-regex:
+    - ^drivers/(adc|dac|gpio|mfd|regulator)/.*adp?\d+
   labels:
     - "platform: ADI"
 
+Bouffalolab Platforms:
+  status: maintained
+  maintainers:
+    - nandojve
+  files:
+    - boards/bouffalolab/
+    - drivers/*/*bflb*
+    - dts/riscv/bouffalolab/
+    - dts/bindings/*/bflb,*
+    - soc/bouffalolab/
+  labels:
+    - "platform: bouffalolab"
+
 Broadcom Platforms:
   status: odd fixes
   files:
@@ -3456,7 +3529,6 @@ GD32 Platforms:
   maintainers:
     - nandojve
   collaborators:
-    - gmarull
     - soburi
     - cameled
   files:
@@ -3553,10 +3625,18 @@ Raspberry Pi Pico Platforms:
     - soburi
   collaborators:
     - yonsch
+    - threeeights
+    - ajf58
   files:
-    - boards/raspberrypi/
+    - boards/raspberrypi/rpi_pico*/
     - boards/adafruit/kb2040/
+    - boards/adafruit/macropad_rp2040/
+    - boards/adafruit/qt_py_rp2040/
+    - boards/pimoroni/pico_plus2/
+    - boards/seeed/xiao_rp2040/
     - boards/sparkfun/pro_micro_rp2040/
+    - boards/waveshare/rp2040_zero/
+    - boards/wiznet/w5500_evb_pico*/
     - dts/arm/raspberrypi/rpi_pico/
     - dts/bindings/*/raspberrypi,pico*
     - drivers/*/*rpi_pico
@@ -3570,17 +3650,21 @@ Silabs Platforms:
   status: maintained
   maintainers:
     - jhedberg
+    - asmellby
   collaborators:
     - jerome-pouiller
-    - asmellby
+    - Martinhoff-maker
   files:
     - soc/silabs/
     - boards/silabs/
     - dts/arm/silabs/
     - dts/bindings/*/silabs*
     - drivers/*/*gecko*
-    - drivers/bluetooth/hci/hci_silabs_*
     - drivers/*/*silabs*
+    - drivers/*/*siwx91x*
+    - drivers/*/*/*silabs*
+    - drivers/*/*/*siwx91x*
+    - tests/boards/silabs/
   labels:
     - "platform: Silabs"
 
@@ -3710,6 +3794,7 @@ NXP Drivers:
     - decsny
     - manuargue
     - dbaluta
+    - Raymond0225
   files-regex:
     - ^drivers/.*nxp.*
     - ^drivers/.*mcux.*
@@ -3727,18 +3812,34 @@ NXP Drivers:
     - include/zephyr/dt-bindings/inputmux/
     - include/zephyr/dt-bindings/rdc/
     - include/zephyr/drivers/*/*nxp*
+    - include/zephyr/drivers/*/*nxp*/
     - include/zephyr/drivers/*/*mcux*
     - arch/arm/core/mpu/nxp_mpu.c
     - dts/bindings/*/nxp*
   files-exclude:
-    - drivers/wifi/nxp/
-    - drivers/usb/*/*mcux*
+    - drivers/wifi/
+    - drivers/bluetooth/
+    - drivers/usb/
   files-regex-exclude:
     - .*s32.*
   labels:
     - "platform: NXP Drivers"
   description: NXP Drivers
 
+NXP Wireless:
+  status: maintained
+  maintainers:
+    - dleach02
+  collaborators:
+    - MaochenWang1
+    - axelnxp
+  files:
+    - drivers/wifi/nxp/
+    - drivers/bluetooth/hci/*nxp*
+    - drivers/ieee802154/ieee802154_kw41z.c
+  labels:
+    - "platform: NXP Drivers"
+
 NXP MCUX USB:
   status: maintained
   maintainers:
@@ -3746,6 +3847,7 @@ NXP MCUX USB:
     - MarkWangChinese
   files:
     - drivers/usb/*/*mcux*
+    - boards/nxp/usb_kw24d512/
   labels:
     - "platform: NXP Drivers"
   description: NXP MCUX USB shim drivers
@@ -3757,7 +3859,6 @@ NXP Platforms (MCU):
     - mmahadevan108
   collaborators:
     - DerekSnell
-    - yvanderv
     - EmilioCBen
     - decsny
     - butok
@@ -3766,8 +3867,11 @@ NXP Platforms (MCU):
     - boards/nxp/frdm*/
     - boards/nxp/lpcxpress*/
     - boards/nxp/twr_*/
-    - boards/nxp/vmu*/
     - boards/nxp/*rw*/
+    - boards/nxp/hexiwear/
+    - boards/nxp/common/
+    - boards/nxp/*
+    - soc/nxp/common/
     - soc/nxp/imxrt/
     - soc/nxp/kinetis/
     - soc/nxp/lpc/
@@ -3788,13 +3892,9 @@ NXP Platforms (S32):
   maintainers:
     - manuargue
   collaborators:
-    - PetervdPerk-NXP
-    - bperseghetti
     - Dat-NguyenDuy
   files:
-    - boards/nxp/s32*/
-    - boards/nxp/mr_canhubk3/
-    - boards/nxp/ucans32k1sic/
+    - boards/nxp/*s32*/
     - boards/common/*nxp_s32*
     - soc/nxp/s32/
     - drivers/*/*nxp_s32*
@@ -3817,12 +3917,12 @@ NXP Platforms (MPU):
     - dleach02
     - dbaluta
     - iuliana-prodan
-    - yvanderv
   files:
     - dts/arm64/nxp/
     - dts/arm/nxp/nxp_imx*
     - soc/nxp/imx/
     - soc/nxp/layerscape/
+    - boards/nxp/ls1046ardb/
   files-regex:
     - boards/nxp/m?imx[^(rt)].*/
   labels:
@@ -3842,6 +3942,19 @@ NXP Platforms (Xtensa):
     - "platform: NXP Xtensa"
   description: NXP Xtensa platforms
 
+NXP Platforms (Robotics Products):
+  status: maintained
+  maintainers:
+    - bperseghetti
+    - PetervdPerk-NXP
+  files:
+    - boards/nxp/vmu*/
+    - boards/nxp/rddrone_fmuk66/
+    - boards/nxp/mr_canhubk3/
+  labels:
+    - "platform: NXP Robotics"
+  description: NXP Robotics Module Platform Products
+
 Microchip MEC Platforms:
   status: maintained
   maintainers:
@@ -3916,6 +4029,19 @@ nRF Platforms:
   labels:
     - "platform: nRF"
 
+Octavo Systems Platforms:
+  status: maintained
+  maintainers:
+    - fkokosinski
+    - tgorochowik
+  collaborators:
+    - kgugala
+  files:
+    - boards/oct/
+    - soc/oct/
+  labels:
+    - "platform: Octavo Systems"
+
 OpenTitan Platforms:
   status: maintained
   maintainers:
@@ -3973,6 +4099,7 @@ Renesas RA Platforms:
   collaborators:
     - duynguyenxa
     - thaoluonguw
+    - thenguyenyf
   files:
     - boards/arduino/uno_r4/
     - boards/renesas/*ra*/
@@ -3981,6 +4108,7 @@ Renesas RA Platforms:
     - dts/arm/renesas/ra/
     - dts/bindings/*/*renesas,ra*
     - soc/renesas/ra/
+    - samples/boards/renesas/
   labels:
     - "platform: Renesas RA"
   description: >-
@@ -3991,13 +4119,18 @@ Renesas RZ Platforms:
   status: maintained
   maintainers:
     - tgorochowik
+    - binhnguyen2434
+  collaborators:
+    - nhutnguyenkc
   files:
-    - boards/renesas/rzt2m_*/
+    - boards/renesas/rz*/
     - drivers/*/*rzt2m*
+    - drivers/*/*renesas_rz*
     - drivers/pinctrl/renesas/rz/
     - dts/arm/renesas/rz/
     - dts/bindings/*/*rzt2m*
-    - soc/renesas/rzt2m/
+    - dts/bindings/*/*renesas,rz*
+    - soc/renesas/rz/
   labels:
     - "platforms: Renesas RZ"
   description: >-
@@ -4080,6 +4213,17 @@ STM32 Wireless Platforms:
     STM32WB SOCs, dts files and related drivers. STM32WB development boards
     and ST bluetooth shields.
 
+Enclustra Platforms:
+  status: maintained
+  maintainers:
+    - fkokosinski
+  collaborators:
+    - tgorochowik
+  files:
+    - boards/enclustra/
+  labels:
+    - "platform: Enclustra"
+
 Espressif Platforms:
   status: maintained
   maintainers:
@@ -4153,8 +4297,11 @@ TI K3 Platforms:
   collaborators:
     - gramsay0
     - dnltz
+    - glneo
   files:
     - boards/ti/*am62*/
+    - drivers/*/*davinci*
+    - drivers/*/*omap*
     - drivers/*/*ti_k3*
     - dts/bindings/*/ti,k3*
     - soc/ti/k3/
@@ -4266,13 +4413,24 @@ Secure storage:
     - subsys/secure_storage/
     - include/zephyr/psa/
     - samples/psa/
-    - doc/services/secure_storage.rst
+    - doc/services/storage/secure_storage/index.rst
     - tests/subsys/secure_storage/
   labels:
     - "area: Secure storage"
   tests:
     - psa.secure_storage
 
+Sensry Platforms:
+  status: maintained
+  maintainers:
+    - tswaehn
+  files:
+    - boards/sensry/
+  files-regex:
+    - .*sy1xx.*
+  labels:
+    - "platform: sensry"
+
 Storage:
   status: odd fixes
   files:
@@ -4340,8 +4498,13 @@ Task Watchdog:
 TDK Sensors:
   status: maintained
   maintainers:
+    - afontaine-invn
+    - rbuisson-invn
+  collaborators:
     - teburd
     - MaureenHelm
+    - sriccardi-invn
+    - gjabouley-invn
   files:
     - drivers/sensor/tdk/
   labels:
@@ -4404,6 +4567,18 @@ TDK Sensors:
   labels:
     - "area: Toolchains"
 
+"Toolchain IAR":
+  status: maintained
+  maintainers:
+    - RobinKastberg
+  files:
+    - cmake/*/iar/
+    - include/zephyr/toolchain/iar.h
+    - include/zephyr/toolchain/iar/*
+    - lib/libc/iar/*
+  labels:
+    - "area: Toolchains"
+
 "Toolchain oneApi":
   status: maintained
   maintainers:
@@ -4702,10 +4877,10 @@ West:
 "West project: cmsis_6":
   status: maintained
   maintainers:
-    - ithinuel
+    - wearyzen
   collaborators:
     - tomi-font
-    - wearyzen
+    - ithinuel
   files: []
   labels:
     - "area: CMSIS_6"
@@ -4737,6 +4912,7 @@ West:
   collaborators:
     - ozersa
     - ttmut
+    - yasinustunerg
   files: []
   labels:
     - "platform: ADI"
@@ -4772,6 +4948,15 @@ West:
   labels:
     - "platform: Microchip SAM"
 
+"West project: hal_bouffalolab":
+  status: maintained
+  maintainers:
+    - nandojve
+  files:
+    - modules/hal_bouffalolab/
+  labels:
+    - "platform: Bouffalo Lab"
+
 "West project: hal_cypress":
   status: maintained
   maintainers:
@@ -4800,9 +4985,9 @@ West:
   status: maintained
   maintainers:
     - kristofer-jonsson-arm
-    - ithinuel
-  collaborators:
     - wearyzen
+  collaborators:
+    - ithinuel
   files:
     - drivers/misc/ethos_u/
     - modules/hal_ethos_u/
@@ -4814,7 +4999,6 @@ West:
   maintainers:
     - nandojve
   collaborators:
-    - gmarull
     - soburi
   files:
     - modules/hal_gigadevice/
@@ -4881,9 +5065,6 @@ West:
     - bperseghetti
   files:
     - modules/hal_nxp/
-    - modules/Kconfig.imx
-    - modules/Kconfig.mcux
-    - modules/Kconfig.nxp_s32
   labels:
     - "platform: NXP"
 
@@ -4926,6 +5107,8 @@ West:
     - soburi
   collaborators:
     - yonsch
+    - threeeights
+    - ajf58
   files:
     - modules/hal_rpi_pico/
   labels:
@@ -4935,13 +5118,14 @@ West:
   status: maintained
   maintainers:
     - jhedberg
+    - asmellby
   collaborators:
     - jerome-pouiller
-    - asmellby
     - sateeshkotapati
     - yonsch
     - mnkp
     - rettichschnidi
+    - Martinhoff-maker
   files:
     - modules/hal_silabs/
   labels:
@@ -5005,6 +5189,8 @@ West:
   maintainers:
     - nzmichaelh
     - kholia
+  collaborators:
+    - VynDragon
   files:
     - modules/hal_wch/
 
@@ -5047,6 +5233,17 @@ West:
   labels:
     - "area: Rust"
 
+"West project: libmctp":
+  status: maintained
+  maintainers:
+    - teburd
+  collaborators:
+    - nashif
+    - inteljiangwe1
+  files: []
+  labels:
+    - "area: MCTP"
+
 "West project: libmetal":
   status: odd fixes
   collaborators:
@@ -5117,10 +5314,10 @@ West:
     - d3zd3z
     - ceolin
   collaborators:
-    - ithinuel
     - wearyzen
     - valeriosetti
     - tomi-font
+    - ithinuel
   files:
     - modules/mbedtls/
     - tests/crypto/mbedtls/
@@ -5204,6 +5401,8 @@ West:
   status: odd fixes
   collaborators:
     - carlocaione
+    - uLipe
+    - iuliana-prodan
   files:
     - modules/Kconfig.open-amp
   labels:
@@ -5270,7 +5469,9 @@ West:
     - "area: Audio"
 
 "West project: tflite-micro":
-  status: odd fixes
+  status: maintained
+  maintainers:
+    - XenuIsWatching
   collaborators:
     - laurenmurphyx64
   files:
@@ -5306,10 +5507,10 @@ West:
     - d3zd3z
   collaborators:
     - Vge0rge
-    - ithinuel
     - wearyzen
     - valeriosetti
     - tomi-font
+    - ithinuel
   files:
     - modules/trusted-firmware-m/
     - samples/tfm_integration/
@@ -5326,8 +5527,8 @@ West:
     - d3zd3z
   collaborators:
     - Vge0rge
-    - ithinuel
     - wearyzen
+    - ithinuel
   files: []
   labels:
     - "area: TF-M"
@@ -5339,8 +5540,8 @@ West:
     - sgrrzhf
   collaborators:
     - carlocaione
-    - ithinuel
     - wearyzen
+    - ithinuel
   files:
     - modules/trusted-firmware-a/
   labels:
@@ -5352,8 +5553,8 @@ West:
     - d3zd3z
   collaborators:
     - Vge0rge
-    - ithinuel
     - wearyzen
+    - ithinuel
   files: []
   labels:
     - "area: TF-M"
@@ -5516,6 +5717,31 @@ Random:
   labels:
     - "area: Random"
 
+Peregrine Platforms:
+  status: maintained
+  maintainers:
+    - nandojve
+  files:
+    - boards/peregrine/
+  labels:
+    - "platform: Peregrine"
+
+WCH Platforms:
+  status: maintained
+  maintainers:
+    - nzmichaelh
+    - kholia
+  collaborators:
+    - VynDragon
+  files:
+    - boards/wch/
+    - dts/riscv/wch/
+    - soc/wch/
+    - drivers/*/*wch*
+    - dts/bindings/*/wch,*
+  labels:
+    - "platform: WinChipHead"
+
 # This area is to be converted to a subarea
 Testing with Renode:
   status: odd fixes
@@ -5526,8 +5752,8 @@ Testing with Renode:
     - cmake/emu/renode.cmake
     - soc/renode/
     - boards/renode/
-    - boards/**/*/support/*.repl
-    - boards/**/*/support/*.resc
+    - boards/*/*/support/*.repl
+    - boards/*/*/support/*.resc
   labels:
     - "area: Renode"
 
@@ -5557,6 +5783,7 @@ zbus:
     - cmake/llext-edk.cmake
     - samples/subsys/llext/
     - include/zephyr/llext/
+    - tests/misc/llext-edk/
     - tests/subsys/llext/
     - subsys/llext/
     - doc/services/llext/
diff --git a/VERSION b/VERSION
index b170abf44be..9749142466b 100644
--- a/VERSION
+++ b/VERSION
@@ -1,5 +1,5 @@
 VERSION_MAJOR = 4
-VERSION_MINOR = 0
+VERSION_MINOR = 1
 PATCHLEVEL = 99
 VERSION_TWEAK = 0
 EXTRAVERSION =
diff --git a/arch/Kconfig b/arch/Kconfig
index 94e9a540a08..916351ae605 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -8,7 +8,7 @@
 # Include these first so that any properties (e.g. defaults) below can be
 # overridden (by defining symbols in multiple locations)
 
-source "$(ARCH_DIR)/Kconfig.$(HWM_SCHEME)"
+source "$(KCONFIG_BINARY_DIR)/arch/Kconfig"
 
 # ToDo: Generate a Kconfig.arch for loading of additional arch in HWMv2.
 osource "$(KCONFIG_BINARY_DIR)/Kconfig.arch"
@@ -317,7 +317,7 @@ config PRIVILEGED_STACK_SIZE
 	int "Size of privileged stack"
 	default 2048 if EMUL
 	default 1024
-	depends on ARCH_HAS_USERSPACE
+	depends on USERSPACE
 	help
 	  This option sets the privileged stack region size that will be used
 	  in addition to the user mode thread stack.  During normal execution,
@@ -331,14 +331,14 @@ config KOBJECT_TEXT_AREA
 	default 512 if NO_OPTIMIZATIONS
 	default 512 if STACK_CANARIES && RISCV
 	default 256
-	depends on ARCH_HAS_USERSPACE
+	depends on USERSPACE
 	help
 	  Size of kernel object text area. Used in linker script.
 
 config KOBJECT_DATA_AREA_RESERVE_EXTRA_PERCENT
 	int "Reserve extra kobject data area (in percentage)"
 	default 100
-	depends on ARCH_HAS_USERSPACE
+	depends on USERSPACE
 	help
 	  Multiplication factor used to calculate the size of placeholder to
 	  reserve space for kobject metadata hash table. The hash table is
@@ -352,7 +352,7 @@ config KOBJECT_DATA_AREA_RESERVE_EXTRA_PERCENT
 config KOBJECT_RODATA_AREA_EXTRA_BYTES
 	int "Reserve extra bytes for kobject rodata area"
 	default 16
-	depends on ARCH_HAS_USERSPACE
+	depends on USERSPACE
 	help
 	  Reserve a few more bytes for the RODATA region for kobject metadata.
 	  This is to account for the uncertainty of tables generated by gperf.
@@ -573,6 +573,15 @@ config IRQ_OFFLOAD
 	  run in interrupt context. Only useful for test cases that need
 	  to validate the correctness of kernel objects in IRQ context.
 
+config SRAM_VECTOR_TABLE
+	bool "Place the vector table in SRAM instead of flash"
+	depends on ARCH_HAS_VECTOR_TABLE_RELOCATION
+	depends on XIP
+	depends on !ROMSTART_RELOCATION_ROM
+	help
+	  When XiP is enabled, this option will result in the vector table being
+	  relocated from Flash to SRAM.
+
 config IRQ_OFFLOAD_NESTED
 	bool "irq_offload() supports nested IRQs"
 	depends on IRQ_OFFLOAD
@@ -671,6 +680,9 @@ config ARCH_HAS_NOCACHE_MEMORY_SUPPORT
 config ARCH_HAS_RAMFUNC_SUPPORT
 	bool
 
+config ARCH_HAS_VECTOR_TABLE_RELOCATION
+	bool
+
 config ARCH_HAS_NESTED_EXCEPTION_DETECTION
 	bool
 
@@ -1134,9 +1146,9 @@ config ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
 config ARCH_HAS_CUSTOM_SWAP_TO_MAIN
 	bool
 	help
-	  It's possible that an architecture port cannot use _Swap() to swap to
-	  the _main() thread, but instead must do something custom. It must
-	  enable this option in that case.
+	  It's possible that an architecture port cannot use z_swap_unlocked()
+	  to swap to the main thread (bg_thread_main), but instead must do
+	  something custom. It must enable this option in that case.
 
 config ARCH_HAS_CUSTOM_BUSY_WAIT
 	bool
diff --git a/arch/Kconfig.v1 b/arch/Kconfig.v1
deleted file mode 100644
index d76acba59a3..00000000000
--- a/arch/Kconfig.v1
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright (c) 2023 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-# Note: $ARCH might be a glob pattern
-source "$(ARCH_DIR)/$(ARCH)/Kconfig"
diff --git a/arch/Kconfig.v2 b/arch/Kconfig.v2
deleted file mode 100644
index 19db8d46246..00000000000
--- a/arch/Kconfig.v2
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright (c) 2023 Nordic Semiconductor ASA
-
-# SPDX-License-Identifier: Apache-2.0
-
-source "$(KCONFIG_BINARY_DIR)/arch/Kconfig"
diff --git a/arch/arc/arcmwdt/arcmwdt-dtr-stubs.c b/arch/arc/arcmwdt/arcmwdt-dtr-stubs.c
index 6ba748b3455..f33bd638d77 100644
--- a/arch/arc/arcmwdt/arcmwdt-dtr-stubs.c
+++ b/arch/arc/arcmwdt/arcmwdt-dtr-stubs.c
@@ -8,14 +8,6 @@
 
 __weak void *__dso_handle;
 
-int __cxa_atexit(void (*destructor)(void *), void *objptr, void *dso)
-{
-	ARG_UNUSED(destructor);
-	ARG_UNUSED(objptr);
-	ARG_UNUSED(dso);
-	return 0;
-}
-
 int atexit(void (*function)(void))
 {
 	return 0;
diff --git a/arch/arc/core/elf.c b/arch/arc/core/elf.c
index 9f9f1073431..db2a74e164e 100644
--- a/arch/arc/core/elf.c
+++ b/arch/arc/core/elf.c
@@ -6,6 +6,7 @@
 
 #include <zephyr/llext/elf.h>
 #include <zephyr/llext/llext.h>
+#include <zephyr/llext/llext_internal.h>
 #include <zephyr/llext/loader.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/sys/util.h>
@@ -31,12 +32,32 @@ LOG_MODULE_REGISTER(elf, CONFIG_LLEXT_LOG_LEVEL);
  * https://github.com/foss-for-synopsys-dwc-arc-processors/arc-ABI-manual/blob/master/ARCv2_ABI.pdf
  * https://github.com/zephyrproject-rtos/binutils-gdb
  */
-int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc, uintptr_t sym_base_addr, const char *sym_name,
-		      uintptr_t load_bias)
+int arch_elf_relocate(struct llext_loader *ldr, struct llext *ext, elf_rela_t *rel,
+		      const elf_shdr_t *shdr)
 {
 	int ret = 0;
-	uint32_t insn = UNALIGNED_GET((uint32_t *)loc);
 	uint32_t value;
+	const uintptr_t loc = llext_get_reloc_instruction_location(ldr, ext, shdr->sh_info, rel);
+	uint32_t insn = UNALIGNED_GET((uint32_t *)loc);
+	elf_sym_t sym;
+	uintptr_t sym_base_addr;
+	const char *sym_name;
+
+	ret = llext_read_symbol(ldr, ext, rel, &sym);
+
+	if (ret != 0) {
+		LOG_ERR("Could not read symbol from binary!");
+		return ret;
+	}
+
+	sym_name = llext_symbol_name(ldr, ext, &sym);
+
+	ret = llext_lookup_symbol(ldr, ext, &sym_base_addr, rel, &sym, sym_name, shdr);
+
+	if (ret != 0) {
+		LOG_ERR("Could not find symbol %s!", sym_name);
+		return ret;
+	}
 
 	sym_base_addr += rel->r_addend;
 
diff --git a/arch/arc/core/fault.c b/arch/arc/core/fault.c
index 6f9da3cd1e0..adbd6da12bb 100644
--- a/arch/arc/core/fault.c
+++ b/arch/arc/core/fault.c
@@ -346,7 +346,7 @@ static void dump_exception_info(uint32_t vector, uint32_t cause, uint32_t parame
  * invokes the user provided routine k_sys_fatal_error_handler() which is
  * responsible for implementing the error handling policy.
  */
-void _Fault(struct arch_esf *esf, uint32_t old_sp)
+void z_arc_fault(struct arch_esf *esf, uint32_t old_sp)
 {
 	uint32_t vector, cause, parameter;
 	uint32_t exc_addr = z_arc_v2_aux_reg_read(_ARC_V2_EFA);
diff --git a/arch/arc/core/fault_s.S b/arch/arc/core/fault_s.S
index d89f3fe6a82..69fb03082a5 100644
--- a/arch/arc/core/fault_s.S
+++ b/arch/arc/core/fault_s.S
@@ -19,7 +19,7 @@
 #include <zephyr/syscall.h>
 #include <zephyr/arch/arc/asm-compat/assembler.h>
 
-GTEXT(_Fault)
+GTEXT(z_arc_fault)
 GTEXT(__reset)
 GTEXT(__memory_error)
 GTEXT(__instruction_error)
@@ -99,11 +99,11 @@ _exc_entry:
 
 	_save_exc_regs_into_stack
 
-	/* sp is parameter of _Fault */
+	/* sp is parameter of z_arc_fault */
 	MOVR r0, sp
 	/* ilink is the thread's original sp */
 	MOVR r1, ilink
-	jl _Fault
+	jl z_arc_fault
 
 _exc_return:
 /* the exception cause must be fixed in exception handler when exception returns
diff --git a/arch/arm/core/Kconfig b/arch/arm/core/Kconfig
index 2573ca2cac6..5505eee4e19 100644
--- a/arch/arm/core/Kconfig
+++ b/arch/arm/core/Kconfig
@@ -16,6 +16,7 @@ config CPU_CORTEX_M
 	select ARCH_HAS_USERSPACE if ARM_MPU
 	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MPU && CPU_HAS_ARM_MPU && CPU_HAS_DCACHE
 	select ARCH_HAS_RAMFUNC_SUPPORT
+	select ARCH_HAS_VECTOR_TABLE_RELOCATION if CPU_CORTEX_M_HAS_VTOR
 	select ARCH_HAS_NESTED_EXCEPTION_DETECTION
 	select SWAP_NONATOMIC
 	select ARCH_HAS_EXTRA_EXCEPTION_INFO
diff --git a/arch/arm/core/cortex_a_r/Kconfig b/arch/arm/core/cortex_a_r/Kconfig
index 409968ca6c7..a6176bbe5c0 100644
--- a/arch/arm/core/cortex_a_r/Kconfig
+++ b/arch/arm/core/cortex_a_r/Kconfig
@@ -13,6 +13,15 @@
 # CPU_AARCH32_CORTEX_A / if CPU_AARCH32_CORTEX_R blocks so they are not
 # exposed if one selects a different ARM Cortex Family (Cortex-M).
 
+config CPU_CORTEX_A7
+	bool
+	select CPU_AARCH32_CORTEX_A
+	select ARMV7_A
+	select CPU_HAS_ICACHE
+	select CPU_HAS_DCACHE
+	help
+	  This option signifies the use of a Cortex-A7 CPU.
+
 config CPU_CORTEX_A9
 	bool
 	select CPU_AARCH32_CORTEX_A
@@ -82,6 +91,8 @@ config CPU_CORTEX_R5
 	select CPU_AARCH32_CORTEX_R
 	select ARMV7_R
 	select ARMV7_R_FP if CPU_HAS_FPU
+	select CPU_HAS_ICACHE
+	select CPU_HAS_DCACHE
 	help
 	  This option signifies the use of a Cortex-R5 CPU
 
diff --git a/arch/arm/core/cortex_a_r/cache.c b/arch/arm/core/cortex_a_r/cache.c
index 31cf27a08e6..07c5b32bf32 100644
--- a/arch/arm/core/cortex_a_r/cache.c
+++ b/arch/arm/core/cortex_a_r/cache.c
@@ -208,7 +208,13 @@ int arch_icache_flush_range(void *start_addr, size_t size)
 
 int arch_icache_invd_range(void *start_addr, size_t size)
 {
-	return -ENOTSUP;
+	/* Cortex A/R do have the ICIMVAU operation to selectively invalidate
+	 * the instruction cache, but not currently supported by CMSIS.
+	 * For now, invalidate the entire cache.
+	 */
+	L1C_InvalidateICacheAll();
+
+	return 0;
 }
 
 int arch_icache_flush_and_invd_range(void *start_addr, size_t size)
diff --git a/arch/arm/core/cortex_a_r/exc.S b/arch/arm/core/cortex_a_r/exc.S
index 78414fcd0a1..ecf7bab57f0 100644
--- a/arch/arm/core/cortex_a_r/exc.S
+++ b/arch/arm/core/cortex_a_r/exc.S
@@ -237,6 +237,28 @@ SECTION_SUBSEC_FUNC(TEXT, __exc, z_arm_data_abort)
 	b z_arm_exc_exit
 
 #else
+
+GTEXT(z_arm_cortex_ar_exit_exc)
+SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_cortex_ar_exit_exc)
+
+	/* Note:
+	 * This function is expected to be *always* called with
+	 * processor mode set to MODE_SYS.
+	 */
+
+	/* decrement exception depth */
+	get_cpu r2
+	ldrb r1, [r2, #_cpu_offset_to_exc_depth]
+	sub r1, r1, #1
+	strb r1, [r2, #_cpu_offset_to_exc_depth]
+
+	/*
+	 * Restore r0-r3, r12, lr, lr_und and spsr_und from the exception stack
+	 * and return to the current thread.
+	 */
+	pop {r0-r3, r12, lr}
+	rfeia sp!
+
 /**
  * @brief Undefined instruction exception handler
  *
diff --git a/arch/arm/core/cortex_a_r/fault.c b/arch/arm/core/cortex_a_r/fault.c
index daf1d2345ca..eac07cbf9b2 100644
--- a/arch/arm/core/cortex_a_r/fault.c
+++ b/arch/arm/core/cortex_a_r/fault.c
@@ -100,6 +100,59 @@ static uint32_t dump_fault(uint32_t status, uint32_t addr)
 		reason = K_ERR_ARM_UNSUPPORTED_EXCLUSIVE_ACCESS_FAULT;
 		LOG_ERR("Unsupported Exclusive Access Fault @ 0x%08x", addr);
 		break;
+#elif defined(CONFIG_ARMV7_A)
+	case FSR_FS_PERMISSION_FAULT_2ND_LEVEL:
+		reason = K_ERR_ARM_PERMISSION_FAULT_2ND_LEVEL;
+		LOG_ERR("2nd Level Permission Fault @ 0x%08x", addr);
+		break;
+	case FSR_FS_ACCESS_FLAG_FAULT_1ST_LEVEL:
+		reason = K_ERR_ARM_ACCESS_FLAG_FAULT_1ST_LEVEL;
+		LOG_ERR("1st Level Access Flag Fault @ 0x%08x", addr);
+		break;
+	case FSR_FS_ACCESS_FLAG_FAULT_2ND_LEVEL:
+		reason = K_ERR_ARM_ACCESS_FLAG_FAULT_2ND_LEVEL;
+		LOG_ERR("2nd Level Access Flag Fault @ 0x%08x", addr);
+		break;
+	case FSR_FS_CACHE_MAINTENANCE_INSTRUCTION_FAULT:
+		reason = K_ERR_ARM_CACHE_MAINTENANCE_INSTRUCTION_FAULT;
+		LOG_ERR("Cache Maintenance Instruction Fault @ 0x%08x", addr);
+		break;
+	case FSR_FS_TRANSLATION_FAULT:
+		reason = K_ERR_ARM_TRANSLATION_FAULT;
+		LOG_ERR("1st Level Translation Fault @ 0x%08x", addr);
+		break;
+	case FSR_FS_TRANSLATION_FAULT_2ND_LEVEL:
+		reason = K_ERR_ARM_TRANSLATION_FAULT_2ND_LEVEL;
+		LOG_ERR("2nd Level Translation Fault @ 0x%08x", addr);
+		break;
+	case FSR_FS_DOMAIN_FAULT_1ST_LEVEL:
+		reason = K_ERR_ARM_DOMAIN_FAULT_1ST_LEVEL;
+		LOG_ERR("1st Level Domain Fault @ 0x%08x", addr);
+		break;
+	case FSR_FS_DOMAIN_FAULT_2ND_LEVEL:
+		reason = K_ERR_ARM_DOMAIN_FAULT_2ND_LEVEL;
+		LOG_ERR("2nd Level Domain Fault @ 0x%08x", addr);
+		break;
+	case FSR_FS_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_1ST_LEVEL:
+		reason = K_ERR_ARM_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_1ST_LEVEL;
+		LOG_ERR("1st Level Synchronous External Abort Translation Table @ 0x%08x", addr);
+		break;
+	case FSR_FS_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_2ND_LEVEL:
+		reason = K_ERR_ARM_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_2ND_LEVEL;
+		LOG_ERR("2nd Level Synchronous External Abort Translation Table @ 0x%08x", addr);
+		break;
+	case FSR_FS_TLB_CONFLICT_FAULT:
+		reason = K_ERR_ARM_TLB_CONFLICT_FAULT;
+		LOG_ERR("Table Conflict Fault @ 0x%08x", addr);
+		break;
+	case FSR_FS_SYNC_PARITY_ERROR_TRANSLATION_TABLE_1ST_LEVEL:
+		reason = K_ERR_ARM_SYNC_PARITY_ERROR_TRANSLATION_TABLE_1ST_LEVEL;
+		LOG_ERR("1st Level Synchronous Parity Error Translation Table @ 0x%08x", addr);
+		break;
+	case FSR_FS_SYNC_PARITY_ERROR_TRANSLATION_TABLE_2ND_LEVEL:
+		reason = K_ERR_ARM_SYNC_PARITY_ERROR_TRANSLATION_TABLE_2ND_LEVEL;
+		LOG_ERR("2nd Level Synchronous Parity Error Translation Table @ 0x%08x", addr);
+		break;
 #else
 	case FSR_FS_BACKGROUND_FAULT:
 		reason = K_ERR_ARM_BACKGROUND_FAULT;
diff --git a/arch/arm/core/cortex_a_r/irq_manage.c b/arch/arm/core/cortex_a_r/irq_manage.c
index 48c9ede3327..5303d1d7178 100644
--- a/arch/arm/core/cortex_a_r/irq_manage.c
+++ b/arch/arm/core/cortex_a_r/irq_manage.c
@@ -33,6 +33,14 @@ extern void z_arm_reserved(void);
  * Generic Interrupt Controller (GIC) and therefore the architecture interrupt
  * control functions are mapped to the GIC driver interface.
  *
+ * When GIC is used together with other interrupt controller for
+ * multi-level interrupts support (i.e. CONFIG_MULTI_LEVEL_INTERRUPTS
+ * is enabled), the architecture interrupt control functions are mapped
+ * to the SoC layer in `include/arch/arm/irq.h`.
+ * The exported arm interrupt control functions which are wrappers of
+ * GIC control could be used for SoC to do level 1 irq control to implement SoC
+ * layer interrupt control functions.
+ *
  * When a custom interrupt controller is used (i.e.
  * CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER is enabled), the architecture
  * interrupt control functions are mapped to the SoC layer in
@@ -40,17 +48,17 @@ extern void z_arm_reserved(void);
  */
 
 #if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
-void arch_irq_enable(unsigned int irq)
+void arm_irq_enable(unsigned int irq)
 {
 	arm_gic_irq_enable(irq);
 }
 
-void arch_irq_disable(unsigned int irq)
+void arm_irq_disable(unsigned int irq)
 {
 	arm_gic_irq_disable(irq);
 }
 
-int arch_irq_is_enabled(unsigned int irq)
+int arm_irq_is_enabled(unsigned int irq)
 {
 	return arm_gic_irq_is_enabled(irq);
 }
@@ -65,10 +73,11 @@ int arch_irq_is_enabled(unsigned int irq)
  * priority levels which are reserved: three for various types of exceptions,
  * and possibly one additional to support zero latency interrupts.
  */
-void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
+void arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 {
 	arm_gic_irq_set_priority(irq, prio, flags);
 }
+
 #endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */
 
 void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf);
diff --git a/arch/arm/core/cortex_a_r/reboot.c b/arch/arm/core/cortex_a_r/reboot.c
index b5cea619f09..d721baceda2 100644
--- a/arch/arm/core/cortex_a_r/reboot.c
+++ b/arch/arm/core/cortex_a_r/reboot.c
@@ -28,16 +28,13 @@ static inline void relocate_vector_table(void)
 
 #else
 
-#if defined(__GNUC__)
 /*
  * GCC can detect if memcpy is passed a NULL argument, however one of
  * the cases of relocate_vector_table() it is valid to pass NULL, so we
  * suppress the warning for this case.  We need to do this before
  * string.h is included to get the declaration of memcpy.
  */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wnonnull"
-#endif /* __GNUC__ */
+TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_NONNULL)
 
 #include <string.h>
 
@@ -53,9 +50,7 @@ void __weak relocate_vector_table(void)
 #endif
 }
 
-#if defined(__GNUC__)
-#pragma GCC diagnostic pop
-#endif
+TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_NONNULL)
 
 #endif /* !CONFIG_AARCH32_ARMV8_R */
 
diff --git a/arch/arm/core/cortex_a_r/semihost.c b/arch/arm/core/cortex_a_r/semihost.c
index ff5e443759b..1467dbca3a4 100644
--- a/arch/arm/core/cortex_a_r/semihost.c
+++ b/arch/arm/core/cortex_a_r/semihost.c
@@ -19,10 +19,10 @@ long semihost_exec(enum semihost_instr instr, void *args)
 	register long ret __asm__ ("r0");
 
 	if (IS_ENABLED(CONFIG_ISA_THUMB2)) {
-		__asm__ __volatile__ ("svc 0xab"
+		__asm__ volatile ("svc 0xab"
 				      : "=r" (ret) : "r" (r0), "r" (r1) : "memory");
 	} else {
-		__asm__ __volatile__ ("svc 0x123456"
+		__asm__ volatile ("svc 0x123456"
 				      : "=r" (ret) : "r" (r0), "r" (r1) : "memory");
 	}
 	return ret;
diff --git a/arch/arm/core/cortex_a_r/swap_helper.S b/arch/arm/core/cortex_a_r/swap_helper.S
index a41e1ab5942..04b19f0b046 100644
--- a/arch/arm/core/cortex_a_r/swap_helper.S
+++ b/arch/arm/core/cortex_a_r/swap_helper.S
@@ -423,5 +423,9 @@ valid_syscall_id:
 
 GTEXT(z_arm_cortex_r_svc)
 SECTION_FUNC(TEXT, z_arm_cortex_r_svc)
+    .cfi_sections .debug_frame
+    .cfi_startproc simple
+    .cfi_def_cfa 13, 0x0
     svc #_SVC_CALL_CONTEXT_SWITCH
     bx lr
+    .cfi_endproc
diff --git a/arch/arm/core/cortex_a_r/vector_table.S b/arch/arm/core/cortex_a_r/vector_table.S
index e74b6a41c8d..d5d95272548 100644
--- a/arch/arm/core/cortex_a_r/vector_table.S
+++ b/arch/arm/core/cortex_a_r/vector_table.S
@@ -35,27 +35,3 @@ SECTION_SUBSEC_FUNC(exc_vector_table,_vector_table_section,_vector_table)
 #else
 	ldr pc,=z_irq_spurious
 #endif
-
-
-#ifdef CONFIG_USE_SWITCH
-GTEXT(z_arm_cortex_ar_exit_exc)
-SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, z_arm_cortex_ar_exit_exc)
-
-	/* Note:
-	 * This function is expected to be *always* called with
-	 * processor mode set to MODE_SYS.
-	 */
-
-	/* decrement exception depth */
-	get_cpu r2
-	ldrb r1, [r2, #_cpu_offset_to_exc_depth]
-	sub r1, r1, #1
-	strb r1, [r2, #_cpu_offset_to_exc_depth]
-
-	/*
-	 * Restore r0-r3, r12, lr, lr_und and spsr_und from the exception stack
-	 * and return to the current thread.
-	 */
-	pop {r0-r3, r12, lr}
-	rfeia sp!
-#endif
diff --git a/arch/arm/core/cortex_m/CMakeLists.txt b/arch/arm/core/cortex_m/CMakeLists.txt
index 05723811929..54bca650084 100644
--- a/arch/arm/core/cortex_m/CMakeLists.txt
+++ b/arch/arm/core/cortex_m/CMakeLists.txt
@@ -61,3 +61,13 @@ zephyr_linker_sources(
   vt_pointer_section.ld
   )
 endif()
+
+if (CONFIG_CPU_CORTEX_M_HAS_VTOR)
+zephyr_linker_sources_ifdef(CONFIG_SRAM_VECTOR_TABLE
+  RAM_SECTIONS
+  # Maybe need to be changed in order to be placed at the beginning of RAM
+  # (conflict with code relocation script)
+  SORT_KEY 0
+  ram_vector_table.ld
+)
+endif()
diff --git a/arch/arm/core/cortex_m/cmse/arm_core_cmse.c b/arch/arm/core/cortex_m/cmse/arm_core_cmse.c
index aac96472ecf..163a9d0cdd2 100644
--- a/arch/arm/core/cortex_m/cmse/arm_core_cmse.c
+++ b/arch/arm/core/cortex_m/cmse/arm_core_cmse.c
@@ -9,7 +9,7 @@
 
 int arm_cmse_mpu_region_get(uint32_t addr)
 {
-	cmse_address_info_t addr_info =	cmse_TT((void *)addr);
+	cmse_address_info_t addr_info = cmse_TT((void *)addr);
 
 	if (addr_info.flags.mpu_region_valid) {
 		return addr_info.flags.mpu_region;
@@ -40,8 +40,7 @@ int arm_cmse_addr_readwrite_ok(uint32_t addr, int force_npriv)
 	return arm_cmse_addr_read_write_ok(addr, force_npriv, 1);
 }
 
-static int arm_cmse_addr_range_read_write_ok(uint32_t addr, uint32_t size,
-	int force_npriv, int rw)
+static int arm_cmse_addr_range_read_write_ok(uint32_t addr, uint32_t size, int force_npriv, int rw)
 {
 	int flags = 0;
 
@@ -74,10 +73,10 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr
 
 int arm_cmse_mpu_nonsecure_region_get(uint32_t addr)
 {
-	cmse_address_info_t addr_info =	cmse_TTA((void *)addr);
+	cmse_address_info_t addr_info = cmse_TTA((void *)addr);
 
 	if (addr_info.flags.mpu_region_valid) {
-		return  addr_info.flags.mpu_region;
+		return addr_info.flags.mpu_region;
 	}
 
 	return -EINVAL;
@@ -85,7 +84,7 @@ int arm_cmse_mpu_nonsecure_region_get(uint32_t addr)
 
 int arm_cmse_sau_region_get(uint32_t addr)
 {
-	cmse_address_info_t addr_info =	cmse_TT((void *)addr);
+	cmse_address_info_t addr_info = cmse_TT((void *)addr);
 
 	if (addr_info.flags.sau_region_valid) {
 		return addr_info.flags.sau_region;
@@ -96,7 +95,7 @@ int arm_cmse_sau_region_get(uint32_t addr)
 
 int arm_cmse_idau_region_get(uint32_t addr)
 {
-	cmse_address_info_t addr_info =	cmse_TT((void *)addr);
+	cmse_address_info_t addr_info = cmse_TT((void *)addr);
 
 	if (addr_info.flags.idau_region_valid) {
 		return addr_info.flags.idau_region;
@@ -107,13 +106,12 @@ int arm_cmse_idau_region_get(uint32_t addr)
 
 int arm_cmse_addr_is_secure(uint32_t addr)
 {
-	cmse_address_info_t addr_info =	cmse_TT((void *)addr);
+	cmse_address_info_t addr_info = cmse_TT((void *)addr);
 
 	return addr_info.flags.secure;
 }
 
-static int arm_cmse_addr_nonsecure_read_write_ok(uint32_t addr,
-	int force_npriv, int rw)
+static int arm_cmse_addr_nonsecure_read_write_ok(uint32_t addr, int force_npriv, int rw)
 {
 	cmse_address_info_t addr_info;
 	if (force_npriv) {
@@ -122,8 +120,7 @@ static int arm_cmse_addr_nonsecure_read_write_ok(uint32_t addr,
 		addr_info = cmse_TTA((void *)addr);
 	}
 
-	return rw ? addr_info.flags.nonsecure_readwrite_ok :
-		addr_info.flags.nonsecure_read_ok;
+	return rw ? addr_info.flags.nonsecure_readwrite_ok : addr_info.flags.nonsecure_read_ok;
 }
 
 int arm_cmse_addr_nonsecure_read_ok(uint32_t addr, int force_npriv)
@@ -137,7 +134,7 @@ int arm_cmse_addr_nonsecure_readwrite_ok(uint32_t addr, int force_npriv)
 }
 
 static int arm_cmse_addr_range_nonsecure_read_write_ok(uint32_t addr, uint32_t size,
-	int force_npriv, int rw)
+						       int force_npriv, int rw)
 {
 	int flags = CMSE_NONSECURE;
 
@@ -156,18 +153,14 @@ static int arm_cmse_addr_range_nonsecure_read_write_ok(uint32_t addr, uint32_t s
 	}
 }
 
-int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size,
-	int force_npriv)
+int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size, int force_npriv)
 {
-	return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size,
-		force_npriv, 0);
+	return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size, force_npriv, 0);
 }
 
-int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size,
-	int force_npriv)
+int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, int force_npriv)
 {
-	return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size,
-		force_npriv, 1);
+	return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size, force_npriv, 1);
 }
 
 #endif /* CONFIG_ARM_SECURE_FIRMWARE */
diff --git a/arch/arm/core/cortex_m/coredump.c b/arch/arm/core/cortex_m/coredump.c
index c688c91d981..ddb539c4e34 100644
--- a/arch/arm/core/cortex_m/coredump.c
+++ b/arch/arm/core/cortex_m/coredump.c
@@ -7,31 +7,31 @@
 #include <string.h>
 #include <zephyr/debug/coredump.h>
 
-#define ARCH_HDR_VER			2
+#define ARCH_HDR_VER 2
 
 uint32_t z_arm_coredump_fault_sp;
 
 struct arm_arch_block {
 	struct {
-		uint32_t	r0;
-		uint32_t	r1;
-		uint32_t	r2;
-		uint32_t	r3;
-		uint32_t	r12;
-		uint32_t	lr;
-		uint32_t	pc;
-		uint32_t	xpsr;
-		uint32_t	sp;
+		uint32_t r0;
+		uint32_t r1;
+		uint32_t r2;
+		uint32_t r3;
+		uint32_t r12;
+		uint32_t lr;
+		uint32_t pc;
+		uint32_t xpsr;
+		uint32_t sp;
 
 		/* callee registers - optionally collected in V2 */
-		uint32_t	r4;
-		uint32_t	r5;
-		uint32_t	r6;
-		uint32_t	r7;
-		uint32_t	r8;
-		uint32_t	r9;
-		uint32_t	r10;
-		uint32_t	r11;
+		uint32_t r4;
+		uint32_t r5;
+		uint32_t r6;
+		uint32_t r7;
+		uint32_t r8;
+		uint32_t r9;
+		uint32_t r10;
+		uint32_t r11;
 	} r;
 } __packed;
 
@@ -76,12 +76,12 @@ void arch_coredump_info_dump(const struct arch_esf *esf)
 
 #if defined(CONFIG_EXTRA_EXCEPTION_INFO)
 	if (esf->extra_info.callee) {
-		arch_blk.r.r4  = esf->extra_info.callee->v1;
-		arch_blk.r.r5  = esf->extra_info.callee->v2;
-		arch_blk.r.r6  = esf->extra_info.callee->v3;
-		arch_blk.r.r7  = esf->extra_info.callee->v4;
-		arch_blk.r.r8  = esf->extra_info.callee->v5;
-		arch_blk.r.r9  = esf->extra_info.callee->v6;
+		arch_blk.r.r4 = esf->extra_info.callee->v1;
+		arch_blk.r.r5 = esf->extra_info.callee->v2;
+		arch_blk.r.r6 = esf->extra_info.callee->v3;
+		arch_blk.r.r7 = esf->extra_info.callee->v4;
+		arch_blk.r.r8 = esf->extra_info.callee->v5;
+		arch_blk.r.r9 = esf->extra_info.callee->v6;
 		arch_blk.r.r10 = esf->extra_info.callee->v7;
 		arch_blk.r.r11 = esf->extra_info.callee->v8;
 	}
diff --git a/arch/arm/core/cortex_m/cpu_idle.c b/arch/arm/core/cortex_m/cpu_idle.c
index 5f373a88c9d..47eff95090a 100644
--- a/arch/arm/core/cortex_m/cpu_idle.c
+++ b/arch/arm/core/cortex_m/cpu_idle.c
@@ -30,27 +30,31 @@ void z_arm_cpu_idle_init(void)
 #if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
 #define ON_EXIT_IDLE_HOOK SOC_ON_EXIT_CPU_IDLE
 #else
-#define ON_EXIT_IDLE_HOOK do {} while (false)
+#define ON_EXIT_IDLE_HOOK                                                                          \
+	do {                                                                                       \
+	} while (false)
 #endif
 
 #if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK)
-#define SLEEP_IF_ALLOWED(wait_instr) do { \
-	/* Skip the wait instr if on_enter_cpu_idle returns false */ \
-	if (z_arm_on_enter_cpu_idle()) { \
-		/* Wait for all memory transaction to complete */ \
-		/* before entering low power state. */ \
-		__DSB(); \
-		wait_instr(); \
-		/* Inline the macro provided by SoC-specific code */ \
-		ON_EXIT_IDLE_HOOK; \
-	} \
-} while (false)
+#define SLEEP_IF_ALLOWED(wait_instr)                                                               \
+	do {                                                                                       \
+		/* Skip the wait instr if on_enter_cpu_idle returns false */                       \
+		if (z_arm_on_enter_cpu_idle()) {                                                   \
+			/* Wait for all memory transaction to complete */                          \
+			/* before entering low power state. */                                     \
+			__DSB();                                                                   \
+			wait_instr();                                                              \
+			/* Inline the macro provided by SoC-specific code */                       \
+			ON_EXIT_IDLE_HOOK;                                                         \
+		}                                                                                  \
+	} while (false)
 #else
-#define SLEEP_IF_ALLOWED(wait_instr) do { \
-	__DSB(); \
-	wait_instr(); \
-	ON_EXIT_IDLE_HOOK; \
-} while (false)
+#define SLEEP_IF_ALLOWED(wait_instr)                                                               \
+	do {                                                                                       \
+		__DSB();                                                                           \
+		wait_instr();                                                                      \
+		ON_EXIT_IDLE_HOOK;                                                                 \
+	} while (false)
 #endif
 
 #ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE
@@ -94,6 +98,9 @@ void arch_cpu_idle(void)
 
 	SLEEP_IF_ALLOWED(__WFI);
 
+#if defined(CONFIG_TRACING)
+	sys_trace_idle_exit();
+#endif
 	__enable_irq();
 	__ISB();
 }
@@ -133,6 +140,10 @@ void arch_cpu_atomic_idle(unsigned int key)
 
 	SLEEP_IF_ALLOWED(__WFE);
 
+#if defined(CONFIG_TRACING)
+	sys_trace_idle_exit();
+#endif
+
 	arch_irq_unlock(key);
 #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 	__enable_irq();
diff --git a/arch/arm/core/cortex_m/debug.c b/arch/arm/core/cortex_m/debug.c
index 61fb6814535..47141d913dd 100644
--- a/arch/arm/core/cortex_m/debug.c
+++ b/arch/arm/core/cortex_m/debug.c
@@ -35,7 +35,7 @@ bool z_arm_debug_monitor_event_error_check(void)
 			printk("Null-pointer exception?\n");
 		}
 		__ASSERT((DWT->FUNCTION0 & DWT_FUNCTION_MATCHED_Msk) == 0,
-			"MATCHED flag should have been cleared on read.");
+			 "MATCHED flag should have been cleared on read.");
 
 		return true;
 	}
@@ -55,8 +55,8 @@ bool z_arm_debug_monitor_event_error_check(void)
  * so we add a build assert that catches it.
  */
 BUILD_ASSERT(!(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE &
-	(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1)),
-	"the size of the partition must be power of 2");
+	       (CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1)),
+	     "the size of the partition must be power of 2");
 
 int z_arm_debug_enable_null_pointer_detection(void)
 {
@@ -81,20 +81,12 @@ int z_arm_debug_enable_null_pointer_detection(void)
 	DWT->COMP0 = 0;
 	DWT->COMP1 = CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1;
 
-	DWT->FUNCTION0 =
-		((0x4 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk)
-		|
-		((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk)
-		|
-		((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk)
-		;
-	DWT->FUNCTION1 =
-		((0x7 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk)
-		|
-		((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk)
-		|
-		((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk)
-		;
+	DWT->FUNCTION0 = ((0x4 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk) |
+			 ((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk) |
+			 ((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk);
+	DWT->FUNCTION1 = ((0x7 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk) |
+			 ((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk) |
+			 ((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk);
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 
 	/* ASSERT that we have the comparator needed for the implementation */
@@ -106,13 +98,10 @@ int z_arm_debug_enable_null_pointer_detection(void)
 	/* Use comparator 0, R/W access check */
 	DWT->COMP0 = 0;
 
-	DWT->FUNCTION0 = (0x7 << DWT_FUNCTION_FUNCTION_Pos) &
-		DWT_FUNCTION_FUNCTION_Msk;
-
+	DWT->FUNCTION0 = (0x7 << DWT_FUNCTION_FUNCTION_Pos) & DWT_FUNCTION_FUNCTION_Msk;
 
 	/* Set mask according to the desired size */
-	DWT->MASK0 = 32 - __builtin_clzl(
-		CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1);
+	DWT->MASK0 = 32 - __builtin_clzl(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1);
 #endif
 
 	return 0;
diff --git a/arch/arm/core/cortex_m/exc_exit.c b/arch/arm/core/cortex_m/exc_exit.c
index 450b3972361..a919fd8bbd7 100644
--- a/arch/arm/core/cortex_m/exc_exit.c
+++ b/arch/arm/core/cortex_m/exc_exit.c
@@ -55,13 +55,8 @@ FUNC_ALIAS(z_arm_exc_exit, z_arm_int_exit, void);
 Z_GENERIC_SECTION(.text._HandlerModeExit) void z_arm_exc_exit(void)
 {
 #ifdef CONFIG_PREEMPT_ENABLED
-	/* If thread is preemptible */
-	if (_kernel.cpus->current->base.prio >= 0) {
-		/* and cached thread is not current thread */
-		if (_kernel.ready_q.cache != _kernel.cpus->current) {
-			/* trigger a context switch */
-			SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
-		}
+	if (_kernel.ready_q.cache != _kernel.cpus->current) {
+		SCB->ICSR |= SCB_ICSR_PENDSVSET_Msk;
 	}
 #endif /* CONFIG_PREEMPT_ENABLED */
 
diff --git a/arch/arm/core/cortex_m/fault.c b/arch/arm/core/cortex_m/fault.c
index 56d5be60f4c..27ce260dad5 100644
--- a/arch/arm/core/cortex_m/fault.c
+++ b/arch/arm/core/cortex_m/fault.c
@@ -22,7 +22,7 @@
 LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
 
 #if defined(CONFIG_PRINTK) || defined(CONFIG_LOG)
-#define PR_EXC(...) LOG_ERR(__VA_ARGS__)
+#define PR_EXC(...)              LOG_ERR(__VA_ARGS__)
 #define STORE_xFAR(reg_var, reg) uint32_t reg_var = (uint32_t)reg
 #else
 #define PR_EXC(...)
@@ -36,8 +36,8 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
 #endif
 
 #if defined(CONFIG_ARM_MPU) && defined(CONFIG_CPU_HAS_NXP_SYSMPU)
-#define EMN(edr)   (((edr) & SYSMPU_EDR_EMN_MASK) >> SYSMPU_EDR_EMN_SHIFT)
-#define EACD(edr)  (((edr) & SYSMPU_EDR_EACD_MASK) >> SYSMPU_EDR_EACD_SHIFT)
+#define EMN(edr)  (((edr) & SYSMPU_EDR_EMN_MASK) >> SYSMPU_EDR_EMN_SHIFT)
+#define EACD(edr) (((edr) & SYSMPU_EDR_EACD_MASK) >> SYSMPU_EDR_EACD_SHIFT)
 #endif
 
 /* Integrity signature for an ARMv8-M implementation */
@@ -54,15 +54,12 @@ LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
 
 #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 /* helpers to access memory/bus/usage faults */
-#define SCB_CFSR_MEMFAULTSR \
-	(uint32_t)((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk) \
-		   >> SCB_CFSR_MEMFAULTSR_Pos)
-#define SCB_CFSR_BUSFAULTSR \
-	(uint32_t)((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk) \
-		   >> SCB_CFSR_BUSFAULTSR_Pos)
-#define SCB_CFSR_USGFAULTSR \
-	(uint32_t)((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk) \
-		   >> SCB_CFSR_USGFAULTSR_Pos)
+#define SCB_CFSR_MEMFAULTSR                                                                        \
+	(uint32_t)((SCB->CFSR & SCB_CFSR_MEMFAULTSR_Msk) >> SCB_CFSR_MEMFAULTSR_Pos)
+#define SCB_CFSR_BUSFAULTSR                                                                        \
+	(uint32_t)((SCB->CFSR & SCB_CFSR_BUSFAULTSR_Msk) >> SCB_CFSR_BUSFAULTSR_Pos)
+#define SCB_CFSR_USGFAULTSR                                                                        \
+	(uint32_t)((SCB->CFSR & SCB_CFSR_USGFAULTSR_Msk) >> SCB_CFSR_USGFAULTSR_Pos)
 #endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE */
 
 /**
@@ -103,8 +100,8 @@ static void fault_show(const struct arch_esf *esf, int fault)
 	PR_EXC("Fault! EXC #%d", fault);
 
 #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-	PR_EXC("MMFSR: 0x%x, BFSR: 0x%x, UFSR: 0x%x", SCB_CFSR_MEMFAULTSR,
-	       SCB_CFSR_BUSFAULTSR, SCB_CFSR_USGFAULTSR);
+	PR_EXC("MMFSR: 0x%x, BFSR: 0x%x, UFSR: 0x%x", SCB_CFSR_MEMFAULTSR, SCB_CFSR_BUSFAULTSR,
+	       SCB_CFSR_USGFAULTSR);
 #if defined(CONFIG_ARM_SECURE_FIRMWARE)
 	PR_EXC("SFSR: 0x%x", SAU->SFSR);
 #endif /* CONFIG_ARM_SECURE_FIRMWARE */
@@ -127,9 +124,7 @@ static void fault_show(const struct arch_esf *esf, int fault)
 #ifdef CONFIG_USERSPACE
 Z_EXC_DECLARE(z_arm_user_string_nlen);
 
-static const struct z_exc_handle exceptions[] = {
-	Z_EXC_HANDLE(z_arm_user_string_nlen)
-};
+static const struct z_exc_handle exceptions[] = {Z_EXC_HANDLE(z_arm_user_string_nlen)};
 #endif
 
 /* Perform an assessment whether an MPU fault shall be
@@ -146,12 +141,12 @@ static bool memory_fault_recoverable(struct arch_esf *esf, bool synchronous)
 		uint32_t end = (uint32_t)exceptions[i].end & ~0x1U;
 
 #if defined(CONFIG_NULL_POINTER_EXCEPTION_DETECTION_DWT)
-	/* Non-synchronous exceptions (e.g. DebugMonitor) may have
-	 * allowed PC to continue to the next instruction.
-	 */
-	end += (synchronous) ? 0x0 : 0x4;
+		/* Non-synchronous exceptions (e.g. DebugMonitor) may have
+		 * allowed PC to continue to the next instruction.
+		 */
+		end += (synchronous) ? 0x0 : 0x4;
 #else
-	ARG_UNUSED(synchronous);
+		ARG_UNUSED(synchronous);
 #endif
 		if (esf->basic.pc >= start && esf->basic.pc < end) {
 			esf->basic.pc = (uint32_t)(exceptions[i].fixup);
@@ -168,8 +163,7 @@ static bool memory_fault_recoverable(struct arch_esf *esf, bool synchronous)
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 
 #if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
-uint32_t z_check_thread_stack_fail(const uint32_t fault_addr,
-	const uint32_t psp);
+uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp);
 #endif /* CONFIG_MPU_STACK_GUARD || defined(CONFIG_USERSPACE) */
 
 /**
@@ -180,8 +174,7 @@ uint32_t z_check_thread_stack_fail(const uint32_t fault_addr,
  *
  * @return error code to identify the fatal error reason
  */
-static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault,
-			      bool *recoverable)
+static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverable)
 {
 	uint32_t reason = K_ERR_ARM_MEM_GENERIC;
 	uint32_t mmfar = -EINVAL;
@@ -191,7 +184,7 @@ static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault,
 	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) != 0) {
 		reason = K_ERR_ARM_MEM_STACKING;
 		PR_FAULT_INFO("  Stacking error (context area might be"
-			" not valid)");
+			      " not valid)");
 	}
 	if ((SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) != 0) {
 		reason = K_ERR_ARM_MEM_UNSTACKING;
@@ -226,8 +219,7 @@ static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault,
 #if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
 	if ((SCB->CFSR & SCB_CFSR_MLSPERR_Msk) != 0) {
 		reason = K_ERR_ARM_MEM_FP_LAZY_STATE_PRESERVATION;
-		PR_FAULT_INFO(
-			"  Floating-point lazy state preservation error");
+		PR_FAULT_INFO("  Floating-point lazy state preservation error");
 	}
 #endif /* CONFIG_ARMV7_M_ARMV8_M_FP */
 
@@ -244,8 +236,7 @@ static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault,
 	 * Data Access Violation errors may or may not be caused by
 	 * thread stack overflows.
 	 */
-	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) ||
-		(SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
+	if ((SCB->CFSR & SCB_CFSR_MSTKERR_Msk) || (SCB->CFSR & SCB_CFSR_DACCVIOL_Msk)) {
 #if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
 		/* MemManage Faults are always banked between security
 		 * states. Therefore, we can safely assume the fault
@@ -265,8 +256,8 @@ static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault,
 		 * handle the case of 'mmfar' holding the -EINVAL value.
 		 */
 		if (SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) {
-			uint32_t min_stack_ptr = z_check_thread_stack_fail(mmfar,
-				((uint32_t) &esf[0]));
+			uint32_t min_stack_ptr =
+				z_check_thread_stack_fail(mmfar, ((uint32_t)&esf[0]));
 
 			if (min_stack_ptr) {
 				/* When MemManage Stacking Error has occurred,
@@ -299,14 +290,14 @@ static uint32_t mem_manage_fault(struct arch_esf *esf, int from_hard_fault,
 				reason = K_ERR_STACK_CHK_FAIL;
 			} else {
 				__ASSERT(!(SCB->CFSR & SCB_CFSR_MSTKERR_Msk),
-					"Stacking error not a stack fail\n");
+					 "Stacking error not a stack fail\n");
 			}
 		}
 #else
-	(void)mmfar;
-	__ASSERT(!(SCB->CFSR & SCB_CFSR_MSTKERR_Msk),
-		"Stacking or Data Access Violation error "
-		"without stack guard, user-mode or null-pointer detection\n");
+		(void)mmfar;
+		__ASSERT(!(SCB->CFSR & SCB_CFSR_MSTKERR_Msk),
+			 "Stacking or Data Access Violation error "
+			 "without stack guard, user-mode or null-pointer detection\n");
 #endif /* CONFIG_MPU_STACK_GUARD || CONFIG_USERSPACE */
 	}
 
@@ -408,13 +399,10 @@ static int bus_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverabl
 
 			PR_FAULT_INFO("  NXP MPU error, port %d", i);
 			PR_FAULT_INFO("    Mode: %s, %s Address: 0x%x",
-			       edr & BIT(2) ? "Supervisor" : "User",
-			       edr & BIT(1) ? "Data" : "Instruction",
-			       ear);
-			PR_FAULT_INFO(
-					"    Type: %s, Master: %d, Regions: 0x%x",
-			       edr & BIT(0) ? "Write" : "Read",
-			       EMN(edr), EACD(edr));
+				      edr & BIT(2) ? "Supervisor" : "User",
+				      edr & BIT(1) ? "Data" : "Instruction", ear);
+			PR_FAULT_INFO("    Type: %s, Master: %d, Regions: 0x%x",
+				      edr & BIT(0) ? "Write" : "Read", EMN(edr), EACD(edr));
 
 			/* When stack protection is enabled, we need to assess
 			 * if the memory violation error is a stack corruption.
@@ -437,8 +425,7 @@ static int bus_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverabl
 				 */
 				if (SCB->ICSR & SCB_ICSR_RETTOBASE_Msk) {
 					uint32_t min_stack_ptr =
-						z_check_thread_stack_fail(ear,
-							((uint32_t) &esf[0]));
+						z_check_thread_stack_fail(ear, ((uint32_t)&esf[0]));
 
 					if (min_stack_ptr) {
 						/* When BusFault Stacking Error
@@ -468,16 +455,14 @@ static int bus_fault(struct arch_esf *esf, int from_hard_fault, bool *recoverabl
 						 */
 						__set_PSP(min_stack_ptr);
 
-						reason =
-							K_ERR_STACK_CHK_FAIL;
+						reason = K_ERR_STACK_CHK_FAIL;
 						break;
 					}
 				}
 #else
 				(void)ear;
 				__ASSERT(0,
-					"Stacking error without stack guard"
-					"or User-mode support");
+					 "Stacking error without stack guard or User-mode support");
 #endif /* CONFIG_MPU_STACK_GUARD || CONFIG_USERSPACE */
 			}
 		}
@@ -617,8 +602,7 @@ static void debug_monitor(struct arch_esf *esf, bool *recoverable)
 {
 	*recoverable = false;
 
-	PR_FAULT_INFO(
-		"***** Debug monitor exception *****");
+	PR_FAULT_INFO("***** Debug monitor exception *****");
 
 #if defined(CONFIG_NULL_POINTER_EXCEPTION_DETECTION_DWT)
 	if (!z_arm_debug_monitor_event_error_check()) {
@@ -675,7 +659,7 @@ static inline bool z_arm_is_synchronous_svc(struct arch_esf *esf)
 #endif /* ARMV6_M_ARMV8_M_BASELINE && !ARMV8_M_BASELINE */
 
 	if (((fault_insn & 0xff00) == _SVC_OPCODE) &&
-		((fault_insn & 0x00ff) == _SVC_CALL_RUNTIME_EXCEPT)) {
+	    ((fault_insn & 0x00ff) == _SVC_CALL_RUNTIME_EXCEPT)) {
 		return true;
 	}
 #undef _SVC_OPCODE
@@ -759,13 +743,11 @@ static uint32_t hard_fault(struct arch_esf *esf, bool *recoverable)
 			reason = secure_fault(esf);
 #endif /* CONFIG_ARM_SECURE_FIRMWARE */
 		} else {
-			__ASSERT(0,
-			"Fault escalation without FSR info");
+			__ASSERT(0, "Fault escalation without FSR info");
 		}
 	} else {
-		__ASSERT(0,
-		"HardFault without HFSR info"
-		" Shall never occur");
+		__ASSERT(0, "HardFault without HFSR info"
+			    " Shall never occur");
 	}
 #else
 #error Unknown ARM architecture
@@ -786,8 +768,7 @@ static void reserved_exception(const struct arch_esf *esf, int fault)
 	ARG_UNUSED(esf);
 
 	PR_FAULT_INFO("***** %s %d) *****",
-	       fault < 16 ? "Reserved Exception (" : "Spurious interrupt (IRQ ",
-	       fault - 16);
+		      fault < 16 ? "Reserved Exception (" : "Spurious interrupt (IRQ ", fault - 16);
 }
 
 /* Handler function for ARM fault conditions. */
@@ -802,7 +783,7 @@ static uint32_t fault_handle(struct arch_esf *esf, int fault, bool *recoverable)
 		reason = hard_fault(esf, recoverable);
 		break;
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
-	/* HardFault is raised for all fault conditions on ARMv6-M. */
+		/* HardFault is raised for all fault conditions on ARMv6-M. */
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 	case 4:
 		reason = mem_manage_fault(esf, 0, recoverable);
@@ -860,7 +841,7 @@ static void secure_stack_dump(const struct arch_esf *secure_esf)
 	uint32_t sec_ret_addr;
 #if defined(CONFIG_ARMV7_M_ARMV8_M_FP)
 	if ((*top_of_sec_stack == INTEGRITY_SIGNATURE_STD) ||
-		(*top_of_sec_stack == INTEGRITY_SIGNATURE_EXT)) {
+	    (*top_of_sec_stack == INTEGRITY_SIGNATURE_EXT)) {
 #else
 	if (*top_of_sec_stack == INTEGRITY_SIGNATURE) {
 #endif /* CONFIG_ARMV7_M_ARMV8_M_FP */
@@ -879,7 +860,6 @@ static void secure_stack_dump(const struct arch_esf *secure_esf)
 		sec_ret_addr = *top_of_sec_stack;
 	}
 	PR_FAULT_INFO("  S instruction address:  0x%x", sec_ret_addr);
-
 }
 #define SECURE_STACK_DUMP(esf) secure_stack_dump(esf)
 #else
@@ -900,15 +880,14 @@ static void secure_stack_dump(const struct arch_esf *secure_esf)
  * @return ESF pointer on success, otherwise return NULL
  */
 static inline struct arch_esf *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_return,
-	bool *nested_exc)
+				       bool *nested_exc)
 {
 	bool alternative_state_exc = false;
 	struct arch_esf *ptr_esf = NULL;
 
 	*nested_exc = false;
 
-	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) !=
-			EXC_RETURN_INDICATOR_PREFIX) {
+	if ((exc_return & EXC_RETURN_INDICATOR_PREFIX) != EXC_RETURN_INDICATOR_PREFIX) {
 		/* Invalid EXC_RETURN value. This is a fatal error. */
 		return NULL;
 	}
@@ -988,8 +967,7 @@ static inline struct arch_esf *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_
 	/* The processor has a single execution state.
 	 * We verify that the Thread mode is using PSP.
 	 */
-	if ((exc_return & EXC_RETURN_MODE_THREAD) &&
-		(!(exc_return & EXC_RETURN_SPSEL_PROCESS))) {
+	if ((exc_return & EXC_RETURN_MODE_THREAD) && (!(exc_return & EXC_RETURN_SPSEL_PROCESS))) {
 		PR_EXC("SPSEL in thread mode does not indicate PSP");
 		return NULL;
 	}
@@ -998,7 +976,7 @@ static inline struct arch_esf *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_
 	if (!alternative_state_exc) {
 		if (exc_return & EXC_RETURN_MODE_THREAD) {
 			/* Returning to thread mode */
-			ptr_esf =  (struct arch_esf *)psp;
+			ptr_esf = (struct arch_esf *)psp;
 
 		} else {
 			/* Returning to handler mode */
@@ -1041,8 +1019,7 @@ static inline struct arch_esf *get_esf(uint32_t msp, uint32_t psp, uint32_t exc_
  * @param callee_regs Callee-saved registers (R4-R11, PSP)
  *
  */
-void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
-	_callee_saved_t *callee_regs)
+void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return, _callee_saved_t *callee_regs)
 {
 	uint32_t reason = K_ERR_CPU_EXCEPTION;
 	int fault = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk;
@@ -1060,9 +1037,8 @@ void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
 	/* Retrieve the Exception Stack Frame (ESF) to be supplied
 	 * as argument to the remainder of the fault handling process.
 	 */
-	 esf = get_esf(msp, psp, exc_return, &nested_exc);
-	__ASSERT(esf != NULL,
-		"ESF could not be retrieved successfully. Shall never occur.");
+	esf = get_esf(msp, psp, exc_return, &nested_exc);
+	__ASSERT(esf != NULL, "ESF could not be retrieved successfully. Shall never occur.");
 
 	z_arm_set_fault_sp(esf, exc_return);
 
@@ -1080,11 +1056,8 @@ void z_arm_fault(uint32_t msp, uint32_t psp, uint32_t exc_return,
 	 * so we only copy the fields before those.
 	 */
 	memcpy(&esf_copy, esf, offsetof(struct arch_esf, extra_info));
-	esf_copy.extra_info = (struct __extra_esf_info) {
-		.callee = callee_regs,
-		.exc_return = exc_return,
-		.msp = msp
-	};
+	esf_copy.extra_info = (struct __extra_esf_info){
+		.callee = callee_regs, .exc_return = exc_return, .msp = msp};
 #endif /* CONFIG_EXTRA_EXCEPTION_INFO */
 
 	/* Overwrite stacked IPSR to mark a nested exception,
diff --git a/arch/arm/core/cortex_m/fpu.c b/arch/arm/core/cortex_m/fpu.c
index a9c964d14d1..b937d725c28 100644
--- a/arch/arm/core/cortex_m/fpu.c
+++ b/arch/arm/core/cortex_m/fpu.c
@@ -23,11 +23,10 @@ void z_arm_save_fp_context(struct fpu_ctx_full *buffer)
 
 	if (CONTROL & CONTROL_FPCA_Msk) {
 		/* Store caller-saved and callee-saved FP registers. */
-		__asm__ volatile(
-			"vstmia %0, {s0-s15}\n"
-			"vstmia %1, {s16-s31}\n"
-			:: "r" (buffer->caller_saved), "r" (buffer->callee_saved) :
-		);
+		__asm__ volatile("vstmia %0, {s0-s15}\n"
+				 "vstmia %1, {s16-s31}\n" ::"r"(buffer->caller_saved),
+				 "r"(buffer->callee_saved)
+				 :);
 
 		buffer->fpscr = __get_FPSCR();
 		buffer->ctx_saved = true;
@@ -55,11 +54,10 @@ void z_arm_restore_fp_context(const struct fpu_ctx_full *buffer)
 		/* Restore FP state. */
 		__set_FPSCR(buffer->fpscr);
 
-		__asm__ volatile(
-			"vldmia %0, {s0-s15}\n"
-			"vldmia %1, {s16-s31}\n"
-			:: "r" (buffer->caller_saved), "r" (buffer->callee_saved) :
-		);
+		__asm__ volatile("vldmia %0, {s0-s15}\n"
+				 "vldmia %1, {s16-s31}\n" ::"r"(buffer->caller_saved),
+				 "r"(buffer->callee_saved)
+				 :);
 	}
 #endif
 }
diff --git a/arch/arm/core/cortex_m/irq_init.c b/arch/arm/core/cortex_m/irq_init.c
index b6b128e3368..edd1f519677 100644
--- a/arch/arm/core/cortex_m/irq_init.c
+++ b/arch/arm/core/cortex_m/irq_init.c
@@ -27,7 +27,12 @@ void z_arm_interrupt_init(void)
 {
 	int irq = 0;
 
+/* CONFIG_2ND_LVL_ISR_TBL_OFFSET could be treated as total number of level1 interrupts */
+#if defined(CONFIG_MULTI_LEVEL_INTERRUPTS) && defined(CONFIG_2ND_LVL_ISR_TBL_OFFSET)
+	for (; irq < CONFIG_2ND_LVL_ISR_TBL_OFFSET; irq++) {
+#else
 	for (; irq < CONFIG_NUM_IRQS; irq++) {
+#endif
 		NVIC_SetPriority((IRQn_Type)irq, _IRQ_PRIO_OFFSET);
 	}
 }
diff --git a/arch/arm/core/cortex_m/irq_manage.c b/arch/arm/core/cortex_m/irq_manage.c
index cc62386e8ac..6d1c8917c4d 100644
--- a/arch/arm/core/cortex_m/irq_manage.c
+++ b/arch/arm/core/cortex_m/irq_manage.c
@@ -28,23 +28,42 @@
 
 extern void z_arm_reserved(void);
 
-#define NUM_IRQS_PER_REG 32
+#define NUM_IRQS_PER_REG  32
 #define REG_FROM_IRQ(irq) (irq / NUM_IRQS_PER_REG)
 #define BIT_FROM_IRQ(irq) (irq % NUM_IRQS_PER_REG)
 
+/*
+ * For Cortex-M core, the default interrupt controller is the ARM
+ * NVIC and therefore the architecture interrupt control functions
+ * are mapped to the NVIC driver interface.
+ *
+ * When NVIC is used together with other interrupt controller for
+ * multi-level interrupts support (i.e. CONFIG_MULTI_LEVEL_INTERRUPTS
+ * is enabled), the architecture interrupt control functions are mapped
+ * to the SoC layer in `include/arch/arm/irq.h`.
+ * The exported arm interrupt control functions which are wrappers of
+ * NVIC control could be used for SoC to do level 1 irq control to implement SoC
+ * layer interrupt control functions.
+ *
+ * When a custom interrupt controller is used (i.e.
+ * CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER is enabled), the architecture
+ * interrupt control functions are mapped to the SoC layer in
+ * `include/arch/arm/irq.h`.
+ */
+
 #if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
 
-void arch_irq_enable(unsigned int irq)
+void arm_irq_enable(unsigned int irq)
 {
 	NVIC_EnableIRQ((IRQn_Type)irq);
 }
 
-void arch_irq_disable(unsigned int irq)
+void arm_irq_disable(unsigned int irq)
 {
 	NVIC_DisableIRQ((IRQn_Type)irq);
 }
 
-int arch_irq_is_enabled(unsigned int irq)
+int arm_irq_is_enabled(unsigned int irq)
 {
 	return NVIC->ISER[REG_FROM_IRQ(irq)] & BIT(BIT_FROM_IRQ(irq));
 }
@@ -58,7 +77,7 @@ int arch_irq_is_enabled(unsigned int irq)
  * of priority levels is a little complex, as there are some hardware
  * priority levels which are reserved.
  */
-void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
+void arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 {
 	/* The kernel may reserve some of the highest priority levels.
 	 * So we offset the requested priority level with the number
@@ -87,8 +106,7 @@ void z_arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 	 */
 	__ASSERT(prio <= (BIT(NUM_IRQ_PRIO_BITS) - 1),
 		 "invalid priority %d for %d irq! values must be less than %lu\n",
-		 prio - _IRQ_PRIO_OFFSET, irq,
-		 BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
+		 prio - _IRQ_PRIO_OFFSET, irq, BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET));
 	NVIC_SetPriority((IRQn_Type)irq, prio);
 }
 
@@ -141,7 +159,6 @@ void _arch_isr_direct_pm(void)
 #else
 #error Unknown ARM architecture
 #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
-
 }
 #endif
 
@@ -165,8 +182,7 @@ void _arch_isr_direct_pm(void)
  *
  * @return The resulting target state of the given IRQ
  */
-irq_target_state_t irq_target_state_set(unsigned int irq,
-	irq_target_state_t irq_target_state)
+irq_target_state_t irq_target_state_set(unsigned int irq, irq_target_state_t irq_target_state)
 {
 	uint32_t result;
 
@@ -217,7 +233,7 @@ int irq_target_state_is_secure(unsigned int irq)
  * - Bits corresponding to un-implemented interrupts are RES0, so writes
  *   will be ignored.
  *
-*/
+ */
 void irq_target_state_set_all_non_secure(void)
 {
 	int i;
@@ -241,8 +257,8 @@ void irq_target_state_set_all_non_secure(void)
 #ifdef CONFIG_DYNAMIC_INTERRUPTS
 #ifdef CONFIG_GEN_ISR_TABLES
 int arch_irq_connect_dynamic(unsigned int irq, unsigned int priority,
-			     void (*routine)(const void *parameter),
-			     const void *parameter, uint32_t flags)
+			     void (*routine)(const void *parameter), const void *parameter,
+			     uint32_t flags)
 {
 	z_isr_install(irq, routine, parameter);
 	z_arm_irq_priority_set(irq, priority, flags);
diff --git a/arch/arm/core/cortex_m/isr_wrapper.c b/arch/arm/core/cortex_m/isr_wrapper.c
index 46aac160c3b..f75963c413f 100644
--- a/arch/arm/core/cortex_m/isr_wrapper.c
+++ b/arch/arm/core/cortex_m/isr_wrapper.c
@@ -68,7 +68,7 @@ void _isr_wrapper(void)
 #if defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
 	int32_t irq_number = z_soc_irq_get_active();
 #else
-	/* _sw_isr_table does not map the expections, only the interrupts. */
+	/* _sw_isr_table does not map the exceptions, only the interrupts. */
 	int32_t irq_number = __get_IPSR();
 #endif
 	irq_number -= 16;
diff --git a/arch/arm/core/cortex_m/prep_c.c b/arch/arm/core/cortex_m/prep_c.c
index cadf9a9a867..632fc142003 100644
--- a/arch/arm/core/cortex_m/prep_c.c
+++ b/arch/arm/core/cortex_m/prep_c.c
@@ -23,27 +23,27 @@
 #include <zephyr/platform/hooks.h>
 #include <zephyr/arch/cache.h>
 
-#if defined(__GNUC__)
 /*
  * GCC can detect if memcpy is passed a NULL argument, however one of
  * the cases of relocate_vector_table() it is valid to pass NULL, so we
  * suppress the warning for this case.  We need to do this before
  * string.h is included to get the declaration of memcpy.
  */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wnonnull"
-#endif
+TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_NONNULL)
 
 #include <string.h>
 
 #if defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT)
-Z_GENERIC_SECTION(.vt_pointer_section) __attribute__((used))
-void *_vector_table_pointer;
+Z_GENERIC_SECTION(.vt_pointer_section) __attribute__((used)) void *_vector_table_pointer;
 #endif
 
 #ifdef CONFIG_CPU_CORTEX_M_HAS_VTOR
 
+#ifdef CONFIG_SRAM_VECTOR_TABLE
+#define VECTOR_ADDRESS ((uintptr_t)_sram_vector_start)
+#else
 #define VECTOR_ADDRESS ((uintptr_t)_vector_start)
+#endif
 
 /* In some Cortex-M3 implementations SCB_VTOR bit[29] is called the TBLBASE bit */
 #ifdef SCB_VTOR_TBLBASE_Msk
@@ -54,6 +54,12 @@ void *_vector_table_pointer;
 
 void __weak relocate_vector_table(void)
 {
+#ifdef CONFIG_SRAM_VECTOR_TABLE
+	/* Copy vector table to its location in SRAM */
+	size_t vector_size = (size_t)_vector_end - (size_t)_vector_start;
+
+	z_early_memcpy(_sram_vector_start, _vector_start, vector_size);
+#endif
 	SCB->VTOR = VECTOR_ADDRESS & VTOR_MASK;
 	barrier_dsync_fence_full();
 	barrier_isync_fence_full();
@@ -64,8 +70,8 @@ void __weak relocate_vector_table(void)
 
 void __weak relocate_vector_table(void)
 {
-#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) || \
-    !defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0)
+#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) ||                                     \
+	!defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0)
 	size_t vector_size = (size_t)_vector_end - (size_t)_vector_start;
 	(void)memcpy(VECTOR_ADDRESS, _vector_start, vector_size);
 #elif defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT)
@@ -73,9 +79,7 @@ void __weak relocate_vector_table(void)
 #endif
 }
 
-#if defined(__GNUC__)
-#pragma GCC diagnostic pop
-#endif
+TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_NONNULL)
 
 #endif /* CONFIG_CPU_CORTEX_M_HAS_VTOR */
 
@@ -100,7 +104,7 @@ static inline void z_arm_floating_point_init(void)
 #else
 	/* Privileged access only */
 	SCB->CPACR |= CPACR_CP10_PRIV_ACCESS | CPACR_CP11_PRIV_ACCESS;
-#endif /* CONFIG_USERSPACE */
+#endif  /* CONFIG_USERSPACE */
 	/*
 	 * Upon reset, the FPU Context Control Register is 0xC0000000
 	 * (both Automatic and Lazy state preservation is enabled).
@@ -170,7 +174,7 @@ static inline void z_arm_floating_point_init(void)
 	 *
 	 * If CONFIG_INIT_ARCH_HW_AT_BOOT is set, CONTROL is cleared at reset.
 	 */
-#if (!defined(CONFIG_FPU) || !defined(CONFIG_FPU_SHARING)) && \
+#if (!defined(CONFIG_FPU) || !defined(CONFIG_FPU_SHARING)) &&                                      \
 	(!defined(CONFIG_INIT_ARCH_HW_AT_BOOT))
 
 	__set_CONTROL(__get_CONTROL() & (~(CONTROL_FPCA_Msk)));
diff --git a/arch/arm/core/cortex_m/ram_vector_table.ld b/arch/arm/core/cortex_m/ram_vector_table.ld
new file mode 100644
index 00000000000..0c2353ab114
--- /dev/null
+++ b/arch/arm/core/cortex_m/ram_vector_table.ld
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Vector table is not necessarily at the start of the RAM region: in the case where Zephyr code
+ * relocation is used, the vector table is placed after the relocated code.
+ * Relocated code is always placed at the start of the RAM SECTION because of the hard-coded value
+ * generated by "gen_relocate_app.py" in the file. It can create quite a big gap and lose about the
+ * size of alignment in RAM space.
+ */
+
+SECTION_PROLOGUE(.sram_vt,,)
+{
+	/* Heritage of vector table alignment in flash (see vector_table.ld in arch/arm/core/) */
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
+	. = ALIGN( 1 << LOG2CEIL(4 * 64) );
+#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+	. = ALIGN( 1 << LOG2CEIL(4 * 32) );
+#else
+#error "Unsupported architecture variant"
+#endif
+
+	. = ALIGN( 1 << LOG2CEIL(4 * (16 + CONFIG_NUM_IRQS)) );
+
+	_sram_vector_start = .;
+	. += _vector_end - _vector_start;
+	MPU_ALIGN(_sram_vector_size);
+	_sram_vector_end = .;
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
+_sram_vector_size = _sram_vector_end - _sram_vector_start;
diff --git a/arch/arm/core/cortex_m/scb.c b/arch/arm/core/cortex_m/scb.c
index a511a8de9b1..957c66dcc9f 100644
--- a/arch/arm/core/cortex_m/scb.c
+++ b/arch/arm/core/cortex_m/scb.c
@@ -55,8 +55,7 @@ void z_arm_clear_arm_mpu_config(void)
 {
 	int i;
 
-	int num_regions =
-		((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
+	int num_regions = ((MPU->TYPE & MPU_TYPE_DREGION_Msk) >> MPU_TYPE_DREGION_Pos);
 
 	for (i = 0; i < num_regions; i++) {
 		ARM_MPU_ClrRegion(i);
@@ -90,7 +89,7 @@ void z_arm_clear_arm_mpu_config(void)
  */
 void z_arm_init_arch_hw_at_boot(void)
 {
-    /* Disable interrupts */
+	/* Disable interrupts */
 	__disable_irq();
 
 #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
diff --git a/arch/arm/core/cortex_m/semihost.c b/arch/arm/core/cortex_m/semihost.c
index 2a8c6d55a05..51ecd1f478c 100644
--- a/arch/arm/core/cortex_m/semihost.c
+++ b/arch/arm/core/cortex_m/semihost.c
@@ -9,11 +9,10 @@
 
 long semihost_exec(enum semihost_instr instr, void *args)
 {
-	register unsigned int r0 __asm__ ("r0") = instr;
-	register void *r1 __asm__ ("r1") = args;
-	register int ret __asm__ ("r0");
+	register unsigned int r0 __asm__("r0") = instr;
+	register void *r1 __asm__("r1") = args;
+	register int ret __asm__("r0");
 
-	__asm__ __volatile__ ("bkpt 0xab"
-			      : "=r" (ret) : "r" (r0), "r" (r1) : "memory");
+	__asm__ volatile("bkpt 0xab" : "=r"(ret) : "r"(r0), "r"(r1) : "memory");
 	return ret;
 }
diff --git a/arch/arm/core/cortex_m/swap_helper.S b/arch/arm/core/cortex_m/swap_helper.S
index f1bbbfa2a13..40f00fc0056 100644
--- a/arch/arm/core/cortex_m/swap_helper.S
+++ b/arch/arm/core/cortex_m/swap_helper.S
@@ -159,9 +159,13 @@ SECTION_FUNC(TEXT, z_arm_pendsv)
 
 #if defined(CONFIG_THREAD_LOCAL_STORAGE)
     /* Grab the TLS pointer */
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
     ldr r4, =_thread_offset_to_tls
     adds r4, r2, r4
     ldr r0, [r4]
+#else
+    ldr r0, [r2, #_thread_offset_to_tls]
+#endif
 
     /* For Cortex-M, store TLS pointer in a global variable,
      * as it lacks the process ID or thread ID register
diff --git a/arch/arm/core/cortex_m/thread.c b/arch/arm/core/cortex_m/thread.c
index c88fd8e41a0..f1fc2019d9c 100644
--- a/arch/arm/core/cortex_m/thread.c
+++ b/arch/arm/core/cortex_m/thread.c
@@ -22,15 +22,14 @@
 #include <cmsis_core.h>
 
 #if (MPU_GUARD_ALIGN_AND_SIZE_FLOAT > MPU_GUARD_ALIGN_AND_SIZE)
-#define FP_GUARD_EXTRA_SIZE	(MPU_GUARD_ALIGN_AND_SIZE_FLOAT - \
-				 MPU_GUARD_ALIGN_AND_SIZE)
+#define FP_GUARD_EXTRA_SIZE (MPU_GUARD_ALIGN_AND_SIZE_FLOAT - MPU_GUARD_ALIGN_AND_SIZE)
 #else
-#define FP_GUARD_EXTRA_SIZE	0
+#define FP_GUARD_EXTRA_SIZE 0
 #endif
 
 #ifndef EXC_RETURN_FTYPE
 /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
-#define EXC_RETURN_FTYPE           (0x00000010UL)
+#define EXC_RETURN_FTYPE (0x00000010UL)
 #endif
 
 /* Default last octet of EXC_RETURN, for threads that have not run yet.
@@ -58,9 +57,8 @@ K_THREAD_STACK_DECLARE(z_main_stack, CONFIG_MAIN_STACK_SIZE);
  * addresses, we have to unset it manually before storing it in the 'pc' field
  * of the ESF.
  */
-void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
-		     char *stack_ptr, k_thread_entry_t entry,
-		     void *p1, void *p2, void *p3)
+void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack, char *stack_ptr,
+		     k_thread_entry_t entry, void *p1, void *p2, void *p3)
 {
 	struct __basic_sf *iframe;
 
@@ -105,8 +103,7 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 	iframe->a3 = (uint32_t)p2;
 	iframe->a4 = (uint32_t)p3;
 
-	iframe->xpsr =
-		0x01000000UL; /* clear all, thumb bit is 1, even if RO */
+	iframe->xpsr = 0x01000000UL; /* clear all, thumb bit is 1, even if RO */
 
 	thread->callee_saved.psp = (uint32_t)iframe;
 	thread->arch.basepri = 0;
@@ -131,52 +128,42 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 	 */
 }
 
-#if defined(CONFIG_MPU_STACK_GUARD) && defined(CONFIG_FPU) \
-	&& defined(CONFIG_FPU_SHARING)
+#if defined(CONFIG_MPU_STACK_GUARD) && defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
 
-static inline void z_arm_thread_stack_info_adjust(struct k_thread *thread,
-	bool use_large_guard)
+static inline void z_arm_thread_stack_info_adjust(struct k_thread *thread, bool use_large_guard)
 {
 	if (use_large_guard) {
 		/* Switch to use a large MPU guard if not already. */
-		if ((thread->arch.mode &
-			Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) == 0) {
+		if ((thread->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) == 0) {
 			/* Default guard size is used. Update required. */
 			thread->arch.mode |= Z_ARM_MODE_MPU_GUARD_FLOAT_Msk;
 #if defined(CONFIG_USERSPACE)
 			if (thread->arch.priv_stack_start) {
 				/* User thread */
-				thread->arch.priv_stack_start +=
-					FP_GUARD_EXTRA_SIZE;
+				thread->arch.priv_stack_start += FP_GUARD_EXTRA_SIZE;
 			} else
 #endif /* CONFIG_USERSPACE */
 			{
 				/* Privileged thread */
-				thread->stack_info.start +=
-					FP_GUARD_EXTRA_SIZE;
-				thread->stack_info.size -=
-					FP_GUARD_EXTRA_SIZE;
+				thread->stack_info.start += FP_GUARD_EXTRA_SIZE;
+				thread->stack_info.size -= FP_GUARD_EXTRA_SIZE;
 			}
 		}
 	} else {
 		/* Switch to use the default MPU guard size if not already. */
-		if ((thread->arch.mode &
-			Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) {
+		if ((thread->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) {
 			/* Large guard size is used. Update required. */
 			thread->arch.mode &= ~Z_ARM_MODE_MPU_GUARD_FLOAT_Msk;
 #if defined(CONFIG_USERSPACE)
 			if (thread->arch.priv_stack_start) {
 				/* User thread */
-				thread->arch.priv_stack_start -=
-					FP_GUARD_EXTRA_SIZE;
+				thread->arch.priv_stack_start -= FP_GUARD_EXTRA_SIZE;
 			} else
 #endif /* CONFIG_USERSPACE */
 			{
 				/* Privileged thread */
-				thread->stack_info.start -=
-					FP_GUARD_EXTRA_SIZE;
-				thread->stack_info.size +=
-					FP_GUARD_EXTRA_SIZE;
+				thread->stack_info.start -= FP_GUARD_EXTRA_SIZE;
+				thread->stack_info.size += FP_GUARD_EXTRA_SIZE;
 			}
 		}
 	}
@@ -190,7 +177,7 @@ static inline void z_arm_thread_stack_info_adjust(struct k_thread *thread,
 uint32_t z_arm_mpu_stack_guard_and_fpu_adjust(struct k_thread *thread)
 {
 	if (((thread->base.user_options & K_FP_REGS) != 0) ||
-		((thread->arch.mode_exc_return & EXC_RETURN_FTYPE) == 0)) {
+	    ((thread->arch.mode_exc_return & EXC_RETURN_FTYPE) == 0)) {
 		/* The thread has been pre-tagged (at creation or later) with
 		 * K_FP_REGS, i.e. it is expected to be using the FPU registers
 		 * (if not already). Activate lazy stacking and program a large
@@ -226,13 +213,11 @@ uint32_t z_arm_mpu_stack_guard_and_fpu_adjust(struct k_thread *thread)
 #endif
 
 #ifdef CONFIG_USERSPACE
-FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry,
-					void *p1, void *p2, void *p3)
+FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry, void *p1, void *p2, void *p3)
 {
 
 	/* Set up privileged stack before entering user mode */
-	_current->arch.priv_stack_start =
-		(uint32_t)z_priv_stack_find(_current->stack_obj);
+	_current->arch.priv_stack_start = (uint32_t)z_priv_stack_find(_current->stack_obj);
 #if defined(CONFIG_MPU_STACK_GUARD)
 #if defined(CONFIG_THREAD_STACK_INFO)
 	/* We're dropping to user mode which means the guard area is no
@@ -256,21 +241,19 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry,
 	 */
 #if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
 	_current->arch.priv_stack_start +=
-		((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) ?
-		MPU_GUARD_ALIGN_AND_SIZE_FLOAT : MPU_GUARD_ALIGN_AND_SIZE;
+		((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0)
+			? MPU_GUARD_ALIGN_AND_SIZE_FLOAT
+			: MPU_GUARD_ALIGN_AND_SIZE;
 #else
 	_current->arch.priv_stack_start += MPU_GUARD_ALIGN_AND_SIZE;
 #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
 #endif /* CONFIG_MPU_STACK_GUARD */
 
-	z_arm_userspace_enter(user_entry, p1, p2, p3,
-			     (uint32_t)_current->stack_info.start,
-			     _current->stack_info.size -
-			     _current->stack_info.delta);
+	z_arm_userspace_enter(user_entry, p1, p2, p3, (uint32_t)_current->stack_info.start,
+			      _current->stack_info.size - _current->stack_info.delta);
 	CODE_UNREACHABLE;
 }
 
-
 bool z_arm_thread_is_in_user_mode(void)
 {
 	uint32_t value;
@@ -311,14 +294,12 @@ void configure_builtin_stack_guard(struct k_thread *thread)
 	 * than the default thread stack (ensured by design).
 	 */
 	uint32_t guard_start =
-		((thread->arch.priv_stack_start) &&
-			(__get_PSP() >= thread->arch.priv_stack_start)) ?
-		(uint32_t)thread->arch.priv_stack_start :
-		(uint32_t)thread->stack_obj;
+		((thread->arch.priv_stack_start) && (__get_PSP() >= thread->arch.priv_stack_start))
+			? (uint32_t)thread->arch.priv_stack_start
+			: (uint32_t)thread->stack_obj;
 
 	__ASSERT(thread->stack_info.start == ((uint32_t)thread->stack_obj),
-		"stack_info.start does not point to the start of the"
-		"thread allocated area.");
+		 "stack_info.start does not point to the start of the thread allocated area.");
 #else
 	uint32_t guard_start = thread->stack_info.start;
 #endif
@@ -332,13 +313,11 @@ void configure_builtin_stack_guard(struct k_thread *thread)
 
 #if defined(CONFIG_MPU_STACK_GUARD) || defined(CONFIG_USERSPACE)
 
-#define IS_MPU_GUARD_VIOLATION(guard_start, guard_len, fault_addr, stack_ptr) \
-	((fault_addr != -EINVAL) ? \
-	((fault_addr >= guard_start) && \
-	(fault_addr < (guard_start + guard_len)) && \
-	(stack_ptr < (guard_start + guard_len))) \
-	: \
-	(stack_ptr < (guard_start + guard_len)))
+#define IS_MPU_GUARD_VIOLATION(guard_start, guard_len, fault_addr, stack_ptr)                      \
+	((fault_addr != -EINVAL)                                                                   \
+		 ? ((fault_addr >= guard_start) && (fault_addr < (guard_start + guard_len)) &&     \
+		    (stack_ptr < (guard_start + guard_len)))                                       \
+		 : (stack_ptr < (guard_start + guard_len)))
 
 /**
  * @brief Assess occurrence of current thread's stack corruption
@@ -386,11 +365,10 @@ uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp
 	}
 #endif
 
-#if (defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)) && \
-	defined(CONFIG_MPU_STACK_GUARD)
-	uint32_t guard_len =
-		((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0) ?
-		MPU_GUARD_ALIGN_AND_SIZE_FLOAT : MPU_GUARD_ALIGN_AND_SIZE;
+#if (defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)) && defined(CONFIG_MPU_STACK_GUARD)
+	uint32_t guard_len = ((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0)
+				     ? MPU_GUARD_ALIGN_AND_SIZE_FLOAT
+				     : MPU_GUARD_ALIGN_AND_SIZE;
 #else
 	/* If MPU_STACK_GUARD is not enabled, the guard length is
 	 * effectively zero. Stack overflows may be detected only
@@ -404,10 +382,8 @@ uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp
 		/* User thread */
 		if (z_arm_thread_is_in_user_mode() == false) {
 			/* User thread in privilege mode */
-			if (IS_MPU_GUARD_VIOLATION(
-				thread->arch.priv_stack_start - guard_len,
-					guard_len,
-				fault_addr, psp)) {
+			if (IS_MPU_GUARD_VIOLATION(thread->arch.priv_stack_start - guard_len,
+						   guard_len, fault_addr, psp)) {
 				/* Thread's privilege stack corruption */
 				return thread->arch.priv_stack_start;
 			}
@@ -419,26 +395,21 @@ uint32_t z_check_thread_stack_fail(const uint32_t fault_addr, const uint32_t psp
 		}
 	} else {
 		/* Supervisor thread */
-		if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start -
-				guard_len,
-				guard_len,
-				fault_addr, psp)) {
+		if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len, guard_len,
+					   fault_addr, psp)) {
 			/* Supervisor thread stack corruption */
 			return thread->stack_info.start;
 		}
 	}
 #else /* CONFIG_USERSPACE */
 #if defined(CONFIG_MULTITHREADING)
-	if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len,
-			guard_len,
-			fault_addr, psp)) {
+	if (IS_MPU_GUARD_VIOLATION(thread->stack_info.start - guard_len, guard_len, fault_addr,
+				   psp)) {
 		/* Thread stack corruption */
 		return thread->stack_info.start;
 	}
 #else
-	if (IS_MPU_GUARD_VIOLATION((uint32_t)z_main_stack,
-			guard_len,
-			fault_addr, psp)) {
+	if (IS_MPU_GUARD_VIOLATION((uint32_t)z_main_stack, guard_len, fault_addr, psp)) {
 		/* Thread stack corruption */
 		return (uint32_t)K_THREAD_STACK_BUFFER(z_main_stack);
 	}
@@ -572,23 +543,23 @@ void arch_switch_to_main_thread(struct k_thread *main_thread, char *stack_ptr,
 	 * When calling arch_irq_unlock_outlined, LR is lost which is fine since
 	 * we do not intend to return after calling z_thread_entry.
 	 */
-	__asm__ volatile (
-	"mov   r4,  %0\n"	/* force _main to be stored in a register */
-	"msr   PSP, %1\n"	/* __set_PSP(stack_ptr) */
-
-	"movs  r0,  #0\n"	/* arch_irq_unlock(0) */
-	"ldr   r3, =arch_irq_unlock_outlined\n"
-	"blx   r3\n"
-
-	"mov   r0, r4\n"	/* z_thread_entry(_main, NULL, NULL, NULL) */
-	"movs  r1, #0\n"
-	"movs  r2, #0\n"
-	"movs  r3, #0\n"
-	"ldr   r4, =z_thread_entry\n"
-	"bx    r4\n"		/* We don’t intend to return, so there is no need to link. */
-	:
-	: "r" (_main), "r" (stack_ptr)
-	: "r0", "r1", "r2", "r3", "r4", "ip", "lr", "memory");
+	__asm__ volatile("mov   r4,  %0\n" /* force _main to be stored in a register */
+			 "msr   PSP, %1\n" /* __set_PSP(stack_ptr) */
+
+			 "movs  r0,  #0\n" /* arch_irq_unlock(0) */
+			 "ldr   r3, =arch_irq_unlock_outlined\n"
+			 "blx   r3\n"
+
+			 "mov   r0, r4\n" /* z_thread_entry(_main, NULL, NULL, NULL) */
+			 "movs  r1, #0\n"
+			 "movs  r2, #0\n"
+			 "movs  r3, #0\n"
+			 "ldr   r4, =z_thread_entry\n"
+			 /* We don’t intend to return, so there is no need to link. */
+			 "bx    r4\n"
+			 :
+			 : "r"(_main), "r"(stack_ptr)
+			 : "r0", "r1", "r2", "r3", "r4", "ip", "lr", "memory");
 
 	CODE_UNREACHABLE;
 }
@@ -597,7 +568,7 @@ __used void arch_irq_unlock_outlined(unsigned int key)
 {
 #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 	__enable_fault_irq(); /* alters FAULTMASK */
-	__enable_irq(); /* alters PRIMASK */
+	__enable_irq();       /* alters PRIMASK */
 #endif
 	arch_irq_unlock(key);
 }
@@ -609,14 +580,13 @@ __used unsigned int arch_irq_lock_outlined(void)
 
 #if !defined(CONFIG_MULTITHREADING)
 
-FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(
-	k_thread_entry_t main_entry, void *p1, void *p2, void *p3)
+FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(k_thread_entry_t main_entry, void *p1,
+							  void *p2, void *p3)
 {
 	z_arm_prepare_switch_to_main();
 
 	/* Set PSP to the highest address of the main stack. */
-	char *psp =	K_THREAD_STACK_BUFFER(z_main_stack) +
-		K_THREAD_STACK_SIZEOF(z_main_stack);
+	char *psp = K_THREAD_STACK_BUFFER(z_main_stack) + K_THREAD_STACK_SIZEOF(z_main_stack);
 
 #if defined(CONFIG_BUILTIN_STACK_GUARD)
 	char *psplim = (K_THREAD_STACK_BUFFER(z_main_stack));
@@ -636,31 +606,31 @@ FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(
 	 * with the thread entry process.
 	 */
 
-	__asm__ volatile (
+	__asm__ volatile(
 #ifdef CONFIG_BUILTIN_STACK_GUARD
-	"msr  PSPLIM, %[_psplim]\n" /* __set_PSPLIM(_psplim) */
+		"msr  PSPLIM, %[_psplim]\n" /* __set_PSPLIM(_psplim) */
 #endif
-	"msr  PSP, %[_psp]\n"       /* __set_PSP(psp) */
-	"mov r0, #0\n"
-	"ldr r1, =arch_irq_unlock_outlined\n"
-	"blx r1\n"
-
-	"mov r0, %[_p1]\n"
-	"mov r1, %[_p2]\n"
-	"mov r2, %[_p3]\n"
-	"blx  %[_main_entry]\n"     /* main_entry(p1, p2, p3) */
-
-	"ldr r0, =arch_irq_lock_outlined\n"
-	"blx r0\n"
-	"loop: b loop\n\t"    /* while (true); */
-	:
-	: [_p1]"r" (p1), [_p2]"r" (p2), [_p3]"r" (p3),
-	  [_psp]"r" (psp), [_main_entry]"r" (main_entry)
+		"msr  PSP, %[_psp]\n" /* __set_PSP(psp) */
+		"movs r0, #0\n"
+		"ldr r1, =arch_irq_unlock_outlined\n"
+		"blx r1\n"
+
+		"mov r0, %[_p1]\n"
+		"mov r1, %[_p2]\n"
+		"mov r2, %[_p3]\n"
+		"blx  %[_main_entry]\n" /* main_entry(p1, p2, p3) */
+
+		"ldr r0, =arch_irq_lock_outlined\n"
+		"blx r0\n"
+		"loop: b loop\n\t" /* while (true); */
+		:
+		: [_p1] "r"(p1), [_p2] "r"(p2), [_p3] "r"(p3), [_psp] "r"(psp),
+		  [_main_entry] "r"(main_entry)
 #ifdef CONFIG_BUILTIN_STACK_GUARD
-	, [_psplim]"r" (psplim)
+			  ,
+		  [_psplim] "r"(psplim)
 #endif
-	: "r0", "r1", "r2", "ip", "lr"
-	);
+		: "r0", "r1", "r2", "ip", "lr");
 
 	CODE_UNREACHABLE; /* LCOV_EXCL_LINE */
 }
diff --git a/arch/arm/core/cortex_m/timing.c b/arch/arm/core/cortex_m/timing.c
index 6cb157552ac..2ce7f64552b 100644
--- a/arch/arm/core/cortex_m/timing.c
+++ b/arch/arm/core/cortex_m/timing.c
@@ -73,7 +73,6 @@ static inline uint64_t z_arm_dwt_freq_get(void)
 		} while ((dcyc == 0) || (ddwt == 0));
 
 		dwt_frequency = (cyc_freq * ddwt) / dcyc;
-
 	}
 	return dwt_frequency;
 #endif /* CONFIG_SOC_FAMILY_NORDIC_NRF */
@@ -100,8 +99,7 @@ timing_t arch_timing_counter_get(void)
 	return (timing_t)z_arm_dwt_get_cycles();
 }
 
-uint64_t arch_timing_cycles_get(volatile timing_t *const start,
-				volatile timing_t *const end)
+uint64_t arch_timing_cycles_get(volatile timing_t *const start, volatile timing_t *const end)
 {
 	return ((uint32_t)*end - (uint32_t)*start);
 }
diff --git a/arch/arm/core/cortex_m/tz/CMakeLists.txt b/arch/arm/core/cortex_m/tz/CMakeLists.txt
index 19c67476e40..aac4f651619 100644
--- a/arch/arm/core/cortex_m/tz/CMakeLists.txt
+++ b/arch/arm/core/cortex_m/tz/CMakeLists.txt
@@ -2,7 +2,10 @@
 
 # '-mcmse' enables the generation of code for the Secure state of the ARMv8-M
 # Security Extensions. This option is required when building a Secure firmware.
-zephyr_compile_options_ifdef(CONFIG_ARM_SECURE_FIRMWARE -mcmse)
+
+zephyr_compile_options_ifdef(CONFIG_ARM_SECURE_FIRMWARE $<$<COMPILE_LANGUAGE:C>:$<TARGET_PROPERTY:compiler,cmse>>)
+zephyr_compile_options_ifdef(CONFIG_ARM_SECURE_FIRMWARE $<$<COMPILE_LANGUAGE:CXX>:$<TARGET_PROPERTY:compiler,cmse>>)
+zephyr_compile_options_ifdef(CONFIG_ARM_SECURE_FIRMWARE $<$<COMPILE_LANGUAGE:ASM>:$<TARGET_PROPERTY:asm,cmse>>)
 
 if(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)
 
diff --git a/arch/arm/core/elf.c b/arch/arm/core/elf.c
index 5fdc5471a6b..d44e7dd2e2c 100644
--- a/arch/arm/core/elf.c
+++ b/arch/arm/core/elf.c
@@ -7,6 +7,7 @@
 
 #include <zephyr/llext/elf.h>
 #include <zephyr/llext/llext.h>
+#include <zephyr/llext/llext_internal.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/sys/util.h>
 
@@ -316,11 +317,32 @@ static void thm_movs_handler(elf_word reloc_type, uint32_t loc,
  * Do NOT mix them with not 'Thumb instructions' in the below switch/case: they are not
  * intended to work together.
  */
-int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc, uintptr_t sym_base_addr,
-			const char *sym_name, uintptr_t load_bias)
+int arch_elf_relocate(struct llext_loader *ldr, struct llext *ext, elf_rela_t *rel,
+		      const elf_shdr_t *shdr)
 {
 	int ret = 0;
 	elf_word reloc_type = ELF32_R_TYPE(rel->r_info);
+	const uintptr_t load_bias = (uintptr_t)ext->mem[LLEXT_MEM_TEXT];
+	const uintptr_t loc = llext_get_reloc_instruction_location(ldr, ext, shdr->sh_info, rel);
+	elf_sym_t sym;
+	uintptr_t sym_base_addr;
+	const char *sym_name;
+
+	ret = llext_read_symbol(ldr, ext, rel, &sym);
+
+	if (ret != 0) {
+		LOG_ERR("Could not read symbol from binary!");
+		return ret;
+	}
+
+	sym_name = llext_symbol_name(ldr, ext, &sym);
+
+	ret = llext_lookup_symbol(ldr, ext, &sym_base_addr, rel, &sym, sym_name, shdr);
+
+	if (ret != 0) {
+		LOG_ERR("Could not find symbol %s!", sym_name);
+		return ret;
+	}
 
 	LOG_DBG("%d %lx %lx %s", reloc_type, loc, sym_base_addr, sym_name);
 
diff --git a/arch/arm/core/mmu/arm_mmu.c b/arch/arm/core/mmu/arm_mmu.c
index f37b4354d46..62ef1492557 100644
--- a/arch/arm/core/mmu/arm_mmu.c
+++ b/arch/arm/core/mmu/arm_mmu.c
@@ -304,13 +304,15 @@ static struct arm_mmu_perms_attrs arm_mmu_convert_attr_flags(uint32_t attrs)
 		perms_attrs.cacheable = 0;
 		perms_attrs.domain    = ARM_MMU_DOMAIN_DEVICE;
 
-		if (attrs & MATTR_SHARED) {
-			perms_attrs.tex        = 0;
-			perms_attrs.bufferable = 1;
-		} else {
-			perms_attrs.tex        = 2;
-			perms_attrs.bufferable = 0;
-		}
+		/*
+		 * ARM deprecates the marking of Device memory with a
+		 * shareability attribute other than Outer Shareable
+		 * or Shareable. This means ARM strongly recommends
+		 * that Device memory is never assigned a shareability
+		 * attribute of Non-shareable or Inner Shareable.
+		 */
+		perms_attrs.tex        = 0;
+		perms_attrs.bufferable = 1;
 	} else if (attrs & MT_NORMAL) {
 		/*
 		 * TEX[2] is always 1. TEX[1:0] contain the outer cache attri-
@@ -803,10 +805,10 @@ int z_arm_mmu_init(void)
 	}
 
 	/* Clear TTBR1 */
-	__asm__ __volatile__("mcr p15, 0, %0, c2, c0, 1" : : "r"(reg_val));
+	__asm__ volatile("mcr p15, 0, %0, c2, c0, 1" : : "r"(reg_val));
 
 	/* Write TTBCR: EAE, security not yet relevant, N[2:0] = 0 */
-	__asm__ __volatile__("mcr p15, 0, %0, c2, c0, 2"
+	__asm__ volatile("mcr p15, 0, %0, c2, c0, 2"
 			     : : "r"(reg_val));
 
 	/* Write TTBR0 */
diff --git a/arch/arm/core/mpu/Kconfig b/arch/arm/core/mpu/Kconfig
index 0c1fbbf4c0f..ff48692ec65 100644
--- a/arch/arm/core/mpu/Kconfig
+++ b/arch/arm/core/mpu/Kconfig
@@ -1,54 +1,15 @@
 # Memory Protection Unit (MPU) configuration options
 
 # Copyright (c) 2017 Linaro Limited
+# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 if CPU_HAS_MPU
 
-config ARM_MPU
-	bool "ARM MPU Support"
-	select MPU
-	select SRAM_REGION_PERMISSIONS
-	select THREAD_STACK_INFO
-	select ARCH_HAS_EXECUTABLE_PAGE_BIT
-	select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT if !(CPU_HAS_NXP_SYSMPU || ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R)
-	select MPU_REQUIRES_NON_OVERLAPPING_REGIONS if CPU_HAS_ARM_MPU && (ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R)
-	select MPU_GAP_FILLING if AARCH32_ARMV8_R
-	select ARCH_MEM_DOMAIN_SUPPORTS_ISOLATED_STACKS
-	select MEM_DOMAIN_ISOLATED_STACKS
-	help
-	  MCU implements Memory Protection Unit.
-
-	  Notes:
-	  The ARMv6-M and ARMv7-M MPU architecture requires a power-of-two
-	  alignment of MPU region base address and size.
-
-	  The NXP MPU as well as the ARMv8-M MPU do not require MPU regions
-	  to have power-of-two alignment for base address and region size.
-
-	  The ARMv8-M MPU requires the active MPU regions be non-overlapping.
-	  As a result of this, the ARMv8-M MPU needs to fully partition the
-	  memory map when programming dynamic memory regions (e.g. PRIV stack
-	  guard, user thread stack, and application memory domains), if the
-	  system requires PRIV access policy different from the access policy
-	  of the ARMv8-M background memory map. The application developer may
-	  enforce full PRIV (kernel) memory partition by enabling the
-	  CONFIG_MPU_GAP_FILLING option.
-	  By not enforcing full partition, MPU may leave part of kernel
-	  SRAM area covered only by the default ARMv8-M memory map. This
-	  is fine for User Mode, since the background ARM map does not
-	  allow nPRIV access at all. However, since the background map
-	  policy allows instruction fetches by privileged code, forcing
-	  this Kconfig option off prevents the system from directly
-	  triggering MemManage exceptions upon accidental attempts to
-	  execute code from SRAM in XIP builds.
-	  Since this does not compromise User Mode, we make the skipping
-	  of full partitioning the default behavior for the ARMv8-M MPU
-	  driver.
-
 config ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
 	int
 	default 256 if ARM_MPU && ARMV6_M_ARMV8_M_BASELINE && !ARMV8_M_BASELINE
+	default 128 if ARM_MPU && FPU_SHARING && MPU_STACK_GUARD
 	default 64 if ARM_MPU && AARCH32_ARMV8_R
 	default 32 if ARM_MPU
 	default 4
@@ -108,6 +69,15 @@ config CUSTOM_SECTION_MIN_ALIGN_SIZE
 	  size is configured by users, it must also respect the power of
 	  two regulation if hardware requires.
 
+config ARM_MPU_PXN
+	bool
+	depends on ARMV8_1_M_MAINLINE
+	help
+	  Enable support for Armv8.1-m MPU's Privileged Execute Never (PXN) attr.
+	  An MPU region marked with PXN attribute can only be executed from an
+	  unprivileged mode and executing such region from privileged mode will
+	  result in a Memory Management fault.
+
 endif # ARM_MPU
 
 endif # CPU_HAS_MPU
diff --git a/arch/arm/core/mpu/arm_core_mpu.c b/arch/arm/core/mpu/arm_core_mpu.c
index dde98c0b07f..2426b85aacb 100644
--- a/arch/arm/core/mpu/arm_core_mpu.c
+++ b/arch/arm/core/mpu/arm_core_mpu.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2017 Linaro Limited.
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -62,55 +63,80 @@ extern char __ram_text_reloc_start[];
 extern char __ram_text_reloc_size[];
 #endif
 
+#if defined(CONFIG_SRAM_VECTOR_TABLE)
+extern char _sram_vector_start[];
+extern char _sram_vector_size[];
+#endif
+
 static const struct z_arm_mpu_partition static_regions[] = {
 #if defined(CONFIG_COVERAGE_GCOV) && defined(CONFIG_USERSPACE)
-		{
+	{
 		/* GCOV code coverage accounting area. Needs User permissions
 		 * to function
 		 */
 		.start = (uint32_t)&__gcov_bss_start,
 		.size = (uint32_t)&__gcov_bss_size,
 		.attr = K_MEM_PARTITION_P_RW_U_RW,
-		},
+	},
 #endif /* CONFIG_COVERAGE_GCOV && CONFIG_USERSPACE */
 #if defined(CONFIG_NOCACHE_MEMORY)
-		{
+	{
 		/* Special non-cacheable RAM area */
 		.start = (uint32_t)&_nocache_ram_start,
 		.size = (uint32_t)&_nocache_ram_size,
 		.attr = K_MEM_PARTITION_P_RW_U_NA_NOCACHE,
-		},
+	},
 #endif /* CONFIG_NOCACHE_MEMORY */
 #if defined(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT)
-		{
+	{
 		/* Special RAM area for program text */
 		.start = (uint32_t)&__ramfunc_start,
 		.size = (uint32_t)&__ramfunc_size,
+#if defined(CONFIG_ARM_MPU_PXN) && defined(CONFIG_USERSPACE)
+		.attr = K_MEM_PARTITION_P_R_U_RX,
+#else
 		.attr = K_MEM_PARTITION_P_RX_U_RX,
-		},
+#endif
+	},
 #endif /* CONFIG_ARCH_HAS_RAMFUNC_SUPPORT */
 #if defined(CONFIG_CODE_DATA_RELOCATION_SRAM)
-		{
+	{
 		/* RAM area for relocated text */
 		.start = (uint32_t)&__ram_text_reloc_start,
 		.size = (uint32_t)&__ram_text_reloc_size,
+#if defined(CONFIG_ARM_MPU_PXN) && defined(CONFIG_USERSPACE)
+		.attr = K_MEM_PARTITION_P_R_U_RX,
+#else
 		.attr = K_MEM_PARTITION_P_RX_U_RX,
-		},
+#endif
+	},
 #endif /* CONFIG_CODE_DATA_RELOCATION_SRAM */
+#if defined(CONFIG_SRAM_VECTOR_TABLE)
+	{
+		/* Vector table in SRAM */
+		.start = (uint32_t)&_sram_vector_start,
+		.size = (uint32_t)&_sram_vector_size,
+#if defined(CONFIG_ARM_MPU_PXN) && defined(CONFIG_USERSPACE)
+		.attr = K_MEM_PARTITION_P_R_U_RX,
+#else
+		.attr = K_MEM_PARTITION_P_RO_U_RO,
+#endif
+	},
+#endif /* CONFIG_SRAM_VECTOR_TABLE */
 #if !defined(CONFIG_MULTITHREADING) && defined(CONFIG_MPU_STACK_GUARD)
-		/* Main stack MPU guard to detect overflow.
-		 * Note:
-		 * FPU_SHARING and USERSPACE are not supported features
-		 * under CONFIG_MULTITHREADING=n, so the MPU guard (if
-		 * exists) is reserved aside of CONFIG_MAIN_STACK_SIZE
-		 * and there is no requirement for larger guard area (FP
-		 * context is not stacked).
-		 */
-		{
-			.start = (uint32_t)z_main_stack,
-			.size = (uint32_t)MPU_GUARD_ALIGN_AND_SIZE,
-			.attr = K_MEM_PARTITION_P_RO_U_NA,
-		},
+	/* Main stack MPU guard to detect overflow.
+	 * Note:
+	 * FPU_SHARING and USERSPACE are not supported features
+	 * under CONFIG_MULTITHREADING=n, so the MPU guard (if
+	 * exists) is reserved aside of CONFIG_MAIN_STACK_SIZE
+	 * and there is no requirement for larger guard area (FP
+	 * context is not stacked).
+	 */
+	{
+		.start = (uint32_t)z_main_stack,
+		.size = (uint32_t)MPU_GUARD_ALIGN_AND_SIZE,
+		.attr = K_MEM_PARTITION_P_RO_U_NA,
+	},
 #endif /* !CONFIG_MULTITHREADING && CONFIG_MPU_STACK_GUARD */
 };
 
diff --git a/arch/arm/core/mpu/arm_mpu.c b/arch/arm/core/mpu/arm_mpu.c
index f121e57e392..f9a5397da46 100644
--- a/arch/arm/core/mpu/arm_mpu.c
+++ b/arch/arm/core/mpu/arm_mpu.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2017 Linaro Limited.
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -42,7 +43,8 @@ BUILD_ASSERT((DT_FOREACH_STATUS_OKAY_NODE_VARGS(
 	 (DT_REG_SIZE(node_id) >= CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE)) ||
 
 #define DT_NULL_PAGE_DETECT_NODE_EXIST                                                             \
-	(DT_FOREACH_STATUS_OKAY_NODE_VARGS(NULL_PAGE_DETECT_NODE_FINDER, zephyr_memory_attr) false)
+	(DT_FOREACH_STATUS_OKAY_VARGS(zephyr_memory_region, NULL_PAGE_DETECT_NODE_FINDER,          \
+				      zephyr_memory_attr) false)
 
 /*
  * Global status variable holding the number of HW MPU region indices, which
@@ -92,7 +94,7 @@ static int region_allocate_and_init(const uint8_t index,
 						    (reg).dt_addr,	\
 						    (reg).dt_size,	\
 						    _ATTR)
-
+#ifdef CONFIG_MEM_ATTR
 /* This internal function programs the MPU regions defined in the DT when using
  * the `zephyr,memory-attr = <( DT_MEM_ARM(...) )>` property.
  */
@@ -110,6 +112,11 @@ static int mpu_configure_regions_from_dt(uint8_t *reg_index)
 		case DT_MEM_ARM_MPU_RAM:
 			region_conf = _BUILD_REGION_CONF(region[idx], REGION_RAM_ATTR);
 			break;
+#ifdef CONFIG_ARM_MPU_PXN
+		case DT_MEM_ARM_MPU_RAM_PXN:
+			region_conf = _BUILD_REGION_CONF(region[idx], REGION_RAM_ATTR_PXN);
+			break;
+#endif
 #ifdef REGION_RAM_NOCACHE_ATTR
 		case DT_MEM_ARM_MPU_RAM_NOCACHE:
 			region_conf = _BUILD_REGION_CONF(region[idx], REGION_RAM_NOCACHE_ATTR);
@@ -157,7 +164,7 @@ static int mpu_configure_regions_from_dt(uint8_t *reg_index)
 
 	return 0;
 }
-
+#endif /* CONFIG_MEM_ATTR */
 /* This internal function programs an MPU region
  * of a given configuration at a given MPU index.
  */
@@ -458,13 +465,13 @@ int z_arm_mpu_init(void)
 
 	/* Update the number of programmed MPU regions. */
 	static_regions_num = mpu_config.num_regions;
-
+#ifdef CONFIG_MEM_ATTR
 	/* DT-defined MPU regions. */
 	if (mpu_configure_regions_from_dt(&static_regions_num) == -EINVAL) {
 		__ASSERT(0, "Failed to allocate MPU regions from DT\n");
 		return -EINVAL;
 	}
-
+#endif /* CONFIG_MEM_ATTR */
 	/* Clear all regions before enabling MPU */
 	for (int i = static_regions_num; i < get_num_regions(); i++) {
 		mpu_clear_region(i);
diff --git a/arch/arm/core/mpu/arm_mpu_v8_internal.h b/arch/arm/core/mpu/arm_mpu_v8_internal.h
index 51ab093d17c..0716c017ff9 100644
--- a/arch/arm/core/mpu/arm_mpu_v8_internal.h
+++ b/arch/arm/core/mpu/arm_mpu_v8_internal.h
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2017 Linaro Limited.
  * Copyright (c) 2018 Nordic Semiconductor ASA.
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -158,6 +159,7 @@ static void mpu_set_region(uint32_t rnr, uint32_t rbar, uint32_t rlar)
 static void region_init(const uint32_t index,
 	const struct arm_mpu_region *region_conf)
 {
+	/* clang-format off */
 	mpu_set_region(
 		/* RNR */
 		index,
@@ -170,7 +172,11 @@ static void region_init(const uint32_t index,
 		| ((region_conf->attr.mair_idx << MPU_RLAR_AttrIndx_Pos)
 			& MPU_RLAR_AttrIndx_Msk)
 		| MPU_RLAR_EN_Msk
+#ifdef CONFIG_ARM_MPU_PXN
+		| ((region_conf->attr.pxn << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk)
+#endif
 	);
+	/* clang-format on */
 
 	LOG_DBG("[%d] 0x%08x 0x%08x 0x%08x 0x%08x",
 			index, region_conf->base, region_conf->attr.rbar,
@@ -279,6 +285,9 @@ static inline void mpu_region_get_access_attr(const uint32_t index,
 		(MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk);
 	attr->mair_idx = (mpu_get_rlar() & MPU_RLAR_AttrIndx_Msk) >>
 		MPU_RLAR_AttrIndx_Pos;
+#ifdef CONFIG_ARM_MPU_PXN
+	attr->pxn = (mpu_get_rlar() & MPU_RLAR_PXN_Msk) >> MPU_RLAR_PXN_Pos;
+#endif
 }
 
 static inline void mpu_region_get_conf(const uint32_t index,
@@ -313,6 +322,9 @@ static inline void get_region_attr_from_mpu_partition_info(
 		(MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk);
 	p_attr->mair_idx = attr->mair_idx;
 	p_attr->r_limit = REGION_LIMIT_ADDR(base, size);
+#ifdef CONFIG_ARM_MPU_PXN
+	p_attr->pxn = attr->pxn;
+#endif
 }
 
 #if defined(CONFIG_USERSPACE)
diff --git a/arch/arm/core/mpu/nxp_mpu.c b/arch/arm/core/mpu/nxp_mpu.c
index b0fe24c6bf6..ae893086901 100644
--- a/arch/arm/core/mpu/nxp_mpu.c
+++ b/arch/arm/core/mpu/nxp_mpu.c
@@ -151,7 +151,7 @@ static int region_allocate_and_init(const uint8_t index,
 				  .end  = (reg).dt_addr + (reg).dt_size,	\
 				  .attr = _ATTR,				\
 				}
-
+#ifdef CONFIG_MEM_ATTR
 /* This internal function programs the MPU regions defined in the DT when using
  * the `zephyr,memory-attr = <( DT_MEM_ARM(...) )>` property.
  */
@@ -198,7 +198,7 @@ static int mpu_configure_regions_from_dt(uint8_t *reg_index)
 
 	return 0;
 }
-
+#endif /* CONFIG_MEM_ATTR */
 /**
  * This internal function is utilized by the MPU driver to combine a given
  * region attribute configuration and size and fill-in a driver-specific
@@ -700,13 +700,13 @@ int z_arm_mpu_init(void)
 
 	/* Update the number of programmed MPU regions. */
 	static_regions_num = mpu_config.num_regions;
-
+#ifdef CONFIG_MEM_ATTR
 	/* DT-defined MPU regions. */
 	if (mpu_configure_regions_from_dt(&static_regions_num) == -EINVAL) {
 		__ASSERT(0, "Failed to allocate MPU regions from DT\n");
 		return -EINVAL;
 	}
-
+#endif /* CONFIG_MEM_ATTR */
 	arm_core_mpu_enable();
 
 	return 0;
diff --git a/arch/arm/core/tls.c b/arch/arm/core/tls.c
index 9b731286c7d..0dc21285a91 100644
--- a/arch/arm/core/tls.c
+++ b/arch/arm/core/tls.c
@@ -40,8 +40,10 @@ size_t arch_tls_stack_setup(struct k_thread *new_thread, char *stack_ptr)
 	stack_ptr -= z_tls_data_size();
 	z_tls_copy(stack_ptr);
 
+#ifndef __IAR_SYSTEMS_ICC__
 	/* Skip two pointers due to toolchain */
 	stack_ptr -= sizeof(uintptr_t) * 2;
+#endif
 
 	/*
 	 * Set thread TLS pointer which is used in
diff --git a/arch/arm/include/cortex_m/cmse.h b/arch/arm/include/cortex_m/cmse.h
index ff5e5120d8d..ca997220dbd 100644
--- a/arch/arm/include/cortex_m/cmse.h
+++ b/arch/arm/include/cortex_m/cmse.h
@@ -139,7 +139,7 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr
  * where typeof is used instead of __typeof__)
  */
 #ifndef typeof
-#define typeof  __typeof__
+#define typeof __typeof__
 #endif
 
 /**
@@ -157,8 +157,7 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr
  *
  * @return p_obj if object is readable, NULL otherwise.
  */
-#define ARM_CMSE_OBJECT_READ_OK(p_obj) \
-	cmse_check_pointed_object(p_obj, CMSE_MPU_READ)
+#define ARM_CMSE_OBJECT_READ_OK(p_obj) cmse_check_pointed_object(p_obj, CMSE_MPU_READ)
 
 /**
  * @brief Read accessibility of an object (nPRIV mode)
@@ -175,7 +174,7 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr
  *
  * @return p_obj if object is readable, NULL otherwise.
  */
-#define ARM_CMSE_OBJECT_UNPRIV_READ_OK(p_obj) \
+#define ARM_CMSE_OBJECT_UNPRIV_READ_OK(p_obj)                                                      \
 	cmse_check_pointed_object(p_obj, CMSE_MPU_UNPRIV | CMSE_MPU_READ)
 
 /**
@@ -193,8 +192,7 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr
  *
  * @return p_obj if object is Read and Writable, NULL otherwise.
  */
-#define ARM_CMSE_OBJECT_READWRITE_OK(p_obj) \
-	cmse_check_pointed_object(p_obj, CMSE_MPU_READWRITE)
+#define ARM_CMSE_OBJECT_READWRITE_OK(p_obj) cmse_check_pointed_object(p_obj, CMSE_MPU_READWRITE)
 
 /**
  * @brief Read and Write accessibility of an object (nPRIV mode)
@@ -211,7 +209,7 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr
  *
  * @return p_obj if object is Read and Writable, NULL otherwise.
  */
-#define ARM_CMSE_OBJECT_UNPRIV_READWRITE_OK(p_obj) \
+#define ARM_CMSE_OBJECT_UNPRIV_READWRITE_OK(p_obj)                                                 \
 	cmse_check_pointed_object(p_obj, CMSE_MPU_UNPRIV | CMSE_MPU_READWRITE)
 
 #if defined(CONFIG_ARM_SECURE_FIRMWARE)
@@ -231,7 +229,7 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr
  * @param addr The address for which the MPU region is requested
  *
  * @return a valid MPU region number or -EINVAL
-  */
+ */
 int arm_cmse_mpu_nonsecure_region_get(uint32_t addr);
 
 /**
@@ -249,7 +247,7 @@ int arm_cmse_mpu_nonsecure_region_get(uint32_t addr);
  * @param addr The address for which the SAU region is requested
  *
  * @return a valid SAU region number or -EINVAL
-  */
+ */
 int arm_cmse_sau_region_get(uint32_t addr);
 
 /**
@@ -267,7 +265,7 @@ int arm_cmse_sau_region_get(uint32_t addr);
  * @param addr The address for which the IDAU region is requested
  *
  * @return a valid IDAU region number or -EINVAL
-  */
+ */
 int arm_cmse_idau_region_get(uint32_t addr);
 
 /**
@@ -342,8 +340,7 @@ int arm_cmse_addr_nonsecure_readwrite_ok(uint32_t addr, int force_npriv);
  *
  * @return 1 if address range is readable, 0 otherwise.
  */
-int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size,
-	int force_npriv);
+int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size, int force_npriv);
 
 /**
  * @brief Non-Secure Read and Write accessibility of an address range
@@ -365,8 +362,7 @@ int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size,
  *
  * @return 1 if address range is readable, 0 otherwise.
  */
-int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size,
-	int force_npriv);
+int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, int force_npriv);
 
 /**
  * @brief Non-Secure Read accessibility of an object
@@ -383,7 +379,7 @@ int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size,
  *
  * @return p_obj if object is readable from Non-Secure state, NULL otherwise.
  */
-#define ARM_CMSE_OBJECT_NONSECURE_READ_OK(p_obj) \
+#define ARM_CMSE_OBJECT_NONSECURE_READ_OK(p_obj)                                                   \
 	cmse_check_pointed_object(p_obj, CMSE_NONSECURE | CMSE_MPU_READ)
 
 /**
@@ -401,9 +397,8 @@ int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size,
  *
  * @return p_obj if object is readable from Non-Secure state, NULL otherwise.
  */
-#define ARM_CMSE_OBJECT_NONSECURE_UNPRIV_READ_OK(p_obj) \
-	cmse_check_pointed_object(p_obj, \
-		CMSE_NONSECURE | CMSE_MPU_UNPRIV | CMSE_MPU_READ)
+#define ARM_CMSE_OBJECT_NONSECURE_UNPRIV_READ_OK(p_obj)                                            \
+	cmse_check_pointed_object(p_obj, CMSE_NONSECURE | CMSE_MPU_UNPRIV | CMSE_MPU_READ)
 
 /**
  * @brief Non-Secure Read and Write accessibility of an object
@@ -420,7 +415,7 @@ int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size,
  *
  * @return p_obj if object is Non-Secure Read and Writable, NULL otherwise.
  */
-#define ARM_CMSE_OBJECT_NONSECURE_READWRITE_OK(p_obj) \
+#define ARM_CMSE_OBJECT_NONSECURE_READWRITE_OK(p_obj)                                              \
 	cmse_check_pointed_object(p_obj, CMSE_NONSECURE | CMSE_MPU_READWRITE)
 
 /**
@@ -438,9 +433,8 @@ int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size,
  *
  * @return p_obj if object is Non-Secure Read and Writable, NULL otherwise.
  */
-#define ARM_CMSE_OBJECT_NON_SECURE_UNPRIV_READWRITE_OK(p_obj) \
-	cmse_check_pointed_object(p_obj, \
-			CMSE_NONSECURE | CMSE_MPU_UNPRIV | CMSE_MPU_READWRITE)
+#define ARM_CMSE_OBJECT_NON_SECURE_UNPRIV_READWRITE_OK(p_obj)                                      \
+	cmse_check_pointed_object(p_obj, CMSE_NONSECURE | CMSE_MPU_UNPRIV | CMSE_MPU_READWRITE)
 
 #endif /* CONFIG_ARM_SECURE_FIRMWARE */
 
diff --git a/arch/arm/include/cortex_m/dwt.h b/arch/arm/include/cortex_m/dwt.h
index ed0df44dfde..947b35dca92 100644
--- a/arch/arm/include/cortex_m/dwt.h
+++ b/arch/arm/include/cortex_m/dwt.h
@@ -64,7 +64,7 @@ static inline void dwt_access(bool ena)
 			}
 		}
 	}
-#else /* CONFIG_CPU_CORTEX_M7 */
+#else  /* CONFIG_CPU_CORTEX_M7 */
 	ARG_UNUSED(ena);
 #endif /* CONFIG_CPU_CORTEX_M7 */
 }
@@ -103,9 +103,8 @@ static inline int z_arm_dwt_init_cycle_counter(void)
 	/* Assert that the cycle counter is indeed implemented.
 	 * The field is called NOCYCCNT. So 1 means there is no cycle counter.
 	 */
-	__ASSERT((DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk) == 0,
-		"DWT implements no cycle counter. "
-		"Cannot be used for cycle counting\n");
+	__ASSERT((DWT->CTRL & DWT_CTRL_NOCYCCNT_Msk) == 0, "DWT implements no cycle counter. "
+							   "Cannot be used for cycle counting\n");
 
 	return 0;
 }
@@ -148,7 +147,7 @@ static inline void z_arm_dwt_enable_debug_monitor(void)
 	 * assert that the CPU is in normal mode.
 	 */
 	__ASSERT((CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) == 0,
-		"Cannot enable DBM when CPU is in Debug mode\n");
+		 "Cannot enable DBM when CPU is in Debug mode\n");
 
 #if defined(CONFIG_ARMV8_M_SE) && !defined(CONFIG_ARM_NONSECURE_FIRMWARE)
 	/*
@@ -158,8 +157,7 @@ static inline void z_arm_dwt_enable_debug_monitor(void)
 	 * when enabling the DebugMonitor exception, assert that
 	 * it is not targeting the Non Secure domain.
 	 */
-	__ASSERT((CoreDebug->DEMCR & DCB_DEMCR_SDME_Msk) != 0,
-		"DebugMonitor targets Non-Secure\n");
+	__ASSERT((CoreDebug->DEMCR & DCB_DEMCR_SDME_Msk) != 0, "DebugMonitor targets Non-Secure\n");
 #endif
 
 	/* The DebugMonitor handler priority is set already
diff --git a/arch/arm/include/cortex_m/exception.h b/arch/arm/include/cortex_m/exception.h
index c021d59d764..0800a16436f 100644
--- a/arch/arm/include/cortex_m/exception.h
+++ b/arch/arm/include/cortex_m/exception.h
@@ -37,7 +37,7 @@ extern volatile irq_offload_routine_t offload_routine;
 /* Writes to the AIRCR must be accompanied by a write of the value 0x05FA
  * to the Vector Key field, otherwise the writes are ignored.
  */
-#define AIRCR_VECT_KEY_PERMIT_WRITE 0x05FAUL
+#define AIRCR_VECT_KEY_PERMIT_WRITE            0x05FAUL
 
 /* Exception Return (EXC_RETURN) is provided in LR upon exception entry.
  * It is used to perform an exception return and to detect possible state
@@ -47,45 +47,44 @@ extern volatile irq_offload_routine_t offload_routine;
 /* Prefix. Indicates that this is an EXC_RETURN value.
  * This field reads as 0b11111111.
  */
-#define EXC_RETURN_INDICATOR_PREFIX     (0xFF << 24)
+#define EXC_RETURN_INDICATOR_PREFIX            (0xFF << 24)
 /* bit[0]: Exception Secure. The security domain the exception was taken to. */
-#define EXC_RETURN_EXCEPTION_SECURE_Pos 0
-#define EXC_RETURN_EXCEPTION_SECURE_Msk \
-		BIT(EXC_RETURN_EXCEPTION_SECURE_Pos)
+#define EXC_RETURN_EXCEPTION_SECURE_Pos        0
+#define EXC_RETURN_EXCEPTION_SECURE_Msk        BIT(EXC_RETURN_EXCEPTION_SECURE_Pos)
 #define EXC_RETURN_EXCEPTION_SECURE_Non_Secure 0
-#define EXC_RETURN_EXCEPTION_SECURE_Secure EXC_RETURN_EXCEPTION_SECURE_Msk
+#define EXC_RETURN_EXCEPTION_SECURE_Secure     EXC_RETURN_EXCEPTION_SECURE_Msk
 /* bit[2]: Stack Pointer selection. */
-#define EXC_RETURN_SPSEL_Pos 2
-#define EXC_RETURN_SPSEL_Msk BIT(EXC_RETURN_SPSEL_Pos)
-#define EXC_RETURN_SPSEL_MAIN 0
-#define EXC_RETURN_SPSEL_PROCESS EXC_RETURN_SPSEL_Msk
+#define EXC_RETURN_SPSEL_Pos                   2
+#define EXC_RETURN_SPSEL_Msk                   BIT(EXC_RETURN_SPSEL_Pos)
+#define EXC_RETURN_SPSEL_MAIN                  0
+#define EXC_RETURN_SPSEL_PROCESS               EXC_RETURN_SPSEL_Msk
 /* bit[3]: Mode. Indicates the Mode that was stacked from. */
-#define EXC_RETURN_MODE_Pos 3
-#define EXC_RETURN_MODE_Msk BIT(EXC_RETURN_MODE_Pos)
-#define EXC_RETURN_MODE_HANDLER 0
-#define EXC_RETURN_MODE_THREAD EXC_RETURN_MODE_Msk
+#define EXC_RETURN_MODE_Pos                    3
+#define EXC_RETURN_MODE_Msk                    BIT(EXC_RETURN_MODE_Pos)
+#define EXC_RETURN_MODE_HANDLER                0
+#define EXC_RETURN_MODE_THREAD                 EXC_RETURN_MODE_Msk
 /* bit[4]: Stack frame type. Indicates whether the stack frame is a standard
  * integer only stack frame or an extended floating-point stack frame.
  */
-#define EXC_RETURN_STACK_FRAME_TYPE_Pos 4
-#define EXC_RETURN_STACK_FRAME_TYPE_Msk BIT(EXC_RETURN_STACK_FRAME_TYPE_Pos)
-#define EXC_RETURN_STACK_FRAME_TYPE_EXTENDED 0
-#define EXC_RETURN_STACK_FRAME_TYPE_STANDARD EXC_RETURN_STACK_FRAME_TYPE_Msk
+#define EXC_RETURN_STACK_FRAME_TYPE_Pos        4
+#define EXC_RETURN_STACK_FRAME_TYPE_Msk        BIT(EXC_RETURN_STACK_FRAME_TYPE_Pos)
+#define EXC_RETURN_STACK_FRAME_TYPE_EXTENDED   0
+#define EXC_RETURN_STACK_FRAME_TYPE_STANDARD   EXC_RETURN_STACK_FRAME_TYPE_Msk
 /* bit[5]: Default callee register stacking. Indicates whether the default
  * stacking rules apply, or whether the callee registers are already on the
  * stack.
  */
-#define EXC_RETURN_CALLEE_STACK_Pos 5
-#define EXC_RETURN_CALLEE_STACK_Msk BIT(EXC_RETURN_CALLEE_STACK_Pos)
-#define EXC_RETURN_CALLEE_STACK_SKIPPED 0
-#define EXC_RETURN_CALLEE_STACK_DEFAULT EXC_RETURN_CALLEE_STACK_Msk
+#define EXC_RETURN_CALLEE_STACK_Pos            5
+#define EXC_RETURN_CALLEE_STACK_Msk            BIT(EXC_RETURN_CALLEE_STACK_Pos)
+#define EXC_RETURN_CALLEE_STACK_SKIPPED        0
+#define EXC_RETURN_CALLEE_STACK_DEFAULT        EXC_RETURN_CALLEE_STACK_Msk
 /* bit[6]: Secure or Non-secure stack. Indicates whether a Secure or
  * Non-secure stack is used to restore stack frame on exception return.
  */
-#define EXC_RETURN_RETURN_STACK_Pos 6
-#define EXC_RETURN_RETURN_STACK_Msk BIT(EXC_RETURN_RETURN_STACK_Pos)
-#define EXC_RETURN_RETURN_STACK_Non_Secure 0
-#define EXC_RETURN_RETURN_STACK_Secure EXC_RETURN_RETURN_STACK_Msk
+#define EXC_RETURN_RETURN_STACK_Pos            6
+#define EXC_RETURN_RETURN_STACK_Msk            BIT(EXC_RETURN_RETURN_STACK_Pos)
+#define EXC_RETURN_RETURN_STACK_Non_Secure     0
+#define EXC_RETURN_RETURN_STACK_Secure         EXC_RETURN_RETURN_STACK_Msk
 
 /*
  * The current executing vector is found in the IPSR register. All
@@ -170,8 +169,8 @@ static ALWAYS_INLINE void z_arm_exc_setup(void)
 #endif /* CONFIG_ARM_SECURE_FIRMWARE */
 
 	/* Enable Usage, Mem, & Bus Faults */
-	SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk |
-		      SCB_SHCSR_BUSFAULTENA_Msk;
+	SCB->SHCSR |=
+		SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_MEMFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk;
 #if defined(CONFIG_ARM_SECURE_FIRMWARE)
 	/* Enable Secure Fault */
 	SCB->SHCSR |= SCB_SHCSR_SECUREFAULTENA_Msk;
@@ -180,25 +179,21 @@ static ALWAYS_INLINE void z_arm_exc_setup(void)
 #endif /* CONFIG_ARM_SECURE_FIRMWARE */
 #endif /* CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS */
 
-#if defined(CONFIG_ARM_SECURE_FIRMWARE) && \
-	!defined(CONFIG_ARM_SECURE_BUSFAULT_HARDFAULT_NMI)
+#if defined(CONFIG_ARM_SECURE_FIRMWARE) && !defined(CONFIG_ARM_SECURE_BUSFAULT_HARDFAULT_NMI)
 	/* Set NMI, Hard, and Bus Faults as Non-Secure.
 	 * NMI and Bus Faults targeting the Secure state will
 	 * escalate to a SecureFault or SecureHardFault.
 	 */
 	SCB->AIRCR =
-		(SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk)))
-		| SCB_AIRCR_BFHFNMINS_Msk
-		| ((AIRCR_VECT_KEY_PERMIT_WRITE << SCB_AIRCR_VECTKEY_Pos) &
-			SCB_AIRCR_VECTKEY_Msk);
+		(SCB->AIRCR & (~(SCB_AIRCR_VECTKEY_Msk))) | SCB_AIRCR_BFHFNMINS_Msk |
+		((AIRCR_VECT_KEY_PERMIT_WRITE << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk);
 	/* Note: Fault conditions that would generate a SecureFault
 	 * in a PE with the Main Extension instead generate a
 	 * SecureHardFault in a PE without the Main Extension.
 	 */
 #endif /* ARM_SECURE_FIRMWARE && !ARM_SECURE_BUSFAULT_HARDFAULT_NMI */
 
-#if defined(CONFIG_CPU_CORTEX_M_HAS_SYSTICK) && \
-	!defined(CONFIG_CORTEX_M_SYSTICK)
+#if defined(CONFIG_CPU_CORTEX_M_HAS_SYSTICK) && !defined(CONFIG_CORTEX_M_SYSTICK)
 	/* SoC implements SysTick, but the system does not use it
 	 * as driver for system timing. However, the SysTick IRQ is
 	 * always enabled, so we must ensure the interrupt priority
@@ -208,7 +203,6 @@ static ALWAYS_INLINE void z_arm_exc_setup(void)
 	 */
 	NVIC_SetPriority(SysTick_IRQn, _EXC_IRQ_DEFAULT_PRIO);
 #endif /* CPU_CORTEX_M_HAS_SYSTICK && ! CORTEX_M_SYSTICK */
-
 }
 
 /**
@@ -221,9 +215,7 @@ static ALWAYS_INLINE void z_arm_clear_faults(void)
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 	/* Reset all faults */
-	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk |
-		    SCB_CFSR_MEMFAULTSR_Msk |
-		    SCB_CFSR_BUSFAULTSR_Msk;
+	SCB->CFSR = SCB_CFSR_USGFAULTSR_Msk | SCB_CFSR_MEMFAULTSR_Msk | SCB_CFSR_BUSFAULTSR_Msk;
 
 	/* Clear all Hard Faults - HFSR is write-one-to-clear */
 	SCB->HFSR = 0xffffffff;
@@ -253,7 +245,7 @@ static ALWAYS_INLINE void z_arm_set_fault_sp(const struct arch_esf *esf, uint32_
 	 * registers if necessary
 	 */
 	if ((exc_return & EXC_RETURN_STACK_FRAME_TYPE_STANDARD) ==
-			EXC_RETURN_STACK_FRAME_TYPE_EXTENDED) {
+	    EXC_RETURN_STACK_FRAME_TYPE_EXTENDED) {
 		z_arm_coredump_fault_sp += sizeof(esf->fpu);
 	}
 #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
diff --git a/arch/arm/include/cortex_m/kernel_arch_func.h b/arch/arm/include/cortex_m/kernel_arch_func.h
index 2a24103a32d..5abe5870762 100644
--- a/arch/arm/include/cortex_m/kernel_arch_func.h
+++ b/arch/arm/include/cortex_m/kernel_arch_func.h
@@ -61,26 +61,21 @@ static ALWAYS_INLINE void arch_kernel_init(void)
 #endif /* CONFIG_SOC_PER_CORE_INIT_HOOK */
 }
 
-static ALWAYS_INLINE void
-arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
+static ALWAYS_INLINE void arch_thread_return_value_set(struct k_thread *thread, unsigned int value)
 {
 	thread->arch.swap_return_value = value;
 }
 
 #if !defined(CONFIG_MULTITHREADING)
-extern FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(
-	k_thread_entry_t main_func,
-	void *p1, void *p2, void *p3);
+extern FUNC_NORETURN void z_arm_switch_to_main_no_multithreading(k_thread_entry_t main_func,
+								 void *p1, void *p2, void *p3);
 
-#define ARCH_SWITCH_TO_MAIN_NO_MULTITHREADING \
-	z_arm_switch_to_main_no_multithreading
+#define ARCH_SWITCH_TO_MAIN_NO_MULTITHREADING z_arm_switch_to_main_no_multithreading
 
 #endif /* !CONFIG_MULTITHREADING */
 
-extern FUNC_NORETURN void z_arm_userspace_enter(k_thread_entry_t user_entry,
-					       void *p1, void *p2, void *p3,
-					       uint32_t stack_end,
-					       uint32_t stack_start);
+extern FUNC_NORETURN void z_arm_userspace_enter(k_thread_entry_t user_entry, void *p1, void *p2,
+						void *p3, uint32_t stack_end, uint32_t stack_start);
 
 extern void z_arm_fatal_error(unsigned int reason, const struct arch_esf *esf);
 
@@ -102,7 +97,6 @@ static ALWAYS_INLINE int arch_swap(unsigned int key)
 	return _current->arch.swap_return_value;
 }
 
-
 #endif /* _ASMLANGUAGE */
 
 #ifdef __cplusplus
diff --git a/arch/arm/include/cortex_m/stack.h b/arch/arm/include/cortex_m/stack.h
index feeaf719a88..6b534a3ea5b 100644
--- a/arch/arm/include/cortex_m/stack.h
+++ b/arch/arm/include/cortex_m/stack.h
@@ -26,8 +26,7 @@
 extern "C" {
 #endif
 
-K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS,
-			     CONFIG_ISR_STACK_SIZE);
+K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS, CONFIG_ISR_STACK_SIZE);
 
 /**
  *
@@ -39,9 +38,8 @@ K_KERNEL_STACK_ARRAY_DECLARE(z_interrupt_stacks, CONFIG_MP_MAX_NUM_CPUS,
  */
 static ALWAYS_INLINE void z_arm_interrupt_stack_setup(void)
 {
-	uint32_t msp =
-		(uint32_t)(K_KERNEL_STACK_BUFFER(z_interrupt_stacks[0])) +
-			   K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0]);
+	uint32_t msp = (uint32_t)(K_KERNEL_STACK_BUFFER(z_interrupt_stacks[0])) +
+		       K_KERNEL_STACK_SIZEOF(z_interrupt_stacks[0]);
 
 	__set_MSP(msp);
 #if defined(CONFIG_BUILTIN_STACK_GUARD)
diff --git a/arch/arm/include/cortex_m/tz_ns.h b/arch/arm/include/cortex_m/tz_ns.h
index 51ed5eb1ca9..dd6dcb4c22e 100644
--- a/arch/arm/include/cortex_m/tz_ns.h
+++ b/arch/arm/include/cortex_m/tz_ns.h
@@ -46,24 +46,18 @@
  *                  the functions have been called. This instruction must leave
  *                  r0-r3 unmodified.
  */
-#define __TZ_WRAP_FUNC_RAW(preface, name, postface, store_lr, load_lr) \
-		__asm__ volatile( \
-			".global "#preface"; .type "#preface", %function"); \
-		__asm__ volatile( \
-			".global "#name"; .type "#name", %function"); \
-		__asm__ volatile( \
-			".global "#postface"; .type "#postface", %function"); \
-		__asm__ volatile( \
-			store_lr "\n\t" \
-			"push {r0-r3}\n\t" \
-			"bl " #preface "\n\t" \
-			"pop {r0-r3}\n\t" \
-			"bl " #name " \n\t" \
-			"push {r0-r3}\n\t" \
-			"bl " #postface "\n\t" \
-			"pop {r0-r3}\n\t" \
-			load_lr "\n\t" \
-			::);
+#define __TZ_WRAP_FUNC_RAW(preface, name, postface, store_lr, load_lr)                             \
+	__asm__ volatile(".global " #preface "; .type " #preface ", %function");                   \
+	__asm__ volatile(".global " #name "; .type " #name ", %function");                         \
+	__asm__ volatile(".global " #postface "; .type " #postface ", %function");                 \
+	__asm__ volatile(store_lr "\n\t"                                                           \
+				  "push {r0-r3}\n\t"                                               \
+				  "bl " #preface "\n\t"                                            \
+				  "pop {r0-r3}\n\t"                                                \
+				  "bl " #name "\n\t"                                               \
+				  "push {r0-r3}\n\t"                                               \
+				  "bl " #postface "\n\t"                                           \
+				  "pop {r0-r3}\n\t" load_lr "\n\t" ::);
 
 /**
  * @brief Macro for "sandwiching" a function call (@p name) in two other calls
@@ -98,10 +92,8 @@
  *
  * See @ref __TZ_WRAP_FUNC_RAW for more information.
  */
-#define __TZ_WRAP_FUNC(preface, name, postface) \
-	__TZ_WRAP_FUNC_RAW(preface, name, postface, "push {r4, lr}", \
-			"pop {r4, pc}")
-
+#define __TZ_WRAP_FUNC(preface, name, postface)                                                    \
+	__TZ_WRAP_FUNC_RAW(preface, name, postface, "push {r4, lr}", "pop {r4, pc}")
 
 #ifdef CONFIG_ARM_FIRMWARE_USES_SECURE_ENTRY_FUNCS
 /**
@@ -130,10 +122,10 @@
  * @param ...   The rest of the signature of the function. This must be the same
  *              signature as the corresponding NS entry function.
  */
-#define TZ_THREAD_SAFE_NONSECURE_ENTRY_FUNC(name, ret, nsc_name, ...) \
-	ret __attribute__((naked)) name(__VA_ARGS__) \
-	{ \
-		__TZ_WRAP_FUNC(k_sched_lock, nsc_name, k_sched_unlock); \
+#define TZ_THREAD_SAFE_NONSECURE_ENTRY_FUNC(name, ret, nsc_name, ...)                              \
+	ret __attribute__((naked)) name(__VA_ARGS__)                                               \
+	{                                                                                          \
+		__TZ_WRAP_FUNC(k_sched_lock, nsc_name, k_sched_unlock);                            \
 	}
 
 #endif /* CONFIG_ARM_FIRMWARE_USES_SECURE_ENTRY_FUNCS */
diff --git a/arch/arm64/core/Kconfig b/arch/arm64/core/Kconfig
index 29f2cb6105b..35a480a24fd 100644
--- a/arch/arm64/core/Kconfig
+++ b/arch/arm64/core/Kconfig
@@ -143,17 +143,6 @@ config ARM64_SAFE_EXCEPTION_STACK
 	  used for user stack overflow checking, because kernel stack support
 	  the checking work.
 
-config ARM64_ENABLE_FRAME_POINTER
-	bool
-	depends on OVERRIDE_FRAME_POINTER_DEFAULT && !OMIT_FRAME_POINTER
-	depends on !FRAME_POINTER
-	select DEPRECATED
-	help
-	  Deprecated. Use CONFIG_FRAME_POINTER instead.
-	  Hidden option to simplify access to OVERRIDE_FRAME_POINTER_DEFAULT
-	  and OMIT_FRAME_POINTER. It is automatically enabled when the frame
-	  pointer unwinding is enabled.
-
 config ARM64_EXCEPTION_STACK_TRACE
 	bool
 	default y
diff --git a/arch/arm64/core/cortex_r/Kconfig b/arch/arm64/core/cortex_r/Kconfig
index 41353789515..e7008cce5ef 100644
--- a/arch/arm64/core/cortex_r/Kconfig
+++ b/arch/arm64/core/cortex_r/Kconfig
@@ -7,39 +7,6 @@
 
 if CPU_HAS_MPU
 
-config ARM_MPU
-	bool "ARM MPU Support"
-	select THREAD_STACK_INFO
-	select MPU
-	select SRAM_REGION_PERMISSIONS
-	select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
-	default y
-	help
-	  MPU implements Memory Protection Unit.
-
-	  Notes:
-	  The ARMv8-R MPU architecture requires a power-of-two alignment
-	  of MPU region base address and size(64 bytes aligned).
-
-	  The ARMv8-R MPU requires the active MPU regions be non-overlapping.
-	  As a result of this, the ARMv8-R MPU needs to fully partition the
-	  memory map when programming dynamic memory regions (e.g. PRIV stack
-	  guard, user thread stack, and application memory domains), if the
-	  system requires PRIV access policy different from the access policy
-	  of the ARMv8-R background memory map. The application developer may
-	  enforce full PRIV (kernel) memory partition by enabling the
-	  CONFIG_MPU_GAP_FILLING option.
-	  By not enforcing full partition, MPU may leave part of kernel
-	  SRAM area covered only by the default ARMv8-R memory map. This
-	  is fine for User Mode, since the background ARM map does not
-	  allow nPRIV access at all. However, since the background map
-	  policy allows instruction fetches by privileged code, forcing
-	  this Kconfig option off prevents the system from directly
-	  triggering MemManage exceptions upon accidental attempts to
-	  execute code from SRAM in XIP builds.
-	  Since this does not compromise User Mode, we make the skipping
-	  of full partitioning the default behavior for the ARMv8-R MPU
-	  driver.
 
 config ARM_MPU_REGION_MIN_ALIGN_AND_SIZE
 	int
diff --git a/arch/arm64/core/cortex_r/arm_mpu.c b/arch/arm64/core/cortex_r/arm_mpu.c
index 2bd6d265c9a..3053d90cb75 100644
--- a/arch/arm64/core/cortex_r/arm_mpu.c
+++ b/arch/arm64/core/cortex_r/arm_mpu.c
@@ -196,7 +196,7 @@ static ALWAYS_INLINE void region_init(const uint32_t index,
 				  .limit = (reg).dt_addr + (reg).dt_size,	\
 				  .attr  = _ATTR,				\
 				}
-
+#ifdef CONFIG_MEM_ATTR
 /* This internal function programs the MPU regions defined in the DT when using
  * the `zephyr,memory-attr = <( DT_MEM_ARM(...) )>` property.
  */
@@ -247,7 +247,7 @@ static int mpu_configure_regions_from_dt(uint8_t *reg_index)
 
 	return 0;
 }
-
+#endif /* CONFIG_MEM_ATTR */
 /*
  * @brief MPU default configuration
  *
@@ -303,13 +303,13 @@ FUNC_NO_STACK_PROTECTOR void z_arm64_mm_init(bool is_primary_core)
 
 	/* Update the number of programmed MPU regions. */
 	tmp_static_num = mpu_config.num_regions;
-
+#ifdef CONFIG_MEM_ATTR
 	/* DT-defined MPU regions. */
 	if (mpu_configure_regions_from_dt(&tmp_static_num) == -EINVAL) {
 		__ASSERT(0, "Failed to allocate MPU regions from DT\n");
 		return;
 	}
-
+#endif
 	arm_core_mpu_enable();
 
 	if (!is_primary_core) {
diff --git a/arch/arm64/core/elf.c b/arch/arm64/core/elf.c
index 66e9f21fc06..c60c99fad46 100644
--- a/arch/arm64/core/elf.c
+++ b/arch/arm64/core/elf.c
@@ -6,6 +6,7 @@
 
 #include <zephyr/llext/elf.h>
 #include <zephyr/llext/llext.h>
+#include <zephyr/llext/llext_internal.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/sys/util.h>
 #include <zephyr/sys/byteorder.h>
@@ -430,12 +431,32 @@ static int imm_reloc_handler(elf_rela_t *rel, elf_word reloc_type, uintptr_t loc
  * @retval -ENOTSUP Unsupported relocation
  * @retval -ENOEXEC Invalid relocation
  */
-int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc, uintptr_t sym_base_addr, const char *sym_name,
-		      uintptr_t load_bias)
+int arch_elf_relocate(struct llext_loader *ldr, struct llext *ext, elf_rela_t *rel,
+		      const elf_shdr_t *shdr)
 {
 	int ret = 0;
 	bool overflow_check = true;
 	elf_word reloc_type = ELF_R_TYPE(rel->r_info);
+	const uintptr_t loc = llext_get_reloc_instruction_location(ldr, ext, shdr->sh_info, rel);
+	elf_sym_t sym;
+	uintptr_t sym_base_addr;
+	const char *sym_name;
+
+	ret = llext_read_symbol(ldr, ext, rel, &sym);
+
+	if (ret != 0) {
+		LOG_ERR("Could not read symbol from binary!");
+		return ret;
+	}
+
+	sym_name = llext_symbol_name(ldr, ext, &sym);
+
+	ret = llext_lookup_symbol(ldr, ext, &sym_base_addr, rel, &sym, sym_name, shdr);
+
+	if (ret != 0) {
+		LOG_ERR("Could not find symbol %s!", sym_name);
+		return ret;
+	}
 
 	switch (reloc_type) {
 	case R_ARM_NONE:
diff --git a/arch/arm64/core/fatal.c b/arch/arm64/core/fatal.c
index 7955b6f7d6d..e7480c9de15 100644
--- a/arch/arm64/core/fatal.c
+++ b/arch/arm64/core/fatal.c
@@ -17,9 +17,11 @@
 #include <zephyr/drivers/pm_cpu_ops.h>
 #include <zephyr/arch/common/exc_handle.h>
 #include <zephyr/kernel.h>
+#include <zephyr/linker/linker-defs.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/sys/poweroff.h>
 #include <kernel_arch_func.h>
+#include <kernel_arch_interface.h>
 
 #include "paging.h"
 
@@ -201,6 +203,33 @@ static void esf_dump(const struct arch_esf *esf)
 #ifdef CONFIG_ARCH_STACKWALK
 typedef bool (*arm64_stacktrace_cb)(void *cookie, unsigned long addr, void *fp);
 
+static bool is_address_mapped(uint64_t *addr)
+{
+	uintptr_t *phys = NULL;
+
+	if (*addr == 0U)
+		return false;
+
+	/* Check alignment. */
+	if ((*addr & (sizeof(uint32_t) - 1U)) != 0U)
+		return false;
+
+	return !arch_page_phys_get((void *) addr, phys);
+}
+
+static bool is_valid_jump_address(uint64_t *addr)
+{
+	if (*addr == 0U)
+		return false;
+
+	/* Check alignment. */
+	if ((*addr & (sizeof(uint32_t) - 1U)) != 0U)
+		return false;
+
+	return ((*addr >= (uint64_t)__text_region_start) &&
+		(*addr <= (uint64_t)(__text_region_end)));
+}
+
 static void walk_stackframe(arm64_stacktrace_cb cb, void *cookie, const struct arch_esf *esf,
 			    int max_frames)
 {
@@ -234,7 +263,11 @@ static void walk_stackframe(arm64_stacktrace_cb cb, void *cookie, const struct a
 	}
 
 	for (int i = 0; (fp != NULL) && (i < max_frames); i++) {
+		if (!is_address_mapped(fp))
+			break;
 		lr = fp[1];
+		if (!is_valid_jump_address(&lr))
+			break;
 		if (!cb(cookie, lr, fp)) {
 			break;
 		}
@@ -414,8 +447,6 @@ void z_arm64_fatal_error(unsigned int reason, struct arch_esf *esf)
 #endif /* CONFIG_EXCEPTION_DEBUG */
 
 	z_fatal_error(reason, esf);
-
-	CODE_UNREACHABLE;
 }
 
 /**
diff --git a/arch/arm64/core/reset.S b/arch/arm64/core/reset.S
index a01139ad700..235156f9a1c 100644
--- a/arch/arm64/core/reset.S
+++ b/arch/arm64/core/reset.S
@@ -58,9 +58,10 @@ SECTION_SUBSEC_FUNC(TEXT,_reset_section,__reset_prep_c)
 	b	out
 #endif /* CONFIG_ARMV8_R */
 2:
-	/* Disable alignment fault checking */
+	/* Disable alignment fault checking, disable D-Cache, I-Cache, MMU for safety */
 	mrs	x0, sctlr_el2
-	bic	x0, x0, SCTLR_A_BIT
+	mov	x1, #(SCTLR_A_BIT | SCTLR_C_BIT | SCTLR_M_BIT | SCTLR_I_BIT)
+	bic	x0, x0, x1
 	msr	sctlr_el2, x0
 	isb
 
diff --git a/arch/arm64/core/thread.c b/arch/arm64/core/thread.c
index 18f49945eda..c48672a5f07 100644
--- a/arch/arm64/core/thread.c
+++ b/arch/arm64/core/thread.c
@@ -30,7 +30,7 @@
  *   privileged portion of the user stack without touching SP_EL0. This portion
  *   is marked as not user accessible in the MMU/MPU.
  *
- * - a stack guard region will be added bellow the kernel stack when
+ * - a stack guard region will be added below the kernel stack when
  *   ARM64_STACK_PROTECTION is enabled. In this case, SP_EL0 will always point
  *   to the safe exception stack in the kernel space. For the kernel thread,
  *   SP_EL0 will not change always pointing to safe exception stack. For the
diff --git a/arch/arm64/core/vector_table.S b/arch/arm64/core/vector_table.S
index 632304b7029..1c2f4218ff1 100644
--- a/arch/arm64/core/vector_table.S
+++ b/arch/arm64/core/vector_table.S
@@ -63,7 +63,7 @@ _ASM_FILE_PROLOGUE
 	stp	x12, x13, [sp, ___esf_t_x12_x13_OFFSET]
 	stp	x14, x15, [sp, ___esf_t_x14_x15_OFFSET]
 #ifdef CONFIG_ARM64_SAFE_EXCEPTION_STACK
-	/* The expection from el1 does not need to save x16, x17, x18 and lr */
+	/* The exception from el1 does not need to save x16, x17, x18 and lr */
 	.if	\el == el0
 #endif
 	stp	x16, x17, [sp, ___esf_t_x16_x17_OFFSET]
diff --git a/arch/common/CMakeLists.txt b/arch/common/CMakeLists.txt
index 48685151ab1..6f84bb96351 100644
--- a/arch/common/CMakeLists.txt
+++ b/arch/common/CMakeLists.txt
@@ -27,8 +27,6 @@ zephyr_library_sources_ifdef(
   multilevel_irq.c
   )
 
-zephyr_library_sources_ifdef(CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION multilevel_irq_legacy.c)
-
 zephyr_library_sources_ifdef(CONFIG_SHARED_INTERRUPTS shared_irq.c)
 
 if(NOT CONFIG_ARCH_HAS_TIMING_FUNCTIONS AND
@@ -58,12 +56,21 @@ zephyr_linker_sources_ifdef(CONFIG_GEN_IRQ_VECTOR_TABLE
 )
 
 if(CONFIG_GEN_ISR_TABLES)
-  zephyr_linker_section(NAME .intList VMA IDT_LIST LMA IDT_LIST NOINPUT PASS NOT LINKER_ZEPHYR_FINAL)
-  zephyr_linker_section_configure(SECTION .intList KEEP INPUT ".irq_info" FIRST)
-  zephyr_linker_section_configure(SECTION .intList KEEP INPUT ".intList")
-
-  zephyr_linker_section_configure(SECTION /DISCARD/ KEEP INPUT ".irq_info" PASS LINKER_ZEPHYR_FINAL)
-  zephyr_linker_section_configure(SECTION /DISCARD/ KEEP INPUT ".intList"  PASS LINKER_ZEPHYR_FINAL)
+  # IAR Toolchain is having problems with discarding .intList
+  # This will always keep .intList in a harmless location
+  # until we can implement a proper DISCARD.
+  if(ZEPHYR_TOOLCHAIN_VARIANT STREQUAL "iar")
+    zephyr_linker_section(NAME .intList GROUP RODATA_REGION NOINPUT)
+    zephyr_linker_section_configure(SECTION .intList KEEP INPUT ".irq_info" FIRST)
+    zephyr_linker_section_configure(SECTION .intList KEEP INPUT ".intList")
+  else()
+    zephyr_linker_section(NAME .intList VMA IDT_LIST LMA IDT_LIST NOINPUT PASS NOT LINKER_ZEPHYR_FINAL)
+    zephyr_linker_section_configure(SECTION .intList KEEP INPUT ".irq_info" FIRST)
+    zephyr_linker_section_configure(SECTION .intList KEEP INPUT ".intList")
+
+    zephyr_linker_section_configure(SECTION /DISCARD/ KEEP INPUT ".irq_info" PASS LINKER_ZEPHYR_FINAL)
+    zephyr_linker_section_configure(SECTION /DISCARD/ KEEP INPUT ".intList"  PASS LINKER_ZEPHYR_FINAL)
+  endif()
 endif()
 
 zephyr_linker_sources_ifdef(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT
@@ -76,9 +83,8 @@ zephyr_linker_sources_ifdef(CONFIG_NOCACHE_MEMORY
   nocache.ld
 )
 
-# Only ARM, X86 and OPENISA_RV32M1_RISCV32 use ROM_START_OFFSET.
-if (DEFINED CONFIG_ARM OR DEFINED CONFIG_X86 OR DEFINED CONFIG_ARM64
-    OR DEFINED CONFIG_SOC_OPENISA_RV32M1)
+# Only ARM, X86 and RISCV use ROM_START_OFFSET.
+if (DEFINED CONFIG_ARM OR DEFINED CONFIG_X86 OR DEFINED CONFIG_ARM64 OR DEFINED CONFIG_RISCV)
   # Exclamation mark is printable character with lowest number in ASCII table.
   # We are sure that this file will be included as a first.
   zephyr_linker_sources(ROM_START SORT_KEY ! rom_start_address.ld)
diff --git a/arch/common/Kconfig b/arch/common/Kconfig
index 2dcf2f5791b..1cc91d7c25b 100644
--- a/arch/common/Kconfig
+++ b/arch/common/Kconfig
@@ -16,24 +16,53 @@ config SEMIHOST
 	  This option is compatible with hardware and with QEMU, through the
 	  (automatic) use of the -semihosting-config switch when invoking it.
 
-config LEGACY_MULTI_LEVEL_TABLE_GENERATION
-	bool "Auto generates the multi-level interrupt LUT (deprecated)"
-	default y
-	select DEPRECATED
-	depends on MULTI_LEVEL_INTERRUPTS
-	depends on !PLIC
-	depends on !NXP_IRQSTEER
-	depends on !RV32M1_INTMUX
-	depends on !CAVS_ICTL
-	depends on !DW_ICTL_ACE
-	depends on !DW_ICTL
-	help
-	  A make-shift Kconfig to continue generating the multi-level interrupt LUT
-	  with the legacy way using DT macros.
-
 config ISR_TABLE_SHELL
 	bool "Shell command to dump the ISR tables"
 	depends on GEN_SW_ISR_TABLE
 	depends on SHELL
 	help
 	  This option enables a shell command to dump the ISR tables.
+
+
+config ARM_MPU
+	bool "ARM MPU Support"
+	select MPU
+	select SRAM_REGION_PERMISSIONS
+	select THREAD_STACK_INFO
+	select ARCH_HAS_EXECUTABLE_PAGE_BIT if (CPU_AARCH32_CORTEX_R || CPU_CORTEX_M)
+	select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT if !(CPU_HAS_NXP_SYSMPU || ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R)
+	select MPU_REQUIRES_NON_OVERLAPPING_REGIONS if CPU_HAS_ARM_MPU && (ARMV8_M_BASELINE || ARMV8_M_MAINLINE || AARCH32_ARMV8_R)
+	select MPU_GAP_FILLING if AARCH32_ARMV8_R
+	select ARCH_MEM_DOMAIN_SUPPORTS_ISOLATED_STACKS if (CPU_AARCH32_CORTEX_R || CPU_CORTEX_M)
+	select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE && CPU_AARCH64_CORTEX_R
+	default y if CPU_AARCH64_CORTEX_R
+	depends on CPU_HAS_MPU
+	help
+	  MCU implements Memory Protection Unit.
+
+	  Notes:
+	  The ARMv6-M, ARMv7-M, and ARMv8-R MPU MPU architecture requires a power-of-two
+	  alignment of MPU region base address and size.
+
+	  The NXP MPU as well as the ARMv8-M MPU do not require MPU regions
+	  to have power-of-two alignment for base address and region size.
+
+	  The ARMv8-M and ARMv8-R MPU requires the active MPU regions be non-overlapping.
+	  As a result of this, both respective MPUs needs to fully partition the
+	  memory map when programming dynamic memory regions (e.g. PRIV stack
+	  guard, user thread stack, and application memory domains), if the
+	  system requires PRIV access policy different from the access policy
+	  of the ARMv8-M or ARMv8-R background memory map. The application developer may
+	  enforce full PRIV (kernel) memory partition by enabling the
+	  MPU_GAP_FILLING option.
+	  By not enforcing full partition, MPU may leave part of kernel
+	  SRAM area covered only by the default ARMv8-M or ARMv8-R memory map. This
+	  is fine for User Mode, since the background ARM map does not
+	  allow nPRIV access at all. However, since the background map
+	  policy allows instruction fetches by privileged code, forcing
+	  this Kconfig option off prevents the system from directly
+	  triggering MemManage exceptions upon accidental attempts to
+	  execute code from SRAM in XIP builds.
+	  Since this does not compromise User Mode, we make the skipping
+	  of full partitioning the default behavior for the ARMv8-M and ARMv8-R MPU
+	  driver.
diff --git a/arch/common/multilevel_irq_legacy.c b/arch/common/multilevel_irq_legacy.c
deleted file mode 100644
index dd4fe68b5ac..00000000000
--- a/arch/common/multilevel_irq_legacy.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (c) 2018 Intel Corporation.
- * Copyright (c) 2024 Meta.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/sw_isr_table.h>
-#include <zephyr/sys/util.h>
-
-/**
- * @file
- * @brief This file houses the deprecated legacy macros-generated multi-level interrupt lookup
- * table code, compiled when `CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION` is enabled.
- */
-
-/*
- * Insert code if the node_id is an interrupt controller
- */
-#define Z_IF_DT_IS_INTC(node_id, code)                                                             \
-	IF_ENABLED(DT_NODE_HAS_PROP(node_id, interrupt_controller), (code))
-
-/*
- * Expands to node_id if its IRQN is equal to `_irq`, nothing otherwise
- * This only works for `_irq` between 0 & 4095, see `IS_EQ`
- */
-#define Z_IF_DT_INTC_IRQN_EQ(node_id, _irq) IF_ENABLED(IS_EQ(DT_IRQ(node_id, irq), _irq), (node_id))
-
-/*
- * Expands to node_id if it's an interrupt controller & its IRQN is `irq`, or nothing otherwise
- */
-#define Z_DT_INTC_GET_IRQN(node_id, _irq)                                                          \
-	Z_IF_DT_IS_INTC(node_id, Z_IF_DT_INTC_IRQN_EQ(node_id, _irq))
-
-/**
- * Loop through child of "/soc" and get root interrupt controllers with `_irq` as IRQN,
- * this assumes only one device has the IRQN
- * @param _irq irq number
- * @return node_id(s) that has the `_irq` number, or empty if none of them has the `_irq`
- */
-#define INTC_DT_IRQN_GET(_irq)                                                                     \
-	DT_FOREACH_CHILD_STATUS_OKAY_VARGS(DT_PATH(soc), Z_DT_INTC_GET_IRQN, _irq)
-
-#define INIT_IRQ_PARENT_OFFSET_2ND(n, d, i, o)                                                     \
-	IRQ_PARENT_ENTRY_DEFINE(intc_l2_##n, DEVICE_DT_GET_OR_NULL(d), i, o, 2)
-
-#define IRQ_INDEX_TO_OFFSET(i, base) (base + i * CONFIG_MAX_IRQ_PER_AGGREGATOR)
-
-#define CAT_2ND_LVL_LIST(i, base)                                                                  \
-	INIT_IRQ_PARENT_OFFSET_2ND(i, INTC_DT_IRQN_GET(CONFIG_2ND_LVL_INTR_0##i##_OFFSET),         \
-				   CONFIG_2ND_LVL_INTR_0##i##_OFFSET,                              \
-				   IRQ_INDEX_TO_OFFSET(i, base))
-
-LISTIFY(CONFIG_NUM_2ND_LEVEL_AGGREGATORS, CAT_2ND_LVL_LIST, (;), CONFIG_2ND_LVL_ISR_TBL_OFFSET);
-
-#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
-
-BUILD_ASSERT((CONFIG_NUM_3RD_LEVEL_AGGREGATORS * CONFIG_MAX_IRQ_PER_AGGREGATOR) <=
-		     BIT(CONFIG_3RD_LEVEL_INTERRUPT_BITS),
-	     "L3 bits not enough to cover the number of L3 IRQs");
-
-#define INIT_IRQ_PARENT_OFFSET_3RD(n, d, i, o)                                                     \
-	IRQ_PARENT_ENTRY_DEFINE(intc_l3_##n, DEVICE_DT_GET_OR_NULL(d), i, o, 3)
-
-#define CAT_3RD_LVL_LIST(i, base)                                                                  \
-	INIT_IRQ_PARENT_OFFSET_3RD(i, INTC_DT_IRQN_GET(CONFIG_3RD_LVL_INTR_0##i##_OFFSET),         \
-				   CONFIG_3RD_LVL_INTR_0##i##_OFFSET,                              \
-				   IRQ_INDEX_TO_OFFSET(i, base))
-
-LISTIFY(CONFIG_NUM_3RD_LEVEL_AGGREGATORS, CAT_3RD_LVL_LIST, (;), CONFIG_3RD_LVL_ISR_TBL_OFFSET);
-
-#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
diff --git a/arch/common/nocache.ld b/arch/common/nocache.ld
index a4e500e8b17..749e88c9aed 100644
--- a/arch/common/nocache.ld
+++ b/arch/common/nocache.ld
@@ -8,7 +8,7 @@
 /* Copied from linker.ld */
 
 /* Non-cached region of RAM */
-SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),)
+SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,,)
 {
 #if defined(CONFIG_MMU)
 	MMU_ALIGN;
@@ -27,5 +27,6 @@ SECTION_DATA_PROLOGUE(_NOCACHE_SECTION_NAME,(NOLOAD),)
 	MPU_ALIGN(_nocache_ram_size);
 #endif
 	_nocache_ram_end = .;
-} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
 _nocache_ram_size = _nocache_ram_end - _nocache_ram_start;
+_nocache_load_start = LOADADDR(_NOCACHE_SECTION_NAME);
diff --git a/arch/common/timing.c b/arch/common/timing.c
index 8a4f65caa33..642ba79659f 100644
--- a/arch/common/timing.c
+++ b/arch/common/timing.c
@@ -22,13 +22,21 @@ void arch_timing_stop(void)
 
 timing_t arch_timing_counter_get(void)
 {
+#if CONFIG_TIMER_HAS_64BIT_CYCLE_COUNTER
+	return k_cycle_get_64();
+#else
 	return k_cycle_get_32();
+#endif
 }
 
 uint64_t arch_timing_cycles_get(volatile timing_t *const start,
 				volatile timing_t *const end)
 {
+#if CONFIG_TIMER_HAS_64BIT_CYCLE_COUNTER
 	return (*end - *start);
+#else
+	return ((uint32_t)*end - (uint32_t)*start);
+#endif
 }
 
 
diff --git a/arch/mips/core/fatal.c b/arch/mips/core/fatal.c
index a53e5bb0f5e..aee7a597d4d 100644
--- a/arch/mips/core/fatal.c
+++ b/arch/mips/core/fatal.c
@@ -84,7 +84,7 @@ static char *cause_str(unsigned long cause)
 	}
 }
 
-void _Fault(struct arch_esf *esf)
+void z_mips_fault(struct arch_esf *esf)
 {
 	unsigned long cause;
 
diff --git a/arch/mips/core/isr.S b/arch/mips/core/isr.S
index f2f2f342053..1532d06fe5e 100644
--- a/arch/mips/core/isr.S
+++ b/arch/mips/core/isr.S
@@ -66,7 +66,7 @@
 	addi sp, sp, __struct_arch_esf_SIZEOF	;
 
 /* imports */
-GTEXT(_Fault)
+GTEXT(z_mips_fault)
 
 GTEXT(_k_neg_eagain)
 GTEXT(z_thread_mark_switched_in)
@@ -125,7 +125,7 @@ SECTION_FUNC(exception.other, _mips_interrupt)
 
 unhandled:
 	move a0, sp
-	jal _Fault
+	jal z_mips_fault
 	eret
 
 is_kernel_syscall:
diff --git a/arch/nios2/core/exception.S b/arch/nios2/core/exception.S
index ab2d3463dd4..8dd7e0b9b9b 100644
--- a/arch/nios2/core/exception.S
+++ b/arch/nios2/core/exception.S
@@ -12,7 +12,7 @@
 GTEXT(_exception)
 
 /* import */
-GTEXT(_Fault)
+GTEXT(z_nios2_fault)
 GTEXT(arch_swap)
 #ifdef CONFIG_IRQ_OFFLOAD
 GTEXT(z_irq_do_offload)
@@ -171,12 +171,12 @@ not_interrupt:
 
 _exception_enter_fault:
 	/* If we get here, the exception wasn't in interrupt or an
-	 * invocation of irq_oflload(). Let _Fault() handle it in
+	 * invocation of irq_offload(). Let z_nios2_fault() handle it in
 	 * C domain
 	 */
 
 	mov  r4, sp
-	call _Fault
+	call z_nios2_fault
 	jmpi _exception_exit
 
 no_reschedule:
diff --git a/arch/nios2/core/fatal.c b/arch/nios2/core/fatal.c
index b531bb41e17..3f34c1e8fc7 100644
--- a/arch/nios2/core/fatal.c
+++ b/arch/nios2/core/fatal.c
@@ -102,7 +102,7 @@ static char *cause_str(uint32_t cause_code)
 }
 #endif
 
-FUNC_NORETURN void _Fault(const struct arch_esf *esf)
+FUNC_NORETURN void z_nios2_fault(const struct arch_esf *esf)
 {
 #if defined(CONFIG_PRINTK) || defined(CONFIG_LOG)
 	/* Unfortunately, completely unavailable on Nios II/e cores */
diff --git a/arch/posix/CMakeLists.txt b/arch/posix/CMakeLists.txt
index 8dfc696bc6d..21b6bf7f197 100644
--- a/arch/posix/CMakeLists.txt
+++ b/arch/posix/CMakeLists.txt
@@ -75,6 +75,10 @@ if (CONFIG_NATIVE_APPLICATION)
   zephyr_compile_options(
     -include ${ZEPHYR_BASE}/arch/posix/include/posix_cheats.h
   )
+  # About this -include directive: The reason to do it this way, is because in this
+  # manner it is transparent to the application. Otherwise posix_cheats.h needs to
+  # be included in all the applications' files which define main( ), and in any
+  # app file which uses any of the APIs renamed in that header.
 elseif (CONFIG_NATIVE_LIBRARY)
   zephyr_compile_options(
     -fvisibility=hidden
@@ -146,14 +150,6 @@ if (CONFIG_NATIVE_APPLICATION)
   )
 endif()
 
-# About the -include directive: The reason to do it this way, is because in this
-# manner it is transparent to the application. Otherwise posix_cheats.h needs to
-# be included in all the applications' files which define main( ), and in any
-# app file which uses the pthreads like API provided by Zephyr
-# ( include/posix/pthread.h / kernel/pthread.c ) [And any future API added to
-# Zephyr which will clash with the native POSIX API] . It would also need to
-# be included in a few zephyr kernel files.
-
 #
 # Support for the LLVM Sanitizer toolchain instrumentation frameworks
 # (supported by current gcc's as well)
@@ -199,4 +195,5 @@ if(NOT ${LLVM_SANITIZERS_ARG} STREQUAL "")
   target_compile_options(native_simulator INTERFACE ${LLVM_SANITIZERS_ARG})
 endif()
 
+include(natsim_optional.cmake)
 add_subdirectory(core)
diff --git a/arch/posix/Kconfig b/arch/posix/Kconfig
index 1ed79b38976..f7ed30cf175 100644
--- a/arch/posix/Kconfig
+++ b/arch/posix/Kconfig
@@ -3,7 +3,7 @@
 # Copyright (c) 2017 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-menu "POSIX (native) Options"
+menu "Native (POSIX) Architecture Options"
 	depends on ARCH_POSIX
 
 config ARCH
@@ -27,7 +27,7 @@ config ARCH_POSIX_LIBFUZZER
 	help
 	  Build as an LLVM libfuzzer target. Requires
 	  support from the toolchain (currently only clang works, and
-	  only on native_{posix,sim}[//64]), and should normally be used in
+	  only on native_sim[//64]), and should normally be used in
 	  concert with some of CONFIG_ASAN/UBSAN/MSAN for validation.
 	  The application needs to implement the
 	  LLVMFuzzerTestOneInput() entry point, which runs in the host
@@ -41,4 +41,6 @@ config ARCH_POSIX_TRAP_ON_FATAL
 	  Raise a SIGTRAP signal on fatal error before exiting.
 	  This automatically suspends the target if a debugger is attached.
 
+rsource "Kconfig.natsim_optional"
+
 endmenu
diff --git a/arch/posix/Kconfig.natsim_optional b/arch/posix/Kconfig.natsim_optional
new file mode 100644
index 00000000000..4ec8dcdc4a5
--- /dev/null
+++ b/arch/posix/Kconfig.natsim_optional
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config NATIVE_USE_NSI_ERRNO
+	bool
+	help
+	  Build the native simulator nsi_errno component with the Zephyr embedded code.
+	  This component allows translating errno values from/to the embedded libC to/from the host libC.
diff --git a/arch/posix/include/posix_cheats.h b/arch/posix/include/posix_cheats.h
index d8307df0ef8..fa62dc2a2aa 100644
--- a/arch/posix/include/posix_cheats.h
+++ b/arch/posix/include/posix_cheats.h
@@ -16,8 +16,8 @@
  * If you do see a link error telling you that zap_something is undefined, it is
  * likely that you forgot to select the corresponding Zephyr POSIX API.
  *
- * This header is included automatically when targeting some POSIX ARCH boards
- * (for ex. native_posix).
+ * This header is included automatically when targeting old POSIX ARCH boards
+ * based on the CONFIG_NATIVE_APPLICATION architecture.
  * It will be included in _all_ Zephyr and application source files
  * (it is passed with the option "-include" to the compiler call)
  *
@@ -34,7 +34,7 @@
 
 /*
  * Normally main() is the main entry point of a C executable.
- * When compiling for native_posix, the Zephyr "application" is not the actual
+ * When compiling using CONFIG_NATIVE_APPLICATION, the Zephyr "application" is not the actual
  * entry point of the executable but something the Zephyr OS calls during
  * boot.
  * Therefore we need to rename this application main something else, so
@@ -58,7 +58,7 @@ extern "C" int _posix_zephyr_main(void);
 /*
  * The defines below in this header exist only to enable the Zephyr POSIX API
  * (include/posix/), and applications using it, to be compiled on top of
- * native_posix.
+ * the deprecated CONFIG_NATIVE_APPLICATION targets.
  *
  * Without this header, both the Zephyr POSIX API functions and the equivalent
  * host OS functions would have the same name. This would result in the linker
@@ -72,8 +72,8 @@ extern "C" int _posix_zephyr_main(void);
  * into something which is unlikely to collide with other real functions
  * (Any unlikely string would have done)
  *
- * If you want to link an external library together with Zephyr code for the
- * native_posix target, where that external library calls into the Zephyr
+ * If you want to link an external library together with Zephyr code for a
+ * CONFIG_NATIVE_APPLICATION based target, where that external library calls into the Zephyr
  * POSIX API, you may want to include this header when compiling that library,
  * or rename the calls to match the ones in the defines below.
  */
diff --git a/arch/posix/include/posix_core.h b/arch/posix/include/posix_core.h
index 983f80a3abd..8f72a267389 100644
--- a/arch/posix/include/posix_core.h
+++ b/arch/posix/include/posix_core.h
@@ -31,10 +31,9 @@ typedef struct {
 	 * Note: If more elements are added to this structure, remember to
 	 * update ARCH_POSIX_RECOMMENDED_STACK_SIZE in the configuration.
 	 *
-	 * Currently there are 4 pointers + 2 ints, on a 32-bit native posix
-	 * implementation this will result in 24 bytes ( 4*4 + 2*4).
-	 * For a 64-bit implementation the recommended stack size will be
-	 * 40 bytes ( 4*8 + 2*4 ).
+	 * Currently there are 4 pointers + 2 ints, on a 32-bit build this will result in 24 bytes
+	 * (4*4 + 2*4).
+	 * For a 64-bit build the recommended stack size will be 40 bytes ( 4*8 + 2*4 ).
 	 */
 } posix_thread_status_t;
 
diff --git a/arch/posix/natsim_optional.cmake b/arch/posix/natsim_optional.cmake
new file mode 100644
index 00000000000..e2f3d5f0eb3
--- /dev/null
+++ b/arch/posix/natsim_optional.cmake
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Selection of optional components provided by the native simulator
+
+if(CONFIG_NATIVE_USE_NSI_ERRNO)
+  zephyr_library()
+
+  zephyr_library_sources(${NSI_DIR}/common/src/nsi_errno.c)
+endif()
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 83e3ef86d07..72907a41fee 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -220,9 +220,20 @@ config RISCV_HAS_PLIC
 config RISCV_HAS_CLIC
 	bool
 	depends on RISCV_PRIVILEGED
+	select RISCV_ALWAYS_SWITCH_THROUGH_ECALL if MULTITHREADING
+	select CLIC_SUPPORT_INTERRUPT_LEVEL if !NRFX_CLIC
 	help
 	  Does the SOC provide support for a Core-Local Interrupt Controller (CLIC).
 
+config CLIC_SUPPORT_INTERRUPT_LEVEL
+	bool
+	depends on RISCV_HAS_CLIC
+	help
+	  For CLIC implementations with extended interrupt level, where
+	  higher-numbered interrupt levels can preempt lower-numbered interrupt
+	  levels. This option handles interrupt level in ISR to ensure proper
+	  nested ISR exits.
+
 config RISCV_SOC_EXCEPTION_FROM_IRQ
 	bool
 	help
diff --git a/arch/riscv/Kconfig.isa b/arch/riscv/Kconfig.isa
index 70599843c48..7ac915865d1 100644
--- a/arch/riscv/Kconfig.isa
+++ b/arch/riscv/Kconfig.isa
@@ -33,6 +33,8 @@ config RISCV_ISA_EXT_M
 
 config RISCV_ISA_EXT_A
 	bool
+	imply RISCV_ISA_EXT_ZAAMO
+	imply RISCV_ISA_EXT_ZLRSC
 	help
 	  (A) - Standard Extension for Atomic Instructions
 
@@ -111,6 +113,20 @@ config RISCV_ISA_EXT_ZIFENCEI
 	  provides explicit synchronization between writes to instruction
 	  memory and instruction fetches on the same hart.
 
+config RISCV_ISA_EXT_ZAAMO
+	bool
+	help
+	  (Zaamo) - Atomic memory operation subset of the A extension
+
+	  The Zaamo extension enables support for AMO*.W/D-style instructions.
+
+config RISCV_ISA_EXT_ZLRSC
+	bool
+	help
+	  (Zlrsc) - Load-Reserved/Store-Conditional subset of the A extension
+
+	  The Zlrsc extension enables support for LR.W/D and SC.W/D-style instructions.
+
 config RISCV_ISA_EXT_ZBA
 	bool
 	help
diff --git a/arch/riscv/core/cpu_idle.c b/arch/riscv/core/cpu_idle.c
index 413b911a53e..6991da40905 100644
--- a/arch/riscv/core/cpu_idle.c
+++ b/arch/riscv/core/cpu_idle.c
@@ -12,6 +12,7 @@ void arch_cpu_idle(void)
 {
 	sys_trace_idle();
 	__asm__ volatile("wfi");
+	sys_trace_idle_exit();
 	irq_unlock(MSTATUS_IEN);
 }
 #endif
@@ -21,6 +22,7 @@ void arch_cpu_atomic_idle(unsigned int key)
 {
 	sys_trace_idle();
 	__asm__ volatile("wfi");
+	sys_trace_idle_exit();
 	irq_unlock(key);
 }
 #endif
diff --git a/arch/riscv/core/elf.c b/arch/riscv/core/elf.c
index 4f981083b94..2ae4b50d132 100644
--- a/arch/riscv/core/elf.c
+++ b/arch/riscv/core/elf.c
@@ -8,6 +8,9 @@
  */
 #include <zephyr/llext/elf.h>
 #include <zephyr/llext/llext.h>
+#include <zephyr/llext/llext_internal.h>
+#include <zephyr/llext/loader.h>
+
 #include <zephyr/logging/log.h>
 #include <zephyr/sys/util.h>
 
@@ -43,6 +46,13 @@ LOG_MODULE_REGISTER(elf, CONFIG_LLEXT_LOG_LEVEL);
 static inline int riscv_relocation_fits(long long jump_target, long long max_distance,
 					elf_word reloc_type)
 {
+	/*
+	 * two's complement encoding
+	 * e.g., [-128=0b10000000, 127=0b01111111] encodable with 8 bits
+	 */
+	if (jump_target < 0) {
+		max_distance++;
+	}
 	if (llabs(jump_target) > max_distance) {
 		LOG_ERR("%lld byte relocation is not possible for type %" PRIu64 " (max %lld)!",
 			jump_target, (uint64_t)reloc_type, max_distance);
@@ -52,7 +62,133 @@ static inline int riscv_relocation_fits(long long jump_target, long long max_dis
 	return 0;
 }
 
-static long long last_u_type_jump_target;
+static size_t riscv_last_rel_idx;
+
+/**
+ * @brief On RISC-V, PC-relative relocations (PCREL_LO12_I, PCREL_LO12_S) do not refer to
+ * the actual symbol. Instead, they refer to the location of a different instruction in the
+ * same section, which has a PCREL_HI20 relocation. The relocation offset is then computed based
+ * on the location and symbol from the HI20 relocation. 20 bits from the offset go into the
+ * instruction that has the HI20 relocation, and 12 bits go into the PCREL_LO12 instruction.
+ *
+ * @param[in] ldr llext loader
+ * @param[in] ext current extension
+ * @param[in] pcrel_lo12 the elf relocation structure for the PCREL_LO12I/S relocation.
+ * @param[in] shdr ELF section header for the relocation
+ * @param[in] sym ELF symbol for PCREL_LO12I
+ * @param[out] link_addr_out computed link address
+ *
+ */
+static int llext_riscv_find_sym_pcrel(struct llext_loader *ldr, struct llext *ext,
+				      const elf_rela_t *pcrel_lo12, const elf_shdr_t *shdr,
+				      const elf_sym_t *sym, intptr_t *link_addr_out)
+{
+	int ret;
+	elf_rela_t candidate;
+	uintptr_t candidate_loc;
+	elf_word reloc_type;
+	elf_sym_t candidate_sym;
+	uintptr_t link_addr;
+	const char *symbol_name;
+	int iteration_start = riscv_last_rel_idx;
+	bool is_first = true;
+	const elf_word rel_cnt = shdr->sh_size / shdr->sh_entsize;
+	const uintptr_t sect_base = (uintptr_t)llext_loaded_sect_ptr(ldr, ext, shdr->sh_info);
+	bool found_candidate = false;
+
+	if (iteration_start >= rel_cnt) {
+		/* value left over from a different section */
+		iteration_start = 0;
+	}
+
+	reloc_type = ELF32_R_TYPE(pcrel_lo12->r_info);
+
+	if (reloc_type != R_RISCV_PCREL_LO12_I && reloc_type != R_RISCV_PCREL_LO12_S) {
+		/* this function does not apply - the symbol is already correct */
+		return 0;
+	}
+
+	for (int i = iteration_start; i != iteration_start || is_first; i++) {
+
+		is_first = false;
+
+		/* get each relocation entry */
+		ret = llext_seek(ldr, shdr->sh_offset + i * shdr->sh_entsize);
+		if (ret != 0) {
+			return ret;
+		}
+
+		ret = llext_read(ldr, &candidate, shdr->sh_entsize);
+		if (ret != 0) {
+			return ret;
+		}
+
+		/* FIXME currently, RISC-V relocations all fit in ELF_32_R_TYPE */
+		reloc_type = ELF32_R_TYPE(candidate.r_info);
+
+		candidate_loc = sect_base + candidate.r_offset;
+
+		/*
+		 * RISC-V ELF specification: "value" of the symbol for the PCREL_LO12 relocation
+		 * is actually the offset of the PCREL_HI20 relocation instruction from section
+		 * start
+		 */
+		if (candidate.r_offset == sym->st_value && reloc_type == R_RISCV_PCREL_HI20) {
+			found_candidate = true;
+
+			/*
+			 * start here in next iteration
+			 * it is fairly likely (albeit not guaranteed) that we require PCREL_HI20
+			 * relocations in order
+			 * we can safely write this even if an error occurs after the loop -
+			 * in that case,we can safely abort the execution anyway
+			 */
+			riscv_last_rel_idx = i;
+
+			break;
+		}
+
+		if (i + 1 >= rel_cnt) {
+			/* wrap around and search in previously processed indices as well */
+			i = -1;
+		}
+	}
+
+	if (!found_candidate) {
+		LOG_ERR("Could not find R_RISCV_PCREL_HI20 relocation for "
+			"R_RISCV_PCREL_LO12 relocation!");
+		return -ENOEXEC;
+	}
+
+	/* we found a match - need to compute the relocation for this instruction */
+	/* lower 12 bits go to the PCREL_LO12 relocation */
+
+	/* get corresponding / "actual" symbol */
+	ret = llext_seek(ldr, ldr->sects[LLEXT_MEM_SYMTAB].sh_offset +
+			 ELF_R_SYM(candidate.r_info) * sizeof(elf_sym_t));
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = llext_read(ldr, &candidate_sym, sizeof(elf_sym_t));
+	if (ret != 0) {
+		return ret;
+	}
+
+	symbol_name = llext_symbol_name(ldr, ext, &candidate_sym);
+
+	ret = llext_lookup_symbol(ldr, ext, &link_addr, &candidate, &candidate_sym,
+				  symbol_name, shdr);
+
+	if (ret != 0) {
+		return ret;
+	}
+
+	*link_addr_out = (intptr_t)(link_addr + candidate.r_addend - candidate_loc); /* S + A - P */
+
+	/* found the matching entry */
+	return 0;
+}
 
 /**
  * @brief RISC-V specific function for relocating partially linked ELF binaries
@@ -61,11 +197,32 @@ static long long last_u_type_jump_target;
  * https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc
  *
  */
-int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc_unsigned, uintptr_t sym_base_addr_unsigned,
-		      const char *sym_name, uintptr_t load_bias)
+int arch_elf_relocate(struct llext_loader *ldr, struct llext *ext, elf_rela_t *rel,
+		      const elf_shdr_t *shdr)
 {
 	/* FIXME currently, RISC-V relocations all fit in ELF_32_R_TYPE */
 	elf_word reloc_type = ELF32_R_TYPE(rel->r_info);
+	const uintptr_t load_bias = (uintptr_t)ext->mem[LLEXT_MEM_TEXT];
+	const uintptr_t loc_unsigned = llext_get_reloc_instruction_location(ldr, ext,
+									    shdr->sh_info, rel);
+	elf_sym_t sym;
+	uintptr_t sym_base_addr_unsigned;
+	const char *sym_name;
+	int ret;
+
+	ret = llext_read_symbol(ldr, ext, rel, &sym);
+	if (ret != 0) {
+		LOG_ERR("Could not read symbol from binary!");
+		return ret;
+	}
+
+	sym_name = llext_symbol_name(ldr, ext, &sym);
+	ret = llext_lookup_symbol(ldr, ext, &sym_base_addr_unsigned, rel, &sym, sym_name, shdr);
+
+	if (ret != 0) {
+		LOG_ERR("Could not find symbol %s!", sym_name);
+		return ret;
+	}
 	/*
 	 * The RISC-V specification uses the following symbolic names for the relocations:
 	 *
@@ -92,7 +249,22 @@ int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc_unsigned, uintptr_t sym_bas
 	long long original_imm8, jump_target;
 	int16_t compressed_imm8;
 	__typeof__(rel->r_addend) target_alignment = 1;
-	const intptr_t sym_base_addr = (intptr_t)sym_base_addr_unsigned;
+	intptr_t sym_base_addr = (intptr_t)sym_base_addr_unsigned;
+
+	/*
+	 * For HI20/LO12 ("PCREL") relocation pairs, we need a helper function to
+	 * determine the address for the LO12 relocation, as it depends on the
+	 * value in the HI20 relocation.
+	 */
+	ret = llext_riscv_find_sym_pcrel(ldr, ext, rel, shdr, &sym, &sym_base_addr);
+
+	if (ret != 0) {
+		LOG_ERR("Failed to resolve RISC-V PCREL relocation for symbol %s at %p "
+			"with base address %p load address %p type %" PRIu64,
+			sym_name, (void *)loc, (void *)sym_base_addr, (void *)load_bias,
+			(uint64_t)reloc_type);
+		return ret;
+	}
 
 	LOG_DBG("Relocating symbol %s at %p with base address %p load address %p type %" PRIu64,
 		sym_name, (void *)loc, (void *)sym_base_addr, (void *)load_bias,
@@ -169,43 +341,32 @@ int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc_unsigned, uintptr_t sym_bas
 			UNALIGNED_PUT(modified_operand, loc32);
 		}
 
-		last_u_type_jump_target = jump_target;
-
 		return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE,
 					     reloc_type);
 	case R_RISCV_PCREL_LO12_I:
-		/* need the same jump target as preceding U-type relocation */
-		if (last_u_type_jump_target == 0) {
-			LOG_ERR("R_RISCV_PCREL_LO12_I relocation without preceding U-type "
-				"relocation!");
-			return -ENOEXEC;
-		}
+		/*
+		 * Jump target is resolved in llext_riscv_find_sym_pcrel in llext_link.c
+		 * as it depends on other relocations.
+		 */
 		modified_operand = UNALIGNED_GET(loc32);
-		jump_target = last_u_type_jump_target; /* S - P */
-		last_u_type_jump_target = 0;
-		imm8 = jump_target;
+		imm8 = (int32_t)sym_base_addr; /* already computed */
 		modified_operand = R_RISCV_CLEAR_ITYPE_IMM8(modified_operand);
 		modified_operand = R_RISCV_SET_ITYPE_IMM8(modified_operand, imm8);
 		UNALIGNED_PUT(modified_operand, loc32);
-		return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE,
-					     reloc_type);
+		/* we have checked that this fits with the associated relocation */
 		break;
 	case R_RISCV_PCREL_LO12_S:
-		/* need the same jump target as preceding U-type relocation */
-		if (last_u_type_jump_target == 0) {
-			LOG_ERR("R_RISCV_PCREL_LO12_I relocation without preceding U-type "
-				"relocation!");
-			return -ENOEXEC;
-		}
+		/*
+		 * Jump target is resolved in llext_riscv_find_sym_pcrel in llext_link.c
+		 * as it depends on other relocations.
+		 */
 		modified_operand = UNALIGNED_GET(loc32);
-		jump_target = last_u_type_jump_target; /* S - P */
-		last_u_type_jump_target = 0;
-		imm8 = jump_target;
+		imm8 = (int32_t)sym_base_addr; /* already computed */
 		modified_operand = R_RISCV_CLEAR_STYPE_IMM8(modified_operand);
 		modified_operand = R_RISCV_SET_STYPE_IMM8(modified_operand, imm8);
 		UNALIGNED_PUT(modified_operand, loc32);
-		return riscv_relocation_fits(jump_target, RISCV_MAX_JUMP_DISTANCE_U_PLUS_I_TYPE,
-					     reloc_type);
+		/* we have checked that this fits with the associated relocation */
+		break;
 	case R_RISCV_HI20:
 		jump_target = sym_base_addr + rel->r_addend; /* S + A */
 		modified_operand = UNALIGNED_GET(loc32);
diff --git a/arch/riscv/core/fatal.c b/arch/riscv/core/fatal.c
index 879ffab9a80..3bf4e57d874 100644
--- a/arch/riscv/core/fatal.c
+++ b/arch/riscv/core/fatal.c
@@ -203,7 +203,7 @@ static bool bad_stack_pointer(struct arch_esf *esf)
 	return false;
 }
 
-void _Fault(struct arch_esf *esf)
+void z_riscv_fault(struct arch_esf *esf)
 {
 #ifdef CONFIG_USERSPACE
 	/*
diff --git a/arch/riscv/core/isr.S b/arch/riscv/core/isr.S
index 11787d3b324..dad96974dcc 100644
--- a/arch/riscv/core/isr.S
+++ b/arch/riscv/core/isr.S
@@ -72,7 +72,7 @@ GDATA(_sw_isr_table)
 GTEXT(__soc_is_irq)
 #endif
 GTEXT(__soc_handle_irq)
-GTEXT(_Fault)
+GTEXT(z_riscv_fault)
 #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
 GTEXT(__soc_save_context)
 GTEXT(__soc_restore_context)
@@ -198,6 +198,12 @@ SECTION_FUNC(exception.entry, _isr_wrapper)
 	sr s0, __struct_arch_esf_s0_OFFSET(sp)
 	get_current_cpu s0
 
+#ifdef CONFIG_CLIC_SUPPORT_INTERRUPT_LEVEL
+	/* Save mcause register */
+	csrr t0, mcause
+	sr t0, __struct_arch_esf_mcause_OFFSET(sp)
+#endif /* CONFIG_CLIC_SUPPORT_INTERRUPT_LEVEL */
+
 	/* Save MEPC register */
 	csrr t0, mepc
 	sr t0, __struct_arch_esf_mepc_OFFSET(sp)
@@ -336,7 +342,7 @@ no_fp:	/* increment _current->arch.exception_depth */
 
 	/*
 	 * If the exception is the result of an ECALL, check whether to
-	 * perform a context-switch or an IRQ offload. Otherwise call _Fault
+	 * perform a context-switch or an IRQ offload. Otherwise call z_riscv_fault
 	 * to report the exception.
 	 */
 	csrr t0, mcause
@@ -375,15 +381,15 @@ no_fp:	/* increment _current->arch.exception_depth */
 #endif /* CONFIG_USERSPACE */
 
 	/*
-	 * Call _Fault to handle exception.
+	 * Call z_riscv_fault to handle exception.
 	 * Stack pointer is pointing to a struct_arch_esf structure, pass it
-	 * to _Fault (via register a0).
-	 * If _Fault shall return, set return address to
+	 * to z_riscv_fault (via register a0).
+	 * If z_riscv_fault shall return, set return address to
 	 * no_reschedule to restore stack.
 	 */
 	mv a0, sp
 	la ra, no_reschedule
-	tail _Fault
+	tail z_riscv_fault
 
 is_kernel_syscall:
 	/*
@@ -737,6 +743,13 @@ fp_trap_exit:
 	/* Restore MEPC and MSTATUS registers */
 	lr t0, __struct_arch_esf_mepc_OFFSET(sp)
 	lr t2, __struct_arch_esf_mstatus_OFFSET(sp)
+
+#ifdef CONFIG_CLIC_SUPPORT_INTERRUPT_LEVEL
+	/* Restore MCAUSE register for previous interrupt level. */
+	lr t1, __struct_arch_esf_mcause_OFFSET(sp)
+	csrw mcause, t1
+#endif /* CONFIG_CLIC_SUPPORT_INTERRUPT_LEVEL */
+
 	csrw mepc, t0
 	csrw mstatus, t2
 
diff --git a/arch/riscv/core/offsets/offsets.c b/arch/riscv/core/offsets/offsets.c
index 99eba096824..c526ffbaed0 100644
--- a/arch/riscv/core/offsets/offsets.c
+++ b/arch/riscv/core/offsets/offsets.c
@@ -112,6 +112,10 @@ GEN_OFFSET_STRUCT(arch_esf, a7);
 GEN_OFFSET_STRUCT(arch_esf, mepc);
 GEN_OFFSET_STRUCT(arch_esf, mstatus);
 
+#ifdef CONFIG_CLIC_SUPPORT_INTERRUPT_LEVEL
+GEN_OFFSET_STRUCT(arch_esf, mcause);
+#endif /* CONFIG_CLIC_SUPPORT_INTERRUPT_LEVEL */
+
 GEN_OFFSET_STRUCT(arch_esf, s0);
 
 #ifdef CONFIG_USERSPACE
diff --git a/arch/riscv/core/stacktrace.c b/arch/riscv/core/stacktrace.c
index 361e152f00c..74f94d4eb86 100644
--- a/arch/riscv/core/stacktrace.c
+++ b/arch/riscv/core/stacktrace.c
@@ -7,6 +7,7 @@
 #include <zephyr/debug/symtab.h>
 #include <zephyr/kernel.h>
 #include <zephyr/kernel_structs.h>
+#include <zephyr/linker/linker-defs.h>
 #include <kernel_internal.h>
 #include <zephyr/logging/log.h>
 
@@ -90,9 +91,7 @@ static bool in_stack_bound(uintptr_t addr, const struct k_thread *const thread,
 
 static inline bool in_text_region(uintptr_t addr)
 {
-	extern uintptr_t __text_region_start, __text_region_end;
-
-	return (addr >= (uintptr_t)&__text_region_start) && (addr < (uintptr_t)&__text_region_end);
+	return (addr >= (uintptr_t)__text_region_start) && (addr < (uintptr_t)__text_region_end);
 }
 
 #ifdef CONFIG_FRAME_POINTER
diff --git a/arch/riscv/core/thread.c b/arch/riscv/core/thread.c
index 896f8e5199d..ab2cbfe0036 100644
--- a/arch/riscv/core/thread.c
+++ b/arch/riscv/core/thread.c
@@ -110,6 +110,11 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
 	SOC_ISR_STACKING_ESR_INIT;
 #endif
 
+#ifdef CONFIG_CLIC_SUPPORT_INTERRUPT_LEVEL
+	/* Clear the previous interrupt level. */
+	stack_init->mcause = 0;
+#endif
+
 	thread->callee_saved.sp = (unsigned long)stack_init;
 
 	/* where to go when returning from z_riscv_switch() */
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 46f32f92728..a9a883a3104 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -43,7 +43,16 @@ config CPU_APOLLO_LAKE
 	help
 	  This option signifies the use of a CPU from the Apollo Lake family.
 
-config CPU_LAKEMONT
+config CPU_LAKEMONT_VALUE
+	bool
+	select CPU_HAS_FPU
+	select ARCH_HAS_STACK_PROTECTION if X86_MMU
+	select ARCH_HAS_USERSPACE if X86_MMU
+	select CPU_HAS_DCACHE
+	help
+	  This option signifies the use of a CPU from the Lakemont Value family.
+
+config CPU_LAKEMONT_PERF
 	bool
 	select CPU_HAS_FPU
 	select ARCH_HAS_STACK_PROTECTION if X86_MMU
@@ -55,7 +64,7 @@ config CPU_LAKEMONT
 	select X86_CPU_HAS_SSSE3
 	select CPU_HAS_DCACHE
 	help
-	  This option signifies the use of a CPU from the Lakemont family.
+	  This option signifies the use of a CPU from the Lakemont Performance family.
 
 #
 # Configuration common to both IA32 and Intel64 sub-architectures.
@@ -74,6 +83,7 @@ config X86_64
 	select X86_MMX
 	select X86_SSE
 	select X86_SSE2
+	select ARCH_HAS_DIRECTED_IPIS if !X2APIC
 
 menu "x86 Features"
 
diff --git a/arch/x86/core/CMakeLists.txt b/arch/x86/core/CMakeLists.txt
index e8055c6fae2..abbc052a624 100644
--- a/arch/x86/core/CMakeLists.txt
+++ b/arch/x86/core/CMakeLists.txt
@@ -21,6 +21,8 @@ zephyr_library_sources_ifdef(CONFIG_X86_MMU x86_mmu.c)
 zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.c)
 zephyr_library_sources_ifdef(CONFIG_ARCH_CACHE cache.c)
 
+zephyr_library_sources_ifdef(CONFIG_DYNAMIC_BOOTARGS bootargs.c)
+
 zephyr_library_sources_ifdef(CONFIG_X86_VERY_EARLY_CONSOLE early_serial.c)
 
 zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c)
diff --git a/arch/x86/core/bootargs.c b/arch/x86/core/bootargs.c
new file mode 100644
index 00000000000..5ae4c2b0f95
--- /dev/null
+++ b/arch/x86/core/bootargs.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2025 Cadence Design Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+
+#if defined(CONFIG_MULTIBOOT_INFO)
+
+__pinned_noinit char multiboot_cmdline[CONFIG_BOOTARGS_ARGS_BUFFER_SIZE];
+
+const char *get_bootargs(void)
+{
+	return multiboot_cmdline;
+}
+
+#elif defined(CONFIG_X86_EFI)
+
+__pinned_noinit char efi_bootargs[CONFIG_BOOTARGS_ARGS_BUFFER_SIZE];
+
+const char *get_bootargs(void)
+{
+	return efi_bootargs;
+}
+
+#endif
diff --git a/arch/x86/core/efi.c b/arch/x86/core/efi.c
index 64faeb9efa5..e5470e6d8a3 100644
--- a/arch/x86/core/efi.c
+++ b/arch/x86/core/efi.c
@@ -18,10 +18,6 @@ static uint64_t __aligned(64) efi_stack[1024];
 
 struct efi_boot_arg *efi;
 
-#ifdef CONFIG_DYNAMIC_BOOTARGS
-__pinned_noinit char efi_bootargs[CONFIG_BOOTARGS_ARGS_BUFFER_SIZE];
-#endif
-
 void *efi_get_acpi_rsdp(void)
 {
 	if (efi == NULL) {
@@ -173,10 +169,3 @@ int arch_printk_char_out(int c)
 	return efi_console_putchar(c);
 }
 #endif
-
-#ifdef CONFIG_DYNAMIC_BOOTARGS
-const char *get_bootargs(void)
-{
-	return efi_bootargs;
-}
-#endif /* CONFIG_DYNAMIC_BOOTARGS */
diff --git a/arch/x86/core/fatal.c b/arch/x86/core/fatal.c
index d43499a08d2..6511f531e3d 100644
--- a/arch/x86/core/fatal.c
+++ b/arch/x86/core/fatal.c
@@ -458,6 +458,7 @@ void z_x86_page_fault_handler(struct arch_esf *esf)
 		 * the page is present in the kernel's page tables and the
 		 * instruction will just be re-tried, producing another fault.
 		 */
+		was_valid_access = true;
 		if (was_user &&
 		    !z_x86_kpti_is_access_ok(virt, get_ptables(esf))) {
 			was_valid_access = false;
diff --git a/arch/x86/core/ia32/float.c b/arch/x86/core/ia32/float.c
index c89bf7accd5..9b6f4daa18e 100644
--- a/arch/x86/core/ia32/float.c
+++ b/arch/x86/core/ia32/float.c
@@ -194,7 +194,7 @@ void z_float_enable(struct k_thread *thread, unsigned int options)
 	 * must be preserved).
 	 */
 
-	fp_owner = _kernel.current_fp;
+	fp_owner = _kernel.cpus[0].arch.fpu_owner;
 	if (fp_owner != NULL) {
 		if ((fp_owner->arch.flags & X86_THREAD_FLAG_ALL) != 0) {
 			FpCtxSave(fp_owner);
@@ -215,7 +215,7 @@ void z_float_enable(struct k_thread *thread, unsigned int options)
 		 * (The FP context is "live" in hardware, not saved in TCS.)
 		 */
 
-		_kernel.current_fp = thread;
+		_kernel.cpus[0].arch.fpu_owner = thread;
 	} else {
 		/*
 		 * When enabling FP support for someone else, assign ownership
@@ -230,7 +230,7 @@ void z_float_enable(struct k_thread *thread, unsigned int options)
 			 * to its original state.
 			 */
 
-			_kernel.current_fp = thread;
+			_kernel.cpus[0].arch.fpu_owner = thread;
 			z_FpAccessDisable();
 		} else {
 			/*
@@ -280,10 +280,10 @@ int z_float_disable(struct k_thread *thread)
 
 	if (thread == _current) {
 		z_FpAccessDisable();
-		_kernel.current_fp = (struct k_thread *)0;
+		_kernel.cpus[0].arch.fpu_owner = (struct k_thread *)0;
 	} else {
-		if (_kernel.current_fp == thread) {
-			_kernel.current_fp = (struct k_thread *)0;
+		if (_kernel.cpus[0].arch.fpu_owner == thread) {
+			_kernel.cpus[0].arch.fpu_owner = (struct k_thread *)0;
 		}
 	}
 
diff --git a/arch/x86/core/ia32/swap.S b/arch/x86/core/ia32/swap.S
index af104fdff47..6103e4bbe53 100644
--- a/arch/x86/core/ia32/swap.S
+++ b/arch/x86/core/ia32/swap.S
@@ -50,7 +50,7 @@
  * Floating point registers are handled using a lazy save/restore mechanism
  * since it's expected relatively few threads will be created with the
  * K_FP_REGS or K_SSE_REGS option bits.  The kernel data structure maintains a
- * 'current_fp' field to keep track of the thread that "owns" the floating
+ * 'fpu_owner' field to keep track of the thread that "owns" the floating
  * point registers.  Floating point registers consist of ST0->ST7 (x87 FPU and
  * MMX registers) and XMM0 -> XMM7.
  *
@@ -176,7 +176,7 @@ SECTION_FUNC(PINNED_TEXT, arch_swap)
 	 * If so, there there is no need to restore the floating point context.
 	 */
 
-	movl	_kernel_offset_to_current_fp(%edi), %ebx
+	movl	_kernel_offset_to_fpu_owner(%edi), %ebx
 	cmpl	%ebx, %eax
 	je	restoreContext_NoFloatSwap
 
@@ -265,7 +265,7 @@ restoreContext_NoFloatRestore:
 
 	/* record that the incoming thread "owns" the floating point registers */
 
-	movl	%eax, _kernel_offset_to_current_fp(%edi)
+	movl	%eax, _kernel_offset_to_fpu_owner(%edi)
 
 
 	/*
diff --git a/arch/x86/core/intel64/smp.c b/arch/x86/core/intel64/smp.c
index 1e0aeb3e443..90bd9724667 100644
--- a/arch/x86/core/intel64/smp.c
+++ b/arch/x86/core/intel64/smp.c
@@ -38,3 +38,16 @@ void arch_sched_broadcast_ipi(void)
 {
 	z_loapic_ipi(0, LOAPIC_ICR_IPI_OTHERS, CONFIG_SCHED_IPI_VECTOR);
 }
+
+void arch_sched_directed_ipi(uint32_t cpu_bitmap)
+{
+	unsigned int num_cpus = arch_num_cpus();
+
+	for (unsigned int i = 0; i < num_cpus; i++) {
+		if ((cpu_bitmap & BIT(i)) == 0) {
+			continue;
+		}
+
+		z_loapic_ipi(i, LOAPIC_ICR_IPI_SPECIFIC, CONFIG_SCHED_IPI_VECTOR);
+	}
+}
diff --git a/arch/x86/core/multiboot.c b/arch/x86/core/multiboot.c
index b6112b75f82..06d03c7b807 100644
--- a/arch/x86/core/multiboot.c
+++ b/arch/x86/core/multiboot.c
@@ -11,15 +11,6 @@
 
 struct multiboot_info multiboot_info;
 
-#ifdef CONFIG_DYNAMIC_BOOTARGS
-__pinned_noinit char multiboot_cmdline[CONFIG_BOOTARGS_ARGS_BUFFER_SIZE];
-
-const char *get_bootargs(void)
-{
-	return multiboot_cmdline;
-}
-#endif /* CONFIG_DYNAMIC_BOOTARGS */
-
 /*
  * called very early in the boot process to fetch data out of the multiboot
  * info struct. we need to grab the relevant data before any dynamic memory
diff --git a/arch/x86/core/offsets/ia32_offsets.c b/arch/x86/core/offsets/ia32_offsets.c
index 2dfbb5c38ef..dcbf3d7d680 100644
--- a/arch/x86/core/offsets/ia32_offsets.c
+++ b/arch/x86/core/offsets/ia32_offsets.c
@@ -33,6 +33,12 @@
 GEN_OFFSET_SYM(_thread_arch_t, excNestCount);
 #endif
 
+#if defined(CONFIG_FPU_SHARING)
+GEN_OFFSET_SYM(_kernel_t, cpus);
+GEN_OFFSET_SYM(_cpu_t, arch);
+GEN_OFFSET_SYM(_cpu_arch_t, fpu_owner);
+#endif
+
 #ifdef CONFIG_USERSPACE
 GEN_OFFSET_SYM(_thread_arch_t, psp);
 #ifndef CONFIG_X86_COMMON_PAGE_TABLE
diff --git a/arch/x86/core/reboot_rst_cnt.c b/arch/x86/core/reboot_rst_cnt.c
index e20b5b7ae33..3eafcf9709c 100644
--- a/arch/x86/core/reboot_rst_cnt.c
+++ b/arch/x86/core/reboot_rst_cnt.c
@@ -27,12 +27,22 @@ static inline void cold_reboot(void)
 	sys_out8(reset_value, X86_RST_CNT_REG);
 }
 
+static inline void warm_reboot(void)
+{
+	uint8_t reset_value = X86_RST_CNT_CPU_RST | X86_RST_CNT_SYS_RST;
+
+	sys_out8(reset_value, X86_RST_CNT_REG);
+}
+
 void __weak sys_arch_reboot(int type)
 {
 	switch (type) {
 	case SYS_REBOOT_COLD:
 		cold_reboot();
 		break;
+	case SYS_REBOOT_WARM:
+		warm_reboot();
+		break;
 	default:
 		/* do nothing */
 		break;
diff --git a/arch/x86/ia32.cmake b/arch/x86/ia32.cmake
index 5bf5018a32a..90546924af1 100644
--- a/arch/x86/ia32.cmake
+++ b/arch/x86/ia32.cmake
@@ -3,7 +3,10 @@
 
 # Find out if we are optimizing for size
 get_target_property(zephyr_COMPILE_OPTIONS zephyr_interface INTERFACE_COMPILE_OPTIONS)
-if ("-Os" IN_LIST zephyr_COMPILE_OPTIONS)
+#Any -Os is (or may be) wraped in $<COMPILE_LANGUAGE> guards
+list(FILTER zephyr_COMPILE_OPTIONS INCLUDE REGEX "-Os")
+list(LENGTH zephyr_COMPILE_OPTIONS have_os)
+if (${have_os} GREATER 0)
   zephyr_cc_option(-mpreferred-stack-boundary=2)
 else()
   zephyr_compile_definitions(PERF_OPT)
diff --git a/arch/x86/include/ia32/offsets_short_arch.h b/arch/x86/include/ia32/offsets_short_arch.h
index cb5cdb218f0..b818cf60b55 100644
--- a/arch/x86/include/ia32/offsets_short_arch.h
+++ b/arch/x86/include/ia32/offsets_short_arch.h
@@ -14,6 +14,9 @@
 #define _kernel_offset_to_isf \
 	(___kernel_t_arch_OFFSET + ___kernel_arch_t_isf_OFFSET)
 
+#define _kernel_offset_to_fpu_owner \
+	(___kernel_t_cpus_OFFSET + ___cpu_t_arch_OFFSET + ___cpu_arch_t_fpu_owner_OFFSET)
+
 /* end - kernel */
 
 /* threads */
diff --git a/arch/x86/include/x86_mmu.h b/arch/x86/include/x86_mmu.h
index ed6bb59b37c..1a733485e37 100644
--- a/arch/x86/include/x86_mmu.h
+++ b/arch/x86/include/x86_mmu.h
@@ -139,7 +139,7 @@ extern uint8_t z_shared_kernel_page_start;
 /* Called from page fault handler. ptables here is the ptage tables for the
  * faulting user thread and not the current set of page tables
  */
-extern bool z_x86_kpti_is_access_ok(void *virt, pentry_t *ptables)
+extern bool z_x86_kpti_is_access_ok(void *virt, pentry_t *ptables);
 #endif /* CONFIG_DEMAND_PAGING */
 #endif /* CONFIG_X86_KPTI */
 #endif /* CONFIG_USERSPACE */
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index b69d8bcf02b..19ce69b011b 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -169,7 +169,6 @@ config XTENSA_MMU
 	bool "Xtensa MMU Support"
 	select MMU
 	select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
-	select XTENSA_SMALL_VECTOR_TABLE_ENTRY
 	select KERNEL_VM_USE_CUSTOM_MEM_RANGE_CHECK if XTENSA_RPO_CACHE
 	select CURRENT_THREAD_USE_NO_TLS if USERSPACE
 	help
@@ -223,12 +222,6 @@ config XTENSA_MMU_DOUBLE_MAP
 	  This option specifies that the memory is mapped in two
 	  distinct region, cached and uncached.
 
-	config XTENSA_INVALIDATE_MEM_DOMAIN_TLB_ON_SWAP
-		bool
-		help
-		  This invalidates all TLBs referred by the incoming thread's
-		  memory domain when swapping page tables.
-
 config PRIVILEGED_STACK_SIZE
 	# Must be multiple of CONFIG_MMU_PAGE_SIZE
 	default 4096
diff --git a/arch/xtensa/core/CMakeLists.txt b/arch/xtensa/core/CMakeLists.txt
index 7d7e260ca0b..f3a4419f32c 100644
--- a/arch/xtensa/core/CMakeLists.txt
+++ b/arch/xtensa/core/CMakeLists.txt
@@ -73,13 +73,19 @@ else()
   set(MAY_NEED_SYSCALL_SCRATCH_REG false)
 endif()
 
+if(CONFIG_KERNEL_COHERENCE AND NOT CONFIG_SCHED_CPU_MASK_PIN_ONLY)
+  set(NEED_FLUSH_SCRATCH_REG true)
+else()
+  set(NEED_FLUSH_SCRATCH_REG false)
+endif()
+
 # Generates a list of device-specific scratch register choices
 set(ZSR_H ${CMAKE_BINARY_DIR}/zephyr/include/generated/zephyr/zsr.h)
 add_custom_command(OUTPUT ${ZSR_H} DEPENDS ${CORE_ISA_DM}
   COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gen_zsr.py
                                $<$<BOOL:${CONFIG_XTENSA_MMU}>:--mmu>
                                $<$<BOOL:${MAY_NEED_SYSCALL_SCRATCH_REG}>:--syscall-scratch>
-                               $<$<BOOL:${CONFIG_KERNEL_COHERENCE}>:--coherence>
+                               $<$<BOOL:${NEED_FLUSH_SCRATCH_REG}>:--flush-reg>
                                ${CORE_ISA_DM} ${ZSR_H})
 add_custom_target(zsr_h DEPENDS ${ZSR_H})
 add_dependencies(zephyr_interface zsr_h)
diff --git a/arch/xtensa/core/elf.c b/arch/xtensa/core/elf.c
index 17337f4a7bc..6b83a9c0c61 100644
--- a/arch/xtensa/core/elf.c
+++ b/arch/xtensa/core/elf.c
@@ -34,13 +34,18 @@ LOG_MODULE_DECLARE(llext, CONFIG_LLEXT_LOG_LEVEL);
 
 static void xtensa_elf_relocate(struct llext_loader *ldr, struct llext *ext,
 				const elf_rela_t *rel, uintptr_t addr,
-				uint8_t *loc, int type, uint32_t stb)
+				uint8_t *loc, int type, uint32_t stb,
+				const struct llext_load_param *ldr_parm)
 {
 	elf_word *got_entry = (elf_word *)loc;
 
 	switch (type) {
 	case R_XTENSA_RELATIVE:
-		;
+		if (ldr_parm->pre_located) {
+			/* Relative relocations are already correct in the pre-located case */
+			break;
+		}
+
 		/* Relocate a local symbol: Xtensa specific. Seems to only be used with PIC */
 		unsigned int sh_ndx;
 
@@ -146,7 +151,8 @@ void arch_elf_relocate_local(struct llext_loader *ldr, struct llext *ext, const
 		sh_addr = ldr->sects[LLEXT_MEM_TEXT].sh_addr;
 	}
 
-	xtensa_elf_relocate(ldr, ext, rel, sh_addr, rel_addr, type, ELF_ST_BIND(sym->st_info));
+	xtensa_elf_relocate(ldr, ext, rel, sh_addr, rel_addr, type, ELF_ST_BIND(sym->st_info),
+			    ldr_parm);
 }
 
 /**
@@ -163,5 +169,5 @@ void arch_elf_relocate_global(struct llext_loader *ldr, struct llext *ext, const
 	}
 
 	xtensa_elf_relocate(ldr, ext, rel, (uintptr_t)link_addr, rel_addr, type,
-			    ELF_ST_BIND(sym->st_info));
+			    ELF_ST_BIND(sym->st_info), NULL);
 }
diff --git a/arch/xtensa/core/gen_zsr.py b/arch/xtensa/core/gen_zsr.py
index 6d9a228303f..8cb8a713019 100755
--- a/arch/xtensa/core/gen_zsr.py
+++ b/arch/xtensa/core/gen_zsr.py
@@ -14,8 +14,8 @@
 def parse_args():
     parser = argparse.ArgumentParser(allow_abbrev=False)
 
-    parser.add_argument("--coherence", action="store_true",
-                        help="Enable scratch registers for CONFIG_KERNEL_COHERENCE")
+    parser.add_argument("--flush-reg", action="store_true",
+                        help="Enable scratch register ZSR_FLUSH for cache flushing")
     parser.add_argument("--mmu", action="store_true",
                         help="Enable scratch registers for MMU usage")
     parser.add_argument("--syscall-scratch", action="store_true",
@@ -32,7 +32,7 @@ def parse_args():
 NEEDED = ["A0SAVE", "CPU"]
 if args.mmu:
     NEEDED += ["DBLEXC", "DEPC_SAVE", "EXCCAUSE_SAVE"]
-if args.coherence:
+if args.flush_reg:
     NEEDED += ["FLUSH"]
 
 coreisa = args.coreisa
diff --git a/arch/xtensa/core/mmu.c b/arch/xtensa/core/mmu.c
index c1073ac0247..dd20136427a 100644
--- a/arch/xtensa/core/mmu.c
+++ b/arch/xtensa/core/mmu.c
@@ -16,37 +16,33 @@ BUILD_ASSERT((CONFIG_PRIVILEGED_STACK_SIZE > 0) &&
 
 #define ASID_INVALID 0
 
-struct tlb_regs {
-	uint32_t rasid;
-	uint32_t ptevaddr;
-	uint32_t ptepin_as;
-	uint32_t ptepin_at;
-	uint32_t vecpin_as;
-	uint32_t vecpin_at;
-};
-
-static void compute_regs(uint32_t user_asid, uint32_t *l1_page, struct tlb_regs *regs)
+extern uint32_t *xtensa_kernel_ptables;
+
+void xtensa_mmu_compute_domain_regs(struct arch_mem_domain *domain)
 {
 	uint32_t vecbase = XTENSA_RSR("VECBASE");
+	uint32_t *l1_page = domain->ptables;
+	uint32_t user_asid = domain->asid;
 
 	__ASSERT_NO_MSG((((uint32_t)l1_page) & 0xfff) == 0);
 	__ASSERT_NO_MSG((user_asid == 0) || ((user_asid > 2) &&
 				(user_asid < XTENSA_MMU_SHARED_ASID)));
 
 	/* We don't use ring 1, ring 0 ASID must be 1 */
-	regs->rasid = (XTENSA_MMU_SHARED_ASID << 24) |
-		      (user_asid << 16) | 0x000201;
+	domain->reg_asid = (XTENSA_MMU_SHARED_ASID << 24) |
+				(user_asid << 16) | 0x000201;
 
 	/* Derive PTEVADDR from ASID so each domain gets its own PTE area */
-	regs->ptevaddr = CONFIG_XTENSA_MMU_PTEVADDR + user_asid * 0x400000;
+	domain->reg_ptevaddr = CONFIG_XTENSA_MMU_PTEVADDR + user_asid * 0x400000;
 
 	/* The ptables code doesn't add the mapping for the l1 page itself */
-	l1_page[XTENSA_MMU_L1_POS(regs->ptevaddr)] =
+	l1_page[XTENSA_MMU_L1_POS(domain->reg_ptevaddr)] =
 		(uint32_t)l1_page | XTENSA_MMU_PAGE_TABLE_ATTR;
 
-	regs->ptepin_at = (uint32_t)l1_page;
-	regs->ptepin_as = XTENSA_MMU_PTE_ENTRY_VADDR(regs->ptevaddr, regs->ptevaddr)
-			  | XTENSA_MMU_PTE_WAY;
+	domain->reg_ptepin_at = (uint32_t)l1_page;
+	domain->reg_ptepin_as = XTENSA_MMU_PTE_ENTRY_VADDR(domain->reg_ptevaddr,
+							   domain->reg_ptevaddr)
+				| XTENSA_MMU_PTE_WAY;
 
 	/* Pin mapping for refilling the vector address into the ITLB
 	 * (for handling TLB miss exceptions). Note: this is NOT an
@@ -58,9 +54,10 @@ static void compute_regs(uint32_t user_asid, uint32_t *l1_page, struct tlb_regs
 	 */
 	uint32_t vb_pte = l1_page[XTENSA_MMU_L1_POS(vecbase)];
 
-	regs->vecpin_at = vb_pte;
-	regs->vecpin_as = XTENSA_MMU_PTE_ENTRY_VADDR(regs->ptevaddr, vecbase)
-			  | XTENSA_MMU_VECBASE_WAY;
+	domain->reg_vecpin_at = vb_pte;
+	domain->reg_vecpin_as = XTENSA_MMU_PTE_ENTRY_VADDR(domain->reg_ptevaddr,
+							   vecbase)
+				| XTENSA_MMU_VECBASE_WAY;
 }
 
 /* Switch to a new page table.  There are four items we have to set in
@@ -78,18 +75,8 @@ static void compute_regs(uint32_t user_asid, uint32_t *l1_page, struct tlb_regs
  * couldn't think of a way to do the alignment statically that also
  * interoperated well with inline assembly).
  */
-void xtensa_set_paging(uint32_t user_asid, uint32_t *l1_page)
+void xtensa_mmu_set_paging(struct arch_mem_domain *domain)
 {
-	/* Optimization note: the registers computed here are pure
-	 * functions of the two arguments.  With a minor API tweak,
-	 * they could be cached in e.g. a thread struct instead of
-	 * being recomputed.  This is called on context switch paths
-	 * and is performance-sensitive.
-	 */
-	struct tlb_regs regs;
-
-	compute_regs(user_asid, l1_page, &regs);
-
 	__asm__ volatile("j 1f\n"
 			 ".align 16\n" /* enough for 5 insns */
 			 "1:\n"
@@ -98,12 +85,12 @@ void xtensa_set_paging(uint32_t user_asid, uint32_t *l1_page)
 			 "wdtlb %2, %3\n"
 			 "wdtlb %4, %5\n"
 			 "isync"
-			 :: "r"(regs.ptevaddr), "r"(regs.rasid),
-			    "r"(regs.ptepin_at), "r"(regs.ptepin_as),
-			    "r"(regs.vecpin_at), "r"(regs.vecpin_as));
+			 :: "r"(domain->reg_ptevaddr), "r"(domain->reg_asid),
+			    "r"(domain->reg_ptepin_at), "r"(domain->reg_ptepin_as),
+			    "r"(domain->reg_vecpin_at), "r"(domain->reg_vecpin_as));
 }
 
-/* This is effectively the same algorithm from xtensa_set_paging(),
+/* This is effectively the same algorithm from xtensa_mmu_set_paging(),
  * but it also disables the hardware-initialized 512M TLB entries in
  * way 6 (because the hardware disallows duplicate TLB mappings).  For
  * instruction fetches this produces a critical ordering constraint:
@@ -121,12 +108,19 @@ void xtensa_set_paging(uint32_t user_asid, uint32_t *l1_page)
  * asm for correctness.  The other 13 entries get invalidated in a C
  * loop at the end.
  */
-void xtensa_init_paging(uint32_t *l1_page)
+void xtensa_mmu_init_paging(void)
 {
 	extern char z_xt_init_pc; /* defined in asm below */
-	struct tlb_regs regs;
 	unsigned int initial_rasid;
 
+	/* When this is called in xtensa_mmu_init(), the default memory
+	 * domain struct has not been initialized, and memory domains
+	 * are not ready to be used. So we need a local copy of
+	 * struct arch_mem_domain to store the register values to be
+	 * programmed into hardware.
+	 */
+	struct arch_mem_domain domain;
+
 	/* The initial rasid after hardware initialization is 0x04030201.
 	 * 1 is hardwired to ring 0, other slots must be different
 	 * from each other and must not be 0.
@@ -146,10 +140,12 @@ void xtensa_init_paging(uint32_t *l1_page)
 	sys_cache_data_flush_and_invd_all();
 #endif
 
-	compute_regs(ASID_INVALID, l1_page, &regs);
+	domain.asid = ASID_INVALID;
+	domain.ptables = xtensa_kernel_ptables;
+	xtensa_mmu_compute_domain_regs(&domain);
 
-	uint32_t idtlb_pte = (regs.ptevaddr & 0xe0000000) | XCHAL_SPANNING_WAY;
-	uint32_t idtlb_stk = (((uint32_t)&regs) & ~0xfff) | XCHAL_SPANNING_WAY;
+	uint32_t idtlb_pte = (domain.reg_ptevaddr & 0xe0000000) | XCHAL_SPANNING_WAY;
+	uint32_t idtlb_stk = (((uint32_t)&domain) & ~0xfff) | XCHAL_SPANNING_WAY;
 	uint32_t iitlb_pc  = (((uint32_t)&z_xt_init_pc) & ~0xfff) | XCHAL_SPANNING_WAY;
 
 	/* Note: the jump is mostly pedantry, as it's almost
@@ -171,9 +167,9 @@ void xtensa_init_paging(uint32_t *l1_page)
 			 "isync\n"
 			 "iitlb %8\n" /* invalidate pc */
 			 "isync\n" /* <--- traps a ITLB miss */
-			 :: "r"(regs.ptevaddr), "r"(initial_rasid),
-			    "r"(regs.ptepin_at), "r"(regs.ptepin_as),
-			    "r"(regs.vecpin_at), "r"(regs.vecpin_as),
+			 :: "r"(domain.reg_ptevaddr), "r"(initial_rasid),
+			    "r"(domain.reg_ptepin_at), "r"(domain.reg_ptepin_as),
+			    "r"(domain.reg_vecpin_at), "r"(domain.reg_vecpin_as),
 			    "r"(idtlb_pte), "r"(idtlb_stk), "r"(iitlb_pc));
 
 	/* Invalidate the remaining (unused by this function)
diff --git a/arch/xtensa/core/offsets/offsets.c b/arch/xtensa/core/offsets/offsets.c
index 69df38275bf..f0b75c999cc 100644
--- a/arch/xtensa/core/offsets/offsets.c
+++ b/arch/xtensa/core/offsets/offsets.c
@@ -67,8 +67,22 @@ GEN_OFFSET_SYM(_xtensa_irq_bsa_t, hifi);
 
 #ifdef CONFIG_USERSPACE
 GEN_OFFSET_SYM(_thread_arch_t, psp);
+GEN_OFFSET_SYM(_thread_arch_t, return_ps);
+GEN_OFFSET_SYM(_thread_t, switch_handle);
 #ifdef CONFIG_XTENSA_MMU
 GEN_OFFSET_SYM(_thread_arch_t, ptables);
+
+GEN_OFFSET_SYM(_thread_t, mem_domain_info);
+GEN_OFFSET_SYM(_mem_domain_info_t, mem_domain);
+GEN_OFFSET_SYM(k_mem_domain_t, arch);
+
+GEN_OFFSET_SYM(arch_mem_domain_t, reg_asid);
+GEN_OFFSET_SYM(arch_mem_domain_t, reg_ptevaddr);
+GEN_OFFSET_SYM(arch_mem_domain_t, reg_ptepin_as);
+GEN_OFFSET_SYM(arch_mem_domain_t, reg_ptepin_at);
+GEN_OFFSET_SYM(arch_mem_domain_t, reg_vecpin_as);
+GEN_OFFSET_SYM(arch_mem_domain_t, reg_vecpin_at);
+
 #endif
 #ifdef CONFIG_XTENSA_MPU
 GEN_OFFSET_SYM(_thread_arch_t, mpu_map);
diff --git a/arch/xtensa/core/prep_c.c b/arch/xtensa/core/prep_c.c
index 6dbab69f50f..771ad7e4230 100644
--- a/arch/xtensa/core/prep_c.c
+++ b/arch/xtensa/core/prep_c.c
@@ -44,10 +44,12 @@ void z_prep_c(void)
 	 */
 	sys_cache_data_flush_and_invd_all();
 
+#if !defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY)
 	/* Our cache top stash location might have junk in it from a
 	 * pre-boot environment.  Must be zero or valid!
 	 */
 	XTENSA_WSR(ZSR_FLUSH_STR, 0);
+#endif
 #endif
 
 	cpu0->nested = 0;
diff --git a/arch/xtensa/core/ptables.c b/arch/xtensa/core/ptables.c
index c02ecc64b0d..fa7d4fb0f70 100644
--- a/arch/xtensa/core/ptables.c
+++ b/arch/xtensa/core/ptables.c
@@ -157,17 +157,6 @@ static const struct xtensa_mmu_range mmu_zephyr_ranges[] = {
 	},
 };
 
-static inline uint32_t *thread_page_tables_get(const struct k_thread *thread)
-{
-#ifdef CONFIG_USERSPACE
-	if ((thread->base.user_options & K_USER) != 0U) {
-		return thread->arch.ptables;
-	}
-#endif
-
-	return xtensa_kernel_ptables;
-}
-
 /**
  * @brief Check if the page table entry is illegal.
  *
@@ -250,18 +239,25 @@ static void map_memory_range(const uint32_t start, const uint32_t end,
 static void map_memory(const uint32_t start, const uint32_t end,
 		       const uint32_t attrs)
 {
-	map_memory_range(start, end, attrs);
-
 #ifdef CONFIG_XTENSA_MMU_DOUBLE_MAP
+	uint32_t uc_attrs = attrs & ~XTENSA_MMU_PTE_ATTR_CACHED_MASK;
+	uint32_t c_attrs = attrs | XTENSA_MMU_CACHED_WB;
+
 	if (sys_cache_is_ptr_uncached((void *)start)) {
+		map_memory_range(start, end, uc_attrs);
+
 		map_memory_range(POINTER_TO_UINT(sys_cache_cached_ptr_get((void *)start)),
-			POINTER_TO_UINT(sys_cache_cached_ptr_get((void *)end)),
-			attrs | XTENSA_MMU_CACHED_WB);
+			POINTER_TO_UINT(sys_cache_cached_ptr_get((void *)end)),	c_attrs);
 	} else if (sys_cache_is_ptr_cached((void *)start)) {
+		map_memory_range(start, end, c_attrs);
+
 		map_memory_range(POINTER_TO_UINT(sys_cache_uncached_ptr_get((void *)start)),
-			POINTER_TO_UINT(sys_cache_uncached_ptr_get((void *)end)), attrs);
-	}
+			POINTER_TO_UINT(sys_cache_uncached_ptr_get((void *)end)), uc_attrs);
+	} else
 #endif
+	{
+		map_memory_range(start, end, attrs);
+	}
 }
 
 static void xtensa_init_page_tables(void)
@@ -313,7 +309,7 @@ void xtensa_mmu_init(void)
 {
 	xtensa_init_page_tables();
 
-	xtensa_init_paging(xtensa_kernel_ptables);
+	xtensa_mmu_init_paging();
 
 	/*
 	 * This is used to determine whether we are faulting inside double
@@ -328,7 +324,7 @@ void xtensa_mmu_init(void)
 void xtensa_mmu_reinit(void)
 {
 	/* First initialize the hardware */
-	xtensa_init_paging(xtensa_kernel_ptables);
+	xtensa_mmu_init_paging();
 
 #ifdef CONFIG_USERSPACE
 	struct k_thread *thread = _current_cpu->current;
@@ -337,7 +333,7 @@ void xtensa_mmu_reinit(void)
 
 
 	/* Set the page table for current context */
-	xtensa_set_paging(domain->asid, domain->ptables);
+	xtensa_mmu_set_paging(domain);
 #endif /* CONFIG_USERSPACE */
 
 	arch_xtensa_mmu_post_init(_current_cpu->id == 0);
@@ -706,7 +702,7 @@ void xtensa_mmu_tlb_shootdown(void)
 			 */
 			struct arch_mem_domain *domain =
 				&(thread->mem_domain_info.mem_domain->arch);
-			xtensa_set_paging(domain->asid, (uint32_t *)thread_ptables);
+			xtensa_mmu_set_paging(domain);
 		}
 
 	}
@@ -725,6 +721,15 @@ void xtensa_mmu_tlb_shootdown(void)
 
 #ifdef CONFIG_USERSPACE
 
+static inline uint32_t *thread_page_tables_get(const struct k_thread *thread)
+{
+	if ((thread->base.user_options & K_USER) != 0U) {
+		return thread->arch.ptables;
+	}
+
+	return xtensa_kernel_ptables;
+}
+
 static inline uint32_t *alloc_l1_table(void)
 {
 	uint16_t idx;
@@ -833,6 +838,7 @@ int arch_mem_domain_init(struct k_mem_domain *domain)
 	sys_slist_append(&xtensa_domain_list, &domain->arch.node);
 
 end:
+	xtensa_mmu_compute_domain_regs(&domain->arch);
 	ret = 0;
 
 err:
@@ -995,7 +1001,9 @@ int arch_mem_domain_thread_add(struct k_thread *thread)
 	 * the current thread running.
 	 */
 	if (thread == _current_cpu->current) {
-		xtensa_set_paging(domain->arch.asid, thread->arch.ptables);
+		struct arch_mem_domain *arch_domain = &(domain->arch);
+
+		xtensa_mmu_set_paging(arch_domain);
 	}
 
 #if CONFIG_MP_MAX_NUM_CPUS > 1
@@ -1114,26 +1122,4 @@ int arch_buffer_validate(const void *addr, size_t size, int write)
 	return mem_buffer_validate(addr, size, write, XTENSA_MMU_USER_RING);
 }
 
-void xtensa_swap_update_page_tables(struct k_thread *incoming)
-{
-	uint32_t *ptables = incoming->arch.ptables;
-	struct arch_mem_domain *domain =
-		&(incoming->mem_domain_info.mem_domain->arch);
-
-	xtensa_set_paging(domain->asid, ptables);
-
-#ifdef CONFIG_XTENSA_INVALIDATE_MEM_DOMAIN_TLB_ON_SWAP
-	struct k_mem_domain *mem_domain = incoming->mem_domain_info.mem_domain;
-
-	for (int idx = 0; idx < mem_domain->num_partitions; idx++) {
-		struct k_mem_partition *part = &mem_domain->partitions[idx];
-		uintptr_t end = part->start + part->size;
-
-		for (uintptr_t addr = part->start; addr < end; addr += CONFIG_MMU_PAGE_SIZE) {
-			xtensa_dtlb_vaddr_invalidate((void *)addr);
-		}
-	}
-#endif
-}
-
 #endif /* CONFIG_USERSPACE */
diff --git a/arch/xtensa/core/syscall_helper.c b/arch/xtensa/core/syscall_helper.c
index f9673e67814..9e14a560e7e 100644
--- a/arch/xtensa/core/syscall_helper.c
+++ b/arch/xtensa/core/syscall_helper.c
@@ -25,7 +25,7 @@ uintptr_t xtensa_syscall_helper_args_6(uintptr_t arg1, uintptr_t arg2,
 	register uintptr_t a8 __asm__("%a8") = arg5;
 	register uintptr_t a9 __asm__("%a9") = arg6;
 
-	__asm__ volatile("syscall\n\t"
+	__asm__ volatile(XTENSA_SYSCALL_ASM
 			 : "=r" (a2)
 			 : "r" (a2), "r" (a6), "r" (a3), "r" (a4),
 			   "r" (a5), "r" (a8), "r" (a9)
@@ -45,7 +45,7 @@ uintptr_t xtensa_syscall_helper_args_5(uintptr_t arg1, uintptr_t arg2,
 	register uintptr_t a5 __asm__("%a5") = arg4;
 	register uintptr_t a8 __asm__("%a8") = arg5;
 
-	__asm__ volatile("syscall\n\t"
+	__asm__ volatile(XTENSA_SYSCALL_ASM
 			 : "=r" (a2)
 			 : "r" (a2), "r" (a6), "r" (a3), "r" (a4),
 			   "r" (a5), "r" (a8)
@@ -64,7 +64,7 @@ uintptr_t xtensa_syscall_helper_args_4(uintptr_t arg1, uintptr_t arg2,
 	register uintptr_t a4 __asm__("%a4") = arg3;
 	register uintptr_t a5 __asm__("%a5") = arg4;
 
-	__asm__ volatile("syscall\n\t"
+	__asm__ volatile(XTENSA_SYSCALL_ASM
 			 : "=r" (a2)
 			 : "r" (a2), "r" (a6), "r" (a3), "r" (a4),
 			   "r" (a5)
@@ -73,61 +73,6 @@ uintptr_t xtensa_syscall_helper_args_4(uintptr_t arg1, uintptr_t arg2,
 	return a2;
 }
 
-uintptr_t xtensa_syscall_helper_args_3(uintptr_t arg1, uintptr_t arg2,
-				       uintptr_t arg3, uintptr_t call_id)
-{
-	register uintptr_t a2 __asm__("%a2") = call_id;
-	register uintptr_t a6 __asm__("%a6") = arg1;
-	register uintptr_t a3 __asm__("%a3") = arg2;
-	register uintptr_t a4 __asm__("%a4") = arg3;
-
-	__asm__ volatile("syscall\n\t"
-			 : "=r" (a2)
-			 : "r" (a2), "r" (a6), "r" (a3), "r" (a4)
-			 : "memory");
-
-	return a2;
-}
-
-uintptr_t xtensa_syscall_helper_args_2(uintptr_t arg1, uintptr_t arg2,
-				       uintptr_t call_id)
-{
-	register uintptr_t a2 __asm__("%a2") = call_id;
-	register uintptr_t a6 __asm__("%a6") = arg1;
-	register uintptr_t a3 __asm__("%a3") = arg2;
-
-	__asm__ volatile("syscall\n\t"
-			 : "=r" (a2)
-			 : "r" (a2), "r" (a6), "r" (a3)
-			 : "memory");
-
-	return a2;
-}
-
-uintptr_t xtensa_syscall_helper_args_1(uintptr_t arg1, uintptr_t call_id)
-{
-	register uintptr_t a2 __asm__("%a2") = call_id;
-	register uintptr_t a6 __asm__("%a6") = arg1;
-
-	__asm__ volatile("syscall\n\t"
-			 : "=r" (a2)
-			 : "r" (a2), "r" (a6)
-			 : "memory");
-
-	return a2;
-}
-
-uintptr_t xtensa_syscall_helper_args_0(uintptr_t call_id)
-{
-	register uintptr_t a2 __asm__("%a2") = call_id;
-
-	__asm__ volatile("syscall\n\t"
-			 : "=r" (a2)
-			 : "r" (a2)
-			 : "memory");
-
-	return a2;
-}
 #endif /* CONFIG_XTENSA_SYSCALL_USE_HELPER */
 
 #if XCHAL_HAVE_THREADPTR == 0
diff --git a/arch/xtensa/core/thread.c b/arch/xtensa/core/thread.c
index f9b8179173d..2bf1a7e11d3 100644
--- a/arch/xtensa/core/thread.c
+++ b/arch/xtensa/core/thread.c
@@ -42,11 +42,7 @@ static void *init_stack(struct k_thread *thread, int *stack_top,
 	void *ret;
 	_xtensa_irq_stack_frame_a11_t *frame;
 #ifdef CONFIG_USERSPACE
-	struct xtensa_thread_stack_header *header =
-		(struct xtensa_thread_stack_header *)thread->stack_obj;
-
-	thread->arch.psp = header->privilege_stack +
-		sizeof(header->privilege_stack);
+	thread->arch.psp = NULL;
 #endif
 
 	/* Not-a-cpu ID Ensures that the first time this is run, the
@@ -70,26 +66,19 @@ static void *init_stack(struct k_thread *thread, int *stack_top,
 
 	(void)memset(frame, 0, bsasz);
 
-	frame->bsa.ps = PS_WOE | PS_UM | PS_CALLINC(1);
 #ifdef CONFIG_USERSPACE
-	if ((thread->base.user_options & K_USER) == K_USER) {
-#ifdef CONFIG_INIT_STACKS
-		/* setup_thread_stack() does not initialize the architecture specific
-		 * privileged stack. So we need to do it manually here as this function
-		 * is called by arch_new_thread() via z_setup_new_thread() after
-		 * setup_thread_stack() but before thread starts running.
-		 *
-		 * Note that only user threads have privileged stacks and kernel
-		 * only threads do not.
-		 */
-		(void)memset(&header->privilege_stack[0], 0xaa, sizeof(header->privilege_stack));
-#endif
+	/* _restore_context uses this instead of frame->bsa.ps to
+	 * restore PS value.
+	 */
+	thread->arch.return_ps = PS_WOE | PS_UM | PS_CALLINC(1);
 
+	if ((thread->base.user_options & K_USER) == K_USER) {
 		frame->bsa.pc = (uintptr_t)arch_user_mode_enter;
 	} else {
 		frame->bsa.pc = (uintptr_t)z_thread_entry;
 	}
 #else
+	frame->bsa.ps = PS_WOE | PS_UM | PS_CALLINC(1);
 	frame->bsa.pc = (uintptr_t)z_thread_entry;
 #endif
 
@@ -159,6 +148,30 @@ FUNC_NORETURN void arch_user_mode_enter(k_thread_entry_t user_entry,
 	struct k_thread *current = _current;
 	size_t stack_end;
 
+	struct xtensa_thread_stack_header *header =
+		(struct xtensa_thread_stack_header *)current->stack_obj;
+
+	current->arch.psp = header->privilege_stack +
+		sizeof(header->privilege_stack);
+
+#ifdef CONFIG_INIT_STACKS
+	/* setup_thread_stack() does not initialize the architecture specific
+	 * privileged stack. So we need to do it manually here as this function
+	 * is called by arch_new_thread() via z_setup_new_thread() after
+	 * setup_thread_stack() but before thread starts running.
+	 *
+	 * Note that only user threads have privileged stacks and kernel
+	 * only threads do not.
+	 */
+	(void)memset(&header->privilege_stack[0], 0xaa, sizeof(header->privilege_stack));
+
+#endif
+
+#ifdef CONFIG_KERNEL_COHERENCE
+	sys_cache_data_flush_and_invd_range(&header->privilege_stack[0],
+					    sizeof(header->privilege_stack));
+#endif
+
 	/* Transition will reset stack pointer to initial, discarding
 	 * any old context since this is a one-way operation
 	 */
diff --git a/arch/xtensa/core/userspace.S b/arch/xtensa/core/userspace.S
index 3db5d8cea8d..be143ed1f3a 100644
--- a/arch/xtensa/core/userspace.S
+++ b/arch/xtensa/core/userspace.S
@@ -53,6 +53,12 @@ _is_user_context_return:
 _not_checking_user_context:
 	rsr a2, ZSR_SYSCALL_SCRATCH
 #endif
+
+	/* Need to disable any interrupts while we are saving
+	 * register content to avoid any interferences.
+	 */
+	rsil a0, 0xf
+
 	rsr a0, ZSR_CPU
 	l32i a0, a0, ___cpu_t_current_OFFSET
 	l32i a0, a0, _thread_offset_to_psp
@@ -65,21 +71,27 @@ _not_checking_user_context:
 	rsr a2, ZSR_A0SAVE
 	s32i a2, a0, ___xtensa_irq_bsa_t_a0_OFFSET
 	rsr.ps a2
-	movi a3, ~PS_OWB_MASK
+	movi a3, ~PS_OWB_MASK & ~PS_EXCM_MASK
 	and a2, a2, a3
 	s32i a2, a0, ___xtensa_irq_bsa_t_ps_OFFSET
-	rsr.epc1 a2
-	s32i a2, a0, ___xtensa_irq_bsa_t_pc_OFFSET
 
-#if XCHAL_HAVE_NMI
-	movi a2, PS_WOE|PS_INTLEVEL(XCHAL_NMILEVEL)
-#elif XCHAL_HAVE_INTERRUPTS
-	movi a2, PS_WOE|PS_INTLEVEL(XCHAL_NUM_INTLEVELS)
-#else
-#error Xtensa core with no interrupt support is used
-#endif
+	/* Manipulate PC where we will return to after syscall.
+	 * This is needed as syscall will stash the PC where
+	 * the syscall instruction locates, instead of
+	 * the instruction after it. We need to increment it to
+	 * execute the next instruction when we return.
+	 * The instruction size is 3 bytes, so lets just add it.
+	 */
+	rsr.epc1 a3
+	addi a3, a3, 3
+	s32i a3, a0, ___xtensa_irq_bsa_t_pc_OFFSET
+
+	/* Need to setup PS so we can spill all registers.
+	 * EXCM and RING bits need to be cleared as CPU
+	 * needs to run in kernel and non-exception modes
+	 * for window rotation to work.
+	 */
 	rsr.ps a3
-	or a3, a3, a2
 	movi a2, ~(PS_EXCM | PS_RING_MASK)
 	and a3, a3, a2
 	wsr.ps a3
@@ -95,34 +107,7 @@ _not_checking_user_context:
 
 	mov a1, a0
 
-	l32i a3, a1, ___xtensa_irq_bsa_t_pc_OFFSET
-#if XCHAL_HAVE_LOOPS
-	/* If the syscall instruction was the last instruction in the body of
-	 * a zero-overhead loop, and the loop will execute again, decrement
-	 * the loop count and resume execution at the head of the loop.
-	 */
-	rsr.lend a2
-	addi a3, a3, 3
-	bne a2, a3, end_loop
-	rsr.lcount a2
-	beqz a2, end_loop
-	addi a2, a2, -1
-	wsr.lcount a2
-	rsr.lbeg a3
-end_loop:
-#else
-	/* EPC1 (and now a3) contains the address that invoked syscall.
-	 * We need to increment it to execute the next instruction when
-	 * we return. The instruction size is 3 bytes, so lets just add it.
-	 */
-	addi a3, a3, 3
-#endif
-	s32i a3, a1, ___xtensa_irq_bsa_t_pc_OFFSET
-	ODD_REG_SAVE
-
-#if defined(CONFIG_XTENSA_HIFI_SHARING)
-	call0 _xtensa_hifi_save
-#endif
+	ODD_REG_SAVE a0, a1
 
 	call0 xtensa_save_high_regs
 
@@ -134,8 +119,7 @@ end_loop:
 _id_ok:
 	/* Find the function handler for the given syscall id. */
 	movi a3, _k_syscall_table
-	slli a2, a2, 2
-	add a2, a2, a3
+	addx4 a2, a2, a3
 	l32i a2, a2, 0
 
 #if XCHAL_HAVE_THREADPTR
@@ -173,12 +157,14 @@ _id_ok:
 
 	/* Stack frame pointer is the 7th argument to z_mrsh_*()
 	 * as ssf, and must be put on stack to be consumed.
+	 *
+	 * Subtract 16 bytes as stack needs to be 16-byte aligned.
 	 */
 	mov a3, a1
-	addi a1, a1, -4
+	addi a1, a1, -16
 	s32i a3, a1, 0
 
-	l32i a3, a1, 4
+	l32i a3, a1, 16
 	l32i a7, a3, ___xtensa_irq_bsa_t_a3_OFFSET
 
 
@@ -195,7 +181,7 @@ _id_ok:
 	 * actual the stack frame. So restoration of registers
 	 * can be done properly when finishing syscalls.
 	 */
-	addi a1, a1, 4
+	addi a1, a1, 16
 
 	/* copy return value. Lets put it in the top of stack
 	 * because registers will be clobbered in
@@ -204,25 +190,13 @@ _id_ok:
 	l32i a3, a1, 0
 	s32i a6, a3, ___xtensa_irq_bsa_t_a2_OFFSET
 
-	j _syscall_returned
-
 _syscall_returned:
+	/* Disable interrupts as we are restoring context. */
+	rsil a0, 0xf
+
 	call0 xtensa_restore_high_regs
 
-	l32i a3, a1, ___xtensa_irq_bsa_t_sar_OFFSET
-	wsr a3, SAR
-#if XCHAL_HAVE_LOOPS
-	l32i a3, a1, ___xtensa_irq_bsa_t_lbeg_OFFSET
-	wsr a3, LBEG
-	l32i a3, a1, ___xtensa_irq_bsa_t_lend_OFFSET
-	wsr a3, LEND
-	l32i a3, a1, ___xtensa_irq_bsa_t_lcount_OFFSET
-	wsr a3, LCOUNT
-#endif
-#if XCHAL_HAVE_S32C1I
-	l32i a3, a1, ___xtensa_irq_bsa_t_scompare1_OFFSET
-	wsr a3, SCOMPARE1
-#endif
+	ODD_REG_RESTORE a3, a1
 
 #if XCHAL_HAVE_THREADPTR
 #ifdef CONFIG_THREAD_LOCAL_STORAGE
@@ -231,18 +205,14 @@ _syscall_returned:
 	add a0, a3, a0
 	movi a3, 1
 	s32i a3, a0, 0
-#else
-	rsr a3, ZSR_CPU
-	l32i a3, a3, ___cpu_t_current_OFFSET
-	wur.THREADPTR a3
 #endif
 #endif /* XCHAL_HAVE_THREADPTR */
 
 	l32i a3, a1, ___xtensa_irq_bsa_t_ps_OFFSET
-	wsr.ps a3
+	wsr.ZSR_EPS a3
 
 	l32i a3, a1, ___xtensa_irq_bsa_t_pc_OFFSET
-	wsr.epc1 a3
+	wsr.ZSR_EPC a3
 
 	l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
 	l32i a2, a1, ___xtensa_irq_bsa_t_a2_OFFSET
@@ -251,7 +221,7 @@ _syscall_returned:
 	l32i a1, a1, ___xtensa_irq_bsa_t_scratch_OFFSET
 	rsync
 
-	rfe
+	rfi ZSR_RFI_LEVEL
 
 _bad_syscall:
 	movi a2, K_SYSCALL_BAD
@@ -300,7 +270,7 @@ xtensa_userspace_enter:
 
 	l32i a6, a1, 24
 #ifdef CONFIG_XTENSA_MMU
-	call4 xtensa_swap_update_page_tables
+	SWAP_PAGE_TABLE a6, a3, a7
 #endif
 #ifdef CONFIG_XTENSA_MPU
 	call4 xtensa_mpu_map_write
@@ -331,8 +301,11 @@ xtensa_userspace_enter:
 	/* Go back to user stack */
 	l32i a1, a1, 4
 
+	/* Disabling interrupts as we need to use ZSR_EPC and ZSR_EPS */
+	rsil a0, 0xf
+
 	movi a0, z_thread_entry
-	wsr.epc2 a0
+	wsr.ZSR_EPC a0
 
 	/* Configuring PS register.
 	 * We have to set callinc as well, since the called
@@ -346,9 +319,9 @@ xtensa_userspace_enter:
 	movi a0, PS_WOE|PS_CALLINC(1)|PS_UM|PS_RING(1)
 #endif
 
-	wsr a0, EPS2
+	wsr.ZSR_EPS a0
 
 	/* Wipe out a0 (thre is no return from this function */
 	movi a0, 0
 
-	rfi 2
+	rfi ZSR_RFI_LEVEL
diff --git a/arch/xtensa/core/xtensa_asm2_util.S b/arch/xtensa/core/xtensa_asm2_util.S
index 11b18013033..6892831f52a 100644
--- a/arch/xtensa/core/xtensa_asm2_util.S
+++ b/arch/xtensa/core/xtensa_asm2_util.S
@@ -153,9 +153,34 @@ _restore_context:
 
 	l32i a0, a1, ___xtensa_irq_bsa_t_pc_OFFSET
 	wsr a0, ZSR_EPC
+
+#ifdef CONFIG_USERSPACE
+	/* When restoring context via xtensa_switch and
+	 * returning from non-nested interrupts, we use
+	 * the stashed PS value in the thread struct
+	 * instead of the one in the thread stack.
+	 * Both scenarios will have nested value of 0.
+	 */
+	rsr.ZSR_CPU a2
+	l32i a0, a2, ___cpu_t_nested_OFFSET
+	bnez a0, _restore_ps_from_stack
+
+	l32i a0, a2, ___cpu_t_current_OFFSET
+	l32i a0, a0, _thread_offset_to_return_ps
+	wsr a0, ZSR_EPS
+
+	j _restore_ps_after
+
+_restore_ps_from_stack:
+#endif
+
 	l32i a0, a1, ___xtensa_irq_bsa_t_ps_OFFSET
 	wsr a0, ZSR_EPS
 
+#ifdef CONFIG_USERSPACE
+_restore_ps_after:
+#endif
+
 #if XCHAL_HAVE_FP && defined(CONFIG_CPU_HAS_FPU) && defined(CONFIG_FPU_SHARING)
 	FPU_REG_RESTORE
 #endif
@@ -165,25 +190,8 @@ _restore_context:
 	call0 _xtensa_hifi_load
 #endif
 
-	l32i a0, a1, ___xtensa_irq_bsa_t_sar_OFFSET
-	wsr a0, SAR
-#if XCHAL_HAVE_LOOPS
-	l32i a0, a1, ___xtensa_irq_bsa_t_lbeg_OFFSET
-	wsr a0, LBEG
-	l32i a0, a1, ___xtensa_irq_bsa_t_lend_OFFSET
-	wsr a0, LEND
-	l32i a0, a1, ___xtensa_irq_bsa_t_lcount_OFFSET
-	wsr a0, LCOUNT
-#endif
-#if XCHAL_HAVE_S32C1I
-	l32i a0, a1, ___xtensa_irq_bsa_t_scompare1_OFFSET
-	wsr a0, SCOMPARE1
-#endif
-#if XCHAL_HAVE_THREADPTR && \
-	(defined(CONFIG_USERSPACE) || defined(CONFIG_THREAD_LOCAL_STORAGE))
-	l32i a0, a1, ___xtensa_irq_bsa_t_threadptr_OFFSET
-	wur a0, THREADPTR
-#endif
+	ODD_REG_RESTORE a0, a1
+
 	rsync
 
 	l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
@@ -232,7 +240,31 @@ xtensa_arch_kernel_oops_epc:
 .global xtensa_switch
 .align 4
 xtensa_switch:
+#ifdef CONFIG_USERSPACE
+	entry a1, 32
+
+	s32i a4, a1, 0
+	s32i a5, a1, 4
+	s32i a6, a1, 8
+	s32i a7, a1, 12
+
+	rsr a6, ZSR_CPU
+	l32i a6, a6, ___cpu_t_current_OFFSET
+#ifdef CONFIG_XTENSA_MMU
+	SWAP_PAGE_TABLE a6, a4, a7
+#endif
+#ifdef CONFIG_XTENSA_MPU
+	call4 xtensa_mpu_map_write
+#endif
+
+	l32i a7, a1, 12
+	l32i a6, a1, 8
+	l32i a5, a1, 4
+	l32i a4, a1, 0
+#else
 	entry a1, 16
+#endif
+
 	SPILL_ALL_WINDOWS
 	addi a1, a1, -___xtensa_irq_bsa_t_SIZEOF
 
@@ -245,11 +277,27 @@ xtensa_switch:
 	s32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
 	s32i a2, a1, ___xtensa_irq_bsa_t_a2_OFFSET
 	s32i a3, a1, ___xtensa_irq_bsa_t_a3_OFFSET
-	ODD_REG_SAVE
+	ODD_REG_SAVE a0, a1
+
+#if XCHAL_HAVE_FP && defined(CONFIG_CPU_HAS_FPU) && defined(CONFIG_FPU_SHARING)
+	FPU_REG_SAVE
+#endif
 
 	/* Stash our PS register contents and a "restore" PC. */
 	rsr a0, PS
 	s32i a0, a1, ___xtensa_irq_bsa_t_ps_OFFSET
+
+#ifdef CONFIG_USERSPACE
+	/* Backtrack to the head of thread struct and
+	 * then store the PS value to be restored in
+	 * the architecture specific section.
+	 * This will be used to restore PS instead of
+	 * the one stashed inside stack.
+	 */
+	addi a3, a3, -___thread_t_switch_handle_OFFSET
+	s32i a0, a3, _thread_offset_to_return_ps
+#endif
+
 	movi a0, _switch_restore_pc
 	s32i a0, a1, ___xtensa_irq_bsa_t_pc_OFFSET
 
@@ -260,10 +308,11 @@ xtensa_switch:
 	/* Now the high registers */
 	call0 xtensa_save_high_regs
 
-#ifdef CONFIG_KERNEL_COHERENCE
+#if defined(CONFIG_KERNEL_COHERENCE) && !defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY)
 	/* Flush the stack.  The top of stack was stored for us by
 	 * arch_cohere_stacks().  It can be NULL for a dummy thread.
 	 */
+	rsync
 	rsr a0, ZSR_FLUSH
 	beqz a0, noflush
 	mov a3, a1
@@ -282,21 +331,6 @@ noflush:
 	l32i a3, a2, ___xtensa_irq_bsa_t_a3_OFFSET
 	s32i a1, a3, 0
 
-#ifdef CONFIG_USERSPACE
-	/* Switch page tables */
-	rsr a6, ZSR_CPU
-	l32i a6, a6, ___cpu_t_current_OFFSET
-#ifdef CONFIG_XTENSA_MMU
-	call4 xtensa_swap_update_page_tables
-#endif
-#ifdef CONFIG_XTENSA_MPU
-	call4 xtensa_mpu_map_write
-#endif
-
-	l32i a2, a3, 0
-	l32i a2, a2, 0
-#endif
-
 	/* Switch stack pointer and restore.  The jump to
 	 * _restore_context does not return as such, but we arrange
 	 * for the restored "next" address to be immediately after for
diff --git a/arch/xtensa/include/kernel_arch_func.h b/arch/xtensa/include/kernel_arch_func.h
index 5e735dedfff..8e0641f9d4b 100644
--- a/arch/xtensa/include/kernel_arch_func.h
+++ b/arch/xtensa/include/kernel_arch_func.h
@@ -39,23 +39,119 @@ static ALWAYS_INLINE void arch_switch(void *switch_to, void **switched_from)
 }
 
 #ifdef CONFIG_KERNEL_COHERENCE
+/**
+ * @brief Invalidate cache between two stack addresses.
+ *
+ * This invalidates the cache lines between two stack addresses,
+ * beginning with the cache line including the start address, up to
+ * but not including the cache line containing the end address.
+ * Not invalidating the last cache line is due to the usage in
+ * arch_cohere_stacks() where it invalidates the unused portion of
+ * stack. If the stack pointer happens to be in the middle of
+ * a cache line, the cache line containing the stack pointer
+ * address will be flushed, and then immediately invalidated.
+ * If we are swapping back into the same thread (e.g. after
+ * handling interrupt), that cache line, being invalidated, needs
+ * to be retrieved from main memory. This creates unnecessary
+ * data move between main memory and cache.
+ *
+ * @param s_addr Starting address of memory region to have cache invalidated.
+ * @param e_addr Ending address of memory region to have cache invalidated.
+ */
+static ALWAYS_INLINE void xtensa_cohere_stacks_cache_invd(size_t s_addr, size_t e_addr)
+{
+	const size_t first = ROUND_DOWN(s_addr, XCHAL_DCACHE_LINESIZE);
+	const size_t last = ROUND_DOWN(e_addr, XCHAL_DCACHE_LINESIZE);
+	size_t line;
+
+	for (line = first; line < last; line += XCHAL_DCACHE_LINESIZE) {
+		__asm__ volatile("dhi %0, 0" :: "r"(line));
+	}
+}
+
+/**
+ * @brief Flush cache between two stack addresses.
+ *
+ * This flushes the cache lines between two stack addresses,
+ * beginning with the cache line including the start address,
+ * and ending with the cache line including the end address.
+ * Note that, contrary to xtensa_cohere_stacks_cache_invd(),
+ * the last cache line will be flushed instead of being
+ * ignored.
+ *
+ * @param s_addr Starting address of memory region to have cache invalidated.
+ * @param e_addr Ending address of memory region to have cache invalidated.
+ */
+static ALWAYS_INLINE void xtensa_cohere_stacks_cache_flush(size_t s_addr, size_t e_addr)
+{
+	const size_t first = ROUND_DOWN(s_addr, XCHAL_DCACHE_LINESIZE);
+	const size_t last = ROUND_UP(e_addr, XCHAL_DCACHE_LINESIZE);
+	size_t line;
+
+	for (line = first; line < last; line += XCHAL_DCACHE_LINESIZE) {
+		__asm__ volatile("dhwb %0, 0" :: "r"(line));
+	}
+}
+
+/**
+ * @brief Flush and invalidate cache between two stack addresses.
+ *
+ * This flushes the cache lines between two stack addresses,
+ * beginning with the cache line including the start address,
+ * and ending with the cache line including the end address.
+ * Note that, contrary to xtensa_cohere_stacks_cache_invd(),
+ * the last cache line will be flushed and invalidated instead
+ * of being ignored.
+ *
+ * @param s_addr Starting address of memory region to have cache manipulated.
+ * @param e_addr Ending address of memory region to have cache manipulated.
+ */
+static ALWAYS_INLINE void xtensa_cohere_stacks_cache_flush_invd(size_t s_addr, size_t e_addr)
+{
+	const size_t first = ROUND_DOWN(s_addr, XCHAL_DCACHE_LINESIZE);
+	const size_t last = ROUND_UP(e_addr, XCHAL_DCACHE_LINESIZE);
+	size_t line;
+
+	for (line = first; line < last; line += XCHAL_DCACHE_LINESIZE) {
+		__asm__ volatile("dhwbi %0, 0" :: "r"(line));
+	}
+}
+
 static ALWAYS_INLINE void arch_cohere_stacks(struct k_thread *old_thread,
 					     void *old_switch_handle,
 					     struct k_thread *new_thread)
 {
+#ifdef CONFIG_SCHED_CPU_MASK_PIN_ONLY
+	ARG_UNUSED(old_thread);
+	ARG_UNUSED(old_switch_handle);
+	ARG_UNUSED(new_thread);
+
+	/* This kconfig option ensures that a living thread will never
+	 * be executed in a different CPU so we can safely return without
+	 * invalidate and/or flush threads cache.
+	 */
+	return;
+#endif /* CONFIG_SCHED_CPU_MASK_PIN_ONLY */
+
+#if !defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY)
 	int32_t curr_cpu = _current_cpu->id;
 
 	size_t ostack = old_thread->stack_info.start;
-	size_t osz    = old_thread->stack_info.size;
+	size_t oend   = ostack + old_thread->stack_info.size;
 	size_t osp    = (size_t) old_switch_handle;
 
 	size_t nstack = new_thread->stack_info.start;
-	size_t nsz    = new_thread->stack_info.size;
+	size_t nend   = nstack + new_thread->stack_info.size;
 	size_t nsp    = (size_t) new_thread->switch_handle;
 
-	int zero = 0;
+	uint32_t flush_end = 0;
+
+#ifdef CONFIG_USERSPACE
+	/* End of old_thread privileged stack. */
+	void *o_psp_end = old_thread->arch.psp;
+#endif
 
-	__asm__ volatile("wsr %0, " ZSR_FLUSH_STR :: "r"(zero));
+	__asm__ volatile("wsr %0, " ZSR_FLUSH_STR :: "r"(flush_end));
 
 	if (old_switch_handle != NULL) {
 		int32_t a0save;
@@ -66,14 +162,6 @@ static ALWAYS_INLINE void arch_cohere_stacks(struct k_thread *old_thread,
 				 : "=r"(a0save));
 	}
 
-	/* The following option ensures that a living thread will never
-	 * be executed in a different CPU so we can safely return without
-	 * invalidate and/or flush threads cache.
-	 */
-	if (IS_ENABLED(CONFIG_SCHED_CPU_MASK_PIN_ONLY)) {
-		return;
-	}
-
 	/* The "live" area (the region between the switch handle,
 	 * which is the stack pointer, and the top of the stack
 	 * memory) of the inbound stack needs to be invalidated if we
@@ -88,7 +176,7 @@ static ALWAYS_INLINE void arch_cohere_stacks(struct k_thread *old_thread,
 	 * automatically overwritten as needed.
 	 */
 	if (curr_cpu != new_thread->arch.last_cpu) {
-		sys_cache_data_invd_range((void *)nsp, (nstack + nsz) - nsp);
+		xtensa_cohere_stacks_cache_invd(nsp, nend);
 	}
 	old_thread->arch.last_cpu = curr_cpu;
 
@@ -116,8 +204,13 @@ static ALWAYS_INLINE void arch_cohere_stacks(struct k_thread *old_thread,
 	 * to the stack top stashed in a special register.
 	 */
 	if (old_switch_handle != NULL) {
-		sys_cache_data_flush_range((void *)osp, (ostack + osz) - osp);
-		sys_cache_data_invd_range((void *)ostack, osp - ostack);
+#ifdef CONFIG_USERSPACE
+		if (o_psp_end == NULL)
+#endif
+		{
+			xtensa_cohere_stacks_cache_flush(osp, oend);
+			xtensa_cohere_stacks_cache_invd(ostack, osp);
+		}
 	} else {
 		/* When in a switch, our current stack is the outbound
 		 * stack.  Flush the single line containing the stack
@@ -128,13 +221,58 @@ static ALWAYS_INLINE void arch_cohere_stacks(struct k_thread *old_thread,
 		 */
 		__asm__ volatile("mov %0, a1" : "=r"(osp));
 		osp -= 16;
-		sys_cache_data_flush_range((void *)osp, 1);
-		sys_cache_data_invd_range((void *)ostack, osp - ostack);
+		xtensa_cohere_stacks_cache_flush(osp, osp + 16);
 
-		uint32_t end = ostack + osz;
+#ifdef CONFIG_USERSPACE
+		if (o_psp_end == NULL)
+#endif
+		{
+			xtensa_cohere_stacks_cache_invd(ostack, osp);
 
-		__asm__ volatile("wsr %0, " ZSR_FLUSH_STR :: "r"(end));
+			flush_end = oend;
+		}
 	}
+
+#ifdef CONFIG_USERSPACE
+	/* User threads need a bit more processing due to having
+	 * privileged stack for handling syscalls. The privileged
+	 * stack always immediately precedes the thread stack.
+	 *
+	 * Note that, with userspace enabled, we need to swap
+	 * page table during context switch via function calls.
+	 * This means that the stack is being actively used
+	 * unlike the non-userspace case mentioned above.
+	 * Therefore we need to set ZSR_FLUSH_STR to make sure
+	 * we flush the cached data in the stack.
+	 */
+	if (o_psp_end != NULL) {
+		/* Start of old_thread privileged stack.
+		 *
+		 * struct xtensa_thread_stack_header wholly contains
+		 * a array for the privileged stack, so we can use
+		 * its size to calculate where the start is.
+		 */
+		size_t o_psp_start = (size_t)o_psp_end - sizeof(struct xtensa_thread_stack_header);
+
+		if ((osp >= ostack) && (osp < oend)) {
+			/* osp in user stack. */
+			xtensa_cohere_stacks_cache_invd(o_psp_start, osp);
+
+			flush_end = oend;
+		} else if ((osp >= o_psp_start) && (osp < ostack)) {
+			/* osp in privileged stack. */
+			xtensa_cohere_stacks_cache_flush(ostack, oend);
+			xtensa_cohere_stacks_cache_invd(o_psp_start, osp);
+
+			flush_end = (size_t)old_thread->arch.psp;
+		}
+	}
+#endif /* CONFIG_USERSPACE */
+
+	flush_end = ROUND_DOWN(flush_end, XCHAL_DCACHE_LINESIZE);
+	__asm__ volatile("wsr %0, " ZSR_FLUSH_STR :: "r"(flush_end));
+
+#endif /* !CONFIG_SCHED_CPU_MASK_PIN_ONLY */
 }
 #endif
 
diff --git a/arch/xtensa/include/offsets_short_arch.h b/arch/xtensa/include/offsets_short_arch.h
index f19750dc0ac..80ece2b1dee 100644
--- a/arch/xtensa/include/offsets_short_arch.h
+++ b/arch/xtensa/include/offsets_short_arch.h
@@ -12,8 +12,33 @@
 #define _thread_offset_to_psp \
 	(___thread_t_arch_OFFSET + ___thread_arch_t_psp_OFFSET)
 
+#define _thread_offset_to_return_ps \
+	(___thread_t_arch_OFFSET + ___thread_arch_t_return_ps_OFFSET)
+
 #define _thread_offset_to_ptables \
 	(___thread_t_arch_OFFSET + ___thread_arch_t_ptables_OFFSET)
+
+#define _thread_offset_to_mem_domain \
+	(___thread_t_mem_domain_info_OFFSET + ___mem_domain_info_t_mem_domain_OFFSET)
+
+#define _k_mem_domain_offset_to_arch_reg_asid \
+	(__k_mem_domain_t_arch_OFFSET + __arch_mem_domain_t_reg_asid_OFFSET)
+
+#define _k_mem_domain_offset_to_arch_reg_ptevaddr \
+	(__k_mem_domain_t_arch_OFFSET + __arch_mem_domain_t_reg_ptevaddr_OFFSET)
+
+#define _k_mem_domain_offset_to_arch_reg_ptepin_as \
+	(__k_mem_domain_t_arch_OFFSET + __arch_mem_domain_t_reg_ptepin_as_OFFSET)
+
+#define _k_mem_domain_offset_to_arch_reg_ptepin_at \
+	(__k_mem_domain_t_arch_OFFSET + __arch_mem_domain_t_reg_ptepin_at_OFFSET)
+
+#define _k_mem_domain_offset_to_arch_reg_vecpin_as \
+	(__k_mem_domain_t_arch_OFFSET + __arch_mem_domain_t_reg_vecpin_as_OFFSET)
+
+#define _k_mem_domain_offset_to_arch_reg_vecpin_at \
+	(__k_mem_domain_t_arch_OFFSET + __arch_mem_domain_t_reg_vecpin_at_OFFSET)
+
 #endif /* CONFIG_USERSPACE */
 
 #endif /* ZEPHYR_ARCH_XTENSA_INCLUDE_OFFSETS_SHORT_ARCH_H_ */
diff --git a/arch/xtensa/include/xtensa_asm2_context.h b/arch/xtensa/include/xtensa_asm2_context.h
index d5593d7adbc..ac13a611c67 100644
--- a/arch/xtensa/include/xtensa_asm2_context.h
+++ b/arch/xtensa/include/xtensa_asm2_context.h
@@ -80,6 +80,68 @@
 #include <stdint.h>
 #include <zephyr/toolchain.h>
 
+/* Stack needs to aligned on 16-bytes as mentioned on Xtensa ISA.
+ * So we pad _xtensa_irq_bsa_t to achieve that. The followings
+ * are see how much space is taken depending on features enabled.
+ */
+
+#if XCHAL_HAVE_FP && defined(CONFIG_CPU_HAS_FPU) && defined(CONFIG_FPU_SHARING)
+# define _BSA_PADDING_FPU		(sizeof(uintptr_t) * 18U)
+#else
+# define _BSA_PADDING_FPU		(0)
+#endif
+
+#if defined(CONFIG_XTENSA_HIFI_SHARING)
+# define _BSA_PADDING_HIFI		(XCHAL_CP1_SA_SIZE + XCHAL_CP1_SA_ALIGN)
+#else
+# define _BSA_PADDING_HIFI		(0)
+#endif
+
+#if XCHAL_HAVE_THREADPTR
+# define _BSA_PADDING_THREADPTR		(sizeof(uintptr_t))
+#else
+# define _BSA_PADDING_THREADPTR		(0)
+#endif
+
+#if XCHAL_HAVE_S32C1I
+# define _BSA_PADDING_S32C1I		(sizeof(uintptr_t))
+#else
+# define _BSA_PADDING_S32C1I		(0)
+#endif
+
+#if XCHAL_HAVE_LOOPS
+# define _BSA_PADDING_LOOPS		(sizeof(uintptr_t) * 3U)
+#else
+# define _BSA_PADDING_LOOPS		(0)
+#endif
+
+/* Must have fields regardless of features. */
+#define _BSA_PADDING_COMMON		(sizeof(uintptr_t) * 12U)
+
+/* Raw size by adding up all the above. */
+#define _BSA_PADDING_BASE_SIZE		\
+	(_BSA_PADDING_FPU + \
+	 _BSA_PADDING_HIFI + \
+	 _BSA_PADDING_THREADPTR + \
+	 _BSA_PADDING_S32C1I + \
+	 _BSA_PADDING_LOOPS + \
+	 _BSA_PADDING_COMMON)
+
+/* Each stack frame always has a pointer to BSA so we add
+ * that (+4) to the BSA size before padding the BSA to have
+ * size aligned on 16 bytes. Each group of high registers to
+ * be saved (totally 3 groups) consists of 4 registers which
+ * are 16 bytes already. So each type of stack frame
+ * (A[3, 7, 11, 15]) do not need any further padding as long
+ * as the BSA struct is of correct size.
+ */
+#define _BSA_PADDING_PADDED_SIZE	\
+	((((_BSA_PADDING_BASE_SIZE + 4) + 15) / 16 * 16) - 4)
+
+/* How many extra bytes needed. */
+#define _BSA_PADDING_NEEDED		\
+	(_BSA_PADDING_PADDED_SIZE - _BSA_PADDING_BASE_SIZE)
+
 /**
  * Base Save Area (BSA) during interrupt.
  *
@@ -147,6 +209,8 @@ struct xtensa_irq_base_save_area {
 	uintptr_t a2;
 	uintptr_t a3;
 
+	uintptr_t padding[_BSA_PADDING_NEEDED / sizeof(uintptr_t)];
+
 	uintptr_t caller_a0;
 	uintptr_t caller_a1;
 	uintptr_t caller_a2;
@@ -155,6 +219,16 @@ struct xtensa_irq_base_save_area {
 
 typedef struct xtensa_irq_base_save_area _xtensa_irq_bsa_t;
 
+#undef _BSA_PADDING_NEEDED
+#undef _BSA_PADDING_PADDED_SIZE
+#undef _BSA_PADDING_BASE_SIZE
+#undef _BSA_PADDING_COMMON
+#undef _BSA_PADDING_LOOPS
+#undef _BSA_PADDING_S32C1I
+#undef _BSA_PADDING_THREADPTR
+#undef _BSA_PADDING_HIFI
+#undef _BSA_PADDING_FPU
+
 /**
  * Raw interrupt stack frame.
  *
diff --git a/arch/xtensa/include/xtensa_asm2_s.h b/arch/xtensa/include/xtensa_asm2_s.h
index 150df82c35c..198f04f80e8 100644
--- a/arch/xtensa/include/xtensa_asm2_s.h
+++ b/arch/xtensa/include/xtensa_asm2_s.h
@@ -11,6 +11,7 @@
 #include "xtensa_asm2_context.h"
 
 #include <zephyr/offsets.h>
+#include <offsets_short.h>
 
 /* Assembler header!  This file contains macros designed to be included
  * only by the assembler.
@@ -156,134 +157,111 @@
  * ODD_REG_SAVE
  *
  * Stashes the oddball shift/loop context registers in the base save
- * area pointed to by the current stack pointer.  On exit, A0 will
- * have been modified but A2/A3 have not, and the shift/loop
- * instructions can be used freely (though note loops don't work in
- * exceptions for other reasons!).
+ * area pointed to by the register specified by parameter BSA_PTR.
+ * On exit, the scratch register specified by parameter SCRATCH_REG
+ * will have been modified, and the shift/loop instructions can be
+ * used freely (though note loops don't work in exceptions for other
+ * reasons!).
  *
  * Does not populate or modify the PS/PC save locations.
  */
-.macro ODD_REG_SAVE
-	rsr.sar a0
-	s32i a0, a1, ___xtensa_irq_bsa_t_sar_OFFSET
+.macro ODD_REG_SAVE SCRATCH_REG, BSA_PTR
+	rsr.sar \SCRATCH_REG
+	s32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_sar_OFFSET
 #if XCHAL_HAVE_LOOPS
-	rsr.lbeg a0
-	s32i a0, a1, ___xtensa_irq_bsa_t_lbeg_OFFSET
-	rsr.lend a0
-	s32i a0, a1, ___xtensa_irq_bsa_t_lend_OFFSET
-	rsr.lcount a0
-	s32i a0, a1, ___xtensa_irq_bsa_t_lcount_OFFSET
+	rsr.lbeg \SCRATCH_REG
+	s32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_lbeg_OFFSET
+	rsr.lend \SCRATCH_REG
+	s32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_lend_OFFSET
+	rsr.lcount \SCRATCH_REG
+	s32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_lcount_OFFSET
 #endif
-	rsr.exccause a0
-	s32i a0, a1, ___xtensa_irq_bsa_t_exccause_OFFSET
+	rsr.exccause \SCRATCH_REG
+	s32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_exccause_OFFSET
 #if XCHAL_HAVE_S32C1I
-	rsr.scompare1 a0
-	s32i a0, a1, ___xtensa_irq_bsa_t_scompare1_OFFSET
+	rsr.scompare1 \SCRATCH_REG
+	s32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_scompare1_OFFSET
 #endif
 #if XCHAL_HAVE_THREADPTR && \
 	(defined(CONFIG_USERSPACE) || defined(CONFIG_THREAD_LOCAL_STORAGE))
-	rur.THREADPTR a0
-	s32i a0, a1, ___xtensa_irq_bsa_t_threadptr_OFFSET
-#endif
-#if XCHAL_HAVE_FP && defined(CONFIG_CPU_HAS_FPU) && defined(CONFIG_FPU_SHARING)
-	FPU_REG_SAVE
+	rur.THREADPTR \SCRATCH_REG
+	s32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_threadptr_OFFSET
 #endif
 
 .endm
 
-#ifdef CONFIG_XTENSA_MMU
 /*
- * CALC_PTEVADDR_BASE
+ * ODD_REG_RESTORE
  *
- * This calculates the virtual address of the first PTE page
- * (PTEVADDR base, the one mapping 0x00000000) so that we can
- * use this to obtain the virtual address of the PTE page we are
- * interested in. This can be obtained via
- * (1 << CONFIG_XTENSA_MMU_PTEVADDR_SHIFT).
+ * Restores the oddball shift/loop context registers in the base save
+ * area pointed to by the register specified by parameter BSA_PTR.
+ * On exit, the scratch register specified by parameter SCRATCH_REG
+ * will have been modified.
  *
- * Note that this is done this way is to avoid any TLB
- * miss if we are to use l32r to load the PTEVADDR base.
- * If the page containing the PTEVADDR base address is
- * not in TLB, we will need to handle the TLB miss which
- * we are trying to avoid here.
- *
- * @param ADDR_REG Register to store the calculated
- *                 PTEVADDR base address.
- *
- * @note The content of ADDR_REG will be modified.
- *       Save and restore it around this macro usage.
+ * Does not restore the PS/PC save locations.
  */
-.macro CALC_PTEVADDR_BASE ADDR_REG
-	movi \ADDR_REG, 1
-	slli \ADDR_REG, \ADDR_REG, CONFIG_XTENSA_MMU_PTEVADDR_SHIFT
+.macro ODD_REG_RESTORE SCRATCH_REG, BSA_PTR
+	l32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_sar_OFFSET
+	wsr.sar \SCRATCH_REG
+#if XCHAL_HAVE_LOOPS
+	l32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_lbeg_OFFSET
+	wsr.lbeg \SCRATCH_REG
+	l32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_lend_OFFSET
+	wsr.lend \SCRATCH_REG
+	l32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_lcount_OFFSET
+	wsr.lcount \SCRATCH_REG
+#endif
+	l32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_exccause_OFFSET
+	wsr.exccause \SCRATCH_REG
+#if XCHAL_HAVE_S32C1I
+	l32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_scompare1_OFFSET
+	wsr.scompare1 \SCRATCH_REG
+#endif
+#if XCHAL_HAVE_THREADPTR && \
+	(defined(CONFIG_USERSPACE) || defined(CONFIG_THREAD_LOCAL_STORAGE))
+	l32i \SCRATCH_REG, \BSA_PTR, ___xtensa_irq_bsa_t_threadptr_OFFSET
+	wur.THREADPTR \SCRATCH_REG
+#endif
+
 .endm
 
+#if defined(CONFIG_XTENSA_MMU) && defined(CONFIG_USERSPACE)
 /*
- * PRELOAD_PTEVADDR
+ * SWAP_PAGE_TABLE
  *
- * This preloads the page table entries for a 4MB region to avoid TLB
- * misses. This 4MB region is mapped via a page (4KB) of page table
- * entries (PTE). Each entry is 4 bytes mapping a 4KB region. Each page,
- * then, has 1024 entries mapping a 4MB region. Filling TLB entries is
- * automatically done via hardware, as long as the PTE page associated
- * with a particular address is also in TLB. If the PTE page is not in
- * TLB, an exception will be raised that must be handled. This TLB miss
- * is problematic when we are in the middle of dealing with another
- * exception or handling an interrupt. So we need to put the PTE page
- * into TLB by simply do a load operation.
+ * This swaps the page tables by using the pre-computed register values
+ * inside the architecture-specific memory domain struct.
  *
- * @param ADDR_REG Register containing the target address
- * @param PTEVADDR_BASE_REG Register containing the PTEVADDR base
+ * THREAD_PTR_REG is input containing pointer to the incoming thread struct.
+ * SC1_REG and SC2_REG are scratch registers.
  *
- * @note Both the content of ADDR_REG will be modified.
- *       Save and restore it around this macro usage.
+ * Note that all THREAD_PTR_REG, SC1_REG and SC2_REG are all clobbered.
+ * Restore the thread pointer after this if necessary.
  */
-.macro PRELOAD_PTEVADDR ADDR_REG, PTEVADDR_BASE_REG
-	/*
-	 * Calculate the offset to first PTE page of all memory.
-	 *
-	 * Every page (4KB) of page table entries contains
-	 * 1024 entires (as each entry is 4 bytes). Each entry
-	 * maps one 4KB page. So one page of entries maps 4MB of
-	 * memory.
-	 *
-	 * 1. We need to find the virtual address of the PTE page
-	 *    having the page table entry mapping the address in
-	 *    register ADDR_REG. To do this, we first need to find
-	 *    the offset of this PTE page from the first PTE page
-	 *    (the one mapping memory 0x00000000):
-	 *    a. Find the beginning address of the 4KB page
-	 *       containing address in ADDR_REG. This can simply
-	 *       be done by discarding 11 bits (or shifting right
-	 *	 and then left 12 bits).
-	 *    b. Since each PTE page contains 1024 entries,
-	 *	 we divide the address obtained in step (a) by
-	 *       further dividing it by 1024 (shifting right and
-	 *       then left 10 bits) to obtain the offset of
-	 *       the PTE page.
-	 *
-	 *    Step (a) and (b) can be obtained together so that
-	 *    we can shift right 22 bits, and then shift left
-	 *    12 bits.
-	 *
-	 * 2. Once we have combine the results from step (1) and
-	 *    PTEVADDR_BASE_REG to get the virtual address of
-	 *    the PTE page.
-	 *
-	 * 3. Do a l32i to force the PTE page to be in TLB.
-	 */
+.macro SWAP_PAGE_TABLE THREAD_PTR_REG, SC1_REG, SC2_REG
+	l32i \THREAD_PTR_REG, \THREAD_PTR_REG, _thread_offset_to_mem_domain
+
+	j _swap_page_table_\@
+
+.align 16
+_swap_page_table_\@:
+	l32i \SC1_REG, \THREAD_PTR_REG, _k_mem_domain_offset_to_arch_reg_ptevaddr
+	l32i \SC2_REG, \THREAD_PTR_REG, _k_mem_domain_offset_to_arch_reg_asid
+	wsr \SC1_REG, PTEVADDR
+	wsr \SC2_REG, RASID
 
-	/* Step 1 */
-	srli \ADDR_REG, \ADDR_REG, 22
-	slli \ADDR_REG, \ADDR_REG, 12
+	l32i \SC1_REG, \THREAD_PTR_REG, _k_mem_domain_offset_to_arch_reg_ptepin_as
+	l32i \SC2_REG, \THREAD_PTR_REG, _k_mem_domain_offset_to_arch_reg_ptepin_at
+	wdtlb \SC2_REG, \SC1_REG
 
-	/* Step 2 */
-	add \ADDR_REG, \ADDR_REG, \PTEVADDR_BASE_REG
+	l32i \SC1_REG, \THREAD_PTR_REG, _k_mem_domain_offset_to_arch_reg_vecpin_as
+	l32i \SC2_REG, \THREAD_PTR_REG, _k_mem_domain_offset_to_arch_reg_vecpin_at
+	wdtlb \SC2_REG, \SC1_REG
 
-	/* Step 3 */
-	l32i \ADDR_REG, \ADDR_REG, 0
+	isync
 .endm
-#endif /* CONFIG_XTENSA_MMU */
+
+#endif /* CONFIG_XTENSA_MMU && CONFIG_USERSPACE */
 
 /*
  * CROSS_STACK_CALL
@@ -353,16 +331,26 @@
  * the context save handle in A1 as it's first argument.
  */
 .macro CROSS_STACK_CALL
-	mov a6, a3		/* place "new sp" in the next frame's A2 */
-	mov a10, a1             /* pass "context handle" in 2nd frame's A2 */
-	mov a3, a1		/* stash it locally in A3 too */
-	mov a11, a2		/* handler in 2nd frame's A3, next frame's A7 */
+	/* Since accessing A4-A11 may trigger window overflows so
+	 * we need to setup A0 and A1 correctly before putting
+	 * the function arguments for the next two callx4 into
+	 * A6, A10 and A11. So stach the "context handle" into
+	 * ZSR_EPC, which is usable for now similar to ZSR_EPS.
+	 */
+	wsr.ZSR_EPC a1
+	rsync
 
 	/* Recover the interrupted SP from the BSA */
 	l32i a1, a1, 0
 	l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
 	addi a1, a1, ___xtensa_irq_bsa_t_SIZEOF
 
+	mov a6, a3		/* place "new sp" in the next frame's A2 */
+
+	rsr.ZSR_EPC a3		/* restore saved "context handle" in A3 */
+	mov a10, a3             /* pass "context handle" in 2nd frame's A2 */
+	mov a11, a2		/* handler in 2nd frame's A3, next frame's A7 */
+
 	call4 _xstack_call0_\@
 	mov a1, a3		/* restore original SP */
 	mov a2, a6		/* copy return value */
@@ -377,16 +365,46 @@ _xstack_call0_\@:
 	mov a1, a2
 	rsr.ZSR_EPS a2
 	wsr.ps a2
-	call4 _xstack_call1_\@
+
+#ifdef CONFIG_USERSPACE
+	/* Save "context handle" in A3 as we need it to determine
+	 * if we need to swap page table later.
+	 */
+	mov a3, a6
+#endif
+
+	callx4 a7		/* call handler */
 	mov a2, a6		/* copy return value */
-	retw
-.align 4
-_xstack_call1_\@:
-	/* Remember the handler is going to do our ENTRY, so the
-	 * handler pointer is still in A6 (not A2) even though this is
-	 * after the second CALL4.
+
+#ifdef CONFIG_USERSPACE
+	rsil a6, XCHAL_NUM_INTLEVELS
+
+	/* If "next" handle to be restored is the same as
+	 * the current handle, there is no need to swap page
+	 * tables or MPU entries since we will return to
+	 * the same thread that was interrupted.
+	 */
+	beq a2, a3, _xstack_skip_table_swap_\@
+
+	/* Need to switch page tables because the "next" handle
+	 * returned above is not the same handle as we started
+	 * with. This means we are being restored to another
+	 * thread.
 	 */
-	jx a7
+	rsr a6, ZSR_CPU
+	l32i a6, a6, ___cpu_t_current_OFFSET
+
+#ifdef CONFIG_XTENSA_MMU
+	SWAP_PAGE_TABLE a6, a3, a7
+#endif
+#ifdef CONFIG_XTENSA_MPU
+	call4 xtensa_mpu_map_write
+#endif
+
+_xstack_skip_table_swap_\@:
+#endif /* CONFIG_USERSPACE */
+
+	retw
 _xstack_returned_\@:
 .endm
 
@@ -409,7 +427,11 @@ _xstack_returned_\@:
 	 */
 	s32i a2, a1, ___xtensa_irq_bsa_t_scratch_OFFSET
 
-	ODD_REG_SAVE
+	ODD_REG_SAVE a0, a1
+
+#if XCHAL_HAVE_FP && defined(CONFIG_CPU_HAS_FPU) && defined(CONFIG_FPU_SHARING)
+	FPU_REG_SAVE
+#endif
 
 #if defined(CONFIG_XTENSA_HIFI_SHARING)
 	call0 _xtensa_hifi_save    /* Save HiFi registers */
@@ -430,6 +452,23 @@ _xstack_returned_\@:
 	wur.THREADPTR a0
 #endif /* XCHAL_HAVE_THREADPTR && CONFIG_USERSPACE */
 
+	/* Setting up the cross stack call below has states where the
+	 * resulting frames are invalid/non-reentrant, so we can't
+	 * allow nested interrupts.  But we do need EXCM unmasked, as
+	 * we use CALL/ENTRY instructions in the process and need to
+	 * handle exceptions to spill caller/interruptee frames.  Use
+	 * PS.INTLEVEL at maximum to mask all interrupts and stash the
+	 * current value in our designated EPS register (which is
+	 * guaranteed unused across the call)
+	 */
+	rsil a0, 0xf
+
+	/* Since we are unmasking EXCM, we need to set RING bits to kernel
+	 * mode, otherwise we won't be able to run the exception handler in C.
+	 */
+	movi a3, ~(PS_EXCM_MASK) & ~(PS_RING_MASK)
+	and a0, a0, a3
+
 #ifdef CONFIG_XTENSA_INTERRUPT_NONPREEMPTABLE
 
 	/* Setting the interrupt mask to the max non-debug level
@@ -437,12 +476,11 @@ _xstack_returned_\@:
 	 * high level interrupts until processing of that lower level
 	 * interrupt has completed.
 	 */
-	rsr.ps a0
 	movi a3, ~(PS_INTLEVEL_MASK)
 	and a0, a0, a3
 	movi a3, PS_INTLEVEL(ZSR_RFI_LEVEL)
 	or a0, a0, a3
-	wsr.ps a0
+	wsr.ZSR_EPS a0
 
 #else
 
@@ -458,35 +496,20 @@ _xstack_returned_\@:
 	 * argument and expand two versions of this handler.  An
 	 * optimization FIXME, I guess.
 	 */
-	rsr.ps a0
 	movi a3, PS_INTLEVEL_MASK
-	and a0, a0, a3
-	bnez a0, _not_l1
-	rsr.ps a0
+	and a3, a0, a3
+	bnez a3, _not_l1
+
+	/* interrupt masking is zero, so no need to zero it before OR-ing. */
 	movi a3, PS_INTLEVEL(1)
 	or a0, a0, a3
-	wsr.ps a0
 
 _not_l1:
+	wsr.ZSR_EPS a0
 #endif /* CONFIG_XTENSA_INTERRUPT_NONPREEMPTABLE */
 
-	/* Setting up the cross stack call below has states where the
-	 * resulting frames are invalid/non-reentrant, so we can't
-	 * allow nested interrupts.  But we do need EXCM unmasked, as
-	 * we use CALL/ENTRY instructions in the process and need to
-	 * handle exceptions to spill caller/interruptee frames.  Use
-	 * PS.INTLEVEL at maximum to mask all interrupts and stash the
-	 * current value in our designated EPS register (which is
-	 * guaranteed unused across the call)
-	 */
-	rsil a0, 0xf
-
-	/* Since we are unmasking EXCM, we need to set RING bits to kernel
-	 * mode, otherwise we won't be able to run the exception handler in C.
-	 */
-	movi a3, ~(PS_EXCM_MASK) & ~(PS_RING_MASK)
-	and a0, a0, a3
-	wsr.ZSR_EPS a0
+	movi a3, PS_INTLEVEL(0xf)
+	or a0, a0, a3
 	wsr.ps a0
 	rsync
 
@@ -536,52 +559,48 @@ _do_call_\@:
 	 */
 	beq a6, a1, _restore_\@
 
-#ifndef CONFIG_USERSPACE
+#if !defined(CONFIG_KERNEL_COHERENCE) || \
+    (defined(CONFIG_KERNEL_COHERENCE) && defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY))
 	l32i a1, a1, 0
 	l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
 	addi a1, a1, ___xtensa_irq_bsa_t_SIZEOF
-#ifndef CONFIG_KERNEL_COHERENCE
+
 	/* When using coherence, the registers of the interrupted
 	 * context got spilled upstream in arch_cohere_stacks()
 	 */
 	SPILL_ALL_WINDOWS
 #endif
 
-	/* Restore A1 stack pointer from "next" handle. */
-	mov a1, a6
-#else
-	/* With userspace, we cannot simply restore A1 stack pointer
-	 * at this pointer because we need to swap page tables to
-	 * the incoming thread, and we do not want to call that
-	 * function with thread's stack. So we stash the new stack
-	 * pointer into A2 first, then move it to A1 after we have
-	 * swapped the page table.
-	 */
-	mov a2, a6
+#if defined(CONFIG_KERNEL_COHERENCE) && \
+	defined(CONFIG_USERSPACE) && \
+	!defined(CONFIG_SCHED_CPU_MASK_PIN_ONLY)
 
-	/* Need to switch page tables because the "next" handle
-	 * returned above is not the same handle as we started
-	 * with. This means we are being restored to another
-	 * thread.
+	/* With userspace enabled, we need to swap page table via function calls
+	 * above after returning from syscall handler above in CROSS_STACK_CALL.
+	 * This means that the stack is being actively used, and so we need to
+	 * flush the cached data in stack.
 	 */
-	rsr a6, ZSR_CPU
-	l32i a6, a6, ___cpu_t_current_OFFSET
 
-#ifdef CONFIG_XTENSA_MMU
-	call4 xtensa_swap_update_page_tables
-#endif
-#ifdef CONFIG_XTENSA_MPU
-	call4 xtensa_mpu_map_write
-#endif
-	l32i a1, a1, 0
-	l32i a0, a1, ___xtensa_irq_bsa_t_a0_OFFSET
-	addi a1, a1, ___xtensa_irq_bsa_t_SIZEOF
+	movi a2, 0
+	xsr.ZSR_FLUSH a2
+	beqz a2, _excint_noflush_\@
 
-	SPILL_ALL_WINDOWS
+	rsr.ZSR_CPU a3
+	l32i a3, a3, \NEST_OFF
+	bnez a3, _excint_noflush_\@
 
-	/* Moved stashed stack pointer to A1 to restore stack. */
-	mov a1, a2
-#endif
+	mov a3, a1
+
+_excint_flushloop_\@:
+	dhwb a3, 0
+	addi a3, a3, XCHAL_DCACHE_LINESIZE
+	blt a3, a2, _excint_flushloop_\@
+
+_excint_noflush_\@:
+#endif /* CONFIG_KERNEL_COHERENCE && CONFIG_USERSPACE && !CONFIG_SCHED_CPU_MASK_PIN_ONLY */
+
+	/* Restore A1 stack pointer from "next" handle. */
+	mov a1, a6
 
 _restore_\@:
 	j _restore_context
@@ -706,6 +725,25 @@ _Level\LVL\()Vector:
 	s32i a0, a1, ___xtensa_irq_bsa_t_ps_OFFSET
 .endif
 
+#ifdef CONFIG_USERSPACE
+	/* When restoring context via xtensa_switch and
+	 * returning from non-nested interrupts, we will be
+	 * using the stashed PS value in the thread struct
+	 * instead of the one in the thread stack. Both of
+	 * these scenarios will have nested value of 0.
+	 * So when nested value is zero, we store the PS
+	 * value into thread struct.
+	 */
+	rsr.ZSR_CPU a3
+	l32i a2, a3, ___cpu_t_nested_OFFSET
+	bnez a2, _excint_skip_ps_save_to_thread_\LVL
+
+	l32i a2, a3, ___cpu_t_current_OFFSET
+	s32i a0, a2, _thread_offset_to_return_ps
+
+_excint_skip_ps_save_to_thread_\LVL:
+#endif
+
 	rsr.epc\LVL a0
 	s32i a0, a1, ___xtensa_irq_bsa_t_pc_OFFSET
 
diff --git a/arch/xtensa/include/xtensa_mmu_priv.h b/arch/xtensa/include/xtensa_mmu_priv.h
index 608cbac9c46..b4491ff0bc3 100644
--- a/arch/xtensa/include/xtensa_mmu_priv.h
+++ b/arch/xtensa/include/xtensa_mmu_priv.h
@@ -14,6 +14,7 @@
 #include <xtensa/config/core-isa.h>
 #include <zephyr/toolchain.h>
 #include <zephyr/sys/util_macro.h>
+#include <zephyr/arch/xtensa/arch.h>
 
 /**
  * @defgroup xtensa_mmu_internal_apis Xtensa Memory Management Unit (MMU) Internal APIs
@@ -509,18 +510,22 @@ static inline void xtensa_dtlb_vaddr_invalidate(void *vaddr)
 
 /**
  * @brief Tell hardware to use a page table very first time after boot.
- *
- * @param l1_page Pointer to the page table to be used.
  */
-void xtensa_init_paging(uint32_t *l1_page);
+void xtensa_mmu_init_paging(void);
 
 /**
  * @brief Switch to a new page table.
  *
- * @param asid The ASID of the memory domain associated with the incoming page table.
- * @param l1_page Page table to be switched to.
+ * @param domain Architecture-specific memory domain data.
+ */
+void xtensa_mmu_set_paging(struct arch_mem_domain *domain);
+
+/**
+ * @brief Computer the necessary register values when changing page tables.
+ *
+ * @param domain Architecture-specific memory domain data.
  */
-void xtensa_set_paging(uint32_t asid, uint32_t *l1_page);
+void xtensa_mmu_compute_domain_regs(struct arch_mem_domain *domain);
 
 /**
  * @}
diff --git a/boards/01space/esp32c3_042_oled/doc/index.rst b/boards/01space/esp32c3_042_oled/doc/index.rst
index 29fcfc78615..801e8651cfa 100644
--- a/boards/01space/esp32c3_042_oled/doc/index.rst
+++ b/boards/01space/esp32c3_042_oled/doc/index.rst
@@ -34,31 +34,7 @@ It features:
 Supported Features
 ==================
 
-The 01space ESP32C3 0.42 OLED board configuration supports the following hardware features:
-
-+-----------+------------+------------------+
-| Interface | Controller | Driver/Component |
-+===========+============+==================+
-| PMP       | on-chip    | arch/riscv       |
-+-----------+------------+------------------+
-| INTMTRX   | on-chip    | intc_esp32c3     |
-+-----------+------------+------------------+
-| PINMUX    | on-chip    | pinctrl_esp32    |
-+-----------+------------+------------------+
-| USB UART  | on-chip    | serial_esp32_usb |
-+-----------+------------+------------------+
-| GPIO      | on-chip    | gpio_esp32       |
-+-----------+------------+------------------+
-| UART      | on-chip    | uart_esp32       |
-+-----------+------------+------------------+
-| I2C       | on-chip    | i2c_esp32        |
-+-----------+------------+------------------+
-| SPI       | on-chip    | spi_esp32_spim   |
-+-----------+------------+------------------+
-| RADIO     | on-chip    | Bluetooth        |
-+-----------+------------+------------------+
-| DISPLAY   | off-chip   | display          |
-+-----------+------------+------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -91,6 +67,8 @@ retrieve those files.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Standalone application
 ======================
 
diff --git a/boards/01space/esp32c3_042_oled/esp32c3_042_oled_defconfig b/boards/01space/esp32c3_042_oled/esp32c3_042_oled_defconfig
index ef633ce56a1..187793c76e8 100644
--- a/boards/01space/esp32c3_042_oled/esp32c3_042_oled_defconfig
+++ b/boards/01space/esp32c3_042_oled/esp32c3_042_oled_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/96boards/aerocore2/96b_aerocore2.yaml b/boards/96boards/aerocore2/96b_aerocore2.yaml
index 6e704190fdd..01b0b6502fc 100644
--- a/boards/96boards/aerocore2/96b_aerocore2.yaml
+++ b/boards/96boards/aerocore2/96b_aerocore2.yaml
@@ -9,7 +9,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - pwm
diff --git a/boards/96boards/argonkey/96b_argonkey.yaml b/boards/96boards/argonkey/96b_argonkey.yaml
index c0e086b60f2..272af0c82ff 100644
--- a/boards/96boards/argonkey/96b_argonkey.yaml
+++ b/boards/96boards/argonkey/96b_argonkey.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 256
 flash: 1024
 supported:
diff --git a/boards/96boards/avenger96/96b_avenger96.yaml b/boards/96boards/avenger96/96b_avenger96.yaml
index ef14d1b879d..83b5f6af343 100644
--- a/boards/96boards/avenger96/96b_avenger96.yaml
+++ b/boards/96boards/avenger96/96b_avenger96.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - shell
diff --git a/boards/96boards/carbon/96b_carbon_nrf51822.yaml b/boards/96boards/carbon/96b_carbon_nrf51822.yaml
index 135d5aa461b..daa4501a13f 100644
--- a/boards/96boards/carbon/96b_carbon_nrf51822.yaml
+++ b/boards/96boards/carbon/96b_carbon_nrf51822.yaml
@@ -7,7 +7,6 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - ble
 vendor: seeed
diff --git a/boards/96boards/carbon/96b_carbon_stm32f401xe.yaml b/boards/96boards/carbon/96b_carbon_stm32f401xe.yaml
index 4b0c56dc5a4..a0254053ca3 100644
--- a/boards/96boards/carbon/96b_carbon_stm32f401xe.yaml
+++ b/boards/96boards/carbon/96b_carbon_stm32f401xe.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - ble
diff --git a/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.yaml b/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.yaml
index 39f57323369..d214e696cad 100644
--- a/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.yaml
+++ b/boards/96boards/meerkat96/96b_meerkat96_mcimx7d_m4.yaml
@@ -13,7 +13,6 @@ flash: 32
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - shell
diff --git a/boards/96boards/neonkey/96b_neonkey.yaml b/boards/96boards/neonkey/96b_neonkey.yaml
index 614eca9d249..0afdd5a7181 100644
--- a/boards/96boards/neonkey/96b_neonkey.yaml
+++ b/boards/96boards/neonkey/96b_neonkey.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 512
 supported:
diff --git a/boards/96boards/nitrogen/96b_nitrogen.yaml b/boards/96boards/nitrogen/96b_nitrogen.yaml
index 12b1f6c73e1..43875e92ed9 100644
--- a/boards/96boards/nitrogen/96b_nitrogen.yaml
+++ b/boards/96boards/nitrogen/96b_nitrogen.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - ble
   - gpio
diff --git a/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.yaml b/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.yaml
index 160bb802380..ae6db8a8159 100644
--- a/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.yaml
+++ b/boards/96boards/stm32_sensor_mez/96b_stm32_sensor_mez.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - uart
   - gpio
diff --git a/boards/Kconfig b/boards/Kconfig
index 40e8e5006e1..71b3b9571ad 100644
--- a/boards/Kconfig
+++ b/boards/Kconfig
@@ -2,8 +2,7 @@
 
 config BOARD
 	string
-	# When using hw model v2, then the board is inherited from CMake.
-	default "$(BOARD)" if "$(HWM_SCHEME)" = "v2"
+	default "$(BOARD)"
 	help
 	  This option holds the name of the board and is used to locate the files
 	  related to the board in the source tree (under boards/).
@@ -53,7 +52,7 @@ config NET_DRIVERS
 	  When building for a qemu target then NET_DRIVERS will be default
 	  enabled to allow for easy use of SLIP or PPP
 
-rsource "Kconfig.$(HWM_SCHEME)"
+rsource "Kconfig.v2"
 
 # Parse shields references
 # Don't do it as a menuconfig, as shield selection is a CMake feature.
diff --git a/boards/Kconfig.v1 b/boards/Kconfig.v1
deleted file mode 100644
index c98bd27d2db..00000000000
--- a/boards/Kconfig.v1
+++ /dev/null
@@ -1,14 +0,0 @@
-# Copyright (c) 2022 Nordic Semiconductor ASA
-
-# SPDX-License-Identifier: Apache-2.0
-
-# In HWMv1 the KCONFIG_BOARD_DIR points directly to the BOARD_DIR.
-# Set the BOARD_DIR variable for backwards compatibility to legacy hardware model.
-BOARD_DIR := $(KCONFIG_BOARD_DIR)
-
-choice
-	prompt "Board Selection"
-
-source "$(KCONFIG_BOARD_DIR)/Kconfig.board"
-
-endchoice
diff --git a/boards/aconno/acn52832/acn52832.yaml b/boards/aconno/acn52832/acn52832.yaml
index 72e04b829f9..be2495a5a49 100644
--- a/boards/aconno/acn52832/acn52832.yaml
+++ b/boards/aconno/acn52832/acn52832.yaml
@@ -5,6 +5,5 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 512
diff --git a/boards/acrn/acrn/Kconfig b/boards/acrn/acrn/Kconfig
index 7d7b97605a4..857bd347075 100644
--- a/boards/acrn/acrn/Kconfig
+++ b/boards/acrn/acrn/Kconfig
@@ -1,17 +1,9 @@
-# Copyright (c) 2019-2024 Intel Corporation
+# Copyright (c) 2019-2025 Intel Corporation
 #
 # SPDX-License-Identifier: Apache-2.0
 
-config BOARD_ACRN
+config ACRN_COMMON
 	bool
+	default y if BOARD_ACRN || BOARD_ACRN_EHL_CRB || BOARD_ACRN_ADL_CRB
 	select CPU_HAS_FPU
 	select X86_64
-	help
-	  "ACRN User OS"
-
-config BOARD_ACRN_EHL_CRB
-	bool
-	select CPU_HAS_FPU
-	select X86_64
-	help
-	  "ACRN User OS on ElkhartLake CRB"
diff --git a/boards/acrn/acrn/Kconfig.acrn_adl_crb b/boards/acrn/acrn/Kconfig.acrn_adl_crb
new file mode 100644
index 00000000000..c105411cede
--- /dev/null
+++ b/boards/acrn/acrn/Kconfig.acrn_adl_crb
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ACRN_ADL_CRB
+	select SOC_ATOM
diff --git a/boards/acrn/acrn/acrn_adl_crb.dts b/boards/acrn/acrn/acrn_adl_crb.dts
new file mode 100644
index 00000000000..c13054d3891
--- /dev/null
+++ b/boards/acrn/acrn/acrn_adl_crb.dts
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "acrn.dts"
diff --git a/boards/acrn/acrn/acrn_adl_crb.yaml b/boards/acrn/acrn/acrn_adl_crb.yaml
new file mode 100644
index 00000000000..4bb5438c97c
--- /dev/null
+++ b/boards/acrn/acrn/acrn_adl_crb.yaml
@@ -0,0 +1,11 @@
+identifier: acrn_adl_crb
+name: ACRN on ADL configuration
+type: mcu
+arch: x86
+toolchain:
+  - zephyr
+ram: 8192
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
diff --git a/boards/acrn/acrn/acrn_adl_crb_defconfig b/boards/acrn/acrn/acrn_adl_crb_defconfig
new file mode 100644
index 00000000000..de5dfe547e7
--- /dev/null
+++ b/boards/acrn/acrn/acrn_adl_crb_defconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2025 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_PIC_DISABLE=y
+CONFIG_LOAPIC=y
+CONFIG_X2APIC=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1500000000
+CONFIG_BUILD_OUTPUT_BIN=y
+CONFIG_SHELL_BACKEND_SERIAL_INTERRUPT_DRIVEN=n
+CONFIG_KERNEL_VM_SIZE=0x5000000
+CONFIG_APIC_TSC_DEADLINE_TIMER=y
diff --git a/boards/acrn/acrn/board.yml b/boards/acrn/acrn/board.yml
index dce367c0f96..6efec2b876e 100644
--- a/boards/acrn/acrn/board.yml
+++ b/boards/acrn/acrn/board.yml
@@ -8,4 +8,9 @@ boards:
   - name: acrn_ehl_crb
     full_name: ACRN on EHL hypervisor
     socs:
-      - name: elkhart_lake
+      - name: atom
+
+  - name: acrn_adl_crb
+    full_name: ACRN Hypervisor on ADL
+    socs:
+      - name: atom
diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_1_4_0.yaml b/boards/actinius/icarus/actinius_icarus_nrf9160_1_4_0.yaml
index 119745e52ed..1dda7976354 100644
--- a/boards/actinius/icarus/actinius_icarus_nrf9160_1_4_0.yaml
+++ b/boards/actinius/icarus/actinius_icarus_nrf9160_1_4_0.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 88
 flash: 256
diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_2_0_0.yaml b/boards/actinius/icarus/actinius_icarus_nrf9160_2_0_0.yaml
index f017d9c6f3c..2c09e3c40aa 100644
--- a/boards/actinius/icarus/actinius_icarus_nrf9160_2_0_0.yaml
+++ b/boards/actinius/icarus/actinius_icarus_nrf9160_2_0_0.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 88
 flash: 256
diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_ns_1_4_0.yaml b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_1_4_0.yaml
index 07338249661..fd25e54d37f 100644
--- a/boards/actinius/icarus/actinius_icarus_nrf9160_ns_1_4_0.yaml
+++ b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_1_4_0.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 128
 flash: 192
diff --git a/boards/actinius/icarus/actinius_icarus_nrf9160_ns_2_0_0.yaml b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_2_0_0.yaml
index a6a5ecc7738..3d6cdb5b10c 100644
--- a/boards/actinius/icarus/actinius_icarus_nrf9160_ns_2_0_0.yaml
+++ b/boards/actinius/icarus/actinius_icarus_nrf9160_ns_2_0_0.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 128
 flash: 192
diff --git a/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160.yaml b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160.yaml
index 8fd851899ba..af041509705 100644
--- a/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160.yaml
+++ b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 88
 flash: 256
diff --git a/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.yaml b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.yaml
index 89b21ece170..a2d50d9dd27 100644
--- a/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.yaml
+++ b/boards/actinius/icarus_bee/actinius_icarus_bee_nrf9160_ns.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 128
 flash: 192
diff --git a/boards/actinius/icarus_som/actinius_icarus_som_nrf9160.yaml b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160.yaml
index 1eab5025340..1a6ac77ff8c 100644
--- a/boards/actinius/icarus_som/actinius_icarus_som_nrf9160.yaml
+++ b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 88
 flash: 256
diff --git a/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.yaml b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.yaml
index 0a6968beec2..e49b377cab1 100644
--- a/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.yaml
+++ b/boards/actinius/icarus_som/actinius_icarus_som_nrf9160_ns.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 128
 flash: 192
diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160.yaml b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160.yaml
index 3b7d7377caa..56eebadfab1 100644
--- a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160.yaml
+++ b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 88
 flash: 256
diff --git a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.yaml b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.yaml
index b41972384ba..cd0a90c222b 100644
--- a/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.yaml
+++ b/boards/actinius/icarus_som_dk/actinius_icarus_som_dk_nrf9160_ns.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 128
 flash: 192
diff --git a/boards/adafruit/feather_esp32s2/CMakeLists.txt b/boards/adafruit/feather_esp32s2/CMakeLists.txt
new file mode 100644
index 00000000000..218a0602483
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/CMakeLists.txt
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+zephyr_library_sources(board.c)
diff --git a/boards/adafruit/feather_esp32s2/Kconfig b/boards/adafruit/feather_esp32s2/Kconfig
new file mode 100644
index 00000000000..272e4c39ee9
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/Kconfig
@@ -0,0 +1,11 @@
+# Copyright (c) 2023 Google, LLC
+# SPDX-License-Identifier: Apache-2.0
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+	int
+	default 4096
+
+config BOARD_NEEDS_LATE_HOOK
+	bool
+	default y if BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT || BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT_REVERSE
+	select BOARD_LATE_INIT_HOOK
diff --git a/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2 b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2
new file mode 100644
index 00000000000..63f45c11300
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Philipp Steiner <philipp.steiner@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ADAFRUIT_FEATHER_ESP32S2
+	select SOC_ESP32S2_R2
diff --git a/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft
new file mode 100644
index 00000000000..e54cad03d42
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Philipp Steiner <philipp.steiner@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT
+	select SOC_ESP32S2_R2
diff --git a/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft_reverse b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft_reverse
new file mode 100644
index 00000000000..1d470f87490
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/Kconfig.adafruit_feather_esp32s2_tft_reverse
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Philipp Steiner <philipp.steiner@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT_REVERSE
+	select SOC_ESP32S2_R2
diff --git a/boards/adafruit/feather_esp32s2/Kconfig.defconfig b/boards/adafruit/feather_esp32s2/Kconfig.defconfig
new file mode 100644
index 00000000000..734863a6654
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/Kconfig.defconfig
@@ -0,0 +1,28 @@
+# Copyright (c) 2025 Philipp Steiner <philipp.steiner@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT || BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT_REVERSE
+
+if DISPLAY
+
+choice ST7789V_PIXEL_FORMAT
+	default ST7789V_RGB565
+endchoice
+
+if LVGL
+
+config LV_Z_BITS_PER_PIXEL
+	default 16
+
+choice LV_COLOR_DEPTH
+	default LV_COLOR_DEPTH_16
+endchoice
+
+config LV_COLOR_16_SWAP
+	default y
+
+endif # LVGL
+
+endif # DISPLAY
+
+endif # BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT || BOARD_ADAFRUIT_FEATHER_ESP32S2_TFT_REVERSE
diff --git a/boards/adafruit/feather_esp32s2/Kconfig.sysbuild b/boards/adafruit/feather_esp32s2/Kconfig.sysbuild
new file mode 100644
index 00000000000..3a2d17ac5cf
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/Kconfig.sysbuild
@@ -0,0 +1,10 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+choice BOOTLOADER
+	default BOOTLOADER_MCUBOOT
+endchoice
+
+choice BOOT_SIGNATURE_TYPE
+	default BOOT_SIGNATURE_TYPE_NONE
+endchoice
diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2-pinctrl.dtsi b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2-pinctrl.dtsi
new file mode 100644
index 00000000000..a6c67847bbb
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2-pinctrl.dtsi
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2025 Philipp Steiner <philipp.steiner@gmail.com>.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
+#include <dt-bindings/pinctrl/esp32s2-pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/esp32s2-gpio-sigmap.h>
+
+&pinctrl {
+	/*  Debug TX (DBG) - This is the hardware UART debug pin */
+	uart0_default: uart0_default {
+		group1 {
+			pinmux = <UART0_TX_GPIO43>;
+			output-high;
+		};
+	};
+
+	uart1_default: uart1_default {
+		group1 {
+			pinmux = <UART1_TX_GPIO39>;
+			output-high;
+		};
+
+		group2 {
+			pinmux = <UART1_RX_GPIO38>;
+			bias-pull-up;
+		};
+	};
+
+	spim2_default: spim2_default {
+		group1 {
+			pinmux = <SPIM2_MISO_GPIO37>,
+				 <SPIM2_SCLK_GPIO36>,
+				 <SPIM2_CSEL_GPIO7>;
+		};
+
+		group2 {
+			pinmux = <SPIM2_MOSI_GPIO35>;
+			output-low;
+		};
+	};
+
+	spim3_ws2812_led: spim3_ws2812_led {
+		group1 {
+			pinmux = <SPIM3_MOSI_GPIO33>;
+		};
+	};
+
+	i2c0_default: i2c0_default {
+		group1 {
+			pinmux = <I2C0_SDA_GPIO3>,
+				 <I2C0_SCL_GPIO4>;
+			drive-open-drain;
+			output-high;
+		};
+	};
+
+	twai_default: twai_default {
+		group1 {
+			pinmux = <TWAI_TX_GPIO5>,
+				 <TWAI_RX_GPIO6>;
+		};
+	};
+};
diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2.dts b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2.dts
new file mode 100644
index 00000000000..e7e3f8efb7b
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2.dts
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Philipp Steiner <philipp.steiner@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "adafruit_feather_esp32s2_common.dtsi"
+#include "feather_connector.dtsi"
+
+/ {
+	model = "Adafruit Feather ESP32-S2";
+	compatible = "espressif,esp32s2";
+};
diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.overlay b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.overlay
new file mode 100644
index 00000000000..096357d93eb
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Philipp Steiner <philipp.steiner@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	/*
+	 * On-board transistor powers I2C pull-ups and external devices connected
+	 * via the STEMMA QT connector.
+	 */
+	i2c_reg: i2c_reg {
+		label = "I2C Power";
+		compatible = "power-domain-gpio";
+		#power-domain-cells = <0>;
+		enable-gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
+		startup-delay-us = <10>;
+	};
+};
diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.yaml b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.yaml
new file mode 100644
index 00000000000..7246420988f
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_B.yaml
@@ -0,0 +1,20 @@
+identifier: adafruit_feather_esp32s2@B
+name: Adafruit Feather ESP32-S2 Rev B
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+supported:
+  - gpio
+  - uart
+  - i2c
+  - spi
+  - counter
+  - watchdog
+  - entropy
+  - pwm
+  - dma
+vendor: adafruit
+testing:
+  ignore_tags:
+    - bluetooth
diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.overlay b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.overlay
new file mode 100644
index 00000000000..94550a53acd
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Philipp Steiner <philipp.steiner@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	/*
+	 * On-board regulator powers I2C pull-ups and external devices connected
+	 * via the STEMMA QT connector.
+	 */
+	i2c_reg: i2c_reg {
+		label = "I2C Power";
+		compatible = "power-domain-gpio";
+		#power-domain-cells = <0>;
+		enable-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <10>;
+	};
+};
diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.yaml b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.yaml
new file mode 100644
index 00000000000..86ca59f5965
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_C.yaml
@@ -0,0 +1,20 @@
+identifier: adafruit_feather_esp32s2@C
+name: Adafruit Feather ESP32-S2 Rev C
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+supported:
+  - gpio
+  - uart
+  - i2c
+  - spi
+  - counter
+  - watchdog
+  - entropy
+  - pwm
+  - dma
+vendor: adafruit
+testing:
+  ignore_tags:
+    - bluetooth
diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_common.dtsi b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_common.dtsi
new file mode 100644
index 00000000000..257ea650a29
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_common.dtsi
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2025 Philipp Steiner <philipp.steiner@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <espressif/esp32s2/esp32s2.dtsi>
+#include <espressif/esp32s2/esp32s2_wroom.dtsi>
+#include "adafruit_feather_esp32s2-pinctrl.dtsi"
+#include <espressif/partitions_0x1000_default.dtsi>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <dt-bindings/led/led.h>
+#include <dt-bindings/led/worldsemi_ws2812c.h>
+#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
+
+/ {
+	compatible = "espressif,esp32s2";
+
+	chosen {
+		zephyr,sram = &sram1;
+		/*
+		 * uart1 is used as the default uart for zephyr,console and zephyr,shell,
+		 * because USB-OTG is until now not supported and USB-CDC is not available
+		 * for ESP32-S2.
+		 * See issue #29394 - ESP32 development overview
+		 * To use uart1 a FTDI-USB-RS232 or similar needs to be connected to the RX/TX pins.
+		 * See feather_connector.dtsi
+		 */
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+	};
+
+	aliases {
+		led0 = &led0;
+		i2c-0 = &i2c0;
+		sw0 = &user_button;
+		led-strip = &led_strip;
+		watchdog0 = &wdt0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		status = "okay";
+
+		led0: led_0 {
+			label = "Red-LED";
+			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		status = "okay";
+
+		user_button: user_button {
+			label = "BOOT Button";
+			gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-names = "default";
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart1_default>;
+	pinctrl-names = "default";
+};
+
+&gpio0 {
+	status = "okay";
+
+	neopixel_power_enable {
+		gpio-hog;
+		gpios = <21 GPIO_ACTIVE_HIGH>;
+		output-high;
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&timer0 {
+	status = "okay";
+};
+
+&timer1 {
+	status = "okay";
+};
+
+&timer2 {
+	status = "okay";
+};
+
+&timer3 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+};
+
+&trng0 {
+	status = "okay";
+};
+
+&spi2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	pinctrl-0 = <&spim2_default>;
+	pinctrl-names = "default";
+};
+
+&spi3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	pinctrl-0 = <&spim3_ws2812_led>;
+	pinctrl-names = "default";
+
+	line-idle-low;
+
+	led_strip: ws2812@0 {
+		compatible = "worldsemi,ws2812-spi";
+
+		/* WS2812 */
+		reg = <0>;
+		spi-max-frequency = <6400000>;
+		chain-length = <1>;
+		spi-cpha;
+		spi-one-frame = <WS2812C_ONE_FRAME>; /* 11110000: 625ns high and 625ns low */
+		spi-zero-frame = <WS2812C_ZERO_FRAME>; /* 11000000: 312.5ns high and 937.5ns low */
+		color-mapping = <LED_COLOR_ID_GREEN>,
+				<LED_COLOR_ID_RED>,
+				<LED_COLOR_ID_BLUE>;
+	};
+};
+
+&twai {
+	pinctrl-0 = <&twai_default>;
+	pinctrl-names = "default";
+};
+
+&wdt0 {
+	status = "okay";
+};
diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_defconfig b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_defconfig
new file mode 100644
index 00000000000..d8fbaa87925
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_defconfig
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.dts b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.dts
new file mode 100644
index 00000000000..c57ebdc8b8b
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.dts
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2025 Philipp Steiner <philipp.steiner@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "adafruit_feather_esp32s2_common.dtsi"
+#include "feather_connector_tft.dtsi"
+
+/ {
+	model = "Adafruit Feather ESP32-S2 TFT";
+	compatible = "espressif,esp32s2";
+
+	chosen {
+		zephyr,display = &st7789v_tft;
+	};
+
+	aliases {
+		backlight = &led1;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		status = "okay";
+
+		led1: led_1 {
+			label = "TFT Backlight";
+			gpios = <&gpio1 45 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	/*
+	 * On-board regulator powers I2C pull-ups and external devices connected
+	 * via the STEMMA QT connector.
+	 */
+	i2c_reg: i2c_reg {
+		label = "I2C Power";
+		compatible = "power-domain-gpio";
+		#power-domain-cells = <0>;
+		enable-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <10>;
+	};
+
+	mipi_dbi {
+		compatible = "zephyr,mipi-dbi-spi";
+		spi-dev = <&spi2>;
+		dc-gpios = <&gpio1 39 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio1 40 GPIO_ACTIVE_LOW>;
+		write-only;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		st7789v_tft: st7789v_tft@0 {
+			compatible = "sitronix,st7789v";
+			status = "disabled";
+
+			/* Also powered by i2c_reg */
+			power-domains = <&i2c_reg>;
+
+			mipi-max-frequency = <DT_FREQ_M(20)>;
+			reg = <0>;
+			width = <135>;
+			height = <240>;
+			x-offset = <52>;
+			y-offset = <40>;
+			vcom = <0x20>;
+			gctrl = <0x35>;
+			vrhs = <0x0b>;
+			vdvs = <0x20>;
+			mdac = <0x08>;
+			gamma = <0x01>;
+			colmod = <0x55>;
+			lcm = <0x2c>;
+			porch-param = [0c 0c 00 33 33];
+			cmd2en-param = [5a 69 02 01];
+			pwctrl1-param = [a4 a1];
+			pvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25];
+			nvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25];
+			ram-param = [00 F0];
+			rgb-param = [40 02 14];
+			mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE";
+		};
+	};
+};
+
+&gpio0 {
+	status = "okay";
+
+	neopixel_power_enable {
+		gpio-hog;
+		gpios = <34 GPIO_ACTIVE_HIGH>;
+		output-high;
+	};
+};
+
+&pinctrl {
+	uart1_default: uart1_default {
+		group1 {
+			pinmux = <UART1_TX_GPIO1>;
+			output-high;
+		};
+
+		group2 {
+			pinmux = <UART1_RX_GPIO2>;
+			bias-pull-up;
+		};
+	};
+
+	i2c0_default: i2c0_default {
+		group1 {
+			pinmux = <I2C0_SDA_GPIO42>,
+				 <I2C0_SCL_GPIO41>;
+			drive-open-drain;
+			output-high;
+		};
+	};
+};
diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.yaml b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.yaml
new file mode 100644
index 00000000000..99ca5778e7a
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft.yaml
@@ -0,0 +1,21 @@
+identifier: adafruit_feather_esp32s2_tft
+name: Adafruit ESP32-S2 TFT Feather
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+supported:
+  - gpio
+  - uart
+  - i2c
+  - spi
+  - counter
+  - watchdog
+  - entropy
+  - pwm
+  - dma
+  - display
+vendor: adafruit
+testing:
+  ignore_tags:
+    - bluetooth
diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_defconfig b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_defconfig
new file mode 100644
index 00000000000..d8fbaa87925
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_defconfig
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts
new file mode 100644
index 00000000000..fbb4b0993ae
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.dts
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2025 Philipp Steiner <philipp.steiner@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "adafruit_feather_esp32s2_common.dtsi"
+#include "feather_connector.dtsi"
+
+/ {
+	model = "Adafruit Feather ESP32-S2 TFT Reverse";
+	compatible = "espressif,esp32s2";
+
+	chosen {
+		zephyr,display = &st7789v_tft;
+	};
+
+	aliases {
+		backlight = &led1;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		status = "okay";
+
+		led1: led_1 {
+			label = "TFT Backlight";
+			gpios = <&gpio1 45 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		status = "okay";
+
+		d1_button: d1_button {
+			label = "D1 Button";
+			gpios = <&gpio0 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+
+		d2_button: d2_button {
+			label = "D3 Button";
+			gpios = <&gpio0 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			zephyr,code = <INPUT_KEY_3>;
+		};
+	};
+
+	i2c_reg: i2c_reg {
+		label = "TFT I2C Power";
+		compatible = "power-domain-gpio";
+		#power-domain-cells = <0>;
+		enable-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <10>;
+	};
+
+	mipi_dbi {
+		compatible = "zephyr,mipi-dbi-spi";
+		spi-dev = <&spi2>;
+		dc-gpios = <&gpio1 40 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio1 41 GPIO_ACTIVE_LOW>;
+		write-only;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		st7789v_tft: st7789v_tft@0 {
+			compatible = "sitronix,st7789v";
+			status = "disabled";
+
+			/* Also powered by i2c_reg */
+			power-domains = <&i2c_reg>;
+
+			mipi-max-frequency = <DT_FREQ_M(20)>;
+			reg = <0>;
+			width = <135>;
+			height = <240>;
+			x-offset = <52>;
+			y-offset = <40>;
+			vcom = <0x20>;
+			gctrl = <0x35>;
+			vrhs = <0x0b>;
+			vdvs = <0x20>;
+			mdac = <0x08>;
+			gamma = <0x01>;
+			colmod = <0x55>;
+			lcm = <0x2c>;
+			porch-param = [0c 0c 00 33 33];
+			cmd2en-param = [5a 69 02 01];
+			pwctrl1-param = [a4 a1];
+			pvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25];
+			nvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25];
+			ram-param = [00 F0];
+			rgb-param = [40 02 14];
+			mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE";
+		};
+	};
+};
+
+&pinctrl {
+	spim2_default: spim2_default {
+		group1 {
+			pinmux = <SPIM2_MISO_GPIO37>,
+				 <SPIM2_SCLK_GPIO36>,
+				 <SPIM2_CSEL_GPIO42>;
+		};
+
+		group2 {
+			pinmux = <SPIM2_MOSI_GPIO35>;
+			output-low;
+		};
+	};
+};
+
+&i2c0 {
+	max17048: max17048@36 {
+		compatible = "maxim,max17048";
+		status = "disabled";
+		reg = <0x36 >;
+		power-domains = <&i2c_reg>;
+	};
+};
diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.yaml b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.yaml
new file mode 100644
index 00000000000..f5c673e211b
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse.yaml
@@ -0,0 +1,22 @@
+identifier: adafruit_feather_esp32s2_tft_reverse/esp32s2
+name: Adafruit ESP32-S2 TFT Feather Reverse
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+supported:
+  - gpio
+  - uart
+  - i2c
+  - spi
+  - counter
+  - watchdog
+  - entropy
+  - pwm
+  - dma
+  - display
+  - fuel_gauge
+vendor: adafruit
+testing:
+  ignore_tags:
+    - bluetooth
diff --git a/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse_defconfig b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse_defconfig
new file mode 100644
index 00000000000..d8fbaa87925
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/adafruit_feather_esp32s2_tft_reverse_defconfig
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/adafruit/feather_esp32s2/board.c b/boards/adafruit/feather_esp32s2/board.c
new file mode 100644
index 00000000000..e7f65a4ba53
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/board.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024 Leon Rinkel <leon@rinkel.me>
+ * Copyright (c) 2025 Philipp Steiner <philipp.steiner@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Automatically turns on backlight if display is configured, i.e. display DT
+ * node has status okay.
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/init.h>
+
+#define DISPLAY_NODE DT_CHOSEN(zephyr_display)
+
+#if DT_NODE_HAS_STATUS(DISPLAY_NODE, okay)
+static const struct gpio_dt_spec backlight = GPIO_DT_SPEC_GET(DT_ALIAS(backlight), gpios);
+#endif
+
+void board_late_init_hook(void)
+{
+#if DT_NODE_HAS_STATUS(DISPLAY_NODE, okay)
+	if (gpio_is_ready_dt(&backlight)) {
+		gpio_pin_configure_dt(&backlight, GPIO_OUTPUT_ACTIVE);
+	}
+#endif
+}
diff --git a/boards/adafruit/feather_esp32s2/board.cmake b/boards/adafruit/feather_esp32s2/board.cmake
new file mode 100644
index 00000000000..2f04d1fe886
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/board.cmake
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
+  set(OPENOCD OPENOCD-NOTFOUND)
+endif()
+find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
+
+include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/adafruit/feather_esp32s2/board.yml b/boards/adafruit/feather_esp32s2/board.yml
new file mode 100644
index 00000000000..fda3bf5e855
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/board.yml
@@ -0,0 +1,22 @@
+boards:
+- name: adafruit_feather_esp32s2
+  full_name: Adafruit Feather ESP32S2
+  vendor: adafruit
+  socs:
+  - name: esp32s2
+  revision:
+    format: "letter"
+    default: "C"
+    revisions:
+    - name: "B"
+    - name: "C"
+- name: adafruit_feather_esp32s2_tft
+  full_name: Adafruit Feather ESP32S2 TFT
+  vendor: adafruit
+  socs:
+  - name: esp32s2
+- name: adafruit_feather_esp32s2_tft_reverse
+  full_name: Adafruit Feather ESP32S2 TFT Reverse
+  vendor: adafruit
+  socs:
+  - name: esp32s2
diff --git a/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2.rst b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2.rst
new file mode 100644
index 00000000000..a5fb76324d9
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2.rst
@@ -0,0 +1,358 @@
+.. zephyr:board:: adafruit_feather_esp32s2
+
+Overview
+********
+
+The Adafruit Feather ESP32-S2 boards are ESP32-S2 development boards in the
+Feather standard layout, sharing peripheral placement with other devices labeled
+as Feathers or FeatherWings. The board is equipped with an ESP32-S2 mini module,
+a LiPo battery charger, a fuel gauge, a USB-C and `SparkFun Qwiic`_-compatible
+`STEMMA QT`_ connector for the I2C bus.
+
+Hardware
+********
+
+- ESP32-S2 mini module, featuring the 240MHz Tensilica processor
+- 320KB SRAM, 4MB flash + 2MB PSRAM
+- USB-C directly connected to the ESP32-S2 for USB
+- LiPo connector and built-in battery charging when powered via USB-C
+- LC709203 or MAX17048 fuel gauge for battery voltage and state-of-charge reporting
+- Built-in NeoPixel indicator RGB LED
+- STEMMA QT connector for I2C devices, with switchable power for low-power mode
+
+.. note::
+
+   - The `Adafruit ESP32-S2 Feather with BME280 Sensor`_ is the same board as the
+     `Adafruit ESP32-S2 Feather`_ but with an already equipped BME280 Sensor, but is not
+     stated as a separate board, instead the BME280 needs to be added via a devicetree
+     overlay. All boards, except the `Adafruit ESP32-S2 Feather with BME280 Sensor`_ have a
+     space for it, but will not be shipped with.
+   - As of May 31, 2023 - Adafruit has changed the battery monitor chip from the
+     now-discontinued LC709203 to the MAX17048. Check the back silkscreen of your Feather to
+     see which chip you have.
+   - For the MAX17048 a driver in zephyr exists and is supported, but needs to be added via
+     a devicetree overlay.
+   - For the LC709203 a driver does'nt exists yet and the fuel gauge for boards with this IC
+     is not available.
+   - For the `Adafruit ESP32-S2 Feather`_ there are two different Revisions ``rev B`` and
+     ``rev C``. The ``rev C`` board has revised the power circuitry for the NeoPixel and I2C
+     QT port. Instead of a transistor the ``rev C`` has a LDO regulator. To enable the
+     NeoPixel and I2C QT port on ``rev B`` boards ``GPIO7`` (``i2c_reg``) needs to be set to
+     LOW and on ``rev C`` boards it needs to be set HIGH.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+.. note::
+   USB-OTG is until now not supported see `ESP32 development overview`_. To see a serial output
+   a FTDI-USB-RS232 or similar needs to be connected to the RX/TX pins on the feather connector.
+
+Connections and IOs
+===================
+
+The `Adafruit ESP32-S2 Feather`_ User Guide has detailed information about the board including
+pinouts and the schematic.
+
+- `Adafruit ESP32-S2 Feather Pinouts`_
+- `Adafruit ESP32-S2 Feather Schematic`_
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Prerequisites
+=============
+
+Espressif HAL requires WiFi binary blobs in order work. Run the command below
+to retrieve those files.
+
+.. code-block:: console
+
+   west update
+   west blobs fetch hal_espressif
+
+Building & Flashing
+*******************
+
+Simple boot
+===========
+
+The board could be loaded using the single binary image, without 2nd stage
+bootloader. It is the default option when building the application without
+additional configuration.
+
+.. note::
+
+   Simple boot does not provide any security features nor OTA updates.
+
+MCUboot bootloader
+==================
+
+User may choose to use MCUboot bootloader instead. In that case the bootloader
+must be built (and flashed) at least once.
+
+There are two options to be used when building an application:
+
+1. Sysbuild
+2. Manual build
+
+.. note::
+
+   User can select the MCUboot bootloader by adding the following line
+   to the board default configuration file.
+
+   .. code:: cfg
+
+      CONFIG_BOOTLOADER_MCUBOOT=y
+
+Sysbuild
+========
+
+The sysbuild makes possible to build and flash all necessary images needed to
+bootstrap the board with the ESP32 SoC.
+
+To build the sample application using sysbuild use the command:
+
+**Rev B**
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s2@B
+   :goals: build
+   :west-args: --sysbuild
+   :compact:
+
+**Rev C**
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s2@C
+   :goals: build
+   :west-args: --sysbuild
+   :compact:
+
+By default, the ESP32 sysbuild creates bootloader (MCUboot) and application
+images. But it can be configured to create other kind of images.
+
+Build directory structure created by sysbuild is different from traditional
+Zephyr build. Output is structured by the domain subdirectories:
+
+.. code-block::
+
+   build/
+   ├── hello_world
+   │   └── zephyr
+   │       ├── zephyr.elf
+   │       └── zephyr.bin
+   ├── mcuboot
+   │    └── zephyr
+   │       ├── zephyr.elf
+   │       └── zephyr.bin
+   └── domains.yaml
+
+.. note::
+
+   With ``--sysbuild`` option the bootloader will be re-build and re-flash
+   every time the pristine build is used.
+
+For more information about the system build please read the :ref:`sysbuild` documentation.
+
+Manual build
+============
+
+During the development cycle, it is intended to build & flash as quickly possible.
+For that reason, images can be built one at a time using traditional build.
+
+The instructions following are relevant for both manual build and sysbuild.
+The only difference is the structure of the build directory.
+
+.. note::
+
+   Remember that bootloader (MCUboot) needs to be flash at least once.
+
+Build and flash applications as usual:
+
+**Rev B**
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s2@B
+   :goals: build
+
+**Rev C**
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s2@C
+   :goals: build
+
+The usual ``flash`` target will work. Here is an example for the :zephyr:code-sample:`hello_world`
+application.
+
+To enter ROM bootloader mode, hold down ``boot-button`` while clicking reset button.
+When in the ROM bootloader, you can upload code and query the chip using ``west flash``.
+
+
+**Rev B**
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: adafruit_feather_esp32s2@B
+      :goals: flash
+
+**Rev C**
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: adafruit_feather_esp32s2@C
+      :goals: flash
+
+After the flashing you will receive most likely this Error:
+
+.. code-block:: console
+
+   WARNING: ESP32-S2FNR2 (revision v0.0) chip was placed into download mode using GPIO0.
+   esptool.py can not exit the download mode over USB. To run the app, reset the chip manually.
+   To suppress this note, set --after option to 'no_reset'.
+   FATAL ERROR: command exited with status 1: ...
+
+As stated in the Warning-Message ``esptool`` can't reset the board by itself and this message
+can be ignored and the board needs to be reseted via the Reset-Button manually.
+
+Open the serial monitor using the following command:
+
+.. code-block:: shell
+
+   west espressif monitor
+
+After the board has been manually reseted and booted, you should see the following
+message in the monitor:
+
+.. code-block:: console
+
+   ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
+   Hello World! adafruit_feather_esp32s2
+
+Debugging
+*********
+
+ESP32-S2 support on OpenOCD is available at `OpenOCD`_.
+
+ESP32-S2 has a built-in JTAG circuitry and can be debugged without any
+additional chip. Only an USB cable connected to the D+/D- pins is necessary.
+
+Further documentation can be obtained from the SoC vendor
+in `JTAG debugging for ESP32-S2`_.
+
+You can debug an application in the usual way. Here is an example for
+the :zephyr:code-sample:`hello_world` application.
+
+**Rev B**
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s2@B
+   :goals: debug
+
+**Rev C**
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s2@C
+   :goals: debug
+
+Testing the On-Board-LED
+************************
+
+There is a sample available to verify that the LEDs on the board are
+functioning correctly with Zephyr:
+
+**Rev B**
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: adafruit_feather_esp32s2@B
+   :goals: build flash
+
+**Rev C**
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: adafruit_feather_esp32s2@C
+   :goals: build flash
+
+Testing the NeoPixel
+********************
+
+There is a sample available to verify that the NeoPixel on the board are
+functioning correctly with Zephyr:
+
+**Rev B**
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/drivers/led/led_strip
+      :board: adafruit_feather_esp32s2@B
+      :goals: build flash
+
+**Rev C**
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/drivers/led/led_strip
+      :board: adafruit_feather_esp32s2@C
+      :goals: build flash
+
+Testing the Fuel Gauge (MAX17048)
+*********************************
+
+There is a sample available to verify that the MAX17048 fuel gauge on the board are
+functioning correctly with Zephyr:
+
+.. note::
+   As of May 31, 2023 Adafruit changed the battery monitor chip from the now-discontinued LC709203
+   to the MAX17048.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/fuel_gauge/max17048/
+   :board: adafruit_feather_esp32s2@C
+   :goals: build flash
+
+Testing Wi-Fi
+*************
+
+There is a sample available to verify that the Wi-Fi on the board are
+functioning correctly with Zephyr:
+
+.. note::
+   The Prerequisites must be met before testing Wi-Fi.
+
+**Rev B**
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/net/wifi/shell
+      :board: adafruit_feather_esp32s2@B
+      :goals: build flash
+
+**Rev C**
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/net/wifi/shell
+      :board: adafruit_feather_esp32s2@C
+      :goals: build flash
+
+References
+**********
+
+.. target-notes::
+
+.. _`Adafruit ESP32-S2 Feather`: https://www.adafruit.com/product/5000
+.. _`Adafruit ESP32-S2 Feather with BME280 Sensor`: https://www.adafruit.com/product/5303
+.. _`OpenOCD`: https://github.com/openocd-org/openocd
+.. _`ESP32 development overview`: https://github.com/zephyrproject-rtos/zephyr/issues/29394#issuecomment-2635037831
+.. _`Adafruit ESP32-S2 Feather Pinouts`: https://learn.adafruit.com/adafruit-esp32-s2-feather/pinouts
+.. _`Adafruit ESP32-S2 Feather Schematic`: https://learn.adafruit.com/adafruit-esp32-s2-feather/downloads
+.. _`SparkFun Qwiic`: https://www.sparkfun.com/qwiic
+.. _`STEMMA QT`: https://learn.adafruit.com/introducing-adafruit-stemma-qt
+.. _`JTAG debugging for ESP32-S2`: https://docs.espressif.com/projects/esp-idf/en/stable/esp32s2/api-guides/jtag-debugging/index.html
diff --git a/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft.rst b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft.rst
new file mode 100644
index 00000000000..6f44363ca4b
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft.rst
@@ -0,0 +1,296 @@
+.. zephyr:board:: adafruit_feather_esp32s2_tft
+
+Overview
+********
+
+The Adafruit Feather ESP32-S2 boards are ESP32-S2 development boards in the
+Feather standard layout, sharing peripheral placement with other devices labeled
+as Feathers or FeatherWings. The board is equipped with an ESP32-S2 mini module,
+a LiPo battery charger, a fuel gauge, a USB-C and `SparkFun Qwiic`_-compatible
+`STEMMA QT`_ connector for the I2C bus.
+
+Hardware
+********
+
+- ESP32-S2 mini module, featuring the 240MHz Tensilica processor
+- 320KB SRAM, 4MB flash + 2MB PSRAM
+- USB-C directly connected to the ESP32-S2 for USB
+- LiPo connector and built-in battery charging when powered via USB-C
+- LC709203 or MAX17048 fuel gauge for battery voltage and state-of-charge reporting
+- Charging indicator LED, user LED, reset and boot buttons.
+- Built-in NeoPixel indicator RGB LED
+- STEMMA QT connector for I2C devices, with switchable power for low-power mode
+- 240x135 pixel IPS TFT color display with 1.14" diagonal and ST7789 chipset
+
+.. note::
+
+   - The board has a space for a BME280, but will not be shipped with.
+   - As of May 31, 2023 - Adafruit has changed the battery monitor chip from the
+     now-discontinued LC709203 to the MAX17048. Check the back silkscreen of your Feather to
+     see which chip you have.
+   - For the MAX17048 a driver in zephyr exists and is supported, but needs to be added via
+     a devicetree overlay.
+   - For the LC709203 a driver does'nt exists yet and the fuel gauge for boards with this IC
+     is not available.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+.. note::
+   USB-OTG is until now not supported see `ESP32 development overview`_. To see a serial output
+   a FTDI-USB-RS232 or similar needs to be connected to the RX/TX pins on the feather connector.
+
+Connections and IOs
+===================
+
+The `Adafruit ESP32-S2 TFT Feather`_ User Guide has detailed information about the board including
+pinouts and the schematic.
+
+- `Adafruit ESP32-S2 TFT Feather Pinouts`_
+- `Adafruit ESP32-S2 TFT Feather Schematic`_
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Prerequisites
+=============
+
+Espressif HAL requires WiFi binary blobs in order work. Run the command below
+to retrieve those files.
+
+.. code-block:: console
+
+   west update
+   west blobs fetch hal_espressif
+
+Building & Flashing
+*******************
+
+Simple boot
+===========
+
+The board could be loaded using the single binary image, without 2nd stage
+bootloader. It is the default option when building the application without
+additional configuration.
+
+.. note::
+
+   Simple boot does not provide any security features nor OTA updates.
+
+MCUboot bootloader
+==================
+
+User may choose to use MCUboot bootloader instead. In that case the bootloader
+must be built (and flashed) at least once.
+
+There are two options to be used when building an application:
+
+1. Sysbuild
+2. Manual build
+
+.. note::
+
+   User can select the MCUboot bootloader by adding the following line
+   to the board default configuration file.
+
+   .. code:: cfg
+
+      CONFIG_BOOTLOADER_MCUBOOT=y
+
+Sysbuild
+========
+
+The sysbuild makes possible to build and flash all necessary images needed to
+bootstrap the board with the ESP32 SoC.
+
+To build the sample application using sysbuild use the command:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s2_tft
+   :goals: build
+   :west-args: --sysbuild
+   :compact:
+
+By default, the ESP32 sysbuild creates bootloader (MCUboot) and application
+images. But it can be configured to create other kind of images.
+
+Build directory structure created by sysbuild is different from traditional
+Zephyr build. Output is structured by the domain subdirectories:
+
+.. code-block::
+
+   build/
+   ├── hello_world
+   │   └── zephyr
+   │       ├── zephyr.elf
+   │       └── zephyr.bin
+   ├── mcuboot
+   │    └── zephyr
+   │       ├── zephyr.elf
+   │       └── zephyr.bin
+   └── domains.yaml
+
+.. note::
+
+   With ``--sysbuild`` option the bootloader will be re-build and re-flash
+   every time the pristine build is used.
+
+For more information about the system build please read the :ref:`sysbuild` documentation.
+
+Manual build
+============
+
+During the development cycle, it is intended to build & flash as quickly possible.
+For that reason, images can be built one at a time using traditional build.
+
+The instructions following are relevant for both manual build and sysbuild.
+The only difference is the structure of the build directory.
+
+.. note::
+
+   Remember that bootloader (MCUboot) needs to be flash at least once.
+
+Build and flash applications as usual:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s2_tft
+   :goals: build
+
+The usual ``flash`` target will work. Here is an example for the :zephyr:code-sample:`hello_world`
+application.
+
+To enter ROM bootloader mode, hold down ``boot-button`` while clicking reset button.
+When in the ROM bootloader, you can upload code and query the chip using ``west flash``.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s2_tft
+   :goals: flash
+
+After the flashing you will receive most likely this Error:
+
+.. code-block:: console
+
+   WARNING: ESP32-S2FNR2 (revision v0.0) chip was placed into download mode using GPIO0.
+   esptool.py can not exit the download mode over USB. To run the app, reset the chip manually.
+   To suppress this note, set --after option to 'no_reset'.
+   FATAL ERROR: command exited with status 1: ...
+
+As stated in the Warning-Message ``esptool`` can't reset the board by itself and this message
+can be ignored and the board needs to be reseted via the Reset-Button manually.
+
+Open the serial monitor using the following command:
+
+.. code-block:: shell
+
+   west espressif monitor
+
+After the board has been manually reseted and booted, you should see the following
+message in the monitor:
+
+.. code-block:: console
+
+   ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
+   Hello World! adafruit_feather_esp32s2_tft
+
+Debugging
+*********
+
+ESP32-S2 support on OpenOCD is available at `OpenOCD`_.
+
+ESP32-S2 has a built-in JTAG circuitry and can be debugged without any
+additional chip. Only an USB cable connected to the D+/D- pins is necessary.
+
+Further documentation can be obtained from the SoC vendor
+in `JTAG debugging for ESP32-S2`_.
+
+You can debug an application in the usual way. Here is an example for
+the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s2_tft
+   :goals: debug
+
+Testing the On-Board-LED
+************************
+
+There is a sample available to verify that the LEDs on the board are
+functioning correctly with Zephyr:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: adafruit_feather_esp32s2_tft
+   :goals: build flash
+
+Testing the NeoPixel
+********************
+
+There is a sample available to verify that the NeoPixel on the board are
+functioning correctly with Zephyr:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/drivers/led/led_strip
+   :board: adafruit_feather_esp32s2_tft
+   :goals: build flash
+
+Testing the TFT
+***************
+
+.. note::
+   To activate the backlight of the display ``GPIO45`` (``backlight``) needs to be set to HIGH.
+   This will be done automatically via ``board_late_init_hook()``.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/subsys/display/lvgl
+   :board: adafruit_feather_esp32s2_tft
+   :goals: build flash
+
+Testing the Fuel Gauge (MAX17048)
+*********************************
+
+There is a sample available to verify that the MAX17048 fuel gauge on the board are
+functioning correctly with Zephyr:
+
+.. note::
+   As of May 31, 2023 Adafruit changed the battery monitor chip from the now-discontinued LC709203
+   to the MAX17048.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/fuel_gauge/max17048/
+   :board: adafruit_feather_esp32s2_tft
+   :goals: build flash
+
+Testing Wi-Fi
+*************
+
+There is a sample available to verify that the Wi-Fi on the board are
+functioning correctly with Zephyr:
+
+.. note::
+   The Prerequisites must be met before testing Wi-Fi.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/net/wifi/shell
+   :board: adafruit_feather_esp32s2_tft
+   :goals: build flash
+
+References
+**********
+
+.. target-notes::
+
+.. _`Adafruit ESP32-S2 TFT Feather`: https://www.adafruit.com/product/5300
+.. _`OpenOCD`: https://github.com/openocd-org/openocd
+.. _`ESP32 development overview`: https://github.com/zephyrproject-rtos/zephyr/issues/29394#issuecomment-2635037831
+.. _`Adafruit ESP32-S2 TFT Feather Pinouts`: https://learn.adafruit.com/adafruit-esp32-s2-tft-feather/pinouts
+.. _`Adafruit ESP32-S2 TFT Feather Schematic`: https://learn.adafruit.com/adafruit-esp32-s2-tft-feather/downloads
+.. _`SparkFun Qwiic`: https://www.sparkfun.com/qwiic
+.. _`STEMMA QT`: https://learn.adafruit.com/introducing-adafruit-stemma-qt
+.. _`JTAG debugging for ESP32-S2`: https://docs.espressif.com/projects/esp-idf/en/stable/esp32s2/api-guides/jtag-debugging/index.html
diff --git a/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft_reverse.rst b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft_reverse.rst
new file mode 100644
index 00000000000..fcbb6352205
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/doc/adafruit_feather_esp32s2_tft_reverse.rst
@@ -0,0 +1,293 @@
+.. zephyr:board:: adafruit_feather_esp32s2_tft_reverse
+
+Overview
+********
+
+The Adafruit Feather ESP32-S2 boards are ESP32-S2 development boards in the
+Feather standard layout, sharing peripheral placement with other devices labeled
+as Feathers or FeatherWings. The board is equipped with an ESP32-S2 mini module,
+a LiPo battery charger, a fuel gauge, a USB-C and `SparkFun Qwiic`_-compatible
+`STEMMA QT`_ connector for the I2C bus.
+
+Hardware
+********
+
+- ESP32-S2 mini module, featuring the 240MHz Tensilica processor
+- 320KB SRAM, 4MB flash + 2MB PSRAM
+- USB-C directly connected to the ESP32-S2 for USB
+- LiPo connector and built-in battery charging when powered via USB-C
+- LC709203 or MAX17048 fuel gauge for battery voltage and state-of-charge reporting
+- Charging indicator LED, user LED, reset and boot buttons and has 2 additional buttons.
+- Built-in NeoPixel indicator RGB LED
+- 240x135 pixel IPS TFT color display with 1.14" diagonal and ST7789 chipset.
+
+.. note::
+
+   - The board has a space for a BME280, but will not be shipped with.
+   - For the MAX17048 a driver in zephyr exists and is supported, but needs to be added via
+     a devicetree overlay.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+.. note::
+   USB-OTG is until now not supported see `ESP32 development overview`_. To see a serial output
+   a FTDI-USB-RS232 or similar needs to be connected to the RX/TX pins on the feather connector.
+
+Connections and IOs
+===================
+
+The `Adafruit ESP32-S2 Reverse TFT Feather`_ User Guide has detailed information about the board
+including pinouts and the schematic.
+
+- `Adafruit ESP32-S2 Reverse TFT Feather Pinouts`_
+- `Adafruit ESP32-S2 Reverse TFT Feather Schematic`_
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Prerequisites
+=============
+
+Espressif HAL requires WiFi binary blobs in order work. Run the command below
+to retrieve those files.
+
+.. code-block:: console
+
+   west update
+   west blobs fetch hal_espressif
+
+Building & Flashing
+*******************
+
+Simple boot
+===========
+
+The board could be loaded using the single binary image, without 2nd stage
+bootloader. It is the default option when building the application without
+additional configuration.
+
+.. note::
+
+   Simple boot does not provide any security features nor OTA updates.
+
+MCUboot bootloader
+==================
+
+User may choose to use MCUboot bootloader instead. In that case the bootloader
+must be built (and flashed) at least once.
+
+There are two options to be used when building an application:
+
+1. Sysbuild
+2. Manual build
+
+.. note::
+
+   User can select the MCUboot bootloader by adding the following line
+   to the board default configuration file.
+
+   .. code:: cfg
+
+      CONFIG_BOOTLOADER_MCUBOOT=y
+
+Sysbuild
+========
+
+The sysbuild makes possible to build and flash all necessary images needed to
+bootstrap the board with the ESP32 SoC.
+
+To build the sample application using sysbuild use the command:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s2_tft_reverse
+   :goals: build
+   :west-args: --sysbuild
+   :compact:
+
+By default, the ESP32 sysbuild creates bootloader (MCUboot) and application
+images. But it can be configured to create other kind of images.
+
+Build directory structure created by sysbuild is different from traditional
+Zephyr build. Output is structured by the domain subdirectories:
+
+.. code-block::
+
+   build/
+   ├── hello_world
+   │   └── zephyr
+   │       ├── zephyr.elf
+   │       └── zephyr.bin
+   ├── mcuboot
+   │    └── zephyr
+   │       ├── zephyr.elf
+   │       └── zephyr.bin
+   └── domains.yaml
+
+.. note::
+
+   With ``--sysbuild`` option the bootloader will be re-build and re-flash
+   every time the pristine build is used.
+
+For more information about the system build please read the :ref:`sysbuild` documentation.
+
+Manual build
+============
+
+During the development cycle, it is intended to build & flash as quickly possible.
+For that reason, images can be built one at a time using traditional build.
+
+The instructions following are relevant for both manual build and sysbuild.
+The only difference is the structure of the build directory.
+
+.. note::
+
+   Remember that bootloader (MCUboot) needs to be flash at least once.
+
+Build and flash applications as usual:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s2_tft_reverse
+   :goals: build
+
+The usual ``flash`` target will work. Here is an example for the :zephyr:code-sample:`hello_world`
+application.
+
+To enter ROM bootloader mode, hold down ``boot-button`` while clicking reset button.
+When in the ROM bootloader, you can upload code and query the chip using ``west flash``.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s2_tft_reverse
+   :goals: flash
+
+After the flashing you will receive most likely this Error:
+
+.. code-block:: console
+
+   WARNING: ESP32-S2FNR2 (revision v0.0) chip was placed into download mode using GPIO0.
+   esptool.py can not exit the download mode over USB. To run the app, reset the chip manually.
+   To suppress this note, set --after option to 'no_reset'.
+   FATAL ERROR: command exited with status 1: ...
+
+As stated in the Warning-Message ``esptool`` can't reset the board by itself and this message
+can be ignored and the board needs to be reseted via the Reset-Button manually.
+
+Open the serial monitor using the following command:
+
+.. code-block:: shell
+
+   west espressif monitor
+
+After the board has been manually reseted and booted, you should see the following
+message in the monitor:
+
+.. code-block:: console
+
+   ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
+   Hello World! adafruit_feather_esp32s2_tft_reverse
+
+Debugging
+*********
+
+ESP32-S2 support on OpenOCD is available at `OpenOCD`_.
+
+ESP32-S2 has a built-in JTAG circuitry and can be debugged without any
+additional chip. Only an USB cable connected to the D+/D- pins is necessary.
+
+Further documentation can be obtained from the SoC vendor
+in `JTAG debugging for ESP32-S2`_.
+
+You can debug an application in the usual way. Here is an example for
+the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s2_tft_reverse
+   :goals: debug
+
+Testing the On-Board-LED
+************************
+
+There is a sample available to verify that the LEDs on the board are
+functioning correctly with Zephyr:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: adafruit_feather_esp32s2_tft_reverse
+   :goals: build flash
+
+Testing the NeoPixel
+********************
+
+There is a sample available to verify that the NeoPixel on the board are
+functioning correctly with Zephyr:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/drivers/led/led_strip
+   :board: adafruit_feather_esp32s2_tft_reverse
+   :goals: build flash
+
+Testing the TFT
+***************
+
+There is a sample available to verify that the TFT on the board are
+functioning correctly with Zephyr:
+
+.. note::
+   To activated the backlight of the display ``GPIO45`` (``backlight``) needs to be set to HIGH.
+   This will be done automatically via ``board_late_init_hook()``.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/subsys/display/lvgl
+   :board: adafruit_feather_esp32s2_tft_reverse
+   :goals: build flash
+
+Testing the Fuel Gauge (MAX17048)
+*********************************
+
+There is a sample available to verify that the MAX17048 fuel gauge on the board are
+functioning correctly with Zephyr:
+
+.. note::
+   As of May 31, 2023 Adafruit changed the battery monitor chip from the now-discontinued LC709203
+   to the MAX17048.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/fuel_gauge/max17048/
+   :board: adafruit_feather_esp32s2_tft_reverse
+   :goals: build flash
+
+Testing Wi-Fi
+*************
+
+There is a sample available to verify that the Wi-Fi on the board are
+functioning correctly with Zephyr:
+
+.. note::
+   The Prerequisites must be met before testing Wi-Fi.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/net/wifi/shell
+   :board: adafruit_feather_esp32s2_tft_reverse
+   :goals: build flash
+
+References
+**********
+
+.. target-notes::
+
+.. _`Adafruit ESP32-S2 Reverse TFT Feather`: https://www.adafruit.com/product/5345
+.. _`OpenOCD`: https://github.com/openocd-org/openocd
+.. _`ESP32 development overview`: https://github.com/zephyrproject-rtos/zephyr/issues/29394#issuecomment-2635037831
+.. _`Adafruit ESP32-S2 Reverse TFT Feather Pinouts`: https://learn.adafruit.com/esp32-s2-reverse-tft-feather/pinouts
+.. _`Adafruit ESP32-S2 Reverse TFT Feather Schematic`: https://learn.adafruit.com/esp32-s2-reverse-tft-feather/downloads
+.. _`SparkFun Qwiic`: https://www.sparkfun.com/qwiic
+.. _`STEMMA QT`: https://learn.adafruit.com/introducing-adafruit-stemma-qt
+.. _`JTAG debugging for ESP32-S2`: https://docs.espressif.com/projects/esp-idf/en/stable/esp32s2/api-guides/jtag-debugging/index.html
diff --git a/boards/adafruit/feather_esp32s2/doc/img/adafruit_feather_esp32s2.webp b/boards/adafruit/feather_esp32s2/doc/img/adafruit_feather_esp32s2.webp
new file mode 100644
index 00000000000..b63d6c73977
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diff --git a/boards/adafruit/feather_esp32s2/doc/img/adafruit_feather_esp32s2_tft.webp b/boards/adafruit/feather_esp32s2/doc/img/adafruit_feather_esp32s2_tft.webp
new file mode 100644
index 00000000000..a1b9d091218
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diff --git a/boards/adafruit/feather_esp32s2/doc/img/adafruit_feather_esp32s2_tft_reverse.webp b/boards/adafruit/feather_esp32s2/doc/img/adafruit_feather_esp32s2_tft_reverse.webp
new file mode 100644
index 00000000000..8b607c89f85
Binary files /dev/null and b/boards/adafruit/feather_esp32s2/doc/img/adafruit_feather_esp32s2_tft_reverse.webp differ
diff --git a/boards/adafruit/feather_esp32s2/feather_connector.dtsi b/boards/adafruit/feather_esp32s2/feather_connector.dtsi
new file mode 100644
index 00000000000..8414fbbfb10
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/feather_connector.dtsi
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2020 Richard Osterloh <richard.osterloh@gmail.com>
+ * Copyright (c) 2024 Leon Rinkel <leon@rinkel.me>
+ * Copyright (c) 2025 Philipp Steiner <philipp.steiner@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	feather_header: connector {
+		compatible = "adafruit-feather-header";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map =
+			<0 0 &gpio0 18 0>,	/* A0 */
+			<1 0 &gpio0 17 0>,	/* A1 */
+			<2 0 &gpio0 16 0>,	/* A2 */
+			<3 0 &gpio0 15 0>,	/* A3 */
+			<4 0 &gpio0 14 0>,	/* A4 */
+			<5 0 &gpio0 8 0>,	/* A5 */
+			<6 0 &gpio1 36 0>,	/* SCK */
+			<7 0 &gpio1 35 0>,	/* MOSI */
+			<8 0 &gpio1 37 0>,	/* MISO */
+			<9 0 &gpio1 38 0>,	/* RX */
+			<10 0 &gpio1 39 0>,	/* TX */
+			<11 0 &gpio1 43 0>,	/* DB */
+			<12 0 &gpio1 3 0>,	/* SDA */
+			<13 0 &gpio1 4 0>,	/* SCL */
+			<14 0 &gpio0 5 0>,	/* D5 */
+			<15 0 &gpio0 6 0>,	/* D6 */
+			<16 0 &gpio0 9 0>,	/* D9 */
+			<17 0 &gpio0 10 0>,	/* D10 */
+			<18 0 &gpio0 11 0>,	/* D11 */
+			<19 0 &gpio0 12 0>,	/* D12 */
+			<20 0 &gpio0 13 0>;	/* D13 */
+	};
+};
+
+feather_serial: &uart1 {};
+feather_i2c: &i2c0 {};
+feather_spi: &spi2 {};
diff --git a/boards/adafruit/feather_esp32s2/feather_connector_tft.dtsi b/boards/adafruit/feather_esp32s2/feather_connector_tft.dtsi
new file mode 100644
index 00000000000..3a2eb8c3e0d
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/feather_connector_tft.dtsi
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2020 Richard Osterloh <richard.osterloh@gmail.com>
+ * Copyright (c) 2024 Leon Rinkel <leon@rinkel.me>
+ * Copyright (c) 2025 Philipp Steiner <philipp.steiner@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	feather_header: connector {
+		compatible = "adafruit-feather-header";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map =
+			<0 0 &gpio0 18 0>,	/* A0 */
+			<1 0 &gpio0 17 0>,	/* A1 */
+			<2 0 &gpio0 16 0>,	/* A2 */
+			<3 0 &gpio0 15 0>,	/* A3 */
+			<4 0 &gpio0 14 0>,	/* A4 */
+			<5 0 &gpio0 8 0>,	/* A5 */
+			<6 0 &gpio1 36 0>,	/* SCK */
+			<7 0 &gpio1 35 0>,	/* MOSI */
+			<8 0 &gpio1 37 0>,	/* MISO */
+			<9 0 &gpio0 2 0>,	/* RX */
+			<10 0 &gpio0 1 0>,	/* TX */
+			<11 0 &gpio1 43 0>,	/* DB */
+			<12 0 &gpio1 42 0>,	/* SDA */
+			<13 0 &gpio1 41 0>,	/* SCL */
+			<14 0 &gpio0 5 0>,	/* D5 */
+			<15 0 &gpio0 6 0>,	/* D6 */
+			<16 0 &gpio0 9 0>,	/* D9 */
+			<17 0 &gpio0 10 0>,	/* D10 */
+			<18 0 &gpio0 11 0>,	/* D11 */
+			<19 0 &gpio0 12 0>,	/* D12 */
+			<20 0 &gpio0 13 0>;	/* D13 */
+	};
+};
+
+feather_serial: &uart1 {};
+feather_i2c: &i2c0 {};
+feather_spi: &spi2 {};
diff --git a/boards/adafruit/feather_esp32s2/support/openocd.cfg b/boards/adafruit/feather_esp32s2/support/openocd.cfg
new file mode 100644
index 00000000000..2f740b4a36a
--- /dev/null
+++ b/boards/adafruit/feather_esp32s2/support/openocd.cfg
@@ -0,0 +1,7 @@
+set ESP_RTOS none
+set ESP32_ONLYCPU 1
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_jtag.cfg]
+# Source the ESP32-S3 configuration file
+source [find target/esp32s3.cfg]
diff --git a/boards/adafruit/feather_esp32s3/Kconfig b/boards/adafruit/feather_esp32s3/Kconfig
new file mode 100644
index 00000000000..e56e7f846c4
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3/Kconfig
@@ -0,0 +1,10 @@
+# Adafruit Feather ESP32-S3 board configuration
+
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# Copyright (c) 2024 Leon Rinkel <leon@rinkel.me>
+# SPDX-License-Identifier: Apache-2.0
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+	int
+	default 4096 if BOARD_ADAFRUIT_FEATHER_ESP32S3_ESP32S3_PROCPU
+	default 256 if BOARD_ADAFRUIT_FEATHER_ESP32S3_ESP32S3_APPCPU
diff --git a/boards/adafruit/feather_esp32s3/Kconfig.adafruit_feather_esp32s3 b/boards/adafruit/feather_esp32s3/Kconfig.adafruit_feather_esp32s3
new file mode 100644
index 00000000000..a96fe929308
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3/Kconfig.adafruit_feather_esp32s3
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# Copyright (c) 2024 Leon Rinkel <leon@rinkel.me>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ADAFRUIT_FEATHER_ESP32S3
+	select SOC_ESP32S3_WROOM_N8
+	select SOC_ESP32S3_PROCPU if BOARD_ADAFRUIT_FEATHER_ESP32S3_ESP32S3_PROCPU
+	select SOC_ESP32S3_APPCPU if BOARD_ADAFRUIT_FEATHER_ESP32S3_ESP32S3_APPCPU
diff --git a/boards/adafruit/feather_esp32s3/Kconfig.sysbuild b/boards/adafruit/feather_esp32s3/Kconfig.sysbuild
new file mode 100644
index 00000000000..8d3acb9e11d
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3/Kconfig.sysbuild
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+choice BOOTLOADER
+	default BOOTLOADER_MCUBOOT
+endchoice
+
+choice BOOT_SIGNATURE_TYPE
+	default BOOT_SIGNATURE_TYPE_NONE
+endchoice
diff --git a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3-pinctrl.dtsi b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3-pinctrl.dtsi
new file mode 100644
index 00000000000..dc41eaae541
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3-pinctrl.dtsi
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024 Leon Rinkel <leon@rinkel.me>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
+#include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h>
+
+&pinctrl {
+	uart0_default: uart0_default {
+		group1 {
+			pinmux = <UART0_TX_GPIO43>;
+			output-high;
+		};
+		group2 {
+			pinmux = <UART0_RX_GPIO44>;
+			bias-pull-up;
+		};
+	};
+
+	uart1_default: uart1_default {
+		group1 {
+			pinmux = <UART1_TX_GPIO39>;
+			output-high;
+		};
+		group2 {
+			pinmux = <UART1_RX_GPIO38>;
+			bias-pull-up;
+		};
+	};
+
+	i2c0_default: i2c0_default {
+		group1 {
+			pinmux = <I2C0_SDA_GPIO3>,
+				 <I2C0_SCL_GPIO4>;
+			drive-open-drain;
+			output-high;
+		};
+	};
+
+	spim2_default: spim2_default {
+		group1 {
+			pinmux = <SPIM2_MISO_GPIO37>,
+				 <SPIM2_SCLK_GPIO36>,
+				 <SPIM2_CSEL_GPIO10>;
+		};
+		group2 {
+			pinmux = <SPIM2_MOSI_GPIO35>;
+			output-low;
+		};
+	};
+
+	spim3_default: spim3_default {
+		group1 {
+			pinmux = <SPIM3_MOSI_GPIO33>;
+		};
+	};
+
+	twai_default: twai_default {
+		group1 {
+			pinmux = <TWAI_TX_GPIO5>,
+				 <TWAI_RX_GPIO6>;
+		};
+	};
+};
diff --git a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_appcpu.dts b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_appcpu.dts
new file mode 100644
index 00000000000..8b9f9953792
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_appcpu.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024 Leon Rinkel <leon@rinkel.me>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <espressif/esp32s3/esp32s3_wroom_n8.dtsi>
+#include <espressif/partitions_0x0_amp.dtsi>
+#include "adafruit_feather_esp32s3-pinctrl.dtsi"
+
+/ {
+	model = "Adafruit Feather ESP32S3 APPCPU";
+	compatible = "adafruit,feather_esp32s3", "espressif,esp32s3";
+
+	chosen {
+		zephyr,sram = &sram1;
+		zephyr,ipc_shm = &shm0;
+		zephyr,ipc = &ipm0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_appcpu_partition;
+	};
+};
+
+&trng0 {
+	status = "okay";
+};
+
+&ipm0 {
+	status = "okay";
+};
diff --git a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_appcpu.yaml b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_appcpu.yaml
new file mode 100644
index 00000000000..329bcd7fa92
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_appcpu.yaml
@@ -0,0 +1,27 @@
+identifier: adafruit_feather_esp32s3/esp32s3/appcpu
+name: Adafruit Feather ESP32-S3 APPCPU
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+supported:
+  - uart
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+    - flash
+    - cpp
+    - posix
+    - watchdog
+    - logging
+    - kernel
+    - pm
+    - gpio
+    - crypto
+    - eeprom
+    - heap
+    - cmsis_rtos
+    - jwt
+    - zdsp
+vendor: adafruit
diff --git a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_appcpu_defconfig b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_appcpu_defconfig
new file mode 100644
index 00000000000..9abf2ff0430
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_appcpu_defconfig
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MAIN_STACK_SIZE=2048
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts
new file mode 100644
index 00000000000..b745820ddaa
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.dts
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024 Leon Rinkel <leon@rinkel.me>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <espressif/esp32s3/esp32s3_wroom_n8.dtsi>
+#include <espressif/partitions_0x0_amp.dtsi>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/input/esp32-touch-sensor-input.h>
+#include <zephyr/dt-bindings/led/led.h>
+#include "feather_connector.dtsi"
+#include "adafruit_feather_esp32s3-pinctrl.dtsi"
+
+/ {
+	model = "Adafruit Feather ESP32S3 PROCPU";
+	compatible = "adafruit,feather_esp32s3", "espressif,esp32s3";
+
+	aliases {
+		i2c-0 = &i2c0;
+		watchdog0 = &wdt0;
+	};
+
+	chosen {
+		zephyr,sram = &sram1;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,bt-hci = &esp32_bt_hci;
+	};
+
+	/* These aliases are provided for compatibility with samples */
+	aliases {
+		uart-0 = &uart0;
+		sw0 = &button0;
+		led0 = &led0;
+		led-strip = &led_strip;
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+		button0: button_0 {
+			gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "BOOT Button";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led0: led_0 {
+			gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	/*
+	 * The neopixel on this board has its positive side hooked up to a GPIO
+	 * pin rather than a positive voltage rail to save on power.
+	 */
+	neopixel_pwr: neopixel_pwr {
+		compatible = "power-domain-gpio";
+		#power-domain-cells = <0>;
+		enable-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
+	};
+
+	/*
+	 * On-board regulator powers I2C pull-ups and external devices connected
+	 * via the STEMMA QT connector.
+	 */
+	i2c_reg: i2c_reg {
+		compatible = "power-domain-gpio";
+		#power-domain-cells = <0>;
+		enable-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&usb_serial {
+	status = "disabled";
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-names = "default";
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart1_default>;
+	pinctrl-names = "default";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&touch {
+	debounce-interval-ms = <30>;
+	href-microvolt = <2700000>;
+	lref-microvolt = <500000>;
+	href-atten-microvolt = <1000000>;
+	filter-mode = <ESP32_TOUCH_FILTER_MODE_IIR_16>;
+	filter-debounce-cnt = <1>;
+	filter-noise-thr = <ESP32_TOUCH_FILTER_NOISE_THR_4_8TH>;
+	filter-jitter-step = <4>;
+	filter-smooth-level = <ESP32_TOUCH_FILTER_SMOOTH_MODE_IIR_2>;
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+
+	max17048: max17048@36 {
+		compatible = "maxim,max17048";
+		status = "okay";
+		reg = <0x36>;
+
+		/*
+		 * The MAX17048 itself is directly powered by the battery, not
+		 * through the on-board regulator. However using this device
+		 * requires I2C pull-ups powered by the regulator.
+		 */
+		power-domains = <&i2c_reg>;
+	};
+};
+
+&spi2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	pinctrl-0 = <&spim2_default>;
+	pinctrl-names = "default";
+};
+
+&spi3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	pinctrl-0 = <&spim3_default>;
+	pinctrl-names = "default";
+
+	/* Workaround to support WS2812 driver */
+	line-idle-low;
+
+	led_strip: ws2812@0 {
+		compatible = "worldsemi,ws2812-spi";
+		power-domains = <&neopixel_pwr>;
+
+		/* SPI */
+		reg = <0>; /* ignored, but necessary for SPI bindings */
+		spi-max-frequency = <6400000>;
+
+		/* WS2812 */
+		chain-length = <1>;
+		spi-cpha;
+		spi-one-frame = <0xf0>;  /* 625 ns high and 625 ns low */
+		spi-zero-frame = <0xc0>; /* 312.5 ns high and 937.5 ns low */
+		color-mapping = <LED_COLOR_ID_GREEN
+				 LED_COLOR_ID_RED
+				 LED_COLOR_ID_BLUE>;
+	};
+};
+
+&twai {
+	pinctrl-0 = <&twai_default>;
+	pinctrl-names = "default";
+};
+
+&timer0 {
+	status = "disabled";
+};
+
+&timer1 {
+	status = "disabled";
+};
+
+&timer2 {
+	status = "disabled";
+};
+
+&timer3 {
+	status = "disabled";
+};
+
+&wdt0 {
+	status = "okay";
+};
+
+&trng0 {
+	status = "okay";
+};
+
+&esp32_bt_hci {
+	status = "okay";
+};
diff --git a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.yaml b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.yaml
new file mode 100644
index 00000000000..6ca1ba6ae3c
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu.yaml
@@ -0,0 +1,22 @@
+identifier: adafruit_feather_esp32s3/esp32s3/procpu
+name: Adafruit Feather ESP32-S3 PROCPU
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+supported:
+  - gpio
+  - uart
+  - i2c
+  - spi
+  - can
+  - counter
+  - watchdog
+  - entropy
+  - pwm
+  - dma
+  - input
+  - feather_serial
+  - feather_i2c
+  - feather_spi
+vendor: adafruit
diff --git a/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu_defconfig b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu_defconfig
new file mode 100644
index 00000000000..d789bab1824
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3/adafruit_feather_esp32s3_procpu_defconfig
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MAIN_STACK_SIZE=2048
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/adafruit/feather_esp32s3/board.cmake b/boards/adafruit/feather_esp32s3/board.cmake
new file mode 100644
index 00000000000..2f04d1fe886
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3/board.cmake
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
+  set(OPENOCD OPENOCD-NOTFOUND)
+endif()
+find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
+
+include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/adafruit/feather_esp32s3/board.yml b/boards/adafruit/feather_esp32s3/board.yml
new file mode 100644
index 00000000000..89db0bb116c
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: adafruit_feather_esp32s3
+  full_name: Adafruit Feather ESP32S3
+  vendor: adafruit
+  socs:
+  - name: esp32s3
diff --git a/boards/adafruit/feather_esp32s3/doc/img/adafruit_feather_esp32s3.webp b/boards/adafruit/feather_esp32s3/doc/img/adafruit_feather_esp32s3.webp
new file mode 100644
index 00000000000..5d6575dca11
Binary files /dev/null and b/boards/adafruit/feather_esp32s3/doc/img/adafruit_feather_esp32s3.webp differ
diff --git a/boards/adafruit/feather_esp32s3/doc/index.rst b/boards/adafruit/feather_esp32s3/doc/index.rst
new file mode 100644
index 00000000000..17332ba68fa
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3/doc/index.rst
@@ -0,0 +1,281 @@
+.. zephyr:board:: adafruit_feather_esp32s3
+
+Overview
+********
+
+The Adafruit Feather ESP32-S3 is an ESP32-S3 development board in the Feather
+standard layout, sharing peripheral placement with other devices labeled as
+Feathers or FeatherWings. The board is equipped with an ESP32-S3 mini module, a
+LiPo battery charger, a fuel gauge, a USB-C and Qwiic/STEMMA-QT connector. For
+more information, check `Adafruit Feather ESP32-S3`_.
+
+Hardware
+********
+
+- ESP32-S3 mini module, featuring the dual core 32-bit Xtensa Microprocessor
+  (Tensilica LX7), running at up to 240MHz
+- 512KB SRAM and either 8MB flash or 4MB flash + 2MB PSRAM, depending on the
+  module variant
+- USB-C directly connected to the ESP32-S3 for USB/UART and JTAG debugging
+- LiPo connector and built-in battery charging when powered via USB-C
+- MAX17048 fuel gauge for battery voltage and state-of-charge reporting
+- Charging indicator LED, user LED, reset and boot buttons
+- Built-in NeoPixel indicator RGB LED
+- STEMMA QT connector for I2C devices, with switchable power for low-power mode
+
+Asymmetric Multiprocessing (AMP)
+================================
+
+The ESP32-S3 SoC allows 2 different applications to be executed in asymmetric
+multiprocessing. Due to its dual-core architecture, each core can be enabled to
+execute customized tasks in stand-alone mode and/or exchanging data over OpenAMP
+framework. See :zephyr:code-sample-category:`ipc` folder as code reference.
+
+For more information, check the datasheet at `ESP32-S3 Datasheet`_.
+
+Supported Features
+==================
+
+The current ``adafruit_feather_esp32s3`` board supports the following hardware
+features:
+
++------------+------------+-------------------------------------+
+| Interface  | Controller | Driver/Component                    |
++============+============+=====================================+
+| UART       | on-chip    | serial port                         |
++------------+------------+-------------------------------------+
+| GPIO       | on-chip    | gpio                                |
++------------+------------+-------------------------------------+
+| PINMUX     | on-chip    | pinmux                              |
++------------+------------+-------------------------------------+
+| USB-JTAG   | on-chip    | hardware interface                  |
++------------+------------+-------------------------------------+
+| SPI Master | on-chip    | spi                                 |
++------------+------------+-------------------------------------+
+| TWAI/CAN   | on-chip    | can                                 |
++------------+------------+-------------------------------------+
+| ADC        | on-chip    | adc                                 |
++------------+------------+-------------------------------------+
+| Timers     | on-chip    | counter                             |
++------------+------------+-------------------------------------+
+| Watchdog   | on-chip    | watchdog                            |
++------------+------------+-------------------------------------+
+| TRNG       | on-chip    | entropy                             |
++------------+------------+-------------------------------------+
+| LEDC       | on-chip    | pwm                                 |
++------------+------------+-------------------------------------+
+| MCPWM      | on-chip    | pwm                                 |
++------------+------------+-------------------------------------+
+| PCNT       | on-chip    | qdec                                |
++------------+------------+-------------------------------------+
+| GDMA       | on-chip    | dma                                 |
++------------+------------+-------------------------------------+
+| USB-CDC    | on-chip    | serial                              |
++------------+------------+-------------------------------------+
+| Wi-Fi      | on-chip    |                                     |
++------------+------------+-------------------------------------+
+| Bluetooth  | on-chip    |                                     |
++------------+------------+-------------------------------------+
+
+Connections and IOs
+===================
+
+The `Adafruit Feather ESP32-S3 User Guide`_ has detailed information about the
+board including `pinouts`_ and the `schematic`_.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Prerequisites
+=============
+
+Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the
+command below to retrieve those files.
+
+.. code-block:: console
+
+   west blobs fetch hal_espressif
+
+.. note::
+
+   It is recommended running the command above after :file:`west update`.
+
+Building & Flashing
+===================
+
+Simple boot
+-----------
+
+The board could be loaded using the single binary image, without 2nd stage
+bootloader. It is the default option when building the application without
+additional configuration.
+
+.. note::
+
+   Simple boot does not provide any security features nor OTA updates.
+
+MCUboot bootloader
+------------------
+
+User may choose to use MCUboot bootloader instead. In that case the bootloader
+must be build (and flash) at least once.
+
+There are two options to be used when building an application:
+
+1. Sysbuild
+2. Manual build
+
+.. note::
+
+   User can select the MCUboot bootloader by adding the following line
+   to the board default configuration file.
+
+   .. code:: cfg
+
+      CONFIG_BOOTLOADER_MCUBOOT=y
+
+Sysbuild
+--------
+
+The sysbuild makes possible to build and flash all necessary images needed to
+bootstrap the board with the ESP32-S3 SoC.
+
+To build the sample application using sysbuild use the command:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s3/esp32s3/procpu
+   :goals: build
+   :west-args: --sysbuild
+   :compact:
+
+By default, the ESP32-S3 sysbuild creates bootloader (MCUboot) and application
+images. But it can be configured to create other kind of images.
+
+Build directory structure created by sysbuild is different from traditional
+Zephyr build. Output is structured by the domain subdirectories:
+
+.. code-block::
+
+  build/
+  ├── hello_world
+  │   └── zephyr
+  │       ├── zephyr.elf
+  │       └── zephyr.bin
+  ├── mcuboot
+  │    └── zephyr
+  │       ├── zephyr.elf
+  │       └── zephyr.bin
+  └── domains.yaml
+
+.. note::
+
+   With ``--sysbuild`` option the bootloader will be re-build and re-flash
+   every time the pristine build is used.
+
+For more information about the system build please read the :ref:`sysbuild`
+documentation.
+
+Manual build
+------------
+
+During the development cycle, it is intended to build & flash as quickly
+possible. For that reason, images can be build one at a time using traditional
+build.
+
+The instructions following are relevant for both manual build and sysbuild.
+The only difference is the structure of the build directory.
+
+.. note::
+
+   Remember that bootloader (MCUboot) needs to be flash at least once.
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s3/esp32s3/procpu
+   :goals: build
+
+The usual ``flash`` target will work with the ``adafruit_feather_esp32s3`` board
+. Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s3/esp32s3/procpu
+   :goals: flash
+
+Open the serial monitor using the following command:
+
+.. code-block:: shell
+
+   west espressif monitor
+
+After the board has automatically reset and booted, you should see the following
+message in the monitor:
+
+.. code-block:: console
+
+   ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
+   Hello World! adafruit_feather_esp32s3
+
+Debugging
+=========
+
+ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. Download
+and install OpenOCD from `OpenOCD`_.
+
+ESP32-S3 has a built-in JTAG circuitry and can be debugged without any
+additional chip. Only an USB cable connected to the D+/D- pins is necessary.
+
+Further documentation can be obtained from the SoC vendor in `JTAG debugging
+for ESP32-S3`_.
+
+Here is an example for building the :zephyr:code-sample:`hello_world`
+application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s3/esp32s3/procpu
+   :goals: build flash
+
+You can debug an application in the usual way. Here is an example for the
+:zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s3/esp32s3/procpu
+   :goals: debug
+
+References
+**********
+
+.. target-notes::
+
+.. _`Adafruit Feather ESP32-S3`:
+   https://www.adafruit.com/product/5323
+
+.. _`OpenOCD`:
+   https://github.com/openocd-org/openocd
+
+.. _`JTAG debugging for ESP32-S3`:
+   https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/
+
+.. _Adafruit Feather ESP32-S3 User Guide:
+   https://learn.adafruit.com/adafruit-esp32-s3-feather
+
+.. _pinouts:
+   https://learn.adafruit.com/adafruit-esp32-s3-feather/pinouts
+
+.. _schematic:
+   https://learn.adafruit.com/adafruit-esp32-s3-feather/downloads
+
+.. _ESP32-S3 Datasheet:
+   https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-1_wroom-1u_datasheet_en.pdf
+
+.. _ESP32 Technical Reference Manual:
+   https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf
diff --git a/boards/adafruit/feather_esp32s3/feather_connector.dtsi b/boards/adafruit/feather_esp32s3/feather_connector.dtsi
new file mode 100644
index 00000000000..49671be660c
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3/feather_connector.dtsi
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2020 Richard Osterloh <richard.osterloh@gmail.com>
+ * Copyright (c) 2024 Leon Rinkel <leon@rinkel.me>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	feather_header: connector {
+		compatible = "adafruit-feather-header";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpio0 18 0>,	/* A0 */
+			   <1 0 &gpio0 17 0>,	/* A1 */
+			   <2 0 &gpio0 16 0>,	/* A2 */
+			   <3 0 &gpio0 15 0>,	/* A3 */
+			   <4 0 &gpio0 14 0>,	/* A4 */
+			   <5 0 &gpio0 8 0>,	/* A5 */
+			   <6 0 &gpio1 36 0>,	/* SCK */
+			   <7 0 &gpio1 35 0>,	/* MOSI */
+			   <8 0 &gpio1 37 0>,	/* MISO */
+			   <9 0 &gpio1 38 0>,	/* RX */
+			   <10 0 &gpio1 39 0>,	/* TX */
+			   <11 0 &gpio1 44 0>,	/* DB */
+			   <12 0 &gpio0 3 0>,	/* SDA */
+			   <13 0 &gpio0 4 0>,	/* SCL */
+			   <14 0 &gpio0 5 0>,	/* D5 */
+			   <15 0 &gpio0 6 0>,	/* D6 */
+			   <16 0 &gpio0 9 0>,	/* D9 */
+			   <17 0 &gpio0 10 0>,	/* D10 */
+			   <18 0 &gpio0 11 0>,	/* D11 */
+			   <19 0 &gpio0 12 0>,	/* D12 */
+			   <20 0 &gpio0 13 0>;	/* D13 */
+	};
+};
+
+feather_serial: &uart1 {};
+feather_i2c: &i2c0 {};
+feather_spi: &spi2 {};
diff --git a/boards/adafruit/feather_esp32s3/support/openocd.cfg b/boards/adafruit/feather_esp32s3/support/openocd.cfg
new file mode 100644
index 00000000000..2f740b4a36a
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3/support/openocd.cfg
@@ -0,0 +1,7 @@
+set ESP_RTOS none
+set ESP32_ONLYCPU 1
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_jtag.cfg]
+# Source the ESP32-S3 configuration file
+source [find target/esp32s3.cfg]
diff --git a/boards/adafruit/feather_esp32s3_tft/CMakeLists.txt b/boards/adafruit/feather_esp32s3_tft/CMakeLists.txt
new file mode 100644
index 00000000000..218a0602483
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3_tft/CMakeLists.txt
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+zephyr_library_sources(board.c)
diff --git a/boards/adafruit/feather_esp32s3_tft/Kconfig b/boards/adafruit/feather_esp32s3_tft/Kconfig
new file mode 100644
index 00000000000..86f1012ae0d
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3_tft/Kconfig
@@ -0,0 +1,10 @@
+# Adafruit Feather ESP32S3 board configuration
+
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# Copyright (c) 2024 Leon Rinkel <leon@rinkel.me>
+# SPDX-License-Identifier: Apache-2.0
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+	int
+	default 4096 if BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_ESP32S3_PROCPU
+	default 256 if BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_ESP32S3_APPCPU
diff --git a/boards/adafruit/feather_esp32s3_tft/Kconfig.adafruit_feather_esp32s3_tft b/boards/adafruit/feather_esp32s3_tft/Kconfig.adafruit_feather_esp32s3_tft
new file mode 100644
index 00000000000..cd78387ff88
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3_tft/Kconfig.adafruit_feather_esp32s3_tft
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# Copyright (c) 2024 Leon Rinkel <leon@rinkel.me>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT
+	select SOC_ESP32S3_WROOM_N8
+	select SOC_ESP32S3_PROCPU if BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_ESP32S3_PROCPU
+	select SOC_ESP32S3_APPCPU if BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_ESP32S3_APPCPU
diff --git a/boards/adafruit/feather_esp32s3_tft/Kconfig.defconfig b/boards/adafruit/feather_esp32s3_tft/Kconfig.defconfig
new file mode 100644
index 00000000000..2c3e9c9cfa7
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3_tft/Kconfig.defconfig
@@ -0,0 +1,31 @@
+# Copyright (c) 2024 Leon Rinkel <leon@rinkel.me>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_ESP32S3_PROCPU
+
+if DISPLAY
+
+config BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT
+	select BOARD_LATE_INIT_HOOK
+
+choice ST7789V_PIXEL_FORMAT
+	default ST7789V_RGB565
+endchoice
+
+if LVGL
+
+config LV_Z_BITS_PER_PIXEL
+	default 16
+
+choice LV_COLOR_DEPTH
+	default LV_COLOR_DEPTH_16
+endchoice
+
+config LV_COLOR_16_SWAP
+	default y
+
+endif # LVGL
+
+endif # DISPLAY
+
+endif # BOARD_ADAFRUIT_FEATHER_ESP32S3_TFT_PROCPU
diff --git a/boards/adafruit/feather_esp32s3_tft/Kconfig.sysbuild b/boards/adafruit/feather_esp32s3_tft/Kconfig.sysbuild
new file mode 100644
index 00000000000..8d3acb9e11d
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3_tft/Kconfig.sysbuild
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+choice BOOTLOADER
+	default BOOTLOADER_MCUBOOT
+endchoice
+
+choice BOOT_SIGNATURE_TYPE
+	default BOOT_SIGNATURE_TYPE_NONE
+endchoice
diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft-pinctrl.dtsi b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft-pinctrl.dtsi
new file mode 100644
index 00000000000..0cf040eeb87
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft-pinctrl.dtsi
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024 Leon Rinkel <leon@rinkel.me>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
+#include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h>
+
+&pinctrl {
+	uart0_default: uart0_default {
+		group1 {
+			pinmux = <UART0_TX_GPIO43>;
+			output-high;
+		};
+		group2 {
+			pinmux = <UART0_RX_GPIO44>;
+			bias-pull-up;
+		};
+	};
+
+	uart1_default: uart1_default {
+		group1 {
+			pinmux = <UART1_TX_GPIO1>;
+			output-high;
+		};
+		group2 {
+			pinmux = <UART1_RX_GPIO2>;
+			bias-pull-up;
+		};
+	};
+
+	i2c0_default: i2c0_default {
+		group1 {
+			pinmux = <I2C0_SDA_GPIO42>,
+				 <I2C0_SCL_GPIO41>;
+			drive-open-drain;
+			output-high;
+		};
+	};
+
+	spim2_default: spim2_default {
+		group1 {
+			pinmux = <SPIM2_MISO_GPIO37>,
+				 <SPIM2_SCLK_GPIO36>,
+				 <SPIM2_CSEL_GPIO7>;
+		};
+		group2 {
+			pinmux = <SPIM2_MOSI_GPIO35>;
+			output-low;
+		};
+	};
+
+	spim3_default: spim3_default {
+		group1 {
+			pinmux = <SPIM3_MOSI_GPIO33>;
+		};
+	};
+
+	twai_default: twai_default {
+		group1 {
+			pinmux = <TWAI_TX_GPIO5>,
+				 <TWAI_RX_GPIO6>;
+		};
+	};
+};
diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu.dts b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu.dts
new file mode 100644
index 00000000000..f4662f4b0a3
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu.dts
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024 Leon Rinkel <leon@rinkel.me>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <espressif/esp32s3/esp32s3_wroom_n8.dtsi>
+#include <espressif/partitions_0x0_amp.dtsi>
+#include "adafruit_feather_esp32s3_tft-pinctrl.dtsi"
+
+/ {
+	model = "Adafruit Feather ESP32S3 TFT APPCPU";
+	compatible = "adafruit,feather_esp32s3_tft", "espressif,esp32s3";
+
+	chosen {
+		zephyr,sram = &sram1;
+		zephyr,ipc_shm = &shm0;
+		zephyr,ipc = &ipm0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_appcpu_partition;
+	};
+};
+
+&trng0 {
+	status = "okay";
+};
+
+&ipm0 {
+	status = "okay";
+};
diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu.yaml b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu.yaml
new file mode 100644
index 00000000000..baed9f8ff70
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu.yaml
@@ -0,0 +1,27 @@
+identifier: adafruit_feather_esp32s3_tft/esp32s3/appcpu
+name: Adafruit Feather ESP32-S3 TFT APPCPU
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+supported:
+  - uart
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+    - flash
+    - cpp
+    - posix
+    - watchdog
+    - logging
+    - kernel
+    - pm
+    - gpio
+    - crypto
+    - eeprom
+    - heap
+    - cmsis_rtos
+    - jwt
+    - zdsp
+vendor: adafruit
diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu_defconfig b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu_defconfig
new file mode 100644
index 00000000000..9abf2ff0430
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_appcpu_defconfig
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MAIN_STACK_SIZE=2048
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts
new file mode 100644
index 00000000000..b09b6262aa1
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.dts
@@ -0,0 +1,253 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024 Leon Rinkel <leon@rinkel.me>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <espressif/esp32s3/esp32s3_wroom_n8.dtsi>
+#include <espressif/partitions_0x0_amp.dtsi>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/input/esp32-touch-sensor-input.h>
+#include <zephyr/dt-bindings/led/led.h>
+#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
+#include "feather_connector.dtsi"
+#include "adafruit_feather_esp32s3_tft-pinctrl.dtsi"
+
+/ {
+	model = "Adafruit Feather ESP32S3 TFT PROCPU";
+	compatible = "adafruit,feather_esp32s3_tft", "espressif,esp32s3";
+
+	aliases {
+		i2c-0 = &i2c0;
+		watchdog0 = &wdt0;
+	};
+
+	chosen {
+		zephyr,sram = &sram1;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,bt-hci = &esp32_bt_hci;
+		zephyr,display = &st7789v_tft;
+	};
+
+	/* These aliases are provided for compatibility with samples */
+	aliases {
+		uart-0 = &uart0;
+		sw0 = &button0;
+		led0 = &led0;
+		led-strip = &led_strip;
+		backlight = &led1;
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+		button0: button_0 {
+			gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "BOOT Button";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led0: led_0 {
+			gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+		};
+		led1: led_1 {
+			gpios = <&gpio1 45 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	/*
+	 * The neopixel on this board has its positive side hooked up to a GPIO
+	 * pin rather than a positive voltage rail to save on power.
+	 */
+	neopixel_pwr: neopixel_pwr {
+		compatible = "power-domain-gpio";
+		#power-domain-cells = <0>;
+		enable-gpios = <&gpio1 34 GPIO_ACTIVE_HIGH>;
+	};
+
+	/*
+	 * On-board regulator powers I2C pull-ups and external devices connected
+	 * via the STEMMA QT connector.
+	 */
+	i2c_reg: i2c_reg {
+		compatible = "power-domain-gpio";
+		#power-domain-cells = <0>;
+		enable-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>;
+	};
+
+	mipi_dbi {
+		compatible = "zephyr,mipi-dbi-spi";
+		spi-dev = <&spi2>;
+		dc-gpios = <&gpio1 39 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio1 40 GPIO_ACTIVE_LOW>;
+		write-only;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		st7789v_tft: st7789v_tft@0 {
+			compatible = "sitronix,st7789v";
+			status = "disabled";
+
+			/* Also powered by i2c_reg */
+			power-domains = <&i2c_reg>;
+
+			mipi-max-frequency = <DT_FREQ_M(20)>;
+			reg = <0>;
+			width = <135>;
+			height = <240>;
+			x-offset = <52>;
+			y-offset = <40>;
+			vcom = <0x20>;
+			gctrl = <0x35>;
+			vrhs = <0x0b>;
+			vdvs = <0x20>;
+			mdac = <0x08>;
+			gamma = <0x01>;
+			colmod = <0x55>;
+			lcm = <0x2c>;
+			porch-param = [0c 0c 00 33 33];
+			cmd2en-param = [5a 69 02 01];
+			pwctrl1-param = [a4 a1];
+			pvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25];
+			nvgam-param = [70 2C 2E 15 10 09 48 33 53 0B 19 18 20 25];
+			ram-param = [00 F0];
+			rgb-param = [40 02 14];
+			mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE";
+		};
+	};
+};
+
+&usb_serial {
+	status = "disabled";
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-names = "default";
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart1_default>;
+	pinctrl-names = "default";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&touch {
+	debounce-interval-ms = <30>;
+	href-microvolt = <2700000>;
+	lref-microvolt = <500000>;
+	href-atten-microvolt = <1000000>;
+	filter-mode = <ESP32_TOUCH_FILTER_MODE_IIR_16>;
+	filter-debounce-cnt = <1>;
+	filter-noise-thr = <ESP32_TOUCH_FILTER_NOISE_THR_4_8TH>;
+	filter-jitter-step = <4>;
+	filter-smooth-level = <ESP32_TOUCH_FILTER_SMOOTH_MODE_IIR_2>;
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+
+	max17048: max17048@36 {
+		compatible = "maxim,max17048";
+		status = "okay";
+		reg = <0x36>;
+
+		/*
+		 * The MAX17048 itself is directly powered by the battery, not
+		 * through the on-board regulator. However using this device
+		 * requires I2C pull-ups powered by the regulator.
+		 */
+		power-domains = <&i2c_reg>;
+	};
+};
+
+&spi2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	pinctrl-0 = <&spim2_default>;
+	pinctrl-names = "default";
+};
+
+&spi3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	pinctrl-0 = <&spim3_default>;
+	pinctrl-names = "default";
+
+	/* Workaround to support WS2812 driver */
+	line-idle-low;
+
+	led_strip: ws2812@0 {
+		compatible = "worldsemi,ws2812-spi";
+		power-domains = <&neopixel_pwr>;
+
+		/* SPI */
+		reg = <0>; /* ignored, but necessary for SPI bindings */
+		spi-max-frequency = <6400000>;
+
+		/* WS2812 */
+		chain-length = <1>;
+		spi-cpha;
+		spi-one-frame = <0xf0>;  /* 625 ns high and 625 ns low */
+		spi-zero-frame = <0xc0>; /* 312.5 ns high and 937.5 ns low */
+		color-mapping = <LED_COLOR_ID_GREEN
+				 LED_COLOR_ID_RED
+				 LED_COLOR_ID_BLUE>;
+	};
+};
+
+&twai {
+	pinctrl-0 = <&twai_default>;
+	pinctrl-names = "default";
+};
+
+&timer0 {
+	status = "disabled";
+};
+
+&timer1 {
+	status = "disabled";
+};
+
+&timer2 {
+	status = "disabled";
+};
+
+&timer3 {
+	status = "disabled";
+};
+
+&wdt0 {
+	status = "okay";
+};
+
+&trng0 {
+	status = "okay";
+};
+
+&esp32_bt_hci {
+	status = "okay";
+};
diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.yaml b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.yaml
new file mode 100644
index 00000000000..bed1ac8ba70
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu.yaml
@@ -0,0 +1,23 @@
+identifier: adafruit_feather_esp32s3_tft/esp32s3/procpu
+name: Adafruit Feather ESP32-S3 TFT PROCPU
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+supported:
+  - gpio
+  - uart
+  - i2c
+  - spi
+  - can
+  - counter
+  - watchdog
+  - entropy
+  - pwm
+  - dma
+  - input
+  - feather_serial
+  - feather_i2c
+  - feather_spi
+  - display
+vendor: adafruit
diff --git a/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu_defconfig b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu_defconfig
new file mode 100644
index 00000000000..d789bab1824
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3_tft/adafruit_feather_esp32s3_tft_procpu_defconfig
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MAIN_STACK_SIZE=2048
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/adafruit/feather_esp32s3_tft/board.c b/boards/adafruit/feather_esp32s3_tft/board.c
new file mode 100644
index 00000000000..88aa3b0b354
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3_tft/board.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2024 Leon Rinkel <leon@rinkel.me>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Automatically turns on backlight if display is configured, i.e. display DT
+ * node has status okay.
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/init.h>
+
+#define DISPLAY_NODE DT_CHOSEN(zephyr_display)
+
+#if DT_NODE_HAS_STATUS(DISPLAY_NODE, okay)
+static const struct gpio_dt_spec backlight = GPIO_DT_SPEC_GET(DT_ALIAS(backlight), gpios);
+#endif
+
+void board_late_init_hook(void)
+{
+#if DT_NODE_HAS_STATUS(DISPLAY_NODE, okay)
+	if (gpio_is_ready_dt(&backlight)) {
+		gpio_pin_configure_dt(&backlight, GPIO_OUTPUT_ACTIVE);
+	}
+#endif
+}
diff --git a/boards/adafruit/feather_esp32s3_tft/board.cmake b/boards/adafruit/feather_esp32s3_tft/board.cmake
new file mode 100644
index 00000000000..2f04d1fe886
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3_tft/board.cmake
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
+  set(OPENOCD OPENOCD-NOTFOUND)
+endif()
+find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
+
+include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/adafruit/feather_esp32s3_tft/board.yml b/boards/adafruit/feather_esp32s3_tft/board.yml
new file mode 100644
index 00000000000..86f7b9293c8
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3_tft/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: adafruit_feather_esp32s3_tft
+  full_name: Adafruit Feather ESP32S3 TFT
+  vendor: adafruit
+  socs:
+  - name: esp32s3
diff --git a/boards/adafruit/feather_esp32s3_tft/doc/img/adafruit_feather_esp32s3_tft.webp b/boards/adafruit/feather_esp32s3_tft/doc/img/adafruit_feather_esp32s3_tft.webp
new file mode 100644
index 00000000000..796170908e7
Binary files /dev/null and b/boards/adafruit/feather_esp32s3_tft/doc/img/adafruit_feather_esp32s3_tft.webp differ
diff --git a/boards/adafruit/feather_esp32s3_tft/doc/index.rst b/boards/adafruit/feather_esp32s3_tft/doc/index.rst
new file mode 100644
index 00000000000..f46daa99688
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3_tft/doc/index.rst
@@ -0,0 +1,284 @@
+.. zephyr:board:: adafruit_feather_esp32s3_tft
+
+Overview
+********
+
+The Adafruit Feather ESP32-S3 TFT is an ESP32-S3 development board in the
+Feather standard layout, sharing peripheral placement with other devices labeled
+as Feathers or FeatherWings. The board is equipped with an ESP32-S3 mini module,
+a LiPo battery charger, a fuel gauge, a USB-C and Qwiic/STEMMA-QT connector.
+Compared to the base model, this TFT variant additionally comes with a 240x135
+pixel IPS TFT color display. For more information, check
+`Adafruit Feather ESP32-S3 TFT`_.
+
+Hardware
+********
+
+- ESP32-S3 mini module, featuring the dual core 32-bit Xtensa Microprocessor
+  (Tensilica LX7), running at up to 240MHz
+- 512KB SRAM and either 8MB flash or 4MB flash + 2MB PSRAM, depending on the
+  module variant
+- USB-C directly connected to the ESP32-S3 for USB/UART and JTAG debugging
+- LiPo connector and built-in battery charging when powered via USB-C
+- MAX17048 fuel gauge for battery voltage and state-of-charge reporting
+- Charging indicator LED, user LED, reset and boot buttons
+- Built-in NeoPixel indicator RGB LED
+- STEMMA QT connector for I2C devices, with switchable power for low-power mode
+- 240x135 pixel IPS TFT color display with 1.14" diagonal and ST7789 chipset
+
+Asymmetric Multiprocessing (AMP)
+================================
+
+The ESP32-S3 SoC allows 2 different applications to be executed in asymmetric
+multiprocessing. Due to its dual-core architecture, each core can be enabled to
+execute customized tasks in stand-alone mode and/or exchanging data over OpenAMP
+framework. See :zephyr:code-sample-category:`ipc` folder as code reference.
+
+For more information, check the datasheet at `ESP32-S3 Datasheet`_.
+
+Supported Features
+==================
+
+The current ``adafruit_feather_esp32s3_tft`` board supports the following
+hardware features:
+
++------------+------------+-------------------------------------+
+| Interface  | Controller | Driver/Component                    |
++============+============+=====================================+
+| UART       | on-chip    | serial port                         |
++------------+------------+-------------------------------------+
+| GPIO       | on-chip    | gpio                                |
++------------+------------+-------------------------------------+
+| PINMUX     | on-chip    | pinmux                              |
++------------+------------+-------------------------------------+
+| USB-JTAG   | on-chip    | hardware interface                  |
++------------+------------+-------------------------------------+
+| SPI Master | on-chip    | spi                                 |
++------------+------------+-------------------------------------+
+| TWAI/CAN   | on-chip    | can                                 |
++------------+------------+-------------------------------------+
+| ADC        | on-chip    | adc                                 |
++------------+------------+-------------------------------------+
+| Timers     | on-chip    | counter                             |
++------------+------------+-------------------------------------+
+| Watchdog   | on-chip    | watchdog                            |
++------------+------------+-------------------------------------+
+| TRNG       | on-chip    | entropy                             |
++------------+------------+-------------------------------------+
+| LEDC       | on-chip    | pwm                                 |
++------------+------------+-------------------------------------+
+| MCPWM      | on-chip    | pwm                                 |
++------------+------------+-------------------------------------+
+| PCNT       | on-chip    | qdec                                |
++------------+------------+-------------------------------------+
+| GDMA       | on-chip    | dma                                 |
++------------+------------+-------------------------------------+
+| USB-CDC    | on-chip    | serial                              |
++------------+------------+-------------------------------------+
+| Wi-Fi      | on-chip    |                                     |
++------------+------------+-------------------------------------+
+| Bluetooth  | on-chip    |                                     |
++------------+------------+-------------------------------------+
+
+Connections and IOs
+===================
+
+The `Adafruit Feather ESP32-S3 TFT User Guide`_ has detailed information about
+the board including `pinouts`_ and the `schematic`_.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Prerequisites
+=============
+
+Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the
+command below to retrieve those files.
+
+.. code-block:: console
+
+   west blobs fetch hal_espressif
+
+.. note::
+
+   It is recommended running the command above after :file:`west update`.
+
+Building & Flashing
+===================
+
+Simple boot
+-----------
+
+The board could be loaded using the single binary image, without 2nd stage
+bootloader. It is the default option when building the application without
+additional configuration.
+
+.. note::
+
+   Simple boot does not provide any security features nor OTA updates.
+
+MCUboot bootloader
+------------------
+
+User may choose to use MCUboot bootloader instead. In that case the bootloader
+must be build (and flash) at least once.
+
+There are two options to be used when building an application:
+
+1. Sysbuild
+2. Manual build
+
+.. note::
+
+   User can select the MCUboot bootloader by adding the following line
+   to the board default configuration file.
+
+   .. code:: cfg
+
+      CONFIG_BOOTLOADER_MCUBOOT=y
+
+Sysbuild
+--------
+
+The sysbuild makes possible to build and flash all necessary images needed to
+bootstrap the board with the ESP32-S3 SoC.
+
+To build the sample application using sysbuild use the command:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s3_tft/esp32s3/procpu
+   :goals: build
+   :west-args: --sysbuild
+   :compact:
+
+By default, the ESP32-S3 sysbuild creates bootloader (MCUboot) and application
+images. But it can be configured to create other kind of images.
+
+Build directory structure created by sysbuild is different from traditional
+Zephyr build. Output is structured by the domain subdirectories:
+
+.. code-block::
+
+  build/
+  ├── hello_world
+  │   └── zephyr
+  │       ├── zephyr.elf
+  │       └── zephyr.bin
+  ├── mcuboot
+  │    └── zephyr
+  │       ├── zephyr.elf
+  │       └── zephyr.bin
+  └── domains.yaml
+
+.. note::
+
+   With ``--sysbuild`` option the bootloader will be re-build and re-flash
+   every time the pristine build is used.
+
+For more information about the system build please read the :ref:`sysbuild`
+documentation.
+
+Manual build
+------------
+
+During the development cycle, it is intended to build & flash as quickly
+possible. For that reason, images can be build one at a time using traditional
+build.
+
+The instructions following are relevant for both manual build and sysbuild.
+The only difference is the structure of the build directory.
+
+.. note::
+
+   Remember that bootloader (MCUboot) needs to be flash at least once.
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s3_tft/esp32s3/procpu
+   :goals: build
+
+The usual ``flash`` target will work with the ``adafruit_feather_esp32s3_tft``
+board. Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s3_tft/esp32s3/procpu
+   :goals: flash
+
+Open the serial monitor using the following command:
+
+.. code-block:: shell
+
+   west espressif monitor
+
+After the board has automatically reset and booted, you should see the following
+message in the monitor:
+
+.. code-block:: console
+
+   ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
+   Hello World! adafruit_feather_esp32s3_tft
+
+Debugging
+=========
+
+ESP32-S3 support on OpenOCD is available upstream as of version 0.12.0. Download
+and install OpenOCD from `OpenOCD`_.
+
+ESP32-S3 has a built-in JTAG circuitry and can be debugged without any
+additional chip. Only an USB cable connected to the D+/D- pins is necessary.
+
+Further documentation can be obtained from the SoC vendor in `JTAG debugging
+for ESP32-S3`_.
+
+Here is an example for building the :zephyr:code-sample:`hello_world`
+application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s3_tft/esp32s3/procpu
+   :goals: build flash
+
+You can debug an application in the usual way. Here is an example for the
+:zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: adafruit_feather_esp32s3_tft/esp32s3/procpu
+   :goals: debug
+
+References
+**********
+
+.. target-notes::
+
+.. _`Adafruit Feather ESP32-S3 TFT`:
+   https://www.adafruit.com/product/5483
+
+.. _`OpenOCD`:
+   https://github.com/openocd-org/openocd
+
+.. _`JTAG debugging for ESP32-S3`:
+   https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/
+
+.. _Adafruit Feather ESP32-S3 TFT User Guide:
+   https://learn.adafruit.com/adafruit-esp32-s3-tft-feather
+
+.. _pinouts:
+   https://learn.adafruit.com/adafruit-esp32-s3-tft-feather/pinouts
+
+.. _schematic:
+   https://learn.adafruit.com/adafruit-esp32-s3-tft-feather/downloads
+
+.. _ESP32-S3 Datasheet:
+   https://www.espressif.com/sites/default/files/documentation/esp32-s3-wroom-1_wroom-1u_datasheet_en.pdf
+
+.. _ESP32 Technical Reference Manual:
+   https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf
diff --git a/boards/adafruit/feather_esp32s3_tft/feather_connector.dtsi b/boards/adafruit/feather_esp32s3_tft/feather_connector.dtsi
new file mode 100644
index 00000000000..9a4dd731e8c
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3_tft/feather_connector.dtsi
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2020 Richard Osterloh <richard.osterloh@gmail.com>
+ * Copyright (c) 2024 Leon Rinkel <leon@rinkel.me>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	feather_header: connector {
+		compatible = "adafruit-feather-header";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpio0 18 0>,	/* A0 */
+			   <1 0 &gpio0 17 0>,	/* A1 */
+			   <2 0 &gpio0 16 0>,	/* A2 */
+			   <3 0 &gpio0 15 0>,	/* A3 */
+			   <4 0 &gpio0 14 0>,	/* A4 */
+			   <5 0 &gpio0 8 0>,	/* A5 */
+			   <6 0 &gpio1 36 0>,	/* SCK */
+			   <7 0 &gpio1 35 0>,	/* MOSI */
+			   <8 0 &gpio1 37 0>,	/* MISO */
+			   <9 0 &gpio0 2 0>,	/* RX */
+			   <10 0 &gpio0 1 0>,	/* TX */
+			   <11 0 &gpio1 44 0>,	/* DB */
+			   <12 0 &gpio1 42 0>,	/* SDA */
+			   <13 0 &gpio1 41 0>,	/* SCL */
+			   <14 0 &gpio0 5 0>,	/* D5 */
+			   <15 0 &gpio0 6 0>,	/* D6 */
+			   <16 0 &gpio0 9 0>,	/* D9 */
+			   <17 0 &gpio0 10 0>,	/* D10 */
+			   <18 0 &gpio0 11 0>,	/* D11 */
+			   <19 0 &gpio0 12 0>,	/* D12 */
+			   <20 0 &gpio0 13 0>;	/* D13 */
+	};
+};
+
+feather_serial: &uart1 {};
+feather_i2c: &i2c0 {};
+feather_spi: &spi2 {};
diff --git a/boards/adafruit/feather_esp32s3_tft/support/openocd.cfg b/boards/adafruit/feather_esp32s3_tft/support/openocd.cfg
new file mode 100644
index 00000000000..2f740b4a36a
--- /dev/null
+++ b/boards/adafruit/feather_esp32s3_tft/support/openocd.cfg
@@ -0,0 +1,7 @@
+set ESP_RTOS none
+set ESP32_ONLYCPU 1
+
+# Source the JTAG interface configuration file
+source [find interface/esp_usb_jtag.cfg]
+# Source the ESP32-S3 configuration file
+source [find target/esp32s3.cfg]
diff --git a/boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto.yaml b/boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto.yaml
index 859ae9feb17..e8777b1a070 100644
--- a/boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto.yaml
+++ b/boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto.yaml
@@ -7,5 +7,4 @@ flash: 232
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 vendor: adafruit
diff --git a/boards/adafruit/feather_m0_basic_proto/doc/index.rst b/boards/adafruit/feather_m0_basic_proto/doc/index.rst
index 20d1cd4750a..69abd4bb9ac 100644
--- a/boards/adafruit/feather_m0_basic_proto/doc/index.rst
+++ b/boards/adafruit/feather_m0_basic_proto/doc/index.rst
@@ -23,35 +23,7 @@ Hardware
 Supported Features
 ==================
 
-The adafruit_feather_m0_basic_proto board configuration supports the
-following hardware features:
-
-+-----------+------------+------------------------------------------+
-| Interface | Controller | Driver/Component                         |
-+===========+============+==========================================+
-| NVIC      | on-chip    | Nested vector interrupt controller       |
-+-----------+------------+------------------------------------------+
-| Flash     | on-chip    | Can be used with LittleFS to store files |
-+-----------+------------+------------------------------------------+
-| SYSTICK   | on-chip    | Systick                                  |
-+-----------+------------+------------------------------------------+
-| WDT       | on-chip    | Watchdog                                 |
-+-----------+------------+------------------------------------------+
-| GPIO      | on-chip    | I/O ports                                |
-+-----------+------------+------------------------------------------+
-| USART     | on-chip    | Serial port                              |
-+-----------+------------+------------------------------------------+
-| I2C       | on-chip    | Inter-Integrated Circuit                 |
-+-----------+------------+------------------------------------------+
-| SPI       | on-chip    | Serial Peripheral Interface port         |
-+-----------+------------+------------------------------------------+
-| USB       | on-chip    | USB device                               |
-+-----------+------------+------------------------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig file
-:zephyr_file:`boards/adafruit/feather_m0_basic_proto/adafruit_feather_m0_basic_proto_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -96,6 +68,8 @@ serial port that echos characters back to the host PC.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The Adafruit Feather M0 Basic Proto ships with a BOSSA compatible
 SAM-BA bootloader.  The bootloader can be entered by quickly tapping
 the reset button twice.
diff --git a/boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora.yaml b/boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora.yaml
index de9b44f8820..a448a5e177b 100644
--- a/boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora.yaml
+++ b/boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora.yaml
@@ -7,5 +7,4 @@ flash: 232
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 vendor: adafruit
diff --git a/boards/adafruit/feather_m0_lora/doc/index.rst b/boards/adafruit/feather_m0_lora/doc/index.rst
index 7a3e9fc78bf..1e85f48b1f5 100644
--- a/boards/adafruit/feather_m0_lora/doc/index.rst
+++ b/boards/adafruit/feather_m0_lora/doc/index.rst
@@ -24,37 +24,7 @@ Hardware
 Supported Features
 ==================
 
-The adafruit_feather_m0_lora board configuration supports the
-following hardware features:
-
-+-----------+------------+------------------------------------------+
-| Interface | Controller | Driver/Component                         |
-+===========+============+==========================================+
-| NVIC      | on-chip    | Nested vector interrupt controller       |
-+-----------+------------+------------------------------------------+
-| Flash     | on-chip    | Can be used with LittleFS to store files |
-+-----------+------------+------------------------------------------+
-| SYSTICK   | on-chip    | Systick                                  |
-+-----------+------------+------------------------------------------+
-| WDT       | on-chip    | Watchdog                                 |
-+-----------+------------+------------------------------------------+
-| GPIO      | on-chip    | I/O ports                                |
-+-----------+------------+------------------------------------------+
-| USART     | on-chip    | Serial port                              |
-+-----------+------------+------------------------------------------+
-| I2C       | on-chip    | Inter-Integrated Circuit                 |
-+-----------+------------+------------------------------------------+
-| SPI       | on-chip    | Serial Peripheral Interface port         |
-+-----------+------------+------------------------------------------+
-| USB       | on-chip    | USB device                               |
-+-----------+------------+------------------------------------------+
-| RADIO     | SPI        | LoRa radio                               |
-+-----------+------------+------------------------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig file
-:zephyr_file:`boards/adafruit/feather_m0_lora/adafruit_feather_m0_lora_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -105,6 +75,8 @@ version, 433MHz or 900MHz is supported.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The Adafruit Feather M0 with LoRa ships with a BOSSA compatible
 SAM-BA bootloader.  The bootloader can be entered by quickly tapping
 the reset button twice.
diff --git a/boards/adafruit/feather_m4_express/adafruit_feather_m4_express.yaml b/boards/adafruit/feather_m4_express/adafruit_feather_m4_express.yaml
index a8d50925d9f..654b2eb902a 100644
--- a/boards/adafruit/feather_m4_express/adafruit_feather_m4_express.yaml
+++ b/boards/adafruit/feather_m4_express/adafruit_feather_m4_express.yaml
@@ -7,7 +7,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - dma
   - gpio
diff --git a/boards/adafruit/feather_m4_express/doc/index.rst b/boards/adafruit/feather_m4_express/doc/index.rst
index a4178626eee..a44c75808aa 100644
--- a/boards/adafruit/feather_m4_express/doc/index.rst
+++ b/boards/adafruit/feather_m4_express/doc/index.rst
@@ -23,39 +23,7 @@ Hardware
 Supported Features
 ==================
 
-The ``adafruit_feather_m4_express`` board target supports the following
-hardware features:
-
-+-----------+------------+------------------------------------------+
-| Interface | Controller | Driver/Component                         |
-+===========+============+==========================================+
-| SYSTICK   | on-chip    | systick                                  |
-+-----------+------------+------------------------------------------+
-| WDT       | on-chip    | Watchdog                                 |
-+-----------+------------+------------------------------------------+
-| GPIO      | on-chip    | I/O ports                                |
-+-----------+------------+------------------------------------------+
-| USART     | on-chip    | Serial ports                             |
-+-----------+------------+------------------------------------------+
-| SPI       | on-chip    | Serial Peripheral Interface ports        |
-+-----------+------------+------------------------------------------+
-| TRNG      | on-chip    | True Random Number Generator             |
-+-----------+------------+------------------------------------------+
-| HWINFO    | on-chip    | Unique 128 bit serial number             |
-+-----------+------------+------------------------------------------+
-| RTC       | on-chip    | Real-Time Counter                        |
-+-----------+------------+------------------------------------------+
-| USB       | on-chip    | USB device                               |
-+-----------+------------+------------------------------------------+
-| WDT       | on-chip    | Watchdog Timer                           |
-+-----------+------------+------------------------------------------+
-| PWM       | on-chip    | PWM                                      |
-+-----------+------------+------------------------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig file
-:zephyr_file:`boards/adafruit/feather_m4_express/adafruit_feather_m4_express_defconfig`.
+.. zephyr:board-supported-hw::
 
 Zephyr can use the default Cortex-M SYSTICK timer or the SAM0 specific RTC.
 To use the RTC, set :code:`CONFIG_CORTEX_M_SYSTICK=n` and set
@@ -105,6 +73,8 @@ serial port that echos characters back to the host PC.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The Feather ships with a the BOSSA compatible UF2 bootloader.  The
 bootloader can be entered by quickly tapping the reset button twice.
 
diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840.yaml b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840.yaml
index 761f378dcaa..31369a0280c 100644
--- a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840.yaml
+++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - usb_device
diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense.yaml b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense.yaml
index e4a94b6bb36..236e5aafd07 100644
--- a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense.yaml
+++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - usb_device
diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.yaml b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.yaml
index a5f095b336b..3756dc3c2a4 100644
--- a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.yaml
+++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_sense_uf2.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - usb_device
diff --git a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2.yaml b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2.yaml
index ebb7a399f0c..c61e5ae36f9 100644
--- a/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2.yaml
+++ b/boards/adafruit/feather_nrf52840/adafruit_feather_nrf52840_nrf52840_uf2.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - usb_device
diff --git a/boards/adafruit/feather_nrf52840/doc/index.rst b/boards/adafruit/feather_nrf52840/doc/index.rst
index 6f2477e673f..b136a30ba49 100644
--- a/boards/adafruit/feather_nrf52840/doc/index.rst
+++ b/boards/adafruit/feather_nrf52840/doc/index.rst
@@ -58,43 +58,7 @@ Hardware
 Supported Features
 ==================
 
-The Adafruit Feather nRF52840 board configuration supports the
-following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -129,6 +93,8 @@ Push buttons
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.yaml b/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.yaml
index 858b4fcf6db..31454fe1660 100644
--- a/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.yaml
+++ b/boards/adafruit/feather_stm32f405/adafruit_feather_stm32f405.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 1024
 supported:
diff --git a/boards/adafruit/feather_stm32f405/doc/index.rst b/boards/adafruit/feather_stm32f405/doc/index.rst
index 0cc6c327760..656f96f8a8f 100644
--- a/boards/adafruit/feather_stm32f405/doc/index.rst
+++ b/boards/adafruit/feather_stm32f405/doc/index.rst
@@ -26,29 +26,7 @@ Hardware
 Supported Features
 ==================
 
-The Adafruit Feather STM32F405 board configuration supports the
-following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| NVIC      | on-chip    | nested vectored      |
-|           |            | interrupt controller |
-+-----------+------------+----------------------+
-| SYSTICK   | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial port          |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| USB       | on-chip    | USB device           |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -86,6 +64,8 @@ dedicated to the 2 MB SPI Flash chip.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 DFU-Util programming is supported through Zephyr by default. Set up
 of the built in DFU-Util bootloader is possible by following the
 `instructions on the Learn website`_.
diff --git a/boards/adafruit/grand_central_m4_express/doc/index.rst b/boards/adafruit/grand_central_m4_express/doc/index.rst
index 4bab8889967..d85b2e922e0 100644
--- a/boards/adafruit/grand_central_m4_express/doc/index.rst
+++ b/boards/adafruit/grand_central_m4_express/doc/index.rst
@@ -21,37 +21,7 @@ Hardware
 Supported Features
 ==================
 
-The adafruit_grand_central_m4_express board configuration supports the following
-hardware features:
-
-+-----------+------------+------------------------------------------+
-| Interface | Controller | Driver/Component                         |
-+===========+============+==========================================+
-| NVIC      | on-chip    | Nested vector interrupt controller       |
-+-----------+------------+------------------------------------------+
-| SYSTICK   | on-chip    | SysTick                                  |
-+-----------+------------+------------------------------------------+
-| WDT       | on-chip    | Watchdog                                 |
-+-----------+------------+------------------------------------------+
-| GPIO      | on-chip    | I/O ports, User LED                      |
-+-----------+------------+------------------------------------------+
-| UART      | on-chip    | Serial ports, Console                    |
-+-----------+------------+------------------------------------------+
-| SPI       | on-chip    | SPI ports, microSDHC slot                |
-+-----------+------------+------------------------------------------+
-| TRNG      | on-chip    | True Random Number Generator             |
-+-----------+------------+------------------------------------------+
-| RTC       | on-chip    | Real-Time Counter                        |
-+-----------+------------+------------------------------------------+
-| USB       | on-chip    | USB device                               |
-+-----------+------------+------------------------------------------+
-| WDT       | on-chip    | Watchdog Timer                           |
-+-----------+------------+------------------------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig file
-:zephyr_file:`boards/adafruit/grand_central_m4_express/adafruit_grand_central_m4_express_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -95,6 +65,8 @@ serial port that echos characters back to the host PC.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The Grand Central ships with a BOSSA compatible UF2 bootloader.
 The bootloader can be entered by quickly tapping the reset button twice.
 
diff --git a/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.yaml b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.yaml
index 9bf0ea72176..79072d2d015 100644
--- a/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.yaml
+++ b/boards/adafruit/itsybitsy/adafruit_itsybitsy_nrf52840.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - ble
diff --git a/boards/adafruit/itsybitsy/doc/index.rst b/boards/adafruit/itsybitsy/doc/index.rst
index 3fbcb918adb..3dac6fea3b8 100644
--- a/boards/adafruit/itsybitsy/doc/index.rst
+++ b/boards/adafruit/itsybitsy/doc/index.rst
@@ -40,45 +40,7 @@ Hardware
 Supported Features
 ==================
 
-The Adafruit ItsyBitsy nRF52840 board configuration supports the
-following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| QSPI(M)   | on-chip    | nor                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -124,6 +86,9 @@ your board. The button and LED definitions can be found in
 
 Programming and Debugging
 *************************
+
+.. zephyr:board-supported-runners::
+
 The ItsyBitsy ships with the BOSSA compatible UF2 bootloader.  The
 bootloader can be entered by quickly tapping the reset button twice.
 
diff --git a/boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express.yaml b/boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express.yaml
index 7de6fd7a3f2..6a39f7553b2 100644
--- a/boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express.yaml
+++ b/boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express.yaml
@@ -7,7 +7,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - dma
   - gpio
diff --git a/boards/adafruit/itsybitsy_m4_express/doc/index.rst b/boards/adafruit/itsybitsy_m4_express/doc/index.rst
index 31e19cb8a99..19b5cdf2906 100644
--- a/boards/adafruit/itsybitsy_m4_express/doc/index.rst
+++ b/boards/adafruit/itsybitsy_m4_express/doc/index.rst
@@ -22,41 +22,7 @@ Hardware
 Supported Features
 ==================
 
-The adafruit_itsybitsy_m4_express board configuration supports the following
-hardware features:
-
-+-----------+------------+------------------------------------------+
-| Interface | Controller | Driver/Component                         |
-+===========+============+==========================================+
-| NVIC      | on-chip    | Nested vector interrupt controller       |
-+-----------+------------+------------------------------------------+
-| SYSTICK   | on-chip    | systick                                  |
-+-----------+------------+------------------------------------------+
-| WDT       | on-chip    | Watchdog                                 |
-+-----------+------------+------------------------------------------+
-| GPIO      | on-chip    | I/O ports                                |
-+-----------+------------+------------------------------------------+
-| USART     | on-chip    | Serial ports                             |
-+-----------+------------+------------------------------------------+
-| SPI       | on-chip    | Serial Peripheral Interface ports        |
-+-----------+------------+------------------------------------------+
-| TRNG      | on-chip    | True Random Number Generator             |
-+-----------+------------+------------------------------------------+
-| HWINFO    | on-chip    | Unique 128 bit serial number             |
-+-----------+------------+------------------------------------------+
-| RTC       | on-chip    | Real-Time Counter                        |
-+-----------+------------+------------------------------------------+
-| USB       | on-chip    | USB device                               |
-+-----------+------------+------------------------------------------+
-| WDT       | on-chip    | Watchdog Timer                           |
-+-----------+------------+------------------------------------------+
-| PWM       | on-chip    | PWM                                      |
-+-----------+------------+------------------------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig file
-:zephyr_file:`boards/adafruit/itsybitsy_m4_express/adafruit_itsybitsy_m4_express_defconfig`.
+.. zephyr:board-supported-hw::
 
 Zephyr can use the default Cortex-M SYSTICK timer or the SAM0 specific RTC.
 To use the RTC, set :code:`CONFIG_CORTEX_M_SYSTICK=n` and set
@@ -106,6 +72,8 @@ serial port that echos characters back to the host PC.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The ItsyBitsy ships with a the BOSSA compatible UF2 bootloader.  The
 bootloader can be entered by quickly tapping the reset button twice.
 
diff --git a/boards/adafruit/kb2040/adafruit_kb2040.yaml b/boards/adafruit/kb2040/adafruit_kb2040.yaml
index 40511a77633..9fb45644828 100644
--- a/boards/adafruit/kb2040/adafruit_kb2040.yaml
+++ b/boards/adafruit/kb2040/adafruit_kb2040.yaml
@@ -7,7 +7,6 @@ ram: 264
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - uart
   - gpio
diff --git a/boards/adafruit/kb2040/doc/index.rst b/boards/adafruit/kb2040/doc/index.rst
index f1b5d998dc8..0db8c71653e 100644
--- a/boards/adafruit/kb2040/doc/index.rst
+++ b/boards/adafruit/kb2040/doc/index.rst
@@ -27,54 +27,7 @@ Hardware
 Supported Features
 ==================
 
-The adafruit_kb2040 board configuration supports the following
-hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v6m-nvic`
-   * - UART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`raspberrypi,pico-uart`
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`raspberrypi,pico-gpio`
-   * - ADC
-     - :kconfig:option:`CONFIG_ADC`
-     - :dtcompatible:`raspberrypi,pico-adc`
-   * - I2C
-     - :kconfig:option:`CONFIG_I2C`
-     - :dtcompatible:`snps,designware-i2c`
-   * - SPI
-     - :kconfig:option:`CONFIG_SPI`
-     - :dtcompatible:`raspberrypi,pico-spi`
-   * - USB Device
-     - :kconfig:option:`CONFIG_USB_DEVICE_STACK`
-     - :dtcompatible:`raspberrypi,pico-usbd`
-   * - HWINFO
-     - :kconfig:option:`CONFIG_HWINFO`
-     - N/A
-   * - Watchdog Timer (WDT)
-     - :kconfig:option:`CONFIG_WATCHDOG`
-     - :dtcompatible:`raspberrypi,pico-watchdog`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM`
-     - :dtcompatible:`raspberrypi,pico-pwm`
-   * - Flash
-     - :kconfig:option:`CONFIG_FLASH`
-     - :dtcompatible:`raspberrypi,pico-flash`
-   * - Clock controller
-     - :kconfig:option:`CONFIG_CLOCK_CONTROL`
-     - :dtcompatible:`raspberrypi,pico-clock-controller`
-   * - UART (PIO)
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`raspberrypi,pico-uart-pio`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -99,6 +52,8 @@ Default Zephyr Peripheral Mapping:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/adafruit/macropad_rp2040/Kconfig b/boards/adafruit/macropad_rp2040/Kconfig
new file mode 100644
index 00000000000..fcfac0d53f7
--- /dev/null
+++ b/boards/adafruit/macropad_rp2040/Kconfig
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Benjamin Cabé <benjamin@zephyrproject.org>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ADAFRUIT_MACROPAD_RP2040
+	select RP2_FLASH_W25Q080
diff --git a/boards/adafruit/macropad_rp2040/Kconfig.adafruit_macropad_rp2040 b/boards/adafruit/macropad_rp2040/Kconfig.adafruit_macropad_rp2040
new file mode 100644
index 00000000000..dfa06268eae
--- /dev/null
+++ b/boards/adafruit/macropad_rp2040/Kconfig.adafruit_macropad_rp2040
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Benjamin Cabé <benjamin@zephyrproject.org>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ADAFRUIT_MACROPAD_RP2040
+	select SOC_RP2040
diff --git a/boards/adafruit/macropad_rp2040/Kconfig.defconfig b/boards/adafruit/macropad_rp2040/Kconfig.defconfig
new file mode 100644
index 00000000000..d9ef74ce3e0
--- /dev/null
+++ b/boards/adafruit/macropad_rp2040/Kconfig.defconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2025 Benjamin Cabé <benjamin@zephyrproject.org>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_ADAFRUIT_MACROPAD_RP2040
+
+if I2C_DW
+
+config I2C_DW_CLOCK_SPEED
+	default 125
+
+endif # I2C_DW
+
+config USB_SELF_POWERED
+	default n
+
+endif # BOARD_ADAFRUIT_MACROPAD_RP2040
diff --git a/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040-pinctrl.dtsi b/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040-pinctrl.dtsi
new file mode 100644
index 00000000000..1a1953adb0f
--- /dev/null
+++ b/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040-pinctrl.dtsi
@@ -0,0 +1,49 @@
+#include <dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
+
+&pinctrl {
+	uart1_default: uart1_default {
+		group1 {
+			pinmux = <UART1_TX_P20>;
+		};
+		group2 {
+			pinmux = <UART1_RX_P21>;
+			input-enable;
+		};
+	};
+
+	i2c0_default: i2c0_default {
+		group1 {
+			pinmux = <I2C0_SDA_P20>;
+			input-enable;
+		};
+		group2 {
+			pinmux = <I2C0_SCL_P21>;
+			input-enable;
+		};
+	};
+
+	spi1_default: spi1_default {
+		group1 {
+			pinmux = <SPI1_TX_P27>;
+		};
+		group2 {
+			pinmux = <SPI1_RX_P28>;
+			input-enable;
+		};
+		group3 {
+			pinmux = <SPI1_SCK_P26>;
+		};
+	};
+
+	ws2812_pio1_default: ws2812_pio1_default {
+		ws2812 {
+			pinmux = <PIO1_P19>;
+		};
+	};
+
+	pwm_ch0a_default: pwm_ch0a_default {
+		group1 {
+			pinmux = <PWM_0A_P16>;
+		};
+	};
+};
diff --git a/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040.dts b/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040.dts
new file mode 100644
index 00000000000..6181fbdd94d
--- /dev/null
+++ b/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040.dts
@@ -0,0 +1,239 @@
+/dts-v1/;
+
+#include <raspberrypi/rpi_pico/rp2040.dtsi>
+#include "adafruit_macropad_rp2040-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/led/led.h>
+#include <zephyr/dt-bindings/pwm/pwm.h>
+
+
+/ {
+	model = "Adafruit MacroPad RP2040";
+	compatible = "adafruit,macropad-rp2040";
+
+	chosen {
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,flash-controller = &ssi;
+		zephyr,code-partition = &code_partition;
+		zephyr,display = &oled;
+	};
+
+	aliases {
+		watchdog0 = &wdt0;
+		led-strip = &ws2812;
+		led0 = &led0;
+	};
+
+	speaker_reg: speaker-reg {
+		compatible = "regulator-fixed";
+		regulator-name = "Speaker";
+		enable-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		key0: key_0 {
+			gpios = <&gpio0 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_F1>;
+		};
+
+		key1: key_1 {
+			gpios = <&gpio0 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_F2>;
+		};
+
+		key2: key_2 {
+			gpios = <&gpio0 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_F3>;
+		};
+
+		key3: key_3 {
+			gpios = <&gpio0 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_F4>;
+		};
+
+		key4: key_4 {
+			gpios = <&gpio0 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_F5>;
+		};
+
+		key5: key_5 {
+			gpios = <&gpio0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_F6>;
+		};
+
+		key6: key_6 {
+			gpios = <&gpio0 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_F7>;
+		};
+
+		key7: key_7 {
+			gpios = <&gpio0 8 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_F8>;
+		};
+
+		key8: key_8 {
+			gpios = <&gpio0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_F9>;
+		};
+
+		key9: key_9 {
+			gpios = <&gpio0 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_F10>;
+		};
+
+		key10: key_10 {
+			gpios = <&gpio0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_F11>;
+		};
+
+		key11: key_11 {
+			gpios = <&gpio0 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_F12>;
+		};
+
+		encoder_button: encoder_button {
+			gpios = <&gpio0 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_ENTER>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led0: led_0 {
+			gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>;
+			label = "LED 0";
+		};
+	};
+
+	encoder {
+		compatible = "gpio-qdec";
+		gpios = <&gpio0 17 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>,
+			<&gpio0 18 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+		zephyr,axis = <INPUT_REL_WHEEL>;
+		steps-per-period = <4>;
+		sample-time-us = <2000>;
+		idle-timeout-ms = <200>;
+	};
+
+	stemma_connector: stemma_connector {
+		compatible = "stemma-qt-connector";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpio0 21 0>,
+			   <1 0 &gpio0 20 0>;
+	};
+};
+
+&flash0 {
+	reg = <0x10000000 DT_SIZE_M(8)>;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* Reserved memory for the second stage bootloader */
+		second_stage_bootloader: partition@0 {
+			label = "second_stage_bootloader";
+			reg = <0x00000000 0x100>;
+			read-only;
+		};
+
+		/*
+		 * Usable flash. Starts at 0x100, after the bootloader. The partition
+		 * size is 8MB minus the 0x100 bytes taken by the bootloader.
+		 */
+		code_partition: partition@100 {
+			label = "code-partition";
+			reg = <0x100 (DT_SIZE_M(8) - 0x100)>;
+			read-only;
+		};
+	};
+};
+
+&uart1 {
+	current-speed = <115200>;
+	status = "okay";
+	pinctrl-0 = <&uart1_default>;
+	pinctrl-names = "default";
+};
+
+/* You need to disable uart1 to use i2c0 */
+&i2c0 {
+	clock-frequency = <400000>;
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+};
+
+&spi1 {
+	status = "okay";
+	pinctrl-0 = <&spi1_default>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpio0 22 GPIO_ACTIVE_LOW>;
+
+	oled: ssd1306@0 {
+		compatible = "sinowealth,sh1106";
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+		width = <128>;
+		height = <64>;
+		segment-offset = <2>;
+		page-offset = <0>;
+		display-offset = <0>;
+		multiplex-ratio = <63>;
+		prechargep = <0x1F>;
+		segment-remap;
+		com-invdir;
+		inversion-on;
+		reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+		data-cmd-gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
+		ready-time-ms = <100>;  /* SH1106G needs 100ms delay after init */
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&pwm {
+	pinctrl-0 = <&pwm_ch0a_default>;
+	pinctrl-names = "default";
+	divider-int-0 = <255>;
+};
+
+&wdt0 {
+	status = "okay";
+};
+
+zephyr_udc0: &usbd {
+	status = "okay";
+};
+
+&pio1 {
+	status = "okay";
+
+	pio-ws2812 {
+		compatible = "worldsemi,ws2812-rpi_pico-pio";
+		status = "okay";
+		pinctrl-0 = <&ws2812_pio1_default>;
+		pinctrl-names = "default";
+		bit-waveform = <3>, <3>, <4>;
+
+		ws2812: ws2812 {
+			status = "okay";
+			gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
+			chain-length = <12>;
+			color-mapping = <LED_COLOR_ID_GREEN
+					 LED_COLOR_ID_RED
+					 LED_COLOR_ID_BLUE>;
+			reset-delay = <280>;
+			frequency = <800000>;
+		};
+	};
+};
diff --git a/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040.yaml b/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040.yaml
new file mode 100644
index 00000000000..2d0030dd519
--- /dev/null
+++ b/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040.yaml
@@ -0,0 +1,25 @@
+identifier: adafruit_macropad_rp2040
+name: Adafruit MacroPad RP2040
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 264
+flash: 8192
+supported:
+  - uart
+  - gpio
+  - i2c
+  - spi
+  - hwinfo
+  - watchdog
+  - pwm
+  - flash
+  - dma
+  - counter
+  - clock
+  - usbd
+  - display
+  - qdec
+  - led_strip
diff --git a/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040_defconfig b/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040_defconfig
new file mode 100644
index 00000000000..2fb65b60022
--- /dev/null
+++ b/boards/adafruit/macropad_rp2040/adafruit_macropad_rp2040_defconfig
@@ -0,0 +1,13 @@
+# Copyright (c) 2025 Benjamin Cabé <benjamin@zephyrproject.org>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y
+CONFIG_USE_DT_CODE_PARTITION=y
+CONFIG_BUILD_OUTPUT_UF2=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_RESET=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/adafruit/macropad_rp2040/board.cmake b/boards/adafruit/macropad_rp2040/board.cmake
new file mode 100644
index 00000000000..4103e36e635
--- /dev/null
+++ b/boards/adafruit/macropad_rp2040/board.cmake
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(uf2 "--board-id=RPI-RP2")
+
+include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake)
diff --git a/boards/adafruit/macropad_rp2040/board.yml b/boards/adafruit/macropad_rp2040/board.yml
new file mode 100644
index 00000000000..3b0daf408e0
--- /dev/null
+++ b/boards/adafruit/macropad_rp2040/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: adafruit_macropad_rp2040
+  full_name: Adafruit MacroPad RP2040
+  vendor: adafruit
+  socs:
+    - name: rp2040
diff --git a/boards/adafruit/macropad_rp2040/doc/adafruit_macropad_rp2040.webp b/boards/adafruit/macropad_rp2040/doc/adafruit_macropad_rp2040.webp
new file mode 100644
index 00000000000..86f128d85ab
Binary files /dev/null and b/boards/adafruit/macropad_rp2040/doc/adafruit_macropad_rp2040.webp differ
diff --git a/boards/adafruit/macropad_rp2040/doc/index.rst b/boards/adafruit/macropad_rp2040/doc/index.rst
new file mode 100644
index 00000000000..74f9e14fa1d
--- /dev/null
+++ b/boards/adafruit/macropad_rp2040/doc/index.rst
@@ -0,0 +1,66 @@
+.. zephyr:board:: adafruit_macropad_rp2040
+
+Adafruit MacroPad RP2040
+########################
+
+Overview
+********
+
+The Adafruit MacroPad RP2040 is a 3x4 mechanical keyboard development board featuring
+the Raspberry Pi RP2040 microcontroller. It includes 12 mechanical key switches with
+individual RGB NeoPixels, a rotary encoder with push button, a 128x64 OLED display,
+and a small speaker for audio feedback.
+
+Hardware
+********
+
+- Dual core Cortex-M0+ at up to 133MHz
+- 264KB of SRAM
+- 8MB of QSPI flash memory
+- 12 mechanical key switches (Cherry MX compatible)
+- 12 RGB NeoPixel LEDs (one per key)
+- 128x64 monochrome OLED display (SH1106)
+- Rotary encoder with push button
+- Small speaker with Class D amplifier
+- STEMMA QT / Qwiic I2C connector
+- USB Type-C connector
+- Reset button
+- 4x M3 mounting holes
+
+Supported Features
+******************
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``adafruit_macropad_rp2040`` board target can be built and
+flashed in the usual way (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Building and Flashing
+*********************
+
+The MacroPad RP2040 has a built-in UF2 bootloader which can be entered by holding down the rotary
+encoder button (BOOT) and, while continuing to hold it, pressing and releasing the reset button.
+A "RPI-RP2" drive should appear on your host machine.
+
+Here is an example for building and flashing the :zephyr:code-sample:`blinky` sample application
+using UF2.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: adafruit_macropad_rp2040
+   :goals: build flash
+   :flash-args: --runner uf2
+
+References
+**********
+
+.. target-notes::
+
+- `Adafruit MacroPad RP2040 Product Page <https://www.adafruit.com/product/5128>`_
+- `Adafruit MacroPad RP2040 Learn Guide <https://learn.adafruit.com/adafruit-macropad-rp2040>`_
diff --git a/boards/adafruit/nrf52_adafruit_feather/doc/index.rst b/boards/adafruit/nrf52_adafruit_feather/doc/index.rst
index c84bc73f62b..4e318acd793 100644
--- a/boards/adafruit/nrf52_adafruit_feather/doc/index.rst
+++ b/boards/adafruit/nrf52_adafruit_feather/doc/index.rst
@@ -35,29 +35,7 @@ Hardware
 Supported Features
 ==================
 
-The nRF52 Adafruit Feather board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| NVIC      | on-chip    | nested vectored      |
-|           |            | interrupt controller |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial port          |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
-| RTT       | on-chip    | console              |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -80,6 +58,8 @@ Push buttons
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The ``nrf52_adafruit_feather`` board is available in two different versions:
 
 - `Adafruit Feather nRF52 Pro with myNewt Bootloader`_
diff --git a/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.yaml b/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.yaml
index 0bfa59a6c1b..0f6b58a4163 100644
--- a/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.yaml
+++ b/boards/adafruit/nrf52_adafruit_feather/nrf52_adafruit_feather.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 512
 supported:
diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_defconfig b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_defconfig
+++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.overlay b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.overlay
index ac1ec4af1b1..58eaee33a2b 100644
--- a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.overlay
+++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_appcpu_psram.overlay
@@ -27,8 +27,7 @@
 
 /* 2MB psram */
 &psram0 {
-	reg = <0x3c000000 DT_SIZE_M(2)>;
-	status = "okay";
+	size = <DT_SIZE_M(2)>;
 };
 
 #include <espressif/partitions_0x0_amp.dtsi>
diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu.dts b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu.dts
index ac757645e5b..5d8b14a96a6 100644
--- a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu.dts
+++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu.dts
@@ -42,6 +42,15 @@
 			zephyr,code = <INPUT_KEY_0>;
 		};
 	};
+
+	stemma_connector: stemma_connector {
+		compatible = "stemma-qt-connector";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpio1 7 0>,
+			   <1 0 &gpio1 8 0>;
+	};
 };
 
 &usb_serial {
diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_defconfig b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_defconfig
index 6539bd42e59..187793c76e8 100644
--- a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_defconfig
+++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_defconfig
@@ -1,6 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.overlay b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.overlay
index 5ab0be63c3f..cd9ca5f1dcf 100644
--- a/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.overlay
+++ b/boards/adafruit/qt_py_esp32s3/adafruit_qt_py_esp32s3_procpu_psram.overlay
@@ -27,8 +27,7 @@
 
 /* 2MB psram */
 &psram0 {
-	reg = <0x3c000000 DT_SIZE_M(2)>;
-	status = "okay";
+	size = <DT_SIZE_M(2)>;
 };
 
 #include <espressif/partitions_0x0_amp.dtsi>
diff --git a/boards/adafruit/qt_py_esp32s3/doc/index.rst b/boards/adafruit/qt_py_esp32s3/doc/index.rst
index 1c1f6e04eee..8ad715a673c 100644
--- a/boards/adafruit/qt_py_esp32s3/doc/index.rst
+++ b/boards/adafruit/qt_py_esp32s3/doc/index.rst
@@ -32,47 +32,7 @@ numerous peripherals.
 Supported Features
 ==================
 
-Current Zephyr's Adafruit QT Py ESP32-S3 board supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| I2C        | on-chip    | i2c                                 |
-+------------+------------+-------------------------------------+
-| I2S        | on-chip    | i2s                                 |
-+------------+------------+-------------------------------------+
-| TWAI/CAN   | on-chip    | can                                 |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | adc                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| MCPWM      | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| PCNT       | on-chip    | qdec                                |
-+------------+------------+-------------------------------------+
-| GDMA       | on-chip    | dma                                 |
-+------------+------------+-------------------------------------+
-| Wi-Fi      | on-chip    |                                     |
-+------------+------------+-------------------------------------+
-| Bluetooth  | on-chip    |                                     |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Prerequisites
 -------------
@@ -91,6 +51,8 @@ command below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts
index 3f87e4188b2..a6eaf30bbe6 100644
--- a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts
+++ b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.dts
@@ -27,6 +27,15 @@
 		watchdog0 = &wdt0;
 		led-strip = &ws2812;
 	};
+
+	stemma_connector: stemma_connector {
+		compatible = "stemma-qt-connector";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpio0 23 0>,
+			   <1 0 &gpio0 22 0>;
+	};
 };
 
 &flash0 {
diff --git a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.yaml b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.yaml
index 2348e9cec55..132cfe81087 100644
--- a/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.yaml
+++ b/boards/adafruit/qt_py_rp2040/adafruit_qt_py_rp2040.yaml
@@ -7,7 +7,6 @@ ram: 264
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - uart
   - gpio
diff --git a/boards/adafruit/qt_py_rp2040/doc/index.rst b/boards/adafruit/qt_py_rp2040/doc/index.rst
index 0db8b4e4034..253ab615ac2 100644
--- a/boards/adafruit/qt_py_rp2040/doc/index.rst
+++ b/boards/adafruit/qt_py_rp2040/doc/index.rst
@@ -27,51 +27,7 @@ Hardware
 Supported Features
 ==================
 
-The adafruit_qt_py_rp2040 board configuration supports the following
-hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v6m-nvic`
-   * - UART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`raspberrypi,pico-uart`
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`raspberrypi,pico-gpio`
-   * - ADC
-     - :kconfig:option:`CONFIG_ADC`
-     - :dtcompatible:`raspberrypi,pico-adc`
-   * - I2C
-     - :kconfig:option:`CONFIG_I2C`
-     - :dtcompatible:`snps,designware-i2c`
-   * - SPI
-     - :kconfig:option:`CONFIG_SPI`
-     - :dtcompatible:`raspberrypi,pico-spi`
-   * - USB Device
-     - :kconfig:option:`CONFIG_USB_DEVICE_STACK`
-     - :dtcompatible:`raspberrypi,pico-usbd`
-   * - HWINFO
-     - :kconfig:option:`CONFIG_HWINFO`
-     - N/A
-   * - Watchdog Timer (WDT)
-     - :kconfig:option:`CONFIG_WATCHDOG`
-     - :dtcompatible:`raspberrypi,pico-watchdog`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM`
-     - :dtcompatible:`raspberrypi,pico-pwm`
-   * - Flash
-     - :kconfig:option:`CONFIG_FLASH`
-     - :dtcompatible:`raspberrypi,pico-flash`
-   * - UART (PIO)
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`raspberrypi,pico-uart-pio`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -98,6 +54,8 @@ Default Zephyr Peripheral Mapping:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/adafruit/trinket_m0/adafruit_trinket_m0.yaml b/boards/adafruit/trinket_m0/adafruit_trinket_m0.yaml
index f1d21a5c63d..cc4b9bc3738 100644
--- a/boards/adafruit/trinket_m0/adafruit_trinket_m0.yaml
+++ b/boards/adafruit/trinket_m0/adafruit_trinket_m0.yaml
@@ -7,7 +7,6 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - counter
diff --git a/boards/adafruit/trinket_m0/doc/index.rst b/boards/adafruit/trinket_m0/doc/index.rst
index 224f9aa4c6d..ceaa0fd0ca2 100644
--- a/boards/adafruit/trinket_m0/doc/index.rst
+++ b/boards/adafruit/trinket_m0/doc/index.rst
@@ -21,35 +21,7 @@ Hardware
 Supported Features
 ==================
 
-The adafruit_trinket_m0 board configuration supports the following hardware
-features:
-
-+-----------+------------+------------------------------------------+
-| Interface | Controller | Driver/Component                         |
-+===========+============+==========================================+
-| NVIC      | on-chip    | nested vector interrupt controller       |
-+-----------+------------+------------------------------------------+
-| Flash     | on-chip    | Can be used with LittleFS to store files |
-+-----------+------------+------------------------------------------+
-| SYSTICK   | on-chip    | systick                                  |
-+-----------+------------+------------------------------------------+
-| WDT       | on-chip    | Watchdog                                 |
-+-----------+------------+------------------------------------------+
-| GPIO      | on-chip    | I/O ports                                |
-+-----------+------------+------------------------------------------+
-| PWM       | on-chip    | Pulse Width Modulation                   |
-+-----------+------------+------------------------------------------+
-| USART     | on-chip    | Serial ports                             |
-+-----------+------------+------------------------------------------+
-| SPI       | on-chip    | Serial Peripheral Interface ports        |
-+-----------+------------+------------------------------------------+
-| USB       | on-chip    | USB device                               |
-+-----------+------------+------------------------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig file
-:zephyr_file:`boards/adafruit/trinket_m0/adafruit_trinket_m0_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -98,6 +70,8 @@ serial port that echos characters back to the host PC.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The Trinket M0 ships the BOSSA compatible UF2 bootloader.  The
 bootloader can be entered by quickly tapping the reset button twice.
 
diff --git a/boards/adi/ad_swiot1l_sl/Kconfig.ad_swiot1l_sl b/boards/adi/ad_swiot1l_sl/Kconfig.ad_swiot1l_sl
new file mode 100644
index 00000000000..b8b2e0fed81
--- /dev/null
+++ b/boards/adi/ad_swiot1l_sl/Kconfig.ad_swiot1l_sl
@@ -0,0 +1,7 @@
+# AD-SWIOT1L-SL board configuration
+
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_AD_SWIOT1L_SL
+	select SOC_MAX32650
diff --git a/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl.dts b/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl.dts
new file mode 100644
index 00000000000..d46ad87c1cf
--- /dev/null
+++ b/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl.dts
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <adi/max32/max32650.dtsi>
+#include <adi/max32/max32650-pinctrl.dtsi>
+#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "Analog Devices AD-SWIOT1L-SL";
+	compatible = "adi,ad_swiot1l_sl";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1: led_1 {
+			gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
+			label = "Red LED";
+		};
+
+		led2: led_2 {
+			gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
+			label = "Green LED";
+		};
+	};
+
+	/* These aliases are provided for compatibility with samples */
+	aliases {
+		led0 = &led1;
+		led1 = &led2;
+	};
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0_tx_p2_12 &uart0_rx_p2_11>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	data-bits = <8>;
+	parity = "none";
+	status = "okay";
+};
+
+&clk_ipo {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
diff --git a/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl.yaml b/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl.yaml
new file mode 100644
index 00000000000..495481a989d
--- /dev/null
+++ b/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl.yaml
@@ -0,0 +1,13 @@
+identifier: ad_swiot1l_sl
+name: ad_swiot1l_sl
+vendor: adi
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - serial
+ram: 1024
+flash: 3072
diff --git a/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl_defconfig b/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl_defconfig
new file mode 100644
index 00000000000..9428e5334a0
--- /dev/null
+++ b/boards/adi/ad_swiot1l_sl/ad_swiot1l_sl_defconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable UART
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
diff --git a/boards/adi/ad_swiot1l_sl/board.cmake b/boards/adi/ad_swiot1l_sl/board.cmake
new file mode 100644
index 00000000000..716d8121461
--- /dev/null
+++ b/boards/adi/ad_swiot1l_sl/board.cmake
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=MAX32650" "--reset-after-load")
+
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/adi/ad_swiot1l_sl/board.yml b/boards/adi/ad_swiot1l_sl/board.yml
new file mode 100644
index 00000000000..f458ef3b9e8
--- /dev/null
+++ b/boards/adi/ad_swiot1l_sl/board.yml
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board:
+  name: ad_swiot1l_sl
+  full_name: AD-SWIOT1L-SL
+  vendor: adi
+  socs:
+    - name: max32650
diff --git a/boards/adi/ad_swiot1l_sl/doc/img/ad_swiot1l_sl.webp b/boards/adi/ad_swiot1l_sl/doc/img/ad_swiot1l_sl.webp
new file mode 100644
index 00000000000..6b734dc80b4
Binary files /dev/null and b/boards/adi/ad_swiot1l_sl/doc/img/ad_swiot1l_sl.webp differ
diff --git a/boards/adi/ad_swiot1l_sl/doc/index.rst b/boards/adi/ad_swiot1l_sl/doc/index.rst
new file mode 100644
index 00000000000..42ef89a467f
--- /dev/null
+++ b/boards/adi/ad_swiot1l_sl/doc/index.rst
@@ -0,0 +1,107 @@
+.. zephyr:board:: ad_swiot1l_sl
+
+Overview
+********
+The AD-SWIOT1L-SL is a complete hardware and software platform for prototyping intelligent,
+secure, network-capable field devices, with applications in factory automation, process
+control, and intelligent buildings.
+
+The Zephyr port is running on the MAX32650 MCU.
+
+Hardware
+********
+
+- MAX32650 MCU:
+
+  - Ultra-Efficient Microcontroller for Battery-Powered Applications
+
+    - 120MHz Arm Cortex-M4 Processor with FPU
+    - SmartDMA Provides Background Memory Transfers with Programmable Data Processing
+    - 120MHz High-Speed and 50MHz Low-Power Oscillators
+    - 7.3728MHz Low-Power Oscillators
+    - 32.768kHz and RTC Clock (Requires External Crystal)
+    - 8kHz, Always-On, Ultra-Low-Power Oscillator
+    - 3MB Internal Flash, 1MB Internal SRAM
+    - 104μW/MHz Executing from Cache at 1.1V
+    - Five Low-Power Modes: Active, Sleep, Background, Deep Sleep, and Backup
+    - 1.8V and 3.3V I/O with No Level Translators
+
+  - Scalable Cached External Memory Interfaces:
+
+    - 120MB/s HyperBus/Xccela DDR Interface
+    - SPIXF/SPIXR for External Flash/RAM Expansion
+    - 240Mbps SDHC/eMMC/SDIO/microSD Interface
+
+  - Optimal Peripheral Mix Provides Platform Scalability
+
+    - 16-Channel DMA
+    - Three SPI Master (60MHz)/Slave (48MHz)
+    - One QuadSPI Master (60MHz)/Slave (48MHz)
+    - Up to Three 4Mbaud UARTs with Flow Control
+    - Two 1MHz I2C Master/Slave
+    - I2S Slave
+    - Four-Channel, 7.8ksps, 10-Bit Delta-Sigma ADC
+    - USB 2.0 Hi-Speed Device Interface with PHY
+    - 16 Pulse Train Generators
+    - Six 32-Bit Timers with 8mA High Drive
+    - 1-Wire® Master
+
+  - Trust Protection Unit (TPU) for IP/Data Security
+
+    - Modular Arithmetic Accelerator (MAA), True Random Number Generator (TRNG)
+    - Secure Nonvolatile Key Storage, SHA-256, AES-128/192/256
+    - Memory Decryption Integrity Unit, Secure Boot ROM
+
+- External devices connected to the AD-SWIOT1L-SL:
+
+  - On-Board HyperRAM
+  - On-Board QSPI Flash
+  - MAXQ1065 Ultralow Power Cryptographic Controller with ChipDNA
+  - ADIN1110 Robust, Industrial, Low Power 10BASE-T1L Ethernet MAC-PHY
+  - 2-Pin external power supply terminal block (24V DC)
+  - ADP1032 high performance, isolated micropower management unit (PMU)
+  - SWD 10-Pin Header
+  - On-Board 3.3V, 1.8V, and 1.1V voltage regulators
+  - AD74413R Quad-channel, Software Configurable I/O
+  - MAX14906 Quad-channel, Industrial Digital I/O
+  - Two general-purpose LEDs
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Flashing
+========
+The MAX32650 MCU can be flashed by connecting an external debug probe to the
+SWD port. SWD debug can be accessed through the Cortex 10-pin connector, J3.
+Logic levels are fixed to VDDIO (1.8V).
+
+Once the debug probe is connected to your host computer, then you can simply run the
+``west flash`` command to write a firmware image into flash.
+
+.. note::
+
+   This board uses OpenOCD as the default debug interface. You can also use
+   a Segger J-Link with Segger's native tooling by overriding the runner,
+   appending ``--runner jlink`` to your ``west`` command(s). The J-Link should
+   be connected to the standard 2*5 pin debug connector (J3) using an
+   appropriate adapter board and cable
+
+Debugging
+=========
+Please refer to the `Flashing`_ section and run the ``west debug`` command
+instead of ``west flash``.
+
+References
+**********
+
+- `AD-SWIOT1L-SL web page`_
+
+.. _AD-SWIOT1L-SL web page:
+   https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/AD-SWIOT1L-SL.html
diff --git a/boards/adi/apard32690/apard32690_max32690_m4.yaml b/boards/adi/apard32690/apard32690_max32690_m4.yaml
index bc040f86855..bf6486d175b 100644
--- a/boards/adi/apard32690/apard32690_max32690_m4.yaml
+++ b/boards/adi/apard32690/apard32690_max32690_m4.yaml
@@ -6,7 +6,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_gpio
   - arduino_serial
diff --git a/boards/adi/apard32690/board.cmake b/boards/adi/apard32690/board.cmake
index 409b85f0bc1..d388c9a7497 100644
--- a/boards/adi/apard32690/board.cmake
+++ b/boards/adi/apard32690/board.cmake
@@ -1,9 +1,8 @@
-# Copyright (c) 2024 Analog Devices, Inc.
+# Copyright (c) 2024-2025 Analog Devices, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
-board_runner_args(openocd --cmd-pre-init "source [find target/max32690.cfg]")
 board_runner_args(jlink "--device=MAX32690" "--reset-after-load")
 
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/adi/apard32690/doc/index.rst b/boards/adi/apard32690/doc/index.rst
index 8223f2b88e9..318d34b361e 100644
--- a/boards/adi/apard32690/doc/index.rst
+++ b/boards/adi/apard32690/doc/index.rst
@@ -87,32 +87,7 @@ Hardware
 Supported Features
 ==================
 
-Below interfaces are supported by Zephyr on APARD32690.
-
-+-----------+------------+------------------------------------+
-| Interface | Controller | Driver/Component                   |
-+===========+============+====================================+
-| NVIC      | on-chip    | nested vector interrupt controller |
-+-----------+------------+------------------------------------+
-| SYSTICK   | on-chip    | systick                            |
-+-----------+------------+------------------------------------+
-| CLOCK     | on-chip    | clock and reset control            |
-+-----------+------------+------------------------------------+
-| GPIO      | on-chip    | gpio                               |
-+-----------+------------+------------------------------------+
-| UART      | on-chip    | serial                             |
-+-----------+------------+------------------------------------+
-| SPI       | on-chip    | spi                                |
-+-----------+------------+------------------------------------+
-| ADIN1110  | spi        | ADIN1110 10BASE-T1L mac/phy        |
-+-----------+------------+------------------------------------+
-| TRNG      | on-chip    | entropy                            |
-+-----------+------------+------------------------------------+
-| Timer     | on-chip    | counter                            |
-+-----------+------------+------------------------------------+
-| W1        | on-chip    | one wire master                    |
-+-----------+------------+------------------------------------+
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -182,6 +157,8 @@ Connections and IOs
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -190,7 +167,8 @@ SWD port. SWD debug can be accessed through the Cortex 10-pin connector, P9.
 Logic levels are either 1.8V or 3.3V (based on P51 selection).
 
 Once the debug probe is connected to your host computer, then you can simply run the
-``west flash`` command to write a firmware image into flash.
+``west flash`` command to write a firmware image into flash. To perform a full erase,
+pass the ``--erase`` option when executing ``west flash``.
 
 .. note::
 
@@ -209,7 +187,7 @@ instead of ``west flash``.
 References
 **********
 
-- `AD-APARD32690-SL web page`_
+- `AD-APARD32690-SL solution center`_
 
-.. _AD-APARD32690-SL web page:
-   https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/ad-apard32690-sl.html
+.. _AD-APARD32690-SL solution center:
+   https://developer.analog.com/solutions/max32690
diff --git a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.yaml b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.yaml
index c7e9a79567a..c7746597fa4 100644
--- a/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.yaml
+++ b/boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 640
 flash: 2048
 supported:
diff --git a/boards/adi/eval_adin1110ebz/doc/index.rst b/boards/adi/eval_adin1110ebz/doc/index.rst
index 4f38e78faf0..ed1db60a4ee 100644
--- a/boards/adi/eval_adin1110ebz/doc/index.rst
+++ b/boards/adi/eval_adin1110ebz/doc/index.rst
@@ -38,43 +38,7 @@ https://wiki.analog.com/resources/eval/user-guides/eval-adin1110ebz-user-guide
 Supported Features
 ==================
 
-The ADI adi_eval_adin1110ebz board configuration supports the
-following hardware features:
-
-+--------------+------------+-------------------------------------+
-| Interface    | Controller | Driver/Component                    |
-+==============+============+=====================================+
-| NVIC         | on-chip    | nested vector interrupt controller  |
-+--------------+------------+-------------------------------------+
-| UART         | on-chip    | serial port-polling;                |
-|              |            | serial port-interrupt               |
-+--------------+------------+-------------------------------------+
-| PINMUX       | on-chip    | pinmux                              |
-+--------------+------------+-------------------------------------+
-| GPIO         | on-chip    | gpio                                |
-+--------------+------------+-------------------------------------+
-| I2C          | on-chip    | i2c                                 |
-+--------------+------------+-------------------------------------+
-| SPI          | on-chip    | spi                                 |
-+--------------+------------+-------------------------------------+
-| PWM          | on-chip    | pwm                                 |
-+--------------+------------+-------------------------------------+
-| WATCHDOG     | on-chip    | independent watchdog                |
-+--------------+------------+-------------------------------------+
-| ADIN1110     | spi        | adin1110 10BASE-T1L mac/phy         |
-+--------------+------------+-------------------------------------+
-| FT232        | uart       | usb-uart                            |
-+--------------+------------+-------------------------------------+
-| ADT7422      | i2c        | temperature sensor                  |
-+--------------+------------+-------------------------------------+
-| ISS66WVE4M16 | fmc        | 8MB PSRAM                           |
-+--------------+------------+-------------------------------------+
-
-
-The default configuration can be found in the defconfig file:
-
-	:zephyr_file:`boards/adi/eval_adin1110ebz/adi_eval_adin1110ebz_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -119,6 +83,8 @@ to a FT232, so available through Micro USB connector. Default settings are 11520
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.yaml b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.yaml
index bddea6e4a76..c0c48cce543 100644
--- a/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.yaml
+++ b/boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 640
 flash: 2048
 supported:
diff --git a/boards/adi/eval_adin2111ebz/doc/index.rst b/boards/adi/eval_adin2111ebz/doc/index.rst
index 7579c85b0cd..9c65a86ce36 100644
--- a/boards/adi/eval_adin2111ebz/doc/index.rst
+++ b/boards/adi/eval_adin2111ebz/doc/index.rst
@@ -46,39 +46,7 @@ https://wiki.analog.com/resources/eval/user-guides/eval-adin2111ebz-user-guide
 Supported Features
 ==================
 
-The ADI adi_eval_adin2111ebz board configuration supports the
-following hardware features:
-
-+--------------+------------+-------------------------------------+
-| Interface    | Controller | Driver/Component                    |
-+==============+============+=====================================+
-| NVIC         | on-chip    | nested vector interrupt controller  |
-+--------------+------------+-------------------------------------+
-| UART         | on-chip    | serial port-polling;                |
-|              |            | serial port-interrupt               |
-+--------------+------------+-------------------------------------+
-| PINMUX       | on-chip    | pinmux                              |
-+--------------+------------+-------------------------------------+
-| GPIO         | on-chip    | gpio                                |
-+--------------+------------+-------------------------------------+
-| I2C          | on-chip    | i2c                                 |
-+--------------+------------+-------------------------------------+
-| SPI          | on-chip    | spi                                 |
-+--------------+------------+-------------------------------------+
-| PWM          | on-chip    | pwm                                 |
-+--------------+------------+-------------------------------------+
-| WATCHDOG     | on-chip    | independent watchdog                |
-+--------------+------------+-------------------------------------+
-| ADIN2111     | spi        | adin2111 10BASE-T1L mac/phy         |
-+--------------+------------+-------------------------------------+
-| FT232        | uart       | usb-uart                            |
-+--------------+------------+-------------------------------------+
-
-
-The default configuration can be found in the defconfig file:
-
-	:zephyr_file:`boards/adi/eval_adin2111ebz/adi_eval_adin2111ebz_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -120,6 +88,8 @@ Same UART1 TX and RX cmos signals are available before the FT232, at P9 connecto
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/adi/max32650evkit/Kconfig.max32650evkit b/boards/adi/max32650evkit/Kconfig.max32650evkit
new file mode 100644
index 00000000000..accb9f0e0f3
--- /dev/null
+++ b/boards/adi/max32650evkit/Kconfig.max32650evkit
@@ -0,0 +1,7 @@
+# MAX32650EVKIT boards configuration
+
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MAX32650EVKIT
+	select SOC_MAX32650
diff --git a/boards/adi/max32650evkit/board.cmake b/boards/adi/max32650evkit/board.cmake
new file mode 100644
index 00000000000..716d8121461
--- /dev/null
+++ b/boards/adi/max32650evkit/board.cmake
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=MAX32650" "--reset-after-load")
+
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/adi/max32650evkit/board.yml b/boards/adi/max32650evkit/board.yml
new file mode 100644
index 00000000000..24e70315fb5
--- /dev/null
+++ b/boards/adi/max32650evkit/board.yml
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board:
+  name: max32650evkit
+  full_name: MAX32650EVKIT
+  vendor: adi
+  socs:
+    - name: max32650
diff --git a/boards/adi/max32650evkit/doc/img/max32650evkit.webp b/boards/adi/max32650evkit/doc/img/max32650evkit.webp
new file mode 100644
index 00000000000..1300e5e44b9
Binary files /dev/null and b/boards/adi/max32650evkit/doc/img/max32650evkit.webp differ
diff --git a/boards/adi/max32650evkit/doc/index.rst b/boards/adi/max32650evkit/doc/index.rst
new file mode 100644
index 00000000000..d66d875a782
--- /dev/null
+++ b/boards/adi/max32650evkit/doc/index.rst
@@ -0,0 +1,103 @@
+.. zephyr:board:: max32650evkit
+
+Overview
+********
+The MAX32650 evaluation kit (EV kit) provides a platform for evaluating the
+capabilities of the MAX32650 ultra-low power memory-scalable microcontroller
+designed specifically for high performance battery powered applications.
+
+The Zephyr port is running on the MAX32650 MCU.
+
+Hardware
+********
+
+- MAX32650 MCU:
+
+  - Ultra Efficient Microcontroller for Battery-Powered Applications
+
+    - 120MHz Arm Cortex-M4 with FPU
+    - SmartDMA Provides Background Memory Transfers with Programmable Data Processing
+    - 120MHz High-Speed and 50MHz Low-Power Oscillators
+    - 7.3728MHz Low Power Oscillators
+    - 32.768kHz and RTC Clock (Requires External Crystal)
+    - 8kHz, Always-on, Ultra-Low-Power Oscillator
+    - 3MB Internal Flash, 1MB Internal SRAM
+    - 104µW/MHz Executing from Cache at 1.1V
+    - Five Low-Power Modes: Active, Sleep, Background, Deep-Sleep, and Backup
+    - 1.8V and 3.3V I/O with No Level Translators
+    - Programming and Debugging
+
+  - Scalable Cached External Memory Interfaces
+
+    - 120MB/s HyperBus/Xccela DDR Interface
+    - SPIXF/SPIXR for External Flash/RAM Expansion
+    - 240Mbps SDHC/eMMC/SDIO/microSD Interface
+
+  - Optimal Peripheral Mix Provides Platform Scalability
+
+    - 16-Channel DMA
+    - Three SPI Master (60MHz)/Slave (48MHz)
+    - One QuadSPI Master (60MHz)/Slave (48MHz)
+    - Up to Three 4Mbaud UARTs with Flow Control
+    - Two 1MHz I2C Master/Slave
+    - I2S Slave
+    - Four-Channel, 7.8ksps, 10-bit Delta-Sigma ADC
+    - USB 2.0 Hi-Speed Device Interface with PHY
+    - 16 Pulse Train Generators
+    - Six 32-bit Timers with 8mA Hi-Drive
+    - 1-Wire® Master
+
+  - Trust Protection Unit (TPU) for IP/Data and Security
+
+    - Modular Arithmetic Accelerator (MAA), True Random Number Generator (TRNG)
+    - Secure Nonvolatile Key Storage, SHA-256, AES-128/192/256
+    - Memory Decryption Integrity Unit, Secure Boot ROM
+
+- External devices connected to the MAX32650EVKIT:
+
+  - 3.5in 320 x 240 Color TFT Display
+  - 64MB HyperRAM
+  - 64MB XIP Flash
+  - 1MB XIP RAM
+  - USB 2.0 Micro B
+  - Two General-Purpose LEDs and Two GeneralPurpose Pushbutton Switches
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Flashing
+========
+The MAX32650 MCU can be flashed by connecting an external debug probe to the
+SWD port. SWD debug can be accessed through the Cortex 10-pin connector, J3.
+Logic levels are fixed to VDDIO (1.8V).
+
+Once the debug probe is connected to your host computer, then you can simply run the
+``west flash`` command to write a firmware image into flash.
+
+.. note::
+
+   This board uses OpenOCD as the default debug interface. You can also use
+   a Segger J-Link with Segger's native tooling by overriding the runner,
+   appending ``--runner jlink`` to your ``west`` command(s). The J-Link should
+   be connected to the standard 2*5 pin debug connector (J3) using an
+   appropriate adapter board and cable
+
+Debugging
+=========
+Please refer to the `Flashing`_ section and run the ``west debug`` command
+instead of ``west flash``.
+
+References
+**********
+
+- `MAX32650EVKIT web page`_
+
+.. _MAX32650EVKIT web page:
+   https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650-evkit.html
diff --git a/boards/adi/max32650evkit/max32650evkit.dts b/boards/adi/max32650evkit/max32650evkit.dts
new file mode 100644
index 00000000000..2292bfd8b8a
--- /dev/null
+++ b/boards/adi/max32650evkit/max32650evkit.dts
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <adi/max32/max32650.dtsi>
+#include <adi/max32/max32650-pinctrl.dtsi>
+#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "Analog Devices MAX32650EVKIT";
+	compatible = "adi,max32650evkit";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1: led_1 {
+			gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
+			label = "Red LED";
+		};
+
+		led2: led_2 {
+			gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
+			label = "Green LED";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		pb1: pb1 {
+			gpios = <&gpio2 28 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "SW2";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		pb2: pb2 {
+			gpios = <&gpio2 30 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "SW3";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+
+	/* These aliases are provided for compatibility with samples */
+	aliases {
+		led0 = &led1;
+		led1 = &led2;
+	};
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0_tx_p2_12 &uart0_rx_p2_11>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	data-bits = <8>;
+	parity = "none";
+	status = "okay";
+};
+
+&clk_ipo {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
diff --git a/boards/adi/max32650evkit/max32650evkit.yaml b/boards/adi/max32650evkit/max32650evkit.yaml
new file mode 100644
index 00000000000..8e3ced3c437
--- /dev/null
+++ b/boards/adi/max32650evkit/max32650evkit.yaml
@@ -0,0 +1,13 @@
+identifier: max32650evkit
+name: max32650evkit
+vendor: adi
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - serial
+ram: 1024
+flash: 3072
diff --git a/boards/adi/max32650evkit/max32650evkit_defconfig b/boards/adi/max32650evkit/max32650evkit_defconfig
new file mode 100644
index 00000000000..9428e5334a0
--- /dev/null
+++ b/boards/adi/max32650evkit/max32650evkit_defconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable UART
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
diff --git a/boards/adi/max32650fthr/Kconfig.max32650fthr b/boards/adi/max32650fthr/Kconfig.max32650fthr
new file mode 100644
index 00000000000..cf8acafe85d
--- /dev/null
+++ b/boards/adi/max32650fthr/Kconfig.max32650fthr
@@ -0,0 +1,7 @@
+# MAX32650FTHR board configuration
+
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MAX32650FTHR
+	select SOC_MAX32650
diff --git a/boards/adi/max32650fthr/board.cmake b/boards/adi/max32650fthr/board.cmake
new file mode 100644
index 00000000000..716d8121461
--- /dev/null
+++ b/boards/adi/max32650fthr/board.cmake
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=MAX32650" "--reset-after-load")
+
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/adi/max32650fthr/board.yml b/boards/adi/max32650fthr/board.yml
new file mode 100644
index 00000000000..46dee2be233
--- /dev/null
+++ b/boards/adi/max32650fthr/board.yml
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board:
+  name: max32650fthr
+  full_name: MAX32650FTHR
+  vendor: adi
+  socs:
+    - name: max32650
diff --git a/boards/adi/max32650fthr/doc/img/max32650fthr.webp b/boards/adi/max32650fthr/doc/img/max32650fthr.webp
new file mode 100644
index 00000000000..065de009e8c
Binary files /dev/null and b/boards/adi/max32650fthr/doc/img/max32650fthr.webp differ
diff --git a/boards/adi/max32650fthr/doc/index.rst b/boards/adi/max32650fthr/doc/index.rst
new file mode 100644
index 00000000000..de4a139081d
--- /dev/null
+++ b/boards/adi/max32650fthr/doc/index.rst
@@ -0,0 +1,102 @@
+.. zephyr:board:: max32650fthr
+
+Overview
+********
+The MAX32650FTHR evaluation kit provides a platform for evaluating the capabilities
+of the MAX32650 ultra-low-power memory-scalable microcontroller designed specifically
+for high-performance, battery-powered applications.
+
+The Zephyr port is running on the MAX32650 MCU.
+
+Hardware
+********
+
+- MAX32650 MCU:
+
+  - Ultra Efficient Microcontroller for Battery-Powered Applications
+
+    - 120MHz Arm Cortex-M4 with FPU
+    - SmartDMA Provides Background Memory Transfers with Programmable Data Processing
+    - 120MHz High-Speed and 50MHz Low-Power Oscillators
+    - 7.3728MHz Low Power Oscillators
+    - 32.768kHz and RTC Clock (Requires External Crystal)
+    - 8kHz, Always-on, Ultra-Low-Power Oscillator
+    - 3MB Internal Flash, 1MB Internal SRAM
+    - 104µW/MHz Executing from Cache at 1.1V
+    - Five Low-Power Modes: Active, Sleep, Background, Deep-Sleep, and Backup
+    - 1.8V and 3.3V I/O with No Level Translators
+    - Programming and Debugging
+
+  - Scalable Cached External Memory Interfaces
+
+    - 120MB/s HyperBus/Xccela DDR Interface
+    - SPIXF/SPIXR for External Flash/RAM Expansion
+    - 240Mbps SDHC/eMMC/SDIO/microSD Interface
+
+  - Optimal Peripheral Mix Provides Platform Scalability
+
+    - 16-Channel DMA
+    - Three SPI Master (60MHz)/Slave (48MHz)
+    - One QuadSPI Master (60MHz)/Slave (48MHz)
+    - Up to Three 4Mbaud UARTs with Flow Control
+    - Two 1MHz I2C Master/Slave
+    - I2S Slave
+    - Four-Channel, 7.8ksps, 10-bit Delta-Sigma ADC
+    - USB 2.0 Hi-Speed Device Interface with PHY
+    - 16 Pulse Train Generators
+    - Six 32-bit Timers with 8mA Hi-Drive
+    - 1-Wire® Master
+
+  - Trust Protection Unit (TPU) for IP/Data and Security
+
+    - Modular Arithmetic Accelerator (MAA), True Random Number Generator (TRNG)
+    - Secure Nonvolatile Key Storage, SHA-256, AES-128/192/256
+    - Memory Decryption Integrity Unit, Secure Boot ROM
+
+- External devices connected to the MAX32650FTHR:
+
+   - Battery Connector and Charging Circuit
+   - Micro-SD Card Interface
+   - USB 2.0 Full-Speed Device Interface
+   - MAX11261 6-Channel, 24-Bit, 16ksps, ADC
+   - Adafruit® Feather Board Compatible
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Flashing
+========
+The MAX32650 MCU can be flashed by connecting an external debug probe to the
+SWD port. SWD debug can be accessed through the Cortex 10-pin connector, J5.
+Logic levels are fixed to VDDIO (1.8V).
+
+Once the debug probe is connected to your host computer, then you can simply run the
+``west flash`` command to write a firmware image into flash.
+
+.. note::
+
+   This board uses OpenOCD as the default debug interface. You can also use
+   a Segger J-Link with Segger's native tooling by overriding the runner,
+   appending ``--runner jlink`` to your ``west`` command(s). The J-Link should
+   be connected to the standard 2*5 pin debug connector (J5) using an
+   appropriate adapter board and cable
+
+Debugging
+=========
+Please refer to the `Flashing`_ section and run the ``west debug`` command
+instead of ``west flash``.
+
+References
+**********
+
+- `MAX32650FTHR web page`_
+
+.. _MAX32650FTHR web page:
+   https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32650fthr.html
diff --git a/boards/adi/max32650fthr/max32650fthr.dts b/boards/adi/max32650fthr/max32650fthr.dts
new file mode 100644
index 00000000000..b471e2523ce
--- /dev/null
+++ b/boards/adi/max32650fthr/max32650fthr.dts
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <adi/max32/max32650.dtsi>
+#include <adi/max32/max32650-pinctrl.dtsi>
+#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "Analog Devices MAX32650FTHR";
+	compatible = "adi,max32650fthr";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1: led_1 {
+			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+			label = "Red LED";
+		};
+
+		led2: led_2 {
+			gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>;
+			label = "Green LED";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		pb1: pb1 {
+			gpios = <&gpio1 19 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "SW2";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		pb2: pb2 {
+			gpios = <&gpio1 21 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "SW3";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+
+	/* These aliases are provided for compatibility with samples */
+	aliases {
+		led0 = &led1;
+		led1 = &led2;
+	};
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0_tx_p2_12 &uart0_rx_p2_11>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	data-bits = <8>;
+	parity = "none";
+	status = "okay";
+};
+
+&clk_ipo {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
diff --git a/boards/adi/max32650fthr/max32650fthr.yaml b/boards/adi/max32650fthr/max32650fthr.yaml
new file mode 100644
index 00000000000..f967621e702
--- /dev/null
+++ b/boards/adi/max32650fthr/max32650fthr.yaml
@@ -0,0 +1,13 @@
+identifier: max32650fthr
+name: max32650fthr
+vendor: adi
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - serial
+ram: 1024
+flash: 3072
diff --git a/boards/adi/max32650fthr/max32650fthr_defconfig b/boards/adi/max32650fthr/max32650fthr_defconfig
new file mode 100644
index 00000000000..9428e5334a0
--- /dev/null
+++ b/boards/adi/max32650fthr/max32650fthr_defconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable UART
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
diff --git a/boards/adi/max32655evkit/board.cmake b/boards/adi/max32655evkit/board.cmake
index 965de9e4de2..12e0bc56765 100644
--- a/boards/adi/max32655evkit/board.cmake
+++ b/boards/adi/max32655evkit/board.cmake
@@ -1,9 +1,8 @@
-# Copyright (c) 2023-2024 Analog Devices, Inc.
+# Copyright (c) 2023-2025 Analog Devices, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
-board_runner_args(openocd --cmd-pre-init "source [find target/max32655.cfg]")
 board_runner_args(jlink "--device=MAX32655" "--reset-after-load")
 
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/adi/max32655evkit/doc/index.rst b/boards/adi/max32655evkit/doc/index.rst
index 649df3bde37..9c72155a4d9 100644
--- a/boards/adi/max32655evkit/doc/index.rst
+++ b/boards/adi/max32655evkit/doc/index.rst
@@ -69,41 +69,7 @@ Hardware
 Supported Features
 ==================
 
-Below are the interfaces supported by Zephyr on MAX32655EVKIT.
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock and reset control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma controller                      |
-+-----------+------------+-------------------------------------+
-| Watchdog  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| Timer     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| W1        | on-chip    | one wire master                     |
-+-----------+------------+-------------------------------------+
-| Flash     | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -161,6 +127,8 @@ Connections and IOs
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -169,7 +137,8 @@ SWD port. SWD debug can be accessed through the Cortex 10-pin connector, JH3.
 Logic levels are fixed to VDDIO (1.8V).
 
 Once the debug probe is connected to your host computer, then you can simply run the
-``west flash`` command to write a firmware image into flash.
+``west flash`` command to write a firmware image into flash. To perform a full erase,
+pass the ``--erase`` option when executing ``west flash``.
 
 .. note::
 
diff --git a/boards/adi/max32655evkit/max32655evkit_max32655_m4.dts b/boards/adi/max32655evkit/max32655evkit_max32655_m4.dts
index a14953606ea..ae822ce9db1 100644
--- a/boards/adi/max32655evkit/max32655evkit_max32655_m4.dts
+++ b/boards/adi/max32655evkit/max32655evkit_max32655_m4.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023-2024 Analog Devices, Inc.
+ * Copyright (c) 2023-2025 Analog Devices, Inc.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,6 @@
  #include <adi/max32/max32655-pinctrl.dtsi>
  #include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
-#include <zephyr/dt-bindings/dma/max32655_dma.h>
 
 / {
 	 model = "Analog Devices MAX32655EVKIT";
@@ -133,3 +132,34 @@
 &rtc_counter {
 	status = "okay";
 };
+
+&spi0_mosi_p0_5 {
+	power-source = <MAX32_VSEL_VDDIOH>;
+};
+
+&spi0_miso_p0_6 {
+	power-source = <MAX32_VSEL_VDDIOH>;
+};
+
+&spi0_sck_p0_7 {
+	power-source = <MAX32_VSEL_VDDIOH>;
+};
+
+&spi0 {
+	status = "okay";
+	pinctrl-0 = <&spi0_mosi_p0_5 &spi0_miso_p0_6 &spi0_sck_p0_7>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpio0 4 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>;
+
+	spi0_cs0_flash: w25q128@0 {
+		compatible = "jedec,spi-nor";
+		/* 134217728 bits = 16 Mbytes */
+		size = <0x8000000>;
+		reg = <0>;
+		spi-max-frequency = <10000000>;
+		jedec-id = [ef 40 18];
+		hold-gpios = <&gpio0 9 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>;
+		wp-gpios = <&gpio0 8 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>;
+		status = "okay";
+	};
+};
diff --git a/boards/adi/max32655evkit/max32655evkit_max32655_m4.yaml b/boards/adi/max32655evkit/max32655evkit_max32655_m4.yaml
index f3a7fac43ba..141223a8db1 100644
--- a/boards/adi/max32655evkit/max32655evkit_max32655_m4.yaml
+++ b/boards/adi/max32655evkit/max32655evkit_max32655_m4.yaml
@@ -6,7 +6,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - serial
diff --git a/boards/adi/max32655fthr/board.cmake b/boards/adi/max32655fthr/board.cmake
index d2353452cbe..281834ae50a 100644
--- a/boards/adi/max32655fthr/board.cmake
+++ b/boards/adi/max32655fthr/board.cmake
@@ -1,7 +1,5 @@
-# Copyright (c) 2023-2024 Analog Devices, Inc.
+# Copyright (c) 2023-2025 Analog Devices, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
-board_runner_args(openocd --cmd-pre-init "source [find target/max32655.cfg]")
-
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/adi/max32655fthr/doc/index.rst b/boards/adi/max32655fthr/doc/index.rst
index 839365066cc..648133f2142 100644
--- a/boards/adi/max32655fthr/doc/index.rst
+++ b/boards/adi/max32655fthr/doc/index.rst
@@ -82,39 +82,7 @@ Hardware
 Supported Features
 ==================
 
-Below are the interfaces supported by Zephyr on MAX32655FTHR.
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock and reset control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma controller                      |
-+-----------+------------+-------------------------------------+
-| Watchdog  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| Timer     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| Flash     | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Push Buttons
 ************
@@ -184,6 +152,8 @@ used as a user LED.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -191,7 +161,8 @@ The MAX32625 microcontroller on the board is flashed with DAPLink firmware at th
 It allows debugging and flashing the MAX32655 Arm Core over USB.
 
 Once the USB cable is connected to your host computer, then you can simply run the
-``west flash`` command to write a firmware image into flash.
+``west flash`` command to write a firmware image into flash. To perform a full erase,
+pass the ``--erase`` option when executing ``west flash``.
 
 Debugging
 =========
diff --git a/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts b/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts
index 2f82dc09022..7d09e565217 100644
--- a/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts
+++ b/boards/adi/max32655fthr/max32655fthr_max32655_m4.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023-2024 Analog Devices, Inc.
+ * Copyright (c) 2023-2025 Analog Devices, Inc.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,6 @@
 #include <adi/max32/max32655-pinctrl.dtsi>
 #include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
-#include <zephyr/dt-bindings/dma/max32655_dma.h>
 
 / {
 	model = "Analog Devices MAX32655FTHR";
@@ -162,3 +161,35 @@
 &rtc_counter {
 	status = "okay";
 };
+
+&spi0_mosi_p0_5 {
+	power-source = <MAX32_VSEL_VDDIOH>;
+};
+
+&spi0_miso_p0_6 {
+	power-source = <MAX32_VSEL_VDDIOH>;
+};
+
+&spi0_sck_p0_7 {
+	power-source = <MAX32_VSEL_VDDIOH>;
+};
+
+&spi0 {
+	status = "okay";
+	pinctrl-0 = <&spi0_mosi_p0_5 &spi0_miso_p0_6 &spi0_sck_p0_7>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpio0 4 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>,
+		   <&gpio0 11 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>;
+
+	spi0_cs1_flash: w25q128jv@1 {
+		compatible = "jedec,spi-nor";
+		/* 134217728 bits = 16 Mbytes */
+		size = <0x8000000>;
+		reg = <1>;
+		spi-max-frequency = <10000000>;
+		jedec-id = [ef 70 18];
+		hold-gpios = <&gpio0 9 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>;
+		wp-gpios = <&gpio0 8 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>;
+		status = "okay";
+	};
+};
diff --git a/boards/adi/max32655fthr/max32655fthr_max32655_m4.yaml b/boards/adi/max32655fthr/max32655fthr_max32655_m4.yaml
index 37c8b01e02e..66c3d05382d 100644
--- a/boards/adi/max32655fthr/max32655fthr_max32655_m4.yaml
+++ b/boards/adi/max32655fthr/max32655fthr_max32655_m4.yaml
@@ -6,7 +6,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - serial
diff --git a/boards/adi/max32660evsys/Kconfig.max32660evsys b/boards/adi/max32660evsys/Kconfig.max32660evsys
new file mode 100644
index 00000000000..2e936397761
--- /dev/null
+++ b/boards/adi/max32660evsys/Kconfig.max32660evsys
@@ -0,0 +1,7 @@
+# MAX32660EVSYS boards configuration
+
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MAX32660EVSYS
+	select SOC_MAX32660
diff --git a/boards/adi/max32660evsys/board.cmake b/boards/adi/max32660evsys/board.cmake
new file mode 100644
index 00000000000..617eecca8f8
--- /dev/null
+++ b/boards/adi/max32660evsys/board.cmake
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/adi/max32660evsys/board.yml b/boards/adi/max32660evsys/board.yml
new file mode 100644
index 00000000000..5e7e264b04c
--- /dev/null
+++ b/boards/adi/max32660evsys/board.yml
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board:
+  name: max32660evsys
+  full_name: MAX32660EVSYS
+  vendor: adi
+  socs:
+    - name: max32660
diff --git a/boards/adi/max32660evsys/doc/img/max32660evsys.webp b/boards/adi/max32660evsys/doc/img/max32660evsys.webp
new file mode 100644
index 00000000000..b3043a033a2
Binary files /dev/null and b/boards/adi/max32660evsys/doc/img/max32660evsys.webp differ
diff --git a/boards/adi/max32660evsys/doc/index.rst b/boards/adi/max32660evsys/doc/index.rst
new file mode 100644
index 00000000000..c556fcbfeb9
--- /dev/null
+++ b/boards/adi/max32660evsys/doc/index.rst
@@ -0,0 +1,111 @@
+.. zephyr:board:: max32660evsys
+
+Overview
+********
+The MAX32660 evaluation system offers a compact development platform that
+provides access to all the features of the MAX32660 in a tiny, easy to
+use board. A MAX32625PICO-based debug adapter comes attached to the main
+board. It can be snapped free when programming is complete. The debug
+module supports an optional 10-pin Arm® Cortex® debug connector for DAPLink
+functionality. Combined measurements are 0.65in x 2.2in, while the main board
+alone measures 0.65in x 0.95in. External connections terminate in a dual-row
+header footprint compatible with both thru-hole and SMT applications. This
+board provides a powerful processing subsystem in a very small space that
+can be easily integrated into a variety of applications.
+
+The Zephyr port is running on the MAX32660 MCU.
+
+Hardware
+********
+
+- MAX32660 MCU:
+
+  - High-Efficiency Microcontroller for Wearable Devices
+
+     - Internal Oscillator Operates Up to 96MHz
+     - 256KB Flash Memory
+     - 96KB SRAM, Optionally Preserved in Lowest Power Backup Mode
+     - 16KB Instruction Cache
+     - Memory Protection Unit (MPU)
+     - Low 1.1V VCORE Supply Voltage
+     - 3.6V GPIO Operating Range
+     - Internal LDO Provides Operation from Single Supply
+     - Wide Operating Temperature: -40°C to +105°C
+
+  - Power Management Maximizes Uptime for Battery Applications
+
+     - 85µA/MHz Active Executing from Flash
+     - 2µA Full Memory Retention Power in Backup Mode at VDD = 1.8V
+     - 450nA Ultra-Low Power RTC at VDD=1.8V
+     - Internal 80kHz Ring Oscillator
+
+  - Optimal Peripheral Mix Provides Platform Scalability
+
+     - Up to 14 General-Purpose I/O Pins
+     - Up to Two SPI
+     - I2S
+     - Up to Two UARTs
+     - Up to Two I2C, 3.4Mbps High Speed
+     - Four-Channel Standard DMA Controller
+     - Three 32-Bit Timers
+     - Watchdog Timer
+     - CMOS-Level 32.768kHz RTC Output
+
+- Benefits and Features of MAX32660-EVSYS:
+
+  - DIP Breakout Board
+
+     - 100mil Pitch Dual Inline Pin Headers
+     - Breadboard Compatible
+
+  - Integrated Peripherals
+
+     - Red Indicator LED
+     - User Pushbutton
+
+  - MAX32625PICO-Based Debug Adapter
+
+     - CMSIS-DAP SWD Debugger
+     - Virtual UART Console
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Flashing
+========
+
+An Arm® debug access port (DAP) provides an external interface for debugging during application
+development. The DAP is a standard Arm CoreSight® serial wire debug port, uses a two-pin serial
+interface (SWDCLK and SWDIO), and is accessed through 10-pin header (J4).
+
+Once the debug probe is connected to your host computer, then you can simply run the
+``west flash`` command to write a firmware image into flash.
+
+.. note::
+
+   This board uses OpenOCD as the default debug interface. You can also use
+   a Segger J-Link with Segger's native tooling by overriding the runner,
+   appending ``--runner jlink`` to your ``west`` command(s). The J-Link should
+   be connected to the standard 2*5 pin debug connector (J3) using an
+   appropriate adapter board and cable.
+
+Debugging
+=========
+
+Please refer to the `Flashing`_ section and run the ``west debug`` command
+instead of ``west flash``.
+
+References
+**********
+
+- `MAX32660EVSYS web page`_
+
+.. _MAX32660EVSYS web page:
+   https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max32660-evsys.html
diff --git a/boards/adi/max32660evsys/max32660evsys.dts b/boards/adi/max32660evsys/max32660evsys.dts
new file mode 100644
index 00000000000..f06645f94a1
--- /dev/null
+++ b/boards/adi/max32660evsys/max32660evsys.dts
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <adi/max32/max32660.dtsi>
+#include <adi/max32/max32660-pinctrl.dtsi>
+#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "Analog Devices MAX32660EVSYS";
+	compatible = "adi,max32660evsys";
+
+	chosen {
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,sram = &sram2;
+		zephyr,flash = &flash0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1: led_1 {
+			gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
+			label = "Red LED";
+		};
+	};
+
+	/* These aliases are provided for compatibility with samples */
+	aliases {
+		led0 = &led1;
+	};
+
+};
+
+&uart1 {
+	pinctrl-0 = <&uart1_tx_p0_10 &uart1_rx_p0_11>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	data-bits = <8>;
+	parity = "none";
+	status = "okay";
+};
+
+&clk_ipo {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
diff --git a/boards/adi/max32660evsys/max32660evsys.yaml b/boards/adi/max32660evsys/max32660evsys.yaml
new file mode 100644
index 00000000000..da963ef091c
--- /dev/null
+++ b/boards/adi/max32660evsys/max32660evsys.yaml
@@ -0,0 +1,13 @@
+identifier: max32660evsys
+name: max32660evsys
+vendor: adi
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - serial
+ram: 96
+flash: 256
diff --git a/boards/adi/max32660evsys/max32660evsys_defconfig b/boards/adi/max32660evsys/max32660evsys_defconfig
new file mode 100644
index 00000000000..9428e5334a0
--- /dev/null
+++ b/boards/adi/max32660evsys/max32660evsys_defconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable UART
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
diff --git a/boards/adi/max32662evkit/board.cmake b/boards/adi/max32662evkit/board.cmake
index 48ee0fa505f..66bc1b70c0c 100644
--- a/boards/adi/max32662evkit/board.cmake
+++ b/boards/adi/max32662evkit/board.cmake
@@ -1,9 +1,8 @@
-# Copyright (c) 2024 Analog Devices, Inc.
+# Copyright (c) 2024-2025 Analog Devices, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
-board_runner_args(openocd --cmd-pre-init "source [find target/max32662.cfg]")
 board_runner_args(jlink "--device=MAX32662" "--reset-after-load")
 
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/adi/max32662evkit/doc/index.rst b/boards/adi/max32662evkit/doc/index.rst
index b343fb6ed99..cc3d42c03a9 100644
--- a/boards/adi/max32662evkit/doc/index.rst
+++ b/boards/adi/max32662evkit/doc/index.rst
@@ -75,39 +75,7 @@ Hardware
 Supported Features
 ==================
 
-Below interfaces are supported by Zephyr on MAX32662EVKIT.
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock and reset control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| Watchdog  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma controller                      |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| Timer     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| Flash     | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -201,6 +169,8 @@ Connections and IOs
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -212,7 +182,8 @@ the UART1A port can also be accessed through J3.
 
 
 Once the debug probe is connected to your host computer, then you can simply run the
-``west flash`` command to write a firmware image into flash.
+``west flash`` command to write a firmware image into flash. To perform a full erase,
+pass the ``--erase`` option when executing ``west flash``.
 
 .. note::
 
diff --git a/boards/adi/max32662evkit/max32662evkit.dts b/boards/adi/max32662evkit/max32662evkit.dts
index 5f204b91bef..e8cdc4ddb94 100644
--- a/boards/adi/max32662evkit/max32662evkit.dts
+++ b/boards/adi/max32662evkit/max32662evkit.dts
@@ -149,5 +149,5 @@
 	status = "okay";
 	pinctrl-0 = <&spi1a_mosi_p0_8 &spi1a_sck_p0_17>;
 	pinctrl-names = "default";
-	cs-gpios = <&gpio0 18 (GPIO_ACTIVE_LOW | MAX32_VSEL_VDDIOH)>;
+	cs-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
 };
diff --git a/boards/adi/max32662evkit/max32662evkit.yaml b/boards/adi/max32662evkit/max32662evkit.yaml
index eebab96b676..9866e12e0dc 100644
--- a/boards/adi/max32662evkit/max32662evkit.yaml
+++ b/boards/adi/max32662evkit/max32662evkit.yaml
@@ -6,7 +6,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - dma
   - gpio
diff --git a/boards/adi/max32666evkit/board.cmake b/boards/adi/max32666evkit/board.cmake
index 80033d85bdc..024f4a0b7a7 100644
--- a/boards/adi/max32666evkit/board.cmake
+++ b/boards/adi/max32666evkit/board.cmake
@@ -1,9 +1,8 @@
-# Copyright (c) 2024 Analog Devices, Inc.
+# Copyright (c) 2024-2025 Analog Devices, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
-board_runner_args(openocd --cmd-pre-init "source [find target/max32665.cfg]")
 board_runner_args(jlink "--device=MAX32666" "--reset-after-load")
 
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/adi/max32666evkit/doc/index.rst b/boards/adi/max32666evkit/doc/index.rst
index f71b1a69bb6..1569615621d 100644
--- a/boards/adi/max32666evkit/doc/index.rst
+++ b/boards/adi/max32666evkit/doc/index.rst
@@ -86,40 +86,7 @@ Hardware
 Supported Features
 ==================
 
-Below interfaces are supported by Zephyr on MAX32666EVKIT.
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock and reset control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| Watchdog  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma controller                      |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| Timer     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| W1        | on-chip    | one wire master                     |
-+-----------+------------+-------------------------------------+
-| Flash     | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -288,6 +255,8 @@ Connections and IOs
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -296,7 +265,8 @@ SWD port. SWD debug can be accessed through the Cortex 10-pin connector, J6.
 Logic levels are fixed to VDDIOH (1.8V or 3.3V).
 
 Once the debug probe is connected to your host computer, then you can simply run the
-``west flash`` command to write a firmware image into flash.
+``west flash`` command to write a firmware image into flash. To perform a full erase,
+pass the ``--erase`` option when executing ``west flash``.
 
 .. note::
 
diff --git a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml
index 7d5f8699970..f43f703e894 100644
--- a/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml
+++ b/boards/adi/max32666evkit/max32666evkit_max32666_cpu0.yaml
@@ -6,7 +6,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - dma
   - i2c
diff --git a/boards/adi/max32666fthr/board.cmake b/boards/adi/max32666fthr/board.cmake
index b2315d05907..e7077922b36 100644
--- a/boards/adi/max32666fthr/board.cmake
+++ b/boards/adi/max32666fthr/board.cmake
@@ -1,9 +1,8 @@
-# Copyright (c) 2023-2024 Analog Devices, Inc.
+# Copyright (c) 2023-2025 Analog Devices, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
-board_runner_args(openocd --cmd-pre-init "source [find target/max32665.cfg]")
 board_runner_args(jlink "--device=MAX32666" "--reset-after-load")
 
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/adi/max32666fthr/doc/index.rst b/boards/adi/max32666fthr/doc/index.rst
index 1cd8a999de1..5136bf58986 100644
--- a/boards/adi/max32666fthr/doc/index.rst
+++ b/boards/adi/max32666fthr/doc/index.rst
@@ -91,41 +91,7 @@ Hardware
 Supported Features
 ==================
 
-Below interfaces are supported by Zephyr on MAX32666FTHR.
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock and reset control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| Watchdog  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma controller                      |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| Timer     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| W1        | on-chip    | one wire master                     |
-+-----------+------------+-------------------------------------+
-| Flash     | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -208,6 +174,8 @@ JH4 Pinout
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -216,7 +184,8 @@ SWD debug can be accessed through the Cortex 10-pin connector, JH2.
 Logic levels are fixed to VDDIO (1.8V).
 
 Once the debug probe is connected to your host computer, then you can simply run the
-``west flash`` command to write a firmware image into flash.
+``west flash`` command to write a firmware image into flash. To perform a full erase,
+pass the ``--erase`` option when executing ``west flash``.
 
 .. note::
 
diff --git a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts
index 02b45bda3db..5aa45a1c5ce 100644
--- a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts
+++ b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.dts
@@ -55,6 +55,7 @@
 		led2 = &led3;
 		sw0 = &pb1;
 		watchdog0 = &wdt0;
+		sdhc0 = &sdhc0;
 	};
 
 	/* Used for accessing other pins */
@@ -134,3 +135,56 @@
 	pinctrl-0 = <&owm_io_p0_12>;
 	pinctrl-names = "default";
 };
+
+&sdhc0 {
+	pinctrl-0 = <&sdhc_dat3_p1_0 &sdhc_cmd_p1_1 &sdhc_dat0_p1_2 &sdhc_clk_p1_3
+		&sdhc_dat1_p1_4 &sdhc_dat2_p1_5	&sdhc_wp_p1_6 &sdhc_cdn_p1_7>;
+		pinctrl-names = "default";
+};
+
+&sdhc_dat3_p1_0 {
+	power-source = <MAX32_VSEL_VDDIO>;
+	drive-strength = <1>;
+};
+
+&sdhc_cmd_p1_1 {
+	power-source = <MAX32_VSEL_VDDIO>;
+	drive-strength = <1>;
+};
+
+&sdhc_dat0_p1_2 {
+	power-source = <MAX32_VSEL_VDDIOH>;
+	drive-strength = <1>;
+};
+
+&sdhc_clk_p1_3 {
+	power-source = <MAX32_VSEL_VDDIOH>;
+	drive-strength = <1>;
+};
+
+&sdhc_dat1_p1_4 {
+	power-source = <MAX32_VSEL_VDDIOH>;
+	drive-strength = <1>;
+};
+
+&sdhc_dat2_p1_5 {
+	power-source = <MAX32_VSEL_VDDIOH>;
+	drive-strength = <1>;
+};
+
+&sdhc_wp_p1_6 {
+	power-source = <MAX32_VSEL_VDDIOH>;
+	drive-strength = <1>;
+};
+
+&sdhc_cdn_p1_7 {
+	power-source = <MAX32_VSEL_VDDIOH>;
+	drive-strength = <1>;
+};
+
+&sdhc0 {
+	status = "okay";
+	mmc {
+		status = "okay";
+	};
+};
diff --git a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml
index c40294e0ae3..9b924a56a6d 100644
--- a/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml
+++ b/boards/adi/max32666fthr/max32666fthr_max32666_cpu0.yaml
@@ -6,7 +6,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - dma
   - i2c
@@ -21,5 +20,6 @@ supported:
   - pwm
   - w1
   - flash
+  - sdhc
 ram: 560
 flash: 1024
diff --git a/boards/adi/max32670evkit/board.cmake b/boards/adi/max32670evkit/board.cmake
index fc69d3635f1..b370a18f9f3 100644
--- a/boards/adi/max32670evkit/board.cmake
+++ b/boards/adi/max32670evkit/board.cmake
@@ -1,7 +1,5 @@
-# Copyright (c) 2024 Analog Devices, Inc.
+# Copyright (c) 2024-2025 Analog Devices, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
-board_runner_args(openocd --cmd-pre-init "source [find target/max32670.cfg]")
-
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/adi/max32670evkit/doc/index.rst b/boards/adi/max32670evkit/doc/index.rst
index a5b10ef8d9e..4f5b57da3a6 100644
--- a/boards/adi/max32670evkit/doc/index.rst
+++ b/boards/adi/max32670evkit/doc/index.rst
@@ -84,37 +84,7 @@ Hardware
 Supported Features
 ==================
 
-Below interfaces are supported by Zephyr on MAX32670EVKIT.
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock and reset control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma controller                      |
-+-----------+------------+-------------------------------------+
-| Watchdog  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| Timer     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| Flash     | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -178,6 +148,8 @@ Connections and IOs
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -185,7 +157,8 @@ The MAX32670 EVKIT integrates a MAX32625PICO based debugger for DAPLink function
 
 
 Once the debug probe is connected to your host computer, then you can simply run the
-``west flash`` command to write a firmware image into flash.
+``west flash`` command to write a firmware image into flash. To perform a full erase,
+pass the ``--erase`` option when executing ``west flash``.
 
 Debugging
 =========
diff --git a/boards/adi/max32670evkit/max32670evkit.yaml b/boards/adi/max32670evkit/max32670evkit.yaml
index d040a09de49..266d1584aaf 100644
--- a/boards/adi/max32670evkit/max32670evkit.yaml
+++ b/boards/adi/max32670evkit/max32670evkit.yaml
@@ -6,7 +6,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - serial
diff --git a/boards/adi/max32672evkit/board.cmake b/boards/adi/max32672evkit/board.cmake
index 454ec897d2a..76eb5154734 100644
--- a/boards/adi/max32672evkit/board.cmake
+++ b/boards/adi/max32672evkit/board.cmake
@@ -1,9 +1,8 @@
-# Copyright (c) 2024 Analog Devices, Inc.
+# Copyright (c) 2024-2025 Analog Devices, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
-board_runner_args(openocd --cmd-pre-init "source [find target/max32672.cfg]")
 board_runner_args(jlink "--device=MAX32672" "--reset-after-load")
 
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/adi/max32672evkit/doc/index.rst b/boards/adi/max32672evkit/doc/index.rst
index c706898a353..745adcd8a72 100644
--- a/boards/adi/max32672evkit/doc/index.rst
+++ b/boards/adi/max32672evkit/doc/index.rst
@@ -77,40 +77,7 @@ Hardware
 Supported Features
 ==================
 
-Below interfaces are supported by Zephyr on MAX32672EVKIT.
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock and reset control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma controller                      |
-+-----------+------------+-------------------------------------+
-| Watchdog  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| Timer     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| Flash     | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -312,11 +279,9 @@ The I2C ports can independently pulled up to V_AUX (3.3V default) through JP4 (I
 Programming and Debugging
 *************************
 
-The IC can be reset by pushbutton SW1.
-
+.. zephyr:board-supported-runners::
 
-Programming and Debugging
-*************************
+The IC can be reset by pushbutton SW1.
 
 Flashing
 ========
@@ -327,7 +292,8 @@ is supplied externally. Be sure to remove jumper JP15 (LDO_DUT_EN) to disconnect
 LDO if supplying VDD and VDDA externally.
 
 Once the debug probe is connected to your host computer, then you can simply run the
-``west flash`` command to write a firmware image into flash.
+``west flash`` command to write a firmware image into flash. To perform a full erase,
+pass the ``--erase`` option when executing ``west flash``.
 
 .. note::
 
diff --git a/boards/adi/max32672evkit/max32672evkit.dts b/boards/adi/max32672evkit/max32672evkit.dts
index 581a9723c1d..737b2e33370 100644
--- a/boards/adi/max32672evkit/max32672evkit.dts
+++ b/boards/adi/max32672evkit/max32672evkit.dts
@@ -154,7 +154,7 @@
 	status = "okay";
 	pinctrl-0 = <&spi0a_mosi_p0_3 &spi0a_miso_p0_2 &spi0a_sck_p0_4>;
 	pinctrl-names = "default";
-	cs-gpios = <&gpio0 5 (GPIO_ACTIVE_LOW | MAX32_VSEL_VDDIOH)>;
+	cs-gpios = <&gpio0 5 GPIO_ACTIVE_LOW>;
 };
 
 &rtc_counter {
diff --git a/boards/adi/max32672evkit/max32672evkit.yaml b/boards/adi/max32672evkit/max32672evkit.yaml
index e6dae70435c..a8c835774e5 100644
--- a/boards/adi/max32672evkit/max32672evkit.yaml
+++ b/boards/adi/max32672evkit/max32672evkit.yaml
@@ -6,7 +6,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - serial
diff --git a/boards/adi/max32672fthr/board.cmake b/boards/adi/max32672fthr/board.cmake
index 815111de6b7..b370a18f9f3 100644
--- a/boards/adi/max32672fthr/board.cmake
+++ b/boards/adi/max32672fthr/board.cmake
@@ -1,7 +1,5 @@
-# Copyright (c) 2024 Analog Devices, Inc.
+# Copyright (c) 2024-2025 Analog Devices, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
-board_runner_args(openocd --cmd-pre-init "source [find target/max32672.cfg]")
-
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/adi/max32672fthr/doc/index.rst b/boards/adi/max32672fthr/doc/index.rst
index 76033bf97ec..c772136a8bd 100644
--- a/boards/adi/max32672fthr/doc/index.rst
+++ b/boards/adi/max32672fthr/doc/index.rst
@@ -83,40 +83,7 @@ Hardware
 Supported Features
 ==================
 
-Below interfaces are supported by Zephyr on MAX32672FTHR.
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock and reset control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma controller                      |
-+-----------+------------+-------------------------------------+
-| Watchdog  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| Timer     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| Flash     | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -197,6 +164,8 @@ J7 Pinout
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -204,7 +173,8 @@ The MAX32625 microcontroller on the board is flashed with DAPLink firmware at th
 It allows debugging and flashing the MAX32672 Arm Core over USB.
 
 Once the debug probe is connected to your host computer, then you can simply run the
-``west flash`` command to write a firmware image into flash.
+``west flash`` command to write a firmware image into flash. To perform a full erase,
+pass the ``--erase`` option when executing ``west flash``.
 
 Debugging
 =========
diff --git a/boards/adi/max32672fthr/max32672fthr.yaml b/boards/adi/max32672fthr/max32672fthr.yaml
index f98839246c8..28bb5414e07 100644
--- a/boards/adi/max32672fthr/max32672fthr.yaml
+++ b/boards/adi/max32672fthr/max32672fthr.yaml
@@ -6,7 +6,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - serial
diff --git a/boards/adi/max32675evkit/board.cmake b/boards/adi/max32675evkit/board.cmake
index 42caa77e95b..4d691b5106c 100644
--- a/boards/adi/max32675evkit/board.cmake
+++ b/boards/adi/max32675evkit/board.cmake
@@ -1,9 +1,8 @@
-# Copyright (c) 2024 Analog Devices, Inc.
+# Copyright (c) 2024-2025 Analog Devices, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
-board_runner_args(openocd --cmd-pre-init "source [find target/max32675.cfg]")
 board_runner_args(jlink "--device=MAX32675" "--reset-after-load")
 
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/adi/max32675evkit/doc/index.rst b/boards/adi/max32675evkit/doc/index.rst
index a9de574eb21..6c66e204e0c 100644
--- a/boards/adi/max32675evkit/doc/index.rst
+++ b/boards/adi/max32675evkit/doc/index.rst
@@ -68,33 +68,7 @@ Hardware
 Supported Features
 ==================
 
-Below interfaces are supported by Zephyr on MAX32675EVKIT.
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock and reset control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma controller                      |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| Flash     | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -370,6 +344,8 @@ respectively. If the pushbutton is pressed, the attached port pin is pulled low.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -379,7 +355,8 @@ is supplied externally. Be sure to remove jumper JP15 (LDO_DUT_EN) to disconnect
 the 3.3V LDO if supplying VDD and VDDA externally.
 
 Once the debug probe is connected to your host computer, then you can simply run the
-``west flash`` command to write a firmware image into flash.
+``west flash`` command to write a firmware image into flash. To perform a full erase,
+pass the ``--erase`` option when executing ``west flash``.
 
 .. note::
 
diff --git a/boards/adi/max32675evkit/max32675evkit.yaml b/boards/adi/max32675evkit/max32675evkit.yaml
index 023a35465f3..86bee190d25 100644
--- a/boards/adi/max32675evkit/max32675evkit.yaml
+++ b/boards/adi/max32675evkit/max32675evkit.yaml
@@ -6,7 +6,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - dma
   - gpio
diff --git a/boards/adi/max32680evkit/board.cmake b/boards/adi/max32680evkit/board.cmake
index bd318bb200d..b370a18f9f3 100644
--- a/boards/adi/max32680evkit/board.cmake
+++ b/boards/adi/max32680evkit/board.cmake
@@ -1,7 +1,5 @@
-# Copyright (c) 2024 Analog Devices, Inc.
+# Copyright (c) 2024-2025 Analog Devices, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
-board_runner_args(openocd --cmd-pre-init "source [find target/max32680.cfg]")
-
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/adi/max32680evkit/doc/index.rst b/boards/adi/max32680evkit/doc/index.rst
index 13c6d7d06b6..a3c7d909efd 100644
--- a/boards/adi/max32680evkit/doc/index.rst
+++ b/boards/adi/max32680evkit/doc/index.rst
@@ -87,39 +87,7 @@ Hardware
 Supported Features
 ==================
 
-Below interfaces are supported by Zephyr on MAX32680EVKIT.
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock and reset control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma controller                      |
-+-----------+------------+-------------------------------------+
-| Watchdog  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| Timer     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| W1        | on-chip    | one wire master                     |
-+-----------+------------+-------------------------------------+
-| Flash     | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -136,9 +104,9 @@ Connections and IOs
 |           |               |               |                                                                                                  |
 +-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
 | JP2       | REF0P         | +-----------+ |  +-------------------------------------------------------------------------------+               |
-|           |               | | 2-1       | |  | Connects the external high-precision voltage refernce to REF0P.               |               |
+|           |               | | 2-1       | |  | Connects the external high-precision voltage reference to REF0P.              |               |
 |           |               | +-----------+ |  +-------------------------------------------------------------------------------+               |
-|           |               | | 2-3       | |  | Connects the internal voltage refernce to REF0P.                              |               |
+|           |               | | 2-3       | |  | Connects the internal voltage reference to REF0P.                             |               |
 |           |               | +-----------+ |  +-------------------------------------------------------------------------------+               |
 |           |               |               |                                                                                                  |
 +-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
@@ -164,9 +132,9 @@ Connections and IOs
 |           |               |               |                                                                                                  |
 +-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
 | JP6       | REF1P         | +-----------+ |  +-------------------------------------------------------------------------------+               |
-|           |               | | 2-1       | |  | Connects the external high-precision voltage refernce to REF1P.               |               |
+|           |               | | 2-1       | |  | Connects the external high-precision voltage reference to REF1P.              |               |
 |           |               | +-----------+ |  +-------------------------------------------------------------------------------+               |
-|           |               | | 2-3       | |  | Connects the internal voltage refernce to REF1P.                              |               |
+|           |               | | 2-3       | |  | Connects the internal voltage reference to REF1P.                             |               |
 |           |               | +-----------+ |  +-------------------------------------------------------------------------------+               |
 |           |               |               |                                                                                                  |
 +-----------+---------------+---------------+--------------------------------------------------------------------------------------------------+
@@ -319,6 +287,8 @@ Connections and IOs
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -327,7 +297,8 @@ SWD port. SWD debug can be accessed through the Cortex 10-pin connector, JH10.
 Logic levels are set to 1.8V (VDDIO_AUX).
 
 Once the debug probe is connected to your host computer, then you can simply run the
-``west flash`` command to write a firmware image into flash.
+``west flash`` command to write a firmware image into flash. To perform a full erase,
+pass the ``--erase`` option when executing ``west flash``.
 
 Debugging
 =========
diff --git a/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts b/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts
index 4547da3459d..d3459098a11 100644
--- a/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts
+++ b/boards/adi/max32680evkit/max32680evkit_max32680_m4.dts
@@ -163,7 +163,7 @@
 	status = "okay";
 	pinctrl-0 = <&spi0a_mosi_p0_5 &spi0a_miso_p0_6 &spi0a_sck_p0_7>;
 	pinctrl-names = "default";
-	cs-gpios = <&gpio0 4 (GPIO_ACTIVE_LOW | MAX32_VSEL_VDDIOH)>;
+	cs-gpios = <&gpio0 4 (GPIO_ACTIVE_LOW | MAX32_GPIO_VSEL_VDDIOH)>;
 };
 
 &w1 {
diff --git a/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml b/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml
index 1fc90758f49..84f75d376d8 100644
--- a/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml
+++ b/boards/adi/max32680evkit/max32680evkit_max32680_m4.yaml
@@ -6,7 +6,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - serial
diff --git a/boards/adi/max32690evkit/board.cmake b/boards/adi/max32690evkit/board.cmake
index 443c84cc5e8..1c5aa42735d 100644
--- a/boards/adi/max32690evkit/board.cmake
+++ b/boards/adi/max32690evkit/board.cmake
@@ -1,9 +1,8 @@
-# Copyright (c) 2023-2024 Analog Devices, Inc.
+# Copyright (c) 2023-2025 Analog Devices, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
-board_runner_args(openocd --cmd-pre-init "source [find target/max32690.cfg]")
 board_runner_args(jlink "--device=MAX32690" "--reset-after-load")
 
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/adi/max32690evkit/doc/index.rst b/boards/adi/max32690evkit/doc/index.rst
index d976048dcb6..796bbeb1839 100644
--- a/boards/adi/max32690evkit/doc/index.rst
+++ b/boards/adi/max32690evkit/doc/index.rst
@@ -91,42 +91,7 @@ Hardware
 Supported Features
 ==================
 
-Below interfaces are supported by Zephyr on MAX32690EVKIT.
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock and reset control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma controller                      |
-+-----------+------------+-------------------------------------+
-| Watchdog  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| Timer     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| W1        | on-chip    | one wire master                     |
-+-----------+------------+-------------------------------------+
-| Flash     | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -276,6 +241,8 @@ Connections and IOs
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -284,7 +251,8 @@ SWD port. SWD debug can be accessed through the Cortex 10-pin connector, J3.
 Logic levels are fixed to VDDIO (1.8V).
 
 Once the debug probe is connected to your host computer, then you can simply run the
-``west flash`` command to write a firmware image into flash.
+``west flash`` command to write a firmware image into flash. To perform a full erase,
+pass the ``--erase`` option when executing ``west flash``.
 
 .. note::
 
@@ -303,7 +271,7 @@ instead of ``west flash``.
 References
 **********
 
-- `MAX32690EVKIT web page`_
+- `MAX32690EVKIT solution center`_
 
-.. _MAX32690EVKIT web page:
-   https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/MAX32690EVKIT.html
+.. _MAX32690EVKIT solution center:
+   https://developer.analog.com/solutions/max32690
diff --git a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts
index d04a91852cd..132f29f3041 100644
--- a/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts
+++ b/boards/adi/max32690evkit/max32690evkit_max32690_m4.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023-2024 Analog Devices, Inc.
+ * Copyright (c) 2023-2025 Analog Devices, Inc.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -167,3 +167,7 @@
 &rtc_counter {
 	status = "okay";
 };
+
+zephyr_udc0: &usbhs {
+	status = "okay";
+};
diff --git a/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml b/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml
index b6a5a9a5d7a..8278d3fe168 100644
--- a/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml
+++ b/boards/adi/max32690evkit/max32690evkit_max32690_m4.yaml
@@ -6,7 +6,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - serial
@@ -21,5 +20,6 @@ supported:
   - pwm
   - w1
   - flash
+  - usbd
 ram: 1024
 flash: 3072
diff --git a/boards/adi/max32690fthr/board.cmake b/boards/adi/max32690fthr/board.cmake
index 443c84cc5e8..43b3efb7b59 100644
--- a/boards/adi/max32690fthr/board.cmake
+++ b/boards/adi/max32690fthr/board.cmake
@@ -1,9 +1,8 @@
 # Copyright (c) 2023-2024 Analog Devices, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
-board_runner_args(openocd --cmd-pre-init "source [find target/max32690.cfg]")
 board_runner_args(jlink "--device=MAX32690" "--reset-after-load")
 
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/adi/max32690fthr/doc/index.rst b/boards/adi/max32690fthr/doc/index.rst
index fdce08e32e8..ffbc67d9320 100644
--- a/boards/adi/max32690fthr/doc/index.rst
+++ b/boards/adi/max32690fthr/doc/index.rst
@@ -63,31 +63,13 @@ Hardware
 Supported Features
 ==================
 
-Below interfaces are supported by Zephyr on MAX32690FTHR.
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock and reset control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| Flash     | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -97,7 +79,8 @@ Logic levels are fixed to VDDIO (1.8V).
 
 Once the debug probe is connected to your host computer, then you can run the
 ``west flash`` command to write a firmware image into flash. Here is an example
-for the :zephyr:code-sample:`hello_world` application.
+for the :zephyr:code-sample:`hello_world` application. To perform a full erase,
+pass the ``--erase`` option when executing ``west flash``.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
@@ -127,7 +110,7 @@ session. Here is an example for the :zephyr:code-sample:`hello_world` applicatio
 References
 **********
 
-- `MAX32690 product page`_
+- `MAX32690 solution center`_
 
-.. _MAX32690 product page:
-   https://www.analog.com/en/products/max32690.html
+.. _MAX32690 solution center:
+   https://developer.analog.com/solutions/max32690
diff --git a/boards/adi/max32690fthr/max32690fthr_max32690_m4.yaml b/boards/adi/max32690fthr/max32690fthr_max32690_m4.yaml
index d81738ee742..7b802ab4795 100644
--- a/boards/adi/max32690fthr/max32690fthr_max32690_m4.yaml
+++ b/boards/adi/max32690fthr/max32690fthr_max32690_m4.yaml
@@ -6,7 +6,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - serial
diff --git a/boards/adi/max78000evkit/Kconfig.max78000evkit b/boards/adi/max78000evkit/Kconfig.max78000evkit
new file mode 100644
index 00000000000..67f6980da06
--- /dev/null
+++ b/boards/adi/max78000evkit/Kconfig.max78000evkit
@@ -0,0 +1,7 @@
+# MAX78000EVKIT boards configuration
+
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MAX78000EVKIT
+	select SOC_MAX78000_M4 if BOARD_MAX78000EVKIT_MAX78000_M4
diff --git a/boards/adi/max78000evkit/board.cmake b/boards/adi/max78000evkit/board.cmake
new file mode 100644
index 00000000000..c4b66dade5a
--- /dev/null
+++ b/boards/adi/max78000evkit/board.cmake
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=MAX78000" "--reset-after-load")
+
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/adi/max78000evkit/board.yml b/boards/adi/max78000evkit/board.yml
new file mode 100644
index 00000000000..d1b1e370036
--- /dev/null
+++ b/boards/adi/max78000evkit/board.yml
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board:
+  name: max78000evkit
+  full_name: MAX78000EVKIT
+  vendor: adi
+  socs:
+    - name: max78000
diff --git a/boards/adi/max78000evkit/doc/img/max78000evkit.webp b/boards/adi/max78000evkit/doc/img/max78000evkit.webp
new file mode 100644
index 00000000000..691efe7cec7
Binary files /dev/null and b/boards/adi/max78000evkit/doc/img/max78000evkit.webp differ
diff --git a/boards/adi/max78000evkit/doc/index.rst b/boards/adi/max78000evkit/doc/index.rst
new file mode 100644
index 00000000000..18986d881cf
--- /dev/null
+++ b/boards/adi/max78000evkit/doc/index.rst
@@ -0,0 +1,271 @@
+.. zephyr:board:: max78000evkit
+
+Overview
+********
+The MAX78000 evaluation kit (EV kit) provides a platform for leveraging the capabilities of the MAX78000 to build
+new generations of artificial intelligence (AI) devices. Onboard hardware includes a digital microphone, a gyroscope/accelerometer, parallel camera module support
+and a 3.5in touch-enabled color TFT display. A secondary display is driven by a power accumulator for tracking
+device power consumption over time. Uncommitted GPIO as well as analog inputs are readily accessible through
+0.1in pin headers. Primary system power as well as UART access is provided by a USB Micro-B connector. A USB
+to SPI bridge provides rapid access to onboard memory, allowing large networks or images to load quickly
+
+The Zephyr port is running on the MAX78000 MCU.
+
+Hardware
+********
+
+- MAX78000 MCU:
+
+  - Dual-Core, Low-Power Microcontroller
+
+    - Arm Cortex-M4 Processor with FPU up to 100MHz
+    - 512KB Flash and 128KB SRAM
+    - Optimized Performance with 16KB Instruction Cache
+    - Optional Error Correction Code (ECC-SEC-DED) for SRAM
+    - 32-Bit RISC-V Coprocessor up to 60MHz
+    - Up to 52 General-Purpose I/O Pins
+    - 12-Bit Parallel Camera Interface
+    - One I2S Master/Slave for Digital Audio Interface
+
+  - Neural Network Accelerator
+
+    - Highly Optimized for Deep Convolutional Neural Networks
+    - 442k 8-Bit Weight Capacity with 1,2,4,8-Bit Weights
+    - Programmable Input Image Size up to 1024 x 1024 pixels
+    - Programmable Network Depth up to 64 Layers
+    - Programmable per Layer Network Channel Widths up to 1024 Channels
+    - 1 and 2 Dimensional Convolution Processing
+    - Streaming Mode
+    - Flexibility to Support Other Network Types, Including MLP and Recurrent Neural Networks
+
+  - Power Management Maximizes Operating Time for Battery Applications
+
+    - Integrated Single-Inductor Multiple-Output (SIMO) Switch-Mode Power Supply (SMPS)
+    - 2.0V to 3.6V SIMO Supply Voltage Range
+    - Dynamic Voltage Scaling Minimizes Active Core Power Consumption
+    - 22.2μA/MHz While Loop Execution at 3.0V from Cache (CM4 Only)
+    - Selectable SRAM Retention in Low-Power Modes with Real-Time Clock (RTC) Enabled
+
+  - Security and Integrity
+
+    - Available Secure Boot
+    - AES 128/192/256 Hardware Acceleration Engine
+    - True Random Number Generator (TRNG) Seed Generator
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| Name      | Name              | Settings          | Description                                                                                  |
++===========+===================+===================+==============================================================================================+
+| JP1       | LED1 EN           | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Enables auxiliary LED1                                                                  | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | Open          | |  | Disables auxiliary LED1                                                                 | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP2       | LED2 EN           | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Enables auxiliary LED2                                                                  | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | Open          | |  | Disables auxiliary LED2                                                                 | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP3       | TRIG1             | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Enables power monitor event trigger 1                                                   | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | Open          | |  | Disables power monitor event trigger 1                                                  | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP4       | TRIG2             | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Enables power monitor event trigger 2                                                   | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | Open          | |  | Disables power monitor event trigger 2                                                  | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP5       | VREGI             | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Enables 3V3 VREGI power                                                                 | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | Open          | |  | Disables 3V3 VREGI power                                                                | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP6       | VREGIA            | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Enables 3V3 VREGIA power                                                                | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | Open          | |  | Disables 3V3 VREGIA power                                                               | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP7       | CNN BOOST         | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Enables 1V1 boost LDO power                                                             | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | Open          | |  | Disables 1V1 boost LDO power                                                            | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP8       | VDDA              | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Internal SIMO powers VDDA                                                               | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 2-3           | |  | External LDO powers VDDA                                                                | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP9       | VDDIO             | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Internal SIMO powers VDDIO                                                              | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 2-3           | |  | External LDO powers VDDIO                                                               | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP10      | VDDIOH            | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | DUT LDO powers VDDIOH                                                                   | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 2-3           | |  | AUX LDO powers VDDIOH                                                                   | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP11      | VCOREB            | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Internal SIMO powers VCOREB                                                             | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 2-3           | |  | External LDO powers VCOREB                                                              | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP12      | VCOREA            | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Internal SIMO powers VCOREA                                                             | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 2-3           | |  | External LDO powers VCOREA                                                              | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP13      | VREGI PM BYPASS   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Bypasses power monitor shunt                                                            | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | Open          | |  | Enables power monitoring using power accumulator                                        | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP14      | CNN 1V1           | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Connects 1V1 boost LDO to VCOREA                                                        | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | Open          | |  | Disables 1V1 boost LDO                                                                  | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP15      | VCOREA PM BYPASS  | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Bypasses power monitor shunt                                                            | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | Open          | |  | Enables power monitoring using power accumulator                                        | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP16      | VCOREB PM BYPASS  | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Bypasses power monitor shunt                                                            | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | Open          | |  | Enables power monitoring using power accumulator                                        | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP17      | VREG_A PM BYPASS  | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Bypasses power monitor shunt                                                            | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | Open          | |  | Enables power monitoring using power accumulator                                        | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP18      | RESET EN          | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Enables RV JTAG adapter to perform full system reset                                    | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | Open          | |  | Disables system reset by RV JTAG adapter                                                | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP19      | TFT BL            | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Enables main TFT screen backlight                                                       | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | Open          | |  | Disables main TFT screen backlight                                                      | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP20      | I2S CLK SEL       | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Onboard 12.288MHz oscillator drives I2S clock                                           | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 2-3           | |  | External 1V8 CMOS LEVEL source drives I2S clock                                         | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP21      | DUT I             | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | DUT 3V3 total current monitor point                                                     | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | Open          | |  | Open to insert current meter                                                            | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JP22      | USB-SPI/CAM       | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2           | |  | Enables USB-SPI bridge                                                                  | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 2-3           | |  | Enables camera                                                                          | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JH1       | UART 0 EN         | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | 1-2, 3-4      | |  | Enables USB-UART0 bridge, software flow control                                         | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | All Open      | |  | Disables USB-UART0 bridge, allows reuse of port pins                                    | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+| JH2       | UART 1 EN         | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | |All installed  | |  | Enables USB-UART1 bridge                                                                | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   | | All Open      | |  | Disables USB-UART1 bridge, allows reuse of port pins                                    | |
+|           |                   | +---------------+ |  +-----------------------------------------------------------------------------------------+ |
+|           |                   |                   |                                                                                              |
++-----------+-------------------+-------------------+----------------------------------------------------------------------------------------------+
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Flashing
+========
+
+The MAX78000 MCU can be flashed by connecting an external debug probe to the
+SWD port. SWD debug can be accessed through the Cortex 10-pin connector, JH5.
+Logic levels are fixed to VDDIO (1.8V).
+
+Once the debug probe is connected to your host computer, then you can simply run the
+``west flash`` command to write a firmware image into flash. To perform a full erase,
+pass the ``--erase`` option when executing ``west flash``.
+
+.. note::
+
+   This board uses OpenOCD as the default debug interface. You can also use
+   a Segger J-Link with Segger's native tooling by overriding the runner,
+   appending ``--runner jlink`` to your ``west`` command(s). The J-Link should
+   be connected to the standard 2*5 pin debug connector (JH5) using an
+   appropriate adapter board and cable.
+
+Debugging
+=========
+
+Please refer to the `Flashing`_ section and run the ``west debug`` command
+instead of ``west flash``.
+
+References
+**********
+
+- `MAX78000EVKIT web page`_
+
+.. _MAX78000EVKIT web page:
+   https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78000evkit.html
diff --git a/boards/adi/max78000evkit/max78000evkit_max78000_m4.dts b/boards/adi/max78000evkit/max78000evkit_max78000_m4.dts
new file mode 100644
index 00000000000..44e888a24c9
--- /dev/null
+++ b/boards/adi/max78000evkit/max78000evkit_max78000_m4.dts
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <adi/max32/max78000.dtsi>
+#include <adi/max32/max78000-pinctrl.dtsi>
+#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "Analog Devices MAX78000EVKIT";
+	compatible = "adi,max78000evkit";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &sram2;
+		zephyr,flash = &flash0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1: led_1 {
+			gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+			label = "Green LED";
+		};
+
+		led2: led_2 {
+			gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+			label = "Red LED";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		pb1: pb1 {
+			gpios = <&gpio2 6 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "SW2";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		pb2: pb2 {
+			gpios = <&gpio2 7 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "SW3";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+
+		pb_wakeup: pb_wakeup {
+			gpios = <&gpio3 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW
+				| MAX32_GPIO_VSEL_VDDIOH)>;
+			label = "Wakeup";
+			zephyr,code = <INPUT_KEY_WAKEUP>;
+		};
+	};
+
+	/* These aliases are provided for compatibility with samples */
+	aliases {
+		led0 = &led1;
+		led1 = &led2;
+		sw0 = &pb1;
+		sw1 = &pb2;
+		watchdog0 = &wdt0;
+	};
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0a_tx_p0_1 &uart0a_rx_p0_0>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	data-bits = <8>;
+	parity = "none";
+	status = "okay";
+};
+
+&clk_ipo {
+	status = "okay";
+};
+
+&clk_ibro {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&trng {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	pinctrl-0 = <&i2c0_scl_p0_10 &i2c0_sda_p0_11>;
+	pinctrl-names = "default";
+};
+
+&spi0 {
+	status = "okay";
+	pinctrl-0 = <&spi0_mosi_p0_5 &spi0_miso_p0_6 &spi0_sck_p0_7 &spi0_ss0_p0_4>;
+	pinctrl-names = "default";
+};
+
+&dma0 {
+	status = "okay";
+};
+
+&wdt0 {
+	status = "okay";
+};
+
+&w1 {
+	pinctrl-0 = <&owm_io_p0_18 &owm_pe_p0_19>;
+	pinctrl-names = "default";
+};
diff --git a/boards/adi/max78000evkit/max78000evkit_max78000_m4.yaml b/boards/adi/max78000evkit/max78000evkit_max78000_m4.yaml
new file mode 100644
index 00000000000..5f7f5225041
--- /dev/null
+++ b/boards/adi/max78000evkit/max78000evkit_max78000_m4.yaml
@@ -0,0 +1,23 @@
+identifier: max78000evkit/max78000/m4
+name: max78000evkit m4
+vendor: adi
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - adc
+  - counter
+  - dma
+  - flash
+  - gpio
+  - i2c
+  - pwm
+  - serial
+  - spi
+  - trng
+  - w1
+  - watchdog
+ram: 128
+flash: 512
diff --git a/boards/adi/max78000evkit/max78000evkit_max78000_m4_defconfig b/boards/adi/max78000evkit/max78000evkit_max78000_m4_defconfig
new file mode 100644
index 00000000000..9428e5334a0
--- /dev/null
+++ b/boards/adi/max78000evkit/max78000evkit_max78000_m4_defconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable UART
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
diff --git a/boards/adi/max78000fthr/Kconfig.max78000fthr b/boards/adi/max78000fthr/Kconfig.max78000fthr
new file mode 100644
index 00000000000..07efd3aa4be
--- /dev/null
+++ b/boards/adi/max78000fthr/Kconfig.max78000fthr
@@ -0,0 +1,7 @@
+# MAX78000FTHR boards configuration
+
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MAX78000FTHR
+	select SOC_MAX78000_M4 if BOARD_MAX78000FTHR_MAX78000_M4
diff --git a/boards/adi/max78000fthr/board.cmake b/boards/adi/max78000fthr/board.cmake
new file mode 100644
index 00000000000..617eecca8f8
--- /dev/null
+++ b/boards/adi/max78000fthr/board.cmake
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/adi/max78000fthr/board.yml b/boards/adi/max78000fthr/board.yml
new file mode 100644
index 00000000000..365e84d1ad8
--- /dev/null
+++ b/boards/adi/max78000fthr/board.yml
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board:
+  name: max78000fthr
+  full_name: MAX78000FTHR
+  vendor: adi
+  socs:
+    - name: max78000
diff --git a/boards/adi/max78000fthr/doc/img/max78000fthr.webp b/boards/adi/max78000fthr/doc/img/max78000fthr.webp
new file mode 100644
index 00000000000..57f08575845
Binary files /dev/null and b/boards/adi/max78000fthr/doc/img/max78000fthr.webp differ
diff --git a/boards/adi/max78000fthr/doc/index.rst b/boards/adi/max78000fthr/doc/index.rst
new file mode 100644
index 00000000000..1960a00257e
--- /dev/null
+++ b/boards/adi/max78000fthr/doc/index.rst
@@ -0,0 +1,173 @@
+.. zephyr:board:: max78000fthr
+
+Overview
+********
+The MAX78000FTHR is a rapid development platform to help engineers quickly implement ultra low-power, artificial
+intelligence (AI) solutions using the MAX78000 Arm® Cortex®-M4F processor with an integrated Convolutional Neural Network
+accelerator. The board also includes the MAX20303 PMIC for battery and power management. The form factor is 0.9in x 2.6in
+dual-row header footprint that is compatible with Adafruit Feather Wing peripheral expansion boards. The board includes a
+variety of peripherals, such as a CMOS VGA image sensor, digital microphone, low-power stereo audio CODEC, 1MB QSPI
+SRAM, micro SD card connector, RGB indicator LED, and pushbutton. The MAX78000FTHR provides a poweroptimized flexible
+platform for quick proof-of-concepts and early software development to enhance time to market.
+
+The Zephyr port is running on the MAX78000 MCU.
+
+Hardware
+********
+
+- MAX78000 MCU:
+
+  - Dual-Core, Low-Power Microcontroller
+
+    - Arm Cortex-M4 Processor with FPU up to 100MHz
+    - 512KB Flash and 128KB SRAM
+    - Optimized Performance with 16KB Instruction Cache
+    - Optional Error Correction Code (ECC-SEC-DED) for SRAM
+    - 32-Bit RISC-V Coprocessor up to 60MHz
+    - Up to 52 General-Purpose I/O Pins
+    - 12-Bit Parallel Camera Interface
+    - One I2S Master/Slave for Digital Audio Interface
+
+  - Neural Network Accelerator
+
+    - Highly Optimized for Deep Convolutional Neural Networks
+    - 442k 8-Bit Weight Capacity with 1,2,4,8-Bit Weights
+    - Programmable Input Image Size up to 1024 x 1024 pixels
+    - Programmable Network Depth up to 64 Layers
+    - Programmable per Layer Network Channel Widths up to 1024 Channels
+    - 1 and 2 Dimensional Convolution Processing
+    - Streaming Mode
+    - Flexibility to Support Other Network Types, Including MLP and Recurrent Neural Networks
+
+  - Power Management Maximizes Operating Time for Battery Applications
+
+    - Integrated Single-Inductor Multiple-Output (SIMO) Switch-Mode Power Supply (SMPS)
+    - 2.0V to 3.6V SIMO Supply Voltage Range
+    - Dynamic Voltage Scaling Minimizes Active Core Power Consumption
+    - 22.2μA/MHz While Loop Execution at 3.0V from Cache (CM4 Only)
+    - Selectable SRAM Retention in Low-Power Modes with Real-Time Clock (RTC) Enabled
+
+  - Security and Integrity
+
+    - Available Secure Boot
+    - AES 128/192/256 Hardware Acceleration Engine
+    - True Random Number Generator (TRNG) Seed Generator
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+J8 Pinout
+**********
+
++---------+----------+-------------------------------------------------------------------------------------------------+
+| Pin     | Name     | Description                                                                                     |
++=========+==========+=================================================================================================+
+| 1       | RST      | Master Reset Signal                                                                             |
++---------+----------+-------------------------------------------------------------------------------------------------+
+| 2       | 3V3      | 3.3V Output. Typically used to provide 3.3V to peripherals connected to the expansion headers.  |
++---------+----------+-------------------------------------------------------------------------------------------------+
+| 3       | 1V8      | 1.8V Output. Typically used to provide 1.8V to peripherals connected to the expansion headers.  |
++---------+----------+-------------------------------------------------------------------------------------------------+
+| 4       | GND      | Ground                                                                                          |
++---------+----------+-------------------------------------------------------------------------------------------------+
+| 5       | P2_3     | GPIO or Analog Input (AIN3 channel).                                                            |
++---------+----------+-------------------------------------------------------------------------------------------------+
+| 6       | P2_4     | GPIO or Analog Input (AIN4 channel).                                                            |
++---------+----------+-------------------------------------------------------------------------------------------------+
+| 7       | P1_1     | GPIO or UART2 Tx signal                                                                         |
++---------+----------+-------------------------------------------------------------------------------------------------+
+| 8       | P1_0     | GPIO or UART2 Rx signal                                                                         |
++---------+----------+-------------------------------------------------------------------------------------------------+
+| 9       | MPC1     | GPIO controlled by PMIC through I2C interface. Open drain or push-pull programmable             |
++---------+----------+-------------------------------------------------------------------------------------------------+
+| 10      | MPC2     | GPIO controlled by PMIC through I2C interface. Open drain or push-pull programmable             |
++---------+----------+-------------------------------------------------------------------------------------------------+
+| 11      | P0_7     | GPIO or QSPI0 clock signal. Shared with SD card and on-board QSPI SRAM                          |
++---------+----------+-------------------------------------------------------------------------------------------------+
+| 12      | P0_5     | GPIO or QSPI0 MOSI signal. Shared with SD card and on-board QSPI SRAM                           |
++---------+----------+-------------------------------------------------------------------------------------------------+
+| 13      | P0_6     | GPIO or QSPI0 MISO signal. Shared with SD card and on-board QSPI SRAM                           |
++---------+----------+-------------------------------------------------------------------------------------------------+
+| 14      | P2_6     | GPIO or LPUART Rx signal                                                                        |
++---------+----------+-------------------------------------------------------------------------------------------------+
+| 15      | P2_7     | GPIO or LPUART Tx signal                                                                        |
++---------+----------+-------------------------------------------------------------------------------------------------+
+| 16      | GND      | Ground                                                                                          |
++---------+----------+-------------------------------------------------------------------------------------------------+
+
+J4 Pinout
+**********
+
++---------+----------+-----------------------------------------------------------------------------------------------------------+
+| Pin     | Name     | Description                                                                                               |
++=========+==========+===========================================================================================================+
+| 1       | SYS      | SYS Switched Connection to the Battery. This is the primary system power supply and automatically         |
+|         |          | switches between the battery voltage and the USB supply when available.                                   |
++---------+----------+-----------------------------------------------------------------------------------------------------------+
+| 2       | PWR      | Turns off the PMIC if shorted to Ground for 13 seconds. Hard power-down button.                           |
++---------+----------+-----------------------------------------------------------------------------------------------------------+
+| 3       | VBUS     | USB VBUS Signal. This can be used as a 5V supply when connected to USB. This pin can also be              |
+|         |          | used as an input to power the board.                                                                      |
++---------+----------+-----------------------------------------------------------------------------------------------------------+
+| 4       | P1_6     | GPIO                                                                                                      |
++---------+----------+-----------------------------------------------------------------------------------------------------------+
+| 5       | MPC3     | GPIO controlled by PMIC through the I2C interface. Open drain or push-pull programmable.                  |
++---------+----------+-----------------------------------------------------------------------------------------------------------+
+| 6       | P0_9     | GPIO or QSPI0 SDIO3 signal. Shared with SD card and on-board QSPI SRAM.                                   |
++---------+----------+-----------------------------------------------------------------------------------------------------------+
+| 7       | P0_8     | GPIO or QSPI0 SDIO2 signal. Shared with SD Card and on-board QSPI SRAM.                                   |
++---------+----------+-----------------------------------------------------------------------------------------------------------+
+| 8       | P0_11    | GPIO or QSPI0 slave select signal                                                                         |
++---------+----------+-----------------------------------------------------------------------------------------------------------+
+| 9       | P0_19    | GPIO                                                                                                      |
++---------+----------+-----------------------------------------------------------------------------------------------------------+
+| 10      | P3_1     | GPIO or Wake-up signal. This pin is 3.3V only.                                                            |
++---------+----------+-----------------------------------------------------------------------------------------------------------+
+| 11      | P0_16    | GPIO or I2C1 SCL signal. An on-board level shifter allows selecting 1.8V or 3.3V operation through        |
+|         |          | R15 or R20 resistors. Do not populate both.                                                               |
++---------+----------+-----------------------------------------------------------------------------------------------------------+
+| 12      | P0_17    | GPIO or I2C1 SDA signal. An on-board level shifter allows selecting 1.8V or 3.3V operation through        |
+|         |          | R15 or R20 resistors. Do not populate both.                                                               |
++---------+----------+-----------------------------------------------------------------------------------------------------------+
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Flashing
+========
+
+The MAX32625 microcontroller on the board is preprogrammed with DAPLink firmware.
+It allows debugging and programming of the MAX78000 Arm core over USB.
+
+Once the debug probe is connected to your host computer, then you can simply run the
+``west flash`` command to write a firmware image into flash. To perform a full erase,
+pass the ``--erase`` option when executing ``west flash``.
+
+.. note::
+
+   This board uses OpenOCD as the default debug interface. You can also use
+   a Segger J-Link with Segger's native tooling by overriding the runner,
+   appending ``--runner jlink`` to your ``west`` command(s). The J-Link should
+   be connected to the standard 2*5 pin debug connector (JH5) using an
+   appropriate adapter board and cable.
+
+Debugging
+=========
+
+Please refer to the `Flashing`_ section and run the ``west debug`` command
+instead of ``west flash``.
+
+References
+**********
+
+- `MAX78000FTHR web page`_
+
+.. _MAX78000FTHR web page:
+   https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/max78000fthr.html
diff --git a/boards/adi/max78000fthr/max78000fthr_max78000_m4.dts b/boards/adi/max78000fthr/max78000fthr_max78000_m4.dts
new file mode 100644
index 00000000000..0c62d5e4e4e
--- /dev/null
+++ b/boards/adi/max78000fthr/max78000fthr_max78000_m4.dts
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <adi/max32/max78000.dtsi>
+#include <adi/max32/max78000-pinctrl.dtsi>
+#include <zephyr/dt-bindings/gpio/adi-max32-gpio.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "Analog Devices MAX78000FTHR";
+	compatible = "adi,max78000fthr";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &sram2;
+		zephyr,flash = &flash0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1: led_1 {
+			gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
+			label = "Red LED";
+		};
+
+		led2: led_2 {
+			gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+			label = "Green LED";
+		};
+
+		led3: led_3 {
+			gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+			label = "Blue LED";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		pb1: pb1 {
+			gpios = <&gpio0 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "SW1";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		pb2: pb2 {
+			gpios = <&gpio1 7 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "SW2";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+
+	/* These aliases are provided for compatibility with samples */
+	aliases {
+		led0 = &led1;
+		led1 = &led2;
+		sw0 = &pb1;
+		sw1 = &pb2;
+		watchdog0 = &wdt0;
+	};
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0a_tx_p0_1 &uart0a_rx_p0_0>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	data-bits = <8>;
+	parity = "none";
+	status = "okay";
+};
+
+&clk_ipo {
+	status = "okay";
+};
+
+&clk_ibro {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&trng {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	pinctrl-0 = <&i2c0_scl_p0_10 &i2c0_sda_p0_11>;
+	pinctrl-names = "default";
+};
+
+&spi0 {
+	status = "okay";
+	pinctrl-0 = <&spi0_mosi_p0_5 &spi0_miso_p0_6 &spi0_sck_p0_7 &spi0_ss0_p0_4>;
+	pinctrl-names = "default";
+};
+
+&dma0 {
+	status = "okay";
+};
+
+&wdt0 {
+	status = "okay";
+};
+
+&w1 {
+	pinctrl-0 = <&owm_io_p0_6 &owm_pe_p0_7>;
+	pinctrl-names = "default";
+};
diff --git a/boards/adi/max78000fthr/max78000fthr_max78000_m4.yaml b/boards/adi/max78000fthr/max78000fthr_max78000_m4.yaml
new file mode 100644
index 00000000000..116fa9051c5
--- /dev/null
+++ b/boards/adi/max78000fthr/max78000fthr_max78000_m4.yaml
@@ -0,0 +1,23 @@
+identifier: max78000fthr/max78000/m4
+name: max78000fthr m4
+vendor: adi
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - adc
+  - counter
+  - dma
+  - flash
+  - gpio
+  - i2c
+  - pwm
+  - serial
+  - spi
+  - trng
+  - w1
+  - watchdog
+ram: 128
+flash: 512
diff --git a/boards/adi/max78000fthr/max78000fthr_max78000_m4_defconfig b/boards/adi/max78000fthr/max78000fthr_max78000_m4_defconfig
new file mode 100644
index 00000000000..9428e5334a0
--- /dev/null
+++ b/boards/adi/max78000fthr/max78000fthr_max78000_m4_defconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable UART
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
diff --git a/boards/adi/max78002evkit/board.cmake b/boards/adi/max78002evkit/board.cmake
index b7d321b2f84..42001337f58 100644
--- a/boards/adi/max78002evkit/board.cmake
+++ b/boards/adi/max78002evkit/board.cmake
@@ -1,7 +1,8 @@
-# Copyright (c) 2024 Analog Devices, Inc.
+# Copyright (c) 2024-2025 Analog Devices, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
-board_runner_args(openocd --cmd-pre-init "source [find target/max78002.cfg]")
+board_runner_args(jlink "--device=MAX78002" "--reset-after-load")
 
+include(${ZEPHYR_BASE}/boards/common/openocd-adi-max32.boards.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/adi/max78002evkit/doc/index.rst b/boards/adi/max78002evkit/doc/index.rst
index a5bd4acf09b..ffb55415bf4 100644
--- a/boards/adi/max78002evkit/doc/index.rst
+++ b/boards/adi/max78002evkit/doc/index.rst
@@ -42,7 +42,7 @@ Hardware
     - MIPI Camera Serial Interface 2 (MIPI CSI-2) Controller V2.1
     - Support for Two Data Lanes
     - 12-Bit Parallel Camera Interface
-    - I 2S Controller/Target for Digital Audio Interface
+    - I2S Controller/Target for Digital Audio Interface
     - Secure Digital Interface Supports SD 3.0/SDIO 3.0/eMMC 4.51
 
   - Convolutional Neural Network (CNN) Accelerator
@@ -71,51 +71,6 @@ Hardware
     - AES 128/192/256 Hardware Acceleration Engine
     - True Random Number Generator (TRNG) Seed Generator
 
-  - Ultra-Low-Power Wireless Microcontroller
-
-    - Internal 100MHz Oscillator
-    - Flexible Low-Power Modes with 7.3728MHz System Clock Option
-    - 512KB Flash and 128KB SRAM (Optional ECC on One 32KB SRAM Bank)
-    - 16KB Instruction Cache
-
-  - Bluetooth 5.2 LE Radio
-
-    - Dedicated, Ultra-Low-Power, 32-Bit RISC-V Coprocessor to Offload Timing-Critical Bluetooth Processing
-    - Fully Open-Source Bluetooth 5.2 Stack Available
-    - Supports AoA, AoD, LE Audio, and Mesh
-    - High-Throughput (2Mbps) Mode
-    - Long-Range (125kbps and 500kbps) Modes
-    - Rx Sensitivity: -97.5dBm; Tx Power: +4.5dBm
-    - Single-Ended Antenna Connection (50Ω)
-
-  - Power Management Maximizes Battery Life
-
-    - 2.0V to 3.6V Supply Voltage Range
-    - Integrated SIMO Power Regulator
-    - Dynamic Voltage Scaling (DVS)
-    - 23.8μA/MHz Active Current at 3.0V
-    - 4.4μA at 3.0V Retention Current for 32KB
-    - Selectable SRAM Retention + RTC in Low-Power Modes
-
-  - Multiple Peripherals for System Control
-
-    - Up to Two High-Speed SPI Master/Slave
-    - Up to Three High-Speed I2C Master/Slave (3.4Mbps)
-    - Up to Four UART, One I2S Master/Slave
-    - Up to 8-Input, 10-Bit Sigma-Delta ADC 7.8ksps
-    - Up to Four Micro-Power Comparators
-    - Timers: Up to Two Four 32-Bit, Two LP, TwoWatchdog Timers
-    - 1-Wire® Master
-    - Up to Four Pulse Train (PWM) Engines
-    - RTC with Wake-Up Timer
-    - Up to 52 GPIOs
-
-  - Security and Integrity​
-
-    - Available Secure Boot
-    - TRNG Seed Generator
-    - AES 128/192/256 Hardware Acceleration Engine
-
 - External devices connected to the MAX78002 EVKIT:
 
   - Color TFT Display
@@ -126,142 +81,335 @@ Hardware
 Supported Features
 ==================
 
-The ``max78002evkit/max78002/m4`` board target supports the following interfaces:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock and reset control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma controller                      |
-+-----------+------------+-------------------------------------+
-| Watchdog  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| Timer     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| W1        | on-chip    | one wire master                     |
-+-----------+------------+-------------------------------------+
-| Flash     | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
 
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| Name      | Signal            | Usage                                                                            |
-+===========+===================+==================================================================================+
-| JP1       | 3V3 MON           | Normal operation in conjunction with JP3 jumpered 1-2                            |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP2       | 3V3 SW PM BYPASS  | Power monitor shunts for main 3.3 V system power are bypassed                    |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP3       | CNN MON           | Normal operation in conjunction with JP6 jumpered 1-2                            |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP4       | VCOREA PM BYPASS  | Power monitor shunts for U4's share of VCOREA + CNN loads are bypassed           |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP5       | VCOREB PM BYPASS  | Power monitor shunts for VCOREB are bypassed                                     |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP6       | VREGO_A PM BYPASS | Power monitor shunts for VREGO_A are bypassed                                    |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP7       | VBAT              | Enable/Disable 3V3 VBAT power                                                    |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP8       | VREGI             | Enable/Disable 3V3 VREGI power                                                   |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP9       | VREGI/VBAT        | Onboard 3V3_PM / external source at TP10 supplies VREGI/VBAT                     |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP10      | VDDIOH            | Onboard 3V3_PM/3V3_SW supplies VDDIOH                                            |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP11      | VDDA              | VREGO_A_PM powers VDDA                                                           |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP12      | VDDIO             | VREGO_A_PM powers VDDIO                                                          |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP13      | VCOREB            | VREGO_B powers VCOREB                                                            |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP14      | VCOREA            | VREGO_C ties to net VCOREA                                                       |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP15      | VREF              | DUT ADC VREF is supplied by precision external reference                         |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP16      | I2C1 SDA          | I2C1 DATA pull-up                                                                |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP17      | I2C1 SCL          | I2C1 CLOCK pull-up                                                               |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP18      | TRIG1             | PWR accumulator trigger signal 1 ties to port 1.6                                |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP19      | TRIG2             | PWR accumulator trigger signal 2 ties to port 1.7                                |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP20      | UART0 EN          | Connect/Disconnect USB-UART bridge to UART0                                      |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP21      | I2C0_SDA          | I2C0 DATA pull-up                                                                |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP22      | I2C0_SCL          | I2C0 CLOCK pull-up                                                               |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP23      | UART1 EN          | Connect/Disconnect USB-UART bridge to UART1                                      |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP24      | EXT I2C0 EN       | Enable/Disable QWIIC interface for I2C0                                          |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP25      | PB1 PU            | Enable/Disable 100kΩ pull-up for pushbutton mode, port 2.6                       |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP26      | PB2 PU            | Enable/Disable 100kΩ pull-up for pushbutton mode, port 2.7                       |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP27      | I2C2 SDA          | I2C2 DATA pull-up                                                                |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP28      | I2C2 SCL          | I2C2 CLOCK pull-up                                                               |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP29      | VDDB              | USB XCVR VDDB powered from VBUS / powered full time by system 3V3_PM             |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP30      | EXT I2C2 EN       | Enable/Disable QWIIC interface for I2C2                                          |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP31      | L/R SEL           | Select MIC ON R/L CH, I2S microphone data stream                                 |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP32      | MIC-I2S I/O       | External I2S/MIC data from I2S I/O / MIC header connected to I2S SDI             |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP33      | MIC-I2S/CODEC     | Onboard CODEC data / external I2S data from header connects to I2S SDI           |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP34      | I2S VDD           | Select 1.8V/3.3V for external MIC and DATA I2S interface                         |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP35      | I2C1 SDA          | I2C1 DATA pull-up                                                                |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP36      | I2C1 SCL          | I2C1 CLOCK pull-up                                                               |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP37      | I2S CK SEL        | Select SMA connector J6 / onboard crystal oscillator for I2S master clock source |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP38      | DVP CAM PWR       | Enable/Disable OVM7692 for DVP camera PWDN input                                 |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP39      | SW CAM PWUP       | Camera reset and power up under port pin control                                 |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP40      | HW PWUP / SW PWUP | Camera will reset and power up as soon as 3.3V reaches a valid level             |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP41      | CSI CAM I2C EN    | Connect/Disconnect I2C1 to CSI camera Digilent P5C I2C                           |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP42      | TFT DC            | TFT data/command select connects to port 2.2                                     |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP43      | TFT CS            | Select port 0.3 / port 1.7 to drive TFT CS                                       |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP44      | LED1 EN           | Enable/Disable LED1                                                              |
-+-----------+-------------------+----------------------------------------------------------------------------------+
-| JP45      | LED2 EN           | Enable/Disable LED2                                                              |
-+-----------+-------------------+----------------------------------------------------------------------------------+
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| Name      | Name              | Settings      | Description                                                                                      |
++===========+===================+===============+==================================================================================================+
+| JP1       | 3V3 MON           | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | Normal operation in conjunction with JP3 jumpered 1-2                                   |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Test access point for current measurement                                               |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP2       | 3V3 SW PM BYPASS  | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | Power monitor shunts for main 3.3 V system power are bypassed                           |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Main 3.3V input routes through shunts for power accumulator measurements                |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP3       | CNN MON           | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | Normal operation in conjunction with JP6 jumpered 1-2                                   |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Test access point for current measurement of U4's share of VCOREA and CNN loads         |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP4       | VCOREA PM BYPASS  | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | Power monitor shunts for U4's share of VCOREA + CNN loads are bypassed                  |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | VCOREA + CNN loads route through shunts for power accumulator                           |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP5       | VCOREB PM BYPASS  | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | Power monitor shunts for VCOREB are bypassed                                            |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | VCOREB power routes through shunts for power accumulator                                |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP6       | VREGO_A PM BYPASS | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | Power monitor shunts for VREGO_A are bypassed                                           |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | VREGO_A power routes through shunts for power accumulator                               |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP7       | VBAT              | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | Enables 3V3 VBAT power                                                                  |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Disables 3V3 VBAT power                                                                 |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP8       | VREGI             | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | Enables 3V3 VREGI power                                                                 |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Disables 3V3 VREGI power                                                                |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP9       | VREGI/VBAT        | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 2-1       | |  | Onboard 3V3_PM supplies VREGI/VBAT                                                      |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 2-3       | |  | External source at TP10 supplies VREGI/VBAT                                             |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP10      | VDDIOH            | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 2-1       | |  | Onboard 3V3_PM supplies VDDIOH                                                          |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 2-3       | |  | Onboard 3V3_SW supplies VDDIOH                                                          |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP11      | VDDA              | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | VREGO_A_PM powers VDDA                                                                  |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | VDDA may be powered using TP6                                                           |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP12      | VDDIO             | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | VREGO_A_PM powers VDDIO                                                                 |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | VDDIO may be powered using TP7                                                          |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP13      | VCOREB            | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | VREGO_B powers VCOREB                                                                   |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | VCOREB may be powered using TP8                                                         |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP14      | VCOREA            | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | VREGO_C ties to net VCOREA                                                              |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Net VCOREA may be powered using TP9; JP17 may also be used as a current test point      |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP15      | VREF              | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | DUT ADC VREF is supplied by precision external reference                                |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | External ADC VREF disabled; ref voltage may be injected at JP18.1                       |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP16      | I2C1 SDA          | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | I2C1 DATA pullup                                                                        |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Close this jumper as needed to assure proper termination                                |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP17      | I2C1 SCL          | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | I2C1 CLOCK pullup                                                                       |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Close this jumper as needed to assure proper termination                                |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP18      | TRIG1             | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | PWR accumulator trigger signal 1 ties to port 1.6                                       |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | TRIG1 is disabled, so DVP camera PCIF_D10 may be used instead                           |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP19      | TRIG2             | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | PWR accumulator trigger signal 2 ties to port 1.7                                       |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | TRIG2 is disabled, so DVP camera PCIF_D11 may be used instead                           |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP20      | UART0 EN          | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Closed    | |  | USB-UART bridge connected to DUT UART0 (RTS and CTS are supported)                      |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | USB-UART bridge disconnected from DUT UART0                                             |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP21      | I2C0_SDA          | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | I2C0 DATA pull-up                                                                       |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Close this jumper as needed to assure proper termination                                |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP22      | I2C0_SCL          | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | I2C0 CLOCK pull-up                                                                      |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Close this jumper as needed to assure proper termination                                |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP23      | UART1 EN          | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Closed    | |  | USB-UART bridge connected to DUT UART1 (no HW flow control)                             |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | USB-UART bridge disconnected from DUT UART1                                             |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP24      | EXT I2C0 EN       | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | QWIIC interface for I2C0 enabled by default                                             |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Open this jumper to place the QWIIC level translator into a high-Z state                |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP25      | PB1 PU            | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | 100kΩ pull-up enabled for pushbutton mode, port 2.6                                     |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Pull-up disabled, allowing port pin to be repurposed (this port shared with AIN6)       |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP26      | PB2 PU            | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | 100kΩ pull-up enabled for pushbutton mode, port 2.7                                     |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Pull-up disabled, allowing port pin to be repurposed (this port shared with AIN7)       |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP27      | I2C2 SDA          | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | I2C2 DATA pull-up                                                                       |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Close this jumper as needed to assure proper termination                                |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP28      | I2C2 SCL          | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | I2C2 CLOCK pull-up                                                                      |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Close this jumper as needed to assure proper termination                                |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP29      | VDDB              | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 2-1       | |  | DUT USB XCVR VDDB powered from VBUS regulated with dedicated 3.3V LDO                   |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 2-3       | |  | USB XCVR VDDB powered full time by system 3V3_PM                                        |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP30      | EXT I2C2 EN       | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | QWIIC interface for I2C2 enabled by default                                             |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Open this jumper to place the QWIIC level translator into a high-Z state                |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP31      | L/R SEL           | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | MIC ON R CH, I2S microphone data stream                                                 |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | MIC ON L CH, I2S microphone data stream                                                 |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP32      | MIC-I2S I/O       | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | External I2S data from I2S I/O header connected to I2S SDI.                             |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | External MIC data from I2S MIC header connected to I2S SDI                              |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP33      | MIC-I2S/CODEC     | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | Onboard CODEC data connects to I2S SDI                                                  |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | External I2S data (mic or slave I2S) from header connects to I2S SDI                    |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP34      | I2S VDD           | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 2-1       | |  | External MIC and DATA I2S interface headers run at 1.8V                                 |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 2-3       | |  | External MIC and DATA I2S interface headers run at 3.3V                                 |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP35      | I2C1 SDA          | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | I2C1 DATA pull-up                                                                       |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Close this jumper as needed to assure proper termination                                |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP36      | I2C1 SCL          | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | I2C1 CLOCK pull-up                                                                      |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Close this jumper as needed to assure proper termination                                |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP37      | I2S CK SEL        | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | I2S master clock sourced from SMA connector J6                                          |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | I2S master clock sourced from onboard crystal oscillator                                |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP38      | DVP CAM PWR       | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 2-1       | |  | Sets state of DVP camera PWDN input; default is OFF for OVM7692                         |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 2-3       | |  | Sets state of DVP camera PWDN input; 2-3 will power up OVM7692                          |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP39      | SW CAM PWUP       | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | Camera reset and power up under port pin control                                        |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Digilent P5C camera powered down, JP39 can over ride this condition                     |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP40      | HW PWUP / SW PWUP | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | Camera will reset and power up as soon as 3.3V reaches a valid level                    |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Camera reset and power up under port pin control if JP39 is installed; else, camera off |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP41      | CSI CAM I2C EN    | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | CSI camera Digilent P5C I2C connects to I2C1 for register setup                         |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Level translator and I2C PU are in high-Z state; I2C1 disconnected from P5C registers   |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP42      | TFT DC            | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | TFT data/command select connects to port 2.2                                            |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Pull jumper if using AIN2                                                               |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP43      | TFT CS            | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 2-1       | |  | TFT CS driven by port 0.3, shared with UART0 RTS                                        |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 2-3       | |  | TFT CS driven by port 1.7, shared with DVP DATA 11 and TRIG2                            |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP44      | LED1 EN           | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | LED0 illuminates when port 2.4 is high                                                  |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Pull jumper if using AIN4                                                               |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
+| JP45      | LED2 EN           | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | 1-2       | |  | LED1 illuminates when port 2.5 is high                                                  |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   | | Open      | |  | Pull jumper if using AIN5                                                               |     |
+|           |                   | +-----------+ |  +-----------------------------------------------------------------------------------------+     |
+|           |                   |               |                                                                                                  |
++-----------+-------------------+---------------+--------------------------------------------------------------------------------------------------+
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -270,7 +418,8 @@ SWD port. SWD debug can be accessed through the Cortex 10-pin connector, JH8.
 Logic levels are fixed to VDDIO (1.8V).
 
 Once the debug probe is connected to your host computer, then you can simply run the
-``west flash`` command to write a firmware image into flash.
+``west flash`` command to write a firmware image into flash. To perform a full erase,
+pass the ``--erase`` option when executing ``west flash``.
 
 .. note::
 
diff --git a/boards/adi/max78002evkit/max78002evkit_max78002_m4.dts b/boards/adi/max78002evkit/max78002evkit_max78002_m4.dts
index 8b6df6c28c1..6ba9ded8d4a 100644
--- a/boards/adi/max78002evkit/max78002evkit_max78002_m4.dts
+++ b/boards/adi/max78002evkit/max78002evkit_max78002_m4.dts
@@ -125,3 +125,7 @@
 	pinctrl-0 = <&owm_io_p0_6 &owm_pe_p0_7>;
 	pinctrl-names = "default";
 };
+
+&rtc_counter {
+	status = "okay";
+};
diff --git a/boards/adi/max78002evkit/max78002evkit_max78002_m4.yaml b/boards/adi/max78002evkit/max78002evkit_max78002_m4.yaml
index 4631e4e276b..ffe89807e7a 100644
--- a/boards/adi/max78002evkit/max78002evkit_max78002_m4.yaml
+++ b/boards/adi/max78002evkit/max78002evkit_max78002_m4.yaml
@@ -6,7 +6,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - serial
@@ -17,6 +16,7 @@ supported:
   - spi
   - adc
   - counter
+  - rtc_counter
   - pwm
   - w1
   - flash
diff --git a/boards/adi/sdp_k1/adi_sdp_k1.yaml b/boards/adi/sdp_k1/adi_sdp_k1.yaml
index 800bedab7de..b794e9be8f2 100644
--- a/boards/adi/sdp_k1/adi_sdp_k1.yaml
+++ b/boards/adi/sdp_k1/adi_sdp_k1.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 384
 flash: 2048
 supported:
diff --git a/boards/adi/sdp_k1/doc/index.rst b/boards/adi/sdp_k1/doc/index.rst
index 680852f53dd..d684c53374c 100644
--- a/boards/adi/sdp_k1/doc/index.rst
+++ b/boards/adi/sdp_k1/doc/index.rst
@@ -65,23 +65,7 @@ More information about STM32F469NI can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32f469i_disco board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in
-:zephyr_file:`boards/adi/sdp_k1/adi_sdp_k1_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -119,6 +103,8 @@ Default Zephyr Peripheral Mapping:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The ADI SDP-K1 be programmed over USB using the DAPLink firmware running on an
 embedded NXP Freescale microcontroller or a 10-pin ``DEBUG`` header connected
 to a STLINK debugger.
diff --git a/boards/alientek/pandora_stm32l475/doc/index.rst b/boards/alientek/pandora_stm32l475/doc/index.rst
index d976ee7740f..671570b6409 100644
--- a/boards/alientek/pandora_stm32l475/doc/index.rst
+++ b/boards/alientek/pandora_stm32l475/doc/index.rst
@@ -85,44 +85,7 @@ The STM32L475VE SoC provides the following hardware features:
 Supported Features
 ==================
 
-The Zephyr stm32l475ve_pandora board configuration supports the following hardware features:
-
-+-----------+------------+----------------------------------------------+
-| Interface | Controller | Driver/Component                             |
-+===========+============+==============================================+
-| NVIC      | on-chip    | nested vector interrupt controller           |
-+-----------+------------+----------------------------------------------+
-| UART      | on-chip    | serial port-polling;                         |
-|           |            | serial port-interrupt                        |
-+-----------+------------+----------------------------------------------+
-| PINMUX    | on-chip    | pinmux                                       |
-+-----------+------------+----------------------------------------------+
-| GPIO      | on-chip    | gpio                                         |
-+-----------+------------+----------------------------------------------+
-| I2C       | on-chip    | I2C-AHT10(Temperature and humidity sensor)   |
-|           |            | I2C-ICM2068(light environment sensor)        |
-+-----------+------------+----------------------------------------------+
-| I2S       | on-chip    | I2S-ES8388(Audio Decoder)                    |
-+-----------+------------+----------------------------------------------+
-| USB       | on-chip    | I2S-OTG                                      |
-+-----------+------------+----------------------------------------------+
-| SDIO      | on-chip    | SDIO-AP6181(WIFI)                            |
-+-----------+------------+----------------------------------------------+
-| SPI       | on-chip    | LCD-TFT                                      |
-+-----------+------------+----------------------------------------------+
-| QSPI NOR  | on-chip    | flash                                        |
-+-----------+------------+----------------------------------------------+
-| IR-RX/TX  | on-board   | Infrared Receiver(38Khz)/Transmitter         |
-+-----------+------------+----------------------------------------------+
-| STLINK-V2 | on-board   | STLINK-V2 Debugger                           |
-+-----------+------------+----------------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-
-	:zephyr_file:`boards/alientek/pandora_stm32l475/pandora_stm32l475_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -158,6 +121,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/alientek/pandora_stm32l475/pandora_stm32l475.yaml b/boards/alientek/pandora_stm32l475/pandora_stm32l475.yaml
index d0f6adfdbf8..8a1ac762770 100644
--- a/boards/alientek/pandora_stm32l475/pandora_stm32l475.yaml
+++ b/boards/alientek/pandora_stm32l475/pandora_stm32l475.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 512
 supported:
diff --git a/boards/altr/max10/doc/index.rst b/boards/altr/max10/doc/index.rst
index 0c16aa329e8..1e5064b0f0d 100644
--- a/boards/altr/max10/doc/index.rst
+++ b/boards/altr/max10/doc/index.rst
@@ -130,6 +130,8 @@ in the SDK:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi b/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi
index 26cf5e58063..39db2783c37 100644
--- a/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi
+++ b/boards/ambiq/apollo3_evb/apollo3_evb-pinctrl.dtsi
@@ -125,7 +125,7 @@
 			pinmux = <NCE19_P19>;
 			drive-push-pull;
 			drive-strength = "0.5";
-			ambiq,iom-nce-module = <0>;
+			ambiq,nce-src = <0>;
 			ambiq,iom-num = <6>;
 		};
 	};
diff --git a/boards/ambiq/apollo3_evb/apollo3_evb.dts b/boards/ambiq/apollo3_evb/apollo3_evb.dts
index 30828d729c5..b6cf18bc1c6 100644
--- a/boards/ambiq/apollo3_evb/apollo3_evb.dts
+++ b/boards/ambiq/apollo3_evb/apollo3_evb.dts
@@ -139,23 +139,25 @@
 	status = "okay";
 };
 
-&spi0 {
-	compatible = "ambiq,spi";
-	pinctrl-0 = <&spi0_default>;
-	pinctrl-names = "default";
-	cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
-	clock-frequency = <DT_FREQ_M(1)>;
-	status = "okay";
+&iom0 {
+	spi0: spi {
+		pinctrl-0 = <&spi0_default>;
+		pinctrl-names = "default";
+		cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
+		clock-frequency = <DT_FREQ_M(1)>;
+		status = "okay";
+	};
 };
 
-&i2c3 {
-	compatible = "ambiq,i2c";
-	pinctrl-0 = <&i2c3_default>;
-	pinctrl-names = "default";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-	scl-gpios = <&gpio32_63 10 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
-	sda-gpios = <&gpio32_63 11 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
-	status = "okay";
+&iom3 {
+	i2c3: i2c {
+		pinctrl-0 = <&i2c3_default>;
+		pinctrl-names = "default";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		scl-gpios = <&gpio32_63 10 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
+		sda-gpios = <&gpio32_63 11 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
+		status = "okay";
+	};
 };
 
 &counter0 {
@@ -196,7 +198,6 @@
 };
 
 &adc0 {
-	compatible = "ambiq,adc";
 	pinctrl-0 = <&adc0_default>;
 	pinctrl-names = "default";
 	status = "disabled";
diff --git a/boards/ambiq/apollo3_evb/apollo3_evb_connector.dtsi b/boards/ambiq/apollo3_evb/apollo3_evb_connector.dtsi
index 77e22c5bbb5..7a6ad127efa 100644
--- a/boards/ambiq/apollo3_evb/apollo3_evb_connector.dtsi
+++ b/boards/ambiq/apollo3_evb/apollo3_evb_connector.dtsi
@@ -63,5 +63,5 @@
 	};
 };
 
-ambiq_spi0: &spi0 {};
-ambiq_i2c3: &i2c3 {};
+ambiq_spi0: &iom0 {};
+ambiq_i2c3: &iom3 {};
diff --git a/boards/ambiq/apollo3_evb/doc/index.rst b/boards/ambiq/apollo3_evb/doc/index.rst
index 429d973d378..c8d56b0443b 100644
--- a/boards/ambiq/apollo3_evb/doc/index.rst
+++ b/boards/ambiq/apollo3_evb/doc/index.rst
@@ -21,34 +21,13 @@ For more information about the Apollo3 Blue SoC and Apollo3 Blue EVB board:
 Supported Features
 ==================
 
-The Apollo3 Blue EVB board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| STIMER    | on-chip    | stimer                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| WDT       | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| RADIO     | on-chip    | bluetooth                           |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-``boards/arm/apollo3_evb/apollo3_evb_defconfig``.
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 =========================
 
+.. zephyr:board-supported-runners::
+
 Flashing an application
 -----------------------
 
diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi b/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi
index 3eea582a372..f8821a4c2f8 100644
--- a/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi
+++ b/boards/ambiq/apollo3p_evb/apollo3p_evb-pinctrl.dtsi
@@ -126,7 +126,7 @@
 			drive-push-pull;
 			drive-strength = "0.5";
 			ambiq,iom-mspi = <0>;
-			ambiq,iom-nce-module = <0>;
+			ambiq,nce-src = <0>;
 			ambiq,iom-num = <0>;
 		};
 	};
@@ -147,7 +147,7 @@
 			drive-push-pull;
 			drive-strength = "0.5";
 			ambiq,iom-mspi = <0>;
-			ambiq,iom-nce-module = <0>;
+			ambiq,nce-src = <0>;
 			ambiq,iom-num = <1>;
 		};
 	};
@@ -164,7 +164,7 @@
 			drive-push-pull;
 			drive-strength = "0.5";
 			ambiq,iom-mspi = <0>;
-			ambiq,iom-nce-module = <0>;
+			ambiq,nce-src = <0>;
 			ambiq,iom-num = <2>;
 		};
 	};
diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb.dts b/boards/ambiq/apollo3p_evb/apollo3p_evb.dts
index 88b3cefbb2f..a40767bd371 100644
--- a/boards/ambiq/apollo3p_evb/apollo3p_evb.dts
+++ b/boards/ambiq/apollo3p_evb/apollo3p_evb.dts
@@ -117,23 +117,25 @@
 	status = "okay";
 };
 
-&spi0 {
-	compatible = "ambiq,spi";
-	pinctrl-0 = <&spi0_default>;
-	pinctrl-names = "default";
-	cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
-	clock-frequency = <DT_FREQ_M(1)>;
-	status = "okay";
+&iom0 {
+	spi0: spi {
+		pinctrl-0 = <&spi0_default>;
+		pinctrl-names = "default";
+		cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
+		clock-frequency = <DT_FREQ_M(1)>;
+		status = "okay";
+	};
 };
 
-&i2c3 {
-	compatible = "ambiq,i2c";
-	pinctrl-0 = <&i2c3_default>;
-	pinctrl-names = "default";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-	scl-gpios = <&gpio32_63 10 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
-	sda-gpios = <&gpio32_63 11 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
-	status = "okay";
+&iom3 {
+	i2c3: i2c {
+		pinctrl-0 = <&i2c3_default>;
+		pinctrl-names = "default";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		scl-gpios = <&gpio32_63 10 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
+		sda-gpios = <&gpio32_63 11 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
+		status = "okay";
+	};
 };
 
 &counter0 {
@@ -174,7 +176,6 @@
 };
 
 &adc0 {
-	compatible = "ambiq,adc";
 	pinctrl-0 = <&adc0_default>;
 	pinctrl-names = "default";
 	status = "disabled";
diff --git a/boards/ambiq/apollo3p_evb/apollo3p_evb_connector.dtsi b/boards/ambiq/apollo3p_evb/apollo3p_evb_connector.dtsi
index fc85edb4a63..73b8d42e107 100644
--- a/boards/ambiq/apollo3p_evb/apollo3p_evb_connector.dtsi
+++ b/boards/ambiq/apollo3p_evb/apollo3p_evb_connector.dtsi
@@ -88,5 +88,5 @@
 	};
 };
 
-ambiq_spi0: &spi0 {};
-ambiq_i2c3: &i2c3 {};
+ambiq_spi0: &iom0 {};
+ambiq_i2c3: &iom3 {};
diff --git a/boards/ambiq/apollo3p_evb/doc/index.rst b/boards/ambiq/apollo3p_evb/doc/index.rst
index a5f848c4f2c..1aa477d785d 100644
--- a/boards/ambiq/apollo3p_evb/doc/index.rst
+++ b/boards/ambiq/apollo3p_evb/doc/index.rst
@@ -21,34 +21,13 @@ For more information about the Apollo3 Blue Plus SoC and Apollo3 Blue Plus EVB b
 Supported Features
 ==================
 
-The Apollo3 Blue Plus EVB board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| STIMER    | on-chip    | stimer                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| WDT       | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| RADIO     | on-chip    | bluetooth                           |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-``boards/arm/apollo3p_evb/apollo3p_evb_defconfig``.
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 =========================
 
+.. zephyr:board-supported-runners::
+
 Flashing an application
 -----------------------
 
diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig b/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig
index 63595ffddbd..2bcd67ff17c 100644
--- a/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig
+++ b/boards/ambiq/apollo4p_blue_kxr_evb/Kconfig.defconfig
@@ -19,6 +19,9 @@ config MAIN_STACK_SIZE
 config BT_BUF_ACL_TX_COUNT
 	default 14
 
+config BT_BUF_EVT_RX_COUNT
+	default 15
+
 config BT_BUF_CMD_TX_SIZE
 	default $(UINT8_MAX)
 
diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi
index f8c20b0fad9..2cf596eadcd 100644
--- a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi
+++ b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb-pinctrl.dtsi
@@ -128,7 +128,7 @@
 			pinmux = <NCE57_P57>;
 			drive-push-pull;
 			drive-strength = "0.5";
-			ambiq,iom-nce-module = <32>;
+			ambiq,nce-src = <32>;
 		};
 	};
 	mspi1_default: mspi1_default{
@@ -141,7 +141,7 @@
 			pinmux = <NCE56_P56>;
 			drive-push-pull;
 			drive-strength = "0.5";
-			ambiq,iom-nce-module = <34>;
+			ambiq,nce-src = <34>;
 		};
 	};
 	mspi2_default: mspi2_default{
@@ -154,7 +154,7 @@
 			pinmux = <NCE52_P52>;
 			drive-push-pull;
 			drive-strength = "0.5";
-			ambiq,iom-nce-module = <36>;
+			ambiq,nce-src = <36>;
 		};
 	};
 
diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts
index cdcbcee689b..a4e8fdd6b43 100644
--- a/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts
+++ b/boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb.dts
@@ -89,29 +89,33 @@
 	status = "okay";
 };
 
-&i2c0 {
-	compatible = "ambiq,i2c";
-	pinctrl-0 = <&i2c0_default>;
-	pinctrl-names = "default";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-	scl-gpios = <&gpio0_31 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
-	sda-gpios = <&gpio0_31 6 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
-	status = "okay";
+&iom0 {
+	i2c0: i2c {
+		pinctrl-0 = <&i2c0_default>;
+		pinctrl-names = "default";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		scl-gpios = <&gpio0_31 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
+		sda-gpios = <&gpio0_31 6 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
+		status = "okay";
+	};
 };
 
-&spi1 {
-	compatible = "ambiq,spi";
-	pinctrl-0 = <&spi1_default>;
-	pinctrl-names = "default";
-	cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
-	clock-frequency = <DT_FREQ_M(1)>;
-	status = "okay";
+&iom1 {
+	spi1: spi {
+		pinctrl-0 = <&spi1_default>;
+		pinctrl-names = "default";
+		cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
+		clock-frequency = <DT_FREQ_M(1)>;
+		status = "okay";
+	};
 };
 
-&spi4 {
-	pinctrl-0 = <&spi4_default>;
-	pinctrl-names = "default";
-	status = "okay";
+&iom4 {
+	spi4: spi {
+		pinctrl-0 = <&spi4_default>;
+		pinctrl-names = "default";
+		status = "okay";
+	};
 };
 
 &mspi0 {
diff --git a/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst b/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst
index 81158fba6db..b6e891ef53f 100644
--- a/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst
+++ b/boards/ambiq/apollo4p_blue_kxr_evb/doc/index.rst
@@ -23,40 +23,13 @@ For more information about the Apollo4 Blue Plus SoC and Apollo4 Blue Plus KXR E
 Supported Features
 ==================
 
-The Apollo4 Blue Plus KXR EVB board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| STIMER    | on-chip    | stimer                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| WDT       | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| SPI(M)    | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| I2C(M)    | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| RADIO     | on-chip    | bluetooth                           |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/ambiq/apollo4p_blue_kxr_evb/apollo4p_blue_kxr_evb_defconfig`
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 =========================
 
+.. zephyr:board-supported-runners::
+
 Flashing an application
 -----------------------
 
diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi b/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi
index dbbb233485e..ccfdfd72974 100644
--- a/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi
+++ b/boards/ambiq/apollo4p_evb/apollo4p_evb-pinctrl.dtsi
@@ -142,7 +142,7 @@
 			pinmux = <NCE57_P57>;
 			drive-push-pull;
 			drive-strength = "0.5";
-			ambiq,iom-nce-module = <32>;
+			ambiq,nce-src = <32>;
 		};
 	};
 	mspi1_default: mspi1_default{
@@ -155,7 +155,7 @@
 			pinmux = <NCE56_P56>;
 			drive-push-pull;
 			drive-strength = "0.5";
-			ambiq,iom-nce-module = <34>;
+			ambiq,nce-src = <34>;
 		};
 	};
 	mspi2_default: mspi2_default{
@@ -168,7 +168,28 @@
 			pinmux = <NCE0_P0>;
 			drive-push-pull;
 			drive-strength = "0.5";
-			ambiq,iom-nce-module = <36>;
+			ambiq,nce-src = <36>;
+		};
+	};
+	sdio0_default: sdio0_default {
+		group0 {
+			pinmux = <SDIF_DAT1_P85>,
+				 <SDIF_DAT3_P87>,
+				 <SDIF_DAT4_P79>,
+				 <SDIF_DAT5_P80>,
+				 <SDIF_DAT6_P81>,
+				 <SDIF_DAT7_P82>;
+				 drive-strength = "1.0";
+		};
+		group1 {
+			pinmux =
+				 <SDIF_DAT0_P84>,
+				 <SDIF_DAT2_P86>,
+				 <SDIF_CMD_P83>,
+				 <SDIF_CLKOUT_P88>;
+				 drive-strength = "1.0";
+				 bias-pull-up;
+				 ambiq,pull-up-ohms = <12000>;
 		};
 	};
 };
diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb.dts b/boards/ambiq/apollo4p_evb/apollo4p_evb.dts
index 71ccc5399fd..cdac604591c 100644
--- a/boards/ambiq/apollo4p_evb/apollo4p_evb.dts
+++ b/boards/ambiq/apollo4p_evb/apollo4p_evb.dts
@@ -26,6 +26,7 @@
 		sw0 = &button0;
 		sw1 = &button1;
 		rtc = &rtc0;
+		sdhc0 = &sdio0;
 	};
 
 	leds {
@@ -76,7 +77,6 @@
 };
 
 &adc0 {
-	compatible = "ambiq,adc";
 	pinctrl-0 = <&adc0_default>;
 	pinctrl-names = "default";
 	status = "okay";
@@ -95,23 +95,25 @@
 	status = "okay";
 };
 
-&iom0_i2c {
-	compatible = "ambiq,i2c";
-	pinctrl-0 = <&i2c0_default>;
-	pinctrl-names = "default";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-	scl-gpios = <&gpio0_31 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
-	sda-gpios = <&gpio0_31 6 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
-	status = "okay";
+&iom0 {
+	i2c0: i2c {
+		pinctrl-0 = <&i2c0_default>;
+		pinctrl-names = "default";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		scl-gpios = <&gpio0_31 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
+		sda-gpios = <&gpio0_31 6 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
+		status = "okay";
+	};
 };
 
-&iom1_spi {
-	compatible = "ambiq,spi";
-	pinctrl-0 = <&spi1_default>;
-	pinctrl-names = "default";
-	cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
-	clock-frequency = <1000000>;
-	status = "okay";
+&iom1 {
+	spi1: spi {
+		pinctrl-0 = <&spi1_default>;
+		pinctrl-names = "default";
+		cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
+		clock-frequency = <1000000>;
+		status = "okay";
+	};
 };
 
 &mspi0 {
@@ -153,6 +155,19 @@
 	clk-source = <3>;
 };
 
+&sdio0 {
+	pinctrl-0 = <&sdio0_default>;
+	pinctrl-names = "default";
+	txdelay = <0>;
+	rxdelay = <0>;
+	status = "okay";
+	mmc {
+		compatible = "zephyr,mmc-disk";
+		disk-name = "SD2";
+		status = "okay";
+	};
+};
+
 zephyr_udc0: &usb {
 	vddusb33-gpios = <&gpio96_127 7 (GPIO_PULL_UP)>;
 	vddusb0p9-gpios = <&gpio96_127 5 (GPIO_PULL_UP)>;
diff --git a/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi b/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi
index e083db991e2..690ed85437d 100644
--- a/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi
+++ b/boards/ambiq/apollo4p_evb/apollo4p_evb_connector.dtsi
@@ -118,4 +118,4 @@
 	};
 };
 
-spi1: &iom1_spi {};
+ambiq_spi1: &iom1 {};
diff --git a/boards/ambiq/apollo4p_evb/doc/index.rst b/boards/ambiq/apollo4p_evb/doc/index.rst
index d2cc43e5bb4..ab8ccfd456a 100644
--- a/boards/ambiq/apollo4p_evb/doc/index.rst
+++ b/boards/ambiq/apollo4p_evb/doc/index.rst
@@ -22,36 +22,13 @@ For more information about the Apollo4 Plus SoC and Apollo4P EVB board:
 Supported Features
 ==================
 
-The Apollo4P EVB board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| STIMER    | on-chip    | stimer                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| WDT       | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| SPI(M)    | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| I2C(M)    | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/ambiq/apollo4p_evb/apollo4p_evb_defconfig`
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 =========================
 
+.. zephyr:board-supported-runners::
+
 Flashing an application
 -----------------------
 
diff --git a/boards/ambiq/apollo510_evb/CMakeLists.txt b/boards/ambiq/apollo510_evb/CMakeLists.txt
new file mode 100644
index 00000000000..218a0602483
--- /dev/null
+++ b/boards/ambiq/apollo510_evb/CMakeLists.txt
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+zephyr_library_sources(board.c)
diff --git a/boards/ambiq/apollo510_evb/Kconfig b/boards/ambiq/apollo510_evb/Kconfig
new file mode 100644
index 00000000000..6929d894103
--- /dev/null
+++ b/boards/ambiq/apollo510_evb/Kconfig
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2025 Ambiq Micro Inc. <www.ambiq.com>
+
+config BOARD_APOLLO510_EVB
+	select BOARD_EARLY_INIT_HOOK
diff --git a/boards/ambiq/apollo510_evb/Kconfig.apollo510_evb b/boards/ambiq/apollo510_evb/Kconfig.apollo510_evb
new file mode 100644
index 00000000000..38315f5fd69
--- /dev/null
+++ b/boards/ambiq/apollo510_evb/Kconfig.apollo510_evb
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2025 Ambiq Micro Inc. <www.ambiq.com>
+
+config BOARD_APOLLO510_EVB
+	select SOC_APOLLO510
diff --git a/boards/ambiq/apollo510_evb/Kconfig.defconfig b/boards/ambiq/apollo510_evb/Kconfig.defconfig
new file mode 100644
index 00000000000..9f9c9b2a196
--- /dev/null
+++ b/boards/ambiq/apollo510_evb/Kconfig.defconfig
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2025 Ambiq Micro Inc.
+
+if BOARD_APOLLO510_EVB
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 32768 if AMBIQ_STIMER_TIMER
+	default 96000000 if CORTEX_M_SYSTICK
+
+config LOG_BACKEND_SWO_FREQ_HZ
+	default 1000000
+	depends on LOG_BACKEND_SWO
+
+endif # BOARD_APOLLO510_EVB
diff --git a/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi b/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi
new file mode 100644
index 00000000000..3f173b61a03
--- /dev/null
+++ b/boards/ambiq/apollo510_evb/apollo510_evb-pinctrl.dtsi
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025 Ambiq Micro Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <apollo510/ambiq-apollo510-pinmux.h>
+
+&pinctrl {
+	uart0_default: uart0_default {
+		group1 {
+			pinmux = <UART0TX_P30>;
+		};
+		group2 {
+			pinmux = <UART0RX_P55>;
+			input-enable;
+		};
+	};
+	swo_default: swo_default {
+		group0 {
+			pinmux = <SWO_P28>;
+		};
+	};
+};
diff --git a/boards/ambiq/apollo510_evb/apollo510_evb.dts b/boards/ambiq/apollo510_evb/apollo510_evb.dts
new file mode 100644
index 00000000000..2303e43e125
--- /dev/null
+++ b/boards/ambiq/apollo510_evb/apollo510_evb.dts
@@ -0,0 +1,128 @@
+/dts-v1/;
+#include <ambiq/ambiq_apollo510.dtsi>
+#include "apollo510_evb-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "Ambiq Apollo510 evaluation board";
+	compatible = "ambiq,apollo510_evb";
+
+	chosen {
+		zephyr,itcm = &itcm;
+		zephyr,dtcm = &dtcm;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,uart-pipe = &uart0;
+		ambiq,xo32m = &xo32m_xtal;
+		ambiq,xo32k = &xo32k_xtal;
+		ambiq,extrefclk = &extrefclk;
+	};
+
+	aliases {
+		watchdog0 = &wdt0;
+		led0 = &led0;
+		led1 = &led1;
+		led2 = &led2;
+		sw0 = &button0;
+		sw1 = &button1;
+	};
+
+	sram0: memory@SSRAM_BASE_NAME {
+		compatible = "mmio-sram";
+		reg = <SSRAM_BASE_ADDR 0x200000>;
+	};
+
+	sram_no_cache: memory@20280000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20280000 0x100000>;
+		zephyr,memory-region = "SRAM_NO_CACHE";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led0: led_0 {
+			gpios = <&gpio160_191 5 GPIO_ACTIVE_LOW>;
+			label = "LED 0";
+		};
+		led1: led_1 {
+			gpios = <&gpio64_95 25 GPIO_ACTIVE_LOW>;
+			label = "LED 1";
+		};
+		led2: led_2 {
+			gpios = <&gpio64_95 28 GPIO_ACTIVE_LOW>;
+			label = "LED 2";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+		polling-mode;
+		button0: button_0 {
+			gpios = <&gpio64_95 29 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "BTN0";
+			zephyr,code = <INPUT_KEY_0>;
+			status = "okay";
+		};
+		button1: button_1 {
+			gpios = <&gpio64_95 30 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "BTN1";
+			zephyr,code = <INPUT_KEY_1>;
+			status = "okay";
+		};
+	};
+};
+
+&xo32m_xtal {
+	clock-frequency = <DT_FREQ_M(48)>;
+};
+
+&itm {
+	pinctrl-0 = <&swo_default>;
+	pinctrl-names = "default";
+};
+
+&uart0 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&stimer0 {
+	clk-source = <3>;
+};
+
+&wdt0 {
+	status = "okay";
+};
+
+&gpio0_31 {
+	status = "okay";
+};
+
+&gpio32_63 {
+	status = "okay";
+};
+
+&gpio64_95 {
+	status = "okay";
+};
+
+&gpio96_127 {
+	status = "okay";
+};
+
+&gpio128_159 {
+	status = "okay";
+};
+
+&gpio160_191 {
+	status = "okay";
+};
+
+&gpio192_223 {
+	status = "okay";
+};
diff --git a/boards/ambiq/apollo510_evb/apollo510_evb.yaml b/boards/ambiq/apollo510_evb/apollo510_evb.yaml
new file mode 100644
index 00000000000..704c2c00208
--- /dev/null
+++ b/boards/ambiq/apollo510_evb/apollo510_evb.yaml
@@ -0,0 +1,19 @@
+identifier: apollo510_evb
+name: Apollo510 EVB
+type: mcu
+arch: arm
+ram: 3072
+flash: 4096
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - uart
+  - watchdog
+  - gpio
+  - clock_control
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+vendor: ambiq
diff --git a/boards/ambiq/apollo510_evb/apollo510_evb_defconfig b/boards/ambiq/apollo510_evb/apollo510_evb_defconfig
new file mode 100644
index 00000000000..de397a65fbd
--- /dev/null
+++ b/boards/ambiq/apollo510_evb/apollo510_evb_defconfig
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2025 Ambiq Micro Inc.
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_HW_STACK_PROTECTION=y
+CONFIG_ARM_MPU=y
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_DEVICE_RUNTIME=y
diff --git a/boards/ambiq/apollo510_evb/board.c b/boards/ambiq/apollo510_evb/board.c
new file mode 100644
index 00000000000..b3cc847698c
--- /dev/null
+++ b/boards/ambiq/apollo510_evb/board.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2025 Ambiq Micro Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <am_mcu_apollo.h>
+
+#if DT_HAS_CHOSEN(ambiq_xo32m)
+#define XTAL_HS_FREQ DT_PROP(DT_CHOSEN(ambiq_xo32m), clock_frequency)
+#if DT_SAME_NODE(DT_CHOSEN(ambiq_xo32m), DT_NODELABEL(xo32m_xtal))
+#define XTAL_HS_MODE AM_HAL_CLKMGR_XTAL_HS_MODE_XTAL
+#elif DT_SAME_NODE(DT_CHOSEN(ambiq_xo32m), DT_NODELABEL(xo32m_ext))
+#define XTAL_HS_MODE AM_HAL_CLKMGR_XTAL_HS_MODE_EXT
+#endif
+#else
+#define XTAL_HS_FREQ 0
+#define XTAL_HS_MODE AM_HAL_CLKMGR_XTAL_HS_MODE_XTAL
+#endif
+
+#if DT_HAS_CHOSEN(ambiq_xo32k)
+#define XTAL_LS_FREQ DT_PROP(DT_CHOSEN(ambiq_xo32k), clock_frequency)
+#if DT_SAME_NODE(DT_CHOSEN(ambiq_xo32k), DT_NODELABEL(xo32k_xtal))
+#define XTAL_LS_MODE AM_HAL_CLKMGR_XTAL_LS_MODE_XTAL
+#elif DT_SAME_NODE(DT_CHOSEN(ambiq_xo32k), DT_NODELABEL(xo32k_ext))
+#define XTAL_LS_MODE AM_HAL_CLKMGR_XTAL_LS_MODE_EXT
+#endif
+#else
+#define XTAL_LS_FREQ 0
+#define XTAL_LS_MODE AM_HAL_CLKMGR_XTAL_LS_MODE_XTAL
+#endif
+
+#if DT_HAS_CHOSEN(ambiq_extrefclk)
+#define EXTREFCLK_FREQ DT_PROP(DT_CHOSEN(ambiq_extrefclk), clock_frequency)
+#else
+#define EXTREFCLK_FREQ 0
+#endif
+
+void board_early_init_hook(void)
+{
+	/* Set board related info into clock manager */
+	am_hal_clkmgr_board_info_t sClkmgrBoardInfo = {.sXtalHs.eXtalHsMode = XTAL_HS_MODE,
+						       .sXtalHs.ui32XtalHsFreq = XTAL_HS_FREQ,
+						       .sXtalLs.eXtalLsMode = XTAL_LS_MODE,
+						       .sXtalLs.ui32XtalLsFreq = XTAL_LS_FREQ,
+						       .ui32ExtRefClkFreq = EXTREFCLK_FREQ};
+	am_hal_clkmgr_board_info_set(&sClkmgrBoardInfo);
+
+	/* Default HFRC and HFRC2 to Free Running clocks */
+	am_hal_clkmgr_clock_config(AM_HAL_CLKMGR_CLK_ID_HFRC,
+				   AM_HAL_CLKMGR_HFRC_FREQ_FREE_RUN_APPROX_48MHZ, NULL);
+	am_hal_clkmgr_clock_config(AM_HAL_CLKMGR_CLK_ID_HFRC2,
+				   AM_HAL_CLKMGR_HFRC2_FREQ_FREE_RUN_APPROX_250MHZ, NULL);
+
+}
diff --git a/boards/ambiq/apollo510_evb/board.cmake b/boards/ambiq/apollo510_evb/board.cmake
new file mode 100644
index 00000000000..f4ec9988f02
--- /dev/null
+++ b/boards/ambiq/apollo510_evb/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Ambiq Micro Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=AP510NFA-CBR" "--iface=swd" "--speed=1000")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/ambiq/apollo510_evb/board.yml b/boards/ambiq/apollo510_evb/board.yml
new file mode 100644
index 00000000000..b42efb3b452
--- /dev/null
+++ b/boards/ambiq/apollo510_evb/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: apollo510_evb
+  full_name: Apollo510 SOC Evaluation Board
+  vendor: ambiq
+  socs:
+  - name: apollo510
diff --git a/boards/ambiq/apollo510_evb/doc/apollo510-soc-eval-board.jpg b/boards/ambiq/apollo510_evb/doc/apollo510-soc-eval-board.jpg
new file mode 100644
index 00000000000..906b08bae26
Binary files /dev/null and b/boards/ambiq/apollo510_evb/doc/apollo510-soc-eval-board.jpg differ
diff --git a/boards/ambiq/apollo510_evb/doc/index.rst b/boards/ambiq/apollo510_evb/doc/index.rst
new file mode 100644
index 00000000000..82916942776
--- /dev/null
+++ b/boards/ambiq/apollo510_evb/doc/index.rst
@@ -0,0 +1,75 @@
+.. zephyr:board:: apollo510_evb
+
+Apollo510 EVB is a board by Ambiq featuring their ultra-low power Apollo510 SoC.
+
+Hardware
+********
+
+- Apollo510 SoC with up to 250 MHz operating frequency
+- ARM® Cortex® M55 core
+- 64 kB Instruction Cache and 64 kB Data Cache
+- Up to 4 MB of non-volatile memory (NVM) for code/data
+- Up to 3 MB of low leakage / low power RAM for code/data
+- 256 kB Instruction Tightly Coupled RAM (ITCM)
+- 512 kB Data Tightly Coupled RAM (DTCM)
+
+For more information about the Apollo510 SoC and Apollo510 EVB board:
+
+- `Apollo510 Website`_
+- `Apollo510 Datasheet`_
+- `Apollo510 EVB Website`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+=========================
+
+.. zephyr:board-supported-runners::
+
+Flashing an application
+-----------------------
+
+Connect your device to your host computer using the JLINK USB port.
+The sample application :zephyr:code-sample:`hello_world` is used for this example.
+Build the Zephyr kernel and application, then flash it to the device:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: apollo510_evb
+   :goals: flash
+
+.. note::
+   ``west flash`` requires `SEGGER J-Link software`_ and `pylink`_ Python module
+   to be installed on you host computer.
+
+Open a serial terminal (minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Reset the board and you should be able to see on the corresponding Serial Port
+the following message:
+
+.. code-block:: console
+
+   Hello World! apollo510_evb
+
+.. _Apollo510 Website:
+   https://ambiq.com/apollo510/
+
+.. _Apollo510 Datasheet:
+   https://contentportal.ambiq.com/documents/20123/2877485/Apollo510-SoC-Datasheet.pdf
+
+.. _Apollo510 EVB Website:
+   For more information, please reach out to Sales and FAE.
+
+.. _SEGGER J-Link software:
+   https://www.segger.com/downloads/jlink
+
+.. _pylink:
+   https://github.com/Square/pylink
diff --git a/boards/amd/acp_6_0_adsp/acp_6_0_acp_adsp.dts b/boards/amd/acp_6_0_adsp/acp_6_0_adsp.dts
similarity index 100%
rename from boards/amd/acp_6_0_adsp/acp_6_0_acp_adsp.dts
rename to boards/amd/acp_6_0_adsp/acp_6_0_adsp.dts
diff --git a/boards/amd/acp_6_0_adsp/doc/index.rst b/boards/amd/acp_6_0_adsp/doc/index.rst
index fcc9221eafc..2812516f28e 100644
--- a/boards/amd/acp_6_0_adsp/doc/index.rst
+++ b/boards/amd/acp_6_0_adsp/doc/index.rst
@@ -26,15 +26,7 @@ Hardware
 Supported Features
 ==================
 
-The following hardware features are supported:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| I2S       | on-chip    | I2S controller                      |
-+-----------+------------+-------------------------------------+
-| DMIC(PDM) | on-chip    | PDM controller                      |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 System Clock
 ============
@@ -77,6 +69,8 @@ The bottom three variables are specific to acp_6_0.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Building
 ========
 
diff --git a/boards/amd/kv260_r5/doc/index.rst b/boards/amd/kv260_r5/doc/index.rst
index 9383dbd9df6..d939718e58a 100644
--- a/boards/amd/kv260_r5/doc/index.rst
+++ b/boards/amd/kv260_r5/doc/index.rst
@@ -19,20 +19,7 @@ Hardware
 Supported Features
 ==================
 
-The following hardware features are supported:
-
-+--------------+------------+----------------------+
-| Interface    | Controller | Driver/Component     |
-+==============+============+======================+
-| GIC          | on-chip    | generic interrupt    |
-|              |            | controller           |
-+--------------+------------+----------------------+
-| TTC          | on-chip    | system timer         |
-+--------------+------------+----------------------+
-| UART         | on-chip    | serial port          |
-+--------------+------------+----------------------+
-
-The kernel currently does not support other hardware features on this platform.
+.. zephyr:board-supported-hw::
 
 Devices
 ========
@@ -68,6 +55,8 @@ The following platform features are unsupported:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Currently the best way to run this sample is by loading it through remoteproc
 from the APU, running Linux, to the RPU, assuming the target board has a compatible
 Linux kernel.
diff --git a/boards/amd/kv260_r5/kv260_r5.dts b/boards/amd/kv260_r5/kv260_r5.dts
index 85fb1c26891..53ec1923e5d 100644
--- a/boards/amd/kv260_r5/kv260_r5.dts
+++ b/boards/amd/kv260_r5/kv260_r5.dts
@@ -19,6 +19,17 @@
 		zephyr,shell-uart = &uart1;
 		zephyr,ocm = &ocm;
 	};
+
+	aliases {
+		eeprom-0 = &eeprom0;
+		eeprom-1 = &eeprom1;
+	};
+
+	i2c_ref_clk: i2c_ref_clk {
+		compatible = "fixed-clock";
+		clock-frequency = <100000000>;
+		#clock-cells = <0>;
+	};
 };
 
 &uart1 {
@@ -35,3 +46,29 @@
 &psgpio {
 	status = "okay";
 };
+
+&i2c1 {
+	status = "okay";
+	clocks = <&i2c_ref_clk>;
+	clock-frequency = <400000>;
+
+	eeprom0: eeprom@50 {
+		compatible = "st,24c64", "atmel,at24";
+		reg = <0x50>;
+		size = <DT_SIZE_K(8)>;
+		pagesize = <32>;
+		address-width = <16>;
+		timeout = <5>;
+		read-only;
+	};
+
+	eeprom1: eeprom@51 {
+		compatible = "st,24c64", "atmel,at24";
+		reg = <0x51>;
+		size = <DT_SIZE_K(8)>;
+		pagesize = <32>;
+		address-width = <16>;
+		timeout = <5>;
+		read-only;
+	};
+};
diff --git a/boards/amd/kv260_r5/kv260_r5.yaml b/boards/amd/kv260_r5/kv260_r5.yaml
index 9cc92025e91..aa13a0350d5 100644
--- a/boards/amd/kv260_r5/kv260_r5.yaml
+++ b/boards/amd/kv260_r5/kv260_r5.yaml
@@ -5,6 +5,10 @@ toolchain:
   - zephyr
 ram: 65536
 flash: 32768
+supported:
+  - i2c
+  - eeprom
+  - gpio
 testing:
   ignore_tags:
     - net
diff --git a/boards/amd/kv260_r5/kv260_r5_defconfig b/boards/amd/kv260_r5/kv260_r5_defconfig
index 4b86de20d6b..f1bfa8f6707 100644
--- a/boards/amd/kv260_r5/kv260_r5_defconfig
+++ b/boards/amd/kv260_r5/kv260_r5_defconfig
@@ -13,5 +13,9 @@ CONFIG_UART_CONSOLE=y
 # Enable serial port
 CONFIG_UART_XLNX_PS=y
 
+# Enable I2C, EEPROM
+CONFIG_I2C=y
+CONFIG_EEPROM=y
+
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
 CONFIG_ARM_MPU=y
diff --git a/boards/amd/versalnet_rpu/Kconfig.versalnet_rpu b/boards/amd/versalnet_rpu/Kconfig.versalnet_rpu
new file mode 100644
index 00000000000..192725829db
--- /dev/null
+++ b/boards/amd/versalnet_rpu/Kconfig.versalnet_rpu
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config BOARD_VERSALNET_RPU
+	select SOC_AMD_VERSALNET_RPU
diff --git a/boards/amd/versalnet_rpu/board.cmake b/boards/amd/versalnet_rpu/board.cmake
new file mode 100644
index 00000000000..a624cc396d3
--- /dev/null
+++ b/boards/amd/versalnet_rpu/board.cmake
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+include(${ZEPHYR_BASE}/boards/common/xsdb.board.cmake)
diff --git a/boards/amd/versalnet_rpu/board.yml b/boards/amd/versalnet_rpu/board.yml
new file mode 100644
index 00000000000..6135a69a6ab
--- /dev/null
+++ b/boards/amd/versalnet_rpu/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: versalnet_rpu
+  full_name: Versal NET RPU development board
+  vendor: amd
+  socs:
+  - name: amd_versalnet_rpu
diff --git a/boards/amd/versalnet_rpu/doc/index.rst b/boards/amd/versalnet_rpu/doc/index.rst
new file mode 100644
index 00000000000..35d3ea5f22d
--- /dev/null
+++ b/boards/amd/versalnet_rpu/doc/index.rst
@@ -0,0 +1,75 @@
+.. zephyr:board:: versalnet_rpu
+
+Overview
+********
+This configuration provides support for the RPU(R52), real-time processing unit on Xilinx
+Versal Net SOC, it can operate as following:
+
+* Two independent R52 cores with their own TCMs (tightly coupled memories)
+* Or as a single dual lock step unit with the TCM.
+
+This processing unit is based on an ARM Cortex-R52 CPU, it also enables the following devices:
+
+* ARM GIC v3 Interrupt Controller
+* Global Timer Counter
+* SBSA UART
+
+Hardware
+********
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Devices
+========
+System Timer
+------------
+
+This board configuration uses a system timer tick frequency of 100 MHz.
+
+Serial Port
+-----------
+
+This board configuration uses a single serial communication channel with the
+on-chip UART0.
+
+Memories
+--------
+
+Although Flash, DDR and OCM memory regions are defined in the DTS file,
+all the code plus data of the application will be loaded in the sram0 region,
+which points to the DDR memory. The ocm0 memory area is currently available
+for usage, although nothing is placed there by default.
+
+Known Problems or Limitations
+==============================
+
+The following platform features are unsupported:
+
+* Only the first core of the R52 subsystem is supported.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Build and flash in the usual way. Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: versalnet_rpu
+   :goals: build flash
+
+You should see the following message on the console:
+
+.. code-block:: console
+
+   Hello World!
+
+
+References
+**********
+
+1. ARMv8-R Architecture Reference Manual (ARM DDI 0568A.c ID110520)
+2. Cortex-R52 and Cortex-R52F Technical Reference Manual (ARM DDI r1p4 100026_0104_01_en)
diff --git a/boards/amd/versalnet_rpu/support/xsdb.cfg b/boards/amd/versalnet_rpu/support/xsdb.cfg
new file mode 100644
index 00000000000..087ed4c85c1
--- /dev/null
+++ b/boards/amd/versalnet_rpu/support/xsdb.cfg
@@ -0,0 +1,44 @@
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+proc load_image args  {
+	set elf_file [lindex $args 0]
+
+	if { [info exists ::env(HW_SERVER_URL)] } {
+		connect -url $::env(HW_SERVER_URL)
+	} else {
+		connect
+	}
+
+	after 100
+	targets -set -nocase -filter {name =~ "Versal*"}
+	after 100
+	rst -system
+	after 100
+
+	if { [info exists ::env(PDI_FILE_PATH)] } {
+		device program $::env(PDI_FILE_PATH)
+	} else {
+		puts "Error: env variable PDI_FILE_PATH is not set"
+		exit
+	}
+
+	after 100
+	targets -set -nocase -filter {name =~ "DPC"}
+	after 100
+	# Configure timestamp generator to run global timer gracefully
+	# Ideally these registers should be set from bootloader (cdo)
+	mwr -force 0xeb5b0000 0x1
+	mwr -force 0xeb5b0020 100000000
+	after 100
+
+	targets -set -nocase -filter {name =~ "*Cortex-R52 #0.0"}
+	rst -proc
+	after 100
+	dow -force $elf_file
+	con
+	exit
+}
+
+load_image {*}$argv
diff --git a/boards/amd/versalnet_rpu/versalnet_rpu.dts b/boards/amd/versalnet_rpu/versalnet_rpu.dts
new file mode 100644
index 00000000000..73d034e20cb
--- /dev/null
+++ b/boards/amd/versalnet_rpu/versalnet_rpu.dts
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2025, Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <arm/xilinx/versalnet_r52.dtsi>
+
+/ {
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,ocm = &ocm;
+	};
+};
+
+&cpu0 {
+	 clock-frequency = <100000000>;
+};
+
+&soc {
+	sram0: memory@0 {
+		compatible = "mmio-sram";
+		reg = <0x00000 DT_SIZE_M(2048)>;
+	};
+};
+
+&ocm {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <100000000>;
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <100000000>;
+};
diff --git a/boards/amd/versalnet_rpu/versalnet_rpu.yaml b/boards/amd/versalnet_rpu/versalnet_rpu.yaml
new file mode 100644
index 00000000000..eccdf0ae37b
--- /dev/null
+++ b/boards/amd/versalnet_rpu/versalnet_rpu.yaml
@@ -0,0 +1,10 @@
+identifier: versalnet_rpu
+name: AMD Development board for Versal NET RPU
+arch: arm
+toolchain:
+  - zephyr
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+vendor: amd
diff --git a/boards/amd/versalnet_rpu/versalnet_rpu_defconfig b/boards/amd/versalnet_rpu/versalnet_rpu_defconfig
new file mode 100644
index 00000000000..4aec6a299f3
--- /dev/null
+++ b/boards/amd/versalnet_rpu/versalnet_rpu_defconfig
@@ -0,0 +1,9 @@
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable serial port
+CONFIG_UART_PL011=y
diff --git a/boards/andestech/adp_xc7k_ae350/doc/index.rst b/boards/andestech/adp_xc7k_ae350/doc/index.rst
index 3e290dd2f28..42767445c55 100644
--- a/boards/andestech/adp_xc7k_ae350/doc/index.rst
+++ b/boards/andestech/adp_xc7k_ae350/doc/index.rst
@@ -1,7 +1,4 @@
-.. _adp_xc7k_ae350:
-
-Andes ADP-XC7K AE350
-####################
+.. zephyr:board:: adp_xc7k
 
 Overview
 ********
@@ -52,40 +49,7 @@ The ADP-XC7K AE350 platform provides following hardware components:
 Supported Features
 ==================
 
-The ``adp_xc7k/ae350`` board configuration supports the following hardware features:
-
-+----------------+------------+----------------------+
-| Interface      | Controller | Driver/Component     |
-+================+============+======================+
-| PLIC           | on-chip    | interrupt_controller |
-+----------------+------------+----------------------+
-| RISC-V Machine | on-chip    | timer                |
-| Timer          |            |                      |
-+----------------+------------+----------------------+
-| GPIO           | on-chip    | gpio                 |
-+----------------+------------+----------------------+
-| UART           | on-chip    | serial               |
-+----------------+------------+----------------------+
-| COUNTER        | on-chip    | counter              |
-+----------------+------------+----------------------+
-| SPI            | on-chip    | spi                  |
-+----------------+------------+----------------------+
-| I2C            | on-chip    | i2c                  |
-+----------------+------------+----------------------+
-| EEPROM         | on-chip    | eeprom               |
-+----------------+------------+----------------------+
-| FLASH          | on-chip    | flash                |
-+----------------+------------+----------------------+
-| HWINFO         | on-chip    | syscon               |
-+----------------+------------+----------------------+
-| MAILBOX        | on-chip    | mbox                 |
-+----------------+------------+----------------------+
-| DMA            | on-chip    | dma                  |
-+----------------+------------+----------------------+
-| WATCHDOG       | on-chip    | wdt                  |
-+----------------+------------+----------------------+
-
-Other hardware features are not supported yet.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -206,6 +170,8 @@ settings are 115200 8N1.
 Programming and debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 For debugging zephyr applications or burning them into a flash, you will need to
 connect Andes ICE from host computer to ADP-XC7K board and execute the
 Andes ICE management software, ICEman, on this host computer.
diff --git a/boards/antmicro/index.rst b/boards/antmicro/index.rst
new file mode 100644
index 00000000000..d7393218659
--- /dev/null
+++ b/boards/antmicro/index.rst
@@ -0,0 +1,10 @@
+.. _boards-antmicro:
+
+Antmicro
+########
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*
diff --git a/boards/antmicro/myra_sip_baseboard/Kconfig.defconfig b/boards/antmicro/myra_sip_baseboard/Kconfig.defconfig
new file mode 100644
index 00000000000..21533cc29e9
--- /dev/null
+++ b/boards/antmicro/myra_sip_baseboard/Kconfig.defconfig
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_MYRA_SIP_BASEBOARD
+
+config SPI_STM32_INTERRUPT
+	default y
+	depends on SPI
+
+endif # BOARD_MYRA_SIP_BASEBOARD
diff --git a/boards/antmicro/myra_sip_baseboard/Kconfig.myra_sip_baseboard b/boards/antmicro/myra_sip_baseboard/Kconfig.myra_sip_baseboard
new file mode 100644
index 00000000000..5fce139d966
--- /dev/null
+++ b/boards/antmicro/myra_sip_baseboard/Kconfig.myra_sip_baseboard
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Antmicro
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MYRA_SIP_BASEBOARD
+	select SOC_MYRA
diff --git a/boards/antmicro/myra_sip_baseboard/board.cmake b/boards/antmicro/myra_sip_baseboard/board.cmake
new file mode 100644
index 00000000000..7595428a879
--- /dev/null
+++ b/boards/antmicro/myra_sip_baseboard/board.cmake
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+set(SUPPORTED_EMU_PLATFORMS renode)
+set(RENODE_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/support/myra_sip_baseboard.resc)
+set(RENODE_UART sysbus.lpuart1)
+
+board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_myra_sip_baseboard.cfg")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/antmicro/myra_sip_baseboard/board.yml b/boards/antmicro/myra_sip_baseboard/board.yml
new file mode 100644
index 00000000000..71575059420
--- /dev/null
+++ b/boards/antmicro/myra_sip_baseboard/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: myra_sip_baseboard
+  full_name: Myra SiP Baseboard
+  vendor: antmicro
+  socs:
+    - name: myra
diff --git a/boards/antmicro/myra_sip_baseboard/doc/img/myra_sip_baseboard.webp b/boards/antmicro/myra_sip_baseboard/doc/img/myra_sip_baseboard.webp
new file mode 100644
index 00000000000..c521ce0c462
Binary files /dev/null and b/boards/antmicro/myra_sip_baseboard/doc/img/myra_sip_baseboard.webp differ
diff --git a/boards/antmicro/myra_sip_baseboard/doc/index.rst b/boards/antmicro/myra_sip_baseboard/doc/index.rst
new file mode 100644
index 00000000000..0eb273c5245
--- /dev/null
+++ b/boards/antmicro/myra_sip_baseboard/doc/index.rst
@@ -0,0 +1,221 @@
+.. zephyr:board:: myra_sip_baseboard
+
+Overview
+********
+
+The Myra SiP Baseboard features Antmicro's **Myra** SiP, which integrates the **STM32G491REI6** MCU,
+128kB FRAM, and FTDI FT231XQ USB to UART converter. The board is equipped with temperature,
+humidity, and pressure sensors, designed to help monitor conditions in server rooms.
+
+The sensors are placed on a separate island that is detachable from the main PCB and can be
+installed directly in the required place. It provides local storage for data logging and a battery
+backup for protection against data loss. The board can be used as a building block for PoC solutions
+for monitoring environmental parameters.
+
+Key features include:
+
+- STM32G491REI6 MCU (Cortex-M4, 170 MHz)
+- 128 KB Fujitsu FRAM
+- FTDI FT231XQ USB to UART converter
+- 50 mm x 26.5 mm PCB
+- USB-C Connector for data and power
+- SHT45 temperature + humidity sensor
+- BME280 temperature + humidity + pressure sensor
+- QWIIC connectors for peripheral expansion
+- RTC with battery backup
+
+More information about the board can be found on `Antmicro's Open Hardware Portal <https://openhardware.antmicro.com/boards/environment-sensor-sip-baseboard>`_.
+
+Hardware
+********
+
+Myra SiP provides the following hardware:
+
+- **STM32G491REI6 MCU**:
+
+  - ARM Cortex-M4 CPU with FPU, up to 170 MHz
+  - Clock Sources:
+
+    - 4 to 48 MHz external crystal oscillator (HSE)
+    - 32 kHz crystal oscillator for RTC (LSE)
+    - Internal 16 MHz RC (±1%)
+    - Internal low-power 32 kHz RC (±5%)
+    - 2 PLLs for system clock, USB, audio, ADC
+  - RTC: Real-time clock with hardware calendar, alarms, and calibration
+  - Timers:
+
+    - 1x 32-bit timer and 2x 16-bit timers with up to 4x IC/OC/PWM or pulse counter and quadrature
+      (incremental) encoder input
+    - 3x 16-bit advanced motor control timers with up to 8x PWM channels, dead time generation,
+      emergency stop
+    - 1x 16-bit timer with 2x IC/OC, one OCN/PWM, dead time generation, emergency stop
+    - 2x watchdog timers (independent, window)
+    - 2x 16-bit basic timers
+    - SysTick timer
+    - 1x low-power timer
+  - I/Os: Up to 86 fast I/Os, most 5V tolerant
+  - Memory:
+
+    - 512 KB Flash memory with ECC and PCROP protection
+    - 96 KB SRAM including 32 KB with hardware parity check
+  - Analog peripherals:
+
+    - 3x 16-bit ADCs with up to 36 channels, hardware oversampling, and resolution up to 16-bit
+    - 4x 12-bit DAC channels
+    - 4x ultra-fast rail-to-rail analog comparators
+    - 4x operational amplifiers with built-in PGA
+    - Internal temperature sensor and voltage reference with support for three output voltages
+      (2.048 V, 2.5 V, 2.9 V)
+  - Communication Interfaces:
+
+    - 2x FDCAN controllers supporting flexible data rate
+    - 3x I2C Fast Mode Plus (1 Mbit/s) with 20 mA current sink, SMBus/PMBus support
+    - 5x USART/UART (ISO 7816, LIN, IrDA, modem control)
+    - 1x LPUART
+    - 3x SPI interfaces (2x with multiplexed half-duplex I²S)
+    - 1x SAI (serial audio interface)
+    - USB 2.0 full-speed with LPM and BCD support
+    - IRTIM (infrared interface)
+    - USB Type-C™ / USB Power Delivery (UCPD)
+  - Other Peripherals:
+
+    - 16-channel DMA controller
+    - True Random Number Generator (RNG)
+    - CRC calculation unit, 96-bit unique ID
+    - Development support: SWD, JTAG, Embedded Trace Macrocell™
+    - ECOPACK2® compliant packages
+
+- **128 KB Fujitsu MB85RS1MT FRAM**: Local storage for data logging, allowing non-volatile memory storage.
+
+- **FTDI FT231XQ USB to UART converter**: Provides a reliable USB to UART interface.
+
+
+More information about STM32G491RE can be found here:
+
+- `STM32G491RE on www.st.com`_
+
+Other board's peripherals:
+--------------------------
+
+- USB-C Connector: For data and power.
+- SHT45 sensor:
+
+  - Relative humidity accuracy: ±1.0% RH
+  - Operating humidity range: 0-100% RH
+  - Temperature accuracy: ±0.1°C
+  - Operating temperature range: -40°C to 125°C
+- BME280 sensor:
+
+  - Relative humidity accuracy: ±3% RH
+  - Temperature accuracy: ±1°C
+  - Pressure accuracy: ±1 hPa
+  - Operating temperature range: -40°C to 85°C
+  - Pressure range: 300-1100 hPa
+- QWIIC connectors: For easy peripheral expansion.
+
+Supported Features
+------------------
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+-------------------
+
+Antmicro's Myra SiP Baseboard provides the following default pin mappings for peripherals:
+
+.. rst-class:: rst-columns
+
+- LPUART_1_TX : PA2
+- LPUART_1_RX : PA3
+- I2C_1_SCL : PB8
+- I2C_1_SDA : PB9
+- SPI_CS2 : PB2
+- SPI_CS3 : PA7
+- SPI_2_SCK : PB13
+- SPI_2_MISO : PB14
+- SPI_2_MOSI : PB15
+- PWM_2_CH1 : PA5
+- USER_PB : PC13
+- LD2 : PA5
+- ADC1_IN1 : PA0
+- DAC1_OUT1 : PA4
+- USB_MCU_N : PA11
+- USB_MCU_P : PA12
+- SWDIO-JMTS : PA13
+- SWCLK-JTCK : PA14
+- JTDI : PA15
+- JTDO : PB3
+- JTRST : PB4
+- FRAM_HOLD (ACTIVE LOW) : PB10
+- FRAM_WP (ACTIVE LOW) : PB11
+- FRAM_CS (ACTIVE LOW) : PB12
+- GPIO_PC10 : PC10
+- GPIO_PC11 : PC11
+- GPIO_PC12 : PC12
+- PF0_OSC : PF0
+
+System Clock
+------------
+
+System clock can be driven by an internal or an external oscillator, as well as by the main PLL
+clock. By default, system clock is driven by PLL clock at 170MHz (boost mode selected), which in
+turn, is driven by the 8MHz high speed external oscillator (HSE). While the HSE oscillator is
+capable of operating at frequencies up to 48 MHz by default, in this configuration, it is
+specifically set to 8 MHz.
+
+Serial Port
+-----------
+
+The Myra SiP Baseboard has 5 U(S)ARTs. The Zephyr console output is assigned to LPUART1. The default
+settings are 115200 8N1.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``myra_sip_baseboard`` board target can be built and flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run` for more details).
+
+Flashing
+********
+
+This board has a USB-JTAG interface and can be used with OpenOCD.
+
+Connect the Myra SiP Baseboard to your host computer using the USB port, then build and flash
+the application. Here is an example for :zephyr:code-sample:`hello_world`.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: myra_sip_baseboard
+   :goals: build flash
+
+Then run a serial host program to connect with the Myra SiP Baseboard, e.g. using picocom:
+
+.. code-block:: console
+
+   $ picocom /dev/ttyUSB0 -b 115200
+
+.. warning::
+   The board has only one port that is used for both programming and the console. For this reason, it is
+   recommended to set ``CONFIG_BOOT_DELAY`` to an arbitrary value. This is especially important when
+   running twister tests on the device. You should then also use the ``--flash-before`` and
+   ``--device-flash-timeout=120`` options:
+
+   .. code-block:: console
+
+       $ scripts/twister --device-testing --device-serial /dev/ttyUSB0 --device-serial-baud 115200 -p myra_sip_baseboard --flash-before --device-flash-timeout=120 -v
+
+Debugging
+*********
+
+You can debug an application in the usual way. Here is an example for the
+:zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: myra_sip_baseboard
+   :maybe-skip-config:
+   :goals: debug
+
+.. _STM32G491RE on www.st.com:
+   https://www.st.com/en/microcontrollers-microprocessors/stm32g491re.html
diff --git a/boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.dts b/boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.dts
new file mode 100644
index 00000000000..fc815cd352b
--- /dev/null
+++ b/boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.dts
@@ -0,0 +1,220 @@
+/*
+ * Copyright (c) 2024 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <antmicro/myra.dtsi>
+
+/ {
+	compatible = "antmicro,myra-sip-baseboard";
+	model = "Myra SiP Baseboard";
+
+	chosen {
+		zephyr,console = &lpuart1;
+		zephyr,shell-uart = &lpuart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,canbus = &fdcan1;
+		zephyr,code-partition = &slot0_partition;
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+		green_led: led_0 {
+			gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
+			label = "User LD2";
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		green_pwm_led: green_pwm_led {
+			pwms = <&pwm2 1 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button: button {
+			label = "User";
+			gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	aliases {
+		led0 = &green_led;
+		mcuboot-led0 = &green_led;
+		pwm-led0 = &green_pwm_led;
+		sw0 = &user_button;
+		watchdog0 = &iwdg;
+		volt-sensor0 = &vref;
+		volt-sensor1 = &vbat;
+		rtc = &rtc;
+		eeprom-0 = &mb85rs1mt;
+	};
+};
+
+&clk_lse {
+	status = "okay";
+};
+
+&clk_lsi {
+	status = "okay";
+};
+
+&clk_hsi48 {
+	status = "okay";
+};
+
+&clk_hse {
+	clock-frequency = <DT_FREQ_M(8)>;
+	status = "okay";
+};
+
+&pll {
+	div-m = <2>;
+	mul-n = <85>;
+	div-p = <7>;
+	div-q = <2>;
+	div-r = <2>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(170)>;
+	ahb-prescaler = <1>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+};
+
+&lpuart1 {
+	pinctrl-0 = <&lpuart1_tx_pa2 &lpuart1_rx_pa3>;
+	pinctrl-1 = <&analog_pa2 &analog_pa3>;
+	pinctrl-names = "default", "sleep";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	bme280@76 {
+		compatible = "bosch,bme280";
+		reg = <0x76>;
+	};
+
+	sht4x@44 {
+		compatible = "sensirion,sht4x";
+		repeatability = <2>;
+		reg = <0x44>;
+	};
+};
+
+&timers2 {
+	status = "okay";
+
+	pwm2: pwm {
+		status = "okay";
+		pinctrl-0 = <&tim2_ch1_pa5>;
+		pinctrl-names = "default";
+	};
+};
+
+stm32_lp_tick_source: &lptim1 {
+	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
+		<&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
+	status = "okay";
+};
+
+&rtc {
+	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
+		 <&rcc STM32_SRC_LSE RTC_SEL(1)>;
+	status = "okay";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 DT_SIZE_K(34)>;
+		};
+		slot0_partition: partition@8800 {
+			label = "image-0";
+			reg = <0x00008800 DT_SIZE_K(240)>;
+		};
+		slot1_partition: partition@44800 {
+			label = "image-1";
+			reg = <0x00044800 DT_SIZE_K(234)>;
+		};
+		/* Set 4Kb of storage at the end of the 512Kb of flash */
+		storage_partition: partition@7f000 {
+			label = "storage";
+			reg = <0x0007f000 DT_SIZE_K(4)>;
+		};
+	};
+};
+
+&iwdg {
+	status = "okay";
+};
+
+&rng {
+	status = "okay";
+};
+
+&adc1 {
+	pinctrl-0 = <&adc1_in1_pa0>;
+	pinctrl-names = "default";
+	st,adc-clock-source = "SYNC";
+	st,adc-prescaler = <4>;
+	status = "okay";
+};
+
+&die_temp {
+	status = "okay";
+};
+
+&dac1 {
+	pinctrl-0 = <&dac1_out1_pa4>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&fdcan1 {
+	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>,
+		 <&rcc STM32_SRC_HSE FDCAN_SEL(0)>;
+	pinctrl-0 = <&fdcan1_rx_pa11 &fdcan1_tx_pa12>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&vref {
+	status = "okay";
+};
+
+&vbat {
+	status = "okay";
+};
+
+&timers6 {
+	status = "okay";
+	st,prescaler = <1>;
+};
+
+&timers7 {
+	status = "okay";
+	st,prescaler = <1>;
+};
diff --git a/boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.yaml b/boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.yaml
new file mode 100644
index 00000000000..77fe8017c5d
--- /dev/null
+++ b/boards/antmicro/myra_sip_baseboard/myra_sip_baseboard.yaml
@@ -0,0 +1,28 @@
+identifier: myra_sip_baseboard
+name: Myra SiP Baseboard
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 128
+flash: 512
+supported:
+  - nvs
+  - pwm
+  - i2c
+  - gpio
+  - usb device
+  - spi
+  - watchdog
+  - dma
+  - can
+  - rtc
+  - sensors
+  - eeprom
+testing:
+  timeout_multiplier: 3
+  renode:
+    uart: sysbus.lpuart1
+    resc: boards/antmicro/myra_sip_baseboard/support/myra_sip_baseboard.resc
+vendor: antmicro
diff --git a/boards/antmicro/myra_sip_baseboard/myra_sip_baseboard_defconfig b/boards/antmicro/myra_sip_baseboard/myra_sip_baseboard_defconfig
new file mode 100644
index 00000000000..163b6236b23
--- /dev/null
+++ b/boards/antmicro/myra_sip_baseboard/myra_sip_baseboard_defconfig
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SERIAL=y
+CONFIG_GPIO=y
+CONFIG_CLOCK_CONTROL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
diff --git a/boards/antmicro/myra_sip_baseboard/support/myra_sip_baseboard.repl b/boards/antmicro/myra_sip_baseboard/support/myra_sip_baseboard.repl
new file mode 100644
index 00000000000..7d0aab51693
--- /dev/null
+++ b/boards/antmicro/myra_sip_baseboard/support/myra_sip_baseboard.repl
@@ -0,0 +1,87 @@
+flash0: Memory.MappedMemory @ sysbus 0x8000000
+    size: 0x80000
+
+sram0: Memory.MappedMemory @ sysbus 0x20000000
+    size: 0x1c000
+
+timers2: Timers.STM32_Timer @ sysbus <0x40000000, +0x400>
+    frequency: 10000000
+    initialLimit: 0xffffffff
+    ->nvic0@28
+
+timers6: Timers.STM32_Timer @ sysbus <0x40001000, +0x400>
+    frequency: 10000000
+    initialLimit: 0xffffffff
+    ->nvic0@54
+
+timers7: Timers.STM32_Timer @ sysbus <0x40001400, +0x400>
+    frequency: 10000000
+    initialLimit: 0xffffffff
+    ->nvic0@55
+
+clk_lse: Python.PythonPeripheral @ sysbus 0x40007000
+    size: 0x4
+    initable: true
+    filename: "scripts/pydev/rolling-bit.py"
+
+gpioa: GPIOPort.STM32_GPIOPort @ sysbus <0x48000000, +0x400>
+
+gpiob: GPIOPort.STM32_GPIOPort @ sysbus <0x48000400, +0x400>
+
+gpioc: GPIOPort.STM32_GPIOPort @ sysbus <0x48000800, +0x400>
+
+gpiod: GPIOPort.STM32_GPIOPort @ sysbus <0x48000c00, +0x400>
+
+gpioe: GPIOPort.STM32_GPIOPort @ sysbus <0x48001000, +0x400>
+
+gpiof: GPIOPort.STM32_GPIOPort @ sysbus <0x48001400, +0x400>
+
+gpiog: GPIOPort.STM32_GPIOPort @ sysbus <0x48001800, +0x400>
+
+greenled: Miscellaneous.LED @ gpioa 0x5
+
+gpioa:
+    5 -> greenled@0
+
+nvic0: IRQControllers.NVIC @ {
+    sysbus new Bus.BusPointRegistration { address: 0xe000e000; cpu: cpu0 }
+}
+    -> cpu0@0
+
+cpu0: CPU.CortexM @ sysbus
+    cpuType: "cortex-m4f"
+    nvic: nvic0
+
+i2c1: I2C.STM32F7_I2C @ sysbus 0x40005400
+    EventInterrupt->nvic0@31
+    ErrorInterrupt->nvic0@32
+
+sht4x: I2C.SHT45 @ i2c1 0x44
+
+adc1: Analog.STM32_ADC @ sysbus 0x50000000
+    IRQ->nvic0@18
+
+lpuart1: UART.STM32F7_USART @ sysbus 0x40008000
+    frequency: 200000000
+    lowPowerMode: true
+    IRQ->nvic0@91
+
+rcc: Python.PythonPeripheral @ sysbus 0x40021000
+    size: 0x400
+    initable: true
+    filename: "scripts/pydev/flipflop.py"
+
+rng: Miscellaneous.STM32F4_RNG @ sysbus 0x50060800
+    ->nvic0@90
+
+rtc: Timers.STM32F4_RTC @ sysbus 0x40002800
+    AlarmIRQ->nvic0@41
+
+spi2: SPI.STM32SPI @ sysbus 0x40003800
+    IRQ->nvic0@36
+
+iwdg: Timers.STM32_IndependentWatchdog @ sysbus 0x40003000
+    frequency: 32000
+
+dwt: Miscellaneous.DWT @ sysbus 0xE0001000
+    frequency: 72000000
diff --git a/boards/antmicro/myra_sip_baseboard/support/myra_sip_baseboard.resc b/boards/antmicro/myra_sip_baseboard/support/myra_sip_baseboard.resc
new file mode 100644
index 00000000000..2d794d7c7f5
--- /dev/null
+++ b/boards/antmicro/myra_sip_baseboard/support/myra_sip_baseboard.resc
@@ -0,0 +1,17 @@
+:name: Myra SiP Baseboard
+:description: This script is prepared to run Zephyr on the Myra SiP Baseboard.
+
+$name?="Myra SiP Baseboard"
+
+using sysbus
+mach create $name
+machine LoadPlatformDescription $ORIGIN/myra_sip_baseboard.repl
+
+showAnalyzer lpuart1
+
+macro reset
+"""
+    sysbus LoadELF $elf
+    cpu0 VectorTableOffset `sysbus GetSymbolAddress "_vector_table"`
+"""
+runMacro $reset
diff --git a/boards/antmicro/myra_sip_baseboard/support/openocd_myra_sip_baseboard.cfg b/boards/antmicro/myra_sip_baseboard/support/openocd_myra_sip_baseboard.cfg
new file mode 100644
index 00000000000..dc278051fc9
--- /dev/null
+++ b/boards/antmicro/myra_sip_baseboard/support/openocd_myra_sip_baseboard.cfg
@@ -0,0 +1,13 @@
+adapter driver ft232r
+adapter speed 1000
+
+ft232r vid_pid 0x0403 0x6015
+ft232r tck_num RTS
+ft232r tms_num DTR
+ft232r tdi_num RI
+ft232r tdo_num CTS
+ft232r trst_num DSR
+ft232r srst_num DCD
+
+ft232r restore_serial 0x0015
+source [find target/stm32g4x.cfg]
diff --git a/boards/arduino/due/arduino_due-pinctrl.dtsi b/boards/arduino/due/arduino_due-pinctrl.dtsi
index 08f369eed7d..410df4f7eea 100644
--- a/boards/arduino/due/arduino_due-pinctrl.dtsi
+++ b/boards/arduino/due/arduino_due-pinctrl.dtsi
@@ -3,7 +3,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <dt-bindings/pinctrl/sam3XXh-pinctrl.h>
+#include <dt-bindings/pinctrl/sam3XXe-pinctrl.h>
 
 &pinctrl {
 	twi0_default: twi0_default {
@@ -53,10 +53,25 @@
 		};
 	};
 
+	spi0_default: spi0_default {
+		group1 {
+			pinmux = <PA25A_SPI0_MISO>,
+				 <PA26A_SPI0_MOSI>,
+				 <PA27A_SPI0_SPCK>;
+		};
+	};
+
 	pwm0_default: pwm0_default {
 		group1 {
 			pinmux = <PC4B_PWM_PWML1>,
 				 <PC5B_PWM_PWMH1>;
 		};
 	};
+
+	adc0_default: adc0_default {
+		group1 {
+			pinmux = <PA24X_ADC_AD6>,
+				 <PA16X_ADC_AD7>;
+		};
+	};
 };
diff --git a/boards/arduino/due/arduino_due.dts b/boards/arduino/due/arduino_due.dts
index bbfc92b110c..0e9c4693abe 100644
--- a/boards/arduino/due/arduino_due.dts
+++ b/boards/arduino/due/arduino_due.dts
@@ -4,6 +4,7 @@
 
 #include <atmel/sam3x.dtsi>
 #include "arduino_due-pinctrl.dtsi"
+#include "arduino_r3_connector.dtsi"
 
 / {
 	model = "Arduino Due with an Atmel SAM3X8E SoC";
@@ -57,6 +58,13 @@
 	pinctrl-names = "default";
 };
 
+&spi0 {
+	status = "okay";
+	pinctrl-0 = <&spi0_default>;
+	pinctrl-names = "default";
+	cs-gpios = <&pioa 28 GPIO_ACTIVE_LOW>;
+};
+
 &uart {
 	status = "okay";
 	current-speed = <115200>;
diff --git a/boards/arduino/due/arduino_due.yaml b/boards/arduino/due/arduino_due.yaml
index 21a71527ffe..12f9ba82ad4 100644
--- a/boards/arduino/due/arduino_due.yaml
+++ b/boards/arduino/due/arduino_due.yaml
@@ -5,10 +5,10 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 flash: 512
 ram: 96
 supported:
+  - adc
   - arduino_i2c
   - gpio
   - watchdog
diff --git a/boards/arduino/due/arduino_r3_connector.dtsi b/boards/arduino/due/arduino_r3_connector.dtsi
new file mode 100644
index 00000000000..16fcfa2674f
--- /dev/null
+++ b/boards/arduino/due/arduino_r3_connector.dtsi
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2025 Arduino SA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	arduino_header: connector {
+		compatible = "arduino-header-r3";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = < 0 0 &pioa 16 0>,	/* A0 */
+			   < 1 0 &pioa 24 0>,	/* A1 */
+			   < 2 0 &pioa 23 0>,	/* A2 */
+			   < 3 0 &pioa 22 0>,	/* A3 */
+			   < 4 0 &pioa  6 0>,	/* A4 */
+			   < 5 0 &pioa  4 0>,	/* A5 */
+			   < 6 0 &pioa  8 0>,	/* D0 */
+			   < 7 0 &pioa  9 0>,	/* D1 */
+			   < 8 0 &piob 25 0>,	/* D2 */
+			   < 9 0 &pioc 28 0>,	/* D3 */
+			   <10 0 &pioa 29 0>,	/* D4 */
+			   <11 0 &pioc 25 0>,	/* D5 */
+			   <12 0 &pioc 24 0>,	/* D6 */
+			   <13 0 &pioc 23 0>,	/* D7 */
+			   <14 0 &pioc 22 0>,	/* D8 */
+			   <15 0 &pioc 21 0>,	/* D9 */
+			   <16 0 &pioa 28 0>,	/* D10 */
+			   <17 0 &piod  7 0>,	/* D11 */
+			   <18 0 &piod  8 0>,	/* D12 */
+			   <19 0 &piob 27 0>,	/* D13 */
+			   <20 0 &pioa 17 0>,	/* D20 */
+			   <21 0 &pioa 18 0>;	/* D21 */
+	};
+};
diff --git a/boards/arduino/due/doc/index.rst b/boards/arduino/due/doc/index.rst
index e1eda346744..9bce2aa68e3 100644
--- a/boards/arduino/due/doc/index.rst
+++ b/boards/arduino/due/doc/index.rst
@@ -1,7 +1,4 @@
-.. _arduino_due:
-
-Arduino Due
-###########
+.. zephyr:board:: arduino_due
 
 Overview
 ********
@@ -23,41 +20,17 @@ the processor.
 .. note::
    This configuration is not supported by Arduino.
 
-.. image:: img/arduino_due.jpg
-     :align: center
-     :alt: Arduino Due
-
 Hardware
 ********
+
 Supported Features
 ==================
 
-The arduino_due board configuration supports the following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| NVIC      | on-chip    | nested vectored      |
-|           |            | interrupt controller |
-+-----------+------------+----------------------+
-| SYSTICK   | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial port          |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| Watchdog  | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features are not currently supported by the Zephyr kernel.
+.. zephyr:board-supported-hw::
+
 See `Arduino Due website`_ and `Atmel SAM3X8E Datasheet`_ for a complete
 list of Arduino Due board hardware features.
 
-The default configuration can be found in the Kconfig
-:zephyr_file:`boards/arduino/due/arduino_due_defconfig`.
-
 .. note::
    For I2C, pull-up resistors are required for using SCL1 and SDA1 (near IO13).
 
@@ -131,6 +104,8 @@ default, is utilizing this controller.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4.yaml b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4.yaml
index 3917682bd21..bdabab68a16 100644
--- a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4.yaml
+++ b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m4.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 288
 flash: 1024
 supported:
diff --git a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts
index 5d6e0dd7d88..7505ba0f2df 100644
--- a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts
+++ b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts
@@ -252,3 +252,9 @@ zephyr_udc0: &usbotg_fs {
 	pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
 	pinctrl-names = "default";
 };
+
+/* alias used by display shields */
+zephyr_mipi_dsi: &mipi_dsi {};
+
+/* alias used by LCD display shields */
+zephyr_lcd_controller: &ltdc {};
diff --git a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.yaml b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.yaml
index b637d14017b..285330d8b01 100644
--- a/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.yaml
+++ b/boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 512
 flash: 1024
 supported:
diff --git a/boards/arduino/giga_r1/doc/index.rst b/boards/arduino/giga_r1/doc/index.rst
index 696844a71fa..508f6363151 100644
--- a/boards/arduino/giga_r1/doc/index.rst
+++ b/boards/arduino/giga_r1/doc/index.rst
@@ -1,7 +1,4 @@
-.. _arduino_giga_r1_board:
-
-Arduino GIGA R1 WiFi
-####################
+.. zephyr:board:: arduino_giga_r1
 
 Overview
 ********
@@ -22,10 +19,6 @@ The board features:
 - Audio jack
 - ATECC608A secure element
 
-.. image:: img/arduino_giga_r1.jpg
-     :align: center
-     :alt: Arduino GIGA R1 WiFi
-
 More information about the board, including the datasheet, pinout and
 schematics, can be found at the `Arduino GIGA website`_.
 
@@ -38,39 +31,7 @@ More information about STM32H747XIH6 can be found here:
 Supported Features
 ==================
 
-The current Zephyr ``arduino_giga_r1_m7`` board configuration supports the
-following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| IPM       | on-chip    | virtual mailbox based on HSEM       |
-+-----------+------------+-------------------------------------+
-| FMC       | on-chip    | memc (SDRAM)                        |
-+-----------+------------+-------------------------------------+
-| QSPI      | on-chip    | QSPI flash                          |
-+-----------+------------+-------------------------------------+
-| RADIO     | Murata 1DX | WiFi and Bluetooth module           |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr port.
+.. zephyr:board-supported-hw::
 
 Fetch Binary Blobs
 ******************
@@ -102,6 +63,8 @@ two cores. This is done in 3 ways:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``arduino_giga_r1`` board should be built per core target,
 using either ``arduino_giga_r1/stm32h747xx/m7`` or ``arduino_giga_r1/stm32h747xx/m4`` as the target.
 
diff --git a/boards/arduino/mkrzero/arduino_mkrzero-pinctrl.dtsi b/boards/arduino/mkrzero/arduino_mkrzero-pinctrl.dtsi
index df09f3aed8f..f4eadc39c95 100644
--- a/boards/arduino/mkrzero/arduino_mkrzero-pinctrl.dtsi
+++ b/boards/arduino/mkrzero/arduino_mkrzero-pinctrl.dtsi
@@ -6,6 +6,18 @@
 #include <dt-bindings/pinctrl/samd21-da1gXabcd-pinctrl.h>
 
 &pinctrl {
+	adc_default: adc_default {
+		group1 {
+			pinmux = <PA2B_ADC_AIN0>,
+				 <PB2B_ADC_AIN10>,
+				 <PB3B_ADC_AIN11>,
+				 <PA4B_ADC_AIN4>,
+				 <PA5B_ADC_AIN5>,
+				 <PA6B_ADC_AIN6>,
+				 <PA7B_ADC_AIN7>;
+		};
+	};
+
 	dac_default: dac_default {
 		group1 {
 			pinmux = <PA2B_DAC_VOUT>;
@@ -18,6 +30,7 @@
 				 <PA9C_SERCOM0_PAD1>;
 		};
 	};
+
 	sercom1_spi_default: sercom1_spi_default {
 		group1 {
 			pinmux = <PA16C_SERCOM1_PAD0>,
diff --git a/boards/arduino/mkrzero/arduino_mkrzero.dts b/boards/arduino/mkrzero/arduino_mkrzero.dts
index a0f26d57fa0..6a30c3be9d7 100644
--- a/boards/arduino/mkrzero/arduino_mkrzero.dts
+++ b/boards/arduino/mkrzero/arduino_mkrzero.dts
@@ -106,6 +106,13 @@
 	pinctrl-names = "default";
 };
 
+&adc {
+	status = "okay";
+
+	pinctrl-0 = <&adc_default>;
+	pinctrl-names = "default";
+};
+
 &dac0 {
 	status = "okay";
 
diff --git a/boards/arduino/mkrzero/arduino_mkrzero.yaml b/boards/arduino/mkrzero/arduino_mkrzero.yaml
index 9b695e86097..ed631fb6262 100644
--- a/boards/arduino/mkrzero/arduino_mkrzero.yaml
+++ b/boards/arduino/mkrzero/arduino_mkrzero.yaml
@@ -7,7 +7,6 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - counter
diff --git a/boards/arduino/mkrzero/doc/index.rst b/boards/arduino/mkrzero/doc/index.rst
index b6f92d96930..3e528152131 100644
--- a/boards/arduino/mkrzero/doc/index.rst
+++ b/boards/arduino/mkrzero/doc/index.rst
@@ -1,7 +1,4 @@
-.. _arduino_mkrzero:
-
-Arduino MKR Zero
-####################
+.. zephyr:board:: arduino_mkrzero
 
 Overview
 ********
@@ -9,10 +6,6 @@ Overview
 The Arduino MKR Zero built with smaller MKR form factor and powered by Atmel's SAMD21 MCU.
 This board come with microSD card holder that allows you to play with music files with no extra hardware.
 
-.. image:: img/arduino_mkrzero.jpg
-     :align: center
-     :alt: Arduino MKR Zero
-
 Hardware
 ********
 
@@ -27,46 +20,7 @@ Hardware
 Supported Features
 ==================
 
-The arduino_mkrzero board configuration supports the following hardware
-features:
-
-+-----------+------------+------------------------------------------+
-| Interface | Controller | Driver/Component                         |
-+===========+============+==========================================+
-| ADC       | on-chip    | Analog to digital converter              |
-+-----------+------------+------------------------------------------+
-| COUNTER   | on-chip    | Pulse counter                            |
-+-----------+------------+------------------------------------------+
-| DMA       | on-chip    | Direct memory access unit                |
-+-----------+------------+------------------------------------------+
-| Flash     | on-chip    | Can be used with LittleFS to store files |
-+-----------+------------+------------------------------------------+
-| GPIO      | on-chip    | I/O ports                                |
-+-----------+------------+------------------------------------------+
-| HWINFO    | on-chip    | Hardware info and serial number          |
-+-----------+------------+------------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller       |
-+-----------+------------+------------------------------------------+
-| PWM       | on-chip    | Pulse Width Modulation                   |
-+-----------+------------+------------------------------------------+
-| SPI       | on-chip    | Serial Peripheral Interface ports        |
-+-----------+------------+------------------------------------------+
-| I2C       | on-chip    | Inter-Integrated Circuit ports           |
-+-----------+------------+------------------------------------------+
-| SYSTICK   | on-chip    | systick                                  |
-+-----------+------------+------------------------------------------+
-| USART     | on-chip    | Serial ports                             |
-+-----------+------------+------------------------------------------+
-| USB       | on-chip    | USB device                               |
-+-----------+------------+------------------------------------------+
-| WDT       | on-chip    | Watchdog                                 |
-+-----------+------------+------------------------------------------+
-
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig
-:zephyr_file:`boards/arduino/mkrzero/arduino_mkrzero_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -124,6 +78,8 @@ Arduino MKR Zero, the DAC is available on pin A0.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The Arduino MKR Zero ships the BOSSA compatible bootloader.  The
 bootloader can be entered by quickly tapping the reset button twice.
 
diff --git a/boards/arduino/nano_33_ble/arduino_nano_33_ble.yaml b/boards/arduino/nano_33_ble/arduino_nano_33_ble.yaml
index 385d3bd1559..70e0d6999a9 100644
--- a/boards/arduino/nano_33_ble/arduino_nano_33_ble.yaml
+++ b/boards/arduino/nano_33_ble/arduino_nano_33_ble.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - ble
diff --git a/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.yaml b/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.yaml
index 6a80eaecf48..56f57856eef 100644
--- a/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.yaml
+++ b/boards/arduino/nano_33_ble/arduino_nano_33_ble_nrf52840_sense.yaml
@@ -1,11 +1,10 @@
-identifier: arduino_nano_33_ble//sense
+identifier: arduino_nano_33_ble/nrf52840/sense
 name: Arduino Nano 33 BLE Sense
 type: mcu
 arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - ble
diff --git a/boards/arduino/nano_33_ble/arduino_nano_r3_connector.dtsi b/boards/arduino/nano_33_ble/arduino_nano_r3_connector.dtsi
index 21a98b50407..af20cc6c755 100644
--- a/boards/arduino/nano_33_ble/arduino_nano_r3_connector.dtsi
+++ b/boards/arduino/nano_33_ble/arduino_nano_r3_connector.dtsi
@@ -16,8 +16,8 @@
 			   <4 0 &gpio1 15 0>,  /* D4 */
 			   <5 0 &gpio1 13 0>,  /* D5 */
 			   <6 0 &gpio1 14 0>,  /* D6 */
-			   <7 0 &gpio0 9 0>,   /* D7 */
-			   <8 0 &gpio0 10 0>,  /* D8 */
+			   <7 0 &gpio0 23 0>,  /* D7 */
+			   <8 0 &gpio0 21 0>,  /* D8 */
 			   <9 0 &gpio0 27 0>,  /* D9 */
 			   <10 0 &gpio1 2 0>,  /* D10 */
 			   <11 0 &gpio1 1 0>,  /* D11 / SPI-MOSI */
@@ -27,10 +27,10 @@
 			   <15 0 &gpio0 5 0>,  /* D15 / A1 */
 			   <16 0 &gpio0 30 0>, /* D16 / A2 */
 			   <17 0 &gpio0 29 0>, /* D17 / A3 */
-			   <18 0 &gpio0 14 0>, /* D18 / A4 / I2C-SDA */
-			   <19 0 &gpio0 15 0>, /* D19 / A5 / I2C-SCL */
+			   <18 0 &gpio0 31 0>, /* D18 / A4 / I2C-SDA */
+			   <19 0 &gpio0 2 0>,  /* D19 / A5 / I2C-SCL */
 			   <20 0 &gpio0 28 0>, /* D20 / A6 */
-			   <21 0 &gpio1 3 0>;  /* D21 / A7 */
+			   <21 0 &gpio0 3 0>;  /* D21 / A7 */
 	};
 };
 
diff --git a/boards/arduino/nano_33_ble/board.c b/boards/arduino/nano_33_ble/board.c
index 10fd95e74cc..5f6b14645f1 100644
--- a/boards/arduino/nano_33_ble/board.c
+++ b/boards/arduino/nano_33_ble/board.c
@@ -29,7 +29,7 @@ static int board_init(void)
 		return res;
 	}
 
-	return gpio_pin_configure_dt(&user_led, GPIO_OUTPUT_INACTIVE);
+	return gpio_pin_configure_dt(&user_led, GPIO_OUTPUT_HIGH);
 }
 
 SYS_INIT(board_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
diff --git a/boards/arduino/nano_33_ble/doc/index.rst b/boards/arduino/nano_33_ble/doc/index.rst
index 2b5ede0ea11..753209f349d 100644
--- a/boards/arduino/nano_33_ble/doc/index.rst
+++ b/boards/arduino/nano_33_ble/doc/index.rst
@@ -1,7 +1,4 @@
-.. _arduino_nano_33_ble:
-
-Arduino Nano 33 BLE (Sense)
-#################################
+.. zephyr:board:: arduino_nano_33_ble
 
 Overview
 ********
@@ -11,58 +8,13 @@ nRF52840 ARM Cortex-M4F CPU. Arduino sells 2 variants of the board, the
 plain `BLE`_ type and the `BLE Sense`_ type. The "Sense" variant is distinguished by
 the inclusion of more sensors, but otherwise both variants are the same.
 
-.. image:: img/arduino_nano_33_ble_sense.jpg
-     :align: center
-     :alt: Arduino Nano 33 BLE (Sense variant)
-
-The Sense variant of the board
-
 Hardware
 ********
 
 Supported Features
 ==================
 
-The package is configured to support the following hardware:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C0      | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| I2C1      | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
-
-Notably, this includes the PDM (microphone) interface.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -77,6 +29,8 @@ as ``pull-up-gpios``.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 This board requires the Arduino variant of bossac. You will not
 be able to flash with the bossac included with the zephyr-sdk, or
 using shumatech's mainline build.
diff --git a/boards/arduino/nano_33_iot/arduino_nano_33_iot-pinctrl.dtsi b/boards/arduino/nano_33_iot/arduino_nano_33_iot-pinctrl.dtsi
index 73ac01e1296..438eaaf80b9 100644
--- a/boards/arduino/nano_33_iot/arduino_nano_33_iot-pinctrl.dtsi
+++ b/boards/arduino/nano_33_iot/arduino_nano_33_iot-pinctrl.dtsi
@@ -6,6 +6,18 @@
 #include <dt-bindings/pinctrl/samd21-da1gXabcd-pinctrl.h>
 
 &pinctrl {
+	adc_default: adc_default {
+		group1 {
+			pinmux = <PA2B_ADC_AIN0>,
+				 <PB2B_ADC_AIN10>,
+				 <PA11B_ADC_AIN19>,
+				 <PA10B_ADC_AIN18>,
+				 <PB8B_ADC_AIN2>,
+				 <PB9B_ADC_AIN3>,
+				 <PA9B_ADC_AIN17>;
+		};
+	};
+
 	pwm_default: pwm_default {
 		group1 {
 			pinmux = <PA17E_TCC2_WO1>;
diff --git a/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts b/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts
index f5fc56c015f..7a8e3b7e745 100644
--- a/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts
+++ b/boards/arduino/nano_33_iot/arduino_nano_33_iot.dts
@@ -48,6 +48,13 @@
 	clock-frequency = <48000000>;
 };
 
+&adc {
+	status = "okay";
+
+	pinctrl-0 = <&adc_default>;
+	pinctrl-names = "default";
+};
+
 &sercom1 {
 	status = "okay";
 	compatible = "atmel,sam0-spi";
diff --git a/boards/arduino/nano_33_iot/arduino_nano_33_iot.yaml b/boards/arduino/nano_33_iot/arduino_nano_33_iot.yaml
index f7ded1f5239..b75847ab383 100644
--- a/boards/arduino/nano_33_iot/arduino_nano_33_iot.yaml
+++ b/boards/arduino/nano_33_iot/arduino_nano_33_iot.yaml
@@ -7,7 +7,6 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - counter
diff --git a/boards/arduino/nano_33_iot/doc/index.rst b/boards/arduino/nano_33_iot/doc/index.rst
index 419c02a5cea..14c76bc9e25 100644
--- a/boards/arduino/nano_33_iot/doc/index.rst
+++ b/boards/arduino/nano_33_iot/doc/index.rst
@@ -1,7 +1,4 @@
-.. _arduino_nano_33_iot:
-
-Arduino Nano 33 IOT
-###################
+.. zephyr:board:: arduino_nano_33_iot
 
 Overview
 ********
@@ -9,10 +6,6 @@ Overview
 The Arduino Nano 33 IOT is a small form factor development board with USB,
 Wifi, Bluetooth, a 6 axis IMU, and secure element.
 
-.. image:: img/nano_33_iot.jpg
-     :align: center
-     :alt: Arduino Nano 33 IOT
-
 Hardware
 ********
 
@@ -28,43 +21,7 @@ Hardware
 Supported Features
 ==================
 
-The arduino_nano_33_iot board configuration supports the following hardware
-features:
-
-+-----------+------------+------------------------------------------+
-| Interface | Controller | Driver/Component                         |
-+===========+============+==========================================+
-| ADC       | on-chip    | Analog to digital converter              |
-+-----------+------------+------------------------------------------+
-| COUNTER   | on-chip    | Pulse counter                            |
-+-----------+------------+------------------------------------------+
-| DMA       | on-chip    | Direct memory access unit                |
-+-----------+------------+------------------------------------------+
-| Flash     | on-chip    | Can be used with LittleFS to store files |
-+-----------+------------+------------------------------------------+
-| GPIO      | on-chip    | I/O ports                                |
-+-----------+------------+------------------------------------------+
-| HWINFO    | on-chip    | Hardware info and serial number          |
-+-----------+------------+------------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller       |
-+-----------+------------+------------------------------------------+
-| PWM       | on-chip    | Pulse Width Modulation                   |
-+-----------+------------+------------------------------------------+
-| SPI       | on-chip    | Serial Peripheral Interface ports        |
-+-----------+------------+------------------------------------------+
-| SYSTICK   | on-chip    | systick                                  |
-+-----------+------------+------------------------------------------+
-| USART     | on-chip    | Serial ports                             |
-+-----------+------------+------------------------------------------+
-| USB       | on-chip    | USB device                               |
-+-----------+------------+------------------------------------------+
-| WDT       | on-chip    | Watchdog                                 |
-+-----------+------------+------------------------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig
-:zephyr_file:`boards/arduino/nano_33_iot/arduino_nano_33_iot_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -109,6 +66,8 @@ serial port that echos characters back to the host PC.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The Nano 33 IOT ships the BOSSA compatible UF2 bootloader.  The
 bootloader can be entered by quickly tapping the reset button twice.
 
diff --git a/boards/arduino/nicla_sense_me/arduino_nicla_sense_me.yaml b/boards/arduino/nicla_sense_me/arduino_nicla_sense_me.yaml
index 74e8cab3c6b..a138ec5596c 100644
--- a/boards/arduino/nicla_sense_me/arduino_nicla_sense_me.yaml
+++ b/boards/arduino/nicla_sense_me/arduino_nicla_sense_me.yaml
@@ -7,7 +7,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/arduino/nicla_sense_me/doc/index.rst b/boards/arduino/nicla_sense_me/doc/index.rst
index 1bf984f23f4..826fb2f4201 100644
--- a/boards/arduino/nicla_sense_me/doc/index.rst
+++ b/boards/arduino/nicla_sense_me/doc/index.rst
@@ -1,7 +1,4 @@
-.. _arduino_nicla_sense_me:
-
-Arduino Nicla Sense ME
-######################
+.. zephyr:board:: arduino_nicla_sense_me
 
 Overview
 ********
@@ -10,12 +7,6 @@ nrf52832 ARM Cortex-M4F CPU. The board houses 4 low power industrial grade senso
 that can measure rotation, acceleration, pressure, humidity, temperature, air quality
 and CO2 levels.
 
-.. figure:: arduino_nicla_sense_me.jpg
-   :align: center
-   :alt: Arduino Nicla Sense ME
-
-   Arduino Nicla Sense ME (Credit: Arduino)
-
 Hardware
 ********
 
@@ -39,35 +30,7 @@ Hardware
 Supported Features
 ==================
 
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M/S)  | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth Low Energy |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -85,6 +48,8 @@ For more details please refer to the `datasheet`_, `full pinout`_ and the `schem
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``arduino_nicla_sense_me`` board configuration can be built and
 flashed in the usual way (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m4.yaml b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m4.yaml
index 727622952e5..8b179806eb2 100644
--- a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m4.yaml
+++ b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m4.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 288
 flash: 1024
 supported:
diff --git a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.yaml b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.yaml
index 006cd2b35b4..0310b5dce89 100644
--- a/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.yaml
+++ b/boards/arduino/nicla_vision/arduino_nicla_vision_stm32h747xx_m7.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 512
 flash: 1024
 supported:
diff --git a/boards/arduino/nicla_vision/doc/index.rst b/boards/arduino/nicla_vision/doc/index.rst
index 73b2d7cd733..f9cc62c6ee1 100644
--- a/boards/arduino/nicla_vision/doc/index.rst
+++ b/boards/arduino/nicla_vision/doc/index.rst
@@ -1,7 +1,4 @@
-.. _arduino_nicla_vision_board:
-
-Arduino Nicla Vision
-####################
+.. zephyr:board:: arduino_nicla_vision
 
 Overview
 ********
@@ -38,53 +35,7 @@ More information about STM32H747GAII6 can be found here:
 Supported Features
 ==================
 
-The current Zephyr ``arduino_nicla_vision/stm32h747xx/m7`` board configuration supports the
-following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| DCMI      | on-chip    | Parallel Camera interface           |
-+-----------+------------+-------------------------------------+
-| IPM       | on-chip    | virtual mailbox based on HSEM       |
-+-----------+------------+-------------------------------------+
-| RADIO     | Murata 1DX | WiFi and Bluetooth module           |
-+-----------+------------+-------------------------------------+
-
-And the ``arduino_nicla_vision/stm32h747xx/m4`` has the following
-support from Zephyr:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr port.
+.. zephyr:board-supported-hw::
 
 Fetch Binary Blobs
 ******************
@@ -116,6 +67,8 @@ two cores. This is done in 3 ways:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``arduino_nicla_vision`` board should be built per core target,
 using either ``arduino_nicla_vision/stm32h747xx/m7`` or ``arduino_nicla_vision/stm32h747xx/m4`` as the target.
 
diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m4.yaml b/boards/arduino/opta/arduino_opta_stm32h747xx_m4.yaml
index e7495a72ea1..c510be86b80 100644
--- a/boards/arduino/opta/arduino_opta_stm32h747xx_m4.yaml
+++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m4.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 288
 flash: 512
 supported:
diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts
index d1b63e91e52..9580656581f 100644
--- a/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts
+++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.dts
@@ -107,6 +107,8 @@ zephyr_udc0: &usbotg_fs {
 		&eth_txd0_pg13
 	>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
 	status = "okay";
 };
 
@@ -115,9 +117,8 @@ zephyr_udc0: &usbotg_fs {
 	pinctrl-names = "default";
 	status = "okay";
 
-	ethernet-phy@0 {
+	eth_phy: ethernet-phy@0 {
 		compatible = "ethernet-phy";
 		reg = <0x00>;
-		status = "okay";
 	};
 };
diff --git a/boards/arduino/opta/arduino_opta_stm32h747xx_m7.yaml b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.yaml
index 5ce1e815a74..6169f1b3364 100644
--- a/boards/arduino/opta/arduino_opta_stm32h747xx_m7.yaml
+++ b/boards/arduino/opta/arduino_opta_stm32h747xx_m7.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 512
 flash: 768
 supported:
diff --git a/boards/arduino/opta/doc/index.rst b/boards/arduino/opta/doc/index.rst
index 8c6aa788487..4b131659355 100644
--- a/boards/arduino/opta/doc/index.rst
+++ b/boards/arduino/opta/doc/index.rst
@@ -1,7 +1,4 @@
-.. _arduino_opta_m4_board:
-
-Arduino OPTA
-############
+.. zephyr:board:: arduino_opta
 
 Overview
 ********
@@ -31,10 +28,6 @@ Additionally, the device features:
 - 8 x analog inputs
 - 4 x isolated relay outputs
 
-.. image:: img/arduino_opta.jpeg
-     :align: center
-     :alt: ARDUINO-OPTA
-
 More information about the board can be found at the `ARDUINO-OPTA website`_.
 More information about STM32H747XIH6 can be found here:
 
@@ -45,55 +38,7 @@ More information about STM32H747XIH6 can be found here:
 Supported Features
 ==================
 
-The ``arduino_opta/stm32h747xx/m7`` board target
-supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| IPM       | on-chip    | virtual mailbox based on HSEM       |
-+-----------+------------+-------------------------------------+
-| USB       | on-board   | usb-fs                              |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-board   | eth                                 |
-+-----------+------------+-------------------------------------+
-| RS485     | on-board   | uart                                |
-+-----------+------------+-------------------------------------+
-
-The ``arduino_opta/stm32h747xx/m4`` board target
-supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| IPM       | on-chip    | virtual mailbox based on HSEM       |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration per core can be found in the defconfig files:
-:zephyr_file:`boards/arduino/opta/arduino_opta_stm32h747xx_m4_defconfig` and
-:zephyr_file:`boards/arduino/opta/arduino_opta_stm32h747xx_m7_defconfig`.
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -153,6 +98,8 @@ two cores. This is done in 3 ways:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``arduino_opta`` use the regular Zephyr build commands.
 See :ref:`build_an_application` for more information about application builds.
 
diff --git a/boards/arduino/opta/dts/bindings/gpio-power-switches.yaml b/boards/arduino/opta/dts/bindings/gpio-power-switches.yaml
index 580288b2382..8036df3c65e 100644
--- a/boards/arduino/opta/dts/bindings/gpio-power-switches.yaml
+++ b/boards/arduino/opta/dts/bindings/gpio-power-switches.yaml
@@ -2,9 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  This allows to define a group of relays (like in the original Opta)
-  or other kinds of power switches controlled by a GPIO. Each power
-  switch is defined in a child node of the gpio-power-switches node.
+  Group of relays (like in the original Opta) or other kinds of power switches controlled by a GPIO.
+
+  Each power switch is defined in a child node of the gpio-power-switches node.
 
 compatible: "gpio-power-switches"
 
diff --git a/boards/arduino/portenta_h7/Kconfig.defconfig b/boards/arduino/portenta_h7/Kconfig.defconfig
index b2a4abd35e7..3a59127ffa7 100644
--- a/boards/arduino/portenta_h7/Kconfig.defconfig
+++ b/boards/arduino/portenta_h7/Kconfig.defconfig
@@ -5,6 +5,9 @@ if BOARD_ARDUINO_PORTENTA_H7
 
 if NETWORKING
 
+config REGULATOR
+	default y
+
 config NET_L2_ETHERNET
 	default y
 
diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi b/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi
index 7a61e830e52..d7489b77d26 100644
--- a/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi
+++ b/boards/arduino/portenta_h7/arduino_portenta_h7-common.dtsi
@@ -209,17 +209,33 @@
 	};
 };
 
+&rng {
+	status = "okay";
+};
+
 &mac {
 	pinctrl-0 = < &eth_ref_clk_pa1
-		      &eth_mdio_pa2
 		      &eth_crs_dv_pa7
-		      &eth_mdc_pc1
 		      &eth_rxd0_pc4
 		      &eth_rxd1_pc5
 		      &eth_tx_en_pg11
 		      &eth_txd1_pg12
 		      &eth_txd0_pg13 >;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
+	status = "okay";
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
+	pinctrl-names = "default";
+
+	eth_phy: ethernet-phy@0 {
+		compatible = "ethernet-phy";
+		reg = <0x00>;
+	};
 };
 
 zephyr_udc0: &usbotg_hs {
diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.yaml b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.yaml
index 352ae2b3cce..445d14b7809 100644
--- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.yaml
+++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m4.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 288
 flash: 1024
 supported:
diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts
index 3a3745c5a7d..001d8509059 100644
--- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts
+++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.dts
@@ -86,6 +86,54 @@
 
 &i2c1 {
 	status = "okay";
+
+	pf1550: pmic@8 {
+		status = "okay";
+		reg = <0x8>;
+		compatible = "nxp,pf1550";
+
+		pmic_regulators: regulators {
+			status = "okay";
+			compatible = "nxp,pf1550-regulator";
+			pf1550_sw1: BUCK1 {
+				regulator-init-microvolt = <3000000>;
+				regulator-boot-on;
+			};
+			pf1550_sw2: BUCK2 {
+				regulator-init-microvolt = <3300000>;
+				regulator-boot-on;
+			};
+			pf1550_sw3: BUCK3 {
+				regulator-init-microvolt = <3300000>;
+				regulator-init-microamp = <2000000>;
+				regulator-boot-on;
+			};
+			pf1550_ldo1: LDO1 {
+				regulator-init-microvolt = <1000000>;
+				regulator-boot-on;
+			};
+			pf1550_ldo2: LDO2 {
+				regulator-init-microvolt = <1800000>;
+				regulator-boot-on;
+			};
+			pf1550_ldo3: LDO3 {
+				regulator-init-microvolt = <1200000>;
+				regulator-boot-on;
+			};
+		};
+
+		pmic_charger: charger {
+			status = "okay";
+			compatible = "nxp,pf1550-charger";
+			constant-charge-current-max-microamp = <100000>;
+			constant-charge-voltage-max-microvolt = <4200000>;
+			pf1550,int-gpios = <&gpiok 0 0>;
+			pf1550,led-behaviour = "manual-off";
+			pf1550,system-voltage-min-threshold-microvolt = <3500000>;
+			pf1550,thermistor-monitoring-mode = "thermistor";
+			pf1550,vbus-current-limit-microamp = <1500000>;
+		};
+	};
 };
 
 /* Only one should be enabled */
diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.yaml b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.yaml
deleted file mode 100644
index ee73966dbfe..00000000000
--- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7.yaml
+++ /dev/null
@@ -1,13 +0,0 @@
-identifier: arduino_portenta_h7/stm32h747xx/m7
-name: Arduino Portenta H7 (M7)
-type: mcu
-arch: arm
-toolchain:
-  - zephyr
-  - gnuarmemb
-  - xtools
-ram: 512
-flash: 1024
-supported:
-  - gpio
-vendor: arduino
diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_1_0_0.yaml b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_1_0_0.yaml
new file mode 100644
index 00000000000..7dc36b14190
--- /dev/null
+++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_1_0_0.yaml
@@ -0,0 +1,18 @@
+identifier: arduino_portenta_h7@1.0.0/stm32h747xx/m7
+name: Arduino Portenta H7 (M7) rev. 1.0.0
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 512
+flash: 1024
+supported:
+  - gpio
+  - netif:eth
+  - i2c
+  - spi
+  - qspi
+  - memc
+  - usb_device
+vendor: arduino
diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_4_10_0.yaml b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_4_10_0.yaml
new file mode 100644
index 00000000000..456ae5871e3
--- /dev/null
+++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_4_10_0.yaml
@@ -0,0 +1,19 @@
+identifier: arduino_portenta_h7@4.10.0/stm32h747xx/m7
+name: Arduino Portenta H7 (M7) rev. 4.10.0
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 512
+flash: 1024
+supported:
+  - gpio
+  - netif:eth
+  - i2c
+  - spi
+  - qspi
+  - memc
+  - usb_cdc
+  - usb_device
+vendor: arduino
diff --git a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig
index acc978d70c9..a67b6f27c00 100644
--- a/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig
+++ b/boards/arduino/portenta_h7/arduino_portenta_h7_stm32h747xx_m7_defconfig
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 # Enable the internal SMPS regulator
-CONFIG_POWER_SUPPLY_DIRECT_SMPS=y
+CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO=y
 
 # Enable GPIO
 CONFIG_GPIO=y
diff --git a/boards/arduino/portenta_h7/doc/index.rst b/boards/arduino/portenta_h7/doc/index.rst
index 2d1d167065e..85d3212a616 100644
--- a/boards/arduino/portenta_h7/doc/index.rst
+++ b/boards/arduino/portenta_h7/doc/index.rst
@@ -1,7 +1,4 @@
-.. _arduino_portenta_h7_board:
-
-Arduino Portenta H7
-###################
+.. zephyr:board:: arduino_portenta_h7
 
 Overview
 ********
@@ -19,12 +16,6 @@ Additionally, the board features:
 - USB OTG FS
 - 3 color user LEDs
 
-.. image:: img/arduino_portenta_h7.jpeg
-     :width: 500px
-     :align: center
-     :height: 325px
-     :alt: ARDUINO_PORTENTA_H7
-
 More information about the board can be found at the `ARDUINO_PORTENTA_H7 website`_.
 More information about STM32H747XIH6 can be found here:
 
@@ -35,40 +26,7 @@ More information about STM32H747XIH6 can be found here:
 Supported Features
 ==================
 
-The current Zephyr arduino_portenta_h7 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| IPM       | on-chip    | virtual mailbox based on HSEM       |
-+-----------+------------+-------------------------------------+
-| EXTFLASH  | on-chip    | qspi                                |
-+-----------+------------+-------------------------------------+
-| SDRAM     | on-chip    | sdram                               |
-+-----------+------------+-------------------------------------+
-| USB       | on-board   | usb-hs                              |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-board   | eth                                 |
-+-----------+------------+-------------------------------------+
-| RADIO     | Murata 1DX | WiFi and Bluetooth module           |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
+.. zephyr:board-supported-hw::
 
 The high precision low speed external (LSE) clock is only fully supported on
 boards with hardware revision 4.10 or greater. By default the internal source
@@ -108,7 +66,9 @@ two cores. This is done in 3 ways:
   to avoid potential concurrent access issues.
 
 Building and Flashing
-*************************
+*********************
+
+.. zephyr:board-supported-runners::
 
 Applications for the ``arduino_portenta_h7`` board should be built per core target,
 using either ``arduino_portenta_h7_m7`` or ``arduino_portenta_h7_m4`` as the target.
diff --git a/boards/arduino/uno_r4/Kconfig.arduino_uno_r4 b/boards/arduino/uno_r4/Kconfig.arduino_uno_r4
new file mode 100644
index 00000000000..67a9f951d67
--- /dev/null
+++ b/boards/arduino/uno_r4/Kconfig.arduino_uno_r4
@@ -0,0 +1,5 @@
+# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ARDUINO_UNO_R4
+	select SOC_R7FA4M1AB3CFM
diff --git a/boards/arduino/uno_r4/Kconfig.arduino_uno_r4_minima b/boards/arduino/uno_r4/Kconfig.arduino_uno_r4_minima
deleted file mode 100644
index 2fae481238c..00000000000
--- a/boards/arduino/uno_r4/Kconfig.arduino_uno_r4_minima
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_ARDUINO_UNO_R4_MINIMA
-	select SOC_R7FA4M1AB3CFM
diff --git a/boards/arduino/uno_r4/Kconfig.arduino_uno_r4_wifi b/boards/arduino/uno_r4/Kconfig.arduino_uno_r4_wifi
deleted file mode 100644
index 840ead804a4..00000000000
--- a/boards/arduino/uno_r4/Kconfig.arduino_uno_r4_wifi
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright (c) 2024 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_ARDUINO_UNO_R4_WIFI
-	select SOC_R7FA4M1AB3CFM
diff --git a/boards/arduino/uno_r4/arduino_uno_r4-pinctrl.dtsi b/boards/arduino/uno_r4/arduino_uno_r4-pinctrl.dtsi
new file mode 100644
index 00000000000..b54c4d8cfbb
--- /dev/null
+++ b/boards/arduino/uno_r4/arduino_uno_r4-pinctrl.dtsi
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci2_default: sci2_default {
+		group1 {
+			/* tx */
+			psels = <RA_PSEL(RA_PSEL_SCI_2, 3, 2)>;
+			drive-strength = "medium";
+		};
+		group2 {
+			/* rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_2, 3, 1)>;
+		};
+	};
+
+	iic1_default: iic1_default {
+		group1 {
+			/* SCL1 SDA1 */
+			psels = <RA_PSEL(RA_PSEL_I2C, 1, 0)>,
+				<RA_PSEL(RA_PSEL_I2C, 1, 1)>;
+			drive-strength = "medium";
+		};
+	};
+
+	adc0_default: adc0_default {
+		group1 {
+			/* input */
+			psels = <RA_PSEL(RA_PSEL_ADC, 0,  9)>,
+				<RA_PSEL(RA_PSEL_ADC, 0,  0)>,
+				<RA_PSEL(RA_PSEL_ADC, 0,  1)>,
+				<RA_PSEL(RA_PSEL_ADC, 0,  2)>;
+			renesas,analog-enable;
+		};
+	};
+
+	pwm7_default: pwm7_default {
+		group1 {
+			/* GTIOC7A GTIOC7B */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 3, 4)>,
+				<RA_PSEL(RA_PSEL_GPT1, 3, 3)>;
+		};
+	};
+};
diff --git a/boards/arduino/uno_r4/arduino_uno_r4.dts b/boards/arduino/uno_r4/arduino_uno_r4.dts
new file mode 100644
index 00000000000..09ce3664f1d
--- /dev/null
+++ b/boards/arduino/uno_r4/arduino_uno_r4.dts
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra4/r7fa4m1ab3cfm.dtsi>
+#include "arduino_uno_r4-pinctrl.dtsi"
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/adc/adc.h>
+
+/ {
+	model = "Arduino Uno R4 Board";
+	compatible = "renesas,ra4m1", "renesas,ra";
+
+	chosen {
+		zephyr,console = &uart2;
+		zephyr,shell-uart = &uart2;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,entropy = &trng;
+		zephyr,code-partition = &code_partition;
+	};
+};
+
+&sci2 {
+	status = "okay";
+	pinctrl-0 = <&sci2_default>;
+	pinctrl-names = "default";
+	interrupts = <0 1>, <1 1>, <2 1>, <3 1>;
+	interrupt-names = "rxi", "txi", "tei", "eri";
+
+	uart2: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
+
+&ioport1 {
+	status = "okay";
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_default>;
+	pinctrl-names = "default";
+};
+
+&port_irq0 {
+	interrupts = <27 12>;
+	status = "okay";
+};
+
+&port_irq1 {
+	interrupts = <28 12>;
+	status = "okay";
+};
+
+&trng {
+	status = "okay";
+};
+
+&pwm7 {
+	pinctrl-0 = <&pwm7_default>;
+	pinctrl-names = "default";
+	interrupts = <8 1>, <9 1>;
+	interrupt-names = "gtioca", "overflow";
+	status = "okay";
+};
+
+&iic1 {
+	pinctrl-0 = <&iic1_default>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <DT_FREQ_M(1)>;
+	interrupts = <10 1>, <11 1>, <12 1>, <13 1>;
+	interrupt-names = "rxi", "txi", "tei", "eri";
+	status = "okay";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "bootloader";
+			reg = <0x00000000 0x4000>;
+			read-only;
+		};
+
+		code_partition: partition@4000 {
+			label = "code";
+			reg = <0x4000 0x3C000>;
+			read-only;
+		};
+	};
+};
+
+&hoco {
+	status = "okay";
+	clock-frequency = <48000000>;
+};
+
+&pclkblock {
+	clocks = <&hoco>;
+};
+
+&iclk {
+	div = <1>;
+};
+
+&pclka {
+	div = <1>;
+};
+
+&pclkb {
+	div = <2>;
+};
+
+&pclkc {
+	div = <1>;
+};
+
+&pclkd {
+	div = <1>;
+};
+
+&fclk {
+	div = <2>;
+};
diff --git a/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi b/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi
deleted file mode 100644
index f9fff37eaab..00000000000
--- a/boards/arduino/uno_r4/arduino_uno_r4_common.dtsi
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/dts-v1/;
-#include <renesas/ra/r7fa4m1ab3cfm.dtsi>
-#include <zephyr/dt-bindings/gpio/gpio.h>
-
-/ {
-	model = "Arduino Uno R4 Board";
-	compatible = "renesas,r7fa4m1ab3cfm";
-
-	chosen {
-		zephyr,console = &uart2;
-		zephyr,shell-uart = &uart2;
-		zephyr,sram = &sram0;
-		zephyr,flash = &flash0;
-		zephyr,code-partition = &code_partition;
-	};
-};
-
-&sci2 {
-	status = "okay";
-	pinctrl-0 = <&sci2_default>;
-	pinctrl-names = "default";
-	uart2: uart {
-		current-speed = <115200>;
-		status = "okay";
-	};
-};
-
-&ioport1 {
-	status = "okay";
-};
-
-&flash0 {
-	partitions {
-		compatible = "fixed-partitions";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		boot_partition: partition@0 {
-			label = "bootloader";
-			reg = <0x00000000 0x4000>;
-			read-only;
-		};
-
-		code_partition: partition@4000 {
-			label = "code";
-			reg = <0x4000 0x3C000>;
-			read-only;
-		};
-	};
-};
-
-&fcu {
-	status = "okay";
-};
-
-&hoco {
-	status = "okay";
-	clock-frequency = <48000000>;
-};
-
-&pclkblock {
-	clocks = <&hoco>;
-};
-
-&iclk {
-	div = <1>;
-};
-
-&pclka {
-	div = <1>;
-};
-
-&pclkb {
-	div = <2>;
-};
-
-&pclkc {
-	div = <1>;
-};
-
-&pclkd {
-	div = <1>;
-};
-
-&fclk {
-	div = <2>;
-};
diff --git a/boards/arduino/uno_r4/arduino_uno_r4_defconfig b/boards/arduino/uno_r4/arduino_uno_r4_defconfig
new file mode 100644
index 00000000000..17e55274274
--- /dev/null
+++ b/boards/arduino/uno_r4/arduino_uno_r4_defconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+CONFIG_USE_DT_CODE_PARTITION=y
diff --git a/boards/arduino/uno_r4/arduino_uno_r4_minima-pinctrl.dtsi b/boards/arduino/uno_r4/arduino_uno_r4_minima-pinctrl.dtsi
index 863d9e6030a..63940405a7d 100644
--- a/boards/arduino/uno_r4/arduino_uno_r4_minima-pinctrl.dtsi
+++ b/boards/arduino/uno_r4/arduino_uno_r4_minima-pinctrl.dtsi
@@ -4,18 +4,14 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
-
 &pinctrl {
-	sci2_default: sci2_default {
+	spi1_default: spi1_default {
 		group1 {
-			/* tx */
-			psels = <RA_PSEL(RA_PSEL_SCI_2, 3, 2)>;
-			drive-strength = "medium";
-		};
-		group2 {
-			/* rx */
-			psels = <RA_PSEL(RA_PSEL_SCI_2, 3, 1)>;
+			/* MOSI MISO RSPCK SSL */
+			psels = <RA_PSEL(RA_PSEL_SPI, 1,  9)>,
+				<RA_PSEL(RA_PSEL_SPI, 1, 10)>,
+				<RA_PSEL(RA_PSEL_SPI, 1, 11)>,
+				<RA_PSEL(RA_PSEL_SPI, 1, 12)>;
 		};
 	};
 };
diff --git a/boards/arduino/uno_r4/arduino_uno_r4_minima.dts b/boards/arduino/uno_r4/arduino_uno_r4_minima.dts
deleted file mode 100644
index d80ca6d4f1f..00000000000
--- a/boards/arduino/uno_r4/arduino_uno_r4_minima.dts
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/dts-v1/;
-#include "arduino_uno_r4_common.dtsi"
-#include "arduino_uno_r4_minima-pinctrl.dtsi"
-
-/ {
-	model = "Arduino Uno R4 Minima";
-
-	leds {
-		compatible = "gpio-leds";
-		led: led {
-			gpios = <&ioport1 11 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	aliases {
-		led0 = &led;
-	};
-
-	arduino_header: connector {
-		compatible = "arduino-header-r3";
-		#gpio-cells = <2>;
-		gpio-map-mask = <0xffffffff 0xffffffc0>;
-		gpio-map-pass-thru = <0 0x3f>;
-		gpio-map = <0 0 &ioport0 14 0>,   /* A0 */
-			   <1 0 &ioport0 0 0>,    /* A1 */
-			   <2 0 &ioport0 1 0>,    /* A2 */
-			   <3 0 &ioport0 2 0>,    /* A3 */
-			   <4 0 &ioport1 1 0>,    /* A4 */
-			   <5 0 &ioport1 0 0>,    /* A5 */
-			   <6 0 &ioport3 1 0>,    /* D0 */
-			   <7 0 &ioport3 2 0>,    /* D1 */
-			   <8 0 &ioport1 5 0>,    /* D2 */
-			   <9 0 &ioport1 4 0>,    /* D3 */
-			   <10 0 &ioport1 3 0>,   /* D4 */
-			   <11 0 &ioport1 2 0>,   /* D5 */
-			   <12 0 &ioport1 6 0>,   /* D6 */
-			   <13 0 &ioport1 7 0>,   /* D7 */
-			   <14 0 &ioport3 4 0>,   /* D8 */
-			   <15 0 &ioport3 3 0>,   /* D9 */
-			   <16 0 &ioport1 12 0>,  /* D10 */
-			   <17 0 &ioport1 9 0>,   /* D11 */
-			   <18 0 &ioport1 10 0>,  /* D12 */
-			   <19 0 &ioport1 11 0>,  /* D13 */
-			   <20 0 &ioport1 1 0>,   /* D14 */
-			   <21 0 &ioport1 0 0>;   /* D15 */
-	};
-};
diff --git a/boards/arduino/uno_r4/arduino_uno_r4_minima.overlay b/boards/arduino/uno_r4/arduino_uno_r4_minima.overlay
new file mode 100644
index 00000000000..504b1597372
--- /dev/null
+++ b/boards/arduino/uno_r4/arduino_uno_r4_minima.overlay
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "arduino_uno_r4_minima-pinctrl.dtsi"
+
+#include <zephyr/dt-bindings/gpio/arduino-header-r3.h>
+#include <zephyr/dt-bindings/pwm/pwm.h>
+#include <zephyr/dt-bindings/pwm/ra_pwm.h>
+
+/ {
+	model = "Arduino Uno R4 Minima";
+
+	leds {
+		compatible = "gpio-leds";
+		led: led {
+			gpios = <&arduino_header ARDUINO_HEADER_R3_D13 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	pwm_leds {
+		compatible = "pwm-leds";
+		status = "disabled";
+		pwm_led: pwm_led {
+			pwms = <&arduino_pwm ARDUINO_HEADER_R3_D13 PWM_MSEC(1) PWM_POLARITY_NORMAL>;
+			label = "PWM_LED";
+		};
+	};
+
+	aliases {
+		led0 = &led;
+		pwm-led0 = &pwm_led;
+	};
+
+	arduino_header: connector {
+		compatible = "arduino-header-r3";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <ARDUINO_HEADER_R3_A0 0 &ioport0 14 0>,
+			   <ARDUINO_HEADER_R3_A1 0 &ioport0 0 0>,
+			   <ARDUINO_HEADER_R3_A2 0 &ioport0 1 0>,
+			   <ARDUINO_HEADER_R3_A3 0 &ioport0 2 0>,
+			   <ARDUINO_HEADER_R3_A4 0 &ioport1 1 0>,
+			   <ARDUINO_HEADER_R3_A5 0 &ioport1 0 0>,
+			   <ARDUINO_HEADER_R3_D0 0 &ioport3 1 0>,
+			   <ARDUINO_HEADER_R3_D1 0 &ioport3 2 0>,
+			   <ARDUINO_HEADER_R3_D2 0 &ioport1 5 0>,
+			   <ARDUINO_HEADER_R3_D3 0 &ioport1 4 0>,
+			   <ARDUINO_HEADER_R3_D4 0 &ioport1 3 0>,
+			   <ARDUINO_HEADER_R3_D5 0 &ioport1 2 0>,
+			   <ARDUINO_HEADER_R3_D6 0 &ioport1 6 0>,
+			   <ARDUINO_HEADER_R3_D7 0 &ioport1 7 0>,
+			   <ARDUINO_HEADER_R3_D8 0 &ioport3 4 0>,
+			   <ARDUINO_HEADER_R3_D9 0 &ioport3 3 0>,
+			   <ARDUINO_HEADER_R3_D10 0 &ioport1 12 0>,
+			   <ARDUINO_HEADER_R3_D11 0 &ioport1 9 0>,
+			   <ARDUINO_HEADER_R3_D12 0 &ioport1 10 0>,
+			   <ARDUINO_HEADER_R3_D13 0 &ioport1 11 0>,
+			   <ARDUINO_HEADER_R3_D14 0 &ioport1 1 0>,
+			   <ARDUINO_HEADER_R3_D15 0 &ioport1 0 0>;
+	};
+
+	arduino_adc: analog-connector {
+		compatible = "arduino,uno-adc";
+		#io-channel-cells = <1>;
+		io-channel-map = <ARDUINO_HEADER_R3_A0 &adc0 9>,        /* P009 = CH09 */
+				 <ARDUINO_HEADER_R3_A1 &adc0 0>,        /* P000 = CH00 */
+				 <ARDUINO_HEADER_R3_A2 &adc0 1>,        /* P001 = CH01 */
+				 <ARDUINO_HEADER_R3_A3 &adc0 2>,        /* P002 = CH02 */
+				 <ARDUINO_HEADER_R3_A4 &adc0 21>,       /* P101 = CH21 */
+				 <ARDUINO_HEADER_R3_A5 &adc0 22>;       /* P100 = CH22 */
+	};
+
+	arduino_pwm: connector-pwm {
+		compatible = "arduino-header-pwm";
+		#pwm-cells = <3>;
+		pwm-map = <ARDUINO_HEADER_R3_D2 0 0 &pwm1 0 0 0>,       /* P105 = GPT1_A */
+			  <ARDUINO_HEADER_R3_D3 0 0 &pwm1 1 0 0>,       /* P104 = GPT1_B */
+			  <ARDUINO_HEADER_R3_D4 0 0 &pwm2 0 0 0>,       /* P103 = GPT2 A */
+			  <ARDUINO_HEADER_R3_D5 0 0 &pwm2 1 0 0>,       /* P102 = GPT2_B */
+			  <ARDUINO_HEADER_R3_D6 0 0 &pwm0 1 0 0>,       /* P106 = GPT0_B */
+			  <ARDUINO_HEADER_R3_D7 0 0 &pwm0 0 0 0>,       /* P107 = GPT0_A */
+			  <ARDUINO_HEADER_R3_D8 0 0 &pwm7 0 0 0>,       /* P304 = GPT7_A */
+			  <ARDUINO_HEADER_R3_D9 0 0 &pwm7 1 0 0>,       /* P303 = GPT7_B */
+			  <ARDUINO_HEADER_R3_D10 0 0 &pwm3 1 0 0>,      /* P112 = GPT3_B */
+			  <ARDUINO_HEADER_R3_D13 0 0 &pwm3 0 0 0>;      /* P111 = GPT3_A */
+		pwm-map-mask = <0xffffffff 0x0 0x0>;
+		pwm-map-pass-thru = <0x0 0xffffffff 0xffffffff>;
+	};
+};
+
+&spi1 {
+	pinctrl-0 = <&spi1_default>;
+	pinctrl-names = "default";
+	interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
+	interrupt-names = "rxi", "txi", "tei", "eri";
+	status = "okay";
+};
+
+arduino_i2c: &iic1 {};
+arduino_spi: &spi1 {};
diff --git a/boards/arduino/uno_r4/arduino_uno_r4_minima.yaml b/boards/arduino/uno_r4/arduino_uno_r4_minima.yaml
index 81f3a94866a..7e60cd09528 100644
--- a/boards/arduino/uno_r4/arduino_uno_r4_minima.yaml
+++ b/boards/arduino/uno_r4/arduino_uno_r4_minima.yaml
@@ -1,12 +1,14 @@
-identifier: arduino_uno_r4_minima
+identifier: arduino_uno_r4@minima
 name: Arduino Uno R4 Minima
 type: mcu
 arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
 supported:
+  - adc
   - gpio
+  - pwm
+  - spi
   - uart
diff --git a/boards/arduino/uno_r4/arduino_uno_r4_minima_defconfig b/boards/arduino/uno_r4/arduino_uno_r4_minima_defconfig
deleted file mode 100644
index 3c655ea376e..00000000000
--- a/boards/arduino/uno_r4/arduino_uno_r4_minima_defconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
-
-CONFIG_BUILD_OUTPUT_HEX=y
-
-# Enable UART driver
-CONFIG_SERIAL=y
-CONFIG_UART_INTERRUPT_DRIVEN=y
-
-# Enable console
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-
-# Enable GPIO
-CONFIG_GPIO=y
-
-CONFIG_CLOCK_CONTROL=y
-
-CONFIG_USE_DT_CODE_PARTITION=y
diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi b/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi
index 9add47e4723..47f94cc3a0e 100644
--- a/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi
+++ b/boards/arduino/uno_r4/arduino_uno_r4_wifi-pinctrl.dtsi
@@ -4,18 +4,23 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
-
 &pinctrl {
-	sci2_default: sci2_default {
+	iic0_default: iic0_default {
 		group1 {
-			/* tx */
-			psels = <RA_PSEL(RA_PSEL_SCI_2, 3, 2)>;
+			/* SCL0 SDA0 */
+			psels = <RA_PSEL(RA_PSEL_I2C, 4, 0)>,
+				<RA_PSEL(RA_PSEL_I2C, 4, 1)>;
 			drive-strength = "medium";
 		};
-		group2 {
-			/* rx */
-			psels = <RA_PSEL(RA_PSEL_SCI_2, 3, 1)>;
+	};
+
+	spi0_default: spi0_default {
+		group1 {
+			/* MOSI MISO RSPCK SSL */
+			psels = <RA_PSEL(RA_PSEL_SPI, 4, 11)>,
+				<RA_PSEL(RA_PSEL_SPI, 4, 10)>,
+				<RA_PSEL(RA_PSEL_SPI, 1,  2)>,
+				<RA_PSEL(RA_PSEL_SPI, 1,  3)>;
 		};
 	};
 };
diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi.dts b/boards/arduino/uno_r4/arduino_uno_r4_wifi.dts
deleted file mode 100644
index a3a2019990e..00000000000
--- a/boards/arduino/uno_r4/arduino_uno_r4_wifi.dts
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * Copyright (c) 2024 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/dts-v1/;
-#include "arduino_uno_r4_common.dtsi"
-#include "arduino_uno_r4_wifi-pinctrl.dtsi"
-
-/ {
-	model = "Arduino Uno R4 WiFi";
-
-	leds {
-		compatible = "gpio-leds";
-		led: led {
-			gpios = <&ioport1 2 GPIO_ACTIVE_HIGH>;
-		};
-	};
-
-	aliases {
-		led0 = &led;
-	};
-
-	arduino_header: connector {
-		compatible = "arduino-header-r3";
-		#gpio-cells = <2>;
-		gpio-map-mask = <0xffffffff 0xffffffc0>;
-		gpio-map-pass-thru = <0 0x3f>;
-		gpio-map = <0 0 &ioport0 14 0>,   /* A0 */
-			   <1 0 &ioport0 0 0>,    /* A1 */
-			   <2 0 &ioport0 1 0>,    /* A2 */
-			   <3 0 &ioport0 2 0>,    /* A3 */
-			   <4 0 &ioport1 1 0>,    /* A4 */
-			   <5 0 &ioport1 0 0>,    /* A5 */
-			   <6 0 &ioport3 1 0>,    /* D0 */
-			   <7 0 &ioport3 2 0>,    /* D1 */
-			   <8 0 &ioport1 4 0>,    /* D2 */
-			   <9 0 &ioport1 5 0>,    /* D3 */
-			   <10 0 &ioport1 6 0>,   /* D4 */
-			   <11 0 &ioport1 7 0>,   /* D5 */
-			   <12 0 &ioport1 11 0>,  /* D6 */
-			   <13 0 &ioport1 12 0>,  /* D7 */
-			   <14 0 &ioport3 4 0>,   /* D8 */
-			   <15 0 &ioport3 3 0>,   /* D9 */
-			   <16 0 &ioport1 3 0>,   /* D10 */
-			   <17 0 &ioport4 11 0>,  /* D11 */
-			   <18 0 &ioport4 10 0>,  /* D12 */
-			   <19 0 &ioport1 2 0>,   /* D13 */
-			   <20 0 &ioport1 1 0>,   /* D14 */
-			   <21 0 &ioport1 0 0>;   /* D15 */
-	};
-};
diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi.overlay b/boards/arduino/uno_r4/arduino_uno_r4_wifi.overlay
new file mode 100644
index 00000000000..f411487d080
--- /dev/null
+++ b/boards/arduino/uno_r4/arduino_uno_r4_wifi.overlay
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2024 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "arduino_uno_r4_wifi-pinctrl.dtsi"
+
+#include <zephyr/dt-bindings/gpio/arduino-header-r3.h>
+#include <zephyr/dt-bindings/pwm/pwm.h>
+#include <zephyr/dt-bindings/pwm/ra_pwm.h>
+
+/ {
+	model = "Arduino Uno R4 WiFi";
+
+	leds {
+		compatible = "gpio-leds";
+		led: led {
+			gpios = <&arduino_header ARDUINO_HEADER_R3_D13 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	pwm_leds {
+		compatible = "pwm-leds";
+		status = "disabled";
+		pwm_led: pwm_led {
+			pwms = <&arduino_pwm ARDUINO_HEADER_R3_D13 PWM_MSEC(1) PWM_POLARITY_NORMAL>;
+			label = "PWM_LED";
+		};
+	};
+
+	aliases {
+		led0 = &led;
+		pwm-led0 = &pwm_led;
+	};
+
+	arduino_header: connector {
+		compatible = "arduino-header-r3";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <ARDUINO_HEADER_R3_A0 0 &ioport0 14 0>,
+			   <ARDUINO_HEADER_R3_A1 0 &ioport0 0 0>,
+			   <ARDUINO_HEADER_R3_A2 0 &ioport0 1 0>,
+			   <ARDUINO_HEADER_R3_A3 0 &ioport0 2 0>,
+			   <ARDUINO_HEADER_R3_A4 0 &ioport1 1 0>,
+			   <ARDUINO_HEADER_R3_A5 0 &ioport1 0 0>,
+			   <ARDUINO_HEADER_R3_D0 0 &ioport3 1 0>,
+			   <ARDUINO_HEADER_R3_D1 0 &ioport3 2 0>,
+			   <ARDUINO_HEADER_R3_D2 0 &ioport1 4 0>,
+			   <ARDUINO_HEADER_R3_D3 0 &ioport1 5 0>,
+			   <ARDUINO_HEADER_R3_D4 0 &ioport1 6 0>,
+			   <ARDUINO_HEADER_R3_D5 0 &ioport1 7 0>,
+			   <ARDUINO_HEADER_R3_D6 0 &ioport1 11 0>,
+			   <ARDUINO_HEADER_R3_D7 0 &ioport1 12 0>,
+			   <ARDUINO_HEADER_R3_D8 0 &ioport3 4 0>,
+			   <ARDUINO_HEADER_R3_D9 0 &ioport3 3 0>,
+			   <ARDUINO_HEADER_R3_D10 0 &ioport1 3 0>,
+			   <ARDUINO_HEADER_R3_D11 0 &ioport4 11 0>,
+			   <ARDUINO_HEADER_R3_D12 0 &ioport4 10 0>,
+			   <ARDUINO_HEADER_R3_D13 0 &ioport1 2 0>,
+			   <ARDUINO_HEADER_R3_D14 0 &ioport1 1 0>,
+			   <ARDUINO_HEADER_R3_D15 0 &ioport1 0 0>;
+	};
+
+	arduino_adc: analog-connector {
+		compatible = "arduino,uno-adc";
+		#io-channel-cells = <1>;
+		io-channel-map = <ARDUINO_HEADER_R3_A0 &adc0 9>,        /* P009 = CH09 */
+				 <ARDUINO_HEADER_R3_A1 &adc0 0>,        /* P000 = CH00 */
+				 <ARDUINO_HEADER_R3_A2 &adc0 1>,        /* P001 = CH01 */
+				 <ARDUINO_HEADER_R3_A3 &adc0 2>,        /* P002 = CH02 */
+				 <ARDUINO_HEADER_R3_A4 &adc0 21>,       /* P101 = CH21 */
+				 <ARDUINO_HEADER_R3_A5 &adc0 22>;       /* P100 = CH22 */
+	};
+
+	arduino_pwm: connector-pwm {
+		compatible = "arduino-header-pwm";
+		#pwm-cells = <3>;
+		pwm-map = <ARDUINO_HEADER_R3_D2 0 0 &pwm1 1 0 0>,       /* P104 = GPT1_B */
+			  <ARDUINO_HEADER_R3_D3 0 0 &pwm1 0 0 0>,       /* P105 = GPT1_A */
+			  <ARDUINO_HEADER_R3_D4 0 0 &pwm0 1 0 0>,       /* P106 = GPT0 B */
+			  <ARDUINO_HEADER_R3_D5 0 0 &pwm0 0 0 0>,       /* P107 = GPT0_A */
+			  <ARDUINO_HEADER_R3_D6 0 0 &pwm3 0 0 0>,       /* P111 = GPT3_A */
+			  <ARDUINO_HEADER_R3_D7 0 0 &pwm3 1 0 0>,       /* P112 = GPT3_B */
+			  <ARDUINO_HEADER_R3_D8 0 0 &pwm7 0 0 0>,       /* P304 = GPT7_A */
+			  <ARDUINO_HEADER_R3_D9 0 0 &pwm7 1 0 0>,       /* P303 = GPT7_B */
+			  <ARDUINO_HEADER_R3_D10 0 0 &pwm2 0 0 0>,      /* P103 = GPT2_A */
+			  <ARDUINO_HEADER_R3_D11 0 0 &pwm6 0 0 0>,      /* P411 = GPT6_A */
+			  <ARDUINO_HEADER_R3_D12 0 0 &pwm6 1 0 0>,      /* P410 = GPT6_B */
+			  <ARDUINO_HEADER_R3_D13 0 0 &pwm2 1 0 0>;      /* P102 = GPT2_B */
+		pwm-map-mask = <0xffffffff 0x0 0x0>;
+		pwm-map-pass-thru = <0x0 0xffffffff 0xffffffff>;
+	};
+};
+
+&spi0 {
+	pinctrl-0 = <&spi0_default>;
+	pinctrl-names = "default";
+	interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
+	interrupt-names = "rxi", "txi", "tei", "eri";
+	status = "okay";
+};
+
+&iic0 {
+	pinctrl-0 = <&iic0_default>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <DT_FREQ_M(1)>;
+	interrupts = <14 1>, <15 1>, <16 1>, <17 1>;
+	interrupt-names = "rxi", "txi", "tei", "eri";
+	status = "okay";
+};
+
+qwiic_i2c: &iic0 {};
+arduino_i2c: &iic1 {};
+arduino_spi: &spi0 {};
diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi.yaml b/boards/arduino/uno_r4/arduino_uno_r4_wifi.yaml
index bfe5bc8cdcd..e2e101e93ab 100644
--- a/boards/arduino/uno_r4/arduino_uno_r4_wifi.yaml
+++ b/boards/arduino/uno_r4/arduino_uno_r4_wifi.yaml
@@ -1,12 +1,14 @@
-identifier: arduino_uno_r4_wifi
+identifier: arduino_uno_r4@wifi
 name: Arduino Uno R4 WiFi
 type: mcu
 arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
 supported:
+  - adc
   - gpio
+  - pwm
+  - spi
   - uart
diff --git a/boards/arduino/uno_r4/arduino_uno_r4_wifi_defconfig b/boards/arduino/uno_r4/arduino_uno_r4_wifi_defconfig
deleted file mode 100644
index 48137e86d7a..00000000000
--- a/boards/arduino/uno_r4/arduino_uno_r4_wifi_defconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-# Copyright (c) 2024 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
-
-CONFIG_BUILD_OUTPUT_HEX=y
-
-# Enable UART driver
-CONFIG_SERIAL=y
-CONFIG_UART_INTERRUPT_DRIVEN=y
-
-# Enable console
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-
-# Enable GPIO
-CONFIG_GPIO=y
-
-CONFIG_CLOCK_CONTROL=y
-
-CONFIG_USE_DT_CODE_PARTITION=y
diff --git a/boards/arduino/uno_r4/board.yml b/boards/arduino/uno_r4/board.yml
index 9c168c300c2..ee0f51c47d4 100644
--- a/boards/arduino/uno_r4/board.yml
+++ b/boards/arduino/uno_r4/board.yml
@@ -1,11 +1,12 @@
-boards:
-  - name: arduino_uno_r4_minima
-    full_name: Arduino UNO R4 Minima
-    vendor: arduino
-    socs:
-      - name: r7fa4m1ab3cfm
-  - name: arduino_uno_r4_wifi
-    full_name: Arduino UNO R4 WiFi
-    vendor: arduino
-    socs:
-      - name: r7fa4m1ab3cfm
+board:
+  name: arduino_uno_r4
+  full_name: Arduino UNO R4 Minima/WiFi
+  vendor: arduino
+  revision:
+    format: custom
+    default: "minima"
+    revisions:
+      - name: "minima"
+      - name: "wifi"
+  socs:
+    - name: r7fa4m1ab3cfm
diff --git a/boards/arduino/uno_r4/doc/img/arduino_uno_r4_minima.webp b/boards/arduino/uno_r4/doc/img/arduino_uno_r4_minima.webp
new file mode 100644
index 00000000000..c42a9e389e4
Binary files /dev/null and b/boards/arduino/uno_r4/doc/img/arduino_uno_r4_minima.webp differ
diff --git a/boards/arduino/uno_r4/doc/index.rst b/boards/arduino/uno_r4/doc/index.rst
index 1b2b28385ba..71dcd0d94e4 100644
--- a/boards/arduino/uno_r4/doc/index.rst
+++ b/boards/arduino/uno_r4/doc/index.rst
@@ -1,7 +1,4 @@
-.. _arduino_uno_r4:
-
-Arduino UNO R4
-##############
+.. zephyr:board:: arduino_uno_r4
 
 Overview
 ********
@@ -23,20 +20,13 @@ Hardware
 Supported Features
 ==================
 
-The Arduino UNO R4 Minima/Wifi  board configuration supports the following
-hardware features:
-
-+-----------+------------+------------------------------------------+
-| Interface | Controller | Driver/Component                         |
-+===========+============+==========================================+
-| GPIO      | on-chip    | I/O ports                                |
-+-----------+------------+------------------------------------------+
-| UART      | on-chip    | Serial ports                             |
-+-----------+------------+------------------------------------------+
+.. zephyr:board-supported-hw::
 
 Programming and debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Debug adapter
 =============
 
@@ -60,12 +50,12 @@ Here is an example for building and flashing the :zephyr:code-sample:`blinky` ap
 
 .. zephyr-app-commands::
    :zephyr-app: samples/basic/blinky
-   :board: arduino_uno_r4_minima
+   :board: arduino_uno_r4@minima
    :goals: build flash
 
 .. zephyr-app-commands::
    :zephyr-app: samples/basic/blinky
-   :board: arduino_uno_r4_wifi
+   :board: arduino_uno_r4@wifi
    :goals: build flash
 
 Debugging
@@ -77,13 +67,13 @@ Also, see the instructions specific to the debug server that you use.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/basic/blinky
-   :board: arduino_uno_r4_minima
+   :board: arduino_uno_r4@minima
    :maybe-skip-config:
    :goals: debug
 
 .. zephyr-app-commands::
    :zephyr-app: samples/basic/blinky
-   :board: arduino_uno_r4_wifi
+   :board: arduino_uno_r4@wifi
    :maybe-skip-config:
    :goals: debug
 
diff --git a/boards/arduino/uno_r4/revision.cmake b/boards/arduino/uno_r4/revision.cmake
new file mode 100644
index 00000000000..f148e05dd0a
--- /dev/null
+++ b/boards/arduino/uno_r4/revision.cmake
@@ -0,0 +1,8 @@
+set(BOARD_REVISIONS "minima" "wifi")
+if(NOT DEFINED BOARD_REVISION)
+  set(BOARD_REVISION "minima")
+else()
+  if(NOT BOARD_REVISION IN_LIST BOARD_REVISIONS)
+    message(FATAL_ERROR "${BOARD_REVISION} is not a valid revision for arduino_uno_r4. Accepted revisions: ${BOARD_REVISIONS}")
+  endif()
+endif()
diff --git a/boards/arduino/zero/arduino_zero-pinctrl.dtsi b/boards/arduino/zero/arduino_zero-pinctrl.dtsi
index 52b04cd64a5..573e05ea0cd 100644
--- a/boards/arduino/zero/arduino_zero-pinctrl.dtsi
+++ b/boards/arduino/zero/arduino_zero-pinctrl.dtsi
@@ -6,6 +6,17 @@
 #include <dt-bindings/pinctrl/samd21-da1gXabcd-pinctrl.h>
 
 &pinctrl {
+	adc_default: adc_default {
+		group1 {
+			pinmux = <PA2B_ADC_AIN0>,
+				 <PB8B_ADC_AIN2>,
+				 <PB9B_ADC_AIN3>,
+				 <PA4B_ADC_AIN4>,
+				 <PA5B_ADC_AIN5>,
+				 <PB2B_ADC_AIN10>;
+		};
+	};
+
 	dac_default: dac_default {
 		group1 {
 			pinmux = <PA2B_DAC_VOUT>;
diff --git a/boards/arduino/zero/arduino_zero.dts b/boards/arduino/zero/arduino_zero.dts
index 841e7ab7620..1109ea58b89 100644
--- a/boards/arduino/zero/arduino_zero.dts
+++ b/boards/arduino/zero/arduino_zero.dts
@@ -102,6 +102,13 @@
 	pinctrl-names = "default";
 };
 
+&adc {
+	status = "okay";
+
+	pinctrl-0 = <&adc_default>;
+	pinctrl-names = "default";
+};
+
 &dac0 {
 	status = "okay";
 
diff --git a/boards/arduino/zero/arduino_zero.yaml b/boards/arduino/zero/arduino_zero.yaml
index 771199f1e8f..60e0772e289 100644
--- a/boards/arduino/zero/arduino_zero.yaml
+++ b/boards/arduino/zero/arduino_zero.yaml
@@ -7,7 +7,6 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - counter
diff --git a/boards/arduino/zero/doc/index.rst b/boards/arduino/zero/doc/index.rst
index 9e665aa75cd..150c864b3f9 100644
--- a/boards/arduino/zero/doc/index.rst
+++ b/boards/arduino/zero/doc/index.rst
@@ -1,7 +1,4 @@
-.. _arduino_zero:
-
-Arduino/Genuino Zero
-####################
+.. zephyr:board:: arduino_zero
 
 Overview
 ********
@@ -10,10 +7,6 @@ The Arduino Zero is a maker-friendly development board with
 Atmel’s Embedded Debugger (EDBG), which provides a full
 debug interface without the need for additional hardware.
 
-.. image:: img/arduino_zero.jpg
-     :align: center
-     :alt: Arduino Zero
-
 Hardware
 ********
 
@@ -28,37 +21,7 @@ Hardware
 Supported Features
 ==================
 
-The arduino_zero board configuration supports the following hardware
-features:
-
-+-----------+------------+------------------------------------------+
-| Interface | Controller | Driver/Component                         |
-+===========+============+==========================================+
-| NVIC      | on-chip    | nested vector interrupt controller       |
-+-----------+------------+------------------------------------------+
-| Flash     | on-chip    | Can be used with LittleFS to store files |
-+-----------+------------+------------------------------------------+
-| SYSTICK   | on-chip    | systick                                  |
-+-----------+------------+------------------------------------------+
-| WDT       | on-chip    | Watchdog                                 |
-+-----------+------------+------------------------------------------+
-| GPIO      | on-chip    | I/O ports                                |
-+-----------+------------+------------------------------------------+
-| PWM       | on-chip    | Pulse Width Modulation                   |
-+-----------+------------+------------------------------------------+
-| USART     | on-chip    | Serial ports                             |
-+-----------+------------+------------------------------------------+
-| SPI       | on-chip    | Serial Peripheral Interface ports        |
-+-----------+------------+------------------------------------------+
-| USB       | on-chip    | USB device                               |
-+-----------+------------+------------------------------------------+
-| DAC       | on-chip    | Digital to analogue converter            |
-+-----------+------------+------------------------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig
-:zephyr_file:`boards/arduino/zero/arduino_zero_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -111,6 +74,8 @@ Arduino Zero, the DAC is available on pin A0.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The Arduino Zero comes with a Atmel Embedded Debugger (EDBG).  This
 provides a debug interface to the SAMD21 chip and is supported by
 OpenOCD.
diff --git a/boards/arm/fvp_baser_aemv8r/doc/aarch32.rst b/boards/arm/fvp_baser_aemv8r/doc/aarch32.rst
index 8fcc4d07b0e..080d316e6b7 100644
--- a/boards/arm/fvp_baser_aemv8r/doc/aarch32.rst
+++ b/boards/arm/fvp_baser_aemv8r/doc/aarch32.rst
@@ -82,7 +82,7 @@ Arm FVP emulated environment, for example, with the :zephyr:code-sample:`synchro
 .. zephyr-app-commands::
    :zephyr-app: samples/synchronization
    :host-os: unix
-   :board: fvp_baser_aemv8r_aarch32
+   :board: fvp_baser_aemv8r/fvp_aemv8r_aarch32
    :goals: build
 
 This will build an image with the synchronization sample app.
diff --git a/boards/arm/fvp_baser_aemv8r/doc/aarch64.rst b/boards/arm/fvp_baser_aemv8r/doc/aarch64.rst
index 724ee182cc9..0f9a28d0a81 100644
--- a/boards/arm/fvp_baser_aemv8r/doc/aarch64.rst
+++ b/boards/arm/fvp_baser_aemv8r/doc/aarch64.rst
@@ -91,7 +91,7 @@ Arm FVP emulated environment, for example, with the :zephyr:code-sample:`synchro
 .. zephyr-app-commands::
    :zephyr-app: samples/synchronization
    :host-os: unix
-   :board: fvp_baser_aemv8r
+   :board: fvp_baser_aemv8r/fvp_aemv8r_aarch64
    :goals: build
 
 This will build an image with the synchronization sample app.
diff --git a/boards/arm/mps2/CMakeLists.txt b/boards/arm/mps2/CMakeLists.txt
index 2f6cea861c6..7a2209df8f8 100644
--- a/boards/arm/mps2/CMakeLists.txt
+++ b/boards/arm/mps2/CMakeLists.txt
@@ -1,8 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-zephyr_library()
-zephyr_library_sources(pinmux.c)
-
 if(CONFIG_BOARD_MPS2_AN521_CPU1 AND NOT CONFIG_OPENAMP)
   # Building a firmware image for CPU1: this requires a binary
   # for CPU0, which will boot the device and wake up CPU1.
diff --git a/boards/arm/mps2/Kconfig b/boards/arm/mps2/Kconfig
index 4beda641d53..0170bebb4d9 100644
--- a/boards/arm/mps2/Kconfig
+++ b/boards/arm/mps2/Kconfig
@@ -1,6 +1,7 @@
 # Copyright (c) 2017 Linaro Limited
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_MPS2
-	select QEMU_TARGET
 	select HAS_COVERAGE_SUPPORT
+	select QEMU_TARGET if BOARD_MPS2_AN385 || BOARD_MPS2_AN521_CPU0 || BOARD_MPS2_AN521_CPU0_NS || BOARD_MPS2_AN521_CPU1
diff --git a/boards/arm/mps2/Kconfig.defconfig b/boards/arm/mps2/Kconfig.defconfig
index b14613b4880..367e09c2a9a 100644
--- a/boards/arm/mps2/Kconfig.defconfig
+++ b/boards/arm/mps2/Kconfig.defconfig
@@ -1,7 +1,8 @@
 # Copyright (c) 2017 Linaro Limited
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
-if BOARD_MPS2_AN385
+if BOARD_MPS2_AN383 || BOARD_MPS2_AN385 || BOARD_MPS2_AN386 || BOARD_MPS2_AN500
 
 if SERIAL
 
diff --git a/boards/arm/mps2/Kconfig.mps2 b/boards/arm/mps2/Kconfig.mps2
index 0731c5d2855..c350ffeb8cb 100644
--- a/boards/arm/mps2/Kconfig.mps2
+++ b/boards/arm/mps2/Kconfig.mps2
@@ -1,8 +1,12 @@
 # Copyright (c) 2017 Linaro Limited
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_MPS2
+	select SOC_MPS2_AN383 if BOARD_MPS2_AN383
 	select SOC_MPS2_AN385 if BOARD_MPS2_AN385
+	select SOC_MPS2_AN386 if BOARD_MPS2_AN386
+	select SOC_MPS2_AN500 if BOARD_MPS2_AN500
 	select SOC_MPS2_AN521_CPU0 if BOARD_MPS2_AN521_CPU0
 	select SOC_MPS2_AN521_CPU0 if BOARD_MPS2_AN521_CPU0_NS
 	select SOC_MPS2_AN521_CPU1 if BOARD_MPS2_AN521_CPU1
diff --git a/boards/arm/mps2/board.cmake b/boards/arm/mps2/board.cmake
index 6f38d01281b..98e34a99748 100644
--- a/boards/arm/mps2/board.cmake
+++ b/boards/arm/mps2/board.cmake
@@ -1,8 +1,8 @@
 # SPDX-License-Identifier: Apache-2.0
-
-set(SUPPORTED_EMU_PLATFORMS qemu)
+# Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
 
 if(CONFIG_BOARD_MPS2_AN385)
+  set(SUPPORTED_EMU_PLATFORMS qemu armfvp)
   set(QEMU_CPU_TYPE_${ARCH} cortex-m3)
   set(QEMU_FLAGS_${ARCH}
     -cpu ${QEMU_CPU_TYPE_${ARCH}}
@@ -10,7 +10,23 @@ if(CONFIG_BOARD_MPS2_AN385)
     -nographic
     -vga none
     )
+  set(ARMFVP_BIN_NAME FVP_MPS2_Cortex-M3)
+elseif(CONFIG_BOARD_MPS2_AN383)
+  set(SUPPORTED_EMU_PLATFORMS armfvp)
+  set(ARMFVP_BIN_NAME FVP_MPS2_Cortex-M0plus)
+  set(ARMFVP_FLAGS
+  -C armcortexm0plusct.NUM_MPU_REGION=8
+  -C armcortexm0plusct.USER=1
+  -C armcortexm0plusct.VTOR=1
+  )
+elseif(CONFIG_BOARD_MPS2_AN386)
+  set(SUPPORTED_EMU_PLATFORMS armfvp)
+  set(ARMFVP_BIN_NAME FVP_MPS2_Cortex-M4)
+elseif(CONFIG_BOARD_MPS2_AN500)
+  set(SUPPORTED_EMU_PLATFORMS armfvp)
+  set(ARMFVP_BIN_NAME FVP_MPS2_Cortex-M7)
 elseif(CONFIG_BOARD_MPS2_AN521_CPU0 OR CONFIG_BOARD_MPS2_AN521_CPU0_NS OR CONFIG_BOARD_MPS2_AN521_CPU1)
+  set(SUPPORTED_EMU_PLATFORMS qemu)
   set(QEMU_CPU_TYPE_${ARCH} cortex-m33)
   set(QEMU_FLAGS_${ARCH}
     -cpu ${QEMU_CPU_TYPE_${ARCH}}
@@ -19,11 +35,7 @@ elseif(CONFIG_BOARD_MPS2_AN521_CPU0 OR CONFIG_BOARD_MPS2_AN521_CPU0_NS OR CONFIG
     -m 16
     -vga none
     )
-endif()
-
-board_set_debugger_ifnset(qemu)
 
-if(CONFIG_BOARD_MPS2_AN521_CPU0 OR CONFIG_BOARD_MPS2_AN521_CPU0_NS OR CONFIG_BOARD_MPS2_AN521_CPU1)
   # To enable a host tty switch between serial and pty
   #  -chardev serial,path=/dev/ttyS0,id=hostS0
   # pty is not available on Windows.
@@ -36,6 +48,8 @@ if(CONFIG_BOARD_MPS2_AN521_CPU0 OR CONFIG_BOARD_MPS2_AN521_CPU0_NS OR CONFIG_BOA
     # TF-M (Secure) & Zephyr (Non Secure) image (when running
     # in-tree tests).
     set(QEMU_KERNEL_OPTION "-device;loader,file=${CMAKE_BINARY_DIR}/zephyr/tfm_merged.hex")
+
+    set(ARMFVP_FLAGS ${ARMFVP_FLAGS} -a ${APPLICATION_BINARY_DIR}/zephyr/tfm_merged.hex)
   elseif(CONFIG_OPENAMP)
     set(QEMU_EXTRA_FLAGS "-device;loader,file=${REMOTE_ZEPHYR_DIR}/zephyr.elf")
   elseif(CONFIG_BOARD_MPS2_AN521_CPU1)
@@ -44,3 +58,18 @@ if(CONFIG_BOARD_MPS2_AN521_CPU0 OR CONFIG_BOARD_MPS2_AN521_CPU0_NS OR CONFIG_BOA
     list(APPEND QEMU_EXTRA_FLAGS "-device;loader,file=${PROJECT_BINARY_DIR}/${KERNEL_ELF_NAME}")
   endif()
 endif()
+
+board_set_debugger_ifnset(qemu)
+
+set(ARMFVP_FLAGS ${ARMFVP_FLAGS}
+-C fvp_mps2.telnetterminal0.start_telnet=0
+-C fvp_mps2.telnetterminal1.start_telnet=0
+-C fvp_mps2.telnetterminal2.start_telnet=0
+-C fvp_mps2.UART0.out_file=-
+-C fvp_mps2.UART0.unbuffered_output=1
+-C fvp_mps2.UART1.out_file=-
+-C fvp_mps2.UART1.unbuffered_output=1
+-C fvp_mps2.UART2.out_file=-
+-C fvp_mps2.UART2.unbuffered_output=1
+-C fvp_mps2.mps2_visualisation.disable-visualisation=1
+)
diff --git a/boards/arm/mps2/board.yml b/boards/arm/mps2/board.yml
index 779a8ed21cc..5548cd05b17 100644
--- a/boards/arm/mps2/board.yml
+++ b/boards/arm/mps2/board.yml
@@ -3,7 +3,10 @@ board:
   full_name: V2M MPS2
   vendor: arm
   socs:
+  - name: an383
   - name: an385
+  - name: an386
+  - name: an500
   - name: an521
     variants:
     - name: ns
diff --git a/boards/arm/mps2/doc/img/mps2_an521.jpg b/boards/arm/mps2/doc/img/mps2.jpg
similarity index 100%
rename from boards/arm/mps2/doc/img/mps2_an521.jpg
rename to boards/arm/mps2/doc/img/mps2.jpg
diff --git a/boards/arm/mps2/doc/img/mps2_an385.jpg b/boards/arm/mps2/doc/img/mps2_an385.jpg
deleted file mode 100644
index 58e42290939..00000000000
Binary files a/boards/arm/mps2/doc/img/mps2_an385.jpg and /dev/null differ
diff --git a/boards/arm/mps2/doc/index.rst b/boards/arm/mps2/doc/index.rst
new file mode 100644
index 00000000000..b102b37fd80
--- /dev/null
+++ b/boards/arm/mps2/doc/index.rst
@@ -0,0 +1,10 @@
+.. zephyr:board:: mps2
+
+ARM Ltd.
+########
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   *
diff --git a/boards/arm/mps2/doc/mps2_an385.rst b/boards/arm/mps2/doc/mps2_an385.rst
deleted file mode 100644
index 79f01dc9c53..00000000000
--- a/boards/arm/mps2/doc/mps2_an385.rst
+++ /dev/null
@@ -1,281 +0,0 @@
-.. _mps2_an385_board:
-
-ARM V2M MPS2
-############
-
-Overview
-********
-
-The mps2/an385 board configuration is used by Zephyr applications that run on
-the V2M MPS2 board. It provides support for the ARM Cortex-M3 (AN385) CPU and
-the following devices:
-
-- Nested Vectored Interrupt Controller (NVIC)
-- System Tick System Clock (SYSTICK)
-- Cortex-M System Design Kit UART
-
-.. image:: img/mps2_an385.jpg
-     :align: center
-     :alt: ARM V2M MPS2
-
-In addition to enabling actual hardware usage, this board configuration can
-also use QEMU to emulate the AN385 platform running on the MPS2+.
-
-More information about the board can be found at the `V2M MPS2 Website`_.
-
-The Application Note AN385 can be found at `Application Note AN385`_.
-
-.. note::
-   This board configuration makes no claims about its suitability for use
-   with actual MPS2 hardware systems using AN385, or any other hardware
-   system. It has been tested on actual hardware, but its primary purpose is
-   for use with QEMU and unit tests.
-
-Hardware
-********
-
-ARM V2M MPS2 provides the following hardware components:
-
-- ARM Cortex-M3 (AN385)
-- ARM IoT Subsystem for Cortex-M
-- Form factor: 140x120cm
-- ZBTSRAM: 8MB single cycle SRAM, 16MB PSRAM
-- Video: QSVGA touch screen panel, 4bit RGB VGA connector
-- Audio: Audio Codec
-- Debug:
-
-  - ARM JTAG20 connector
-  - ARM parallel trace connector (MICTOR38)
-  - 20 pin Cortex debug connector
-  - 10 pin Cortex debug connector
-  - ILA connector for FPGA debug
-
-- Expansion
-
-  - GPIO
-  - SPI
-
-.. note::
-   4 MB of flash memory (in ZBTSRAM 1, starting at address 0x00400000) and 4 MB of RAM
-   (in ZBTSRAM 2 & 3, starting at address 0x20000000) are available.
-
-Supported Features
-==================
-
-The mps2/an385 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| TIMER     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| DUALTIMER | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by the port.
-See the `V2M MPS2 Website`_ for a complete list of V2M MPS2 board hardware
-features.
-
-The default configuration can be found in
-:zephyr_file:`boards/arm/mps2/mps2_an385_defconfig`
-
-Interrupt Controller
-====================
-
-MPS2 is a Cortex-M3 based SoC and has 15 fixed exceptions and 45 IRQs.
-
-A Cortex-M3/4-based board uses vectored exceptions. This means each exception
-calls a handler directly from the vector table.
-
-Handlers are provided for exceptions 1-6, 11-12, and 14-15. The table here
-identifies the handlers used for each exception.
-
-+------+------------+----------------+--------------------------+
-| Exc# | Name       | Remarks        | Used by Zephyr Kernel    |
-+======+============+================+==========================+
-| 1    | Reset      |                | system initialization    |
-+------+------------+----------------+--------------------------+
-| 2    | NMI        |                | system fatal error       |
-+------+------------+----------------+--------------------------+
-| 3    | Hard fault |                | system fatal error       |
-+------+------------+----------------+--------------------------+
-| 4    | MemManage  | MPU fault      | system fatal error       |
-+------+------------+----------------+--------------------------+
-| 5    | Bus        |                | system fatal error       |
-+------+------------+----------------+--------------------------+
-| 6    | Usage      | undefined      | system fatal error       |
-|      | fault      | instruction,   |                          |
-|      |            | or switch      |                          |
-|      |            | attempt to ARM |                          |
-|      |            | mode           |                          |
-+------+------------+----------------+--------------------------+
-| 11   | SVC        |                | system calls, kernel     |
-|      |            |                | run-time exceptions,     |
-|      |            |                | and IRQ offloading       |
-+------+------------+----------------+--------------------------+
-| 12   | Debug      |                | system fatal error       |
-|      | monitor    |                |                          |
-+------+------------+----------------+--------------------------+
-| 14   | PendSV     |                | context switch           |
-+------+------------+----------------+--------------------------+
-| 15   | SYSTICK    |                | system clock             |
-+------+------------+----------------+--------------------------+
-
-Pin Mapping
-===========
-
-The ARM V2M MPS2 Board has 4 GPIO controllers. These controllers are responsible
-for pin muxing, input/output, pull-up, etc.
-
-All GPIO controller pins are exposed via the following sequence of pin numbers:
-
-- Pins 0 - 15 are for GPIO 0
-- Pins 16 - 31 are for GPIO 1
-- Pins 32 -  47 are for GPIO 2
-- Pins 48 -  51 are for GPIO 3
-
-Mapping from the ARM MPS2 Board pins to GPIO controllers:
-
-.. rst-class:: rst-columns
-
-   - D0 : EXT_0
-   - D1 : EXT_4
-   - D2 : EXT_2
-   - D3 : EXT_3
-   - D4 : EXT_1
-   - D5 : EXT_6
-   - D6 : EXT_7
-   - D7 : EXT_8
-   - D8 : EXT_9
-   - D9 : EXT_10
-   - D10 : EXT_12
-   - D11 : EXT_13
-   - D12 : EXT_14
-   - D13 : EXT_11
-   - D14 : EXT_15
-   - D15 : EXT_5
-   - D16 : EXT_16
-   - D17 : EXT_17
-   - D18 : EXT_18
-   - D19 : EXT_19
-   - D20 : EXT_20
-   - D21 : EXT_21
-   - D22 : EXT_22
-   - D23 : EXT_23
-   - D24 : EXT_24
-   - D25 : EXT_25
-   - D26 : EXT_26
-   - D27 : EXT_30
-   - D28 : EXT_28
-   - D29 : EXT_29
-   - D30 : EXT_27
-   - D31 : EXT_32
-   - D32 : EXT_33
-   - D33 : EXT_34
-   - D34 : EXT_35
-   - D35 : EXT_36
-   - D36 : EXT_38
-   - D37 : EXT_39
-   - D38 : EXT_40
-   - D39 : EXT_44
-   - D40 : EXT_41
-   - D41 : EXT_31
-   - D42 : EXT_37
-   - D43 : EXT_42
-   - D44 : EXT_43
-   - D45 : EXT_45
-   - D46 : EXT_46
-   - D47 : EXT_47
-   - D48 : EXT_48
-   - D49 : EXT_49
-   - D50 : EXT_50
-   - D51 : EXT_51
-
-Peripheral Mapping:
-
-.. rst-class:: rst-columns
-
-   - UART_3_RX : D0
-   - UART_3_TX : D1
-   - SPI_3_CS : D10
-   - SPI_3_MOSI : D11
-   - SPI_3_MISO : D12
-   - SPI_3_SCLK : D13
-   - I2C_3_SDA : D14
-   - I2C_3_SCL : D15
-   - UART_4_RX : D26
-   - UART_4_TX : D30
-   - SPI_4_CS : D36
-   - SPI_4_MOSI : D37
-   - SPI_4_MISO : D38
-   - SPI_4_SCK : D39
-   - I2C_4_SDA : D40
-   - I2C_4_SCL : D41
-
-For more details please refer to `MPS2 Technical Reference Manual (TRM)`_.
-
-System Clock
-============
-
-The V2M MPS2 main clock is 24 MHz.
-
-Serial Port
-===========
-
-The V2M MPS2 processor has five UARTs. Both the UARTs have only two wires for
-RX/TX and no flow control (CTS/RTS) or FIFO. The Zephyr console output, by
-default, is utilizing UART0.
-
-Programming and Debugging
-*************************
-
-Flashing
-========
-
-V2M MPS2 provides:
-
-- A USB connection to the host computer, which exposes a Mass Storage and an
-  USB Serial Port.
-- A Serial Flash device, which implements the USB flash disk file storage.
-- A physical UART connection which is relayed over interface USB Serial port.
-
-Flashing an application to V2M MPS2
------------------------------------
-
-Here is an example for the :zephyr:code-sample:`hello_world` application.
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/hello_world
-   :board: mps2/an385
-   :goals: build
-
-Connect the V2M MPS2 to your host computer using the USB port and you should
-see a USB connection which exposes a Mass Storage and a USB Serial Port.
-Copy the generated zephyr.bin in the exposed drive.
-Reset the board and you should be able to see on the corresponding Serial Port
-the following message:
-
-.. code-block:: console
-
-   Hello World! arm
-
-
-.. _V2M MPS2 Website:
-   https://developer.mbed.org/platforms/ARM-MPS2/
-
-.. _MPS2 Technical Reference Manual (TRM):
-   http://infocenter.arm.com/help/topic/com.arm.doc.100112_0200_05_en/versatile_express_cortex_m_prototyping_systems_v2m_mps2_and_v2m_mps2plus_technical_reference_100112_0200_05_en.pdf
-
-.. _Application Note AN385:
-   http://infocenter.arm.com/help/topic/com.arm.doc.dai0385c/DAI0385C_cortex_m3_on_v2m_mps2.pdf
diff --git a/boards/arm/mps2/doc/mps2_an521.rst b/boards/arm/mps2/doc/mps2_an521.rst
index 33a4f4d7ca6..067b4f286b0 100644
--- a/boards/arm/mps2/doc/mps2_an521.rst
+++ b/boards/arm/mps2/doc/mps2_an521.rst
@@ -15,7 +15,7 @@ CPU and the following devices:
 - Cortex-M System Design Kit GPIO
 - Cortex-M System Design Kit UART
 
-.. image:: img/mps2_an521.jpg
+.. image:: img/mps2.jpg
      :align: center
      :alt: ARM MPS2+ AN521
 
diff --git a/boards/arm/mps2/doc/mps2_armv6m.rst b/boards/arm/mps2/doc/mps2_armv6m.rst
new file mode 100644
index 00000000000..11666d3cf62
--- /dev/null
+++ b/boards/arm/mps2/doc/mps2_armv6m.rst
@@ -0,0 +1,281 @@
+.. _mps2_armv6m_board:
+
+ARM V2M MPS2 Armv6-m (AN383)
+############################
+
+Overview
+********
+
+Currently ``mps2/an383`` is the only mps2 Armv6-m based board target supported in Zephyr.
+It provides support for the ARM Cortex-M0+ (AN383) CPU and the following devices:
+
+- Nested Vectored Interrupt Controller (NVIC)
+- System Tick System Clock (SYSTICK)
+- Cortex-M System Design Kit UART
+
+.. image:: img/mps2.jpg
+     :align: center
+     :alt: ARM V2M MPS2
+
+In addition to enabling actual hardware usage, this board target can
+also use `FVP`_. to emulate the AN383 platform running on the MPS2+.
+
+More information about the board can be found at the `V2M MPS2 Website`_.
+
+The Application Note AN383 can be found at `Application Note AN383`_.
+
+.. note::
+   This board target makes no claims about its suitability for use
+   with actual MPS2 hardware systems using AN383, or any other hardware
+   system. It has been tested on FVP.
+
+
+Hardware
+********
+
+ARM V2M MPS2 AN383 provides the following hardware components:
+
+- ARM Cortex-M0+
+- ARM IoT Subsystem for Cortex-M
+- Form factor: 140x120cm
+- ZBTSRAM: 8MB single cycle SRAM, 16MB PSRAM
+- Video: QSVGA touch screen panel, 4bit RGB VGA connector
+- Audio: Audio Codec
+- Debug:
+
+  - ARM JTAG20 connector
+  - ARM parallel trace connector (MICTOR38)
+  - 20 pin Cortex debug connector
+  - 10 pin Cortex debug connector
+  - ILA connector for FPGA debug
+
+- Expansion
+
+  - GPIO
+  - SPI
+
+.. note::
+   4 MB of flash memory (in ZBTSRAM 1, starting at address 0x00400000) and 4 MB of RAM
+   (in ZBTSRAM 2 & 3, starting at address 0x20000000) are available.
+
+Supported Features
+==================
+
+The ``mps2/an383`` board target supports the following hardware features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| SYSTICK   | on-chip    | systick                             |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port-polling;                |
+|           |            | serial port-interrupt               |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| WATCHDOG  | on-chip    | watchdog                            |
++-----------+------------+-------------------------------------+
+| TIMER     | on-chip    | counter                             |
++-----------+------------+-------------------------------------+
+| DUALTIMER | on-chip    | counter                             |
++-----------+------------+-------------------------------------+
+
+Other hardware features are not currently supported by the port.
+See the `V2M MPS2 Website`_ for a complete list of V2M MPS2 board hardware
+features.
+
+The default configuration can be found in
+:zephyr_file:`boards/arm/mps2/mps2_an383_defconfig`
+
+Interrupt Controller
+====================
+
+MPS2 is a Cortex-M0+ based SoC and has 6 fixed exceptions and 32 IRQs.
+
+A Cortex-M0+ board uses vectored exceptions. This means each exception
+calls a handler directly from the vector table.
+
+Handlers are provided for exceptions 1-3, 11, and 14-15. The table here
+MPS2 is a Cortex-M0+ based SoC and has 15 fixed exceptions and 45 IRQs.
+
++------+------------+----------------+--------------------------+
+| Exc# | Name       | Remarks        | Used by Zephyr Kernel    |
++======+============+================+==========================+
+| 1    | Reset      |                | system initialization    |
++------+------------+----------------+--------------------------+
+| 2    | NMI        |                | system fatal error       |
++------+------------+----------------+--------------------------+
+| 3    | Hard fault |                | system fatal error       |
++------+------------+----------------+--------------------------+
+| 11   | SVC        |                | system calls, kernel     |
+|      |            |                | run-time exceptions,     |
+|      |            |                | and IRQ offloading       |
++------+------------+----------------+--------------------------+
+| 14   | PendSV     |                | context switch           |
++------+------------+----------------+--------------------------+
+| 15   | SYSTICK    | optional       | system clock             |
++------+------------+----------------+--------------------------+
+
+Pin Mapping
+===========
+
+The ARM V2M MPS2 Board has 4 GPIO controllers. These controllers are responsible
+for pin muxing, input/output, pull-up, etc.
+
+All GPIO controller pins are exposed via the following sequence of pin numbers:
+
+- Pins 0 - 15 are for GPIO 0
+- Pins 16 - 31 are for GPIO 1
+- Pins 32 -  47 are for GPIO 2
+- Pins 48 -  51 are for GPIO 3
+
+Mapping from the ARM MPS2 Board pins to GPIO controllers:
+
+.. rst-class:: rst-columns
+
+   - D0 : EXT_0
+   - D1 : EXT_4
+   - D2 : EXT_2
+   - D3 : EXT_3
+   - D4 : EXT_1
+   - D5 : EXT_6
+   - D6 : EXT_7
+   - D7 : EXT_8
+   - D8 : EXT_9
+   - D9 : EXT_10
+   - D10 : EXT_12
+   - D11 : EXT_13
+   - D12 : EXT_14
+   - D13 : EXT_11
+   - D14 : EXT_15
+   - D15 : EXT_5
+   - D16 : EXT_16
+   - D17 : EXT_17
+   - D18 : EXT_18
+   - D19 : EXT_19
+   - D20 : EXT_20
+   - D21 : EXT_21
+   - D22 : EXT_22
+   - D23 : EXT_23
+   - D24 : EXT_24
+   - D25 : EXT_25
+   - D26 : EXT_26
+   - D27 : EXT_30
+   - D28 : EXT_28
+   - D29 : EXT_29
+   - D30 : EXT_27
+   - D31 : EXT_32
+   - D32 : EXT_33
+   - D33 : EXT_34
+   - D34 : EXT_35
+   - D35 : EXT_36
+   - D36 : EXT_38
+   - D37 : EXT_39
+   - D38 : EXT_40
+   - D39 : EXT_44
+   - D40 : EXT_41
+   - D41 : EXT_31
+   - D42 : EXT_37
+   - D43 : EXT_42
+   - D44 : EXT_43
+   - D45 : EXT_45
+   - D46 : EXT_46
+   - D47 : EXT_47
+   - D48 : EXT_48
+   - D49 : EXT_49
+   - D50 : EXT_50
+   - D51 : EXT_51
+
+Peripheral Mapping:
+
+.. rst-class:: rst-columns
+
+   - UART_3_RX : D0
+   - UART_3_TX : D1
+   - SPI_3_CS : D10
+   - SPI_3_MOSI : D11
+   - SPI_3_MISO : D12
+   - SPI_3_SCLK : D13
+   - I2C_3_SDA : D14
+   - I2C_3_SCL : D15
+   - UART_4_RX : D26
+   - UART_4_TX : D30
+   - SPI_4_CS : D36
+   - SPI_4_MOSI : D37
+   - SPI_4_MISO : D38
+   - SPI_4_SCK : D39
+   - I2C_4_SDA : D40
+   - I2C_4_SCL : D41
+
+For more details please refer to `MPS2 Technical Reference Manual (TRM)`_.
+
+System Clock
+============
+
+The V2M MPS2 main clock is 24 MHz.
+
+Serial Port
+===========
+
+The V2M MPS2 processor has five UARTs. Both the UARTs have only two wires for
+RX/TX and no flow control (CTS/RTS) or FIFO. The Zephyr console output, by
+default, is utilizing UART0.
+
+Programming and Debugging
+*************************
+
+Flashing
+========
+
+V2M MPS2 provides:
+
+- A USB connection to the host computer, which exposes a Mass Storage and an
+  USB Serial Port.
+- A Serial Flash device, which implements the USB flash disk file storage.
+- A physical UART connection which is relayed over interface USB Serial port.
+
+Flashing an application to V2M MPS2
+-----------------------------------
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: mps2/an383
+   :goals: build
+
+Connect the V2M MPS2 to your host computer using the USB port and you should
+see a USB connection which exposes a Mass Storage and a USB Serial Port.
+Copy the generated zephyr.bin in the exposed drive.
+Reset the board and you should be able to see on the corresponding Serial Port
+the following message:
+
+.. code-block:: console
+
+   Hello World! arm
+
+Running an applicatoin with FVP
+-------------------------------
+
+Here is the same example for running with FVP.
+Set the ``ARMFVP_BIN_PATH`` environemnt variable to the location of your FVP you have downloaded from `here <FVP_>`_
+
+.. code-block:: console
+
+    export ARMFVP_BIN_PATH=/home/../FVP_MPS2/
+
+Then build with the same command you would use normally, and run with ``west build -t run_armfvp``.
+
+.. _V2M MPS2 Website:
+   https://developer.mbed.org/platforms/ARM-MPS2/
+
+.. _MPS2 Technical Reference Manual (TRM):
+   https://developer.arm.com/documentation/100112/0200/
+
+.. _Application Note AN383:
+   https://documentation-service.arm.com/static/5ed1051dca06a95ce53f88a1
+
+.. _FVP:
+   https://developer.arm.com/downloads/view/FMFVP
diff --git a/boards/arm/mps2/doc/mps2_armv7m.rst b/boards/arm/mps2/doc/mps2_armv7m.rst
new file mode 100644
index 00000000000..ab6fab5d292
--- /dev/null
+++ b/boards/arm/mps2/doc/mps2_armv7m.rst
@@ -0,0 +1,308 @@
+.. _mps2_armv7m_board:
+
+ARM V2M MPS2 Armv7-m (AN385/AN386/AN500)
+########################################
+
+Overview
+********
+
+The ``mps2/an385``, ``mps2/an386``, and ``mps2/an500`` board targets are three of
+the mps2 Armv7-m based board targets supported in Zephyr. This document
+provides details about the support provided for these three Armv7-m mps2 board targets
+(**AN385**, **AN386**, **AN500**) and the following devices:
+
+- Nested Vectored Interrupt Controller (NVIC)
+- System Tick System Clock (SYSTICK)
+- Cortex-M System Design Kit UART
+
+.. image:: img/mps2.jpg
+     :align: center
+     :alt: ARM V2M MPS2
+
+In addition to enabling actual hardware usage, these board targets can
+also use `FVP`_ to emulate the platforms running on the MPS2+.
+
+More information about the board can be found at the `V2M MPS2 Website`_.
+
+The application note for each of the board can be found as follows:
+
+- AN385 can be found at `Application Note AN385`_
+- AN386 can be found at `Application Note AN386`_
+- AN500 can be found at `Application Note AN500`_
+
+AN385 is also supported to run with QEMU, and is set to run with QEMU by default.
+
+.. note::
+   These board targets makes no claims about its suitability for use
+   with actual MPS2 hardware systems, or any other hardware
+   system.
+
+Hardware
+********
+
+ARM V2M MPS2 provides the following hardware components:
+
+- ARM Cortex-M Chip
+- ARM IoT Subsystem for Cortex-M
+- Form factor: 140x120cm
+- ZBTSRAM: 8MB single cycle SRAM, 16MB PSRAM
+- Video: QSVGA touch screen panel, 4bit RGB VGA connector
+- Audio: Audio Codec
+- Debug:
+
+  - ARM JTAG20 connector
+  - ARM parallel trace connector (MICTOR38)
+  - 20 pin Cortex debug connector
+  - 10 pin Cortex debug connector
+  - ILA connector for FPGA debug
+
+- Expansion
+
+  - GPIO
+  - SPI
+
+.. note::
+   4 MB of flash memory (in ZBTSRAM 1, starting at address 0x00400000) and 4 MB of RAM
+   (in ZBTSRAM 2 & 3, starting at address 0x20000000) are available.
+
+Supported Features
+==================
+
+The ``mps2/an385``, ``mps2/an386``, and ``mps2/an500`` board targets support the following hardware features:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| NVIC      | on-chip    | nested vector interrupt controller  |
++-----------+------------+-------------------------------------+
+| SYSTICK   | on-chip    | systick                             |
++-----------+------------+-------------------------------------+
+| UART      | on-chip    | serial port-polling;                |
+|           |            | serial port-interrupt               |
++-----------+------------+-------------------------------------+
+| GPIO      | on-chip    | gpio                                |
++-----------+------------+-------------------------------------+
+| WATCHDOG  | on-chip    | watchdog                            |
++-----------+------------+-------------------------------------+
+| TIMER     | on-chip    | counter                             |
++-----------+------------+-------------------------------------+
+| DUALTIMER | on-chip    | counter                             |
++-----------+------------+-------------------------------------+
+
+Other hardware features are not currently supported by the port.
+See the `V2M MPS2 Website`_ for a complete list of V2M MPS2 board hardware
+features.
+
+The default configuration can be found in
+:zephyr_file:`boards/arm/mps2/mps2_an385_defconfig`
+or similarly in ``mps2_anxxx_defconfig`` for the other applicable boards.
+
+Interrupt Controller
+====================
+
+MPS2 is a Cortex-M based SoC and has 15 fixed exceptions and 45 IRQs.
+
+A Cortex-M3/4/7-based board uses vectored exceptions. This means each exception
+calls a handler directly from the vector table.
+
+Handlers are provided for exceptions 1-6, 11-12, and 14-15. The table here
+identifies the handlers used for each exception.
+
++------+------------+----------------+--------------------------+
+| Exc# | Name       | Remarks        | Used by Zephyr Kernel    |
++======+============+================+==========================+
+| 1    | Reset      |                | system initialization    |
++------+------------+----------------+--------------------------+
+| 2    | NMI        |                | system fatal error       |
++------+------------+----------------+--------------------------+
+| 3    | Hard fault |                | system fatal error       |
++------+------------+----------------+--------------------------+
+| 4    | MemManage  | MPU fault      | system fatal error       |
++------+------------+----------------+--------------------------+
+| 5    | Bus        |                | system fatal error       |
++------+------------+----------------+--------------------------+
+| 6    | Usage      | undefined      | system fatal error       |
+|      | fault      | instruction,   |                          |
+|      |            | or switch      |                          |
+|      |            | attempt to ARM |                          |
+|      |            | mode           |                          |
++------+------------+----------------+--------------------------+
+| 11   | SVC        |                | system calls, kernel     |
+|      |            |                | run-time exceptions,     |
+|      |            |                | and IRQ offloading       |
++------+------------+----------------+--------------------------+
+| 12   | Debug      |                | system fatal error       |
+|      | monitor    |                |                          |
++------+------------+----------------+--------------------------+
+| 14   | PendSV     |                | context switch           |
++------+------------+----------------+--------------------------+
+| 15   | SYSTICK    |                | system clock             |
++------+------------+----------------+--------------------------+
+
+Pin Mapping
+===========
+
+The ARM V2M MPS2 Board has 4 GPIO controllers. These controllers are responsible
+for pin muxing, input/output, pull-up, etc.
+
+All GPIO controller pins are exposed via the following sequence of pin numbers:
+
+- Pins 0 - 15 are for GPIO 0
+- Pins 16 - 31 are for GPIO 1
+- Pins 32 -  47 are for GPIO 2
+- Pins 48 -  51 are for GPIO 3
+
+Mapping from the ARM MPS2 Board pins to GPIO controllers:
+
+.. rst-class:: rst-columns
+
+   - D0 : EXT_0
+   - D1 : EXT_4
+   - D2 : EXT_2
+   - D3 : EXT_3
+   - D4 : EXT_1
+   - D5 : EXT_6
+   - D6 : EXT_7
+   - D7 : EXT_8
+   - D8 : EXT_9
+   - D9 : EXT_10
+   - D10 : EXT_12
+   - D11 : EXT_13
+   - D12 : EXT_14
+   - D13 : EXT_11
+   - D14 : EXT_15
+   - D15 : EXT_5
+   - D16 : EXT_16
+   - D17 : EXT_17
+   - D18 : EXT_18
+   - D19 : EXT_19
+   - D20 : EXT_20
+   - D21 : EXT_21
+   - D22 : EXT_22
+   - D23 : EXT_23
+   - D24 : EXT_24
+   - D25 : EXT_25
+   - D26 : EXT_26
+   - D27 : EXT_30
+   - D28 : EXT_28
+   - D29 : EXT_29
+   - D30 : EXT_27
+   - D31 : EXT_32
+   - D32 : EXT_33
+   - D33 : EXT_34
+   - D34 : EXT_35
+   - D35 : EXT_36
+   - D36 : EXT_38
+   - D37 : EXT_39
+   - D38 : EXT_40
+   - D39 : EXT_44
+   - D40 : EXT_41
+   - D41 : EXT_31
+   - D42 : EXT_37
+   - D43 : EXT_42
+   - D44 : EXT_43
+   - D45 : EXT_45
+   - D46 : EXT_46
+   - D47 : EXT_47
+   - D48 : EXT_48
+   - D49 : EXT_49
+   - D50 : EXT_50
+   - D51 : EXT_51
+
+Peripheral Mapping:
+
+.. rst-class:: rst-columns
+
+   - UART_3_RX : D0
+   - UART_3_TX : D1
+   - SPI_3_CS : D10
+   - SPI_3_MOSI : D11
+   - SPI_3_MISO : D12
+   - SPI_3_SCLK : D13
+   - I2C_3_SDA : D14
+   - I2C_3_SCL : D15
+   - UART_4_RX : D26
+   - UART_4_TX : D30
+   - SPI_4_CS : D36
+   - SPI_4_MOSI : D37
+   - SPI_4_MISO : D38
+   - SPI_4_SCK : D39
+   - I2C_4_SDA : D40
+   - I2C_4_SCL : D41
+
+For more details please refer to `MPS2 Technical Reference Manual (TRM)`_.
+
+System Clock
+============
+
+The V2M MPS2 main clock is 24 MHz.
+
+Serial Port
+===========
+
+The V2M MPS2 processor has five UARTs. Both the UARTs have only two wires for
+RX/TX and no flow control (CTS/RTS) or FIFO. The Zephyr console output, by
+default, is utilizing UART0.
+
+Programming and Debugging
+*************************
+
+Flashing
+========
+
+V2M MPS2 provides:
+
+- A USB connection to the host computer, which exposes a Mass Storage and an
+  USB Serial Port.
+- A Serial Flash device, which implements the USB flash disk file storage.
+- A physical UART connection which is relayed over interface USB Serial port.
+
+Flashing an application to V2M MPS2
+-----------------------------------
+
+Here is an example for the :zephyr:code-sample:`hello_world` application with AN385.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: mps2/an385
+   :goals: build
+
+Connect the V2M MPS2 to your host computer using the USB port and you should
+see a USB connection which exposes a Mass Storage and a USB Serial Port.
+Copy the generated zephyr.bin in the exposed drive.
+Reset the board and you should be able to see on the corresponding Serial Port
+the following message:
+
+.. code-block:: console
+
+   Hello World! arm
+
+Running an applicatoin with FVP
+-------------------------------
+
+Here is the same example for running with FVP.
+Set the ``ARMFVP_BIN_PATH`` environemnt variable to the location of your FVP you have downloaded from `here <FVP_>`_
+
+.. code-block:: console
+
+    export ARMFVP_BIN_PATH=/home/../FVP_MPS2/
+
+Then build with the same command you would use normally, and run with ``west build -t run_armfvp``.
+
+.. _V2M MPS2 Website:
+   https://developer.mbed.org/platforms/ARM-MPS2/
+
+.. _MPS2 Technical Reference Manual (TRM):
+   https://developer.arm.com/documentation/100112/0200/
+
+.. _Application Note AN385:
+   https://documentation-service.arm.com/static/5ed107a5ca06a95ce53f89e3
+
+.. _Application Note AN386:
+   https://documentation-service.arm.com/static/5ed1094dca06a95ce53f8a9f
+
+.. _Application Note AN500:
+   https://documentation-service.arm.com/static/5ed112fcca06a95ce53f8eb3
+
+.. _FVP:
+   https://developer.arm.com/downloads/view/FMFVP
diff --git a/boards/arm/mps2/mps2-pinctrl.dtsi b/boards/arm/mps2/mps2-pinctrl.dtsi
new file mode 100644
index 00000000000..da259040e97
--- /dev/null
+++ b/boards/arm/mps2/mps2-pinctrl.dtsi
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/arm-mps2-pinctrl.h>
+
+&pinctrl {
+	/omit-if-no-ref/  uart3_default: uart3_default {
+		group1 {
+			pinmux = <UART3_TXD_EXP>;
+		};
+
+		group2 {
+			pinmux = <UART3_RXD_EXP>;
+			input-enable;
+		};
+	};
+
+	 /omit-if-no-ref/ uart4_default: uart4_default {
+		 group1 {
+			 pinmux = <UART4_TXD_EXP>;
+		};
+
+		group2 {
+			pinmux = <UART4_RXD_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ spi0_default: spi0_default {
+		group1 {
+			pinmux = <SPI3_SCK_EXP>, <SPI3_SS_EXP>,
+				  <SPI3_MOSI_EXP>;
+		};
+		group2 {
+			pinmux = <SPI3_MISO_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ spi1_default: spi1_default {
+		group1 {
+			pinmux = <SPI4_SCK_EXP>, <SPI4_SS_EXP>,
+				 <SPI4_MOSI_EXP>;
+		};
+		group2 {
+			pinmux = <SPI4_MISO_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ sbcon0_default: sbcon0_default {
+		group1 {
+			pinmux = <SBCON2_SCL_EXP>, <SBCON2_SDA_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ sbcon1_default: sbcon1_default {
+		group1 {
+			pinmux = <SBCON3_SCL_EXP>, <SBCON3_SDA_EXP>;
+			input-enable;
+		};
+	};
+};
diff --git a/boards/arm/mps2/mps2_an383.dts b/boards/arm/mps2/mps2_an383.dts
new file mode 100644
index 00000000000..ef21f37b3f7
--- /dev/null
+++ b/boards/arm/mps2/mps2_an383.dts
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <arm/armv6-m.dtsi>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include "mps2_base.dtsi"
+
+/* FVP does not support uart3 and uart4  */
+/* hence we delete them for AN383 in FVP */
+/delete-node/ &uart3;
+/delete-node/ &uart4;
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m0+";
+			reg = <0>;
+		};
+	};
+};
diff --git a/boards/arm/mps2/mps2_an383.yaml b/boards/arm/mps2/mps2_an383.yaml
new file mode 100644
index 00000000000..24922573775
--- /dev/null
+++ b/boards/arm/mps2/mps2_an383.yaml
@@ -0,0 +1,18 @@
+identifier: mps2/an383
+name: ARM V2M MPS2-an383
+type: mcu
+arch: arm
+simulation:
+  - name: armfvp
+    exec: FVP_MPS2_Cortex-M0plus
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - counter
+  - netif:serial-net
+  - gpio
+  - watchdog
+testing:
+  default: true
+vendor: arm
diff --git a/boards/arm/mps2/mps2_an383_defconfig b/boards/arm/mps2/mps2_an383_defconfig
new file mode 100644
index 00000000000..aaa7c33d63d
--- /dev/null
+++ b/boards/arm/mps2/mps2_an383_defconfig
@@ -0,0 +1,20 @@
+#
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_RUNTIME_NMI=y
+
+# GPIOs
+CONFIG_GPIO=y
+
+# Serial
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+
+CONFIG_ARM_MPU=y
+
+# 0x0 is a valid address, we cannot prevent access to that area
+CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
diff --git a/boards/arm/mps2/mps2_an385.dts b/boards/arm/mps2/mps2_an385.dts
index d2db1cebed0..fd7279d203d 100644
--- a/boards/arm/mps2/mps2_an385.dts
+++ b/boards/arm/mps2/mps2_an385.dts
@@ -1,58 +1,25 @@
-/* SPDX-License-Identifier: Apache-2.0 */
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ */
 
 /dts-v1/;
 
 #include <arm/armv7-m.dtsi>
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
+#include "mps2_base.dtsi"
 
-/ {
-	compatible = "arm,mps2";
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	aliases {
-		led0 = &led_0;
-		led1 = &led_1;
-		sw0 = &user_button_0;
-		sw1 = &user_button_1;
-		watchdog0 = &wdog0;
-	};
-
-	chosen {
-		zephyr,console = &uart0;
-		zephyr,shell-uart = &uart0;
-		zephyr,uart-pipe = &uart1;
-		zephyr,sram = &sram0;
-		zephyr,flash = &flash0;
-	};
+/*
+ * FVP does not support uart3 and uart4 whilst QEMU does.
+ * So if using QEMU, you might want to comment out the following two lines
+ */
 
-	leds {
-		compatible = "gpio-leds";
-		led_0: led_0 {
-			gpios = <&gpio_led0 0>;
-			label = "USERLED0";
-		};
-		led_1: led_1 {
-			gpios = <&gpio_led0 1>;
-			label = "USERLED1";
-		};
-	};
-
-	gpio_keys {
-		compatible = "gpio-keys";
-		user_button_0: button_0 {
-			label = "USERPB0";
-			gpios = <&gpio_button 0>;
-			zephyr,code = <INPUT_KEY_0>;
-		};
-		user_button_1: button_1 {
-			label = "USERPB1";
-			gpios = <&gpio_button 1>;
-			zephyr,code = <INPUT_KEY_1>;
-		};
-	};
+/delete-node/ &uart3;
+/delete-node/ &uart4;
 
+/ {
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -62,223 +29,4 @@
 			reg = <0>;
 		};
 	};
-
-	sram0: memory@20000000 {
-		compatible = "mmio-sram";
-		reg = <0x20000000 0x400000>;
-	};
-
-	flash0: flash@0 {
-		compatible = "soc-nv-flash";
-		reg = <0 0x400000>;
-	};
-
-	sim_flash_controller: sim_flash_controller {
-		compatible = "zephyr,sim-flash";
-
-		#address-cells = <1>;
-		#size-cells = <1>;
-		erase-value = <0x00>;
-
-		flash_sim0: flash_sim@0 {
-			compatible = "soc-nv-flash";
-			reg = <0x00000000 0x8000>;
-
-			erase-block-size = <1024>;
-			write-block-size = <4>;
-
-			partitions {
-				compatible = "fixed-partitions";
-				#address-cells = <1>;
-				#size-cells = <1>;
-
-				storage_partition: partition@0 {
-					label = "storage_partition";
-					reg = <0x00000000 0x8000>;
-				};
-			};
-		};
-	};
-
-	sysclk: system-clock {
-		compatible = "fixed-clock";
-		clock-frequency = <25000000>;
-		#clock-cells = <0>;
-	};
-
-	soc {
-		timer0: timer@40000000 {
-			compatible = "arm,cmsdk-timer";
-			reg = <0x40000000 0x1000>;
-			interrupts = <8 3>;
-		};
-
-		timer1: timer@40001000 {
-			compatible = "arm,cmsdk-timer";
-			reg = <0x40001000 0x1000>;
-			interrupts = <9 3>;
-		};
-
-		dtimer0: dtimer@40002000 {
-			compatible = "arm,cmsdk-dtimer";
-			reg = <0x40002000 0x1000>;
-			interrupts = <10 3>;
-		};
-
-		uart0: uart@40004000 {
-			compatible = "arm,cmsdk-uart";
-			reg = <0x40004000 0x1000>;
-			interrupts = <1 3 0 3>;
-			interrupt-names = "tx", "rx";
-			clocks = <&sysclk>;
-			current-speed = <115200>;
-		};
-
-		uart1: uart@40005000 {
-			compatible = "arm,cmsdk-uart";
-			reg = <0x40005000 0x1000>;
-			interrupts = <3 3 2 3>;
-			interrupt-names = "tx", "rx";
-			clocks = <&sysclk>;
-			current-speed = <115200>;
-		};
-
-		uart2: uart@40006000 {
-			compatible = "arm,cmsdk-uart";
-			reg = <0x40006000 0x1000>;
-			interrupts = <5 3 4 3>;
-			interrupt-names = "tx", "rx";
-			clocks = <&sysclk>;
-			current-speed = <115200>;
-		};
-
-		uart3: uart@40007000 {
-			compatible = "arm,cmsdk-uart";
-			reg = <0x40007000 0x1000>;
-			interrupts = <19 3 18 3>;
-			interrupt-names = "tx", "rx";
-			clocks = <&sysclk>;
-			current-speed = <115200>;
-		};
-
-		wdog0: wdog@40008000 {
-			compatible = "arm,cmsdk-watchdog";
-			clocks = <&sysclk>;
-			reg = <0x40008000 0x1000>;
-		};
-
-		uart4: uart@40009000 {
-			compatible = "arm,cmsdk-uart";
-			reg = <0x40009000 0x1000>;
-			interrupts = <21 3 20 3>;
-			interrupt-names = "tx", "rx";
-			clocks = <&sysclk>;
-			current-speed = <115200>;
-		};
-
-		gpio0: gpio@40010000 {
-			compatible = "arm,cmsdk-gpio";
-			reg = <0x40010000 0x1000>;
-			interrupts = <6 3>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		gpio1: gpio@40011000 {
-			compatible = "arm,cmsdk-gpio";
-			reg = <0x40011000 0x1000>;
-			interrupts = <7 3>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		gpio2: gpio@40012000 {
-			compatible = "arm,cmsdk-gpio";
-			reg = <0x40012000 0x1000>;
-			interrupts = <16 3>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		gpio3: gpio@40013000 {
-			compatible = "arm,cmsdk-gpio";
-			reg = <0x40013000 0x1000>;
-			interrupts = <17 3>;
-			gpio-controller;
-			#gpio-cells = <2>;
-		};
-
-		eth0: eth@40200000 {
-			/* Linux has "smsc,lan9115" */
-			compatible = "smsc,lan9220";
-			/* Such a big size from memory map in AN385 */
-			/* Actual reg range is ~0x200 */
-			reg = <0x40200000 0x100000>;
-			interrupts = <13 3>;
-		};
-
-		i2c_touch: i2c@40022000 {
-			compatible = "arm,versatile-i2c";
-			clock-frequency = <I2C_BITRATE_STANDARD>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x40022000 0x1000>;
-		};
-
-		i2c_audio_conf: i2c@40023000 {
-			compatible = "arm,versatile-i2c";
-			clock-frequency = <I2C_BITRATE_STANDARD>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x40023000 0x1000>;
-		};
-
-		i2c_shield0: i2c@40029000 {
-			compatible = "arm,versatile-i2c";
-			clock-frequency = <I2C_BITRATE_STANDARD>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x40029000 0x1000>;
-		};
-
-		i2c_shield1: i2c@4002a000 {
-			compatible = "arm,versatile-i2c";
-			clock-frequency = <I2C_BITRATE_STANDARD>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x4002a000 0x1000>;
-		};
-
-		gpio_led0: mps2_fpgaio@40028000 {
-			compatible = "arm,mps2-fpgaio-gpio";
-
-			reg = <0x40028000 0x4>;
-			gpio-controller;
-			#gpio-cells = <1>;
-			ngpios = <2>;
-		};
-
-		gpio_button: mps2_fpgaio@40028008 {
-			compatible = "arm,mps2-fpgaio-gpio";
-
-			reg = <0x40028008 0x4>;
-			gpio-controller;
-			#gpio-cells = <1>;
-			ngpios = <2>;
-		};
-
-		gpio_misc: mps2_fpgaio@4002804c {
-			compatible = "arm,mps2-fpgaio-gpio";
-
-			reg = <0x4002804c 0x4>;
-			gpio-controller;
-			#gpio-cells = <1>;
-			ngpios = <10>;
-		};
-
-	};
-};
-
-&nvic {
-	arm,num-irq-priority-bits = <3>;
 };
diff --git a/boards/arm/mps2/mps2_an385.yaml b/boards/arm/mps2/mps2_an385.yaml
index bbd929892c5..ca7d2443c93 100644
--- a/boards/arm/mps2/mps2_an385.yaml
+++ b/boards/arm/mps2/mps2_an385.yaml
@@ -4,10 +4,11 @@ type: mcu
 arch: arm
 simulation:
   - name: qemu
+  - name: armfvp
+    exec: FVP_MPS2_Cortex-M3
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - netif:serial-net
@@ -16,3 +17,5 @@ supported:
 testing:
   default: true
 vendor: arm
+ram: 4096
+flash: 4096
diff --git a/boards/arm/mps2/mps2_an386.dts b/boards/arm/mps2/mps2_an386.dts
new file mode 100644
index 00000000000..44aacd6cbc1
--- /dev/null
+++ b/boards/arm/mps2/mps2_an386.dts
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <arm/armv7-m.dtsi>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include "mps2_base.dtsi"
+
+/* FVP does not support uart3 and uart4  */
+/* hence we delete them for AN386 in FVP */
+/delete-node/ &uart3;
+/delete-node/ &uart4;
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+};
diff --git a/boards/arm/mps2/mps2_an386.yaml b/boards/arm/mps2/mps2_an386.yaml
new file mode 100644
index 00000000000..f71e166e683
--- /dev/null
+++ b/boards/arm/mps2/mps2_an386.yaml
@@ -0,0 +1,19 @@
+identifier: mps2/an386
+name: ARM V2M MPS2-an386
+type: mcu
+arch: arm
+simulation:
+  - name: armfvp
+    exec: FVP_MPS2_Cortex-M4
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - counter
+  - gpio
+  - watchdog
+testing:
+  default: true
+  ignore_tags:
+    - net
+vendor: arm
diff --git a/boards/arm/mps2/mps2_an386_defconfig b/boards/arm/mps2/mps2_an386_defconfig
new file mode 100644
index 00000000000..723288edb52
--- /dev/null
+++ b/boards/arm/mps2/mps2_an386_defconfig
@@ -0,0 +1,15 @@
+#
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_RUNTIME_NMI=y
+
+# GPIOs
+CONFIG_GPIO=y
+
+# Serial
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
diff --git a/boards/arm/mps2/mps2_an500.dts b/boards/arm/mps2/mps2_an500.dts
new file mode 100644
index 00000000000..6cd48be45fc
--- /dev/null
+++ b/boards/arm/mps2/mps2_an500.dts
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+/* Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com> */
+/dts-v1/;
+
+#include <arm/armv7-m.dtsi>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include "mps2_base.dtsi"
+
+/* FVP does not support uart3 and uart4  */
+/* hence we delete them for AN500 in FVP */
+/delete-node/ &uart3;
+/delete-node/ &uart4;
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			compatible = "arm,cortex-m7";
+			reg = <0>;
+		};
+	};
+};
diff --git a/boards/arm/mps2/mps2_an500.yaml b/boards/arm/mps2/mps2_an500.yaml
new file mode 100644
index 00000000000..cc4c713d799
--- /dev/null
+++ b/boards/arm/mps2/mps2_an500.yaml
@@ -0,0 +1,19 @@
+identifier: mps2/an500
+name: ARM V2M MPS2-an500
+type: mcu
+arch: arm
+simulation:
+  - name: armfvp
+    exec: FVP_MPS2_Cortex-M7
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - counter
+  - gpio
+  - watchdog
+testing:
+  default: true
+  ignore_tags:
+    - net
+vendor: arm
diff --git a/boards/arm/mps2/mps2_an500_defconfig b/boards/arm/mps2/mps2_an500_defconfig
new file mode 100644
index 00000000000..723288edb52
--- /dev/null
+++ b/boards/arm/mps2/mps2_an500_defconfig
@@ -0,0 +1,15 @@
+#
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_RUNTIME_NMI=y
+
+# GPIOs
+CONFIG_GPIO=y
+
+# Serial
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
diff --git a/boards/arm/mps2/mps2_an521-common.dtsi b/boards/arm/mps2/mps2_an521-common.dtsi
index 5b1959ff5fe..b96f1144982 100644
--- a/boards/arm/mps2/mps2_an521-common.dtsi
+++ b/boards/arm/mps2/mps2_an521-common.dtsi
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2019 Linaro Limited
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -112,6 +113,8 @@ uart3: uart@203000 {
 	interrupt-names = "tx", "rx";
 	clocks = <&sysclk>;
 	current-speed = <115200>;
+	pinctrl-0 = <&uart3_default>;
+	pinctrl-names = "default";
 };
 
 uart4: uart@204000 {
@@ -121,6 +124,8 @@ uart4: uart@204000 {
 	interrupt-names = "tx", "rx";
 	clocks = <&sysclk>;
 	current-speed = <115200>;
+	pinctrl-0 = <&uart4_default>;
+	pinctrl-names = "default";
 };
 
 i2c_touch: i2c@207000 {
@@ -145,6 +150,8 @@ i2c_shield0: i2c@20c000 {
 	#address-cells = <1>;
 	#size-cells = <0>;
 	reg = <0x20c000 0x1000>;
+	pinctrl-0 = <&sbcon0_default>;
+	pinctrl-names = "default";
 };
 
 i2c_shield1: i2c@20d000 {
@@ -153,10 +160,12 @@ i2c_shield1: i2c@20d000 {
 	#address-cells = <1>;
 	#size-cells = <0>;
 	reg = <0x20d000 0x1000>;
+	pinctrl-0 = <&sbcon1_default>;
+	pinctrl-names = "default";
 };
 
 gpio_led0: mps2_fpgaio@302000 {
-	compatible = "arm,mps2-fpgaio-gpio";
+	compatible = "arm,mmio32-gpio";
 
 	reg = <0x302000 0x4>;
 	gpio-controller;
@@ -165,16 +174,17 @@ gpio_led0: mps2_fpgaio@302000 {
 };
 
 gpio_button: mps2_fpgaio@302008 {
-	compatible = "arm,mps2-fpgaio-gpio";
+	compatible = "arm,mmio32-gpio";
 
 	reg = <0x302008 0x4>;
 	gpio-controller;
 	#gpio-cells = <1>;
 	ngpios = <2>;
+	direction-input;
 };
 
 gpio_misc: mps2_fpgaio@30204c {
-	compatible = "arm,mps2-fpgaio-gpio";
+	compatible = "arm,mmio32-gpio";
 
 	reg = <0x30204c 0x4>;
 	gpio-controller;
@@ -189,3 +199,8 @@ eth0: eth@2000000 {
 	reg = <0x2000000 0x100000>;
 	interrupts = <48 3>;
 };
+
+pinctrl: pinctrl {
+	compatible = "arm,mps2-pinctrl";
+	status = "okay";
+};
diff --git a/boards/arm/mps2/mps2_an521_cpu0.dts b/boards/arm/mps2/mps2_an521_cpu0.dts
index 2bb956645ca..532384377da 100644
--- a/boards/arm/mps2/mps2_an521_cpu0.dts
+++ b/boards/arm/mps2/mps2_an521_cpu0.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018-2019 Linaro Limited
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -128,3 +129,5 @@
 &uart1 {
 	status = "okay";
 };
+
+#include "mps2-pinctrl.dtsi"
diff --git a/boards/arm/mps2/mps2_an521_cpu0.yaml b/boards/arm/mps2/mps2_an521_cpu0.yaml
index 68210b954b4..e511285c190 100644
--- a/boards/arm/mps2/mps2_an521_cpu0.yaml
+++ b/boards/arm/mps2/mps2_an521_cpu0.yaml
@@ -10,13 +10,11 @@ simulation:
 toolchain:
   - gnuarmemb
   - zephyr
-  - xtools
 supported:
   - gpio
 testing:
   default: true
   ignore_tags:
-    - drivers
     - bluetooth
     - net
     - timer
diff --git a/boards/arm/mps2/mps2_an521_cpu0_ns.dts b/boards/arm/mps2/mps2_an521_cpu0_ns.dts
index e2b24cd9ba5..d67718fcc59 100644
--- a/boards/arm/mps2/mps2_an521_cpu0_ns.dts
+++ b/boards/arm/mps2/mps2_an521_cpu0_ns.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018-2019 Linaro Limited
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -142,3 +143,4 @@
 &nvic {
 	arm,num-irq-priority-bits = <3>;
 };
+#include "mps2-pinctrl.dtsi"
diff --git a/boards/arm/mps2/mps2_an521_cpu0_ns.yaml b/boards/arm/mps2/mps2_an521_cpu0_ns.yaml
index c4a589c9396..8f0a61596ca 100644
--- a/boards/arm/mps2/mps2_an521_cpu0_ns.yaml
+++ b/boards/arm/mps2/mps2_an521_cpu0_ns.yaml
@@ -10,7 +10,6 @@ simulation:
 toolchain:
   - gnuarmemb
   - zephyr
-  - xtools
 testing:
   default: true
   only_tags:
diff --git a/boards/arm/mps2/mps2_an521_cpu1.dts b/boards/arm/mps2/mps2_an521_cpu1.dts
index 311694ca399..24b39b50978 100644
--- a/boards/arm/mps2/mps2_an521_cpu1.dts
+++ b/boards/arm/mps2/mps2_an521_cpu1.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018-2019 Linaro Limited
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -144,3 +145,5 @@
 &nvic {
 	arm,num-irq-priority-bits = <3>;
 };
+
+#include "mps2-pinctrl.dtsi"
diff --git a/boards/arm/mps2/mps2_an521_cpu1.yaml b/boards/arm/mps2/mps2_an521_cpu1.yaml
index 3880d479d6e..5264acb61f4 100644
--- a/boards/arm/mps2/mps2_an521_cpu1.yaml
+++ b/boards/arm/mps2/mps2_an521_cpu1.yaml
@@ -10,7 +10,6 @@ simulation:
 toolchain:
   - gnuarmemb
   - zephyr
-  - xtools
 testing:
   default: true
   only_tags:
diff --git a/boards/arm/mps2/mps2_base.dtsi b/boards/arm/mps2/mps2_base.dtsi
new file mode 100644
index 00000000000..021373fac43
--- /dev/null
+++ b/boards/arm/mps2/mps2_base.dtsi
@@ -0,0 +1,282 @@
+/* Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com> */
+/* SPDX-License-Identifier: Apache-2.0 */
+
+/ {
+	compatible = "arm,mps2";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	aliases {
+		led0 = &led_0;
+		led1 = &led_1;
+		sw0 = &user_button_0;
+		sw1 = &user_button_1;
+		watchdog0 = &wdog0;
+	};
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,uart-pipe = &uart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,flash-controller = &sim_flash_controller;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		led_0: led_0 {
+			gpios = <&gpio_led0 0>;
+			label = "USERLED0";
+		};
+
+		led_1: led_1 {
+			gpios = <&gpio_led0 1>;
+			label = "USERLED1";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button_0: button_0 {
+			label = "USERPB0";
+			gpios = <&gpio_button 0>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		user_button_1: button_1 {
+			label = "USERPB1";
+			gpios = <&gpio_button 1>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+		reg = <0x20000000 0x400000>;
+	};
+
+	flash0: flash@0 {
+		compatible = "soc-nv-flash";
+		reg = <0 0x400000>;
+	};
+
+	sim_flash_controller: sim_flash_controller {
+		compatible = "zephyr,sim-flash";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		erase-value = <0x00>;
+
+		flash_sim0: flash_sim@0 {
+			compatible = "soc-nv-flash";
+			reg = <0x00000000 0x8000>;
+			erase-block-size = <1024>;
+			write-block-size = <4>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				storage_partition: partition@0 {
+					label = "storage_partition";
+					reg = <0x00000000 0x8000>;
+				};
+			};
+		};
+	};
+
+	sysclk: system-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <25000000>;
+		#clock-cells = <0>;
+	};
+
+	soc {
+		timer0: timer@40000000 {
+			compatible = "arm,cmsdk-timer";
+			reg = <0x40000000 0x1000>;
+			interrupts = <8 3>;
+		};
+
+		timer1: timer@40001000 {
+			compatible = "arm,cmsdk-timer";
+			reg = <0x40001000 0x1000>;
+			interrupts = <9 3>;
+		};
+
+		dtimer0: dtimer@40002000 {
+			compatible = "arm,cmsdk-dtimer";
+			reg = <0x40002000 0x1000>;
+			interrupts = <10 3>;
+		};
+
+		uart0: uart@40004000 {
+			compatible = "arm,cmsdk-uart";
+			reg = <0x40004000 0x1000>;
+			interrupts = <1 3 0 3>;
+			interrupt-names = "tx", "rx";
+			clocks = <&sysclk>;
+			current-speed = <115200>;
+		};
+
+		uart1: uart@40005000 {
+			compatible = "arm,cmsdk-uart";
+			reg = <0x40005000 0x1000>;
+			interrupts = <3 3 2 3>;
+			interrupt-names = "tx", "rx";
+			clocks = <&sysclk>;
+			current-speed = <115200>;
+		};
+
+		uart2: uart@40006000 {
+			compatible = "arm,cmsdk-uart";
+			reg = <0x40006000 0x1000>;
+			interrupts = <5 3 4 3>;
+			interrupt-names = "tx", "rx";
+			clocks = <&sysclk>;
+			current-speed = <115200>;
+		};
+
+		uart3: uart@40007000 {
+			compatible = "arm,cmsdk-uart";
+			reg = <0x40007000 0x1000>;
+			interrupts = <19 3 18 3>;
+			interrupt-names = "tx", "rx";
+			clocks = <&sysclk>;
+			current-speed = <115200>;
+			pinctrl-0 = <&uart3_default>;
+			pinctrl-names = "default";
+		};
+
+		wdog0: wdog@40008000 {
+			compatible = "arm,cmsdk-watchdog";
+			clocks = <&sysclk>;
+			reg = <0x40008000 0x1000>;
+		};
+
+		uart4: uart@40009000 {
+			compatible = "arm,cmsdk-uart";
+			reg = <0x40009000 0x1000>;
+			interrupts = <21 3 20 3>;
+			interrupt-names = "tx", "rx";
+			clocks = <&sysclk>;
+			current-speed = <115200>;
+			pinctrl-0 = <&uart4_default>;
+			pinctrl-names = "default";
+		};
+
+		gpio0: gpio@40010000 {
+			compatible = "arm,cmsdk-gpio";
+			reg = <0x40010000 0x1000>;
+			interrupts = <6 3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio1: gpio@40011000 {
+			compatible = "arm,cmsdk-gpio";
+			reg = <0x40011000 0x1000>;
+			interrupts = <7 3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio2: gpio@40012000 {
+			compatible = "arm,cmsdk-gpio";
+			reg = <0x40012000 0x1000>;
+			interrupts = <16 3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		gpio3: gpio@40013000 {
+			compatible = "arm,cmsdk-gpio";
+			reg = <0x40013000 0x1000>;
+			interrupts = <17 3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+		};
+
+		eth0: eth@40200000 {
+			/* Linux has "smsc,lan9115" */
+			compatible = "smsc,lan9220";
+			/* Such a big size from memory map in AN385 */
+			/* Actual reg range is ~0x200 */
+			reg = <0x40200000 0x100000>;
+			interrupts = <13 3>;
+		};
+
+		i2c_touch: i2c@40022000 {
+			compatible = "arm,versatile-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40022000 0x1000>;
+		};
+
+		i2c_audio_conf: i2c@40023000 {
+			compatible = "arm,versatile-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40023000 0x1000>;
+		};
+
+		i2c_shield0: i2c@40029000 {
+			compatible = "arm,versatile-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40029000 0x1000>;
+			pinctrl-0 = <&sbcon0_default>;
+			pinctrl-names = "default";
+		};
+
+		i2c_shield1: i2c@4002a000 {
+			compatible = "arm,versatile-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x4002a000 0x1000>;
+			pinctrl-0 = <&sbcon1_default>;
+			pinctrl-names = "default";
+		};
+
+		gpio_led0: mps2_fpgaio@40028000 {
+			compatible = "arm,mmio32-gpio";
+			reg = <0x40028000 0x4>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			ngpios = <2>;
+		};
+
+		gpio_button: mps2_fpgaio@40028008 {
+			compatible = "arm,mmio32-gpio";
+			reg = <0x40028008 0x4>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			ngpios = <2>;
+			direction-input;
+		};
+
+		gpio_misc: mps2_fpgaio@4002804c {
+			compatible = "arm,mmio32-gpio";
+			reg = <0x4002804c 0x4>;
+			gpio-controller;
+			#gpio-cells = <1>;
+			ngpios = <10>;
+		};
+	};
+
+	pinctrl: pinctrl {
+		compatible = "arm,mps2-pinctrl";
+		status = "okay";
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};
+
+#include "mps2-pinctrl.dtsi"
diff --git a/boards/arm/mps2/pinmux.c b/boards/arm/mps2/pinmux.c
deleted file mode 100644
index 6cf93983072..00000000000
--- a/boards/arm/mps2/pinmux.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Copyright (c) 2016 Linaro Limited
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/device.h>
-#include <zephyr/init.h>
-#include <zephyr/kernel.h>
-#include <soc.h>
-#include <zephyr/sys/sys_io.h>
-#include <zephyr/drivers/gpio/gpio_cmsdk_ahb.h>
-
-/**
- * @brief Pinmux driver for ARM MPS2 AN385 Board
- *
- * The ARM MPS2 AN385 Board has 4 GPIO controllers. These controllers
- * are responsible for pin muxing, input/output, pull-up, etc.
- *
- * All GPIO controller pins are exposed via the following sequence of pin
- * numbers:
- *   Pins  0 -  15 are for GPIO0
- *   Pins 16 -  31 are for GPIO1
- *   Pins 32 -  47 are for GPIO2
- *   Pins 48 -  51 are for GPIO3
- *
- * For the GPIO controllers configuration ARM MPS2 AN385 Board follows the
- * Arduino compliant pin out.
- */
-
-#define CMSDK_AHB_GPIO0_DEV \
-	((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio0)))
-#define CMSDK_AHB_GPIO1_DEV \
-	((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio1)))
-#define CMSDK_AHB_GPIO2_DEV \
-	((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio2)))
-#define CMSDK_AHB_GPIO3_DEV \
-	((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio3)))
-
-/*
- * This is the mapping from the ARM MPS2 AN385 Board pins to GPIO
- * controllers.
- *
- * D0 : EXT_0
- * D1 : EXT_4
- * D2 : EXT_2
- * D3 : EXT_3
- * D4 : EXT_1
- * D5 : EXT_6
- * D6 : EXT_7
- * D7 : EXT_8
- * D8 : EXT_9
- * D9 : EXT_10
- * D10 : EXT_12
- * D11 : EXT_13
- * D12 : EXT_14
- * D13 : EXT_11
- * D14 : EXT_15
- * D15 : EXT_5
- * D16 : EXT_16
- * D17 : EXT_17
- * D18 : EXT_18
- * D19 : EXT_19
- * D20 : EXT_20
- * D21 : EXT_21
- * D22 : EXT_22
- * D23 : EXT_23
- * D24 : EXT_24
- * D25 : EXT_25
- * D26 : EXT_26
- * D27 : EXT_30
- * D28 : EXT_28
- * D29 : EXT_29
- * D30 : EXT_27
- * D31 : EXT_32
- * D32 : EXT_33
- * D33 : EXT_34
- * D34 : EXT_35
- * D35 : EXT_36
- * D36 : EXT_38
- * D37 : EXT_39
- * D38 : EXT_40
- * D39 : EXT_44
- * D40 : EXT_41
- * D41 : EXT_31
- * D42 : EXT_37
- * D43 : EXT_42
- * D44 : EXT_43
- * D45 : EXT_45
- * D46 : EXT_46
- * D47 : EXT_47
- * D48 : EXT_48
- * D49 : EXT_49
- * D50 : EXT_50
- * D51 : EXT_51
- *
- * UART_3_RX : D0
- * UART_3_TX : D1
- * SPI_3_CS : D10
- * SPI_3_MOSI : D11
- * SPI_3_MISO : D12
- * SPI_3_SCLK : D13
- * I2C_3_SDA : D14
- * I2C_3_SCL : D15
- * UART_4_RX : D26
- * UART_4_TX : D30
- * SPI_4_CS : D36
- * SPI_4_MOSI : D37
- * SPI_4_MISO : D38
- * SPI_4_SCK : D39
- * I2C_4_SDA : D40
- * I2C_4_SCL : D41
- *
- */
-static void arm_mps2_pinmux_defaults(void)
-{
-	uint32_t gpio_0 = 0U;
-	uint32_t gpio_1 = 0U;
-	uint32_t gpio_2 = 0U;
-
-	/* Set GPIO Alternate Functions */
-
-	gpio_0 = (1<<0)   /* Shield 0 UART 3 RXD */
-	       | (1<<4)   /* Shield 0 UART 3 TXD */
-	       | (1<<5)   /* Shield 0 I2C SCL SBCON2 */
-	       | (1<<15)  /* Shield 0 I2C SDA SBCON2 */
-	       | (1<<11)  /* Shield 0 SPI 3 SCK */
-	       | (1<<12)  /* Shield 0 SPI 3 SS */
-	       | (1<<13)  /* Shield 0 SPI 3 MOSI */
-	       | (1<<14); /* Shield 0 SPI 3 MISO */
-
-	CMSDK_AHB_GPIO0_DEV->altfuncset = gpio_0;
-
-	gpio_1 = (1<<10) /* Shield 1 UART 4 RXD */
-	       | (1<<14) /* Shield 1 UART 4 TXD */
-	       | (1<<15) /* Shield 1 I2C SCL SBCON3 */
-	       | (1<<0)  /* ADC SPI 2 SS */
-	       | (1<<1)  /* ADC SPI 2 MISO */
-	       | (1<<2)  /* ADC SPI 2 MOSI */
-	       | (1<<3)  /* ADC SPI 2 SCK */
-	       | (1<<5)  /* USER BUTTON 0 */
-	       | (1<<6); /* USER BUTTON 1 */
-
-	CMSDK_AHB_GPIO1_DEV->altfuncset = gpio_1;
-
-	gpio_2 = (1<<9)   /* Shield 1 I2C SDA SBCON3 */
-	       | (1<<6)   /* Shield 1 SPI 4 SS */
-	       | (1<<7)   /* Shield 1 SPI 4 MOSI */
-	       | (1<<8)   /* Shield 1 SPI 4 MISO */
-	       | (1<<12); /* Shield 1 SPI 4 SCK */
-
-	CMSDK_AHB_GPIO2_DEV->altfuncset = gpio_2;
-}
-
-static int arm_mps2_pinmux_init(void)
-{
-
-	arm_mps2_pinmux_defaults();
-
-	return 0;
-}
-
-SYS_INIT(arm_mps2_pinmux_init, PRE_KERNEL_1,
-	 CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/boards/arm/mps3/Kconfig.defconfig b/boards/arm/mps3/Kconfig.defconfig
index 4ce6cf0c910..014b80f307f 100644
--- a/boards/arm/mps3/Kconfig.defconfig
+++ b/boards/arm/mps3/Kconfig.defconfig
@@ -1,5 +1,5 @@
 # Copyright (c) 2018-2021 Linaro Limited
-# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 if BOARD_MPS3_CORSTONE300_AN547 || BOARD_MPS3_CORSTONE300_AN552 || BOARD_MPS3_CORSTONE300_FVP || BOARD_MPS3_CORSTONE310_AN555 || BOARD_MPS3_CORSTONE310_FVP
@@ -19,4 +19,14 @@ config UART_INTERRUPT_DRIVEN
 
 endif # SERIAL
 
+if ROMSTART_RELOCATION_ROM && (BOARD_MPS3_CORSTONE310_AN555 || BOARD_MPS3_CORSTONE310_FVP)
+
+config ROMSTART_REGION_ADDRESS
+	default $(dt_nodelabel_reg_addr_hex,itcm)
+
+config ROMSTART_REGION_SIZE
+	default $(dt_nodelabel_reg_size_hex,itcm,0,k)
+
+endif
+
 endif
diff --git a/boards/arm/mps3/board.cmake b/boards/arm/mps3/board.cmake
index ca090a832fc..e6204c4c2ea 100644
--- a/boards/arm/mps3/board.cmake
+++ b/boards/arm/mps3/board.cmake
@@ -1,5 +1,5 @@
 # Copyright (c) 2021 Linaro
-# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 # The FVP variant must be used to enable Ethos-U55 NPU support, but QEMU also
@@ -37,6 +37,10 @@ elseif(CONFIG_BOARD_MPS3_CORSTONE310_FVP OR CONFIG_BOARD_MPS3_CORSTONE310_FVP_NS
     set(ARMFVP_FLAGS
       # default is '0x11000000' but should match cpu<i>.INITSVTOR which is 0.
       -C mps3_board.sse300.iotss3_systemcontrol.INITSVTOR_RST=0
+      # default is 0x8, this change is needed since we split flash into itcm
+      # and sram and it reduces the number of available mpu regions causing a
+      # few MPU tests to fail.
+      -C cpu0.MPU_S=16
     )
   endif()
 endif()
@@ -48,6 +52,8 @@ if (CONFIG_BUILD_WITH_TFM)
   # TF-M (Secure) & Zephyr (Non Secure) image (when running
   # in-tree tests).
   set(QEMU_KERNEL_OPTION "-device;loader,file=${CMAKE_BINARY_DIR}/zephyr/tfm_merged.hex")
+
+  set(ARMFVP_FLAGS ${ARMFVP_FLAGS} -a ${APPLICATION_BINARY_DIR}/zephyr/tfm_merged.hex)
 endif()
 
 # FVP Parameters
diff --git a/boards/arm/mps3/mps3-pinctrl.dtsi b/boards/arm/mps3/mps3-pinctrl.dtsi
new file mode 100644
index 00000000000..17b143ae644
--- /dev/null
+++ b/boards/arm/mps3/mps3-pinctrl.dtsi
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/arm-mps3-pinctrl.h>
+
+&pinctrl {
+	/omit-if-no-ref/  uart3_default: uart3_default {
+		group1 {
+			pinmux = <UART3_TXD_EXP>;
+		};
+
+		group2 {
+			pinmux = <UART3_RXD_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ uart4_default: uart4_default {
+		group1 {
+			pinmux = <UART4_TXD_EXP>;
+		};
+
+		group2 {
+			pinmux = <UART4_RXD_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ spi3_default: spi3_default {
+		group1 {
+			pinmux = <SPI3_SS_EXP>, <SPI3_MOSI_EXP>,
+				 <SPI3_SCK_EXP>;
+		};
+
+		group2 {
+			pinmux = <SPI3_MISO_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ spi4_default: spi4_default {
+		group1 {
+			pinmux = <SPI4_SS_EXP>, <SPI4_MOSI_EXP>, <SPI4_SCK_EXP>;
+		};
+
+		group2 {
+			pinmux = <SPI4_MISO_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ sbcon2_default: sbcon2_default {
+		group1 {
+			pinmux = <SBCON2_SDA_EXP>, <SBCON2_SCL_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ sbcon3_default: sbcon3_default {
+		group1 {
+			pinmux = <SBCON3_SDA_EXP>, <SBCON3_SCL_EXP>;
+			input-enable;
+		};
+	};
+};
diff --git a/boards/arm/mps3/mps3_common.dtsi b/boards/arm/mps3/mps3_common.dtsi
index 798af263310..3348101bc72 100644
--- a/boards/arm/mps3/mps3_common.dtsi
+++ b/boards/arm/mps3/mps3_common.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ * Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -104,3 +104,4 @@
 &nvic {
 	arm,num-irq-priority-bits = <3>;
 };
+#include "mps3-pinctrl.dtsi"
diff --git a/boards/arm/mps3/mps3_common_soc_peripheral.dtsi b/boards/arm/mps3/mps3_common_soc_peripheral.dtsi
index 6fd5c7acd40..d46f6c602cf 100644
--- a/boards/arm/mps3/mps3_common_soc_peripheral.dtsi
+++ b/boards/arm/mps3/mps3_common_soc_peripheral.dtsi
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2019-2021 Linaro Limited
- * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ * Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -85,6 +85,8 @@ spi_shield0: spi@9203000 {
 	clocks = <&sysclk>;
 	#address-cells = <1>;
 	#size-cells = <0>;
+	pinctrl-0 = <&spi3_default>;
+	pinctrl-names = "default";
 };
 
 spi_shield1: spi@9204000 {
@@ -95,6 +97,8 @@ spi_shield1: spi@9204000 {
 	clocks = <&sysclk>;
 	#address-cells = <1>;
 	#size-cells = <0>;
+	pinctrl-0 = <&spi4_default>;
+	pinctrl-names = "default";
 };
 
 i2c_shield0: i2c@9205000 {
@@ -103,6 +107,8 @@ i2c_shield0: i2c@9205000 {
 	#address-cells = <1>;
 	#size-cells = <0>;
 	reg = <0x9205000 0x1000>;
+	pinctrl-0 = <&sbcon2_default>;
+	pinctrl-names = "default";
 };
 
 i2c_shield1: i2c@9206000 {
@@ -111,6 +117,8 @@ i2c_shield1: i2c@9206000 {
 	#address-cells = <1>;
 	#size-cells = <0>;
 	reg = <0x9206000 0x1000>;
+	pinctrl-0 = <&sbcon3_default>;
+	pinctrl-names = "default";
 };
 
 i2c_ddr4_eeprom: i2c@9208000 {
@@ -122,7 +130,7 @@ i2c_ddr4_eeprom: i2c@9208000 {
 };
 
 gpio_led0: mps3_fpgaio@9302000 {
-	compatible = "arm,mps3-fpgaio-gpio";
+	compatible = "arm,mmio32-gpio";
 
 	reg = <0x9302000 0x4>;
 	gpio-controller;
@@ -131,16 +139,17 @@ gpio_led0: mps3_fpgaio@9302000 {
 };
 
 gpio_button: mps3_fpgaio@9302008 {
-	compatible = "arm,mps3-fpgaio-gpio";
+	compatible = "arm,mmio32-gpio";
 
 	reg = <0x9302008 0x4>;
 	gpio-controller;
 	#gpio-cells = <1>;
 	ngpios = <2>;
+	direction-input;
 };
 
 gpio_misc: mps3_fpgaio@930204c {
-	compatible = "arm,mps3-fpgaio-gpio";
+	compatible = "arm,mmio32-gpio";
 
 	reg = <0x930204c 0x4>;
 	gpio-controller;
@@ -182,6 +191,8 @@ uart3: uart@9306000 {
 	interrupt-names = "tx", "rx";
 	clocks = <&sysclk>;
 	current-speed = <115200>;
+	pinctrl-0 = <&uart3_default>;
+	pinctrl-names = "default";
 };
 
 uart4: uart@9307000 {
@@ -191,6 +202,8 @@ uart4: uart@9307000 {
 	interrupt-names = "tx", "rx";
 	clocks = <&sysclk>;
 	current-speed = <115200>;
+	pinctrl-0 = <&uart4_default>;
+	pinctrl-names = "default";
 };
 
 uart5: uart@9308000 {
@@ -202,3 +215,8 @@ uart5: uart@9308000 {
 	clocks = <&sysclk>;
 	current-speed = <115200>;
 };
+
+pinctrl: pinctrl {
+	compatible = "arm,mps3-pinctrl";
+	status = "okay";
+};
diff --git a/boards/arm/mps3/mps3_corstone300_an547.dts b/boards/arm/mps3/mps3_corstone300_an547.dts
index ae71ddf7282..55188180f0c 100644
--- a/boards/arm/mps3/mps3_corstone300_an547.dts
+++ b/boards/arm/mps3/mps3_corstone300_an547.dts
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018-2021 Linaro Limited
- * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ * Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,7 +11,6 @@
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <mem.h>
-#include "mps3_common.dtsi"
 
 / {
 	compatible = "arm,mps3-an547";
@@ -95,3 +94,4 @@
 		};
 	};
 };
+#include "mps3_common.dtsi"
diff --git a/boards/arm/mps3/mps3_corstone300_an547.yaml b/boards/arm/mps3/mps3_corstone300_an547.yaml
index 87a7100ed37..b63d2b1211c 100644
--- a/boards/arm/mps3/mps3_corstone300_an547.yaml
+++ b/boards/arm/mps3/mps3_corstone300_an547.yaml
@@ -1,6 +1,6 @@
 #
 # Copyright (c) 2019-2021 Linaro Limited
-# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -17,10 +17,10 @@ simulation:
 toolchain:
   - gnuarmemb
   - zephyr
-  - xtools
 supported:
   - gpio
 testing:
+  default: true
   ignore_tags:
     - drivers
     - bluetooth
diff --git a/boards/arm/mps3/mps3_corstone300_an547_ns.dts b/boards/arm/mps3/mps3_corstone300_an547_ns.dts
index 5a4e0031946..9540682e37b 100644
--- a/boards/arm/mps3/mps3_corstone300_an547_ns.dts
+++ b/boards/arm/mps3/mps3_corstone300_an547_ns.dts
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018-2021 Linaro Limited
- * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ * Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,7 +11,6 @@
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <mem.h>
-#include "mps3_common.dtsi"
 
 / {
 	compatible = "arm,mps3-an547";
@@ -100,3 +99,4 @@
 		};
 	};
 };
+#include "mps3_common.dtsi"
diff --git a/boards/arm/mps3/mps3_corstone300_an547_ns.yaml b/boards/arm/mps3/mps3_corstone300_an547_ns.yaml
index 3efa3da5de6..15e47f38110 100644
--- a/boards/arm/mps3/mps3_corstone300_an547_ns.yaml
+++ b/boards/arm/mps3/mps3_corstone300_an547_ns.yaml
@@ -16,7 +16,6 @@ simulation:
 toolchain:
   - gnuarmemb
   - zephyr
-  - xtools
 testing:
   default: true
   only_tags:
diff --git a/boards/arm/mps3/mps3_corstone300_an552.dts b/boards/arm/mps3/mps3_corstone300_an552.dts
index 7c7ec8d02a5..51aabcda2fa 100644
--- a/boards/arm/mps3/mps3_corstone300_an552.dts
+++ b/boards/arm/mps3/mps3_corstone300_an552.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ * Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,6 @@
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <mem.h>
-#include "mps3_common.dtsi"
 
 / {
 	compatible = "arm,mps3-an552";
@@ -94,3 +93,4 @@
 		};
 	};
 };
+#include "mps3_common.dtsi"
diff --git a/boards/arm/mps3/mps3_corstone300_an552.yaml b/boards/arm/mps3/mps3_corstone300_an552.yaml
index ecabe715085..8feba8f3d6c 100644
--- a/boards/arm/mps3/mps3_corstone300_an552.yaml
+++ b/boards/arm/mps3/mps3_corstone300_an552.yaml
@@ -10,7 +10,6 @@ flash: 512
 toolchain:
   - gnuarmemb
   - zephyr
-  - xtools
 supported:
   - gpio
 testing:
diff --git a/boards/arm/mps3/mps3_corstone300_an552_ns.dts b/boards/arm/mps3/mps3_corstone300_an552_ns.dts
index 17e9d259bca..7b8bab99ff6 100644
--- a/boards/arm/mps3/mps3_corstone300_an552_ns.dts
+++ b/boards/arm/mps3/mps3_corstone300_an552_ns.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ * Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,6 @@
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <mem.h>
-#include "mps3_common.dtsi"
 
 / {
 	compatible = "arm,mps3-an552";
@@ -99,3 +98,4 @@
 		};
 	};
 };
+#include "mps3_common.dtsi"
diff --git a/boards/arm/mps3/mps3_corstone300_an552_ns.yaml b/boards/arm/mps3/mps3_corstone300_an552_ns.yaml
index b8a914a5725..229778378bd 100644
--- a/boards/arm/mps3/mps3_corstone300_an552_ns.yaml
+++ b/boards/arm/mps3/mps3_corstone300_an552_ns.yaml
@@ -10,7 +10,6 @@ flash: 512
 toolchain:
   - gnuarmemb
   - zephyr
-  - xtools
 testing:
   default: true
   only_tags:
diff --git a/boards/arm/mps3/mps3_corstone300_fvp.dts b/boards/arm/mps3/mps3_corstone300_fvp.dts
index eff11378c61..886b8d77629 100644
--- a/boards/arm/mps3/mps3_corstone300_fvp.dts
+++ b/boards/arm/mps3/mps3_corstone300_fvp.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ * Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,6 @@
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <mem.h>
-#include "mps3_common.dtsi"
 
 / {
 	compatible = "arm,mps3-fvp";
@@ -94,3 +93,4 @@
 		};
 	};
 };
+#include "mps3_common.dtsi"
diff --git a/boards/arm/mps3/mps3_corstone300_fvp.yaml b/boards/arm/mps3/mps3_corstone300_fvp.yaml
index 3d850b7f4ea..e6cb88bc5a7 100644
--- a/boards/arm/mps3/mps3_corstone300_fvp.yaml
+++ b/boards/arm/mps3/mps3_corstone300_fvp.yaml
@@ -1,4 +1,4 @@
-# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 identifier: mps3/corstone300/fvp
@@ -13,12 +13,11 @@ simulation:
 toolchain:
   - gnuarmemb
   - zephyr
-  - xtools
 supported:
   - gpio
 testing:
+  default: true
   ignore_tags:
-    - drivers
     - bluetooth
     - net
     - timer
diff --git a/boards/arm/mps3/mps3_corstone300_fvp_ns.dts b/boards/arm/mps3/mps3_corstone300_fvp_ns.dts
index 8a9704cae3a..d2be764eb50 100644
--- a/boards/arm/mps3/mps3_corstone300_fvp_ns.dts
+++ b/boards/arm/mps3/mps3_corstone300_fvp_ns.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ * Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,6 @@
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <mem.h>
-#include "mps3_common.dtsi"
 
 / {
 	compatible = "arm,mps3-fvp";
@@ -99,3 +98,4 @@
 		};
 	};
 };
+#include "mps3_common.dtsi"
diff --git a/boards/arm/mps3/mps3_corstone300_fvp_ns.yaml b/boards/arm/mps3/mps3_corstone300_fvp_ns.yaml
index 0802a129434..52de52a2a1b 100644
--- a/boards/arm/mps3/mps3_corstone300_fvp_ns.yaml
+++ b/boards/arm/mps3/mps3_corstone300_fvp_ns.yaml
@@ -7,12 +7,9 @@ type: mcu
 arch: arm
 ram: 2048
 flash: 512
-# Related issue #81656
-twister: false
 toolchain:
   - gnuarmemb
   - zephyr
-  - xtools
 testing:
   default: true
   only_tags:
diff --git a/boards/arm/mps3/mps3_corstone310_an555.dts b/boards/arm/mps3/mps3_corstone310_an555.dts
index f16aff58eae..47c2a9626a8 100644
--- a/boards/arm/mps3/mps3_corstone310_an555.dts
+++ b/boards/arm/mps3/mps3_corstone310_an555.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ * Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,6 @@
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <mem.h>
-#include "mps3_common.dtsi"
 
 / {
 	compatible = "arm,mps3-an555";
@@ -20,8 +19,8 @@
 	chosen {
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
-		zephyr,sram = &dtcm;
-		zephyr,flash = &itcm;
+		zephyr,sram = &sram;
+		zephyr,flash = &isram;
 	};
 
 	cpus {
@@ -94,3 +93,4 @@
 		};
 	};
 };
+#include "mps3_common.dtsi"
diff --git a/boards/arm/mps3/mps3_corstone310_an555.yaml b/boards/arm/mps3/mps3_corstone310_an555.yaml
index 5bcd0fb1925..5005c8c6843 100644
--- a/boards/arm/mps3/mps3_corstone310_an555.yaml
+++ b/boards/arm/mps3/mps3_corstone310_an555.yaml
@@ -10,7 +10,6 @@ flash: 32
 toolchain:
   - gnuarmemb
   - zephyr
-  - xtools
 supported:
   - gpio
 testing:
diff --git a/boards/arm/mps3/mps3_corstone310_an555_defconfig b/boards/arm/mps3/mps3_corstone310_an555_defconfig
index f5607f3da4c..cfea436df56 100644
--- a/boards/arm/mps3/mps3_corstone310_an555_defconfig
+++ b/boards/arm/mps3/mps3_corstone310_an555_defconfig
@@ -1,4 +1,4 @@
-# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 CONFIG_RUNTIME_NMI=y
@@ -15,3 +15,5 @@ CONFIG_SERIAL=y
 
 # Build a Secure firmware image
 CONFIG_TRUSTED_EXECUTION_SECURE=y
+# ROMSTART_REGION address and size are defined in Kconfig.defconfig
+CONFIG_ROMSTART_RELOCATION_ROM=y
diff --git a/boards/arm/mps3/mps3_corstone310_an555_ns.dts b/boards/arm/mps3/mps3_corstone310_an555_ns.dts
index 786ca6d9eb1..4a910777e11 100644
--- a/boards/arm/mps3/mps3_corstone310_an555_ns.dts
+++ b/boards/arm/mps3/mps3_corstone310_an555_ns.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ * Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,6 @@
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <mem.h>
-#include "mps3_common.dtsi"
 
 / {
 	compatible = "arm,mps3-an555";
@@ -99,3 +98,4 @@
 		};
 	};
 };
+#include "mps3_common.dtsi"
diff --git a/boards/arm/mps3/mps3_corstone310_an555_ns.yaml b/boards/arm/mps3/mps3_corstone310_an555_ns.yaml
index f6a1f444f39..80423596e31 100644
--- a/boards/arm/mps3/mps3_corstone310_an555_ns.yaml
+++ b/boards/arm/mps3/mps3_corstone310_an555_ns.yaml
@@ -10,7 +10,6 @@ flash: 32
 toolchain:
   - gnuarmemb
   - zephyr
-  - xtools
 testing:
   default: true
   only_tags:
diff --git a/boards/arm/mps3/mps3_corstone310_fvp.dts b/boards/arm/mps3/mps3_corstone310_fvp.dts
index 6ad45b5f973..585a7297d72 100644
--- a/boards/arm/mps3/mps3_corstone310_fvp.dts
+++ b/boards/arm/mps3/mps3_corstone310_fvp.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ * Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,6 @@
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <mem.h>
-#include "mps3_common.dtsi"
 
 / {
 	compatible = "arm,mps3-fvp";
@@ -20,8 +19,8 @@
 	chosen {
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
-		zephyr,sram = &dtcm;
-		zephyr,flash = &itcm;
+		zephyr,sram = &sram;
+		zephyr,flash = &isram;
 	};
 
 	cpus {
@@ -94,3 +93,4 @@
 		};
 	};
 };
+#include "mps3_common.dtsi"
diff --git a/boards/arm/mps3/mps3_corstone310_fvp.yaml b/boards/arm/mps3/mps3_corstone310_fvp.yaml
index ab6c8d7e561..7259d65a238 100644
--- a/boards/arm/mps3/mps3_corstone310_fvp.yaml
+++ b/boards/arm/mps3/mps3_corstone310_fvp.yaml
@@ -1,4 +1,4 @@
-# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 identifier: mps3/corstone310/fvp
@@ -13,10 +13,10 @@ simulation:
 toolchain:
   - gnuarmemb
   - zephyr
-  - xtools
 supported:
   - gpio
 testing:
+  default: true
   ignore_tags:
     - drivers
     - bluetooth
diff --git a/boards/arm/mps3/mps3_corstone310_fvp_defconfig b/boards/arm/mps3/mps3_corstone310_fvp_defconfig
index f5607f3da4c..cfea436df56 100644
--- a/boards/arm/mps3/mps3_corstone310_fvp_defconfig
+++ b/boards/arm/mps3/mps3_corstone310_fvp_defconfig
@@ -1,4 +1,4 @@
-# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 CONFIG_RUNTIME_NMI=y
@@ -15,3 +15,5 @@ CONFIG_SERIAL=y
 
 # Build a Secure firmware image
 CONFIG_TRUSTED_EXECUTION_SECURE=y
+# ROMSTART_REGION address and size are defined in Kconfig.defconfig
+CONFIG_ROMSTART_RELOCATION_ROM=y
diff --git a/boards/arm/mps3/mps3_corstone310_fvp_ns.dts b/boards/arm/mps3/mps3_corstone310_fvp_ns.dts
index acc9b5fb737..9cd73ee3959 100644
--- a/boards/arm/mps3/mps3_corstone310_fvp_ns.dts
+++ b/boards/arm/mps3/mps3_corstone310_fvp_ns.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ * Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,7 +10,6 @@
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <mem.h>
-#include "mps3_common.dtsi"
 
 / {
 	compatible = "arm,mps3-fvp";
@@ -99,3 +98,4 @@
 		};
 	};
 };
+#include "mps3_common.dtsi"
diff --git a/boards/arm/mps3/mps3_corstone310_fvp_ns.yaml b/boards/arm/mps3/mps3_corstone310_fvp_ns.yaml
index 6a70eff7fb0..307329bcf90 100644
--- a/boards/arm/mps3/mps3_corstone310_fvp_ns.yaml
+++ b/boards/arm/mps3/mps3_corstone310_fvp_ns.yaml
@@ -10,7 +10,6 @@ flash: 32
 toolchain:
   - gnuarmemb
   - zephyr
-  - xtools
 testing:
   default: true
   only_tags:
diff --git a/boards/arm/v2m_beetle/CMakeLists.txt b/boards/arm/v2m_beetle/CMakeLists.txt
deleted file mode 100644
index 9bc25bae4c6..00000000000
--- a/boards/arm/v2m_beetle/CMakeLists.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library()
-zephyr_library_sources(pinmux.c)
diff --git a/boards/arm/v2m_beetle/pinmux.c b/boards/arm/v2m_beetle/pinmux.c
deleted file mode 100644
index 856239761b8..00000000000
--- a/boards/arm/v2m_beetle/pinmux.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Copyright (c) 2016 Linaro Limited
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/device.h>
-#include <zephyr/init.h>
-#include <zephyr/kernel.h>
-#include <soc.h>
-#include <zephyr/sys/sys_io.h>
-#include <zephyr/drivers/gpio/gpio_cmsdk_ahb.h>
-
-/**
- * @brief Pinmux driver for ARM V2M Beetle Board
- *
- * The ARM V2M Beetle Board has 4 GPIO controllers. These controllers
- * are responsible for pin muxing, input/output, pull-up, etc.
- *
- * The GPIO controllers 2 and 3 are reserved and therefore not exposed by
- * this driver.
- *
- * All GPIO controller exposed pins are exposed via the following sequence of
- * pin numbers:
- *   Pins  0 -  15 are for GPIO0
- *   Pins 16 -  31 are for GPIO1
- *
- * For the exposed GPIO controllers ARM V2M Beetle Board follows the Arduino
- * compliant pin out.
- */
-
-#define CMSDK_AHB_GPIO0_DEV \
-	((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio0)))
-#define CMSDK_AHB_GPIO1_DEV \
-	((volatile struct gpio_cmsdk_ahb *)DT_REG_ADDR(DT_NODELABEL(gpio1)))
-
-/*
- * This is the mapping from the ARM V2M Beetle Board pins to GPIO
- * controllers.
- *
- * D0 : P0_0
- * D1 : P0_1
- * D2 : P0_2
- * D3 : P0_3
- * D4 : P0_4
- * D5 : P0_5
- * D6 : P0_6
- * D7 : P0_7
- * D8 : P0_8
- * D9 : P0_9
- * D10 : P0_10
- * D11 : P0_11
- * D12 : P0_12
- * D13 : P0_13
- * D14 : P0_14
- * D15 : P0_15
- * D16 : P1_0
- * D17 : P1_1
- * D18 : P1_2
- * D19 : P1_3
- * D20 : P1_4
- * D21 : P1_5
- * D22 : P1_6
- * D23 : P1_7
- * D24 : P1_8
- * D25 : P1_9
- * D26 : P1_10
- * D27 : P1_11
- * D28 : P1_12
- * D29 : P1_13
- * D30 : P1_14
- * D31 : P1_15
- *
- * UART_0_RX : D0
- * UART_0_TX : D1
- * SPI_0_CS : D10
- * SPI_0_MOSI : D11
- * SPI_0_MISO : D12
- * SPI_0_SCLK : D13
- * I2C_0_SCL : D14
- * I2C_0_SDA : D15
- * UART_1_RX : D16
- * UART_1_TX : D17
- * SPI_1_CS : D18
- * SPI_1_MOSI : D19
- * SPI_1_MISO : D20
- * SPI_1_SCK : D21
- * I2C_1_SDA : D22
- * I2C_1_SCL : D23
- *
- */
-static void arm_v2m_beetle_pinmux_defaults(void)
-{
-	uint32_t gpio_0 = 0U;
-	uint32_t gpio_1 = 0U;
-
-	/* Set GPIO Alternate Functions */
-
-	gpio_0 = (1<<0); /* Shield 0 UART 0 RXD */
-	gpio_0 |= (1<<1); /* Shield 0 UART 0 TXD */
-	gpio_0 |= (1<<14); /* Shield 0 I2C SDA SBCON2 */
-	gpio_0 |= (1<<15); /* Shield 0 I2C SCL SBCON2 */
-	gpio_0 |= (1<<10); /* Shield 0 SPI_3 nCS */
-	gpio_0 |= (1<<11); /* Shield 0 SPI_3 MOSI */
-	gpio_0 |= (1<<12); /* Shield 0 SPI_3 MISO */
-	gpio_0 |= (1<<13); /* Shield 0 SPI_3 SCK */
-
-	CMSDK_AHB_GPIO0_DEV->altfuncset = gpio_0;
-
-	gpio_1 = (1<<0); /* UART 1 RXD */
-	gpio_1 |= (1<<1); /* UART 1 TXD */
-	gpio_1 |= (1<<6); /* Shield 1 I2C SDA */
-	gpio_1 |= (1<<7); /* Shield 1 I2C SCL */
-	gpio_1 |= (1<<2); /* ADC SPI_1 nCS */
-	gpio_1 |= (1<<3); /* ADC SPI_1 MOSI */
-	gpio_1 |= (1<<4); /* ADC SPI_1 MISO */
-	gpio_1 |= (1<<5); /* ADC SPI_1 SCK */
-
-	gpio_1 |= (1<<8); /* QSPI CS 2 */
-	gpio_1 |= (1<<9); /* QSPI CS 1 */
-	gpio_1 |= (1<<10); /* QSPI IO 0 */
-	gpio_1 |= (1<<11); /* QSPI IO 1 */
-	gpio_1 |= (1<<12); /* QSPI IO 2 */
-	gpio_1 |= (1<<13); /* QSPI IO 3 */
-	gpio_1 |= (1<<14); /* QSPI SCK */
-
-	CMSDK_AHB_GPIO1_DEV->altfuncset = gpio_1;
-
-	/* Set the ARD_PWR_EN GPIO1[15] as an output */
-	CMSDK_AHB_GPIO1_DEV->outenableset |= (0x1 << 15);
-	/* Set on 3v3 (for ARDUINO HDR compliance) */
-	CMSDK_AHB_GPIO1_DEV->data |= (0x1 << 15);
-}
-
-static int arm_v2m_beetle_pinmux_init(void)
-{
-
-	arm_v2m_beetle_pinmux_defaults();
-
-	return 0;
-}
-
-SYS_INIT(arm_v2m_beetle_pinmux_init, PRE_KERNEL_1,
-	CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/boards/arm/v2m_beetle/v2m_beetle-pinctrl.dtsi b/boards/arm/v2m_beetle/v2m_beetle-pinctrl.dtsi
new file mode 100644
index 00000000000..3bd342daac9
--- /dev/null
+++ b/boards/arm/v2m_beetle/v2m_beetle-pinctrl.dtsi
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/arm-v2m_beetle-pinctrl.h>
+
+&pinctrl {
+	/omit-if-no-ref/  uart0_default: uart0_default {
+		group1 {
+			pinmux = <UART0_TXD_EXP>;
+		};
+
+		group2 {
+			pinmux = <UART0_RXD_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ uart1_default: uart1_default {
+		group1 {
+			pinmux = <UART1_TXD_EXP>;
+		};
+
+		group2 {
+			pinmux = <UART1_RXD_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ spi0_default: spi0_default {
+		group1 {
+			pinmux = <SPI0_SS_EXP>, <SPI0_MOSI_EXP>, <SPI0_SCK_EXP>;
+		};
+		group2 {
+			pinmux = <SPI0_MISO_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ spi1_default: spi1_default {
+		group1 {
+			pinmux = <SPI1_SCK_EXP>, <SPI1_SS_EXP>, <SPI0_MOSI_EXP>;
+
+		};
+		group2 {
+			pinmux = <SPI1_MISO_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ sbcon0_default: sbcon0_default {
+		group1 {
+			pinmux = <SBCON0_SDA_EXP>, <SBCON0_SCL_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ sbcon1_default: sbcon1_default {
+		group1 {
+			pinmux = <SBCON1_SDA_EXP>, <SBCON1_SCL_EXP>;
+			input-enable;
+		};
+	};
+};
diff --git a/boards/arm/v2m_beetle/v2m_beetle.dts b/boards/arm/v2m_beetle/v2m_beetle.dts
index abb2687701c..8e8dc71872a 100644
--- a/boards/arm/v2m_beetle/v2m_beetle.dts
+++ b/boards/arm/v2m_beetle/v2m_beetle.dts
@@ -74,6 +74,8 @@
 			interrupts = <0 3>;
 			clocks = <&sysclk &syscon>;
 			current-speed = <115200>;
+			pinctrl-0 = <&uart0_default>;
+			pinctrl-names = "default";
 		};
 
 		uart1: uart@40005000 {
@@ -82,6 +84,8 @@
 			interrupts = <2 3>;
 			clocks = <&sysclk &syscon>;
 			current-speed = <115200>;
+			pinctrl-0 = <&uart1_default>;
+			pinctrl-names = "default";
 		};
 
 		wdog0: wdog@40008000 {
@@ -131,9 +135,15 @@
 			reg = <0x4001f000 0x1000>;
 			#clock-cells = <0>;
 		};
+
+		pinctrl: pinctrl {
+			compatible = "arm,mps3-pinctrl";
+			status = "okay";
+		};
 	};
 };
 
 &nvic {
 	arm,num-irq-priority-bits = <3>;
 };
+#include "v2m_beetle-pinctrl.dtsi"
diff --git a/boards/arm/v2m_beetle/v2m_beetle.yaml b/boards/arm/v2m_beetle/v2m_beetle.yaml
index ca1e17d2d8d..3284abddb36 100644
--- a/boards/arm/v2m_beetle/v2m_beetle.yaml
+++ b/boards/arm/v2m_beetle/v2m_beetle.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
 vendor: arm
diff --git a/boards/arm/v2m_musca_b1/v2m_musca_b1.yaml b/boards/arm/v2m_musca_b1/v2m_musca_b1.yaml
index 72be434271d..51b0acbf3a4 100644
--- a/boards/arm/v2m_musca_b1/v2m_musca_b1.yaml
+++ b/boards/arm/v2m_musca_b1/v2m_musca_b1.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
 vendor: arm
diff --git a/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns.yaml b/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns.yaml
index 8f8700b0885..7d13a46149f 100644
--- a/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns.yaml
+++ b/boards/arm/v2m_musca_b1/v2m_musca_b1_musca_b1_ns.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 1663
 vendor: arm
diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1.yaml b/boards/arm/v2m_musca_s1/v2m_musca_s1.yaml
index 7e99e0fc4eb..2d35c16b3c3 100644
--- a/boards/arm/v2m_musca_s1/v2m_musca_s1.yaml
+++ b/boards/arm/v2m_musca_s1/v2m_musca_s1.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
 vendor: arm
diff --git a/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.yaml b/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.yaml
index 090f6996c58..747247dcc75 100644
--- a/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.yaml
+++ b/boards/arm/v2m_musca_s1/v2m_musca_s1_musca_s1_ns.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 256
 flash: 511
 vendor: arm
diff --git a/boards/aspeed/ast1030_evb/doc/index.rst b/boards/aspeed/ast1030_evb/doc/index.rst
index 1c23d7d2644..1faa0185e27 100644
--- a/boards/aspeed/ast1030_evb/doc/index.rst
+++ b/boards/aspeed/ast1030_evb/doc/index.rst
@@ -26,22 +26,7 @@ Hardware
 Supported Features
 ==================
 
-The following features are supported:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by Zephyr (at the moment)
-
-The default configuration can be found in
-:zephyr_file:`boards/aspeed/ast1030_evb/ast1030_evb_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -63,6 +48,8 @@ UART5 is configured for serial logs.  The default serial setup is 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 This board comes with a JTAG port which facilitates debugging using a single physical connection.
 
 Flashing
diff --git a/boards/atmel/sam/sam4e_xpro/doc/index.rst b/boards/atmel/sam/sam4e_xpro/doc/index.rst
index 1069727aa6c..fe51eaf3f90 100644
--- a/boards/atmel/sam/sam4e_xpro/doc/index.rst
+++ b/boards/atmel/sam/sam4e_xpro/doc/index.rst
@@ -27,45 +27,7 @@ Hardware
 Supported Features
 ==================
 
-The sam4e_xpro board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| AFEC      | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| HWINFO    | on-chip    | hwinfo                              |
-+-----------+------------+-------------------------------------+
-| HSMCI     | on-chip    | sdhc                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| USART     | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig
-:zephyr_file:`boards/atmel/sam/sam4e_xpro/sam4e_xpro_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -89,6 +51,8 @@ chip.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing the Zephyr project onto SAM4E MCU requires the `OpenOCD tool`_.
 By default a factory new SAM4E chip will boot SAM-BA boot loader located in
 the ROM, not the flashed image. This is determined by the value of GPNVM1
diff --git a/boards/atmel/sam/sam4e_xpro/sam4e_xpro.yaml b/boards/atmel/sam/sam4e_xpro/sam4e_xpro.yaml
index 561b06b8afe..ef72c87ba72 100644
--- a/boards/atmel/sam/sam4e_xpro/sam4e_xpro.yaml
+++ b/boards/atmel/sam/sam4e_xpro/sam4e_xpro.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 flash: 1024
 ram: 128
 supported:
diff --git a/boards/atmel/sam/sam4l_ek/doc/index.rst b/boards/atmel/sam/sam4l_ek/doc/index.rst
index f958a540515..899498f61a5 100644
--- a/boards/atmel/sam/sam4l_ek/doc/index.rst
+++ b/boards/atmel/sam/sam4l_ek/doc/index.rst
@@ -49,38 +49,7 @@ Hardware
 Supported Features
 ==================
 
-The sam4l_ek board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | arch/arm                            |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | arch/arm                            |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| HWINFO    | on-chip    | Unique 120 bit serial number        |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| TWIM      | on-chip    | i2c master port-interrupt           |
-+-----------+------------+-------------------------------------+
-| USART     | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb device                          |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig
-:zephyr_file:`boards/atmel/sam/sam4l_ek/sam4l_ek_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -104,6 +73,8 @@ between all others headers and RS-485 port.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The SAM4L-EK board have a Segger Embedded Debugger Unit
 `J-Link OB <https://www.segger.com/jlink-ob.html>`_.  This provides a debug
 interface to the SAM4LC4C chip. You can use Ozone or JLink to communicate with
diff --git a/boards/atmel/sam/sam4l_ek/sam4l_ek.yaml b/boards/atmel/sam/sam4l_ek/sam4l_ek.yaml
index 3a8193e5515..3be5a297f05 100644
--- a/boards/atmel/sam/sam4l_ek/sam4l_ek.yaml
+++ b/boards/atmel/sam/sam4l_ek/sam4l_ek.yaml
@@ -1,3 +1,6 @@
+# Copyright (c) 2020-2025, Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
 identifier: sam4l_ek
 name: SAM4L-EK
 type: mcu
@@ -5,7 +8,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 flash: 256
 ram: 32
 supported:
@@ -17,4 +19,5 @@ supported:
   - spi
   - uart
   - usb_device
+  - watchdog
 vendor: atmel
diff --git a/boards/atmel/sam/sam4l_ek/sam4l_ek_defconfig b/boards/atmel/sam/sam4l_ek/sam4l_ek_defconfig
index 6c902f537d7..141c98be565 100644
--- a/boards/atmel/sam/sam4l_ek/sam4l_ek_defconfig
+++ b/boards/atmel/sam/sam4l_ek/sam4l_ek_defconfig
@@ -1,7 +1,9 @@
+# Copyright (c) 2020-2025, Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
 CONFIG_ARM_MPU=y
 CONFIG_HW_STACK_PROTECTION=y
+CONFIG_WDT_DISABLE_AT_BOOT=y
 
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
diff --git a/boards/atmel/sam/sam4s_xplained/doc/index.rst b/boards/atmel/sam/sam4s_xplained/doc/index.rst
index 480411323bd..6f39a88367a 100644
--- a/boards/atmel/sam/sam4s_xplained/doc/index.rst
+++ b/boards/atmel/sam/sam4s_xplained/doc/index.rst
@@ -23,43 +23,7 @@ Hardware
 Supported Features
 ==================
 
-The sam4s_xplained board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| HWINFO    | on-chip    | Unique device serial number         |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| SMC       | on-chip    | memc (PSRAM)                        |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| USART     | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig
-:zephyr_file:`boards/atmel/sam/sam4s_xplained/sam4s_xplained_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -84,6 +48,8 @@ The section flashing uses the UART from the Segger USB debug connection.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The SAM4S Xplained board comes with Segger
 `J-Link OB <https://www.segger.com/jlink-ob.html>`_. This provides a debug
 interface to the SAM4S16C chip. You can use Ozone or JLink to communicate with
diff --git a/boards/atmel/sam/sam4s_xplained/sam4s_xplained-pinctrl.dtsi b/boards/atmel/sam/sam4s_xplained/sam4s_xplained-pinctrl.dtsi
index 703e04ca5e1..479755f1a79 100644
--- a/boards/atmel/sam/sam4s_xplained/sam4s_xplained-pinctrl.dtsi
+++ b/boards/atmel/sam/sam4s_xplained/sam4s_xplained-pinctrl.dtsi
@@ -29,18 +29,21 @@
 				 <PA10A_UART0_TXD>;
 		};
 	};
+
 	uart1_default: uart1_default {
 		group1 {
 			pinmux = <PB2A_UART1_RXD>,
 				 <PB3A_UART1_TXD>;
 		};
 	};
+
 	usart1_default: usart1_default {
 		group1 {
 			pinmux = <PA21A_USART1_RXD>,
 				 <PA22A_USART1_TXD>;
 		};
 	};
+
 	pwm0_default: pwm0_default {
 		group1 {
 			pinmux = <PA12B_PWM_PWMH1>,
@@ -48,12 +51,21 @@
 				 <PA14B_PWM_PWMH3>;
 		};
 	};
+
 	adc0_default: adc0_default {
 		group1 {
 			pinmux = <PB0X_ADC_AD4>,
 				 <PB1X_ADC_AD5>;
 		};
 	};
+
+	dacc_default: dacc_default {
+		group1 {
+			pinmux = <PB13D_DACC_DAC0>,
+				 <PB14D_DACC_DAC1>;
+		};
+	};
+
 	smc_default: smc_default {
 		group1 {
 			pinmux = <PC18A_EBI_A0>,
diff --git a/boards/atmel/sam/sam4s_xplained/sam4s_xplained.dts b/boards/atmel/sam/sam4s_xplained/sam4s_xplained.dts
index 2e06d08aade..eb777a75b17 100644
--- a/boards/atmel/sam/sam4s_xplained/sam4s_xplained.dts
+++ b/boards/atmel/sam/sam4s_xplained/sam4s_xplained.dts
@@ -190,6 +190,13 @@
 	tracking-time = <2>;
 };
 
+&dacc {
+	status = "okay";
+
+	pinctrl-0 = <&dacc_default>;
+	pinctrl-names = "default";
+};
+
 &wdt {
 	status = "okay";
 };
diff --git a/boards/atmel/sam/sam4s_xplained/sam4s_xplained.yaml b/boards/atmel/sam/sam4s_xplained/sam4s_xplained.yaml
index 0cc1a4f9deb..857d2995164 100644
--- a/boards/atmel/sam/sam4s_xplained/sam4s_xplained.yaml
+++ b/boards/atmel/sam/sam4s_xplained/sam4s_xplained.yaml
@@ -5,12 +5,12 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 flash: 1024
 ram: 128
 supported:
   - adc
   - counter
+  - dac
   - gpio
   - hwinfo
   - memc
diff --git a/boards/atmel/sam/sam_e70_xplained/doc/index.rst b/boards/atmel/sam/sam_e70_xplained/doc/index.rst
index 6c816439176..659f793049d 100644
--- a/boards/atmel/sam/sam_e70_xplained/doc/index.rst
+++ b/boards/atmel/sam/sam_e70_xplained/doc/index.rst
@@ -27,53 +27,7 @@ Hardware
 Supported Features
 ==================
 
-The sam_e70_xplained board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| AFEC      | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| CAN FD    | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | dac                                 |
-+-----------+------------+-------------------------------------+
-| HWINFO    | on-chip    | Unique device serial number         |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| I2S       | on-chip    | i2s                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| USART     | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| XDMAC     | on-chip    | dma                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig
-:zephyr_file:`boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -96,6 +50,8 @@ chip.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing the Zephyr project onto SAM E70 MCU requires the `OpenOCD tool`_.
 Support for Atmel SAM E microcontroller series was added in OpenOCD release
 0.10.0, which was added in Zephyr SDK 0.9.2.
diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml
index a9fb5a4704f..3cec4f75182 100644
--- a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml
+++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 flash: 2048
 ram: 384
 supported:
diff --git a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml
index 4adc2dc6dd3..7a70dbc5844 100644
--- a/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml
+++ b/boards/atmel/sam/sam_e70_xplained/sam_e70_xplained_same70q21b.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 flash: 2048
 ram: 384
 supported:
diff --git a/boards/atmel/sam/sam_v71_xult/doc/index.rst b/boards/atmel/sam/sam_v71_xult/doc/index.rst
index cb7ecbfda43..d58c6ded861 100644
--- a/boards/atmel/sam/sam_v71_xult/doc/index.rst
+++ b/boards/atmel/sam/sam_v71_xult/doc/index.rst
@@ -33,53 +33,7 @@ Hardware
 Supported Features
 ==================
 
-The sam_v71_xplained_ultra board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| AFEC      | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| CAN FD    | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | dac                                 |
-+-----------+------------+-------------------------------------+
-| HWINFO    | on-chip    | Unique device serial number         |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| I2S       | on-chip    | i2s                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| USART     | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| XDMAC     | on-chip    | dma                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig
-:zephyr_file:`boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -102,6 +56,8 @@ for the console and is available as a Virtual COM Port via EDBG USB chip.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing the Zephyr project onto SAM V71 MCU requires the `OpenOCD tool`_.
 By default a factory new SAM V71 chip will boot the `SAM-BA`_ boot loader
 located in the ROM, not the flashed image. This is determined by the value
diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml
index 271565dac24..c1873f6aaae 100644
--- a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml
+++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 flash: 2048
 ram: 384
 supported:
diff --git a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml
index 732d1de39e6..b0a226550c9 100644
--- a/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml
+++ b/boards/atmel/sam/sam_v71_xult/sam_v71_xult_samv71q21b.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 flash: 2048
 ram: 384
 supported:
diff --git a/boards/atmel/sam0/samc21n_xpro/doc/index.rst b/boards/atmel/sam0/samc21n_xpro/doc/index.rst
index 678e3afa453..094f75631ea 100644
--- a/boards/atmel/sam0/samc21n_xpro/doc/index.rst
+++ b/boards/atmel/sam0/samc21n_xpro/doc/index.rst
@@ -25,53 +25,7 @@ Hardware
 Supported Features
 ==================
 
-The samc21n_xpro board configuration supports the following hardware
-features:
-
-.. list-table::
-    :header-rows: 1
-
-    * - Interface
-      - Controller
-      - Driver / Component
-    * - NVIC
-      - on-chip
-      - nested vector interrupt controller
-    * - Flash
-      - on-chip
-      - Can be used with LittleFS to store files
-    * - SYSTICK
-      - on-chip
-      - systick
-    * - WDT
-      - on-chip
-      - Watchdog
-    * - ADC
-      - on-chip
-      - Analog to Digital Converter
-    * - GPIO
-      - on-chip
-      - I/O ports
-    * - PWM
-      - on-chip
-      - Pulse Width Modulation
-    * - USART
-      - on-chip
-      - Serial ports
-    * - I2C
-      - on-chip
-      - I2C ports
-    * - SPI
-      - on-chip
-      - Serial Peripheral Interface ports
-    * - CAN
-      - on-chip
-      - CAN ports
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig
-:zephyr_file:`boards/atmel/sam0/samc21n_xpro/samc21n_xpro_defconfig`.
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -129,6 +83,8 @@ driven by TCC2 instead of by GPIO.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The SAM C21N Xplained Pro comes with a Atmel Embedded Debugger (EDBG). This
 provides a debug interface to the SAMC21 chip and is supported by
 OpenOCD.
diff --git a/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.dts b/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.dts
index 3827dc104d9..dc49e1016c3 100644
--- a/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.dts
+++ b/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2022 Kamil Serwus
+ # Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -82,6 +83,14 @@
 	pinctrl-names = "default";
 };
 
+&rtc {
+	status = "okay";
+	counter-mode = "clock";
+	prescaler = <1024>;
+
+	atmel,assigned-clocks = <&osc32kctrl 4>;
+};
+
 &sercom0 {
 	status = "okay";
 	compatible = "atmel,sam0-uart";
diff --git a/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.yaml b/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.yaml
index 428d79e1110..3c32cfef322 100644
--- a/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.yaml
+++ b/boards/atmel/sam0/samc21n_xpro/samc21n_xpro.yaml
@@ -1,5 +1,5 @@
 # Copyright (c) 2022 Kamil Serwus
-# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
+# Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 identifier: samc21n_xpro
 name: SAM C21N Xplained Pro
@@ -8,7 +8,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 flash: 256
 ram: 32
 supported:
@@ -18,6 +17,7 @@ supported:
   - gpio
   - i2c
   - pwm
+  - rtc
   - spi
   - uart
 vendor: atmel
diff --git a/boards/atmel/sam0/samd20_xpro/doc/index.rst b/boards/atmel/sam0/samd20_xpro/doc/index.rst
index 6127a37aff6..f374a15dad3 100644
--- a/boards/atmel/sam0/samd20_xpro/doc/index.rst
+++ b/boards/atmel/sam0/samd20_xpro/doc/index.rst
@@ -23,47 +23,7 @@ Hardware
 Supported Features
 ==================
 
-The samd20_xpro board configuration supports the following hardware
-features:
-
-.. list-table::
-    :header-rows: 1
-
-    * - Interface
-      - Controller
-      - Driver / Component
-    * - NVIC
-      - on-chip
-      - nested vector interrupt controller
-    * - Flash
-      - on-chip
-      - Can be used with LittleFS to store files
-    * - SYSTICK
-      - on-chip
-      - systick
-    * - WDT
-      - on-chip
-      - Watchdog
-    * - ADC
-      - on-chip
-      - Analog to Digital Converter
-    * - GPIO
-      - on-chip
-      - I/O ports
-    * - USART
-      - on-chip
-      - Serial ports
-    * - I2C
-      - on-chip
-      - I2C ports
-    * - SPI
-      - on-chip
-      - Serial Peripheral Interface ports
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig
-:zephyr_file:`boards/atmel/sam0/samd20_xpro/samd20_xpro_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -93,6 +53,8 @@ SERCOM0 is available on the EXT1 connector.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The SAM D20 Xplained Pro comes with a Atmel Embedded Debugger (EDBG).  This
 provides a debug interface to the SAMD20 chip and is supported by
 OpenOCD.
diff --git a/boards/atmel/sam0/samd20_xpro/samd20_xpro.dts b/boards/atmel/sam0/samd20_xpro/samd20_xpro.dts
index 83f5df99c05..6e465087aef 100644
--- a/boards/atmel/sam0/samd20_xpro/samd20_xpro.dts
+++ b/boards/atmel/sam0/samd20_xpro/samd20_xpro.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018 Sean Nyekjaer
+ # Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -51,6 +52,12 @@
 	clock-frequency = <DT_FREQ_M(48)>;
 };
 
+&rtc {
+	status = "okay";
+	counter-mode = "clock";
+	prescaler = <1024>;
+};
+
 &sercom0 {
 	status = "okay";
 	compatible = "atmel,sam0-spi";
diff --git a/boards/atmel/sam0/samd20_xpro/samd20_xpro.yaml b/boards/atmel/sam0/samd20_xpro/samd20_xpro.yaml
index 1db726120e1..06077f79cd3 100644
--- a/boards/atmel/sam0/samd20_xpro/samd20_xpro.yaml
+++ b/boards/atmel/sam0/samd20_xpro/samd20_xpro.yaml
@@ -1,4 +1,4 @@
-# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
+# Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
 identifier: samd20_xpro
@@ -8,13 +8,13 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 flash: 256
 ram: 32
 supported:
   - flash
   - gpio
   - i2c
+  - rtc
   - spi
   - uart
   - watchdog
diff --git a/boards/atmel/sam0/samd21_xpro/doc/index.rst b/boards/atmel/sam0/samd21_xpro/doc/index.rst
index 057d6d80b8d..a7b2245e158 100644
--- a/boards/atmel/sam0/samd21_xpro/doc/index.rst
+++ b/boards/atmel/sam0/samd21_xpro/doc/index.rst
@@ -23,53 +23,7 @@ Hardware
 Supported Features
 ==================
 
-The samd21_xpro board configuration supports the following hardware
-features:
-
-.. list-table::
-    :header-rows: 1
-
-    * - Interface
-      - Controller
-      - Driver / Component
-    * - NVIC
-      - on-chip
-      - nested vector interrupt controller
-    * - Flash
-      - on-chip
-      - Can be used with LittleFS to store files
-    * - SYSTICK
-      - on-chip
-      - systick
-    * - WDT
-      - on-chip
-      - Watchdog
-    * - ADC
-      - on-chip
-      - Analog to Digital Converter
-    * - GPIO
-      - on-chip
-      - I/O ports
-    * - PWM
-      - on-chip
-      - Pulse Width Modulation
-    * - USART
-      - on-chip
-      - Serial ports
-    * - I2C
-      - on-chip
-      - I2C ports
-    * - SPI
-      - on-chip
-      - Serial Peripheral Interface ports
-    * - USB
-      - on-chip
-      - Universal Serial Bus device ports
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig
-:zephyr_file:`boards/atmel/sam0/samd21_xpro/samd21_xpro_defconfig`.
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -134,6 +88,8 @@ SERCOM5 is connected to an 8 megabit SPI flash.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The SAM D21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG).  This
 provides a debug interface to the SAMD21 chip and is supported by
 OpenOCD.
diff --git a/boards/atmel/sam0/samd21_xpro/samd21_xpro.dts b/boards/atmel/sam0/samd21_xpro/samd21_xpro.dts
index f390bc106de..72c0b815b8b 100644
--- a/boards/atmel/sam0/samd21_xpro/samd21_xpro.dts
+++ b/boards/atmel/sam0/samd21_xpro/samd21_xpro.dts
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2018 Bryan O'Donoghue
- * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
+ # Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -71,6 +71,12 @@
 	pinctrl-names = "default";
 };
 
+&rtc {
+	status = "okay";
+	counter-mode = "clock";
+	prescaler = <1024>;
+};
+
 &sercom0 {
 	status = "okay";
 	compatible = "atmel,sam0-uart";
diff --git a/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml b/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml
index e1e8e08bdbb..2ffa9435ca5 100644
--- a/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml
+++ b/boards/atmel/sam0/samd21_xpro/samd21_xpro.yaml
@@ -1,5 +1,5 @@
 # Copyright (c) 2018 Bryan O'Donoghue
-# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
+# Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
 identifier: samd21_xpro
@@ -9,7 +9,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 flash: 256
 ram: 32
 supported:
@@ -18,6 +17,7 @@ supported:
   - gpio
   - i2c
   - pwm
+  - rtc
   - spi
   - uart
   - usb_device
diff --git a/boards/atmel/sam0/same54_xpro/doc/index.rst b/boards/atmel/sam0/same54_xpro/doc/index.rst
index 61b127d7a1b..3e76b6492d3 100644
--- a/boards/atmel/sam0/same54_xpro/doc/index.rst
+++ b/boards/atmel/sam0/same54_xpro/doc/index.rst
@@ -3,7 +3,7 @@
 Overview
 ********
 
-The SAM E54 Xplained Pro evaluation kit is ideal for evaluation and
+The `SAM E54 Xplained Pro Evaluation Kit`_ is ideal for evaluation and
 prototyping with the SAM E54 Cortex®-M4F processor-based
 microcontrollers. The kit includes Atmel’s Embedded Debugger (EDBG),
 which provides a full debug interface without the need for additional
@@ -36,61 +36,7 @@ Hardware
 Supported Features
 ==================
 
-The same54_xpro board configuration supports the following hardware
-features:
-
-+---------------+------------+----------------------------+
-| Interface     | Controller | Driver/Component           |
-+===============+============+============================+
-| ADC           | on-chip    | adc                        |
-+---------------+------------+----------------------------+
-| DAC           | on-chip    | dac                        |
-+---------------+------------+----------------------------+
-| DMAC          | on-chip    | dma                        |
-+---------------+------------+----------------------------+
-| EEPROM        | i2c        | eeprom, EUI-48 MAC Address |
-+---------------+------------+----------------------------+
-| EIC           | on-chip    | interrupt_controller       |
-+---------------+------------+----------------------------+
-| GMAC          | on-chip    | ethernet, mdio             |
-+---------------+------------+----------------------------+
-| GPIO          | on-chip    | gpio                       |
-+---------------+------------+----------------------------+
-| MPU           | on-chip    | arch/arm                   |
-+---------------+------------+----------------------------+
-| NVIC          | on-chip    | arch/arm                   |
-+---------------+------------+----------------------------+
-| NVMCTRL       | on-chip    | flash                      |
-+---------------+------------+----------------------------+
-| PORT          | on-chip    | pinctrl                    |
-+---------------+------------+----------------------------+
-| RTC           | on-chip    | timer                      |
-+---------------+------------+----------------------------+
-| SERCOM I2C    | on-chip    | i2c                        |
-+---------------+------------+----------------------------+
-| SERCOM SPI    | on-chip    | spi                        |
-+---------------+------------+----------------------------+
-| SERCOM USART  | on-chip    | serial, console            |
-+---------------+------------+----------------------------+
-| Serial Number | on-chip    | hwinfo                     |
-+---------------+------------+----------------------------+
-| SYSTICK       | on-chip    | timer                      |
-+---------------+------------+----------------------------+
-| TC            | on-chip    | counter                    |
-+---------------+------------+----------------------------+
-| TCC           | on-chip    | counter, pwm               |
-+---------------+------------+----------------------------+
-| TRNG          | on-chip    | entropy                    |
-+---------------+------------+----------------------------+
-| USB           | on-chip    | usb                        |
-+---------------+------------+----------------------------+
-| WDT           | on-chip    | watchdog                   |
-+---------------+------------+----------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig
-:zephyr_file:`boards/atmel/sam0/same54_xpro/same54_xpro_defconfig`.
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -98,8 +44,9 @@ Pin Mapping
 The SAM E54 Xplained Pro evaluation kit has 4 GPIO controllers. These
 controllers are responsible for pin muxing, input/output, pull-up, etc.
 
-For more details please refer to `SAM D5x/E5x Family Datasheet`_ and the `SAM E54
-Xplained Pro Schematic`_.
+For more details please refer to `SAM D5x/E5x Family Datasheet (Web)`_, the `SAM E54
+Xplained Pro Schematic (Blue PCB)`_, or `SAM E54
+Xplained Pro Schematic (Red PCB)`_.
 
 .. image:: img/ATSAME54-XPRO-pinout.jpg
      :align: center
@@ -165,6 +112,8 @@ Authentication device.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The SAM E54 Xplained Pro comes with a Atmel Embedded Debugger (EDBG).  This
 provides a debug interface to the SAME54 chip and is supported by
 OpenOCD.
@@ -213,11 +162,17 @@ References
 
 .. target-notes::
 
-.. _Microchip website:
-    http://www.microchip.com/DevelopmentTools/ProductDetails.aspx?PartNO=ATSAME54-XPRO
+.. _SAM E54 Xplained Pro Evaluation Kit:
+    https://www.microchip.com/en-us/development-tool/ATSAME54-XPRO
+
+.. _SAM D5x/E5x Family Datasheet (Web):
+    https://onlinedocs.microchip.com/oxy/GUID-AA358083-AEED-4BA8-8511-9F986D3390A5-en-US-2/index.html
+
+.. _Sam D5x/E5x Family Datasheet (PDF):
+    https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/UserGuides/70005321A.pdf
 
-.. _SAM D5x/E5x Family Datasheet:
-    http://ww1.microchip.com/downloads/en/DeviceDoc/60001507C.pdf
+.. _SAM E54 Xplained Pro Schematic (Blue PCB):
+    https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/BoardDesignFiles/SAM-E54-Xplained-Pro-Design-Documentation-Rev9.zip
 
-.. _SAM E54 Xplained Pro Schematic:
-    http://ww1.microchip.com/downloads/en/DeviceDoc/SAME54-Xplained-Pro_Design-Documentation.zip
+.. _SAM E54 Xplained Pro Schematic (Red PCB):
+   https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ProductDocuments/BoardDesignFiles/SAM-E54-Xplained-Pro-Design-Documentation-Rev11.zip
diff --git a/boards/atmel/sam0/same54_xpro/same54_xpro.dts b/boards/atmel/sam0/same54_xpro/same54_xpro.dts
index f8d957727cd..b6b9ff9d78d 100644
--- a/boards/atmel/sam0/same54_xpro/same54_xpro.dts
+++ b/boards/atmel/sam0/same54_xpro/same54_xpro.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2019 Benjamin Valentin
+ # Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -68,6 +69,14 @@
 	pinctrl-names = "default";
 };
 
+&rtc {
+	status = "okay";
+	counter-mode = "clock";
+	prescaler = <1024>;
+
+	atmel,assigned-clocks = <&osc32kctrl 4>;
+};
+
 &sercom2 {
 	status = "okay";
 	compatible = "atmel,sam0-uart";
diff --git a/boards/atmel/sam0/same54_xpro/same54_xpro.yaml b/boards/atmel/sam0/same54_xpro/same54_xpro.yaml
index 1cddeeaf7ad..bd46418551f 100644
--- a/boards/atmel/sam0/same54_xpro/same54_xpro.yaml
+++ b/boards/atmel/sam0/same54_xpro/same54_xpro.yaml
@@ -1,5 +1,5 @@
 # Copyright (c) 2019 Benjamin Valentin
-# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
+# Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 identifier: same54_xpro
 name: SAM E54 Xplained Pro
@@ -8,16 +8,17 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 flash: 1024
 ram: 256
 supported:
   - adc
+  - dma
   - flash
   - gpio
   - i2c
   - netif:eth
   - pwm
+  - rtc
   - spi
   - uart
   - usb_device
diff --git a/boards/atmel/sam0/saml21_xpro/doc/index.rst b/boards/atmel/sam0/saml21_xpro/doc/index.rst
index b92e1bf09a7..90ee2676088 100644
--- a/boards/atmel/sam0/saml21_xpro/doc/index.rst
+++ b/boards/atmel/sam0/saml21_xpro/doc/index.rst
@@ -23,50 +23,7 @@ Hardware
 Supported Features
 ==================
 
-The saml21_xpro board configuration supports the following hardware
-features:
-
-.. list-table::
-    :header-rows: 1
-
-    * - Interface
-      - Controller
-      - Driver / Component
-    * - NVIC
-      - on-chip
-      - nested vector interrupt controller
-    * - Flash
-      - on-chip
-      - Can be used with LittleFS to store files
-    * - SYSTICK
-      - on-chip
-      - systick
-    * - WDT
-      - on-chip
-      - Watchdog
-    * - GPIO
-      - on-chip
-      - I/O ports
-    * - PWM
-      - on-chip
-      - Pulse Width Modulation
-    * - USART
-      - on-chip
-      - Serial ports
-    * - I2C
-      - on-chip
-      - I2C ports
-    * - SPI
-      - on-chip
-      - Serial Peripheral Interface ports
-    * - TRNG
-      - on-chip
-      - True Random Number Generator
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig
-:zephyr_file:`boards/atmel/sam0/saml21_xpro/saml21_xpro_defconfig`.
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -136,6 +93,8 @@ The SAML21 MCU has 6 SERCOM based SPIs, with two configured as SPI in this BSP.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The SAM L21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG).  This
 provides a debug interface to the SAML21 chip and is supported by
 OpenOCD.
diff --git a/boards/atmel/sam0/saml21_xpro/saml21_xpro.dts b/boards/atmel/sam0/saml21_xpro/saml21_xpro.dts
index c0e0e43d666..f1a14ab071b 100644
--- a/boards/atmel/sam0/saml21_xpro/saml21_xpro.dts
+++ b/boards/atmel/sam0/saml21_xpro/saml21_xpro.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2021 Argentum Systems Ltd.
+ # Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -71,6 +72,14 @@
 	pinctrl-names = "default";
 };
 
+&rtc {
+	status = "okay";
+	counter-mode = "clock";
+	prescaler = <1024>;
+
+	atmel,assigned-clocks = <&osc32kctrl 4>;
+};
+
 &sercom0 {
 	status = "okay";
 	compatible = "atmel,sam0-spi";
diff --git a/boards/atmel/sam0/saml21_xpro/saml21_xpro.yaml b/boards/atmel/sam0/saml21_xpro/saml21_xpro.yaml
index be39f0dc517..9588bef980d 100644
--- a/boards/atmel/sam0/saml21_xpro/saml21_xpro.yaml
+++ b/boards/atmel/sam0/saml21_xpro/saml21_xpro.yaml
@@ -1,5 +1,5 @@
 # Copyright (c) 2021 Argentum Systems Ltd.
-# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
+# Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 identifier: saml21_xpro
 name: SAM L21 Xplained Pro
@@ -8,7 +8,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 flash: 256
 ram: 32
 supported:
@@ -18,6 +17,7 @@ supported:
   - gpio
   - i2c
   - pwm
+  - rtc
   - spi
   - uart
   - usb_device
diff --git a/boards/atmel/sam0/samr21_xpro/doc/index.rst b/boards/atmel/sam0/samr21_xpro/doc/index.rst
index e04b4d7a711..94db3100c6e 100644
--- a/boards/atmel/sam0/samr21_xpro/doc/index.rst
+++ b/boards/atmel/sam0/samr21_xpro/doc/index.rst
@@ -23,33 +23,7 @@ Hardware
 Supported Features
 ==================
 
-The samr21_xpro board configuration supports the following hardware
-features:
-
-+-----------+------------+--------------------------------------+
-| Interface | Controller | Driver/Component                     |
-+===========+============+======================================+
-| NVIC      | on-chip    | nested vector interrupt controller   |
-+-----------+------------+--------------------------------------+
-| SYSTICK   | on-chip    | systick                              |
-+-----------+------------+--------------------------------------+
-| WDT       | on-chip    | Watchdog                             |
-+-----------+------------+--------------------------------------+
-| GPIO      | on-chip    | I/O ports                            |
-+-----------+------------+--------------------------------------+
-| PWM       | on-chip    | Pulse Width Modulation               |
-+-----------+------------+--------------------------------------+
-| USART     | on-chip    | Serial ports                         |
-+-----------+------------+--------------------------------------+
-| SPI       | on-chip    | Serial Peripheral Interface ports    |
-+-----------+------------+--------------------------------------+
-| I2C       | on-chip    | I2C Peripheral Interface ports       |
-+-----------+------------+--------------------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig
-:zephyr_file:`boards/atmel/sam0/samr21_xpro/samr21_xpro_defconfig`.
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -160,6 +134,8 @@ echo demo. More information at :zephyr:code-sample:`sockets-echo-server` and
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The SAM R21 Xplained Pro comes with a Atmel Embedded Debugger (EDBG).  This
 provides a debug interface to the SAMR21 chip and is supported by
 OpenOCD.
diff --git a/boards/atmel/sam0/samr21_xpro/samr21_xpro.dts b/boards/atmel/sam0/samr21_xpro/samr21_xpro.dts
index e53fdc80f55..5b7514c26d8 100644
--- a/boards/atmel/sam0/samr21_xpro/samr21_xpro.dts
+++ b/boards/atmel/sam0/samr21_xpro/samr21_xpro.dts
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2019 Benjamin Valentin
- * Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
+ * Copyright (c) 2019-2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -122,6 +122,12 @@
 	pinctrl-names = "default";
 };
 
+&rtc {
+	status = "okay";
+	counter-mode = "clock";
+	prescaler = <1024>;
+};
+
 &sercom0 {
 	status = "okay";
 	compatible = "atmel,sam0-uart";
diff --git a/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml b/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml
index b61a8209edb..77e032878b2 100644
--- a/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml
+++ b/boards/atmel/sam0/samr21_xpro/samr21_xpro.yaml
@@ -1,5 +1,5 @@
 # Copyright (c) 2019 Benjamin Valentin
-# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
+# Copyright (c) 2019-2025 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
 identifier: samr21_xpro
@@ -9,16 +9,17 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 flash: 256
 ram: 32
 supported:
   - adc
+  - dma
   - flash
   - gpio
   - i2c
   - netif
   - pwm
+  - rtc
   - spi
   - uart
   - usb_device
diff --git a/boards/atmel/sam0/samr34_xpro/doc/index.rst b/boards/atmel/sam0/samr34_xpro/doc/index.rst
index 4a38544be35..001233e1180 100644
--- a/boards/atmel/sam0/samr34_xpro/doc/index.rst
+++ b/boards/atmel/sam0/samr34_xpro/doc/index.rst
@@ -28,63 +28,7 @@ Hardware
 Supported Features
 ==================
 
-The samr34_xpro board configuration supports the following hardware
-features:
-
-.. list-table::
-    :header-rows: 1
-
-    * - Interface
-      - Controller
-      - Driver / Component
-    * - NVIC
-      - on-chip
-      - nested vector interrupt controller
-    * - Flash
-      - on-chip
-      - Can be used with LittleFS to store files
-    * - SYSTICK
-      - on-chip
-      - systick
-    * - WDT
-      - on-chip
-      - Watchdog
-    * - GPIO
-      - on-chip
-      - I/O ports
-    * - PWM
-      - on-chip
-      - Pulse Width Modulation
-    * - USART
-      - on-chip
-      - Serial ports
-    * - I2C
-      - on-chip
-      - I2C ports
-    * - SPI
-      - on-chip
-      - Serial Peripheral Interface ports
-    * - TRNG
-      - on-chip
-      - True Random Number Generator
-
-The following hardware features are supported by Zephyr, but not yet fully
-supported by the SOC:
-
-.. list-table::
-    :header-rows: 1
-
-    * - Interface
-      - Controller
-      - Driver / Component
-    * - LoRa Radio
-      - on-chip
-      - Internal SX1276 LoRa Radio
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig
-:zephyr_file:`boards/atmel/sam0/samr34_xpro/samr34_xpro_defconfig`.
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -150,6 +94,8 @@ The SAMR34 MCU has 6 SERCOM based SPIs, with two configured as SPI in this BSP.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The SAM R34 Xplained Pro comes with a Atmel Embedded Debugger (EDBG).  This
 provides a debug interface to the SAMR34 chip and is supported by
 OpenOCD.
diff --git a/boards/atmel/sam0/samr34_xpro/pre_dt_board.cmake b/boards/atmel/sam0/samr34_xpro/pre_dt_board.cmake
new file mode 100644
index 00000000000..94f7f4e4459
--- /dev/null
+++ b/boards/atmel/sam0/samr34_xpro/pre_dt_board.cmake
@@ -0,0 +1,5 @@
+# Copyright (c) 2021 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+# SPI is implemented via sercom so node name isn't spi@...
+list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge")
diff --git a/boards/atmel/sam0/samr34_xpro/samr34_xpro.dts b/boards/atmel/sam0/samr34_xpro/samr34_xpro.dts
index 964cd8af4df..cb267d86dba 100644
--- a/boards/atmel/sam0/samr34_xpro/samr34_xpro.dts
+++ b/boards/atmel/sam0/samr34_xpro/samr34_xpro.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2021 Argentum Systems Ltd.
+ # Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -71,6 +72,14 @@
 	pinctrl-names = "default";
 };
 
+&rtc {
+	status = "okay";
+	counter-mode = "clock";
+	prescaler = <1024>;
+
+	atmel,assigned-clocks = <&osc32kctrl 4>;
+};
+
 &sercom0 {
 	status = "okay";
 	compatible = "atmel,sam0-uart";
diff --git a/boards/atmel/sam0/samr34_xpro/samr34_xpro.yaml b/boards/atmel/sam0/samr34_xpro/samr34_xpro.yaml
index 488fba3bb32..c4365171526 100644
--- a/boards/atmel/sam0/samr34_xpro/samr34_xpro.yaml
+++ b/boards/atmel/sam0/samr34_xpro/samr34_xpro.yaml
@@ -1,5 +1,5 @@
 # Copyright (c) 2021 Argentum Systems Ltd.
-# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
+# Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 identifier: samr34_xpro
 name: SAM R34 Xplained Pro
@@ -8,7 +8,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 flash: 256
 ram: 32
 supported:
@@ -18,6 +17,7 @@ supported:
   - gpio
   - i2c
   - pwm
+  - rtc
   - spi
   - uart
   - usb_device
diff --git a/boards/bbc/microbit/bbc_microbit.yaml b/boards/bbc/microbit/bbc_microbit.yaml
index cb1b12a7d36..521c111f2b8 100644
--- a/boards/bbc/microbit/bbc_microbit.yaml
+++ b/boards/bbc/microbit/bbc_microbit.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 16
 testing:
   ignore_tags:
diff --git a/boards/bbc/microbit/doc/index.rst b/boards/bbc/microbit/doc/index.rst
index 1d829d89a89..9224cd4f24d 100644
--- a/boards/bbc/microbit/doc/index.rst
+++ b/boards/bbc/microbit/doc/index.rst
@@ -13,13 +13,6 @@ magnetometer sensors, Bluetooth and USB connectivity, a display consisting of
 external battery pack. The device inputs and outputs are through five ring
 connectors that are part of the 23-pin edge connector.
 
-* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
-* :abbr:`RTC (nRF RTC System Clock)`
-* UART
-* GPIO
-* FLASH
-* RADIO (Bluetooth Low Energy)
-
 More information about the board can be found at the `microbit website`_.
 
 Hardware
@@ -39,29 +32,13 @@ The micro:bit has the following physical features:
 Supported Features
 ==================
 
-The bbc_microbit board configuration supports the following nRF51
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| NVIC      | on-chip    | nested vectored      |
-|           |            | interrupt controller |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial port          |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/bbc/microbit_v2/bbc_microbit_v2.yaml b/boards/bbc/microbit_v2/bbc_microbit_v2.yaml
index 5eb925efff6..81928e2c1ed 100644
--- a/boards/bbc/microbit_v2/bbc_microbit_v2.yaml
+++ b/boards/bbc/microbit_v2/bbc_microbit_v2.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 testing:
   ignore_tags:
diff --git a/boards/bbc/microbit_v2/doc/index.rst b/boards/bbc/microbit_v2/doc/index.rst
index 62c3cee2252..24fbaf5d2a3 100644
--- a/boards/bbc/microbit_v2/doc/index.rst
+++ b/boards/bbc/microbit_v2/doc/index.rst
@@ -33,29 +33,13 @@ The micro:bit-v2 has the following physical features:
 Supported Features
 ==================
 
-The bbc_microbit_v2 board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| NVIC      | on-chip    | nested vectored      |
-|           |            | interrupt controller |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial port          |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/bcdevices/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.yaml b/boards/bcdevices/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.yaml
index 6536b8a957f..74fa69a1cba 100644
--- a/boards/bcdevices/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.yaml
+++ b/boards/bcdevices/plt_demo_v2/blueclover_plt_demo_v2_nrf52832.yaml
@@ -6,7 +6,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 512
 supported:
diff --git a/boards/bcdevices/plt_demo_v2/doc/index.rst b/boards/bcdevices/plt_demo_v2/doc/index.rst
index 646e5c92025..cdab9ada052 100644
--- a/boards/bcdevices/plt_demo_v2/doc/index.rst
+++ b/boards/bcdevices/plt_demo_v2/doc/index.rst
@@ -41,40 +41,7 @@ Hardware
 Supported Features
 ==================
 
-The Blue Clover PLT Demo V2 board configuration supports the
-following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -105,6 +72,8 @@ NFC
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``blueclover_plt_demo_v2/nrf52832`` board configuration
 can be built and flashed in the usual way (see :ref:`build_an_application`
 and :ref:`application_run` for more details).
diff --git a/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0-pinctrl.dtsi b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0-pinctrl.dtsi
index dfc744b72e4..9cf1363ba22 100644
--- a/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0-pinctrl.dtsi
+++ b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0-pinctrl.dtsi
@@ -18,4 +18,12 @@
 		/* 0x14 is address of padconfig register of p8.22 and 14 is mux mode */
 		pinmux = <K3_PINMUX(0x14, PIN_INPUT, MUX_MODE_14)>;
 	};
+	i2c6_scl_default: i2c6_scl_default {
+		/* 0x1e0 is the address of padconfig register of p9.17 and 2 is mux mode */
+		pinmux = <K3_PINMUX(0x1d0, PIN_INPUT_PULLUP, MUX_MODE_2)>;
+	};
+	i2c6_sda_default: i2c6_sda_default {
+		/* 0x1dc is the address of padconfig register of p9.18 and 2 is mux mode */
+		pinmux = <K3_PINMUX(0x1e4, PIN_INPUT_PULLUP, MUX_MODE_2)>;
+	};
 };
diff --git a/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts
index 8c4c8f0e8e4..804abfd9566 100644
--- a/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts
+++ b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.dts
@@ -45,6 +45,12 @@
 	};
 };
 
+&i2c6 {
+	status = "okay";
+	pinctrl-0 = <&i2c6_scl_default &i2c6_sda_default>;
+	pinctrl-names = "default";
+};
+
 &uart2 {
 	status = "okay";
 	pinctrl-0 = <&uart2_tx_default &uart2_rx_default>;
diff --git a/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.yaml b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.yaml
index 0adaeddf82f..1bc51599e77 100644
--- a/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.yaml
+++ b/boards/beagle/beaglebone_ai64/beaglebone_ai64_j721e_main_r5f0_0.yaml
@@ -11,7 +11,7 @@ ram: 32
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - uart
+  - i2c
 vendor: beagle
diff --git a/boards/beagle/beaglebone_ai64/doc/index.rst b/boards/beagle/beaglebone_ai64/doc/index.rst
index d54775011db..3e62a1ad54a 100644
--- a/boards/beagle/beaglebone_ai64/doc/index.rst
+++ b/boards/beagle/beaglebone_ai64/doc/index.rst
@@ -44,9 +44,11 @@ The board configuration supports,
 +-----------+------------+-----------------------+
 | Interface | Controller | Driver/Component      |
 +===========+============+=======================+
-| UART      | on-chip    | serial port-polling   |
+| UART      | on-chip    | serial port-polling,  |
 |           |            | serial port-interrupt |
 +-----------+------------+-----------------------+
+| I2C       | on-chip    | i2c-polling           |
++-----------+------------+-----------------------+
 
 Other hardwares features are currently not supported.
 
diff --git a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.yaml b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.yaml
index cbe7f154814..989f7f8e2f0 100644
--- a/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.yaml
+++ b/boards/beagle/beagleconnect_freedom/beagleconnect_freedom.yaml
@@ -7,7 +7,6 @@ flash: 704
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/beagle/beagleconnect_freedom/doc/index.rst b/boards/beagle/beagleconnect_freedom/doc/index.rst
index 8bf3bf4e6e6..3fac0a1f08d 100644
--- a/boards/beagle/beagleconnect_freedom/doc/index.rst
+++ b/boards/beagle/beagleconnect_freedom/doc/index.rst
@@ -24,41 +24,7 @@ GPIO expander.
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PINMUX    | on-chip    | pinmux               |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| HWINFO    | on-chip    | hwinfo               |
-+-----------+------------+----------------------+
-| I2C       | off-chip   | OPT3001              |
-+-----------+------------+----------------------+
-| I2C       | off-chip   | HDC2010              |
-+-----------+------------+----------------------+
-| I2C       | off-chip   | BCF_BRIDGE_MCU       |
-+-----------+------------+----------------------+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | ieee802154           |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
diff --git a/boards/beagle/beagleplay/beagleplay_cc1352p7.yaml b/boards/beagle/beagleplay/beagleplay_cc1352p7.yaml
index 816b755471f..8a35e3700ed 100644
--- a/boards/beagle/beagleplay/beagleplay_cc1352p7.yaml
+++ b/boards/beagle/beagleplay/beagleplay_cc1352p7.yaml
@@ -7,7 +7,6 @@ flash: 704
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - uart
diff --git a/boards/beagle/beagleplay/doc/beagleplay_cc1352p7.rst b/boards/beagle/beagleplay/doc/beagleplay_cc1352p7.rst
index 24665eafce1..7f38c4589c7 100644
--- a/boards/beagle/beagleplay/doc/beagleplay_cc1352p7.rst
+++ b/boards/beagle/beagleplay/doc/beagleplay_cc1352p7.rst
@@ -55,23 +55,7 @@ BeaglePlay ARM Cortex-A53 CPUs typically run Linux, while the CC1352P7 Cortex-M4
 Supported Features
 ==================
 
-The ``beagleplay/cc1352p7`` board target supports the following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PINMUX    | on-chip    | pinmux               |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | ieee802154           |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -137,6 +121,8 @@ CC1352 reset is connected to AM62 GPIO0_14.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/beagle/beagley_ai/Kconfig.beagley_ai b/boards/beagle/beagley_ai/Kconfig.beagley_ai
new file mode 100644
index 00000000000..fb4ca252ea1
--- /dev/null
+++ b/boards/beagle/beagley_ai/Kconfig.beagley_ai
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+#	Andrew Davis <afd@ti.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_BEAGLEY_AI
+	select SOC_J722S_MAIN_R5F0_0 if BOARD_BEAGLEY_AI_J722S_MAIN_R5F0_0
+	select SOC_J722S_MCU_R5F0_0 if BOARD_BEAGLEY_AI_J722S_MCU_R5F0_0
diff --git a/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0-pinctrl.dtsi b/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0-pinctrl.dtsi
new file mode 100644
index 00000000000..0ffa8f91073
--- /dev/null
+++ b/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0-pinctrl.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ *	Andrew Davis <afd@ti.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
+
+&pinctrl {
+	uart1_rx_default: uart1_rx_default {
+		/* (C27) MCASP0_AFSR.UART1_RXD */
+		pinmux = <K3_PINMUX(0x01ac, PIN_INPUT, MUX_MODE_2)>;
+	};
+
+	uart1_tx_default: uart1_tx_default {
+		/* (F24) MCASP0_ACLKR.UART1_TXD */
+		pinmux = <K3_PINMUX(0x01b0, PIN_OUTPUT, MUX_MODE_2)>;
+	};
+};
diff --git a/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0.dts b/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0.dts
new file mode 100644
index 00000000000..5bf213b6444
--- /dev/null
+++ b/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0.dts
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ *	Andrew Davis <afd@ti.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <ti/j722s_main_r5.dtsi>
+#include "beagley_ai_j722s_main_r5f0_0-pinctrl.dtsi"
+#include <freq.h>
+
+/ {
+	model = "BeagleBoard.org BeagleY-AI";
+	compatible = "beagle,beagley-ai";
+
+	chosen {
+		zephyr,sram = &atcm;
+		zephyr,console = &uart1;
+	};
+
+	cpus {
+		cpu@0 {
+			status = "okay";
+		};
+	};
+
+	ddr0: memory@a2000000 {
+		compatible = "mmio-sram";
+		reg = <0xa2000000 DT_SIZE_M(1)>;
+	};
+
+	rsc_table: memory@a2100000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0xa2100000 DT_SIZE_M(1)>;
+		zephyr,memory-region = "RSC_TABLE";
+	};
+
+	ddr1: memory@a2200000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0xa2200000 DT_SIZE_M(14)>;
+		zephyr,memory-region = "DRAM";
+	};
+};
+
+&uart1 {
+	status = "okay";
+	pinctrl-0 = <&uart1_tx_default &uart1_rx_default>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+};
+
+&systick_timer {
+	status = "okay";
+};
diff --git a/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0.yaml b/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0.yaml
new file mode 100644
index 00000000000..40986711f15
--- /dev/null
+++ b/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+# 	Andrew Davis <afd@ti.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: beagley_ai/j722s/main_r5f0_0
+name: BeagleY-AI MAIN domain R5F Core 0
+type: mcu
+arch: arm
+ram: 32
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - uart
+vendor: beagle
diff --git a/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0_defconfig b/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0_defconfig
new file mode 100644
index 00000000000..a8cf44f32db
--- /dev/null
+++ b/boards/beagle/beagley_ai/beagley_ai_j722s_main_r5f0_0_defconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+#	Andrew Davis <afd@ti.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Zephyr Kernel Configuration
+CONFIG_XIP=n
+
+# Serial Driver
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0-pinctrl.dtsi b/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0-pinctrl.dtsi
new file mode 100644
index 00000000000..0ffa8f91073
--- /dev/null
+++ b/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0-pinctrl.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ *	Andrew Davis <afd@ti.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
+
+&pinctrl {
+	uart1_rx_default: uart1_rx_default {
+		/* (C27) MCASP0_AFSR.UART1_RXD */
+		pinmux = <K3_PINMUX(0x01ac, PIN_INPUT, MUX_MODE_2)>;
+	};
+
+	uart1_tx_default: uart1_tx_default {
+		/* (F24) MCASP0_ACLKR.UART1_TXD */
+		pinmux = <K3_PINMUX(0x01b0, PIN_OUTPUT, MUX_MODE_2)>;
+	};
+};
diff --git a/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts b/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts
new file mode 100644
index 00000000000..e2957226a66
--- /dev/null
+++ b/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.dts
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ *	Andrew Davis <afd@ti.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <ti/j722s_mcu_r5.dtsi>
+#include "beagley_ai_j722s_mcu_r5f0_0-pinctrl.dtsi"
+#include <freq.h>
+
+/ {
+	model = "BeagleBoard.org BeagleY-AI";
+	compatible = "beagle,beagley-ai";
+
+	chosen {
+		zephyr,sram = &atcm;
+		zephyr,console = &uart1;
+	};
+
+	cpus {
+		cpu@0 {
+			status = "okay";
+		};
+	};
+
+	ddr0: memory@a1000000 {
+		compatible = "mmio-sram";
+		reg = <0xa1000000 DT_SIZE_M(1)>;
+	};
+
+	rsc_table: memory@a1100000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0xa1100000 DT_SIZE_M(1)>;
+		zephyr,memory-region = "RSC_TABLE";
+	};
+
+	ddr1: memory@a1200000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0xa1200000 DT_SIZE_M(14)>;
+		zephyr,memory-region = "DRAM";
+	};
+};
+
+&uart1 {
+	status = "okay";
+	pinctrl-0 = <&uart1_tx_default &uart1_rx_default>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+};
+
+&systick_timer {
+	status = "okay";
+};
diff --git a/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.yaml b/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.yaml
new file mode 100644
index 00000000000..665814f9d53
--- /dev/null
+++ b/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+# 	Andrew Davis <afd@ti.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: beagley_ai/j722s/mcu_r5f0_0
+name: BeagleY-AI MCU domain R5F Core 0
+type: mcu
+arch: arm
+ram: 32
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - uart
+vendor: beagle
diff --git a/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0_defconfig b/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0_defconfig
new file mode 100644
index 00000000000..a8cf44f32db
--- /dev/null
+++ b/boards/beagle/beagley_ai/beagley_ai_j722s_mcu_r5f0_0_defconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+#	Andrew Davis <afd@ti.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Zephyr Kernel Configuration
+CONFIG_XIP=n
+
+# Serial Driver
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/beagle/beagley_ai/board.yml b/boards/beagle/beagley_ai/board.yml
new file mode 100644
index 00000000000..af83769160e
--- /dev/null
+++ b/boards/beagle/beagley_ai/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: beagley_ai
+  full_name: BeagleY-AI
+  vendor: beagle
+  socs:
+  - name: j722s
diff --git a/boards/beagle/beagley_ai/doc/assets/beagley_ai.webp b/boards/beagle/beagley_ai/doc/assets/beagley_ai.webp
new file mode 100644
index 00000000000..f943829c710
Binary files /dev/null and b/boards/beagle/beagley_ai/doc/assets/beagley_ai.webp differ
diff --git a/boards/beagle/beagley_ai/doc/index.rst b/boards/beagle/beagley_ai/doc/index.rst
new file mode 100644
index 00000000000..6e1e6ca7e7e
--- /dev/null
+++ b/boards/beagle/beagley_ai/doc/index.rst
@@ -0,0 +1,134 @@
+.. zephyr:board:: beagley_ai
+
+Overview
+********
+
+BeagleY-AI is a computational platform powered by TI AM67A (J722S) SoC, which is
+targeted for automotive applications.
+
+Hardware
+********
+BeagleY-AI is powered by TI AM67A (J722S) SoC, which has two domains (Main,
+MCU). This document gives overview of Zephyr running on both Cortex R5.
+
+L1 Memory System
+----------------
+BeagleY-AI defaults to single-core mode for the R5 subsystem. Changes in that
+will impact the L1 memory system configuration.
+
+* 32KB instruction cache
+* 32KB data cache
+* 64KB tightly-coupled memory (TCM)
+  * 32KB TCMA
+  * 32KB TCMB
+
+Region Address Translation
+--------------------------
+The RAT module performs a region based address translation. It translates a
+32-bit input address into a 36-bit output address. Any input transaction that
+starts inside of a programmed region will have its address translated, if the
+region is enabled.
+
+VIM Interrupt Controller
+------------------------
+The VIM aggregates device interrupts and sends them to the R5F CPU(s). The VIM
+module supports 512 interrupt inputs per R5F core. Each interrupt can be either
+a level or a pulse (both active-high). The VIM has two interrupt outputs per core
+IRQ and FIQ.
+
+Supported Features
+******************
+The board configuration supports a console UART via the HAT header pins. Future
+versions will also support a console over RPmsg.
+
++-----------+------------+-----------------------+
+| Interface | Controller | Driver/Component      |
++===========+============+=======================+
+| UART      | on-chip    | serial port-polling   |
+|           |            | serial port-interrupt |
++-----------+------------+-----------------------+
+
+Other hardware features are currently not supported.
+
+The default configuration can be found in the defconfig file.
+
+Future configurations will add support for GPIO, I2C, SPI, etc.
+
+Running Zephyr
+**************
+
+The AM67A does not have a separate flash for the R5 core. Because of this
+an A53 core has to load the program for the R5 core to the right memory
+address, set the PC and start the processor.
+This can be done from Linux on the A53 core via remoteproc.
+
+This is the memory mapping from A53 to the memory usable by the R5. Note that
+the R5 core always sees its local TCMA at address 0x00000000 and its TCMB0
+at address 0x41010000.
+
+The A53 Linux configuration allocates a region in DDR that is shared with
+the R5. The amount of the allocation can be changed in the Linux device tree.
+Note that BeagleY-AI has 4GB of DDR.
+
++-------------------+---------------+--------------+--------+
+| Region            | Addr from A53 | MAIN R5F     | Size   |
++===================+===============+==============+========+
+| ATCM              | 0x0078400000  | 0x0000000000 | 32KB   |
++-------------------+---------------+--------------+--------+
+| BTCM              | 0x0078500000  | 0x0041010000 | 32KB   |
++-------------------+---------------+--------------+--------+
+| DDR Shared Region | 0x00A2000000  | 0x00A2000000 | 16MB   |
++-------------------+---------------+--------------+--------+
+
++-------------------+---------------+--------------+--------+
+| Region            | Addr from A53 | MCU R5F      | Size   |
++===================+===============+==============+========+
+| ATCM              | 0x0079000000  | 0x0000000000 | 32KB   |
++-------------------+---------------+--------------+--------+
+| BTCM              | 0x0079020000  | 0x0041010000 | 32KB   |
++-------------------+---------------+--------------+--------+
+| DDR Shared Region | 0x00A1000000  | 0x00A1000000 | 16MB   |
++-------------------+---------------+--------------+--------+
+
+Steps to run the image
+----------------------
+Here is an example for the :zephyr:code-sample:`hello_world` application
+targeting the MAIN domain Cortex R5F on BeagleY-AI:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: beagley_ai/j722s/main_r5f0_0
+   :goals: build
+
+For the MCU domain Cortex R5F on BeagleY-AI:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: beagley_ai/j722s/mcu_r5f0_0
+   :goals: build
+
+To load the image:
+
+| Copy Zephyr image to the /lib/firmware/ directory.
+| ``cp build/zephyr/zephyr.elf /lib/firmware/``
+|
+| Ensure the Core is not running.
+| ``echo stop > /dev/remoteproc/am67a-{main,mcu}-r5f0_0/state``
+|
+| Configuring the image name to the remoteproc module.
+| ``echo zephyr.elf > /dev/remoteproc/am67a-{main,mcu}-r5f0_0/firmware``
+|
+| Once the image name is configured, send the start command.
+| ``echo start > /dev/remoteproc/am67a-{main,mcu}-r5f0_0/state``
+
+Console
+-------
+The Zephyr on BeagleY-AI Cortex-R5F uses UART 1 (HAT pins 8-TX, 10-RX)
+as console.
+
+References
+**********
+* `BeagleY-AI Homepage <https://beagley.ai>`_
+* `AM67A TRM <https://www.ti.com/lit/zip/sprujb3>`_
+* `Pinout guide <https://pinout.beagley.ai/>`_
+* `Documentation <https://docs.beagleboard.org/latest/boards/beagley/ai>`_
diff --git a/boards/beagle/pocketbeagle_2/Kconfig.pocketbeagle_2 b/boards/beagle/pocketbeagle_2/Kconfig.pocketbeagle_2
new file mode 100644
index 00000000000..b154f4e2e4e
--- /dev/null
+++ b/boards/beagle/pocketbeagle_2/Kconfig.pocketbeagle_2
@@ -0,0 +1,8 @@
+# BeagleBoard.org PocketBeagle 2
+#
+# Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_POCKETBEAGLE_2
+	select SOC_AM6232_M4 if BOARD_POCKETBEAGLE_2_AM6232_M4
diff --git a/boards/beagle/pocketbeagle_2/board.cmake b/boards/beagle/pocketbeagle_2/board.cmake
new file mode 100644
index 00000000000..d1f7b9aff41
--- /dev/null
+++ b/boards/beagle/pocketbeagle_2/board.cmake
@@ -0,0 +1,10 @@
+# BeagleBoard.org PocketBeagle 2
+#
+# Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_AM6232_M4)
+  board_runner_args(openocd "--no-init" "--no-halt" "--no-targets" "--gdb-client-port=3339")
+  include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+endif()
diff --git a/boards/beagle/pocketbeagle_2/board.yml b/boards/beagle/pocketbeagle_2/board.yml
new file mode 100644
index 00000000000..03f54cde3bb
--- /dev/null
+++ b/boards/beagle/pocketbeagle_2/board.yml
@@ -0,0 +1,12 @@
+board:
+  name: pocketbeagle_2
+  full_name: PocketBeagle 2
+  vendor: beagle
+  socs:
+    - name: am6232
+  revision:
+    format: custom
+    exact: true
+    default: "A0"
+    revisions:
+      - name: "A0"
diff --git a/boards/beagle/pocketbeagle_2/doc/img/pocketbeagle_2.webp b/boards/beagle/pocketbeagle_2/doc/img/pocketbeagle_2.webp
new file mode 100644
index 00000000000..34ecf2d1e00
Binary files /dev/null and b/boards/beagle/pocketbeagle_2/doc/img/pocketbeagle_2.webp differ
diff --git a/boards/beagle/pocketbeagle_2/doc/index.rst b/boards/beagle/pocketbeagle_2/doc/index.rst
new file mode 100644
index 00000000000..ecd9542919c
--- /dev/null
+++ b/boards/beagle/pocketbeagle_2/doc/index.rst
@@ -0,0 +1,121 @@
+.. zephyr:board:: pocketbeagle_2
+
+Overview
+********
+
+PocketBeagle 2 is a computational platform powered by TI AM62x SoC (there are two
+revisions, AM6232 and AM6254).
+
+The board configuration provides support for the ARM Cortex-M4F MCU core.
+
+See the `PocketBeagle 2 Product Page`_ for details.
+
+Hardware
+********
+PocketBeagle 2 features the TI AM62x SoC based around an Arm Cortex-A53 multicore
+cluster with an Arm Cortex-M4F microcontroller, Imagination Technologies AXE-1-16
+graphics processor (from revision A1) and TI programmable real-time unit subsystem
+microcontroller cluster coprocessors.
+
+Zephyr is ported to run on the M4F core and the following listed hardware
+specifications are used:
+
+- Low-power ARM Cortex-M4F
+- Memory
+
+   - 256KB of SRAM
+   - 512MB of DDR4
+
+Currently supported PocketBeagle 2 revisions:
+
+- A0: Comes wth SOC AM6232
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Devices
+========
+System Clock
+------------
+
+This board configuration uses a system clock frequency of 400 MHz.
+
+DDR RAM
+-------
+
+The board has 512MB of DDR RAM available. This board configuration
+allocates Zephyr 4kB of RAM (only for resource table: 0x9CC00000 to 0x9CC00400).
+
+Serial Port
+-----------
+
+This board configuration uses a single serial communication channel with the
+MCU domain UART (MCU_UART0, i.e. P2.05 as RX and P2.07 as TX).
+
+SD Card
+*******
+
+Download BeagleBoard.org's official `BeagleBoard Imaging Utility`_ to create bootable
+SD-card with the Linux distro image. This will boot Linux on the A53 application
+cores. These cores will then load the Zephyr binary on the M4 core using remoteproc.
+
+Flashing
+********
+
+The board supports remoteproc using the OpenAMP resource table.
+
+The testing requires the binary to be copied to the SD card to allow the A53 cores to load it while booting using remoteproc.
+
+To test the M4F core, we build the :zephyr:code-sample:`hello_world` sample with the following command.
+
+.. zephyr-app-commands::
+   :board: pocketbeagle_2/am6232/m4
+   :zephyr-app: samples/hello_world
+   :goals: build
+
+This builds the program and the binary is present in the :file:`build/zephyr` directory as
+:file:`zephyr.elf`.
+
+We now copy this binary onto the SD card in the :file:`/lib/firmware` directory and name it as
+:file:`am62-mcu-m4f0_0-fw`.
+
+.. code-block:: console
+
+   # Mount the SD card at sdcard for example
+   sudo mount /dev/sdX sdcard
+   # copy the elf to the /lib/firmware directory
+   sudo cp --remove-destination zephyr.elf sdcard/lib/firmware/am62-mcu-m4f0_0-fw
+
+The SD card can now be used for booting. The binary will now be loaded onto the M4F core on boot.
+
+The binary will run and print Hello world to the MCU_UART0 port.
+
+Debugging
+*********
+
+The board supports debugging M4 core from the A53 cores running Linux. Since the target needs
+superuser privilege, openocd needs to be launched seperately for now:
+
+.. code-block:: console
+
+   sudo openocd -f board/ti_am625_swd_native.cfg
+
+
+Start debugging
+
+.. zephyr-app-commands::
+   :goals: debug
+
+References
+**********
+
+* `PocketBeagle 2 Product Page`_
+* `Documentation <https://docs.beagleboard.org/boards/pocketbeagle-2/index.html>`_
+
+.. _PocketBeagle 2 Product Page:
+   https://www.beagleboard.org/boards/pocketbeagle-2
+
+.. _BeagleBoard Imaging Utility:
+   https://github.com/beagleboard/bb-imager-rs/releases
diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4-pinctrl.dtsi b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4-pinctrl.dtsi
new file mode 100644
index 00000000000..7f54984345a
--- /dev/null
+++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4-pinctrl.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
+
+&pinctrl {
+	mcu_uart0_rx_default: mcu_uart0_rx_default {
+		pinmux = <K3_PINMUX(0x0014, PIN_INPUT, MUX_MODE_0)>;
+	};
+
+	mcu_uart0_tx_default: mcu_uart0_tx_default {
+		pinmux = <K3_PINMUX(0x0018, PIN_OUTPUT, MUX_MODE_0)>;
+	};
+};
diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.dts b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.dts
new file mode 100644
index 00000000000..6b1c256976b
--- /dev/null
+++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.dts
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <ti/am62x_m4.dtsi>
+#include "pocketbeagle_2_am6232_m4-pinctrl.dtsi"
+
+/ {
+	model = "BeagleBoard.org PocketBeagle 2";
+	compatible = "beagle,pocketbeagle_2_m4";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,ipc = &ipc0;
+		zephyr,ipc_shm = &ddr0;
+		zephyr,sram1 = &ddr1;
+	};
+
+	cpus {
+		cpu@0 {
+			status = "okay";
+			clock-frequency = <400000000>;
+		};
+	};
+
+	ddr0: memory@9cb00000 {
+		compatible = "mmio-sram";
+		reg = <0x9cb00000 DT_SIZE_M(1)>;
+	};
+
+	rsc_table: memory@9cc00000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x9cc00000 DT_SIZE_K(4)>;
+		zephyr,memory-region = "RSC_TABLE";
+	};
+
+	ddr1: memory@9cc01000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x9cc01000 (DT_SIZE_M(15) - DT_SIZE_K(4))>;
+		zephyr,memory-region = "DDR";
+	};
+
+	ipc0: ipc {
+		compatible = "zephyr,mbox-ipm";
+		mboxes = <&mbox0 0>, <&mbox0 1>;
+		mbox-names = "tx", "rx";
+	};
+};
+
+&uart0 {
+	current-speed = <115200>;
+	pinctrl-0 = <&mcu_uart0_rx_default &mcu_uart0_tx_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.yaml b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.yaml
new file mode 100644
index 00000000000..fc258c2e383
--- /dev/null
+++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4.yaml
@@ -0,0 +1,10 @@
+identifier: pocketbeagle_2/am6232/m4
+name: BeagleBoard.org PocketBeagle 2
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+ram: 192
+vendor: beagle
+supported:
+  - uart
diff --git a/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4_defconfig b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4_defconfig
new file mode 100644
index 00000000000..02a9f623a27
--- /dev/null
+++ b/boards/beagle/pocketbeagle_2/pocketbeagle_2_am6232_m4_defconfig
@@ -0,0 +1,18 @@
+# BeagleBoard.org PocketBeagle 2
+#
+# Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Platform Configuration
+CONFIG_CORTEX_M_SYSTICK=y
+
+# Zephyr Kernel Configuration
+CONFIG_XIP=n
+
+# Serial Driver
+CONFIG_SERIAL=y
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/beagle/pocketbeagle_2/revision.cmake b/boards/beagle/pocketbeagle_2/revision.cmake
new file mode 100644
index 00000000000..f7698f24bf3
--- /dev/null
+++ b/boards/beagle/pocketbeagle_2/revision.cmake
@@ -0,0 +1,10 @@
+set(BOARD_REVISIONS "A0")
+
+# If BOARD_REVISION not set, use the default revision
+if(NOT DEFINED BOARD_REVISION)
+  set(BOARD_REVISION ${LIST_BOARD_REVISION_DEFAULT})
+endif()
+
+if(NOT BOARD_REVISION IN_LIST BOARD_REVISIONS)
+  message(FATAL_ERROR "${BOARD_REVISION} is not a valid revision for PocketBeagle 2. Accepted revisions: ${BOARD_REVISIONS}")
+endif()
diff --git a/boards/beagle/pocketbeagle_2/support/openocd.cfg b/boards/beagle/pocketbeagle_2/support/openocd.cfg
new file mode 100644
index 00000000000..f0cff3f9e2d
--- /dev/null
+++ b/boards/beagle/pocketbeagle_2/support/openocd.cfg
@@ -0,0 +1,7 @@
+# BeagleBoard.org PocketBeagle 2
+#
+# Copyright (c) 2025 Ayush Singh, BeagleBoard.org Foundation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+source [find board/ti_am625_swd_native.cfg]
diff --git a/boards/blues/cygnet/Kconfig.cygnet b/boards/blues/cygnet/Kconfig.cygnet
new file mode 100644
index 00000000000..f907d27024b
--- /dev/null
+++ b/boards/blues/cygnet/Kconfig.cygnet
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Blues
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_CYGNET
+	select SOC_STM32L433XX
diff --git a/boards/blues/cygnet/Kconfig.defconfig b/boards/blues/cygnet/Kconfig.defconfig
new file mode 100644
index 00000000000..898cdfcf29a
--- /dev/null
+++ b/boards/blues/cygnet/Kconfig.defconfig
@@ -0,0 +1,12 @@
+# STM32L433CC Cygnet board configuration
+
+# Copyright (c) 2025 Blues
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_CYGNET
+
+config SPI_STM32_INTERRUPT
+	default y
+	depends on SPI
+
+endif # BOARD_CYGNET
diff --git a/boards/blues/cygnet/board.cmake b/boards/blues/cygnet/board.cmake
new file mode 100644
index 00000000000..3f2cb762859
--- /dev/null
+++ b/boards/blues/cygnet/board.cmake
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# keep first
+board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
+board_runner_args(jlink "--device=STM32L433CC" "--speed=4000")
+
+# keep first
+include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/blues/cygnet/board.yml b/boards/blues/cygnet/board.yml
new file mode 100644
index 00000000000..4341ee22c8e
--- /dev/null
+++ b/boards/blues/cygnet/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: cygnet
+  full_name: Cygnet
+  vendor: blues
+  socs:
+    - name: stm32l433xx
diff --git a/boards/blues/cygnet/cygnet.dts b/boards/blues/cygnet/cygnet.dts
new file mode 100644
index 00000000000..00fd5282bd2
--- /dev/null
+++ b/boards/blues/cygnet/cygnet.dts
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2025 Blues
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/l4/stm32l433Xc.dtsi>
+#include <st/l4/stm32l433c(b-c)ux-pinctrl.dtsi>
+#include "feather_connector.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "Blues Cygnet";
+	compatible = "blues,cygnet";
+
+	chosen {
+		zephyr,console = &lpuart1;
+		zephyr,shell-uart = &lpuart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		user_led: led_0 {
+			gpios = <&gpioa 8 GPIO_ACTIVE_HIGH>;
+			label = "User LED";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		user_button: button {
+			gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
+			label = "User Button";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	aliases {
+		led0 = &user_led;
+		sw0 = &user_button;
+	};
+};
+
+&clk_lsi {
+	status = "okay";
+};
+
+&clk_hsi {
+	status = "okay";
+};
+
+&pll {
+	div-m = <1>;
+	mul-n = <20>;
+	div-p = <7>;
+	div-q = <2>;
+	div-r = <4>;
+	clocks = <&clk_hsi>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(80)>;
+	ahb-prescaler = <1>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+};
+
+&lpuart1 {
+	pinctrl-0 = <&lpuart1_tx_pb11 &lpuart1_rx_pb10>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&usart1 {
+	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+};
+
+&spi1 {
+	pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pb5>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpiob 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb7>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	status = "okay";
+};
+
+&timers2 {
+	status = "okay";
+
+	pwm2: pwm {
+		status = "okay";
+		pinctrl-0 = <&tim2_ch1_pa0>;
+		pinctrl-names = "default";
+	};
+};
+
+&can1 {
+	pinctrl-0 = <&can1_rx_pb8 &can1_tx_pb9>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&rtc {
+	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
+		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
+	status = "okay";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/*
+		 * Reserve the final 16 KiB for file system partition
+		 */
+		storage_partition: partition@3c000 {
+			label = "storage";
+			reg = <0x0003c000 DT_SIZE_K(16)>;
+		};
+	};
+};
diff --git a/boards/blues/cygnet/cygnet.yaml b/boards/blues/cygnet/cygnet.yaml
new file mode 100644
index 00000000000..88af7f3d91d
--- /dev/null
+++ b/boards/blues/cygnet/cygnet.yaml
@@ -0,0 +1,22 @@
+identifier: cygnet
+name: Blues Cygnet
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+ram: 64
+flash: 256
+supported:
+  - nvs
+  - can
+  - spi
+  - i2c
+  - pwm
+  - gpio
+  - counter
+  - feather_serial
+  - feather_i2c
+  - feather_spi
+vendor: blues
diff --git a/boards/blues/cygnet/cygnet_defconfig b/boards/blues/cygnet/cygnet_defconfig
new file mode 100644
index 00000000000..674354645c1
--- /dev/null
+++ b/boards/blues/cygnet/cygnet_defconfig
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/blues/cygnet/doc/img/cygnet-pinout.webp b/boards/blues/cygnet/doc/img/cygnet-pinout.webp
new file mode 100644
index 00000000000..9499bcaa82e
Binary files /dev/null and b/boards/blues/cygnet/doc/img/cygnet-pinout.webp differ
diff --git a/boards/blues/cygnet/doc/img/cygnet.webp b/boards/blues/cygnet/doc/img/cygnet.webp
new file mode 100644
index 00000000000..a1355669cb2
Binary files /dev/null and b/boards/blues/cygnet/doc/img/cygnet.webp differ
diff --git a/boards/blues/cygnet/doc/index.rst b/boards/blues/cygnet/doc/index.rst
new file mode 100644
index 00000000000..8283eb15db6
--- /dev/null
+++ b/boards/blues/cygnet/doc/index.rst
@@ -0,0 +1,204 @@
+.. zephyr:board:: cygnet
+
+Overview
+********
+
+The Blues Cygnet board features an ARM Cortex-M4 based STM32L433CC MCU
+with a wide range of connectivity support and configurations. Here are
+some highlights of the Cygnet board:
+
+- STM32L4 microcontroller in LQFP48 package
+- Adafruit Feather connector
+- User LED
+- User push-button
+- USB Type-C connector
+
+More information about the board can be found at the `Blues Cygnet website`_.
+
+Hardware
+********
+
+The STM32L433CC SoC provides the following hardware IPs:
+
+- Ultra-low-power with FlexPowerControl (down to 28 nA Standby mode and 84
+  |micro| A/MHz run mode)
+- Core: ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU, frequency up to 80 MHz,
+  100DMIPS/1.25DMIPS/MHz (Dhrystone 2.1)
+- Clock Sources:
+
+  - 32 kHz crystal oscillator for RTC (LSE)
+  - Internal 16 MHz factory-trimmed RC ( |plusminus| 1%)
+  - Internal low-power 32 kHz RC ( |plusminus| 5%)
+  - Internal multispeed 100 kHz to 48 MHz oscillator, auto-trimmed by
+    LSE (better than |plusminus| 0.25 % accuracy)
+  - 2 PLLs for system clock, USB, audio, ADC
+
+- RTC with HW calendar, alarms and calibration
+- 11x timers:
+
+  - 1x 16-bit advanced motor-control
+  - 1x 32-bit and 2x 16-bit general purpose
+  - 2x 16-bit basic
+  - 2x low-power 16-bit timers (available in Stop mode)
+  - 2x watchdogs
+  - SysTick timer
+
+- Up to 21 fast I/Os, most 5 V-tolerant
+- Memories
+
+  - Up to 256 KB single bank Flash, proprietary code readout protection
+  - 64 KB of SRAM including 16 KB with hardware parity check
+
+- Rich analog peripherals (independent supply)
+
+  - 1x 12-bit ADC 5 MSPS, up to 16-bit with hardware oversampling, 200
+    |micro| A/MSPS
+  - 2x 12-bit DAC output channels, low-power sample and hold
+  - 1x operational amplifiers with built-in PGA
+  - 2x ultra-low-power comparators
+
+- 17x communication interfaces
+
+  - USB 2.0 full-speed crystal less solution with LPM and BCD
+  - 1x SAI (serial audio interface)
+  - 3x I2C FM+(1 Mbit/s), SMBus/PMBus
+  - 4x USARTs (ISO 7816, LIN, IrDA, modem)
+  - 1x LPUART (Stop 2 wake-up)
+  - 3x SPIs (and 1x Quad SPI)
+  - CAN (2.0B Active)
+
+- 14-channel DMA controller
+- True random number generator
+- CRC calculation unit, 96-bit unique ID
+- Development support: serial wire debug (SWD), JTAG, Embedded Trace Macrocell*
+
+More information about STM32L433CC can be found here:
+
+- `STM32L433CC on www.st.com`_
+- `STM32L432 reference manual`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+.. note:: CAN feature requires a CAN transceiver.
+
+Connections and IOs
+===================
+
+The Cygnet board has 6 GPIO controllers. These controllers are responsible for pin muxing,
+input/output, pull-up, etc.
+
+Available pins
+--------------
+.. image:: img/cygnet-pinout.webp
+   :align: center
+   :alt: Cygnet Pinout
+
+For more details please refer to `Blues Cygnet User Manual`_.
+
+Default Zephyr Peripheral Mapping
+---------------------------------
+
+- LPUART_1_TX : PB11
+- LPUART_1_RX : PB10
+- UART_1_TX : PA9
+- UART_1_RX : PA10
+- I2C_1_SCL : PB6
+- I2C_1_SDA : PB7
+- PWM_2_CH1 : PA0
+- SPI_1: SCK/MISO/MOSI : PA5/PA6/PB5
+
+System Clock
+------------
+
+The Cygnet board System Clock could be driven by internal or external oscillator,
+as well as main PLL clock. By default System clock is driven by PLL clock at 80MHz,
+driven by 16MHz high speed internal oscillator.
+
+Serial Port
+-----------
+
+The Cygnet board has 4 U(S)ARTs and 1 LPUART. The Zephyr console output is assigned
+to LPUART1. Default settings are 115200 8N1.
+
+
+Programming and Debugging
+*************************
+
+The Cygnet board requires an ST-LINK embedded debug tool in order to be programmed and debugged.
+
+Applications for the ``cygnet`` board configuration can be built and
+flashed in the usual way (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Flashing
+========
+
+The board is configured to be flashed using west `STM32CubeProgrammer`_ runner,
+so its :ref:`installation <stm32cubeprog-flash-host-tools>` is required.
+
+Alternatively, OpenOCD or JLink can also be used to flash the board using
+the ``--runner`` (or ``-r``) option:
+
+.. code-block:: console
+
+   $ west flash --runner openocd
+   $ west flash --runner jlink
+
+Flashing an application to Cygnet
+---------------------------------
+
+Connect the Cygnet to the ST-LINK debugger, then run a serial host program to connect with your Cygnet board.
+
+.. code-block:: console
+
+   $ picocom /dev/ttyACM0 -b 115200
+
+Now build and flash an application. Here is an example for
+:zephyr:code-sample:`hello_world`.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: cygnet
+   :goals: build flash
+
+You should see the following message on the console:
+
+.. code-block:: console
+
+   $ Hello World! cygnet
+
+
+Debugging
+=========
+
+You can debug an application in the usual way.  Here is an example for the
+:zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: cygnet
+   :maybe-skip-config:
+   :goals: debug
+
+References
+**********
+
+.. target-notes::
+
+.. _Blues Cygnet website:
+   https://www.blues.dev/
+
+.. _Blues Cygnet User Manual:
+   https://dev.blues.io/feather-mcus/cygnet/cygnet-introduction/
+
+.. _STM32L433CC on www.st.com:
+   https://www.st.com/en/microcontrollers-microprocessors/stm32l433cc.html
+
+.. _STM32L432 reference manual:
+   https://www.st.com/resource/en/reference_manual/dm00151940.pdf
+
+.. _STM32CubeProgrammer:
+   https://www.st.com/en/development-tools/stm32cubeprog.html
diff --git a/boards/blues/cygnet/feather_connector.dtsi b/boards/blues/cygnet/feather_connector.dtsi
new file mode 100644
index 00000000000..da08fb45884
--- /dev/null
+++ b/boards/blues/cygnet/feather_connector.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2025 Blues Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	feather_header: connector {
+		compatible = "adafruit-feather-header";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpioa 0 0>,	/* A0 */
+					<1 0 &gpioa 1 0>,	/* A1 */
+					<2 0 &gpioa 2 0>,	/* A2 */
+					<3 0 &gpioa 3 0>,	/* A3 */
+					<4 0 &gpiob 1 0>,	/* A4 */
+					<5 0 &gpioa 7 0>,	/* A5 */
+					<6 0 &gpioa 5 0>,	/* SCK */
+					<7 0 &gpiob 5 0>,	/* MOSI */
+					<8 0 &gpioa 6 0>,	/* MISO */
+					<9 0 &gpioa 10 0>,	/* RX */
+					<10 0 &gpioa 9 0>,	/* TX */
+					<11 0 &gpiob 1 0>,	/* D4 */
+					<12 0 &gpiob 7 0>,	/* SDA */
+					<13 0 &gpiob 6 0>,	/* SCL */
+					<14 0 &gpiob 8 0>,	/* D5 */
+					<15 0 &gpiob 9 0>,	/* D6 */
+					<16 0 &gpiob 14 0>,	/* D9 */
+					<17 0 &gpiob 13 0>,	/* D10 */
+					<18 0 &gpiob 0 0>,	/* D11 */
+					<19 0 &gpiob 15 0>,	/* D12 */
+					<20 0 &gpiob 4 0>;	/* D13 */
+	};
+};
+
+feather_serial: &usart1 {};
+feather_i2c: &i2c1 {};
+feather_spi: &spi1 {};
diff --git a/boards/blues/cygnet/support/openocd.cfg b/boards/blues/cygnet/support/openocd.cfg
new file mode 100644
index 00000000000..cd566c1fa1c
--- /dev/null
+++ b/boards/blues/cygnet/support/openocd.cfg
@@ -0,0 +1,7 @@
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+source [find target/stm32l4x.cfg]
+
+reset_config srst_only
diff --git a/boards/blues/swan_r5/doc/index.rst b/boards/blues/swan_r5/doc/index.rst
index 51212bd4c64..0c2c796abd4 100644
--- a/boards/blues/swan_r5/doc/index.rst
+++ b/boards/blues/swan_r5/doc/index.rst
@@ -85,37 +85,7 @@ More information about Swan can be found here:
 Supported Features
 ==================
 
-The Zephyr Swan board configuration supports the following
-hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/blues/swan_r5/swan_r5_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -189,6 +159,8 @@ assigned to LPUART.  Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Connect Swan to your host computer using the USB port.
 Then build and flash an application. Here is an example for the
 :zephyr:code-sample:`hello_world` application.
diff --git a/boards/blues/swan_r5/swan_r5.yaml b/boards/blues/swan_r5/swan_r5.yaml
index 5e0efea6540..7f9791b19d2 100644
--- a/boards/blues/swan_r5/swan_r5.yaml
+++ b/boards/blues/swan_r5/swan_r5.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - pwm
   - spi
diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/Kconfig.bl604e_iot_dvk b/boards/bouffalolab/bl60x/bl604e_iot_dvk/Kconfig.bl604e_iot_dvk
new file mode 100644
index 00000000000..806d0c5ca00
--- /dev/null
+++ b/boards/bouffalolab/bl60x/bl604e_iot_dvk/Kconfig.bl604e_iot_dvk
@@ -0,0 +1,6 @@
+# Copyright (c) 2022-2025 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_BL604E_IOT_DVK
+	select SOC_BL604E20Q2I
diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk-pinctrl.dtsi b/boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk-pinctrl.dtsi
new file mode 100644
index 00000000000..f5cce349d3c
--- /dev/null
+++ b/boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk-pinctrl.dtsi
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2021-2025 ATL Electronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/bl604x-pinctrl.h>
+
+&pinctrl {
+	uart0_default: uart0_default {
+		group1 {
+			pinmux = <GPIO7_UART0_RX>,
+				 <GPIO16_UART0_TX>;
+			bias-pull-up;
+			input-schmitt-enable;
+		};
+	};
+
+	uart0_sleep: uart0_sleep {
+		group1 {
+			pinmux = <GPIO7_UART0_RX>,
+				 <GPIO16_UART0_TX>;
+			bias-high-impedance;
+		};
+	};
+};
diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.dts b/boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.dts
new file mode 100644
index 00000000000..e81d9cc6b37
--- /dev/null
+++ b/boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.dts
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2022-2025 ATL Electronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <bouffalolab/bl60x.dtsi>
+#include "bl604e_iot_dvk-pinctrl.dtsi"
+
+/ {
+	model = "BL604E IOT DVK development board";
+	compatible = "bflb,bl604";
+
+	chosen {
+		zephyr,flash = &flash0;
+		zephyr,itcm = &itcm;
+		zephyr,dtcm = &dtcm;
+		zephyr,sram = &sram0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+};
+
+&cpu0 {
+	clock-frequency = <DT_FREQ_M(192)>;
+};
+
+&spi1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	reg = <0x4000b000 0x1000 0x23000000 0xc00000>;
+
+	flash0: flash@0 {
+		compatible = "issi,is25lp128", "jedec,spi-nor";
+		status = "disabled";
+		size = <DT_SIZE_M(128)>;
+		jedec-id = [96 60 18];
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_M(133)>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-1 = <&uart0_sleep>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.yaml b/boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.yaml
new file mode 100644
index 00000000000..51b1065ff22
--- /dev/null
+++ b/boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2022-2025 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl604e_iot_dvk
+name: BL604E IOT DVK development board
+type: mcu
+arch: riscv
+ram: 64
+toolchain:
+  - zephyr
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+supported:
+  - pinctrl
+  - uart
+vendor: bflb
diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk_defconfig b/boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk_defconfig
new file mode 100644
index 00000000000..2b274c4a841
--- /dev/null
+++ b/boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk_defconfig
@@ -0,0 +1,9 @@
+# Copyright (c) 2022-2025 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_BFLB=y
diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/board.cmake b/boards/bouffalolab/bl60x/bl604e_iot_dvk/board.cmake
new file mode 100644
index 00000000000..a8e089640bd
--- /dev/null
+++ b/boards/bouffalolab/bl60x/bl604e_iot_dvk/board.cmake
@@ -0,0 +1,20 @@
+# Copyright (c) 2022-2025 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(openocd --cmd-pre-init "source [find bl60x.cfg]")
+
+board_runner_args(openocd --use-elf --no-load --no-init)
+board_runner_args(openocd --gdb-init "set mem inaccessible-by-default off")
+board_runner_args(openocd --gdb-init "set architecture riscv:rv32")
+board_runner_args(openocd --gdb-init "set remotetimeout 250")
+board_runner_args(openocd --gdb-init "set print asm-demangle on")
+board_runner_args(openocd --gdb-init "set backtrace limit 32")
+board_runner_args(openocd --gdb-init "mem 0x22008000 0x22014000 rw")
+board_runner_args(openocd --gdb-init "mem 0x42008000 0x42014000 rw")
+board_runner_args(openocd --gdb-init "mem 0x22014000 0x22020000 rw")
+board_runner_args(openocd --gdb-init "mem 0x42014000 0x42020000 rw")
+board_runner_args(openocd --gdb-init "mem 0x22020000 0x2203C000 rw")
+board_runner_args(openocd --gdb-init "mem 0x42020000 0x4203C000 rw")
+board_runner_args(openocd --gdb-init "mem 0x23000000 0x23400000 ro")
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/board.yml b/boards/bouffalolab/bl60x/bl604e_iot_dvk/board.yml
new file mode 100644
index 00000000000..843d38b0e8a
--- /dev/null
+++ b/boards/bouffalolab/bl60x/bl604e_iot_dvk/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: bl604e_iot_dvk
+  full_name: BL604E IOT DVK development board
+  vendor: bflb
+  socs:
+    - name: bl604e20q2i
diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/doc/img/bl_604e.webp b/boards/bouffalolab/bl60x/bl604e_iot_dvk/doc/img/bl_604e.webp
new file mode 100644
index 00000000000..a4e60232feb
Binary files /dev/null and b/boards/bouffalolab/bl60x/bl604e_iot_dvk/doc/img/bl_604e.webp differ
diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/doc/index.rst b/boards/bouffalolab/bl60x/bl604e_iot_dvk/doc/index.rst
new file mode 100644
index 00000000000..76522129e41
--- /dev/null
+++ b/boards/bouffalolab/bl60x/bl604e_iot_dvk/doc/index.rst
@@ -0,0 +1,104 @@
+.. zephyr:board:: bl604e_iot_dvk
+
+Overview
+********
+
+BL602/BL604 is a Wi-Fi+BLE chipset introduced by Bouffalo Lab, which is used
+for low power consumption and high performance application development.  The
+wireless subsystem includes 2.4G radio, Wi-Fi 802.11b/g/n and BLE 5.0
+baseband/MAC design.  The microcontroller subsystem includes a 32-bit RISC CPU
+with low power consumption, cache and memory.  The power management unit
+controls the low power consumption mode.  In addition, it also supports
+various security features.  The external interfaces include SDIO, SPI, UART,
+I2C, IR remote, PWM, ADC, DAC, PIR and GPIO.
+
+The BL602 Development Board features a SiFive E24 32 bit RISC-V CPU with FPU,
+it supports High Frequency clock up to 192Mhz, have 128k ROM, 276kB RAM,
+2.4 GHz WIFI 1T1R mode, support 20 MHz, data rate up to 72.2 Mbps, BLE 5.0
+with 2MB phy.  It is a secure MCU which supports Secure boot, ECC-256 signed
+image, QSPI/SPI Flash On-The-Fly AES Decryption and PKA (Public Key
+Accelerator).
+
+Hardware
+********
+
+For more information about the Bouffalo Lab BL-60x MCU:
+
+- `Bouffalo Lab BL60x MCU Website`_
+- `Bouffalo Lab BL60x MCU Datasheet`_
+- `Bouffalo Lab Development Zone`_
+- `The RISC-V BL602 Book`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+The default configuration can be found in the Kconfig
+:zephyr_file:`boards/bouffalolab/bl60x/bl604e_iot_dvk/bl604e_iot_dvk_defconfig`.
+
+System Clock
+============
+
+The BL604E Development Board is configured to run at max speed (192MHz).
+
+Serial Port
+===========
+
+The ``bl604e_iot_dvk`` board uses UART0 as default serial port.  It is connected
+to USB Serial converter and port is used for both program and console.
+
+
+Programming and Debugging
+*************************
+
+Samples
+=======
+
+#. Build the Zephyr kernel and the :zephyr:code-sample:`hello_world` sample
+application:
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: bl604e_iot_dvk
+      :goals: build flash
+
+#. Run your favorite terminal program to listen for output. Under Linux the
+   terminal should be :code:`/dev/ttyACM0`. For example:
+
+   .. code-block:: console
+
+      $ minicom -D /dev/ttyACM0 -o
+
+   The -o option tells minicom not to send the modem initialization
+   string. Connection should be configured as follows:
+
+      - Speed: 115200
+      - Data: 8 bits
+      - Parity: None
+      - Stop bits: 1
+
+   Then, press and release RST button
+
+   .. code-block:: console
+
+      *** Booting Zephyr OS build v4.1.0 ***
+      Hello World! bl604e_iot_dvk/bl604e20q2i
+
+Congratulations, you have ``bl604e_iot_dvk`` configured and running Zephyr.
+
+
+.. _Bouffalo Lab BL60x MCU Website:
+	https://en.bouffalolab.com/product/?type=detail&id=6
+
+.. _Bouffalo Lab BL60x MCU Datasheet:
+	https://github.com/bouffalolab/bl_docs/tree/main/BL602_DS/en
+
+.. _Bouffalo Lab Development Zone:
+	https://dev.bouffalolab.com/home?id=guest
+
+.. _The RISC-V BL602 Book:
+	https://lupyuen.github.io/articles/book
+
+.. _Flashing Firmware to BL602:
+	https://lupyuen.github.io/articles/book#flashing-firmware-to-bl602
diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/support/bl60x.cfg b/boards/bouffalolab/bl60x/bl604e_iot_dvk/support/bl60x.cfg
new file mode 100644
index 00000000000..fcabb2c4e7c
--- /dev/null
+++ b/boards/bouffalolab/bl60x/bl604e_iot_dvk/support/bl60x.cfg
@@ -0,0 +1,79 @@
+# Copyright (c) 2022-2025 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if { [info exists CHIPNAME] } {
+    set _CHIPNAME $CHIPNAME
+} else {
+    set _CHIPNAME riscv
+}
+
+if { [info exists WORKAREASIZE] } {
+    set _WORKAREASIZE $WORKAREASIZE
+} else {
+    set _WORKAREASIZE 0x10000
+}
+
+if { [info exists WORKAREAADDR] } {
+    set _WORKAREAADDR $WORKAREAADDR
+} else {
+    set _WORKAREAADDR 0x22020000
+}
+
+if { [info exists CPUTAPID] } {
+    set _CPUTAPID $CPUTAPID
+} else {
+    set _CPUTAPID 0x20000c05
+}
+
+transport select jtag
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+
+$_TARGETNAME.0 configure -work-area-phys $_WORKAREAADDR -work-area-size $_WORKAREASIZE -work-area-backup 1
+
+echo "Ready for Remote Connections"
+
+$_TARGETNAME.0 configure -event reset-assert-pre {
+    echo "reset-assert-pre"
+    adapter speed 100
+}
+
+$_TARGETNAME.0 configure -event reset-deassert-post {
+    echo "reset-deassert-post"
+
+    adapter speed 100
+
+    reg mstatus 0x7800
+    reg mie 0x0
+#    reg pc 0x23000000
+}
+
+$_TARGETNAME.0 configure -event reset-init {
+    echo "reset-init"
+
+    adapter speed 3000
+}
+
+$_TARGETNAME.0 configure -event gdb-attach {
+        echo "Debugger attaching: halting execution"
+        reset halt
+        gdb_breakpoint_override hard
+}
+
+$_TARGETNAME.0 configure -event gdb-detach {
+        echo "Debugger detaching: resuming execution"
+        resume
+}
+
+gdb_memory_map enable
+gdb_flash_program enable
+
+# 'progbuf', 'sysbus' or 'abstract'
+riscv set_mem_access sysbus
+riscv set_command_timeout_sec 1
+
+init
+reset init
diff --git a/boards/bouffalolab/bl60x/bl604e_iot_dvk/support/openocd.cfg b/boards/bouffalolab/bl60x/bl604e_iot_dvk/support/openocd.cfg
new file mode 100644
index 00000000000..ffd60cfb196
--- /dev/null
+++ b/boards/bouffalolab/bl60x/bl604e_iot_dvk/support/openocd.cfg
@@ -0,0 +1,19 @@
+# OpenOCD Script for PineCone connected via Sipeed JTAG Debugger (FTDI FT2232D)
+# Ref: bl_iot_sdk/tools/debug/if_bflb_link.cfg
+# source [find interface/if_bflb_link.cfg]
+
+# Uncomment to enable debug messages
+# debug_level 4
+
+# BouffaloLab USB-JTAG/TTL adapter
+# Or Sipeed JTAG Debugger based on FTDI FT2232D
+
+adapter driver ftdi
+ftdi vid_pid 0x0403 0x6010
+
+# Sipeed JTAG Debugger uses FTDI Channel 0, not 1
+ftdi channel 0
+# ftdi_channel 1
+
+ftdi layout_init 0x00f8 0x00fb
+adapter speed 4000
diff --git a/boards/bouffalolab/index.rst b/boards/bouffalolab/index.rst
new file mode 100644
index 00000000000..f0380b6b45c
--- /dev/null
+++ b/boards/bouffalolab/index.rst
@@ -0,0 +1,10 @@
+.. _boards-bouffalolab:
+
+Bouffalo Lab Intelligent Technology (Nanjing) Co., Ltd.
+#######################################################
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*
diff --git a/boards/bytesatwork/bytesensi_l/bytesensi_l.dts b/boards/bytesatwork/bytesensi_l/bytesensi_l.dts
index 2054d6bd2e2..b3be00fc171 100644
--- a/boards/bytesatwork/bytesensi_l/bytesensi_l.dts
+++ b/boards/bytesatwork/bytesensi_l/bytesensi_l.dts
@@ -93,15 +93,15 @@
 		int-gpios = <&gpio0 25 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
 	};
 
-	temperature_sensor: tmp116@4a {
+	temperature_sensor: tmp11x@4a {
 		status = "okay";
-		compatible = "ti,tmp116";
+		compatible = "ti,tmp11x";
 		reg = <0x4a>;
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		eeprom: ti_tmp116_eeprom@0 {
-			compatible = "ti,tmp116-eeprom";
+		eeprom: ti_tmp11x_eeprom@0 {
+			compatible = "ti,tmp11x-eeprom";
 			reg = <0x0>;
 			read-only;
 		};
diff --git a/boards/bytesatwork/bytesensi_l/doc/index.rst b/boards/bytesatwork/bytesensi_l/doc/index.rst
index d1b220a778b..35e402497ed 100644
--- a/boards/bytesatwork/bytesensi_l/doc/index.rst
+++ b/boards/bytesatwork/bytesensi_l/doc/index.rst
@@ -12,33 +12,7 @@ Hardware
 Supported Features
 ==================
 
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| GPS       | u-blox     | gnss                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
-| RADIO     | Semtech    | LoRa                 |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -121,6 +95,8 @@ External GPS Antenna @ J3
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 The byteSENSI-L board can be flashed with the SEGGER JLink programmer.
diff --git a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160.yaml b/boards/circuitdojo/feather/circuitdojo_feather_nrf9160.yaml
index ee93576b4af..c3f8f1634d4 100644
--- a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160.yaml
+++ b/boards/circuitdojo/feather/circuitdojo_feather_nrf9160.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 64
 flash: 256
diff --git a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_ns.yaml b/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_ns.yaml
index 582e28dbfc9..85c4c60194f 100644
--- a/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_ns.yaml
+++ b/boards/circuitdojo/feather/circuitdojo_feather_nrf9160_ns.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 128
 flash: 192
diff --git a/boards/common/esp32.board.cmake b/boards/common/esp32.board.cmake
index cfe7b7683fc..4669c2e620b 100644
--- a/boards/common/esp32.board.cmake
+++ b/boards/common/esp32.board.cmake
@@ -13,4 +13,4 @@ board_runner_args(openocd  --gdb-init "thb main")
 set(ESP_IDF_PATH ${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR})
 assert(ESP_IDF_PATH "ESP_IDF_PATH is not set")
 
-board_finalize_runner_args(esp32 "--esp-idf-path=${ESP_IDF_PATH}")
+board_runner_args(esp32 "--esp-idf-path=${ESP_IDF_PATH}")
diff --git a/boards/common/openocd-adi-max32.boards.cmake b/boards/common/openocd-adi-max32.boards.cmake
new file mode 100644
index 00000000000..c231f5ad1cf
--- /dev/null
+++ b/boards/common/openocd-adi-max32.boards.cmake
@@ -0,0 +1,26 @@
+#
+# Copyright (c) 2025 Analog Devices, Inc
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_ARCH STREQUAL "riscv")
+  set(MAX32_TARGET_CFG "${CONFIG_SOC}_riscv.cfg")
+  set(MAX32_INTERFACE_CFG "olimex-arm-usb-ocd-h.cfg")
+else()
+  set(MAX32_TARGET_CFG "${CONFIG_SOC}.cfg")
+  set(MAX32_INTERFACE_CFG "cmsis-dap.cfg")
+endif()
+
+# MAX32666 share the same target configuration file with MAX32665
+if(CONFIG_SOC_MAX32666)
+  set(MAX32_TARGET_CFG "max32665.cfg")
+endif()
+
+board_runner_args(openocd --cmd-pre-init "source [find interface/${MAX32_INTERFACE_CFG}]")
+board_runner_args(openocd --cmd-pre-init "source [find target/${MAX32_TARGET_CFG}]")
+board_runner_args(openocd "--target-handle=_CHIPNAME.cpu")
+
+if(CONFIG_SOC_FAMILY_MAX32_M4)
+  board_runner_args(openocd --cmd-pre-init "allow_low_pwr_dbg")
+  board_runner_args(openocd "--cmd-erase=max32xxx mass_erase 0")
+endif()
diff --git a/boards/common/openocd-stm32.board.cmake b/boards/common/openocd-stm32.board.cmake
new file mode 100644
index 00000000000..855411fa34b
--- /dev/null
+++ b/boards/common/openocd-stm32.board.cmake
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_SERIES_STM32L0X OR CONFIG_SOC_SERIES_STM32L1X)
+  board_runner_args(openocd "--cmd-erase=stm32l1x mass_erase 0")
+elseif(CONFIG_SOC_SERIES_STM32L4X OR
+       CONFIG_SOC_SERIES_STM32L5X OR
+       CONFIG_SOC_SERIES_STM32U5X OR
+       CONFIG_SOC_SERIES_STM32WBX OR
+       CONFIG_SOC_SERIES_STM32G0X OR
+       CONFIG_SOC_SERIES_STM32G4X)
+  board_runner_args(openocd "--cmd-erase=stm32l4x mass_erase 0")
+elseif(CONFIG_SOC_SERIES_STM32F0X OR
+       CONFIG_SOC_SERIES_STM32F1X OR
+       CONFIG_SOC_SERIES_STM32F3X)
+  board_runner_args(openocd "--cmd-erase=stm32f1x mass_erase 0")
+elseif(CONFIG_SOC_SERIES_STM32F2X OR
+       CONFIG_SOC_SERIES_STM32F4X OR
+       CONFIG_SOC_SERIES_STM32F7X)
+  board_runner_args(openocd "--cmd-erase=stm32f2x mass_erase 0")
+endif()
diff --git a/boards/common/openocd.board.cmake b/boards/common/openocd.board.cmake
index 14d32d4be25..b1d09fe0a2d 100644
--- a/boards/common/openocd.board.cmake
+++ b/boards/common/openocd.board.cmake
@@ -20,3 +20,6 @@ board_finalize_runner_args(openocd
   --cmd-load "${OPENOCD_CMD_LOAD_DEFAULT}"
   --cmd-verify "${OPENOCD_CMD_VERIFY_DEFAULT}"
   )
+
+# Manufacturer common options
+include(${CMAKE_CURRENT_LIST_DIR}/openocd-stm32.board.cmake)
diff --git a/boards/common/rfp.board.cmake b/boards/common/rfp.board.cmake
new file mode 100644
index 00000000000..afce0c8019c
--- /dev/null
+++ b/boards/common/rfp.board.cmake
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_set_flasher_ifnset(rfp)
+
+board_finalize_runner_args(rfp)
diff --git a/boards/contextualelectronics/abc/contextualelectronics_abc.yaml b/boards/contextualelectronics/abc/contextualelectronics_abc.yaml
index f96fa8c29bf..57f5b4f49bb 100644
--- a/boards/contextualelectronics/abc/contextualelectronics_abc.yaml
+++ b/boards/contextualelectronics/abc/contextualelectronics_abc.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_i2c
   - arduino_spi
diff --git a/boards/contextualelectronics/abc/doc/index.rst b/boards/contextualelectronics/abc/doc/index.rst
index d7f12bc4738..02ddb9689e5 100644
--- a/boards/contextualelectronics/abc/doc/index.rst
+++ b/boards/contextualelectronics/abc/doc/index.rst
@@ -35,38 +35,8 @@ is 32.768 kHz. The frequency of the main clock is 32 MHz.
 Supported Features
 ==================
 
-The contextualelectronics_abc board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M)    | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| Modem     | on-board   | quectel_bg9x         |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `ABC Board website`_ for more details on this board, and
 `Nordic Semiconductor Infocenter`_ for a complete list of SoC
 features.
@@ -74,6 +44,8 @@ features.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``contextualelectronics_abc`` board configuration can be
 built and flashed in the usual way (see :ref:`build_an_application`
 and :ref:`application_run` for more details).
diff --git a/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.yaml b/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.yaml
index bc550fd4cc4..3eef0741d5a 100644
--- a/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.yaml
+++ b/boards/croxel/croxel_cx1825/croxel_cx1825_nrf52840.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - ble
   - counter
diff --git a/boards/croxel/croxel_cx1825/doc/index.rst b/boards/croxel/croxel_cx1825/doc/index.rst
index ab88c4dd432..cee944d5f97 100644
--- a/boards/croxel/croxel_cx1825/doc/index.rst
+++ b/boards/croxel/croxel_cx1825/doc/index.rst
@@ -46,12 +46,7 @@ Hardware
 Supported Features
 ==================
 
-- Discrete LEDs (red and green)
-- Buttons (User and Reset)
-- Sensors (Accelerometer, Light, Temperature and Humidity, Pressure and Hall-Effect sensors)
-- Beeper
-- Radio (Bluetooth, IEEE 802.15.4)
-- SOC peripherals (ADC, Clock, Flash, GPIO, I2C, MPU, NVIC, PWM, Radio, RTC, SPI, USB, WDT)
+.. zephyr:board-supported-hw::
 
 Future Feature Support
 ======================
@@ -81,6 +76,8 @@ Digital Inputs
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``croxel_cx1825/nrf52840`` board configuration
 can be built and flashed in the usual way (see :ref:`build_an_application`
 and :ref:`application_run` for more details).
diff --git a/boards/ct/ctcc/ctcc_nrf52840.yaml b/boards/ct/ctcc/ctcc_nrf52840.yaml
index 3f4099b5b87..332273c3a42 100644
--- a/boards/ct/ctcc/ctcc_nrf52840.yaml
+++ b/boards/ct/ctcc/ctcc_nrf52840.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - ble
   - gpio
diff --git a/boards/ct/ctcc/ctcc_nrf9161-pinctrl.dtsi b/boards/ct/ctcc/ctcc_nrf9161-pinctrl.dtsi
index c48b2987b85..10eece2fd56 100644
--- a/boards/ct/ctcc/ctcc_nrf9161-pinctrl.dtsi
+++ b/boards/ct/ctcc/ctcc_nrf9161-pinctrl.dtsi
@@ -25,28 +25,6 @@
 		};
 	};
 
-	uart1_default: uart1_default {
-		group1 {
-			psels = <NRF_PSEL(UART_TX, 0, 27)>,
-				<NRF_PSEL(UART_RTS, 0, 16)>;
-		};
-		group2 {
-			psels = <NRF_PSEL(UART_RX, 0, 26)>,
-				<NRF_PSEL(UART_CTS, 0, 17)>;
-			bias-pull-up;
-		};
-	};
-
-	uart1_sleep: uart1_sleep {
-		group1 {
-			psels = <NRF_PSEL(UART_TX, 0, 27)>,
-				<NRF_PSEL(UART_RX, 0, 26)>,
-				<NRF_PSEL(UART_RTS, 0, 16)>,
-				<NRF_PSEL(UART_CTS, 0, 17)>;
-			low-power-enable;
-		};
-	};
-
 	spi3_default: spi3_default {
 		group1 {
 			psels = <NRF_PSEL(SPIM_SCK, 0, 3)>,
diff --git a/boards/ct/ctcc/ctcc_nrf9161.yaml b/boards/ct/ctcc/ctcc_nrf9161.yaml
index 8cc32c4068a..3c3a63796e1 100644
--- a/boards/ct/ctcc/ctcc_nrf9161.yaml
+++ b/boards/ct/ctcc/ctcc_nrf9161.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 88
 flash: 1024
 supported:
diff --git a/boards/ct/ctcc/ctcc_nrf9161_common.dtsi b/boards/ct/ctcc/ctcc_nrf9161_common.dtsi
index 92a2a757c55..00e53a5262c 100644
--- a/boards/ct/ctcc/ctcc_nrf9161_common.dtsi
+++ b/boards/ct/ctcc/ctcc_nrf9161_common.dtsi
@@ -39,10 +39,6 @@
 	};
 };
 
-&adc {
-	status = "okay";
-};
-
 &gpiote {
 	status = "okay";
 };
@@ -59,14 +55,6 @@
 	pinctrl-names = "default", "sleep";
 };
 
-&uart1 {
-	status = "okay";
-	current-speed = <115200>;
-	pinctrl-0 = <&uart1_default>;
-	pinctrl-1 = <&uart1_sleep>;
-	pinctrl-names = "default", "sleep";
-};
-
 &spi3 {
 	compatible = "nordic,nrf-spim";
 	status = "okay";
diff --git a/boards/ct/ctcc/ctcc_nrf9161_ns.yaml b/boards/ct/ctcc/ctcc_nrf9161_ns.yaml
index 67a17c77209..1017ca1989b 100644
--- a/boards/ct/ctcc/ctcc_nrf9161_ns.yaml
+++ b/boards/ct/ctcc/ctcc_nrf9161_ns.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 192
 supported:
diff --git a/boards/ct/ctcc/doc/index.rst b/boards/ct/ctcc/doc/index.rst
index 97780246a74..5a890893c23 100644
--- a/boards/ct/ctcc/doc/index.rst
+++ b/boards/ct/ctcc/doc/index.rst
@@ -57,63 +57,7 @@ Hardware
 Supported Features
 ==================
 
-The ``ctcc/nrf52840`` board target supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-The ``ctcc/nrf9161`` board target supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| FLASH     | external   | spi                  |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | LTE-M/NB-IoT,        |
-|           |            | DECT NR\+            |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| SPU       | on-chip    | system protection    |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -137,6 +81,8 @@ nRF9161:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for ``ctcc`` boards can be
 built in the usual way (see :ref:`build_an_application` for more details).
 
diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml
index 0ef2e8ae823..562a016589c 100644
--- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml
+++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_0_0_0.yaml
@@ -14,7 +14,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_gpio
   - arduino_spi
diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml
index 032fc65cdf3..c4284bd0ef8 100644
--- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml
+++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_1_0_0.yaml
@@ -14,7 +14,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_gpio
   - arduino_spi
diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_defconfig b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_defconfig
index fefeed4980f..16e024e3bca 100644
--- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_defconfig
+++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m0_defconfig
@@ -7,7 +7,6 @@
 
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
-CONFIG_BUILD_OUTPUT_HEX=y
 
 # UART driver
 CONFIG_SERIAL=y
diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml
index 1ca0aaa3a11..ba6b4bbc74d 100644
--- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml
+++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.yaml
@@ -14,7 +14,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_gpio
   - gpio
diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml
index cdfb09a6942..44697309a42 100644
--- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml
+++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_1_0_0.yaml
@@ -14,7 +14,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_gpio
   - gpio
diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_defconfig b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_defconfig
index fefeed4980f..16e024e3bca 100644
--- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_defconfig
+++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_defconfig
@@ -7,7 +7,6 @@
 
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
-CONFIG_BUILD_OUTPUT_HEX=y
 
 # UART driver
 CONFIG_SERIAL=y
diff --git a/boards/cypress/cy8ckit_062_ble/doc/index.rst b/boards/cypress/cy8ckit_062_ble/doc/index.rst
index 01ad4696ea2..8a5090a5ed4 100644
--- a/boards/cypress/cy8ckit_062_ble/doc/index.rst
+++ b/boards/cypress/cy8ckit_062_ble/doc/index.rst
@@ -1,7 +1,4 @@
-.. _cy8ckit_062_ble:
-
-INFINEON PSOC 63 BLE Pioneer Kit
-################################
+.. zephyr:board:: cy8ckit_062_ble
 
 Overview
 ********
@@ -30,10 +27,6 @@ enabling you to emulate a BLE host on your computer.
 The Cortex-M0+ is a primary core on the board's SoC. It starts first and
 enables the CM4 core.
 
-.. image:: img/cy8ckit-062-ble.jpg
-     :align: center
-     :alt: CY8CKIT_062_BLE
-
 1. Battery charging indicator (LED6)
 2. USB PD output voltage availability indicator (LED7)
 3. KitProg2 USB Type-C connector (J10)
@@ -147,6 +140,8 @@ To get the OpenOCD package, it is required that you
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The CY8CKIT-062-BLE includes an onboard programmer/debugger (KitProg2) with
 mass storage programming to provide debugging, flash programming, and serial
 communication over USB. There are also PSOC 6 program and debug headers J11
diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml
index 4135437c52a..12d1dca31d5 100644
--- a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml
+++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0.yaml
@@ -13,7 +13,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
 vendor: cypress
diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig
index fd9d1d319ab..d9ff32f44cc 100644
--- a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig
+++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m0_defconfig
@@ -6,7 +6,6 @@
 
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
-CONFIG_BUILD_OUTPUT_HEX=y
 
 # UART driver
 CONFIG_SERIAL=y
diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml
index e861d197140..2a5b4a1f788 100644
--- a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml
+++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4.yaml
@@ -13,7 +13,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
 vendor: cypress
diff --git a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4_defconfig b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4_defconfig
index fd9d1d319ab..d9ff32f44cc 100644
--- a/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4_defconfig
+++ b/boards/cypress/cy8ckit_062_wifi_bt/cy8ckit_062_wifi_bt_cy8c6247_m4_defconfig
@@ -6,7 +6,6 @@
 
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
-CONFIG_BUILD_OUTPUT_HEX=y
 
 # UART driver
 CONFIG_SERIAL=y
diff --git a/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst b/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst
index a0ad601ad63..dc201ecc7a7 100644
--- a/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst
+++ b/boards/cypress/cy8ckit_062_wifi_bt/doc/index.rst
@@ -1,7 +1,4 @@
-.. _cy8ckit_062_wifi_bt:
-
-INFINEON PSOC 6 WiFi-BT Pioneer Kit
-###################################
+.. zephyr:board:: cy8ckit_062_wifi_bt
 
 Overview
 ********
@@ -23,10 +20,6 @@ The PSOC 6 WiFi-BT Pioneer board offers compatibility with Arduino shields.
 The Cortex-M0+ is a primary core on the board's SoC. It starts first and
 enables the CM4 core.
 
-.. image:: img/cy8ckit_062_wifi_bt_m0.jpg
-     :align: center
-     :alt: CY8CKIT_062_WIFI_BT
-
 1. USB PD output voltage availability indicator (LED7)
 2. Battery charging indicator (LED6)
 3. KitProg2 USB Type-C connector (J10)
@@ -134,6 +127,8 @@ To get the OpenOCD package, it is required that you
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The CY8CKIT-062-WiFi-BT includes an onboard programmer/debugger (KitProg2) with
 mass storage programming to provide debugging, flash programming, and serial
 communication over USB. There are also PSOC 6 program and debug headers J11
diff --git a/boards/deprecated.cmake b/boards/deprecated.cmake
index 78a960ec2e4..1dd7b14a629 100644
--- a/boards/deprecated.cmake
+++ b/boards/deprecated.cmake
@@ -16,6 +16,15 @@
 set(adafruit_feather_DEPRECATED
     adafruit_feather_nrf52840/nrf52840
 )
+set(arduino_uno_r4_minima_DEPRECATED
+    arduino_uno_r4@minima
+)
+set(arduino_uno_r4_wifi_DEPRECATED
+    arduino_uno_r4@wifi
+)
+set(esp32c6_devkitc_DEPRECATED
+    esp32c6_devkitc/esp32c6/hpcore
+)
 set(qemu_xtensa_DEPRECATED
     qemu_xtensa/dc233c
 )
@@ -37,3 +46,9 @@ set(mimxrt1060_evk_DEPRECATED
 set(mimxrt1060_evkb_DEPRECATED
     mimxrt1060_evk@B/mimxrt1062/qspi
 )
+set(neorv32_DEPRECATED
+    neorv32/neorv32/up5kdemo
+)
+set(xiao_esp32c6_DEPRECATED
+    xiao_esp32c6/esp32c6/hpcore
+)
diff --git a/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1.yaml b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1.yaml
index 565ddbffdb8..aaf3326b4a4 100644
--- a/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1.yaml
+++ b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m1.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
 flash: 64
 supported:
diff --git a/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3.yaml b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3.yaml
index 416365ff291..c4334d658f5 100644
--- a/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3.yaml
+++ b/boards/digilent/arty_a7/arty_a7_designstart_fpga_cortex_m3.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
 flash: 32
 supported:
diff --git a/boards/digilent/zybo/zybo.yaml b/boards/digilent/zybo/zybo.yaml
index 573fb74f666..8f4e5f5b94a 100644
--- a/boards/digilent/zybo/zybo.yaml
+++ b/boards/digilent/zybo/zybo.yaml
@@ -8,7 +8,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 524288
 supported:
   - gpio
diff --git a/boards/dptechnics/walter/doc/index.rst b/boards/dptechnics/walter/doc/index.rst
index c77e266f52b..eb5dc5e3d50 100644
--- a/boards/dptechnics/walter/doc/index.rst
+++ b/boards/dptechnics/walter/doc/index.rst
@@ -58,47 +58,7 @@ Form factor
 Supported Features
 ==================
 
-Current Zephyr's Walter board supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| TWAI/CAN   | on-chip    | can                                 |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | adc                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| MCPWM      | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| PCNT       | on-chip    | qdec                                |
-+------------+------------+-------------------------------------+
-| GDMA       | on-chip    | dma                                 |
-+------------+------------+-------------------------------------+
-| USB-CDC    | on-chip    | serial                              |
-+------------+------------+-------------------------------------+
-| Wi-Fi      | on-chip    |                                     |
-+------------+------------+-------------------------------------+
-| Bluetooth  | on-chip    |                                     |
-+------------+------------+-------------------------------------+
-| Cellular   | on-board   | modem_cellular                      |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Prerequisites
 -------------
@@ -117,6 +77,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/dptechnics/walter/walter_esp32s3_appcpu_defconfig b/boards/dptechnics/walter/walter_esp32s3_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/dptechnics/walter/walter_esp32s3_appcpu_defconfig
+++ b/boards/dptechnics/walter/walter_esp32s3_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/dptechnics/walter/walter_esp32s3_procpu.dts b/boards/dptechnics/walter/walter_esp32s3_procpu.dts
index 8d864885e0f..0568d597960 100644
--- a/boards/dptechnics/walter/walter_esp32s3_procpu.dts
+++ b/boards/dptechnics/walter/walter_esp32s3_procpu.dts
@@ -49,6 +49,7 @@
 		status = "okay";
 		compatible = "sqn,gm02s";
 		mdm-reset-gpios = <&gpio1 13 (GPIO_OPEN_DRAIN | GPIO_ACTIVE_LOW)>;
+		mdm-wake-gpios = <&gpio1 14 (GPIO_OPEN_SOURCE | GPIO_ACTIVE_HIGH)>;
 	};
 };
 
@@ -120,3 +121,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/dptechnics/walter/walter_esp32s3_procpu_defconfig b/boards/dptechnics/walter/walter_esp32s3_procpu_defconfig
index 59f3df7a866..36749d64448 100644
--- a/boards/dptechnics/walter/walter_esp32s3_procpu_defconfig
+++ b/boards/dptechnics/walter/walter_esp32s3_procpu_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/dragino/lsn50/doc/index.rst b/boards/dragino/lsn50/doc/index.rst
index 999c809a90f..d5981b51817 100644
--- a/boards/dragino/lsn50/doc/index.rst
+++ b/boards/dragino/lsn50/doc/index.rst
@@ -78,24 +78,7 @@ More information about STM32L072CZ can be found here:
 Supported Features
 ==================
 
-The Zephyr Dragino LSN50 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/dragino/lsn50/dragino_lsn50_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -130,6 +113,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``dragino_lsn50`` board configuration can be built and
 flashed in the usual way (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/dragino/lsn50/dragino_lsn50.yaml b/boards/dragino/lsn50/dragino_lsn50.yaml
index 52418c949a4..cc4c19c5958 100644
--- a/boards/dragino/lsn50/dragino_lsn50.yaml
+++ b/boards/dragino/lsn50/dragino_lsn50.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 20
 flash: 192
 testing:
diff --git a/boards/dragino/nbsn95/doc/index.rst b/boards/dragino/nbsn95/doc/index.rst
index c18bb7eee40..c99e6c87bdc 100644
--- a/boards/dragino/nbsn95/doc/index.rst
+++ b/boards/dragino/nbsn95/doc/index.rst
@@ -77,24 +77,7 @@ More information about STM32L072CZ can be found here:
 Supported Features
 ==================
 
-The Zephyr Dragino NBSN95 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/dragino/nbsn95/dragino_nbsn95_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -129,6 +112,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``dragino_nbsn95`` board configuration can be built and
 flashed in the usual way (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/dragino/nbsn95/dragino_nbsn95.yaml b/boards/dragino/nbsn95/dragino_nbsn95.yaml
index f614987d58d..3128e7d2a04 100644
--- a/boards/dragino/nbsn95/dragino_nbsn95.yaml
+++ b/boards/dragino/nbsn95/dragino_nbsn95.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 20
 flash: 192
 testing:
diff --git a/boards/ebyte/e73_tbb/doc/index.rst b/boards/ebyte/e73_tbb/doc/index.rst
index 5d1327e322c..68bd2608dc9 100644
--- a/boards/ebyte/e73_tbb/doc/index.rst
+++ b/boards/ebyte/e73_tbb/doc/index.rst
@@ -39,42 +39,8 @@ and solder NFC antenna using NFC_ANT connector.
 Supported Features
 ==================
 
-The ebyte_e73_tbb/nrf52832 board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features are not supported by the Zephyr kernel.
+.. zephyr:board-supported-hw::
+
 See `E73-TBB website`_ and `Nordic Semiconductor Infocenter`_
 for a complete list of nRF52832 hardware features.
 
@@ -169,6 +135,8 @@ NFC_ANT
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.yaml b/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.yaml
index 9311e76cff1..67853fd073d 100644
--- a/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.yaml
+++ b/boards/ebyte/e73_tbb/ebyte_e73_tbb_nrf52832.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 512
 supported:
diff --git a/boards/electronut/nrf52840_blip/doc/index.rst b/boards/electronut/nrf52840_blip/doc/index.rst
index 03dfff0bf56..376412e4d40 100644
--- a/boards/electronut/nrf52840_blip/doc/index.rst
+++ b/boards/electronut/nrf52840_blip/doc/index.rst
@@ -34,43 +34,7 @@ is 32 MHz.
 Supported Features
 ==================
 
-The nrf52840_blip board configuration supports the following
-hardware features currently:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -116,6 +80,8 @@ MicroSD is connected to these pins, and CS pin is connected to P0.17.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``nrf52840_blip`` board configuration can be
 built and flashed in the usual way (see :ref:`build_an_application`
 and :ref:`application_run` for more details); The onboard Black Magic
diff --git a/boards/electronut/nrf52840_blip/nrf52840_blip.yaml b/boards/electronut/nrf52840_blip/nrf52840_blip.yaml
index 694c2c251b8..975f1b831ed 100644
--- a/boards/electronut/nrf52840_blip/nrf52840_blip.yaml
+++ b/boards/electronut/nrf52840_blip/nrf52840_blip.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - i2c
diff --git a/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst b/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst
index 391175eebc2..f674496b021 100644
--- a/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst
+++ b/boards/electronut/nrf52840_papyr/doc/nrf52840_papyr.rst
@@ -36,41 +36,7 @@ is 32 MHz.
 Supported Features
 ==================
 
-The nrf52840_papyr board configuration supports the following
-hardware features currently:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -123,6 +89,8 @@ Other pins used by the e-paper display are:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``nrf52840_papyr`` board configuration can be
 built and flashed in the usual way (see :ref:`build_an_application`
 and :ref:`application_run` for more details); Black Magic
diff --git a/boards/electronut/nrf52840_papyr/nrf52840_papyr.yaml b/boards/electronut/nrf52840_papyr/nrf52840_papyr.yaml
index 446c5205f96..1c743016802 100644
--- a/boards/electronut/nrf52840_papyr/nrf52840_papyr.yaml
+++ b/boards/electronut/nrf52840_papyr/nrf52840_papyr.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - usb_device
diff --git a/boards/element14/warp7/doc/index.rst b/boards/element14/warp7/doc/index.rst
index d0940f5271a..016681c30ab 100644
--- a/boards/element14/warp7/doc/index.rst
+++ b/boards/element14/warp7/doc/index.rst
@@ -68,33 +68,7 @@ For more information about the i.MX7 SoC and WaRP7, see these references:
 Supported Features
 ==================
 
-The WaRP7 configuration supports the following hardware features on the
-Cortex M4 Core:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| SENSOR    | off-chip   | fxos8700 polling;                   |
-|           |            | fxos8700 trigger;                   |
-|           |            | fxas21002 polling;                  |
-|           |            | fxas21002 trigger;                  |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/element14/warp7/warp7_mcimx7d_m4_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -136,6 +110,8 @@ the number 6 is used in the mikroBUS connector.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The WaRP7 doesn't have QSPI flash for the M4 and it needs to be started by
 the A7 core. The A7 core is responsible to load the M4 binary application into
 the RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and
diff --git a/boards/element14/warp7/warp7_mcimx7d_m4.yaml b/boards/element14/warp7/warp7_mcimx7d_m4.yaml
index 96a7e7fbca8..24bcdb296fb 100644
--- a/boards/element14/warp7/warp7_mcimx7d_m4.yaml
+++ b/boards/element14/warp7/warp7_mcimx7d_m4.yaml
@@ -13,7 +13,6 @@ flash: 32
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 testing:
   ignore_tags:
     - net
diff --git a/boards/enclustra/mercury_xu/mercury_xu.dts b/boards/enclustra/mercury_xu/mercury_xu.dts
index df51ab470c5..c0abbec19a3 100644
--- a/boards/enclustra/mercury_xu/mercury_xu.dts
+++ b/boards/enclustra/mercury_xu/mercury_xu.dts
@@ -10,7 +10,7 @@
 
 / {
 	model = "Mercury XU";
-	compatible = "xlnx,zynqmp";
+	compatible = "enclustra,mercury_xu";
 
 	chosen {
 		zephyr,console = &uart0;
diff --git a/boards/enclustra/mercury_xu/mercury_xu.yaml b/boards/enclustra/mercury_xu/mercury_xu.yaml
index df01c2b112a..f2cc537a06c 100644
--- a/boards/enclustra/mercury_xu/mercury_xu.yaml
+++ b/boards/enclustra/mercury_xu/mercury_xu.yaml
@@ -6,4 +6,4 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-vendor: xlnx
+vendor: enclustra
diff --git a/boards/ene/kb1200_evb/doc/index.rst b/boards/ene/kb1200_evb/doc/index.rst
index 6558b8dad54..2bd60859af7 100644
--- a/boards/ene/kb1200_evb/doc/index.rst
+++ b/boards/ene/kb1200_evb/doc/index.rst
@@ -1,7 +1,4 @@
-.. _ene_kb1200_evb:
-
-ENE KB1200_EVB
-##############
+.. zephyr:board:: kb1200_evb
 
 Overview
 ********
@@ -24,38 +21,7 @@ Hardware
 Supported Features
 ==================
 
-The following features are supported:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc controller                      |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c port/controller                 |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| PMU       | on-chip    | power management                    |
-+-----------+------------+-------------------------------------+
-| PSL       | on-chip    | power switch logic                  |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pulse width modulator               |
-+-----------+------------+-------------------------------------+
-| TACH      | on-chip    | tachometer sensor                   |
-+-----------+------------+-------------------------------------+
-| SER       | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WDT       | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by Zephyr (at the moment)
+.. zephyr:board-supported-hw::
 
 System Clock
 ============
@@ -67,6 +33,8 @@ See Processor clock control register (refer 5.1 General Configuration)
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/ene/kb1200_evb/kb1200_evb.yaml b/boards/ene/kb1200_evb/kb1200_evb.yaml
index efa85b9c830..e381e7c6c6a 100644
--- a/boards/ene/kb1200_evb/kb1200_evb.yaml
+++ b/boards/ene/kb1200_evb/kb1200_evb.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - uart
diff --git a/boards/enjoydigital/litex_vexriscv/doc/index.rst b/boards/enjoydigital/litex_vexriscv/doc/index.rst
index f9764907eb4..bd47c381a73 100644
--- a/boards/enjoydigital/litex_vexriscv/doc/index.rst
+++ b/boards/enjoydigital/litex_vexriscv/doc/index.rst
@@ -1,7 +1,4 @@
-.. _litex-vexriscv:
-
-LiteX VexRiscv
-##############
+.. zephyr:board:: litex_vexriscv
 
 LiteX VexRiscv is an example of a system on a chip (SoC) that consists of
 a `VexRiscv processor <https://github.com/SpinalHDL/VexRiscv>`_
@@ -20,10 +17,6 @@ LiteX VexRiscv SoC implementation generated for the
 <https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists>`_
 or `SDI-MIPI Video Converter <https://github.com/antmicro/sdi-mipi-video-converter>`_.
 
-.. image:: img/litex_vexriscv.jpg
-   :align: center
-   :alt: LiteX VexRiscv on Digilent Arty 35T Board
-
 LiteX is based on
 `Migen <https://m-labs.hk/gateware/migen/>`_/`MiSoC SoC builder <https://github.com/m-labs/misoc>`_
 and provides ready-made system components such as buses, streams, interconnects,
@@ -49,6 +42,11 @@ using the
 `Zephyr on LiteX VexRiscv <https://github.com/litex-hub/zephyr-on-litex-vexriscv>`_
 reference platform. You can also use the official LiteX SoC Builder.
 
+Supported Features
+******************
+
+.. zephyr:board-supported-hw::
+
 Bitstream generation
 ********************
 
diff --git a/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts b/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts
index 19f56f8b289..cb308261903 100644
--- a/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts
+++ b/boards/enjoydigital/litex_vexriscv/litex_vexriscv.dts
@@ -72,6 +72,10 @@
 	status = "okay";
 };
 
+&i2c1 {
+	status = "okay";
+};
+
 &pwm0 {
 	status = "okay";
 };
diff --git a/boards/espressif/esp32_devkitc_wroom/doc/index.rst b/boards/espressif/esp32_devkitc_wroom/doc/index.rst
index 228660a603a..9b5bc1c6baf 100644
--- a/boards/espressif/esp32_devkitc_wroom/doc/index.rst
+++ b/boards/espressif/esp32_devkitc_wroom/doc/index.rst
@@ -50,45 +50,7 @@ and/or exchanging data over OpenAMP framework. See :zephyr:code-sample-category:
 Supported Features
 ==================
 
-Current Zephyr's ESP32-DevKitC-WROOM board supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| MCPWM      | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| PCNT       | on-chip    | qdec                                |
-+------------+------------+-------------------------------------+
-| SPI DMA    | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| TWAI       | on-chip    | can                                 |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | adc                                 |
-+------------+------------+-------------------------------------+
-| DAC        | on-chip    | dac                                 |
-+------------+------------+-------------------------------------+
-| Wi-Fi      | on-chip    |                                     |
-+------------+------------+-------------------------------------+
-| Bluetooth  | on-chip    |                                     |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 System requirements
 ===================
@@ -110,6 +72,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom-pinctrl.dtsi b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom-pinctrl.dtsi
index b1f03780559..1089af3047e 100644
--- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom-pinctrl.dtsi
+++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2022-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -74,5 +74,35 @@
 			output-high;
 		};
 	};
+
+	i2s0_default: i2s0_default {
+		group1 {
+			pinmux = <I2S0_O_WS_GPIO5>,
+				 <I2S0_O_BCK_GPIO6>,
+				 <I2S0_O_SD_GPIO7>,
+				 <I2S0_I_WS_GPIO15>,
+				 <I2S0_I_BCK_GPIO16>;
+			output-enable;
+		};
+		group2 {
+			pinmux = <I2S0_I_SD_GPIO17>;
+			input-enable;
+		};
+	};
+
+	i2s1_default: i2s1_default {
+		group1 {
+			pinmux = <I2S1_O_WS_GPIO8>,
+				 <I2S1_O_BCK_GPIO3>,
+				 <I2S1_O_SD_GPIO9>,
+				 <I2S1_I_WS_GPIO10>,
+				 <I2S1_I_BCK_GPIO11>;
+			output-enable;
+		};
+		group2 {
+			pinmux = <I2S1_I_SD_GPIO12>;
+			input-enable;
+		};
+	};
 };
 
diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts
index 783a8f2a7f7..e9d5e2855ab 100644
--- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts
+++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2023-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -89,6 +89,18 @@
 	pinctrl-names = "default";
 };
 
+&i2s0 {
+	pinctrl-0 = <&i2s0_default>;
+	pinctrl-names = "default";
+	status = "disabled";
+};
+
+&i2s1 {
+	pinctrl-0 = <&i2s1_default>;
+	pinctrl-names = "default";
+	status = "disabled";
+};
+
 &spi2 {
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -132,3 +144,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.yaml b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.yaml
index 7bc3c8feb55..c3e9af32006 100644
--- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.yaml
+++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu.yaml
@@ -9,6 +9,7 @@ supported:
   - dac
   - gpio
   - i2c
+  - i2s
   - watchdog
   - uart
   - nvs
diff --git a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu_defconfig b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu_defconfig
index 3be2d9e39d5..172a46d1005 100644
--- a/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu_defconfig
+++ b/boards/espressif/esp32_devkitc_wroom/esp32_devkitc_wroom_procpu_defconfig
@@ -1,8 +1,6 @@
 # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/espressif/esp32_devkitc_wrover/doc/index.rst b/boards/espressif/esp32_devkitc_wrover/doc/index.rst
index cf1fb64f32f..5bab845c938 100644
--- a/boards/espressif/esp32_devkitc_wrover/doc/index.rst
+++ b/boards/espressif/esp32_devkitc_wrover/doc/index.rst
@@ -50,45 +50,7 @@ and/or exchanging data over OpenAMP framework. See :zephyr:code-sample-category:
 Supported Features
 ==================
 
-Current Zephyr's ESP32-DevKitC-WROVER board supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| MCPWM      | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| PCNT       | on-chip    | qdec                                |
-+------------+------------+-------------------------------------+
-| SPI DMA    | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| TWAI       | on-chip    | can                                 |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | adc                                 |
-+------------+------------+-------------------------------------+
-| DAC        | on-chip    | dac                                 |
-+------------+------------+-------------------------------------+
-| Wi-Fi      | on-chip    |                                     |
-+------------+------------+-------------------------------------+
-| Bluetooth  | on-chip    |                                     |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 System requirements
 ===================
@@ -110,6 +72,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover-pinctrl.dtsi b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover-pinctrl.dtsi
index f4f51cce98a..dbfd9d07b80 100644
--- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover-pinctrl.dtsi
+++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2022-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -74,4 +74,34 @@
 			output-high;
 		};
 	};
+
+	i2s0_default: i2s0_default {
+		group1 {
+			pinmux = <I2S0_O_WS_GPIO5>,
+				 <I2S0_O_BCK_GPIO6>,
+				 <I2S0_O_SD_GPIO7>,
+				 <I2S0_I_WS_GPIO15>,
+				 <I2S0_I_BCK_GPIO16>;
+			output-enable;
+		};
+		group2 {
+			pinmux = <I2S0_I_SD_GPIO17>;
+			input-enable;
+		};
+	};
+
+	i2s1_default: i2s1_default {
+		group1 {
+			pinmux = <I2S1_O_WS_GPIO8>,
+				 <I2S1_O_BCK_GPIO3>,
+				 <I2S1_O_SD_GPIO9>,
+				 <I2S1_I_WS_GPIO10>,
+				 <I2S1_I_BCK_GPIO11>;
+			output-enable;
+		};
+		group2 {
+			pinmux = <I2S1_I_SD_GPIO12>;
+			input-enable;
+		};
+	};
 };
diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu_defconfig b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu_defconfig
+++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts
index 33f0f3f134b..c91a7178113 100644
--- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts
+++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2023-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -89,6 +89,18 @@
 	pinctrl-names = "default";
 };
 
+&i2s0 {
+	pinctrl-0 = <&i2s0_default>;
+	pinctrl-names = "default";
+	status = "disabled";
+};
+
+&i2s1 {
+	pinctrl-0 = <&i2s1_default>;
+	pinctrl-names = "default";
+	status = "disabled";
+};
+
 &spi2 {
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -128,3 +140,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.yaml b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.yaml
index 62e40f71e93..32de7a52bd3 100644
--- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.yaml
+++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu.yaml
@@ -9,6 +9,7 @@ supported:
   - dac
   - gpio
   - i2c
+  - i2s
   - watchdog
   - uart
   - nvs
diff --git a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu_defconfig b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu_defconfig
index 3be2d9e39d5..172a46d1005 100644
--- a/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu_defconfig
+++ b/boards/espressif/esp32_devkitc_wrover/esp32_devkitc_wrover_procpu_defconfig
@@ -1,8 +1,6 @@
 # Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/espressif/esp32_ethernet_kit/doc/index.rst b/boards/espressif/esp32_ethernet_kit/doc/index.rst
index 7233284d314..22a942989fd 100644
--- a/boards/espressif/esp32_ethernet_kit/doc/index.rst
+++ b/boards/espressif/esp32_ethernet_kit/doc/index.rst
@@ -34,6 +34,13 @@ features FTDI FT2232H chip - an advanced multi-interface USB bridge.
 This chip enables to use JTAG for direct debugging of ESP32 through the
 USB interface without a separate JTAG debugger.
 
+Hardware
+********
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
 
 Functionality Overview
 ======================
@@ -425,6 +432,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit-pinctrl.dtsi b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit-pinctrl.dtsi
index 3e30654db8b..1b6bd6b701c 100644
--- a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit-pinctrl.dtsi
+++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 Grant Ramsay <grant.ramsay@hotmail.com>
+ * Copyright (c) 2022-2025 Grant Ramsay <grant.ramsay@hotmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -40,4 +40,33 @@
 		};
 	};
 
+	i2s0_default: i2s0_default {
+		group1 {
+			pinmux = <I2S0_O_WS_GPIO5>,
+				 <I2S0_O_BCK_GPIO6>,
+				 <I2S0_O_SD_GPIO7>,
+				 <I2S0_I_WS_GPIO15>,
+				 <I2S0_I_BCK_GPIO16>;
+			output-enable;
+		};
+		group2 {
+			pinmux = <I2S0_I_SD_GPIO17>;
+			input-enable;
+		};
+	};
+
+	i2s1_default: i2s1_default {
+		group1 {
+			pinmux = <I2S1_O_WS_GPIO8>,
+				 <I2S1_O_BCK_GPIO3>,
+				 <I2S1_O_SD_GPIO9>,
+				 <I2S1_I_WS_GPIO10>,
+				 <I2S1_I_BCK_GPIO11>;
+			output-enable;
+		};
+		group2 {
+			pinmux = <I2S1_I_SD_GPIO12>;
+			input-enable;
+		};
+	};
 };
diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_appcpu_defconfig b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_appcpu_defconfig
+++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts
index 91446897fc4..bf2fbbd6d3a 100644
--- a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts
+++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 Grant Ramsay <grant.ramsay@hotmail.com>
+ * Copyright (c) 2022-2025 Grant Ramsay <grant.ramsay@hotmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,7 +7,7 @@
 
 #include <espressif/esp32/esp32_wrover_e_n4r8.dtsi>
 #include "esp32_ethernet_kit-pinctrl.dtsi"
-#include <espressif/partitions_0x1000_default.dtsi>
+#include <espressif/partitions_0x1000_amp.dtsi>
 
 / {
 	model = "Espressif ESP32-Ethernet-Kit PROCPU";
@@ -43,6 +43,18 @@
 	status = "okay";
 };
 
+&i2s0 {
+	pinctrl-0 = <&i2s0_default>;
+	pinctrl-names = "default";
+	status = "disabled";
+};
+
+&i2s1 {
+	pinctrl-0 = <&i2s1_default>;
+	pinctrl-names = "default";
+	status = "disabled";
+};
+
 &spi2 {
 	#address-cells = <1>;
 	#size-cells = <0>;
@@ -89,3 +101,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.yaml b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.yaml
index fb3c3cdd704..f6fd5a5f410 100644
--- a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.yaml
+++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu.yaml
@@ -10,4 +10,5 @@ supported:
   - uart
   - nvs
   - pwm
+  - i2s
 vendor: espressif
diff --git a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu_defconfig b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu_defconfig
index f029cac9e9e..e192c240251 100644
--- a/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu_defconfig
+++ b/boards/espressif/esp32_ethernet_kit/esp32_ethernet_kit_procpu_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/espressif/esp32c3_devkitc/doc/index.rst b/boards/espressif/esp32c3_devkitc/doc/index.rst
index a57d0be2623..eae08a6b8fc 100644
--- a/boards/espressif/esp32c3_devkitc/doc/index.rst
+++ b/boards/espressif/esp32c3_devkitc/doc/index.rst
@@ -42,41 +42,7 @@ manual at `ESP32-C3 Technical Reference Manual`_.
 Supported Features
 ==================
 
-Current Zephyr's ESP32-C3-DevKitC board supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| SPI DMA    | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| TWAI       | on-chip    | can                                 |
-+------------+------------+-------------------------------------+
-| USB-CDC    | on-chip    | serial                              |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | adc                                 |
-+------------+------------+-------------------------------------+
-| Wi-Fi      | on-chip    |                                     |
-+------------+------------+-------------------------------------+
-| Bluetooth  | on-chip    |                                     |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 System requirements
 *******************
@@ -98,6 +64,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.dts b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.dts
index 86326fcc077..ec61f303a6c 100644
--- a/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.dts
+++ b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc.dts
@@ -97,3 +97,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/espressif/esp32c3_devkitc/esp32c3_devkitc_defconfig b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc_defconfig
index ef633ce56a1..187793c76e8 100644
--- a/boards/espressif/esp32c3_devkitc/esp32c3_devkitc_defconfig
+++ b/boards/espressif/esp32c3_devkitc/esp32c3_devkitc_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/espressif/esp32c3_devkitm/doc/index.rst b/boards/espressif/esp32c3_devkitm/doc/index.rst
index 24eb23bc7b8..d4fcb4e1713 100644
--- a/boards/espressif/esp32c3_devkitm/doc/index.rst
+++ b/boards/espressif/esp32c3_devkitm/doc/index.rst
@@ -42,41 +42,7 @@ manual at `ESP32-C3 Technical Reference Manual`_.
 Supported Features
 ==================
 
-Current Zephyr's ESP32-C3-Devkitm board supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| SPI DMA    | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| TWAI       | on-chip    | can                                 |
-+------------+------------+-------------------------------------+
-| USB-CDC    | on-chip    | serial                              |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | adc                                 |
-+------------+------------+-------------------------------------+
-| Wi-Fi      | on-chip    |                                     |
-+------------+------------+-------------------------------------+
-| Bluetooth  | on-chip    |                                     |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 System requirements
 *******************
@@ -98,6 +64,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts
index 25bd583daee..2e1b41edfc1 100644
--- a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts
+++ b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm.dts
@@ -103,3 +103,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm_defconfig b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm_defconfig
index ef633ce56a1..187793c76e8 100644
--- a/boards/espressif/esp32c3_devkitm/esp32c3_devkitm_defconfig
+++ b/boards/espressif/esp32c3_devkitm/esp32c3_devkitm_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/espressif/esp32c3_rust/doc/index.rst b/boards/espressif/esp32c3_rust/doc/index.rst
index a6f41a01866..144b6948b85 100644
--- a/boards/espressif/esp32c3_rust/doc/index.rst
+++ b/boards/espressif/esp32c3_rust/doc/index.rst
@@ -42,41 +42,7 @@ manual at `ESP32-C3 Technical Reference Manual`_.
 Supported Features
 ==================
 
-Current Zephyr's ESP32-C3-DevKit-RUST board supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| SPI DMA    | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| TWAI       | on-chip    | can                                 |
-+------------+------------+-------------------------------------+
-| USB-CDC    | on-chip    | serial                              |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | adc                                 |
-+------------+------------+-------------------------------------+
-| Wi-Fi      | on-chip    |                                     |
-+------------+------------+-------------------------------------+
-| Bluetooth  | on-chip    |                                     |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 I2C Peripherals
 ===============
@@ -143,6 +109,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/espressif/esp32c3_rust/esp32c3_rust.dts b/boards/espressif/esp32c3_rust/esp32c3_rust.dts
index 867fa84adcf..9c931e91f57 100644
--- a/boards/espressif/esp32c3_rust/esp32c3_rust.dts
+++ b/boards/espressif/esp32c3_rust/esp32c3_rust.dts
@@ -128,3 +128,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/espressif/esp32c3_rust/esp32c3_rust_defconfig b/boards/espressif/esp32c3_rust/esp32c3_rust_defconfig
index a0483fa8a08..147089fe70e 100644
--- a/boards/espressif/esp32c3_rust/esp32c3_rust_defconfig
+++ b/boards/espressif/esp32c3_rust/esp32c3_rust_defconfig
@@ -1,8 +1,6 @@
 # Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/espressif/esp32c6_devkitc/Kconfig b/boards/espressif/esp32c6_devkitc/Kconfig
index c6a99b1032d..e24ba970a9b 100644
--- a/boards/espressif/esp32c6_devkitc/Kconfig
+++ b/boards/espressif/esp32c6_devkitc/Kconfig
@@ -3,4 +3,5 @@
 
 config HEAP_MEM_POOL_ADD_SIZE_BOARD
 	int
-	default 4096
+	default 4096 if BOARD_ESP32C6_DEVKITC_ESP32C6_HPCORE
+	default 256 if BOARD_ESP32C6_DEVKITC_ESP32C6_LPCORE
diff --git a/boards/espressif/esp32c6_devkitc/Kconfig.esp32c6_devkitc b/boards/espressif/esp32c6_devkitc/Kconfig.esp32c6_devkitc
index 4bd1fce4efc..9b30251fea4 100644
--- a/boards/espressif/esp32c6_devkitc/Kconfig.esp32c6_devkitc
+++ b/boards/espressif/esp32c6_devkitc/Kconfig.esp32c6_devkitc
@@ -5,3 +5,5 @@
 
 config BOARD_ESP32C6_DEVKITC
 	select SOC_ESP32_C6_WROOM_1U_N8
+	select SOC_ESP32C6_HPCORE if BOARD_ESP32C6_DEVKITC_ESP32C6_HPCORE
+	select SOC_ESP32C6_LPCORE if BOARD_ESP32C6_DEVKITC_ESP32C6_LPCORE
diff --git a/boards/espressif/esp32c6_devkitc/doc/index.rst b/boards/espressif/esp32c6_devkitc/doc/index.rst
index ecbc4573360..ee0f04afaa7 100644
--- a/boards/espressif/esp32c6_devkitc/doc/index.rst
+++ b/boards/espressif/esp32c6_devkitc/doc/index.rst
@@ -84,41 +84,7 @@ manual at `ESP32-C6 Technical Reference Manual`_.
 Supported Features
 ==================
 
-Current Zephyr's ESP32-C6-DevKitC board supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| I2C        | on-chip    | i2c                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| MCPWM      | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| SPI DMA    | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| GDMA       | on-chip    | dma                                 |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| USB-CDC    | on-chip    | serial                              |
-+------------+------------+-------------------------------------+
-| Wi-Fi      | on-chip    |                                     |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 System requirements
 *******************
@@ -140,6 +106,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
@@ -181,7 +149,7 @@ To build the sample application using sysbuild use the command:
 .. zephyr-app-commands::
    :tool: west
    :zephyr-app: samples/hello_world
-   :board: esp32c6_devkitc
+   :board: esp32c6_devkitc/esp32c6/hpcore
    :goals: build
    :west-args: --sysbuild
    :compact:
@@ -230,7 +198,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: esp32c6_devkitc
+   :board: esp32c6_devkitc/esp32c6/hpcore
    :goals: build
 
 The usual ``flash`` target will work with the ``esp32c6_devkitc`` board
@@ -239,7 +207,7 @@ application.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: esp32c6_devkitc
+   :board: esp32c6_devkitc/esp32c6/hpcore
    :goals: flash
 
 Open the serial monitor using the following command:
@@ -254,7 +222,7 @@ message in the monitor:
 .. code-block:: console
 
    ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
-   Hello World! esp32c6_devkitc
+   Hello World! esp32c6_devkitc/esp32c6/hpcore
 
 Debugging
 *********
@@ -271,7 +239,7 @@ Here is an example for building the :zephyr:code-sample:`hello_world` applicatio
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: esp32c6_devkitc
+   :board: esp32c6_devkitc/esp32c6/hpcore
    :goals: build flash
    :gen-args: -DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>
 
@@ -279,9 +247,32 @@ You can debug an application in the usual way. Here is an example for the :zephy
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: esp32c6_devkitc
+   :board: esp32c6_devkitc/esp32c6/hpcore
    :goals: debug
 
+Low-Power CPU (LP CORE)
+***********************
+
+The ESP32-C6 SoC has two RISC-V cores: the High-Performance Core (HP CORE) and the Low-Power Core (LP CORE).
+The LP Core features ultra low power consumption, an interrupt controller, a debug module and a system bus
+interface for memory and peripheral access.
+
+The LP Core is in sleep mode by default. It has two application scenarios:
+
+- Power insensitive scenario: When the High-Performance CPU (HP Core) is active, the LP Core can assist the HP CPU with some speed and efficiency-insensitive controls and computations.
+- Power sensitive scenario: When the HP CPU is in the power-down state to save power, the LP Core can be woken up to handle some external wake-up events.
+
+For more information, check the datasheet at `ESP32-C6 Datasheet`_ or the technical reference
+manual at `ESP32-C6 Technical Reference Manual`_.
+
+The LP Core support is fully integrated with :ref:`sysbuild`. The user can enable the LP Core by adding
+the following configuration to the project:
+
+.. code:: cfg
+
+   CONFIG_ULP_COPROC_ENABLED=y
+
+See :zephyr:code-sample-category:`lp-core` folder as code reference.
 
 References
 **********
diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.dts b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.dts
deleted file mode 100644
index 896ae30530c..00000000000
--- a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.dts
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/dts-v1/;
-
-#include <espressif/esp32c6/esp32c6_wroom_n8.dtsi>
-#include "esp32c6_devkitc-pinctrl.dtsi"
-#include <zephyr/dt-bindings/input/input-event-codes.h>
-#include <espressif/partitions_0x0_default.dtsi>
-
-/ {
-	model = "esp32c6_devkitc";
-	compatible = "espressif,esp32c6";
-
-	chosen {
-		zephyr,sram = &sramhp;
-		zephyr,console = &uart0;
-		zephyr,shell-uart = &uart0;
-		zephyr,flash = &flash0;
-		zephyr,code-partition = &slot0_partition;
-	};
-
-	aliases {
-		sw0 = &user_button1;
-		watchdog0 = &wdt0;
-	};
-
-	gpio_keys {
-		compatible = "gpio-keys";
-		user_button1: button_1 {
-			label = "User SW1";
-			gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
-			zephyr,code = <INPUT_KEY_0>;
-		};
-	};
-};
-
-&uart0 {
-	status = "okay";
-	current-speed = <115200>;
-	pinctrl-0 = <&uart0_default>;
-	pinctrl-names = "default";
-};
-
-&trng0 {
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-	pinctrl-0 = <&i2c0_default>;
-	pinctrl-names = "default";
-};
-
-&spi2 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "okay";
-	pinctrl-0 = <&spim2_default>;
-	pinctrl-names = "default";
-};
-
-&gpio0 {
-	status = "okay";
-};
-
-&wdt0 {
-	status = "okay";
-};
diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.yaml b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.yaml
deleted file mode 100644
index f36685e8367..00000000000
--- a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc.yaml
+++ /dev/null
@@ -1,17 +0,0 @@
-identifier: esp32c6_devkitc
-name: ESP32-C6
-vendor: espressif
-type: mcu
-arch: riscv
-toolchain:
-  - zephyr
-supported:
-  - gpio
-  - watchdog
-  - uart
-  - dma
-  - pwm
-  - spi
-  - counter
-  - entropy
-  - i2c
diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_defconfig b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_defconfig
deleted file mode 100644
index 6539bd42e59..00000000000
--- a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_MAIN_STACK_SIZE=2048
-CONFIG_CONSOLE=y
-CONFIG_SERIAL=y
-CONFIG_UART_CONSOLE=y
-CONFIG_GPIO=y
diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc-pinctrl.dtsi b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore-pinctrl.dtsi
similarity index 100%
rename from boards/espressif/esp32c6_devkitc/esp32c6_devkitc-pinctrl.dtsi
rename to boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore-pinctrl.dtsi
diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.dts b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.dts
new file mode 100644
index 00000000000..ef8dbea59b3
--- /dev/null
+++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.dts
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <espressif/esp32c6/esp32c6_wroom_n8.dtsi>
+#include "esp32c6_devkitc_hpcore-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <espressif/partitions_0x0_default.dtsi>
+
+/ {
+	model = "esp32c6_devkitc HP Core";
+	compatible = "espressif,esp32c6";
+
+	chosen {
+		zephyr,sram = &sramhp;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+	};
+
+	aliases {
+		sw0 = &user_button1;
+		watchdog0 = &wdt0;
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button1: button_1 {
+			label = "User SW1";
+			gpios = <&gpio0 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-names = "default";
+};
+
+&trng0 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+};
+
+&spi2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	pinctrl-0 = <&spim2_default>;
+	pinctrl-names = "default";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&wdt0 {
+	status = "okay";
+};
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.yaml b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.yaml
new file mode 100644
index 00000000000..6eed11176b0
--- /dev/null
+++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore.yaml
@@ -0,0 +1,21 @@
+identifier: esp32c6_devkitc/esp32c6/hpcore
+name: ESP32-C6-DevKitC HP Core
+vendor: espressif
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+supported:
+  - adc
+  - gpio
+  - watchdog
+  - uart
+  - dma
+  - pwm
+  - spi
+  - counter
+  - entropy
+  - i2c
+testing:
+  ignore_tags:
+    - bluetooth
diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore_defconfig b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore_defconfig
new file mode 100644
index 00000000000..187793c76e8
--- /dev/null
+++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_hpcore_defconfig
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y
diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore.dts b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore.dts
new file mode 100644
index 00000000000..739781e692b
--- /dev/null
+++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore.dts
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <espressif/esp32c6/esp32c6_lpcore_wroom_n4.dtsi>
+#include <espressif/partitions_0x0_default.dtsi>
+
+/ {
+	model = "Espressif ESP32C6-DevkitC LPCORE";
+	compatible = "espressif,esp32c6";
+
+	chosen {
+		zephyr,sram = &sramlp;
+		zephyr,code-partition = &slot0_lpcore_partition;
+		zephyr,console = &lp_uart;
+		zephyr,shell-uart = &lp_uart;
+	};
+};
+
+&lp_uart {
+	status = "okay";
+	current-speed = <115200>;
+};
diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore.yaml b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore.yaml
new file mode 100644
index 00000000000..49e25bcdba0
--- /dev/null
+++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore.yaml
@@ -0,0 +1,19 @@
+identifier: esp32c6_devkitc/esp32c6/lpcore
+name: ESP32-C6-DevKitC LP Core
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+supported:
+  - cpu
+  - uart
+  - serial
+testing:
+  only_tags:
+    - introduction
+  ignore_tags:
+    - kernel
+    - posix
+    - chre
+    - cpp
+vendor: espressif
diff --git a/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore_defconfig b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore_defconfig
new file mode 100644
index 00000000000..42ee26028f9
--- /dev/null
+++ b/boards/espressif/esp32c6_devkitc/esp32c6_devkitc_lpcore_defconfig
@@ -0,0 +1,19 @@
+# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+# Memory protection
+CONFIG_THREAD_STACK_INFO=n
+CONFIG_THREAD_CUSTOM_DATA=n
+
+# Boot
+CONFIG_BOOT_BANNER=n
+
+# Console
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_PRINTK=n
+CONFIG_CBPRINTF_NANO=y
+
+# Build
+CONFIG_SIZE_OPTIMIZATIONS=y
diff --git a/boards/espressif/esp32s2_devkitc/doc/index.rst b/boards/espressif/esp32s2_devkitc/doc/index.rst
index e5cb0ff6191..63bf3eca409 100644
--- a/boards/espressif/esp32s2_devkitc/doc/index.rst
+++ b/boards/espressif/esp32s2_devkitc/doc/index.rst
@@ -41,39 +41,7 @@ manual at `ESP32-S2 Technical Reference Manual`_.
 Supported Features
 ==================
 
-Current Zephyr's ESP32-S2-devkitc board supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| PCNT       | on-chip    | qdec                                |
-+------------+------------+-------------------------------------+
-| SPI DMA    | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | adc                                 |
-+------------+------------+-------------------------------------+
-| DAC        | on-chip    | dac                                 |
-+------------+------------+-------------------------------------+
-| Wi-Fi      | on-chip    |                                     |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 System requirements
 ===================
@@ -95,6 +63,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc-pinctrl.dtsi b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc-pinctrl.dtsi
index 756aaf9b5b7..434260d9486 100644
--- a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc-pinctrl.dtsi
+++ b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -65,4 +65,19 @@
 		};
 	};
 
+	i2s0_default: i2s0_default {
+		group1 {
+			pinmux = <I2S0_MCLK_GPIO4>,
+				 <I2S0_O_WS_GPIO5>,
+				 <I2S0_O_BCK_GPIO6>,
+				 <I2S0_O_SD_GPIO7>,
+				 <I2S0_I_WS_GPIO15>,
+				 <I2S0_I_BCK_GPIO16>;
+			output-enable;
+		};
+		group2 {
+			pinmux = <I2S0_I_SD_GPIO17>;
+			input-enable;
+		};
+	};
 };
diff --git a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts
index 9038cea4a1e..337a63b6b56 100644
--- a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts
+++ b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -23,7 +23,7 @@
 	};
 
 	chosen {
-		zephyr,sram = &sram0;
+		zephyr,sram = &sram1;
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
 		zephyr,flash = &flash0;
@@ -96,6 +96,12 @@
 	pinctrl-names = "default";
 };
 
+&i2s0 {
+	pinctrl-0 = <&i2s0_default>;
+	pinctrl-names = "default";
+	status = "disabled";
+};
+
 &trng0 {
 	status = "okay";
 };
@@ -123,3 +129,7 @@
 &dac {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.yaml b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.yaml
index 44a6f971e3b..b3598a28d9c 100644
--- a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.yaml
+++ b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc.yaml
@@ -9,6 +9,7 @@ supported:
   - dac
   - gpio
   - i2c
+  - i2s
   - watchdog
   - uart
   - nvs
@@ -19,4 +20,7 @@ supported:
   - input
   - can
   - dma
+testing:
+  ignore_tags:
+    - bluetooth
 vendor: espressif
diff --git a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc_defconfig b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc_defconfig
index f029cac9e9e..e192c240251 100644
--- a/boards/espressif/esp32s2_devkitc/esp32s2_devkitc_defconfig
+++ b/boards/espressif/esp32s2_devkitc/esp32s2_devkitc_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/espressif/esp32s2_saola/doc/index.rst b/boards/espressif/esp32s2_saola/doc/index.rst
index a2ad776acfe..d86a986b5e6 100644
--- a/boards/espressif/esp32s2_saola/doc/index.rst
+++ b/boards/espressif/esp32s2_saola/doc/index.rst
@@ -41,39 +41,7 @@ manual at `ESP32-S2 Technical Reference Manual`_.
 Supported Features
 ==================
 
-Current Zephyr's ESP32-S2-Saola board supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| PCNT       | on-chip    | qdec                                |
-+------------+------------+-------------------------------------+
-| SPI DMA    | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | adc                                 |
-+------------+------------+-------------------------------------+
-| DAC        | on-chip    | dac                                 |
-+------------+------------+-------------------------------------+
-| Wi-Fi      | on-chip    |                                     |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 System requirements
 ===================
@@ -95,6 +63,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/espressif/esp32s2_saola/esp32s2_saola-pinctrl.dtsi b/boards/espressif/esp32s2_saola/esp32s2_saola-pinctrl.dtsi
index 7ab4fc67119..5b402c838cf 100644
--- a/boards/espressif/esp32s2_saola/esp32s2_saola-pinctrl.dtsi
+++ b/boards/espressif/esp32s2_saola/esp32s2_saola-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2022-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -65,4 +65,19 @@
 		};
 	};
 
+	i2s0_default: i2s0_default {
+		group1 {
+			pinmux = <I2S0_MCLK_GPIO4>,
+				 <I2S0_O_WS_GPIO5>,
+				 <I2S0_O_BCK_GPIO6>,
+				 <I2S0_O_SD_GPIO7>,
+				 <I2S0_I_WS_GPIO15>,
+				 <I2S0_I_BCK_GPIO16>;
+			output-enable;
+		};
+		group2 {
+			pinmux = <I2S0_I_SD_GPIO17>;
+			input-enable;
+		};
+	};
 };
diff --git a/boards/espressif/esp32s2_saola/esp32s2_saola.dts b/boards/espressif/esp32s2_saola/esp32s2_saola.dts
index c97108951ab..23249ceb3f6 100644
--- a/boards/espressif/esp32s2_saola/esp32s2_saola.dts
+++ b/boards/espressif/esp32s2_saola/esp32s2_saola.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2021-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -23,7 +23,7 @@
 	};
 
 	chosen {
-		zephyr,sram = &sram0;
+		zephyr,sram = &sram1;
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
 		zephyr,flash = &flash0;
@@ -96,6 +96,12 @@
 	pinctrl-names = "default";
 };
 
+&i2s0 {
+	pinctrl-0 = <&i2s0_default>;
+	pinctrl-names = "default";
+	status = "disabled";
+};
+
 &trng0 {
 	status = "okay";
 };
@@ -119,3 +125,7 @@
 &wdt0 {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/espressif/esp32s2_saola/esp32s2_saola.yaml b/boards/espressif/esp32s2_saola/esp32s2_saola.yaml
index bebe2a293a8..e8a37ffd2ed 100644
--- a/boards/espressif/esp32s2_saola/esp32s2_saola.yaml
+++ b/boards/espressif/esp32s2_saola/esp32s2_saola.yaml
@@ -9,6 +9,7 @@ supported:
   - dac
   - gpio
   - i2c
+  - i2s
   - watchdog
   - uart
   - nvs
@@ -17,4 +18,7 @@ supported:
   - counter
   - entropy
   - input
+testing:
+  ignore_tags:
+    - bluetooth
 vendor: espressif
diff --git a/boards/espressif/esp32s2_saola/esp32s2_saola_defconfig b/boards/espressif/esp32s2_saola/esp32s2_saola_defconfig
index 5476839e2ba..e192c240251 100644
--- a/boards/espressif/esp32s2_saola/esp32s2_saola_defconfig
+++ b/boards/espressif/esp32s2_saola/esp32s2_saola_defconfig
@@ -1,8 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/espressif/esp32s3_devkitc/doc/index.rst b/boards/espressif/esp32s3_devkitc/doc/index.rst
index 008b64fecae..4d5b07797a2 100644
--- a/boards/espressif/esp32s3_devkitc/doc/index.rst
+++ b/boards/espressif/esp32s3_devkitc/doc/index.rst
@@ -81,41 +81,7 @@ manual at `ESP32-S3 Technical Reference Manual`_.
 Supported Features
 ==================
 
-Current Zephyr's ESP32-S3-DevKitC board supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| TWAI/CAN   | on-chip    | can                                 |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | adc                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| MCPWM      | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| PCNT       | on-chip    | qdec                                |
-+------------+------------+-------------------------------------+
-| GDMA       | on-chip    | dma                                 |
-+------------+------------+-------------------------------------+
-| USB-CDC    | on-chip    | serial                              |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Prerequisites
 -------------
@@ -134,6 +100,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_appcpu_defconfig b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_appcpu_defconfig
+++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts
index 48806ab5a4c..a7dec600f43 100644
--- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts
+++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu.dts
@@ -147,3 +147,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu_defconfig b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu_defconfig
index d789bab1824..d8fbaa87925 100644
--- a/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu_defconfig
+++ b/boards/espressif/esp32s3_devkitc/esp32s3_devkitc_procpu_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/espressif/esp32s3_devkitm/doc/index.rst b/boards/espressif/esp32s3_devkitm/doc/index.rst
index ada774ec2a1..044a3a6a660 100644
--- a/boards/espressif/esp32s3_devkitm/doc/index.rst
+++ b/boards/espressif/esp32s3_devkitm/doc/index.rst
@@ -81,41 +81,7 @@ manual at `ESP32-S3 Technical Reference Manual`_.
 Supported Features
 ==================
 
-Current Zephyr's ESP32-S3-DevKitM board supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| TWAI/CAN   | on-chip    | can                                 |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | adc                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| MCPWM      | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| PCNT       | on-chip    | qdec                                |
-+------------+------------+-------------------------------------+
-| GDMA       | on-chip    | dma                                 |
-+------------+------------+-------------------------------------+
-| USB-CDC    | on-chip    | serial                              |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Prerequisites
 -------------
@@ -134,6 +100,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu_defconfig b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu_defconfig
deleted file mode 100644
index 1ac2b1c55c9..00000000000
--- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_appcpu_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_MAIN_STACK_SIZE=4096
diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts
index 89c5b8c1641..c468871e25e 100644
--- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts
+++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu.dts
@@ -147,3 +147,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu_defconfig b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu_defconfig
index 92308aa841b..d8fbaa87925 100644
--- a/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu_defconfig
+++ b/boards/espressif/esp32s3_devkitm/esp32s3_devkitm_procpu_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=4096
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/espressif/esp32s3_eye/doc/index.rst b/boards/espressif/esp32s3_eye/doc/index.rst
index 662c4e51998..e7b7643cbba 100644
--- a/boards/espressif/esp32s3_eye/doc/index.rst
+++ b/boards/espressif/esp32s3_eye/doc/index.rst
@@ -17,6 +17,11 @@ ESP32-S3-WROOM-1 module, camera, SD card slot, digital microphone, USB port, and
 and the sub board (ESP32-S3-EYE-SUB) that contains an LCD display.
 The main board and sub board are connected through pin headers.
 
+Supported Features
+------------------
+
+.. zephyr:board-supported-hw::
+
 Block Diagram
 -------------
 
@@ -130,6 +135,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 -----------
 
diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu_defconfig b/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu_defconfig
+++ b/boards/espressif/esp32s3_eye/esp32s3_eye_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts
index 1b2afa8b83a..7391ad2357e 100644
--- a/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts
+++ b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu.dts
@@ -204,3 +204,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/espressif/esp32s3_eye/esp32s3_eye_procpu_defconfig b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu_defconfig
index 6c24dead95b..32d7051fab4 100644
--- a/boards/espressif/esp32s3_eye/esp32s3_eye_procpu_defconfig
+++ b/boards/espressif/esp32s3_eye/esp32s3_eye_procpu_defconfig
@@ -1,6 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=4096
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/espressif/esp8684_devkitm/doc/index.rst b/boards/espressif/esp8684_devkitm/doc/index.rst
index 1b20435c586..c5e00b5b5b4 100644
--- a/boards/espressif/esp8684_devkitm/doc/index.rst
+++ b/boards/espressif/esp8684_devkitm/doc/index.rst
@@ -46,31 +46,7 @@ For detailed information check `ESP8684 Technical Reference Manual`_.
 Supported Features
 ==================
 
-Current Zephyr's ESP8684-DevKitM board supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Wi-Fi      | on-chip    |                                     |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| SPI DMA    | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 For a getting started user guide, please check `ESP8684-DevKitM User Guide`_.
 
@@ -94,6 +70,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts b/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts
index a6a76ac4756..8081d955c8f 100644
--- a/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts
+++ b/boards/espressif/esp8684_devkitm/esp8684_devkitm.dts
@@ -60,3 +60,7 @@
 &timer0 {
 	status = "disabled";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml b/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml
index 3344e8d5e2c..870622d948c 100644
--- a/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml
+++ b/boards/espressif/esp8684_devkitm/esp8684_devkitm.yaml
@@ -5,6 +5,7 @@ arch: riscv
 toolchain:
   - zephyr
 supported:
+  - adc
   - gpio
   - watchdog
   - uart
diff --git a/boards/espressif/esp8684_devkitm/esp8684_devkitm_defconfig b/boards/espressif/esp8684_devkitm/esp8684_devkitm_defconfig
index ef633ce56a1..187793c76e8 100644
--- a/boards/espressif/esp8684_devkitm/esp8684_devkitm_defconfig
+++ b/boards/espressif/esp8684_devkitm/esp8684_devkitm_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/espressif/esp_wrover_kit/doc/index.rst b/boards/espressif/esp_wrover_kit/doc/index.rst
index 96f1c0570c2..0c5a2ee8dd4 100644
--- a/boards/espressif/esp_wrover_kit/doc/index.rst
+++ b/boards/espressif/esp_wrover_kit/doc/index.rst
@@ -441,45 +441,7 @@ Turn the Power Switch to ON, the 5V Power On LED should light up.
 Supported Features
 ==================
 
-Current Zephyr's ESP32-Wrover-Kit board supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| MCPWM      | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| PCNT       | on-chip    | qdec                                |
-+------------+------------+-------------------------------------+
-| SPI DMA    | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| TWAI       | on-chip    | can                                 |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | adc                                 |
-+------------+------------+-------------------------------------+
-| DAC        | on-chip    | dac                                 |
-+------------+------------+-------------------------------------+
-| Wi-Fi      | on-chip    |                                     |
-+------------+------------+-------------------------------------+
-| Bluetooth  | on-chip    |                                     |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 System requirements
 ===================
@@ -501,6 +463,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_appcpu_defconfig b/boards/espressif/esp_wrover_kit/esp_wrover_kit_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/espressif/esp_wrover_kit/esp_wrover_kit_appcpu_defconfig
+++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts b/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts
index 614bd1ec54f..552829c4c52 100644
--- a/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts
+++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu.dts
@@ -218,3 +218,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu_defconfig b/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu_defconfig
index f029cac9e9e..e192c240251 100644
--- a/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu_defconfig
+++ b/boards/espressif/esp_wrover_kit/esp_wrover_kit_procpu_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/ezurio/bl5340_dvk/Kconfig.defconfig b/boards/ezurio/bl5340_dvk/Kconfig.defconfig
index b71b51265b9..2f93c265e0a 100644
--- a/boards/ezurio/bl5340_dvk/Kconfig.defconfig
+++ b/boards/ezurio/bl5340_dvk/Kconfig.defconfig
@@ -72,9 +72,6 @@ config BT_HCI_VS
 # https://www.buydisplay.com/2-8-inch-tft-touch-shield-for-arduino-w-capacitive-touch-screen-module
 if DISPLAY
 
-config INPUT_FT5336_INTERRUPT
-	default y
-
 if LVGL
 
 config LV_Z_VDB_SIZE
diff --git a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml
index cf432d7ab6e..5237c073ffa 100644
--- a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml
+++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 448
 flash: 1024
diff --git a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml
index 89d29c79e05..9bbf93a52d2 100644
--- a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml
+++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpuapp_ns.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 192
 flash: 192
diff --git a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml
index ab6f60bdd3a..99e7ee5a37e 100644
--- a/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml
+++ b/boards/ezurio/bl5340_dvk/bl5340_dvk_nrf5340_cpunet.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 64
 flash: 256
diff --git a/boards/ezurio/bl5340_dvk/doc/index.rst b/boards/ezurio/bl5340_dvk/doc/index.rst
index b19a0516c30..35ce806fc53 100644
--- a/boards/ezurio/bl5340_dvk/doc/index.rst
+++ b/boards/ezurio/bl5340_dvk/doc/index.rst
@@ -56,78 +56,8 @@ is 32MHz.
 Supported Features
 ==================
 
-The ``bl5340_dvk/nrf5340/cpuapp`` board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| QSPI(M)   | on-chip    | nor                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| SPU       | on-chip    | system protection    |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-The ``bl5340_dvk/nrf5340/cpunet`` board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `Nordic Semiconductor Infocenter`_
 for a complete list of hardware features.
 
@@ -261,6 +191,8 @@ Security components
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The BL5340's application core supports the Armv8-M Security Extension.
 Applications built for the ``bl5340_dvk/nrf5340/cpuapp`` board by default
 boot in the Secure state.
diff --git a/boards/ezurio/bl54l15_dvk/Kconfig b/boards/ezurio/bl54l15_dvk/Kconfig
new file mode 100644
index 00000000000..412d5c5b3dd
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/Kconfig
@@ -0,0 +1,31 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# BL54L15 DVK board configuration
+
+if BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS
+
+DT_NRF_MPC := $(dt_nodelabel_path,nrf_mpc)
+
+config NRF_TRUSTZONE_FLASH_REGION_SIZE
+	hex
+	default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity)
+	help
+	  This defines the flash region size from the TrustZone perspective.
+	  It is used when configuring the TrustZone and when setting alignments
+	  requirements for the partitions.
+	  This abstraction allows us to configure TrustZone without depending
+	  on peripheral-specific symbols.
+
+config NRF_TRUSTZONE_RAM_REGION_SIZE
+	hex
+	default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity)
+	help
+	  This defines the RAM region size from the TrustZone perspective.
+	  It is used when configuring the TrustZone and when setting alignments
+	  requirements for the partitions.
+	  This abstraction allows us to configure TrustZone without depending
+	  on peripheral specific symbols.
+
+endif # BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS
diff --git a/boards/ezurio/bl54l15_dvk/Kconfig.bl54l15_dvk b/boards/ezurio/bl54l15_dvk/Kconfig.bl54l15_dvk
new file mode 100644
index 00000000000..739ab7de8a5
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/Kconfig.bl54l15_dvk
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_BL54L15_DVK
+	select SOC_NRF54L10_CPUAPP if BOARD_BL54L15_DVK_NRF54L10_CPUAPP || BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS
+	select SOC_NRF54L15_CPUAPP if BOARD_BL54L15_DVK_NRF54L15_CPUAPP || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS
+	select SOC_NRF54L15_CPUFLPR if BOARD_BL54L15_DVK_NRF54L15_CPUFLPR || \
+					    BOARD_BL54L15_DVK_NRF54L15_CPUFLPR_XIP
diff --git a/boards/ezurio/bl54l15_dvk/Kconfig.defconfig b/boards/ezurio/bl54l15_dvk/Kconfig.defconfig
new file mode 100644
index 00000000000..61d46eebccf
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/Kconfig.defconfig
@@ -0,0 +1,32 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
+DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition
+
+if BOARD_BL54L15_DVK_NRF54L10_CPUAPP || BOARD_BL54L15_DVK_NRF54L15_CPUAPP
+
+config ROM_START_OFFSET
+	default 0x800 if BOOTLOADER_MCUBOOT
+
+endif # BOARD_BL54L15_DVK_NRF54L10_CPUAPP || BOARD_BL54L15_DVK_NRF54L15_CPUAPP
+
+if BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS
+
+config BT_CTLR
+	default BT
+
+config FLASH_LOAD_OFFSET
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+config FLASH_LOAD_SIZE
+	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+# By default, if we build for a Non-Secure version of the board,
+# enable building with TF-M as the Secure Execution Environment.
+config BUILD_WITH_TFM
+	default y
+
+endif # BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS || BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_common.dtsi b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_common.dtsi
new file mode 100644
index 00000000000..62aa39437b8
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_common.dtsi
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15_dvk_nrf54l_10_15-pinctrl.dtsi"
+
+/ {
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led_0 {
+			gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 0";
+		};
+
+		led1: led_1 {
+			gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 1";
+		};
+
+		led2: led_2 {
+			gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 2";
+		};
+
+		led3: led_3 {
+			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 3";
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		/*
+		 * PWM signal can be exposed on GPIO pin only within same domain.
+		 * There is only one domain which contains both PWM and GPIO:
+		 * PWM20/21/22 and GPIO Port P1.
+		 * Only LEDs connected to P1 can work with PWM, for example LED1.
+		 */
+		pwm_led1: pwm_led_1 {
+			pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		button0: button_0 {
+			gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 0";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		button1: button_1 {
+			gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 1";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+
+		button2: button_2 {
+			gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 2";
+			zephyr,code = <INPUT_KEY_2>;
+		};
+
+		button3: button_3 {
+			gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 3";
+			zephyr,code = <INPUT_KEY_3>;
+		};
+	};
+
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		led2 = &led2;
+		led3 = &led3;
+		pwm-led0 = &pwm_led1;
+		sw0 = &button0;
+		sw1 = &button1;
+		sw2 = &button2;
+		sw3 = &button3;
+		watchdog0 = &wdt31;
+	};
+};
+
+&uart20 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart20_default>;
+	pinctrl-1 = <&uart20_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&uart30 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart30_default>;
+	pinctrl-1 = <&uart30_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&pwm20 {
+	status = "okay";
+	pinctrl-0 = <&pwm20_default>;
+	pinctrl-1 = <&pwm20_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+/* Get a node label for wi-fi spi to use in shield files */
+wifi_spi: &spi22 {};
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.dts
new file mode 100644
index 00000000000..3d9336bbeab
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.dts
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nordic/nrf54l10_cpuapp.dtsi>
+#include "nrf54l_10_15_cpuapp_common.dtsi"
+
+/ {
+	compatible = "ezurio,bl54l15_dvk_nrf54l10-cpuapp";
+	model = "Ezurio BL54L15 DVK nRF54L10 Application MCU";
+
+	chosen {
+		zephyr,code-partition = &slot0_partition;
+		zephyr,sram = &cpuapp_sram;
+	};
+};
+
+/* FLPR not supported yet, give all SRAM and RRAM to the APP core */
+&cpuapp_sram {
+	reg = <0x20000000 DT_SIZE_K(192)>;
+	ranges = <0x0 0x20000000 DT_SIZE_K(192)>;
+};
+
+&cpuapp_rram {
+	reg = <0x0 DT_SIZE_K(1022)>;
+};
+
+/* These partition sizes assume no FLPR area in RRAM */
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		slot0_partition: partition@10000 {
+			label = "image-0";
+			reg = <0x10000 DT_SIZE_K(224)>;
+		};
+
+		slot0_ns_partition: partition@48000 {
+			label = "image-0-nonsecure";
+			reg = <0x48000 DT_SIZE_K(224)>;
+		};
+
+		slot1_partition: partition@80000 {
+			label = "image-1";
+			reg = <0x80000 DT_SIZE_K(224)>;
+		};
+
+		slot1_ns_partition: partition@b8000 {
+			label = "image-1-nonsecure";
+			reg = <0xb8000 DT_SIZE_K(224)>;
+		};
+
+		/* 32K from 0xf0000 to 0xf7fff reserved for TF-M partitions */
+
+		storage_partition: partition@f8000 {
+			label = "storage";
+			reg = <0xf8000 DT_SIZE_K(28)>;
+		};
+
+		/* 2K from 0xff000 to 0xff7ff unused */
+	};
+};
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.yaml b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.yaml
new file mode 100644
index 00000000000..0a53875b749
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp.yaml
@@ -0,0 +1,24 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl54l15_dvk/nrf54l10/cpuapp
+name: BL54L15-DVK-nRF54L10-Application
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - zephyr
+sysbuild: true
+ram: 192
+flash: 230
+supported:
+  - adc
+  - counter
+  - gpio
+  - i2c
+  - pwm
+  - retained_mem
+  - spi
+  - watchdog
+  - i2s
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_defconfig b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_defconfig
new file mode 100644
index 00000000000..c460d11847e
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_defconfig
@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.dts
new file mode 100644
index 00000000000..02d900390cc
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.dts
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#define USE_NON_SECURE_ADDRESS_MAP 1
+
+#include <nordic/nrf54l10_cpuapp.dtsi>
+#include "nrf54l_10_15_cpuapp_common.dtsi"
+
+/ {
+	compatible = "ezurio,bl54l15_dvk_nrf54l10-cpuapp";
+	model = "Ezurio BL54L15 DVK nRF54L10 Application MCU";
+
+	chosen {
+		zephyr,code-partition = &slot0_ns_partition;
+		zephyr,sram = &sram0_ns;
+		zephyr,entropy = &psa_rng;
+	};
+
+	/delete-node/ rng;
+
+	psa_rng: psa-rng {
+		status = "okay";
+	};
+};
+
+/ {
+	/*
+	 * Default SRAM planning when building for nRF54L10 with ARM TrustZone-M support.
+	 * - Lowest 96 kB SRAM allocated to Secure image (sram0_s).
+	 * - Upper 96 kB SRAM allocated to Non-Secure image (sram0_ns).
+	 *
+	 * nRF54L10 has 192 kB of volatile memory (SRAM) but the last 42kB are reserved for
+	 * the FLPR MCU.
+	 * This static layout needs to be the same with the upstream TF-M layout in the
+	 * header flash_layout.h of the relevant platform. Any updates in the layout
+	 * needs to happen both in the flash_layout.h and in this file at the same time.
+	 */
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		sram0_s: image_s@20000000 {
+			/* Secure image memory */
+			reg = <0x20000000 DT_SIZE_K(72)>;
+		};
+
+		sram0_ns: image_ns@20012000 {
+			/* Non-Secure image memory */
+			reg = <0x20012000 DT_SIZE_K(72)>;
+		};
+	};
+};
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		/* nRF54L10 has 1022 kB of non volatile memory (RRAM) but the
+		 * last 62kB are reserved for the FLPR MCU.
+		 *
+		 * This static layout needs to be the same with the upstream TF-M layout in the
+		 * header flash_layout.h of the relevant platform. Any updates in the layout
+		 * needs to happen both in the flash_layout.h and in this file at the same time.
+		 */
+		slot0_partition: partition@0 {
+			label = "image-0";
+			reg = <0x0000000 DT_SIZE_K(384)>;
+		};
+
+		tfm_ps_partition: partition@60000 {
+			label = "tfm-ps";
+			reg = <0x00060000 DT_SIZE_K(16)>;
+		};
+
+		tfm_its_partition: partition@64000 {
+			label = "tfm-its";
+			reg = <0x00064000 DT_SIZE_K(16)>;
+		};
+
+		tfm_otp_partition: partition@68000 {
+			label = "tfm-otp";
+			reg = <0x00068000 DT_SIZE_K(8)>;
+		};
+
+		slot0_ns_partition: partition@6A000 {
+			label = "image-0-nonsecure";
+			reg = <0x0006A000 DT_SIZE_K(504)>;
+		};
+
+		storage_partition: partition@E8000 {
+			label = "storage";
+			reg = <0x000E8000 DT_SIZE_K(32)>;
+		};
+	};
+};
+
+&uart30 {
+	/* Disable so that TF-M can use this UART */
+	status = "disabled";
+};
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.yaml b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.yaml
new file mode 100644
index 00000000000..d2ad19f03c4
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl54l15_dvk/nrf54l10/cpuapp/ns
+name: BL54L15-DVK-nRF54l10-Application-Non-Secure
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - zephyr
+sysbuild: true
+ram: 192
+flash: 1022
+supported:
+  - adc
+  - gpio
+  - i2c
+  - spi
+  - counter
+  - watchdog
+  - adc
+  - i2s
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns_defconfig b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns_defconfig
new file mode 100644
index 00000000000..dea04c45f20
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l10_cpuapp_ns_defconfig
@@ -0,0 +1,37 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
+CONFIG_ARM_TRUSTZONE_M=y
+
+# This Board implies building Non-Secure firmware
+CONFIG_TRUSTED_EXECUTION_NONSECURE=y
+
+# Don't enable the cache in the non-secure image as it is a
+# secure-only peripheral on 54l
+CONFIG_CACHE_MANAGEMENT=n
+CONFIG_EXTERNAL_CACHE=n
+
+CONFIG_UART_CONSOLE=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_GPIO=y
+
+# Start SYSCOUNTER on driver init
+CONFIG_NRF_GRTC_START_SYSCOUNTER=y
+
+# Disable TFM BL2 since it is not supported
+CONFIG_TFM_BL2=n
+
+# Support for silence logging is not supported at the moment
+# Tracked by: NCSDK-31930
+CONFIG_TFM_LOG_LEVEL_SILENCE=n
+
+# The oscillators are configured as secure and cannot be configured
+# from the non secure application directly. This needs to be set
+# otherwise nrfx will try to configure them, resulting in a bus
+# fault.
+CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG=y
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp.dts
new file mode 100644
index 00000000000..ef92bda9930
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp.dts
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nordic/nrf54l15_cpuapp.dtsi>
+#include "nrf54l_10_15_cpuapp_common.dtsi"
+
+/ {
+	compatible = "ezurio,bl54l15_dvk_nrf54l15-cpuapp";
+	model = "Ezurio BL54L15_DVK nRF54L15 Application MCU";
+
+	chosen {
+		zephyr,code-partition = &slot0_partition;
+		zephyr,sram = &cpuapp_sram;
+	};
+};
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		slot0_partition: partition@10000 {
+			label = "image-0";
+			reg = <0x10000 DT_SIZE_K(324)>;
+		};
+
+		slot0_ns_partition: partition@61000 {
+			label = "image-0-nonsecure";
+			reg = <0x61000 DT_SIZE_K(324)>;
+		};
+
+		slot1_partition: partition@b2000 {
+			label = "image-1";
+			reg = <0xb2000 DT_SIZE_K(324)>;
+		};
+
+		slot1_ns_partition: partition@103000 {
+			label = "image-1-nonsecure";
+			reg = <0x103000 DT_SIZE_K(324)>;
+		};
+
+		/* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */
+		storage_partition: partition@15c000 {
+			label = "storage";
+			reg = <0x15c000 DT_SIZE_K(36)>;
+		};
+	};
+};
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp.yaml b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp.yaml
new file mode 100644
index 00000000000..abcf0f54482
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl54l15_dvk/nrf54l15/cpuapp
+name: BL54L15-DVK-nRF54l15-Application
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - zephyr
+sysbuild: true
+ram: 188
+flash: 324
+supported:
+  - adc
+  - counter
+  - dmic
+  - gpio
+  - i2c
+  - pwm
+  - retained_mem
+  - spi
+  - watchdog
+  - i2s
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_defconfig b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_defconfig
new file mode 100644
index 00000000000..c460d11847e
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_defconfig
@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.dts
new file mode 100644
index 00000000000..38712ba7074
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.dts
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#define USE_NON_SECURE_ADDRESS_MAP 1
+
+#include <nordic/nrf54l15_cpuapp.dtsi>
+#include "nrf54l_10_15_cpuapp_common.dtsi"
+
+/ {
+	compatible = "ezurio,bl54l15_dvk_nrf54l15-cpuapp";
+	model = "Ezurio BL54L15 DVK nRF54L15 Application MCU";
+
+	chosen {
+		zephyr,code-partition = &slot0_ns_partition;
+		zephyr,sram = &sram0_ns;
+		zephyr,entropy = &psa_rng;
+	};
+
+	/delete-node/ rng;
+
+	psa_rng: psa-rng {
+		status = "okay";
+	};
+};
+
+/ {
+	/*
+	 * Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support
+	 * - Lowest 80 kB SRAM allocated to Secure image (sram0_s).
+	 * - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns).
+	 *
+	 * nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for
+	 * the FLPR MCU.
+	 * This static layout needs to be the same with the upstream TF-M layout in the
+	 * header flash_layout.h of the relevant platform. Any updates in the layout
+	 * needs to happen both in the flash_layout.h and in this file at the same time.
+	 */
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		sram0_s: image_s@20000000 {
+			/* Secure image memory */
+			reg = <0x20000000 DT_SIZE_K(80)>;
+		};
+
+		sram0_ns: image_ns@20014000 {
+			/* Non-Secure image memory */
+			reg = <0x20014000 DT_SIZE_K(80)>;
+		};
+	};
+};
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* nRF54L15 has 1524 kB of non volatile memory (RRAM) but the
+		 * last 96kB are reserved for the FLPR MCU.
+		 *
+		 * This static layout needs to be the same with the upstream TF-M layout in the
+		 * header flash_layout.h of the relevant platform. Any updates in the layout
+		 * needs to happen both in the flash_layout.h and in this file at the same time.
+		 */
+		slot0_partition: partition@0 {
+			label = "image-0";
+			reg = <0x0000000 DT_SIZE_K(512)>;
+		};
+
+		tfm_ps_partition: partition@80000 {
+			label = "tfm-ps";
+			reg = <0x00080000 DT_SIZE_K(16)>;
+		};
+
+		tfm_its_partition: partition@84000 {
+			label = "tfm-its";
+			reg = <0x00084000 DT_SIZE_K(16)>;
+		};
+
+		tfm_otp_partition: partition@88000 {
+			label = "tfm-otp";
+			reg = <0x00088000 DT_SIZE_K(8)>;
+		};
+
+		slot0_ns_partition: partition@8A000 {
+			label = "image-0-nonsecure";
+			reg = <0x0008A000 DT_SIZE_K(844)>;
+		};
+
+		storage_partition: partition@15D000 {
+			label = "storage";
+			reg = <0x00015D000 DT_SIZE_K(32)>;
+		};
+	};
+};
+
+&uart30 {
+	/* Disable so that TF-M can use this UART */
+	status = "disabled";
+
+	current-speed = <115200>;
+	pinctrl-0 = <&uart30_default>;
+	pinctrl-1 = <&uart30_sleep>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.yaml b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.yaml
new file mode 100644
index 00000000000..83ef14a15a3
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl54l15_dvk/nrf54l15/cpuapp/ns
+name: BL54L15-DVK-nRF54l15-Application-Non-Secure
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - zephyr
+sysbuild: true
+ram: 256
+flash: 1524
+supported:
+  - adc
+  - gpio
+  - i2c
+  - spi
+  - counter
+  - watchdog
+  - adc
+  - i2s
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns_defconfig b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns_defconfig
new file mode 100644
index 00000000000..dea04c45f20
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuapp_ns_defconfig
@@ -0,0 +1,37 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
+CONFIG_ARM_TRUSTZONE_M=y
+
+# This Board implies building Non-Secure firmware
+CONFIG_TRUSTED_EXECUTION_NONSECURE=y
+
+# Don't enable the cache in the non-secure image as it is a
+# secure-only peripheral on 54l
+CONFIG_CACHE_MANAGEMENT=n
+CONFIG_EXTERNAL_CACHE=n
+
+CONFIG_UART_CONSOLE=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_GPIO=y
+
+# Start SYSCOUNTER on driver init
+CONFIG_NRF_GRTC_START_SYSCOUNTER=y
+
+# Disable TFM BL2 since it is not supported
+CONFIG_TFM_BL2=n
+
+# Support for silence logging is not supported at the moment
+# Tracked by: NCSDK-31930
+CONFIG_TFM_LOG_LEVEL_SILENCE=n
+
+# The oscillators are configured as secure and cannot be configured
+# from the non secure application directly. This needs to be set
+# otherwise nrfx will try to configure them, resulting in a bus
+# fault.
+CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG=y
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr.dts
new file mode 100644
index 00000000000..0e00b2d1e5e
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr.dts
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf54l15_cpuflpr.dtsi>
+#include "bl54l15_dvk_common.dtsi"
+
+/ {
+	model = "Ezurio BL54L15 DVK nRF54L15 FLPR MCU";
+	compatible = "ezurio,bl54l15_dvk_nrf54l15-cpuflpr";
+
+	chosen {
+		zephyr,console = &uart30;
+		zephyr,shell-uart = &uart30;
+		zephyr,code-partition = &cpuflpr_code_partition;
+		zephyr,flash = &cpuflpr_rram;
+		zephyr,sram = &cpuflpr_sram;
+	};
+};
+
+&cpuflpr_sram {
+	status = "okay";
+	/* size must be increased due to booting from SRAM */
+	reg = <0x20028000 DT_SIZE_K(96)>;
+	ranges = <0x0 0x20028000 0x18000>;
+};
+
+&cpuflpr_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cpuflpr_code_partition: partition@0 {
+			label = "image-0";
+			reg = <0x0 DT_SIZE_K(96)>;
+		};
+	};
+};
+
+&grtc {
+	owned-channels = <3 4>;
+	status = "okay";
+};
+
+&uart30 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr.yaml b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr.yaml
new file mode 100644
index 00000000000..a324778c0e4
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl54l15_dvk/nrf54l15/cpuflpr
+name: BL54L15-DVK-nRF54L15-Fast-Lightweight-Peripheral-Processor
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+sysbuild: true
+ram: 96
+flash: 96
+supported:
+  - counter
+  - gpio
+  - i2c
+  - spi
+  - watchdog
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_defconfig b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_defconfig
new file mode 100644
index 00000000000..9695bd3f5df
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_defconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+CONFIG_USE_DT_CODE_PARTITION=y
+
+# Execute from SRAM
+CONFIG_XIP=n
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip.dts b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip.dts
new file mode 100644
index 00000000000..f1bbe27b447
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip.dts
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15_dvk_nrf54l15_cpuflpr.dts"
+
+&cpuflpr_sram {
+	reg = <0x2002f000 DT_SIZE_K(68)>;
+	ranges = <0x0 0x2002f000 0x11000>;
+};
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip.yaml b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip.yaml
new file mode 100644
index 00000000000..0c473591f9c
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl54l15_dvk/nrf54l15/cpuflpr/xip
+name: BL54L15-DVK-nRF54L15-Fast-Lightweight-Peripheral-Processor (RRAM XIP)
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+sysbuild: true
+ram: 68
+flash: 96
+supported:
+  - counter
+  - gpio
+  - i2c
+  - spi
+  - watchdog
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip_defconfig b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip_defconfig
new file mode 100644
index 00000000000..b433045216a
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l15_cpuflpr_xip_defconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Execute from RRAM
+CONFIG_XIP=y
diff --git a/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l_10_15-pinctrl.dtsi b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l_10_15-pinctrl.dtsi
new file mode 100644
index 00000000000..1377b613e2f
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/bl54l15_dvk_nrf54l_10_15-pinctrl.dtsi
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ * Copyright (c) 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	/omit-if-no-ref/ uart20_default: uart20_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 4)>,
+				<NRF_PSEL(UART_RTS, 1, 6)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 1, 5)>,
+				<NRF_PSEL(UART_CTS, 1, 7)>;
+			bias-pull-up;
+		};
+	};
+
+	/omit-if-no-ref/ uart20_sleep: uart20_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 4)>,
+				<NRF_PSEL(UART_RX, 1, 5)>,
+				<NRF_PSEL(UART_RTS, 1, 6)>,
+				<NRF_PSEL(UART_CTS, 1, 7)>;
+			low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ uart30_default: uart30_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 0)>,
+				<NRF_PSEL(UART_RTS, 0, 2)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 0, 1)>,
+				<NRF_PSEL(UART_CTS, 0, 3)>;
+			bias-pull-up;
+		};
+	};
+
+	/omit-if-no-ref/ uart30_sleep: uart30_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 0)>,
+				<NRF_PSEL(UART_RX, 0, 1)>,
+				<NRF_PSEL(UART_RTS, 0, 2)>,
+				<NRF_PSEL(UART_CTS, 0, 3)>;
+			low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ spi00_default: spi00_default {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 1)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 2)>,
+				<NRF_PSEL(SPIM_MISO, 2, 4)>;
+		};
+	};
+
+	/omit-if-no-ref/ spi00_sleep: spi00_sleep {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 1)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 2)>,
+				<NRF_PSEL(SPIM_MISO, 2, 4)>;
+				low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ pwm20_default: pwm20_default {
+		group1 {
+			psels = <NRF_PSEL(PWM_OUT0, 1, 10)>;
+		};
+	};
+
+	/omit-if-no-ref/ pwm20_sleep: pwm20_sleep {
+		group1 {
+			psels = <NRF_PSEL(PWM_OUT0, 1, 10)>;
+			low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ grtc_default: grtc_default {
+		group1 {
+			psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 8)>,
+				<NRF_PSEL(GRTC_CLKOUT_32K, 0, 4)>;
+		};
+	};
+
+	/omit-if-no-ref/ grtc_sleep: grtc_sleep {
+		group1 {
+			psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 8)>,
+				<NRF_PSEL(GRTC_CLKOUT_32K, 0, 4)>;
+			low-power-enable;
+		};
+	};
+};
diff --git a/boards/ezurio/bl54l15_dvk/board.cmake b/boards/ezurio/bl54l15_dvk/board.cmake
new file mode 100644
index 00000000000..53b6961dee0
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/board.cmake
@@ -0,0 +1,23 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_NRF54L10_CPUAPP OR CONFIG_SOC_NRF54L15_CPUAPP)
+  board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000")
+elseif(CONFIG_SOC_NRF54L15_CPUFLPR)
+  board_runner_args(jlink "--device=nRF54L15_RV32")
+elseif(CONFIG_SOC_NRF54L10_CPUFLPR)
+  set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54l_10_15_cpuflpr.JLinkScript)
+  board_runner_args(jlink "--device=RISC-V" "--speed=4000" "-if SW" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}")
+endif()
+
+if(CONFIG_BOARD_BL54L15_DVK_NRF54L10_CPUAPP_NS OR CONFIG_BOARD_BL54L15_DVK_NRF54L15_CPUAPP_NS)
+  set(TFM_PUBLIC_KEY_FORMAT "full")
+endif()
+
+if(CONFIG_TFM_FLASH_MERGED_BINARY)
+  set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex)
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/ezurio/bl54l15_dvk/board.yml b/boards/ezurio/bl54l15_dvk/board.yml
new file mode 100644
index 00000000000..841dec0f4ae
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/board.yml
@@ -0,0 +1,52 @@
+board:
+  name: bl54l15_dvk
+  full_name: BL54L15 DVK
+  vendor: ezurio
+  socs:
+    - name: nrf54l10
+      variants:
+        - name: ns
+          cpucluster: cpuapp
+    - name: nrf54l15
+      variants:
+        - name: xip
+          cpucluster: cpuflpr
+        - name: ns
+          cpucluster: cpuapp
+runners:
+  run_once:
+    '--recover':
+      - runners:
+          - nrfjprog
+          - nrfutil
+        run: first
+        groups:
+          - boards:
+              - bl54l15_dvk/nrf54l15/cpuapp
+              - bl54l15_dvk/nrf54l15/cpuapp/ns
+              - bl54l15_dvk/nrf54l15/cpuflpr
+              - bl54l15_dvk/nrf54l15/cpuflpr/xip
+    '--erase':
+      - runners:
+          - nrfjprog
+          - jlink
+          - nrfutil
+        run: first
+        groups:
+          - boards:
+              - bl54l15_dvk/nrf54l15/cpuapp
+              - bl54l15_dvk/nrf54l15/cpuapp/ns
+              - bl54l15_dvk/nrf54l15/cpuflpr
+              - bl54l15_dvk/nrf54l15/cpuflpr/xip
+    '--reset':
+      - runners:
+          - nrfjprog
+          - jlink
+          - nrfutil
+        run: last
+        groups:
+          - boards:
+              - bl54l15_dvk/nrf54l15/cpuapp
+              - bl54l15_dvk/nrf54l15/cpuapp/ns
+              - bl54l15_dvk/nrf54l15/cpuflpr
+              - bl54l15_dvk/nrf54l15/cpuflpr/xip
diff --git a/boards/ezurio/bl54l15_dvk/doc/bl54l15_dvk.rst b/boards/ezurio/bl54l15_dvk/doc/bl54l15_dvk.rst
new file mode 100644
index 00000000000..f5f7c798b01
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/doc/bl54l15_dvk.rst
@@ -0,0 +1,142 @@
+.. zephyr:board:: bl54l15_dvk
+
+Overview
+********
+
+.. note::
+   You can find more information about the BL54L15 module on the `BL54L15 website`_.
+
+   You can find more information about the BL54L10 module on the `BL54L10 website`_.
+
+   You can find more information about the underlying nRF54L15 SoC on the
+   `nRF54L15 website`_. For the nRF54L15 technical documentation and other
+   resources (such as SoC Datasheet), see the `nRF54L15 documentation`_ page.
+
+The BL54L15 Development Kit provides support for the Ezurio BL54L15 and BL54L10
+range of modules.
+
+The modules are based on the Nordic Semiconductor nRF54L15 and nRF54L10 Arm Cortex-M33 CPUs.
+
+The BL54L15 module incorporates the QFN package nRF54L15 (1524kB Flash, 256kB RAM). The BL54L10
+module the QFN package nRF54L10 (1022kB Flash, 192kB RAM). Both parts feature up to 31 configurable
+GPIOs and BLE Radio TX Power up to 7dBm.
+
+The modules include the following devices:
+
+* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)`
+* CLOCK
+* RRAM
+* :abbr:`GPIO (General Purpose Input Output)`
+* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)`
+* MEMCONF
+* :abbr:`MPU (Memory Protection Unit)`
+* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
+* :abbr:`PWM (Pulse Width Modulation)`
+* :abbr:`GRTC (Global real-time counter)`
+* Segger RTT (RTT Console)
+* :abbr:`SPI (Serial Peripheral Interface)`
+* :abbr:`UARTE (Universal asynchronous receiver-transmitter)`
+* :abbr:`WDT (Watchdog Timer)`
+
+Hardware
+********
+
+The BL54L15 DVK has two crystal oscillators:
+
+* High-frequency 32 MHz crystal oscillator (HFXO)
+* Low-frequency 32.768 kHz crystal oscillator (LFXO)
+
+The crystal oscillators can be configured to use either
+internal or external capacitors.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+Applications for the ``bl54l15_dvk/nrf54l15/cpuapp`` and ``bl54l15_dvk/nrf54l10/cpuapp``
+board targets can be built, flashed, and debugged in the usual way.
+See :ref:`build_an_application` and :ref:`application_run` for more
+details on building and running.
+
+Applications for the ``bl54l15_dvk/nrf54l15/cpuflpr`` board target need to be built
+using sysbuild to include the ``vpr_launcher`` image for the application core.
+
+Enter the following command to compile ``hello_world`` for the FLPR core:
+
+.. code-block:: console
+
+   west build -p -b bl54l15_dvk/nrf54l15/cpuflpr --sysbuild
+
+Flashing
+========
+
+As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world`
+application.
+
+.. warning::
+
+   When programming the device, you might get an error similar to the following message::
+
+    ERROR: The operation attempted is unavailable due to readback protection in
+    ERROR: your device. Please use --recover to unlock the device.
+
+   This error occurs when readback protection is enabled.
+   To disable the readback protection, you must *recover* your device.
+
+   Enter the following command to recover the core::
+
+    west flash --recover
+
+   The ``--recover`` command erases the flash memory and then writes a small binary into
+   the recovered flash memory.
+   This binary prevents the readback protection from enabling itself again after a pin
+   reset or power cycle.
+
+Follow the instructions in the :ref:`nordic_segger` page to install
+and configure all the necessary software. Further information can be
+found in :ref:`nordic_segger_flashing`.
+
+To build and program the sample to the BL54L15 DVK, complete the following steps:
+
+First, connect the BL54L15 DVK to your computer using the IMCU USB port on the DVK.
+Next, build the sample by running the following command:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: bl54l15_dvk/nrf54l15/cpuapp
+   :goals: build flash
+
+Testing the LEDs and buttons on the BL54L15 DVK
+************************************************
+
+Test the BL54L15 DVK with a :zephyr:code-sample:`blinky` sample.
+
+.. _BL54L15 website: https://www.ezurio.com/product/bl54l15-series-bluetooth-le-80215-4-nfc
+.. _BL54L10 website: https://www.ezurio.com/wireless-modules/bluetooth-modules/bl54-series/bl54l10-series-bluetooth-le-802-15-4-nfc
+.. _nRF54L15 website: https://www.nordicsemi.com/Products/nRF54L15
+.. _nRF54L15 documentation: https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/device_guides/nrf54l/index.html
+
+.. _bl54l15_dvk_nrf54l10:
+
+BL54L10 emulation on BL54L15 DVK
+********************************
+
+Overview
+========
+
+The ``bl54l15_dvk/nrf54l10`` board is a modified version of the BL54L15 DVK
+that enforces the limitations imposed by the nRF54L10 IC, upon which the BL54L10 is based.
+The nRF54L10 is a cost-reduced variant of the original nRF54L15. Since Ezurio does not offer a
+development kit for the BL54L10 you can use this board to develop for this
+module while using the BL54L15 Development Kit (453-00001-K1, 453-00044-K1).
+
+See above for more information about the development board. Refer to
+the `BL54L10 website`_ for details of the BL54L10 module and the `nRF54L10 website`_ for
+the official reference on the underlying SoC.
+
+.. _BL54L10 website: https://www.ezurio.com/wireless-modules/bluetooth-modules/bl54-series/bl54l10-series-bluetooth-le-802-15-4-nfc
+.. _nRF54L10 website: https://www.nordicsemi.com/Products/nRF54L10
diff --git a/boards/ezurio/bl54l15_dvk/doc/img/bl54l15_dvk.webp b/boards/ezurio/bl54l15_dvk/doc/img/bl54l15_dvk.webp
new file mode 100644
index 00000000000..9bdc924af83
Binary files /dev/null and b/boards/ezurio/bl54l15_dvk/doc/img/bl54l15_dvk.webp differ
diff --git a/boards/ezurio/bl54l15_dvk/nrf54l_10_15_cpuapp_common.dtsi b/boards/ezurio/bl54l15_dvk/nrf54l_10_15_cpuapp_common.dtsi
new file mode 100644
index 00000000000..8671beb29cf
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/nrf54l_10_15_cpuapp_common.dtsi
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* This file is common to the secure and non-secure domain */
+
+#include "bl54l15_dvk_common.dtsi"
+
+/ {
+	chosen {
+		zephyr,console = &uart20;
+		zephyr,shell-uart = &uart20;
+		zephyr,uart-mcumgr = &uart20;
+		zephyr,bt-mon-uart = &uart20;
+		zephyr,bt-c2h-uart = &uart20;
+		zephyr,flash-controller = &rram_controller;
+		zephyr,flash = &cpuapp_rram;
+		zephyr,ieee802154 = &ieee802154;
+	};
+};
+
+&cpuapp_sram {
+	status = "okay";
+};
+
+&lfxo {
+	load-capacitors = "internal";
+	load-capacitance-femtofarad = <15500>;
+};
+
+&hfxo {
+	load-capacitors = "internal";
+	load-capacitance-femtofarad = <15000>;
+};
+
+&regulators {
+	status = "okay";
+};
+
+&vregmain {
+	status = "okay";
+	regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
+};
+
+&grtc {
+	owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
+	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
+	child-owned-channels = <3 4 7 8 9 10 11>;
+	status = "okay";
+};
+
+&uart20 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};
+
+&radio {
+	status = "okay";
+};
+
+&ieee802154 {
+	status = "okay";
+};
+
+&temp {
+	status = "okay";
+};
+
+&clock {
+	status = "okay";
+};
+
+&spi00 {
+	status = "okay";
+	cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spi00_default>;
+	pinctrl-1 = <&spi00_sleep>;
+	pinctrl-names = "default", "sleep";
+
+	mx25r64: mx25r6435f@0 {
+		compatible = "jedec,spi-nor";
+		status = "okay";
+		reg = <0>;
+		spi-max-frequency = <8000000>;
+		jedec-id = [c2 28 17];
+		sfdp-bfp = [
+			e5 20 f1 ff  ff ff ff 03  44 eb 08 6b  08 3b 04 bb
+			ee ff ff ff  ff ff 00 ff  ff ff 00 ff  0c 20 0f 52
+			10 d8 00 ff  23 72 f5 00  82 ed 04 cc  44 83 48 44
+			30 b0 30 b0  f7 c4 d5 5c  00 be 29 ff  f0 d0 ff ff
+		];
+		size = <67108864>;
+		has-dpd;
+		t-enter-dpd = <10000>;
+		t-exit-dpd = <35000>;
+	};
+};
+
+&adc {
+	status = "okay";
+};
diff --git a/boards/ezurio/bl54l15_dvk/support/nrf54l_10_15_cpuflpr.JLinkScript b/boards/ezurio/bl54l15_dvk/support/nrf54l_10_15_cpuflpr.JLinkScript
new file mode 100644
index 00000000000..1cf94ee52a4
--- /dev/null
+++ b/boards/ezurio/bl54l15_dvk/support/nrf54l_10_15_cpuflpr.JLinkScript
@@ -0,0 +1,5 @@
+int InitTarget(void) {
+  // Base address where DMI registers can be found in the APB address space
+  JLINK_ExecCommand("CORESIGHT_SetCoreBaseAddr = 0x5004C400");
+  return 0;
+}
diff --git a/boards/ezurio/bl54l15u_dvk/Kconfig b/boards/ezurio/bl54l15u_dvk/Kconfig
new file mode 100644
index 00000000000..b1623fe1b82
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/Kconfig
@@ -0,0 +1,31 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# BL54L15U DVK board configuration
+
+if BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS
+
+DT_NRF_MPC := $(dt_nodelabel_path,nrf_mpc)
+
+config NRF_TRUSTZONE_FLASH_REGION_SIZE
+	hex
+	default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity)
+	help
+	  This defines the flash region size from the TrustZone perspective.
+	  It is used when configuring the TrustZone and when setting alignments
+	  requirements for the partitions.
+	  This abstraction allows us to configure TrustZone without depending
+	  on peripheral-specific symbols.
+
+config NRF_TRUSTZONE_RAM_REGION_SIZE
+	hex
+	default $(dt_node_int_prop_hex,$(DT_NRF_MPC),override-granularity)
+	help
+	  This defines the RAM region size from the TrustZone perspective.
+	  It is used when configuring the TrustZone and when setting alignments
+	  requirements for the partitions.
+	  This abstraction allows us to configure TrustZone without depending
+	  on peripheral specific symbols.
+
+endif # BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS
diff --git a/boards/ezurio/bl54l15u_dvk/Kconfig.bl54l15u_dvk b/boards/ezurio/bl54l15u_dvk/Kconfig.bl54l15u_dvk
new file mode 100644
index 00000000000..f807b23268e
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/Kconfig.bl54l15u_dvk
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_BL54L15U_DVK
+	select SOC_NRF54L15_CPUAPP if BOARD_BL54L15U_DVK_NRF54L15_CPUAPP || BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS
+	select SOC_NRF54L15_CPUFLPR if BOARD_BL54L15U_DVK_NRF54L15_CPUFLPR || \
+					    BOARD_BL54L15U_DVK_NRF54L15_CPUFLPR_XIP
diff --git a/boards/ezurio/bl54l15u_dvk/Kconfig.defconfig b/boards/ezurio/bl54l15u_dvk/Kconfig.defconfig
new file mode 100644
index 00000000000..4ee4dc3e6d2
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/Kconfig.defconfig
@@ -0,0 +1,32 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
+DT_CHOSEN_Z_SRAM_PARTITION := zephyr,sram-secure-partition
+
+if BOARD_BL54L15U_DVK_NRF54L15_CPUAPP
+
+config ROM_START_OFFSET
+	default 0x800 if BOOTLOADER_MCUBOOT
+
+endif # BOARD_BL54L15U_DVK_NRF54L15_CPUAPP
+
+if BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS
+
+config BT_CTLR
+	default BT
+
+config FLASH_LOAD_OFFSET
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+config FLASH_LOAD_SIZE
+	default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_Z_CODE_PARTITION))
+
+# By default, if we build for a Non-Secure version of the board,
+# enable building with TF-M as the Secure Execution Environment.
+config BUILD_WITH_TFM
+	default y
+
+endif # BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS
diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_common.dtsi b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_common.dtsi
new file mode 100644
index 00000000000..72206859685
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_common.dtsi
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15u_dvk_nrf54l15-pinctrl.dtsi"
+
+/ {
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led_0 {
+			gpios = <&gpio2 9 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 0";
+		};
+
+		led1: led_1 {
+			gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 1";
+		};
+
+		led2: led_2 {
+			gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 2";
+		};
+
+		led3: led_3 {
+			gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 3";
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		/*
+		 * PWM signal can be exposed on GPIO pin only within same domain.
+		 * There is only one domain which contains both PWM and GPIO:
+		 * PWM20/21/22 and GPIO Port P1.
+		 * Only LEDs connected to P1 can work with PWM, for example LED1.
+		 */
+		pwm_led1: pwm_led_1 {
+			pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		button0: button_0 {
+			gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 0";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		button1: button_1 {
+			gpios = <&gpio1 9 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 1";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+
+		button2: button_2 {
+			gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 2";
+			zephyr,code = <INPUT_KEY_2>;
+		};
+
+		button3: button_3 {
+			gpios = <&gpio0 4 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 3";
+			zephyr,code = <INPUT_KEY_3>;
+		};
+	};
+
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		led2 = &led2;
+		led3 = &led3;
+		pwm-led0 = &pwm_led1;
+		sw0 = &button0;
+		sw1 = &button1;
+		sw2 = &button2;
+		sw3 = &button3;
+		watchdog0 = &wdt31;
+	};
+};
+
+&uart20 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart20_default>;
+	pinctrl-1 = <&uart20_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&uart30 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart30_default>;
+	pinctrl-1 = <&uart30_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&pwm20 {
+	status = "okay";
+	pinctrl-0 = <&pwm20_default>;
+	pinctrl-1 = <&pwm20_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+/* Get a node label for wi-fi spi to use in shield files */
+wifi_spi: &spi22 {};
diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15-pinctrl.dtsi b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15-pinctrl.dtsi
new file mode 100644
index 00000000000..1377b613e2f
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15-pinctrl.dtsi
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ * Copyright (c) 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	/omit-if-no-ref/ uart20_default: uart20_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 4)>,
+				<NRF_PSEL(UART_RTS, 1, 6)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 1, 5)>,
+				<NRF_PSEL(UART_CTS, 1, 7)>;
+			bias-pull-up;
+		};
+	};
+
+	/omit-if-no-ref/ uart20_sleep: uart20_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 4)>,
+				<NRF_PSEL(UART_RX, 1, 5)>,
+				<NRF_PSEL(UART_RTS, 1, 6)>,
+				<NRF_PSEL(UART_CTS, 1, 7)>;
+			low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ uart30_default: uart30_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 0)>,
+				<NRF_PSEL(UART_RTS, 0, 2)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 0, 1)>,
+				<NRF_PSEL(UART_CTS, 0, 3)>;
+			bias-pull-up;
+		};
+	};
+
+	/omit-if-no-ref/ uart30_sleep: uart30_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 0)>,
+				<NRF_PSEL(UART_RX, 0, 1)>,
+				<NRF_PSEL(UART_RTS, 0, 2)>,
+				<NRF_PSEL(UART_CTS, 0, 3)>;
+			low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ spi00_default: spi00_default {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 1)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 2)>,
+				<NRF_PSEL(SPIM_MISO, 2, 4)>;
+		};
+	};
+
+	/omit-if-no-ref/ spi00_sleep: spi00_sleep {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 1)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 2)>,
+				<NRF_PSEL(SPIM_MISO, 2, 4)>;
+				low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ pwm20_default: pwm20_default {
+		group1 {
+			psels = <NRF_PSEL(PWM_OUT0, 1, 10)>;
+		};
+	};
+
+	/omit-if-no-ref/ pwm20_sleep: pwm20_sleep {
+		group1 {
+			psels = <NRF_PSEL(PWM_OUT0, 1, 10)>;
+			low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ grtc_default: grtc_default {
+		group1 {
+			psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 8)>,
+				<NRF_PSEL(GRTC_CLKOUT_32K, 0, 4)>;
+		};
+	};
+
+	/omit-if-no-ref/ grtc_sleep: grtc_sleep {
+		group1 {
+			psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 8)>,
+				<NRF_PSEL(GRTC_CLKOUT_32K, 0, 4)>;
+			low-power-enable;
+		};
+	};
+};
diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp.dts b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp.dts
new file mode 100644
index 00000000000..7ea5099aa3f
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp.dts
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nordic/nrf54l15_cpuapp.dtsi>
+#include "nrf54l15_cpuapp_common.dtsi"
+
+/ {
+	compatible = "ezurio,bl54l15u_dvk_nrf54l15-cpuapp";
+	model = "Ezurio BL54L15u_DVK nRF54L15 Application MCU";
+
+	chosen {
+		zephyr,code-partition = &slot0_partition;
+		zephyr,sram = &cpuapp_sram;
+	};
+};
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		slot0_partition: partition@10000 {
+			label = "image-0";
+			reg = <0x10000 DT_SIZE_K(324)>;
+		};
+
+		slot0_ns_partition: partition@61000 {
+			label = "image-0-nonsecure";
+			reg = <0x61000 DT_SIZE_K(324)>;
+		};
+
+		slot1_partition: partition@b2000 {
+			label = "image-1";
+			reg = <0xb2000 DT_SIZE_K(324)>;
+		};
+
+		slot1_ns_partition: partition@103000 {
+			label = "image-1-nonsecure";
+			reg = <0x103000 DT_SIZE_K(324)>;
+		};
+
+		/* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */
+		storage_partition: partition@15c000 {
+			label = "storage";
+			reg = <0x15c000 DT_SIZE_K(36)>;
+		};
+	};
+};
diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp.yaml b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp.yaml
new file mode 100644
index 00000000000..264368c2baf
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl54l15u_dvk/nrf54l15/cpuapp
+name: BL54L15u-DVK-nRF54l15-Application
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - zephyr
+sysbuild: true
+ram: 188
+flash: 324
+supported:
+  - adc
+  - counter
+  - dmic
+  - gpio
+  - i2c
+  - pwm
+  - retained_mem
+  - spi
+  - watchdog
+  - i2s
diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_defconfig b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_defconfig
new file mode 100644
index 00000000000..c460d11847e
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_defconfig
@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.dts b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.dts
new file mode 100644
index 00000000000..f03eb6a5e81
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.dts
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#define USE_NON_SECURE_ADDRESS_MAP 1
+
+#include <nordic/nrf54l15_cpuapp.dtsi>
+#include "nrf54l15_cpuapp_common.dtsi"
+
+/ {
+	compatible = "ezurio,bl54l15u_dvk_nrf54l15-cpuapp";
+	model = "Ezurio BL54L15u DVK nRF54L15 Application MCU";
+
+	chosen {
+		zephyr,code-partition = &slot0_ns_partition;
+		zephyr,sram = &sram0_ns;
+		zephyr,entropy = &psa_rng;
+	};
+
+	/delete-node/ rng;
+
+	psa_rng: psa-rng {
+		status = "okay";
+	};
+};
+
+/ {
+	/*
+	 * Default SRAM planning when building for nRF54L15 with ARM TrustZone-M support
+	 * - Lowest 80 kB SRAM allocated to Secure image (sram0_s).
+	 * - Upper 80 kB SRAM allocated to Non-Secure image (sram0_ns).
+	 *
+	 * nRF54L15 has 256 kB of volatile memory (SRAM) but the last 96kB are reserved for
+	 * the FLPR MCU.
+	 * This static layout needs to be the same with the upstream TF-M layout in the
+	 * header flash_layout.h of the relevant platform. Any updates in the layout
+	 * needs to happen both in the flash_layout.h and in this file at the same time.
+	 */
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		sram0_s: image_s@20000000 {
+			/* Secure image memory */
+			reg = <0x20000000 DT_SIZE_K(80)>;
+		};
+
+		sram0_ns: image_ns@20014000 {
+			/* Non-Secure image memory */
+			reg = <0x20014000 DT_SIZE_K(80)>;
+		};
+	};
+};
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* nRF54L15 has 1524 kB of non volatile memory (RRAM) but the
+		 * last 96kB are reserved for the FLPR MCU.
+		 *
+		 * This static layout needs to be the same with the upstream TF-M layout in the
+		 * header flash_layout.h of the relevant platform. Any updates in the layout
+		 * needs to happen both in the flash_layout.h and in this file at the same time.
+		 */
+		slot0_partition: partition@0 {
+			label = "image-0";
+			reg = <0x0000000 DT_SIZE_K(512)>;
+		};
+
+		tfm_ps_partition: partition@80000 {
+			label = "tfm-ps";
+			reg = <0x00080000 DT_SIZE_K(16)>;
+		};
+
+		tfm_its_partition: partition@84000 {
+			label = "tfm-its";
+			reg = <0x00084000 DT_SIZE_K(16)>;
+		};
+
+		tfm_otp_partition: partition@88000 {
+			label = "tfm-otp";
+			reg = <0x00088000 DT_SIZE_K(8)>;
+		};
+
+		slot0_ns_partition: partition@8A000 {
+			label = "image-0-nonsecure";
+			reg = <0x0008A000 DT_SIZE_K(844)>;
+		};
+
+		storage_partition: partition@15D000 {
+			label = "storage";
+			reg = <0x00015D000 DT_SIZE_K(32)>;
+		};
+	};
+};
+
+&uart30 {
+	/* Disable so that TF-M can use this UART */
+	status = "disabled";
+
+	current-speed = <115200>;
+	pinctrl-0 = <&uart30_default>;
+	pinctrl-1 = <&uart30_sleep>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.yaml b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.yaml
new file mode 100644
index 00000000000..11a3347969d
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+
+identifier: bl54l15u_dvk/nrf54l15/cpuapp/ns
+name: BL54L15u-DVK-nRF54l15-Application-Non-Secure
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - zephyr
+sysbuild: true
+ram: 256
+flash: 1524
+supported:
+  - adc
+  - gpio
+  - i2c
+  - spi
+  - counter
+  - watchdog
+  - adc
+  - i2s
diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns_defconfig b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns_defconfig
new file mode 100644
index 00000000000..24848d53b82
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuapp_ns_defconfig
@@ -0,0 +1,37 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
+CONFIG_ARM_TRUSTZONE_M=y
+
+# This Board implies building Non-Secure firmware
+CONFIG_TRUSTED_EXECUTION_NONSECURE=y
+
+# Don't enable the cache in the non-secure image as it is a
+# secure-only peripheral on 54l
+CONFIG_CACHE_MANAGEMENT=n
+CONFIG_EXTERNAL_CACHE=n
+
+CONFIG_UART_CONSOLE=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_GPIO=y
+
+# Start SYSCOUNTER on driver init
+CONFIG_NRF_GRTC_START_SYSCOUNTER=y
+
+# Disable TFM BL2 since it is not supported
+CONFIG_TFM_BL2=n
+
+# Support for silence logging is not supported at the moment
+# Tracked by: NCSDK-31930
+CONFIG_TFM_LOG_LEVEL_SILENCE=n
+
+# The oscillators are configured as secure and cannot be configured
+# from the non secure application directly. This needs to be set
+# otherwise nrfx will try to configure them, resulting in a bus
+# fault.
+CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG=y
diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr.dts b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr.dts
new file mode 100644
index 00000000000..12e280a9a90
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr.dts
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf54l15_cpuflpr.dtsi>
+#include "bl54l15u_dvk_common.dtsi"
+
+/ {
+	model = "Ezurio BL54L15u DVK nRF54L15 FLPR MCU";
+	compatible = "ezurio,bl54l15u_dvk_nrf54l15-cpuflpr";
+
+	chosen {
+		zephyr,console = &uart30;
+		zephyr,shell-uart = &uart30;
+		zephyr,code-partition = &cpuflpr_code_partition;
+		zephyr,flash = &cpuflpr_rram;
+		zephyr,sram = &cpuflpr_sram;
+	};
+};
+
+&cpuflpr_sram {
+	status = "okay";
+	/* size must be increased due to booting from SRAM */
+	reg = <0x20028000 DT_SIZE_K(96)>;
+	ranges = <0x0 0x20028000 0x18000>;
+};
+
+&cpuflpr_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cpuflpr_code_partition: partition@0 {
+			label = "image-0";
+			reg = <0x0 DT_SIZE_K(96)>;
+		};
+	};
+};
+
+&grtc {
+	owned-channels = <3 4>;
+	status = "okay";
+};
+
+&uart30 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};
diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr.yaml b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr.yaml
new file mode 100644
index 00000000000..bf3c14b52bf
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl54l15u_dvk/nrf54l15/cpuflpr
+name: BL54L15u-DVK-nRF54L15-Fast-Lightweight-Peripheral-Processor
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+sysbuild: true
+ram: 96
+flash: 96
+supported:
+  - counter
+  - gpio
+  - i2c
+  - spi
+  - watchdog
diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_defconfig b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_defconfig
new file mode 100644
index 00000000000..9695bd3f5df
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_defconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+CONFIG_USE_DT_CODE_PARTITION=y
+
+# Execute from SRAM
+CONFIG_XIP=n
diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip.dts b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip.dts
new file mode 100644
index 00000000000..2380f2cdf25
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip.dts
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15u_dvk_nrf54l15_cpuflpr.dts"
+
+&cpuflpr_sram {
+	reg = <0x2002f000 DT_SIZE_K(68)>;
+	ranges = <0x0 0x2002f000 0x11000>;
+};
diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip.yaml b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip.yaml
new file mode 100644
index 00000000000..27d584351de
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: bl54l15u_dvk/nrf54l15/cpuflpr/xip
+name: BL54L15u-DVK-nRF54L15-Fast-Lightweight-Peripheral-Processor (RRAM XIP)
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+sysbuild: true
+ram: 68
+flash: 96
+supported:
+  - counter
+  - gpio
+  - i2c
+  - spi
+  - watchdog
diff --git a/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip_defconfig b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip_defconfig
new file mode 100644
index 00000000000..b433045216a
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/bl54l15u_dvk_nrf54l15_cpuflpr_xip_defconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Execute from RRAM
+CONFIG_XIP=y
diff --git a/boards/ezurio/bl54l15u_dvk/board.cmake b/boards/ezurio/bl54l15u_dvk/board.cmake
new file mode 100644
index 00000000000..f8e306c4bcc
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/board.cmake
@@ -0,0 +1,20 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_NRF54L15_CPUAPP)
+  board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000")
+elseif(CONFIG_SOC_NRF54L15_CPUFLPR)
+  board_runner_args(jlink "--device=nRF54L15_RV32")
+endif()
+
+if(CONFIG_BOARD_BL54L15U_DVK_NRF54L15_CPUAPP_NS)
+  set(TFM_PUBLIC_KEY_FORMAT "full")
+endif()
+
+if(CONFIG_TFM_FLASH_MERGED_BINARY)
+  set_property(TARGET runners_yaml_props_target PROPERTY hex_file tfm_merged.hex)
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/ezurio/bl54l15u_dvk/board.yml b/boards/ezurio/bl54l15u_dvk/board.yml
new file mode 100644
index 00000000000..1553980eaa8
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/board.yml
@@ -0,0 +1,48 @@
+board:
+  name: bl54l15u_dvk
+  full_name: BL54L15u DVK
+  vendor: ezurio
+  socs:
+    - name: nrf54l15
+      variants:
+        - name: xip
+          cpucluster: cpuflpr
+        - name: ns
+          cpucluster: cpuapp
+runners:
+  run_once:
+    '--recover':
+      - runners:
+          - nrfjprog
+          - nrfutil
+        run: first
+        groups:
+          - boards:
+              - bl54l15u_dvk/nrf54l15/cpuapp
+              - bl54l15u_dvk/nrf54l15/cpuapp/ns
+              - bl54l15u_dvk/nrf54l15/cpuflpr
+              - bl54l15u_dvk/nrf54l15/cpuflpr/xip
+    '--erase':
+      - runners:
+          - nrfjprog
+          - jlink
+          - nrfutil
+        run: first
+        groups:
+          - boards:
+              - bl54l15u_dvk/nrf54l15/cpuapp
+              - bl54l15u_dvk/nrf54l15/cpuapp/ns
+              - bl54l15u_dvk/nrf54l15/cpuflpr
+              - bl54l15u_dvk/nrf54l15/cpuflpr/xip
+    '--reset':
+      - runners:
+          - nrfjprog
+          - jlink
+          - nrfutil
+        run: last
+        groups:
+          - boards:
+              - bl54l15u_dvk/nrf54l15/cpuapp
+              - bl54l15u_dvk/nrf54l15/cpuapp/ns
+              - bl54l15u_dvk/nrf54l15/cpuflpr
+              - bl54l15u_dvk/nrf54l15/cpuflpr/xip
diff --git a/boards/ezurio/bl54l15u_dvk/doc/bl54l15u_dvk.rst b/boards/ezurio/bl54l15u_dvk/doc/bl54l15u_dvk.rst
new file mode 100644
index 00000000000..3e3e705be8d
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/doc/bl54l15u_dvk.rst
@@ -0,0 +1,115 @@
+.. zephyr:board:: bl54l15u_dvk
+
+Overview
+********
+
+.. note::
+   You can find more information about the BL54L15u module on the `BL54L15u website`_.
+
+   You can find more information about the underlying nRF54L15 SoC on the
+   `nRF54L15 website`_. For the nRF54L15 technical documentation and other
+   resources (such as SoC Datasheet), see the `nRF54L15 documentation`_ page.
+
+The BL54L15u Development Kit provides support for the Ezurio BL54L15u module.
+
+The module is based on the Nordic Semiconductor nRF54L15 Arm Cortex-M33 CPU.
+
+The BL54L15u module incorporates the WLCSP package nRF54L15 (1524kB Flash, 256kB RAM).
+The part features up to 32 configurable GPIOs and BLE Radio TX Power up to 8dBm.
+
+The module includes the following devices:
+
+* :abbr:`SAADC (Successive Approximation Analog to Digital Converter)`
+* CLOCK
+* RRAM
+* :abbr:`GPIO (General Purpose Input Output)`
+* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)`
+* MEMCONF
+* :abbr:`MPU (Memory Protection Unit)`
+* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
+* :abbr:`PWM (Pulse Width Modulation)`
+* :abbr:`GRTC (Global real-time counter)`
+* Segger RTT (RTT Console)
+* :abbr:`SPI (Serial Peripheral Interface)`
+* :abbr:`UARTE (Universal asynchronous receiver-transmitter)`
+* :abbr:`WDT (Watchdog Timer)`
+
+Hardware
+********
+
+The BL54L15u DVK has two crystal oscillators:
+
+* High-frequency 32 MHz crystal oscillator (HFXO)
+* Low-frequency 32.768 kHz crystal oscillator (LFXO)
+
+The crystal oscillators can be configured to use either
+internal or external capacitors.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+Applications for the ``bl54l15u_dvk/nrf54l15/cpuapp`` board target can be built,
+flashed, and debugged in the usual way. See :ref:`build_an_application` and
+:ref:`application_run` for more details on building and running.
+
+Applications for the ``bl54l15u_dvk/nrf54l15/cpuflpr`` board target need to be
+built using sysbuild to include the ``vpr_launcher`` image for the application core.
+
+Enter the following command to compile ``hello_world`` for the FLPR core:
+
+.. code-block:: console
+
+   west build -p -b bl54l15u_dvk/nrf54l15/cpuflpr --sysbuild
+
+Flashing
+========
+
+As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world`
+application.
+
+.. warning::
+
+   When programming the device, you might get an error similar to the following message::
+
+    ERROR: The operation attempted is unavailable due to readback protection in
+    ERROR: your device. Please use --recover to unlock the device.
+
+   This error occurs when readback protection is enabled.
+   To disable the readback protection, you must *recover* your device.
+
+   Enter the following command to recover the core::
+
+    west flash --recover
+
+   The ``--recover`` command erases the flash memory and then writes a small binary into
+   the recovered flash memory.
+   This binary prevents the readback protection from enabling itself again after a pin
+   reset or power cycle.
+
+Follow the instructions in the :ref:`nordic_segger` page to install
+and configure all the necessary software. Further information can be
+found in :ref:`nordic_segger_flashing`.
+
+To build and program the sample to the BL54L15u DVK, complete the following steps:
+
+First, connect the BL54L15u DVK to your computer using the IMCU USB port on the DVK.
+Next, build the sample by running the following command:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: bl54l15u_dvk/nrf54l15/cpuapp
+   :goals: build flash
+
+Testing the LEDs and buttons on the BL54L15u DVK
+************************************************
+
+Test the BL54L15u DVK with a :zephyr:code-sample:`blinky` sample.
+
+.. _BL54L15u website: https://www.ezurio.com/wireless-modules/bluetooth-modules/bl54-series/bl54l15-micro-series-bluetooth-le-802-15-4-nfc
+.. _nRF54L15 website: https://www.nordicsemi.com/Products/nRF54L15
+.. _nRF54L15 documentation: https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/device_guides/nrf54l/index.html
diff --git a/boards/ezurio/bl54l15u_dvk/doc/img/bl54l15u_dvk.webp b/boards/ezurio/bl54l15u_dvk/doc/img/bl54l15u_dvk.webp
new file mode 100644
index 00000000000..bef2a629baf
Binary files /dev/null and b/boards/ezurio/bl54l15u_dvk/doc/img/bl54l15u_dvk.webp differ
diff --git a/boards/ezurio/bl54l15u_dvk/nrf54l15_cpuapp_common.dtsi b/boards/ezurio/bl54l15u_dvk/nrf54l15_cpuapp_common.dtsi
new file mode 100644
index 00000000000..e630abab4a9
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/nrf54l15_cpuapp_common.dtsi
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* This file is common to the secure and non-secure domain */
+
+#include "bl54l15u_dvk_common.dtsi"
+
+/ {
+	chosen {
+		zephyr,console = &uart20;
+		zephyr,shell-uart = &uart20;
+		zephyr,uart-mcumgr = &uart20;
+		zephyr,bt-mon-uart = &uart20;
+		zephyr,bt-c2h-uart = &uart20;
+		zephyr,flash-controller = &rram_controller;
+		zephyr,flash = &cpuapp_rram;
+		zephyr,ieee802154 = &ieee802154;
+	};
+};
+
+&cpuapp_sram {
+	status = "okay";
+};
+
+&lfxo {
+	load-capacitors = "internal";
+	load-capacitance-femtofarad = <15500>;
+};
+
+&hfxo {
+	load-capacitors = "internal";
+	load-capacitance-femtofarad = <15000>;
+};
+
+&regulators {
+	status = "okay";
+};
+
+&vregmain {
+	status = "okay";
+	regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
+};
+
+&grtc {
+	owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
+	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
+	child-owned-channels = <3 4 7 8 9 10 11>;
+	status = "okay";
+};
+
+&uart20 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};
+
+&radio {
+	status = "okay";
+};
+
+&ieee802154 {
+	status = "okay";
+};
+
+&temp {
+	status = "okay";
+};
+
+&clock {
+	status = "okay";
+};
+
+&spi00 {
+	status = "okay";
+	cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spi00_default>;
+	pinctrl-1 = <&spi00_sleep>;
+	pinctrl-names = "default", "sleep";
+
+	mx25r64: mx25r6435f@0 {
+		compatible = "jedec,spi-nor";
+		status = "okay";
+		reg = <0>;
+		spi-max-frequency = <8000000>;
+		jedec-id = [c2 28 17];
+		sfdp-bfp = [
+			e5 20 f1 ff  ff ff ff 03  44 eb 08 6b  08 3b 04 bb
+			ee ff ff ff  ff ff 00 ff  ff ff 00 ff  0c 20 0f 52
+			10 d8 00 ff  23 72 f5 00  82 ed 04 cc  44 83 48 44
+			30 b0 30 b0  f7 c4 d5 5c  00 be 29 ff  f0 d0 ff ff
+		];
+		size = <67108864>;
+		has-dpd;
+		t-enter-dpd = <10000>;
+		t-exit-dpd = <35000>;
+	};
+};
+
+&adc {
+	status = "okay";
+};
diff --git a/boards/ezurio/bl54l15u_dvk/support/nrf54l15_cpuflpr.JLinkScript b/boards/ezurio/bl54l15u_dvk/support/nrf54l15_cpuflpr.JLinkScript
new file mode 100644
index 00000000000..1cf94ee52a4
--- /dev/null
+++ b/boards/ezurio/bl54l15u_dvk/support/nrf54l15_cpuflpr.JLinkScript
@@ -0,0 +1,5 @@
+int InitTarget(void) {
+  // Base address where DMI registers can be found in the APB address space
+  JLINK_ExecCommand("CORESIGHT_SetCoreBaseAddr = 0x5004C400");
+  return 0;
+}
diff --git a/boards/ezurio/bl652_dvk/bl652_dvk.yaml b/boards/ezurio/bl652_dvk/bl652_dvk.yaml
index a549fcfdd66..4e1a2904366 100644
--- a/boards/ezurio/bl652_dvk/bl652_dvk.yaml
+++ b/boards/ezurio/bl652_dvk/bl652_dvk.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 512
 supported:
diff --git a/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst b/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst
index 27ec3f92928..cdceadb2a34 100644
--- a/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst
+++ b/boards/ezurio/bl652_dvk/doc/bl652_dvk.rst
@@ -43,42 +43,8 @@ Hardware
 Supported Features
 ==================
 
-The BL652 DVK board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `BL652 Module Website`_.
 
 Connections and IOs
@@ -196,6 +162,8 @@ J32/J22 Digital I/O
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/ezurio/bl653_dvk/bl653_dvk.yaml b/boards/ezurio/bl653_dvk/bl653_dvk.yaml
index ee1b610f312..24a17bc8c77 100644
--- a/boards/ezurio/bl653_dvk/bl653_dvk.yaml
+++ b/boards/ezurio/bl653_dvk/bl653_dvk.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - usb_device
diff --git a/boards/ezurio/bl653_dvk/doc/bl653_dvk.rst b/boards/ezurio/bl653_dvk/doc/bl653_dvk.rst
index e4de59757e8..811ce96a517 100644
--- a/boards/ezurio/bl653_dvk/doc/bl653_dvk.rst
+++ b/boards/ezurio/bl653_dvk/doc/bl653_dvk.rst
@@ -33,45 +33,8 @@ Hardware
 Supported Features
 ==================
 
-The BL653 DVK board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `BL653 website`_
 for a complete list of BL653 Development Kit board hardware features.
 
@@ -98,6 +61,8 @@ Push buttons
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``bl653_dvk`` board configuration can be built, flashed,
 and debugged in the usual way. See :ref:`build_an_application` and
 :ref:`application_run` for more details on building and running.
diff --git a/boards/ezurio/bl654_dvk/bl654_dvk.yaml b/boards/ezurio/bl654_dvk/bl654_dvk.yaml
index c4d016d63b6..c43d8f4328a 100644
--- a/boards/ezurio/bl654_dvk/bl654_dvk.yaml
+++ b/boards/ezurio/bl654_dvk/bl654_dvk.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - usb_device
diff --git a/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.dts b/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.dts
index d826a466bfd..ee5d7260fa4 100644
--- a/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.dts
+++ b/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.dts
@@ -9,7 +9,8 @@
 
 / {
 	/* Information from Nordic SDK-Based Application Development and SKY66112 datasheet */
-	sky66112_fem: fem {
+	nrf_radio_fem: fem {
+		status = "okay";
 		compatible = "generic-fem-two-ctrl-pins";
 		ctx-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
 		crx-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
@@ -21,5 +22,5 @@
 };
 
 &radio {
-	fem = <&sky66112_fem>;
+	fem = <&nrf_radio_fem>;
 };
diff --git a/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.yaml b/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.yaml
index 6ecf9191591..d38960a6eed 100644
--- a/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.yaml
+++ b/boards/ezurio/bl654_dvk/bl654_dvk_nrf52840_pa.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - usb_device
diff --git a/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst b/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst
index 5a59932df25..30e23866587 100644
--- a/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst
+++ b/boards/ezurio/bl654_dvk/doc/bl654_dvk.rst
@@ -44,45 +44,8 @@ Hardware
 Supported Features
 ==================
 
-The BL654 DVK board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `BL654 website`_
 for a complete list of BL654 Development Kit board hardware features.
 
@@ -109,6 +72,8 @@ Push buttons
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``bl654_dvk`` board configuration can be built, flashed,
 and debugged in the usual way. See :ref:`build_an_application` and
 :ref:`application_run` for more details on building and running.
diff --git a/boards/ezurio/bl654_sensor_board/bl654_sensor_board.yaml b/boards/ezurio/bl654_sensor_board/bl654_sensor_board.yaml
index bcaafe5669a..0dce5bbbe46 100644
--- a/boards/ezurio/bl654_sensor_board/bl654_sensor_board.yaml
+++ b/boards/ezurio/bl654_sensor_board/bl654_sensor_board.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - ble
diff --git a/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst b/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst
index 373e9bf1bdc..605b5eb8c7f 100644
--- a/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst
+++ b/boards/ezurio/bl654_sensor_board/doc/bl654_sensor_board.rst
@@ -40,43 +40,7 @@ Hardware
 Supported Features
 ==================
 
-The BL654 Sensor Board configuration supports the following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
-See the `BL654 website`_ for a complete list of BL654 module hardware features.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -119,6 +83,8 @@ be blobbed.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``bl654_sensor_board`` board configuration can be built,
 flashed, and debugged in the usual way. See :ref:`build_an_application` and
 :ref:`application_run` for more details on building and running. An external
diff --git a/boards/ezurio/bl654_usb/bl654_usb.yaml b/boards/ezurio/bl654_usb/bl654_usb.yaml
index 4bf396760cc..a56efa32877 100644
--- a/boards/ezurio/bl654_usb/bl654_usb.yaml
+++ b/boards/ezurio/bl654_usb/bl654_usb.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - usb_device
   - ble
diff --git a/boards/ezurio/bl654_usb/doc/bl654_usb.rst b/boards/ezurio/bl654_usb/doc/bl654_usb.rst
index 345331890ec..04ac5759753 100644
--- a/boards/ezurio/bl654_usb/doc/bl654_usb.rst
+++ b/boards/ezurio/bl654_usb/doc/bl654_usb.rst
@@ -36,35 +36,8 @@ Hardware
 Supported Features
 ==================
 
-The BL654 USB board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `BL654 website`_
 for a complete list of BL654 USB adapter hardware features.
 
@@ -92,6 +65,8 @@ Zephyr console output is available as follows:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``bl654_usb`` board configuration can be
 built in the usual way (see :ref:`build_an_application` for more details). The
 ``bl654_usb`` board cannot be used for debugging. The compatible BL654 DVK
@@ -106,8 +81,10 @@ The board supports programming using the built-in bootloader.
 The board is factory-programmed with a Ezurio variation of Nordic's
 open bootloader from Nordic's nRF5x SDK. With this option, you'll use
 Nordic's `nrfutil`_ program to create firmware packages supported by this
-bootloader and flash them to the device. Make sure ``nrfutil`` is installed
-before proceeding. These instructions were tested with version 6.1.0.
+bootloader and flash them to the device. Before proceeding, make sure:
+
+* ``nrfutil`` is installed.
+* The ``nrf5sdk-tools`` command is installed within ``nrfutil``.
 
 #. With the adapter plugged in, reset the board into the bootloader by pressing
    the RESET button.
@@ -132,16 +109,19 @@ before proceeding. These instructions were tested with version 6.1.0.
 
    .. code-block:: console
 
-      nrfutil pkg generate --hw-version 52 --sd-req=0x00 \
-              --application build/zephyr/zephyr.hex \
-              --application-version 1 blinky.zip
+      nrfutil nrf5sdk-tools pkg generate \
+               --hw-version 52 \
+               --sd-req=0x00 \
+               --application build/zephyr/zephyr.hex \
+               --application-version 1 \
+               blinky.zip
 
 #. Flash it onto the board. Note :file:`/dev/ttyACM0` is for Linux; it will be
    something like ``COMx`` on Windows, and something else on macOS.
 
    .. code-block:: console
 
-      nrfutil dfu usb-serial -pkg blinky.zip -p /dev/ttyACM0
+      nrfutil nrf5sdk-tools dfu usb-serial -pkg blinky.zip -p /dev/ttyACM0
 
    When this command exits, observe the blue LED on the board blinking.
 
diff --git a/boards/ezurio/bt510/bt510.yaml b/boards/ezurio/bt510/bt510.yaml
index 198b538eecd..f13cd759f42 100644
--- a/boards/ezurio/bt510/bt510.yaml
+++ b/boards/ezurio/bt510/bt510.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - ble
diff --git a/boards/ezurio/bt510/doc/bt510.rst b/boards/ezurio/bt510/doc/bt510.rst
index fdfd9312ffe..74b4c48703c 100644
--- a/boards/ezurio/bt510/doc/bt510.rst
+++ b/boards/ezurio/bt510/doc/bt510.rst
@@ -36,39 +36,7 @@ Hardware
 Supported Features
 ==================
 
-The BT510 Sensor supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -116,6 +84,8 @@ The BT510 incorporates an I2C Silabs SI7055 temperature sensor. Refer to the `Si
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``bt510`` board configuration can be built, flashed, and
 debugged in the usual way. See :ref:`build_an_application` and
 :ref:`application_run` for more details on building and running.
diff --git a/boards/ezurio/bt610/bt610.yaml b/boards/ezurio/bt610/bt610.yaml
index 5b96d98c527..c56ec758736 100644
--- a/boards/ezurio/bt610/bt610.yaml
+++ b/boards/ezurio/bt610/bt610.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - ble
diff --git a/boards/ezurio/bt610/doc/bt610.rst b/boards/ezurio/bt610/doc/bt610.rst
index 0ae62035a48..afa138eac63 100644
--- a/boards/ezurio/bt610/doc/bt610.rst
+++ b/boards/ezurio/bt610/doc/bt610.rst
@@ -40,43 +40,7 @@ Hardware
 Supported Features
 ==================
 
-The BT610 Sensor supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| QSPI      | on-chip    | qspi                 |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M)    | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 .. figure:: img/bt610_board.jpg
      :align: center
@@ -473,6 +437,8 @@ Required pins are as follows.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``bt610`` board configuration can be
 built and flashed in the usual way (see :ref:`build_an_application`
 and :ref:`application_run` for more details); however, the standard
diff --git a/boards/ezurio/mg100/doc/index.rst b/boards/ezurio/mg100/doc/index.rst
index 5f66c65e147..b2baed38724 100644
--- a/boards/ezurio/mg100/doc/index.rst
+++ b/boards/ezurio/mg100/doc/index.rst
@@ -49,47 +49,7 @@ Hardware
 Supported Features
 ==================
 
-The MG100 board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-| QSPI      | on-chip    | qspi/MX25R64(8MB)    |
-+-----------+------------+----------------------+
-| LIS3DH    | I2C(M)     | sensor/lis3dh        |
-+-----------+------------+----------------------+
-| HL7800    | UART       | HL7800 modem driver  |
-+-----------+------------+----------------------+
-| SDMMC     | SPI(M)     | SD Card via SPI      |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 See `MG100 website`_ for a complete list
 of MG100 hardware features.
@@ -149,6 +109,8 @@ SPI MISO = P0.12
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``mg100`` board configuration can be
 built and flashed in the usual way. (see :ref:`build_an_application`
 and :ref:`application_run` for more details)
diff --git a/boards/ezurio/mg100/mg100.yaml b/boards/ezurio/mg100/mg100.yaml
index 54de18e63ee..bbfd5f81bc7 100644
--- a/boards/ezurio/mg100/mg100.yaml
+++ b/boards/ezurio/mg100/mg100.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - ble
diff --git a/boards/ezurio/pinnacle_100_dvk/doc/index.rst b/boards/ezurio/pinnacle_100_dvk/doc/index.rst
index 71511d8dfc8..d9f8b260efd 100644
--- a/boards/ezurio/pinnacle_100_dvk/doc/index.rst
+++ b/boards/ezurio/pinnacle_100_dvk/doc/index.rst
@@ -52,49 +52,7 @@ Hardware
 Supported Features
 ==================
 
-The Pinnacle 100 development board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-| QSPI      | on-chip    | qspi/MX25R64(8MB)    |
-+-----------+------------+----------------------+
-| BME680    | I2C(M)     | sensor/bme680        |
-+-----------+------------+----------------------+
-| HL7800    | UART       | HL7800 modem driver  |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 See `Pinnacle 100 website`_ for a complete list
 of Pinnacle 100 Development Kit hardware features.
@@ -122,6 +80,8 @@ Push buttons
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``pinnacle_100_dvk`` board configuration can be
 built and flashed in the usual way. (see :ref:`build_an_application`
 and :ref:`application_run` for more details)
diff --git a/boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk.yaml b/boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk.yaml
index 3d44a009e2d..5888bc4febc 100644
--- a/boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk.yaml
+++ b/boards/ezurio/pinnacle_100_dvk/pinnacle_100_dvk.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - ble
diff --git a/boards/ezurio/rm1xx_dvk/doc/index.rst b/boards/ezurio/rm1xx_dvk/doc/index.rst
index 8462f92c1b2..ebb994540eb 100644
--- a/boards/ezurio/rm1xx_dvk/doc/index.rst
+++ b/boards/ezurio/rm1xx_dvk/doc/index.rst
@@ -48,40 +48,8 @@ is 16MHz.
 Supported Features
 ==================
 
-The rm1xx_dvk board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| SPU       | on-chip    | system protection    |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `Nordic Semiconductor Infocenter`_
 for a complete list of hardware features.
 
@@ -125,6 +93,8 @@ Refer to the `Semtech SX1272 datasheet`_ for further details.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/fanke/fk743m5_xih6/Kconfig.fk743m5_xih6 b/boards/fanke/fk743m5_xih6/Kconfig.fk743m5_xih6
new file mode 100644
index 00000000000..b429435dd09
--- /dev/null
+++ b/boards/fanke/fk743m5_xih6/Kconfig.fk743m5_xih6
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 zack jiang, Honbo He <hehongbo918@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FK743M5_XIH6
+	select SOC_STM32H743XX
diff --git a/boards/fanke/fk743m5_xih6/board.cmake b/boards/fanke/fk743m5_xih6/board.cmake
new file mode 100644
index 00000000000..10170d65424
--- /dev/null
+++ b/boards/fanke/fk743m5_xih6/board.cmake
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(openocd --target-handle=_CHIPNAME.cpu0)
+board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
+board_runner_args(jlink "--device=STM32H743XI" "--speed=4000")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/fanke/fk743m5_xih6/board.yml b/boards/fanke/fk743m5_xih6/board.yml
new file mode 100644
index 00000000000..b6a9f42f25d
--- /dev/null
+++ b/boards/fanke/fk743m5_xih6/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: fk743m5_xih6
+  full_name: FK743M5-XIH6
+  vendor: fanke
+  socs:
+    - name: stm32h743xx
diff --git a/boards/fanke/fk743m5_xih6/doc/img/fk743m5_xih6.webp b/boards/fanke/fk743m5_xih6/doc/img/fk743m5_xih6.webp
new file mode 100644
index 00000000000..733b0efc806
Binary files /dev/null and b/boards/fanke/fk743m5_xih6/doc/img/fk743m5_xih6.webp differ
diff --git a/boards/fanke/fk743m5_xih6/doc/index.rst b/boards/fanke/fk743m5_xih6/doc/index.rst
new file mode 100644
index 00000000000..0c7dbbfbe44
--- /dev/null
+++ b/boards/fanke/fk743m5_xih6/doc/index.rst
@@ -0,0 +1,131 @@
+.. zephyr:board:: fk743m5_xih6
+
+Overview
+********
+
+The FK743M5-XIH6 core board by FANKE Technology Co., Ltd. is an advanced microcontroller
+platform based on the STMicroelectronics Arm® Cortex®-M7 core STM32H743XIH6 microcontroller.
+This board is an ideal solution for developers looking to create high-performance
+applications, leveraging its robust capabilities and support for sophisticated display
+and image processing technologies.
+
+The FK743M5-XIH6 is designed as a reference design for user application development before
+transitioning to the final product, significantly simplifying the development process.
+Its wide range of hardware features, including advanced display and image processing capabilities,
+allowing for comprehensive evaluation and testing of peripherals and functionalities.
+
+Hardware
+********
+
+FK743M5-XIH6 provides the following hardware components:
+
+- STM32H743XI in 265-TFBGA package
+- ARM 32-bit Cortex-M7 CPU with FPU
+- 480 MHz max CPU frequency
+- 2048 KB Flash
+- 1 MB SRAM: 192 Kbytes TCM RAM (64 Kbytes ITCM RAM + 128 Kbytes DTCM RAM), 864 Kbytes user SRAM, and 4 Kbytes SRAM in Backup domain
+- Main clock: External 25MHz crystal oscillator.
+- RTC: 32.768kHz crystal oscillator.
+- high-resolution timers(2.1 ns max resolution, 1)
+- 32-bit timers(2)
+- 16-bit timers(17)
+- 1 reset button, and 1 BOOT button
+- 1 user LED
+- External 64-Mbit QSPI (W25Q64) NOR Flash memory.
+- USB OTG Full Speed and High Speed(1)
+- 1 micro SD card
+- 1 DCMI camera interface
+- 1 SPI LCD interface
+- SWD and serial port accessibility through a pin header
+- Bring out 83 IO ports
+
+More information about STM32H743XI can be found here:
+
+- `STM32H743XI on www.st.com`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Pin Mapping
+===========
+
+FK743M5-XIH6 board has 5 GPIO controllers. These controllers are responsible for pin muxing,
+input/output, pull-up, etc.
+
+Default Zephyr Peripheral Mapping
+---------------------------------
+
+The FK743M5-XIH6 board is configured as follows
+
+- UART_1 TX/RX : PA9/PA10 (available on the header pins)
+- User LED (blue) : PC13
+- SPI5 NCS/CLK/MOSI : PE11/PE12/PE14 (SPI LCD)
+- QuadSPI NCS/CLK/IO0/IO1/IO2/IO3 : PG6/PF10/PF8/PF9/PF7/PF6 (NOR Flash)
+- USB DM/DP : PA11/PA12
+
+System Clock
+============
+
+The FK743M5-XIH6 System Clock could be driven by an internal or external oscillator,
+as well as by the main PLL clock. By default the system clock is driven by the PLL clock at 480MHz,
+driven by an 25MHz external crystal oscillator.
+
+Serial Port
+===========
+
+The Zephyr console output is assigned to UART1. The default communication settings are 115200 8N1.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``fk743m5_xih6`` board target can be built and flashed in the usual
+way (see :ref:`build_an_application` and :ref:`application_run` for more details).
+
+Flashing
+========
+
+The FK743M5-XIH6 board does not include an on-board debugger. As a result, it requires
+an external debugger, such as ST-Link, for programming and debugging purposes.
+
+The board provides header pins for the Serial Wire Debug (SWD) interface.
+
+Flashing an application to FK743M5-XIH6
+---------------------------------------
+
+To begin, connect the ST-Link Debug Programmer to the FK743M5-XIH6 board using the SWD
+interface. Next, connect the ST-Link to your host computer via a USB port.
+Once this setup is complete, you can proceed to build and flash your application to the board
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: fk743m5_xih6
+   :goals: build flash
+
+Run a serial host program to connect with your board:
+
+.. code-block:: console
+
+   $ minicom -D /dev/ttyACM0 -b 115200
+
+Then, press the RESET button, you should see the following message:
+
+.. code-block:: console
+
+   Hello World! fk743m5_xih6
+
+Debugging
+=========
+
+This current Zephyr port does not support debugging.
+
+References
+**********
+
+.. target-notes::
+.. _STM32H743XI on www.st.com: https://www.st.com/en/microcontrollers/stm32h743xi.html
diff --git a/boards/fanke/fk743m5_xih6/fk743m5_xih6.dts b/boards/fanke/fk743m5_xih6/fk743m5_xih6.dts
new file mode 100644
index 00000000000..93f9cd88847
--- /dev/null
+++ b/boards/fanke/fk743m5_xih6/fk743m5_xih6.dts
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2025 zack jiang, Honbo He <hehongbo918@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/h7/stm32h743Xi.dtsi>
+#include <st/h7/stm32h743xihx-pinctrl.dtsi>
+
+/ {
+	model = "FANKE FK743M5-XIH6 board";
+	compatible = "fanke,fk743m5-xih6";
+
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		user_led: led_0 {
+			gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
+			label = "User LED";
+		};
+	};
+
+	aliases {
+		led0 = &user_led;
+	};
+};
+
+&clk_hsi48 {
+	status = "okay";
+};
+
+&clk_hse {
+	clock-frequency = <DT_FREQ_M(25)>;
+	status = "okay";
+};
+
+&pll {
+	div-m = <5>;
+	mul-n = <192>;
+	div-p = <2>;
+	div-q = <4>;
+	div-r = <4>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&pll3 {
+	div-m = <5>;
+	mul-n = <192>;
+	div-p = <2>;
+	div-q = <20>;
+	div-r = <99>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(480)>;
+	d1cpre = <1>;
+	hpre = <2>;
+	d1ppre = <2>;
+	d2ppre1 = <2>;
+	d2ppre2 = <2>;
+	d3ppre = <2>;
+};
+
+&quadspi {
+	pinctrl-0 = <&quadspi_bk1_io0_pf8 &quadspi_bk1_io1_pf9
+		     &quadspi_bk1_io2_pf7 &quadspi_bk1_io3_pf6
+		     &quadspi_clk_pf10 &quadspi_bk1_ncs_pg6>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	/* Winbond external flash */
+	w25q64_qspi: qspi-nor-flash@90000000 {
+		compatible = "st,stm32-qspi-nor";
+		reg = <0x90000000 DT_SIZE_M(8)>; /* 64 Mbits */
+		qspi-max-frequency = <40000000>;
+		status = "okay";
+		spi-bus-width = <4>;
+		writeoc = "PP_1_1_4";
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			storage_partition: partition@0 {
+				label = "storage";
+				reg = <0x00000000 DT_SIZE_M(8)>;
+			};
+		};
+	};
+};
+
+&usart1 {
+	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&backup_sram {
+	status = "okay";
+};
+
+&rng {
+	status = "okay";
+};
diff --git a/boards/fanke/fk743m5_xih6/fk743m5_xih6.yaml b/boards/fanke/fk743m5_xih6/fk743m5_xih6.yaml
new file mode 100644
index 00000000000..932fcb5f3f4
--- /dev/null
+++ b/boards/fanke/fk743m5_xih6/fk743m5_xih6.yaml
@@ -0,0 +1,16 @@
+identifier: fk743m5_xih6
+name: FANKE FK743M5-XIH6
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 1024
+flash: 2048
+supported:
+  - uart
+  - gpio
+  - spi
+  - backup_sram
+  - qspi
+vendor: fanke
diff --git a/boards/fanke/fk743m5_xih6/fk743m5_xih6_defconfig b/boards/fanke/fk743m5_xih6/fk743m5_xih6_defconfig
new file mode 100644
index 00000000000..13a1289e51c
--- /dev/null
+++ b/boards/fanke/fk743m5_xih6/fk743m5_xih6_defconfig
@@ -0,0 +1,18 @@
+# Copyright (c) zack jiang, Honbo He <hehongbo918@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable UART
+CONFIG_SERIAL=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
diff --git a/boards/fanke/fk743m5_xih6/support/openocd.cfg b/boards/fanke/fk743m5_xih6/support/openocd.cfg
new file mode 100644
index 00000000000..4ea6d13db0b
--- /dev/null
+++ b/boards/fanke/fk743m5_xih6/support/openocd.cfg
@@ -0,0 +1,25 @@
+# Copyright (c) zack jiang, Honbo He <hehongbo918@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+source [find interface/stlink-dap.cfg]
+transport select "dapdirect_swd"
+
+set WORKAREASIZE 0x8000
+
+set CHIPNAME STM32H743XI
+set BOARDNAME FK743M5-XIH6
+
+source [find target/stm32h7x.cfg]
+
+# Enable debug when in low power modes
+set ENABLE_LOW_POWER 1
+
+# Stop Watchdog counters when halt
+set STOP_WATCHDOG 1
+
+# Reset configuration
+# use hardware reset, connect under reset
+# connect_assert_srst needed if low power mode application running (WFI...)
+reset_config srst_only srst_nogate connect_assert_srst
+set CONNECT_UNDER_RESET 1
+set CORE_RESET 0
diff --git a/boards/fanke/fk750m1_vbt6/doc/index.rst b/boards/fanke/fk750m1_vbt6/doc/index.rst
index 6a558bddc08..f5340f336b6 100644
--- a/boards/fanke/fk750m1_vbt6/doc/index.rst
+++ b/boards/fanke/fk750m1_vbt6/doc/index.rst
@@ -46,35 +46,7 @@ More information about STM32H750VB can be found here:
 Supported Features
 ==================
 
-The Zephyr ``fk750m1_vbt6`` board target supports the following hardware
-features:
-
-+-------------+------------+-------------------------------------+
-| Interface   | Controller | Driver/Component                    |
-+=============+============+=====================================+
-| NVIC        | on-chip    | nested vector interrupt controller  |
-+-------------+------------+-------------------------------------+
-| FLASH       | on-chip    | flash memory                        |
-+-------------+------------+-------------------------------------+
-| UART        | on-chip    | serial port                         |
-+-------------+------------+-------------------------------------+
-| PINMUX      | on-chip    | pinmux                              |
-+-------------+------------+-------------------------------------+
-| GPIO        | on-chip    | gpio                                |
-+-------------+------------+-------------------------------------+
-| RNG         | on-chip    | True Random number generator        |
-+-------------+------------+-------------------------------------+
-| Backup SRAM | on-chip    | Backup SRAM                         |
-+-------------+------------+-------------------------------------+
-| SPI         | on-chip    | spi bus                             |
-+-------------+------------+-------------------------------------+
-| QUADSPI     | on-chip    | quadspi                             |
-+-------------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration per core can be found in
-:zephyr_file:`boards/fanke/fk750m1_vbt6/fk750m1_vbt6_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -108,6 +80,8 @@ The Zephyr console output is assigned to UART1. The default communication settin
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``fk750m1_vbt6`` board target can be built and flashed in the usual
 way (see :ref:`build_an_application` and :ref:`application_run` for more details).
 
diff --git a/boards/fanke/fk750m1_vbt6/fk750m1_vbt6.yaml b/boards/fanke/fk750m1_vbt6/fk750m1_vbt6.yaml
index ffb5170ae82..e436cc6dc0a 100644
--- a/boards/fanke/fk750m1_vbt6/fk750m1_vbt6.yaml
+++ b/boards/fanke/fk750m1_vbt6/fk750m1_vbt6.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 1024
 flash: 128
 supported:
diff --git a/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.yaml b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.yaml
index e50692f318a..6012823f29c 100644
--- a/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.yaml
+++ b/boards/fanke/fk7b0m1_vbt6/fk7b0m1_vbt6.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 1376
 flash: 128
 supported:
diff --git a/boards/firefly/roc_rk3568_pc/doc/index.rst b/boards/firefly/roc_rk3568_pc/doc/index.rst
index bd55e747c51..e26092db576 100644
--- a/boards/firefly/roc_rk3568_pc/doc/index.rst
+++ b/boards/firefly/roc_rk3568_pc/doc/index.rst
@@ -42,18 +42,7 @@ has frequency up to 2.0GHz. Zephyr OS is ported to run on it.
 Supported Features
 ==================
 
-The Zephyr roc_rk3568_pc board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| GIC-v3    | on-chip    | interrupt controller                |
-+-----------+------------+-------------------------------------+
-| ARM TIMER | on-chip    | system clock                        |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Devices
 ========
@@ -72,6 +61,8 @@ CPU's UART2.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Use U-Boot to load the zephyr.bin to the memory and kick it:
 
 .. code-block:: console
diff --git a/boards/franzininho/esp32s2_franzininho/doc/index.rst b/boards/franzininho/esp32s2_franzininho/doc/index.rst
index 47f223b83ca..bdbc20574ec 100644
--- a/boards/franzininho/esp32s2_franzininho/doc/index.rst
+++ b/boards/franzininho/esp32s2_franzininho/doc/index.rst
@@ -47,6 +47,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts
index beee6810d62..f5e6429233a 100644
--- a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts
+++ b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.dts
@@ -22,7 +22,7 @@
 	};
 
 	chosen {
-		zephyr,sram = &sram0;
+		zephyr,sram = &sram1;
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
 		zephyr,flash = &flash0;
@@ -111,3 +111,7 @@
 &wdt0 {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml
index da3da1bdc3a..4fc82a2f23d 100644
--- a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml
+++ b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho.yaml
@@ -14,4 +14,5 @@ supported:
 testing:
   ignore_tags:
     - heap
+    - bluetooth
 vendor: franzininho
diff --git a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho_defconfig b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho_defconfig
index f566acd9340..e192c240251 100644
--- a/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho_defconfig
+++ b/boards/franzininho/esp32s2_franzininho/esp32s2_franzininho_defconfig
@@ -1,9 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-
-
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/fysetc/ucan/doc/index.rst b/boards/fysetc/ucan/doc/index.rst
index f9b4b53809f..725d87e62a4 100644
--- a/boards/fysetc/ucan/doc/index.rst
+++ b/boards/fysetc/ucan/doc/index.rst
@@ -16,28 +16,7 @@ drawings are available in the `UCAN GitHub repository`_.
 Supported Features
 ==================
 
-The ``ucan`` board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB                                 |
-+-----------+------------+-------------------------------------+
-| CAN1      | on-chip    | CAN controller                      |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/fysetc/ucan/ucan_defconfig`.
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 System Clock
 ============
@@ -48,6 +27,8 @@ configured to provide a system clock of 48 MHz.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
diff --git a/boards/gaisler/generic_leon3/doc/index.rst b/boards/gaisler/generic_leon3/doc/index.rst
index 9f7781f3e21..0dde96f2fc7 100644
--- a/boards/gaisler/generic_leon3/doc/index.rst
+++ b/boards/gaisler/generic_leon3/doc/index.rst
@@ -17,6 +17,8 @@ M2GL-EVAL-KIT.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Building
 ========
 
diff --git a/boards/gaisler/generic_leon3/generic_leon3.yaml b/boards/gaisler/generic_leon3/generic_leon3.yaml
index 62130690461..206eedbabc9 100644
--- a/boards/gaisler/generic_leon3/generic_leon3.yaml
+++ b/boards/gaisler/generic_leon3/generic_leon3.yaml
@@ -9,7 +9,6 @@ ram: 4096
 flash: 2048
 toolchain:
   - zephyr
-  - xtools
 supported:
   - netif
 testing:
diff --git a/boards/gaisler/gr716a_mini/doc/index.rst b/boards/gaisler/gr716a_mini/doc/index.rst
index 0f723306105..77cf7231192 100644
--- a/boards/gaisler/gr716a_mini/doc/index.rst
+++ b/boards/gaisler/gr716a_mini/doc/index.rst
@@ -26,6 +26,8 @@ if enabled in GRMON, is preserved.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Building
 ========
 
diff --git a/boards/gaisler/gr716a_mini/gr716a_mini.yaml b/boards/gaisler/gr716a_mini/gr716a_mini.yaml
index 4d2743602c6..8625d54c095 100644
--- a/boards/gaisler/gr716a_mini/gr716a_mini.yaml
+++ b/boards/gaisler/gr716a_mini/gr716a_mini.yaml
@@ -7,7 +7,6 @@ simulation:
 arch: sparc
 toolchain:
   - zephyr
-  - xtools
 supported:
   - netif
   - spi
diff --git a/boards/gardena/sgrm/doc/index.rst b/boards/gardena/sgrm/doc/index.rst
index 40d05a9f4f3..5b0da0a61c7 100644
--- a/boards/gardena/sgrm/doc/index.rst
+++ b/boards/gardena/sgrm/doc/index.rst
@@ -24,24 +24,7 @@ Hardware
 Supported Features
 ==================
 
-The ``sgrm`` board target supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma                                 |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -77,6 +60,8 @@ Connections and IOs
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/gardena/sgrm/sgrm.yaml b/boards/gardena/sgrm/sgrm.yaml
index fe14fefec88..9488fca96fc 100644
--- a/boards/gardena/sgrm/sgrm.yaml
+++ b/boards/gardena/sgrm/sgrm.yaml
@@ -10,7 +10,6 @@ ram: 32
 flash: 256
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 supported:
   - dma
diff --git a/boards/gd/gd32a503v_eval/doc/index.rst b/boards/gd/gd32a503v_eval/doc/index.rst
index 8fcec05bdc3..27e715227a7 100644
--- a/boards/gd/gd32a503v_eval/doc/index.rst
+++ b/boards/gd/gd32a503v_eval/doc/index.rst
@@ -39,47 +39,7 @@ For more information about the GD32A503 SoC and GD32A503V-EVAL board:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - EXTI
-     - :kconfig:option:`CONFIG_GD32_EXTI`
-     - :dtcompatible:`gd,gd32-exti`
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`gd,gd32-gpio`
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v8m-nvic`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM`
-     - :dtcompatible:`gd,gd32-pwm`
-   * - SYSTICK
-     - N/A
-     - N/A
-   * - USART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`gd,gd32-usart`
-   * - PINMUX
-     - :kconfig:option:`CONFIG_PINCTRL`
-     - :dtcompatible:`gd,gd32-pinctrl-af`
-   * - ADC
-     - :kconfig:option:`CONFIG_ADC`
-     - :dtcompatible:`gd,gd32-adc`
-   * - DAC
-     - :kconfig:option:`CONFIG_DAC`
-     - :dtcompatible:`gd,gd32-dac`
-   * - FMC
-     - N/A
-     - :dtcompatible:`gd,gd32-flash-controller`
-   * - SPI
-     - :kconfig:option:`CONFIG_SPI`
-     - :dtcompatible:`gd,gd32-spi`
+.. zephyr:board-supported-hw::
 
 Serial Port
 ===========
@@ -90,6 +50,8 @@ is UART0 at PIN-72 and PIN-73.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Before program your board make sure to configure boot setting and serial port.
 The default serial port is USART0.
 
diff --git a/boards/gd/gd32a503v_eval/gd32a503v_eval.yaml b/boards/gd/gd32a503v_eval/gd32a503v_eval.yaml
index e2e2145d9af..3182b92a191 100644
--- a/boards/gd/gd32a503v_eval/gd32a503v_eval.yaml
+++ b/boards/gd/gd32a503v_eval/gd32a503v_eval.yaml
@@ -10,7 +10,6 @@ flash: 384
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - counter
diff --git a/boards/gd/gd32e103v_eval/doc/index.rst b/boards/gd/gd32e103v_eval/doc/index.rst
index 382bed8c7de..49d6f799199 100644
--- a/boards/gd/gd32e103v_eval/doc/index.rst
+++ b/boards/gd/gd32e103v_eval/doc/index.rst
@@ -43,24 +43,7 @@ For more information about the GD32E103 SoC and GD32E103V-EVAL board:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v7m-nvic`
-   * - SYSTICK
-     - N/A
-     - N/A
-   * - USART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`gd,gd32-usart`
-
+.. zephyr:board-supported-hw::
 
 Serial Port
 ===========
@@ -71,6 +54,8 @@ is UART0 at PIN-9 and PIN-10.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Before program your board make sure to configure boot setting and serial port.
 The default serial port is USART0.  This port uses header JP-5/6 to route
 signals between USB VBUS/ID and USART J2.
diff --git a/boards/gd/gd32e103v_eval/gd32e103v_eval.yaml b/boards/gd/gd32e103v_eval/gd32e103v_eval.yaml
index a5dd9ba759b..203ef2d95e9 100644
--- a/boards/gd/gd32e103v_eval/gd32e103v_eval.yaml
+++ b/boards/gd/gd32e103v_eval/gd32e103v_eval.yaml
@@ -10,7 +10,6 @@ flash: 128
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - dac
   - counter
diff --git a/boards/gd/gd32e507v_start/doc/index.rst b/boards/gd/gd32e507v_start/doc/index.rst
index a8b8f7a9469..68eaf60ef49 100644
--- a/boards/gd/gd32e507v_start/doc/index.rst
+++ b/boards/gd/gd32e507v_start/doc/index.rst
@@ -30,34 +30,7 @@ For more information about the GD32E507 SoC and GD32E507V-START board:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - EXTI
-     - :kconfig:option:`CONFIG_GD32_EXTI`
-     - :dtcompatible:`gd,gd32-exti`
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`gd,gd32-gpio`
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v8m-nvic`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM`
-     - :dtcompatible:`gd,gd32-pwm`
-   * - SYSTICK
-     - N/A
-     - N/A
-   * - USART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`gd,gd32-usart`
-
-Other peripherals may be used if shields are connected to the board.
+.. zephyr:board-supported-hw::
 
 Serial Port
 ===========
@@ -69,6 +42,8 @@ virtual COM port via the CN3 USB connector.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Before programming your board make sure to configure boot jumpers as
 follows:
 
diff --git a/boards/gd/gd32e507v_start/gd32e507v_start.yaml b/boards/gd/gd32e507v_start/gd32e507v_start.yaml
index 8a1b4e4b89b..3e216953ec8 100644
--- a/boards/gd/gd32e507v_start/gd32e507v_start.yaml
+++ b/boards/gd/gd32e507v_start/gd32e507v_start.yaml
@@ -10,7 +10,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - pwm
   - gpio
diff --git a/boards/gd/gd32e507z_eval/doc/index.rst b/boards/gd/gd32e507z_eval/doc/index.rst
index 610562b3eae..f43863fbadb 100644
--- a/boards/gd/gd32e507z_eval/doc/index.rst
+++ b/boards/gd/gd32e507z_eval/doc/index.rst
@@ -40,32 +40,7 @@ For more information about the GD32E507 SoC and GD32E507Z-EVAL board:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - EXTI
-     - :kconfig:option:`CONFIG_GD32_EXTI`
-     - :dtcompatible:`gd,gd32-exti`
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`gd,gd32-gpio`
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v8m-nvic`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM`
-     - :dtcompatible:`gd,gd32-pwm`
-   * - SYSTICK
-     - N/A
-     - N/A
-   * - USART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`gd,gd32-usart`
+.. zephyr:board-supported-hw::
 
 Serial Port
 ===========
@@ -77,6 +52,8 @@ virtual COM port via the J1 USB connector.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Before programming your board make sure to configure boot jumpers as
 follows:
 
diff --git a/boards/gd/gd32e507z_eval/gd32e507z_eval.yaml b/boards/gd/gd32e507z_eval/gd32e507z_eval.yaml
index 594df3a5f8d..f4174207b84 100644
--- a/boards/gd/gd32e507z_eval/gd32e507z_eval.yaml
+++ b/boards/gd/gd32e507z_eval/gd32e507z_eval.yaml
@@ -10,7 +10,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - pwm
   - gpio
diff --git a/boards/gd/gd32f350r_eval/doc/index.rst b/boards/gd/gd32f350r_eval/doc/index.rst
index 2c7ad726352..e30ab453690 100644
--- a/boards/gd/gd32f350r_eval/doc/index.rst
+++ b/boards/gd/gd32f350r_eval/doc/index.rst
@@ -35,29 +35,7 @@ For more information about the GD32F350 SoC and GD32F350R-EVAL board:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v7m-nvic`
-   * - SYSTICK
-     - N/A
-     - N/A
-   * - USART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`gd,gd32-usart`
-   * - PINMUX
-     - :kconfig:option:`CONFIG_PINCTRL`
-     - :dtcompatible:`gd,gd32-pinctrl-af`
-   * - ADC
-     - :kconfig:option:`CONFIG_ADC`
-     - :dtcompatible:`gd,gd32-adc`
+.. zephyr:board-supported-hw::
 
 Serial Port
 ===========
@@ -68,6 +46,8 @@ is USART0 with TX connected at PA9 and RX at PA10.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Before programming your board make sure to configure boot and serial jumpers as follows:
 
 - J4:  Select 2-3 for both (labeled as ``L``)
diff --git a/boards/gd/gd32f350r_eval/gd32f350r_eval.yaml b/boards/gd/gd32f350r_eval/gd32f350r_eval.yaml
index 17834719ff1..1133959c2f4 100644
--- a/boards/gd/gd32f350r_eval/gd32f350r_eval.yaml
+++ b/boards/gd/gd32f350r_eval/gd32f350r_eval.yaml
@@ -10,7 +10,6 @@ flash: 128
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - watchdog
   - dma
diff --git a/boards/gd/gd32f403z_eval/doc/index.rst b/boards/gd/gd32f403z_eval/doc/index.rst
index d304094a3e7..7d2ca320ca7 100644
--- a/boards/gd/gd32f403z_eval/doc/index.rst
+++ b/boards/gd/gd32f403z_eval/doc/index.rst
@@ -43,27 +43,7 @@ For more information about the GD32F403 SoC and GD32F403Z-Eval board:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-+-----------+------------+-----------------------+
-| Interface | Controller | Driver/Component      |
-+===========+============+=======================+
-| EXTI      | on-chip    | EXTI interrupt        |
-|           |            | controller            |
-+-----------+------------+-----------------------+
-| GPIO      | on-chip    | gpio                  |
-+-----------+------------+-----------------------+
-| NVIC      | on-chip    | nested vectored       |
-|           |            | interrupt controller  |
-+-----------+------------+-----------------------+
-| PWM       | on-chip    | PWM                   |
-+-----------+------------+-----------------------+
-| SYSTICK   | on-chip    | system clock          |
-+-----------+------------+-----------------------+
-| UART      | on-chip    | serial port-polling   |
-+-----------+------------+-----------------------+
-| ADC       | on-chip    | ADC                   |
-+-----------+------------+-----------------------+
+.. zephyr:board-supported-hw::
 
 Serial Port
 ===========
@@ -74,6 +54,8 @@ is UART0 at PIN-9 and PIN-10.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Before program your board make sure to configure boot setting and serial port.
 The default serial port is USART0.  This port uses header JP-5/6 to route
 signals between USB VBUS/ID and USART J2.
diff --git a/boards/gd/gd32f403z_eval/gd32f403z_eval.yaml b/boards/gd/gd32f403z_eval/gd32f403z_eval.yaml
index 1bec175723a..675d101ad31 100644
--- a/boards/gd/gd32f403z_eval/gd32f403z_eval.yaml
+++ b/boards/gd/gd32f403z_eval/gd32f403z_eval.yaml
@@ -10,7 +10,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - pwm
diff --git a/boards/gd/gd32f407v_start/doc/index.rst b/boards/gd/gd32f407v_start/doc/index.rst
index 68332eb51b8..615659bf820 100644
--- a/boards/gd/gd32f407v_start/doc/index.rst
+++ b/boards/gd/gd32f407v_start/doc/index.rst
@@ -30,34 +30,7 @@ For more information about the GD32F407 SoC and GD32F407V-START board:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - EXTI
-     - :kconfig:option:`CONFIG_GD32_EXTI`
-     - :dtcompatible:`gd,gd32-exti`
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`gd,gd32-gpio`
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v7m-nvic`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM`
-     - :dtcompatible:`gd,gd32-pwm`
-   * - SYSTICK
-     - N/A
-     - N/A
-   * - USART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`gd,gd32-usart`
-
-Other peripherals may be used if shields are connected to the board.
+.. zephyr:board-supported-hw::
 
 Serial Port
 ===========
@@ -68,6 +41,8 @@ is USART0 with TX connected at PB6 and RX at PB7.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Before programming your board make sure to configure boot jumpers as
 follows:
 
diff --git a/boards/gd/gd32f407v_start/gd32f407v_start.yaml b/boards/gd/gd32f407v_start/gd32f407v_start.yaml
index e79982ef6e8..418a6be76e1 100644
--- a/boards/gd/gd32f407v_start/gd32f407v_start.yaml
+++ b/boards/gd/gd32f407v_start/gd32f407v_start.yaml
@@ -10,7 +10,6 @@ flash: 3072
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - pwm
   - gpio
diff --git a/boards/gd/gd32f450i_eval/doc/index.rst b/boards/gd/gd32f450i_eval/doc/index.rst
index d342cc9774d..05b2c20ba7a 100644
--- a/boards/gd/gd32f450i_eval/doc/index.rst
+++ b/boards/gd/gd32f450i_eval/doc/index.rst
@@ -43,44 +43,7 @@ For more information about the GD32F450 SoC and GD32F450I-EVAL board:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - EXTI
-     - :kconfig:option:`CONFIG_GD32_EXTI`
-     - :dtcompatible:`gd,gd32-exti`
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`gd,gd32-gpio`
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v7m-nvic`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM`
-     - :dtcompatible:`gd,gd32-pwm`
-   * - SYSTICK
-     - N/A
-     - N/A
-   * - USART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`gd,gd32-usart`
-   * - DAC
-     - :kconfig:option:`CONFIG_DAC`
-     - :dtcompatible:`gd,gd32-dac`
-   * - I2C
-     - :kconfig:option:`CONFIG_I2C`
-     - :dtcompatible:`gd,gd32-i2c`
-   * - EEPROM
-     - :kconfig:option:`CONFIG_EEPROM`
-     - :dtcompatible:`atmel,at24`
-   * - ADC
-     - :kconfig:option:`CONFIG_ADC`
-     - :dtcompatible:`gd,gd32-adc`
+.. zephyr:board-supported-hw::
 
 Serial Port
 ===========
@@ -91,6 +54,8 @@ is USART0 with TX connected at PA9 and RX at PA10.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Before programming your board make sure to configure boot and serial jumpers
 as follows:
 
diff --git a/boards/gd/gd32f450i_eval/gd32f450i_eval.yaml b/boards/gd/gd32f450i_eval/gd32f450i_eval.yaml
index 88ac1c0f558..c4e95480151 100644
--- a/boards/gd/gd32f450i_eval/gd32f450i_eval.yaml
+++ b/boards/gd/gd32f450i_eval/gd32f450i_eval.yaml
@@ -10,7 +10,6 @@ flash: 3072
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - dac
   - pwm
diff --git a/boards/gd/gd32f450v_start/doc/index.rst b/boards/gd/gd32f450v_start/doc/index.rst
index 36870e0c667..6105b6afc16 100644
--- a/boards/gd/gd32f450v_start/doc/index.rst
+++ b/boards/gd/gd32f450v_start/doc/index.rst
@@ -30,34 +30,7 @@ For more information about the GD32F450 SoC and GD32F450V-START board:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - EXTI
-     - :kconfig:option:`CONFIG_GD32_EXTI`
-     - :dtcompatible:`gd,gd32-exti`
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`gd,gd32-gpio`
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v8m-nvic`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM`
-     - :dtcompatible:`gd,gd32-pwm`
-   * - SYSTICK
-     - N/A
-     - N/A
-   * - USART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`gd,gd32-usart`
-
-Other peripherals may be used if shields are connected to the board.
+.. zephyr:board-supported-hw::
 
 Serial Port
 ===========
@@ -70,6 +43,8 @@ UART-USB adapter.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Before programming your board make sure to configure boot jumpers as
 follows:
 
diff --git a/boards/gd/gd32f450v_start/gd32f450v_start.yaml b/boards/gd/gd32f450v_start/gd32f450v_start.yaml
index 62cf201bcd2..ede877bb156 100644
--- a/boards/gd/gd32f450v_start/gd32f450v_start.yaml
+++ b/boards/gd/gd32f450v_start/gd32f450v_start.yaml
@@ -10,7 +10,6 @@ flash: 3072
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - pwm
   - gpio
diff --git a/boards/gd/gd32f450z_eval/doc/index.rst b/boards/gd/gd32f450z_eval/doc/index.rst
index 5a8d8b74763..7b012d1ddb2 100644
--- a/boards/gd/gd32f450z_eval/doc/index.rst
+++ b/boards/gd/gd32f450z_eval/doc/index.rst
@@ -41,41 +41,7 @@ For more information about the GD32F450 SoC and GD32F450Z-EVAL board:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - EXTI
-     - :kconfig:option:`CONFIG_GD32_EXTI`
-     - :dtcompatible:`gd,gd32-exti`
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`gd,gd32-gpio`
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v7m-nvic`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM`
-     - :dtcompatible:`gd,gd32-pwm`
-   * - SYSTICK
-     - N/A
-     - N/A
-   * - USART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`gd,gd32-usart`
-   * - DAC
-     - :kconfig:option:`CONFIG_DAC`
-     - :dtcompatible:`gd,gd32-dac`
-   * - I2C
-     - :kconfig:option:`CONFIG_I2C`
-     - :dtcompatible:`gd,gd32-i2c`
-   * - EEPROM
-     - :kconfig:option:`CONFIG_EEPROM`
-     - :dtcompatible:`atmel,at24`
+.. zephyr:board-supported-hw::
 
 Serial Port
 ===========
@@ -86,6 +52,8 @@ is USART0 with TX connected at PA9 and RX at PA10.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Before programming your board make sure to configure boot and serial jumpers
 as follows:
 
diff --git a/boards/gd/gd32f450z_eval/gd32f450z_eval.yaml b/boards/gd/gd32f450z_eval/gd32f450z_eval.yaml
index 3cc5f359495..b5d60e8d905 100644
--- a/boards/gd/gd32f450z_eval/gd32f450z_eval.yaml
+++ b/boards/gd/gd32f450z_eval/gd32f450z_eval.yaml
@@ -10,7 +10,6 @@ flash: 3072
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - dac
diff --git a/boards/gd/gd32f470i_eval/doc/index.rst b/boards/gd/gd32f470i_eval/doc/index.rst
index 1a8865f4d06..4c90c4d3f12 100644
--- a/boards/gd/gd32f470i_eval/doc/index.rst
+++ b/boards/gd/gd32f470i_eval/doc/index.rst
@@ -42,44 +42,7 @@ For more information about the GD32F470 SoC and GD32F470I-EVAL board:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - EXTI
-     - :kconfig:option:`CONFIG_GD32_EXTI`
-     - :dtcompatible:`gd,gd32-exti`
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`gd,gd32-gpio`
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v7m-nvic`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM`
-     - :dtcompatible:`gd,gd32-pwm`
-   * - SYSTICK
-     - N/A
-     - N/A
-   * - USART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`gd,gd32-usart`
-   * - DAC
-     - :kconfig:option:`CONFIG_DAC`
-     - :dtcompatible:`gd,gd32-dac`
-   * - I2C
-     - :kconfig:option:`CONFIG_I2C`
-     - :dtcompatible:`gd,gd32-i2c`
-   * - EEPROM
-     - :kconfig:option:`CONFIG_EEPROM`
-     - :dtcompatible:`atmel,at24`
-   * - SPI
-     - :kconfig:option:`CONFIG_SPI`
-     - :dtcompatible:`gd,gd32-spi`
+.. zephyr:board-supported-hw::
 
 Serial Port
 ===========
@@ -90,6 +53,8 @@ is USART0 with TX connected at PA9 and RX at PA10.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Before programming your board make sure to configure boot and serial jumpers
 as follows:
 
diff --git a/boards/gd/gd32f470i_eval/gd32f470i_eval.yaml b/boards/gd/gd32f470i_eval/gd32f470i_eval.yaml
index 9537f9aef30..ba01d162869 100644
--- a/boards/gd/gd32f470i_eval/gd32f470i_eval.yaml
+++ b/boards/gd/gd32f470i_eval/gd32f470i_eval.yaml
@@ -10,7 +10,6 @@ flash: 3072
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - dac
diff --git a/boards/gd/gd32l233r_eval/doc/index.rst b/boards/gd/gd32l233r_eval/doc/index.rst
index d6770856256..d025a2bf96e 100644
--- a/boards/gd/gd32l233r_eval/doc/index.rst
+++ b/boards/gd/gd32l233r_eval/doc/index.rst
@@ -34,35 +34,7 @@ For more information about the GD32L233 SoC and GD32L233R-EVAL board:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - EXTI
-     - :kconfig:option:`CONFIG_GD32_EXTI`
-     - :dtcompatible:`gd,gd32-exti`
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`gd,gd32-gpio`
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v8m-nvic`
-   * - SYSTICK
-     - N/A
-     - N/A
-   * - USART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`gd,gd32-usart`
-   * - PINMUX
-     - :kconfig:option:`CONFIG_PINCTRL`
-     - :dtcompatible:`gd,gd32-pinctrl-af`
-   * - ADC
-     - :kconfig:option:`CONFIG_ADC`
-     - :dtcompatible:`gd,gd32-adc`
+.. zephyr:board-supported-hw::
 
 Serial Port
 ===========
@@ -74,6 +46,8 @@ CH04E serial connector with Mini-USB.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Using J-Link
 =============
 
diff --git a/boards/gd/gd32l233r_eval/gd32l233r_eval.yaml b/boards/gd/gd32l233r_eval/gd32l233r_eval.yaml
index 04e38f9e46c..99aacaea2f5 100644
--- a/boards/gd/gd32l233r_eval/gd32l233r_eval.yaml
+++ b/boards/gd/gd32l233r_eval/gd32l233r_eval.yaml
@@ -10,5 +10,4 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 vendor: gd
diff --git a/boards/gd/gd32vf103c_starter/doc/index.rst b/boards/gd/gd32vf103c_starter/doc/index.rst
index 40b22fa18c5..a443dbde5f3 100644
--- a/boards/gd/gd32vf103c_starter/doc/index.rst
+++ b/boards/gd/gd32vf103c_starter/doc/index.rst
@@ -30,29 +30,7 @@ For more information about the GD32VF103 SoC and GD32VF103C-STARTER board:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`gd,gd32-gpio`
-   * - Machine timer
-     - :kconfig:option:`CONFIG_RISCV_MACHINE_TIMER`
-     - :dtcompatible:`riscv,machine-timer`
-   * - Nuclei ECLIC Interrupt Controller
-     - :kconfig:option:`CONFIG_NUCLEI_ECLIC`
-     - :dtcompatible:`nuclei,eclic`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM`
-     - :dtcompatible:`gd,gd32-pwm`
-   * - USART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`gd,gd32-usart`
+.. zephyr:board-supported-hw::
 
 Serial Port
 ===========
@@ -63,6 +41,8 @@ TX connected at PA9 and RX at PA10.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Before programming your board make sure to configure boot and serial jumpers
 as follows:
 
diff --git a/boards/gd/gd32vf103v_eval/doc/index.rst b/boards/gd/gd32vf103v_eval/doc/index.rst
index 773262c8eab..2f8dd496f61 100644
--- a/boards/gd/gd32vf103v_eval/doc/index.rst
+++ b/boards/gd/gd32vf103v_eval/doc/index.rst
@@ -37,32 +37,7 @@ For more information about the GD32VF103 SoC and GD32VF103V-EVAL board:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`gd,gd32-gpio`
-   * - Machine timer
-     - :kconfig:option:`CONFIG_RISCV_MACHINE_TIMER`
-     - :dtcompatible:`riscv,machine-timer`
-   * - Nuclei ECLIC Interrupt Controller
-     - :kconfig:option:`CONFIG_NUCLEI_ECLIC`
-     - :dtcompatible:`nuclei,eclic`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM`
-     - :dtcompatible:`gd,gd32-pwm`
-   * - USART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`gd,gd32-usart`
-   * - ADC
-     - :kconfig:option:`CONFIG_ADC`
-     - :dtcompatible:`gd,gd32-adc`
+.. zephyr:board-supported-hw::
 
 Serial Port
 ===========
@@ -73,6 +48,8 @@ is USART0 with TX connected at PA9 and RX at PA10.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Before programming your board make sure to configure boot and serial jumpers
 as follows:
 
diff --git a/boards/google/dragonclaw/doc/index.rst b/boards/google/dragonclaw/doc/index.rst
index 3f717a84341..ed5c8c11135 100644
--- a/boards/google/dragonclaw/doc/index.rst
+++ b/boards/google/dragonclaw/doc/index.rst
@@ -26,6 +26,8 @@ Peripherial Mapping
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build application as usual for the ``dragonclaw`` board, and flash
 using μServo or an external J-Link connected to J4. If μServo is used, please
 follow the `Chromium EC Flashing Documentation`_.
diff --git a/boards/google/dragonclaw/google_dragonclaw.yaml b/boards/google/dragonclaw/google_dragonclaw.yaml
index bf535af2c1e..584bcbd29a4 100644
--- a/boards/google/dragonclaw/google_dragonclaw.yaml
+++ b/boards/google/dragonclaw/google_dragonclaw.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 256
 flash: 1024
 vendor: google
diff --git a/boards/google/icetower/doc/index.rst b/boards/google/icetower/doc/index.rst
index 45ecb81be2d..7106102f718 100644
--- a/boards/google/icetower/doc/index.rst
+++ b/boards/google/icetower/doc/index.rst
@@ -26,6 +26,8 @@ Default Zephyr Peripheral Mapping:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build application as usual for the ``google_icetower`` board, and flash
 using μServo or an external J-Link connected to J4. If μServo is used, please
 follow the `Chromium EC Flashing Documentation`_.
diff --git a/boards/google/icetower/google_icetower.yaml b/boards/google/icetower/google_icetower.yaml
index c0b2473c100..b867fb64846 100644
--- a/boards/google/icetower/google_icetower.yaml
+++ b/boards/google/icetower/google_icetower.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 1024
 flash: 2048
 vendor: google
diff --git a/boards/google/quincy/Kconfig.google_quincy b/boards/google/quincy/Kconfig.google_quincy
new file mode 100644
index 00000000000..5bf9347a860
--- /dev/null
+++ b/boards/google/quincy/Kconfig.google_quincy
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_GOOGLE_QUINCY
+	select SOC_NPCX9MFP
diff --git a/boards/google/quincy/board.cmake b/boards/google/quincy/board.cmake
new file mode 100644
index 00000000000..85a7ea7b5f1
--- /dev/null
+++ b/boards/google/quincy/board.cmake
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=Cortex-M4" "--speed=4000")
+board_runner_args(openocd --cmd-load "npcx_write_image")
+board_runner_args(openocd --cmd-verify "npcx_verify_image")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/google/quincy/board.yml b/boards/google/quincy/board.yml
new file mode 100644
index 00000000000..e0774ca8b86
--- /dev/null
+++ b/boards/google/quincy/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: google_quincy
+  full_name: Quincy
+  vendor: google
+  socs:
+    - name: npcx9mfp
diff --git a/boards/google/quincy/doc/index.rst b/boards/google/quincy/doc/index.rst
new file mode 100644
index 00000000000..ec960007ec8
--- /dev/null
+++ b/boards/google/quincy/doc/index.rst
@@ -0,0 +1,49 @@
+.. zephyr:board:: google_quincy
+
+Overview
+********
+
+Google Quincy is a board created for fingerprint-related functionality
+development.
+
+The board has connectors for fingerprint sensors. A UART Console is exposed
+over μServo and USB connectors. The MCU can be flashed using μServo or SWD.
+
+Hardware
+********
+
+- NPCX99FPA0BX VFBGA144 package
+
+Peripheral Mapping
+===================
+
+- UART_1 (CONSOLE) TX/RX : GPIO65/GPIO64
+- UART_2 (PROG) TX/RX : GPIO86/GPIO75
+- SPI_0 (SHI) CS/CLK/MISO/MOSI : GPIO53/GPIO55/GPIO47/GPIO46
+- SPI_1 (SPIP) CS/CLK/MISO/MOSI : GPIOA6/GPIOA1/GPIO95/GPIOA3
+- SPI_2 (GP) CS/CLK/MISO/MOSI : GPIO30/GPIO25/GPIO24/GPIO31
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Build application as usual for the ``google_quincy`` board target, and flash
+using μServo or an external J-Link connected to J4. If μServo is used, please
+follow the `Chromium EC Flashing Documentation`_ and
+`Chromium Servo Micro Documentation`_.
+
+Debugging
+=========
+
+Use SWD with a J-Link.
+
+References
+**********
+
+.. target-notes::
+
+.. _Chromium EC Flashing Documentation:
+   https://chromium.googlesource.com/chromiumos/platform/ec#Flashing-via-the-servo-debug-board
+.. _Chromium Servo Micro Documentation:
+   https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/master/docs/servo_micro.md
diff --git a/boards/google/quincy/google_quincy.dts b/boards/google/quincy/google_quincy.dts
new file mode 100644
index 00000000000..7067cd4cf31
--- /dev/null
+++ b/boards/google/quincy/google_quincy.dts
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2024 Google LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nuvoton/npcx9mfp.dtsi>
+#include <nuvoton/npcx/npcx9/npcx9-pinctrl.dtsi>
+
+/ {
+	model = "Google Quincy development board";
+	compatible = "google,quincy-fpmcu";
+
+	chosen {
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,flash-controller = &int_flash;
+	};
+
+	aliases {
+		/* For watchdog sample */
+		watchdog0 = &twd0;
+	};
+};
+
+/* UART1: Servo UART (console) */
+&uart1 {
+	/* Use UART1_SL2 ie. PIN64.65 */
+	pinctrl-0 = <&uart1_2_sin_gp64
+		     &uart1_2_sout_gp65>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+/* UART2: AP UART (Host Commands and MKBP) */
+&uart2 {
+	pinctrl-0 = <&uart2_sin_gp75
+		     &uart2_sout_gp86>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+/* SHI0: communication with the AP */
+&shi0 {
+	status = "okay";
+	pinctrl-0 = <&shi_gp46_47_53_55>;
+	pinctrl-names = "default";
+};
+
+/* SPIP0: communication with the fingerprint sensor */
+&spip0 {
+	pinctrl-0 = <&spip_sclk_mosi_miso_gp95_gpa1_gpa3_gpa5_sl
+		     &spip_sclk_mosi_miso_gp95_gpa1_gpa3_gpa5_no_spip_inv>;
+	cs-gpios = <&gpioa 6 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/boards/google/quincy/google_quincy.yaml b/boards/google/quincy/google_quincy.yaml
new file mode 100644
index 00000000000..5ec04710dfe
--- /dev/null
+++ b/boards/google/quincy/google_quincy.yaml
@@ -0,0 +1,19 @@
+identifier: google_quincy
+name: Google Quincy Development Board
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 512
+flash: 1024
+vendor: google
+supported:
+  - clock
+  - gpio
+  - i2c
+  - pm
+  - pwm
+  - spi
+  - uart
+  - watchdog
diff --git a/boards/google/quincy/google_quincy_defconfig b/boards/google/quincy/google_quincy_defconfig
new file mode 100644
index 00000000000..0b5fcc5649f
--- /dev/null
+++ b/boards/google/quincy/google_quincy_defconfig
@@ -0,0 +1,23 @@
+# Copyright (c) 2024 Google Inc
+# SPDX-License-Identifier: Apache-2.0
+
+# General Kernel Options
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=15000000
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+
+# Clock Controller
+CONFIG_CLOCK_CONTROL=y
+
+# Enable MPU and HW stack protection
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
diff --git a/boards/google/twinkie_v2/doc/index.rst b/boards/google/twinkie_v2/doc/index.rst
index 3ba2f42e267..89450cf04ff 100644
--- a/boards/google/twinkie_v2/doc/index.rst
+++ b/boards/google/twinkie_v2/doc/index.rst
@@ -14,22 +14,7 @@ Hardware
 Supported Features
 ==================
 
-The following features are supported:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/google/twinkie_v2/google_twinkie_v2_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -45,6 +30,8 @@ Default Zephyr Peripheral Mapping:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build application as usual for the ``google_twinkie_v2`` board, and flash
 using dfu-util or J-Link.
 
diff --git a/boards/google/twinkie_v2/google_twinkie_v2.yaml b/boards/google/twinkie_v2/google_twinkie_v2.yaml
index bc9028b4e9a..5509e5f4079 100644
--- a/boards/google/twinkie_v2/google_twinkie_v2.yaml
+++ b/boards/google/twinkie_v2/google_twinkie_v2.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 144
 flash: 512
 testing:
diff --git a/boards/hardkernel/odroid_go/doc/index.rst b/boards/hardkernel/odroid_go/doc/index.rst
index 0963435fa3d..3c14c9c23b0 100644
--- a/boards/hardkernel/odroid_go/doc/index.rst
+++ b/boards/hardkernel/odroid_go/doc/index.rst
@@ -51,23 +51,7 @@ External Connector
 Supported Features
 ==================
 
-The Zephyr odroid_go board configuration supports the following hardware
-features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| I2C        | on-chip    | i2c                                 |
-+------------+------------+-------------------------------------+
-| SPI        | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-
+.. zephyr:board-supported-hw::
 
 System requirements
 *******************
@@ -89,6 +73,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/hardkernel/odroid_go/odroid_go_appcpu_defconfig b/boards/hardkernel/odroid_go/odroid_go_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/hardkernel/odroid_go/odroid_go_appcpu_defconfig
+++ b/boards/hardkernel/odroid_go/odroid_go_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/hardkernel/odroid_go/odroid_go_procpu.dts b/boards/hardkernel/odroid_go/odroid_go_procpu.dts
index 386627ff358..38510fbeadf 100644
--- a/boards/hardkernel/odroid_go/odroid_go_procpu.dts
+++ b/boards/hardkernel/odroid_go/odroid_go_procpu.dts
@@ -174,3 +174,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/hardkernel/odroid_go/odroid_go_procpu_defconfig b/boards/hardkernel/odroid_go/odroid_go_procpu_defconfig
index 1a0608e1def..c59a51342aa 100644
--- a/boards/hardkernel/odroid_go/odroid_go_procpu_defconfig
+++ b/boards/hardkernel/odroid_go/odroid_go_procpu_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst b/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst
index c4987a76b8f..abe91f4ca90 100644
--- a/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst
+++ b/boards/heltec/heltec_wifi_lora32_v2/doc/index.rst
@@ -39,6 +39,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_appcpu_defconfig b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_appcpu_defconfig
+++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts
index c641e773e07..426a7a13378 100644
--- a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts
+++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu.dts
@@ -115,5 +115,9 @@
 	status = "okay";
 };
 
+&wifi {
+	status = "okay";
+};
+
 /* Required by the ssd1306_128x64 shield which enables the OLED display */
 arduino_i2c: &i2c0 {};
diff --git a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu_defconfig b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu_defconfig
index f029cac9e9e..e192c240251 100644
--- a/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu_defconfig
+++ b/boards/heltec/heltec_wifi_lora32_v2/heltec_wifi_lora32_v2_procpu_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst b/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst
index 4f6430965e5..431f83d41eb 100644
--- a/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst
+++ b/boards/heltec/heltec_wireless_stick_lite_v3/doc/index.rst
@@ -20,13 +20,8 @@ The main hardware features are:
 
 Supported Features
 ==================
-- LoRa via SPI
-- UART0 (USB Serial via CP2102)
-- UART1
-- I2C
-- CAN (optional, need to enable)
-- PWM LED
-- User Switch / Button
+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -146,6 +141,8 @@ below to retrieve those files.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_appcpu_defconfig b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_appcpu_defconfig
+++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts
index 9e02e3db483..631d873cd10 100644
--- a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts
+++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu.dts
@@ -176,3 +176,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu_defconfig b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu_defconfig
index 2dfe1853d5c..c698c607636 100644
--- a/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu_defconfig
+++ b/boards/heltec/heltec_wireless_stick_lite_v3/heltec_wireless_stick_lite_v3_procpu_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CLOCK_CONTROL=y
 CONFIG_CONSOLE=y
 CONFIG_GPIO=y
diff --git a/boards/holyiot/yj16019/doc/index.rst b/boards/holyiot/yj16019/doc/index.rst
index 86575a0838b..867fbdf88a6 100644
--- a/boards/holyiot/yj16019/doc/index.rst
+++ b/boards/holyiot/yj16019/doc/index.rst
@@ -30,34 +30,7 @@ The nRF52832 of the Holyiot YJ-16019 is clocked by an external crystal with a fr
 Supported Features
 ==================
 
-The holyiot_yj16019 board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -71,6 +44,8 @@ LED and push button
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``holyiot_yj16019`` board configuration can be
 built and flashed in the usual way (see :ref:`build_an_application`
 and :ref:`application_run` for more details); however, an external
diff --git a/boards/holyiot/yj16019/holyiot_yj16019.yaml b/boards/holyiot/yj16019/holyiot_yj16019.yaml
index 573af0e86d3..f60d7b319a3 100644
--- a/boards/holyiot/yj16019/holyiot_yj16019.yaml
+++ b/boards/holyiot/yj16019/holyiot_yj16019.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - ble
   - pwm
diff --git a/boards/iar/index.rst b/boards/iar/index.rst
new file mode 100644
index 00000000000..3cc895fdb55
--- /dev/null
+++ b/boards/iar/index.rst
@@ -0,0 +1,10 @@
+.. _boards-iar:
+
+IAR
+###
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*
diff --git a/boards/iar/stm32f429ii_aca/Kconfig.stm32f429ii_aca b/boards/iar/stm32f429ii_aca/Kconfig.stm32f429ii_aca
new file mode 100644
index 00000000000..f04f3979a7e
--- /dev/null
+++ b/boards/iar/stm32f429ii_aca/Kconfig.stm32f429ii_aca
@@ -0,0 +1,6 @@
+# Copyright (c) 2016 Linaro Limited.
+# Copyright (c) 2025 IAR Systems.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_STM32F429II_ACA
+	select SOC_STM32F429XX
diff --git a/boards/iar/stm32f429ii_aca/board.cmake b/boards/iar/stm32f429ii_aca/board.cmake
new file mode 100644
index 00000000000..1d0b4be283d
--- /dev/null
+++ b/boards/iar/stm32f429ii_aca/board.cmake
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=STM32F429II" "--speed=4000")
+board_runner_args(pyocd "--target=stm32f429xi")
+board_runner_args(pyocd "--flash-opt=-O reset_type=hw")
+board_runner_args(pyocd "--flash-opt=-O connect_mode=under-reset")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
diff --git a/boards/iar/stm32f429ii_aca/board.yml b/boards/iar/stm32f429ii_aca/board.yml
new file mode 100644
index 00000000000..67419bb5068
--- /dev/null
+++ b/boards/iar/stm32f429ii_aca/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: stm32f429ii_aca
+  full_name: STM32F429II-ACA
+  vendor: iar
+  socs:
+    - name: stm32f429xx
diff --git a/boards/iar/stm32f429ii_aca/doc/img/stm32f429ii_aca.webp b/boards/iar/stm32f429ii_aca/doc/img/stm32f429ii_aca.webp
new file mode 100644
index 00000000000..1ce5bb76c16
Binary files /dev/null and b/boards/iar/stm32f429ii_aca/doc/img/stm32f429ii_aca.webp differ
diff --git a/boards/iar/stm32f429ii_aca/doc/index.rst b/boards/iar/stm32f429ii_aca/doc/index.rst
new file mode 100644
index 00000000000..cc95c94a0ff
--- /dev/null
+++ b/boards/iar/stm32f429ii_aca/doc/index.rst
@@ -0,0 +1,138 @@
+.. zephyr:board:: stm32f429ii_aca
+
+Overview
+********
+
+The IAR STM32F429II-ACA evaluation board features an ARM Cortex-M4 based STM32F429II MCU.
+Here are some highlights of the STM32F429II-ACA board:
+
+- STM32 microcontroller in LQFP144 package
+- JTAG/SWD debugger/programmer interface
+- Flexible board power supply
+
+  - JTAG/SWD connector
+  - USB HS connector
+
+- 3x user push-buttons and 1x RESET push-button
+- Open-close switch and on-auto-off switch
+- 2x capacitive touch panels
+- USB OTG with mini-USB connector
+- Small speaker
+- Trimmer potentiometer
+- Nine LEDs
+
+  - 1x power LED
+  - 3x car traffic light LEDs
+  - 2x pedestrian traffic light LEDs
+  - 1x car interior light LED
+  - 2x user LEDs
+
+Schematics for the board can be found `here <stm32f429ii-aca-schematics_>`_
+
+Hardware
+********
+
+The STM32F429II-ACA evaluation board provides the following hardware components:
+
+- STM32F429II in LQFP144 package
+- ARM |reg| 32-bit Cortex |reg| -M4 CPU with FPU
+- 180 MHz max CPU frequency
+- VDD from 1.8 V to 3.6 V
+- 2 MB Internal Flash
+- 4 Mbit External Flash
+- 256+4 KB SRAM including 64-KB of core coupled memory
+- GPIO with external interrupt capability
+- 12-bit ADC
+- 12-bit DAC
+- RTC
+- General Purpose Timers
+- I2C
+- SPI
+- USB 2.0 OTG HS/FS with dedicated DMA, on-chip full-speed PHY and ULPI
+- CRC calculation unit
+- True random number generator
+- DMA Controller
+
+More information about STM32F429II can be found here:
+
+- `STM32F429II on www.st.com`_
+- `STM32F429 Reference Manual`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+- I2C_1_SCL : PB8
+- I2C_1_SDA : PB7
+- I2C_2_SCL : PH4
+- I2C_2_SDA : PH5
+- SPI_5_NSS : PF6
+- SPI_5_SCK : PF7
+- SPI_5_MISO : PF8
+- SPI_5_MOSI : PF9
+- OTG_HS_ID : PB12
+- OTG_HS_DM : PB14
+- OTG_HS_DP : PB15
+
+Serial Port
+===========
+
+By default, the STM32F429II-ACA evaluation board has no physical serial port available.
+The board has up to 8 UARTs, of which none are used.
+
+USB Port
+========
+
+The STM32F429II-ACA evaluation board has a USB HS capable Mini-USB port. It is connected to the on-chip
+OTG_HS peripheral.
+
+Programming and Debugging
+*************************
+
+Applications for the ``stm32f429ii_aca`` board configuration can be built
+and flashed in the usual way (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Flashing
+========
+
+In order to flash this board using west, an external debug probe such as a Segger J-Link
+has to be connected through the JTAG/SWD connector on the board.
+By default, the board is set to be flashed using the jlink runner.
+Alternatively, openocd, or pyocd can also be used as runners to flash the board using
+the ``--runner`` (or ``-r``) option:
+
+.. code-block:: console
+
+   $ west flash --runner openocd
+   $ west flash --runner pyocd
+
+First, connect the STM32F429II-ACA evaluation board to your host computer using
+your debug probe through the JTAG/SWD connector to prepare it for flashing.
+Then build and flash your application.
+
+Here is an example for the :zephyr:code-sample:`blinky` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: stm32f429ii_aca
+   :goals: build flash
+
+LED0 should then begin to blink continuously with a 1-second delay.
+
+References
+**********
+
+.. target-notes::
+
+.. _stm32f429ii-aca-schematics:
+   https://iar.my.salesforce.com/sfc/p/#30000000YATY/a/Qx000000vZVh/EzlIqYKIBVXN8PN4Q8MgtowSZrR_vZarwLiNJXw7UJw
+
+.. _STM32F429II on www.st.com:
+   https://www.st.com/en/microcontrollers-microprocessors/stm32f429ii.html
+
+.. _STM32F429 Reference Manual:
+   https://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf
diff --git a/boards/iar/stm32f429ii_aca/stm32f429ii_aca.dts b/boards/iar/stm32f429ii_aca/stm32f429ii_aca.dts
new file mode 100644
index 00000000000..ff7635b676d
--- /dev/null
+++ b/boards/iar/stm32f429ii_aca/stm32f429ii_aca.dts
@@ -0,0 +1,277 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ * Copyright (c) 2024 STMicroelectronics
+ * Copyright (c) 2025 IAR Systems
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/f4/stm32f429Xi.dtsi>
+#include <st/f4/stm32f429iitx-pinctrl.dtsi>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "IAR STM32F429II-ACA board";
+	compatible = "iar,stm32f429ii-aca";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,ccm = &ccm0;
+	};
+
+	sdram2: sdram@d0000000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		device_type = "memory";
+		reg = <0xd0000000 DT_SIZE_M(8)>;
+		zephyr,memory-region = "SDRAM2";
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		traffic_red_led: led_0 {
+			gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
+			label = "LED0";
+		};
+
+		traffic_yellow_led: led_1 {
+			gpios = <&gpiod 4 GPIO_ACTIVE_LOW>;
+			label = "LED1";
+		};
+
+		traffic_green_led: led_2 {
+			gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
+			label = "LED2";
+		};
+
+		car_led: led_3 {
+			gpios = <&gpiod 6 GPIO_ACTIVE_LOW>;
+			label = "LED3";
+		};
+
+		pedestrian_red_led: led_4 {
+			gpios = <&gpiod 7 GPIO_ACTIVE_LOW>;
+			label = "LED4";
+		};
+
+		pedestrian_green_led: led_5 {
+			gpios = <&gpiod 11 GPIO_ACTIVE_LOW>;
+			label = "LED5";
+		};
+
+		user_led_1: led_6 {
+			gpios = <&gpiod 12 GPIO_ACTIVE_LOW>;
+			label = "LED6";
+		};
+
+		user_led_2: led_7 {
+			gpios = <&gpiod 13 GPIO_ACTIVE_LOW>;
+			label = "LED7";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		button0: button_0 {
+			label = "BUT0";
+			gpios = <&gpioa 0 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		button1: button_1 {
+			label = "BUT1";
+			gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+
+		button2: button_2 {
+			label = "BUT2";
+			gpios = <&gpiog 9 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_2>;
+		};
+
+		open_close_switch: switch_0 {
+			label = "OPEN/CLOSE SWITCH";
+			gpios = <&gpioi 11 GPIO_ACTIVE_HIGH>;
+			zephyr,code = <INPUT_KEY_3>;
+		};
+
+		interior_light_switch_on: switch_1 {
+			label = "ON";
+			gpios = <&gpioi 10 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_4>;
+		};
+
+		interior_light_switch_auto: switch_2 {
+			label = "AUTO";
+			gpios = <&gpioi 9 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_5>;
+		};
+
+		interior_light_switch_off: switch_3 {
+			label = "OFF";
+			gpios = <&gpioi 8 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_6>;
+		};
+
+		cap_button0: cap_button_0 {
+			label = "CAP_BUT0";
+			gpios = <&gpioh 6 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_7>;
+		};
+
+		cap_button1: cap_button_1 {
+			label = "CAP_BUT1";
+			gpios = <&gpioh 7 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_8>;
+		};
+	};
+
+	aliases {
+		led0 = &traffic_red_led;
+		led1 = &traffic_yellow_led;
+		led2 = &traffic_green_led;
+		led3 = &car_led;
+		led4 = &pedestrian_red_led;
+		led5 = &pedestrian_green_led;
+		led6 = &user_led_1;
+		led7 = &user_led_2;
+		sw0 = &button0;
+		sw1 = &button1;
+		sw2 = &button2;
+		sw3 = &open_close_switch;
+		sw4 = &interior_light_switch_on;
+		sw5 = &interior_light_switch_auto;
+		sw6 = &interior_light_switch_off;
+		sw7 = &cap_button0;
+		sw8 = &cap_button1;
+	};
+};
+
+&clk_lsi {
+	status = "okay";
+};
+
+&clk_hse {
+	clock-frequency = <DT_FREQ_M(8)>;
+	status = "okay";
+};
+
+&pll {
+	div-m = <8>;
+	mul-n = <336>;
+	div-p = <2>;
+	div-q = <7>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(168)>;
+	ahb-prescaler = <1>;
+	apb1-prescaler = <4>;
+	apb2-prescaler = <2>;
+};
+
+&rtc {
+	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
+		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb7>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_scl_ph4 &i2c2_sda_ph5>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+
+&spi5 {
+	pinctrl-0 = <&spi5_nss_pf6 &spi5_sck_pf7
+		     &spi5_miso_pf8 &spi5_mosi_pf9>;
+	pinctrl-names = "default";
+	status = "okay";
+	cs-gpios = <&gpioc 2 GPIO_ACTIVE_LOW>;
+};
+
+&fmc {
+	status = "okay";
+	pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1
+		     &fmc_sdclk_pg8 &fmc_sdnwe_pc0 &fmc_sdcke0_pc3
+		     &fmc_sdne0_pc2 &fmc_sdnras_pf11 &fmc_sdncas_pg15
+		     &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3
+		     &fmc_a4_pf4 &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13
+		     &fmc_a8_pf14 &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1
+		     &fmc_a12_pg2 &fmc_a13_pg3 &fmc_a14_pg4 &fmc_a15_pg5
+		     &fmc_d0_pd14 &fmc_d1_pd15 &fmc_d2_pd0 &fmc_d3_pd1
+		     &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9 &fmc_d7_pe10
+		     &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13 &fmc_d11_pe14
+		     &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9 &fmc_d15_pd10>;
+	pinctrl-names = "default";
+
+	sdram {
+		status = "okay";
+
+		power-up-delay = <100>;
+		num-auto-refresh = <1>;
+		mode-register = <0>;
+		refresh-rate = <1386>;
+
+		bank@1 {
+			reg = <1>;
+
+			st,sdram-control = <STM32_FMC_SDRAM_NC_8
+					    STM32_FMC_SDRAM_NR_12
+					    STM32_FMC_SDRAM_MWID_16
+					    STM32_FMC_SDRAM_NB_4
+					    STM32_FMC_SDRAM_CAS_2
+					    STM32_FMC_SDRAM_SDCLK_PERIOD_3
+					    STM32_FMC_SDRAM_RBURST_DISABLE
+					    STM32_FMC_SDRAM_RPIPE_1>;
+			st,sdram-timing = <2 7 4 7 2 2 2>;
+		};
+	};
+};
+
+&adc2 {
+	compatible = "st,stm32f4-adc", "st,stm32-adc";
+	pinctrl-0 = <&adc2_in6_pa6>;
+	pinctrl-names = "default";
+	st,adc-prescaler = <2>;
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@6 {
+		reg = <6>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
+
+&dac1 {
+	pinctrl-0 = <&dac_out2_pa5>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+zephyr_udc0: &usbotg_hs {
+	pinctrl-0 = <&usb_otg_hs_dm_pb14 &usb_otg_hs_dp_pb15 &usb_otg_hs_id_pb12>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/boards/iar/stm32f429ii_aca/stm32f429ii_aca.yaml b/boards/iar/stm32f429ii_aca/stm32f429ii_aca.yaml
new file mode 100644
index 00000000000..b430c8f5d9b
--- /dev/null
+++ b/boards/iar/stm32f429ii_aca/stm32f429ii_aca.yaml
@@ -0,0 +1,15 @@
+identifier: stm32f429ii_aca
+name: IAR STM32F429II ACA
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - iar
+ram: 192
+flash: 2048
+supported:
+  - counter
+  - i2c
+  - spi
+vendor: iar
diff --git a/boards/iar/stm32f429ii_aca/stm32f429ii_aca_defconfig b/boards/iar/stm32f429ii_aca/stm32f429ii_aca_defconfig
new file mode 100644
index 00000000000..75a3154c8fb
--- /dev/null
+++ b/boards/iar/stm32f429ii_aca/stm32f429ii_aca_defconfig
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable GPIO
+CONFIG_GPIO=y
diff --git a/boards/iar/stm32f429ii_aca/support/openocd.cfg b/boards/iar/stm32f429ii_aca/support/openocd.cfg
new file mode 100644
index 00000000000..fa1360a7143
--- /dev/null
+++ b/boards/iar/stm32f429ii_aca/support/openocd.cfg
@@ -0,0 +1,17 @@
+source [find interface/cmsis-dap.cfg]
+
+set CHIPNAME STM32F429IITx
+set BOARDNAME STM32F429II-ACA
+
+source [find target/stm32f4x.cfg]
+
+$_TARGETNAME configure -event gdb-attach {
+	echo "Debugger attaching: halting execution"
+	reset halt
+	gdb_breakpoint_override hard
+}
+
+$_TARGETNAME configure -event gdb-detach {
+	echo "Debugger detaching: resuming execution"
+	resume
+}
diff --git a/boards/index.rst b/boards/index.rst
index 0643a355e59..9b83276abbf 100644
--- a/boards/index.rst
+++ b/boards/index.rst
@@ -24,6 +24,10 @@ this page <boards-shields>`.
      single field, selecting multiple options (such as two architectures) will show boards matching
      **either** option.
 
+   * The list of supported hardware features for each board is automatically generated using
+     information from the Devicetree. It may not be reflecting the full list of supported features
+     since some of them may not be enabled by default.
+
    * Can't find your exact board? Don't worry! If a similar board with the same or a closely related
      MCU exists, you can use it as a :ref:`starting point <create-your-board-directory>` for adding
      support for your own board.
diff --git a/boards/infineon/cy8ckit_062s2_ai/doc/index.rst b/boards/infineon/cy8ckit_062s2_ai/doc/index.rst
index 8395bcd98ce..a7c2ad2f4f6 100644
--- a/boards/infineon/cy8ckit_062s2_ai/doc/index.rst
+++ b/boards/infineon/cy8ckit_062s2_ai/doc/index.rst
@@ -28,31 +28,7 @@ For more information about the CY8C624ABZI-S2D44 MCU SoC and CY8CKIT-062S2-AI bo
 Supported Features
 ==================
 
-The ``cy8ckit_062s2_ai/cy8c624abzi_s2d44`` board target supports the following hardware features:
-
-+-----------+------------+-----------------------+
-| Interface | Controller | Driver/Component      |
-+===========+============+=======================+
-| NVIC      | on-chip    | nested vectored       |
-|           |            | interrupt controller  |
-+-----------+------------+-----------------------+
-| SYSTICK   | on-chip    | system clock          |
-+-----------+------------+-----------------------+
-| GPIO      | on-chip    | GPIO                  |
-+-----------+------------+-----------------------+
-| PINCTRL   | on-chip    | pin control           |
-+-----------+------------+-----------------------+
-| UART      | on-chip    | serial port-polling;  |
-|           |            | serial port-interrupt |
-+-----------+------------+-----------------------+
-| WATCHDOG  | on-chip    | watchdog              |
-+-----------+------------+-----------------------+
-
-
-The default configuration can be found in the defconfig and dts files:
-
-  - :zephyr_file:`boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai_defconfig`
-  - :zephyr_file:`boards/infineon/cy8ckit_062s2_ai/cy8ckit_062s2_ai.dts`
+.. zephyr:board-supported-hw::
 
 System Clock
 ============
@@ -87,6 +63,8 @@ Here is an example for building the :zephyr:code-sample:`blinky` sample applicat
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The CY8CKIT-062S2-AI board includes an onboard programmer/debugger (`KitProg3`_)
 to provide debugging, flash programming, and serial communication over USB.
 Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version,
diff --git a/boards/infineon/cy8ckit_062s4/cy8ckit_062s4_defconfig b/boards/infineon/cy8ckit_062s4/cy8ckit_062s4_defconfig
index d0909391c45..80182936a00 100644
--- a/boards/infineon/cy8ckit_062s4/cy8ckit_062s4_defconfig
+++ b/boards/infineon/cy8ckit_062s4/cy8ckit_062s4_defconfig
@@ -5,7 +5,6 @@ CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
 CONFIG_SERIAL=y
 
-CONFIG_BUILD_OUTPUT_HEX=y
 CONFIG_CORTEX_M_SYSTICK=y
 CONFIG_XIP=y
 
diff --git a/boards/infineon/cy8ckit_062s4/doc/index.rst b/boards/infineon/cy8ckit_062s4/doc/index.rst
index b5e3e39cc1d..8a1efe9fe28 100644
--- a/boards/infineon/cy8ckit_062s4/doc/index.rst
+++ b/boards/infineon/cy8ckit_062s4/doc/index.rst
@@ -24,25 +24,7 @@ Hardware
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-+-----------+------------+-----------------------+
-| Interface | Controller | Driver/Component      |
-+===========+============+=======================+
-| NVIC      | on-chip    | nested vectored       |
-|           |            | interrupt controller  |
-+-----------+------------+-----------------------+
-| SYSTICK   | on-chip    | system clock          |
-+-----------+------------+-----------------------+
-| PINCTRL   | on-chip    | pin control           |
-+-----------+------------+-----------------------+
-| UART      | on-chip    | serial port-polling;  |
-+-----------+------------+-----------------------+
-
-
-The default configuration can be found in the Kconfig
-
-:zephyr_file:`boards/infineon/cy8ckit_062s4/cy8ckit_062s4_defconfig`
+.. zephyr:board-supported-hw::
 
 Clock Configuration
 ===================
@@ -77,6 +59,8 @@ Here is an example for building the :zephyr:code-sample:`blinky` sample applicat
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The CY8CKIT-062S4 includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed.
 
 Infineon OpenOCD Installation
diff --git a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml
index 5eb55d4de6d..7d4185c860e 100644
--- a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml
+++ b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w.yaml
@@ -24,5 +24,6 @@ supported:
   - i2c
   - thermistor
   - uart
+  - dma
   - timer
 vendor: infineon
diff --git a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig
index 221643eca27..54183d73c1c 100644
--- a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig
+++ b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig
@@ -5,8 +5,6 @@
 
 # General configuration
 CONFIG_CORTEX_M_SYSTICK=y
-CONFIG_BUILD_OUTPUT_HEX=y
-
 CONFIG_ARM_MPU=y
 CONFIG_HW_STACK_PROTECTION=y
 
@@ -22,6 +20,3 @@ CONFIG_GPIO=y
 
 # Enable clock controller
 CONFIG_CLOCK_CONTROL=y
-
-# Main Stack Size
-CONFIG_MAIN_STACK_SIZE=2048
diff --git a/boards/infineon/cy8cproto_062_4343w/doc/index.rst b/boards/infineon/cy8cproto_062_4343w/doc/index.rst
index f04c28e5d00..c4696ca8d86 100644
--- a/boards/infineon/cy8cproto_062_4343w/doc/index.rst
+++ b/boards/infineon/cy8cproto_062_4343w/doc/index.rst
@@ -49,27 +49,7 @@ Kit Contents:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-+-----------+------------+-----------------------+
-| Interface | Controller | Driver/Component      |
-+===========+============+=======================+
-| NVIC      | on-chip    | nested vectored       |
-|           |            | interrupt controller  |
-+-----------+------------+-----------------------+
-| SYSTICK   | on-chip    | system clock          |
-+-----------+------------+-----------------------+
-| GPIO      | on-chip    | GPIO                  |
-+-----------+------------+-----------------------+
-| UART      | on-chip    | serial port-polling;  |
-|           |            | serial port-interrupt |
-+-----------+------------+-----------------------+
-
-
-The default configuration can be found in the Kconfig
-
-:zephyr_file:`boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig`
-
+.. zephyr:board-supported-hw::
 
 System Clock
 ============
@@ -105,6 +85,8 @@ Here is an example for building the :zephyr:code-sample:`blinky` sample applicat
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The CY8CPROTO-062-4343W includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed.
 
 Infineon OpenOCD Installation
diff --git a/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig b/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig
index 7d0d29ea39c..51c814073a3 100644
--- a/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig
+++ b/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig
@@ -6,8 +6,6 @@
 
 # General configuration
 CONFIG_CORTEX_M_SYSTICK=y
-CONFIG_BUILD_OUTPUT_HEX=y
-
 CONFIG_ARM_MPU=y
 CONFIG_HW_STACK_PROTECTION=y
 
@@ -24,8 +22,5 @@ CONFIG_GPIO=y
 # Enable clock controller
 CONFIG_CLOCK_CONTROL=y
 
-# Main Stack Size
-CONFIG_MAIN_STACK_SIZE=2048
-
 # Add catcm0p sleep images for CM0 Devices
 CONFIG_SOC_PSOC6_CM0P_IMAGE_SLEEP=y
diff --git a/boards/infineon/cy8cproto_063_ble/doc/index.rst b/boards/infineon/cy8cproto_063_ble/doc/index.rst
index 90623b80382..f3c83260513 100644
--- a/boards/infineon/cy8cproto_063_ble/doc/index.rst
+++ b/boards/infineon/cy8cproto_063_ble/doc/index.rst
@@ -22,38 +22,7 @@ For more information about the PSOC 63 BLE MCU SoC and CY8CPROTO-063-BLE board:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-+-----------+------------+-----------------------+
-| Interface | Controller | Driver/Component      |
-+===========+============+=======================+
-| NVIC      | on-chip    | nested vectored       |
-|           |            | interrupt controller  |
-+-----------+------------+-----------------------+
-| SYSTICK   | on-chip    | system clock          |
-+-----------+------------+-----------------------+
-| GPIO      | on-chip    | GPIO                  |
-+-----------+------------+-----------------------+
-| PINCTRL   | on-chip    | pin control           |
-+-----------+------------+-----------------------+
-| SPI       | on-chip    | SPI                   |
-+-----------+------------+-----------------------+
-| UART      | on-chip    | serial port-polling;  |
-|           |            | serial port-interrupt |
-+-----------+------------+-----------------------+
-| I2C       | on-chip    | I2C                   |
-+-----------+------------+-----------------------+
-| PWM       | on-chip    | PWM                   |
-+-----------+------------+-----------------------+
-| Counter   | on-chip    | Counter               |
-+-----------+------------+-----------------------+
-| Bluetooth | on-chip    | Bluetooth             |
-+-----------+------------+-----------------------+
-
-
-The default configuration can be found in the Kconfig
-
-:zephyr_file:`boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig`
+.. zephyr:board-supported-hw::
 
 System Clock
 ============
@@ -89,6 +58,8 @@ Here is an example for building the :zephyr:code-sample:`blinky` sample applicat
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The CY8CPROTO-063-BLE includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed.
 
 Infineon OpenOCD Installation
diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts
index 927b1f865f4..92a748d2ee1 100644
--- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts
+++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.dts
@@ -38,6 +38,16 @@ uart2: &scb2 {
 
 	pinctrl-0 = <&p3_3_scb2_uart_tx &p3_2_scb2_uart_rx &p3_1_scb2_uart_rts &p3_0_scb2_uart_cts>;
 	pinctrl-names = "default";
+
+	dmas = <&dma0 8>, <&dma0 9>;
+	dma-names = "tx", "rx";
+};
+
+&dma0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "infineon,cat1-dma";
+	status = "okay";
 };
 
 &fll0 {
diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml
index 9d83de725c0..3244d698080 100644
--- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml
+++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02.yaml
@@ -17,6 +17,7 @@ supported:
   - uart
   - clock_control
   - bluetooth
+  - adc
   - watchdog
   - spi
   - i2c
diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig
index e50b5462bab..c59deaae71c 100644
--- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig
+++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig
@@ -4,9 +4,6 @@
 #
 
 # General configuration
-CONFIG_BUILD_OUTPUT_HEX=y
-CONFIG_BUILD_OUTPUT_BIN=y
-
 CONFIG_ARM_MPU=y
 CONFIG_HW_STACK_PROTECTION=y
 
@@ -23,8 +20,5 @@ CONFIG_GPIO=y
 # Enable clock controller
 CONFIG_CLOCK_CONTROL=y
 
-# Main Stack Size
-CONFIG_MAIN_STACK_SIZE=2048
-
 # Enable code/data relocation to move SMIF driver into RAM
 CONFIG_CODE_DATA_RELOCATION=y
diff --git a/boards/infineon/cyw920829m2evk_02/doc/index.rst b/boards/infineon/cyw920829m2evk_02/doc/index.rst
index d4c5193c382..0dd56962c15 100644
--- a/boards/infineon/cyw920829m2evk_02/doc/index.rst
+++ b/boards/infineon/cyw920829m2evk_02/doc/index.rst
@@ -36,26 +36,7 @@ Kit Contents:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-+-----------+------------+-----------------------+
-| Interface | Controller | Driver/Component      |
-+===========+============+=======================+
-| NVIC      | on-chip    | nested vectored       |
-|           |            | interrupt controller  |
-+-----------+------------+-----------------------+
-| SYSTICK   | on-chip    | system clock          |
-+-----------+------------+-----------------------+
-| GPIO      | on-chip    | GPIO                  |
-+-----------+------------+-----------------------+
-| UART      | on-chip    | serial port-polling;  |
-|           |            | serial port-interrupt |
-+-----------+------------+-----------------------+
-
-
-The default configuration can be found in the Kconfig
-
-:zephyr_file:`boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig`
+.. zephyr:board-supported-hw::
 
 System Clock
 ============
@@ -88,6 +69,8 @@ Here is an example for building the :zephyr:code-sample:`blinky` sample applicat
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The CYW920829M2EVK-02 includes an onboard programmer/debugger (`KitProg3`_) to provide debugging, flash programming, and serial communication over USB. Flash and debug commands use OpenOCD and require a custom Infineon OpenOCD version, that supports KitProg3, to be installed.
 
 The CYW920829M2EVK-02 supports RTT via a SEGGER JLink device, under the target name cyw20829_tm. This can be enabled for an application by building with the rtt-console snippet or setting the following config values: CONFIG_UART_CONSOLE=n, CONFIG_RTT_CONSOLE=y, and CONFIG_USE_SEGGER_RTT=y.
diff --git a/boards/infineon/xmc45_relax_kit/doc/index.rst b/boards/infineon/xmc45_relax_kit/doc/index.rst
index bfad619aedc..5d89d5e2dbd 100644
--- a/boards/infineon/xmc45_relax_kit/doc/index.rst
+++ b/boards/infineon/xmc45_relax_kit/doc/index.rst
@@ -22,50 +22,9 @@ Details on the Relax Kit development board can be found in the `Relax Kit User M
 Supported Features
 ==================
 
-* The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 120MHz.
-
-The Relax Kit development board configuration supports the following hardware features:
-
-+-----------+------------+-----------------------+
-| Interface | Controller | Driver/Component      |
-+===========+============+=======================+
-| NVIC      | on-chip    | nested vectored       |
-|           |            | interrupt controller  |
-+-----------+------------+-----------------------+
-| SYSTICK   | on-chip    | system clock          |
-+-----------+------------+-----------------------+
-| UART      | on-chip    | serial port           |
-+-----------+------------+-----------------------+
-| SPI       | on-chip    | spi                   |
-+-----------+------------+-----------------------+
-| GPIO      | on-chip    | gpio                  |
-+-----------+------------+-----------------------+
-| FLASH     | on-chip    | flash                 |
-+-----------+------------+-----------------------+
-| ADC       | on-chip    | adc                   |
-+-----------+------------+-----------------------+
-| DMA       | on-chip    | dma                   |
-+-----------+------------+-----------------------+
-| PWM       | on-chip    | pwm                   |
-+-----------+------------+-----------------------+
-| WATCHDOG  | on-chip    | watchdog              |
-+-----------+------------+-----------------------+
-| MDIO      | on-chip    | mdio                  |
-+-----------+------------+-----------------------+
-| ETHERNET  | on-chip    | ethernet              |
-+-----------+------------+-----------------------+
-| PTP       | on-chip    | ethernet              |
-+-----------+------------+-----------------------+
-| RTC       | on-chip    | rtc                   |
-+-----------+------------+-----------------------+
-
-More details about the supported peripherals are available in `XMC4500 TRM`_
-
-The default configuration can be found in the Kconfig
-
-:zephyr_file:`boards/infineon/xmc45_relax_kit/xmc45_relax_kit_defconfig`
-
-Other hardware features are not currently supported by the Zephyr kernel.
+.. zephyr:board-supported-hw::
+
+The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 120MHz.
 
 Build hello world sample
 ************************
@@ -78,6 +37,9 @@ Here is an example for building the :zephyr:code-sample:`hello_world` sample app
 
 Programming and Debugging
 *************************
+
+.. zephyr:board-supported-runners::
+
 West Commands
 =============
 Here is an example for the :zephyr:code-sample:`hello_world` application.
diff --git a/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.yaml b/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.yaml
index fde3084c862..7733dd224e0 100644
--- a/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.yaml
+++ b/boards/infineon/xmc45_relax_kit/xmc45_relax_kit.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - dma
diff --git a/boards/infineon/xmc47_relax_kit/doc/index.rst b/boards/infineon/xmc47_relax_kit/doc/index.rst
index d5796afd7ea..09aa90843a0 100644
--- a/boards/infineon/xmc47_relax_kit/doc/index.rst
+++ b/boards/infineon/xmc47_relax_kit/doc/index.rst
@@ -27,47 +27,9 @@ Details on the Relax Kit development board can be found in the `Relax Kit User M
 Supported Features
 ==================
 
-The Relax Kit development board configuration supports the following hardware features:
-
-+-----------+------------+-----------------------+
-| Interface | Controller | Driver/Component      |
-+===========+============+=======================+
-| NVIC      | on-chip    | nested vectored       |
-|           |            | interrupt controller  |
-+-----------+------------+-----------------------+
-| SYSTICK   | on-chip    | system clock          |
-+-----------+------------+-----------------------+
-| UART      | on-chip    | serial port           |
-+-----------+------------+-----------------------+
-| SPI       | on-chip    | spi                   |
-+-----------+------------+-----------------------+
-| GPIO      | on-chip    | gpio                  |
-+-----------+------------+-----------------------+
-| FLASH     | on-chip    | flash                 |
-+-----------+------------+-----------------------+
-| ADC       | on-chip    | adc                   |
-+-----------+------------+-----------------------+
-| DMA       | on-chip    | dma                   |
-+-----------+------------+-----------------------+
-| PWM       | on-chip    | pwm                   |
-+-----------+------------+-----------------------+
-| WATCHDOG  | on-chip    | watchdog              |
-+-----------+------------+-----------------------+
-| MDIO      | on-chip    | mdio                  |
-+-----------+------------+-----------------------+
-| ETHERNET  | on-chip    | ethernet              |
-+-----------+------------+-----------------------+
-| PTP       | on-chip    | ethernet              |
-+-----------+------------+-----------------------+
-| RTC       | on-chip    | rtc                   |
-+-----------+------------+-----------------------+
+.. zephyr:board-supported-hw::
 
 More details about the supported peripherals are available in `XMC4700 TRM`_
-Other hardware features are not currently supported by the Zephyr kernel.
-
-The default configuration can be found in the Kconfig
-
-:zephyr_file:`boards/infineon/xmc47_relax_kit/xmc47_relax_kit_defconfig`
 
 Build hello world sample
 ************************
@@ -80,6 +42,9 @@ Here is an example for building the :zephyr:code-sample:`hello_world` sample app
 
 Programming and Debugging
 *************************
+
+.. zephyr:board-supported-runners::
+
 West Commands
 =============
 Here is an example for the :zephyr:code-sample:`hello_world` application.
diff --git a/boards/innblue/innblue21/doc/index.rst b/boards/innblue/innblue21/doc/index.rst
index bafb7d9911a..6a923bc969a 100644
--- a/boards/innblue/innblue21/doc/index.rst
+++ b/boards/innblue/innblue21/doc/index.rst
@@ -20,34 +20,7 @@ The following parts are built into the board:
 Supported Features
 ==================
 
-The innblue21 board configuration supports the following
-hardware (as of nRF9160) features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPU       | on-chip    | system protection    |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -77,6 +50,8 @@ Security components
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 innblue21 supports the Armv8m Security Extension, and by default boots
 in the Secure state.
 
diff --git a/boards/innblue/innblue21/innblue21_nrf9160.yaml b/boards/innblue/innblue21/innblue21_nrf9160.yaml
index 5722ebcd8c9..e19348bd0fd 100644
--- a/boards/innblue/innblue21/innblue21_nrf9160.yaml
+++ b/boards/innblue/innblue21/innblue21_nrf9160.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 64
 flash: 256
diff --git a/boards/innblue/innblue21/innblue21_nrf9160_ns.yaml b/boards/innblue/innblue21/innblue21_nrf9160_ns.yaml
index 17faee49190..dd1cef9b328 100644
--- a/boards/innblue/innblue21/innblue21_nrf9160_ns.yaml
+++ b/boards/innblue/innblue21/innblue21_nrf9160_ns.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 128
 flash: 192
diff --git a/boards/innblue/innblue22/doc/index.rst b/boards/innblue/innblue22/doc/index.rst
index 9e84c4691df..d87a7b222a8 100644
--- a/boards/innblue/innblue22/doc/index.rst
+++ b/boards/innblue/innblue22/doc/index.rst
@@ -20,34 +20,7 @@ The following parts are built into the board:
 Supported Features
 ==================
 
-The innblue22 board configuration supports the following
-hardware (as of nRF9160) features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPU       | on-chip    | system protection    |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -77,6 +50,8 @@ Security components
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 innblue22 supports the Armv8m Security Extension, and by default boots
 in the Secure state.
 
diff --git a/boards/innblue/innblue22/innblue22_nrf9160.yaml b/boards/innblue/innblue22/innblue22_nrf9160.yaml
index 9bad5763319..2fc3a3cb3d3 100644
--- a/boards/innblue/innblue22/innblue22_nrf9160.yaml
+++ b/boards/innblue/innblue22/innblue22_nrf9160.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 64
 flash: 256
diff --git a/boards/innblue/innblue22/innblue22_nrf9160_ns.yaml b/boards/innblue/innblue22/innblue22_nrf9160_ns.yaml
index 4542d90bad0..d81920f42ed 100644
--- a/boards/innblue/innblue22/innblue22_nrf9160_ns.yaml
+++ b/boards/innblue/innblue22/innblue22_nrf9160_ns.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 128
 flash: 192
diff --git a/boards/intel/adl/Kconfig.defconfig b/boards/intel/adl/Kconfig.defconfig
index 3a6bcaf9ce0..4e3f649a205 100644
--- a/boards/intel/adl/Kconfig.defconfig
+++ b/boards/intel/adl/Kconfig.defconfig
@@ -7,10 +7,10 @@ config BUILD_OUTPUT_STRIPPED
 config MP_MAX_NUM_CPUS
 	default 2
 
-# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
+# TSC on this board is 1.5 GHz, HPET and APIC are 19.2 MHz
 config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 1900000000 if APIC_TSC_DEADLINE_TIMER
-	default 1900000000 if APIC_TIMER_TSC
+	default 1500000000 if APIC_TSC_DEADLINE_TIMER
+	default 1500000000 if APIC_TIMER_TSC
 	default 19200000
 
 if APIC_TIMER
diff --git a/boards/intel/adsp/Kconfig.defconfig b/boards/intel/adsp/Kconfig.defconfig
index eafedb0c550..8c804c48c75 100644
--- a/boards/intel/adsp/Kconfig.defconfig
+++ b/boards/intel/adsp/Kconfig.defconfig
@@ -8,3 +8,18 @@ config DAI_SSP_HAS_POWER_CONTROL
 	def_bool y
 
 endif
+
+if BOARD_INTEL_ADSP
+
+config MAIN_STACK_SIZE
+	default 2048 if BOARD_INTEL_ADSP_CAVS25
+	default 2048 if BOARD_INTEL_ADSP_CAVS25_TGPH
+	default 2048 if BOARD_INTEL_ADSP_ACE15_MTPM
+	default 2048 if BOARD_INTEL_ADSP_ACE15_MTPM_SIM
+	default 2048 if BOARD_INTEL_ADSP_ACE20_LNL
+	default 2048 if BOARD_INTEL_ADSP_ACE20_LNL_SIM
+	default 4096 if BOARD_INTEL_ADSP_ACE30
+	default 4096 if BOARD_INTEL_ADSP_ACE30_PTL
+	default 4096 if BOARD_INTEL_ADSP_ACE30_PTL_SIM
+
+endif # BOARD_INTEL_ADSP
diff --git a/boards/intel/adsp/intel_adsp_ace15_mtpm_defconfig b/boards/intel/adsp/intel_adsp_ace15_mtpm_defconfig
index 2237dfb963a..9c0d2ca0cda 100644
--- a/boards/intel/adsp/intel_adsp_ace15_mtpm_defconfig
+++ b/boards/intel/adsp/intel_adsp_ace15_mtpm_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_GEN_ISR_TABLES=y
 CONFIG_GEN_IRQ_VECTOR_TABLE=n
 
diff --git a/boards/intel/adsp/intel_adsp_ace15_mtpm_sim_defconfig b/boards/intel/adsp/intel_adsp_ace15_mtpm_sim_defconfig
index 7a051327234..8c36c0e39dd 100644
--- a/boards/intel/adsp/intel_adsp_ace15_mtpm_sim_defconfig
+++ b/boards/intel/adsp/intel_adsp_ace15_mtpm_sim_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_INTEL_ADSP_SIM=y
 CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW=y
 
diff --git a/boards/intel/adsp/intel_adsp_ace20_lnl_defconfig b/boards/intel/adsp/intel_adsp_ace20_lnl_defconfig
index 3d897eb9673..4f2503e2afc 100644
--- a/boards/intel/adsp/intel_adsp_ace20_lnl_defconfig
+++ b/boards/intel/adsp/intel_adsp_ace20_lnl_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_GEN_ISR_TABLES=y
 CONFIG_GEN_IRQ_VECTOR_TABLE=n
 
diff --git a/boards/intel/adsp/intel_adsp_ace20_lnl_sim_defconfig b/boards/intel/adsp/intel_adsp_ace20_lnl_sim_defconfig
index 5f03e403e3c..6acb302da0b 100644
--- a/boards/intel/adsp/intel_adsp_ace20_lnl_sim_defconfig
+++ b/boards/intel/adsp/intel_adsp_ace20_lnl_sim_defconfig
@@ -1,6 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_INTEL_ADSP_SIM=y
 CONFIG_GEN_ISR_TABLES=y
 CONFIG_GEN_IRQ_VECTOR_TABLE=n
diff --git a/boards/intel/adsp/intel_adsp_ace30_defconfig b/boards/intel/adsp/intel_adsp_ace30_defconfig
index 913d2a8c3e3..85f377409f7 100644
--- a/boards/intel/adsp/intel_adsp_ace30_defconfig
+++ b/boards/intel/adsp/intel_adsp_ace30_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=4096
-
 CONFIG_GEN_ISR_TABLES=y
 CONFIG_GEN_IRQ_VECTOR_TABLE=n
 
diff --git a/boards/intel/adsp/intel_adsp_ace30_ptl_defconfig b/boards/intel/adsp/intel_adsp_ace30_ptl_defconfig
index 913d2a8c3e3..85f377409f7 100644
--- a/boards/intel/adsp/intel_adsp_ace30_ptl_defconfig
+++ b/boards/intel/adsp/intel_adsp_ace30_ptl_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=4096
-
 CONFIG_GEN_ISR_TABLES=y
 CONFIG_GEN_IRQ_VECTOR_TABLE=n
 
diff --git a/boards/intel/adsp/intel_adsp_ace30_ptl_sim_defconfig b/boards/intel/adsp/intel_adsp_ace30_ptl_sim_defconfig
index 429223286bf..5373f0c0bf8 100644
--- a/boards/intel/adsp/intel_adsp_ace30_ptl_sim_defconfig
+++ b/boards/intel/adsp/intel_adsp_ace30_ptl_sim_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_INTEL_ADSP_SIM=y
 CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW=y
 
diff --git a/boards/intel/adsp/intel_adsp_cavs25_defconfig b/boards/intel/adsp/intel_adsp_cavs25_defconfig
index 24443bce131..37aab5b06d4 100644
--- a/boards/intel/adsp/intel_adsp_cavs25_defconfig
+++ b/boards/intel/adsp/intel_adsp_cavs25_defconfig
@@ -2,8 +2,6 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_GEN_ISR_TABLES=y
 CONFIG_GEN_IRQ_VECTOR_TABLE=n
 
diff --git a/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig b/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig
index 7e79840a033..d842740df75 100644
--- a/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig
+++ b/boards/intel/adsp/intel_adsp_cavs25_tgph_defconfig
@@ -2,8 +2,6 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_GEN_ISR_TABLES=y
 CONFIG_GEN_IRQ_VECTOR_TABLE=n
 
diff --git a/boards/intel/btl/CMakeLists.txt b/boards/intel/btl/CMakeLists.txt
new file mode 100644
index 00000000000..ee5e7343e83
--- /dev/null
+++ b/boards/intel/btl/CMakeLists.txt
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Create an EFI image
+if(CONFIG_BUILD_OUTPUT_EFI)
+  set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+    COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/arch/x86/zefi/zefi.py
+    -c ${CMAKE_C_COMPILER}
+    -o ${CMAKE_OBJCOPY}
+    -i ${ZEPHYR_BASE}/include ${PROJECT_BINARY_DIR}/include/generated
+    -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf
+    $<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose>
+    WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
+  )
+endif()
diff --git a/boards/intel/btl/Kconfig.defconfig b/boards/intel/btl/Kconfig.defconfig
new file mode 100644
index 00000000000..177c7c1f0d2
--- /dev/null
+++ b/boards/intel/btl/Kconfig.defconfig
@@ -0,0 +1,71 @@
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+
+config BUILD_OUTPUT_STRIPPED
+	default y
+
+config MP_MAX_NUM_CPUS
+	default 2
+
+# TSC on this board is 2.9 GHz, HPET is 19.2 MHz
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 2900000000 if APIC_TSC_DEADLINE_TIMER
+	default 2900000000 if APIC_TIMER_TSC
+	default 19200000
+
+if APIC_TIMER
+
+config APIC_TIMER_IRQ
+	default 24
+
+endif
+
+if APIC_TIMER_TSC
+
+config APIC_TIMER_TSC_M
+	default 3
+
+config APIC_TIMER_TSC_N
+	default 249
+
+endif
+
+config ACPI
+	default y
+
+if ACPI
+
+config HEAP_MEM_POOL_ADD_SIZE_ACPI
+	default 64000000
+
+config MAIN_STACK_SIZE
+	default 320000
+
+if SHELL
+
+config SHELL_STACK_SIZE
+	default 320000
+
+endif # SHELL
+
+endif # ACPI
+
+if DMA
+
+config DMA_64BIT
+	default y
+
+config DMA_DW_HW_LLI
+	default n
+
+config DMA_DW_CHANNEL_COUNT
+	default 2
+
+endif
+
+config UART_NS16550_INTEL_LPSS_DMA
+	default y if BOARD_INTEL_BTL_S_CRB
+
+config HAS_COVERAGE_SUPPORT
+	default y
diff --git a/boards/intel/btl/Kconfig.intel_btl_s_crb b/boards/intel/btl/Kconfig.intel_btl_s_crb
new file mode 100644
index 00000000000..19f802f0c31
--- /dev/null
+++ b/boards/intel/btl/Kconfig.intel_btl_s_crb
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_INTEL_BTL_S_CRB
+	select SOC_RAPTOR_LAKE
diff --git a/boards/intel/btl/board.cmake b/boards/intel/btl/board.cmake
new file mode 100644
index 00000000000..6b01bab2aee
--- /dev/null
+++ b/boards/intel/btl/board.cmake
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_set_flasher_ifnset(misc-flasher)
+board_finalize_runner_args(misc-flasher)
diff --git a/boards/intel/btl/board.yml b/boards/intel/btl/board.yml
new file mode 100644
index 00000000000..f3b6dd2e2f8
--- /dev/null
+++ b/boards/intel/btl/board.yml
@@ -0,0 +1,6 @@
+boards:
+  - name: intel_btl_s_crb
+    full_name: Bartlett Lake P CRB
+    vendor: intel
+    socs:
+      - name: raptor_lake
diff --git a/boards/intel/btl/doc/index.rst b/boards/intel/btl/doc/index.rst
new file mode 100644
index 00000000000..239a679eb89
--- /dev/null
+++ b/boards/intel/btl/doc/index.rst
@@ -0,0 +1,57 @@
+.. zephyr:board:: intel_btl_s_crb
+
+Overview
+********
+Bartlett Lake processor is a 64-bit multi-core processor built on Intel 7 process
+Technology. Bartlett Lake is based on a Hybrid architecture, utilizing
+P-cores for performance and E-Cores for efficiency.
+
+The S-Processor line is a 2-Chip Platform that includes the Processor Die and
+Platform Controller Hub (PCH-S) Die in the Package.
+
+For more information about Raptor Lake Processor lines, P-cores, and E-cores
+please refer to `BTL`_.
+
+This board configuration enables kernel support for the Bartlett Lake S boards.
+
+Hardware
+********
+
+.. zephyr:board-supported-hw::
+
+General information about the board can be found at the `BTL`_ website.
+
+Connections and IOs
+===================
+
+Refer to the `BTL`_ website for more information.
+
+Programming and Debugging
+*************************
+Use the following procedures for booting an image for an Bartlett Lake S CRB board.
+
+.. contents::
+   :depth: 1
+   :local:
+   :backlinks: top
+
+Build Zephyr application
+========================
+
+#. Build a Zephyr application; for instance, to build the ``hello_world``
+   application for Bartlett Lake S CRB:
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: intel_btl_s_crb
+      :goals: build
+
+   .. note::
+
+      A Zephyr EFI image file named :file:`zephyr.efi` is automatically
+      created in the build directory after the application is built.
+
+.. include:: ../../../intel/common/efi_boot.rst
+   :start-after: start_include_here
+
+.. _BTL: https://www.intel.com/content/www/us/en/secure/content-details/839635/bartlett-lake-s-processor-external-design-specification-eds-for-edge-platforms.html?DocID=839635
diff --git a/boards/intel/btl/intel_btl_s_crb.dts b/boards/intel/btl/intel_btl_s_crb.dts
new file mode 100644
index 00000000000..3ae2d4592c8
--- /dev/null
+++ b/boards/intel/btl/intel_btl_s_crb.dts
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <mem.h>
+
+#define DT_DRAM_SIZE		DT_SIZE_M(2048)
+
+#include <intel/bartlett_lake_s.dtsi>
+
+/ {
+	model = "intel_btl_s_crb";
+	compatible = "intel,bartlett-lake-crb";
+
+	chosen {
+		zephyr,sram = &dram0;
+		zephyr,console = &uart_ec_0;
+		zephyr,shell-uart = &uart_ec_0;
+	};
+
+	aliases {
+		watchdog0 = &tco_wdt;
+		rtc = &rtc;
+	};
+};
+
+&uart_ec_0 {
+	status = "okay";
+};
+
+&rtc {
+	status = "okay";
+};
diff --git a/boards/intel/btl/intel_btl_s_crb.yaml b/boards/intel/btl/intel_btl_s_crb.yaml
new file mode 100644
index 00000000000..a569213d394
--- /dev/null
+++ b/boards/intel/btl/intel_btl_s_crb.yaml
@@ -0,0 +1,15 @@
+identifier: intel_btl_s_crb
+name: Bartlett Lake S CRB
+type: mcu
+arch: x86
+toolchain:
+  - zephyr
+ram: 2048
+supported:
+  - acpi
+  - smp
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+vendor: intel
diff --git a/boards/intel/btl/intel_btl_s_crb_defconfig b/boards/intel/btl/intel_btl_s_crb_defconfig
new file mode 100644
index 00000000000..853850deb12
--- /dev/null
+++ b/boards/intel/btl/intel_btl_s_crb_defconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_PIC_DISABLE=y
+CONFIG_LOAPIC=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_NS16550=y
+CONFIG_UART_NS16550_VARIANT_NS16750=y
+CONFIG_UART_CONSOLE=y
+CONFIG_X2APIC=y
+CONFIG_SMP=y
+CONFIG_BUILD_OUTPUT_EFI=y
diff --git a/boards/intel/niosv_g/niosv_g.dts b/boards/intel/niosv_g/niosv_g.dts
index 4ebd9c9721a..cbaf19ec02d 100644
--- a/boards/intel/niosv_g/niosv_g.dts
+++ b/boards/intel/niosv_g/niosv_g.dts
@@ -27,7 +27,7 @@
 };
 
 &mtimer {
-	reg = <0x90000 0x10>;
+	reg = <0x90000 0x8 0x90008 0x8>;
 };
 
 &uart0 {
diff --git a/boards/intel/niosv_m/niosv_m.dts b/boards/intel/niosv_m/niosv_m.dts
index 495594f72dc..e32edc3c7c2 100644
--- a/boards/intel/niosv_m/niosv_m.dts
+++ b/boards/intel/niosv_m/niosv_m.dts
@@ -27,7 +27,7 @@
 };
 
 &mtimer {
-	reg = <0x90000 0x10>;
+	reg = <0x90000 0x8 0x90008 0x8>;
 };
 
 &uart0 {
diff --git a/boards/intel/rpl/Kconfig.defconfig b/boards/intel/rpl/Kconfig.defconfig
index 4eb5d8c3126..6478c25f658 100644
--- a/boards/intel/rpl/Kconfig.defconfig
+++ b/boards/intel/rpl/Kconfig.defconfig
@@ -8,12 +8,26 @@ config BUILD_OUTPUT_STRIPPED
 config MP_MAX_NUM_CPUS
 	default 2
 
-# TSC on this board is 1.9 GHz, HPET and APIC are 19.2 MHz
+if BOARD_INTEL_RPL_S_CRB
+
+# TSC on this board is 2.4 GHz for RPL-S, HPET and APIC are 19.2 MHz
 config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 1900000000 if APIC_TSC_DEADLINE_TIMER
-	default 1900000000 if APIC_TIMER_TSC
+	default 2400000000 if APIC_TSC_DEADLINE_TIMER
+	default 2400000000 if APIC_TIMER_TSC
 	default 19200000
 
+endif #BOARD_INTEL_RPL_S_CRB
+
+if BOARD_INTEL_RPL_P_CRB
+
+# TSC on this board is 1.8 GHz for RPL-P, HPET and APIC are 19.2 MHz
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 1800000000 if APIC_TSC_DEADLINE_TIMER
+	default 1800000000 if APIC_TIMER_TSC
+	default 19200000
+
+endif #BOARD_INTEL_RPL_P_CRB
+
 if APIC_TIMER
 config APIC_TIMER_IRQ
 	default 24
diff --git a/boards/ite/it515xx_evb/Kconfig.defconfig b/boards/ite/it515xx_evb/Kconfig.defconfig
new file mode 100644
index 00000000000..e5033cdd7c3
--- /dev/null
+++ b/boards/ite/it515xx_evb/Kconfig.defconfig
@@ -0,0 +1,17 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_IT515XX_EVB
+
+if PM
+
+config PM_DEVICE
+	default y
+
+choice PM_POLICY
+	default PM_POLICY_CUSTOM
+endchoice
+
+endif # PM
+
+endif # BOARD_IT515XX_EVB
diff --git a/boards/ite/it515xx_evb/Kconfig.it515xx_evb b/boards/ite/it515xx_evb/Kconfig.it515xx_evb
new file mode 100644
index 00000000000..123837216ab
--- /dev/null
+++ b/boards/ite/it515xx_evb/Kconfig.it515xx_evb
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_IT515XX_EVB
+	select SOC_IT51526AW
diff --git a/boards/ite/it515xx_evb/board.yml b/boards/ite/it515xx_evb/board.yml
new file mode 100644
index 00000000000..d4c7074979f
--- /dev/null
+++ b/boards/ite/it515xx_evb/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: it515xx_evb
+  full_name: IT51XXX series
+  vendor: ite
+  socs:
+    - name: it51526aw
diff --git a/boards/ite/it515xx_evb/doc/index.rst b/boards/ite/it515xx_evb/doc/index.rst
new file mode 100644
index 00000000000..cdd3ad54735
--- /dev/null
+++ b/boards/ite/it515xx_evb/doc/index.rst
@@ -0,0 +1,163 @@
+.. zephyr:board:: it515xx_evb
+
+Overview
+********
+
+The IT51XXX is a 32-bit RISC-V microcontroller.
+And a highly integrated embedded controller with system functions.
+It is suitable for mobile system applications. The picture below is
+the IT51526 development board (also known as it515xx_evb) and its debug card.
+
+.. figure:: it515xx_evb_and_debug_card.webp
+     :align: center
+     :alt: IT51526 EVB
+
+To find out more about ITE, visit our World Wide Web at:`ITE's website`_
+
+Hardware
+********
+The IT51XXX series contains different chip types(ex, it51526, it51527),
+and they support different hardware features.
+Listing the IT51526 hardware features as following:
+
+- RISC-V RV32IMC instruction set
+- 4KB instruction cache size
+- 128KB SRAM in total
+- Built-in 32.768 kHz clock generator
+- Embedded Flash, 512K/1024K-byte e-flash
+- eSPI, SPI, BRAM, KBC, PECI, UART
+- GPIO, PWM, ADC, INTC, WUC, Timer, Watchdog, KB scan, JTAG
+- Support 3 Voltage Comparator
+- Support Cryptographic Engine
+- 9 SMBus hosts, 3 targets, with 12 SMBus channels, compatible with I2C
+- I3C host: Support two I3C controllers, compliant with the MIPI I3C v1.0 SEPC.
+- Two-wire serial interface up to 12.5MHz using Push-Pull.
+- Support SDR, IBI, Hot-Join.
+- I3C target: Support SDR, FIFO co-use DLM. Support Push-Pull output.
+
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and debugging on it51526
+************************************
+
+In order to upload the application to the device,
+you'll need our flash tool and Download board.
+You can get them at: `ITE's website`_.
+
+Wiring
+=======
+#. Connect the Download Board to your host computer using the USB cable.
+
+#. Connect the it515xx_evb to the evolution motherboard.
+
+#. Connect the Download Board J5 to J38(GPC1 & GPC2) on the evolution motherboard.
+
+#. Connect the USB to UART wire to UART0 connector on the evolution motherboard.
+
+   .. image:: it515xx_evb_wiring.webp
+        :align: center
+        :alt: it515xx_evb wiring
+
+   .. note:: Be careful during connection!
+    Use separate wires to connect I2C pins with pins on the it515xx_evb board.
+    Wiring connection is described in the table below.
+
+    +-------------+---------------+
+    |   J5        | it515xx_evb   |
+    |   Connector | J38 Connector |
+    +=============+===============+
+    |      2      |      C1       |
+    +-------------+---------------+
+    |      3      |      C2       |
+    +-------------+---------------+
+    |      4      |      GND      |
+    +-------------+---------------+
+
+    For USB to UART cable, connect the evolution motherboard as below:
+
+    +-------------+---------------+
+    | USB to UART | Evolution     |
+    | cable       | motherboard   |
+    |             | UART0         |
+    |             | Connector     |
+    +=============+===============+
+    |     USB     |     UART0     |
+    +-------------+---------------+
+
+Building
+========
+
+#. Build :zephyr:code-sample:`hello_world` application as you would normally do
+   (see :`Zephyr Getting Started Guide`_):.
+
+   .. zephyr-app-commands::
+      :board: it515xx_evb
+      :zephyr-app: samples/hello_world
+      :goals: build
+
+#. The file :file:`zephyr.bin` will be created by west.
+
+Flashing
+========
+
+Windows
+--------
+
+Use the winflash tool to program a zephyr application
+to the it515xx board flash.
+
+#. Flashing steps as described in the link: `Flashing steps`_.
+
+#. Turn on the it515xx_evb board switch, you should see ``"Hello World! it515xx_evb"``
+   sent by the board. If you don't see this message, press the Reset button and the
+   message should appear.
+
+Ubuntu
+--------
+
+#. Run your favorite terminal program to listen for output.
+   Under Linux the terminal should be :code:`/dev/ttyUSB0`. Do not close it.
+
+   For example:
+
+   .. code-block:: console
+
+      $ minicom -D /dev/ttyUSB0 -b 115200
+
+#. Open a second terminal window and use the Linux flash tool to flash your board.
+
+   .. code-block:: console
+
+      $ sudo ~/itetool/ite -f build/zephyr/zephyr.bin
+
+   .. note:: The source code of ITE tool can be downloaded here:
+    https://www.ite.com.tw/upload/2024_01_23/6_20240123162336wu55j1Rjm4.bz2
+
+#. Split first and second terminal windows to view both of them.
+   You should see ``"Hello World! it515xx_evb"`` in the first terminal window.
+   If you don't see this message, press the Reset button and the message should appear.
+
+Debugging
+=========
+
+it515xx_evb board can be debugged by connecting USB to UART. We can write commands and
+read messages through minicom in the Ubuntu terminal.
+
+Troubleshooting
+===============
+
+#. If the flash tool reports a failure, re-plug the 8390 Download board or
+   power cycle the it515xx_evb board and try again.
+
+References
+==========
+
+.. target-notes::
+
+.. _ITE's website: https://www.ite.com.tw/en
+.. _Zephyr Getting Started Guide: https://docs.zephyrproject.org/latest/getting_started/index.html
+.. _Flashing steps: https://docs.zephyrproject.org/latest/boards/ite/it82xx2_evb/doc/index.html#flashing
diff --git a/boards/ite/it515xx_evb/doc/it515xx_evb_and_debug_card.webp b/boards/ite/it515xx_evb/doc/it515xx_evb_and_debug_card.webp
new file mode 100644
index 00000000000..d6d81db1aea
Binary files /dev/null and b/boards/ite/it515xx_evb/doc/it515xx_evb_and_debug_card.webp differ
diff --git a/boards/ite/it515xx_evb/doc/it515xx_evb_wiring.webp b/boards/ite/it515xx_evb/doc/it515xx_evb_wiring.webp
new file mode 100644
index 00000000000..c942044b556
Binary files /dev/null and b/boards/ite/it515xx_evb/doc/it515xx_evb_wiring.webp differ
diff --git a/boards/ite/it515xx_evb/it515xx_evb.dts b/boards/ite/it515xx_evb/it515xx_evb.dts
new file mode 100644
index 00000000000..4d0ccfb7485
--- /dev/null
+++ b/boards/ite/it515xx_evb/it515xx_evb.dts
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <ite/it51xxx.dtsi>
+#include <ite/it51xxx-pinctrl-map.dtsi>
+
+/ {
+	model = "IT515XX EV-Board";
+	compatible = "ite,it515xx-evb";
+
+	aliases {
+		led0 = &led0;
+		watchdog0 = &twd0;
+	};
+
+	chosen {
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,flash-controller = &flashctrl;
+		zephyr,code-partition = &slot0_partition;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led_0 {
+			gpios = <&gpioc 0 GPIO_ACTIVE_HIGH>;
+			label = "Green LED";
+		};
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	clock-frequency = <1843200>;
+	pinctrl-0 = <&uart1_rx_gpc7_default
+		     &uart1_tx_gpe6_default>;
+	pinctrl-names = "default";
+};
+
+&ite_uart1_wrapper {
+	status = "okay";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		slot0_partition: partition@0 {
+			label = "image-0";
+			reg = <0x00000000 DT_SIZE_K(128)>;
+		};
+
+		slot1_partition: partition@20000 {
+			label = "image-1";
+			reg = <0x00020000 DT_SIZE_K(128)>;
+		};
+
+		storage_partition: partition@40000 {
+			label = "storage";
+			reg = <0x00040000 DT_SIZE_K(256)>;
+		};
+	};
+};
+
+&kbd {
+	status = "okay";
+	pinctrl-0 = <&ksi0_default
+		     &ksi1_default
+		     &ksi2_default
+		     &ksi3_default
+		     &ksi4_default
+		     &ksi5_default
+		     &ksi6_default
+		     &ksi7_default
+		     &kso0_default
+		     &kso1_default
+		     &kso2_default
+		     &kso3_default
+		     &kso4_default
+		     &kso5_default
+		     &kso6_default
+		     &kso7_default
+		     &kso8_default
+		     &kso9_default
+		     &kso10_default
+		     &kso11_default
+		     &kso12_default
+		     &kso13_default
+		     &kso14_default
+		     &kso15_default>;
+	pinctrl-names = "default";
+	row-size = <8>;
+	col-size = <16>;
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_ch3_gpi3_default>;
+	pinctrl-names = "default";
+};
+
+/* test fan tachometer sensor */
+&tach0 {
+	status = "okay";
+	input-pin = <IT51XXX_TACH_INPUT_PIN_A>;
+	pulses-per-round = <2>;
+	pinctrl-0 = <&tach0a_gpd6_default>;
+	pinctrl-names = "default";
+};
diff --git a/boards/ite/it515xx_evb/it515xx_evb.yaml b/boards/ite/it515xx_evb/it515xx_evb.yaml
new file mode 100644
index 00000000000..cddae71d22d
--- /dev/null
+++ b/boards/ite/it515xx_evb/it515xx_evb.yaml
@@ -0,0 +1,14 @@
+identifier: it515xx_evb
+name: ITE IT51XXX EVB
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+ram: 128
+supported:
+  - flash
+  - gpio
+  - pinctrl
+  - pm
+  - uart
+vendor: ite
diff --git a/boards/ite/it515xx_evb/it515xx_evb_defconfig b/boards/ite/it515xx_evb/it515xx_evb_defconfig
new file mode 100644
index 00000000000..b14dac07519
--- /dev/null
+++ b/boards/ite/it515xx_evb/it515xx_evb_defconfig
@@ -0,0 +1,19 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+# General Kernel Options
+CONFIG_XIP=y
+
+# UART Driver
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Console Driver
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# GPIO Driver
+CONFIG_GPIO=y
+
+# Clock Driver
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/ite/it82xx2_evb/Kconfig.defconfig b/boards/ite/it82xx2_evb/Kconfig.defconfig
deleted file mode 100644
index a106a9d6151..00000000000
--- a/boards/ite/it82xx2_evb/Kconfig.defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright (c) 2023 ITE Corporation. All Rights Reserved.
-# SPDX-License-Identifier: Apache-2.0
-
-if BOARD_IT82XX2_EVB
-
-config INPUT
-	default y if KSCAN
-
-endif
diff --git a/boards/ite/it82xx2_evb/doc/index.rst b/boards/ite/it82xx2_evb/doc/index.rst
index d31b989f225..938264879b8 100644
--- a/boards/ite/it82xx2_evb/doc/index.rst
+++ b/boards/ite/it82xx2_evb/doc/index.rst
@@ -1,7 +1,4 @@
-.. _it82xx2_evb:
-
-ITE IT82XX2 series
-######################
+.. zephyr:board:: it82xx2_evb
 
 Overview
 ********
@@ -40,63 +37,8 @@ Listing the IT82202 hardware features as following:
 
 Supported Features
 ==================
-currently supports the following hardware features:
-
-.. list-table:: Supported Features
-   :header-rows: 1
-   :widths: auto
-
-   * - Interface
-     - Controller
-     - Driver/Component
-   * - NVIC
-     - on-chip
-     - interrupt controller
-   * - FLASH
-     - on-chip
-     - flash controller
-   * - PINCTRL
-     - on-chip
-     - pin controller
-   * - ESPI
-     - on-chip
-     - espi
-   * - PECI
-     - on-chip
-     - peci
-   * - UART
-     - on-chip
-     - serial
-   * - GPIO
-     - on-chip
-     - gpio
-   * - PWM
-     - on-chip
-     - pwm
-   * - ADC
-     - on-chip
-     - adc
-   * - TIMER
-     - on-chip
-     - timer
-   * - WATCHDOG
-     - on-chip
-     - watchdog
-   * - KSCAN
-     - on-chip
-     - kscan
-   * - SENSOR
-     - on-chip
-     - voltage comparator
-   * - I2C
-     - on-chip
-     - i2c
-
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the
-:zephyr_file:`boards/ite/it82xx2_evb/it82xx2_evb_defconfig` Kconfig file.
+
+.. zephyr:board-supported-hw::
 
 Programming and debugging on it82202
 ************************************
diff --git a/boards/ite/it82xx2_evb/it82xx2_evb.dts b/boards/ite/it82xx2_evb/it82xx2_evb.dts
index 29e8ad721c8..3aa16d53df1 100644
--- a/boards/ite/it82xx2_evb/it82xx2_evb.dts
+++ b/boards/ite/it82xx2_evb/it82xx2_evb.dts
@@ -17,7 +17,6 @@
 		i2c-0 = &i2c0;
 		peci-0 = &peci0;
 		led0 = &led0;
-		kscan0 = &kscan_input;
 		watchdog0 = &twd0;
 		pwm-0 = &pwm0;
 	};
@@ -30,7 +29,6 @@
 		zephyr,flash = &flash0;
 		zephyr,flash-controller = &flashctrl;
 		zephyr,code-partition = &slot0_partition;
-		zephyr,keyboard-scan = &kscan_input;
 	};
 
 	leds {
@@ -196,10 +194,6 @@
 	pinctrl-names = "default";
 	row-size = <8>;
 	col-size = <16>;
-
-	kscan_input: kscan-input {
-		compatible = "zephyr,kscan-input";
-	};
 };
 
 &peci0 {
diff --git a/boards/ite/it82xx2_evb/it82xx2_evb.yaml b/boards/ite/it82xx2_evb/it82xx2_evb.yaml
index 505c2d7d910..e4e0b974264 100644
--- a/boards/ite/it82xx2_evb/it82xx2_evb.yaml
+++ b/boards/ite/it82xx2_evb/it82xx2_evb.yaml
@@ -15,7 +15,6 @@ supported:
   - gpio
   - usb_device
   - i2c
-  - kscan
   - pm
   - pwm
   - tach
diff --git a/boards/ite/it82xx2_evb/it82xx2_evb_defconfig b/boards/ite/it82xx2_evb/it82xx2_evb_defconfig
index 2b174670d48..2a244e464eb 100644
--- a/boards/ite/it82xx2_evb/it82xx2_evb_defconfig
+++ b/boards/ite/it82xx2_evb/it82xx2_evb_defconfig
@@ -18,8 +18,3 @@ CONFIG_UART_CONSOLE=y
 
 # GPIO Driver
 CONFIG_GPIO=y
-
-# Power Management
-CONFIG_PM=y
-CONFIG_PM_DEVICE=y
-CONFIG_PM_POLICY_CUSTOM=y
diff --git a/boards/ite/it8xxx2_evb/Kconfig.defconfig b/boards/ite/it8xxx2_evb/Kconfig.defconfig
index 57fc0404475..0c81c357762 100644
--- a/boards/ite/it8xxx2_evb/Kconfig.defconfig
+++ b/boards/ite/it8xxx2_evb/Kconfig.defconfig
@@ -14,7 +14,4 @@ endchoice
 
 endif # PM
 
-config INPUT
-	default y if KSCAN
-
 endif # BOARD_IT8XXX2_EVB
diff --git a/boards/ite/it8xxx2_evb/doc/index.rst b/boards/ite/it8xxx2_evb/doc/index.rst
index 0e215fddf7e..751294a77b6 100644
--- a/boards/ite/it8xxx2_evb/doc/index.rst
+++ b/boards/ite/it8xxx2_evb/doc/index.rst
@@ -1,7 +1,4 @@
-.. _it8xxx2_evb:
-
-ITE IT8XXX2 series
-######################
+.. zephyr:board:: it8xxx2_evb
 
 Overview
 ********
@@ -37,42 +34,8 @@ Listing the IT81302 hardware features as following:
 
 Supported Features
 ==================
-currently supports the following hardware features:
-
-.. list-table:: Supported Features
-   :header-rows: 1
-   :widths: auto
-
-   * - Interface
-     - Controller
-     - Driver/Component
-   * - NVIC
-     - on-chip
-     - interrupt controller
-   * - TIMER
-     - on-chip
-     - timer
-   * - UART
-     - on-chip
-     - serial
-   * - GPIO
-     - on-chip
-     - gpio
-   * - ADC
-     - on-chip
-     - adc
-   * - I2C
-     - on-chip
-     - i2c
-   * - KSCAN
-     - on-chip
-     - kscan
-
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the
-:zephyr_file:`boards/ite/it8xxx2_evb/it8xxx2_evb_defconfig` Kconfig file.
+
+.. zephyr:board-supported-hw::
 
 Hardware reworks
 ****************
diff --git a/boards/ite/it8xxx2_evb/it8xxx2_evb.dts b/boards/ite/it8xxx2_evb/it8xxx2_evb.dts
index 0ee42f981f0..59b4af711c9 100644
--- a/boards/ite/it8xxx2_evb/it8xxx2_evb.dts
+++ b/boards/ite/it8xxx2_evb/it8xxx2_evb.dts
@@ -17,7 +17,6 @@
 		i2c-0 = &i2c0;
 		peci-0 = &peci0;
 		led0 = &led0;
-		kscan0 = &kscan_input;
 		watchdog0 = &twd0;
 		pwm-0 = &pwm0;
 	};
@@ -30,7 +29,6 @@
 		zephyr,flash = &flash0;
 		zephyr,flash-controller = &flashctrl;
 		zephyr,code-partition = &slot0_partition;
-		zephyr,keyboard-scan = &kscan_input;
 	};
 
 	leds {
@@ -180,10 +178,6 @@
 	pinctrl-names = "default";
 	row-size = <8>;
 	col-size = <16>;
-
-	kscan_input: kscan-input {
-		compatible = "zephyr,kscan-input";
-	};
 };
 &peci0 {
 	status = "okay";
diff --git a/boards/ite/it8xxx2_evb/it8xxx2_evb.yaml b/boards/ite/it8xxx2_evb/it8xxx2_evb.yaml
index 0a57a0937f7..31ef24d2811 100644
--- a/boards/ite/it8xxx2_evb/it8xxx2_evb.yaml
+++ b/boards/ite/it8xxx2_evb/it8xxx2_evb.yaml
@@ -13,7 +13,6 @@ supported:
   - gpio
   - adc
   - i2c
-  - kscan
   - pwm
   - watchdog
 vendor: ite
diff --git a/boards/khadas/edge2/Kconfig.khadas_edge2 b/boards/khadas/edge2/Kconfig.khadas_edge2
new file mode 100644
index 00000000000..58dd61dfe79
--- /dev/null
+++ b/boards/khadas/edge2/Kconfig.khadas_edge2
@@ -0,0 +1,5 @@
+# Copyright 2024 Université Gustave Eiffel
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_KHADAS_EDGE2
+	select SOC_RK3588S
diff --git a/boards/khadas/edge2/board.yml b/boards/khadas/edge2/board.yml
new file mode 100644
index 00000000000..93138f3a2bb
--- /dev/null
+++ b/boards/khadas/edge2/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: khadas_edge2
+  full_name: Edge2
+  vendor: khadas
+  socs:
+  - name: rk3588s
diff --git a/boards/khadas/edge2/doc/index.rst b/boards/khadas/edge2/doc/index.rst
new file mode 100644
index 00000000000..f0ac6de53f8
--- /dev/null
+++ b/boards/khadas/edge2/doc/index.rst
@@ -0,0 +1,83 @@
+.. zephyr:board:: khadas_edge2
+
+Overview
+********
+
+See `Product page`_
+
+.. _Product page: https://www.khadas.com/edge2
+
+Hardware
+********
+
+See `Hardware details`_
+
+.. _Hardware details: https://docs.khadas.com/products/sbc/edge2/hardware/start
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+There are multiple serial ports on the board: Zephyr is using
+uart2 as serial console.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Use the following configuration to run basic Zephyr applications and
+kernel tests on Khadas Edge2 board. For example, with the :zephyr:code-sample:`hello_world`:
+
+1. Non-SMP mode
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :host-os: unix
+   :board: khadas_edge2
+   :goals: build
+
+This will build an image with the hello world sample app.
+
+Build the zephyr image:
+
+.. code-block:: console
+
+   mkimage -C none -A arm64 -O linux -a 0x10000000 -e 0x10000000 -d build/zephyr/zephyr.bin build/zephyr/zephyr.img
+
+Burn the image on the board (we choose to use Rockchip burning tool `rkdeveloptool <https://github.com/rockchip-linux/rkdeveloptool.git>`_, you will need a `SPL <http://dl.khadas.com/products/edge2/firmware/boot/>`_ which is provided by khadas:
+
+.. code-block:: console
+
+   rkdeveloptool db rk3588_spl_loader_*; rkdeveloptool wl 0x100000 zephyr.img; rkdeveloptool rd
+
+The sector 0x100000 was chosen arbitrarily (far away from U-Boot image)
+
+Use U-Boot to load and run Zephyr:
+
+.. code-block:: console
+
+   mmc read ${pxefile_addr_r} 0x100000 0x1000; bootm start ${pxefile_addr_r}; bootm loados; bootm go
+
+0x1000 is the size (in number of sectors) or your image. Increase it if needed.
+
+It will display the following console output:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build XXXXXXXXXXXX  ***
+   Hello World! khadas_edge2
+
+Flashing
+========
+
+Zephyr image can be loaded in DDR memory at address 0x10000000 from SD Card,
+EMMC, QSPI Flash or downloaded from network in uboot.
+
+References
+==========
+
+`Edge2 Documentation`_
+
+.. _Edge2 Documentation: https://docs.khadas.com/products/sbc/edge2/start
diff --git a/boards/khadas/edge2/doc/khadas_edge2.jpg b/boards/khadas/edge2/doc/khadas_edge2.jpg
new file mode 100644
index 00000000000..68278e72a98
Binary files /dev/null and b/boards/khadas/edge2/doc/khadas_edge2.jpg differ
diff --git a/boards/khadas/edge2/khadas_edge2.dts b/boards/khadas/edge2/khadas_edge2.dts
new file mode 100644
index 00000000000..021015213b7
--- /dev/null
+++ b/boards/khadas/edge2/khadas_edge2.dts
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2024 Université Gustave Eiffel
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <rockchip/rk3588s.dtsi>
+
+/ {
+	model = "Khadas Edge2";
+	compatible = "khadas,edge2";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart2;
+		zephyr,shell-uart = &uart2;
+	};
+
+	cpus {
+		/delete-node/ cpu@1;
+		/delete-node/ cpu@2;
+		/delete-node/ cpu@3;
+		/delete-node/ cpu@4;
+		/delete-node/ cpu@5;
+		/delete-node/ cpu@6;
+		/delete-node/ cpu@7;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
diff --git a/boards/khadas/edge2/khadas_edge2.yaml b/boards/khadas/edge2/khadas_edge2.yaml
new file mode 100644
index 00000000000..c9ed4ad11b2
--- /dev/null
+++ b/boards/khadas/edge2/khadas_edge2.yaml
@@ -0,0 +1,9 @@
+identifier: khadas_edge2
+name: Khadas Edge2 (single core, non SMP)
+type: mcu
+arch: arm64
+toolchain:
+  - zephyr
+  - cross-compile
+ram: 8192
+vendor: khadas
diff --git a/boards/khadas/edge2/khadas_edge2_defconfig b/boards/khadas/edge2/khadas_edge2_defconfig
new file mode 100644
index 00000000000..38b7f52812f
--- /dev/null
+++ b/boards/khadas/edge2/khadas_edge2_defconfig
@@ -0,0 +1,17 @@
+# Copyright 2024 Université Gustave Eiffel
+# SPDX-License-Identifier: Apache-2.0
+
+# Platform Configuration
+CONFIG_ARM64_VA_BITS_40=y
+CONFIG_ARM64_PA_BITS_40=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=24000000
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_ARMV8_A_NS=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/khadas/edgev/doc/index.rst b/boards/khadas/edgev/doc/index.rst
index 82294c07e99..b645563e5b2 100644
--- a/boards/khadas/edgev/doc/index.rst
+++ b/boards/khadas/edgev/doc/index.rst
@@ -13,23 +13,7 @@ See <https://docs.khadas.com/linux/edge/Hardware.html#Edge-V-1>
 Supported Features
 ==================
 
-Khadas Edge-V board default configuration supports the following
-hardware features:
-
-+-----------+------------+--------------------------------------+
-| Interface | Controller | Driver/Component                     |
-+===========+============+======================================+
-| GIC-500   | on-chip    | GICv3 interrupt controller           |
-+-----------+------------+--------------------------------------+
-| ARM TIMER | on-chip    | System Clock                         |
-+-----------+------------+--------------------------------------+
-| UART      | on-chip    | Synopsys DesignWare 8250 serial port |
-+-----------+------------+--------------------------------------+
-
-Other hardware features have not been enabled yet for this board.
-
-The default configuration can be found in (NON-SMP)
-:zephyr_file:`boards/khadas/edgev/khadas_edgev_defconfig`
+.. zephyr:board-supported-hw::
 
 There are multiple serial ports on the board: Zephyr is using
 uart2 as serial console.
@@ -37,6 +21,8 @@ uart2 as serial console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Use the following configuration to run basic Zephyr applications and
 kernel tests on Khadas Edge-V board. For example, with the :zephyr:code-sample:`hello_world`:
 
diff --git a/boards/kincony/kincony_kc868_a32/doc/index.rst b/boards/kincony/kincony_kc868_a32/doc/index.rst
index d88eec584c6..6a001bbfdd8 100644
--- a/boards/kincony/kincony_kc868_a32/doc/index.rst
+++ b/boards/kincony/kincony_kc868_a32/doc/index.rst
@@ -40,6 +40,8 @@ below to retrieve those files.
 Building & Flashing
 -------------------
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu_defconfig b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu_defconfig
+++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu_defconfig b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu_defconfig
index 071024ac98d..7ed3d6b89a2 100644
--- a/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu_defconfig
+++ b/boards/kincony/kincony_kc868_a32/kincony_kc868_a32_procpu_defconfig
@@ -1,8 +1,6 @@
 # Copyright (c) Bartosz Bilas
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/kws/common/pico_spe-pinctrl-common.dtsi b/boards/kws/common/pico_spe-pinctrl-common.dtsi
new file mode 100644
index 00000000000..bfdcff973f9
--- /dev/null
+++ b/boards/kws/common/pico_spe-pinctrl-common.dtsi
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2025 KWS Computersysteme Gmbh
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart0_default: uart0_default {
+		group1 {
+			pinmux = <UART0_TX_P0>;
+		};
+
+		group2 {
+			pinmux = <UART0_RX_P1>;
+			input-enable;
+		};
+	};
+
+	i2c0_default: i2c0_default {
+		group1 {
+			pinmux = <I2C0_SDA_P4>, <I2C0_SCL_P5>;
+			input-enable;
+			input-schmitt-enable;
+		};
+	};
+
+	i2c1_default: i2c1_default {
+		group1 {
+			pinmux = <I2C1_SDA_P6>, <I2C1_SCL_P7>;
+			input-enable;
+			input-schmitt-enable;
+		};
+	};
+
+	spi0_default: spi0_default {
+		group1 {
+			pinmux = <SPI0_CSN_P17>, <SPI0_SCK_P18>, <SPI0_TX_P19>;
+		};
+
+		group2 {
+			pinmux = <SPI0_RX_P16>;
+			input-enable;
+		};
+	};
+
+	spi1_default: spi1_default {
+		group1 {
+			pinmux = <SPI1_CSN_P13>, <SPI1_SCK_P10>, <SPI1_TX_P11>;
+		};
+
+		group2 {
+			pinmux = <SPI1_RX_P12>;
+			input-enable;
+		};
+	};
+
+	pwm_ch4b_default: pwm_ch4b_default {
+		group1 {
+			pinmux = <PWM_4B_P25>;
+		};
+	};
+
+	adc_default: adc_default {
+		group1 {
+			pinmux = <ADC_CH0_P26>, <ADC_CH1_P27>, <ADC_CH2_P28>, <ADC_CH3_P29>;
+			input-enable;
+		};
+	};
+};
diff --git a/boards/kws/index.rst b/boards/kws/index.rst
new file mode 100644
index 00000000000..0f8fc102b94
--- /dev/null
+++ b/boards/kws/index.rst
@@ -0,0 +1,10 @@
+.. _boards-kws:
+
+KWS Computersysteme Gmbh
+########################
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*
diff --git a/boards/kws/pico2_spe/Kconfig.defconfig b/boards/kws/pico2_spe/Kconfig.defconfig
new file mode 100644
index 00000000000..3daadffce78
--- /dev/null
+++ b/boards/kws/pico2_spe/Kconfig.defconfig
@@ -0,0 +1,34 @@
+# Copyright (c) 2025 KWS Computersysteme Gmbh
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_PICO2_SPE
+
+if I2C_DW
+
+config I2C_DW_CLOCK_SPEED
+	default 125
+
+endif # I2C_DW
+
+config USB_SELF_POWERED
+	default n
+
+config PHY_INIT_PRIORITY
+	default 82
+	depends on NET_L2_ETHERNET && ETH_DRIVER
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+if ETH_LAN865X
+
+config NET_IF_MAX_IPV4_COUNT
+	default 2
+
+endif # ETH_LAN865X
+
+endif # NETWORKING
+
+endif # BOARD_PICO2_SPE
diff --git a/boards/kws/pico2_spe/Kconfig.pico2_spe b/boards/kws/pico2_spe/Kconfig.pico2_spe
new file mode 100644
index 00000000000..9487cc1d810
--- /dev/null
+++ b/boards/kws/pico2_spe/Kconfig.pico2_spe
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 KWS Computersysteme Gmbh
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_PICO2_SPE
+	select SOC_RP2350A_M33 if BOARD_PICO2_SPE_RP2350A_M33
diff --git a/boards/kws/pico2_spe/board.cmake b/boards/kws/pico2_spe/board.cmake
new file mode 100644
index 00000000000..feae063129a
--- /dev/null
+++ b/boards/kws/pico2_spe/board.cmake
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "")
+	set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap")
+endif()
+
+board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]")
+board_runner_args(openocd --cmd-pre-init "source [find target/rp2350.cfg]")
+
+# The adapter speed is expected to be set by interface configuration.
+# The Raspberry Pi's OpenOCD fork doesn't, so match their documentation at
+# https://www.raspberrypi.com/documentation/microcontrollers/debug-probe.html#debugging-with-swd
+board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 5000")
+
+board_runner_args(uf2 "--board-id=RP2350")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake)
diff --git a/boards/kws/pico2_spe/board.yml b/boards/kws/pico2_spe/board.yml
new file mode 100644
index 00000000000..e292243d1b0
--- /dev/null
+++ b/boards/kws/pico2_spe/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: pico2_spe
+  full_name: Pico2-SPE
+  vendor: kws
+  socs:
+  - name: rp2350a
diff --git a/boards/kws/pico2_spe/doc/img/pico2_spe.webp b/boards/kws/pico2_spe/doc/img/pico2_spe.webp
new file mode 100644
index 00000000000..1cf931ddf99
Binary files /dev/null and b/boards/kws/pico2_spe/doc/img/pico2_spe.webp differ
diff --git a/boards/kws/pico2_spe/doc/index.rst b/boards/kws/pico2_spe/doc/index.rst
new file mode 100644
index 00000000000..48bccacea86
--- /dev/null
+++ b/boards/kws/pico2_spe/doc/index.rst
@@ -0,0 +1,59 @@
+.. zephyr:board:: pico2_spe
+
+Overview
+********
+
+The Pico2-SPE is a small, low-cost, versatile boards from
+KWS Computersysteme Gmbh. They are equipped with an RP2350a SoC, an on-board LED,
+a USB connector, an SWD interface. The Pico2-SPE additionally contains an
+Microchip LAN8651 10Base-T1S module. The USB bootloader allows the
+ability to flash without any adapter, in a drag-and-drop manner.
+It is also possible to flash and debug the boards with their SWD interface,
+using an external adapter.
+
+Hardware
+********
+
+- Dual Cortex-M33 or Hazard3 processors at up to 150MHz
+- 520KB of SRAM, and 4MB of on-board flash memory
+- USB 1.1 with device and host support
+- Low-power sleep and dormant modes
+- Drag-and-drop programming using mass storage over USB
+- 26 multi-function GPIO pins including 3 that can be used for ADC
+- 1 SPI, 2 I2C, 2 UART, 3 12-bit 500ksps Analogue to Digital - Converter (ADC), 24 controllable PWM channels
+- 2 Timer with 4 alarms, 1 AON Timer
+- Temperature sensor
+- Microchip LAN8651 10Base-T1S
+- 3 Programmable IO (PIO) blocks, 12 state machines total for custom peripheral support
+
+  - Flexible, user-programmable high-speed IO
+  - Can emulate interfaces such as SD Card and VGA
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+The default pin mapping is unchanged from the Pico-SPE.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+As with the Pico-SPE, the SWD interface can be used to program and debug the
+device, e.g. using OpenOCD with the `Raspberry Pi Debug Probe <https://www.raspberrypi.com/documentation/microcontrollers/debug-probe.html>`_ .
+
+References
+**********
+
+.. _Getting Started with Pico-SPE-Series:
+   https://kws-computer.de/go/pico-spe-getting-started
+
+.. _Pico2-SPE Documentation:
+   https://kws-computer.de/go/pico2-spe-datasheet
+
+.. target-notes::
diff --git a/boards/kws/pico2_spe/pico2_spe-pinctrl.dtsi b/boards/kws/pico2_spe/pico2_spe-pinctrl.dtsi
new file mode 100644
index 00000000000..889f287c642
--- /dev/null
+++ b/boards/kws/pico2_spe/pico2_spe-pinctrl.dtsi
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2025 KWS Computersysteme Gmbh
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/rpi-pico-rp2350a-pinctrl.h>
+
+#include "../common/pico_spe-pinctrl-common.dtsi"
diff --git a/boards/kws/pico2_spe/pico2_spe.dtsi b/boards/kws/pico2_spe/pico2_spe.dtsi
new file mode 100644
index 00000000000..87211d91eff
--- /dev/null
+++ b/boards/kws/pico2_spe/pico2_spe.dtsi
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2025 KWS Computersysteme Gmbh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <freq.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/pwm/pwm.h>
+
+#include "pico2_spe-pinctrl.dtsi"
+
+/ {
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,code-partition = &code_partition;
+	};
+
+	aliases {
+		watchdog0 = &wdt0;
+	};
+
+	pico_header: connector {
+		compatible = "raspberrypi,pico-header";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpio0 0 0>,	/* GP0 */
+			<1 0 &gpio0 1 0>,	/* GP1 */
+			<2 0 &gpio0 2 0>,	/* GP2 */
+			<3 0 &gpio0 3 0>,	/* GP3 */
+			<4 0 &gpio0 4 0>,	/* GP4 */
+			<5 0 &gpio0 5 0>,	/* GP5 */
+			<6 0 &gpio0 6 0>,	/* GP6 */
+			<7 0 &gpio0 7 0>,	/* GP7 */
+			<8 0 &gpio0 8 0>,	/* GP8 */
+			<9 0 &gpio0 9 0>,	/* GP9 */
+			<10 0 &gpio0 10 0>,	/* GP10 */
+			<11 0 &gpio0 11 0>,	/* GP11 */
+			<12 0 &gpio0 12 0>,	/* GP12 */
+			<13 0 &gpio0 13 0>,	/* GP13 */
+			<14 0 &gpio0 14 0>,	/* GP14 */
+			<15 0 &gpio0 15 0>,	/* GP15 */
+			<16 0 &gpio0 16 0>,	/* GP16 */
+			<17 0 &gpio0 17 0>,	/* GP17 */
+			<18 0 &gpio0 18 0>,	/* GP18 */
+			<19 0 &gpio0 19 0>,	/* GP19 */
+			<20 0 &gpio0 20 0>,	/* GP20 */
+			<21 0 &gpio0 21 0>,	/* GP21 */
+			<22 0 &gpio0 22 0>,	/* GP22 */
+			<26 0 &gpio0 26 0>,	/* GP26 */
+			<27 0 &gpio0 27 0>,	/* GP27 */
+			<28 0 &gpio0 28 0>;	/* GP28 */
+	};
+};
+
+&flash0 {
+	reg = <0x10000000 DT_SIZE_M(4)>;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* Reserved memory for an image definition block. The block is much
+		 * smaller than 256 bytes, but in practice the linker places the vector
+		 * table at a much larger alignment offset.
+		 */
+		image_def: partition@0 {
+			label = "image_def";
+			reg = <0x00000000 0x100>;
+			read-only;
+		};
+
+		/*
+		 * Usable flash. Starts at 0x100, after the image definition block.
+		 * The partition size is 4MB minus the 0x100 bytes taken by the
+		 * image definition.
+		 */
+		code_partition: partition@100 {
+			label = "code-partition";
+			reg = <0x100 (DT_SIZE_M(4) - 0x100)>;
+			read-only;
+		};
+	};
+};
+
+&uart0 {
+	current-speed = <115200>;
+	status = "okay";
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-names = "default";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&spi1 {
+	clock-frequency = <DT_FREQ_M(25)>;
+	status = "okay";
+	pinctrl-0 = <&spi1_default>;
+		pinctrl-names = "default";
+	cs-gpios = <&pico_header 13 GPIO_ACTIVE_LOW>;
+
+	lan8651: lan865x@0 {
+		compatible = "microchip,lan865x";
+		reg = <0x0>;
+		spi-max-frequency = <DT_FREQ_M(25)>;
+		int-gpios = <&gpio0 21 (GPIO_ACTIVE_LOW)>;
+		rst-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+		status = "okay";
+
+		local-mac-address = [ CA 2F B7 10 23 79];
+
+		lan865x_mdio: lan865x_mdio {
+			compatible = "microchip,lan865x-mdio";
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ethernet-phy@0 {
+				compatible = "microchip,t1s-phy";
+				reg = <0x0>;
+				plca-enable;
+				plca-node-id = <0>;
+				plca-node-count = <8>;
+				plca-burst-count = <0>;
+				plca-burst-timer = <0x80>;
+				plca-to-timer = <0x20>;
+				status = "okay";
+			};
+		};
+	};
+};
+
+&i2c0 {
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c1_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&adc {
+	pinctrl-0 = <&adc_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&pwm {
+	pinctrl-0 = <&pwm_ch4b_default>;
+	pinctrl-names = "default";
+	divider-int-0 = <255>;
+};
+
+&timer0 {
+	status = "okay";
+};
+
+zephyr_udc0: &usbd {
+	status = "okay";
+};
+
+pico_serial: &uart0 {};
diff --git a/boards/kws/pico2_spe/pico2_spe_rp2350a_m33.dts b/boards/kws/pico2_spe/pico2_spe_rp2350a_m33.dts
new file mode 100644
index 00000000000..4bebd86dbd0
--- /dev/null
+++ b/boards/kws/pico2_spe/pico2_spe_rp2350a_m33.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025 KWS Computersysteme Gmbh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+/* The build system assumes that there's a cpucluster-specific file.
+ *
+ * This file provides composition of the device tree:
+ * 1. The common features of the SoC
+ * 2. Core-specific configuration.
+ * 3. Board-specific configuration.
+ */
+#include <raspberrypi/rpi_pico/rp2350a.dtsi>
+#include <raspberrypi/rpi_pico/m33.dtsi>
+
+/* there's nothing specific to the Cortex-M33 cores vs the (not yet
+ * implemented) Hazard3 cores.
+ */
+#include "pico2_spe.dtsi"
diff --git a/boards/kws/pico2_spe/pico2_spe_rp2350a_m33.yaml b/boards/kws/pico2_spe/pico2_spe_rp2350a_m33.yaml
new file mode 100644
index 00000000000..acdaeafe3a6
--- /dev/null
+++ b/boards/kws/pico2_spe/pico2_spe_rp2350a_m33.yaml
@@ -0,0 +1,20 @@
+identifier: pico2_spe/rp2350a/m33
+name: KWS Pico2 SinglePairEthernet
+type: mcu
+arch: arm
+flash: 4096
+ram: 520
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - adc
+  - clock
+  - counter
+  - dma
+  - gpio
+  - hwinfo
+  - i2c
+  - pwm
+  - spi
+  - uart
diff --git a/boards/kws/pico2_spe/pico2_spe_rp2350a_m33_defconfig b/boards/kws/pico2_spe/pico2_spe_rp2350a_m33_defconfig
new file mode 100644
index 00000000000..8bd68e35113
--- /dev/null
+++ b/boards/kws/pico2_spe/pico2_spe_rp2350a_m33_defconfig
@@ -0,0 +1,14 @@
+# This configuration is orthogonal to whether the Cortex-M33 or Hazard3 cores
+# are in use, but Zephyr does not support providing a qualifier-agnostic
+# _defconfig file.
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_BUILD_OUTPUT_UF2=y
+CONFIG_CLOCK_CONTROL=y
+CONFIG_CONSOLE=y
+CONFIG_GPIO=y
+CONFIG_RESET=y
+CONFIG_SERIAL=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=150000000
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_USE_DT_CODE_PARTITION=y
diff --git a/boards/kws/pico2_spe/support/openocd.cfg b/boards/kws/pico2_spe/support/openocd.cfg
new file mode 100644
index 00000000000..82666bb5331
--- /dev/null
+++ b/boards/kws/pico2_spe/support/openocd.cfg
@@ -0,0 +1,11 @@
+# Copyright (c) 2024 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+# Checking and set 'adapter speed'.
+# Set the adaptor speed, if unset, and given as an argument.
+proc set_adapter_speed_if_not_set { speed } {
+	puts "checking adapter speed..."
+	if { [catch {adapter speed} ret] } {
+		adapter speed $speed
+	}
+}
diff --git a/boards/kws/pico_spe/Kconfig b/boards/kws/pico_spe/Kconfig
new file mode 100644
index 00000000000..e1a877543e6
--- /dev/null
+++ b/boards/kws/pico_spe/Kconfig
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 KWS Computersysteme Gmbh
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_PICO_SPE
+	select RP2_FLASH_W25Q080
diff --git a/boards/kws/pico_spe/Kconfig.defconfig b/boards/kws/pico_spe/Kconfig.defconfig
new file mode 100644
index 00000000000..4f5d5090163
--- /dev/null
+++ b/boards/kws/pico_spe/Kconfig.defconfig
@@ -0,0 +1,34 @@
+# Copyright (c) 2024 KWS Computersysteme Gmbh
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_PICO_SPE
+
+if I2C_DW
+
+config I2C_DW_CLOCK_SPEED
+	default 125
+
+endif # I2C_DW
+
+config USB_SELF_POWERED
+	default n
+
+config PHY_INIT_PRIORITY
+	default 82
+	depends on NET_L2_ETHERNET && ETH_DRIVER
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+if ETH_LAN865X
+
+config NET_IF_MAX_IPV4_COUNT
+	default 2
+
+endif # ETH_LAN865X
+
+endif # NETWORKING
+
+endif # BOARD_PICO_SPE
diff --git a/boards/kws/pico_spe/Kconfig.pico_spe b/boards/kws/pico_spe/Kconfig.pico_spe
new file mode 100644
index 00000000000..1ecb279b3f6
--- /dev/null
+++ b/boards/kws/pico_spe/Kconfig.pico_spe
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 KWS Computersysteme Gmbh
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_PICO_SPE
+	select SOC_RP2040
diff --git a/boards/kws/pico_spe/board.cmake b/boards/kws/pico_spe/board.cmake
new file mode 100644
index 00000000000..ff6f71a2c50
--- /dev/null
+++ b/boards/kws/pico_spe/board.cmake
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# This configuration allows selecting what debug adapter debugging Pico-SPE
+# by a command-line argument.
+# It is mainly intended to support both the 'picoprobe' and 'raspberrypi-swd'
+# adapter described in "Getting started with Raspberry Pi Pico".
+# And any other SWD debug adapter might also be usable with this configuration.
+
+# Set RPI_PICO_DEBUG_ADAPTER to select debug adapter by command-line arguments.
+# e.g.) west build -b pico_spe -- -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd
+# The value is treated as a part of an interface file name that
+# the debugger's configuration file.
+# The value must be the 'stem' part of the name of one of the files
+# in the openocd interface configuration file.
+# The setting is store to CMakeCache.txt.
+if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "")
+	set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap")
+endif()
+
+board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]")
+board_runner_args(openocd --cmd-pre-init "transport select swd")
+board_runner_args(openocd --cmd-pre-init "source [find target/rp2040.cfg]")
+
+# The adapter speed is expected to be set by interface configuration.
+# But if not so, set 2000 to adapter speed.
+board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 2000")
+
+board_runner_args(jlink "--device=RP2040_M0_0")
+board_runner_args(uf2 "--board-id=RPI-RP2")
+board_runner_args(pyocd "--target=rp2040")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/blackmagicprobe.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
\ No newline at end of file
diff --git a/boards/kws/pico_spe/board.yml b/boards/kws/pico_spe/board.yml
new file mode 100644
index 00000000000..5d80b878c0b
--- /dev/null
+++ b/boards/kws/pico_spe/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: pico_spe
+  full_name: Pico-SPE
+  vendor: kws
+  socs:
+  - name: rp2040
diff --git a/boards/kws/pico_spe/doc/img/pico_spe.webp b/boards/kws/pico_spe/doc/img/pico_spe.webp
new file mode 100644
index 00000000000..00e143500b4
Binary files /dev/null and b/boards/kws/pico_spe/doc/img/pico_spe.webp differ
diff --git a/boards/kws/pico_spe/doc/index.rst b/boards/kws/pico_spe/doc/index.rst
new file mode 100644
index 00000000000..3246d36a972
--- /dev/null
+++ b/boards/kws/pico_spe/doc/index.rst
@@ -0,0 +1,235 @@
+.. zephyr:board:: pico_spe
+
+Overview
+********
+
+The Pico-SPE is a small, low-cost, versatile boards from
+KWS Computersysteme Gmbh. They are equipped with an RP2040 SoC, an on-board LED,
+a USB connector, an SWD interface. The Pico-SPE additionally contains an
+Microchip LAN8651 10Base-T1S module. The USB bootloader allows the
+ability to flash without any adapter, in a drag-and-drop manner.
+It is also possible to flash and debug the boards with their SWD interface,
+using an external adapter.
+
+Hardware
+********
+- Dual core Arm Cortex-M0+ processor running up to 133MHz
+- 264KB on-chip SRAM
+- 16MB on-board QSPI flash with XIP capabilities
+- 16 GPIO pins
+- 3 Analog inputs
+- 2 UART peripherals
+- 2 I2C controllers
+- 16 PWM channels
+- USB 1.1 controller (host/device)
+- 8 Programmable I/O (PIO) for custom peripherals
+- On-board LED
+- 1 Watchdog timer peripheral
+- Microchip LAN8651 10Base-T1S
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Pin Mapping
+===========
+
+The peripherals of the RP2040 SoC can be routed to various pins on the board.
+The configuration of these routes can be modified through DTS. Please refer to
+the datasheet to see the possible routings for each peripheral.
+
+External pin mapping on the Pico-SPE is identical to the Pico, but note that internal
+RP2040 GPIO lines 10, 11, 12, 13, 20, 21 are routed to the Microchip LAN8651 on the
+Pico-SPE.
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+.. rst-class:: rst-columns
+
+- UART0_TX : P0
+- UART0_RX : P1
+- I2C0_SDA : P4
+- I2C0_SCL : P5
+- I2C1_SDA : P6
+- I2C1_SCL : P7
+- ADC_CH0 : P26
+- ADC_CH1 : P27
+- ADC_CH2 : P28
+
+Programmable I/O (PIO)
+**********************
+The RP2040 SoC comes with two PIO periherals. These are two simple
+co-processors that are designed for I/O operations. The PIOs run
+a custom instruction set, generated from a custom assembly language.
+PIO programs are assembled using :command:`pioasm`, a tool provided by Raspberry Pi.
+
+Zephyr does not (currently) assemble PIO programs. Rather, they should be
+manually assembled and embedded in source code. An example of how this is done
+can be found at :zephyr_file:`drivers/serial/uart_rpi_pico_pio.c`.
+
+Sample: SPI via PIO
+====================
+
+The :zephyr:code-sample:`bme280` sample includes a
+demonstration of using the PIO SPI driver to communicate with an
+environmental sensor.  The PIO SPI driver supports using any
+combination of GPIO pins for an SPI bus, as well as allowing up to
+four independent SPI buses on a single board (using the two SPI
+devices as well as both PIO devices).
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Flashing
+========
+
+Using SEGGER JLink
+------------------
+
+You can Flash the pico_spe with a SEGGER JLink debug probe as described in
+:ref:`Building, Flashing and Debugging <west-flashing>`.
+
+Here is an example of building and flashing the :zephyr:code-sample:`blinky` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: pico_spe
+   :goals: build
+
+.. code-block:: bash
+
+  west flash --runner jlink
+
+Using OpenOCD
+-------------
+
+To use CMSIS-DAP, you must configure **udev**.
+
+Create a file in /etc/udev.rules.d with any name, and write the line below.
+
+.. code-block:: bash
+
+   ATTRS{idVendor}=="2e8a", ATTRS{idProduct}=="000c", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
+This example is valid for the case that the user joins to ``plugdev`` groups.
+
+The Pico-SPE has an SWD interface that can be used to program
+and debug the on board RP2040. This interface can be utilized by OpenOCD.
+To use it with the RP2040, OpenOCD version 0.12.0 or later is needed.
+
+If you are using a Debian based system (including RaspberryPi OS, Ubuntu. and more),
+using the `pico_setup.sh`_ script is a convenient way to set up the forked version of OpenOCD.
+
+Depending on the interface used (such as JLink), you might need to
+checkout to a branch that supports this interface, before proceeding.
+Build and install OpenOCD as described in the README.
+
+Here is an example of building and flashing the :zephyr:code-sample:`blinky` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: pico_spe
+   :goals: build flash
+   :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=cmsis-dap
+
+Set the environment variables **OPENOCD** to :file:`/usr/local/bin/openocd`
+and **OPENOCD_DEFAULT_PATH** to :file:`/usr/local/share/openocd/scripts`. This should work
+with the OpenOCD that was installed with the default configuration.
+This configuration also works with an environment that is set up by the `pico_setup.sh`_ script.
+
+**RPI_PICO_DEBUG_ADAPTER** specifies what debug adapter is used for debugging.
+
+If **RPI_PICO_DEBUG_ADAPTER** was not assigned, ``cmsis-dap`` is used by default.
+The other supported adapters are ``raspberrypi-swd``, ``jlink`` and ``blackmagicprobe``.
+How to connect ``cmsis-dap`` and ``raspberrypi-swd`` is described in `Getting Started with Pico-SPE-Series`_.
+Any other SWD debug adapter maybe also work with this configuration.
+
+The value of **RPI_PICO_DEBUG_ADAPTER** is cached, so it can be omitted from
+``west flash`` and ``west debug`` if it was previously set while running
+``west build``.
+
+**RPI_PICO_DEBUG_ADAPTER** is used in an argument to OpenOCD as ``"source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]"``.
+Thus, **RPI_PICO_DEBUG_ADAPTER** needs to be assigned the file name of the debug adapter.
+
+You can also flash the board with the following
+command that directly calls OpenOCD (assuming a SEGGER JLink adapter is used):
+
+.. code-block:: console
+
+   $ openocd -f interface/jlink.cfg -c 'transport select swd' -f target/rp2040.cfg -c "adapter speed 2000" -c 'targets rp2040.core0' -c 'program path/to/zephyr.elf verify reset exit'
+
+Using UF2
+---------
+
+If you don't have an SWD adapter, you can flash the Pico-SPE with
+a UF2 file. By default, building an app for this board will generate a
+:file:`build/zephyr/zephyr.uf2` file. If the Pico is powered on with the ``BOOTSEL``
+button pressed, it will appear on the host as a mass storage device. The
+UF2 file should be drag-and-dropped to the device, which will flash the Pico.
+
+Debugging
+=========
+
+The SWD interface can also be used to debug the board. To achieve this, you can
+either use SEGGER JLink or OpenOCD.
+
+Using SEGGER JLink
+------------------
+
+Use a SEGGER JLink debug probe and follow the instruction in
+:ref:`Building, Flashing and Debugging<west-debugging>`.
+
+
+Using OpenOCD
+-------------
+
+Install OpenOCD as described for flashing the board.
+
+Here is an example for debugging the :zephyr:code-sample:`blinky` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: pico_spe
+   :maybe-skip-config:
+   :goals: debug
+   :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd
+
+As with flashing, you can specify the debug adapter by specifying **RPI_PICO_DEBUG_ADAPTER**
+at ``west build`` time. No needs to specify it at ``west debug`` time.
+
+You can also debug with OpenOCD and gdb launching from command-line.
+Run the following command:
+
+.. code-block:: console
+
+   $ openocd -f interface/jlink.cfg -c 'transport select swd' -f target/rp2040.cfg -c "adapter speed 2000" -c 'targets rp2040.core0'
+
+On another terminal, run:
+
+.. code-block:: console
+
+   $ gdb-multiarch
+
+Inside gdb, run:
+
+.. code-block:: console
+
+   (gdb) tar ext :3333
+   (gdb) file path/to/zephyr.elf
+
+You can then start debugging the board.
+
+.. target-notes::
+
+.. _pico_setup.sh:
+   https://raw.githubusercontent.com/raspberrypi/pico-setup/master/pico_setup.sh
+
+.. _Getting Started with Pico-SPE-Series:
+   https://kws-computer.de/go/pico-spe-getting-started
+
+.. _Pico-SPE Documentation:
+   https://kws-computer.de/go/pico-spe-datasheet
diff --git a/boards/kws/pico_spe/pico_spe-pinctrl.dtsi b/boards/kws/pico_spe/pico_spe-pinctrl.dtsi
new file mode 100644
index 00000000000..ba6d29bb19b
--- /dev/null
+++ b/boards/kws/pico_spe/pico_spe-pinctrl.dtsi
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2024 KWS Computersysteme Gmbh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/rpi-pico-rp2040-pinctrl.h>
+
+#include "../common/pico_spe-pinctrl-common.dtsi"
diff --git a/boards/kws/pico_spe/pico_spe.dts b/boards/kws/pico_spe/pico_spe.dts
new file mode 100644
index 00000000000..5a4e89ead58
--- /dev/null
+++ b/boards/kws/pico_spe/pico_spe.dts
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2024 KWS Computersysteme Gmbh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <freq.h>
+#include <raspberrypi/rpi_pico/rp2040.dtsi>
+#include <zephyr/dt-bindings/dma/rpi-pico-dma-rp2040.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/pwm/pwm.h>
+
+#include "pico_spe-pinctrl.dtsi"
+
+/ {
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,flash-controller = &ssi;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,code-partition = &code_partition;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led_0 {
+			gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
+			label = "LED";
+		};
+	};
+
+	pwm_leds {
+		compatible = "pwm-leds";
+		status = "disabled";
+
+		pwm_led0: pwm_led_0 {
+			pwms = <&pwm 9 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+			label = "PWM_LED";
+		};
+	};
+
+	aliases {
+		led0 = &led0;
+		pwm-led0 = &pwm_led0;
+		rtc = &rtc;
+		watchdog0 = &wdt0;
+	};
+
+	pico_header: connector {
+		compatible = "raspberrypi,pico-header";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpio0 0 0>,	/* GP0 */
+			<1 0 &gpio0 1 0>,	/* GP1 */
+			<2 0 &gpio0 2 0>,	/* GP2 */
+			<3 0 &gpio0 3 0>,	/* GP3 */
+			<4 0 &gpio0 4 0>,	/* GP4 */
+			<5 0 &gpio0 5 0>,	/* GP5 */
+			<6 0 &gpio0 6 0>,	/* GP6 */
+			<7 0 &gpio0 7 0>,	/* GP7 */
+			<8 0 &gpio0 8 0>,	/* GP8 */
+			<9 0 &gpio0 9 0>,	/* GP9 */
+			<10 0 &gpio0 10 0>,	/* GP10 */
+			<11 0 &gpio0 11 0>,	/* GP11 */
+			<12 0 &gpio0 12 0>,	/* GP12 */
+			<13 0 &gpio0 13 0>,	/* GP13 */
+			<14 0 &gpio0 14 0>,	/* GP14 */
+			<15 0 &gpio0 15 0>,	/* GP15 */
+			<16 0 &gpio0 16 0>,	/* GP16 */
+			<17 0 &gpio0 17 0>,	/* GP17 */
+			<18 0 &gpio0 18 0>,	/* GP18 */
+			<19 0 &gpio0 19 0>,	/* GP19 */
+			<20 0 &gpio0 20 0>,	/* GP20 */
+			<21 0 &gpio0 21 0>,	/* GP21 */
+			<22 0 &gpio0 22 0>,	/* GP22 */
+			<26 0 &gpio0 26 0>,	/* GP26 */
+			<27 0 &gpio0 27 0>,	/* GP27 */
+			<28 0 &gpio0 28 0>;	/* GP28 */
+	};
+};
+
+&flash0 {
+	reg = <0x10000000 DT_SIZE_M(2)>;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* Reserved memory for the second stage bootloader */
+		second_stage_bootloader: partition@0 {
+			label = "second_stage_bootloader";
+			reg = <0x00000000 0x100>;
+			read-only;
+		};
+
+		/*
+		 * Usable flash. Starts at 0x100, after the bootloader. The partition
+		 * size is 2MB minus the 0x100 bytes taken by the bootloader.
+		 */
+		code_partition: partition@100 {
+			label = "code-partition";
+			reg = <0x100 (DT_SIZE_M(2) - 0x100)>;
+			read-only;
+		};
+	};
+};
+
+&uart0 {
+	current-speed = <115200>;
+	status = "okay";
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-names = "default";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	status = "okay";
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+};
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_default>;
+	pinctrl-names = "default";
+	status = "disabled";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&spi1 {
+	clock-frequency = <DT_FREQ_M(25)>;
+	status = "okay";
+	pinctrl-0 = <&spi1_default>;
+		pinctrl-names = "default";
+	cs-gpios = <&pico_header 13 GPIO_ACTIVE_LOW>;
+
+	lan8651: lan865x@0 {
+		compatible = "microchip,lan865x";
+		reg = <0x0>;
+		spi-max-frequency = <DT_FREQ_M(25)>;
+		int-gpios = <&gpio0 21 (GPIO_ACTIVE_LOW)>;
+		rst-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+		status = "okay";
+		local-mac-address = [ CA 2F B7 10 23 78];
+
+		lan865x_mdio: lan865x_mdio {
+			compatible = "microchip,lan865x-mdio";
+			status = "okay";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ethernet-phy@0 {
+				compatible = "microchip,t1s-phy";
+				reg = <0x0>;
+				plca-enable;
+				plca-node-id = <0>;
+				plca-node-count = <8>;
+				plca-burst-count = <0>;
+				plca-burst-timer = <0x80>;
+				plca-to-timer = <0x20>;
+				status = "okay";
+			};
+		};
+	};
+};
+
+&timer {
+	status = "okay";
+};
+
+&wdt0 {
+	status = "okay";
+};
+
+&rtc {
+	clocks = <&clocks RPI_PICO_CLKID_CLK_RTC>;
+	status = "okay";
+};
+
+&adc {
+	status = "okay";
+	pinctrl-0 = <&adc_default>;
+	pinctrl-names = "default";
+};
+
+zephyr_udc0: &usbd {
+	status = "okay";
+};
+
+&pwm {
+	pinctrl-0 = <&pwm_ch4b_default>;
+	pinctrl-names = "default";
+};
+
+&vreg {
+	regulator-always-on;
+	regulator-allowed-modes = <REGULATOR_RPI_PICO_MODE_NORMAL>;
+};
+
+pico_spi: &spi1 {};
+pico_i2c0: &i2c0 {};
+pico_i2c1: &i2c1 {};
+pico_serial: &uart0 {};
diff --git a/boards/kws/pico_spe/pico_spe.yaml b/boards/kws/pico_spe/pico_spe.yaml
new file mode 100644
index 00000000000..c0b383270f5
--- /dev/null
+++ b/boards/kws/pico_spe/pico_spe.yaml
@@ -0,0 +1,23 @@
+identifier: pico_spe
+name: KWS Pico SinglePairEthernet
+type: mcu
+arch: arm
+flash: 2048
+ram: 264
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+supported:
+  - uart
+  - gpio
+  - adc
+  - i2c
+  - spi
+  - hwinfo
+  - watchdog
+  - pwm
+  - flash
+  - dma
+  - counter
+  - clock
diff --git a/boards/kws/pico_spe/pico_spe_defconfig b/boards/kws/pico_spe/pico_spe_defconfig
new file mode 100644
index 00000000000..df003531af9
--- /dev/null
+++ b/boards/kws/pico_spe/pico_spe_defconfig
@@ -0,0 +1,11 @@
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=125000000
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y
+CONFIG_USE_DT_CODE_PARTITION=y
+CONFIG_BUILD_OUTPUT_UF2=y
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_RESET=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/kws/pico_spe/support/openocd.cfg b/boards/kws/pico_spe/support/openocd.cfg
new file mode 100644
index 00000000000..34ab592b186
--- /dev/null
+++ b/boards/kws/pico_spe/support/openocd.cfg
@@ -0,0 +1,11 @@
+# Copyright (c) 2022 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+# Checking and set 'adapter speed'.
+# Set the adaptor speed, if unset, and given as an argument.
+proc set_adapter_speed_if_not_set { speed } {
+	puts "checking adapter speed..."
+	if { [catch {adapter speed} ret] } {
+		adapter speed $speed
+	}
+}
diff --git a/boards/lilygo/tdongle_s3/Kconfig b/boards/lilygo/tdongle_s3/Kconfig
new file mode 100644
index 00000000000..2da6bfecb7c
--- /dev/null
+++ b/boards/lilygo/tdongle_s3/Kconfig
@@ -0,0 +1,7 @@
+# Copyright (c) 2025 Stefan Golinschi <stefan.golinschi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+	int
+	default 4096 if BOARD_TDONGLE_S3_ESP32S3_PROCPU
+	default 256 if BOARD_TDONGLE_S3_ESP32S3_APPCPU
diff --git a/boards/lilygo/tdongle_s3/Kconfig.sysbuild b/boards/lilygo/tdongle_s3/Kconfig.sysbuild
new file mode 100644
index 00000000000..420778b68b2
--- /dev/null
+++ b/boards/lilygo/tdongle_s3/Kconfig.sysbuild
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Stefan Golinschi <stefan.golinschi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+choice BOOTLOADER
+	default BOOTLOADER_MCUBOOT
+endchoice
+
+choice BOOT_SIGNATURE_TYPE
+	default BOOT_SIGNATURE_TYPE_NONE
+endchoice
diff --git a/boards/lilygo/tdongle_s3/Kconfig.tdongle_s3 b/boards/lilygo/tdongle_s3/Kconfig.tdongle_s3
new file mode 100644
index 00000000000..12f013272e0
--- /dev/null
+++ b/boards/lilygo/tdongle_s3/Kconfig.tdongle_s3
@@ -0,0 +1,7 @@
+# Copyright (c) 2025 Stefan Golinschi <stefan.golinschi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_TDONGLE_S3
+	select SOC_ESP32S3_WROOM_N16R8
+	select SOC_ESP32S3_PROCPU if BOARD_TDONGLE_S3_ESP32S3_PROCPU
+	select SOC_ESP32S3_APPCPU if BOARD_TDONGLE_S3_ESP32S3_APPCPU
diff --git a/boards/lilygo/tdongle_s3/board.cmake b/boards/lilygo/tdongle_s3/board.cmake
new file mode 100644
index 00000000000..57d1a920ecd
--- /dev/null
+++ b/boards/lilygo/tdongle_s3/board.cmake
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Stefan Golinschi <stefan.golinschi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
+  set(OPENOCD OPENOCD-NOTFOUND)
+endif()
+find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
+
+include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/lilygo/tdongle_s3/board.yml b/boards/lilygo/tdongle_s3/board.yml
new file mode 100644
index 00000000000..ad92d0100c9
--- /dev/null
+++ b/boards/lilygo/tdongle_s3/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: tdongle_s3
+  full_name: T-Dongle S3
+  vendor: lilygo
+  socs:
+  - name: esp32s3
diff --git a/boards/lilygo/tdongle_s3/doc/img/tdongle_s3.webp b/boards/lilygo/tdongle_s3/doc/img/tdongle_s3.webp
new file mode 100644
index 00000000000..b970f6b1b8d
Binary files /dev/null and b/boards/lilygo/tdongle_s3/doc/img/tdongle_s3.webp differ
diff --git a/boards/lilygo/tdongle_s3/doc/index.rst b/boards/lilygo/tdongle_s3/doc/index.rst
new file mode 100644
index 00000000000..b90f5a21417
--- /dev/null
+++ b/boards/lilygo/tdongle_s3/doc/index.rst
@@ -0,0 +1,189 @@
+.. zephyr:board:: tdongle_s3
+
+Overview
+********
+
+Lilygo T-Dongle S3 is an IoT mini development board based on the
+Espressif ESP32-S3 WiFi/Bluetooth dual-mode chip.
+
+It features the following integrated components:
+
+- ESP32-S3 chip (240MHz dual core, Bluetooth 5, WiFi)
+- On-board antenna and IPEX connector
+- USB-A connector with integrated TF Card slot
+- MX 1.25mm 2-pin battery connector
+- APA102 RGB LED
+- JST SH 1.0mm 4-pin UART connector
+- Transparent plastic case
+
+Functional Description
+**********************
+This board is based on the ESP32-S3 with 16MB of flash, WiFi and BLE support. It
+has an USB-A port for programming and debugging, integrated battery charging
+and an on-board antenna. The fitted U.FL external antenna connector can be
+enabled by moving a 0-ohm resistor.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Start Application Development
+*****************************
+
+Before powering up your Lilygo T-Dongle T8-S3, please make sure that the board is in good
+condition with no obvious signs of damage.
+
+System requirements
+*******************
+
+Prerequisites
+=============
+
+Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
+below to retrieve those files.
+
+.. code-block:: console
+
+   west blobs fetch hal_espressif
+
+.. note::
+
+   It is recommended running the command above after :file:`west update`.
+
+Building & Flashing
+*******************
+
+.. zephyr:board-supported-runners::
+
+Simple boot
+===========
+
+The board could be loaded using a single binary image, without 2nd stage bootloader.
+It is the default option when building the application without additional configuration.
+
+.. note::
+
+   Simple boot does not provide any security features nor OTA updates.
+
+MCUboot bootloader
+==================
+
+User may choose to use MCUboot bootloader instead. In that case the bootloader
+must be built (and flashed) at least once.
+
+There are two options to be used when building an application:
+
+1. Sysbuild
+2. Manual build
+
+.. note::
+
+   User can select the MCUboot bootloader by adding the following line
+   to the board default configuration file.
+
+   .. code-block:: cfg
+
+      CONFIG_BOOTLOADER_MCUBOOT=y
+
+Sysbuild
+========
+
+The sysbuild makes it possible to build and flash all necessary images needed to
+bootstrap the board with the ESP32 SoC.
+
+To build the sample application using sysbuild use the command:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: samples/hello_world
+   :board: tdongle_s3/esp32s3/procpu
+   :goals: build
+   :west-args: --sysbuild
+   :compact:
+
+By default, the ESP32 sysbuild creates bootloader (MCUboot) and application
+images. But it can be configured to create other kind of images.
+
+Build directory structure created by sysbuild is different from traditional
+Zephyr build. Output is structured by the domain subdirectories:
+
+.. code-block::
+
+  build/
+  ├── hello_world
+  │   └── zephyr
+  │       ├── zephyr.elf
+  │       └── zephyr.bin
+  ├── mcuboot
+  │    └── zephyr
+  │       ├── zephyr.elf
+  │       └── zephyr.bin
+  └── domains.yaml
+
+.. note::
+
+   With ``--sysbuild`` option the bootloader will be re-build and re-flash
+   every time the pristine build is used.
+
+For more information about the system build please read the :ref:`sysbuild` documentation.
+
+Manual build
+============
+
+During the development cycle, it is intended to build & flash as quickly possible.
+For that reason, images can be built one at a time using traditional build.
+
+The instructions following are relevant for both manual build and sysbuild.
+The only difference is the structure of the build directory.
+
+.. note::
+
+   Remember that bootloader (MCUboot) needs to be flashed at least once.
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: tdongle_s3/esp32s3/procpu
+   :goals: build
+
+The usual ``flash`` target will work with the ``tdongle_s3`` board target.
+Here is an example for the :zephyr:code-sample:`hello_world`
+application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: tdongle_s3/esp32s3/procpu
+   :goals: flash
+
+The default baud rate for the Lilygo T-Dongle S3 is set to 1500000bps. If experiencing issues when flashing,
+try using different values by using ``--esp-baud-rate <BAUD>`` option during
+``west flash`` (e.g. ``west flash --esp-baud-rate 115200``).
+
+You can also open the serial monitor using the following command:
+
+.. code-block:: shell
+
+   west espressif monitor
+
+After the board has automatically reset and booted, you should see the following
+message in the monitor:
+
+.. code-block:: console
+
+   ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
+   Hello World! tdongle_s3/esp32s3/procpu
+
+References
+**********
+
+.. target-notes::
+
+.. _`Lilygo T-Dongle S3 schematic`: https://github.com/Xinyuan-LilyGO/T-Dongle-S3/blob/main/shcematic/T-Dongle-S3.pdf
+.. _`Lilygo github repo`: https://github.com/Xinyuan-LilyGO/T-Dongle-S3.git
+.. _`ESP32-S3 Datasheet`: https://github.com/Xinyuan-LilyGO/T-Dongle-S3/blob/main/doc/esp32-s3_datasheet_en.pdf
+.. _`ESP32-S3 Technical Reference Manual`: https://github.com/Xinyuan-LilyGO/T-Dongle-S3/blob/main/doc/esp32-s3_technical_reference_manual_en.pdf
+.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases
+.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/
diff --git a/boards/lilygo/tdongle_s3/support/openocd.cfg b/boards/lilygo/tdongle_s3/support/openocd.cfg
new file mode 100644
index 00000000000..0b2c4909fe0
--- /dev/null
+++ b/boards/lilygo/tdongle_s3/support/openocd.cfg
@@ -0,0 +1,7 @@
+set ESP_RTOS none
+set ESP32_ONLYCPU 1
+
+source [find interface/esp_usb_jtag.cfg]
+
+source [find target/esp32s3.cfg]
+adapter_khz 5000
diff --git a/boards/lilygo/tdongle_s3/tdongle_s3-pinctrl.dtsi b/boards/lilygo/tdongle_s3/tdongle_s3-pinctrl.dtsi
new file mode 100644
index 00000000000..a4bff2af2d2
--- /dev/null
+++ b/boards/lilygo/tdongle_s3/tdongle_s3-pinctrl.dtsi
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2025 Stefan Golinschi <stefan.golinschi@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
+#include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h>
+
+&pinctrl {
+	uart0_default: uart0_default {
+		group1 {
+			pinmux = <UART0_TX_GPIO43>;
+			output-high;
+		};
+
+		group2 {
+			pinmux = <UART0_RX_GPIO44>;
+			bias-pull-up;
+		};
+	};
+
+	spim2_default: spim2_default {
+		group1 {
+			pinmux = <SPIM2_SCLK_GPIO5>,
+					 <SPIM2_CSEL_GPIO4>,
+					 <SPIM2_MOSI_GPIO3>;
+		};
+	};
+
+	spim3_default: spim3_default {
+		group1 {
+			pinmux = <SPIM3_SCLK_GPIO39>,
+					 <SPIM3_MOSI_GPIO40>;
+		};
+	};
+
+	sdhc0_default: sdhc0_default {
+		group1 {
+			pinmux = <SDHC0_CLKOUT_GPIO12>,
+					 <SDHC0_CMD_GPIO16>,
+					 <SDHC0_DATA0_GPIO14>,
+					 <SDHC0_DATA1_GPIO17>,
+					 <SDHC0_DATA2_GPIO21>,
+					 <SDHC0_DATA3_GPIO18>;
+			bias-pull-up;
+			output-high;
+		};
+	};
+};
diff --git a/boards/lilygo/tdongle_s3/tdongle_s3_appcpu.dts b/boards/lilygo/tdongle_s3/tdongle_s3_appcpu.dts
new file mode 100644
index 00000000000..2d2422e11a9
--- /dev/null
+++ b/boards/lilygo/tdongle_s3/tdongle_s3_appcpu.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2025 Stefan Golinschi <stefan.golinschi@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <espressif/esp32s3/esp32s3_appcpu.dtsi>
+#include <espressif/partitions_0x0_amp.dtsi>
+
+/ {
+	model = "TDONGLE S3 APPCPU";
+	compatible = "espressif,esp32s3";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,ipc_shm = &shm0;
+		zephyr,ipc = &ipm0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_appcpu_partition;
+	};
+};
+
+&flash0 {
+	reg = <0x0 DT_SIZE_M(4)>;
+};
+
+&trng0 {
+	status = "okay";
+};
+
+&ipm0 {
+	status = "okay";
+};
diff --git a/boards/lilygo/tdongle_s3/tdongle_s3_appcpu.yaml b/boards/lilygo/tdongle_s3/tdongle_s3_appcpu.yaml
new file mode 100644
index 00000000000..b9bea7145c3
--- /dev/null
+++ b/boards/lilygo/tdongle_s3/tdongle_s3_appcpu.yaml
@@ -0,0 +1,27 @@
+identifier: tdongle_s3/esp32s3/appcpu
+name: LILYGO T-DONGLE S3 APPCPU
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+supported:
+  - uart
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+    - flash
+    - cpp
+    - posix
+    - watchdog
+    - logging
+    - kernel
+    - pm
+    - gpio
+    - crypto
+    - eeprom
+    - heap
+    - cmsis_rtos
+    - jwt
+    - zdsp
+vendor: lilygo
diff --git a/boards/lilygo/tdongle_s3/tdongle_s3_appcpu_defconfig b/boards/lilygo/tdongle_s3/tdongle_s3_appcpu_defconfig
new file mode 100644
index 00000000000..6087787aad3
--- /dev/null
+++ b/boards/lilygo/tdongle_s3/tdongle_s3_appcpu_defconfig
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Stefan Golinschi <stefan.golinschi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/lilygo/tdongle_s3/tdongle_s3_procpu.dts b/boards/lilygo/tdongle_s3/tdongle_s3_procpu.dts
new file mode 100644
index 00000000000..d325c30273b
--- /dev/null
+++ b/boards/lilygo/tdongle_s3/tdongle_s3_procpu.dts
@@ -0,0 +1,160 @@
+/*
+ * Copyright 2025 Stefan Golinschi <stefan.golinschi@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <espressif/esp32s3/esp32s3_wroom_n16r8.dtsi>
+#include "tdongle_s3-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
+#include <espressif/partitions_0x0_amp.dtsi>
+#include <zephyr/dt-bindings/led/led.h>
+
+/ {
+	model = "TDONGLE S3 PROCPU";
+	compatible = "espressif,esp32s3";
+
+	aliases {
+		watchdog0 = &wdt0;
+		sdhc0 = &sdhc0;
+		uart-0 = &uart0;
+		sw0 = &button0;
+		led-strip = &apa102;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		/* console can be UART or USB CDC */
+		/* zephyr,console = &uart0; */
+		/* zephyr,shell-uart = &uart0; */
+		zephyr,console = &usb_serial;
+		zephyr,shell-uart = &usb_serial;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,bt-hci = &esp32_bt_hci;
+		zephyr,display = &st7735r;
+		zephyr,sdhc = &sdhc0;
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+		status = "okay";
+
+		button0: button_0 {
+			gpios = <&gpio0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "BOOT Button";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	mipi_dbi {
+		compatible = "zephyr,mipi-dbi-spi";
+		/* Enable D/C line for 4wire mode */
+		dc-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+		spi-dev = <&spi2>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		write-only;
+		status = "okay";
+
+		st7735r: st7735r@0 {
+			compatible = "sitronix,st7735r";
+			mipi-max-frequency = <20000000>;
+			mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE";
+			reg = <0>;
+			width = <160>;
+			height = <80>;
+			inversion-on;
+			rgb-is-inverted;
+			madctl = <0xBE>;
+			x-offset = <1>;
+			y-offset = <26>;
+			gamctrp1 = [02 1c 07 12 37 32 29 2d 29 25 2B 39 00 01 03 10];
+			gamctrn1 = [03 1d 07 06 2E 2C 29 2D 2E 2E 37 3F 00 00 02 10];
+			te-delay = <0x0A>;
+			vmctr1 = <0x0E>;
+			colmod = <0x05>;
+			caset = [00 02 00 81];
+			raset = [00 01 00 A0];
+			status = "okay";
+		};
+	};
+};
+
+&uart0 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&spi2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	cs-gpios = <&gpio0 4 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spim2_default>;
+	pinctrl-names = "default";
+	clock-frequency = <20000000>;
+	status = "okay";
+};
+
+&spi3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-0 = <&spim3_default>;
+	pinctrl-names = "default";
+	clock-frequency = <20000000>;
+	status = "okay";
+
+	apa102: apa102@0 {
+		compatible = "apa,apa102";
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+		chain-length = <1>;
+		color-mapping = <LED_COLOR_ID_RED
+						 LED_COLOR_ID_BLUE
+						 LED_COLOR_ID_GREEN>;
+		status = "okay";
+	};
+};
+
+&usb_serial {
+	status = "okay";
+};
+
+&timer0 {
+	status = "okay";
+};
+
+&wdt0 {
+	status = "okay";
+};
+
+&trng0 {
+	status = "okay";
+};
+
+&esp32_bt_hci {
+	status = "okay";
+};
+
+&sdhc {
+	sdhc0: sdhc@0 {
+		pinctrl-0 = <&sdhc0_default>;
+		pinctrl-names = "default";
+		power-delay-ms = <100>;
+		max-bus-freq = <52000000>;
+		bus-width = <4>;
+		status = "okay";
+
+		mmc {
+			compatible = "zephyr,sdmmc-disk";
+			disk-name = "SD";
+			status = "okay";
+		};
+	};
+};
diff --git a/boards/lilygo/tdongle_s3/tdongle_s3_procpu.yaml b/boards/lilygo/tdongle_s3/tdongle_s3_procpu.yaml
new file mode 100644
index 00000000000..5b01812a0bf
--- /dev/null
+++ b/boards/lilygo/tdongle_s3/tdongle_s3_procpu.yaml
@@ -0,0 +1,22 @@
+identifier: tdongle_s3/esp32s3/procpu
+name: TDONGLE S3 PROCPU
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+supported:
+  - gpio
+  - uart
+  - i2c
+  - i2s
+  - spi
+  - can
+  - counter
+  - watchdog
+  - entropy
+  - pwm
+  - dma
+  - input
+  - video
+  - display
+vendor: lilygo
diff --git a/boards/lilygo/tdongle_s3/tdongle_s3_procpu_defconfig b/boards/lilygo/tdongle_s3/tdongle_s3_procpu_defconfig
new file mode 100644
index 00000000000..fbb8fd6b910
--- /dev/null
+++ b/boards/lilygo/tdongle_s3/tdongle_s3_procpu_defconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Stefan Golinschi <stefan.golinschi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/lilygo/ttgo_lora32/doc/index.rst b/boards/lilygo/ttgo_lora32/doc/index.rst
index fa6613d7414..1b662bb030c 100644
--- a/boards/lilygo/ttgo_lora32/doc/index.rst
+++ b/boards/lilygo/ttgo_lora32/doc/index.rst
@@ -15,39 +15,13 @@ It's available in two versions supporting two different frequency ranges and fea
 
 Some of the ESP32 I/O pins are accessible on the board's pin headers.
 
-Functional Description
-**********************
-
-The following table below describes the key components, interfaces, and controls
-of the Lilygo TTGO LoRa32 board.
-
-.. _SX127x: https://www.semtech.com/products/wireless-rf/lora-connect/sx1276#documentation
-.. _ESP32-PICO-D4: https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf
-.. _SSD1306: https://cdn-shop.adafruit.com/datasheets/SSD1306.pdf
-
-+------------------+-------------------------------------------------------------------------+
-| Key Component    | Description                                                             |
-+==================+=========================================================================+
-| ESP32-PICO-D4    | This `ESP32-PICO-D4`_ module provides complete Wi-Fi and Bluetooth      |
-|                  | functionalities and integrates a 4-MB SPI flash.                        |
-+------------------+-------------------------------------------------------------------------+
-| Diagnostic LED   | One user LED connected to the GPIO pin.                                 |
-+------------------+-------------------------------------------------------------------------+
-| USB Port         | USB interface. Power supply for the board as well as the                |
-|                  | serial communication interface between a computer and the board.        |
-|                  | Micro-USB type connector.                                               |
-+------------------+-------------------------------------------------------------------------+
-| Power Switch     | Sliding power switch.                                                   |
-+------------------+-------------------------------------------------------------------------+
-| OLED display     | Built-in OLED display \(`SSD1306`_, 0.96", 128x64 px\) controlled       |
-|                  | by I2C interface                                                        |
-+------------------+-------------------------------------------------------------------------+
-| SX1276/SX1278    | LoRa radio frontend chip, connected via SPI.                            |
-|                  | Use SX1276 for 433MHz and SX1276 for 868/915/923MHz.                    |
-+------------------+-------------------------------------------------------------------------+
-| TF card slot     | TF card slot wired to the SDHC interface of the MCU.                    |
-+------------------+-------------------------------------------------------------------------+
+Hardware
+********
+
+Supported Features
+==================
 
+.. zephyr:board-supported-hw::
 
 Start Application Development
 *****************************
@@ -61,7 +35,7 @@ System requirements
 Prerequisites
 =============
 
-Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
+Espressif HAL requires WiFi and Bluetooth binary blobs in order to work. Run the command
 below to retrieve those files.
 
 .. code-block:: console
@@ -75,10 +49,12 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
-The board could be loaded using the single binary image, without 2nd stage bootloader.
+The board could be loaded using a single binary image, without 2nd stage bootloader.
 It is the default option when building the application without additional configuration.
 
 .. note::
@@ -108,7 +84,7 @@ There are two options to be used when building an application:
 Sysbuild
 ========
 
-The sysbuild makes possible to build and flash all necessary images needed to
+The sysbuild makes it possible to build and flash all necessary images needed to
 bootstrap the board with the ESP32-PICO-D4 SoC.
 
 To build the sample application using sysbuild use the command:
@@ -193,7 +169,7 @@ message in the monitor:
 .. code-block:: console
 
    ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
-   Hello World! ttgo_lora32
+   Hello World! ttgo_lora32/esp32/procpu
 
 Code samples
 ============
@@ -218,3 +194,5 @@ Related Documents
 - `ESP32-PICO-D4 Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf>`_ (PDF)
 - `ESP32 Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf>`_ (PDF)
 - `ESP32 Hardware Reference <https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html>`_
+- `SX127x Datasheet <https://www.semtech.com/products/wireless-rf/lora-connect/sx1276#documentation>`_
+- `SSD1306 Datasheet <https://cdn-shop.adafruit.com/datasheets/SSD1306.pdf>`_ (PDF)
diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu_defconfig b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu_defconfig
+++ b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts
index 6ae0dbeb015..42c3391f387 100644
--- a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts
+++ b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu.dts
@@ -148,3 +148,7 @@
 		};
 	};
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu_defconfig b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu_defconfig
index e18641b5d44..8dcf3d7e54b 100644
--- a/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu_defconfig
+++ b/boards/lilygo/ttgo_lora32/ttgo_lora32_esp32_procpu_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/lilygo/ttgo_t7v1_5/board.yml b/boards/lilygo/ttgo_t7v1_5/board.yml
index 0a3f7198646..5912db5520c 100644
--- a/boards/lilygo/ttgo_t7v1_5/board.yml
+++ b/boards/lilygo/ttgo_t7v1_5/board.yml
@@ -1,5 +1,6 @@
 board:
   name: ttgo_t7v1_5
+  full_name: TTGO T7 Mini32 V1.5
   vendor: lilygo
   socs:
   - name: esp32
diff --git a/boards/lilygo/ttgo_t7v1_5/doc/index.rst b/boards/lilygo/ttgo_t7v1_5/doc/index.rst
index 13f5107cd80..57d12645c9a 100644
--- a/boards/lilygo/ttgo_t7v1_5/doc/index.rst
+++ b/boards/lilygo/ttgo_t7v1_5/doc/index.rst
@@ -13,38 +13,17 @@ It features the following integrated components:
 - JST GH 2-pin battery connector
 - LED
 
-Functional Description
-**********************
+Hardware
+********
+
 This board is based on the ESP32-WROVER-E module with 4MB of flash (there
 are models 16MB as well), WiFi and BLE support. It has a Micro-USB port for
 programming and debugging, integrated battery charging and an on-board antenna.
 
-Connections and IOs
-===================
+Supported Features
+==================
 
-The ``ttgo_t7v1_5/esp32/procpu`` board target supports the following hardware features:
-
-+-----------+------------+------------------+
-| Interface | Controller | Driver/Component |
-+===========+============+==================+
-| CPU       | ESP32      | arch/xtensa      |
-+-----------+------------+------------------+
-| GPIO      | on-chip    | gpio_esp32       |
-+-----------+------------+------------------+
-| UART      | on-chip    | uart_esp32       |
-+-----------+------------+------------------+
-| I2C       | on-chip    | i2c_esp32        |
-+-----------+------------+------------------+
-| SPI       | on-chip    | spi_esp32_spim   |
-+-----------+------------+------------------+
-| LoRa      | SX1276     | lora_sx127x      |
-+-----------+------------+------------------+
-| WiFi      | on-chip    | wifi_esp32       |
-+-----------+------------+------------------+
-| BLE       | on-chip    | bluetooth_esp32  |
-+-----------+------------+------------------+
-| Flash     | on-chip    | flash_esp32      |
-+-----------+------------+------------------+
+.. zephyr:board-supported-hw::
 
 System requirements
 *******************
@@ -52,7 +31,7 @@ System requirements
 Prerequisites
 =============
 
-Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
+Espressif HAL requires WiFi and Bluetooth binary blobs in order to work. Run the command
 below to retrieve those files.
 
 .. code-block:: console
@@ -66,10 +45,12 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
-The board could be loaded using the single binary image, without 2nd stage bootloader.
+The board could be loaded using a single binary image, without 2nd stage bootloader.
 It is the default option when building the application without additional configuration.
 
 .. note::
@@ -80,7 +61,7 @@ MCUboot bootloader
 ==================
 
 User may choose to use MCUboot bootloader instead. In that case the bootloader
-must be build (and flash) at least once.
+must be built (and flashed) at least once.
 
 There are two options to be used when building an application:
 
@@ -92,14 +73,14 @@ There are two options to be used when building an application:
    User can select the MCUboot bootloader by adding the following line
    to the board default configuration file.
 
-   .. code:: cfg
+   .. code-block:: cfg
 
       CONFIG_BOOTLOADER_MCUBOOT=y
 
 Sysbuild
 ========
 
-The sysbuild makes possible to build and flash all necessary images needed to
+The sysbuild makes it possible to build and flash all necessary images needed to
 bootstrap the board with the ESP32 SoC.
 
 To build the sample application using sysbuild use the command:
@@ -142,7 +123,7 @@ Manual build
 ============
 
 During the development cycle, it is intended to build & flash as quickly possible.
-For that reason, images can be build one at a time using traditional build.
+For that reason, images can be built one at a time using traditional build.
 
 The instructions following are relevant for both manual build and sysbuild.
 The only difference is the structure of the build directory.
diff --git a/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_appcpu.dts b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_appcpu.dts
index baca8424861..d61269a1d52 100644
--- a/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_appcpu.dts
+++ b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_appcpu.dts
@@ -13,7 +13,7 @@
 	compatible = "espressif,esp32";
 
 	chosen {
-		zephyr,sram = &sram0;
+		zephyr,sram = &sram1;
 		zephyr,ipc_shm = &shm0;
 		zephyr,ipc = &ipm0;
 		zephyr,flash = &flash0;
diff --git a/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_appcpu_defconfig b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_appcpu_defconfig
+++ b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_procpu.dts b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_procpu.dts
index 4fab0e2ae72..735ba0a8c52 100644
--- a/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_procpu.dts
+++ b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_procpu.dts
@@ -22,7 +22,7 @@
 	};
 
 	chosen {
-		zephyr,sram = &sram0;
+		zephyr,sram = &sram1;
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
 		zephyr,flash = &flash0;
diff --git a/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_procpu_defconfig b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_procpu_defconfig
index f029cac9e9e..e192c240251 100644
--- a/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_procpu_defconfig
+++ b/boards/lilygo/ttgo_t7v1_5/ttgo_t7v1_5_esp32_procpu_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/lilygo/ttgo_t8c3/doc/index.rst b/boards/lilygo/ttgo_t8c3/doc/index.rst
index 4179528b6af..33cab641524 100644
--- a/boards/lilygo/ttgo_t8c3/doc/index.rst
+++ b/boards/lilygo/ttgo_t8c3/doc/index.rst
@@ -14,39 +14,18 @@ It features the following integrated components:
 - JST GH 2-pin battery connector
 - LED
 
-Functional Description
-**********************
+Hardware
+********
+
 This board is based on the ESP32-C3 with 4MB of flash, WiFi and BLE support. It
 has an USB-C port for programming and debugging, integrated battery charging
 and an on-board antenna. The fitted U.FL external antenna connector can be
 enabled by moving a 0-ohm resistor.
 
-Connections and IOs
-===================
+Supported Features
+==================
 
-The ``ttgo_t8c3`` board target supports the following hardware features:
-
-+-----------+------------+------------------+
-| Interface | Controller | Driver/Component |
-+===========+============+==================+
-| PMP       | on-chip    | arch/riscv       |
-+-----------+------------+------------------+
-| INTMTRX   | on-chip    | intc_esp32c3     |
-+-----------+------------+------------------+
-| PINMUX    | on-chip    | pinctrl_esp32    |
-+-----------+------------+------------------+
-| USB UART  | on-chip    | serial_esp32_usb |
-+-----------+------------+------------------+
-| GPIO      | on-chip    | gpio_esp32       |
-+-----------+------------+------------------+
-| UART      | on-chip    | uart_esp32       |
-+-----------+------------+------------------+
-| I2C       | on-chip    | i2c_esp32        |
-+-----------+------------+------------------+
-| SPI       | on-chip    | spi_esp32_spim   |
-+-----------+------------+------------------+
-| TWAI      | on-chip    | can_esp32_twai   |
-+-----------+------------+------------------+
+.. zephyr:board-supported-hw::
 
 Start Application Development
 *****************************
@@ -60,7 +39,7 @@ System requirements
 Prerequisites
 =============
 
-Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
+Espressif HAL requires WiFi and Bluetooth binary blobs in order to work. Run the command
 below to retrieve those files.
 
 .. code-block:: console
@@ -74,10 +53,12 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
-The board could be loaded using the single binary image, without 2nd stage bootloader.
+The board could be loaded using a single binary image, without 2nd stage bootloader.
 It is the default option when building the application without additional configuration.
 
 .. note::
@@ -107,7 +88,7 @@ There are two options to be used when building an application:
 Sysbuild
 ========
 
-The sysbuild makes possible to build and flash all necessary images needed to
+The sysbuild makes it possible to build and flash all necessary images needed to
 bootstrap the board with the ESP32-C3 SoC.
 
 To build the sample application using sysbuild use the command:
diff --git a/boards/lilygo/ttgo_t8c3/ttgo_t8c3_defconfig b/boards/lilygo/ttgo_t8c3/ttgo_t8c3_defconfig
index ef633ce56a1..187793c76e8 100644
--- a/boards/lilygo/ttgo_t8c3/ttgo_t8c3_defconfig
+++ b/boards/lilygo/ttgo_t8c3/ttgo_t8c3_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/lilygo/ttgo_t8s3/doc/index.rst b/boards/lilygo/ttgo_t8s3/doc/index.rst
index 09455ed19a6..fb29b2e5f7b 100644
--- a/boards/lilygo/ttgo_t8s3/doc/index.rst
+++ b/boards/lilygo/ttgo_t8s3/doc/index.rst
@@ -15,51 +15,18 @@ It features the following integrated components:
 - JST SH 1.0mm 4-pin UART connector
 - SD card slot
 
-Functional Description
-**********************
+Hardware
+********
+
 This board is based on the ESP32-S3 with 16MB of flash, WiFi and BLE support. It
 has an USB-C port for programming and debugging, integrated battery charging
 and an on-board antenna. The fitted U.FL external antenna connector can be
 enabled by moving a 0-ohm resistor.
 
-Connections and IOs
-===================
-
-The ``ttgo_t8s3`` board target supports the following hardware features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi, sdmmc                          |
-+------------+------------+-------------------------------------+
-| TWAI/CAN   | on-chip    | can                                 |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | adc                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| MCPWM      | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| PCNT       | on-chip    | qdec                                |
-+------------+------------+-------------------------------------+
-| GDMA       | on-chip    | dma                                 |
-+------------+------------+-------------------------------------+
-| USB-CDC    | on-chip    | serial                              |
-+------------+------------+-------------------------------------+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
 
 Start Application Development
 *****************************
@@ -73,7 +40,7 @@ System requirements
 Prerequisites
 =============
 
-Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
+Espressif HAL requires WiFi and Bluetooth binary blobs in order to work. Run the command
 below to retrieve those files.
 
 .. code-block:: console
@@ -87,10 +54,12 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
-The board could be loaded using the single binary image, without 2nd stage bootloader.
+The board could be loaded using a single binary image, without 2nd stage bootloader.
 It is the default option when building the application without additional configuration.
 
 .. note::
@@ -120,7 +89,7 @@ There are two options to be used when building an application:
 Sysbuild
 ========
 
-The sysbuild makes possible to build and flash all necessary images needed to
+The sysbuild makes it possible to build and flash all necessary images needed to
 bootstrap the board with the ESP32 SoC.
 
 To build the sample application using sysbuild use the command:
diff --git a/boards/lilygo/ttgo_t8s3/ttgo_t8s3_appcpu_defconfig b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/lilygo/ttgo_t8s3/ttgo_t8s3_appcpu_defconfig
+++ b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu.dts b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu.dts
index a034a9cb49a..0bc8b847092 100644
--- a/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu.dts
+++ b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu.dts
@@ -144,3 +144,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu_defconfig b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu_defconfig
index 723de34c471..d8fbaa87925 100644
--- a/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu_defconfig
+++ b/boards/lilygo/ttgo_t8s3/ttgo_t8s3_procpu_defconfig
@@ -1,6 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/lilygo/ttgo_tbeam/Kconfig b/boards/lilygo/ttgo_tbeam/Kconfig
new file mode 100644
index 00000000000..c52379f257a
--- /dev/null
+++ b/boards/lilygo/ttgo_tbeam/Kconfig
@@ -0,0 +1,7 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+	int
+	default 4096 if BOARD_TTGO_TBEAM_ESP32_PROCPU
+	default 256 if BOARD_TTGO_TBEAM_ESP32_APPCPU
diff --git a/boards/lilygo/ttgo_tbeam/Kconfig.sysbuild b/boards/lilygo/ttgo_tbeam/Kconfig.sysbuild
new file mode 100644
index 00000000000..3a2d17ac5cf
--- /dev/null
+++ b/boards/lilygo/ttgo_tbeam/Kconfig.sysbuild
@@ -0,0 +1,10 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+choice BOOTLOADER
+	default BOOTLOADER_MCUBOOT
+endchoice
+
+choice BOOT_SIGNATURE_TYPE
+	default BOOT_SIGNATURE_TYPE_NONE
+endchoice
diff --git a/boards/lilygo/ttgo_tbeam/Kconfig.ttgo_tbeam b/boards/lilygo/ttgo_tbeam/Kconfig.ttgo_tbeam
new file mode 100644
index 00000000000..3b3202cf8e4
--- /dev/null
+++ b/boards/lilygo/ttgo_tbeam/Kconfig.ttgo_tbeam
@@ -0,0 +1,7 @@
+# Copyright (c) 2024 Lothar Felten <lothar.felten@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_TTGO_TBEAM
+	select SOC_ESP32_PICO_D4
+	select SOC_ESP32_PROCPU if BOARD_TTGO_TBEAM_ESP32_PROCPU
+	select SOC_ESP32_APPCPU if BOARD_TTGO_TBEAM_ESP32_APPCPU
diff --git a/boards/lilygo/ttgo_tbeam/board.cmake b/boards/lilygo/ttgo_tbeam/board.cmake
new file mode 100644
index 00000000000..91b3caa2c75
--- /dev/null
+++ b/boards/lilygo/ttgo_tbeam/board.cmake
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
+  set(OPENOCD OPENOCD-NOTFOUND)
+endif()
+find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
+
+include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+
+# the default ESP32 baud rate is not supported
+board_runner_args(esp32 "--esp-baud-rate=1500000")
diff --git a/boards/lilygo/ttgo_tbeam/board.yml b/boards/lilygo/ttgo_tbeam/board.yml
new file mode 100644
index 00000000000..fad0e34cdca
--- /dev/null
+++ b/boards/lilygo/ttgo_tbeam/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: ttgo_tbeam
+  full_name: TTGO TBeam
+  vendor: lilygo
+  socs:
+  - name: esp32
diff --git a/boards/lilygo/ttgo_tbeam/doc/img/ttgo_tbeam.webp b/boards/lilygo/ttgo_tbeam/doc/img/ttgo_tbeam.webp
new file mode 100644
index 00000000000..eb488921e4a
Binary files /dev/null and b/boards/lilygo/ttgo_tbeam/doc/img/ttgo_tbeam.webp differ
diff --git a/boards/lilygo/ttgo_tbeam/doc/index.rst b/boards/lilygo/ttgo_tbeam/doc/index.rst
new file mode 100644
index 00000000000..fa6082abaa2
--- /dev/null
+++ b/boards/lilygo/ttgo_tbeam/doc/index.rst
@@ -0,0 +1,204 @@
+.. zephyr:board:: ttgo_tbeam
+
+Overview
+********
+
+The Lilygo TTGO TBeam, is an ESP32-based development board for LoRa applications.
+
+It's available in two versions supporting two different frequency ranges and features the following integrated components:
+
+- ESP32-PICO-D4 chip (240MHz dual core, 600 DMIPS, 520KB SRAM, Wi-Fi)
+- SSD1306, 128x64 px, 0.96" screen (optional)
+- SX1278 (433MHz) or SX1276 (868/915/923MHz) LoRa radio frontend (optional, with SMA or IPEX connector)
+- NEO-6M or NEO-M8N GNSS module
+- X-Powers AXP2101 PMIC
+- JST GH 2-pin battery connector
+- 18650 Li-Ion battery clip
+
+Some of the ESP32 I/O pins are accessible on the board's pin headers.
+
+Hardware
+********
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Start Application Development
+*****************************
+
+Before powering up your Lilygo TTGO TBeam, please make sure that the board is in good
+condition with no obvious signs of damage.
+
+System requirements
+*******************
+
+Prerequisites
+=============
+
+Espressif HAL requires WiFi and Bluetooth binary blobs in order to work. Run the command
+below to retrieve those files.
+
+.. code-block:: console
+
+   west blobs fetch hal_espressif
+
+.. note::
+
+   It is recommended running the command above after :file:`west update`.
+
+Building & Flashing
+*******************
+
+.. zephyr:board-supported-runners::
+
+Simple boot
+===========
+
+The board could be loaded using a single binary image, without 2nd stage bootloader.
+It is the default option when building the application without additional configuration.
+
+.. note::
+
+   Simple boot does not provide any security features nor OTA updates.
+
+MCUboot bootloader
+==================
+
+User may choose to use MCUboot bootloader instead. In that case the bootloader
+must be built (and flashed) at least once.
+
+There are two options to be used when building an application:
+
+1. Sysbuild
+2. Manual build
+
+.. note::
+
+   User can select the MCUboot bootloader by adding the following line
+   to the board default configuration file.
+
+   .. code-block:: cfg
+
+      CONFIG_BOOTLOADER_MCUBOOT=y
+
+Sysbuild
+========
+
+The sysbuild makes it possible to build and flash all necessary images needed to
+bootstrap the board with the ESP32-PICO-D4 SoC.
+
+To build the sample application using sysbuild use the command:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: samples/hello_world
+   :board: ttgo_tbeam/esp32/procpu
+   :goals: build
+   :west-args: --sysbuild
+   :compact:
+
+By default, the ESP32-PICO-D4 sysbuild creates bootloader (MCUboot) and application
+images. But it can be configured to create other kind of images.
+
+Build directory structure created by sysbuild is different from traditional
+Zephyr build. Output is structured by the domain subdirectories:
+
+.. code-block::
+
+  build/
+  ├── hello_world
+  │   └── zephyr
+  │       ├── zephyr.elf
+  │       └── zephyr.bin
+  ├── mcuboot
+  │    └── zephyr
+  │       ├── zephyr.elf
+  │       └── zephyr.bin
+  └── domains.yaml
+
+.. note::
+
+   With ``--sysbuild`` option the bootloader will be re-build and re-flash
+   every time the pristine build is used.
+
+For more information about the system build please read the :ref:`sysbuild` documentation.
+
+Manual build
+============
+
+During the development cycle, it is intended to build & flash as quickly possible.
+For that reason, images can be built one at a time using traditional build.
+
+The instructions following are relevant for both manual build and sysbuild.
+The only difference is the structure of the build directory.
+
+.. note::
+
+   Remember that bootloader (MCUboot) needs to be flash at least once.
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: ttgo_tbeam/esp32/procpu
+   :goals: build
+
+The usual ``flash`` target will work with the ``ttgo_tbeam`` board target.
+Here is an example for the :zephyr:code-sample:`hello_world`
+application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: ttgo_tbeam/esp32/procpu
+   :goals: flash
+
+The default baud rate for the Lilygo TTGO TBeam is set to 1500000bps. If experiencing issues when flashing,
+try using different values by using ``--esp-baud-rate <BAUD>`` option during
+``west flash`` (e.g. ``west flash --esp-baud-rate 115200``).
+
+You can also open the serial monitor using the following command:
+
+.. code-block:: shell
+
+   west espressif monitor
+
+After the board has automatically reset and booted, you should see the following
+message in the monitor:
+
+.. code-block:: console
+
+   ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
+   Hello World! ttgo_tbeam/esp32/procpu
+
+Code samples
+============
+
+The following sample applications will work out of the box with this board:
+
+* :zephyr:code-sample:`lora-send`
+* :zephyr:code-sample:`lora-receive`
+* :zephyr:code-sample:`gnss`
+* :zephyr:code-sample:`wifi-shell`
+* :zephyr:code-sample:`character-frame-buffer`
+* :zephyr:code-sample:`blinky`
+
+Debugging
+*********
+
+Lilygo TTGO TBeam debugging is not supported due to pinout limitations.
+
+Related Documents
+*****************
+- `Lilygo TTGO TBeam schematic <https://github.com/Xinyuan-LilyGO/LilyGo-LoRa-Series/blob/master/schematic/LilyGo_TBeam_V1.2.pdf>`_ (PDF)
+- `Lilygo TTGO TBeam documentation <https://www.lilygo.cc/products/t-beam-v1-1-esp32-lora-module>`_
+- `Lilygo github repo <https://github.com/Xinyuan-LilyGo>`_
+- `ESP32-PICO-D4 Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32-pico-d4_datasheet_en.pdf>`_ (PDF)
+- `ESP32 Datasheet <https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf>`_ (PDF)
+- `ESP32 Hardware Reference <https://docs.espressif.com/projects/esp-idf/en/latest/esp32/hw-reference/index.html>`_
+- `SX127x Datasheet <https://www.semtech.com/products/wireless-rf/lora-connect/sx1276#documentation>`_
+- `SSD1306 Datasheet <https://cdn-shop.adafruit.com/datasheets/SSD1306.pdf>`_ (PDF)
+- `NEO-6M Datasheet <https://content.u-blox.com/sites/default/files/products/documents/NEO-6_DataSheet_%28GPS.G6-HW-09005%29.pdf>`_ (PDF)
+- `NEO-N8M Datasheet <https://content.u-blox.com/sites/default/files/NEO-M8-FW3_DataSheet_UBX-15031086.pdf>`_ (PDF)
diff --git a/boards/lilygo/ttgo_tbeam/support/openocd.cfg b/boards/lilygo/ttgo_tbeam/support/openocd.cfg
new file mode 100644
index 00000000000..338e6e4e6ea
--- /dev/null
+++ b/boards/lilygo/ttgo_tbeam/support/openocd.cfg
@@ -0,0 +1,5 @@
+set ESP_RTOS none
+set ESP32_ONLYCPU 1
+
+source [find interface/ftdi/esp32_devkitj_v1.cfg]
+source [find target/esp32.cfg]
diff --git a/boards/lilygo/ttgo_tbeam/ttgo_tbeam-pinctrl.dtsi b/boards/lilygo/ttgo_tbeam/ttgo_tbeam-pinctrl.dtsi
new file mode 100644
index 00000000000..a8a93a72bf8
--- /dev/null
+++ b/boards/lilygo/ttgo_tbeam/ttgo_tbeam-pinctrl.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2024 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
+#include <dt-bindings/pinctrl/esp32-pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/esp32-gpio-sigmap.h>
+
+&pinctrl {
+	uart0_default: uart0_default {
+		group1 {
+			pinmux = <UART0_TX_GPIO1>;
+			output-high;
+		};
+
+		group2 {
+			pinmux = <UART0_RX_GPIO3>;
+			bias-pull-up;
+		};
+	};
+
+	uart1_default: uart1_default {
+		group1 {
+			pinmux = <UART1_TX_GPIO12>;
+			output-high;
+		};
+
+		group2 {
+			pinmux = <UART1_RX_GPIO34>;
+			bias-pull-up;
+		};
+	};
+
+	spim3_default: spim3_default {
+		group1 {
+			pinmux = <SPIM3_MISO_GPIO19>,
+				 <SPIM3_SCLK_GPIO5>;
+		};
+
+		group2 {
+			pinmux = <SPIM3_MOSI_GPIO27>;
+			output-low;
+		};
+	};
+
+	i2c0_default: i2c0_default {
+		group1 {
+			pinmux = <I2C0_SDA_GPIO21>,
+				 <I2C0_SCL_GPIO22>;
+			bias-pull-up;
+			drive-open-drain;
+			output-high;
+		};
+	};
+};
diff --git a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_appcpu.dts b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_appcpu.dts
new file mode 100644
index 00000000000..3547f3e351a
--- /dev/null
+++ b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_appcpu.dts
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <espressif/esp32/esp32_appcpu.dtsi>
+#include <espressif/partitions_0x1000_amp.dtsi>
+
+/ {
+	model = "TTGO TBeam APPCPU";
+	compatible = "espressif,esp32";
+
+	chosen {
+		zephyr,sram = &sram1;
+		zephyr,ipc_shm = &shm0;
+		zephyr,ipc = &ipm0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_appcpu_partition;
+	};
+};
+
+&ipm0 {
+	status = "okay";
+};
+
+&trng0 {
+	status = "okay";
+};
diff --git a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_appcpu.yaml b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_appcpu.yaml
new file mode 100644
index 00000000000..8eca6127690
--- /dev/null
+++ b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_appcpu.yaml
@@ -0,0 +1,28 @@
+identifier: ttgo_tbeam/esp32/appcpu
+name: TTGO TBeam APPCPU
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+supported:
+  - uart
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+    - flash
+    - cpp
+    - posix
+    - watchdog
+    - logging
+    - kernel
+    - pm
+    - gpio
+    - crypto
+    - eeprom
+    - heap
+    - cmsis_rtos
+    - jwt
+    - zdsp
+    - gnss
+vendor: lilygo
diff --git a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_appcpu_defconfig b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_appcpu_defconfig
new file mode 100644
index 00000000000..48546641cad
--- /dev/null
+++ b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_appcpu_defconfig
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.dts b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.dts
new file mode 100644
index 00000000000..43143525fb5
--- /dev/null
+++ b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.dts
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2024 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <espressif/esp32/esp32_pico_d4.dtsi>
+#include "ttgo_tbeam-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <espressif/partitions_0x1000_amp.dtsi>
+
+/ {
+	model = "TTGO TBeam PROCPU";
+	compatible = "lilygo,ttgo-tbeam";
+
+	aliases {
+		led0 = &red_led;
+		uart-0 = &uart0;
+		i2c-0 = &i2c0;
+		watchdog0 = &wdt0;
+		lora0 = &lora0;
+		gnss = &gnss;
+		regulator0 = &axp2101;
+	};
+
+	chosen {
+		zephyr,sram = &sram1;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,display = &ssd1306_128x64;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		red_led: led_0 {
+			gpios =  <&gpio0 4 GPIO_ACTIVE_HIGH>;
+			label = "Red - LED0";
+		};
+	};
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-names = "default";
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <9600>;
+	pinctrl-0 = <&uart1_default>;
+	pinctrl-names = "default";
+
+	gnss: gnss-nmea-generic {
+		compatible = "gnss-nmea-generic";
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	sda-gpios = <&gpio0 21 GPIO_OPEN_DRAIN>;
+	scl-gpios = <&gpio0 22 GPIO_OPEN_DRAIN>;
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+
+	ssd1306_128x64: ssd1306@3c {
+		compatible = "solomon,ssd1306fb";
+		reg = <0x3c>;
+		width = <128>;
+		height = <64>;
+		segment-offset = <0>;
+		page-offset = <0>;
+		display-offset = <0>;
+		multiplex-ratio = <63>;
+		segment-remap;
+		com-invdir;
+		prechargep = <0x22>;
+	};
+
+	axp2101: axp2101@34 {
+		status = "okay";
+		reg = <0x34>;
+		compatible = "x-powers,axp2101";
+		regulator {
+			compatible = "x-powers,axp2101-regulator";
+
+			vdd_mcu: DCDC1 {
+				regulator-min-microvolt = <3200000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vdd_lora: ALDO2 {
+				regulator-min-microvolt = <2900000>;
+				regulator-max-microvolt = <3000000>;
+				regulator-boot-on;
+				regulator-always-on;
+			};
+
+			vdd_gnss: ALDO3 {
+				regulator-min-microvolt = <2700000>;
+				regulator-max-microvolt = <2800000>;
+				regulator-boot-on;
+			};
+		};
+	};
+};
+
+&spi3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	pinctrl-0 = <&spim3_default>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
+
+	lora0: lora@0 {
+		compatible = "semtech,sx1276";
+		reg = <0>;
+		reset-gpios = <&gpio0 23 GPIO_ACTIVE_LOW>;
+		dio-gpios =
+			/* SX1276 D0 -> GPIO26 */
+			<&gpio0 26 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>,
+			/* SX1276 D1 -> GPIO33 */
+			<&gpio1 1 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>,
+			/* SX1276 D2 -> GPIO32 */
+			<&gpio1 0 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>;
+		spi-max-frequency = <1000000>;
+		power-amplifier-output = "pa-boost";
+	};
+};
+
+&timer0 {
+	status = "okay";
+};
+
+&timer1 {
+	status = "okay";
+};
+
+&timer2 {
+	status = "okay";
+};
+
+&timer3 {
+	status = "okay";
+};
+
+&trng0 {
+	status = "okay";
+};
diff --git a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.yaml b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.yaml
new file mode 100644
index 00000000000..6d2fe9c703a
--- /dev/null
+++ b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu.yaml
@@ -0,0 +1,22 @@
+identifier: ttgo_tbeam/esp32/procpu
+name: TTGO TBeam PROCPU
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+supported:
+  - gpio
+  - i2c
+  - spi
+  - watchdog
+  - uart
+  - pinmux
+  - display
+  - lora
+  - nvs
+  - gnss
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+vendor: lilygo
diff --git a/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu_defconfig b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu_defconfig
new file mode 100644
index 00000000000..6b1097cdb38
--- /dev/null
+++ b/boards/lilygo/ttgo_tbeam/ttgo_tbeam_esp32_procpu_defconfig
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+CONFIG_GPIO=y
+CONFIG_MFD=y
+CONFIG_REGULATOR=y
diff --git a/boards/lilygo/ttgo_toiplus/Kconfig b/boards/lilygo/ttgo_toiplus/Kconfig
new file mode 100644
index 00000000000..c6a99b1032d
--- /dev/null
+++ b/boards/lilygo/ttgo_toiplus/Kconfig
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+	int
+	default 4096
diff --git a/boards/lilygo/ttgo_toiplus/Kconfig.sysbuild b/boards/lilygo/ttgo_toiplus/Kconfig.sysbuild
new file mode 100644
index 00000000000..3a2d17ac5cf
--- /dev/null
+++ b/boards/lilygo/ttgo_toiplus/Kconfig.sysbuild
@@ -0,0 +1,10 @@
+# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+choice BOOTLOADER
+	default BOOTLOADER_MCUBOOT
+endchoice
+
+choice BOOT_SIGNATURE_TYPE
+	default BOOT_SIGNATURE_TYPE_NONE
+endchoice
diff --git a/boards/lilygo/ttgo_toiplus/Kconfig.ttgo_toiplus b/boards/lilygo/ttgo_toiplus/Kconfig.ttgo_toiplus
new file mode 100644
index 00000000000..ddca709de7a
--- /dev/null
+++ b/boards/lilygo/ttgo_toiplus/Kconfig.ttgo_toiplus
@@ -0,0 +1,5 @@
+# Copyright 2025 aisuneko icecat <iceneko@protonmail.ch>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_TTGO_TOIPLUS
+	select SOC_ESP32C3_FN4
diff --git a/boards/lilygo/ttgo_toiplus/board.cmake b/boards/lilygo/ttgo_toiplus/board.cmake
new file mode 100644
index 00000000000..2f04d1fe886
--- /dev/null
+++ b/boards/lilygo/ttgo_toiplus/board.cmake
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
+  set(OPENOCD OPENOCD-NOTFOUND)
+endif()
+find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
+
+include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/lilygo/ttgo_toiplus/board.yml b/boards/lilygo/ttgo_toiplus/board.yml
new file mode 100644
index 00000000000..e5295b2bec2
--- /dev/null
+++ b/boards/lilygo/ttgo_toiplus/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: ttgo_toiplus
+  full_name: TTGO T-OI-PLUS
+  vendor: lilygo
+  socs:
+  - name: esp32c3
diff --git a/boards/lilygo/ttgo_toiplus/doc/img/ttgo_toiplus.webp b/boards/lilygo/ttgo_toiplus/doc/img/ttgo_toiplus.webp
new file mode 100644
index 00000000000..115cc04fa29
Binary files /dev/null and b/boards/lilygo/ttgo_toiplus/doc/img/ttgo_toiplus.webp differ
diff --git a/boards/lilygo/ttgo_toiplus/doc/index.rst b/boards/lilygo/ttgo_toiplus/doc/index.rst
new file mode 100644
index 00000000000..3ea6b50446f
--- /dev/null
+++ b/boards/lilygo/ttgo_toiplus/doc/index.rst
@@ -0,0 +1,199 @@
+.. zephyr:board:: ttgo_toiplus
+
+Overview
+********
+
+Lilygo TTGO T-OI-PLUS is an mini IoT development board based on
+Espressif's ESP32-C3 WiFi/Bluetooth dual-mode chip.
+
+It features the following integrated components:
+
+- ESP32-C3 SoC (RISC-V 160MHz single core, 400KB SRAM, Wi-Fi, Bluetooth)
+- on board Grove connector
+- USB-C connector for power and communication (on board serial)
+- optional 18340 Li-ion battery holder
+- LED
+
+Functional Description
+**********************
+This board is based on the ESP32-C3 with 4MB of flash, WiFi and BLE support. It
+has an USB-C port for programming and debugging, integrated battery charging
+and an Grove connector.
+
+Connections and IOs
+===================
+
+.. zephyr:board-supported-hw::
+
+(Note: the above UART interface also supports connecting through USB.)
+
+Start Application Development
+*****************************
+
+Before powering up your Lilygo TTGO T-OI-PLUS, please make sure that the board is in good
+condition with no obvious signs of damage.
+
+System requirements
+*******************
+
+Prerequisites
+=============
+
+Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
+below to retrieve those files.
+
+.. code-block:: console
+
+   west blobs fetch hal_espressif
+
+.. note::
+
+   It is recommended running the command above after :file:`west update`.
+
+Building & Flashing
+*******************
+
+Simple boot
+===========
+
+The board could be loaded using the single binary image, without 2nd stage bootloader.
+It is the default option when building the application without additional configuration.
+
+.. note::
+
+   Simple boot does not provide any security features nor OTA updates.
+
+MCUboot bootloader
+==================
+
+User may choose to use MCUboot bootloader instead. In that case the bootloader
+must be built (and flashed) at least once.
+
+There are two options to be used when building an application:
+
+1. Sysbuild
+2. Manual build
+
+.. note::
+
+   User can select the MCUboot bootloader by adding the following line
+   to the board default configuration file.
+
+   .. code:: cfg
+
+      CONFIG_BOOTLOADER_MCUBOOT=y
+
+Sysbuild
+========
+
+The sysbuild makes possible to build and flash all necessary images needed to
+bootstrap the board with the ESP32-C3 SoC.
+
+To build the sample application using sysbuild use the command:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: samples/hello_world
+   :board: ttgo_toiplus
+   :goals: build
+   :west-args: --sysbuild
+   :compact:
+
+By default, the ESP32-C3 sysbuild creates bootloader (MCUboot) and application
+images. But it can be configured to create other kind of images.
+
+Build directory structure created by sysbuild is different from traditional
+Zephyr build. Output is structured by the domain subdirectories:
+
+.. code-block::
+
+  build/
+  ├── hello_world
+  │   └── zephyr
+  │       ├── zephyr.elf
+  │       └── zephyr.bin
+  ├── mcuboot
+  │    └── zephyr
+  │       ├── zephyr.elf
+  │       └── zephyr.bin
+  └── domains.yaml
+
+.. note::
+
+   With ``--sysbuild`` option the bootloader will be re-build and re-flash
+   every time the pristine build is used.
+
+For more information about the system build please read the :ref:`sysbuild` documentation.
+
+Manual build
+============
+
+During the development cycle, it is intended to build & flash as quickly possible.
+For that reason, images can be built one at a time using traditional build.
+
+The instructions following are relevant for both manual build and sysbuild.
+The only difference is the structure of the build directory.
+
+.. note::
+
+   Remember that bootloader (MCUboot) needs to be flash at least once.
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: ttgo_toiplus
+   :goals: build
+
+The usual ``flash`` target will work with the ``ttgo_toiplus`` board target.
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: ttgo_toiplus
+   :goals: flash
+
+You can also open the serial monitor using the following command:
+
+.. code-block:: shell
+
+   west espressif monitor
+
+After the board has automatically reset and booted, you should see the following
+message in the monitor:
+
+.. code-block:: console
+
+   ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
+   Hello World! ttgo_toiplus
+
+Sample applications
+===================
+
+The following samples will run out of the box on the TTGO T-OI-PLUS board.
+
+To build the blinky sample:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: samples/basic/blinky
+   :board: ttgo_toiplus
+   :goals: build
+
+To build the bluetooth beacon sample:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: samples/bluetooth/beacon
+   :board: ttgo_toiplus
+   :goals: build
+
+
+Related Documents
+*****************
+.. _`Lilygo TTGO T-OI-PLUS schematic`: https://github.com/Xinyuan-LilyGO/LilyGo-T-OI-PLUS/blob/main/schematic/T-OI_PLUS_Schematic.pdf
+.. _`Lilygo github repo`: https://github.com/Xinyuan-LilyGO
+.. _`Espressif ESP32-C3 datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_datasheet_en.pdf
+.. _`Espressif ESP32-C3 technical reference manual`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf
+.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases
diff --git a/boards/lilygo/ttgo_toiplus/support/openocd.cfg b/boards/lilygo/ttgo_toiplus/support/openocd.cfg
new file mode 100644
index 00000000000..02754ff2a73
--- /dev/null
+++ b/boards/lilygo/ttgo_toiplus/support/openocd.cfg
@@ -0,0 +1,6 @@
+set ESP_RTOS none
+
+source [find interface/esp_usb_jtag.cfg]
+
+source [find target/esp32c3.cfg]
+adapter_khz 5000
diff --git a/boards/lilygo/ttgo_toiplus/ttgo_toiplus-pinctrl.dtsi b/boards/lilygo/ttgo_toiplus/ttgo_toiplus-pinctrl.dtsi
new file mode 100644
index 00000000000..874d3c94639
--- /dev/null
+++ b/boards/lilygo/ttgo_toiplus/ttgo_toiplus-pinctrl.dtsi
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2024 Lothar Felten <lothar.felten@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
+#include <dt-bindings/pinctrl/esp32c3-pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/esp32c3-gpio-sigmap.h>
+
+&pinctrl {
+	uart0_default: uart0_default {
+		group1 {
+			pinmux = <UART0_TX_GPIO21>;
+			output-high;
+		};
+
+		group2 {
+			pinmux = <UART0_RX_GPIO20>;
+			bias-pull-up;
+		};
+	};
+
+	spim2_default: spim2_default {
+		group1 {
+			pinmux = <SPIM2_MISO_GPIO5>,
+				 <SPIM2_SCLK_GPIO4>;
+		};
+
+		/* GPIO6 is CS */
+
+		group2 {
+			pinmux = <SPIM2_MOSI_GPIO7>;
+			output-low;
+		};
+	};
+
+	i2c0_default: i2c0_default {
+		group1 {
+			pinmux = <I2C0_SDA_GPIO2>,
+				 <I2C0_SCL_GPIO8>;
+			bias-pull-up;
+			drive-open-drain;
+			output-high;
+		};
+	};
+
+	twai_default: twai_default {
+		group1 {
+			pinmux = <TWAI_TX_GPIO0>,
+				 <TWAI_RX_GPIO10>;
+		};
+	};
+};
diff --git a/boards/lilygo/ttgo_toiplus/ttgo_toiplus.dts b/boards/lilygo/ttgo_toiplus/ttgo_toiplus.dts
new file mode 100644
index 00000000000..6db7d4c16e6
--- /dev/null
+++ b/boards/lilygo/ttgo_toiplus/ttgo_toiplus.dts
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2025 aisuneko icecat <iceneko@protonmail.ch>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <espressif/esp32c3/esp32c3_common.dtsi>
+#include "ttgo_toiplus-pinctrl.dtsi"
+#include <espressif/partitions_0x0_default.dtsi>
+
+/ {
+	model = "Lilygo TTGO T-OI-PLUS";
+	compatible = "lilygo,ttgo-toiplus";
+
+	aliases {
+		led0 = &green_led;
+		i2c-0 = &i2c0;
+		watchdog0 = &wdt0;
+	};
+
+	chosen {
+		zephyr,sram = &sram1;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,bt-hci = &esp32_bt_hci;
+		zephyr,canbus = &twai;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		green_led: led_0 {
+			gpios =  <&gpio0 3 GPIO_ACTIVE_HIGH>;
+			label = "Green - LED0";
+		};
+	};
+};
+
+&flash0 {
+	reg = <0x0 DT_SIZE_M(4)>;
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-names = "default";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+};
+
+&trng0 {
+	status = "okay";
+};
+
+&spi2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	pinctrl-0 = <&spim2_default>;
+	pinctrl-names = "default";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&wdt0 {
+	status = "okay";
+};
+
+&timer0 {
+	status = "okay";
+};
+
+&timer1 {
+	status = "okay";
+};
+
+&twai {
+	status = "okay";
+	pinctrl-0 = <&twai_default>;
+	pinctrl-names = "default";
+};
+
+&wifi {
+	status = "okay";
+};
+
+&esp32_bt_hci {
+	status = "okay";
+};
diff --git a/boards/lilygo/ttgo_toiplus/ttgo_toiplus.yaml b/boards/lilygo/ttgo_toiplus/ttgo_toiplus.yaml
new file mode 100644
index 00000000000..746472787cb
--- /dev/null
+++ b/boards/lilygo/ttgo_toiplus/ttgo_toiplus.yaml
@@ -0,0 +1,14 @@
+identifier: ttgo_toiplus
+name: TTGO T-OI-PLUS
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+supported:
+  - gpio
+  - i2c
+  - spi
+  - uart
+  - watchdog
+  - can
+vendor: lilygo
diff --git a/boards/lilygo/ttgo_toiplus/ttgo_toiplus_defconfig b/boards/lilygo/ttgo_toiplus/ttgo_toiplus_defconfig
new file mode 100644
index 00000000000..187793c76e8
--- /dev/null
+++ b/boards/lilygo/ttgo_toiplus/ttgo_toiplus_defconfig
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y
diff --git a/boards/lilygo/twatch_s3/Kconfig b/boards/lilygo/twatch_s3/Kconfig
new file mode 100644
index 00000000000..8d5a48cfc2c
--- /dev/null
+++ b/boards/lilygo/twatch_s3/Kconfig
@@ -0,0 +1,7 @@
+# Copyright (c) 2025 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+config HEAP_MEM_POOL_ADD_SIZE_BOARD
+	int
+	default 4096 if BOARD_TWATCH_S3_ESP32S3_PROCPU
+	default 256 if BOARD_TWATCH_S3_ESP32S3_APPCPU
diff --git a/boards/lilygo/twatch_s3/Kconfig.defconfig b/boards/lilygo/twatch_s3/Kconfig.defconfig
new file mode 100644
index 00000000000..f7e4f32af39
--- /dev/null
+++ b/boards/lilygo/twatch_s3/Kconfig.defconfig
@@ -0,0 +1,17 @@
+# Copyright 2025 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+if DISPLAY
+
+choice ST7789V_PIXEL_FORMAT
+	default ST7789V_BGR565
+endchoice
+
+if LVGL
+
+config LV_COLOR_16_SWAP
+	default y
+
+endif # LVGL
+
+endif # DISPLAY
diff --git a/boards/lilygo/twatch_s3/Kconfig.sysbuild b/boards/lilygo/twatch_s3/Kconfig.sysbuild
new file mode 100644
index 00000000000..7d37de9b1aa
--- /dev/null
+++ b/boards/lilygo/twatch_s3/Kconfig.sysbuild
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+choice BOOTLOADER
+	default BOOTLOADER_MCUBOOT
+endchoice
+
+choice BOOT_SIGNATURE_TYPE
+	default BOOT_SIGNATURE_TYPE_NONE
+endchoice
diff --git a/boards/lilygo/twatch_s3/Kconfig.twatch_s3 b/boards/lilygo/twatch_s3/Kconfig.twatch_s3
new file mode 100644
index 00000000000..338ccb6bec9
--- /dev/null
+++ b/boards/lilygo/twatch_s3/Kconfig.twatch_s3
@@ -0,0 +1,7 @@
+# Copyright 2025 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_TWATCH_S3
+	select SOC_ESP32S3_WROOM_N16R8
+	select SOC_ESP32S3_PROCPU if BOARD_TWATCH_S3_ESP32S3_PROCPU
+	select SOC_ESP32S3_APPCPU if BOARD_TWATCH_S3_ESP32S3_APPCPU
diff --git a/boards/lilygo/twatch_s3/board.cmake b/boards/lilygo/twatch_s3/board.cmake
new file mode 100644
index 00000000000..2f04d1fe886
--- /dev/null
+++ b/boards/lilygo/twatch_s3/board.cmake
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT "${OPENOCD}" MATCHES "^${ESPRESSIF_TOOLCHAIN_PATH}/.*")
+  set(OPENOCD OPENOCD-NOTFOUND)
+endif()
+find_program(OPENOCD openocd PATHS ${ESPRESSIF_TOOLCHAIN_PATH}/openocd-esp32/bin NO_DEFAULT_PATH)
+
+include(${ZEPHYR_BASE}/boards/common/esp32.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/lilygo/twatch_s3/board.yml b/boards/lilygo/twatch_s3/board.yml
new file mode 100644
index 00000000000..e894af0d251
--- /dev/null
+++ b/boards/lilygo/twatch_s3/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: twatch_s3
+  full_name: T-Watch S3
+  vendor: lilygo
+  socs:
+  - name: esp32s3
diff --git a/boards/lilygo/twatch_s3/doc/img/twatch_s3.webp b/boards/lilygo/twatch_s3/doc/img/twatch_s3.webp
new file mode 100644
index 00000000000..b79ef681317
Binary files /dev/null and b/boards/lilygo/twatch_s3/doc/img/twatch_s3.webp differ
diff --git a/boards/lilygo/twatch_s3/doc/index.rst b/boards/lilygo/twatch_s3/doc/index.rst
new file mode 100644
index 00000000000..3dc07e37673
--- /dev/null
+++ b/boards/lilygo/twatch_s3/doc/index.rst
@@ -0,0 +1,198 @@
+.. zephyr:board:: twatch_s3
+
+Overview
+********
+
+LILYGO T-Watch S3 is an ESP32-S3 based smartwatch with the following features:
+
+- ESP32-S3-R8 chip
+
+   - Dual core Xtensa LX-7 up to 240MHz
+   - 8 MB of integrated PSRAM
+   - Bluetooth LE v5.0
+   - Wi-Fi 802.11 b/g/n
+
+- 16 MB external QSPI flash (Winbond W25Q128JWPIQ)
+- Power Management Unit (X-Powers AXP2101) which provides
+
+   - Regulators (DC-DCs and LDOs)
+   - Battery charging
+   - Fuel gauge
+
+- 470 mAh battery
+- RTC (NXP PCF8563)
+- Haptic (Texas Instruments DRV2605)
+- Accelerometer (Bosch BMA423)
+- 240x240 pixels LCD with touchscreen
+
+   - ST7789V LCD Controller
+   - Focaltech FT5336 touch sensor
+
+- Microphone (Knowles SPM1423HM4H-B)
+- LoRA radio (Semtech SX1262)
+- Audio amplifier (Maxim MAX98357A)
+
+The board features a single micro USB connector which can be used for serial
+flashing, debugging and console thanks to the integrated JTAG support in the
+chip.
+
+It does not have any GPIO that can easily be connected to something external.
+There is only 1 physical button which is connected to the PMU and it's used
+to turn on/off the device.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Building & Flashing
+*******************
+
+.. zephyr:board-supported-runners::
+
+Prerequisites
+=============
+
+Espressif HAL requires WiFi and Bluetooth binary blobs in order to work. Run the command
+below to retrieve those files.
+
+.. code-block:: console
+
+   west blobs fetch hal_espressif
+
+.. note::
+
+   It is recommended running the command above after :file:`west update`.
+
+Simple boot
+===========
+
+The board could be loaded using a single binary image, without 2nd stage bootloader.
+It is the default option when building the application without additional configuration.
+
+.. note::
+
+   Simple boot does not provide any security features nor OTA updates.
+
+MCUboot bootloader
+==================
+
+User may choose to use MCUboot bootloader instead. In that case the bootloader
+must be built (and flashed) at least once.
+
+There are two options to be used when building an application:
+
+1. Sysbuild
+2. Manual build
+
+.. note::
+
+   User can select the MCUboot bootloader by adding the following line
+   to the board default configuration file.
+
+   .. code-block:: cfg
+
+      CONFIG_BOOTLOADER_MCUBOOT=y
+
+Sysbuild
+--------
+
+The sysbuild makes it possible to build and flash all necessary images needed to
+bootstrap the board with the ESP32 SoC.
+
+To build the sample application using sysbuild, use the command:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: samples/hello_world
+   :board: twatch_s3/esp32s3/procpu
+   :goals: build
+   :west-args: --sysbuild
+   :compact:
+
+By default, the ESP32-S3 sysbuild creates bootloader (MCUboot) and application
+images. But it can be configured to create other kind of images.
+
+Build directory structure created by sysbuild is different from traditional
+Zephyr build. Output is structured by the domain subdirectories:
+
+.. code-block::
+
+  build/
+  ├── hello_world
+  │   └── zephyr
+  │       ├── zephyr.elf
+  │       └── zephyr.bin
+  ├── mcuboot
+  │    └── zephyr
+  │       ├── zephyr.elf
+  │       └── zephyr.bin
+  └── domains.yaml
+
+.. note::
+
+   With ``--sysbuild`` option the bootloader will be re-built and re-flashed
+   every time the pristine build is used.
+
+For more information about the system build please read the :ref:`sysbuild` documentation.
+
+Manual build
+------------
+
+During the development cycle, it is intended to build & flash as quickly as possible.
+For that reason, images can be built one at a time using traditional build.
+
+The instructions following are relevant for both manual build and sysbuild.
+The only difference is the structure of the build directory.
+
+.. note::
+
+   Remember that bootloader (MCUboot) needs to be flashed at least once.
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: twatch_s3/esp32s3/procpu
+   :goals: build
+
+The usual ``flash`` target will work with the ``twatch_s3`` board target
+configuration. Here is an example for the :zephyr:code-sample:`hello_world`
+application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: twatch_s3/esp32s3/procpu
+   :goals: flash
+
+The default baud rate is set to 1500000bps. If experiencing issues when flashing,
+try using different values by using ``--esp-baud-rate <BAUD>`` option during
+``west flash`` (e.g. ``west flash --esp-baud-rate 115200``).
+
+You can also open the serial monitor using the following command:
+
+.. code-block:: shell
+
+   west espressif monitor
+
+After the board has automatically reset and booted, you should see the following
+message in the monitor:
+
+.. code-block:: console
+
+   ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
+   Hello World! twatch_s3/esp32s3/procpu
+
+References
+**********
+
+.. target-notes::
+
+.. _`Lilygo Twatch S3 schematic`: https://github.com/Xinyuan-LilyGO/TTGO_TWatch_Library/blob/t-watch-s3/schematic/T_WATCH_S3.pdf
+.. _`Lilygo T-Watch S3 repo`: https://github.com/Xinyuan-LilyGO/TTGO_TWatch_Library/tree/t-watch-s3
+.. _`Lilygo T-Watch Deps repo`: https://github.com/Xinyuan-LilyGO/T-Watch-Deps
+.. _`ESP32-S3 Datasheet`: https://www.espressif.com/sites/default/files/documentation/esp32-s3_datasheet_en.pdf
+.. _`ESP32-S3 Technical Reference Manual`: https://www.espressif.com/sites/default/files/documentation/esp32-c3_technical_reference_manual_en.pdf
+.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases
+.. _`JTAG debugging for ESP32-S3`: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-guides/jtag-debugging/
diff --git a/boards/lilygo/twatch_s3/support/openocd.cfg b/boards/lilygo/twatch_s3/support/openocd.cfg
new file mode 100644
index 00000000000..0b2c4909fe0
--- /dev/null
+++ b/boards/lilygo/twatch_s3/support/openocd.cfg
@@ -0,0 +1,7 @@
+set ESP_RTOS none
+set ESP32_ONLYCPU 1
+
+source [find interface/esp_usb_jtag.cfg]
+
+source [find target/esp32s3.cfg]
+adapter_khz 5000
diff --git a/boards/lilygo/twatch_s3/twatch_s3-pinctrl.dtsi b/boards/lilygo/twatch_s3/twatch_s3-pinctrl.dtsi
new file mode 100644
index 00000000000..b62a16f797a
--- /dev/null
+++ b/boards/lilygo/twatch_s3/twatch_s3-pinctrl.dtsi
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2025 BayLibre SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/esp-pinctrl-common.h>
+#include <dt-bindings/pinctrl/esp32s3-pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/esp32s3-gpio-sigmap.h>
+
+&pinctrl {
+	i2c0_default: i2c0_default {
+		group1 {
+			pinmux = <I2C0_SCL_GPIO11>,
+				 <I2C0_SDA_GPIO10>;
+			drive-open-drain;
+			output-high;
+		};
+	};
+
+	i2c1_default: i2c1_default {
+		group1 {
+			pinmux = <I2C1_SCL_GPIO40>,
+				 <I2C1_SDA_GPIO39>;
+			drive-open-drain;
+			output-high;
+		};
+	};
+
+	spim3_default: spim3_default {
+		group1 {
+			pinmux = <SPIM3_SCLK_GPIO18>,
+				 <SPIM3_CSEL_GPIO12>;
+		};
+
+		group2 {
+			pinmux = <SPIM3_MOSI_GPIO13>;
+			output-low;
+		};
+	};
+
+	ledc0_default: ledc0_default {
+		group1 {
+			pinmux = <LEDC_CH0_GPIO45>;
+			output-enable;
+		};
+	};
+};
diff --git a/boards/lilygo/twatch_s3/twatch_s3_appcpu.dts b/boards/lilygo/twatch_s3/twatch_s3_appcpu.dts
new file mode 100644
index 00000000000..35d19fc17b1
--- /dev/null
+++ b/boards/lilygo/twatch_s3/twatch_s3_appcpu.dts
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025 BayLibre SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <espressif/esp32s3/esp32s3_r8.dtsi>
+#include <espressif/partitions_0x0_amp_16M.dtsi>
+
+/ {
+	model = "T-Watch S3 APPCPU";
+	compatible = "espressif,esp32s3";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,ipc_shm = &shm0;
+		zephyr,ipc = &ipm0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_appcpu_partition;
+	};
+};
+
+&flash0 {
+	reg = <0x0 DT_SIZE_M(16)>;
+};
+
+&trng0 {
+	status = "okay";
+};
+
+&ipm0 {
+	status = "okay";
+};
diff --git a/boards/lilygo/twatch_s3/twatch_s3_appcpu.yaml b/boards/lilygo/twatch_s3/twatch_s3_appcpu.yaml
new file mode 100644
index 00000000000..e834a090c9f
--- /dev/null
+++ b/boards/lilygo/twatch_s3/twatch_s3_appcpu.yaml
@@ -0,0 +1,27 @@
+identifier: twatch_s3/esp32s3/appcpu
+name: T-Watch S3 APPCPU
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+supported:
+  - uart
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+    - flash
+    - cpp
+    - posix
+    - watchdog
+    - logging
+    - kernel
+    - pm
+    - gpio
+    - crypto
+    - eeprom
+    - heap
+    - cmsis_rtos
+    - jwt
+    - zdsp
+vendor: lilygo
diff --git a/boards/lilygo/twatch_s3/twatch_s3_appcpu_defconfig b/boards/lilygo/twatch_s3/twatch_s3_appcpu_defconfig
new file mode 100644
index 00000000000..48546641cad
--- /dev/null
+++ b/boards/lilygo/twatch_s3/twatch_s3_appcpu_defconfig
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/lilygo/twatch_s3/twatch_s3_procpu.dts b/boards/lilygo/twatch_s3/twatch_s3_procpu.dts
new file mode 100644
index 00000000000..b78676a8b0a
--- /dev/null
+++ b/boards/lilygo/twatch_s3/twatch_s3_procpu.dts
@@ -0,0 +1,282 @@
+/*
+ * Copyright (c) 2025 BayLibre SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <espressif/esp32s3/esp32s3_r8.dtsi>
+#include "twatch_s3-pinctrl.dtsi"
+#include <espressif/partitions_0x0_amp_16M.dtsi>
+#include <zephyr/dt-bindings/pwm/pwm.h>
+
+/ {
+	model = "T-Watch S3 PROCPU";
+	compatible = "espressif,esp32s3";
+
+	aliases {
+		i2c-0 = &i2c0;
+		i2c-1 = &i2c1;
+		watchdog0 = &wdt0;
+		rtc = &pfc8563_rtc;
+		pwm-led0 = &backlight_pwm;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &usb_serial;
+		zephyr,shell-uart = &usb_serial;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,bt-hci = &esp32_bt_hci;
+		zephyr,display = &st7789v;
+		zephyr,touch = &ft5336;
+		zephyr,ipc_shm = &shm0;
+		zephyr,ipc = &ipm0;
+	};
+
+	mipi_dbi {
+		compatible = "zephyr,mipi-dbi-spi";
+		dc-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+		spi-dev = <&spi3>;
+		write-only;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		st7789v: st7789v@0 {
+			compatible = "sitronix,st7789v";
+			mipi-max-frequency = <20000000>;
+			mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE";
+			reg = <0>;
+			width = <240>;
+			height = <240>;
+			x-offset = <0>;
+			y-offset = <80>;
+			mdac = <0xc8>;
+			ram-param = [00 e0];
+			colmod = <0x55>;
+			porch-param = [0c 0c 00 33 33];
+			gctrl = <0x35>;
+			vcom = <0x28>;
+			lcm = <0x0c>;
+			vrhs = <0x10>;
+			vdvs = <0x20>;
+			pwctrl1-param = [a4 a1];
+			pvgam-param = [d0 00 02 07 0a 28 32 44 42 06 0e 12 14 17];
+			nvgam-param = [d0 00 02 07 0a 28 31 54 47 0e 1c 17 1b 1e];
+			/* Values below are not set by the eTFT_SPI driver from
+			 * LilyGO. Therefore let's keep ST7789V values.
+			 */
+			gamma = <0x01>;
+			cmd2en-param = [5a 69 02 00];
+			rgb-param = [40 02 14];
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		backlight_pwm: pwm_0 {
+			label = "LCD backlight PWM";
+			pwms = <&ledc0 0 PWM_HZ(100) PWM_POLARITY_NORMAL>;
+		};
+	};
+
+	lvgl_pointer {
+		compatible = "zephyr,lvgl-pointer-input";
+		input = <&ft5336>;
+		swap-xy;
+	};
+};
+
+&ledc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	pinctrl-0 = <&ledc0_default>;
+	pinctrl-names = "default";
+
+	channel0@0 {
+		reg = <0x0>;
+		timer = <0>;
+	};
+};
+
+&spi3 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	pinctrl-0 = <&spim3_default>;
+	pinctrl-names = "default";
+};
+
+&i2c0 {
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	pfc8563_rtc: pfc8563@51 {
+		compatible = "nxp,pcf8563";
+		reg = <0x51>;
+		status = "okay";
+	};
+
+	bma423: bma423@19 {
+		compatible = "bosch,bma4xx";
+		reg = <0x19>;
+		status = "okay";
+		int1-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
+	};
+
+	haptic: drv2605@5a {
+		compatible = "ti,drv2605";
+		reg = <0x5a>;
+		status = "okay";
+		actuator-mode = "ERM";
+	};
+
+	axp2101@34 {
+		compatible = "x-powers,axp2101";
+		reg = <0x34>;
+
+		charger {
+			compatible = "x-powers,axp2101-charger";
+			constant-charge-current-max-microamp = <300000>;
+			constant-charge-voltage-max-microvolt = <4200000>;
+			charge-term-current-microamp = <100000>;
+			vbackup-enable;
+		};
+
+		regulators {
+			compatible = "x-powers,axp2101-regulator";
+
+			dcdc1 {
+				regulator-min-microvolt = <3300000>;
+				regulator-init-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+			};
+
+			dcdc2 {
+				regulator-boot-off;
+			};
+
+			dcdc3 {
+				regulator-min-microvolt = <3300000>;
+				regulator-init-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+			};
+
+			dcdc4 {
+				regulator-boot-off;
+			};
+
+			dcdc5 {
+				regulator-boot-off;
+			};
+
+			aldo1 {
+				regulator-min-microvolt = <3300000>;
+				regulator-init-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+			};
+
+			aldo2 {
+				regulator-min-microvolt = <3300000>;
+				regulator-init-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+			};
+
+			aldo3 {
+				regulator-min-microvolt = <3300000>;
+				regulator-init-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+			};
+
+			aldo4 {
+				regulator-min-microvolt = <3300000>;
+				regulator-init-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+			};
+
+			bldo1 {
+				regulator-boot-off;
+			};
+
+			bldo2 {
+				regulator-min-microvolt = <3300000>;
+				regulator-init-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+			};
+
+			cplusldo {
+				regulator-boot-off;
+			};
+
+			dldo1 {
+				regulator-boot-off;
+			};
+
+			dldo2 {
+				regulator-boot-off;
+			};
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c1_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	ft5336: ft5336@38 {
+		compatible = "focaltech,ft5336";
+		reg = <0x38>;
+		int-gpios = <&gpio0 16 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+		reset-gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
+	};
+};
+
+&usb_serial {
+	status = "okay";
+};
+
+&wdt0 {
+	status = "okay";
+};
+
+&trng0 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&esp32_bt_hci {
+	status = "okay";
+};
+
+&flash0 {
+	reg = <0x0 DT_SIZE_M(16)>;
+};
+
+&timer0 {
+	status = "okay";
+};
+
+&ipm0 {
+	status = "okay";
+};
diff --git a/boards/lilygo/twatch_s3/twatch_s3_procpu.yaml b/boards/lilygo/twatch_s3/twatch_s3_procpu.yaml
new file mode 100644
index 00000000000..975c4750ac0
--- /dev/null
+++ b/boards/lilygo/twatch_s3/twatch_s3_procpu.yaml
@@ -0,0 +1,19 @@
+identifier: twatch_s3/esp32s3/procpu
+name: T-Watch S3 PROCPU
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+supported:
+  - gpio
+  - i2c
+  - spi
+  - counter
+  - watchdog
+  - entropy
+  - pwm
+  - dma
+  - input
+  - video
+  - rtc
+vendor: lilygo
diff --git a/boards/lilygo/twatch_s3/twatch_s3_procpu_defconfig b/boards/lilygo/twatch_s3/twatch_s3_procpu_defconfig
new file mode 100644
index 00000000000..d8fbaa87925
--- /dev/null
+++ b/boards/lilygo/twatch_s3/twatch_s3_procpu_defconfig
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/lowrisc/opentitan_earlgrey/doc/index.rst b/boards/lowrisc/opentitan_earlgrey/doc/index.rst
index b91c0700def..bfc13c12181 100644
--- a/boards/lowrisc/opentitan_earlgrey/doc/index.rst
+++ b/boards/lowrisc/opentitan_earlgrey/doc/index.rst
@@ -1,7 +1,4 @@
-.. _opentitan_earlgrey:
-
-OpenTitan Earl Grey
-###################
+.. zephyr:board:: opentitan_earlgrey
 
 Overview
 ********
@@ -51,6 +48,8 @@ Other hardware features are not yet supported on Zephyr porting.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 First, build and install Verilator as described in the `OpenTitan Verilator
 Setup`_ guide .
 
diff --git a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi
index f000b61f316..1b0a13b77df 100644
--- a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi
+++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core.dtsi
@@ -96,3 +96,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_defconfig b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_defconfig
index ef633ce56a1..187793c76e8 100644
--- a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_defconfig
+++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb_defconfig b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb_defconfig
index ef633ce56a1..187793c76e8 100644
--- a/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb_defconfig
+++ b/boards/luatos/esp32c3_luatos_core/esp32c3_luatos_core_esp32c3_usb_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi
index 43ee4b45264..fc3c57e1b9f 100644
--- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi
+++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core.dtsi
@@ -107,3 +107,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_defconfig b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_defconfig
+++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb_defconfig b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb_defconfig
+++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_appcpu_usb_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_defconfig b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_defconfig
index d789bab1824..d8fbaa87925 100644
--- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_defconfig
+++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_usb_defconfig b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_usb_defconfig
index d789bab1824..d8fbaa87925 100644
--- a/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_usb_defconfig
+++ b/boards/luatos/esp32s3_luatos_core/esp32s3_luatos_core_procpu_usb_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/m5stack/m5stack_atom_lite/doc/index.rst b/boards/m5stack/m5stack_atom_lite/doc/index.rst
index 87e56a23677..9b84f801fd6 100644
--- a/boards/m5stack/m5stack_atom_lite/doc/index.rst
+++ b/boards/m5stack/m5stack_atom_lite/doc/index.rst
@@ -16,39 +16,7 @@ It features the following integrated components:
 Supported Features
 ==================
 
-The Zephyr m5stack_atom_lite board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | dac                                 |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-
+.. zephyr:board-supported-hw::
 
 Start Application Development
 *****************************
@@ -76,6 +44,8 @@ below to retrieve those files.
 Building & Flashing
 -------------------
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
diff --git a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_appcpu_defconfig b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_appcpu_defconfig
+++ b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts
index 012c2b1f8fe..226b1d1a004 100644
--- a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts
+++ b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu.dts
@@ -147,3 +147,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu_defconfig b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu_defconfig
index 0ec9d053667..c3c35f0cfe9 100644
--- a/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu_defconfig
+++ b/boards/m5stack/m5stack_atom_lite/m5stack_atom_lite_procpu_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_GPIO=y
 
 CONFIG_CONSOLE=y
diff --git a/boards/m5stack/m5stack_atoms3/doc/index.rst b/boards/m5stack/m5stack_atoms3/doc/index.rst
index 1b863cb08be..9cedbfb5180 100644
--- a/boards/m5stack/m5stack_atoms3/doc/index.rst
+++ b/boards/m5stack/m5stack_atoms3/doc/index.rst
@@ -18,39 +18,7 @@ It features the following integrated components:
 Supported Features
 ==================
 
-The Zephyr m5stack_atoms3 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | dac                                 |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-
+.. zephyr:board-supported-hw::
 
 Start Application Development
 *****************************
@@ -78,6 +46,8 @@ below to retrieve those files.
 Building & Flashing
 -------------------
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_appcpu_defconfig b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_appcpu_defconfig
+++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts
index ed963407407..bb81fbbb39f 100644
--- a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts
+++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu.dts
@@ -158,3 +158,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu_defconfig b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu_defconfig
index 88c69e52e8c..60b1ee000fc 100644
--- a/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu_defconfig
+++ b/boards/m5stack/m5stack_atoms3/m5stack_atoms3_procpu_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_GPIO=y
 CONFIG_REGULATOR=y # for LCD backlight
 
diff --git a/boards/m5stack/m5stack_atoms3_lite/doc/index.rst b/boards/m5stack/m5stack_atoms3_lite/doc/index.rst
index 23af62d96e6..8403358be1e 100644
--- a/boards/m5stack/m5stack_atoms3_lite/doc/index.rst
+++ b/boards/m5stack/m5stack_atoms3_lite/doc/index.rst
@@ -16,39 +16,7 @@ It features the following integrated components:
 Supported Features
 ==================
 
-The Zephyr m5stack_atoms3_lite board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | dac                                 |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-
+.. zephyr:board-supported-hw::
 
 Start Application Development
 *****************************
@@ -76,6 +44,8 @@ below to retrieve those files.
 Building & Flashing
 -------------------
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_appcpu_defconfig b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_appcpu_defconfig
+++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts
index c5884a846a1..60bc3d6429a 100644
--- a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts
+++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu.dts
@@ -117,3 +117,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu_defconfig b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu_defconfig
index d789bab1824..d8fbaa87925 100644
--- a/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu_defconfig
+++ b/boards/m5stack/m5stack_atoms3_lite/m5stack_atoms3_lite_procpu_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/m5stack/m5stack_core2/Kconfig.defconfig b/boards/m5stack/m5stack_core2/Kconfig.defconfig
index 155a3c1d39c..1999b90c5b8 100644
--- a/boards/m5stack/m5stack_core2/Kconfig.defconfig
+++ b/boards/m5stack/m5stack_core2/Kconfig.defconfig
@@ -14,7 +14,7 @@ config GPIO_HOGS_INIT_PRIORITY
 config MFD_INIT_PRIORITY
 	default 70
 
-config REGULATOR_AXP192_INIT_PRIORITY
+config REGULATOR_AXP192_AXP2101_INIT_PRIORITY
 	default 71
 
 config GPIO_AXP192_INIT_PRIORITY
@@ -23,9 +23,6 @@ config GPIO_AXP192_INIT_PRIORITY
 config REGULATOR_FIXED_INIT_PRIORITY
 	default 75
 
-config INPUT_FT5336_INTERRUPT
-	default y if INPUT
-
 config INPUT
 	default y
 
diff --git a/boards/m5stack/m5stack_core2/doc/index.rst b/boards/m5stack/m5stack_core2/doc/index.rst
index 9855ef1de59..fb21227767c 100644
--- a/boards/m5stack/m5stack_core2/doc/index.rst
+++ b/boards/m5stack/m5stack_core2/doc/index.rst
@@ -104,39 +104,7 @@ These voltages can be controlled via regulator api.
 Supported Features
 ==================
 
-The Zephyr m5stack_core2 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | dac                                 |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-
+.. zephyr:board-supported-hw::
 
 Start Application Development
 *****************************
@@ -164,6 +132,8 @@ below to retrieve those files.
 Building & Flashing
 -------------------
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_appcpu_defconfig b/boards/m5stack/m5stack_core2/m5stack_core2_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/m5stack/m5stack_core2/m5stack_core2_appcpu_defconfig
+++ b/boards/m5stack/m5stack_core2/m5stack_core2_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts b/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts
index 554e1885488..172fb1c6c5d 100644
--- a/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts
+++ b/boards/m5stack/m5stack_core2/m5stack_core2_procpu.dts
@@ -87,8 +87,7 @@
 };
 
 &psram0 {
-	reg = <0x3f800000 DT_SIZE_M(8)>;
-	status = "disabled";
+	size = <DT_SIZE_M(8)>;
 };
 
 &uart0 {
@@ -191,7 +190,7 @@
 	ft5336_touch: ft5336@38 {
 		compatible = "focaltech,ft5336";
 		reg = <0x38>;
-		int-gpios = <&gpio1 7 0>;
+		int-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
 	};
 };
 
@@ -253,3 +252,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/m5stack/m5stack_core2/m5stack_core2_procpu_defconfig b/boards/m5stack/m5stack_core2/m5stack_core2_procpu_defconfig
index 008eb0afc9e..0fcad2e5e26 100644
--- a/boards/m5stack/m5stack_core2/m5stack_core2_procpu_defconfig
+++ b/boards/m5stack/m5stack_core2/m5stack_core2_procpu_defconfig
@@ -1,12 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-CONFIG_ESP_HEAP_MEM_POOL_REGION_1_SIZE=0
-
 CONFIG_GPIO=y
-
 CONFIG_REGULATOR=y
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/m5stack/m5stack_cores3/Kconfig.defconfig b/boards/m5stack/m5stack_cores3/Kconfig.defconfig
index b31bac7c90a..fe718f3cf4a 100644
--- a/boards/m5stack/m5stack_cores3/Kconfig.defconfig
+++ b/boards/m5stack/m5stack_cores3/Kconfig.defconfig
@@ -5,9 +5,6 @@
 
 if BOARD_M5STACK_CORES3_ESP32S3_PROCPU || BOARD_M5STACK_CORES3_ESP32S3_PROCPU_SE
 
-config INPUT_FT5336_INTERRUPT
-	default y if INPUT
-
 config INPUT
 	default y
 
diff --git a/boards/m5stack/m5stack_cores3/doc/index.rst b/boards/m5stack/m5stack_cores3/doc/index.rst
index d9025e3f6d8..2fdd042c38e 100644
--- a/boards/m5stack/m5stack_cores3/doc/index.rst
+++ b/boards/m5stack/m5stack_cores3/doc/index.rst
@@ -52,6 +52,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu_defconfig b/boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu_defconfig
+++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts
index 1def598cdec..5a579251bb6 100644
--- a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts
+++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu.dts
@@ -30,3 +30,20 @@
 		reg = <0x10>;
 	};
 };
+
+&regulator {
+	vddcam_3v3: ALDO3 {
+		regulator-min-microvolt  = <3000000>;
+		/* regulator-init-microvolt = <3300000>; */
+		regulator-max-microvolt  = <3500000>;
+		regulator-boot-on;
+		status = "okay";
+	};
+
+	avdd: BLDO1 {
+		regulator-min-microvolt = <2700000>;
+		/* regulator-init-microvolt = <2800000>; */
+		regulator-max-microvolt = <3300000>;
+		status = "okay";
+	};
+};
diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi
index 9b9b8991a15..1d4fd8c4a6f 100644
--- a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi
+++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_common.dtsi
@@ -31,6 +31,7 @@
 		watchdog0 = &wdt0;
 		rtc = &bm8563_rtc;
 		sdhc0 = &sd0;
+		led0 = &axp2101_led;
 	};
 
 	lvgl_pointer {
@@ -78,13 +79,101 @@
 	pinctrl-0 = <&i2c0_default>;
 	pinctrl-names = "default";
 
+	axp2101@34 {
+		compatible = "x-powers,axp2101";
+		reg = <0x34>;
+		status = "okay";
+
+		regulator: regulator {
+			compatible = "x-powers,axp2101-regulator";
+			status = "okay";
+
+			/*
+			 * Typically, no initialization is performed since non-volatile
+			 * values are used.
+			 * If you remove the commenting, initialization will be performed
+			 * with the default value.
+			 */
+
+			vdd_3v3: DCDC1 {
+				regulator-min-microvolt  = <3000000>;
+				/* regulator-init-microvolt = <3300000>; */
+				regulator-max-microvolt  = <3300000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "okay";
+			};
+
+			vcc_3v3: DCDC3 {
+				regulator-min-microvolt  = <3100000>;
+				/* regulator-init-microvolt = <3300000>; */
+				regulator-max-microvolt  = <3500000>;
+				regulator-boot-on;
+				regulator-always-on;
+				status = "okay";
+			};
+
+			vdd_1v8: ALDO1 {
+				regulator-min-microvolt  = <1700000>;
+				/* regulator-init-microvolt = <1800000>; */
+				regulator-max-microvolt  = <1900000>;
+				regulator-boot-on;
+				status = "okay";
+			};
+
+			vdda_3v3: ALDO2 {
+				regulator-min-microvolt  = <3100000>;
+				/* regulator-init-microvolt = <3300000>; */
+				regulator-max-microvolt  = <3500000>;
+				regulator-boot-on;
+				status = "okay";
+			};
+
+			vdd_3v3_sd: ALDO4 {
+				regulator-min-microvolt  = <3100000>;
+				/* regulator-init-microvolt = <3300000>; */
+				regulator-max-microvolt  = <3500000>;
+				regulator-boot-on;
+				status = "okay";
+			};
+
+			dvdd: BLDO2 {
+				regulator-min-microvolt = <3100000>;
+				/* regulator-init-microvolt = <3300000>; */
+				regulator-max-microvolt = <3500000>;
+				status = "okay";
+			};
+
+			vcc_bl: DLDO1 {
+				regulator-min-microvolt = <2500000>;
+				/* regulator-init-microvolt = <3300000>; */
+				regulator-max-microvolt = <3300000>;
+				regulator-boot-on;
+				status = "okay";
+			};
+		};
+
+		charger: charger {
+			compatible = "x-powers,axp2101-charger";
+			constant-charge-current-max-microamp = <200000>;
+			constant-charge-voltage-max-microvolt = <4200000>;
+			charge-term-current-microamp = <125000>;
+		};
+
+		axp2101_led: led {
+			compatible = "x-powers,axp2101-led";
+			status = "okay";
+			x-powers,mode = "by-reg";
+		};
+	};
+
 	bm8563_rtc: bm8563@51 {
 		compatible = "nxp,pcf8563";
 		reg = <0x51>;
 		status = "okay";
 	};
 
-	aw9523b@58 {
+	aw9523b: aw9523b@58 {
 		compatible = "awinic,aw9523b";
 		reg = <0x58>;
 		status = "okay";
@@ -156,3 +245,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_defconfig b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_defconfig
index 6539bd42e59..187793c76e8 100644
--- a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_defconfig
+++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_defconfig
@@ -1,6 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se_defconfig b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se_defconfig
index 6539bd42e59..187793c76e8 100644
--- a/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se_defconfig
+++ b/boards/m5stack/m5stack_cores3/m5stack_cores3_procpu_se_defconfig
@@ -1,6 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/m5stack/m5stack_stamps3/doc/index.rst b/boards/m5stack/m5stack_stamps3/doc/index.rst
index 3762fd49b1c..4e006eca8a3 100644
--- a/boards/m5stack/m5stack_stamps3/doc/index.rst
+++ b/boards/m5stack/m5stack_stamps3/doc/index.rst
@@ -134,6 +134,8 @@ below to retrieve those files.
 Building & Flashing
 -------------------
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu_defconfig b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu_defconfig
+++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts
index f2733a57195..d2aa01fa61c 100644
--- a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts
+++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu.dts
@@ -156,3 +156,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu_defconfig b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu_defconfig
index 466f9999601..68d1fe58d2e 100644
--- a/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu_defconfig
+++ b/boards/m5stack/m5stack_stamps3/m5stack_stamps3_procpu_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_GPIO=y
 
 CONFIG_CONSOLE=y
diff --git a/boards/m5stack/m5stickc_plus/Kconfig.defconfig b/boards/m5stack/m5stickc_plus/Kconfig.defconfig
index 86819dba82d..9399c4d1f32 100644
--- a/boards/m5stack/m5stickc_plus/Kconfig.defconfig
+++ b/boards/m5stack/m5stickc_plus/Kconfig.defconfig
@@ -11,7 +11,7 @@ config GPIO_HOGS_INIT_PRIORITY
 config MFD_INIT_PRIORITY
 	default 70
 
-config REGULATOR_AXP192_INIT_PRIORITY
+config REGULATOR_AXP192_AXP2101_INIT_PRIORITY
 	default 71
 
 config GPIO_AXP192_INIT_PRIORITY
diff --git a/boards/m5stack/m5stickc_plus/doc/index.rst b/boards/m5stack/m5stickc_plus/doc/index.rst
index f40e21fbd5e..e6e65a3e1d8 100644
--- a/boards/m5stack/m5stickc_plus/doc/index.rst
+++ b/boards/m5stack/m5stickc_plus/doc/index.rst
@@ -84,6 +84,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu_defconfig b/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu_defconfig
+++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts b/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts
index 6b1a2dd8ba2..2a85c2c0353 100644
--- a/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts
+++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu.dts
@@ -218,3 +218,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu_defconfig b/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu_defconfig
index 6b210f481bc..35626ba6fea 100644
--- a/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu_defconfig
+++ b/boards/m5stack/m5stickc_plus/m5stickc_plus_procpu_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/m5stack/stamp_c3/doc/index.rst b/boards/m5stack/stamp_c3/doc/index.rst
index a953b595b2c..704bacc6cad 100644
--- a/boards/m5stack/stamp_c3/doc/index.rst
+++ b/boards/m5stack/stamp_c3/doc/index.rst
@@ -11,30 +11,7 @@ For more details see the `M5Stack STAMP-C3`_ page.
 Supported Features
 ==================
 
-The STAMP-C3 board configuration supports the following hardware features:
-
-+-----------+------------+------------------+
-| Interface | Controller | Driver/Component |
-+===========+============+==================+
-| PMP       | on-chip    | arch/riscv       |
-+-----------+------------+------------------+
-| INTMTRX   | on-chip    | intc_esp32c3     |
-+-----------+------------+------------------+
-| PINMUX    | on-chip    | pinctrl_esp32    |
-+-----------+------------+------------------+
-| USB UART  | on-chip    | serial_esp32_usb |
-+-----------+------------+------------------+
-| GPIO      | on-chip    | gpio_esp32       |
-+-----------+------------+------------------+
-| UART      | on-chip    | uart_esp32       |
-+-----------+------------+------------------+
-| I2C       | on-chip    | i2c_esp32        |
-+-----------+------------+------------------+
-| SPI       | on-chip    | spi_esp32_spim   |
-+-----------+------------+------------------+
-| TWAI      | on-chip    | can_esp32_twai   |
-+-----------+------------+------------------+
-
+.. zephyr:board-supported-hw::
 
 Prerequisites
 *************
@@ -53,6 +30,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/m5stack/stamp_c3/stamp_c3.dts b/boards/m5stack/stamp_c3/stamp_c3.dts
index cbd3a3fdd92..800ae9f36c0 100644
--- a/boards/m5stack/stamp_c3/stamp_c3.dts
+++ b/boards/m5stack/stamp_c3/stamp_c3.dts
@@ -96,3 +96,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/m5stack/stamp_c3/stamp_c3_defconfig b/boards/m5stack/stamp_c3/stamp_c3_defconfig
index ef633ce56a1..187793c76e8 100644
--- a/boards/m5stack/stamp_c3/stamp_c3_defconfig
+++ b/boards/m5stack/stamp_c3/stamp_c3_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/madmachine/mm_feather/doc/index.rst b/boards/madmachine/mm_feather/doc/index.rst
index 7c1b985fc70..c717db21baa 100644
--- a/boards/madmachine/mm_feather/doc/index.rst
+++ b/boards/madmachine/mm_feather/doc/index.rst
@@ -44,33 +44,7 @@ Hardware
 Supported Features
 ==================
 
-The mm_feather board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| DISPLAY   | on-chip    | display                             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| I2S       | on-chip    | I2S                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -166,8 +140,10 @@ The Swift ID is not the same as the Zephyr driver ID.
 +-----------+---------------+----------+---------------+----------+---------------+
 
 
-Programming and Flash
-*************************
+Programming and Flashing
+************************
+
+.. zephyr:board-supported-runners::
 
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/madmachine/mm_feather/mm_feather.dts b/boards/madmachine/mm_feather/mm_feather.dts
index 0b655edd1c2..ea9dd21d797 100644
--- a/boards/madmachine/mm_feather/mm_feather.dts
+++ b/boards/madmachine/mm_feather/mm_feather.dts
@@ -56,6 +56,7 @@
 
 
 &flexspi {
+	status = "okay";
 	reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
 	is25wp064: is25wp064@0 {
 		compatible = "nxp,imx-flexspi-nor";
diff --git a/boards/madmachine/mm_feather/mm_feather.yaml b/boards/madmachine/mm_feather/mm_feather.yaml
index a8af021d856..a4541bc88a8 100644
--- a/boards/madmachine/mm_feather/mm_feather.yaml
+++ b/boards/madmachine/mm_feather/mm_feather.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32768
 flash: 8192
 supported:
diff --git a/boards/madmachine/mm_swiftio/doc/index.rst b/boards/madmachine/mm_swiftio/doc/index.rst
index 6845fa1fa36..80cff7d6c96 100644
--- a/boards/madmachine/mm_swiftio/doc/index.rst
+++ b/boards/madmachine/mm_swiftio/doc/index.rst
@@ -26,31 +26,7 @@ Hardware
 Supported Features
 ==================
 
-The mm_swiftio board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| DISPLAY   | on-chip    | display                             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -166,10 +142,12 @@ The Swift ID is not the same as the Zephyr driver ID.
 +-----------+---------------+----------+---------------+----------+---------------+
 
 
-Programming and Flash
-*************************
+Programming and Flashing
+************************
+
+.. zephyr:board-supported-runners::
 
-Build  applications as usual (see :ref:`build_an_application` for more details).
+Build applications as usual (see :ref:`build_an_application` for more details).
 
 Configuring a Debug Probe
 =========================
diff --git a/boards/madmachine/mm_swiftio/mm_swiftio.dts b/boards/madmachine/mm_swiftio/mm_swiftio.dts
index cbdf85c3c12..814c448c1d8 100644
--- a/boards/madmachine/mm_swiftio/mm_swiftio.dts
+++ b/boards/madmachine/mm_swiftio/mm_swiftio.dts
@@ -56,6 +56,7 @@
 
 
 &flexspi {
+	status = "okay";
 	reg = <0x402a8000 0x4000>, <0x60000000 DT_SIZE_M(8)>;
 	is25wp064: is25wp064@0 {
 		compatible = "nxp,imx-flexspi-nor";
diff --git a/boards/madmachine/mm_swiftio/mm_swiftio.yaml b/boards/madmachine/mm_swiftio/mm_swiftio.yaml
index cc27cbe2540..dbd5b79b7b6 100644
--- a/boards/madmachine/mm_swiftio/mm_swiftio.yaml
+++ b/boards/madmachine/mm_swiftio/mm_swiftio.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32768
 flash: 8192
 supported:
diff --git a/boards/makerbase/mks_canable_v20/doc/index.rst b/boards/makerbase/mks_canable_v20/doc/index.rst
index 0a86e6fa6fc..abc27df5189 100644
--- a/boards/makerbase/mks_canable_v20/doc/index.rst
+++ b/boards/makerbase/mks_canable_v20/doc/index.rst
@@ -30,27 +30,7 @@ More information about STM32G431KB can be found here:
 Supported Features
 ==================
 
-The Zephyr ``mks_canable_v20`` board target supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | universal-serial-bus                |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| FDCAN     | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/makerbase/mks_canable_v20/mks_canable_v20_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -84,6 +64,8 @@ The FDCAN1 peripheral is driven by PLLQ, which has 80 MHz frequency.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 MKS CANable V2.0 board includes an SWDIO debug connector header J4.
 
 .. note::
diff --git a/boards/makerdiary/nrf52832_mdk/nrf52832_mdk.yaml b/boards/makerdiary/nrf52832_mdk/nrf52832_mdk.yaml
index 68b42cf5afa..3218983ff38 100644
--- a/boards/makerdiary/nrf52832_mdk/nrf52832_mdk.yaml
+++ b/boards/makerdiary/nrf52832_mdk/nrf52832_mdk.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 512
 supported:
diff --git a/boards/makerdiary/nrf52840_mdk/nrf52840_mdk.yaml b/boards/makerdiary/nrf52840_mdk/nrf52840_mdk.yaml
index c3be56dacaa..79d62b2bf32 100644
--- a/boards/makerdiary/nrf52840_mdk/nrf52840_mdk.yaml
+++ b/boards/makerdiary/nrf52840_mdk/nrf52840_mdk.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - usb_device
   - ble
diff --git a/boards/makerdiary/nrf52840_mdk_usb_dongle/doc/index.rst b/boards/makerdiary/nrf52840_mdk_usb_dongle/doc/index.rst
index ac4743c7748..83b5621bee8 100644
--- a/boards/makerdiary/nrf52840_mdk_usb_dongle/doc/index.rst
+++ b/boards/makerdiary/nrf52840_mdk_usb_dongle/doc/index.rst
@@ -3,24 +3,40 @@
 Overview
 ********
 
-The nRF52840 MDK USB Dongle is a small and low-cost development platform enabled
-by the nRF5240 multiprotocol SoC in a convenient USB dongle form factor.
+The nRF52840 MDK USB Dongle is a small and low-cost development platform
+enabled by the nRF52840 multiprotocol SoC in a convenient USB dongle
+form factor.
 
-The design features a programmable user button, RGB LED, up to 12 GPIOs and 2.4G
-Chip antenna on board. It can be used as a low-cost
-Bluetooth5/Tread/802.15.4/ANT/2.4GHz multiprotocol node or development
-board. Alternatively the USB Dongle can be used as a Network Co-Processor(NCP)
-with a simple connection to a PC or other USB enabled device.
+Hardware
+********
+
+The design features:
+
+* Programmable user button
+* RGB LED
+* Up to 12 GPIOs
+* 2.4 GHz chip antenna
 
-See `nrf52840-mdk-usb-dongle website`_ for more information about the development
-board and `nRF52840 website`_ for the official reference on the IC itself.
+The USB Dongle can be used as:
 
+* A low-cost Bluetooth 5/Thread/802.15.4/ANT/2.4GHz multiprotocol node
+* A development board
+* A Network Co-Processor (NCP) with a simple connection to a PC or other USB enabled device
+
+For more information:
+
+* See the `nrf52840-mdk-usb-dongle website`_ for details about the development board
+* See the `nRF52840 website`_ for the official reference on the IC itself
+* See the `nrf52840-mdk-usb-dongle pinout diagram`_ for details about the pin usage of the board
 
 References
 **********
+
 .. target-notes::
 
 .. _nRF52840 website:
    https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52840
 .. _nrf52840-mdk-usb-dongle website:
    https://wiki.makerdiary.com/nrf52840-mdk-usb-dongle/
+.. _nrf52840-mdk-usb-dongle pinout diagram:
+    https://wiki.makerdiary.com/nrf52840-mdk-usb-dongle/assets/attachments/nrf52840-mdk-usb-dongle-pinout_v1_1.pdf
diff --git a/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml b/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml
index e714e1cafb5..f0fa9668e55 100644
--- a/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml
+++ b/boards/makerdiary/nrf52840_mdk_usb_dongle/nrf52840_mdk_usb_dongle.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - usb_device
   - ble
diff --git a/boards/mediatek/mt8186/afe-mt8186.dts b/boards/mediatek/mt8186/afe-mt8186.dts
new file mode 100644
index 00000000000..e6bd2ac557c
--- /dev/null
+++ b/boards/mediatek/mt8186/afe-mt8186.dts
@@ -0,0 +1,54 @@
+	afe_dl1: afe_dl1 {
+		compatible = "mediatek,afe";
+		afe-name = "DL1";
+		dai-id = <0>;
+		downlink;
+		base = <0x11210050 0x11210054>;
+		cur = <0x11210058 0x1121005c>;
+		end = <0x11210060 0x11210064>;
+		fs = <0x1121004c 24 4>;
+		mono = <0x1121004c 8 1>;
+		enable = <0x11210010 4 1>;
+		hd = <0x1121004c 0 1>;
+	};
+
+	afe_dl2: afe_dl2 {
+		compatible = "mediatek,afe";
+		afe-name = "DL2";
+		dai-id = <1>;
+		downlink;
+		base = <0x1121006c 0x11210070>;
+		cur = <0x11210074 0x11210078>;
+		end = <0x1121007c 0x11210080>;
+		fs = <0x11210068 24 4>;
+		mono = <0x11210068 8 1>;
+		enable = <0x11210010 5 1>;
+		hd = <0x11210068 0 1>;
+	};
+
+	afe_ul1: afe_ul1 {
+		compatible = "mediatek,afe";
+		afe-name = "UL1";
+		dai-id = <2>;
+		base = <0x11210378 0x1121037c>;
+		cur = <0x11210380 0x11210384>;
+		end = <0x11210388 0x1121038c>;
+		fs = <0x11210374 24 4>;
+		mono = <0x11210374 8 1>;
+		quad-ch = <0x11210374 11 1>;
+		enable = <0x11210010 31 1>;
+		hd = <0x11210374 0 1>;
+	};
+
+	afe_ul2: afe_ul2 {
+		compatible = "mediatek,afe";
+		afe-name = "UL2";
+		dai-id = <3>;
+		base = <0x11210860 0x11210864>;
+		cur = <0x11210868 0x1121086c>;
+		end = <0x11210870 0x11210874>;
+		fs = <0x1121085c 24 4>;
+		mono = <0x1121085c 8 1>;
+		enable = <0x11210010 16 1>;
+		hd = <0x1121085c 0 1>;
+	};
diff --git a/boards/mediatek/mt8188/afe-mt8188.dts b/boards/mediatek/mt8188/afe-mt8188.dts
new file mode 100644
index 00000000000..fbe47f5a2b4
--- /dev/null
+++ b/boards/mediatek/mt8188/afe-mt8188.dts
@@ -0,0 +1,67 @@
+	afe_dl2: afe_dl2 {
+		compatible = "mediatek,afe";
+		afe-name = "DL2";
+		dai-id = <0>;
+		downlink;
+		base = <0x00000000 0x10b11250>;
+		cur = <0x00000000 0x10b11254>;
+		end = <0x00000000 0x10b11258>;
+		fs = <0x10b115a0 10 5>;
+		enable = <0x10b11200 18 1>;
+		hd = <0x10b1125c 5 1>;
+		msb = <0x10b1192c 18 1>;
+		msb2 = <0x10b11930 18 1>;
+		agent-disable = <0x10b10014 18 1>;
+		ch-num = <0x10b1125c 0 5>;
+	};
+
+	afe_dl3: afe_dl3 {
+		compatible = "mediatek,afe";
+		afe-name = "DL3";
+		dai-id = <1>;
+		downlink;
+		base = <0x00000000 0x10b11260>;
+		cur = <0x00000000 0x10b11264>;
+		end = <0x00000000 0x10b11268>;
+		fs = <0x10b115a0 15 5>;
+		enable = <0x10b11200 19 1>;
+		hd = <0x10b1126c 5 1>;
+		msb = <0x10b1192c 19 1>;
+		msb2 = <0x10b11930 19 1>;
+		agent-disable = <0x10b10014 19 1>;
+		ch-num = <0x10b1126c 0 5>;
+	};
+
+	afe_ul4: afe_ul4 {
+		compatible = "mediatek,afe";
+		afe-name = "UL4";
+		dai-id = <2>;
+		base = <0x00000000 0x10b11330>;
+		cur = <0x00000000 0x10b11334>;
+		end = <0x00000000 0x10b11338>;
+		fs = <0x10b115a8 15 5>;
+		mono = <0x10b1133c 1 1>;
+		int-odd = <0x10b1133c 0 1>;
+		enable = <0x10b11200 4 1>;
+		hd = <0x10b1133c 5 1>;
+		msb = <0x10b1192c 3 1>;
+		msb2 = <0x10b11930 3 1>;
+		agent-disable = <0x10b10014 3 1>;
+	};
+
+	afe_ul5: afe_ul5 {
+		compatible = "mediatek,afe";
+		afe-name = "UL5";
+		dai-id = <3>;
+		base = <0x00000000 0x10b11340>;
+		cur = <0x00000000 0x10b11344>;
+		end = <0x00000000 0x10b11348>;
+		fs = <0x10b115a8 20 5>;
+		mono = <0x10b1134c 1 1>;
+		int-odd = <0x10b1134c 0 1>;
+		enable = <0x10b11200 5 1>;
+		hd = <0x10b1134c 5 1>;
+		msb = <0x10b1192c 4 1>;
+		msb2 = <0x10b11930 4 1>;
+		agent-disable = <0x10b10014 4 1>;
+	};
diff --git a/boards/mediatek/mt8195/afe-mt8195.dts b/boards/mediatek/mt8195/afe-mt8195.dts
new file mode 100644
index 00000000000..37b335754df
--- /dev/null
+++ b/boards/mediatek/mt8195/afe-mt8195.dts
@@ -0,0 +1,65 @@
+	afe_dl2: afe_dl2 {
+		compatible = "mediatek,afe";
+		afe-name = "DL2";
+		dai-id = <0>;
+		downlink;
+		base = <0x00000000 0x10891250>;
+		cur = <0x00000000 0x10891254>;
+		end = <0x00000000 0x10891258>;
+		fs = <0x108915a0 10 5>;
+		enable = <0x10891200 18 1>;
+		hd = <0x1089125c 5 1>;
+		msb = <0x1089192c 18 1>;
+		msb2 = <0x10891930 18 1>;
+		agent-disable = <0x10890014 18 1>;
+		ch-num = <0x1089125c 0 5>;
+	};
+
+	afe_dl3: afe_dl3 {
+		compatible = "mediatek,afe";
+		afe-name = "DL3";
+		dai-id = <1>;
+		downlink;
+		base = <0x00000000 0x10891260>;
+		cur = <0x00000000 0x10891264>;
+		end = <0x00000000 0x10891268>;
+		fs = <0x108915a0 15 5>;
+		enable = <0x10891200 19 1>;
+		hd = <0x1089126c 5 1>;
+		msb = <0x1089192c 19 1>;
+		msb2 = <0x10891930 19 1>;
+		agent-disable = <0x10890014 19 1>;
+		ch-num = <0x1089126c 0 5>;
+	};
+
+	afe_ul4: afe_ul4 {
+		compatible = "mediatek,afe";
+		afe-name = "UL4";
+		dai-id = <2>;
+		base = <0x00000000 0x10891330>;
+		cur = <0x00000000 0x10891334>;
+		end = <0x00000000 0x10891338>;
+		fs = <0x108915a8 15 5>;
+		mono = <0x1089133c 1 1>;
+		enable = <0x10891200 4 1>;
+		hd = <0x1089133c 5 1>;
+		msb = <0x1089192c 3 1>;
+		msb2 = <0x10891930 3 1>;
+		agent-disable = <0x10890014 3 1>;
+	};
+
+	afe_ul5: afe_ul5 {
+		compatible = "mediatek,afe";
+		afe-name = "UL5";
+		dai-id = <3>;
+		base = <0x00000000 0x10891340>;
+		cur = <0x00000000 0x10891344>;
+		end = <0x00000000 0x10891348>;
+		fs = <0x108915a8 20 5>;
+		mono = <0x1089134c 1 1>;
+		enable = <0x10891200 5 1>;
+		hd = <0x1089134c 5 1>;
+		msb = <0x1089192c 4 1>;
+		msb2 = <0x10891930 4 1>;
+		agent-disable = <0x10890014 4 1>;
+	};
diff --git a/boards/mediatek/mt8195/mt8195_adsp.dts b/boards/mediatek/mt8195/mt8195_adsp.dts
index 76a2b94415a..53346746041 100644
--- a/boards/mediatek/mt8195/mt8195_adsp.dts
+++ b/boards/mediatek/mt8195/mt8195_adsp.dts
@@ -34,9 +34,9 @@
 		cpuclk: cpuclk@10000000 {
 			compatible = "mediatek,mt8195_cpuclk";
 			reg = <0x10000000 380>;
-			cg_reg = <0x10720180>;
-			pll_ctrl_reg = <0x1000c7e0>;
-			freqs_mhz = <26 370 540 720>;
+			cg-reg = <0x10720180>;
+			pll-ctrl-reg = <0x1000c7e0>;
+			freqs-mhz = <26 370 540 720>;
 		};
 
 		core_intc: core_intc@0 {
diff --git a/boards/mediatek/mt8196/afe-mt8196.dts b/boards/mediatek/mt8196/afe-mt8196.dts
new file mode 100644
index 00000000000..a28d9f658e1
--- /dev/null
+++ b/boards/mediatek/mt8196/afe-mt8196.dts
@@ -0,0 +1,66 @@
+	afe_dl1: afe_dl1 {
+		compatible = "mediatek,afe";
+		afe-name = "DL1";
+		dai-id = <1>;
+		downlink;
+		base = <0x1a114470 0x1a114474>;
+		cur = <0x1a114478 0x1a11447c>;
+		end = <0x1a114480 0x1a114484>;
+		fs = <0x1a114490 8 5>;
+		mono = <0x1a114490 4 1>;
+		enable = <0x1a114490 28 1>;
+		hd = <0x1a114490 0 1>;
+	};
+
+	afe_dl_24ch: afe_dl_24ch {
+		compatible = "mediatek,afe";
+		afe-name = "DL_24CH";
+		dai-id = <0>;
+		downlink;
+		base = <0x1a114620 0x1a114624>;
+		cur = <0x1a114628 0x1a11462c>;
+		end = <0x1a114630 0x1a114634>;
+		fs = <0x1a114640 8 5>;
+		enable = <0x1a114640 31 1>;
+		hd = <0x1a114640 0 1>;
+		ch-num = <0x1a114640 24 6>;
+	};
+
+	afe_ul0: afe_ul0 {
+		compatible = "mediatek,afe";
+		afe-name = "UL0";
+		dai-id = <2>;
+		base = <0x1a114d60 0x1a114d64>;
+		cur = <0x1a114d68 0x1a114d6c>;
+		end = <0x1a114d70 0x1a114d74>;
+		fs = <0x1a114d80 8 5>;
+		mono = <0x1a114d80 4 1>;
+		enable = <0x1a114d80 28 1>;
+		hd = <0x1a114d80 0 1>;
+	};
+
+	afe_ul1: afe_ul1 {
+		compatible = "mediatek,afe";
+		afe-name = "UL1";
+		dai-id = <3>;
+		base = <0x1a114d90 0x1a114d94>;
+		cur = <0x1a114d98 0x1a114d9c>;
+		end = <0x1a114da0 0x1a114da4>;
+		fs = <0x1a114db0 8 5>;
+		mono = <0x1a114db0 4 1>;
+		enable = <0x1a114db0 28 1>;
+		hd = <0x1a114db0 0 1>;
+	};
+
+	afe_ul2: afe_ul2 {
+		compatible = "mediatek,afe";
+		afe-name = "UL2";
+		dai-id = <4>;
+		base = <0x1a114dc0 0x1a114dc4>;
+		cur = <0x1a114dc8 0x1a114dcc>;
+		end = <0x1a114dd0 0x1a114dd4>;
+		fs = <0x1a114de0 8 5>;
+		mono = <0x1a114de0 4 1>;
+		enable = <0x1a114de0 28 1>;
+		hd = <0x1a114de0 0 1>;
+	};
diff --git a/boards/mediatek/mt8196/mt8196_adsp.dts b/boards/mediatek/mt8196/mt8196_adsp.dts
index 27fc2f0048a..f8bee05bbe4 100644
--- a/boards/mediatek/mt8196/mt8196_adsp.dts
+++ b/boards/mediatek/mt8196/mt8196_adsp.dts
@@ -101,6 +101,10 @@
 			interrupt-parent = <&intc_g2>;
 			interrupts = <7 0 0>;
 		};
+
+/* Generated code for AFE devices */
+#include "afe-mt8196.dts"
+
 	}; /* soc */
 
 	chosen { };
diff --git a/boards/microchip/ev11l78a/doc/index.rst b/boards/microchip/ev11l78a/doc/index.rst
index 95d05add0c0..15661123062 100644
--- a/boards/microchip/ev11l78a/doc/index.rst
+++ b/boards/microchip/ev11l78a/doc/index.rst
@@ -20,51 +20,10 @@ Hardware
 Supported Features
 ==================
 
-The ev11l78a board configuration supports the following hardware
-features:
-
-
-.. list-table::
-    :header-rows: 1
-
-    * - Interface
-      - Controller
-      - Driver / Component
-    * - NVIC
-      - on-chip
-      - nested vector interrupt controller
-    * - Flash
-      - on-chip
-      - Can be used with LittleFS to store files
-    * - SYSTICK
-      - on-chip
-      - systick
-    * - WDT
-      - on-chip
-      - Watchdog
-    * - ADC
-      - on-chip
-      - Analog to Digital Converter
-    * - GPIO
-      - on-chip
-      - I/O ports
-    * - USART
-      - on-chip
-      - Serial ports
-    * - I2C
-      - on-chip
-      - I2C ports
-    * - SPI
-      - on-chip
-      - Serial Peripheral Interface ports
-
-Other hardware features are not currently supported by Zephyr.
+.. zephyr:board-supported-hw::
 
 Refer to the `EV11L78A Schematics`_ for a detailed hardware diagram.
 
-The default configuration can be found in the Kconfig
-:zephyr_file:`boards/microchip/ev11l78a/ev11l78a_defconfig`.
-
 Serial Port
 ===========
 
diff --git a/boards/microchip/ev11l78a/ev11l78a.yaml b/boards/microchip/ev11l78a/ev11l78a.yaml
index f9b2a1a53a2..88417ca90d9 100644
--- a/boards/microchip/ev11l78a/ev11l78a.yaml
+++ b/boards/microchip/ev11l78a/ev11l78a.yaml
@@ -7,7 +7,6 @@ flash: 64
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - gpio
diff --git a/boards/microchip/m2gl025_miv/doc/index.rst b/boards/microchip/m2gl025_miv/doc/index.rst
index 88a4fa2b951..d48d0bebcab 100644
--- a/boards/microchip/m2gl025_miv/doc/index.rst
+++ b/boards/microchip/m2gl025_miv/doc/index.rst
@@ -11,6 +11,8 @@ More information can be found on
 Programming and debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Building
 ========
 
diff --git a/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig b/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig
index 0ca8a90ad48..0b7eb516d7e 100644
--- a/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig
+++ b/boards/microchip/mec1501modular_assy6885/Kconfig.defconfig
@@ -3,40 +3,11 @@
 
 if BOARD_MEC1501MODULAR_ASSY6885
 
-config INPUT
-	default y if KSCAN
-
 #PS/2 driver is compiled in terms of this flag.
 config ESPI_PERIPHERAL_8042_KBC
 	default y
 	depends on ESPI_XEC
 
-if RTOS_TIMER
-
-# XEC RTOS timer HW frequency is fixed at 32768
-# The driver requires tickless mode and ticks per
-# second to be 32768 for accurate operation.
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 32768
-
-config SYS_CLOCK_TICKS_PER_SEC
-	default 32768
-
-endif # RTOS_TIMER
-
-if !RTOS_TIMER
-
-# If RTOS timer is not enabled we use ARM Cortex-M
-# SYSTICK. SYSTICK frequency is 48MHz divided by
-# SOC_MEC1501_PROC_CLK_DIV.
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 48000000
-
-config SYS_CLOCK_TICKS_PER_SEC
-	default 1000
-
 if ESPI
 
 config ESPI_PERIPHERAL_UART_SOC_MAPPING
@@ -44,6 +15,4 @@ config ESPI_PERIPHERAL_UART_SOC_MAPPING
 
 endif # ESPI
 
-endif # RTOS_TIMER
-
 endif # BOARD_MEC1501MODULAR_ASSY6885
diff --git a/boards/microchip/mec1501modular_assy6885/doc/index.rst b/boards/microchip/mec1501modular_assy6885/doc/index.rst
index 910ba104da1..8a65f871360 100644
--- a/boards/microchip/mec1501modular_assy6885/doc/index.rst
+++ b/boards/microchip/mec1501modular_assy6885/doc/index.rst
@@ -45,44 +45,7 @@ For more information about the SOC please see the `MEC152x Reference Manual`_
 Supported Features
 ==================
 
-The mec1501modular_assy6885 board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| ESPI      | on-chip    | espi                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| RTOS      | on-chip    | timer                               |
-+-----------+------------+-------------------------------------+
-| TIMER     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| PS2       | on-chip    | ps2                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by Zephyr (at the moment)
-
-The default configuration can be found in the
-:zephyr_file:`boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig`
-Kconfig file.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -225,6 +188,8 @@ Jumper location map
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Setup
 =====
 
diff --git a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts
index 856069de406..7c5c131cf52 100644
--- a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts
+++ b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.dts
@@ -17,7 +17,6 @@
 		zephyr,sram = &sram0;
 		zephyr,console = &uart1;
 		zephyr,flash = &flash0;
-		zephyr,keyboard-scan = &kscan_input;
 	};
 
 	aliases {
@@ -26,7 +25,6 @@
 
 		i2c0 = &i2c_smb_0;
 		i2c1 = &i2c_smb_1;
-		kscan0 = &kscan_input;
 		watchdog0 = &wdog;
 	};
 };
@@ -52,7 +50,7 @@
 
 &i2c_smb_0 {
 	status = "okay";
-	port_sel = <0>;
+	port-sel = <0>;
 	sda-gpios = <MCHP_GPIO_DECODE_003 0>;
 	scl-gpios = <MCHP_GPIO_DECODE_004 0>;
 	pinctrl-0 = < &i2c00_scl_gpio004 &i2c00_sda_gpio003 >;
@@ -61,7 +59,7 @@
 
 &i2c_smb_1 {
 	status = "okay";
-	port_sel = <1>;
+	port-sel = <1>;
 	sda-gpios = <MCHP_GPIO_DECODE_130 0>;
 	scl-gpios = <MCHP_GPIO_DECODE_131 0>;
 	pinctrl-0 = < &i2c01_scl_gpio131 &i2c01_sda_gpio130 >;
@@ -70,9 +68,9 @@
 
 &espi0 {
 	status = "okay";
-	io_girq = <19>;
-	vw_girqs = <24 25>;
-	pc_girq = <15>;
+	io-girq = <19>;
+	vw-girqs = <24 25>;
+	pc-girq = <15>;
 	pinctrl-0 = < &espi_reset_n_gpio061 &espi_cs_n_gpio066
 		  &espi_alert_n_gpio063 &espi_clk_gpio065
 		  &espi_io0_gpio070 &espi_io1_gpio071
@@ -120,10 +118,6 @@
 	pinctrl-names = "default", "sleep";
 	row-size = <8>;
 	col-size = <16>;
-
-	kscan_input: kscan-input {
-		compatible = "zephyr,kscan-input";
-	};
 };
 
 &peci0 {
diff --git a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.yaml b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.yaml
index d78477f825f..da7c46a8a54 100644
--- a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.yaml
+++ b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885.yaml
@@ -21,6 +21,5 @@ supported:
   - i2c
   - pwm
   - watchdog
-  - kscan
   - tach
 vendor: microchip
diff --git a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig
index 3039d18174e..164cb7182e7 100644
--- a/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig
+++ b/boards/microchip/mec1501modular_assy6885/mec1501modular_assy6885_defconfig
@@ -7,12 +7,9 @@
 # Make sure external power management setup is as indicated in documentation
 CONFIG_SOC_MEC1501_VTR3_1_8V=y
 CONFIG_SOC_MEC1501_VCI_PINS_AS_GPIOS=n
-CONFIG_RTOS_TIMER=y
 
 CONFIG_CLOCK_CONTROL=y
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_GPIO=y
-
-CONFIG_PM=y
diff --git a/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig b/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig
index 229ba41dff7..01a7081bcf4 100644
--- a/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig
+++ b/boards/microchip/mec15xxevb_assy6853/Kconfig.defconfig
@@ -3,40 +3,8 @@
 
 if BOARD_MEC15XXEVB_ASSY6853
 
-config INPUT
-	default y if KSCAN
-
 config ESPI_XEC
 	default y
 	depends on ESPI
 
-if RTOS_TIMER
-
-# XEC RTOS timer HW frequency is fixed at 32768
-# The driver requires tickless mode and ticks per
-# second to be 32768 for accurate operation.
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 32768
-
-config SYS_CLOCK_TICKS_PER_SEC
-	default 32768
-
-endif # RTOS_TIMER
-
-if !RTOS_TIMER
-
-# If RTOS timer is not enabled we use ARM Cortex-M
-# SYSTICK. SYSTICK frequency is 48MHz divided by
-# SOC_MEC1501_PROC_CLK_DIV.
-#
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 48000000
-
-config SYS_CLOCK_TICKS_PER_SEC
-	default 1000
-
-endif # RTOS_TIMER
-
 endif # BOARD_MEC15XXEVB_ASSY6853
diff --git a/boards/microchip/mec15xxevb_assy6853/doc/index.rst b/boards/microchip/mec15xxevb_assy6853/doc/index.rst
index c712d74b563..9a3c9e22aeb 100644
--- a/boards/microchip/mec15xxevb_assy6853/doc/index.rst
+++ b/boards/microchip/mec15xxevb_assy6853/doc/index.rst
@@ -42,38 +42,7 @@ For more information about the SOC's please see `MEC152x Reference Manual`_
 Supported Features
 ==================
 
-The mec15xxevb_assy6853 board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| PS/2      | on-chip    | ps2                                 |
-+-----------+------------+-------------------------------------+
-| KSCAN     | on-chip    | kscan                               |
-+-----------+------------+-------------------------------------+
-| TACH      | on-chip    | tachometer                          |
-+-----------+------------+-------------------------------------+
-
-
-
-
-Other hardware features are not currently supported by Zephyr (at the moment)
-
-The default configuration can be found in the
-:zephyr_file:`boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig` Kconfig file.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -233,6 +202,8 @@ in reference section below.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Setup
 =====
 #. If you use Dediprog SF100 programmer, then setup it.
diff --git a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts
index a70db14a3eb..fbc1aa677af 100644
--- a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts
+++ b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.dts
@@ -16,7 +16,6 @@
 		zephyr,sram = &sram0;
 		zephyr,console = &uart2;
 		zephyr,flash = &flash0;
-		zephyr,keyboard-scan = &kscan_input;
 	};
 
 	aliases {
@@ -29,7 +28,6 @@
 		i2c-0 = &i2c_smb_0;
 		i2c1 = &i2c_smb_1;
 		i2c7 = &i2c_smb_2;
-		kscan0 = &kscan_input;
 		watchdog0 = &wdog;
 	};
 
@@ -80,7 +78,7 @@
 
 &i2c_smb_0 {
 	status = "okay";
-	port_sel = <0>;
+	port-sel = <0>;
 	sda-gpios = <MCHP_GPIO_DECODE_003 0>;
 	scl-gpios = <MCHP_GPIO_DECODE_004 0>;
 	pinctrl-0 = < &i2c00_scl_gpio004 &i2c00_sda_gpio003 >;
@@ -89,7 +87,7 @@
 
 &i2c_smb_1 {
 	status = "okay";
-	port_sel = <1>;
+	port-sel = <1>;
 	sda-gpios = <MCHP_GPIO_DECODE_130 0>;
 	scl-gpios = <MCHP_GPIO_DECODE_131 0>;
 	pinctrl-0 = < &i2c01_scl_gpio131 &i2c01_sda_gpio130 >;
@@ -114,7 +112,7 @@
 
 &i2c_smb_2 {
 	status = "okay";
-	port_sel = <7>;
+	port-sel = <7>;
 	sda-gpios = <MCHP_GPIO_DECODE_012 0>;
 	scl-gpios = <MCHP_GPIO_DECODE_013 0>;
 	pinctrl-0 = < &i2c07_scl_gpio013 &i2c07_sda_gpio012 >;
@@ -123,9 +121,9 @@
 
 &espi0 {
 	status = "okay";
-	io_girq = <19>;
-	vw_girqs = <24 25>;
-	pc_girq = <15>;
+	io-girq = <19>;
+	vw-girqs = <24 25>;
+	pc-girq = <15>;
 	pinctrl-0 = < &espi_reset_n_gpio061 &espi_cs_n_gpio066
 		  &espi_alert_n_gpio063 &espi_clk_gpio065
 		  &espi_io0_gpio070 &espi_io1_gpio071
@@ -177,10 +175,6 @@
 	pinctrl-names = "default", "sleep";
 	row-size = <8>;
 	col-size = <16>;
-
-	kscan_input: kscan-input {
-		compatible = "zephyr,kscan-input";
-	};
 };
 
 &peci0 {
diff --git a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.yaml b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.yaml
index 8b8190d20d8..afd985cb020 100644
--- a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.yaml
+++ b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853.yaml
@@ -21,5 +21,4 @@ supported:
   - i2c
   - pwm
   - watchdog
-  - kscan
 vendor: microchip
diff --git a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig
index 51e8498df60..731a1c2d63f 100644
--- a/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig
+++ b/boards/microchip/mec15xxevb_assy6853/mec15xxevb_assy6853_defconfig
@@ -5,13 +5,9 @@
 #
 
 CONFIG_SOC_MEC1501_VTR3_1_8V=y
-CONFIG_RTOS_TIMER=y
 
 CONFIG_CLOCK_CONTROL=y
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_GPIO=y
-
-# power management stuff
-CONFIG_PM=y
diff --git a/boards/microchip/mec172xevb_assy6906/Kconfig.defconfig b/boards/microchip/mec172xevb_assy6906/Kconfig.defconfig
deleted file mode 100644
index 2c93b83e744..00000000000
--- a/boards/microchip/mec172xevb_assy6906/Kconfig.defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-# Copyright (c) 2021 Microchip Technology Inc.
-# SPDX-License-Identifier: Apache-2.0
-
-if BOARD_MEC172XEVB_ASSY6906
-
-config INPUT
-	default y if KSCAN
-
-if RTOS_TIMER
-
-# XEC RTOS timer HW frequency is fixed at 32768 Hz.
-# The driver requires tickless mode and ticks per second to be 32768 for
-# accurate operation.
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 32768
-
-config SYS_CLOCK_TICKS_PER_SEC
-	default 32768
-
-endif # RTOS_TIMER
-
-if !RTOS_TIMER
-
-# If RTOS timer is not enabled we use ARM Cortex-M
-# SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR
-# processor clock divider register. We assume PCR processor clock divider
-# is set to 1. Refer to SOC_MEC_PROC_CLK_DIV
-#
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 96000000
-
-config SYS_CLOCK_TICKS_PER_SEC
-	default 1000
-
-endif # RTOS_TIMER
-
-endif # BOARD_MEC172XEVB_ASSY6906
diff --git a/boards/microchip/mec172xevb_assy6906/doc/index.rst b/boards/microchip/mec172xevb_assy6906/doc/index.rst
index 0671beb4143..b05c4d5bd3f 100644
--- a/boards/microchip/mec172xevb_assy6906/doc/index.rst
+++ b/boards/microchip/mec172xevb_assy6906/doc/index.rst
@@ -36,37 +36,7 @@ For more information about the SOC's please see `MEC172x Reference Manual`_
 Supported Features
 ==================
 
-The mec172xevb_assy6906 board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| PS/2      | on-chip    | ps2                                 |
-+-----------+------------+-------------------------------------+
-| KSCAN     | on-chip    | kscan                               |
-+-----------+------------+-------------------------------------+
-| TACH      | on-chip    | tachometer                          |
-+-----------+------------+-------------------------------------+
-| RPMFAN    | on-chip    | Fan speed controller                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the
-:zephyr_file:`boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig` Kconfig file.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -260,6 +230,8 @@ NOTE: ``JP121 3-4`` on base board also needs to be loaded.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Setup
 =====
 
diff --git a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts
index c0427d03d3d..bc2ad391664 100644
--- a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts
+++ b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906.dts
@@ -125,7 +125,7 @@
 /* I2C */
 &i2c_smb_0 {
 	status = "okay";
-	port_sel = <0>;
+	port-sel = <0>;
 
 	pinctrl-0 = < &i2c00_scl_gpio004 &i2c00_sda_gpio003 >;
 	pinctrl-names = "default";
@@ -145,7 +145,7 @@
 
 &i2c_smb_1 {
 	status = "okay";
-	port_sel = <1>;
+	port-sel = <1>;
 	pinctrl-0 = <&i2c01_scl_gpio131 &i2c01_sda_gpio130>;
 	pinctrl-names = "default";
 
@@ -180,7 +180,7 @@
 
 &i2c_smb_2 {
 	status = "okay";
-	port_sel = <7>;
+	port-sel = <7>;
 	pinctrl-0 = <&i2c07_scl_gpio013 &i2c07_sda_gpio012>;
 	pinctrl-names = "default";
 };
@@ -233,10 +233,6 @@
 	pinctrl-names = "default", "sleep";
 	row-size = <8>;
 	col-size = <16>;
-
-	kscan_input: kscan-input {
-		compatible = "zephyr,kscan-input";
-	};
 };
 
 &ksi0_gpio017 {
diff --git a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig
index d1aeaeaac58..f2b72ae4282 100644
--- a/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig
+++ b/boards/microchip/mec172xevb_assy6906/mec172xevb_assy6906_defconfig
@@ -4,8 +4,6 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-CONFIG_RTOS_TIMER=y
-
 CONFIG_CLOCK_CONTROL=y
 CONFIG_GPIO=y
 CONFIG_SERIAL=y
diff --git a/boards/microchip/mec172xmodular_assy6930/CMakeLists.txt b/boards/microchip/mec172xmodular_assy6930/CMakeLists.txt
index 92626f6319f..6e36ea0dec8 100644
--- a/boards/microchip/mec172xmodular_assy6930/CMakeLists.txt
+++ b/boards/microchip/mec172xmodular_assy6930/CMakeLists.txt
@@ -4,8 +4,6 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-zephyr_library()
-
 #Allow users to pre-specify the tool using '-DMEC172X_SPI_GEN=<path-to-tool>/toolname'
 if (NOT DEFINED MEC172X_SPI_GEN)
   set(MEC172X_SPI_GEN $ENV{MEC172X_SPI_GEN})
diff --git a/boards/microchip/mec172xmodular_assy6930/Kconfig.defconfig b/boards/microchip/mec172xmodular_assy6930/Kconfig.defconfig
deleted file mode 100644
index c3487f561e9..00000000000
--- a/boards/microchip/mec172xmodular_assy6930/Kconfig.defconfig
+++ /dev/null
@@ -1,39 +0,0 @@
-# Copyright (c) 2022 Microchip Technology Inc.
-# SPDX-License-Identifier: Apache-2.0
-
-if BOARD_MEC172XMODULAR_ASSY6930
-
-config INPUT
-	default y if KSCAN
-
-if RTOS_TIMER
-
-# XEC RTOS timer HW frequency is fixed at 32768 Hz.
-# The driver requires tickless mode and ticks per second to be 32768 for
-# accurate operation.
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 32768
-
-config SYS_CLOCK_TICKS_PER_SEC
-	default 32768
-
-endif # RTOS_TIMER
-
-if !RTOS_TIMER
-
-# If RTOS timer is not enabled we use ARM Cortex-M
-# SYSTICK. SYSTICK frequency is 96 MHz divided down by the MEC172x PCR
-# processor clock divider register. We assume PCR processor clock divider
-# is set to 1. Refer to SOC_MEC_PROC_CLK_DIV
-#
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 96000000
-
-config SYS_CLOCK_TICKS_PER_SEC
-	default 1000
-
-endif # RTOS_TIMER
-
-endif # BOARD_MEC172XMODULAR_ASSY6930
diff --git a/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst b/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst
index a6bc75fc8fb..18441232c41 100644
--- a/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst
+++ b/boards/microchip/mec172xmodular_assy6930/doc/mec172xmodular_assy6930.rst
@@ -46,36 +46,7 @@ The board is powered through the +5V USB micro-A connector or from the MECC conn
 Supported Features
 ==================
 
-The mec172xmodular_assy6930 (Rev. B) board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| PS/2      | on-chip    | ps2                                 |
-+-----------+------------+-------------------------------------+
-| KSCAN     | on-chip    | kscan                               |
-+-----------+------------+-------------------------------------+
-| TACH      | on-chip    | tachometer                          |
-+-----------+------------+-------------------------------------+
-| RPMFAN    | on-chip    | Fan speed controller                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by Zephyr (at the moment)
-
-The default configuration can be found in the
-:zephyr_file:`boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig` Kconfig file.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -150,6 +121,8 @@ or Master Attached Flash (MAF).
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Setup
 =====
 
diff --git a/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts
index 94a08cd03f1..e5d7e888baa 100644
--- a/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts
+++ b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930.dts
@@ -119,7 +119,7 @@
 /* I2C */
 &i2c_smb_0 {
 	status = "okay";
-	port_sel = <0>;
+	port-sel = <0>;
 
 	pinctrl-0 = < &i2c00_scl_gpio004 &i2c00_sda_gpio003 >;
 	pinctrl-names = "default";
@@ -139,7 +139,7 @@
 
 &i2c_smb_1 {
 	status = "okay";
-	port_sel = <1>;
+	port-sel = <1>;
 	pinctrl-0 = <&i2c01_scl_gpio131 &i2c01_sda_gpio130>;
 	pinctrl-names = "default";
 };
@@ -158,7 +158,7 @@
 
 &i2c_smb_2 {
 	status = "okay";
-	port_sel = <7>;
+	port-sel = <7>;
 	pinctrl-0 = <&i2c07_scl_gpio013 &i2c07_sda_gpio012>;
 	pinctrl-names = "default";
 };
@@ -211,10 +211,6 @@
 	pinctrl-names = "default", "sleep";
 	row-size = <8>;
 	col-size = <16>;
-
-	kscan_input: kscan-input {
-		compatible = "zephyr,kscan-input";
-	};
 };
 
 &ksi0_gpio017 {
diff --git a/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig
index c191b0b1555..ec6ae819151 100644
--- a/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig
+++ b/boards/microchip/mec172xmodular_assy6930/mec172xmodular_assy6930_defconfig
@@ -4,8 +4,6 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-CONFIG_RTOS_TIMER=y
-
 CONFIG_CLOCK_CONTROL=y
 CONFIG_GPIO=y
 CONFIG_SERIAL=y
diff --git a/boards/microchip/mec_assy6941/CMakeLists.txt b/boards/microchip/mec_assy6941/CMakeLists.txt
new file mode 100644
index 00000000000..84b859f1f17
--- /dev/null
+++ b/boards/microchip/mec_assy6941/CMakeLists.txt
@@ -0,0 +1,59 @@
+#
+# Copyright (c) 2025 Microchip Technology Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if(CONFIG_SOC_SERIES_MEC174X)
+  set(PART_PREFIX mec174x)
+elseif(CONFIG_SOC_SERIES_MEC175X)
+  set(PART_PREFIX mec175x)
+else()
+  message(NOTICE "Unknown SoC series! No SPI image will be generated")
+endif()
+
+if(DEFINED ENV{MEC5_SPI_GEN})
+  # Grab it from environment variable if defined
+  set(MEC5_SPI_GEN $ENV{MEC5_SPI_GEN})
+else()
+  # Else find the tool in PATH
+  if(CMAKE_HOST_APPLE)
+    # CMAKE_HOST_UNIX is also true for Apple,
+    # but there is no tool for Apple. So
+    # we need to skip it.
+    message(NOTICE "There is no SPI image generation tool for MacOS.")
+  elseif(CMAKE_HOST_UNIX)
+    set(MEC5_SPI_GEN_FILENAME ${PART_PREFIX}_spi_gen_linux_x86_64)
+  elseif(CMAKE_HOST_WIN32)
+    set(MEC5_SPI_GEN_FILENAME ${PART_PREFIX}_spi_gen.exe)
+  endif()
+
+  find_file(MEC5_SPI_GEN_FINDFILE ${MEC5_SPI_GEN_FILENAME})
+  if(MEC5_SPI_GEN_FINDFILE STREQUAL MEC5_SPI_GEN_FINDFILE-NOTFOUND)
+    message(WARNING "Microchip SPI Image Generation tool (${MEC5_SPI_GEN_FILENAME}) is not available. SPI Image will not be generated.")
+  else()
+    set(MEC5_SPI_GEN ${MEC5_SPI_GEN_FINDFILE})
+  endif()
+
+  unset(MEC5_SPI_GEN_FINDFILE)
+  unset(MEC5_SPI_GEN_FILENAME)
+endif()
+
+if(DEFINED MEC5_SPI_GEN)
+  if(DEFINED ENV{MEC5_SPI_CFG})
+    set(MEC5_SPI_CFG $ENV{MEC5_SPI_CFG})
+  else()
+    set(MEC5_SPI_CFG ${BOARD_DIR}/support/${PART_PREFIX}_spi_cfg.txt)
+  endif()
+
+  set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+    COMMAND ${MEC5_SPI_GEN}
+    -i ${MEC5_SPI_CFG}
+    -o ${PROJECT_BINARY_DIR}/${SPI_IMAGE_NAME}
+  )
+
+  unset(MEC5_SPI_GEN)
+  unset(MEC5_SPI_CFG)
+endif()
+
+unset(PART_PREFIX)
diff --git a/boards/microchip/mec_assy6941/Kconfig.mec_assy6941 b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941
new file mode 100644
index 00000000000..85a094ac8d1
--- /dev/null
+++ b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MEC_ASSY6941
+	select SOC_MEC1743_QLJ if BOARD_MEC_ASSY6941_MEC1743_QLJ
+	select SOC_MEC1743_QSZ if BOARD_MEC_ASSY6941_MEC1743_QSZ
+	select SOC_MEC1753_QLJ if BOARD_MEC_ASSY6941_MEC1753_QLJ
+	select SOC_MEC1753_QSZ if BOARD_MEC_ASSY6941_MEC1753_QSZ
diff --git a/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1743_qlj b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1743_qlj
new file mode 100644
index 00000000000..b58c53c2bcc
--- /dev/null
+++ b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1743_qlj
@@ -0,0 +1,5 @@
+# Copyright (c) 2025, Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MEC_ASSY6941_MEC1743_QLJ
+	select SOC_MEC1743_QLJ
diff --git a/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1743_qsz b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1743_qsz
new file mode 100644
index 00000000000..951583698bd
--- /dev/null
+++ b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1743_qsz
@@ -0,0 +1,5 @@
+# Copyright (c) 2025, Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MEC_ASSY6941_MEC1743_QSZ
+	select SOC_MEC1743_QSZ
diff --git a/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1753_qlj b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1753_qlj
new file mode 100644
index 00000000000..0ea3dbcffa4
--- /dev/null
+++ b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1753_qlj
@@ -0,0 +1,5 @@
+# Copyright (c) 2025, Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MEC_ASSY6941_MEC1753_QLJ
+	select SOC_MEC1753_QLJ
diff --git a/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1753_qsz b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1753_qsz
new file mode 100644
index 00000000000..2d631fca280
--- /dev/null
+++ b/boards/microchip/mec_assy6941/Kconfig.mec_assy6941_mec1753_qsz
@@ -0,0 +1,5 @@
+# Copyright (c) 2025, Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MEC_ASSY6941_MEC1753_QSZ
+	select SOC_MEC1753_QSZ
diff --git a/boards/microchip/mec_assy6941/board.cmake b/boards/microchip/mec_assy6941/board.cmake
new file mode 100644
index 00000000000..840168650d4
--- /dev/null
+++ b/boards/microchip/mec_assy6941/board.cmake
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
+set(SPI_IMAGE_NAME spi_image.bin)
+
+board_set_flasher_ifnset(dediprog)
+
+# --vcc=0 - use 3.5V to flash
+board_finalize_runner_args(dediprog
+  "--spi-image=${PROJECT_BINARY_DIR}/${SPI_IMAGE_NAME}"
+  "--vcc=0"
+)
+
+# This allows a custom script to be used for flashing the SPI chip.
+include(${ZEPHYR_BASE}/boards/common/misc.board.cmake)
diff --git a/boards/microchip/mec_assy6941/board.yml b/boards/microchip/mec_assy6941/board.yml
new file mode 100644
index 00000000000..2849b6b8a08
--- /dev/null
+++ b/boards/microchip/mec_assy6941/board.yml
@@ -0,0 +1,9 @@
+board:
+  name: mec_assy6941
+  full_name: MEC17xxEVB ASSY6941
+  vendor: microchip
+  socs:
+  - name: mec1743_qlj
+  - name: mec1743_qsz
+  - name: mec1753_qlj
+  - name: mec1753_qsz
diff --git a/boards/microchip/mec_assy6941/doc/index.rst b/boards/microchip/mec_assy6941/doc/index.rst
new file mode 100644
index 00000000000..da25d132cef
--- /dev/null
+++ b/boards/microchip/mec_assy6941/doc/index.rst
@@ -0,0 +1,394 @@
+.. zephyr:board:: mec_assy6941
+
+Overview
+********
+
+The MEC5 Assembly 6941 EVB kit is a development platform to evaluate the Microchip
+MEC174x and MEC175x series microcontrollers. This board requires a CPU daughter card:
+DC 176WFBGA DC ASSY 6942 for MEC1743Q-LJ or MEC1753Q-LJ (176-pin package)
+
+Hardware
+********
+
+- MEC174xQ-LJ/SZ or MEC175xQ-LJ/SZ ARM Cortex-M4 Processor
+- 480 KB total SRAM (416 KB code, 64 KB data) and 128 KB boot ROM
+- Keyboard interface
+- ADC & GPIO headers
+- Four DB9 UART connectors
+- FAN0, FAN1, FAN2 headers
+- FAN PWM interface
+- JTAG/SWD, ETM and MCHP Trace ports
+- PECI interface 3.0
+- I2C voltage translator
+- 10 SMBUS headers
+- VCI interface
+- Two Hardware Driven PS/2 Port
+- eSPI header
+- 2 Sockets for SPI NOR chips
+- One reset and VCC_PWRDGD pushbuttons
+- One external PCA9555 I/O port with jumper selectable I2C address.
+- One external LTC2489 delta-sigma ADC with jumper selectable I2C address.
+- Board power jumper selectable from +5V 2.1mm/5.5mm barrel connector or USB Micro A connector.
+- MEC175x has one I3C Host controller and one I3C secondary controller each with multiple ports.
+
+For more information about the MEC174x please see `MEC174x Data Brief`_
+For more information about the MEC175x please see `MEC175x Data Brief`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+This evaluation board kit is comprised of the following HW blocks:
+
+- MEC174x EVB ASSY 6941 Rev B
+- MEC174x 176WFBGA SOLDER DC ASSY 6942 with MEC1743Q-LJ or MEC1753Q-LJ silicon
+- SPI DONGLE ASSY 6791
+
+System Clock
+============
+
+The MEC174x/MEC175x MCU is configured to use the 96Mhz internal oscillator with the
+on-chip PLL to generate a resulting EC clock rate of 96 MHz. See Processor clock
+control register in chapter 4 "4.0 POWER, CLOCKS, and RESETS" of the data sheet in
+the references at the end of this document.
+
+Serial Port
+===========
+
+UART1 is configured for serial logs.
+
+Jumper settings
+***************
+
+Please follow the jumper settings below to properly demo this
+board. Advanced users may deviate from this recommendation.
+
+Jumper settings for EVB Assy 6941 Rev B
+=======================================
+
+Power-related jumpers
+---------------------
+
+If you wish to power from +5V power brick, then connect to barrel connector ``P1``
+(5.5mm OD, 2.1mm ID) and set the jumper ``J1 5-6``.
+
+If you wish to power from the Host USB micro-USB type A/B connector ``J62``, move the
+jumper to ``J1 9-10`` ``J59 1-2`` and ``J61 1-2``.
+
+
+.. note:: A single jumper is required in ``J1``.
+
+Required power jumpers on:
+
+	* ``JP42 1-2``, ``JP43 1-2``, ``JP45 1-2``, ``JP47 1-2``, ``JP48 1-2``
+	* ``JP50 1-2``, ``JP53 1-2``, ``JP56 1-2``, ``JP58 1-2``, ``JP60 1-2``
+	* ``JP62 1-2``, ``JP65 1-2``, ``JP66 1-2``, ``JP68 1-2``
+
+Select board +3.3V_STBY for:
+
+	* ``JP161 1-2``  VBAT_CHIP power rail
+	* ``J67 1-2``    VCHIP_VTR_REG power rail
+	* ``JP157 1-2``  VCHIP_VTR_PLL power rail
+	* ``JP158 1-2``  VCHIP_VTR_ANALOG power rail
+	* ``JP159 1-2``  VCHIP_VTR1 power rail
+
+VCHIP_VTR2 power rail can be +3.3V or +1.8V affecting the pins on VTR2.
+NOTE: QSPI shared port pins are on the VTR2 power rail.
+Select one only:
+
+	* ``J68 1-2`` VTR2 is connected to +3.3V_STBY
+	* ``J68 3-4`` VTR2 is connected to +1.8V_STBY
+
+VCHIP_VTR3 power rail in normal operation is connected to +1.8V.
+	* ``JP160 1-2`` VTR3 is connected to +1.8V_STBY
+
+Jumper selection for VCC_PWRGD
+VCC_PWRGD is connected to a 4.75K pull-up to VTR1, switch S1 to ground it,
+and reset generator U2.
+
+	* ``JP17 3x7 19-20``
+	* ``JP19 3x6 8-9``
+	* ``JP36 1-2``
+	* ``JP34 1-2``
+
+Jumper selection for nRESET_IN
+nRESET_IN is connected to a 4.75K pull-up to VTR1, switch S2 to ground it,
+and reset generator U3.
+
+	* ``JP37 1-2``
+	* ``JP35 1-2``
+
+Boot-ROM Straps
+---------------
+
+These jumpers configure MEC174x/MEC175x Boot-ROM straps.
+
+	* ``JP1 1-2`` UART_BSTRAP Normal Boot
+	* ``JP2 1-2`` CR_STRAP Normal Boot
+	* ``JP3 2-3`` JTAG_STRAP JTAG/SWD interface is not held in reset
+	* ``JP4 2-3`` CMP_STRAP GPIO207 is available as a GPIO
+	* ``JP5 1-2`` PWRGD_STRAP
+	* ``JP7 1-2`` BSS_STRAP Select eSPI CAF vs G3 if enabled in OTP
+	* ``JP8 1-2`` BSS_STRAP Default BSS_STRAP. Select load from Shared SPI
+	* ``JP6 1-2`` VTR2_STRAP
+	* ``JP9 1-2`` CRISIS_RECOVERY_STRAP
+
+Peripheral Routing Jumpers
+--------------------------
+
+UART0 to P19A DB9(top)
+
+	* ``JP89 No jumper`` RS-232 transceiver U8 not in reset.
+	* ``JP21 2-3, 8-9`` Select UART0_TX and UART0_RX from GPIOs.
+	* ``JP22 1-2, 4-5`` Select UART0_TX and UART0_RX to U8.
+
+UART1 to P19B DB9(bottom)
+
+	* ``JP90 No jumper`` RS-232 transceiver U9 not in reset.
+	* ``JP91 1-2, 4-5`` Connect UART1_TX and UART1_RX to U9.
+	* ``JP24 2-3, 5-6`` Select UART1_TX and UART1_RX from GPIOs.
+
+Shared SPI on J18 2x10 header.
+
+	* ``JP18 14-15`` Select SHD_nCS0.
+	* ``JP18 17-18`` Select SHD_CLK.
+	* ``JP18 2-3`` Select SHD_IO0.
+	* ``JP18 5-6`` Select SHD_IO1.
+	* ``JP18 8-9`` Select SHD_IO2(nWP).
+	* ``JP18 11-12`` Select SHD_IO3(nHOLD).
+
+Second chip select for accessing SPI dongle flash U7.
+	* ``JP18 20-12`` Select SHD_nCS1.
+
+JTAG/SWD ARM JTAG 2x10 J29.
+
+	* ``JP80 1-2`` No jumper. This jumper holds JTAG/SWD interface in reset.
+	* ``JP12 2-3`` Select JTAG_TDO or SWO.
+	* ``JP12 5-6`` Select JTAG_TDI Not required for ARM SWD.
+	* ``JP12 8-9`` Select JTAG_TMS or SWDIO.
+	* ``JP12 11-12`` Select JTAG_CLK or SWCLK.
+
+NOTE:
+ARM SWD is a two pin interface using JTAG_TMS as a bidirectional I/O pin and JTAG_CLK.
+The ARM Serial Wire Output Trace feature is on a third pin, JTAG_TDO.
+Configuration options are:
+
+	1. 4-pin JTAG or SWD plus SWO. Connect all four JP12 jumpers shown above.
+	2. 2-pin SWD plus SWO. Connect JP12 jumpers for JTAG_TDO, JTAG_TMS, and JTAG_CLK. JTAG_TDI is available to use as GPIO145.
+	3. 2-pin SWD only. Connect JP12 jumpers for JTAG_TMS and JTAG_CLK. JTAG_TDI and JTAG_TDO are available as GPIO145 and GPIO146 respectively
+
+Jumper settings for MEC174x/MEC175x 176WFBGA Socket DC Assy 6942 Rev A0p1
+=========================================================================
+
+The jumper configuration explained above covers the base board. The ASSY
+6942 MEC174x/MEC175x CPU board provides capability for an optional, external 32KHz
+clock source. The card includes a 32KHz crystal oscillator. The card can
+also be configured to use an external 50% duty cycle 32KHz source on the
+XTAL2/32KHZ_IN pin. Note, firmware must set the MEC174x/MEC175x clock enable
+register to select the external source matching the jumper settings. If
+using the MEC174x/MEC175x internal silicon oscillator then the 32K jumper settings
+are don't cares. ``JP1`` on DC is for scoping test clock outputs. Please
+refer to the schematic in reference section below.
+
+Parallel 32KHz crystal configuration
+------------------------------------
+``JP1 1x2 ON``
+``JP2 1x3 2-3``
+
+External 32KHz 50% duty cycle configuration
+-------------------------------------------
+``JP1 1x2 NC``
+``JP2 1x3 1-2``
+
+NOTE: EVB ``JP117 3-4`` Connects 32KHz OSC U15 output to DC.
+
+Building
+========
+
+#. Build :zephyr:code-sample:'hello_world` application as you normally do.
+
+#. The file :file:`spi_image.bin` will be created if the build system
+   can find the image generation tool. This binary image can be used
+   to flash the SPI chip.
+
+Programming and Debugging
+=========================
+
+Setup
+=====
+
+#. Example programming the SPI flash on the Assy6791 SPI dongle.
+
+#. We use a low cost USB-to-GPIO device based on the FTDI FT232H device.
+
+   The FT232H device used here is the `AdaFruit FT232H`_
+   The AdaFruit FT232H supports both 5V and 3.3V parts.
+
+   The linux flashrom tool supports FT232H USB-to-GPIO used as an SPI programmer.
+
+   .. code-block:: console
+
+      $ sudo /usr/sbin/flashrom -V -p ft2232_spi:type=232H,divisor=30 -w spi_image.bin
+
+#. Clone the `MEC174x SPI Image Gen`_ or `MEC175x SPI Image Gen`_ repository or download the
+   files within that directory.
+
+#. Make the image generation available for Zephyr, by making the tool
+   searchable by path, or by setting an environment variable
+   ``MEC5_SPI_GEN``, for example:
+
+   .. code-block:: console
+
+      export MEC5_SPI_GEN=<path to tool>/mec174x_spi_gen_linux_x86_64
+      or
+      export MEC5_SPI_GEN=<path to tool>/mec175x_spi_gen_linux_x86_64
+
+
+#. The default configuration file is mec174x_spi_cfg.txt or mec175x_spi_cfg.txt located in
+   ${BOARD_DIR}/support. If needed, a custom SPI image configuration file can be specified
+   to override the default one.
+
+   .. code-block:: console
+
+      export MEC5_SPI_CFG=custom_spi_cfg.txt
+
+Wiring
+========
+
+#. Connect the SPI Dongle ASSY 6791 to ``J18`` in the EVB.
+
+   .. image:: spi_dongle_assy6791.webp
+        :align: center
+        :alt: SPI DONGLE ASSY 6791 Connected
+
+#. IMPORTANT: Temporarily remove the jumper from JP87 to isolate SPI dongle power from EVB power rails.
+   This will prevent the SPI programmer from back driving voltage to the EVB.
+
+#. Connect programmer to the header J6 on the Assy6791 board, it will flash the SPI NOR chip
+   ``U3``.
+
+   .. note:: The AdaFruit FT232H board supports +5V or +3.3V SPI flash devices. It has
+    separate +3V and +5V pins. You should connect the appropriate voltage rail to the
+    Assy6791 flash dongle's J6-1 power pin.  It is recommended to remove the Assy6791
+    dongle from the EVB when flashing. If the dongle is attached to an unpowered EVB then
+    then the SPI programmer will back drive all the components. Back driving voltage can
+    be avoided by removing the jumper on EVB JP87 disconnecting VTR1/VTR2 from the 2x10
+    header J18.
+
+    +------------+---------------+
+    |  AdaFruit  |  Assy6791     |
+    |  Connector |  J6 Connector |
+    +============+===============+
+    |  3V or 5V  |       1       |
+    +------------+---------------+
+    |    GND     |       2       |
+    +------------+---------------+
+    |    D3      |       3       |
+    +------------+---------------+
+    |    D0      |       4       |
+    +------------+---------------+
+    |    D2      |       6       |
+    +------------+---------------+
+    |    D1      |       5       |
+    +------------+---------------+
+
+#. The AdaFruit FT232H has USB type-C connector. Connect it to your
+   development system with the appropriate USB cable. The FT232H board and
+   Assy6791 dongle will be powered.
+
+
+Flashing
+========
+
+#. Run your favorite terminal program
+
+#. Flash the SPI image created by Microchip SPI image generator during the
+   zephyr build process. The divisor option flashrom passes to the linux
+   FT232 driver divides down the 60 MHz SPI clock.  You can read the current
+   SPI image by changing the '-w' option to '-r'.
+
+   .. code-block:: console
+
+      $ sudo /usr/sbin/flashrom -V -p ft2232_spi:type=232H,divisor=30 -w spi_image.bin
+
+
+#. When flashrom completes.
+   Disconnect USB cable to remove power from the AdaFruit FT232H programmer.
+   Disconnect FT232H from Assy6791 dongle.
+   Replace the jumper on EVB JP87.
+
+# Power on the EVB.
+
+#. You should see ``"Hello World! <board name>"`` in the first terminal window.
+   If you don't see this message, press the Reset button and the message should appear.
+
+Debugging
+=========
+
+This board comes with a Cortex ETM port which facilitates tracing and debugging
+using a single physical connection.  In addition, it comes with sockets for
+JTAG only sessions.
+
+Troubleshooting
+===============
+
+#. In case you don't see your application running, please make sure ``LED1`` and ``LED2``
+   are lit. If one of these is off, then check the power-related jumpers again.
+
+#. If you suspect the SPI image was not programmed remove the SPI dongle from the EVB
+   and try flashing it again.
+
+PCA9555 Enabling
+================
+#. To enable PCA9555PW and test the I2C on mec172xevb_assy6906, additional works are needed:
+
+   As the I2C slave device NXP pca95xx on mec172xevb_assy6906 is connected to I2C00 port,
+   however, I2C00 port is shared with UART2 RS232 to TTL converter used to catch serial log,
+   so it's not possible to use UART2 and I2C00 port simultaneously. We need to change to use
+   I2C01 port by making some jumpers setting as below:
+
+    +---------+---------+------------------------------------------+
+    |  Pin 1  | Pin 2   |                Comment                   |
+    +=========+=========+==========================================+
+    | JP49.1  | JP49.2  | Connect PCA9555 VCC to +3.3V_STBY        |
+    +---------+---------+------------------------------------------+
+    | JP53.1  | JP53.2  | Select address 0100b, which means 0x26   |
+    +---------+---------+------------------------------------------+
+    | JP12.13 | JP12.14 | Connect I2C01_SDA from CPU to header J20 |
+    +---------+---------+------------------------------------------+
+    | JP12.4  | JP12.5  | Connect I2C01_SCL from CPU to header J20 |
+    +---------+---------+------------------------------------------+
+    | JP77.7  | JP77.8  | External pull-up for I2C01_SDA           |
+    +---------+---------+------------------------------------------+
+    | JP77.9  | JP77.10 | External pull-up for I2C01_SCL           |
+    +---------+---------+------------------------------------------+
+    | JP58.1  | JP20.1  | Connect NXP PCA9555 SCL to I2C01         |
+    +---------+---------+------------------------------------------+
+    | JP58.3  | JP20.3  | Connect NXP PCA9555 SDA to I2C01         |
+    +---------+---------+------------------------------------------+
+
+References
+**********
+
+.. target-notes::
+
+.. _MEC174x Data Brief:
+    https://github.com/MicrochipTech/CPGZephyrDocs/blob/main/MEC174x/MEC174x_DataBrief.pdf
+.. _MEC175x Data Brief:
+    https://github.com/MicrochipTech/CPGZephyrDocs/blob/main/MEC175x/MEC175x_DataBrief.pdf
+.. _EVB Schematic:
+    https://github.com/MicrochipTech/CPGZephyrDocs/blob/main/schematics/EVB_Assy6941.pdf
+.. _SOC Daughter Card Schematic:
+    https://github.com/MicrochipTech/CPGZephyrDocs/blob/main/schematics/MEC174x_176WFBGA_DC_6942.pdf
+.. _SPI Dongle Schematic:
+    https://github.com/MicrochipTech/CPGZephyrDocs/blob/main/schematics/SPI_Flash_and_EEPROM_Dongle_Assy6791_Rev_B1p0.pdf
+.. _MEC174x SPI Image Gen:
+    https://github.com/MicrochipTech/CPGZephyrDocs/tree/main/MEC174x/SPI_image_gen
+.. _MEC175x SPI Image Gen:
+    https://github.com/MicrochipTech/CPGZephyrDocs/tree/main/MEC175x/SPI_image_gen
+.. _AdaFruit FT232H:
+    https://www.adafruit.com/product/2264
diff --git a/boards/microchip/mec_assy6941/doc/mec_assy6941_evb.webp b/boards/microchip/mec_assy6941/doc/mec_assy6941_evb.webp
new file mode 100644
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diff --git a/boards/microchip/mec_assy6941/doc/spi_dongle_assy6791.webp b/boards/microchip/mec_assy6941/doc/spi_dongle_assy6791.webp
new file mode 100644
index 00000000000..f71375f8690
Binary files /dev/null and b/boards/microchip/mec_assy6941/doc/spi_dongle_assy6791.webp differ
diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.dts b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.dts
new file mode 100644
index 00000000000..a2b52bd505c
--- /dev/null
+++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.dts
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2025, Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <microchip/mec5_mec1743qlj.dtsi>
+#include <microchip/mec5/mec1743qlj-a0-pinctrl.dtsi>
+
+/ {
+	model = "Microchip MEC ASSY6941 MEC1743-QLJ evaluation board";
+	compatible = "microchip,mec_assy6941-mec1743_qlj";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart1;
+		rtimer-busy-wait-timer = &timer5;
+	};
+
+	power-states {
+		idle: idle {
+			compatible = "zephyr,power-state";
+			power-state-name = "suspend-to-idle";
+			min-residency-us = <1000000>;
+		};
+
+		suspend_to_ram: suspend_to_ram {
+			compatible = "zephyr,power-state";
+			power-state-name = "suspend-to-ram";
+			min-residency-us = <2000000>;
+		};
+	};
+};
+
+&cpu0 {
+	clock-frequency = <96000000>;
+	status = "okay";
+	cpu-power-states = <&idle &suspend_to_ram>;
+};
+
+/* Disable ARM SysTick kernel timer driver */
+&systick {
+	status = "disabled";
+};
+
+/* Enable MCHP kernel timer driver using 32KHz RTOS timer and 1MHz basic timer */
+&rtimer {
+	compatible = "microchip,mec5-ktimer";
+	status = "okay";
+};
+
+/* We chose 32-bit basic timer 5 for use by ktimer */
+&timer5 {
+	status = "okay";
+};
+
+&uart1 {
+	compatible = "microchip,mec5-uart";
+	status = "okay";
+	clock-frequency = <1843200>;
+	current-speed = <115200>;
+	pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>;
+	pinctrl-names = "default";
+};
diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.yaml b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.yaml
new file mode 100644
index 00000000000..cfdc0564d2f
--- /dev/null
+++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj.yaml
@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2025, Microchip Technology Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mec_assy6941/mec1743_qlj
+name: MEC174X EVB ASSY 6941 with MEC1743-QLJ
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 60
+flash: 416
+supported:
+  - gpio
+  - pinctrl
+  - i2c
+  - spi
+testing:
+  binaries:
+    - spi_image.bin
+  ignore_tags:
+    - bluetooth
+    - net
+vendor: microchip
diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj_defconfig b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj_defconfig
new file mode 100644
index 00000000000..47eaa31ebd3
--- /dev/null
+++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qlj_defconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2025, Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_GPIO=y
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.dts b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.dts
new file mode 100644
index 00000000000..fc4eb98d568
--- /dev/null
+++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.dts
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2025, Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <microchip/mec5_mec1743qlj.dtsi>
+#include <microchip/mec5/mec1743qlj-a0-pinctrl.dtsi>
+
+/ {
+	model = "Microchip MEC ASSY6941 MEC1743-QSZ evaluation board";
+	compatible = "microchip,mec_assy6941-mec1743_qsz";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart1;
+		rtimer-busy-wait-timer = &timer5;
+	};
+
+	power-states {
+		idle: idle {
+			compatible = "zephyr,power-state";
+			power-state-name = "suspend-to-idle";
+			min-residency-us = <1000000>;
+		};
+
+		suspend_to_ram: suspend_to_ram {
+			compatible = "zephyr,power-state";
+			power-state-name = "suspend-to-ram";
+			min-residency-us = <2000000>;
+		};
+	};
+};
+
+&cpu0 {
+	clock-frequency = <96000000>;
+	status = "okay";
+	cpu-power-states = <&idle &suspend_to_ram>;
+};
+
+/* Disable ARM SysTick kernel timer driver */
+&systick {
+	status = "disabled";
+};
+
+/* Enable MCHP kernel timer driver using 32KHz RTOS timer and 1MHz basic timer */
+&rtimer {
+	compatible = "microchip,mec5-ktimer";
+	status = "okay";
+};
+
+/* We chose 32-bit basic timer 5 for use by ktimer */
+&timer5 {
+	status = "okay";
+};
+
+&uart1 {
+	compatible = "microchip,mec5-uart";
+	status = "okay";
+	clock-frequency = <1843200>;
+	current-speed = <115200>;
+	pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>;
+	pinctrl-names = "default";
+};
diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.yaml b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.yaml
new file mode 100644
index 00000000000..ae39df56b04
--- /dev/null
+++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz.yaml
@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2025, Microchip Technology Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mec_assy6941/mec1743_qsz
+name: MEC174X EVB ASSY 6941 with MEC1743-QSZ
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 60
+flash: 416
+supported:
+  - gpio
+  - pinctrl
+  - i2c
+  - spi
+testing:
+  binaries:
+    - spi_image.bin
+  ignore_tags:
+    - bluetooth
+    - net
+vendor: microchip
diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz_defconfig b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz_defconfig
new file mode 100644
index 00000000000..47eaa31ebd3
--- /dev/null
+++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1743_qsz_defconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2025, Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_GPIO=y
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.dts b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.dts
new file mode 100644
index 00000000000..1187fef8a07
--- /dev/null
+++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.dts
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2025, Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <microchip/mec5_mec1753qlj.dtsi>
+#include <microchip/mec5/mec1753qlj-a0-pinctrl.dtsi>
+
+/ {
+	model = "Microchip MEC ASSY6941 MEC1753-QLJ evaluation board";
+	compatible = "microchip,mec_assy6941-mec1753_qlj";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart1;
+		rtimer-busy-wait-timer = &timer5;
+	};
+
+	power-states {
+		idle: idle {
+			compatible = "zephyr,power-state";
+			power-state-name = "suspend-to-idle";
+			min-residency-us = <1000000>;
+		};
+
+		suspend_to_ram: suspend_to_ram {
+			compatible = "zephyr,power-state";
+			power-state-name = "suspend-to-ram";
+			min-residency-us = <2000000>;
+		};
+	};
+};
+
+&cpu0 {
+	clock-frequency = <96000000>;
+	status = "okay";
+	cpu-power-states = <&idle &suspend_to_ram>;
+};
+
+/* Disable ARM SysTick kernel timer driver */
+&systick {
+	status = "disabled";
+};
+
+/* Enable MCHP kernel timer driver using 32KHz RTOS timer and 1MHz basic timer */
+&rtimer {
+	compatible = "microchip,mec5-ktimer";
+	status = "okay";
+};
+
+/* We chose 32-bit basic timer 5 for use by ktimer */
+&timer5 {
+	status = "okay";
+};
+
+&uart1 {
+	compatible = "microchip,mec5-uart";
+	status = "okay";
+	clock-frequency = <1843200>;
+	current-speed = <115200>;
+	pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>;
+	pinctrl-names = "default";
+};
diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.yaml b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.yaml
new file mode 100644
index 00000000000..ad4578718f4
--- /dev/null
+++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj.yaml
@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2025, Microchip Technology Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mec_assy6941/mec1753_qlj
+name: MEC174X EVB ASSY 6941 with MEC1753-QLJ
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 60
+flash: 416
+supported:
+  - gpio
+  - pinctrl
+  - i2c
+  - spi
+testing:
+  binaries:
+    - spi_image.bin
+  ignore_tags:
+    - bluetooth
+    - net
+vendor: microchip
diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj_defconfig b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj_defconfig
new file mode 100644
index 00000000000..47eaa31ebd3
--- /dev/null
+++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qlj_defconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2025, Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_GPIO=y
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.dts b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.dts
new file mode 100644
index 00000000000..b2e7c570cc6
--- /dev/null
+++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.dts
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2025, Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <microchip/mec5_mec1753qsz.dtsi>
+#include <microchip/mec5/mec1753qsz-a0-pinctrl.dtsi>
+
+/ {
+	model = "Microchip MEC ASSY6941 MEC1753-QSZ evaluation board";
+	compatible = "microchip,mec_assy6941-mec1753_qsz";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart1;
+		rtimer-busy-wait-timer = &timer5;
+	};
+
+	power-states {
+		idle: idle {
+			compatible = "zephyr,power-state";
+			power-state-name = "suspend-to-idle";
+			min-residency-us = <1000000>;
+		};
+
+		suspend_to_ram: suspend_to_ram {
+			compatible = "zephyr,power-state";
+			power-state-name = "suspend-to-ram";
+			min-residency-us = <2000000>;
+		};
+	};
+};
+
+&cpu0 {
+	clock-frequency = <96000000>;
+	status = "okay";
+	cpu-power-states = <&idle &suspend_to_ram>;
+};
+
+/* Disable ARM SysTick kernel timer driver */
+&systick {
+	status = "disabled";
+};
+
+/* Enable MCHP kernel timer driver using 32KHz RTOS timer and 1MHz basic timer */
+&rtimer {
+	compatible = "microchip,mec5-ktimer";
+	status = "okay";
+};
+
+/* We chose 32-bit basic timer 5 for use by ktimer */
+&timer5 {
+	status = "okay";
+};
+
+&uart1 {
+	compatible = "microchip,mec5-uart";
+	status = "okay";
+	clock-frequency = <1843200>;
+	current-speed = <115200>;
+	pinctrl-0 = <&uart1_tx_gpio170 &uart1_rx_gpio171>;
+	pinctrl-names = "default";
+};
diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.yaml b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.yaml
new file mode 100644
index 00000000000..d825e2177d8
--- /dev/null
+++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz.yaml
@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2025, Microchip Technology Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mec_assy6941/mec1753_qsz
+name: MEC174X EVB ASSY 6941 with MEC1753-QSZ
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 60
+flash: 416
+supported:
+  - gpio
+  - pinctrl
+  - i2c
+  - spi
+testing:
+  binaries:
+    - spi_image.bin
+  ignore_tags:
+    - bluetooth
+    - net
+vendor: microchip
diff --git a/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz_defconfig b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz_defconfig
new file mode 100644
index 00000000000..47eaa31ebd3
--- /dev/null
+++ b/boards/microchip/mec_assy6941/mec_assy6941_mec1753_qsz_defconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2025, Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_GPIO=y
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/microchip/mec_assy6941/support/mec174x_spi_cfg.txt b/boards/microchip/mec_assy6941/support/mec174x_spi_cfg.txt
new file mode 100644
index 00000000000..62ddf143691
--- /dev/null
+++ b/boards/microchip/mec_assy6941/support/mec174x_spi_cfg.txt
@@ -0,0 +1,51 @@
+; MEC174x SPI Image Generator configuration file
+[SPI]
+SPISizeMegabits = 128
+
+[DEVICE]
+TagAddr0 = 0
+TagAddr1 = 0
+; BoardID is used by a Boot-ROM feature named PlatformID. By default PlatformID
+; is disabled. If PlatformID is enabled in OTP Boot-ROM will check the image
+; BoardID value with an OTP PlatformID value. Load is aborted if the ID's do
+; not match.
+BoardID = 0x316
+
+[IMAGE "0"]
+ImageLocation = 0x2000
+SpiFreqMHz = 24
+SpiReadCommand = slow
+SpiDriveStrength = 4
+SpiSlewFast = false
+SpiSignalControl = 0x00
+IMG1BinFile = zephyr.bin
+ImageRevision = 0
+FwOffset = 0
+IMG1LoadAddress = 0xB0000
+IMG1EntryAddress = 0
+UseECDSA = false
+AuthenticateKeySelt = 5
+AutoKeyRevEn = true
+KeyRevPermission = 0xff
+AutoRollBackProtEn = false
+RollbackProtPerm031000 = 0
+RollbackProtPerm063032 = 0
+RollbackProtPerm095063 = 0
+RollbackProtPerm127096 = 0
+ECDSAPrivKeyFile = ECC384r.pem
+ECDSAPrivKeyPassword = MCHPECC384r
+FwEncrypt = false
+AesGenECPubKeyFile = ECC384r_crt.pem
+TagBuildNumber= 0
+Comp0ProgDrvStrenEN = false
+Comp0WritCmdTotByts = 0
+Comp0ReadCmdByte = 0
+Comp0WritCmdByte = 0
+Comp0DrvValue = 0
+Comp0DrvMask = 0
+Comp1ProgDrvStrenEN = false
+Comp1WritCmdTotByts = 0
+Comp1ReadCmdByte = 0
+Comp1WritCmdByte = 0
+Comp1DrvValue = 0
+Comp1DrvMask = 0
diff --git a/boards/microchip/mec_assy6941/support/mec175x_spi_cfg.txt b/boards/microchip/mec_assy6941/support/mec175x_spi_cfg.txt
new file mode 100644
index 00000000000..b7428492fc6
--- /dev/null
+++ b/boards/microchip/mec_assy6941/support/mec175x_spi_cfg.txt
@@ -0,0 +1,52 @@
+; MEC175x SPI Image Generator configuration file
+[SPI]
+SPISizeMegabits = 128
+
+[DEVICE]
+DeviceSel = A
+TagAddr0 = 0
+TagAddr1 = 0
+; BoardID is used by a Boot-ROM feature named PlatformID. By default PlatformID
+; is disabled. If PlatformID is enabled in OTP Boot-ROM will check the image
+; BoardID value with an OTP PlatformID value. Load is aborted if the ID's do
+; not match.
+BoardID = 0x316
+
+[IMAGE "0"]
+ImageLocation = 0x2000
+SpiFreqMHz = 24
+SpiReadCommand = slow
+SpiDriveStrength = 4
+SpiSlewFast = false
+SpiSignalControl = 0x00
+IMG1BinFile = zephyr.bin
+ImageRevision = 0
+FwOffset = 0
+IMG1LoadAddress = 0xB0000
+IMG1EntryAddress = 0
+UseECDSA = false
+AuthenticateKeySelt = 5
+AutoKeyRevEn = true
+KeyRevPermission = 0xff
+AutoRollBackProtEn = false
+RollbackProtPerm031000 = 0
+RollbackProtPerm063032 = 0
+RollbackProtPerm095063 = 0
+RollbackProtPerm127096 = 0
+ECDSAPrivKeyFile = ECC384r.pem
+ECDSAPrivKeyPassword = MCHPECC384r
+FwEncrypt = false
+AesGenECPubKeyFile = ECC384r_crt.pem
+TagBuildNumber= 0
+Comp0ProgDrvStrenEN = false
+Comp0WritCmdTotByts = 0
+Comp0ReadCmdByte = 0
+Comp0WritCmdByte = 0
+Comp0DrvValue = 0
+Comp0DrvMask = 0
+Comp1ProgDrvStrenEN = false
+Comp1WritCmdTotByts = 0
+Comp1ReadCmdByte = 0
+Comp1WritCmdByte = 0
+Comp1DrvValue = 0
+Comp1DrvMask = 0
diff --git a/boards/microchip/mpfs_icicle/Kconfig.defconfig b/boards/microchip/mpfs_icicle/Kconfig.defconfig
new file mode 100644
index 00000000000..8c630afbfc0
--- /dev/null
+++ b/boards/microchip/mpfs_icicle/Kconfig.defconfig
@@ -0,0 +1,10 @@
+# Copyright 2025 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_MPFS_ICICLE
+
+choice SPI_NOR_SFDP
+	default SPI_NOR_SFDP_RUNTIME
+endchoice
+
+endif
diff --git a/boards/microchip/mpfs_icicle/doc/index.rst b/boards/microchip/mpfs_icicle/doc/index.rst
index ee5d07b5bda..12c57e62029 100644
--- a/boards/microchip/mpfs_icicle/doc/index.rst
+++ b/boards/microchip/mpfs_icicle/doc/index.rst
@@ -10,6 +10,8 @@ More information can be found on the `Microchip website <https://www.microchip.c
 Programming and debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Building
 ========
 
diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.yaml b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.yaml
index 3518a70f8d8..c9b5fe17137 100644
--- a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.yaml
+++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_e51.yaml
@@ -9,5 +9,4 @@ testing:
   ignore_tags:
     - net
     - bluetooth
-    - flash
 vendor: microchip
diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.yaml b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.yaml
index 9599b13e1c5..6a4b1c78265 100644
--- a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.yaml
+++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54.yaml
@@ -9,5 +9,4 @@ testing:
   ignore_tags:
     - net
     - bluetooth
-    - flash
 vendor: microchip
diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_defconfig b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_defconfig
index c40256dbf73..daee5c31bb8 100644
--- a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_defconfig
+++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_defconfig
@@ -14,3 +14,4 @@ CONFIG_RV_BOOT_HART=1
 # GPIO driver options
 CONFIG_GPIO=y
 CONFIG_I2C=y
+CONFIG_MP_MAX_NUM_CPUS=1
diff --git a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.yaml b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.yaml
index 6118303c246..ab9d74860e4 100644
--- a/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.yaml
+++ b/boards/microchip/mpfs_icicle/mpfs_icicle_polarfire_u54_smp.yaml
@@ -9,5 +9,4 @@ testing:
   ignore_tags:
     - net
     - bluetooth
-    - flash
 vendor: microchip
diff --git a/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst b/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst
index a33f76d8beb..3541b8165e6 100644
--- a/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst
+++ b/boards/mikroe/clicker_2/doc/mikroe_clicker_2.rst
@@ -21,31 +21,8 @@ to the microcontroller.
 
 Supported Features
 ==================
-The Zephyr MikroE Clicker 2 configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features have not been enabled yet for this board.
-
-The default configuration can be found in
-:zephyr_file:`boards/mikroe/clicker_2/mikroe_clicker_2_defconfig`
+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -59,6 +36,9 @@ For connections on the edge connectors, please refer to `Clicker 2 for STM32 Use
 
 Programming and Debugging
 *************************
+
+.. zephyr:board-supported-runners::
+
 Applications for the ``mikroe_clicker_2`` board configuration can
 be built and flashed in the usual way (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/mikroe/clicker_2/mikroe_clicker_2.yaml b/boards/mikroe/clicker_2/mikroe_clicker_2.yaml
index b69a800360b..1f7b0fe4f82 100644
--- a/boards/mikroe/clicker_2/mikroe_clicker_2.yaml
+++ b/boards/mikroe/clicker_2/mikroe_clicker_2.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 192
 flash: 1024
 supported:
diff --git a/boards/mikroe/clicker_ra4m1/doc/index.rst b/boards/mikroe/clicker_ra4m1/doc/index.rst
index 56099ee6f42..88a005f03ff 100644
--- a/boards/mikroe/clicker_ra4m1/doc/index.rst
+++ b/boards/mikroe/clicker_ra4m1/doc/index.rst
@@ -18,30 +18,13 @@ development board see the `Clicker RA4M1 website`_.
 Supported Features
 ==================
 
-The Zephyr Mikroe Clicker RA4M1 configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling                 |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | GPIO output                         |
-|           |            | GPIO input                          |
-+-----------+------------+-------------------------------------+
-
-Other hardware features have not been enabled yet for this board.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1_defconfig`.
+.. zephyr:board-supported-hw::
 
 Programming and debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Building & Flashing
 ===================
 
diff --git a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1-pinctrl.dtsi b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1-pinctrl.dtsi
new file mode 100644
index 00000000000..d2bd43dfa19
--- /dev/null
+++ b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1-pinctrl.dtsi
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2025 Ian Morris
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci0_default: sci0_default {
+		group1 {
+			/* tx */
+			psels = <RA_PSEL(RA_PSEL_SCI_0, 4, 11)>;
+		};
+
+		group2 {
+			/* rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_0, 4, 10)>;
+		};
+	};
+
+	iic1_default: iic1_default {
+		group1 {
+			/* SCL1 SDA1 */
+			psels = <RA_PSEL(RA_PSEL_I2C, 2, 5)>,
+			<RA_PSEL(RA_PSEL_I2C, 2, 6)>;
+			drive-strength = "medium";
+		};
+	};
+
+	spi0_default: spi0_default {
+		group1 {
+			/* MISO MOSI RSPCK SSL */
+			psels = <RA_PSEL(RA_PSEL_SPI, 1, 0)>,
+			<RA_PSEL(RA_PSEL_SPI, 1, 1)>,
+			<RA_PSEL(RA_PSEL_SPI, 1, 2)>,
+			<RA_PSEL(RA_PSEL_SPI, 1, 3)>;
+		};
+	};
+};
diff --git a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts
index 5a626a78364..d5fea8287b3 100644
--- a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts
+++ b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.dts
@@ -5,14 +5,15 @@
  */
 
 /dts-v1/;
-#include <renesas/ra/r7fa4m1ab3cfm.dtsi>
+#include <renesas/ra/ra4/r7fa4m1ab3cfm.dtsi>
 #include <zephyr/dt-bindings/gpio/gpio.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
-#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
+
+#include "mikroe_clicker_ra4m1-pinctrl.dtsi"
 
 / {
 	model = "Mikroe Clicker RA4M1";
-	compatible = "renesas,r7fa4m1ab3cfm";
+	compatible = "renesas,ra4m1", "renesas,ra";
 
 	chosen {
 		zephyr,console = &uart0;
@@ -27,6 +28,7 @@
 			gpios = <&ioport4 9 GPIO_ACTIVE_HIGH>;
 			label = "User LED 1";
 		};
+
 		ld2: led_2 {
 			gpios = <&ioport4 8 GPIO_ACTIVE_HIGH>;
 			label = "User LED 2";
@@ -40,6 +42,12 @@
 			label = "User Button 1";
 			zephyr,code = <INPUT_KEY_0>;
 		};
+
+		btn2: button_2 {
+			gpios = <&ioport3 1 GPIO_ACTIVE_LOW>;
+			label = "User Button 2";
+			zephyr,code = <INPUT_KEY_1>;
+		};
 	};
 
 	mikrobus_header: mikrobus-connector {
@@ -69,19 +77,7 @@
 		led0 = &ld1;
 		led1 = &ld2;
 		sw0 = &btn1;
-	};
-};
-
-&pinctrl {
-	sci0_default: sci0_default {
-		group1 {
-			/* tx */
-			psels = <RA_PSEL(RA_PSEL_SCI_0, 4, 11)>;
-		};
-		group2 {
-			/* rx */
-			psels = <RA_PSEL(RA_PSEL_SCI_0, 4, 10)>;
-		};
+		sw1 = &btn2;
 	};
 };
 
@@ -95,6 +91,25 @@
 	};
 };
 
+&iic1 {
+	pinctrl-0 = <&iic1_default>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <DT_FREQ_K(400)>;
+	interrupts = <10 1>, <11 1>, <12 1>, <13 1>;
+	interrupt-names = "rxi", "txi", "tei", "eri";
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-0 = <&spi0_default>;
+	pinctrl-names = "default";
+	interrupts = <23 1>, <24 1>, <25 1>, <26 1>;
+	interrupt-names = "rxi", "txi", "tei", "eri";
+	status = "okay";
+};
+
 &ioport0 {
 	status = "okay";
 };
@@ -115,7 +130,13 @@
 	status = "okay";
 };
 
-&fcu {
+&port_irq6 {
+	interrupts = <28 12>;
+	status = "okay";
+};
+
+&port_irq9 {
+	interrupts = <27 12>;
 	status = "okay";
 };
 
@@ -129,6 +150,7 @@
 };
 
 &iclk {
+	clock-frequency = <12000000>;
 	div = <1>;
 };
 
@@ -151,3 +173,7 @@
 &fclk {
 	div = <2>;
 };
+
+mikrobus_serial: &uart0 {};
+mikrobus_i2c: &iic1 {};
+mikrobus_spi: &spi0 {};
diff --git a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.yaml b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.yaml
index 9cc16dc9c8d..04a7c550fed 100644
--- a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.yaml
+++ b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1.yaml
@@ -6,7 +6,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
 flash: 256
 supported:
diff --git a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1_defconfig b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1_defconfig
index 2e434ba45ea..1c187cb544c 100644
--- a/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1_defconfig
+++ b/boards/mikroe/clicker_ra4m1/mikroe_clicker_ra4m1_defconfig
@@ -1,10 +1,6 @@
 # Copyright (c) 2024 Ian Morris
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=12000000
-
-CONFIG_BUILD_OUTPUT_HEX=y
-
 # Enable uart driver
 CONFIG_SERIAL=y
 
@@ -14,6 +10,3 @@ CONFIG_UART_CONSOLE=y
 
 # Enable GPIO
 CONFIG_GPIO=y
-
-# Enable Clocks
-CONFIG_CLOCK_CONTROL=y
diff --git a/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst b/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst
index 02208b66bf3..02504c3bc9a 100644
--- a/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst
+++ b/boards/mikroe/mini_m4_for_stm32/doc/mikroe_mini_m4_for_stm32.rst
@@ -49,37 +49,7 @@ The board can be flashed by using STLinkV2 with the following connections.
 Supported Features
 ==================
 
-The MINI-M4 for STM32 board configuration supports the following hardware
-features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| CRYP      | on-chip    | crypto               |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | nested vectored      |
-|           |            | interrupt controller |
-+-----------+------------+----------------------+
-| PINMUX    | on-chip    | pinmux               |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial port          |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | PWM                  |
-+-----------+------------+----------------------+
-| USB       | on-chip    | USB                  |
-+-----------+------------+----------------------+
-
-
-Other hardware features have not been enabled yet for this board.
-
-The default configuration can be found in
-:zephyr_file:`boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32_defconfig`
+.. zephyr:board-supported-hw::
 
 Serial Port
 ===========
@@ -89,6 +59,8 @@ The Zephyr console output is assigned to USART2. Default settings are 115200 8N1
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``mikroe_mini_m4_for_stm32`` board configuration can
 be built and flashed in the usual way (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.yaml b/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.yaml
index e83b864f1ab..1ea71f99223 100644
--- a/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.yaml
+++ b/boards/mikroe/mini_m4_for_stm32/mikroe_mini_m4_for_stm32.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 1024
 supported:
diff --git a/boards/mikroe/stm32_m4_clicker/doc/index.rst b/boards/mikroe/stm32_m4_clicker/doc/index.rst
index 8bddfd3f7aa..77f52fa96bf 100644
--- a/boards/mikroe/stm32_m4_clicker/doc/index.rst
+++ b/boards/mikroe/stm32_m4_clicker/doc/index.rst
@@ -18,37 +18,13 @@ board see the `STM32 M4 Clicker website`_.
 Supported Features
 ==================
 
-The ``mikroe_stm32_m4_clicker`` board target supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | GPIO output                         |
-|           |            | GPIO input                          |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features have not yet been enabled for this board.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker_defconfig`.
+.. zephyr:board-supported-hw::
 
 Programming and debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Building & Flashing
 ===================
 
diff --git a/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker.yaml b/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker.yaml
index 96d16aa2d63..361df157777 100644
--- a/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker.yaml
+++ b/boards/mikroe/stm32_m4_clicker/mikroe_stm32_m4_clicker.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 1024
 supported:
diff --git a/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.yaml b/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.yaml
index bcb0ab9aa29..e67ec4da930 100644
--- a/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.yaml
+++ b/boards/mxchip/az3166_iotdevkit/az3166_iotdevkit.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - pwm
diff --git a/boards/mxchip/az3166_iotdevkit/doc/index.rst b/boards/mxchip/az3166_iotdevkit/doc/index.rst
index 230073f8295..8ea178b7f93 100644
--- a/boards/mxchip/az3166_iotdevkit/doc/index.rst
+++ b/boards/mxchip/az3166_iotdevkit/doc/index.rst
@@ -34,25 +34,7 @@ The MXChip AZ3166 IoT DevKit has the following physical features:
 Supported Features
 ==================
 
-The az3166_iotdevkit board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| NVIC      | on-chip    | nested vector        |
-|           |            | interrupt controller |
-+-----------+------------+----------------------+
-| SYSTICK   | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial port          |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 .. note::
 
@@ -61,6 +43,8 @@ hardware features:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/native/doc/arch_soc.rst b/boards/native/doc/arch_soc.rst
index 8906001f177..6b6a5a5e10e 100644
--- a/boards/native/doc/arch_soc.rst
+++ b/boards/native/doc/arch_soc.rst
@@ -53,8 +53,8 @@ This port is designed and tested to run in Linux.
 
 .. note::
 
-   You must have the 32-bit C library installed in your system
-   (in Ubuntu 16.04 install the gcc-multilib package)
+   To build for the 32bit targets you must have the 32-bit C library installed in your system
+   (in Debian/Ubuntu this is provided by the ``gcc-multilib`` package).
 
 .. note::
 
@@ -306,7 +306,7 @@ Architecture and design
 
 .. note::
 
-   This section does not describe anymore the old :ref:`native_posix<native_posix>` or
+   This section does not describe anymore the old
    :kconfig:option:`CONFIG_NATIVE_APPLICATION` based architecture.
    It only describes the new native simulator based architecture used by targets built with the
    :kconfig:option:`CONFIG_NATIVE_LIBRARY` option.
diff --git a/boards/native/native_posix/CMakeLists.txt b/boards/native/native_posix/CMakeLists.txt
deleted file mode 100644
index b86941cc854..00000000000
--- a/boards/native/native_posix/CMakeLists.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-# Copyright (c) 2017 Oticon A/S
-
-zephyr_library()
-
-zephyr_library_compile_definitions(NO_POSIX_CHEATS)
-zephyr_library_compile_definitions(_POSIX_C_SOURCE=200809L _XOPEN_SOURCE=600 _XOPEN_SOURCE_EXTENDED)
-
-zephyr_library_sources(
-	hw_models_top.c
-	timer_model.c
-	native_rtc.c
-	irq_handler.c
-	irq_ctrl.c
-	main.c
-	tracing.c
-	cmdline_common.c
-	cmdline.c
-	cpu_wait.c
-	hw_counter.c
-	)
-
-zephyr_library_include_directories(
-  ${ZEPHYR_BASE}/kernel/include
-  ${ZEPHYR_BASE}/arch/posix/include
-  )
-
-if(CONFIG_HAS_SDL)
-	add_subdirectory(${ZEPHYR_BASE}/boards/native/common/sdl/ ${CMAKE_CURRENT_BINARY_DIR}/sdl)
-endif()
-
-zephyr_ld_options(
-  -lm
-)
diff --git a/boards/native/native_posix/Kconfig b/boards/native/native_posix/Kconfig
deleted file mode 100644
index b629778f4cb..00000000000
--- a/boards/native/native_posix/Kconfig
+++ /dev/null
@@ -1,35 +0,0 @@
-# Copyright (c) 2017 Oticon A/S
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_NATIVE_POSIX
-	bool
-	imply NATIVE_POSIX_TIMER
-	select POSIX_ARCH_CONSOLE
-	select NATIVE_APPLICATION
-	select 64BIT if BOARD_NATIVE_POSIX_NATIVE_64
-	help
-	  Native POSIX
-	  Will produce a console Linux process which can be executed natively.
-	  It provides some minimal needed models:
-	  An interrupt controller, timer (system tick), and redirects kernel prints to
-	  stdout.
-
-if BOARD_NATIVE_POSIX
-
-comment "Native POSIX options"
-
-config NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME
-	bool "Slow down execution to real time"
-	default n if ARCH_POSIX_LIBFUZZER
-	default y if BT_USERCHAN || !TEST
-	help
-	  When selected the execution of the process will be slowed down to real time.
-	  (if there is a lot of load it may be slower than real time)
-	  If deselected, the process will run as fast as possible.
-	  Note that this only decouples simulated time from real/wall time. In either
-	  case the zephyr kernel and application cannot tell the difference unless they
-	  interact with some other driver/device which runs at real time.
-
-source "boards/native/common/sdl/Kconfig"
-
-endif # BOARD_NATIVE_POSIX
diff --git a/boards/native/native_posix/Kconfig.defconfig b/boards/native/native_posix/Kconfig.defconfig
deleted file mode 100644
index 2d896061f78..00000000000
--- a/boards/native/native_posix/Kconfig.defconfig
+++ /dev/null
@@ -1,38 +0,0 @@
-# Copyright (c) 2017 Oticon A/S
-# SPDX-License-Identifier: Apache-2.0
-
-if BOARD_NATIVE_POSIX
-
-config BOARD_DEPRECATED_RELEASE
-	default "v4.2.0"
-
-config BUILD_OUTPUT_BIN
-	default n
-
-config BUILD_OUTPUT_EXE
-	default y
-
-config OUTPUT_PRINT_MEMORY_USAGE
-	default n
-
-if NETWORKING
-
-config NET_L2_ETHERNET
-	default y if !NET_LOOPBACK && !NET_TEST
-
-config ETH_NATIVE_POSIX
-	default y if NET_L2_ETHERNET && ETH_DRIVER
-
-endif # NETWORKING
-
-if CONSOLE
-
-config POSIX_ARCH_CONSOLE
-	default y if !SERIAL
-
-config UART_CONSOLE
-	default y if SERIAL
-
-endif # CONSOLE
-
-endif # BOARD_NATIVE_POSIX
diff --git a/boards/native/native_posix/Kconfig.native_posix b/boards/native/native_posix/Kconfig.native_posix
deleted file mode 100644
index cb7c03889c4..00000000000
--- a/boards/native/native_posix/Kconfig.native_posix
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright (c) 2024 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_NATIVE_POSIX
-	select SOC_POSIX
diff --git a/boards/native/native_posix/board.cmake b/boards/native/native_posix/board.cmake
deleted file mode 100644
index c3f7c89918d..00000000000
--- a/boards/native/native_posix/board.cmake
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-# Copyright (c) 2017 Oticon A/S
-
-set(SUPPORTED_EMU_PLATFORMS native)
-
-board_set_debugger_ifnset(native)
-board_set_flasher_ifnset(native)
-board_finalize_runner_args(native)
diff --git a/boards/native/native_posix/board.yml b/boards/native/native_posix/board.yml
deleted file mode 100644
index 07defd4185b..00000000000
--- a/boards/native/native_posix/board.yml
+++ /dev/null
@@ -1,8 +0,0 @@
-boards:
-- name: native_posix
-  full_name: Native POSIX execution (native_posix)
-  vendor: zephyr
-  socs:
-  - name: native
-    variants:
-    - name: "64"
diff --git a/boards/native/native_posix/board_irq.h b/boards/native/native_posix/board_irq.h
deleted file mode 100644
index 21c29768c8e..00000000000
--- a/boards/native/native_posix/board_irq.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2017 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef BOARDS_POSIX_NATIVE_POSIX_BOARD_IRQ_H
-#define BOARDS_POSIX_NATIVE_POSIX_BOARD_IRQ_H
-
-#include "../common/irq/board_irq.h"
-
-#endif /* BOARDS_POSIX_NATIVE_POSIX_BOARD_IRQ_H */
diff --git a/boards/native/native_posix/board_soc.h b/boards/native/native_posix/board_soc.h
deleted file mode 100644
index 572617a0736..00000000000
--- a/boards/native/native_posix/board_soc.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2017 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-/**
- * @file Extra definitions provided by the board to soc.h
- *
- * Background:
- * The POSIX ARCH/SOC/board layering is different than in normal archs
- * The "SOC" does not provide almost any of the typical SOC functionality
- * but that is left for the "board" to define it
- * Device code may rely on the soc.h defining some things (like the interrupts
- * numbers)
- * Therefore this file is included from the inf_clock soc.h to allow a board
- * to define that kind of SOC related snippets
- */
-
-#ifndef _POSIX_SP_BOARD_SOC_H
-#define _POSIX_SP_BOARD_SOC_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define TIMER_TICK_IRQ 0
-#define OFFLOAD_SW_IRQ 1
-#define COUNTER_EVENT_IRQ 2
-
-/*
- * This interrupt will awake the CPU if IRQs are not locked,
- * This interrupt does not have an associated status bit or handler
- */
-#define PHONY_WEAK_IRQ 0xFFFE
-/*
- * This interrupt will awake the CPU even if IRQs are locked,
- * This interrupt does not have an associated status bit or handler
- * (the lock is only ignored when the interrupt is raised from the HW models,
- * SW threads should not try to use this)
- */
-#define PHONY_HARD_IRQ 0xFFFF
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _POSIX_SP_BOARD_SOC_H */
diff --git a/boards/native/native_posix/cmdline.c b/boards/native/native_posix/cmdline.c
deleted file mode 100644
index aa0ef1e6974..00000000000
--- a/boards/native/native_posix/cmdline.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * Copyright (c) 2018 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <stdbool.h>
-#include <stdlib.h>
-#include <string.h>
-#include "cmdline_common.h"
-#include <zephyr/types.h>
-#include "hw_models_top.h"
-#include "timer_model.h"
-#include "cmdline.h"
-#include <zephyr/toolchain.h>
-#include <zephyr/arch/posix/posix_trace.h>
-#include "native_tracing.h"
-
-static int s_argc, test_argc;
-static char **s_argv, **test_argv;
-
-static struct args_struct_t *args_struct;
-static int used_args;
-static int args_aval;
-#define ARGS_ALLOC_CHUNK_SIZE 20
-
-void native_cleanup_cmd_line(void)
-{
-	if (args_struct != NULL) { /* LCOV_EXCL_BR_LINE */
-		free(args_struct);
-		args_struct = NULL;
-	}
-}
-
-/**
- * Add a set of command line options to the program.
- *
- * Each option to be added is described in one entry of the input <args>
- * This input must be terminated with an entry containing ARG_TABLE_ENDMARKER.
- */
-void native_add_command_line_opts(struct args_struct_t *args)
-{
-	int count = 0;
-
-	while (args[count].option != NULL) {
-		count++;
-	}
-	count++; /*for the end marker*/
-
-	if (used_args + count >= args_aval) {
-		int growby = count;
-		/* reallocs are expensive let's do them only in big chunks */
-		if (growby < ARGS_ALLOC_CHUNK_SIZE) {
-			growby = ARGS_ALLOC_CHUNK_SIZE;
-		}
-
-		struct args_struct_t *new_args_struct = realloc(args_struct,
-				      (args_aval + growby)*
-				      sizeof(struct args_struct_t));
-		args_aval += growby;
-		/* LCOV_EXCL_START */
-		if (new_args_struct == NULL) {
-			posix_print_error_and_exit("Could not allocate memory");
-		} else {
-			args_struct = new_args_struct;
-		}
-		/* LCOV_EXCL_STOP */
-	}
-
-	memcpy(&args_struct[used_args], args,
-		count*sizeof(struct args_struct_t));
-
-	used_args += count - 1;
-	/*
-	 * -1 as the end marker should be overwritten next time something
-	 * is added
-	 */
-}
-
-void native_add_testargs_option(void)
-{
-	static struct args_struct_t testargs_options[] = {
-		/*
-		 * Fields:
-		 * manual, mandatory, switch,
-		 * option_name, var_name ,type,
-		 * destination, callback,
-		 * description
-		 */
-		{true, false, false,
-		"testargs", "arg", 'l',
-		(void *)NULL, NULL,
-		"Any argument that follows will be ignored by the top level, "
-		"and made available for possible tests"},
-		ARG_TABLE_ENDMARKER};
-
-	native_add_command_line_opts(testargs_options);
-}
-
-static void print_invalid_opt_error(char *argv)
-{
-	posix_print_error_and_exit("Incorrect option '%s'. Did you misspell it?"
-				   " Is that feature supported in this build?"
-				   "\n",
-				   argv);
-
-}
-
-/**
- * Handle possible command line arguments.
- *
- * We also store them for later use by possible test applications
- */
-void native_handle_cmd_line(int argc, char *argv[])
-{
-	int i;
-
-	native_add_tracing_options();
-	native_add_testargs_option();
-
-	s_argv = argv;
-	s_argc = argc;
-
-	cmd_args_set_defaults(args_struct);
-
-	for (i = 1; i < argc; i++) {
-
-		if ((cmd_is_option(argv[i], "testargs", 0))) {
-			test_argc = argc - i - 1;
-			test_argv = &argv[i+1];
-			break;
-		}
-
-		if (!cmd_parse_one_arg(argv[i], args_struct)) {
-			cmd_print_switches_help(args_struct);
-			print_invalid_opt_error(argv[i]);
-		}
-	}
-}
-
-/**
- * The application/test can use this function to inspect all the command line
- * arguments
- */
-void native_get_cmd_line_args(int *argc, char ***argv)
-{
-	*argc = s_argc;
-	*argv = s_argv;
-}
-
-/**
- * The application/test can use this function to inspect the command line
- * arguments received after --testargs
- */
-void native_get_test_cmd_line_args(int *argc, char ***argv)
-{
-	*argc = test_argc;
-	*argv = test_argv;
-}
diff --git a/boards/native/native_posix/cmdline.h b/boards/native/native_posix/cmdline.h
deleted file mode 100644
index 05d445ddd1b..00000000000
--- a/boards/native/native_posix/cmdline.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2018 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _NATIVE_POSIX_CMDLINE_H
-#define _NATIVE_POSIX_CMDLINE_H
-
-#include "cmdline_common.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void native_handle_cmd_line(int argc, char *argv[]);
-void native_get_cmd_line_args(int *argc, char ***argv);
-void native_get_test_cmd_line_args(int *argc, char ***argv);
-void native_add_command_line_opts(struct args_struct_t *args);
-void native_cleanup_cmd_line(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _NATIVE_POSIX_CMDLINE_H */
diff --git a/boards/native/native_posix/cmdline_common.c b/boards/native/native_posix/cmdline_common.c
deleted file mode 100644
index 8723505658a..00000000000
--- a/boards/native/native_posix/cmdline_common.c
+++ /dev/null
@@ -1,418 +0,0 @@
-/*
- * Copyright (c) 2018 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <string.h>
-#include <strings.h>
-#include <stdbool.h>
-#include <stdlib.h>
-#include <stdio.h>
-#include <math.h>
-#include <zephyr/arch/posix/posix_trace.h>
-#include "posix_board_if.h"
-#include <zephyr/types.h>
-#include "cmdline_common.h"
-
-/**
- * Check if <arg> is the option <option>
- * The accepted syntax is:
- *   * For options without a value following:
- *       [-[-]]<option>
- *   * For options with value:
- *       [-[-]]<option>{:|=}<value>
- *
- * Returns 0 if it is not, or a number > 0 if it is.
- * The returned number is the number of characters it went through
- * to find the end of the option including the ':' or '=' character in case of
- * options with value
- */
-int cmd_is_option(const char *arg, const char *option, int with_value)
-{
-	int of = 0;
-	size_t to_match_len = strlen(option);
-
-	if (arg[of] == '-') {
-		of++;
-	}
-	if (arg[of] == '-') {
-		of++;
-	}
-
-	if (!with_value) {
-		if (strcmp(&arg[of], option) != 0) {
-			return 0;
-		} else {
-			return of + to_match_len;
-		}
-	}
-
-	while (!(arg[of] == 0 && *option == 0)) {
-		if (*option == 0) {
-			if ((arg[of] == ':') || (arg[of] == '=')) {
-				of++;
-				break;
-			}
-			return 0;
-		}
-		if (arg[of] != *option) {
-			return 0;
-		}
-		of++;
-		option++;
-	}
-
-	if (arg[of] == 0) { /* we need a value to follow */
-		posix_print_error_and_exit("Incorrect option syntax '%s'. The "
-					   "value should follow the options. "
-					   "For example --ratio=3\n",
-					   arg);
-	}
-	return of;
-}
-
-/**
- * Return 1 if <arg> matches an accepted help option.
- * 0 otherwise
- *
- * Valid help options are [-[-]]{?|h|help}
- * with the h or help in any case combination
- */
-int cmd_is_help_option(const char *arg)
-{
-	if (arg[0] == '-') {
-		arg++;
-	}
-	if (arg[0] == '-') {
-		arg++;
-	}
-	if ((strcasecmp(arg, "?") == 0) ||
-	    (strcasecmp(arg, "h") == 0) ||
-	    (strcasecmp(arg, "help") == 0)) {
-		return 1;
-	} else {
-		return 0;
-	}
-}
-
-#define CMD_TYPE_ERROR "Coding error: type %c not understood"
-#define CMD_ERR_BOOL_SWI "Programming error: I only know how to "\
-	"automatically read boolean switches\n"
-
-/**
- * Read out a the value following an option from str, and store it into
- * <dest>
- * <type> indicates the type of parameter (and type of dest pointer)
- *   'b' : boolean
- *   's' : string (char *)
- *   'u' : 32 bit unsigned integer
- *   'U' : 64 bit unsigned integer
- *   'i' : 32 bit signed integer
- *   'I' : 64 bit signed integer
- *   'd' : *double* float
- *
- * Note: list type ('l') cannot be handled by this function and must always be
- *       manual
- *
- *  <long_d> is the long name of the option
- */
-void cmd_read_option_value(const char *str, void *dest, const char type,
-			   const char *option)
-{
-	int error = 0;
-	char *endptr = NULL;
-
-	switch (type) {
-	case 'b':
-		if (strcasecmp(str, "false") == 0) {
-			*(bool *)dest = false;
-			endptr = (char *)str + 5;
-		} else if (strcmp(str, "0") == 0) {
-			*(bool *)dest = false;
-			endptr = (char *)str + 1;
-		} else if (strcasecmp(str, "true") == 0) {
-			*(bool *)dest = true;
-			endptr = (char *)str + 4;
-		} else if (strcmp(str, "1") == 0) {
-			*(bool *)dest = true;
-			endptr = (char *)str + 1;
-		} else {
-			error = 1;
-		}
-		break;
-	case 's':
-		*(char **)dest = (char *)str;
-		endptr = (char *)str + strlen(str);
-		break;
-	case 'u':
-		*(uint32_t *)dest = strtoul(str, &endptr, 0);
-		break;
-	case 'U':
-		*(uint64_t *)dest = strtoull(str, &endptr, 0);
-		break;
-	case 'i':
-		*(int32_t *)dest = strtol(str, &endptr, 0);
-		break;
-	case 'I':
-		*(int64_t *)dest = strtoll(str, &endptr, 0);
-		break;
-	case 'd':
-		*(double *)dest = strtod(str, &endptr);
-		break;
-	default:
-		posix_print_error_and_exit(CMD_TYPE_ERROR, type);
-		/* Unreachable */
-		break;
-	}
-
-	if (!error && endptr && *endptr != 0) {
-		error = 1;
-	}
-
-	if (error) {
-		posix_print_error_and_exit("Error reading value of %s '%s'. Use"
-					   " --help for usage information\n",
-					   option, str);
-	}
-}
-
-/**
- * Initialize existing dest* to defaults based on type
- */
-void cmd_args_set_defaults(struct args_struct_t args_struct[])
-{
-	int count = 0;
-
-	while (args_struct[count].option != NULL) {
-
-		if (args_struct[count].dest == NULL) {
-			count++;
-			continue;
-		}
-
-		switch (args_struct[count].type) {
-		case 0: /* does not have storage */
-			break;
-		case 'b':
-			*(bool *)args_struct[count].dest = false;
-			break;
-		case 's':
-			*(char **)args_struct[count].dest = NULL;
-			break;
-		case 'u':
-			*(uint32_t *)args_struct[count].dest = UINT32_MAX;
-			break;
-		case 'U':
-			*(uint64_t *)args_struct[count].dest = UINT64_MAX;
-			break;
-		case 'i':
-			*(int32_t *)args_struct[count].dest = INT32_MAX;
-			break;
-		case 'I':
-			*(int64_t *)args_struct[count].dest = INT64_MAX;
-			break;
-		case 'd':
-			*(double *)args_struct[count].dest = (double)NAN;
-			break;
-		default:
-			posix_print_error_and_exit(CMD_TYPE_ERROR,
-						   args_struct[count].type);
-			break;
-		}
-		count++;
-	}
-}
-
-/**
- * For the help messages:
- * Generate a string containing how the option described by <args_s_el>
- * should be used
- *
- * The string is saved in <buf> which has been allocated <size> bytes by the
- * caller
- */
-static void cmd_gen_switch_syntax(char *buf, int size,
-				  struct args_struct_t *args_s_el)
-{
-	int ret = 0;
-
-	if (size <= 0) {
-		return;
-	}
-
-	if (args_s_el->is_mandatory == false) {
-		*buf++ = '[';
-		size--;
-	}
-
-	if (args_s_el->is_switch == true) {
-		ret = snprintf(buf, size, "-%s", args_s_el->option);
-	} else {
-		if (args_s_el->type != 'l') {
-			ret = snprintf(buf, size, "-%s=<%s>",
-					args_s_el->option, args_s_el->name);
-		} else {
-			ret = snprintf(buf, size, "-%s <%s>...",
-					args_s_el->option, args_s_el->name);
-		}
-	}
-
-	if (ret < 0) {
-		posix_print_error_and_exit("Unexpected error in %s %i\n",
-					   __FILE__, __LINE__);
-	}
-	if (size - ret < 0) {
-		/*
-		 * If we run out of space we can just stop,
-		 * this is not critical
-		 */
-		return;
-	}
-	buf += ret;
-	size -= ret;
-
-	if (args_s_el->is_mandatory == false) {
-		snprintf(buf, size, "] ");
-	} else {
-		snprintf(buf, size, " ");
-	}
-}
-
-/**
- * Print short list of available switches
- */
-void cmd_print_switches_help(struct args_struct_t args_struct[])
-{
-	int count = 0;
-	int printed_in_line = strlen(_HELP_SWITCH) + 1;
-
-	fprintf(stdout, "%s ", _HELP_SWITCH);
-
-	while (args_struct[count].option != NULL) {
-		char stringy[_MAX_STRINGY_LEN];
-
-		cmd_gen_switch_syntax(stringy, _MAX_STRINGY_LEN,
-				      &args_struct[count]);
-
-		if (printed_in_line + strlen(stringy) > _MAX_LINE_WIDTH) {
-			fprintf(stdout, "\n");
-			printed_in_line = 0;
-		}
-
-		fprintf(stdout, "%s", stringy);
-		printed_in_line += strlen(stringy);
-		count++;
-	}
-
-	fprintf(stdout, "\n");
-}
-
-/**
- * Print the long help message of the program
- */
-void cmd_print_long_help(struct args_struct_t args_struct[])
-{
-	int ret;
-	int count = 0;
-	int printed_in_line = 0;
-	char stringy[_MAX_STRINGY_LEN];
-
-	cmd_print_switches_help(args_struct);
-
-	fprintf(stdout, "\n %-*s:%s\n", _LONG_HELP_ALIGN-1,
-		_HELP_SWITCH, _HELP_DESCR);
-
-	while (args_struct[count].option != NULL) {
-		int printed_right;
-		char *toprint;
-		int total_to_print;
-
-		cmd_gen_switch_syntax(stringy, _MAX_STRINGY_LEN,
-				      &args_struct[count]);
-
-		ret = fprintf(stdout, " %-*s:", _LONG_HELP_ALIGN-1, stringy);
-		printed_in_line = ret;
-		printed_right = 0;
-		toprint = args_struct[count].descript;
-		total_to_print = strlen(toprint);
-		ret = fprintf(stdout, "%.*s\n",
-				_MAX_LINE_WIDTH - printed_in_line,
-				&toprint[printed_right]);
-		printed_right += ret - 1;
-
-		while (printed_right < total_to_print) {
-			fprintf(stdout, "%*s", _LONG_HELP_ALIGN, "");
-			ret = fprintf(stdout, "%.*s\n",
-				      _MAX_LINE_WIDTH - _LONG_HELP_ALIGN,
-				      &toprint[printed_right]);
-			printed_right += ret - 1;
-		}
-		count++;
-	}
-	fprintf(stdout, "\n");
-	fprintf(stdout, "Note that which options are available depends on the "
-		"enabled features/drivers\n\n");
-}
-
-/*
- * <argv> matched the argument described in <arg_element>
- *
- * If arg_element->dest points to a place to store a possible value, read it
- * If there is a callback registered, call it after
- */
-static void cmd_handle_this_matched_arg(char *argv, int offset,
-					struct args_struct_t *arg_element)
-{
-	if (arg_element->dest != NULL) {
-		if (arg_element->is_switch) {
-			if (arg_element->type == 'b') {
-				*(bool *)arg_element->dest = true;
-			} else {
-				posix_print_error_and_exit(CMD_ERR_BOOL_SWI);
-			}
-		} else { /* if not a switch we need to read its value */
-			cmd_read_option_value(&argv[offset],
-					      arg_element->dest,
-					      arg_element->type,
-					      arg_element->option);
-		}
-	}
-
-	if (arg_element->call_when_found) {
-		arg_element->call_when_found(argv, offset);
-	}
-}
-
-/**
- * Try to find if this argument is in the list (and it is not manual)
- * if it does, try to parse it, set its dest accordingly, and return true
- * if it is not found, return false
- */
-bool cmd_parse_one_arg(char *argv, struct args_struct_t args_struct[])
-{
-	int count = 0;
-	int ret;
-
-	if (cmd_is_help_option(argv)) {
-		cmd_print_long_help(args_struct);
-		posix_exit(0);
-	}
-
-	while (args_struct[count].option != NULL) {
-		if (args_struct[count].manual) {
-			count++;
-			continue;
-		}
-		ret = cmd_is_option(argv, args_struct[count].option,
-				    !args_struct[count].is_switch);
-		if (ret) {
-			cmd_handle_this_matched_arg(argv,
-						    ret,
-						    &args_struct[count]);
-			return true;
-		}
-		count++;
-	}
-	return false;
-}
diff --git a/boards/native/native_posix/cmdline_common.h b/boards/native/native_posix/cmdline_common.h
deleted file mode 100644
index bf33599f2a7..00000000000
--- a/boards/native/native_posix/cmdline_common.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (c) 2018 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef _CMDLINE_COMMON_H
-#define _CMDLINE_COMMON_H
-
-#include <stdbool.h>
-#include <stddef.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define _MAX_LINE_WIDTH 100 /*Total width of the help message*/
-/* Horizontal alignment of the 2nd column of the help message */
-#define _LONG_HELP_ALIGN 30
-
-#define _MAXOPT_SWITCH_LEN  32 /* Maximum allowed length for a switch name */
-#define _MAXOPT_NAME_LEN    32 /* Maximum allowed length for a variable name */
-
-#define _HELP_SWITCH  "[-h] [--h] [--help] [-?]"
-#define _HELP_DESCR   "Display this help"
-
-#define _MAX_STRINGY_LEN (_MAXOPT_SWITCH_LEN + _MAXOPT_NAME_LEN + 2 + 1 + 2 + 1)
-
-
-/**
- * Prototype for a callback function when an option is found:
- * inputs:
- *  argv: Whole argv[i] option as received in main
- *  offset: Offset to the end of the option string
- *          (including a possible ':' or '=')
- *  If the option had a value, it would be placed in &argv[offset]
- */
-typedef void (*option_found_callback_f)(char *argv, int offset);
-
-/*
- * Structure defining each command line option
- */
-struct args_struct_t {
-	/*
-	 * if manual is set cmd_args_parse*() will ignore it except for
-	 * displaying it the help messages and initializing <dest> to its
-	 * default
-	 */
-	bool manual;
-	/* For help messages, should it be wrapped in "[]" */
-	bool is_mandatory;
-	/* It is just a switch: it does not have something to store after */
-	bool is_switch;
-	/* Option name we search for: --<option> */
-	char *option;
-	/*
-	 * Name of the option destination in the help messages:
-	 * "--<option>=<name>"
-	 */
-	char *name;
-	/* Type of option (see cmd_read_option_value()) */
-	char type;
-	/* Pointer to where the read value will be stored (may be NULL) */
-	void *dest;
-	/* Optional callback to be called when the switch is found */
-	option_found_callback_f call_when_found;
-	/* Long description for the help messages */
-	char *descript;
-};
-
-#define ARG_TABLE_ENDMARKER \
-	{false, false, false, NULL, NULL, 0, NULL, NULL, NULL}
-
-int cmd_is_option(const char *arg, const char *option, int with_value);
-int cmd_is_help_option(const char *arg);
-void cmd_read_option_value(const char *str, void *dest, const char type,
-			   const char *option);
-void cmd_args_set_defaults(struct args_struct_t args_struct[]);
-bool cmd_parse_one_arg(char *argv, struct args_struct_t args_struct[]);
-void cmd_print_switches_help(struct args_struct_t args_struct[]);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _CMDLINE_COMMON_H */
diff --git a/boards/native/native_posix/cpu_wait.c b/boards/native/native_posix/cpu_wait.c
deleted file mode 100644
index c6464bcf7ea..00000000000
--- a/boards/native/native_posix/cpu_wait.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (c) 2020 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <stdbool.h>
-#include "timer_model.h"
-#include <zephyr/arch/posix/posix_soc_if.h>
-#include <posix_board_if.h>
-#include <posix_soc.h>
-
-/**
- * Replacement to the kernel k_busy_wait()
- * Will block this thread (and therefore the whole Zephyr) during usec_to_wait
- *
- * Note that interrupts may be received in the meanwhile and that therefore this
- * thread may lose context.
- * Therefore the wait time may be considerably longer.
- *
- * All this function ensures is that it will return after usec_to_wait or later.
- *
- * This special arch_busy_wait() is necessary due to how the POSIX arch/SOC INF
- * models a CPU. Conceptually it could be thought as if the MCU was running
- * at an infinitely high clock, and therefore no simulated time passes while
- * executing instructions(*1).
- * Therefore to be able to busy wait this function does the equivalent of
- * programming a dedicated timer which will raise a non-maskable interrupt,
- * and halting the CPU.
- *
- * (*1) In reality simulated time is simply not advanced just due to the "MCU"
- * running. Meaning, the SW running on the MCU is assumed to take 0 time.
- */
-void arch_busy_wait(uint32_t usec_to_wait)
-{
-	uint64_t time_end = hwm_get_time() + usec_to_wait;
-
-	while (hwm_get_time() < time_end) {
-		/*
-		 * There may be wakes due to other interrupts including
-		 * other threads calling arch_busy_wait
-		 */
-		hwtimer_wake_in_time(time_end);
-		posix_halt_cpu();
-	}
-}
-
-/**
- * Will block this thread (and therefore the whole Zephyr) during usec_to_waste
- *
- * Very similar to arch_busy_wait(), but if an interrupt or context switch
- * occurs this function will continue waiting after, ensuring that
- * usec_to_waste are spent in this context, irrespectively of how much more
- * time would be spent on interrupt handling or possible switched-in tasks.
- *
- * Can be used to emulate code execution time.
- */
-void posix_cpu_hold(uint32_t usec_to_waste)
-{
-	uint64_t time_start;
-	int64_t to_wait = usec_to_waste;
-
-	while (to_wait > 0) {
-		/*
-		 * There may be wakes due to other interrupts or nested calls to
-		 * cpu_hold in interrupt handlers
-		 */
-		time_start = hwm_get_time();
-		hwtimer_wake_in_time(time_start + to_wait);
-		posix_change_cpu_state_and_wait(true);
-		to_wait -= hwm_get_time() - time_start;
-
-		posix_irq_handler();
-	}
-}
diff --git a/boards/native/native_posix/doc/index.rst b/boards/native/native_posix/doc/index.rst
deleted file mode 100644
index ea53463a7ff..00000000000
--- a/boards/native/native_posix/doc/index.rst
+++ /dev/null
@@ -1,96 +0,0 @@
-.. _native_posix:
-
-Native POSIX execution (native_posix)
-#######################################
-
-.. contents::
-   :depth: 1
-   :backlinks: entry
-   :local:
-
-Overview
-********
-
-.. warning::
-   ``native_posix`` is deprecated in favour of :ref:`native_sim<native_sim>`, and will be removed
-   in the 4.2 release.
-
-.. note::
-   For native_posix users, if needed, :ref:`native_sim<native_sim>` includes a compatibility mode
-   :kconfig:option:`CONFIG_NATIVE_SIM_NATIVE_POSIX_COMPAT`,
-   which will set its configuration to mimic a native_posix-like configuration.
-
-``native_posix`` is the predecessor of :ref:`native_sim<native_sim>`.
-Just like with :ref:`native_sim<native_sim>` you can build your Zephyr application
-with the Zephyr kernel, creating a normal Linux executable with your host tooling,
-and can debug and instrument it like any other Linux program.
-
-But unlike with :ref:`native_sim<native_sim>` you are limited to only using the host C library.
-:ref:`native_sim<native_sim>` supports all ``native_posix`` use cases.
-
-This board does not intend to simulate any particular HW, but it provides
-a few peripherals such as an Ethernet driver, display, UART, etc., to enable
-developing and testing application code which would require them.
-This board supports the same :ref:`peripherals<native_sim_peripherals>`
-:ref:`and backends as native_sim<native_sim_backends>`.
-
-.. _native_posix_deps:
-
-Host system dependencies
-************************
-
-Please check the
-:ref:`Posix Arch Dependencies<posix_arch_deps>`
-
-.. _native_important_limitations:
-
-Important limitations
-*********************
-
-This board inherits
-:ref:`the limitations of its architecture<posix_arch_limitations>`
-
-Moreover, being limited to build only with the host C library, it is not possible to build
-applications with the :ref:`Zephyr POSIX OS abstraction<posix_support>`, as there would be symbol
-collisions between the host OS and this abstraction layer.
-
-.. _native_posix_how_to_use:
-
-How to use it
-*************
-
-To build, simply specify the ``native_posix`` board as target:
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/hello_world
-   :host-os: unix
-   :board: native_posix
-   :goals: build
-   :compact:
-
-Now you have a Linux executable, ``./build/zephyr/zephyr.exe``, you can use just like any
-other Linux program.
-
-You can run, debug, build it with sanitizers or with coverage just like with
-:ref:`native_sim<native_sim>`.
-Please check :ref:`native_sim's how to<native_sim_how_to_use>` for more info.
-
-.. _native_posix32_64:
-
-32 and 64bit versions
-*********************
-
-Just like :ref:`native_sim<native_sim>`, ``native_posix`` comes with two targets:
-A 32 bit and 64 bit version.
-The 32 bit version, ``native_posix``, is the default target, which will compile
-your code for the ILP32 ABI (i386 in a x86 or x86_64 system) where pointers
-and longs are 32 bits.
-This mimics the ABI of most embedded systems Zephyr targets,
-and is therefore normally best to test and debug your code, as some bugs are
-dependent on the size of pointers and longs.
-This target requires either a 64 bit system with multilib support installed or
-one with a 32bit userspace.
-
-The 64 bit version, ``native_posix/native/64``, compiles your code targeting the
-LP64 ABI (x86-64 in x86 systems), where pointers and longs are 64 bits.
-You can use this target if you cannot compile or run 32 bit binaries.
diff --git a/boards/native/native_posix/hw_counter.c b/boards/native/native_posix/hw_counter.c
deleted file mode 100644
index eb02fd00807..00000000000
--- a/boards/native/native_posix/hw_counter.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Copyright (c) 2020 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <stdbool.h>
-#include <stdint.h>
-#include "hw_models_top.h"
-#include "board_soc.h"
-#include "board_irq.h"
-#include "irq_ctrl.h"
-
-uint64_t hw_counter_timer;
-
-static bool counter_running;
-static uint64_t counter_value;
-static uint64_t counter_target;
-static uint64_t counter_period;
-static uint64_t counter_wrap;
-
-/**
- * Initialize the counter with prescaler of HW
- */
-void hw_counter_init(void)
-{
-	hw_counter_timer = NEVER;
-	counter_target = NEVER;
-	counter_value = 0;
-	counter_running = false;
-	counter_period = NEVER;
-	counter_wrap = NEVER;
-}
-
-void hw_counter_triggered(void)
-{
-	if (!counter_running) {
-		hw_counter_timer = NEVER;
-		return;
-	}
-
-	hw_counter_timer = hwm_get_time() + counter_period;
-	counter_value = (counter_value + 1) % counter_wrap;
-
-	if (counter_value == counter_target) {
-		hw_irq_ctrl_set_irq(COUNTER_EVENT_IRQ);
-	}
-}
-
-/**
- * Configures the counter period.
- * The counter will be incremented every 'period' microseconds.
- */
-void hw_counter_set_period(uint64_t period)
-{
-	counter_period = period;
-}
-
-/*
- * Set the count value at which the counter will wrap
- * The counter will count up to  (counter_wrap-1), i.e.:
- * 0, 1, 2,.., (counter_wrap - 1), 0
- */
-void hw_counter_set_wrap_value(uint64_t wrap_value)
-{
-	counter_wrap = wrap_value;
-}
-
-/**
- * Starts the counter. It must be previously configured with
- * hw_counter_set_period() and hw_counter_set_target().
- */
-void hw_counter_start(void)
-{
-	if (counter_running) {
-		return;
-	}
-
-	counter_running = true;
-
-	hw_counter_timer = hwm_get_time() + counter_period;
-	hwm_find_next_timer();
-}
-
-/**
- * Stops the counter at current value.
- * On the next call to hw_counter_start, the counter will
- * start from the value at which it was stopped.
- */
-void hw_counter_stop(void)
-{
-	counter_running = false;
-	hw_counter_timer = NEVER;
-	hwm_find_next_timer();
-}
-
-bool hw_counter_is_started(void)
-{
-	return counter_running;
-}
-
-/**
- * Returns the current counter value.
- */
-uint64_t hw_counter_get_value(void)
-{
-	return counter_value;
-}
-
-/**
- * Resets the counter value.
- */
-void hw_counter_reset(void)
-{
-	counter_value = 0;
-}
-
-/**
- * Configures the counter to generate an interrupt
- * when its count value reaches target.
- */
-void hw_counter_set_target(uint64_t target)
-{
-	counter_target = target;
-}
diff --git a/boards/native/native_posix/hw_counter.h b/boards/native/native_posix/hw_counter.h
deleted file mode 100644
index efbb7e39e29..00000000000
--- a/boards/native/native_posix/hw_counter.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (c) 2020 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _NATIVE_POSIX_HW_COUNTER_H
-#define _NATIVE_POSIX_HW_COUNTER_H
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void hw_counter_init(void);
-void hw_counter_triggered(void);
-
-void hw_counter_set_period(uint64_t period);
-void hw_counter_set_target(uint64_t counter_target);
-void hw_counter_set_wrap_value(uint64_t wrap_value);
-void hw_counter_start(void);
-void hw_counter_stop(void);
-bool hw_counter_is_started(void);
-uint64_t hw_counter_get_value(void);
-void hw_counter_reset(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _NATIVE_POSIX_HW_COUNTER_H */
diff --git a/boards/native/native_posix/hw_models_top.c b/boards/native/native_posix/hw_models_top.c
deleted file mode 100644
index ba2f7d6584c..00000000000
--- a/boards/native/native_posix/hw_models_top.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * Copyright (c) 2017 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * Reduced set of HW models sufficient to run some of the sample apps
- * and regression tests
- */
-
-#include <stdint.h>
-#include <signal.h>
-#include <stddef.h>
-#include <stdlib.h>
-#include <pthread.h>
-#include "hw_models_top.h"
-#include "timer_model.h"
-#include "irq_ctrl.h"
-#include "posix_board_if.h"
-#include "hw_counter.h"
-#include <zephyr/arch/posix/posix_soc_if.h>
-#include "posix_arch_internal.h"
-#include <zephyr/sys/util.h>
-
-
-static uint64_t simu_time; /* The actual time as known by the HW models */
-static uint64_t end_of_time = NEVER; /* When will this device stop */
-
-/* List of HW model timers: */
-extern uint64_t hw_timer_timer; /* When should this timer_model be called */
-extern uint64_t irq_ctrl_timer;
-extern uint64_t hw_counter_timer;
-
-static enum {
-	HWTIMER = 0,
-	IRQCNT,
-	HW_COUNTER,
-	NUMBER_OF_TIMERS,
-	NONE
-} next_timer_index = NONE;
-
-static uint64_t *Timer_list[NUMBER_OF_TIMERS] = {
-	&hw_timer_timer,
-	&irq_ctrl_timer,
-	&hw_counter_timer,
-};
-
-static uint64_t next_timer_time;
-
-/* Have we received a SIGTERM or SIGINT */
-static volatile sig_atomic_t signaled_end;
-
-/**
- * Handler for SIGTERM and SIGINT
- */
-void hwm_signal_end_handler(int sig)
-{
-	signaled_end = 1;
-}
-
-/**
- * Set the handler for SIGTERM and SIGINT which will cause the
- * program to exit gracefully when they are received the 1st time
- *
- * Note that our handler only sets a variable indicating the signal was
- * received, and in each iteration of the hw main loop this variable is
- * evaluated.
- * If for some reason (the program is stuck) we never evaluate it, the program
- * would never exit.
- * Therefore we set SA_RESETHAND: This way, the 2nd time the signal is received
- * the default handler would be called to terminate the program no matter what.
- *
- * Note that SA_RESETHAND requires either _POSIX_C_SOURCE>=200809L or
- * _XOPEN_SOURCE>=500
- */
-void hwm_set_sig_handler(void)
-{
-	struct sigaction act;
-
-	act.sa_handler = hwm_signal_end_handler;
-	PC_SAFE_CALL(sigemptyset(&act.sa_mask));
-
-	act.sa_flags = SA_RESETHAND;
-
-	PC_SAFE_CALL(sigaction(SIGTERM, &act, NULL));
-	PC_SAFE_CALL(sigaction(SIGINT, &act, NULL));
-}
-
-
-static void hwm_sleep_until_next_timer(void)
-{
-	if (next_timer_time >= simu_time) { /* LCOV_EXCL_BR_LINE */
-		simu_time = next_timer_time;
-	} else {
-		/* LCOV_EXCL_START */
-		posix_print_warning("next_timer_time corrupted (%"PRIu64"<= %"
-				PRIu64", timer idx=%i)\n",
-				(uint64_t)next_timer_time,
-				(uint64_t)simu_time,
-				next_timer_index);
-		/* LCOV_EXCL_STOP */
-	}
-
-	if (signaled_end || (simu_time > end_of_time)) {
-		posix_print_trace("\nStopped at %.3Lfs\n",
-				((long double)simu_time)/1.0e6L);
-		posix_exit(0);
-	}
-}
-
-
-/**
- * Find in between all timers which is the next one
- * and update  next_timer_* accordingly
- */
-void hwm_find_next_timer(void)
-{
-	next_timer_index = 0;
-	next_timer_time  = *Timer_list[0];
-
-	for (unsigned int i = 1; i < NUMBER_OF_TIMERS ; i++) {
-		if (next_timer_time > *Timer_list[i]) {
-			next_timer_index = i;
-			next_timer_time = *Timer_list[i];
-		}
-	}
-}
-
-/**
- * Execute the next scheduled HW event/timer
- */
-void hwm_one_event(void)
-{
-	hwm_sleep_until_next_timer();
-
-	switch (next_timer_index) { /* LCOV_EXCL_BR_LINE */
-	case HWTIMER:
-		hwtimer_timer_reached();
-		break;
-	case IRQCNT:
-		hw_irq_ctrl_timer_triggered();
-		break;
-	case HW_COUNTER:
-		hw_counter_triggered();
-		break;
-	default:
-		/* LCOV_EXCL_START */
-		posix_print_error_and_exit(
-					   "next_timer_index corrupted\n");
-		break;
-		/* LCOV_EXCL_STOP */
-	}
-
-	hwm_find_next_timer();
-}
-
-/**
- * Set the simulated time when the process will stop
- */
-void hwm_set_end_of_time(uint64_t new_end_of_time)
-{
-	end_of_time = new_end_of_time;
-}
-
-/**
- * Return the current time as known by the device
- */
-uint64_t hwm_get_time(void)
-{
-	return simu_time;
-}
-
-uint64_t posix_get_hw_cycle(void)
-{
-	return hwm_get_time();
-}
-
-/**
- * Function to initialize the HW models
- */
-void hwm_init(void)
-{
-	hwm_set_sig_handler();
-	hwtimer_init();
-	hw_counter_init();
-	hw_irq_ctrl_init();
-
-	hwm_find_next_timer();
-}
-
-/**
- * Function to free any resources allocated by the HW models
- * Note that this function needs to be designed so it is possible
- * to call it more than once during cleanup
- */
-void hwm_cleanup(void)
-{
-	hwtimer_cleanup();
-	hw_irq_ctrl_cleanup();
-}
diff --git a/boards/native/native_posix/hw_models_top.h b/boards/native/native_posix/hw_models_top.h
deleted file mode 100644
index ea50d0f949c..00000000000
--- a/boards/native/native_posix/hw_models_top.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (c) 2017 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _NATIVE_POSIX_HW_MODELS_H
-#define _NATIVE_POSIX_HW_MODELS_H
-
-#include <zephyr/types.h>
-#include <inttypes.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define NEVER UINT64_MAX
-#define NSI_NEVER UINT64_MAX
-
-void hwm_one_event(void);
-void hwm_init(void);
-void hwm_cleanup(void);
-void hwm_set_end_of_time(uint64_t new_end_of_time);
-uint64_t hwm_get_time(void);
-void hwm_find_next_timer(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _NATIVE_POSIX_HW_MODELS_H */
diff --git a/boards/native/native_posix/irq_ctrl.c b/boards/native/native_posix/irq_ctrl.c
deleted file mode 100644
index 6524e5123a4..00000000000
--- a/boards/native/native_posix/irq_ctrl.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * Copyright (c) 2017 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * HW IRQ controller model
- */
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "hw_models_top.h"
-#include "irq_ctrl.h"
-#include "irq_handler.h"
-#include <zephyr/arch/posix/arch.h> /* for find_lsb_set() */
-#include "board_soc.h"
-#include "posix_soc.h"
-#include <zephyr/types.h>
-
-uint64_t irq_ctrl_timer = NEVER;
-
-
-static uint64_t irq_status;  /* pending interrupts */
-static uint64_t irq_premask; /* interrupts before the mask */
-
-/*
- * Mask of which interrupts will actually cause the cpu to vector into its
- * irq handler
- * If an interrupt is masked in this way, it will be pending in the premask in
- * case it is enabled later before clearing it.
- * If the irq_mask enables and interrupt pending in irq_premask, it will cause
- * the controller to raise the interrupt immediately
- */
-static uint64_t irq_mask;
-
-/*
- * Interrupts lock/disable. When set, interrupts are registered
- * (in the irq_status) but do not awake the cpu. if when unlocked,
- * irq_status != 0 an interrupt will be raised immediately
- */
-static bool irqs_locked;
-static bool lock_ignore; /* For the hard fake IRQ, temporarily ignore lock */
-
-static uint8_t irq_prio[N_IRQS]; /* Priority of each interrupt */
-/* note that prio = 0 == highest, prio=255 == lowest */
-
-static int currently_running_prio = 256; /* 255 is the lowest prio interrupt */
-
-void hw_irq_ctrl_init(void)
-{
-	irq_mask = 0U; /* Let's assume all interrupts are disable at boot */
-	irq_premask = 0U;
-	irqs_locked = false;
-	lock_ignore = false;
-
-	for (int i = 0 ; i < N_IRQS; i++) {
-		irq_prio[i] = 255U;
-	}
-}
-
-void hw_irq_ctrl_cleanup(void)
-{
-	/* Nothing to be done */
-}
-
-void hw_irq_ctrl_set_cur_prio(int new)
-{
-	currently_running_prio = new;
-}
-
-int hw_irq_ctrl_get_cur_prio(void)
-{
-	return currently_running_prio;
-}
-
-void hw_irq_ctrl_prio_set(unsigned int irq, unsigned int prio)
-{
-	irq_prio[irq] = prio;
-}
-
-uint8_t hw_irq_ctrl_get_prio(unsigned int irq)
-{
-	return irq_prio[irq];
-}
-
-/**
- * Get the currently pending highest priority interrupt which has a priority
- * higher than a possibly currently running interrupt
- *
- * If none, return -1
- */
-int hw_irq_ctrl_get_highest_prio_irq(void)
-{
-	if (irqs_locked) {
-		return -1;
-	}
-
-	uint64_t hw_irq_status = hw_irq_ctrl_get_irq_status();
-	int winner = -1;
-	int winner_prio = 256;
-
-	while (hw_irq_status != 0U) {
-		int irq_nbr = find_lsb_set(hw_irq_status) - 1;
-
-		hw_irq_status &= ~((uint64_t) 1 << irq_nbr);
-		if ((winner_prio > (int)irq_prio[irq_nbr])
-		   && (currently_running_prio > (int)irq_prio[irq_nbr])) {
-			winner = irq_nbr;
-			winner_prio = irq_prio[irq_nbr];
-		}
-	}
-	return winner;
-}
-
-
-uint32_t hw_irq_ctrl_get_current_lock(void)
-{
-	return irqs_locked;
-}
-
-uint32_t hw_irq_ctrl_change_lock(uint32_t new_lock)
-{
-	uint32_t previous_lock = irqs_locked;
-
-	irqs_locked = new_lock;
-
-	if ((previous_lock == true) && (new_lock == false)) {
-		if (irq_status != 0U) {
-			posix_irq_handler_im_from_sw();
-		}
-	}
-	return previous_lock;
-}
-
-uint64_t hw_irq_ctrl_get_irq_status(void)
-{
-	return irq_status;
-}
-
-void hw_irq_ctrl_clear_all_enabled_irqs(void)
-{
-	irq_status  = 0U;
-	irq_premask &= ~irq_mask;
-}
-
-void hw_irq_ctrl_clear_all_irqs(void)
-{
-	irq_status  = 0U;
-	irq_premask = 0U;
-}
-
-void hw_irq_ctrl_disable_irq(unsigned int irq)
-{
-	irq_mask &= ~((uint64_t)1<<irq);
-}
-
-int hw_irq_ctrl_is_irq_enabled(unsigned int irq)
-{
-	return (irq_mask & ((uint64_t)1 << irq))?1:0;
-}
-
-uint64_t hw_irq_ctrl_get_irq_mask(void)
-{
-	return irq_mask;
-}
-
-void hw_irq_ctrl_clear_irq(unsigned int irq)
-{
-	irq_status  &= ~((uint64_t)1<<irq);
-	irq_premask &= ~((uint64_t)1<<irq);
-}
-
-
-/**
- * Enable an interrupt
- *
- * This function may only be called from SW threads
- *
- * If the enabled interrupt is pending, it will immediately vector to its
- * interrupt handler and continue (maybe with some swap() before)
- */
-void hw_irq_ctrl_enable_irq(unsigned int irq)
-{
-	irq_mask |= ((uint64_t)1<<irq);
-	if (irq_premask & ((uint64_t)1<<irq)) { /* if IRQ is pending */
-		hw_irq_ctrl_raise_im_from_sw(irq);
-	}
-}
-
-
-static inline void hw_irq_ctrl_irq_raise_prefix(unsigned int irq)
-{
-	if (irq < N_IRQS) {
-		irq_premask |= ((uint64_t)1<<irq);
-
-		if (irq_mask & (1 << irq)) {
-			irq_status |= ((uint64_t)1<<irq);
-		}
-	} else if (irq == PHONY_HARD_IRQ) {
-		lock_ignore = true;
-	}
-}
-
-/**
- * Set/Raise an interrupt
- *
- * This function is meant to be used by either the SW manual IRQ raising
- * or by HW which wants the IRQ to be raised in one delta cycle from now
- */
-void hw_irq_ctrl_set_irq(unsigned int irq)
-{
-	hw_irq_ctrl_irq_raise_prefix(irq);
-	if ((irqs_locked == false) || (lock_ignore)) {
-		/*
-		 * Awake CPU in 1 delta
-		 * Note that we awake the CPU even if the IRQ is disabled
-		 * => we assume the CPU is always idling in a WFE() like
-		 * instruction and the CPU is allowed to awake just with the irq
-		 * being marked as pending
-		 */
-		irq_ctrl_timer = hwm_get_time();
-		hwm_find_next_timer();
-	}
-}
-
-
-
-static void irq_raising_from_hw_now(void)
-{
-	/*
-	 * We always awake the CPU even if the IRQ was masked,
-	 * but not if irqs are locked unless this is due to a
-	 * PHONY_HARD_IRQ
-	 */
-	if ((irqs_locked == false) || (lock_ignore)) {
-		lock_ignore = false;
-		posix_interrupt_raised();
-	}
-}
-
-/**
- * Set/Raise an interrupt immediately.
- * Like hw_irq_ctrl_set_irq() but awake immediately the CPU instead of in
- * 1 delta cycle
- *
- * Call only from HW threads
- */
-void hw_irq_ctrl_raise_im(unsigned int irq)
-{
-	hw_irq_ctrl_irq_raise_prefix(irq);
-	irq_raising_from_hw_now();
-}
-
-/**
- * Like hw_irq_ctrl_raise_im() but for SW threads
- *
- * Call only from SW threads
- */
-void hw_irq_ctrl_raise_im_from_sw(unsigned int irq)
-{
-	hw_irq_ctrl_irq_raise_prefix(irq);
-
-	if (irqs_locked == false) {
-		posix_irq_handler_im_from_sw();
-	}
-}
-
-void hw_irq_ctrl_timer_triggered(void)
-{
-	irq_ctrl_timer = NEVER;
-	irq_raising_from_hw_now();
-}
diff --git a/boards/native/native_posix/irq_ctrl.h b/boards/native/native_posix/irq_ctrl.h
deleted file mode 100644
index cd5dcbea066..00000000000
--- a/boards/native/native_posix/irq_ctrl.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (c) 2017 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _NATIVE_POSIX_IRQ_CTRL_H
-#define _NATIVE_POSIX_IRQ_CTRL_H
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void hw_irq_ctrl_init(void);
-void hw_irq_ctrl_cleanup(void);
-void hw_irq_ctrl_timer_triggered(void);
-
-void hw_irq_ctrl_set_cur_prio(int new);
-int hw_irq_ctrl_get_cur_prio(void);
-
-void hw_irq_ctrl_prio_set(unsigned int irq, unsigned int prio);
-uint8_t hw_irq_ctrl_get_prio(unsigned int irq);
-
-int hw_irq_ctrl_get_highest_prio_irq(void);
-uint32_t hw_irq_ctrl_get_current_lock(void);
-uint32_t hw_irq_ctrl_change_lock(uint32_t new_lock);
-uint64_t hw_irq_ctrl_get_irq_status(void);
-void hw_irq_ctrl_disable_irq(unsigned int irq);
-int hw_irq_ctrl_is_irq_enabled(unsigned int irq);
-void hw_irq_ctrl_clear_irq(unsigned int irq);
-void hw_irq_ctrl_enable_irq(unsigned int irq);
-void hw_irq_ctrl_set_irq(unsigned int irq);
-void hw_irq_ctrl_raise_im(unsigned int irq);
-void hw_irq_ctrl_raise_im_from_sw(unsigned int irq);
-
-
-#define N_IRQS 32
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _NATIVE_POSIX_IRQ_CTRL_H */
diff --git a/boards/native/native_posix/irq_handler.c b/boards/native/native_posix/irq_handler.c
deleted file mode 100644
index 56ce6931c26..00000000000
--- a/boards/native/native_posix/irq_handler.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * Copyright (c) 2014 Wind River Systems, Inc.
- * Copyright (c) 2017 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * SW side of the IRQ handling
- */
-
-#include <stdint.h>
-#include "irq_handler.h"
-#include <zephyr/irq_offload.h>
-#include <zephyr/kernel_structs.h>
-#include "kernel_internal.h"
-#include "kswap.h"
-#include "irq_ctrl.h"
-#include "posix_core.h"
-#include "board_soc.h"
-#include <zephyr/sw_isr_table.h>
-#include "soc.h"
-#include <zephyr/tracing/tracing.h>
-
-typedef void (*normal_irq_f_ptr)(const void *);
-typedef int (*direct_irq_f_ptr)(void);
-
-typedef struct _isr_list isr_table_entry_t;
-static isr_table_entry_t irq_vector_table[N_IRQS] = { { 0 } };
-
-static int currently_running_irq = -1;
-
-static inline void vector_to_irq(int irq_nbr, int *may_swap)
-{
-	sys_trace_isr_enter();
-
-	if (irq_vector_table[irq_nbr].func == NULL) { /* LCOV_EXCL_BR_LINE */
-		/* LCOV_EXCL_START */
-		posix_print_error_and_exit("Received irq %i without a "
-					"registered handler\n",
-					irq_nbr);
-		/* LCOV_EXCL_STOP */
-	} else {
-		if (irq_vector_table[irq_nbr].flags & ISR_FLAG_DIRECT) {
-			*may_swap |= ((direct_irq_f_ptr)
-					irq_vector_table[irq_nbr].func)();
-		} else {
-#ifdef CONFIG_PM
-			posix_irq_check_idle_exit();
-#endif
-			((normal_irq_f_ptr)irq_vector_table[irq_nbr].func)
-					(irq_vector_table[irq_nbr].param);
-			*may_swap = 1;
-		}
-	}
-
-	sys_trace_isr_exit();
-}
-
-/**
- * When an interrupt is raised, this function is called to handle it and, if
- * needed, swap to a re-enabled thread
- *
- * Note that even that this function is executing in a Zephyr thread,  it is
- * effectively the model of the interrupt controller passing context to the IRQ
- * handler and therefore its priority handling
- */
-void posix_irq_handler(void)
-{
-	uint64_t irq_lock;
-	int irq_nbr;
-	static int may_swap;
-
-	irq_lock = hw_irq_ctrl_get_current_lock();
-
-	if (irq_lock) {
-		/* "spurious" wakes can happen with interrupts locked */
-		return;
-	}
-
-	if (_kernel.cpus[0].nested == 0) {
-		may_swap = 0;
-	}
-
-	_kernel.cpus[0].nested++;
-
-	while ((irq_nbr = hw_irq_ctrl_get_highest_prio_irq()) != -1) {
-		int last_current_running_prio = hw_irq_ctrl_get_cur_prio();
-		int last_running_irq = currently_running_irq;
-
-		hw_irq_ctrl_set_cur_prio(hw_irq_ctrl_get_prio(irq_nbr));
-		hw_irq_ctrl_clear_irq(irq_nbr);
-
-		currently_running_irq = irq_nbr;
-		vector_to_irq(irq_nbr, &may_swap);
-		currently_running_irq = last_running_irq;
-
-		hw_irq_ctrl_set_cur_prio(last_current_running_prio);
-	}
-
-	_kernel.cpus[0].nested--;
-
-	/* Call swap if all the following is true:
-	 * 1) may_swap was enabled
-	 * 2) We are not nesting irq_handler calls (interrupts)
-	 * 3) Next thread to run in the ready queue is not this thread
-	 */
-	if (may_swap
-		&& (hw_irq_ctrl_get_cur_prio() == 256)
-		&& (_kernel.ready_q.cache) && (_kernel.ready_q.cache != _current)) {
-
-		(void)z_swap_irqlock(irq_lock);
-	}
-}
-
-/**
- * Thru this function the IRQ controller can raise an immediate  interrupt which
- * will interrupt the SW itself
- * (this function should only be called from the HW model code, from SW threads)
- */
-void posix_irq_handler_im_from_sw(void)
-{
-	/*
-	 * if a higher priority interrupt than the possibly currently running is
-	 * pending we go immediately into irq_handler() to vector into its
-	 * handler
-	 */
-	if (hw_irq_ctrl_get_highest_prio_irq() != -1) {
-		if (!posix_is_cpu_running()) { /* LCOV_EXCL_BR_LINE */
-			/* LCOV_EXCL_START */
-			posix_print_error_and_exit("programming error: %s "
-					"called from a HW model thread\n",
-					__func__);
-			/* LCOV_EXCL_STOP */
-		}
-		posix_irq_handler();
-	}
-}
-
-/**
- * @brief Disable all interrupts on the CPU
- *
- * This routine disables interrupts.  It can be called from either interrupt,
- * task or fiber level.  This routine returns an architecture-dependent
- * lock-out key representing the "interrupt disable state" prior to the call;
- * this key can be passed to irq_unlock() to re-enable interrupts.
- *
- * The lock-out key should only be used as the argument to the irq_unlock()
- * API. It should never be used to manually re-enable interrupts or to inspect
- * or manipulate the contents of the source register.
- *
- * This function can be called recursively: it will return a key to return the
- * state of interrupt locking to the previous level.
- *
- * WARNINGS
- * Invoking a kernel routine with interrupts locked may result in
- * interrupts being re-enabled for an unspecified period of time.  If the
- * called routine blocks, interrupts will be re-enabled while another
- * thread executes, or while the system is idle.
- *
- * The "interrupt disable state" is an attribute of a thread.  Thus, if a
- * fiber or task disables interrupts and subsequently invokes a kernel
- * routine that causes the calling thread to block, the interrupt
- * disable state will be restored when the thread is later rescheduled
- * for execution.
- *
- * @return An architecture-dependent lock-out key representing the
- * "interrupt disable state" prior to the call.
- *
- */
-unsigned int posix_irq_lock(void)
-{
-	return hw_irq_ctrl_change_lock(true);
-}
-
-/**
- * @brief Enable all interrupts on the CPU
- *
- * This routine re-enables interrupts on the CPU.  The @a key parameter is a
- * board-dependent lock-out key that is returned by a previous invocation of
- * board_irq_lock().
- *
- * This routine can be called from either interrupt, task or fiber level.
- */
-void posix_irq_unlock(unsigned int key)
-{
-	hw_irq_ctrl_change_lock(key);
-}
-
-void posix_irq_full_unlock(void)
-{
-	hw_irq_ctrl_change_lock(false);
-}
-
-void posix_irq_enable(unsigned int irq)
-{
-	hw_irq_ctrl_enable_irq(irq);
-}
-
-void posix_irq_disable(unsigned int irq)
-{
-	hw_irq_ctrl_disable_irq(irq);
-}
-
-int posix_irq_is_enabled(unsigned int irq)
-{
-	return hw_irq_ctrl_is_irq_enabled(irq);
-}
-
-int posix_get_current_irq(void)
-{
-	return currently_running_irq;
-}
-
-/**
- * Configure a static interrupt.
- *
- * posix_isr_declare will populate the interrupt table table with the
- * interrupt's parameters, the vector table and the software ISR table.
- *
- * We additionally set the priority in the interrupt controller at
- * runtime.
- *
- * @param irq_p IRQ line number
- * @param flags [plug it directly (1), or as a SW managed interrupt (0)]
- * @param isr_p Interrupt service routine
- * @param isr_param_p ISR parameter
- * @param flags_p IRQ options
- */
-void posix_isr_declare(unsigned int irq_p, int flags, void isr_p(const void *),
-		       const void *isr_param_p)
-{
-	if (irq_p >= N_IRQS) {
-		posix_print_error_and_exit("Attempted to configure not existent interrupt %u\n",
-					   irq_p);
-		return;
-	}
-	irq_vector_table[irq_p].irq   = irq_p;
-	irq_vector_table[irq_p].func  = isr_p;
-	irq_vector_table[irq_p].param = isr_param_p;
-	irq_vector_table[irq_p].flags = flags;
-}
-
-/**
- * @internal
- *
- * @brief Set an interrupt's priority
- *
- * Lower values take priority over higher values.
- */
-void posix_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
-{
-	hw_irq_ctrl_prio_set(irq, prio);
-}
-
-/**
- * Similar to ARM's NVIC_SetPendingIRQ
- * set a pending IRQ from SW
- *
- * Note that this will interrupt immediately if the interrupt is not masked and
- * IRQs are not locked, and this interrupt has higher priority than a possibly
- * currently running interrupt
- */
-void posix_sw_set_pending_IRQ(unsigned int IRQn)
-{
-	hw_irq_ctrl_raise_im_from_sw(IRQn);
-}
-
-/**
- * Similar to ARM's NVIC_ClearPendingIRQ
- * clear a pending irq from SW
- */
-void posix_sw_clear_pending_IRQ(unsigned int IRQn)
-{
-	hw_irq_ctrl_clear_irq(IRQn);
-}
-
-#ifdef CONFIG_IRQ_OFFLOAD
-/**
- * Storage for functions offloaded to IRQ
- */
-static void (*off_routine)(const void *);
-static const void *off_parameter;
-
-/**
- * IRQ handler for the SW interrupt assigned to irq_offload()
- */
-static void offload_sw_irq_handler(const void *a)
-{
-	ARG_UNUSED(a);
-	off_routine(off_parameter);
-}
-
-/**
- * @brief Run a function in interrupt context
- *
- * Raise the SW IRQ assigned to handled this
- */
-void posix_irq_offload(void (*routine)(const void *), const void *parameter)
-{
-	off_routine = routine;
-	off_parameter = parameter;
-	posix_isr_declare(OFFLOAD_SW_IRQ, 0, offload_sw_irq_handler, NULL);
-	posix_irq_enable(OFFLOAD_SW_IRQ);
-	posix_sw_set_pending_IRQ(OFFLOAD_SW_IRQ);
-	posix_irq_disable(OFFLOAD_SW_IRQ);
-}
-#endif /* CONFIG_IRQ_OFFLOAD */
diff --git a/boards/native/native_posix/irq_handler.h b/boards/native/native_posix/irq_handler.h
deleted file mode 100644
index 3425182369d..00000000000
--- a/boards/native/native_posix/irq_handler.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Copyright (c) 2017 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _NATIVE_POSIX_IRQ_HANDLER_H
-#define _NATIVE_POSIX_IRQ_HANDLER_H
-
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-void posix_irq_handler_im_from_sw(void);
-void posix_sw_set_pending_IRQ(unsigned int IRQn);
-void posix_sw_clear_pending_IRQ(unsigned int IRQn);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _NATIVE_POSIX_IRQ_HANDLER_H */
diff --git a/boards/native/native_posix/main.c b/boards/native/native_posix/main.c
deleted file mode 100644
index f68f4dbf0e3..00000000000
--- a/boards/native/native_posix/main.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * Copyright (c) 2017 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/*
- * The basic principle of operation is:
- *   No asynchronous behavior, no indeterminism.
- *   If you run the same thing 20 times, you get exactly the same result 20
- *   times.
- *   It does not matter if you are running from console, or in a debugger
- *   and you go for lunch in the middle of the debug session.
- *
- * This is achieved as follows:
- *  The execution of native_posix is decoupled from the underlying host and its
- *  peripherals (unless set otherwise).
- *  In general, time in native_posix is simulated.
- *
- * But, native_posix can also be linked if desired to the underlying host,
- * e.g.:You can use the provided Ethernet TAP driver, or a host BLE controller.
- *
- * In this case, the no-indeterminism principle is lost. Runs of native_posix
- * will depend on the host load and the interactions with those real host
- * peripherals.
- *
- */
-
-#include <stdio.h>
-#include <soc.h>
-#include "hw_models_top.h"
-#include <stdlib.h>
-#include <zephyr/sys/util.h>
-#include <zephyr/sys/time_units.h>
-#include "cmdline.h"
-#include "irq_ctrl.h"
-
-void posix_exit(int exit_code)
-{
-	static int max_exit_code;
-
-	max_exit_code = MAX(exit_code, max_exit_code);
-	/*
-	 * posix_soc_clean_up may not return if this is called from a SW thread,
-	 * but instead it would get posix_exit() recalled again
-	 * ASAP from the HW thread
-	 */
-	posix_soc_clean_up();
-	hwm_cleanup();
-	native_cleanup_cmd_line();
-	exit(max_exit_code);
-}
-
-/**
- * Run all early native_posix initialization steps, including command
- * line parsing and CPU start, until we are ready to let the HW models
- * run via hwm_one_event()
- */
-void posix_init(int argc, char *argv[])
-{
-	/*
-	 * Let's ensure that even if we are redirecting to a file, we get stdout
-	 * and stderr line buffered (default for console)
-	 * Note that glibc ignores size. But just in case we set a reasonable
-	 * number in case somebody tries to compile against a different library
-	 */
-	setvbuf(stdout, NULL, _IOLBF, 512);
-	setvbuf(stderr, NULL, _IOLBF, 512);
-
-	run_native_tasks(_NATIVE_PRE_BOOT_1_LEVEL);
-
-	native_handle_cmd_line(argc, argv);
-
-	run_native_tasks(_NATIVE_PRE_BOOT_2_LEVEL);
-
-	hwm_init();
-
-	run_native_tasks(_NATIVE_PRE_BOOT_3_LEVEL);
-
-	posix_boot_cpu();
-
-	run_native_tasks(_NATIVE_FIRST_SLEEP_LEVEL);
-}
-
-/**
- * Execute the simulator for at least the specified timeout, then
- * return.  Note that this does not affect event timing, so the "next
- * event" may be significantly after the request if the hardware has
- * not been configured to e.g. send an interrupt when expected.
- */
-void posix_exec_for(uint64_t us)
-{
-	uint64_t start = hwm_get_time();
-
-	do {
-		hwm_one_event();
-	} while (hwm_get_time() < (start + us));
-}
-
-#ifndef CONFIG_ARCH_POSIX_LIBFUZZER
-
-/**
- * This is the actual host process main routine.  The Zephyr
- * application's main() is renamed via preprocessor trickery to avoid
- * collisions.
- *
- * Not used when building fuzz cases, as libfuzzer has its own main()
- * and calls the "OS" through a per-case fuzz test entry point.
- */
-int main(int argc, char *argv[])
-{
-	posix_init(argc, argv);
-	while (true) {
-		hwm_one_event();
-	}
-
-	/* This line should be unreachable */
-	return 1; /* LCOV_EXCL_LINE */
-}
-
-#endif
diff --git a/boards/native/native_posix/native_posix.dts b/boards/native/native_posix/native_posix.dts
deleted file mode 100644
index 74a3c30049b..00000000000
--- a/boards/native/native_posix/native_posix.dts
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Copyright (c) 2023 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "../native_sim/native_sim.dts"
diff --git a/boards/native/native_posix/native_posix.yaml b/boards/native/native_posix/native_posix.yaml
deleted file mode 100644
index 28601c1647e..00000000000
--- a/boards/native/native_posix/native_posix.yaml
+++ /dev/null
@@ -1,25 +0,0 @@
-identifier: native_posix
-name: Native 32-bit POSIX port
-type: native
-simulation:
-  - name: native
-arch: posix
-ram: 65536
-flash: 65536
-toolchain:
-  - host
-  - llvm
-supported:
-  - can
-  - counter
-  - display
-  - dma
-  - eeprom
-  - netif:eth
-  - usb_device
-  - adc
-  - i2c
-  - spi
-  - gpio
-  - rtc
-vendor: zephyr
diff --git a/boards/native/native_posix/native_posix_64.dts b/boards/native/native_posix/native_posix_64.dts
deleted file mode 100644
index 74a3c30049b..00000000000
--- a/boards/native/native_posix/native_posix_64.dts
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Copyright (c) 2023 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "../native_sim/native_sim.dts"
diff --git a/boards/native/native_posix/native_posix_64_defconfig b/boards/native/native_posix/native_posix_64_defconfig
deleted file mode 100644
index b0033eda61f..00000000000
--- a/boards/native/native_posix/native_posix_64_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_CONSOLE=y
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000
diff --git a/boards/native/native_posix/native_posix_defconfig b/boards/native/native_posix/native_posix_defconfig
deleted file mode 100644
index b0033eda61f..00000000000
--- a/boards/native/native_posix/native_posix_defconfig
+++ /dev/null
@@ -1,4 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_CONSOLE=y
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000
diff --git a/boards/native/native_posix/native_posix_native_64.yaml b/boards/native/native_posix/native_posix_native_64.yaml
deleted file mode 100644
index 5510fc9ac50..00000000000
--- a/boards/native/native_posix/native_posix_native_64.yaml
+++ /dev/null
@@ -1,23 +0,0 @@
-identifier: native_posix/native/64
-name: Native 64-bit POSIX port
-type: native
-simulation:
-  - name: native
-arch: posix
-ram: 65536
-flash: 65536
-toolchain:
-  - host
-  - llvm
-supported:
-  - can
-  - counter
-  - display
-  - dma
-  - eeprom
-  - netif:eth
-  - usb_device
-  - adc
-  - gpio
-  - rtc
-vendor: zephyr
diff --git a/boards/native/native_posix/native_rtc.c b/boards/native/native_posix/native_rtc.c
deleted file mode 100644
index efdd7752e1c..00000000000
--- a/boards/native/native_posix/native_rtc.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright (c) 2018 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * API to the native_posix (Real) Time Clock
- */
-
-#include "native_rtc.h"
-#include "hw_models_top.h"
-#include "timer_model.h"
-#include <zephyr/arch/posix/posix_trace.h>
-
-/**
- * Return the (simulation) time in microseconds
- * where clock_type is one of RTC_CLOCK_*
- */
-uint64_t native_rtc_gettime_us(int clock_type)
-{
-	if (clock_type == RTC_CLOCK_BOOT) {
-		return hwm_get_time();
-	} else if (clock_type == RTC_CLOCK_REALTIME) { /* RTC_CLOCK_REALTIME */
-		return hwtimer_get_simu_rtc_time();
-	} else if (clock_type == RTC_CLOCK_PSEUDOHOSTREALTIME) {
-		uint32_t nsec;
-		uint64_t sec;
-
-		hwtimer_get_pseudohost_rtc_time(&nsec, &sec);
-		return sec * 1000000UL + nsec / 1000U;
-	}
-
-	posix_print_error_and_exit("Unknown clock source %i\n",
-				   clock_type);
-	return 0;
-}
-
-/**
- * Similar to POSIX clock_gettime()
- * get the simulation time split in nsec and seconds
- * where clock_type is one of RTC_CLOCK_*
- */
-void native_rtc_gettime(int clock_type, uint32_t *nsec, uint64_t *sec)
-{
-	if (clock_type == RTC_CLOCK_BOOT || clock_type == RTC_CLOCK_REALTIME) {
-		uint64_t us = native_rtc_gettime_us(clock_type);
-		*nsec = (us % 1000000UL) * 1000U;
-		*sec  = us / 1000000UL;
-	} else { /* RTC_CLOCK_PSEUDOHOSTREALTIME */
-		hwtimer_get_pseudohost_rtc_time(nsec, sec);
-	}
-}
-
-/**
- * Offset the real time clock by a number of microseconds.
- * Note that this only affects the RTC_CLOCK_REALTIME and
- * RTC_CLOCK_PSEUDOHOSTREALTIME clocks.
- */
-void native_rtc_offset(int64_t delta_us)
-{
-	hwtimer_adjust_rtc_offset(delta_us);
-}
-
-/**
- * Adjust the speed of the clock source by a multiplicative factor
- */
-void native_rtc_adjust_clock(double clock_correction)
-{
-	hwtimer_adjust_rt_ratio(clock_correction);
-}
diff --git a/boards/native/native_posix/native_rtc.h b/boards/native/native_posix/native_rtc.h
deleted file mode 100644
index c17395448af..00000000000
--- a/boards/native/native_posix/native_rtc.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (c) 2018 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief API to the native_posix (Real) Time Clock
- */
-
-
-#ifndef _NATIVE_POSIX_RTC_H
-#define _NATIVE_POSIX_RTC_H
-
-#include "hw_models_top.h"
-#include <stdbool.h>
-#include <zephyr/types.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * Types of clocks this RTC provides:
- */
-/** Time since boot, cannot be offset. Microsecond resolution */
-#define RTC_CLOCK_BOOT               0
-/** Persistent clock, can be offset. Microsecond resolution */
-#define RTC_CLOCK_REALTIME           1
-/**
- * Pseudo-host real time clock (Please see documentation).
- * Nanosecond resolution
- */
-#define RTC_CLOCK_PSEUDOHOSTREALTIME 2
-
-/**
- * @brief Get the value of a clock in microseconds
- *
- * @param clock_type Which clock to measure from
- *
- * @return Number of microseconds
- */
-uint64_t native_rtc_gettime_us(int clock_type);
-
-/**
- * @brief Get the value of a clock split in nsec and seconds
- *
- * @param clock_type Which clock to measure from
- * @param nsec Pointer to store the nanoseconds
- * @param nsec Pointer to store the seconds
- */
-void native_rtc_gettime(int clock_type, uint32_t *nsec, uint64_t *sec);
-
-/**
- * @brief Offset the real time clock by a number of microseconds.
- * Note that this only affects the RTC_CLOCK_REALTIME and
- * RTC_CLOCK_PSEUDOHOSTREALTIME clocks.
- *
- * @param delta_us Number of microseconds to offset. The value is added to all
- * offsetable clocks.
- */
-void native_rtc_offset(int64_t delta_us);
-
-/**
- * @brief Adjust the speed of the clock source by a multiplicative factor
- *
- * @param clock_correction Factor by which to correct the clock speed
- */
-void native_rtc_adjust_clock(double clock_correction);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _NATIVE_POSIX_RTC_H */
diff --git a/boards/native/native_posix/native_tracing.h b/boards/native/native_posix/native_tracing.h
deleted file mode 100644
index 6c84c78a4aa..00000000000
--- a/boards/native/native_posix/native_tracing.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (c) 2018 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef NATIVE_TRACING_H
-#define NATIVE_TRACING_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void native_add_tracing_options(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* NATIVE_TRACING_H */
diff --git a/boards/native/native_posix/timer_model.c b/boards/native/native_posix/timer_model.c
deleted file mode 100644
index 4927d1028c4..00000000000
--- a/boards/native/native_posix/timer_model.c
+++ /dev/null
@@ -1,546 +0,0 @@
-/*
- * Copyright (c) 2017 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * This provides a model of:
- *  - A system tick
- *  - A real time clock
- *  - A one shot HW timer which can be used to awake the CPU at a given time
- *  - The clock source for all of this, and therefore for native_posix
- *
- * Please see doc/board.rst for more information, specially sections:
- *  About time in native_posix
- *  Peripherals:
- *	Clock source, system tick and timer
- *	Real time clock
- */
-
-#include <stdint.h>
-#include <time.h>
-#include <stdbool.h>
-#include <math.h>
-#include "hw_models_top.h"
-#include "irq_ctrl.h"
-#include "board_soc.h"
-#include <zephyr/types.h>
-#include <zephyr/arch/posix/posix_trace.h>
-#include <zephyr/sys/util.h>
-#include "cmdline.h"
-#include "posix_native_task.h"
-
-#define DEBUG_NP_TIMER 0
-
-#if DEBUG_NP_TIMER
-
-/**
- * Helper function to convert a 64 bit time in microseconds into a string.
- * The format will always be: hh:mm:ss.ssssss\0
- *
- * Note: the caller has to allocate the destination buffer (at least 17 chars)
- */
-#include <stdio.h>
-static char *us_time_to_str(char *dest, uint64_t time)
-{
-	if (time != NEVER) {
-		unsigned int hour;
-		unsigned int minute;
-		unsigned int second;
-		unsigned int us;
-
-		hour   = (time / 3600U / 1000000U) % 24;
-		minute = (time / 60U / 1000000U) % 60;
-		second = (time / 1000000U) % 60;
-		us     = time % 1000000;
-
-		sprintf(dest, "%02u:%02u:%02u.%06u", hour, minute, second, us);
-	} else {
-		sprintf(dest, " NEVER/UNKNOWN ");
-
-	}
-	return dest;
-}
-#endif
-
-uint64_t hw_timer_timer;
-
-uint64_t hw_timer_tick_timer;
-uint64_t hw_timer_awake_timer;
-
-static uint64_t tick_p; /* Period of the ticker */
-static int64_t silent_ticks;
-
-static bool real_time_mode =
-#if defined(CONFIG_NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME)
-	true;
-#else
-	false;
-#endif
-
-static bool reset_rtc; /*"Reset" the RTC on boot*/
-
-/*
- * When this executable started running, this value shall not be changed after
- * boot
- */
-static uint64_t boot_time;
-
-/*
- * Ratio of the simulated clock to the real host time
- * For ex. a clock_ratio = 1+100e-6 means the simulated time is 100ppm faster
- * than real time
- */
-static double clock_ratio = 1.0;
-
-#if DEBUG_NP_TIMER
-/*
- * Offset of the simulated time vs the real host time due to drift/clock ratio
- * until "last_radj_*time"
- *
- * A positive value means simulated time is ahead of the host time
- *
- * This variable is only kept for debugging purposes
- */
-static int64_t last_drift_offset;
-#endif
-
-/*
- * Offsets of the RTC relative to the hardware models simu_time
- * "simu_time" == simulated time which starts at 0 on boot
- */
-static int64_t rtc_offset;
-
-/* Last host/real time when the ratio was adjusted */
-static uint64_t last_radj_rtime;
-/* Last simulated time when the ratio was adjusted */
-static uint64_t last_radj_stime;
-
-extern uint64_t posix_get_hw_cycle(void);
-
-void hwtimer_set_real_time_mode(bool new_rt)
-{
-	real_time_mode = new_rt;
-}
-
-static void hwtimer_update_timer(void)
-{
-	hw_timer_timer = MIN(hw_timer_tick_timer, hw_timer_awake_timer);
-}
-
-static inline void host_clock_gettime(struct timespec *tv)
-{
-#if defined(CLOCK_MONOTONIC_RAW)
-	clock_gettime(CLOCK_MONOTONIC_RAW, tv);
-#else
-	clock_gettime(CLOCK_MONOTONIC, tv);
-#endif
-}
-
-uint64_t get_host_us_time(void)
-{
-	struct timespec tv;
-
-	host_clock_gettime(&tv);
-	return (uint64_t)tv.tv_sec * 1e6 + tv.tv_nsec / 1000;
-}
-
-void hwtimer_init(void)
-{
-	silent_ticks = 0;
-	hw_timer_tick_timer = NEVER;
-	hw_timer_awake_timer = NEVER;
-	hwtimer_update_timer();
-	if (real_time_mode) {
-		boot_time = get_host_us_time();
-		last_radj_rtime = boot_time;
-		last_radj_stime = 0U;
-	}
-	if (!reset_rtc) {
-		struct timespec tv;
-		uint64_t realhosttime;
-
-		clock_gettime(CLOCK_REALTIME, &tv);
-		realhosttime = (uint64_t)tv.tv_sec * 1e6 + tv.tv_nsec / 1000;
-
-		rtc_offset += realhosttime;
-	}
-}
-
-void hwtimer_cleanup(void)
-{
-
-}
-
-/**
- * Enable the HW timer tick interrupts with a period <period> in microseconds
- */
-void hwtimer_enable(uint64_t period)
-{
-	tick_p = period;
-	hw_timer_tick_timer = hwm_get_time() + tick_p;
-	hwtimer_update_timer();
-	hwm_find_next_timer();
-}
-
-static void hwtimer_tick_timer_reached(void)
-{
-	if (real_time_mode) {
-		uint64_t expected_rt = (hw_timer_tick_timer - last_radj_stime)
-				    / clock_ratio
-				    + last_radj_rtime;
-		uint64_t real_time = get_host_us_time();
-
-		int64_t diff = expected_rt - real_time;
-
-#if DEBUG_NP_TIMER
-		char es[30];
-		char rs[30];
-
-		us_time_to_str(es, expected_rt - boot_time);
-		us_time_to_str(rs, real_time - boot_time);
-		printf("tick @%5llims: diff = expected_rt - real_time = "
-			"%5lli = %s - %s\n",
-			hw_timer_tick_timer/1000U, diff, es, rs);
-#endif
-
-		if (diff > 0) { /* we need to slow down */
-			struct timespec requested_time;
-			struct timespec remaining;
-
-			requested_time.tv_sec  = diff / 1e6;
-			requested_time.tv_nsec = (diff -
-						 requested_time.tv_sec*1e6)*1e3;
-
-			(void) nanosleep(&requested_time, &remaining);
-		}
-	}
-
-	hw_timer_tick_timer += tick_p;
-	hwtimer_update_timer();
-
-	if (silent_ticks > 0) {
-		silent_ticks -= 1;
-	} else {
-		hw_irq_ctrl_set_irq(TIMER_TICK_IRQ);
-	}
-}
-
-static void hwtimer_awake_timer_reached(void)
-{
-	hw_timer_awake_timer = NEVER;
-	hwtimer_update_timer();
-	hw_irq_ctrl_set_irq(PHONY_HARD_IRQ);
-}
-
-void hwtimer_timer_reached(void)
-{
-	uint64_t Now = hw_timer_timer;
-
-	if (hw_timer_awake_timer == Now) {
-		hwtimer_awake_timer_reached();
-	}
-
-	if (hw_timer_tick_timer == Now) {
-		hwtimer_tick_timer_reached();
-	}
-}
-
-/**
- * The timer HW will awake the CPU (without an interrupt) at least when <time>
- * comes (it may awake it earlier)
- *
- * If there was a previous request for an earlier time, the old one will prevail
- *
- * This is meant for k_busy_wait() like functionality
- */
-void hwtimer_wake_in_time(uint64_t time)
-{
-	if (hw_timer_awake_timer > time) {
-		hw_timer_awake_timer = time;
-		hwtimer_update_timer();
-		hwm_find_next_timer();
-	}
-}
-
-/**
- * The kernel wants to skip the next sys_ticks tick interrupts
- * If sys_ticks == 0, the next interrupt will be raised.
- */
-void hwtimer_set_silent_ticks(int64_t sys_ticks)
-{
-	silent_ticks = sys_ticks;
-}
-
-int64_t hwtimer_get_pending_silent_ticks(void)
-{
-	return silent_ticks;
-}
-
-
-/**
- * During boot set the real time clock simulated time not start
- * from the real host time
- */
-void hwtimer_reset_rtc(void)
-{
-	reset_rtc = true;
-}
-
-/**
- * Set a time offset (microseconds) of the RTC simulated time
- * Note: This should not be used after starting
- */
-void hwtimer_set_rtc_offset(int64_t offset)
-{
-	rtc_offset = offset;
-}
-
-/**
- * Set the ratio of the simulated time to host (real) time.
- * Note: This should not be used after starting
- */
-void hwtimer_set_rt_ratio(double ratio)
-{
-	clock_ratio = ratio;
-}
-
-/**
- * Increase or decrease the RTC simulated time by offset_delta
- */
-void hwtimer_adjust_rtc_offset(int64_t offset_delta)
-{
-	rtc_offset += offset_delta;
-}
-
-/**
- * Adjust the ratio of the simulated time by a factor
- */
-void hwtimer_adjust_rt_ratio(double ratio_correction)
-{
-	uint64_t current_stime = hwm_get_time();
-	int64_t s_diff = current_stime - last_radj_stime;
-	/* Accumulated real time drift time since last adjustment: */
-
-	last_radj_rtime += s_diff / clock_ratio;
-	last_radj_stime = current_stime;
-
-#if DEBUG_NP_TIMER
-	char ct[30];
-	int64_t r_drift = (long double)(clock_ratio-1.0)/(clock_ratio)*s_diff;
-
-	last_drift_offset += r_drift;
-	us_time_to_str(ct, current_stime);
-
-	printf("%s(): @%s, s_diff= %llius after last adjust\n"
-		" during which we drifted %.3fms\n"
-		" total acc drift (last_drift_offset) = %.3fms\n"
-		" last_radj_rtime = %.3fms (+%.3fms )\n"
-		" Ratio adjusted to %f\n",
-		__func__, ct, s_diff,
-		r_drift/1000.0,
-		last_drift_offset/1000.0,
-		last_radj_rtime/1000.0,
-		s_diff/clock_ratio/1000.0,
-		clock_ratio*ratio_correction);
-#endif
-
-	clock_ratio *= ratio_correction;
-}
-
-/**
- * Return the current simulated RTC time in microseconds
- */
-int64_t hwtimer_get_simu_rtc_time(void)
-{
-	return hwm_get_time() + rtc_offset;
-}
-
-
-/**
- * Return a version of the host time which would have drifted as if the host
- * real time clock had been running from the native_posix clock, and adjusted
- * both in rate and in offsets as the native_posix has been.
- *
- * Note that this time may be significantly ahead of the simulated time
- * (the time the Zephyr kernel thinks it is).
- * This will be the case in general if native_posix is not able to run at or
- * faster than real time.
- */
-void hwtimer_get_pseudohost_rtc_time(uint32_t *nsec, uint64_t *sec)
-{
-	/*
-	 * Note: long double has a 64bits mantissa in x86.
-	 * Therefore to avoid loss of precision after 500 odd years into
-	 * the epoch, we first calculate the offset from the last adjustment
-	 * time split in us and ns. So we keep the full precision for 500 odd
-	 * years after the last clock ratio adjustment (or native_posix boot,
-	 * whichever is latest).
-	 * Meaning, we will still start to loose precision after 500 off
-	 * years of runtime without a clock ratio adjustment, but that really
-	 * should not be much of a problem, given that the ns lower digits are
-	 * pretty much noise anyhow.
-	 * (So, all this is a huge overkill)
-	 *
-	 * The operation below in plain is just:
-	 *   st = (rt - last_rt_adj_time)*ratio + last_dt_adj_time
-	 * where st = simulated time
-	 *       rt = real time
-	 *       last_rt_adj_time = time (real) when the last ratio
-	 *			    adjustment took place
-	 *       last_st_adj_time = time (simulated) when the last ratio
-	 *			    adjustment took place
-	 *       ratio = ratio between simulated time and real time
-	 */
-	struct timespec tv;
-
-	host_clock_gettime(&tv);
-
-	uint64_t rt_us = (uint64_t)tv.tv_sec * 1000000ULL + tv.tv_nsec / 1000;
-	uint32_t rt_ns = tv.tv_nsec % 1000;
-
-	long double drt_us = (long double)rt_us - last_radj_rtime;
-	long double drt_ns = drt_us * 1000.0L + (long double)rt_ns;
-	long double st = drt_ns * (long double)clock_ratio +
-			 (long double)(last_radj_stime + rtc_offset) * 1000.0L;
-
-	*nsec = fmodl(st, 1e9L);
-	*sec = st / 1e9L;
-}
-
-static struct {
-	double stop_at;
-	double rtc_offset;
-	double rt_drift;
-	double rt_ratio;
-} args;
-
-static void cmd_stop_at_found(char *argv, int offset)
-{
-	ARG_UNUSED(offset);
-	if (args.stop_at < 0) {
-		posix_print_error_and_exit("Error: stop-at must be positive "
-					   "(%s)\n", argv);
-	}
-	hwm_set_end_of_time(args.stop_at*1e6);
-}
-
-static void cmd_realtime_found(char *argv, int offset)
-{
-	ARG_UNUSED(argv);
-	ARG_UNUSED(offset);
-	hwtimer_set_real_time_mode(true);
-}
-
-static void cmd_no_realtime_found(char *argv, int offset)
-{
-	ARG_UNUSED(argv);
-	ARG_UNUSED(offset);
-	hwtimer_set_real_time_mode(false);
-}
-
-static void cmd_rtcoffset_found(char *argv, int offset)
-{
-	ARG_UNUSED(argv);
-	ARG_UNUSED(offset);
-	hwtimer_set_rtc_offset(args.rtc_offset*1e6);
-}
-
-static void cmd_rt_drift_found(char *argv, int offset)
-{
-	ARG_UNUSED(argv);
-	ARG_UNUSED(offset);
-	if (!(args.rt_drift > -1)) {
-		posix_print_error_and_exit("The drift needs to be > -1. "
-					  "Please use --help for more info\n");
-	}
-	args.rt_ratio = args.rt_drift + 1;
-	hwtimer_set_rt_ratio(args.rt_ratio);
-}
-
-static void cmd_rt_ratio_found(char *argv, int offset)
-{
-	ARG_UNUSED(argv);
-	ARG_UNUSED(offset);
-	if ((args.rt_ratio <= 0)) {
-		posix_print_error_and_exit("The ratio needs to be > 0. "
-					  "Please use --help for more info\n");
-	}
-	hwtimer_set_rt_ratio(args.rt_ratio);
-}
-
-static void cmd_rtcreset_found(char *argv, int offset)
-{
-	ARG_UNUSED(argv);
-	ARG_UNUSED(offset);
-	hwtimer_reset_rtc();
-}
-
-static void native_add_time_options(void)
-{
-	static struct args_struct_t timer_options[] = {
-		/*
-		 * Fields:
-		 * manual, mandatory, switch,
-		 * option_name, var_name ,type,
-		 * destination, callback,
-		 * description
-		 */
-		{false, false, true,
-		"rt", "", 'b',
-		NULL, cmd_realtime_found,
-		"Slow down the execution to the host real time, "
-		"or a ratio of it (see --rt-ratio below)"},
-
-		{false, false, true,
-		"no-rt", "", 'b',
-		NULL, cmd_no_realtime_found,
-		"Do NOT slow down the execution to real time, but advance "
-		"Zephyr's time as fast as possible and decoupled from the host "
-		"time"},
-
-		{false, false, false,
-		"rt-drift", "dratio", 'd',
-		(void *)&args.rt_drift, cmd_rt_drift_found,
-		"Drift of the simulated clock relative to the host real time. "
-		"Normally this would be set to a value of a few ppm (e.g. 50e-6"
-		") "
-		"This option has no effect in non real time mode"
-		},
-
-		{false, false, false,
-		"rt-ratio", "ratio", 'd',
-		(void *)&args.rt_ratio, cmd_rt_ratio_found,
-		"Relative speed of the simulated time vs real time. "
-		"For ex. set to 2 to have simulated time pass at double the "
-		"speed of real time. "
-		"Note that both rt-drift & rt-ratio adjust the same clock "
-		"speed, and therefore it does not make sense to use them "
-		"simultaneously. "
-		"This option has no effect in non real time mode"
-		},
-
-		{false, false, false,
-		"rtc-offset", "time_offset", 'd',
-		(void *)&args.rtc_offset, cmd_rtcoffset_found,
-		"At boot offset the RTC clock by this amount of seconds"
-		},
-
-		{false, false, true,
-		"rtc-reset", "", 'b',
-		NULL, cmd_rtcreset_found,
-		"Start the simulated real time clock at 0. Otherwise it starts "
-		"matching the value provided by the host real time clock"},
-
-		{false, false, false,
-		 "stop_at", "time", 'd',
-		(void *)&args.stop_at, cmd_stop_at_found,
-		"In simulated seconds, when to stop automatically"},
-
-		ARG_TABLE_ENDMARKER};
-
-	native_add_command_line_opts(timer_options);
-}
-
-NATIVE_TASK(native_add_time_options, PRE_BOOT_1, 1);
diff --git a/boards/native/native_posix/timer_model.h b/boards/native/native_posix/timer_model.h
deleted file mode 100644
index 2c782d69daa..00000000000
--- a/boards/native/native_posix/timer_model.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2017 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _NATIVE_POSIX_TIMER_MODEL_H
-#define _NATIVE_POSIX_TIMER_MODEL_H
-
-#include "hw_models_top.h"
-#include <stdbool.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void hwtimer_init(void);
-void hwtimer_cleanup(void);
-void hwtimer_set_real_time_mode(bool new_rt);
-void hwtimer_timer_reached(void);
-void hwtimer_wake_in_time(uint64_t time);
-void hwtimer_set_silent_ticks(int64_t sys_ticks);
-void hwtimer_enable(uint64_t period);
-int64_t hwtimer_get_pending_silent_ticks(void);
-
-void hwtimer_reset_rtc(void);
-void hwtimer_set_rtc_offset(int64_t offset);
-void hwtimer_set_rt_ratio(double ratio);
-
-void hwtimer_adjust_rtc_offset(int64_t offset_delta);
-void hwtimer_adjust_rt_ratio(double ratio_correction);
-int64_t hwtimer_get_simu_rtc_time(void);
-void hwtimer_get_pseudohost_rtc_time(uint32_t *nsec, uint64_t *sec);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _NATIVE_POSIX_TIMER_MODEL_H */
diff --git a/boards/native/native_posix/tracing.c b/boards/native/native_posix/tracing.c
deleted file mode 100644
index 5a0c4ec89d8..00000000000
--- a/boards/native/native_posix/tracing.c
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * Copyright (c) 2017 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * Functions to print errors and traces
- */
-
-#include <stdlib.h> /* for exit */
-#include <stdio.h>  /* for printfs */
-#include <stdarg.h> /* for va args */
-#include <unistd.h>
-#include "soc.h"
-#include "posix_board_if.h"
-#include "cmdline.h"
-
-void posix_vprint_error_and_exit(const char *format, va_list vargs)
-{
-	vfprintf(stderr, format, vargs);
-	posix_exit(1);
-}
-
-void posix_vprint_warning(const char *format, va_list vargs)
-{
-	vfprintf(stderr, format, vargs);
-}
-
-void posix_vprint_trace(const char *format, va_list vargs)
-{
-	vfprintf(stdout, format, vargs);
-}
-
-void posix_print_error_and_exit(const char *format, ...)
-{
-	va_list variable_args;
-
-	va_start(variable_args, format);
-	posix_vprint_error_and_exit(format, variable_args);
-	va_end(variable_args);
-}
-
-void posix_print_warning(const char *format, ...)
-{
-	va_list variable_args;
-
-	va_start(variable_args, format);
-	vfprintf(stderr, format, variable_args);
-	va_end(variable_args);
-}
-
-void posix_print_trace(const char *format, ...)
-{
-	va_list variable_args;
-
-	va_start(variable_args, format);
-	vfprintf(stdout, format, variable_args);
-	va_end(variable_args);
-}
-
-/**
- * Are stdout and stderr connected to a tty
- * 0  = no
- * 1  = yes
- * -1 = we do not know yet
- * Indexed 0:stdout, 1:stderr
- */
-static int is_a_tty[2] = {-1, -1};
-
-void trace_disable_color(char *argv, int offset)
-{
-	is_a_tty[0] = 0;
-	is_a_tty[1] = 0;
-}
-
-void trace_enable_color(char *argv, int offset)
-{
-	is_a_tty[0] = -1;
-	is_a_tty[1] = -1;
-
-}
-
-void trace_force_color(char *argv, int offset)
-{
-	is_a_tty[0] = 1;
-	is_a_tty[1] = 1;
-}
-
-int posix_trace_over_tty(int file_number)
-{
-	return is_a_tty[file_number];
-}
-
-static void decide_about_color(void)
-{
-	if (is_a_tty[0] == -1) {
-		is_a_tty[0] = isatty(STDOUT_FILENO);
-	}
-	if (is_a_tty[1] == -1) {
-		is_a_tty[1] = isatty(STDERR_FILENO);
-	}
-}
-
-NATIVE_TASK(decide_about_color, PRE_BOOT_2, 0);
-
-void native_add_tracing_options(void)
-{
-	static struct args_struct_t trace_options[] = {
-		/*
-		 * Fields:
-		 * manual, mandatory, switch,
-		 * option_name, var_name ,type,
-		 * destination, callback,
-		 * description
-		 */
-		{ false, false, true,
-		"color", "color", 'b',
-		NULL, trace_enable_color,
-		"(default) Enable color in traces if printing to console"},
-		{ false, false, true,
-		"no-color", "no-color", 'b',
-		NULL, trace_disable_color,
-		"Disable color in traces even if printing to console"},
-		{ false, false, true,
-		"force-color", "force-color", 'b',
-		NULL, trace_force_color,
-		"Enable color in traces even if printing to files/pipes"},
-		ARG_TABLE_ENDMARKER};
-
-	native_add_command_line_opts(trace_options);
-}
diff --git a/boards/native/native_sim/Kconfig b/boards/native/native_sim/Kconfig
index fc84adda149..4ecdbf702f5 100644
--- a/boards/native/native_sim/Kconfig
+++ b/boards/native/native_sim/Kconfig
@@ -5,7 +5,7 @@ config BOARD_NATIVE_SIM
 	bool
 	select POSIX_ARCH_CONSOLE
 	select NATIVE_LIBRARY
-	select NATIVE_POSIX_TIMER
+	select NATIVE_SIM_TIMER
 	select 64BIT if BOARD_NATIVE_SIM_NATIVE_64
 	imply BOARD_NATIVE_POSIX if NATIVE_SIM_NATIVE_POSIX_COMPAT
 	help
@@ -45,6 +45,7 @@ config BOARD_NATIVE_POSIX
 config NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME
 	bool "Slow down execution to real time (native_posix compat)"
 	select NATIVE_SIM_SLOWDOWN_TO_REAL_TIME
+	select DEPRECATED
 	help
 	  Transitional option which allows applications which targeted native_posix
 	  to set the correct native_sim option (CONFIG_NATIVE_SIM_SLOWDOWN_TO_REAL_TIME)
diff --git a/boards/native/native_sim/Kconfig.defconfig b/boards/native/native_sim/Kconfig.defconfig
index c74a9fe041e..5e1724b4413 100644
--- a/boards/native/native_sim/Kconfig.defconfig
+++ b/boards/native/native_sim/Kconfig.defconfig
@@ -17,7 +17,7 @@ if NETWORKING
 config NET_L2_ETHERNET
 	default y if !NET_LOOPBACK && !NET_TEST
 
-config ETH_NATIVE_POSIX
+config ETH_NATIVE_TAP
 	default y if NET_L2_ETHERNET && ETH_DRIVER
 
 endif # NETWORKING
diff --git a/boards/native/native_sim/cmdline.c b/boards/native/native_sim/cmdline.c
index 0cab99d2832..e1395aa8da6 100644
--- a/boards/native/native_sim/cmdline.c
+++ b/boards/native/native_sim/cmdline.c
@@ -4,11 +4,6 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/*
- * To support native_posix drivers or tests which register their own arguments
- * we provide the same API as in native_posix
- */
-
 #include "nsi_cmdline.h"
 
 void native_add_command_line_opts(struct args_struct_t *args)
diff --git a/boards/native/native_sim/cmdline.h b/boards/native/native_sim/cmdline.h
index acf46d1ce26..cb4465192e1 100644
--- a/boards/native/native_sim/cmdline.h
+++ b/boards/native/native_sim/cmdline.h
@@ -15,8 +15,8 @@ extern "C" {
 #endif
 
 /*
- * To support native_posix drivers or tests which register their own arguments
- * we provide a header with the same name as in native_posix
+ * API provided by native_sim for drivers or tests which want to register their own command line
+ * arguments
  */
 void native_get_cmd_line_args(int *argc, char ***argv);
 void native_get_test_cmd_line_args(int *argc, char ***argv);
diff --git a/boards/native/native_sim/cmdline_common.h b/boards/native/native_sim/cmdline_common.h
index c645caadc00..b8e7692fa52 100644
--- a/boards/native/native_sim/cmdline_common.h
+++ b/boards/native/native_sim/cmdline_common.h
@@ -6,6 +6,9 @@
 #ifndef BOARDS_POSIX_NATIVE_SIM_CMDLINE_COMMON_H
 #define BOARDS_POSIX_NATIVE_SIM_CMDLINE_COMMON_H
 
+#warning "This transitional header is now deprecated and will be removed by v4.4. "\
+	 "Use nsi_cmdline.h instead."
+
 /*
  * To support native_posix drivers which register their own arguments
  * we provide a header with the same name as in native_posix
diff --git a/boards/native/native_sim/doc/index.rst b/boards/native/native_sim/doc/index.rst
index 5e8ec87935c..8cdffc32526 100644
--- a/boards/native/native_sim/doc/index.rst
+++ b/boards/native/native_sim/doc/index.rst
@@ -26,7 +26,7 @@ See `Peripherals`_ for more information.
 
 .. note::
 
-   | ``native_sim`` is an evolution of the older :ref:`native_posix<native_posix>`.
+   | ``native_sim`` is an evolution of its predecessor ``native_posix``.
    | Some components, code, options names, and documentation will still use the old native_posix
      names. But all components which worked with native_posix will work with native_sim.
 
@@ -310,10 +310,10 @@ The following peripherals are currently provided with this board:
 **UART/Serial**
    Two optional native UART drivers are available:
 
-   **PTTY driver (UART_NATIVE_POSIX)**
-      With this driver, one or two Zephyr UART devices can be created. These
+   **PTY driver (UART_NATIVE_PTY)**
+      With this driver, Zephyr UART devices can be created. These
       can be connected to the Linux process stdin/stdout or a newly created
-      pseudo-tty. For more information refer to the section `PTTY UART`_.
+      pseudo-tty. For more information refer to the section `PTY UART`_.
 
    **TTY driver (UART_NATIVE_TTY)**
       An UART driver for interacting with host-attached serial port devices
@@ -469,7 +469,7 @@ The following peripherals are currently provided with this board:
   Some more information can be found in :ref:`the emulators page <emul_flash_simu_brief>`.
 
   The flash content can be accessed from the host system, as explained in the
-  `Host based flash access`_ section.
+  `Host (FUSE) filesystem access`_ section.
 
 **Input events**
   Two optional native input drivers are available:
@@ -510,44 +510,46 @@ The following peripherals are currently provided with this board:
 
 .. _native_ptty_uart:
 
-PTTY UART
+PTY UART
 =========
 
-This driver can be configured with :kconfig:option:`CONFIG_UART_NATIVE_POSIX`
-to instantiate up to two UARTs. By default only one UART is enabled.
-With :kconfig:option:`CONFIG_UART_NATIVE_POSIX_PORT_1_ENABLE`
-you can enable the second one.
-
-For the first UART, it can link it to a new
-pseudoterminal (i.e. :file:`/dev/pts{<nbr>}`), or map the UART input and
-output to the executable's ``stdin`` and ``stdout``.
-This is chosen by selecting either
-:kconfig:option:`CONFIG_NATIVE_UART_0_ON_OWN_PTY` or
-:kconfig:option:`CONFIG_NATIVE_UART_0_ON_STDINOUT`
-For interactive use with the :ref:`shell_api`, choose the first (OWN_PTY) option.
-The second (STDINOUT) option can be used with the shell for automated
-testing, such as when piping other processes' output to control it.
-This is because the shell subsystem expects access to a raw terminal,
+This driver is automatically enabled when devicetree contains nodes with the
+``"zephyr,native-pty-uart"`` compatible property and ``okay`` status and
+:kconfig:option:`CONFIG_SERIAL` is set.
+By default one ready UART of this type is setup in DTS, but any number can be enabled as desired.
+
+Normally these UARTs are connected to new pseudoterminals PTYs, i.e. :file:`/dev/pts{<nbr>}`,
+but it is also possible to map one of them to the executable's ``stdin`` and ``stdout``.
+This can be done in two ways, either with the command line option ``--<uart_name>_stdinout``
+(where ``<uart_name>`` is the UART DTS node name), or, for the first PTY UART instance by chosing
+:kconfig:option:`CONFIG_UART_NATIVE_PTY_0_ON_STDINOUT` instead of the default
+:kconfig:option:`CONFIG_UART_NATIVE_PTY_0_ON_OWN_PTY`.
+For interactive use with the :ref:`shell_api`, it is recommended to choose the PTY option.
+The ``STDINOUT`` option can be used for automated testing, such as when piping other processes'
+output to control it. This is because the shell subsystem expects access to a raw terminal,
 which (by default) a normal Linux terminal is not.
 
-When :kconfig:option:`CONFIG_NATIVE_UART_0_ON_OWN_PTY` is chosen, the name of the
-newly created UART pseudo-terminal will be displayed in the console.
-If you want to interact with it manually, you should attach a terminal emulator
-to it. This can be done, for example with the command:
+When a UART is connected to a new PTY, the name of the newly created UART pseudo-terminal will be
+displayed in the console.
+If you want to interact with it manually, you should attach a terminal emulator to it.
+This can be done, for example with the command:
 
 .. code-block:: console
 
-   $ xterm -e screen /dev/<ttyn> &
+   $ xterm -e screen /dev/<ptyn> &
+   # Or if you prefer gnome-terminal:
+   $ gnome-terminal -- screen /dev/<ptyn> &
 
-where :file:`/dev/tty{<n>}` should be replaced with the actual TTY device.
+where :file:`/dev/{<ptyn>}` should be replaced with the actual PTY device.
 
-You may also chose to automatically attach a terminal emulator to the first UART
-by passing the command line option ``-attach_uart`` to the executable.
-The command used for attaching to the new shell can be set with the command line
-option ``-attach_uart_cmd=<"cmd">``. Where the default command is given by
-:kconfig:option:`CONFIG_NATIVE_UART_AUTOATTACH_DEFAULT_CMD`.
-Note that the default command assumes both ``xterm`` and ``screen`` are
-installed in the system.
+You may also chose to automatically attach a terminal emulator to any of these UARTs.
+To automatically attach one to all these UARTs, pass the command line option ``-attach_uart`` to the
+executable. To automatically attach one to a single UART use ``-<uart_name>_attach_uart``
+The command used for attaching to the new shell can be set for all UARTs with the command line
+option ``-attach_uart_cmd=<"cmd">``, or for each individual UART with
+``-<uart_name>_attach_uart_cmd``. Where the default command is given by
+:kconfig:option:`CONFIG_UART_NATIVE_PTY_AUTOATTACH_DEFAULT_CMD`.
+Note that the default command assumes both ``xterm`` and ``screen`` are installed in the system.
 
 This driver only supports poll mode. Interrupt and async mode are not supported.
 Neither runtime configuration or line control are supported.
@@ -557,9 +559,8 @@ Neither runtime configuration or line control are supported.
 TTY UART
 ========
 
-With this driver an application can use the polling UART API (``uart_poll_out``,
-``uart_poll_in``) to write and read characters to and from a connected serial
-port device.
+With this driver an application can use the polling and interrupt based UART APIs to write and read
+characters to and from a connected serial port device.
 
 This driver is automatically enabled when a devicetree contains a node
 with ``"zephyr,native-tty-uart"`` compatible property and ``okay`` status, such
@@ -612,7 +613,7 @@ development by integrating more seamlessly with the host operating system:
   redirect any :c:func:`printk` write to the native host application's
   ``stdout``.
 
-  This driver is selected by default if the `PTTY UART`_ is not compiled in.
+  This driver is selected by default if no UART driver is compiled in.
   Otherwise :kconfig:option:`CONFIG_UART_CONSOLE` will be set to select the UART as
   console backend.
 
@@ -646,21 +647,18 @@ All :ref:`available HW emulators <emulators>` can be used with native_sim.
 
 .. _native_fuse_flash:
 
-Host based flash access
-***********************
+Host (FUSE) filesystem access
+*****************************
 
-If a flash device is present, the file system partitions on the flash
-device can be exposed through the host file system by enabling
-:kconfig:option:`CONFIG_FUSE_FS_ACCESS`. This option enables a FUSE
-(File system in User space) layer that maps the Zephyr file system calls to
-the required UNIX file system calls, and provides access to the flash file
-system partitions with normal operating system commands such as ``cd``,
-``ls`` and ``mkdir``.
+When building Zephyr with a filesystem, the device partitions can be exposed through the host file
+system by enabling :kconfig:option:`CONFIG_FUSE_FS_ACCESS`. This option enables a FUSE
+(File system in User space) layer that mounts the simulated embedded filesystem in the host
+filesystem, maps the Zephyr file system calls to the required UNIX file system calls, and provides
+access to its partitions with normal operating system commands such as ``cd``, ``ls`` and ``mkdir``.
 
 By default the partitions are exposed through the directory :file:`flash/` in the
 current working directory. This directory can be changed via the command line
-option ``--flash-mount``. As this directory operates as a mount point for FUSE
-you have to ensure that it exists before starting the native_sim board.
+option ``--flash-mount``.
 
 On exit, the native_sim board application will take care of unmounting the
 directory. In the unfortunate case that the native_sim board application
@@ -698,16 +696,16 @@ host libC (:kconfig:option:`CONFIG_EXTERNAL_LIBC`):
    :header: Driver class, driver name, driver kconfig, libC choices
 
      ADC, ADC emul, :kconfig:option:`CONFIG_ADC_EMUL`, All
-     Bluetooth, :ref:`Userchan <nsim_bt_host_cont>`, :kconfig:option:`CONFIG_BT_USERCHAN`, Host libC
+     Bluetooth, :ref:`Userchan <nsim_bt_host_cont>`, :kconfig:option:`CONFIG_BT_USERCHAN`, Host and pico libC
      CAN, CAN native Linux, :kconfig:option:`CONFIG_CAN_NATIVE_LINUX`, All
      Console backend, :ref:`POSIX arch console <nsim_back_console>`, :kconfig:option:`CONFIG_POSIX_ARCH_CONSOLE`, All
      Display, :ref:`Display SDL <nsim_per_disp_sdl>`, :kconfig:option:`CONFIG_SDL_DISPLAY`, All
-     Entropy, :ref:`Native posix entropy <nsim_per_entr>`, :kconfig:option:`CONFIG_FAKE_ENTROPY_NATIVE_POSIX`, All
+     Entropy, :ref:`Native simulator entropy <nsim_per_entr>`, :kconfig:option:`CONFIG_FAKE_ENTROPY_NATIVE_SIM`, All
      EEPROM, EEPROM simulator, :kconfig:option:`CONFIG_EEPROM_SIMULATOR`, All
      EEPROM, EEPROM emulator, :kconfig:option:`CONFIG_EEPROM_EMULATOR`, All
-     Ethernet, :ref:`Eth native_posix <nsim_per_ethe>`, :kconfig:option:`CONFIG_ETH_NATIVE_POSIX`, All
+     Ethernet, :ref:`Eth native_tap <nsim_per_ethe>`, :kconfig:option:`CONFIG_ETH_NATIVE_TAP`, All
      Flash, :ref:`Flash simulator <nsim_per_flash_simu>`, :kconfig:option:`CONFIG_FLASH_SIMULATOR`, All
-     Flash, :ref:`Host based flash access <native_fuse_flash>`, :kconfig:option:`CONFIG_FUSE_FS_ACCESS`, Host libC
+     FUSE, :ref:`Host based filesystem access <native_fuse_flash>`, :kconfig:option:`CONFIG_FUSE_FS_ACCESS`, All
      GPIO, GPIO emulator, :kconfig:option:`CONFIG_GPIO_EMUL`, All
      GPIO, SDL GPIO emulator, :kconfig:option:`CONFIG_GPIO_EMUL_SDL`, All
      I2C, I2C emulator, :kconfig:option:`CONFIG_I2C_EMUL`, All
@@ -716,9 +714,9 @@ host libC (:kconfig:option:`CONFIG_EXTERNAL_LIBC`):
      Logger backend, :ref:`Native backend <nsim_back_logger>`, :kconfig:option:`CONFIG_LOG_BACKEND_NATIVE_POSIX`, All
      Offloaded sockets, :ref:`nsim_per_offloaded_sockets`, :kconfig:option:`CONFIG_NET_NATIVE_OFFLOADED_SOCKETS`, All
      RTC, RTC emul, :kconfig:option:`CONFIG_RTC_EMUL`, All
-     Serial, :ref:`UART native posix/PTTY <native_ptty_uart>`, :kconfig:option:`CONFIG_UART_NATIVE_POSIX`, All
+     Serial, :ref:`UART native PTY <native_ptty_uart>`, :kconfig:option:`CONFIG_UART_NATIVE_PTY`, All
      Serial, :ref:`UART native TTY <native_tty_uart>`, :kconfig:option:`CONFIG_UART_NATIVE_TTY`, All
      SPI, SPI emul, :kconfig:option:`CONFIG_SPI_EMUL`, All
-     System tick, Native_posix timer, :kconfig:option:`CONFIG_NATIVE_POSIX_TIMER`, All
+     System tick, Native_sim timer, :kconfig:option:`CONFIG_NATIVE_SIM_TIMER`, All
      Tracing, :ref:`Posix tracing backend <nsim_back_trace>`, :kconfig:option:`CONFIG_TRACING_BACKEND_POSIX`, All
      USB, :ref:`USB native posix <nsim_per_usb>`, :kconfig:option:`CONFIG_USB_NATIVE_POSIX`, Host libC
diff --git a/boards/native/native_sim/irq_handler.c b/boards/native/native_sim/irq_handler.c
index 38462b4b14a..6eb250f8450 100644
--- a/boards/native/native_sim/irq_handler.c
+++ b/boards/native/native_sim/irq_handler.c
@@ -256,6 +256,11 @@ void posix_isr_declare(unsigned int irq_p, int flags, void isr_p(const void *),
  */
 void posix_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
 {
+	if (irq >= N_IRQS) {
+		posix_print_error_and_exit("Attempted to configure not existent interrupt %u\n",
+					   irq);
+		return;
+	}
 	hw_irq_ctrl_prio_set(irq, prio);
 }
 
diff --git a/boards/native/native_sim/native_posix_compat.h b/boards/native/native_sim/native_posix_compat.h
index 6c943606f3f..f545f4173fe 100644
--- a/boards/native/native_sim/native_posix_compat.h
+++ b/boards/native/native_sim/native_posix_compat.h
@@ -15,6 +15,9 @@
 #ifndef BOARDS_POSIX_NATIVE_SIM_NATIVE_POSIX_COMPAT_H
 #define BOARDS_POSIX_NATIVE_SIM_NATIVE_POSIX_COMPAT_H
 
+#warning "This transitional header is now deprecated and will be removed by v4.4. "\
+	 "Use nsi_hw_scheduler.h instead."
+
 #include <stdint.h>
 #include <zephyr/toolchain.h>
 #include "nsi_hw_scheduler.h"
diff --git a/boards/native/native_sim/native_sim.dts b/boards/native/native_sim/native_sim.dts
index 162fcf07457..4ab4ef76f41 100644
--- a/boards/native/native_sim/native_sim.dts
+++ b/boards/native/native_sim/native_sim.dts
@@ -54,7 +54,7 @@
 		#size-cells = <0>;
 
 		cpu0: cpu@0 {
-			compatible = "zephyr,native-posix-cpu";
+			compatible = "zephyr,native-sim-cpu";
 			reg = <0>;
 		};
 	};
@@ -147,7 +147,7 @@
 
 	uart0: uart {
 		status = "okay";
-		compatible = "zephyr,native-posix-uart";
+		compatible = "zephyr,native-pty-uart";
 		/* Dummy current-speed entry to comply with serial
 		 * DTS binding
 		 */
@@ -155,8 +155,8 @@
 	};
 
 	uart1: uart_1 {
-		status = "okay";
-		compatible = "zephyr,native-posix-uart";
+		status = "disabled";
+		compatible = "zephyr,native-pty-uart";
 		/* Dummy current-speed entry to comply with serial
 		 * DTS binding
 		 */
@@ -165,12 +165,12 @@
 
 	rng: rng {
 		status = "okay";
-		compatible = "zephyr,native-posix-rng";
+		compatible = "zephyr,native-sim-rng";
 	};
 
 	counter0: counter {
 		status = "okay";
-		compatible = "zephyr,native-posix-counter";
+		compatible = "zephyr,native-sim-counter";
 	};
 
 	gpio0: gpio_emul {
@@ -196,6 +196,7 @@
 
 	input_sdl_touch: input-sdl-touch {
 		compatible = "zephyr,input-sdl-touch";
+		display = <&sdl_dc>;
 	};
 
 	can_loopback0: can_loopback0 {
diff --git a/boards/native/native_sim/timer_model.h b/boards/native/native_sim/timer_model.h
index a159ef444f1..b12a4991f17 100644
--- a/boards/native/native_sim/timer_model.h
+++ b/boards/native/native_sim/timer_model.h
@@ -7,6 +7,9 @@
 #ifndef BOARDS_POSIX_NATIVE_SIM_TIMER_MODEL_H
 #define BOARDS_POSIX_NATIVE_SIM_TIMER_MODEL_H
 
+#warning "This transitional header is now deprecated and will be removed by v4.4. "\
+	 "Use nsi_timer_model.h instead."
+
 /*
  * To support the native_posix timer driver
  * we provide a header with the same name as in native_posix
diff --git a/boards/native/nrf_bsim/common/cmdline.h b/boards/native/nrf_bsim/common/cmdline.h
index 004d6202b53..a84f048d094 100644
--- a/boards/native/nrf_bsim/common/cmdline.h
+++ b/boards/native/nrf_bsim/common/cmdline.h
@@ -20,7 +20,7 @@
 #ifndef BOARDS_POSIX_NRF_BSIM_CMDLINE_H
 #define BOARDS_POSIX_NRF_BSIM_CMDLINE_H
 
-#include "../../native_posix/cmdline_common.h"
+#include "../../../native/src/include/nsi_cmdline.h"
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/boards/native/nrf_bsim/doc/nrf54l15bsim.rst b/boards/native/nrf_bsim/doc/nrf54l15bsim.rst
index 3b527545503..6ad96b9d6dc 100644
--- a/boards/native/nrf_bsim/doc/nrf54l15bsim.rst
+++ b/boards/native/nrf_bsim/doc/nrf54l15bsim.rst
@@ -90,6 +90,4 @@ ARM's TrustZone is not modeled in this board. This means that:
   can be labeled as restricted for secure or non secure access.
 * TF-M cannot be used.
 
-Note that the CRACEN peripheral is not modeled.
 As crypto library, Mbed TLS can be used with its SW crypto backend.
-As entropy driver, the :dtcompatible:`zephyr,native-posix-rng` is enabled by default.
diff --git a/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp.dts b/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp.dts
index 39cbc7bcbd8..35a052b7808 100644
--- a/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp.dts
+++ b/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp.dts
@@ -55,7 +55,7 @@
 
 	rng: rng {
 		status = "okay";
-		compatible = "zephyr,native-posix-rng";
+		compatible = "nordic,nrf-cracen-ctrdrbg";
 	};
 
 	psa_rng: psa-rng {
@@ -68,8 +68,6 @@
 	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
 	child-owned-channels = <3 4 7 8 9 10 11>;
 	status = "okay";
-	/delete-property/ clocks;
-	/delete-property/ clock-names;
 };
 
 &cpuapp_rram {
diff --git a/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp_defconfig b/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp_defconfig
index c8f804a2005..0fde4e01b58 100644
--- a/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp_defconfig
+++ b/boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp_defconfig
@@ -6,5 +6,3 @@ CONFIG_NO_OPTIMIZATIONS=y
 
 # Start SYSCOUNTER on driver init
 CONFIG_NRF_GRTC_START_SYSCOUNTER=y
-
-CONFIG_FAKE_ENTROPY_NATIVE_POSIX_SEED_BY_DEFAULT=n
diff --git a/boards/nordic/nrf21540dk/doc/index.rst b/boards/nordic/nrf21540dk/doc/index.rst
index 7ed102b2b61..06c4e26de78 100644
--- a/boards/nordic/nrf21540dk/doc/index.rst
+++ b/boards/nordic/nrf21540dk/doc/index.rst
@@ -1,7 +1,4 @@
-.. _nrf21540dk_nrf52840:
-
-nRF21540 DK
-###########
+.. zephyr:board:: nrf21540dk
 
 Overview
 ********
@@ -25,12 +22,6 @@ The CPU provides support for the following devices:
 * :abbr:`USB (Universal Serial Bus)`
 * :abbr:`WDT (Watchdog Timer)`
 
-.. figure:: img/nrf21540dk_nrf52840.jpg
-     :align: center
-     :alt: nRF21540 DK
-
-     nRF21540 DK (Credit: Nordic Semiconductor)
-
 More information about the board can be found at the `nRF21540 website`_.
 `nRF21540 Product Specification`_ contains the processor's and front end
 module's information and the datasheet.
@@ -44,45 +35,8 @@ of the slow clock is 32.768 kHz. The frequency of the main clock is 32 MHz.
 Supported Features
 ==================
 
-The nrf21540dk/nrf52840 board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `nRF52840 Product Specification`_ and `nRF21540 DK Hardware guide`_
 for a complete list of nRF21540 Development Kit board hardware features.
 
@@ -122,6 +76,8 @@ Front End Module
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``nrf21540dk/nrf52840`` board configuration can be built,
 flashed, and debugged in the usual way. See :ref:`build_an_application` and
 :ref:`application_run` for more details on building and running.
diff --git a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.yaml b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.yaml
index b84c5371d87..d097ead5541 100644
--- a/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.yaml
+++ b/boards/nordic/nrf21540dk/nrf21540dk_nrf52840.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - arduino_gpio
diff --git a/boards/nordic/nrf51dk/doc/img/nrf51dk_nrf51822.jpg b/boards/nordic/nrf51dk/doc/img/nrf51dk.jpg
similarity index 100%
rename from boards/nordic/nrf51dk/doc/img/nrf51dk_nrf51822.jpg
rename to boards/nordic/nrf51dk/doc/img/nrf51dk.jpg
diff --git a/boards/nordic/nrf51dk/doc/index.rst b/boards/nordic/nrf51dk/doc/index.rst
index 8cae453e2ed..7058df1ed57 100644
--- a/boards/nordic/nrf51dk/doc/index.rst
+++ b/boards/nordic/nrf51dk/doc/index.rst
@@ -1,7 +1,4 @@
-.. _nrf51dk_nrf51822:
-
-nRF51 DK
-########
+.. zephyr:board:: nrf51dk
 
 Overview
 ********
@@ -22,12 +19,6 @@ Semiconductor nRF51822 ARM Cortex-M0 CPU and the following devices:
 * :abbr:`UART (Universal asynchronous receiver-transmitter)`
 * :abbr:`WDT (Watchdog Timer)`
 
-.. figure:: img/nrf51dk_nrf51822.jpg
-     :align: center
-     :alt: nRF51 DK
-
-     nRF51 DK (Credit: Nordic Semiconductor)
-
 More information about the board can be found at the
 `nRF51 DK website`_. The `nRF51 Development Kit User Guide`_
 contains the processor's information and the datasheet.
@@ -43,38 +34,8 @@ is 16 MHz.
 Supported Features
 ==================
 
-The nrf51dk/nrf51822 board configuration supports the following nRF51
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `nRF51 DK website`_ and `nRF51 Development Kit User Guide`_
 for a complete list of nRF51 Development Kit board hardware features.
 
@@ -101,6 +62,8 @@ Push buttons
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/nordic/nrf51dk/nrf51dk_nrf51822.yaml b/boards/nordic/nrf51dk/nrf51dk_nrf51822.yaml
index e3aab4cbf85..801aa256adc 100644
--- a/boards/nordic/nrf51dk/nrf51dk_nrf51822.yaml
+++ b/boards/nordic/nrf51dk/nrf51dk_nrf51822.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
 flash: 256
 supported:
diff --git a/boards/nordic/nrf51dongle/doc/img/nrf51dongle_nrf51822.jpg b/boards/nordic/nrf51dongle/doc/img/nrf51dongle.jpg
similarity index 100%
rename from boards/nordic/nrf51dongle/doc/img/nrf51dongle_nrf51822.jpg
rename to boards/nordic/nrf51dongle/doc/img/nrf51dongle.jpg
diff --git a/boards/nordic/nrf51dongle/doc/index.rst b/boards/nordic/nrf51dongle/doc/index.rst
index 63f288e23fc..62a938511e9 100644
--- a/boards/nordic/nrf51dongle/doc/index.rst
+++ b/boards/nordic/nrf51dongle/doc/index.rst
@@ -1,7 +1,4 @@
-.. _nrf51dongle_nrf51422:
-
-nRF51 Dongle
-############
+.. zephyr:board:: nrf51dongle
 
 Overview
 ********
@@ -22,12 +19,6 @@ Semiconductor nRF51822 ARM Cortex-M0 CPU and the following devices:
 * :abbr:`UART (Universal asynchronous receiver-transmitter)`
 * :abbr:`WDT (Watchdog Timer)`
 
-.. figure:: img/nrf51dongle_nrf51822.jpg
-     :align: center
-     :alt: nRF51 Dongle
-
-     nRF51 Dongle (Credit: Nordic Semiconductor)
-
 More information about the board can be found at the
 `nRF51 Dongle website`_. The `Nordic Semiconductor TechDocs`_
 contains the processor's information and the datasheet.
@@ -43,38 +34,8 @@ is 16 MHz.
 Supported Features
 ==================
 
-The nrf51dongle/nrf51822 board configuration supports the following nRF51
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `nRF51 Dongle website`_ and `Nordic Semiconductor TechDocs`_
 for a complete list of nRF51 Dongle hardware features.
 
@@ -96,6 +57,8 @@ Push buttons
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.yaml b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.yaml
index 8622e018ba3..9f87b6282c7 100644
--- a/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.yaml
+++ b/boards/nordic/nrf51dongle/nrf51dongle_nrf51822.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
 flash: 256
 supported:
diff --git a/boards/nordic/nrf52833dk/doc/index.rst b/boards/nordic/nrf52833dk/doc/index.rst
index ed057bbc93c..847fef754a5 100644
--- a/boards/nordic/nrf52833dk/doc/index.rst
+++ b/boards/nordic/nrf52833dk/doc/index.rst
@@ -1,7 +1,4 @@
-.. _nrf52833dk_nrf52833:
-
-nRF52833 DK
-###########
+.. zephyr:board:: nrf52833dk
 
 Overview
 ********
@@ -41,45 +38,8 @@ is 32 MHz.
 Supported Features
 ==================
 
-The ``nrf52833dk/nrf52833`` board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `nRF52833 DK website`_ and `nRF52833 DK Hardware guide`_
 for a complete list of nRF52833 Development Kit board hardware features.
 
@@ -106,6 +66,8 @@ Push buttons
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``nrf52833dk/nrf52833`` board configuration can be built,
 flashed, and debugged in the usual way. See :ref:`build_an_application` and
 :ref:`application_run` for more details on building and running.
@@ -206,36 +168,24 @@ In the table 7.1.1 'aQFN73 ball assignments' select the pins marked
 'General purpose I/O'.  Note that pins marked as 'low frequency I/O only' can only be used
 in under-10KHz applications. They are not suitable for 115200 speed of UART.
 
-References
-**********
-
-.. target-notes::
-
-.. _nRF52833 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52833-DK
-.. _nRF52833 Product Specification: https://docs.nordicsemi.com/bundle/ps_nrf52833/page/keyfeatures_html5.html
-.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html
-.. _nRF52833 DK Hardware guide: https://docs.nordicsemi.com/bundle/ug_nrf52833_dk/page/UG/dk/intro.html
-
-.. _nrf52833dk_nrf52820:
-
 nRF52820 emulation on nRF52833 DK
-#################################
-
-Overview
-********
+*********************************
 
-The ``nrf52833dk/nrf52820`` board is a modified version of the
-:ref:`nrf52833dk_nrf52833` that enforces the limitations imposed by the nRF52820
+The ``nrf52833dk/nrf52820`` board variant is a modified version of the
+:zephyr:board:`nrf52833dk` that enforces the limitations imposed by the nRF52820
 IC, which is a variant of the original nRF52833. Since Nordic does not offer a
 development kit for the nRF52820 you can use this board to develop for this IC
 while using the nRF52833 Development Kit (PCA10100).
 
-See :ref:`nrf52833dk_nrf52833` for more information about the development board
-and `nRF52820 website`_ for the official reference on the IC itself.
+See `nRF52820 website`_ for the official reference on the IC itself.
 
 References
 **********
 
 .. target-notes::
 
+.. _nRF52833 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52833-DK
+.. _nRF52833 Product Specification: https://docs.nordicsemi.com/bundle/ps_nrf52833/page/keyfeatures_html5.html
+.. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html
+.. _nRF52833 DK Hardware guide: https://docs.nordicsemi.com/bundle/ug_nrf52833_dk/page/UG/dk/intro.html
 .. _nRF52820 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52820
diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.yaml b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.yaml
index 62e32392798..682b6a0c67c 100644
--- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.yaml
+++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52820.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
 flash: 256
 supported:
diff --git a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.yaml b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.yaml
index 8ab244fd648..93d3744e2fe 100644
--- a/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.yaml
+++ b/boards/nordic/nrf52833dk/nrf52833dk_nrf52833.yaml
@@ -7,7 +7,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - arduino_gpio
diff --git a/boards/nordic/nrf52840dk/doc/index.rst b/boards/nordic/nrf52840dk/doc/index.rst
index 7c948d7cffd..1c7c30449f9 100644
--- a/boards/nordic/nrf52840dk/doc/index.rst
+++ b/boards/nordic/nrf52840dk/doc/index.rst
@@ -1,7 +1,4 @@
-.. _nrf52840dk_nrf52840:
-
-nRF52840 DK
-###########
+.. zephyr:board:: nrf52840dk
 
 Overview
 ********
@@ -25,12 +22,6 @@ Nordic Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices:
 * :abbr:`USB (Universal Serial Bus)`
 * :abbr:`WDT (Watchdog Timer)`
 
-.. figure:: img/nrf52840dk_nrf52840.jpg
-     :align: center
-     :alt: nRF52840 DK
-
-     nRF52840 DK (Credit: Nordic Semiconductor)
-
 More information about the board can be found at the `nRF52840 DK website`_.
 `nRF52840 Product Specification`_ contains the processor's information
 and the datasheet.
@@ -45,45 +36,8 @@ is 32.768 kHz. The frequency of the main clock is 32 MHz.
 Supported Features
 ==================
 
-The ``nrf52840dk/nrf52840`` board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `nRF52840 DK website`_ and `nRF52840 DK Hardware guide`_
 for a complete list of nRF52840 Development Kit board hardware features.
 
@@ -110,6 +64,8 @@ Push buttons
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``nrf52840dk/nrf52840`` board configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
@@ -216,27 +172,15 @@ in under-10KHz applications. They are not suitable for 115200 speed of UART.
 .. _nrf52840dk_nrf52811:
 
 nRF52811 emulation on nRF52840 DK
-#################################
-
-Overview
-********
+*********************************
 
 The ``nrf52840dk/nrf52811`` board variant is a modified version of the
-:ref:`nrf52840dk_nrf52840` that enforces the limitations imposed by the nRF52811
+:zephyr:board:`nrf52840dk` that enforces the limitations imposed by the nRF52811
 IC, which is a variant of the original nRF52840. Since Nordic does not offer a
 development kit for the nRF52811 you can use this board to develop for this IC
 while using the nRF52840 Development Kit (PCA10056).
 
-See :ref:`nrf52840dk_nrf52840` for more information about the development board
-and `nRF52811 website`_ for the official reference on the IC itself.
-
-
-References
-**********
-
-.. target-notes::
-
-.. _nRF52811 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52811
+See `nRF52811 website`_ for the official reference on the IC itself.
 
 References
 **********
diff --git a/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.yaml b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.yaml
index 4c06984e3de..1316814cc61 100644
--- a/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.yaml
+++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52811.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 24
 flash: 192
 supported:
diff --git a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts
index 03a74b76002..0e61ee5654c 100644
--- a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts
+++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.dts
@@ -21,6 +21,7 @@
 		zephyr,bt-mon-uart = &uart0;
 		zephyr,bt-c2h-uart = &uart0;
 		zephyr,ieee802154 = &ieee802154;
+		zephyr,boot-mode = &boot_mode0;
 	};
 
 	leds {
@@ -276,3 +277,13 @@ zephyr_udc0: &usbd {
 	compatible = "nordic,nrf-usbd";
 	status = "okay";
 };
+
+&gpregret1 {
+	status = "okay";
+
+	boot_mode0: boot_mode@0 {
+		compatible = "zephyr,retention";
+		status = "okay";
+		reg = <0x0 0x1>;
+	};
+};
diff --git a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.yaml b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.yaml
index 313a975e6d0..d257234e739 100644
--- a/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.yaml
+++ b/boards/nordic/nrf52840dk/nrf52840dk_nrf52840.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - arduino_gpio
diff --git a/boards/nordic/nrf52840dk/support/nrf52840dk_qspi_nrfutil_config.json b/boards/nordic/nrf52840dk/support/nrf52840dk_qspi_nrfutil_config.json
index 1918a1e5923..0da2c383c43 100644
--- a/boards/nordic/nrf52840dk/support/nrf52840dk_qspi_nrfutil_config.json
+++ b/boards/nordic/nrf52840dk/support/nrf52840dk_qspi_nrfutil_config.json
@@ -10,7 +10,7 @@
     "io2": 22,
     "io3": 23
   },
-  "flash_size": 67108864,
+  "flash_size": 8388608,
   "sck_frequency": 8000000,
   "address_mode": "MODE24BIT",
   "readoc": "READ4IO",
diff --git a/boards/nordic/nrf52840dongle/doc/img/nrf52840dongle_nrf52840.jpg b/boards/nordic/nrf52840dongle/doc/img/nrf52840dongle.jpg
similarity index 100%
rename from boards/nordic/nrf52840dongle/doc/img/nrf52840dongle_nrf52840.jpg
rename to boards/nordic/nrf52840dongle/doc/img/nrf52840dongle.jpg
diff --git a/boards/nordic/nrf52840dongle/doc/index.rst b/boards/nordic/nrf52840dongle/doc/index.rst
index 9aa6f74811f..95ec7a34288 100644
--- a/boards/nordic/nrf52840dongle/doc/index.rst
+++ b/boards/nordic/nrf52840dongle/doc/index.rst
@@ -1,7 +1,4 @@
-.. _nrf52840dongle_nrf52840:
-
-nRF52840 Dongle
-###############
+.. zephyr:board:: nrf52840dongle
 
 Overview
 ********
@@ -24,12 +21,6 @@ Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices:
 * :abbr:`USB (Universal Serial Bus)`
 * :abbr:`WDT (Watchdog Timer)`
 
-.. figure:: img/nrf52840dongle_nrf52840.jpg
-     :align: center
-     :alt: nRF52840 Dongle
-
-     nRF52840 Dongle
-
 More information about the board can be found at the
 `nRF52840 Dongle website`_. The `nRF52840 Dongle guide`_
 contains the processor's information and the datasheet.
@@ -45,43 +36,8 @@ is 32 MHz.
 Supported Features
 ==================
 
-The ``nrf52840dongle/nrf52840`` board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `nRF52840 Dongle website`_ and `nRF52840 Dongle Hardware description`_
 for a complete list of nRF52840 Dongle board hardware features.
 
@@ -105,6 +61,8 @@ Push buttons
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``nrf52840dongle/nrf52840`` board configuration can be
 built in the usual way (see :ref:`build_an_application` for more details).
 
@@ -126,7 +84,10 @@ Option 1: Using the Built-In Bootloader Only
 The board is factory-programmed with Nordic's bootloader from Nordic's nRF5
 SDK. With this option, you'll use Nordic's `nrfutil`_ program to create
 firmware packages supported by this bootloader and flash them to the
-device. Make sure ``nrfutil`` is installed before proceeding.
+device. Before proceeding make sure:
+
+* ``nrfutil`` is installed.
+* The ``nrf5sdk-tools`` command is installed within ``nrfutil``.
 
 #. Reset the board into the Nordic bootloader by pressing the RESET button.
 
@@ -151,16 +112,19 @@ device. Make sure ``nrfutil`` is installed before proceeding.
 
    .. code-block:: console
 
-      nrfutil pkg generate --hw-version 52 --sd-req=0x00 \
-              --application build/zephyr/zephyr.hex \
-              --application-version 1 blinky.zip
+      nrfutil nrf5sdk-tools pkg generate \
+               --hw-version 52 \
+               --sd-req=0x00 \
+               --application build/zephyr/zephyr.hex \
+               --application-version 1 \
+               blinky.zip
 
 #. Flash it onto the board. Note :file:`/dev/ttyACM0` is for Linux; it will be
    something like ``COMx`` on Windows, and something else on macOS.
 
    .. code-block:: console
 
-      nrfutil dfu usb-serial -pkg blinky.zip -p /dev/ttyACM0
+      nrfutil nrf5sdk-tools dfu usb-serial -pkg blinky.zip -p /dev/ttyACM0
 
    When this command exits, observe the green LED on the board blinking,
    instead of the red LED used by the bootloader.
@@ -198,16 +162,19 @@ to the zephyr repository on your computer.
 
    .. code-block:: console
 
-      nrfutil pkg generate --hw-version 52 --sd-req=0x00 \
-              --application build/mcuboot/zephyr/zephyr.hex \
-              --application-version 1 mcuboot.zip
+      nrfutil nrf5sdk-tools pkg generate \
+               --hw-version 52 \
+               --sd-req=0x00 \
+               --application build/mcuboot/zephyr/zephyr.hex \
+               --application-version 1 \
+               mcuboot.zip
 
 #. Flash it onto the board. Note :file:`/dev/ttyACM0` is for Linux; it will be
    something like ``COMx`` on Windows, and something else on macOS.
 
    .. code-block:: console
 
-      nrfutil dfu usb-serial -pkg mcuboot.zip -p /dev/ttyACM0
+      nrfutil nrf5sdk-tools dfu usb-serial -pkg mcuboot.zip -p /dev/ttyACM0
 
 You can now flash a Zephyr application to the board using MCUboot's serial
 recovery mode. We'll use the :zephyr:code-sample:`smp-svr` sample since it's ready to be
@@ -341,7 +308,7 @@ References
 .. _Nordic Semiconductor USB DFU:
    https://docs.nordicsemi.com/bundle/sdk_nrf5_v17.1.0/page/sdk_app_serial_dfu_bootloader.html
 .. _nrfutil:
-   https://github.com/NordicSemiconductor/pc-nrfutil
+   https://www.nordicsemi.com/Products/Development-tools/nrf-util
 .. _MCUboot:
    https://github.com/JuulLabs-OSS/mcuboot
 .. _mcumgr:
diff --git a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.yaml b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.yaml
index e5410c74c71..7eb89aa894b 100644
--- a/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.yaml
+++ b/boards/nordic/nrf52840dongle/nrf52840dongle_nrf52840.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - usb_device
diff --git a/boards/nordic/nrf52dk/doc/index.rst b/boards/nordic/nrf52dk/doc/index.rst
index 61349e8d31c..6d3c8c06356 100644
--- a/boards/nordic/nrf52dk/doc/index.rst
+++ b/boards/nordic/nrf52dk/doc/index.rst
@@ -1,7 +1,4 @@
-.. _nrf52dk_nrf52832:
-
-nRF52 DK
-########
+.. zephyr:board:: nrf52dk
 
 Overview
 ********
@@ -25,12 +22,6 @@ the following devices:
 * :abbr:`UART (Universal asynchronous receiver-transmitter)`
 * :abbr:`WDT (Watchdog Timer)`
 
-.. figure:: img/nrf52dk_nrf52832.jpg
-     :align: center
-     :alt: nRF52 DK
-
-     nRF52 DK (Credit: Nordic Semiconductor)
-
 More information about the board can be found at the
 `nRF52 DK website`_. `nRF52832 Product Specification`_
 contains the processor's information and the datasheet.
@@ -46,42 +37,8 @@ is 32 MHz.
 Supported Features
 ==================
 
-The ``nrf52dk/nrf52832`` board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `nRF52 DK website`_ and `nRF52832 Product Specification`_
 for a complete list of nRF52 Development Kit board hardware features.
 
@@ -348,6 +305,8 @@ P5/P11
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -397,59 +356,38 @@ You can build and flash the examples to make sure Zephyr is running correctly on
 your board. The button and LED definitions can be found in
 :zephyr_file:`boards/nordic/nrf52dk/nrf52dk_nrf52832.dts`.
 
-References
-**********
-
-.. target-notes::
-
-.. _nRF52 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52-DK
-.. _nRF52832 Product Specification: https://docs.nordicsemi.com/bundle/ps_nrf52832/page/nrf52832_ps.html
-
 .. _nrf52dk_nrf52805:
 
 nRF52805 emulation on nRF52 DK
-##############################
-
-Overview
-********
+******************************
 
-The ``nrf52dk/nrf52805`` board is a modified version of the :ref:`nrf52dk_nrf52832`
+The ``nrf52dk/nrf52805`` board is a modified version of the :zephyr:board:`nrf52dk`
 that enforces the limitations imposed by the nRF52805 IC, which is a
 cost-reduced variant of the original nRF52832. Since Nordic does not offer a
 development kit for the nRF52805, you can use this board to develop for this
 IC while using the nRF52 Development Kit (PCA10040).
 
-See :ref:`nrf52dk_nrf52832` for more information about the development board and
-`nRF52805 website`_ for the official reference on the IC itself.
-
-References
-**********
-
-.. target-notes::
-
-.. _nRF52805 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52805
+See `nRF52805 website`_ for the official reference on the IC itself.
 
 .. _nrf52dk_nrf52810:
 
 nRF52810 emulation on nRF52 DK
-##############################
+******************************
 
-Overview
-********
-
-The ``nrf52dk/nrf52810`` board is a modified version of the :ref:`nrf52dk_nrf52832`
+The ``nrf52dk/nrf52810`` board variant is a modified version of the :zephyr:board:`nrf52dk`
 that enforces the limitations imposed by the nRF52810 IC, which is a
 cost-reduced variant of the original nRF52832. Since Nordic does not offer a
 development kit for the nRF52810 you can use this board to develop for this
 IC while using the nRF52 Development Kit (PCA10040).
 
-See :ref:`nrf52dk_nrf52832` for more information about the development board and
-`nRF52810 website`_ for the official reference on the IC itself.
-
+See `nRF52810 website`_ for the official reference on the IC itself.
 
 References
 **********
 
 .. target-notes::
 
+.. _nRF52 DK website: https://www.nordicsemi.com/Software-and-Tools/Development-Kits/nRF52-DK
+.. _nRF52832 Product Specification: https://docs.nordicsemi.com/bundle/ps_nrf52832/page/nrf52832_ps.html
+.. _nRF52805 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52805
 .. _nRF52810 website: https://www.nordicsemi.com/Products/Low-power-short-range-wireless/nRF52810
diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52805.yaml b/boards/nordic/nrf52dk/nrf52dk_nrf52805.yaml
index 86d3e44b8ef..29f13ebf887 100644
--- a/boards/nordic/nrf52dk/nrf52dk_nrf52805.yaml
+++ b/boards/nordic/nrf52dk/nrf52dk_nrf52805.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - gpio
diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52810.yaml b/boards/nordic/nrf52dk/nrf52dk_nrf52810.yaml
index 46cc9adbac6..d92f22d7d18 100644
--- a/boards/nordic/nrf52dk/nrf52dk_nrf52810.yaml
+++ b/boards/nordic/nrf52dk/nrf52dk_nrf52810.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - gpio
diff --git a/boards/nordic/nrf52dk/nrf52dk_nrf52832.yaml b/boards/nordic/nrf52dk/nrf52dk_nrf52832.yaml
index f50bb91ba04..b2b9939a553 100644
--- a/boards/nordic/nrf52dk/nrf52dk_nrf52832.yaml
+++ b/boards/nordic/nrf52dk/nrf52dk_nrf52832.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 512
 supported:
diff --git a/boards/nordic/nrf5340_audio_dk/doc/index.rst b/boards/nordic/nrf5340_audio_dk/doc/index.rst
index f7b23c0d6de..239e2846b14 100644
--- a/boards/nordic/nrf5340_audio_dk/doc/index.rst
+++ b/boards/nordic/nrf5340_audio_dk/doc/index.rst
@@ -1,7 +1,4 @@
-.. _nrf5340_audio_dk_nrf5340:
-
-nRF5340 Audio DK
-################
+.. zephyr:board:: nrf5340_audio_dk
 
 Overview
 ********
@@ -31,10 +28,6 @@ The nRF5340 Audio DK comes with the following hardware features:
 * Stereo analog input using 3.5 mm jack
 * USB soundcard capability
 
-.. figure:: img/nrf5340_audio_dk.jpg
-     :align: center
-     :alt: nRF5340 DK
-
 More information about the board can be found at the `nRF5340 Audio DK website`_. The `nRF5340 Audio DK hardware guide`_
 contains the processor's information and the datasheet.
 
@@ -59,13 +52,17 @@ the datasheet.
 Supported Features
 ==================
 
-See :ref:`nrf5340dk_nrf5340` and `nRF5340 Audio DK hardware guide`_
+.. zephyr:board-supported-hw::
+
+See :zephyr:board:`nrf5340dk` and `nRF5340 Audio DK hardware guide`_
 for a complete list of nRF5340 Audio DK board hardware features.
 
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -84,7 +81,7 @@ applications as usual (:ref:`build_an_application` and
 
    .. code-block:: console
 
-      west flash -H -r nrfjprog --skip-rebuild
+      west flash -H -r nrfutil --skip-rebuild
 
 .. note::
 
diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.yaml b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.yaml
index 8d8e3781795..b2b5d48b041 100644
--- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.yaml
+++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 448
 flash: 1024
diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml
index ecb4f5d04fd..9f189ce164e 100644
--- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml
+++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpuapp_ns.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 192
 flash: 192
diff --git a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.yaml b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.yaml
index 35e0ba7ca28..bf828e53094 100644
--- a/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.yaml
+++ b/boards/nordic/nrf5340_audio_dk/nrf5340_audio_dk_nrf5340_cpunet.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 64
 flash: 256
diff --git a/boards/nordic/nrf5340dk/doc/index.rst b/boards/nordic/nrf5340dk/doc/index.rst
index 9aa3f79180b..e896701d556 100644
--- a/boards/nordic/nrf5340dk/doc/index.rst
+++ b/boards/nordic/nrf5340dk/doc/index.rst
@@ -1,7 +1,4 @@
-.. _nrf5340dk_nrf5340:
-
-nRF5340 DK
-##########
+.. zephyr:board:: nrf5340dk
 
 Overview
 ********
@@ -40,12 +37,6 @@ nRF5340 SoC provides support for the following devices:
 * :abbr:`USB (Universal Serial Bus)`
 * :abbr:`WDT (Watchdog Timer)`
 
-.. figure:: img/nrf5340dk.jpg
-     :align: center
-     :alt: nRF5340 DK
-
-     nRF5340 DK (Credit: Nordic Semiconductor)
-
 More information about the board can be found at the
 `nRF5340 DK website`_.
 The `nRF5340 DK Product Specification`_
@@ -62,76 +53,8 @@ is 32 MHz.
 Supported Features
 ==================
 
-The ``nrf5340dk/nrf5340/cpuapp`` board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| SPU       | on-chip    | system protection    |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-The ``nrf5340dk/nrf5340/cpunet`` board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `nRF5340 DK Product Specification`_
 for a complete list of nRF5340 DK board hardware features.
 
@@ -168,6 +91,8 @@ Security components
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 nRF5340 application core supports the Armv8-M Security Extension.
 Applications built for the ``nrf5340dk/nrf5340/cpuapp`` board by default
 boot in the Secure state.
@@ -269,7 +194,7 @@ applications as usual (:ref:`build_an_application` and
 
    .. code-block:: console
 
-      west flash -H -r nrfjprog --skip-rebuild
+      west flash -H -r nrfutil --skip-rebuild
 
 .. note::
 
diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.dts b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.dts
index cf21413ede4..c459033b46a 100644
--- a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.dts
+++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.dts
@@ -18,5 +18,16 @@
 		zephyr,code-partition = &slot0_partition;
 		zephyr,sram-secure-partition = &sram0_s;
 		zephyr,sram-non-secure-partition = &sram0_ns;
+		zephyr,boot-mode = &boot_mode0;
+	};
+};
+
+&gpregret1 {
+	status = "okay";
+
+	boot_mode0: boot_mode@0 {
+		compatible = "zephyr,retention";
+		status = "okay";
+		reg = <0x0 0x1>;
 	};
 };
diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.yaml b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.yaml
index 3daf13dbd4f..914353fface 100644
--- a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.yaml
+++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 448
 flash: 1024
diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.yaml b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.yaml
index cec7b107776..eaf2b548531 100644
--- a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.yaml
+++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpuapp_ns.yaml
@@ -4,11 +4,14 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 192
 flash: 192
 supported:
+  - arduino_gpio
+  - arduino_i2c
+  - arduino_serial
+  - arduino_spi
   - i2c
   - pwm
   - watchdog
diff --git a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.yaml b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.yaml
index a44099c4587..90fd8786513 100644
--- a/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.yaml
+++ b/boards/nordic/nrf5340dk/nrf5340dk_nrf5340_cpunet.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 64
 flash: 256
diff --git a/boards/nordic/nrf5340dk/support/nrf5340dk_qspi_nrfutil_config.json b/boards/nordic/nrf5340dk/support/nrf5340dk_qspi_nrfutil_config.json
index f7a1a4a06bd..817d233c1c1 100644
--- a/boards/nordic/nrf5340dk/support/nrf5340dk_qspi_nrfutil_config.json
+++ b/boards/nordic/nrf5340dk/support/nrf5340dk_qspi_nrfutil_config.json
@@ -10,7 +10,7 @@
     "io2": 15,
     "io3": 16
   },
-  "flash_size": 67108864,
+  "flash_size": 8388608,
   "sck_frequency": 8000000,
   "address_mode": "MODE24BIT",
   "readoc": "READ4IO",
diff --git a/boards/nordic/nrf54h20dk/board.cmake b/boards/nordic/nrf54h20dk/board.cmake
index 80963356dc9..5ad6557c003 100644
--- a/boards/nordic/nrf54h20dk/board.cmake
+++ b/boards/nordic/nrf54h20dk/board.cmake
@@ -2,8 +2,9 @@
 
 include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
 
-if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD)
-  if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP)
+if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD
+    OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON)
+  if(CONFIG_SOC_NRF54H20_CPUAPP)
     set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpuapp.JLinkScript)
   else()
     set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpurad.JLinkScript)
diff --git a/boards/nordic/nrf54h20dk/doc/index.rst b/boards/nordic/nrf54h20dk/doc/index.rst
index c8e95e39875..a15e0872dc9 100644
--- a/boards/nordic/nrf54h20dk/doc/index.rst
+++ b/boards/nordic/nrf54h20dk/doc/index.rst
@@ -1,7 +1,4 @@
-.. _nrf54h20dk_nrf54h20:
-
-nRF54H20 DK
-###########
+.. zephyr:board:: nrf54h20dk
 
 Overview
 ********
@@ -59,49 +56,7 @@ nRF54H20 DK has two crystal oscillators:
 Supported Features
 ==================
 
-The ``nrf54h20dk/nrf54h20/cpuapp`` board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| GRTC      | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MEMCONF   | on-chip    | retained_mem         |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-The ``nrf54h20dk/nrf54h20/cpurad`` board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| GRTC      | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MEMCONF   | on-chip    | retained_mem         |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -126,6 +81,12 @@ Push buttons
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
+.. note::
+   When first using the nRF54H20 DK, you must program the `nRF54H20 SoC binaries`_ on the development kit.
+   To do so, follow the bring up steps instructions on the `Getting started with the nRF54H20 DK`_ documentation.
+
 Applications for all targets can be built and flashed the usual way.
 See :ref:`build_an_application` and :ref:`application_run` for more details on
 building and running. Debugging is for now limited to the application and radio
@@ -163,3 +124,9 @@ your board. The button and LED definitions can be found in
 
 .. _nRF Util:
    https://www.nordicsemi.com/Products/Development-tools/nrf-util
+
+.. _Getting started with the nRF54H20 DK:
+   https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/device_guides/nrf54h/ug_nrf54h20_gs.html
+
+.. _nRF54H20 SoC binaries:
+   https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/releases_and_maturity/abi_compatibility.html
diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts
index 6f28374d976..b2139f30249 100644
--- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts
+++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts
@@ -149,16 +149,11 @@
 };
 
 &cpusec_cpuapp_ipc {
-	status = "okay";
 	mbox-names = "tx", "rx";
 	tx-region = <&cpuapp_cpusec_ipc_shm>;
 	rx-region = <&cpusec_cpuapp_ipc_shm>;
 };
 
-&cpusec_bellboard {
-	status = "okay";
-};
-
 ipc0: &cpuapp_cpurad_ipc {
 	status = "okay";
 	mbox-names = "rx", "tx";
diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_0_9_0.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_0_9_0.yaml
index 02acf129ef1..1884ce0a4d0 100644
--- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_0_9_0.yaml
+++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_0_9_0.yaml
@@ -7,7 +7,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 sysbuild: true
 ram: 256
diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts
index 8734ff9f745..0553ab1fab5 100644
--- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts
+++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad.dts
@@ -64,16 +64,11 @@
 };
 
 &cpusec_cpurad_ipc {
-	status = "okay";
 	mbox-names = "tx", "rx";
 	tx-region = <&cpurad_cpusec_ipc_shm>;
 	rx-region = <&cpusec_cpurad_ipc_shm>;
 };
 
-&cpusec_bellboard {
-	status = "okay";
-};
-
 ipc0: &cpuapp_cpurad_ipc {
 	status = "okay";
 	mbox-names = "tx", "rx";
diff --git a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_0_9_0.yaml b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_0_9_0.yaml
index 568f6fcc18e..de557fcc2cd 100644
--- a/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_0_9_0.yaml
+++ b/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_0_9_0.yaml
@@ -7,7 +7,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 sysbuild: true
 ram: 192
diff --git a/boards/nordic/nrf54l09pdk/Kconfig.defconfig b/boards/nordic/nrf54l09pdk/Kconfig.defconfig
index 44589c9b35b..f6c1efe188b 100644
--- a/boards/nordic/nrf54l09pdk/Kconfig.defconfig
+++ b/boards/nordic/nrf54l09pdk/Kconfig.defconfig
@@ -3,9 +3,6 @@
 
 if BOARD_NRF54L09PDK_NRF54L09_CPUAPP
 
-config BT_CTLR
-	default BT
-
 config ROM_START_OFFSET
 	default 0x800 if BOOTLOADER_MCUBOOT
 
diff --git a/boards/nordic/nrf54l09pdk/doc/index.rst b/boards/nordic/nrf54l09pdk/doc/index.rst
index 0ef130b5473..4d5d9e3b3a9 100644
--- a/boards/nordic/nrf54l09pdk/doc/index.rst
+++ b/boards/nordic/nrf54l09pdk/doc/index.rst
@@ -1,7 +1,4 @@
-.. _nrf54l09pdk_nrf54l09:
-
-nRF54L09 PDK
-############
+.. zephyr:board:: nrf54l09pdk
 
 Overview
 ********
@@ -36,29 +33,13 @@ internal or external capacitors.
 Supported Features
 ==================
 
-The ``nrf54l09pdk/nrf54l09/cpuapp`` board target supports the following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| RRAM      | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| GRTC      | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``nrf54l09pdk/nrf54l09/cpuapp`` board target can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
diff --git a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp.yaml b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp.yaml
index e5d61a7c483..6edd22f0a41 100644
--- a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp.yaml
+++ b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp.yaml
@@ -7,7 +7,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 sysbuild: true
 ram: 192
@@ -15,3 +14,4 @@ flash: 200
 supported:
   - counter
   - gpio
+  - watchdog
diff --git a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp_defconfig b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp_defconfig
index 02796a1361e..80996ce11ad 100644
--- a/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp_defconfig
+++ b/boards/nordic/nrf54l09pdk/nrf54l09pdk_nrf54l09_cpuapp_defconfig
@@ -16,14 +16,3 @@ CONFIG_ARM_MPU=y
 
 # Enable hardware stack protection
 CONFIG_HW_STACK_PROTECTION=y
-
-# MPU-based null-pointer dereferencing detection cannot
-# be applied as the (0x0 - 0x400) is unmapped for this target.
-CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
-
-# Enable Cache
-CONFIG_CACHE_MANAGEMENT=y
-CONFIG_EXTERNAL_CACHE=y
-
-# Start SYSCOUNTER on driver init
-CONFIG_NRF_GRTC_START_SYSCOUNTER=y
diff --git a/boards/nordic/nrf54l15dk/Kconfig b/boards/nordic/nrf54l15dk/Kconfig
index 29168aeb17e..bf64dd32293 100644
--- a/boards/nordic/nrf54l15dk/Kconfig
+++ b/boards/nordic/nrf54l15dk/Kconfig
@@ -3,7 +3,7 @@
 
 # nRF54L15 DK board configuration
 
-if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
+if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS || BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS
 
 DT_NRF_MPC := $(dt_nodelabel_path,nrf_mpc)
 
@@ -27,4 +27,4 @@ config NRF_TRUSTZONE_RAM_REGION_SIZE
 	  This abstraction allows us to configure TrustZone without depending
 	  on peripheral specific symbols.
 
-endif # BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
+endif # BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS || BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS
diff --git a/boards/nordic/nrf54l15dk/Kconfig.defconfig b/boards/nordic/nrf54l15dk/Kconfig.defconfig
index 5835146bc57..b7b15587c58 100644
--- a/boards/nordic/nrf54l15dk/Kconfig.defconfig
+++ b/boards/nordic/nrf54l15dk/Kconfig.defconfig
@@ -15,7 +15,7 @@ config ROM_START_OFFSET
 endif # BOARD_NRF54L15DK_NRF54L05_CPUAPP || BOARD_NRF54L15DK_NRF54L10_CPUAPP || \
 	# BOARD_NRF54L15DK_NRF54L15_CPUAPP
 
-if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
+if BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS || BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS
 
 config BT_CTLR
 	default BT
@@ -31,4 +31,4 @@ config FLASH_LOAD_SIZE
 config BUILD_WITH_TFM
 	default y
 
-endif # BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
+endif # BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS || BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS
diff --git a/boards/nordic/nrf54l15dk/Kconfig.nrf54l15dk b/boards/nordic/nrf54l15dk/Kconfig.nrf54l15dk
index 57b90e2c516..c7ae2fff596 100644
--- a/boards/nordic/nrf54l15dk/Kconfig.nrf54l15dk
+++ b/boards/nordic/nrf54l15dk/Kconfig.nrf54l15dk
@@ -3,7 +3,7 @@
 
 config BOARD_NRF54L15DK
 	select SOC_NRF54L05_CPUAPP if BOARD_NRF54L15DK_NRF54L05_CPUAPP
-	select SOC_NRF54L10_CPUAPP if BOARD_NRF54L15DK_NRF54L10_CPUAPP
+	select SOC_NRF54L10_CPUAPP if BOARD_NRF54L15DK_NRF54L10_CPUAPP || BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS
 	select SOC_NRF54L15_CPUAPP if BOARD_NRF54L15DK_NRF54L15_CPUAPP || BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
 	select SOC_NRF54L15_CPUFLPR if BOARD_NRF54L15DK_NRF54L15_CPUFLPR || \
 					    BOARD_NRF54L15DK_NRF54L15_CPUFLPR_XIP
diff --git a/boards/nordic/nrf54l15dk/board.cmake b/boards/nordic/nrf54l15dk/board.cmake
index 08f5afb160d..03383155d98 100644
--- a/boards/nordic/nrf54l15dk/board.cmake
+++ b/boards/nordic/nrf54l15dk/board.cmake
@@ -2,13 +2,15 @@
 # SPDX-License-Identifier: Apache-2.0
 
 if(CONFIG_SOC_NRF54L05_CPUAPP OR CONFIG_SOC_NRF54L10_CPUAPP OR CONFIG_SOC_NRF54L15_CPUAPP)
-  board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
-elseif(CONFIG_SOC_NRF54L05_CPUFLPR OR CONFIG_SOC_NRF54L10_CPUFLPR OR CONFIG_SOC_NRF54L15_CPUFLPR)
+	board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000")
+elseif(CONFIG_SOC_NRF54L15_CPUFLPR)
+  board_runner_args(jlink "--device=nRF54L15_RV32")
+elseif(CONFIG_SOC_NRF54L05_CPUFLPR OR CONFIG_SOC_NRF54L10_CPUFLPR)
   set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54l_05_10_15_cpuflpr.JLinkScript)
   board_runner_args(jlink "--device=RISC-V" "--speed=4000" "-if SW" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}")
 endif()
 
-if(CONFIG_BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS)
+if(CONFIG_BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS OR CONFIG_BOARD_NRF54L15DK_NRF54L10_CPUAPP_NS)
   set(TFM_PUBLIC_KEY_FORMAT "full")
 endif()
 
diff --git a/boards/nordic/nrf54l15dk/board.yml b/boards/nordic/nrf54l15dk/board.yml
index f4214f09d28..8d97ef356a9 100644
--- a/boards/nordic/nrf54l15dk/board.yml
+++ b/boards/nordic/nrf54l15dk/board.yml
@@ -3,11 +3,51 @@ board:
   full_name: nRF54L15 DK
   vendor: nordic
   socs:
-  - name: nrf54l05
-  - name: nrf54l10
-  - name: nrf54l15
-    variants:
-    - name: xip
-      cpucluster: cpuflpr
-    - name: ns
-      cpucluster: cpuapp
+    - name: nrf54l05
+    - name: nrf54l10
+      variants:
+        - name: ns
+          cpucluster: cpuapp
+    - name: nrf54l15
+      variants:
+        - name: xip
+          cpucluster: cpuflpr
+        - name: ns
+          cpucluster: cpuapp
+runners:
+  run_once:
+    '--recover':
+      - runners:
+          - nrfjprog
+          - nrfutil
+        run: first
+        groups:
+          - boards:
+              - nrf54l15dk/nrf54l15/cpuapp
+              - nrf54l15dk/nrf54l15/cpuapp/ns
+              - nrf54l15dk/nrf54l15/cpuflpr
+              - nrf54l15dk/nrf54l15/cpuflpr/xip
+    '--erase':
+      - runners:
+          - nrfjprog
+          - jlink
+          - nrfutil
+        run: first
+        groups:
+          - boards:
+              - nrf54l15dk/nrf54l15/cpuapp
+              - nrf54l15dk/nrf54l15/cpuapp/ns
+              - nrf54l15dk/nrf54l15/cpuflpr
+              - nrf54l15dk/nrf54l15/cpuflpr/xip
+    '--reset':
+      - runners:
+          - nrfjprog
+          - jlink
+          - nrfutil
+        run: last
+        groups:
+          - boards:
+              - nrf54l15dk/nrf54l15/cpuapp
+              - nrf54l15dk/nrf54l15/cpuapp/ns
+              - nrf54l15dk/nrf54l15/cpuflpr
+              - nrf54l15dk/nrf54l15/cpuflpr/xip
diff --git a/boards/nordic/nrf54l15dk/doc/index.rst b/boards/nordic/nrf54l15dk/doc/index.rst
index e4ad1e8ad09..cab58e2d21b 100644
--- a/boards/nordic/nrf54l15dk/doc/index.rst
+++ b/boards/nordic/nrf54l15dk/doc/index.rst
@@ -1,7 +1,4 @@
-.. _nrf54l15dk_nrf54l15:
-
-nRF54L15 DK
-############
+.. zephyr:board:: nrf54l15dk
 
 Overview
 ********
@@ -29,12 +26,6 @@ nRF54L15 Arm Cortex-M33 CPU and the following devices:
 * :abbr:`UARTE (Universal asynchronous receiver-transmitter)`
 * :abbr:`WDT (Watchdog Timer)`
 
-.. figure:: img/nrf54l15dk_nrf54l15.webp
-     :align: center
-     :alt: nRF54L15 DK
-
-     nRF54L15 DK (Credit: Nordic Semiconductor)
-
 Hardware
 ********
 
@@ -49,59 +40,27 @@ internal or external capacitors.
 Supported Features
 ==================
 
-The ``nrf54l15dk/nrf54l15/cpuapp`` board target configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| GRTC      | on-chip    | counter              |
-+-----------+------------+----------------------+
-| MEMCONF   | on-chip    | retained_mem         |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RRAM      | on-chip    | flash                |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SAADC     | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| SPU       | on-chip    | system protection    |
-+-----------+------------+----------------------+
-| TWIM      | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``nrf54l15dk/nrf54l15/cpuapp`` board target can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
 building and running.
 
 Applications for the ``nrf54l15dk/nrf54l15/cpuflpr`` board target need
-to be built as multicore configuration with code snippet called ``vpr_launcher``
-for the application core.
+to be built using sysbuild to include the ``vpr_launcher`` image for the application core.
+
+Enter the following command to compile ``hello_world`` for the FLPR core:
+
+.. code-block:: console
+
+   west build -p -b nrf54l15dk/nrf54l15/cpuflpr --sysbuild
 
-Enter the following command to compile ``hello_world`` for the FLPR core::
- west build -p -b nrf54l15dk/nrf54l15/cpuflpr --sysbuild -- -DSB_VPR_LAUNCHER=y
 
 Flashing
 ========
@@ -148,43 +107,39 @@ Testing the LEDs and buttons in the nRF54L15 DK
 Test the nRF54L15 DK with a :zephyr:code-sample:`blinky` sample.
 
 
-.. _nRF54L15 website: https://www.nordicsemi.com/Products/nRF54L15
-.. _nRF54L15 documentation: https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/device_guides/nrf54l/index.html
-
 .. _nrf54l15dk_nrf54l05:
 
 nRF54L05 emulation on nRF54L15 DK
-#################################
-
-Overview
-********
+*********************************
 
-The ``nrf54l15dk/nrf54l05`` board is a modified version of the :ref:`nrf54l15dk_nrf54l15`
+The ``nrf54l15dk/nrf54l05`` board is a modified version of the :zephyr:board:`nrf54l15dk`
 that enforces the limitations imposed by the nRF54L05 IC, which is a
 cost-reduced variant of the original nRF54L15. Since Nordic does not offer a
 development kit for the nRF54L05, you can use this board to develop for this
 IC while using the nRF54L15 Development Kit (PCA10156).
 
-See :ref:`nrf54l15dk_nrf54l15` for more information about the development board and
-`nRF54L05 website`_ for the official reference on the IC itself.
+See `nRF54L05 website`_ for the official reference on the IC itself.
 
-.. _nRF54L05 website: https://www.nordicsemi.com/Products/nRF54L05
 
 .. _nrf54l15dk_nrf54l10:
 
 nRF54L10 emulation on nRF54L15 DK
-#################################
-
-Overview
-********
+*********************************
 
-The ``nrf54l15dk/nrf54l10`` board is a modified version of the :ref:`nrf54l15dk_nrf54l15`
+The ``nrf54l15dk/nrf54l10`` board is a modified version of the :zephyr:board:`nrf54l15dk`
 that enforces the limitations imposed by the nRF54L10 IC, which is a
 cost-reduced variant of the original nRF54L15. Since Nordic does not offer a
 development kit for the nRF54L10 you can use this board to develop for this
 IC while using the nRF54L15 Development Kit (PCA10156).
 
-See :ref:`nrf54l15dk_nrf54l15` for more information about the development board and
-`nRF54L10 website`_ for the official reference on the IC itself.
+See `nRF54L10 website`_ for the official reference on the IC itself.
 
+References
+**********
+
+.. target-notes::
+
+.. _nRF54L15 website: https://www.nordicsemi.com/Products/nRF54L15
+.. _nRF54L15 documentation: https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/device_guides/nrf54l/index.html
+.. _nRF54L05 website: https://www.nordicsemi.com/Products/nRF54L05
 .. _nRF54L10 website: https://www.nordicsemi.com/Products/nRF54L10
diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l05_cpuapp.yaml b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l05_cpuapp.yaml
index 0c451b19a2e..2a41fbf2ca1 100644
--- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l05_cpuapp.yaml
+++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l05_cpuapp.yaml
@@ -7,7 +7,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 sysbuild: true
 ram: 96
diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l05_cpuapp_defconfig b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l05_cpuapp_defconfig
index 02796a1361e..80996ce11ad 100644
--- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l05_cpuapp_defconfig
+++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l05_cpuapp_defconfig
@@ -16,14 +16,3 @@ CONFIG_ARM_MPU=y
 
 # Enable hardware stack protection
 CONFIG_HW_STACK_PROTECTION=y
-
-# MPU-based null-pointer dereferencing detection cannot
-# be applied as the (0x0 - 0x400) is unmapped for this target.
-CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
-
-# Enable Cache
-CONFIG_CACHE_MANAGEMENT=y
-CONFIG_EXTERNAL_CACHE=y
-
-# Start SYSCOUNTER on driver init
-CONFIG_NRF_GRTC_START_SYSCOUNTER=y
diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp.dts b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp.dts
index 1ae6be3e9e9..020fdd16af2 100644
--- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp.dts
+++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp.dts
@@ -35,29 +35,39 @@
 		compatible = "fixed-partitions";
 		#address-cells = <1>;
 		#size-cells = <1>;
+
 		boot_partition: partition@0 {
 			label = "mcuboot";
 			reg = <0x0 DT_SIZE_K(64)>;
 		};
+
 		slot0_partition: partition@10000 {
 			label = "image-0";
-			reg = <0x10000 DT_SIZE_K(230)>;
+			reg = <0x10000 DT_SIZE_K(224)>;
 		};
-		slot0_ns_partition: partition@49800 {
+
+		slot0_ns_partition: partition@48000 {
 			label = "image-0-nonsecure";
-			reg = <0x49800 DT_SIZE_K(230)>;
+			reg = <0x48000 DT_SIZE_K(224)>;
 		};
-		slot1_partition: partition@83000 {
+
+		slot1_partition: partition@80000 {
 			label = "image-1";
-			reg = <0x83000 DT_SIZE_K(230)>;
+			reg = <0x80000 DT_SIZE_K(224)>;
 		};
-		slot1_ns_partition: partition@bc800 {
+
+		slot1_ns_partition: partition@b8000 {
 			label = "image-1-nonsecure";
-			reg = <0xbc800 DT_SIZE_K(230)>;
+			reg = <0xb8000 DT_SIZE_K(224)>;
 		};
-		storage_partition: partition@f6000 {
+
+		/* 32K from 0xf0000 to 0xf7fff reserved for TF-M partitions */
+
+		storage_partition: partition@f8000 {
 			label = "storage";
-			reg = <0xf6000 DT_SIZE_K(38)>;
+			reg = <0xf8000 DT_SIZE_K(28)>;
 		};
+
+		/* 2K from 0xff000 to 0xff7ff unused */
 	};
 };
diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp.yaml b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp.yaml
index 63afb059b93..d56468281ac 100644
--- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp.yaml
+++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp.yaml
@@ -7,7 +7,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 sysbuild: true
 ram: 192
diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_defconfig b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_defconfig
index 02796a1361e..80996ce11ad 100644
--- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_defconfig
+++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_defconfig
@@ -16,14 +16,3 @@ CONFIG_ARM_MPU=y
 
 # Enable hardware stack protection
 CONFIG_HW_STACK_PROTECTION=y
-
-# MPU-based null-pointer dereferencing detection cannot
-# be applied as the (0x0 - 0x400) is unmapped for this target.
-CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
-
-# Enable Cache
-CONFIG_CACHE_MANAGEMENT=y
-CONFIG_EXTERNAL_CACHE=y
-
-# Start SYSCOUNTER on driver init
-CONFIG_NRF_GRTC_START_SYSCOUNTER=y
diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.dts b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.dts
new file mode 100644
index 00000000000..f1aa851ed2d
--- /dev/null
+++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.dts
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#define USE_NON_SECURE_ADDRESS_MAP 1
+
+#include <nordic/nrf54l10_cpuapp.dtsi>
+#include "nrf54l_05_10_15_cpuapp_common.dtsi"
+
+/ {
+	compatible = "nordic,nrf54l15dk_nrf54l10-cpuapp";
+	model = "Nordic nRF54L15 DK nRF54L10 Application MCU";
+
+	chosen {
+		zephyr,code-partition = &slot0_ns_partition;
+		zephyr,sram = &sram0_ns;
+		zephyr,entropy = &psa_rng;
+	};
+
+	/delete-node/ rng;
+
+	psa_rng: psa-rng {
+		status = "okay";
+	};
+};
+
+/ {
+	/*
+	 * Default SRAM planning when building for nRF54L10 with ARM TrustZone-M support.
+	 * - Lowest 96 kB SRAM allocated to Secure image (sram0_s).
+	 * - Upper 96 kB SRAM allocated to Non-Secure image (sram0_ns).
+	 *
+	 * nRF54L10 has 192 kB of volatile memory (SRAM) but the last 42kB are reserved for
+	 * the FLPR MCU.
+	 * This static layout needs to be the same with the upstream TF-M layout in the
+	 * header flash_layout.h of the relevant platform. Any updates in the layout
+	 * needs to happen both in the flash_layout.h and in this file at the same time.
+	 */
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		sram0_s: image_s@20000000 {
+			/* Secure image memory */
+			reg = <0x20000000 DT_SIZE_K(72)>;
+		};
+
+		sram0_ns: image_ns@20012000 {
+			/* Non-Secure image memory */
+			reg = <0x20012000 DT_SIZE_K(72)>;
+		};
+	};
+};
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		/* nRF54L10 has 1022 kB of non volatile memory (RRAM) but the
+		 * last 62kB are reserved for the FLPR MCU.
+		 *
+		 * This static layout needs to be the same with the upstream TF-M layout in the
+		 * header flash_layout.h of the relevant platform. Any updates in the layout
+		 * needs to happen both in the flash_layout.h and in this file at the same time.
+		 */
+		slot0_partition: partition@0 {
+			label = "image-0";
+			reg = <0x0000000 DT_SIZE_K(384)>;
+		};
+
+		tfm_ps_partition: partition@60000 {
+			label = "tfm-ps";
+			reg = <0x00060000 DT_SIZE_K(16)>;
+		};
+
+		tfm_its_partition: partition@64000 {
+			label = "tfm-its";
+			reg = <0x00064000 DT_SIZE_K(16)>;
+		};
+
+		tfm_otp_partition: partition@68000 {
+			label = "tfm-otp";
+			reg = <0x00068000 DT_SIZE_K(8)>;
+		};
+
+		slot0_ns_partition: partition@6A000 {
+			label = "image-0-nonsecure";
+			reg = <0x0006A000 DT_SIZE_K(504)>;
+		};
+
+		storage_partition: partition@E8000 {
+			label = "storage";
+			reg = <0x000E8000 DT_SIZE_K(32)>;
+		};
+	};
+};
+
+&uart30 {
+	/* Disable so that TF-M can use this UART */
+	status = "disabled";
+};
diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.yaml b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.yaml
new file mode 100644
index 00000000000..9f42daedf4e
--- /dev/null
+++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: nrf54l15dk/nrf54l10/cpuapp/ns
+name: nRF54l15-DK-nRF54l10-Application-Non-Secure
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - zephyr
+ram: 192
+flash: 1022
+supported:
+  - adc
+  - gpio
+  - i2c
+  - spi
+  - counter
+  - watchdog
+  - adc
+  - i2s
+vendor: nordic
+sysbuild: true
diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns_defconfig b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns_defconfig
new file mode 100644
index 00000000000..1d759be671c
--- /dev/null
+++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l10_cpuapp_ns_defconfig
@@ -0,0 +1,36 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
+CONFIG_ARM_TRUSTZONE_M=y
+
+# This Board implies building Non-Secure firmware
+CONFIG_TRUSTED_EXECUTION_NONSECURE=y
+
+# Don't enable the cache in the non-secure image as it is a
+# secure-only peripheral on 54l
+CONFIG_CACHE_MANAGEMENT=n
+CONFIG_EXTERNAL_CACHE=n
+
+CONFIG_UART_CONSOLE=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_GPIO=y
+
+# Start SYSCOUNTER on driver init
+CONFIG_NRF_GRTC_START_SYSCOUNTER=y
+
+# Disable TFM BL2 since it is not supported
+CONFIG_TFM_BL2=n
+
+# Support for silence logging is not supported at the moment
+# Tracked by: NCSDK-31930
+CONFIG_TFM_LOG_LEVEL_SILENCE=n
+
+# The oscillators are configured as secure and cannot be configured
+# from the non secure application directly. This needs to be set
+# otherwise nrfx will try to configure them, resulting in a bus
+# fault.
+CONFIG_SOC_NRF54LX_SKIP_CLOCK_CONFIG=y
diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.yaml b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.yaml
index 4da5c7e9951..3fbfefe01a3 100644
--- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.yaml
+++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp.yaml
@@ -7,7 +7,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 sysbuild: true
 ram: 188
diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_defconfig b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_defconfig
index 02796a1361e..80996ce11ad 100644
--- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_defconfig
+++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_defconfig
@@ -16,14 +16,3 @@ CONFIG_ARM_MPU=y
 
 # Enable hardware stack protection
 CONFIG_HW_STACK_PROTECTION=y
-
-# MPU-based null-pointer dereferencing detection cannot
-# be applied as the (0x0 - 0x400) is unmapped for this target.
-CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
-
-# Enable Cache
-CONFIG_CACHE_MANAGEMENT=y
-CONFIG_EXTERNAL_CACHE=y
-
-# Start SYSCOUNTER on driver init
-CONFIG_NRF_GRTC_START_SYSCOUNTER=y
diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns.yaml b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns.yaml
index 6798de376fd..43bd7c8f244 100644
--- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns.yaml
+++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns.yaml
@@ -1,5 +1,5 @@
 # Copyright (c) 2025 Nordic Semiconductor ASA
-# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+# SPDX-License-Identifier: Apache-2.0
 
 identifier: nrf54l15dk/nrf54l15/cpuapp/ns
 name: nRF54l15-DK-nRF54l15-Application-Non-Secure
diff --git a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns_defconfig b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns_defconfig
index bcd99e01dc9..1d759be671c 100644
--- a/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns_defconfig
+++ b/boards/nordic/nrf54l15dk/nrf54l15dk_nrf54l15_cpuapp_ns_defconfig
@@ -1,5 +1,5 @@
 # Copyright (c) 2025 Nordic Semiconductor ASA
-# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+# SPDX-License-Identifier: Apache-2.0
 
 CONFIG_ARM_MPU=y
 CONFIG_HW_STACK_PROTECTION=y
diff --git a/boards/nordic/nrf54l15dk/nrf54l_05_10_15_cpuapp_common.dtsi b/boards/nordic/nrf54l15dk/nrf54l_05_10_15_cpuapp_common.dtsi
index 323ebfd1a1b..eade6178a6a 100644
--- a/boards/nordic/nrf54l15dk/nrf54l_05_10_15_cpuapp_common.dtsi
+++ b/boards/nordic/nrf54l15dk/nrf54l_05_10_15_cpuapp_common.dtsi
@@ -18,6 +18,7 @@
 		zephyr,flash-controller = &rram_controller;
 		zephyr,flash = &cpuapp_rram;
 		zephyr,ieee802154 = &ieee802154;
+		zephyr,boot-mode = &boot_mode0;
 	};
 };
 
@@ -91,6 +92,16 @@
 	status = "okay";
 };
 
+&gpregret1 {
+	status = "okay";
+
+	boot_mode0: boot_mode@0 {
+		compatible = "zephyr,retention";
+		status = "okay";
+		reg = <0x0 0x1>;
+	};
+};
+
 &spi00 {
 	status = "okay";
 	cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
diff --git a/boards/nordic/nrf54l20pdk/board.yml b/boards/nordic/nrf54l20pdk/board.yml
index de39dcb4a3f..4eaa66669fc 100644
--- a/boards/nordic/nrf54l20pdk/board.yml
+++ b/boards/nordic/nrf54l20pdk/board.yml
@@ -4,6 +4,3 @@ board:
   vendor: nordic
   socs:
   - name: nrf54l20
-    variants:
-    - name: xip
-      cpucluster: cpuflpr
diff --git a/boards/nordic/nrf54l20pdk/doc/index.rst b/boards/nordic/nrf54l20pdk/doc/index.rst
index 7805d2ea9f9..847380d4db6 100644
--- a/boards/nordic/nrf54l20pdk/doc/index.rst
+++ b/boards/nordic/nrf54l20pdk/doc/index.rst
@@ -1,7 +1,4 @@
-.. _nrf54l20pdk_nrf54l20:
-
-nRF54L20 PDK
-############
+.. zephyr:board:: nrf54l20pdk
 
 Overview
 ********
@@ -36,30 +33,13 @@ internal or external capacitors.
 Supported Features
 ==================
 
-The ``nrf54l20pdk/nrf54l20/cpuapp`` board target configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| RRAM      | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| GRTC      | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``nrf54l20pdk/nrf54l20/cpuapp`` board target can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml
index 2f3e9d15fb3..164fd22206b 100644
--- a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml
+++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp.yaml
@@ -7,7 +7,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 sysbuild: true
 ram: 512
diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp_defconfig b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp_defconfig
index 02796a1361e..80996ce11ad 100644
--- a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp_defconfig
+++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuapp_defconfig
@@ -16,14 +16,3 @@ CONFIG_ARM_MPU=y
 
 # Enable hardware stack protection
 CONFIG_HW_STACK_PROTECTION=y
-
-# MPU-based null-pointer dereferencing detection cannot
-# be applied as the (0x0 - 0x400) is unmapped for this target.
-CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
-
-# Enable Cache
-CONFIG_CACHE_MANAGEMENT=y
-CONFIG_EXTERNAL_CACHE=y
-
-# Start SYSCOUNTER on driver init
-CONFIG_NRF_GRTC_START_SYSCOUNTER=y
diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.yaml b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.yaml
index ef6374d0f91..9535e42f71d 100644
--- a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.yaml
+++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr.yaml
@@ -13,3 +13,4 @@ flash: 64
 supported:
   - counter
   - gpio
+  - watchdog
diff --git a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr_defconfig b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr_defconfig
index 75f7c4386e3..90cf13bdee5 100644
--- a/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr_defconfig
+++ b/boards/nordic/nrf54l20pdk/nrf54l20pdk_nrf54l20_cpuflpr_defconfig
@@ -15,5 +15,3 @@ CONFIG_USE_DT_CODE_PARTITION=y
 
 # Execute from SRAM
 CONFIG_XIP=n
-
-CONFIG_RISCV_ALWAYS_SWITCH_THROUGH_ECALL=y
diff --git a/boards/nordic/nrf7002dk/doc/index.rst b/boards/nordic/nrf7002dk/doc/index.rst
index 3e3153c376f..ff9d7c75471 100644
--- a/boards/nordic/nrf7002dk/doc/index.rst
+++ b/boards/nordic/nrf7002dk/doc/index.rst
@@ -1,7 +1,4 @@
-.. _nrf7002dk_nrf5340:
-
-nRF7002 DK
-##########
+.. zephyr:board:: nrf7002dk
 
 Overview
 ********
@@ -28,12 +25,6 @@ The ``nrf7002dk/nrf5340/cpuapp`` board target provides support for the applicati
 nRF5340 SoC. The ``nrf7002dk/nrf5340/cpunet`` board target provides support for the network
 core on the nRF5340 SoC.
 
-.. figure:: img/nrf7002dk.jpg
-   :align: center
-   :alt: nRF7002 DK
-
-   nRF7002 DK (Credit: Nordic Semiconductor)
-
 More information about the board can be found at the
 `nRF7002 DK website`_.
 The `nRF7002 DK Product Specification`_
@@ -53,78 +44,8 @@ Hardware
 Supported features
 ------------------
 
-The ``nrf7002dk/nrf5340/cpuapp`` board configuration supports the following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| RADIO     | nrf7002    | Wi-Fi 6 (802.11ax)   |
-+-----------+------------+----------------------+
-| QSPI      | on-chip    | qspi                 |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| SPU       | on-chip    | system protection    |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-The ``nrf7002dk/nrf5340/cpunet`` board configuration supports the following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `nRF7002 DK Product Specification`_
 for a complete list of nRF7002 DK board hardware features.
 
@@ -173,6 +94,8 @@ The following security components are available:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The nRF5340 application core supports the Armv8-M Security Extension.
 Applications built for the ``nrf7002dk/nrf5340/cpuapp`` board boot by default in the
 secure state.
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.yaml b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.yaml
index 9a6c6531442..707ab18abbc 100644
--- a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.yaml
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 448
 flash: 1024
@@ -17,4 +16,5 @@ supported:
   - usbd
   - usb_device
   - netif:openthread
+  - netif:wifi
 vendor: nordic
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_defconfig b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_defconfig
index 8b28700426e..49f3e03e263 100644
--- a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_defconfig
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_defconfig
@@ -19,5 +19,9 @@ CONFIG_SERIAL=y
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
 
+# Enable RNG
+CONFIG_MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG=y
+CONFIG_MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG_ALLOW_NON_CSPRNG=y
+
 # ISN needs CS-Rand which isn't supported upstream for nRF boards
 CONFIG_NET_TCP_ISN_RFC6528=n
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.yaml b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.yaml
index e74ba0628ab..2607f083004 100644
--- a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.yaml
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpuapp_nrf7001.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 448
 flash: 1024
diff --git a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.yaml b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.yaml
index f04ef6cee84..febd55d7fe3 100644
--- a/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.yaml
+++ b/boards/nordic/nrf7002dk/nrf7002dk_nrf5340_cpunet.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 64
 flash: 256
diff --git a/boards/nordic/nrf9131ek/doc/index.rst b/boards/nordic/nrf9131ek/doc/index.rst
index 236f6b396fc..98bf55e3d6d 100644
--- a/boards/nordic/nrf9131ek/doc/index.rst
+++ b/boards/nordic/nrf9131ek/doc/index.rst
@@ -1,7 +1,4 @@
-.. _nrf9131ek_nrf9131:
-
-nRF9131 EK
-##########
+.. zephyr:board:: nrf9131ek
 
 Overview
 ********
@@ -26,12 +23,6 @@ Cortex-M33F CPU with ARMv8-M Security Extension and the following devices:
 * :abbr:`WDT (Watchdog Timer)`
 * :abbr:`IDAU (Implementation Defined Attribution Unit)`
 
-.. figure:: img/nrf9131ek_nrf9131.webp
-     :align: center
-     :alt: nRF9131 EK
-
-     nRF9131 EK (Credit: Nordic Semiconductor)
-
 The `Nordic Semiconductor TechDocs`_ will soon
 contain the processor's information and the datasheet.
 
@@ -46,40 +37,7 @@ is 32 MHz.
 Supported Features
 ==================
 
-The ``nrf9131ek/nrf9131`` board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| SPU       | on-chip    | system protection    |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -110,6 +68,8 @@ Security components
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 ``nrf9131ek/nrf9131`` supports the Armv8m Security Extension, and by default boots
 in the Secure state.
 
diff --git a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131.yaml b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131.yaml
index 8cb2adc385f..22212b9a29c 100644
--- a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131.yaml
+++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 88
 flash: 1024
diff --git a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.yaml b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.yaml
index 0fac2b9f3c8..69d0260b101 100644
--- a/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.yaml
+++ b/boards/nordic/nrf9131ek/nrf9131ek_nrf9131_ns.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 128
 flash: 212
diff --git a/boards/nordic/nrf9151dk/doc/index.rst b/boards/nordic/nrf9151dk/doc/index.rst
index 2365de529f7..a688062d2dd 100644
--- a/boards/nordic/nrf9151dk/doc/index.rst
+++ b/boards/nordic/nrf9151dk/doc/index.rst
@@ -1,7 +1,4 @@
-.. _nrf9151dk_nrf9151:
-
-nRF9151 DK
-##########
+.. zephyr:board:: nrf9151dk
 
 Overview
 ********
@@ -39,50 +36,7 @@ is 32 MHz.
 Supported Features
 ==================
 
-The ``nrf9151dk/nrf9151`` board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| FLASH     | external   | spi                  |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| GPIO      | external   | i2c                  |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | nRF53      | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| SPU       | on-chip    | system protection    |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-
-.. _nrf9151dk_additional_hardware:
-
-Other hardware features have not been enabled yet for this board.
-See the `nRF9151 website`_ for more information.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -117,6 +71,8 @@ Security components
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 ``nrf9151dk/nrf9151`` supports the Armv8m Security Extension, and by default boots
 in the Secure state.
 
diff --git a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151.yaml b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151.yaml
index aa4473d49ea..73359226597 100644
--- a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151.yaml
+++ b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 88
 flash: 1024
diff --git a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.yaml b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.yaml
index 5b406a35b96..a52bd428105 100644
--- a/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.yaml
+++ b/boards/nordic/nrf9151dk/nrf9151dk_nrf9151_ns.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 128
 flash: 192
diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_14_0.yaml b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_14_0.yaml
index 71e5bc2d0b3..1a33e5c9240 100644
--- a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_14_0.yaml
+++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_14_0.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 88
 flash: 1024
diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_7_0.yaml b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_7_0.yaml
index 52a05c85455..89fc6aac34a 100644
--- a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_7_0.yaml
+++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_0_7_0.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 88
 flash: 1024
diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_14_0.yaml b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_14_0.yaml
index 86161bb4385..a16b89b7b64 100644
--- a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_14_0.yaml
+++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_14_0.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 128
 flash: 192
diff --git a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_7_0.yaml b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_7_0.yaml
index 52b8f85efb4..ea5b804b2ce 100644
--- a/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_7_0.yaml
+++ b/boards/nordic/nrf9160dk/nrf9160dk_nrf9160_ns_0_7_0.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 128
 flash: 192
diff --git a/boards/nordic/nrf9161dk/doc/index.rst b/boards/nordic/nrf9161dk/doc/index.rst
index bb9d4eebbe4..00e2e702823 100644
--- a/boards/nordic/nrf9161dk/doc/index.rst
+++ b/boards/nordic/nrf9161dk/doc/index.rst
@@ -1,7 +1,4 @@
-.. _nrf9161dk_nrf9161:
-
-nRF9161 DK
-##########
+.. zephyr:board:: nrf9161dk
 
 Overview
 ********
@@ -41,49 +38,10 @@ is 32 MHz.
 Supported Features
 ==================
 
-The ``nrf9161dk/nrf9161`` board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| FLASH     | external   | spi                  |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| GPIO      | external   | i2c                  |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | nRF53      | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| SPU       | on-chip    | system protection    |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
+.. zephyr:board-supported-hw::
 
 .. _nrf9161dk_additional_hardware:
 
-Other hardware features have not been enabled yet for this board.
 See `nRF9161 DK website`_ and `nRF9161 Product Specification`_
 for a complete list of nRF9161 DK board hardware features.
 
@@ -120,6 +78,8 @@ Security components
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 ``nrf9161dk/nrf9161`` supports the Armv8m Security Extension, and by default boots
 in the Secure state.
 
diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_7_0.yaml b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_7_0.yaml
index 9d9f07dc48b..930b3a3ddd9 100644
--- a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_7_0.yaml
+++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_7_0.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 88
 flash: 1024
diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_9_0.yaml b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_9_0.yaml
index 55e021d3f68..fad5afb0c8c 100644
--- a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_9_0.yaml
+++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_0_9_0.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 88
 flash: 1024
diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_7_0.yaml b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_7_0.yaml
index 90bd4e63772..806f2c73ea2 100644
--- a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_7_0.yaml
+++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_7_0.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 128
 flash: 192
diff --git a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_9_0.yaml b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_9_0.yaml
index 925c57b71c5..9a71f59a18b 100644
--- a/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_9_0.yaml
+++ b/boards/nordic/nrf9161dk/nrf9161dk_nrf9161_ns_0_9_0.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 128
 flash: 192
diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.yaml b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.yaml
index 68babc33bcf..d4bc799100d 100644
--- a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.yaml
+++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpuapp.yaml
@@ -7,7 +7,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 sysbuild: true
 ram: 512
diff --git a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.yaml b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.yaml
index 543a7377c1d..59ed708713f 100644
--- a/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.yaml
+++ b/boards/nordic/nrf9280pdk/nrf9280pdk_nrf9280_cpurad.yaml
@@ -7,7 +7,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 sysbuild: true
 ram: 32
diff --git a/boards/nordic/thingy52/doc/img/thingy52_nrf52832.jpg b/boards/nordic/thingy52/doc/img/thingy52.jpg
similarity index 100%
rename from boards/nordic/thingy52/doc/img/thingy52_nrf52832.jpg
rename to boards/nordic/thingy52/doc/img/thingy52.jpg
diff --git a/boards/nordic/thingy52/doc/index.rst b/boards/nordic/thingy52/doc/index.rst
index bef78aa2ed6..b40b7f79df4 100644
--- a/boards/nordic/thingy52/doc/index.rst
+++ b/boards/nordic/thingy52/doc/index.rst
@@ -1,7 +1,4 @@
-.. _thingy52_nrf52832:
-
-Thingy:52
-#########
+.. zephyr:board:: thingy52
 
 .. warning::
 
@@ -34,12 +31,6 @@ processor, a set of environmental sensors, a pushbutton, and two RGB LEDs.
 * :abbr:`UART (Universal asynchronous receiver-transmitter)`
 * :abbr:`WDT (Watchdog Timer)`
 
-.. figure:: img/thingy52_nrf52832.jpg
-     :align: center
-     :alt: nRF52 Thingy:52
-
-     nRF52 Thingy:52 (Credit: Nordic Semiconductor)
-
 More information about the board can be found at the `nRF52 DK website`_. The
 `Nordic Thingy:52 guide`_ contains the processor's information and the
 datasheet.
@@ -61,46 +52,7 @@ Thingy:52 has the following features:
 Supported Features
 ==================
 
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| Gas       | on-board   | ccs811               |
-| Sensor    |            |                      |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| GPIO Exp  | on-board   | sx1509b              |
-+-----------+------------+----------------------+
-| Humidity  | on-board   | hts221               |
-| and Temp  |            |                      |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| Pressure  | on-board   | lps22hb_press        |
-| and Temp  |            |                      |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -348,6 +300,8 @@ CCS811
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -362,7 +316,7 @@ Thingy:52 does not have an on-board J-Link debug IC as some other nRF5
 development boards, however, instructions from the :ref:`nordic_segger` page
 also apply to this board, with the additional step of connecting an external
 debugger. A development board with a Debug out connector such as the
-:ref:`nrf52dk_nrf52832` can be used as a debugger with Thingy:52.
+:zephyr:board:`nrf52dk` can be used as a debugger with Thingy:52.
 
 Testing board features
 **********************
diff --git a/boards/nordic/thingy52/thingy52_nrf52832.yaml b/boards/nordic/thingy52/thingy52_nrf52832.yaml
index a49aeaba6ce..80b97596bde 100644
--- a/boards/nordic/thingy52/thingy52_nrf52832.yaml
+++ b/boards/nordic/thingy52/thingy52_nrf52832.yaml
@@ -7,7 +7,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/nordic/thingy53/doc/index.rst b/boards/nordic/thingy53/doc/index.rst
index f82626e1684..a3f49c06c93 100644
--- a/boards/nordic/thingy53/doc/index.rst
+++ b/boards/nordic/thingy53/doc/index.rst
@@ -1,7 +1,4 @@
-.. _thingy53_nrf5340:
-
-Thingy:53
-#########
+.. zephyr:board:: thingy53
 
 Overview
 ********
@@ -25,9 +22,19 @@ support for the network core on the nRF5340 SoC.
 The `Nordic Thingy:53 Hardware guide`_ contains the processor's information and
 the datasheet.
 
+Hardware
+********
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -41,7 +48,7 @@ Thingy:53 does not have an on-board J-Link debug IC as some other nRF5
 development boards, however, instructions from the :ref:`nordic_segger` page
 also apply to this board, with the additional step of connecting an external
 debugger. A development board with a Debug out connector such as the
-:ref:`nrf5340dk_nrf5340` can be used as a debugger with Thingy:53.
+:zephyr:board:`nrf5340dk` can be used as a debugger with Thingy:53.
 
 References
 **********
diff --git a/boards/nordic/thingy53/support/thingy53_qspi_nrfutil_config.json b/boards/nordic/thingy53/support/thingy53_qspi_nrfutil_config.json
index 8138801cd91..9f3c4567731 100644
--- a/boards/nordic/thingy53/support/thingy53_qspi_nrfutil_config.json
+++ b/boards/nordic/thingy53/support/thingy53_qspi_nrfutil_config.json
@@ -10,7 +10,7 @@
     "io2": 15,
     "io3": 16
   },
-  "flash_size": 67108864,
+  "flash_size": 8388608,
   "sck_frequency": 8000000,
   "address_mode": "MODE24BIT",
   "readoc": "READ2IO",
diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.yaml b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.yaml
index bc3d8de14b6..568512216bd 100644
--- a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.yaml
+++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp.yaml
@@ -4,11 +4,11 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 448
 flash: 1024
 supported:
+  - ble
   - gpio
   - i2c
   - pwm
diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.yaml b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.yaml
index 700d0deaf79..e672b5080c4 100644
--- a/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.yaml
+++ b/boards/nordic/thingy53/thingy53_nrf5340_cpuapp_ns.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 192
 flash: 192
diff --git a/boards/nordic/thingy53/thingy53_nrf5340_cpunet.yaml b/boards/nordic/thingy53/thingy53_nrf5340_cpunet.yaml
index c039c5ad9f4..42d7dd6ac14 100644
--- a/boards/nordic/thingy53/thingy53_nrf5340_cpunet.yaml
+++ b/boards/nordic/thingy53/thingy53_nrf5340_cpunet.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 64
 flash: 256
diff --git a/boards/norik/octopus_io_board/doc/index.rst b/boards/norik/octopus_io_board/doc/index.rst
index 088a3b936d3..52238ee0b66 100644
--- a/boards/norik/octopus_io_board/doc/index.rst
+++ b/boards/norik/octopus_io_board/doc/index.rst
@@ -47,6 +47,11 @@ and in the `Octopus IO-Board Documentation`_.
 Hardware
 ********
 
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
 Connections and IOs
 ===================
 
@@ -86,6 +91,8 @@ The board also has multiple built-in test points for measuring current consumpti
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Norik Octopus IO-Board can be programmed and debugged using the Tag-Connect TC2030-IDC 6-pin connector or 6-pin SWD pinheader.
 
 Building an application
diff --git a/boards/norik/octopus_io_board/octopus_io_board_nrf9160.yaml b/boards/norik/octopus_io_board/octopus_io_board_nrf9160.yaml
index e91c1da14b5..d066558c2c9 100644
--- a/boards/norik/octopus_io_board/octopus_io_board_nrf9160.yaml
+++ b/boards/norik/octopus_io_board/octopus_io_board_nrf9160.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/norik/octopus_io_board/octopus_io_board_nrf9160_ns.yaml b/boards/norik/octopus_io_board/octopus_io_board_nrf9160_ns.yaml
index 675c316f6c2..6d541fb1b3e 100644
--- a/boards/norik/octopus_io_board/octopus_io_board_nrf9160_ns.yaml
+++ b/boards/norik/octopus_io_board/octopus_io_board_nrf9160_ns.yaml
@@ -7,7 +7,6 @@ flash: 192
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/norik/octopus_som/doc/index.rst b/boards/norik/octopus_som/doc/index.rst
index 1d3790a04d7..5bbf484599d 100644
--- a/boards/norik/octopus_som/doc/index.rst
+++ b/boards/norik/octopus_som/doc/index.rst
@@ -32,42 +32,10 @@ in the `Octopus SoM Documentation`_.
 Hardware
 ********
 
-The ``octopus_som/nrf9160`` and ``octopus_som/nrf9160/ns`` board targets support the
-following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| SPU       | on-chip    | system protection    |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-| ACCEL     | Analog     | adxl362              |
-+-----------+------------+----------------------+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -91,6 +59,8 @@ SIM select switch
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Norik Octopus SoM can be programmed and debugged using the exposed SWD pins.
 
 Building an application
diff --git a/boards/norik/octopus_som/octopus_som_nrf9160.yaml b/boards/norik/octopus_som/octopus_som_nrf9160.yaml
index 44a13234b8a..f4eafba8e6b 100644
--- a/boards/norik/octopus_som/octopus_som_nrf9160.yaml
+++ b/boards/norik/octopus_som/octopus_som_nrf9160.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/norik/octopus_som/octopus_som_nrf9160_ns.yaml b/boards/norik/octopus_som/octopus_som_nrf9160_ns.yaml
index 85bb40d75ab..dd306bb6621 100644
--- a/boards/norik/octopus_som/octopus_som_nrf9160_ns.yaml
+++ b/boards/norik/octopus_som/octopus_som_nrf9160_ns.yaml
@@ -7,7 +7,6 @@ flash: 192
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/nuvoton/npcm400_evb/doc/index.rst b/boards/nuvoton/npcm400_evb/doc/index.rst
index 93c91eb474a..48758a08cb6 100644
--- a/boards/nuvoton/npcm400_evb/doc/index.rst
+++ b/boards/nuvoton/npcm400_evb/doc/index.rst
@@ -26,33 +26,7 @@ Hardware
 Supported Features
 ==================
 
-The following features are supported:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc controller                      |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c port/controller                 |
-+-----------+------------+-------------------------------------+
-| I3C       | on-chip    | i3c port/controller                 |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WDT       | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/nuvoton/npcm400_evb/npcm400_evb_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -67,6 +41,8 @@ UART0 is configured for serial logs. The default serial setup is 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 This board comes with a Cortex ETM port which facilitates tracing and debugging
 using a single physical connection. In addition, it comes with sockets for
 JTAG-only sessions.
diff --git a/boards/nuvoton/npcx4m8f_evb/Kconfig.defconfig b/boards/nuvoton/npcx4m8f_evb/Kconfig.defconfig
index 4bd26c0d348..f7c7cc5430a 100644
--- a/boards/nuvoton/npcx4m8f_evb/Kconfig.defconfig
+++ b/boards/nuvoton/npcx4m8f_evb/Kconfig.defconfig
@@ -3,6 +3,3 @@
 
 config SYS_CLOCK_TICKS_PER_SEC
 	default 1000
-
-config INPUT
-	default y if KSCAN
diff --git a/boards/nuvoton/npcx4m8f_evb/doc/index.rst b/boards/nuvoton/npcx4m8f_evb/doc/index.rst
index 1fd1e7ae5d9..1f941510cb8 100644
--- a/boards/nuvoton/npcx4m8f_evb/doc/index.rst
+++ b/boards/nuvoton/npcx4m8f_evb/doc/index.rst
@@ -21,42 +21,7 @@ Hardware
 Supported Features
 ==================
 
-The following features are supported:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc controller                      |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c port/controller                 |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| PM        | on-chip    | power management                    |
-+-----------+------------+-------------------------------------+
-| PSL       | on-chip    | power switch logic                  |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pulse width modulator               |
-+-----------+------------+-------------------------------------+
-| TACH      | on-chip    | tachometer sensor                   |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WDT       | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by Zephyr (at the moment)
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -78,6 +43,8 @@ UART1 is configured for serial logs.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 This board comes with a Cortex ETM port which facilitates tracing and debugging
 using a single physical connection. In addition, it comes with sockets for
 JTAG-only sessions.
diff --git a/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.dts b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.dts
index e175105a7e1..6c0e8cc23b4 100644
--- a/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.dts
+++ b/boards/nuvoton/npcx4m8f_evb/npcx4m8f_evb.dts
@@ -16,8 +16,8 @@
 	chosen {
 		zephyr,sram = &sram0;
 		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
 		zephyr,flash = &flash0;
-		zephyr,keyboard-scan = &kscan_input;
 	};
 
 	aliases {
@@ -27,7 +27,6 @@
 		i2c-0 = &i2c0_0;
 		watchdog0 = &twd0;
 		peci-0 = &peci0;
-		kscan0 = &kscan_input;
 	};
 
 	leds-pwm {
@@ -113,10 +112,6 @@
 	row-size = <8>;
 	col-size = <13>;
 	status = "okay";
-
-	kscan_input: kscan-input {
-		compatible = "zephyr,kscan-input";
-	};
 };
 
 &i3c0 {
diff --git a/boards/nuvoton/npcx7m6fb_evb/Kconfig.defconfig b/boards/nuvoton/npcx7m6fb_evb/Kconfig.defconfig
index 91a81edc353..82495946194 100644
--- a/boards/nuvoton/npcx7m6fb_evb/Kconfig.defconfig
+++ b/boards/nuvoton/npcx7m6fb_evb/Kconfig.defconfig
@@ -3,6 +3,3 @@
 
 config SYS_CLOCK_TICKS_PER_SEC
 	default 1000
-
-config INPUT
-	default y if KSCAN
diff --git a/boards/nuvoton/npcx7m6fb_evb/doc/index.rst b/boards/nuvoton/npcx7m6fb_evb/doc/index.rst
index 2dc8382d737..b4e5f67ea02 100644
--- a/boards/nuvoton/npcx7m6fb_evb/doc/index.rst
+++ b/boards/nuvoton/npcx7m6fb_evb/doc/index.rst
@@ -21,28 +21,7 @@ Hardware
 Supported Features
 ==================
 
-The following features are supported:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by Zephyr (at the moment)
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -65,6 +44,8 @@ UART1 is configured for serial logs.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 This board comes with a Cortex ETM port which facilitates tracing and debugging
 using a single physical connection.  In addition, it comes with sockets for
 JTAG only sessions.
diff --git a/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb.dts b/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb.dts
index 34a8cc9de74..3857262528f 100644
--- a/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb.dts
+++ b/boards/nuvoton/npcx7m6fb_evb/npcx7m6fb_evb.dts
@@ -15,8 +15,8 @@
 	chosen {
 		zephyr,sram = &sram0;
 		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
 		zephyr,flash = &flash0;
-		zephyr,keyboard-scan = &kscan_input;
 	};
 
 	aliases {
@@ -28,8 +28,6 @@
 		i2c-0 = &i2c0_0;
 		watchdog0 = &twd0;
 		peci-0 = &peci0;
-		/* For kscan test suites */
-		kscan0 = &kscan_input;
 	};
 
 	pwmleds {
@@ -117,8 +115,4 @@
 	row-size = <8>;
 	col-size = <6>;
 	status = "okay";
-
-	kscan_input: kscan-input {
-		compatible = "zephyr,kscan-input";
-	};
 };
diff --git a/boards/nuvoton/npcx9m6f_evb/Kconfig.defconfig b/boards/nuvoton/npcx9m6f_evb/Kconfig.defconfig
index 3004ce803d4..2114a4ad349 100644
--- a/boards/nuvoton/npcx9m6f_evb/Kconfig.defconfig
+++ b/boards/nuvoton/npcx9m6f_evb/Kconfig.defconfig
@@ -3,6 +3,3 @@
 
 config SYS_CLOCK_TICKS_PER_SEC
 	default 1000
-
-config INPUT
-	default y if KSCAN
diff --git a/boards/nuvoton/npcx9m6f_evb/doc/index.rst b/boards/nuvoton/npcx9m6f_evb/doc/index.rst
index 2e9ac2e368b..0b8ef7d9f06 100644
--- a/boards/nuvoton/npcx9m6f_evb/doc/index.rst
+++ b/boards/nuvoton/npcx9m6f_evb/doc/index.rst
@@ -21,42 +21,7 @@ Hardware
 Supported Features
 ==================
 
-The following features are supported:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc controller                      |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c port/controller                 |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| PM        | on-chip    | power management                    |
-+-----------+------------+-------------------------------------+
-| PSL       | on-chip    | power switch logic                  |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pulse width modulator               |
-+-----------+------------+-------------------------------------+
-| TACH      | on-chip    | tachometer sensor                   |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WDT       | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by Zephyr (at the moment)
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -79,6 +44,8 @@ UART1 is configured for serial logs.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 This board comes with a Cortex ETM port which facilitates tracing and debugging
 using a single physical connection. In addition, it comes with sockets for
 JTAG-only sessions.
diff --git a/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb.dts b/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb.dts
index fe186dca262..08eaf3e3ee1 100644
--- a/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb.dts
+++ b/boards/nuvoton/npcx9m6f_evb/npcx9m6f_evb.dts
@@ -15,8 +15,8 @@
 	chosen {
 		zephyr,sram = &sram0;
 		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
 		zephyr,flash = &flash0;
-		zephyr,keyboard-scan = &kscan_input;
 	};
 
 	aliases {
@@ -31,8 +31,6 @@
 		/* For watchdog sample */
 		watchdog0 = &twd0;
 		peci-0 = &peci0;
-		/* For kscan test suites */
-		kscan0 = &kscan_input;
 	};
 
 	leds-pwm {
@@ -136,8 +134,4 @@
 	row-size = <8>;
 	col-size = <13>;
 	status = "okay";
-
-	kscan_input: kscan-input {
-		compatible = "zephyr,kscan-input";
-	};
 };
diff --git a/boards/nuvoton/numaker_m2l31ki/doc/index.rst b/boards/nuvoton/numaker_m2l31ki/doc/index.rst
index 98838ae7e1d..a91bdc32778 100644
--- a/boards/nuvoton/numaker_m2l31ki/doc/index.rst
+++ b/boards/nuvoton/numaker_m2l31ki/doc/index.rst
@@ -24,30 +24,17 @@ More information about the board can be found at the `NuMaker M2L31KI User Manua
 Supported Features
 ==================
 
-* The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 72MHz.
+.. zephyr:board-supported-hw::
 
-The development board configuration supports the following hardware features:
-
-+-----------+------------+-----------------------+
-| Interface | Controller | Driver/Component      |
-+===========+============+=======================+
-| NVIC      | on-chip    | nested vectored       |
-|           |            | interrupt controller  |
-+-----------+------------+-----------------------+
-| SYSTICK   | on-chip    | system clock          |
-+-----------+------------+-----------------------+
-| UART      | on-chip    | serial port           |
-+-----------+------------+-----------------------+
-| GPIO      | on-chip    | gpio                  |
-+-----------+------------+-----------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
+The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 72MHz.
 
 More details about the supported peripherals are available in `M2L31 TRM`_
-Other hardware features are not currently supported by the Zephyr kernel.
 
 Building and Flashing
 *********************
+
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.yaml b/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.yaml
index 3ed0f87a06c..e553c0c800e 100644
--- a/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.yaml
+++ b/boards/nuvoton/numaker_m2l31ki/numaker_m2l31ki.yaml
@@ -8,7 +8,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 168
 flash: 512
 supported:
diff --git a/boards/nuvoton/numaker_m55m1/Kconfig b/boards/nuvoton/numaker_m55m1/Kconfig
new file mode 100644
index 00000000000..4e60a55a218
--- /dev/null
+++ b/boards/nuvoton/numaker_m55m1/Kconfig
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Nuvoton NuMaker M55M1 board configuration
+#
+# Copyright (c) 2025 Nuvoton Technology Corporation.
+
+config BOARD_NUMAKER_M55M1
+	select SOC_FLASH_NUMAKER
diff --git a/boards/nuvoton/numaker_m55m1/Kconfig.defconfig b/boards/nuvoton/numaker_m55m1/Kconfig.defconfig
new file mode 100644
index 00000000000..923a86f8dfc
--- /dev/null
+++ b/boards/nuvoton/numaker_m55m1/Kconfig.defconfig
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Nuvoton NuMaker M55M1 board configuration
+#
+# Copyright (c) 2025 Nuvoton Technology Corporation.
+
+if BOARD_NUMAKER_M55M1
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y if !MODEM
+
+endif # NETWORKING
+
+endif # BOARD_NUMAKER_M55M1
diff --git a/boards/nuvoton/numaker_m55m1/Kconfig.numaker_m55m1 b/boards/nuvoton/numaker_m55m1/Kconfig.numaker_m55m1
new file mode 100644
index 00000000000..fef8d1e0662
--- /dev/null
+++ b/boards/nuvoton/numaker_m55m1/Kconfig.numaker_m55m1
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Nuvoton NuMaker M55M1 board configuration
+#
+# Copyright (c) 2025 Nuvoton Technology Corporation.
+
+config BOARD_NUMAKER_M55M1
+	select SOC_M55M1XXX
diff --git a/boards/nuvoton/numaker_m55m1/board.cmake b/boards/nuvoton/numaker_m55m1/board.cmake
new file mode 100644
index 00000000000..834a265466e
--- /dev/null
+++ b/boards/nuvoton/numaker_m55m1/board.cmake
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(pyocd "--target=m55m1h2ljae")
+
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/nuvoton/numaker_m55m1/board.yml b/boards/nuvoton/numaker_m55m1/board.yml
new file mode 100644
index 00000000000..4b378e461c6
--- /dev/null
+++ b/boards/nuvoton/numaker_m55m1/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: numaker_m55m1
+  full_name: NUMAKER M55M1
+  vendor: nuvoton
+  socs:
+  - name: m55m1xxx
diff --git a/boards/nuvoton/numaker_m55m1/doc/index.rst b/boards/nuvoton/numaker_m55m1/doc/index.rst
new file mode 100644
index 00000000000..d1b37b22e37
--- /dev/null
+++ b/boards/nuvoton/numaker_m55m1/doc/index.rst
@@ -0,0 +1,78 @@
+.. zephyr:board:: numaker_m55m1
+
+Overview
+********
+
+The NuMaker M55M1 is an Internet of Things (IoT) application focused platform
+specially developed by Nuvoton. The NuMaker-M55M1 is based on the NuMicro® M55M1
+series MCU with ARM® -Cortex®-M55 core.
+
+Features
+========
+- 32-bit Arm Cortex®-M55 M55M1H2LJAE MCU
+- Core clock up to 220 MHz
+- 2 MB embedded Dual Bank Flash and 1344 KB SRAM
+- 128 KB DTCM and 64 KB ITCM
+- USB 2.0 Full-Speed OTG / Device
+- USB 1.1 Host
+- Arduino UNO compatible interface
+- One push-button is for reset
+- Two LEDs: one is for power indication and the other is for user-defined
+- On-board NU-Link2 ICE debugger/programmer with SWD connector
+
+More information about the board can be found at the `NuMaker M55M1 User Manual`_.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 220 MHz.
+
+More details about the supported peripherals are available in `M55M1 TRM`_
+
+Building and Flashing
+*********************
+
+.. zephyr:board-supported-runners::
+
+Flashing
+========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+On board debugger Nu-link2 can emulate UART0 as a virtual COM port over usb,
+To enable this, set ISW1 DIP switch 1-3 (TXD RXD VOM) to ON.
+Connect the NuMaker-M55M1 to your host computer using the USB port, then
+run a serial host program to connect with your board. For example:
+
+.. code-block:: console
+
+   $ minicom -D /dev/ttyACM0
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: numaker_m55m1
+   :goals: flash
+
+Debugging
+=========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: numaker_m55m1
+   :goals: debug
+
+Step through the application in your debugger.
+
+References
+**********
+
+.. target-notes::
+
+.. _NuMaker M55M1 User Manual:
+   https://www.nuvoton.com/products/microcontrollers/arm-cortex-m55-mcus/m55m1-series/
+.. _M55M1 TRM:
+   https://www.nuvoton.com/products/microcontrollers/arm-cortex-m55-mcus/m55m1-series/
diff --git a/boards/nuvoton/numaker_m55m1/doc/m55m1.webp b/boards/nuvoton/numaker_m55m1/doc/m55m1.webp
new file mode 100644
index 00000000000..63acf0ab0b9
Binary files /dev/null and b/boards/nuvoton/numaker_m55m1/doc/m55m1.webp differ
diff --git a/boards/nuvoton/numaker_m55m1/numaker_m55m1-pinctrl.dtsi b/boards/nuvoton/numaker_m55m1/numaker_m55m1-pinctrl.dtsi
new file mode 100644
index 00000000000..9139b82417e
--- /dev/null
+++ b/boards/nuvoton/numaker_m55m1/numaker_m55m1-pinctrl.dtsi
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2025 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "pinctrl/m55m1h2l-pinctrl.h"
+
+&pinctrl {
+	uart0_default: uart0_default {
+		group0 {
+			pinmux = <PB12MFP_UART0_RXD>,
+				 <PB13MFP_UART0_TXD>;
+		};
+	};
+
+	/* TX/RX/RTS/CTS/RST --> D1/D0/A2/A3/D2 --> PB3/PB2/PB8/PB9/PC9 */
+	uart1_default: uart1_default {
+		group0 {
+			pinmux = <PB9MFP_UART1_nCTS>,
+				 <PB8MFP_UART1_nRTS>,
+				 <PB2MFP_UART1_RXD>,
+				 <PB3MFP_UART1_TXD>,
+				 <PC9MFP_GPIO>;
+		};
+	};
+
+	/* EMAC multi-function pins for MDIO, TX, REFCLK, RX pins */
+	emac_default: emac_default {
+		group0 {
+			pinmux = <PE8MFP_EMAC0_RMII_MDC>,
+				 <PE9MFP_EMAC0_RMII_MDIO>,
+				 <PC8MFP_EMAC0_RMII_REFCLK>,
+				 <PC7MFP_EMAC0_RMII_RXD0>,
+				 <PC6MFP_EMAC0_RMII_RXD1>,
+				 <PA7MFP_EMAC0_RMII_CRSDV>,
+				 <PA6MFP_EMAC0_RMII_RXERR>;
+		};
+		group1 {
+			pinmux = <PE10MFP_EMAC0_RMII_TXD0>,
+				 <PE11MFP_EMAC0_RMII_TXD1>,
+				 <PE12MFP_EMAC0_RMII_TXEN>;
+				 slew-rate = "fast";
+		};
+	};
+};
diff --git a/boards/nuvoton/numaker_m55m1/numaker_m55m1.dts b/boards/nuvoton/numaker_m55m1/numaker_m55m1.dts
new file mode 100644
index 00000000000..edfb4bcc0a6
--- /dev/null
+++ b/boards/nuvoton/numaker_m55m1/numaker_m55m1.dts
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2025 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nuvoton/m55m1h2l.dtsi>
+#include "numaker_m55m1-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "Nuvoton NuMaker M55M1 board";
+	compatible = "nuvoton,numaker-m55m1";
+
+	aliases {
+		led0 = &green_led;
+		led1 = &yellow_led;
+	};
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &sram0;
+		zephyr,dtcm = &dtcm;
+		zephyr,itcm = &itcm;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		green_led: led_0 {
+			gpios = <&gpiod 5 GPIO_ACTIVE_LOW>;
+			label = "User LD0";
+		};
+
+		yellow_led: led_1 {
+			gpios = <&gpiod 6 GPIO_ACTIVE_LOW>;
+			label = "User LD1";
+		};
+	};
+};
+
+&gpiod {
+	status = "okay";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 0x8000>;
+		};
+
+		slot0_partition: partition@8000 {
+			label = "image-0";
+			reg = <0x8000 0xf8000>;
+		};
+
+		slot1_partition: partition@100000 {
+			label = "image-1";
+			reg = <0x100000 0xf8000>;
+		};
+
+		storage_partition: partition@1f8000 {
+			label = "storage";
+			reg = <0x1f8000 0x8000>;
+		};
+	};
+};
+
+&sram0 {
+	reg = <0x20100000 DT_SIZE_K(1344)>;
+};
+
+&uart0 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&emac {
+	pinctrl-0 = <&emac_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/boards/nuvoton/numaker_m55m1/numaker_m55m1.yaml b/boards/nuvoton/numaker_m55m1/numaker_m55m1.yaml
new file mode 100644
index 00000000000..2563989c8ef
--- /dev/null
+++ b/boards/nuvoton/numaker_m55m1/numaker_m55m1.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2025 Nuvoton Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: numaker_m55m1
+name: NUVOTON NUMAKER-M55M1 Kit
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 1536
+flash: 2048
+supported:
+  - gpio
+vendor: nuvoton
diff --git a/boards/nuvoton/numaker_m55m1/numaker_m55m1_defconfig b/boards/nuvoton/numaker_m55m1/numaker_m55m1_defconfig
new file mode 100644
index 00000000000..a1f6ad9e5ec
--- /dev/null
+++ b/boards/nuvoton/numaker_m55m1/numaker_m55m1_defconfig
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_GPIO=y
+
+# Enable system clock controller driver
+CONFIG_CLOCK_CONTROL=y
+CONFIG_CLOCK_CONTROL_NUMAKER_SCC=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=220000000
+
+# Enable UART driver
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable FMC
+CONFIG_FLASH=y
diff --git a/boards/nuvoton/numaker_m55m1/support/openocd.cfg b/boards/nuvoton/numaker_m55m1/support/openocd.cfg
new file mode 100644
index 00000000000..c393f756c4d
--- /dev/null
+++ b/boards/nuvoton/numaker_m55m1/support/openocd.cfg
@@ -0,0 +1,2 @@
+source [find interface/nulink.cfg]
+source [find target/numicro.cfg]
diff --git a/boards/nuvoton/numaker_pfm_m467/doc/index.rst b/boards/nuvoton/numaker_pfm_m467/doc/index.rst
index 70d4cba1ec0..622a84c9eb9 100644
--- a/boards/nuvoton/numaker_pfm_m467/doc/index.rst
+++ b/boards/nuvoton/numaker_pfm_m467/doc/index.rst
@@ -27,30 +27,17 @@ More information about the board can be found at the `PFM M467 User Manual`_.
 Supported Features
 ==================
 
-* The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 200MHz.
+.. zephyr:board-supported-hw::
 
-The development board configuration supports the following hardware features:
-
-+-----------+------------+-----------------------+
-| Interface | Controller | Driver/Component      |
-+===========+============+=======================+
-| NVIC      | on-chip    | nested vectored       |
-|           |            | interrupt controller  |
-+-----------+------------+-----------------------+
-| SYSTICK   | on-chip    | system clock          |
-+-----------+------------+-----------------------+
-| UART      | on-chip    | serial port           |
-+-----------+------------+-----------------------+
-| GPIO      | on-chip    | gpio                  |
-+-----------+------------+-----------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
+The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 200MHz.
 
 More details about the supported peripherals are available in `M460 TRM`_
-Other hardware features are not currently supported by the Zephyr kernel.
 
 Building and Flashing
 *********************
+
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.yaml b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.yaml
index a7e26960ae6..3f709b8447d 100644
--- a/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.yaml
+++ b/boards/nuvoton/numaker_pfm_m467/numaker_pfm_m467.yaml
@@ -8,7 +8,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 512
 flash: 1024
 supported:
diff --git a/boards/nuvoton/numaker_pfm_m487/doc/index.rst b/boards/nuvoton/numaker_pfm_m487/doc/index.rst
index ce0e583bf30..78dbcaeb432 100644
--- a/boards/nuvoton/numaker_pfm_m487/doc/index.rst
+++ b/boards/nuvoton/numaker_pfm_m487/doc/index.rst
@@ -29,25 +29,11 @@ More information about the board can be found at the `PFM M487 User Manual`_.
 Supported Features
 ==================
 
-* The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 192MHz.
+.. zephyr:board-supported-hw::
 
-The development board configuration supports the following hardware features:
-
-+-----------+------------+-----------------------+
-| Interface | Controller | Driver/Component      |
-+===========+============+=======================+
-| NVIC      | on-chip    | nested vectored       |
-|           |            | interrupt controller  |
-+-----------+------------+-----------------------+
-| SYSTICK   | on-chip    | system clock          |
-+-----------+------------+-----------------------+
-| UART      | on-chip    | serial port           |
-+-----------+------------+-----------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
+The on-board 12-MHz crystal allows the device to run at its maximum operating speed of 192MHz.
 
 More details about the supported peripherals are available in `M480 TRM`_
-Other hardware features are not currently supported by the Zephyr kernel.
 
 Building and Flashing
 *********************
diff --git a/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487.yaml b/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487.yaml
index 396f6780698..0c747394be2 100644
--- a/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487.yaml
+++ b/boards/nuvoton/numaker_pfm_m487/numaker_pfm_m487.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 160
 flash: 512
 vendor: nuvoton
diff --git a/boards/nxp/common/board-footer.rst b/boards/nxp/common/board-footer.rst
new file mode 100644
index 00000000000..98edbdf6281
--- /dev/null
+++ b/boards/nxp/common/board-footer.rst
@@ -0,0 +1,32 @@
+:orphan:
+
+.. nxp-board-footer
+
+Support Resources for Zephyr
+============================
+- `NXP Zephyr Downstream Software Development Kit`_
+- `MCUXpresso for VS Code`_, `wiki`_ documentation and `Zephyr lab guides`_
+- `NXP Zephyr Knowledge Hub`_
+- `NXP’s Zephyr landing page`_  (including training resources)
+- `NXP Support Community forum for Zephyr`_
+
+.. _NXP Zephyr Downstream Software Development Kit:
+   https://github.com/nxp-zephyr/nxp-zsdk
+
+.. _MCUXpresso for VS Code:
+   https://www.nxp.com/design/design-center/software/embedded-software/mcuxpresso-for-visual-studio-code:MCUXPRESSO-VSC?tid=vanMCUXPRESSO-VSC
+
+.. _wiki:
+   https://github.com/nxp-mcuxpresso/vscode-for-mcux/wiki
+
+.. _Zephyr lab guides:
+   https://github.com/nxp-mcuxpresso/vscode-for-mcux/wiki/Training-Zephyr-Getting-Started
+
+.. _NXP Zephyr Knowledge Hub:
+   https://community.nxp.com/t5/Zephyr-Project-Knowledge-Base/Zephyr-Knowledge-Hub/ta-p/2008548
+
+.. _NXP’s Zephyr landing page:
+   https://nxp.com/zephyr
+
+.. _NXP Support Community forum for Zephyr:
+   https://community.nxp.com/t5/Zephyr-Project/bd-p/Zephyr-Project
diff --git a/boards/nxp/frdm_k22f/doc/index.rst b/boards/nxp/frdm_k22f/doc/index.rst
index ef2420ac0f4..fa8762225ae 100644
--- a/boards/nxp/frdm_k22f/doc/index.rst
+++ b/boards/nxp/frdm_k22f/doc/index.rst
@@ -50,55 +50,15 @@ For more information about the K22F SoC and FRDM-K22F board:
 Supported Features
 ==================
 
-The frdm_k22f board configuration supports the hardware features listed
-below.  For additional features not yet supported, please also refer to the
-:zephyr:board:`frdm_k64f`, which is the superset board in NXP's Kinetis K series.
-NXP prioritizes enabling the superset board with NXP's Full Platform Support for
-Zephyr.  Therefore, the frdm_k64f board may have additional features
-already supported, which can also be re-used on this frdm_k22f board:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | soc flash                           |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| SENSOR    | off-chip   | fxos8700 polling;                   |
-|           |            | fxos8700 trigger                    |
-+-----------+------------+-------------------------------------+
-| RNGA      | on-chip    | entropy;                            |
-|           |            | random                              |
-+-----------+------------+-------------------------------------+
-| FTFE      | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-
-:zephyr_file:`boards/nxp/frdm_k22f/frdm_k22f_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   For additional features not yet supported, please also refer to the
+   :zephyr:board:`frdm_k64f`, which is the superset board in NXP's Kinetis K series.
+   NXP prioritizes enabling the superset board with NXP's Full Platform Support for
+   Zephyr.  Therefore, the frdm_k64f board may have additional features
+   already supported, which can also be re-used on this frdm_k22f board.
 
 Connections and IOs
 ===================
@@ -168,6 +128,8 @@ Only USB device function is supported in Zephyr at the moment.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -277,6 +239,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS v2.0.0 *****
    Hello World! frdm_k22f
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _FRDM-K22F Website:
    https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/freedom-development-boards/mcu-boards/nxp-freedom-development-platform-for-kinetis-k22-mcus:FRDM-K22F
 
diff --git a/boards/nxp/frdm_k64f/doc/index.rst b/boards/nxp/frdm_k64f/doc/index.rst
index 192398674c7..6ac28c0682c 100644
--- a/boards/nxp/frdm_k64f/doc/index.rst
+++ b/boards/nxp/frdm_k64f/doc/index.rst
@@ -54,62 +54,9 @@ Supported Features
 NXP considers the FRDM-K64F as the superset board for the Kinetis K
 series of MCUs.  This board is a focus for NXP's Full Platform Support for
 Zephyr, to better enable the entire Kinetis K series.  NXP prioritizes enabling
-this board with new support for Zephyr features.  The frdm_k64f board
-configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | dac                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | soc flash                           |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| SENSOR    | off-chip   | fxos8700 polling;                   |
-|           |            | fxos8700 trigger                    |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma                                 |
-+-----------+------------+-------------------------------------+
-| RNGA      | on-chip    | entropy;                            |
-|           |            | random                              |
-+-----------+------------+-------------------------------------+
-| FTFE      | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-| PIT       | on-chip    | pit                                 |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/frdm_k64f/frdm_k64f_defconfig`
-
-Other hardware features are not currently supported by the port.
+this board with new support for Zephyr features.
+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -223,6 +170,8 @@ use the CAN bus, an external CAN bus transceiver must be connected to ``PTB18``
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -358,6 +307,9 @@ of pyocd commands:
    Resetting target
    >>> quit
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _FRDM-K64F Website:
    https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-k64-k63-and-k24-mcus:FRDM-K64F
 
diff --git a/boards/nxp/frdm_k64f/frdm_k64f.yaml b/boards/nxp/frdm_k64f/frdm_k64f.yaml
index 578ac4edd0d..11cff339ce9 100644
--- a/boards/nxp/frdm_k64f/frdm_k64f.yaml
+++ b/boards/nxp/frdm_k64f/frdm_k64f.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - arduino_gpio
diff --git a/boards/nxp/frdm_k64f/support/pyocd.yaml b/boards/nxp/frdm_k64f/support/pyocd.yaml
new file mode 100644
index 00000000000..ded7208f43c
--- /dev/null
+++ b/boards/nxp/frdm_k64f/support/pyocd.yaml
@@ -0,0 +1,2 @@
+connect_mode: 'under-reset'
+reset_type: 'hw'
diff --git a/boards/nxp/frdm_k82f/doc/index.rst b/boards/nxp/frdm_k82f/doc/index.rst
index 4693e0dd244..d775fae90d4 100644
--- a/boards/nxp/frdm_k82f/doc/index.rst
+++ b/boards/nxp/frdm_k82f/doc/index.rst
@@ -51,59 +51,15 @@ For more information about the K82F SoC and FRDM-K82F board:
 Supported Features
 ==================
 
-The frdm_k82f board configuration supports the hardware features listed
-below.  For additional features not yet supported, please also refer to the
-:zephyr:board:`frdm_k64f`, which is the superset board in NXP's Kinetis K series.
-NXP prioritizes enabling the superset board with NXP's Full Platform Support for
-Zephyr.  Therefore, the frdm_k64f board may have additional features
-already supported, which can also be re-used on this frdm_k82f board:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | soc flash                           |
-+-----------+------------+-------------------------------------+
-| FLASH     | off-chip   | QSPI flash                          |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| SENSOR    | off-chip   | fxos8700 polling;                   |
-|           |            | fxos8700 trigger                    |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| FTFA      | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-| PIT       | on-chip    | pit                                 |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/frdm_k82f/frdm_k82f_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   For additional features not yet supported, please also refer to the
+   :zephyr:board:`frdm_k64f`, which is the superset board in NXP's Kinetis K series.
+   NXP prioritizes enabling the superset board with NXP's Full Platform Support for
+   Zephyr.  Therefore, the frdm_k64f board may have additional features
+   already supported, which can also be re-used on this frdm_k82f board.
 
 System Clock
 ============
@@ -127,6 +83,8 @@ Only USB device function is supported in Zephyr at the moment.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -220,6 +178,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx *****
    Hello World! frdm_k82f
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _FRDM-K82F Website:
    https://www.nxp.com/design/development-boards/freedom-development-boards/mcu-boards/freedom-development-platform-for-kinetis-k82-k81-and-k80-mcus:FRDM-K82F
 
diff --git a/boards/nxp/frdm_k82f/frdm_k82f.yaml b/boards/nxp/frdm_k82f/frdm_k82f.yaml
index 2a4c29652cb..1ca2c1ed3eb 100644
--- a/boards/nxp/frdm_k82f/frdm_k82f.yaml
+++ b/boards/nxp/frdm_k82f/frdm_k82f.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 192
 flash: 256
 supported:
diff --git a/boards/nxp/frdm_ke15z/doc/index.rst b/boards/nxp/frdm_ke15z/doc/index.rst
index c8d155be6fb..fceb5e8eee1 100644
--- a/boards/nxp/frdm_ke15z/doc/index.rst
+++ b/boards/nxp/frdm_ke15z/doc/index.rst
@@ -32,26 +32,7 @@ these NXP reference documents:
 Supported Features
 ==================
 
-The frdm_ke15z board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | uart polling;                       |
-|           |            | uart interrupt                      |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/nxp/frdm_ke15z/frdm_ke15z_defconfig`.
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 System Clock
 ============
@@ -66,6 +47,8 @@ The KE15 SoC has three UARTs. UART1 is configured for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -155,6 +138,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS v3.6.0-xxx-gxxxxxxxxxxxx *****
    Hello World! frdm_ke15z
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _KE1XZ SoC Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/ke-series-arm-cortex-m4-m0-plus/ke1xz-arm-cortex-m0-plus-5v-main-stream-mcu-with-nxp-touch-and-can-control:KE1xZ
 
diff --git a/boards/nxp/frdm_ke15z/frdm_ke15z.yaml b/boards/nxp/frdm_ke15z/frdm_ke15z.yaml
index bb9212fc7b5..c7296fc12ea 100644
--- a/boards/nxp/frdm_ke15z/frdm_ke15z.yaml
+++ b/boards/nxp/frdm_ke15z/frdm_ke15z.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 flash: 256
 ram: 24
 supported:
diff --git a/boards/nxp/frdm_ke17z/doc/index.rst b/boards/nxp/frdm_ke17z/doc/index.rst
index 3f9f7aa3049..61dc98249b2 100644
--- a/boards/nxp/frdm_ke17z/doc/index.rst
+++ b/boards/nxp/frdm_ke17z/doc/index.rst
@@ -34,43 +34,7 @@ these NXP reference documents:
 Supported Features
 ==================
 
-The frdm_ke17z board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINCTRL   | on-chip    | pinctrl                             |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| LPTMR     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | uart                                |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma                                 |
-+-----------+------------+-------------------------------------+
-| FTM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| ACMP      | on-chip    | sensor                              |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/nxp/frdm_ke17z/frdm_ke17z_defconfig`.
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 System Clock
 ============
@@ -85,6 +49,8 @@ The KE17Z SoC has three UARTs. UART0 is configured for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -180,6 +146,9 @@ should see the following message in the terminal:
    *** Booting Zephyr OS build xxxxxxxxxxxx ***
    Hello World! frdm_ke17z/mke17z7
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _FRDM-KE17Z Website:
    https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/freedom-development-platform-for-72mhz-ke17z-ke13z-ke12z-mcus:FRDM-KE17Z
 
diff --git a/boards/nxp/frdm_ke17z/frdm_ke17z.yaml b/boards/nxp/frdm_ke17z/frdm_ke17z.yaml
index 17ccc33e871..cf4b8c2b0be 100644
--- a/boards/nxp/frdm_ke17z/frdm_ke17z.yaml
+++ b/boards/nxp/frdm_ke17z/frdm_ke17z.yaml
@@ -7,7 +7,6 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - counter
diff --git a/boards/nxp/frdm_ke17z512/doc/index.rst b/boards/nxp/frdm_ke17z512/doc/index.rst
index 09ac1d95c67..09253e01ab4 100644
--- a/boards/nxp/frdm_ke17z512/doc/index.rst
+++ b/boards/nxp/frdm_ke17z512/doc/index.rst
@@ -35,44 +35,7 @@ these NXP reference documents:
 Supported Features
 ==================
 
-The frdm_ke17z512 board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| LPTMR     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | uart polling;                       |
-|           |            | uart interrupt                      |
-+-----------+------------+-------------------------------------+
-| FTM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | I2C                                 |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| ACMP      | on-chip    | sensor                              |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-``boards/nxp/frdm_ke17z512/frdm_ke17z512_defconfig``.
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 System Clock
 ============
@@ -87,6 +50,8 @@ The KE17Z9 SoC has three LPUARTs. UART2 is configured for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -176,6 +141,9 @@ should see the following message in the terminal:
    *** Booting Zephyr OS build v3.6.0-xxxx-gxxxxxxxxxxxx ***
    Hello World! frdm_ke17z512/mke17z9
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _FRDM-KE17Z512 Website:
    https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/frdm-development-board-for-96-mhz-ke17z-ke13z-ke12z-with-512-kb-flash-mcus:FRDM-KE17Z512
 
diff --git a/boards/nxp/frdm_ke17z512/frdm_ke17z512.yaml b/boards/nxp/frdm_ke17z512/frdm_ke17z512.yaml
index 3b9dae0fa6b..9f19b417ed3 100644
--- a/boards/nxp/frdm_ke17z512/frdm_ke17z512.yaml
+++ b/boards/nxp/frdm_ke17z512/frdm_ke17z512.yaml
@@ -13,7 +13,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - gpio
diff --git a/boards/nxp/frdm_kl25z/doc/index.rst b/boards/nxp/frdm_kl25z/doc/index.rst
index 134f577ce1e..c0bab35ead0 100644
--- a/boards/nxp/frdm_kl25z/doc/index.rst
+++ b/boards/nxp/frdm_kl25z/doc/index.rst
@@ -30,35 +30,7 @@ For more information about the KL25Z SoC and FRDM-KL25Z board:
 Supported Features
 ==================
 
-The frdm_kl25z board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | soc flash                           |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/frdm_kl25z/frdm_kl25z_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -108,6 +80,8 @@ Only USB device function is supported in Zephyr at the moment.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -214,6 +188,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS v1.14.0-rc1 *****
    Hello World! frdm_kl25z
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _FRDM-KL25Z Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/l-seriesultra-low-powerm0-plus/freedom-development-platform-for-kinetis-kl14-kl15-kl24-kl25-mcus:FRDM-KL25Z
 
diff --git a/boards/nxp/frdm_kl25z/frdm_kl25z.yaml b/boards/nxp/frdm_kl25z/frdm_kl25z.yaml
index 79c0082e156..de25dbba937 100644
--- a/boards/nxp/frdm_kl25z/frdm_kl25z.yaml
+++ b/boards/nxp/frdm_kl25z/frdm_kl25z.yaml
@@ -7,7 +7,6 @@ flash: 128
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 testing:
   ignore_tags:
     - net
diff --git a/boards/nxp/frdm_kw41z/doc/index.rst b/boards/nxp/frdm_kw41z/doc/index.rst
index 20b83687106..fe7f65999cc 100644
--- a/boards/nxp/frdm_kw41z/doc/index.rst
+++ b/boards/nxp/frdm_kw41z/doc/index.rst
@@ -45,46 +45,7 @@ For more information about the KW41Z SoC and FRDM-KW41Z board:
 Supported Features
 ==================
 
-The frdm_kw41z board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | soc flash                           |
-+-----------+------------+-------------------------------------+
-| SENSOR    | off-chip   | fxos8700 polling:                   |
-|           |            | fxos8700 trigger                    |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | tpm                                 |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| FTFA      | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/frdm_kw41z/frdm_kw41z_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -138,6 +99,8 @@ The KW41Z SoC has one UART, which is used for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -227,6 +190,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS v1.14.0-rc1 *****
    Hello World! frdm_kw41z
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _FRDM-KW41Z Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/w-serieswireless-conn.m0-plus-m4/freedom-development-kit-for-kinetis-kw41z-31z-21z-mcus:FRDM-KW41Z
 
diff --git a/boards/nxp/frdm_kw41z/frdm_kw41z.yaml b/boards/nxp/frdm_kw41z/frdm_kw41z.yaml
index 9855726bc16..1697439dffb 100644
--- a/boards/nxp/frdm_kw41z/frdm_kw41z.yaml
+++ b/boards/nxp/frdm_kw41z/frdm_kw41z.yaml
@@ -7,7 +7,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - arduino_gpio
diff --git a/boards/nxp/frdm_mcxa153/CMakeLists.txt b/boards/nxp/frdm_mcxa153/CMakeLists.txt
new file mode 100644
index 00000000000..c06b9273965
--- /dev/null
+++ b/boards/nxp/frdm_mcxa153/CMakeLists.txt
@@ -0,0 +1,8 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library()
+zephyr_library_sources(board.c)
diff --git a/boards/nxp/frdm_mcxa153/Kconfig b/boards/nxp/frdm_mcxa153/Kconfig
new file mode 100644
index 00000000000..4fdb500ab32
--- /dev/null
+++ b/boards/nxp/frdm_mcxa153/Kconfig
@@ -0,0 +1,5 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FRDM_MCXA153
+	select BOARD_EARLY_INIT_HOOK
diff --git a/boards/nxp/frdm_mcxa153/Kconfig.frdm_mcxa153 b/boards/nxp/frdm_mcxa153/Kconfig.frdm_mcxa153
new file mode 100644
index 00000000000..f9747b70d32
--- /dev/null
+++ b/boards/nxp/frdm_mcxa153/Kconfig.frdm_mcxa153
@@ -0,0 +1,6 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FRDM_MCXA153
+	select SOC_MCXA153 if BOARD_FRDM_MCXA153
+	select SOC_PART_NUMBER_MCXA153VLH
diff --git a/boards/nxp/frdm_mcxa153/board.c b/boards/nxp/frdm_mcxa153/board.c
new file mode 100644
index 00000000000..b6ededcb572
--- /dev/null
+++ b/boards/nxp/frdm_mcxa153/board.c
@@ -0,0 +1,126 @@
+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/init.h>
+#include <zephyr/device.h>
+#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
+#include <fsl_clock.h>
+#include <fsl_spc.h>
+#include <soc.h>
+
+/* Core clock frequency: 96MHz */
+#define CLOCK_INIT_CORE_CLOCK            960000000U
+#define BOARD_BOOTCLOCKFRO96M_CORE_CLOCK 960000000U
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+void board_early_init_hook(void)
+{
+	uint32_t coreFreq;
+	spc_active_mode_core_ldo_option_t ldoOption;
+	spc_sram_voltage_config_t sramOption;
+
+	/* Get the CPU Core frequency */
+	coreFreq = CLOCK_GetCoreSysClkFreq();
+
+	/* The flow of increasing voltage and frequency */
+	if (coreFreq <= BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
+		/* Set the LDO_CORE VDD regulator level */
+		ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+		ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+		(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+		/* Configure Flash to support different voltage level and frequency */
+		FMU0->FCTRL =
+			(FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
+		/* Specifies the operating voltage for the SRAM's read/write timing margin */
+		sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+		sramOption.requestVoltageUpdate = true;
+		(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+	}
+
+	CLOCK_SetupFROHFClocking(CLOCK_INIT_CORE_CLOCK); /*!< Enable FRO HF(96MHz) output */
+
+	CLOCK_SetupFRO12MClocking(); /*!< Setup FRO12M clock */
+
+	CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to FRO_HF */
+
+	/* The flow of decreasing voltage and frequency */
+	if (coreFreq > BOARD_BOOTCLOCKFRO96M_CORE_CLOCK) {
+		/* Configure Flash to support different voltage level and frequency */
+		FMU0->FCTRL =
+			(FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x2U));
+		/* Specifies the operating voltage for the SRAM's read/write timing margin */
+		sramOption.operateVoltage = kSPC_sramOperateAt1P1V;
+		sramOption.requestVoltageUpdate = true;
+		(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+		/* Set the LDO_CORE VDD regulator level */
+		ldoOption.CoreLDOVoltage = kSPC_CoreLDO_NormalVoltage;
+		ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+		(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+	}
+
+	/*!< Set up clock selectors - Attach clocks to the peripheries */
+
+	/*!< Set up dividers */
+	CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U);     /* !< Set AHBCLKDIV divider to value 1 */
+	CLOCK_SetClockDiv(kCLOCK_DivFRO_HF_DIV, 1U); /* !< Set FROHFDIV divider to value 1 */
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(edma0))
+	RESET_ReleasePeripheralReset(kDMA_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0))
+	RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1))
+	RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2))
+	RESET_ReleasePeripheralReset(kGPIO2_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO2);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3))
+	RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO3);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+	CLOCK_AttachClk(kFRO12M_to_LPUART0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART1, 1u);
+	CLOCK_AttachClk(kFRO12M_to_LPUART1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart2))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART2, 1u);
+	CLOCK_AttachClk(kFRO12M_to_LPUART2);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porta))
+	RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portb))
+	RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portc))
+	RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portd))
+	RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
+#endif
+
+	/* Set SystemCoreClock variable. */
+	SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
+}
diff --git a/boards/nxp/frdm_mcxa153/board.cmake b/boards/nxp/frdm_mcxa153/board.cmake
new file mode 100644
index 00000000000..ca3da9f8289
--- /dev/null
+++ b/boards/nxp/frdm_mcxa153/board.cmake
@@ -0,0 +1,13 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+board_runner_args(jlink "--device=MCXA153")
+board_runner_args(linkserver "--device=MCXA153:FRDM-MCXA153")
+board_runner_args(pyocd "--target=mcxA153")
+
+include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
diff --git a/boards/nxp/frdm_mcxa153/board.yml b/boards/nxp/frdm_mcxa153/board.yml
new file mode 100644
index 00000000000..6a2fb603b3d
--- /dev/null
+++ b/boards/nxp/frdm_mcxa153/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: frdm_mcxa153
+  full_name: FRDM-MCXA153
+  vendor: nxp
+  socs:
+  - name: mcxa153
diff --git a/boards/nxp/frdm_mcxa153/doc/frdm_mcxa153.webp b/boards/nxp/frdm_mcxa153/doc/frdm_mcxa153.webp
new file mode 100644
index 00000000000..715ddf843eb
Binary files /dev/null and b/boards/nxp/frdm_mcxa153/doc/frdm_mcxa153.webp differ
diff --git a/boards/nxp/frdm_mcxa153/doc/index.rst b/boards/nxp/frdm_mcxa153/doc/index.rst
new file mode 100644
index 00000000000..13105e605f9
--- /dev/null
+++ b/boards/nxp/frdm_mcxa153/doc/index.rst
@@ -0,0 +1,181 @@
+.. zephyr:board:: frdm_mcxa153
+
+Overview
+********
+
+FRDM-MCXA153 are compact and scalable development boards for rapid prototyping of
+MCX A14x and A15x MCUs. They offer industry standard headers for easy access
+to the MCU's I/Os, integrated open-standard serial interfaces, external flash
+memory and an on-board MCU-Link debugger. Additional tools like NXP's Expansion
+Board Hub for add-on boards and the Application Code Hub for software examples
+are available through the MCUXpresso Developer Experience.
+
+Hardware
+********
+
+- MCX-A153 Arm Cortex-M33 microcontroller running at 96 MHz
+- 128KB dual-bank on chip Flash
+- 32 KB RAM
+- USB full-speed with on-chip FS PHY. USB Type-C connectors
+- 1x I3C
+- On-board MCU-Link debugger with CMSIS-DAP
+- Arduino Header, mikroBUS
+
+For more information about the MCX-A153 SoC and FRDM-MCXA153 board, see:
+
+- `MCX-A153 SoC Website`_
+- `MCX-A153 Datasheet`_
+- `MCX-A153 Reference Manual`_
+- `FRDM-MCXA153 Website`_
+- `FRDM-MCXA153 User Guide`_
+- `FRDM-MCXA153 Board User Manual`_
+- `FRDM-MCXA153 Schematics`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+The MCX-A153 SoC has 4 gpio controllers and has pinmux registers which
+can be used to configure the functionality of a pin.
+
++------------+-----------------+----------------------------+
+| Name       | Function        | Usage                      |
++============+=================+============================+
+| PIO0_2     | UART            | UART RX                    |
++------------+-----------------+----------------------------+
+| PIO0_3     | UART            | UART TX                    |
++------------+-----------------+----------------------------+
+
+System Clock
+============
+
+The MCX-A153 SoC is configured to use FRO running at 96MHz as a source for
+the system clock.
+
+Serial Port
+===========
+
+The FRDM-MCXA153 SoC has 3 LPUART interfaces for serial communication.
+LPUART 0 is configured as UART for the console.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Configuring a Debug Probe
+=========================
+
+A debug probe is used for both flashing and debugging the board. This board is
+configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
+
+Using LinkServer
+----------------
+
+Linkserver is the default runner for this board, and supports the factory
+default MCU-Link firmware. Follow the instructions in
+:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link
+firmware. This only needs to be done if the default onboard debug circuit
+firmware was changed. To put the board in ``ISP mode`` to program the firmware,
+short jumper JP8.
+
+Using J-Link
+------------
+
+There are two options. The onboard debug circuit can be updated with Segger
+J-Link firmware by following the instructions in
+:ref:`mcu-link-jlink-onboard-debug-probe`.
+To be able to program the firmware, you need to put the board in ``ISP mode``
+by shorting the jumper JP8.
+The second option is to attach a :ref:`jlink-external-debug-probe` to the
+10-pin SWD connector (J18) of the board. Additionally, the jumper JP20 must
+be shorted.
+For both options use the ``-r jlink`` option with west to use the jlink runner.
+
+.. code-block:: console
+
+   west flash -r jlink
+
+Configuring a Console
+=====================
+
+Connect a USB cable from your PC to J15, and use the serial terminal of your choice
+(minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Flashing
+========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: frdm_mcxa153
+   :goals: flash
+
+Open a serial terminal, reset the board (press the RESET button), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
+   Hello World! frdm_mcxa3/mcxa153
+
+Debugging
+=========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: frdm_mcxa153/mcxa153
+   :goals: debug
+
+Open a serial terminal, step through the application in your debugger, and you
+should see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
+   Hello World! frdm_mcxa153/mcxa153
+
+Troubleshooting
+===============
+
+.. include:: ../../common/segger-ecc-systemview.rst
+   :start-after: segger-ecc-systemview
+
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
+.. _MCX-A153 SoC Website:
+   https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers/mcx-a13x-14x-15x-mcus-with-arm-cortex-m33-scalable-device-options-low-power-and-intelligent-peripherals:MCX-A13X-A14X-A15X
+
+.. _MCX-A153 Datasheet:
+   https://www.nxp.com/docs/en/data-sheet/MCXAP64M96FS3.pdf
+
+.. _MCX-A153 Reference Manual:
+   https://www.nxp.com/webapp/Download?colCode=MCXAP64M96FS3RM
+
+.. _FRDM-MCXA153 Website:
+   https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-MCXA153
+
+.. _FRDM-MCXA153 User Guide:
+   https://www.nxp.com/document/guide/getting-started-with-frdm-mcxa153:GS-FRDM-MCXAXX
+
+.. _FRDM-MCXA153 Board User Manual:
+   https://www.nxp.com/docs/en/user-manual/UM12012.pdf
+
+.. _FRDM-MCXA153 Schematics:
+   https://www.nxp.com/webapp/Download?colCode=SPF-90829_A1
diff --git a/boards/nxp/frdm_mcxa153/frdm_mcxa153-pinctrl.dtsi b/boards/nxp/frdm_mcxa153/frdm_mcxa153-pinctrl.dtsi
new file mode 100644
index 00000000000..65419589b86
--- /dev/null
+++ b/boards/nxp/frdm_mcxa153/frdm_mcxa153-pinctrl.dtsi
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <nxp/mcx/MCXA153VLH-pinctrl.h>
+
+&pinctrl {
+	pinmux_flexpwm0_pwm0: pinmux_flexpwm0_pwm0 {
+		group0 {
+			pinmux = <PWM0_A0_P3_6>,
+				<PWM0_B0_P3_7>;
+			slew-rate = "fast";
+			drive-strength = "low";
+		};
+	};
+
+	pinmux_lpuart0: pinmux_lpuart0 {
+		group0 {
+			pinmux = <LPUART0_RXD_P0_2>,
+				<LPUART0_TXD_P0_3>;
+			drive-strength = "low";
+			slew-rate = "fast";
+			input-enable;
+		};
+	};
+
+	pinmux_lpuart2: pinmux_lpuart2 {
+		group0 {
+			pinmux = <LPUART2_RXD_P3_14>,
+				<LPUART2_TXD_P3_15>;
+			drive-strength = "low";
+			slew-rate = "fast";
+			input-enable;
+		};
+	};
+};
diff --git a/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts b/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts
new file mode 100644
index 00000000000..d2d96daf79e
--- /dev/null
+++ b/boards/nxp/frdm_mcxa153/frdm_mcxa153.dts
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_mcxa153.dtsi>
+#include "frdm_mcxa153-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "NXP FRDM_MCXA153 board";
+	compatible = "nxp,mcxa153", "nxp,mcx";
+
+	aliases{
+		led0 = &red_led;
+		led1 = &green_led;
+		led2 = &blue_led;
+		sw0 = &user_button_2;
+		sw1 = &user_button_3;
+		pwm-0 = &flexpwm0_pwm0;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash;
+		zephyr,flash-controller = &fmu;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,console = &lpuart0;
+		zephyr,shell-uart = &lpuart0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		red_led: led_0 {
+			gpios = <&gpio3 12 GPIO_ACTIVE_LOW>;
+			label = "Red LED";
+		};
+
+		green_led: led_1 {
+			gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
+			label = "Green LED";
+		};
+
+		blue_led: led_2 {
+			gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
+			label = "Blue LED";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		user_button_2: button_2 {
+			label = "User SW2";
+			gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		user_button_3: button_3 {
+			label = "User SW3";
+			gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+};
+
+&flash {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 DT_SIZE_K(32)>;
+			read-only;
+		};
+		slot0_partition: partition@8000 {
+			label = "image-0";
+			reg = <0x00008000 DT_SIZE_K(40)>;
+		};
+		slot1_partition: partition@12000 {
+			label = "image-1";
+			reg = <0x00012000 DT_SIZE_K(40)>;
+		};
+		storage_partition: partition@1C000 {
+			label = "storage";
+			reg = <0x0001C000 DT_SIZE_K(16)>;
+		};
+	};
+};
+
+&flexpwm0_pwm0 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_flexpwm0_pwm0>;
+	pinctrl-names = "default";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&lpuart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&pinmux_lpuart0>;
+	pinctrl-names = "default";
+};
diff --git a/boards/nxp/frdm_mcxa153/frdm_mcxa153.yaml b/boards/nxp/frdm_mcxa153/frdm_mcxa153.yaml
new file mode 100644
index 00000000000..ae838f08d70
--- /dev/null
+++ b/boards/nxp/frdm_mcxa153/frdm_mcxa153.yaml
@@ -0,0 +1,22 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: frdm_mcxa153
+name: NXP FRDM MCXA153
+type: mcu
+arch: arm
+ram: 24
+flash: 128
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - dma
+  - flash
+  - gpio
+  - pwm
+  - uart
+vendor: nxp
diff --git a/boards/nxp/frdm_mcxa153/frdm_mcxa153_defconfig b/boards/nxp/frdm_mcxa153/frdm_mcxa153_defconfig
new file mode 100644
index 00000000000..a630917318f
--- /dev/null
+++ b/boards/nxp/frdm_mcxa153/frdm_mcxa153_defconfig
@@ -0,0 +1,11 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_GPIO=y
diff --git a/boards/nxp/frdm_mcxa156/Kconfig b/boards/nxp/frdm_mcxa156/Kconfig
index 23271bc179f..f71a70e94ea 100644
--- a/boards/nxp/frdm_mcxa156/Kconfig
+++ b/boards/nxp/frdm_mcxa156/Kconfig
@@ -1,8 +1,5 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-config BOARD_INIT_PRIORITY
-	int "Board initialization priority"
-	default 1
-	help
-	  Board initialization priority.
+config BOARD_FRDM_MCXA156
+	select BOARD_EARLY_INIT_HOOK
diff --git a/boards/nxp/frdm_mcxa156/board.c b/boards/nxp/frdm_mcxa156/board.c
index f73cbb9c8c6..6a479bf3086 100644
--- a/boards/nxp/frdm_mcxa156/board.c
+++ b/boards/nxp/frdm_mcxa156/board.c
@@ -15,7 +15,7 @@
 /* System clock frequency. */
 extern uint32_t SystemCoreClock;
 
-static int frdm_mcxa156_init(void)
+void board_early_init_hook(void)
 {
 	uint32_t coreFreq;
 	spc_active_mode_core_ldo_option_t ldoOption;
@@ -165,6 +165,12 @@ static int frdm_mcxa156_init(void)
 	CLOCK_AttachClk(kFRO_HF_to_FLEXIO0);
 #endif
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i3c0))
+	/* Attach FRO_HF_DIV clock to I3C, 96MHz / 4 = 24MHz. */
+	CLOCK_SetClockDiv(kCLOCK_DivI3C0_FCLK, 4U);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_I3C0FCLK);
+#endif
+
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc0))
 	CLOCK_SetClockDiv(kCLOCK_DivADC0, 1u);
 	CLOCK_AttachClk(kFRO12M_to_ADC0);
@@ -198,6 +204,18 @@ static int frdm_mcxa156_init(void)
 	CLOCK_AttachClk(kFRO12M_to_LPI2C3);
 #endif
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi0))
+	/* Configure input clock to be able to reach the datasheet specified band rate. */
+	CLOCK_SetClockDiv(kCLOCK_DivLPSPI0, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi1))
+	/* Configure input clock to be able to reach the datasheet specified band rate. */
+	CLOCK_SetClockDiv(kCLOCK_DivLPSPI1, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_LPSPI1);
+#endif
+
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptmr0))
 
 /*
@@ -228,8 +246,4 @@ static int frdm_mcxa156_init(void)
 
 	/* Set SystemCoreClock variable. */
 	SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
-
-	return 0;
 }
-
-SYS_INIT(frdm_mcxa156_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);
diff --git a/boards/nxp/frdm_mcxa156/doc/index.rst b/boards/nxp/frdm_mcxa156/doc/index.rst
index 0bcc9d6e9ee..01bcd2dbf5e 100644
--- a/boards/nxp/frdm_mcxa156/doc/index.rst
+++ b/boards/nxp/frdm_mcxa156/doc/index.rst
@@ -34,61 +34,7 @@ For more information about the MCX-A156 SoC and FRDM-MCXA156 board, see:
 Supported Features
 ==================
 
-The FRDM-MCXA156 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | soc flash                           |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| CTIMER    | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | dac                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma                                 |
-+-----------+------------+-------------------------------------+
-| FLEXCAN   | on-chip    | CAN                                 |
-+-----------+------------+-------------------------------------+
-| FLEXIO    | on-chip    | flexio                              |
-+-----------+------------+-------------------------------------+
-| DISPLAY   | on-chip    | flexio; MIPI-DBI. Tested with       |
-|           |            | :ref:`lcd_par_s035`                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| LPCMP     | on-chip    | sensor(comparator)                  |
-+-----------+------------+-------------------------------------+
-| LPTMR     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-
-Targets available
-==================
-
-The default configuration file
-:zephyr_file:`boards/nxp/frdm_mcxa156/frdm_mcxa156_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -119,6 +65,8 @@ LPUART 0 is configured as UART for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -208,6 +156,9 @@ Troubleshooting
 .. include:: ../../common/segger-ecc-systemview.rst
    :start-after: segger-ecc-systemview
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _MCX-A156 SoC Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers/mcx-a13x-14x-15x-mcus-with-arm-cortex-m33-scalable-device-options-low-power-and-intelligent-peripherals:MCX-A13X-A14X-A15X
 
diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156-pinctrl.dtsi b/boards/nxp/frdm_mcxa156/frdm_mcxa156-pinctrl.dtsi
index 7fa90600ee2..319d698ba7d 100644
--- a/boards/nxp/frdm_mcxa156/frdm_mcxa156-pinctrl.dtsi
+++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156-pinctrl.dtsi
@@ -89,6 +89,22 @@
 			drive-strength = "low";
 		};
 	};
+	pinmux_i3c0: pinmux_i3c0 {
+		group0 {
+			pinmux = <I3C0_SDA_P0_16>,
+				<I3C0_SCL_P0_17>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+			bias-pull-up;
+		};
+		group1 {
+			pinmux = <I3C0_PUR_P1_11>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
 	pinmux_lpadc0: pinmux_lpadc0 {
 		group0 {
 			pinmux = <ADC0_A0_P2_0>,
@@ -138,4 +154,15 @@
 			drive-open-drain;
 		};
 	};
+	pinmux_lpspi0: pinmux_lpspi0 {
+		group0 {
+			pinmux = <LPSPI0_SDO_P1_0>,
+				 <LPSPI0_SCK_P1_1>,
+				 <LPSPI0_SDI_P1_2>,
+				 <LPSPI0_PCS0_P1_3>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
 };
diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts b/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts
index 7aef98641a1..50698489641 100644
--- a/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts
+++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156.dts
@@ -9,6 +9,7 @@
 #include <nxp/nxp_mcxa156.dtsi>
 #include "frdm_mcxa156-pinctrl.dtsi"
 #include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <freq.h>
 
 / {
 	model = "NXP FRDM_MCXA156 board";
@@ -23,6 +24,7 @@
 		pwm-0 = &flexpwm0_pwm0;
 		mcuboot-button0 = &user_button_2;
 		watchdog0 = &wwdt0;
+		ambient-temp0 = &p3t1755;
 	};
 
 	chosen {
@@ -165,6 +167,22 @@ zephyr_mipi_dbi_parallel: &flexio0_lcd {
 	pinctrl-names = "default";
 };
 
+&i3c0 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_i3c0>;
+	pinctrl-names = "default";
+
+	i2c-scl-hz = <DT_FREQ_K(400)>;
+	i3c-scl-hz = <DT_FREQ_M(4)>;
+	i3c-od-scl-hz = <DT_FREQ_K(1500)>;
+
+	p3t1755: p3t1755@4800000236152a0090 {
+		compatible = "nxp,p3t1755";
+		reg = <0x48 0x0236 0x152a0090>;
+		status = "okay";
+	};
+};
+
 &lpadc0 {
 	status = "okay";
 	pinctrl-0 = <&pinmux_lpadc0>;
@@ -189,6 +207,12 @@ zephyr_mipi_dbi_parallel: &flexio0_lcd {
 	pinctrl-names = "default";
 };
 
+&lpspi0 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_lpspi0>;
+	pinctrl-names = "default";
+};
+
 &lptmr0 {
 	status = "okay";
 };
diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156.yaml b/boards/nxp/frdm_mcxa156/frdm_mcxa156.yaml
index 2a3960c25eb..df74238b2fa 100644
--- a/boards/nxp/frdm_mcxa156/frdm_mcxa156.yaml
+++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156.yaml
@@ -13,7 +13,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - flash
@@ -23,7 +22,9 @@ supported:
   - dac
   - dma
   - i2c
+  - i3c
   - pwm
+  - spi
   - usb_device
   - usbd
   - watchdog
diff --git a/boards/nxp/frdm_mcxa156/frdm_mcxa156_defconfig b/boards/nxp/frdm_mcxa156/frdm_mcxa156_defconfig
index 8a733179c9f..cff11a6ec9e 100644
--- a/boards/nxp/frdm_mcxa156/frdm_mcxa156_defconfig
+++ b/boards/nxp/frdm_mcxa156/frdm_mcxa156_defconfig
@@ -9,3 +9,5 @@ CONFIG_UART_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
 CONFIG_GPIO=y
+CONFIG_LPADC_DO_OFFSET_CALIBRATION=y
+CONFIG_TEST_RANDOM_GENERATOR=y
diff --git a/boards/nxp/frdm_mcxa166/CMakeLists.txt b/boards/nxp/frdm_mcxa166/CMakeLists.txt
new file mode 100644
index 00000000000..c06b9273965
--- /dev/null
+++ b/boards/nxp/frdm_mcxa166/CMakeLists.txt
@@ -0,0 +1,8 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library()
+zephyr_library_sources(board.c)
diff --git a/boards/nxp/frdm_mcxa166/Kconfig b/boards/nxp/frdm_mcxa166/Kconfig
new file mode 100644
index 00000000000..64334d8cb82
--- /dev/null
+++ b/boards/nxp/frdm_mcxa166/Kconfig
@@ -0,0 +1,5 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FRDM_MCXA166
+	select BOARD_EARLY_INIT_HOOK
diff --git a/boards/nxp/frdm_mcxa166/Kconfig.frdm_mcxa166 b/boards/nxp/frdm_mcxa166/Kconfig.frdm_mcxa166
new file mode 100644
index 00000000000..442f61f27c6
--- /dev/null
+++ b/boards/nxp/frdm_mcxa166/Kconfig.frdm_mcxa166
@@ -0,0 +1,6 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FRDM_MCXA166
+	select SOC_MCXA166
+	select SOC_PART_NUMBER_MCXA166VLQ
diff --git a/boards/nxp/frdm_mcxa166/board.c b/boards/nxp/frdm_mcxa166/board.c
new file mode 100644
index 00000000000..1c0ffff6c07
--- /dev/null
+++ b/boards/nxp/frdm_mcxa166/board.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright 2024-2025  NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/init.h>
+#include <zephyr/device.h>
+#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
+#include <fsl_clock.h>
+#include <fsl_spc.h>
+#include <soc.h>
+
+/* Core clock frequency: 180MHz */
+#define CLOCK_INIT_CORE_CLOCK               180000000U
+#define BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK 180000000U
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+void board_early_init_hook(void)
+{
+	uint32_t coreFreq;
+	spc_active_mode_core_ldo_option_t ldoOption;
+	spc_sram_voltage_config_t sramOption;
+
+	/* Get the CPU Core frequency */
+	coreFreq = CLOCK_GetCoreSysClkFreq();
+
+	/* The flow of increasing voltage and frequency */
+	if (coreFreq <= BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK) {
+		/* Set the LDO_CORE VDD regulator level */
+		ldoOption.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage;
+		ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+		(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+		/* Configure Flash to support different voltage level and frequency */
+		FMU0->FCTRL =
+			(FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x4U));
+		/* Specifies the operating voltage for the SRAM's read/write timing margin */
+		sramOption.operateVoltage = kSPC_sramOperateAt1P2V;
+		sramOption.requestVoltageUpdate = true;
+		(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+	}
+
+	/*!< Set up system dividers */
+	CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set SYSCON.AHBCLKDIV divider to value 1 */
+	CLOCK_SetClockDiv(kCLOCK_DivFRO_HF, 1U); /* !< Set SYSCON.FROHFDIV divider to value 1 */
+	CLOCK_SetupFROHFClocking(BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK); /*!< Enable FRO HF */
+	CLOCK_SetupFRO12MClocking();             /*!< Setup FRO12M clock */
+
+	CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to kFRO_HF */
+
+	/* The flow of decreasing voltage and frequency */
+	if (coreFreq > BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK) {
+		/* Configure Flash to support different voltage level and frequency */
+		FMU0->FCTRL =
+			(FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x4U));
+		/* Specifies the operating voltage for the SRAM's read/write timing margin */
+		sramOption.operateVoltage = kSPC_sramOperateAt1P2V;
+		sramOption.requestVoltageUpdate = true;
+		(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+		/* Set the LDO_CORE VDD regulator level */
+		ldoOption.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage;
+		ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+		(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+	}
+
+	/*!< Set up clock selectors - Attach clocks to the peripheries */
+	CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
+
+	/*!< Set up dividers */
+	CLOCK_SetClockDiv(kCLOCK_DivFRO_LF, 1U); /* !< Set SYSCON.FROLFDIV divider to value 1 */
+	CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U);  /* !< Set MRCC.WWDT0_CLKDIV divider to value 1 */
+	CLOCK_SetClockDiv(kCLOCK_DivTRACE, 2U);  /* !< Set MRCC.TRACE_CLKDIV divider to value 2 */
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porta))
+	RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GatePORT0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portb))
+	RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GatePORT1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portc))
+	RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GatePORT2);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portd))
+	RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GatePORT3);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porte))
+	RESET_ReleasePeripheralReset(kPORT4_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GatePORT4);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0))
+	RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1))
+	RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2))
+	RESET_ReleasePeripheralReset(kGPIO2_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO2);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3))
+	RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO3);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio4))
+	RESET_ReleasePeripheralReset(kGPIO4_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO4);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+	CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART0);
+	RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART1, 1u);
+	CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART1);
+	RESET_ReleasePeripheralReset(kLPUART1_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart2))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART2, 1u);
+	CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART2);
+	RESET_ReleasePeripheralReset(kLPUART2_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart3))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART3, 1u);
+	CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART3);
+	RESET_ReleasePeripheralReset(kLPUART3_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart4))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART4, 1u);
+	CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART4);
+	RESET_ReleasePeripheralReset(kLPUART4_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(edma0))
+	RESET_ReleasePeripheralReset(kDMA0_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wwdt0))
+	CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1u);
+#endif
+
+	/* Set SystemCoreClock variable. */
+	SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
+}
diff --git a/boards/nxp/frdm_mcxa166/board.cmake b/boards/nxp/frdm_mcxa166/board.cmake
new file mode 100644
index 00000000000..f82d580a841
--- /dev/null
+++ b/boards/nxp/frdm_mcxa166/board.cmake
@@ -0,0 +1,13 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+board_runner_args(jlink "--device=MCXA166")
+board_runner_args(linkserver "--device=MCXA166:FRDM-MCXA166")
+board_runner_args(pyocd "--target=mcxA166")
+
+include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
diff --git a/boards/nxp/frdm_mcxa166/board.yml b/boards/nxp/frdm_mcxa166/board.yml
new file mode 100644
index 00000000000..5a1b42e98c1
--- /dev/null
+++ b/boards/nxp/frdm_mcxa166/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: frdm_mcxa166
+  full_name: FRDM-MCXA166
+  vendor: nxp
+  socs:
+  - name: mcxa166
diff --git a/boards/nxp/frdm_mcxa166/doc/frdm_mcxa166.webp b/boards/nxp/frdm_mcxa166/doc/frdm_mcxa166.webp
new file mode 100644
index 00000000000..0c6808e3f8e
Binary files /dev/null and b/boards/nxp/frdm_mcxa166/doc/frdm_mcxa166.webp differ
diff --git a/boards/nxp/frdm_mcxa166/doc/index.rst b/boards/nxp/frdm_mcxa166/doc/index.rst
new file mode 100644
index 00000000000..16f0245349f
--- /dev/null
+++ b/boards/nxp/frdm_mcxa166/doc/index.rst
@@ -0,0 +1,178 @@
+.. zephyr:board:: frdm_mcxa166
+
+Overview
+********
+
+FRDM-MCXA166 are compact and scalable development boards for rapid prototyping of
+MCX A16X MCUs. They offer industry standard headers for easy access to the MCUs I/Os,
+integrated open-standard serial interfaces and an on-board MCU-Link debugger.
+MCX A Series are high-performance, low-power microcontrollers with MAU,SmartDMA and performance efficiency.
+
+Hardware
+********
+
+- MCX-A166 Arm Cortex-M33 microcontroller running at 180 MHz
+- 1MB dual-bank on chip Flash
+- 256 KB RAM
+- 1x FlexCAN with FD, 1x RGB LED, 3x SW buttons
+- On-board MCU-Link debugger with CMSIS-DAP
+- Arduino Header, SmartDMA/Camera Header, mikroBUS
+
+For more information about the MCX-A166 SoC and FRDM-MCXA166 board, see:
+
+- `MCX-A166 SoC Website`_
+- `MCX-A166 Datasheet`_
+- `MCX-A166 Reference Manual`_
+- `FRDM-MCXA166 Website`_
+- `FRDM-MCXA166 User Guide`_
+- `FRDM-MCXA166 Board User Manual`_
+- `FRDM-MCXA166 Schematics`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+The MCX-A166 SoC has 6 gpio controllers and has pinmux registers which
+can be used to configure the functionality of a pin.
+
++------------+-----------------+----------------------------+
+| Name       | Function        | Usage                      |
++============+=================+============================+
+| PIO2_3     | UART            | UART RX                    |
++------------+-----------------+----------------------------+
+| PIO2_2     | UART            | UART TX                    |
++------------+-----------------+----------------------------+
+
+System Clock
+============
+
+The MCX-A166 SoC is configured to use FRO running at 180MHz as a source for
+the system clock.
+
+Serial Port
+===========
+
+The FRDM-MCXA166 SoC has 6 LPUART  interfaces for serial communication.
+LPUART 2 is configured as UART for the console.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Configuring a Debug Probe
+=========================
+
+A debug probe is used for both flashing and debugging the board. This board is
+configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
+
+Using LinkServer
+----------------
+
+Linkserver is the default runner for this board, and supports the factory
+default MCU-Link firmware. Follow the instructions in
+:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link
+firmware. This only needs to be done if the default onboard debug circuit
+firmware was changed. To put the board in ``ISP mode`` to program the firmware,
+short jumper JP4.
+
+Using J-Link
+------------
+
+There are two options. The onboard debug circuit can be updated with Segger
+J-Link firmware by following the instructions in
+:ref:`mcu-link-jlink-onboard-debug-probe`.
+To be able to program the firmware, you need to put the board in ``ISP mode``
+by shortening the jumper JP4.
+The second option is to attach a :ref:`jlink-external-debug-probe` to the
+10-pin SWD connector (J14) of the board. Additionally, the jumper JP6 must
+be shorted.
+For both options use the ``-r jlink`` option with west to use the jlink runner.
+
+.. code-block:: console
+
+   west flash -r jlink
+
+Configuring a Console
+=====================
+
+Connect a USB cable from your PC to J15, and use the serial terminal of your choice
+(minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Flashing
+========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: frdm_mcxa166
+   :goals: flash
+
+Open a serial terminal, reset the board (press the RESET button), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
+   Hello World! frdm_mcxa166/mcxa166
+
+Debugging
+=========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: frdm_mcxa166/mcxa166
+   :goals: debug
+
+Open a serial terminal, step through the application in your debugger, and you
+should see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
+   Hello World! frdm_mcxa166/mcxa166
+
+Troubleshooting
+===============
+
+.. include:: ../../common/segger-ecc-systemview.rst
+   :start-after: segger-ecc-systemview
+
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
+.. _MCX-A166 SoC Website:
+   https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers/mcx-a13x-14x-15x-mcus-with-arm-cortex-m33-scalable-device-options-low-power-and-intelligent-peripherals:MCX-A13X-A14X-A15X
+
+.. _MCX-A166 Datasheet:
+   https://www.nxp.com/docs/en/data-sheet/MCXAP100M96FS6.pdf
+
+.. _MCX-A166 Reference Manual:
+   https://www.nxp.com/webapp/Download?colCode=MCXAP100M96FS6RM
+
+.. _FRDM-MCXA166 Website:
+   https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/frdm-development-board-for-mcx-a144-5-6-a154-5-6-mcus:FRDM-MCXA166
+
+.. _FRDM-MCXA166 User Guide:
+   https://www.nxp.com/document/guide/getting-started-with-frdm-mcxa166:GS-FRDM-MCXA166
+
+.. _FRDM-MCXA166 Board User Manual:
+   https://www.nxp.com/docs/en/user-manual/UM12121.pdf
+
+.. _FRDM-MCXA166 Schematics:
+   https://www.nxp.com/webapp/Download?colCode=SPF-90841
diff --git a/boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi b/boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi
new file mode 100644
index 00000000000..ed6e8de8186
--- /dev/null
+++ b/boards/nxp/frdm_mcxa166/frdm_mcxa166-pinctrl.dtsi
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <nxp/mcx/MCXA166VLQ-pinctrl.h>
+
+&pinctrl {
+	pinmux_lpuart2: pinmux_lpuart2 {
+		group0 {
+			pinmux = <LPUART2_RXD_P2_3>,
+				<LPUART2_TXD_P2_2>;
+			drive-strength = "low";
+			slew-rate = "fast";
+			input-enable;
+		};
+	};
+
+	pinmux_lpuart3: pinmux_lpuart3 {
+		group0 {
+			pinmux = <LPUART3_RXD_P4_2>,
+				<LPUART3_TXD_P4_5>;
+			drive-strength = "low";
+			slew-rate = "fast";
+			input-enable;
+		};
+	};
+};
diff --git a/boards/nxp/frdm_mcxa166/frdm_mcxa166.dts b/boards/nxp/frdm_mcxa166/frdm_mcxa166.dts
new file mode 100644
index 00000000000..0305e2b5c41
--- /dev/null
+++ b/boards/nxp/frdm_mcxa166/frdm_mcxa166.dts
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_mcxa166.dtsi>
+#include "frdm_mcxa166-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "NXP FRDM_MCXA166 board";
+	compatible = "nxp,mcxa166", "nxp,mcx";
+
+	aliases{
+		led0 = &red_led;
+		led1 = &green_led;
+		led2 = &red_led;
+		sw0 = &user_button_2;
+		sw1 = &user_button_3;
+		watchdog0 = &wwdt0;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash;
+		zephyr,flash-controller = &fmu;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,console = &lpuart2;
+		zephyr,shell-uart = &lpuart2;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		red_led: led_0 {
+			gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+			label = "Red LED";
+		};
+
+		green_led: led_1 {
+			gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+			label = "Green LED";
+		};
+
+		blue_led: led_2 {
+			gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
+			label = "Blue LED";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		user_button_2: button_2 {
+			label = "User SW2";
+			gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		user_button_3: button_3 {
+			label = "User SW3";
+			gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+
+};
+
+&porta {
+	status = "okay";
+};
+
+&portb {
+	status = "okay";
+};
+
+&portc {
+	status = "okay";
+};
+
+&portd {
+	status = "okay";
+};
+
+&porte {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&lpuart2 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&pinmux_lpuart2>;
+	pinctrl-names = "default";
+};
+
+&flash {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 DT_SIZE_K(64)>;
+			read-only;
+		};
+		slot0_partition: partition@10000 {
+			label = "image-0";
+			reg = <0x00010000 DT_SIZE_K(400)>;
+		};
+		slot1_partition: partition@74000 {
+			label = "image-1";
+			reg = <0x00074000 DT_SIZE_K(400)>;
+		};
+		storage_partition: partition@d8000 {
+			label = "storage";
+			reg = <0x000d8000 DT_SIZE_K(112)>;
+		};
+	};
+};
+
+&wwdt0 {
+	status = "okay";
+};
diff --git a/boards/nxp/frdm_mcxa166/frdm_mcxa166.yaml b/boards/nxp/frdm_mcxa166/frdm_mcxa166.yaml
new file mode 100644
index 00000000000..90ed90d1117
--- /dev/null
+++ b/boards/nxp/frdm_mcxa166/frdm_mcxa166.yaml
@@ -0,0 +1,21 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: frdm_mcxa166
+name: NXP FRDM MCXA166
+type: mcu
+arch: arm
+ram: 240
+flash: 1024
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - uart
+  - flash
+  - watchdog
+vendor: nxp
diff --git a/boards/nxp/frdm_mcxa166/frdm_mcxa166_defconfig b/boards/nxp/frdm_mcxa166/frdm_mcxa166_defconfig
new file mode 100644
index 00000000000..a630917318f
--- /dev/null
+++ b/boards/nxp/frdm_mcxa166/frdm_mcxa166_defconfig
@@ -0,0 +1,11 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_GPIO=y
diff --git a/boards/nxp/frdm_mcxa276/CMakeLists.txt b/boards/nxp/frdm_mcxa276/CMakeLists.txt
new file mode 100644
index 00000000000..c06b9273965
--- /dev/null
+++ b/boards/nxp/frdm_mcxa276/CMakeLists.txt
@@ -0,0 +1,8 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library()
+zephyr_library_sources(board.c)
diff --git a/boards/nxp/frdm_mcxa276/Kconfig b/boards/nxp/frdm_mcxa276/Kconfig
new file mode 100644
index 00000000000..74b18017bc2
--- /dev/null
+++ b/boards/nxp/frdm_mcxa276/Kconfig
@@ -0,0 +1,5 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FRDM_MCXA276
+	select BOARD_EARLY_INIT_HOOK
diff --git a/boards/nxp/frdm_mcxa276/Kconfig.frdm_mcxa276 b/boards/nxp/frdm_mcxa276/Kconfig.frdm_mcxa276
new file mode 100644
index 00000000000..632f03c4d0f
--- /dev/null
+++ b/boards/nxp/frdm_mcxa276/Kconfig.frdm_mcxa276
@@ -0,0 +1,6 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FRDM_MCXA276
+	select SOC_MCXA276
+	select SOC_PART_NUMBER_MCXA276VLQ
diff --git a/boards/nxp/frdm_mcxa276/board.c b/boards/nxp/frdm_mcxa276/board.c
new file mode 100644
index 00000000000..1c0ffff6c07
--- /dev/null
+++ b/boards/nxp/frdm_mcxa276/board.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright 2024-2025  NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/init.h>
+#include <zephyr/device.h>
+#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
+#include <fsl_clock.h>
+#include <fsl_spc.h>
+#include <soc.h>
+
+/* Core clock frequency: 180MHz */
+#define CLOCK_INIT_CORE_CLOCK               180000000U
+#define BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK 180000000U
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+void board_early_init_hook(void)
+{
+	uint32_t coreFreq;
+	spc_active_mode_core_ldo_option_t ldoOption;
+	spc_sram_voltage_config_t sramOption;
+
+	/* Get the CPU Core frequency */
+	coreFreq = CLOCK_GetCoreSysClkFreq();
+
+	/* The flow of increasing voltage and frequency */
+	if (coreFreq <= BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK) {
+		/* Set the LDO_CORE VDD regulator level */
+		ldoOption.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage;
+		ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+		(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+		/* Configure Flash to support different voltage level and frequency */
+		FMU0->FCTRL =
+			(FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x4U));
+		/* Specifies the operating voltage for the SRAM's read/write timing margin */
+		sramOption.operateVoltage = kSPC_sramOperateAt1P2V;
+		sramOption.requestVoltageUpdate = true;
+		(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+	}
+
+	/*!< Set up system dividers */
+	CLOCK_SetClockDiv(kCLOCK_DivAHBCLK, 1U); /* !< Set SYSCON.AHBCLKDIV divider to value 1 */
+	CLOCK_SetClockDiv(kCLOCK_DivFRO_HF, 1U); /* !< Set SYSCON.FROHFDIV divider to value 1 */
+	CLOCK_SetupFROHFClocking(BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK); /*!< Enable FRO HF */
+	CLOCK_SetupFRO12MClocking();             /*!< Setup FRO12M clock */
+
+	CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /* !< Switch MAIN_CLK to kFRO_HF */
+
+	/* The flow of decreasing voltage and frequency */
+	if (coreFreq > BOARD_BOOTCLOCKFROHF180M_CORE_CLOCK) {
+		/* Configure Flash to support different voltage level and frequency */
+		FMU0->FCTRL =
+			(FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x4U));
+		/* Specifies the operating voltage for the SRAM's read/write timing margin */
+		sramOption.operateVoltage = kSPC_sramOperateAt1P2V;
+		sramOption.requestVoltageUpdate = true;
+		(void)SPC_SetSRAMOperateVoltage(SPC0, &sramOption);
+		/* Set the LDO_CORE VDD regulator level */
+		ldoOption.CoreLDOVoltage = kSPC_CoreLDO_OverDriveVoltage;
+		ldoOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
+		(void)SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldoOption);
+	}
+
+	/*!< Set up clock selectors - Attach clocks to the peripheries */
+	CLOCK_AttachClk(kCPU_CLK_to_TRACE); /* !< Switch TRACE to CPU_CLK */
+
+	/*!< Set up dividers */
+	CLOCK_SetClockDiv(kCLOCK_DivFRO_LF, 1U); /* !< Set SYSCON.FROLFDIV divider to value 1 */
+	CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1U);  /* !< Set MRCC.WWDT0_CLKDIV divider to value 1 */
+	CLOCK_SetClockDiv(kCLOCK_DivTRACE, 2U);  /* !< Set MRCC.TRACE_CLKDIV divider to value 2 */
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porta))
+	RESET_ReleasePeripheralReset(kPORT0_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GatePORT0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portb))
+	RESET_ReleasePeripheralReset(kPORT1_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GatePORT1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portc))
+	RESET_ReleasePeripheralReset(kPORT2_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GatePORT2);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(portd))
+	RESET_ReleasePeripheralReset(kPORT3_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GatePORT3);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(porte))
+	RESET_ReleasePeripheralReset(kPORT4_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GatePORT4);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0))
+	RESET_ReleasePeripheralReset(kGPIO0_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1))
+	RESET_ReleasePeripheralReset(kGPIO1_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2))
+	RESET_ReleasePeripheralReset(kGPIO2_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO2);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3))
+	RESET_ReleasePeripheralReset(kGPIO3_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO3);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio4))
+	RESET_ReleasePeripheralReset(kGPIO4_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_GateGPIO4);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART0, 1u);
+	CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART0);
+	RESET_ReleasePeripheralReset(kLPUART0_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART1, 1u);
+	CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART1);
+	RESET_ReleasePeripheralReset(kLPUART1_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart2))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART2, 1u);
+	CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART2);
+	RESET_ReleasePeripheralReset(kLPUART2_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart3))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART3, 1u);
+	CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART3);
+	RESET_ReleasePeripheralReset(kLPUART3_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart4))
+	CLOCK_SetClockDiv(kCLOCK_DivLPUART4, 1u);
+	CLOCK_AttachClk(kFRO_LF_DIV_to_LPUART4);
+	RESET_ReleasePeripheralReset(kLPUART4_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(edma0))
+	RESET_ReleasePeripheralReset(kDMA0_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wwdt0))
+	CLOCK_SetClockDiv(kCLOCK_DivWWDT0, 1u);
+#endif
+
+	/* Set SystemCoreClock variable. */
+	SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
+}
diff --git a/boards/nxp/frdm_mcxa276/board.cmake b/boards/nxp/frdm_mcxa276/board.cmake
new file mode 100644
index 00000000000..21bb9b2cd36
--- /dev/null
+++ b/boards/nxp/frdm_mcxa276/board.cmake
@@ -0,0 +1,13 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+board_runner_args(jlink "--device=MCXA276")
+board_runner_args(linkserver "--device=MCXA276:FRDM-MCXA276")
+board_runner_args(pyocd "--target=mcxA276")
+
+include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
diff --git a/boards/nxp/frdm_mcxa276/board.yml b/boards/nxp/frdm_mcxa276/board.yml
new file mode 100644
index 00000000000..5d06ed14347
--- /dev/null
+++ b/boards/nxp/frdm_mcxa276/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: frdm_mcxa276
+  full_name: FRDM-MCXA276
+  vendor: nxp
+  socs:
+  - name: mcxa276
diff --git a/boards/nxp/frdm_mcxa276/doc/frdm_mcxa276.webp b/boards/nxp/frdm_mcxa276/doc/frdm_mcxa276.webp
new file mode 100644
index 00000000000..34489d4c08a
Binary files /dev/null and b/boards/nxp/frdm_mcxa276/doc/frdm_mcxa276.webp differ
diff --git a/boards/nxp/frdm_mcxa276/doc/index.rst b/boards/nxp/frdm_mcxa276/doc/index.rst
new file mode 100644
index 00000000000..c176de8b82c
--- /dev/null
+++ b/boards/nxp/frdm_mcxa276/doc/index.rst
@@ -0,0 +1,181 @@
+.. zephyr:board:: frdm_mcxa276
+
+Overview
+********
+
+FRDM-MCXA276 are compact and scalable development boards for rapid prototyping of
+MCX A27X MCUs. They offer industry standard headers for easy access to the MCUs I/Os,
+integrated open-standard serial interfaces and an on-board MCU-Link debugger.
+MCX A Series are high-performance, low-power microcontrollers with MAU,SmartDMA and performance efficiency.
+
+Hardware
+********
+
+- MCX-A276 Arm Cortex-M33 microcontroller running at 180 MHz
+- 1MB dual-bank on chip Flash
+- 256 KB RAM
+- 1x FlexCAN with FD, 1x RGB LED, 3x SW buttons
+- On-board MCU-Link debugger with CMSIS-DAP
+- Arduino Header, SmartDMA/Camera Header, mikroBUS
+
+For more information about the MCX-A276 SoC and FRDM-MCXA276 board, see:
+
+- `MCX-A276 SoC Website`_
+- `MCX-A276 Datasheet`_
+- `MCX-A276 Reference Manual`_
+- `FRDM-MCXA276 Website`_
+- `FRDM-MCXA276 User Guide`_
+- `FRDM-MCXA276 Board User Manual`_
+- `FRDM-MCXA276 Schematics`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+The MCX-A276 SoC has 6 gpio controllers and has pinmux registers which
+can be used to configure the functionality of a pin.
+
++------------+-----------------+----------------------------+
+| Name       | Function        | Usage                      |
++============+=================+============================+
+| PIO2_3     | UART            | UART RX                    |
++------------+-----------------+----------------------------+
+| PIO2_2     | UART            | UART TX                    |
++------------+-----------------+----------------------------+
+
+System Clock
+============
+
+The MCX-A276 SoC is configured to use FRO running at 180MHz as a source for
+the system clock.
+
+Serial Port
+===========
+
+The FRDM-MCXA276 SoC has 6 LPUART  interfaces for serial communication.
+LPUART 2 is configured as UART for the console.
+
+Programming and Debugging
+*************************
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Configuring a Debug Probe
+=========================
+
+A debug probe is used for both flashing and debugging the board. This board is
+configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
+
+Using LinkServer
+----------------
+
+Linkserver is the default runner for this board, and supports the factory
+default MCU-Link firmware. Follow the instructions in
+:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link
+firmware. This only needs to be done if the default onboard debug circuit
+firmware was changed. To put the board in ``ISP mode`` to program the firmware,
+short jumper JP4.
+
+Using J-Link
+------------
+
+There are two options. The onboard debug circuit can be updated with Segger
+J-Link firmware by following the instructions in
+:ref:`mcu-link-jlink-onboard-debug-probe`.
+To be able to program the firmware, you need to put the board in ``ISP mode``
+by shortening the jumper JP4.
+The second option is to attach a :ref:`jlink-external-debug-probe` to the
+10-pin SWD connector (J14) of the board. Additionally, the jumper JP6 must
+be shorted.
+For both options use the ``-r jlink`` option with west to use the jlink runner.
+
+.. code-block:: console
+
+   west flash -r jlink
+
+Configuring a Console
+=====================
+
+Connect a USB cable from your PC to J15, and use the serial terminal of your choice
+(minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Programming and Debugging
+=========================
+
+.. zephyr:board-supported-runners::
+
+Flashing
+========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: frdm_mcxa276
+   :goals: flash
+
+Open a serial terminal, reset the board (press the RESET button), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
+   Hello World! frdm_mcxa276/mcxa276
+
+Debugging
+=========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: frdm_mcxa276/mcxa276
+   :goals: debug
+
+Open a serial terminal, step through the application in your debugger, and you
+should see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v3.6.0-4478-ge6c3a42f5f52 ***
+   Hello World! frdm_mcxa276/mcxa276
+
+Troubleshooting
+===============
+
+.. include:: ../../common/segger-ecc-systemview.rst
+   :start-after: segger-ecc-systemview
+
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
+.. _MCX-A276 SoC Website:
+   https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-a-series-microcontrollers/mcx-a13x-14x-15x-mcus-with-arm-cortex-m33-scalable-device-options-low-power-and-intelligent-peripherals:MCX-A13X-A14X-A15X
+
+.. _MCX-A276 Datasheet:
+   https://www.nxp.com/docs/en/data-sheet/MCXAP100M96FS6.pdf
+
+.. _MCX-A276 Reference Manual:
+   https://www.nxp.com/webapp/Download?colCode=MCXAP100M96FS6RM
+
+.. _FRDM-MCXA276 Website:
+   https://www.nxp.com/design/design-center/development-boards-and-designs/general-purpose-mcus/frdm-development-board-for-mcx-a144-5-6-a154-5-6-mcus:FRDM-MCXA276
+
+.. _FRDM-MCXA276 User Guide:
+   https://www.nxp.com/document/guide/getting-started-with-frdm-mcxa276:GS-FRDM-MCXA276
+
+.. _FRDM-MCXA276 Board User Manual:
+   https://www.nxp.com/docs/en/user-manual/UM12121.pdf
+
+.. _FRDM-MCXA276 Schematics:
+   https://www.nxp.com/webapp/Download?colCode=SPF-90841
diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi b/boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi
new file mode 100644
index 00000000000..4eb700d76b2
--- /dev/null
+++ b/boards/nxp/frdm_mcxa276/frdm_mcxa276-pinctrl.dtsi
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <nxp/mcx/MCXA276VLQ-pinctrl.h>
+
+&pinctrl {
+	pinmux_lpuart2: pinmux_lpuart2 {
+		group0 {
+			pinmux = <LPUART2_RXD_P2_3>,
+				<LPUART2_TXD_P2_2>;
+			drive-strength = "low";
+			slew-rate = "fast";
+			input-enable;
+		};
+	};
+
+	pinmux_lpuart3: pinmux_lpuart3 {
+		group0 {
+			pinmux = <LPUART3_RXD_P4_2>,
+				<LPUART3_TXD_P4_5>;
+			drive-strength = "low";
+			slew-rate = "fast";
+			input-enable;
+		};
+	};
+};
diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276.dts b/boards/nxp/frdm_mcxa276/frdm_mcxa276.dts
new file mode 100644
index 00000000000..2858f54c094
--- /dev/null
+++ b/boards/nxp/frdm_mcxa276/frdm_mcxa276.dts
@@ -0,0 +1,147 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_mcxa276.dtsi>
+#include "frdm_mcxa276-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "NXP FRDM_MCXA276 board";
+	compatible = "nxp,mcxa276", "nxp,mcx";
+
+	aliases{
+		led0 = &red_led;
+		led1 = &green_led;
+		led2 = &red_led;
+		sw0 = &user_button_2;
+		sw1 = &user_button_3;
+		watchdog0 = &wwdt0;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash;
+		zephyr,flash-controller = &fmu;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,console = &lpuart2;
+		zephyr,shell-uart = &lpuart2;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		red_led: led_0 {
+			gpios = <&gpio3 18 GPIO_ACTIVE_LOW>;
+			label = "Red LED";
+		};
+
+		green_led: led_1 {
+			gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
+			label = "Green LED";
+		};
+
+		blue_led: led_2 {
+			gpios = <&gpio3 21 GPIO_ACTIVE_LOW>;
+			label = "Blue LED";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		user_button_2: button_2 {
+			label = "User SW2";
+			gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		user_button_3: button_3 {
+			label = "User SW3";
+			gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+
+};
+
+&porta {
+	status = "okay";
+};
+
+&portb {
+	status = "okay";
+};
+
+&portc {
+	status = "okay";
+};
+
+&portd {
+	status = "okay";
+};
+
+&porte {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&lpuart2 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&pinmux_lpuart2>;
+	pinctrl-names = "default";
+};
+
+&flash {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 DT_SIZE_K(64)>;
+			read-only;
+		};
+		slot0_partition: partition@10000 {
+			label = "image-0";
+			reg = <0x00010000 DT_SIZE_K(400)>;
+		};
+		slot1_partition: partition@74000 {
+			label = "image-1";
+			reg = <0x00074000 DT_SIZE_K(400)>;
+		};
+		storage_partition: partition@d8000 {
+			label = "storage";
+			reg = <0x000d8000 DT_SIZE_K(112)>;
+		};
+	};
+};
+
+&wwdt0 {
+	status = "okay";
+};
diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml b/boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml
new file mode 100644
index 00000000000..72c1be60f4e
--- /dev/null
+++ b/boards/nxp/frdm_mcxa276/frdm_mcxa276.yaml
@@ -0,0 +1,21 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: frdm_mcxa276
+name: NXP FRDM MCXA276
+type: mcu
+arch: arm
+ram: 240
+flash: 1024
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - uart
+  - flash
+  - watchdog
+vendor: nxp
diff --git a/boards/nxp/frdm_mcxa276/frdm_mcxa276_defconfig b/boards/nxp/frdm_mcxa276/frdm_mcxa276_defconfig
new file mode 100644
index 00000000000..a630917318f
--- /dev/null
+++ b/boards/nxp/frdm_mcxa276/frdm_mcxa276_defconfig
@@ -0,0 +1,11 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_GPIO=y
diff --git a/boards/nxp/frdm_mcxc242/Kconfig.defconfig b/boards/nxp/frdm_mcxc242/Kconfig.defconfig
new file mode 100644
index 00000000000..6028882b542
--- /dev/null
+++ b/boards/nxp/frdm_mcxc242/Kconfig.defconfig
@@ -0,0 +1,16 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if BOARD_FRDM_MCXC242
+
+if USB_CDC_ACM
+
+config USB_CDC_ACM_RINGBUF_SIZE
+	default 256
+
+endif #USB_CDC_ACM
+
+endif #BOARD_FRDM_MCXC242
diff --git a/boards/nxp/frdm_mcxc242/doc/index.rst b/boards/nxp/frdm_mcxc242/doc/index.rst
index 447cebd8dfa..1c2286ca7dc 100644
--- a/boards/nxp/frdm_mcxc242/doc/index.rst
+++ b/boards/nxp/frdm_mcxc242/doc/index.rst
@@ -38,47 +38,7 @@ these references:
 Supported Features
 ==================
 
-The ``frdm_mcxc242`` board target supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling                 |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | soc flash                           |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| LPTMR     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| PIT       | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-
-
-Targets available
-==================
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/frdm_mcxc242/frdm_mcxc242_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -101,6 +61,10 @@ PORTB/GPIOB, PORTC/GPIOC, PORTD/GPIOD, and PORTE/GPIOE) for the FRDM-MCXC242 boa
 +-------+-------------+---------------------------+
 | PTA2  | LPUART0_TX  | UART Console              |
 +-------+-------------+---------------------------+
+| PTE1  | LPUART1_RX  | UART                      |
++-------+-------------+---------------------------+
+| PTE0  | LPUART1_TX  | UART                      |
++-------+-------------+---------------------------+
 | PTA20 | RESET       | RESET Button SW1          |
 +-------+-------------+---------------------------+
 | PTC1  | GPIO        | User button SW2           |
@@ -125,6 +89,8 @@ The MCXC242 LPUART0 is used for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -208,6 +174,9 @@ should see the following message in the terminal:
    *** Booting Zephyr OS build v3.6.0-4475-gfa5bd8bb098e ***
    Hello World! frdm_mcxc242/mcxc242
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _MCX C14x/24x/44x Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-c-series-microcontrollers/mcx-c14x-24x-44x-mcus-with-arm-cortex-m0-plus-entry-level-mcus-with-usb-segment-lcd-and-classical-peripherals:MCX-C14x-24x-44x
 
diff --git a/boards/nxp/frdm_mcxc242/frdm_mcxc242-pinctrl.dtsi b/boards/nxp/frdm_mcxc242/frdm_mcxc242-pinctrl.dtsi
index 2e8908e954e..2bcb42359a9 100644
--- a/boards/nxp/frdm_mcxc242/frdm_mcxc242-pinctrl.dtsi
+++ b/boards/nxp/frdm_mcxc242/frdm_mcxc242-pinctrl.dtsi
@@ -16,6 +16,14 @@
 			slew-rate = "slow";
 		};
 	};
+	pinmux_lpuart1: pinmux_lpuart1 {
+		group0 {
+			pinmux = <LPUART1_RX_PTE1>,
+				<LPUART1_TX_PTE0>;
+			drive-strength = "low";
+			slew-rate = "slow";
+		};
+	};
 	pinmux_uart2: pinmux_uart2 {
 		group0 {
 			pinmux = <UART2_RX_PTD2>,
diff --git a/boards/nxp/frdm_mcxc242/frdm_mcxc242.dts b/boards/nxp/frdm_mcxc242/frdm_mcxc242.dts
index 7c4a9da5004..20564d40a25 100644
--- a/boards/nxp/frdm_mcxc242/frdm_mcxc242.dts
+++ b/boards/nxp/frdm_mcxc242/frdm_mcxc242.dts
@@ -122,6 +122,13 @@
 	pinctrl-names = "default";
 };
 
+&lpuart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&pinmux_lpuart1>;
+	pinctrl-names = "default";
+};
+
 &uart2 {
 	status = "disabled";
 	current-speed = <115200>;
diff --git a/boards/nxp/frdm_mcxc242/frdm_mcxc242.yaml b/boards/nxp/frdm_mcxc242/frdm_mcxc242.yaml
index 778d8428495..a8e920ea89d 100644
--- a/boards/nxp/frdm_mcxc242/frdm_mcxc242.yaml
+++ b/boards/nxp/frdm_mcxc242/frdm_mcxc242.yaml
@@ -13,7 +13,6 @@ flash: 64
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - counter
diff --git a/boards/nxp/frdm_mcxc444/doc/index.rst b/boards/nxp/frdm_mcxc444/doc/index.rst
index 601bc9877a7..28cde8b45b9 100644
--- a/boards/nxp/frdm_mcxc444/doc/index.rst
+++ b/boards/nxp/frdm_mcxc444/doc/index.rst
@@ -37,45 +37,7 @@ these references:
 Supported Features
 ==================
 
-The ``frdm_mcxc444`` board target supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | soc flash                           |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| LPTMR     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| PIT       | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-
-
-Targets available
-==================
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/frdm_mcxc444/frdm_mcxc444_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -122,6 +84,8 @@ The MCXC444 LPUART0 is used for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -205,6 +169,9 @@ should see the following message in the terminal:
    *** Booting Zephyr OS build v3.6.0-4475-gfa5bd8bb098e ***
    Hello World! frdm_mcxc444/mcxc444
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _MCX C14x/24x/44x Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-c-series-microcontrollers/mcx-c14x-24x-44x-mcus-with-arm-cortex-m0-plus-entry-level-mcus-with-usb-segment-lcd-and-classical-peripherals:MCX-C14x-24x-44x
 
diff --git a/boards/nxp/frdm_mcxc444/frdm_mcxc444-pinctrl.dtsi b/boards/nxp/frdm_mcxc444/frdm_mcxc444-pinctrl.dtsi
index 36b40c40abc..328ce758ba4 100644
--- a/boards/nxp/frdm_mcxc444/frdm_mcxc444-pinctrl.dtsi
+++ b/boards/nxp/frdm_mcxc444/frdm_mcxc444-pinctrl.dtsi
@@ -8,6 +8,14 @@
 #include <nxp/mcx/MCXC444VLH-pinctrl.h>
 
 &pinctrl {
+	pinmux_adc0: pinmux_adc0 {
+		group0 {
+			pinmux = <ADC0_SE0_PTE20>,
+				 <ADC0_SE3_PTE22>;
+			drive-strength = "low";
+			slew-rate = "slow";
+		};
+	};
 	pinmux_i2c0: pinmux_i2c0 {
 		group0 {
 			pinmux = <I2C0_SCL_PTE24>,
diff --git a/boards/nxp/frdm_mcxc444/frdm_mcxc444.dts b/boards/nxp/frdm_mcxc444/frdm_mcxc444.dts
index df6c55e5721..3fc85d96075 100644
--- a/boards/nxp/frdm_mcxc444/frdm_mcxc444.dts
+++ b/boards/nxp/frdm_mcxc444/frdm_mcxc444.dts
@@ -119,6 +119,12 @@
 	status = "okay";
 };
 
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_adc0>;
+	pinctrl-names = "default";
+};
+
 i2c0: &i2c0 {
 	status = "okay";
 	pinctrl-0 = <&pinmux_i2c0>;
diff --git a/boards/nxp/frdm_mcxc444/frdm_mcxc444.yaml b/boards/nxp/frdm_mcxc444/frdm_mcxc444.yaml
index a7aabf28a35..201eacecb17 100644
--- a/boards/nxp/frdm_mcxc444/frdm_mcxc444.yaml
+++ b/boards/nxp/frdm_mcxc444/frdm_mcxc444.yaml
@@ -13,8 +13,8 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
+  - adc
   - counter
   - flash
   - gpio
diff --git a/boards/nxp/frdm_mcxn236/Kconfig b/boards/nxp/frdm_mcxn236/Kconfig
index 23271bc179f..db8c981eda9 100644
--- a/boards/nxp/frdm_mcxn236/Kconfig
+++ b/boards/nxp/frdm_mcxn236/Kconfig
@@ -1,8 +1,5 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
-
-config BOARD_INIT_PRIORITY
-	int "Board initialization priority"
-	default 1
-	help
-	  Board initialization priority.
+#
+config BOARD_FRDM_MCXN236
+	select BOARD_EARLY_INIT_HOOK
diff --git a/boards/nxp/frdm_mcxn236/Kconfig.defconfig b/boards/nxp/frdm_mcxn236/Kconfig.defconfig
new file mode 100644
index 00000000000..919727e5e7e
--- /dev/null
+++ b/boards/nxp/frdm_mcxn236/Kconfig.defconfig
@@ -0,0 +1,13 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_FRDM_MCXN236
+
+if BOOTLOADER_MCUBOOT
+choice MCUBOOT_BOOTLOADER_MODE
+	# Board only supports MCUBoot via "upgrade only" method:
+	default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY
+endchoice
+endif #BOOTLOADER_MCUBOOT
+
+endif
diff --git a/boards/nxp/frdm_mcxn236/Kconfig.sysbuild b/boards/nxp/frdm_mcxn236/Kconfig.sysbuild
new file mode 100644
index 00000000000..d7364d0356b
--- /dev/null
+++ b/boards/nxp/frdm_mcxn236/Kconfig.sysbuild
@@ -0,0 +1,6 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+choice MCUBOOT_MODE
+	default MCUBOOT_MODE_OVERWRITE_ONLY
+endchoice
diff --git a/boards/nxp/frdm_mcxn236/board.c b/boards/nxp/frdm_mcxn236/board.c
index 0f26f857242..fff4c085a96 100644
--- a/boards/nxp/frdm_mcxn236/board.c
+++ b/boards/nxp/frdm_mcxn236/board.c
@@ -12,7 +12,7 @@
 #include "usb_phy.h"
 #include "usb.h"
 
-/* USB PHY condfiguration */
+/* USB PHY configuration */
 #define BOARD_USB_PHY_D_CAL     0x04U
 #define BOARD_USB_PHY_TXCAL45DP 0x07U
 #define BOARD_USB_PHY_TXCAL45DM 0x07U
@@ -57,7 +57,7 @@ void power_mode_od(void)
 	SPC_SetSRAMOperateVoltage(SPC0, &cfg);
 }
 
-static int frdm_mcxn236_init(void)
+void board_early_init_hook(void)
 {
 	enable_lpcac();
 
@@ -119,23 +119,27 @@ static int frdm_mcxn236_init(void)
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm1))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
 	CLOCK_SetClkDiv(kCLOCK_DivFlexcom1Clk, 1u);
-	CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM1);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm2))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
 	CLOCK_SetClkDiv(kCLOCK_DivFlexcom2Clk, 1u);
-	CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM2);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm3))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
 	CLOCK_SetClkDiv(kCLOCK_DivFlexcom3Clk, 1u);
-	CLOCK_AttachClk(kFRO12M_to_FLEXCOMM3);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM3);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm4))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
 	CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
-	CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM4);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm5))
@@ -301,8 +305,4 @@ static int frdm_mcxn236_init(void)
 
 	/* Set SystemCoreClock variable. */
 	SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
-
-	return 0;
 }
-
-SYS_INIT(frdm_mcxn236_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);
diff --git a/boards/nxp/frdm_mcxn236/board.cmake b/boards/nxp/frdm_mcxn236/board.cmake
index 705a6443526..da7dfb17a86 100644
--- a/boards/nxp/frdm_mcxn236/board.cmake
+++ b/boards/nxp/frdm_mcxn236/board.cmake
@@ -6,16 +6,6 @@
 
 board_runner_args(jlink "--device=MCXN236" "--reset-after-load")
 board_runner_args(linkserver  "--device=MCXN236:FRDM-MCXN236")
-board_runner_args(linkserver  "--core=cm33_core0")
-board_runner_args(linkserver  "--override=/device/memory/1/flash-driver=MCXNxxx_S.cfx")
-board_runner_args(linkserver  "--override=/device/memory/1/location=0x10000000")
-# Linkserver v1.4.85 and earlier do not include the secure regions in the
-# MCXN236 memory map, so we add them here
-board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x30000000\",\
-                               \"size\":\"0x00040000\",\"type\":\"RAM\"\}")
-# Define region for peripherals
-board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x50000000\",\
-                               \"size\":\"0x00140000\",\"type\":\"RAM\"\}")
 
 # Pyocd support added with the NXP.MCXN236_DFP.17.0.0.pack CMSIS Pack
 board_runner_args(pyocd "--target=mcxn236")
diff --git a/boards/nxp/frdm_mcxn236/doc/index.rst b/boards/nxp/frdm_mcxn236/doc/index.rst
index 48052ad4e56..91fe9514ebb 100644
--- a/boards/nxp/frdm_mcxn236/doc/index.rst
+++ b/boards/nxp/frdm_mcxn236/doc/index.rst
@@ -35,63 +35,7 @@ For more information about the MCX-N236 SoC and FRDM-MCXN236 board, see:
 Supported Features
 ==================
 
-The FRDM-MCXN236 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| I3C       | on-chip    | i3c                                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | soc flash                           |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| VREF      | on-chip    | regulator                           |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| USBHS     | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| LPCMP     | on-chip    | sensor(comparator)                  |
-+-----------+------------+-------------------------------------+
-| FLEXCAN   | on-chip    | CAN                                 |
-+-----------+------------+-------------------------------------+
-| FLEXIO    | on-chip    | flexio                              |
-+-----------+------------+-------------------------------------+
-| DISPLAY   | on-chip    | flexio; MIPI-DBI. Tested with       |
-|           |            | :ref:`lcd_par_s035`                 |
-+-----------+------------+-------------------------------------+
-| LPTMR     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| MRT       | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Targets available
-==================
-
-The default configuration file
-:zephyr_file:`boards/nxp/frdm_mcxn236/frdm_mcxn236_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -122,6 +66,8 @@ Flexcomm 4 is configured as UART for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -211,6 +157,9 @@ Troubleshooting
 .. include:: ../../common/segger-ecc-systemview.rst
    :start-after: segger-ecc-systemview
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _MCX-N236 SoC Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-n-series-microcontrollers/mcx-n23x-highly-integrated-mcus-with-on-chip-accelerators-intelligent-peripherals-and-advanced-security:MCX-N23X
 
diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi
index 26515a78797..8223342b414 100644
--- a/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi
+++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.dtsi
@@ -15,6 +15,7 @@
 		led2 = &blue_led;
 		sw0 = &user_button_2;
 		sw1 = &user_button_3;
+		mcuboot-button0 = &user_button_2;
 	};
 
 	leds {
@@ -115,20 +116,28 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 {
 		#address-cells = <1>;
 		#size-cells = <1>;
 
+		/*
+		 * Partition sizes must be aligned
+		 * to the flash memory sector size of 8KB.
+		 */
 		boot_partition: partition@0 {
 			label = "mcuboot";
-			reg = <0x00000000 DT_SIZE_K(64)>;
+			reg = <0x00000000 DT_SIZE_K(80)>;
 		};
-		/* Note slot 0 has one additional sector,
-		 * this is intended for use with the swap move algorithm
+		/* For the MCUBoot "upgrade only" method,
+		 * the slot sizes must be equal.
 		 */
-		slot0_partition: partition@10000 {
+		slot0_partition: partition@14000 {
 			label = "image-0";
-			reg = <0x00010000 DT_SIZE_K(480)>;
+			reg = <0x00014000 DT_SIZE_K(440)>;
 		};
-		slot1_partition: partition@88000 {
+		slot1_partition: partition@84000 {
 			label = "image-1";
-			reg = <0x0088000 DT_SIZE_K(472)>;
+			reg = <0x0084000 DT_SIZE_K(440)>;
+		};
+		storage_partition: partition@F0000 {
+			label = "storage";
+			reg = <0x000F0000 DT_SIZE_K(64)>;
 		};
 	};
 };
diff --git a/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml b/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml
index 6e2ef3c817c..2453534b318 100644
--- a/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml
+++ b/boards/nxp/frdm_mcxn236/frdm_mcxn236.yaml
@@ -13,7 +13,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - can
diff --git a/boards/nxp/frdm_mcxn947/Kconfig b/boards/nxp/frdm_mcxn947/Kconfig
index 23271bc179f..2e1614f868b 100644
--- a/boards/nxp/frdm_mcxn947/Kconfig
+++ b/boards/nxp/frdm_mcxn947/Kconfig
@@ -1,8 +1,5 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-config BOARD_INIT_PRIORITY
-	int "Board initialization priority"
-	default 1
-	help
-	  Board initialization priority.
+config BOARD_FRDM_MCXN947
+	select BOARD_EARLY_INIT_HOOK
diff --git a/boards/nxp/frdm_mcxn947/board.c b/boards/nxp/frdm_mcxn947/board.c
index 7bf3f8999cc..40efcb3ab81 100644
--- a/boards/nxp/frdm_mcxn947/board.c
+++ b/boards/nxp/frdm_mcxn947/board.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024  NXP
+ * Copyright 2024-2025 NXP
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <zephyr/init.h>
@@ -12,7 +12,7 @@
 #include "usb_phy.h"
 #include "usb.h"
 
-/* USB PHY condfiguration */
+/* USB PHY configuration */
 #define BOARD_USB_PHY_D_CAL     (0x04U)
 #define BOARD_USB_PHY_TXCAL45DP (0x07U)
 #define BOARD_USB_PHY_TXCAL45DM (0x07U)
@@ -84,7 +84,20 @@ __ramfunc static void enable_cache64(void)
 }
 #endif
 
-static int frdm_mcxn947_init(void)
+static void unsecure_gpio(GPIO_Type * base)
+{
+	/* Enables CPU1 to access GPIO registers
+	 * Pins and interrupts can be configured in non-secure access
+	 */
+	base->PCNS = 0xFFFFFFFFU;
+	base->ICNS = GPIO_ICNS_NSE1_MASK | GPIO_ICNS_NSE0_MASK;
+
+	/* Pins and interrupts can be configured in non-privilege access */
+	base->PCNP = 0xFFFFFFFFU;
+	base->ICNP = GPIO_ICNP_NPE1_MASK | GPIO_ICNP_NPE0_MASK;
+}
+
+void board_early_init_hook(void)
 {
 	power_mode_od();
 
@@ -131,43 +144,50 @@ static int frdm_mcxn947_init(void)
 
 	CLOCK_SetupExtClocking(BOARD_XTAL0_CLK_HZ);
 
-#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan0))
-	/* Set up PLL1 for 80 MHz FlexCAN clock */
-	const pll_setup_t pll1Setup = {
-		.pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(27U) |
-			   SCG_SPLLCTRL_SELP(13U),
-		.pllndiv = SCG_SPLLNDIV_NDIV(3U),
-		.pllpdiv = SCG_SPLLPDIV_PDIV(1U),
-		.pllmdiv = SCG_SPLLMDIV_MDIV(10U),
-		.pllRate = 80000000U
-	};
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1))
+	/* < Set up PLL1 */
+	const pll_setup_t pll1_Setup = {
+		.pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(3U) |
+				 SCG_SPLLCTRL_SELP(1U),
+		.pllndiv = SCG_SPLLNDIV_NDIV(25U),
+		.pllpdiv = SCG_SPLLPDIV_PDIV(10U),
+		.pllmdiv = SCG_SPLLMDIV_MDIV(256U),
+		.pllRate = 24576000U};
 
 	/* Configure PLL1 to the desired values */
-	CLOCK_SetPLL1Freq(&pll1Setup);
-	/* PLL1 Monitor is disabled */
-	CLOCK_SetPll1MonitorMode(kSCG_Pll1MonitorDisable);
+	CLOCK_SetPLL1Freq(&pll1_Setup);
 	/* Set PLL1 CLK0 divider to value 1 */
 	CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 1U);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm1))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
 	CLOCK_SetClkDiv(kCLOCK_DivFlexcom1Clk, 1u);
-	CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM1);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm2))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
 	CLOCK_SetClkDiv(kCLOCK_DivFlexcom2Clk, 1u);
-	CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM2);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm3))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom3Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM3);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm4))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
 	CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
-	CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM4);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm7))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
 	CLOCK_SetClkDiv(kCLOCK_DivFlexcom7Clk, 1u);
-	CLOCK_AttachClk(kFRO12M_to_FLEXCOMM7);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM7);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(os_timer))
@@ -176,22 +196,27 @@ static int frdm_mcxn947_init(void)
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0))
 	CLOCK_EnableClock(kCLOCK_Gpio0);
+	unsecure_gpio(GPIO0);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1))
 	CLOCK_EnableClock(kCLOCK_Gpio1);
+	unsecure_gpio(GPIO1);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2))
 	CLOCK_EnableClock(kCLOCK_Gpio2);
+	unsecure_gpio(GPIO2);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3))
 	CLOCK_EnableClock(kCLOCK_Gpio3);
+	unsecure_gpio(GPIO3);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio4))
 	CLOCK_EnableClock(kCLOCK_Gpio4);
+	unsecure_gpio(GPIO4);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dac0))
@@ -250,7 +275,7 @@ static int frdm_mcxn947_init(void)
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan0))
 	CLOCK_SetClkDiv(kCLOCK_DivFlexcan0Clk, 1U);
-	CLOCK_AttachClk(kPLL1_CLK0_to_FLEXCAN0);
+	CLOCK_AttachClk(kFRO_HF_to_FLEXCAN0);
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc0))
@@ -383,10 +408,18 @@ static int frdm_mcxn947_init(void)
 	CLOCK_AttachClk(kFRO_HF_to_SCT);
 #endif
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0))
+	CLOCK_SetClkDiv(kCLOCK_DivSai0Clk, 1u);
+	CLOCK_AttachClk(kPLL1_CLK0_to_SAI0);
+	CLOCK_EnableClock(kCLOCK_Sai0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1))
+	CLOCK_SetClkDiv(kCLOCK_DivSai1Clk, 1u);
+	CLOCK_AttachClk(kPLL1_CLK0_to_SAI1);
+	CLOCK_EnableClock(kCLOCK_Sai1);
+#endif
+
 	/* Set SystemCoreClock variable. */
 	SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
-
-	return 0;
 }
-
-SYS_INIT(frdm_mcxn947_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);
diff --git a/boards/nxp/frdm_mcxn947/board.cmake b/boards/nxp/frdm_mcxn947/board.cmake
index fa5862e5e00..f26f08890bf 100644
--- a/boards/nxp/frdm_mcxn947/board.cmake
+++ b/boards/nxp/frdm_mcxn947/board.cmake
@@ -4,10 +4,14 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-if(CONFIG_SOC_MCXN947_CPU0)
+if(CONFIG_SOC_MCXN947_CPU0 OR CONFIG_SECOND_CORE_MCUX)
   board_runner_args(jlink "--device=MCXN947_M33_0" "--reset-after-load")
   board_runner_args(linkserver  "--device=MCXN947:FRDM-MCXN947")
-  board_runner_args(linkserver  "--core=cm33_core0")
+  if(CONFIG_SECOND_CORE_MCUX)
+    board_runner_args(linkserver  "--core=all")
+  else()
+    board_runner_args(linkserver  "--core=cm33_core0")
+  endif()
   board_runner_args(linkserver  "--override=/device/memory/1/flash-driver=MCXN9xx_S.cfx")
   board_runner_args(linkserver  "--override=/device/memory/1/location=0x10000000")
   # Linkserver v1.4.85 and earlier do not include the secure regions in the
@@ -19,8 +23,10 @@ if(CONFIG_SOC_MCXN947_CPU0)
   # Define region for peripherals
   board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x50000000\",\
                                \"size\":\"0x00140000\",\"type\":\"RAM\"\}")
-else()
-  message(FATAL_ERROR "Support for cpu1 not available yet")
+elseif(CONFIG_SOC_MCXN947_CPU1)
+  board_runner_args(jlink "--device=MCXN947_M33_1" "--reset-after-load")
+  board_runner_args(linkserver  "--device=MCXN947:FRDM-MCXN947")
+  board_runner_args(linkserver  "--core=cm33_core1")
 endif()
 
 # Pyocd support added with the NXP.MCXN947_DFP.17.0.0.pack CMSIS Pack
diff --git a/boards/nxp/frdm_mcxn947/doc/index.rst b/boards/nxp/frdm_mcxn947/doc/index.rst
index e923d67b9ab..3f7ca04a6ba 100644
--- a/boards/nxp/frdm_mcxn947/doc/index.rst
+++ b/boards/nxp/frdm_mcxn947/doc/index.rst
@@ -37,80 +37,55 @@ For more information about the MCX-N947 SoC and FRDM-MCXN947 board, see:
 Supported Features
 ==================
 
-The FRDM-MCXN947 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| I3C       | on-chip    | i3c                                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | soc flash                           |
-+-----------+------------+-------------------------------------+
-| FLEXSPI   | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | dac                                 |
-+-----------+------------+-------------------------------------+
-| ENET QOS  | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| SCTimer   | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| CTIMER    | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| USDHC     | on-chip    | sdhc                                |
-+-----------+------------+-------------------------------------+
-| VREF      | on-chip    | regulator                           |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| HWINFO    | on-chip    | Unique device serial number         |
-+-----------+------------+-------------------------------------+
-| USBHS     | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| LPCMP     | on-chip    | sensor(comparator)                  |
-+-----------+------------+-------------------------------------+
-| FLEXCAN   | on-chip    | CAN                                 |
-+-----------+------------+-------------------------------------+
-| LPTMR     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| FLEXIO    | on-chip    | flexio                              |
-+-----------+------------+-------------------------------------+
-| DISPLAY   | on-chip    | flexio; MIPI-DBI. Tested with       |
-|           |            | :ref:`lcd_par_s035`                 |
-+-----------+------------+-------------------------------------+
-| MRT       | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
+
+Dual Core samples
+*****************
+
++-----------+----------------------+-------------------------------+
+| Core      | Flash Region         | Comment                       |
++===========+======================+===============================+
+| CPU0      | Full flash memory    | Primary core with bootloader  |
+|           | (including partition | access and application in     |
+|           | slot0_partition)     | slot0_partition               |
++-----------+----------------------+-------------------------------+
+| CPU1      | slot1_partition only | Secondary core restricted to  |
+|           |                      | its dedicated partition       |
++-----------+----------------------+-------------------------------+
+
++----------+------------------+-----------------------+
+| Memory   | Region           | Comment               |
++==========+==================+=======================+
+| srama    | RAM (320KB)      | CPU0 ram              |
++----------+------------------+-----------------------+
+| sramg    | RAM (64KB)       | CPU1 ram              |
++----------+------------------+-----------------------+
+| sramh    | RAM (32KB)       | Shared memory         |
++----------+------------------+-----------------------+
+
+.. note::
+   The actual memory addresses are defined in the device tree and can be viewed in the
+   generated map files after building. CPU0 accesses the full flash memory starting from
+   its base address, while CPU1 is restricted to the slot1_partition region.
 
 Targets available
 ==================
 
 The default configuration file
 :zephyr_file:`boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_defconfig`
-only enables the first core.
+only enables the first core. CPU0 is the only target that can run standalone.
 
-Other hardware features are not currently supported by the port.
+CPU1 does not work without CPU0 enabling it.
+
+To enable CPU1, create System Build application project and enable the
+second core with config :kconfig:option:`CONFIG_SECOND_CORE_MCUX`.
+
+Please have a look at some already enabled samples:
+
+- :zephyr_file:`samples/subsys/ipc/ipc_service/static_vrings`
+- :zephyr_file:`samples/subsys/ipc/openamp`
+- :zephyr_file:`samples/drivers/mbox`
+- :zephyr_file:`samples/drivers/mbox_data`
 
 Connections and IOs
 ===================
@@ -121,9 +96,13 @@ can be used to configure the functionality of a pin.
 +------------+-----------------+----------------------------+
 | Name       | Function        | Usage                      |
 +============+=================+============================+
-| P0_PIO1_8  | UART            | UART RX                    |
+| P0_PIO1_8  | UART            | UART RX cpu0               |
++------------+-----------------+----------------------------+
+| P1_PIO1_9  | UART            | UART TX cpu0               |
++------------+-----------------+----------------------------+
+| P4_PIO4_3  | UART            | UART RX cpu1               |
 +------------+-----------------+----------------------------+
-| P1_PIO1_9  | UART            | UART TX                    |
+| P4_PIO4_2  | UART            | UART TX cpu1               |
 +------------+-----------------+----------------------------+
 
 System Clock
@@ -141,6 +120,8 @@ Flexcomm 4 is configured as UART for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -206,6 +187,25 @@ see the following message in the terminal:
    *** Booting Zephyr OS build v3.6.0-479-g91faa20c6741 ***
    Hello World! frdm_mcxn947/mcxn947/cpu0
 
+Building a dual-core image
+--------------------------
+
+The dual-core samples are run using ``frdm_mcxn947/mcxn947/cpu0`` target.
+
+Images built for ``frdm_mcxn947/mcxn947/cpu1`` will be loaded from flash
+and executed on the second core when :kconfig:option:`CONFIG_SECOND_CORE_MCUX` is selected.
+
+For an example of building for both cores with System Build, see
+:zephyr_file:`samples/subsys/ipc/ipc_service/static_vrings`
+
+Here is an example for the :zephyr:code-sample:`mbox_data` application.
+
+.. zephyr-app-commands::
+   :app: zephyr/samples/drivers/mbox_data
+   :board: frdm_mcxn947/mcxn947/cpu0
+   :goals: flash
+   :west-args: --sysbuild
+
 Flashing to QSPI
 ================
 
@@ -261,12 +261,23 @@ should see the following message in the terminal:
    *** Booting Zephyr OS build v3.6.0-479-g91faa20c6741 ***
    Hello World! frdm_mcxn947/mcxn947/cpu0
 
+Debugging a dual-core image
+---------------------------
+
+For dual core builds, the secondary core should be placed into a loop,
+then a debugger can be attached.
+As a reference please see (`AN13264`_, section 4.2.3 for more information).
+The reference is for the RT1170 but similar technique can be also used here.
+
 Troubleshooting
 ===============
 
 .. include:: ../../common/segger-ecc-systemview.rst
    :start-after: segger-ecc-systemview
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _MCX-N947 SoC Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-n-series-microcontrollers/mcx-n94x-54x-highly-integrated-multicore-mcus-with-on-chip-accelerators-intelligent-peripherals-and-advanced-security:MCX-N94X-N54X
 
@@ -287,3 +298,6 @@ Troubleshooting
 
 .. _FRDM-MCXN947 Schematics:
    https://www.nxp.com/webapp/Download?colCode=90818-MCXN947SH
+
+.. _AN13264:
+   https://www.nxp.com/docs/en/application-note/AN13264.pdf
diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi
index ce4995b6d1c..b2597191d55 100644
--- a/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi
+++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947-pinctrl.dtsi
@@ -31,6 +31,18 @@
 		};
 	};
 
+	pinmux_flexcomm3_lpi2c: pinmux_flexcomm3_lpi2c {
+		group0 {
+			pinmux = <FC3_P0_PIO1_0>,
+				<FC3_P1_PIO1_1>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+			bias-pull-up;
+			drive-open-drain;
+		};
+	};
+
 	pinmux_flexcomm7_lpi2c: pimux_flexcomm7_lpi2c {
 		group0 {
 			pinmux = <FC7_P0_PIO3_2>,
@@ -92,6 +104,31 @@
 		};
 	};
 
+	pinmux_sai1: pinmux_sai1 {
+		group0 {
+			pinmux = <SAI1_TX_BCLK_PIO3_16>,
+				<SAI1_TX_FS_PIO3_17>,
+				<SAI1_TXD0_PIO3_20>,
+				<SAI1_RX_FS_PIO3_19>,
+				<SAI1_RX_BCLK_PIO3_18>,
+				<SAI1_RXD0_PIO3_21>;
+			drive-strength = "high";
+			slew-rate = "fast";
+			input-enable;
+		};
+	};
+
+	pinmux_sai0: pinmux_sai0 {
+		group0 {
+			pinmux = <SAI0_TXD0_PIO2_2>,
+				<SAI0_TX_BCLK_PIO2_6>,
+				<SAI0_TX_FS_PIO2_7>;
+			drive-strength = "high";
+			slew-rate = "fast";
+			input-enable;
+		};
+	};
+
 	pinmux_enet_qos: pinmux_enet_qos {
 		mdio_group {
 			pinmux = <ENET0_MDC_PIO1_20>,
diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi
index 574f20aecaf..3ebc13c0e9a 100644
--- a/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi
+++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947.dtsi
@@ -132,12 +132,27 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 {
 	status = "okay";
 };
 
+&sram {
+	sramg: memory@20050000 {
+		compatible = "mmio-sram";
+		reg = <0x20050000 DT_SIZE_K(64)>;
+	};
+	sramh: memory@20060000 {
+		compatible = "mmio-sram";
+		reg = <0x20060000 DT_SIZE_K(32)>;
+	};
+};
+
 &flash {
 	partitions {
 		compatible = "fixed-partitions";
 		#address-cells = <1>;
 		#size-cells = <1>;
 
+		/*
+		 * Partition sizes must be aligned
+		 * to the flash memory sector size of 8KB.
+		 */
 		boot_partition: partition@0 {
 			label = "mcuboot";
 			reg = <0x00000000 DT_SIZE_K(80)>;
@@ -183,15 +198,6 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 {
 		cs-setup-time = <3>;
 		data-valid-time = <2>;
 		column-space = <0>;
-		partitions {
-			compatible = "fixed-partitions";
-			#address-cells = <1>;
-			#size-cells = <1>;
-			storage_partition: partition@0 {
-				label = "storage";
-				reg = <0x0 DT_SIZE_M(8)>;
-			};
-		};
 	};
 };
 
@@ -200,6 +206,16 @@ nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 {
 	pinctrl-names = "default";
 };
 
+&sai1 {
+	pinctrl-0 = <&pinmux_sai1>;
+	pinctrl-names = "default";
+};
+
+&sai0 {
+	pinctrl-0 = <&pinmux_sai0>;
+	pinctrl-names = "default";
+};
+
 &enet {
 	pinctrl-0 = <&pinmux_enet_qos>;
 	pinctrl-names = "default";
diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi
index 789f4d8c18e..d74efb27ac6 100644
--- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi
+++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.dtsi
@@ -27,6 +27,7 @@
 		zephyr,console = &flexcomm4_lpuart4;
 		zephyr,shell-uart = &flexcomm4_lpuart4;
 		zephyr,canbus = &flexcan0;
+		zephyr,code-cpu1-partition = &slot1_partition;
 	};
 
 	aliases{
@@ -51,6 +52,10 @@
 	reg = <0x20000000 DT_SIZE_K(320)>;
 };
 
+&mbox {
+	status = "okay";
+};
+
 &gpio4 {
 	status = "okay";
 };
@@ -129,6 +134,15 @@
 
 &w25q64jvssiq {
 	status = "okay";
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		storage_partition: partition@0 {
+			label = "storage";
+			reg = <0x0 DT_SIZE_M(8)>;
+		};
+	};
 };
 
 &dac0 {
@@ -182,7 +196,7 @@
 
 zephyr_udc0: &usb1 {
 	status = "okay";
-	phy_handle = <&usbphy1>;
+	phy-handle = <&usbphy1>;
 };
 
 &usbphy1 {
@@ -219,3 +233,10 @@ zephyr_udc0: &usb1 {
 &sc_timer {
 	status = "okay";
 };
+
+&sai1 {
+	status = "okay";
+};
+&sai0 {
+	status = "okay";
+};
diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml
index 8578e55b931..057162bca26 100644
--- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml
+++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0.yaml
@@ -13,7 +13,6 @@ flash: 2048
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - can
@@ -23,9 +22,11 @@ supported:
   - flash
   - gpio
   - i2c
+  - i2s
   - i3c
   - pwm
   - regulator
+  - rtc
   - sdhc
   - spi
   - usb_device
diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.yaml
index 15648a75da5..438ed728693 100644
--- a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.yaml
+++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu0_qspi.yaml
@@ -13,7 +13,6 @@ flash: 8192
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - can
@@ -26,6 +25,7 @@ supported:
   - i3c
   - pwm
   - regulator
+  - rtc
   - sdhc
   - spi
   - usb_device
diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1.dts b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1.dts
new file mode 100644
index 00000000000..78fc22c12a7
--- /dev/null
+++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1.dts
@@ -0,0 +1,72 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_mcxn94x.dtsi>
+#include "frdm_mcxn947.dtsi"
+
+/ {
+	model = "NXP FRDM_N94 board";
+	compatible = "nxp,mcxn947", "nxp,mcx";
+
+	cpus {
+		/delete-node/ cpu@0;
+	};
+
+	chosen {
+		zephyr,sram = &sramg;
+		zephyr,flash = &flash;
+		zephyr,flash-controller = &fmu;
+		zephyr,code-partition = &slot1_partition;
+		zephyr,console = &flexcomm2_lpuart2;
+		zephyr,shell-uart = &flexcomm2_lpuart2;
+	};
+};
+
+&flexcomm2 {
+	status = "okay";
+};
+
+&flexcomm2_lpuart2 {
+	status = "okay";
+};
+
+&mbox {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&green_led {
+	status = "okay";
+};
+
+&red_led {
+	status = "okay";
+};
+
+&user_button_2 {
+	status = "okay";
+};
+
+&edma0 {
+	status = "okay";
+};
diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1.yaml b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1.yaml
new file mode 100644
index 00000000000..62335a40f84
--- /dev/null
+++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1.yaml
@@ -0,0 +1,19 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: frdm_mcxn947/mcxn947/cpu1
+name: NXP FRDM MCXN947 (CPU1)
+type: mcu
+arch: arm
+ram: 64
+flash: 200
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - dma
+  - gpio
+vendor: nxp
diff --git a/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1_defconfig b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1_defconfig
new file mode 100644
index 00000000000..97c86346580
--- /dev/null
+++ b/boards/nxp/frdm_mcxn947/frdm_mcxn947_mcxn947_cpu1_defconfig
@@ -0,0 +1,13 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_GPIO=y
+
+CONFIG_USE_DT_CODE_PARTITION=y
diff --git a/boards/nxp/frdm_mcxw71/doc/index.rst b/boards/nxp/frdm_mcxw71/doc/index.rst
index d7d979fbe40..525ad8cdcf5 100644
--- a/boards/nxp/frdm_mcxw71/doc/index.rst
+++ b/boards/nxp/frdm_mcxw71/doc/index.rst
@@ -32,42 +32,7 @@ For more information about the MCXW71 SoC and FRDM-MCXW71 board, see:
 Supported Features
 ==================
 
-The ``frdm_mcxw71`` board target in Zephyr currently supports the following features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinctrl                             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| LPUART    | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| LPI2C     | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| LPSPI     | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| FMU       | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
-| TPM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| WDOG32    | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| LPTMR     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| BLE       | on-chip    | Bluetooth                           |
-+-----------+------------+-------------------------------------+
-| FLEXCAN   | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
-| VREF      | on-chip    | regulator                           |
-+-----------+------------+-------------------------------------+
-| LPADC     | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Fetch Binary Blobs
 ******************
@@ -82,6 +47,8 @@ achieved by running the following command:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -128,8 +95,26 @@ Connect a USB cable from your PC to J10, and use the serial terminal of your cho
 - Parity: None
 - Stop bits: 1
 
-Flashing
-========
+Application Building
+====================
+
+Openthread applications
+-----------------------
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/net/sockets/echo_server
+   :board: frdm_mcxw71
+   :goals: build
+   :gen-args: -DEXTRA_CONF_FILE=overlay-ot.conf
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/net/sockets/echo_client
+   :board: frdm_mcxw71
+   :goals: build
+   :gen-args: -DEXTRA_CONF_FILE=overlay-ot.conf
+
+Application Flashing
+====================
 
 Here is an example for the :zephyr:code-sample:`hello_world` application.
 
@@ -164,15 +149,17 @@ should see the following message in the terminal:
    *** Booting Zephyr OS build v3.7.0-xxx-xxxx ***
    Hello World! frdm_mcxw71/mcxw716c
 
-Bluetooth
-=========
+NBU Flashing
+============
 
 BLE functionality requires to fetch binary blobs, so make sure to follow
 the ``Fetch Binary Blobs`` section first.
 
 Two images must be written to the board: one for the host (CM33) and one for the NBU (CM3).
-- To flash the application (CM33) refer to the ``Flashing`` section above.
-- To flash the NBU, follow the instructions below:
+
+- To flash the application (CM33) refer to the ``Application Flashing`` section above.
+
+- To flash the ``NBU Flashing``, follow the instructions below:
 
    * Install ``blhost`` from NXP's website. This is the tool that will allow you to flash the NBU.
    * Enter ISP mode. To boot the MCU in ISP mode, follow these steps:
@@ -182,17 +169,39 @@ Two images must be written to the board: one for the host (CM33) and one for the
       - Reconnect any external power supply, if needed.
    * Use the following command to flash NBU file:
 
-.. code-block:: console
+.. tabs::
 
-   # On Windows
-   blhost.exe -p COMxx -- receive-sb-file mcxw71_nbu_ble.sb3
+   .. group-tab:: BLE NBU - Windows
 
-   # On Linux
-   ./blhost -p /dev/ttyxx -- receive-sb-file mcxw71_nbu_ble.sb3
+      .. code-block:: console
+         :caption: Flash BLE only NBU on Windows
+
+         blhost.exe -p COMxx -- receive-sb-file mcxw71_nbu_ble.sb3
+
+   .. group-tab:: BLE NBU - Linux
+
+      .. code-block:: console
+         :caption: Flash BLE only NBU on Linux
+
+         ./blhost -p /dev/ttyxx -- receive-sb-file mcxw71_nbu_ble.sb3
+
+   .. group-tab:: DYN NBU - Windows
+
+      .. code-block:: console
+         :caption: Flash Dynamic NBU (BLE + 15.4) on Windows
+
+         blhost.exe -p COMxx -- receive-sb-file mcxw71_nbu_ble_15_4_dyn.sb3
+
+   .. group-tab:: DYN NBU - Linux
+
+      .. code-block:: console
+         :caption: Flash Dynamic NBU (BLE + 15.4) on Linux
+
+         ./blhost -p /dev/ttyxx -- receive-sb-file mcxw71_nbu_ble_15_4_dyn.sb3
 
 Please consider changing ``COMxx`` on Windows or ``ttyxx`` on Linux to the serial port used by your board.
 
-The NBU file can be found in : ``<zephyr workspace>/modules/hal/nxp/zephyr/blobs/mcxw71/mcxw71_nbu_ble.sb3``
+The NBU files can be found in : ``<zephyr workspace>/modules/hal/nxp/zephyr/blobs/mcxw71/`` folder.
 
 For more details:
 
@@ -208,6 +217,9 @@ Troubleshooting
 .. include:: ../../common/segger-ecc-systemview.rst
    :start-after: segger-ecc-systemview
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 References
 **********
 
diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi b/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi
index 29e41f6926e..e1b876ee0b0 100644
--- a/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi
+++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71-pinctrl.dtsi
@@ -32,6 +32,16 @@
 		};
 	};
 
+	pinmux_lpi2c0: pinmux_lpi2c0 {
+		group0 {
+			pinmux = <LPI2C0_SCL_PTA19>,
+				<LPI2C0_SDA_PTA18>;
+			drive-strength = "low";
+			slew-rate = "fast";
+			drive-open-drain;
+		};
+	};
+
 	pinmux_lpi2c1: pinmux_lpi2c1 {
 		group0 {
 			pinmux = <LPI2C1_SCL_PTB5>,
@@ -45,7 +55,9 @@
 	pinmux_lpspi1: pinmux_lpspi1 {
 		group0 {
 			pinmux = <LPSPI1_SIN_PTB1>,
-				 <LPSPI1_SOUT_PTB3>;
+				 <LPSPI1_SCK_PTB2>,
+				 <LPSPI1_SOUT_PTB3>,
+				 <LPSPI1_PCS0_PTB0>;
 			slew-rate = "fast";
 			drive-strength = "low";
 		};
diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts
index 65e2e7a2f6a..99481630239 100644
--- a/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts
+++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -7,12 +7,14 @@
 
 #include <nxp/nxp_mcxw71.dtsi>
 #include "frdm_mcxw71-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
 
 / {
 	model = "NXP FRDM-MCXW71 board";
 
 	aliases {
 		led0 = &blue_led;
+		sw0 = &user_button_0;
 		blue-pwm-led = &blue_pwm_led;
 		green-pwm-led = &green_pwm_led;
 		red-pwm-led = &red_pwm_led;
@@ -28,6 +30,7 @@
 		zephyr,uart-pipe = &lpuart0;
 		zephyr,canbus = &flexcan0;
 		zephyr,uart-mcumgr = &lpuart0;
+		zephyr,bt-c2h-uart = &lpuart0;
 	};
 
 	user_led {
@@ -49,12 +52,26 @@
 			pwms = <&tpm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
 		};
 	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button_0: button_0 {
+			label = "User SW2";
+			gpios = <&gpioc 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_0>;
+			status = "okay";
+		};
+	};
 };
 
 &vref {
 	status = "okay";
 };
 
+&gpiob {
+	status = "okay";
+};
+
 &gpioc {
 	status = "okay";
 };
@@ -77,12 +94,40 @@
 	status = "okay";
 	pinctrl-0 = <&pinmux_lpi2c1>;
 	pinctrl-names = "default";
+
+	accelerometer: accelerometer@19 {
+		status = "okay";
+		compatible = "nxp,fxls8974";
+		reg = <0x19>;
+	};
 };
 
 &lpspi1 {
 	status = "okay";
 	pinctrl-0 = <&pinmux_lpspi1>;
 	pinctrl-names = "default";
+	pcs-sck-delay = <5>;
+	sck-pcs-delay = <5>;
+	transfer-delay = <125>;
+
+	mx25r6435fm2il0: flash@0 {
+		compatible = "jedec,spi-nor";
+		jedec-id = [c2 28 17];
+		reg = <0>;
+		/* only wp-gpio on default board configuration,
+		 * there is a reset gpio line but the line is
+		 * DNP by default on the board (R4 on schematic)
+		 */
+		wp-gpios = <&gpioc 0 GPIO_ACTIVE_LOW>;
+		size = <DT_SIZE_M(64)>;
+		has-dpd;
+		dpd-wakeup-sequence = <30000 20 35000>;
+		t-enter-dpd = <10000>;
+		/* this is the default (reset) mode for this flash */
+		mxicy,mx25r-power-mode = "low-power";
+		/* 8 MHz for low power mode */
+		spi-max-frequency = <8000000>;
+	};
 };
 
 &flash {
@@ -142,3 +187,7 @@
 	status = "okay";
 	wakeup-source;
 };
+
+&rtc {
+	status = "okay";
+};
diff --git a/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml b/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml
index 54cbe67d972..24b5be8c10f 100644
--- a/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml
+++ b/boards/nxp/frdm_mcxw71/frdm_mcxw71.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - can
diff --git a/boards/nxp/frdm_mcxw72/Kconfig.frdm_mcxw72 b/boards/nxp/frdm_mcxw72/Kconfig.frdm_mcxw72
new file mode 100644
index 00000000000..0d5844ca6b6
--- /dev/null
+++ b/boards/nxp/frdm_mcxw72/Kconfig.frdm_mcxw72
@@ -0,0 +1,6 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FRDM_MCXW72
+	select SOC_MCXW727C_CPU0 if BOARD_FRDM_MCXW72_MCXW727C_CPU0
+	select SOC_PART_NUMBER_MCXW727CMFTA
diff --git a/boards/nxp/frdm_mcxw72/board.cmake b/boards/nxp/frdm_mcxw72/board.cmake
new file mode 100644
index 00000000000..6282eec263b
--- /dev/null
+++ b/boards/nxp/frdm_mcxw72/board.cmake
@@ -0,0 +1,8 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(linkserver "--device=MCXW727C:MCX-W72-EVK")
+board_runner_args(jlink "--device=MCXW727" "--reset-after-load")
+
+include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/nxp/frdm_mcxw72/board.yml b/boards/nxp/frdm_mcxw72/board.yml
new file mode 100644
index 00000000000..f00b6125749
--- /dev/null
+++ b/boards/nxp/frdm_mcxw72/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: frdm_mcxw72
+  full_name: FRDM-MCXW72
+  vendor: nxp
+  socs:
+    - name: mcxw727c
diff --git a/boards/nxp/frdm_mcxw72/doc/frdm_mcxw72.webp b/boards/nxp/frdm_mcxw72/doc/frdm_mcxw72.webp
new file mode 100644
index 00000000000..993086e1c1a
Binary files /dev/null and b/boards/nxp/frdm_mcxw72/doc/frdm_mcxw72.webp differ
diff --git a/boards/nxp/frdm_mcxw72/doc/index.rst b/boards/nxp/frdm_mcxw72/doc/index.rst
new file mode 100644
index 00000000000..56f84381b1e
--- /dev/null
+++ b/boards/nxp/frdm_mcxw72/doc/index.rst
@@ -0,0 +1,136 @@
+.. zephyr:board:: frdm_mcxw72
+
+Overview
+********
+
+The FRDM-MCXW72
+
+The MCX W72x family features a 96 MHz Arm® Cortex®-M33 core coupled with a
+multiprotocol radio subsystem supporting Matter, Thread, Zigbee and
+Bluetooth LE. The independent radio subsystem, with a dedicated core and
+memory, offloads the main CPU, preserving it for the primary application and
+allowing firmware updates to support future wireless standards.
+
+Hardware
+********
+
+- MCXW72 Arm Cortex-M33 microcontroller running up to 96 MHz
+- 2MB on-chip Flash memory unit
+- 256 KB TCM RAM
+- On-board MCU-Link debugger with CMSIS-DAP
+
+For more information about the MCXW72 SoC and FRDM-MCXW72 board, see:
+
+- `MCXW72 SoC Website`_
+- `FRDM-MCXW72 Website`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Configuring a Debug Probe
+=========================
+
+A debug probe is used for both flashing and debugging the board. This board is
+configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
+
+Using LinkServer
+----------------
+
+Linkserver is the default runner for this board, and supports the factory
+default MCU-Link firmware. Follow the instructions in
+:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link
+firmware. This only needs to be done if the default onboard debug circuit
+firmware was changed. To put the board in ``DFU mode`` to program the firmware,
+short jumper JP5.
+
+Using J-Link
+------------
+
+There are two options. The onboard debug circuit can be updated with Segger
+J-Link firmware by following the instructions in
+:ref:`mcu-link-jlink-onboard-debug-probe`.
+To be able to program the firmware, you need to put the board in ``DFU mode``
+by shortening the jumper JP5.
+The second option is to attach a :ref:`jlink-external-debug-probe` to the
+10-pin SWD connector (J12) of the board.
+For both options use the ``-r jlink`` option with west to use the jlink runner.
+
+.. code-block:: console
+
+   west flash -r jlink
+
+Configuring a Console
+=====================
+
+Connect a USB cable from your PC to J14, and use the serial terminal of your choice
+(minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Flashing
+========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: frdm_mcxw72/mcxw727c/cpu0
+   :goals: flash
+
+Open a serial terminal, reset the board (press the RESET button), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v3.7.0-xxx-xxxx ***
+   Hello World! frdm_mcxw72/mcxw727c/cpu0
+
+Debugging
+=========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: frdm_mcxw72/mcxw727c/cpu0
+   :goals: debug
+
+Open a serial terminal, step through the application in your debugger, and you
+should see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v3.7.0-xxx-xxxx ***
+   Hello World! frdm_mcxw72/mcxw727c/cpu0
+
+Troubleshooting
+===============
+
+.. include:: ../../common/segger-ecc-systemview.rst
+   :start-after: segger-ecc-systemview
+
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
+References
+**********
+
+.. target-notes::
+
+.. _MCXW72 SoC Website:
+   https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-w-series-microcontrollers/mcx-w72x-secure-and-ultra-low-power-mcus-for-matter-thread-zigbee-and-bluetooth-le:MCX-W72X
+
+.. _FRDM-MCXW72 Website:
diff --git a/boards/nxp/frdm_mcxw72/frdm_mcxw72-pinctrl.dtsi b/boards/nxp/frdm_mcxw72/frdm_mcxw72-pinctrl.dtsi
new file mode 100644
index 00000000000..81d37051ec6
--- /dev/null
+++ b/boards/nxp/frdm_mcxw72/frdm_mcxw72-pinctrl.dtsi
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/mcx/MCXW727CMFTA-pinctrl.h>
+
+&pinctrl {
+	pinmux_lpuart0: pinmux_lpuart0 {
+		group0 {
+			pinmux = <LPUART0_RX_PTA16>, <LPUART0_TX_PTA17>;
+			drive-strength = "low";
+			slew-rate = "fast";
+		};
+	};
+
+	pinmux_lpuart1: pinmux_lpuart1 {
+		group0 {
+			pinmux = <LPUART1_RX_PTC2>, <LPUART1_TX_PTC3>;
+			drive-strength = "low";
+			slew-rate = "fast";
+		};
+	};
+
+	pinmux_tpm0: pinmux_tpm0 {
+		group0 {
+			pinmux = <TPM0_CH0_PTA21>, <TPM0_CH1_PTA20>,
+				<TPM0_CH2_PTA19>, <TPM0_CH3_PTA18>;
+			drive-strength = "low";
+			slew-rate = "fast";
+		};
+	};
+
+	pinmux_lpspi1: pinmux_lpspi1 {
+		group0 {
+			pinmux = <LPSPI1_SIN_PTB1>,
+				 <LPSPI1_SOUT_PTB3>;
+			slew-rate = "fast";
+			drive-strength = "low";
+		};
+	};
+
+	pinmux_flexcan: pinmux_flexcan {
+		group0 {
+			pinmux = <CAN0_RX_PTC5>, <CAN0_TX_PTC4>;
+			slew-rate = "slow";
+			drive-strength = "low";
+		};
+	};
+
+	pinmux_lpadc0: pinmux_lpadc0 {
+		group0 {
+			pinmux = <ADC0_A6_PTD2>,
+				<ADC0_B6_PTD3>,
+				<ADC0_B5_PTD1>;
+			drive-strength = "low";
+			slew-rate = "fast";
+		};
+	};
+
+	pinmux_lpi2c0: pinmux_lpi2c0 {
+		group0 {
+			pinmux = <LPI2C0_SCL_PTA19>,
+				<LPI2C0_SDA_PTA18>;
+			drive-strength = "low";
+			slew-rate = "fast";
+			drive-open-drain;
+		};
+	};
+
+	pinmux_lpi2c1: pinmux_lpi2c1 {
+		group0 {
+			pinmux = <LPI2C1_SCL_PTB5>,
+				<LPI2C1_SDA_PTB4>;
+			drive-strength = "low";
+			slew-rate = "fast";
+			drive-open-drain;
+		};
+	};
+};
diff --git a/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts
new file mode 100644
index 00000000000..b9981c6f9b3
--- /dev/null
+++ b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.dts
@@ -0,0 +1,158 @@
+/*
+ * Copyright 2024-2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_mcxw72.dtsi>
+#include "frdm_mcxw72-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "NXP FRDM-MCXW72 board";
+
+	aliases {
+		led0 = &blue_led;
+		blue-pwm-led = &blue_pwm_led;
+		green-pwm-led = &green_pwm_led;
+		red-pwm-led = &red_pwm_led;
+		sw0 = &user_button_0;
+	};
+
+	chosen {
+		zephyr,flash = &flash;
+		zephyr,flash-controller = &fmu;
+		zephyr,code-partition = &code_partition;
+		zephyr,sram = &stcm0;
+		zephyr,console = &lpuart1;
+		zephyr,shell-uart = &lpuart1;
+		zephyr,uart-pipe = &lpuart0;
+		zephyr,canbus = &flexcan0;
+		zephyr,bt-c2h-uart = &lpuart0;
+	};
+
+	user_led {
+		compatible = "gpio-leds";
+		blue_led: led {
+			gpios = <&gpioc 1 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+		blue_pwm_led: pwm_led_0 {
+			pwms = <&tpm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
+		};
+		green_pwm_led: pwm_led_1 {
+			pwms = <&tpm0 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
+		};
+		red_pwm_led: pwm_led_2 {
+			pwms = <&tpm0 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button_0: button_0 {
+			label = "User SW2";
+			gpios = <&gpioc 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_0>;
+			status = "okay";
+		};
+	};
+};
+
+&gpioa {
+	status = "okay";
+};
+
+&gpiob {
+	status = "okay";
+};
+
+&gpioc {
+	status = "okay";
+};
+
+&lpuart0 {
+	current-speed = <115200>;
+	status =  "okay";
+	pinctrl-0 = <&pinmux_lpuart0>;
+	pinctrl-names = "default";
+};
+
+&lpuart1 {
+	current-speed = <115200>;
+	status =  "okay";
+	pinctrl-0 = <&pinmux_lpuart1>;
+	pinctrl-names = "default";
+};
+
+&flash {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		code_partition: partition@0 {
+			reg = <0x0 DT_SIZE_K(2032)>;
+		};
+
+		storage_partition: partition@1FC000 {
+			reg = <0x1FC000 DT_SIZE_K(16)>;
+		};
+	};
+};
+
+&fmu {
+	status = "okay";
+};
+
+&tpm0 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_tpm0>;
+	pinctrl-names = "default";
+};
+
+&lptmr0 {
+	status = "okay";
+};
+
+&lpspi1 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_lpspi1>;
+	pinctrl-names = "default";
+};
+
+&flexcan0 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_flexcan>;
+	pinctrl-names = "default";
+
+	can-transceiver {
+		max-bitrate = <5000000>;
+	};
+};
+
+&vref {
+	status = "okay";
+};
+
+&adc0 {
+	pinctrl-0 = <&pinmux_lpadc0>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&lpi2c1 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_lpi2c1>;
+	pinctrl-names = "default";
+
+	accelerometer: accelerometer@19 {
+		status = "okay";
+		compatible = "nxp,fxls8974";
+		reg = <0x19>;
+	};
+};
diff --git a/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.yaml b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.yaml
new file mode 100644
index 00000000000..b41068a1c99
--- /dev/null
+++ b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0.yaml
@@ -0,0 +1,19 @@
+identifier: frdm_mcxw72/mcxw727c/cpu0
+name: NXP FRDM_MCXW72
+type: mcu
+arch: arm
+ram: 264
+flash: 2048
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - adc
+  - can
+  - counter
+  - gpio
+  - i2c
+  - pinctrl
+  - pwm
+  - spi
+  - uart
diff --git a/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0_defconfig b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0_defconfig
new file mode 100644
index 00000000000..19a6063f677
--- /dev/null
+++ b/boards/nxp/frdm_mcxw72/frdm_mcxw72_mcxw727c_cpu0_defconfig
@@ -0,0 +1,12 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_ARM_MPU=y
+CONFIG_TRUSTED_EXECUTION_SECURE=y
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y
diff --git a/boards/nxp/frdm_rw612/CMakeLists.txt b/boards/nxp/frdm_rw612/CMakeLists.txt
index a2a0b122735..74480e24ba9 100644
--- a/boards/nxp/frdm_rw612/CMakeLists.txt
+++ b/boards/nxp/frdm_rw612/CMakeLists.txt
@@ -1,15 +1,23 @@
 #
-# Copyright 2022-2023 NXP
+# Copyright 2022-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
 
+zephyr_library()
+zephyr_library_sources(init.c)
+
 if(CONFIG_NXP_RW6XX_BOOT_HEADER)
   zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024)
-  zephyr_library()
   # This FCB is specific to the flash on this board, it won't work
   # for boards with different flash chips. If you flash this FCB
   # onto a board with a different flash chip you may break it.
   # See MCUXpresso config tools for making a correct one.
   zephyr_library_sources(W25Q512JVFIQ_FCB.c)
 endif()
+
+if (CONFIG_DT_HAS_NXP_ENET_MAC_ENABLED AND CONFIG_XTAL32K)
+	message(FATAL_ERROR "Ethernet and external 32K clock source are "
+		"mutually exclusive on FRDM_RW612 due to shared PCB nets "
+		"between the ethernet PHY and the external oscillator")
+endif()
diff --git a/boards/nxp/frdm_rw612/Kconfig b/boards/nxp/frdm_rw612/Kconfig
new file mode 100644
index 00000000000..274f00c1db2
--- /dev/null
+++ b/boards/nxp/frdm_rw612/Kconfig
@@ -0,0 +1,5 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FRDM_RW612
+	select BOARD_EARLY_INIT_HOOK
diff --git a/boards/nxp/frdm_rw612/Kconfig.defconfig b/boards/nxp/frdm_rw612/Kconfig.defconfig
index 89d264de123..26d9acb9209 100644
--- a/boards/nxp/frdm_rw612/Kconfig.defconfig
+++ b/boards/nxp/frdm_rw612/Kconfig.defconfig
@@ -1,6 +1,6 @@
 # FRDM_RW612 board
 
-# Copyright 2024 NXP
+# Copyright 2024-25 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 if BOARD_FRDM_RW612
@@ -8,4 +8,28 @@ if BOARD_FRDM_RW612
 config NET_L2_ETHERNET
 	default y if DT_HAS_NXP_ENET_MAC_ENABLED && NETWORKING
 
+if LVGL
+
+# Enable DMA for LCDIC
+config MIPI_DBI_NXP_LCDIC_DMA
+	default y if MIPI_DBI
+
+# Increase descriptor count. LVGL will allocate a 30KB buffer,
+# and the SPI driver sets up RX and TX side. Since LPC DMA has
+# 1KB limit per descriptor, we need 60
+config DMA_MCUX_LPC_NUMBER_OF_DESCRIPTORS
+	default 60
+
+config LV_Z_FLUSH_THREAD
+	default y
+
+endif # LVGL
+
+if COUNTER_MCUX_LPC_RTC_1HZ
+
+config XTAL32K
+	default y
+
+endif # COUNTER_MCUX_LPC_RTC_1HZ
+
 endif # BOARD_FRDM_RW612
diff --git a/boards/nxp/frdm_rw612/doc/index.rst b/boards/nxp/frdm_rw612/doc/index.rst
index a1a9b7dc817..a45d32d4cda 100644
--- a/boards/nxp/frdm_rw612/doc/index.rst
+++ b/boards/nxp/frdm_rw612/doc/index.rst
@@ -23,72 +23,17 @@ Hardware
 Supported Features
 ==================
 
-+-----------+------------+-----------------------------------+
-| Interface | Controller | Driver/Component                  |
-+===========+============+===================================+
-| NVIC      | on-chip    | nested vector interrupt controller|
-+-----------+------------+-----------------------------------+
-| SYSTICK   | on-chip    | systick                           |
-+-----------+------------+-----------------------------------+
-| MCI_IOMUX | on-chip    | pinmux                            |
-+-----------+------------+-----------------------------------+
-| GPIO      | on-chip    | gpio                              |
-+-----------+------------+-----------------------------------+
-| USART     | on-chip    | serial                            |
-+-----------+------------+-----------------------------------+
-| DMA       | on-chip    | dma                               |
-+-----------+------------+-----------------------------------+
-| SPI       | on-chip    | spi                               |
-+-----------+------------+-----------------------------------+
-| I2C       | on-chip    | i2c                               |
-+-----------+------------+-----------------------------------+
-| TRNG      | on-chip    | entropy                           |
-+-----------+------------+-----------------------------------+
-| WWDT      | on-chip    | watchdog                          |
-+-----------+------------+-----------------------------------+
-| USBOTG    | on-chip    | usb                               |
-+-----------+------------+-----------------------------------+
-| CTIMER    | on-chip    | counter                           |
-+-----------+------------+-----------------------------------+
-| SCTIMER   | on-chip    | pwm                               |
-+-----------+------------+-----------------------------------+
-| MRT       | on-chip    | counter                           |
-+-----------+------------+-----------------------------------+
-| OS_TIMER  | on-chip    | os timer                          |
-+-----------+------------+-----------------------------------+
-| PM        | on-chip    | power management; uses SoC Power  |
-|           |            | Modes 1 and 2                     |
-+-----------+------------+-----------------------------------+
-| BLE       | on-chip    | Bluetooth                         |
-+-----------+------------+-----------------------------------+
-| ADC       | on-chip    | adc                               |
-+-----------+------------+-----------------------------------+
-| DAC       | on-chip    | dac                               |
-+-----------+------------+-----------------------------------+
-| ENET      | on-chip    | ethernet                          |
-+-----------+------------+-----------------------------------+
-| Wi-Fi     | on-chip    | Wi-Fi                             |
-+-----------+------------+-----------------------------------+
-
-The default configuration can be found in the defconfig file:
-
-   :zephyr_file:`boards/nxp/frdm_rw612/frdm_rw612_defconfig`
-
-Other hardware features are not currently supported
+.. zephyr:board-supported-hw::
 
-Fetch Binary Blobs
-******************
-
-To support Bluetooth or Wi-Fi, frdm_rw612 requires fetching binary blobs, which can be
-achieved by running the following command:
+.. note::
 
-.. code-block:: console
-
-   west blobs fetch hal_nxp
+   Power modes 1, 2 and 3 are supported when using System Power Management.
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -147,6 +92,34 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS zephyr-v3.6.0 *****
    Hello World! frdm_rw612
 
+SRAM Bus Access Partitioning
+****************************
+
+RW612 supports shared access of the SRAM from both the code bus and data bus.
+The bus used to access the SRAM is determined using two separate memory mapped address spaces.
+The application can configure the partitioning of the SRAM access regions by a devicetree overlay.
+For example, below is part of an overlay to change the whole SRAM to be used for data.
+
+.. code-block:: devicetree
+
+   &sram_data {
+        reg = <0x0 DT_SIZE_K(1216)>;
+   };
+
+
+Wireless Connectivity Support
+*****************************
+
+Fetch Binary Blobs
+==================
+
+To support Bluetooth or Wi-Fi, frdm_rw612 requires fetching binary blobs, which can be
+achieved by running the following command:
+
+.. code-block:: console
+
+   west blobs fetch hal_nxp
+
 Bluetooth
 =========
 
@@ -167,8 +140,22 @@ frdm_rw612 platform supports the monolithic feature. The required binary blob
 ``<zephyr workspace>/modules/hal/nxp/zephyr/blobs/rw61x_sb_wifi_a2.bin`` will be linked
 with the application image directly, forming one single monolithic image.
 
+RTC Sub-Second Counter
+======================
+
+To use the RTC sub-second counter which is clocked at a 32kHZ rate, make the
+following modifications to the board hardware:
+
+1. Move the short on SJ21 from 1 and 2 to short 2 and 3.
+2. Move the short on SJ22 from 1 and 2 to short 2 and 3.
+
+After this change, the ENET will stop functioning on the board.
+
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 Resources
-=========
+*********
 
 .. _RW612 Website:
    https://www.nxp.com/products/wireless-connectivity/wi-fi-plus-bluetooth-plus-802-15-4/wireless-mcu-with-integrated-tri-radiobr1x1-wi-fi-6-plus-bluetooth-low-energy-5-3-802-15-4:RW612
diff --git a/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi b/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi
index 12ecaa90f40..b54f0aa7e91 100644
--- a/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi
+++ b/boards/nxp/frdm_rw612/frdm_rw612-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022-2024 NXP
+ * Copyright 2022-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -60,4 +60,23 @@
 			slew-rate = "normal";
 		};
 	};
+
+	pinmux_lcdic: pinmux_lcdic {
+		group0 {
+			pinmux = <IO_MUX_LCD_SPI_IO44
+				IO_MUX_LCD_SPI_IO45
+				IO_MUX_LCD_SPI_IO46
+				IO_MUX_LCD_SPI_IO47
+				IO_MUX_LCD_SPI_IO48
+				IO_MUX_LCD_SPI_IO49>;
+			slew-rate = "ultra";
+		};
+	};
+
+	pinmux_flexcomm1_i2s: pinmux_flexcomm1_i2s {
+		group0 {
+			pinmux = <IO_MUX_FC1_I2S>;
+			slew-rate = "normal";
+		};
+	};
 };
diff --git a/boards/nxp/frdm_rw612/frdm_rw612.yaml b/boards/nxp/frdm_rw612/frdm_rw612.yaml
index 0ad00472dc2..59697fc6cbf 100644
--- a/boards/nxp/frdm_rw612/frdm_rw612.yaml
+++ b/boards/nxp/frdm_rw612/frdm_rw612.yaml
@@ -1,5 +1,5 @@
 #
-# Copyright 2022-2024 NXP
+# Copyright 2022-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 960
 flash: 65536
 supported:
@@ -19,6 +18,7 @@ supported:
   - dma
   - spi
   - i2c
+  - i2s
   - entropy
   - usb_device
   - watchdog
diff --git a/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi b/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi
index 2f496ca7796..cf039cd59e7 100644
--- a/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi
+++ b/boards/nxp/frdm_rw612/frdm_rw612_common.dtsi
@@ -1,10 +1,11 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include "frdm_rw612-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
 
 / {
 	model = "nxp,frdm_rw612";
@@ -15,6 +16,8 @@
 		usart-0 = &flexcomm3;
 		i2c-0 = &flexcomm2;
 		pwm-0 = &sctimer;
+		sw0 = &user_button_0;
+		ambient-temp0 = &p3t1755;
 	};
 
 	chosen {
@@ -22,14 +25,36 @@
 		zephyr,flash = &w25q512jvfiq;
 		zephyr,console = &flexcomm3;
 		zephyr,shell-uart = &flexcomm3;
+		zephyr,flash-controller = &w25q512jvfiq;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,uart-mcumgr = &flexcomm3;
 	};
 
 	leds {
 		compatible = "gpio-leds";
 		green_led: led_1 {
-			gpios = <&hsgpio0 12 0>;
+			gpios = <&hsgpio0 12 GPIO_ACTIVE_LOW>;
 		};
 	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button_0: button_0 {
+			label = "User SW2";
+			gpios = <&hsgpio0 11 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_0>;
+			status = "okay";
+		};
+	};
+
+	nxp_lcd_pmod_connector: lcd-pmod-connector {
+		compatible = "nxp,lcd-pmod";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xfffffff0>;
+		gpio-map-pass-thru = <0 0xf>;
+		gpio-map = <10  0 &hsgpio1 12 0>,  /* Pin 10, LCD and touch reset */
+			   <12  0 &hsgpio0 18 0>;  /* Pin 11, LCD touch INT */
+	};
 };
 
 &flexcomm3 {
@@ -172,6 +197,7 @@
 &os_timer {
 	status = "okay";
 	wakeup-source;
+	deep-sleep-counter = <&rtc_highres>;
 };
 
 &systick {
@@ -192,6 +218,12 @@
 	pinctrl-names = "default";
 };
 
+/* RTC is the wakeup source for PM modes 3,4 */
+&rtc_highres {
+	status = "okay";
+	wakeup-source;
+};
+
 &nbu {
 	status = "okay";
 	wakeup-source;
@@ -224,4 +256,20 @@ arduino_i2c: &flexcomm2 {
 	#size-cells = <0>;
 	pinctrl-0 = <&pinmux_flexcomm2_i2c>;
 	pinctrl-names = "default";
+
+	p3t1755: p3t1755@48 {
+		compatible = "nxp,p3t1755";
+		reg = <0x48>;
+		status = "okay";
+	};
+};
+
+zephyr_mipi_dbi_spi: &lcdic {
+	status = "okay";
+	pinctrl-0 = <&pinmux_lcdic>;
+	pinctrl-names = "default";
+};
+
+nxp_pmod_touch_panel_i2c: &arduino_i2c {
+	status = "okay";
 };
diff --git a/boards/nxp/frdm_rw612/init.c b/boards/nxp/frdm_rw612/init.c
new file mode 100644
index 00000000000..44c05ad3efe
--- /dev/null
+++ b/boards/nxp/frdm_rw612/init.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2022, 2024-25 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/pm/pm.h>
+#include <fsl_power.h>
+#include <fsl_common.h>
+
+static void frdm_rw612_power_init_config(void)
+{
+	power_init_config_t initCfg = {
+		/* VCORE AVDD18 supplied from iBuck on FRDM board. */
+		.iBuck = true,
+		/* CAU_SOC_SLP_REF_CLK is needed for LPOSC. */
+		.gateCauRefClk = false,
+	};
+
+	POWER_InitPowerConfig(&initCfg);
+}
+
+#if CONFIG_PM
+static void frdm_rw612_pm_state_exit(enum pm_state state)
+{
+	switch (state) {
+	case PM_STATE_STANDBY:
+		frdm_rw612_power_init_config();
+		break;
+	default:
+		break;
+	}
+}
+#endif
+
+void board_early_init_hook(void)
+{
+	frdm_rw612_power_init_config();
+
+#if CONFIG_PM
+	static struct pm_notifier frdm_rw612_pm_notifier = {
+		.state_exit = frdm_rw612_pm_state_exit,
+	};
+
+	pm_notifier_register(&frdm_rw612_pm_notifier);
+#endif
+
+#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES
+	/*
+	 * Eventually this code should not be here
+	 * but should be configured by some SYSCTL node
+	 */
+
+	/* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm1 */
+	SYSCTL1->SHAREDCTRLSET[0] = SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL(1) |
+				SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL(1);
+
+	/* Select Data in from Transmit I2S - Flexcomm 1 */
+	SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL(1);
+	/* Enable Transmit I2S - Flexcomm 1 for Shared Data Out */
+	SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN(1);
+
+	/* Set Receive I2S - Flexcomm 0 SCK, WS from shared signal set 0 */
+	SYSCTL1->FCCTRLSEL[0] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |
+				SYSCTL1_FCCTRLSEL_WSINSEL(1);
+
+	/* Set Transmit I2S - Flexcomm 1 SCK, WS from shared signal set 0 */
+	SYSCTL1->FCCTRLSEL[1] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |
+				SYSCTL1_FCCTRLSEL_WSINSEL(1);
+
+	/* Select Receive I2S - Flexcomm 0 Data in from shared signal set 0 */
+	SYSCTL1->FCCTRLSEL[0] |= SYSCTL1_FCCTRLSEL_DATAINSEL(1);
+	/* Select Transmit I2S - Flexcomm 1 Data out to shared signal set 0 */
+	SYSCTL1->FCCTRLSEL[1] |= SYSCTL1_FCCTRLSEL_DATAOUTSEL(1);
+#endif /* CONFIG_I2S_TEST_SEPARATE_DEVICES */
+}
diff --git a/boards/nxp/hexiwear/doc/index.rst b/boards/nxp/hexiwear/doc/index.rst
index 6f47bddf00d..225921966ca 100644
--- a/boards/nxp/hexiwear/doc/index.rst
+++ b/boards/nxp/hexiwear/doc/index.rst
@@ -501,6 +501,9 @@ you should see the following message in the terminal:
    ***** Booting Zephyr OS v1.14.0-rc1 *****
    Hello World! hexiwear
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _KW40Z Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/w-serieswireless-conn.m0-plus-m4/kinetis-kw40z-2.4-ghz-dual-mode-ble-and-802.15.4-wireless-radio-microcontroller-mcu-based-on-arm-cortex-m0-plus-core:KW40Z
 
diff --git a/boards/nxp/hexiwear/hexiwear_mk64f12.yaml b/boards/nxp/hexiwear/hexiwear_mk64f12.yaml
index ecf1aa1b8aa..f545c591d96 100644
--- a/boards/nxp/hexiwear/hexiwear_mk64f12.yaml
+++ b/boards/nxp/hexiwear/hexiwear_mk64f12.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - ble
diff --git a/boards/nxp/hexiwear/hexiwear_mkw40z4.yaml b/boards/nxp/hexiwear/hexiwear_mkw40z4.yaml
index af4d8d5220d..e0e49ea82e9 100644
--- a/boards/nxp/hexiwear/hexiwear_mkw40z4.yaml
+++ b/boards/nxp/hexiwear/hexiwear_mkw40z4.yaml
@@ -7,7 +7,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 testing:
   ignore_tags:
     - net
diff --git a/boards/nxp/imx8mm_evk/doc/index.rst b/boards/nxp/imx8mm_evk/doc/index.rst
index 6984f06a8e6..3c2a8540aba 100644
--- a/boards/nxp/imx8mm_evk/doc/index.rst
+++ b/boards/nxp/imx8mm_evk/doc/index.rst
@@ -42,56 +42,11 @@ More information about the board can be found at the
 Supported Features
 ==================
 
-The Zephyr imx8mm_evk board for Cortex-A53 configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| GIC-v3    | on-chip    | interrupt controller                |
-+-----------+------------+-------------------------------------+
-| ARM TIMER | on-chip    | system clock                        |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| RDC       | on-chip    | Resource Domain Controller          |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| GPT       | on-chip    | timer                               |
-+-----------+------------+-------------------------------------+
-| ENET      | on-chip    | ethernet port                       |
-+-----------+------------+-------------------------------------+
-
-The Zephyr imx8mm_evk board for Cortex-M4 supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | GPIO output                         |
-|           |            | GPIO input                          |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4_defconfig`
-
-It is recommended to disable peripherals used by the M4 core on the Linux host.
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   It is recommended to disable peripherals used by the M4 core on the Linux host.
 
 Devices
 ========
@@ -111,6 +66,8 @@ CPU's UART4. This is used for the M4 and A53 core targets.
 Programming and Debugging (A53)
 *******************************
 
+.. zephyr:board-supported-runners::
+
 U-Boot "cpu" command is used to load and kick Zephyr to Cortex-A secondary Core, Currently
 it is supported in : `Real-Time Edge U-Boot`_ (use the branch "uboot_vxxxx.xx-y.y.y,
 xxxx.xx is uboot version and y.y.y is Real-Time Edge Software version, for example
@@ -245,8 +202,8 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS build zephyr-v2.0.0-1859-g292afe8533c0 *****
    Hello World! imx8mm_evk
 
-References
-==========
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
 
 .. _NXP website:
    https://www.nxp.com/design/development-boards/i.mx-evaluation-and-development-boards/evaluation-kit-for-thebr-i.mx-8m-mini-applications-processor:8MMINILPD4-EVK
diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk-pinctrl.dtsi b/boards/nxp/imx8mm_evk/imx8mm_evk-pinctrl.dtsi
index 9dff995dd9d..b3f7251becc 100644
--- a/boards/nxp/imx8mm_evk/imx8mm_evk-pinctrl.dtsi
+++ b/boards/nxp/imx8mm_evk/imx8mm_evk-pinctrl.dtsi
@@ -63,4 +63,16 @@
 			drive-strength = "x6";
 		};
 	};
+
+	pinmux_i2c3: pinmux_i2c3 {
+		group0 {
+			pinmux = <&iomuxc_i2c3_scl_i2c_scl_i2c3_scl>,
+				<&iomuxc_i2c3_sda_i2c_sda_i2c3_sda>;
+			bias-pull-up;
+			input-schmitt-enable;
+			slew-rate = "slow";
+			drive-strength = "x4";
+			input-enable;
+		};
+	};
 };
diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts
index 13213ee010c..4f1d71902af 100644
--- a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts
+++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.dts
@@ -6,6 +6,8 @@
 
 /dts-v1/;
 
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
 #include <nxp/nxp_mimx8mm_a53.dtsi>
 #include "imx8mm_evk-pinctrl.dtsi"
 
@@ -67,3 +69,23 @@
 	pinctrl-names = "default";
 	status = "okay";
 };
+
+&gpio1 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_i2c3>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+
+	gpio_exp1: pca6416@20 {
+		compatible = "nxp,pca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-gpios = <&gpio1 12 (GPIO_ACTIVE_LOW|GPIO_PULL_UP)>;
+		status = "okay";
+	};
+};
diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.yaml b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.yaml
index 4132df2e1f6..4b60037a0a6 100644
--- a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.yaml
+++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_a53.yaml
@@ -1,5 +1,5 @@
 #
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -15,6 +15,8 @@ ram: 1024
 supported:
   - uart
   - net
+  - gpio
+  - i2c
 testing:
   ignore_tags:
     - bluetooth
diff --git a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.yaml b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.yaml
index 9ae6cadff5d..44c9ea57cde 100644
--- a/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.yaml
+++ b/boards/nxp/imx8mm_evk/imx8mm_evk_mimx8mm6_m4.yaml
@@ -14,7 +14,6 @@ flash: 128
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 testing:
   ignore_tags:
     - net
diff --git a/boards/nxp/imx8mn_evk/doc/index.rst b/boards/nxp/imx8mn_evk/doc/index.rst
index 265c30be41c..3102e2a159b 100644
--- a/boards/nxp/imx8mn_evk/doc/index.rst
+++ b/boards/nxp/imx8mn_evk/doc/index.rst
@@ -42,28 +42,7 @@ More information about the board can be found at the
 Supported Features
 ==================
 
-The Zephyr mimx8mn_evk board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| GIC-v3    | on-chip    | interrupt controller                |
-+-----------+------------+-------------------------------------+
-| ARM TIMER | on-chip    | system clock                        |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| RDC       | on-chip    | Resource Domain Controller          |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| GPT       | on-chip    | timer                               |
-+-----------+------------+-------------------------------------+
-| ENET      | on-chip    | ethernet port                       |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Devices
 ========
@@ -81,6 +60,8 @@ CPU's UART4.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 U-Boot "cpu" command is used to load and kick Zephyr to Cortex-A secondary Core, Currently
 it has been supported in latest U-Boot version by `patch serials`_.
 
@@ -134,8 +115,8 @@ Use Jailhouse hypervisor, after root cell linux is up:
     #jailhouse cell load 1 zephyr.bin -a 0x93c00000
     #jailhouse cell start 1
 
-References
-==========
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
 
 .. _NXP website:
    https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-nano-applications-processor:8MNANOD4-EVK
diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk-pinctrl.dtsi b/boards/nxp/imx8mn_evk/imx8mn_evk-pinctrl.dtsi
index 23326b53f8f..edc00e207a5 100644
--- a/boards/nxp/imx8mn_evk/imx8mn_evk-pinctrl.dtsi
+++ b/boards/nxp/imx8mn_evk/imx8mn_evk-pinctrl.dtsi
@@ -63,4 +63,16 @@
 			drive-strength = "x6";
 		};
 	};
+
+	pinmux_i2c3: pinmux_i2c3 {
+		group0 {
+			pinmux = <&iomuxc_i2c3_scl_i2c_scl_i2c3_scl>,
+				<&iomuxc_i2c3_sda_i2c_sda_i2c3_sda>;
+			bias-pull-up;
+			input-schmitt-enable;
+			slew-rate = "slow";
+			drive-strength = "x4";
+			input-enable;
+		};
+	};
 };
diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts
index 60ab0ae04ed..e1b3d4ec286 100644
--- a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts
+++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.dts
@@ -6,6 +6,8 @@
 
 /dts-v1/;
 
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
 #include <nxp/nxp_mimx8mn_a53.dtsi>
 #include "imx8mn_evk-pinctrl.dtsi"
 
@@ -67,3 +69,23 @@
 	pinctrl-names = "default";
 	status = "okay";
 };
+
+&gpio1 {
+	status = "okay";
+};
+
+&i2c3 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_i2c3>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+
+	gpio_exp1: pca6416@20 {
+		compatible = "nxp,pca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-gpios = <&gpio1 12 (GPIO_ACTIVE_LOW|GPIO_PULL_UP)>;
+		status = "okay";
+	};
+};
diff --git a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.yaml b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.yaml
index a4a5dd0b50a..7d50419b06a 100644
--- a/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.yaml
+++ b/boards/nxp/imx8mn_evk/imx8mn_evk_mimx8mn6_a53.yaml
@@ -1,5 +1,5 @@
 #
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -15,6 +15,8 @@ ram: 1024
 supported:
   - uart
   - net
+  - gpio
+  - i2c
 testing:
   ignore_tags:
     - bluetooth
diff --git a/boards/nxp/imx8mp_evk/doc/index.rst b/boards/nxp/imx8mp_evk/doc/index.rst
index 7afafb33593..70f14700813 100644
--- a/boards/nxp/imx8mp_evk/doc/index.rst
+++ b/boards/nxp/imx8mp_evk/doc/index.rst
@@ -42,44 +42,7 @@ More information about the board can be found at the
 Supported Features
 ==================
 
-The Zephyr mimx8mp_evk_a53 board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| GIC-v3    | on-chip    | interrupt controller                |
-+-----------+------------+-------------------------------------+
-| ARM TIMER | on-chip    | system clock                        |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| RDC       | on-chip    | Resource Domain Controller          |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| ENET      | on-chip    | ethernet port                       |
-+-----------+------------+-------------------------------------+
-
-The Zephyr mimx8mp_evk_m7 board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Devices
 ========
@@ -99,6 +62,8 @@ CPU's UART4.
 Programming and Debugging (A53)
 *******************************
 
+.. zephyr:board-supported-runners::
+
 U-Boot "cpu" command is used to load and kick Zephyr to Cortex-A secondary Core, Currently
 it is supported in : `Real-Time Edge U-Boot`_ (use the branch "uboot_vxxxx.xx-y.y.y,
 xxxx.xx is uboot version and y.y.y is Real-Time Edge Software version, for example
@@ -319,8 +284,8 @@ should see the following message in the terminal:
    *** Booting Zephyr OS build v2.7.99-1310-g2801bf644a91  ***
    Hello World! imx8mp_evk
 
-References
-==========
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
 
 .. _NXP website:
    https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-plus-applications-processor:8MPLUSLPD4-EVK
diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi b/boards/nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi
index f88555b13e2..dd9346bc19c 100644
--- a/boards/nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi
+++ b/boards/nxp/imx8mp_evk/imx8mp_evk-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022-2024 NXP
+ * Copyright 2022-2025 NXP
  * SPDX-License-Identifier: Apache-2.0
  *
  */
@@ -7,6 +7,34 @@
 #include <nxp/nxp_imx/mimx8ml8dvnlz-pinctrl.dtsi>
 
 &pinctrl {
+	sai3_default: sai3_default {
+		group0 {
+			pinmux = <&iomuxc_sai3_txfs_sai_tx_sync_sai3_tx_sync>,
+				 <&iomuxc_sai3_txc_sai_tx_bclk_sai3_tx_bclk>,
+				 <&iomuxc_sai3_rxd_sai_rx_data_sai3_rx_data0>,
+				 <&iomuxc_sai3_txd_sai_tx_data_sai3_tx_data0>,
+				 <&iomuxc_sai3_mclk_sai_mclk_sai3_mclk>;
+			bias-pull-up;
+			slew-rate = "fast";
+			drive-strength = "x6";
+			input-schmitt-enable;
+		};
+	};
+
+	pdm_default: pdm_default {
+		group0 {
+			pinmux = <&iomuxc_sai5_rxc_pdm_clk_pdm_clk>,
+				 <&iomuxc_sai5_rxd0_pdm_bit_stream_pdm_bit_stream0>,
+				 <&iomuxc_sai5_rxd1_pdm_bit_stream_pdm_bit_stream1>,
+				 <&iomuxc_sai5_rxd2_pdm_bit_stream_pdm_bit_stream2>,
+				 <&iomuxc_sai5_rxd3_pdm_bit_stream_pdm_bit_stream3>;
+			bias-pull-up;
+			slew-rate = "fast";
+			drive-strength = "x6";
+			input-schmitt-enable;
+		};
+	};
+
 	uart2_default: uart2_default {
 		group0 {
 			pinmux = <&iomuxc_uart2_rxd_uart_rx_uart2_rx>,
@@ -66,4 +94,16 @@
 			drive-strength = "x1";
 		};
 	};
+
+	pinmux_i2c3: pinmux_i2c3 {
+		group0 {
+			pinmux = <&iomuxc_i2c3_scl_i2c_scl_i2c3_scl>,
+				<&iomuxc_i2c3_sda_i2c_sda_i2c3_sda>;
+			bias-pull-up;
+			input-schmitt-enable;
+			slew-rate = "slow";
+			drive-strength = "x4";
+			input-enable;
+		};
+	};
 };
diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts
index c50173e3f3a..01dd37b68c2 100644
--- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts
+++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.dts
@@ -1,11 +1,13 @@
 /*
- * Copyright 2021-2024 NXP
+ * Copyright 2021-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 /dts-v1/;
 
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
 #include <nxp/nxp_mimx8mp_a53.dtsi>
 #include "imx8mp_evk-pinctrl.dtsi"
 
@@ -69,3 +71,23 @@
 	pinctrl-0 = <&uart4_default>;
 	pinctrl-names = "default";
 };
+
+&i2c3 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_i2c3>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+
+	gpio_exp1: pca6416@20 {
+		compatible = "nxp,pca6416";
+		reg = <0x20>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-gpios = <&gpio1 12 (GPIO_ACTIVE_LOW|GPIO_PULL_UP)>;
+		status = "okay";
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml
index dff021eab7e..bbacbcfd9fd 100644
--- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml
+++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_a53.yaml
@@ -1,5 +1,5 @@
 #
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -15,6 +15,8 @@ ram: 1024
 supported:
   - uart
   - net
+  - gpio
+  - i2c
 testing:
   ignore_tags:
     - bluetooth
diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp.dts b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp.dts
index dc8c0ab48a5..bf84ad41c5f 100644
--- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp.dts
+++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_adsp.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2021, 2023, 2024 NXP
+ * Copyright 2021, 2023-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,7 +7,7 @@
 /dts-v1/;
 
 #include <nxp/nxp_imx8m.dtsi>
-#include <nxp/nxp_imx/mimx8ml8dvnlz-pinctrl.dtsi>
+#include "imx8mp_evk-pinctrl.dtsi"
 
 / {
 	model = "NXP i.MX 8MPLUS Audio DSP";
@@ -21,16 +21,14 @@
 	};
 };
 
-&pinctrl {
-	uart4_default: uart4_default {
-		group0 {
-			pinmux = <&iomuxc_uart4_rxd_uart_rx_uart4_rx>,
-				<&iomuxc_uart4_txd_uart_tx_uart4_tx>;
-			bias-pull-up;
-			slew-rate = "slow";
-			drive-strength = "x1";
-		};
-	};
+&micfil {
+	pinctrl-0 = <&pdm_default>;
+	pinctrl-names = "default";
+};
+
+&sai3 {
+	pinctrl-0 = <&sai3_default>;
+	pinctrl-names = "default";
 };
 
 &uart4 {
diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml
index 799c88b4fb3..bd9c5588ac2 100644
--- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml
+++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7.yaml
@@ -13,7 +13,6 @@ flash: 128
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 testing:
   ignore_tags:
     - net
diff --git a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml
index f76568a30d7..9f841e668b2 100644
--- a/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml
+++ b/boards/nxp/imx8mp_evk/imx8mp_evk_mimx8ml8_m7_ddr.yaml
@@ -13,7 +13,6 @@ flash: 2048
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 testing:
   ignore_tags:
     - net
diff --git a/boards/nxp/imx8mq_evk/doc/index.rst b/boards/nxp/imx8mq_evk/doc/index.rst
index 6022aeb6667..fe3e417321b 100644
--- a/boards/nxp/imx8mq_evk/doc/index.rst
+++ b/boards/nxp/imx8mq_evk/doc/index.rst
@@ -40,28 +40,7 @@ More information about the board can be found at the
 Supported Features
 ==================
 
-The Zephyr mimx8mq_evk board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4_defconfig`.
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -91,6 +70,8 @@ the remaining are not used/tested.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The MIMX8MQ EVK board doesn't have QSPI flash for the M4 and it needs
 to be started by the A53 core. The A53 core is responsible to load the M4 binary
 application into the RAM, put the M4 in reset, set the M4 Program Counter and
@@ -198,8 +179,8 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS build zephyr-v2.6.99-30942-g6ee70bd22058 *****
    Hello World! imx8mq_evk
 
-References
-==========
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
 
 .. _NXP website:
    https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/evaluation-kit-for-the-i-mx-8m-applications-processor:MCIMX8M-EVK
diff --git a/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.yaml b/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.yaml
index acb8e15d8a5..69d3f77231f 100644
--- a/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.yaml
+++ b/boards/nxp/imx8mq_evk/imx8mq_evk_mimx8mq6_m4.yaml
@@ -13,7 +13,6 @@ flash: 128
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 testing:
   ignore_tags:
     - net
diff --git a/boards/nxp/imx91_evk/Kconfig.imx91_evk b/boards/nxp/imx91_evk/Kconfig.imx91_evk
new file mode 100644
index 00000000000..6bfc897688e
--- /dev/null
+++ b/boards/nxp/imx91_evk/Kconfig.imx91_evk
@@ -0,0 +1,6 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_IMX91_EVK
+	select SOC_MIMX9131
+	select SOC_PART_NUMBER_MIMX9131CVVXJ
diff --git a/boards/nxp/imx91_evk/board.yml b/boards/nxp/imx91_evk/board.yml
new file mode 100644
index 00000000000..8912c7df530
--- /dev/null
+++ b/boards/nxp/imx91_evk/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: imx91_evk
+  full_name: i.MX91 EVK
+  vendor: nxp
+  socs:
+  - name: mimx9131
diff --git a/boards/nxp/imx91_evk/doc/index.rst b/boards/nxp/imx91_evk/doc/index.rst
new file mode 100644
index 00000000000..be734dfb1ce
--- /dev/null
+++ b/boards/nxp/imx91_evk/doc/index.rst
@@ -0,0 +1,108 @@
+.. zephyr:board:: imx91_evk
+
+Overview
+********
+
+The i.MX 91 Evaluation Kit (MCIMX91-EVK board) is a platform designed
+to display the most commonly used features of the i.MX 91 applications
+processor. The MCIMX91-EVK board is an entry-level development board
+with a small and low-cost package. The board can be used by developers
+to get familiar with the processor before investing a large amount of
+resources in more specific designs.
+
+The i.MX 91 applications processor features an Arm Cortex-A55 core
+that can operate at speeds of up to 1.4 GHz.
+
+- Board features:
+
+  - RAM: 2GB LPDDR4
+  - Storage:
+
+    - SanDisk 16GB eMMC5.1
+    - microSD Socket
+  - Wireless:
+
+    - Murata Type-2EL (SDIO+UART+SPI) module. It is based on NXP IW612 SoC,
+      which supports dual-band (2.4 GHz /5 GHz) 1x1 Wi-Fi 6, Bluetooth 5.2,
+      and 802.15.4
+  - USB:
+
+    - Two USB 2.0 Type C connectors
+  - Ethernet:
+
+    - ENET: 10/100/1000 Mbit/s RGMII Ethernet connected with external PHY
+      RTL8211
+    - ENET_QoS: 10/100/1000 Mbit/s RGMII Ethernet supporting TSN connected
+      with external PHY RTL8211
+  - PCIe:
+
+    - One M.2/NGFF Key E mini card 75-pin connector
+  - Connectors:
+
+    - 40-Pin Dual Row Header
+  - LEDs:
+
+    - 1x Power status LED
+    - 2x UART LED
+  - Debug:
+
+    - JTAG 20-pin connector
+    - MicroUSB for UART debug
+
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Devices
+========
+System Clock
+------------
+
+This board configuration uses a system clock frequency of 24 MHz.
+Cortex-A55 Core runs up to 1.4 GHz.
+
+Serial Port
+-----------
+
+This board configuration uses a single serial communication channel with the
+CPU's UART1 for A55 core.
+
+Programming and Debugging
+*******************************
+
+U-Boot "go" command is used to load and kick Zephyr to Cortex-A55 Core.
+
+Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and
+plug the SD card into the board. Power it up and stop the u-boot execution at
+prompt.
+
+Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core:
+
+.. code-block:: console
+
+    fatload mmc 1:1 0x80000000 zephyr.bin; dcache flush; icache flush; go 0x80000000
+
+Use this configuration to run basic Zephyr applications and kernel tests,
+for example, with the :zephyr:code-sample:`synchronization` sample:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/synchronization
+   :host-os: unix
+   :board: imx91_evk/mimx9131
+   :goals: build
+
+This will build an image with the synchronization sample app, boot it and
+display the following console output:
+
+.. code-block:: console
+
+    *** Booting Zephyr OS build v4.0.0-3277-g69f43115c9a8 ***
+    thread_a: Hello World from cpu 0 on imx91_evk!
+    thread_b: Hello World from cpu 0 on imx91_evk!
+    thread_a: Hello World from cpu 0 on imx91_evk!
+    thread_b: Hello World from cpu 0 on imx91_evk!
+
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
diff --git a/boards/nxp/imx91_evk/imx91_evk-pinctrl.dtsi b/boards/nxp/imx91_evk/imx91_evk-pinctrl.dtsi
new file mode 100644
index 00000000000..94d9f0f7f91
--- /dev/null
+++ b/boards/nxp/imx91_evk/imx91_evk-pinctrl.dtsi
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#include <nxp/nxp_imx/mimx9131cvvxj-pinctrl.dtsi>
+
+&pinctrl {
+	uart1_default: uart1_default {
+		group0 {
+			pinmux = <&iomuxc1_uart1_rxd_lpuart_rx_lpuart1_rx>,
+				<&iomuxc1_uart1_txd_lpuart_tx_lpuart1_tx>;
+			bias-pull-up;
+			slew-rate = "slightly_fast";
+			drive-strength = "x5";
+		};
+	};
+
+	uart2_default: uart2_default {
+		group0 {
+			pinmux = <&iomuxc1_uart2_rxd_lpuart_rx_lpuart2_rx>,
+				<&iomuxc1_uart2_txd_lpuart_tx_lpuart2_tx>;
+			bias-pull-up;
+			slew-rate = "slightly_fast";
+			drive-strength = "x5";
+		};
+	};
+};
diff --git a/boards/nxp/imx91_evk/imx91_evk_mimx9131.dts b/boards/nxp/imx91_evk/imx91_evk_mimx9131.dts
new file mode 100644
index 00000000000..6b4f464375b
--- /dev/null
+++ b/boards/nxp/imx91_evk/imx91_evk_mimx9131.dts
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_mimx91.dtsi>
+#include "imx91_evk-pinctrl.dtsi"
+
+/ {
+	model = "NXP i.MX91 A55";
+	compatible = "fsl,mimx91";
+
+	chosen {
+		zephyr,console = &lpuart1;
+		zephyr,shell-uart = &lpuart1;
+		/* sram node actually locates at DDR DRAM */
+		zephyr,sram = &dram;
+	};
+
+	dram: memory@80000000 {
+		reg = <0x80000000 DT_SIZE_M(1)>;
+	};
+
+};
+
+&lpuart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart1_default>;
+	pinctrl-names = "default";
+};
diff --git a/boards/nxp/imx91_evk/imx91_evk_mimx9131.yaml b/boards/nxp/imx91_evk/imx91_evk_mimx9131.yaml
new file mode 100644
index 00000000000..4302f9566b4
--- /dev/null
+++ b/boards/nxp/imx91_evk/imx91_evk_mimx9131.yaml
@@ -0,0 +1,17 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: imx91_evk/mimx9131
+name: NXP i.MX91 EVK
+type: mcu
+arch: arm64
+toolchain:
+  - zephyr
+  - cross-compile
+ram: 1024
+supported:
+  - uart
+vendor: nxp
diff --git a/boards/nxp/imx91_evk/imx91_evk_mimx9131_defconfig b/boards/nxp/imx91_evk/imx91_evk_mimx9131_defconfig
new file mode 100644
index 00000000000..830456d006d
--- /dev/null
+++ b/boards/nxp/imx91_evk/imx91_evk_mimx9131_defconfig
@@ -0,0 +1,30 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# ARM Options
+CONFIG_AARCH64_IMAGE_HEADER=y
+CONFIG_ARMV8_A_NS=y
+
+# MMU Options
+# Increase the value when encounter the assert on the MAX_XLAT_TABLES
+CONFIG_MAX_XLAT_TABLES=24
+
+# Cache Options
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_DCACHE_LINE_SIZE_DETECT=y
+CONFIG_ICACHE_LINE_SIZE_DETECT=y
+
+# Zephyr Kernel Configuration
+CONFIG_XIP=n
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/nxp/imx93_evk/CMakeLists.txt b/boards/nxp/imx93_evk/CMakeLists.txt
index 218a0602483..39ae9ed0e4e 100644
--- a/boards/nxp/imx93_evk/CMakeLists.txt
+++ b/boards/nxp/imx93_evk/CMakeLists.txt
@@ -1,4 +1,16 @@
+#
+# Copyright 2025 NXP
+#
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_library()
 zephyr_library_sources(board.c)
+
+if(CONFIG_SOC_MIMX9352_A55)
+  file(WRITE ${CMAKE_BINARY_DIR}/zephyr/runner.jlinkscript
+    "LE
+    loadfile "${CMAKE_BINARY_DIR}/zephyr/zephyr.bin" ${CONFIG_SRAM_BASE_ADDRESS}
+    WReg PC ${CONFIG_SRAM_BASE_ADDRESS}
+    g
+    q")
+endif()
diff --git a/boards/nxp/imx93_evk/board.cmake b/boards/nxp/imx93_evk/board.cmake
index 9881313609a..97de8649143 100644
--- a/boards/nxp/imx93_evk/board.cmake
+++ b/boards/nxp/imx93_evk/board.cmake
@@ -1 +1,12 @@
+#
+# Copyright 2025 NXP
+#
 # SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_MIMX9352_A55)
+
+board_runner_args(jlink "--device=MIMX9352_A55_0" "--no-reset" "--flash-script=${CMAKE_BINARY_DIR}/zephyr/runner.jlinkscript")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+
+endif()
diff --git a/boards/nxp/imx93_evk/doc/index.rst b/boards/nxp/imx93_evk/doc/index.rst
index d410cd5dd26..ce5080d0755 100644
--- a/boards/nxp/imx93_evk/doc/index.rst
+++ b/boards/nxp/imx93_evk/doc/index.rst
@@ -45,53 +45,7 @@ Cortex®-M33 core. Zephyr OS is ported to run on one of the Cortex®-A55 core.
 Supported Features
 ==================
 
-The Zephyr mimx93_evk board Cortex-A Core configuration supports the following
-hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| GIC-v4    | on-chip    | interrupt controller                |
-+-----------+------------+-------------------------------------+
-| ARM TIMER | on-chip    | system clock                        |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | GPIO                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
-| TPM       | on-chip    | TPM Counter                         |
-+-----------+------------+-------------------------------------+
-| ENET      | on-chip    | ethernet port                       |
-+-----------+------------+-------------------------------------+
-
-The Zephyr imx93_evk board Cortex-M33 configuration supports the following
-hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | interrupt controller                |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | GPIO                                |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Devices
 ========
@@ -162,8 +116,62 @@ Note: The overlay only supports ``mimx9352/a55``, but can be extended to support
 Programming and Debugging (A55)
 *******************************
 
-U-Boot "cpu" command is used to load and kick Zephyr to Cortex-A secondary Core, Currently
-it is supported in : `Real-Time Edge U-Boot`_ (use the branch "uboot_vxxxx.xx-y.y.y,
+.. zephyr:board-supported-runners::
+
+There are multiple method to program and debug Zephyr on the A55 core:
+
+Option 1. Boot Zephyr by Using JLink Runner
+===========================================
+
+The default runner for the board is JLink, connect the EVK board's JTAG connector to
+the host computer using a J-Link debugger, power up the board and stop the board at
+U-Boot command line, execute the following U-boot command to disable D-Cache:
+
+.. code-block:: console
+
+    dcache off
+
+then use "west flash" or "west debug" command to load the zephyr.bin
+image from the host computer and start the Zephyr application on A55 core0.
+
+Flash and Run
+-------------
+
+Here is an example for the :zephyr:code-sample:`synchronization` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/synchronization
+   :host-os: unix
+   :board: imx93_evk/mimx9352/a55
+   :goals: flash
+
+Then the following log could be found on UART2 console:
+
+.. code-block:: console
+
+    *** Booting Zephyr OS build Booting Zephyr OS build v3.7.0-2055-g630f27a5a867  ***
+    thread_a: Hello World from cpu 0 on imx93_evk!
+    thread_b: Hello World from cpu 0 on imx93_evk!
+    thread_a: Hello World from cpu 0 on imx93_evk!
+    thread_b: Hello World from cpu 0 on imx93_evk!
+
+Debug
+-----
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :host-os: unix
+   :board: imx93_evk/mimx9352/a55
+   :goals: debug
+
+Option 2. Boot Zephyr by Using U-Boot Command
+=============================================
+
+U-Boot "go" command can be used to start Zephyr on A55 core0 and U-Boot "cpu" command
+is used to load and kick Zephyr to the other A55 secondary Cores. Currently "cpu" command
+is supported in : `Real-Time Edge U-Boot`_ (use the branch "uboot_vxxxx.xx-y.y.y,
 xxxx.xx is uboot version and y.y.y is Real-Time Edge Software version, for example
 "uboot_v2023.04-2.9.0" branch is U-Boot v2023.04 used in Real-Time Edge Software release
 v2.9.0), and pre-build images and user guide can be found at `Real-Time Edge Software`_.
@@ -173,23 +181,45 @@ v2.9.0), and pre-build images and user guide can be found at `Real-Time Edge Sof
 .. _Real-Time Edge Software:
    https://www.nxp.com/rtedge
 
-Copy the compiled ``zephyr.bin`` to the first FAT partition of the SD card and
-plug the SD card into the board. Power it up and stop the u-boot execution at
-prompt.
+Step 1: Download Zephyr Image into DDR Memory
+---------------------------------------------
+
+Firstly need to download Zephyr binary image into DDR memory, it can use tftp:
+
+.. code-block:: console
+
+    tftp 0xd0000000 zephyr.bin
 
-Use U-Boot to load and kick zephyr.bin to Cortex-A55 Core1:
+Or copy the Zephyr image ``zephyr.bin`` SD card and plug the card into the board, for example
+if copy to the FAT partition of the SD card, use the following U-Boot command to load the image
+into DDR memory (assuming the SD card is dev 1, fat partition ID is 1, they could be changed
+based on actual setup):
 
 .. code-block:: console
 
-    fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; cpu 1 release 0xd0000000
+    fatload mmc 1:1 0xd0000000 zephyr.bin;
 
+Step 2: Boot Zephyr
+-------------------
 
-Or use the following command to kick zephyr.bin to Cortex-A55 Core0:
+Then use the following command to boot Zephyr on the core0:
 
 .. code-block:: console
 
-    fatload mmc 1:1 0xd0000000 zephyr.bin; dcache flush; icache flush; go 0xd0000000
+    dcache off; icache flush; go 0xd0000000;
 
+Or use "cpu" command to boot from secondary Core, for example Core1:
+
+.. code-block:: console
+
+    dcache flush; icache flush; cpu 1 release 0xd0000000
+
+Option 3. Boot Zephyr by Using Remoteproc under Linux
+=====================================================
+
+When running Linux on the A55 core, it can use the remoteproc framework to load and boot Zephyr,
+refer to Real-Time Edge user guide for more details. Pre-build images and user guide can be found
+at `Real-Time Edge Software`_.
 
 Use this configuration to run basic Zephyr applications and kernel tests,
 for example, with the :zephyr:code-sample:`synchronization` sample:
@@ -383,3 +413,6 @@ This board has been designed for SOF so it's only intended to be used with SOF.
 
 TODO: document the SOF build process for this board. For now, the support for
 i.MX93 is still in review and has yet to merged on SOF side.
+
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
diff --git a/boards/nxp/imx95_evk/CMakeLists.txt b/boards/nxp/imx95_evk/CMakeLists.txt
index 4b246954743..19302b77d01 100644
--- a/boards/nxp/imx95_evk/CMakeLists.txt
+++ b/boards/nxp/imx95_evk/CMakeLists.txt
@@ -11,3 +11,6 @@ if (CONFIG_SOF AND CONFIG_BOARD_IMX95_EVK_MIMX9596_M7_DDR)
     DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
   )
 endif()
+
+zephyr_library()
+zephyr_library_sources(board.c)
diff --git a/boards/nxp/imx95_evk/board.c b/boards/nxp/imx95_evk/board.c
new file mode 100644
index 00000000000..477bcc38f6a
--- /dev/null
+++ b/boards/nxp/imx95_evk/board.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <soc.h>
+
+static int board_init(void)
+{
+#if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0)
+	/* Port 0 to 2 protocol configure: RGMII, RGMII, XGMII */
+	BLK_CTRL_NETCMIX->CFG_LINK_MII_PROT = 0x00000522;
+	BLK_CTRL_NETCMIX->CFG_LINK_PCS_PROT_2 = 0x00000040;
+
+	/* Unlock the IERB. It will warm reset whole NETC. */
+	NETC_PRIV->NETCRR &= ~NETC_PRIV_NETCRR_LOCK_MASK;
+	while ((NETC_PRIV->NETCRR & NETC_PRIV_NETCRR_LOCK_MASK) != 0U) {
+	}
+
+	/* Lock the IERB. */
+	NETC_PRIV->NETCRR |= NETC_PRIV_NETCRR_LOCK_MASK;
+	while ((NETC_PRIV->NETCSR & NETC_PRIV_NETCSR_STATE_MASK) != 0U) {
+	}
+#endif
+	return 0;
+}
+
+/*
+ * Because platform is using ARM SCMI, drivers like scmi, mbox etc. are
+ * initialized during PRE_KERNEL_1. Common init hooks is not able to use.
+ * SoC early init and board early init could be run during PRE_KERNEL_2 instead.
+ */
+SYS_INIT(board_init, PRE_KERNEL_2, 10);
diff --git a/boards/nxp/imx95_evk/doc/index.rst b/boards/nxp/imx95_evk/doc/index.rst
index 1acf8cc536f..75aba8fd01d 100644
--- a/boards/nxp/imx95_evk/doc/index.rst
+++ b/boards/nxp/imx95_evk/doc/index.rst
@@ -73,42 +73,7 @@ Hardware
 Supported Features
 ==================
 
-The Zephyr ``imx95_evk/mimx9596/m7`` board target supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | interrupt controller                |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| TPM       | on-chip    | tpm                                 |
-+-----------+------------+-------------------------------------+
-
-The Zephyr ``imx95_evk/mimx9596/a55`` and ``imx95_evk/mimx9596/a55/smp`` board targets support
-the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| GIC-v4    | on-chip    | interrupt controller                |
-+-----------+------------+-------------------------------------+
-| ARM TIMER | on-chip    | system clock                        |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 System Clock
 ------------
@@ -131,10 +96,25 @@ oscilloscope.
 Channel 2 signal routed to resistance R881.
 Channel 3 signal routed to resistance R882.
 
+SPI
+---
+
+The EVK board need to be reworked to solder R1217/R1218/R1219/R1220 with 0R resistances.
+SPI1 on J35 is enabled for M7.
+
+Ethernet
+--------
+
+NETC driver supports to manage the Physical Station Interface (PSI).
+The first ENET1 port could be enabled for M7 by west build option
+``-DEXTRA_DTC_OVERLAY_FILE=enetc_psi0.overlay``.
+
 
 Programming and Debugging (A55)
 *******************************
 
+.. zephyr:board-supported-runners::
+
 Use this configuration to run basic Zephyr applications and kernel tests,
 for example, with the :zephyr:code-sample:`synchronization` sample:
 
@@ -283,11 +263,8 @@ while, for the ``imx95_evk/mimx9596/m7/ddr`` board, you should get the following
 .. _MCUX SDK release:
    https://mcuxpresso.nxp.com/
 
-References
-==========
-
-More information can refer to NXP official website:
-`NXP website`_.
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
 
 .. _NXP website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors/i-mx-95-applications-processor-family-high-performance-safety-enabled-platform-with-eiq-neutron-npu:iMX95
diff --git a/boards/nxp/imx95_evk/dts/enetc_psi0.overlay b/boards/nxp/imx95_evk/dts/enetc_psi0.overlay
new file mode 100644
index 00000000000..2e24f5ff94b
--- /dev/null
+++ b/boards/nxp/imx95_evk/dts/enetc_psi0.overlay
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&emdio {
+	status = "okay";
+
+	phy0: phy@1 {
+		status = "okay";
+	};
+};
+
+&enetc_psi0 {
+	status = "okay";
+};
diff --git a/boards/nxp/imx95_evk/imx95_evk-pinctrl.dtsi b/boards/nxp/imx95_evk/imx95_evk-pinctrl.dtsi
index fecd72a46f1..607e84753d8 100644
--- a/boards/nxp/imx95_evk/imx95_evk-pinctrl.dtsi
+++ b/boards/nxp/imx95_evk/imx95_evk-pinctrl.dtsi
@@ -6,6 +6,42 @@
 #include <nxp/nxp_imx/mimx9596avzxn-pinctrl.dtsi>
 
 &pinctrl {
+	emdio_default: emdio_default {
+		group1 {
+			pinmux = <&iomuxc_enet1_mdc_netc_mdc_netc_mdc>,
+				<&iomuxc_enet1_mdio_netc_mdio_netc_mdio>;
+			bias-pull-down;
+			slew-rate = "slightly_fast";
+			drive-strength = "x6";
+		};
+	};
+
+	eth0_default: eth0_default {
+		group1 {
+			pinmux = <&iomuxc_enet1_rx_ctl_eth_rgmii_rx_ctl_eth0_rgmii_rx_ctl>,
+				<&iomuxc_enet1_rd0_eth_rgmii_rd_eth0_rgmii_rd0>,
+				<&iomuxc_enet1_rd1_eth_rgmii_rd_eth0_rgmii_rd1>,
+				<&iomuxc_enet1_rd2_eth_rgmii_rd_eth0_rgmii_rd2>,
+				<&iomuxc_enet1_rd3_eth_rgmii_rd_eth0_rgmii_rd3>,
+				<&iomuxc_enet1_tx_ctl_eth_rgmii_tx_ctl_eth0_rgmii_tx_ctl>,
+				<&iomuxc_enet1_td0_eth_rgmii_td_eth0_rgmii_td0>,
+				<&iomuxc_enet1_td1_eth_rgmii_td_eth0_rgmii_td1>,
+				<&iomuxc_enet1_td2_eth_rgmii_td_eth0_rgmii_td2>,
+				<&iomuxc_enet1_td3_eth_rgmii_td_eth0_rgmii_td3>;
+			bias-pull-down;
+			slew-rate = "slightly_fast";
+			drive-strength = "x6";
+		};
+		group2 {
+			pinmux = <&iomuxc_enet1_rxc_eth_rgmii_rx_clk_eth0_rgmii_rx_clk>,
+				<&iomuxc_enet1_txc_eth_rgmii_tx_clk_eth0_rgmii_tx_clk>;
+			bias-pull-down;
+			slew-rate = "fast";
+			drive-strength = "x6";
+		};
+
+	};
+
 	lpi2c5_default: lpi2c5_default {
 		group0 {
 			pinmux = <&iomuxc_gpio_io23_lpi2c_scl_lpi2c5_scl>,
@@ -28,6 +64,18 @@
 		};
 	};
 
+	lpspi1_default: lpspi1_default {
+		group0 {
+			pinmux = <&iomuxc_sai1_txfs_lpspi_pcs_lpspi1_pcs0>,
+				<&iomuxc_sai1_txd0_lpspi_sck_lpspi1_sck>,
+				<&iomuxc_sai1_txc_lpspi_sin_lpspi1_sin>,
+				<&iomuxc_sai1_rxd0_lpspi_sout_lpspi1_sout>;
+			bias-pull-down;
+			slew-rate = "slightly_fast";
+			drive-strength = "x4";
+		};
+	};
+
 	lpuart1_default: lpuart1_default {
 		group0 {
 			pinmux = <&iomuxc_uart1_rxd_lpuart_rx_lpuart1_rx>,
diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.dts b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.dts
index 62997746f44..d4aff0f100d 100644
--- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.dts
+++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -47,6 +47,18 @@
 	};
 };
 
+&lpi2c5 {
+	pinctrl-0 = <&lpi2c5_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&lpi2c7 {
+	pinctrl-0 = <&lpi2c7_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &lpuart1 {
 	status = "okay";
 	current-speed = <115200>;
diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.yaml b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.yaml
index c1183ca216a..a4597d08db3 100644
--- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.yaml
+++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55.yaml
@@ -13,5 +13,7 @@ toolchain:
   - cross-compile
 ram: 1024
 supported:
+  - counter
+  - i2c
   - uart
 vendor: nxp
diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.dts b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.dts
index cdb7edf2f74..3dec65cf983 100644
--- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.dts
+++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -29,6 +29,18 @@
 	};
 };
 
+&lpi2c5 {
+	pinctrl-0 = <&lpi2c5_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&lpi2c7 {
+	pinctrl-0 = <&lpi2c7_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &lpuart1 {
 	status = "okay";
 	current-speed = <115200>;
diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.yaml b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.yaml
index 210f5f3278a..5b048d8fa77 100644
--- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.yaml
+++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_a55_smp.yaml
@@ -13,6 +13,8 @@ toolchain:
   - cross-compile
 ram: 1024
 supported:
+  - counter
+  - i2c
   - smp
   - uart
 vendor: nxp
diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts
index ebc22540f8e..cdc053f5c94 100644
--- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts
+++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts
@@ -23,6 +23,27 @@
 	};
 };
 
+&emdio {
+	pinctrl-0 = <&emdio_default>;
+	pinctrl-names = "default";
+	status = "disabled";
+
+	phy0: phy@1 {
+		compatible = "realtek,rtl8211f";
+		reg = <0x1>;
+		status = "disabled";
+	};
+};
+
+&enetc_psi0 {
+	local-mac-address = [00 00 00 01 02 00];
+	pinctrl-0 = <&eth0_default>;
+	pinctrl-names = "default";
+	phy-handle = <&phy0>;
+	phy-connection-type = "rgmii";
+	status = "disabled";
+};
+
 &lpi2c5 {
 	pinctrl-0 = <&lpi2c5_default>;
 	pinctrl-names = "default";
@@ -35,6 +56,12 @@
 	status = "okay";
 };
 
+&lpspi1 {
+	pinctrl-0 = <&lpspi1_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &lpuart3 {
 	status = "okay";
 	current-speed = <115200>;
diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml
index 23fab0caeab..50cd837eb7b 100644
--- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml
+++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml
@@ -13,9 +13,10 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - uart
   - i2c
   - pwm
+  - spi
+  - netif:eth
 vendor: nxp
diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr.yaml b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr.yaml
index b1f0b22dfc9..8a1674b8bd9 100644
--- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr.yaml
+++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr.yaml
@@ -12,7 +12,6 @@ ram: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - uart
 vendor: nxp
diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr_defconfig b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr_defconfig
index f89de52c036..effcdb5e4d4 100644
--- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr_defconfig
+++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_ddr_defconfig
@@ -17,6 +17,7 @@ CONFIG_CONSOLE=y
 CONFIG_MBOX=y
 CONFIG_MBOX_INIT_PRIORITY=0
 CONFIG_ARM_SCMI=y
+CONFIG_ARM_SCMI_NXP_VENDOR_EXTENSIONS=y
 
 # kernel-related configurations
 CONFIG_XIP=n
diff --git a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_defconfig b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_defconfig
index 180973c667f..338c3ea662a 100644
--- a/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_defconfig
+++ b/boards/nxp/imx95_evk/imx95_evk_mimx9596_m7_defconfig
@@ -13,3 +13,4 @@ CONFIG_XIP=y
 CONFIG_MBOX=y
 CONFIG_MBOX_INIT_PRIORITY=0
 CONFIG_ARM_SCMI=y
+CONFIG_ARM_SCMI_NXP_VENDOR_EXTENSIONS=y
diff --git a/boards/nxp/lpcxpresso11u68/doc/index.rst b/boards/nxp/lpcxpresso11u68/doc/index.rst
index 4fe74d245c8..5ab49c3df48 100644
--- a/boards/nxp/lpcxpresso11u68/doc/index.rst
+++ b/boards/nxp/lpcxpresso11u68/doc/index.rst
@@ -42,30 +42,7 @@ More information can be found here:
 Supported Features
 ==================
 
-The lpcxpresso11U68 supports the following features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| IOCON     | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock and reset control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c master/slave controller         |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port interrupt               |
-+-----------+------------+-------------------------------------+
-| EEPROM    | on-chip    | eeprom                              |
-+-----------+------------+-------------------------------------+
-
-Other hardware is not yet supported on Zephyr.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -94,6 +71,8 @@ The IOCON controller can be used to configure the LPC11U68 pins.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -140,6 +119,9 @@ References
 - `LPCXPRESSO11U68 Website`_
 - `LPCXPRESSO11U68 Schematics`_
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _LPC11UXX SoC Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc1100-cortex-m0-plus-m0/scalable-entry-level-32-bit-microcontroller-mcu-based-on-arm-cortex-m0-plus-and-cortex-m0-cores:LPC11U00
 
diff --git a/boards/nxp/lpcxpresso51u68/doc/index.rst b/boards/nxp/lpcxpresso51u68/doc/index.rst
index 3246a9f9393..da861418841 100644
--- a/boards/nxp/lpcxpresso51u68/doc/index.rst
+++ b/boards/nxp/lpcxpresso51u68/doc/index.rst
@@ -31,30 +31,7 @@ More information can be found here:
 Supported Features
 ==================
 
-The lpcxpresso51u68 support the following features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| IOCON     | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock and reset control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c master/slave controller         |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port interrupt               |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | SPI master                          |
-+-----------+------------+-------------------------------------+
-
-Other hardware is not yet supported on Zephyr.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -90,6 +67,8 @@ The IOCON controller can be used to configure the LPC51U68 pins.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -156,6 +135,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS build zephyr-v2.6.0-934-g4c438c0c7d13 *****
    Hello World! lpcxpresso51u68
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _LPC51U68 SoC Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/high-performance-power-efficient-and-cost-sensitive-arm-cortex-m0-plus-mcus:LPC51U68
 
diff --git a/boards/nxp/lpcxpresso51u68/lpcxpresso51u68.yaml b/boards/nxp/lpcxpresso51u68/lpcxpresso51u68.yaml
index 1c7a0644a10..91fbd6f992a 100644
--- a/boards/nxp/lpcxpresso51u68/lpcxpresso51u68.yaml
+++ b/boards/nxp/lpcxpresso51u68/lpcxpresso51u68.yaml
@@ -13,7 +13,6 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - gpio
diff --git a/boards/nxp/lpcxpresso54114/doc/index.rst b/boards/nxp/lpcxpresso54114/doc/index.rst
index 410a052b433..84b9bf44c2d 100644
--- a/boards/nxp/lpcxpresso54114/doc/index.rst
+++ b/boards/nxp/lpcxpresso54114/doc/index.rst
@@ -40,37 +40,7 @@ For more information about the LPC54114 SoC and LPCXPRESSO54114 board:
 Supported Features
 ==================
 
-The lpcxpresso54114 board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| IOCON     | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| USART     | on-chip    | serial port-polling                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| IAP       | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-
-The default configuration for each core can be found in the defconfig files:
-
-- :zephyr_file:`boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4_defconfig`
-- :zephyr_file:`boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -120,6 +90,8 @@ configured as USART for the console and the remaining are not used.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -192,6 +164,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS v1.14.0-rc1 *****
    Hello World! lpcxpresso54114_m4
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _LPC54114 SoC Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc54000-series-cortex-m4-mcus/low-power-microcontrollers-mcus-based-on-arm-cortex-m4-cores-with-optional-cortex-m0-plus-co-processor:LPC541XX
 
diff --git a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.yaml b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.yaml
index 8f99d4bbd9d..8294367fcbd 100644
--- a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.yaml
+++ b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m0.yaml
@@ -14,7 +14,6 @@ testing:
   ignore_tags:
     - net
 toolchain:
-  - xtools
   - zephyr
   - gnuarmemb
 vendor: nxp
diff --git a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml
index f2ed30e6976..f1f13fb5cda 100644
--- a/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml
+++ b/boards/nxp/lpcxpresso54114/lpcxpresso54114_lpc54114_m4.yaml
@@ -13,7 +13,6 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_i2c
   - arduino_spi
diff --git a/boards/nxp/lpcxpresso55s06/board.cmake b/boards/nxp/lpcxpresso55s06/board.cmake
index a6df50bba73..305ed963f21 100644
--- a/boards/nxp/lpcxpresso55s06/board.cmake
+++ b/boards/nxp/lpcxpresso55s06/board.cmake
@@ -8,5 +8,5 @@
 board_runner_args(linkserver  "--device=LPC55S06:LPCXpresso55S06")
 board_runner_args(jlink "--device=LPC55S06" "--reset-after-load")
 
-include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/nxp/lpcxpresso55s06/doc/index.rst b/boards/nxp/lpcxpresso55s06/doc/index.rst
index a4f5234aa70..61c9c681023 100644
--- a/boards/nxp/lpcxpresso55s06/doc/index.rst
+++ b/boards/nxp/lpcxpresso55s06/doc/index.rst
@@ -36,40 +36,15 @@ For more information about the LPC55S06 SoC and LPCXPresso55S06 board, see:
 Supported Features
 ==================
 
-The lpcxpresso55s06 board configuration supports the hardware features listed
-below.  For additional features not yet supported, please also refer to the
-:zephyr:board:`lpcxpresso55s69` , which is the superset board in NXP's LPC55xx series.
-NXP prioritizes enabling the superset board with NXP's Full Platform Support for
-Zephyr.  Therefore, the lpcxpresso55s69 board may have additional features
-already supported, which can also be re-used on this lpcxpresso55s06 board:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| IOCON     | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| USART     | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | entropy;                            |
-|           |            | random                              |
-+-----------+------------+-------------------------------------+
-| IAP       | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently enabled.
-
-Currently available targets for this board are:
-
-- *lpcxpresso55s06*
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   For additional features not yet supported, please also refer to the
+   :zephyr:board:`lpcxpresso55s69` , which is the superset board in NXP's LPC55xx series.
+   NXP prioritizes enabling the superset board with NXP's Full Platform Support for
+   Zephyr.  Therefore, the lpcxpresso55s69 board may have additional features
+   already supported, which can also be re-used on this lpcxpresso55s06 board:
 
 Connections and IOs
 ===================
@@ -114,25 +89,25 @@ and the remaining are not used.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application`
 and :ref:`application_run` for more details).
 
 Configuring a Debug Probe
 =========================
 
-A debug probe is used for both flashing and debugging the board. This
-board is configured by default to use the LPC-Link2 CMSIS-DAP Onboard
-Debug Probe, however the :ref:`pyocd-debug-host-tools` does not yet
-support the LPC55S06 so you must reconfigure the board for one of the
-J-Link debug probe instead.
+LinkServer is the default runner for this board.
+A debug probe is used for both flashing and debugging the board. This board is
+configured by default to use the integrated :ref:`mcu-link-onboard-debug-probe`
+in the CMSIS-DAP mode. To use this probe with Zephyr, you need to install the
+:ref:`linkserver-debug-host-tools` and make sure they are in your search path.
+Refer to the detailed overview about :ref:`application_debugging` for additional
+information.
 
-First install the :ref:`jlink-debug-host-tools` and make sure they are
-in your search path.
-
-Then follow the instructions in
-:ref:`lpclink2-jlink-onboard-debug-probe` to program the J-Link
-firmware. Please make sure you have the latest firmware for this
-board.
+The integrated MCU-Link hardware can also be used as a J-Link probe with a
+firmware update, as described in :ref:`mcu-link-jlink-onboard-debug-probe`.
+The :ref:`jlink-debug-host-tools` should be available in this case.
 
 Configuring a Console
 =====================
@@ -182,6 +157,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS zephyr-v3.0.0 *****
    Hello World! lpcxpresso55s06
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _LPC55S06 SoC Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc5500-cortex-m33/lpc550x-s0x-baseline-arm-cortex-m33-based-microcontroller-family:LPC550x
 
diff --git a/boards/nxp/lpcxpresso55s06/lpcxpresso55s06.yaml b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06.yaml
index f6cbb2e4e6e..958a493b81a 100644
--- a/boards/nxp/lpcxpresso55s06/lpcxpresso55s06.yaml
+++ b/boards/nxp/lpcxpresso55s06/lpcxpresso55s06.yaml
@@ -12,7 +12,6 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - can
   - flash
diff --git a/boards/nxp/lpcxpresso55s16/board.cmake b/boards/nxp/lpcxpresso55s16/board.cmake
index f1a6370b01f..45ca5dcfe1c 100644
--- a/boards/nxp/lpcxpresso55s16/board.cmake
+++ b/boards/nxp/lpcxpresso55s16/board.cmake
@@ -9,6 +9,6 @@ board_runner_args(linkserver  "--device=LPC55S16:LPCXpresso55S16")
 board_runner_args(jlink "--device=LPC55S16" "--reset-after-load")
 board_runner_args(pyocd "--target=lpc55s16")
 
-include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
diff --git a/boards/nxp/lpcxpresso55s16/doc/index.rst b/boards/nxp/lpcxpresso55s16/doc/index.rst
index f38fd083c8a..f164238247e 100644
--- a/boards/nxp/lpcxpresso55s16/doc/index.rst
+++ b/boards/nxp/lpcxpresso55s16/doc/index.rst
@@ -41,50 +41,15 @@ For more information about the LPC55S16 SoC and LPCXPresso55S16 board, see:
 Supported Features
 ==================
 
-The lpcxpresso55s16 board configuration supports the hardware features listed
-below.  For additional features not yet supported, please also refer to the
-:zephyr:board:`lpcxpresso55s69` , which is the superset board in NXP's LPC55xx series.
-NXP prioritizes enabling the superset board with NXP's Full Platform Support for
-Zephyr.  Therefore, the lpcxpresso55s69 board may have additional features
-already supported, which can also be re-used on this lpcxpresso55s16 board:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| IOCON     | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| USART     | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| SENSOR    | off-chip   | fxos8700 trigger                    |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | canbus                              |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | entropy;                            |
-|           |            | random                              |
-+-----------+------------+-------------------------------------+
-| IAP       | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently enabled.
-
-Currently available targets for this board are:
-
-- *lpcxpresso55s16*
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   For additional features not yet supported, please also refer to the
+   :zephyr:board:`lpcxpresso55s69` , which is the superset board in NXP's LPC55xx series.
+   NXP prioritizes enabling the superset board with NXP's Full Platform Support for
+   Zephyr.  Therefore, the lpcxpresso55s69 board may have additional features
+   already supported, which can also be re-used on this lpcxpresso55s16 board.
 
 Connections and IOs
 ===================
@@ -149,25 +114,25 @@ configured for I2C, and the remaining are not used.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application`
 and :ref:`application_run` for more details).
 
 Configuring a Debug Probe
 =========================
 
-A debug probe is used for both flashing and debugging the board. This
-board is configured by default to use the LPC-Link2 CMSIS-DAP Onboard
-Debug Probe, however the :ref:`pyocd-debug-host-tools` does not yet
-support the LPC55S16 so you must reconfigure the board for one of the
-J-Link debug probe instead.
+LinkServer is the default runner for this board.
+A debug probe is used for both flashing and debugging the board. This board is
+configured by default to use the integrated :ref:`mcu-link-onboard-debug-probe`
+in the CMSIS-DAP mode. To use this probe with Zephyr, you need to install the
+:ref:`linkserver-debug-host-tools` and make sure they are in your search path.
+Refer to the detailed overview about :ref:`application_debugging` for additional
+information.
 
-First install the :ref:`jlink-debug-host-tools` and make sure they are
-in your search path.
-
-Then follow the instructions in
-:ref:`lpclink2-jlink-onboard-debug-probe` to program the J-Link
-firmware. Please make sure you have the latest firmware for this
-board.
+The integrated MCU-Link hardware can also be used as a J-Link probe with a
+firmware update, as described in :ref:`mcu-link-jlink-onboard-debug-probe`.
+The :ref:`jlink-debug-host-tools` should be available in this case.
 
 Configuring a Console
 =====================
@@ -217,6 +182,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS zephyr-v2.2.0 *****
    Hello World! lpcxpresso55s16
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _LPC55S16 SoC Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc5500-cortex-m33/lpc551x-s1x-baseline-arm-cortex-m33-based-microcontroller-family:LPC551X-S1X
 
diff --git a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.dts b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.dts
index 9a19e69aed7..0baeb3e6293 100644
--- a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.dts
+++ b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.dts
@@ -26,7 +26,7 @@
 
 zephyr_udc0: &usbhs {
 	status = "okay";
-	phy_handle = <&usbphy1>;
+	phy-handle = <&usbphy1>;
 };
 
 &usbphy1 {
diff --git a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.yaml b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.yaml
index 8b930b43ae5..797e5a680f0 100644
--- a/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.yaml
+++ b/boards/nxp/lpcxpresso55s16/lpcxpresso55s16.yaml
@@ -13,7 +13,6 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_gpio
   - arduino_i2c
diff --git a/boards/nxp/lpcxpresso55s28/board.cmake b/boards/nxp/lpcxpresso55s28/board.cmake
index 933e3815a8c..0a6ea8e61fe 100644
--- a/boards/nxp/lpcxpresso55s28/board.cmake
+++ b/boards/nxp/lpcxpresso55s28/board.cmake
@@ -8,6 +8,6 @@ board_runner_args(linkserver  "--device=LPC55S28:LPCXpresso55S28")
 board_runner_args(pyocd "--target=lpc55s28")
 board_runner_args(jlink "--device=LPC55S28" "--reset-after-load")
 
-include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
diff --git a/boards/nxp/lpcxpresso55s28/doc/index.rst b/boards/nxp/lpcxpresso55s28/doc/index.rst
index b0cea1547be..ca86f0fe9b3 100644
--- a/boards/nxp/lpcxpresso55s28/doc/index.rst
+++ b/boards/nxp/lpcxpresso55s28/doc/index.rst
@@ -41,47 +41,15 @@ For more information about the LPC55S28 SoC and LPCXPresso55S28 board, see:
 Supported Features
 ==================
 
-The lpcxpresso55s28 board configuration supports the hardware features listed
-below.  For additional features not yet supported, please also refer to the
-:zephyr:board:`lpcxpresso55s69` , which is the superset board in NXP's LPC55xx series.
-NXP prioritizes enabling the superset board with NXP's Full Platform Support for
-Zephyr.  Therefore, the lpcxpresso55s69 board may have additional features
-already supported, which can also be re-used on this lpcxpresso55s28 board:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| IOCON     | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| USART     | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WWDT      | on-chip    | windowed watchdog timer             |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | entropy;                            |
-|           |            | random                              |
-+-----------+------------+-------------------------------------+
-| IAP       | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently enabled.
-
-The default configuration file
-:zephyr_file:`boards/nxp/lpcxpresso55s28/lpcxpresso55s28_defconfig`
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   For additional features not yet supported, please also refer to the
+   :zephyr:board:`lpcxpresso55s69` , which is the superset board in NXP's LPC55xx series.
+   NXP prioritizes enabling the superset board with NXP's Full Platform Support for
+   Zephyr.  Therefore, the lpcxpresso55s69 board may have additional features
+   already supported, which can also be re-used on this board.
 
 Connections and IOs
 ===================
@@ -133,15 +101,25 @@ configured as USART for the console and the remaining are not used.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application`
 and :ref:`application_run` for more details).
 
 Configuring a Debug Probe
 =========================
 
-A debug probe is used for both flashing and debugging the board. This
-board is configured by default to use the LPC-Link2 CMSIS-DAP Onboard
-Debug Probe.
+LinkServer is the default runner for this board.
+A debug probe is used for both flashing and debugging the board. This board is
+configured by default to use the integrated :ref:`mcu-link-onboard-debug-probe`
+in the CMSIS-DAP mode. To use this probe with Zephyr, you need to install the
+:ref:`linkserver-debug-host-tools` and make sure they are in your search path.
+Refer to the detailed overview about :ref:`application_debugging` for additional
+information.
+
+The integrated MCU-Link hardware can also be used as a J-Link probe with a
+firmware update, as described in :ref:`mcu-link-jlink-onboard-debug-probe`.
+The :ref:`jlink-debug-host-tools` should be available in this case.
 
 Configuring a Console
 =====================
@@ -190,6 +168,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS zephyr-v2.4.0 *****
    Hello World! lpcxpresso55s28
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _LPC55S28 SoC Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc5500-cortex-m33/lpc552x-s2x-mainstream-arm-cortex-m33-based-microcontroller-family:LPC552x-S2x
 
diff --git a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.yaml b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.yaml
index 898d75c9c27..1892da06e8f 100644
--- a/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.yaml
+++ b/boards/nxp/lpcxpresso55s28/lpcxpresso55s28.yaml
@@ -8,12 +8,11 @@ identifier: lpcxpresso55s28
 name: NXP LPCXpresso55S28
 type: mcu
 arch: arm
-ram: 64
-flash: 256
+ram: 192
+flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - arduino_gpio
diff --git a/boards/nxp/lpcxpresso55s36/board.cmake b/boards/nxp/lpcxpresso55s36/board.cmake
index d1a92d0164d..b1e16906bd5 100644
--- a/boards/nxp/lpcxpresso55s36/board.cmake
+++ b/boards/nxp/lpcxpresso55s36/board.cmake
@@ -8,6 +8,6 @@ board_runner_args(linkserver  "--device=LPC55S36:LPCXpresso55S36")
 board_runner_args(jlink "--device=LPC55S36" "--reset-after-load")
 board_runner_args(pyocd "--target=lpc55s36")
 
-include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
diff --git a/boards/nxp/lpcxpresso55s36/doc/index.rst b/boards/nxp/lpcxpresso55s36/doc/index.rst
index f361f1ea796..0811bb00dc6 100644
--- a/boards/nxp/lpcxpresso55s36/doc/index.rst
+++ b/boards/nxp/lpcxpresso55s36/doc/index.rst
@@ -14,7 +14,7 @@ Hardware
 ********
 
 - LPC55S36 Arm® Cortex®-M33 microcontroller running at up to 150 MHz
-- 256 KB flash and 96 KB SRAM on-chip
+- 256 KB flash and 112 KB SRAM on-chip
 - LPC-Link2 debug high speed USB probe with VCOM port
 - I2C and SPI USB bridging to the LPC device via LPC-Link2 probe
 - MikroElektronika Click expansion option
@@ -43,43 +43,11 @@ Supported Features
 NXP considers the LPCXpresso55S36 as a superset board for the LPC55(S)3x
 family of MCUs.  This board is a focus for NXP's Full Platform Support for
 Zephyr, to better enable the entire LPC55(S)3x family.  NXP prioritizes enabling
-this board with new support for Zephyr features.  The lpcxpresso55s36 board
-configuration supports the hardware features below.  Another similar superset
+this board with new support for Zephyr features.  Another similar superset
 board is the :zephyr:board:`lpcxpresso55s69`, and that board may have additional features
-already supported, which can also be re-used on this lpcxpresso55s36 board:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| IOCON     | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| USART     | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | canbus                              |
-+-----------+------------+-------------------------------------+
-| IAP       | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| USB FS    | on-chip    | USB Full Speed device               |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | dac                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently enabled.
-
-Currently available targets for this board are:
-
-- *lpcxpresso55s36*
+already supported, which can also be re-used on this lpcxpresso55s36 board.
+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -153,18 +121,20 @@ remaining are not used.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application`
 and :ref:`application_run` for more details).
 
 Configuring a Debug Probe
 =========================
 
+LinkServer is the default runner for this board.
 A debug probe is used for both flashing and debugging the board. This board is
 configured by default to use the integrated :ref:`mcu-link-onboard-debug-probe`
 in the CMSIS-DAP mode. To use this probe with Zephyr, you need to install the
 :ref:`linkserver-debug-host-tools` and make sure they are in your search path.
-Then, use the ``linkserver`` runner option to flash and debug the board. Refer
-to the detailed overview about :ref:`application_debugging` for additional
+Refer to the detailed overview about :ref:`application_debugging` for additional
 information.
 
 The integrated MCU-Link hardware can also be used as a J-Link probe with a
@@ -219,6 +189,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS zephyr-v2.2.0 *****
    Hello World! lpcxpresso55s36
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _LPC55S36 SoC Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/lpc5500-cortex-m33/lpc553x-s3x-advanced-analog-armcortex-m33-based-mcu-family:LPC553x
 
diff --git a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml
index aec2ca1f6ac..c5e4f7154a4 100644
--- a/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml
+++ b/boards/nxp/lpcxpresso55s36/lpcxpresso55s36.yaml
@@ -8,12 +8,11 @@ identifier: lpcxpresso55s36
 name: NXP LPCXpresso55S36
 type: mcu
 arch: arm
-ram: 96
-flash: 256
+ram: 112
+flash: 246
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_gpio
   - can
diff --git a/boards/nxp/lpcxpresso55s69/Kconfig b/boards/nxp/lpcxpresso55s69/Kconfig
new file mode 100644
index 00000000000..160ff5a7121
--- /dev/null
+++ b/boards/nxp/lpcxpresso55s69/Kconfig
@@ -0,0 +1,5 @@
+# Copyright 2024-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_LPCXPRESSO55S69
+	select BOARD_EARLY_INIT_HOOK
diff --git a/boards/nxp/lpcxpresso55s69/board.c b/boards/nxp/lpcxpresso55s69/board.c
index 9908b589b98..f3c367e570b 100644
--- a/boards/nxp/lpcxpresso55s69/board.c
+++ b/boards/nxp/lpcxpresso55s69/board.c
@@ -8,7 +8,7 @@
 #include <fsl_common.h>
 #include <soc.h>
 
-static int lpcxpresso_55s69_board_init(void)
+void board_early_init_hook(void)
 {
 
 #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm6), nxp_lpc_i2s, okay)) && \
@@ -47,8 +47,4 @@ static int lpcxpresso_55s69_board_init(void)
 #endif
 
 #endif
-
-	return 0;
 }
-
-SYS_INIT(lpcxpresso_55s69_board_init,  PRE_KERNEL_1, 0);
diff --git a/boards/nxp/lpcxpresso55s69/doc/index.rst b/boards/nxp/lpcxpresso55s69/doc/index.rst
index 8e1a41e11fc..2214ba3206c 100644
--- a/boards/nxp/lpcxpresso55s69/doc/index.rst
+++ b/boards/nxp/lpcxpresso55s69/doc/index.rst
@@ -44,58 +44,9 @@ Supported Features
 NXP considers the LPCXpresso55S69 as the superset board for the LPC55xx
 series of MCUs.  This board is a focus for NXP's Full Platform Support for
 Zephyr, to better enable the entire LPC55xx series.  NXP prioritizes enabling
-this board with new support for Zephyr features.  The lpcxpresso55s69 board
-configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| IOCON     | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| USART     | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WWDT      | on-chip    | windowed watchdog timer             |
-+-----------+------------+-------------------------------------+
-| TrustZone | on-chip    | Trusted Firmware-M                  |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| MAILBOX   | on-chip    | ipm                                 |
-+-----------+------------+-------------------------------------+
-| HWINFO    | on-chip    | Unique device serial number         |
-+-----------+------------+-------------------------------------+
-| USB HS    | on-chip    | USB High Speed device               |
-+-----------+------------+-------------------------------------+
-| USB FS    | on-chip    | USB Full Speed device               |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| I2S       | on-chip    | i2s                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | entropy;                            |
-|           |            | random                              |
-+-----------+------------+-------------------------------------+
-| IAP       | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-| SDIF      | on-chip    | sdhc                                |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma (on CPU0)                       |
-+-----------+------------+-------------------------------------+
+this board with new support for Zephyr features.
+
+.. zephyr:board-supported-hw::
 
 Targets available
 ==================
@@ -267,6 +218,8 @@ configured as USART for the console and the remaining are not used.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -275,32 +228,15 @@ Configuring a Debug Probe
 
 LinkServer is the default runner for this board.
 A debug probe is used for both flashing and debugging the board. This board is
-configured by default to use the LPC-Link2 CMSIS-DAP Onboard Debug Probe,
-however the :ref:`pyocd-debug-host-tools` does not yet support this probe so you
-must reconfigure the board for one of the following debug probes instead.
-
-:ref:`lpclink2-jlink-onboard-debug-probe`
------------------------------------------
-
-Install the :ref:`jlink-debug-host-tools` and make sure they are in your search
-path.
-
-Follow the instructions in :ref:`lpclink2-jlink-onboard-debug-probe` to program
-the J-Link firmware. Please make sure you have the latest firmware for this
-board.
+configured by default to use the integrated :ref:`mcu-link-onboard-debug-probe`
+in the CMSIS-DAP mode. To use this probe with Zephyr, you need to install the
+:ref:`linkserver-debug-host-tools` and make sure they are in your search path.
+Refer to the detailed overview about :ref:`application_debugging` for additional
+information.
 
-:ref:`lpclink2-cmsis-onboard-debug-probe`
------------------------------------------
-
-        1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path.
-        2. To update the debug firmware, please follow the instructions on `LPCXPRESSO55S69 Debug Firmware`_
-
-:ref:`opensda-daplink-onboard-debug-probe`
-------------------------------------------
-
-PyOCD support for this board is ongoing and not yet available.
-To use DAPLink's flash memory programming on this board, follow the instructions
-for `updating LPCXpresso firmware`_.
+The integrated MCU-Link hardware can also be used as a J-Link probe with a
+firmware update, as described in :ref:`mcu-link-jlink-onboard-debug-probe`.
+The :ref:`jlink-debug-host-tools` should be available in this case.
 
 Configuring a Console
 =====================
@@ -375,6 +311,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS zephyr-v1.14.0 *****
    Hello World! lpcxpresso55s69
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _LPC55S69 SoC Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/lpc-cortex-m-mcus/lpc5500-cortex-m33/high-efficiency-arm-cortex-m33-based-microcontroller-family:LPC55S6x
 
diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts
index e87cb04fc79..b966c8545e6 100644
--- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts
+++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts
@@ -152,7 +152,7 @@
 
 zephyr_udc0: &usbhs {
 	status = "okay";
-	phy_handle = <&usbphy1>;
+	phy-handle = <&usbphy1>;
 };
 
 &usbphy1 {
diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.yaml b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.yaml
index bd616045798..cec1ec0332a 100644
--- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.yaml
+++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.yaml
@@ -13,7 +13,6 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - arduino_gpio
diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.yaml b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.yaml
index 5d76704ba7b..2b3541c40f6 100644
--- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.yaml
+++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0_ns.yaml
@@ -13,7 +13,6 @@ flash: 96
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - arduino_spi
diff --git a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.yaml b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.yaml
index 4d6f1c70ab8..1576a30e5da 100644
--- a/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.yaml
+++ b/boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu1.yaml
@@ -13,7 +13,6 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
 vendor: nxp
diff --git a/boards/nxp/ls1046ardb/doc/index.rst b/boards/nxp/ls1046ardb/doc/index.rst
index 28ad3259ed0..f22f54552e1 100644
--- a/boards/nxp/ls1046ardb/doc/index.rst
+++ b/boards/nxp/ls1046ardb/doc/index.rst
@@ -47,39 +47,18 @@ LS1046A RDB boards supports the following features:
 Supported Features
 ==================
 
-NXP LS1046A RDB board default configuration supports the following
-hardware features:
+.. zephyr:board-supported-hw::
 
-+-----------+------------+--------------------------------------+
-| Interface | Controller | Driver/Component                     |
-+===========+============+======================================+
-| GIC-400   | on-chip    | GICv2 interrupt controller           |
-+-----------+------------+--------------------------------------+
-| ARM TIMER | on-chip    | System Clock                         |
-+-----------+------------+--------------------------------------+
-| UART      | on-chip    | NS16550 compatible serial port       |
-+-----------+------------+--------------------------------------+
+.. note::
 
-Other hardware features have not been enabled yet for this board.
-
-The default configuration can be found in the defconfig file for NON-SMP:
-
-    :zephyr_file:`boards/nxp/ls1046ardb/ls1046ardb_ls1046a_defconfig`
-
-Or for SMP running on all four CPU Cores:
-
-	:zephyr_file:`boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_4cores_defconfig`
-
-Or for SMP running on 2 CPU Cores (Core2 and Core3):
-
-	:zephyr_file:`boards/nxp/ls1046ardb/ls1046ardb_ls1046a_smp_defconfig`
-
-There are two serial port on the board: uart1 and uart2, Zephyr is using
-uart2 as serial console.
+   There are two serial ports on the board: uart1 and uart2. Zephyr is using
+   uart2 as serial console.
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Use the following configuration to run basic Zephyr applications and
 kernel tests on LS1046A RDB board. For example, with the :zephyr:code-sample:`synchronization` sample:
 
@@ -204,6 +183,9 @@ Debugging
 LS1046A RDB board includes one JTAG connector on board, connect it to
 CodeWarrior TAP for debugging.
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 References
 ==========
 
diff --git a/boards/nxp/mcx_n9xx_evk/CMakeLists.txt b/boards/nxp/mcx_n9xx_evk/CMakeLists.txt
new file mode 100644
index 00000000000..df4c3939ca7
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/CMakeLists.txt
@@ -0,0 +1,8 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_library()
+zephyr_library_sources(board.c)
diff --git a/boards/nxp/mcx_n9xx_evk/Kconfig b/boards/nxp/mcx_n9xx_evk/Kconfig
new file mode 100644
index 00000000000..cde6c0aea5f
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/Kconfig
@@ -0,0 +1,5 @@
+# Copyright 2024-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MCX_N9XX_EVK
+	select BOARD_EARLY_INIT_HOOK
diff --git a/boards/nxp/mcx_n9xx_evk/Kconfig.defconfig b/boards/nxp/mcx_n9xx_evk/Kconfig.defconfig
new file mode 100644
index 00000000000..286acdad25f
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/Kconfig.defconfig
@@ -0,0 +1,24 @@
+# Copyright 2024-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_MCX_N9XX_EVK
+
+config NET_L2_ETHERNET
+	default y if NETWORKING
+
+if SD_STACK
+
+# SD stack requires larger main stack size
+config MAIN_STACK_SIZE
+	default 1536
+
+endif
+
+if BOOTLOADER_MCUBOOT
+choice MCUBOOT_BOOTLOADER_MODE
+	# Board only supports MCUBoot via "upgrade only" method:
+	default MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY
+endchoice
+endif #BOOTLOADER_MCUBOOT
+
+endif
diff --git a/boards/nxp/mcx_n9xx_evk/Kconfig.mcx_n9xx_evk b/boards/nxp/mcx_n9xx_evk/Kconfig.mcx_n9xx_evk
new file mode 100644
index 00000000000..b0f19694fa8
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/Kconfig.mcx_n9xx_evk
@@ -0,0 +1,7 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MCX_N9XX_EVK
+	select SOC_MCXN947_CPU0 if BOARD_MCX_N9XX_EVK_MCXN947_CPU0 || BOARD_MCX_N9XX_EVK_MCXN947_CPU0_QSPI
+	select SOC_MCXN947_CPU1 if BOARD_MCX_N9XX_EVK_MCXN947_CPU1
+	select SOC_PART_NUMBER_MCXN947VDF
diff --git a/boards/nxp/mcx_n9xx_evk/Kconfig.sysbuild b/boards/nxp/mcx_n9xx_evk/Kconfig.sysbuild
new file mode 100644
index 00000000000..4625c7d2929
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/Kconfig.sysbuild
@@ -0,0 +1,6 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+choice MCUBOOT_MODE
+	default MCUBOOT_MODE_OVERWRITE_ONLY
+endchoice
diff --git a/boards/nxp/mcx_n9xx_evk/board.c b/boards/nxp/mcx_n9xx_evk/board.c
new file mode 100644
index 00000000000..4d6c1f6d694
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/board.c
@@ -0,0 +1,445 @@
+/*
+ * Copyright 2024-2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/init.h>
+#include <zephyr/device.h>
+#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
+#include <fsl_clock.h>
+#include <fsl_spc.h>
+#include <soc.h>
+#if CONFIG_USB_DC_NXP_EHCI
+#include "usb_phy.h"
+#include "usb.h"
+
+/* USB PHY configuration */
+#define BOARD_USB_PHY_D_CAL     (0x04U)
+#define BOARD_USB_PHY_TXCAL45DP (0x07U)
+#define BOARD_USB_PHY_TXCAL45DM (0x07U)
+
+usb_phy_config_struct_t usbPhyConfig = {
+	BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM,
+};
+#endif
+
+/* Board xtal frequency in Hz */
+#define BOARD_XTAL0_CLK_HZ                        24000000U
+/* Core clock frequency: 150MHz */
+#define CLOCK_INIT_CORE_CLOCK                     150000000U
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/* Update Active mode voltage for OverDrive mode. */
+void power_mode_od(void)
+{
+	/* Set the DCDC VDD regulator to 1.2 V voltage level */
+	spc_active_mode_dcdc_option_t opt = {
+		.DCDCVoltage       = kSPC_DCDC_OverdriveVoltage,
+		.DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength,
+	};
+	SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &opt);
+
+	/* Set the LDO_CORE VDD regulator to 1.2 V voltage level */
+	spc_active_mode_core_ldo_option_t ldo_opt = {
+		.CoreLDOVoltage       = kSPC_CoreLDO_OverDriveVoltage,
+		.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength,
+	};
+	SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &ldo_opt);
+
+	/* Specifies the 1.2V operating voltage for the SRAM's read/write timing margin */
+	spc_sram_voltage_config_t cfg = {
+		.operateVoltage       = kSPC_sramOperateAt1P2V,
+		.requestVoltageUpdate = true,
+	};
+	SPC_SetSRAMOperateVoltage(SPC0, &cfg);
+}
+
+#if CONFIG_FLASH_MCUX_FLEXSPI_NOR || CONFIG_FLASH_MCUX_FLEXSPI_XIP
+__ramfunc static void enable_cache64(void)
+{
+	/* Make sure the FlexSPI clock is enabled before configuring the FlexSPI cache. */
+	SYSCON->AHBCLKCTRLSET[0] |= SYSCON_AHBCLKCTRL0_FLEXSPI_MASK;
+
+	/* Set command to invalidate all ways and write GO bit to initiate command */
+	CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK;
+	CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK;
+	/* Wait until the command completes */
+	while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U) {
+	}
+	/* Enable cache, enable write buffer */
+	CACHE64_CTRL0->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK | CACHE64_CTRL_CCR_ENCACHE_MASK);
+
+	/* configure reg0, reg1 to cover the whole FlexSPI
+	 * reg 0 covers the space where Zephyr resides in case of XIP from FlexSPI
+	 * reg 1 covers the storage space in case of XIP from FlexSPI
+	 */
+	CACHE64_POLSEL0->REG0_TOP = 0x7FFC00;
+	CACHE64_POLSEL0->REG1_TOP = 0x0;
+	CACHE64_POLSEL0->POLSEL =
+		(CACHE64_POLSEL_POLSEL_REG0_POLICY(1) | CACHE64_POLSEL_POLSEL_REG1_POLICY(0) |
+		 CACHE64_POLSEL_POLSEL_REG2_POLICY(0));
+
+	__ISB();
+	__DSB();
+}
+#endif
+
+void board_early_init_hook(void)
+{
+	power_mode_od();
+
+	/* Enable SCG clock */
+	CLOCK_EnableClock(kCLOCK_Scg);
+
+	/* FRO OSC setup - begin, enable the FRO for safety switching */
+
+	/* Switch to FRO 12M first to ensure we can change the clock setting */
+	CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
+
+	/* Configure Flash wait-states to support 1.2V voltage level and 150000000Hz frequency */
+	FMU0->FCTRL = (FMU0->FCTRL & ~((uint32_t)FMU_FCTRL_RWSC_MASK)) | (FMU_FCTRL_RWSC(0x3U));
+
+	/* Enable FRO HF(48MHz) output */
+	CLOCK_SetupFROHFClocking(48000000U);
+
+#ifdef CONFIG_FLASH_MCUX_FLEXSPI_XIP
+	/* Call function flexspi_clock_safe_config() to move FleXSPI clock to a stable
+	 * clock source when updating the PLL if in XIP (execute code from FlexSPI memory
+	 */
+	flexspi_clock_safe_config();
+#endif
+
+	/* Set up PLL0 */
+	const pll_setup_t pll0Setup = {
+		.pllctrl = SCG_APLLCTRL_SOURCE(1U) | SCG_APLLCTRL_SELI(27U) |
+			   SCG_APLLCTRL_SELP(13U),
+		.pllndiv = SCG_APLLNDIV_NDIV(8U),
+		.pllpdiv = SCG_APLLPDIV_PDIV(1U),
+		.pllmdiv = SCG_APLLMDIV_MDIV(50U),
+		.pllRate = 150000000U
+	};
+	/* Configure PLL0 to the desired values */
+	CLOCK_SetPLL0Freq(&pll0Setup);
+	/* PLL0 Monitor is disabled */
+	CLOCK_SetPll0MonitorMode(kSCG_Pll0MonitorDisable);
+
+	/* Switch MAIN_CLK to PLL0 */
+	CLOCK_AttachClk(kPLL0_to_MAIN_CLK);
+
+	/* Set AHBCLKDIV divider to value 1 */
+	CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U);
+
+	CLOCK_SetupExtClocking(BOARD_XTAL0_CLK_HZ);
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1))
+	/* < Set up PLL1 */
+	const pll_setup_t pll1_Setup = {
+		.pllctrl = SCG_SPLLCTRL_SOURCE(1U) | SCG_SPLLCTRL_SELI(3U) |
+				 SCG_SPLLCTRL_SELP(1U),
+		.pllndiv = SCG_SPLLNDIV_NDIV(25U),
+		.pllpdiv = SCG_SPLLPDIV_PDIV(10U),
+		.pllmdiv = SCG_SPLLMDIV_MDIV(256U),
+		.pllRate = 24576000U};
+
+	/* Configure PLL1 to the desired values */
+	CLOCK_SetPLL1Freq(&pll1_Setup);
+	/* Set PLL1 CLK0 divider to value 1 */
+	CLOCK_SetClkDiv(kCLOCK_DivPLL1Clk0, 1U);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm0))
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom0Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm1))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom1Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm2))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom2Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM2);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm3))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom3Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM3);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm4))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom4Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM4);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm5))
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom5Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM5);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm6))
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom6Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM6);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm7))
+	/* Configure input clock to be able to reach the datasheet specified SPI band rate. */
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom7Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM7);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm8))
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom8Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM8);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcomm9))
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcom9Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_DIV_to_FLEXCOMM9);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(os_timer))
+	CLOCK_AttachClk(kCLK_1M_to_OSTIMER);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio0))
+	CLOCK_EnableClock(kCLOCK_Gpio0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio1))
+	CLOCK_EnableClock(kCLOCK_Gpio1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio2))
+	CLOCK_EnableClock(kCLOCK_Gpio2);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio3))
+	CLOCK_EnableClock(kCLOCK_Gpio3);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpio4))
+	CLOCK_EnableClock(kCLOCK_Gpio4);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dac0))
+	SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlDac0);
+	CLOCK_SetClkDiv(kCLOCK_DivDac0Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_to_DAC0);
+
+	CLOCK_EnableClock(kCLOCK_Dac0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dac1))
+	SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlDac1);
+	CLOCK_SetClkDiv(kCLOCK_DivDac1Clk, 1u);
+	CLOCK_AttachClk(kFRO_HF_to_DAC1);
+
+	CLOCK_EnableClock(kCLOCK_Dac1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet))
+	CLOCK_AttachClk(kNONE_to_ENETRMII);
+	CLOCK_EnableClock(kCLOCK_Enet);
+	SYSCON0->PRESETCTRL2 = SYSCON_PRESETCTRL2_ENET_RST_MASK;
+	SYSCON0->PRESETCTRL2 &= ~SYSCON_PRESETCTRL2_ENET_RST_MASK;
+	/* rmii selection for this board */
+	SYSCON->ENET_PHY_INTF_SEL = SYSCON_ENET_PHY_INTF_SEL_PHY_SEL(1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wwdt0))
+	CLOCK_SetClkDiv(kCLOCK_DivWdt0Clk, 1u);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer0))
+	CLOCK_SetClkDiv(kCLOCK_DivCtimer0Clk, 1U);
+	CLOCK_AttachClk(kPLL0_to_CTIMER0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer1))
+	CLOCK_SetClkDiv(kCLOCK_DivCtimer1Clk, 1U);
+	CLOCK_AttachClk(kPLL0_to_CTIMER1);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer2))
+	CLOCK_SetClkDiv(kCLOCK_DivCtimer2Clk, 1U);
+	CLOCK_AttachClk(kPLL0_to_CTIMER2);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer3))
+	CLOCK_SetClkDiv(kCLOCK_DivCtimer3Clk, 1U);
+	CLOCK_AttachClk(kPLL0_to_CTIMER3);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ctimer4))
+	CLOCK_SetClkDiv(kCLOCK_DivCtimer4Clk, 1U);
+	CLOCK_AttachClk(kPLL0_to_CTIMER4);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexcan0))
+	CLOCK_SetClkDiv(kCLOCK_DivFlexcan0Clk, 1U);
+	CLOCK_AttachClk(kFRO_HF_to_FLEXCAN0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usdhc0))
+	CLOCK_SetClkDiv(kCLOCK_DivUSdhcClk, 1u);
+	CLOCK_AttachClk(kFRO_HF_to_USDHC);
+#endif
+
+#if CONFIG_FLASH_MCUX_FLEXSPI_NOR || CONFIG_FLASH_MCUX_FLEXSPI_XIP
+	/* Setup the FlexSPI clock */
+	flexspi_clock_set_freq(MCUX_FLEXSPI_CLK,
+			       DT_PROP(DT_NODELABEL(w25q64jwtbjq), spi_max_frequency));
+	enable_cache64();
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(smartdma))
+	CLOCK_EnableClock(kCLOCK_Smartdma);
+	RESET_PeripheralReset(kSMART_DMA_RST_SHIFT_RSTn);
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(video_sdma))
+	/* Drive CLKOUT from main clock, divided by 25 to yield 6MHz clock
+	 * The camera will use this clock signal to generate
+	 * PCLK, HSYNC, and VSYNC
+	 */
+	CLOCK_AttachClk(kMAIN_CLK_to_CLKOUT);
+	CLOCK_SetClkDiv(kCLOCK_DivClkOut, 25U);
+#endif
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(vref))
+	CLOCK_EnableClock(kCLOCK_Vref);
+	SPC_EnableActiveModeAnalogModules(SPC0, kSPC_controlVref);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpadc0))
+	CLOCK_SetClkDiv(kCLOCK_DivAdc0Clk, 1U);
+	CLOCK_AttachClk(kFRO_HF_to_ADC0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb0)) && (CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS)
+	CLOCK_AttachClk(kCLK_48M_to_USB0);
+	CLOCK_EnableClock(kCLOCK_Usb0Ram);
+	CLOCK_EnableClock(kCLOCK_Usb0Fs);
+	CLOCK_EnableUsbfsClock();
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && (CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)
+	SPC0->ACTIVE_VDELAY = 0x0500;
+	/* Change the power DCDC to 1.8v (By default, DCDC is 1.8V), CORELDO to 1.1v (By default,
+	 * CORELDO is 1.0V)
+	 */
+	SPC0->ACTIVE_CFG &= ~SPC_ACTIVE_CFG_CORELDO_VDD_DS_MASK;
+	SPC0->ACTIVE_CFG |= SPC_ACTIVE_CFG_DCDC_VDD_LVL(0x3) | SPC_ACTIVE_CFG_CORELDO_VDD_LVL(0x3) |
+			    SPC_ACTIVE_CFG_SYSLDO_VDD_DS_MASK | SPC_ACTIVE_CFG_DCDC_VDD_DS(0x2u);
+	/* Wait until it is done */
+	while (SPC0->SC & SPC_SC_BUSY_MASK) {
+	};
+	if (0u == (SCG0->LDOCSR & SCG_LDOCSR_LDOEN_MASK)) {
+		SCG0->TRIM_LOCK = 0x5a5a0001U;
+		SCG0->LDOCSR |= SCG_LDOCSR_LDOEN_MASK;
+		/* wait LDO ready */
+		while (0U == (SCG0->LDOCSR & SCG_LDOCSR_VOUT_OK_MASK)) {
+		};
+	}
+	SYSCON->AHBCLKCTRLSET[2] |= SYSCON_AHBCLKCTRL2_USB_HS_MASK |
+				    SYSCON_AHBCLKCTRL2_USB_HS_PHY_MASK;
+	SCG0->SOSCCFG &= ~(SCG_SOSCCFG_RANGE_MASK | SCG_SOSCCFG_EREFS_MASK);
+	/* xtal = 20 ~ 30MHz */
+	SCG0->SOSCCFG = (1U << SCG_SOSCCFG_RANGE_SHIFT) | (1U << SCG_SOSCCFG_EREFS_SHIFT);
+	SCG0->SOSCCSR |= SCG_SOSCCSR_SOSCEN_MASK;
+	while (1) {
+		if (SCG0->SOSCCSR & SCG_SOSCCSR_SOSCVLD_MASK) {
+			break;
+		}
+	}
+	SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK |
+			      SYSCON_CLOCK_CTRL_CLKIN_ENA_FM_USBH_LPT_MASK;
+	CLOCK_EnableClock(kCLOCK_UsbHs);
+	CLOCK_EnableClock(kCLOCK_UsbHsPhy);
+	CLOCK_EnableUsbhsPhyPllClock(kCLOCK_Usbphy480M, BOARD_XTAL0_CLK_HZ);
+	CLOCK_EnableUsbhsClock();
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && CONFIG_USB_DC_NXP_EHCI
+	USB_EhciPhyInit(kUSB_ControllerEhci0, BOARD_XTAL0_CLK_HZ, &usbPhyConfig);
+#endif
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpcmp0))
+	CLOCK_SetClkDiv(kCLOCK_DivCmp0FClk, 1U);
+	CLOCK_AttachClk(kFRO12M_to_CMP0F);
+	SPC_EnableActiveModeAnalogModules(SPC0, (kSPC_controlCmp0 | kSPC_controlCmp0Dac));
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpcmp2))
+	CLOCK_SetClkDiv(kCLOCK_DivCmp2FClk, 1U);
+	CLOCK_AttachClk(kFRO12M_to_CMP2F);
+	SPC_EnableActiveModeAnalogModules(SPC0, (kSPC_controlCmp2 | kSPC_controlCmp2Dac));
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptmr0))
+
+/*
+ * Clock Select Decides what input source the lptmr will clock from
+ *
+ * 0 <- 12MHz FRO
+ * 1 <- 16K FRO
+ * 2 <- 32K OSC
+ * 3 <- Output from the OSC_SYS
+ */
+#if DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x0
+	CLOCK_SetupClockCtrl(kCLOCK_FRO12MHZ_ENA);
+#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x1
+	CLOCK_SetupClk16KClocking(kCLOCK_Clk16KToVsys);
+#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x2
+	CLOCK_SetupOsc32KClocking(kCLOCK_Osc32kToVsys);
+#elif DT_PROP(DT_NODELABEL(lptmr0), clk_source) == 0x3
+	/* Value here should not exceed 25MHZ when using lptmr */
+	CLOCK_SetupExtClocking(MHZ(24));
+	CLOCK_SetupClockCtrl(kCLOCK_CLKIN_ENA_FM_USBH_LPT);
+#endif /* DT_PROP(DT_NODELABEL(lptmr0), clk_source) */
+
+#endif /* DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lptmr0)) */
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexio0))
+	CLOCK_SetClkDiv(kCLOCK_DivFlexioClk, 1u);
+	CLOCK_AttachClk(kPLL0_to_FLEXIO);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(i3c1), okay)
+	/* Enable 1MHz clock. */
+	SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK;
+
+	CLOCK_SetClkDiv(kCLOCK_DivI3c1FClk, DT_PROP(DT_NODELABEL(i3c1), clk_divider));
+	CLOCK_SetClkDiv(kCLOCK_DivI3c1FClkS, DT_PROP(DT_NODELABEL(i3c1), clk_divider_slow));
+	CLOCK_SetClkDiv(kCLOCK_DivI3c1FClkStc, DT_PROP(DT_NODELABEL(i3c1), clk_divider_tc));
+
+	/* Attach PLL0 clock to I3C, 150MHz / 6 = 25MHz. */
+	CLOCK_AttachClk(kPLL0_to_I3C1FCLK);
+	CLOCK_AttachClk(kCLK_1M_to_I3C1FCLKS);
+	CLOCK_AttachClk(kI3C1FCLK_to_I3C1FCLKSTC);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(sc_timer), okay)
+	/* attach FRO HF to SCT */
+	CLOCK_SetClkDiv(kCLOCK_DivSctClk, 1u);
+	CLOCK_AttachClk(kFRO_HF_to_SCT);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai0))
+	CLOCK_SetClkDiv(kCLOCK_DivSai0Clk, 1u);
+	CLOCK_AttachClk(kPLL1_CLK0_to_SAI0);
+	CLOCK_EnableClock(kCLOCK_Sai0);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sai1))
+	CLOCK_SetClkDiv(kCLOCK_DivSai1Clk, 1u);
+	CLOCK_AttachClk(kPLL1_CLK0_to_SAI1);
+	CLOCK_EnableClock(kCLOCK_Sai1);
+#endif
+
+	/* Set SystemCoreClock variable. */
+	SystemCoreClock = CLOCK_INIT_CORE_CLOCK;
+}
diff --git a/boards/nxp/mcx_n9xx_evk/board.cmake b/boards/nxp/mcx_n9xx_evk/board.cmake
new file mode 100644
index 00000000000..5845dcdeaf5
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/board.cmake
@@ -0,0 +1,37 @@
+#
+# Copyright 2024-2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if(CONFIG_SOC_MCXN947_CPU0 OR CONFIG_SECOND_CORE_MCUX)
+  board_runner_args(jlink "--device=MCXN947_M33_0" "--reset-after-load")
+  board_runner_args(linkserver  "--device=MCXN947:MCX-N9XX-EVK")
+  if(CONFIG_SECOND_CORE_MCUX)
+    board_runner_args(linkserver  "--core=all")
+  else()
+    board_runner_args(linkserver  "--core=cm33_core0")
+  endif()
+  board_runner_args(linkserver  "--override=/device/memory/1/flash-driver=MCXN9xx_S.cfx")
+  board_runner_args(linkserver  "--override=/device/memory/1/location=0x10000000")
+  # Linkserver v1.4.85 and earlier do not include the secure regions in the
+  # MCXN947 memory map, so we add them here
+  board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x30000000\",\
+                               \"size\":\"0x00060000\",\"type\":\"RAM\"\}")
+  board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x30060000\",\
+                               \"size\":\"0x00008000\",\"type\":\"RAM\"\}")
+  # Define region for peripherals
+  board_runner_args(linkserver "--override=/device/memory/-=\{\"location\":\"0x50000000\",\
+                               \"size\":\"0x00140000\",\"type\":\"RAM\"\}")
+elseif(CONFIG_SOC_MCXN947_CPU1)
+  board_runner_args(jlink "--device=MCXN947_M33_1" "--reset-after-load")
+  board_runner_args(linkserver  "--device=MCXN947:MCX-N9XX-EVK")
+  board_runner_args(linkserver  "--core=cm33_core1")
+endif()
+
+# Pyocd support added with the NXP.MCXN947_DFP.17.0.0.pack CMSIS Pack
+board_runner_args(pyocd "--target=mcxn947")
+
+include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
diff --git a/boards/nxp/mcx_n9xx_evk/board.yml b/boards/nxp/mcx_n9xx_evk/board.yml
new file mode 100644
index 00000000000..a6b49fd7d43
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/board.yml
@@ -0,0 +1,9 @@
+board:
+  name: mcx_n9xx_evk
+  full_name: MCX-N9XX-EVK
+  vendor: nxp
+  socs:
+  - name: mcxn947
+    variants:
+    - name: qspi
+      cpucluster: 'cpu0'
diff --git a/boards/nxp/mcx_n9xx_evk/doc/index.rst b/boards/nxp/mcx_n9xx_evk/doc/index.rst
new file mode 100644
index 00000000000..c6fab3fd9a0
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/doc/index.rst
@@ -0,0 +1,294 @@
+.. zephyr:board:: mcx_n9xx_evk
+
+Overview
+********
+
+MCX-N9XX-EVK is a full featured evaluation kit for prototyping of MCX N94 / N54
+MCUs. They offer industry standard headers for access to the MCU’s I/Os,
+integrated open-standard serial interfaces and an on-board MCU-Link debugger
+with power measurement capability.  MCX N Series are high-performance, low-power
+microcontrollers with intelligent peripherals and accelerators providing
+multi-tasking capabilities and performance efficiency.
+
+Hardware
+********
+
+- MCX-N947 Dual Arm Cortex-M33 microcontroller running at 150 MHz
+- 2MB dual-bank on chip Flash
+- 512 KB RAM
+- External Quad SPI flash over FlexSPI
+- USB high-speed (Host/Device) with on-chip HS PHY.
+- USB full-speed (Host/Device) with on-chip FS PHY.
+- 10x LP Flexcomms each supporting SPI, I2C, UART
+- FlexCAN with FD, I3Cs, SAI
+- 1x Ethernet with QoS
+- On-board MCU-Link debugger with CMSIS-DAP
+- Arduino Header, FlexIO/LCD Header, mikroBUS, M.2
+
+For more information about the MCX-N947 SoC and MCX-N9XX-EVK board, see:
+
+- `MCX-N947 SoC Website`_
+- `MCX-N947 Datasheet`_
+- `MCX-N947 Reference Manual`_
+- `MCX-N9XX-EVK Website`_
+- `MCX-N9XX-EVK Board User Manual`_
+- `MCX-N9XX-EVK Schematics`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Shields for Supported Features
+==============================
+Some features in the table above are tested with Zephyr shields.  These shields
+are tested on this board:
+- :ref:`lcd_par_s035` - supports the Display interface.  This board uses the
+MIPI_DBI interface of the shield, connected to the FlexIO on-chip peripheral.
+
+Dual Core samples
+*****************
+
++-----------+-------------------+----------------------+
+| Core      | Boot Address      | Comment              |
++===========+===================+======================+
+| CPU0      | 0x10000000[1856K] | primary core flash   |
++-----------+-------------------+----------------------+
+| CPU1      | 0x101d0000[192K]  | secondary core flash |
++-----------+-------------------+----------------------+
+
++----------+------------------+-----------------------+
+| Memory   | Address[Size]    | Comment               |
++==========+==================+=======================+
+| srama    | 0x20000000[320k] | CPU0 ram              |
++----------+------------------+-----------------------+
+| sramg    | 0x20050000[64k]  | CPU1 ram              |
++----------+------------------+-----------------------+
+| sramh    | 0x20060000[32k]  | Shared memory         |
++----------+------------------+-----------------------+
+
+Targets available
+==================
+
+The default configuration file
+:zephyr_file:`boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_defconfig`
+only enables the first core. CPU0 is the only target that can run standalone.
+
+CPU1 does not work without CPU0 enabling it.
+
+To enable CPU1, create System Build application project and enable the
+second core with config :kconfig:option:`CONFIG_SECOND_CORE_MCUX`.
+
+Please have a look at some already enabled samples:
+
+- :zephyr:code-sample:`ipc-static-vrings`
+- :zephyr:code-sample:`openamp`
+- :zephyr:code-sample:`mbox`
+- :zephyr:code-sample:`mbox_data`
+
+Connections and IOs
+===================
+
+The MCX-N947 SoC has 6 gpio controllers and has pinmux registers which
+can be used to configure the functionality of a pin.
+
++------------+-----------------+----------------------------+
+| Name       | Function        | Usage                      |
++============+=================+============================+
+| P0_PIO1_8  | UART            | UART RX cpu0               |
++------------+-----------------+----------------------------+
+| P1_PIO1_9  | UART            | UART TX cpu0               |
++------------+-----------------+----------------------------+
+| P4_PIO4_3  | UART            | UART RX cpu1               |
++------------+-----------------+----------------------------+
+| P4_PIO4_2  | UART            | UART TX cpu1               |
++------------+-----------------+----------------------------+
+
+System Clock
+============
+
+The MCX-N947 SoC is configured to use PLL0 running at 150MHz as a source for
+the system clock.
+
+Serial Port
+===========
+
+The MCX-N9XX-EVK SoC has 10 FLEXCOMM interfaces for serial communication.
+Flexcomm 4 is configured as UART for the console.
+
+Ethernet
+========
+To use networking samples with the Ethernet jack, change jumper JP13 to pins 2-3.
+
+Programming and Debugging
+*************************
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Configuring a Debug Probe
+=========================
+
+A debug probe is used for both flashing and debugging the board. This board is
+configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
+
+Using LinkServer
+----------------
+
+LinkServer is the default runner for this board, and supports the factory
+default MCU-Link firmware. Follow the instructions in
+:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link
+firmware. This only needs to be done if the default onboard debug circuit
+firmware was changed. To put the board in ``ISP mode`` to program the firmware,
+short jumper JP24.
+
+Using J-Link
+------------
+
+There are two options. The onboard debug circuit can be updated with Segger
+J-Link firmware by following the instructions in
+:ref:`mcu-link-jlink-onboard-debug-probe`.
+To be able to program the firmware, you need to put the board in ``ISP mode``
+by shortening the jumper JP24.
+The second option is to attach a :ref:`jlink-external-debug-probe` to the
+20-pin SWD connector (J11) of the board. Additionally, the jumper JP6 must
+be shorted.
+For both options use the ``-r jlink`` option with west to use the jlink runner.
+
+.. code-block:: console
+
+   west flash -r jlink
+
+Configuring a Console
+=====================
+
+Connect a USB cable from your PC to J5, and use the serial terminal of your choice
+(minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Flashing
+========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: mcx_n9xx_evk/mcxn947/cpu0
+   :goals: flash
+
+Open a serial terminal, reset the board (press the RESET button), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build vX.X.X ***
+   Hello World! mcx_n9xx_evk/mcxn947/cpu0
+
+Building a dual-core image
+==========================
+
+The dual-core samples are run using ``mcx_n9xx_evk/mcxn947/cpu0`` target.
+
+Images built for ``mcx_n9xx_evk/mcxn947/cpu1`` will be loaded from flash
+and executed on the second core when :kconfig:option:`CONFIG_SECOND_CORE_MCUX` is selected.
+
+For an example of building for both cores with System Build, see
+:zephyr:code-sample:`ipc-static-vrings`
+
+Here is an example for the :zephyr:code-sample:`mbox_data` application.
+
+.. zephyr-app-commands::
+   :app: zephyr/samples/drivers/mbox_data
+   :board: mcx_n9xx_evk/mcxn947/cpu0
+   :goals: flash
+   :west-args: --sysbuild
+
+Flashing to QSPI
+================
+
+In order to load Zephyr application from QSPI, program a bootloader like
+MCUboot bootloader to internal flash. Here are the steps for the
+:zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :app: zephyr/samples/hello_world
+   :board: mcx_n9xx_evk/mcxn947/cpu0/qspi
+   :gen-args: --sysbuild -- -DSB_CONFIG_BOOTLOADER_MCUBOOT=y
+   :goals: flash
+
+Open a serial terminal, reset the board (press the RESET button), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+  *** Booting MCUboot vX.X.X ***
+  *** Using Zephyr OS build vX.X.X ***
+  I: Starting bootloader
+  I: Primary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
+  I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
+  I: Boot source: none
+  I: Image index: 0, Swap type: none
+  I: Bootloader chainload address offset: 0x0
+  I: Jumping to the first image slot
+  *** Booting Zephyr OS build vX.X.X ***
+  Hello World! mcx_n9xx_evk/mcxn947/cpu0/qspi
+
+Debugging
+=========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: mcx_n9xx_evk/mcxn947/cpu0
+   :goals: debug
+
+Open a serial terminal, step through the application in your debugger, and you
+should see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build vX.X.X ***
+   Hello World! mcx_n9xx_evk/mcxn947/cpu0
+
+Debugging a dual-core image
+---------------------------
+
+For dual core builds, the secondary core should be placed into a loop,
+then a debugger can be attached.
+As a reference please see (`AN13264`_, section 4.2.3 for more information).
+The reference is for the RT1170 but similar technique can be also used here.
+
+Troubleshooting
+===============
+
+.. include:: ../../common/segger-ecc-systemview.rst
+   :start-after: segger-ecc-systemview
+
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
+.. _MCX-N947 SoC Website:
+   https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-n-series-microcontrollers/mcx-n94x-54x-highly-integrated-multicore-mcus-with-on-chip-accelerators-intelligent-peripherals-and-advanced-security:MCX-N94X-N54X
+
+.. _MCX-N947 Datasheet:
+   https://www.nxp.com/docs/en/data-sheet/MCXNx4xDS.pdf
+
+.. _MCX-N947 Reference Manual:
+   https://www.nxp.com/webapp/Download?colCode=MCXNX4XRM
+
+.. _MCX-N9XX-EVK Website:
+   https://www.nxp.com/design/design-center/development-boards-and-designs/MCX-N9XX-EVK
+
+.. _MCX-N9XX-EVK Board User Manual:
+   https://www.nxp.com/webapp/Download?colCode=UM12036
+
+.. _MCX-N9XX-EVK Schematics:
+   https://www.nxp.com/webapp/Download?colCode=SPF-55276
+
+.. _AN13264:
+   https://www.nxp.com/docs/en/application-note/AN13264.pdf
diff --git a/boards/nxp/mcx_n9xx_evk/doc/mcx_n9xx_evk.webp b/boards/nxp/mcx_n9xx_evk/doc/mcx_n9xx_evk.webp
new file mode 100644
index 00000000000..a6f5cef1a97
Binary files /dev/null and b/boards/nxp/mcx_n9xx_evk/doc/mcx_n9xx_evk.webp differ
diff --git a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk-pinctrl.dtsi b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk-pinctrl.dtsi
new file mode 100644
index 00000000000..f0e3db91cf9
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk-pinctrl.dtsi
@@ -0,0 +1,273 @@
+/*
+ * Copyright 2024-2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <nxp/mcx/MCXN947VDF-pinctrl.h>
+
+&pinctrl {
+	pinmux_flexcomm1_lpspi: pinmux_flexcomm1_lpspi {
+		group0 {
+			pinmux = <FC1_P0_PIO0_24>,
+				<FC1_P1_PIO0_25>,
+				<FC1_P2_PIO0_26>,
+				<FC1_P3_PIO0_27>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
+
+	pinmux_flexcomm2_lpi2c: pinmux_flexcomm2_lpi2c {
+		group0 {
+			pinmux = <FC2_P0_PIO4_0>,
+				<FC2_P1_PIO4_1>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+			bias-pull-up;
+			drive-open-drain;
+		};
+	};
+
+	pinmux_flexcomm3_lpi2c: pimux_flexcomm3_lpi2c {
+		group0 {
+			pinmux = <FC3_P0_PIO1_0>,
+				<FC3_P1_PIO1_1>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+			bias-pull-up;
+			drive-open-drain;
+		};
+	};
+
+	pinmux_flexcomm2_lpuart: pinmux_flexcomm2_lpuart {
+		group0 {
+			pinmux = <FC2_P2_PIO4_2>,
+				<FC2_P3_PIO4_3>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
+
+	pinmux_flexcomm4_lpuart: pinmux_flexcomm4_lpuart {
+		group0 {
+			pinmux = <FC4_P0_PIO1_8>,
+				<FC4_P1_PIO1_9>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
+
+	pinmux_flexspi: pinmux_flexspi {
+		group0 {
+			pinmux = <FLEXSPI0_A_SS0_b_PIO3_0>,
+					<FLEXSPI0_A_SCLK_PIO3_7>,
+					<FLEXSPI0_A_DQS_PIO3_6>,
+					<FLEXSPI0_A_DATA0_PIO3_8>,
+					<FLEXSPI0_A_DATA1_PIO3_9>;
+			input-enable;
+			slew-rate = "fast";
+			drive-strength = "low";
+		};
+		group1 {
+			pinmux = <FLEXSPI0_A_DATA2_PIO3_10>,
+					<FLEXSPI0_A_DATA3_PIO3_11>;
+			input-enable;
+			slew-rate = "fast";
+			drive-strength = "low";
+			bias-pull-up;
+		};
+	};
+
+	pinmux_dac0: pinmux_dac0 {
+		group0 {
+			pinmux = <DAC0_OUT_PIO4_2>;
+			drive-strength = "low";
+			slew-rate = "fast";
+		};
+	};
+
+	pinmux_sai1: pinmux_sai1 {
+		group0 {
+			pinmux = <SAI1_TX_BCLK_PIO3_16>,
+				<SAI1_TX_FS_PIO3_17>,
+				<SAI1_TXD0_PIO3_20>,
+				<SAI1_RX_FS_PIO3_19>,
+				<SAI1_RX_BCLK_PIO3_18>,
+				<SAI1_RXD0_PIO3_21>;
+			drive-strength = "high";
+			slew-rate = "fast";
+			input-enable;
+		};
+	};
+
+	pinmux_enet_qos: pinmux_enet_qos {
+		mdio_group {
+			pinmux = <ENET0_MDC_PIO1_20>,
+				<ENET0_MDIO_PIO1_21>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+		mac_group {
+			pinmux = <ENET0_RXDV_PIO1_13>,
+				<ENET0_RXD0_PIO1_14>,
+				<ENET0_RXD1_PIO1_15>,
+				<ENET0_TX_CLK_PIO1_4>,
+				<ENET0_TXEN_PIO1_5>,
+				<ENET0_TXD0_PIO1_6>,
+				<ENET0_TXD1_PIO1_7>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
+
+	pinmux_flexpwm1_pwm0: pinmux_flexpwm1_pwm0 {
+		group0 {
+			pinmux = <PWM1_A0_PIO2_6>,
+				<PWM1_B0_PIO2_7>;
+			slew-rate = "fast";
+			drive-strength = "low";
+		};
+	};
+
+	pinmux_flexpwm1_pwm1: pinmux_flexpwm1_pwm1 {
+		group0 {
+			pinmux = <PWM1_A1_PIO2_4>,
+				<PWM1_B1_PIO2_5>;
+			slew-rate = "fast";
+			drive-strength = "low";
+		};
+	};
+
+	pinmux_flexpwm1_pwm2: pinmux_flexpwm1_pwm2 {
+		group0 {
+			pinmux = <PWM1_A2_PIO2_2>,
+				<PWM1_B2_PIO2_3>;
+			slew-rate = "fast";
+			drive-strength = "low";
+		};
+	};
+
+	pinmux_usdhc0: pinmux_usdhc0 {
+		group0 {
+			pinmux = <SDHC0_CMD_PIO2_5>,
+			       <SDHC0_D0_PIO2_3>,
+			       <SDHC0_D1_PIO2_2>,
+			       <SDHC0_D2_PIO2_7>,
+			       <SDHC0_D3_PIO2_6>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			bias-pull-up;
+			input-enable;
+		};
+		group1 {
+			pinmux = <SDHC0_CLK_PIO2_4>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
+
+	pinmux_lpadc0: pinmux_lpadc0 {
+		group0 {
+			pinmux = <ADC0_A2_PIO4_23>,
+				<ADC0_A1_PIO4_15>,
+				<ADC0_B1_PIO4_19>;
+			slew-rate = "fast";
+			drive-strength = "low";
+		};
+	};
+
+	pinmux_lpcmp2: pinmux_lpcmp2 {
+		group0 {
+			pinmux = <CMP2_IN0_PIO1_2>;
+			drive-strength = "low";
+			slew-rate = "fast";
+			bias-pull-up;
+		};
+	};
+
+	pinmux_flexcan0: pinmux_flexcan0 {
+		group0 {
+			pinmux = <CAN0_TXD_PIO1_18>,
+				<CAN0_RXD_PIO1_19>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
+
+	pinmux_i3c1: pinmux_i3c1 {
+		group0 {
+			pinmux = <I3C1_SDA_PIO1_16>,
+				<I3C1_SCL_PIO1_17>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+			bias-pull-up;
+		};
+		group1 {
+			pinmux = <I3C1_PUR_PIO1_11>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
+
+	pinmux_sctimer: pinmux_sctimer {
+		group0 {
+			pinmux = <SCT0_OUT0_PIO2_2>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+	};
+
+	pinmux_flexio_lcd: pinmux_flexio_lcd {
+		group0 {
+			pinmux = <FLEXIO0_D16_PIO2_8>,
+				<FLEXIO0_D17_PIO2_9>,
+				<FLEXIO0_D18_PIO2_10>,
+				<FLEXIO0_D19_PIO2_11>,
+				<FLEXIO0_D20_PIO4_12>,
+				<FLEXIO0_D21_PIO4_13>,
+				<FLEXIO0_D22_PIO4_14>,
+				<FLEXIO0_D23_PIO4_15>,
+				<FLEXIO0_D24_PIO4_16>,
+				<FLEXIO0_D25_PIO4_17>,
+				<FLEXIO0_D26_PIO4_18>,
+				<FLEXIO0_D27_PIO4_19>,
+				<FLEXIO0_D28_PIO4_20>,
+				<FLEXIO0_D29_PIO4_21>,
+				<FLEXIO0_D30_PIO4_22>,
+				<FLEXIO0_D31_PIO4_23>,
+				<PIO0_7>,
+				<PIO0_12>,
+				<PIO4_7>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+		};
+		group1 {
+			pinmux = <FLEXIO0_D0_PIO0_8>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+			bias-pull-up;
+		};
+		group2 {
+			pinmux = <FLEXIO0_D1_PIO0_9>;
+			slew-rate = "slow";
+			drive-strength = "low";
+			input-enable;
+			bias-pull-up;
+		};
+	};
+};
diff --git a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk.dtsi b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk.dtsi
new file mode 100644
index 00000000000..e85fcff4ffd
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk.dtsi
@@ -0,0 +1,265 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "mcx_n9xx_evk-pinctrl.dtsi"
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	aliases{
+		led0 = &red_led;
+		led1 = &green_led;
+		led2 = &blue_led;
+		sw0 = &user_button_2;
+		sw1 = &user_button_3;
+		sdhc0 = &usdhc0;
+		mcuboot-button0 = &user_button_2;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		green_led: led_1 {
+			gpios = <&gpio3 2 GPIO_ACTIVE_HIGH>;
+			label = "Green LED";
+			status = "disabled";
+		};
+		blue_led: led_2 {
+			gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>;
+			label = "Blue LED";
+			status = "disabled";
+		};
+		red_led: led_3 {
+			gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+			label = "Red LED";
+			status = "disabled";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button_2: button_0 {
+			label = "User SW2";
+			gpios = <&gpio1 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_0>;
+			status = "disabled";
+		};
+		user_button_3: button_1 {
+			label = "User SW3";
+			gpios = <&gpio0 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_1>;
+			status = "disabled";
+		};
+	};
+
+	/*
+	 * This node describes the GPIO pins of the LCD-PAR-S035 panel 8080 interface.
+	 */
+	nxp_lcd_8080_connector: lcd-8080-connector {
+		compatible = "nxp,lcd-8080";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map =	<9  0 &gpio4 6 0>,	/* Pin 9, LCD touch INT */
+				<10  0 &gpio1 11 0>,	/* Pin 10, LCD backlight control */
+				<11  0 &gpio4 7 0>;	/* Pin 11, LCD and touch reset */
+	};
+};
+
+&flexcomm1_lpspi1 {
+	pinctrl-0 = <&pinmux_flexcomm1_lpspi>;
+	pinctrl-names = "default";
+};
+
+nxp_8080_touch_panel_i2c: &flexcomm2_lpi2c2 {
+	pinctrl-0 = <&pinmux_flexcomm2_lpi2c>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&flexcomm2_lpuart2 {
+	current-speed = <115200>;
+	pinctrl-0 = <&pinmux_flexcomm2_lpuart>;
+	pinctrl-names = "default";
+};
+
+&flexcomm4_lpuart4 {
+	current-speed = <115200>;
+	pinctrl-0 = <&pinmux_flexcomm4_lpuart>;
+	pinctrl-names = "default";
+};
+
+&flexcomm3_lpi2c3 {
+	pinctrl-0 = <&pinmux_flexcomm3_lpi2c>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+/*
+ * MCXN947 board uses OS timer as the kernel timer
+ * In case we need to switch to SYSTICK timer, then
+ * replace &os_timer with &systick
+ */
+&os_timer {
+	status = "disabled";
+};
+
+&systick {
+	status = "okay";
+};
+
+&sram {
+	sramg: memory@20050000 {
+		compatible = "mmio-sram";
+		reg = <0x20050000 DT_SIZE_K(64)>;
+	};
+	sramh: memory@20060000 {
+		compatible = "mmio-sram";
+		reg = <0x20060000 DT_SIZE_K(32)>;
+	};
+};
+
+&flash {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/*
+		 * Partition sizes must be aligned
+		 * to the flash memory sector size of 8KB.
+		 */
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 DT_SIZE_K(80)>;
+		};
+		/* For the MCUBoot "upgrade only" method,
+		 * the slot sizes must be equal.
+		 */
+		slot0_partition: partition@14000 {
+			label = "image-0";
+			reg = <0x00014000 DT_SIZE_K(984)>;
+		};
+		slot1_partition: partition@10A000 {
+			label = "image-1";
+			reg = <0x0010A000 DT_SIZE_K(984)>;
+		};
+		/* storage_partition is placed in WINBOND flash memory*/
+	};
+};
+
+&flexspi {
+	pinctrl-0 = <&pinmux_flexspi>;
+	pinctrl-names = "default";
+	ahb-prefetch;
+	ahb-bufferable;
+	ahb-cacheable;
+	ahb-read-addr-opt;
+	combination-mode;
+	rx-clock-source = <1>;
+
+	/* WINBOND flash memory*/
+	w25q64jwtbjq: w25q64jwtbjq@0 {
+		compatible = "nxp,imx-flexspi-nor";
+		status = "disabled";
+		size = <67108864>;
+		reg = <0>;
+		spi-max-frequency = <133000000>;
+		jedec-id = [ef 40 17];
+		erase-block-size = <4096>;
+		write-block-size = <1>;
+		cs-interval-unit = <1>;
+		cs-interval = <2>;
+		cs-hold-time = <3>;
+		cs-setup-time = <3>;
+		data-valid-time = <2>;
+		column-space = <0>;
+	};
+};
+
+&dac0 {
+	pinctrl-0 = <&pinmux_dac0>;
+	pinctrl-names = "default";
+};
+
+&sai1 {
+	pinctrl-0 = <&pinmux_sai1>;
+	pinctrl-names = "default";
+};
+
+&enet {
+	pinctrl-0 = <&pinmux_enet_qos>;
+	pinctrl-names = "default";
+};
+
+&enet_mac {
+	phy-connection-type = "rmii";
+	zephyr,random-mac-address;
+	phy-handle = <&phy>;
+};
+
+&enet_mdio {
+	phy: ethernet-phy@0 {
+		compatible = "ethernet-phy";
+		reg = <0>;
+		status = "okay";
+	};
+};
+
+&flexpwm1_pwm0 {
+	pinctrl-0 = <&pinmux_flexpwm1_pwm0>;
+	pinctrl-names = "default";
+};
+
+&usdhc0 {
+	pinctrl-0 = <&pinmux_usdhc0>;
+	pinctrl-1 = <&pinmux_usdhc0>;
+	pinctrl-2 = <&pinmux_usdhc0>;
+	cd-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
+	pwr-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+	pinctrl-names = "default", "slow", "med";
+	no-1-8-v;
+};
+
+&lpadc0 {
+	pinctrl-0 = <&pinmux_lpadc0>;
+	pinctrl-names = "default";
+};
+
+zephyr_mipi_dbi_parallel: &flexio0_lcd {
+	/* DMA channels 0, muxed to FlexIO TX */
+	dmas = <&edma0 0 61>;
+	dma-names = "tx";
+	shifters-count = <8>;
+	timers-count = <1>;
+	enwr-pin = <1>;
+	rd-pin = <0>;
+	data-pin-start = <16>;
+	reset-gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>;
+	cs-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>;
+	rs-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+	pinctrl-0 = <&pinmux_flexio_lcd>;
+	pinctrl-names = "default";
+};
+
+&lpcmp2 {
+	pinctrl-0 = <&pinmux_lpcmp2>;
+	pinctrl-names = "default";
+};
+
+&i3c1 {
+	pinctrl-0 = <&pinmux_i3c1>;
+	pinctrl-names = "default";
+};
+
+&flexcan0 {
+	pinctrl-0 = <&pinmux_flexcan0>;
+	pinctrl-names = "default";
+};
+
+&sc_timer {
+	pinctrl-0 = <&pinmux_sctimer>;
+	pinctrl-names = "default";
+};
diff --git a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.dts b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.dts
new file mode 100644
index 00000000000..ec7c9926045
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.dts
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "mcx_n9xx_evk_mcxn947_cpu0.dtsi"
+
+/ {
+	model = "NXP MCX-N9XX-EVK board";
+	compatible = "nxp,mcxn947", "nxp,mcx";
+};
diff --git a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.dtsi b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.dtsi
new file mode 100644
index 00000000000..9f849fa3249
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.dtsi
@@ -0,0 +1,243 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Common dts file to enable supported features for CPU 0.
+ * This file is included by both the default variant
+ * which is run from internal flash and the QSPI variant.
+ */
+/dts-v1/;
+
+#include <nxp/nxp_mcxn94x.dtsi>
+#include "mcx_n9xx_evk.dtsi"
+
+/ {
+	cpus {
+		/delete-node/ cpu@1;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash;
+		zephyr,flash-controller = &fmu;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,uart-mcumgr = &flexcomm4_lpuart4;
+		zephyr,console = &flexcomm4_lpuart4;
+		zephyr,shell-uart = &flexcomm4_lpuart4;
+		zephyr,canbus = &flexcan0;
+		zephyr,code-cpu1-partition = &slot1_partition;
+	};
+
+	aliases{
+		watchdog0 = &wwdt0;
+		pwm-0 = &flexpwm1_pwm0;
+		pwm-1 = &sc_timer;
+		rtc = &rtc;
+	};
+};
+
+/*
+ * Default for this board is to allocate SRAM0-5 to cpu0 but the
+ * application can have an application specific device tree to
+ * allocate the SRAM0-7 differently.
+ *
+ * For example, SRAM0-6 could be allocated to cpu0 with only SRAM7
+ * for cpu1. This would require the value of sram0 to have a DT_SIZE_K
+ * of 384. You would have to make updates to cpu1 sram settings as well.
+ */
+&sram0 {
+	compatible = "mmio-sram";
+	reg = <0x20000000 DT_SIZE_K(320)>;
+};
+
+&mbox {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&green_led {
+	status = "okay";
+};
+
+&red_led {
+	status = "okay";
+};
+
+&user_button_2 {
+	status = "okay";
+};
+
+&edma0 {
+	status = "okay";
+};
+
+&flexcomm1 {
+	status = "okay";
+};
+
+&flexcomm1_lpspi1 {
+	status = "okay";
+};
+
+&flexcomm2 {
+	status = "okay";
+};
+
+&flexcomm2_lpi2c2 {
+	status = "okay";
+};
+
+/*
+ *LPFLEXCOMM supports UART and I2C on the same instance, enable this for
+ * LFLEXCOMM2
+ */
+&flexcomm2_lpuart2 {
+	status = "okay";
+};
+
+&flexcomm4 {
+	status = "okay";
+};
+
+&flexcomm4_lpuart4 {
+	status = "okay";
+};
+
+&flexcomm3 {
+	status = "okay";
+};
+
+&flexcomm3_lpi2c3 {
+	status = "okay";
+};
+
+&flexspi {
+	status = "okay";
+};
+
+&w25q64jwtbjq {
+	status = "okay";
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		storage_partition: partition@0 {
+			label = "storage";
+			reg = <0x0 DT_SIZE_M(8)>;
+		};
+	};
+};
+
+&dac0 {
+	status = "okay";
+};
+
+&enet {
+	status = "okay";
+};
+
+&enet_mac {
+	status = "okay";
+};
+
+&enet_mdio {
+	status = "okay";
+};
+
+&wwdt0 {
+	status = "okay";
+};
+
+&flexpwm1_pwm0 {
+	status = "okay";
+};
+
+&flexcan0 {
+	status = "okay";
+};
+
+&ctimer0 {
+	status = "okay";
+};
+
+&usdhc0 {
+	status = "okay";
+	sdmmc {
+		compatible = "zephyr,sdmmc-disk";
+		disk-name = "SD";
+		status = "okay";
+	};
+};
+
+&vref {
+	status = "okay";
+};
+
+&lpadc0 {
+	status = "okay";
+};
+
+zephyr_udc0: &usb1 {
+	status = "okay";
+	phy-handle = <&usbphy1>;
+};
+
+&usbphy1 {
+	status = "okay";
+	tx-d-cal = <4>;
+	tx-cal-45-dp-ohms = <7>;
+	tx-cal-45-dm-ohms = <7>;
+};
+
+&lpcmp2 {
+	status = "okay";
+};
+
+&lptmr0 {
+	status = "okay";
+};
+
+&i3c1 {
+	status = "okay";
+};
+
+&flexio0 {
+	status = "okay";
+};
+
+&mrt0_channel0 {
+	status = "okay";
+};
+
+&rtc {
+	status = "okay";
+};
+
+&sc_timer {
+	status = "okay";
+};
+
+&sai1 {
+	status = "okay";
+};
diff --git a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.yaml b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.yaml
new file mode 100644
index 00000000000..b7f1b052e2e
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0.yaml
@@ -0,0 +1,34 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mcx_n9xx_evk/mcxn947/cpu0
+name: NXP MCX-N9XX-EVK (CPU0)
+type: mcu
+arch: arm
+ram: 320
+flash: 2048
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - adc
+  - can
+  - counter
+  - dac
+  - dma
+  - flash
+  - gpio
+  - i2c
+  - i2s
+  - i3c
+  - pwm
+  - regulator
+  - rtc
+  - sdhc
+  - spi
+  - usb_device
+  - watchdog
+vendor: nxp
diff --git a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_defconfig b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_defconfig
new file mode 100644
index 00000000000..f200a450d2f
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_defconfig
@@ -0,0 +1,17 @@
+#
+# Copyright 2024-2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_GPIO=y
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable TrustZone-M
+CONFIG_TRUSTED_EXECUTION_SECURE=y
diff --git a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.dts b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.dts
new file mode 100644
index 00000000000..e9d45587553
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.dts
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "mcx_n9xx_evk_mcxn947_cpu0.dtsi"
+
+/delete-node/ &slot0_partition;
+/delete-node/ &slot1_partition;
+/delete-node/ &storage_partition;
+
+/ {
+	model = "NXP MCX-N9XX-EVK board, QSPI variant";
+	compatible = "nxp,mcxn947", "nxp,mcx";
+
+	chosen {
+		zephyr,flash = &w25q64jwtbjq;
+	};
+
+};
+
+&w25q64jwtbjq {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		slot0_partition: partition@0 {
+			label = "image-0";
+			reg = <0x00000000 DT_SIZE_M(3)>;
+		};
+		slot1_partition: partition@300000 {
+			label = "image-1";
+			reg = <0x00300000 DT_SIZE_M(3)>;
+		};
+		storage_partition: partition@600000 {
+			label = "storage";
+			reg = <0x00600000 DT_SIZE_M(2)>;
+		};
+	};
+};
diff --git a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.yaml b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.yaml
new file mode 100644
index 00000000000..c2b1422dfe4
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi.yaml
@@ -0,0 +1,32 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mcx_n9xx_evk/mcxn947/cpu0/qspi
+name: NXP MCX-N9XX-EVK QSPI (CPU0)
+type: mcu
+arch: arm
+ram: 320
+flash: 8192
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - adc
+  - can
+  - counter
+  - dac
+  - dma
+  - flash
+  - gpio
+  - i2c
+  - i3c
+  - pwm
+  - regulator
+  - sdhc
+  - spi
+  - usb_device
+  - watchdog
+vendor: nxp
diff --git a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi_defconfig b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi_defconfig
new file mode 100644
index 00000000000..f200a450d2f
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu0_qspi_defconfig
@@ -0,0 +1,17 @@
+#
+# Copyright 2024-2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_GPIO=y
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable TrustZone-M
+CONFIG_TRUSTED_EXECUTION_SECURE=y
diff --git a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu1.dts b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu1.dts
new file mode 100644
index 00000000000..68ee11d2659
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu1.dts
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_mcxn94x.dtsi>
+#include "mcx_n9xx_evk.dtsi"
+
+/ {
+	model = "NXP MCX-N9XX-EVK board";
+	compatible = "nxp,mcxn947", "nxp,mcx";
+
+	cpus {
+		/delete-node/ cpu@0;
+	};
+
+	chosen {
+		zephyr,sram = &sramg;
+		zephyr,flash = &flash;
+		zephyr,flash-controller = &fmu;
+		zephyr,code-partition = &slot1_partition;
+		zephyr,console = &flexcomm2_lpuart2;
+		zephyr,shell-uart = &flexcomm2_lpuart2;
+	};
+};
+
+&flexcomm2 {
+	status = "okay";
+};
+
+&flexcomm2_lpuart2 {
+	status = "okay";
+};
+
+&mbox {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&green_led {
+	status = "okay";
+};
+
+&red_led {
+	status = "okay";
+};
+
+&user_button_2 {
+	status = "okay";
+};
+
+&edma0 {
+	status = "okay";
+};
diff --git a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu1.yaml b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu1.yaml
new file mode 100644
index 00000000000..0aa11cb627f
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu1.yaml
@@ -0,0 +1,19 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mcx_n9xx_evk/mcxn947/cpu1
+name: NXP FRDM MCXN947 (CPU1)
+type: mcu
+arch: arm
+ram: 64
+flash: 200
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - dma
+  - gpio
+vendor: nxp
diff --git a/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu1_defconfig b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu1_defconfig
new file mode 100644
index 00000000000..6e944c1f0f6
--- /dev/null
+++ b/boards/nxp/mcx_n9xx_evk/mcx_n9xx_evk_mcxn947_cpu1_defconfig
@@ -0,0 +1,13 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_GPIO=y
+
+CONFIG_USE_DT_CODE_PARTITION=y
diff --git a/boards/nxp/mcxw72_evk/Kconfig.mcxw72_evk b/boards/nxp/mcxw72_evk/Kconfig.mcxw72_evk
new file mode 100644
index 00000000000..8b851a30e80
--- /dev/null
+++ b/boards/nxp/mcxw72_evk/Kconfig.mcxw72_evk
@@ -0,0 +1,6 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MCXW72_EVK
+	select SOC_MCXW727C_CPU0 if BOARD_MCXW72_EVK_MCXW727C_CPU0
+	select SOC_PART_NUMBER_MCXW727CMFTA
diff --git a/boards/nxp/mcxw72_evk/board.cmake b/boards/nxp/mcxw72_evk/board.cmake
new file mode 100644
index 00000000000..6282eec263b
--- /dev/null
+++ b/boards/nxp/mcxw72_evk/board.cmake
@@ -0,0 +1,8 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(linkserver "--device=MCXW727C:MCX-W72-EVK")
+board_runner_args(jlink "--device=MCXW727" "--reset-after-load")
+
+include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/nxp/mcxw72_evk/board.yml b/boards/nxp/mcxw72_evk/board.yml
new file mode 100644
index 00000000000..d63ad4b623e
--- /dev/null
+++ b/boards/nxp/mcxw72_evk/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: mcxw72_evk
+  full_name: MCXW72-EVK
+  vendor: nxp
+  socs:
+    - name: mcxw727c
diff --git a/boards/nxp/mcxw72_evk/doc/index.rst b/boards/nxp/mcxw72_evk/doc/index.rst
new file mode 100644
index 00000000000..6cb8885094b
--- /dev/null
+++ b/boards/nxp/mcxw72_evk/doc/index.rst
@@ -0,0 +1,161 @@
+.. zephyr:board:: mcxw72_evk
+
+Overview
+********
+
+The MCXW72-EVK
+
+The MCX W72x family features a 96 MHz Arm® Cortex®-M33 core coupled with a
+multiprotocol radio subsystem supporting Matter, Thread, Zigbee and
+Bluetooth LE. The independent radio subsystem, with a dedicated core and
+memory, offloads the main CPU, preserving it for the primary application and
+allowing firmware updates to support future wireless standards.
+
+Hardware
+********
+
+- MCXW72 Arm Cortex-M33 microcontroller running up to 96 MHz
+- 2MB on-chip Flash memory unit
+- 256 KB TCM RAM
+- On-board MCU-Link debugger with CMSIS-DAP
+
+For more information about the MCXW72 SoC and MCXW72-EVK board, see:
+
+- `MCXW72 SoC Website`_
+- `MCXW72-EVK Website`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Fetch Binary Blobs
+******************
+
+To support Bluetooth, mcxw72_evk requires fetching binary blobs, which can be
+achieved by running the following command:
+
+.. code-block:: console
+
+   west blobs fetch hal_nxp
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Configuring a Debug Probe
+=========================
+
+A debug probe is used for both flashing and debugging the board. This board is
+configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
+
+Using LinkServer
+----------------
+
+Linkserver is the default runner for this board, and supports the factory
+default MCU-Link firmware. Follow the instructions in
+:ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram the default MCU-Link
+firmware. This only needs to be done if the default onboard debug circuit
+firmware was changed. To put the board in ``DFU mode`` to program the firmware,
+short jumper JP20.
+
+Using J-Link
+------------
+
+There are two options. The onboard debug circuit can be updated with Segger
+J-Link firmware by following the instructions in
+:ref:`mcu-link-jlink-onboard-debug-probe`.
+To be able to program the firmware, you need to put the board in ``DFU mode``
+by shortening the jumper JP20.
+The second option is to attach a :ref:`jlink-external-debug-probe` to the
+10-pin SWD connector (J16) of the board.
+For both options use the ``-r jlink`` option with west to use the jlink runner.
+
+.. code-block:: console
+
+   west flash -r jlink
+
+Configuring a Console
+=====================
+
+Connect a USB cable from your PC to J14, and use the serial terminal of your choice
+(minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Flashing
+========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: mcxw72_evk/mcxw727c/cpu0
+   :goals: flash
+
+Open a serial terminal, reset the board (press the RESET button), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v3.7.0-xxx-xxxx ***
+   Hello World! mcxw72_evk/mcxw727c/cpu0
+
+Debugging
+=========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: mcxw72_evk/mcxw727c/cpu0
+   :goals: debug
+
+Open a serial terminal, step through the application in your debugger, and you
+should see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v3.7.0-xxx-xxxx ***
+   Hello World! mcxw72_evk/mcxw727c/cpu0
+
+Bluetooth
+=========
+
+BLE functionality requires to fetch binary blobs, so make sure to follow
+the ``Fetch Binary Blobs`` section first.
+
+Two images must be written to the board: one for the host (CM33 core0) and one for the NBU (CM33 core1).
+- To flash the application (CM33) refer to the ``Flashing`` section above.
+- To flash the NBU, follow the instructions below:
+
+.. code-block:: console
+
+	JLinkExe -device MCXW727C_CORE1 -if SWD -speed 4000 -autoconnect 1
+	J-Link>loadbin <path to nbu blob file> 0x0
+
+Troubleshooting
+===============
+
+.. include:: ../../common/segger-ecc-systemview.rst
+   :start-after: segger-ecc-systemview
+
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
+References
+**********
+
+.. target-notes::
+
+.. _MCXW72 SoC Website:
+   https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/general-purpose-mcus/mcx-arm-cortex-m/mcx-w-series-microcontrollers/mcx-w72x-secure-and-ultra-low-power-mcus-for-matter-thread-zigbee-and-bluetooth-le:MCX-W72X
+
+.. _MCXW72-EVK Website:
diff --git a/boards/nxp/mcxw72_evk/doc/mcxw72_evk.webp b/boards/nxp/mcxw72_evk/doc/mcxw72_evk.webp
new file mode 100644
index 00000000000..cfa1e647037
Binary files /dev/null and b/boards/nxp/mcxw72_evk/doc/mcxw72_evk.webp differ
diff --git a/boards/nxp/mcxw72_evk/mcxw72_evk-pinctrl.dtsi b/boards/nxp/mcxw72_evk/mcxw72_evk-pinctrl.dtsi
new file mode 100644
index 00000000000..08289d5e5c3
--- /dev/null
+++ b/boards/nxp/mcxw72_evk/mcxw72_evk-pinctrl.dtsi
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/mcx/MCXW727CMFTA-pinctrl.h>
+
+&pinctrl {
+	pinmux_lpuart0: pinmux_lpuart0 {
+		group0 {
+			pinmux = <LPUART0_RX_PTA16>, <LPUART0_TX_PTA17>;
+			drive-strength = "low";
+			slew-rate = "fast";
+		};
+	};
+
+	pinmux_lpuart1: pinmux_lpuart1 {
+		group0 {
+			pinmux = <LPUART1_RX_PTC2>, <LPUART1_TX_PTC3>;
+			drive-strength = "low";
+			slew-rate = "fast";
+		};
+	};
+
+	pinmux_tpm0: pinmux_tpm0 {
+		group0 {
+			pinmux = <TPM0_CH0_PTA21>, <TPM0_CH1_PTA20>,
+				<TPM0_CH2_PTA19>, <TPM0_CH3_PTA18>;
+			drive-strength = "low";
+			slew-rate = "fast";
+		};
+	};
+
+	pinmux_lpspi1: pinmux_lpspi1 {
+		group0 {
+			pinmux = <LPSPI1_SIN_PTB1>,
+				 <LPSPI1_SOUT_PTB3>,
+				 <LPSPI1_SCK_PTB2>,
+				 <LPSPI1_PCS0_PTB0>;
+			slew-rate = "fast";
+			drive-strength = "low";
+		};
+	};
+
+	pinmux_flexcan: pinmux_flexcan {
+		group0 {
+			pinmux = <CAN0_RX_PTC5>, <CAN0_TX_PTC4>;
+			slew-rate = "slow";
+			drive-strength = "low";
+		};
+	};
+
+	pinmux_lpadc0: pinmux_lpadc0 {
+		group0 {
+			pinmux = <ADC0_A6_PTD2>,
+				<ADC0_B6_PTD3>,
+				<ADC0_B5_PTD1>;
+			drive-strength = "low";
+			slew-rate = "fast";
+		};
+	};
+
+	pinmux_lpi2c0: pinmux_lpi2c0 {
+		group0 {
+			pinmux = <LPI2C0_SCL_PTA19>,
+				<LPI2C0_SDA_PTA18>;
+			drive-strength = "low";
+			slew-rate = "fast";
+			drive-open-drain;
+		};
+	};
+
+	pinmux_lpi2c1: pinmux_lpi2c1 {
+		group0 {
+			pinmux = <LPI2C1_SCL_PTB5>,
+				<LPI2C1_SDA_PTB4>;
+			drive-strength = "low";
+			slew-rate = "fast";
+			drive-open-drain;
+		};
+	};
+};
diff --git a/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.dts b/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.dts
new file mode 100644
index 00000000000..41e634bfecf
--- /dev/null
+++ b/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.dts
@@ -0,0 +1,162 @@
+/*
+ * Copyright 2024-2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_mcxw72.dtsi>
+#include "mcxw72_evk-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "NXP MCXW72-EVK board";
+
+	aliases {
+		led0 = &blue_led;
+		blue-pwm-led = &blue_pwm_led;
+		green-pwm-led = &green_pwm_led;
+		red-pwm-led = &red_pwm_led;
+		sw0 = &user_button_0;
+	};
+
+	chosen {
+		zephyr,flash = &flash;
+		zephyr,flash-controller = &fmu;
+		zephyr,code-partition = &code_partition;
+		zephyr,sram = &stcm0;
+		zephyr,console = &lpuart1;
+		zephyr,shell-uart = &lpuart1;
+		zephyr,uart-pipe = &lpuart0;
+		zephyr,canbus = &flexcan0;
+		zephyr,bt-c2h-uart = &lpuart0;
+	};
+
+	user_led {
+		compatible = "gpio-leds";
+		blue_led: led {
+			gpios = <&gpioc 1 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+		blue_pwm_led: pwm_led_0 {
+			pwms = <&tpm0 1 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
+		};
+		green_pwm_led: pwm_led_1 {
+			pwms = <&tpm0 2 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
+		};
+		red_pwm_led: pwm_led_2 {
+			pwms = <&tpm0 0 PWM_MSEC(20) PWM_POLARITY_INVERTED>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button_0: button_0 {
+			label = "User SW3";
+			gpios = <&gpioc 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_0>;
+			status = "okay";
+		};
+	};
+};
+
+&gpioa {
+	status = "okay";
+};
+
+&gpiob {
+	status = "okay";
+};
+
+&gpioc {
+	status = "okay";
+};
+
+&lpuart0 {
+	current-speed = <115200>;
+	status =  "okay";
+	pinctrl-0 = <&pinmux_lpuart0>;
+	pinctrl-names = "default";
+};
+
+&lpuart1 {
+	current-speed = <115200>;
+	status =  "okay";
+	pinctrl-0 = <&pinmux_lpuart1>;
+	pinctrl-names = "default";
+};
+
+&flash {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		code_partition: partition@0 {
+			reg = <0x0 DT_SIZE_K(2032)>;
+		};
+
+		storage_partition: partition@1FC000 {
+			reg = <0x1FC000 DT_SIZE_K(16)>;
+		};
+	};
+};
+
+&fmu {
+	status = "okay";
+};
+
+&tpm0 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_tpm0>;
+	pinctrl-names = "default";
+};
+
+&lptmr0 {
+	status = "okay";
+};
+
+&lpspi1 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_lpspi1>;
+	pinctrl-names = "default";
+};
+
+&flexcan0 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_flexcan>;
+	pinctrl-names = "default";
+
+	can-transceiver {
+		max-bitrate = <5000000>;
+	};
+};
+
+&vref {
+	status = "okay";
+};
+
+&adc0 {
+	pinctrl-0 = <&pinmux_lpadc0>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&lpi2c1 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_lpi2c1>;
+	pinctrl-names = "default";
+
+	accelerometer: accelerometer@19 {
+		status = "okay";
+		compatible = "nxp,fxls8974";
+		reg = <0x19>;
+	};
+};
+
+&rtc {
+	status = "okay";
+};
diff --git a/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.yaml b/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.yaml
new file mode 100644
index 00000000000..f3f9a54cf1d
--- /dev/null
+++ b/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0.yaml
@@ -0,0 +1,19 @@
+identifier: mcxw72_evk/mcxw727c/cpu0
+name: NXP MCXW72_EVK
+type: mcu
+arch: arm
+ram: 264
+flash: 2048
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - adc
+  - can
+  - counter
+  - gpio
+  - i2c
+  - pinctrl
+  - pwm
+  - spi
+  - uart
diff --git a/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0_defconfig b/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0_defconfig
new file mode 100644
index 00000000000..19a6063f677
--- /dev/null
+++ b/boards/nxp/mcxw72_evk/mcxw72_evk_mcxw727c_cpu0_defconfig
@@ -0,0 +1,12 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_ARM_MPU=y
+CONFIG_TRUSTED_EXECUTION_SECURE=y
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y
diff --git a/boards/nxp/mimxrt1010_evk/CMakeLists.txt b/boards/nxp/mimxrt1010_evk/CMakeLists.txt
index 260448d63c7..8c1028b5f36 100644
--- a/boards/nxp/mimxrt1010_evk/CMakeLists.txt
+++ b/boards/nxp/mimxrt1010_evk/CMakeLists.txt
@@ -20,7 +20,7 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER)
     zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1)
     zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024)
     set(RT1010_BOARD_DIR
-      "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1010")
+      "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1010")
     zephyr_library_sources(${RT1010_BOARD_DIR}/xip/evkmimxrt1010_flexspi_nor_config.c)
     zephyr_library_include_directories(${RT1010_BOARD_DIR}/xip)
   endif()
diff --git a/boards/nxp/mimxrt1010_evk/doc/index.rst b/boards/nxp/mimxrt1010_evk/doc/index.rst
index 7b2d5d8c5ef..66809750946 100644
--- a/boards/nxp/mimxrt1010_evk/doc/index.rst
+++ b/boards/nxp/mimxrt1010_evk/doc/index.rst
@@ -52,7 +52,7 @@ This platform has the following external memories:
 +--------------------+------------+-------------------------------------+
 | Device             | Controller | Status                              |
 +====================+============+=====================================+
-| AT25SF128A         | FLEXSPI    | Enabled via flash configurationn    |
+| AT25SF128A         | FLEXSPI    | Enabled via flash configuration     |
 |                    |            | block, which sets up FLEXSPI at     |
 |                    |            | boot time.                          |
 +--------------------+------------+-------------------------------------+
@@ -60,44 +60,15 @@ This platform has the following external memories:
 Supported Features
 ==================
 
-The mimxrt1010_evk board configuration supports the hardware features listed
-below.  For additional features not yet supported, please also refer to the
-:zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
-NXP prioritizes enabling the superset board with NXP's Full Platform Support for
-Zephyr.  Therefore, the mimxrt1064_evk board may have additional features
-already supported, which can also be re-used on this mimxrt1010_evk board:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| GPT       | on-chip    | gpt                                 |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| PIT       | on-chip    | pit                                 |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/mimxrt1010_evk/mimxrt1010_evk_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   For additional features not yet supported, please also refer to the
+   :zephyr:board:`mimxrt1064_evk`, which is the superset board in NXP's i.MX RT10xx family.
+   NXP prioritizes enabling the superset board with NXP's Full Platform Support for
+   Zephyr.  Therefore, the mimxrt1064_evk board may have additional features
+   already supported, which can also be re-used on this mimxrt1010_evk board:
 
 Connections and I/Os
 ====================
@@ -152,6 +123,8 @@ and the remaining are not used.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 This board supports 3 debug host tools. Please install your preferred host
 tool, then follow the instructions in `Configuring a Debug Probe`_ to
 configure the board appropriately.
@@ -208,6 +181,8 @@ see the following message in the terminal:
 
     Hello World! mimxrt1010_evk
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
 
 .. _MIMXRT1010-EVK Website:
    https://www.nxp.com/MIMXRT1010-EVK
diff --git a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.yaml b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.yaml
index f9c8719a8de..b205958cf29 100644
--- a/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.yaml
+++ b/boards/nxp/mimxrt1010_evk/mimxrt1010_evk.yaml
@@ -12,7 +12,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 16384
 supported:
diff --git a/boards/nxp/mimxrt1015_evk/CMakeLists.txt b/boards/nxp/mimxrt1015_evk/CMakeLists.txt
index 115153b462b..599383f6aae 100644
--- a/boards/nxp/mimxrt1015_evk/CMakeLists.txt
+++ b/boards/nxp/mimxrt1015_evk/CMakeLists.txt
@@ -19,7 +19,7 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER)
     zephyr_compile_definitions(XIP_BOOT_HEADER_ENABLE=1)
     zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024)
     set(RT1015_BOARD_DIR
-      "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1015")
+      "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1015")
     zephyr_library_sources(${RT1015_BOARD_DIR}/xip/evkmimxrt1015_flexspi_nor_config.c)
     zephyr_library_include_directories(${RT1015_BOARD_DIR}/xip)
   endif()
diff --git a/boards/nxp/mimxrt1015_evk/doc/index.rst b/boards/nxp/mimxrt1015_evk/doc/index.rst
index a4bf7bf6756..dcfe584a5ba 100644
--- a/boards/nxp/mimxrt1015_evk/doc/index.rst
+++ b/boards/nxp/mimxrt1015_evk/doc/index.rst
@@ -52,7 +52,7 @@ This platform has the following external memories:
 +--------------------+------------+-------------------------------------+
 | Device             | Controller | Status                              |
 +====================+============+=====================================+
-| AT25SF128A         | FLEXSPI    | Enabled via flash configurationn    |
+| AT25SF128A         | FLEXSPI    | Enabled via flash configuration     |
 |                    |            | block, which sets up FLEXSPI at     |
 |                    |            | boot time.                          |
 +--------------------+------------+-------------------------------------+
@@ -60,42 +60,15 @@ This platform has the following external memories:
 Supported Features
 ==================
 
-The mimxrt1015_evk board configuration supports the hardware features listed
-below.  For additional features not yet supported, please also refer to the
-:zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
-NXP prioritizes enabling the superset board with NXP's Full Platform Support for
-Zephyr.  Therefore, the mimxrt1064_evk board may have additional features
-already supported, which can also be re-used on this mimxrt1015_evk board:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC                                 |
-+-----------+------------+-------------------------------------+
-| GPT       | on-chip    | gpt                                 |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/mimxrt1015_evk/mimxrt1015_evk_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   For additional features not yet supported, please also refer to the
+   :zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
+   NXP prioritizes enabling the superset board with NXP's Full Platform Support for
+   Zephyr.  Therefore, the mimxrt1064_evk board may have additional features
+   already supported, which can also be re-used on this mimxrt1015_evk board.
 
 Connections and I/Os
 ====================
@@ -154,6 +127,8 @@ and the remaining are not used.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 This board supports 3 debug host tools. Please install your preferred host
 tool, then follow the instructions in `Configuring a Debug Probe`_ to
 configure the board appropriately.
@@ -211,6 +186,8 @@ see the following message in the terminal:
     ***** Booting Zephyr OS v1.14.0-rc1-1297-g312d75f2459e *****
     Hello World! mimxrt1015_evk
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
 
 .. _MIMXRT1015-EVK Website:
    https://www.nxp.com/support/developer-resources/run-time-software/i.mx-developer-resources/i.mx-rt1015-evaluation-kit:MIMXRT1015-EVK
diff --git a/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.yaml b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.yaml
index 80afd63da22..8f6d9713bc6 100644
--- a/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.yaml
+++ b/boards/nxp/mimxrt1015_evk/mimxrt1015_evk.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
 flash: 16384
 supported:
diff --git a/boards/nxp/mimxrt1020_evk/CMakeLists.txt b/boards/nxp/mimxrt1020_evk/CMakeLists.txt
index 63a6d289e6d..56275e10ce7 100644
--- a/boards/nxp/mimxrt1020_evk/CMakeLists.txt
+++ b/boards/nxp/mimxrt1020_evk/CMakeLists.txt
@@ -13,7 +13,7 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER)
      "update your flash configuration or device configuration data blocks")
   endif()
   set(RT1020_BOARD_DIR
-    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1020")
+    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1020")
   if(CONFIG_BOOT_FLEXSPI_NOR)
     # Include flash configuration block for RT1020 EVK from NXP's HAL.
     # This configuration block may need modification if another flash chip is
diff --git a/boards/nxp/mimxrt1020_evk/Kconfig.defconfig b/boards/nxp/mimxrt1020_evk/Kconfig.defconfig
index 9c2251e2e60..e632fbf4651 100644
--- a/boards/nxp/mimxrt1020_evk/Kconfig.defconfig
+++ b/boards/nxp/mimxrt1020_evk/Kconfig.defconfig
@@ -16,9 +16,6 @@ if NETWORKING
 config NET_L2_ETHERNET
 	default y
 
-config ETH_MCUX_PHY_RESET
-	default y
-
 endif # NETWORKING
 
 endif # BOARD_MIMXRT1020_EVK
diff --git a/boards/nxp/mimxrt1020_evk/doc/index.rst b/boards/nxp/mimxrt1020_evk/doc/index.rst
index 88e62be8b9e..ab3a9fd7a2a 100644
--- a/boards/nxp/mimxrt1020_evk/doc/index.rst
+++ b/boards/nxp/mimxrt1020_evk/doc/index.rst
@@ -64,7 +64,7 @@ This platform has the following external memories:
 |                |            | data block, which sets up SEMC at   |
 |                |            | boot time                           |
 +----------------+------------+-------------------------------------+
-| IS25LP064A     | FLEXSPI    | Enabled via flash configurationn    |
+| IS25LP064A     | FLEXSPI    | Enabled via flash configuration     |
 |                |            | block, which sets up FLEXSPI at     |
 |                |            | boot time                           |
 +----------------+------------+-------------------------------------+
@@ -72,50 +72,15 @@ This platform has the following external memories:
 Supported Features
 ==================
 
-The mimxrt1020_evk board configuration supports the hardware features listed
-below.  For additional features not yet supported, please also refer to the
-:zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
-NXP prioritizes enabling the superset board with NXP's Full Platform Support for
-Zephyr.  Therefore, the mimxrt1064_evk board may have additional features
-already supported, which can also be re-used on this mimxrt1020_evk board:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | QSPI flash                          |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SDHC      | on-chip    | disk access                         |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| ENET      | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| GPT       | on-chip    | gpt                                 |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| FLEXSPI   | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/mimxrt1020_evk/mimxrt1020_evk_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   For additional features not yet supported, please also refer to the
+   :zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
+   NXP prioritizes enabling the superset board with NXP's Full Platform Support for
+   Zephyr.  Therefore, the mimxrt1064_evk board may have additional features
+   already supported, which can also be re-used on this mimxrt1020_evk board.
 
 Connections and I/Os
 ====================
@@ -212,6 +177,8 @@ remaining are not used.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 This board supports 3 debug host tools. Please install your preferred host
 tool, then follow the instructions in `Configuring a Debug Probe`_ to
 configure the board appropriately.
@@ -287,6 +254,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS v1.14.0-rc1 *****
    Hello World! mimxrt1020_evk
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _MIMXRT1020-EVK Website:
    https://www.nxp.com/support/developer-resources/run-time-software/i.mx-developer-resources/i.mx-rt1020-evaluation-kit:MIMXRT1020-EVK
 
diff --git a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.yaml b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.yaml
index 88c5629fa0c..886968e1c76 100644
--- a/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.yaml
+++ b/boards/nxp/mimxrt1020_evk/mimxrt1020_evk.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32768
 flash: 8192
 supported:
diff --git a/boards/nxp/mimxrt1024_evk/CMakeLists.txt b/boards/nxp/mimxrt1024_evk/CMakeLists.txt
index 229a396bcf6..82d756716ea 100644
--- a/boards/nxp/mimxrt1024_evk/CMakeLists.txt
+++ b/boards/nxp/mimxrt1024_evk/CMakeLists.txt
@@ -13,7 +13,7 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER)
      "update your flash configuration or device configuration data blocks")
   endif()
   set(RT1024_BOARD_DIR
-    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1024")
+    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1024")
   if(CONFIG_BOOT_FLEXSPI_NOR)
     # Include flash configuration block for RT1024 EVK from NXP's HAL.
     # This configuration block may need modification if another flash chip is
diff --git a/boards/nxp/mimxrt1024_evk/Kconfig.defconfig b/boards/nxp/mimxrt1024_evk/Kconfig.defconfig
index f9bc8cbfe60..8e84a3543aa 100644
--- a/boards/nxp/mimxrt1024_evk/Kconfig.defconfig
+++ b/boards/nxp/mimxrt1024_evk/Kconfig.defconfig
@@ -20,13 +20,6 @@ if NETWORKING
 config NET_L2_ETHERNET
 	default y
 
-if ETH_MCUX
-
-config ETH_MCUX_PHY_RESET
-	default y
-
-endif # ETH_MCUX
-
 endif # NETWORKING
 
 endif # BOARD_MIMXRT1024_EVK
diff --git a/boards/nxp/mimxrt1024_evk/doc/index.rst b/boards/nxp/mimxrt1024_evk/doc/index.rst
index 62a5a987128..2a8cc0b6819 100644
--- a/boards/nxp/mimxrt1024_evk/doc/index.rst
+++ b/boards/nxp/mimxrt1024_evk/doc/index.rst
@@ -73,54 +73,15 @@ This platform has the following external memories:
 Supported Features
 ==================
 
-The mimxrt1024_evk board configuration supports the hardware features listed
-below.  For additional features not yet supported, please also refer to the
-:zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
-NXP prioritizes enabling the superset board with NXP's Full Platform Support for
-Zephyr.  Therefore, the mimxrt1064_evk board may have additional features
-already supported, which can also be re-used on this mimxrt1024_evk board:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | QSPI flash                          |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ENET      | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| HWINFO    | on-chip    | reset cause                         |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| GPT       | on-chip    | gpt                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB                                 |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| FLEXSPI   | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/mimxrt1024_evk/mimxrt1024_evk_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   For additional features not yet supported, please also refer to the
+   :zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
+   NXP prioritizes enabling the superset board with NXP's Full Platform Support for
+   Zephyr.  Therefore, the mimxrt1064_evk board may have additional features
+   already supported, which can also be re-used on this mimxrt1024_evk board.
 
 Connections and I/Os
 ====================
@@ -199,6 +160,8 @@ remaining are not used.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 This board supports 3 debug host tools. Please install your preferred host
 tool, then follow the instructions in `Configuring a Debug Probe`_ to
 configure the board appropriately.
@@ -270,6 +233,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS v2.4.0-rc1 *****
    Hello World! mimxrt1024_evk
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _MIMXRT1024-EVK Website:
    https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1024-evaluation-kit:MIMXRT1024-EVK
 
diff --git a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.yaml b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.yaml
index 67fad31a54d..4d2bfe65864 100644
--- a/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.yaml
+++ b/boards/nxp/mimxrt1024_evk/mimxrt1024_evk.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32768
 flash: 4096
 supported:
diff --git a/boards/nxp/mimxrt1040_evk/CMakeLists.txt b/boards/nxp/mimxrt1040_evk/CMakeLists.txt
index e5e2d4d4140..53079848c6c 100644
--- a/boards/nxp/mimxrt1040_evk/CMakeLists.txt
+++ b/boards/nxp/mimxrt1040_evk/CMakeLists.txt
@@ -18,7 +18,7 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER)
      "update your flash configuration or device configuration data blocks")
   endif()
   set(RT1040_BOARD_DIR
-    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1040")
+    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1040")
   if(CONFIG_BOOT_FLEXSPI_NOR)
     # Include flash configuration block for RT1040 EVK from NXP's HAL.
     # This configuration block may need modification if another flash chip is
diff --git a/boards/nxp/mimxrt1040_evk/doc/index.rst b/boards/nxp/mimxrt1040_evk/doc/index.rst
index 8f9f4edf8da..db592aa16e8 100644
--- a/boards/nxp/mimxrt1040_evk/doc/index.rst
+++ b/boards/nxp/mimxrt1040_evk/doc/index.rst
@@ -74,7 +74,7 @@ This platform has the following external memories:
 |                |            | data block, which sets up SEMC at   |
 |                |            | boot time                           |
 +----------------+------------+-------------------------------------+
-| W25Q64JVSSIQ   | FLEXSPI    | Enabled via flash configurationn    |
+| W25Q64JVSSIQ   | FLEXSPI    | Enabled via flash configuration     |
 |                |            | block, which sets up FLEXSPI at     |
 |                |            | boot time. Supported for XIP only.  |
 +----------------+------------+-------------------------------------+
@@ -82,48 +82,15 @@ This platform has the following external memories:
 Supported Features
 ==================
 
-The mimxrt1040_evk board configuration supports the hardware features listed
-below.  For additional features not yet supported, please also refer to the
-:zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
-NXP prioritizes enabling the superset board with NXP's Full Platform Support for
-Zephyr.  Therefore, the mimxrt1064_evk board may have additional features
-already supported, which can also be re-used on this mimxrt1040_evk board:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| GPT       | on-chip    | gpt                                 |
-+-----------+------------+-------------------------------------+
-| DISPLAY   | on-chip    | eLCDIF. Tested with                 |
-|           |            | :ref:`rk043fn02h_ct`, and           |
-|           |            | :ref:`rk043fn66hs_ctg` shields      |
-+-----------+------------+-------------------------------------+
-| UART      | NXP NW61x  | M.2 WIFI/BT module                  |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/mimxrt1040_evk/mimxrt1040_evk_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   For additional features not yet supported, please also refer to the
+   :zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
+   NXP prioritizes enabling the superset board with NXP's Full Platform Support for
+   Zephyr.  Therefore, the mimxrt1064_evk board may have additional features
+   already supported, which can also be re-used on this mimxrt1040_evk board.
 
 Connections and IOs
 ===================
@@ -205,6 +172,8 @@ that run the command:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 This board supports 3 debug host tools. Please install your preferred host
 tool, then follow the instructions in `Configuring a Debug Probe`_ to
 configure the board appropriately.
@@ -351,6 +320,8 @@ the M.2 WiFi module is interfering with the debug signals
 To resolve this, you may remove the M.2 WiFi module from the board when
 flashing or debugging it, or remove jumper J80.
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
 
 .. _MIMXRT1040-EVK Website:
    https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1040-evaluation-kit:MIMXRT1040-EVK
diff --git a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.yaml b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.yaml
index 3d5aeefadcd..b4cf62676db 100644
--- a/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.yaml
+++ b/boards/nxp/mimxrt1040_evk/mimxrt1040_evk.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32768
 flash: 8192
 supported:
diff --git a/boards/nxp/mimxrt1050_evk/CMakeLists.txt b/boards/nxp/mimxrt1050_evk/CMakeLists.txt
index 597a64852cf..2782a277c9a 100644
--- a/boards/nxp/mimxrt1050_evk/CMakeLists.txt
+++ b/boards/nxp/mimxrt1050_evk/CMakeLists.txt
@@ -24,7 +24,7 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER)
     set(FLASH_CONF evkbimxrt1050_flexspi_nor_config.c)
   endif()
   set(RT1050_BOARD_DIR
-    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkbimxrt1050")
+    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkbimxrt1050")
   if(CONFIG_BOOT_FLEXSPI_NOR)
     # Include flash configuration block for RT1050 EVK from NXP's HAL.
     # This configuration block may need modification if another flash chip is
diff --git a/boards/nxp/mimxrt1050_evk/Kconfig.defconfig b/boards/nxp/mimxrt1050_evk/Kconfig.defconfig
index 90fc7a76598..1e93c2ec049 100644
--- a/boards/nxp/mimxrt1050_evk/Kconfig.defconfig
+++ b/boards/nxp/mimxrt1050_evk/Kconfig.defconfig
@@ -16,13 +16,6 @@ if NETWORKING
 config NET_L2_ETHERNET
 	default y
 
-if ETH_MCUX
-
-config ETH_MCUX_PHY_RESET
-	default y
-
-endif # ETH_MCUX
-
 endif # NETWORKING
 
 endif # BOARD_MIMXRT1050_EVK
diff --git a/boards/nxp/mimxrt1050_evk/doc/index.rst b/boards/nxp/mimxrt1050_evk/doc/index.rst
index 379498dd33b..3c2fcc2fec7 100644
--- a/boards/nxp/mimxrt1050_evk/doc/index.rst
+++ b/boards/nxp/mimxrt1050_evk/doc/index.rst
@@ -87,7 +87,7 @@ This platform has the following external memories:
 |                    |            | data block, which sets up SEMC at   |
 |                    |            | boot time                           |
 +--------------------+------------+-------------------------------------+
-| S26KS512SDPBHI020  | FLEXSPI    | Enabled via flash configurationn    |
+| S26KS512SDPBHI020  | FLEXSPI    | Enabled via flash configuration     |
 |                    |            | block, which sets up FLEXSPI at     |
 |                    |            | boot time.                          |
 +--------------------+------------+-------------------------------------+
@@ -95,52 +95,15 @@ This platform has the following external memories:
 Supported Features
 ==================
 
-The mimxrt1050_evk board configuration supports the hardware features listed
-below.  For additional features not yet supported, please also refer to the
-:zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
-NXP prioritizes enabling the superset board with NXP's Full Platform Support for
-Zephyr.  Therefore, the mimxrt1064_evk board may have additional features
-already supported, which can also be re-used on this mimxrt1050_evk board:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| DISPLAY   | on-chip    | eLCDIF. Tested with                 |
-|           |            | :ref:`rk043fn02h_ct`, and           |
-|           |            | :ref:`rk043fn66hs_ctg` shields      |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SDHC      | on-chip    | disk access                         |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| ENET      | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| GPT       | on-chip    | gpt                                 |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| FLEXSPI   | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/mimxrt1050_evk/mimxrt1050_evk_hyperflash_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   For additional features not yet supported, please also refer to the
+   :zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
+   NXP prioritizes enabling the superset board with NXP's Full Platform Support for
+   Zephyr.  Therefore, the mimxrt1064_evk board may have additional features
+   already supported, which can also be re-used on this mimxrt1050_evk board.
 
 Connections and IOs
 ===================
@@ -312,6 +275,8 @@ depending on which flash to set as ``zephyr,flash``:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 .. note::
    Newer revisions of this board use :ref:`lpc-link2-onboard-debug-probe`,
    while older revisions use the :ref:`opensda-onboard-debug-probe`.
@@ -449,6 +414,9 @@ For more details, please see the following `NXP i.MXRT1050 A0 to A1 Migration Gu
 
 Current Zephyr build supports the new MIMXRT1050-EVKB
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _MIMXRT1050-EVK Website:
    https://www.nxp.com/products/microcontrollers-and-processors/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1050-evaluation-kit:MIMXRT1050-EVK
 
diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi
index 3879b04cb50..4fdca2496d3 100644
--- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi
+++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk.dtsi
@@ -166,6 +166,7 @@ zephyr_lcdif: &lcdif {
 	dma-names = "rx", "tx";
 	pinctrl-0 = <&pinmux_lpspi1>;
 	pinctrl-names = "default";
+	tristate-output;
 };
 
 &lpspi3 {
diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.yaml b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.yaml
index c44f53326df..4a097f4e441 100644
--- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.yaml
+++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_hyperflash.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32768
 flash: 65536
 supported:
diff --git a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml
index 68c150c9366..62b065a0658 100644
--- a/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml
+++ b/boards/nxp/mimxrt1050_evk/mimxrt1050_evk_mimxrt1052_qspi.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32768
 flash: 8192
 supported:
diff --git a/boards/nxp/mimxrt1060_evk/CMakeLists.txt b/boards/nxp/mimxrt1060_evk/CMakeLists.txt
index 2778972698b..1bce9631ef4 100644
--- a/boards/nxp/mimxrt1060_evk/CMakeLists.txt
+++ b/boards/nxp/mimxrt1060_evk/CMakeLists.txt
@@ -1,5 +1,5 @@
 #
-# Copyright 2018-2022 NXP
+# Copyright 2018-2022, 2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -12,7 +12,7 @@ endif()
 
 if(CONFIG_NXP_IMXRT_BOOT_HEADER)
   zephyr_library()
-  if(${BOARD_REVISION} STREQUAL "B")
+  if((${BOARD_REVISION} STREQUAL "B") OR (${BOARD_REVISION} STREQUAL "C"))
     set(FLASH_CONF evkbmimxrt1060_flexspi_nor_config.c)
     set(BOARD_NAME evkbmimxrt1060)
   elseif(CONFIG_DT_HAS_NXP_IMX_FLEXSPI_NOR_ENABLED)
@@ -33,7 +33,7 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER)
     set(BOARD_NAME evkbmimxrt1060)
   endif()
   set(RT1060_BOARD_DIR
-    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/${BOARD_NAME}")
+    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/${BOARD_NAME}")
   if(CONFIG_BOOT_FLEXSPI_NOR)
     # Include flash configuration block for RT1060 EVK from NXP's HAL.
     # This configuration block may need modification if another flash chip is
diff --git a/boards/nxp/mimxrt1060_evk/Kconfig.defconfig b/boards/nxp/mimxrt1060_evk/Kconfig.defconfig
index bc06c96f7b8..6caa52d0af2 100644
--- a/boards/nxp/mimxrt1060_evk/Kconfig.defconfig
+++ b/boards/nxp/mimxrt1060_evk/Kconfig.defconfig
@@ -16,13 +16,6 @@ if NETWORKING
 config NET_L2_ETHERNET
 	default y
 
-if ETH_MCUX
-
-config ETH_MCUX_PHY_RESET
-	default y
-
-endif # ETH_MCUX
-
 endif # NETWORKING
 
 endif # BOARD_MIMXRT1060_EVK
diff --git a/boards/nxp/mimxrt1060_evk/board.cmake b/boards/nxp/mimxrt1060_evk/board.cmake
index e6748688a78..9fe7e3718ea 100644
--- a/boards/nxp/mimxrt1060_evk/board.cmake
+++ b/boards/nxp/mimxrt1060_evk/board.cmake
@@ -12,9 +12,16 @@ endif()
 
 board_runner_args(pyocd "--target=mimxrt1060")
 board_runner_args(jlink "--device=MIMXRT1062xxx6A")
+
+if ("${BOARD_REVISION}" STREQUAL "B")
+board_runner_args(linkserver  "--device=MIMXRT1062xxxxB:MIMXRT1060-EVKB")
+elseif ("${BOARD_REVISION}" STREQUAL "C")
+board_runner_args(linkserver  "--device=MIMXRT1062xxxxB:MIMXRT1060-EVKC")
+else()
 board_runner_args(linkserver  "--device=MIMXRT1062xxxxA:EVK-MIMXRT1060")
+endif()
 
-if(("${BOARD_QUALIFIERS}" MATCHES "qspi") OR ("${BOARD_REVISION}" STREQUAL "B"))
+if(("${BOARD_QUALIFIERS}" MATCHES "qspi") OR ("${BOARD_REVISION}" STREQUAL "B") OR ("${BOARD_REVISION}" STREQUAL "C"))
   board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=QSPI")
 elseif ("${BOARD_QUALIFIERS}" MATCHES "hyperflash")
   board_runner_args(jlink "--loader=BankAddr=0x60000000&Loader=HyperFlash")
diff --git a/boards/nxp/mimxrt1060_evk/board.yml b/boards/nxp/mimxrt1060_evk/board.yml
index 30a5701b1fe..6ea1376ab86 100644
--- a/boards/nxp/mimxrt1060_evk/board.yml
+++ b/boards/nxp/mimxrt1060_evk/board.yml
@@ -9,7 +9,8 @@ boards:
           - name: "hyperflash"
     revision:
       format: "letter"
-      default: "A"
+      default: "C"
       revisions:
         - name: "A"
         - name: "B"
+        - name: "C"
diff --git a/boards/nxp/mimxrt1060_evk/doc/index.rst b/boards/nxp/mimxrt1060_evk/doc/index.rst
index 940ca2a593e..3f2265cb6a9 100644
--- a/boards/nxp/mimxrt1060_evk/doc/index.rst
+++ b/boards/nxp/mimxrt1060_evk/doc/index.rst
@@ -87,7 +87,7 @@ This platform has the following external memories:
 |                    |            | data block, which sets up SEMC at   |
 |                    |            | boot time                           |
 +--------------------+------------+-------------------------------------+
-| IS42S16160J        | FLEXSPI    | Enabled via flash configurationn    |
+| IS42S16160J        | FLEXSPI    | Enabled via flash configuration     |
 |                    |            | block, which sets up FLEXSPI at     |
 |                    |            | boot time.                          |
 +--------------------+------------+-------------------------------------+
@@ -95,64 +95,15 @@ This platform has the following external memories:
 Supported Features
 ==================
 
-The mimxrt1060_evk board configuration supports the hardware features listed
-below.  For additional features not yet supported, please also refer to the
-:zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
-NXP prioritizes enabling the superset board with NXP's Full Platform Support for
-Zephyr.  Therefore, the mimxrt1064_evk board may have additional features
-already supported, which can also be re-used on this mimxrt1060_evk board:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| DISPLAY   | on-chip    | eLCDIF. Tested with                 |
-|           |            | :ref:`rk043fn02h_ct`, and           |
-|           |            | :ref:`rk043fn66hs_ctg` shields      |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | QSPI flash                          |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| SDHC      | on-chip    | disk access                         |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| ENET      | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| SAI       | on-chip    | i2s                                 |
-+-----------+------------+-------------------------------------+
-| GPT       | on-chip    | gpt                                 |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| FLEXSPI   | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-| PIT       | on-chip    | pit                                 |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   For additional features not yet supported, please also refer to the
+   :zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
+   NXP prioritizes enabling the superset board with NXP's Full Platform Support for
+   Zephyr.  Therefore, the mimxrt1064_evk board may have additional features
+   already supported, which can also be re-used on this mimxrt1060_evk board.
 
 Connections and I/Os
 ====================
@@ -316,8 +267,28 @@ The MIMXRT1060 SoC has eight UARTs. ``LPUART1`` is configured for the console,
 ``LPUART3`` for the Bluetooth Host Controller Interface (BT HCI), and the
 remaining are not used.
 
-Board Targets
-*************
+Board Revisions and Targets
+***************************
+
+There are three revisions of this board.
+
+Rev A:
+
+* Initial version
+
+Rev B:
+
+* adds the M.2 connector for Wi-Fi/BLE
+* adds audio expansion connector J23
+* USER LED1 changed to GPIO1 pin 8
+
+Rev C:
+
+* Replaces audio codec WM8960(EOL) to WM8962
+* Replaces 32.768 KHz oscillator from ASH7K-32.768KHz-T(EOL)to ASH7KW-32.768KHZ-L-T
+* Replaces motion sensor from FXOS8700CQ(EOL) to FXLS8974CFR3
+* Re-assigns Bluetooth Audio PCM with dedicated I2S2
+* Re-assigns Bluetooth interface UART_CTS, UART_RTS to hardware PIN
 
 This board has two variants that can be targeted,
 depending on which flash to set as ``zephyr,flash``:
@@ -332,6 +303,8 @@ depending on which flash to set as ``zephyr,flash``:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 This board supports 3 debug host tools. Please install your preferred host
 tool, then follow the instructions in `Configuring a Debug Probe`_ to
 configure the board appropriately.
@@ -387,10 +360,28 @@ Flashing
 
 Here is an example for the :zephyr:code-sample:`hello_world` application.
 
-.. zephyr-app-commands::
-   :zephyr-app: samples/hello_world
-   :board: mimxrt1060_evk//qspi
-   :goals: flash
+.. tabs::
+
+   .. group-tab:: i.MX RT1060 Rev A
+
+      .. zephyr-app-commands::
+         :zephyr-app: samples/hello_world
+         :board: mimxrt1060_evk@A//qspi
+         :goals: flash
+
+   .. group-tab:: i.MX RT1060 Rev B
+
+      .. zephyr-app-commands::
+         :zephyr-app: samples/hello_world
+         :board: mimxrt1060_evk@B//qspi
+         :goals: flash
+
+   .. group-tab:: i.MX RT1060 Rev C (default)
+
+      .. zephyr-app-commands::
+         :zephyr-app: samples/hello_world
+         :board: mimxrt1060_evk@C//qspi
+         :goals: flash
 
 Open a serial terminal, reset the board (press the SW9 button), and you should
 see the following message in the terminal:
@@ -405,10 +396,29 @@ Debugging
 
 Here is an example for the :zephyr:code-sample:`hello_world` application.
 
-.. zephyr-app-commands::
-   :zephyr-app: samples/hello_world
-   :board: mimxrt1060_evk//qspi
-   :goals: debug
+.. tabs::
+
+   .. group-tab:: i.MX RT1060 Rev A
+
+      .. zephyr-app-commands::
+         :zephyr-app: samples/hello_world
+         :board: mimxrt1060_evk@A//qspi
+         :goals: debug
+
+   .. group-tab:: i.MX RT1060 Rev B
+
+      .. zephyr-app-commands::
+         :zephyr-app: samples/hello_world
+         :board: mimxrt1060_evk@B//qspi
+         :goals: debug
+
+   .. group-tab:: i.MX RT1060 Rev C (default)
+
+      .. zephyr-app-commands::
+         :zephyr-app: samples/hello_world
+         :board: mimxrt1060_evk@C//qspi
+         :goals: debug
+
 
 Open a serial terminal, step through the application in your debugger, and you
 should see the following message in the terminal:
@@ -453,6 +463,9 @@ If the west flash or debug commands fail, and the command hangs while executing
 runners.jlink, confirm the J-Link debug probe is configured, powered, and
 connected to the EVK properly.
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _MIMXRT1060-EVK Website:
    https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1060-evaluation-kit:MIMXRT1060-EVKB
 
diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi
index 84dbaac3ae4..2a26160c2a2 100644
--- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi
+++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dtsi
@@ -185,7 +185,7 @@ arduino_i2c: &lpi2c1 {
 
 zephyr_udc0: &usb1 {
 	status = "okay";
-	phy_handle = <&usbphy1>;
+	phy-handle = <&usbphy1>;
 };
 
 &usbphy1 {
@@ -268,7 +268,6 @@ arduino_spi: &lpspi1 {
 	dma-names = "rx", "tx";
 	pinctrl-0 = <&pinmux_lpspi3>;
 	pinctrl-names = "default";
-
 };
 
 &sai1 {
diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml
index 1d81a48175a..688e5c8f576 100644
--- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml
+++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_hyperflash.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32768
 flash: 65536
 supported:
diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.yaml b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.yaml
index cd57a0bc6c2..56f608d3a67 100644
--- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.yaml
+++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi.yaml
@@ -4,14 +4,13 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-identifier: mimxrt1060_evk/mimxrt1062/qspi
+identifier: mimxrt1060_evk@A/mimxrt1062/qspi
 name: NXP MIMXRT1060-EVK
 type: mcu
 arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32768
 flash: 8192
 supported:
diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_B.yaml b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_B.yaml
index 5c9f42d5ef7..c32eb2fdcf1 100644
--- a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_B.yaml
+++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_B.yaml
@@ -11,24 +11,23 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32768
 flash: 8192
 supported:
+  - adc
   - arduino_gpio
   - arduino_i2c
   - arduino_serial
   - arduino_spi
+  - can
   - counter
   - display
+  - dma
   - gpio
   - i2c
   - netif:eth
   - sdhc
   - spi
-  - usb_device
-  - dma
-  - can
+  - usbd
   - watchdog
-  - adc
 vendor: nxp
diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
new file mode 100644
index 00000000000..284679eaa9f
--- /dev/null
+++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2022, Whisper.ai
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* FLEXPWM not routed to LED on this EVK */
+&flexpwm2_pwm3 {
+	status = "disabled";
+};
+
+&green_led {
+	gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
+	label = "User LED1";
+};
diff --git a/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_C.yaml b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_C.yaml
new file mode 100644
index 00000000000..2a1c3311647
--- /dev/null
+++ b/boards/nxp/mimxrt1060_evk/mimxrt1060_evk_mimxrt1062_qspi_C.yaml
@@ -0,0 +1,33 @@
+#
+# Copyright (c) 2022, Whisper.ai
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mimxrt1060_evk@C/mimxrt1062/qspi
+name: NXP MIMXRT1060-EVKC
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 32768
+flash: 8192
+supported:
+  - adc
+  - arduino_gpio
+  - arduino_i2c
+  - arduino_serial
+  - arduino_spi
+  - can
+  - counter
+  - display
+  - dma
+  - gpio
+  - i2c
+  - netif:eth
+  - sdhc
+  - spi
+  - usbd
+  - watchdog
+vendor: nxp
diff --git a/boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt b/boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt
index 70f8df6e741..40e22e4176b 100644
--- a/boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt
+++ b/boards/nxp/mimxrt1062_fmurt6/CMakeLists.txt
@@ -14,7 +14,7 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER)
     set(BOARD_NAME evkbimxrt1050)
   endif()
   set(RT1062_BOARD_DIR
-    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/${BOARD_NAME}")
+    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/${BOARD_NAME}")
   if(CONFIG_BOOT_FLEXSPI_NOR)
     # Include flash configuration block for RT1050 EVK from NXP's HAL.
     # This configuration block may need modification if another flash chip is
diff --git a/boards/nxp/mimxrt1062_fmurt6/doc/index.rst b/boards/nxp/mimxrt1062_fmurt6/doc/index.rst
index 25dd714bf73..c93a2738fa6 100644
--- a/boards/nxp/mimxrt1062_fmurt6/doc/index.rst
+++ b/boards/nxp/mimxrt1062_fmurt6/doc/index.rst
@@ -68,56 +68,15 @@ these references:
 Supported Features
 ==================
 
-The mimxrt1062_fmurt6 board configuration supports the hardware features listed
-below.  For additional features not yet supported, please also refer to the
-:zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
-NXP prioritizes enabling the superset board with NXP's Full Platform Support for
-Zephyr.  Therefore, the mimxrt1064_evk board may have additional features
-already supported, which can also be re-used on this mimxrt1060_evk board:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| DISPLAY   | on-chip    | display                             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | QSPI hyper flash                    |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| ENET      | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma                                 |
-+-----------+------------+-------------------------------------+
-| GPT       | on-chip    | gpt                                 |
-+-----------+------------+-------------------------------------+
-| FLEXSPI   | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   For additional features not yet supported, please also refer to the
+   :zephyr:board:`mimxrt1064_evk` , which is the superset board in NXP's i.MX RT10xx family.
+   NXP prioritizes enabling the superset board with NXP's Full Platform Support for
+   Zephyr.  Therefore, the mimxrt1064_evk board may have additional features
+   already supported, which can also be re-used on this mimxrt1060_evk board.
 
 Connections and I/Os
 ====================
@@ -244,6 +203,8 @@ The MIMXRT1062 SoC has eight UARTs. ``LPUART7`` is configured for the console,
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -336,6 +297,9 @@ If the west flash or debug commands fail, and the command hangs while executing
 runners.jlink, confirm the J-Link debug probe is configured, powered, and
 connected to the FMURT6 properly.
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _MIMXRT1062-FMURT6 Website:
    https://www.nxp.com/part/RDDRONE-FMURT6#
 
diff --git a/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.yaml b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.yaml
index 9e4a523d944..d0a6c75480a 100644
--- a/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.yaml
+++ b/boards/nxp/mimxrt1062_fmurt6/mimxrt1062_fmurt6.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 768
 flash: 65536
 supported:
diff --git a/boards/nxp/mimxrt1064_evk/CMakeLists.txt b/boards/nxp/mimxrt1064_evk/CMakeLists.txt
index 7d2f7effa10..0d057397083 100644
--- a/boards/nxp/mimxrt1064_evk/CMakeLists.txt
+++ b/boards/nxp/mimxrt1064_evk/CMakeLists.txt
@@ -18,7 +18,7 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER)
      "update your flash configuration or device configuration data blocks")
   endif()
   set(RT1064_BOARD_DIR
-    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1064")
+    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1064")
   if(CONFIG_BOOT_FLEXSPI_NOR)
     # Include flash configuration block for RT1064 EVK from NXP's HAL.
     # This configuration block may need modification if another flash chip is
diff --git a/boards/nxp/mimxrt1064_evk/Kconfig.defconfig b/boards/nxp/mimxrt1064_evk/Kconfig.defconfig
index 6454f9b6329..d212ccfdfdd 100644
--- a/boards/nxp/mimxrt1064_evk/Kconfig.defconfig
+++ b/boards/nxp/mimxrt1064_evk/Kconfig.defconfig
@@ -16,13 +16,6 @@ if NETWORKING
 config NET_L2_ETHERNET
 	default y
 
-if ETH_MCUX
-
-config ETH_MCUX_PHY_RESET
-	default y
-
-endif # ETH_MCUX
-
 endif # NETWORKING
 
 endif # BOARD_MIMXRT1064_EVK
diff --git a/boards/nxp/mimxrt1064_evk/doc/index.rst b/boards/nxp/mimxrt1064_evk/doc/index.rst
index 865b1c2764f..6ef06dfd77d 100644
--- a/boards/nxp/mimxrt1064_evk/doc/index.rst
+++ b/boards/nxp/mimxrt1064_evk/doc/index.rst
@@ -94,62 +94,9 @@ Supported Features
 NXP considers the MIMXRT1064-EVK as the superset board for the i.MX RT10xx
 family of MCUs.  This board is a focus for NXP's Full Platform Support for
 Zephyr, to better enable the entire RT10xx family.  NXP prioritizes enabling
-this board with new support for Zephyr features.  The mimxrt1064_evk board
-configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| DISPLAY   | on-chip    | eLCDIF. Tested with                 |
-|           |            | :ref:`rk043fn02h_ct`, and           |
-|           |            | :ref:`rk043fn66hs_ctg` shields      |
-+-----------+------------+-------------------------------------+
-| VIDEO     | on-chip    | video, using CSI                    |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | QSPI flash                          |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| SDHC      | on-chip    | disk access                         |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| ENET      | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| GPT       | on-chip    | gpt                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma                                 |
-+-----------+------------+-------------------------------------+
-| HWINFO    | on-chip    | Unique device serial number         |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| FLEXSPI   | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/mimxrt1064_evk/mimxrt1064_evk_defconfig`
-
-Other hardware features are not currently supported by the port.
+this board with new support for Zephyr features.
+
+.. zephyr:board-supported-hw::
 
 Connections and I/Os
 ====================
@@ -310,6 +257,8 @@ and the remaining are not used.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 This board supports 3 debug host tools. Please install your preferred host
 tool, then follow the instructions in `Configuring a Debug Probe`_ to
 configure the board appropriately.
@@ -437,6 +386,9 @@ If the west flash or debug commands fail, and the command hangs while executing
 runners.jlink, confirm the J-Link debug probe is configured, powered, and
 connected to the EVK properly.
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _MIMXRT1064-EVK Website:
    https://www.nxp.com/support/developer-resources/run-time-software/i.mx-developer-resources/mimxrt1064-evk-i.mx-rt1064-evaluation-kit:MIMXRT1064-EVK
 
diff --git a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts
index 8d9f2437d6a..004c280362c 100644
--- a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts
+++ b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.dts
@@ -304,6 +304,7 @@ zephyr_udc0: &usb1 {
 	/* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */
 	dmas = <&edma0 0 13>, <&edma0 1 14>;
 	dma-names = "rx", "tx";
+	tristate-output;
 	pinctrl-0 = <&pinmux_lpspi1>;
 	pinctrl-names = "default";
 };
diff --git a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.yaml b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.yaml
index eab16e277e5..deec4f1d66d 100644
--- a/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.yaml
+++ b/boards/nxp/mimxrt1064_evk/mimxrt1064_evk.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32768
 flash: 4096
 supported:
diff --git a/boards/nxp/mimxrt1160_evk/CMakeLists.txt b/boards/nxp/mimxrt1160_evk/CMakeLists.txt
index 928a9693df7..97fb4c3e12c 100644
--- a/boards/nxp/mimxrt1160_evk/CMakeLists.txt
+++ b/boards/nxp/mimxrt1160_evk/CMakeLists.txt
@@ -13,7 +13,7 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER)
      "update your flash configuration or device configuration data blocks")
   endif()
   set(RT1160_BOARD_DIR
-    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1160")
+    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1160")
   if(CONFIG_BOOT_FLEXSPI_NOR)
     # Include flash configuration block for RT1160 EVK from NXP's HAL.
     # This configuration block may need modification if another flash chip is
diff --git a/boards/nxp/mimxrt1160_evk/Kconfig.defconfig b/boards/nxp/mimxrt1160_evk/Kconfig.defconfig
index d4743f1db06..392674479f8 100644
--- a/boards/nxp/mimxrt1160_evk/Kconfig.defconfig
+++ b/boards/nxp/mimxrt1160_evk/Kconfig.defconfig
@@ -36,9 +36,6 @@ if NETWORKING
 config NET_L2_ETHERNET
 	default y if CPU_CORTEX_M7 # No cache memory support is required for driver
 
-config ETH_MCUX_PHY_RESET
-	default y
-
 endif # NETWORKING
 
 endif # BOARD_MIMXRT1160_EVK
diff --git a/boards/nxp/mimxrt1160_evk/doc/index.rst b/boards/nxp/mimxrt1160_evk/doc/index.rst
index b0d513ec8bd..1d97c49f0a4 100644
--- a/boards/nxp/mimxrt1160_evk/doc/index.rst
+++ b/boards/nxp/mimxrt1160_evk/doc/index.rst
@@ -83,7 +83,7 @@ This platform has the following external memories:
 |                    |            | data block, which sets up SEMC at   |
 |                    |            | boot time                           |
 +--------------------+------------+-------------------------------------+
-| IS25WP128          | FLEXSPI    | Enabled via flash configurationn    |
+| IS25WP128          | FLEXSPI    | Enabled via flash configuration     |
 |                    |            | block, which sets up FLEXSPI at     |
 |                    |            | boot time.                          |
 +--------------------+------------+-------------------------------------+
@@ -91,64 +91,15 @@ This platform has the following external memories:
 Supported Features
 ==================
 
-The mimxrt1160_evk board configuration supports the hardware features listed
-below.  For additional features not yet supported, please also refer to the
-:zephyr:board:`mimxrt1170_evk` , which is the superset board in NXP's i.MX RT11xx family.
-NXP prioritizes enabling the superset board with NXP's Full Platform Support for
-Zephyr.  Therefore, the mimxrt1170_evk board may have additional features
-already supported, which can also be re-used on this mimxrt1160_evk board:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | flexcan                             |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma                                 |
-+-----------+------------+-------------------------------------+
-| GPT       | on-chip    | gpt                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB Device                          |
-+-----------+------------+-------------------------------------+
-| HWINFO    | on-chip    | Unique device serial number         |
-+-----------+------------+-------------------------------------+
-| CAAM RNG  | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| FLEXSPI   | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-| PIT       | on-chip    | pit                                 |
-+-----------+------------+-------------------------------------+
-| DISPLAY   | on-chip    | eLCDIF; MIPI-DSI. Tested with       |
-|           |            | :ref:`rk055hdmipi4m`,               |
-|           |            | :ref:`rk055hdmipi4ma0`,             |
-|           |            | and :ref:`g1120b0mipi` shields      |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
+.. note::
+
+   For additional features not yet supported, please also refer to the
+   :zephyr:board:`mimxrt1170_evk` , which is the superset board in NXP's i.MX RT11xx family.
+   NXP prioritizes enabling the superset board with NXP's Full Platform Support for
+   Zephyr.  Therefore, the mimxrt1170_evk board may have additional features
+   already supported, which can also be re-used on this mimxrt1160_evk board:
 
 Connections and I/Os
 ====================
@@ -239,6 +190,8 @@ remaining are not used.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -362,6 +315,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS v2.4.0-xxxx-xxxxxxxxxxxxx *****
    Hello World! mimxrt1160_evk
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _MIMXRT1160-EVK Website:
    https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1160-evaluation-kit:MIMXRT1160-EVK
 
diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml
index b265336cb24..445f170f573 100644
--- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml
+++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm4.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 128
 supported:
diff --git a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml
index b9780a95746..d803d9332e3 100644
--- a/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml
+++ b/boards/nxp/mimxrt1160_evk/mimxrt1160_evk_mimxrt1166_cm7.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 256
 flash: 16384
 supported:
diff --git a/boards/nxp/mimxrt1170_evk/CMakeLists.txt b/boards/nxp/mimxrt1170_evk/CMakeLists.txt
index e87e07401d0..5b845eb090e 100644
--- a/boards/nxp/mimxrt1170_evk/CMakeLists.txt
+++ b/boards/nxp/mimxrt1170_evk/CMakeLists.txt
@@ -18,7 +18,7 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER)
     set(RT1170_BOARD_NAME "evkbmimxrt1170")
   endif()
   set(RT1170_BOARD_DIR
-    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/${RT1170_BOARD_NAME}")
+    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/${RT1170_BOARD_NAME}")
   if(CONFIG_BOOT_FLEXSPI_NOR)
     # Include flash configuration block for RT1170 EVK from NXP's HAL.
     # This configuration block may need modification if another flash chip is
diff --git a/boards/nxp/mimxrt1170_evk/Kconfig.defconfig b/boards/nxp/mimxrt1170_evk/Kconfig.defconfig
index 3dcd48449bd..b28654c3296 100644
--- a/boards/nxp/mimxrt1170_evk/Kconfig.defconfig
+++ b/boards/nxp/mimxrt1170_evk/Kconfig.defconfig
@@ -39,9 +39,6 @@ if NETWORKING
 config NET_L2_ETHERNET
 	default y if CPU_CORTEX_M7 # No cache memory support is required for driver
 
-config ETH_MCUX_PHY_RESET
-	default y
-
 endif # NETWORKING
 
 endif
diff --git a/boards/nxp/mimxrt1170_evk/board.yml b/boards/nxp/mimxrt1170_evk/board.yml
index 4a6a25318b0..fce50aef20b 100644
--- a/boards/nxp/mimxrt1170_evk/board.yml
+++ b/boards/nxp/mimxrt1170_evk/board.yml
@@ -6,7 +6,7 @@ board:
     - name: mimxrt1176
   revision:
     format: "letter"
-    default: "A"
+    default: "B"
     revisions:
       - name: "A"
       - name: "B"
diff --git a/boards/nxp/mimxrt1170_evk/doc/index.rst b/boards/nxp/mimxrt1170_evk/doc/index.rst
index 0f69b3d1416..6b36d454e58 100644
--- a/boards/nxp/mimxrt1170_evk/doc/index.rst
+++ b/boards/nxp/mimxrt1170_evk/doc/index.rst
@@ -73,6 +73,7 @@ these references:
 - `i.MX RT1170 Datasheet`_
 - `i.MX RT1170 Reference Manual`_
 - `MIMXRT1170-EVK Website`_
+- `MIMXRT1170-EVKB Board Hardware User's Guide`_
 - `MIMXRT1170-EVK Board Hardware User's Guide`_
 
 External Memory
@@ -102,76 +103,9 @@ Supported Features
 
 NXP considers the MIMXRT1170-EVK as the superset board for the i.MX RT11xx
 family of MCUs.  This board is a focus for NXP's Full Platform Support for
-Zephyr, to better enable the entire RT11xx family.  NXP prioritizes enabling
-this board with new support for Zephyr features. Note that this table
-covers two boards: the RT1170 EVK (``mimxrt1170_evk//cm7/cm4``), and
-RT1170 EVKB (``mimxrt1170_evk@B//cm7/cm4``)
-
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| Interface | Controller | Driver/Component                    | RT1170 EVK      | RT1170 EVKB     |
-+===========+============+=====================================+=================+=================+
-| NVIC      | on-chip    | nested vector interrupt controller  | Supported       | Supported       |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| SYSTICK   | on-chip    | systick                             | Supported       | Supported       |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| GPIO      | on-chip    | gpio                                | Supported       | Supported       |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| COUNTER   | on-chip    | gpt                                 | Supported       | Supported       |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| TIMER     | on-chip    | gpt                                 | Supported       | Supported       |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| CAN       | on-chip    | flexcan                             | Supported (M7)  | Supported (M7)  |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| SPI       | on-chip    | spi                                 | Supported (M7)  | Supported       |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| I2C       | on-chip    | i2c                                 | Supported       | Supported       |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| PWM       | on-chip    | pwm                                 | Supported       | Supported       |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| ADC       | on-chip    | adc                                 | Supported (M7)  | Supported (M7)  |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| UART      | on-chip    | serial port-polling;                | Supported       | Supported       |
-|           |            | serial port-interrupt;              |                 |                 |
-|           |            | serial port-async                   |                 |                 |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| DMA       | on-chip    | dma                                 | Supported       | Supported       |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| WATCHDOG  | on-chip    | watchdog                            | Supported (M7)  | Supported (M7)  |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| ENET      | on-chip    | ethernet - 10/100M                  | Supported (M7)  | No support      |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| ENET1G    | on-chip    | ethernet - 10/100/1000M             | Supported (M7)  | No support      |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| SAI       | on-chip    | i2s                                 | Supported       | No support      |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| USB       | on-chip    | USB Device                          | Supported (M7)  | Supported (M7)  |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| HWINFO    | on-chip    | Unique device serial number         | Supported (M7)  | Supported (M7)  |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| DISPLAY   | on-chip    | eLCDIF; MIPI-DSI. Tested with       | Supported (M7)  | Supported (M7)  |
-|           |            | :ref:`rk055hdmipi4m`,               |                 |                 |
-|           |            | :ref:`rk055hdmipi4ma0`,             |                 |                 |
-|           |            | and :ref:`g1120b0mipi` shields      |                 |                 |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| ACMP      | on-chip    | sensor                              | Supported       | No support      |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| CAAM RNG  | on-chip    | entropy                             | Supported (M7)  | No support      |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| FLEXSPI   | on-chip    | flash programming                   | Supported (M7)  | Supported (M7)  |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| SDHC      | on-chip    | SD host controller                  | Supported (M7)  | Supported (M7)  |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| PIT       | on-chip    | pit                                 | Supported (M7)  | Supported (M7)  |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| VIDEO     | on-chip    | CSI; MIPI CSI-2 Rx. Tested with     | Supported (M7)  | Supported (M7)  |
-|           |            | :ref:`nxp_btb44_ov5640` shield      |                 |                 |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-| UART      | NXP NW61x  | M.2 WIFI/BT module                  | Unsupported     | Supported (M7)  |
-+-----------+------------+-------------------------------------+-----------------+-----------------+
-
-The default configuration can be found in the defconfig files:
-:zephyr_file:`boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_defconfig`
-:zephyr_file:`boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_defconfig`
+Zephyr, to better enable the entire RT11xx family.
+
+.. zephyr:board-supported-hw::
 
 Connections and I/Os
 ====================
@@ -314,6 +248,8 @@ that run the command:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -360,29 +296,28 @@ reprogrammed with JLink firmware.
 - MIMXRT1170-EVKB: :ref:`mcu-link-cmsis-onboard-debug-probe`
 - MIMXRT1170-EVK:  :ref:`opensda-daplink-onboard-debug-probe`
 
+Using LinkServer
+----------------
+
+Install the :ref:`linkserver-debug-host-tools` and make sure they are in your
+search path.  LinkServer works with the default CMSIS-DAP firmware included in
+the on-board debugger.
+
 Using J-Link
 ------------
 
-JLink is the default runner for this board.  Install the
-:ref:`jlink-debug-host-tools` and make sure they are in your search path.
+Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path.
 
 There are two options: the onboard debug circuit can be updated with Segger
 J-Link firmware, or :ref:`jlink-external-debug-probe` can be attached to the
 EVK. See `Using J-Link with MIMXRT1170-EVKB`_ or
 `Using J-Link with MIMXRT1160-EVK or MIMXRT1170-EVK`_ for more details.
 
-Using LinkServer
-----------------
-
-Install the :ref:`linkserver-debug-host-tools` and make sure they are in your
-search path.  LinkServer works with the default CMSIS-DAP firmware included in
-the on-board debugger.
-
-Use the ``-r linkserver`` option with West to use the LinkServer runner.
+Use the ``-r jlink`` option with West to use the jlink runner.
 
 .. code-block:: console
 
-   west flash -r linkserver
+   west flash -r jlink
 
 Alternatively, pyOCD can be used to flash and debug the board by using the
 ``-r pyocd`` option with West. pyOCD is installed when you complete the
@@ -453,12 +388,25 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS v3.4.0-xxxx-xxxxxxxxxxxxx *****
    Hello World! mimxrt1170_evk
 
+ENET1G Driver
+=============
+
+Current default of ethernet driver is to use 100M Ethernet instance ENET.
+To use the 1G Ethernet instance ENET1G, include the overlay to west build with
+the option ``-DEXTRA_DTC_OVERLAY_FILE=nxp,enet1g.overlay`` instead.
+
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _MIMXRT1170-EVK Website:
    https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt1170-evaluation-kit:MIMXRT1170-EVK
 
 .. _MIMXRT1170-EVK Board Hardware User's Guide:
    https://www.nxp.com/webapp/Download?colCode=MIMXRT1170EVKHUG
 
+.. _MIMXRT1170-EVKB Board Hardware User's Guide:
+   https://www.nxp.com/webapp/Download?colCode=MIMXRT1170EVKBHUG
+
 .. _i.MX RT1170 Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt1170-crossover-mcu-family-first-ghz-mcu-with-arm-cortex-m7-and-cortex-m4-cores:i.MX-RT1170
 
@@ -479,10 +427,3 @@ should see the following message in the terminal:
 
 .. _NXP MCUXpresso for Visual Studio Code:
 	https://www.nxp.com/design/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-for-visual-studio-code:MCUXPRESSO-VSC
-
-ENET1G Driver
-=============
-
-Current default of ethernet driver is to use 100M Ethernet instance ENET.
-To use the 1G Ethernet instance ENET1G, include the overlay to west build with
-the option ``-DEXTRA_DTC_OVERLAY_FILE=nxp,enet1g.overlay`` instead.
diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml
index 08bbfa3e6b9..dd213e258bf 100644
--- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml
+++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4.yaml
@@ -4,14 +4,13 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-identifier: mimxrt1170_evk/mimxrt1176/cm4
+identifier: mimxrt1170_evk@A/mimxrt1176/cm4
 name: NXP MIMXRT1170-EVK CM4
 type: mcu
 arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 128
 supported:
diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml
index 061366570f2..e967a26465d 100644
--- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml
+++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm4_B.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 128
 supported:
diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts
index 7e2a6c182fb..6d4a76fe260 100644
--- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts
+++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.dts
@@ -150,7 +150,7 @@ nxp_mipi_i2c: &lpi2c5 {
 
 zephyr_udc0: &usb1 {
 	status = "okay";
-	phy_handle = <&usbphy1>;
+	phy-handle = <&usbphy1>;
 };
 
 &usbphy1 {
diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml
index bf2f139da10..976b0e71f12 100644
--- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml
+++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7.yaml
@@ -4,14 +4,13 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-identifier: mimxrt1170_evk/mimxrt1176/cm7
+identifier: mimxrt1170_evk@A/mimxrt1176/cm7
 name: NXP MIMXRT1170-EVK CM7
 type: mcu
 arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 256
 flash: 16384
 supported:
diff --git a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml
index 9935c53c7d0..6765cf82f25 100644
--- a/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml
+++ b/boards/nxp/mimxrt1170_evk/mimxrt1170_evk_mimxrt1176_cm7_B.yaml
@@ -1,5 +1,5 @@
 #
-# Copyright 2023 NXP
+# Copyright 2023, 2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 65536
 flash: 65536
 supported:
@@ -24,8 +23,10 @@ supported:
   - hwinfo
   - i2c
   - mipi_dsi
+  - netif:eth
+  - pwm
   - spi
-  - usb_device
+  - usbd
   - video
   - watchdog
 vendor: nxp
diff --git a/boards/nxp/mimxrt1180_evk/CMakeLists.txt b/boards/nxp/mimxrt1180_evk/CMakeLists.txt
index 1fbff933116..d1df93939c7 100644
--- a/boards/nxp/mimxrt1180_evk/CMakeLists.txt
+++ b/boards/nxp/mimxrt1180_evk/CMakeLists.txt
@@ -15,7 +15,7 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER)
      "update your flash configuration or device configuration data blocks")
   endif()
   set(RT1180_BOARD_DIR
-    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1180")
+    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1180")
   if(CONFIG_BOOT_FLEXSPI_NOR)
     # Include flash configuration block for RT1180 EVK from NXP's HAL.
     # This configuration block may need modification if another flash chip is
diff --git a/boards/nxp/mimxrt1180_evk/Kconfig b/boards/nxp/mimxrt1180_evk/Kconfig
new file mode 100644
index 00000000000..af3247b1354
--- /dev/null
+++ b/boards/nxp/mimxrt1180_evk/Kconfig
@@ -0,0 +1,5 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MIMXRT1180_EVK
+	select BOARD_EARLY_INIT_HOOK
diff --git a/boards/nxp/mimxrt1180_evk/Kconfig.defconfig b/boards/nxp/mimxrt1180_evk/Kconfig.defconfig
index a71be9a7729..2724201d047 100644
--- a/boards/nxp/mimxrt1180_evk/Kconfig.defconfig
+++ b/boards/nxp/mimxrt1180_evk/Kconfig.defconfig
@@ -1,6 +1,6 @@
 # MIMXRT1180-EVK board
 
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 if BOARD_MIMXRT1180_EVK
@@ -12,6 +12,19 @@ config EXTERNAL_MEM_CONFIG_DATA
 config NXP_IMX_EXTERNAL_HYPERRAM
 	default y if CPU_CORTEX_M33
 
-config BOARD_EARLY_INIT_HOOK
+if SECOND_CORE_MCUX && BOARD_MIMXRT1180_EVK_MIMXRT1189_CM7
+
+config BUILD_OUTPUT_INFO_HEADER
 	default y
+
+DT_CHOSEN_IMAGE_M7 = nxp,m7-partition
+
+# Adjust the offset of the output image if building for RT18xx SOC
+config BUILD_OUTPUT_ADJUST_LMA
+	default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_M7)) + \
+	$(dt_node_reg_addr_hex,/soc/spi@425e0000,1)) - \
+	$(dt_node_reg_addr_hex,/soc/itcm@0)"
+
+endif
+
 endif # BOARD_MIMXRT1180_EVK
diff --git a/boards/nxp/mimxrt1180_evk/board.c b/boards/nxp/mimxrt1180_evk/board.c
index 6ecd6a868b0..976f3dfcfda 100644
--- a/boards/nxp/mimxrt1180_evk/board.c
+++ b/boards/nxp/mimxrt1180_evk/board.c
@@ -12,11 +12,17 @@ void board_early_init_hook(void)
 {
 #if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0)
 	/* RMII mode */
+	BLK_CTRL_WAKEUPMIX->NETC_LINK_CFG[0] = BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_MII_PROT(1);
 	BLK_CTRL_WAKEUPMIX->NETC_LINK_CFG[4] = BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_MII_PROT(1);
+	/* RGMII mode */
+	BLK_CTRL_WAKEUPMIX->NETC_LINK_CFG[1] = BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_MII_PROT(2);
+	BLK_CTRL_WAKEUPMIX->NETC_LINK_CFG[2] = BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_MII_PROT(2);
+	BLK_CTRL_WAKEUPMIX->NETC_LINK_CFG[3] = BLK_CTRL_WAKEUPMIX_NETC_LINK_CFG_MII_PROT(2);
 
 	/* Output reference clock for RMII */
 	BLK_CTRL_WAKEUPMIX->NETC_PORT_MISC_CFG |=
-		BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT4_RMII_REF_CLK_DIR_MASK;
+		BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT4_RMII_REF_CLK_DIR_MASK |
+		BLK_CTRL_WAKEUPMIX_NETC_PORT_MISC_CFG_PORT0_RMII_REF_CLK_DIR_MASK;
 
 	/* Unlock the IERB. It will warm reset whole NETC. */
 	NETC_PRIV->NETCRR &= ~NETC_PRIV_NETCRR_LOCK_MASK;
diff --git a/boards/nxp/mimxrt1180_evk/board.cmake b/boards/nxp/mimxrt1180_evk/board.cmake
index 36f76d83153..71701f8a6c0 100644
--- a/boards/nxp/mimxrt1180_evk/board.cmake
+++ b/boards/nxp/mimxrt1180_evk/board.cmake
@@ -1,15 +1,15 @@
 #
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
 
 set(RT1180_BOARD_DIR
-"${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1180")
+"${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1180")
 # Note1: Suggest developers use Secure Provisioning Tool(SPT) to download RT1180 image
 # SPT can be downloaded on NXP web: https://www.nxp.com/design/design-center/software/development-software/mcuxpresso-software-and-tools-/mcuxpresso-secure-provisioning-tool:MCUXPRESSO-SECURE-PROVISIONING
 # Details about the usage of SPT on MIMXRT1180-EVK board can be referred on chapter 7 of getting start with Mcuxpresso SDK for MIMXRT1180-EVK doc in SDK package.
-if(CONFIG_SOC_MIMXRT1189_CM33)
+if(CONFIG_SOC_MIMXRT1189_CM33 OR CONFIG_SECOND_CORE_MCUX)
 board_runner_args(linkserver  "--device=MIMXRT1189xxxxx:MIMXRT1180-EVK")
 board_runner_args(jlink "--device=MIMXRT1189xxx8_M33" "--reset-after-load" "--tool-opt=-jlinkscriptfile ${RT1180_BOARD_DIR}/jlinkscript/evkmimxrt1180_cm33.jlinkscript")
 elseif(CONFIG_SOC_MIMXRT1189_CM7)
@@ -19,5 +19,5 @@ board_runner_args(linkserver "--core=cm7")
 board_runner_args(jlink "--device=MIMXRT1189xxx8_M7" "--speed=4000" "--no-reset" "--tool-opt=-jlinkscriptfile ${RT1180_BOARD_DIR}/jlinkscript/evkmimxrt1180_cm7.jlinkscript" "--tool-opt=-ir")
 endif()
 
-include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/nxp/mimxrt1180_evk/doc/index.rst b/boards/nxp/mimxrt1180_evk/doc/index.rst
index d9dcdaed721..07836b47c19 100644
--- a/boards/nxp/mimxrt1180_evk/doc/index.rst
+++ b/boards/nxp/mimxrt1180_evk/doc/index.rst
@@ -13,8 +13,9 @@ Hardware
 
 - MIMXRT1189CVM8B MCU
 
-  - 240MHz Cortex-M33 & 792Mhz Cortex-M7
-  - 1.5MB SRAM with 512KB of TCM for Cortex-M7 and 256KB of TCM for Cortex-M4
+  - 240MHz Cortex-M33 with 256KB TCM and 16 KB caches
+  - 792Mhz Cortex-M7 with 512KB TCM and 32 KB caches
+  - 1.5MB SRAM
 
 - Memory
 
@@ -70,7 +71,7 @@ This platform has the following external memories:
 |                    |            | data block, which sets up SEMC at   |
 |                    |            | boot time                           |
 +--------------------+------------+-------------------------------------+
-| W25Q128JWSIQ       | FLEXSPI    | Enabled via flash configurationn    |
+| W25Q128JWSIQ       | FLEXSPI    | Enabled via flash configuration     |
 |                    |            | block, which sets up FLEXSPI at     |
 |                    |            | boot time.                          |
 +--------------------+------------+-------------------------------------+
@@ -81,51 +82,9 @@ Supported Features
 NXP considers the MIMXRT1180-EVK as the superset board for the i.MX RT118x
 family of MCUs.  This board is a focus for NXP's Full Platform Support for
 Zephyr, to better enable the entire RT118x family.  NXP prioritizes enabling
-this board with new support for Zephyr features.  The mimxrt1180_evk board
-configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| GPT       | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| QTMR      | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| ACMP      | on-chip    | sensor                              |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| NETC      | on-chip    | ethernet, mdio                      |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
-| LPTMR     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| FLEXSPI   | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | tpm                                 |
-+-----------+------------+-------------------------------------+
-| I3C       | on-chip    | i3c                                 |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33_defconfig`
-
-Other hardware features are not currently supported by the port.
+this board with new support for Zephyr features.
 
+.. zephyr:board-supported-hw::
 
 Connections and I/Os
 ====================
@@ -139,11 +98,26 @@ The MIMXRT1180 SoC has six pairs of pinmux/gpio controllers.
 +---------------+-----------------+---------------------------+
 | GPIO_AD_27    | GPIO            | LED                       |
 +---------------+-----------------+---------------------------+
-| GPIO_AON_08   | LPUART1_TX      | UART Console              |
+| GPIO_AON_08   | LPUART1_TX      | UART Console M33 core     |
 +---------------+-----------------+---------------------------+
-| GPIO_AON_09   | LPUART1_RX      | UART Console              |
+| GPIO_AON_09   | LPUART1_RX      | UART Console M33 core     |
++---------------+---------------------------------------------+
+| GPIO_AON_19   | LPUART12_TX     | UART Console M7 core      |
++---------------+-----------------+---------------------------+
+| GPIO_AON_20   | LPUART12_RX     | UART Console M7 core      |
++---------------+-----------------+---------------------------+
+| GPIO_SD_B1_00 | SPI1_CS0        | spi                       |
++---------------+---------------------------------------------+
+| GPIO_SD_B1_01 | SPI1_CLK        | spi                       |
++---------------+---------------------------------------------+
+| GPIO_SD_B1_02 | SPI1_SDO        | spi                       |
++---------------+---------------------------------------------+
+| GPIO_SD_B1_03 | SPI1_SDI        | spi                       |
 +---------------+-----------------+---------------------------+
 
+UART for M7 core is connected to USB-to-UART J60 connector.
+Or user can use open JP7 Jumper to enable second UART on MCU LINK J53 connector.
+
 System Clock
 ============
 
@@ -154,35 +128,66 @@ running at 792MHz
 Serial Port
 ===========
 
-The MIMXRT1180 SoC has 12 UARTs. One is configured for the console and the
-remaining are not used.
+The MIMXRT1180 SoC has 12 UARTs. LPUART1 is configured for the CM33 console, the LPUART12 is
+configured for the CM7 console core and the remaining are not used.
 
 Ethernet
 ========
 
-NETC driver supports to manage the Physical Station Interface (PSI).
+NETC Ethernet driver supports to manage the Physical Station Interface (PSI).
+NETC DSA driver supports to manage switch ports. Current DSA support is with
+limitation that only switch function is available without management via
+DSA master port. DSA master port support is TODO work.
+
+.. code-block:: none
+
+                   +--------+                  +--------+
+                   | ENETC1 |                  | ENETC0 |
+                   |        |                  |        |
+                   | Pseudo |                  |  1G    |
+                   |  MAC   |                  |  MAC   |
+                   +--------+                  +--------+
+                       | zero copy interface       |
+   +-------------- +--------+----------------+     |
+   |               | Pseudo |                |     |
+   |               |  MAC   |                |     |
+   |               |        |                |     |
+   |               | Port 4 |                |     |
+   |               +--------+                |     |
+   |           SWITCH       CORE             |     |
+   +--------+ +--------+ +--------+ +--------+     |
+   | Port 0 | | Port 1 | | Port 2 | | Port 3 |     |
+   |        | |        | |        | |        |     |
+   |  1G    | |  1G    | |  1G    | |  1G    |     |
+   |  MAC   | |  MAC   | |  MAC   | |  MAC   |     |
+   +--------+-+--------+-+--------+-+--------+     |
+       |          |          |          |          |
+   NETC External Interfaces (4 switch ports, 1 end-point port)
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
 Configuring a Debug Probe
 =========================
 
+LinkServer is the default runner for this board.
 A debug probe is used for both flashing and debugging the board. This board is
-configured by default to use the :ref:`mcu-link-cmsis-onboard-debug-probe`,
-however the :ref:`pyocd-debug-host-tools` do not yet support programming the
-external flashes on this board so you must reconfigure the board for one of the
-following debug probes instead.
+configured by default to use the :ref:`mcu-link-cmsis-onboard-debug-probe`.
+The :ref:`pyocd-debug-host-tools` do not yet support programming the
+external flashes on this board. Use one of the other supported debug probes
+below.
 
 .. _Using J-Link RT1180:
 
 Using J-Link
 ------------
 
-Please ensure used JLINK above V7.94g and jumper JP5 installed if using
+Please ensure to use a version of JLINK above V7.94g and jumper JP5 is installed if using
 external jlink plus on J37 as debugger.
 
 When debugging cm33 core, need to ensure the SW5 on "0100" mode.
@@ -200,12 +205,22 @@ EVK.
 Using Linkserver
 ----------------
 
-Please ensure used linkserver above V1.5.30 and jumper JP5 uninstalled.
+Please ensure to use a version of Linkserver above V1.5.30 and jumper JP5 is uninstalled (default setting).
 
 When debugging cm33 core, need to ensure the SW5 on "0100" mode.
 When debugging cm7 core, need to ensure the SW5 on "0001" mode.
 (Only support run cm7 image when debugging due to default boot core on board is cm33 core)
 
+Dual Core samples Debugging
+***************************
+
+When debugging dual core samples, need to ensure the SW5 on "0100" mode.
+The CM33 core is responsible for copying and starting the CM7.
+To debug the CM7 it is useful to put infinite while loop either in reset vector or
+into main function and attach via debugger to CM7 core.
+
+CM7 core can be started again only after reset, so after flashing ensure to reset board.
+
 Configuring a Console
 =====================
 
@@ -263,6 +278,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS v3.7.0-xxx-xxxxxxxxxxxxx *****
    Hello World! mimxrt1180_evk/mimxrt1189/cm33
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _MIMXRT1180-EVK Website:
    https://www.nxp.com/design/design-center/development-boards-and-designs/i-mx-evaluation-and-development-boards/i-mx-rt1180-evaluation-kit:MIMXRT1180-EVK
 
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi
index bfaa7852dce..a0ee4993f68 100644
--- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  * SPDX-License-Identifier: Apache-2.0
  *
  */
@@ -17,6 +17,88 @@
 		};
 	};
 
+	eth0_default: eth0_default {
+		group1 {
+			pinmux = <&iomuxc_gpio_emc_b2_05_eth0_tx_data0>,
+				<&iomuxc_gpio_emc_b2_06_eth0_tx_data1>,
+				<&iomuxc_gpio_emc_b2_07_eth0_tx_en>,
+				<&iomuxc_gpio_emc_b2_09_eth0_rx_data0>,
+				<&iomuxc_gpio_emc_b2_10_eth0_rx_data1>,
+				<&iomuxc_gpio_emc_b2_11_eth0_rx_en>,
+				<&iomuxc_gpio_emc_b2_12_eth0_rx_er>;
+			bias-pull-down;
+			slew-rate = "fast";
+			drive-strength = "high";
+		};
+		group2 {
+			pinmux = <&iomuxc_gpio_emc_b2_08_eth0_tx_clk>;
+			input-enable;
+			bias-pull-down;
+			slew-rate = "fast";
+			drive-strength = "high";
+		};
+	};
+
+	eth1_default: eth1_default {
+		group1 {
+			pinmux = <&iomuxc_gpio_b1_00_eth1_tx_data0>,
+				<&iomuxc_gpio_b1_01_eth1_tx_data1>,
+				<&iomuxc_gpio_b1_02_eth1_tx_en>,
+				<&iomuxc_gpio_b1_03_eth1_tx_clk >,
+				<&iomuxc_gpio_b1_04_eth1_rx_data0>,
+				<&iomuxc_gpio_b1_05_eth1_rx_data1>,
+				<&iomuxc_gpio_b1_06_eth1_rx_en>,
+				<&iomuxc_gpio_b1_07_eth1_tx_data2>,
+				<&iomuxc_gpio_b1_08_eth1_tx_data3>,
+				<&iomuxc_gpio_b1_09_eth1_rx_data2>,
+				<&iomuxc_gpio_b1_10_eth1_rx_data3>,
+				<&iomuxc_gpio_b1_11_eth1_rx_clk>;
+			bias-pull-down;
+			slew-rate = "fast";
+			drive-strength = "high";
+		};
+	};
+
+	eth2_default: eth2_default {
+		group1 {
+			pinmux = <&iomuxc_gpio_emc_b1_13_eth2_rx_en>,
+				<&iomuxc_gpio_emc_b1_16_eth2_rx_data0>,
+				<&iomuxc_gpio_emc_b1_17_eth2_rx_data1>,
+				<&iomuxc_gpio_emc_b1_21_eth2_rx_clk>,
+				<&iomuxc_gpio_emc_b1_22_eth2_rx_data2>,
+				<&iomuxc_gpio_emc_b1_23_eth2_rx_data3>,
+				<&iomuxc_gpio_emc_b1_24_eth2_tx_data3>,
+				<&iomuxc_gpio_emc_b1_25_eth2_tx_data2>,
+				<&iomuxc_gpio_emc_b1_26_eth2_tx_data1>,
+				<&iomuxc_gpio_emc_b1_27_eth2_tx_data0>,
+				<&iomuxc_gpio_emc_b1_28_eth2_tx_en>,
+				<&iomuxc_gpio_emc_b1_29_eth2_tx_clk>;
+			bias-pull-down;
+			slew-rate = "fast";
+			drive-strength = "high";
+		};
+	};
+
+	eth3_default: eth3_default {
+		group1 {
+			pinmux = <&iomuxc_gpio_emc_b1_00_eth3_tx_data3>,
+				<&iomuxc_gpio_emc_b1_01_eth3_tx_data2>,
+				<&iomuxc_gpio_emc_b1_02_eth3_rx_clk>,
+				<&iomuxc_gpio_emc_b1_03_eth3_rx_data3>,
+				<&iomuxc_gpio_emc_b1_04_eth3_rx_data2>,
+				<&iomuxc_gpio_emc_b1_05_eth3_tx_data0>,
+				<&iomuxc_gpio_emc_b1_06_eth3_tx_data1>,
+				<&iomuxc_gpio_emc_b1_07_eth3_tx_en>,
+				<&iomuxc_gpio_emc_b1_08_eth3_tx_clk>,
+				<&iomuxc_gpio_emc_b1_09_eth3_rx_data0>,
+				<&iomuxc_gpio_emc_b1_10_eth3_rx_data1>,
+				<&iomuxc_gpio_emc_b1_11_eth3_rx_en>;
+			bias-pull-down;
+			slew-rate = "fast";
+			drive-strength = "high";
+		};
+	};
+
 	eth4_default: eth4_default {
 		group1 {
 			pinmux = <&iomuxc_gpio_emc_b2_13_eth4_tx_data0>,
@@ -73,6 +155,52 @@
 		};
 	};
 
+	pinmux_lpuart12: pinmux_lpuart12 {
+		group0 {
+			pinmux = <&iomuxc_aon_gpio_aon_20_lpuart12_rxd>,
+				<&iomuxc_aon_gpio_aon_19_lpuart12_txd>;
+			drive-strength = "high";
+			slew-rate = "fast";
+		};
+	};
+
+	pinmux_lpuart12_sleep: pinmux_lpuart12_sleep {
+		group0 {
+			pinmux = <&iomuxc_aon_gpio_aon_20_lpuart12_rxd>;
+			drive-strength = "high";
+			bias-pull-up;
+			slew-rate = "fast";
+		};
+		group1 {
+			pinmux = <&iomuxc_aon_gpio_aon_19_lpuart12_txd>;
+			drive-strength = "high";
+			slew-rate = "fast";
+		};
+	};
+
+	pinmux_lpuart3: pinmux_lpuart3 {
+		group0 {
+			pinmux = <&iomuxc_gpio_ad_14_lpuart3_rxd>,
+				<&iomuxc_gpio_ad_13_lpuart3_txd>;
+			drive-strength = "high";
+			slew-rate = "fast";
+		};
+	};
+
+	pinmux_lpuart3_sleep: pinmux_lpuart3_sleep {
+		group0 {
+			pinmux = <&iomuxc_gpio_ad_14_gpio4_io14>;
+			drive-strength = "high";
+			bias-pull-up;
+			slew-rate = "fast";
+		};
+		group1 {
+			pinmux = <&iomuxc_gpio_ad_13_lpuart3_txd>;
+			drive-strength = "high";
+			slew-rate = "fast";
+		};
+	};
+
 	/* Connected to FXLS8974 */
 	pinmux_lpi2c2: pinmux_lpi2c2 {
 		group0 {
@@ -162,4 +290,61 @@
 			drive-strength = "high";
 		};
 	};
+
+	pinmux_usdhc1: pinmux_usdhc1 {
+		group0 {
+			pinmux = <&iomuxc_gpio_sd_b1_00_usdhc1_cmd>,
+				<&iomuxc_gpio_sd_b1_01_usdhc1_clk>,
+				<&iomuxc_gpio_sd_b1_02_usdhc1_data0>,
+				<&iomuxc_gpio_sd_b1_03_usdhc1_data1>,
+				<&iomuxc_gpio_sd_b1_04_usdhc1_data2>,
+				<&iomuxc_gpio_sd_b1_05_usdhc1_data3>;
+			bias-pull-up;
+			input-enable;
+		};
+		group1 {
+			pinmux = <&iomuxc_gpio_ad_34_usdhc1_vselect>,
+				<&iomuxc_gpio_ad_15_gpio4_io15>;
+			drive-strength = "high";
+			bias-pull-down;
+			slew-rate = "fast";
+		};
+		group2 {
+			pinmux = <&iomuxc_gpio_ad_14_gpio4_io14>;
+			drive-strength = "high";
+			bias-pull-up;
+			slew-rate = "fast";
+		};
+	};
+
+	/* removes pull on dat3 for card detect */
+	pinmux_usdhc1_dat3_nopull: pinmux_usdhc1_dat3_nopull {
+		group0 {
+			pinmux = <&iomuxc_gpio_sd_b1_05_usdhc1_data3>;
+			bias-disable;
+			input-enable;
+		};
+		group1 {
+			pinmux = <&iomuxc_gpio_sd_b1_00_usdhc1_cmd>,
+				<&iomuxc_gpio_sd_b1_01_usdhc1_clk>,
+				<&iomuxc_gpio_sd_b1_02_usdhc1_data0>,
+				<&iomuxc_gpio_sd_b1_03_usdhc1_data1>,
+				<&iomuxc_gpio_sd_b1_04_usdhc1_data2>;
+			bias-pull-up;
+			input-enable;
+		};
+		group2 {
+			pinmux = <&iomuxc_gpio_ad_34_usdhc1_vselect>,
+				<&iomuxc_gpio_ad_15_gpio4_io15>;
+			drive-strength = "high";
+			bias-pull-down;
+			slew-rate = "fast";
+		};
+		group3 {
+			pinmux = <&iomuxc_gpio_ad_14_gpio4_io14>;
+			drive-strength = "high";
+			bias-pull-up;
+			slew-rate = "fast";
+		};
+	};
 };
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi
index 5af9c455524..699c1a6457d 100644
--- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,7 @@
 		led0 = &green_led;
 		sw0 = &user_button;
 		pwm-led0 = &green_pwm_led;
+		sdhc0 = &usdhc1;
 	};
 
 	leds {
@@ -19,7 +20,7 @@
 		green_led: led-1 {
 			gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>;
 			label = "User LED D6";
-	    };
+		};
 	};
 
 	gpio_keys {
@@ -39,6 +40,102 @@
 	};
 };
 
+&emdio {
+	pinctrl-0 = <&emdio_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	phy0: phy@2 {
+		compatible = "ethernet-phy";
+		reg = <0x2>;
+		status = "okay";
+	};
+
+	phy1: phy@5 {
+		compatible = "realtek,rtl8211f";
+		reg = <0x5>;
+		status = "okay";
+	};
+
+	phy2: phy@4 {
+		compatible = "realtek,rtl8211f";
+		reg = <0x4>;
+		status = "okay";
+	};
+
+	phy3: phy@7 {
+		compatible = "realtek,rtl8211f";
+		reg = <0x7>;
+		status = "okay";
+	};
+
+	phy4: phy@3 {
+		compatible = "ethernet-phy";
+		reg = <0x3>;
+		status = "okay";
+	};
+};
+
+&enetc_psi0 {
+	local-mac-address = [00 00 00 01 02 00];
+	pinctrl-0 = <&eth4_default>;
+	pinctrl-names = "default";
+	phy-handle = <&phy4>;
+	status = "okay";
+};
+
+/* Internal port */
+&enetc_psi1 {
+	local-mac-address = [00 00 00 01 03 00];
+	status = "okay";
+};
+
+&switch {
+	status = "okay";
+};
+
+&switch_port0 {
+	zephyr,random-mac-address;
+	pinctrl-0 = <&eth0_default>;
+	pinctrl-names = "default";
+	phy-handle = <&phy0>;
+	phy-connection-type = "rmii";
+	status = "okay";
+};
+
+&switch_port1 {
+	zephyr,random-mac-address;
+	pinctrl-0 = <&eth1_default>;
+	pinctrl-names = "default";
+	phy-handle = <&phy1>;
+	phy-connection-type = "rgmii";
+	status = "okay";
+};
+
+&switch_port2 {
+	zephyr,random-mac-address;
+	pinctrl-0 = <&eth2_default>;
+	pinctrl-names = "default";
+	phy-handle = <&phy2>;
+	phy-connection-type = "rgmii";
+	status = "okay";
+};
+
+&switch_port3 {
+	zephyr,random-mac-address;
+	pinctrl-0 = <&eth3_default>;
+	pinctrl-names = "default";
+	phy-handle = <&phy3>;
+	phy-connection-type = "rgmii";
+	status = "okay";
+};
+
+/* Internal port */
+&switch_port4 {
+	zephyr,random-mac-address;
+	status = "okay";
+};
+
 &lpuart1 {
 	status = "okay";
 	current-speed = <115200>;
@@ -47,6 +144,20 @@
 	pinctrl-names = "default", "sleep";
 };
 
+&lpuart12 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&pinmux_lpuart12>;
+	pinctrl-1 = <&pinmux_lpuart12_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&lpuart3 {
+	pinctrl-0 = <&pinmux_lpuart3>;
+	pinctrl-1 = <&pinmux_lpuart3_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
 &user_button {
 	status = "okay";
 };
@@ -152,3 +263,25 @@
 
 p3t1755dp_ard_i3c_interface: &i3c2 {};
 p3t1755dp_ard_i2c_interface: &lpi2c2 {};
+
+&lpspi3 {
+	dmas = <&edma4 1 13>, <&edma4 2 12>;
+	dma-names = "rx", "tx";
+	pinctrl-0 = <&pinmux_lpspi3>;
+	pinctrl-names = "default";
+};
+
+&usdhc1 {
+	status = "okay";
+	detect-dat3;
+	no-1-8-v;
+	pwr-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&pinmux_usdhc1>;
+	pinctrl-1 = <&pinmux_usdhc1_dat3_nopull>;
+	pinctrl-names = "default", "nopull";
+	sdmmc {
+		compatible = "zephyr,sdmmc-disk";
+		disk-name = "SD";
+		status = "okay";
+	};
+};
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts
index 97a3752628b..528c2f4357b 100644
--- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.dts
@@ -19,8 +19,10 @@
 		zephyr,itcm = &itcm;
 		zephyr,flash-controller = &w25q128jw;
 		zephyr,flash = &w25q128jw;
+		zephyr,code-partition = &slot0_partition;
 		zephyr,console = &lpuart1;
 		zephyr,shell-uart = &lpuart1;
+		zephyr,uart-mcumgr = &lpuart1;
 		zephyr,canbus = &flexcan3;
 	};
 
@@ -31,26 +33,6 @@
 	};
 };
 
-&emdio {
-	pinctrl-0 = <&emdio_default>;
-	pinctrl-names = "default";
-	status = "okay";
-
-	phy4: phy@3 {
-		compatible = "ethernet-phy";
-		reg = <0x3>;
-		status = "okay";
-	};
-};
-
-&enetc_psi0 {
-	local-mac-address = [00 00 00 01 02 00];
-	pinctrl-0 = <&eth4_default>;
-	pinctrl-names = "default";
-	phy-handle = <&phy4>;
-	status = "okay";
-};
-
 &lpuart1 {
 	status = "okay";
 	current-speed = <115200>;
@@ -79,3 +61,39 @@
 &i3c2 {
 	status = "okay";
 };
+
+&lpspi3 {
+	status = "okay";
+};
+
+&edma3 {
+	status = "okay";
+};
+
+&edma4 {
+	status = "okay";
+};
+
+zephyr_udc0: &usb1 {
+	status = "okay";
+	phy-handle = <&usbphy1>;
+};
+
+&usbphy1 {
+	status = "okay";
+	tx-d-cal = <7>;
+	tx-cal-45-dp-ohms = <6>;
+	tx-cal-45-dm-ohms = <6>;
+};
+
+zephyr_udc1: &usb2{
+	status = "okay";
+	phy-handle = <&usbphy2>;
+};
+
+&usbphy2 {
+	status = "okay";
+	tx-d-cal = <7>;
+	tx-cal-45-dp-ohms = <6>;
+	tx-cal-45-dm-ohms = <6>;
+};
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml
index bddd1e8a0a3..5af46ebc691 100644
--- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm33.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 16384
 supported:
@@ -21,8 +20,14 @@ supported:
   - flash
   - gpio
   - i2c
+  - mbox
   - netif:eth
   - pwm
   - uart
   - i3c
+  - dma
+  - spi
+  - watchdog
+  - usbd
+  - sdhc
 vendor: nxp
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts
index 7e003fe903e..c6a3499c778 100644
--- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,15 +15,24 @@
 
 	chosen {
 		zephyr,sram = &dtcm;
+		zephyr,dtcm = &dtcm;
+		zephyr,itcm = &itcm;
 		zephyr,flash-controller = &w25q128jw;
 		zephyr,flash = &itcm;
-		zephyr,console = &lpuart1;
-		zephyr,shell-uart = &lpuart1;
+		zephyr,console = &lpuart12;
+		zephyr,shell-uart = &lpuart12;
 		zephyr,canbus = &flexcan3;
+		nxp,m7-partition = &slot1_partition;
+	};
+
+	hyperram0: memory@04000000 {
+		/* Winbond W957A8MFYA5K */
+		device_type = "memory";
+		reg = <0x04000000 DT_SIZE_M(8)>;
 	};
 };
 
-&lpuart1 {
+&lpuart12 {
 	status = "okay";
 	current-speed = <115200>;
 };
@@ -51,3 +60,39 @@
 &i3c2 {
 	status = "okay";
 };
+
+&lpspi3 {
+	status = "okay";
+};
+
+&edma3 {
+	status = "okay";
+};
+
+&edma4 {
+	status = "okay";
+};
+
+zephyr_udc0: &usb1 {
+	status = "okay";
+	phy-handle = <&usbphy1>;
+};
+
+&usbphy1 {
+	status = "okay";
+	tx-d-cal = <7>;
+	tx-cal-45-dp-ohms = <6>;
+	tx-cal-45-dm-ohms = <6>;
+};
+
+zephyr_udc1: &usb2{
+	status = "okay";
+	phy-handle = <&usbphy2>;
+};
+
+&usbphy2 {
+	status = "okay";
+	tx-d-cal = <7>;
+	tx-cal-45-dp-ohms = <6>;
+	tx-cal-45-dm-ohms = <6>;
+};
diff --git a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml
index 60b954ec533..34b0b8d7961 100644
--- a/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml
+++ b/boards/nxp/mimxrt1180_evk/mimxrt1180_evk_mimxrt1189_cm7.yaml
@@ -11,17 +11,20 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 256
 flash: 256
 supported:
   - adc
   - can
   - counter
+  - dma
   - flash
   - gpio
   - i2c
+  - i3c
+  - mbox
   - pwm
+  - sdhc
+  - spi
   - uart
-  - i3c
 vendor: nxp
diff --git a/boards/nxp/mimxrt595_evk/CMakeLists.txt b/boards/nxp/mimxrt595_evk/CMakeLists.txt
index 79cb85e0664..9cea226cf29 100644
--- a/boards/nxp/mimxrt595_evk/CMakeLists.txt
+++ b/boards/nxp/mimxrt595_evk/CMakeLists.txt
@@ -22,7 +22,7 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER)
   zephyr_compile_definitions(BOOT_HEADER_ENABLE=1)
   zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024)
   set(RT595_BOARD_DIR
-    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt595")
+    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt595")
   zephyr_library_sources(${RT595_BOARD_DIR}/flash_config/flash_config.c)
   zephyr_library_include_directories(${RT595_BOARD_DIR}/flash_config)
 endif()
diff --git a/boards/nxp/mimxrt595_evk/Kconfig b/boards/nxp/mimxrt595_evk/Kconfig
index c97c859f16d..33b997c2518 100644
--- a/boards/nxp/mimxrt595_evk/Kconfig
+++ b/boards/nxp/mimxrt595_evk/Kconfig
@@ -1,12 +1,9 @@
-# Copyright 2022, NXP
+# Copyright 2022, 2025 NXP
 # Copyright (c) 2023 Google LLC.
 # SPDX-License-Identifier: Apache-2.0
 
-config BOARD_INIT_PRIORITY
-	int "Board initialization priority"
-	default 45
-	help
-	  Board initialization priority.
+config BOARD_MIMXRT595_EVK
+	select BOARD_EARLY_INIT_HOOK if BOARD_MIMXRT595_EVK_MIMXRT595S_CM33
 
 DT_ADSP_RESET_MEM := $(dt_nodelabel_path,adsp_reset)
 DT_ADSP_DATA_MEM := $(dt_nodelabel_path,adsp_data)
diff --git a/boards/nxp/mimxrt595_evk/board.c b/boards/nxp/mimxrt595_evk/board.c
index ecb6cbcd129..4c4e7f65cd6 100644
--- a/boards/nxp/mimxrt595_evk/board.c
+++ b/boards/nxp/mimxrt595_evk/board.c
@@ -263,7 +263,7 @@ __ramfunc int32_t power_manager_set_profile(uint32_t power_profile)
 
 #endif /* CONFIG_REGULATOR */
 
-static int mimxrt595_evk_init(void)
+void board_early_init_hook(void)
 {
 	/* Set the correct voltage range according to the board. */
 	power_pad_vrange_t vrange = {
@@ -352,7 +352,6 @@ static int mimxrt595_evk_init(void)
 	INPUTMUX_EnableSignal(INPUTMUX,
 			kINPUTMUX_I3c1TxToDmac1Ch31RequestEna, true);
 #endif /* dma1 */
-	INPUTMUX_Deinit(INPUTMUX);
 
 #ifdef CONFIG_REBOOT
 	/*
@@ -386,8 +385,6 @@ static int mimxrt595_evk_init(void)
 		rd_trim_96 = CLKCTL0->FRO_RDTRIM;
 		sc_trim_96 = sc_trim_192;
 	}
-
-	return 0;
 }
 
 
@@ -418,5 +415,3 @@ SYS_INIT(board_config_pmic, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY);
  */
 SYS_INIT(init_psram_framebufs, POST_KERNEL, CONFIG_APPLICATION_INIT_PRIORITY);
 #endif
-
-SYS_INIT(mimxrt595_evk_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);
diff --git a/boards/nxp/mimxrt595_evk/doc/index.rst b/boards/nxp/mimxrt595_evk/doc/index.rst
index 899d777a6ff..07bc895051c 100644
--- a/boards/nxp/mimxrt595_evk/doc/index.rst
+++ b/boards/nxp/mimxrt595_evk/doc/index.rst
@@ -54,67 +54,11 @@ Supported Features
 NXP considers the MIMXRT595-EVK as a superset board for the i.MX RT5xx
 family of MCUs.  This board is a focus for NXP's Full Platform Support for
 Zephyr, to better enable the entire RT5xx family.  NXP prioritizes enabling
-this board with new support for Zephyr features.  The mimxrt595_evk board
-configuration supports the hardware features below.  Another very similar
+this board with new support for Zephyr features.  Another very similar
 board is the :zephyr:board:`mimxrt685_evk`, and that board may have additional features
-already supported, which can also be re-used on this mimxrt595_evk board:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| OS_TIMER  | on-chip    | os timer                            |
-+-----------+------------+-------------------------------------+
-| IOCON     | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| USART     | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| CTIMER    | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| WDT       | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | OctalSPI Flash                      |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| FLEXSPI   | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| PM        | on-chip    | power management; uses SoC sleep,   |
-|           |            | deep sleep and deep-powerdown modes |
-+-----------+------------+-------------------------------------+
-| SDHC      | on-chip    | disk access (works with eMMC & SD)  |
-+-----------+------------+-------------------------------------+
-| I2S       | on-chip    | i2s                                 |
-+-----------+------------+-------------------------------------+
-| DISPLAY   | on-chip    | LCDIF; MIPI-DSI. Tested with        |
-|           |            | :ref:`rk055hdmipi4m`,               |
-|           |            | :ref:`rk055hdmipi4ma0`, and         |
-|           |            | :ref:`g1120b0mipi` display shields  |
-+-----------+------------+-------------------------------------+
-| DMIC      | on-chip    | dmic                                |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-
-   :zephyr_file:`boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33_defconfig`
-
-Other hardware features are not currently supported by the port.
+already supported, which can also be re-used on this mimxrt595_evk board.
+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -187,6 +131,8 @@ this document: `Getting Started with Xplorer for EVK-MIMXRT595`_
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -303,6 +249,9 @@ steps:
 
 #. Reset by pressing SW3
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _MIMXRT595-EVK Website:
    https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt595-evaluation-kit:MIMXRT595-EVK
 
diff --git a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml
index a2e8406c02b..65739236386 100644
--- a/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml
+++ b/boards/nxp/mimxrt595_evk/mimxrt595_evk_mimxrt595s_cm33.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 4608
 flash: 65536
 supported:
diff --git a/boards/nxp/mimxrt685_evk/CMakeLists.txt b/boards/nxp/mimxrt685_evk/CMakeLists.txt
index c08b123bdc1..53eb5a6e13e 100644
--- a/boards/nxp/mimxrt685_evk/CMakeLists.txt
+++ b/boards/nxp/mimxrt685_evk/CMakeLists.txt
@@ -21,7 +21,7 @@ if(CONFIG_NXP_IMXRT_BOOT_HEADER)
   zephyr_compile_definitions(BOOT_HEADER_ENABLE=1)
   zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024)
   set(RT685_BOARD_DIR
-    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt685")
+    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt685")
   zephyr_library_sources(${RT685_BOARD_DIR}/flash_config/flash_config.c)
   zephyr_library_include_directories(${RT685_BOARD_DIR}/flash_config)
 endif()
diff --git a/boards/nxp/mimxrt685_evk/Kconfig b/boards/nxp/mimxrt685_evk/Kconfig
index 593dcf929c6..88f3b34861b 100644
--- a/boards/nxp/mimxrt685_evk/Kconfig
+++ b/boards/nxp/mimxrt685_evk/Kconfig
@@ -1,8 +1,6 @@
+# Copyright 2025 NXP
 # Copyright (c) 2022 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-config BOARD_INIT_PRIORITY
-	int "Board initialization priority"
-	default 45
-	help
-	  Board initialization priority.
+config BOARD_MIMXRT685_EVK
+	select BOARD_EARLY_INIT_HOOK
diff --git a/boards/nxp/mimxrt685_evk/doc/index.rst b/boards/nxp/mimxrt685_evk/doc/index.rst
index ebd1d9c1d31..6acc0cbdc6c 100644
--- a/boards/nxp/mimxrt685_evk/doc/index.rst
+++ b/boards/nxp/mimxrt685_evk/doc/index.rst
@@ -50,62 +50,11 @@ Supported Features
 NXP considers the MIMXRT685-EVK as a superset board for the i.MX RT6xx
 family of MCUs.  This board is a focus for NXP's Full Platform Support for
 Zephyr, to better enable the entire RT6xx family.  NXP prioritizes enabling
-this board with new support for Zephyr features.  The mimxrt685_evk board
-configuration supports the hardware features below.  Another very similar
+this board with new support for Zephyr features.  Another very similar
 board is the :zephyr:board:`mimxrt595_evk`, and that board may have additional features
-already supported, which can also be re-used on this mimxrt685_evk board:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| OS_TIMER  | on-chip    | os timer                            |
-+-----------+------------+-------------------------------------+
-| IOCON     | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | OctalSPI Flash                      |
-+-----------+------------+-------------------------------------+
-| USART     | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| I2S       | on-chip    | i2s                                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| HWINFO    | on-chip    | Unique device serial number         |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| WDT       | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| SDHC      | on-chip    | disk access                         |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| CTIMER    | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| FLEXSPI   | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33_defconfig`
-
-Other hardware features are not currently supported by the port.
+already supported, which can also be re-used on this mimxrt685_evk board.
+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -208,6 +157,8 @@ configured as USART for the console and the remaining are not used.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -343,6 +294,9 @@ steps:
 
 #. Reset by pressing SW3
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _MIMXRT685-EVK Website:
    https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt600-evaluation-kit:MIMXRT685-EVK
 
diff --git a/boards/nxp/mimxrt685_evk/init.c b/boards/nxp/mimxrt685_evk/init.c
index 8c0cd087881..f2f6755aafa 100644
--- a/boards/nxp/mimxrt685_evk/init.c
+++ b/boards/nxp/mimxrt685_evk/init.c
@@ -7,7 +7,7 @@
 #include <zephyr/devicetree.h>
 #include <fsl_device_registers.h>
 
-static int mimxrt685_evk_init(void)
+void board_early_init_hook(void)
 {
 
 /* flexcomm1 and flexcomm3 are configured to loopback the TX signal to RX */
@@ -54,8 +54,4 @@ static int mimxrt685_evk_init(void)
 	 */
 	 OCOTP->OTP_SHADOW[97] = 0x314000;
 #endif /* CONFIG_REBOOT */
-
-	return 0;
 }
-
-SYS_INIT(mimxrt685_evk_init, PRE_KERNEL_1, CONFIG_BOARD_INIT_PRIORITY);
diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts
index bc091a2abf4..a92f00d2700 100644
--- a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts
+++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts
@@ -359,7 +359,7 @@ i2s1: &flexcomm3 {
 
 zephyr_udc0: &usbhs {
 	status = "okay";
-	phy_handle = <&usbphy>;
+	phy-handle = <&usbphy>;
 };
 
 &usbphy {
diff --git a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.yaml b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.yaml
index 75124a8e7da..8e861a3a3e5 100644
--- a/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.yaml
+++ b/boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 4608
 flash: 65536
 supported:
diff --git a/boards/nxp/mimxrt700_evk/CMakeLists.txt b/boards/nxp/mimxrt700_evk/CMakeLists.txt
new file mode 100644
index 00000000000..32c47fe3d95
--- /dev/null
+++ b/boards/nxp/mimxrt700_evk/CMakeLists.txt
@@ -0,0 +1,28 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if(CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0 OR CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU1)
+  zephyr_library()
+  zephyr_library_sources(board.c)
+endif()
+
+if(CONFIG_NXP_IMXRT_BOOT_HEADER)
+  if(NOT ((DEFINED CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0)
+  OR (DEFINED CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU1)))
+  message(WARNING "It appears you are using the board definition for "
+    "the MIMXRT7xx-EVK, but targeting a custom board. You may need to "
+    "update your flash configuration block data")
+  endif()
+  # Include flash configuration block for RT7xx EVK from NXP's HAL.
+  # This configuration block may need modification if another flash chip is
+  # used on your custom board. See NXP AN13304 for more information.
+  zephyr_compile_definitions(BOOT_HEADER_ENABLE=1)
+  zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024)
+  set(RT7XX_BOARD_DIR
+    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/mimxrt700evk")
+  zephyr_library_sources(${RT7XX_BOARD_DIR}/flash_config/flash_config.c)
+  zephyr_library_include_directories(${RT7XX_BOARD_DIR}/flash_config)
+endif()
diff --git a/boards/nxp/mimxrt700_evk/Kconfig b/boards/nxp/mimxrt700_evk/Kconfig
new file mode 100644
index 00000000000..26c13047452
--- /dev/null
+++ b/boards/nxp/mimxrt700_evk/Kconfig
@@ -0,0 +1,7 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MIMXRT700_EVK
+	select BOARD_EARLY_INIT_HOOK if \
+		BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0 || \
+		BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU1
diff --git a/boards/nxp/mimxrt700_evk/Kconfig.mimxrt700_evk b/boards/nxp/mimxrt700_evk/Kconfig.mimxrt700_evk
new file mode 100644
index 00000000000..1e27338890b
--- /dev/null
+++ b/boards/nxp/mimxrt700_evk/Kconfig.mimxrt700_evk
@@ -0,0 +1,9 @@
+# Copyright 2024-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_MIMXRT700_EVK
+	select SOC_MIMXRT798S_CM33_CPU0 if BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0
+	select SOC_MIMXRT798S_CM33_CPU1 if BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU1
+	select SOC_MIMXRT798S_HIFI4 if BOARD_MIMXRT700_EVK_MIMXRT798S_HIFI4
+	select SOC_MIMXRT798S_HIFI1 if BOARD_MIMXRT700_EVK_MIMXRT798S_HIFI1
+	select SOC_PART_NUMBER_MIMXRT798SGFOA
diff --git a/boards/nxp/mimxrt700_evk/board.c b/boards/nxp/mimxrt700_evk/board.c
new file mode 100644
index 00000000000..ef162aab824
--- /dev/null
+++ b/boards/nxp/mimxrt700_evk/board.c
@@ -0,0 +1,580 @@
+/*
+ * Copyright 2024-2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/init.h>
+#include <zephyr/device.h>
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include <soc.h>
+#include <fsl_glikey.h>
+
+/*!< System oscillator settling time in us */
+#define SYSOSC_SETTLING_US 220U
+/*!< xtal frequency in Hz */
+#define XTAL_SYS_CLK_HZ    24000000U
+
+#if CONFIG_SOC_MIMXRT798S_CM33_CPU0
+#define SYSCON_BASE DT_REG_ADDR(DT_NODELABEL(syscon0))
+#define EN_NUM 4
+#elif CONFIG_SOC_MIMXRT798S_CM33_CPU1
+#define SYSCON_BASE DT_REG_ADDR(DT_NODELABEL(syscon1))
+#define EN_NUM 2
+#endif
+
+#define EDMA_EN_OFFSET 0x420
+#define EDMA_EN_REG(instance, idx) ((uint32_t *)((uint32_t)(SYSCON_BASE) + \
+	(EDMA_EN_OFFSET) +  0x10U * (instance) + 4U * (idx)))
+
+#define SET_UP_FLEXCOMM_CLOCK(x)                                                                   \
+	do {                                                                                       \
+		CLOCK_AttachClk(kFCCLK0_to_FLEXCOMM##x);                                           \
+		RESET_ClearPeripheralReset(kFC##x##_RST_SHIFT_RSTn);                               \
+		CLOCK_EnableClock(kCLOCK_LPFlexComm##x);                                           \
+	} while (0)
+
+#ifdef CONFIG_SOC_MIMXRT798S_CM33_CPU0
+#define SET_UP_CTIMER_CLOCK(x)                                       \
+	do {                                                             \
+		CLOCK_AttachClk(kFRO0_DIV1_to_CTIMER##x);				     \
+		CLOCK_SetClkDiv(kCLOCK_DivCtimer##x##Clk, 1U);               \
+	} while (0)
+#elif CONFIG_SOC_MIMXRT798S_CM33_CPU1
+#define SET_UP_CTIMER_CLOCK(x)                                       \
+	do {                                                             \
+		CLOCK_AttachClk(kFRO2_DIV1_to_CTIMER##x);					 \
+		CLOCK_SetClkDiv(kCLOCK_DivCtimer##x##Clk, 1U);               \
+	} while (0)
+#endif
+
+const clock_main_pll_config_t g_mainPllConfig_clock_init = {
+	.main_pll_src = kCLOCK_MainPllOscClk, /* OSC clock */
+	.numerator = 0,   /* Numerator of the SYSPLL0 fractional loop divider is 0 */
+	.denominator = 1, /* Denominator of the SYSPLL0 fractional loop divider is 1 */
+	.main_pll_mult = kCLOCK_MainPllMult22 /* Divide by 22 */
+};
+
+const clock_audio_pll_config_t g_audioPllConfig_clock_init = {
+	.audio_pll_src = kCLOCK_AudioPllOscClk, /* OSC clock */
+	.numerator = 5040,    /* Numerator of the Audio PLL fractional loop divider is 0 */
+	.denominator = 27000, /* Denominator of the Audio PLL fractional loop divider is 1 */
+	.audio_pll_mult = kCLOCK_AudioPllMult22, /* Divide by 22 */
+	.enableVcoOut = true};
+
+static void BOARD_InitAHBSC(void);
+#if CONFIG_DT_HAS_NXP_MCUX_EDMA_ENABLED
+static void edma_enable_all_request(uint8_t instance);
+#endif
+
+void board_early_init_hook(void)
+{
+#if CONFIG_SOC_MIMXRT798S_CM33_CPU0
+	const clock_fro_config_t froAutotrimCfg = {
+		.targetFreq = 300000000U,
+		.range = 50U,
+		.trim1DelayUs = 15U,
+		.trim2DelayUs = 15U,
+		.refDiv = 1U,
+		.enableInt = 0U,
+		.coarseTrimEn = true,
+	};
+
+	POWER_DisablePD(kPDRUNCFG_PD_LPOSC);
+
+	/* Power up OSC */
+	POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL);
+	/* Enable system OSC */
+	CLOCK_EnableSysOscClk(true, true, SYSOSC_SETTLING_US);
+	/* Sets external XTAL OSC freq */
+	CLOCK_SetXtalFreq(XTAL_SYS_CLK_HZ);
+
+	/* Make sure FRO1 is enabled. */
+	POWER_DisablePD(kPDRUNCFG_PD_FRO1);
+
+	/* Switch to FRO1 for safe configure. */
+	CLOCK_AttachClk(kFRO1_DIV1_to_COMPUTE_BASE);
+	CLOCK_AttachClk(kCOMPUTE_BASE_to_COMPUTE_MAIN);
+	CLOCK_SetClkDiv(kCLOCK_DivCmptMainClk, 1U);
+	CLOCK_AttachClk(kFRO1_DIV1_to_RAM);
+	CLOCK_SetClkDiv(kCLOCK_DivComputeRamClk, 1U);
+	CLOCK_AttachClk(kFRO1_DIV1_to_COMMON_BASE);
+	CLOCK_AttachClk(kCOMMON_BASE_to_COMMON_VDDN);
+	CLOCK_SetClkDiv(kCLOCK_DivCommonVddnClk, 1U);
+
+#if CONFIG_FLASH_MCUX_XSPI_XIP
+	/* Change to common_base clock(Sourced by FRO1). */
+	xspi_clock_safe_config();
+#endif
+
+	/* Ungate all FRO clock. */
+	POWER_DisablePD(kPDRUNCFG_GATE_FRO0);
+	/* Use close loop mode. */
+	CLOCK_EnableFroClkFreqCloseLoop(FRO0, &froAutotrimCfg, kCLOCK_FroAllOutEn);
+	/* Enable FRO0 MAX clock for all domains.*/
+	CLOCK_EnableFro0ClkForDomain(kCLOCK_AllDomainEnable);
+
+	CLOCK_InitMainPll(&g_mainPllConfig_clock_init);
+	CLOCK_InitMainPfd(kCLOCK_Pfd0, 20U); /* 475 MHz */
+	CLOCK_InitMainPfd(kCLOCK_Pfd1, 24U); /* 396 MHz */
+	CLOCK_InitMainPfd(kCLOCK_Pfd2, 18U); /* 528 MHz */
+	/* Main PLL kCLOCK_Pfd3 (528 * 18 / 19) = 500 MHz -need 2 div  -> 250 MHz*/
+	CLOCK_InitMainPfd(kCLOCK_Pfd3, 19U);
+
+	CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd0, kCLOCK_AllDomainEnable);
+	CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd1, kCLOCK_AllDomainEnable);
+	CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd2, kCLOCK_AllDomainEnable);
+	CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd3, kCLOCK_AllDomainEnable);
+
+	CLOCK_SetClkDiv(kCLOCK_DivCmptMainClk, 2U);
+	CLOCK_AttachClk(kMAIN_PLL_PFD0_to_COMPUTE_MAIN); /* Switch to PLL 237.5 MHz */
+
+	CLOCK_SetClkDiv(kCLOCK_DivMediaMainClk, 2U);
+	CLOCK_AttachClk(kMAIN_PLL_PFD0_to_MEDIA_MAIN); /* Switch to PLL 237.5 MHz */
+
+	CLOCK_SetClkDiv(kCLOCK_DivMediaVddnClk, 2U);
+	CLOCK_AttachClk(kMAIN_PLL_PFD0_to_MEDIA_VDDN); /* Switch to PLL 237.5 MHz */
+
+	CLOCK_SetClkDiv(kCLOCK_DivComputeRamClk, 2U);
+	CLOCK_AttachClk(kMAIN_PLL_PFD0_to_RAM); /* Switch to PLL 237.5 MHz */
+
+	CLOCK_SetClkDiv(kCLOCK_DivCommonVddnClk, 2U);
+	CLOCK_AttachClk(kMAIN_PLL_PFD3_to_COMMON_VDDN); /* Switch to 250MHZ */
+
+	/* Configure Audio PLL clock source. */
+	CLOCK_InitAudioPll(&g_audioPllConfig_clock_init); /* 532.48MHZ */
+	CLOCK_InitAudioPfd(kCLOCK_Pfd1, 24U);             /* 399.36MHz */
+	CLOCK_InitAudioPfd(kCLOCK_Pfd3, 26U); /* Enable Audio PLL PFD3 clock to 368.64MHZ */
+	CLOCK_EnableAudioPllPfdClkForDomain(kCLOCK_Pfd1, kCLOCK_AllDomainEnable);
+	CLOCK_EnableAudioPllPfdClkForDomain(kCLOCK_Pfd3, kCLOCK_AllDomainEnable);
+
+#if CONFIG_FLASH_MCUX_XSPI_XIP
+	/* Call function xspi_setup_clock() to set user configured clock for XSPI. */
+	xspi_setup_clock(XSPI0, 3U, 1U); /* Main PLL PDF1 DIV1. */
+#endif                                      /* CONFIG_FLASH_MCUX_XSPI_XIP */
+
+#elif CONFIG_SOC_MIMXRT798S_CM33_CPU1
+	/* Power up OSC in case it's not enabled. */
+	POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL);
+	/* Enable system OSC */
+	CLOCK_EnableSysOscClk(true, true, SYSOSC_SETTLING_US);
+	/* Sets external XTAL OSC freq */
+	CLOCK_SetXtalFreq(XTAL_SYS_CLK_HZ);
+
+	CLOCK_AttachClk(kFRO1_DIV3_to_SENSE_BASE);
+	CLOCK_SetClkDiv(kCLOCK_DivSenseMainClk, 1);
+	CLOCK_AttachClk(kSENSE_BASE_to_SENSE_MAIN);
+
+	POWER_DisablePD(kPDRUNCFG_GATE_FRO2);
+	CLOCK_EnableFroClkFreq(FRO2, 300000000U, kCLOCK_FroAllOutEn);
+
+	CLOCK_EnableFro2ClkForDomain(kCLOCK_AllDomainEnable);
+
+	CLOCK_AttachClk(kFRO2_DIV3_to_SENSE_BASE);
+	CLOCK_SetClkDiv(kCLOCK_DivSenseMainClk, 1);
+	CLOCK_AttachClk(kSENSE_BASE_to_SENSE_MAIN);
+#endif /* CONFIG_SOC_MIMXRT798S_CM33_CPU0 */
+
+	BOARD_InitAHBSC();
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(edma0), okay)
+	CLOCK_EnableClock(kCLOCK_Dma0);
+	RESET_ClearPeripheralReset(kDMA0_RST_SHIFT_RSTn);
+	edma_enable_all_request(0);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(edma1), okay)
+	CLOCK_EnableClock(kCLOCK_Dma1);
+	RESET_ClearPeripheralReset(kDMA1_RST_SHIFT_RSTn);
+	edma_enable_all_request(1);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(iocon), okay)
+	RESET_ClearPeripheralReset(kIOPCTL0_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_Iopctl0);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(iocon1), okay)
+	RESET_ClearPeripheralReset(kIOPCTL1_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_Iopctl1);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(iocon2), okay)
+	RESET_ClearPeripheralReset(kIOPCTL2_RST_SHIFT_RSTn);
+	CLOCK_EnableClock(kCLOCK_Iopctl2);
+#endif
+
+#ifdef CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0
+	CLOCK_AttachClk(kOSC_CLK_to_FCCLK0);
+	CLOCK_SetClkDiv(kCLOCK_DivFcclk0Clk, 1U);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm0), okay)
+	SET_UP_FLEXCOMM_CLOCK(0);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm1), okay)
+	SET_UP_FLEXCOMM_CLOCK(1);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm2), okay)
+	SET_UP_FLEXCOMM_CLOCK(2);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm3), okay)
+	SET_UP_FLEXCOMM_CLOCK(3);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm4), okay)
+	SET_UP_FLEXCOMM_CLOCK(4);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm5), okay)
+	SET_UP_FLEXCOMM_CLOCK(5);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm6), okay)
+	SET_UP_FLEXCOMM_CLOCK(6);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm7), okay)
+	SET_UP_FLEXCOMM_CLOCK(7);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm8), okay)
+	SET_UP_FLEXCOMM_CLOCK(8);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm9), okay)
+	SET_UP_FLEXCOMM_CLOCK(9);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm10), okay)
+	SET_UP_FLEXCOMM_CLOCK(10);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm11), okay)
+	SET_UP_FLEXCOMM_CLOCK(11);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm12), okay)
+	SET_UP_FLEXCOMM_CLOCK(12);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm13), okay)
+	SET_UP_FLEXCOMM_CLOCK(13);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi14), okay)
+	CLOCK_AttachClk(kFRO1_DIV1_to_LPSPI14);
+	CLOCK_SetClkDiv(kCLOCK_DivLpspi14Clk, 3U);
+	CLOCK_EnableClock(kCLOCK_LPSpi14);
+	RESET_ClearPeripheralReset(kLPSPI14_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c15), okay)
+	CLOCK_EnableClock(kCLOCK_LPI2c15);
+	RESET_ClearPeripheralReset(kLPI2C15_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi16), okay)
+	CLOCK_AttachClk(kFRO0_DIV1_to_LPSPI16);
+	CLOCK_SetClkDiv(kCLOCK_DivLpspi16Clk, 1U);
+	CLOCK_EnableClock(kCLOCK_LPSpi16);
+	RESET_ClearPeripheralReset(kLPSPI16_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm17), okay)
+	CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM17);
+	CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm17Clk, 4U);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm18), okay)
+	CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM18);
+	CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm18Clk, 4U);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm19), okay)
+	CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM19);
+	CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm19Clk, 4U);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm20), okay)
+	CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM20);
+	CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm20Clk, 4U);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexio), okay)
+	CLOCK_AttachClk(kFRO0_DIV1_to_FLEXIO);
+	CLOCK_SetClkDiv(kCLOCK_DivFlexioClk, 1U);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay)
+	CLOCK_EnableClock(kCLOCK_Gpio0);
+	RESET_ClearPeripheralReset(kGPIO0_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
+	CLOCK_EnableClock(kCLOCK_Gpio1);
+	RESET_ClearPeripheralReset(kGPIO1_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay)
+	CLOCK_EnableClock(kCLOCK_Gpio2);
+	RESET_ClearPeripheralReset(kGPIO2_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay)
+	CLOCK_EnableClock(kCLOCK_Gpio3);
+	RESET_ClearPeripheralReset(kGPIO3_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay)
+	CLOCK_EnableClock(kCLOCK_Gpio4);
+	RESET_ClearPeripheralReset(kGPIO4_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay)
+	CLOCK_EnableClock(kCLOCK_Gpio5);
+	RESET_ClearPeripheralReset(kGPIO5_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio6), okay)
+	CLOCK_EnableClock(kCLOCK_Gpio6);
+	RESET_ClearPeripheralReset(kGPIO6_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio7), okay)
+	CLOCK_EnableClock(kCLOCK_Gpio7);
+	RESET_ClearPeripheralReset(kGPIO7_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio8), okay)
+	CLOCK_EnableClock(kCLOCK_Gpio8);
+	RESET_ClearPeripheralReset(kGPIO8_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio9), okay)
+	CLOCK_EnableClock(kCLOCK_Gpio9);
+	RESET_ClearPeripheralReset(kGPIO9_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio10), okay)
+	CLOCK_EnableClock(kCLOCK_Gpio10);
+	RESET_ClearPeripheralReset(kGPIO10_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer0), okay)
+	SET_UP_CTIMER_CLOCK(0);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer1), okay)
+	SET_UP_CTIMER_CLOCK(1);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer2), okay)
+	SET_UP_CTIMER_CLOCK(2);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer3), okay)
+	SET_UP_CTIMER_CLOCK(3);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer4), okay)
+	SET_UP_CTIMER_CLOCK(4);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer5), okay)
+	SET_UP_CTIMER_CLOCK(5);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer6), okay)
+	SET_UP_CTIMER_CLOCK(6);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(ctimer7), okay)
+	SET_UP_CTIMER_CLOCK(7);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpadc0), okay)
+	CLOCK_AttachClk(kFRO1_DIV1_to_SENSE_MAIN);
+	CLOCK_AttachClk(kSENSE_BASE_to_ADC);
+	CLOCK_SetClkDiv(kCLOCK_DivAdcClk, 1U);
+#endif
+
+#if (DT_NODE_HAS_STATUS(DT_NODELABEL(os_timer_cpu0), okay) || \
+		DT_NODE_HAS_STATUS(DT_NODELABEL(os_timer_cpu1), okay))
+	CLOCK_AttachClk(kLPOSC_to_OSTIMER);
+	CLOCK_SetClkDiv(kCLOCK_DivOstimerClk, 1U);
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb0)) && CONFIG_UDC_NXP_EHCI
+	/* Power on COM VDDN domain for USB */
+	POWER_DisablePD(kPDRUNCFG_DSR_VDDN_COM);
+
+	/* Power on usb ram array as need, powered USB0RAM array*/
+	POWER_DisablePD(kPDRUNCFG_APD_USB0_SRAM);
+	POWER_DisablePD(kPDRUNCFG_PPD_USB0_SRAM);
+	/* Apply the config */
+	POWER_ApplyPD();
+	/* disable the read and write gate */
+	SYSCON4->USB0_MEM_CTRL |= (SYSCON4_USB0_MEM_CTRL_MEM_WIG_MASK |
+				   SYSCON4_USB0_MEM_CTRL_MEM_RIG_MASK |
+				   SYSCON4_USB0_MEM_CTRL_MEM_STDBY_MASK);
+	/* Enable the USBPHY0 CLOCK */
+	SYSCON4->USBPHY0_CLK_ACTIVE |= SYSCON4_USBPHY0_CLK_ACTIVE_IPG_CLK_ACTIVE_MASK;
+	CLOCK_AttachClk(k32KHZ_WAKE_to_USB);
+	CLOCK_AttachClk(kOSC_CLK_to_USB_24MHZ);
+	CLOCK_EnableClock(kCLOCK_Usb0);
+	CLOCK_EnableClock(kCLOCK_UsbphyRef);
+	RESET_PeripheralReset(kUSB0_RST_SHIFT_RSTn);
+	RESET_PeripheralReset(kUSBPHY0_RST_SHIFT_RSTn);
+	CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usbphy480M,
+				DT_PROP_BY_PHANDLE(DT_NODELABEL(usb0), clocks, clock_frequency));
+	CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M,
+				DT_PROP_BY_PHANDLE(DT_NODELABEL(usb0), clocks, clock_frequency));
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(wwdt0))
+	CLOCK_AttachClk(kLPOSC_to_WWDT0);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(sc_timer), okay)
+	CLOCK_AttachClk(kFRO0_DIV6_to_SCT);
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lcdif), nxp_dcnano_lcdif, okay) && \
+	CONFIG_DISPLAY
+	/* Assert LCDIF reset. */
+	RESET_SetPeripheralReset(kLCDIF_RST_SHIFT_RSTn);
+
+	/* Disable media main and LCDIF power down. */
+	POWER_DisablePD(kPDRUNCFG_SHUT_MEDIA_MAINCLK);
+	POWER_DisablePD(kPDRUNCFG_APD_LCDIF);
+	POWER_DisablePD(kPDRUNCFG_PPD_LCDIF);
+
+	/* Apply power down configuration. */
+	POWER_ApplyPD();
+
+	CLOCK_AttachClk(kMAIN_PLL_PFD2_to_LCDIF);
+	/* Note- pixel clock follows formula
+	 * (height  VSW  VFP  VBP) * (width  HSW  HFP  HBP) * frame rate.
+	 * this means the clock divider will vary depending on
+	 * the attached display.
+	 *
+	 * The root clock used here is the main PLL (PLL PFD2).
+	 */
+	CLOCK_SetClkDiv(
+		kCLOCK_DivLcdifClk,
+		(CLOCK_GetMainPfdFreq(kCLOCK_Pfd2) /
+		  DT_PROP(DT_CHILD(DT_NODELABEL(lcdif), display_timings), clock_frequency)));
+
+	CLOCK_EnableClock(kCLOCK_Lcdif);
+
+	/* Clear LCDIF reset. */
+	RESET_ClearPeripheralReset(kLCDIF_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lcdif), nxp_mipi_dbi_dcnano_lcdif, okay)
+	/* Assert LCDIF reset. */
+	RESET_SetPeripheralReset(kLCDIF_RST_SHIFT_RSTn);
+
+	/* Disable media main and LCDIF power down. */
+	POWER_DisablePD(kPDRUNCFG_SHUT_MEDIA_MAINCLK);
+	POWER_DisablePD(kPDRUNCFG_APD_LCDIF);
+	POWER_DisablePD(kPDRUNCFG_PPD_LCDIF);
+
+	/* Apply power down configuration. */
+	POWER_ApplyPD();
+
+	/* Calculate the divider for MEDIA MAIN clock source main pll pfd2. */
+	CLOCK_InitMainPfd(kCLOCK_Pfd2, (uint64_t)CLOCK_GetMainPllFreq() * 18UL /
+						DT_PROP(DT_NODELABEL(lcdif), clock_frequency));
+	CLOCK_SetClkDiv(kCLOCK_DivMediaMainClk, 1U);
+	CLOCK_AttachClk(kMAIN_PLL_PFD2_to_MEDIA_MAIN);
+
+	CLOCK_EnableClock(kCLOCK_Lcdif);
+
+	/* Clear LCDIF reset. */
+	RESET_ClearPeripheralReset(kLCDIF_RST_SHIFT_RSTn);
+#endif
+}
+
+static void GlikeyWriteEnable(GLIKEY_Type *base, uint8_t idx)
+{
+	(void)GLIKEY_SyncReset(base);
+
+	(void)GLIKEY_StartEnable(base, idx);
+	(void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP1);
+	(void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP2);
+	(void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP3);
+	(void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP_EN);
+}
+
+static void GlikeyClearConfig(GLIKEY_Type *base)
+{
+	(void)GLIKEY_SyncReset(base);
+}
+
+/* Disable the secure check for AHBSC and enable periperhals/sram access for masters */
+static void BOARD_InitAHBSC(void)
+{
+#if defined(CONFIG_SOC_MIMXRT798S_CM33_CPU0)
+	GlikeyWriteEnable(GLIKEY0, 1U);
+	AHBSC0->MISC_CTRL_DP_REG = 0x000086aa;
+	/* AHBSC0 MISC_CTRL_REG, disable Privilege & Secure checking. */
+	AHBSC0->MISC_CTRL_REG = 0x000086aa;
+
+	GlikeyWriteEnable(GLIKEY0, 7U);
+	/* Enable arbiter0 accessing SRAM */
+	AHBSC0->COMPUTE_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
+	AHBSC0->SENSE_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
+	AHBSC0->MEDIA_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
+	AHBSC0->NPU_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
+	AHBSC0->HIFI4_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF;
+#endif
+
+	GlikeyWriteEnable(GLIKEY1, 1U);
+	AHBSC3->MISC_CTRL_DP_REG = 0x000086aa;
+	/* AHBSC3 MISC_CTRL_REG, disable Privilege & Secure checking.*/
+	AHBSC3->MISC_CTRL_REG = 0x000086aa;
+
+	GlikeyWriteEnable(GLIKEY1, 9U);
+	/* Enable arbiter1 accessing SRAM */
+	AHBSC3->COMPUTE_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
+	AHBSC3->SENSE_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
+	AHBSC3->MEDIA_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
+	AHBSC3->NPU_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
+	AHBSC3->HIFI4_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
+	AHBSC3->HIFI1_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF;
+
+	GlikeyWriteEnable(GLIKEY1, 8U);
+	/* Access enable for COMPUTE domain masters to common APB peripherals.*/
+	AHBSC3->COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
+	AHBSC3->SENSE_APB_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
+	GlikeyWriteEnable(GLIKEY1, 7U);
+	AHBSC3->COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
+	AHBSC3->SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE = 0xffffffff;
+
+	GlikeyWriteEnable(GLIKEY2, 1U);
+	/*Disable secure and secure privilege checking. */
+	AHBSC4->MISC_CTRL_DP_REG = 0x000086aa;
+	AHBSC4->MISC_CTRL_REG = 0x000086aa;
+
+#if defined(CONFIG_SOC_MIMXRT798S_CM33_CPU0)
+	GlikeyClearConfig(GLIKEY0);
+#endif
+	GlikeyClearConfig(GLIKEY1);
+	GlikeyClearConfig(GLIKEY2);
+}
+
+#if CONFIG_DT_HAS_NXP_MCUX_EDMA_ENABLED
+static void edma_enable_all_request(uint8_t instance)
+{
+	uint32_t *reg;
+
+	for (uint8_t idx = 0; idx < EN_NUM; idx++) {
+		reg = EDMA_EN_REG(instance, idx);
+		*reg |= 0xFFFFFFFF;
+	}
+}
+#endif
diff --git a/boards/nxp/mimxrt700_evk/board.cmake b/boards/nxp/mimxrt700_evk/board.cmake
new file mode 100644
index 00000000000..800d65c1ead
--- /dev/null
+++ b/boards/nxp/mimxrt700_evk/board.cmake
@@ -0,0 +1,19 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if(CONFIG_SOC_MIMXRT798S_CM33_CPU0)
+  board_runner_args(jlink "--device=MIMXRT798S_M33_0" "--reset-after-load")
+  board_runner_args(linkserver  "--device=MIMXRT798S:MIMXRT700-EVK")
+  board_runner_args(linkserver  "--override=/device/memory/4=")
+  board_runner_args(linkserver  "--core=cm33_core0")
+elseif(CONFIG_SOC_MIMXRT798S_CM33_CPU1)
+  board_runner_args(jlink "--device=MIMXRT798S_M33_1")
+  board_runner_args(linkserver  "--device=MIMXRT798S:MIMXRT700-EVK")
+  board_runner_args(linkserver  "--core=cm33_core1")
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake)
diff --git a/boards/nxp/mimxrt700_evk/board.yml b/boards/nxp/mimxrt700_evk/board.yml
new file mode 100644
index 00000000000..e4aa90748f9
--- /dev/null
+++ b/boards/nxp/mimxrt700_evk/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: mimxrt700_evk
+  full_name: MIMXRT700-EVK
+  vendor: nxp
+  socs:
+  - name: mimxrt798s
diff --git a/boards/nxp/mimxrt700_evk/doc/index.rst b/boards/nxp/mimxrt700_evk/doc/index.rst
new file mode 100644
index 00000000000..a02f8a1c705
--- /dev/null
+++ b/boards/nxp/mimxrt700_evk/doc/index.rst
@@ -0,0 +1,241 @@
+.. zephyr:board:: mimxrt700_evk
+
+Overview
+********
+
+The new i.MX RT700 CPU architecture is composed of a high-performance main-compute subsystem,
+a secondary “always-on” sense-compute subsystem and specialized coprocessors.
+
+The main-compute subsystem has a primary Arm® Cortex®-M33 running at 325 MHz, with an integrated
+Cadence® Tensilica® HiFi 4 DSP for more demanding DSP and audio processing tasks.
+The sense-compute subsystem has a second Arm® Cortex®-M33 and an integrated Cadence® Tensilica®
+HiFi 1 DSP. This removes the need for an external sensor hub, reducing system design complexity,
+footprint and BOM costs.
+
+The HiFi4 is a high performance DSP core based upon a Very Long Instruction Word (VLIW) architecture,
+which is capable of processing up to eight 32x16 MACs per instruction cycle. It can be used for offloading
+high-performance numerical tasks such as audio and image processing and supports both fixed-point and
+floating-point operations.
+
+The i.MX RT700 also features NXP’s eIQ Neutron NPU, enabled with the eIQ machine learning software
+development environment.
+
+Hardware
+********
+
+- Main Compute Subsystem:
+   - Arm Cortex-M33 up to 325 MHz
+   - HiFi 4 DSP up to 325 MHz
+   - eIQ Neutron NPU up to 325 MHz
+- Sense Compute Subsystem:
+   - Arm Cortex-M33 up to 250 MHz
+   - HiFi 1 DSP up to 250 MHz
+- 7.5 MB on-chip SRAM
+- Three xSPI interfaces for off-chip memory expansion, supporting up to 16b wide external memories up to 250 MHz DDR
+- eUSB support with integrated PHY
+- Two SD/eMMC memory card interfaces—one supporting eMMC 5.0 with HS400/DDR operation
+- USB high-speed host/device controller with on-chip PHY
+- A digital microphone interface supporting up to 8 channels
+- Serial peripherals (UART/I²C/I3C/SPI/HSPI/SAI)
+- 2.5D GPU with vector graphics acceleration and frame buffer compression
+- EZH-V using RISC-V core with additional SIMD/DSP instructions
+- Full openVG 1.1 support
+- Up to 720p@60FPS from on-chip SRAM
+- LCD Interface + MIPI DSI
+- Integrated JPEG and PNG support
+- CSI 8/10/16-bit parallel (via FlexIO)
+
+For more information about the MIMXRT798 SoC and MIMXRT700-EVK board, see
+these references:
+
+- `i.MX RT700 Website`_
+
+Supported Features
+==================
+
+NXP considers the MIMXRT700-EVK as a superset board for the i.MX RT7xx
+family of MCUs. This board is a focus for NXP's Full Platform Support for
+Zephyr, to better enable the entire RT7xx family. NXP prioritizes enabling
+this board with new support for Zephyr features.
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+The MIMXRT798 SoC has IOCON registers, which can be used to configure the
+functionality of a pin.
+
++---------+-----------------+----------------------------+
+| Name    | Function        | Usage                      |
++=========+=================+============================+
+| PIO0_6  | I2C             | I2C SDA                    |
++---------+-----------------+----------------------------+
+| PIO0_7  | I2C             | I2C SCL                    |
++---------+-----------------+----------------------------+
+| PIO0_31 | UART0           | UART RX                    |
++---------+-----------------+----------------------------+
+| PIO1_0  | UART0           | UART TX                    |
++---------+-----------------+----------------------------+
+| PIO0_18 | GPIO            | GREEN LED                  |
++---------+-----------------+----------------------------+
+| PIO0_9  | GPIO            | SW5                        |
++---------+-----------------+----------------------------+
+| PIO8_14 | UART19          | UART TX                    |
++---------+-----------------+----------------------------+
+| PIO8_15 | UART19          | UART RX                    |
++---------+-----------------+----------------------------+
+| PIO3_0  | SPI             | SPI MOSI                   |
++---------+-----------------+----------------------------+
+| PIO3_1  | SPI             | SPI SCK                    |
++---------+-----------------+----------------------------+
+| PIO3_2  | SPI             | SPI MISO                   |
++---------+-----------------+----------------------------+
+| PIO3_3  | SPI             | SPI SSEL                   |
++---------+-----------------+----------------------------+
+
+System Clock
+============
+
+The MIMXRT700 EVK is configured to use the Systick
+as a source for the system clock.
+
+HiFi1 DSP Core
+==================
+
+One can build a Zephyr application for the i.MX RT700 HiFi 1  DSP core by targeting the HiFi 1
+SOC. Xtensa toolchain supporting RT700 DSP cores is included in Zephyr SDK.
+
+To build the hello_world sample for the i.MX RT700 HiFi 1 DSP core:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: samples/hello_world
+   :board: mimxrt700_evk/mimxrt798s/hifi1
+   :goals: build
+
+HiFi4 DSP Core
+==================
+
+One can build a Zephyr application for the i.MX RT700 HiFi 4  DSP core by targeting the HiFi 4
+SOC. Xtensa toolchain supporting RT700 DSP cores is included in Zephyr SDK.
+
+To build the hello_world sample for the i.MX RT700 HiFi 4 DSP core:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: samples/hello_world
+   :board: mimxrt700_evk/mimxrt798s/hifi4
+   :goals: build
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Configuring a Debug Probe
+=========================
+
+A debug probe is used for both flashing and debugging the board. This board is
+configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe.
+
+.. tabs::
+    .. group-tab:: LinkServer
+
+
+        1. Install the :ref:`linkserver-debug-host-tools` and make sure they are in your search path.
+        2. To put the board in ``DFU mode`` to program the firmware, short jumper J20.
+        3. To update the debug firmware, please follow the instructions on `MIMXRT700-EVK Debug Firmware`
+
+    .. group-tab:: JLink External
+
+
+        1. Install the :ref:`jlink-debug-host-tools` and make sure they are in your search path.
+
+        2. To disconnect the SWD signals from onboard debug circuit, **short** jumpers JP18.
+
+        3. Connect the J-Link probe to J18 20-pin header.
+
+        See :ref:`jlink-external-debug-probe` for more information.
+
+Configuring a Console
+=====================
+
+Connect a USB cable from your PC to J54, and use the serial terminal of your choice
+(minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Flashing
+========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the
+:ref:`jlink-debug-host-tools` as default.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: mimxrt700_evk/mimxrt798s/cm33_cpu0
+   :goals: flash
+
+Open a serial terminal, reset the board (press the RESET button), and you should
+see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS v3.7.0 ***
+   Hello World! mimxrt700_evk/mimxrt798s/cm33_cpu0
+
+Debugging
+=========
+
+Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the
+:ref:`jlink-debug-host-tools` as default.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: mimxrt700_evk/mimxrt798s/cm33_cpu0
+   :goals: debug
+
+Open a serial terminal, step through the application in your debugger, and you
+should see the following message in the terminal:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS v3.7.0 ***
+   Hello World! mimxrt700_evk/mimxrt798s/cm33_cpu0
+
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
+.. _i.MX RT700 Website:
+   https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt700-crossover-mcu-with-arm-cortex-m33-npu-dsp-and-gpu-cores:i.MX-RT700
+
+.. _MIMXRT700-EVK Debug Firmware:
+   https://www.nxp.com/docs/en/application-note/AN13206.pdf
+
+Display Support
+***************
+
+The mimxrt700_evk board supports following in-tree display module(s). Setup for
+each module is described below:
+
+NXP G1120B0MIPI MIPI Display
+============================
+
+The :ref:`g1120b0mipi` connects to the board's MIPI connector J52
+directly, but some modifications are required (see
+:zephyr_file:`boards/shields/g1120b0mipi/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay`
+for a list). The display sample can be built for this module like so:
+
+.. zephyr-app-commands::
+   :board: mimxrt700_evk
+   :shield: g1120b0mipi
+   :zephyr-app: samples/drivers/display
+   :goals: build
+   :compact:
diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi b/boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi
new file mode 100644
index 00000000000..80054f5b477
--- /dev/null
+++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2024-2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/nxp_imx/rt/MIMXRT798SGFOA-pinctrl.h>
+
+&pinctrl {
+	pinmux_flexcomm0_lpuart: pinmux_flexcomm0_lpuart {
+		group0 {
+			pinmux = <LP_FLEXCOMM0_P0_PIO0_31>;
+			input-enable;
+			slew-rate = "normal";
+			drive-strength = "normal";
+		};
+		group1 {
+			pinmux = <LP_FLEXCOMM0_P1_PIO1_0>;
+			slew-rate = "normal";
+			drive-strength = "normal";
+		};
+	};
+
+	pinmux_flexcomm8_i2c: pinmux_flexcomm8_i2c {
+		group0 {
+			pinmux = <LP_FLEXCOMM8_P0_PIO0_6>,
+				<LP_FLEXCOMM8_P1_PIO0_7>;
+			bias-pull-up;
+			input-enable;
+			slew-rate = "normal";
+			drive-strength = "high";
+			drive-open-drain;
+		};
+	};
+
+	pinmux_flexcomm19_lpuart: pinmux_flexcomm19_lpuart {
+		group0 {
+			pinmux = <LP_FLEXCOMM19_P0_PIO8_14>;
+			input-enable;
+			slew-rate = "normal";
+			drive-strength = "normal";
+		};
+		group1 {
+			pinmux = <LP_FLEXCOMM19_P1_PIO8_15>;
+			slew-rate = "normal";
+			drive-strength = "normal";
+		};
+	};
+
+	pinmux_lpspi14: pinmux_lpspi14 {
+		group0 {
+			pinmux = <LPSPI14_SOUT_PIO3_0>,
+				<LPSPI14_SCK_PIO3_1>,
+				<LPSPI14_SIN_PIO3_2>,
+				<LPSPI14_PCS0_PIO3_3>;
+			slew-rate = "normal";
+			drive-strength = "normal";
+			input-enable;
+		};
+	};
+
+	flexio_pwm_default: flexio_pwm_default {
+		group0 {
+			pinmux = <FLEXIO_IO7_PIO2_7>;
+			drive-strength = "normal";
+			slew-rate = "slow";
+		};
+	};
+
+	pinmux_lpadc0: pinmux_lpadc0 {
+		group0 {
+			pinmux = <ADC0_CH0_PIO10_0>,
+				<ADC0_CH1_PIO10_2>;
+			slew-rate = "normal";
+			drive-strength = "normal";
+			nxp,analog-mode;
+		};
+	};
+
+	pinmux_sctimer: pinmux_sctimer {
+		group0 {
+			pinmux = <SCT0_IN0_PIO0_0>;
+			slew-rate = "normal";
+			drive-strength = "normal";
+			input-enable;
+		};
+	};
+};
diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts
new file mode 100644
index 00000000000..df8e0d77bb6
--- /dev/null
+++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts
@@ -0,0 +1,218 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_rt7xx_cm33_cpu0.dtsi>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include "mimxrt700_evk-pinctrl.dtsi"
+
+/ {
+	model = "NXP MIMXRT700-EVK board";
+	compatible = "nxp,mimxrt798s";
+
+	aliases {
+		led0 = &green_led;
+		led1 = &blue_led;
+		sw0 = &user_button_1;
+		sw1 = &user_button_2;
+		watchdog0 = &wwdt0;
+		pwm-0 = &sc_timer;
+	};
+
+	chosen {
+		zephyr,flash-controller = &mx25um51345g;
+		zephyr,flash = &mx25um51345g;
+		zephyr,sram = &sram0;
+		zephyr,console = &flexcomm0_lpuart0;
+		zephyr,shell-uart = &flexcomm0_lpuart0;
+		zephyr,display = &lcdif;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		green_led: led_0 {
+			gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+			label = "User LED_GREEN";
+		};
+		blue_led: led_1 {
+			gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>;
+			label = "User LED_BLUE";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button_1: button_0 {
+			label = "User SW5";
+			gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+		user_button_2: button_1 {
+			label = "User SW7";
+			gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+
+	/*
+	 * This node describes the GPIO pins of the MIPI FPC interface,
+	 * J50 on the EVK. This interface is standard to several
+	 * NXP EVKs, and is used with several MIPI displays
+	 * (available as zephyr shields)
+	 */
+	nxp_mipi_connector: mipi-connector {
+		compatible = "gpio-nexus";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map =	<0  0 &gpio1 14 0>,	/* Pin 1, LEDK */
+					<21 0 &gpio3 4 0>,	/* Pin 21, RESET */
+					<22 0 &gpio3 5 0>,	/* Pin 22, LPTE */
+					<26 0 &gpio0 6 0>,	/* Pin 26, CTP_I2C SDA */
+					<27 0 &gpio0 7 0>,	/* Pin 27, CTP_I2C SCL */
+					<28 0 &gpio3 8 0>,	/* Pin 28, CTP_RST */
+					<29 0 &gpio1 13 0>,	/* Pin 29, CTP_INT */
+					<32 0 &gpio1 10 0>,	/* Pin 32, PWR_EN */
+					<34 0 &gpio1 14 0>;	/* Pin 34, BL_PWM */
+	};
+
+	en_mipi_display: enable-mipi-display {
+		compatible = "regulator-fixed";
+		regulator-name = "en_mipi_display";
+		enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+		regulator-boot-on;
+	};
+};
+
+&ctimer0 {
+	status = "okay";
+};
+
+&edma0 {
+	status = "okay";
+};
+
+/*
+ * RT700-EVK board cm33_cpu0 uses OS timer as the kernel timer
+ * In case we need to switch to SYSTICK timer, then
+ * replace &os_timer with &systick
+ */
+&os_timer_cpu0 {
+	status = "okay";
+	wakeup-source;
+};
+
+&flexcomm0{
+	status = "okay";
+};
+
+&flexcomm0_lpuart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&pinmux_flexcomm0_lpuart>;
+	pinctrl-names = "default";
+};
+
+&lpspi14 {
+	status = "okay";
+	/* DMA channels 0 and 1, muxed to LPSPI14 RX and TX */
+	dmas = <&edma0 0 73>, <&edma0 1 74>;
+	dma-names = "rx", "tx";
+	pinctrl-0 = <&pinmux_lpspi14>;
+	pinctrl-names = "default";
+};
+
+&flexcomm8{
+	status = "okay";
+};
+
+&flexcomm8_lpi2c8 {
+	pinctrl-0 = <&pinmux_flexcomm8_i2c>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+nxp_mipi_i2c: &flexcomm8_lpi2c8 {};
+
+zephyr_mipi_dsi: &mipi_dsi {};
+
+zephyr_lcdif: &lcdif {};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
+&green_led {
+	status = "okay";
+};
+
+&lpadc0 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_lpadc0>;
+	pinctrl-names = "default";
+};
+
+&blue_led {
+	status = "okay";
+};
+
+&mrt0_channel0 {
+	status = "okay";
+};
+
+&sc_timer {
+	status = "okay";
+	pinctrl-0 = <&pinmux_sctimer>;
+	pinctrl-names = "default";
+};
+
+&xspi0 {
+	status = "okay";
+
+	mx25um51345g: mx25um51345g@0 {
+		compatible = "nxp,xspi-mx25um51345g";
+		/* MX25UM51245G is 64MB, 512MBit flash part */
+		size = <DT_SIZE_M(64 * 8)>;
+		reg = <0>;
+		spi-max-frequency = <200000000>;
+		status = "okay";
+		jedec-id = [c2 81 3a];
+		erase-block-size = <4096>;
+		write-block-size = <2>;
+	};
+};
+
+zephyr_udc0: &usb0 {
+	status = "okay";
+	phy-handle = <&usbphy>;
+};
+
+&usbphy {
+	status = "okay";
+	tx-d-cal = <7>;
+	tx-cal-45-dp-ohms = <6>;
+	tx-cal-45-dm-ohms = <6>;
+};
+
+&wwdt0 {
+	status = "okay";
+};
+
+p3t1755dp_ard_i2c_interface: &flexcomm8_lpi2c8 {};
diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.yaml b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.yaml
new file mode 100644
index 00000000000..10b049b8277
--- /dev/null
+++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.yaml
@@ -0,0 +1,25 @@
+#
+# Copyright 2024-2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mimxrt700_evk/mimxrt798s/cm33_cpu0
+name: NXP MIMXRT700-EVK (CM33_CPU0)
+type: mcu
+arch: arm
+ram: 512
+flash: 65536
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - counter
+  - gpio
+  - i2c
+  - uart
+  - spi
+  - adc
+  - usb_device
+  - watchdog
+vendor: nxp
diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0_defconfig b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0_defconfig
new file mode 100644
index 00000000000..2e0bfcbd83e
--- /dev/null
+++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0_defconfig
@@ -0,0 +1,17 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_GPIO=y
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable TrustZone-M
+CONFIG_TRUSTED_EXECUTION_SECURE=y
diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts
new file mode 100644
index 00000000000..92ecdc41aaf
--- /dev/null
+++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts
@@ -0,0 +1,82 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_rt7xx_cm33_cpu1.dtsi>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include "mimxrt700_evk-pinctrl.dtsi"
+
+/ {
+	model = "NXP MIMXRT700-EVK board";
+	compatible = "nxp,mimxrt798s";
+
+	aliases {
+		led0 = &red_led;
+		sw0 = &user_button_1;
+	};
+
+	chosen {
+		zephyr,flash = &sram_code;
+		zephyr,sram = &sram0;
+		zephyr,console = &flexcomm19_lpuart19;
+		zephyr,shell-uart = &flexcomm19_lpuart19;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		red_led: led_0 {
+			status = "okay";
+			gpios = <&gpio8 6 GPIO_ACTIVE_HIGH>;
+			label = "User LED_RED";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button_1: button_0 {
+			label = "User SW6";
+			gpios = <&gpio8 5 (GPIO_ACTIVE_LOW)>;
+			zephyr,code = <INPUT_KEY_0>;
+			status = "okay";
+		};
+	};
+};
+
+&ctimer5 {
+	status = "okay";
+};
+
+&lpadc0 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_lpadc0>;
+	pinctrl-names = "default";
+};
+
+/*
+ * RT700-EVK board cm33_cpu1 uses OS timer as the kernel timer
+ * In case we need to switch to SYSTICK timer, then
+ * replace &os_timer with &systick
+ */
+&os_timer_cpu1 {
+	status = "okay";
+	wakeup-source;
+};
+
+&flexcomm19{
+	status = "okay";
+};
+
+&flexcomm19_lpuart19 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&pinmux_flexcomm19_lpuart>;
+	pinctrl-names = "default";
+};
+
+&gpio8 {
+	status = "okay";
+};
diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.yaml b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.yaml
new file mode 100644
index 00000000000..38c45ae9027
--- /dev/null
+++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.yaml
@@ -0,0 +1,21 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mimxrt700_evk/mimxrt798s/cm33_cpu1
+name: NXP MIMXRT700-EVK (CM33_CPU1)
+type: mcu
+arch: arm
+ram: 256
+flash: 512
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - counter
+  - gpio
+  - uart
+  - adc
+vendor: nxp
diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1_defconfig b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1_defconfig
new file mode 100644
index 00000000000..29cdb5d3cfd
--- /dev/null
+++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1_defconfig
@@ -0,0 +1,18 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_GPIO=y
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable TrustZone-M
+CONFIG_TRUSTED_EXECUTION_SECURE=y
+CONFIG_NXP_IMXRT_BOOT_HEADER=n
diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi1.dts b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi1.dts
new file mode 100644
index 00000000000..6f1c5380db5
--- /dev/null
+++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi1.dts
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_imxrt700_hifi1.dtsi>
+
+/ {
+	model = "NXP MIMXRT700-EVK HiFi1 DSP";
+	compatible = "nxp,mimxrt798s";
+
+	chosen {
+		zephyr,sram = &dtcm;
+	};
+};
diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi1.yaml b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi1.yaml
new file mode 100644
index 00000000000..7c3bee257ef
--- /dev/null
+++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi1.yaml
@@ -0,0 +1,18 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mimxrt700_evk/mimxrt798s/hifi1
+name: NXP MIMXRT700-EVK HiFi1
+type: mcu
+arch: xtensa
+toolchain:
+  - xcc
+  - xt-clang
+  - zephyr
+testing:
+  only_tags:
+    - kernel
+vendor: nxp
diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.dts b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.dts
new file mode 100644
index 00000000000..392a4c27a1d
--- /dev/null
+++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.dts
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nxp/nxp_imxrt700_hifi4.dtsi>
+
+/ {
+	model = "NXP MIMXRT700-EVK HiFi4 DSP";
+	compatible = "nxp,mimxrt798s";
+
+	chosen {
+		zephyr,sram = &dtcm;
+	};
+};
diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.yaml b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.yaml
new file mode 100644
index 00000000000..925a17ac466
--- /dev/null
+++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_hifi4.yaml
@@ -0,0 +1,18 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: mimxrt700_evk/mimxrt798s/hifi4
+name: NXP MIMXRT700-EVK HiFi4
+type: mcu
+arch: xtensa
+toolchain:
+  - xcc
+  - xt-clang
+  - zephyr
+testing:
+  only_tags:
+    - kernel
+vendor: nxp
diff --git a/boards/nxp/mr_canhubk3/doc/index.rst b/boards/nxp/mr_canhubk3/doc/index.rst
index fcb813b882d..47dfdcc20b9 100644
--- a/boards/nxp/mr_canhubk3/doc/index.rst
+++ b/boards/nxp/mr_canhubk3/doc/index.rst
@@ -33,33 +33,7 @@ More information about the hardware and design resources can be found at
 Supported Features
 ==================
 
-The ``mr_canhubk3`` board configuration supports the following hardware features:
-
-============  ==========  ================================
-Interface     Controller  Driver/Component
-============  ==========  ================================
-SIUL2         on-chip     | pinctrl
-                          | gpio
-                          | external interrupt controller
-WKPU          on-chip     interrupt controller
-LPUART        on-chip     serial
-QSPI          on-chip     flash
-FLEXCAN       on-chip     can
-LPI2C         on-chip     i2c
-ADC SAR       on-chip     adc
-LPSPI         on-chip     spi
-WDT           FS26 SBC    watchdog
-SWT           on-chip     watchdog
-EMAC          on-chip     ethernet
-                          mdio
-eMIOS         on-chip     pwm
-EDMA          on-chip     dma
-FLEXIO PWM    on-chip     pwm
-STM           on-chip     counter
-============  ==========  ================================
-
-The default configuration can be found in the Kconfig file
-:zephyr_file:`boards/nxp/mr_canhubk3/mr_canhubk3_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -275,15 +249,18 @@ The 100Base-T1 signals are available in connector ``P9`` and can be converted to
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``mr_canhubk3`` board can be built in the usual way as
 documented in :ref:`build_an_application`.
 
 This board configuration supports `Lauterbach TRACE32`_, `SEGGER J-Link`_ and `pyOCD`_
-West runners for flashing and debugging applications. Follow the steps described
-in :ref:`lauterbach-trace32-debug-host-tools`, :ref:`jlink-debug-host-tools` and
-:ref:`pyocd-debug-host-tools`,
-to setup the flash and debug host tools for these runners, respectively. The
-default runner is J-Link.
+West runners for flashing and debugging. Follow the steps described in
+:ref:`lauterbach-trace32-debug-host-tools`, :ref:`jlink-debug-host-tools` and
+:ref:`pyocd-debug-host-tools`, to set up the required host tools.
+The default runner is J-Link.
+
+If using TRACE32, ensure you have version >= 2024.09 installed.
 
 Flashing
 ========
@@ -326,6 +303,9 @@ Run the ``west debug`` command to start a GDB session using SEGGER J-Link.
 Alternatively, run ``west debug -r trace32`` or ``west debug -r pyocd``
 to launch the Lauterbach TRACE32 or pyOCD software debugging interface respectively.
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 References
 **********
 
diff --git a/boards/nxp/mr_canhubk3/mr_canhubk3.dts b/boards/nxp/mr_canhubk3/mr_canhubk3.dts
index 6759aaf49fb..c8df4985fbf 100644
--- a/boards/nxp/mr_canhubk3/mr_canhubk3.dts
+++ b/boards/nxp/mr_canhubk3/mr_canhubk3.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright 2023 NXP
+ * Copyright 2023-2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -344,6 +344,8 @@
 		readoc = "1-4-4";
 		writeoc = "1-4-4";
 		has-32k-erase;
+		max-program-buffer-size = <256>;
+		write-block-size = <1>;
 		status = "okay";
 
 		partitions {
@@ -499,7 +501,6 @@
 		emios0_bus_a {
 			mode = "MCB_UP_COUNTER";
 			prescaler = <16>;
-			period = <1000>;
 			status = "okay";
 		};
 	};
@@ -513,63 +514,43 @@
 		pwm_0 {
 			channel = <0>;
 			pwm-mode = "OPWFMB";
-			period = <65535>;
-			duty-cycle = <0>;
 			prescaler = <8>;
-			polarity = "ACTIVE_HIGH";
 		};
 
 		pwm_1 {
 			channel = <1>;
 			pwm-mode = "OPWFMB";
-			period = <65535>;
-			duty-cycle = <0>;
 			prescaler = <8>;
-			polarity = "ACTIVE_HIGH";
 		};
 
 		pwm_2 {
 			channel = <2>;
 			pwm-mode = "OPWFMB";
-			period = <65535>;
-			duty-cycle = <0>;
 			prescaler = <8>;
-			polarity = "ACTIVE_HIGH";
 		};
 
 		pwm_3 {
 			channel = <3>;
 			pwm-mode = "OPWFMB";
-			period = <65535>;
-			duty-cycle = <0>;
 			prescaler = <8>;
-			polarity = "ACTIVE_HIGH";
 		};
 
 		pwm_4 {
 			channel = <4>;
 			pwm-mode = "OPWFMB";
-			period = <65535>;
-			duty-cycle = <0>;
 			prescaler = <8>;
-			polarity = "ACTIVE_HIGH";
 		};
 
 		pwm_5 {
 			channel = <5>;
 			pwm-mode = "OPWFMB";
-			period = <65535>;
-			duty-cycle = <0>;
 			prescaler = <8>;
-			polarity = "ACTIVE_HIGH";
 		};
 
 		rgb_red {
 			channel = <19>;
 			master-bus = <&emios0_bus_a>;
-			duty-cycle = <0>;
 			pwm-mode = "OPWMB";
-			polarity = "ACTIVE_LOW";
 		};
 	};
 };
@@ -586,14 +567,12 @@
 		emios1_bus_a {
 			prescaler = <16>;
 			mode = "MCB_UP_COUNTER";
-			period = <1000>;
 			status = "okay";
 		};
 
 		emios1_bus_f {
 			prescaler = <16>;
 			mode = "MCB_UP_COUNTER";
-			period = <1000>;
 			status = "okay";
 		};
 	};
@@ -606,17 +585,13 @@
 		rgb_green {
 			channel = <10>;
 			master-bus = <&emios1_bus_a>;
-			duty-cycle = <0>;
 			pwm-mode = "OPWMB";
-			polarity = "ACTIVE_LOW";
 		};
 
 		rgb_blue {
 			channel = <5>;
 			master-bus = <&emios1_bus_f>;
-			duty-cycle = <0>;
 			pwm-mode = "OPWMB";
-			polarity = "ACTIVE_LOW";
 		};
 	};
 };
diff --git a/boards/nxp/mr_canhubk3/support/startup.cmm b/boards/nxp/mr_canhubk3/support/startup.cmm
index 2a7194937a1..736b9db6816 100644
--- a/boards/nxp/mr_canhubk3/support/startup.cmm
+++ b/boards/nxp/mr_canhubk3/support/startup.cmm
@@ -51,7 +51,7 @@ TrOnchip.Set BUSERR OFF
 SYStem.Up
 
 ; Init SRAM
-DO ~~/demo/arm/hardware/s32k3/scripts/init_sram.cmm
+DO ~~/demo/arm/hardware/s32k3/misc/init_sram.cmm
 
 ; Only declares flash, does not execute flash programming
 DO ~~/demo/arm/flash/s32k3.cmm PREPAREONLY
@@ -97,7 +97,7 @@ IF ("&loadTo"=="flash")
 ELSE
 (
   ; Init ITCM
-  DO ~~/demo/arm/hardware/s32k3/scripts/init_itcm.cmm
+  DO ~~/demo/arm/hardware/s32k3/misc/init_itcm.cmm
 
   Data.LOAD.Elf &elfFile
 )
diff --git a/boards/nxp/rd_rw612_bga/CMakeLists.txt b/boards/nxp/rd_rw612_bga/CMakeLists.txt
index 1317c39df31..e7ec1b7f361 100644
--- a/boards/nxp/rd_rw612_bga/CMakeLists.txt
+++ b/boards/nxp/rd_rw612_bga/CMakeLists.txt
@@ -1,9 +1,12 @@
 #
-# Copyright 2022-2023 NXP
+# Copyright 2022-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
 
+zephyr_library()
+zephyr_library_sources(init.c)
+
 if(CONFIG_NXP_RW6XX_BOOT_HEADER)
   if(NOT DEFINED CONFIG_BOARD_RD_RW612_BGA)
     message(WARNING "It appears you are using the board definition for "
@@ -12,6 +15,11 @@ if(CONFIG_NXP_RW6XX_BOOT_HEADER)
   endif()
   zephyr_compile_definitions(BOOT_HEADER_ENABLE=1)
   zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024)
-  zephyr_library()
   zephyr_library_sources(MX25U51245GZ4I00_FCB.c)
 endif()
+
+if (CONFIG_DT_HAS_NXP_ENET_MAC_ENABLED AND CONFIG_XTAL32K)
+	message(FATAL_ERROR "Ethernet and external 32K clock source are "
+		"mutually exclusive on RD_RW612_BGA due to shared PCB nets "
+		"between the ethernet PHY and the external oscillator")
+endif()
diff --git a/boards/nxp/rd_rw612_bga/Kconfig b/boards/nxp/rd_rw612_bga/Kconfig
new file mode 100644
index 00000000000..89e6c3a3f49
--- /dev/null
+++ b/boards/nxp/rd_rw612_bga/Kconfig
@@ -0,0 +1,5 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RD_RW612_BGA
+	select BOARD_EARLY_INIT_HOOK
diff --git a/boards/nxp/rd_rw612_bga/Kconfig.defconfig b/boards/nxp/rd_rw612_bga/Kconfig.defconfig
index 6f644448c7f..e78a9fea422 100644
--- a/boards/nxp/rd_rw612_bga/Kconfig.defconfig
+++ b/boards/nxp/rd_rw612_bga/Kconfig.defconfig
@@ -1,6 +1,6 @@
 # RD_RW612_BGA board
 
-# Copyright 2022-2024 NXP
+# Copyright 2022-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 if BOARD_RD_RW612_BGA
@@ -30,10 +30,6 @@ config LV_Z_FLUSH_THREAD
 
 endif # LVGL
 
-# Enable interrupt support when using FT5336 driver
-config INPUT_FT5336_INTERRUPT
-	default y if INPUT
-
 if DT_HAS_NXP_ENET_MAC_ENABLED && NETWORKING
 
 config NET_L2_ETHERNET
@@ -41,4 +37,11 @@ config NET_L2_ETHERNET
 
 endif # DT_HAS_NXP_ENET_MAC_ENABLED && NETWORKING
 
+if COUNTER_MCUX_LPC_RTC_1HZ
+
+config XTAL32K
+	default y
+
+endif # COUNTER_MCUX_LPC_RTC_1HZ
+
 endif # BOARD_RD_RW612_BGA
diff --git a/boards/nxp/rd_rw612_bga/doc/index.rst b/boards/nxp/rd_rw612_bga/doc/index.rst
index 340dcccbd01..a755399e37e 100644
--- a/boards/nxp/rd_rw612_bga/doc/index.rst
+++ b/boards/nxp/rd_rw612_bga/doc/index.rst
@@ -23,65 +23,11 @@ Hardware
 Supported Features
 ==================
 
-+-----------+------------+-----------------------------------+
-| Interface | Controller | Driver/Component                  |
-+===========+============+===================================+
-| NVIC      | on-chip    | nested vector interrupt controller|
-+-----------+------------+-----------------------------------+
-| SYSTICK   | on-chip    | systick                           |
-+-----------+------------+-----------------------------------+
-| MCI_IOMUX | on-chip    | pinmux                            |
-+-----------+------------+-----------------------------------+
-| GPIO      | on-chip    | gpio                              |
-+-----------+------------+-----------------------------------+
-| USART     | on-chip    | serial                            |
-+-----------+------------+-----------------------------------+
-| DMA       | on-chip    | dma                               |
-+-----------+------------+-----------------------------------+
-| SPI       | on-chip    | spi                               |
-+-----------+------------+-----------------------------------+
-| I2C       | on-chip    | i2c                               |
-+-----------+------------+-----------------------------------+
-| FLEXSPI   | on-chip    | flash/memc                        |
-+-----------+------------+-----------------------------------+
-| TRNG      | on-chip    | entropy                           |
-+-----------+------------+-----------------------------------+
-| DMIC      | on-chip    | dmic                              |
-+-----------+------------+-----------------------------------+
-| LCDIC     | on-chip    | mipi-dbi                          |
-+-----------+------------+-----------------------------------+
-| WWDT      | on-chip    | watchdog                          |
-+-----------+------------+-----------------------------------+
-| USBOTG    | on-chip    | usb                               |
-+-----------+------------+-----------------------------------+
-| CTIMER    | on-chip    | counter                           |
-+-----------+------------+-----------------------------------+
-| SCTIMER   | on-chip    | pwm                               |
-+-----------+------------+-----------------------------------+
-| MRT       | on-chip    | counter                           |
-+-----------+------------+-----------------------------------+
-| OS_TIMER  | on-chip    | os timer                          |
-+-----------+------------+-----------------------------------+
-| PM        | on-chip    | power management; uses SoC Power  |
-|           |            | Modes 1 and 2                     |
-+-----------+------------+-----------------------------------+
-| BLE       | on-chip    | Bluetooth                         |
-+-----------+------------+-----------------------------------+
-| ADC       | on-chip    | adc                               |
-+-----------+------------+-----------------------------------+
-| DAC       | on-chip    | dac                               |
-+-----------+------------+-----------------------------------+
-| ENET      | on-chip    | ethernet                          |
-+-----------+------------+-----------------------------------+
-| Wi-Fi     | on-chip    | Wi-Fi                             |
-+-----------+------------+-----------------------------------+
-
-The default configuration can be found in the defconfig file:
-
-   :zephyr_file:`boards/nxp/rd_rw612_bga/rd_rw612_bga_defconfig/`
-
-Other hardware features are not currently supported
+.. zephyr:board-supported-hw::
 
+.. note::
+
+   Power modes 1, 2 and 3 are supported when using System Power Management.
 
 Display Support
 ***************
@@ -148,6 +94,8 @@ achieved by running the following command:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -257,6 +205,9 @@ Remove resistors:
 
 Then, build for the board target ``rd_rw612_bga//ethernet``.
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 Resources
 *********
 
diff --git a/boards/nxp/rd_rw612_bga/dts/goworld_16880_lcm.overlay b/boards/nxp/rd_rw612_bga/dts/goworld_16880_lcm.overlay
index 658778d373b..9ee80d03528 100644
--- a/boards/nxp/rd_rw612_bga/dts/goworld_16880_lcm.overlay
+++ b/boards/nxp/rd_rw612_bga/dts/goworld_16880_lcm.overlay
@@ -89,6 +89,6 @@
 		compatible = "focaltech,ft5336";
 		reg = <0x38>;
 		reset-gpios = <&hsgpio0 15 GPIO_ACTIVE_LOW>;
-		int-gpios = <&hsgpio0 11 GPIO_ACTIVE_HIGH>;
+		int-gpios = <&hsgpio0 11 GPIO_ACTIVE_LOW>;
 	};
 };
diff --git a/boards/nxp/rd_rw612_bga/init.c b/boards/nxp/rd_rw612_bga/init.c
new file mode 100644
index 00000000000..d3b8459495d
--- /dev/null
+++ b/boards/nxp/rd_rw612_bga/init.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright 2022, 2024-25 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/pm/pm.h>
+#include <fsl_power.h>
+#include <fsl_common.h>
+
+static void rdrw61x_power_init_config(void)
+{
+	power_init_config_t initCfg = {
+		/* VCORE AVDD18 supplied from iBuck on RD board. */
+		.iBuck = true,
+		/* CAU_SOC_SLP_REF_CLK is needed for LPOSC. */
+		.gateCauRefClk = false,
+	};
+
+	POWER_InitPowerConfig(&initCfg);
+}
+
+#if CONFIG_PM
+static void rdrw61x_pm_state_exit(enum pm_state state)
+{
+	switch (state) {
+	case PM_STATE_STANDBY:
+		rdrw61x_power_init_config();
+		break;
+	default:
+		break;
+	}
+}
+#endif
+
+void board_early_init_hook(void)
+{
+	rdrw61x_power_init_config();
+
+#if CONFIG_PM
+	static struct pm_notifier rdrw61x_pm_notifier = {
+		.state_exit = rdrw61x_pm_state_exit,
+	};
+
+	pm_notifier_register(&rdrw61x_pm_notifier);
+#endif
+
+#ifdef CONFIG_I2S_TEST_SEPARATE_DEVICES
+	/*
+	 * Eventually this code should not be here
+	 * but should be configured by some SYSCTL node
+	 */
+
+	/* Set shared signal set 0 SCK, WS from Transmit I2S - Flexcomm1 */
+	SYSCTL1->SHAREDCTRLSET[0] = SYSCTL1_SHAREDCTRLSET_SHAREDSCKSEL(1) |
+				SYSCTL1_SHAREDCTRLSET_SHAREDWSSEL(1);
+
+	/* Select Data in from Transmit I2S - Flexcomm 1 */
+	SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_SHAREDDATASEL(1);
+	/* Enable Transmit I2S - Flexcomm 1 for Shared Data Out */
+	SYSCTL1->SHAREDCTRLSET[0] |= SYSCTL1_SHAREDCTRLSET_FC1DATAOUTEN(1);
+
+	/* Set Receive I2S - Flexcomm 0 SCK, WS from shared signal set 0 */
+	SYSCTL1->FCCTRLSEL[0] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |
+				SYSCTL1_FCCTRLSEL_WSINSEL(1);
+
+	/* Set Transmit I2S - Flexcomm 1 SCK, WS from shared signal set 0 */
+	SYSCTL1->FCCTRLSEL[1] = SYSCTL1_FCCTRLSEL_SCKINSEL(1) |
+				SYSCTL1_FCCTRLSEL_WSINSEL(1);
+
+	/* Select Receive I2S - Flexcomm 0 Data in from shared signal set 0 */
+	SYSCTL1->FCCTRLSEL[0] |= SYSCTL1_FCCTRLSEL_DATAINSEL(1);
+	/* Select Transmit I2S - Flexcomm 1 Data out to shared signal set 0 */
+	SYSCTL1->FCCTRLSEL[1] |= SYSCTL1_FCCTRLSEL_DATAOUTSEL(1);
+#endif /* CONFIG_I2S_TEST_SEPARATE_DEVICES */
+}
diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi
index a82b286091a..c98853fa499 100644
--- a/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi
+++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022-2024 NXP
+ * Copyright 2022-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -119,4 +119,11 @@
 			slew-rate = "normal";
 		};
 	};
+
+	pinmux_flexcomm1_i2s: pinmux_flexcomm1_i2s {
+		group0 {
+			pinmux = <IO_MUX_FC1_I2S>;
+			slew-rate = "normal";
+		};
+	};
 };
diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi
index 8d8bd71cd61..4c050c63d91 100644
--- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi
+++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022-2024 NXP
+ * Copyright 2022-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -270,6 +270,12 @@ nxp_8080_touch_panel_i2c: &arduino_i2c {
 	pinctrl-names = "default";
 };
 
+/* RTC is the wakeup source for PM modes 3,4 */
+&rtc_highres {
+	status = "okay";
+	wakeup-source;
+};
+
 &pmu {
 	reset-causes-en = <PMU_RESET_CM33_LOCKUP>,
 			  <PMU_RESET_ITRC>,
@@ -288,6 +294,7 @@ nxp_8080_touch_panel_i2c: &arduino_i2c {
 &os_timer {
 	status = "okay";
 	wakeup-source;
+	deep-sleep-counter = <&rtc_highres>;
 };
 
 &systick {
diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml
index 1971325463b..7e3402f7fc8 100644
--- a/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml
+++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga.yaml
@@ -1,5 +1,5 @@
 #
-# Copyright 2022-2024 NXP
+# Copyright 2022-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 960
 flash: 65536
 supported:
@@ -25,6 +24,7 @@ supported:
   - gpio
   - hwinfo
   - i2c
+  - i2s
   - pwm
   - spi
   - usb_device
diff --git a/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet.yaml b/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet.yaml
index 19d26ea8162..dbdff161607 100644
--- a/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet.yaml
+++ b/boards/nxp/rd_rw612_bga/rd_rw612_bga_rw612_ethernet.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 960
 flash: 65536
 supported:
diff --git a/boards/nxp/rddrone_fmuk66/doc/index.rst b/boards/nxp/rddrone_fmuk66/doc/index.rst
index f83f310974b..2e8c4c3a62b 100644
--- a/boards/nxp/rddrone_fmuk66/doc/index.rst
+++ b/boards/nxp/rddrone_fmuk66/doc/index.rst
@@ -36,51 +36,7 @@ For more information about the K64F SoC and FRDM-K64F board:
 Supported Features
 ==================
 
-The rddrone-fmuk66 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | dac                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | soc flash                           |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma                                 |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/rddrone_fmuk66/rddrone_fmuk66_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 System Clock
 ============
@@ -105,6 +61,8 @@ Only USB device function is supported in Zephyr at the moment.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -170,6 +128,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS v2.7.0 *****
    Hello World! rddrone-fmuk66
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _RDDRONE-FMUK66 Website:
 
 https://www.nxp.com/design/designs/px4-robotic-drone-vehicle-flight-management-unit-vmu-fmu-rddrone-fmuk66:RDDRONE-FMUK66
diff --git a/boards/nxp/s32z2xxdc2/doc/index.rst b/boards/nxp/s32z2xxdc2/doc/index.rst
index 9cb0972bf8f..6383dc8ad32 100644
--- a/boards/nxp/s32z2xxdc2/doc/index.rst
+++ b/boards/nxp/s32z2xxdc2/doc/index.rst
@@ -21,47 +21,7 @@ Information about the hardware and design resources can be found at
 Supported Features
 ==================
 
-The boards support the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| Arm GIC   | on-chip    | interrupt_controller                |
-+-----------+------------+-------------------------------------+
-| Arm Timer | on-chip    | timer                               |
-+-----------+------------+-------------------------------------+
-| LINFlexD  | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| MRU       | on-chip    | mbox                                |
-+-----------+------------+-------------------------------------+
-| NETC      | on-chip    | ethernet                            |
-|           |            |                                     |
-|           |            | mdio                                |
-+-----------+------------+-------------------------------------+
-| SIUL2     | on-chip    | pinctrl                             |
-|           |            |                                     |
-|           |            | gpio                                |
-|           |            |                                     |
-|           |            | external interrupt controller       |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| SWT       | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| CANEXCEL  | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
-| FLEXCAN   | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
-| SAR_ADC   | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| LPI2C     | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| EDMA      | on-chip    | dma                                 |
-+-----------+------------+-------------------------------------+
-| DSPI      | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -170,9 +130,17 @@ EDMA
 The EDMA modules feature four EDMA3 instances: Instance 0 with 32 channels,
 and instances 1, 4, and 5, each with 16 channels.
 
+External Flash
+==============
+
+The on-board S26HS512T 512M-bit HyperFlash memory is connected to the QSPI controller
+port A1. This board configuration selects it as the default flash controller.
+
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``s32z2xxdc2`` boards can be built in the usual way as
 documented in :ref:`build_an_application`.
 
@@ -232,13 +200,11 @@ the terminal:
 
    Hello World! s32z2xxdc2
 
-To debug with Lauterbach TRACE32 softare run instead:
+To debug with Lauterbach TRACE32 software run instead:
 
-.. zephyr-app-commands::
-   :zephyr-app: samples/hello_world
-   :board: s32z2xxdc2/s32z270/rtu0
-   :goals: build debug -r trace32
-   :compact:
+.. code-block:: console
+
+   west debug -r trace32
 
 Flashing
 ========
@@ -251,7 +217,8 @@ SRAM and run.
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
    :board: s32z2xxdc2/s32z270/rtu0
-   :goals: build flash -r trace32
+   :goals: build flash
+   :flash-args: -r trace32
    :compact:
 
 .. note::
@@ -263,11 +230,9 @@ SRAM and run.
 To imitate a similar behavior using NXP S32 Debug Probe runner, you can run the
 ``debug`` command with GDB in batch mode:
 
-.. zephyr-app-commands::
-   :zephyr-app: samples/hello_world
-   :board: s32z2xxdc2/s32z270/rtu0
-   :goals: build debug --tool-opt='--batch'
-   :compact:
+.. code-block:: console
+
+   west debug --tool-opt='--batch'
 
 RTU and Core Configuration
 ==========================
@@ -324,11 +289,14 @@ line:
 
 .. code-block:: console
 
-   west debug --startup-args elfFile=<elf_path> rtu=<rtu_id> core=<core_id> lockstep=<yes/no>
+   west debug -r trace32 --startup-args elfFile=<elf_path> rtu=<rtu_id> core=<core_id> lockstep=<yes/no>
 
 Where ``<elf_path>`` is the path to the Zephyr application ELF in the output
 directory.
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 References
 **********
 
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi
index 65f04794ce3..87befae0db2 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270.dtsi
@@ -5,6 +5,7 @@
  */
 
 #include "s32z2xxdc2_s32z270_pinctrl.dtsi"
+#include <zephyr/dt-bindings/qspi/nxp-s32-qspi.h>
 
 &swt0 {
 	status = "okay";
@@ -58,3 +59,69 @@
 &sar_adc1 {
 	vref-mv = <1800>;
 };
+
+&qspi0 {
+	pinctrl-0 = <&qspi0_default>;
+	pinctrl-names = "default";
+	data-rate = "DDR";
+	column-space = <3>;
+	word-addressable;
+	hold-time-2x;
+	a-dll-freq-enable;
+	a-dll-ref-counter = <2>;
+	a-dll-resolution = <2>;
+	a-dll-coarse-delay = <2>;
+	a-dll-fine-delay = <2>;
+	a-dll-mode = "AUTO UPDATE";
+	a-rx-clock-source = "EXTERNAL DQS";
+	ahb-buffers-masters = <0 1 2 3>;
+	ahb-buffers-sizes = <256 256 256 256>;
+	ahb-buffers-all-masters;
+	status = "okay";
+
+	sfp_mdad {
+		compatible = "nxp,s32-qspi-sfp-mdad";
+
+		mdad_0: mdad_0 {
+			domain-id = <0>;
+			secure-attribute = <NXP_S32_QSPI_SECURE>;
+		};
+	};
+
+	sfp_frad {
+		compatible = "nxp,s32-qspi-sfp-frad";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		frad_0: frad@0 {
+			reg = <0x0 DT_SIZE_M(512)>;
+			master-domain-acp-policy = <NXP_S32_QSPI_SECURE>;
+		};
+	};
+
+	s26hs512t: s26hs512t@0 {
+		compatible = "nxp,s32-qspi-hyperflash";
+		reg = <0>;
+		jedec-id = [00 34 00 7b 00 1a 00 0f 00 90];
+		device-id-word-addr = <0x800>;
+		size = <DT_SIZE_M(512)>;
+		write-block-size = <2>;
+		read-latency-cycles = <16>;
+		max-program-buffer-size = <256>;
+		vcc-mv = <1800>;
+		drive-strength-ohm = <27>;
+		ppw-sectors-addr-mapping = "LOW";
+		status = "okay";
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			storage_partition: partition@0 {
+				label = "storage";
+				reg = <0x0 0x10000>;
+			};
+		};
+	};
+};
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi
index 05b92b08931..7433ba00e40 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_pinctrl.dtsi
@@ -127,4 +127,25 @@
 			drive-open-drain;
 		};
 	};
+
+	qspi0_default: qspi0_default {
+		group1 {
+			pinmux = <PI4_QSPI_0_DATA_A_O0>, <PH14_QSPI_0_DATA_A_O1>,
+				 <PI8_QSPI_0_DATA_A_O2>, <PI1_QSPI_0_DATA_A_O3>,
+				 <PI5_QSPI_0_DATA_A_O4>, <PH15_QSPI_0_DATA_A_O5>,
+				 <PI7_QSPI_0_DATA_A_O6>, <PI0_QSPI_0_DATA_A_O7>,
+				 <PI6_QSPI_0_DQS_A_O>;
+			output-enable;
+			input-enable;
+		};
+		group2 {
+			pinmux = <PH13_QSPI_0_CS_A0>, <PI9_QSPI_0_CS_A1>,
+				 <PI2_QSPI_0_CK_A_B>, <PI3_QSPI_0_CK_A>;
+			output-enable;
+		};
+		group3 {
+			pinmux = <PH12_QSPI_0_INTA_B>;
+			input-enable;
+		};
+	};
 };
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts
index da6b9645614..e38e8b51792 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.dts
@@ -16,6 +16,7 @@
 		zephyr,sram = &dram0;
 		zephyr,flash = &cram0;
 		zephyr,canbus = &canxl0;
+		zephyr,flash-controller = &s26hs512t;
 	};
 
 	aliases {
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml
index 070c33e6bfd..60b258ad5a1 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml
@@ -19,4 +19,5 @@ supported:
   - adc
   - i2c
   - dma
+  - pwm
 vendor: nxp
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml
index 9d692144a76..c35cc47699b 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml
@@ -19,4 +19,5 @@ supported:
   - adc
   - i2c
   - dma
+  - pwm
 vendor: nxp
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts
index 286fd8d094c..f8792f880f3 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.dts
@@ -16,6 +16,7 @@
 		zephyr,sram = &dram1;
 		zephyr,flash = &cram1;
 		zephyr,canbus = &flexcan0;
+		zephyr,flash-controller = &s26hs512t;
 	};
 
 	aliases {
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml
index 3de95effa80..3d4f2062cc9 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml
@@ -19,4 +19,5 @@ supported:
   - adc
   - i2c
   - dma
+  - pwm
 vendor: nxp
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml
index ef45138807e..334d75319ca 100644
--- a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml
+++ b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml
@@ -19,4 +19,5 @@ supported:
   - adc
   - i2c
   - dma
+  - pwm
 vendor: nxp
diff --git a/boards/nxp/twr_ke18f/doc/index.rst b/boards/nxp/twr_ke18f/doc/index.rst
index 5bdf3dcf51e..87c412cad28 100644
--- a/boards/nxp/twr_ke18f/doc/index.rst
+++ b/boards/nxp/twr_ke18f/doc/index.rst
@@ -37,52 +37,7 @@ these NXP reference documents:
 Supported Features
 ==================
 
-The twr_ke18f board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | soc flash                           |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| I2C(M)    | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SENSOR    | off-chip   | fxos8700 polling;                   |
-|           |            | trigger supported with H/W mods     |
-|           |            | explained below;                    |
-+-----------+------------+-------------------------------------+
-| SPI(M)    | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
-| WDT       | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | dac                                 |
-+-----------+------------+-------------------------------------+
-| ACMP      | on-chip    | sensor                              |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/nxp/twr_ke18f/twr_ke18f_defconfig`.
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 System Clock
 ============
@@ -124,6 +79,8 @@ Finally, a trigger option must be enabled in Kconfig (either
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -217,6 +174,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx *****
    Hello World! twr_ke18f
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _TWR-KE18F Website:
    https://www.nxp.com/TWR-KE18F
 
diff --git a/boards/nxp/twr_ke18f/twr_ke18f.yaml b/boards/nxp/twr_ke18f/twr_ke18f.yaml
index 2ee4b9bef15..33737e551ad 100644
--- a/boards/nxp/twr_ke18f/twr_ke18f.yaml
+++ b/boards/nxp/twr_ke18f/twr_ke18f.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
 flash: 512
 supported:
diff --git a/boards/nxp/twr_kv58f220m/doc/index.rst b/boards/nxp/twr_kv58f220m/doc/index.rst
index 69b5add3505..7c8b9e66865 100644
--- a/boards/nxp/twr_kv58f220m/doc/index.rst
+++ b/boards/nxp/twr_kv58f220m/doc/index.rst
@@ -34,39 +34,7 @@ these NXP reference documents:
 Supported Features
 ==================
 
-The twr_kv58f220m board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | soc flash                           |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SENSOR    | off-chip   | fxos8700 polling;                   |
-|           |            | fxos8700 trigger                    |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/nxp/twr_kv58f220m/twr_kv58f220m_defconfig`.
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 System Clock
 ============
@@ -95,6 +63,8 @@ the jumpers ``J2`` and ``J9``. A trigger option also must be enabled in Kconfig
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -172,6 +142,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS v1.14.0-xxx-gxxxxxxxxxxxx *****
    Hello World! twr_kv58f220m
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _TWR-KV58F220M Website:
    https://www.nxp.com/TWR-KV58F220M
 
diff --git a/boards/nxp/twr_kv58f220m/twr_kv58f220m.yaml b/boards/nxp/twr_kv58f220m/twr_kv58f220m.yaml
index 453ce7d004c..fc0c8b521d7 100644
--- a/boards/nxp/twr_kv58f220m/twr_kv58f220m.yaml
+++ b/boards/nxp/twr_kv58f220m/twr_kv58f220m.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 1024
 supported:
diff --git a/boards/nxp/ucans32k1sic/doc/index.rst b/boards/nxp/ucans32k1sic/doc/index.rst
index 8468d46669b..dec3549ba58 100644
--- a/boards/nxp/ucans32k1sic/doc/index.rst
+++ b/boards/nxp/ucans32k1sic/doc/index.rst
@@ -31,26 +31,7 @@ More information about the hardware and design resources can be found at
 Supported Features
 ==================
 
-The ``ucans32k1sic`` board configuration supports the following hardware features:
-
-============  ==========  ================================
-Interface     Controller  Driver/Component
-============  ==========  ================================
-SYSMPU        on-chip     mpu
-PORT          on-chip     pinctrl
-GPIO          on-chip     gpio
-LPUART        on-chip     serial
-LPI2C         on-chip     i2c
-LPSPI         on-chip     spi
-FTM           on-chip     pwm
-FlexCAN       on-chip     can
-Watchdog      on-chip     watchdog
-RTC           on-chip     counter
-ADC           on-chip     adc
-============  ==========  ================================
-
-The default configuration can be found in the Kconfig file
-:zephyr_file:`boards/nxp/ucans32k1sic/ucans32k1sic_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -124,6 +105,8 @@ The Arm Cortex-M4F core is configured to run at 80 MHz (RUN mode).
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``ucans32k1sic`` board can be built in the usual way as
 documented in :ref:`build_an_application`.
 
@@ -173,6 +156,9 @@ Run the ``west debug`` command to start a GDB session using SEGGER J-Link.
 Alternatively, run ``west debug -r trace32`` to launch the Lauterbach TRACE32
 software debugging interface.
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 References
 **********
 
diff --git a/boards/nxp/usb_kw24d512/doc/index.rst b/boards/nxp/usb_kw24d512/doc/index.rst
index 4706d94cc0d..b08d14da8e4 100644
--- a/boards/nxp/usb_kw24d512/doc/index.rst
+++ b/boards/nxp/usb_kw24d512/doc/index.rst
@@ -33,42 +33,7 @@ For more information about the KW2xD SiP and USB-KW24D512 board:
 Supported Features
 ==================
 
-The USB-KW24D512 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | soc flash                           |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| RNGA      | on-chip    | entropy;                            |
-|           |            | random                              |
-+-----------+------------+-------------------------------------+
-| FTFL      | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/usb_kw24d512/usb_kw24d512_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -129,6 +94,8 @@ can only be used in device mode.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -208,6 +175,9 @@ you should see the following message in the terminal:
    ***** Booting Zephyr OS v1.14.0-rc1 *****
    Hello World! usb_kw24d512
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _USB-KW24D512 Website:
    https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/kinetis-cortex-m-mcus/w-serieswireless-conn.m0-plus-m4/ieee-802.15.4-packet-sniffer-usb-dongle-form-factor:USB-KW24D512
 
diff --git a/boards/nxp/usb_kw24d512/usb_kw24d512.yaml b/boards/nxp/usb_kw24d512/usb_kw24d512.yaml
index 1252d6418fc..4320277c684 100644
--- a/boards/nxp/usb_kw24d512/usb_kw24d512.yaml
+++ b/boards/nxp/usb_kw24d512/usb_kw24d512.yaml
@@ -7,7 +7,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - flash
   - usb_device
diff --git a/boards/nxp/vmu_rt1170/CMakeLists.txt b/boards/nxp/vmu_rt1170/CMakeLists.txt
index 2a12ecb3611..dc909c81c81 100644
--- a/boards/nxp/vmu_rt1170/CMakeLists.txt
+++ b/boards/nxp/vmu_rt1170/CMakeLists.txt
@@ -7,7 +7,7 @@
 if(CONFIG_NXP_IMXRT_BOOT_HEADER)
   zephyr_library()
   set(RT1170_BOARD_DIR
-    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/evkmimxrt1170")
+    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/boards/evkmimxrt1170")
   if(CONFIG_BOOT_FLEXSPI_NOR)
     # Include flash configuration block for RT1170 EVK from NXP's HAL.
     # This configuration block may need modification if another flash chip is
diff --git a/boards/nxp/vmu_rt1170/Kconfig.defconfig b/boards/nxp/vmu_rt1170/Kconfig.defconfig
index 7c62ad7ecde..35cd885fe66 100644
--- a/boards/nxp/vmu_rt1170/Kconfig.defconfig
+++ b/boards/nxp/vmu_rt1170/Kconfig.defconfig
@@ -17,7 +17,7 @@ if NETWORKING
 config NET_L2_ETHERNET
 	default y if CPU_CORTEX_M7 # No cache memory support is required for driver
 
-config ETH_MCUX_RMII_EXT_CLK
+config ETH_NXP_ENET_RMII_EXT_CLK
 	default y
 
 endif # NETWORKING
diff --git a/boards/nxp/vmu_rt1170/doc/index.rst b/boards/nxp/vmu_rt1170/doc/index.rst
index 4b5d72f9ba9..30d627b6f81 100644
--- a/boards/nxp/vmu_rt1170/doc/index.rst
+++ b/boards/nxp/vmu_rt1170/doc/index.rst
@@ -69,60 +69,9 @@ Supported Features
 ==================
 
 VMU-RT1170 is a "Vehicle Management Unit" based on the general i.MX RT1170
-family of processors. The VMU RT1170 board configuration supports the
-following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | flexcan                             |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | flexpwm, qtmr                       |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma                                 |
-+-----------+------------+-------------------------------------+
-| GPT       | on-chip    | gpt                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| ENET      | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| SAI       | on-chip    | i2s                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB Device                          |
-+-----------+------------+-------------------------------------+
-| HWINFO    | on-chip    | Unique device serial number         |
-+-----------+------------+-------------------------------------+
-| DISPLAY   | on-chip    | display                             |
-+-----------+------------+-------------------------------------+
-| ACMP      | on-chip    | sensor                              |
-+-----------+------------+-------------------------------------+
-| CAAM RNG  | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| FLEXSPI   | on-chip    | flash programming                   |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/nxp/vmu_rt1170/vmu_rt1170_mimxrt1176_cm7_defconfig`
-
-Other hardware features are not currently supported by the port.
+family of processors.
+
+.. zephyr:board-supported-hw::
 
 Connections and I/Os
 ====================
@@ -469,6 +418,8 @@ The MIMXRT1170 SoC has 12 UARTs.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
@@ -532,6 +483,9 @@ should see the following message in the terminal:
    ***** Booting Zephyr OS v3.4.0-xxxx-xxxxxxxxxxxxx *****
    Hello World! vmu_rt1170
 
+.. include:: ../../common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _VMU RT1170 Schematics:
    https://github.com/CogniPilot/NXP-VMU_RT117x-HW
 
diff --git a/boards/nxp/vmu_rt1170/vmu_rt1170.yaml b/boards/nxp/vmu_rt1170/vmu_rt1170.yaml
index 0ad33d74855..ffa04d5773d 100644
--- a/boards/nxp/vmu_rt1170/vmu_rt1170.yaml
+++ b/boards/nxp/vmu_rt1170/vmu_rt1170.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 256
 flash: 65536
 supported:
diff --git a/boards/oct/index.rst b/boards/oct/index.rst
new file mode 100644
index 00000000000..6fe0a5434eb
--- /dev/null
+++ b/boards/oct/index.rst
@@ -0,0 +1,10 @@
+.. _boards-octavo:
+
+Octavo
+######
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*
diff --git a/boards/oct/osd32mp1_brk/Kconfig.defconfig b/boards/oct/osd32mp1_brk/Kconfig.defconfig
new file mode 100644
index 00000000000..7ca8f045d0a
--- /dev/null
+++ b/boards/oct/osd32mp1_brk/Kconfig.defconfig
@@ -0,0 +1,13 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_OSD32MP1_BRK
+
+config SPI_STM32_INTERRUPT
+	default y
+	depends on SPI
+
+config CLOCK_STM32_HSE_CLOCK
+	default 24000000
+
+endif # BOARD_OSD32MP1_BRK
diff --git a/boards/oct/osd32mp1_brk/Kconfig.osd32mp1_brk b/boards/oct/osd32mp1_brk/Kconfig.osd32mp1_brk
new file mode 100644
index 00000000000..3aeb8d038ad
--- /dev/null
+++ b/boards/oct/osd32mp1_brk/Kconfig.osd32mp1_brk
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_OSD32MP1_BRK
+	select SOC_OSD32MP15X
diff --git a/boards/oct/osd32mp1_brk/board.cmake b/boards/oct/osd32mp1_brk/board.cmake
new file mode 100644
index 00000000000..4ff51e763b6
--- /dev/null
+++ b/boards/oct/osd32mp1_brk/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+
+board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd.cfg")
diff --git a/boards/oct/osd32mp1_brk/board.yml b/boards/oct/osd32mp1_brk/board.yml
new file mode 100644
index 00000000000..b553a86737e
--- /dev/null
+++ b/boards/oct/osd32mp1_brk/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: osd32mp1_brk
+  full_name: OSD32MP1-BRK
+  vendor: oct
+  socs:
+    - name: osd32mp15x
diff --git a/boards/oct/osd32mp1_brk/doc/img/osd32mp1_brk.webp b/boards/oct/osd32mp1_brk/doc/img/osd32mp1_brk.webp
new file mode 100644
index 00000000000..3cbd534c79b
Binary files /dev/null and b/boards/oct/osd32mp1_brk/doc/img/osd32mp1_brk.webp differ
diff --git a/boards/oct/osd32mp1_brk/doc/osd32mp1_brk.rst b/boards/oct/osd32mp1_brk/doc/osd32mp1_brk.rst
new file mode 100644
index 00000000000..f20a21d1740
--- /dev/null
+++ b/boards/oct/osd32mp1_brk/doc/osd32mp1_brk.rst
@@ -0,0 +1,310 @@
+.. zephyr:board:: osd32mp1_brk
+
+Overview
+********
+
+The OSD32MP1-BRK development board by Octavo Systems integrates the OSD32MP15x
+System-in-Package (SiP), which contains a multicore STM32MP157F microprocessor.
+Zephyr OS is ported to run on the Cortex®-M4 core of the STM32MP157F.
+
+- Common features:
+
+  - OSD32MP15x SiP:
+
+    - STM32MP15x microprocessor:
+
+      - Dual-core Arm® Cortex®-A7 up to 800 MHz, 32 bits
+      - Cortex®-M4 up to 209 MHz, 32 bits
+      - Embedded SRAM (448 Kbytes) for Cortex®-M4.
+
+    - 512MB DDR3 memory
+    - STPMIC1A Power Management
+    - Integrated 4kB EEPROM
+    - MEMS oscillator
+    - Over 100 passive components
+
+  - Small form factor:
+
+    - Dimensions: 75 mm x 46 mm (3 in x 1.8 in)
+    - Breadboard-compatible with access to 106 I/Os via two 2x30 100-mil headers
+
+  - Built-in features:
+
+    - μUSB
+    - ST-Link header
+    - UART
+    - μSD card slot
+    - 32 kHz crystal
+    - User LEDs and reset button
+    - 4 Layer Design
+    - No Back Side Components
+
+For a detailed list of features, visit the `OSD32MP1-BRK product page`_.
+
+Hardware
+********
+
+The OSD32MP15x SiP in integration with the STM32MP17 SoC provides the following hardware capabilities:
+
+- Core:
+
+  - 32-bit dual-core Arm® Cortex®-A7
+
+    - L1 32-Kbyte I / 32-Kbyte D for each core
+    - 256-Kbyte unified level 2 cache
+    - Arm® NEON™ and Arm® TrustZone®
+
+  - 32-bit Arm® Cortex®-M4 with FPU/MPU
+
+    - Up to 209 MHz (Up to 703 CoreMark®)
+
+- Memories:
+
+  - 512 MB DDR3L memory (on SiP)
+  - 708 Kbytes of internal SRAM:
+
+    - 256 KB AXI SYSRAM
+    - 384 KB AHB SRAM
+    - 64 KB AHB SRAM in backup domain
+
+  - Dual mode Quad-SPI memory interface
+  - Flexible external memory controller with up to 16-bit data bus
+  - Integrated 4 KB EEPROM (on SiP)
+
+- Security/safety:
+
+  - Secure boot, TrustZone® peripherals with Cortex®-M4 resource isolation
+
+- Clock management:
+
+  - Internal oscillators:
+
+    - 64 MHz HSI oscillator
+    - 4 MHz CSI oscillator
+    - 32 kHz LSI oscillator
+
+  - External oscillators:
+
+    - 8-48 MHz HSE oscillator
+    - 32.768 kHz LSE oscillator
+
+  - 6 × PLLs with fractional mode
+  - MEMS oscillator (on SiP)
+
+- General-purpose input/outputs:
+
+  - Up to 176 I/O ports with interrupt capability
+  - 106 I/Os routed to expansion headers (on board)
+
+- Interconnect matrix
+
+- 3 DMA controllers
+
+- Communication peripherals:
+
+  - 6 × I2C FM+ (1 Mbit/s, SMBus/PMBus)
+  - 4 × UART + 4 × USART (12.5 Mbit/s, ISO7816 interface, LIN, IrDA, SPI slave)
+  - 6 × SPI (50 Mbit/s, including 3 with full duplex I2S audio class accuracy)
+  - 4 × SAI (stereo audio: I2S, PDM, SPDIF Tx)
+  - SPDIF Rx with 4 inputs
+  - HDMI-CEC interface
+  - MDIO Slave interface
+  - 3 × SDMMC up to 8-bit (SD / e•MMC™ / SDIO)
+  - 2 × CAN controllers supporting CAN FD protocol, TTCAN capability
+  - 2 × USB 2.0 high-speed Host+ 1 × USB 2.0 full-speed OTG simultaneously
+  - 10/100M or Gigabit Ethernet GMAC (IEEE 1588v2 hardware, MII/RMII/GMII/RGMI)
+  - 8- to 14-bit camera interface up to 140 Mbyte/s
+  - 6 analog peripherals
+  - 2 × ADCs with 16-bit max. resolution
+  - 1 × temperature sensor
+  - 2 × 12-bit D/A converters (1 MHz)
+  - 1 × digital filters for sigma delta modulator (DFSDM) with 8 channels/6
+    filters
+  - Internal or external ADC/DAC reference VREF+
+
+- Graphics:
+
+  - 3D GPU: Vivante® - OpenGL® ES 2.0
+  - LCD-TFT controller, up to 24-bit // RGB888, up to WXGA (1366 × 768) @60 fps
+  - MIPI® DSI 2 data lanes up to 1 GHz each
+
+- Timers:
+
+  - 2 × 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature
+    (incremental) encoder input
+  - 2 × 16-bit advanced motor control timers
+  - 10 × 16-bit general-purpose timers (including 2 basic timers without PWM)
+  - 5 × 16-bit low-power timers
+  - RTC with sub-second accuracy and hardware calendar
+  - 2 × 4 Cortex®-A7 system timers (secure, non-secure, virtual, hypervisor)
+  - 1 × SysTick Cortex®-M4 timer
+
+- Hardware acceleration:
+
+  - AES 128, 192, 256, TDES
+  - HASH (MD5, SHA-1, SHA224, SHA256), HMAC
+  - 2 × true random number generator (3 oscillators each)
+  - 2 × CRC calculation unit
+
+- Debug mode:
+
+  - Arm® CoreSight™ trace and debug: SWD and JTAG interfaces
+  - 8-Kbyte embedded trace buffer
+  - 3072-bit fuses including 96-bit unique ID, up to 1184-bit available for user
+
+More information about the hardware can be found here:
+
+- `STM32MP157F on www.st.com`_
+- `OSD32MP15x SiP documentation`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+OSD32MP1-BRK Board schematic is available here:
+`OSD32MP1-BRK schematics`_.
+
+OSD32MP1-BRK Board pin mapping is available here:
+`OSD32MP1-BRK default pin mapping`_.
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+- UART7 TX/RX: PA15/PB3 (default console)
+- I2C5 SCL/SDA: PA11/PA12
+- SPI4 SCK/MISO/MOSI: PE12/PE13/PE14
+
+System Clock
+------------
+
+The Cortex®-M4 Core is configured to run at a 209 MHz clock speed.
+This value must match the configured mlhclk_ck frequency.
+
+Serial Port
+-----------
+
+The Zephyr console output is assigned by default to the RAM console to be dumped
+by the Linux Remoteproc Framework on Cortex®-A7 core. To enable the USART2 console, modify
+the board's devicetree and the osd32mp1_brk_defconfig board file (or prj.conf project files)
+Default USART settings are 115200 8N1.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+The STM32MP157F doesn't have QSPI flash for Cortex®-M4 and it needs to be
+started by the Cortex®-A7 core. The Cortex®-A7 core is responsible for loading the
+Cortex®-M4 binary application into the RAM, and getting Cortex®-M4 out of reset.
+Cortex®-A7 can perform these steps at bootloader level or after the Linux
+system has booted.
+
+Cortex®-M4 can use up to 2 different RAMs. The program pointer starts at
+the 0x00000000 (RETRAM) address, and the vector table should be loaded at this address.
+The following table provides memory mappings for Cortex®-A7 and Cortex®-M4:
+
++------------+-----------------------+------------------------+----------------+
+| Region     | Cortex®-A7            | Cortex®-M4             | Size           |
++============+=======================+========================+================+
+| RETRAM     | 0x38000000-0x3800FFFF | 0x00000000-0x0000FFFF  | 64KB           |
++------------+-----------------------+------------------------+----------------+
+| MCUSRAM    | 0x10000000-0x1005FFFF | 0x10000000-0x1005FFFF  | 384KB          |
++------------+-----------------------+------------------------+----------------+
+| DDR        | 0xC0000000-0x20000000 |                        | 512MB          |
++------------+-----------------------+------------------------+----------------+
+
+Refer to following instructions to boot Zephyr on the Cortex®-M4 core:
+
+1. Download and install the Octavo OpenSTLinux distribution:
+   `OSD32MP1 OpenSTLinux`_.
+
+   (You can find more details about this process here: `OSD32MP1-BRK Getting Started`_)
+
+2. Build the Zephyr application:
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: osd32mp1_brk
+      :goals: build
+
+3. Transfer the built firmware to the board via USB RNDIS:
+
+   .. code-block:: console
+
+      scp build/zephyr/zephyr.elf root@192.168.7.1:/lib/firmware
+
+4. Boot Zephyr on the Cortex®-M4 core:
+
+   .. code-block:: console
+
+      ssh root@192.168.7.1
+      echo stop > /sys/class/remoteproc/remoteproc0/state
+      echo -n zephyr.elf > /sys/class/remoteproc/remoteproc0/firmware
+      echo start > /sys/class/remoteproc/remoteproc0/state
+      cat /sys/kernel/debug/remoteproc/remoteproc0/trace0
+
+   The console output should display:
+
+   .. code-block::
+
+      *** Booting Zephyr OS build v4.0.0 ***
+      Hello World! osd32mp1_brk/osd32mp15x
+
+
+Refer to `OSD32MP1-BRK Getting Started`_ and `stm32mp157 boot Cortex-M4 firmware`_ wiki page for more
+detailed instructions.
+
+Debugging
+=========
+
+You can debug an application using OpenOCD and GDB. The solution proposed below
+is based on attaching to preloaded firmware, which is available only for a Linux
+environment. The firmware must first be loaded by the Cortex®-A7. The developer
+then attaches the debugger to the running Zephyr using OpenOCD.
+
+The principle is to attach to the firmware already loaded by Linux.
+
+- Build the sample:
+
+  .. zephyr-app-commands::
+     :zephyr-app: samples/hello_world
+     :board: osd32mp1_brk
+     :goals: build
+
+- Copy the firmware on the target filesystem, load it and start it (`stm32mp157 boot Cortex-M4 firmware`_).
+- Attach to the target:
+
+  .. code-block:: console
+
+    west attach
+
+.. _OSD32MP1-BRK product page:
+   https://octavosystems.com/octavo_products/osd32mp1-brk/
+
+.. _OSD32MP1-BRK documentation:
+   https://octavosystems.com/docs/osd32mp15x-datasheet/
+
+.. _STM32MP157F on www.st.com:
+   https://www.st.com/en/microcontrollers-microprocessors/stm32mp157f.html
+
+.. _OSD32MP15x SiP documentation:
+   https://octavosystems.com/docs/osd32mp15x-datasheet/
+
+.. _OSD32MP1 OpenSTLinux:
+   https://octavosystems.com/files/osd32mp1-brk-openstlinux-v3-0/
+
+.. _OSD32MP1-BRK Getting Started:
+    https://octavosystems.com/app_notes/osd32mp1-brk-getting-started/
+
+.. _stm32mp157 boot Cortex-M4 firmware:
+   https://wiki.st.com/stm32mpu/index.php/Linux_remoteproc_framework_overview#How_to_use_the_framework
+
+.. _OSD32MP1-BRK schematics:
+   https://octavosystems.com/docs/osd32mp1-brk-schematics/
+
+.. _OSD32MP1-BRK default pin mapping:
+   https://octavosystems.com/octavosystems.com/wp-content/uploads/2020/05/Default-Pin-Mapping.pdf
diff --git a/boards/oct/osd32mp1_brk/osd32mp1_brk.dts b/boards/oct/osd32mp1_brk/osd32mp1_brk.dts
new file mode 100644
index 00000000000..0ba685ec398
--- /dev/null
+++ b/boards/oct/osd32mp1_brk/osd32mp1_brk.dts
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2024 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <oct/osd32mp15x.dtsi>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "Octavo Systems OSD32MP1-BRK";
+	compatible = "oct,osd32mp1-brk";
+	chosen {
+		/*
+		 * By default, Zephyr console and shell are assigned to
+		 * remoteproc. To enable console and shell over UART, uncomment
+		 * following lines and set the correct config in
+		 * osd32mp1_brk_defconfig "Serial Port" section in Zephyr
+		 * board documentation.
+		 * zephyr,console = &usart2;
+		 * zephyr,shell-uart = &usart2;
+		 */
+		zephyr,flash = &retram;
+		zephyr,sram = &mcusram;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		green_led_2: led_1 {
+			label = "LED2_GRN";
+			gpios = <&gpioi 9 GPIO_ACTIVE_HIGH>;
+			status = "okay";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button: button {
+			label = "User 1";
+			gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	aliases {
+		led0 = &green_led_2;
+		sw0 = &user_button;
+	};
+};
+
+&spi4_miso_pe13 {
+	slew-rate = "very-high-speed";
+};
+
+&usart2 {
+	pinctrl-0 = <&usart2_tx_pf5 &usart2_rx_pf4>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&uart7 {
+	pinctrl-0 = <&uart7_tx_pa15 &uart7_rx_pb3>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&i2c5 {
+	pinctrl-0 = <&i2c5_scl_pd1 &i2c5_sda_pd0>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&uart7_tx_pa15 {
+	bias-disable;
+};
+
+&uart7_rx_pb3 {
+	bias-disable;
+};
+
+&usart2_tx_pf5 {
+	bias-disable;
+};
+
+&usart2_rx_pf4 {
+	bias-disable;
+};
diff --git a/boards/oct/osd32mp1_brk/osd32mp1_brk.yaml b/boards/oct/osd32mp1_brk/osd32mp1_brk.yaml
new file mode 100644
index 00000000000..b9d5e0ab7e1
--- /dev/null
+++ b/boards/oct/osd32mp1_brk/osd32mp1_brk.yaml
@@ -0,0 +1,22 @@
+identifier: osd32mp1_brk
+name: OSD32MP1-BRK
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+supported:
+  - gpio
+  - shell
+testing:
+  ignore_tags:
+    - cmsis_rtos_v2
+    - net
+    - mpu
+    - crypto
+    - aes
+    - cmm
+    - LED
+    - nfc
+ram: 256
+flash: 64
+vendor: oct
diff --git a/boards/oct/osd32mp1_brk/osd32mp1_brk_defconfig b/boards/oct/osd32mp1_brk/osd32mp1_brk_defconfig
new file mode 100644
index 00000000000..755f96c1948
--- /dev/null
+++ b/boards/oct/osd32mp1_brk/osd32mp1_brk_defconfig
@@ -0,0 +1,20 @@
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Console (remote proc console by default)
+CONFIG_CONSOLE=y
+CONFIG_RAM_CONSOLE=y
+CONFIG_RAM_CONSOLE_BUFFER_SIZE=1024
+
+# UART console (overrides remote proc console)
+CONFIG_UART_CONSOLE=n
diff --git a/boards/oct/osd32mp1_brk/support/openocd.cfg b/boards/oct/osd32mp1_brk/support/openocd.cfg
new file mode 100644
index 00000000000..c9f1013c691
--- /dev/null
+++ b/boards/oct/osd32mp1_brk/support/openocd.cfg
@@ -0,0 +1,6 @@
+source [find board/stm32mp15x_dk2.cfg]
+
+# By default the port 3333 is assigned for the Cortex-A debug. Disable them
+stm32mp15x.cpu0 configure -gdb-port disabled
+stm32mp15x.cpu1 configure -gdb-port disabled
+targets stm32mp15x.cm4
diff --git a/boards/olimex/lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst b/boards/olimex/lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst
index 1755c3cdc72..197e940c3f2 100644
--- a/boards/olimex/lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst
+++ b/boards/olimex/lora_stm32wl_devkit/doc/olimex_lora_stm32wl_devkit.rst
@@ -34,52 +34,13 @@ More information about the board and the module can be found here:
 Supported Features
 ==================
 
-The Zephyr Olimex LoRa STM32WL Dev Kit configuration supports the following
-hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| AES       | on-chip    | crypto                              |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| MPU       | on-chip    | arch/arm                            |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | arch/arm                            |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| RADIO     | on-chip    | LoRa                                |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in:
-
-- :zephyr_file:`boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_defconfig`
-- :zephyr_file:`boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit.dts`
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``olimex_lora_stm32wl_devkit`` board configuration can be built the
 usual way (see :ref:`build_an_application`).
 
diff --git a/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.yaml b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.yaml
index 5fdb67ec933..7fc09001375 100644
--- a/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.yaml
+++ b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_C.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 256
 supported:
diff --git a/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.yaml b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.yaml
index ead08879d1b..7d6af1766ef 100644
--- a/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.yaml
+++ b/boards/olimex/lora_stm32wl_devkit/olimex_lora_stm32wl_devkit_D.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 256
 supported:
diff --git a/boards/olimex/olimex_esp32_evb/doc/index.rst b/boards/olimex/olimex_esp32_evb/doc/index.rst
index 880e3933ab9..1f5ca0033fb 100644
--- a/boards/olimex/olimex_esp32_evb/doc/index.rst
+++ b/boards/olimex/olimex_esp32_evb/doc/index.rst
@@ -41,46 +41,7 @@ these reference documents:
 Supported Features
 ******************
 
-The olimex_esp32_evb board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| EFUSE     | on-chip    | hwinfo, device ID                   |
-+-----------+------------+-------------------------------------+
-| FLASH     | module     | External flash                      |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | I2C                                 |
-+-----------+------------+-------------------------------------+
-| INTERRUPT | on-chip    | interrupt controller                |
-+-----------+------------+-------------------------------------+
-| IO_MUX    | on-chip    | pinctrl                             |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| TIMG      | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| TWAI      | on-chip    | CAN controller                      |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | uart                                |
-+-----------+------------+-------------------------------------+
-| WDT       | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| WiFi      | on-chip    | WiFi                                |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/olimex/olimex_esp32_evb/olimex_esp32_evb_appcpu_defconfig`
-and
-:zephyr_file:`boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu_defconfig`
-
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 System requirements
 *******************
@@ -102,6 +63,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.dts b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.dts
index c39916c6de6..729a6e83a0b 100644
--- a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.dts
+++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu.dts
@@ -131,3 +131,7 @@ uext_spi: &spi2 {};
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu_defconfig b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu_defconfig
index f029cac9e9e..e192c240251 100644
--- a/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu_defconfig
+++ b/boards/olimex/olimex_esp32_evb/olimex_esp32_evb_procpu_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/olimex/olimexino_stm32/doc/index.rst b/boards/olimex/olimexino_stm32/doc/index.rst
index af42d6b0ac1..76a4466ff1c 100644
--- a/boards/olimex/olimexino_stm32/doc/index.rst
+++ b/boards/olimex/olimexino_stm32/doc/index.rst
@@ -14,33 +14,7 @@ information and the datasheet.
 Supported Features
 ==================
 
-The olimexino_stm32 board configuration supports the following
-hardware features:
-
-+-----------+------------+-------------------------+
-| Interface | Controller | Driver/Component        |
-+===========+============+=========================+
-| NVIC      | on-chip    | nested vectored         |
-|           |            | interrupt controller    |
-+-----------+------------+-------------------------+
-| SYSTICK   | on-chip    | system clock            |
-+-----------+------------+-------------------------+
-| UART      | on-chip    | serial port             |
-+-----------+------------+-------------------------+
-| GPIO      | on-chip    | gpio                    |
-+-----------+------------+-------------------------+
-| I2C       | on-chip    | i2c                     |
-+-----------+------------+-------------------------+
-| SPI       | on-chip    | spi                     |
-+-----------+------------+-------------------------+
-| USB       | on-chip    | USB device              |
-+-----------+------------+-------------------------+
-| WATCHDOG  | on-chip    | independent watchdog    |
-+-----------+------------+-------------------------+
-| CAN       | on-chip    | Controller Area Network |
-+-----------+------------+-------------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -377,6 +351,8 @@ The default jumper settings for the OLIMEXIMO-STM32E are:
 Flashing Zephyr onto OLIMEXINO-STM32
 ************************************
 
+.. zephyr:board-supported-runners::
+
 Flashing the Zephyr kernel onto OLIMEXINO-STM32 requires the
 `stm32flash tool`_.
 
diff --git a/boards/olimex/olimexino_stm32/olimexino_stm32.yaml b/boards/olimex/olimexino_stm32/olimexino_stm32.yaml
index 266ff002184..fd3b52f986a 100644
--- a/boards/olimex/olimexino_stm32/olimexino_stm32.yaml
+++ b/boards/olimex/olimexino_stm32/olimexino_stm32.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 20
 supported:
   - gpio
diff --git a/boards/olimex/stm32_e407/doc/index.rst b/boards/olimex/stm32_e407/doc/index.rst
index 98a698b3c14..84bd6c1673e 100644
--- a/boards/olimex/stm32_e407/doc/index.rst
+++ b/boards/olimex/stm32_e407/doc/index.rst
@@ -17,27 +17,7 @@ information and the datasheet.
 Supported Features
 ==================
 
-The olimex_stm32_e407 board configuration supports the following
-hardware features:
-
-+------------+------------+----------------------+
-| Interface  | Controller | Driver/Component     |
-+============+============+======================+
-| NVIC       | on-chip    | nested vectored      |
-|            |            | interrupt controller |
-+------------+------------+----------------------+
-| SYSTICK    | on-chip    | system clock         |
-+------------+------------+----------------------+
-| UART       | on-chip    | serial port          |
-+------------+------------+----------------------+
-| GPIO       | on-chip    | gpio                 |
-+------------+------------+----------------------+
-| USB OTG FS | on-chip    | USB device           |
-+------------+------------+----------------------+
-| USB OTG HS | on-chip    | USB device           |
-+------------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -312,6 +292,9 @@ which can be set as high as 168 MHz.
 
 Programming and Debugging
 *************************
+
+.. zephyr:board-supported-runners::
+
 The OLIMEX-STM32-E407 board does not include an embedded debug tool
 interface. You will need to use ST tools or an external JTAG probe.
 In the following examples a ST-Link V2 USB dongle is used.
diff --git a/boards/olimex/stm32_e407/olimex_stm32_e407.dts b/boards/olimex/stm32_e407/olimex_stm32_e407.dts
index 728380da88d..897370a31f9 100644
--- a/boards/olimex/stm32_e407/olimex_stm32_e407.dts
+++ b/boards/olimex/stm32_e407/olimex_stm32_e407.dts
@@ -116,15 +116,26 @@ zephyr_udc0: &usbotg_hs {
 
 &mac {
 	status = "okay";
-	pinctrl-0 = <&eth_mdc_pc1
-		     &eth_rxd0_pc4
+	pinctrl-0 = <&eth_rxd0_pc4
 		     &eth_rxd1_pc5
 		     &eth_ref_clk_pa1
-		     &eth_mdio_pa2
 		     &eth_col_pa3
 		     &eth_crs_dv_pa7
 		     &eth_tx_en_pg11
 		     &eth_txd0_pg13
 		     &eth_txd1_pg14>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
+	pinctrl-names = "default";
+
+	eth_phy: ethernet-phy@0 {
+		compatible = "ethernet-phy";
+		reg = <0x00>;
+	};
 };
diff --git a/boards/olimex/stm32_e407/olimex_stm32_e407.yaml b/boards/olimex/stm32_e407/olimex_stm32_e407.yaml
index beefd5d2c8a..8c68e307af6 100644
--- a/boards/olimex/stm32_e407/olimex_stm32_e407.yaml
+++ b/boards/olimex/stm32_e407/olimex_stm32_e407.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 1024
 supported:
diff --git a/boards/olimex/stm32_h103/doc/index.rst b/boards/olimex/stm32_h103/doc/index.rst
index 3055207f476..fc5c9f4dcfa 100644
--- a/boards/olimex/stm32_h103/doc/index.rst
+++ b/boards/olimex/stm32_h103/doc/index.rst
@@ -20,32 +20,7 @@ information and the datasheet.
 Supported Features
 ==================
 
-The OLIMEX STM32-H103 supports the following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| NVIC      | on-chip    | nested vectored      |
-|           |            | interrupt controller |
-+-----------+------------+----------------------+
-| SYSTICK   | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial port          |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| USB       | on-chip    | USB device           |
-+-----------+------------+----------------------+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -181,6 +156,8 @@ EXTENSION 2
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 This board does not include any embedded debug tool interface, instead you
 will have to use an external probe connected to the available 20-pin JTAG
 connector to program and debug the board. Both JTAG and SWD are supported.
diff --git a/boards/olimex/stm32_h103/olimex_stm32_h103.yaml b/boards/olimex/stm32_h103/olimex_stm32_h103.yaml
index b863460fda4..f1b406b1c68 100644
--- a/boards/olimex/stm32_h103/olimex_stm32_h103.yaml
+++ b/boards/olimex/stm32_h103/olimex_stm32_h103.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 20
 flash: 128
 supported:
diff --git a/boards/olimex/stm32_h405/doc/index.rst b/boards/olimex/stm32_h405/doc/index.rst
index 4d06e17c991..22a35de4069 100644
--- a/boards/olimex/stm32_h405/doc/index.rst
+++ b/boards/olimex/stm32_h405/doc/index.rst
@@ -17,32 +17,7 @@ information and the datasheet.
 Supported Features
 ==================
 
-The olimex_stm32_h405 board configuration supports the following
-hardware features:
-
-+-----------+------------+-------------------------+
-| Interface | Controller | Driver/Component        |
-+===========+============+=========================+
-| NVIC      | on-chip    | nested vectored         |
-|           |            | interrupt controller    |
-+-----------+------------+-------------------------+
-| SYSTICK   | on-chip    | system clock            |
-+-----------+------------+-------------------------+
-| UART      | on-chip    | serial port             |
-+-----------+------------+-------------------------+
-| GPIO      | on-chip    | gpio                    |
-+-----------+------------+-------------------------+
-| USB       | on-chip    | USB device              |
-+-----------+------------+-------------------------+
-| WATCHDOG  | on-chip    | independent watchdog    |
-+-----------+------------+-------------------------+
-| COUNTER   | on-chip    | rtc                     |
-+-----------+------------+-------------------------+
-| RNG       | on-chip    | random number generator |
-+-----------+------------+-------------------------+
-
-Other hardware features have not been enabled yet for this board.
-
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -149,6 +124,9 @@ which can be set as high as 168 MHz.
 
 Programming and Debugging
 *************************
+
+.. zephyr:board-supported-runners::
+
 The OLIMEX-STM32-H405 board does not include an embedded debug tool
 interface. You will need to use ST tools or an external JTAG probe.
 In the following examples a ST-Link V2 USB dongle is used.
diff --git a/boards/olimex/stm32_h405/olimex_stm32_h405.yaml b/boards/olimex/stm32_h405/olimex_stm32_h405.yaml
index 9930505236f..686345ce2ac 100644
--- a/boards/olimex/stm32_h405/olimex_stm32_h405.yaml
+++ b/boards/olimex/stm32_h405/olimex_stm32_h405.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 1024
 supported:
diff --git a/boards/olimex/stm32_h407/doc/index.rst b/boards/olimex/stm32_h407/doc/index.rst
index 13ad7db8ce3..8005208930d 100644
--- a/boards/olimex/stm32_h407/doc/index.rst
+++ b/boards/olimex/stm32_h407/doc/index.rst
@@ -23,23 +23,7 @@ information and the datasheet.
 Supported Features
 ==================
 
-The olimex_stm32_h407 board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| NVIC      | on-chip    | nested vectored      |
-|           |            | interrupt controller |
-+-----------+------------+----------------------+
-| SYSTICK   | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial port          |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -314,6 +298,9 @@ which can be set as high as 168 MHz.
 
 Programming and Debugging
 *************************
+
+.. zephyr:board-supported-runners::
+
 The OLIMEX-STM32-H407 board does not include an embedded debug tool
 interface. You will need to use ST tools or an external JTAG probe.
 In the following examples the Olimex ARM-USB-OCD-H is used.
diff --git a/boards/olimex/stm32_h407/olimex_stm32_h407.yaml b/boards/olimex/stm32_h407/olimex_stm32_h407.yaml
index fea55c8a3d4..b7cdeeccf4d 100644
--- a/boards/olimex/stm32_h407/olimex_stm32_h407.yaml
+++ b/boards/olimex/stm32_h407/olimex_stm32_h407.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 1024
 supported:
diff --git a/boards/olimex/stm32_p405/doc/index.rst b/boards/olimex/stm32_p405/doc/index.rst
index 87a3d409d59..18a0653ec49 100644
--- a/boards/olimex/stm32_p405/doc/index.rst
+++ b/boards/olimex/stm32_p405/doc/index.rst
@@ -17,23 +17,7 @@ information and the datasheet.
 Supported Features
 ==================
 
-The olimex_stm32_p405 board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| NVIC      | on-chip    | nested vectored      |
-|           |            | interrupt controller |
-+-----------+------------+----------------------+
-| SYSTICK   | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial port          |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -200,6 +184,9 @@ which can be set as high as 168 MHz.
 
 Programming and Debugging
 *************************
+
+.. zephyr:board-supported-runners::
+
 The OLIMEX-STM32-P405 board does not include an embedded debug tool
 interface. You will need to use ST tools or an external JTAG probe.
 In the following examples a ST-Link V2 USB dongle is used.
diff --git a/boards/olimex/stm32_p405/olimex_stm32_p405.yaml b/boards/olimex/stm32_p405/olimex_stm32_p405.yaml
index d3c23913f35..67e408336ff 100644
--- a/boards/olimex/stm32_p405/olimex_stm32_p405.yaml
+++ b/boards/olimex/stm32_p405/olimex_stm32_p405.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 1024
 supported:
diff --git a/boards/openhwgroup/cv32a6_genesys_2/Kconfig.cv32a6_genesys_2 b/boards/openhwgroup/cv32a6_genesys_2/Kconfig.cv32a6_genesys_2
new file mode 100644
index 00000000000..2d08387fb6a
--- /dev/null
+++ b/boards/openhwgroup/cv32a6_genesys_2/Kconfig.cv32a6_genesys_2
@@ -0,0 +1,4 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+config BOARD_CV32A6_GENESYS_2
+	select SOC_CV32A6
diff --git a/boards/openhwgroup/cv32a6_genesys_2/board.cmake b/boards/openhwgroup/cv32a6_genesys_2/board.cmake
new file mode 100644
index 00000000000..921ea08b8c7
--- /dev/null
+++ b/boards/openhwgroup/cv32a6_genesys_2/board.cmake
@@ -0,0 +1,8 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+board_runner_args(openocd "--config=${BOARD_DIR}/support/ariane.cfg")
+board_runner_args(openocd "--use-elf")
+board_runner_args(openocd "--verify")
+board_runner_args(openocd "--cmd-pre-init=riscv.cpu configure -work-area-phys 0x90000000 -work-area-size 16780000")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/openhwgroup/cv32a6_genesys_2/board.yml b/boards/openhwgroup/cv32a6_genesys_2/board.yml
new file mode 100644
index 00000000000..64fbf083382
--- /dev/null
+++ b/boards/openhwgroup/cv32a6_genesys_2/board.yml
@@ -0,0 +1,7 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+board:
+  name: cv32a6_genesys_2
+  vendor: openhwgroup
+  socs:
+    - name: cv32a6
diff --git a/boards/openhwgroup/cv32a6_genesys_2/cv32a6_genesys_2.dts b/boards/openhwgroup/cv32a6_genesys_2/cv32a6_genesys_2.dts
new file mode 100644
index 00000000000..a6588c2aa4c
--- /dev/null
+++ b/boards/openhwgroup/cv32a6_genesys_2/cv32a6_genesys_2.dts
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <openhwgroup/cv32a6.dtsi>
+
+/ {
+	model = "Openhardwaregroup CV32A6 on Genesys 2";
+	compatible = "openhwgroup,cv32a6_genesys_2";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &memory0;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+};
+
+&clint {
+	status = "okay";
+};
+
+&mtimer {
+	status = "okay";
+};
+
+&eth {
+	local-mac-address = [00 18 3e 02 e3 7f];
+	status = "okay";
+};
+
+&xlnx_gpio {
+	status = "okay";
+};
diff --git a/boards/openhwgroup/cv32a6_genesys_2/cv32a6_genesys_2.yaml b/boards/openhwgroup/cv32a6_genesys_2/cv32a6_genesys_2.yaml
new file mode 100644
index 00000000000..243237da98f
--- /dev/null
+++ b/boards/openhwgroup/cv32a6_genesys_2/cv32a6_genesys_2.yaml
@@ -0,0 +1,12 @@
+identifier: cv32a6_genesys_2
+name: OpenHW Group cv32a6 on Genesys 2
+type: mcu
+arch: riscv
+ram: 1048576
+toolchain:
+  - zephyr
+supported:
+  - gpio
+  - spi
+  - uart
+vendor: openhwgroup
diff --git a/boards/openhwgroup/cv32a6_genesys_2/cv32a6_genesys_2_defconfig b/boards/openhwgroup/cv32a6_genesys_2/cv32a6_genesys_2_defconfig
new file mode 100644
index 00000000000..90772f73ca0
--- /dev/null
+++ b/boards/openhwgroup/cv32a6_genesys_2/cv32a6_genesys_2_defconfig
@@ -0,0 +1,9 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+CONFIG_INCLUDE_RESET_VECTOR=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y
+CONFIG_CONSOLE_HANDLER=y
+CONFIG_XIP=n
diff --git a/boards/openhwgroup/cv32a6_genesys_2/doc/cv32a6_genesys_2.webp b/boards/openhwgroup/cv32a6_genesys_2/doc/cv32a6_genesys_2.webp
new file mode 100644
index 00000000000..e78dc22136f
Binary files /dev/null and b/boards/openhwgroup/cv32a6_genesys_2/doc/cv32a6_genesys_2.webp differ
diff --git a/boards/openhwgroup/cv32a6_genesys_2/doc/index.rst b/boards/openhwgroup/cv32a6_genesys_2/doc/index.rst
new file mode 100644
index 00000000000..85479edcb68
--- /dev/null
+++ b/boards/openhwgroup/cv32a6_genesys_2/doc/index.rst
@@ -0,0 +1,81 @@
+.. zephyr:board:: cv32a6_genesys_2
+
+Overview
+********
+
+The Digilent Genesys 2 board features a Xilinx Kintex-7 FPGA which can run various softcore CPUs.
+In this configuration, the Genesys 2 is configured with a 32-bit version of the CVA6 RISC-V CPU.
+The SoC is configured with a memory controller interfacing with the Genesys' DRAM, PLIC and CLINT
+interrupt controllers, a UART device interfacing with the Genesys' USB UART, a RISC-V compatible
+debug module that interfaces with the Genesys' FTDI (USB JTAG) chip, a Xilinx SPI interface
+interfacing with the Genesys' SD card slot and a Xilinx GPIO interfacing with the Genesys' LEDs
+and switches.
+The complete hardware sources (see first reference) in conjunction with
+instructions for compiling and loading the configuration onto the Genesys 2 are available.
+
+See the following references for more information:
+
+- `CVA6 documentation`_
+- `Genesys 2 Reference Manual`_
+- `Genesys 2 Schematic`_
+
+Hardware
+********
+
+- CVA6 CPU with RV32imac instruction sets with PLIC, CLINT interrupt controllers.
+- 1 GB DDR3 DRAM
+- 10/100/1000 Ethernet with copper interface, lowRISC Ethernet MAC
+- ns16550a-compatible USB UART, 115200 baud
+- RISCV debug module, connected via on-board FTDI (USB JTAG)
+- Xilinx SPI controller, connected to microSD slot
+- Xilinx GPIO, connected to 7 switches and LEDs
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+Loading the FPGA configuration
+==============================
+
+You need to build a bitstream with Xilinx Vivado and load it into the FPGA
+before you can load zephyr onto the board.
+Please refer to the CVA6 documentation for the required steps.
+This configuration is compatible with the following build targets:
+cv32a6_imac_sv0, cv32a6_imac_sv32, cv32a6_imafc_sv32, cv32a6_ima_sv32_fpga.
+
+Flashing
+========
+west flash is supported via the openocd runner.
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: cv32a6_genesys_2
+   :goals: build flash
+
+Debugging
+=========
+
+west debug, attach and debugserver commands are supported via the openocd runner.
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: cv32a6_genesys_2
+   :goals: build debug
+
+References
+**********
+
+.. _CVA6 documentation:
+   https://github.com/openhwgroup/cva6
+
+.. _Genesys 2 Reference Manual:
+   https://digilent.com/reference/programmable-logic/genesys-2/reference-manual
+
+.. _Genesys 2 Schematic:
+   https://digilent.com/reference/_media/reference/programmable-logic/genesys-2/genesys-2_sch.pdf
diff --git a/boards/openhwgroup/cv32a6_genesys_2/support/ariane.cfg b/boards/openhwgroup/cv32a6_genesys_2/support/ariane.cfg
new file mode 100644
index 00000000000..9bece8fca9c
--- /dev/null
+++ b/boards/openhwgroup/cv32a6_genesys_2/support/ariane.cfg
@@ -0,0 +1,49 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+# Based on the ariane.cfg from the cva6 project:
+# https://github.com/openhwgroup/cva6/blob/master/corev_apu/fpga/ariane.cfg
+adapter_khz     1000
+
+interface ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+# Channel 1 is taken by Xilinx JTAG
+ftdi_channel 0
+
+# links:
+# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html
+#
+# Bit  MPSSE     FT2232    JTAG    Type   Description
+# Bit0 TCK       ADBUS0    TCK     Out    Clock Signal Output
+# Bit1 TDI       ADBUS1    TDI     Out    Serial Data Out
+# Bit2 TDO       ADBUS2    TDO     In     Serial Data In
+# Bit3 TMS       ADBUS3    TMS     Out    Select Signal Out
+# Bit4 GPIOL0    ADBUS4    nTRST   In/Out General Purpose I/O
+# this corresponds to the following in/out layout, with TMS initially set to 1
+ftdi_layout_init 0x0018 0x001b
+# we only have to specify nTRST, the others are assigned correctly by default
+ftdi_layout_signal nTRST -ndata 0x0010
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+riscv set_reset_timeout_sec 120
+riscv set_command_timeout_sec 120
+
+# prefer to use sba for system bus access
+riscv set_prefer_sba off
+
+# Try enabling address translation (only works for newer versions)
+if { [catch {riscv set_enable_virtual on} ] } {
+    echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." }
+
+init
+halt
+echo "Ready for Remote Connections"
diff --git a/boards/openhwgroup/cv64a6_genesys_2/Kconfig.cv64a6_genesys_2 b/boards/openhwgroup/cv64a6_genesys_2/Kconfig.cv64a6_genesys_2
new file mode 100644
index 00000000000..1a983093e99
--- /dev/null
+++ b/boards/openhwgroup/cv64a6_genesys_2/Kconfig.cv64a6_genesys_2
@@ -0,0 +1,4 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+config BOARD_CV64A6_GENESYS_2
+	select SOC_CV64A6_IMAFDC
diff --git a/boards/openhwgroup/cv64a6_genesys_2/board.cmake b/boards/openhwgroup/cv64a6_genesys_2/board.cmake
new file mode 100644
index 00000000000..921ea08b8c7
--- /dev/null
+++ b/boards/openhwgroup/cv64a6_genesys_2/board.cmake
@@ -0,0 +1,8 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+board_runner_args(openocd "--config=${BOARD_DIR}/support/ariane.cfg")
+board_runner_args(openocd "--use-elf")
+board_runner_args(openocd "--verify")
+board_runner_args(openocd "--cmd-pre-init=riscv.cpu configure -work-area-phys 0x90000000 -work-area-size 16780000")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/openhwgroup/cv64a6_genesys_2/board.yml b/boards/openhwgroup/cv64a6_genesys_2/board.yml
new file mode 100644
index 00000000000..293fab13c58
--- /dev/null
+++ b/boards/openhwgroup/cv64a6_genesys_2/board.yml
@@ -0,0 +1,7 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+board:
+  name: cv64a6_genesys_2
+  vendor: openhwgroup
+  socs:
+    - name: cv64a6_imafdc
diff --git a/boards/openhwgroup/cv64a6_genesys_2/cv64a6_genesys_2.dts b/boards/openhwgroup/cv64a6_genesys_2/cv64a6_genesys_2.dts
new file mode 100644
index 00000000000..eab1183221a
--- /dev/null
+++ b/boards/openhwgroup/cv64a6_genesys_2/cv64a6_genesys_2.dts
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <openhwgroup/cv64a6.dtsi>
+
+/ {
+	model = "Openhardwaregroup CV64A6 on Genesys 2";
+	compatible = "openhwgroup,cv64a6_genesys_2";
+
+	chosen {
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,sram = &memory0;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+};
+
+&clint {
+	status = "okay";
+};
+
+&mtimer {
+	status = "okay";
+};
+
+&dma0 {
+	status = "disabled";
+};
+
+&eth {
+	local-mac-address = [00 18 3e 02 e3 7f];
+	status = "okay";
+};
+
+&xlnx_gpio {
+	status = "okay";
+};
diff --git a/boards/openhwgroup/cv64a6_genesys_2/cv64a6_genesys_2.yaml b/boards/openhwgroup/cv64a6_genesys_2/cv64a6_genesys_2.yaml
new file mode 100644
index 00000000000..d54b2ec0ebf
--- /dev/null
+++ b/boards/openhwgroup/cv64a6_genesys_2/cv64a6_genesys_2.yaml
@@ -0,0 +1,12 @@
+identifier: cv64a6_genesys_2
+name: OpenHW Group cv64a6 on Genesys 2
+type: mcu
+arch: riscv
+ram: 1048576
+toolchain:
+  - zephyr
+supported:
+  - gpio
+  - spi
+  - uart
+vendor: openhwgroup
diff --git a/boards/openhwgroup/cv64a6_genesys_2/cv64a6_genesys_2_defconfig b/boards/openhwgroup/cv64a6_genesys_2/cv64a6_genesys_2_defconfig
new file mode 100644
index 00000000000..90772f73ca0
--- /dev/null
+++ b/boards/openhwgroup/cv64a6_genesys_2/cv64a6_genesys_2_defconfig
@@ -0,0 +1,9 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+CONFIG_INCLUDE_RESET_VECTOR=y
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_NS16550_ACCESS_WORD_ONLY=y
+CONFIG_CONSOLE_HANDLER=y
+CONFIG_XIP=n
diff --git a/boards/openhwgroup/cv64a6_genesys_2/doc/cv64a6_genesys_2.webp b/boards/openhwgroup/cv64a6_genesys_2/doc/cv64a6_genesys_2.webp
new file mode 100644
index 00000000000..e78dc22136f
Binary files /dev/null and b/boards/openhwgroup/cv64a6_genesys_2/doc/cv64a6_genesys_2.webp differ
diff --git a/boards/openhwgroup/cv64a6_genesys_2/doc/index.rst b/boards/openhwgroup/cv64a6_genesys_2/doc/index.rst
new file mode 100644
index 00000000000..090332078de
--- /dev/null
+++ b/boards/openhwgroup/cv64a6_genesys_2/doc/index.rst
@@ -0,0 +1,80 @@
+.. zephyr:board:: cv64a6_genesys_2
+
+Overview
+********
+
+The Digilent Genesys 2 board features a Xilinx Kintex-7 FPGA which can run various softcore CPUs.
+In this configuration, the Genesys 2 is configured with a 64-bit version of the CVA6 RISC-V CPU.
+The SoC is configured with a memory controller interfacing with the Genesys' DRAM, PLIC and CLINT
+interrupt controllers, a UART device interfacing with the Genesys' USB UART, a RISC-V compatible
+debug module that interfaces with the Genesys' FTDI (USB JTAG) chip, a Xilinx SPI interface
+interfacing with the Genesys' SD card slot and a Xilinx GPIO interfacing with the Genesys' LEDs
+and switches.
+The complete hardware sources (see first reference) in conjunction with
+instructions for compiling and loading the configuration onto the Genesys 2 are available.
+
+See the following references for more information:
+
+- `CVA6 documentation`_
+- `Genesys 2 Reference Manual`_
+- `Genesys 2 Schematic`_
+
+Hardware
+********
+
+- CVA6 CPU with RV64imafdc instruction sets and an SV39 MMU
+- 1 GB DDR3 DRAM
+- 10/100/1000 Ethernet with copper interface, lowRISC Ethernet MAC
+- ns16550a-compatible USB UART, 115200 baud
+- RISCV debug module, connected via on-board FTDI (USB JTAG)
+- Xilinx SPI controller, connected to microSD slot
+- Xilinx GPIO, connected to 7 switches and LEDs
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+Loading the FPGA configuration
+==============================
+
+You need to build a bitstream with Xilinx Vivado and load it into the FPGA
+before you can load zephyr onto the board.
+Please refer to the CVA6 documentation for the required steps.
+This configuration is compatible with the following build target: cv64a6_imafdc_sv39
+
+Flashing
+========
+west flash is supported via the openocd runner.
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: cv64a6_genesys_2
+   :goals: build flash
+
+Debugging
+=========
+
+west debug, attach and debugserver commands are supported via the openocd runner.
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: cv64a6_genesys_2
+   :goals: build debug
+
+References
+**********
+
+.. _CVA6 documentation:
+   https://github.com/openhwgroup/cva6
+
+.. _Genesys 2 Reference Manual:
+   https://digilent.com/reference/programmable-logic/genesys-2/reference-manual
+
+.. _Genesys 2 Schematic:
+   https://digilent.com/reference/_media/reference/programmable-logic/genesys-2/genesys-2_sch.pdf
diff --git a/boards/openhwgroup/cv64a6_genesys_2/support/ariane.cfg b/boards/openhwgroup/cv64a6_genesys_2/support/ariane.cfg
new file mode 100644
index 00000000000..9bece8fca9c
--- /dev/null
+++ b/boards/openhwgroup/cv64a6_genesys_2/support/ariane.cfg
@@ -0,0 +1,49 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+# Based on the ariane.cfg from the cva6 project:
+# https://github.com/openhwgroup/cva6/blob/master/corev_apu/fpga/ariane.cfg
+adapter_khz     1000
+
+interface ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+# Channel 1 is taken by Xilinx JTAG
+ftdi_channel 0
+
+# links:
+# http://openocd.org/doc-release/html/Debug-Adapter-Configuration.html
+#
+# Bit  MPSSE     FT2232    JTAG    Type   Description
+# Bit0 TCK       ADBUS0    TCK     Out    Clock Signal Output
+# Bit1 TDI       ADBUS1    TDI     Out    Serial Data Out
+# Bit2 TDO       ADBUS2    TDO     In     Serial Data In
+# Bit3 TMS       ADBUS3    TMS     Out    Select Signal Out
+# Bit4 GPIOL0    ADBUS4    nTRST   In/Out General Purpose I/O
+# this corresponds to the following in/out layout, with TMS initially set to 1
+ftdi_layout_init 0x0018 0x001b
+# we only have to specify nTRST, the others are assigned correctly by default
+ftdi_layout_signal nTRST -ndata 0x0010
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid 0
+
+gdb_report_data_abort enable
+gdb_report_register_access_error enable
+
+riscv set_reset_timeout_sec 120
+riscv set_command_timeout_sec 120
+
+# prefer to use sba for system bus access
+riscv set_prefer_sba off
+
+# Try enabling address translation (only works for newer versions)
+if { [catch {riscv set_enable_virtual on} ] } {
+    echo "Warning: This version of OpenOCD does not support address translation. To debug on virtual addresses, please update to the latest version." }
+
+init
+halt
+echo "Ready for Remote Connections"
diff --git a/boards/openhwgroup/index.rst b/boards/openhwgroup/index.rst
new file mode 100644
index 00000000000..5ad2474d9b4
--- /dev/null
+++ b/boards/openhwgroup/index.rst
@@ -0,0 +1,10 @@
+.. _boards-openhwgroup:
+
+OpenHW Group
+############
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*
diff --git a/boards/openisa/rv32m1_vega/doc/index.rst b/boards/openisa/rv32m1_vega/doc/index.rst
index d5cf180bb1b..97c2ba7b44a 100644
--- a/boards/openisa/rv32m1_vega/doc/index.rst
+++ b/boards/openisa/rv32m1_vega/doc/index.rst
@@ -59,59 +59,7 @@ Additional features:
 Supported Features
 ==================
 
-Zephyr's RI5CY configuration, ``rv32m1_vega/openisa_rv32m1/ri5cy``, currently supports
-the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| EVENT     | on-chip    | event unit interrupt controller     |
-+-----------+------------+-------------------------------------+
-| INTMUX    | on-chip    | level 2 interrupt controller        |
-+-----------+------------+-------------------------------------+
-| LPTMR     | on-chip    | lptmr-based system timer            |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| I2C(M)    | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| TPM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| SENSOR    | off-chip   | fxos8700 polling;                   |
-|           |            | fxos8700 trigger;                   |
-+-----------+------------+-------------------------------------+
-
-Zephyr's ZERO-RISCY configuration, ``rv32m1_vega/openisa_rv32m1/zero_riscy``, currently
-supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| EVENT     | on-chip    | event unit interrupt controller     |
-+-----------+------------+-------------------------------------+
-| INTMUX    | on-chip    | level 2 interrupt controller        |
-+-----------+------------+-------------------------------------+
-| LPTMR     | on-chip    | lptmr-based system timer            |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| I2C(M)    | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| TPM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| SENSOR    | off-chip   | fxos8700 polling;                   |
-|           |            | fxos8700 trigger;                   |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 BLE Software Link Layer experimental support
 ==================================================
@@ -337,6 +285,8 @@ default for console and logging.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 .. _rv32m1-programming-hw:
 
 .. important::
diff --git a/boards/others/black_f407ve/black_f407ve.yaml b/boards/others/black_f407ve/black_f407ve.yaml
index 3b37380ff48..849779180eb 100644
--- a/boards/others/black_f407ve/black_f407ve.yaml
+++ b/boards/others/black_f407ve/black_f407ve.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 192
 flash: 512
 supported:
diff --git a/boards/others/black_f407ve/doc/index.rst b/boards/others/black_f407ve/doc/index.rst
index f6f088b3998..b15012459fc 100644
--- a/boards/others/black_f407ve/doc/index.rst
+++ b/boards/others/black_f407ve/doc/index.rst
@@ -81,40 +81,12 @@ More information about STM32F407VE SOC can be found here:
 Supported Features
 ==================
 
-The Zephyr black_f407ve board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb                                 |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | CAN controller                      |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 .. note:: CAN feature requires CAN transceiver.
 	  Zephyr default configuration uses CAN_2 exclusively, as
 	  simultaneous use of CAN_1 and CAN_2 is not yet supported.
 
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in
-:zephyr_file:`boards/others/black_f407ve/black_f407ve_defconfig`
-
-
 Pin Mapping
 ===========
 
@@ -181,6 +153,8 @@ it to UART1 pins (PA9/PA10).
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``black_f407ve`` board configuration can be built and
 flashed in the usual way (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/others/black_f407zg_pro/black_f407zg_pro.yaml b/boards/others/black_f407zg_pro/black_f407zg_pro.yaml
index a686cf3a54c..5a720fbbdcd 100644
--- a/boards/others/black_f407zg_pro/black_f407zg_pro.yaml
+++ b/boards/others/black_f407zg_pro/black_f407zg_pro.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 192
 flash: 1024
 supported:
diff --git a/boards/others/black_f407zg_pro/doc/index.rst b/boards/others/black_f407zg_pro/doc/index.rst
index ec7e6313c10..db45dd7b539 100644
--- a/boards/others/black_f407zg_pro/doc/index.rst
+++ b/boards/others/black_f407zg_pro/doc/index.rst
@@ -78,40 +78,12 @@ More information about STM32F407ZG SOC can be found here:
 Supported Features
 ==================
 
-The Zephyr black_f407zg_pro board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb                                 |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | CAN controller                      |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 .. note:: CAN feature requires CAN transceiver.
 	  Zephyr default configuration uses CAN_2 exclusively, as
 	  simultaneous use of CAN_1 and CAN_2 is not yet supported.
 
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in
-:zephyr_file:`boards/others/black_f407zg_pro/black_f407zg_pro_defconfig`
-
-
 Pin Mapping
 ===========
 
@@ -163,6 +135,8 @@ it to UART2 pins (PA2/PA3).
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``black_f407zg_pro`` board configuration can be built and
 flashed in the usual way (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/others/canbardo/Kconfig.canbardo b/boards/others/canbardo/Kconfig.canbardo
new file mode 100644
index 00000000000..dd82cb29466
--- /dev/null
+++ b/boards/others/canbardo/Kconfig.canbardo
@@ -0,0 +1,5 @@
+# Copyright (c) 2024-2025 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_CANBARDO
+	select SOC_SAME70N20B
diff --git a/boards/others/canbardo/board.cmake b/boards/others/canbardo/board.cmake
new file mode 100644
index 00000000000..470cf0a5322
--- /dev/null
+++ b/boards/others/canbardo/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2024-2025 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=ATSAME70N20B")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/others/canbardo/board.yml b/boards/others/canbardo/board.yml
new file mode 100644
index 00000000000..096e332f896
--- /dev/null
+++ b/boards/others/canbardo/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: canbardo
+  full_name: CANbardo
+  vendor: others
+  socs:
+    - name: same70n20b
diff --git a/boards/others/canbardo/canbardo-pinctrl.dtsi b/boards/others/canbardo/canbardo-pinctrl.dtsi
new file mode 100644
index 00000000000..18a4cb01c72
--- /dev/null
+++ b/boards/others/canbardo/canbardo-pinctrl.dtsi
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2024-2025 Henrik Brix Andersen <henrik@brixandersen.dk>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/same70n-pinctrl.h>
+
+&pinctrl {
+	uart1_default: uart1_default {
+		group1 {
+			pinmux = <PA5C_UART1_RXD>,
+				 <PA4C_UART1_TXD>;
+		};
+	};
+
+	can0_default: can0_default {
+		group1 {
+			pinmux = <PB3A_CAN0_RX>,
+				 <PB2A_CAN0_TX>;
+		};
+	};
+
+	can1_default: can1_default {
+		group1 {
+			pinmux = <PD28B_CAN1_RX>,
+				 <PD12B_CAN1_TX>;
+		};
+	};
+};
diff --git a/boards/others/canbardo/canbardo.dts b/boards/others/canbardo/canbardo.dts
new file mode 100644
index 00000000000..70da7b427bf
--- /dev/null
+++ b/boards/others/canbardo/canbardo.dts
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2024-2025 Henrik Brix Andersen <henrik@brixandersen.dk>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <freq.h>
+#include <mem.h>
+#include <atmel/same70x20b.dtsi>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+#include "canbardo-pinctrl.dtsi"
+
+/ {
+	model = "CANbardo board";
+	compatible = "canbardo", "atmel,same70n20b", "atmel,same70b";
+
+	chosen {
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,canbus = &can0;
+	};
+
+	aliases {
+		led0 = &dfu_led;
+		sw0 = &sw;
+		mcuboot-led0 = &dfu_led;
+		mcuboot-button0 = &sw;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		dfu_led: dfu_led {
+			gpios = <&piod 9 GPIO_ACTIVE_LOW>;
+			label = "DFU LED";
+		};
+
+		can_0_ledr: can_0_ledr {
+			gpios = <&piod 25 GPIO_ACTIVE_LOW>;
+			label = "CAN0 LED ERR";
+		};
+
+		can_0_ledg: can_0_ledg {
+			gpios = <&piod 22 GPIO_ACTIVE_LOW>;
+			label = "CAN0 LED RDY";
+		};
+
+		can_0_ledy: can_0_ledy {
+			gpios = <&piod 24 GPIO_ACTIVE_LOW>;
+			label = "CAN0 LED ACT";
+		};
+
+		can_1_ledr: can_1_ledr {
+			gpios = <&piod 19 GPIO_ACTIVE_LOW>;
+			label = "CAN1 LED ERR";
+		};
+
+		can_1_ledg: can_1_ledg {
+			gpios = <&piod 17 GPIO_ACTIVE_LOW>;
+			label = "CAN1 LED RDY";
+		};
+
+		can_1_ledy: can_1_ledy {
+			gpios = <&piod 18 GPIO_ACTIVE_LOW>;
+			label = "CAN1 LED ACT";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		sw: sw {
+			label = "SW";
+			gpios = <&piod 15 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	transceiver0: can-phy0 {
+		compatible = "microchip,mcp2558fd", "can-transceiver-gpio";
+		enable-gpios = <&piod 26 GPIO_ACTIVE_LOW>;
+		max-bitrate = <8000000>;
+		#phy-cells = <0>;
+	};
+
+	transceiver1: can-phy1 {
+		compatible = "microchip,mcp2558fd", "can-transceiver-gpio";
+		enable-gpios = <&piod 20 GPIO_ACTIVE_LOW>;
+		max-bitrate = <8000000>;
+		#phy-cells = <0>;
+	};
+};
+
+&cpu0 {
+	clock-frequency = <DT_FREQ_M(300)>;
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart1_default>;
+	pinctrl-names = "default";
+};
+
+zephyr_udc0: &usbhs {
+	status = "okay";
+};
+
+&can0 {
+	status = "okay";
+	pinctrl-0 = <&can0_default>;
+	pinctrl-names = "default";
+	phys = <&transceiver0>;
+};
+
+&can1 {
+	status = "okay";
+	pinctrl-0 = <&can1_default>;
+	pinctrl-names = "default";
+	phys = <&transceiver1>;
+};
+
+&wdt {
+	status = "okay";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* First half of sector 0 */
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(64)>;
+			read-only;
+		};
+
+		/* From sector 1 to sector 3 (included) */
+		slot0_partition: partition@20000 {
+			label = "image-0";
+			reg = <0x00020000 DT_SIZE_K(384)>;
+		};
+
+		/* From sector 4 to sector 6 (included) */
+		slot1_partition: partition@80000 {
+			label = "image-1";
+			reg = <0x00080000 DT_SIZE_K(384)>;
+		};
+
+		/* Sector 7 */
+		storage_partition: partition@e0000 {
+			label = "storage";
+			reg = <0x000e0000 DT_SIZE_K(128)>;
+		};
+	};
+};
diff --git a/boards/others/canbardo/canbardo.yaml b/boards/others/canbardo/canbardo.yaml
new file mode 100644
index 00000000000..fab283bb573
--- /dev/null
+++ b/boards/others/canbardo/canbardo.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2024-2025 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: canbardo/same70n20b
+name: CANbardo
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+flash: 1024
+ram: 384
+supported:
+  - can
+  - gpio
+  - usb
+  - usb_device
+vendor: others
diff --git a/boards/others/canbardo/canbardo_defconfig b/boards/others/canbardo/canbardo_defconfig
new file mode 100644
index 00000000000..72c0c1bffff
--- /dev/null
+++ b/boards/others/canbardo/canbardo_defconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2024-2025 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARM_MPU=y
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_HW_STACK_PROTECTION=y
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_WDT_DISABLE_AT_BOOT=y
diff --git a/boards/others/canbardo/doc/canbardo.webp b/boards/others/canbardo/doc/canbardo.webp
new file mode 100644
index 00000000000..48ec7164061
Binary files /dev/null and b/boards/others/canbardo/doc/canbardo.webp differ
diff --git a/boards/others/canbardo/doc/index.rst b/boards/others/canbardo/doc/index.rst
new file mode 100644
index 00000000000..dfbb1b7f050
--- /dev/null
+++ b/boards/others/canbardo/doc/index.rst
@@ -0,0 +1,44 @@
+.. zephyr:board:: canbardo
+
+Overview
+********
+
+CANbardo is an open hardware Universal Serial Bus (USB) to Controller Area Network (CAN) adapter
+board. It is designed to be compatible with the open source :ref:`external_module_cannectivity`.
+
+Hardware
+********
+
+The CANbardo board is equipped with an Atmel SAME70N20B microcontroller and features an USB-C
+connector (high-speed USB 2.0), two DB-9M connectors for CAN FD (up to 8 Mbit/s), a number of status
+LEDs, and a push button. Schematics and component placement drawings are available in the `CANbardo
+GitHub repository`_.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+System Clock
+============
+
+The SAME70N20B is driven by a 12 MHz crystal and configured to provide a system clock of 300
+MHz. The two CAN FD controllers have a core clock frequency of 80 MHz.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Here is an example for the :zephyr:code-sample:`blinky` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: canbardo
+   :Goals: flash
+
+.. _CANbardo GitHub repository:
+   https://github.com/CANbardo/canbardo
diff --git a/boards/others/candlelight/doc/index.rst b/boards/others/candlelight/doc/index.rst
index ac61b2a5eed..c81e927acaf 100644
--- a/boards/others/candlelight/doc/index.rst
+++ b/boards/others/candlelight/doc/index.rst
@@ -16,28 +16,7 @@ are available in the `candleLight GitHub repository`_.
 Supported Features
 ==================
 
-The ``candlelight`` board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB                                 |
-+-----------+------------+-------------------------------------+
-| CAN1      | on-chip    | CAN controller                      |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/others/candlelight/candlelight_defconfig`.
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 System Clock
 ============
@@ -48,6 +27,8 @@ configured to provide a system clock of 48 MHz.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
diff --git a/boards/others/candlelightfd/doc/index.rst b/boards/others/candlelightfd/doc/index.rst
index ea622f4db72..935969ee37a 100644
--- a/boards/others/candlelightfd/doc/index.rst
+++ b/boards/others/candlelightfd/doc/index.rst
@@ -16,28 +16,7 @@ are available in the `candleLight FD GitHub repository`_.
 Supported Features
 ==================
 
-The ``candlelightfd/stm32g0b1xx`` board target supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB                                 |
-+-----------+------------+-------------------------------------+
-| CAN1      | on-chip    | CAN controller                      |
-+-----------+------------+-------------------------------------+
-| CAN2      | on-chip    | CAN controller                      |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/others/candlelightfd/candlelightfd_stm32g0b1xx_defconfig`.
+.. zephyr:board-supported-hw::
 
 System Clock
 ============
@@ -49,6 +28,8 @@ clock of 80 MHz.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
diff --git a/boards/others/esp32c3_supermini/doc/index.rst b/boards/others/esp32c3_supermini/doc/index.rst
index 7a7ff21dbd1..234129ef32c 100644
--- a/boards/others/esp32c3_supermini/doc/index.rst
+++ b/boards/others/esp32c3_supermini/doc/index.rst
@@ -40,41 +40,7 @@ manual at `ESP32-C3 Technical Reference Manual`_.
 Supported Features
 ==================
 
-Currently Zephyr's ``esp32c3_supermini`` board target supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| SPI DMA    | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| TWAI       | on-chip    | can                                 |
-+------------+------------+-------------------------------------+
-| USB-CDC    | on-chip    | serial                              |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | adc                                 |
-+------------+------------+-------------------------------------+
-| Wi-Fi      | on-chip    |                                     |
-+------------+------------+-------------------------------------+
-| Bluetooth  | on-chip    |                                     |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 System requirements
 *******************
@@ -96,6 +62,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/others/esp32c3_supermini/esp32c3_supermini.dts b/boards/others/esp32c3_supermini/esp32c3_supermini.dts
index ebbd64d4f81..317494ca200 100644
--- a/boards/others/esp32c3_supermini/esp32c3_supermini.dts
+++ b/boards/others/esp32c3_supermini/esp32c3_supermini.dts
@@ -16,7 +16,7 @@
 	compatible = "espressif,esp32c3_supermini";
 
 	chosen {
-		zephyr,sram = &sram0;
+		zephyr,sram = &sram1;
 		zephyr,console = &usb_serial;
 		zephyr,shell-uart = &usb_serial;
 		zephyr,flash = &flash0;
@@ -89,3 +89,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/others/esp32c3_supermini/esp32c3_supermini_defconfig b/boards/others/esp32c3_supermini/esp32c3_supermini_defconfig
index bf6c07714fa..c5ef331aa76 100644
--- a/boards/others/esp32c3_supermini/esp32c3_supermini_defconfig
+++ b/boards/others/esp32c3_supermini/esp32c3_supermini_defconfig
@@ -1,8 +1,6 @@
 # Copyright (c) 2024 Arrel Neumiller
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/others/icev_wireless/doc/index.rst b/boards/others/icev_wireless/doc/index.rst
index 91c4ee1ff98..f9168a14890 100644
--- a/boards/others/icev_wireless/doc/index.rst
+++ b/boards/others/icev_wireless/doc/index.rst
@@ -28,32 +28,7 @@ For details on iCE40 hardware please refer to the following resources:
 Supported Features
 ==================
 
-The ICE-V Wireless board configuration supports the following hardware
-features:
-
-+-----------+------------+------------------+
-| Interface | Controller | Driver/Component |
-+===========+============+==================+
-| PMP       | on-chip    | arch/riscv       |
-+-----------+------------+------------------+
-| INTMTRX   | on-chip    | intc_esp32c3     |
-+-----------+------------+------------------+
-| PINMUX    | on-chip    | pinctrl_esp32    |
-+-----------+------------+------------------+
-| USB UART  | on-chip    | serial_esp32_usb |
-+-----------+------------+------------------+
-| GPIO      | on-chip    | gpio_esp32       |
-+-----------+------------+------------------+
-| UART      | on-chip    | uart_esp32       |
-+-----------+------------+------------------+
-| I2C       | on-chip    | i2c_esp32        |
-+-----------+------------+------------------+
-| SPI       | on-chip    | spi_esp32_spim   |
-+-----------+------------+------------------+
-| ADC       | on-chip    |                  |
-+-----------+------------+------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -83,6 +58,8 @@ below.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Programming and debugging for the ICE-V Wireless ESP32-C3 target is
 incredibly easy 🎉 following the steps below.
 
diff --git a/boards/others/icev_wireless/icev_wireless.dts b/boards/others/icev_wireless/icev_wireless.dts
index b91814c3b43..3c0e725fe53 100644
--- a/boards/others/icev_wireless/icev_wireless.dts
+++ b/boards/others/icev_wireless/icev_wireless.dts
@@ -97,3 +97,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/others/icev_wireless/icev_wireless_defconfig b/boards/others/icev_wireless/icev_wireless_defconfig
index ef633ce56a1..187793c76e8 100644
--- a/boards/others/icev_wireless/icev_wireless_defconfig
+++ b/boards/others/icev_wireless/icev_wireless_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/others/neorv32/CMakeLists.txt b/boards/others/neorv32/CMakeLists.txt
index ef15ed3fcc5..40e809dfb70 100644
--- a/boards/others/neorv32/CMakeLists.txt
+++ b/boards/others/neorv32/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
+# Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
 # SPDX-License-Identifier: Apache-2.0
 
 if((CONFIG_BOARD_NEORV32) AND (CONFIG_BUILD_OUTPUT_BIN))
@@ -18,7 +18,7 @@ if((CONFIG_BOARD_NEORV32) AND (CONFIG_BUILD_OUTPUT_BIN))
 
     set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
       COMMAND ${IMAGE_GEN}
-      ARGS -app_img
+      ARGS -app_vhd
       ${CONFIG_KERNEL_BIN_NAME}.bin
       ${CONFIG_KERNEL_BIN_NAME}.vhd
       ${PROJECT_BINARY_DIR}
diff --git a/boards/others/neorv32/Kconfig b/boards/others/neorv32/Kconfig
index 57e0edc10d6..038c6c6cc86 100644
--- a/boards/others/neorv32/Kconfig
+++ b/boards/others/neorv32/Kconfig
@@ -1,5 +1,19 @@
-# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
+# Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
 # SPDX-License-Identifier: Apache-2.0
 
+if BOARD_NEORV32_NEORV32_MINIMALBOOT
+
+config BOARD_NEORV32
+	select RISCV_ISA_RV32I
+	select ATOMIC_OPERATIONS_C
+
+endif # BOARD_NEORV32_NEORV32_MINIMALBOOT
+
+if BOARD_NEORV32_NEORV32_UP5KDEMO
+
 config BOARD_NEORV32
-	select SOC_NEORV32_V1_8_6 if "$(BOARD_REVISION)" = "1.8.6"
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select ATOMIC_OPERATIONS_C
+
+endif # BOARD_NEORV32_NEORV32_UP5KDEMO
diff --git a/boards/others/neorv32/board.cmake b/boards/others/neorv32/board.cmake
index b5088e8677e..56bb9fc1a38 100644
--- a/boards/others/neorv32/board.cmake
+++ b/boards/others/neorv32/board.cmake
@@ -1,5 +1,10 @@
-# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
+# Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
 # SPDX-License-Identifier: Apache-2.0
 
 board_runner_args(openocd "--use-elf" "--cmd-reset-halt" "halt")
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+
+if("${BOARD_QUALIFIERS}" STREQUAL "/neorv32")
+  message(FATAL_ERROR "Please specify a variant for the neorv32 board "
+                      "(e.g. neorv32/neorv32/minimalboot or neorv32/neorv32/up5kdemo)")
+endif()
diff --git a/boards/others/neorv32/board.yml b/boards/others/neorv32/board.yml
index 9154d90e8a9..2c3c6552cd8 100644
--- a/boards/others/neorv32/board.yml
+++ b/boards/others/neorv32/board.yml
@@ -2,10 +2,8 @@ board:
   name: neorv32
   full_name: NEORV32
   vendor: others
-  revision:
-    format: major.minor.patch
-    default: "1.8.6"
-    revisions:
-      - name: "1.8.6"
   socs:
     - name: neorv32
+      variants:
+        - name: "minimalboot"
+        - name: "up5kdemo"
diff --git a/boards/others/neorv32/doc/index.rst b/boards/others/neorv32/doc/index.rst
index 066377bbf25..d9a76304c15 100644
--- a/boards/others/neorv32/doc/index.rst
+++ b/boards/others/neorv32/doc/index.rst
@@ -13,91 +13,102 @@ For more information about the NEORV32, see the following websites:
 - `The NEORV32 RISC-V Processor Datasheet`_
 - `The NEORV32 RISC-V Processor User Guide`_
 
-The currently supported version is 1.8.6.
+The currently supported version is NEORV32 v1.11.2.
+
+Supported Board Targets
+=======================
+
+The following NEORV32 board targets are supported by Zephyr:
+
+- ``neorv32/neorv32/minimalboot``
+- ``neorv32/neorv32/up5kdemo``
+
+Each of these match one of the NEORV32 processor templates provided alongside the NEORV32 RTL.
+These board targets can be customized out-of-tree to match custom NEORV32 implementations using
+:ref:`board extensions <extend-board>` or :ref:`devicetree overlays <use-dt-overlays>`.
+
+.. zephyr:board-supported-hw::
 
 Supported Features
-==================
+******************
 
-The ``neorv32`` board configuration can be used a generic definition for NEORV32
-based boards. Customisation to fit custom NEORV32 implementations can be done
-using :ref:`devicetree overlays <use-dt-overlays>`.
-
-Zephyr currently supports the following hardware features of the NEORV32
-Processor (SoC):
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| INTC      | on-chip    | interrupt controller                |
-+-----------+------------+-------------------------------------+
-| MTIME     | on-chip    | system timer                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio, non-interrupt                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-
-The default board configuration for the NEORV32 Processor (SoC) can be found in
-the defconfig file: :file:`boards/riscv/neorv32/neorv32_defconfig`.
+The following NEORV32 features are supported by Zephyr. These are pre-configured for the supported
+board targets, but can be customized to match custom NEORV32 implementations.
 
 System Clock
 ============
 
-The default board configuration assumes a system clock of 100 MHz. The clock
-frequency can be overridden by changing the ``clock-frequency`` property of the
-``cpu0`` devicetree node.
+The default board configuration reads the system clock frequency from the NEORV32 SYSINFO module,
+which results in a small run-time overhead. If the clock frequency is known at build time, this
+behavior can be overridden by setting the ``clock-frequency`` property of the ``cpu0`` devicetree
+node.
 
 CPU
 ===
 
-The default board configuration assumes the NEORV32 CPU implementation has the
-following RISC-V ISA extensions enabled:
+The SoC configuration assumes the NEORV32 CPU implementation has the following RISC-V ISA extensions
+enabled:
 
-- C (Compresses Instructions)
-- M (Integer Multiplication and Division)
-- Zicsr (Control and Status Register (CSR) Instructions)
+- Zicntr (Extension for Base Counters and Timers)
+- Zicsr (Control and Status Register (CSR) Instructions, always enabled)
+- Zifencei (Instruction-fetch fence, always enabled)
+
+Other supported RISC-V ISA extensions must be enabled via Kconfig on the board level, and the
+``riscv,isa`` devicetree property of the ``cpu0`` node must be set accordingly.
+
+Core Local Interruptor
+======================
+
+The NEORV32 Core Local Interruptor (CLINT) and its machine timer (MTIMER) are supported but disabled
+by default. For NEORV32 SoC implementations supporting these, support can be enabled by setting
+the ``status`` properties of the ``clint`` and ``mtimer`` devicetree node to ``okay``.
 
 Internal Instruction Memory
 ===========================
 
-The default board configuration assumes the NEORV32 SoC implementation has a 64k
-byte internal instruction memory (IMEM) for code execution. The size of the
-instruction memory can be overridden by changing the ``reg`` property of the
-``imem`` devicetree node.
+The internal instruction memory (IMEM) for code execution is supported but disabled by default. For
+NEORV32 SoC implementations supporting IMEM, support can be enabled by setting the size via the
+``reg`` property of the ``imem`` devicetree node and setting its ``status`` property to ``okay``.
 
 Internal Data Memory
 ====================
 
-The default board configuration assumes the NEORV32 SoC implementation has a 32k
-byte internal data memory (DMEM). The size of the data memory can be overridden
-by changing the ``reg`` property of the ``dmem`` devicetree node.
+The internal data memory (DMEM) is supported but disabled by default. For NEORV32 SoC
+implementations supporting DMEM, support can be enabled by setting the size via the ``reg`` property
+of the ``dmem`` devicetree node and setting its ``status`` property to ``okay``.
 
 Serial Port
 ===========
 
-The default configuration assumes the NEORV32 SoC implements UART0 for use as
-system console.
+The NEORV32 serial ports (UART0 and UART1) are supported but disabled by default. For NEORV32 SoC
+implementations supporting either of the UARTs, support can be enabled by setting the ``status``
+properties of the ``uart0`` and/or ``uart1`` devicetree node to ``okay``.
 
 .. note::
+   The board targets provide a console on UART0 with a baud rate of 19200 to match that of the
+   standard NEORV32 bootloader. The baudrate can be changed by modifying the ``current-speed``
+   property of the ``uart0`` devicetree node.
 
-   The default configuration uses a baud rate of 19200 to match that of the
-   standard NEORV32 bootloader. The baudrate can be changed by modifying the
-   ``current-speed`` property of the ``uart0`` devicetree node.
+General Purpose Input/Output
+============================
+
+The NEORV32 GPIO port is supported but disabled by default. For NEORV32 SoC implementations
+supporting the GPIOs, support can be enabled by setting the ``status`` property of the ``gpio``
+devicetree node to ``okay``. The number of supported GPIOs can be set via the ``ngpios`` devicetree
+property.
 
 True Random-Number Generator
 ============================
 
-The True Random-Number Generator (TRNG) of the NEORV32 is supported, but
-disabled by default. For NEORV32 SoC implementations supporting the TRNG,
-support can be enabled by setting the ``status`` property of the ``trng``
-devicetree node to ``okay``.
+The True Random-Number Generator (TRNG) of the NEORV32 is supported, but disabled by default. For
+NEORV32 SoC implementations supporting the TRNG, support can be enabled by setting the ``status``
+property of the ``trng`` devicetree node to ``okay``.
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 First, configure the FPGA with the NEORV32 bitstream as described in the NEORV32
 user guide.
 
@@ -129,26 +140,26 @@ implementation with the On-Chip Debugger (OCD) and bootloader enabled.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: neorv32
+   :board: neorv32/neorv32/<variant>
    :goals: flash
 
 The default board configuration uses an :ref:`openocd-debug-host-tools`
 configuration similar to the example provided by the NEORV32 project. Other
-JTAGs can be used by providing further arguments when building. Here is an
-example for using the Flyswatter JTAG:
+JTAGs can be used by providing further arguments when flashing. Here is an
+example for using the Flyswatter JTAG @ 2 kHz:
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: neorv32
+   :board: neorv32/neorv32/<variant>
    :goals: flash
-   :gen-args: -DBOARD_RUNNER_ARGS_openocd="--config;interface/ftdi/flyswatter.cfg;--config;neorv32.cfg;--cmd-pre-init;'adapter speed 2000'"
+   :flash-args: --config interface/ftdi/flyswatter.cfg --config neorv32.cfg --cmd-pre-init 'adapter speed 2000'
 
 After flashing, you should see message similar to the following in the terminal:
 
 .. code-block:: console
 
    *** Booting Zephyr OS build zephyr-vn.n.nn  ***
-   Hello World! neorv32
+   Hello World! neorv32/neorv32/<variant>
 
 Note, however, that the application was not persisted in flash memory by the
 above steps. It was merely written to internal block RAM in the FPGA. It will
@@ -167,7 +178,7 @@ can be passed at build time:
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: neorv32
+   :board: neorv32/neorv32/<variant>
    :goals: build
    :gen-args: -DCMAKE_PROGRAM_PATH=<path/to/neorv32/sw/image_gen/>
 
@@ -186,7 +197,7 @@ Here is an example for the :zephyr:code-sample:`hello_world` application.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: neorv32
+   :board: neorv32/neorv32/<variant>
    :goals: debug
 
 Step through the application in your debugger, and you should see a message
@@ -195,7 +206,7 @@ similar to the following in the terminal:
 .. code-block:: console
 
    *** Booting Zephyr OS build zephyr-vn.n.nn  ***
-   Hello World! neorv32
+   Hello World! neorv32/neorv32/<variant>
 
 .. _The NEORV32 RISC-V Processor GitHub:
    https://github.com/stnolting/neorv32
diff --git a/boards/others/neorv32/doc/neorv32.png b/boards/others/neorv32/doc/neorv32.png
new file mode 100644
index 00000000000..8bf84fd9529
Binary files /dev/null and b/boards/others/neorv32/doc/neorv32.png differ
diff --git a/boards/others/neorv32/neorv32.dts b/boards/others/neorv32/neorv32.dts
deleted file mode 100644
index ec78e301fb0..00000000000
--- a/boards/others/neorv32/neorv32.dts
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/dts-v1/;
-
-#include <neorv32.dtsi>
-#include <freq.h>
-#include <mem.h>
-
-/ {
-	model = "NEORV32";
-	compatible = "neorv32";
-
-	aliases {
-		led0 = &led0;
-		led1 = &led1;
-		led2 = &led2;
-		led3 = &led3;
-	};
-
-	chosen {
-		zephyr,flash = &imem;
-		zephyr,sram = &dmem;
-		zephyr,console = &uart0;
-		zephyr,shell-uart = &uart0;
-		zephyr,uart-pipe = &uart0;
-	};
-
-	soc {
-		imem: memory@0 {
-			compatible = "soc-nv-flash", "mmio-sram";
-			reg = <0x0 DT_SIZE_K(64)>;
-		};
-
-		bootrom: memory@ffff0000 {
-			compatible = "soc-nv-flash", "mmio-sram";
-			reg = <0xffff0000 DT_SIZE_K(4)>;
-		};
-
-		dmem: memory@80000000 {
-			compatible = "mmio-sram";
-			reg = <0x80000000 DT_SIZE_K(32)>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		led0: led0 {
-			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
-			label = "LED_0";
-		};
-
-		led1: led1 {
-			gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
-			label = "LED_1";
-		};
-
-		led2: led2 {
-			gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
-			label = "LED_2";
-		};
-
-		led3: led3 {
-			gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
-			label = "LED_3";
-		};
-	};
-};
-
-&cpu0 {
-	clock-frequency = <DT_FREQ_M(100)>;
-};
-
-&uart0 {
-	status = "okay";
-	current-speed = <19200>;
-};
-
-&gpio_lo {
-	status = "okay";
-};
-
-&gpio_hi {
-	status = "okay";
-};
diff --git a/boards/others/neorv32/neorv32.yaml b/boards/others/neorv32/neorv32.yaml
deleted file mode 100644
index 15c1dd875e8..00000000000
--- a/boards/others/neorv32/neorv32.yaml
+++ /dev/null
@@ -1,11 +0,0 @@
-identifier: neorv32
-name: NEORV32 Processor (SoC)
-type: mcu
-arch: riscv
-toolchain:
-  - cross-compile
-  - zephyr
-ram: 32
-flash: 64
-supported:
-  - gpio
diff --git a/boards/others/neorv32/neorv32_defconfig b/boards/others/neorv32/neorv32_defconfig
deleted file mode 100644
index 2642d046b50..00000000000
--- a/boards/others/neorv32/neorv32_defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_SOC_NEORV32_ISA_C=y
-CONFIG_SERIAL=y
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-CONFIG_UART_INTERRUPT_DRIVEN=y
-CONFIG_GPIO=y
diff --git a/boards/others/neorv32/neorv32_neorv32_minimalboot.dts b/boards/others/neorv32/neorv32_neorv32_minimalboot.dts
new file mode 100644
index 00000000000..8fd995f5c9b
--- /dev/null
+++ b/boards/others/neorv32/neorv32_neorv32_minimalboot.dts
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2025 Henrik Brix Andersen <henrik@brixandersen.dk>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <neorv32.dtsi>
+#include <mem.h>
+
+/ {
+	model = "NEORV32 MinimalBoot";
+	compatible = "neorv32";
+
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		led2 = &led2;
+		led3 = &led3;
+	};
+
+	chosen {
+		zephyr,flash = &imem;
+		zephyr,sram = &dmem;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,uart-pipe = &uart0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led0 {
+			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
+			label = "LED_0";
+		};
+
+		led1: led1 {
+			gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+			label = "LED_1";
+		};
+
+		led2: led2 {
+			gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
+			label = "LED_2";
+		};
+
+		led3: led3 {
+			gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
+			label = "LED_3";
+		};
+	};
+};
+
+&cpu0 {
+	riscv,isa = "rv32i_zicsr_zifencei";
+};
+
+&bootrom {
+	status = "okay";
+};
+
+&imem {
+	status = "okay";
+	reg = <0x0 DT_SIZE_K(64)>;
+};
+
+&dmem {
+	status = "okay";
+	reg = <0x80000000 DT_SIZE_K(64)>;
+};
+
+&clint {
+	status = "okay";
+};
+
+&mtimer {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <19200>;
+};
+
+&gpio {
+	status = "okay";
+	ngpios = <4>;
+};
diff --git a/boards/others/neorv32/neorv32_neorv32_minimalboot.yaml b/boards/others/neorv32/neorv32_neorv32_minimalboot.yaml
new file mode 100644
index 00000000000..88b24248d22
--- /dev/null
+++ b/boards/others/neorv32/neorv32_neorv32_minimalboot.yaml
@@ -0,0 +1,11 @@
+identifier: neorv32/neorv32/minimalboot
+name: NEORV32 MinimalBoot
+type: mcu
+arch: riscv
+toolchain:
+  - cross-compile
+  - zephyr
+ram: 64
+flash: 64
+supported:
+  - gpio
diff --git a/boards/others/neorv32/neorv32_neorv32_minimalboot_defconfig b/boards/others/neorv32/neorv32_neorv32_minimalboot_defconfig
new file mode 100644
index 00000000000..146b34dfc02
--- /dev/null
+++ b/boards/others/neorv32/neorv32_neorv32_minimalboot_defconfig
@@ -0,0 +1,7 @@
+# Copyright (c) 2025 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
diff --git a/boards/others/neorv32/neorv32_neorv32_up5kdemo.dts b/boards/others/neorv32/neorv32_neorv32_up5kdemo.dts
new file mode 100644
index 00000000000..43046f9398e
--- /dev/null
+++ b/boards/others/neorv32/neorv32_neorv32_up5kdemo.dts
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <neorv32.dtsi>
+#include <mem.h>
+
+/ {
+	model = "NEORV32 UP5KDemo";
+	compatible = "neorv32";
+
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		led2 = &led2;
+		led3 = &led3;
+	};
+
+	chosen {
+		zephyr,flash = &imem;
+		zephyr,sram = &dmem;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,uart-pipe = &uart0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led0 {
+			gpios = <&gpio 0 GPIO_ACTIVE_HIGH>;
+			label = "LED_0";
+		};
+
+		led1: led1 {
+			gpios = <&gpio 1 GPIO_ACTIVE_HIGH>;
+			label = "LED_1";
+		};
+
+		led2: led2 {
+			gpios = <&gpio 2 GPIO_ACTIVE_HIGH>;
+			label = "LED_2";
+		};
+
+		led3: led3 {
+			gpios = <&gpio 3 GPIO_ACTIVE_HIGH>;
+			label = "LED_3";
+		};
+	};
+};
+
+&cpu0 {
+	riscv,isa = "rv32im_zicsr_zifencei";
+};
+
+&bootrom {
+	status = "okay";
+};
+
+&imem {
+	status = "okay";
+	reg = <0x0 DT_SIZE_K(64)>;
+};
+
+&dmem {
+	status = "okay";
+	reg = <0x80000000 DT_SIZE_K(64)>;
+};
+
+&clint {
+	status = "okay";
+};
+
+&mtimer {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <19200>;
+};
+
+&gpio {
+	status = "okay";
+	ngpios = <32>;
+};
diff --git a/boards/others/neorv32/neorv32_neorv32_up5kdemo.yaml b/boards/others/neorv32/neorv32_neorv32_up5kdemo.yaml
new file mode 100644
index 00000000000..273e702c57a
--- /dev/null
+++ b/boards/others/neorv32/neorv32_neorv32_up5kdemo.yaml
@@ -0,0 +1,11 @@
+identifier: neorv32/neorv32/up5kdemo
+name: NEORV32 UP5KDemo
+type: mcu
+arch: riscv
+toolchain:
+  - cross-compile
+  - zephyr
+ram: 64
+flash: 64
+supported:
+  - gpio
diff --git a/boards/others/neorv32/neorv32_neorv32_up5kdemo_defconfig b/boards/others/neorv32/neorv32_neorv32_up5kdemo_defconfig
new file mode 100644
index 00000000000..e8abbc77864
--- /dev/null
+++ b/boards/others/neorv32/neorv32_neorv32_up5kdemo_defconfig
@@ -0,0 +1,7 @@
+# Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
diff --git a/boards/others/neorv32/support/openocd.cfg b/boards/others/neorv32/support/openocd.cfg
index a857c8ba7c1..fc7e7462559 100644
--- a/boards/others/neorv32/support/openocd.cfg
+++ b/boards/others/neorv32/support/openocd.cfg
@@ -1,17 +1,15 @@
-# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
+# Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
 # SPDX-License-Identifier: Apache-2.0
 
 adapter driver ftdi
-ftdi_vid_pid 0x0403 0x6010
-ftdi_channel 0
+adapter speed 1000
 
 if { [info exists _ZEPHYR_BOARD_SERIAL] } {
-    ftdi_serial $_ZEPHYR_BOARD_SERIAL
+    adapter serial $_ZEPHYR_BOARD_SERIAL
 }
 
-ftdi_layout_init 0x0038 0x003b
-
-adapter speed 1000
-ftdi_layout_signal nTRST -ndata 0x0010 -noe 0x0040
+ftdi vid_pid 0x0403 0x6010
+ftdi channel 0
+ftdi layout_init 0x0038 0x003b
 
 source [find neorv32.cfg]
diff --git a/boards/others/promicro_nrf52840/Kconfig.defconfig b/boards/others/promicro_nrf52840/Kconfig.defconfig
index 85e9768bccc..58880f52c9e 100644
--- a/boards/others/promicro_nrf52840/Kconfig.defconfig
+++ b/boards/others/promicro_nrf52840/Kconfig.defconfig
@@ -23,7 +23,4 @@ config FLASH_LOAD_OFFSET
 	default 0x1000
 	depends on BOARD_HAS_NRF5_BOOTLOADER && (MCUBOOT || !USE_DT_CODE_PARTITION)
 
-config BT_CTLR
-	default BT
-
 endif # BOARD_PROMICRO_NRF52840
diff --git a/boards/others/promicro_nrf52840/doc/index.rst b/boards/others/promicro_nrf52840/doc/index.rst
index 857644d03d5..de0f284d63a 100644
--- a/boards/others/promicro_nrf52840/doc/index.rst
+++ b/boards/others/promicro_nrf52840/doc/index.rst
@@ -1,7 +1,4 @@
-.. _promicro_nrf52840_nrf52840:
-
-Pro Micro nRF52840
-##################
+.. zephyr:board:: promicro_nrf52840
 
 More of a board type than a unique board, It is based on Nice!Nano.
 Also referred to as Pro Micro, Promicro, SuperMini nRF52840 boards.
@@ -27,12 +24,6 @@ Semiconductor nRF52840 ARM Cortex-M4F CPU and the following devices:
 * :abbr:`USB (Universal Serial Bus)`
 * :abbr:`WDT (Watchdog Timer)`
 
-.. figure:: img/others_promicro_nrf52840.webp
-     :align: center
-     :alt: Tenstar Pro Micro nRF52840
-
-     Tenstar Pro Micro nRF5284
-
 More information about the original board can be found at the
 `Nice!Nano website`_.
 
@@ -44,41 +35,7 @@ Pinout and Schematic are available in the `Nice!Nano Documentation`_
 Supported Features
 ==================
 
-The ``promicro_nrf52840/nrf52840`` board target supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -91,6 +48,8 @@ LED
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``promicro_nrf52840/nrf52840`` board target can be
 built in the usual way (see :ref:`build_an_application` for more details).
 
diff --git a/boards/others/promicro_nrf52840/promicro_nrf52840-pinctrl.dtsi b/boards/others/promicro_nrf52840/promicro_nrf52840-pinctrl.dtsi
index d4e61141803..65e941475e0 100644
--- a/boards/others/promicro_nrf52840/promicro_nrf52840-pinctrl.dtsi
+++ b/boards/others/promicro_nrf52840/promicro_nrf52840-pinctrl.dtsi
@@ -68,13 +68,13 @@
 
 	pwm0_default: pwm0_default {
 		group1 {
-			psels = <NRF_PSEL(PWM_OUT0, 0, 17)>;
+			psels = <NRF_PSEL(PWM_OUT0, 0, 15)>;
 		};
 	};
 
 	pwm0_sleep: pwm0_sleep {
 		group1 {
-			psels = <NRF_PSEL(PWM_OUT0, 0, 17)>;
+			psels = <NRF_PSEL(PWM_OUT0, 0, 15)>;
 			low-power-enable;
 		};
 	};
diff --git a/boards/others/promicro_nrf52840/promicro_nrf52840.yaml b/boards/others/promicro_nrf52840/promicro_nrf52840.yaml
index 35afde899eb..0f8ccd9b1a2 100644
--- a/boards/others/promicro_nrf52840/promicro_nrf52840.yaml
+++ b/boards/others/promicro_nrf52840/promicro_nrf52840.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - usb_device
diff --git a/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_uf2.yaml b/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_uf2.yaml
index 6d1862dbad6..7aa472b784d 100644
--- a/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_uf2.yaml
+++ b/boards/others/promicro_nrf52840/promicro_nrf52840_nrf52840_uf2.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - usb_device
diff --git a/boards/others/serpente/doc/index.rst b/boards/others/serpente/doc/index.rst
index 0894427ff3e..3872360dabc 100644
--- a/boards/others/serpente/doc/index.rst
+++ b/boards/others/serpente/doc/index.rst
@@ -21,35 +21,7 @@ Hardware
 Supported Features
 ==================
 
-The Serpente board configuration supports the
-following hardware features:
-
-+-----------+------------+------------------------------------------+
-| Interface | Controller | Driver/Component                         |
-+===========+============+==========================================+
-| NVIC      | on-chip    | nested vector interrupt controller       |
-+-----------+------------+------------------------------------------+
-| Flash     | on-chip    | Can be used with LittleFS to store files |
-+-----------+------------+------------------------------------------+
-| SYSTICK   | on-chip    | systick                                  |
-+-----------+------------+------------------------------------------+
-| WDT       | on-chip    | Watchdog                                 |
-+-----------+------------+------------------------------------------+
-| GPIO      | on-chip    | I/O ports                                |
-+-----------+------------+------------------------------------------+
-| PWM       | on-chip    | Pulse Width Modulation                   |
-+-----------+------------+------------------------------------------+
-| USART     | on-chip    | Serial ports                             |
-+-----------+------------+------------------------------------------+
-| SPI       | on-chip    | Serial Peripheral Interface ports        |
-+-----------+------------+------------------------------------------+
-| USB       | on-chip    | USB device                               |
-+-----------+------------+------------------------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig file
-:zephyr_file:`boards/others/serpente/serpente_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -74,6 +46,8 @@ to the host PC.
 Programming and Debugging
 =========================
 
+.. zephyr:board-supported-runners::
+
 The Serpente ships the BOSSA compatible UF2 bootloader. The bootloader
 can be entered by quickly tapping the reset button twice.
 
diff --git a/boards/others/serpente/serpente.yaml b/boards/others/serpente/serpente.yaml
index 7d3c1e68e58..438093aa072 100644
--- a/boards/others/serpente/serpente.yaml
+++ b/boards/others/serpente/serpente.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 flash: 256
 ram: 32
 supported:
diff --git a/boards/others/stm32_min_dev/doc/index.rst b/boards/others/stm32_min_dev/doc/index.rst
index 29d5a75b27e..8f37502cc01 100644
--- a/boards/others/stm32_min_dev/doc/index.rst
+++ b/boards/others/stm32_min_dev/doc/index.rst
@@ -81,32 +81,7 @@ respectively.
 Supported Features
 ==================
 
-The stm32_min_dev board configuration supports the following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| NVIC      | on-chip    | nested vectored      |
-|           |            | interrupt controller |
-+-----------+------------+----------------------+
-| SYSTICK   | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial port          |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| USB       | on-chip    | USB device           |
-+-----------+------------+----------------------+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -145,6 +120,8 @@ variants respectively.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``stm32_min_dev@(blue|black)`` board configuration can be
 built and flashed in the usual way (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/others/stm32_min_dev/twister.yaml b/boards/others/stm32_min_dev/twister.yaml
index bcb30a9fdd0..19a0fa99723 100644
--- a/boards/others/stm32_min_dev/twister.yaml
+++ b/boards/others/stm32_min_dev/twister.yaml
@@ -3,7 +3,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 20
 supported:
   - i2c
diff --git a/boards/others/stm32f030_demo/doc/index.rst b/boards/others/stm32f030_demo/doc/index.rst
index 84d619b38b0..751465ebf81 100644
--- a/boards/others/stm32f030_demo/doc/index.rst
+++ b/boards/others/stm32f030_demo/doc/index.rst
@@ -31,29 +31,7 @@ Hardware
 Supported Features
 ==================
 
-The Zephyr stm32f030_demo board configuration supports the following
-hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr porting.
-
-The default configuration can be found in
-:zephyr_file:`boards/others/stm32f030_demo/stm32f030_demo_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -67,6 +45,8 @@ Default Zephyr Peripheral Mapping:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``stm32f030_demo`` board configuration can be built and
 flashed in the usual way (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/others/stm32f030_demo/stm32f030_demo.yaml b/boards/others/stm32f030_demo/stm32f030_demo.yaml
index 4a847323445..e327b7fb769 100644
--- a/boards/others/stm32f030_demo/stm32f030_demo.yaml
+++ b/boards/others/stm32f030_demo/stm32f030_demo.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 4
 flash: 16
 supported:
diff --git a/boards/others/stm32f103_mini/doc/index.rst b/boards/others/stm32f103_mini/doc/index.rst
index 0377a9b5952..f7e5cfc3ffa 100644
--- a/boards/others/stm32f103_mini/doc/index.rst
+++ b/boards/others/stm32f103_mini/doc/index.rst
@@ -42,41 +42,7 @@ More information about STM32F103RC can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32f103_mini board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/others/stm32f103_mini/stm32f103_mini_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -113,6 +79,8 @@ The on-board 8MHz crystal is used to produce a 72MHz system clock with PLL.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``stm32f103_mini`` board configuration can be built and
 flashed in the usual way (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/others/stm32f103_mini/stm32f103_mini.yaml b/boards/others/stm32f103_mini/stm32f103_mini.yaml
index 792145e6a16..8478581eed9 100644
--- a/boards/others/stm32f103_mini/stm32f103_mini.yaml
+++ b/boards/others/stm32f103_mini/stm32f103_mini.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 48
 flash: 256
 supported:
diff --git a/boards/others/stm32f401_mini/doc/index.rst b/boards/others/stm32f401_mini/doc/index.rst
index 5cfa267f712..e007f48c694 100644
--- a/boards/others/stm32f401_mini/doc/index.rst
+++ b/boards/others/stm32f401_mini/doc/index.rst
@@ -35,35 +35,7 @@ hardware components:
 Supported Features
 ==================
 
-The Zephyr stm32f401_mini board configuration supports the following
-hardware features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| NVIC       | on-chip    | nested vector interrupt controller  |
-+------------+------------+-------------------------------------+
-| SYSTICK    | on-chip    | system clock                        |
-+------------+------------+-------------------------------------+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| FLASH      | on-chip    | flash                               |
-+------------+------------+-------------------------------------+
-| SPI        | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| I2C        | on-chip    | i2c                                 |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | ADC Controller                      |
-+------------+------------+-------------------------------------+
-| USB OTG FS | on-chip    | USB device                          |
-+------------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/others/stm32f401_mini/stm32f401_mini_defconfig`
+.. zephyr:board-supported-hw::
 
 Default Zephyr Peripheral Mapping:
 ----------------------------------
@@ -89,6 +61,8 @@ derived from HSE, and is set at 84MHz.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM
 bootloader, and another by using the SWD debug port (which requires additional
 hardware). Flashing using the ROM bootloader requires a special activation
diff --git a/boards/others/stm32f401_mini/stm32f401_mini.yaml b/boards/others/stm32f401_mini/stm32f401_mini.yaml
index ba3cdefd138..a9570bc0ffb 100644
--- a/boards/others/stm32f401_mini/stm32f401_mini.yaml
+++ b/boards/others/stm32f401_mini/stm32f401_mini.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - spi
diff --git a/boards/panasonic/pan1770_evb/doc/index.rst b/boards/panasonic/pan1770_evb/doc/index.rst
index c518d4baa82..f1ba60117ac 100644
--- a/boards/panasonic/pan1770_evb/doc/index.rst
+++ b/boards/panasonic/pan1770_evb/doc/index.rst
@@ -7,7 +7,7 @@ The PAN1770 Evaluation Board is a development tool for the PAN1770 module
 which is based on the nRF52840 chipset from Nordic Semiconductor.
 
 It is basically a clone of the official nRF52840 development kit (PCA10056)
-from Nordic Semiconductor. Please refer to :ref:`nrf52840dk_nrf52840` for
+from Nordic Semiconductor. Please refer to :zephyr:board:`nrf52840dk` for
 further information.
 
 You can find more information about the PAN1770 module and the PAN1770
@@ -42,6 +42,8 @@ The schematics for the PAN1770 Evaluation Board are available in the
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Please use the ``pan1770_evb`` board configuration when
 :ref:`build_an_application` and :ref:`application_run`.
 
diff --git a/boards/panasonic/pan1770_evb/pan1770_evb.yaml b/boards/panasonic/pan1770_evb/pan1770_evb.yaml
index 35ada5617cc..a10c15ea3e1 100644
--- a/boards/panasonic/pan1770_evb/pan1770_evb.yaml
+++ b/boards/panasonic/pan1770_evb/pan1770_evb.yaml
@@ -12,7 +12,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - arduino_gpio
diff --git a/boards/panasonic/pan1780_evb/doc/index.rst b/boards/panasonic/pan1780_evb/doc/index.rst
index aac1ce9bd83..770c2811288 100644
--- a/boards/panasonic/pan1780_evb/doc/index.rst
+++ b/boards/panasonic/pan1780_evb/doc/index.rst
@@ -7,7 +7,7 @@ The PAN1780 Evaluation Board is a development tool for the PAN1780 module which
 is based on the nRF52840 chipset from Nordic Semiconductor.
 
 It is basically a clone of the official nRF52840 development kit (PCA10056)
-from Nordic Semiconductor. Please refer to :ref:`nrf52840dk_nrf52840` for
+from Nordic Semiconductor. Please refer to :zephyr:board:`nrf52840dk` for
 further information.
 
 You can find more information about the PAN1780 module and the PAN1780
@@ -41,6 +41,8 @@ The schematics for the PAN1780 Evaluation Board are available in the
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Please use the ``pan1780_evb`` board configuration when
 :ref:`build_an_application` and :ref:`application_run`.
 
diff --git a/boards/panasonic/pan1780_evb/pan1780_evb.yaml b/boards/panasonic/pan1780_evb/pan1780_evb.yaml
index 8833f01c3a2..65a29e5c75f 100644
--- a/boards/panasonic/pan1780_evb/pan1780_evb.yaml
+++ b/boards/panasonic/pan1780_evb/pan1780_evb.yaml
@@ -12,7 +12,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - arduino_gpio
diff --git a/boards/panasonic/pan1781_evb/doc/index.rst b/boards/panasonic/pan1781_evb/doc/index.rst
index e8dc75b84ec..7f208839f4f 100644
--- a/boards/panasonic/pan1781_evb/doc/index.rst
+++ b/boards/panasonic/pan1781_evb/doc/index.rst
@@ -9,7 +9,7 @@ which is based on the nRF52820 chipset from Nordic Semiconductor.
 You can find more information about the PAN1781 module and the PAN1781
 evaluation board on the `product website`_.
 
-Please also refer to :ref:`nrf52833dk_nrf52820` for general information about
+Please also refer to :zephyr:board:`nrf52833dk` for general information about
 development kits for the nRF52820 from Nordic Semiconductor.
 
 The PAN1781 evaluation board is closely linked to these other evaluation
@@ -40,6 +40,8 @@ The schematics for the PAN1781 Evaluation Board are available in the
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Please use the ``pan1781_evb`` board configuration when
 :ref:`build_an_application` and :ref:`application_run`.
 
diff --git a/boards/panasonic/pan1781_evb/pan1781_evb.yaml b/boards/panasonic/pan1781_evb/pan1781_evb.yaml
index 3061b639c54..5ba7fae607f 100644
--- a/boards/panasonic/pan1781_evb/pan1781_evb.yaml
+++ b/boards/panasonic/pan1781_evb/pan1781_evb.yaml
@@ -12,9 +12,7 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
-  - arduino_gpio
   - arduino_i2c
   - arduino_spi
   - ble
diff --git a/boards/panasonic/pan1782_evb/doc/index.rst b/boards/panasonic/pan1782_evb/doc/index.rst
index eb158172a88..d1385cc26ac 100644
--- a/boards/panasonic/pan1782_evb/doc/index.rst
+++ b/boards/panasonic/pan1782_evb/doc/index.rst
@@ -9,7 +9,7 @@ which is based on the nRF52833 chipset from Nordic Semiconductor.
 You can find more information about the PAN1782 module and the PAN1782
 evaluation board on the `product website`_.
 
-Please also refer to :ref:`nrf52833dk_nrf52833` for general information about
+Please also refer to :zephyr:board:`nrf52833dk` for general information about
 development kits for the nRF52833 from Nordic Semiconductor.
 
 The PAN1782 evaluation board is closely linked to these other evaluation
@@ -40,6 +40,8 @@ The schematics for the PAN1782 Evaluation Board are available in the
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Please use the ``pan1782_evb`` board configuration when
 :ref:`build_an_application` and :ref:`application_run`.
 
diff --git a/boards/panasonic/pan1782_evb/pan1782_evb.yaml b/boards/panasonic/pan1782_evb/pan1782_evb.yaml
index 9e896b97a56..0574926ea72 100644
--- a/boards/panasonic/pan1782_evb/pan1782_evb.yaml
+++ b/boards/panasonic/pan1782_evb/pan1782_evb.yaml
@@ -12,10 +12,8 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
-  - arduino_gpio
   - arduino_i2c
   - arduino_spi
   - usb_device
diff --git a/boards/panasonic/pan1783/doc/index.rst b/boards/panasonic/pan1783/doc/index.rst
index 72759be8d62..3f2a337f47c 100644
--- a/boards/panasonic/pan1783/doc/index.rst
+++ b/boards/panasonic/pan1783/doc/index.rst
@@ -50,6 +50,8 @@ of the `Panasonic Wireless Connectivity Development Hub`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Please use the ``pan1783_evb_cpuapp``, ``pan1783a_evb_cpuapp`` or
 ``pan1783a_pa_evb_cpuapp`` for application core and ``pan1783_evb_cpunet``,
 ``pan1783a_evb_cpunet`` or ``pan1783a_pa_evb_cpunet`` board configuration
diff --git a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.yaml b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.yaml
index 771055b508a..4ed394738f0 100644
--- a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.yaml
+++ b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpuapp.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 448
 flash: 1024
diff --git a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.yaml b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.yaml
index 510ceef5691..586252099df 100644
--- a/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.yaml
+++ b/boards/panasonic/pan1783/pan1783_evb_nrf5340_cpunet.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 64
 flash: 256
diff --git a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.yaml b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.yaml
index 3d9bea54228..9f7fda71c41 100644
--- a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.yaml
+++ b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpuapp.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 448
 flash: 1024
diff --git a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.yaml b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.yaml
index 4904371041c..8a5ee9547e3 100644
--- a/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.yaml
+++ b/boards/panasonic/pan1783/pan1783a_evb_nrf5340_cpunet.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 64
 flash: 256
diff --git a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.yaml b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.yaml
index d9936750286..8279d7aa7c6 100644
--- a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.yaml
+++ b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpuapp.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 448
 flash: 1024
diff --git a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.yaml b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.yaml
index 14ff8c16914..d49319f020d 100644
--- a/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.yaml
+++ b/boards/panasonic/pan1783/pan1783a_pa_evb_nrf5340_cpunet.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 64
 flash: 256
diff --git a/boards/panasonic/panb511evb/Kconfig.defconfig b/boards/panasonic/panb511evb/Kconfig.defconfig
new file mode 100644
index 00000000000..03c84b8f538
--- /dev/null
+++ b/boards/panasonic/panb511evb/Kconfig.defconfig
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_PANB511EVB_NRF54L15_CPUAPP
+
+config ROM_START_OFFSET
+	default 0x800 if BOOTLOADER_MCUBOOT
+
+endif # BOARD_PANB511EVB_NRF54L15_CPUAPP
diff --git a/boards/panasonic/panb511evb/Kconfig.panb511evb b/boards/panasonic/panb511evb/Kconfig.panb511evb
new file mode 100644
index 00000000000..2454aba6270
--- /dev/null
+++ b/boards/panasonic/panb511evb/Kconfig.panb511evb
@@ -0,0 +1,7 @@
+# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_PANB511EVB
+	select SOC_NRF54L15_CPUAPP if BOARD_PANB511EVB_NRF54L15_CPUAPP
+	select SOC_NRF54L15_CPUFLPR if BOARD_PANB511EVB_NRF54L15_CPUFLPR || \
+					    BOARD_PANB511EVB_NRF54L15_CPUFLPR_XIP
diff --git a/boards/panasonic/panb511evb/board.cmake b/boards/panasonic/panb511evb/board.cmake
new file mode 100644
index 00000000000..3138d0b04d7
--- /dev/null
+++ b/boards/panasonic/panb511evb/board.cmake
@@ -0,0 +1,12 @@
+# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_NRF54L15_CPUAPP)
+  board_runner_args(jlink "--device=nRF54L15_M33" "--speed=4000")
+elseif(CONFIG_SOC_NRF54L15_CPUFLPR)
+  set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54l15_cpuflpr.JLinkScript)
+  board_runner_args(jlink "--device=RISC-V" "--speed=4000" "-if SW" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}")
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/panasonic/panb511evb/board.yml b/boards/panasonic/panb511evb/board.yml
new file mode 100644
index 00000000000..a7e9a5901a4
--- /dev/null
+++ b/boards/panasonic/panb511evb/board.yml
@@ -0,0 +1,9 @@
+board:
+  name: panb511evb
+  full_name: PAN B511 Evaluation Board
+  vendor: panasonic
+  socs:
+  - name: nrf54l15
+    variants:
+    - name: xip
+      cpucluster: cpuflpr
diff --git a/boards/panasonic/panb511evb/doc/img/panb511evb.webp b/boards/panasonic/panb511evb/doc/img/panb511evb.webp
new file mode 100644
index 00000000000..51748e65c8d
Binary files /dev/null and b/boards/panasonic/panb511evb/doc/img/panb511evb.webp differ
diff --git a/boards/panasonic/panb511evb/doc/index.rst b/boards/panasonic/panb511evb/doc/index.rst
new file mode 100644
index 00000000000..25920e77482
--- /dev/null
+++ b/boards/panasonic/panb511evb/doc/index.rst
@@ -0,0 +1,46 @@
+.. zephyr:board:: panb511evb
+
+Overview
+********
+
+The PAN B511 Evaluation Board (panb511evb) is a development tool
+for the PAN B511 module which is based on the nRF54L15 chipset
+from Nordic Semiconductor.
+
+More information about the PAN B511 Module Variants and Evaluation Board can be found
+on the `product website`_.
+
+Usage
+*****
+
+You can find the `panb511evb user guide`_ for the PAN B511 Evaluation Board in the
+`Panasonic Wireless Connectivity Development Hub`_.
+
+The User Guide contains (amongst other things) detailed information about
+
+* pin mapping
+* powering options
+* breakout pin header interface
+* current consumption measurement
+* software development
+
+and other things.
+
+The schematics for the PANB511 Evaluation Boards are available in the
+`download section PANB511`_ of the `Panasonic Wireless Connectivity Development Hub`_.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``panb511evb/nrf54l15/cpuapp`` board target can
+be built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+.. target-notes::
+.. _product website: https://industry.panasonic.eu/products/devices/wireless-connectivity/bluetooth-low-energy-modules
+.. _Panasonic Wireless Connectivity Development Hub: https://pideu.panasonic.de/development-hub/
+.. _panb511evb user guide: https://pideu.panasonic.de/development-hub/panb511/evaluation_board/user_guide/
+.. _download section PANB511: https://pideu.panasonic.de/development-hub/panb511/downloads/
diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15-pinctrl.dtsi b/boards/panasonic/panb511evb/panb511evb_nrf54l15-pinctrl.dtsi
new file mode 100644
index 00000000000..bc3a54459d9
--- /dev/null
+++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15-pinctrl.dtsi
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	/omit-if-no-ref/ uart20_default: uart20_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 4)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 1, 5)>;
+			bias-pull-up;
+		};
+	};
+
+	/omit-if-no-ref/ uart20_sleep: uart20_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 4)>,
+				<NRF_PSEL(UART_RX, 1, 5)>;
+			low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ uart30_default: uart30_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 1)>,
+				<NRF_PSEL(UART_RTS, 0, 3)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 0, 2)>,
+				<NRF_PSEL(UART_CTS, 0, 4)>;
+			bias-pull-up;
+		};
+	};
+
+	/omit-if-no-ref/ uart30_sleep: uart30_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 1)>,
+				<NRF_PSEL(UART_RX, 0, 2)>,
+				<NRF_PSEL(UART_RTS, 0, 3)>,
+				<NRF_PSEL(UART_CTS, 0, 4)>;
+			low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ spi00_default: spi00_default {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 1)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 2)>,
+				<NRF_PSEL(SPIM_MISO, 2, 4)>;
+		};
+	};
+
+	/omit-if-no-ref/ spi00_sleep: spi00_sleep {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 1)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 2)>,
+				<NRF_PSEL(SPIM_MISO, 2, 4)>;
+			low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ pwm20_default: pwm20_default {
+		group1 {
+			psels = <NRF_PSEL(PWM_OUT0, 1, 10)>;
+		};
+	};
+
+	/omit-if-no-ref/ pwm20_sleep: pwm20_sleep {
+		group1 {
+			psels = <NRF_PSEL(PWM_OUT0, 1, 10)>;
+			low-power-enable;
+		};
+	};
+};
diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_common.dtsi b/boards/panasonic/panb511evb/panb511evb_nrf54l15_common.dtsi
new file mode 100644
index 00000000000..fc300f888b9
--- /dev/null
+++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_common.dtsi
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "panb511evb_nrf54l15-pinctrl.dtsi"
+
+/ {
+	leds {
+		compatible = "gpio-leds";
+
+		evb_led1: evb_led_1 {
+			gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
+			label = "LED1 on EVB";
+		};
+
+		evb_led2: evb_led_2 {
+			gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
+			label = "LED2 on EVB";
+		};
+
+		evb_led3: evb_led_3 {
+			gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+			label = "LED3 on EVB";
+		};
+
+		evb_led4: evb_led_4 {
+			gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
+			label = "LED4 on EVB";
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		/*
+		 * PWM signal can be exposed on GPIO pin only within same domain.
+		 * There is only one domain which contains both PWM and GPIO:
+		 * PWM20/21/22 and GPIO Port P1.
+		 * Only LEDs connected to P1 can work with PWM, for example LED1.
+		 */
+		pwm_evb_led1: pwm_evb_led_1 {
+			pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		evb_sw1: evb_sw_1 {
+			gpios = <&gpio1 11 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "SW1 on EVB";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		evb_sw2: evb_sw_2 {
+			gpios = <&gpio1 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "SW2 on EVB";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+
+		evb_sw3: evb_sw_3 {
+			gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "SW3 on EVB";
+			zephyr,code = <INPUT_KEY_2>;
+		};
+
+		evb_sw4: evb_sw_4 {
+			gpios = <&gpio1 14 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "SW4 on EVB";
+			zephyr,code = <INPUT_KEY_3>;
+		};
+	};
+
+	mikrobus_header: mikrobus-connector {
+		compatible = "mikro-bus";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpio1 6 0>,	/* AN */
+			/* Not a GPIO*/		/* RST */
+			<2 0 &gpio2 10 0>,	/* CS */
+			<3 0 &gpio2 6 0>,	/* SCK */
+			<4 0 &gpio2 9 0>,	/* MISO */
+			<5 0 &gpio2 8 0>,	/* MOSI */
+			/* +3.3V */
+			/* GND */
+			<6 0 &gpio1 15 0>,	/* PWM */
+			<7 0 &gpio2 7 0>,	/* INT */
+			<8 0 &gpio1 5 0>,	/* RX */
+			<9 0 &gpio1 4 0>,	/* TX */
+			<10 0 &gpio1 8 0>,	/* SCL */
+			<11 0 &gpio1 9 0>;	/* SDA */
+			/* +5V */
+			/* GND */
+	};
+
+	arduino_header: connector {
+		compatible = "arduino-header-r3";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpio1 6 0>, /* A0 */
+			<1 0 &gpio1 7 0>, /* A1 */
+			<2 0 &gpio1 11 0>, /* A2 */
+			<3 0 &gpio1 12 0>, /* A3 */
+			<4 0 &gpio1 13 0>, /* A4 */
+			<5 0 &gpio1 14 0>, /* A5 */
+			<6 0 &gpio1 4 0>, /* D0 */
+			<7 0 &gpio1 5 0>, /* D1 */
+			<8 0 &gpio0 0 0>, /* D2 */
+			<9 0 &gpio1 2 0>, /* D3 */
+			<10 0 &gpio1 3 0>, /* D4 */
+			<11 0 &gpio1 10 0>, /* D5 */
+			<12 0 &gpio1 13 0>, /* D6 */
+			<13 0 &gpio1 14 0>, /* D7 */
+			<14 0 &gpio1 15 0>, /* D8 */
+			<15 0 &gpio2 7 0>, /* D9 */
+			<16 0 &gpio2 10 0>, /* D10 */
+			<17 0 &gpio2 8 0>, /* D11 */
+			<18 0 &gpio2 9 0>, /* D12 */
+			<19 0 &gpio2 6 0>, /* D13 */
+			<20 0 &gpio1 9 0>, /* D14 */
+			<21 0 &gpio1 8 0>; /* D15 */
+	};
+
+	arduino_adc: analog-connector {
+		compatible = "arduino,uno-adc";
+		#io-channel-cells = <1>;
+		io-channel-map = <0 &adc 0>,	/* A0 = P1.06 = AIN0 */
+			<1 &adc 1>,	/* A1 = P1.07 = AIN1 */
+			<2 &adc 2>,	/* A2 = P1.11 = AIN2 */
+			<3 &adc 3>,	/* A3 = P1.12 = AIN3 */
+			<4 &adc 4>,	/* A4 = P1.13 = AIN4 */
+			<5 &adc 5>;	/* A5 = P1.14 = AIN5 */
+	};
+
+	aliases {
+		led0 = &evb_led1;
+		led1 = &evb_led2;
+		led2 = &evb_led3;
+		led3 = &evb_led4;
+		pwm-led0 = &pwm_evb_led1;
+		sw0 = &evb_sw1;
+		sw1 = &evb_sw2;
+		sw2 = &evb_sw3;
+		sw3 = &evb_sw4;
+		watchdog0 = &wdt31;
+	};
+};
+
+&uart20 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart20_default>;
+	pinctrl-1 = <&uart20_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&uart30 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart30_default>;
+	pinctrl-1 = <&uart30_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&pwm20 {
+	status = "okay";
+	pinctrl-0 = <&pwm20_default>;
+	pinctrl-1 = <&pwm20_sleep>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.dts b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.dts
new file mode 100644
index 00000000000..c79847a3b57
--- /dev/null
+++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.dts
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <nordic/nrf54l15_cpuapp.dtsi>
+#include "panb511evb_nrf54l15_cpuapp_common.dtsi"
+
+/ {
+	compatible = "panasonic-industrial-devices-europe-gmbh,panb511evb-cpuapp";
+	model = "Panasonic PAN B511 EVB nRF54L15 Application MCU";
+
+	chosen {
+		zephyr,code-partition = &slot0_partition;
+		zephyr,sram = &cpuapp_sram;
+	};
+};
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		slot0_partition: partition@10000 {
+			label = "image-0";
+			reg = <0x10000 DT_SIZE_K(324)>;
+		};
+
+		slot0_ns_partition: partition@61000 {
+			label = "image-0-nonsecure";
+			reg = <0x61000 DT_SIZE_K(324)>;
+		};
+
+		slot1_partition: partition@b2000 {
+			label = "image-1";
+			reg = <0xb2000 DT_SIZE_K(324)>;
+		};
+
+		slot1_ns_partition: partition@103000 {
+			label = "image-1-nonsecure";
+			reg = <0x103000 DT_SIZE_K(324)>;
+		};
+
+		/* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */
+		storage_partition: partition@15c000 {
+			label = "storage";
+			reg = <0x15c000 DT_SIZE_K(36)>;
+		};
+	};
+};
diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.yaml b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.yaml
new file mode 100644
index 00000000000..b30e5ffa106
--- /dev/null
+++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: panb511evb/nrf54l15/cpuapp
+name: PANB511-EVB-nRF54l15-Application
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - zephyr
+sysbuild: true
+ram: 188
+flash: 324
+supported:
+  - adc
+  - counter
+  - gpio
+  - i2c
+  - pwm
+  - retained_mem
+  - spi
+  - watchdog
+  - i2s
diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_common.dtsi b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_common.dtsi
new file mode 100644
index 00000000000..bf7922d8069
--- /dev/null
+++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_common.dtsi
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* This file is common to the secure and non-secure domain */
+
+#include "panb511evb_nrf54l15_common.dtsi"
+
+/ {
+	chosen {
+		zephyr,console = &uart30;
+		zephyr,shell-uart = &uart30;
+		zephyr,uart-mcumgr = &uart30;
+		zephyr,bt-mon-uart = &uart30;
+		zephyr,bt-c2h-uart = &uart30;
+		zephyr,flash-controller = &rram_controller;
+		zephyr,flash = &cpuapp_rram;
+		zephyr,ieee802154 = &ieee802154;
+	};
+};
+
+&cpuapp_sram {
+	status = "okay";
+};
+
+&lfxo {
+	load-capacitors = "internal";
+	load-capacitance-femtofarad = <15500>;
+};
+
+&hfxo {
+	load-capacitors = "internal";
+	load-capacitance-femtofarad = <15000>;
+};
+
+&regulators {
+	status = "okay";
+};
+
+&vregmain {
+	status = "okay";
+	regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
+};
+
+&grtc {
+	owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
+	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
+	child-owned-channels = <3 4 7 8 9 10 11>;
+	status = "okay";
+};
+
+&uart30 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};
+
+&radio {
+	status = "okay";
+};
+
+&ieee802154 {
+	status = "okay";
+};
+
+&temp {
+	status = "okay";
+};
+
+&clock {
+	status = "okay";
+};
+
+&spi00 {
+	status = "okay";
+	cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spi00_default>;
+	pinctrl-1 = <&spi00_sleep>;
+	pinctrl-names = "default", "sleep";
+
+	mx25r64: mx25r6435f@0 {
+		compatible = "jedec,spi-nor";
+		status = "okay";
+		reg = <0>;
+		spi-max-frequency = <8000000>;
+		jedec-id = [c2 28 17];
+		sfdp-bfp = [
+			e5 20 f1 ff  ff ff ff 03  44 eb 08 6b  08 3b 04 bb
+			ee ff ff ff  ff ff 00 ff  ff ff 00 ff  0c 20 0f 52
+			10 d8 00 ff  23 72 f5 00  82 ed 04 cc  44 83 48 44
+			30 b0 30 b0  f7 c4 d5 5c  00 be 29 ff  f0 d0 ff ff
+		];
+		size = <67108864>;
+		has-dpd;
+		t-enter-dpd = <10000>;
+		t-exit-dpd = <35000>;
+	};
+};
+
+&adc {
+	status = "okay";
+};
diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_defconfig b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_defconfig
new file mode 100644
index 00000000000..41648ab5b23
--- /dev/null
+++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuapp_defconfig
@@ -0,0 +1,29 @@
+# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# MPU-based null-pointer dereferencing detection cannot
+# be applied as the (0x0 - 0x400) is unmapped for this target.
+CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
+
+# Enable Cache
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_EXTERNAL_CACHE=y
+
+# Start SYSCOUNTER on driver init
+CONFIG_NRF_GRTC_START_SYSCOUNTER=y
diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr.dts b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr.dts
new file mode 100644
index 00000000000..5a238b48a6b
--- /dev/null
+++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr.dts
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf54l15_cpuflpr.dtsi>
+#include "panb511evb_nrf54l15_common.dtsi"
+
+/ {
+	model = "Panasonic PAN B511 EVB nRF54L15 FLPR MCU";
+	compatible = "panasonic-industrial-devices-europe-gmbh,panb511evb-cpuflpr";
+
+	chosen {
+		zephyr,console = &uart20;
+		zephyr,shell-uart = &uart20;
+		zephyr,code-partition = &cpuflpr_code_partition;
+		zephyr,flash = &cpuflpr_rram;
+		zephyr,sram = &cpuflpr_sram;
+	};
+};
+
+&cpuflpr_sram {
+	status = "okay";
+	/* Size must be increased due to booting from SRAM */
+	reg = <0x20028000 DT_SIZE_K(96)>;
+	ranges = <0x0 0x20028000 0x18000>;
+};
+
+&cpuflpr_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cpuflpr_code_partition: partition@0 {
+			label = "image-0";
+			reg = <0x0 DT_SIZE_K(96)>;
+		};
+	};
+};
+
+&grtc {
+	owned-channels = <3 4>;
+	status = "okay";
+};
+
+&uart20 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};
diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr.yaml b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr.yaml
new file mode 100644
index 00000000000..481fcb00bd0
--- /dev/null
+++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: panb511evb/nrf54l15/cpuflpr
+name: PANB511-EVB-nRF54L15-Fast-Lightweight-Peripheral-Processor
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+sysbuild: true
+ram: 96
+flash: 96
+supported:
+  - counter
+  - gpio
+  - i2c
+  - spi
+  - watchdog
diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_defconfig b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_defconfig
new file mode 100644
index 00000000000..35618b20a6e
--- /dev/null
+++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_defconfig
@@ -0,0 +1,17 @@
+# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+CONFIG_USE_DT_CODE_PARTITION=y
+
+# Execute from SRAM
+CONFIG_XIP=n
diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_xip.dts b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_xip.dts
new file mode 100644
index 00000000000..f14f44e0975
--- /dev/null
+++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_xip.dts
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "panb511evb_nrf54l15_cpuflpr.dts"
+
+&cpuflpr_sram {
+	reg = <0x2002f000 DT_SIZE_K(68)>;
+	ranges = <0x0 0x2002f000 0x11000>;
+};
diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_xip.yaml b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_xip.yaml
new file mode 100644
index 00000000000..e54c5a7b9fd
--- /dev/null
+++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_xip.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: panb511evb/nrf54l15/cpuflpr/xip
+name: PANB511-EVB-nRF54L15-Fast-Lightweight-Peripheral-Processor (RRAM XIP)
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+sysbuild: true
+ram: 68
+flash: 96
+supported:
+  - counter
+  - gpio
+  - i2c
+  - spi
+  - watchdog
diff --git a/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_xip_defconfig b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_xip_defconfig
new file mode 100644
index 00000000000..8f75855af3c
--- /dev/null
+++ b/boards/panasonic/panb511evb/panb511evb_nrf54l15_cpuflpr_xip_defconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Execute from RRAM
+CONFIG_XIP=y
diff --git a/boards/panasonic/panb511evb/support/nrf54l15_cpuflpr.JLinkScript b/boards/panasonic/panb511evb/support/nrf54l15_cpuflpr.JLinkScript
new file mode 100644
index 00000000000..1cf94ee52a4
--- /dev/null
+++ b/boards/panasonic/panb511evb/support/nrf54l15_cpuflpr.JLinkScript
@@ -0,0 +1,5 @@
+int InitTarget(void) {
+  // Base address where DMI registers can be found in the APB address space
+  JLINK_ExecCommand("CORESIGHT_SetCoreBaseAddr = 0x5004C400");
+  return 0;
+}
diff --git a/boards/particle/argon/doc/index.rst b/boards/particle/argon/doc/index.rst
index d0391a102a4..adc9dc6d2a2 100644
--- a/boards/particle/argon/doc/index.rst
+++ b/boards/particle/argon/doc/index.rst
@@ -37,31 +37,7 @@ It contains circuitry for LIPO usage and can be charged via the USB port.
 Supported Features
 ==================
 
-The particle_argon board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| NVIC      | on-chip    | nested vectored      |
-|           |            | interrupt controller |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial port          |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -118,6 +94,8 @@ UART
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``particle_argon`` board configuration can be
 built and flashed in the usual way (see :ref:`build_an_application`
 and :ref:`application_run` for more details).
diff --git a/boards/particle/argon/particle_argon.yaml b/boards/particle/argon/particle_argon.yaml
index 489b8c9dd1e..8ec6c888b92 100644
--- a/boards/particle/argon/particle_argon.yaml
+++ b/boards/particle/argon/particle_argon.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - i2c
   - spi
diff --git a/boards/particle/boron/doc/index.rst b/boards/particle/boron/doc/index.rst
index 73ece4387d6..fcdff03cc8f 100644
--- a/boards/particle/boron/doc/index.rst
+++ b/boards/particle/boron/doc/index.rst
@@ -37,31 +37,7 @@ It contains circuitry for LIPO usage and can be charged via the USB port.
 Supported Features
 ==================
 
-The particle_boron board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| NVIC      | on-chip    | nested vectored      |
-|           |            | interrupt controller |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial port          |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -114,6 +90,8 @@ UART
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``particle_boron`` board configuration can be
 built and flashed in the usual way (see :ref:`build_an_application`
 and :ref:`application_run` for more details).
diff --git a/boards/particle/boron/particle_boron.yaml b/boards/particle/boron/particle_boron.yaml
index bec2a0cbb03..1e2835ac09d 100644
--- a/boards/particle/boron/particle_boron.yaml
+++ b/boards/particle/boron/particle_boron.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - i2c
   - spi
diff --git a/boards/particle/nrf51_blenano/doc/index.rst b/boards/particle/nrf51_blenano/doc/index.rst
index 5cedb0aa100..36743f56656 100644
--- a/boards/particle/nrf51_blenano/doc/index.rst
+++ b/boards/particle/nrf51_blenano/doc/index.rst
@@ -15,25 +15,7 @@ is 32.768 kHz. The frequency of the main clock is 16 MHz.
 Supported Features
 ==================
 
-The nrf51_blenano board configuration supports the following nRF51
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| NVIC      | on-chip    | nested vectored      |
-|           |            | interrupt controller |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial port          |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ====================
@@ -58,6 +40,8 @@ More information about Nano and DAPLink can be found at the `RedBear Github`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``nrf51_blenano`` board configuration can be built and
 flashed in the usual way (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/particle/nrf51_blenano/nrf51_blenano.dts b/boards/particle/nrf51_blenano/nrf51_blenano.dts
index f3e4dc8509c..8770c0b09ff 100644
--- a/boards/particle/nrf51_blenano/nrf51_blenano.dts
+++ b/boards/particle/nrf51_blenano/nrf51_blenano.dts
@@ -29,7 +29,7 @@
 	leds {
 		compatible = "gpio-leds";
 		led0: led_0 {
-			gpios = <&gpio0 19 0>;
+			gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
 			label = "LED";
 		};
 	};
diff --git a/boards/particle/nrf51_blenano/nrf51_blenano.yaml b/boards/particle/nrf51_blenano/nrf51_blenano.yaml
index 97ddb9002ab..4d4c9c96a22 100644
--- a/boards/particle/nrf51_blenano/nrf51_blenano.yaml
+++ b/boards/particle/nrf51_blenano/nrf51_blenano.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 16
 supported:
   - ble
diff --git a/boards/particle/nrf52_blenano2/doc/index.rst b/boards/particle/nrf52_blenano2/doc/index.rst
index 5fd77e80c67..003378a166f 100644
--- a/boards/particle/nrf52_blenano2/doc/index.rst
+++ b/boards/particle/nrf52_blenano2/doc/index.rst
@@ -17,23 +17,8 @@ Hardware
 
 Supported Features
 ==================
-The BLE Nano v2 board configuration supports the following hardware features:
-
-+-----------+------------+--------------------------------------+
-| Interface | Controller |      Driver/Component                |
-+===========+============+======================================+
-| NVIC      | on-chip    | nested vectored interrupt controller |
-+-----------+------------+--------------------------------------+
-| UART      | on-chip    | serial port                          |
-+-----------+------------+--------------------------------------+
-| GPIO      | on-chip    | gpio                                 |
-+-----------+------------+--------------------------------------+
-| FLASH     | on-chip    | flash                                |
-+-----------+------------+--------------------------------------+
-| RADIO     | on-chip    | Bluetooth                            |
-+-----------+------------+--------------------------------------+
-| I2C       | on-chip    | i2c                                  |
-+-----------+------------+--------------------------------------+
+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ====================
@@ -57,6 +42,8 @@ It also regulates 5V from USB to 3.3V via the onboard LDO to power Nano v2.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``nrf52_blenano2`` board configuration can be built and
 flashed in the usual way (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/particle/nrf52_blenano2/nrf52_blenano2.yaml b/boards/particle/nrf52_blenano2/nrf52_blenano2.yaml
index c3a0c8648bf..84f1dc668f8 100644
--- a/boards/particle/nrf52_blenano2/nrf52_blenano2.yaml
+++ b/boards/particle/nrf52_blenano2/nrf52_blenano2.yaml
@@ -5,6 +5,5 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 512
diff --git a/boards/particle/xenon/doc/index.rst b/boards/particle/xenon/doc/index.rst
index 795393b09f4..4f6cf37fcf4 100644
--- a/boards/particle/xenon/doc/index.rst
+++ b/boards/particle/xenon/doc/index.rst
@@ -36,31 +36,7 @@ It contains circuitry for LIPO usage and can be charged via the USB port.
 Supported Features
 ==================
 
-The particle_xenon board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| NVIC      | on-chip    | nested vectored      |
-|           |            | interrupt controller |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial port          |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -119,6 +95,8 @@ UART
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``particle_xenon`` board configuration can be
 built and flashed in the usual way (see :ref:`build_an_application`
 and :ref:`application_run` for more details).
diff --git a/boards/particle/xenon/particle_xenon.yaml b/boards/particle/xenon/particle_xenon.yaml
index 0aa6a4afa15..0b217696547 100644
--- a/boards/particle/xenon/particle_xenon.yaml
+++ b/boards/particle/xenon/particle_xenon.yaml
@@ -12,7 +12,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - i2c
   - spi
diff --git a/boards/peregrine/index.rst b/boards/peregrine/index.rst
new file mode 100644
index 00000000000..a14270121da
--- /dev/null
+++ b/boards/peregrine/index.rst
@@ -0,0 +1,10 @@
+.. _boards-peregrine:
+
+Peregrine
+#########
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*
diff --git a/boards/peregrine/sam4l_wm400_cape/Kconfig.defconfig b/boards/peregrine/sam4l_wm400_cape/Kconfig.defconfig
new file mode 100644
index 00000000000..1f95ae349d0
--- /dev/null
+++ b/boards/peregrine/sam4l_wm400_cape/Kconfig.defconfig
@@ -0,0 +1,22 @@
+# Copyright (c) 2020-2025 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_SAM4L_WM400_CAPE
+
+if NETWORKING
+
+config IEEE802154_RF2XX
+	default y
+	depends on IEEE802154
+
+endif # NETWORKING
+
+# By default the board uses BOSSA bootloader and require that to zephyr relocate
+# the code_partition. This should be disabled when using the whole flash without
+# bootloader.
+config USE_DT_CODE_PARTITION
+	default y
+
+source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig"
+
+endif # BOARD_SAM4L_WM400_CAPE
diff --git a/boards/peregrine/sam4l_wm400_cape/Kconfig.sam4l_wm400_cape b/boards/peregrine/sam4l_wm400_cape/Kconfig.sam4l_wm400_cape
new file mode 100644
index 00000000000..44f81df5d32
--- /dev/null
+++ b/boards/peregrine/sam4l_wm400_cape/Kconfig.sam4l_wm400_cape
@@ -0,0 +1,5 @@
+# Copyright (c) 2020-2025 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_SAM4L_WM400_CAPE
+	select SOC_SAM4LC4B
diff --git a/boards/peregrine/sam4l_wm400_cape/board.cmake b/boards/peregrine/sam4l_wm400_cape/board.cmake
new file mode 100644
index 00000000000..1b805dc8c9f
--- /dev/null
+++ b/boards/peregrine/sam4l_wm400_cape/board.cmake
@@ -0,0 +1,12 @@
+# Copyright (c) 2020-2025 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=atsam4lc4b")
+board_runner_args(jlink "--speed=4000")
+board_runner_args(jlink "--reset-after-load")
+board_runner_args(jlink "-rtos GDBServer/RTOSPlugin_Zephyr")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+
+board_runner_args(bossac "--bossac-port=/dev/ttyACM0")
+board_runner_args(bossac "--erase")
+include(${ZEPHYR_BASE}/boards/common/bossac.board.cmake)
diff --git a/boards/peregrine/sam4l_wm400_cape/board.yml b/boards/peregrine/sam4l_wm400_cape/board.yml
new file mode 100644
index 00000000000..ded0ab037ae
--- /dev/null
+++ b/boards/peregrine/sam4l_wm400_cape/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: sam4l_wm400_cape
+  full_name: SAM4L WM-400 Cape Board
+  vendor: peregrine
+  socs:
+    - name: sam4lc4b
diff --git a/boards/peregrine/sam4l_wm400_cape/doc/img/wm-400-pin-out.webp b/boards/peregrine/sam4l_wm400_cape/doc/img/wm-400-pin-out.webp
new file mode 100644
index 00000000000..28bfe30e3b4
Binary files /dev/null and b/boards/peregrine/sam4l_wm400_cape/doc/img/wm-400-pin-out.webp differ
diff --git a/boards/peregrine/sam4l_wm400_cape/doc/index.rst b/boards/peregrine/sam4l_wm400_cape/doc/index.rst
new file mode 100644
index 00000000000..586c7cb5f8b
--- /dev/null
+++ b/boards/peregrine/sam4l_wm400_cape/doc/index.rst
@@ -0,0 +1,124 @@
+.. zephyr:board:: sam4l_wm400_cape
+
+Overview
+********
+
+The SAM4L WM-400 Cape is a full featured design to enable IEEE 802.15.4 low
+power nodes. It is a Beaglebone Black cape concept with an Atmel AT86RF233
+radio transceiver. User can develop Touch interface and have access to many
+sensors and conectivity buses.
+
+Hardware
+********
+
+- ATSAM4LC4B ARM Cortex-M4 Processor
+- 12 MHz crystal oscillator
+- 32.768 kHz crystal oscillator
+- 1 RS-232 interface
+- 1 RS-485 full duplex interface
+- Micro-AB USB OTG host/device
+- 1 user touch button and One user pushbutton
+- 4 user LEDs
+- 1 AT86RF233 IEEE 802.15.4 transceiver
+- 1 MPL115A2 I²C Barometric Pressure/Temperature Sensor
+- 1 VCNL4010 Proximity/Light Sensor
+- 1 CC2D33S Advanced Humidity Temperature Sensor
+- 1 NCP18WF104J03RB NTC Temperature Sensor
+- 1 TEMT6000X01 Ambient Light Sensor
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+For detailed information see `SAM4L WM-400 Cape`_ Information.
+
+System Clock
+============
+
+The SAM4L MCU is configured to use the 12 MHz internal oscillator on the board
+with the on-chip PLL to generate an 48 MHz system clock.
+
+Serial Port
+===========
+
+The ATSAM4LC4B MCU has 4 USARTs. One of the USARTs (USART3) is shared between
+RS-232 and RS-485 interfaces. The default console terminal is available at
+RS-232 onboard port or via USB device.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+The SAM4L WM-400 Cape board has a 10-pin header to connect to a Segger JLink.
+Using the JLink is possible to program and debug the SAM4LC4B chip. The board
+came with a SAM-BA bootloader that only can be used to flash the software.
+
+Flashing
+========
+
+#. For JLink instructions, see :ref:`jlink-debug-host-tools`.
+
+#. Run your favorite terminal program to listen for output. Under Linux the
+   terminal should be :code:`/dev/ttyACM0`. For example:
+
+   .. code-block:: console
+
+      $ minicom -D /dev/ttyACM0 -o
+
+   The -o option tells minicom not to send the modem initialization
+   string. Connection should be configured as follows:
+
+   - Speed: 115200
+   - Data: 8 bits
+   - Parity: None
+   - Stop bits: 1
+
+#. Connect the SAM4L WM-400 Cape board to your host computer using the
+   USB debug port. Then build and flash the :zephyr:code-sample:`hello_world`
+   application.
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: sam4l_wm400_cape
+      :goals: build flash
+
+   You should see ``Hello World! sam4l_wm400_cape`` in your terminal.
+
+#. For SAM-BA bootloader instructions, see :ref:`atmel_sam_ba_bootloader`.
+
+#. Connect the SAM4L WM-400 Cape board to your host computer using the
+   USB debug port pressing the S1 button. Then build and flash the
+   :zephyr:code-sample:`hello_world` application. After programming the board
+   the application will start automatically.
+
+   .. zephyr-app-commands::
+      :zephyr-app: samples/hello_world
+      :board: sam4l_wm400_cape
+      :goals: build flash
+      :flash-args: -r bossac
+
+
+Debugging
+=========
+
+You can debug an application in the usual way.  Here is an example for the
+:zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: sam4l_wm400_cape
+   :maybe-skip-config:
+   :goals: debug
+
+References
+**********
+
+.. target-notes::
+
+.. _SAM4L WM-400 Cape:
+    https://gfbudke.wordpress.com/2014/04/30/modulo-wireless-ieee-802-15-4zigbee-wm-400-e-wm-400l-bbbs
diff --git a/boards/peregrine/sam4l_wm400_cape/sam4l_wm400_cape-pinctrl.dtsi b/boards/peregrine/sam4l_wm400_cape/sam4l_wm400_cape-pinctrl.dtsi
new file mode 100644
index 00000000000..e1b81485b5b
--- /dev/null
+++ b/boards/peregrine/sam4l_wm400_cape/sam4l_wm400_cape-pinctrl.dtsi
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2022-2025 Gerson Fernando Budke <nandojve@gmail.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/sam4lcXb-pinctrl.h>
+
+&pinctrl {
+	spi0_default: spi0_default {
+		group1 {
+			pinmux = <PA21A_SPI_MISO>,
+				 <PA22A_SPI_MOSI>,
+				 <PA23A_SPI_SCK>,
+				 <PA13C_SPI_NPCS1>,
+				 <PA14C_SPI_NPCS2>;
+		};
+	};
+
+	twi1_default: twi1_default {
+		group1 {
+			pinmux = <PB1A_TWIMS1_TWCK>,
+				 <PB0A_TWIMS1_TWD>;
+		};
+	};
+
+	usart0_default: usart0_default {
+		group1 {
+			pinmux = <PB14A_USART0_RXD>,
+				 <PB15A_USART0_TXD>;
+		};
+	};
+
+	usart0_hw_ctrl_flow: usart0_hw_ctrl_flow {
+		group1 {
+			pinmux = <PB14A_USART0_RXD>,
+				 <PB12A_USART0_RTS>;
+			bias-pull-up;
+		};
+
+		group2 {
+			pinmux = <PB15A_USART0_TXD>,
+				 <PB11A_USART0_CTS>,
+				 <PB13A_USART0_CLK>;
+		};
+	};
+
+	usart1_default: usart1_default {
+		group1 {
+			pinmux = <PA15A_USART1_RXD>,
+				 <PA16A_USART1_TXD>;
+		};
+	};
+
+	usbc_default: usbc_default {
+		group1 {
+			pinmux = <PA25A_USBC_DM>,
+				 <PA26A_USBC_DP>;
+		};
+	};
+};
diff --git a/boards/peregrine/sam4l_wm400_cape/sam4l_wm400_cape.dts b/boards/peregrine/sam4l_wm400_cape/sam4l_wm400_cape.dts
new file mode 100644
index 00000000000..5f181100344
--- /dev/null
+++ b/boards/peregrine/sam4l_wm400_cape/sam4l_wm400_cape.dts
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2020-2025 Gerson Fernando Budke <nandojve@gmail.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <atmel/sam4lx4.dtsi>
+#include "sam4l_wm400_cape-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "Atmel SAM4L WM-400 Cape Board with an Atmel SAM4LC4B SoC";
+	compatible = "peregrine,sam4l_wm400_cape", "atmel,sam4lc4b", "atmel,sam4l";
+
+	aliases {
+		i2c-0 = &twim1;
+		led0 = &red_mod_led;
+		led1 = &green_mod_led;
+		led2 = &blue_mod_led;
+		led3 = &red_cape_led;
+		sw0 = &sw0_dfu;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition= &code_partition;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		red_mod_led: led_0 {
+			gpios = <&gpioa 8 GPIO_ACTIVE_LOW>;
+			label = "LED_0";
+		};
+
+		green_mod_led: led_1 {
+			gpios = <&gpiob 6 GPIO_ACTIVE_LOW>;
+			label = "LED_1";
+		};
+
+		blue_mod_led: led_2 {
+			gpios = <&gpiob 7 GPIO_ACTIVE_LOW>;
+			label = "LED_2";
+		};
+
+		red_cape_led: led_3 {
+			gpios = <&gpioa 24 GPIO_ACTIVE_LOW>;
+			label = "LED_3";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		sw0_dfu: button_1 {
+			gpios = <&gpiob 3 (GPIO_ACTIVE_LOW)>;
+			label = "SW0_DFU";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+};
+
+&cpu0 {
+	clock-frequency = <48000000>;
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "sam-ba";
+			reg = <0x000000000 0x00004000>;
+		};
+
+		code_partition: partition@4000 {
+			label = "image";
+			reg = <0x00004000 0x0003c000>;
+		};
+	};
+};
+
+&spi0 {
+	status = "okay";
+
+	pinctrl-0 = <&spi0_default>;
+	pinctrl-names = "default";
+
+	cs-gpios = <&gpioa 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)
+		    &gpioa 14 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+
+	rf2xx@0 {
+		compatible = "atmel,rf2xx";
+		reg = <0x0>;
+		spi-max-frequency = <6000000>;
+		irq-gpios = <&gpioa 20 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>;
+		reset-gpios = <&gpioa 10 GPIO_ACTIVE_LOW>;
+		slptr-gpios = <&gpioa 9 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
+
+	at45db: at45db081d@1 {
+		compatible = "atmel,at45";
+		reg = <1>;
+		spi-max-frequency = <8000000>;
+		jedec-id = [1f 25 00];
+		size = <8388608>;
+		sector-size = <65536>;
+		block-size = <2048>;
+		page-size = <256>;
+		enter-dpd-delay = <3000>;
+		exit-dpd-delay = <35000>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			storage_partition: partition@0 {
+				label = "storage";
+				reg = <0x00000000 0x00100000>;
+			};
+		};
+	};
+};
+
+&tc0 {
+	clk = <4>;
+	status = "okay";
+};
+
+&twim1 {
+	status = "okay";
+
+	pinctrl-0 = <&twi1_default>;
+	pinctrl-names = "default";
+
+	std-clk-slew-lim = <0>;
+	std-clk-strength-low = "0.5";
+	std-data-slew-lim = <0>;
+	std-data-strength-low = "0.5";
+
+	hs-clk-slew-lim = <0>;
+	hs-clk-strength-high = "0.5";
+	hs-clk-strength-low = "0.5";
+	hs-data-slew-lim = <0>;
+	hs-data-strength-low = "0.5";
+
+	hs-master-code = <0>;
+
+	eeprom1: eeprom@57 {
+		compatible = "atmel,at24";
+		reg = <0x57>;
+		size = <32768>;
+		pagesize = <64>;
+		address-width = <16>;
+		timeout = <5>;
+	};
+};
+
+&usart0 {
+	status = "okay";
+	current-speed = <115200>;
+
+	pinctrl-0 = <&usart0_default>;
+	pinctrl-names = "default";
+};
+
+&usart1 {
+	status = "okay";
+	current-speed = <115200>;
+
+	pinctrl-0 = <&usart1_default>;
+	pinctrl-names = "default";
+};
+
+zephyr_udc0: &usbc {
+	status = "okay";
+
+	pinctrl-0 = <&usbc_default>;
+	pinctrl-names = "default";
+};
+
+#include <../boards/common/usb/cdc_acm_serial.dtsi>
diff --git a/boards/peregrine/sam4l_wm400_cape/sam4l_wm400_cape.yaml b/boards/peregrine/sam4l_wm400_cape/sam4l_wm400_cape.yaml
new file mode 100644
index 00000000000..ac9516c9431
--- /dev/null
+++ b/boards/peregrine/sam4l_wm400_cape/sam4l_wm400_cape.yaml
@@ -0,0 +1,24 @@
+# Copyright (c) 2020-2025 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: sam4l_wm400_cape
+name: SAM4L WM-400 Cape
+type: mcu
+arch: arm
+flash: 256
+ram: 32
+toolchain:
+  - zephyr
+supported:
+  - counter
+  - gpio
+  - entropy
+  - hwinfo
+  - i2c
+  - ieee802154
+  - spi
+  - uart
+  - usart
+  - usb_device
+  - watchdog
+vendor: peregrine
diff --git a/boards/peregrine/sam4l_wm400_cape/sam4l_wm400_cape_defconfig b/boards/peregrine/sam4l_wm400_cape/sam4l_wm400_cape_defconfig
new file mode 100644
index 00000000000..623c83b1e06
--- /dev/null
+++ b/boards/peregrine/sam4l_wm400_cape/sam4l_wm400_cape_defconfig
@@ -0,0 +1,11 @@
+# Copyright (c) 2020-2025 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+CONFIG_CORTEX_M_SYSTICK=y
+CONFIG_WDT_DISABLE_AT_BOOT=y
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/phytec/phyboard_electra/phyboard_electra_am6442_m4.dts b/boards/phytec/phyboard_electra/phyboard_electra_am6442_m4.dts
index d19c5a62c92..cc243d6243c 100644
--- a/boards/phytec/phyboard_electra/phyboard_electra_am6442_m4.dts
+++ b/boards/phytec/phyboard_electra/phyboard_electra_am6442_m4.dts
@@ -17,7 +17,8 @@
 		zephyr,sram = &sram0;
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
-		zephyr,sram1 = &ddr0;
+		zephyr,ipc_shm = &ddr0;
+		zephyr,sram1 = &ddr1;
 	};
 
 	aliases {
@@ -31,9 +32,20 @@
 		};
 	};
 
-	ddr0:memory@a4100000 {
+	ddr0: memory@a4000000 {
+		compatible = "mmio-sram";
+		reg = <0xa4000000 DT_SIZE_M(1)>;
+	};
+
+	rsc_table: memory@a4100000 {
 		compatible = "zephyr,memory-region", "mmio-sram";
 		reg = <0xa4100000 DT_SIZE_K(4)>;
+		zephyr,memory-region = "RSC_TABLE";
+	};
+
+	ddr1: memory@a4101000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0xa4101000 (DT_SIZE_M(15) - DT_SIZE_K(4))>;
 		zephyr,memory-region = "DDR";
 	};
 
diff --git a/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_a53.rst b/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_a53.rst
index 9b6d2f42a3d..b7d00a9764f 100644
--- a/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_a53.rst
+++ b/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_a53.rst
@@ -45,6 +45,8 @@ features:
 +-----------+------------+-------------------------------------+
 | UART      | on-chip    | serial port                         |
 +-----------+------------+-------------------------------------+
+| Mailbox   | on-chip    | IPC Mailbox                         |
++-----------+------------+-------------------------------------+
 
 Devices
 ========
diff --git a/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_m4.rst b/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_m4.rst
index d0f61264890..cf36efc4f5e 100644
--- a/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_m4.rst
+++ b/boards/phytec/phyboard_lyra/doc/phyboard_lyra_am62xx_m4.rst
@@ -56,6 +56,8 @@ The phyboard_lyra/am6234/m4 configuration supports the following hardware featur
 +-----------+------------+-------------------------------------+
 | UART      | on-chip    | serial                              |
 +-----------+------------+-------------------------------------+
+| Mailbox   | on-chip    | IPC Mailbox                         |
++-----------+------------+-------------------------------------+
 
 Other hardware features are not currently supported by the port.
 
diff --git a/boards/phytec/phyboard_lyra/phyboard_lyra_am6234_m4.dts b/boards/phytec/phyboard_lyra/phyboard_lyra_am6234_m4.dts
index 8112aeba419..403277aea06 100644
--- a/boards/phytec/phyboard_lyra/phyboard_lyra_am6234_m4.dts
+++ b/boards/phytec/phyboard_lyra/phyboard_lyra_am6234_m4.dts
@@ -17,7 +17,8 @@
 		zephyr,sram = &sram0;
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
-		zephyr,sram1 = &ddr0;
+		zephyr,ipc_shm = &ddr0;
+		zephyr,sram1 = &ddr1;
 	};
 
 	aliases {
@@ -31,9 +32,20 @@
 		};
 	};
 
-	ddr0:memory@9CC00000{
+	ddr0: memory@9cb00000 {
+		compatible = "mmio-sram";
+		reg = <0x9cb00000 DT_SIZE_M(1)>;
+	};
+
+	rsc_table: memory@9cc00000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x9cc00000 DT_SIZE_K(4)>;
+		zephyr,memory-region = "RSC_TABLE";
+	};
+
+	ddr1: memory@9cc01000 {
 		compatible = "zephyr,memory-region", "mmio-sram";
-		reg = <0x9CC00000 DT_SIZE_K(4)>;
+		reg = <0x9cc01000 (DT_SIZE_M(15) - DT_SIZE_K(4))>;
 		zephyr,memory-region = "DDR";
 	};
 
diff --git a/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.yaml b/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.yaml
index 5167e4d0aec..23d07a25c99 100644
--- a/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.yaml
+++ b/boards/phytec/phyboard_polis/phyboard_polis_mimx8mm6_m4.yaml
@@ -13,7 +13,6 @@ flash: 128
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 testing:
   ignore_tags:
     - net
diff --git a/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.yaml b/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.yaml
index 01084520792..2af3d88b937 100644
--- a/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.yaml
+++ b/boards/phytec/phyboard_pollux/phyboard_pollux_mimx8ml8_m7.yaml
@@ -13,7 +13,6 @@ flash: 128
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 testing:
   ignore_tags:
     - net
diff --git a/boards/phytec/reel_board/reel_board_1.yaml b/boards/phytec/reel_board/reel_board_1.yaml
index b357f545511..c973f47cc79 100644
--- a/boards/phytec/reel_board/reel_board_1.yaml
+++ b/boards/phytec/reel_board/reel_board_1.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - i2c
   - spi
diff --git a/boards/phytec/reel_board/reel_board_nrf52840_2.yaml b/boards/phytec/reel_board/reel_board_nrf52840_2.yaml
index e98f366b969..5852cf72161 100644
--- a/boards/phytec/reel_board/reel_board_nrf52840_2.yaml
+++ b/boards/phytec/reel_board/reel_board_nrf52840_2.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - i2c
   - spi
diff --git a/boards/pimoroni/index.rst b/boards/pimoroni/index.rst
new file mode 100644
index 00000000000..3867af38c3c
--- /dev/null
+++ b/boards/pimoroni/index.rst
@@ -0,0 +1,10 @@
+.. _boards-pimoroni:
+
+Pimoroni Ltd.
+#############
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*
diff --git a/boards/pimoroni/pico_plus2/Kconfig.defconfig b/boards/pimoroni/pico_plus2/Kconfig.defconfig
new file mode 100644
index 00000000000..35cdf927054
--- /dev/null
+++ b/boards/pimoroni/pico_plus2/Kconfig.defconfig
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_PICO_PLUS2
+
+config USB_SELF_POWERED
+	default n
+
+endif # BOARD_PICO_PLUS2
diff --git a/boards/pimoroni/pico_plus2/Kconfig.pico_plus2 b/boards/pimoroni/pico_plus2/Kconfig.pico_plus2
new file mode 100644
index 00000000000..cd30fda60ae
--- /dev/null
+++ b/boards/pimoroni/pico_plus2/Kconfig.pico_plus2
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_PICO_PLUS2
+	select SOC_RP2350B_M33 if BOARD_PICO_PLUS2_RP2350B_M33
diff --git a/boards/pimoroni/pico_plus2/board.cmake b/boards/pimoroni/pico_plus2/board.cmake
new file mode 100644
index 00000000000..6de42450d89
--- /dev/null
+++ b/boards/pimoroni/pico_plus2/board.cmake
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(openocd --cmd-pre-init "source [find interface/cmsis-dap.cfg]")
+board_runner_args(openocd --cmd-pre-init "source [find target/rp2350.cfg]")
+
+# The adapter speed is expected to be set by interface configuration.
+# The Raspberry Pi's OpenOCD fork doesn't, so match their documentation at
+# https://www.raspberrypi.com/documentation/microcontrollers/debug-probe.html#debugging-with-swd
+board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 5000")
+
+board_runner_args(uf2 "--board-id=RP2350")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake)
diff --git a/boards/pimoroni/pico_plus2/board.yml b/boards/pimoroni/pico_plus2/board.yml
new file mode 100644
index 00000000000..71acca8e80e
--- /dev/null
+++ b/boards/pimoroni/pico_plus2/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: pico_plus2
+  full_name: Pimoroni Pico Plus2
+  vendor: pimoroni
+  socs:
+  - name: rp2350b
diff --git a/boards/pimoroni/pico_plus2/doc/img/pico_plus2.webp b/boards/pimoroni/pico_plus2/doc/img/pico_plus2.webp
new file mode 100644
index 00000000000..4d4967b6a58
Binary files /dev/null and b/boards/pimoroni/pico_plus2/doc/img/pico_plus2.webp differ
diff --git a/boards/pimoroni/pico_plus2/doc/index.rst b/boards/pimoroni/pico_plus2/doc/index.rst
new file mode 100644
index 00000000000..28f265e3898
--- /dev/null
+++ b/boards/pimoroni/pico_plus2/doc/index.rst
@@ -0,0 +1,61 @@
+.. zephyr:board:: pico_plus2
+
+Overview
+********
+
+The `Pimoroni Pico Plus 2`_ is a compact and versatile board featuring the Raspberry Pi RP2350B SoC.
+It includes USB Type-C, Qwiic/STEMMA QT connectors, SP/CE connectors, a debug connector,
+a reset button, and a BOOT button.
+
+Hardware
+********
+
+- Dual Cortex-M33 or Hazard3 processors at up to 150MHz
+- 520KB of SRAM, and 4MB of on-board flash memory
+- 16MB of on-board QSPI flash (supports XiP)
+- 8MB of PSRAM
+- USB 1.1 with device and host support
+- Low-power sleep and dormant modes
+- Drag-and-drop programming using mass storage over USB
+- 48 multi-function GPIO pins including 8 that can be used for ADC
+- 2 SPI, 2 I2C, 2 UART, 3 12-bit 500ksps Analogue to Digital - Converter (ADC), 24 controllable PWM channels
+- 2 Timer with 4 alarms, 1 AON Timer
+- Temperature sensor
+- 3 Programmable IO (PIO) blocks, 12 state machines total for custom peripheral support
+- USB-C connector for power, programming, and data transfer
+- Qwiic/STEMMA QT(Qw/ST) connector
+- SP/CE connector
+- 3-pin debug connector, this can use with `Raspberry Pi Debug Probe`_.
+- Reset button and BOOT button (BOOT button also usable as a user switch)
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+You can use peripherals that are made by using the PIO.
+See :ref:`rpi_pico_pio_based_features`
+
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+The overall explanation regarding flashing and debugging is the same as or ``rpi_pico``.
+See :ref:`rpi_pico_flashing_using_openocd` and :ref:`rpi_pico_flashing_using_uf2`
+in ``rpi_pico`` documentation.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: pico_plus2
+   :goals: build flash
+   :gen-args: -DOPENOCD=/usr/local/bin/openocd
+
+.. target-notes::
+
+.. _Pimoroni Pico Plus 2:
+  https://shop.pimoroni.com/products/pimoroni-pico-plus-2
+
+.. _Raspberry Pi Debug Probe:
+   https://www.raspberrypi.com/documentation/microcontrollers/debug-probe.html
diff --git a/boards/pimoroni/pico_plus2/pico_plus2-pinctrl.dtsi b/boards/pimoroni/pico_plus2/pico_plus2-pinctrl.dtsi
new file mode 100644
index 00000000000..1a0112cb80b
--- /dev/null
+++ b/boards/pimoroni/pico_plus2/pico_plus2-pinctrl.dtsi
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2024 TOKITA Hiroshi
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/rpi-pico-rp2350b-pinctrl.h>
+
+&pinctrl {
+	uart0_default: uart0_default {
+		group1 {
+			pinmux = <UART0_TX_P0>;
+		};
+
+		group2 {
+			pinmux = <UART0_RX_P1>;
+			input-enable;
+		};
+	};
+
+	i2c0_default: i2c0_default {
+		group1 {
+			pinmux = <I2C0_SDA_P4>, <I2C0_SCL_P5>;
+			input-enable;
+			input-schmitt-enable;
+		};
+	};
+
+	spi0_default: spi0_default {
+		group1 {
+			pinmux = <SPI0_CSN_P17>, <SPI0_SCK_P18>, <SPI0_TX_P19>;
+		};
+
+		group2 {
+			pinmux = <SPI0_RX_P16>;
+			input-enable;
+		};
+	};
+
+	pwm_ch4b_default: pwm_ch4b_default {
+		group1 {
+			pinmux = <PWM_4B_P25>;
+		};
+	};
+
+	adc_default: adc_default {
+		group1 {
+			pinmux = <ADC_CH0_P40>, <ADC_CH1_P41>, <ADC_CH2_P42>, <ADC_CH3_P43>;
+			input-enable;
+		};
+	};
+};
diff --git a/boards/pimoroni/pico_plus2/pico_plus2.dtsi b/boards/pimoroni/pico_plus2/pico_plus2.dtsi
new file mode 100644
index 00000000000..f77ae33e042
--- /dev/null
+++ b/boards/pimoroni/pico_plus2/pico_plus2.dtsi
@@ -0,0 +1,178 @@
+/*
+ * Copyright (c) 2024 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <freq.h>
+
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/pwm/pwm.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+#include "pico_plus2-pinctrl.dtsi"
+
+/ {
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,code-partition = &code_partition;
+	};
+
+	aliases {
+		watchdog0 = &wdt0;
+		led0 = &led0;
+		pwm-led0 = &pwm_led0;
+		sw0 = &user_sw;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led_0 {
+			gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
+			label = "LED";
+		};
+	};
+
+	pwm_leds {
+		compatible = "pwm-leds";
+		status = "disabled";
+
+		pwm_led0: pwm_led_0 {
+			pwms = <&pwm 9 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+			label = "PWM_LED";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		user_sw: user_sw {
+			gpios = <&gpio0_hi 13 (GPIO_ACTIVE_LOW)>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	pico_header: connector {
+		compatible = "raspberrypi,pico-header";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpio0 0 0>,	/* GP0 */
+			<1 0 &gpio0 1 0>,	/* GP1 */
+			<2 0 &gpio0 2 0>,	/* GP2 */
+			<3 0 &gpio0 3 0>,	/* GP3 */
+			<4 0 &gpio0 4 0>,	/* GP4 */
+			<5 0 &gpio0 5 0>,	/* GP5 */
+			<6 0 &gpio0 6 0>,	/* GP6 */
+			<7 0 &gpio0 7 0>,	/* GP7 */
+			<8 0 &gpio0 8 0>,	/* GP8 */
+			<9 0 &gpio0 9 0>,	/* GP9 */
+			<10 0 &gpio0 10 0>,	/* GP10 */
+			<11 0 &gpio0 11 0>,	/* GP11 */
+			<12 0 &gpio0 12 0>,	/* GP12 */
+			<13 0 &gpio0 13 0>,	/* GP13 */
+			<14 0 &gpio0 14 0>,	/* GP14 */
+			<15 0 &gpio0 15 0>,	/* GP15 */
+			<16 0 &gpio0 16 0>,	/* GP16 */
+			<17 0 &gpio0 17 0>,	/* GP17 */
+			<18 0 &gpio0 18 0>,	/* GP18 */
+			<19 0 &gpio0 19 0>,	/* GP19 */
+			<20 0 &gpio0 20 0>,	/* GP20 */
+			<21 0 &gpio0 21 0>,	/* GP21 */
+			<22 0 &gpio0 22 0>,	/* GP22 */
+			<26 0 &gpio0 26 0>,	/* GP26 */
+			<27 0 &gpio0 27 0>,	/* GP27 */
+			<28 0 &gpio0 28 0>;	/* GP28 */
+	};
+};
+
+&flash0 {
+	reg = <0x10000000 DT_SIZE_M(16)>;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* Reserved memory for an image definition block. The block is much
+		 * smaller than 256 bytes, but in practice the linker places the vector
+		 * table at a much larger alignment offset.
+		 */
+		image_def: partition@0 {
+			label = "image_def";
+			reg = <0x00000000 0x100>;
+			read-only;
+		};
+
+		/*
+		 * Usable flash. Starts at 0x100, after the image definition block.
+		 * The partition size is 16MB minus the 0x100 bytes taken by the
+		 * image definition.
+		 */
+		code_partition: partition@100 {
+			label = "code-partition";
+			reg = <0x100 (DT_SIZE_M(16) - 0x100)>;
+			read-only;
+		};
+	};
+};
+
+&uart0 {
+	current-speed = <115200>;
+	status = "okay";
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-names = "default";
+};
+
+gpio0_lo: &gpio0 {
+	status = "okay";
+};
+
+&gpio0_hi {
+	status = "okay";
+};
+
+&spi0 {
+	clock-frequency = <DT_FREQ_M(8)>;
+	pinctrl-0 = <&spi0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&adc {
+	pinctrl-0 = <&adc_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&pwm {
+	pinctrl-0 = <&pwm_ch4b_default>;
+	pinctrl-names = "default";
+	divider-int-0 = <255>;
+};
+
+&timer0 {
+	status = "okay";
+};
+
+zephyr_udc0: &usbd {
+	status = "okay";
+};
+
+
+pico_spi: &spi0 {};
+pico_i2c0: &i2c0 {};
+pico_i2c1: &i2c1 {};
+pico_serial: &uart0 {};
+stemma_qt_i2c: &i2c0 {};
diff --git a/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_m33.dts b/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_m33.dts
new file mode 100644
index 00000000000..425c2237f73
--- /dev/null
+++ b/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_m33.dts
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+/* The build system assumes that there's a cpucluster-specific file.
+ *
+ * This file provides composition of the device tree:
+ * 1. The common features of the SoC
+ * 2. Core-specific configuration.
+ * 3. Board-specific configuration.
+ */
+#include <raspberrypi/rpi_pico/rp2350b.dtsi>
+#include <raspberrypi/rpi_pico/m33.dtsi>
+
+/* there's nothing specific to the Cortex-M33 cores vs the (not yet
+ * implemented) Hazard3 cores.
+ */
+#include "pico_plus2.dtsi"
diff --git a/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_m33.yaml b/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_m33.yaml
new file mode 100644
index 00000000000..a3ac06cff12
--- /dev/null
+++ b/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_m33.yaml
@@ -0,0 +1,21 @@
+identifier: pico_plus2/rp2350b/m33
+name: Pimoroni Pico Plus 2 (Cortex-M33)
+type: mcu
+arch: arm
+flash: 16384
+ram: 8192
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - adc
+  - clock
+  - counter
+  - dma
+  - gpio
+  - hwinfo
+  - i2c
+  - pwm
+  - spi
+  - usbd
+  - uart
diff --git a/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_m33_defconfig b/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_m33_defconfig
new file mode 100644
index 00000000000..8bd68e35113
--- /dev/null
+++ b/boards/pimoroni/pico_plus2/pico_plus2_rp2350b_m33_defconfig
@@ -0,0 +1,14 @@
+# This configuration is orthogonal to whether the Cortex-M33 or Hazard3 cores
+# are in use, but Zephyr does not support providing a qualifier-agnostic
+# _defconfig file.
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_BUILD_OUTPUT_UF2=y
+CONFIG_CLOCK_CONTROL=y
+CONFIG_CONSOLE=y
+CONFIG_GPIO=y
+CONFIG_RESET=y
+CONFIG_SERIAL=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=150000000
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_USE_DT_CODE_PARTITION=y
diff --git a/boards/pimoroni/pico_plus2/support/openocd.cfg b/boards/pimoroni/pico_plus2/support/openocd.cfg
new file mode 100644
index 00000000000..82666bb5331
--- /dev/null
+++ b/boards/pimoroni/pico_plus2/support/openocd.cfg
@@ -0,0 +1,11 @@
+# Copyright (c) 2024 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+# Checking and set 'adapter speed'.
+# Set the adaptor speed, if unset, and given as an argument.
+proc set_adapter_speed_if_not_set { speed } {
+	puts "checking adapter speed..."
+	if { [catch {adapter speed} ret] } {
+		adapter speed $speed
+	}
+}
diff --git a/boards/pine64/pinetime_devkit0/doc/index.rst b/boards/pine64/pinetime_devkit0/doc/index.rst
index 097bbcf4a11..d6ab460723c 100644
--- a/boards/pine64/pinetime_devkit0/doc/index.rst
+++ b/boards/pine64/pinetime_devkit0/doc/index.rst
@@ -110,6 +110,8 @@ basic button sample:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The PineTime Dev Kit comes with the back not glued down to allow it to be
 easily reprogrammed.
 
diff --git a/boards/pine64/pinetime_devkit0/pinetime_devkit0.yaml b/boards/pine64/pinetime_devkit0/pinetime_devkit0.yaml
index 081daced8ab..10bee1f3d6b 100644
--- a/boards/pine64/pinetime_devkit0/pinetime_devkit0.yaml
+++ b/boards/pine64/pinetime_devkit0/pinetime_devkit0.yaml
@@ -5,9 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 512
-supported:
-  - kscan:touch
 vendor: pine64
diff --git a/boards/pjrc/teensy4/doc/teensy40.jpg b/boards/pjrc/teensy4/doc/img/teensy40.jpg
similarity index 100%
rename from boards/pjrc/teensy4/doc/teensy40.jpg
rename to boards/pjrc/teensy4/doc/img/teensy40.jpg
diff --git a/boards/pjrc/teensy4/doc/teensy41.jpg b/boards/pjrc/teensy4/doc/img/teensy41.jpg
similarity index 100%
rename from boards/pjrc/teensy4/doc/teensy41.jpg
rename to boards/pjrc/teensy4/doc/img/teensy41.jpg
diff --git a/boards/pjrc/teensy4/doc/index.rst b/boards/pjrc/teensy4/doc/index.rst
index 66aefe952c0..3517b1fb70f 100644
--- a/boards/pjrc/teensy4/doc/index.rst
+++ b/boards/pjrc/teensy4/doc/index.rst
@@ -5,72 +5,100 @@ PJRC TEENSY 4
 
 Overview
 ********
+
 The Teensy is a complete USB-based microcontroller development system, in a
 very small footprint, capable of implementing many types of projects. All
 programming is done via the USB port.
 
+.. tabs::
+
+   .. group-tab:: Teensy 4.0
+
+      .. figure:: img/teensy40.jpg
+           :align: center
+           :alt: TEENSY40
 
-.. figure:: teensy40.jpg
-   :align: center
-   :alt: TEENSY40
+           (Credit: https://www.pjrc.com)
 
-   TEENSY40 (Credit: https://www.pjrc.com)
+   .. group-tab:: Teensy 4.1
 
-.. figure:: teensy41.jpg
-   :align: center
-   :alt: TEENSY41
+      .. figure:: img/teensy41.jpg
+           :align: center
+           :alt: TEENSY41
 
-   TEENSY41 (Credit: https://www.pjrc.com)
+           (Credit: https://www.pjrc.com)
 
 Hardware
 ********
 
-Teensy 4.0:
+.. tabs::
+
+   .. group-tab:: Teensy 4.0
+
+      - MIMXRT1062DVL6A MCU (600 MHz, 1024 KB on-chip memory)
+      - 16 Mbit QSPI Flash
+      - User LED
+      - USB 2.0 host connector
+
+      See the `Teensy 4.0 Website`_ for a complete hardware description.
 
-- MIMXRT1062DVL6A MCU (600 MHz, 1024 KB on-chip memory)
-- 16 Mbit QSPI Flash
-- LED
-- USB 2.0 host connector
+   .. group-tab:: Teensy 4.1
 
-Teensy 4.1:
+      - MIMXRT1062DVJ6A MCU (600 MHz, 1024 KB on-chip memory)
+      - 64 Mbit QSPI Flash
+      - User LED
+      - USB 2.0 host connector
+      - USB 2.0 OTG connector
+      - 10/100 Mbit/s Ethernet transceiver
+      - TF socket for SD card
 
-- MIMXRT1062DVJ6A MCU (600 MHz, 1024 KB on-chip memory)
-- 64 Mbit QSPI Flash
-- LED
-- USB 2.0 host connector
-- USB 2.0 OTG connector
-- 10/100 Mbit/s Ethernet PHY
-- TF socket for SD card
+      To connect an Ethernet cable, additional `Teensy 4.1 Ethernet Kit`_ is required.
 
-See the `Teensy 4.0 Website`_ for a complete hardware description.
+      See the `Teensy 4.1 Website`_ for a complete hardware description.
+
+For more information, check the `i.MX RT1060 Datasheet`_.
 
 Supported Features
 ==================
 
-The teensy40 board configuration supports the following hardware
+The Teensy 4.0 board configuration supports the following hardware
 features:
 
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/pjrc/teensy4/teensy40_defconfig`
-
-The teensy41 board configuration supports additional hardware
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component     |
++===========+============+======================+
+| ADC       | on-chip    | adc                  |
++-----------+------------+----------------------+
+| CLOCK     | on-chip    | clock_control        |
++-----------+------------+----------------------+
+| FLASH     | on-chip    | flash                |
++-----------+------------+----------------------+
+| GPIO      | on-chip    | gpio                 |
++-----------+------------+----------------------+
+| I2C       | on-chip    | i2c                  |
++-----------+------------+----------------------+
+| I2S       | on-chip    | i2s                  |
++-----------+------------+----------------------+
+| NVIC      | on-chip    | arch/arm             |
++-----------+------------+----------------------+
+| PWM       | on-chip    | pwm                  |
++-----------+------------+----------------------+
+| RTC       | on-chip    | system clock         |
++-----------+------------+----------------------+
+| SPI       | on-chip    | spi                  |
++-----------+------------+----------------------+
+| CAN       | on-chip    | can                  |
++-----------+------------+----------------------+
+| UART      | on-chip    | serial               |
++-----------+------------+----------------------+
+| USB       | on-chip    | usb                  |
++-----------+------------+----------------------+
+| TRNG      | on-chip    | entropy              |
++-----------+------------+----------------------+
+| WDT       | on-chip    | watchdog             |
++-----------+------------+----------------------+
+
+The Teensy 4.1 board configuration supports additional hardware
 features:
 
 +-----------+------------+-------------------------------------+
@@ -81,10 +109,7 @@ features:
 | ENET      | on-chip    | ethernet                            |
 +-----------+------------+-------------------------------------+
 
-The default configuration can be found in
-:zephyr_file:`boards/pjrc/teensy4/teensy41_defconfig`
-
-Other hardware features are not currently supported by the port.
+Other hardware features have not been enabled yet for this board.
 
 Connections and IOs
 ===================
@@ -204,23 +229,97 @@ Programming and Debugging
 
 Flashing
 ========
-Build applications as usual (see :ref:`build_an_application` for more details).
 
-Flash hex-file with the documented tools:
+Both the Teensy 4.0 and Teensy 4.1 ship with a dedicated bootloader chip,
+which supports flashing using USB. This allows easy flashing of new images,
+but does not support debugging the device.
+
+#. Build the Zephyr kernel and the :zephyr:code-sample:`blinky` sample application.
+
+.. tabs::
+
+   .. group-tab:: Teensy 4.0
+
+      .. zephyr-app-commands::
+         :zephyr-app: samples/basic/blinky
+         :board: teensy40
+         :goals: build
+         :compact:
 
-.. _Teensy flash tools:
-   https://www.pjrc.com/teensy/loader.html
+   .. group-tab:: Teensy 4.1
 
-Debugging
-=========
-Console output is mapped to teensy pins 0 (RX1) and 1 (TX1). Connect a usb-to-serial adapter
-to use this serial console. Use the following settings with your serial terminal of choice (minicom, putty,
-etc.):
+      .. zephyr-app-commands::
+         :zephyr-app: samples/basic/blinky
+         :board: teensy41
+         :goals: build
+         :compact:
 
-- Speed: 115200
-- Data: 8 bits
-- Parity: None
-- Stop bits: 1
+#. Connect the board to your host computer using USB.
+
+#. Tap the reset button to enter bootloader mode.
+   Red LED blinks.
+
+#. Flash the image.
+
+.. tabs::
+
+   .. group-tab:: Teensy 4.0
+
+      .. zephyr-app-commands::
+         :zephyr-app: samples/basic/blinky
+         :board: teensy40
+         :goals: flash
+         :compact:
+
+   .. group-tab:: Teensy 4.1
+
+      .. zephyr-app-commands::
+         :zephyr-app: samples/basic/blinky
+         :board: teensy41
+         :goals: flash
+         :compact:
+
+#. You should see the orange LED blink.
+
+Configuring a Console
+=====================
+
+.. tabs::
+
+   .. group-tab:: UART-Console
+
+      By default console output is mapped to teensy pins 0 (RX1) and 1 (TX1). Connect a usb-to-serial adapter
+      to use this serial console. Use the following settings with your serial terminal of choice (minicom, putty,
+      etc.):
+
+      - Speed: 115200
+      - Data: 8 bits
+      - Parity: None
+      - Stop bits: 1
+
+   .. group-tab:: USB-Console
+
+      By mapping the console output to USB, a usb-to-serial adapter is no longer required.
+      Utilizing the :ref:`snippet-cdc-acm-console` and a config option will enable this feature.
+
+      #. If application code doesn´t enable USB device support, this must be done via Kconfig option.
+
+         .. code-block:: kconfig
+
+            CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=y
+
+      #. Build application including the snippet.
+
+         .. zephyr-app-commands::
+            :zephyr-app: samples/basic/blinky
+            :snippets: cdc-acm-console
+            :board: teensy41
+            :goals: flash
+            :compact:
+
+      #. After application startup a serial device named like
+         ``tty.usbmodem14203`` should appear on your host computer.
+         You can use e.g. ``Serial Monitor`` plugin for VScode to monitor.
 
 References
 **********
@@ -230,14 +329,11 @@ References
 .. _Teensy 4.0 Website:
    https://www.pjrc.com/store/teensy40.html
 
-.. _Teensy Schematics:
-   https://www.pjrc.com/teensy/schematic.html
+.. _Teensy 4.1 Website:
+   https://www.pjrc.com/store/teensy41.html
 
-.. _i.MX RT1060 Website:
-   https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-rt-series/i.mx-rt1060-crossover-processor-with-arm-cortex-m7-core:i.MX-RT1060
+.. _Teensy 4.1 Ethernet Kit:
+   https://www.pjrc.com/store/ethernet_kit.html
 
 .. _i.MX RT1060 Datasheet:
    https://www.nxp.com/docs/en/nxp/data-sheets/IMXRT1060CEC.pdf
-
-.. _i.MX RT1060 Reference Manual:
-   https://www.nxp.com/webapp/Download?colCode=IMXRT1060RM
diff --git a/boards/pjrc/teensy4/teensy40.yaml b/boards/pjrc/teensy4/teensy40.yaml
index 11a7f0b284d..a4908dc6abd 100644
--- a/boards/pjrc/teensy4/teensy40.yaml
+++ b/boards/pjrc/teensy4/teensy40.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 768
 flash: 2048
 supported:
diff --git a/boards/pjrc/teensy4/teensy41.yaml b/boards/pjrc/teensy4/teensy41.yaml
index 18f320a2df6..659f6838ffa 100644
--- a/boards/pjrc/teensy4/teensy41.yaml
+++ b/boards/pjrc/teensy4/teensy41.yaml
@@ -11,7 +11,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 768
 flash: 8192
 supported:
diff --git a/boards/qemu/arc/doc/index.rst b/boards/qemu/arc/doc/index.rst
index 1c38701b22e..ee73af20e9d 100644
--- a/boards/qemu/arc/doc/index.rst
+++ b/boards/qemu/arc/doc/index.rst
@@ -63,6 +63,8 @@ The following platform features are unsupported:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
 emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample
 (note you may use ``qemu_arc/qemu_em``, ``qemu_arc/qemu_hs``,  ``qemu_arc/qemu_hs5x`` or
diff --git a/boards/qemu/cortex_a53/doc/index.rst b/boards/qemu/cortex_a53/doc/index.rst
index d6e2e307b09..e56bbe27d1e 100644
--- a/boards/qemu/cortex_a53/doc/index.rst
+++ b/boards/qemu/cortex_a53/doc/index.rst
@@ -56,6 +56,8 @@ The following platform features are unsupported:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
 emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
 
diff --git a/boards/qemu/cortex_a53/qemu_cortex_a53.yaml b/boards/qemu/cortex_a53/qemu_cortex_a53.yaml
index 509a461422f..9701dbf5f1f 100644
--- a/boards/qemu/cortex_a53/qemu_cortex_a53.yaml
+++ b/boards/qemu/cortex_a53/qemu_cortex_a53.yaml
@@ -7,7 +7,8 @@ arch: arm64
 toolchain:
   - zephyr
   - cross-compile
-ram: 128
+ram: 131072
+flash: 65536
 testing:
   default: true
   ignore_tags:
diff --git a/boards/qemu/cortex_a9/qemu_cortex_a9.yaml b/boards/qemu/cortex_a9/qemu_cortex_a9.yaml
index eb3e9ccc2c2..b1ed651c830 100644
--- a/boards/qemu/cortex_a9/qemu_cortex_a9.yaml
+++ b/boards/qemu/cortex_a9/qemu_cortex_a9.yaml
@@ -14,7 +14,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - net
   - netif:eth
diff --git a/boards/qemu/cortex_m0/doc/index.rst b/boards/qemu/cortex_m0/doc/index.rst
index e091ace42a7..543c5870dd4 100644
--- a/boards/qemu/cortex_m0/doc/index.rst
+++ b/boards/qemu/cortex_m0/doc/index.rst
@@ -60,6 +60,8 @@ The following platform features are unsupported:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
 emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
 
diff --git a/boards/qemu/cortex_m0/qemu_cortex_m0.yaml b/boards/qemu/cortex_m0/qemu_cortex_m0.yaml
index 5d6f166eeb7..02703d6f35c 100644
--- a/boards/qemu/cortex_m0/qemu_cortex_m0.yaml
+++ b/boards/qemu/cortex_m0/qemu_cortex_m0.yaml
@@ -7,7 +7,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 16
 flash: 256
 testing:
diff --git a/boards/qemu/cortex_m3/doc/index.rst b/boards/qemu/cortex_m3/doc/index.rst
index 96eb19bc375..15562e066d9 100644
--- a/boards/qemu/cortex_m3/doc/index.rst
+++ b/boards/qemu/cortex_m3/doc/index.rst
@@ -66,6 +66,8 @@ The following platform features are unsupported:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
 emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
 
diff --git a/boards/qemu/cortex_m3/qemu_cortex_m3.yaml b/boards/qemu/cortex_m3/qemu_cortex_m3.yaml
index 70f17485495..3d27987244a 100644
--- a/boards/qemu/cortex_m3/qemu_cortex_m3.yaml
+++ b/boards/qemu/cortex_m3/qemu_cortex_m3.yaml
@@ -7,7 +7,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - netif:serial-net
   - gpio
diff --git a/boards/qemu/cortex_r5/doc/index.rst b/boards/qemu/cortex_r5/doc/index.rst
index 9d385b5a578..e717b14732f 100644
--- a/boards/qemu/cortex_r5/doc/index.rst
+++ b/boards/qemu/cortex_r5/doc/index.rst
@@ -60,6 +60,8 @@ The following platform features are unsupported:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Use this configuration to run basic Zephyr applications and kernel tests in the
 QEMU emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
 
diff --git a/boards/qemu/cortex_r5/qemu_cortex_r5.yaml b/boards/qemu/cortex_r5/qemu_cortex_r5.yaml
index 120c983fec2..392438c4e5d 100644
--- a/boards/qemu/cortex_r5/qemu_cortex_r5.yaml
+++ b/boards/qemu/cortex_r5/qemu_cortex_r5.yaml
@@ -7,7 +7,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 65536
 flash: 32768
 testing:
diff --git a/boards/qemu/kvm_arm64/doc/index.rst b/boards/qemu/kvm_arm64/doc/index.rst
index e1341211e46..a69b1357bae 100644
--- a/boards/qemu/kvm_arm64/doc/index.rst
+++ b/boards/qemu/kvm_arm64/doc/index.rst
@@ -48,6 +48,8 @@ CPU's UART0.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Refer to the qemu_cortex_a53 board instructions for this part.
 
 Debugging
diff --git a/boards/qemu/leon3/doc/index.rst b/boards/qemu/leon3/doc/index.rst
index 32a85ebbc5a..69db94575be 100644
--- a/boards/qemu/leon3/doc/index.rst
+++ b/boards/qemu/leon3/doc/index.rst
@@ -8,6 +8,8 @@ The LEON3 QEMU board configuration is used to emulate the LEON3 processor.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``qemu_leon3`` board configuration can be built and run in
 the usual way for emulated boards (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/qemu/leon3/qemu_leon3.yaml b/boards/qemu/leon3/qemu_leon3.yaml
index 9e21ec42bbb..58a38e2fb02 100644
--- a/boards/qemu/leon3/qemu_leon3.yaml
+++ b/boards/qemu/leon3/qemu_leon3.yaml
@@ -8,7 +8,6 @@ ram: 1048576
 flash: 524288
 toolchain:
   - zephyr
-  - xtools
 supported:
   - netif
 testing:
diff --git a/boards/qemu/malta/doc/index.rst b/boards/qemu/malta/doc/index.rst
index f10dcc8c8df..8668ddc9cda 100644
--- a/boards/qemu/malta/doc/index.rst
+++ b/boards/qemu/malta/doc/index.rst
@@ -54,6 +54,8 @@ with the FPGA UART2.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
 emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
 
diff --git a/boards/qemu/malta/qemu_malta.yaml b/boards/qemu/malta/qemu_malta.yaml
index 836d037aabb..db1040b3d9a 100644
--- a/boards/qemu/malta/qemu_malta.yaml
+++ b/boards/qemu/malta/qemu_malta.yaml
@@ -6,7 +6,6 @@ simulation:
 arch: mips
 toolchain:
   - zephyr
-  - xtools
 ram: 1024
 flash: 512
 testing:
diff --git a/boards/qemu/malta/qemu_malta_qemu_malta_be.yaml b/boards/qemu/malta/qemu_malta_qemu_malta_be.yaml
index a20cc223e85..aba9aa35864 100644
--- a/boards/qemu/malta/qemu_malta_qemu_malta_be.yaml
+++ b/boards/qemu/malta/qemu_malta_qemu_malta_be.yaml
@@ -6,7 +6,6 @@ simulation:
 arch: mips
 toolchain:
   - zephyr
-  - xtools
 ram: 1024
 flash: 512
 testing:
diff --git a/boards/qemu/nios2/doc/index.rst b/boards/qemu/nios2/doc/index.rst
index 81717ab91b4..235b9b41be4 100644
--- a/boards/qemu/nios2/doc/index.rst
+++ b/boards/qemu/nios2/doc/index.rst
@@ -70,6 +70,8 @@ The following platform features are unsupported:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
 emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
 
diff --git a/boards/qemu/nios2/qemu_nios2.yaml b/boards/qemu/nios2/qemu_nios2.yaml
index c0a3cf21644..816c280b5a0 100644
--- a/boards/qemu/nios2/qemu_nios2.yaml
+++ b/boards/qemu/nios2/qemu_nios2.yaml
@@ -8,7 +8,6 @@ ram: 128
 flash: 128
 toolchain:
   - zephyr
-  - xtools
 testing:
   default: true
   ignore_tags:
diff --git a/boards/qemu/riscv32/doc/index.rst b/boards/qemu/riscv32/doc/index.rst
index ef2e3f91623..69e003c21f8 100644
--- a/boards/qemu/riscv32/doc/index.rst
+++ b/boards/qemu/riscv32/doc/index.rst
@@ -8,6 +8,8 @@ The RISCV32 QEMU board configuration is used to emulate the RISCV32 architecture
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``qemu_riscv32`` board configuration can be built and run in
 the usual way for emulated boards (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/qemu/riscv32/qemu_riscv32.yaml b/boards/qemu/riscv32/qemu_riscv32.yaml
index 6421fe744bd..b6f258878a7 100644
--- a/boards/qemu/riscv32/qemu_riscv32.yaml
+++ b/boards/qemu/riscv32/qemu_riscv32.yaml
@@ -6,9 +6,10 @@ simulation:
 arch: riscv
 toolchain:
   - zephyr
-  - xtools
 supported:
   - netif
+ram: 262144
+flash: 32768
 testing:
   default: true
   ignore_tags:
diff --git a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml
index 368fa750090..ab001b71df1 100644
--- a/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml
+++ b/boards/qemu/riscv32/qemu_riscv32_qemu_virt_riscv32_smp.yaml
@@ -6,10 +6,11 @@ simulation:
 arch: riscv
 toolchain:
   - zephyr
-  - xtools
 supported:
   - netif
   - smp
+ram: 262144
+flash: 32768
 testing:
   default: true
   ignore_tags:
diff --git a/boards/qemu/riscv32_xip/doc/index.rst b/boards/qemu/riscv32_xip/doc/index.rst
index aea547ff75d..759892d5e14 100644
--- a/boards/qemu/riscv32_xip/doc/index.rst
+++ b/boards/qemu/riscv32_xip/doc/index.rst
@@ -8,6 +8,8 @@ The RISCV32 XIP QEMU board configuration is used to emulate the RISCV32 architec
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``qemu_riscv32_xip`` board configuration can be built and run in
 the usual way for emulated boards (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/qemu/riscv32_xip/qemu_riscv32_xip.yaml b/boards/qemu/riscv32_xip/qemu_riscv32_xip.yaml
index 2e21c4acd2f..c2270c4236f 100644
--- a/boards/qemu/riscv32_xip/qemu_riscv32_xip.yaml
+++ b/boards/qemu/riscv32_xip/qemu_riscv32_xip.yaml
@@ -7,7 +7,6 @@ arch: riscv
 ram: 16
 toolchain:
   - zephyr
-  - xtools
 testing:
   default: true
   only_tags:
diff --git a/boards/qemu/riscv32e/doc/index.rst b/boards/qemu/riscv32e/doc/index.rst
index 6b47c3a3639..a45687eeb7d 100644
--- a/boards/qemu/riscv32e/doc/index.rst
+++ b/boards/qemu/riscv32e/doc/index.rst
@@ -8,6 +8,8 @@ The RISCV32E QEMU board configuration is used to emulate the RISCV32 (RV32E) arc
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``qemu_riscv32e`` board configuration can be built and run in
 the usual way for emulated boards (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/qemu/riscv32e/qemu_riscv32e.yaml b/boards/qemu/riscv32e/qemu_riscv32e.yaml
index 8159d8c6292..89fdcc478f7 100644
--- a/boards/qemu/riscv32e/qemu_riscv32e.yaml
+++ b/boards/qemu/riscv32e/qemu_riscv32e.yaml
@@ -6,9 +6,10 @@ simulation:
 arch: riscv
 toolchain:
   - zephyr
-  - xtools
 supported:
   - netif
+ram: 262144
+flash: 32768
 testing:
   default: true
   ignore_tags:
diff --git a/boards/qemu/riscv64/doc/index.rst b/boards/qemu/riscv64/doc/index.rst
index 79d4f6d155f..884efce1f72 100644
--- a/boards/qemu/riscv64/doc/index.rst
+++ b/boards/qemu/riscv64/doc/index.rst
@@ -17,6 +17,8 @@ for more details.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``qemu_riscv64`` board configuration can be built and run in
 the usual way for emulated boards (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/qemu/riscv64/qemu_riscv64.yaml b/boards/qemu/riscv64/qemu_riscv64.yaml
index fc840e29886..240ebcdbde9 100644
--- a/boards/qemu/riscv64/qemu_riscv64.yaml
+++ b/boards/qemu/riscv64/qemu_riscv64.yaml
@@ -8,6 +8,8 @@ toolchain:
   - zephyr
 supported:
   - netif
+ram: 262144
+flash: 32768
 testing:
   default: true
   ignore_tags:
diff --git a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml
index 914aec92c1a..ebcfb42e1f0 100644
--- a/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml
+++ b/boards/qemu/riscv64/qemu_riscv64_qemu_virt_riscv64_smp.yaml
@@ -9,6 +9,8 @@ toolchain:
 supported:
   - netif
   - smp
+ram: 262144
+flash: 32768
 testing:
   default: true
   ignore_tags:
diff --git a/boards/qemu/x86/doc/index.rst b/boards/qemu/x86/doc/index.rst
index 98e0098d39a..3e6b147d2ab 100644
--- a/boards/qemu/x86/doc/index.rst
+++ b/boards/qemu/x86/doc/index.rst
@@ -67,6 +67,8 @@ The following platform features are unsupported:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``qemu_x86`` board configuration can be built and run in
 the usual way for emulated boards (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/qemu/x86/qemu_x86.yaml b/boards/qemu/x86/qemu_x86.yaml
index 09ed538e457..5188e5253b2 100644
--- a/boards/qemu/x86/qemu_x86.yaml
+++ b/boards/qemu/x86/qemu_x86.yaml
@@ -7,7 +7,6 @@ arch: x86
 ram: 3000
 toolchain:
   - zephyr
-  - xtools
   - llvm
 supported:
   - pci
diff --git a/boards/qemu/x86/qemu_x86_64.yaml b/boards/qemu/x86/qemu_x86_64.yaml
index 5811211385b..3fa3fd18a3c 100644
--- a/boards/qemu/x86/qemu_x86_64.yaml
+++ b/boards/qemu/x86/qemu_x86_64.yaml
@@ -4,7 +4,6 @@ type: qemu
 arch: x86
 toolchain:
   - zephyr
-  - xtools
 simulation:
   - name: qemu
 supported:
diff --git a/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml b/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml
index 943ee9ae0b6..c776a903163 100644
--- a/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml
+++ b/boards/qemu/x86/qemu_x86_64_atom_nokpti.yaml
@@ -4,7 +4,6 @@ type: qemu
 arch: x86
 toolchain:
   - zephyr
-  - xtools
 supported:
   - smp
 simulation:
diff --git a/boards/qemu/x86/qemu_x86_atom_nokpti.yaml b/boards/qemu/x86/qemu_x86_atom_nokpti.yaml
index 9620cfc0724..83a396d06db 100644
--- a/boards/qemu/x86/qemu_x86_atom_nokpti.yaml
+++ b/boards/qemu/x86/qemu_x86_atom_nokpti.yaml
@@ -6,7 +6,6 @@ simulation:
   - name: qemu
 toolchain:
   - zephyr
-  - xtools
 testing:
   default: true
   only_tags:
diff --git a/boards/qemu/x86/qemu_x86_atom_nommu.yaml b/boards/qemu/x86/qemu_x86_atom_nommu.yaml
index e8fac2e2f57..7e7042a1462 100644
--- a/boards/qemu/x86/qemu_x86_atom_nommu.yaml
+++ b/boards/qemu/x86/qemu_x86_atom_nommu.yaml
@@ -6,7 +6,6 @@ simulation:
   - name: qemu
 toolchain:
   - zephyr
-  - xtools
 testing:
   default: true
   only_tags:
diff --git a/boards/qemu/x86/qemu_x86_atom_nopae.yaml b/boards/qemu/x86/qemu_x86_atom_nopae.yaml
index 5809fec52fa..dfb264fb474 100644
--- a/boards/qemu/x86/qemu_x86_atom_nopae.yaml
+++ b/boards/qemu/x86/qemu_x86_atom_nopae.yaml
@@ -6,7 +6,6 @@ simulation:
   - name: qemu
 toolchain:
   - zephyr
-  - xtools
 testing:
   default: true
   only_tags:
diff --git a/boards/qemu/x86/qemu_x86_atom_virt.yaml b/boards/qemu/x86/qemu_x86_atom_virt.yaml
index 782a28ac688..8794d17df9f 100644
--- a/boards/qemu/x86/qemu_x86_atom_virt.yaml
+++ b/boards/qemu/x86/qemu_x86_atom_virt.yaml
@@ -6,7 +6,6 @@ simulation:
   - name: qemu
 toolchain:
   - zephyr
-  - xtools
 testing:
   default: true
   only_tags:
diff --git a/boards/qemu/x86/qemu_x86_atom_xip.yaml b/boards/qemu/x86/qemu_x86_atom_xip.yaml
index ec2cfb9104e..6607c68681f 100644
--- a/boards/qemu/x86/qemu_x86_atom_xip.yaml
+++ b/boards/qemu/x86/qemu_x86_atom_xip.yaml
@@ -6,7 +6,6 @@ simulation:
   - name: qemu
 toolchain:
   - zephyr
-  - xtools
 testing:
   default: true
   only_tags:
diff --git a/boards/qemu/x86/qemu_x86_lakemont.yaml b/boards/qemu/x86/qemu_x86_lakemont.yaml
index 7f153643b9e..3d6103d9404 100644
--- a/boards/qemu/x86/qemu_x86_lakemont.yaml
+++ b/boards/qemu/x86/qemu_x86_lakemont.yaml
@@ -6,7 +6,6 @@ simulation:
 arch: x86
 toolchain:
   - zephyr
-  - xtools
   - llvm
 testing:
   default: true
diff --git a/boards/qemu/x86/qemu_x86_tiny.yaml b/boards/qemu/x86/qemu_x86_tiny.yaml
index c09f5b51379..29197ecd6d8 100644
--- a/boards/qemu/x86/qemu_x86_tiny.yaml
+++ b/boards/qemu/x86/qemu_x86_tiny.yaml
@@ -6,7 +6,6 @@ simulation:
   - name: qemu
 toolchain:
   - zephyr
-  - xtools
 testing:
   default: true
   only_tags:
diff --git a/boards/qemu/xtensa/Kconfig.defconfig b/boards/qemu/xtensa/Kconfig.defconfig
index c94da322385..1acc6ce8d4e 100644
--- a/boards/qemu/xtensa/Kconfig.defconfig
+++ b/boards/qemu/xtensa/Kconfig.defconfig
@@ -11,6 +11,7 @@ config IPM_CONSOLE_STACK_SIZE
 
 # Must match XCHAL_DCACHE_LINESIZE form core-isa.h
 config DCACHE_LINE_SIZE
+	default 4 if BOARD_QEMU_XTENSA_SAMPLE_CONTROLLER32_MPU
 	default 32
 
 endif # BOARD_QEMU_XTENSA
diff --git a/boards/qemu/xtensa/doc/index.rst b/boards/qemu/xtensa/doc/index.rst
index 741e0569b7f..0ad63fe7fdd 100644
--- a/boards/qemu/xtensa/doc/index.rst
+++ b/boards/qemu/xtensa/doc/index.rst
@@ -9,6 +9,8 @@ configuration provides support for the Xtensa simulation environment.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Use this configuration to run basic Zephyr applications and kernel tests in the QEMU
 emulated environment, for example, with the :zephyr:code-sample:`synchronization` sample:
 
diff --git a/boards/qemu/xtensa/qemu_xtensa_dc233c.yaml b/boards/qemu/xtensa/qemu_xtensa_dc233c.yaml
index c0fd17ab84c..0a69c0347c7 100644
--- a/boards/qemu/xtensa/qemu_xtensa_dc233c.yaml
+++ b/boards/qemu/xtensa/qemu_xtensa_dc233c.yaml
@@ -6,10 +6,11 @@ simulation:
 arch: xtensa
 toolchain:
   - zephyr
-  - xtools
 testing:
   default: true
   ignore_tags:
     - net
     - bluetooth
 vendor: cdns
+ram: 16384
+flash: 32768
diff --git a/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.yaml b/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.yaml
index b9bbbd89698..136ac569f9c 100644
--- a/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.yaml
+++ b/boards/qemu/xtensa/qemu_xtensa_dc233c_mmu.yaml
@@ -6,7 +6,6 @@ simulation:
 arch: xtensa
 toolchain:
   - zephyr
-  - xtools
 testing:
   default: true
   ignore_tags:
diff --git a/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.yaml b/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.yaml
index 6503c5a3aae..b394aee0307 100644
--- a/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.yaml
+++ b/boards/qorvo/decawave_dwm1001_dev/decawave_dwm1001_dev.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 512
 supported:
diff --git a/boards/qorvo/decawave_dwm1001_dev/doc/index.rst b/boards/qorvo/decawave_dwm1001_dev/doc/index.rst
index 491851f3075..108d245f936 100644
--- a/boards/qorvo/decawave_dwm1001_dev/doc/index.rst
+++ b/boards/qorvo/decawave_dwm1001_dev/doc/index.rst
@@ -15,6 +15,8 @@ official reference on the IC itself.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``decawave_dwm1001_dev`` board configuration can be built,
 flashed, and debugged in the usual way. See :ref:`build_an_application` and
 :ref:`application_run` for more details on building and running.
diff --git a/boards/qorvo/decawave_dwm3001cdk/board.yml b/boards/qorvo/decawave_dwm3001cdk/board.yml
index e62aeef1789..a3a6a767b9c 100644
--- a/boards/qorvo/decawave_dwm3001cdk/board.yml
+++ b/boards/qorvo/decawave_dwm3001cdk/board.yml
@@ -1,5 +1,6 @@
 board:
   name: decawave_dwm3001cdk
+  full_name: Decawave DWM3001CDK
   vendor: qorvo
   socs:
   - name: nrf52833
diff --git a/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk.yaml b/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk.yaml
index 50fdad0ba87..da6ecebeea3 100644
--- a/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk.yaml
+++ b/boards/qorvo/decawave_dwm3001cdk/decawave_dwm3001cdk.yaml
@@ -8,7 +8,6 @@ vendor: decawave
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - usb_device
diff --git a/boards/qorvo/decawave_dwm3001cdk/doc/index.rst b/boards/qorvo/decawave_dwm3001cdk/doc/index.rst
index ada232518fe..588c2ec7a4a 100644
--- a/boards/qorvo/decawave_dwm3001cdk/doc/index.rst
+++ b/boards/qorvo/decawave_dwm3001cdk/doc/index.rst
@@ -1,7 +1,4 @@
-.. _decawave_dwm3001cdk:
-
-Decawave DWM3001CDK
-###################
+.. zephyr:board:: decawave_dwm3001cdk
 
 Overview
 ********
@@ -18,6 +15,8 @@ itself, and `nRF52833 website`_ for the official reference on the IC itself.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``decawave_dwm3001cdk`` board target can be built, flashed,
 and debugged in the usual way. See :ref:`build_an_application` and
 :ref:`application_run` for more details on building and running.
diff --git a/boards/quicklogic/qomu/qomu.yaml b/boards/quicklogic/qomu/qomu.yaml
index 7e47a163ac9..ca9d4a7edc2 100644
--- a/boards/quicklogic/qomu/qomu.yaml
+++ b/boards/quicklogic/qomu/qomu.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 testing:
   ignore_tags:
     - net
diff --git a/boards/quicklogic/quick_feather/doc/index.rst b/boards/quicklogic/quick_feather/doc/index.rst
index 11394643956..8a8f1a4364d 100644
--- a/boards/quicklogic/quick_feather/doc/index.rst
+++ b/boards/quicklogic/quick_feather/doc/index.rst
@@ -23,19 +23,7 @@ Detailed information about the board can be found in a `QuickFeather repository`
 Supported Features
 ==================
 
-The QuickFeather configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/quicklogic/quick_feather/quick_feather_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -45,6 +33,8 @@ Detailed information about pinouts is available in the `schematics document`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/quicklogic/quick_feather/quick_feather.yaml b/boards/quicklogic/quick_feather/quick_feather.yaml
index 9342b75994e..29e067d1aa1 100644
--- a/boards/quicklogic/quick_feather/quick_feather.yaml
+++ b/boards/quicklogic/quick_feather/quick_feather.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 testing:
   ignore_tags:
     - net
diff --git a/boards/rakwireless/rak11720/doc/index.rst b/boards/rakwireless/rak11720/doc/index.rst
index cae97f57c14..081753fbfd6 100644
--- a/boards/rakwireless/rak11720/doc/index.rst
+++ b/boards/rakwireless/rak11720/doc/index.rst
@@ -37,36 +37,13 @@ For more information about the RAK11720 stamp module:
 Supported Features
 ==================
 
-The RAK11720 module configuration supports the following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| SYSTICK   | on-chip    | systick              |
-+-----------+------------+----------------------+
-| STIMER    | on-chip    | stimer               |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | bluetooth            |
-+-----------+------------+----------------------+
-| RADIO     | on-board   | LoRa (SX1262)        |
-+-----------+------------+----------------------+
-
-The default configuration can be found in the defconfig file:
-``boards/rak/rak11720/rak11720_defconfig``.
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 =========================
 
+.. zephyr:board-supported-runners::
+
 The RAK11720 board shall be connected to a Segger Embedded Debugger Unit
 `J-Link OB <https://www.segger.com/jlink-ob.html>`_. This provides a debug
 interface to the Apollo3 Blue chip. You can use JLink to communicate with
diff --git a/boards/rakwireless/rak11720/rak11720.dts b/boards/rakwireless/rak11720/rak11720.dts
index 828c676f0dd..6596d689962 100644
--- a/boards/rakwireless/rak11720/rak11720.dts
+++ b/boards/rakwireless/rak11720/rak11720.dts
@@ -105,42 +105,48 @@
 	status = "okay";
 };
 
-&i2c2 {
-	compatible = "ambiq,i2c";
-	pinctrl-0 = <&i2c2_default>;
-	pinctrl-names = "default";
-	clock-frequency = <I2C_BITRATE_STANDARD>;
-	status = "okay";
+&iom2 {
+	i2c2: i2c {
+		compatible = "ambiq,i2c";
+		pinctrl-0 = <&i2c2_default>;
+		pinctrl-names = "default";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		status = "okay";
+	};
 };
 
-&spi0 {
-	compatible = "ambiq,spi";
-	pinctrl-0 = <&spi0_default>;
-	pinctrl-names = "default";
-	cs-gpios = <&gpio0_31 1 GPIO_ACTIVE_LOW>;
-	clock-frequency = <DT_FREQ_M(1)>;
-	status = "okay";
+&iom0 {
+	spi0: spi {
+		compatible = "ambiq,spi";
+		pinctrl-0 = <&spi0_default>;
+		pinctrl-names = "default";
+		cs-gpios = <&gpio0_31 1 GPIO_ACTIVE_LOW>;
+		clock-frequency = <DT_FREQ_M(1)>;
+		status = "okay";
+	};
 };
 
-&spi1 {
-	compatible = "ambiq,spi";
-	status = "okay";
-	pinctrl-0 = <&spi1_default>;
-	pinctrl-names = "default";
-	clock-frequency = <DT_FREQ_M(1)>;
-	cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
-
-	lora: lora@0 {
-		compatible = "semtech,sx1262";
-		reg = <0>;
-		reset-gpios = <&gpio0_31 17 GPIO_ACTIVE_LOW>;
-		busy-gpios = <&gpio0_31 16 GPIO_ACTIVE_HIGH>;
-		dio1-gpios = <&gpio0_31 15 GPIO_ACTIVE_HIGH>;
-		antenna-enable-gpios = <&gpio0_31 18 GPIO_ACTIVE_LOW>;
-		dio2-tx-enable;
-		dio3-tcxo-voltage = <SX126X_DIO3_TCXO_3V3>;
-		tcxo-power-startup-delay-ms = <5>;
-		spi-max-frequency = <DT_FREQ_M(1)>;
+&iom1 {
+	spi1: spi {
+		compatible = "ambiq,spi";
+		status = "okay";
+		pinctrl-0 = <&spi1_default>;
+		pinctrl-names = "default";
+		clock-frequency = <DT_FREQ_M(1)>;
+		cs-gpios = <&gpio0_31 11 GPIO_ACTIVE_LOW>;
+
+		lora: lora@0 {
+			compatible = "semtech,sx1262";
+			reg = <0>;
+			reset-gpios = <&gpio0_31 17 GPIO_ACTIVE_LOW>;
+			busy-gpios = <&gpio0_31 16 GPIO_ACTIVE_HIGH>;
+			dio1-gpios = <&gpio0_31 15 GPIO_ACTIVE_HIGH>;
+			antenna-enable-gpios = <&gpio0_31 18 GPIO_ACTIVE_LOW>;
+			dio2-tx-enable;
+			dio3-tcxo-voltage = <SX126X_DIO3_TCXO_3V3>;
+			tcxo-power-startup-delay-ms = <5>;
+			spi-max-frequency = <DT_FREQ_M(1)>;
+		};
 	};
 };
 
diff --git a/boards/rakwireless/rak11720/rak11720_apollo3-pinctrl.dtsi b/boards/rakwireless/rak11720/rak11720_apollo3-pinctrl.dtsi
index dbfd0ab8796..2f4d692a064 100644
--- a/boards/rakwireless/rak11720/rak11720_apollo3-pinctrl.dtsi
+++ b/boards/rakwireless/rak11720/rak11720_apollo3-pinctrl.dtsi
@@ -108,7 +108,7 @@
 			pinmux = <NCE19_P19>;
 			drive-push-pull;
 			drive-strength = "0.5";
-			ambiq,iom-nce-module = <0>;
+			ambiq,nce-src = <0>;
 			ambiq,iom-num = <6>;
 		};
 	};
diff --git a/boards/rakwireless/rak3172/Kconfig.rak3172 b/boards/rakwireless/rak3172/Kconfig.rak3172
new file mode 100644
index 00000000000..bdb0e9d6de1
--- /dev/null
+++ b/boards/rakwireless/rak3172/Kconfig.rak3172
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Kenneth Lu <kuohsianglu@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RAK3172
+	select SOC_STM32WLE5XX
diff --git a/boards/rakwireless/rak3172/board.cmake b/boards/rakwireless/rak3172/board.cmake
new file mode 100644
index 00000000000..8d07af62873
--- /dev/null
+++ b/boards/rakwireless/rak3172/board.cmake
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Kenneth Lu <kuohsianglu@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(pyocd "--target=stm32wle5ccux")
+board_runner_args(pyocd "--flash-opt=-O cmsis_dap.limit_packets=1")
+board_runner_args(jlink "--device=STM32WLE5CC" "--speed=4000" "--reset-after-load")
+
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/rakwireless/rak3172/board.yml b/boards/rakwireless/rak3172/board.yml
new file mode 100644
index 00000000000..0e6400c3aee
--- /dev/null
+++ b/boards/rakwireless/rak3172/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: rak3172
+  full_name: RAK3172
+  vendor: rakwireless
+  socs:
+  - name: stm32wle5xx
diff --git a/boards/rakwireless/rak3172/doc/img/pinout.webp b/boards/rakwireless/rak3172/doc/img/pinout.webp
new file mode 100644
index 00000000000..038a4ba2a5e
Binary files /dev/null and b/boards/rakwireless/rak3172/doc/img/pinout.webp differ
diff --git a/boards/rakwireless/rak3172/doc/img/rak3172.webp b/boards/rakwireless/rak3172/doc/img/rak3172.webp
new file mode 100644
index 00000000000..af4904399ed
Binary files /dev/null and b/boards/rakwireless/rak3172/doc/img/rak3172.webp differ
diff --git a/boards/rakwireless/rak3172/doc/index.rst b/boards/rakwireless/rak3172/doc/index.rst
new file mode 100644
index 00000000000..f251c41ace3
--- /dev/null
+++ b/boards/rakwireless/rak3172/doc/index.rst
@@ -0,0 +1,93 @@
+.. zephyr:board:: rak3172
+
+Overview
+********
+
+RAK3172 is a WisDuo LPWAN module which integrating a STM32WLE5CC chip.
+The breakout board has the RAK3172 as its core and with soldered to the
+antenna connector.
+
+Hardware
+********
+
+The breakout board footprint allows RAK3172 stamp module pins to be transferred to 2.54 mm headers.
+It is designed to easy access to the pins on the board and simplify the evaluation of the RAK3172
+module.
+
+- RAK3172 STM32WLE5CC Module with LPWAN single-core Cortex®-M4 at 48 MHz
+- 256-Kbyte Flash memory and 64-Kbyte SRAM
+- RF transceiver LoRa® modulations
+- Hardware encryption AES256-bit and a True random number generator
+- SMA connectors for the LORA antenna
+- I/O ports:
+
+   - UART
+   - I2C
+   - SPI
+   - SWD
+
+.. image:: img/pinout.webp
+   :align: center
+   :alt: RAK3172-pinout
+
+For more information about the RAK3172 stamp module:
+
+- `WisDuo RAK3172 Website`_
+- `STM32WLE5CC on www.st.com`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+=========================
+
+.. zephyr:board-supported-runners::
+
+The RAK3172 board can be debugged and flashed with an external debug probe connected
+to the SWD pins.
+It can also be flashed via `pyOCD`_, but have to install an additional pack to support STM32WL.
+
+.. code-block:: console
+
+   $ pyocd pack --update
+   $ pyocd pack --install stm32wl
+
+Flashing an application
+-----------------------
+
+Connect the board to your host computer and build and flash an application.
+The sample application :zephyr:code-sample:`hello_world` is used for this example.
+Build the Zephyr kernel and application, then flash it to the device:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rak3172
+   :goals: build flash
+
+Run a serial terminal to connect with your board. By default, ``usart1`` is
+accessible via the USB to TTL converter.
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+.. code-block:: console
+
+   Hello World! rak3172/stm32wle5xx
+
+References
+**********
+
+.. target-notes::
+
+.. _WisDuo RAK3172 Website:
+   https://docs.rakwireless.com/Product-Categories/WisDuo/RAK3172-Module/Overview/#product-description
+
+.. _STM32WLE5CC on www.st.com:
+   https://www.st.com/en/microcontrollers-microprocessors/stm32wle5cc.html
+
+.. _pyOCD:
+   https://github.com/pyocd/pyOCD
diff --git a/boards/rakwireless/rak3172/rak3172.dts b/boards/rakwireless/rak3172/rak3172.dts
new file mode 100644
index 00000000000..afd16df61c0
--- /dev/null
+++ b/boards/rakwireless/rak3172/rak3172.dts
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2024 Kenneth Lu <kuohsianglu@gmail.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/wl/stm32wle5Xc.dtsi>
+#include <st/wl/stm32wle5ccux-pinctrl.dtsi>
+
+/ {
+	model = "RAKWireless RAK3172 WisDuo LPWAN Module with a STM32WLE5CC SoC";
+	compatible = "stm32,rak3172_stm32wl";
+
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		blue_led: led_2 {
+			gpios = <&gpioa 1 GPIO_ACTIVE_HIGH>;
+			label = "Blue LED";
+		};
+
+		green_led: led_1 {
+			gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
+			label = "Green LED";
+		};
+	};
+
+	aliases {
+		led0 = &green_led;
+		lora0 = &lora;
+		watchdog0 = &iwdg;
+	};
+};
+
+&lptim1 {
+	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
+		 <&rcc STM32_SRC_LSI LPTIM1_SEL(1)>;
+	status = "okay";
+};
+
+&clk_lsi {
+	status = "okay";
+};
+
+&pll {
+	div-m = <1>;
+	mul-n = <6>;
+	div-r = <2>;
+	div-q = <2>;
+	clocks = <&clk_hsi>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(48)>;
+	cpu1-prescaler = <1>;
+	ahb3-prescaler = <1>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+};
+
+&usart1 {
+	pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&usart2 {
+	pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_scl_pa12 &i2c2_sda_pa11>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&spi1 {
+	pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5
+		     &spi1_miso_pa6 &spi1_mosi_pa7>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&rtc {
+	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
+		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
+	status = "okay";
+};
+
+&iwdg {
+	status = "okay";
+};
+
+&aes {
+	status = "okay";
+};
+
+&rng {
+	status = "okay";
+};
+
+&clk_lse {
+	clock-frequency = <32768>;
+};
+
+&clk_hsi {
+	status = "okay";
+};
+
+&subghzspi {
+	status = "okay";
+
+	lora: radio@0 {
+		status = "okay";
+		tx-enable-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; /* FE_CTRL1 */
+		rx-enable-gpios = <&gpiob 8 GPIO_ACTIVE_LOW>;  /* FE_CTRL2 */
+		power-amplifier-output = "rfo-lp";
+		rfo-lp-max-power = <14>;
+	};
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 DT_SIZE_K(32)>;
+			read-only;
+		};
+
+		slot0_partition: partition@8000 {
+			label = "image-0";
+			reg = <0x00008000 DT_SIZE_K(108)>;
+		};
+
+		slot1_partition: partition@23000 {
+			label = "image-1";
+			reg = <0x00023000 DT_SIZE_K(108)>;
+		};
+
+		storage_partition: partition@3e000 {
+			label = "storage";
+			reg = <0x0003e000 DT_SIZE_K(8)>;
+		};
+	};
+};
diff --git a/boards/rakwireless/rak3172/rak3172.yaml b/boards/rakwireless/rak3172/rak3172.yaml
new file mode 100644
index 00000000000..75017423ed6
--- /dev/null
+++ b/boards/rakwireless/rak3172/rak3172.yaml
@@ -0,0 +1,19 @@
+identifier: rak3172
+name: RAK3172 LoRa STM32WL
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 64
+flash: 256
+supported:
+  - counter
+  - gpio
+  - i2c
+  - nvs
+  - spi
+  - uart
+  - watchdog
+  - lora
+vendor: rak
diff --git a/boards/rakwireless/rak3172/rak3172_defconfig b/boards/rakwireless/rak3172/rak3172_defconfig
new file mode 100644
index 00000000000..a177820ad78
--- /dev/null
+++ b/boards/rakwireless/rak3172/rak3172_defconfig
@@ -0,0 +1,18 @@
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable Clocks
+CONFIG_CLOCK_CONTROL=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
diff --git a/boards/rakwireless/rak4631/doc/index.rst b/boards/rakwireless/rak4631/doc/index.rst
index 5d237f7bf71..ad14745fbbb 100644
--- a/boards/rakwireless/rak4631/doc/index.rst
+++ b/boards/rakwireless/rak4631/doc/index.rst
@@ -33,45 +33,7 @@ programming/debug interface.
 Supported Features
 ==================
 
-The ``rak4631/nrf52840`` board configuration supports the following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RADIO     | on-board   | LoRa (SX1262)        |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-The default board configuration can be found in
-:zephyr_file:`boards/rakwireless/rak4631/rak4631_nrf52840_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -85,6 +47,8 @@ LED
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The RAK4631 board shall be connected to a Segger Embedded Debugger Unit
 `J-Link OB <https://www.segger.com/jlink-ob.html>`_.  This provides a debug
 interface to the NRF52840 chip. You can use JLink to communicate with
diff --git a/boards/rakwireless/rak4631/rak4631_nrf52840.dts b/boards/rakwireless/rak4631/rak4631_nrf52840.dts
index de485c86bc1..5c9b846edf6 100644
--- a/boards/rakwireless/rak4631/rak4631_nrf52840.dts
+++ b/boards/rakwireless/rak4631/rak4631_nrf52840.dts
@@ -56,6 +56,7 @@
 
 &uicr {
 	gpio-as-nreset;
+	nfct-pins-as-gpios;
 };
 
 &gpiote {
@@ -118,7 +119,6 @@
 		reg = <0>;
 		reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;
 		busy-gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
-		tx-enable-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
 		rx-enable-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
 		dio1-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
 		dio2-tx-enable;
diff --git a/boards/rakwireless/rak4631/rak4631_nrf52840.yaml b/boards/rakwireless/rak4631/rak4631_nrf52840.yaml
index f8b3e235826..342b30b8f7f 100644
--- a/boards/rakwireless/rak4631/rak4631_nrf52840.yaml
+++ b/boards/rakwireless/rak4631/rak4631_nrf52840.yaml
@@ -7,7 +7,6 @@ ram: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - ble
diff --git a/boards/rakwireless/rak5010/doc/index.rst b/boards/rakwireless/rak5010/doc/index.rst
index 3ffc2b7f712..5c76ad0d9a2 100644
--- a/boards/rakwireless/rak5010/doc/index.rst
+++ b/boards/rakwireless/rak5010/doc/index.rst
@@ -1,8 +1,5 @@
 .. zephyr:board:: rak5010
 
-RAK5010
-#######
-
 Overview
 ********
 
@@ -44,42 +41,7 @@ Hardware
 Supported Features
 ==================
 
-The ``rak5010/nrf52840`` board configuration supports the following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -93,6 +55,8 @@ LED
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The RAK5010 board shall be connected to a Segger Embedded Debugger Unit
 `J-Link OB <https://www.segger.com/jlink-ob.html>`_.  This provides a debug
 interface to the NRF52840 chip. You can use JLink to communicate with
diff --git a/boards/rakwireless/rak5010/rak5010_nrf52840.yaml b/boards/rakwireless/rak5010/rak5010_nrf52840.yaml
index 2b947436b26..41c9a3e3789 100644
--- a/boards/rakwireless/rak5010/rak5010_nrf52840.yaml
+++ b/boards/rakwireless/rak5010/rak5010_nrf52840.yaml
@@ -7,7 +7,6 @@ ram: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - ble
diff --git a/boards/raspberrypi/rpi_4b/doc/index.rst b/boards/raspberrypi/rpi_4b/doc/index.rst
index 88862cf7f9f..b0c658faf2d 100644
--- a/boards/raspberrypi/rpi_4b/doc/index.rst
+++ b/boards/raspberrypi/rpi_4b/doc/index.rst
@@ -10,33 +10,14 @@ see <https://www.raspberrypi.com/documentation/computers/raspberry-pi.html>
 
 Supported Features
 ==================
-The Raspberry Pi 4 Model B board configuration supports the following
-hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - GIC-400
-     - N/A
-     - :dtcompatible:`arm,gic-v2`
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`brcm,bcm2711-gpio`
-   * - UART (Mini UART)
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`brcm,bcm2711-aux-uart`
-
-Other hardware features have not been enabled yet for this board.
-
-The default configuration can be found in
-:zephyr_file:`boards/raspberrypi/rpi_4b/rpi_4b_defconfig`
+
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 TF Card
 =======
 
diff --git a/boards/raspberrypi/rpi_5/doc/index.rst b/boards/raspberrypi/rpi_5/doc/index.rst
index d503f573df3..e73e65570db 100644
--- a/boards/raspberrypi/rpi_5/doc/index.rst
+++ b/boards/raspberrypi/rpi_5/doc/index.rst
@@ -29,35 +29,15 @@ Hardware
 Supported Features
 ==================
 
-The Raspberry Pi 5 board configuration supports the following hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - GIC-400
-     - N/A
-     - :dtcompatible:`arm,gic-v2`
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`raspberrypi,rp1-gpio`
-   * - GPIO (Internal)
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`brcm,brcmstb-gpio`
-   * - UART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`arm,pl011`
-
-Not all hardware features are supported yet. See `Raspberry Pi hardware`_ for the complete list of hardware features.
-
-The default configuration can be found in
-:zephyr_file:`boards/raspberrypi/rpi_5/rpi_5_defconfig`.
+.. zephyr:board-supported-hw::
+
+See `Raspberry Pi hardware`_ for the complete list of hardware features.
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Blinky
 ======
 
diff --git a/boards/raspberrypi/rpi_5/rpi_5.dts b/boards/raspberrypi/rpi_5/rpi_5.dts
index adba94d9474..3f942d4e6f5 100644
--- a/boards/raspberrypi/rpi_5/rpi_5.dts
+++ b/boards/raspberrypi/rpi_5/rpi_5.dts
@@ -23,6 +23,7 @@
 		zephyr,sram = &sram0;
 		zephyr,console = &uart10;
 		zephyr,shell-uart = &uart10;
+		zephyr,pcie-controller = &pcie1;
 	};
 
 	leds {
diff --git a/boards/raspberrypi/rpi_5/rpi_5_defconfig b/boards/raspberrypi/rpi_5/rpi_5_defconfig
index bc0375e8120..55855307b4d 100644
--- a/boards/raspberrypi/rpi_5/rpi_5_defconfig
+++ b/boards/raspberrypi/rpi_5/rpi_5_defconfig
@@ -8,3 +8,6 @@ CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME=y
 CONFIG_SERIAL=y
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
+
+CONFIG_PCIE=y
+CONFIG_PCIE_CONTROLLER=y
diff --git a/boards/raspberrypi/rpi_pico/doc/index.rst b/boards/raspberrypi/rpi_pico/doc/index.rst
index 71f5b42003e..b82b484f4f2 100644
--- a/boards/raspberrypi/rpi_pico/doc/index.rst
+++ b/boards/raspberrypi/rpi_pico/doc/index.rst
@@ -3,16 +3,20 @@
 Overview
 ********
 
-The Raspberry Pi Pico and Pico W are small, low-cost, versatile boards from
-Raspberry Pi. They are equipped with an RP2040 SoC, an on-board LED,
-a USB connector, and an SWD interface. The Pico W additionally contains an
-Infineon CYW43439 2.4 GHz Wi-Fi/Bluetooth module. The USB bootloader allows the
-ability to flash without any adapter, in a drag-and-drop manner.
+The `Raspberry Pi Pico`_ and Pico W are small, low-cost, versatile boards from
+Raspberry Pi. They are equipped with an `RP2040 <RP2040_Datasheet>`_ SoC, an on-board LED,
+a USB connector, and an SWD interface.
+
+The Pico W additionally contains an `Infineon CYW43439`_ 2.4 GHz Wi-Fi/Bluetooth module.
+
+The USB bootloader allows the ability to flash without any adapter,
+in a drag-and-drop manner.
 It is also possible to flash and debug the boards with their SWD interface,
 using an external adapter.
 
 Hardware
 ********
+
 - Dual core Arm Cortex-M0+ processor running up to 133MHz
 - 264KB on-chip SRAM
 - 2MB on-board QSPI flash with XIP capabilities
@@ -44,57 +48,7 @@ Hardware
 Supported Features
 ==================
 
-The rpi_pico board configuration supports the following
-hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v6m-nvic`
-   * - UART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`raspberrypi,pico-uart`
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`raspberrypi,pico-gpio`
-   * - ADC
-     - :kconfig:option:`CONFIG_ADC`
-     - :dtcompatible:`raspberrypi,pico-adc`
-   * - I2C
-     - :kconfig:option:`CONFIG_I2C`
-     - :dtcompatible:`snps,designware-i2c`
-   * - SPI
-     - :kconfig:option:`CONFIG_SPI`
-     - :dtcompatible:`raspberrypi,pico-spi`
-   * - USB Device
-     - :kconfig:option:`CONFIG_USB_DEVICE_STACK`
-     - :dtcompatible:`raspberrypi,pico-usbd`
-   * - HWINFO
-     - :kconfig:option:`CONFIG_HWINFO`
-     - N/A
-   * - Watchdog Timer (WDT)
-     - :kconfig:option:`CONFIG_WATCHDOG`
-     - :dtcompatible:`raspberrypi,pico-watchdog`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM`
-     - :dtcompatible:`raspberrypi,pico-pwm`
-   * - Flash
-     - :kconfig:option:`CONFIG_FLASH`
-     - :dtcompatible:`raspberrypi,pico-flash`
-   * - Clock controller
-     - :kconfig:option:`CONFIG_CLOCK_CONTROL`
-     - :dtcompatible:`raspberrypi,pico-clock-controller`
-   * - UART (PIO)
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`raspberrypi,pico-uart-pio`
-   * - SPI (PIO)
-     - :kconfig:option:`CONFIG_SPI`
-     - :dtcompatible:`raspberrypi,pico-spi-pio`
+.. zephyr:board-supported-hw::
 
 .. _rpi_pico_pin_mapping:
 
@@ -133,7 +87,8 @@ Default Zephyr Peripheral Mapping:
 
 Programmable I/O (PIO)
 **********************
-The RP2040 SoC comes with two PIO periherals. These are two simple
+
+The RP2040 SoC comes with two PIO peripherals. These are two simple
 co-processors that are designed for I/O operations. The PIOs run
 a custom instruction set, generated from a custom assembly language.
 PIO programs are assembled using :command:`pioasm`, a tool provided by Raspberry Pi.
@@ -152,9 +107,38 @@ combination of GPIO pins for an SPI bus, as well as allowing up to
 four independent SPI buses on a single board (using the two SPI
 devices as well as both PIO devices).
 
+.. _rpi_pico_pio_based_features:
+
+PIO Based Features
+==================
+
+Raspberry Pi Pico's PIO is a programmable chip that can implement a variety of peripherals.
+
+.. list-table::
+   :header-rows: 1
+
+   * - Peripheral
+     - Kconfig option
+     - Devicetree compatible
+   * - UART (PIO)
+     - :kconfig:option:`CONFIG_SERIAL`
+     - :dtcompatible:`raspberrypi,pico-uart-pio`
+   * - SPI (PIO)
+     - :kconfig:option:`CONFIG_SPI`
+     - :dtcompatible:`raspberrypi,pico-spi-pio`
+   * - WS2812 (PIO)
+     - :kconfig:option:`CONFIG_LED_STRIP`
+     - :dtcompatible:`worldsemi,ws2812-rpi_pico-pio`
+
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
+Applications for the ``rpi_pico`` board configuration can be built and
+flashed in the usual way (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
 System requirements
 ===================
 
@@ -172,14 +156,32 @@ provided by Infineon. Run the command below to retrieve those files:
 
    It is recommended running the command above after :file:`west update`.
 
+Debug Probe and Host Tools
+--------------------------
+
+Several debugging tools support the Raspberry Pi Pico.
+The `Raspberry Pi Debug Probe`_ is an easy-to-obtain CMSIS-DAP adapter
+officially provided by the Raspberry Pi Foundation,
+making it a convenient choice for debugging ``rpi_pico``.
+
+It can be used with
+
+- :ref:`openocd-debug-host-tools`
+- :ref:`pyocd-debug-host-tools`
+
+OpenOCD is the default for ``rpi_pico``.
+
+- `SEGGER J-Link`_
+- `Black Magic Debug Probe <Black Magic Debug>`_
+
+can also be used.
+These are used with dedicated probes.
+
 Flashing
 ========
 
-Using SEGGER JLink
-------------------
-
-You can Flash the rpi_pico with a SEGGER JLink debug probe as described in
-:ref:`Building, Flashing and Debugging <west-flashing>`.
+The ``rpi_pico`` can flash with Zephyr's standard method.
+See also :ref:`Building, Flashing and Debugging<west-flashing>`.
 
 Here is an example of building and flashing the :zephyr:code-sample:`blinky` application.
 
@@ -188,51 +190,42 @@ Here is an example of building and flashing the :zephyr:code-sample:`blinky` app
    :board: rpi_pico
    :goals: build
 
-.. code-block:: bash
+.. code-block:: console
 
   west flash --runner jlink
 
-Using OpenOCD
--------------
-
-To use CMSIS-DAP, You must configure **udev**.
-
-Create a file in /etc/udev.rules.d with any name, and write the line below.
 
-.. code-block:: bash
+.. _rpi_pico_flashing_using_openocd:
 
-   ATTRS{idVendor}=="2e8a", ATTRS{idProduct}=="000c", MODE="660", GROUP="plugdev", TAG+="uaccess"
+Using OpenOCD
+-------------
 
-This example is valid for the case that the user joins to ``plugdev`` groups.
+To use a debugging adapter such as the Raspberry Pi Debug Probe,
+You must configure **udev**. Refer to :ref:`setting-udev-rules` for details.
 
 The Raspberry Pi Pico has an SWD interface that can be used to program
-and debug the on board RP2040. This interface can be utilized by OpenOCD.
-To use it with the RP2040, OpenOCD version 0.12.0 or later is needed.
+and debug the onboard SoC. This interface can be used with OpenOCD.
+To use it, OpenOCD version 0.12.0 or later is needed.
 
-If you are using a Debian based system (including RaspberryPi OS, Ubuntu. and more),
+If you are using a Debian based system (including Raspberry Pi OS, Ubuntu. and more),
 using the `pico_setup.sh`_ script is a convenient way to set up the forked version of OpenOCD.
 
-Depending on the interface used (such as JLink), you might need to
-checkout to a branch that supports this interface, before proceeding.
-Build and install OpenOCD as described in the README.
-
 Here is an example of building and flashing the :zephyr:code-sample:`blinky` application.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/basic/blinky
    :board: rpi_pico
    :goals: build flash
-   :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=cmsis-dap
+   :gen-args: -DOPENOCD=/usr/local/bin/openocd -DRPI_PICO_DEBUG_ADAPTER=cmsis-dap
 
-Set the environment variables **OPENOCD** to :file:`/usr/local/bin/openocd`
-and **OPENOCD_DEFAULT_PATH** to :file:`/usr/local/share/openocd/scripts`. This should work
+Set the CMake option **OPENOCD** to :file:`/usr/local/bin/openocd`. This should work
 with the OpenOCD that was installed with the default configuration.
 This configuration also works with an environment that is set up by the `pico_setup.sh`_ script.
 
 **RPI_PICO_DEBUG_ADAPTER** specifies what debug adapter is used for debugging.
 
-If **RPI_PICO_DEBUG_ADAPTER** was not assigned, ``cmsis-dap`` is used by default.
-The other supported adapters are ``raspberrypi-swd``, ``jlink`` and ``blackmagicprobe``.
+If **RPI_PICO_DEBUG_ADAPTER** was not set, ``cmsis-dap`` is used by default.
+The ``raspberrypi-swd`` and ``jlink`` are verified to work.
 How to connect ``cmsis-dap`` and ``raspberrypi-swd`` is described in `Getting Started with Raspberry Pi Pico`_.
 Any other SWD debug adapter maybe also work with this configuration.
 
@@ -243,12 +236,7 @@ The value of **RPI_PICO_DEBUG_ADAPTER** is cached, so it can be omitted from
 **RPI_PICO_DEBUG_ADAPTER** is used in an argument to OpenOCD as ``"source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]"``.
 Thus, **RPI_PICO_DEBUG_ADAPTER** needs to be assigned the file name of the debug adapter.
 
-You can also flash the board with the following
-command that directly calls OpenOCD (assuming a SEGGER JLink adapter is used):
-
-.. code-block:: console
-
-   $ openocd -f interface/jlink.cfg -c 'transport select swd' -f target/rp2040.cfg -c "adapter speed 2000" -c 'targets rp2040.core0' -c 'program path/to/zephyr.elf verify reset exit'
+.. _rpi_pico_flashing_using_uf2:
 
 Using UF2
 ---------
@@ -262,59 +250,48 @@ UF2 file should be drag-and-dropped to the device, which will flash the Pico.
 Debugging
 =========
 
-The SWD interface can also be used to debug the board. To achieve this, you can
-either use SEGGER JLink or OpenOCD.
-
-Using SEGGER JLink
-------------------
-
-Use a SEGGER JLink debug probe and follow the instruction in
-:ref:`Building, Flashing and Debugging<west-debugging>`.
-
-
-Using OpenOCD
--------------
-
-Install OpenOCD as described for flashing the board.
-
-Here is an example for debugging the :zephyr:code-sample:`blinky` application.
+Like flashing, debugging can also be performed using Zephyr's standard method
+(see :ref:`application_run`).
+The following sample demonstrates how to debug using OpenOCD and
+the `Raspberry Pi Debug Probe`_.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/basic/blinky
    :board: rpi_pico
    :maybe-skip-config:
    :goals: debug
-   :gen-args: -DOPENOCD=/usr/local/bin/openocd -DOPENOCD_DEFAULT_PATH=/usr/local/share/openocd/scripts -DRPI_PICO_DEBUG_ADAPTER=raspberrypi-swd
-
-As with flashing, you can specify the debug adapter by specifying **RPI_PICO_DEBUG_ADAPTER**
-at ``west build`` time. No needs to specify it at ``west debug`` time.
+   :gen-args: -DOPENOCD=/usr/local/bin/openocd -DRPI_PICO_DEBUG_ADAPTER=cmsis-dap
 
-You can also debug with OpenOCD and gdb launching from command-line.
-Run the following command:
+The default debugging tool is ``openocd``.
+If you use a different tool, specify it with the ``--runner``,
+such as ``jlink``.
 
-.. code-block:: console
+If you use OpenOCD, see also the description about flashing :ref:`rpi_pico_flashing_using_uf2`
+for more information.
 
-   $ openocd -f interface/jlink.cfg -c 'transport select swd' -f target/rp2040.cfg -c "adapter speed 2000" -c 'targets rp2040.core0'
 
-On another terminal, run:
-
-.. code-block:: console
-
-   $ gdb-multiarch
+.. target-notes::
 
-Inside gdb, run:
+.. _Raspberry Pi Pico:
+   https://www.raspberrypi.com/products/raspberry-pi-pico/
 
-.. code-block:: console
+.. _RP2040 Datasheet:
+   https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf
 
-   (gdb) tar ext :3333
-   (gdb) file path/to/zephyr.elf
-
-You can then start debugging the board.
-
-.. target-notes::
+.. _Infineon CYW43439:
+   https://www.infineon.com/cms/en/product/wireless-connectivity/airoc-wi-fi-plus-bluetooth-combos/wi-fi-4-802.11n/cyw43439/
 
 .. _pico_setup.sh:
    https://raw.githubusercontent.com/raspberrypi/pico-setup/master/pico_setup.sh
 
 .. _Getting Started with Raspberry Pi Pico:
-  https://datasheets.raspberrypi.com/pico/getting-started-with-pico.pdf
+   https://datasheets.raspberrypi.com/pico/getting-started-with-pico.pdf
+
+.. _Raspberry Pi Debug Probe:
+   https://www.raspberrypi.com/documentation/microcontrollers/debug-probe.html
+
+.. _SEGGER J-Link:
+   https://www.segger.com/products/debug-probes/j-link/
+
+.. _Black Magic Debug:
+   https://black-magic.org/
diff --git a/boards/raspberrypi/rpi_pico/rpi_pico.yaml b/boards/raspberrypi/rpi_pico/rpi_pico.yaml
index 80de519dad5..03e2673ce72 100644
--- a/boards/raspberrypi/rpi_pico/rpi_pico.yaml
+++ b/boards/raspberrypi/rpi_pico/rpi_pico.yaml
@@ -1,5 +1,5 @@
 identifier: rpi_pico
-name: RaspberryPi-Pico
+name: Raspberry Pi Pico
 type: mcu
 arch: arm
 flash: 2048
@@ -7,7 +7,6 @@ ram: 264
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - uart
   - gpio
diff --git a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.yaml b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.yaml
index 581645830a7..f06ac1ce74c 100644
--- a/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.yaml
+++ b/boards/raspberrypi/rpi_pico/rpi_pico_rp2040_w.yaml
@@ -1,5 +1,5 @@
 identifier: rpi_pico/rp2040/w
-name: RaspberryPi-Pico-w
+name: Raspberry Pi Pico W
 type: mcu
 arch: arm
 flash: 2048
@@ -7,7 +7,6 @@ ram: 264
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - uart
   - gpio
diff --git a/boards/raspberrypi/rpi_pico2/doc/index.rst b/boards/raspberrypi/rpi_pico2/doc/index.rst
index 1457a8b849e..a6ed699a820 100644
--- a/boards/raspberrypi/rpi_pico2/doc/index.rst
+++ b/boards/raspberrypi/rpi_pico2/doc/index.rst
@@ -30,51 +30,7 @@ Hardware
 Supported Features
 ==================
 
-The ``rpi_pico2/rp2350a/m33`` board target supports the following
-hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v8m-nvic`
-   * - ADC
-     - :kconfig:option:`CONFIG_ADC`
-     - :dtcompatible:`raspberrypi,pico-adc`
-   * - Clock controller
-     - :kconfig:option:`CONFIG_CLOCK_CONTROL`
-     - :dtcompatible:`raspberrypi,pico-clock-controller`
-   * - Counter
-     - :kconfig:option:`CONFIG_COUNTER`
-     - :dtcompatible:`raspberrypi,pico-timer`
-   * - DMA
-     - :kconfig:option:`CONFIG_DMA`
-     - :dtcompatible:`raspberrypi,pico-dma`
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`raspberrypi,pico-gpio`
-   * - HWINFO
-     - :kconfig:option:`CONFIG_HWINFO`
-     - N/A
-   * - I2C
-     - :kconfig:option:`CONFIG_I2C`
-     - :dtcompatible:`snps,designware-i2c`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM`
-     - :dtcompatible:`raspberrypi,pico-pwm`
-   * - SPI
-     - :kconfig:option:`CONFIG_SPI`
-     - :dtcompatible:`raspberrypi,pico-spi`
-   * - UART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`raspberrypi,pico-uart`
-   * - UART (PIO)
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`raspberrypi,pico-uart-pio`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -84,6 +40,8 @@ The default pin mapping is unchanged from the Pico 1 (see :ref:`rpi_pico_pin_map
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 As with the Pico 1, the SWD interface can be used to program and debug the
 device, e.g. using OpenOCD with the `Raspberry Pi Debug Probe <https://www.raspberrypi.com/documentation/microcontrollers/debug-probe.html>`_ .
 
diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi b/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi
index 85cdb97e845..522413c94f1 100644
--- a/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi
+++ b/boards/raspberrypi/rpi_pico2/rpi_pico2.dtsi
@@ -97,7 +97,7 @@
 	pinctrl-names = "default";
 };
 
-&gpio0 {
+gpio0_lo: &gpio0 {
 	status = "okay";
 };
 
@@ -137,6 +137,10 @@
 	status = "okay";
 };
 
+&wdt0 {
+	status = "okay";
+};
+
 zephyr_udc0: &usbd {
 	status = "okay";
 };
diff --git a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.yaml b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.yaml
index d3c340d88b1..f83082393e0 100644
--- a/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.yaml
+++ b/boards/raspberrypi/rpi_pico2/rpi_pico2_rp2350a_m33.yaml
@@ -7,7 +7,6 @@ ram: 520
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - clock
@@ -19,3 +18,5 @@ supported:
   - pwm
   - spi
   - uart
+  - usbd
+  - watchdog
diff --git a/boards/raytac/mdbt50q_db_33/doc/index.rst b/boards/raytac/mdbt50q_db_33/doc/index.rst
index fe10186965e..eadb5fad4d2 100644
--- a/boards/raytac/mdbt50q_db_33/doc/index.rst
+++ b/boards/raytac/mdbt50q_db_33/doc/index.rst
@@ -30,7 +30,7 @@ Hardware
 ********
 - Module Demo Board build by MDBT50Q-512K
 - Nordic nRF52833 SoC Solution
-- A recommnded 3rd-party module by Nordic Semiconductor.
+- A recommended 3rd-party module by Nordic Semiconductor.
 - BT5.2&BT5.1&BT5 Bluetooth Specification Cerified
 - Supports BT5 Long Range Features
 - Cerifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC
@@ -44,52 +44,15 @@ Hardware
 - 3 User LEDs
 - 4 User buttons
 - 1 Mini USB connector for power supply and USB communication
-- SWD connector for FW programing
-- J-Link interface for FW programing
+- SWD connector for FW programming
+- J-Link interface for FW programming
 - UART interface for UART communication
 
 Supported Features
 ==================
 
-The raytac_mdbt50q_db_33/nrf52833 board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `MDBT50Q-DB-33 website`_ and `MDBT50Q-DB-33 Specification`_
 for a complete list of Raytac MDBT50Q-DB-33 board hardware features.
 
@@ -121,6 +84,8 @@ UART
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``raytac_mdbt50q_db_33/nrf52833`` board configuration can be
 built, flashed, and debugged in the usual way. See :ref:`build_an_application` and
 :ref:`application_run` for more details on building and running.
diff --git a/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.yaml b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.yaml
index e0698628e71..fa8c20d0163 100644
--- a/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.yaml
+++ b/boards/raytac/mdbt50q_db_33/raytac_mdbt50q_db_33_nrf52833.yaml
@@ -10,7 +10,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - ble
diff --git a/boards/raytac/mdbt50q_db_40/doc/index.rst b/boards/raytac/mdbt50q_db_40/doc/index.rst
index 5655d41e229..d656eb6e4c9 100644
--- a/boards/raytac/mdbt50q_db_40/doc/index.rst
+++ b/boards/raytac/mdbt50q_db_40/doc/index.rst
@@ -30,7 +30,7 @@ Hardware
 ********
 - Module Demo Board build by MDBT50Q-1MV2
 - Nordic nRF52840 SoC Solution Version: 2
-- A recommnded 3rd-party module by Nordic Semiconductor.
+- A recommended 3rd-party module by Nordic Semiconductor.
 - BT5.2&BT5.1&BT5 Bluetooth Specification Cerified
 - Supports BT5 Long Range Features
 - Cerifications: FCC, IC, CE, Telec(MIC), KC, SRRC, NCC, RCM, WPC
@@ -44,54 +44,15 @@ Hardware
 - 3 User LEDs
 - 4 User buttons
 - 1 Mini USB connector for power supply and USB communication
-- SWD connector for FW programing
-- J-Link interface for FW programing
+- SWD connector for FW programming
+- J-Link interface for FW programming
 - UART interface for UART communication
 
 Supported Features
 ==================
 
-The raytac_mdbt50q_db_40/nrf52840 board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| QSPI(M)   | on-chip    | qspi                 |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `MDBT50Q-DB-40 website`_ and `MDBT50Q-DB-40 Specification`_
 for a complete list of Raytac MDBT50Q-DB-40 board hardware features.
 
@@ -123,6 +84,8 @@ UART
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``raytac_mdbt50q_db_40/nrf52840`` board configuration can be
 built, flashed, and debugged in the usual way. See :ref:`build_an_application` and
 :ref:`application_run` for more details on building and running.
diff --git a/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.yaml b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.yaml
index cc99eab1a53..4a1e5fd20de 100644
--- a/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.yaml
+++ b/boards/raytac/mdbt50q_db_40/raytac_mdbt50q_db_40_nrf52840.yaml
@@ -12,7 +12,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - ble
diff --git a/boards/raytac/mdbt53_db_40/doc/index.rst b/boards/raytac/mdbt53_db_40/doc/index.rst
index a429f7b1881..3b0e9b221be 100644
--- a/boards/raytac/mdbt53_db_40/doc/index.rst
+++ b/boards/raytac/mdbt53_db_40/doc/index.rst
@@ -48,7 +48,7 @@ Hardware
 ********
 - Module Demo Board build by MDBT53-1M
 - Nordic nRF5340 SoC Solution
-- A recommnded 3rd-party module by Nordic Semiconductor.
+- A recommended 3rd-party module by Nordic Semiconductor.
 - Dual-core Arm® Cortex® M33
 - 1MB/256KB Flash Memory; 512kB/ 64kB RAM
 - Supports BT5 Long Range Features
@@ -64,79 +64,15 @@ Hardware
 - 4 User LEDs
 - 4 User buttons
 - 1 Mini USB connector for power supply
-- SWD connector for FW programing
-- J-Link interface for FW programing
+- SWD connector for FW programming
+- J-Link interface for FW programming
 - UART interface for UART communication
 
 Supported Features
 ==================
 
-The ``raytac_mdbt53_db_40_nrf5340/cpuapp`` board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| QSPI(M)   | on-chip    | nor                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| SPU       | on-chip    | system protection    |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-The ``raytac_mdbt53_db_40_nrf5340/cpunet`` board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `MDBT53-DB-40 website`_ and `MDBT53-DB-40 Specification`_
 for a complete list of Raytac MDBT53-DB-40 board hardware features.
 
@@ -180,6 +116,8 @@ Security components
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 nRF5340 application core supports the Armv8-M Security Extension.
 Applications built for the ``raytac_mdbt53_db_40/nrf5340/cpuapp`` board by
 default boot in the Secure state.
diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml
index 44596dc8a5b..719c66ec644 100644
--- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml
+++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 448
 flash: 1024
diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml
index d77e8d5c8f0..6e0d66b0a41 100644
--- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml
+++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpuapp_ns.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 192
 flash: 192
diff --git a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet.yaml b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet.yaml
index b6badb279f9..6bde25d2003 100644
--- a/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet.yaml
+++ b/boards/raytac/mdbt53_db_40/raytac_mdbt53_db_40_nrf5340_cpunet.yaml
@@ -8,7 +8,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 64
 flash: 256
diff --git a/boards/raytac/mdbt53v_db_40/doc/index.rst b/boards/raytac/mdbt53v_db_40/doc/index.rst
index 834971e7c7d..bd8584b7833 100644
--- a/boards/raytac/mdbt53v_db_40/doc/index.rst
+++ b/boards/raytac/mdbt53v_db_40/doc/index.rst
@@ -47,7 +47,7 @@ Hardware
 ********
 - Module Demo Board build by MDBT53V-1M
 - Nordic nRF5340 SoC Solution
-- A recommnded 3rd-party module by Nordic Semiconductor.
+- A recommended 3rd-party module by Nordic Semiconductor.
 - Dual-core Arm® Cortex® M33
 - 1MB/256KB Flash Memory; 512kB/ 64kB RAM
 - Supports BT5 Long Range Features
@@ -64,74 +64,14 @@ Hardware
 - 1 User LEDs
 - 3 User buttons
 - 1 Mini USB connector for power supply
-- SWD connector for FW programing
-- J-Link interface for FW programing
+- SWD connector for FW programming
+- J-Link interface for FW programming
 
 Supported Features
 ==================
 
-The raytac_mdbt53v_db_40_nrf5340_cpuapp board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-The raytac_mdbt53v_db_40_nrf5340_cpunet board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UARTE     | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
+
 See `MDBT53V-DB-40 website`_ and `MDBT53V-DB-40 Specification`_
 for a complete list of Raytac MDBT53V-DB-40 board hardware features.
 
@@ -180,6 +120,8 @@ Security components
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 nRF5340 application core supports the Armv8-M Security Extension.
 Applications built for the raytac_mdbt53v_db_40_nrf5340_cpuapp board by
 default boot in the Secure state.
diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml
index bd576367268..3151f265685 100644
--- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml
+++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 448
 flash: 1024
diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml
index e5340237e6a..87aafde68e7 100644
--- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml
+++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpuapp_ns.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 192
 flash: 192
diff --git a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet.yaml b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet.yaml
index eb5cac4d609..c6684dff068 100644
--- a/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet.yaml
+++ b/boards/raytac/mdbt53v_db_40/raytac_mdbt53v_db_40_nrf5340_cpunet.yaml
@@ -8,7 +8,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 64
 flash: 256
diff --git a/boards/realtek/rts5912_evb/board.yml b/boards/realtek/rts5912_evb/board.yml
index 2be9b8d1746..8e0e6eb7ebd 100644
--- a/boards/realtek/rts5912_evb/board.yml
+++ b/boards/realtek/rts5912_evb/board.yml
@@ -1,5 +1,6 @@
 board:
   name: rts5912_evb
+  full_name: RTS5912 Evaluation Board
   vendor: realtek
   socs:
   - name: rts5912
diff --git a/boards/realtek/rts5912_evb/doc/rts5912evb.webp b/boards/realtek/rts5912_evb/doc/img/rts5912evb.webp
similarity index 100%
rename from boards/realtek/rts5912_evb/doc/rts5912evb.webp
rename to boards/realtek/rts5912_evb/doc/img/rts5912evb.webp
diff --git a/boards/realtek/rts5912_evb/doc/index.rst b/boards/realtek/rts5912_evb/doc/index.rst
new file mode 100644
index 00000000000..a8bbc18b11b
--- /dev/null
+++ b/boards/realtek/rts5912_evb/doc/index.rst
@@ -0,0 +1,69 @@
+.. zephyr:board:: rts5912_evb
+
+Overview
+********
+
+The RTS5912 EVB is a development platform to evaluate the Realtek RTS5912 embedded controller.
+
+Hardware
+********
+
+- Realtek-M300 Processor (compatible to Cortex-M33)
+- Memory:
+
+   - 384 KB SRAM
+   - 64 KB ROM
+   - 512 KB Flash(MCM)
+   - 256 B Battery SRAM
+- PECI interface 3.1
+- FAN, PWM and TACHO pins
+- 6x I2C instances
+- eSPI header
+- 1x PS/2 ports
+- Keyboard interface headers
+
+For more information about the evb board please see `RTS5912_EVB_Schematics`_ and `RTS5912_DATASHEET`_
+
+The board is powered through the +5V USB Type-C connector or adaptor.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Building
+========
+
+#. Build :zephyr:code-sample:`hello_world` application as you would normally do.
+
+#. The file ``zephyr.rts5912.bin`` will be created if the build system can build successfully.
+   This binary image can be found under file "build/zephyr/".
+
+Flashing
+========
+
+#. Connect Dediprog into header ``J81`` and ``J82``.
+#. Use Dediprog SF600 programmer to write the binary into the external flash ``U10`` at the address 0x0.
+#. Power off the board.
+#. Set the strap pin ``GPIO108`` to high and power on the board.
+
+Debugging
+=========
+
+Using SWD or JTAG with ULINPRO.
+
+References
+**********
+
+.. target-notes::
+
+.. _RTS5912_EVB_Schematics:
+    https://github.com/JasonLin-RealTek/Realtek_EC/blob/main/RTS5912_EVB_Schematic_Ver%201.1_20240701_1407.pdf
+
+.. _RTS5912_DATASHEET:
+   https://github.com/JasonLin-RealTek/Realtek_EC/blob/main/RTS5912_datasheet_brief.pdf
diff --git a/boards/realtek/rts5912_evb/doc/rts5912_evb.rst b/boards/realtek/rts5912_evb/doc/rts5912_evb.rst
deleted file mode 100644
index cb77ad613cc..00000000000
--- a/boards/realtek/rts5912_evb/doc/rts5912_evb.rst
+++ /dev/null
@@ -1,93 +0,0 @@
-.. _rts5912_evb:
-
-Realtek RTS5912 Evaluation Board
-################################
-
-Overview
-********
-
-The RTS5912 EVB is a development platform to evaluate the Realtek RTS5912 embedded controller.
-
-.. figure:: rts5912evb.webp
-   :width: 800px
-   :align: center
-   :alt: RTS5912-GR EVB
-
-Hardware
-********
-
-- Realtek-M300 Processor (compatible to Cortex-M33)
-- Memory:
-
-   - 384 KB SRAM
-   - 64 KB ROM
-   - 512 KB Flash(MCM)
-   - 256 B Battery SRAM
-- PECI interface 3.1
-- FAN, PWM and TACHO pins
-- 6x I2C instances
-- eSPI header
-- 1x PS/2 ports
-- Keyboard interface headers
-
-For more information about the evb board please see `RTS5912_EVB_Schematics`_ and `RTS5912_DATASHEET`_
-
-The board is powered through the +5V USB Type-C connector or adaptor.
-
-Supported Features
-==================
-
-The ``rts5912_evb`` supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| PINCTRL   | on-chip    | pinctrl                             |
-+-----------+------------+-------------------------------------+
-| SCCON     | on-chip    | clock_control                       |
-+-----------+------------+-------------------------------------+
-| RTMR      | on-chip    | timer                               |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-Programming and Debugging
-*************************
-
-Building
-========
-
-#. Build :zephyr:code-sample:`hello_world` application as you would normally do.
-
-#. The file ``zephyr.rts5912.bin`` will be created if the build system can build successfully.
-   This binary image can be found under file "build/zephyr/".
-
-Flashing
-========
-
-#. Connect Dediprog into header ``J81`` and ``J82``.
-#. Use Dediprog SF600 programmer to write the binary into the external flash ``U10`` at the address 0x0.
-#. Power off the board.
-#. Set the strap pin ``GPIO108`` to high and power on the board.
-
-Debugging
-=========
-
-Using SWD or JTAG with ULINPRO.
-
-References
-**********
-
-.. target-notes::
-
-.. _RTS5912_EVB_Schematics:
-    https://github.com/JasonLin-RealTek/Realtek_EC/blob/main/RTS5912_EVB_Schematic_Ver%201.1_20240701_1407.pdf
-
-.. _RTS5912_DATASHEET:
-   https://github.com/JasonLin-RealTek/Realtek_EC/blob/main/RTS5912_datasheet_brief.pdf
diff --git a/boards/realtek/rts5912_evb/rts5912_evb.dts b/boards/realtek/rts5912_evb/rts5912_evb.dts
index 1e22d6c4ace..f58d75e36da 100644
--- a/boards/realtek/rts5912_evb/rts5912_evb.dts
+++ b/boards/realtek/rts5912_evb/rts5912_evb.dts
@@ -20,6 +20,17 @@
 	};
 };
 
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_gpio074 &adc1_gpio075
+		&adc2_gpio076 &adc3_gpio077
+		&adc4_gpio078 &adc5_gpio079
+		&adc6_gpio080 &adc7_gpio081
+		&adc8_gpio082 &adc9_gpio054
+		&adc10_gpio098 &adc11_gpio024>;
+	pinctrl-names = "default";
+};
+
 &uart0 {
 	status = "okay";
 	current-speed = <115200>;
@@ -31,6 +42,32 @@
 	pinctrl-names = "default";
 };
 
+&kbd {
+	status = "okay";
+	pinctrl-0 = <&kso0_gpio041 &kso1_gpio042
+		     &kso2_gpio043 &kso3_gpio044
+		     &kso4_gpio045 &kso5_gpio046
+		     &kso6_gpio047 &kso7_gpio048
+		     &kso8_gpio049 &kso9_gpio050
+		     &kso10_gpio051 &kso11_gpio055
+		     &kso12_gpio056 &kso13_gpio057
+		     &kso14_gpio058 &kso15_gpio059
+		     &ksi0_gpio064 &ksi1_gpio065
+		     &ksi2_gpio066 &ksi3_gpio067
+		     &ksi4_gpio068 &ksi5_gpio069
+		     &ksi6_gpio070 &ksi7_gpio071>;
+	pinctrl-names = "default";
+	row-size = <8>;
+	col-size = <16>;
+};
+
 &swj_port {
 	status = "okay";
 };
+
+&tach0 {
+	status = "okay";
+	pinctrl-0 = <&tacho0_gpio052>;
+	pinctrl-names = "default";
+	pulses-per-round = <2>;
+};
diff --git a/boards/realtek/rts5912_evb/rts5912_evb.yaml b/boards/realtek/rts5912_evb/rts5912_evb.yaml
index 199a6e1027a..e781df48992 100644
--- a/boards/realtek/rts5912_evb/rts5912_evb.yaml
+++ b/boards/realtek/rts5912_evb/rts5912_evb.yaml
@@ -10,10 +10,10 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 320
 supported:
   - gpio
   - pinmux
+  - adc
 vendor: realtek
diff --git a/boards/realtek/rts5912_evb/rts5912_evb_defconfig b/boards/realtek/rts5912_evb/rts5912_evb_defconfig
index 64454c374d5..a454f6a87a0 100644
--- a/boards/realtek/rts5912_evb/rts5912_evb_defconfig
+++ b/boards/realtek/rts5912_evb/rts5912_evb_defconfig
@@ -17,3 +17,9 @@ CONFIG_UART_CONSOLE=y
 
 # Enable GPIO
 CONFIG_GPIO=y
+
+# Input Driver
+CONFIG_INPUT=y
+
+# Enable ADC
+CONFIG_ADC=y
diff --git a/boards/renesas/da14695_dk_usb/da14695_dk_usb.yaml b/boards/renesas/da14695_dk_usb/da14695_dk_usb.yaml
index b85aee119b6..d6c2d7efa23 100644
--- a/boards/renesas/da14695_dk_usb/da14695_dk_usb.yaml
+++ b/boards/renesas/da14695_dk_usb/da14695_dk_usb.yaml
@@ -6,7 +6,6 @@ ram: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - hwinfo
diff --git a/boards/renesas/da14695_dk_usb/doc/index.rst b/boards/renesas/da14695_dk_usb/doc/index.rst
index 84f5c772d8a..bb530186668 100644
--- a/boards/renesas/da14695_dk_usb/doc/index.rst
+++ b/boards/renesas/da14695_dk_usb/doc/index.rst
@@ -1,4 +1,4 @@
-.. _da14695_dk_usb:
+.. zephyr:board:: da14695_dk_usb
 
 DA14695 Development Kit USB
 ###########################
@@ -10,13 +10,6 @@ The DA14695 Development Kit USB is a low cost development board for DA14695.
 The development kit comes with an integrated debugger and an USB hub
 to have both the on-chip USB and the J-Link connected via a single port.
 
-.. figure:: da14695-00hqdevkt-u-usb-board.jpg
-     :width: 442px
-     :align: center
-     :alt: DA14695 Development Kit USB
-
-     DA14695 Development Kit USB (Credit: Renesas Electronics Corporation)
-
 Hardware
 ********
 
@@ -26,29 +19,7 @@ the sleep clock is 32768 Hz. The frequency of the system clock is 32 MHz.
 Supported Features
 ==================
 
-The _da14695_dk_usb board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-
-Other hardware features, including the Configurable MAC (CMAC) controller,
-are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 For more information about the DA14695 Development Kit see:
 
@@ -77,6 +48,8 @@ The pin connections are as follows:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``da14695_dk_usb`` board configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
diff --git a/boards/renesas/da1469x_dk_pro/Kconfig.defconfig b/boards/renesas/da1469x_dk_pro/Kconfig.defconfig
index 496044aa9b6..3ca13893da1 100644
--- a/boards/renesas/da1469x_dk_pro/Kconfig.defconfig
+++ b/boards/renesas/da1469x_dk_pro/Kconfig.defconfig
@@ -29,9 +29,6 @@ endif # LVGL
 
 if INPUT
 
-config INPUT_FT5336_INTERRUPT
-	default y
-
 config LV_Z_POINTER_INPUT_MSGQ_COUNT
 	default 70
 
diff --git a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml
index 1d988ecbf57..1c9a7e2885a 100644
--- a/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml
+++ b/boards/renesas/da1469x_dk_pro/da1469x_dk_pro.yaml
@@ -6,7 +6,6 @@ ram: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_gpio
   - counter
diff --git a/boards/renesas/da1469x_dk_pro/doc/index.rst b/boards/renesas/da1469x_dk_pro/doc/index.rst
index f45c1f333fe..3c8b643b5b8 100644
--- a/boards/renesas/da1469x_dk_pro/doc/index.rst
+++ b/boards/renesas/da1469x_dk_pro/doc/index.rst
@@ -1,4 +1,4 @@
-.. _da1469x_dk_pro:
+.. zephyr:board:: da1469x_dk_pro
 
 DA1469x Development Kit Pro
 ###########################
@@ -11,13 +11,6 @@ DA1469x ARM Cortex-M33 MCU family. The development kit consist of a motherboard
 with connectors and integrated debugger and an interchangeable daughterboard
 with an actual MCU (e.g. DA14695 or DA14699).
 
-.. figure:: da14695-00hqdevkt-board.jpg
-     :width: 442px
-     :align: center
-     :alt: DA14695 Development Kit Pro
-
-     DA14695 Development Kit Pro (Credit: Renesas Electronics Corporation)
-
 Hardware
 ********
 
@@ -27,29 +20,7 @@ the sleep clock is 32768 Hz. The frequency of the system clock is 32 MHz.
 Supported Features
 ==================
 
-The _da1469x_dk_pro board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-
-Other hardware features, including the Configurable MAC (CMAC) controller,
-are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 For more information about the DA14695 Development Kit see:
 
@@ -79,6 +50,8 @@ The pin connections are as follows:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``da1469x_dk_pro`` board configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
diff --git a/boards/renesas/ek_ra2a1/doc/index.rst b/boards/renesas/ek_ra2a1/doc/index.rst
index fd8ebc5e26d..25f8d131212 100644
--- a/boards/renesas/ek_ra2a1/doc/index.rst
+++ b/boards/renesas/ek_ra2a1/doc/index.rst
@@ -1,7 +1,4 @@
-.. _ek_ra2a1:
-
-RA2A1 Evaluation Kit
-####################
+.. zephyr:board:: ek_ra2a1
 
 Overview
 ********
@@ -31,12 +28,6 @@ Renesas RA2A1 Microcontroller Group has following features
 - Watchdog Timer
 - 49 Input/Output pins
 
-.. figure:: ek_ra2a1.webp
-	:align: center
-	:alt: RA2A1 Evaluation Kit
-
-	EK-RA2A1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
-
 Hardware
 ********
 
@@ -64,38 +55,13 @@ EK-RA2A1 has following features.
 Supported Features
 ==================
 
-The Renesas EK-RA2A1 board configuration supports the following
-hardware features:
-
-+-----------+------------+-------------------------------+
-| Interface | Controller | Driver/components             |
-+===========+============+===============================+
-| PINCTRL   | on-chip    | pinctrl                       |
-+-----------+------------+-------------------------------+
-| CLOCK     | on-chip    | clock_control                 |
-+-----------+------------+-------------------------------+
-| GPIO      | on-chip    | gpio                          |
-+-----------+------------+-------------------------------+
-| UART      | on-chip    | uart                          |
-+-----------+------------+-------------------------------+
-| SPI       | on-chip    | spi                           |
-+-----------+------------+-------------------------------+
-| COUNTER   | on-chip    | counter                       |
-+-----------+------------+-------------------------------+
-| PWM       | on-chip    | pwm                           |
-+-----------+------------+-------------------------------+
-| ENTROPY   | on-chip    | entropy                       |
-+-----------+------------+-------------------------------+
-| I2C       | on-chip    | i2c                           |
-+-----------+------------+-------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/renesas/ek_ra2a1/ek_ra2a1_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Programming and debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Building & Flashing
 ===================
 
diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi b/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi
index 26835a70ea5..690f5736c75 100644
--- a/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi
+++ b/boards/renesas/ek_ra2a1/ek_ra2a1-pinctrl.dtsi
@@ -43,4 +43,12 @@
 			drive-strength = "medium";
 		};
 	};
+
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_CAC_DAC, 5, 0)>;
+			renesas,analog-enable;
+		};
+	};
 };
diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1.dts b/boards/renesas/ek_ra2a1/ek_ra2a1.dts
index f0040a3fd6d..39d5d372cd9 100644
--- a/boards/renesas/ek_ra2a1/ek_ra2a1.dts
+++ b/boards/renesas/ek_ra2a1/ek_ra2a1.dts
@@ -43,6 +43,7 @@
 	aliases {
 		led0 = &led1;
 		sw0 = &button0;
+		watchdog0 = &wdt;
 	};
 };
 
@@ -109,3 +110,13 @@
 	interrupt-names = "rxi", "txi", "tei", "eri";
 	status = "okay";
 };
+
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1.yaml b/boards/renesas/ek_ra2a1/ek_ra2a1.yaml
index 78000823a98..9a6fd6f7748 100644
--- a/boards/renesas/ek_ra2a1/ek_ra2a1.yaml
+++ b/boards/renesas/ek_ra2a1/ek_ra2a1.yaml
@@ -10,3 +10,5 @@ toolchain:
 supported:
   - gpio
   - uart
+  - watchdog
+vendor: renesas
diff --git a/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig b/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig
index 85bd6dcd455..15e3f1e271c 100644
--- a/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig
+++ b/boards/renesas/ek_ra2a1/ek_ra2a1_defconfig
@@ -1,8 +1,6 @@
 # Copyright (c) 2024 TOKITA Hiroshi
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=48000000
-
 # Enable GPIO
 CONFIG_GPIO=y
 
@@ -11,6 +9,3 @@ CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
 CONFIG_CONSOLE=y
-
-CONFIG_BUILD_OUTPUT_HEX=y
-CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/ek_ra2l1/Kconfig.ek_ra2l1 b/boards/renesas/ek_ra2l1/Kconfig.ek_ra2l1
new file mode 100644
index 00000000000..53479a895c8
--- /dev/null
+++ b/boards/renesas/ek_ra2l1/Kconfig.ek_ra2l1
@@ -0,0 +1,5 @@
+# Copyright (c) 2021-2024 MUNIC SA
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_EK_RA2L1
+	select SOC_R7FA2L1ABXXFP
diff --git a/boards/renesas/ek_ra2l1/board.cmake b/boards/renesas/ek_ra2l1/board.cmake
new file mode 100644
index 00000000000..e39493b726b
--- /dev/null
+++ b/boards/renesas/ek_ra2l1/board.cmake
@@ -0,0 +1,12 @@
+# Copyright (c) 2021-2024 MUNIC SA
+# SPDX-License-Identifier: Apache-2.0
+
+board_set_debugger_ifnset(jlink)
+board_set_flasher_ifnset(jlink)
+
+board_runner_args(jlink "--device=r7fa2l1ab")
+board_runner_args(pyocd "--target=r7fa2l1ab")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/renesas/ek_ra2l1/board.yml b/boards/renesas/ek_ra2l1/board.yml
new file mode 100644
index 00000000000..181a338410b
--- /dev/null
+++ b/boards/renesas/ek_ra2l1/board.yml
@@ -0,0 +1,5 @@
+board:
+  name: ek_ra2l1
+  vendor: renesas
+  socs:
+  - name: r7fa2l1abxxfp
diff --git a/boards/renesas/ek_ra2l1/doc/ek_ra2l1.webp b/boards/renesas/ek_ra2l1/doc/ek_ra2l1.webp
new file mode 100644
index 00000000000..54da2916330
Binary files /dev/null and b/boards/renesas/ek_ra2l1/doc/ek_ra2l1.webp differ
diff --git a/boards/renesas/ek_ra2l1/doc/index.rst b/boards/renesas/ek_ra2l1/doc/index.rst
new file mode 100644
index 00000000000..15e08fd215e
--- /dev/null
+++ b/boards/renesas/ek_ra2l1/doc/index.rst
@@ -0,0 +1,103 @@
+.. zephyr:board:: ek_ra2l1
+
+Overview
+********
+
+The EK-RA2L1 is an evaluation kit for Renesas RA2L1 Microcontroller Group.
+
+Renesas RA2L1 Microcontroller Group has following features
+
+- 48MHz, Arm Cortex-M23 core
+- 256kB or 128kB Code Flash, 8kB Data Flash, 32kB SRAM (divided on 2 equal areas
+  with- and without- ECC support)
+- SCI x 5
+- SPI x 2
+- I2C x 2
+- CAN x 1
+- 12-bit A/D Converter
+- 12-bit D/A Converter
+- Low-Power Analog Comparator x 2
+- Temperature Sensor
+- General PWM Timer 32-bit x 4
+- General PWM Timer 16-bit x 6
+- Low Power Asynchronous General-Purpose Timer x 2
+- Watchdog Timer (WDT)
+- Independent Watchdog Timer (IWDT)
+- up to 85 Input/Output pins (depends on the package type)
+
+Hardware
+********
+
+EK-RA2L1 has following features.
+
+- Native pin access through 1 x 40-pin and 3 x 20-pin male headers
+- MCU current measurement points for precision current consumption measurement
+- Multiple clock sources – Low-precision clocks are available internal to the MCU.
+  Additionally, MCU oscillator and sub-clock oscillator crystals,
+  20.000 MHz and 32,768 Hz, are provided for precision
+- SEGGER J-Link on-board programmer and debugger
+- Two Digilent Pmod (SPI and UART)
+- Three user LEDs (red, blue, green)
+- Power LED (white) indicating availability of regulated power
+- Debug LED (yellow) indicating the debug connection
+- Two user buttons
+- One reset button
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Building & Flashing
+===================
+
+You can build and flash an application with onboard J-Link debug adapter.
+:ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Here is an example for building and flashing the :zephyr:code-sample:`blinky` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: ek_ra2l1
+   :goals: build flash
+
+
+Debugging
+=========
+
+Debugging also can be done with onboard J-Link debug adapter.
+The following command is debugging the :zephyr:code-sample:`blinky` application.
+Also, see the instructions specific to the debug server that you use.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: ek_ra2l1
+   :maybe-skip-config:
+   :goals: debug
+
+Or you can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface
+
+Once downloaded and installed, open Segger Ozone and configure the debug project
+like so:
+
+* Target Device: R7FA2L1AB
+* Target Interface: SWD
+* Target Interface Speed: 4 MHz
+* Host Interface: USB
+* Program File: <path/to/your/build/zephyr.elf>
+
+
+References
+**********
+
+.. EK-RA2L1 Web site:
+   https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra2l1-evaluation-kit-ra2l1-mcu-group
+
+.. _Segger Ozone Download:
+   https://www.segger.com/downloads/jlink#Ozone
diff --git a/boards/renesas/ek_ra2l1/ek_ra2l1-pinctrl.dtsi b/boards/renesas/ek_ra2l1/ek_ra2l1-pinctrl.dtsi
new file mode 100644
index 00000000000..851d8543bee
--- /dev/null
+++ b/boards/renesas/ek_ra2l1/ek_ra2l1-pinctrl.dtsi
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci0_default: sci0_default {
+		group1 {
+			/* tx rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_0, 4, 11)>,
+			<RA_PSEL(RA_PSEL_SCI_0, 4, 10)>;
+		};
+	};
+};
diff --git a/boards/renesas/ek_ra2l1/ek_ra2l1.dts b/boards/renesas/ek_ra2l1/ek_ra2l1.dts
new file mode 100644
index 00000000000..546451d10ac
--- /dev/null
+++ b/boards/renesas/ek_ra2l1/ek_ra2l1.dts
@@ -0,0 +1,62 @@
+/**
+ * Copyright (c) 2021-2024 MUNIC SA
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * DTS for Renesas EK-RA2L1 eval. board
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra2/ra2l1.dtsi>
+#include <renesas/ra/ra2/r7fa2l1xb.dtsi>
+#include <renesas/ra/ra2/r7fa2l1xxxxfp.dtsi>
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include "ek_ra2l1-pinctrl.dtsi"
+
+/ {
+	model = "Renesas EK-RA2L1";
+	compatible = "renesas,r7fa2l1abxxfp", "renesas,ra2l1";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1: led1 {
+			gpios = <&ioport5 3 GPIO_ACTIVE_HIGH>;
+			label = "LED1";
+		};
+	};
+
+	aliases {
+		led0 = &led1;
+		watchdog0 = &wdt;
+	};
+};
+
+&ioport5 {
+	status = "okay";
+};
+
+&sci0 {
+	pinctrl-0 = <&sci0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	uart0: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/boards/renesas/ek_ra2l1/ek_ra2l1.yaml b/boards/renesas/ek_ra2l1/ek_ra2l1.yaml
new file mode 100644
index 00000000000..2ab8e436db3
--- /dev/null
+++ b/boards/renesas/ek_ra2l1/ek_ra2l1.yaml
@@ -0,0 +1,17 @@
+identifier: ek_ra2l1
+name: Renesas EK-RA2L1
+type: mcu
+arch: arm
+ram: 32
+flash: 256
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - flash
+  - watchdog
+vendor: renesas
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
diff --git a/boards/renesas/ek_ra2l1/ek_ra2l1_defconfig b/boards/renesas/ek_ra2l1/ek_ra2l1_defconfig
new file mode 100644
index 00000000000..9c7ccf6a625
--- /dev/null
+++ b/boards/renesas/ek_ra2l1/ek_ra2l1_defconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2021-2024 MUNIC SA
+# Copyright (c) 2024-2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_UART_CONSOLE=y
+CONFIG_CONSOLE=y
diff --git a/boards/renesas/ek_ra4e2/doc/index.rst b/boards/renesas/ek_ra4e2/doc/index.rst
index 8b2c7312140..06983955d95 100644
--- a/boards/renesas/ek_ra4e2/doc/index.rst
+++ b/boards/renesas/ek_ra4e2/doc/index.rst
@@ -1,7 +1,4 @@
-.. _ek_ra4e2:
-
-RA4E2 Evaluation Kit
-####################
+.. zephyr:board:: ek_ra4e2
 
 Overview
 ********
@@ -16,6 +13,7 @@ The MCU in this series incorporates a high-performance Arm Cortex®-M33 core run
 100 MHz with the following features:
 
 **MCU Native Pin Access**
+
 - R7FA4E2B93CFM MCU (referred to as RA MCU)
 - 100 MHz, Arm® Cortex®-M33 core
 - 128 kB Code Flash, 40 kB SRAM
@@ -23,10 +21,11 @@ The MCU in this series incorporates a high-performance Arm Cortex®-M33 core run
 - Native pin access through 2 x 14-pin and 1 x 40-pin male headers
 - MCU current measurement points for precision current consumption measurement
 - Multiple clock sources - RA MCU oscillator and sub-clock oscillator crystals, providing precision
-20.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are available internal to the
-RA MCU
+  20.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are available internal to the
+  RA MCU
 
 **System Control and Ecosystem Access**
+
 - USB Full Speed Device (micro-AB connector)
 - Three 5 V input sources
 
@@ -61,15 +60,9 @@ RA MCU
 
 - CAN FD (3-pin header)
 
-.. figure:: ek_ra4e2.webp
-	:align: center
-	:alt: RA4E2 Evaluation Kit
-
-	EK-RA4E2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
-
 Hardware
 ********
-Detail Hardware feature for the RA4E2 MCU group can be found at `RA4E2 Group User's Manual Hardware`_
+Detailed hardware features for the RA4E2 MCU group can be found at `RA4E2 Group User's Manual Hardware`_
 
 .. figure:: ra4e2_block_diagram.webp
 	:width: 442px
@@ -78,42 +71,18 @@ Detail Hardware feature for the RA4E2 MCU group can be found at `RA4E2 Group Use
 
 	RA4E2 Block diagram (Credit: Renesas Electronics Corporation)
 
-Detail Hardware feature for the EK-RA4E2 MCU can be found at `EK-RA4E2 - User's Manual`_
+Detailed hardware features for the EK-RA4E2 MCU can be found at `EK-RA4E2 - User's Manual`_
 
 Supported Features
 ==================
 
-The below features are currently supported on Zephyr OS for EK-RA4E2 board:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock control        |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| ENTROPY   | on-chip    | entropy              |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``ek_ra4e2`` board target configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
@@ -123,15 +92,15 @@ Flashing
 ========
 
 Program can be flashed to EK-RA4E2 via the on-board SEGGER J-Link debugger.
-SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
 
 To flash the program to board
 
-  1. Connect to J-Link OB via USB port to host PC
+1. Connect to J-Link OB via USB port to host PC
 
-  2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4E2 - User's Manual`_
+2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4E2 - User's Manual`_
 
-  3. Execute west command
+3. Execute west command
 
 	.. code-block:: console
 
diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi b/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi
index 4fa94b5c08d..29ce6c5c302 100644
--- a/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi
+++ b/boards/renesas/ek_ra4e2/ek_ra4e2-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -39,6 +39,14 @@
 		};
 	};
 
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
+			renesas,analog-enable;
+		};
+	};
+
 	pwm1_default: pwm1_default {
 		group1 {
 			/* GTIOC1A GTIOC1B */
diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.dts b/boards/renesas/ek_ra4e2/ek_ra4e2.dts
index c5065f16f76..923c73fabed 100644
--- a/boards/renesas/ek_ra4e2/ek_ra4e2.dts
+++ b/boards/renesas/ek_ra4e2/ek_ra4e2.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -59,6 +59,7 @@
 		led0 = &led1;
 		sw0 = &button0;
 		sw1 = &button1;
+		watchdog0 = &wdt;
 	};
 
 	transceiver0: can-phy0 {
@@ -142,6 +143,12 @@
 	pinctrl-names = "default";
 };
 
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &ioport3 {
 	status = "okay";
 };
@@ -181,3 +188,7 @@
 		};
 	};
 };
+
+&wdt {
+	status = "okay";
+};
diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2.yaml b/boards/renesas/ek_ra4e2/ek_ra4e2.yaml
index bceab6ca960..661dcd6c89d 100644
--- a/boards/renesas/ek_ra4e2/ek_ra4e2.yaml
+++ b/boards/renesas/ek_ra4e2/ek_ra4e2.yaml
@@ -10,3 +10,5 @@ toolchain:
 supported:
   - gpio
   - uart
+  - watchdog
+vendor: renesas
diff --git a/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig b/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig
index 93569c968fc..770a30fc47d 100644
--- a/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig
+++ b/boards/renesas/ek_ra4e2/ek_ra4e2_defconfig
@@ -1,8 +1,6 @@
 # Copyright (c) 2024 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000
-
 # Enable GPIO
 CONFIG_GPIO=y
 
@@ -11,6 +9,3 @@ CONFIG_SERIAL=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
 CONFIG_UART_CONSOLE=y
 CONFIG_CONSOLE=y
-
-CONFIG_BUILD_OUTPUT_HEX=y
-CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/ek_ra4l1/Kconfig.ek_ra4l1 b/boards/renesas/ek_ra4l1/Kconfig.ek_ra4l1
new file mode 100644
index 00000000000..136246af8c7
--- /dev/null
+++ b/boards/renesas/ek_ra4l1/Kconfig.ek_ra4l1
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_EK_RA4L1
+	select SOC_R7FA4L1BD4CFP
diff --git a/boards/renesas/ek_ra4l1/board.cmake b/boards/renesas/ek_ra4l1/board.cmake
new file mode 100644
index 00000000000..ede2ff300bb
--- /dev/null
+++ b/boards/renesas/ek_ra4l1/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7FA4L1BD")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/ek_ra4l1/board.yml b/boards/renesas/ek_ra4l1/board.yml
new file mode 100644
index 00000000000..d2e6b1bf6cb
--- /dev/null
+++ b/boards/renesas/ek_ra4l1/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: ek_ra4l1
+  full_name: RA4L1 Evaluation Kit
+  vendor: renesas
+  socs:
+  - name: r7fa4l1bd4cfp
diff --git a/boards/renesas/ek_ra4l1/doc/ek_ra4l1.webp b/boards/renesas/ek_ra4l1/doc/ek_ra4l1.webp
new file mode 100644
index 00000000000..219105795b0
Binary files /dev/null and b/boards/renesas/ek_ra4l1/doc/ek_ra4l1.webp differ
diff --git a/boards/renesas/ek_ra4l1/doc/index.rst b/boards/renesas/ek_ra4l1/doc/index.rst
new file mode 100644
index 00000000000..d9d1a6ded01
--- /dev/null
+++ b/boards/renesas/ek_ra4l1/doc/index.rst
@@ -0,0 +1,124 @@
+.. zephyr:board:: ek_ra4l1
+
+Overview
+********
+
+The Renesas RA4L1 group of 32-bit microcontrollers (MCUs) uses the high-performance Arm
+Cortex®-M33 core. Share a common set of Renesas peripherals to facilitate design scalability
+and efficient platform-based product development.
+
+The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to
+80 MHz with the following features:
+
+**MCU Native Pin Access**
+
+- R7FA4L1BD4CFP MCU (referred to as RA MCU)
+- 80 MHz, Arm® Cortex®-M33 core
+- 512 KB Code Flash, 64 KB SRAM
+- 100-pin LQFP package
+
+**System Control and Ecosystem Access**
+
+- USB Full Speed Host and Device (USB-C connector)
+- Three 5 V input sources
+
+  - USB (Debug, Full Speed)
+  - External power supply (using surface mount clamp test points and power input vias)
+
+- Three Debug modes
+
+  - Debug on-board (SWD)
+  - Debug in (SWD)
+  - Debug out (SWD, SW0 and JTAG)
+
+- User LEDs and buttons
+
+  - Three User LEDs (red, blue, green)
+  - Power LED (white) indicating availability of regulated power
+  - Debug LED (yellow) indicating the debug connection
+  - Two User buttons
+  - One Reset button
+
+- Five most popular ecosystems expansions
+
+	- 1 Seeed Grove® system (I3C) connector
+	- 1 Seeed Grove® system (I2C/Analog) connector
+	- 2 Digilent PmodTM (SPI, UART and I2C) connectors
+	- ArduinoTM (Uno R3) connector
+	- MikroElektronikaTM mikroBUS connector
+
+- MCU boot configuration jumper
+
+**Special Feature Access**
+
+- 256 Mb (32 MB) External QUAD-SPI Flash
+- CAN FD (3-pin header)
+- Segment LCD Board Interface (50-pin header)
+
+Hardware
+********
+
+Detailed hardware features can be found at:
+
+- RA4L1 MCU: `RA4L1 Group User's Manual Hardware`_
+- EK-RA4L1 board: `EK-RA4L1 - User's Manual`_
+
+Debug on-board:
+
+  - Connector Used: USB-C (J10)
+
++----------------+------+------+--------------------+------+--------------------------------------+
+| Debug Modes    | J6   | J6-A | J8                 | J9   | J29                                  |
++================+======+======+====================+======+======================================+
+| Debug on-board | Open | Open | Jumper on pins 1-2 | Open | Jumpers on pins 1-2, 3-4, 5-6, 7-8   |
++----------------+------+------+--------------------+------+--------------------------------------+
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``ek_ra4l1`` board configuration can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Flashing
+========
+
+Program can be flashed to EK-RA4L1 via the on-board SEGGER J-Link debugger.
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
+
+To flash the program to board
+
+1. Connect to J-Link OB via USB port to host PC
+
+2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4L1 - User's Manual`_
+
+3. Execute west command
+
+  .. code-block:: console
+
+    west flash -r jlink
+
+References
+**********
+- `EK-RA4L1 Website`_
+- `RA4L1 MCU group Website`_
+
+.. _EK-RA4L1 Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4l1-evaluation-kit-ra4l1-mcu-group
+
+.. _RA4L1 MCU group Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra4l1-80mhz-arm-cortex-m33-based-low-power-mcu-trustzone-segment-lcd-controller-and-advanced-security
+
+.. _EK-RA4L1 - User's Manual:
+   https://www.renesas.com/en/document/mat/ek-ra4l1-v1-users-manual?r=25570359
+
+.. _RA4L1 Group User's Manual Hardware:
+   https://www.renesas.com/en/document/mah/ra4l1-group-users-manual-hardware?r=25568281
diff --git a/boards/renesas/ek_ra4l1/ek_ra4l1-pinctrl.dtsi b/boards/renesas/ek_ra4l1/ek_ra4l1-pinctrl.dtsi
new file mode 100644
index 00000000000..23b0ff8bd65
--- /dev/null
+++ b/boards/renesas/ek_ra4l1/ek_ra4l1-pinctrl.dtsi
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci5_default: sci5_default {
+		group1 {
+			/* tx rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_5, 5, 6)>,
+			<RA_PSEL(RA_PSEL_SCI_5, 5, 7)>;
+		};
+	};
+
+	spi0_default: spi0_default {
+		group1 {
+			/* MISO MOSI RSPCK SSL */
+			psels = <RA_PSEL(RA_PSEL_SPI, 1, 10)>,
+			<RA_PSEL(RA_PSEL_SPI, 1, 9)>,
+			<RA_PSEL(RA_PSEL_SPI, 1, 11)>,
+			<RA_PSEL(RA_PSEL_SPI, 1, 12)>;
+		};
+	};
+
+	adc0_default: adc0_default {
+		group1 {
+			/* input */
+			psels = <RA_PSEL(RA_PSEL_ADC, 0, 3)>;
+			renesas,analog-enable;
+		};
+	};
+
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 4)>;
+			renesas,analog-enable;
+		};
+	};
+
+	pwm1_default: pwm1_default {
+		group1 {
+			/* GTIOC1A GTIOC1B */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 4, 5)>,
+				<RA_PSEL(RA_PSEL_GPT1, 4, 6)>;
+		};
+	};
+
+	iic0_default: iic0_default {
+		group1 {
+			/* SCL0 SDA0 */
+			psels = <RA_PSEL(RA_PSEL_I2C, 1, 1)>,
+			<RA_PSEL(RA_PSEL_I2C, 1, 0)>;
+			drive-strength = "medium";
+		};
+	};
+
+	canfd0_default: canfd0_default {
+		group1 {
+			/* CRX0 CTX0 */
+			psels = <RA_PSEL(RA_PSEL_CANFD, 1, 3)>,
+			<RA_PSEL(RA_PSEL_CANFD, 1, 2)>;
+			drive-strength = "high";
+		};
+	};
+};
diff --git a/boards/renesas/ek_ra4l1/ek_ra4l1.dts b/boards/renesas/ek_ra4l1/ek_ra4l1.dts
new file mode 100644
index 00000000000..21c5eb62f80
--- /dev/null
+++ b/boards/renesas/ek_ra4l1/ek_ra4l1.dts
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra4/r7fa4l1bd4cfp.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/adc/adc.h>
+#include "ek_ra4l1-pinctrl.dtsi"
+
+/ {
+	model = "Renesas EK-RA4L1";
+	compatible = "renesas,ra4l1", "renesas,ra";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash-controller = &flash1;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart5;
+		zephyr,shell-uart = &uart5;
+		zephyr,canbus = &canfd0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1: led1 {
+			gpios = <&ioport6 9 GPIO_ACTIVE_HIGH>;
+			label = "LED1";
+		};
+
+		led2: led2 {
+			gpios = <&ioport6 10 GPIO_ACTIVE_HIGH>;
+			label = "LED2";
+		};
+
+		led3: led3 {
+			gpios = <&ioport6 1 GPIO_ACTIVE_HIGH>;
+			label = "LED3";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		button0: s1 {
+			gpios = <&ioport0 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button switch 1";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		button1: s2 {
+			gpios = <&ioport0 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button switch 2";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+
+	aliases {
+		led0 = &led1;
+		sw0 = &button0;
+		sw1 = &button1;
+		watchdog0 = &wdt;
+	};
+
+	transceiver0: can-phy0 {
+		compatible = "microchip,mcp2562fd", "can-transceiver-gpio";
+		standby-gpios = <&ioport1 6 GPIO_ACTIVE_LOW>;
+		max-bitrate = <5000000>;
+		#phy-cells = <0>;
+	};
+};
+
+&xtal {
+	clock-frequency = <DT_FREQ_M(8)>;
+	mosel = <0>;
+	#clock-cells = <0>;
+	status = "okay";
+};
+
+&subclk {
+	status = "okay";
+};
+
+&pll {
+	clocks = <&xtal>;
+	div = <1>;
+	mul = <10 0>;
+	status = "okay";
+};
+
+&canfdclk {
+	clocks = <&pll>;
+	div = <2>;
+	status = "okay";
+};
+
+&sci5 {
+	pinctrl-0 = <&sci5_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	uart5: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
+
+&ioport0 {
+	status = "okay";
+};
+
+&ioport1 {
+	status = "okay";
+};
+
+&ioport4 {
+	status = "okay";
+};
+
+&ioport5 {
+	status = "okay";
+};
+
+&ioport6 {
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-0 = <&spi0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_default>;
+	pinctrl-names = "default";
+};
+
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&port_irq6 {
+	interrupts = <14 12>;
+	status = "okay";
+};
+
+&port_irq7 {
+	interrupts = <15 12>;
+	status = "okay";
+};
+
+&pwm1 {
+	pinctrl-0 = <&pwm1_default>;
+	pinctrl-names = "default";
+	interrupts = <8 1>, <9 1>;
+	interrupt-names = "gtioca", "overflow";
+	status = "okay";
+};
+
+&iic0 {
+	pinctrl-0 = <&iic0_default>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <DT_FREQ_M(1)>;
+	interrupts = <10 1>, <11 1>, <12 1>, <13 1>;
+	interrupt-names = "rxi", "txi", "tei", "eri";
+	status = "okay";
+};
+
+&canfd_global {
+	status = "okay";
+
+	canfd0 {
+		pinctrl-0 = <&canfd0_default>;
+		pinctrl-names = "default";
+		phys = <&transceiver0>;
+		rx-max-filters = <16>;
+		status = "okay";
+	};
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/boards/renesas/ek_ra4l1/ek_ra4l1.yaml b/boards/renesas/ek_ra4l1/ek_ra4l1.yaml
new file mode 100644
index 00000000000..1c50ba9907c
--- /dev/null
+++ b/boards/renesas/ek_ra4l1/ek_ra4l1.yaml
@@ -0,0 +1,14 @@
+identifier: ek_ra4l1
+name: Renesas EK-RA4L1
+type: mcu
+arch: arm
+ram: 64
+flash: 512
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - uart
+  - watchdog
+vendor: renesas
diff --git a/boards/renesas/ek_ra4l1/ek_ra4l1_defconfig b/boards/renesas/ek_ra4l1/ek_ra4l1_defconfig
new file mode 100644
index 00000000000..f26066de3e5
--- /dev/null
+++ b/boards/renesas/ek_ra4l1/ek_ra4l1_defconfig
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_UART_CONSOLE=y
+CONFIG_CONSOLE=y
diff --git a/boards/renesas/ek_ra4m1/Kconfig.ek_ra4m1 b/boards/renesas/ek_ra4m1/Kconfig.ek_ra4m1
new file mode 100644
index 00000000000..9e52f5c7bde
--- /dev/null
+++ b/boards/renesas/ek_ra4m1/Kconfig.ek_ra4m1
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_EK_RA4M1
+	select SOC_R7FA4M1AB3CFP
diff --git a/boards/renesas/ek_ra4m1/board.cmake b/boards/renesas/ek_ra4m1/board.cmake
new file mode 100644
index 00000000000..8711194800b
--- /dev/null
+++ b/boards/renesas/ek_ra4m1/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7FA4M1AB")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/ek_ra4m1/board.yml b/boards/renesas/ek_ra4m1/board.yml
new file mode 100644
index 00000000000..02926e4a438
--- /dev/null
+++ b/boards/renesas/ek_ra4m1/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: ek_ra4m1
+  full_name: RA4M1 Evaluation Kit
+  vendor: renesas
+  socs:
+  - name: r7fa4m1ab3cfp
diff --git a/boards/renesas/ek_ra4m1/doc/ek_ra4m1.webp b/boards/renesas/ek_ra4m1/doc/ek_ra4m1.webp
new file mode 100644
index 00000000000..510ee1689b0
Binary files /dev/null and b/boards/renesas/ek_ra4m1/doc/ek_ra4m1.webp differ
diff --git a/boards/renesas/ek_ra4m1/doc/index.rst b/boards/renesas/ek_ra4m1/doc/index.rst
new file mode 100644
index 00000000000..2baaeb98c33
--- /dev/null
+++ b/boards/renesas/ek_ra4m1/doc/index.rst
@@ -0,0 +1,130 @@
+.. zephyr:board:: ek_ra4m1
+
+Overview
+********
+
+The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit
+cores that share a common set of Renesas peripherals to facilitate design scalability
+and efficient platform-based product development.
+The MCU provides an optimal combination of low-power, high-performance Arm Cortex®-M4 core
+running up to 48 MHz with the following features:
+
+**Renesas RA4M1 Microcontroller Group**
+
+- R7FA4M1AB3CFP
+- 100-pin LQFP package
+- 48 MHz Arm® Cortex®-M4 core with Floating Point Unit (FPU)
+- 32 KB SRAM
+- 256 KB code flash memory
+- 8 KB data flash memory
+
+**Connectivity**
+
+- A Device USB connector for the Main MCU
+- SEGGER J-Link® On-Board (OB) interface for debugging and programming of the RA4M1 MCU. A
+  10pin JTAG/SWD interface is also provided for connecting optional external debuggers and
+  programmers.
+- Two PMOD connectors, allowing use of appropriate PMOD compliant peripheral plug-in modules for
+  rapid prototyping
+- Pin headers for access to power and signals for the Main MCU
+
+**Multiple clock sources**
+
+- Main MCU oscillator crystals, providing precision 12.000 MHz and 32,768 Hz external reference
+  clocks
+- Additional low-precision clocks are available internal to the Main MCU
+
+**General purpose I/O ports**
+
+- One jumper to allow measuring of Main MCU current
+- Copper jumpers on PCB bottom side for configuration and access to selected MCU signals
+
+**Operating voltage**
+
+- External 5 V input through the Debug USB connector supplies the on-board power regulator to power
+  logic and interfaces on the board. External 5 V or 3.3 V may be also supplied through alternate
+  locations on the board.
+- A two-color board status LED indicating availability of regulated power and connection status of the J-Link
+  interface.
+- A red User LED, controlled by the Main MCU firmware
+- A User Push-Button switch, User Capacitive Touch Button sensor, and an optional User Potentiometer,
+  all of which are controlled by the Main MCU firmware
+- MCU reset push-button switch
+- MCU boot configuration jumper
+
+Hardware
+********
+
+Detailed hardware features can be found at:
+
+- RA4M1 MCU: `RA4M1 Group User's Manual Hardware`_
+- EK-RA4M1 board: `EK-RA4M1 - User's Manual`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``ek_ra4m1`` board can be built, flashed, and debugged
+in the usual way. See :ref:`build_an_application` and :ref:`application_run`
+for more details on building and running.
+
+Flashing
+========
+
+Program can be flashed to EK-RA4M1 via the on-board SEGGER J-Link debugger.
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
+
+To flash the program to board
+
+1. Connect to J-Link OB via USB port to host PC
+
+2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4M1 - User's Manual`_
+
+3. Execute west command
+
+  .. code-block:: console
+
+    west flash -r jlink
+
+Debugging
+=========
+
+You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface
+
+Once downloaded and installed, open Segger Ozone and configure the debug project
+like so:
+
+* Target Device: R7FA4M1AB
+* Target Interface: SWD
+* Target Interface Speed: 4 MHz
+* Host Interface: USB
+* Program File: <path/to/your/build/zephyr.elf>
+
+**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later
+version of Segger Ozone
+
+References
+**********
+- `EK-RA4M1 Website`_
+- `RA4M1 MCU group Website`_
+
+.. _EK-RA4M1 Website:
+   https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m1-evaluation-kit-ra4m1-mcu-group
+
+.. _RA4M1 MCU group Website:
+   https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra4m1-32-bit-microcontrollers-48mhz-arm-cortex-m4-and-lcd-controller-and-cap-touch-hmi
+
+.. _EK-RA4M1 - User's Manual:
+   https://www.renesas.com/us/en/document/mat/ek-ra4m1-v1-users-manual
+
+.. _RA4M1 Group User's Manual Hardware:
+   https://www.renesas.com/us/en/document/mah/renesas-ra4m1-group-users-manual-hardware?r=1054146
+
+.. _Segger Ozone Download:
+   https://www.segger.com/downloads/jlink#Ozone
diff --git a/boards/renesas/ek_ra4m1/ek_ra4m1-pinctrl.dtsi b/boards/renesas/ek_ra4m1/ek_ra4m1-pinctrl.dtsi
new file mode 100644
index 00000000000..50f97bd4796
--- /dev/null
+++ b/boards/renesas/ek_ra4m1/ek_ra4m1-pinctrl.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci1_default: sci1_default {
+		group1 {
+			/* tx rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_1, 4, 1)>,
+			<RA_PSEL(RA_PSEL_SCI_1, 4, 2)>;
+		};
+	};
+
+	spi1_default: spi1_default {
+		group1 {
+			/* MISO MOSI RSPCK SSL */
+			psels = <RA_PSEL(RA_PSEL_SPI, 2, 2)>,
+			<RA_PSEL(RA_PSEL_SPI, 2, 3)>,
+			<RA_PSEL(RA_PSEL_SPI, 2, 4)>,
+			<RA_PSEL(RA_PSEL_SPI, 2, 5)>;
+		};
+	};
+
+	adc0_default: adc0_default {
+		group1 {
+			/* input */
+			psels = <RA_PSEL(RA_PSEL_ADC, 0, 0)>;
+			renesas,analog-enable;
+		};
+	};
+
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
+			renesas,analog-enable;
+		};
+	};
+
+	pwm1_default: pwm1_default {
+		group1 {
+			/* GTIOC1A GTIOC1B */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 4, 5)>,
+				<RA_PSEL(RA_PSEL_GPT1, 4, 6)>;
+		};
+	};
+
+	iic1_default: iic1_default {
+		group1 {
+			/* SCL1 SDA1 */
+			psels = <RA_PSEL(RA_PSEL_I2C, 1, 0)>,
+			<RA_PSEL(RA_PSEL_I2C, 2, 6)>;
+			drive-strength = "medium";
+		};
+	};
+};
diff --git a/boards/renesas/ek_ra4m1/ek_ra4m1.dts b/boards/renesas/ek_ra4m1/ek_ra4m1.dts
new file mode 100644
index 00000000000..054adf4c925
--- /dev/null
+++ b/boards/renesas/ek_ra4m1/ek_ra4m1.dts
@@ -0,0 +1,141 @@
+/*
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra4/r7fa4m1ab3cfp.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <dt-bindings/input/input-event-codes.h>
+#include "ek_ra4m1-pinctrl.dtsi"
+
+/ {
+	model = "Renesas EK-RA4M1";
+	compatible = "renesas,ra4m1", "renesas,ra";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,entropy = &trng;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1: led1 {
+			gpios = <&ioport1 6 GPIO_ACTIVE_HIGH>;
+			label = "LED1";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		button0: s1 {
+			gpios = <&ioport1 5 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button switch 1";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	aliases {
+		led0 = &led1;
+		sw0 = &button0;
+		watchdog0 = &wdt;
+	};
+};
+
+&xtal {
+	clock-frequency = <DT_FREQ_M(12)>;
+	mosel = <0>;
+	#clock-cells = <0>;
+	status = "okay";
+};
+
+&subclk {
+	status = "okay";
+};
+
+&pll {
+	clocks = <&xtal>;
+	div = <2>;
+	mul = <8 0>;
+	status = "okay";
+};
+
+&sci1 {
+	pinctrl-0 = <&sci1_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	uart1: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
+
+&ioport1 {
+	status = "okay";
+};
+
+&ioport2 {
+	status = "okay";
+};
+
+&ioport4 {
+	status = "okay";
+};
+
+&spi1 {
+	pinctrl-0 = <&spi1_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_default>;
+	pinctrl-names = "default";
+};
+
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&port_irq0 {
+	interrupts = <27 12>;
+	status = "okay";
+};
+
+&trng {
+	status = "okay";
+};
+
+&pwm1 {
+	pinctrl-0 = <&pwm1_default>;
+	pinctrl-names = "default";
+	interrupts = <8 1>, <9 1>;
+	interrupt-names = "gtioca", "overflow";
+	status = "okay";
+};
+
+&iic1 {
+	pinctrl-0 = <&iic1_default>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <DT_FREQ_M(1)>;
+	interrupts = <10 1>, <11 1>, <12 1>, <13 1>;
+	interrupt-names = "rxi", "txi", "tei", "eri";
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/boards/renesas/ek_ra4m1/ek_ra4m1.yaml b/boards/renesas/ek_ra4m1/ek_ra4m1.yaml
new file mode 100644
index 00000000000..1e624c9bda6
--- /dev/null
+++ b/boards/renesas/ek_ra4m1/ek_ra4m1.yaml
@@ -0,0 +1,14 @@
+identifier: ek_ra4m1
+name: Renesas EK-RA4M1
+type: mcu
+arch: arm
+ram: 32
+flash: 256
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - uart
+  - watchdog
+vendor: renesas
diff --git a/boards/renesas/ek_ra4m1/ek_ra4m1_defconfig b/boards/renesas/ek_ra4m1/ek_ra4m1_defconfig
new file mode 100644
index 00000000000..770a30fc47d
--- /dev/null
+++ b/boards/renesas/ek_ra4m1/ek_ra4m1_defconfig
@@ -0,0 +1,11 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_UART_CONSOLE=y
+CONFIG_CONSOLE=y
diff --git a/boards/renesas/ek_ra4m2/doc/index.rst b/boards/renesas/ek_ra4m2/doc/index.rst
index 08025a1836f..3ce70ec23cd 100644
--- a/boards/renesas/ek_ra4m2/doc/index.rst
+++ b/boards/renesas/ek_ra4m2/doc/index.rst
@@ -1,7 +1,4 @@
-.. _ek_ra4m2:
-
-RA4M2 Evaluation Kit
-####################
+.. zephyr:board:: ek_ra4m2
 
 Overview
 ********
@@ -17,17 +14,19 @@ The MCU in this series incorporates a high-performance Arm Cortex®-M33 core run
 100 MHz with the following features:
 
 **Renesas RA4M2 Microcontroller Group**
+
 - R7FA4M2AD3CFP
 - 100-pin LQFP package
 - 100 MHz Arm® Cortex®-M33 core
 - 512 kB Code Flash, 128 KB SRAM
 - Native pin access through 4 x 28-pin male headers
 - MCU current measurement points for precision current consumption measurement
--  Multiple clock sources - RA MCU oscillator and sub-clock oscillator crystals, providing
-precision 24.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are
-available internal to the RA MCU
+- Multiple clock sources - RA MCU oscillator and sub-clock oscillator crystals, providing
+  precision 24.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are
+  available internal to the RA MCU
 
 **System Control and Ecosystem Access**
+
 - USB Full Speed Host and Device (micro AB connector)
 - Three 5 V input sources
 
@@ -59,17 +58,12 @@ available internal to the RA MCU
 - MCU boot configuration jumper
 
 **Special Feature Access**
-- 32 MB (256 Mb) External Quad-SPI Flash
 
-.. figure:: ek_ra4m2.webp
-	:align: center
-	:alt: RA4M2 Evaluation Kit
-
-	EK-RA4M2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
+- 32 MB (256 Mb) External Quad-SPI Flash
 
 Hardware
 ********
-Detail Hardware feature for the RA4M2 MCU group can be found at `RA4M2 Group User's Manual Hardware`_
+Detailed hardware features for the RA4M2 MCU group can be found at `RA4M2 Group User's Manual Hardware`_
 
 .. figure:: ra4m2_block_diagram.webp
 	:width: 442px
@@ -78,44 +72,18 @@ Detail Hardware feature for the RA4M2 MCU group can be found at `RA4M2 Group Use
 
 	RA4M2 Block diagram (Credit: Renesas Electronics Corporation)
 
-Detail Hardware feature for the EK-RA4M2 MCU can be found at `EK-RA4M2 - User's Manual`_
+Detailed hardware features for the EK-RA4M2 MCU can be found at `EK-RA4M2 - User's Manual`_
 
 Supported Features
 ==================
 
-The below features are currently supported on Zephyr OS for EK-RA4M2 board:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock control        |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| COUNTER   | on-chip    | counter              |
-+-----------+------------+----------------------+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``ek_ra4m2`` board target configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
@@ -125,15 +93,15 @@ Flashing
 ========
 
 Program can be flashed to EK-RA4M2 via the on-board SEGGER J-Link debugger.
-SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
 
 To flash the program to board
 
-  1. Connect to J-Link OB via USB port to host PC
+1. Connect to J-Link OB via USB port to host PC
 
-  2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4M2 - User's Manual`_
+2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4M2 - User's Manual`_
 
-  3. Execute west command
+3. Execute west command
 
 	.. code-block:: console
 
diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2-pinctrl.dtsi b/boards/renesas/ek_ra4m2/ek_ra4m2-pinctrl.dtsi
index cd65bed269b..97e386641c8 100644
--- a/boards/renesas/ek_ra4m2/ek_ra4m2-pinctrl.dtsi
+++ b/boards/renesas/ek_ra4m2/ek_ra4m2-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -30,6 +30,14 @@
 		};
 	};
 
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
+			renesas,analog-enable;
+		};
+	};
+
 	pwm1_default: pwm1_default {
 		group1 {
 			/* GTIOC1A GTIOC1B */
@@ -46,4 +54,12 @@
 			drive-strength = "medium";
 		};
 	};
+
+	usbfs_default: usbfs_default {
+		group1 {
+			/* USB_VBUS */
+			psels = <RA_PSEL(RA_PSEL_USBFS, 4, 7)>;
+			drive-strength = "high";
+		};
+	};
 };
diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.dts b/boards/renesas/ek_ra4m2/ek_ra4m2.dts
index 23e7c573ad1..a3ade121275 100644
--- a/boards/renesas/ek_ra4m2/ek_ra4m2.dts
+++ b/boards/renesas/ek_ra4m2/ek_ra4m2.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -21,6 +21,7 @@
 		zephyr,flash = &flash0;
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
+		zephyr,entropy = &trng;
 	};
 
 	leds {
@@ -57,6 +58,7 @@
 		led0 = &led1;
 		sw0 = &button0;
 		sw1 = &button1;
+		watchdog0 = &wdt;
 	};
 };
 
@@ -78,6 +80,19 @@
 	status = "okay";
 };
 
+&pll2 {
+	clocks = <&xtal>;
+	div = <2>;
+	mul = <20 0>;
+	status = "okay";
+};
+
+&uclk {
+	clocks = <&pll2>;
+	div = <5>;
+	status = "okay";
+};
+
 &sci0 {
 	pinctrl-0 = <&sci0_default>;
 	pinctrl-names = "default";
@@ -108,6 +123,12 @@
 	pinctrl-names = "default";
 };
 
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &port_irq10 {
 	interrupts = <41 12>;
 	status = "okay";
@@ -149,3 +170,21 @@
 		};
 	};
 };
+
+&trng {
+	status = "okay";
+};
+
+&usbfs {
+	pinctrl-0 = <&usbfs_default>;
+	pinctrl-names = "default";
+	maximum-speed = "full-speed";
+	status = "okay";
+	zephyr_udc0: udc {
+		status = "okay";
+	};
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2.yaml b/boards/renesas/ek_ra4m2/ek_ra4m2.yaml
index d61c6bf05fe..74567cb2432 100644
--- a/boards/renesas/ek_ra4m2/ek_ra4m2.yaml
+++ b/boards/renesas/ek_ra4m2/ek_ra4m2.yaml
@@ -10,3 +10,6 @@ toolchain:
 supported:
   - gpio
   - uart
+  - usbd
+  - watchdog
+vendor: renesas
diff --git a/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig b/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig
index 93569c968fc..770a30fc47d 100644
--- a/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig
+++ b/boards/renesas/ek_ra4m2/ek_ra4m2_defconfig
@@ -1,8 +1,6 @@
 # Copyright (c) 2024 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000
-
 # Enable GPIO
 CONFIG_GPIO=y
 
@@ -11,6 +9,3 @@ CONFIG_SERIAL=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
 CONFIG_UART_CONSOLE=y
 CONFIG_CONSOLE=y
-
-CONFIG_BUILD_OUTPUT_HEX=y
-CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/ek_ra4m3/doc/index.rst b/boards/renesas/ek_ra4m3/doc/index.rst
index fc96aade862..f4b3911d679 100644
--- a/boards/renesas/ek_ra4m3/doc/index.rst
+++ b/boards/renesas/ek_ra4m3/doc/index.rst
@@ -1,7 +1,4 @@
-.. _ek_ra4m3:
-
-RA4M3 Evaluation Kit
-####################
+.. zephyr:board:: ek_ra4m3
 
 Overview
 ********
@@ -18,6 +15,7 @@ The MCU in this series incorporates a high-performance Arm Cortex®-M33 core run
 100 MHz with the following features:
 
 **MCU Native Pin Access**
+
 - R7FA4M3AF3CFB
 - 100-pin LQFP package
 - 100 MHz Arm® Cortex®-M33 core
@@ -26,24 +24,23 @@ The MCU in this series incorporates a high-performance Arm Cortex®-M33 core run
 - Native pin access through 4 x 40-pin male headers
 - MCU and USB current measurement points for precision current consumption measurement
 - Multiple clock sources - RA MCU oscillator and sub-clock oscillator crystals, providing precision
-24.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are available internal to the
-RA MCU
+  24.000 MHz and 32,768 Hz reference clock. Additional low-precision clocks are available internal to the
+  RA MCU
 
 **System Control and Ecosystem Access**
+
 - USB Full Speed Host and Device (micro AB connector)
-- Three 5 V input sources
 
+- Three 5 V input sources
 	- USB (Debug, Full Speed)
 	- External power supply (using surface mount clamp test points and power input vias)
 
- Three Debug modes
-
+- Three Debug modes
 	- Debug on-board (SWD)
 	- Debug in (ETM, SWD, and JTAG)
 	- Debug out (SWD)
 
- User LEDs and buttons
-
+- User LEDs and buttons
 	- Three User LEDs (red, blue, green)
 	- Power LED (white) indicating availability of regulated power
 	- Debug LED (yellow) indicating the debug connection
@@ -51,7 +48,6 @@ RA MCU
 	- One Reset button
 
 - Five most popular ecosystems expansions
-
 	- 2 Seeed Grove® system (I2C/Analog) connectors
 	- SparkFun® Qwiic® connector
 	- 2 Digilent PmodTM (SPI and UART) connectors
@@ -63,15 +59,9 @@ RA MCU
 **Special Feature Access**
 - 32 MB (256 Mb) External Quad-SPI Flash
 
-.. figure:: ek_ra4m3.webp
-	:align: center
-	:alt: RA4M3 Evaluation Kit
-
-	EK-RA4M3 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
-
 Hardware
 ********
-Detail Hardware feature for the RA4M3 MCU group can be found at `RA4M3 Group User's Manual Hardware`_
+Detailed hardware features for the RA4M3 MCU group can be found at `RA4M3 Group User's Manual Hardware`_
 
 .. figure:: ra4m3_block_diagram.webp
 	:width: 442px
@@ -80,44 +70,18 @@ Detail Hardware feature for the RA4M3 MCU group can be found at `RA4M3 Group Use
 
 	RA4M3 Block diagram (Credit: Renesas Electronics Corporation)
 
-Detail Hardware feature for the EK-RA4M3 MCU can be found at `EK-RA4M3 - User's Manual`_
+Detailed hardware features for the EK-RA4M3 MCU can be found at `EK-RA4M3 - User's Manual`_
 
 Supported Features
 ==================
 
-The below features are currently supported on Zephyr OS for EK-RA4M3 board:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock control        |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| COUNTER   | on-chip    | counter              |
-+-----------+------------+----------------------+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``ek_ra4m3`` board target configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
@@ -127,7 +91,7 @@ Flashing
 ========
 
 Program can be flashed to EK-RA4M3 via the on-board SEGGER J-Link debugger.
-SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
 
 To flash the program to board
 
diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3-pinctrl.dtsi b/boards/renesas/ek_ra4m3/ek_ra4m3-pinctrl.dtsi
index 93f63b5a56a..0b574b13c5f 100644
--- a/boards/renesas/ek_ra4m3/ek_ra4m3-pinctrl.dtsi
+++ b/boards/renesas/ek_ra4m3/ek_ra4m3-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -30,6 +30,14 @@
 		};
 	};
 
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
+			renesas,analog-enable;
+		};
+	};
+
 	pwm1_default: pwm1_default {
 		group1 {
 			/* GTIOC1A GTIOC1B */
@@ -46,4 +54,12 @@
 			drive-strength = "medium";
 		};
 	};
+
+	usbfs_default: usbfs_default {
+		group1 {
+			/* USB_VBUS */
+			psels = <RA_PSEL(RA_PSEL_USBFS, 4, 7)>;
+			drive-strength = "high";
+		};
+	};
 };
diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.dts b/boards/renesas/ek_ra4m3/ek_ra4m3.dts
index 05b258b3652..384da60afca 100644
--- a/boards/renesas/ek_ra4m3/ek_ra4m3.dts
+++ b/boards/renesas/ek_ra4m3/ek_ra4m3.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -21,6 +21,7 @@
 		zephyr,flash = &flash0;
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
+		zephyr,entropy = &trng;
 	};
 
 	leds {
@@ -57,6 +58,7 @@
 		led0 = &led1;
 		sw0 = &button0;
 		sw1 = &button1;
+		watchdog0 = &wdt;
 	};
 };
 
@@ -78,6 +80,19 @@
 	status = "okay";
 };
 
+&pll2 {
+	clocks = <&xtal>;
+	div = <3>;
+	mul = <24 0>;
+	status = "okay";
+};
+
+&uclk {
+	clocks = <&pll2>;
+	div = <4>;
+	status = "okay";
+};
+
 &sci0 {
 	pinctrl-0 = <&sci0_default>;
 	pinctrl-names = "default";
@@ -108,6 +123,12 @@
 	pinctrl-names = "default";
 };
 
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &port_irq10 {
 	interrupts = <41 12>;
 	status = "okay";
@@ -149,3 +170,21 @@
 		};
 	};
 };
+
+&trng {
+	status = "okay";
+};
+
+&usbfs {
+	pinctrl-0 = <&usbfs_default>;
+	pinctrl-names = "default";
+	maximum-speed = "full-speed";
+	status = "okay";
+	zephyr_udc0: udc {
+		status = "okay";
+	};
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3.yaml b/boards/renesas/ek_ra4m3/ek_ra4m3.yaml
index e05b8e804da..3035a25af53 100644
--- a/boards/renesas/ek_ra4m3/ek_ra4m3.yaml
+++ b/boards/renesas/ek_ra4m3/ek_ra4m3.yaml
@@ -10,3 +10,6 @@ toolchain:
 supported:
   - gpio
   - uart
+  - usbd
+  - watchdog
+vendor: renesas
diff --git a/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig b/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig
index 93569c968fc..770a30fc47d 100644
--- a/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig
+++ b/boards/renesas/ek_ra4m3/ek_ra4m3_defconfig
@@ -1,8 +1,6 @@
 # Copyright (c) 2024 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=100000000
-
 # Enable GPIO
 CONFIG_GPIO=y
 
@@ -11,6 +9,3 @@ CONFIG_SERIAL=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
 CONFIG_UART_CONSOLE=y
 CONFIG_CONSOLE=y
-
-CONFIG_BUILD_OUTPUT_HEX=y
-CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/ek_ra4w1/doc/index.rst b/boards/renesas/ek_ra4w1/doc/index.rst
index c9501e3dc1d..89c92588b98 100644
--- a/boards/renesas/ek_ra4w1/doc/index.rst
+++ b/boards/renesas/ek_ra4w1/doc/index.rst
@@ -1,7 +1,4 @@
-.. _ek_ra4w1:
-
-RA4W1 Evaluation Kit
-####################
+.. zephyr:board:: ek_ra4w1
 
 Overview
 ********
@@ -14,54 +11,56 @@ excellent reception performance. RA4W1 is geared towards IoT application requiri
 embedded RAM and low power consumption.
 
 **MCU Native Pin Access**
+
 - R7FA4W1AD2CNG
 - QFN-56 package
 - On-chip memory: 512-KB ROM, 96-KB RAM, 8-KB data flash memory
 
 **Power-supply voltage**
+
 - USB connector: 5-V input
 - Power-supply IC: 5-V input, 3.3-V output
 - External power-supply header*1: 3.3-V input, 2 pins x 1
 
 **Main clock**
+
 - Crystal oscillator (surface-mount technology (SMT)) for the main system clock
 - Crystal oscillator or ceramic resonator (lead type) for the main system clock
 
 **Sub-clock**
+
 - Crystal oscillator (SMT) for the sub-clock
 
 **Bluetooth Low Energy**
+
 - Bluetooth Low Energy (BLE) circuit x1
 - Range of frequency: 2402 to 2480 MHz
 - Maximum transmission output power: 4 dBm (in 4-dBm output mode)
 - Output variation: +2 dB
 
 **Push switches**
+
 - Reset switch x 1
 - User switch x 1
 
 **LED**
+
 - Power indicator: green x 1
 - User: green x 2
 - ACT LED: green x 1
 
-**Conetivity**
+**Connectivity**
+
 - Connector for an on-board emulator: USB Micro-B
 - Connector for a USB serial-conversion interface: USB Micro-B
 - Pmod™ connector: Angle type, 12 pins
 - Arduino™ UNO connectors
 
-- Emulator reset switch
-
-.. figure:: ek_ra4w1.webp
-	:align: center
-	:alt: RA4W1 Evaluation Kit
-
-	EK-RA4W1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
+- Emulator reset switch: DIP switch x 1
 
 Hardware
 ********
-Detail Hardware feature for the RA4W1 MCU group can be found at `RA4W1 Group User's Manual Hardware`_
+Detailed Hardware features for the RA4W1 MCU group can be found at `RA4W1 Group User's Manual Hardware`_
 
 .. figure:: ra4w1_block_diagram.webp
 	:width: 442px
@@ -70,44 +69,18 @@ Detail Hardware feature for the RA4W1 MCU group can be found at `RA4W1 Group Use
 
 	RA4W1 Block diagram (Credit: Renesas Electronics Corporation)
 
-Detail Hardware feature for the EK-RA4W1 MCU can be found at `EK-RA4W1 - User's Manual`_
+Detailed Hardware features for the EK-RA4W1 MCU can be found at `EK-RA4W1 - User's Manual`_
 
 Supported Features
 ==================
 
-The below features are currently supported on Zephyr OS for EK-RA4W1 board:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock control        |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| COUNTER   | on-chip    | counter              |
-+-----------+------------+----------------------+
-| ENTROPY   | on-chip    | entropy              |
-+-----------+------------+----------------------+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``ek_ra4w1`` board target configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
@@ -117,15 +90,15 @@ Flashing
 ========
 
 Program can be flashed to EK-RA4W1 via the on-board SEGGER J-Link debugger.
-SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
 
 To flash the program to board
 
-  1. Connect to J-Link OB via USB port to host PC
+1. Connect to J-Link OB via USB port to host PC
 
-  2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4W1 - User's Manual`_
+2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA4W1 - User's Manual`_
 
-  3. Execute west command
+3. Execute west command
 
 	.. code-block:: console
 
diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1-pinctrl.dtsi b/boards/renesas/ek_ra4w1/ek_ra4w1-pinctrl.dtsi
index f0b48f12f95..93c32a1721e 100644
--- a/boards/renesas/ek_ra4w1/ek_ra4w1-pinctrl.dtsi
+++ b/boards/renesas/ek_ra4w1/ek_ra4w1-pinctrl.dtsi
@@ -30,6 +30,14 @@
 		};
 	};
 
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
+			renesas,analog-enable;
+		};
+	};
+
 	pwm1_default: pwm1_default {
 		group1 {
 			/* GTIOC1A GTIOC1B */
diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1.dts b/boards/renesas/ek_ra4w1/ek_ra4w1.dts
index a8adbfd99a1..7ab31de3e89 100644
--- a/boards/renesas/ek_ra4w1/ek_ra4w1.dts
+++ b/boards/renesas/ek_ra4w1/ek_ra4w1.dts
@@ -48,6 +48,7 @@
 	aliases {
 		led0 = &led1;
 		sw0 = &button0;
+		watchdog0 = &wdt;
 	};
 };
 
@@ -89,8 +90,14 @@
 	pinctrl-names = "default";
 };
 
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &port_irq4 {
-	interrupts = <31 12>;
+	interrupts = <27 12>;
 	status = "okay";
 };
 
@@ -112,3 +119,7 @@
 	interrupt-names = "rxi", "txi", "tei", "eri";
 	status = "okay";
 };
+
+&wdt {
+	status = "okay";
+};
diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1.yaml b/boards/renesas/ek_ra4w1/ek_ra4w1.yaml
index f31bcd0a7bc..6d6decc81cd 100644
--- a/boards/renesas/ek_ra4w1/ek_ra4w1.yaml
+++ b/boards/renesas/ek_ra4w1/ek_ra4w1.yaml
@@ -10,3 +10,5 @@ toolchain:
 supported:
   - gpio
   - uart
+  - watchdog
+vendor: renesas
diff --git a/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig b/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig
index 631c90786a6..770a30fc47d 100644
--- a/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig
+++ b/boards/renesas/ek_ra4w1/ek_ra4w1_defconfig
@@ -1,8 +1,6 @@
 # Copyright (c) 2024 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=32000000
-
 # Enable GPIO
 CONFIG_GPIO=y
 
@@ -11,6 +9,3 @@ CONFIG_SERIAL=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
 CONFIG_UART_CONSOLE=y
 CONFIG_CONSOLE=y
-
-CONFIG_BUILD_OUTPUT_HEX=y
-CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/ek_ra6e2/doc/index.rst b/boards/renesas/ek_ra6e2/doc/index.rst
index 46fb121cc82..3b476688eb3 100644
--- a/boards/renesas/ek_ra6e2/doc/index.rst
+++ b/boards/renesas/ek_ra6e2/doc/index.rst
@@ -1,7 +1,4 @@
-.. _ek_ra6e2:
-
-RA6E2 Evaluation Kit
-####################
+.. zephyr:board:: ek_ra6e2
 
 Overview
 ********
@@ -22,7 +19,7 @@ The key features of the EK-RA6E2 board are categorized in three groups as follow
 - MCU current measurement points for precision current consumption measurement
 - Multiple clock sources - RA6E2 MCU oscillator and sub-clock oscillator crystals,
   providing precision 20.000 MHz and 32,768 Hz reference clock.
-  Additional low precision clocks are avaialbe internal to the RA6E2 MCU
+  Additional low precision clocks are available internal to the RA6E2 MCU
 
 **System Control and Ecosystem Access**
 
@@ -61,15 +58,9 @@ The key features of the EK-RA6E2 board are categorized in three groups as follow
 - 16 Mb (128 Mb) External Quad-SPI Flash
 - CAN (3-pin header)
 
-.. figure:: ek_ra6e2.webp
-	:align: center
-	:alt: RA6E2 Evaluation Kit
-
-	EK-RA6E2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
-
 Hardware
 ********
-Detailed hardware feature for the RA6E2 MCU group can be found at `RA6E2 Group User's Manual Hardware`_
+Detailed hardware features for the RA6E2 MCU group can be found at `RA6E2 Group User's Manual Hardware`_
 
 .. figure:: ra6e2_block_diagram.webp
 	:width: 442px
@@ -78,42 +69,18 @@ Detailed hardware feature for the RA6E2 MCU group can be found at `RA6E2 Group U
 
 	RA6E2 Block diagram (Credit: Renesas Electronics Corporation)
 
-Detailed hardware feature for the EK-RA6E2 MCU can be found at `EK-RA6E2 - User's Manual`_
+Detailed hardware features for the EK-RA6E2 MCU can be found at `EK-RA6E2 - User's Manual`_
 
 Supported Features
 ==================
 
-The below features are currently supported on Zephyr OS for EK-RA6E2 board:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock control        |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| ENTROPY   | on-chip    | entropy              |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``ek_ra6e2`` board target configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
@@ -123,15 +90,15 @@ Flashing
 ========
 
 Program can be flashed to EK-RA6E2 via the on-board SEGGER J-Link debugger.
-SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
 
 To flash the program to board
 
-  1. Connect to J-Link OB via USB port to host PC
+1. Connect to J-Link OB via USB port to host PC
 
-  2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6E2 - User's Manual`_
+2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6E2 - User's Manual`_
 
-  3. Execute west command
+3. Execute west command
 
 	.. code-block:: console
 
diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi b/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi
index f947ec6eba7..f8065c394f9 100644
--- a/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi
+++ b/boards/renesas/ek_ra6e2/ek_ra6e2-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -39,6 +39,14 @@
 		};
 	};
 
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
+			renesas,analog-enable;
+		};
+	};
+
 	pwm1_default: pwm1_default {
 		group1 {
 			/* GTIOC1A GTIOC1B */
diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.dts b/boards/renesas/ek_ra6e2/ek_ra6e2.dts
index a2ef88dba3e..7d4911bb9da 100644
--- a/boards/renesas/ek_ra6e2/ek_ra6e2.dts
+++ b/boards/renesas/ek_ra6e2/ek_ra6e2.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -60,6 +60,7 @@
 		led0 = &led1;
 		sw0 = &button0;
 		sw1 = &button1;
+		watchdog0 = &wdt;
 	};
 };
 
@@ -143,6 +144,12 @@
 	pinctrl-names = "default";
 };
 
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &port_irq9 {
 	interrupts = <4 12>;
 	status = "okay";
@@ -178,3 +185,7 @@
 		};
 	};
 };
+
+&wdt {
+	status = "okay";
+};
diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2.yaml b/boards/renesas/ek_ra6e2/ek_ra6e2.yaml
index dcb71bda519..dc2a982ccc3 100644
--- a/boards/renesas/ek_ra6e2/ek_ra6e2.yaml
+++ b/boards/renesas/ek_ra6e2/ek_ra6e2.yaml
@@ -9,3 +9,5 @@ toolchain:
   - gnuarmemb
 supported:
   - gpio
+  - watchdog
+vendor: renesas
diff --git a/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig b/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig
index 882cf699d98..770a30fc47d 100644
--- a/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig
+++ b/boards/renesas/ek_ra6e2/ek_ra6e2_defconfig
@@ -1,8 +1,6 @@
 # Copyright (c) 2024 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
-
 # Enable GPIO
 CONFIG_GPIO=y
 
@@ -11,6 +9,3 @@ CONFIG_SERIAL=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
 CONFIG_UART_CONSOLE=y
 CONFIG_CONSOLE=y
-
-CONFIG_BUILD_OUTPUT_HEX=y
-CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/ek_ra6m1/doc/index.rst b/boards/renesas/ek_ra6m1/doc/index.rst
index 88aa944e3c1..0c91d3905e0 100644
--- a/boards/renesas/ek_ra6m1/doc/index.rst
+++ b/boards/renesas/ek_ra6m1/doc/index.rst
@@ -1,7 +1,4 @@
-.. _ek_ra6m1:
-
-RA6M1 Evaluation Kit
-####################
+.. zephyr:board:: ek_ra6m1
 
 Overview
 ********
@@ -17,6 +14,7 @@ low power consumption.
 The key features of the EK-RA6M1 board are categorized in three groups as follow:
 
 **MCU Native Pin Access**
+
 - R7FA6M1AD3CFP
 - 100-pin LQFP package
 - 120 MHz Arm® Cortex®-M4 core with Floating Point Unit (FPU)
@@ -25,47 +23,42 @@ The key features of the EK-RA6M1 board are categorized in three groups as follow
 - 8 KB data flash memory
 
 **Connectivity**
+
 - A Device USB connector for the Main MCU
 - S124 MCU-based SEGGER J-Link® On-Board interface for debugging and programming of the
-RA6M1 MCU. A 10-pin JTAG/SWD interface is also provided for connecting optional external
-debuggers and programmers.
+  RA6M1 MCU. A 10-pin JTAG/SWD interface is also provided for connecting optional external
+  debuggers and programmers.
 - Two PMOD connectors, allowing use of appropriate PMOD compliant peripheral plug-in modules for
-rapid prototyping
+  rapid prototyping.
 - Pin headers for access to power and signals for the Main MCU
 
 **Multiple clock sources**
+
 - Main MCU oscillator crystals, providing precision 12.000 MHz and 32,768 Hz external reference
-clocks
+  clocks
 - Additional low-precision clocks are available internal to the Main MCU
 
 **General purpose I/O ports**
+
 - One jumper to allow measuring of Main MCU current
 - Copper jumpers on PCB bottom side for configuration and access to selected MCU signals
+
 **Operating voltage**
+
 - External 5 V input through the Debug USB connector supplies the on-board power regulator to power
-logic and interfaces on the board. External 5 V or 3.3 V may be also supplied through alternate
-locations on the board.
+  logic and interfaces on the board. External 5 V or 3.3 V may be also supplied through alternate
+  locations on the board.
 - A two-color board status LED indicating availability of regulated power and connection status of the J-Link
-interface.
+  interface.
 - A red User LED, controlled by the Main MCU firmware
 - A User Push-Button switch, User Capacitive Touch Button sensor, and an optional User Potentiometer,
-all of which are controlled by the Main MCU firmware
+  all of which are controlled by the Main MCU firmware
 - MCU reset push-button switch
 - MCU boot configuration jumper
 
-**Special Feature Access**
-
-- USB Full Speed Debug and Device (micro-AB connector)
-
-.. figure:: ek_ra6m1.webp
-	:align: center
-	:alt: RA6M1 Evaluation Kit
-
-	EK-RA6M1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
-
 Hardware
 ********
-Detailed hardware feature for the RA6M1 MCU group can be found at `RA6M1 Group User's Manual Hardware`_
+Detailed hardware features for the RA6M1 MCU group can be found at `RA6M1 Group User's Manual Hardware`_
 
 .. figure:: ra6m1_block_diagram.webp
 	:width: 442px
@@ -74,44 +67,18 @@ Detailed hardware feature for the RA6M1 MCU group can be found at `RA6M1 Group U
 
 	RA6M1 Block diagram (Credit: Renesas Electronics Corporation)
 
-Detailed hardware feature for the EK-RA6M1 MCU can be found at `EK-RA6M1 - User's Manual`_
+Detailed hardware features for the EK-RA6M1 MCU can be found at `EK-RA6M1 - User's Manual`_
 
 Supported Features
 ==================
 
-The below features are currently supported on Zephyr OS for EK-RA6M1 board:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock control        |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| COUNTER   | on-chip    | counter              |
-+-----------+------------+----------------------+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``ek_ra6m1`` board target configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
@@ -121,15 +88,15 @@ Flashing
 ========
 
 Program can be flashed to EK-RA6M1 via the on-board SEGGER J-Link debugger.
-SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
 
 To flash the program to board
 
-  1. Connect to J-Link OB via USB port to host PC
+1. Connect to J-Link OB via USB port to host PC
 
-  2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M1 - User's Manual`_
+2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M1 - User's Manual`_
 
-  3. Execute west command
+3. Execute west command
 
 	.. code-block:: console
 
diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi b/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi
index 667e6dcd5c8..87e76e218ca 100644
--- a/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi
+++ b/boards/renesas/ek_ra6m1/ek_ra6m1-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -39,6 +39,14 @@
 		};
 	};
 
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
+			renesas,analog-enable;
+		};
+	};
+
 	pwm1_default: pwm1_default {
 		group1 {
 			/* GTIOC1A GTIOC1B */
@@ -46,4 +54,12 @@
 				<RA_PSEL(RA_PSEL_GPT1, 4, 6)>;
 		};
 	};
+
+	usbfs_default: usbfs_default {
+		group1 {
+			/* USB_VBUS */
+			psels = <RA_PSEL(RA_PSEL_USBFS, 4, 7)>;
+			drive-strength = "high";
+		};
+	};
 };
diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.dts b/boards/renesas/ek_ra6m1/ek_ra6m1.dts
index a6df950b29e..00fd4ff3267 100644
--- a/boards/renesas/ek_ra6m1/ek_ra6m1.dts
+++ b/boards/renesas/ek_ra6m1/ek_ra6m1.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -45,6 +45,7 @@
 	aliases {
 		led0 = &led1;
 		sw0 = &button0;
+		watchdog0 = &wdt;
 	};
 };
 
@@ -111,6 +112,12 @@
 	pinctrl-names = "default";
 };
 
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &port_irq8 {
 	interrupts = <41 12>;
 	status = "okay";
@@ -136,3 +143,23 @@
 		};
 	};
 };
+
+&uclk {
+	clocks = <&pll>;
+	div = <5>;
+	status = "okay";
+};
+
+&usbfs {
+	pinctrl-0 = <&usbfs_default>;
+	pinctrl-names = "default";
+	maximum-speed = "full-speed";
+	status = "okay";
+	zephyr_udc0: udc {
+		status = "okay";
+	};
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1.yaml b/boards/renesas/ek_ra6m1/ek_ra6m1.yaml
index 92e8d569db2..d2aece1948e 100644
--- a/boards/renesas/ek_ra6m1/ek_ra6m1.yaml
+++ b/boards/renesas/ek_ra6m1/ek_ra6m1.yaml
@@ -10,3 +10,6 @@ toolchain:
 supported:
   - gpio
   - uart
+  - usbd
+  - watchdog
+vendor: renesas
diff --git a/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig b/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig
index fb0bf97d888..35ed0307b9a 100644
--- a/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig
+++ b/boards/renesas/ek_ra6m1/ek_ra6m1_defconfig
@@ -1,14 +1,9 @@
 # Copyright (c) 2024 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
-
 # Enable GPIO
 CONFIG_GPIO=y
 
-CONFIG_BUILD_OUTPUT_HEX=y
-CONFIG_CLOCK_CONTROL=y
-
 # Enable Console
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/renesas/ek_ra6m2/doc/index.rst b/boards/renesas/ek_ra6m2/doc/index.rst
index 7ef4dc9589d..8e135b2efaa 100644
--- a/boards/renesas/ek_ra6m2/doc/index.rst
+++ b/boards/renesas/ek_ra6m2/doc/index.rst
@@ -1,7 +1,4 @@
-.. _ek_ra6m2:
-
-RA6M2 Evaluation Kit
-####################
+.. zephyr:board:: ek_ra6m2
 
 Overview
 ********
@@ -20,7 +17,7 @@ The key features of the EK-RA6M2 board are categorized in three groups as follow
 - MCU and USB current measurement points for precision current consumption measurement
 - Multiple clock sources - RA6M2 MCU oscillator and sub-clock oscillator crystals,
   providing precision 12.000 MHz and 32,768 Hz reference clock.
-  Additional low precision clocks are avaialbe internal to the RA6M2 MCU
+  Additional low precision clocks are available internal to the RA6M2 MCU
 
 **System Control and Ecosystem Access**
 
@@ -51,15 +48,9 @@ The key features of the EK-RA6M2 board are categorized in three groups as follow
 
 - USB Full Speed Host and Device (micro-AB connector)
 
-.. figure:: ek_ra6m2.webp
-	:align: center
-	:alt: RA6M2 Evaluation Kit
-
-	EK-RA6M2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
-
 Hardware
 ********
-Detailed hardware feature for the RA6M2 MCU group can be found at `RA6M2 Group User's Manual Hardware`_
+Detailed hardware features for the RA6M2 MCU group can be found at `RA6M2 Group User's Manual Hardware`_
 
 .. figure:: ra6m2_block_diagram.webp
 	:width: 871px
@@ -68,44 +59,18 @@ Detailed hardware feature for the RA6M2 MCU group can be found at `RA6M2 Group U
 
 	RA6M2 Block diagram (Credit: Renesas Electronics Corporation)
 
-Detailed hardware feature for the EK-RA6M2 MCU can be found at `EK-RA6M2 - User's Manual`_
+Detailed hardware features for the EK-RA6M2 MCU can be found at `EK-RA6M2 - User's Manual`_
 
 Supported Features
 ==================
 
-The below features are currently supported on Zephyr OS for EK-RA6M2 board:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock control        |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| COUNTER   | on-chip    | counter              |
-+-----------+------------+----------------------+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``ek_ra6m2`` board target configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
@@ -115,7 +80,7 @@ Flashing
 ========
 
 Program can be flashed to EK-RA6M2 via the on-board SEGGER J-Link debugger.
-SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
 
 To flash the program to board
 
diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2-pinctrl.dtsi b/boards/renesas/ek_ra6m2/ek_ra6m2-pinctrl.dtsi
index bfccf28bc96..85a43362ea8 100644
--- a/boards/renesas/ek_ra6m2/ek_ra6m2-pinctrl.dtsi
+++ b/boards/renesas/ek_ra6m2/ek_ra6m2-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -39,6 +39,14 @@
 		};
 	};
 
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
+			renesas,analog-enable;
+		};
+	};
+
 	pwm1_default: pwm1_default {
 		group1 {
 			/* GTIOC1A GTIOC1B */
@@ -46,4 +54,12 @@
 				<RA_PSEL(RA_PSEL_GPT1, 4, 6)>;
 		};
 	};
+
+	usbfs_default: usbfs_default {
+		group1 {
+			/* USB_VBUS */
+			psels = <RA_PSEL(RA_PSEL_USBFS, 4, 7)>;
+			drive-strength = "high";
+		};
+	};
 };
diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.dts b/boards/renesas/ek_ra6m2/ek_ra6m2.dts
index 46ea01ac4c6..46fcc3ad442 100644
--- a/boards/renesas/ek_ra6m2/ek_ra6m2.dts
+++ b/boards/renesas/ek_ra6m2/ek_ra6m2.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -45,6 +45,7 @@
 	aliases {
 		led0 = &led1;
 		sw0 = &button0;
+		watchdog0 = &wdt;
 	};
 };
 
@@ -107,6 +108,12 @@
 	pinctrl-names = "default";
 };
 
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &port_irq0 {
 	interrupts = <41 12>;
 	status = "okay";
@@ -132,3 +139,23 @@
 		};
 	};
 };
+
+&uclk {
+	clocks = <&pll>;
+	div = <5>;
+	status = "okay";
+};
+
+&usbfs {
+	pinctrl-0 = <&usbfs_default>;
+	pinctrl-names = "default";
+	maximum-speed = "full-speed";
+	status = "okay";
+	zephyr_udc0: udc {
+		status = "okay";
+	};
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2.yaml b/boards/renesas/ek_ra6m2/ek_ra6m2.yaml
index 3f3c049c5e5..a579a97b90d 100644
--- a/boards/renesas/ek_ra6m2/ek_ra6m2.yaml
+++ b/boards/renesas/ek_ra6m2/ek_ra6m2.yaml
@@ -9,3 +9,6 @@ toolchain:
   - gnuarmemb
 supported:
   - gpio
+  - usbd
+  - watchdog
+vendor: renesas
diff --git a/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig b/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig
index fb0bf97d888..35ed0307b9a 100644
--- a/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig
+++ b/boards/renesas/ek_ra6m2/ek_ra6m2_defconfig
@@ -1,14 +1,9 @@
 # Copyright (c) 2024 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
-
 # Enable GPIO
 CONFIG_GPIO=y
 
-CONFIG_BUILD_OUTPUT_HEX=y
-CONFIG_CLOCK_CONTROL=y
-
 # Enable Console
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/renesas/ek_ra6m3/Kconfig.defconfig b/boards/renesas/ek_ra6m3/Kconfig.defconfig
new file mode 100644
index 00000000000..d8546450c2c
--- /dev/null
+++ b/boards/renesas/ek_ra6m3/Kconfig.defconfig
@@ -0,0 +1,13 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_EK_RA6M3
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+endif # NETWORKING
+
+endif # BOARD_EK_RA6M3
diff --git a/boards/renesas/ek_ra6m3/doc/index.rst b/boards/renesas/ek_ra6m3/doc/index.rst
index 1421fbaac1b..76557710d1b 100644
--- a/boards/renesas/ek_ra6m3/doc/index.rst
+++ b/boards/renesas/ek_ra6m3/doc/index.rst
@@ -1,7 +1,4 @@
-.. _ek_ra6m3:
-
-RA6M3 Evaluation Kit
-####################
+.. zephyr:board:: ek_ra6m3
 
 Overview
 ********
@@ -20,7 +17,7 @@ The key features of the EK-RA6M3 board are categorized in three groups as follow
 - MCU and USB current measurement points for precision current consumption measurement
 - Multiple clock sources - RA6M3 MCU oscillator and sub-clock oscillator crystals,
   providing precision 24.000 MHz and 32,768 Hz reference clock.
-  Additional low precision clocks are avaialbe internal to the RA6M3 MCU
+  Additional low precision clocks are available internal to the RA6M3 MCU
 
 **System Control and Ecosystem Access**
 
@@ -59,15 +56,9 @@ The key features of the EK-RA6M3 board are categorized in three groups as follow
 - USB High Speed Host and Device (micro-AB connector)
 - 32 Mb (256 Mb) External Quad-SPI Flash
 
-.. figure:: ek_ra6m3.webp
-	:align: center
-	:alt: RA6M3 Evaluation Kit
-
-	EK-RA6M3 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
-
 Hardware
 ********
-Detailed hardware feature for the RA6M3 MCU group can be found at `RA6M3 Group User's Manual Hardware`_
+Detailed hardware features for the RA6M3 MCU group can be found at `RA6M3 Group User's Manual Hardware`_
 
 .. figure:: ra6m3_block_diagram.webp
 	:width: 442px
@@ -76,46 +67,18 @@ Detailed hardware feature for the RA6M3 MCU group can be found at `RA6M3 Group U
 
 	RA6M3 Block diagram (Credit: Renesas Electronics Corporation)
 
-Detail hardware feature for the EK-RA6M3 MCU can be found at `EK-RA6M3 - User's Manual`_
+Detailed hardware features for the EK-RA6M3 MCU can be found at `EK-RA6M3 - User's Manual`_
 
 Supported Features
 ==================
 
-The below features are currently supported on Zephyr OS for EK-RA6M3 board:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock control        |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| COUNTER   | on-chip    | counter              |
-+-----------+------------+----------------------+
-| USBHS     | on-chip    | udc                  |
-+-----------+------------+----------------------+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``ek_ra6m3`` board target configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
@@ -125,15 +88,15 @@ Flashing
 ========
 
 Program can be flashed to EK-RA6M3 via the on-board SEGGER J-Link debugger.
-SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
 
 To flash the program to board
 
-  1. Connect to J-Link OB via USB port to host PC
+1. Connect to J-Link OB via USB port to host PC
 
-  2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M3 - User's Manual`_
+2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M3 - User's Manual`_
 
-  3. Execute west command
+3. Execute west command
 
 	.. code-block:: console
 
diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi b/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi
index 6c3d7f285fd..b6236c0199a 100644
--- a/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi
+++ b/boards/renesas/ek_ra6m3/ek_ra6m3-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -46,11 +46,43 @@
 		};
 	};
 
-	pwm1_default: pwm1_default {
+	dac0_default: dac0_default {
 		group1 {
-			/* GTIOC1A GTIOC1B */
-			psels = <RA_PSEL(RA_PSEL_GPT1, 4, 5)>,
-				<RA_PSEL(RA_PSEL_GPT1, 4, 6)>;
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
+			renesas,analog-enable;
+		};
+	};
+
+	pwm0_default: pwm0_default {
+		group1 {
+			/* GTIOC0A GTIOC0B */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 4, 15)>,
+				<RA_PSEL(RA_PSEL_GPT1, 4, 14)>;
+		};
+	};
+
+	usbfs_default: usbfs_default {
+		group1 {
+			/* USB_VBUS */
+			psels = <RA_PSEL(RA_PSEL_USBFS, 11, 1)>;
+			drive-strength = "high";
+		};
+	};
+
+	ether_default: ether_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_ETH_RMII, 4, 1)>, /* ET0_MDC */
+				<RA_PSEL(RA_PSEL_ETH_RMII, 4, 2)>, /* ET0_MDIO */
+				<RA_PSEL(RA_PSEL_ETH_RMII, 4, 5)>, /* RMII0_TXD_EN_B */
+				<RA_PSEL(RA_PSEL_ETH_RMII, 4, 6)>, /* RMII0_TXD1_BR */
+				<RA_PSEL(RA_PSEL_ETH_RMII, 7, 0)>, /* RMII0_TXD0_B */
+				<RA_PSEL(RA_PSEL_ETH_RMII, 7, 1)>, /* REF50CK0_B */
+				<RA_PSEL(RA_PSEL_ETH_RMII, 7, 2)>, /* RMII0_RXD0_B */
+				<RA_PSEL(RA_PSEL_ETH_RMII, 7, 3)>, /* RMII0_RXD1_B */
+				<RA_PSEL(RA_PSEL_ETH_RMII, 7, 4)>, /* RMII0_RX_ER_B */
+				<RA_PSEL(RA_PSEL_ETH_RMII, 7, 5)>; /* RMII0_CRS_DV_B */
+			drive-strength = "high";
 		};
 	};
 };
diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.dts b/boards/renesas/ek_ra6m3/ek_ra6m3.dts
index 5ef2fd4b8b5..409f0549ff3 100644
--- a/boards/renesas/ek_ra6m3/ek_ra6m3.dts
+++ b/boards/renesas/ek_ra6m3/ek_ra6m3.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -59,6 +59,7 @@
 		led0 = &led1;
 		sw0 = &button0;
 		sw1 = &button1;
+		watchdog0 = &wdt;
 	};
 };
 
@@ -123,6 +124,12 @@
 	status ="okay";
 };
 
+&uclk {
+	clocks = <&pll>;
+	div = <5>;
+	status = "okay";
+};
+
 &usbhs {
 	pinctrl-0 = <&usbhs_default>;
 	pinctrl-names = "default";
@@ -143,6 +150,12 @@
 	pinctrl-names = "default";
 };
 
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &port_irq12 {
 	interrupts = <41 12>;
 	status = "okay";
@@ -153,8 +166,8 @@
 	status = "okay";
 };
 
-&pwm1 {
-	pinctrl-0 = <&pwm1_default>;
+&pwm0 {
+	pinctrl-0 = <&pwm0_default>;
 	pinctrl-names = "default";
 	interrupts = <63 1>, <64 1>;
 	interrupt-names = "gtioca", "overflow";
@@ -173,3 +186,31 @@
 		};
 	};
 };
+
+&usbfs {
+	pinctrl-0 = <&usbfs_default>;
+	pinctrl-names = "default";
+	maximum-speed = "full-speed";
+};
+
+&wdt {
+	status = "okay";
+};
+
+&eth {
+	local-mac-address = [00 11 22 33 44 57];
+	status = "okay";
+	phy-handle = <&phy>;
+};
+
+&mdio {
+	pinctrl-0 = <&ether_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	phy: ethernet-phy@5 {
+		compatible = "ethernet-phy";
+		reg = <0>;
+		status = "okay";
+	};
+};
diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3.yaml b/boards/renesas/ek_ra6m3/ek_ra6m3.yaml
index 50cc8737e92..c66c24bc725 100644
--- a/boards/renesas/ek_ra6m3/ek_ra6m3.yaml
+++ b/boards/renesas/ek_ra6m3/ek_ra6m3.yaml
@@ -9,3 +9,6 @@ toolchain:
   - gnuarmemb
 supported:
   - gpio
+  - usbd
+  - watchdog
+vendor: renesas
diff --git a/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig b/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig
index 914980bc08c..791f9faca40 100644
--- a/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig
+++ b/boards/renesas/ek_ra6m3/ek_ra6m3_defconfig
@@ -1,8 +1,6 @@
 # Copyright (c) 2024 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=120000000
-
 # Enable GPIO
 CONFIG_GPIO=y
 
@@ -11,6 +9,3 @@ CONFIG_SERIAL=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
-
-CONFIG_BUILD_OUTPUT_HEX=y
-CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/ek_ra6m4/doc/index.rst b/boards/renesas/ek_ra6m4/doc/index.rst
index 1945197d633..2dce8bb0fc6 100644
--- a/boards/renesas/ek_ra6m4/doc/index.rst
+++ b/boards/renesas/ek_ra6m4/doc/index.rst
@@ -1,7 +1,4 @@
-.. _ek_ra6m4:
-
-RA6M4 Evaluation Kit
-####################
+.. zephyr:board:: ek_ra6m4
 
 Overview
 ********
@@ -24,7 +21,7 @@ The key features of the EK-RA6M4 board are categorized in three groups as follow
 - MCU current measurement points for precision current consumption measurement
 - Multiple clock sources - RA6M4 MCU oscillator and sub-clock oscillator crystals,
   providing precision 24.000 MHz and 32,768 Hz reference clock.
-  Additional low precision clocks are avaialbe internal to the RA6M4 MCU
+  Additional low precision clocks are available internal to the RA6M4 MCU
 
 **System Control and Ecosystem Access**
 
@@ -64,15 +61,9 @@ The key features of the EK-RA6M4 board are categorized in three groups as follow
 - 32 Mb (256 Mb) External Quad-SPI Flash
 - 64 Mb (512 Mb) External Octo-SPI Flash
 
-.. figure:: ek_ra6m4.webp
-	:align: center
-	:alt: RA6M4 Evaluation Kit
-
-	EK-RA6M4 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
-
 Hardware
 ********
-Detailed hardware feature for the RA6M4 MCU group can be found at `RA6M4 Group User's Manual Hardware`_
+Detailed hardware features for the RA6M4 MCU group can be found at `RA6M4 Group User's Manual Hardware`_
 
 .. figure:: ra6m4_block_diagram.webp
 	:width: 442px
@@ -81,44 +72,18 @@ Detailed hardware feature for the RA6M4 MCU group can be found at `RA6M4 Group U
 
 	RA6M4 Block diagram (Credit: Renesas Electronics Corporation)
 
-Detailed hardware feature for the EK-RA6M4 MCU can be found at `EK-RA6M4 - User's Manual`_
+Detailed hardware features for the EK-RA6M4 MCU can be found at `EK-RA6M4 - User's Manual`_
 
 Supported Features
 ==================
 
-The below features are currently supported on Zephyr OS for EK-RA6M4 board:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock control        |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| COUNTER   | on-chip    | counter              |
-+-----------+------------+----------------------+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``ek_ra6m4`` board target configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
@@ -128,15 +93,15 @@ Flashing
 ========
 
 Program can be flashed to EK-RA6M4 via the on-board SEGGER J-Link debugger.
-SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
 
 To flash the program to board
 
-  1. Connect to J-Link OB via USB port to host PC
+1. Connect to J-Link OB via USB port to host PC
 
-  2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M4 - User's Manual`_
+2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M4 - User's Manual`_
 
-  3. Execute west command
+3. Execute west command
 
 	.. code-block:: console
 
diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi b/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi
index 29ef6ff2382..081e3a74621 100644
--- a/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi
+++ b/boards/renesas/ek_ra6m4/ek_ra6m4-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -12,6 +12,14 @@
 		};
 	};
 
+	sci7_default: sci7_default {
+		group1 {
+			/* tx rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_7, 6, 13)>,
+			<RA_PSEL(RA_PSEL_SCI_7, 6, 14)>;
+		};
+	};
+
 	iic1_default: iic1_default {
 		group1 {
 			/* SCL1 SDA1 */
@@ -39,6 +47,14 @@
 		};
 	};
 
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
+			renesas,analog-enable;
+		};
+	};
+
 	pwm1_default: pwm1_default {
 		group1 {
 			/* GTIOC1A GTIOC1B */
@@ -46,4 +62,12 @@
 				<RA_PSEL(RA_PSEL_GPT1, 4, 6)>;
 		};
 	};
+
+	usbfs_default: usbfs_default {
+		group1 {
+			/* USB_VBUS */
+			psels = <RA_PSEL(RA_PSEL_USBFS, 4, 7)>;
+			drive-strength = "high";
+		};
+	};
 };
diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.dts b/boards/renesas/ek_ra6m4/ek_ra6m4.dts
index dbfd41347fb..e8ab9b35966 100644
--- a/boards/renesas/ek_ra6m4/ek_ra6m4.dts
+++ b/boards/renesas/ek_ra6m4/ek_ra6m4.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -22,6 +22,7 @@
 		zephyr,flash = &flash0;
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
+		zephyr,entropy = &trng;
 	};
 
 	leds {
@@ -40,6 +41,29 @@
 		};
 	};
 
+	mikrobus_header: mikrobus-connector {
+		compatible = "mikro-bus";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map =	<0 0 &ioport0 0 0>,	/* AN  */
+				<1 0 &ioport1 15 0>,	/* RST */
+				<2 0 &ioport2 5 0>,	/* CS   */
+				<3 0 &ioport2 4 0>,	/* SCK  */
+				<4 0 &ioport2 2 0>,	/* MISO */
+				<5 0 &ioport2 3 0>,	/* MOSI */
+							/* +3.3V */
+							/* GND */
+				<6 0 &ioport4 8 0>,	/* PWM  */
+				<7 0 &ioport4 9 0>,	/* INT  */
+				<8 0 &ioport6 14 0>,	/* RX   */
+				<9 0 &ioport6 13 0>,	/* TX   */
+				<10 0 &ioport5 12 0>,	/* SCL  */
+				<11 0 &ioport5 11 0>;	/* SDA  */
+							/* +5V */
+							/* GND */
+	};
+
 	buttons {
 		compatible = "gpio-keys";
 		button0: s1 {
@@ -58,6 +82,7 @@
 		led0 = &led1;
 		sw0 = &button0;
 		sw1 = &button1;
+		watchdog0 = &wdt;
 	};
 };
 
@@ -71,6 +96,16 @@
 	};
 };
 
+&sci7 {
+	pinctrl-0 = <&sci7_default>;
+	pinctrl-names = "default";
+	status = "okay";
+	uart7: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
+
 &iic1 {
 	status = "okay";
 	#address-cells = <1>;
@@ -92,10 +127,26 @@
 	status = "okay";
 };
 
+&ioport1 {
+	status = "okay";
+};
+
+&ioport2 {
+	status = "okay";
+};
+
 &ioport4 {
 	status = "okay";
 };
 
+&ioport5 {
+	status = "okay";
+};
+
+&ioport6 {
+	status = "okay";
+};
+
 &xtal {
 	clock-frequency = <DT_FREQ_M(24)>;
 	mosel = <0>;
@@ -114,6 +165,13 @@
 	status = "okay";
 };
 
+&pll2 {
+	clocks = <&hoco>;
+	div = <2>;
+	mul = <24 0>;
+	status = "okay";
+};
+
 &pclka {
 	clocks = <&pll>;
 	div = <2>;
@@ -126,6 +184,12 @@
 	pinctrl-names = "default";
 };
 
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &port_irq10 {
 	interrupts = <41 12>;
 	status = "okay";
@@ -156,3 +220,31 @@
 		};
 	};
 };
+
+&trng {
+	status = "okay";
+};
+
+&uclk {
+	clocks = <&pll2>;
+	div = <5>;
+	status = "okay";
+};
+
+&usbfs {
+	pinctrl-0 = <&usbfs_default>;
+	pinctrl-names = "default";
+	maximum-speed = "full-speed";
+	status = "okay";
+	zephyr_udc0: udc {
+		status = "okay";
+	};
+};
+
+mikrobus_serial: &uart7 {};
+mikrobus_i2c: &iic1 {};
+mikrobus_spi: &spi0 {};
+
+&wdt {
+	status = "okay";
+};
diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4.yaml b/boards/renesas/ek_ra6m4/ek_ra6m4.yaml
index d9488b99e81..77c870f0327 100644
--- a/boards/renesas/ek_ra6m4/ek_ra6m4.yaml
+++ b/boards/renesas/ek_ra6m4/ek_ra6m4.yaml
@@ -9,3 +9,6 @@ toolchain:
   - gnuarmemb
 supported:
   - gpio
+  - usbd
+  - watchdog
+vendor: renesas
diff --git a/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig b/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig
index 7d9405d6204..791f9faca40 100644
--- a/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig
+++ b/boards/renesas/ek_ra6m4/ek_ra6m4_defconfig
@@ -1,8 +1,6 @@
 # Copyright (c) 2024 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
-
 # Enable GPIO
 CONFIG_GPIO=y
 
@@ -11,6 +9,3 @@ CONFIG_SERIAL=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
 CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
-
-CONFIG_BUILD_OUTPUT_HEX=y
-CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/ek_ra6m5/doc/index.rst b/boards/renesas/ek_ra6m5/doc/index.rst
index 5ab8b3bc49d..4d3691ee6f9 100644
--- a/boards/renesas/ek_ra6m5/doc/index.rst
+++ b/boards/renesas/ek_ra6m5/doc/index.rst
@@ -1,7 +1,4 @@
-.. _ek_ra6m5:
-
-RA6M5 Evaluation Kit
-####################
+.. zephyr:board:: ek_ra6m5
 
 Overview
 ********
@@ -20,7 +17,7 @@ The key features of the EK-RA6M5 board are categorized in three groups as follow
 - MCU current measurement points for precision current consumption measurement
 - Multiple clock sources - RA6M5 MCU oscillator and sub-clock oscillator crystals,
   providing precision 24.000 MHz and 32,768 Hz reference clock.
-  Additional low precision clocks are avaialbe internal to the RA6M5 MCU
+  Additional low precision clocks are available internal to the RA6M5 MCU
 
 **System Control and Ecosystem Access**
 
@@ -62,15 +59,9 @@ The key features of the EK-RA6M5 board are categorized in three groups as follow
 - 64 Mb (512 Mb) External Octo-SPI Flash
 - CAN (3-pin header)
 
-.. figure:: ek_ra6m5.webp
-	:align: center
-	:alt: RA6M5 Evaluation Kit
-
-	EK-RA6M5 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
-
 Hardware
 ********
-Detailed hardware feature for the RA6M5 MCU group can be found at `RA6M5 Group User's Manual Hardware`_
+Detailed hardware features for the RA6M5 MCU group can be found at `RA6M5 Group User's Manual Hardware`_
 
 .. figure:: ra6m5_block_diagram.webp
 	:width: 442px
@@ -79,46 +70,18 @@ Detailed hardware feature for the RA6M5 MCU group can be found at `RA6M5 Group U
 
 	RA6M5 Block diagram (Credit: Renesas Electronics Corporation)
 
-Detailed hardware feature for the EK-RA6M5 MCU can be found at `EK-RA6M5 - User's Manual`_
+Detailed hardware features for the EK-RA6M5 MCU can be found at `EK-RA6M5 - User's Manual`_
 
 Supported Features
 ==================
 
-The below features are currently supported on Zephyr OS for EK-RA6M5 board:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock control        |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| COUNTER   | on-chip    | counter              |
-+-----------+------------+----------------------+
-| USBHS     | on-chip    | udc                  |
-+-----------+------------+----------------------+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``ek_ra6m5`` board target configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
@@ -128,15 +91,15 @@ Flashing
 ========
 
 Program can be flashed to EK-RA6M5 via the on-board SEGGER J-Link debugger.
-SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
 
 To flash the program to board
 
-  1. Connect to J-Link OB via USB port to host PC
+1. Connect to J-Link OB via USB port to host PC
 
-  2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M5 - User's Manual`_
+2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA6M5 - User's Manual`_
 
-  3. Execute west command
+3. Execute west command
 
 	.. code-block:: console
 
diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi b/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi
index 709f6168898..b279f0540ad 100644
--- a/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi
+++ b/boards/renesas/ek_ra6m5/ek_ra6m5-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -46,6 +46,14 @@
 		};
 	};
 
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
+			renesas,analog-enable;
+		};
+	};
+
 	pwm1_default: pwm1_default {
 		group1 {
 			/* GTIOC1A GTIOC1B */
@@ -53,4 +61,12 @@
 				<RA_PSEL(RA_PSEL_GPT1, 4, 6)>;
 		};
 	};
+
+	usbfs_default: usbfs_default {
+		group1 {
+			/* USB_VBUS */
+			psels = <RA_PSEL(RA_PSEL_USBFS, 11, 1)>;
+			drive-strength = "high";
+		};
+	};
 };
diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.dts b/boards/renesas/ek_ra6m5/ek_ra6m5.dts
index 9f5d1a5c276..47cfc8fcb48 100644
--- a/boards/renesas/ek_ra6m5/ek_ra6m5.dts
+++ b/boards/renesas/ek_ra6m5/ek_ra6m5.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -22,6 +22,7 @@
 		zephyr,flash = &flash0;
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
+		zephyr,entropy = &trng;
 	};
 
 	leds {
@@ -58,6 +59,7 @@
 		led0 = &led1;
 		sw0 = &button0;
 		sw1 = &button1;
+		watchdog0 = &wdt;
 	};
 };
 
@@ -110,6 +112,19 @@
 	status = "okay";
 };
 
+&pll2 {
+	clocks = <&xtal>;
+	div = <2>;
+	mul = <20 0>;
+	status = "okay";
+};
+
+&uclk {
+	clocks = <&pll2>;
+	div = <5>;
+	status = "okay";
+};
+
 &usbhs {
 	pinctrl-0 = <&usbhs_default>;
 	pinctrl-names = "default";
@@ -130,6 +145,12 @@
 	pinctrl-names = "default";
 };
 
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &port_irq9 {
 	interrupts = <41 12>;
 	status = "okay";
@@ -160,3 +181,17 @@
 		};
 	};
 };
+
+&trng {
+	status = "okay";
+};
+
+&usbfs {
+	pinctrl-0 = <&usbfs_default>;
+	pinctrl-names = "default";
+	maximum-speed = "full-speed";
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5.yaml b/boards/renesas/ek_ra6m5/ek_ra6m5.yaml
index 2f65bfb229d..c3d21e8c3d5 100644
--- a/boards/renesas/ek_ra6m5/ek_ra6m5.yaml
+++ b/boards/renesas/ek_ra6m5/ek_ra6m5.yaml
@@ -9,3 +9,6 @@ toolchain:
   - gnuarmemb
 supported:
   - gpio
+  - usbd
+  - watchdog
+vendor: renesas
diff --git a/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig b/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig
index 6a9a032666e..35ed0307b9a 100644
--- a/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig
+++ b/boards/renesas/ek_ra6m5/ek_ra6m5_defconfig
@@ -1,14 +1,9 @@
 # Copyright (c) 2024 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
-
 # Enable GPIO
 CONFIG_GPIO=y
 
-CONFIG_BUILD_OUTPUT_HEX=y
-CONFIG_CLOCK_CONTROL=y
-
 # Enable Console
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/renesas/ek_ra8d1/Kconfig.defconfig b/boards/renesas/ek_ra8d1/Kconfig.defconfig
index db92a2bd461..0c5143bf597 100644
--- a/boards/renesas/ek_ra8d1/Kconfig.defconfig
+++ b/boards/renesas/ek_ra8d1/Kconfig.defconfig
@@ -1,4 +1,4 @@
-# Copyright (c) 2024 Renesas Electronics Corporation
+# Copyright (c) 2024-2025 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 if BOARD_EK_RA8D1
@@ -10,11 +10,21 @@ config NET_L2_ETHERNET
 
 endif # NETWORKING
 
-if SHIELD_RTKMIPILCDB00000BE
+if DISPLAY
+
+if SHIELD_RTKMIPILCDB00000BE || SHIELD_RTK7EKA6M3B00001BU
 
 config MEMC
 	default y
 
+config RENESAS_RA_GLCDC_FRAME_BUFFER_SECTION
+	default ".sdram"
+	depends on RENESAS_RA_GLCDC
+
+endif # SHIELD_RTKMIPILCDB00000BE || SHIELD_RTK7EKA6M3B00001BU
+
+endif # DISPLAY
+
 if LVGL
 
 config LV_Z_VDB_CUSTOM_SECTION
@@ -22,6 +32,4 @@ config LV_Z_VDB_CUSTOM_SECTION
 
 endif # LVGL
 
-endif # SHIELD_RTKMIPILCDB00000BE
-
 endif # BOARD_EK_RA8D1
diff --git a/boards/renesas/ek_ra8d1/doc/index.rst b/boards/renesas/ek_ra8d1/doc/index.rst
index 183ed37acbd..027f08a261d 100644
--- a/boards/renesas/ek_ra8d1/doc/index.rst
+++ b/boards/renesas/ek_ra8d1/doc/index.rst
@@ -1,7 +1,4 @@
-.. _ek_ra8d1:
-
-RA8D1 Evaluation Kit
-####################
+.. zephyr:board:: ek_ra8d1
 
 Overview
 ********
@@ -20,7 +17,7 @@ The key features of the EK-RA8D1 board are categorized in three groups as follow
 - MCU current measurement points for precision current consumption measurement
 - Multiple clock sources - RA8D1 MCU oscillator and sub-clock oscillator crystals,
   providing precision 20.000MHz and 32,768 Hz refeence clocks.
-  Additional low precision clocks are avaialbe internal to the RA8D1 MCU
+  Additional low precision clocks are available internal to the RA8D1 MCU
 
 **System Control and Ecosystem Access**
 
@@ -61,15 +58,9 @@ The key features of the EK-RA8D1 board are categorized in three groups as follow
 - 512 Mb (64 MB) External Octo-SPI Flash (present in the MCU Native Pin Access area of the EK-RA8D1 board)
 - CAN FD (3-pin header)
 
-.. figure:: ek_ra8d1.jpg
-	:align: center
-	:alt: RA8D1 Evaluation Kit
-
-	EK-RA8D1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
-
 Hardware
 ********
-Detail Hardware feature for the RA8D1 MCU group can be found at `RA8D1 Group User's Manual Hardware`_
+Detailed Hardware features for the RA8D1 MCU group can be found at `RA8D1 Group User's Manual Hardware`_
 
 .. figure:: ra8d1_block_diagram.png
 	:width: 442px
@@ -78,77 +69,57 @@ Detail Hardware feature for the RA8D1 MCU group can be found at `RA8D1 Group Use
 
 	RA8D1 Block diagram (Credit: Renesas Electronics Corporation)
 
-Detail Hardware feature for the EK-RA8D1 MCU can be found at `EK-RA8D1 - User's Manual`_
+Detailed Hardware features for the EK-RA8D1 MCU can be found at `EK-RA8D1 - User's Manual`_
 
 Supported Features
 ==================
 
-The below features are currently supported on Zephyr OS for EK-RA8D1 board:
-
-+--------------+------------+-----------------------------------+
-| Interface    | Controller | Driver/Component                  |
-+==============+============+===================================+
-| GPIO         | on-chip    | gpio                              |
-+--------------+------------+-----------------------------------+
-| MPU          | on-chip    | arch/arm                          |
-+--------------+------------+-----------------------------------+
-| NVIC         | on-chip    | arch/arm                          |
-+--------------+------------+-----------------------------------+
-| UART         | on-chip    | serial                            |
-+--------------+------------+-----------------------------------+
-| CLOCK        | on-chip    | clock control                     |
-+--------------+------------+-----------------------------------+
-| ENTROPY      | on-chip    | entropy                           |
-+--------------+------------+-----------------------------------+
-| SPI          | on-chip    | spi                               |
-+--------------+------------+-----------------------------------+
-| FLASH        | on-chip    | flash                             |
-+--------------+------------+-----------------------------------+
-| PWM          | on-chip    | pwm                               |
-+--------------+------------+-----------------------------------+
-| COUNTER      | on-chip    | counter                           |
-+--------------+------------+-----------------------------------+
-| CAN          | on-chip    | canfd                             |
-+--------------+------------+-----------------------------------+
-| I2C          | on-chip    | i2c                               |
-+--------------+------------+-----------------------------------+
-| USBHS        | on-chip    | udc                               |
-+--------------+------------+-----------------------------------+
-| DISPLAY      | on-chip    | LCDIF; MIPI-DSI. Tested with      |
-|              |            | :ref:`rtkmipilcdb00000be` shields |
-+--------------+------------+-----------------------------------+
-| ETHERNET     | on-chip    | ethernet                          |
-+--------------+------------+-----------------------------------+
-| ADC          | on-chip    | adc                               |
-+--------------+------------+-----------------------------------+
-| SDHC         | on-chip    | sdhc                              |
-+--------------+------------+-----------------------------------+
-
-**Note:**
-
-- For using Ethernet on RA8D1 board please set switch SW1 as following configuration:
-
-+-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
-| SW1-1 PMOD1 | SW1-2 TRACE | SW1-3 CAMERA | SW1-4 ETHA | SW1-5 ETHB | SW1-6 GLCD | SW1-7 SDRAM | SW1-8 I3C |
-+-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
-|     OFF     |      OFF    |      OFF     |     OFF    |     ON     |      OFF   |      OFF    |     OFF   |
-+-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
-
-- For using SDHC channel 1 on RA8D1 board please set switch SW1 as following configuration:
-
-+-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
-| SW1-1 PMOD1 | SW1-2 TRACE | SW1-3 CAMERA | SW1-4 ETHA | SW1-5 ETHB | SW1-6 GLCD | SW1-7 SDRAM | SW1-8 I3C |
-+-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
-|     OFF     |      OFF    |      OFF     |     OFF    |     OFF    |      OFF   |      OFF    |     OFF   |
-+-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
-
-**CAUTION:** Do not enable SW1-4 and SW1-5 together
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   - For using Ethernet on RA8D1 board please set switch SW1 as following configuration:
+
+     +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
+     | SW1-1 PMOD1 | SW1-2 TRACE | SW1-3 CAMERA | SW1-4 ETHA | SW1-5 ETHB | SW1-6 GLCD | SW1-7 SDRAM | SW1-8 I3C |
+     +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
+     |     OFF     |      OFF    |      OFF     |     OFF    |     ON     |      OFF   |      OFF    |     OFF   |
+     +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
+
+   - For using SDHC channel 1 on RA8D1 board please set switch SW1 as following configuration:
+
+     +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
+     | SW1-1 PMOD1 | SW1-2 TRACE | SW1-3 CAMERA | SW1-4 ETHA | SW1-5 ETHB | SW1-6 GLCD | SW1-7 SDRAM | SW1-8 I3C |
+     +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
+     |     OFF     |      OFF    |      OFF     |     OFF    |     OFF    |      OFF   |      OFF    |     OFF   |
+     +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
+
+   - For using MIPI Graphics Expansion Port (J58) on RA8D1 board please set switch SW1 as following configuration:
+
+     +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
+     | SW1-1 PMOD1 | SW1-2 TRACE | SW1-3 CAMERA | SW1-4 ETHA | SW1-5 ETHB | SW1-6 GLCD | SW1-7 SDRAM | SW1-8 I3C |
+     +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
+     |     OFF     |     OFF     |      OFF     |     OFF    |     OFF    |     ON     |     ON      |    OFF    |
+     +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
+
+   - For using the Parallel Graphics Expansion Port (J57) with the Graphics Expansion Board supplied as part of the kit,
+     please set switch SW1 as following configuration:
+
+     +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
+     | SW1-1 PMOD1 | SW1-2 TRACE | SW1-3 CAMERA | SW1-4 ETHA | SW1-5 ETHB | SW1-6 GLCD | SW1-7 SDRAM | SW1-8 I3C |
+     +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
+     |     OFF     |     OFF     |      OFF     |     OFF    |     OFF    |     ON     |     ON      |    OFF    |
+     +-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
+
+.. warning::
+
+   Do not enable SW1-4 and SW1-5 together
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``ek_ra8d1`` board configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
@@ -161,15 +132,15 @@ Flashing
 ========
 
 Program can be flashed to EK-RA8D1 via the on-board SEGGER J-Link debugger.
-SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
 
 To flash the program to board
 
-  1. Connect to J-Link OB via USB port to host PC
+1. Connect to J-Link OB via USB port to host PC
 
-  2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA8D1 - User's Manual`_
+2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA8D1 - User's Manual`_
 
-  3. Execute west command
+3. Execute west command
 
 	.. code-block:: console
 
diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi b/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi
index b4d3168b903..ba342a63572 100644
--- a/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi
+++ b/boards/renesas/ek_ra8d1/ek_ra8d1-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -16,7 +16,16 @@
 		};
 	};
 
-	spi0_default: spi0_default {
+	sci4_default: sci4_default {
+		group1 {
+			/* sda scl */
+			psels = <RA_PSEL(RA_PSEL_SCI_4, 4, 15)>,<RA_PSEL(RA_PSEL_SCI_4, 4, 14)>;
+			drive-strength = "medium";
+			drive-open-drain;
+		};
+	};
+
+	spi1_default: spi1_default {
 		group1 {
 			/* MISO MOSI RSPCK SSL */
 			psels = <RA_PSEL(RA_PSEL_SPI, 4, 10)>,
@@ -86,6 +95,14 @@
 		};
 	};
 
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
+			renesas,analog-enable;
+		};
+	};
+
 	sdram_default: sdram_default{
 		group1 {
 			/* SDRAM_DQM1 */
@@ -179,71 +196,6 @@
 		};
 	};
 
-	glcdc_default: glcdc_default {
-		group1 {
-			/* LCDC_TCON0 */
-			psels = <RA_PSEL(RA_PSEL_GLCDC, 8, 5)>,
-			/* LCDC_TCON1 */
-			<RA_PSEL(RA_PSEL_GLCDC, 8, 7)>,
-			/* LCDC_TCON2 */
-			<RA_PSEL(RA_PSEL_GLCDC, 5, 13)>,
-			/* LCDC_TCON3 */
-			<RA_PSEL(RA_PSEL_GLCDC, 5, 15)>,
-			/* LCDC_DATA00 */
-			<RA_PSEL(RA_PSEL_GLCDC, 9, 14)>,
-			/* LCDC_DATA01 */
-			<RA_PSEL(RA_PSEL_GLCDC, 9, 15)>,
-			/* LCDC_DATA02 */
-			<RA_PSEL(RA_PSEL_GLCDC, 9, 10)>,
-			/* LCDC_DATA03 */
-			<RA_PSEL(RA_PSEL_GLCDC, 9, 11)>,
-			/* LCDC_DATA04 */
-			<RA_PSEL(RA_PSEL_GLCDC, 9, 12)>,
-			/* LCDC_DATA05 */
-			<RA_PSEL(RA_PSEL_GLCDC, 9, 13)>,
-			/* LCDC_DATA06 */
-			<RA_PSEL(RA_PSEL_GLCDC, 9, 4)>,
-			/* LCDC_DATA07 */
-			<RA_PSEL(RA_PSEL_GLCDC, 9, 3)>,
-			/* LCDC_DATA08 */
-			<RA_PSEL(RA_PSEL_GLCDC, 9, 2)>,
-			/* LCDC_DATA09 */
-			<RA_PSEL(RA_PSEL_GLCDC, 2, 7)>,
-			/* LCDC_DATA10 */
-			<RA_PSEL(RA_PSEL_GLCDC, 7, 11)>,
-			/* LCDC_DATA11 */
-			<RA_PSEL(RA_PSEL_GLCDC, 7, 12)>,
-			/* LCDC_DATA12 */
-			<RA_PSEL(RA_PSEL_GLCDC, 7, 13)>,
-			/* LCDC_DATA13 */
-			<RA_PSEL(RA_PSEL_GLCDC, 7, 14)>,
-			/* LCDC_DATA14 */
-			<RA_PSEL(RA_PSEL_GLCDC, 7, 15)>,
-			/* LCDC_DATA15 */
-			<RA_PSEL(RA_PSEL_GLCDC, 11, 7)>,
-			/* LCDC_DATA16 */
-			<RA_PSEL(RA_PSEL_GLCDC, 11, 6)>,
-			/* LCDC_DATA17 */
-			<RA_PSEL(RA_PSEL_GLCDC, 11, 5)>,
-			/* LCDC_DATA18 */
-			<RA_PSEL(RA_PSEL_GLCDC, 11, 1)>,
-			/* LCDC_DATA19 */
-			<RA_PSEL(RA_PSEL_GLCDC, 11, 4)>,
-			/* LCDC_DATA20 */
-			<RA_PSEL(RA_PSEL_GLCDC, 11, 3)>,
-			/* LCDC_DATA21 */
-			<RA_PSEL(RA_PSEL_GLCDC, 11, 2)>,
-			/* LCDC_DATA22 */
-			<RA_PSEL(RA_PSEL_GLCDC, 11, 0)>,
-			/* LCDC_DATA23 */
-			<RA_PSEL(RA_PSEL_GLCDC, 7, 7)>,
-			/* LCDC_CLK */
-			<RA_PSEL(RA_PSEL_GLCDC, 8, 6)>,
-			/* LCDC_EXTCLK */
-			<RA_PSEL(RA_PSEL_GLCDC, 5, 14)>;
-		};
-	};
-
 	/* NOTE: pins conflict with ether_default */
 	sdhc1_default: sdhc1_default {
 		group1 {
@@ -261,4 +213,61 @@
 			drive-strength = "highspeed-high";
 		};
 	};
+
+	usbfs_default: usbfs_default {
+		group1 {
+			/* USBP USBN */
+			psels = <RA_PSEL(RA_PSEL_USBFS, 8, 15)>,
+				<RA_PSEL(RA_PSEL_USBFS, 8, 14)>,
+				<RA_PSEL(RA_PSEL_USBFS, 4, 7)>;
+			drive-strength = "high";
+		};
+	};
+
+	/omit-if-no-ref/ acmphs_ivref0: acmphs_ivref0 {
+		group1 {
+			/* IVREF0 */
+			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 1)>;
+			renesas,analog-enable;
+		};
+	};
+
+	/omit-if-no-ref/ acmphs_ivref1: acmphs_ivref1 {
+		group1 {
+			/* IVREF1 */
+			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 3)>;
+			renesas,analog-enable;
+		};
+	};
+
+	/omit-if-no-ref/ acmphs0_ivcmp0: acmphs0_ivcmp0 {
+		group1 {
+			/* CH0 IVCMP0 */
+			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 10)>;
+			renesas,analog-enable;
+		};
+	};
+
+	/omit-if-no-ref/ acmphs0_ivcmp2: acmphs0_ivcmp2 {
+		group1 {
+			/* CH0 IVCMP2 */
+			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 4)>;
+			renesas,analog-enable;
+		};
+	};
+
+	/omit-if-no-ref/ acmphs0_ivcmp3: acmphs0_ivcmp3 {
+		group1 {
+			/* CH0 IVCMP3 */
+			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 6)>;
+			renesas,analog-enable;
+		};
+	};
+
+	/omit-if-no-ref/ acmphs_vcout: acmphs_vcout {
+		group1 {
+			/* VCOUT */
+			psels = <RA_PSEL(RA_PSEL_ACMPHS_VCOUT, 2, 8)>;
+		};
+	};
 };
diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.dts b/boards/renesas/ek_ra8d1/ek_ra8d1.dts
index a89c31f0940..9fb7fec4dd1 100644
--- a/boards/renesas/ek_ra8d1/ek_ra8d1.dts
+++ b/boards/renesas/ek_ra8d1/ek_ra8d1.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -82,6 +82,7 @@
 		sw0 = &button0;
 		sw1 = &button1;
 		mipi-dsi = &mipi_dsi;
+		watchdog0 = &wdt;
 	};
 };
 
@@ -103,6 +104,8 @@
 	};
 
 	pllq {
+		div = <4>;
+		freq = <DT_FREQ_M(240)>;
 		status = "okay";
 	};
 
@@ -111,7 +114,6 @@
 	};
 };
 
-
 &sciclk {
 	clocks = <&pllp>;
 	div = <4>;
@@ -119,8 +121,8 @@
 };
 
 &canfdclk {
-	clocks = <&pll>;
-	div = <5>;
+	clocks = <&pllp>;
+	div = <6>;
 	status = "okay";
 };
 
@@ -130,6 +132,12 @@
 	status = "okay";
 };
 
+&uclk {
+	clocks = <&pllq>;
+	div = <5>;
+	status = "okay";
+};
+
 &ioport0 {
 	status = "okay";
 };
@@ -154,12 +162,6 @@
 	status = "okay";
 };
 
-&sci0 {
-	/* sci0 and spi0 cannot be enabled together */
-	pinctrl-0 = <&sci9_default>;
-	pinctrl-names = "default";
-};
-
 &sci9 {
 	pinctrl-0 = <&sci9_default>;
 	pinctrl-names = "default";
@@ -170,12 +172,23 @@
 	};
 };
 
+&sci4 {
+	pinctrl-0 = <&sci4_default>;
+	pinctrl-names = "default";
+
+	i2c4: i2c {
+		sda-output-delay = <300>;
+		noise-filter-clock-select = <1>;
+		bit-rate-modulation;
+	};
+};
+
 &trng {
 	status = "okay";
 };
 
-&spi0 {
-	pinctrl-0 = <&spi0_default>;
+&spi1 {
+	pinctrl-0 = <&spi1_default>;
 	pinctrl-names = "default";
 	status = "okay";
 };
@@ -257,6 +270,12 @@
 	pinctrl-names = "default";
 };
 
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &port_irq12 {
 	interrupts = <88 12>;
 	status = "okay";
@@ -290,13 +309,36 @@
 	};
 };
 
-zephyr_lcdif: &lcdif {
-	pinctrl-0 = <&glcdc_default>;
-	pinctrl-names = "default";
-};
+zephyr_lcdif: &lcdif {};
 
 zephyr_mipi_dsi: &mipi_dsi {};
 
-renesas_mipi_i2c: &iic1{};
+renesas_mipi_i2c: &iic1 {};
 
 pmod_sd_shield: &sdhc1 {};
+
+&usbfs {
+	pinctrl-0 = <&usbfs_default>;
+	pinctrl-names = "default";
+	maximum-speed = "full-speed";
+};
+
+&wdt {
+	status = "okay";
+};
+
+&ulpt0 {
+	status = "okay";
+
+	timer {
+		status = "okay";
+	};
+};
+
+&ulpt1 {
+	status = "okay";
+
+	timer {
+		status = "okay";
+	};
+};
diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1.yaml b/boards/renesas/ek_ra8d1/ek_ra8d1.yaml
index 2432f8ed657..15bb3fca1d6 100644
--- a/boards/renesas/ek_ra8d1/ek_ra8d1.yaml
+++ b/boards/renesas/ek_ra8d1/ek_ra8d1.yaml
@@ -10,3 +10,7 @@ toolchain:
 supported:
   - gpio
   - uart
+  - watchdog
+  - usbd
+  - display
+vendor: renesas
diff --git a/boards/renesas/ek_ra8d1/ek_ra8d1_defconfig b/boards/renesas/ek_ra8d1/ek_ra8d1_defconfig
index 1f67b94e7c1..35ed0307b9a 100644
--- a/boards/renesas/ek_ra8d1/ek_ra8d1_defconfig
+++ b/boards/renesas/ek_ra8d1/ek_ra8d1_defconfig
@@ -1,8 +1,6 @@
 # Copyright (c) 2024 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000
-
 # Enable GPIO
 CONFIG_GPIO=y
 
@@ -11,6 +9,3 @@ CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
 CONFIG_CONSOLE=y
-CONFIG_CLOCK_CONTROL=y
-
-CONFIG_BUILD_OUTPUT_HEX=y
diff --git a/boards/renesas/ek_ra8m1/doc/index.rst b/boards/renesas/ek_ra8m1/doc/index.rst
index 55890ac3fcc..c5553bc608f 100644
--- a/boards/renesas/ek_ra8m1/doc/index.rst
+++ b/boards/renesas/ek_ra8m1/doc/index.rst
@@ -1,7 +1,4 @@
-.. _ek_ra8m1:
-
-RA8M1 Evaluation Kit
-####################
+.. zephyr:board:: ek_ra8m1
 
 Overview
 ********
@@ -20,7 +17,7 @@ The key features of the EK-RA8M1 board are categorized in three groups as follow
 - MCU current measurement points for precision current consumption measurement
 - Multiple clock sources - RA8M1 MCU oscillator and sub-clock oscillator crystals,
   providing precision 20.000MHz and 32,768 Hz refeence clocks.
-  Additional low precision clocks are avaialbe internal to the RA8M1 MCU
+  Additional low precision clocks are available internal to the RA8M1 MCU
 
 **System Control and Ecosystem Access**
 
@@ -61,15 +58,9 @@ The key features of the EK-RA8M1 board are categorized in three groups as follow
 - 512 Mb (64 MB) External Octo-SPI Flash (present in the MCU Native Pin Access area of the EK-RA8M1 board)
 - CAN FD (3-pin header)
 
-.. figure:: ek_ra8m1.jpg
-	:align: center
-	:alt: RA8M1 Evaluation Kit
-
-	EK-RA8M1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
-
 Hardware
 ********
-Detail Hardware feature for the RA8M1 MCU group can be found at `RA8M1 Group User's Manual Hardware`_
+Detailed Hardware features for the RA8M1 MCU group can be found at `RA8M1 Group User's Manual Hardware`_
 
 .. figure:: ra8m1_block_diagram.jpg
 	:width: 442px
@@ -78,59 +69,23 @@ Detail Hardware feature for the RA8M1 MCU group can be found at `RA8M1 Group Use
 
 	RA8M1 Block diagram (Credit: Renesas Electronics Corporation)
 
-Detail Hardware feature for the EK-RA8M1 MCU can be found at `EK-RA8M1 - User's Manual`_
+Detailed Hardware features for the EK-RA8M1 MCU can be found at `EK-RA8M1 - User's Manual`_
 
 Supported Features
 ==================
 
-The below features are currently supported on Zephyr OS for EK-RA8M1 board:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock control        |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| ENTROPY   | on-chip    | entropy              |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| COUNTER   | on-chip    | counter              |
-+-----------+------------+----------------------+
-| CAN       | on-chip    | canfd                |
-+-----------+------------+----------------------+
-| USBHS     | on-chip    | udc                  |
-+-----------+------------+----------------------+
-| ETHERNET  | on-chip    | ethernet             |
-+-----------+------------+----------------------+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| SDHC      | on-chip    | sdhc                 |
-+-----------+------------+----------------------+
-
-**Note:**
-
-- For using Ethernet module on EK-RA8M1, remove jumper J61 to enable Ethernet B
-- For using SDHC driver on EK-RA8M1, remove jumper J61 to use with channel 0
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   - For using Ethernet module on EK-RA8M1, remove jumper J61 to enable Ethernet B
+   - For using SDHC driver on EK-RA8M1, remove jumper J61 to use with channel 0
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``ek_ra8m1`` board configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
@@ -143,15 +98,15 @@ Flashing
 ========
 
 Program can be flashed to EK-RA8M1 via the on-board SEGGER J-Link debugger.
-SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
 
 To flash the program to board
 
-  1. Connect to J-Link OB via USB port to host PC
+1. Connect to J-Link OB via USB port to host PC
 
-  2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA8M1 - User's Manual`_
+2. Make sure J-Link OB jumper is in default configuration as describe in `EK-RA8M1 - User's Manual`_
 
-  3. Execute west command
+3. Execute west command
 
 	.. code-block:: console
 
diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi b/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi
index f3c3ec3ebd9..e8a26e09905 100644
--- a/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi
+++ b/boards/renesas/ek_ra8m1/ek_ra8m1-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -16,6 +16,15 @@
 		};
 	};
 
+	sci1_default: sci1_default {
+		group1 {
+			/* sda scl */
+			psels = <RA_PSEL(RA_PSEL_SCI_1, 7, 7)>,<RA_PSEL(RA_PSEL_SCI_1, 7, 6)>;
+			drive-strength = "medium";
+			drive-open-drain;
+		};
+	};
+
 	sci2_default: sci2_default {
 		group1 {
 			/* tx */
@@ -68,6 +77,14 @@
 		};
 	};
 
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
+			renesas,analog-enable;
+		};
+	};
+
 	spi1_default: spi1_default {
 		group1 {
 			/* MISO MOSI RSPCK SSL*/
@@ -138,4 +155,61 @@
 			drive-strength = "highspeed-high";
 		};
 	};
+
+	usbfs_default: usbfs_default {
+		group1 {
+			/* USBP USBN */
+			psels = <RA_PSEL(RA_PSEL_USBFS, 8, 15)>,
+				<RA_PSEL(RA_PSEL_USBFS, 8, 14)>,
+				<RA_PSEL(RA_PSEL_USBFS, 4, 7)>;
+			drive-strength = "high";
+		};
+	};
+
+	/omit-if-no-ref/ acmphs_ivref0: acmphs_ivref0 {
+		group1 {
+			/* IVREF0 */
+			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 1)>;
+			renesas,analog-enable;
+		};
+	};
+
+	/omit-if-no-ref/ acmphs_ivref1: acmphs_ivref1 {
+		group1 {
+			/* IVREF1 */
+			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 3)>;
+			renesas,analog-enable;
+		};
+	};
+
+	/omit-if-no-ref/ acmphs0_ivcmp0: acmphs0_ivcmp0 {
+		group1 {
+			/* CH0 IVCMP0 */
+			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 10)>;
+			renesas,analog-enable;
+		};
+	};
+
+	/omit-if-no-ref/ acmphs0_ivcmp2: acmphs0_ivcmp2 {
+		group1 {
+			/* CH0 IVCMP2 */
+			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 4)>;
+			renesas,analog-enable;
+		};
+	};
+
+	/omit-if-no-ref/ acmphs0_ivcmp3: acmphs0_ivcmp3 {
+		group1 {
+			/* CH0 IVCMP3 */
+			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 6)>;
+			renesas,analog-enable;
+		};
+	};
+
+	/omit-if-no-ref/ acmphs_vcout: acmphs_vcout {
+		group1 {
+			/* VCOUT */
+			psels = <RA_PSEL(RA_PSEL_ACMPHS_VCOUT, 2, 8)>;
+		};
+	};
 };
diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.dts b/boards/renesas/ek_ra8m1/ek_ra8m1.dts
index 96e952cd099..e1c08487718 100644
--- a/boards/renesas/ek_ra8m1/ek_ra8m1.dts
+++ b/boards/renesas/ek_ra8m1/ek_ra8m1.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -112,6 +112,7 @@
 		led0 = &led1;
 		sw0 = &button0;
 		sw1 = &button1;
+		watchdog0 = &wdt;
 	};
 
 	transceiver0: can-phy0 {
@@ -140,6 +141,8 @@
 	};
 
 	pllq {
+		div = <4>;
+		freq = <DT_FREQ_M(240)>;
 		status = "okay";
 	};
 
@@ -156,7 +159,13 @@
 };
 
 &canfdclk {
-	clocks = <&pll>;
+	clocks = <&pllp>;
+	div = <6>;
+	status = "okay";
+};
+
+&uclk {
+	clocks = <&pllq>;
 	div = <5>;
 	status = "okay";
 };
@@ -211,6 +220,17 @@
 	};
 };
 
+&sci1 {
+	pinctrl-0 = <&sci1_default>;
+	pinctrl-names = "default";
+
+	i2c1: i2c {
+		sda-output-delay = <300>;
+		noise-filter-clock-select = <1>;
+		bit-rate-modulation;
+	};
+};
+
 &sci2 {
 	pinctrl-0 = <&sci2_default>;
 	pinctrl-names = "default";
@@ -258,6 +278,12 @@ mikrobus_serial: &uart3 {};
 	average-count = <4>;
 };
 
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &trng {
 	status = "okay";
 };
@@ -349,3 +375,29 @@ pmod_header: &pmod1_header {};
 };
 
 pmod_sd_shield: &sdhc0 {};
+
+&usbfs {
+	pinctrl-0 = <&usbfs_default>;
+	pinctrl-names = "default";
+	maximum-speed = "full-speed";
+};
+
+&wdt {
+	status = "okay";
+};
+
+&ulpt0 {
+	status = "okay";
+
+	timer {
+		status = "okay";
+	};
+};
+
+&ulpt1 {
+	status = "okay";
+
+	timer {
+		status = "okay";
+	};
+};
diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1.yaml b/boards/renesas/ek_ra8m1/ek_ra8m1.yaml
index 28c7aa4296b..97d74ff416a 100644
--- a/boards/renesas/ek_ra8m1/ek_ra8m1.yaml
+++ b/boards/renesas/ek_ra8m1/ek_ra8m1.yaml
@@ -10,3 +10,6 @@ toolchain:
 supported:
   - gpio
   - uart
+  - watchdog
+  - usbd
+vendor: renesas
diff --git a/boards/renesas/ek_ra8m1/ek_ra8m1_defconfig b/boards/renesas/ek_ra8m1/ek_ra8m1_defconfig
index d20f5032468..35ed0307b9a 100644
--- a/boards/renesas/ek_ra8m1/ek_ra8m1_defconfig
+++ b/boards/renesas/ek_ra8m1/ek_ra8m1_defconfig
@@ -1,8 +1,6 @@
 # Copyright (c) 2024 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000
-
 # Enable GPIO
 CONFIG_GPIO=y
 
@@ -11,6 +9,3 @@ CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
 CONFIG_CONSOLE=y
-
-CONFIG_BUILD_OUTPUT_HEX=y
-CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/fpb_ra4e1/Kconfig.fpb_ra4e1 b/boards/renesas/fpb_ra4e1/Kconfig.fpb_ra4e1
new file mode 100644
index 00000000000..0f57b0aedb9
--- /dev/null
+++ b/boards/renesas/fpb_ra4e1/Kconfig.fpb_ra4e1
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_FPB_RA4E1
+	select SOC_R7FA4E10D2CFM
diff --git a/boards/renesas/fpb_ra4e1/board.cmake b/boards/renesas/fpb_ra4e1/board.cmake
new file mode 100644
index 00000000000..590f06a5743
--- /dev/null
+++ b/boards/renesas/fpb_ra4e1/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7FA4E10D")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/fpb_ra4e1/board.yml b/boards/renesas/fpb_ra4e1/board.yml
new file mode 100644
index 00000000000..49c5b77196d
--- /dev/null
+++ b/boards/renesas/fpb_ra4e1/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: fpb_ra4e1
+  full_name: RA4E1 Fast Prototyping Board
+  vendor: renesas
+  socs:
+  - name: r7fa4e10d2cfm
diff --git a/boards/renesas/fpb_ra4e1/doc/fpb_ra4e1.webp b/boards/renesas/fpb_ra4e1/doc/fpb_ra4e1.webp
new file mode 100644
index 00000000000..3a094861385
Binary files /dev/null and b/boards/renesas/fpb_ra4e1/doc/fpb_ra4e1.webp differ
diff --git a/boards/renesas/fpb_ra4e1/doc/index.rst b/boards/renesas/fpb_ra4e1/doc/index.rst
new file mode 100644
index 00000000000..eed107b32a6
--- /dev/null
+++ b/boards/renesas/fpb_ra4e1/doc/index.rst
@@ -0,0 +1,127 @@
+.. zephyr:board:: fpb_ra4e1
+
+Overview
+********
+
+The Renesas RA4E1 Group delivers up to 100 MHz of CPU performance using an Arm® Cortex®-M33 core
+with 512 KB code flash memory, 8 KB of data flash memory, and 128 KB of SRAM. RA4E1 MCUs
+offer leading-performance. The RA4E1 Group offers a wide set of peripherals, including
+USB 2.0 Full-Speed, Quad SPI, and advanced analog.
+
+The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to
+100 MHz with the following features:
+
+**MCU Native Pin Access**
+
+- R7FA4E10D2CFM MCU (referred to as RA MCU)
+- 100 MHz, Arm® Cortex®-M33 core
+- 512 KB Code Flash, 8 KB Data Flash, 128 KB SRAM
+- 64 pins, LQFP package
+- Native pin access through 2 x 50-pin male headers (not fitted)
+- MCU current measurement point for precision current consumption measurement
+- Multiple clock sources - Low-precision (~1%) clocks are available internal to the RA MCU.
+  RA MCU oscillator and sub-clock oscillator crystals, providing precision 24.000 MHz (not fitted)
+  and 32,768 Hz reference clocks are also available
+
+**System Control and Ecosystem Access**
+
+- Two 5 V input sources
+
+   - USB (Debug, Full Speed)
+   - External power supply (using 2-pin header) (not fitted)
+
+- Built-in SEGGER J-Link Emulator On-Board programmer/debugger (SWD)
+
+- User LEDs and buttons
+
+   - Two User LEDs (green)
+   - Power LED (green) (not fitted) indicating availability of regulated power
+   - Debug/power LED (yellow) indicating power and the debug connection
+   -  One User button
+   - One Reset button
+
+- Two popular ecosystem expansions
+
+   - Two Digilent PmodTM (SPI, UART) connectors (not fitted)
+   - ArduinoTM (Uno R3) connectors
+
+- MCU boot configuration jumper (not fitted)
+
+Hardware
+********
+
+Detailed hardware features can be found at:
+
+- RA4E1 MCU: `RA4E1 Group User's Manual Hardware`_
+- FPB-RA4E1 board: `FPB-RA4E1 - User's Manual`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``fpb_ra4e1`` board can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Flashing
+========
+
+Program can be flashed to FPB-RA4E1 via the on-board SEGGER J-Link debugger.
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
+
+To flash the program to board
+
+1. Connect to J-Link OB via USB port to host PC
+
+2. Make sure J-Link OB jumper is in default configuration as describe in `FPB-RA4E1 - User's Manual`_
+
+3. Execute west command
+
+	.. code-block:: console
+
+		west flash -r jlink
+
+Debugging
+=========
+
+You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface
+
+Once downloaded and installed, open Segger Ozone and configure the debug project
+like so:
+
+* Target Device: R7FA4E10D
+* Target Interface: SWD
+* Target Interface Speed: 4 MHz
+* Host Interface: USB
+* Program File: <path/to/your/build/zephyr.elf>
+
+**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later
+version of Segger Ozone
+
+References
+**********
+
+- `FPB-RA4E1 Website`_
+- `RA4E1 MCU group Website`_
+
+.. _FPB-RA4E1 Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/fpb-ra4e1-fast-prototyping-board-ra4e1-mcu-group
+
+.. _RA4E1 MCU group Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra4e1-100mhz-arm-cortex-m33-entry-line-balanced-low-power-consumption-optimized-feature-integration
+
+.. _FPB-RA4E1 - User's Manual:
+   https://www.renesas.com/en/document/mat/fpb-ra4e1-users-manual
+
+.. _RA4E1 Group User's Manual Hardware:
+   https://www.renesas.com/en/document/mah/ra4e1-group-users-manual-hardware
+
+.. _Segger Ozone Download:
+   https://www.segger.com/downloads/jlink#Ozone
diff --git a/boards/renesas/fpb_ra4e1/fpb_ra4e1-pinctrl.dtsi b/boards/renesas/fpb_ra4e1/fpb_ra4e1-pinctrl.dtsi
new file mode 100644
index 00000000000..5cad33f9449
--- /dev/null
+++ b/boards/renesas/fpb_ra4e1/fpb_ra4e1-pinctrl.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci0_default: sci0_default {
+		group1 {
+			/* tx rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_0, 1, 1)>,
+			<RA_PSEL(RA_PSEL_SCI_0, 1, 0)>;
+		};
+	};
+
+	iic0_default: iic0_default {
+		group1 {
+			/* SCL0 SDA0 */
+			psels = <RA_PSEL(RA_PSEL_I2C, 4, 0)>,
+			<RA_PSEL(RA_PSEL_I2C, 4, 1)>;
+			drive-strength = "medium";
+		};
+	};
+
+	spi0_default: spi0_default {
+		group1 {
+			/* MISO MOSI RSPCK SSL */
+			psels = <RA_PSEL(RA_PSEL_SPI, 1, 10)>,
+			<RA_PSEL(RA_PSEL_SPI, 1, 9)>,
+			<RA_PSEL(RA_PSEL_SPI, 1, 11)>,
+			<RA_PSEL(RA_PSEL_SPI, 3, 1)>;
+		};
+	};
+
+	adc0_default: adc0_default {
+		group1 {
+			/* input */
+			psels = <RA_PSEL(RA_PSEL_ADC, 0, 0)>;
+			renesas,analog-enable;
+		};
+	};
+
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
+			renesas,analog-enable;
+		};
+	};
+
+	pwm1_default: pwm1_default {
+		group1 {
+			/* GTIOC1A GTIOC1B */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 5)>,
+				<RA_PSEL(RA_PSEL_GPT1, 1, 4)>;
+		};
+	};
+};
diff --git a/boards/renesas/fpb_ra4e1/fpb_ra4e1.dts b/boards/renesas/fpb_ra4e1/fpb_ra4e1.dts
new file mode 100644
index 00000000000..7a8396753b8
--- /dev/null
+++ b/boards/renesas/fpb_ra4e1/fpb_ra4e1.dts
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra4/r7fa4e10d2cfm.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/adc/adc.h>
+#include "fpb_ra4e1-pinctrl.dtsi"
+
+/ {
+	model = "Renesas FPB-RA4E1";
+	compatible = "renesas,ra4e1", "renesas,ra";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash-controller = &flash1;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,entropy = &trng;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1: led1 {
+			gpios = <&ioport4 8 GPIO_ACTIVE_HIGH>;
+			label = "LED1";
+		};
+
+		led2: led2 {
+			gpios = <&ioport4 7 GPIO_ACTIVE_HIGH>;
+			label = "LED2";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		button0: s1 {
+			gpios = <&ioport2 5 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button switch 1";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	aliases {
+		led0 = &led1;
+		sw0 = &button0;
+		watchdog0 = &wdt;
+	};
+};
+
+&subclk {
+	status = "okay";
+};
+
+&pll {
+	clocks = <&hoco>;
+	div = <2>;
+	mul = <20 0>;
+	status = "okay";
+};
+
+&sci0 {
+	pinctrl-0 = <&sci0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	uart0: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
+
+&ioport0 {
+	status = "okay";
+};
+
+&ioport1 {
+	status = "okay";
+};
+
+&ioport2 {
+	status = "okay";
+};
+
+&ioport3 {
+	status = "okay";
+};
+
+&ioport4 {
+	status = "okay";
+};
+
+&spi0 {
+	pinctrl-0 = <&spi0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&iic0 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	interrupts = <91 1>, <92 1>, <93 1>, <94 1>;
+	interrupt-names = "rxi", "txi", "tei", "eri";
+	clock-frequency = <DT_FREQ_M(1)>;
+	pinctrl-0 = <&iic0_default>;
+	pinctrl-names = "default";
+};
+
+&adc0 {
+	status = "okay";
+	pinctrl-0 = <&adc0_default>;
+	pinctrl-names = "default";
+};
+
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&port_irq1 {
+	interrupts = <41 12>;
+	status = "okay";
+};
+
+&pwm1 {
+	pinctrl-0 = <&pwm1_default>;
+	pinctrl-names = "default";
+	interrupts = <63 1>, <64 1>;
+	interrupt-names = "gtioca", "overflow";
+	status = "okay";
+};
+
+&trng {
+	status = "okay";
+};
+
+&flash1 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		storage_partition: partition@0 {
+			label = "storage";
+			reg = <0X0 DT_SIZE_K(8)>;
+		};
+	};
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/boards/renesas/fpb_ra4e1/fpb_ra4e1.yaml b/boards/renesas/fpb_ra4e1/fpb_ra4e1.yaml
new file mode 100644
index 00000000000..865a0ee3375
--- /dev/null
+++ b/boards/renesas/fpb_ra4e1/fpb_ra4e1.yaml
@@ -0,0 +1,14 @@
+identifier: fpb_ra4e1
+name: Renesas FPB-RA4E1
+type: mcu
+arch: arm
+ram: 128
+flash: 512
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - uart
+  - watchdog
+vendor: renesas
diff --git a/boards/renesas/fpb_ra4e1/fpb_ra4e1_defconfig b/boards/renesas/fpb_ra4e1/fpb_ra4e1_defconfig
new file mode 100644
index 00000000000..f26066de3e5
--- /dev/null
+++ b/boards/renesas/fpb_ra4e1/fpb_ra4e1_defconfig
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_UART_CONSOLE=y
+CONFIG_CONSOLE=y
diff --git a/boards/renesas/fpb_ra6e1/doc/index.rst b/boards/renesas/fpb_ra6e1/doc/index.rst
index b9df0e22f36..7104db650db 100644
--- a/boards/renesas/fpb_ra6e1/doc/index.rst
+++ b/boards/renesas/fpb_ra6e1/doc/index.rst
@@ -1,7 +1,4 @@
-.. _fpb_ra6e1:
-
-RA6E1 Fast Prototyping Board
-############################
+.. zephyr:board:: fpb_ra6e1
 
 Overview
 ********
@@ -46,15 +43,9 @@ The key features of the FPB-RA6E1 board are categorized in three groups as follo
 
 - MCU boot configuration jumper
 
-.. figure:: fpb_ra6e1.webp
-	:align: center
-	:alt: RA6E1 Fast Prototyping Board
-
-	FPB-RA6E1 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
-
 Hardware
 ********
-Detailed hardware feature for the RA6E1 MCU group can be found at `RA6E1 Group User's Manual Hardware`_
+Detailed hardware features for the RA6E1 MCU group can be found at `RA6E1 Group User's Manual Hardware`_
 
 .. figure:: ra6e1_block_diagram.webp
 	:width: 442px
@@ -63,42 +54,18 @@ Detailed hardware feature for the RA6E1 MCU group can be found at `RA6E1 Group U
 
 	RA6E1 Block diagram (Credit: Renesas Electronics Corporation)
 
-Detailed hardware feature for the FPB-RA6E1 MCU can be found at `FPB-RA6E1 - User's Manual`_
+Detailed hardware features for the FPB-RA6E1 MCU can be found at `FPB-RA6E1 - User's Manual`_
 
 Supported Features
 ==================
 
-The below features are currently supported on Zephyr OS for FPB-RA6E1 board:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| COUNTER   | on-chip    | counter              |
-+-----------+------------+----------------------+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``fpb_ra6e1`` board target configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
@@ -108,15 +75,15 @@ Flashing
 ========
 
 Program can be flashed to FPB-RA6E1 via the on-board SEGGER J-Link debugger.
-SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
 
 To flash the program to board
 
-  1. Connect to J-Link OB via USB port to host PC
+1. Connect to J-Link OB via USB port to host PC
 
-  2. Make sure J-Link OB jumper is in default configuration as describe in `FPB-RA6E1 - User's Manual`_
+2. Make sure J-Link OB jumper is in default configuration as describe in `FPB-RA6E1 - User's Manual`_
 
-  3. Execute west command
+3. Execute west command
 
 	.. code-block:: console
 
diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi b/boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi
index 89628ad68be..1b86818f001 100644
--- a/boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi
+++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -39,6 +39,14 @@
 		};
 	};
 
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
+			renesas,analog-enable;
+		};
+	};
+
 	pwm1_default: pwm1_default {
 		group1 {
 			/* GTIOC1A GTIOC1B */
diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts
index 776df2f4b25..7b64e442278 100644
--- a/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts
+++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -22,6 +22,7 @@
 		zephyr,flash = &flash0;
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
+		zephyr,entropy = &trng;
 	};
 
 	leds {
@@ -48,6 +49,7 @@
 	aliases {
 		led0 = &led1;
 		sw0 = &button0;
+		watchdog0 = &wdt;
 	};
 };
 
@@ -116,6 +118,12 @@
 	pinctrl-names = "default";
 };
 
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &port_irq1 {
 	interrupts = <41 12>;
 	status = "okay";
@@ -128,3 +136,11 @@
 	interrupt-names = "gtioca", "overflow";
 	status = "okay";
 };
+
+&trng {
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml b/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml
index 8942834aca5..aaa08aa02e0 100644
--- a/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml
+++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1.yaml
@@ -9,3 +9,5 @@ toolchain:
   - gnuarmemb
 supported:
   - gpio
+  - watchdog
+vendor: renesas
diff --git a/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig b/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig
index 4fd3e749468..770a30fc47d 100644
--- a/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig
+++ b/boards/renesas/fpb_ra6e1/fpb_ra6e1_defconfig
@@ -1,17 +1,11 @@
 # Copyright (c) 2024 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
-
 # Enable GPIO
 CONFIG_GPIO=y
 
-CONFIG_BUILD_OUTPUT_HEX=y
-
 # Enable Console
 CONFIG_SERIAL=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
 CONFIG_UART_CONSOLE=y
 CONFIG_CONSOLE=y
-
-CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/fpb_ra6e2/doc/index.rst b/boards/renesas/fpb_ra6e2/doc/index.rst
index 76e04dba216..abef15ced4c 100644
--- a/boards/renesas/fpb_ra6e2/doc/index.rst
+++ b/boards/renesas/fpb_ra6e2/doc/index.rst
@@ -1,7 +1,4 @@
-.. _fpb_ra6e2:
-
-RA6E2 Fast Prototyping Board
-############################
+.. zephyr:board:: fpb_ra6e2
 
 Overview
 ********
@@ -23,7 +20,7 @@ The key features of the FPB-RA6E2 board are categorized in three groups as follo
 - MCU current measurement point for precision current consumption measurement
 - Multiple clock sources - RA6E2 MCU oscillator and sub-clock oscillator crystals,
   providing precision 24.000 MHz and 32,768 Hz reference clock.
-  Additional low precision clocks are avaialbe internal to the RA6E2 MCU
+  Additional low precision clocks are available internal to the RA6E2 MCU
 
 **System Control and Ecosystem Access**
 
@@ -50,15 +47,9 @@ The key features of the FPB-RA6E2 board are categorized in three groups as follo
 
 - MCU boot configuration jumper
 
-.. figure:: fpb_ra6e2.webp
-	:align: center
-	:alt: RA6E2 Fast Prototyping Board
-
-	FPB-RA6E2 Board Functional Area Definitions (Credit: Renesas Electronics Corporation)
-
 Hardware
 ********
-Detailed hardware feature for the RA6E2 MCU group can be found at `RA6E2 Group User's Manual Hardware`_
+Detailed hardware features for the RA6E2 MCU group can be found at `RA6E2 Group User's Manual Hardware`_
 
 .. figure:: ra6e2_block_diagram.webp
 	:width: 442px
@@ -67,40 +58,18 @@ Detailed hardware feature for the RA6E2 MCU group can be found at `RA6E2 Group U
 
 	RA6E2 Block diagram (Credit: Renesas Electronics Corporation)
 
-Detailed hardware feature for the FPB-RA6E2 MCU can be found at `FPB-RA6E2 - User's Manual`_
+Detailed hardware features for the FPB-RA6E2 MCU can be found at `FPB-RA6E2 - User's Manual`_
 
 Supported Features
 ==================
 
-The below features are currently supported on Zephyr OS for FPB-RA6E2 board:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| ENTROPY   | on-chip    | entropy              |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``fpb_ra6e2`` board target configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
@@ -110,15 +79,15 @@ Flashing
 ========
 
 Program can be flashed to fpb-RA6E2 via the on-board SEGGER J-Link debugger.
-SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
 
 To flash the program to board
 
-  1. Connect to J-Link OB via USB port to host PC
+1. Connect to J-Link OB via USB port to host PC
 
-  2. Make sure J-Link OB jumper is in default configuration as describe in `FPB-RA6E2 - User's Manual`_
+2. Make sure J-Link OB jumper is in default configuration as describe in `FPB-RA6E2 - User's Manual`_
 
-  3. Execute west command
+3. Execute west command
 
 	.. code-block:: console
 
diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi b/boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi
index 8d7e96e99b1..746d405e4c2 100644
--- a/boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi
+++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -30,6 +30,14 @@
 		};
 	};
 
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
+			renesas,analog-enable;
+		};
+	};
+
 	pwm1_default: pwm1_default {
 		group1 {
 			/* GTIOC1A GTIOC1B */
diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts
index 6175be7aaa0..60323b043e6 100644
--- a/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts
+++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -49,6 +49,7 @@
 		led0 = &led1;
 		led1 = &led2;
 		sw0 = &button0;
+		watchdog0 = &wdt;
 	};
 };
 
@@ -106,6 +107,12 @@
 	pinctrl-names = "default";
 };
 
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &port_irq9 {
 	interrupts = <41 12>;
 	status = "okay";
@@ -123,3 +130,7 @@
 &trng {
 	status ="okay";
 };
+
+&wdt {
+	status = "okay";
+};
diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml b/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml
index edd2002b2a3..0abf95dda52 100644
--- a/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml
+++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2.yaml
@@ -9,3 +9,5 @@ toolchain:
   - gnuarmemb
 supported:
   - gpio
+  - watchdog
+vendor: renesas
diff --git a/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig b/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig
index 882cf699d98..770a30fc47d 100644
--- a/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig
+++ b/boards/renesas/fpb_ra6e2/fpb_ra6e2_defconfig
@@ -1,8 +1,6 @@
 # Copyright (c) 2024 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=200000000
-
 # Enable GPIO
 CONFIG_GPIO=y
 
@@ -11,6 +9,3 @@ CONFIG_SERIAL=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
 CONFIG_UART_CONSOLE=y
 CONFIG_CONSOLE=y
-
-CONFIG_BUILD_OUTPUT_HEX=y
-CONFIG_CLOCK_CONTROL=y
diff --git a/boards/renesas/mck_ra8t1/board.yml b/boards/renesas/mck_ra8t1/board.yml
index b7897016bbe..dcd1bd71840 100644
--- a/boards/renesas/mck_ra8t1/board.yml
+++ b/boards/renesas/mck_ra8t1/board.yml
@@ -1,6 +1,6 @@
 board:
   name: mck_ra8t1
-  full_name: RA8T1 Evaluation Kit
+  full_name: RA8T1 Motor Control Kit
   vendor: renesas
   socs:
   - name: r7fa8t1ahecbd
diff --git a/boards/renesas/mck_ra8t1/doc/index.rst b/boards/renesas/mck_ra8t1/doc/index.rst
index e80028da83b..b8d6cdfddf1 100644
--- a/boards/renesas/mck_ra8t1/doc/index.rst
+++ b/boards/renesas/mck_ra8t1/doc/index.rst
@@ -1,7 +1,4 @@
-.. _mcb_ra8t1:
-
-RA8T1 Evaluation Kit
-####################
+.. zephyr:board:: mck_ra8t1
 
 Overview
 ********
@@ -20,7 +17,7 @@ MCK-RA8T1 kit includes the items below:
 
 .. figure:: mck_ra8t1_product_contents.jpg
 	:align: center
-	:alt: RA8T1 Evaluation Kit
+	:alt: RA8T1 Motor Control Kit
 
 	MCK-RA8T1 product contents (Credit: Renesas Electronics Corporation)
 
@@ -54,12 +51,6 @@ The specifications of the CPU board are shown below:
 - Ethrnet connector
 - microSD card connector
 
-.. figure:: mck_ra8t1.jpg
-	:align: center
-	:alt: RA8T1 Evaluation Kit
-
-	CPU Board Layout (Credit: Renesas Electronics Corporation)
-
 **Onboard debugger**
 
 This product has the onboard debugger circuit, J-Link On-Board (hereinafter called “J-Link-OB”). You can
@@ -67,7 +58,7 @@ write a program (firmware) of RA8T1 with it.
 
 Hardware
 ********
-Detail Hardware feature for the RA8T1 MCU group can be found at `RA8T1 Group User's Manual Hardware`_
+Detailed Hardware features for the RA8T1 MCU group can be found at `RA8T1 Group User's Manual Hardware`_
 
 .. figure:: ra8t1_block_diagram.png
 	:width: 442px
@@ -76,54 +67,22 @@ Detail Hardware feature for the RA8T1 MCU group can be found at `RA8T1 Group Use
 
 	RA8T1 Block diagram (Credit: Renesas Electronics Corporation)
 
-Detail Hardware feature for the  MCB-RA8T1 board can be found at `MCB-RA8T1 - User's Manual`_
+Detailed Hardware features for the  MCB-RA8T1 board can be found at `MCB-RA8T1 - User's Manual`_
 
 Supported Features
 ==================
 
-The below features are currently supported on Zephyr OS for MCB-RA8T1 board:
-
-+--------------+------------+----------------------+
-| Interface    | Controller | Driver/Component     |
-+==============+============+======================+
-| GPIO         | on-chip    | gpio                 |
-+--------------+------------+----------------------+
-| MPU          | on-chip    | arch/arm             |
-+--------------+------------+----------------------+
-| NVIC         | on-chip    | arch/arm             |
-+--------------+------------+----------------------+
-| UART         | on-chip    | serial               |
-+--------------+------------+----------------------+
-| CLOCK        | on-chip    | clock control        |
-+--------------+------------+----------------------+
-| ENTROPY      | on-chip    | entropy              |
-+--------------+------------+----------------------+
-| SPI          | on-chip    | spi                  |
-+--------------+------------+----------------------+
-| FLASH        | on-chip    | flash                |
-+--------------+------------+----------------------+
-| PWM          | on-chip    | pwm                  |
-+--------------+------------+----------------------+
-| COUNTER      | on-chip    | counter              |
-+--------------+------------+----------------------+
-| CAN          | on-chip    | canfd                |
-+--------------+------------+----------------------+
-| I2C          | on-chip    | i2c                  |
-+--------------+------------+----------------------+
-| ETHERNET     | on-chip    | ethernet             |
-+--------------+------------+----------------------+
-| ADC          | on-chip    | adc                  |
-+--------------+------------+----------------------+
-| SDHC         | on-chip    | sdhc                 |
-+--------------+------------+----------------------+
-
-**Note:** For using SDHC module on EK-RA8M1, Connect microSD Card to microSD Socket (CN12)
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
+
+.. note::
+
+   For using SDHC module on EK-RA8M1, Connect microSD Card to microSD Socket (CN12)
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``mcb_ra8t1`` board configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
@@ -136,15 +95,15 @@ Flashing
 ========
 
 Program can be flashed to MCB-RA8T1 via the on-board SEGGER J-Link debugger.
-SEGGER J-link's drivers are avaialbe at https://www.segger.com/downloads/jlink/
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
 
 To flash the program to board
 
-  1. Connect to J-Link OB via USB port to host PC
+1. Connect to J-Link OB via USB port to host PC
 
-  2. Make sure J-Link OB jumper is in default configuration as describe in `MCB-RA8T1 - User's Manual`_
+2. Make sure J-Link OB jumper is in default configuration as describe in `MCB-RA8T1 - User's Manual`_
 
-  3. Execute west command
+3. Execute west command
 
 	.. code-block:: console
 
diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi b/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi
index 5bb55bb8a0d..e9d127f2dfd 100644
--- a/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi
+++ b/boards/renesas/mck_ra8t1/mck_ra8t1-pinctrl.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -16,6 +16,15 @@
 		};
 	};
 
+	sci9_default: sci9_default {
+		group1 {
+			/* sda scl*/
+			psels = <RA_PSEL(RA_PSEL_SCI_9, 10, 14)>,<RA_PSEL(RA_PSEL_SCI_9, 10, 15)>;
+			drive-strength = "medium";
+			drive-open-drain;
+		};
+	};
+
 	spi0_default: spi0_default {
 		group1 {
 			/* MISO MOSI RSPCK SSL*/
@@ -79,6 +88,14 @@
 		};
 	};
 
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
+			renesas,analog-enable;
+		};
+	};
+
 	sdhc0_default: sdhc0_default {
 		group1 {
 			psels = <RA_PSEL(RA_PSEL_SDHI, 3, 6)>, /* SDCD */
@@ -95,4 +112,61 @@
 			drive-strength = "highspeed-high";
 		};
 	};
+
+	usbfs_default: usbfs_default {
+		group1 {
+			/* USBP USBN */
+			psels = <RA_PSEL(RA_PSEL_USBFS, 8, 15)>,
+				<RA_PSEL(RA_PSEL_USBFS, 8, 14)>,
+				<RA_PSEL(RA_PSEL_USBFS, 4, 7)>;
+			drive-strength = "high";
+		};
+	};
+
+	/omit-if-no-ref/ acmphs_ivref0: acmphs_ivref0 {
+		group1 {
+			/* IVREF0 */
+			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 1)>;
+			renesas,analog-enable;
+		};
+	};
+
+	/omit-if-no-ref/ acmphs_ivref1: acmphs_ivref1 {
+		group1 {
+			/* IVREF1 */
+			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 3)>;
+			renesas,analog-enable;
+		};
+	};
+
+	/omit-if-no-ref/ acmphs0_ivcmp0: acmphs0_ivcmp0 {
+		group1 {
+			/* CH0 IVCMP0 */
+			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 10)>;
+			renesas,analog-enable;
+		};
+	};
+
+	/omit-if-no-ref/ acmphs0_ivcmp2: acmphs0_ivcmp2 {
+		group1 {
+			/* CH0 IVCMP2 */
+			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 4)>;
+			renesas,analog-enable;
+		};
+	};
+
+	/omit-if-no-ref/ acmphs0_ivcmp3: acmphs0_ivcmp3 {
+		group1 {
+			/* CH0 IVCMP3 */
+			psels = <RA_PSEL(RA_PSEL_ACMPHS, 0, 6)>;
+			renesas,analog-enable;
+		};
+	};
+
+	/omit-if-no-ref/ acmphs_vcout: acmphs_vcout {
+		group1 {
+			/* VCOUT */
+			psels = <RA_PSEL(RA_PSEL_ACMPHS_VCOUT, 2, 8)>;
+		};
+	};
 };
diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.dts b/boards/renesas/mck_ra8t1/mck_ra8t1.dts
index d20ad5ecc4e..75cb5fc5c8e 100644
--- a/boards/renesas/mck_ra8t1/mck_ra8t1.dts
+++ b/boards/renesas/mck_ra8t1/mck_ra8t1.dts
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -47,6 +47,7 @@
 	aliases {
 		led0 = &led1;
 		sdhc0 = &sdhc0;
+		watchdog0 = &wdt;
 	};
 };
 
@@ -68,6 +69,8 @@
 	};
 
 	pllq {
+		div = <4>;
+		freq = <DT_FREQ_M(240)>;
 		status = "okay";
 	};
 
@@ -83,7 +86,13 @@
 };
 
 &canfdclk {
-	clocks = <&pll>;
+	clocks = <&pllp>;
+	div = <6>;
+	status = "okay";
+};
+
+&uclk {
+	clocks = <&pllq>;
 	div = <5>;
 	status = "okay";
 };
@@ -110,6 +119,17 @@
 	};
 };
 
+&sci9 {
+	pinctrl-0 = <&sci9_default>;
+	pinctrl-names = "default";
+
+	i2c9: i2c {
+		sda-output-delay = <300>;
+		noise-filter-clock-select = <1>;
+		bit-rate-modulation;
+	};
+};
+
 &trng {
 	status = "okay";
 };
@@ -184,6 +204,12 @@
 	average-count = <4>;
 };
 
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &sdhc0 {
 	compatible = "renesas,ra-sdhc";
 	pinctrl-0 = <&sdhc0_default>;
@@ -196,3 +222,33 @@
 		status = "okay";
 	};
 };
+
+&usbfs {
+	pinctrl-0 = <&usbfs_default>;
+	pinctrl-names = "default";
+	maximum-speed = "full-speed";
+	status = "okay";
+	zephyr_udc0: udc {
+		status = "okay";
+	};
+};
+
+&wdt {
+	status = "okay";
+};
+
+&ulpt0 {
+	status = "okay";
+
+	timer {
+		status = "okay";
+	};
+};
+
+&ulpt1 {
+	status = "okay";
+
+	timer {
+		status = "okay";
+	};
+};
diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1.yaml b/boards/renesas/mck_ra8t1/mck_ra8t1.yaml
index 52ef233d98f..ca61ae119d0 100644
--- a/boards/renesas/mck_ra8t1/mck_ra8t1.yaml
+++ b/boards/renesas/mck_ra8t1/mck_ra8t1.yaml
@@ -10,3 +10,6 @@ toolchain:
 supported:
   - gpio
   - uart
+  - watchdog
+  - usbd
+vendor: renesas
diff --git a/boards/renesas/mck_ra8t1/mck_ra8t1_defconfig b/boards/renesas/mck_ra8t1/mck_ra8t1_defconfig
index 07c0ee5f1ca..35ed0307b9a 100644
--- a/boards/renesas/mck_ra8t1/mck_ra8t1_defconfig
+++ b/boards/renesas/mck_ra8t1/mck_ra8t1_defconfig
@@ -1,8 +1,6 @@
 # Copyright (c) 2024 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=480000000
-
 # Enable GPIO
 CONFIG_GPIO=y
 
@@ -11,7 +9,3 @@ CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
 CONFIG_CONSOLE=y
-
-CONFIG_CLOCK_CONTROL=y
-
-CONFIG_BUILD_OUTPUT_HEX=y
diff --git a/boards/renesas/rza2m_evk/Kconfig.rza2m_evk b/boards/renesas/rza2m_evk/Kconfig.rza2m_evk
new file mode 100644
index 00000000000..80e6a4421d4
--- /dev/null
+++ b/boards/renesas/rza2m_evk/Kconfig.rza2m_evk
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RZA2M_EVK
+	select SOC_R7S921053VCBG
diff --git a/boards/renesas/rza2m_evk/board.cmake b/boards/renesas/rza2m_evk/board.cmake
new file mode 100644
index 00000000000..2b517560142
--- /dev/null
+++ b/boards/renesas/rza2m_evk/board.cmake
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7S921053VCBG")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/rza2m_evk/board.yml b/boards/renesas/rza2m_evk/board.yml
new file mode 100644
index 00000000000..cf207b412da
--- /dev/null
+++ b/boards/renesas/rza2m_evk/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: rza2m_evk
+  full_name: RZ/A2M Evaluation Kit
+  vendor: renesas
+  socs:
+  - name: r7s921053vcbg
diff --git a/boards/renesas/rza2m_evk/doc/index.rst b/boards/renesas/rza2m_evk/doc/index.rst
new file mode 100644
index 00000000000..91999c07e2e
--- /dev/null
+++ b/boards/renesas/rza2m_evk/doc/index.rst
@@ -0,0 +1,73 @@
+.. zephyr:board:: rza2m_evk
+
+Overview
+********
+
+The RZ/A2M Evaluation Board Kit is a best evaluation board kit to evaluate RZ/A2M.
+
+* On-board device: RZ/A2M (R7S921053VCBG: with DRP function, without encryption function, internal
+  RAM 4MB) Evaluation of DRP (Dynamically Reconfigurable Processor) is possible.
+* MIPI Camera Module (MIPI CSI) is bundled and image recognition processing etc. can be used with
+  images input with MIPI camera.
+* HyperMCP (Multi-chip package), in which HyperFlash and HyperRAM are installed in one package,
+  is mounted. HyperFlash and HyperRAM can be evaluated.
+* A Display Output Board is included and the graphic output is possible by connecting it to the
+  external display.
+* It is possible to evaluate 2ch Ethernet communication.
+* Other peripheral functions such as SDHI and USB can also be evaluated.
+* Allows for safe and secure connection to the AWS cloud.
+  HyperFlash and HyperRAM are trademarks of Cypress Semiconductor Corporation of the U.S.
+
+Hardware
+********
+
+The Renesas RZ/A2M MPU documentation can be found at `RZ/A2M Group Website`_
+
+.. figure:: rza2m_block_diagram.webp
+	:width: 600px
+	:align: center
+	:alt: RZ/A2M group feature
+
+	RZ/A2M block diagram (Credit: Renesas Electronics Corporation)
+
+Detailed hardware features for the board can be found at `RZ/A2M-EVK Website`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``rza2m_evk`` board configuration can be
+built and flashed in the usual way (see :ref:`build_an_application`
+and :ref:`application_run` for more details).
+
+Console
+=======
+
+The UART port is accessed by USB-Serial port (CN5).
+
+Building & Flashing
+===================
+
+Here is an example for building and flashing the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rza2m_evk
+   :goals: build flash
+
+References
+**********
+
+.. target-notes::
+
+.. _RZ/A2M Group Website:
+   https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rza2m-image-processing-rtos-mpu-drp-and-4mb-chip-ram
+
+.. _RZ/A2M-EVK Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rza2m-evkit-rza2m-evaluation-kit
diff --git a/boards/renesas/rza2m_evk/doc/rza2m_block_diagram.webp b/boards/renesas/rza2m_evk/doc/rza2m_block_diagram.webp
new file mode 100644
index 00000000000..228f93ee4dd
Binary files /dev/null and b/boards/renesas/rza2m_evk/doc/rza2m_block_diagram.webp differ
diff --git a/boards/renesas/rza2m_evk/doc/rza2m_evkit.webp b/boards/renesas/rza2m_evk/doc/rza2m_evkit.webp
new file mode 100644
index 00000000000..71a57f850a7
Binary files /dev/null and b/boards/renesas/rza2m_evk/doc/rza2m_evkit.webp differ
diff --git a/boards/renesas/rza2m_evk/rza2m_evk-pinctrl.dtsi b/boards/renesas/rza2m_evk/rza2m_evk-pinctrl.dtsi
new file mode 100644
index 00000000000..8d076ece20e
--- /dev/null
+++ b/boards/renesas/rza2m_evk/rza2m_evk-pinctrl.dtsi
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza2m.h>
+
+&pinctrl {
+	/omit-if-no-ref/ scif4_default: scif4_default {
+		scif4-pinmux {
+			pinmux = <RZA2M_PINMUX(PORT_09, 0, 4)>, /* TXD */
+				 <RZA2M_PINMUX(PORT_09, 1, 4)>; /* RXD */
+		};
+	};
+};
diff --git a/boards/renesas/rza2m_evk/rza2m_evk.dts b/boards/renesas/rza2m_evk/rza2m_evk.dts
new file mode 100644
index 00000000000..64ab5b34339
--- /dev/null
+++ b/boards/renesas/rza2m_evk/rza2m_evk.dts
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <arm/renesas/rz/rza/r7s9210.dtsi>
+#include <freq.h>
+#include "rza2m_evk-pinctrl.dtsi"
+
+/ {
+	model = "Renesas RZA2M EVK";
+	compatible = "renesas,rza2m_evk";
+
+	chosen {
+		zephyr,sram = &ram;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,console = &scif4;
+		zephyr,shell-uart = &scif4;
+	};
+
+	aliases {
+		led0 = &led1_green;
+		led1 = &led1_red;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1_red: led1_red {
+			gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>;
+		};
+
+		led1_green: led1_green {
+			gpios = <&gpioc 1 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	flash0: flash@20000000 {
+		compatible = "mmio-sram";
+		reg = <0x20000000 DT_SIZE_M(64)>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			loader_program: partition@0 {
+				label = "loader-program";
+				reg = <0x00000000 DT_SIZE_K(56)>;
+				read-only;
+			};
+
+			slot0_partition: partition@E000  {
+				label = "image-0";
+				reg = <0x0000E000 (DT_SIZE_M(64) - DT_SIZE_K(56))>;
+				read-only;
+			};
+		};
+	};
+};
+
+&osc {
+	clock-frequency = <DT_FREQ_M(24)>;
+};
+
+&iclk {
+	clock-frequency = <DT_FREQ_M(528)>;
+};
+
+&bclk {
+	clock-frequency = <DT_FREQ_M(132)>;
+};
+
+&p1clk {
+	clock-frequency = <DT_FREQ_M(66)>;
+};
+
+&ostm0 {
+	status = "okay";
+};
+
+/* Currently, the maximum supported baud rate on the USB Micro port (CN5) is 115200 */
+&scif4 {
+	pinctrl-0 = <&scif4_default>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
diff --git a/boards/renesas/rza2m_evk/rza2m_evk.yaml b/boards/renesas/rza2m_evk/rza2m_evk.yaml
new file mode 100644
index 00000000000..402c81a73ef
--- /dev/null
+++ b/boards/renesas/rza2m_evk/rza2m_evk.yaml
@@ -0,0 +1,11 @@
+identifier: rza2m_evk
+name: RZ/A2M Evaluation Kit
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - uart
+  - gpio
+vendor: renesas
diff --git a/boards/renesas/rza2m_evk/rza2m_evk_defconfig b/boards/renesas/rza2m_evk/rza2m_evk_defconfig
new file mode 100644
index 00000000000..e9b1c9e5c94
--- /dev/null
+++ b/boards/renesas/rza2m_evk/rza2m_evk_defconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_XIP=n
+
+# Enable clock control
+CONFIG_CLOCK_CONTROL=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
diff --git a/boards/renesas/rza3ul_smarc/Kconfig.rza3ul_smarc b/boards/renesas/rza3ul_smarc/Kconfig.rza3ul_smarc
new file mode 100644
index 00000000000..56e7567e777
--- /dev/null
+++ b/boards/renesas/rza3ul_smarc/Kconfig.rza3ul_smarc
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RZA3UL_SMARC
+	select SOC_R9A07G063U02GBG
diff --git a/boards/renesas/rza3ul_smarc/board.cmake b/boards/renesas/rza3ul_smarc/board.cmake
new file mode 100644
index 00000000000..f67ff5510ec
--- /dev/null
+++ b/boards/renesas/rza3ul_smarc/board.cmake
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R9A07G063U02GBG")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/rza3ul_smarc/board.yml b/boards/renesas/rza3ul_smarc/board.yml
new file mode 100644
index 00000000000..d00b2df7af9
--- /dev/null
+++ b/boards/renesas/rza3ul_smarc/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: rza3ul_smarc
+  full_name: RZ/A3UL SMARC Evaluation Board Kit
+  vendor: renesas
+  socs:
+  - name: r9a07g063u02gbg
diff --git a/boards/renesas/rza3ul_smarc/doc/index.rst b/boards/renesas/rza3ul_smarc/doc/index.rst
new file mode 100644
index 00000000000..e26850853ab
--- /dev/null
+++ b/boards/renesas/rza3ul_smarc/doc/index.rst
@@ -0,0 +1,129 @@
+.. zephyr:board:: rza3ul_smarc
+
+Overview
+********
+
+The Renesas RZ/A3UL SMARC Evaluation Board Kit (RZ/A3UL-EVKIT) consists of a SMARC v2.1 module board and a carrier board.
+Two types of evaluation boards are available: QSPI version and Octal-SPI version. The QSPI version is supported.
+
+* Device: RZ/A3UL R9A07G063U02GBG
+
+  * Cortex-A55 Single
+  * BGA361pin, 13mmSq body, 0.5mm pitch
+  * Certified device in `Azure Certified Device Catalog <https://devicecatalog.azure.com/devices/5848d87b-5d3e-4c11-ad76-90612639b025>`_
+
+* SMARC v2.1 Module Board Functions
+
+  * Two types of evaluation boards are available:
+
+    * QSPI version: QSPI Serial Flash (Boot) + DDR4
+    * Octal-SPI version: Octa Flash (Boot) + OctaRAM + DDR4
+
+  * DDR4 SDRAM: 1GB x 1pc
+  * QSPI flash memory: 128Mb x 1pc `AT25QL128A <https://www.renesas.com/en/products/memory-logic/non-volatile-memory/spi-nor-flash/at25ql128a-128mbit-17v-minimum-spi-serial-flash-memory-dual-io-quad-io-and-qpi-support>`_ (QSPI version)
+  * Octa RAM memory: 512Mb x 1pc / Octa flash memory: 1Gb x 1pc (Octal-SPI version)
+  * eMMC memory: 64GB x 1pc
+  * The microSD card slot is implemented and used as an eSD for boot.
+  * 5-output clock oscillator `5P35023 <https://www.renesas.com/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator>`_ implemented
+  * PMIC power supply `DA9062 <https://www.renesas.com/en/products/power-management/multi-channel-power-management-ics-pmics/da9062-pmic-designed-applications-requiring-85a>`_ implemented
+
+* Carrier Board Functions
+
+  * The FFC/FPC connector is mounted as standard for connection to high-speed serial interface for camera module.
+  * The Micro-HDMI connector via DSI/HDMI conversion module is mounted as standard for connection to high-speed serial interface for digital video module.
+  * The Micro-AB receptacle (ch0: USB2.0 OTG) and A receptacle (ch1: USB2.0 Host) are respectively mounted as standard for connection to USB interface.
+  * The RJ45 connector is mounted as standard for software development and evaluation using Ethernet.
+  * The audio codec is mounted as standard for advance development of audio system. The audio jack is implemented for connection to audio interface.
+  * The Micro-AB receptacles are implemented for connection to asynchronous serial port interface.
+  * The microSD card slot and two sockets for PMOD are implemented as an interface for RZ/A3UL peripheral functions.
+  * For power supply, a mounted USB Type-C receptacle supports the USB PD standard.
+
+Hardware
+********
+The Renesas RZ/A3UL MPU documentation can be found at `RZ/A3UL Group Website`_
+
+.. figure:: rza3ul_block_diagram.webp
+	:width: 600px
+	:align: center
+	:alt: RZ/A3UL group feature
+
+	RZ/A3UL block diagram (Credit: Renesas Electronics Corporation)
+
+Detailed hardware features for the board can be found at `RZA3UL-EVKIT Website`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+RZ/A3UL-EVKIT uses Initial Program Loader (IPL) to perform initial settings and copy the Zephyr image from flash to DDR SRAM for execution. It only needs to be written to flash once.
+
+There are two options to write IPL:
+
+1. (Recommended) Follow ''4. Tutorial: Your First RZ MPU Project - Blinky'' of `Getting Started with RZ/A Flexible Software Package`_
+   to start writing a blinky sample with FSP. The IPL will be written to flash by default in debugging time.
+
+2. Follow the `Initial Program Loader Application Note`_ to write the IPL separately. The minimal steps are described below.
+
+   a. Follow ''6. IPL development environment construction procedure'' to prepare the build environment.
+
+   b. Follow ''7. IPL build environment construction procedure'' to build Initial Program Loader.
+      If the build is successful, Initial Program Loader file will be generated in /build/a3ul/release/rza3ul_smarc_qspi_ipl.srec
+
+   c. Follow ''8.1 Create Debug Configuration'' to create a Debug configuration to run Initial Program Loader on the target board.
+
+   d. Follow ''8.2 Connection to SMARC EVK Board'' to setup target board with SW1 Debugger Enable (SW1-1 OFF) and Boot (1.8V) Mode (SW11[1:4]=OFF OFF OFF ON).
+
+   e. Follow ''8.4 Execution procedure of IPL'' to write Initial Program Loader to the target board.
+
+Applications for the ``rza3ul_smarc`` board can be built in the usual way as
+documented in :ref:`build_an_application`.
+
+Console
+=======
+The UART port is accessed by USB Type-mircoB port (CN14).
+
+Debugging
+=========
+
+It is possible to load and execute a Zephyr application binary on this board on the Cortex-A55 System Core
+from the DDR SDRAM, using ``JLink`` debugger (:ref:`jlink-debug-host-tools`).
+
+Here is an example for building and debugging with the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rza3ul_smarc
+   :goals: build debug
+
+Flashing
+========
+
+Zephyr application can be flashed to QSPI/Octal-SPI storage and then loaded by Initial Program Loader.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rza3ul_smarc
+   :goals: build flash
+
+References
+**********
+
+.. target-notes::
+
+.. _RZ/A3UL Group Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rza3ul-powerful-1ghz-64-bit-mpus-rtos-support-enables-high-definition-hmi-and-quick-startup?
+
+.. _RZA3UL-EVKIT Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rza3ul-evkit-rza3ul-evaluation-board-kit
+
+.. _Initial Program Loader Application Note:
+   https://github.com/renesas/rza-initial-program-loader/tree/main/application_note
+
+.. _Getting Started with RZ/A Flexible Software Package:
+   https://www.renesas.com/en/document/apn/rza-getting-started-flexible-software-package
diff --git a/boards/renesas/rza3ul_smarc/doc/rza3ul_block_diagram.webp b/boards/renesas/rza3ul_smarc/doc/rza3ul_block_diagram.webp
new file mode 100644
index 00000000000..1eee3f8b4bc
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diff --git a/boards/renesas/rza3ul_smarc/doc/rza3ul_smarc.webp b/boards/renesas/rza3ul_smarc/doc/rza3ul_smarc.webp
new file mode 100644
index 00000000000..91335d3057f
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diff --git a/boards/renesas/rza3ul_smarc/rza3ul_smarc-pinctrl.dtsi b/boards/renesas/rza3ul_smarc/rza3ul_smarc-pinctrl.dtsi
new file mode 100644
index 00000000000..25e26032f61
--- /dev/null
+++ b/boards/renesas/rza3ul_smarc/rza3ul_smarc-pinctrl.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza-common.h>
+
+&pinctrl {
+	/omit-if-no-ref/ scif0_pins: scif0 {
+		scif0-pinmux {
+			pinmux = <RZA_PINMUX(PORT_06, 3, 6)>, /* RXD */
+				 <RZA_PINMUX(PORT_06, 4, 6)>; /* TXD */
+			drive-strength = <1>;
+			slew-rate = "fast";
+		};
+	};
+};
diff --git a/boards/renesas/rza3ul_smarc/rza3ul_smarc.dts b/boards/renesas/rza3ul_smarc/rza3ul_smarc.dts
new file mode 100644
index 00000000000..c3c0be4c817
--- /dev/null
+++ b/boards/renesas/rza3ul_smarc/rza3ul_smarc.dts
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
+#include <freq.h>
+#include <arm64/renesas/rz/rza/r9a07g063.dtsi>
+#include "rza3ul_smarc-pinctrl.dtsi"
+
+/ {
+	model = "Renesas RZ/A3UL SMARC";
+	compatible = "renesas,rza3ul-smarc";
+
+	chosen {
+		zephyr,sram = &ddr;
+		zephyr,flash = &spi_flash;
+		zephyr,console = &scif0;
+		zephyr,shell-uart = &scif0;
+		zephyr,code-partition= &slot0_partition;
+	};
+
+	ddr: memory@40200000 {
+		compatible ="zephyr,memory-region", "mmio-sram";
+		reg = <0x40200000 (DT_SIZE_M(1024) - 0x200000)>;
+		zephyr,memory-region = "DDR";
+	};
+
+	sram: memory@1e000 {
+		compatible ="zephyr,memory-region", "mmio-sram";
+		reg = <0x1e000 DT_SIZE_K(72)>;
+		zephyr,memory-region = "SRAM";
+	};
+
+	spi_flash: memory@20020000 {
+		compatible = "mmio-sram";
+		reg = <0x20020000 (DT_SIZE_M(16) - 0x20000)>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			header: partition@0 {
+				label = "header";
+				reg = <0x00000000 0x200>;
+				read-only;
+			};
+
+			slot0_partition: partition@200 {
+				label = "image-0";
+				reg = <0x00000200 (DT_SIZE_M(16)- 0x20200)>;
+				read-only;
+			};
+		};
+	};
+
+};
+
+&scif0 {
+	current-speed = <115200>;
+	pinctrl-0 = <&scif0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/boards/renesas/rza3ul_smarc/rza3ul_smarc.yaml b/boards/renesas/rza3ul_smarc/rza3ul_smarc.yaml
new file mode 100644
index 00000000000..2e7f9d53356
--- /dev/null
+++ b/boards/renesas/rza3ul_smarc/rza3ul_smarc.yaml
@@ -0,0 +1,13 @@
+identifier: rza3ul_smarc
+name: Cortex-A55 for Renesas RZ/A3UL SMARC
+type: mcu
+arch: arm64
+toolchain:
+  - zephyr
+  - cross-compile
+supported:
+  - uart
+  - gpio
+testing:
+  ignore_tags:
+    - bluetooth
diff --git a/boards/renesas/rza3ul_smarc/rza3ul_smarc_defconfig b/boards/renesas/rza3ul_smarc/rza3ul_smarc_defconfig
new file mode 100644
index 00000000000..dd2f33248dd
--- /dev/null
+++ b/boards/renesas/rza3ul_smarc/rza3ul_smarc_defconfig
@@ -0,0 +1,19 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_XIP=n
+
+# MMU Options
+CONFIG_MAX_XLAT_TABLES=24
+
+# Cache Options
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_DCACHE_LINE_SIZE_DETECT=y
+CONFIG_ICACHE_LINE_SIZE_DETECT=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/renesas/rzg2l_smarc/Kconfig.rzg2l_smarc b/boards/renesas/rzg2l_smarc/Kconfig.rzg2l_smarc
new file mode 100644
index 00000000000..5182ddce831
--- /dev/null
+++ b/boards/renesas/rzg2l_smarc/Kconfig.rzg2l_smarc
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RZG2L_SMARC
+	select SOC_R9A07G044L23GBG
diff --git a/boards/renesas/rzg2l_smarc/board.cmake b/boards/renesas/rzg2l_smarc/board.cmake
new file mode 100644
index 00000000000..a9ee8b37d8c
--- /dev/null
+++ b/boards/renesas/rzg2l_smarc/board.cmake
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R9A07G044L23")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/rzg2l_smarc/board.yml b/boards/renesas/rzg2l_smarc/board.yml
new file mode 100644
index 00000000000..c051acd5449
--- /dev/null
+++ b/boards/renesas/rzg2l_smarc/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: rzg2l_smarc
+  full_name: RZ/G2L SMARC Evaluation Board Kit
+  vendor: renesas
+  socs:
+  - name: r9a07g044l23gbg
diff --git a/boards/renesas/rzg2l_smarc/doc/index.rst b/boards/renesas/rzg2l_smarc/doc/index.rst
new file mode 100644
index 00000000000..5af6b0d19bf
--- /dev/null
+++ b/boards/renesas/rzg2l_smarc/doc/index.rst
@@ -0,0 +1,158 @@
+.. zephyr:board:: rzg2l_smarc
+
+Overview
+********
+
+The Renesas RZ/G2L SMARC Evaluation Board Kit (RZ/G2L-EVKIT) consists of a SMARC v2.1 module board and a carrier board.
+
+* Device: RZ/G2L R9A07G044L23GBG
+
+  * Cortex-A55 Dual, Cortex-M33
+  * BGA551pin, 15mmSq body, 0.5mm pitch
+
+* SMARC v2.1 Module Board Functions
+
+  * DDR4 SDRAM: 2GB x 1pc
+  * QSPI flash memory: 512Mb x 1pc
+  * eMMC memory: 64GB x 1pc
+  * The microSD card slot is implemented and used as an eSD for boot
+  * 5-output clock oscillator `5P35023 <https://www.renesas.com/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator>`_ implemented
+  * PMIC power supply `RAA215300 <https://www.renesas.com/en/products/power-management/multi-channel-power-management-ics-pmics/raa215300-high-performance-9-channel-pmic-supporting-ddr-memory-built-charger-and-rtc>`_ implemented
+
+* Carrier Board Functions
+
+  * The FFC/FPC connector is mounted as standard for connection to high-speed serial interface for camera module.
+  * The Micro-HDMI connector via DSI/HDMI conversion module is mounted as standard for connection to high-speed serial interface for digital video module.
+  * The Micro-AB receptacle (ch0: USB2.0 OTG) and A receptacle (ch1: USB2.0 Host) are respectively mounted as standard for connection to USB interface.
+  * The RJ45 connector is mounted as standard for software development and evaluation using Ethernet.
+  * The audio codec is mounted as standard for advance development of audio system. The audio jack is implemented for connection to audio interface.
+  * The Micro-AB receptacles are implemented for connection to asynchronous serial port interface.
+  * The microSD card slot and two sockets for PMOD are implemented as an interface for peripheral functions.
+  * For power supply, a mounted USB Type-C receptacle supports the USB PD standard.
+
+Hardware
+********
+
+The Renesas RZ/G2L MPU documentation can be found at `RZ/G2L Group Website`_
+
+.. figure:: rzg2l_block_diagram.webp
+	:width: 600px
+	:align: center
+	:alt: RZ/G2L group feature
+
+	RZ/G2L block diagram (Credit: Renesas Electronics Corporation)
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+Applications for the ``rzg2l_smarc`` board can be built in the usual way as
+documented in :ref:`build_an_application`.
+
+Console
+=======
+
+The UART port for Cortex-M33 System Core can be accessed by connecting `Pmod USBUART <https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/>`_
+to the upper side of ``PMOD 1``.
+
+Debugging
+=========
+
+It is possible to load and execute a Zephyr application binary on
+this board on the Cortex-M33 System Core from
+the internal SRAM, using ``JLink`` debugger (:ref:`jlink-debug-host-tools`).
+
+Here is an example for building and debugging with the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rzg2l_smarc/r9a07g044l23gbg/cm33
+   :goals: build debug
+
+Flashing
+========
+
+RZ/G2L-EVKIT is designed to start different systems on different cores.
+It uses Yocto as the build system to build Linux system and boot loaders
+to run Zephyr on Cortex-M33 with u-boot. The minimal steps are described below.
+
+1. Follow "2.2 Building Images" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ to prepare the build environment.
+
+2. At step (4), follow step "2. Download Multi-OS Package" and "3. Add the layer for Multi-OS Package"
+   of "3.2 OpenAMP related stuff Integration for RZ/G2L, RZ/G2LC and RZ/G2UL" of `Release Note for RZ/G Multi-OS Package V2.0.2`_
+   to add the layer for Multi-OS Package.
+
+   .. code-block:: console
+
+      $ cd ~/rzg_vlp_<pkg ver>
+      $ unzip <Multi-OS Dir>/r01an5869ej0202-rzg-multi-os-pkg.zip
+      $ tar zxvf r01an5869ej0202-rzg-multi-os-pkg/meta-rz-features_multi-os_v2.0.2.tar.gz
+      $ bitbake-layers add-layer ../meta-rz-features/meta-rz-multi-os/meta-rzg2l
+
+3. Start the build:
+
+   .. code-block:: console
+
+      $ MACHINE=smarc-rzg2l bitbake core-image-minimal
+
+   The below necessary artifacts will be located in the build/tmp/deploy/images
+
+   +---------------+------------------------------------------------------+
+   | Artifacts     | File name                                            |
+   +===============+======================================================+
+   | Boot loader   | bl2_bp-smarc-rzg2l_pmic.srec                         |
+   |               |                                                      |
+   |               | fip-smarc-rzg2l_pmic.srec                            |
+   +---------------+------------------------------------------------------+
+   | Flash Writer  | Flash_Writer_SCIF_RZG2L_SMARC_PMIC_DDR4_2GB_1PCS.mot |
+   +---------------+------------------------------------------------------+
+
+4. Follow "4.2 Startup Procedure" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ for power supply and board setting
+   at SCIF download (SW11[1:4] = OFF, ON, OFF, ON) and (SW1[1:2] = ON, OFF)
+
+5. Follow "4.3 Download Flash Writer to RAM" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ to download Flash Writer to RAM
+
+6. Follow "4.4 Write the Bootloader" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ to write the boot loader
+   to the target board by using Flash Writer.
+
+7. Follow "4.5 Change Back to Normal Boot Mode" with switch setting (SW11[1:4] = OFF, OFF, OFF, ON) and (SW1[1:2] = ON, OFF)
+
+8. Follow "3. Preparing the SD Card" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ to write files to the microSD Card
+
+9. Copy zephyr.bin file to microSD card
+
+10. Follow "4.4.2 CM33 Sample Program Invocation with u-boot" from the beginning to step 4 of `Release Note for RZ/G Multi-OS Package V2.0.2`_
+
+11. Execute the commands stated below on the console to start zephyr application with CM33 core.
+    Here, ''N'' stands for the partition number in which you stored zephyr.bin file.
+
+   .. code-block:: console
+
+      Hit any key to stop autoboot: 2
+      => dcache off
+      => mmc dev 1
+      => fatload mmc 1:N 0x00010000 zephyr.bin
+      => fatload mmc 1:N 0x40010000 zephyr.bin
+      => cm33 start_normal 0x00010000 0x40010000
+      => dcache on
+
+References
+**********
+
+.. target-notes::
+
+.. _RZ/G2L Group Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzg2l-general-purpose-mpu-dual-core-arm-cortex-a55-cpus-and-single-core-cortex-m33-cpu-3d-graphics-and
+
+.. _RZG2L-EVKIT Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzg2l-evkit-evaluation-board-kit-rzg2l-mpu
+
+.. _SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide:
+   https://www.renesas.com/en/document/gde/smarc-evk-rzg2l-rzg2lc-rzg2ul-linux-start-guide-rev105
+
+.. _Release Note for RZ/G Multi-OS Package V2.0.2:
+   https://www.renesas.com/us/en/document/rln/release-note-rzg-multi-os-package-v202
diff --git a/boards/renesas/rzg2l_smarc/doc/rzg2l_block_diagram.webp b/boards/renesas/rzg2l_smarc/doc/rzg2l_block_diagram.webp
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diff --git a/boards/renesas/rzg2l_smarc/rzg2l_smarc-pinctrl.dtsi b/boards/renesas/rzg2l_smarc/rzg2l_smarc-pinctrl.dtsi
new file mode 100644
index 00000000000..7990abe700e
--- /dev/null
+++ b/boards/renesas/rzg2l_smarc/rzg2l_smarc-pinctrl.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg2-common.h>
+
+&pinctrl {
+	/omit-if-no-ref/ scif0_pins: scif0 {
+		scif0-pinmux {
+			pinmux = <RZG_PINMUX(PORT_38, 0, 1)>, /* TXD */
+				 <RZG_PINMUX(PORT_38, 1, 1)>; /* RXD */
+		};
+	};
+
+	/omit-if-no-ref/ scif2_pins: scif2 {
+		scif2-pinmux {
+			pinmux = <RZG_PINMUX(PORT_48, 0, 1)>, /* TXD */
+				 <RZG_PINMUX(PORT_48, 1, 1)>; /* RXD */
+		};
+	};
+};
diff --git a/boards/renesas/rzg2l_smarc/rzg2l_smarc_r9a07g044l23gbg_cm33.dts b/boards/renesas/rzg2l_smarc/rzg2l_smarc_r9a07g044l23gbg_cm33.dts
new file mode 100644
index 00000000000..7dc022ec427
--- /dev/null
+++ b/boards/renesas/rzg2l_smarc/rzg2l_smarc_r9a07g044l23gbg_cm33.dts
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <arm/renesas/rz/rzg/r9a07g044.dtsi>
+#include "rzg2l_smarc-pinctrl.dtsi"
+
+/ {
+	model = "Renesas RZ/G2L SMARC";
+	compatible = "renesas,rzg2l-smarc";
+
+	chosen {
+		zephyr,sram = &ddr;
+		zephyr,console = &scif2;
+		zephyr,shell-uart = &scif2;
+	};
+
+	ddr: memory@60010000 {
+		compatible = "mmio-sram";
+		reg = <0x60010000 DT_SIZE_M(46)>;
+	};
+};
+
+&scif2 {
+	current-speed = <115200>;
+	pinctrl-0 = <&scif2_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/boards/renesas/rzg2l_smarc/rzg2l_smarc_r9a07g044l23gbg_cm33.yaml b/boards/renesas/rzg2l_smarc/rzg2l_smarc_r9a07g044l23gbg_cm33.yaml
new file mode 100644
index 00000000000..f2f11f6f5d8
--- /dev/null
+++ b/boards/renesas/rzg2l_smarc/rzg2l_smarc_r9a07g044l23gbg_cm33.yaml
@@ -0,0 +1,10 @@
+identifier: rzg2l_smarc/r9a07g044l23gbg/cm33
+name: Cortex-M33 for Renesas RZ/G2L SMARC
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - uart
+  - gpio
diff --git a/boards/renesas/rzg2l_smarc/rzg2l_smarc_r9a07g044l23gbg_cm33_defconfig b/boards/renesas/rzg2l_smarc/rzg2l_smarc_r9a07g044l23gbg_cm33_defconfig
new file mode 100644
index 00000000000..c9dd44d6c70
--- /dev/null
+++ b/boards/renesas/rzg2l_smarc/rzg2l_smarc_r9a07g044l23gbg_cm33_defconfig
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_XIP=n
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/renesas/rzg2lc_smarc/Kconfig.rzg2lc_smarc b/boards/renesas/rzg2lc_smarc/Kconfig.rzg2lc_smarc
new file mode 100644
index 00000000000..91b89b55e6b
--- /dev/null
+++ b/boards/renesas/rzg2lc_smarc/Kconfig.rzg2lc_smarc
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RZG2LC_SMARC
+	select SOC_R9A07G044C22GBG
diff --git a/boards/renesas/rzg2lc_smarc/board.cmake b/boards/renesas/rzg2lc_smarc/board.cmake
new file mode 100644
index 00000000000..4d702170b69
--- /dev/null
+++ b/boards/renesas/rzg2lc_smarc/board.cmake
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R9A07G044C22")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/rzg2lc_smarc/board.yml b/boards/renesas/rzg2lc_smarc/board.yml
new file mode 100644
index 00000000000..5a518a9f7a3
--- /dev/null
+++ b/boards/renesas/rzg2lc_smarc/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: rzg2lc_smarc
+  full_name: RZ/G2LC SMARC Evaluation Board Kit
+  vendor: renesas
+  socs:
+  - name: r9a07g044c22gbg
diff --git a/boards/renesas/rzg2lc_smarc/doc/index.rst b/boards/renesas/rzg2lc_smarc/doc/index.rst
new file mode 100644
index 00000000000..ea2061fe3cc
--- /dev/null
+++ b/boards/renesas/rzg2lc_smarc/doc/index.rst
@@ -0,0 +1,158 @@
+.. zephyr:board:: rzg2lc_smarc
+
+Overview
+********
+
+The Renesas RZ/G2LC SMARC Evaluation Board Kit (RZ/G2LC-EVKIT) consists of a SMARC v2.1 module board and a carrier board.
+
+* Device: RZ/G2LC R9A07G044C22GBG
+
+  * Cortex-A55 Dual, Cortex-M33
+  * BGA361pin, 13mmSq body, 0.5mm pitch
+
+* SMARC v2.1 Module Board Functions
+
+  * DDR4 SDRAM: 1GB x 1pc
+  * QSPI flash memory: 512Mb x 1pc
+  * eMMC memory: 64GB x 1pc
+  * The microSD card slot is implemented and used as an eSD for boot
+  * 5-output clock oscillator `5P35023 <https://www.renesas.com/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator>`_ implemented
+  * PMIC power supply `RAA215300 <https://www.renesas.com/en/products/power-management/multi-channel-power-management-ics-pmics/raa215300-high-performance-9-channel-pmic-supporting-ddr-memory-built-charger-and-rtc>`_ implemented
+
+* Carrier Board Functions
+
+  * The FFC/FPC connector is mounted as standard for connection to high-speed serial interface for camera module.
+  * The Micro-HDMI connector via DSI/HDMI conversion module is mounted as standard for connection to high-speed serial interface for digital video module.
+  * The Micro-AB receptacle (ch0: USB2.0 OTG) and A receptacle (ch1: USB2.0 Host) are respectively mounted as standard for connection to USB interface.
+  * The RJ45 connector is mounted as standard for software development and evaluation using Ethernet.
+  * The audio codec is mounted as standard for advance development of audio system. The audio jack is implemented for connection to audio interface.
+  * The Micro-AB receptacles are implemented for connection to asynchronous serial port interface.
+  * The microSD card slot and two sockets for PMOD are implemented as an interface for peripheral functions.
+  * For power supply, a mounted USB Type-C receptacle supports the USB PD standard.
+
+Hardware
+********
+
+The Renesas RZ/G2LC MPU documentation can be found at `RZ/G2LC Group Website`_
+
+.. figure:: rzg2lc_block_diagram.webp
+	:width: 600px
+	:align: center
+	:alt: RZ/G2LC group feature
+
+	RZ/G2LC block diagram (Credit: Renesas Electronics Corporation)
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+Applications for the ``rzg2lc_smarc`` board can be built in the usual way as
+documented in :ref:`build_an_application`.
+
+Console
+=======
+
+The UART port for Cortex-M33 System Core can be accessed by connecting `Pmod USBUART <https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/>`_
+to the upper side of ``PMOD 1``.
+
+Debugging
+=========
+
+It is possible to load and execute a Zephyr application binary on
+this board on the Cortex-M33 System Core from
+the internal SRAM, using ``JLink`` debugger (:ref:`jlink-debug-host-tools`).
+
+Here is an example for building and debugging with the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rzg2lc_smarc/r9a07g044c22gbg/cm33
+   :goals: build debug
+
+Flashing
+========
+
+RZ/G2LC-EVKIT is designed to start different systems on different cores.
+It uses Yocto as the build system to build Linux system and boot loaders
+to run Zephyr on Cortex-M33 with u-boot. The minimal steps are described below.
+
+1. Follow "2.2 Building Images" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ to prepare the build environment.
+
+2. At step (4), follow step "2. Download Multi-OS Package" and "3. Add the layer for Multi-OS Package"
+   of "3.2 OpenAMP related stuff Integration for RZ/G2L, RZ/G2LC and RZ/G2UL" of `Release Note for RZ/G Multi-OS Package V2.0.2`_
+   to add the layer for Multi-OS Package.
+
+   .. code-block:: console
+
+      $ cd ~/rzg_vlp_<pkg ver>
+      $ unzip <Multi-OS Dir>/r01an5869ej0202-rzg-multi-os-pkg.zip
+      $ tar zxvf r01an5869ej0202-rzg-multi-os-pkg/meta-rz-features_multi-os_v2.0.2.tar.gz
+      $ bitbake-layers add-layer ../meta-rz-features/meta-rz-multi-os/meta-rzg2l
+
+3. Start the build:
+
+   .. code-block:: console
+
+      $ MACHINE=smarc-rzg2lc bitbake core-image-minimal
+
+   The below necessary artifacts will be located in the build/tmp/deploy/images
+
+   +---------------+------------------------------------------------------+
+   | Artifacts     | File name                                            |
+   +===============+======================================================+
+   | Boot loader   | bl2_bp-smarc-rzg2lc.srec                             |
+   |               |                                                      |
+   |               | fip-smarc-rzg2lc.srec                                |
+   +---------------+------------------------------------------------------+
+   | Flash Writer  | Flash_Writer_SCIF_RZG2LC_SMARC_DDR4_1GB_1PCS.mot     |
+   +---------------+------------------------------------------------------+
+
+4. Follow "4.2 Startup Procedure" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ for power supply and board setting
+   at SCIF download (SW11[1:4] = OFF, ON, OFF, ON) and (SW1[1:2] = ON, OFF)
+
+5. Follow "4.3 Download Flash Writer to RAM" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ to download Flash Writer to RAM
+
+6. Follow "4.4 Write the Bootloader" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ to write the boot loader
+   to the target board by using Flash Writer.
+
+7. Follow "4.5 Change Back to Normal Boot Mode" with switch setting (SW11[1:4] = OFF, OFF, OFF, ON) and (SW1[1:2] = ON, OFF)
+
+8. Follow "3. Preparing the SD Card" of `SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide`_ to write files to the microSD Card
+
+9. Copy zephyr.bin file to microSD card
+
+10. Follow "4.4.2 CM33 Sample Program Invocation with u-boot" from the beginning to step 4 of `Release Note for RZ/G Multi-OS Package V2.0.2`_
+
+11. Execute the commands stated below on the console to start zephyr application with CM33 core.
+    Here, ''N'' stands for the partition number in which you stored zephyr.bin file.
+
+   .. code-block:: console
+
+      Hit any key to stop autoboot: 2
+      => dcache off
+      => mmc dev 1
+      => fatload mmc 1:N 0x00010000 zephyr.bin
+      => fatload mmc 1:N 0x40010000 zephyr.bin
+      => cm33 start_normal 0x00010000 0x40010000
+      => dcache on
+
+References
+**********
+
+.. target-notes::
+
+.. _RZ/G2LC Group Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzg2lc-general-purpose-mcus-dual-core-arm-cortex-a55-12ghz-cpus-and-single-core-arm-cortex-m33-200mhz-cpu
+
+.. _RZG2LC-EVKIT Website:
+  https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzg2lc-evkit-evaluation-board-kit-rzg2lc-mpu
+
+.. _SMARC EVK of RZ/G2L, RZ/G2LC, RZ/G2UL Linux Start-up Guide:
+   https://www.renesas.com/en/document/gde/smarc-evk-rzg2l-rzg2lc-rzg2ul-linux-start-guide-rev105
+
+.. _Release Note for RZ/G Multi-OS Package V2.0.2:
+   https://www.renesas.com/us/en/document/rln/release-note-rzg-multi-os-package-v202
diff --git a/boards/renesas/rzg2lc_smarc/doc/rzg2lc_block_diagram.webp b/boards/renesas/rzg2lc_smarc/doc/rzg2lc_block_diagram.webp
new file mode 100644
index 00000000000..f5b97f75e8f
Binary files /dev/null and b/boards/renesas/rzg2lc_smarc/doc/rzg2lc_block_diagram.webp differ
diff --git a/boards/renesas/rzg2lc_smarc/doc/rzg2lc_smarc.webp b/boards/renesas/rzg2lc_smarc/doc/rzg2lc_smarc.webp
new file mode 100644
index 00000000000..e6abebed9f2
Binary files /dev/null and b/boards/renesas/rzg2lc_smarc/doc/rzg2lc_smarc.webp differ
diff --git a/boards/renesas/rzg2lc_smarc/rzg2lc_smarc-pinctrl.dtsi b/boards/renesas/rzg2lc_smarc/rzg2lc_smarc-pinctrl.dtsi
new file mode 100644
index 00000000000..ecae377d2a4
--- /dev/null
+++ b/boards/renesas/rzg2lc_smarc/rzg2lc_smarc-pinctrl.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg2-common.h>
+
+&pinctrl {
+	/omit-if-no-ref/ scif0_pins: scif0 {
+		scif0-pinmux {
+			pinmux = <RZG_PINMUX(PORT_38, 0, 1)>, /* TXD */
+				 <RZG_PINMUX(PORT_38, 1, 1)>; /* RXD */
+		};
+	};
+
+	/omit-if-no-ref/ scif1_pins: scif1 {
+		scif1-pinmux {
+			pinmux = <RZG_PINMUX(PORT_40, 0, 1)>, /* TXD */
+				 <RZG_PINMUX(PORT_40, 1, 1)>; /* RXD */
+		};
+	};
+};
diff --git a/boards/renesas/rzg2lc_smarc/rzg2lc_smarc_r9a07g044c22gbg_cm33.dts b/boards/renesas/rzg2lc_smarc/rzg2lc_smarc_r9a07g044c22gbg_cm33.dts
new file mode 100644
index 00000000000..87db249d6f8
--- /dev/null
+++ b/boards/renesas/rzg2lc_smarc/rzg2lc_smarc_r9a07g044c22gbg_cm33.dts
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <arm/renesas/rz/rzg/r9a07g044c.dtsi>
+#include "rzg2lc_smarc-pinctrl.dtsi"
+
+/ {
+	model = "Renesas RZ/G2LC SMARC";
+	compatible = "renesas,rzg2lc-smarc";
+
+	chosen {
+		zephyr,sram = &ddr;
+		zephyr,console = &scif1;
+		zephyr,shell-uart = &scif1;
+	};
+
+	ddr: memory@60010000 {
+		compatible = "mmio-sram";
+		reg = <0x60010000 DT_SIZE_M(46)>;
+	};
+};
+
+&scif1 {
+	current-speed = <115200>;
+	pinctrl-0 = <&scif1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/boards/renesas/rzg2lc_smarc/rzg2lc_smarc_r9a07g044c22gbg_cm33.yaml b/boards/renesas/rzg2lc_smarc/rzg2lc_smarc_r9a07g044c22gbg_cm33.yaml
new file mode 100644
index 00000000000..5d0aac9cdb1
--- /dev/null
+++ b/boards/renesas/rzg2lc_smarc/rzg2lc_smarc_r9a07g044c22gbg_cm33.yaml
@@ -0,0 +1,10 @@
+identifier: rzg2lc_smarc/r9a07g044c22gbg/cm33
+name: Cortex-M33 for Renesas RZ/G2LC SMARC
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - uart
+  - gpio
diff --git a/boards/renesas/rzg2lc_smarc/rzg2lc_smarc_r9a07g044c22gbg_cm33_defconfig b/boards/renesas/rzg2lc_smarc/rzg2lc_smarc_r9a07g044c22gbg_cm33_defconfig
new file mode 100644
index 00000000000..c9dd44d6c70
--- /dev/null
+++ b/boards/renesas/rzg2lc_smarc/rzg2lc_smarc_r9a07g044c22gbg_cm33_defconfig
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_XIP=n
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/renesas/rzg3s_smarc/doc/index.rst b/boards/renesas/rzg3s_smarc/doc/index.rst
index e442a836ee4..d69f9686e2c 100644
--- a/boards/renesas/rzg3s_smarc/doc/index.rst
+++ b/boards/renesas/rzg3s_smarc/doc/index.rst
@@ -48,6 +48,13 @@ The Renesas RZ/G3S MPU documentation can be found at `RZ/G3S Group Website`_
 
 	RZ/G3S block diagram (Credit: Renesas Electronics Corporation)
 
+Multi-OS processing
+*******************
+
+The RZ/G3S-EVKIT allows different applications to be executed in RZ/G3S SoC. With its multi-core architecture,
+each core can operate independently to perform customized tasks or exchange data using the OpenAMP framework.
+Please see :zephyr:code-sample:`rz-openamp-linux-zephyr` sample for reference.
+
 Supported Features
 ==================
 
@@ -63,16 +70,34 @@ and the following hardware features:
 +-----------+------------+-------------------------------------+
 | PINCTRL   | on-chip    | pinctrl                             |
 +-----------+------------+-------------------------------------+
+| ADC       | on-chip    | adc                                 |
++-----------+------------+-------------------------------------+
 | GPIO      | on-chip    | gpio                                |
 +-----------+------------+-------------------------------------+
+| DMA       | on-chip    | dma                                 |
++-----------+------------+-------------------------------------+
+| I2C       | on-chip    | i2c                                 |
++-----------+------------+-------------------------------------+
 | UART      | on-chip    | serial                              |
 +-----------+------------+-------------------------------------+
+| GTM       | on-chip    | counter                             |
++-----------+------------+-------------------------------------+
+| GPT       | on-chip    | pwm                                 |
++-----------+------------+-------------------------------------+
+| INTC      | on-chip    | external interrupt controller       |
++-----------+------------+-------------------------------------+
+| CLOCK     | on-chip    | clock control                       |
++-----------+------------+-------------------------------------+
+| MHU       | on-chip    | mbox                                |
++-----------+------------+-------------------------------------+
 
 Other hardware features are currently not supported by the port.
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 RZ/G3S-EVKIT is designed to start different systems on different cores.
 It uses Yocto as the build system to build Linux system and boot loaders
 to run BL2 TF-A on Cortex-A55 System Core before starting Zephyr. The minimal steps are described below.
@@ -219,6 +244,30 @@ version.
    :goals: build flash
    :compact:
 
+Troubleshooting
+===============
+
+Linux and Zephyr application should not share SoC HW resources otherwise it will cause HW corruption and unpredictable behavior.
+Therefore, HW resources assigned to Zephyr application must be disabled in Linux.
+
+The below patch shows how to prevent Linux from configuring SCIF1 which is used by Zephyr.
+
+.. code-block:: diff
+
+    diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
+    index f01801b18e8a..d9f9a0a2bb08 100644
+    --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
+    +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi
+    @@ -347,7 +347,7 @@ &scif1 {
+            pinctrl-0 = <&scif1_pins>;
+            pinctrl-names = "default";
+            uart-has-rtscts;
+    -       status = "okay";
+    +       status = "disabled";
+    };
+    #elif SPDIF_SEL == SW_ON
+    &spdif {
+
 References
 **********
 
diff --git a/boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi b/boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi
index aa8ae25d057..72a243947cd 100644
--- a/boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi
+++ b/boards/renesas/rzg3s_smarc/rzg3s_smarc-pinctrl.dtsi
@@ -35,4 +35,24 @@
 				 <RZG_PINMUX(PORT_15, 2, 6)>; /* TXD */
 		};
 	};
+
+	/omit-if-no-ref/ gpt0_pins: gpt0 {
+		gpt0-pinmux {
+			pinmux = <RZG_PINMUX(PORT_13, 0, 2)>, /* GTIOCA */
+				 <RZG_PINMUX(PORT_13, 1, 2)>; /* GTIOCB */
+		};
+	};
+
+	/omit-if-no-ref/ gpt3_pins: gpt3 {
+		gpt3-pinmux {
+			pinmux = <RZG_PINMUX(PORT_18, 0, 7)>, /* GTIOCA */
+				 <RZG_PINMUX(PORT_18, 1, 7)>; /* GTIOCB */
+		};
+	};
+
+	/omit-if-no-ref/ gpt6_pins: gpt6 {
+		gpt6-pinmux {
+			pinmux = <RZG_PINMUX(PORT_13, 4, 7)>; /* GTIOCA */
+		};
+	};
 };
diff --git a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts
index 81210407ae4..1f2bd49c9b9 100644
--- a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts
+++ b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.dts
@@ -90,3 +90,7 @@
 &gpio18{
 	status = "okay";
 };
+
+&adc {
+	status = "okay";
+};
diff --git a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml
index 06285a945de..ad2a7687a93 100644
--- a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml
+++ b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33.yaml
@@ -6,5 +6,10 @@ toolchain:
   - zephyr
   - gnuarmemb
 supported:
+  - adc
   - uart
+  - dma
+  - i2c
   - gpio
+  - counter
+  - pwm
diff --git a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33_defconfig b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33_defconfig
index b06a719875e..90a8ce52189 100644
--- a/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33_defconfig
+++ b/boards/renesas/rzg3s_smarc/rzg3s_smarc_r9a08g045s33gbg_cm33_defconfig
@@ -8,5 +8,5 @@ CONFIG_XIP=n
 CONFIG_SERIAL=y
 
 # Enable console
-CONFIG_CONSOLE=ys
+CONFIG_CONSOLE=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/renesas/rzn2l_rsk/Kconfig.rzn2l_rsk b/boards/renesas/rzn2l_rsk/Kconfig.rzn2l_rsk
new file mode 100644
index 00000000000..b4c2eef0c20
--- /dev/null
+++ b/boards/renesas/rzn2l_rsk/Kconfig.rzn2l_rsk
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RZN2L_RSK
+	select SOC_R9A07G084M04GBG
diff --git a/boards/renesas/rzn2l_rsk/board.cmake b/boards/renesas/rzn2l_rsk/board.cmake
new file mode 100644
index 00000000000..201aa741e4a
--- /dev/null
+++ b/boards/renesas/rzn2l_rsk/board.cmake
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R9A07G084M04GBG")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/rzn2l_rsk/board.yml b/boards/renesas/rzn2l_rsk/board.yml
new file mode 100644
index 00000000000..c4b44f17523
--- /dev/null
+++ b/boards/renesas/rzn2l_rsk/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: rzn2l_rsk
+  full_name: Renesas Starter Kit+ for RZ/N2L
+  vendor: renesas
+  socs:
+  - name: r9a07g084m04gbg
diff --git a/boards/renesas/rzn2l_rsk/doc/index.rst b/boards/renesas/rzn2l_rsk/doc/index.rst
new file mode 100644
index 00000000000..99ebe79943b
--- /dev/null
+++ b/boards/renesas/rzn2l_rsk/doc/index.rst
@@ -0,0 +1,117 @@
+.. zephyr:board:: rzn2l_rsk
+
+Overview
+********
+
+Renesas Starter Kit+ for RZ/N2L is for evaluation or development using the RZ/N2L MPU.
+With the on-board emulator, you can start evaluation by simply connecting the bundled cable with
+your PC. This product has rich functional ICs such as Gigabit Ethernet PHY and Octal Flash,
+you can fully evaluate functions without an extension board.
+
+* On-board RZ/N2L MPU 225-pin (R9A07G084M04GBG)
+* Rich functional ICs such as Gigabit Ethernet PHY and Octal Flash are mounted,
+  so functions of target MPU can be fully evaluated
+* Generic interfaces such as Pmod/Grove/Qwiic/mikroBUS
+* Pin headers for external extension enable you to evaluate many use cases
+* Emulator circuit is mounted, and program debugging can be started by simply connecting USB cable
+  to PC (two USB cables are included, one for emulator and the other for power supply)
+* On-board memory components:
+
+  * SDRAM (256MBit)
+  * NOR Flash (256MBit)
+  * Octa Flash (512MBit)
+  * HyperRAM (64Mbit)
+  * QSPI Serial Flash (512Mbit)
+  * I2C EEPROM (32Kbit)
+
+* Communication interfaces include:
+
+  * Debug interfaces (J-Link OB, MIPI-10, MIPI-20)
+  * Ethernet
+  * CAN
+  * USB
+  * RS485
+  * UART
+  * I2C
+  * SPI
+
+Hardware
+********
+
+The Renesas RZ/N2L MPU documentation can be found at `RZ/N2L Group Website`_
+
+.. figure:: rzn2l_block_diagram.webp
+	:width: 500px
+	:align: center
+	:alt: RZ/N2L group feature
+
+	RZ/N2L block diagram (Credit: Renesas Electronics Corporation)
+
+Detailed hardware features for the board can be found at `RZ/N2L-RSK Website`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+By default, the board is configured for use with:
+
+* UART0 connected to the USB serial port (pins H15, G11),
+* UART3 connected to the PMOD Header (J25, pins E14, E15),
+* LEDs defined as ``led0``, ``led1``, ``led2`` and ``led3``,
+
+The Zephyr console uses UART0.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``rzn2l_rsk`` board can be
+built, flashed, and debugged in the usual way. See :ref:`build_an_application`
+and :ref:`application_run` for more details on building and running.
+
+To use J-Link OB on RSK+RZN2L,
+
+1. Open the jumper pin (J9) for switching the debug connection.
+
+2. Connect the micro-USB type-B to J-Link OB USB connector (J10), and then the LED4 is lighted.
+
+Console
+=======
+
+The UART port is accessed by USB-Serial port (CN16).
+
+Debugging
+=========
+
+Here is an example for building and debugging with the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rzn2l_rsk
+   :goals: build debug
+
+Flashing
+=========
+
+Before using ``flash`` command, the board must be set to xSPI boot mode.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rzn2l_rsk
+   :goals: build flash
+
+References
+**********
+
+.. target-notes::
+
+.. _RZ/N2L Group Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzn2l-integrated-tsn-compliant-3-port-gigabit-ethernet-switch-enables-various-industrial-applications
+
+.. _RZ/N2L-RSK Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzn2l-rsk-renesas-starter-kit-rzn2l
diff --git a/boards/renesas/rzn2l_rsk/doc/rzn2l_block_diagram.webp b/boards/renesas/rzn2l_rsk/doc/rzn2l_block_diagram.webp
new file mode 100644
index 00000000000..215211d9b8e
Binary files /dev/null and b/boards/renesas/rzn2l_rsk/doc/rzn2l_block_diagram.webp differ
diff --git a/boards/renesas/rzn2l_rsk/doc/rzn2l_rsk.webp b/boards/renesas/rzn2l_rsk/doc/rzn2l_rsk.webp
new file mode 100644
index 00000000000..a5ef4679e5a
Binary files /dev/null and b/boards/renesas/rzn2l_rsk/doc/rzn2l_rsk.webp differ
diff --git a/boards/renesas/rzn2l_rsk/rzn2l_rsk-pinctrl.dtsi b/boards/renesas/rzn2l_rsk/rzn2l_rsk-pinctrl.dtsi
new file mode 100644
index 00000000000..ab95fd84a7e
--- /dev/null
+++ b/boards/renesas/rzn2l_rsk/rzn2l_rsk-pinctrl.dtsi
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzn-common.h>
+
+&pinctrl {
+	/omit-if-no-ref/ sci0_default: sci0_default {
+		sci0-pinmux {
+			pinmux = <RZN_PINMUX(PORT_16, 5, 1)>, /* TXD */
+				 <RZN_PINMUX(PORT_16, 6, 2)>; /* RXD */
+		};
+	};
+
+	/omit-if-no-ref/ sci3_default: sci3_default {
+		sci3-pinmux {
+			pinmux = <RZN_PINMUX(PORT_18, 0, 4)>, /* TXD */
+				 <RZN_PINMUX(PORT_17, 7, 4)>; /* RXD */
+		};
+	};
+
+	/omit-if-no-ref/ irq7_default: irq7_default {
+		irq7-pinmux {
+			pinmux = <RZN_PINMUX(PORT_16, 3, 0)>;
+			input-enable;
+		};
+	};
+};
diff --git a/boards/renesas/rzn2l_rsk/rzn2l_rsk.dts b/boards/renesas/rzn2l_rsk/rzn2l_rsk.dts
new file mode 100644
index 00000000000..9ba2003c646
--- /dev/null
+++ b/boards/renesas/rzn2l_rsk/rzn2l_rsk.dts
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <arm/renesas/rz/rzn/r9a07g084.dtsi>
+#include "rzn2l_rsk-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "Renesas Starter Kit+ for RZ/N2L";
+	compatible = "renesas,rzn2l-rsk";
+
+	chosen {
+		zephyr,sram = &atcm;
+		zephyr,flash = &xspi0_cs0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		sw0 = &sw1;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led0 {
+			gpios = <&gpio18 2 0>;
+			label = "led0";
+		};
+
+		led1: led1 {
+			gpios = <&gpio22 3 0>;
+			label = "led1";
+		};
+
+		led2: led2 {
+			gpios = <&gpio4 1 0>;
+			label = "led2";
+		};
+
+		led3: led3 {
+			gpios = <&gpio17 3 0>;
+			label = "led3";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		sw1: sw1 {
+			label = "sw1";
+			gpios = <&gpio16 3 0>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		sw2: sw2 {
+			label = "sw2";
+			gpios = <&gpio5 4 0>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+};
+
+&sci0 {
+	pinctrl-0 = <&sci0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	uart0: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
+
+&gpio18 {
+	status = "okay";
+};
+
+&gpio22 {
+	status = "okay";
+};
+
+&gpio4 {
+	status = "okay";
+};
+
+&gpio17 {
+	status = "okay";
+};
+
+&irq7 {
+	trigger-type = "falling";
+	pinctrl-0 = <&irq7_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&gpio16 {
+	irqs = <3 7>;
+	status = "okay";
+};
+
+&gpio5 {
+	status = "okay";
+};
diff --git a/boards/renesas/rzn2l_rsk/rzn2l_rsk.yaml b/boards/renesas/rzn2l_rsk/rzn2l_rsk.yaml
new file mode 100644
index 00000000000..196b812a193
--- /dev/null
+++ b/boards/renesas/rzn2l_rsk/rzn2l_rsk.yaml
@@ -0,0 +1,10 @@
+identifier: rzn2l_rsk
+name: Renesas Starter Kit+ for RZ/N2L
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+supported:
+  - uart
+  - gpio
+vendor: renesas
diff --git a/boards/renesas/rzn2l_rsk/rzn2l_rsk_defconfig b/boards/renesas/rzn2l_rsk/rzn2l_rsk_defconfig
new file mode 100644
index 00000000000..11b00aa34ef
--- /dev/null
+++ b/boards/renesas/rzn2l_rsk/rzn2l_rsk_defconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_XIP=n
+
+# Enable UART driver
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
diff --git a/boards/renesas/rzt2l_rsk/Kconfig.rzt2l_rsk b/boards/renesas/rzt2l_rsk/Kconfig.rzt2l_rsk
new file mode 100644
index 00000000000..2da42ee1781
--- /dev/null
+++ b/boards/renesas/rzt2l_rsk/Kconfig.rzt2l_rsk
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RZT2L_RSK
+	select SOC_R9A07G074M04GBG
diff --git a/boards/renesas/rzt2l_rsk/board.cmake b/boards/renesas/rzt2l_rsk/board.cmake
new file mode 100644
index 00000000000..75c233c25d0
--- /dev/null
+++ b/boards/renesas/rzt2l_rsk/board.cmake
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R9A07G074M04")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/rzt2l_rsk/board.yml b/boards/renesas/rzt2l_rsk/board.yml
new file mode 100644
index 00000000000..d0bf007cf7b
--- /dev/null
+++ b/boards/renesas/rzt2l_rsk/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: rzt2l_rsk
+  full_name: Renesas Starter Kit+ for RZ/T2L
+  vendor: renesas
+  socs:
+  - name: r9a07g074m04gbg
diff --git a/boards/renesas/rzt2l_rsk/doc/index.rst b/boards/renesas/rzt2l_rsk/doc/index.rst
new file mode 100644
index 00000000000..17cc1f61dd5
--- /dev/null
+++ b/boards/renesas/rzt2l_rsk/doc/index.rst
@@ -0,0 +1,115 @@
+.. zephyr:board:: rzt2l_rsk
+
+Overview
+********
+
+Renesas Starter Kit+ for RZ/T2L is an evaluation and development kit for the RZ/T2L MPU.
+By simply connecting the bundled cable to your PC, you can immediately start evaluation through an
+on-board emulator. This product contains rich functional ICs such as Gigabit Ethernet PHY and
+Octal Flash so you can evaluate various functions of the RZ/T2L without an extension board.
+
+* On-board RZ/T2L MPU 196-pin (R9A07G074M04GBG)
+* Rich functional ICs such as Gigabit Ethernet PHY and Octal Flash
+  so you can evaluate various functions of the RZ/T2L without an extension board
+* Generic interfaces such as Pmod/Grove/QWIIC/mikroBUS
+* Pin headers for external extension enable you to evaluate many use cases
+* Emulator circuit is mounted, and program debugging can be started by simply connecting USB cable
+  to PC (two USB cables are included, one for emulator and the other for power supply)
+* On-board memory components:
+
+  * Octa Flash (512MBit)
+  * HyperRAM (64Mbit)
+  * QSPI Serial Flash (128Mbit)
+  * I2C EEPROM (16Kbit)
+
+* Communication interfaces include:
+
+  * Debug interfaces (J-Link OB, MIPI-10, MIPI-20, Mictor-38)
+  * Ethernet
+  * CAN
+  * USB
+  * RS485
+  * UART
+  * I2C
+  * SPI
+
+Hardware
+********
+
+The Renesas RZ/T2L MPU documentation can be found at `RZ/T2L Group Website`_
+
+.. figure:: rzt2l_block_diagram.webp
+	:width: 500px
+	:align: center
+	:alt: RZ/T2L group feature
+
+	RZ/T2L block diagram (Credit: Renesas Electronics Corporation)
+
+Detailed hardware features for the board can be found at `RZ/T2L-RSK Website`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+By default, the board is configured for use with:
+
+* UART0 connected to the USB serial port (pins G12, G11),
+* UART2 connected to the PMOD Header (J25, pins M1, L2),
+* LEDs defined as ``led1`` and ``led3``,
+
+The Zephyr console uses UART0.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``rzt2l_rsk`` board can be
+built, flashed, and debugged in the usual way. See :ref:`build_an_application`
+and :ref:`application_run` for more details on building and running.
+
+To use J-Link OB on RSK+RZT2L,
+
+1. Open the jumper pin (J9) for switching the debug connection.
+
+2. Connect the micro-USB type-B to J-Link OB USB connector (J10), and then the LED6 is lighted.
+
+Console
+=======
+
+The UART port is accessed by USB-Serial port (CN16).
+
+Debugging
+=========
+
+Here is an example for building and debugging with the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rzt2l_rsk
+   :goals: build debug
+
+Flashing
+=========
+
+Before using ``flash`` command, the board must be set to xSPI1 boot mode.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rzt2l_rsk
+   :goals: build flash
+
+References
+**********
+
+.. target-notes::
+
+.. _RZ/T2L Group Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzt2l-high-performance-mpu-realizing-high-speed-and-high-precision-real-time-control-ethercat
+
+.. _RZ/T2L-RSK Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzt2l-rsk-renesas-starter-kit-rzt2l
diff --git a/boards/renesas/rzt2l_rsk/doc/rzt2l_block_diagram.webp b/boards/renesas/rzt2l_rsk/doc/rzt2l_block_diagram.webp
new file mode 100644
index 00000000000..ec5cc0be48a
Binary files /dev/null and b/boards/renesas/rzt2l_rsk/doc/rzt2l_block_diagram.webp differ
diff --git a/boards/renesas/rzt2l_rsk/doc/rzt2l_rsk.webp b/boards/renesas/rzt2l_rsk/doc/rzt2l_rsk.webp
new file mode 100644
index 00000000000..8f2df8c90d2
Binary files /dev/null and b/boards/renesas/rzt2l_rsk/doc/rzt2l_rsk.webp differ
diff --git a/boards/renesas/rzt2l_rsk/rzt2l_rsk-pinctrl.dtsi b/boards/renesas/rzt2l_rsk/rzt2l_rsk-pinctrl.dtsi
new file mode 100644
index 00000000000..4f63c4a8367
--- /dev/null
+++ b/boards/renesas/rzt2l_rsk/rzt2l_rsk-pinctrl.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzt-common.h>
+
+&pinctrl {
+	/omit-if-no-ref/ sci0_default: sci0_default {
+		sci0-pinmux {
+			pinmux = <RZT_PINMUX(PORT_16, 0, 2)>, /* TXD */
+				 <RZT_PINMUX(PORT_16, 1, 3)>; /* RXD */
+		};
+	};
+
+	/omit-if-no-ref/ irq7_default: irq7_default {
+		irq7-pinmux {
+			pinmux = <RZT_PINMUX(PORT_16, 3, 0)>;
+			input-enable;
+		};
+	};
+};
diff --git a/boards/renesas/rzt2l_rsk/rzt2l_rsk.dts b/boards/renesas/rzt2l_rsk/rzt2l_rsk.dts
new file mode 100644
index 00000000000..00fe010130d
--- /dev/null
+++ b/boards/renesas/rzt2l_rsk/rzt2l_rsk.dts
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <arm/renesas/rz/rzt/r9a07g074.dtsi>
+#include <freq.h>
+#include "rzt2l_rsk-pinctrl.dtsi"
+
+/ {
+	model = "Renesas Starter Kit+ for RZ/T2L";
+	compatible = "renesas,rzt2l-rsk";
+
+	chosen {
+		zephyr,sram = &atcm;
+		zephyr,flash = &xspi1_cs0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+
+	aliases {
+		led0 = &led1;
+		sw0 = &sw2;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1: led1 {
+			gpios = <&gpio17 6 0>;
+			label = "led1";
+		};
+
+		led3: led3 {
+			gpios = <&gpio18 1 0>;
+			label = "led3";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		sw1: sw1 {
+			label = "sw1";
+			gpios = <&gpio14 2 0>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		sw2: sw2 {
+			label = "sw2";
+			gpios = <&gpio16 3 0>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+};
+
+&sci0 {
+	pinctrl-0 = <&sci0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	uart0: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
+
+&gpio14 {
+	status = "okay";
+};
+
+&gpio16 {
+	irqs = <3 7>;
+	status = "okay";
+};
+
+&gpio17 {
+	status = "okay";
+};
+
+&gpio18 {
+	status = "okay";
+};
+
+&irq7 {
+	trigger-type = "falling";
+	pinctrl-0 = <&irq7_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/boards/renesas/rzt2l_rsk/rzt2l_rsk.yaml b/boards/renesas/rzt2l_rsk/rzt2l_rsk.yaml
new file mode 100644
index 00000000000..6bfd1397438
--- /dev/null
+++ b/boards/renesas/rzt2l_rsk/rzt2l_rsk.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: rzt2l_rsk
+name: Renesas Starter Kit+ for RZ/T2L
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+supported:
+  - uart
+  - gpio
+vendor: renesas
diff --git a/boards/renesas/rzt2l_rsk/rzt2l_rsk_defconfig b/boards/renesas/rzt2l_rsk/rzt2l_rsk_defconfig
new file mode 100644
index 00000000000..11b00aa34ef
--- /dev/null
+++ b/boards/renesas/rzt2l_rsk/rzt2l_rsk_defconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_XIP=n
+
+# Enable UART driver
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
diff --git a/boards/renesas/rzt2m_rsk/Kconfig.rzt2m_rsk b/boards/renesas/rzt2m_rsk/Kconfig.rzt2m_rsk
new file mode 100644
index 00000000000..42c03c3b5bd
--- /dev/null
+++ b/boards/renesas/rzt2m_rsk/Kconfig.rzt2m_rsk
@@ -0,0 +1,6 @@
+# Copyright (c) 2023 Nordic Semiconductor ASA
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RZT2M_RSK
+	select SOC_R9A07G075M24GBG
diff --git a/boards/renesas/rzt2m_starterkit/board.cmake b/boards/renesas/rzt2m_rsk/board.cmake
similarity index 100%
rename from boards/renesas/rzt2m_starterkit/board.cmake
rename to boards/renesas/rzt2m_rsk/board.cmake
diff --git a/boards/renesas/rzt2m_rsk/board.yml b/boards/renesas/rzt2m_rsk/board.yml
new file mode 100644
index 00000000000..2ef8c0a005e
--- /dev/null
+++ b/boards/renesas/rzt2m_rsk/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: rzt2m_rsk
+  full_name: Renesas Starter Kit+ for RZ/T2M
+  vendor: renesas
+  socs:
+  - name: r9a07g075m24gbg
diff --git a/boards/renesas/rzt2m_rsk/doc/index.rst b/boards/renesas/rzt2m_rsk/doc/index.rst
new file mode 100644
index 00000000000..4beff6866a4
--- /dev/null
+++ b/boards/renesas/rzt2m_rsk/doc/index.rst
@@ -0,0 +1,106 @@
+.. zephyr:board:: rzt2m_rsk
+
+Overview
+********
+
+The Renesas Starter Kit+ for RZ/T2M is an evaluation and development kit for the RZ/T2M MPU.
+The board is powered through a 5V input via a DC Power Jack or USB Type-C Connector.
+
+* On-board RZ/T2M MPU 320-pin (R9A07G075M24GBG)
+* Rich functional ICs such as Gigabit Ethernet PHY and Octal Flash are mounted,
+  functions of target MPU can be fully evaluated
+* Generic interface such as Pmod/Grove/QWIIC/mikroBUS
+* The pin header enables users to freely combine with the user's hardware system and evaluate RZ/T2M
+* Emulator circuit is mounted, can start program debugging by simply connecting USB cable
+  to PC (two USB cables are bundled: one for emulator, and the other for power supply)
+* On-board memory components:
+
+  * SDRAM (256MBit)
+  * NOR Flash (256MBit)
+  * Octa Flash (512MBit)
+  * HyperRAM (512Mbit)
+  * QSPI Serial Flash (512Mbit)
+  * I2C EEPROM (32Kbit)
+
+* Communication interfaces include:
+
+  * Debug interfaces (J-Link OB, MIPI-10, MIPI-20)
+  * Ethernet
+  * CAN
+  * USB
+  * RS485
+  * UART
+  * I2C
+  * SPI
+
+Hardware
+********
+
+The Renesas RZ/T2M MPU documentation can be found at `RZT2M Product page`_
+
+.. figure:: rzt2m_block_diagram.webp
+	:width: 500px
+	:align: center
+	:alt: RZ/T2M group feature
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+By default, the board is configured for use with:
+
+* UART0 connected to the USB serial port (pins K18, K19),
+* UART3 connected to the PMOD Header (J25, pins H16, G20),
+* LEDs defined as ``led0``, ``led1``, ``led2`` and ``led3``,
+
+The Zephyr console uses UART0.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``rzt2m_rsk`` board can be built in the usual way as
+documented in :ref:`build_an_application`.
+
+To use J-Link OB on RSK+RZT2M,
+
+1. Open the jumper pin (J9) for switching the debug connection.
+
+2. Connect the micro-USB type-B to J-Link OB USB connector (J10), and then the LED4 is lighted.
+
+Console
+=======
+
+The UART port is accessed by USB-Serial port (CN16).
+
+Debugging
+=========
+
+Here is an example for building and debugging with the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rzt2m_rsk/r9a07g075m24gbg/cr520
+   :goals: build debug
+
+Flashing
+=========
+
+Before using ``flash`` command, the board must be set to xSPI boot mode.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rzt2m_rsk/r9a07g075m24gbg/cr520
+   :goals: build flash
+
+References
+**********
+
+.. target-notes::
+
+.. _RZT2M Product page: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzt2m-high-performance-multi-function-mpu-realizing-high-speed-processing-and-high-precision-control
diff --git a/boards/renesas/rzt2m_rsk/doc/rzt2m_block_diagram.webp b/boards/renesas/rzt2m_rsk/doc/rzt2m_block_diagram.webp
new file mode 100644
index 00000000000..7e2f23eb51a
Binary files /dev/null and b/boards/renesas/rzt2m_rsk/doc/rzt2m_block_diagram.webp differ
diff --git a/boards/renesas/rzt2m_rsk/doc/rzt2m_rsk.webp b/boards/renesas/rzt2m_rsk/doc/rzt2m_rsk.webp
new file mode 100644
index 00000000000..85510da36e4
Binary files /dev/null and b/boards/renesas/rzt2m_rsk/doc/rzt2m_rsk.webp differ
diff --git a/boards/renesas/rzt2m_starterkit/doc/rzt2m_starterkit.png b/boards/renesas/rzt2m_rsk/doc/rzt2m_starterkit.png
similarity index 100%
rename from boards/renesas/rzt2m_starterkit/doc/rzt2m_starterkit.png
rename to boards/renesas/rzt2m_rsk/doc/rzt2m_starterkit.png
diff --git a/boards/renesas/rzt2m_rsk/rzt2m_rsk-pinctrl.dtsi b/boards/renesas/rzt2m_rsk/rzt2m_rsk-pinctrl.dtsi
new file mode 100644
index 00000000000..3bb24fd431b
--- /dev/null
+++ b/boards/renesas/rzt2m_rsk/rzt2m_rsk-pinctrl.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzt-common.h>
+
+&pinctrl {
+	/omit-if-no-ref/ sci0_default: sci0_default {
+		sci0-pinmux {
+			pinmux = <RZT_PINMUX(PORT_16, 5, 1)>, /* TXD */
+				 <RZT_PINMUX(PORT_16, 6, 2)>; /* RXD */
+		};
+	};
+
+	/omit-if-no-ref/ irq2_default: irq2_default{
+		irq2-pinmux{
+			pinmux = <RZT_PINMUX(PORT_10, 5, 0)>;
+			input-enable;
+		};
+	};
+};
diff --git a/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.dts b/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.dts
new file mode 100644
index 00000000000..18e5b7ddf90
--- /dev/null
+++ b/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.dts
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <arm/renesas/rz/rzt/r9a07g075.dtsi>
+#include "rzt2m_rsk-pinctrl.dtsi"
+
+/ {
+	model = "Renesas Starter Kit+ for RZ/T2M";
+	compatible = "renesas,rzt2m-rsk";
+
+	chosen {
+		zephyr,sram = &cpu0_atcm;
+		zephyr,flash = &xspi0_cs0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+
+	aliases {
+		led0 = &led0;
+		sw0 = &sw1;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led0 {
+			gpios = <&gpio19 6 0>;
+			label = "led0";
+		};
+
+		led1: led1 {
+			gpios = <&gpio19 4 0>;
+			label = "led1";
+		};
+
+		led2: led2 {
+			gpios = <&gpio20 0 0>;
+			label = "led2";
+		};
+
+		led3: led3 {
+			gpios = <&gpio23 4 0>;
+			label = "led3";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		sw1: sw1 {
+			label = "sw1";
+			gpios = <&gpio10 5 0>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		sw2: sw2 {
+			label = "sw2";
+			gpios = <&gpio16 3 0>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+};
+
+&sci0 {
+	pinctrl-0 = <&sci0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	uart0: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
+
+&irq2 {
+	trigger-type = "falling";
+	pinctrl-0 = <&irq2_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&gpio10 {
+	irqs = <5 2>;
+	status = "okay";
+};
+
+&gpio16 {
+	status = "okay";
+};
+
+&gpio19 {
+	status = "okay";
+};
+
+&gpio20 {
+	status = "okay";
+};
+
+&gpio23 {
+	status = "okay";
+};
diff --git a/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.yaml b/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.yaml
new file mode 100644
index 00000000000..2fbd50880f0
--- /dev/null
+++ b/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: rzt2m_rsk/r9a07g075m24gbg/cr520
+name: Renesas Starter Kit+ for RZ/T2M
+type: mcu
+arch: arm
+ram: 2048
+toolchain:
+  - zephyr
+supported:
+  - uart
+  - gpio
+vendor: renesas
diff --git a/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520_defconfig b/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520_defconfig
new file mode 100644
index 00000000000..6d9ab2f7679
--- /dev/null
+++ b/boards/renesas/rzt2m_rsk/rzt2m_rsk_r9a07g075m24gbg_cr520_defconfig
@@ -0,0 +1,13 @@
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_XIP=n
+
+# Enable UART driver
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
diff --git a/boards/renesas/rzt2m_starterkit/Kconfig.rzt2m_starter_kit b/boards/renesas/rzt2m_starterkit/Kconfig.rzt2m_starter_kit
deleted file mode 100644
index 83f98b5c90b..00000000000
--- a/boards/renesas/rzt2m_starterkit/Kconfig.rzt2m_starter_kit
+++ /dev/null
@@ -1,6 +0,0 @@
-# Copyright (c) 2023 Nordic Semiconductor ASA
-
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_RZT2M_STARTER_KIT
-	select SOC_RENESAS_RZT2M
diff --git a/boards/renesas/rzt2m_starterkit/board.yml b/boards/renesas/rzt2m_starterkit/board.yml
deleted file mode 100644
index 21be12a29b2..00000000000
--- a/boards/renesas/rzt2m_starterkit/board.yml
+++ /dev/null
@@ -1,6 +0,0 @@
-board:
-  name: rzt2m_starter_kit
-  full_name: Starter Kit+ for RZ/T2M
-  vendor: renesas
-  socs:
-  - name: renesas_rzt2m
diff --git a/boards/renesas/rzt2m_starterkit/doc/index.rst b/boards/renesas/rzt2m_starterkit/doc/index.rst
deleted file mode 100644
index 69f6c532700..00000000000
--- a/boards/renesas/rzt2m_starterkit/doc/index.rst
+++ /dev/null
@@ -1,100 +0,0 @@
-.. _rzt2m_starterkit:
-
-Renesas Starter Kit+ for RZ/T2M
-###############################
-
-Overview
-********
-
-The Renesas Starter Kit+ for RZ/T2M is an evaluation and development kit for the RZ/T2M MPU.
-The board is powered through a 5V input via a DC Power Jack or USB Type-C Connector.
-
-.. figure:: rzt2m_starterkit.png
-   :width: 800px
-   :align: center
-   :alt: Starter Kit+ for RZ/T2M
-
-   Starter Kit+ for RZ/T2M (Credit: Renesas)
-
-Hardware
-********
-
-The board utilizes the SoC of part no. R9A07G075M24GBG, with 2MB of RAM.
-
-It has several on-board memory components:
-
-* SDRAM (256MBit),
-* NOR Flash (256MBit),
-* Octa Flash (512MBit),
-* HyperRAM (512Mbit),
-* QSPI Serial Flash (512Mbit),
-* I2C EEPROM (32Kbit).
-
-The communication interfaces include:
-
-* Debug interfaces (J-Link, MIPI-10, MIPI-20),
-* Ethernet,
-* CAN,
-* USB,
-* RS485,
-* UART,
-* I2C,
-* SPI.
-
-Supported Features
-==================
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINCTRL   | on-chip    | pinctrl                             |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by the port.
-
-Connections and IOs
-===================
-
-By default, the board is configured for use with:
-
-* UART0 connected to the USB serial port (pins K18, K19),
-* UART3 connected to the PMOD Header (J25, pins H16, G20),
-* LEDs defined as ``led0``, ``led1``, ``led2`` and ``led3``,
-
-The Zephyr console uses UART0.
-
-Programming and Debugging
-*************************
-
-Debugging
-=========
-
-Connect to the board using the J-Link On-board USB connector.
-Use ``west`` to start the debug server:
-
-.. code-block:: console
-
-    west debugserver
-
-Connect GDB to the server and load an application:
-
-.. code-block::
-
-    target remote :2331
-    file build/zephyr/zephyr.elf
-    load
-
-References
-**********
-
-.. target-notes::
-
-.. _RZT2M Product page: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzt2m-high-performance-multi-function-mpu-realizing-high-speed-processing-and-high-precision-control
diff --git a/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit.yaml b/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit.yaml
deleted file mode 100644
index 5d091d0fddb..00000000000
--- a/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit.yaml
+++ /dev/null
@@ -1,15 +0,0 @@
-# Copyright (c) 2023 Antmicro <www.antmicro.com>
-# SPDX-License-Identifier: Apache-2.0
-
-identifier: rzt2m_starter_kit
-name: Renesas RZ/T2M Starter Kit+
-type: mcu
-arch: arm
-ram: 2048
-toolchain:
-  - zephyr
-supported:
-  - counter
-  - uart
-  - gpio
-vendor: renesas
diff --git a/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m.dts b/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m.dts
deleted file mode 100644
index 717c21c0cda..00000000000
--- a/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m.dts
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright (c) 2023 Antmicro <www.antmicro.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/dts-v1/;
-#include <dt-bindings/pinctrl/renesas-rzt2m-pinctrl.h>
-#include <arm/renesas/rz/rzt2m.dtsi>
-#include <zephyr/dt-bindings/input/input-event-codes.h>
-
-/ {
-	model = "RZT/2M Starter Kit";
-	compatible = "renesas,rzt2m_starter_kit";
-
-	chosen {
-		zephyr,sram = &cpu0_atcm;
-		zephyr,console = &uart0;
-		zephyr,shell-uart = &uart0;
-	};
-
-	aliases {
-		led0 = &led0;
-		sw0 = &sw1;
-	};
-
-	leds {
-		compatible = "gpio-leds";
-		led0: led0 {
-			gpios = <&gpio19 6 0>;
-			label = "led0";
-		};
-		led1: led1 {
-			gpios = <&gpio19 4 0>;
-			label = "led1";
-		};
-		led2: led2 {
-			gpios = <&gpio20 0 0>;
-			label = "led2";
-		};
-		led3: led3 {
-			gpios = <&gpio23 4 0>;
-			label = "led3";
-		};
-	};
-
-	gpio_keys {
-		compatible = "gpio-keys";
-		sw1: sw1 {
-			label = "sw1";
-			gpios = <&gpio10 5 0>;
-			zephyr,code = <INPUT_KEY_0>;
-		};
-		sw2: sw2 {
-			label = "sw2";
-			gpios = <&gpio16 3 0>;
-			zephyr,code = <INPUT_KEY_1>;
-		};
-	};
-};
-
-
-&pinctrl {
-	uart0_default: uart0_default {
-		group1 {
-			pinmux = <UART0TX_P16_5>;
-		};
-		group2 {
-			pinmux = <UART0RX_P16_6>;
-			input-enable;
-		};
-	};
-	uart3_default: uart3_default {
-		group1 {
-			pinmux = <UART3TX_P18_0>;
-		};
-		group2 {
-			pinmux = <UART3RX_P17_7>;
-			input-enable;
-		};
-	};
-};
-
-&uart0 {
-	status = "okay";
-	pinctrl-0 = <&uart0_default>;
-	pinctrl-names = "default";
-};
-
-&uart3 {
-	status = "okay";
-	pinctrl-0 = <&uart3_default>;
-	pinctrl-names = "default";
-};
diff --git a/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m_defconfig b/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m_defconfig
deleted file mode 100644
index 18f0eb4aee7..00000000000
--- a/boards/renesas/rzt2m_starterkit/rzt2m_starter_kit_renesas_rzt2m_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright (c) 2023 Antmicro <www.antmicro.com>
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_SERIAL=y
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-CONFIG_UART_INTERRUPT_DRIVEN=y
diff --git a/boards/renesas/rzv2l_smarc/Kconfig.rzv2l_smarc b/boards/renesas/rzv2l_smarc/Kconfig.rzv2l_smarc
new file mode 100644
index 00000000000..d294caf29ea
--- /dev/null
+++ b/boards/renesas/rzv2l_smarc/Kconfig.rzv2l_smarc
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_RZV2L_SMARC
+	select SOC_R9A07G054L23GBG
diff --git a/boards/renesas/rzv2l_smarc/board.cmake b/boards/renesas/rzv2l_smarc/board.cmake
new file mode 100644
index 00000000000..b2f27aac3e4
--- /dev/null
+++ b/boards/renesas/rzv2l_smarc/board.cmake
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R9A07G054L23")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/rzv2l_smarc/board.yml b/boards/renesas/rzv2l_smarc/board.yml
new file mode 100644
index 00000000000..3c484033274
--- /dev/null
+++ b/boards/renesas/rzv2l_smarc/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: rzv2l_smarc
+  full_name: RZ/V2L SMARC Evaluation Board Kit
+  vendor: renesas
+  socs:
+  - name: r9a07g054l23gbg
diff --git a/boards/renesas/rzv2l_smarc/doc/index.rst b/boards/renesas/rzv2l_smarc/doc/index.rst
new file mode 100644
index 00000000000..f190b44e215
--- /dev/null
+++ b/boards/renesas/rzv2l_smarc/doc/index.rst
@@ -0,0 +1,167 @@
+.. zephyr:board:: rzv2l_smarc
+
+Overview
+********
+
+The Renesas RZ/V2L SMARC Evaluation Board Kit (RZ/V2L-EVKIT) consists of a SMARC v2.1 module board and a carrier board.
+
+* Device: RZ/V2L R9A07G054L23GBG
+
+  * Cortex-A55 Dual, Cortex-M33
+  * BGA551pin, 15mmSq body, 0.5mm pitch
+
+* SMARC v2.1 Module Board Functions
+
+  * DDR4 SDRAM: 2GB x 1pc
+  * QSPI flash memory: 512Mb x 1pc
+  * eMMC memory: 64GB x 1pc
+  * The microSD card slot is implemented and used as an eSD for boot
+  * 5-output clock oscillator `5P35023 <https://www.renesas.com/en/products/clocks-timing/clock-generation/programmable-clocks/5p35023-versaclock-3s-programmable-clock-generator>`_ implemented
+  * PMIC power supply `RAA215300 <https://www.renesas.com/en/products/power-management/multi-channel-power-management-ics-pmics/raa215300-high-performance-9-channel-pmic-supporting-ddr-memory-built-charger-and-rtc>`_ implemented
+
+* Carrier Board Functions
+
+  * The FFC/FPC connector is mounted as standard for connection to high-speed serial interface for camera module.
+  * The Micro-HDMI connector via DSI/HDMI conversion module is mounted as standard for connection to high-speed serial interface for digital video module.
+  * The Micro-AB receptacle (ch0: USB2.0 OTG) and A receptacle (ch1: USB2.0 Host) are respectively mounted as standard for connection to USB interface.
+  * The RJ45 connector is mounted as standard for software development and evaluation using Ethernet.
+  * The audio codec is mounted as standard for advance development of audio system. The audio jack is implemented for connection to audio interface.
+  * The CAN connector is implemented for connection to CAN-Bus interface.
+  * The Micro-AB receptacles are implemented for connection to asynchronous serial port interface.
+  * The microSD card slot and two sockets for PMOD are implemented as an interface for RZ/V2L peripheral functions.
+  * For power supply, a mounted USB Type-C receptacle supports the USB PD standard.
+
+* MIPI Camera Module
+
+  * MIPI Camera Module (MIPI CSI) is included. Image recognition processing can be used with images input with MIPI camera.
+
+Hardware
+********
+
+The Renesas RZ/V2L MPU documentation can be found at `RZ/V2L Group Website`_
+
+.. figure:: rzv2l_block_diagram.webp
+	:width: 600px
+	:align: center
+	:alt: RZ/V2L group feature
+
+	RZ/V2L block diagram (Credit: Renesas Electronics Corporation)
+
+Detailed hardware features for the board can be found at `RZV2L-EVKIT Website`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``rzv2l_smarc`` board can be built in the usual way as
+documented in :ref:`build_an_application`.
+
+Console
+=======
+
+The UART port for Cortex-M33 System Core can be accessed by connecting `Pmod USBUART <https://store.digilentinc.com/pmod-usbuart-usb-to-uart-interface/>`_
+to the upper side of ``PMOD 1``.
+
+Debugging
+=========
+
+It is possible to load and execute a Zephyr application binary on
+this board on the Cortex-M33 System Core from
+the internal SRAM, using ``JLink`` debugger (:ref:`jlink-debug-host-tools`).
+
+Here is an example for building and debugging with the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: rzv2l_smarc/r9a07g054l23gbg/cm33
+   :goals: build debug
+
+Flashing
+========
+
+RZ/V2L-EVKIT is designed to start different systems on different cores.
+It uses Yocto as the build system to build Linux system and boot loaders
+to run Zephyr on Cortex-M33 with u-boot. The minimal steps are described below.
+
+1. Follow ''2.2 Building Images'' of `SMARC EVK of RZ/V2L Linux Start-up Guide`_ to prepare the build environment.
+
+2. At step (4), follow step ''2. Download Multi-OS Package'' and ''3. Add the layer for Multi-OS Package''
+   of ''3.2 OpenAMP related stuff Integration for RZ/V2L'' of `RZ/V2L Quick Start Guide for RZ/V Multi-OS Package`_
+   to add the layer for Multi-OS Package.
+
+.. code-block:: console
+
+   $ cd ~/rzv_vlp_<pkg ver>
+   $ unzip <Multi-OS Dir>/r01an7254ej0300-rzv-multi-os-pkg.zip
+   $ tar zxvf r01an7254ej0300-rzv-multi-os-pkg/meta-rz-features_multi-os_v3.0.0.tar.gz
+   $ bitbake-layers add-layer ../meta-rz-features/meta-rz-multi-os/meta-rzv2l
+
+3. Start the build:
+
+.. code-block:: console
+
+   $ MACHINE=smarc-rzv2l bitbake core-image-minimal
+
+The below necessary artifacts will be located in the build/tmp/deploy/images
+
++---------------+------------------------------------------------------+
+| Artifacts     | File name                                            |
++===============+======================================================+
+| Boot loader   | bl2_bp-smarc-rzv2l_pmic.srec                         |
+|               |                                                      |
+|               | fip-smarc-rzv2l_pmic.srec                            |
++---------------+------------------------------------------------------+
+| Flash Writer  | Flash_Writer_SCIF_RZV2L_SMARC_PMIC_DDR4_2GB_1PCS.mot |
++---------------+------------------------------------------------------+
+
+4. Follow ''4.2 Startup Procedure'' of `SMARC EVK of RZ/V2L Linux Start-up Guide`_ for power supply and board setting
+   at SCIF download (SW11[1:4] = OFF, ON, OFF, ON) and (SW1[1:2] = ON, OFF)
+
+5. Follow ''4.3 Download Flash Writer to RAM'' of `SMARC EVK of RZ/V2L Linux Start-up Guide`_ to download Flash Writer to RAM
+
+6. Follow ''4.4 Write the Bootloader'' of `SMARC EVK of RZ/V2L Linux Start-up Guide`_ to write the boot loader
+   to the target board by using Flash Writer.
+
+7. Follow ''4.5 Change Back to Normal Boot Mode'' with switch setting (SW11[1:4] = OFF, OFF, OFF, ON) and (SW1[1:2] = ON, OFF)
+
+8. Follow ''3. Preparing the SD Card'' of `SMARC EVK of RZ/V2L Linux Start-up Guide`_ to write files to the microSD Card
+
+9. Copy zephyr.bin file to microSD card
+
+10. Follow "4.3.2 CM33 Sample Program Invocation with u-boot" from the beginning to step 4 of `RZ/V2L Quick Start Guide for RZ/V Multi-OS Package`_
+
+11. Execute the commands stated below on the console to start zephyr application with CM33 core.
+    Here, ''N'' stands for the partition number in which you stored zephyr.bin file.
+
+.. code-block:: console
+
+   Hit any key to stop autoboot: 2
+   => dcache off
+   => mmc dev 1
+   => fatload mmc 1:N 0x00010000 zephyr.bin
+   => fatload mmc 1:N 0x40010000 zephyr.bin
+   => cm33 start_normal 0x00010000 0x40010000
+   => dcache on
+
+References
+**********
+
+.. target-notes::
+
+.. _RZ/V2L Group Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzv2l-general-purpose-microprocessor-equipped-renesas-original-ai-accelerator-drp-ai-12ghz-dual-core-arm
+
+.. _RZV2L-EVKIT Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/rz-mpus/rzv2l-evkit-smarc-som-evaluation-kit-rzv2l-mpu-ai-accelerator
+
+.. _SMARC EVK of RZ/V2L Linux Start-up Guide:
+   https://www.renesas.com/en/document/gde/smarc-evk-rzv2l-linux-start-guide-rev104
+
+.. _RZ/V2L Quick Start Guide for RZ/V Multi-OS Package:
+   https://www.renesas.com/en/document/apn/rzv2l-quick-start-guide-rzv-multi-os-package-v300
diff --git a/boards/renesas/rzv2l_smarc/doc/rzv2l_block_diagram.webp b/boards/renesas/rzv2l_smarc/doc/rzv2l_block_diagram.webp
new file mode 100644
index 00000000000..b3d0eaae918
Binary files /dev/null and b/boards/renesas/rzv2l_smarc/doc/rzv2l_block_diagram.webp differ
diff --git a/boards/renesas/rzv2l_smarc/doc/rzv2l_smarc.webp b/boards/renesas/rzv2l_smarc/doc/rzv2l_smarc.webp
new file mode 100644
index 00000000000..bec47b8e601
Binary files /dev/null and b/boards/renesas/rzv2l_smarc/doc/rzv2l_smarc.webp differ
diff --git a/boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi b/boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi
new file mode 100644
index 00000000000..3795c701c8f
--- /dev/null
+++ b/boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzv-common.h>
+
+&pinctrl {
+	/omit-if-no-ref/ scif2_pins: scif2 {
+		scif2-pinmux {
+			pinmux = <RZV_PINMUX(PORT_48, 0, 1)>, /* TXD */
+				 <RZV_PINMUX(PORT_48, 1, 1)>; /* RXD */
+		};
+	};
+};
diff --git a/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.dts b/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.dts
new file mode 100644
index 00000000000..28b3f8dcfdc
--- /dev/null
+++ b/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
+#include <arm/renesas/rz/rzv/r9a07g054.dtsi>
+#include "rzv2l_smarc-pinctrl.dtsi"
+
+/ {
+	model = "Renesas RZ/V2L SMARC";
+	compatible = "renesas,rzv2l-smarc";
+
+	chosen {
+		zephyr,sram = &ddr;
+		zephyr,console = &scif2;
+		zephyr,shell-uart = &scif2;
+	};
+
+	ddr: memory@60010000 {
+		compatible = "mmio-sram";
+		reg = <0x60010000 DT_SIZE_M(46)>;
+	};
+};
+
+&scif2 {
+	current-speed = <115200>;
+	pinctrl-0 = <&scif2_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.yaml b/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.yaml
new file mode 100644
index 00000000000..e3d17a6daf5
--- /dev/null
+++ b/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.yaml
@@ -0,0 +1,11 @@
+identifier: rzv2l_smarc/r9a07g054l23gbg/cm33
+name: Cortex-M33 for Renesas RZ/V2L SMARC
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - uart
+  - gpio
+vendor: renesas
diff --git a/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33_defconfig b/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33_defconfig
new file mode 100644
index 00000000000..c9dd44d6c70
--- /dev/null
+++ b/boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33_defconfig
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_XIP=n
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/renesas/voice_ra4e1/Kconfig.voice_ra4e1 b/boards/renesas/voice_ra4e1/Kconfig.voice_ra4e1
new file mode 100644
index 00000000000..51239caf331
--- /dev/null
+++ b/boards/renesas/voice_ra4e1/Kconfig.voice_ra4e1
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_VOICE_RA4E1
+	select SOC_R7FA4E10D2CNE
diff --git a/boards/renesas/voice_ra4e1/board.cmake b/boards/renesas/voice_ra4e1/board.cmake
new file mode 100644
index 00000000000..590f06a5743
--- /dev/null
+++ b/boards/renesas/voice_ra4e1/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7FA4E10D")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/renesas/voice_ra4e1/board.yml b/boards/renesas/voice_ra4e1/board.yml
new file mode 100644
index 00000000000..2d675896174
--- /dev/null
+++ b/boards/renesas/voice_ra4e1/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: voice_ra4e1
+  full_name: RA4E1 Voice User Reference Kit
+  vendor: renesas
+  socs:
+  - name: r7fa4e10d2cne
diff --git a/boards/renesas/voice_ra4e1/doc/index.rst b/boards/renesas/voice_ra4e1/doc/index.rst
new file mode 100644
index 00000000000..1b957560728
--- /dev/null
+++ b/boards/renesas/voice_ra4e1/doc/index.rst
@@ -0,0 +1,119 @@
+.. zephyr:board:: voice_ra4e1
+
+Overview
+********
+
+VOICE-RA4E1 is an edge voice recognition evaluation kit designed to be used by Ecosystem Partners,
+Application Engineers, Field Application Engineers, and for Business Development opportunities. The
+primary purpose is to evaluate the functionality of projects developed by Ecosystem Partners, and to
+facilitate the development of additional partner projects. The kit design to use the RA4E1 MCU with QFN
+48pin package as the core logic device, with QSPI flash, OPAMP and power devices chosen from the
+Renesas product portfolio.
+
+The MCU in this series incorporates a high-performance Arm Cortex®-M33 core running up to
+100 MHz with the following features:
+
+**MCU Native Pin Access**
+
+- R7FA4E10D2CNE MCU (referred to as RA MCU)
+- 100 MHz, Arm® Cortex®-M33 core
+- 512 KB Code Flash, 8 KB Data Flash, 128 KB SRAM
+- 48 pins, LQFP package
+- MCU current measurement point for precision current consumption measurement
+- Multiple clock sources - Low-precision (~1%) clocks are available internal to the RA MCU.
+
+**Kit Peripheral Features**
+
+Following is a list of the specific features that have been implemented:
+
+- QSPI: One QSPI flash memory device, Dialog AT25SF641B-MHB-T, 64M-bit (8MB).
+- PMOD: 1 Digilent PMOD connectors, supporting UART, SPI and I2C configurations.
+- Microphones: 1 I2S MEMS digital microphones and 2 MEMS analog microphones, distance between
+  each pair of microphones is 50mm which is suitable for beamforming applications.
+- Audio out: One stereo audio headphone jack supporting mono output on both channels.
+- LEDs: Five LEDs, D2 (Red), D3 (Green) and D4 (Blue) configurable by user, D5 (Blue) as a 3.3V power
+  indicator, D8(Green) as a JLOB (J-LINK on board) indicator.
+- Buttons: One RESET button (S2), and one USER button (S1).
+- Debug: J-Link On-Board debug interface, supporting JTAG or SWD debug port.
+- USB: Micro USB-B (J6) for power input and J-Link On-Board function, USB-C (J1) for power input and
+  RA4E1 USB Full Speed port as a USB device.
+- Form Factor: 7.5 x 6 cm
+
+Hardware
+********
+
+Detailed hardware features can be found at:
+
+- RA4E1 MCU: `RA4E1 Group User's Manual Hardware`_
+- VOICE-RA4E1 board: `VOICE-RA4E1 - Engineering Manual`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``voice_ra4e1`` board can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Flashing
+========
+
+Program can be flashed to VOICE-RA4E1 via the on-board SEGGER J-Link debugger.
+SEGGER J-link's drivers are available at https://www.segger.com/downloads/jlink/
+
+To flash the program to board
+
+1. Connect to J-Link OB via USB port to host PC
+
+2. Make sure J-Link OB jumper is in default configuration as describe in `VOICE-RA4E1 - Engineering Manual`_
+
+3. Execute west command
+
+	.. code-block:: console
+
+		west flash -r jlink
+
+Debugging
+=========
+
+You can use Segger Ozone (`Segger Ozone Download`_) for a visual debug interface
+
+Once downloaded and installed, open Segger Ozone and configure the debug project
+like so:
+
+* Target Device: R7FA4E10D
+* Target Interface: SWD
+* Target Interface Speed: 4 MHz
+* Host Interface: USB
+* Program File: <path/to/your/build/zephyr.elf>
+
+**Note:** It's verified that we can debug OK on Segger Ozone v3.30d so please use this or later
+version of Segger Ozone
+
+References
+**********
+
+- `VOICE-RA4E1 Website`_
+- `RA4E1 MCU group Website`_
+
+.. _VOICE-RA4E1 Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/tw001-vuia4e1pocz-ra4e1-voice-user-reference-kit
+
+.. _RA4E1 MCU group Website:
+   https://www.renesas.com/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra4e1-100mhz-arm-cortex-m33-entry-line-balanced-low-power-consumption-optimized-feature-integration
+
+.. _VOICE-RA4E1 - Engineering Manual:
+   https://www.renesas.com/en/document/mat/voice-ra4e1-engineering-manual
+
+.. _RA4E1 Group User's Manual Hardware:
+   https://www.renesas.com/en/document/mah/ra4e1-group-users-manual-hardware
+
+.. _Segger Ozone Download:
+   https://www.segger.com/downloads/jlink#Ozone
diff --git a/boards/renesas/voice_ra4e1/doc/voice_ra4e1.webp b/boards/renesas/voice_ra4e1/doc/voice_ra4e1.webp
new file mode 100644
index 00000000000..efed12efb2c
Binary files /dev/null and b/boards/renesas/voice_ra4e1/doc/voice_ra4e1.webp differ
diff --git a/boards/renesas/voice_ra4e1/voice_ra4e1-pinctrl.dtsi b/boards/renesas/voice_ra4e1/voice_ra4e1-pinctrl.dtsi
new file mode 100644
index 00000000000..54d8881d3bb
--- /dev/null
+++ b/boards/renesas/voice_ra4e1/voice_ra4e1-pinctrl.dtsi
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci3_default: sci3_default {
+		group1 {
+			/* tx rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_3, 4, 9)>,
+			<RA_PSEL(RA_PSEL_SCI_3, 4, 8)>;
+		};
+	};
+
+	usbfs_default: usbfs_default {
+		group1 {
+			/* USB_VBUS */
+			psels = <RA_PSEL(RA_PSEL_USBFS, 4, 7)>;
+			drive-strength = "high";
+		};
+	};
+
+	dac0_default: dac0_default {
+		group1 {
+			/* output */
+			psels = <RA_PSEL(RA_PSEL_DAC, 0, 14)>;
+			renesas,analog-enable;
+		};
+	};
+};
diff --git a/boards/renesas/voice_ra4e1/voice_ra4e1.dts b/boards/renesas/voice_ra4e1/voice_ra4e1.dts
new file mode 100644
index 00000000000..7cf9ec82e01
--- /dev/null
+++ b/boards/renesas/voice_ra4e1/voice_ra4e1.dts
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra4/r7fa4e10d2cne.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/adc/adc.h>
+#include "voice_ra4e1-pinctrl.dtsi"
+
+/ {
+	model = "Renesas VOICE-RA4E1";
+	compatible = "renesas,ra4e1", "renesas,ra";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash-controller = &flash1;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart3;
+		zephyr,shell-uart = &uart3;
+		zephyr,entropy = &trng;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1: led1 {
+			gpios = <&ioport5 0 GPIO_ACTIVE_HIGH>;
+			label = "LED1";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		button0: s1 {
+			gpios = <&ioport4 2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button switch 1";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	aliases {
+		led0 = &led1;
+		sw0 = &button0;
+		watchdog0 = &wdt;
+	};
+};
+
+&subclk {
+	status = "okay";
+};
+
+&pll {
+	clocks = <&hoco>;
+	div = <2>;
+	mul = <20 0>;
+	status = "okay";
+};
+
+&pll2 {
+	clocks = <&hoco>;
+	div = <2>;
+	mul = <24 0>;
+	status = "okay";
+};
+
+&uclk {
+	clocks = <&pll2>;
+	div = <5>;
+	status = "okay";
+};
+
+&sci3 {
+	interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
+	interrupt-names = "rxi", "txi", "tei", "eri";
+	pinctrl-0 = <&sci3_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	uart3: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
+
+&ioport1 {
+	status = "okay";
+};
+
+&ioport2 {
+	status = "okay";
+};
+
+&ioport4 {
+	status = "okay";
+};
+
+&ioport5 {
+	status = "okay";
+};
+
+&port_irq4 {
+	interrupts = <41 12>;
+	status = "okay";
+};
+
+&trng {
+	status = "okay";
+};
+
+&flash1 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		storage_partition: partition@0 {
+			label = "storage";
+			reg = <0X0 DT_SIZE_K(8)>;
+		};
+	};
+};
+
+&usbfs {
+	pinctrl-0 = <&usbfs_default>;
+	pinctrl-names = "default";
+	maximum-speed = "full-speed";
+	status = "okay";
+	zephyr_udc0: udc {
+		status = "okay";
+	};
+};
+
+&wdt {
+	status = "okay";
+};
+
+&dac0 {
+	pinctrl-0 = <&dac0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/boards/renesas/voice_ra4e1/voice_ra4e1.yaml b/boards/renesas/voice_ra4e1/voice_ra4e1.yaml
new file mode 100644
index 00000000000..bd744cc553d
--- /dev/null
+++ b/boards/renesas/voice_ra4e1/voice_ra4e1.yaml
@@ -0,0 +1,15 @@
+identifier: voice_ra4e1
+name: Renesas VOICE-RA4E1
+type: mcu
+arch: arm
+ram: 128
+flash: 512
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - uart
+  - usbd
+  - watchdog
+vendor: renesas
diff --git a/boards/renesas/voice_ra4e1/voice_ra4e1_defconfig b/boards/renesas/voice_ra4e1/voice_ra4e1_defconfig
new file mode 100644
index 00000000000..f26066de3e5
--- /dev/null
+++ b/boards/renesas/voice_ra4e1/voice_ra4e1_defconfig
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_UART_CONSOLE=y
+CONFIG_CONSOLE=y
diff --git a/boards/renode/cortex_r8_virtual/doc/index.rst b/boards/renode/cortex_r8_virtual/doc/index.rst
index 8691724fcea..9b6e6f3ded0 100644
--- a/boards/renode/cortex_r8_virtual/doc/index.rst
+++ b/boards/renode/cortex_r8_virtual/doc/index.rst
@@ -12,6 +12,8 @@ to learn how to obtain Renode for your host.
 Programming and debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Building
 ========
 
diff --git a/boards/renode/riscv32_virtual/doc/index.rst b/boards/renode/riscv32_virtual/doc/index.rst
index 478260d2689..67f087010df 100644
--- a/boards/renode/riscv32_virtual/doc/index.rst
+++ b/boards/renode/riscv32_virtual/doc/index.rst
@@ -11,6 +11,8 @@ configurations that only exist in proprietary boards/SoCs to be tested in upstre
 Programming and debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Building
 ========
 
diff --git a/boards/ronoth/lodev/ronoth_lodev.yaml b/boards/ronoth/lodev/ronoth_lodev.yaml
index ca715a9ed55..495f9ff9c67 100644
--- a/boards/ronoth/lodev/ronoth_lodev.yaml
+++ b/boards/ronoth/lodev/ronoth_lodev.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 20
 flash: 192
 supported:
diff --git a/boards/ruiside/art_pi2/Kconfig.art_pi2 b/boards/ruiside/art_pi2/Kconfig.art_pi2
new file mode 100644
index 00000000000..d88e6dc02ff
--- /dev/null
+++ b/boards/ruiside/art_pi2/Kconfig.art_pi2
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Shan Pen <bricle031@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ART_PI2
+	select SOC_STM32H7R7XX
diff --git a/boards/ruiside/art_pi2/art_pi2.dts b/boards/ruiside/art_pi2/art_pi2.dts
new file mode 100644
index 00000000000..e0fa2b3df9e
--- /dev/null
+++ b/boards/ruiside/art_pi2/art_pi2.dts
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2025 Shan Pen <bricle031@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/h7rs/stm32h7r7X8.dtsi>
+#include <st/h7/stm32h7r7l8hxh-pinctrl.dtsi>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "Ruiside Electronic ART-Pi2 board";
+	compatible = "ruiside,art-pi2";
+
+	chosen {
+		zephyr,console = &uart4;
+		zephyr,shell-uart = &uart4;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		red_led: led_1 {
+			gpios = <&gpioo 1 GPIO_ACTIVE_HIGH>;
+			label = "User LED1";
+		};
+
+		blue_led: led_2 {
+			gpios = <&gpioo 5 GPIO_ACTIVE_LOW>;
+			label = "User LED2";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		user_button: button_0 {
+			label = "User";
+			gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	aliases {
+		led0 = &red_led;
+		led1 = &blue_led;
+		sw0 = &user_button;
+		watchdog0 = &iwdg;
+		die-temp0 = &die_temp;
+		volt-sensor0 = &vref;
+		volt-sensor1 = &vbat;
+	};
+};
+
+&dtcm {
+	reg = <0x20000000 DT_SIZE_K(64)>;
+};
+
+&clk_hsi48 {
+	status = "okay";
+};
+
+&clk_hse {
+	clock-frequency = <DT_FREQ_M(24)>;
+	status = "okay";
+};
+
+&pll {
+	div-m = <12>;
+	mul-n = <250>;
+	div-p = <2>;
+	div-q = <2>;
+	div-r = <2>;
+	div-s = <2>;
+	div-t = <2>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(250)>;
+	dcpre = <1>;
+	hpre = <1>;
+	ppre1 = <2>;
+	ppre2 = <2>;
+	ppre4 = <2>;
+	ppre5 = <2>;
+};
+
+&uart4 {
+	pinctrl-0 = <&uart4_tx_pd1 &uart4_rx_pd0>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&rng {
+	status = "okay";
+};
+
+&iwdg {
+	status = "okay";
+};
+
+&wwdg {
+	status = "okay";
+};
+
+&vref {
+	status = "okay";
+};
+
+&vbat {
+	status = "okay";
+};
diff --git a/boards/ruiside/art_pi2/art_pi2.yaml b/boards/ruiside/art_pi2/art_pi2.yaml
new file mode 100644
index 00000000000..575256904ce
--- /dev/null
+++ b/boards/ruiside/art_pi2/art_pi2.yaml
@@ -0,0 +1,14 @@
+identifier: art_pi2
+name: art pi2
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+ram: 640
+flash: 64
+supported:
+  - gpio
+  - uart
+  - watchdog
+  - entropy
+vendor: ruiside
diff --git a/boards/ruiside/art_pi2/art_pi2_defconfig b/boards/ruiside/art_pi2/art_pi2_defconfig
new file mode 100644
index 00000000000..d29ed69be8d
--- /dev/null
+++ b/boards/ruiside/art_pi2/art_pi2_defconfig
@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Shan Pen <bricle031@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable SMPS
+CONFIG_POWER_SUPPLY_DIRECT_SMPS=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
diff --git a/boards/ruiside/art_pi2/board.cmake b/boards/ruiside/art_pi2/board.cmake
new file mode 100644
index 00000000000..1a9c29c25ea
--- /dev/null
+++ b/boards/ruiside/art_pi2/board.cmake
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# keep first
+board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
+board_runner_args(pyocd "--target=stm32h7r7l8hxh")
+
+# keep first
+include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
diff --git a/boards/ruiside/art_pi2/board.yml b/boards/ruiside/art_pi2/board.yml
new file mode 100644
index 00000000000..78cc314195c
--- /dev/null
+++ b/boards/ruiside/art_pi2/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: art_pi2
+  full_name: ART-Pi2
+  vendor: ruiside
+  socs:
+    - name: stm32h7r7xx
diff --git a/boards/ruiside/art_pi2/doc/img/art_pi2.webp b/boards/ruiside/art_pi2/doc/img/art_pi2.webp
new file mode 100644
index 00000000000..b572880848d
Binary files /dev/null and b/boards/ruiside/art_pi2/doc/img/art_pi2.webp differ
diff --git a/boards/ruiside/art_pi2/doc/index.rst b/boards/ruiside/art_pi2/doc/index.rst
new file mode 100644
index 00000000000..7dee5755e9b
--- /dev/null
+++ b/boards/ruiside/art_pi2/doc/index.rst
@@ -0,0 +1,163 @@
+.. zephyr:board:: art_pi2
+
+Overview
+********
+
+The ART-Pi2 is an open-source hardware platform designed by the
+RT-Thread team specifically for embedded software engineers
+and open-source makers, offering extensive expandability for DIY projects.
+
+Key Features
+
+- STM32H7R7L8HxH microcontroller featuring 64 Kbytes of Flash and 620 Kbytes of SRAM in an TFBGA225 package
+- On-board ST-LINK/V2.1 debugger/programmer
+- SDIO TF Card slot
+- SDIO WIFI:CYWL6208
+- HDC UART BuleTooth:CYWL6208
+- 32-MB HyperRAM
+- 64-MB HyperFlash
+- One Power LED (blue) for 3.3 V power-on
+- Two user LEDs blue and red
+- Two ST-LINK LEDs: blue and red
+- Two push-buttons (user and reset)
+- Board connectors:
+
+  - USB OTG with Type-C connector
+  - RGB888 FPC connector
+
+More information about the board can be found at the `ART-Pi2 website`_.
+
+Hardware
+********
+
+ART-Pi2 provides the following hardware components:
+
+The STM32H7R7xx devices are a high-performance microcontrollers family (STM32H7
+Series) based on the high-performance Arm |reg| Cortex |reg|-M7 32-bit RISC core.
+They operate at a frequency of up to 600 MHz.
+
+More information about STM32H7R7 can be found here:
+
+- `STM32H7R7L8 on www.st.com`_
+- `STM32H7Rx reference manual`_
+
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+The ART-Pi2 board features a On-board ST-LINK/V2.1 debugger/programmer. Board is configured as follows:
+
+- UART4 TX/RX : PD1/PD0 (ST-Link Virtual Port Com)
+- LED1 (red) : PO1
+- LED2 (blue) : PO5
+- USER PUSH-BUTTON : PC13
+
+System Clock
+------------
+
+ART-Pi2 System Clock could be driven by an internal or external
+oscillator, as well as the main PLL clock. By default, the System clock is
+driven by the PLL clock at 250MHz, driven by an 24MHz high-speed external clock.
+
+Serial Port
+-----------
+
+ART-Pi2 board has 4 UARTs and 3 USARTs plus one LowPower UART. The Zephyr console
+output is assigned to UART4. Default settings are 115200 8N1.
+
+Backup SRAM
+-----------
+
+In order to test backup SRAM you may want to disconnect VBAT from VDD. You can
+do it by removing ``SB13`` jumper on the back side of the board.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+ART-Pi2 board includes an ST-LINK/V2.1 embedded debug tool interface.
+
+.. note::
+
+   Check if your ST-LINK V2.1 has newest FW version. It can be done with `STM32CubeProgrammer`_
+
+Flashing
+========
+
+The board is configured to be flashed using west `STM32CubeProgrammer`_ runner,
+so its :ref:`installation <stm32cubeprog-flash-host-tools>` is required.
+
+Flashing an application to ART-Pi2
+----------------------------------
+
+First, connect the art_pi2 to your host computer using
+the USB port to prepare it for flashing. Then build and flash your application.
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+Run a serial host program to connect with your art_pi2 board.
+
+.. code-block:: console
+
+   $ minicom -b 115200 -D /dev/ttyACM0
+
+or use screen:
+
+.. code-block:: console
+
+   $ screen /dev/ttyACM0 115200
+
+Build and flash the application:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: art_pi2
+   :goals: build flash
+
+You should see the following message on the console:
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v4.1.0-1907-g415ab379a8af ***
+   Hello World! art_pi2/stm32h7r7xx
+
+Blinky example can also be used:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: art_pi2
+   :goals: build flash
+
+Debugging
+=========
+
+You can debug an application in the usual way.  Here is an example for the
+:zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: art_pi2
+   :maybe-skip-config:
+   :goals: debug
+
+References
+**********
+.. target-notes::
+
+.. _ART-Pi2 website:
+   https://github.com/RT-Thread-Studio/sdk-bsp-stm32h7r-realthread-artpi2
+
+.. _STM32H7R7L8 on www.st.com:
+   https://www.st.com/en/microcontrollers-microprocessors/stm32h7r7l8.html
+
+.. _STM32H7Rx reference manual:
+   https://www.st.com/resource/en/reference_manual/rm0477-stm32h7rx7sx-armbased-32bit-mcus-stmicroelectronics.pdf
+
+.. _STM32CubeProgrammer:
+   https://www.st.com/en/development-tools/stm32cubeprog.html
diff --git a/boards/ruiside/index.rst b/boards/ruiside/index.rst
new file mode 100644
index 00000000000..0422a90b1f5
--- /dev/null
+++ b/boards/ruiside/index.rst
@@ -0,0 +1,10 @@
+.. _boards-Ruiside:
+
+Ruiside
+#######
+
+.. toctree::
+   :maxdepth: 1
+   :glob:
+
+   **/*
diff --git a/boards/ruuvi/ruuvitag/doc/index.rst b/boards/ruuvi/ruuvitag/doc/index.rst
index 946b9549468..a9fb0017055 100644
--- a/boards/ruuvi/ruuvitag/doc/index.rst
+++ b/boards/ruuvi/ruuvitag/doc/index.rst
@@ -29,37 +29,7 @@ RuuviTag's have the following physical features:
 Supported Features
 ==================
 
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-| Humidity, | on-board   | bme280               |
-| Temp & Air|            |                      |
-| Pressure  |            |                      |
-+-----------+------------+----------------------+
-| Acc       | on-board   | lis2dh12             |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -129,6 +99,8 @@ P1 = TC2030 TagConnect (on RuuviTag Rev.B6)
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/ruuvi/ruuvitag/ruuvi_ruuvitag.yaml b/boards/ruuvi/ruuvitag/ruuvi_ruuvitag.yaml
index 151e614cbfb..3331bd17905 100644
--- a/boards/ruuvi/ruuvitag/ruuvi_ruuvitag.yaml
+++ b/boards/ruuvi/ruuvitag/ruuvi_ruuvitag.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 512
 supported:
diff --git a/boards/sc/scobc_module1/doc/index.rst b/boards/sc/scobc_module1/doc/index.rst
index 52e8000b1b8..264e27801ea 100644
--- a/boards/sc/scobc_module1/doc/index.rst
+++ b/boards/sc/scobc_module1/doc/index.rst
@@ -58,6 +58,8 @@ respectively.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/seagate/faze/doc/index.rst b/boards/seagate/faze/doc/index.rst
index fbb0b5e0084..f4d5f2317d1 100644
--- a/boards/seagate/faze/doc/index.rst
+++ b/boards/seagate/faze/doc/index.rst
@@ -1,7 +1,4 @@
-.. _faze:
-
-Seagate FireCuda Gaming SSD (FaZe) board
-########################################
+.. zephyr:board:: faze
 
 Overview
 ********
@@ -14,10 +11,6 @@ through I2C and GPIOs.
 
 This Zephyr port is running on the NXP LPC11U67 MCU.
 
-.. image:: firecuda-gaming-ssd.jpg
-   :align: center
-   :alt: Seagate FireCuda Gaming SSD
-
 Hardware
 ********
 
@@ -44,28 +37,7 @@ More information can be found here:
 Supported Features
 ==================
 
-All the hardware features available on the FaZe board are supported in Zephyr.
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| IOCON     | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock and reset control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c master/slave controller         |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port interrupt               |
-+-----------+------------+-------------------------------------+
-| EEPROM    | on-chip    | eeprom                              |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -97,6 +69,8 @@ The IOCON controller can be used to configure the LPC11U67 pins.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/seagate/legend/board.yml b/boards/seagate/legend/board.yml
index a015c60bc4e..e4780925afe 100644
--- a/boards/seagate/legend/board.yml
+++ b/boards/seagate/legend/board.yml
@@ -4,5 +4,10 @@ board:
   vendor: seagate
   revision:
     format: custom
+    default: "25hdd"
+    revisions:
+      - name: "25hdd"
+      - name: "25ssd"
+      - name: "35"
   socs:
     - name: stm32f070xb
diff --git a/boards/seagate/legend/doc/index.rst b/boards/seagate/legend/doc/index.rst
index 1156a792317..f265db5fb0d 100644
--- a/boards/seagate/legend/doc/index.rst
+++ b/boards/seagate/legend/doc/index.rst
@@ -1,7 +1,4 @@
-.. _legend:
-
-Legend
-######
+.. zephyr:board:: legend
 
 Overview
 ********
@@ -52,31 +49,7 @@ Hardware
 Supported Features
 ==================
 
-All the hardware features available on the Legend boards are supported by
-Zephyr.
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | clock and reset control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c master/slave controller         |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| SPI flash | on-chip    | spi_nor                             |
-+-----------+------------+-------------------------------------+
-| LED strip | on-chip    | ws2812                              |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb                                 |
-+-----------+------------+-------------------------------------+
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -112,6 +85,8 @@ Connections and IOs
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/seagate/legend/legend_stm32f070xb_25hdd.yaml b/boards/seagate/legend/legend_stm32f070xb_25hdd.yaml
index e94bd6e2faa..04853f50efd 100644
--- a/boards/seagate/legend/legend_stm32f070xb_25hdd.yaml
+++ b/boards/seagate/legend/legend_stm32f070xb_25hdd.yaml
@@ -7,7 +7,6 @@ flash: 128
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/seagate/legend/legend_stm32f070xb_25ssd.yaml b/boards/seagate/legend/legend_stm32f070xb_25ssd.yaml
index b1aa3766f77..52f80c47701 100644
--- a/boards/seagate/legend/legend_stm32f070xb_25ssd.yaml
+++ b/boards/seagate/legend/legend_stm32f070xb_25ssd.yaml
@@ -7,7 +7,6 @@ flash: 128
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/seagate/legend/legend_stm32f070xb_35.yaml b/boards/seagate/legend/legend_stm32f070xb_35.yaml
index 851fb36a8b4..098487e913f 100644
--- a/boards/seagate/legend/legend_stm32f070xb_35.yaml
+++ b/boards/seagate/legend/legend_stm32f070xb_35.yaml
@@ -7,7 +7,6 @@ flash: 128
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/seco/stm32f3_seco_d23/doc/index.rst b/boards/seco/stm32f3_seco_d23/doc/index.rst
index 03e0bf82586..10517105ae7 100644
--- a/boards/seco/stm32f3_seco_d23/doc/index.rst
+++ b/boards/seco/stm32f3_seco_d23/doc/index.rst
@@ -50,35 +50,7 @@ More information about STM32F302VC can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32f3_seco_d23 board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | CAN                                 |
-+-----------+------------+-------------------------------------+
-| IWDG      | on-chip    | Independent WatchDoG                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -172,6 +144,8 @@ main processor (Rockchip PX30) and SPI2 is connected to CN39.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/seco/stm32f3_seco_d23/stm32f3_seco_d23.yaml b/boards/seco/stm32f3_seco_d23/stm32f3_seco_d23.yaml
index 469523eadc2..e1c2b9fe64a 100644
--- a/boards/seco/stm32f3_seco_d23/stm32f3_seco_d23.yaml
+++ b/boards/seco/stm32f3_seco_d23/stm32f3_seco_d23.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 40
 supported:
   - gpio
diff --git a/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst b/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst
index 9c2071abd4f..4d1b56175d6 100644
--- a/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst
+++ b/boards/seeed/lora_e5_dev_board/doc/lora_e5_dev_board.rst
@@ -66,49 +66,7 @@ More information about LoRa-E5 STM32WLE5JC Module can be found here:
 Supported Features
 ==================
 
-The Zephyr LoRa-E5 Dev Board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| AES       | on-chip    | crypto                              |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| MPU       | on-chip    | arch/arm                            |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | arch/arm                            |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| RADIO     | on-chip    | LoRa                                |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in:
-
-- :zephyr_file:`boards/seeed/lora_e5_dev_board/lora_e5_dev_board_defconfig`
-- :zephyr_file:`boards/seeed/lora_e5_dev_board/lora_e5_dev_board.dts`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -196,6 +154,8 @@ By default System clock is driven by the MSI clock at 48MHz.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``lora_e5_dev_board`` board configuration can be built the
 usual way (see :ref:`build_an_application`).
 
diff --git a/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.yaml b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.yaml
index dede51f8125..7b630ff1696 100644
--- a/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.yaml
+++ b/boards/seeed/lora_e5_dev_board/lora_e5_dev_board.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 256
 supported:
diff --git a/boards/seeed/lora_e5_mini/doc/index.rst b/boards/seeed/lora_e5_mini/doc/index.rst
index 05e94cdaf3a..a396bd4d991 100644
--- a/boards/seeed/lora_e5_mini/doc/index.rst
+++ b/boards/seeed/lora_e5_mini/doc/index.rst
@@ -56,48 +56,7 @@ More information about LoRa-E5 STM32WLE5JC Module can be found here:
 Supported Features
 ==================
 
-The Zephyr LoRa-E5 mini configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| AES       | on-chip    | crypto                              |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| MPU       | on-chip    | arch/arm                            |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | arch/arm                            |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| RADIO     | on-chip    | LoRa                                |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in:
-
-- :zephyr_file:`boards/seeed/lora_e5_mini/lora_e5_mini_defconfig`
-- :zephyr_file:`boards/seeed/lora_e5_mini/lora_e5_mini.dts`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -132,6 +91,8 @@ main PLL clock. By default System clock is driven by the MSI clock at 48MHz.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``lora_e5_mini`` board configuration can be built the
 usual way (see :ref:`build_an_application`).
 
diff --git a/boards/seeed/lora_e5_mini/lora_e5_mini.yaml b/boards/seeed/lora_e5_mini/lora_e5_mini.yaml
index 72a8018b0e3..3b1b998b6c7 100644
--- a/boards/seeed/lora_e5_mini/lora_e5_mini.yaml
+++ b/boards/seeed/lora_e5_mini/lora_e5_mini.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 256
 supported:
diff --git a/boards/seeed/seeeduino_xiao/doc/index.rst b/boards/seeed/seeeduino_xiao/doc/index.rst
index 7dc905e39b3..2f2d40bd250 100644
--- a/boards/seeed/seeeduino_xiao/doc/index.rst
+++ b/boards/seeed/seeeduino_xiao/doc/index.rst
@@ -18,41 +18,7 @@ Hardware
 Supported Features
 ==================
 
-The seeeduino_xiao board configuration supports the following hardware
-features:
-
-+-----------+------------+------------------------------------------+
-| Interface | Controller | Driver/Component                         |
-+===========+============+==========================================+
-| DMA       | on-chip    | Direct memory access                     |
-+-----------+------------+------------------------------------------+
-| DAC       | on-chip    | Digital to analogue converter            |
-+-----------+------------+------------------------------------------+
-| Flash     | on-chip    | Can be used with LittleFS to store files |
-+-----------+------------+------------------------------------------+
-| GPIO      | on-chip    | I/O ports                                |
-+-----------+------------+------------------------------------------+
-| HWINFO    | on-chip    | Hardware info                            |
-+-----------+------------+------------------------------------------+
-| I2C       | on-chip    | Inter-Integrated Circuit                 |
-+-----------+------------+------------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller       |
-+-----------+------------+------------------------------------------+
-| SPI       | on-chip    | Serial Peripheral Interface ports        |
-+-----------+------------+------------------------------------------+
-| SYSTICK   | on-chip    | systick                                  |
-+-----------+------------+------------------------------------------+
-| USART     | on-chip    | Serial ports                             |
-+-----------+------------+------------------------------------------+
-| USB       | on-chip    | USB device                               |
-+-----------+------------+------------------------------------------+
-| WDT       | on-chip    | Watchdog                                 |
-+-----------+------------+------------------------------------------+
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig file
-:zephyr_file:`boards/seeed/seeeduino_xiao/seeeduino_xiao_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -104,6 +70,8 @@ the XIAO, the DAC is available on pin 0.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The XIAO ships the BOSSA compatible UF2 bootloader.  The bootloader can be
 entered by shorting the RST and GND pads twice.
 
diff --git a/boards/seeed/seeeduino_xiao/seeeduino_xiao.yaml b/boards/seeed/seeeduino_xiao/seeeduino_xiao.yaml
index 4330f0a754a..fec73550e3f 100644
--- a/boards/seeed/seeeduino_xiao/seeeduino_xiao.yaml
+++ b/boards/seeed/seeeduino_xiao/seeeduino_xiao.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 flash: 256
 ram: 32
 supported:
@@ -18,4 +17,9 @@ supported:
   - uart
   - usb_device
   - watchdog
+  - xiao_adc
+  - xiao_gpio
+  - xiao_i2c
+  - xiao_serial
+  - xiao_spi
 vendor: seeed
diff --git a/boards/seeed/wio_terminal/doc/index.rst b/boards/seeed/wio_terminal/doc/index.rst
index 736d3cb6984..48632f64b63 100644
--- a/boards/seeed/wio_terminal/doc/index.rst
+++ b/boards/seeed/wio_terminal/doc/index.rst
@@ -33,58 +33,7 @@ Hardware
 Supported Features
 ==================
 
-The wio_terminal board configuration supports the following hardware features:
-
-.. list-table::
-    :header-rows: 1
-
-    * - Interface
-      - Controller
-      - Driver / Component
-    * - NVIC
-      - on-chip
-      - Nested vector interrupt controller
-    * - Flash
-      - on-chip
-      - Can be used with LittleFS to store files
-    * - SYSTICK
-      - on-chip
-      - Systick
-    * - WDT
-      - on-chip
-      - Watchdog
-    * - GPIO
-      - on-chip
-      - I/O ports
-    * - USART
-      - on-chip
-      - Serial port
-    * - I2C
-      - on-chip
-      - Inter-Integrated Circuit
-    * - SPI
-      - on-chip
-      - Serial Peripheral Interface port
-    * - TRNG
-      - on-chip
-      - True Random Number Generator
-    * - HWINFO
-      - on-chip
-      - Unique 128 bit serial number
-    * - RTC
-      - on-chip
-      - Real-Time Counter
-    * - USB
-      - on-chip
-      - USB device
-    * - PWM
-      - on-chip
-      - PWM
-
-Other hardware features are not currently supported by Zephyr.
-
-The default configuration can be found in the Kconfig file
-:zephyr_file:`boards/seeed/wio_terminal/wio_terminal_defconfig`.
+.. zephyr:board-supported-hw::
 
 Zephyr can use the default Cortex-M SYSTICK timer or the SAM0 specific RTC.
 To use the RTC, set :kconfig:option:`CONFIG_CORTEX_M_SYSTICK=n` and set
@@ -120,6 +69,8 @@ characters back to the host PC.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The Wio Terminal ships with an UF2 bootloader that is BOSSA compatible. The
 bootloader can be entered by quickly tapping the reset button twice.
 
diff --git a/boards/seeed/wio_terminal/wio_terminal.yaml b/boards/seeed/wio_terminal/wio_terminal.yaml
index 66a97ebefc0..a5445ae3cd0 100644
--- a/boards/seeed/wio_terminal/wio_terminal.yaml
+++ b/boards/seeed/wio_terminal/wio_terminal.yaml
@@ -7,7 +7,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - counter
diff --git a/boards/seeed/xiao_ble/doc/index.rst b/boards/seeed/xiao_ble/doc/index.rst
index 831eb872a9d..c36c5004a2f 100644
--- a/boards/seeed/xiao_ble/doc/index.rst
+++ b/boards/seeed/xiao_ble/doc/index.rst
@@ -23,42 +23,7 @@ Hardware
 Supported Features
 ==================
 
-The xiao_ble board configuration supports the following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash, QSPI flash    |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| USB       | on-chip    | usb                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -76,6 +41,8 @@ LED
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The XIAO BLE ships with the `Adafruit nRF52 Bootloader`_ which supports flashing
 using `UF2`_. Doing so allows easy flashing of new images, but does not support
 debugging the device. For debugging please use `External Debugger`_.
diff --git a/boards/seeed/xiao_ble/xiao_ble.yaml b/boards/seeed/xiao_ble/xiao_ble.yaml
index 3351b8f609e..a6482108e38 100644
--- a/boards/seeed/xiao_ble/xiao_ble.yaml
+++ b/boards/seeed/xiao_ble/xiao_ble.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - ble
@@ -20,4 +19,9 @@ supported:
   - usb_device
   - watchdog
   - netif:openthread
+  - xiao_adc
+  - xiao_gpio
+  - xiao_i2c
+  - xiao_serial
+  - xiao_spi
 vendor: seeed
diff --git a/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml
index 9de9481776a..9275e38f7f6 100644
--- a/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml
+++ b/boards/seeed/xiao_ble/xiao_ble_nrf52840_sense.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - ble
@@ -20,4 +19,9 @@ supported:
   - usb_device
   - watchdog
   - netif:openthread
+  - xiao_adc
+  - xiao_gpio
+  - xiao_i2c
+  - xiao_serial
+  - xiao_spi
 vendor: seeed
diff --git a/boards/seeed/xiao_esp32c3/doc/index.rst b/boards/seeed/xiao_esp32c3/doc/index.rst
index fa9811661a4..ef8bdb5a86e 100644
--- a/boards/seeed/xiao_esp32c3/doc/index.rst
+++ b/boards/seeed/xiao_esp32c3/doc/index.rst
@@ -19,29 +19,7 @@ pinout.
 Supported Features
 ==================
 
-The XIAO ESP32C3 board configuration supports the following hardware features:
-
-+-----------+------------+------------------+
-| Interface | Controller | Driver/Component |
-+===========+============+==================+
-| PMP       | on-chip    | arch/riscv       |
-+-----------+------------+------------------+
-| INTMTRX   | on-chip    | intc_esp32c3     |
-+-----------+------------+------------------+
-| PINMUX    | on-chip    | pinctrl_esp32    |
-+-----------+------------+------------------+
-| USB UART  | on-chip    | serial_esp32_usb |
-+-----------+------------+------------------+
-| GPIO      | on-chip    | gpio_esp32       |
-+-----------+------------+------------------+
-| UART      | on-chip    | uart_esp32       |
-+-----------+------------+------------------+
-| I2C       | on-chip    | i2c_esp32        |
-+-----------+------------+------------------+
-| SPI       | on-chip    | spi_esp32_spim   |
-+-----------+------------+------------------+
-| TWAI      | on-chip    | can_esp32_twai   |
-+-----------+------------+------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -71,6 +49,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/seeed/xiao_esp32c3/xiao_esp32c3.yaml b/boards/seeed/xiao_esp32c3/xiao_esp32c3.yaml
index bacf2a681bd..2cb67d19dca 100644
--- a/boards/seeed/xiao_esp32c3/xiao_esp32c3.yaml
+++ b/boards/seeed/xiao_esp32c3/xiao_esp32c3.yaml
@@ -11,4 +11,9 @@ supported:
   - uart
   - watchdog
   - can
+  - xiao_adc
+  - xiao_gpio
+  - xiao_i2c
+  - xiao_serial
+  - xiao_spi
 vendor: seeed
diff --git a/boards/seeed/xiao_esp32c3/xiao_esp32c3_defconfig b/boards/seeed/xiao_esp32c3/xiao_esp32c3_defconfig
index ef633ce56a1..187793c76e8 100644
--- a/boards/seeed/xiao_esp32c3/xiao_esp32c3_defconfig
+++ b/boards/seeed/xiao_esp32c3/xiao_esp32c3_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/seeed/xiao_esp32c6/Kconfig b/boards/seeed/xiao_esp32c6/Kconfig
index bc76c90de06..c753069c633 100644
--- a/boards/seeed/xiao_esp32c6/Kconfig
+++ b/boards/seeed/xiao_esp32c6/Kconfig
@@ -3,4 +3,5 @@
 
 config HEAP_MEM_POOL_ADD_SIZE_BOARD
 	int
-	default 4096
+	default 4096 if BOARD_XIAO_ESP32C6_ESP32C6_HPCORE
+	default 256 if BOARD_XIAO_ESP32C6_ESP32C6_LPCORE
diff --git a/boards/seeed/xiao_esp32c6/Kconfig.xiao_esp32c6 b/boards/seeed/xiao_esp32c6/Kconfig.xiao_esp32c6
index 34fc9fe1b5e..d86b021015d 100644
--- a/boards/seeed/xiao_esp32c6/Kconfig.xiao_esp32c6
+++ b/boards/seeed/xiao_esp32c6/Kconfig.xiao_esp32c6
@@ -5,3 +5,5 @@
 
 config BOARD_XIAO_ESP32C6
 	select SOC_ESP32_C6_WROOM_1U_N4
+	select SOC_ESP32C6_HPCORE if BOARD_XIAO_ESP32C6_ESP32C6_HPCORE
+	select SOC_ESP32C6_LPCORE if BOARD_XIAO_ESP32C6_ESP32C6_LPCORE
diff --git a/boards/seeed/xiao_esp32c6/doc/index.rst b/boards/seeed/xiao_esp32c6/doc/index.rst
index 5e6865c5b02..a1b93cc9c42 100644
--- a/boards/seeed/xiao_esp32c6/doc/index.rst
+++ b/boards/seeed/xiao_esp32c6/doc/index.rst
@@ -21,37 +21,7 @@ It is based on a standard XIAO 14 pin pinout.
 Supported Features
 ==================
 
-The Zephyr ``xiao_esp32c6`` board target supports the following hardware features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| I2C        | on-chip    | i2c                                 |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| SPI DMA    | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| GDMA       | on-chip    | dma                                 |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| USB-CDC    | on-chip    | serial                              |
-+------------+------------+-------------------------------------+
-| Wi-Fi      | on-chip    |                                     |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 The board uses a standard XIAO pinout, the default pin mapping is the following:
 
@@ -81,6 +51,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
@@ -122,12 +94,12 @@ To build the sample application using sysbuild use the command:
 .. zephyr-app-commands::
    :tool: west
    :zephyr-app: samples/hello_world
-   :board: xiao_esp32c6
+   :board: xiao_esp32c6/esp32c6/hpcore
    :goals: build
    :west-args: --sysbuild
    :compact:
 
-By default, the ESP32 sysbuild creates bootloader (MCUboot) and application
+By default, the ESP32-C6 sysbuild creates bootloader (MCUboot) and application
 images. But it can be configured to create other kind of images.
 
 Build directory structure created by sysbuild is different from traditional
@@ -171,7 +143,7 @@ Build and flash applications as usual (see :ref:`build_an_application` and
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: xiao_esp32c6
+   :board: xiao_esp32c6/esp32c6/hpcore
    :goals: build
 
 The usual ``flash`` target will work with the ``xiao_esp32c6`` board
@@ -180,7 +152,7 @@ application.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: xiao_esp32c6
+   :board: xiao_esp32c6/esp32c6/hpcore
    :goals: flash
 
 Since the Zephyr console is by default on the ``usb_serial`` device, we use
@@ -196,7 +168,7 @@ message in the monitor:
 .. code-block:: console
 
    ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
-   Hello World! xiao_esp32c6/esp32c6
+   Hello World! xiao_esp32c6/esp32c6/hpcore
 
 Debugging
 *********
@@ -213,7 +185,7 @@ Here is an example for building the :zephyr:code-sample:`hello_world` applicatio
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: xiao_esp32c6
+   :board: xiao_esp32c6/esp32c6/hpcore
    :goals: build flash
    :gen-args: -DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>
 
@@ -221,7 +193,7 @@ You can debug an application in the usual way. Here is an example for the :zephy
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: xiao_esp32c6
+   :board: xiao_esp32c6/esp32c6/hpcore
    :goals: debug
 
 References
diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6.dts b/boards/seeed/xiao_esp32c6/xiao_esp32c6.dts
deleted file mode 100644
index d155f5aa201..00000000000
--- a/boards/seeed/xiao_esp32c6/xiao_esp32c6.dts
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2024 Mario Paja
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/dts-v1/;
-
-#include <espressif/esp32c6/esp32c6_wroom_n4.dtsi>
-#include "xiao_esp32c6-pinctrl.dtsi"
-#include <zephyr/dt-bindings/input/input-event-codes.h>
-#include <espressif/partitions_0x0_default.dtsi>
-#include "seeed_xiao_connector.dtsi"
-
-/ {
-	model = "Seeed XIAO ESP32C6";
-	compatible = "seeed,xiao-esp32c6";
-
-	chosen {
-		zephyr,sram = &sramhp;
-		zephyr,console = &usb_serial;
-		zephyr,shell-uart = &usb_serial;
-		zephyr,flash = &flash0;
-		zephyr,code-partition = &slot0_partition;
-	};
-
-	leds: leds {
-		compatible = "gpio-leds";
-		yellow_led: led_0 {
-			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
-			label = "User LED1";
-		};
-	};
-
-	aliases {
-		led0 = &yellow_led;
-		watchdog0 = &wdt0;
-	};
-
-};
-
-&trng0 {
-	status = "okay";
-};
-
-&gpio0 {
-	status = "okay";
-};
-
-&wdt0 {
-	status = "okay";
-};
-
-&usb_serial {
-	status = "okay";
-};
-
-&i2c0 {
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-	pinctrl-0 = <&i2c0_default>;
-	pinctrl-names = "default";
-};
-
-&spi2 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	status = "okay";
-	pinctrl-0 = <&spim2_default>;
-	pinctrl-names = "default";
-};
-
-&uart0 {
-	status = "okay";
-	current-speed = <115200>;
-	pinctrl-0 = <&uart0_default>;
-	pinctrl-names = "default";
-};
diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6.yaml b/boards/seeed/xiao_esp32c6/xiao_esp32c6.yaml
deleted file mode 100644
index 50a8f099a3e..00000000000
--- a/boards/seeed/xiao_esp32c6/xiao_esp32c6.yaml
+++ /dev/null
@@ -1,18 +0,0 @@
-identifier: xiao_esp32c6
-name: XIAO ESP32C6
-type: mcu
-arch: riscv
-toolchain:
-  - zephyr
-supported:
-  - gpio
-  - watchdog
-  - uart
-  - dma
-  - spi
-  - entropy
-  - i2c
-testing:
-  ignore_tags:
-    - tracing
-vendor: seeed
diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6_defconfig b/boards/seeed/xiao_esp32c6/xiao_esp32c6_defconfig
deleted file mode 100644
index 6539bd42e59..00000000000
--- a/boards/seeed/xiao_esp32c6/xiao_esp32c6_defconfig
+++ /dev/null
@@ -1,7 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_MAIN_STACK_SIZE=2048
-CONFIG_CONSOLE=y
-CONFIG_SERIAL=y
-CONFIG_UART_CONSOLE=y
-CONFIG_GPIO=y
diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6_hpcore.dts b/boards/seeed/xiao_esp32c6/xiao_esp32c6_hpcore.dts
new file mode 100644
index 00000000000..4789d7ccf76
--- /dev/null
+++ b/boards/seeed/xiao_esp32c6/xiao_esp32c6_hpcore.dts
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2024 Mario Paja
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <espressif/esp32c6/esp32c6_wroom_n4.dtsi>
+#include "xiao_esp32c6-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <espressif/partitions_0x0_default.dtsi>
+#include "seeed_xiao_connector.dtsi"
+
+/ {
+	model = "Seeed XIAO ESP32C6 HP Core";
+	compatible = "seeed,xiao-esp32c6";
+
+	chosen {
+		zephyr,sram = &sramhp;
+		zephyr,console = &usb_serial;
+		zephyr,shell-uart = &usb_serial;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+		yellow_led: led_0 {
+			gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
+			label = "User LED1";
+		};
+	};
+
+	aliases {
+		led0 = &yellow_led;
+		watchdog0 = &wdt0;
+	};
+
+};
+
+&trng0 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&wdt0 {
+	status = "okay";
+};
+
+&usb_serial {
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+};
+
+&spi2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	pinctrl-0 = <&spim2_default>;
+	pinctrl-names = "default";
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-names = "default";
+};
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6_hpcore.yaml b/boards/seeed/xiao_esp32c6/xiao_esp32c6_hpcore.yaml
new file mode 100644
index 00000000000..7108d35e997
--- /dev/null
+++ b/boards/seeed/xiao_esp32c6/xiao_esp32c6_hpcore.yaml
@@ -0,0 +1,23 @@
+identifier: xiao_esp32c6/esp32c6/hpcore
+name: XIAO ESP32C6 HP Core
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+supported:
+  - gpio
+  - watchdog
+  - uart
+  - dma
+  - spi
+  - entropy
+  - i2c
+  - xiao_gpio
+  - xiao_i2c
+  - xiao_serial
+  - xiao_spi
+testing:
+  ignore_tags:
+    - bluetooth
+    - tracing
+vendor: seeed
diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6_hpcore_defconfig b/boards/seeed/xiao_esp32c6/xiao_esp32c6_hpcore_defconfig
new file mode 100644
index 00000000000..187793c76e8
--- /dev/null
+++ b/boards/seeed/xiao_esp32c6/xiao_esp32c6_hpcore_defconfig
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y
diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6_lpcore.dts b/boards/seeed/xiao_esp32c6/xiao_esp32c6_lpcore.dts
new file mode 100644
index 00000000000..4a2571598f6
--- /dev/null
+++ b/boards/seeed/xiao_esp32c6/xiao_esp32c6_lpcore.dts
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/dts-v1/;
+
+#include <espressif/esp32c6/esp32c6_lpcore_wroom_n4.dtsi>
+#include <espressif/partitions_0x0_default.dtsi>
+
+/ {
+	model = "Seeed XIAO ESP32C6 LP Core";
+	compatible = "seeed,xiao-esp32c6";
+
+	chosen {
+		zephyr,sram = &sramlp;
+		zephyr,code-partition = &slot0_lpcore_partition;
+	};
+};
diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6_lpcore.yaml b/boards/seeed/xiao_esp32c6/xiao_esp32c6_lpcore.yaml
new file mode 100644
index 00000000000..f2941054ba3
--- /dev/null
+++ b/boards/seeed/xiao_esp32c6/xiao_esp32c6_lpcore.yaml
@@ -0,0 +1,17 @@
+identifier: xiao_esp32c6/esp32c6/lpcore
+name: XIAO ESP32C6 LP Core
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+supported:
+  - cpu
+testing:
+  only_tags:
+    - introduction
+  ignore_tags:
+    - kernel
+    - posix
+    - chre
+    - cpp
+vendor: seeed
diff --git a/boards/seeed/xiao_esp32c6/xiao_esp32c6_lpcore_defconfig b/boards/seeed/xiao_esp32c6/xiao_esp32c6_lpcore_defconfig
new file mode 100644
index 00000000000..13d59f76b7d
--- /dev/null
+++ b/boards/seeed/xiao_esp32c6/xiao_esp32c6_lpcore_defconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+# Memory protection
+CONFIG_THREAD_STACK_INFO=n
+CONFIG_THREAD_CUSTOM_DATA=n
+
+# Boot
+CONFIG_BOOT_BANNER=n
+
+# Console
+CONFIG_PRINTK=n
+
+# Build
+CONFIG_SIZE_OPTIMIZATIONS=y
diff --git a/boards/seeed/xiao_esp32s3/doc/index.rst b/boards/seeed/xiao_esp32s3/doc/index.rst
index afc3a7e231c..1aacfe17bc4 100644
--- a/boards/seeed/xiao_esp32s3/doc/index.rst
+++ b/boards/seeed/xiao_esp32s3/doc/index.rst
@@ -38,41 +38,7 @@ Additionally, Sense variant integrates a OV2640 camera sensor, microphone and sd
 Supported Features
 ==================
 
-Current Zephyr's XIAO ESP32S3 board supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| TWAI/CAN   | on-chip    | can                                 |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | adc                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| MCPWM      | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| PCNT       | on-chip    | qdec                                |
-+------------+------------+-------------------------------------+
-| GDMA       | on-chip    | dma                                 |
-+------------+------------+-------------------------------------+
-| LCD_CAM    | on-chip    | lcd_cam                             |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -102,6 +68,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_appcpu_defconfig b/boards/seeed/xiao_esp32s3/xiao_esp32s3_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/seeed/xiao_esp32s3/xiao_esp32s3_appcpu_defconfig
+++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.yaml b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.yaml
index dea06b25bb5..b8cfc2dfb74 100644
--- a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.yaml
+++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu.yaml
@@ -15,4 +15,9 @@ supported:
   - entropy
   - pwm
   - dma
+  - xiao_adc
+  - xiao_gpio
+  - xiao_i2c
+  - xiao_serial
+  - xiao_spi
 vendor: seeed
diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_common.dtsi b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_common.dtsi
index 79860b26447..bc5ee7e87c4 100644
--- a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_common.dtsi
+++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_common.dtsi
@@ -94,3 +94,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_defconfig b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_defconfig
index 6539bd42e59..187793c76e8 100644
--- a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_defconfig
+++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_defconfig
@@ -1,6 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense.yaml b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense.yaml
index f617abbb697..18370365282 100644
--- a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense.yaml
+++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense.yaml
@@ -15,4 +15,9 @@ supported:
   - entropy
   - pwm
   - dma
+  - xiao_adc
+  - xiao_gpio
+  - xiao_i2c
+  - xiao_serial
+  - xiao_spi
 vendor: seeed
diff --git a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense_defconfig b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense_defconfig
index 6539bd42e59..187793c76e8 100644
--- a/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense_defconfig
+++ b/boards/seeed/xiao_esp32s3/xiao_esp32s3_procpu_sense_defconfig
@@ -1,6 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/seeed/xiao_mg24/Kconfig.defconfig b/boards/seeed/xiao_mg24/Kconfig.defconfig
new file mode 100644
index 00000000000..33f72abc057
--- /dev/null
+++ b/boards/seeed/xiao_mg24/Kconfig.defconfig
@@ -0,0 +1,37 @@
+# Copyright (c) 2020 Piotr Mienkowski
+# Copyright (c) 2020 TriaGnoSys GmbH
+# Copyright (c) 2025 Pete Johanson
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_XIAO_MG24
+
+config LOG_BACKEND_SWO_FREQ_HZ
+	default 875000
+	depends on LOG_BACKEND_SWO
+
+if SOC_GECKO_USE_RAIL
+
+config FPU
+	default y
+
+endif # SOC_GECKO_USE_RAIL
+
+if BT
+
+# Used to enable RF switch and selection
+config GPIO_HOGS
+	default y
+
+config FPU
+	default y
+
+config COMMON_LIBC_MALLOC_ARENA_SIZE
+	default 8192
+
+config MAIN_STACK_SIZE
+	default 3072 if PM
+	default 2304
+
+endif # BT
+
+endif # BOARD_XIAO_MG24
diff --git a/boards/seeed/xiao_mg24/Kconfig.xiao_mg24 b/boards/seeed/xiao_mg24/Kconfig.xiao_mg24
new file mode 100644
index 00000000000..441384dd416
--- /dev/null
+++ b/boards/seeed/xiao_mg24/Kconfig.xiao_mg24
@@ -0,0 +1,7 @@
+# Copyright (c) 2020 Piotr Mienkowski
+# Copyright (c) 2020 TriaGnoSys GmbH
+# Copyright (c) 2025 Pete Johanson
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_XIAO_MG24
+	select SOC_PART_NUMBER_EFR32MG24B220F1536IM48
diff --git a/boards/seeed/xiao_mg24/board.cmake b/boards/seeed/xiao_mg24/board.cmake
new file mode 100644
index 00000000000..503f4a0a2e2
--- /dev/null
+++ b/boards/seeed/xiao_mg24/board.cmake
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(openocd)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+
+board_runner_args(jlink "--device=EFR32MG24BxxxF1536")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/seeed/xiao_mg24/board.yml b/boards/seeed/xiao_mg24/board.yml
new file mode 100644
index 00000000000..fe6e7c9452e
--- /dev/null
+++ b/boards/seeed/xiao_mg24/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: xiao_mg24
+  full_name: XIAO MG24
+  vendor: seeed
+  socs:
+    - name: efr32mg24b220f1536im48
diff --git a/boards/seeed/xiao_mg24/doc/index.rst b/boards/seeed/xiao_mg24/doc/index.rst
new file mode 100644
index 00000000000..2625f5d0e58
--- /dev/null
+++ b/boards/seeed/xiao_mg24/doc/index.rst
@@ -0,0 +1,119 @@
+.. zephyr:board:: xiao_mg24
+
+Overview
+********
+
+Seeed Studio XIAO MG24 is a mini development board based on Silicon Labs' MG24. XIAO MG24 is based
+on ARM Cortex-M33 core, 32-bit RISC architecture with a maximum clock speed of 78MHz, supporting DSP
+instructions and FPU floating-point operations, possessing powerful computing power, and built-in
+AL/ML hardware accelerator MVP, which can efficiently process AI/machine learning algorithms.
+Secondly, it has excellent RF performance, with a transmission power of up to+19.5 dBm and a
+reception sensitivity as low as -105.4 dBm. It supports multiple IoT and wireless transmission
+protocols such as Matter, Thread, Zigbee, Bluetooth LE 5.3,Bluetooth mesh etc.
+
+Hardware
+********
+
+- EFR32MG24B220F1536IM48 Mighty Gecko SoC
+- CPU core: ARM Cortex®-M33 with FPU
+- Flash memory: 1536 kB
+- RAM: 256 kB
+- Transmit power: up to +20 dBm
+- Operation frequency: 2.4 GHz
+- Crystals for LFXO (32.768 kHz) and HFXO (39 MHz).
+- 3.7v LiPo power and charge support
+- User and battery charge LEDs
+
+For more information about the EFR32MG24 SoC and XIAO MG24 board, refer to these
+documents:
+
+- `EFR32MG24 Website`_
+- `EFR32MG24 Datasheet`_
+- `EFR32xG24 Reference Manual`_
+- `XIAO MG24 Wiki`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+In the following table, the column **Name** contains Pin names. For example, PA2
+means Pin number 2 on PORTA, as used in the board's datasheets and manuals.
+
++-------+-------------+------------------+
+| Name  | Function    | Usage            |
++=======+=============+==================+
+| PA7   | GPIO        | LED0             |
++-------+-------------+------------------+
+| PA8   | USART0_TX   | UART Console TX  |
++-------+-------------+------------------+
+| PA9   | USART0_RX   | UART Console RX  |
++-------+-------------+------------------+
+
+The default configuration can be found in
+:zephyr_file:`boards/seeed/xiao_mg24/xiao_mg24_defconfig`
+
+System Clock
+============
+
+The EFR32MG24 SoC is configured to use the 39 MHz external oscillator on the
+board.
+
+Serial Port
+===========
+
+The EFR32MG24 SoC has one USART and two EUSARTs.
+USART0 is connected to the board controller and is used for the console.
+
+Programming and Debugging
+*************************
+
+The XIAO MG24 contains an SAMD11 with CMSIS-DAP, allowing flashing, debugging, logging, etc. over
+the USB port. Doing so requires a version of OpenOCD that includes support for the flash on the MG24
+MCU. Until those changes are included in stock OpenOCD, the version bundled with Arduino can be
+used, or can be installed from the `OpenOCD Arduino Fork`_. When flashing, debugging, etc. you may
+need to include ``--openocd=/usr/local/bin/openocd
+--openocd-search=/usr/local/share/openocd/scripts/`` options to the command.
+
+Flashing
+========
+
+Connect the XIAO MG24 board to your host computer using the USB port. A USB CDC ACM serial port
+should appear on the host, that can be used to view logs from the flashed application.
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: xiao_mg24
+   :goals: flash
+
+Open a serial terminal (minicom, putty, etc.) connecting to the UCB CDC ACM serial port.
+
+Reset the board and you should see the following message in the terminal:
+
+.. code-block:: console
+
+   Hello World! xiao_mg24
+
+
+.. _XIAO MG24 Wiki:
+   https://wiki.seeedstudio.com/xiao_mg24_getting_started/
+
+.. _BRD4187C User Guide:
+   https://www.silabs.com/documents/public/user-guides/ug526-brd4187c-user-guide.pdf
+
+.. _EFR32MG24 Website:
+   https://www.silabs.com/wireless/zigbee/efr32mg24-series-2-socs
+
+.. _EFR32MG24 Datasheet:
+   https://www.silabs.com/documents/public/data-sheets/efr32mg24-datasheet.pdf
+
+.. _EFR32xG24 Reference Manual:
+   https://www.silabs.com/documents/public/reference-manuals/brd4187c-rm.pdf
+
+.. _OpenOCD Arduino Fork:
+   https://github.com/facchinm/OpenOCD/tree/arduino-0.12.0-rtx5
diff --git a/boards/seeed/xiao_mg24/doc/xiao_mg24.webp b/boards/seeed/xiao_mg24/doc/xiao_mg24.webp
new file mode 100644
index 00000000000..00821e38c19
Binary files /dev/null and b/boards/seeed/xiao_mg24/doc/xiao_mg24.webp differ
diff --git a/boards/seeed/xiao_mg24/pre_dt_board.cmake b/boards/seeed/xiao_mg24/pre_dt_board.cmake
new file mode 100644
index 00000000000..beb76b85552
--- /dev/null
+++ b/boards/seeed/xiao_mg24/pre_dt_board.cmake
@@ -0,0 +1,5 @@
+# Copyright (c) 2021 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+# SPI is implemented via usart so node name isn't spi@...
+list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge")
diff --git a/boards/seeed/xiao_mg24/seeed_xiao_connector.dtsi b/boards/seeed/xiao_mg24/seeed_xiao_connector.dtsi
new file mode 100644
index 00000000000..027f44c07ef
--- /dev/null
+++ b/boards/seeed/xiao_mg24/seeed_xiao_connector.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 Peter Johanson
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	xiao_d: connector {
+		compatible = "seeed,xiao-gpio";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpioc 0 0>, /* D0 */
+			   <1 0 &gpioc 1 0>, /* D1 */
+			   <2 0 &gpioc 2 0>, /* D2 */
+			   <3 0 &gpioc 3 0>, /* D3 */
+			   <4 0 &gpioc 4 0>, /* D4 */
+			   <5 0 &gpioc 5 0>, /* D5 */
+			   <6 0 &gpioc 6 0>, /* D6 */
+			   <7 0 &gpioc 7 0>, /* D7 */
+			   <8 0 &gpioa 3 0>, /* D8 */
+			   <9 0 &gpioa 4 0>, /* D9 */
+			   <10 0 &gpioa 5 0>; /* D10 */
+	};
+};
+
+xiao_spi: &eusart1 {};
+
+xiao_serial: &eusart0 {};
+
+xiao_i2c: &i2c0 {};
diff --git a/boards/seeed/xiao_mg24/support/openocd.cfg b/boards/seeed/xiao_mg24/support/openocd.cfg
new file mode 100644
index 00000000000..eed46c1687d
--- /dev/null
+++ b/boards/seeed/xiao_mg24/support/openocd.cfg
@@ -0,0 +1,25 @@
+if {[info exists env(OPENOCD_INTERFACE)]} {
+	set INTERFACE $env(OPENOCD_INTERFACE)
+} else {
+	# By default connect over Debug USB port using the CMSIS-DAP interface
+	set INTERFACE "cmsis-dap"
+}
+
+source [find interface/$INTERFACE.cfg]
+
+transport select swd
+
+set CHIPNAME efr32
+
+source [find target/efm32s2_g23.cfg]
+
+$_TARGETNAME configure -event gdb-attach {
+	echo "Debugger attaching: halting execution"
+	reset halt
+	gdb_breakpoint_override hard
+}
+
+$_TARGETNAME configure -event gdb-detach {
+	echo "Debugger detaching: resuming execution"
+	resume
+}
diff --git a/boards/seeed/xiao_mg24/xiao_mg24-pinctrl.dtsi b/boards/seeed/xiao_mg24/xiao_mg24-pinctrl.dtsi
new file mode 100644
index 00000000000..a1930b8e78b
--- /dev/null
+++ b/boards/seeed/xiao_mg24/xiao_mg24-pinctrl.dtsi
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2025 Pete Johanson
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/silabs/xg24-pinctrl.h>
+
+&pinctrl {
+	eusart0_default: eusart0_default {
+		group0 {
+			pins = <EUSART1_TX_PC6>;
+			drive-push-pull;
+			output-high;
+		};
+
+		group1 {
+			pins = <EUSART1_RX_PC7>;
+			input-enable;
+			silabs,input-filter;
+		};
+	};
+
+	eusart1_default: eusart1_default {
+		group0 {
+			pins = <EUSART1_TX_PA5>, <EUSART1_SCLK_PA3>;
+			drive-push-pull;
+			output-high;
+		};
+
+		group1 {
+			pins = <EUSART1_RX_PA4>;
+			input-enable;
+			silabs,input-filter;
+		};
+	};
+
+	usart0_default: usart0_default {
+		group0 {
+			pins = <USART0_TX_PA8>;
+			drive-push-pull;
+			output-high;
+		};
+
+		group1 {
+			pins = <USART0_RX_PA9>;
+			input-enable;
+			silabs,input-filter;
+		};
+	};
+
+	i2c0_default: i2c0_default {
+		group0 {
+			pins = <I2C0_SCL_PC4>, <I2C0_SDA_PC5>;
+			drive-open-drain;
+			bias-pull-up;
+		};
+	};
+};
diff --git a/boards/seeed/xiao_mg24/xiao_mg24.dts b/boards/seeed/xiao_mg24/xiao_mg24.dts
new file mode 100644
index 00000000000..24a2cc570ea
--- /dev/null
+++ b/boards/seeed/xiao_mg24/xiao_mg24.dts
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2025 Pete Johanson
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <silabs/efr32mg24b220f1536im48.dtsi>
+#include "xiao_mg24-pinctrl.dtsi"
+#include "seeed_xiao_connector.dtsi"
+
+/ {
+	model = "Seeed XIAO MG24";
+	compatible = "seeed,xiao_mg24", "silabs,efr32mg24";
+
+	chosen {
+		zephyr,console = &usart0;
+		zephyr,shell-uart = &usart0;
+		zephyr,uart-pipe = &usart0;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,bt-hci = &bt_hci_silabs;
+	};
+
+	/* These aliases are provided for compatibility with samples */
+	aliases {
+		led0 = &led0;
+		watchdog0 = &wdog0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led_0 {
+			gpios = <&gpioa 7 GPIO_ACTIVE_LOW>;
+			label = "LED 0";
+		};
+	};
+};
+
+&cpu0 {
+	clock-frequency = <78000000>;
+};
+
+&pstate_em3 {
+	status = "disabled";
+};
+
+&hfxo {
+	status = "okay";
+	ctune = <95>;
+	precision = <50>;
+};
+
+&lfxo {
+	status = "okay";
+	ctune = <44>;
+	precision = <50>;
+};
+
+&hfrcodpll {
+	clock-frequency = <DT_FREQ_M(78)>;
+	clocks = <&hfxo>;
+	dpll-n = <3839>;
+	dpll-m = <1919>;
+	dpll-edge = "fall";
+	dpll-lock = "phase";
+	dpll-autorecover;
+};
+
+&em23grpaclk {
+	clocks = <&lfxo>;
+};
+
+&em4grpaclk {
+	clocks = <&lfxo>;
+};
+
+&sysrtcclk {
+	clocks = <&lfxo>;
+};
+
+&wdog0clk {
+	clocks = <&lfxo>;
+};
+
+&wdog1clk {
+	clocks = <&lfxo>;
+};
+
+&usart0 {
+	current-speed = <115200>;
+	pinctrl-0 = <&usart0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&eusart0 {
+	compatible = "silabs,eusart-uart";
+	pinctrl-0 = <&eusart0_default>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+};
+
+&eusart1 {
+	compatible = "silabs,eusart-spi";
+	pinctrl-0 = <&eusart1_default>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpioc 7 GPIO_ACTIVE_LOW>;
+	clock-frequency = <4000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+};
+
+&i2c0 {
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+};
+
+&gpio {
+	location-swo = <0>;
+	status = "okay";
+};
+
+&gpioa {
+	status = "okay";
+};
+
+&gpiob {
+	status = "okay";
+
+	rf_sw: rf_sw {
+		gpio-hog;
+		gpios = <4 GPIO_ACTIVE_HIGH>;
+		output-low;
+	};
+
+	rf_sw_enable: rf_sw_enable {
+		gpio-hog;
+		gpios = <5 GPIO_ACTIVE_HIGH>;
+		output-high;
+	};
+};
+
+&gpioc {
+	status = "okay";
+
+};
+
+&gpiod {
+	status = "okay";
+};
+
+&wdog0 {
+	status = "okay";
+};
+
+&sysrtc0 {
+	status = "okay";
+};
+
+&se {
+	status = "okay";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* Reserve 48 kB for the bootloader */
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(48)>;
+			read-only;
+		};
+
+		/* Reserve 720 kB for the application in slot 0 */
+		slot0_partition: partition@c000 {
+			label = "image-0";
+			reg = <0x0000c000 0x000B8000>;
+		};
+
+		/* Reserve 720 kB for the application in slot 1 */
+		slot1_partition: partition@C4000 {
+			label = "image-1";
+			reg = <0x000C0000 0x000B8000>;
+		};
+
+		/* Set 16 kB of storage at the end of the 1536 kB of flash */
+		storage_partition: partition@17c000 {
+			label = "storage";
+			reg = <0x0017c000 DT_SIZE_K(16)>;
+		};
+	};
+};
+
+&bt_hci_silabs {
+	status = "okay";
+};
diff --git a/boards/seeed/xiao_mg24/xiao_mg24.yaml b/boards/seeed/xiao_mg24/xiao_mg24.yaml
new file mode 100644
index 00000000000..aaacd6892e8
--- /dev/null
+++ b/boards/seeed/xiao_mg24/xiao_mg24.yaml
@@ -0,0 +1,20 @@
+identifier: xiao_mg24
+name: XIAO MG24
+type: mcu
+arch: arm
+ram: 256
+flash: 1536
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - bluetooth
+  - gpio
+  - uart
+  - dma
+  - watchdog
+  - comparator
+testing:
+  ignore_tags:
+    - pm
+vendor: seeed
diff --git a/boards/seeed/xiao_mg24/xiao_mg24_defconfig b/boards/seeed/xiao_mg24/xiao_mg24_defconfig
new file mode 100644
index 00000000000..e70f8f5c519
--- /dev/null
+++ b/boards/seeed/xiao_mg24/xiao_mg24_defconfig
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARM_MPU=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_GPIO=y
diff --git a/boards/seeed/xiao_ra4m1/Kconfig.xiao_ra4m1 b/boards/seeed/xiao_ra4m1/Kconfig.xiao_ra4m1
new file mode 100644
index 00000000000..6c83b598172
--- /dev/null
+++ b/boards/seeed/xiao_ra4m1/Kconfig.xiao_ra4m1
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Pete Johanson
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_XIAO_RA4M1
+	select SOC_R7FA4M1AB3CNE
diff --git a/boards/seeed/xiao_ra4m1/board.cmake b/boards/seeed/xiao_ra4m1/board.cmake
new file mode 100644
index 00000000000..14102460aab
--- /dev/null
+++ b/boards/seeed/xiao_ra4m1/board.cmake
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Pete Johanson
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=R7FA4M1AB")
+board_runner_args(rfp "--device=RA")
+
+include(${ZEPHYR_BASE}/boards/common/rfp.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/seeed/xiao_ra4m1/board.yml b/boards/seeed/xiao_ra4m1/board.yml
new file mode 100644
index 00000000000..7a3f7e6db23
--- /dev/null
+++ b/boards/seeed/xiao_ra4m1/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: xiao_ra4m1
+  full_name: XIAO RA4M1
+  vendor: seeed
+  socs:
+  - name: r7fa4m1ab3cne
diff --git a/boards/seeed/xiao_ra4m1/doc/index.rst b/boards/seeed/xiao_ra4m1/doc/index.rst
new file mode 100644
index 00000000000..54806f46db4
--- /dev/null
+++ b/boards/seeed/xiao_ra4m1/doc/index.rst
@@ -0,0 +1,109 @@
+.. zephyr:board:: xiao_ra4m1
+
+Overview
+********
+
+The XIAO RA4M1 integrates Renesas' RA4M1 chip (32-bit ARM® Cortex®-M4 MCU up to 48 MHz) into the
+classic XIAO form factor. This development board offers 256KB Flash, 32KB SRAM, 8KB EEPROM, a USB
+2.0 connector, reset and boot buttons, 3 LEDs, a 14-bit A/D converter, a 12-bit D/A converter, and a
+CAN BUS interface. With onboard charging circuitry and low-power modes (as low as 45μA), it’s ideal
+for battery-powered applications. Sharing the same 32-bit RA4M1 microcontroller as the Arduino Uno
+R4, it's natively compatible with Arduino IDE and the extensive XIAO accessories, making it the
+perfect starting point for electronics projects.
+
+**Renesas RA4M1 Microcontroller Group**
+
+- R7FA4M1AB3CNE
+- 48-pin LQFP package
+- 48 MHz Arm® Cortex®-M4 core with Floating Point Unit (FPU)
+- 32 KB SRAM
+- 256 KB code flash memory
+- 8 KB data flash memory
+
+**Connectivity**
+
+- A Device USB connector for the Main MCU
+- Pin headers for access to power and signals
+- Bottom pads for access to signals, SWD, and battery hookup
+
+**Operating voltage**
+
+- External 5 V input through the Debug USB connector supplies the on-board power regulator to power
+  logic and interfaces on the board. External 5 V or 3.3 V may be also supplied through alternate
+  locations on the board.
+- An external 3.7 V LiPo battery can be connected and the board includes the ability to charge the
+  battery when 5 V power is supplied.
+- A yellow User LED, controlled by the Main MCU firmware
+- MCU reset push-button switch
+- MCU boot push-button switch
+
+Hardware
+********
+
+Detailed hardware features can be found at:
+
+- RA4M1 MCU: `RA4M1 Group User's Manual Hardware`_
+- XIOA RA4M1 board: `XIAO RA4M1 Website`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``xiao_ra4m1`` board can be built, flashed, and debugged
+in the usual way. See :ref:`build_an_application` and :ref:`application_run`
+for more details on building and running.
+
+Flashing
+========
+
+Program can be flashed to XIAO RA4M1 via the built in RA4 USB bootloader.
+
+To flash the program to board
+
+1. Connect the XIAO RA4M1 USB port to the host.
+
+2. Enter bootloader mode by holding the right Boot button, and tapping the left
+   Reset button. The Boot button needs to be held for a second or two after the
+   Reset has been released.
+
+3. Execute west command
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: xiao_ra4m1
+   :goals: build flash
+
+Debugging
+=========
+
+To debug on the XIAO RA4M1, connect an external debugger to the SWD pads on the
+bottom of the controller. Once completed, debugging can be performed using
+Zephyr's standard method (see :ref:`application_run`).
+The following sample demonstrates how to debug using JLink:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: xiao_ra4m1
+   :maybe-skip-config:
+   :goals: debug
+
+
+References
+**********
+- `XIAO RA4M1 Website`_
+- `RA4M1 MCU group Website`_
+
+.. _XIAO RA4M1 Website:
+   https://wiki.seeedstudio.com/getting_started_xiao_ra4m1/
+
+.. _RA4M1 MCU group Website:
+   https://www.renesas.com/us/en/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ra4m1-32-bit-microcontrollers-48mhz-arm-cortex-m4-and-lcd-controller-and-cap-touch-hmi
+
+.. _RA4M1 Group User's Manual Hardware:
+   https://www.renesas.com/us/en/document/mah/renesas-ra4m1-group-users-manual-hardware?r=1054146
diff --git a/boards/seeed/xiao_ra4m1/doc/xiao_ra4m1.webp b/boards/seeed/xiao_ra4m1/doc/xiao_ra4m1.webp
new file mode 100644
index 00000000000..99c22da3b7b
Binary files /dev/null and b/boards/seeed/xiao_ra4m1/doc/xiao_ra4m1.webp differ
diff --git a/boards/seeed/xiao_ra4m1/seeed_xiao_connector.dtsi b/boards/seeed/xiao_ra4m1/seeed_xiao_connector.dtsi
new file mode 100644
index 00000000000..bd3ee8b6815
--- /dev/null
+++ b/boards/seeed/xiao_ra4m1/seeed_xiao_connector.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 Pete Johanson
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	xiao_d: connector {
+		compatible = "seeed,xiao-gpio";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map
+			= <0 0 &ioport0 14 0>		/* D0 */
+			, <1 0 &ioport0 0 0>		/* D1 */
+			, <2 0 &ioport0 1 0>		/* D2 */
+			, <3 0 &ioport0 2 0>		/* D3 */
+			, <4 0 &ioport2 6 0>		/* D4 */
+			, <5 0 &ioport1 0 0>		/* D5 */
+			, <6 0 &ioport3 2 0>		/* D6 */
+			, <7 0 &ioport3 1 0>		/* D7 */
+			, <8 0 &ioport1 11 0>		/* D8 */
+			, <9 0 &ioport1 10 0>		/* D9 */
+			, <10 0 &ioport1 9 0>		/* D10 */
+			;
+	};
+};
+
+xiao_spi: &spi1 {};
+
+xiao_serial: &uart0 {};
diff --git a/boards/seeed/xiao_ra4m1/xiao_ra4m1-pinctrl.dtsi b/boards/seeed/xiao_ra4m1/xiao_ra4m1-pinctrl.dtsi
new file mode 100644
index 00000000000..223c5284d36
--- /dev/null
+++ b/boards/seeed/xiao_ra4m1/xiao_ra4m1-pinctrl.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 Peter Johanson
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci2_default: sci2_default {
+		group1 {
+			/* tx rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_2, 3, 2)>,
+			<RA_PSEL(RA_PSEL_SCI_2, 3, 1)>;
+		};
+	};
+
+	spi1_default: spi1_default {
+		group1 {
+			/* MISO MOSI RSPCK */
+			psels = <RA_PSEL(RA_PSEL_SPI, 1, 10)>,
+			<RA_PSEL(RA_PSEL_SPI, 1, 9)>,
+			<RA_PSEL(RA_PSEL_SPI, 1, 11)>;
+		};
+	};
+
+	usbfs_default: usbfs_default {
+		group1 {
+			/* USB_VBUS */
+			psels = <RA_PSEL(RA_PSEL_USBFS, 4, 7)>;
+			drive-strength = "high";
+		};
+	};
+};
diff --git a/boards/seeed/xiao_ra4m1/xiao_ra4m1.dts b/boards/seeed/xiao_ra4m1/xiao_ra4m1.dts
new file mode 100644
index 00000000000..1fb8d393533
--- /dev/null
+++ b/boards/seeed/xiao_ra4m1/xiao_ra4m1.dts
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
+ * Copyright (c) 2025 Pete Johanson
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <renesas/ra/ra4/r7fa4m1ab3cne.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <dt-bindings/input/input-event-codes.h>
+#include "xiao_ra4m1-pinctrl.dtsi"
+
+/ {
+	model = "Seeed XIAO-RA4M1";
+	compatible = "renesas,ra4m1", "renesas,ra";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,entropy = &trng;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1: led1 {
+			gpios = <&ioport0 11 GPIO_ACTIVE_LOW>;
+			label = "LED1";
+		};
+	};
+
+	aliases {
+		led0 = &led1;
+		watchdog0 = &wdt;
+	};
+};
+
+&uclk {
+	clocks = <&hoco>;
+	div = <1>;
+	status = "okay";
+};
+
+&usbfs {
+	pinctrl-0 = <&usbfs_default>;
+	pinctrl-names = "default";
+	maximum-speed = "full-speed";
+	status = "okay";
+
+	zephyr_udc0: udc {
+		status = "okay";
+	};
+};
+
+&hoco {
+	status = "okay";
+	clock-frequency = <48000000>;
+};
+
+&pclkblock {
+	clocks = <&hoco>;
+};
+
+&iclk {
+	div = <1>;
+};
+
+&pclka {
+	div = <1>;
+};
+
+&pclkb {
+	div = <2>;
+};
+
+&pclkc {
+	div = <1>;
+};
+
+&pclkd {
+	div = <1>;
+};
+
+&fclk {
+	div = <2>;
+};
+
+&sci2 {
+	pinctrl-0 = <&sci2_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	uart0: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
+
+&ioport0 {
+	status = "okay";
+};
+
+&ioport1 {
+	status = "okay";
+};
+
+&ioport2 {
+	status = "okay";
+};
+
+&ioport4 {
+	status = "okay";
+};
+
+&spi1 {
+	pinctrl-0 = <&spi1_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&trng {
+	status = "okay";
+};
+
+&wdt {
+	status = "okay";
+};
+
+#include "seeed_xiao_connector.dtsi"
diff --git a/boards/seeed/xiao_ra4m1/xiao_ra4m1.yaml b/boards/seeed/xiao_ra4m1/xiao_ra4m1.yaml
new file mode 100644
index 00000000000..97d6fa8518d
--- /dev/null
+++ b/boards/seeed/xiao_ra4m1/xiao_ra4m1.yaml
@@ -0,0 +1,14 @@
+identifier: xiao_ra4m1
+name: Seeeduino XIAO RA4M1
+type: mcu
+arch: arm
+ram: 32
+flash: 256
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - uart
+  - watchdog
+vendor: renesas
diff --git a/boards/seeed/xiao_ra4m1/xiao_ra4m1_defconfig b/boards/seeed/xiao_ra4m1/xiao_ra4m1_defconfig
new file mode 100644
index 00000000000..e83a94a3c64
--- /dev/null
+++ b/boards/seeed/xiao_ra4m1/xiao_ra4m1_defconfig
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Pete Johanson
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable Console
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_UART_CONSOLE=y
+CONFIG_CONSOLE=y
diff --git a/boards/seeed/xiao_rp2040/doc/index.rst b/boards/seeed/xiao_rp2040/doc/index.rst
index 0cf39c014c7..572ebb9c500 100644
--- a/boards/seeed/xiao_rp2040/doc/index.rst
+++ b/boards/seeed/xiao_rp2040/doc/index.rst
@@ -25,54 +25,7 @@ are 11 digital pins, 4 analog pins, 11 PWM Pins,1 I2C interface,
 Supported Features
 ==================
 
-The ``xiao_rp2040`` board target supports the following hardware
-features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v6m-nvic`
-   * - UART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`raspberrypi,pico-uart`
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`raspberrypi,pico-gpio`
-   * - ADC
-     - :kconfig:option:`CONFIG_ADC`
-     - :dtcompatible:`raspberrypi,pico-adc`
-   * - I2C
-     - :kconfig:option:`CONFIG_I2C`
-     - :dtcompatible:`snps,designware-i2c`
-   * - SPI
-     - :kconfig:option:`CONFIG_SPI`
-     - :dtcompatible:`raspberrypi,pico-spi`
-   * - USB Device
-     - :kconfig:option:`CONFIG_USB_DEVICE_STACK`
-     - :dtcompatible:`raspberrypi,pico-usbd`
-   * - HWINFO
-     - :kconfig:option:`CONFIG_HWINFO`
-     - N/A
-   * - Watchdog Timer (WDT)
-     - :kconfig:option:`CONFIG_WATCHDOG`
-     - :dtcompatible:`raspberrypi,pico-watchdog`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM`
-     - :dtcompatible:`raspberrypi,pico-pwm`
-   * - Flash
-     - :kconfig:option:`CONFIG_FLASH`
-     - :dtcompatible:`raspberrypi,pico-flash-controller`
-   * - Clock controller
-     - :kconfig:option:`CONFIG_CLOCK_CONTROL`
-     - :dtcompatible:`raspberrypi,pico-clock-controller`
-   * - UART (PIO)
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`raspberrypi,pico-uart-pio`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -108,6 +61,8 @@ The board uses a standard XIAO pinout, the default pin mapping is the following:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/seeed/xiao_rp2040/xiao_rp2040.dts b/boards/seeed/xiao_rp2040/xiao_rp2040.dts
index 98a700f242f..c0f96c5fdab 100644
--- a/boards/seeed/xiao_rp2040/xiao_rp2040.dts
+++ b/boards/seeed/xiao_rp2040/xiao_rp2040.dts
@@ -78,6 +78,18 @@
 		compatible = "fixed-partitions";
 		#address-cells = <1>;
 		#size-cells = <1>;
+
+		/* Reserved memory for the second stage bootloader */
+		second_stage_bootloader: partition@0 {
+			label = "second_stage_bootloader";
+			reg = <0x00000000 0x100>;
+			read-only;
+		};
+
+		/*
+		 * Usable flash. Starts at 0x100, after the bootloader. The partition
+		 * size is 2MB minus the 0x100 bytes taken by the bootloader.
+		 */
 		code_partition: partition@100 {
 			label = "code";
 			reg = <0x100 (DT_SIZE_M(2) - 0x100)>;
diff --git a/boards/seeed/xiao_rp2040/xiao_rp2040.yaml b/boards/seeed/xiao_rp2040/xiao_rp2040.yaml
index b2852757aa3..c91e45a1e2c 100644
--- a/boards/seeed/xiao_rp2040/xiao_rp2040.yaml
+++ b/boards/seeed/xiao_rp2040/xiao_rp2040.yaml
@@ -3,11 +3,10 @@ name: XIAO RP2040
 type: mcu
 arch: arm
 flash: 2048
-ram: 256
+ram: 264
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - uart
   - gpio
@@ -21,4 +20,8 @@ supported:
   - dma
   - counter
   - clock
+  - xiao_gpio
+  - xiao_i2c
+  - xiao_serial
+  - xiao_spi
 vendor: seeed
diff --git a/boards/segger/ip_k66f/Kconfig.defconfig b/boards/segger/ip_k66f/Kconfig.defconfig
index 06952ee0707..8d1d7ca0e21 100644
--- a/boards/segger/ip_k66f/Kconfig.defconfig
+++ b/boards/segger/ip_k66f/Kconfig.defconfig
@@ -22,11 +22,8 @@ if NETWORKING
 config NET_L2_ETHERNET
 	default y
 
-config ETH_MCUX_RMII_EXT_CLK
-	default y if ETH_MCUX
-
-config ETH_MCUX_NO_PHY_SMI
-	default y if ETH_MCUX
+config ETH_NXP_ENET_RMII_EXT_CLK
+	default y
 
 endif # NETWORKING
 
diff --git a/boards/segger/ip_k66f/doc/index.rst b/boards/segger/ip_k66f/doc/index.rst
index 902802eb6d3..9c816768d1e 100644
--- a/boards/segger/ip_k66f/doc/index.rst
+++ b/boards/segger/ip_k66f/doc/index.rst
@@ -32,28 +32,7 @@ For more information about the K66F SoC and IP-K66F board:
 Supported Features
 ==================
 
-The ip_k66f board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | soc flash                           |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/segger/ip_k66f/ip_k66f_defconfig`
+.. zephyr:board-supported-hw::
 
 Micrel/Microchip KSZ8794CNX Ethernet Switch is supported
 (see :zephyr:code-sample:`dsa` sample).
@@ -85,6 +64,8 @@ The K66F SoC has six UARTs. None of them are used.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
diff --git a/boards/segger/ip_k66f/ip_k66f.yaml b/boards/segger/ip_k66f/ip_k66f.yaml
index ef2de5f4467..0ce51cd967d 100644
--- a/boards/segger/ip_k66f/ip_k66f.yaml
+++ b/boards/segger/ip_k66f/ip_k66f.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - gpio
diff --git a/boards/segger/trb_stm32f407/doc/index.rst b/boards/segger/trb_stm32f407/doc/index.rst
index 0b90123c411..2d108bfc09a 100644
--- a/boards/segger/trb_stm32f407/doc/index.rst
+++ b/boards/segger/trb_stm32f407/doc/index.rst
@@ -19,28 +19,7 @@ and the datasheet.
 Supported Features
 ==================
 
-The SEGGER-TRB-STM32F407 board configuration supports the following
-hardware features:
-
-+------------+------------+------------------------------+
-| Interface  | Controller | Driver/Component             |
-+============+============+==============================+
-| NVIC       | on-chip    | nested vectored              |
-|            |            | interrupt controller         |
-+------------+------------+------------------------------+
-| SYSTICK    | on-chip    | system clock                 |
-+------------+------------+------------------------------+
-| GPIO       | on-chip    | gpio                         |
-+------------+------------+------------------------------+
-| WATCHDOG   | on-chip    | independent watchdog         |
-+------------+------------+------------------------------+
-| COUNTER    | on-chip    | rtc                          |
-+------------+------------+------------------------------+
-| RNG        | on-chip    | True Random number generator |
-+------------+------------+------------------------------+
-
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -91,6 +70,9 @@ master clock, which can be set as high as 168 MHz.
 
 Programming and Debugging
 *************************
+
+.. zephyr:board-supported-runners::
+
 The SEGGER-TRB-STM32F407 board is specially designed to test the SEGGER
 Trace-Pro debuggers, so this example assumes a J-Trace or J-Link is used.
 
diff --git a/boards/segger/trb_stm32f407/segger_trb_stm32f407.yaml b/boards/segger/trb_stm32f407/segger_trb_stm32f407.yaml
index 911c3764802..c88382807b0 100644
--- a/boards/segger/trb_stm32f407/segger_trb_stm32f407.yaml
+++ b/boards/segger/trb_stm32f407/segger_trb_stm32f407.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 192
 flash: 512
 supported:
diff --git a/boards/sensry/ganymed_bob/board.cmake b/boards/sensry/ganymed_bob/board.cmake
new file mode 100644
index 00000000000..876aa967780
--- /dev/null
+++ b/boards/sensry/ganymed_bob/board.cmake
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+board_set_flasher_ifnset(sy1xx)
+board_finalize_runner_args(sy1xx)
diff --git a/boards/sensry/ganymed_bob/doc/index.rst b/boards/sensry/ganymed_bob/doc/index.rst
index d8fdbee20ee..0726dc771ec 100644
--- a/boards/sensry/ganymed_bob/doc/index.rst
+++ b/boards/sensry/ganymed_bob/doc/index.rst
@@ -1,7 +1,6 @@
-.. _ganymed_bob:
+.. zephyr:board:: ganymed_bob
 
-Ganymed Break-Out-Board (BOB)
-#############################
+.. _ganymed_bob:
 
 Overview
 ********
@@ -14,9 +13,10 @@ Overview
 The Ganymed board hardware provides support for the Ganymed sy1xx series IoT multicore
 RISC-V SoC with optional sensor level.
 
-The SoC has the following core features:
+Hardware
+********
 
-* 32-Bit RSIC-V 1+8-core processor, up to 500MHz
+* 32-Bit RISC-V 1+8-core processor, up to 500MHz
 
   * 1x Data Acquisition Unit
   * 8x Data Processing Unit
@@ -28,117 +28,91 @@ The SoC has the following core features:
 * 512 KB Global MRAM
 * 512 KB Secure MRAM
 * CLOCK
-* RAM
-* :abbr:`32x GPIO (General Purpose Input Output)`
-* :abbr:`4x TWIM (I2C-compatible two-wire interface with MicroDMA)`
-* 4x I2S
-* :abbr:`7x SPI (Serial Peripheral Interface with MicroDMA)`
-* :abbr:`3x UART (Universal receiver-transmitter with MicroDMA)`
-* :abbr:`1x TSN (Time sensitive networking ethernet MAC with MicroDMA)`
-* 1x CAN-FD
-* 3x ADC
+* Peripherals
+
+    * :abbr:`32x GPIO (General Purpose Input Output)`
+    * :abbr:`4x TWIM (I2C-compatible two-wire interface with MicroDMA)`
+    * 4x I2S
+    * :abbr:`7x SPI (Serial Peripheral Interface with MicroDMA)`
+    * :abbr:`3x UART (Universal receiver-transmitter with MicroDMA)`
+    * :abbr:`1x TSN (Time sensitive networking ethernet MAC with MicroDMA)`
+    * 1x CAN-FD
+    * 3x ADC
+* Power section for on-board power generation and power measurement (selectable)
+
+    * USB type-C
+    * external 5V power source
+* 40-pin JTAG connector (compatible to Olimex ARM-JTAG-OCD-H)
+* USB over FTDI (connected to UART0)
+* Header for all I/Os and configuration
 
-.. figure:: img/ganymed_bob_sy120_gbm.webp
-     :align: center
-     :alt: Ganymed Break-Out-Board (BOB) equipped with SY120 GBM
+* Assembly options for the SoC
 
-     Ganymed Break-Out-Board (BOB) equipped with SY120 GBM (Credit: Sensry)
+  * SY120-GBM - Generic Base Module without top level sensors
+  * SY120-GEN1 - Generic Module type 1 with top level sensors (see below)
 
-.. figure:: img/ganymed_bob_sy120_gen1.webp
-     :align: center
-     :alt: Ganymed Break-Out-Board (BOB) equipped with SY120 GEN1
+The ``ganymed-bob/sy120-gen1`` comes with additional on-board sensors.
 
-     Ganymed Break-Out-Board (BOB) equipped with SY120 GEN1 (Credit: Sensry)
+Supported Features
+==================
 
-Hardware
-********
+.. zephyr:board-supported-hw::
 
-The Ganymed BOB has:
+For more detailed description please refer to `Ganymed BreakOut Board Documentation`_
 
-* Assembly options for the SoC include
 
-  * SY120-GBM - Generic Base Module without top level sensors
-  * SY120-GEN1 - Generic Module type 1 with top level sensors (Bosch BME680 - SPI1 , Bosch BMA456 - SPI0, Bosch BMG250 - SPI2, STMicro MIS2DH - I2C0)
+Programming and Testing
+***********************
 
-* power section for on-board power generation and power measurement (selectable)
-* 40-pin JTAG connector (compatible to Olimex ARM-JTAG-OCD-H)
-* USB over FTDI (connected to UART0)
-* Header for I/Os and additional configuration
+.. zephyr:board-supported-runners::
 
-Supported Features
-==================
+Building
+========
 
-The ``ganymed-bob/sy120-gbm`` board supports the following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| SAADC     | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| MRAM      | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| TWIM      | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| GRTC      | on-chip    | counter              |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| SPU       | on-chip    | system protection    |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| TSN       | on-chip    | ethernet MAC         |
-+-----------+------------+----------------------+
-| CAN       | on-chip    | CAN                  |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
-
-The ``ganymed-bob/sy120-gen1`` board includes all hardware features of the ``ganymed-bob/sy120-gbm`` board and comes additionally
-with these features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| BME680    | on-chip    | environment sensor   |
-+-----------+------------+----------------------+
-| BMA456    | on-chip    | acceleration sensor  |
-+-----------+------------+----------------------+
-| BMG250    | on-chip    | gyrosope sensor      |
-+-----------+------------+----------------------+
-| MIS2DH    | on-chip    | vibration sensor     |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
-
-Power
-*****
-
-* USB type-C
-* external 5V power source
-
-Programming and Debugging
-*************************
-
-Applications for the ``ganymed-bob/sy120-gbm`` board can be
-built, flashed, and debugged in the usual way. See
+Applications for the ``ganymed_bob/sy120_gbm`` board can be
+built and flashed in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
 building and running.
 
-Testing the Ganymed BreakOut Board
-**********************************
+Building the :zephyr:code-sample:`hello_world` sample:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: samples/hello_world
+   :board: ganymed_bob/sy120_gbm
+   :goals: build
+   :compact:
+
+
+Flashing
+========
+
+Test the Ganymed with a :zephyr:code-sample:`hello_world` sample.
+
+Flash the zephyr image:
 
-Test the Ganymed with a :zephyr:code-sample:`blinky` sample.
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: samples/hello_world
+   :goals: flash
+   :west-args: --serial /dev/ttyUSB0
+   :compact:
+
+
+Testing
+=======
+
+Then attach a serial console, ex. minicom / picocom / putty; Reset the target.
 The sample output should be:
 
 .. code-block:: console
 
-    Hello World! ganymed-bob/sy120-gbm
+    Hello World! ganymed_bob/sy120_gbm
+
+
+References
+**********
+
+.. target-notes::
+
+.. _`Ganymed BreakOut Board Documentation`: https://docs.sensry.net/datasheets/sy120-bob/
diff --git a/boards/sensry/ganymed_bob/ganymed_bob_sy120-pinctrl.dtsi b/boards/sensry/ganymed_bob/ganymed_bob_sy120-pinctrl.dtsi
new file mode 100644
index 00000000000..97649fe985f
--- /dev/null
+++ b/boards/sensry/ganymed_bob/ganymed_bob_sy120-pinctrl.dtsi
@@ -0,0 +1,202 @@
+/* Copyright (c) 2024 sensry.io */
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <zephyr/dt-bindings/pinctrl/sy1xx-pinctrl.h>
+
+&pinctrl {
+
+	/* UART0 */
+	/omit-if-no-ref/ uart0_tx: uart0_tx {
+		pinmux = <SY1XX_UART0_PAD_CFG0 SY1XX_PAD(0)>;
+	};
+
+	/omit-if-no-ref/ uart0_rx: uart0_rx {
+		pinmux = <SY1XX_UART0_PAD_CFG0 SY1XX_PAD(1)>;
+		input-enable;
+	};
+
+	/* UART1 */
+	/omit-if-no-ref/ uart1_tx: uart1_tx {
+		pinmux = <SY1XX_UART1_PAD_CFG0 SY1XX_PAD(0)>;
+	};
+
+	/omit-if-no-ref/ uart1_rx: uart1_rx {
+		pinmux = <SY1XX_UART1_PAD_CFG0 SY1XX_PAD(1)>;
+		input-enable;
+	};
+
+	/omit-if-no-ref/ uart1_cts: uart1_cts {
+		pinmux = <SY1XX_UART1_PAD_CFG0 SY1XX_PAD(2)>;
+	};
+
+	/omit-if-no-ref/ uart1_rts: uart1_rts {
+		pinmux = <SY1XX_UART1_PAD_CFG0 SY1XX_PAD(3)>;
+		input-enable;
+		bias-pull-up;
+	};
+
+	/* UART2 */
+	/omit-if-no-ref/ uart2_tx: uart2_tx {
+		pinmux = <SY1XX_UART2_PAD_CFG0 SY1XX_PAD(0)>;
+	};
+
+	/omit-if-no-ref/ uart2_rx: uart2_rx {
+		pinmux = <SY1XX_UART2_PAD_CFG0 SY1XX_PAD(1)>;
+		input-enable;
+	};
+
+	/omit-if-no-ref/ uart2_cts: uart2_cts {
+		pinmux = <SY1XX_UART2_PAD_CFG0 SY1XX_PAD(2)>;
+	};
+
+	/omit-if-no-ref/ uart2_rts: uart2_rts {
+		pinmux = <SY1XX_UART2_PAD_CFG0 SY1XX_PAD(3)>;
+		input-enable;
+		bias-pull-up;
+	};
+
+	/* I2C Port 0 */
+	/omit-if-no-ref/ i2c0_scl: i2c0_scl {
+		pinmux = <SY1XX_I2C0_PAD_CFG0 SY1XX_PAD(0)>;
+	};
+
+	/omit-if-no-ref/ i2c0_sda: i2c0_sda {
+		pinmux = <SY1XX_I2C0_PAD_CFG0 SY1XX_PAD(1)>;
+	};
+
+	/* I2C Port 1 */
+	/omit-if-no-ref/ i2c1_scl: i2c1_scl {
+		pinmux = <SY1XX_I2C1_PAD_CFG0 SY1XX_PAD(0)>;
+	};
+
+	/omit-if-no-ref/ i2c1_sda: i2c1_sda {
+		pinmux = <SY1XX_I2C1_PAD_CFG0 SY1XX_PAD(1)>;
+	};
+
+	/* I2C Port 2 */
+	/omit-if-no-ref/ i2c2_scl: i2c2_scl {
+		pinmux = <SY1XX_I2C2_PAD_CFG0 SY1XX_PAD(0)>;
+	};
+
+	/omit-if-no-ref/ i2c2_sda: i2c2_sda {
+		pinmux = <SY1XX_I2C2_PAD_CFG0 SY1XX_PAD(1)>;
+	};
+
+	/* I2C Port 3 */
+	/omit-if-no-ref/ i2c3_scl: i2c3_scl {
+		pinmux = <SY1XX_I2C3_PAD_CFG0 SY1XX_PAD(0)>;
+	};
+
+	/omit-if-no-ref/ i2c3_sda: i2c3_sda {
+		pinmux = <SY1XX_I2C3_PAD_CFG0 SY1XX_PAD(1)>;
+	};
+
+	/* MDIO */
+	/omit-if-no-ref/ mdio_io: mdio_io {
+		pinmux = <SY1XX_RGMII0_PAD_CFG3 SY1XX_PAD(0)>;
+		input-enable;
+	};
+
+	/omit-if-no-ref/ mdio_clk: mdio_clk {
+		pinmux = <SY1XX_RGMII0_PAD_CFG3 SY1XX_PAD(1)>;
+	};
+
+	/* RGMII */
+	/omit-if-no-ref/ rgmii_rx_ctl: rgmii_rx_ctl {
+		pinmux = <SY1XX_RGMII0_PAD_CFG0 SY1XX_PAD(0)>;
+		input-enable;
+	};
+
+	/omit-if-no-ref/ rgmii_rx_clk: rgmii_rx_clk {
+		pinmux = <SY1XX_RGMII0_PAD_CFG0 SY1XX_PAD(1)>;
+		input-enable;
+	};
+
+	/omit-if-no-ref/ rgmii_tx_ctl: rgmii_tx_ctl {
+		pinmux = <SY1XX_RGMII0_PAD_CFG0 SY1XX_PAD(2)>;
+	};
+
+	/omit-if-no-ref/ rgmii_tx_clk: rgmii_tx_clk {
+		pinmux = <SY1XX_RGMII0_PAD_CFG0 SY1XX_PAD(3)>;
+	};
+
+	/omit-if-no-ref/ rgmii_txd0: rgmii_txd0 {
+		pinmux = <SY1XX_RGMII0_PAD_CFG1 SY1XX_PAD(0)>;
+	};
+
+	/omit-if-no-ref/ rgmii_txd1: rgmii_txd1 {
+		pinmux = <SY1XX_RGMII0_PAD_CFG1 SY1XX_PAD(1)>;
+	};
+
+	/omit-if-no-ref/ rgmii_txd2: rgmii_txd2 {
+		pinmux = <SY1XX_RGMII0_PAD_CFG1 SY1XX_PAD(2)>;
+	};
+
+	/omit-if-no-ref/ rgmii_txd3: rgmii_txd3 {
+		pinmux = <SY1XX_RGMII0_PAD_CFG1 SY1XX_PAD(3)>;
+	};
+
+	/omit-if-no-ref/ rgmii_rxd0: rgmii_rxd0 {
+		pinmux = <SY1XX_RGMII0_PAD_CFG2 SY1XX_PAD(0)>;
+		input-enable;
+	};
+
+	/omit-if-no-ref/ rgmii_rxd1: rgmii_rxd1 {
+		pinmux = <SY1XX_RGMII0_PAD_CFG2 SY1XX_PAD(1)>;
+		input-enable;
+	};
+
+	/omit-if-no-ref/ rgmii_rxd2: rgmii_rxd2 {
+		pinmux = <SY1XX_RGMII0_PAD_CFG2 SY1XX_PAD(2)>;
+		input-enable;
+	};
+
+	/omit-if-no-ref/ rgmii_rxd3: rgmii_rxd3 {
+		pinmux = <SY1XX_RGMII0_PAD_CFG2 SY1XX_PAD(3)>;
+		input-enable;
+	};
+};
+
+
+&uart0 {
+	pinctrl-0 = <&uart0_tx &uart0_rx>;
+	pinctrl-names = "default";
+};
+
+&uart1 {
+	pinctrl-0 = <&uart1_tx &uart1_rx &uart1_cts &uart1_rts>;
+	pinctrl-names = "default";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2_tx &uart2_rx &uart2_cts &uart2_rts>;
+	pinctrl-names = "default";
+};
+
+&i2c0 {
+	pinctrl-0 = <&i2c0_scl &i2c0_sda>;
+	pinctrl-names = "default";
+};
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_scl &i2c1_sda>;
+	pinctrl-names = "default";
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_scl &i2c2_sda>;
+	pinctrl-names = "default";
+};
+
+&i2c3 {
+	pinctrl-0 = <&i2c3_scl &i2c3_sda>;
+	pinctrl-names = "default";
+};
+
+&eth0 {
+	pinctrl-0 = <&rgmii_rx_ctl &rgmii_rx_clk
+				 &rgmii_tx_ctl &rgmii_tx_clk
+				 &rgmii_txd0 &rgmii_txd1 &rgmii_txd2 &rgmii_txd3
+				 &rgmii_rxd0 &rgmii_rxd1 &rgmii_rxd2 &rgmii_rxd3>;
+	pinctrl-names = "default";
+};
diff --git a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.dts b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.dts
index f0c4e8c30bf..04993ff48f3 100644
--- a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.dts
+++ b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gbm.dts
@@ -3,7 +3,10 @@
 
 /dts-v1/;
 
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
 #include <sensry/ganymed-sy1xx.dtsi>
+#include "ganymed_bob_sy120-pinctrl.dtsi"
 
 / {
 
@@ -15,3 +18,26 @@
 	};
 
 };
+
+&mdio0 {
+	status = "okay";
+
+	pinctrl-0 = <&mdio_clk &mdio_io>;
+	pinctrl-names = "default";
+
+	pyh0: phy@0 {
+		compatible = "microchip,vsc8541";
+		reg = <0x0>;
+		status = "okay";
+
+		reset-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+
+		microchip,interface-type = "rgmii";
+	};
+};
+
+&eth0 {
+	status = "okay";
+
+	phy-handle = <&pyh0>;
+};
diff --git a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.dts b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.dts
index f0c4e8c30bf..04993ff48f3 100644
--- a/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.dts
+++ b/boards/sensry/ganymed_bob/ganymed_bob_sy120_gen1.dts
@@ -3,7 +3,10 @@
 
 /dts-v1/;
 
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
 #include <sensry/ganymed-sy1xx.dtsi>
+#include "ganymed_bob_sy120-pinctrl.dtsi"
 
 / {
 
@@ -15,3 +18,26 @@
 	};
 
 };
+
+&mdio0 {
+	status = "okay";
+
+	pinctrl-0 = <&mdio_clk &mdio_io>;
+	pinctrl-names = "default";
+
+	pyh0: phy@0 {
+		compatible = "microchip,vsc8541";
+		reg = <0x0>;
+		status = "okay";
+
+		reset-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+
+		microchip,interface-type = "rgmii";
+	};
+};
+
+&eth0 {
+	status = "okay";
+
+	phy-handle = <&pyh0>;
+};
diff --git a/boards/sensry/ganymed_sk/Kconfig.ganymed_sk b/boards/sensry/ganymed_sk/Kconfig.ganymed_sk
new file mode 100644
index 00000000000..fd1ea49b901
--- /dev/null
+++ b/boards/sensry/ganymed_sk/Kconfig.ganymed_sk
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_GANYMED_SK
+	select SOC_SY120_GBM if BOARD_GANYMED_SK_SY120_GBM
+	select SOC_SY120_GEN1 if BOARD_GANYMED_SK_SY120_GEN1
diff --git a/boards/sensry/ganymed_sk/board.cmake b/boards/sensry/ganymed_sk/board.cmake
new file mode 100644
index 00000000000..876aa967780
--- /dev/null
+++ b/boards/sensry/ganymed_sk/board.cmake
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+board_set_flasher_ifnset(sy1xx)
+board_finalize_runner_args(sy1xx)
diff --git a/boards/sensry/ganymed_sk/board.yml b/boards/sensry/ganymed_sk/board.yml
new file mode 100644
index 00000000000..4bcdb1ff362
--- /dev/null
+++ b/boards/sensry/ganymed_sk/board.yml
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+board:
+  name: ganymed_sk
+  full_name: Ganymed Starter Kit (SK)
+  vendor: sensry
+  socs:
+    - name: sy120_gbm
+    - name: sy120_gen1
diff --git a/boards/sensry/ganymed_sk/doc/img/ganymed_sk.webp b/boards/sensry/ganymed_sk/doc/img/ganymed_sk.webp
new file mode 100644
index 00000000000..639a9136f3f
Binary files /dev/null and b/boards/sensry/ganymed_sk/doc/img/ganymed_sk.webp differ
diff --git a/boards/sensry/ganymed_sk/doc/index.rst b/boards/sensry/ganymed_sk/doc/index.rst
new file mode 100644
index 00000000000..fbddec63913
--- /dev/null
+++ b/boards/sensry/ganymed_sk/doc/index.rst
@@ -0,0 +1,118 @@
+.. zephyr:board:: ganymed_sk
+
+.. _ganymed_sk:
+
+Overview
+********
+
+.. note::
+
+   All software for the Ganymed StarterKit (SK) is experimental and hardware availability
+   is restricted to the participants in the limited sampling program.
+
+The Ganymed board hardware provides support for the Ganymed sy1xx series IoT multicore
+RISC-V SoC with optional sensor level.
+
+Hardware
+********
+
+* 32-Bit RISC-V 1+8-core processor, up to 500MHz
+
+  * 1x Data Acquisition Unit
+  * 8x Data Processing Unit
+  * Event Bus
+  * MicroDMA
+
+* 4096 KB Global SRAM
+* 64 KB Secure SRAM
+* 512 KB Global MRAM
+* 512 KB Secure MRAM
+* CLOCK
+* Peripherals
+
+    * :abbr:`32x GPIO (General Purpose Input Output)`
+    * :abbr:`4x TWIM (I2C-compatible two-wire interface with MicroDMA)`
+    * 4x I2S
+    * :abbr:`7x SPI (Serial Peripheral Interface with MicroDMA)`
+    * :abbr:`3x UART (Universal receiver-transmitter with MicroDMA)`
+    * :abbr:`1x TSN (Time sensitive networking ethernet MAC with MicroDMA)`
+    * 1x CAN-FD
+    * 3x ADC
+* Power section for on-board power generation and power measurement (selectable)
+
+    * USB type-C
+    * external 5V power source
+* 40-pin JTAG connector (compatible to Olimex ARM-JTAG-OCD-H)
+* USB over FTDI (connected to UART0)
+* Header for all I/Os and configuration
+
+* Assembly options for the SoC
+
+  * SY120-GBM - Generic Base Module without top level sensors
+  * SY120-GEN1 - Generic Module type 1 with top level sensors (see below)
+
+The ``ganymed-sk/sy120-gen1`` comes with additional on-board sensors.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+For more detailed description please refer to `Ganymed StarterKit Board Documentation`_
+
+
+Programming and Testing
+***********************
+
+.. zephyr:board-supported-runners::
+
+Building
+========
+
+Applications for the ``ganymed_sk/sy120_gbm`` board can be
+built and flashed in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Building the :zephyr:code-sample:`hello_world` sample:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: samples/hello_world
+   :board: ganymed_sk/sy120_gbm
+   :goals: build
+   :compact:
+
+
+Flashing
+========
+
+Test the Ganymed with a :zephyr:code-sample:`hello_world` sample.
+
+Flash the zephyr image:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: samples/hello_world
+   :goals: flash
+   :west-args: --dev-id /dev/ttyUSB0
+   :compact:
+
+
+Testing
+=======
+
+Then attach a serial console, ex. minicom / picocom / putty; Reset the target.
+The sample output should be:
+
+.. code-block:: console
+
+    Hello World! ganymed_sk/sy120_gbm
+
+
+References
+**********
+
+.. target-notes::
+
+.. _`Ganymed StarterKit Board Documentation`: https://docs.sensry.net/datasheets/sy120-bob/
diff --git a/boards/sensry/ganymed_sk/ganymed_sk_sy120-pinctrl.dtsi b/boards/sensry/ganymed_sk/ganymed_sk_sy120-pinctrl.dtsi
new file mode 100644
index 00000000000..09a8fa16f88
--- /dev/null
+++ b/boards/sensry/ganymed_sk/ganymed_sk_sy120-pinctrl.dtsi
@@ -0,0 +1,202 @@
+/* Copyright (c) 2025 sensry.io */
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <zephyr/dt-bindings/pinctrl/sy1xx-pinctrl.h>
+
+&pinctrl {
+
+	/* UART0 */
+	/omit-if-no-ref/ uart0_tx: uart0_tx {
+		pinmux = <SY1XX_UART0_PAD_CFG0 SY1XX_PAD(0)>;
+	};
+
+	/omit-if-no-ref/ uart0_rx: uart0_rx {
+		pinmux = <SY1XX_UART0_PAD_CFG0 SY1XX_PAD(1)>;
+		input-enable;
+	};
+
+	/* UART1 */
+	/omit-if-no-ref/ uart1_tx: uart1_tx {
+		pinmux = <SY1XX_UART1_PAD_CFG0 SY1XX_PAD(0)>;
+	};
+
+	/omit-if-no-ref/ uart1_rx: uart1_rx {
+		pinmux = <SY1XX_UART1_PAD_CFG0 SY1XX_PAD(1)>;
+		input-enable;
+	};
+
+	/omit-if-no-ref/ uart1_cts: uart1_cts {
+		pinmux = <SY1XX_UART1_PAD_CFG0 SY1XX_PAD(2)>;
+	};
+
+	/omit-if-no-ref/ uart1_rts: uart1_rts {
+		pinmux = <SY1XX_UART1_PAD_CFG0 SY1XX_PAD(3)>;
+		input-enable;
+		bias-pull-up;
+	};
+
+	/* UART2 */
+	/omit-if-no-ref/ uart2_tx: uart2_tx {
+		pinmux = <SY1XX_UART2_PAD_CFG0 SY1XX_PAD(0)>;
+	};
+
+	/omit-if-no-ref/ uart2_rx: uart2_rx {
+		pinmux = <SY1XX_UART2_PAD_CFG0 SY1XX_PAD(1)>;
+		input-enable;
+	};
+
+	/omit-if-no-ref/ uart2_cts: uart2_cts {
+		pinmux = <SY1XX_UART2_PAD_CFG0 SY1XX_PAD(2)>;
+	};
+
+	/omit-if-no-ref/ uart2_rts: uart2_rts {
+		pinmux = <SY1XX_UART2_PAD_CFG0 SY1XX_PAD(3)>;
+		input-enable;
+		bias-pull-up;
+	};
+
+	/* I2C Port 0 */
+	/omit-if-no-ref/ i2c0_scl: i2c0_scl {
+		pinmux = <SY1XX_I2C0_PAD_CFG0 SY1XX_PAD(0)>;
+	};
+
+	/omit-if-no-ref/ i2c0_sda: i2c0_sda {
+		pinmux = <SY1XX_I2C0_PAD_CFG0 SY1XX_PAD(1)>;
+	};
+
+	/* I2C Port 1 */
+	/omit-if-no-ref/ i2c1_scl: i2c1_scl {
+		pinmux = <SY1XX_I2C1_PAD_CFG0 SY1XX_PAD(0)>;
+	};
+
+	/omit-if-no-ref/ i2c1_sda: i2c1_sda {
+		pinmux = <SY1XX_I2C1_PAD_CFG0 SY1XX_PAD(1)>;
+	};
+
+	/* I2C Port 2 */
+	/omit-if-no-ref/ i2c2_scl: i2c2_scl {
+		pinmux = <SY1XX_I2C2_PAD_CFG0 SY1XX_PAD(0)>;
+	};
+
+	/omit-if-no-ref/ i2c2_sda: i2c2_sda {
+		pinmux = <SY1XX_I2C2_PAD_CFG0 SY1XX_PAD(1)>;
+	};
+
+	/* I2C Port 3 */
+	/omit-if-no-ref/ i2c3_scl: i2c3_scl {
+		pinmux = <SY1XX_I2C3_PAD_CFG0 SY1XX_PAD(0)>;
+	};
+
+	/omit-if-no-ref/ i2c3_sda: i2c3_sda {
+		pinmux = <SY1XX_I2C3_PAD_CFG0 SY1XX_PAD(1)>;
+	};
+
+	/* MDIO */
+	/omit-if-no-ref/ mdio_io: mdio_io {
+		pinmux = <SY1XX_RGMII0_PAD_CFG3 SY1XX_PAD(0)>;
+		input-enable;
+	};
+
+	/omit-if-no-ref/ mdio_clk: mdio_clk {
+		pinmux = <SY1XX_RGMII0_PAD_CFG3 SY1XX_PAD(1)>;
+	};
+
+	/* RGMII */
+	/omit-if-no-ref/ rgmii_rx_ctl: rgmii_rx_ctl {
+		pinmux = <SY1XX_RGMII0_PAD_CFG0 SY1XX_PAD(0)>;
+		input-enable;
+	};
+
+	/omit-if-no-ref/ rgmii_rx_clk: rgmii_rx_clk {
+		pinmux = <SY1XX_RGMII0_PAD_CFG0 SY1XX_PAD(1)>;
+		input-enable;
+	};
+
+	/omit-if-no-ref/ rgmii_tx_ctl: rgmii_tx_ctl {
+		pinmux = <SY1XX_RGMII0_PAD_CFG0 SY1XX_PAD(2)>;
+	};
+
+	/omit-if-no-ref/ rgmii_tx_clk: rgmii_tx_clk {
+		pinmux = <SY1XX_RGMII0_PAD_CFG0 SY1XX_PAD(3)>;
+	};
+
+	/omit-if-no-ref/ rgmii_txd0: rgmii_txd0 {
+		pinmux = <SY1XX_RGMII0_PAD_CFG1 SY1XX_PAD(0)>;
+	};
+
+	/omit-if-no-ref/ rgmii_txd1: rgmii_txd1 {
+		pinmux = <SY1XX_RGMII0_PAD_CFG1 SY1XX_PAD(1)>;
+	};
+
+	/omit-if-no-ref/ rgmii_txd2: rgmii_txd2 {
+		pinmux = <SY1XX_RGMII0_PAD_CFG1 SY1XX_PAD(2)>;
+	};
+
+	/omit-if-no-ref/ rgmii_txd3: rgmii_txd3 {
+		pinmux = <SY1XX_RGMII0_PAD_CFG1 SY1XX_PAD(3)>;
+	};
+
+	/omit-if-no-ref/ rgmii_rxd0: rgmii_rxd0 {
+		pinmux = <SY1XX_RGMII0_PAD_CFG2 SY1XX_PAD(0)>;
+		input-enable;
+	};
+
+	/omit-if-no-ref/ rgmii_rxd1: rgmii_rxd1 {
+		pinmux = <SY1XX_RGMII0_PAD_CFG2 SY1XX_PAD(1)>;
+		input-enable;
+	};
+
+	/omit-if-no-ref/ rgmii_rxd2: rgmii_rxd2 {
+		pinmux = <SY1XX_RGMII0_PAD_CFG2 SY1XX_PAD(2)>;
+		input-enable;
+	};
+
+	/omit-if-no-ref/ rgmii_rxd3: rgmii_rxd3 {
+		pinmux = <SY1XX_RGMII0_PAD_CFG2 SY1XX_PAD(3)>;
+		input-enable;
+	};
+};
+
+
+&uart0 {
+	pinctrl-0 = <&uart0_tx &uart0_rx>;
+	pinctrl-names = "default";
+};
+
+&uart1 {
+	pinctrl-0 = <&uart1_tx &uart1_rx &uart1_cts &uart1_rts>;
+	pinctrl-names = "default";
+};
+
+&uart2 {
+	pinctrl-0 = <&uart2_tx &uart2_rx &uart2_cts &uart2_rts>;
+	pinctrl-names = "default";
+};
+
+&i2c0 {
+	pinctrl-0 = <&i2c0_scl &i2c0_sda>;
+	pinctrl-names = "default";
+};
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_scl &i2c1_sda>;
+	pinctrl-names = "default";
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_scl &i2c2_sda>;
+	pinctrl-names = "default";
+};
+
+&i2c3 {
+	pinctrl-0 = <&i2c3_scl &i2c3_sda>;
+	pinctrl-names = "default";
+};
+
+&eth0 {
+	pinctrl-0 = <&rgmii_rx_ctl &rgmii_rx_clk
+				 &rgmii_tx_ctl &rgmii_tx_clk
+				 &rgmii_txd0 &rgmii_txd1 &rgmii_txd2 &rgmii_txd3
+				 &rgmii_rxd0 &rgmii_rxd1 &rgmii_rxd2 &rgmii_rxd3>;
+	pinctrl-names = "default";
+};
diff --git a/boards/sensry/ganymed_sk/ganymed_sk_sy120_gbm.dts b/boards/sensry/ganymed_sk/ganymed_sk_sy120_gbm.dts
new file mode 100644
index 00000000000..b587927127c
--- /dev/null
+++ b/boards/sensry/ganymed_sk/ganymed_sk_sy120_gbm.dts
@@ -0,0 +1,54 @@
+/* Copyright (c) 2025 sensry.io */
+/* SPDX-License-Identifier: Apache-2.0 */
+
+/dts-v1/;
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+#include <sensry/ganymed-sy1xx.dtsi>
+#include "ganymed_sk_sy120-pinctrl.dtsi"
+
+/ {
+	aliases {
+		led0 = &green_led;
+	};
+
+	chosen {
+		zephyr,code-partition = &l2_ram_text;
+		zephyr,sram = &l2_ram_data;
+
+		zephyr,console = &uart0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		green_led: led_0 {
+			gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
+			label = "User LED";
+		};
+	};
+};
+
+&mdio0 {
+	status = "okay";
+
+	pinctrl-0 = <&mdio_clk &mdio_io>;
+	pinctrl-names = "default";
+
+	pyh0: phy@0b {
+		compatible = "microchip,vsc8541";
+		reg = <0x0b>;
+		status = "okay";
+
+		reset-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+
+		microchip,interface-type = "rgmii";
+	};
+};
+
+&eth0 {
+	status = "okay";
+
+	phy-handle = <&pyh0>;
+};
diff --git a/boards/sensry/ganymed_sk/ganymed_sk_sy120_gbm.yaml b/boards/sensry/ganymed_sk/ganymed_sk_sy120_gbm.yaml
new file mode 100644
index 00000000000..0c38ad787cb
--- /dev/null
+++ b/boards/sensry/ganymed_sk/ganymed_sk_sy120_gbm.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2025 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: ganymed_sk/sy120_gbm
+vendor: sensry
+name: Ganymed family starter kit board with SY120_GBM chip equipped
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+supported:
+  - gpio
+  - uart
+  - spi
+  - i2c
diff --git a/boards/sensry/ganymed_sk/ganymed_sk_sy120_gbm_defconfig b/boards/sensry/ganymed_sk/ganymed_sk_sy120_gbm_defconfig
new file mode 100644
index 00000000000..7162c610fc2
--- /dev/null
+++ b/boards/sensry/ganymed_sk/ganymed_sk_sy120_gbm_defconfig
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/sensry/ganymed_sk/ganymed_sk_sy120_gen1.dts b/boards/sensry/ganymed_sk/ganymed_sk_sy120_gen1.dts
new file mode 100644
index 00000000000..b587927127c
--- /dev/null
+++ b/boards/sensry/ganymed_sk/ganymed_sk_sy120_gen1.dts
@@ -0,0 +1,54 @@
+/* Copyright (c) 2025 sensry.io */
+/* SPDX-License-Identifier: Apache-2.0 */
+
+/dts-v1/;
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+#include <sensry/ganymed-sy1xx.dtsi>
+#include "ganymed_sk_sy120-pinctrl.dtsi"
+
+/ {
+	aliases {
+		led0 = &green_led;
+	};
+
+	chosen {
+		zephyr,code-partition = &l2_ram_text;
+		zephyr,sram = &l2_ram_data;
+
+		zephyr,console = &uart0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		green_led: led_0 {
+			gpios = <&gpio0 10 GPIO_ACTIVE_HIGH>;
+			label = "User LED";
+		};
+	};
+};
+
+&mdio0 {
+	status = "okay";
+
+	pinctrl-0 = <&mdio_clk &mdio_io>;
+	pinctrl-names = "default";
+
+	pyh0: phy@0b {
+		compatible = "microchip,vsc8541";
+		reg = <0x0b>;
+		status = "okay";
+
+		reset-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+
+		microchip,interface-type = "rgmii";
+	};
+};
+
+&eth0 {
+	status = "okay";
+
+	phy-handle = <&pyh0>;
+};
diff --git a/boards/sensry/ganymed_sk/ganymed_sk_sy120_gen1.yaml b/boards/sensry/ganymed_sk/ganymed_sk_sy120_gen1.yaml
new file mode 100644
index 00000000000..ebf95cc42c2
--- /dev/null
+++ b/boards/sensry/ganymed_sk/ganymed_sk_sy120_gen1.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2025 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: ganymed_sk/sy120_gen1
+vendor: sensry
+name: Ganymed family starter kit board with SY120_GEN1 chip equipped
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+supported:
+  - gpio
+  - uart
+  - spi
+  - i2c
diff --git a/boards/sensry/ganymed_sk/ganymed_sk_sy120_gen1_defconfig b/boards/sensry/ganymed_sk/ganymed_sk_sy120_gen1_defconfig
new file mode 100644
index 00000000000..7162c610fc2
--- /dev/null
+++ b/boards/sensry/ganymed_sk/ganymed_sk_sy120_gen1_defconfig
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/shields/abrobot_esp32c3_oled/Kconfig.shield b/boards/shields/abrobot_esp32c3_oled/Kconfig.shield
new file mode 100644
index 00000000000..61ddd0836b5
--- /dev/null
+++ b/boards/shields/abrobot_esp32c3_oled/Kconfig.shield
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Rick Cai <wwhheerree@hotmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SHIELD_SH1106_72X40
+	def_bool $(shields_list_contains,sh1106_72x40)
diff --git a/boards/shields/abrobot_esp32c3_oled/abrobot_sh1106_72x40.overlay b/boards/shields/abrobot_esp32c3_oled/abrobot_sh1106_72x40.overlay
new file mode 100644
index 00000000000..7160e706c87
--- /dev/null
+++ b/boards/shields/abrobot_esp32c3_oled/abrobot_sh1106_72x40.overlay
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2024 Rick Cai <wwhheerree@hotmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,display = &abrobot_72x40;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+
+	abrobot_72x40: ssd1306@3c {
+		compatible = "sinowealth,sh1106";
+		reg = <0x3c>;
+		width = <72>;
+		height = <40>;
+		segment-offset = <30>;
+		page-offset = <0>;
+		display-offset = <0xC>;
+		multiplex-ratio = <0x27>;
+		prechargep = <0x22>;
+		ready-time-ms = <10>;
+		segment-remap;
+		com-invdir;
+		use-internal-iref;
+	};
+};
diff --git a/boards/shields/abrobot_esp32c3_oled/doc/abrobot_esp32c3_oled.webp b/boards/shields/abrobot_esp32c3_oled/doc/abrobot_esp32c3_oled.webp
new file mode 100644
index 00000000000..b9961f50675
Binary files /dev/null and b/boards/shields/abrobot_esp32c3_oled/doc/abrobot_esp32c3_oled.webp differ
diff --git a/boards/shields/abrobot_esp32c3_oled/doc/index.rst b/boards/shields/abrobot_esp32c3_oled/doc/index.rst
new file mode 100644
index 00000000000..2c887814e17
--- /dev/null
+++ b/boards/shields/abrobot_esp32c3_oled/doc/index.rst
@@ -0,0 +1,31 @@
+.. _abrobot_esp32c3oled_shield:
+
+Abrobot ESP32 C3 OLED Shield
+############################
+
+Overview
+********
+
+.. figure:: abrobot_esp32c3_oled.webp
+   :align: center
+   :alt: Abrobot ESP32 C3 OLED Shield
+
+Abrobot esp32c3 oled only works with sh1106_compatible display driver. It does not support 1306 display driver commands.
+Its screen resolution is 72x40.
+Its screen start position is 30, 12.
+
+Requirements
+************
+
+This shield can only be used with esp32c3_042_oled board.
+
+Programming
+***********
+
+Set ``-b esp32c3_042_oled --shield abrobot_sh1106_72x40`` when you invoke ``west build``. For example:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/drivers/display
+   :board: esp32c3_042_oled
+   :shield: abrobot_sh1106_72x40
+   :goals: build
diff --git a/boards/shields/adafruit_2_8_tft_touch_v2/Kconfig.defconfig b/boards/shields/adafruit_2_8_tft_touch_v2/Kconfig.defconfig
index eb44e86b271..07dcda05e05 100644
--- a/boards/shields/adafruit_2_8_tft_touch_v2/Kconfig.defconfig
+++ b/boards/shields/adafruit_2_8_tft_touch_v2/Kconfig.defconfig
@@ -5,14 +5,6 @@ if SHIELD_ADAFRUIT_2_8_TFT_TOUCH_V2 || SHIELD_ADAFRUIT_2_8_TFT_TOUCH_V2_NANO
 
 if DISPLAY
 
-if INPUT
-
-# NOTE: Enable if IRQ line is available (requires to solder jumper)
-config INPUT_FT5336_INTERRUPT
-	default n
-
-endif # INPUT
-
 if LVGL
 
 config LV_Z_VDB_SIZE
diff --git a/boards/shields/adafruit_pca9685/adafruit_pca9685.overlay b/boards/shields/adafruit_pca9685/adafruit_pca9685.overlay
index 45c20a72830..8707059f21a 100644
--- a/boards/shields/adafruit_pca9685/adafruit_pca9685.overlay
+++ b/boards/shields/adafruit_pca9685/adafruit_pca9685.overlay
@@ -4,6 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <dt-bindings/pwm/pwm.h>
+
 &arduino_i2c {
 	status = "okay";
 
diff --git a/boards/shields/arduino_giga_display_shield/Kconfig.defconfig b/boards/shields/arduino_giga_display_shield/Kconfig.defconfig
new file mode 100644
index 00000000000..67fc0f5a2f6
--- /dev/null
+++ b/boards/shields/arduino_giga_display_shield/Kconfig.defconfig
@@ -0,0 +1,27 @@
+# Copyright (c) 2025 Arduino SA
+# SPDX-License-Identifier: Apache-2.0
+
+if SHIELD_ARDUINO_GIGA_DISPLAY_SHIELD
+
+if LVGL
+
+config INPUT
+	default y
+
+config LV_Z_BITS_PER_PIXEL
+	default 16
+
+config LV_DPI_DEF
+	default 128
+
+config LV_Z_FLUSH_THREAD
+	default y
+
+choice LV_COLOR_DEPTH
+	default LV_COLOR_DEPTH_16
+
+endchoice
+
+endif # LVGL
+
+endif # SHIELD_ARDUINO_GIGA_DISPLAY_SHIELD
diff --git a/boards/shields/arduino_giga_display_shield/Kconfig.shield b/boards/shields/arduino_giga_display_shield/Kconfig.shield
new file mode 100644
index 00000000000..16714a397c9
--- /dev/null
+++ b/boards/shields/arduino_giga_display_shield/Kconfig.shield
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Arduino SA
+# SPDX-License-Identifier: Apache-2.0
+
+config SHIELD_ARDUINO_GIGA_DISPLAY_SHIELD
+	def_bool $(shields_list_contains,arduino_giga_display_shield)
diff --git a/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.conf b/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.conf
new file mode 100644
index 00000000000..881770e9f68
--- /dev/null
+++ b/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.conf
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Arduino SA
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MEMC=y
+CONFIG_STM32_LTDC_RGB565=y
+CONFIG_DISPLAY_INIT_PRIORITY=87
+CONFIG_STM32_LTDC_DISABLE_FMC_BANK1=y
+CONFIG_INPUT_GT911_INTERRUPT=y
+CONFIG_STM32_LTDC_FB_USE_SHARED_MULTI_HEAP=y
diff --git a/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.defconfig b/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.defconfig
new file mode 100644
index 00000000000..d3a6c64d367
--- /dev/null
+++ b/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.defconfig
@@ -0,0 +1,22 @@
+# Copyright (c) 2025 Arduino SA
+# SPDX-License-Identifier: Apache-2.0
+
+if SHIELD_ARDUINO_GIGA_DISPLAY_SHIELD
+
+if LVGL
+
+# Double frame buffer maintained by lvgl.
+config STM32_LTDC_FB_NUM
+	default 0
+
+config LV_Z_DOUBLE_VDB
+	default y
+
+config LV_Z_FULL_REFRESH
+	default y
+
+endchoice
+
+endif # LVGL
+
+endif # SHIELD_ARDUINO_GIGA_DISPLAY_SHIELD
diff --git a/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.overlay b/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.overlay
new file mode 100644
index 00000000000..72fe8031f71
--- /dev/null
+++ b/boards/shields/arduino_giga_display_shield/boards/arduino_giga_r1_m7.overlay
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2025 Arduino SA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/display/panel.h>
+
+/ {
+	lvgl_pointer {
+		compatible = "zephyr,lvgl-pointer-input";
+		input = <&gt911>;
+	};
+
+	aliases {
+		accel0 = &gt911;
+	};
+
+	chosen {
+		zephyr,display = &zephyr_lcd_controller;
+		zephyr,touch = &gt911;
+	};
+};
+
+&sdram1 {
+	/* Frame buffer memory cache will cause screen flickering. */
+	zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
+};
+
+&zephyr_lcd_controller {
+	status = "okay";
+	ext-sdram = <&sdram1>;
+	width = <480>;
+	height = <800>;
+	def-back-color-red = <0>;
+	def-back-color-green = <0>;
+	def-back-color-blue = <0>;
+	pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
+
+	disp-on-gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>;
+	bl-ctrl-gpios = <&gpiob 12 GPIO_ACTIVE_HIGH>;
+
+	/* sitronix, st7701 */
+	display-timings {
+		compatible = "zephyr,panel-timing";
+		hsync-active = <1>;
+		vsync-active = <0>;
+		de-active = <0>;
+		pixelclk-active = <0>;
+		hback-porch = <40>;
+		hsync-len = <32>;
+		hfront-porch = <8>;
+		vback-porch = <6>;
+		vsync-len = <8>;
+		vfront-porch = <9>;
+	};
+};
+
+/* ltdc uses pll3_r as pixel clock */
+&pll3 {
+	status = "okay";
+	clocks = <&clk_hse>;
+	div-m = <16>;
+	mul-n = <110>;
+	div-p = <2>;
+	div-q = <2>;
+	div-r = <4>; /* 27.5 MHz */
+};
+
+&zephyr_mipi_dsi {
+	status = "okay";
+
+	pll-ndiv = <125>;
+	pll-idf = <4>;
+	pll-odf = <0>;
+
+	de-active-high;
+	largest-packet-size = <0>;
+
+	phy-timings = <35 35 35 35 0 10>;
+};
+
+&i2c4 {
+	pinctrl-0 = <&i2c4_scl_pb6 &i2c4_sda_ph12>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	status = "okay";
+
+	gt911: gt911@5d {
+		compatible = "goodix,gt911";
+		reg = <0x5d>;
+		alt-addr = <0x14>;
+		reset-gpios = <&gpioi 2 GPIO_ACTIVE_LOW>;
+		irq-gpios = <&gpioi 1 GPIO_ACTIVE_HIGH>;
+	};
+};
diff --git a/boards/shields/arduino_giga_display_shield/doc/img/ASX00039_00.default_1000x750.webp b/boards/shields/arduino_giga_display_shield/doc/img/ASX00039_00.default_1000x750.webp
new file mode 100644
index 00000000000..b149f1535ce
Binary files /dev/null and b/boards/shields/arduino_giga_display_shield/doc/img/ASX00039_00.default_1000x750.webp differ
diff --git a/boards/shields/arduino_giga_display_shield/doc/index.rst b/boards/shields/arduino_giga_display_shield/doc/index.rst
new file mode 100644
index 00000000000..b2834b23520
--- /dev/null
+++ b/boards/shields/arduino_giga_display_shield/doc/index.rst
@@ -0,0 +1,53 @@
+.. _arduino_giga_display_shield:
+
+Arduino GIGA Display Shield
+###########################
+
+Overview
+********
+
+The Arduino GIGA Display Shield is an extension for the Arduino GIGA R1 WiFi board.
+It provides a convenient way to add a display to your projects by offering connectors
+for various display modules, including DSI and DPI interfaces.
+Additionally, it exposes connectors for the camera interface and includes a microSD card slot.
+
+The front of the shield is equipped with the KD040WVFID026-01-C025A panel, a 3.97-inch
+TFT display with a resolution of 480*800 pixels. The panel also features a capacitive
+multi-touch screen with a GT911 controller accessible over I2C.
+
+The shield can be connected to the Arduino GIGA R1 WiFi board via the high-density connectors.
+
+More information about the shield can be found at `Arduino GIGA Display Shield website`_.
+
+.. figure:: img/ASX00039_00.default_1000x750.webp
+     :align: center
+
+     Arduino GIGA Display Shield
+
+Requirements
+************
+
+This shield can only be used with the Arduino GIGA R1 WiFi board, which provides the
+necessary connectors and interfaces for display and camera modules.
+The board must define node aliases for the required peripherals (e.g., I2C, SPI, DSI)
+to properly interface with the shield.
+
+Programming
+***********
+
+Include ``--shield arduino_giga_display_shield`` when you invoke ``west build``
+for projects utilizing this shield. For example:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/subsys/display/lvgl
+   :board: arduino_giga_r1_wifi
+   :shield: arduino_giga_display_shield
+   :goals: build
+
+References
+**********
+
+.. target-notes::
+
+.. _Arduino GIGA Display Shield website:
+   https://docs.arduino.cc/hardware/giga-display-shield/
diff --git a/boards/shields/arduino_giga_display_shield/giga_display_shield.overlay b/boards/shields/arduino_giga_display_shield/giga_display_shield.overlay
new file mode 100644
index 00000000000..5da125332db
--- /dev/null
+++ b/boards/shields/arduino_giga_display_shield/giga_display_shield.overlay
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2025 Arduino SA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&zephyr_mipi_dsi {
+	st7701: st7701@0 {
+		status = "okay";
+		compatible = "sitronix,st7701";
+		reg = <0x0>;
+		height = <800>;
+		width = <480>;
+		data-lanes = <2>;
+		pixel-format = <MIPI_DSI_PIXFMT_RGB565>;
+		rotation = <0>;
+		gip-e0 = [E0 00 00 02];
+		gip-e1 = [E1 08 00 0A 00 07 00 09 00 00 33 33];
+		gip-e2 = [E2 00 00 00 00 00 00 00 00 00 00 00 00 00];
+		gip-e3 = [E3 00 00 33 33];
+		gip-e4 = [E4 44 44];
+		gip-e5 = [E5 0E 60 A0 A0 10 60 A0 A0 0A 60 A0 A0 0C 60 A0 A0];
+		gip-e6 = [E6 00 00 33 33];
+		gip-e7 = [E7 44 44];
+		gip-e8 = [E8 0D 60 A0 A0 0F 60 A0 A0 09 60 A0 A0 0B 60 A0 A0];
+		gip-eb = [EB 02 01 E4 E4 44 00 40];
+		gip-ec = [EC 02 01];
+		gip-ed = [ED AB 89 76 54 01 FF FF FF FF FF FF 10 45 67 98 BA];
+		gip-ed = [ED AB 89 76 54 01 FF FF FF FF FF FF 10 45 67 98 BA];
+		pvgamctrl = [B0 40 C9 91 0D 12 07 02 09 09 1F 04 50 0F E4 29 DF];
+		nvgamctrl = [B1 40 CB D0 11 92 07 00 08 07 1C 06 53 12 63 EB DF];
+
+		display-timings {
+			compatible = "zephyr,panel-timing";
+			hsync-active = <1>;
+			vsync-active = <0>;
+			de-active = <0>;
+			pixelclk-active = <0>;
+			hback-porch = <40>;
+			hsync-len = <32>;
+			hfront-porch = <8>;
+			vback-porch = <6>;
+			vsync-len = <8>;
+			vfront-porch = <9>;
+		};
+	};
+};
diff --git a/boards/shields/buydisplay_2_8_tft_touch_arduino/Kconfig.defconfig b/boards/shields/buydisplay_2_8_tft_touch_arduino/Kconfig.defconfig
index 38e54dbec88..17653ad0142 100644
--- a/boards/shields/buydisplay_2_8_tft_touch_arduino/Kconfig.defconfig
+++ b/boards/shields/buydisplay_2_8_tft_touch_arduino/Kconfig.defconfig
@@ -5,14 +5,6 @@ if SHIELD_BUYDISPLAY_2_8_TFT_TOUCH_ARDUINO
 
 if DISPLAY
 
-if INPUT
-
-# NOTE: Enable if IRQ line is available (requires to solder jumper)
-config INPUT_FT5336_INTERRUPT
-	default n
-
-endif # INPUT
-
 if LVGL
 
 config LV_Z_VDB_SIZE
diff --git a/boards/shields/buydisplay_3_5_tft_touch_arduino/Kconfig.defconfig b/boards/shields/buydisplay_3_5_tft_touch_arduino/Kconfig.defconfig
index 1e95dee988e..08024b830a7 100644
--- a/boards/shields/buydisplay_3_5_tft_touch_arduino/Kconfig.defconfig
+++ b/boards/shields/buydisplay_3_5_tft_touch_arduino/Kconfig.defconfig
@@ -5,14 +5,6 @@ if SHIELD_BUYDISPLAY_3_5_TFT_TOUCH_ARDUINO
 
 if DISPLAY
 
-if INPUT
-
-# NOTE: Enable if IRQ line is available (requires to solder jumper)
-config INPUT_FT5336_INTERRUPT
-	default n
-
-endif # INPUT
-
 if LVGL
 
 config LV_Z_VDB_SIZE
diff --git a/boards/shields/eval_ad4052_ardz/Kconfig.shield b/boards/shields/eval_ad4052_ardz/Kconfig.shield
new file mode 100644
index 00000000000..c53e991ee5a
--- /dev/null
+++ b/boards/shields/eval_ad4052_ardz/Kconfig.shield
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SHIELD_EVAL_AD4052_ARDZ
+	def_bool $(shields_list_contains,eval_ad4052_ardz)
diff --git a/boards/shields/eval_ad4052_ardz/boards/apard32690_max32690_m4.overlay b/boards/shields/eval_ad4052_ardz/boards/apard32690_max32690_m4.overlay
new file mode 100644
index 00000000000..eadfaa8d469
--- /dev/null
+++ b/boards/shields/eval_ad4052_ardz/boards/apard32690_max32690_m4.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc4052_eval_ad4052_ardz 0>;
+	};
+};
diff --git a/boards/shields/eval_ad4052_ardz/doc/index.rst b/boards/shields/eval_ad4052_ardz/doc/index.rst
new file mode 100644
index 00000000000..771920affdc
--- /dev/null
+++ b/boards/shields/eval_ad4052_ardz/doc/index.rst
@@ -0,0 +1,52 @@
+.. _eval_ad4052_ardz:
+
+EVAL-AD4052-ARDZ
+#################
+
+Overview
+********
+
+The EVAL-AD4052-ARDZ is a 16-Bit SAR ADC Arduino shield powered
+by the Analog Devices AD4052.
+
+Programming
+***********
+
+Set ``--shield eval_ad4052_ardz`` when you invoke ``west build``. For example:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/drivers/adc/
+   :board: apard32690/max32690/m4
+   :shield: eval_ad4052_ardz
+   :goals: build
+
+Requirements
+************
+
+This shield can only be used with a board which provides a configuration for
+Arduino connectors and defines node aliases for SPI and GPIO interfaces (see
+:ref:`shields` for more details).
+
+References
+**********
+
+- `EVAL-AD4052-ARDZ product page`_
+- `EVAL-AD4052-ARDZ user guide`_
+- `EVAL-AD4052-ARDZ schematic`_
+- `AD4052 product page`_
+- `AD4052 data sheet`_
+
+.. _EVAL-AD4052-ARDZ product page:
+   https://www.analog.com/en/resources/evaluation-hardware-and-software/evaluation-boards-kits/eval-ad4052-ardz.html#eb-overview
+
+.. _EVAL-AD4052-ARDZ user guide:
+   https://www.analog.com/media/en/technical-documentation/user-guides/eval-ad4050-ad4052-ug-2222.pdf
+
+.. _EVAL-AD4052-ARDZ schematic:
+   https://www.analog.com/media/en/evaluation-documentation/evaluation-design-files/eval-ad4052-ardz-designsupport-files.zip
+
+.. _AD4052 product page:
+   https://www.analog.com/en/products/ad4052.html
+
+.. _AD4052 data sheet:
+   https://www.analog.com/media/en/technical-documentation/data-sheets/ad4052-ad4058.pdf
diff --git a/boards/shields/eval_ad4052_ardz/eval_ad4052_ardz.overlay b/boards/shields/eval_ad4052_ardz/eval_ad4052_ardz.overlay
new file mode 100644
index 00000000000..856bdf9877c
--- /dev/null
+++ b/boards/shields/eval_ad4052_ardz/eval_ad4052_ardz.overlay
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&arduino_spi {
+	status = "okay";
+
+	adc4052_eval_ad4052_ardz: adc4052@0 {
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_M(2)>;
+		gp1-gpios = <&arduino_header 14 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>;
+		gp0-gpios = <&arduino_header 15 (GPIO_PULL_DOWN)>;
+		conversion-gpios = <&arduino_header 12 (GPIO_ACTIVE_HIGH | MAX32_GPIO_VSEL_VDDIOH)>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#io-channel-cells = <1>;
+		status = "okay";
+		compatible = "adi,ad405x-adc";
+
+		channel@0 {
+			reg = <0>;
+			zephyr,gain = "ADC_GAIN_1";
+			zephyr,reference = "ADC_REF_INTERNAL";
+			zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+			zephyr,resolution = <16>;
+			zephyr,vref-mv = <2500>;
+		};
+	};
+};
diff --git a/boards/shields/frdm_cr20a/doc/index.rst b/boards/shields/frdm_cr20a/doc/index.rst
index 244d34df0bc..c03ae311550 100644
--- a/boards/shields/frdm_cr20a/doc/index.rst
+++ b/boards/shields/frdm_cr20a/doc/index.rst
@@ -60,6 +60,9 @@ Set ``--shield frdm_cr20a`` when you invoke ``west build``. For example:
    :shield: frdm_cr20a
    :goals: build
 
+.. include:: ../../../nxp/common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _FRDM-CR20A Website:
    https://www.nxp.com/support/developer-resources/evaluation-and-development-boards/freedom-development-boards/wireless-connectivy/freedom-development-board-for-mcr20a-wireless-transceiver:FRDM-CR20A
 
diff --git a/boards/shields/frdm_kw41z/doc/index.rst b/boards/shields/frdm_kw41z/doc/index.rst
index 6f471295e62..f710197c64a 100644
--- a/boards/shields/frdm_kw41z/doc/index.rst
+++ b/boards/shields/frdm_kw41z/doc/index.rst
@@ -64,6 +64,9 @@ host controller interface (HCI):
       :shield: frdm_kw41z
       :goals: build
 
+.. include:: ../../../nxp/common/board-footer.rst
+   :start-after: nxp-board-footer
+
 References
 **********
 
diff --git a/boards/shields/frdm_stbc_agm01/doc/index.rst b/boards/shields/frdm_stbc_agm01/doc/index.rst
index e477ba85e64..3b7043ed594 100644
--- a/boards/shields/frdm_stbc_agm01/doc/index.rst
+++ b/boards/shields/frdm_stbc_agm01/doc/index.rst
@@ -60,6 +60,9 @@ Set ``--shield frdm_stbc_agm01`` when you invoke ``west build``. For example:
    :shield: frdm_stbc_agm01
    :goals: build
 
+.. include:: ../../../nxp/common/board-footer.rst
+   :start-after: nxp-board-footer
+
 .. _FRDM-STBC-AGM01 Website:
    https://www.nxp.com/design/development-boards/freedom-development-boards/sensors/sensor-toolbox-development-boards-for-a-9-axis-solution-using-fxas21002c-and-fxos8700cq:FRDM-STBC-AGM01
 
diff --git a/boards/shields/ftdi_vm800c/ftdi_vm800c.overlay b/boards/shields/ftdi_vm800c/ftdi_vm800c.overlay
index 479ac193f25..faa68a2a43e 100644
--- a/boards/shields/ftdi_vm800c/ftdi_vm800c.overlay
+++ b/boards/shields/ftdi_vm800c/ftdi_vm800c.overlay
@@ -19,7 +19,7 @@
 		irq-gpios = <&arduino_header 8 GPIO_ACTIVE_LOW>;
 
 		pclk = <5>;
-		pclk_pol = <1>;
+		pclk-pol = <1>;
 		cspread = <1>;
 		swizzle = <0>;
 		vsize = <272>;
diff --git a/boards/shields/g1120b0mipi/Kconfig.defconfig b/boards/shields/g1120b0mipi/Kconfig.defconfig
index 5a6971aeef3..dd96ec88e06 100644
--- a/boards/shields/g1120b0mipi/Kconfig.defconfig
+++ b/boards/shields/g1120b0mipi/Kconfig.defconfig
@@ -8,9 +8,6 @@ if LVGL
 config INPUT
 	default y
 
-config INPUT_FT5336_INTERRUPT
-	default y
-
 if MIPI_DSI_MCUX_2L
 # Enable color swap in driver
 
diff --git a/boards/shields/g1120b0mipi/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf b/boards/shields/g1120b0mipi/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf
new file mode 100644
index 00000000000..768bb57bef2
--- /dev/null
+++ b/boards/shields/g1120b0mipi/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf
@@ -0,0 +1,2 @@
+CONFIG_REGULATOR=y
+CONFIG_DCACHE=n
diff --git a/boards/shields/g1120b0mipi/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay b/boards/shields/g1120b0mipi/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay
new file mode 100644
index 00000000000..e4a3ddd2720
--- /dev/null
+++ b/boards/shields/g1120b0mipi/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
+#include <zephyr/dt-bindings/display/panel.h>
+
+&zephyr_lcdif {
+	status = "okay";
+	clock-frequency = <279000000>;
+	wr-period = <14>;
+	wr-assert = <6>;
+	wr-deassert = <13>;
+	cs-assert = <1>;
+	cs-deassert = <4>;
+};
diff --git a/boards/shields/g1120b0mipi/doc/index.rst b/boards/shields/g1120b0mipi/doc/index.rst
index 8f23e7e43b5..51287b6f3f1 100644
--- a/boards/shields/g1120b0mipi/doc/index.rst
+++ b/boards/shields/g1120b0mipi/doc/index.rst
@@ -59,6 +59,9 @@ example:
    :shield: g1120b0mipi
    :goals: build
 
+.. include:: ../../../nxp/common/board-footer.rst
+   :start-after: nxp-board-footer
+
 References
 **********
 
diff --git a/boards/shields/lcd_par_s035/Kconfig.shield b/boards/shields/lcd_par_s035/Kconfig.shield
index 4dba938831b..aef614a8b27 100644
--- a/boards/shields/lcd_par_s035/Kconfig.shield
+++ b/boards/shields/lcd_par_s035/Kconfig.shield
@@ -2,4 +2,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SHIELD_LCD_PAR_S035
-	def_bool $(shields_list_contains,lcd_par_s035_8080)
+	def_bool $(shields_list_contains,lcd_par_s035_spi) ||\
+		$(shields_list_contains,lcd_par_s035_8080)
diff --git a/boards/shields/lcd_par_s035/boards/frdm_rw612.overlay b/boards/shields/lcd_par_s035/boards/frdm_rw612.overlay
new file mode 100644
index 00000000000..0f7a831e660
--- /dev/null
+++ b/boards/shields/lcd_par_s035/boards/frdm_rw612.overlay
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&lcdic {
+	/* Enable byte swapping */
+	nxp,swap-bytes;
+	/* Raise the timer0 ratio to enable longer reset delay */
+	nxp,timer0-ratio = <15>;
+	/* Lower timer1 ratio to enable shorter TE delay */
+	nxp,timer1-ratio = <0>;
+};
diff --git a/boards/shields/lcd_par_s035/doc/index.rst b/boards/shields/lcd_par_s035/doc/index.rst
index 6e29a798b5d..e7302e3fc1c 100644
--- a/boards/shields/lcd_par_s035/doc/index.rst
+++ b/boards/shields/lcd_par_s035/doc/index.rst
@@ -16,14 +16,13 @@ Requirements
 ************
 
 This shield can only be used with FRDM-X evaluation kits with a parallel LCD
-connector or a PMOD connector. Currently only the parallel LCD connector is
-enabled.
+connector or a PMOD connector.
 
 Programming
 ***********
 
-Set ``--shield lcd_par_s035_8080`` when you invoke ``west build``. For
-example:
+Set ``--shield lcd_par_s035_8080`` or ``--shield lcd_par_s035_spi`` when you
+invoke ``west build``. For example:
 
 .. zephyr-app-commands::
    :zephyr-app: samples/drivers/display
@@ -31,6 +30,9 @@ example:
    :shield: lcd_par_s035_8080
    :goals: build
 
+.. include:: ../../../nxp/common/board-footer.rst
+   :start-after: nxp-board-footer
+
 References
 **********
 
diff --git a/boards/shields/lcd_par_s035/lcd_par_s035_spi.overlay b/boards/shields/lcd_par_s035/lcd_par_s035_spi.overlay
new file mode 100644
index 00000000000..3ae939df7ad
--- /dev/null
+++ b/boards/shields/lcd_par_s035/lcd_par_s035_spi.overlay
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
+#include <zephyr/dt-bindings/spi/spi.h>
+
+/{
+	chosen {
+		zephyr,display = &st7796s;
+		zephyr,touch = &gt911_lcd_par_s035;
+	};
+
+	lvgl_pointer {
+		compatible = "zephyr,lvgl-pointer-input";
+		input = <&gt911_lcd_par_s035>;
+		swap-xy;
+		invert-y;
+	};
+};
+
+&nxp_pmod_touch_panel_i2c {
+	status = "okay";
+
+	gt911_lcd_par_s035: gt911-lcd_par_s035@5d {
+		compatible = "goodix,gt911";
+		reg = <0x5d>;
+		irq-gpios = <&nxp_lcd_pmod_connector 12 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&zephyr_mipi_dbi_spi {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	st7796s: st7796s@0 {
+		compatible = "sitronix,st7796s";
+		reg = <0>;
+		/*
+		 * Display supports minimum write cycle time of 66ns. This
+		 * means we can clock the LCDIC module at 30MHz, as
+		 * the minimum write duration will be 2x the module
+		 * clock. Note that this frequency is too fast for reading
+		 * from the display module
+		 */
+		mipi-max-frequency = <30000000>;
+		mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE";
+		duplex = <SPI_HALF_DUPLEX>;
+		height = <320>;
+		width = <480>;
+		invert-mode = "1-dot";
+		frmctl1 = [80 10];
+		bpc = [1F 50 00 20];
+		dfc = [8A 07 3B];
+		pwr1 = [80 64];
+		pwr2 = <0x13>;
+		pwr3 = <0xA7>;
+		vcmpctl = <0x09>;
+		doca = [40 8A 00 00 29 19 A5 33];
+		pgc = [F0 06 0B 07 06 05 2E 33 47 3A 17 16 2E 31];
+		ngc = [F0 09 0D 09 08 23 2E 33 46 38 13 13 2C 32];
+		madctl = <0x28>;
+		color-invert;
+	};
+};
diff --git a/boards/shields/m5stack_cardputer/Kconfig.defconfig b/boards/shields/m5stack_cardputer/Kconfig.defconfig
new file mode 100644
index 00000000000..b34ca26e4c4
--- /dev/null
+++ b/boards/shields/m5stack_cardputer/Kconfig.defconfig
@@ -0,0 +1,38 @@
+# Copyright (c) 2025 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+if SHIELD_M5STACK_CARDPUTER
+
+config INPUT
+	default y
+
+if DISK_DRIVERS
+
+config DISK_DRIVER_SDMMC
+	default y
+
+endif # DISK_DRIVERS
+
+if DISPLAY
+
+choice ST7789V_PIXEL_FORMAT
+	default ST7789V_RGB565
+endchoice
+
+if LVGL
+
+config LV_Z_BITS_PER_PIXEL
+	default 16
+
+choice LV_COLOR_DEPTH
+	default LV_COLOR_DEPTH_16
+endchoice
+
+configdefault LV_COLOR_16_SWAP
+	default y
+
+endif # LVGL
+
+endif # DISPLAY
+
+endif # SHIELD_M5STACK_CARDPUTER
diff --git a/boards/shields/m5stack_cardputer/Kconfig.shield b/boards/shields/m5stack_cardputer/Kconfig.shield
new file mode 100644
index 00000000000..3b4251f49bf
--- /dev/null
+++ b/boards/shields/m5stack_cardputer/Kconfig.shield
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+config SHIELD_M5STACK_CARDPUTER
+	def_bool $(shields_list_contains,m5stack_cardputer)
diff --git a/boards/shields/m5stack_cardputer/doc/img/m5stack_cardputer.webp b/boards/shields/m5stack_cardputer/doc/img/m5stack_cardputer.webp
new file mode 100644
index 00000000000..6d5b945ee63
Binary files /dev/null and b/boards/shields/m5stack_cardputer/doc/img/m5stack_cardputer.webp differ
diff --git a/boards/shields/m5stack_cardputer/doc/index.rst b/boards/shields/m5stack_cardputer/doc/index.rst
new file mode 100644
index 00000000000..63d426a1439
--- /dev/null
+++ b/boards/shields/m5stack_cardputer/doc/index.rst
@@ -0,0 +1,87 @@
+.. _m5stack_cardputer:
+
+M5Stack-Cardputer base shield
+#############################
+
+Overview
+********
+
+`M5Stack-Cardputer`_ is a card-sized portable computer that is perfect for engineers.
+At the heart of Cardputer is the M5StampS3, a mini development board based on the ESP32-S3
+chip.
+
+The 56-key keyboard and 1.14" TFT screen allow users to easily enter and view
+information. The on-board SPM1423 digital MEMS microphone and built-in speaker
+enable voice operations such as recording, wake-up and audio playback. The
+infrared emitter allows infrared control interaction with external devices such
+as TVs or air conditioners. And Cardputer offers a HY2.0-4P interface for
+expanding I2C sensors such as temperature and humidity sensors, light sensors
+and pressure sensors. It also includes a Micro SD card slot for expanding storage.
+
+The device is powered by an internal 120mAh+1400mAh (in the base) lithium
+battery solution.
+
+.. figure:: img/m5stack_cardputer.webp
+        :align: center
+        :alt: M5Stack-Cardputer
+        :width: 400 px
+
+        M5Stack-Cardputer
+
+.. note::
+   The NS4186 I2S Codec, SPM1423 microphone, IR LED and Keyboard functionality is not implemented yet.
+
+Pins Assignments
+================
+
++-------------------+---------------+
+| ESP32-S3 GPIO Pin | Function      |
++===================+======+========+
+| 0                 | User Button   |
++-------------------+---------------+
+| 1                 | I2C SCL       |
++-------------------+---------------+
+| 2                 | I2C SDA       |
++-------------------+---------------+
+| 10                | VBAT Voltage  |
++-------------------+---------------+
+| 33                | LCD RST       |
++-------------------+---------------+
+| 34                | LCD RS/DC     |
++-------------------+---------------+
+| 35                | LCD MOSI      |
++-------------------+---------------+
+| 36                | LCD SCLK      |
++-------------------+---------------+
+| 37                | LCD CS        |
++-------------------+---------------+
+| 38                | LCD Backlight |
++-------------------+---------------+
+| 39                | uSD MISO      |
++-------------------+---------------+
+| 40                | uSD SCLK      |
++-------------------+---------------+
+| 12                | uSD CS        |
++-------------------+---------------+
+| 14                | uSD MOSI      |
++-------------------+---------------+
+
+Programming
+***********
+
+Set ``--shield m5stack_cardputer`` when you invoke ``west build``.
+For example:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/drivers/display
+   :board: m5stack_stamps3/esp32s3/procpu
+   :shield: m5stack_cardputer
+   :goals: build
+
+References
+**********
+
+.. target-notes::
+
+.. _M5Stack-Cardputer:
+   https://docs.m5stack.com/en/core/Cardputer
diff --git a/boards/shields/m5stack_cardputer/m5stack_cardputer.overlay b/boards/shields/m5stack_cardputer/m5stack_cardputer.overlay
new file mode 100644
index 00000000000..0009e3228fe
--- /dev/null
+++ b/boards/shields/m5stack_cardputer/m5stack_cardputer.overlay
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2025 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 9>;
+	};
+
+	aliases {
+		/delete-property/ led-strip;
+	};
+
+	chosen {
+		zephyr,display = &st7789v;
+	};
+
+	mipi_dbi {
+		compatible = "zephyr,mipi-dbi-spi";
+		spi-dev = <&spi2>;
+		dc-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+		write-only;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		st7789v: st7789v@0 {
+			compatible = "sitronix,st7789v";
+			reg = <0>;
+			mipi-max-frequency = <20000000>;
+
+			width = <135>;
+			height = <240>;
+			x-offset = <53>;
+			y-offset = <40>;
+
+			vcom = <0x28>;
+			gctrl = <0x35>;
+			vrhs = <0x10>;
+			vdvs = <0x20>;
+			mdac = <0x00>;
+			gamma = <0x01>;
+			colmod = <0x55>;
+			lcm = <0x2c>;
+			porch-param = [0c 0c 00 33 33];
+			cmd2en-param = [5a 69 02 00];
+			pwctrl1-param = [a4 a1];
+			pvgam-param = [d0 00 02 07 0a 28 32 44 42 06 0e 12 14 17];
+			nvgam-param = [d0 00 02 07 0a 28 31 54 47 0e 1c 17 1b 1e];
+			ram-param = [00 F0];
+			rgb-param = [40 02 14];
+			mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE";
+		};
+	};
+};
+
+/delete-node/ &status_rgb_led;
+
+&pinctrl {
+	spim2_default: spim2_default {
+		group1 {
+			pinmux = <SPIM2_SCLK_GPIO36>,
+				 <SPIM2_CSEL_GPIO37>;
+		};
+
+		group2 {
+			pinmux = <SPIM2_MOSI_GPIO35>;
+			output-low;
+		};
+	};
+
+	spim3_default: spim3_default {
+		group1 {
+			pinmux = <SPIM3_SCLK_GPIO40>,
+				 <SPIM3_MISO_GPIO39>;
+		};
+
+		group2 {
+			pinmux = <SPIM3_MOSI_GPIO14>;
+			output-low;
+		};
+	};
+
+	i2c1_default: i2c1_default {
+		group1 {
+			pinmux = <I2C1_SDA_GPIO1>,
+				 <I2C1_SCL_GPIO2>;
+			bias-pull-up;
+			drive-open-drain;
+			output-high;
+		};
+	};
+};
+
+&adc0 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@9 {
+		reg = <9>;
+		zephyr,gain = "ADC_GAIN_1_4";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
+
+&spi3 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+	pinctrl-0 = <&spim3_default>;
+	pinctrl-names = "default";
+	clock-frequency = <25000000>;
+	cs-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; /* TF-CARD */
+
+	sd0: sd@0 {
+		compatible = "zephyr,sdhc-spi-slot";
+		reg = <0>;
+		status = "okay";
+		spi-max-frequency = <25000000>;
+
+		mmc {
+			compatible = "zephyr,sdmmc-disk";
+			disk-name = "SD";
+			status = "okay";
+		};
+	};
+};
+
+&gpio1 {
+	status = "okay";
+
+	lcd-backlight {
+		gpio-hog;
+		gpios = <6 GPIO_ACTIVE_HIGH>;
+		output-high;
+	};
+};
diff --git a/boards/shields/nxp_btb44_ov5640/doc/index.rst b/boards/shields/nxp_btb44_ov5640/doc/index.rst
index 07a7d24e7d1..2fc16104377 100644
--- a/boards/shields/nxp_btb44_ov5640/doc/index.rst
+++ b/boards/shields/nxp_btb44_ov5640/doc/index.rst
@@ -125,6 +125,9 @@ Set ``--shield nxp_btb44_ov5640`` when you invoke ``west build``. For example:
    :shield: nxp_btb44_ov5640
    :goals: build
 
+.. include:: ../../../nxp/common/board-footer.rst
+   :start-after: nxp-board-footer
+
 References
 **********
 
diff --git a/boards/shields/p3t1755dp_ard_i2c/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay b/boards/shields/p3t1755dp_ard_i2c/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay
new file mode 100644
index 00000000000..9198366967e
--- /dev/null
+++ b/boards/shields/p3t1755dp_ard_i2c/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&flexcomm8_lpi2c8 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
diff --git a/boards/shields/rk043fn02h_ct/Kconfig.defconfig b/boards/shields/rk043fn02h_ct/Kconfig.defconfig
index f2b199d9169..65edfb50c7a 100644
--- a/boards/shields/rk043fn02h_ct/Kconfig.defconfig
+++ b/boards/shields/rk043fn02h_ct/Kconfig.defconfig
@@ -8,9 +8,6 @@ if LVGL
 config INPUT
 	default y
 
-config INPUT_FT5336_INTERRUPT
-	default y
-
 # LVGL should allocate buffers equal to size of display
 config LV_Z_VDB_SIZE
 	default 100
diff --git a/boards/shields/rk043fn02h_ct/doc/index.rst b/boards/shields/rk043fn02h_ct/doc/index.rst
index 6b80c91f72c..9e398b77348 100644
--- a/boards/shields/rk043fn02h_ct/doc/index.rst
+++ b/boards/shields/rk043fn02h_ct/doc/index.rst
@@ -96,6 +96,9 @@ example:
    :shield: rk043fn02h_ct
    :goals: build
 
+.. include:: ../../../nxp/common/board-footer.rst
+   :start-after: nxp-board-footer
+
 References
 **********
 
diff --git a/boards/shields/rk043fn66hs_ctg/doc/index.rst b/boards/shields/rk043fn66hs_ctg/doc/index.rst
index b600afedc30..1191f2a22f0 100644
--- a/boards/shields/rk043fn66hs_ctg/doc/index.rst
+++ b/boards/shields/rk043fn66hs_ctg/doc/index.rst
@@ -96,6 +96,9 @@ example:
    :shield: rk043fn66hs_ctg
    :goals: build
 
+.. include:: ../../../nxp/common/board-footer.rst
+   :start-after: nxp-board-footer
+
 References
 **********
 
diff --git a/boards/shields/rk055hdmipi4m/doc/index.rst b/boards/shields/rk055hdmipi4m/doc/index.rst
index 32975c5c962..17bf9ea4a34 100644
--- a/boards/shields/rk055hdmipi4m/doc/index.rst
+++ b/boards/shields/rk055hdmipi4m/doc/index.rst
@@ -59,6 +59,9 @@ example:
    :shield: rk055hdmipi4m
    :goals: build
 
+.. include:: ../../../nxp/common/board-footer.rst
+   :start-after: nxp-board-footer
+
 References
 **********
 
diff --git a/boards/shields/rk055hdmipi4ma0/Kconfig.defconfig b/boards/shields/rk055hdmipi4ma0/Kconfig.defconfig
index 938ebb3b070..27b6d9befc4 100644
--- a/boards/shields/rk055hdmipi4ma0/Kconfig.defconfig
+++ b/boards/shields/rk055hdmipi4ma0/Kconfig.defconfig
@@ -14,7 +14,7 @@ endif # DISPLAY
 
 if LVGL
 
-# Configure LVGL to use touchscreen with KSCAN API
+# Configure LVGL to use touchscreen
 
 config INPUT
 	default y
diff --git a/boards/shields/rk055hdmipi4ma0/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf b/boards/shields/rk055hdmipi4ma0/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf
new file mode 100644
index 00000000000..74ec3e6b695
--- /dev/null
+++ b/boards/shields/rk055hdmipi4ma0/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.conf
@@ -0,0 +1,5 @@
+CONFIG_MCUX_DCNANO_LCDIF_EXTERNAL_FB_MEM=y
+CONFIG_MCUX_DCNANO_LCDIF_EXTERNAL_FB_ADDR=0x60000000
+CONFIG_MCUX_DCNANO_LCDIF_MAINTAIN_CACHE=n
+CONFIG_HEAP_MEM_POOL_SIZE=40000
+CONFIG_REGULATOR=y
diff --git a/boards/shields/rk055hdmipi4ma0/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay b/boards/shields/rk055hdmipi4ma0/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay
new file mode 100644
index 00000000000..b8b5fec6fb2
--- /dev/null
+++ b/boards/shields/rk055hdmipi4ma0/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&zephyr_lcdif {
+	compatible = "nxp,dcnano-lcdif";
+	version = "DC8000";
+	display-timings {
+		clock-frequency = <29333333>;
+	};
+};
+
+&zephyr_mipi_dsi {
+	/* Use lower DPHY clock since RT700 uses AUDIO pll pfd2 as source,
+	 * and its max allowed clock frequency is
+	 * 532.48 x 18 / 16 = 599.04MHz. In this case the 60fps cannot be used, use 30fps instead.
+	 */
+	phy-clock = <396000000>;
+};
diff --git a/boards/shields/rk055hdmipi4ma0/doc/index.rst b/boards/shields/rk055hdmipi4ma0/doc/index.rst
index a5d93b454e6..d34e4bfa80b 100644
--- a/boards/shields/rk055hdmipi4ma0/doc/index.rst
+++ b/boards/shields/rk055hdmipi4ma0/doc/index.rst
@@ -59,6 +59,9 @@ example:
    :shield: rk055hdmipi4ma0
    :goals: build
 
+.. include:: ../../../nxp/common/board-footer.rst
+   :start-after: nxp-board-footer
+
 References
 **********
 
diff --git a/boards/shields/rpi_pico_uno_flexypin/doc/index.rst b/boards/shields/rpi_pico_uno_flexypin/doc/index.rst
index f7d19831e6e..06aa96c6add 100644
--- a/boards/shields/rpi_pico_uno_flexypin/doc/index.rst
+++ b/boards/shields/rpi_pico_uno_flexypin/doc/index.rst
@@ -1,7 +1,7 @@
 .. _rpi_pico_uno_flexypin:
 
-RaspberryPi Pico to UNO FlexyPin Adapter
-########################################
+Raspberry Pi Pico to UNO FlexyPin Adapter
+#########################################
 
 Overview
 ********
@@ -16,10 +16,10 @@ to the Arduino UNO form factor.
 
 .. image:: img/rpi_pico_uno_flexypin.png
      :align: center
-     :alt: RaspberryPi Pico to UNO FlexyPin Adapter
+     :alt: Raspberry Pi Pico to UNO FlexyPin Adapter
 
-Pins Assignment of the RaspberryPi Pico to UNO FlexyPin Adapter
-===============================================================
+Pins Assignment of the Raspberry Pi Pico to UNO FlexyPin Adapter
+================================================================
 
 +---------------------+------------+
 | Rpi-Pico Pin        | UNO Header |
diff --git a/boards/shields/rtk7eka6m3b00001bu/Kconfig.defconfig b/boards/shields/rtk7eka6m3b00001bu/Kconfig.defconfig
new file mode 100644
index 00000000000..4da6abdda96
--- /dev/null
+++ b/boards/shields/rtk7eka6m3b00001bu/Kconfig.defconfig
@@ -0,0 +1,39 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SHIELD_RTK7EKA6M3B00001BU
+
+if LVGL
+
+# Configure LVGL to use touchscreen with input API
+
+config INPUT
+	default y
+
+# LVGL should allocate buffers equal to size of display
+config LV_Z_VDB_SIZE
+	default 100
+
+# Enable double buffering
+config LV_Z_DOUBLE_VDB
+	default y
+
+# Force full refresh. This prevents memory copy associated with partial
+# display refreshes, which is not necessary for the GLCDC driver
+config LV_Z_FULL_REFRESH
+	default y
+
+config LV_Z_BITS_PER_PIXEL
+	default 32
+
+# Use offloaded render thread
+config LV_Z_FLUSH_THREAD
+	default y
+
+choice LV_COLOR_DEPTH
+	default LV_COLOR_DEPTH_32
+endchoice
+
+endif # LVGL
+
+endif # SHIELD_RTK7EKA6M3B00001BU
diff --git a/boards/shields/rtk7eka6m3b00001bu/Kconfig.shield b/boards/shields/rtk7eka6m3b00001bu/Kconfig.shield
new file mode 100644
index 00000000000..a880c767f29
--- /dev/null
+++ b/boards/shields/rtk7eka6m3b00001bu/Kconfig.shield
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SHIELD_RTK7EKA6M3B00001BU
+	def_bool $(shields_list_contains,rtk7eka6m3b00001bu)
diff --git a/boards/shields/rtk7eka6m3b00001bu/boards/ek_ra8d1.overlay b/boards/shields/rtk7eka6m3b00001bu/boards/ek_ra8d1.overlay
new file mode 100644
index 00000000000..7c689e77bfe
--- /dev/null
+++ b/boards/shields/rtk7eka6m3b00001bu/boards/ek_ra8d1.overlay
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	renesas_parallel_graphics_connector: parallel-graphics-connector {
+		compatible = "renesas,ra-parallel-graphics-header";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map =	<1 0 &ioport4 4 0>,	/* DISP_BLEN */
+				<2 0 &ioport5 11 0>,	/* IIC_SDA */
+				<3 0 &ioport5 10 0>,	/* DISP_INT */
+				<4 0 &ioport5 12 0>,	/* IIC_SCL */
+				<6 0 &ioporta 1 0>;	/* DISP_RST */
+	};
+};
+
+&port_irq3 {
+	interrupts = <90 1>;
+	status = "okay";
+};
+
+&pinctrl {
+	glcdc_default: glcdc_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_GLCDC, 8, 5)>, /* LCDC_TCON0 */
+				<RA_PSEL(RA_PSEL_GLCDC, 8, 7)>, /* LCDC_TCON1 */
+				<RA_PSEL(RA_PSEL_GLCDC, 5, 13)>, /* LCDC_TCON2 */
+				<RA_PSEL(RA_PSEL_GLCDC, 5, 15)>, /* LCDC_TCON3 */
+				<RA_PSEL(RA_PSEL_GLCDC, 9, 14)>, /* LCDC_DATA00 */
+				<RA_PSEL(RA_PSEL_GLCDC, 9, 15)>, /* LCDC_DATA01 */
+				<RA_PSEL(RA_PSEL_GLCDC, 9, 10)>, /* LCDC_DATA02 */
+				<RA_PSEL(RA_PSEL_GLCDC, 9, 11)>, /* LCDC_DATA03 */
+				<RA_PSEL(RA_PSEL_GLCDC, 9, 12)>, /* LCDC_DATA04 */
+				<RA_PSEL(RA_PSEL_GLCDC, 9, 13)>, /* LCDC_DATA05 */
+				<RA_PSEL(RA_PSEL_GLCDC, 9, 4)>, /* LCDC_DATA06 */
+				<RA_PSEL(RA_PSEL_GLCDC, 9, 3)>, /* LCDC_DATA07 */
+				<RA_PSEL(RA_PSEL_GLCDC, 9, 2)>, /* LCDC_DATA08 */
+				<RA_PSEL(RA_PSEL_GLCDC, 2, 7)>, /* LCDC_DATA09 */
+				<RA_PSEL(RA_PSEL_GLCDC, 7, 11)>, /* LCDC_DATA10 */
+				<RA_PSEL(RA_PSEL_GLCDC, 7, 12)>, /* LCDC_DATA11 */
+				<RA_PSEL(RA_PSEL_GLCDC, 7, 13)>, /* LCDC_DATA12 */
+				<RA_PSEL(RA_PSEL_GLCDC, 7, 14)>, /* LCDC_DATA13 */
+				<RA_PSEL(RA_PSEL_GLCDC, 7, 15)>, /* LCDC_DATA14 */
+				<RA_PSEL(RA_PSEL_GLCDC, 11, 7)>, /* LCDC_DATA15 */
+				<RA_PSEL(RA_PSEL_GLCDC, 11, 6)>, /* LCDC_DATA16 */
+				<RA_PSEL(RA_PSEL_GLCDC, 11, 5)>, /* LCDC_DATA17 */
+				<RA_PSEL(RA_PSEL_GLCDC, 11, 1)>, /* LCDC_DATA18 */
+				<RA_PSEL(RA_PSEL_GLCDC, 11, 4)>, /* LCDC_DATA19 */
+				<RA_PSEL(RA_PSEL_GLCDC, 11, 3)>, /* LCDC_DATA20 */
+				<RA_PSEL(RA_PSEL_GLCDC, 11, 2)>, /* LCDC_DATA21 */
+				<RA_PSEL(RA_PSEL_GLCDC, 11, 0)>, /* LCDC_DATA22 */
+				<RA_PSEL(RA_PSEL_GLCDC, 7, 7)>, /* LCDC_DATA23 */
+				<RA_PSEL(RA_PSEL_GLCDC, 8, 6)>, /* LCDC_CLK */
+				<RA_PSEL(RA_PSEL_GLCDC, 5, 14)>; /* LCDC_EXTCLK */
+		};
+	};
+
+	iic1_default: iic1_default {
+		group1 {
+			/* SCL1 SDA1 */
+			psels = <RA_PSEL(RA_PSEL_I2C, 5, 12)>,
+				<RA_PSEL(RA_PSEL_I2C, 5, 11)>;
+			drive-strength = "medium";
+		};
+	};
+};
+
+&zephyr_lcdif {
+	pinctrl-0 = <&glcdc_default>;
+	pinctrl-names = "default";
+	output-pin-hsync = "TCON_PIN_1";
+	output-pin-vsync = "TCON_PIN_0";
+	output-pin-de = "TCON_PIN_2";
+};
+
+&iic1 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clock-frequency = <DT_FREQ_K(100)>;
+	pinctrl-0 = <&iic1_default>;
+	pinctrl-names = "default";
+};
diff --git a/boards/shields/rtk7eka6m3b00001bu/doc/index.rst b/boards/shields/rtk7eka6m3b00001bu/doc/index.rst
new file mode 100644
index 00000000000..2ae42ca9255
--- /dev/null
+++ b/boards/shields/rtk7eka6m3b00001bu/doc/index.rst
@@ -0,0 +1,49 @@
+.. _rtk7eka6m3b00001bu:
+
+RTK7EKA6M3B00001BU Display
+##########################
+
+Overview
+********
+
+The Graphics Expansion Board includes a 4.3-inch 480x272 pixel TFT color LCD with a
+capacitive touch overlay.
+
+This display uses a 40-pin connector header.
+
+Pins Assignment of the Renesas RTK7EKA6M3B00001BU Display
+=========================================================
+
++-----------------+--------------------------+
+| Connector Pin   | Function                 |
++=================+==========================+
+| 1               | Display backlight enable |
++-----------------+--------------------------+
+| 2               | Touch ctrl I2C SDA       |
++-----------------+--------------------------+
+| 3               | External interrupt       |
++-----------------+--------------------------+
+| 4               | Touch ctrl I2C SCL       |
++-----------------+--------------------------+
+| 6               | Display reset            |
++-----------------+--------------------------+
+
+Hardware Requirements:
+**********************
+
+Supported Renesas RA boards: EK-RA8D1
+
+- 1 x RA Board
+- 1 x Micro USB cable
+
+Programming
+***********
+
+Set ``--shield=rtk7eka6m3b00001bu`` when you invoke ``west build``. For
+example:
+
+.. zephyr-app-commands::
+   :zephyr-app: tests/drivers/display/display_read_write
+   :board: ek_ra8d1
+   :shield: rtk7eka6m3b00001bu
+   :goals: build
diff --git a/boards/shields/rtk7eka6m3b00001bu/rtk7eka6m3b00001bu.overlay b/boards/shields/rtk7eka6m3b00001bu/rtk7eka6m3b00001bu.overlay
new file mode 100644
index 00000000000..1a374de75e6
--- /dev/null
+++ b/boards/shields/rtk7eka6m3b00001bu/rtk7eka6m3b00001bu.overlay
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/display/panel.h>
+
+/ {
+	chosen {
+		zephyr,display = &zephyr_lcdif;
+	};
+
+	lvgl_pointer {
+		compatible = "zephyr,lvgl-pointer-input";
+		input = <&ft5336_rtk7eka6m3b00001bu>;
+	};
+};
+
+&iic1 {
+	status = "okay";
+	ft5336_rtk7eka6m3b00001bu: ft5336-rtk7eka6m3b00001bu@38 {
+		compatible = "focaltech,ft5336";
+		reg = <0x38>;
+		int-gpios = <&renesas_parallel_graphics_connector 3 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&zephyr_lcdif {
+	status = "okay";
+	width = <480>;
+	height = <272>;
+	input-pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
+	output-pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
+	display-timings {
+		compatible = "zephyr,panel-timing";
+		hsync-len = <1>;
+		hback-porch = <40>;
+		vsync-len = <1>;
+		vback-porch = <8>;
+		hsync-active = <0>;
+		vsync-active = <0>;
+		de-active = <1>;
+		pixelclk-active = <0>;
+		hfront-porch = <4>;
+		vfront-porch = <35>;
+	};
+	backlight-gpios = <&renesas_parallel_graphics_connector 1 GPIO_ACTIVE_HIGH>;
+};
diff --git a/boards/shields/rtkmipilcdb00000be/boards/ek_ra8d1.conf b/boards/shields/rtkmipilcdb00000be/boards/ek_ra8d1.conf
new file mode 100644
index 00000000000..0ac7b7ace6a
--- /dev/null
+++ b/boards/shields/rtkmipilcdb00000be/boards/ek_ra8d1.conf
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_LV_Z_FLUSH_THREAD=n
+CONFIG_LV_Z_BITS_PER_PIXEL=16
+CONFIG_LV_COLOR_DEPTH_16=y
diff --git a/boards/shields/rtkmipilcdb00000be/boards/ek_ra8d1.overlay b/boards/shields/rtkmipilcdb00000be/boards/ek_ra8d1.overlay
index 30399bc741f..70e2a1817dd 100644
--- a/boards/shields/rtkmipilcdb00000be/boards/ek_ra8d1.overlay
+++ b/boards/shields/rtkmipilcdb00000be/boards/ek_ra8d1.overlay
@@ -9,7 +9,7 @@
 		group1 {
 			/* SCL1 SDA1 */
 			psels = <RA_PSEL(RA_PSEL_I2C, 5, 12)>,
-					<RA_PSEL(RA_PSEL_I2C, 5, 11)>;
+				<RA_PSEL(RA_PSEL_I2C, 5, 11)>;
 			drive-strength = "medium";
 		};
 	};
@@ -23,3 +23,27 @@
 	pinctrl-0 = <&iic1_default>;
 	pinctrl-names = "default";
 };
+
+&zephyr_lcdif {
+	input-pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
+};
+
+&mipi_dsi {
+	status = "okay";
+	pll-div = <1>;
+	pll-mul-int = <50>;
+	pll-mul-frac = "0.00";
+	lp-divisor = <5>;
+	ulps-wakeup-period = <97>;
+	video-mode-delay = <186>;
+	timing = <1183 11 26 40>;
+
+	phys-timing {
+		t-init = <71999>;
+		t-clk-prep = <8>;
+		t-hs-prep = <5>;
+		t-lp-exit = <7>;
+		dphytim4 = <27 1 19 7>;
+		dphytim5 = <19 8 11>;
+	};
+};
diff --git a/boards/shields/rtkmipilcdb00000be/doc/index.rst b/boards/shields/rtkmipilcdb00000be/doc/index.rst
index 4e77512e6d5..301a793382d 100644
--- a/boards/shields/rtkmipilcdb00000be/doc/index.rst
+++ b/boards/shields/rtkmipilcdb00000be/doc/index.rst
@@ -14,19 +14,19 @@ This display uses a 26 pin connector header.
 Pins Assignment of the Renesas RTKMIPILCDB00000BE MIPI Display
 ==============================================================
 
-+-----------------------+------------------------+
++----------------------+-------------------------+
 | Connector Pin        | Function                |
-+=======================+========================+
++======================+=========================+
 | 14                   | Touch ctrl I2C SDA      |
-+-----------------------+------------------------+
++----------------------+-------------------------+
 | 15                   | Display backlight enable|
-+-----------------------+------------------------+
++----------------------+-------------------------+
 | 16                   | Touch ctrl I2C SCL      |
-+-----------------------+------------------------+
++----------------------+-------------------------+
 | 17                   | External interrupt      |
-+-----------------------+------------------------+
++----------------------+-------------------------+
 | 18                   | Display reset           |
-+-----------------------+------------------------+
++----------------------+-------------------------+
 
 Hardware Requirements:
 **********************
@@ -35,19 +35,6 @@ Supported Renesas RA boards: EK-RA8D1
 - 1 x RA Board
 - 1 x Micro USB cable
 
-Hardware Configuration:
-***********************
-
-The MIPI Graphics Expansion Port (J58) connects the EK-RA8D1 board to the MIPI Graphics Expansion Board
-supplied as part of the kit.
-
-Set the configuration switches (SW1) as below to avoid potential failures.
-		+-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
-		| SW1-1 PMOD1 | SW1-2 TRACE | SW1-3 CAMERA | SW1-4 ETHA | SW1-5 ETHB | SW1-6 GLCD | SW1-7 SDRAM | SW1-8 I3C |
-		+-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
-		|     OFF     |     OFF     |      OFF     |     OFF    |     OFF    |     ON     |     ON      |    OFF    |
-		+-------------+-------------+--------------+------------+------------+------------+-------------+-----------+
-
 Programming
 ***********
 
diff --git a/boards/shields/ssd1306/ssd1306_128x64_spi.overlay b/boards/shields/ssd1306/ssd1306_128x64_spi.overlay
index 7aabf73b2ee..ad9301086f1 100644
--- a/boards/shields/ssd1306/ssd1306_128x64_spi.overlay
+++ b/boards/shields/ssd1306/ssd1306_128x64_spi.overlay
@@ -26,7 +26,7 @@
 		segment-remap;
 		com-invdir;
 		prechargep = <0x22>;
-		data_cmd-gpios = <&arduino_header 15 0>;
+		data-cmd-gpios = <&arduino_header 15 0>;
 		/* reset-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; */
 	};
 };
diff --git a/boards/shields/st_b_cams_omv_mb1683/Kconfig.shield b/boards/shields/st_b_cams_omv_mb1683/Kconfig.shield
new file mode 100644
index 00000000000..48bd6cd8249
--- /dev/null
+++ b/boards/shields/st_b_cams_omv_mb1683/Kconfig.shield
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Charles Dias <charlesdias.cd@outlook.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SHIELD_ST_B_CAMS_OMV_MB1683
+	def_bool $(shields_list_contains,st_b_cams_omv_mb1683)
diff --git a/boards/shields/st_b_cams_omv_mb1683/boards/stm32h7b3i_dk.overlay b/boards/shields/st_b_cams_omv_mb1683/boards/stm32h7b3i_dk.overlay
new file mode 100644
index 00000000000..c6e629d2342
--- /dev/null
+++ b/boards/shields/st_b_cams_omv_mb1683/boards/stm32h7b3i_dk.overlay
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2025 Charles Dias <charlesdias.cd@outlook.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+&st_cam_i2c {
+	pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pd13>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&st_cam_dvp {
+	pinctrl-0 = <&dcmi_hsync_pa4 &dcmi_pixclk_pa6 &dcmi_vsync_pb7
+		&dcmi_d0_pc6 &dcmi_d1_pc7 &dcmi_d2_pg10 &dcmi_d3_pc9
+		&dcmi_d4_pc11 &dcmi_d5_pd3 &dcmi_d6_pb8 &dcmi_d7_pb9>;
+	pinctrl-names = "default";
+
+	dmas = <&dma1 0 75 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_PERIPH_NO_INC |
+		STM32_DMA_MEM_INC | STM32_DMA_PERIPH_8BITS | STM32_DMA_MEM_32BITS |
+		STM32_DMA_PRIORITY_HIGH) STM32_DMA_FIFO_1_4>;
+};
+
+&dma1 {
+	status = "okay";
+};
+
+&dmamux1 {
+	status = "okay";
+};
diff --git a/boards/shields/st_b_cams_omv_mb1683/doc/index.rst b/boards/shields/st_b_cams_omv_mb1683/doc/index.rst
new file mode 100644
index 00000000000..754fbf2c9b7
--- /dev/null
+++ b/boards/shields/st_b_cams_omv_mb1683/doc/index.rst
@@ -0,0 +1,153 @@
+.. _st_b_cams_omv_mb1683:
+
+ST B-CAMS-OMV-MB1683
+####################
+
+Overview
+********
+
+The camera module bundle (B-CAMS-OMV) provides extension connectors
+for the MB1379 STMicroelectronics camera module daughterboard or
+third-party modules like OpenMV and Waveshare modules. It can be used
+with the STM32 boards featuring a 1 x 30 pin ZIF connector for the
+connection of multiple cameras to implement computer vision on STM32
+microcontrollers easily.
+
+The camera module bundle is compatible with all STM32 Discovery kits and
+Evaluation boards featuring a ZIF connector, such as the STM32H747I-DISCO,
+STM32H7B3I-DK, and 32L4R9IDISCOVERY Discovery kits.
+
+.. figure:: st_b_cams_omv.webp
+     :width: 600px
+     :align: center
+     :alt: B-CAMS-OMV-MB1683
+
+     B-CAMS-OMV MB1683 Image (Credit: STMicroelectronics.)
+
+The camera signals go into the shield from one of the supported input
+connectors (CN1, CN2, CN4), and out of the shield towards Zephyr through
+the output 30-pin ZIF connector CN5.
+
+Refer to the `User manual`_ for the pinout of CN1 and CN2.
+
+Waveshare camera board connector CN4 (camera input)
+***************************************************
+
++------------+-----------------+------------+--------------+
+| Pin number | Description     | Pin number | Description  |
++============+=================+============+==============+
+| 1          | GND             | 2          | VCAM         |
++------------+-----------------+------------+--------------+
+| 3          | I2C_SDA         | 4          | I2C_SCL      |
++------------+-----------------+------------+--------------+
+| 5          | DCMI_HSYNC      | 6          | DCMI_VSYNC   |
++------------+-----------------+------------+--------------+
+| 7          | Camera_CLK      | 8          | DCMI_PIXCLK  |
++------------+-----------------+------------+--------------+
+| 9          | DCMI_D6         | 10         | DCMI_D7      |
++------------+-----------------+------------+--------------+
+| 11         | DCMI_D4         | 12         | DCMI_D5      |
++------------+-----------------+------------+--------------+
+| 13         | DCMI_D2         | 14         | DCMI_D3      |
++------------+-----------------+------------+--------------+
+| 15         | DCMI_D0         | 16         | DCMI_D1      |
++------------+-----------------+------------+--------------+
+| 17         | PWR_EN / LED1   | 18         | RESET#       |
++------------+-----------------+------------+--------------+
+
+ZIF connector CN5 (camera output)
+*********************************
+
++------------+-----------------+
+| Pin number | Description     |
++============+=================+
+| 1          | 3V3             |
++------------+-----------------+
+| 2          | GND             |
++------------+-----------------+
+| 3          | I2C_SCL         |
++------------+-----------------+
+| 4          | I2C_SDA         |
++------------+-----------------+
+| 5          | RESET#          |
++------------+-----------------+
+| 6          | PWR_EN / LED1   |
++------------+-----------------+
+| 7          | SHUTTER         |
++------------+-----------------+
+| 8          | GND             |
++------------+-----------------+
+| 9          | PULLDOWN / LED2 |
++------------+-----------------+
+| 10         | Camera_CLK      |
++------------+-----------------+
+| 11         | 3V3             |
++------------+-----------------+
+| 12         | DCMI_VSYNC      |
++------------+-----------------+
+| 13         | 5V (RSU)        |
++------------+-----------------+
+| 14         | DCMI_HSYNC      |
++------------+-----------------+
+| 15         | GND             |
++------------+-----------------+
+| 16         | DCMI_PIXCK      |
++------------+-----------------+
+| 17         | GND             |
++------------+-----------------+
+| 18         | SPI_MISO        |
++------------+-----------------+
+| 19         | SPI_CS          |
++------------+-----------------+
+| 20         | DCMI_D7         |
++------------+-----------------+
+| 21         | DCMI_D6         |
++------------+-----------------+
+| 22         | DCMI_D5         |
++------------+-----------------+
+| 23         | DCMI_D4         |
++------------+-----------------+
+| 24         | DCMI_D3         |
++------------+-----------------+
+| 25         | DCMI_D2         |
++------------+-----------------+
+| 26         | DCMI_D1         |
++------------+-----------------+
+| 27         | DCMI_D0         |
++------------+-----------------+
+| 28         | SPI_MOSI        |
++------------+-----------------+
+| 29         | SPI_CLK         |
++------------+-----------------+
+| 30         | GND             |
++------------+-----------------+
+
+Requirements
+************
+
+The camera module bundle is compatible with all STM32 Discovery kits and
+Evaluation boards featuring a ZIF connector, such as the STM32H747I-DISCO,
+STM32H7B3I-DK, and 32L4R9IDISCOVERY Discovery kits.
+
+Usage
+*****
+
+The shield can be used in any application by setting ``SHIELD`` to
+``_st_b_cams_omv_mb1683`` and adding the necessary device tree properties.
+
+Set ``--shield "st_b_cams_omv_mb1683"`` when you invoke ``west build``. For example:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/drivers/video/capture_to_lvgl
+   :board: stm32h7b3i_dk
+   :shield: st_b_cams_omv_mb1683
+   :goals: build
+
+References
+**********
+
+- `Product page <https://www.st.com/en/evaluation-tools/b-cams-omv.html>`_
+
+- `Databrief <https://www.st.com/resource/en/data_brief/b-cams-omv.pdf>`_
+
+- `User manual <https://www.st.com/resource/en/user_manual/um2779-camera-module-bundle-for-stm32-boards-stmicroelectronics.pdf>`_
diff --git a/boards/shields/st_b_cams_omv_mb1683/doc/st_b_cams_omv.webp b/boards/shields/st_b_cams_omv_mb1683/doc/st_b_cams_omv.webp
new file mode 100644
index 00000000000..2060d43b2e4
Binary files /dev/null and b/boards/shields/st_b_cams_omv_mb1683/doc/st_b_cams_omv.webp differ
diff --git a/boards/shields/st_b_cams_omv_mb1683/st_b_cams_omv_mb1683.overlay b/boards/shields/st_b_cams_omv_mb1683/st_b_cams_omv_mb1683.overlay
new file mode 100644
index 00000000000..0ffb5669dad
--- /dev/null
+++ b/boards/shields/st_b_cams_omv_mb1683/st_b_cams_omv_mb1683.overlay
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2025 Charles Dias <charlesdias.cd@outlook.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#include <zephyr/dt-bindings/video/video-interfaces.h>
+
+/ {
+	chosen {
+		zephyr,camera = &st_cam_dvp;
+	};
+};
+
+&st_cam_i2c {
+
+	ov5640: ov5640@3c {
+		compatible = "ovti,ov5640";
+		reg = <0x3c>;
+		status = "okay";
+		reset-gpios = <&dmci_camera_connector 5 GPIO_ACTIVE_LOW>;
+		powerdown-gpios = <&dmci_camera_connector 6 GPIO_ACTIVE_HIGH>;
+
+		port {
+			ov5640_ep_out: endpoint {
+				remote-endpoint-label = "dcmi_ep_in";
+				bus-type = <VIDEO_BUS_TYPE_PARALLEL>;
+			};
+		};
+	};
+};
+
+&st_cam_dvp {
+	status = "okay";
+	sensor = <&ov5640>;
+
+	bus-width = <8>;
+	hsync-active = <0>;
+	vsync-active = <0>;
+	pixelclk-active = <1>;
+	capture-rate = <1>;
+
+	port {
+		dcmi_ep_in: endpoint {
+			remote-endpoint-label = "ov5640_ep_out";
+		};
+	};
+};
diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166/stm32h757i_eval_stm32h757xx_m7.conf b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166/stm32h757i_eval_stm32h757xx_m7.conf
new file mode 100644
index 00000000000..80af9d85fff
--- /dev/null
+++ b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/st_b_lcd40_dsi1_mb1166/stm32h757i_eval_stm32h757xx_m7.conf
@@ -0,0 +1,7 @@
+# Copyright (c) 2023 bytes at work AG
+# Copyright (c) 2024 Erik Andersson <erian747@gmail.com>
+# Copyright (c) 2025 Foss Analytical A/S
+# SPDX-License-Identifier: Apache-2.0
+
+# Initialize after LTDC and MIPI-DSI
+CONFIG_DISPLAY_OTM8009A_INIT_PRIORITY=87
diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h757i_eval_stm32h757xx_m7.conf b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h757i_eval_stm32h757xx_m7.conf
new file mode 100644
index 00000000000..8ff1f5b0838
--- /dev/null
+++ b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h757i_eval_stm32h757xx_m7.conf
@@ -0,0 +1,6 @@
+# Copyright (c) 2023 bytes at work AG
+# Copyright (c) 2025 Foss Analytical A/S
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MEMC=y
+CONFIG_STM32_LTDC_ARGB8888=y
diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h757i_eval_stm32h757xx_m7.defconfig b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h757i_eval_stm32h757xx_m7.defconfig
new file mode 100644
index 00000000000..a48bcaf437d
--- /dev/null
+++ b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h757i_eval_stm32h757xx_m7.defconfig
@@ -0,0 +1,24 @@
+# Copyright (c) 2024 Linumiz
+# Copyright (c) 2025 Foss Analytical A/S
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_STM32H757I_EVAL_STM32H757XX_M7
+
+if LVGL
+
+# Double frame buffer maintained by lvgl.
+config STM32_LTDC_FB_NUM
+	default 0
+
+config LV_Z_DOUBLE_VDB
+	default y
+
+config LV_Z_VDB_CUSTOM_SECTION
+	default y
+
+config LV_Z_FULL_REFRESH
+	default y
+
+endif # LVGL
+
+endif # BOARD_STM32H757I_EVAL_STM32H757XX_M7
diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h757i_eval_stm32h757xx_m7.overlay b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h757i_eval_stm32h757xx_m7.overlay
new file mode 100644
index 00000000000..167160594bb
--- /dev/null
+++ b/boards/shields/st_b_lcd40_dsi1_mb1166/boards/stm32h757i_eval_stm32h757xx_m7.overlay
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2023 bytes at work AG
+ * Copyright (c) 2025 Foss Analytical A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&sdram2 {
+	/* Frame buffer memory when cached causes screen flickering. */
+	zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
+};
+
+&zephyr_lcd_controller {
+	status = "okay";
+	ext-sdram = <&sdram2>;
+	def-back-color-red = <0>;
+	def-back-color-green = <0>;
+	def-back-color-blue = <0>;
+};
+
+/* ltdc uses pll3_r as pixel clock */
+&pll3 {
+	status = "okay";
+	clocks = <&clk_hse>;
+	div-m = <5>;
+	mul-n = <132>;
+	div-p = <2>;
+	div-q = <2>;
+	div-r = <24>; /* 27.5 MHz */
+};
+
+&zephyr_mipi_dsi {
+	status = "okay";
+
+	/* DSI HOST dedicated PLL
+	 * F_VCO = CLK_IN / pll-idf * 2 * pll-ndiv
+	 * PHI = F_VCO / 2 / (1 << pll-odf) = lane_byte_clk
+	 *     = 25 MHz / 5 * 2 * 100 / 2 / (1<<0) / 8 = 62.5 MHz
+	 */
+	pll-ndiv = <100>;
+	pll-idf = <5>;
+	pll-odf = <0>;
+
+	vs-active-high;
+	hs-active-high;
+	de-active-high;
+};
diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166.overlay b/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166.overlay
index 5e577214d27..608ad73a24e 100644
--- a/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166.overlay
+++ b/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166.overlay
@@ -59,7 +59,7 @@
 	ft5336: ft5336@38 {
 		compatible = "focaltech,ft5336";
 		reg = <0x38>;
-		int-gpios = <&dsi_lcd_qsh_030 4 0>;
+		int-gpios = <&dsi_lcd_qsh_030 4 GPIO_ACTIVE_LOW>;
 		status = "okay";
 	};
 };
diff --git a/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166_a09.overlay b/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166_a09.overlay
index ddef9b74e02..3e8a7aa38f9 100644
--- a/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166_a09.overlay
+++ b/boards/shields/st_b_lcd40_dsi1_mb1166/st_b_lcd40_dsi1_mb1166_a09.overlay
@@ -59,7 +59,7 @@
 	ft5336: ft5336@38 {
 		compatible = "focaltech,ft5336";
 		reg = <0x38>;
-		int-gpios = <&dsi_lcd_qsh_030 4 0>;
+		int-gpios = <&dsi_lcd_qsh_030 4 GPIO_ACTIVE_LOW>;
 		status = "okay";
 	};
 };
diff --git a/boards/shields/waveshare_pico_lcd_1_14/Kconfig.defconfig b/boards/shields/waveshare_pico_lcd_1_14/Kconfig.defconfig
new file mode 100644
index 00000000000..4d03c6d8a44
--- /dev/null
+++ b/boards/shields/waveshare_pico_lcd_1_14/Kconfig.defconfig
@@ -0,0 +1,31 @@
+# Copyright (c) 2025 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+if SHIELD_WAVESHARE_PICO_LCD_1_14 || SHIELD_WAVESHARE_PICO_LCD_1_14_DISPLAY
+
+if DISPLAY
+
+choice ST7789V_PIXEL_FORMAT
+	default ST7789V_RGB565
+endchoice
+
+if LVGL
+
+config LV_DPI_DEF
+	default 242
+
+config LV_Z_BITS_PER_PIXEL
+	default 16
+
+choice LV_COLOR_DEPTH
+	default LV_COLOR_DEPTH_16
+endchoice
+
+configdefault LV_COLOR_16_SWAP
+	default y
+
+endif # LVGL
+
+endif # DISPLAY
+
+endif # SHIELD_WAVESHARE_PICO_LCD_1_14
diff --git a/boards/shields/waveshare_pico_lcd_1_14/Kconfig.shield b/boards/shields/waveshare_pico_lcd_1_14/Kconfig.shield
new file mode 100644
index 00000000000..d4e81fed056
--- /dev/null
+++ b/boards/shields/waveshare_pico_lcd_1_14/Kconfig.shield
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+config SHIELD_WAVESHARE_PICO_LCD_1_14
+	def_bool $(shields_list_contains,waveshare_pico_lcd_1_14)
+
+config SHIELD_WAVESHARE_PICO_LCD_1_14_DISPLAY
+	def_bool $(shields_list_contains,waveshare_pico_lcd_1_14_display)
+
+config SHIELD_WAVESHARE_PICO_LCD_1_14_BUTTONS
+	def_bool $(shields_list_contains,waveshare_pico_lcd_1_14_buttons)
diff --git a/boards/shields/waveshare_pico_lcd_1_14/boards/pico_plus2_rp2350b_m33.overlay b/boards/shields/waveshare_pico_lcd_1_14/boards/pico_plus2_rp2350b_m33.overlay
new file mode 100644
index 00000000000..f97a5f748aa
--- /dev/null
+++ b/boards/shields/waveshare_pico_lcd_1_14/boards/pico_plus2_rp2350b_m33.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* pico_plus2 can use with the rpi_pico configuration. */
+#include "rpi_pico.overlay"
diff --git a/boards/shields/waveshare_pico_lcd_1_14/boards/rpi_pico.overlay b/boards/shields/waveshare_pico_lcd_1_14/boards/rpi_pico.overlay
new file mode 100644
index 00000000000..29574081340
--- /dev/null
+++ b/boards/shields/waveshare_pico_lcd_1_14/boards/rpi_pico.overlay
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	spi1_default: spi1_default {
+		group1 {
+			pinmux = <SPI1_CSN_P9>, <SPI1_SCK_P10>, <SPI1_TX_P11>;
+		};
+	};
+};
+
+&spi1 {
+	pinctrl-0 = < &spi1_default >;
+	pinctrl-names = "default";
+	cs-gpios = <&pico_header 9 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
diff --git a/boards/shields/waveshare_pico_lcd_1_14/boards/rpi_pico2_rp2350a_m33.overlay b/boards/shields/waveshare_pico_lcd_1_14/boards/rpi_pico2_rp2350a_m33.overlay
new file mode 100644
index 00000000000..34e8cc4082a
--- /dev/null
+++ b/boards/shields/waveshare_pico_lcd_1_14/boards/rpi_pico2_rp2350a_m33.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* rpi_pico2 can use with the rpi_pico configuration. */
+#include "rpi_pico.overlay"
diff --git a/boards/shields/waveshare_pico_lcd_1_14/boards/w5500_evb_pico.overlay b/boards/shields/waveshare_pico_lcd_1_14/boards/w5500_evb_pico.overlay
new file mode 100644
index 00000000000..f7430a242ac
--- /dev/null
+++ b/boards/shields/waveshare_pico_lcd_1_14/boards/w5500_evb_pico.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* w5500_evb_pico2 can use with the rpi_pico configuration. */
+#include "rpi_pico.overlay"
diff --git a/boards/shields/waveshare_pico_lcd_1_14/boards/w5500_evb_pico2_rp2350a_m33.overlay b/boards/shields/waveshare_pico_lcd_1_14/boards/w5500_evb_pico2_rp2350a_m33.overlay
new file mode 100644
index 00000000000..f7430a242ac
--- /dev/null
+++ b/boards/shields/waveshare_pico_lcd_1_14/boards/w5500_evb_pico2_rp2350a_m33.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* w5500_evb_pico2 can use with the rpi_pico configuration. */
+#include "rpi_pico.overlay"
diff --git a/boards/shields/waveshare_pico_lcd_1_14/doc/index.rst b/boards/shields/waveshare_pico_lcd_1_14/doc/index.rst
new file mode 100644
index 00000000000..6af8fbde237
--- /dev/null
+++ b/boards/shields/waveshare_pico_lcd_1_14/doc/index.rst
@@ -0,0 +1,66 @@
+.. _waveshare_pico_lcd_1_14:
+
+Waveshare 1.14inch LCD Display Module for Raspberry Pi Pico
+###########################################################
+
+Overview
+********
+
+The Waveshare 1.14inch LCD Display Module for Raspberry Pi Pico is
+a 240x135/65K color IPS LCD module based on the ST7789V controller.
+This module connects via SPI.
+This display module has two buttons and joystick that the user program can use.
+It is convenient for implementing user interfaces.
+
+More information about the shield and Arduino adapter can be found at
+the `Waveshare Pico-LCD-1.14 Module website`_.
+
+Pin Assignments
+===============
+
++-------+-----------+-------------------------------------------+
+| Name  | Function  | Usage                                     |
++=======+===========+===========================================+
+| GP2   | UP        | Joystick Up                               |
++-------+-----------+-------------------------------------------+
+| GP3   | CTRL      | Joystick Center                           |
++-------+-----------+-------------------------------------------+
+| GP8   | LCD_DC    | Data/Command control pin                  |
++-------+-----------+-------------------------------------------+
+| GP9   | LCD_CS    | SPI Chip Select   (SPI1_CSN)              |
++-------+-----------+-------------------------------------------+
+| GP10  | LCD_CLK   | SPI Clock input   (SPI1_SCK)              |
++-------+-----------+-------------------------------------------+
+| GP11  | LCD_DIN   | SPI Data input    (SPI1_TX)               |
++-------+-----------+-------------------------------------------+
+| GP12  | LCD_RST   | Reset                                     |
++-------+-----------+-------------------------------------------+
+| GP13  | LCD_BL    | Backlight                                 |
++-------+-----------+-------------------------------------------+
+| GP15  | GPIO      | User Key A                                |
++-------+-----------+-------------------------------------------+
+| GP17  | GPIO      | User Key 1                                |
++-------+-----------+-------------------------------------------+
+| GP18  | DOWN      | Joystick Down                             |
++-------+-----------+-------------------------------------------+
+| GP20  | RIGHT     | Joystick Right                            |
++-------+-----------+-------------------------------------------+
+
+Programming
+***********
+
+Set ``-DSHIELD=waveshare_pico_lcd_1_14`` when you invoke ``west build``. For example:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/subsys/display/lvgl
+   :board: rpi_pico
+   :shield: waveshare_pico_oled_1_14
+   :goals: build
+
+References
+**********
+
+.. target-notes::
+
+.. _Waveshare Pico-LCD-1.14 Module website:
+   https://www.waveshare.com/wiki/Pico-LCD-1.14
diff --git a/boards/shields/waveshare_pico_lcd_1_14/waveshare_pico_lcd_1_14.overlay b/boards/shields/waveshare_pico_lcd_1_14/waveshare_pico_lcd_1_14.overlay
new file mode 100644
index 00000000000..3b809ab510e
--- /dev/null
+++ b/boards/shields/waveshare_pico_lcd_1_14/waveshare_pico_lcd_1_14.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "waveshare_pico_lcd_1_14_display.overlay"
+#include "waveshare_pico_lcd_1_14_buttons.overlay"
diff --git a/boards/shields/waveshare_pico_lcd_1_14/waveshare_pico_lcd_1_14_buttons.overlay b/boards/shields/waveshare_pico_lcd_1_14/waveshare_pico_lcd_1_14_buttons.overlay
new file mode 100644
index 00000000000..8fd18afad8d
--- /dev/null
+++ b/boards/shields/waveshare_pico_lcd_1_14/waveshare_pico_lcd_1_14_buttons.overlay
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/lvgl/lvgl.h>
+
+/ {
+	waveshare_pico_lcd_1_14_buttons: waveshare-pico_lcd_1_14-buttons {
+		compatible = "gpio-keys";
+
+		key_a: key_a {
+			label = "User key A";
+			gpios = <&pico_header 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			zephyr,code = <INPUT_KEY_A>;
+		};
+
+		key_b: key_b {
+			label = "User key B";
+			gpios = <&pico_header 17 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			zephyr,code = <INPUT_KEY_B>;
+		};
+	};
+
+	waveshare_pico_lcd_1_14_joystick: waveshare-pico_lcd_1_14-joystick {
+		compatible = "gpio-keys";
+
+		joystick_enter: joystick_enter {
+			label = "User joystick ENTER";
+			gpios = <&pico_header 3 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			zephyr,code = <INPUT_KEY_ENTER>;
+		};
+
+		joystick_right: joystick_right {
+			label = "User joystick RIGHT";
+			gpios = <&pico_header 20 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			zephyr,code = <INPUT_KEY_RIGHT>;
+		};
+
+		joystick_up: joystick_up {
+			label = "User joystick UP";
+			gpios = <&pico_header  2 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			zephyr,code = <INPUT_KEY_UP>;
+		};
+
+		joystick_down: joystick_down {
+			label = "User joystick DOWN";
+			gpios = <&pico_header  18 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			zephyr,code = <INPUT_KEY_DOWN>;
+		};
+
+		joystick_left: joystick_left {
+			label = "User joystick LEFT";
+			gpios = <&pico_header 16 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			zephyr,code = <INPUT_KEY_LEFT>;
+		};
+	};
+
+	aliases {
+		sw0 = &key_a;
+		sw1 = &key_b;
+	};
+};
diff --git a/boards/shields/waveshare_pico_lcd_1_14/waveshare_pico_lcd_1_14_display.overlay b/boards/shields/waveshare_pico_lcd_1_14/waveshare_pico_lcd_1_14_display.overlay
new file mode 100644
index 00000000000..eb027f772bb
--- /dev/null
+++ b/boards/shields/waveshare_pico_lcd_1_14/waveshare_pico_lcd_1_14_display.overlay
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
+
+/ {
+	chosen {
+		zephyr,display = &st7789v_waveshare_pico_lcd_1_14;
+	};
+
+	mipi_dbi_waveshare_pico_lcd_1_14 {
+		compatible = "zephyr,mipi-dbi-spi";
+		spi-dev = <&spi1>;
+		dc-gpios = <&pico_header 8 GPIO_ACTIVE_HIGH>;
+		reset-gpios = <&pico_header 12 GPIO_ACTIVE_LOW>;
+		write-only;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+
+		st7789v_waveshare_pico_lcd_1_14: st7789v@0 {
+			compatible = "sitronix,st7789v";
+			reg = <0>;
+			mipi-max-frequency = <20000000>;
+
+			width = <240>;
+			height = <135>;
+			x-offset = <40>;
+			y-offset = <53>;
+
+			vcom = <0x19>;
+			gctrl = <0x35>;
+			vrhs = <0x12>;
+			vdvs = <0x20>;
+			mdac = <0x77>;
+			gamma = <0x00>;
+			colmod = <0x05>;
+			lcm = <0x2c>;
+			porch-param = [0c 0c 00 33 33];
+			cmd2en-param = [5a 69 02 00];
+			pwctrl1-param = [a4 a1];
+			pvgam-param = [d0 04 0d 11 13 2b 3f 54 4c 18 0d 0b 1f 23];
+			nvgam-param = [d0 04 0c 11 13 2c 3f 44 51 2f 1f 1f 20 23];
+			ram-param = [00 F0];
+			rgb-param = [40 02 14];
+			mipi-mode = "MIPI_DBI_MODE_SPI_4WIRE";
+			status = "okay";
+		};
+	};
+
+	lcd_backlight_en {
+		compatible = "regulator-fixed";
+		regulator-name = "lcd_backlight_enable";
+		enable-gpios = <&pico_header 13 GPIO_ACTIVE_HIGH>;
+		regulator-boot-on;
+	};
+};
diff --git a/boards/shields/waveshare_pico_oled_1_3/Kconfig.defconfig b/boards/shields/waveshare_pico_oled_1_3/Kconfig.defconfig
new file mode 100644
index 00000000000..81883a4658f
--- /dev/null
+++ b/boards/shields/waveshare_pico_oled_1_3/Kconfig.defconfig
@@ -0,0 +1,24 @@
+# Copyright (c) 2025 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+if SHIELD_WAVESHARE_PICO_OLED_1_3
+
+if DISPLAY
+
+if LVGL
+
+config LV_DPI_DEF
+	default 110
+
+config LV_Z_BITS_PER_PIXEL
+	default 1
+
+choice LV_COLOR_DEPTH
+	default LV_COLOR_DEPTH_1
+endchoice
+
+endif # LVGL
+
+endif # DISPLAY
+
+endif # SHIELD_WAVESHARE_PICO_OLED_1_3
diff --git a/boards/shields/waveshare_pico_oled_1_3/Kconfig.shield b/boards/shields/waveshare_pico_oled_1_3/Kconfig.shield
new file mode 100644
index 00000000000..205293098eb
--- /dev/null
+++ b/boards/shields/waveshare_pico_oled_1_3/Kconfig.shield
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+config SHIELD_WAVESHARE_PICO_OLED_1_3
+	def_bool $(shields_list_contains,waveshare_pico_oled_1_3)
+
+config SHIELD_WAVESHARE_PICO_OLED_1_3_DISPLAY
+	def_bool $(shields_list_contains,waveshare_pico_oled_1_3_display)
+
+config SHIELD_WAVESHARE_PICO_OLED_1_3_BUTTONS
+	def_bool $(shields_list_contains,waveshare_pico_oled_1_3_buttons)
diff --git a/boards/shields/waveshare_pico_oled_1_3/boards/pico_plus2_rp2350b_m33.overlay b/boards/shields/waveshare_pico_oled_1_3/boards/pico_plus2_rp2350b_m33.overlay
new file mode 100644
index 00000000000..f97a5f748aa
--- /dev/null
+++ b/boards/shields/waveshare_pico_oled_1_3/boards/pico_plus2_rp2350b_m33.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* pico_plus2 can use with the rpi_pico configuration. */
+#include "rpi_pico.overlay"
diff --git a/boards/shields/waveshare_pico_oled_1_3/boards/rpi_pico.overlay b/boards/shields/waveshare_pico_oled_1_3/boards/rpi_pico.overlay
new file mode 100644
index 00000000000..154456fbaaa
--- /dev/null
+++ b/boards/shields/waveshare_pico_oled_1_3/boards/rpi_pico.overlay
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	i2c1_default: i2c1_default {
+		waveshare_pico_oled_1_3_group1 {
+			pinmux = <I2C1_SDA_P6>, <I2C1_SCL_P7>;
+			input-enable;
+			input-schmitt-enable;
+		};
+	};
+};
+
+&i2c1 {
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c1_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/boards/shields/waveshare_pico_oled_1_3/boards/rpi_pico2_rp2350a_m33.overlay b/boards/shields/waveshare_pico_oled_1_3/boards/rpi_pico2_rp2350a_m33.overlay
new file mode 100644
index 00000000000..34e8cc4082a
--- /dev/null
+++ b/boards/shields/waveshare_pico_oled_1_3/boards/rpi_pico2_rp2350a_m33.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* rpi_pico2 can use with the rpi_pico configuration. */
+#include "rpi_pico.overlay"
diff --git a/boards/shields/waveshare_pico_oled_1_3/boards/w5500_evb_pico.overlay b/boards/shields/waveshare_pico_oled_1_3/boards/w5500_evb_pico.overlay
new file mode 100644
index 00000000000..f7430a242ac
--- /dev/null
+++ b/boards/shields/waveshare_pico_oled_1_3/boards/w5500_evb_pico.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* w5500_evb_pico2 can use with the rpi_pico configuration. */
+#include "rpi_pico.overlay"
diff --git a/boards/shields/waveshare_pico_oled_1_3/boards/w5500_evb_pico2_rp2350a_m33.overlay b/boards/shields/waveshare_pico_oled_1_3/boards/w5500_evb_pico2_rp2350a_m33.overlay
new file mode 100644
index 00000000000..f7430a242ac
--- /dev/null
+++ b/boards/shields/waveshare_pico_oled_1_3/boards/w5500_evb_pico2_rp2350a_m33.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* w5500_evb_pico2 can use with the rpi_pico configuration. */
+#include "rpi_pico.overlay"
diff --git a/boards/shields/waveshare_pico_oled_1_3/doc/index.rst b/boards/shields/waveshare_pico_oled_1_3/doc/index.rst
new file mode 100644
index 00000000000..48f101e4fb8
--- /dev/null
+++ b/boards/shields/waveshare_pico_oled_1_3/doc/index.rst
@@ -0,0 +1,65 @@
+.. _waveshare_pico_oled_1_3:
+
+Waveshare 1.3inch OLED Display Module for Raspberry Pi Pico
+###########################################################
+
+Overview
+********
+
+The Waveshare 1.3inch OLED Display Module for Raspberry Pi Pico is
+a 64x128 vertically long LCD module based on the SinoWealth SH1107 controller.
+This module connects via I2C and optionally can use SPI(need soldering).
+This display module has two buttons that the user program can use.
+It is convenient for implementing user interfaces.
+
+More information about the shield and Arduino adapter can be found at
+the `Waveshare Pico OLED 1.3 Module website`_.
+
+Pin Assignments
+===============
+
++-------+-----------+-------------------------------------------+
+| Name  | Function  | Usage                                     |
++=======+===========+===========================================+
+| GP6   | I2C_SDA   | I2C Data input    (I2C1_SDA)              |
++-------+-----------+-------------------------------------------+
+| GP7   | I2C_SCL   | I2C Clock input   (I2C1_SCL)              |
++-------+-----------+-------------------------------------------+
+| GP8   | OLED_DC   | Data/Command control pin (optional)       |
++-------+-----------+-------------------------------------------+
+| GP9   | OLED_CS   | SPI Chip Select   (SPI1_CSN, optional)    |
++-------+-----------+-------------------------------------------+
+| GP10  | OLED_CLK  | SPI Clock input   (SPI1_SCK, optional)    |
++-------+-----------+-------------------------------------------+
+| GP11  | OLED_DIN  | SPI Data input    (SPI1_TX, optional)     |
++-------+-----------+-------------------------------------------+
+| GP12  | OLED_RST  | Reset                                     |
++-------+-----------+-------------------------------------------+
+| GP15  | GPIO      | User Key 0                                |
++-------+-----------+-------------------------------------------+
+| GP17  | GPIO      | User Key 1                                |
++-------+-----------+-------------------------------------------+
+
+.. note::
+   The SPI interface is not available by default.
+   Switch the J1, J2, and J3 jumper by moving 0-ohm registers
+   to the SPI side to enable SPI.
+
+Programming
+***********
+
+Set ``-DSHIELD=waveshare_pico_oled_1_3`` when you invoke ``west build``. For example:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/subsys/display/lvgl
+   :board: rpi_pico
+   :shield: waveshare_pico_oled_1_3
+   :goals: build
+
+References
+**********
+
+.. target-notes::
+
+.. _Waveshare Pico OLED 1.3 Module website:
+   https://www.waveshare.com/wiki/Pico-OLED-1.3
diff --git a/boards/shields/waveshare_pico_oled_1_3/waveshare_pico_oled_1_3.overlay b/boards/shields/waveshare_pico_oled_1_3/waveshare_pico_oled_1_3.overlay
new file mode 100644
index 00000000000..dd449e18bd3
--- /dev/null
+++ b/boards/shields/waveshare_pico_oled_1_3/waveshare_pico_oled_1_3.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "waveshare_pico_oled_1_3_display.overlay"
+#include "waveshare_pico_oled_1_3_buttons.overlay"
diff --git a/boards/shields/waveshare_pico_oled_1_3/waveshare_pico_oled_1_3_buttons.overlay b/boards/shields/waveshare_pico_oled_1_3/waveshare_pico_oled_1_3_buttons.overlay
new file mode 100644
index 00000000000..96d3b76735a
--- /dev/null
+++ b/boards/shields/waveshare_pico_oled_1_3/waveshare_pico_oled_1_3_buttons.overlay
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/lvgl/lvgl.h>
+
+/ {
+	buttons {
+		compatible = "gpio-keys";
+
+		key0: key0 {
+			label = "User Key 0";
+			gpios = <&pico_header 15 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		key1: key1 {
+			label = "User Key 1";
+			gpios = <&pico_header 17 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+
+	aliases {
+		sw0 = &key0;
+	};
+};
diff --git a/boards/shields/waveshare_pico_oled_1_3/waveshare_pico_oled_1_3_display.overlay b/boards/shields/waveshare_pico_oled_1_3/waveshare_pico_oled_1_3_display.overlay
new file mode 100644
index 00000000000..78da3f6c179
--- /dev/null
+++ b/boards/shields/waveshare_pico_oled_1_3/waveshare_pico_oled_1_3_display.overlay
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	chosen {
+		zephyr,display = &sh1107_waveshare_pico_oled_1_3;
+	};
+};
+
+&i2c1 {
+	sh1107_waveshare_pico_oled_1_3: sh1107@3c {
+		compatible = "sinowealth,sh1106";
+		reg = <0x3c>;
+
+		width = <64>;
+		height = <128>;
+		segment-offset = <0>;
+		page-offset = <0>;
+		display-offset = <0x20>;
+		multiplex-ratio = <63>;
+		prechargep = <0x22>;
+		segment-remap;
+		com-invdir;
+		reset-gpios = <&pico_header 12 GPIO_ACTIVE_LOW>;
+
+		status = "okay";
+	};
+};
diff --git a/boards/shields/x_nucleo_iks01a3/x_nucleo_iks01a3.overlay b/boards/shields/x_nucleo_iks01a3/x_nucleo_iks01a3.overlay
index 5db40cb3267..abc28041acc 100644
--- a/boards/shields/x_nucleo_iks01a3/x_nucleo_iks01a3.overlay
+++ b/boards/shields/x_nucleo_iks01a3/x_nucleo_iks01a3.overlay
@@ -4,6 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
 / {
 	aliases {
 		magn0 = &lis2mdl_1e_x_nucleo_iks01a3;
diff --git a/boards/sifive/hifive1/doc/index.rst b/boards/sifive/hifive1/doc/index.rst
index dcd9a2948ef..96336cd9910 100644
--- a/boards/sifive/hifive1/doc/index.rst
+++ b/boards/sifive/hifive1/doc/index.rst
@@ -23,6 +23,8 @@ and `HiFive1 Rev B <https://www.sifive.com/boards/hifive1-rev-b>`__.
 Programming and debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Building
 ========
 
diff --git a/boards/sifive/hifive_unleashed/doc/index.rst b/boards/sifive/hifive_unleashed/doc/index.rst
index e6450ac1f6c..8336d7da279 100644
--- a/boards/sifive/hifive_unleashed/doc/index.rst
+++ b/boards/sifive/hifive_unleashed/doc/index.rst
@@ -9,6 +9,8 @@ multi-core 64bit RISC-V SoC.
 Programming and debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Building
 ========
 
diff --git a/boards/sifive/hifive_unmatched/doc/index.rst b/boards/sifive/hifive_unmatched/doc/index.rst
index bc2447104b2..4a151a8c8ed 100644
--- a/boards/sifive/hifive_unmatched/doc/index.rst
+++ b/boards/sifive/hifive_unmatched/doc/index.rst
@@ -9,6 +9,8 @@ multi-core 64bit RISC-V SoC.
 Programming and debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Building
 ========
 
diff --git a/boards/silabs/dev_kits/sim3u1xx_dk/doc/index.rst b/boards/silabs/dev_kits/sim3u1xx_dk/doc/index.rst
index da8bb3cac5e..8cc622d66b2 100644
--- a/boards/silabs/dev_kits/sim3u1xx_dk/doc/index.rst
+++ b/boards/silabs/dev_kits/sim3u1xx_dk/doc/index.rst
@@ -40,26 +40,7 @@ For more information about the SiM3U167 SoC and the SiM3U1xx board, refer to the
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| AES       | on-chip    | crypto                              |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | dma                                 |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -91,6 +72,8 @@ Connections and IOs
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.yaml b/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.yaml
index 13a20e8a736..0617a1a05fa 100644
--- a/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.yaml
+++ b/boards/silabs/dev_kits/sim3u1xx_dk/sim3u1xx_dk.yaml
@@ -10,7 +10,6 @@ ram: 32
 flash: 256
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 supported:
   - crypto
diff --git a/boards/silabs/dev_kits/sltb004a/doc/index.rst b/boards/silabs/dev_kits/sltb004a/doc/index.rst
index 14795756afc..b53f3b6fe9c 100644
--- a/boards/silabs/dev_kits/sltb004a/doc/index.rst
+++ b/boards/silabs/dev_kits/sltb004a/doc/index.rst
@@ -43,39 +43,7 @@ For more information about the EFR32MG12 SoC and Thunderboard Sense 2 board:
 Supported Features
 ==================
 
-The sltb004a board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtcc                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c port-polling                    |
-+-----------+------------+-------------------------------------+
-| SPI(M)    | on-chip    | spi port-polling                    |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | true random number generator        |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/silabs/dev_kits/sltb004a/sltb004a_defconfig`
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -140,6 +108,8 @@ purpose application serial data transfer with this interface.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 .. note::
    Before using the kit the first time, you should update the J-Link firmware
    in Simplicity Studio.
diff --git a/boards/silabs/dev_kits/sltb004a/sltb004a.dts b/boards/silabs/dev_kits/sltb004a/sltb004a.dts
index 5252b0b6a48..10ecd3c946f 100644
--- a/boards/silabs/dev_kits/sltb004a/sltb004a.dts
+++ b/boards/silabs/dev_kits/sltb004a/sltb004a.dts
@@ -81,7 +81,7 @@
 };
 
 &usart2 {
-	compatible = "silabs,gecko-spi-usart";
+	compatible = "silabs,usart-spi";
 
 	#address-cells = <1>;
 	#size-cells = <0>;
diff --git a/boards/silabs/dev_kits/sltb004a/sltb004a.yaml b/boards/silabs/dev_kits/sltb004a/sltb004a.yaml
index c1e842247f6..5eb52c7e024 100644
--- a/boards/silabs/dev_kits/sltb004a/sltb004a.yaml
+++ b/boards/silabs/dev_kits/sltb004a/sltb004a.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/silabs/dev_kits/sltb009a/doc/index.rst b/boards/silabs/dev_kits/sltb009a/doc/index.rst
index 8be84aefc60..285bd1b6bc2 100644
--- a/boards/silabs/dev_kits/sltb009a/doc/index.rst
+++ b/boards/silabs/dev_kits/sltb009a/doc/index.rst
@@ -26,30 +26,7 @@ For more information about the WGM160P and SLTB009A board:
 Supported Features
 ==================
 
-The efm32gg_sltb009a board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtcc                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c port-polling                    |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/silabs/dev_kits/sltb009a/sltb009a_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -99,6 +76,8 @@ USART0 is connected to the board controller and is used for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 .. note::
    Before using the kit the first time, you should update the J-Link firmware
    in Simplicity Studio.
diff --git a/boards/silabs/dev_kits/sltb010a/Kconfig.defconfig b/boards/silabs/dev_kits/sltb010a/Kconfig.defconfig
index fac4f17b12e..b9edc20d7cf 100644
--- a/boards/silabs/dev_kits/sltb010a/Kconfig.defconfig
+++ b/boards/silabs/dev_kits/sltb010a/Kconfig.defconfig
@@ -1,6 +1,11 @@
 # Copyright (c) 2023 Antmicro <www.antmicro.com>
 # SPDX-License-Identifier: Apache-2.0
 
+if BOARD_SLTB010A
+
+configdefault LOG_BACKEND_SWO_FREQ_HZ
+	default 875000
+
 if SOC_GECKO_USE_RAIL
 
 config FPU
@@ -24,3 +29,5 @@ endif # BT
 
 config REGULATOR
 	default y if SI7210
+
+endif
diff --git a/boards/silabs/dev_kits/sltb010a/doc/index.rst b/boards/silabs/dev_kits/sltb010a/doc/index.rst
index eb7dcfb24a0..a9fcdd71643 100644
--- a/boards/silabs/dev_kits/sltb010a/doc/index.rst
+++ b/boards/silabs/dev_kits/sltb010a/doc/index.rst
@@ -42,40 +42,7 @@ For more information about the EFR32BG SoC and Thunderboard EFR32BG22 board:
 Supported Features
 ==================
 
-The sltb010a board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | stimer                              |
-+-----------+------------+-------------------------------------+
-| SPI(M/S)  | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | ldma                                |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | true random number generator        |
-+-----------+------------+-------------------------------------+
-| I2C(M/S)  | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| RADIO     | on-chip    | bluetooth                           |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/silabs/dev_kits/sltb010a/sltb010a_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -122,6 +89,8 @@ board.
 Programming and Debugging
 =========================
 
+.. zephyr:board-supported-runners::
+
 Flashing an application
 -----------------------
 
diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a-pinctrl.dtsi b/boards/silabs/dev_kits/sltb010a/sltb010a-pinctrl.dtsi
index 435ca5a0cf4..756653bdcf5 100644
--- a/boards/silabs/dev_kits/sltb010a/sltb010a-pinctrl.dtsi
+++ b/boards/silabs/dev_kits/sltb010a/sltb010a-pinctrl.dtsi
@@ -39,4 +39,12 @@
 			bias-pull-up;
 		};
 	};
+
+	itm_default: itm_default {
+		group0 {
+			pins = <GPIO_SWV_PA3>;
+			drive-push-pull;
+			output-high;
+		};
+	};
 };
diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a.dts b/boards/silabs/dev_kits/sltb010a/sltb010a.dts
index 994a75007ee..520d9837d74 100644
--- a/boards/silabs/dev_kits/sltb010a/sltb010a.dts
+++ b/boards/silabs/dev_kits/sltb010a/sltb010a.dts
@@ -105,6 +105,10 @@
 	enable-gpios = <&gpiob 4 GPIO_ACTIVE_HIGH>;
 };
 
+&radio {
+	pa-voltage-mv = <1800>;
+};
+
 &bt_hci_silabs {
 	status = "okay";
 };
diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a_0.yaml b/boards/silabs/dev_kits/sltb010a/sltb010a_0.yaml
index 90a2ebc846a..fd679198dc9 100644
--- a/boards/silabs/dev_kits/sltb010a/sltb010a_0.yaml
+++ b/boards/silabs/dev_kits/sltb010a/sltb010a_0.yaml
@@ -7,7 +7,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - bluetooth
   - counter
diff --git a/boards/silabs/dev_kits/sltb010a/sltb010a_2.yaml b/boards/silabs/dev_kits/sltb010a/sltb010a_2.yaml
index b0642de163e..fbd9f8c9724 100644
--- a/boards/silabs/dev_kits/sltb010a/sltb010a_2.yaml
+++ b/boards/silabs/dev_kits/sltb010a/sltb010a_2.yaml
@@ -7,7 +7,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - bluetooth
   - counter
diff --git a/boards/silabs/dev_kits/sltb010a/thunderboard.dtsi b/boards/silabs/dev_kits/sltb010a/thunderboard.dtsi
index 0ec7c11aa15..771a45e1e93 100644
--- a/boards/silabs/dev_kits/sltb010a/thunderboard.dtsi
+++ b/boards/silabs/dev_kits/sltb010a/thunderboard.dtsi
@@ -68,6 +68,12 @@
 	clock-frequency = <76800000>;
 };
 
+&itm {
+	pinctrl-0 = <&itm_default>;
+	pinctrl-names = "default";
+	swo-ref-frequency = <DT_FREQ_K(76800)>;
+};
+
 &pstate_em3 {
 	status = "disabled";
 };
diff --git a/boards/silabs/dev_kits/xg24_dk2601b/Kconfig.defconfig b/boards/silabs/dev_kits/xg24_dk2601b/Kconfig.defconfig
index 13cb5b0c77c..325d26f1f4a 100644
--- a/boards/silabs/dev_kits/xg24_dk2601b/Kconfig.defconfig
+++ b/boards/silabs/dev_kits/xg24_dk2601b/Kconfig.defconfig
@@ -3,6 +3,9 @@
 
 if BOARD_XG24_DK2601B
 
+configdefault LOG_BACKEND_SWO_FREQ_HZ
+	default 875000
+
 if SOC_GECKO_USE_RAIL
 
 config FPU
diff --git a/boards/silabs/dev_kits/xg24_dk2601b/doc/index.rst b/boards/silabs/dev_kits/xg24_dk2601b/doc/index.rst
index c2453e977c0..8df7d25dc8f 100644
--- a/boards/silabs/dev_kits/xg24_dk2601b/doc/index.rst
+++ b/boards/silabs/dev_kits/xg24_dk2601b/doc/index.rst
@@ -17,7 +17,7 @@ Hardware
 - Transmit power: up to +20 dBm
 - Operation frequency: 2.4 GHz
 - Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz).
-- On board sensors:
+- On board devices:
 
   - Silicon Labs Si7021 relative humidity & temperature sensor
   - Silicon Labs Si7210 hall effect sensor
@@ -25,6 +25,7 @@ Hardware
   - TDK InvenSense ICM-20689 6-axis inertial measurement sensor
   - Vishay VEML6035 ambient light sensor
   - Bosch BMP384 pressure sensor with internal temperature sensor
+  - MX25R3235F 32 Mbit SPI data flash
 
 For more information about the EFR32MG24 SoC and BRD2601B board, refer to these
 documents:
@@ -37,59 +38,43 @@ documents:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | stimer                              |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | ldma                                |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | semailbox                           |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| I2C(M/S)  | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| RADIO     | on-chip    | bluetooth                           |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
 
 In the following table, the column **Name** contains Pin names. For example, PA2
-means Pin number 2 on PORTA, as used in the board's datasheets and manuals.
-
-+-------+-------------+-------------------------------------+
-| Name  | Function    | Usage                               |
-+=======+=============+=====================================+
-| PA4   | GPIO        | LED0                                |
-+-------+-------------+-------------------------------------+
-| PB0   | GPIO        | LED1                                |
-+-------+-------------+-------------------------------------+
-| PB2   | GPIO        | Push Button 0                       |
-+-------+-------------+-------------------------------------+
-| PB3   | GPIO        | Push Button 1                       |
-+-------+-------------+-------------------------------------+
-| PA5   | USART0_TX   | UART Console VCOM_TX US0_TX         |
-+-------+-------------+-------------------------------------+
-| PA6   | USART0_RX   | UART Console VCOM_RX US0_RX         |
-+-------+-------------+-------------------------------------+
+means Pin number 2 on Port A, as used in the board's datasheets and manuals.
+
++------+--------------+---------------------+
+| Name | Function     | Usage               |
++======+==============+=====================+
+| PA4  | GPIO         | LED0                |
++------+--------------+---------------------+
+| PB0  | GPIO         | LED1                |
++------+--------------+---------------------+
+| PD2  | GPIO         | LED2                |
++------+--------------+---------------------+
+| PB2  | GPIO         | Push Button 0       |
++------+--------------+---------------------+
+| PB3  | GPIO         | Push Button 1       |
++------+--------------+---------------------+
+| PA5  | USART0_TX    | UART Console        |
++------+--------------+---------------------+
+| PA6  | USART0_RX    | UART Console        |
++------+--------------+---------------------+
+| PC3  | EUSART1_TX   | SPI bus: flash, IMU |
++------+--------------+---------------------+
+| PC2  | EUSART1_RX   | SPI bus: flash, IMU |
++------+--------------+---------------------+
+| PC1  | EUSART1_SCLK | SPI bus: flash, IMU |
++------+--------------+---------------------+
+| PC0  | EUSART1_CS   | SPI bus: flash      |
++------+--------------+---------------------+
+| PC4  | I2C0_SCL     | I2C bus             |
++------+--------------+---------------------+
+| PC5  | I2C0_SDA     | I2C bus             |
++------+--------------+---------------------+
 
 The default configuration can be found in
 :zephyr_file:`boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b_defconfig`
@@ -109,6 +94,8 @@ USART0 is connected to the board controller and is used for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 .. note::
    Before using the kit the first time, you should update the J-Link firmware
    in Simplicity Studio.
diff --git a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b-pinctrl.dtsi b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b-pinctrl.dtsi
index 30aaa4655ba..a991860ea0f 100644
--- a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b-pinctrl.dtsi
+++ b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b-pinctrl.dtsi
@@ -20,6 +20,19 @@
 		};
 	};
 
+	eusart1_default: eusart1_default {
+		group0 {
+			pins = <EUSART1_TX_PC3>, <EUSART1_SCLK_PC1>;
+			drive-push-pull;
+			output-high;
+		};
+		group1 {
+			pins = <EUSART1_RX_PC2>;
+			input-enable;
+			silabs,input-filter;
+		};
+	};
+
 	i2c0_default: i2c0_default {
 		group0 {
 			pins = <I2C0_SCL_PC4>, <I2C0_SDA_PC5>;
@@ -27,4 +40,12 @@
 			bias-pull-up;
 		};
 	};
+
+	itm_default: itm_default {
+		group0 {
+			pins = <GPIO_SWV_PA3>;
+			drive-push-pull;
+			output-high;
+		};
+	};
 };
diff --git a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts
index 0859df1b3d4..9fafecd6df1 100644
--- a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts
+++ b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.dts
@@ -75,6 +75,12 @@
 	clock-frequency = <78000000>;
 };
 
+&itm {
+	pinctrl-0 = <&itm_default>;
+	pinctrl-names = "default";
+	swo-ref-frequency = <DT_FREQ_M(78)>;
+};
+
 &hfxo {
 	status = "okay";
 	ctune = <140>;
@@ -124,6 +130,29 @@
 	status = "okay";
 };
 
+&eusart1 {
+	compatible = "silabs,eusart-spi";
+	pinctrl-0 = <&eusart1_default>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpioc 0 GPIO_ACTIVE_LOW>;
+	clock-frequency = <4000000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	mx25r32: mx25r3235f@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <80000000>;
+		size = <0x2000000>;
+		jedec-id = [c2 28 16];
+		has-dpd;
+		dpd-wakeup-sequence = <30000 20 35000>;
+		mxicy,mx25r-power-mode = "low-power";
+		zephyr,pm-device-runtime-auto;
+	};
+};
+
 &i2c0 {
 	pinctrl-0 = <&i2c0_default>;
 	pinctrl-names = "default";
@@ -230,6 +259,10 @@
 	status = "okay";
 };
 
+&radio {
+	pa-voltage-mv = <1800>;
+};
+
 &bt_hci_silabs {
 	status = "okay";
 };
diff --git a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.yaml b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.yaml
index 599c5c6657e..1682cc6038b 100644
--- a/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.yaml
+++ b/boards/silabs/dev_kits/xg24_dk2601b/xg24_dk2601b.yaml
@@ -15,8 +15,9 @@ supported:
   - dma
   - watchdog
   - clock_control
+  - comparator
+  - adc
 testing:
   ignore_tags:
     - pm
-    - hwinfo
 vendor: silabs
diff --git a/boards/silabs/dev_kits/xg24_ek2703a/Kconfig.defconfig b/boards/silabs/dev_kits/xg24_ek2703a/Kconfig.defconfig
index 53290acffd0..aa088655ef5 100644
--- a/boards/silabs/dev_kits/xg24_ek2703a/Kconfig.defconfig
+++ b/boards/silabs/dev_kits/xg24_ek2703a/Kconfig.defconfig
@@ -3,6 +3,9 @@
 
 if BOARD_XG24_EK2703A
 
+configdefault LOG_BACKEND_SWO_FREQ_HZ
+	default 875000
+
 config CMU_HFXO_FREQ
 	default 39000000
 
diff --git a/boards/silabs/dev_kits/xg24_ek2703a/doc/index.rst b/boards/silabs/dev_kits/xg24_ek2703a/doc/index.rst
index e841838b1be..59befeeec0f 100644
--- a/boards/silabs/dev_kits/xg24_ek2703a/doc/index.rst
+++ b/boards/silabs/dev_kits/xg24_ek2703a/doc/index.rst
@@ -29,35 +29,7 @@ documents:
 Supported Features
 ==================
 
-The ``xg24_ek2703a`` board supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | stimer                              |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | semailbox                           |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| I2C(M/S)  | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| RADIO     | on-chip    | bluetooth                           |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -99,6 +71,8 @@ USART0 is connected to the board controller and is used for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 .. note::
    Before using the kit the first time, you should update the J-Link firmware
    in Simplicity Studio.
diff --git a/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a-pinctrl.dtsi b/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a-pinctrl.dtsi
index 30aaa4655ba..81c23b9a88f 100644
--- a/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a-pinctrl.dtsi
+++ b/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a-pinctrl.dtsi
@@ -27,4 +27,12 @@
 			bias-pull-up;
 		};
 	};
+
+	itm_default: itm_default {
+		group0 {
+			pins = <GPIO_SWV_PA3>;
+			drive-push-pull;
+			output-high;
+		};
+	};
 };
diff --git a/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.dts b/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.dts
index a4bf9f857e5..7ebddf29945 100644
--- a/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.dts
+++ b/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.dts
@@ -64,6 +64,12 @@
 	clock-frequency = <78000000>;
 };
 
+&itm {
+	pinctrl-0 = <&itm_default>;
+	pinctrl-names = "default";
+	swo-ref-frequency = <DT_FREQ_M(78)>;
+};
+
 &hfxo {
 	status = "okay";
 	ctune = <140>;
diff --git a/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.yaml b/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.yaml
index 551f2754872..9a0285d4423 100644
--- a/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.yaml
+++ b/boards/silabs/dev_kits/xg24_ek2703a/xg24_ek2703a.yaml
@@ -14,8 +14,8 @@ supported:
   - uart
   - watchdog
   - clock_control
+  - comparator
 testing:
   ignore_tags:
     - pm
-    - hwinfo
 vendor: silabs
diff --git a/boards/silabs/dev_kits/xg27_dk2602a/Kconfig.defconfig b/boards/silabs/dev_kits/xg27_dk2602a/Kconfig.defconfig
index fac4f17b12e..866eb2483c3 100644
--- a/boards/silabs/dev_kits/xg27_dk2602a/Kconfig.defconfig
+++ b/boards/silabs/dev_kits/xg27_dk2602a/Kconfig.defconfig
@@ -1,6 +1,11 @@
 # Copyright (c) 2023 Antmicro <www.antmicro.com>
 # SPDX-License-Identifier: Apache-2.0
 
+if BOARD_XG27_DK2602A
+
+configdefault LOG_BACKEND_SWO_FREQ_HZ
+	default 875000
+
 if SOC_GECKO_USE_RAIL
 
 config FPU
@@ -24,3 +29,5 @@ endif # BT
 
 config REGULATOR
 	default y if SI7210
+
+endif
diff --git a/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst b/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst
index c700e1cf9c0..eec5ba7c021 100644
--- a/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst
+++ b/boards/silabs/dev_kits/xg27_dk2602a/doc/index.rst
@@ -32,23 +32,7 @@ For more information, refer to these documents:
 Supported Features
 ==================
 
-The xg27_dk2602a board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | ldma                                |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Flashing
 ========
@@ -97,6 +81,8 @@ Commander in unattended mode and passes all the necessary arguments to it.
 Programming and Debugging
 =========================
 
+.. zephyr:board-supported-runners::
+
 The sample application :zephyr:code-sample:`hello_world` is used for this example.
 Build the Zephyr kernel and application:
 
diff --git a/boards/silabs/dev_kits/xg27_dk2602a/thunderboard.dtsi b/boards/silabs/dev_kits/xg27_dk2602a/thunderboard.dtsi
index 0ec7c11aa15..771a45e1e93 100644
--- a/boards/silabs/dev_kits/xg27_dk2602a/thunderboard.dtsi
+++ b/boards/silabs/dev_kits/xg27_dk2602a/thunderboard.dtsi
@@ -68,6 +68,12 @@
 	clock-frequency = <76800000>;
 };
 
+&itm {
+	pinctrl-0 = <&itm_default>;
+	pinctrl-names = "default";
+	swo-ref-frequency = <DT_FREQ_K(76800)>;
+};
+
 &pstate_em3 {
 	status = "disabled";
 };
diff --git a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a-pinctrl.dtsi b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a-pinctrl.dtsi
index 915d9bfe209..2d2c481f2f5 100644
--- a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a-pinctrl.dtsi
+++ b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a-pinctrl.dtsi
@@ -39,4 +39,12 @@
 			bias-pull-up;
 		};
 	};
+
+	itm_default: itm_default {
+		group0 {
+			pins = <GPIO_SWV_PA3>;
+			drive-push-pull;
+			output-high;
+		};
+	};
 };
diff --git a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts
index f201a09e86a..7bd14874e9b 100644
--- a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts
+++ b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.dts
@@ -127,6 +127,10 @@
 	gpios = <&gpiob 3 GPIO_ACTIVE_LOW>;
 };
 
+&radio {
+	pa-voltage-mv = <1800>;
+};
+
 &bt_hci_silabs {
 	status = "okay";
 };
diff --git a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml
index 519f9ce9a9e..8f8bfd19fb2 100644
--- a/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml
+++ b/boards/silabs/dev_kits/xg27_dk2602a/xg27_dk2602a.yaml
@@ -7,7 +7,6 @@ flash: 768
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - bluetooth
   - counter
@@ -15,4 +14,6 @@ supported:
   - uart
   - dma
   - clock_control
+  - comparator
+  - adc
 vendor: silabs
diff --git a/boards/silabs/radio_boards/common/efr32-series1-common.dtsi b/boards/silabs/radio_boards/common/efr32-series1-common.dtsi
index 72e771c1b28..1a235e498af 100644
--- a/boards/silabs/radio_boards/common/efr32-series1-common.dtsi
+++ b/boards/silabs/radio_boards/common/efr32-series1-common.dtsi
@@ -64,7 +64,7 @@
 };
 
 &usart1 {
-	compatible = "silabs,gecko-spi-usart";
+	compatible = "silabs,usart-spi";
 
 	#address-cells = <1>;
 	#size-cells = <0>;
diff --git a/boards/silabs/radio_boards/siwx917_rb4338a/Kconfig.siwx917_rb4338a b/boards/silabs/radio_boards/siwx917_rb4338a/Kconfig.siwx917_rb4338a
new file mode 100644
index 00000000000..a27803e5014
--- /dev/null
+++ b/boards/silabs/radio_boards/siwx917_rb4338a/Kconfig.siwx917_rb4338a
@@ -0,0 +1,5 @@
+# Copyright (c) 2023 Antmicro
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_SIWX917_RB4338A
+	select SOC_PART_NUMBER_SIWG917M111MGTBA
diff --git a/boards/silabs/radio_boards/siwx917_rb4338a/board.cmake b/boards/silabs/radio_boards/siwx917_rb4338a/board.cmake
new file mode 100644
index 00000000000..7b487f2cec8
--- /dev/null
+++ b/boards/silabs/radio_boards/siwx917_rb4338a/board.cmake
@@ -0,0 +1,13 @@
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(silabs_commander "--device=SiWG917M111GTBA" "--file-type=bin"
+    "--file=${PROJECT_BINARY_DIR}/${KERNEL_BIN_NAME}.rps")
+include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake)
+
+# It is not possible to load/flash a firmware using JLink, but it is possible to
+# debug a firmware with:
+#    west attach -r jlink
+# Once started, it should be possible to reset the device with "monitor reset"
+board_runner_args(jlink "--device=Si917" "--speed=10000")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/silabs/radio_boards/siwx917_rb4338a/board.yml b/boards/silabs/radio_boards/siwx917_rb4338a/board.yml
new file mode 100644
index 00000000000..bf757c06ce3
--- /dev/null
+++ b/boards/silabs/radio_boards/siwx917_rb4338a/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: siwx917_rb4338a
+  full_name: SiWx917 Wi-Fi 6 and Bluetooth LE SoC 8 MB Flash Radio Board (SLWRB4338A)
+  vendor: silabs
+  socs:
+    - name: siwg917m111mgtba
diff --git a/boards/silabs/radio_boards/siwx917_rb4338a/doc/index.rst b/boards/silabs/radio_boards/siwx917_rb4338a/doc/index.rst
new file mode 100644
index 00000000000..20dbe472cb1
--- /dev/null
+++ b/boards/silabs/radio_boards/siwx917_rb4338a/doc/index.rst
@@ -0,0 +1,106 @@
+.. zephyr:board:: siwx917_rb4338a
+
+
+Overview
+********
+
+The SiWx917-RB4338A (aka BRD4338A) radio board provides support for the Silicon
+Labs SiWG917 SoC. This board cannot be used stand-alone and requires a a
+`Wireless Pro Kit`_ Mainboard (Si-MB4002A aka BRD4002A), for power, debug
+options etc.
+
+This board might be sold as a part of the `SiWx917-PK6031A`_ bundle ("SiWx917
+Wi-Fi 6 and Bluetooth LE 8 MB Flash Pro Kit"), which includes the BRD4002A
+Mainboard in addition of the BRD4338A.
+
+SiWG917 is an ultra-low power SoC that includes hardware support for Single-Band
+Wi-Fi 6 + Bluetooth LE 5.4, Matter...
+
+Hardware
+********
+
+For more information about the SiWG917 SoC and BRD4338A board, refer to these
+documents:
+
+- `SiWG917 Website`_
+- `SiWG917 Datasheet`_
+- `SiWG917 Reference Manual`_
+- `BRD4338A Website`_
+- `BRD4338A User Guide`_
+
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Flashing
+========
+
+Applications for the ``siwx917_rb4338a`` board can be built in the usual
+way. The flash method requires on `Simplicity Commander`_ installed on the host.
+
+Then, connect the BRD4002A board with a mounted BRD4338A radio module to your
+host computer using the USB port.
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: siwx917_rb4338a
+   :goals: flash
+
+Open a serial terminal (minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Reset the board and you should see the following message in the terminal:
+
+.. code-block:: console
+
+   Hello World! siwx917_rb4338a
+
+
+Debugging
+=========
+
+Debuggning relies on JLink tool. JLink is not able to flash the firmware. So
+debug session has to be done in two steps. ``west flash`` will flahs the
+firmware using Simplicity Commander. Then ``west attach`` will use JLink to
+attach to the board. The Zephyr image may has already booted when user runs
+``west attach``. User may execute ``monitor reset`` in the gdb prompt to reset
+the board.
+
+
+
+.. _SiWx917-PK6031A:
+   https://www.silabs.com/development-tools/wireless/wi-fi/siwx917-pk6031a-wifi-6-bluetooth-le-soc-pro-kit
+
+.. _Wireless Pro Kit:
+   https://www.silabs.com/development-tools/wireless/wireless-pro-kit-mainboard
+
+.. _BRD4338A Website:
+   https://www.silabs.com/development-tools/wireless/wi-fi/siwx917-rb4338a-wifi-6-bluetooth-le-soc-radio-board
+
+.. _BRD4338A User Guide:
+   https://www.silabs.com/documents/public/user-guides/ug562-brd4338a-user-guide.pdf
+
+.. _SiWG917 Website:
+   https://www.silabs.com/wireless/wi-fi/siwx917-wireless-socs
+
+.. _SiWG917 Datasheet:
+   https://www.silabs.com/documents/public/data-sheets/siwg917-datasheet.pdf
+
+.. _SiWG917 Reference Manual:
+   https://www.silabs.com/documents/public/reference-manuals/siw917x-family-rm.pdf
+
+.. _Simplicity Commander:
+   https://www.silabs.com/developer-tools/simplicity-studio/simplicity-commander
diff --git a/boards/silabs/radio_boards/siwx917_rb4338a/doc/siwx917_rb4338a.webp b/boards/silabs/radio_boards/siwx917_rb4338a/doc/siwx917_rb4338a.webp
new file mode 100644
index 00000000000..80bb6f8a346
Binary files /dev/null and b/boards/silabs/radio_boards/siwx917_rb4338a/doc/siwx917_rb4338a.webp differ
diff --git a/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a.dts b/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a.dts
new file mode 100644
index 00000000000..c0df650bfd7
--- /dev/null
+++ b/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a.dts
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2023 Antmicro
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <silabs/siwg917m111mgtba.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input-event-codes.h>
+#include <dt-bindings/pinctrl/silabs/siwx91x-pinctrl.h>
+#include <common/freq.h>
+
+/ {
+	model = "Silicon Labs BRD4338A (SiWG917 Radio Board)";
+	compatible = "silabs,x917_rb4338a", "silabs,siwg917";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,code-partition = &code_partition;
+		zephyr,console = &ulpuart;
+		zephyr,shell-uart = &ulpuart;
+		zephyr,uart-pipe = &ulpuart;
+		zephyr,bt-hci = &bt_hci0;
+	};
+
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		sw0 = &button0;
+		sw1 = &button1;
+		dht0 = &si7021;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led_0 {
+			gpios = <&ulpgpio 2 GPIO_ACTIVE_HIGH>;
+		};
+
+		led1: led_1 {
+			gpios = <&gpioa 10 GPIO_ACTIVE_HIGH>;
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		button0: button_0 {
+			gpios = <&uulpgpio 2 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		button1: button_1 {
+			gpios = <&gpioa 11 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+};
+
+&pinctrl0 {
+	ulpuart_default: ulpuart_default {
+		out {
+			pinmux = <ULPUART_TX_ULP11>;
+		};
+		in {
+			pinmux = <ULPUART_RX_ULP9>;
+		};
+	};
+
+	ulpi2c_default: ulpi2c_default {
+		group {
+			pinmux = <ULPI2C_SDA_ULP6>, <ULPI2C_SCL_ULP7>;
+		};
+	};
+};
+
+&ulpuart {
+	status = "okay";
+	pinctrl-0 = <&ulpuart_default>;
+	pinctrl-names = "default";
+};
+
+&ulpi2c {
+	status = "okay";
+	pinctrl-0 = <&ulpi2c_default>;
+	pinctrl-names = "default";
+	clock-frequency = <DT_FREQ_K(100)>;
+
+	si7021: si7021@40 {
+		compatible = "silabs,si7006";
+		reg = <0x40>;
+	};
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		code_partition: partition@0 {
+			label = "code_partition";
+			reg = <0x0000000 DT_SIZE_K(2008)>;
+		};
+
+		storage_partition: partition@1f6000 {
+			label = "storage";
+			reg = <0x001f6000 DT_SIZE_K(32)>;
+		};
+	};
+};
+
+&sysrtc0  {
+	status = "okay";
+};
+
+&bt_hci0 {
+	status = "okay";
+};
+
+&wifi0 {
+	status = "okay";
+};
diff --git a/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a.yaml b/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a.yaml
new file mode 100644
index 00000000000..29a0ddccea5
--- /dev/null
+++ b/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a.yaml
@@ -0,0 +1,20 @@
+identifier: siwx917_rb4338a
+name: SiWx917 Wi-Fi 6 and Bluetooth LE 8MB Flash Radio Board (SLWRB4338A, BRD4338A)
+type: mcu
+arch: arm
+ram: 191
+flash: 1024
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - bluetooth
+  - dma
+  - entropy
+  - flash
+  - gpio
+  - i2c
+  - pwm
+  - watchdog
+  - wifi
+vendor: silabs
diff --git a/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a_defconfig b/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a_defconfig
new file mode 100644
index 00000000000..afc7028e3b0
--- /dev/null
+++ b/boards/silabs/radio_boards/siwx917_rb4338a/siwx917_rb4338a_defconfig
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=180000000
+CONFIG_USE_DT_CODE_PARTITION=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/boards/silabs/radio_boards/slwrb4104a/doc/index.rst b/boards/silabs/radio_boards/slwrb4104a/doc/index.rst
index 1cee2ffd5ab..ac419da806f 100644
--- a/boards/silabs/radio_boards/slwrb4104a/doc/index.rst
+++ b/boards/silabs/radio_boards/slwrb4104a/doc/index.rst
@@ -37,33 +37,7 @@ documents:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtcc                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| SPI(M)    | on-chip    | spi port-polling                    |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/silabs/radio_boards/slwrb4104a/slwrb4104a_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -113,6 +87,8 @@ USART0 is connected to the board controller and is used for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/silabs/radio_boards/slwrb4104a/slwrb4104a.yaml b/boards/silabs/radio_boards/slwrb4104a/slwrb4104a.yaml
index a407f847f6f..56a9c32bd47 100644
--- a/boards/silabs/radio_boards/slwrb4104a/slwrb4104a.yaml
+++ b/boards/silabs/radio_boards/slwrb4104a/slwrb4104a.yaml
@@ -7,7 +7,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - gpio
diff --git a/boards/silabs/radio_boards/slwrb4161a/doc/index.rst b/boards/silabs/radio_boards/slwrb4161a/doc/index.rst
index 134dbdb3af0..f2e0fcdb7b1 100644
--- a/boards/silabs/radio_boards/slwrb4161a/doc/index.rst
+++ b/boards/silabs/radio_boards/slwrb4161a/doc/index.rst
@@ -32,33 +32,7 @@ documents:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtcc                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| SPI(M)    | on-chip    | spi port-polling                    |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/silabs/radio_boards/slwrb4161a/slwrb4161a_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -107,6 +81,8 @@ USART0 is connected to the board controller and is used for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/silabs/radio_boards/slwrb4161a/slwrb4161a.dts b/boards/silabs/radio_boards/slwrb4161a/slwrb4161a.dts
index 90787898290..2e978e83f4a 100644
--- a/boards/silabs/radio_boards/slwrb4161a/slwrb4161a.dts
+++ b/boards/silabs/radio_boards/slwrb4161a/slwrb4161a.dts
@@ -69,7 +69,7 @@
 };
 
 &usart2 {
-	compatible = "silabs,gecko-spi-usart";
+	compatible = "silabs,usart-spi";
 	#address-cells = <1>;
 	#size-cells = <0>;
 	pinctrl-0 = <&usart2_default>;
diff --git a/boards/silabs/radio_boards/slwrb4170a/doc/index.rst b/boards/silabs/radio_boards/slwrb4170a/doc/index.rst
index 9c96d7ec31e..54ec7a1985b 100644
--- a/boards/silabs/radio_boards/slwrb4170a/doc/index.rst
+++ b/boards/silabs/radio_boards/slwrb4170a/doc/index.rst
@@ -32,33 +32,7 @@ documents:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtcc                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| SPI(M)    | on-chip    | spi port-polling                    |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/silabs/radio_boards/slwrb4170a/slwrb4170a_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -107,6 +81,8 @@ USART0 is connected to the board controller and is used for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/silabs/radio_boards/slwrb4180a/doc/index.rst b/boards/silabs/radio_boards/slwrb4180a/doc/index.rst
index d49a5770e4c..540c4f96739 100644
--- a/boards/silabs/radio_boards/slwrb4180a/doc/index.rst
+++ b/boards/silabs/radio_boards/slwrb4180a/doc/index.rst
@@ -34,34 +34,7 @@ documents:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtcc                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c port-polling                    |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip     | ldma                               |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -106,6 +79,8 @@ USART0 is connected to the board controller and is used for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.yaml b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.yaml
index 580908453da..b359407b929 100644
--- a/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.yaml
+++ b/boards/silabs/radio_boards/slwrb4180a/slwrb4180a.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - gpio
diff --git a/boards/silabs/radio_boards/slwrb4180b/Kconfig.defconfig b/boards/silabs/radio_boards/slwrb4180b/Kconfig.defconfig
new file mode 100644
index 00000000000..9fa20f62d7c
--- /dev/null
+++ b/boards/silabs/radio_boards/slwrb4180b/Kconfig.defconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2020 Piotr Mienkowski
+# Copyright (c) 2020 TriaGnoSys GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_SLWRB4180B
+
+config LOG_BACKEND_SWO_FREQ_HZ
+	default 875000
+	depends on LOG_BACKEND_SWO
+
+if SOC_GECKO_USE_RAIL
+
+config FPU
+	default y
+
+endif # SOC_GECKO_USE_RAIL
+
+endif # BOARD_SLWRB4180B
diff --git a/boards/silabs/radio_boards/slwrb4180b/Kconfig.slwrb4180b b/boards/silabs/radio_boards/slwrb4180b/Kconfig.slwrb4180b
new file mode 100644
index 00000000000..b802cf3ae94
--- /dev/null
+++ b/boards/silabs/radio_boards/slwrb4180b/Kconfig.slwrb4180b
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Capgemini
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_SLWRB4180B
+	select SOC_PART_NUMBER_EFR32MG21A020F1024IM32
diff --git a/boards/silabs/radio_boards/slwrb4180b/board.cmake b/boards/silabs/radio_boards/slwrb4180b/board.cmake
new file mode 100644
index 00000000000..9505e42eed4
--- /dev/null
+++ b/boards/silabs/radio_boards/slwrb4180b/board.cmake
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=EFR32MG21AxxxF1024")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+
+board_runner_args(openocd)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+
+board_runner_args(silabs_commander "--device=EFR32MG21A020F1024IM32")
+include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake)
diff --git a/boards/silabs/radio_boards/slwrb4180b/board.yml b/boards/silabs/radio_boards/slwrb4180b/board.yml
new file mode 100644
index 00000000000..adef398703b
--- /dev/null
+++ b/boards/silabs/radio_boards/slwrb4180b/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: slwrb4180b
+  full_name: EFR32xG21 2.4 GHz 20 dBm (SLWRB4180B)
+  vendor: silabs
+  socs:
+    - name: efr32mg21a020f1024im32
diff --git a/boards/silabs/radio_boards/slwrb4180b/doc/efr32mg21-slwrb4180b.webp b/boards/silabs/radio_boards/slwrb4180b/doc/efr32mg21-slwrb4180b.webp
new file mode 100644
index 00000000000..cc37a1a5747
Binary files /dev/null and b/boards/silabs/radio_boards/slwrb4180b/doc/efr32mg21-slwrb4180b.webp differ
diff --git a/boards/silabs/radio_boards/slwrb4180b/doc/index.rst b/boards/silabs/radio_boards/slwrb4180b/doc/index.rst
new file mode 100644
index 00000000000..f47dffab43e
--- /dev/null
+++ b/boards/silabs/radio_boards/slwrb4180b/doc/index.rst
@@ -0,0 +1,112 @@
+.. zephyr:board:: slwrb4180b
+
+Overview
+********
+
+The EFR32MG21 Mighty Gecko Radio Board is one of the two
+radio boards delivered with `EFR32-SLWSTK6006A Website`_. It features a
+Wireless System-On-Chip (SoC) from the EFR32MG21 family, built on an
+ARM Cortex®-M33F processor, offering exceptional low-power performance.
+
+The SLWRB4180B radio board is designed to connect seamlessly with
+the Wireless Starter Kit Mainboards BRD4001A and BRD4002A
+
+Hardware
+********
+
+- EFR32MG21A020F1024IM32 Mighty Gecko SoC
+- CPU core: ARM Cortex®-M33 with FPU
+- Flash memory: 1024 kB
+- RAM: 96 kB
+- Transmit power: up to +20 dBm
+- Operation frequency: 2.4 GHz
+- Crystals for LFXO (32.768 kHz) and HFXO (38.4 MHz).
+
+For more information about the EFR32MG21 SoC and BRD4180B board, refer to these
+documents:
+
+- `EFR32MG21 Website`_
+- `EFR32MG21 Datasheet`_
+- `EFR32xG21 Reference Manual`_
+- `EFR32-SLWSTK6006A Website`_
+- `BRD4180B User Guide`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+In the following table, the column **Name** contains Pin names. For example, PD2
+means Pin number 2 on PORTD, as used in the board's datasheets and manuals.
+
++-------+-------------+-------------------------------------+
+| Name  | Function    | Usage                               |
++=======+=============+=====================================+
+| PD2   | GPIO        | LED0                                |
++-------+-------------+-------------------------------------+
+| PD3   | GPIO        | LED1                                |
++-------+-------------+-------------------------------------+
+| PB0   | GPIO        | Push Button PB0                     |
++-------+-------------+-------------------------------------+
+| PB1   | GPIO        | Push Button PB1                     |
++-------+-------------+-------------------------------------+
+| PD4   | GPIO        | Board Controller Enable             |
+|       |             | EFM_BC_EN                           |
++-------+-------------+-------------------------------------+
+| PA5   | USART1_TX   | UART Console EFM_BC_TX US1_TX       |
++-------+-------------+-------------------------------------+
+| PA6   | USART1_RX   | UART Console EFM_BC_RX US1_RX       |
++-------+-------------+-------------------------------------+
+
+The default configuration can be found in
+:zephyr_file:`boards/silabs/radio_boards/slwrb4180b/slwrb4180b_defconfig`
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Flashing
+========
+
+Connect the BRD4001A or BRD4002A mainboard, with the BRD4180B radio module mounted,
+to your host computer via the USB port.
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: slwrb4180b
+   :goals: flash
+
+Open a serial terminal (minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Reset the board and you should see the following message in the terminal:
+
+.. code-block:: console
+
+   Hello World! slwrb4180b
+
+
+.. _EFR32-SLWSTK6006A Website:
+   https://www.silabs.com/products/development-tools/wireless/efr32xg21-wireless-starter-kit
+
+.. _BRD4180B User Guide:
+   https://www.silabs.com/documents/public/user-guides/ug427-brd4180b-user-guide.pdf
+
+.. _EFR32MG21 Website:
+   https://www.silabs.com/products/wireless/mesh-networking/efr32mg21-series-2-socs
+
+.. _EFR32MG21 Datasheet:
+   https://www.silabs.com/documents/public/data-sheets/efr32mg21-datasheet.pdf
+
+.. _EFR32xG21 Reference Manual:
+   https://www.silabs.com/documents/public/reference-manuals/efr32xg21-rm.pdf
diff --git a/boards/silabs/radio_boards/slwrb4180b/pre_dt_board.cmake b/boards/silabs/radio_boards/slwrb4180b/pre_dt_board.cmake
new file mode 100644
index 00000000000..beb76b85552
--- /dev/null
+++ b/boards/silabs/radio_boards/slwrb4180b/pre_dt_board.cmake
@@ -0,0 +1,5 @@
+# Copyright (c) 2021 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+# SPI is implemented via usart so node name isn't spi@...
+list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge")
diff --git a/boards/silabs/radio_boards/slwrb4180b/slwrb4180b-pinctrl.dtsi b/boards/silabs/radio_boards/slwrb4180b/slwrb4180b-pinctrl.dtsi
new file mode 100644
index 00000000000..4f8612eb15b
--- /dev/null
+++ b/boards/silabs/radio_boards/slwrb4180b/slwrb4180b-pinctrl.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 Capgemini
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/silabs/xg21-pinctrl.h>
+
+&pinctrl {
+	usart0_default: usart0_default {
+		group0 {
+			pins = <USART0_TX_PA5>;
+			drive-push-pull;
+			output-high;
+		};
+		group1 {
+			pins = <USART0_RX_PA6>;
+			input-enable;
+			silabs,input-filter;
+		};
+	};
+};
diff --git a/boards/silabs/radio_boards/slwrb4180b/slwrb4180b.dts b/boards/silabs/radio_boards/slwrb4180b/slwrb4180b.dts
new file mode 100644
index 00000000000..77654a1f033
--- /dev/null
+++ b/boards/silabs/radio_boards/slwrb4180b/slwrb4180b.dts
@@ -0,0 +1,183 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Capgemini
+ *
+ */
+
+/dts-v1/;
+#include <silabs/efr32mg21a020f1024im32.dtsi>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include "slwrb4180b-pinctrl.dtsi"
+
+/ {
+	model = "Silicon Labs BRD4180B (Wireless Gecko 21 Radio Board)";
+	compatible = "silabs,slwrb4180b", "silabs,efr32mg21";
+
+	chosen {
+		zephyr,console = &usart0;
+		zephyr,shell-uart = &usart0;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+	};
+
+	/* These aliases are provided for compatibility with samples */
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		sw0 = &button0;
+		sw1 = &button1;
+		watchdog0 = &wdog0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led_0 {
+			gpios = <&gpiod 2 0>;
+			label = "LED0";
+		};
+
+		led1: led_1 {
+			gpios = <&gpiod 3 0>;
+			label = "LED1";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		button0: button_0 {
+			gpios = <&gpiob 0 GPIO_ACTIVE_LOW>;
+			label = "BTN0";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		button1: button_1 {
+			gpios = <&gpiob 1 GPIO_ACTIVE_LOW>;
+			label = "BTN1";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+};
+
+&cpu0 {
+	clock-frequency = <76800000>;
+};
+
+&hfxo {
+	status = "okay";
+	ctune = <129>;
+	precision = <50>;
+};
+
+&lfxo {
+	status = "okay";
+	ctune = <79>;
+	precision = <50>;
+};
+
+&hfrcodpll {
+	clock-frequency = <DT_FREQ_K(76800)>;
+	clocks = <&hfxo>;
+	dpll-n = <3839>;
+	dpll-m = <1919>;
+	dpll-edge = "fall";
+	dpll-lock = "phase";
+	dpll-autorecover;
+};
+
+&em23grpaclk {
+	clocks = <&lfxo>;
+};
+
+&em4grpaclk {
+	clocks = <&lfxo>;
+};
+
+&rtccclk {
+	clocks = <&lfxo>;
+};
+
+&wdog0clk {
+	clocks = <&lfxo>;
+};
+
+&wdog1clk {
+	clocks = <&lfxo>;
+};
+
+&usart0 {
+	current-speed = <115200>;
+	pinctrl-0 = <&usart0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&rtcc0 {
+	prescaler = <1>;
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpioa {
+	status = "okay";
+};
+
+&gpiob {
+	status = "okay";
+};
+
+&gpioc {
+	status = "okay";
+};
+
+&gpiod {
+	status = "okay";
+
+	board-controller-enable {
+		gpio-hog;
+		gpios = <4 GPIO_ACTIVE_HIGH>;
+		output-high;
+	};
+};
+
+&wdog0 {
+	status = "okay";
+};
+
+&dma0 {
+	status = "okay";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 DT_SIZE_K(48)>;
+		};
+
+		slot0_partition: partition@c000 {
+			label = "image-0";
+			reg = <0x0000C000 DT_SIZE_K(472)>;
+		};
+
+		slot1_partition: partition@82000 {
+			label = "image-1";
+			reg = <0x00082000 DT_SIZE_K(472)>;
+		};
+
+		storage_partition: partition@F8000 {
+			label = "storage";
+			reg = <0x000F8000 DT_SIZE_K(32)>;
+		};
+	};
+};
diff --git a/boards/silabs/radio_boards/slwrb4180b/slwrb4180b.yaml b/boards/silabs/radio_boards/slwrb4180b/slwrb4180b.yaml
new file mode 100644
index 00000000000..c6e9d2b90cf
--- /dev/null
+++ b/boards/silabs/radio_boards/slwrb4180b/slwrb4180b.yaml
@@ -0,0 +1,18 @@
+identifier: slwrb4180b
+name: EFR32xG21 2.4 GHz 20 dBm Radio Board (SLWRB4180B)
+type: mcu
+arch: arm
+ram: 96
+flash: 1024
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+supported:
+  - counter
+  - gpio
+  - nvs
+  - uart
+  - dma
+  - watchdog
+vendor: silabs
diff --git a/boards/silabs/radio_boards/slwrb4180b/slwrb4180b_defconfig b/boards/silabs/radio_boards/slwrb4180b/slwrb4180b_defconfig
new file mode 100644
index 00000000000..e70f8f5c519
--- /dev/null
+++ b/boards/silabs/radio_boards/slwrb4180b/slwrb4180b_defconfig
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARM_MPU=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_GPIO=y
diff --git a/boards/silabs/radio_boards/slwrb4180b/support/openocd.cfg b/boards/silabs/radio_boards/slwrb4180b/support/openocd.cfg
new file mode 100644
index 00000000000..38409eb70ad
--- /dev/null
+++ b/boards/silabs/radio_boards/slwrb4180b/support/openocd.cfg
@@ -0,0 +1,25 @@
+if {[info exists env(OPENOCD_INTERFACE)]} {
+	set INTERFACE $env(OPENOCD_INTERFACE)
+} else {
+	# By default connect over Debug USB port using the J-Link interface
+	set INTERFACE "jlink"
+}
+
+source [find interface/$INTERFACE.cfg]
+
+transport select swd
+
+set CHIPNAME efr32
+
+source [find target/efm32.cfg]
+
+$_TARGETNAME configure -event gdb-attach {
+	echo "Debugger attaching: halting execution"
+	reset halt
+	gdb_breakpoint_override hard
+}
+
+$_TARGETNAME configure -event gdb-detach {
+	echo "Debugger detaching: resuming execution"
+	resume
+}
diff --git a/boards/silabs/radio_boards/slwrb4250b/doc/index.rst b/boards/silabs/radio_boards/slwrb4250b/doc/index.rst
index 57a26c65cbf..8908b8eda38 100644
--- a/boards/silabs/radio_boards/slwrb4250b/doc/index.rst
+++ b/boards/silabs/radio_boards/slwrb4250b/doc/index.rst
@@ -36,33 +36,7 @@ documents:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtcc                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| SPI(M)    | on-chip    | spi port-polling                    |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/silabs/radio_boards/slwrb4250b/slwrb4250b_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -111,6 +85,8 @@ USART0 is connected to the board controller and is used for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/silabs/radio_boards/slwrb4250b/slwrb4250b.yaml b/boards/silabs/radio_boards/slwrb4250b/slwrb4250b.yaml
index 699eaf13971..0d89f5be4b3 100644
--- a/boards/silabs/radio_boards/slwrb4250b/slwrb4250b.yaml
+++ b/boards/silabs/radio_boards/slwrb4250b/slwrb4250b.yaml
@@ -7,7 +7,6 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - gpio
diff --git a/boards/silabs/radio_boards/slwrb4255a/doc/index.rst b/boards/silabs/radio_boards/slwrb4255a/doc/index.rst
index 47cb5a15fbb..84ba0aa8d47 100644
--- a/boards/silabs/radio_boards/slwrb4255a/doc/index.rst
+++ b/boards/silabs/radio_boards/slwrb4255a/doc/index.rst
@@ -32,33 +32,7 @@ documents:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtcc                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| SPI(M)    | on-chip    | spi port-polling                    |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/silabs/radio_boards/slwrb4255a/slwrb4255a_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -107,6 +81,8 @@ USART0 is connected to the board controller and is used for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/silabs/radio_boards/slwrb4255a/slwrb4255a.yaml b/boards/silabs/radio_boards/slwrb4255a/slwrb4255a.yaml
index 2e5a295ff8e..116d7acbaf2 100644
--- a/boards/silabs/radio_boards/slwrb4255a/slwrb4255a.yaml
+++ b/boards/silabs/radio_boards/slwrb4255a/slwrb4255a.yaml
@@ -7,7 +7,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - gpio
diff --git a/boards/silabs/radio_boards/slwrb4321a/doc/index.rst b/boards/silabs/radio_boards/slwrb4321a/doc/index.rst
index ccd82c5387e..e61d4f95529 100644
--- a/boards/silabs/radio_boards/slwrb4321a/doc/index.rst
+++ b/boards/silabs/radio_boards/slwrb4321a/doc/index.rst
@@ -33,37 +33,7 @@ For more information about the WGM160P and SLWSTK6121A board:
 Supported Features
 ==================
 
-The slwrb4321a board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtcc                                |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c port-polling                    |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/silabs/radio_boards/slwrb4321a/slwrb4321a_defconfig`
-
-Other hardware features, including the WF200 WiFi transceiver, are
-currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -110,6 +80,8 @@ USART0 is connected to the board controller and is used for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 .. note::
    Before using the kit the first time, you should update the J-Link firmware
    in Simplicity Studio.
diff --git a/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.dts b/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.dts
index a778fbfb180..e9122db2ab7 100644
--- a/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.dts
+++ b/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.dts
@@ -125,19 +125,19 @@
 
 	/* PHY management pins */
 	location-mdio        = <GECKO_LOCATION(3)>;
-	location-phy_mdc     = <GECKO_LOCATION(3) GECKO_PORT_A GECKO_PIN(6)>;
-	location-phy_mdio    = <GECKO_LOCATION(3) GECKO_PORT_A GECKO_PIN(15)>;
+	location-phy-mdc     = <GECKO_LOCATION(3) GECKO_PORT_A GECKO_PIN(6)>;
+	location-phy-mdio    = <GECKO_LOCATION(3) GECKO_PORT_A GECKO_PIN(15)>;
 
 	/* RMII interface pins */
 	location-rmii        = <GECKO_LOCATION(0)>;
-	location-rmii_refclk = <GECKO_LOCATION(0) GECKO_PORT_A GECKO_PIN(3)>;
-	location-rmii_crs_dv = <GECKO_LOCATION(0) GECKO_PORT_A GECKO_PIN(4)>;
-	location-rmii_txd0   = <GECKO_LOCATION(0) GECKO_PORT_E GECKO_PIN(15)>;
-	location-rmii_txd1   = <GECKO_LOCATION(0) GECKO_PORT_E GECKO_PIN(14)>;
-	location-rmii_tx_en  = <GECKO_LOCATION(0) GECKO_PORT_A GECKO_PIN(0)>;
-	location-rmii_rxd0   = <GECKO_LOCATION(0) GECKO_PORT_A GECKO_PIN(2)>;
-	location-rmii_rxd1   = <GECKO_LOCATION(0) GECKO_PORT_A GECKO_PIN(1)>;
-	location-rmii_rx_er  = <GECKO_LOCATION(0) GECKO_PORT_A GECKO_PIN(5)>;
+	location-rmii-refclk = <GECKO_LOCATION(0) GECKO_PORT_A GECKO_PIN(3)>;
+	location-rmii-crs-dv = <GECKO_LOCATION(0) GECKO_PORT_A GECKO_PIN(4)>;
+	location-rmii-txd0   = <GECKO_LOCATION(0) GECKO_PORT_E GECKO_PIN(15)>;
+	location-rmii-txd1   = <GECKO_LOCATION(0) GECKO_PORT_E GECKO_PIN(14)>;
+	location-rmii-tx-en  = <GECKO_LOCATION(0) GECKO_PORT_A GECKO_PIN(0)>;
+	location-rmii-rxd0   = <GECKO_LOCATION(0) GECKO_PORT_A GECKO_PIN(2)>;
+	location-rmii-rxd1   = <GECKO_LOCATION(0) GECKO_PORT_A GECKO_PIN(1)>;
+	location-rmii-rx-er  = <GECKO_LOCATION(0) GECKO_PORT_A GECKO_PIN(5)>;
 
 	status = "okay";
 };
diff --git a/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.yaml b/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.yaml
index b6f05256c98..1ddec312c05 100644
--- a/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.yaml
+++ b/boards/silabs/radio_boards/slwrb4321a/slwrb4321a.yaml
@@ -7,7 +7,6 @@ flash: 2048
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - i2c
diff --git a/boards/silabs/radio_boards/xg23_rb4210a/doc/index.rst b/boards/silabs/radio_boards/xg23_rb4210a/doc/index.rst
index 153ef502a7c..866b1a93752 100644
--- a/boards/silabs/radio_boards/xg23_rb4210a/doc/index.rst
+++ b/boards/silabs/radio_boards/xg23_rb4210a/doc/index.rst
@@ -21,6 +21,9 @@ Hardware
 - Transmit power: up to +20 dBm
 - Operation frequency: 868-915 MHz
 - Crystals for LFXO (32.768 kHz) and HFXO (39 MHz).
+- Silicon Labs Si7021 relative humidity and temperature sensor
+- Low-power 128x128 pixel Memory LCD
+- Macronix ultra low power 8-Mbit SPI flash (MX25R8035F)
 
 For more information about the EFR32ZG23 SoC and BRD4210A board, refer to these
 documents:
@@ -34,37 +37,7 @@ documents:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | stimer                              |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | ldma                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | semailbox                           |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -75,20 +48,37 @@ means Pin number 2 on PORTA, as used in the board's datasheets and manuals.
 +-------+-------------+-------------------------------------+
 | Name  | Function    | Usage                               |
 +=======+=============+=====================================+
-| PB2   | GPIO        | LED0                                |
+| PA8   | EUSART0_TX  | UART Console TX                     |
 +-------+-------------+-------------------------------------+
-| PD3   | GPIO        | LED1                                |
+| PA9   | EUSART0_RX  | UART Console RX                     |
++-------+-------------+-------------------------------------+
+| PB0   | GPIO        | Board Controller Enable             |
 +-------+-------------+-------------------------------------+
 | PB1   | GPIO        | Push Button 0                       |
 +-------+-------------+-------------------------------------+
+| PB2   | GPIO        | LED0                                |
++-------+-------------+-------------------------------------+
 | PB3   | GPIO        | Push Button 1                       |
 +-------+-------------+-------------------------------------+
-| PB0   | GPIO        | Board Controller Enable             |
-|       |             | VCOM_ENABLE                         |
+| PC1   | EUSART1_TX  | Display/Flash SPI MOSI              |
++-------+-------------+-------------------------------------+
+| PC2   | EUSART1_RX  | Flash SPI MISO                      |
 +-------+-------------+-------------------------------------+
-| PA8   | USART0_TX   | UART Console VCOM_TX US0_TX         |
+| PC3   | EUSART1_CLK | Display/Flash SPI Clock             |
 +-------+-------------+-------------------------------------+
-| PA9   | USART0_RX   | UART Console VCOM_RX US0_RX         |
+| PC4   | GPIO        | Flash SPI Chip Select               |
++-------+-------------+-------------------------------------+
+| PC5   | I2C0_SCL    | Si7021 I2C Clock                    |
++-------+-------------+-------------------------------------+
+| PC6   | GPIO        | Display COM Inversion               |
++-------+-------------+-------------------------------------+
+| PC7   | I2C0_SDA    | Si7021 I2C Data                     |
++-------+-------------+-------------------------------------+
+| PC8   | GPIO        | Display SPI Chip Select             |
++-------+-------------+-------------------------------------+
+| PC9   | GPIO        | Display/Si7021 Enable               |
++-------+-------------+-------------------------------------+
+| PD3   | GPIO        | LED1                                |
 +-------+-------------+-------------------------------------+
 
 The default configuration can be found in
@@ -109,6 +99,8 @@ USART0 is connected to the board controller and is used for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a-pinctrl.dtsi b/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a-pinctrl.dtsi
index 9b7f1b02c58..ec58fdc58f2 100644
--- a/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a-pinctrl.dtsi
+++ b/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a-pinctrl.dtsi
@@ -7,16 +7,45 @@
 #include <dt-bindings/pinctrl/silabs/xg23-pinctrl.h>
 
 &pinctrl {
-	usart0_default: usart0_default {
+	eusart0_default: eusart0_default {
 		group0 {
-			pins = <USART0_TX_PA8>;
+			pins = <EUSART0_TX_PA8>;
 			drive-push-pull;
 			output-high;
 		};
 		group1 {
-			pins = <USART0_RX_PA9>;
+			pins = <EUSART0_RX_PA9>;
 			input-enable;
 			silabs,input-filter;
 		};
 	};
+
+	eusart1_default: eusart1_default {
+		group0 {
+			pins = <EUSART1_TX_PC1>, <EUSART1_SCLK_PC3>;
+			drive-push-pull;
+			output-high;
+		};
+		group1 {
+			pins = <EUSART1_RX_PC2>;
+			input-enable;
+			silabs,input-filter;
+		};
+	};
+
+	i2c0_default: i2c0_default {
+		group0 {
+			pins = <I2C0_SCL_PC5>, <I2C0_SDA_PC7>;
+			drive-open-drain;
+			bias-pull-up;
+		};
+	};
+
+	itm_default: itm_default {
+		group0 {
+			pins = <GPIO_SWV_PA3>;
+			drive-push-pull;
+			output-high;
+		};
+	};
 };
diff --git a/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.dts b/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.dts
index c5800aeb520..dd94b0dfa36 100644
--- a/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.dts
+++ b/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.dts
@@ -15,12 +15,13 @@
 	compatible = "silabs,xg23_rb4210a", "silabs,efr32zg23";
 
 	chosen {
-		zephyr,console = &usart0;
-		zephyr,shell-uart = &usart0;
-		zephyr,uart-pipe = &usart0;
+		zephyr,console = &eusart0;
+		zephyr,shell-uart = &eusart0;
+		zephyr,uart-pipe = &eusart0;
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
 		zephyr,code-partition = &slot0_partition;
+		zephyr,display = &ls0xx_ls013b7dh03;
 	};
 
 	aliases {
@@ -29,6 +30,7 @@
 		sw0 = &button0;
 		sw1 = &button1;
 		watchdog0 = &wdog0;
+		dht0 = &si7021;
 	};
 
 	leds {
@@ -57,12 +59,24 @@
 		};
 	};
 
+	sensor_disp_enable: sensor_disp_enable {
+		compatible = "regulator-fixed";
+		regulator-name = "sensor_disp_enable";
+		enable-gpios = <&gpioc 9 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
 };
 
 &cpu0 {
 	clock-frequency = <78000000>;
 };
 
+&itm {
+	pinctrl-0 = <&itm_default>;
+	pinctrl-names = "default";
+	swo-ref-frequency = <DT_FREQ_M(78)>;
+};
+
 &pstate_em3 {
 	status = "disabled";
 };
@@ -109,13 +123,59 @@
 	clocks = <&lfxo>;
 };
 
-&usart0 {
+&eusart0 {
+	compatible = "silabs,eusart-uart";
 	current-speed = <115200>;
-	pinctrl-0 = <&usart0_default>;
+	pinctrl-0 = <&eusart0_default>;
 	pinctrl-names = "default";
 	status = "okay";
 };
 
+&eusart1 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-0 = <&eusart1_default>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpioc 8 GPIO_ACTIVE_HIGH>, <&gpioc 4 GPIO_ACTIVE_LOW>;
+
+	ls0xx_ls013b7dh03: ls0xx@0 {
+		compatible = "sharp,ls0xx";
+		spi-max-frequency = <DT_FREQ_K(1100)>;
+		reg = <0>;
+		width = <128>;
+		height = <128>;
+		extcomin-gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>;
+		extcomin-frequency = <60>;
+		disp-en-gpios = <&gpioc 9 GPIO_ACTIVE_HIGH>;
+	};
+
+	mx25r80: mx25r8035f@1 {
+		compatible = "jedec,spi-nor";
+		reg = <1>;
+		spi-max-frequency = <DT_FREQ_M(33)>;
+		size = <DT_SIZE_M(8)>;
+		jedec-id = [c2 28 14];
+		has-dpd;
+		dpd-wakeup-sequence = <30000 20 35000>;
+		t-enter-dpd = <0>;
+		mxicy,mx25r-power-mode = "low-power";
+	};
+};
+
+&i2c0 {
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	si7021: si7021@40 {
+		compatible = "silabs,si7006";
+		reg = <0x40>;
+		vin-supply = <&sensor_disp_enable>;
+		status = "okay";
+	};
+};
+
 &gpio {
 	status = "okay";
 };
diff --git a/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.yaml b/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.yaml
index a9229ef60b1..1a95532a64f 100644
--- a/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.yaml
+++ b/boards/silabs/radio_boards/xg23_rb4210a/xg23_rb4210a.yaml
@@ -7,7 +7,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - clock_control
   - counter
@@ -21,6 +20,7 @@ supported:
   - uart
   - dma
   - watchdog
+  - comparator
 testing:
   ignore_tags:
     - pm
diff --git a/boards/silabs/radio_boards/xg24_rb4187c/doc/index.rst b/boards/silabs/radio_boards/xg24_rb4187c/doc/index.rst
index f104714f2b3..9d836519b5e 100644
--- a/boards/silabs/radio_boards/xg24_rb4187c/doc/index.rst
+++ b/boards/silabs/radio_boards/xg24_rb4187c/doc/index.rst
@@ -34,69 +34,13 @@ documents:
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | stimer                              |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | ldma                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | semailbox                           |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are currently not supported by the port.
-
-Connections and IOs
-===================
-
-In the following table, the column **Name** contains Pin names. For example, PA2
-means Pin number 2 on PORTA, as used in the board's datasheets and manuals.
-
-+-------+-------------+-------------------------------------+
-| Name  | Function    | Usage                               |
-+=======+=============+=====================================+
-| PB2   | GPIO        | LED0                                |
-+-------+-------------+-------------------------------------+
-| PB4   | GPIO        | LED1                                |
-+-------+-------------+-------------------------------------+
-| PB1   | GPIO        | Push Button 0                       |
-+-------+-------------+-------------------------------------+
-| PB3   | GPIO        | Push Button 1                       |
-+-------+-------------+-------------------------------------+
-| PB0   | GPIO        | Board Controller Enable             |
-|       |             | VCOM_ENABLE                         |
-+-------+-------------+-------------------------------------+
-| PA8   | USART0_TX   | UART Console VCOM_TX US0_TX         |
-+-------+-------------+-------------------------------------+
-| PA9   | USART0_RX   | UART Console VCOM_RX US0_RX         |
-+-------+-------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c_defconfig`
+.. zephyr:board-supported-hw::
 
 System Clock
 ============
 
-The EFR32MG24 SoC is configured to use the 39 MHz external oscillator on the
-board.
+The EFR32MG24 SoC is configured to use the HFRCODPLL oscillator at 78 MHz as the system clock,
+locked to the 39 MHz external crystal oscillator on the board.
 
 Serial Port
 ===========
@@ -107,6 +51,8 @@ USART0 is connected to the board controller and is used for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c-pinctrl.dtsi b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c-pinctrl.dtsi
index 75e9112e69c..67e9032e418 100644
--- a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c-pinctrl.dtsi
+++ b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c-pinctrl.dtsi
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ * Copyright (c) 2025 Silicon Laboratories Inc.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,4 +20,33 @@
 			silabs,input-filter;
 		};
 	};
+
+	eusart1_default: eusart1_default {
+		group0 {
+			pins = <EUSART1_TX_PC1>, <EUSART1_SCLK_PC3>;
+			drive-push-pull;
+			output-high;
+		};
+		group1 {
+			pins = <EUSART1_RX_PC2>;
+			input-enable;
+			silabs,input-filter;
+		};
+	};
+
+	i2c0_default: i2c0_default {
+		group0 {
+			pins = <I2C0_SCL_PC5>, <I2C0_SDA_PC7>;
+			drive-open-drain;
+			bias-pull-up;
+		};
+	};
+
+	itm_default: itm_default {
+		group0 {
+			pins = <GPIO_SWV_PA3>;
+			drive-push-pull;
+			output-high;
+		};
+	};
 };
diff --git a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts
index 819ed7cd800..ba9e0a1420a 100644
--- a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts
+++ b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.dts
@@ -22,6 +22,7 @@
 		zephyr,flash = &flash0;
 		zephyr,code-partition = &slot0_partition;
 		zephyr,bt-hci = &bt_hci_silabs;
+		zephyr,display = &ls0xx_ls013b7dh03;
 	};
 
 	/* These aliases are provided for compatibility with samples */
@@ -31,6 +32,7 @@
 		sw0 = &button0;
 		sw1 = &button1;
 		watchdog0 = &wdog0;
+		dht0 = &si7021;
 	};
 
 	leds {
@@ -59,12 +61,24 @@
 		};
 	};
 
+	sensor_enable: sensor_enable {
+		compatible = "regulator-fixed";
+		regulator-name = "sensor_enable";
+		enable-gpios = <&gpiod 3 GPIO_ACTIVE_HIGH>;
+		status = "okay";
+	};
 };
 
 &cpu0 {
 	clock-frequency = <78000000>;
 };
 
+&itm {
+	pinctrl-0 = <&itm_default>;
+	pinctrl-names = "default";
+	swo-ref-frequency = <DT_FREQ_M(78)>;
+};
+
 &pstate_em3 {
 	status = "disabled";
 };
@@ -118,6 +132,53 @@
 	status = "okay";
 };
 
+&eusart1 {
+	compatible = "silabs,eusart-spi";
+	pinctrl-0 = <&eusart1_default>;
+	pinctrl-names = "default";
+	clock-frequency = <DT_FREQ_M(10)>;
+	cs-gpios = <&gpioc 8 GPIO_ACTIVE_HIGH>, <&gpioc 4 GPIO_ACTIVE_LOW>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	ls0xx_ls013b7dh03: ls0xx@0 {
+		compatible = "sharp,ls0xx";
+		spi-max-frequency = <DT_FREQ_K(1100)>;
+		reg = <0>;
+		width = <128>;
+		height = <128>;
+		extcomin-gpios = <&gpioc 6 GPIO_ACTIVE_HIGH>;
+		extcomin-frequency = <60>;
+		disp-en-gpios = <&gpioc 9 GPIO_ACTIVE_HIGH>;
+	};
+
+	mx25r80: mx25r8035f@1 {
+		compatible = "jedec,spi-nor";
+		reg = <1>;
+		spi-max-frequency = <DT_FREQ_M(33)>;
+		size = <DT_SIZE_M(8)>;
+		jedec-id = [c2 28 14];
+		has-dpd;
+		dpd-wakeup-sequence = <30000 20 35000>;
+		mxicy,mx25r-power-mode = "low-power";
+		zephyr,pm-device-runtime-auto;
+	};
+};
+
+&i2c0 {
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	si7021: si7021@40 {
+		compatible = "silabs,si7006";
+		reg = <0x40>;
+		vin-supply = <&sensor_enable>;
+		status = "okay";
+	};
+};
+
 &gpio {
 	location-swo = <0>;
 	status = "okay";
diff --git a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.yaml b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.yaml
index 014021b5548..d783e3919ec 100644
--- a/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.yaml
+++ b/boards/silabs/radio_boards/xg24_rb4187c/xg24_rb4187c.yaml
@@ -7,15 +7,16 @@ flash: 1536
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
+  - adc
   - bluetooth
   - gpio
   - uart
+  - spi
   - dma
   - watchdog
+  - comparator
 testing:
   ignore_tags:
     - pm
-    - hwinfo
 vendor: silabs
diff --git a/boards/silabs/radio_boards/xg29_rb4412a/Kconfig.defconfig b/boards/silabs/radio_boards/xg29_rb4412a/Kconfig.defconfig
new file mode 100644
index 00000000000..6004474fc86
--- /dev/null
+++ b/boards/silabs/radio_boards/xg29_rb4412a/Kconfig.defconfig
@@ -0,0 +1,31 @@
+# Copyright (c) 2025 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_XG29_RB4412A
+
+config LOG_BACKEND_SWO_FREQ_HZ
+	default 875000
+	depends on LOG_BACKEND_SWO
+
+if SOC_GECKO_USE_RAIL
+
+config FPU
+	default y
+
+endif # SOC_GECKO_USE_RAIL
+
+if BT
+
+config FPU
+	default y
+
+config COMMON_LIBC_MALLOC_ARENA_SIZE
+	default 8192
+
+config MAIN_STACK_SIZE
+	default 3072 if PM
+	default 2304
+
+endif # BT
+
+endif # BOARD_XG29_RB4412A
diff --git a/boards/silabs/radio_boards/xg29_rb4412a/Kconfig.xg29_rb4412a b/boards/silabs/radio_boards/xg29_rb4412a/Kconfig.xg29_rb4412a
new file mode 100644
index 00000000000..a7c877e51b6
--- /dev/null
+++ b/boards/silabs/radio_boards/xg29_rb4412a/Kconfig.xg29_rb4412a
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_XG29_RB4412A
+	select SOC_PART_NUMBER_EFR32MG29B140F1024IM40
diff --git a/boards/silabs/radio_boards/xg29_rb4412a/board.cmake b/boards/silabs/radio_boards/xg29_rb4412a/board.cmake
new file mode 100644
index 00000000000..f44b8f013fb
--- /dev/null
+++ b/boards/silabs/radio_boards/xg29_rb4412a/board.cmake
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=EFR32MG29BxxxF1024")
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+
+board_runner_args(silabs_commander "--device=EFR32MG29B140F1024IM40")
+include(${ZEPHYR_BASE}/boards/common/silabs_commander.board.cmake)
diff --git a/boards/silabs/radio_boards/xg29_rb4412a/board.yml b/boards/silabs/radio_boards/xg29_rb4412a/board.yml
new file mode 100644
index 00000000000..994b5891f0a
--- /dev/null
+++ b/boards/silabs/radio_boards/xg29_rb4412a/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: xg29_rb4412a
+  full_name: EFR32xG29 2.4 GHz 8 dBm Buck (xG29-RB4412A)
+  vendor: silabs
+  socs:
+    - name: efr32mg29b140f1024im40
diff --git a/boards/silabs/radio_boards/xg29_rb4412a/doc/index.rst b/boards/silabs/radio_boards/xg29_rb4412a/doc/index.rst
new file mode 100644
index 00000000000..707d79e15f2
--- /dev/null
+++ b/boards/silabs/radio_boards/xg29_rb4412a/doc/index.rst
@@ -0,0 +1,84 @@
+.. zephyr:board:: xg29_rb4412a
+
+Overview
+********
+
+The xG24-RB4412A radio board provides support for the Silicon Labs EFR32MG29 SoC.
+
+Hardware
+********
+
+- EFR32MG29B140F1024IM40 SoC
+- CPU core: ARM Cortex®-M33 with FPU
+- Flash memory: 1024 kB
+- RAM: 256 kB
+- Transmit power: up to +8 dBm
+- Operation frequency: 2.4 GHz
+- Crystal oscillators for LFXO (32.768 kHz) and HFXO (38.4 MHz)
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``xg29_rb4412a`` board target can be built, flashed, and debugged in the
+usual way. See :ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Flashing
+========
+
+As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world`
+application.
+
+To build and program the sample to the xG24-RB4412A, complete the following steps:
+
+First, plug the xG24-RB4412A to a compatible mainboard and connect the mainboard to your computer
+using the USB port on the left side.
+Next, build and flash the sample by running the following command:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: xg29_rb4412a
+   :goals: build flash
+
+``west flash`` will by default use SEGGER JLink. Make sure that the JLinkExe binary is available on
+the PATH. Alternatively, use ``west flash -r silabs_commander`` to use Simplicity Commander to flash.
+In this case, make sure that the commander binary is available on PATH.
+
+Open a serial terminal (minicom, putty, etc.) with the following settings:
+
+- Speed: 115200
+- Data: 8 bits
+- Parity: None
+- Stop bits: 1
+
+Reset the board and you should see the following message in the terminal:
+
+.. code-block:: console
+
+   Hello World! xg29_rb4412a
+
+Bluetooth
+=========
+
+To use the BLE function, run the command below to retrieve necessary binary
+blobs from the SiLabs HAL repository.
+
+.. code-block:: console
+
+   west blobs fetch hal_silabs
+
+Then build the Zephyr kernel and a Bluetooth sample with the following
+command. The :zephyr:code-sample:`bluetooth_observer` sample application is used in
+this example.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/bluetooth/observer
+   :board: xg29_rb4412a
+   :goals: build
diff --git a/boards/silabs/radio_boards/xg29_rb4412a/pre_dt_board.cmake b/boards/silabs/radio_boards/xg29_rb4412a/pre_dt_board.cmake
new file mode 100644
index 00000000000..66dcd771b3e
--- /dev/null
+++ b/boards/silabs/radio_boards/xg29_rb4412a/pre_dt_board.cmake
@@ -0,0 +1,5 @@
+# Copyright (c) 2021 Linaro Limited
+# SPDX-License-Identifier: Apache-2.0
+
+# SPI is implemented via usart/eusart so node name isn't spi@...
+list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge")
diff --git a/boards/silabs/radio_boards/xg29_rb4412a/xg29_rb4412a-pinctrl.dtsi b/boards/silabs/radio_boards/xg29_rb4412a/xg29_rb4412a-pinctrl.dtsi
new file mode 100644
index 00000000000..c53b1c2458f
--- /dev/null
+++ b/boards/silabs/radio_boards/xg29_rb4412a/xg29_rb4412a-pinctrl.dtsi
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/silabs/xg29-pinctrl.h>
+
+&pinctrl {
+	usart1_default: usart1_default {
+		group0 {
+			pins = <USART1_TX_PA5>;
+			drive-push-pull;
+			output-high;
+		};
+		group1 {
+			pins = <USART1_RX_PA6>;
+			input-enable;
+			silabs,input-filter;
+		};
+	};
+
+	eusart1_default: eusart1_default {
+		group0 {
+			pins = <EUSART1_TX_PC0>, <EUSART1_SCLK_PC2>;
+			drive-push-pull;
+			output-high;
+		};
+		group1 {
+			pins = <EUSART1_RX_PC1>;
+			input-enable;
+			silabs,input-filter;
+		};
+	};
+
+	i2c0_default: i2c0_default {
+		group0 {
+			pins = <I2C0_SCL_PB2>, <I2C0_SDA_PB3>;
+			drive-open-drain;
+			bias-pull-up;
+		};
+	};
+
+	itm_default: itm_default {
+		group0 {
+			pins = <GPIO_SWV_PA3>;
+			drive-push-pull;
+			output-high;
+		};
+	};
+};
diff --git a/boards/silabs/radio_boards/xg29_rb4412a/xg29_rb4412a.dts b/boards/silabs/radio_boards/xg29_rb4412a/xg29_rb4412a.dts
new file mode 100644
index 00000000000..e99ae541ff0
--- /dev/null
+++ b/boards/silabs/radio_boards/xg29_rb4412a/xg29_rb4412a.dts
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <silabs/xg29/efr32mg29b140f1024im40.dtsi>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/regulator/silabs_dcdc.h>
+#include "xg29_rb4412a-pinctrl.dtsi"
+
+/ {
+	model = "Silicon Labs xG29-RB4412A";
+	compatible = "silabs,xg29_rb4412a", "silabs,efr32mg29";
+
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+		zephyr,uart-pipe = &usart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,bt-hci = &bt_hci_silabs;
+		zephyr,display = &ls013b7dh03;
+	};
+
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		sw0 = &button0;
+		sw1 = &button1;
+		watchdog0 = &wdog0;
+		spi-flash0 = &mx25r80;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led_0 {
+			gpios = <&gpiob 0 GPIO_ACTIVE_LOW>;
+			label = "LED 0";
+		};
+
+		led1: led_1 {
+			gpios = <&gpiob 1 GPIO_ACTIVE_LOW>;
+			label = "LED 1";
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		button0: button_0 {
+			gpios = <&gpiob 0 GPIO_ACTIVE_LOW>;
+			label = "User Push Button 0";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		button1: button_1 {
+			gpios = <&gpiob 1 GPIO_ACTIVE_LOW>;
+			label = "User Push Button 1";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+
+	display_enable: sensor_enable: gpio_switch_0 {
+		compatible = "regulator-fixed";
+		regulator-name = "sensor_enable";
+		enable-gpios = <&gpioc 7 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&cpu0 {
+	clock-frequency = <76800000>;
+};
+
+&itm {
+	pinctrl-0 = <&itm_default>;
+	pinctrl-names = "default";
+	swo-ref-frequency = <DT_FREQ_K(76800)>;
+};
+
+&hfxo {
+	status = "okay";
+	ctune = <140>;
+	precision = <50>;
+};
+
+&lfxo {
+	status = "okay";
+	ctune = <63>;
+	precision = <50>;
+};
+
+&hfrcodpll {
+	clock-frequency = <DT_FREQ_K(76800)>;
+	clocks = <&hfxo>;
+	dpll-n = <3839>;
+	dpll-m = <1919>;
+	dpll-edge = "fall";
+	dpll-lock = "phase";
+	dpll-autorecover;
+};
+
+&em23grpaclk {
+	clocks = <&lfxo>;
+};
+
+&em4grpaclk {
+	clocks = <&lfxo>;
+};
+
+&rtccclk {
+	clocks = <&lfxo>;
+};
+
+&wdog0clk {
+	clocks = <&lfxo>;
+};
+
+&usart1 {
+	current-speed = <115200>;
+	pinctrl-0 = <&usart1_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c0 {
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	si7021: si7021@40 {
+		compatible = "silabs,si7006";
+		reg = <0x40>;
+		status = "okay";
+	};
+};
+
+&eusart1 {
+	pinctrl-0 = <&eusart1_default>;
+	pinctrl-names = "default";
+	clock-frequency = <DT_FREQ_M(8)>;
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>, <&gpioc 6 GPIO_ACTIVE_HIGH>;
+
+	mx25r80: mx25r8035f@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_M(33)>;
+		size = <0x800000>;
+		jedec-id = [c2 28 14];
+		has-dpd;
+		dpd-wakeup-sequence = <30000 20 35000>;
+		t-enter-dpd = <0>;
+		mxicy,mx25r-power-mode = "low-power";
+	};
+
+	ls013b7dh03: ls0xx@1 {
+		compatible = "sharp,ls0xx";
+		spi-max-frequency = <DT_FREQ_M(2)>;
+		reg = <1>;
+		width = <128>;
+		height = <128>;
+		extcomin-gpios = <&gpiod 2 GPIO_ACTIVE_HIGH>;
+		extcomin-frequency = <60>;
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpioa {
+	status = "okay";
+};
+
+&gpiob {
+	status = "okay";
+
+	vcom-enable {
+		gpio-hog;
+		gpios = <4 GPIO_ACTIVE_HIGH>;
+		output-high;
+	};
+};
+
+&gpioc {
+	status = "okay";
+};
+
+&gpiod {
+	status = "okay";
+};
+
+&wdog0 {
+	status = "okay";
+};
+
+&rtcc0 {
+	status = "okay";
+};
+
+&se {
+	status = "okay";
+};
+
+&dcdc {
+	status = "okay";
+	regulator-boot-on;
+	regulator-initial-mode = <SILABS_DCDC_MODE_BUCK>;
+};
+
+&radio {
+	pa-voltage-mv = <1800>;
+};
+
+&bt_hci_silabs {
+	status = "okay";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 DT_SIZE_K(48)>;
+		};
+
+		slot0_partition: partition@c000 {
+			label = "image-0";
+			reg = <0x0000C000 DT_SIZE_K(472)>;
+		};
+
+		slot1_partition: partition@82000 {
+			label = "image-1";
+			reg = <0x00082000 DT_SIZE_K(472)>;
+		};
+
+		storage_partition: partition@F8000 {
+			label = "storage";
+			reg = <0x000F8000 DT_SIZE_K(32)>;
+		};
+	};
+};
diff --git a/boards/silabs/radio_boards/xg29_rb4412a/xg29_rb4412a.yaml b/boards/silabs/radio_boards/xg29_rb4412a/xg29_rb4412a.yaml
new file mode 100644
index 00000000000..ea0a2e3936b
--- /dev/null
+++ b/boards/silabs/radio_boards/xg29_rb4412a/xg29_rb4412a.yaml
@@ -0,0 +1,21 @@
+identifier: xg29_rb4412a
+name: EFR32xG29 2.4 GHz 8 dBm Buck Radio Board (xG29-RB4412A, BRD4412A)
+type: mcu
+arch: arm
+ram: 256
+flash: 1024
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - adc
+  - bluetooth
+  - comparator
+  - dma
+  - entropy
+  - gpio
+  - flash
+  - spi
+  - uart
+  - watchdog
+vendor: silabs
diff --git a/boards/silabs/radio_boards/xg29_rb4412a/xg29_rb4412a_defconfig b/boards/silabs/radio_boards/xg29_rb4412a/xg29_rb4412a_defconfig
new file mode 100644
index 00000000000..e70f8f5c519
--- /dev/null
+++ b/boards/silabs/radio_boards/xg29_rb4412a/xg29_rb4412a_defconfig
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARM_MPU=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_GPIO=y
diff --git a/boards/silabs/starter_kits/efm32wg_stk3800/doc/index.rst b/boards/silabs/starter_kits/efm32wg_stk3800/doc/index.rst
index e8f4b9e432a..0856d97b6bc 100644
--- a/boards/silabs/starter_kits/efm32wg_stk3800/doc/index.rst
+++ b/boards/silabs/starter_kits/efm32wg_stk3800/doc/index.rst
@@ -30,29 +30,7 @@ For more information about the EFM32WG SoC and EFM32WG-STK3800 board:
 Supported Features
 ==================
 
-The efm32wg_stk3800 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/silabs/starter_kits/efm32wg_stk3800/efm32wg_stk3800_defconfig`
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -97,6 +75,8 @@ UART0 is connected to the board controller and is used for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 .. note::
    Before using the kit the first time, you should update the J-Link firmware
    in Simplicity Studio.
diff --git a/boards/silabs/starter_kits/efm32wg_stk3800/efm32wg_stk3800.yaml b/boards/silabs/starter_kits/efm32wg_stk3800/efm32wg_stk3800.yaml
index 46f0a60822a..2c55d747297 100644
--- a/boards/silabs/starter_kits/efm32wg_stk3800/efm32wg_stk3800.yaml
+++ b/boards/silabs/starter_kits/efm32wg_stk3800/efm32wg_stk3800.yaml
@@ -7,7 +7,6 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - nvs
diff --git a/boards/silabs/starter_kits/slstk3400a/Kconfig.defconfig b/boards/silabs/starter_kits/slstk3400a/Kconfig.defconfig
index 7c867fdd8e4..4839c7bf7cb 100644
--- a/boards/silabs/starter_kits/slstk3400a/Kconfig.defconfig
+++ b/boards/silabs/starter_kits/slstk3400a/Kconfig.defconfig
@@ -9,4 +9,15 @@ config CMU_HFXO_FREQ
 config CMU_LFXO_FREQ
 	default 32768
 
+# Kernel Options due to Low Memory (8k)
+
+configdefault MAIN_STACK_SIZE
+	default 640
+
+configdefault IDLE_STACK_SIZE
+	default 200
+
+configdefault ISR_STACK_SIZE
+	default 512
+
 endif # BOARD_SLSTK3400A
diff --git a/boards/silabs/starter_kits/slstk3400a/doc/index.rst b/boards/silabs/starter_kits/slstk3400a/doc/index.rst
index 91786515008..01693d34b74 100644
--- a/boards/silabs/starter_kits/slstk3400a/doc/index.rst
+++ b/boards/silabs/starter_kits/slstk3400a/doc/index.rst
@@ -33,27 +33,7 @@ See these documents for more information
 Supported Features
 ==================
 
-The efm32hg_slstk3400 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| USART     | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/silabs/starter_kits/slstk3400a/slstk3400a_defconfig`
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -98,6 +78,8 @@ USART1 is connected to the board controller and is used for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 .. note::
    Before using the kit the first time, you should update the J-Link firmware
    in Simplicity Studio.
diff --git a/boards/silabs/starter_kits/slstk3400a/slstk3400a.yaml b/boards/silabs/starter_kits/slstk3400a/slstk3400a.yaml
index e3bb4628be0..28438025a42 100644
--- a/boards/silabs/starter_kits/slstk3400a/slstk3400a.yaml
+++ b/boards/silabs/starter_kits/slstk3400a/slstk3400a.yaml
@@ -7,7 +7,6 @@ flash: 64
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - nvs
diff --git a/boards/silabs/starter_kits/slstk3400a/slstk3400a_defconfig b/boards/silabs/starter_kits/slstk3400a/slstk3400a_defconfig
index 957fedcc584..48429f2f899 100644
--- a/boards/silabs/starter_kits/slstk3400a/slstk3400a_defconfig
+++ b/boards/silabs/starter_kits/slstk3400a/slstk3400a_defconfig
@@ -6,8 +6,3 @@ CONFIG_SERIAL=y
 CONFIG_GPIO=y
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=24000000
 CONFIG_CMU_HFCLK_HFXO=y
-
-# Kernel Options due to Low Memory (8k)
-CONFIG_MAIN_STACK_SIZE=640
-CONFIG_IDLE_STACK_SIZE=200
-CONFIG_ISR_STACK_SIZE=512
diff --git a/boards/silabs/starter_kits/slstk3401a/doc/index.rst b/boards/silabs/starter_kits/slstk3401a/doc/index.rst
index 8e5fa5fb1ee..e3805b2b197 100644
--- a/boards/silabs/starter_kits/slstk3401a/doc/index.rst
+++ b/boards/silabs/starter_kits/slstk3401a/doc/index.rst
@@ -28,35 +28,7 @@ For more information about the EFM32PG SoC and SLSTK3401A board:
 Supported Features
 ==================
 
-The slstk3401a board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtcc                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c port-polling                    |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/silabs/starter_kits/slstk3401a/slstk3401a_defconfig`
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -109,6 +81,8 @@ The EFM32PG SoC has two USARTs and one Low Energy UART (LEUART).
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 .. note::
    Before using the kit the first time, you should update the J-Link firmware
    in Simplicity Studio.
diff --git a/boards/silabs/starter_kits/slstk3401a/slstk3401a.yaml b/boards/silabs/starter_kits/slstk3401a/slstk3401a.yaml
index a7de8915c22..6de92764e91 100644
--- a/boards/silabs/starter_kits/slstk3401a/slstk3401a.yaml
+++ b/boards/silabs/starter_kits/slstk3401a/slstk3401a.yaml
@@ -7,7 +7,6 @@ flash: 256
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - i2c
   - gpio
diff --git a/boards/silabs/starter_kits/slstk3402a/doc/index.rst b/boards/silabs/starter_kits/slstk3402a/doc/index.rst
index 3470e9e6701..30bea70c4f6 100644
--- a/boards/silabs/starter_kits/slstk3402a/doc/index.rst
+++ b/boards/silabs/starter_kits/slstk3402a/doc/index.rst
@@ -29,41 +29,7 @@ For more information about the EFM32PG SoC and SLSTK3402A board:
 Supported Features
 ==================
 
-The slstk3402a board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtcc                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c port-polling                    |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | true random number generator        |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32pg12b500f1024gl125_defconfig`
-
-The default configuration when building using this board to develop for the
-EFM32JG12 SoC can be found in
-:zephyr_file:`boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32jg12b500f1024gl125_defconfig`
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 EFM32 Jade Gecko SoC
 --------------------
@@ -132,6 +98,8 @@ The EFM32PG12 SoC has four USARTs and one Low Energy UART (LEUART).
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 .. note::
    Before using the kit the first time, you should update the J-Link firmware
    in Simplicity Studio.
diff --git a/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32jg12b500f1024gl125.yaml b/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32jg12b500f1024gl125.yaml
index 552699ed84a..5230f2a6a82 100644
--- a/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32jg12b500f1024gl125.yaml
+++ b/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32jg12b500f1024gl125.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - i2c
   - gpio
diff --git a/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32pg12b500f1024gl125.yaml b/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32pg12b500f1024gl125.yaml
index 8274823adfa..60aee6d99e1 100644
--- a/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32pg12b500f1024gl125.yaml
+++ b/boards/silabs/starter_kits/slstk3402a/slstk3402a_efm32pg12b500f1024gl125.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - i2c
   - gpio
diff --git a/boards/silabs/starter_kits/slstk3701a/doc/index.rst b/boards/silabs/starter_kits/slstk3701a/doc/index.rst
index d63c3f3844b..ca3d2feb8dc 100644
--- a/boards/silabs/starter_kits/slstk3701a/doc/index.rst
+++ b/boards/silabs/starter_kits/slstk3701a/doc/index.rst
@@ -34,36 +34,7 @@ For more information about the EFM32GG11 SoC and SLSTK3701A board:
 Supported Features
 ==================
 
-The slstk3701a board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | memory protection unit              |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtcc                                |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c port-polling                    |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/silabs/starter_kits/slstk3701a/slstk3701a_defconfig`
-
-Other hardware features are currently not supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -121,6 +92,8 @@ USART4 is connected to the board controller and is used for the console.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 .. note::
    Before using the kit the first time, you should update the J-Link firmware
    in Simplicity Studio.
diff --git a/boards/silabs/starter_kits/slstk3701a/slstk3701a.dts b/boards/silabs/starter_kits/slstk3701a/slstk3701a.dts
index 331a2163718..64a656bb723 100644
--- a/boards/silabs/starter_kits/slstk3701a/slstk3701a.dts
+++ b/boards/silabs/starter_kits/slstk3701a/slstk3701a.dts
@@ -156,19 +156,19 @@
 
 	/* PHY management pins */
 	location-mdio        = <GECKO_LOCATION(1)>;
-	location-phy_mdc     = <GECKO_LOCATION(1) GECKO_PORT_D GECKO_PIN(14)>;
-	location-phy_mdio    = <GECKO_LOCATION(1) GECKO_PORT_D GECKO_PIN(13)>;
+	location-phy-mdc     = <GECKO_LOCATION(1) GECKO_PORT_D GECKO_PIN(14)>;
+	location-phy-mdio    = <GECKO_LOCATION(1) GECKO_PORT_D GECKO_PIN(13)>;
 
 	/* RMII interface pins */
 	location-rmii        = <GECKO_LOCATION(1)>;
-	location-rmii_refclk = <GECKO_LOCATION(5) GECKO_PORT_D GECKO_PIN(10)>;
-	location-rmii_crs_dv = <GECKO_LOCATION(1) GECKO_PORT_D GECKO_PIN(11)>;
-	location-rmii_txd0   = <GECKO_LOCATION(1) GECKO_PORT_F GECKO_PIN(7)>;
-	location-rmii_txd1   = <GECKO_LOCATION(1) GECKO_PORT_F GECKO_PIN(6)>;
-	location-rmii_tx_en  = <GECKO_LOCATION(1) GECKO_PORT_F GECKO_PIN(8)>;
-	location-rmii_rxd0   = <GECKO_LOCATION(1) GECKO_PORT_D GECKO_PIN(9)>;
-	location-rmii_rxd1   = <GECKO_LOCATION(1) GECKO_PORT_F GECKO_PIN(9)>;
-	location-rmii_rx_er  = <GECKO_LOCATION(1) GECKO_PORT_D GECKO_PIN(12)>;
+	location-rmii-refclk = <GECKO_LOCATION(5) GECKO_PORT_D GECKO_PIN(10)>;
+	location-rmii-crs-dv = <GECKO_LOCATION(1) GECKO_PORT_D GECKO_PIN(11)>;
+	location-rmii-txd0   = <GECKO_LOCATION(1) GECKO_PORT_F GECKO_PIN(7)>;
+	location-rmii-txd1   = <GECKO_LOCATION(1) GECKO_PORT_F GECKO_PIN(6)>;
+	location-rmii-tx-en  = <GECKO_LOCATION(1) GECKO_PORT_F GECKO_PIN(8)>;
+	location-rmii-rxd0   = <GECKO_LOCATION(1) GECKO_PORT_D GECKO_PIN(9)>;
+	location-rmii-rxd1   = <GECKO_LOCATION(1) GECKO_PORT_F GECKO_PIN(9)>;
+	location-rmii-rx-er  = <GECKO_LOCATION(1) GECKO_PORT_D GECKO_PIN(12)>;
 
 	status = "okay";
 };
diff --git a/boards/silabs/starter_kits/slstk3701a/slstk3701a.yaml b/boards/silabs/starter_kits/slstk3701a/slstk3701a.yaml
index 2c9a0d812cd..9ee9e8746ad 100644
--- a/boards/silabs/starter_kits/slstk3701a/slstk3701a.yaml
+++ b/boards/silabs/starter_kits/slstk3701a/slstk3701a.yaml
@@ -7,7 +7,6 @@ flash: 2048
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - i2c
   - gpio
diff --git a/boards/sipeed/longan_nano/doc/index.rst b/boards/sipeed/longan_nano/doc/index.rst
index 49a52c00d65..9acb207cc84 100644
--- a/boards/sipeed/longan_nano/doc/index.rst
+++ b/boards/sipeed/longan_nano/doc/index.rst
@@ -35,41 +35,7 @@ Hardware
 Supported Features
 ==================
 
-The board configuration supports the following hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`gd,gd32-gpio`
-   * - Machine timer
-     - :kconfig:option:`CONFIG_RISCV_MACHINE_TIMER`
-     - :dtcompatible:`riscv,machine-timer`
-   * - Nuclei ECLIC Interrupt Controller
-     - :kconfig:option:`CONFIG_NUCLEI_ECLIC`
-     - :dtcompatible:`nuclei,eclic`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM`
-     - :dtcompatible:`gd,gd32-pwm`
-   * - USART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`gd,gd32-usart`
-   * - I2C
-     - :kconfig:option:`CONFIG_I2C`
-     - :dtcompatible:`gd,gd32-i2c`
-   * - DAC
-     - :kconfig:option:`CONFIG_DAC`
-     - :dtcompatible:`gd,gd32-dac`
-   * - ADC
-     - :kconfig:option:`CONFIG_ADC`
-     - :dtcompatible:`gd,gd32-adc`
-   * - SPI
-     - :kconfig:option:`CONFIG_SPI`
-     - :dtcompatible:`gd,gd32-spi`
+.. zephyr:board-supported-hw::
 
 The microSD card reader in Longan Nano board is connected to SPI1.
 
@@ -82,6 +48,8 @@ Connect to TX0 (PA9) and RX0 (PA10).
 Programming and debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Building & Flashing
 ===================
 
diff --git a/boards/sipeed/longan_nano/longan_nano.yaml b/boards/sipeed/longan_nano/longan_nano.yaml
index aebc7291fb8..2289d7ad3b4 100644
--- a/boards/sipeed/longan_nano/longan_nano.yaml
+++ b/boards/sipeed/longan_nano/longan_nano.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: riscv
 toolchain:
   - zephyr
-  - xtools
 flash: 128
 ram: 32
 supported:
diff --git a/boards/sipeed/longan_nano/longan_nano_gd32vf103_lite.yaml b/boards/sipeed/longan_nano/longan_nano_gd32vf103_lite.yaml
index 27636b6d47e..f12b0970902 100644
--- a/boards/sipeed/longan_nano/longan_nano_gd32vf103_lite.yaml
+++ b/boards/sipeed/longan_nano/longan_nano_gd32vf103_lite.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: riscv
 toolchain:
   - zephyr
-  - xtools
 flash: 64
 ram: 20
 supported:
diff --git a/boards/snps/em_starterkit/doc/index.rst b/boards/snps/em_starterkit/doc/index.rst
index 9fc53692b66..cbb669a5736 100644
--- a/boards/snps/em_starterkit/doc/index.rst
+++ b/boards/snps/em_starterkit/doc/index.rst
@@ -108,6 +108,8 @@ copy the initialized data section to the data memory if CONFIG_XIP is used.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Required Hardware and Software
 ==============================
 
diff --git a/boards/snps/em_starterkit/em_starterkit_emsk_em11d.yaml b/boards/snps/em_starterkit/em_starterkit_emsk_em11d.yaml
index 3189656c78f..65ec248abf2 100644
--- a/boards/snps/em_starterkit/em_starterkit_emsk_em11d.yaml
+++ b/boards/snps/em_starterkit/em_starterkit_emsk_em11d.yaml
@@ -5,7 +5,6 @@ arch: arc
 toolchain:
   - zephyr
   - cross-compile
-  - xtools
 supported:
   - i2c
   - spi
diff --git a/boards/snps/em_starterkit/em_starterkit_emsk_em7d.yaml b/boards/snps/em_starterkit/em_starterkit_emsk_em7d.yaml
index fe2276e2d73..9a37326ce9b 100644
--- a/boards/snps/em_starterkit/em_starterkit_emsk_em7d.yaml
+++ b/boards/snps/em_starterkit/em_starterkit_emsk_em7d.yaml
@@ -5,7 +5,6 @@ arch: arc
 toolchain:
   - zephyr
   - cross-compile
-  - xtools
 supported:
   - i2c
   - spi
diff --git a/boards/snps/em_starterkit/em_starterkit_emsk_em7d_2_2.yaml b/boards/snps/em_starterkit/em_starterkit_emsk_em7d_2_2.yaml
index 29f4404ca95..9baa05d0cf9 100644
--- a/boards/snps/em_starterkit/em_starterkit_emsk_em7d_2_2.yaml
+++ b/boards/snps/em_starterkit/em_starterkit_emsk_em7d_2_2.yaml
@@ -5,7 +5,6 @@ arch: arc
 toolchain:
   - zephyr
   - cross-compile
-  - xtools
 supported:
   - i2c
   - spi
diff --git a/boards/snps/em_starterkit/em_starterkit_emsk_em9d.yaml b/boards/snps/em_starterkit/em_starterkit_emsk_em9d.yaml
index 34b10ca6d7b..e60017820fd 100644
--- a/boards/snps/em_starterkit/em_starterkit_emsk_em9d.yaml
+++ b/boards/snps/em_starterkit/em_starterkit_emsk_em9d.yaml
@@ -5,7 +5,6 @@ arch: arc
 toolchain:
   - zephyr
   - cross-compile
-  - xtools
 supported:
   - i2c
   - spi
diff --git a/boards/snps/em_starterkit/em_starterkit_r23.dtsi b/boards/snps/em_starterkit/em_starterkit_r23.dtsi
index ef93abcfd46..16236f315b7 100644
--- a/boards/snps/em_starterkit/em_starterkit_r23.dtsi
+++ b/boards/snps/em_starterkit/em_starterkit_r23.dtsi
@@ -34,9 +34,9 @@
 			compatible = "snps,creg-gpio";
 			reg = <0xf0000014 0x4>;
 			ngpios = <6>;
-			bit_per_gpio = <1>;
-			off_val = <0>;
-			on_val = <1>;
+			bit-per-gpio = <1>;
+			off-val = <0>;
+			on-val = <1>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
diff --git a/boards/snps/emsdp/doc/index.rst b/boards/snps/emsdp/doc/index.rst
index f300d3723ce..d880a6ad6da 100644
--- a/boards/snps/emsdp/doc/index.rst
+++ b/boards/snps/emsdp/doc/index.rst
@@ -117,6 +117,8 @@ multiplexer ARDUINO_MUX_CTRL is in the default mode (GPIO).
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Required Hardware and Software
 ==============================
 
diff --git a/boards/snps/emsdp/emsdp_emsdp_em11d.yaml b/boards/snps/emsdp/emsdp_emsdp_em11d.yaml
index b9c1868a133..1f30455891d 100644
--- a/boards/snps/emsdp/emsdp_emsdp_em11d.yaml
+++ b/boards/snps/emsdp/emsdp_emsdp_em11d.yaml
@@ -5,7 +5,6 @@ arch: arc
 toolchain:
   - zephyr
   - cross-compile
-  - xtools
 ram: 128
 supported:
   - spi
diff --git a/boards/snps/emsdp/emsdp_emsdp_em4.yaml b/boards/snps/emsdp/emsdp_emsdp_em4.yaml
index 96f05b3251f..12549b40176 100644
--- a/boards/snps/emsdp/emsdp_emsdp_em4.yaml
+++ b/boards/snps/emsdp/emsdp_emsdp_em4.yaml
@@ -5,7 +5,6 @@ arch: arc
 toolchain:
   - zephyr
   - cross-compile
-  - xtools
 ram: 128
 testing:
   ignore_tags:
diff --git a/boards/snps/emsdp/emsdp_emsdp_em5d.yaml b/boards/snps/emsdp/emsdp_emsdp_em5d.yaml
index 91f3c1d1c4e..dfc2b087793 100644
--- a/boards/snps/emsdp/emsdp_emsdp_em5d.yaml
+++ b/boards/snps/emsdp/emsdp_emsdp_em5d.yaml
@@ -5,7 +5,6 @@ arch: arc
 toolchain:
   - zephyr
   - cross-compile
-  - xtools
 ram: 128
 testing:
   ignore_tags:
diff --git a/boards/snps/emsdp/emsdp_emsdp_em6.yaml b/boards/snps/emsdp/emsdp_emsdp_em6.yaml
index 0c74c5b7c21..643d08876a1 100644
--- a/boards/snps/emsdp/emsdp_emsdp_em6.yaml
+++ b/boards/snps/emsdp/emsdp_emsdp_em6.yaml
@@ -5,7 +5,6 @@ arch: arc
 toolchain:
   - zephyr
   - cross-compile
-  - xtools
 ram: 128
 supported:
   - spi
diff --git a/boards/snps/emsdp/emsdp_emsdp_em7d.yaml b/boards/snps/emsdp/emsdp_emsdp_em7d.yaml
index 94dfbdd2af0..6ec11b101c2 100644
--- a/boards/snps/emsdp/emsdp_emsdp_em7d.yaml
+++ b/boards/snps/emsdp/emsdp_emsdp_em7d.yaml
@@ -5,7 +5,6 @@ arch: arc
 toolchain:
   - zephyr
   - cross-compile
-  - xtools
 ram: 128
 testing:
   ignore_tags:
diff --git a/boards/snps/emsdp/emsdp_emsdp_em7d_esp.yaml b/boards/snps/emsdp/emsdp_emsdp_em7d_esp.yaml
index fcbc5e24c74..f0126cc2b4c 100644
--- a/boards/snps/emsdp/emsdp_emsdp_em7d_esp.yaml
+++ b/boards/snps/emsdp/emsdp_emsdp_em7d_esp.yaml
@@ -5,7 +5,6 @@ arch: arc
 toolchain:
   - zephyr
   - cross-compile
-  - xtools
 ram: 128
 supported:
   - spi
diff --git a/boards/snps/emsdp/emsdp_emsdp_em9d.yaml b/boards/snps/emsdp/emsdp_emsdp_em9d.yaml
index e22e8d37092..8a7e40aa827 100644
--- a/boards/snps/emsdp/emsdp_emsdp_em9d.yaml
+++ b/boards/snps/emsdp/emsdp_emsdp_em9d.yaml
@@ -5,7 +5,6 @@ arch: arc
 toolchain:
   - zephyr
   - cross-compile
-  - xtools
 ram: 128
 supported:
   - spi
diff --git a/boards/snps/hsdk/doc/index.rst b/boards/snps/hsdk/doc/index.rst
index f7d82a9866f..9e5dee7556c 100644
--- a/boards/snps/hsdk/doc/index.rst
+++ b/boards/snps/hsdk/doc/index.rst
@@ -343,6 +343,8 @@ For hardware feature details, refer to : `Designware HS Development Kit website
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Required Hardware and Software
 ==============================
 
diff --git a/boards/snps/hsdk/hsdk.yaml b/boards/snps/hsdk/hsdk.yaml
index 3547f1a313b..7a63a47ee67 100644
--- a/boards/snps/hsdk/hsdk.yaml
+++ b/boards/snps/hsdk/hsdk.yaml
@@ -5,7 +5,6 @@ arch: arc
 toolchain:
   - zephyr
   - cross-compile
-  - xtools
   - arcmwdt
 supported:
   - smp
diff --git a/boards/snps/hsdk/hsdk_arc_hsdk_2cores.yaml b/boards/snps/hsdk/hsdk_arc_hsdk_2cores.yaml
index 24c50b0b918..b4bd8f19f5d 100644
--- a/boards/snps/hsdk/hsdk_arc_hsdk_2cores.yaml
+++ b/boards/snps/hsdk/hsdk_arc_hsdk_2cores.yaml
@@ -5,7 +5,6 @@ arch: arc
 toolchain:
   - zephyr
   - cross-compile
-  - xtools
   - arcmwdt
 supported:
   - smp
diff --git a/boards/snps/hsdk4xd/doc/index.rst b/boards/snps/hsdk4xd/doc/index.rst
index 0808b76ca6d..52e88da142a 100644
--- a/boards/snps/hsdk4xd/doc/index.rst
+++ b/boards/snps/hsdk4xd/doc/index.rst
@@ -340,6 +340,8 @@ For hardware feature details, refer to : `Designware HS4x/HS4xD Development Kit
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Required Hardware and Software
 ==============================
 
diff --git a/boards/snps/hsdk4xd/hsdk4xd.yaml b/boards/snps/hsdk4xd/hsdk4xd.yaml
index 798d7be5f2b..8cc50a8db6b 100644
--- a/boards/snps/hsdk4xd/hsdk4xd.yaml
+++ b/boards/snps/hsdk4xd/hsdk4xd.yaml
@@ -5,7 +5,6 @@ arch: arc
 toolchain:
   - zephyr
   - cross-compile
-  - xtools
   - arcmwdt
 supported:
   - smp
diff --git a/boards/snps/iotdk/doc/index.rst b/boards/snps/iotdk/doc/index.rst
index 8176f51618d..d038451dd05 100644
--- a/boards/snps/iotdk/doc/index.rst
+++ b/boards/snps/iotdk/doc/index.rst
@@ -25,6 +25,8 @@ For hardware feature details, refer to : `ARC IoT Development Kit
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Required Hardware and Software
 ==============================
 
diff --git a/boards/snps/iotdk/iotdk.yaml b/boards/snps/iotdk/iotdk.yaml
index 5ec9fdc8d15..9de77e5c1a7 100644
--- a/boards/snps/iotdk/iotdk.yaml
+++ b/boards/snps/iotdk/iotdk.yaml
@@ -5,7 +5,6 @@ arch: arc
 toolchain:
   - zephyr
   - cross-compile
-  - xtools
 ram: 128
 testing:
   ignore_tags:
diff --git a/boards/snps/nsim/arc_classic/doc/index.rst b/boards/snps/nsim/arc_classic/doc/index.rst
index c3839dfc893..b6111d234a3 100644
--- a/boards/snps/nsim/arc_classic/doc/index.rst
+++ b/boards/snps/nsim/arc_classic/doc/index.rst
@@ -68,6 +68,8 @@ I.e. for the multi-core ``nsim/nsim_hs5x/smp`` platform there is only
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Required Hardware and Software
 ==============================
 
diff --git a/boards/snps/nsim/arc_v/doc/index.rst b/boards/snps/nsim/arc_v/doc/index.rst
index a0bc41c2be7..4d6bf6427f6 100644
--- a/boards/snps/nsim/arc_v/doc/index.rst
+++ b/boards/snps/nsim/arc_v/doc/index.rst
@@ -27,6 +27,8 @@ which options are configured and so will be used on invocation of the simulator.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Required Hardware and Software
 ==============================
 
diff --git a/boards/snps/nsim/arc_v/rmx1xx.dtsi b/boards/snps/nsim/arc_v/rmx1xx.dtsi
index 9480922e217..5cd969114a7 100644
--- a/boards/snps/nsim/arc_v/rmx1xx.dtsi
+++ b/boards/snps/nsim/arc_v/rmx1xx.dtsi
@@ -37,6 +37,13 @@
 				interrupt-names = "soft0", "timer0";
 			};
 
+			mtimer: timer@200bff8 {
+				compatible = "riscv,machine-timer";
+				interrupts-extended = <&cpu0_intc 7>;
+				reg = <0x200bff8 0x8 0x2004000 0x8>;
+				reg-names = "mtime", "mtimecmp";
+			};
+
 			uart0: serial@10000000{
 				compatible = "ns16550", "snps,dw-apb-uart";
 				reg = <0x10000000 0x400>;
diff --git a/boards/sparkfun/micromod/micromod_nrf52840.yaml b/boards/sparkfun/micromod/micromod_nrf52840.yaml
index 520d9607d5e..d1cc5c241b5 100644
--- a/boards/sparkfun/micromod/micromod_nrf52840.yaml
+++ b/boards/sparkfun/micromod/micromod_nrf52840.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - ble
   - gpio
diff --git a/boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun.yaml b/boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun.yaml
index a377d060073..76b50d5879a 100644
--- a/boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun.yaml
+++ b/boards/sparkfun/nrf52_sparkfun/nrf52_sparkfun.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 512
 vendor: sparkfun
diff --git a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.yaml b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.yaml
index a2a8932d78f..d7e2587d89d 100644
--- a/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.yaml
+++ b/boards/sparkfun/pro_micro_rp2040/sparkfun_pro_micro_rp2040.yaml
@@ -7,7 +7,6 @@ ram: 264
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - uart
   - gpio
diff --git a/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160.yaml b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160.yaml
index f9d59872c14..07bf5bd58c1 100644
--- a/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160.yaml
+++ b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 64
 flash: 256
diff --git a/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns.yaml b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns.yaml
index 6fbb1dfb13a..2ea6bea8e7b 100644
--- a/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns.yaml
+++ b/boards/sparkfun/thing_plus/sparkfun_thing_plus_nrf9160_ns.yaml
@@ -4,7 +4,6 @@ type: mcu
 arch: arm
 toolchain:
   - gnuarmemb
-  - xtools
   - zephyr
 ram: 128
 flash: 192
diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts
index 05db65eb187..e24f97961a5 100644
--- a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts
+++ b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.dts
@@ -73,7 +73,7 @@
 };
 
 &eusart1 {
-	compatible = "silabs,gecko-spi-eusart";
+	compatible = "silabs,eusart-spi";
 
 	#address-cells = <1>;
 	#size-cells = <0>;
diff --git a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.yaml b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.yaml
index 392fbb38fb9..928cf3ac060 100644
--- a/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.yaml
+++ b/boards/sparkfun/thing_plus_matter_mgm240p/sparkfun_thing_plus_matter_mgm240p.yaml
@@ -7,7 +7,6 @@ flash: 1536
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - gpio
diff --git a/boards/st/b_g474e_dpow1/b_g474e_dpow1.yaml b/boards/st/b_g474e_dpow1/b_g474e_dpow1.yaml
index ff6b032e815..d014e0a9ed7 100644
--- a/boards/st/b_g474e_dpow1/b_g474e_dpow1.yaml
+++ b/boards/st/b_g474e_dpow1/b_g474e_dpow1.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 512
 supported:
diff --git a/boards/st/b_g474e_dpow1/doc/index.rst b/boards/st/b_g474e_dpow1/doc/index.rst
index b130b728663..8d377e784c5 100644
--- a/boards/st/b_g474e_dpow1/doc/index.rst
+++ b/boards/st/b_g474e_dpow1/doc/index.rst
@@ -43,29 +43,7 @@ More information about STM32G474RE can be found here:
 Supported Features
 ==================
 
-The Zephyr b_g474e_dpow1 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb                                 |
-+-----------+------------+-------------------------------------+
-| UCPD      | on-chip    | ucpd                                |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/b_g474e_dpow1/b_g474e_dpow1_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -98,6 +76,8 @@ For more details please refer to `B-G474E-DPOW1 Discovery board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The B-G474E-DPOW1 Discovery board includes an ST-LINK/V3E embedded debug tool interface.
 
 Applications for the ``b_g474e_dpow1`` board configuration can be built and
diff --git a/boards/st/b_l072z_lrwan1/b_l072z_lrwan1.yaml b/boards/st/b_l072z_lrwan1/b_l072z_lrwan1.yaml
index eef460836cb..e94ba64e891 100644
--- a/boards/st/b_l072z_lrwan1/b_l072z_lrwan1.yaml
+++ b/boards/st/b_l072z_lrwan1/b_l072z_lrwan1.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 20
 flash: 192
 testing:
diff --git a/boards/st/b_l072z_lrwan1/doc/index.rst b/boards/st/b_l072z_lrwan1/doc/index.rst
index 06385429700..4f2caa6d828 100644
--- a/boards/st/b_l072z_lrwan1/doc/index.rst
+++ b/boards/st/b_l072z_lrwan1/doc/index.rst
@@ -108,40 +108,7 @@ More information about STM32L072CZ can be found here:
 Supported Features
 ==================
 
-The Zephyr B-L072Z-LRWAN1 Discovery board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| TRNG      | on-chip    | true random number generator        |
-+-----------+------------+-------------------------------------+
-| EEPROM    | on-chip    | eeprom                              |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb                                 |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
-| LoRa      | on-module  | sx1276                              |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/b_l072z_lrwan1/b_l072z_lrwan1_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -184,6 +151,8 @@ the USB data lines to the MCU, short solder bridges SB15 and SB16.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 B-L072Z-LRWAN1 Discovery board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``b_l072z_lrwan1`` board configuration can be built and
diff --git a/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts
index d7f5adab5be..da6bcc44c6a 100644
--- a/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts
+++ b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.dts
@@ -239,7 +239,7 @@ zephyr_udc0: &usbotg_fs {
 		     &octospim_p1_io2_pe14 &octospim_p1_io3_pe15>;
 	pinctrl-names = "default";
 
-	dmas = <&dma1 0 40 0x480>; /* request 40 for OCTOSPI1 */
+	dmas = <&dma1 0 40 STM32_DMA_PERIPH_RX>; /* request 40 for OCTOSPI1 */
 	dma-names = "tx_rx";
 
 	status = "okay";
diff --git a/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.yaml b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.yaml
index d0928a8aa1d..daaa2bd2f40 100644
--- a/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.yaml
+++ b/boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 192
 flash: 2048
 supported:
diff --git a/boards/st/b_l4s5i_iot01a/doc/index.rst b/boards/st/b_l4s5i_iot01a/doc/index.rst
index 83a6dcd1e8a..82cfef30935 100644
--- a/boards/st/b_l4s5i_iot01a/doc/index.rst
+++ b/boards/st/b_l4s5i_iot01a/doc/index.rst
@@ -99,37 +99,7 @@ More information about STM32L4S5VI can be found here:
 Supported Features
 ==================
 
-The Zephyr b_l4s5i_iot01a board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| BLE       | module     | bluetooth                           |
-+-----------+------------+-------------------------------------+
-| WIFI      | module     | es-wifi                             |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-
-	:zephyr_file:`boards/st/b_l4s5i_iot01a/b_l4s5i_iot01a_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -170,6 +140,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 B_L4S5I_IOT01A Discovery kit includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Flashing
diff --git a/boards/st/b_u585i_iot02a/b_u585i_iot02a.yaml b/boards/st/b_u585i_iot02a/b_u585i_iot02a.yaml
index 48f1064731c..621e4557204 100644
--- a/boards/st/b_u585i_iot02a/b_u585i_iot02a.yaml
+++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 786
 flash: 2048
 supported:
diff --git a/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns.yaml b/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns.yaml
index 662c6f18848..f3b9d44684c 100644
--- a/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns.yaml
+++ b/boards/st/b_u585i_iot02a/b_u585i_iot02a_stm32u585xx_ns.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 786
 flash: 512
 vendor: st
diff --git a/boards/st/b_u585i_iot02a/doc/index.rst b/boards/st/b_u585i_iot02a/doc/index.rst
index c9d9378444a..7f1e812c89c 100644
--- a/boards/st/b_u585i_iot02a/doc/index.rst
+++ b/boards/st/b_u585i_iot02a/doc/index.rst
@@ -153,48 +153,7 @@ More information about STM32U585AI can be found here:
 Supported Features
 ==================
 
-The Zephyr b_u585i_iot02a board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | dac                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb_device                          |
-+-----------+------------+-------------------------------------+
-| BKP SRAM  | on-chip    | Backup SRAM                         |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-| AES       | on-chip    | crypto                              |
-+-----------+------------+-------------------------------------+
-| RADIO     | STM32WB5MMG| Bluetooth Low Energy (BLE)          |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/b_u585i_iot02a/b_u585i_iot02a_defconfig`
+.. zephyr:board-supported-hw::
 
 Zephyr board options
 ====================
@@ -283,6 +242,8 @@ do it by removing ``SB6`` jumper on the back side of the board.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 B_U585I_IOT02A Discovery kit includes an ST-LINK/V3 embedded debug tool interface.
 This probe allows to flash the board using various tools.
 
diff --git a/boards/st/b_u585i_iot02a/pre_dt_board.cmake b/boards/st/b_u585i_iot02a/pre_dt_board.cmake
deleted file mode 100644
index 812d18cdf6c..00000000000
--- a/boards/st/b_u585i_iot02a/pre_dt_board.cmake
+++ /dev/null
@@ -1,3 +0,0 @@
-
-# SPI is implemented via octospi so node name isn't spi@...
-list(APPEND EXTRA_DTC_FLAGS "-Wno-spi_bus_bridge")
diff --git a/boards/st/common/scripts/board_power_reset.sh b/boards/st/common/scripts/board_power_reset.sh
new file mode 100755
index 00000000000..47227f7de05
--- /dev/null
+++ b/boards/st/common/scripts/board_power_reset.sh
@@ -0,0 +1,9 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2025 STMicroelectronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+STM32_Programmer_CLI -c port=swd mode=UR --power off index=0 --power on index=0 > /dev/null
+
+sleep 1
diff --git a/boards/st/disco_l475_iot1/arduino_r3_connector.dtsi b/boards/st/disco_l475_iot1/arduino_r3_connector.dtsi
index b48af67e2a1..05228c5ccb8 100644
--- a/boards/st/disco_l475_iot1/arduino_r3_connector.dtsi
+++ b/boards/st/disco_l475_iot1/arduino_r3_connector.dtsi
@@ -35,6 +35,6 @@
 	};
 };
 
-arduino_i2c: &i2c3 {};
+arduino_i2c: &i2c1 {};
 arduino_spi: &spi1 {};
 arduino_serial: &uart4 {};
diff --git a/boards/st/disco_l475_iot1/disco_l475_iot1.dts b/boards/st/disco_l475_iot1/disco_l475_iot1.dts
index 6ffb6950124..166d24c3ee5 100644
--- a/boards/st/disco_l475_iot1/disco_l475_iot1.dts
+++ b/boards/st/disco_l475_iot1/disco_l475_iot1.dts
@@ -228,9 +228,9 @@
 			read-only;
 		};
 
-		slot0_partition: partition@1000 {
+		slot0_partition: partition@10000 {
 			label = "image-0";
-			reg = <0x1000 DT_SIZE_K(928)>;
+			reg = <0x10000 DT_SIZE_K(928)>;
 		};
 
 		storage_partition: partition@f8000 {
diff --git a/boards/st/disco_l475_iot1/disco_l475_iot1.yaml b/boards/st/disco_l475_iot1/disco_l475_iot1.yaml
index 83d7b66b0cb..801856fa3b0 100644
--- a/boards/st/disco_l475_iot1/disco_l475_iot1.yaml
+++ b/boards/st/disco_l475_iot1/disco_l475_iot1.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_gpio
   - arduino_i2c
diff --git a/boards/st/disco_l475_iot1/doc/index.rst b/boards/st/disco_l475_iot1/doc/index.rst
index b301979a163..60523b3cfe1 100644
--- a/boards/st/disco_l475_iot1/doc/index.rst
+++ b/boards/st/disco_l475_iot1/doc/index.rst
@@ -92,47 +92,7 @@ More information about STM32L475VG can be found here:
 Supported Features
 ==================
 
-The Zephyr Disco L475 IoT board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | DAC Controller                      |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| QSPI NOR  | on-chip    | off-chip flash                      |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-
-	:zephyr_file:`boards/st/disco_l475_iot1/disco_l475_iot1_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -186,6 +146,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Disco L475 IoT board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``disco_l475_iot1`` board configuration can be built and
diff --git a/boards/st/nucleo_c031c6/doc/index.rst b/boards/st/nucleo_c031c6/doc/index.rst
index 7de1e597fac..6bdc4707018 100644
--- a/boards/st/nucleo_c031c6/doc/index.rst
+++ b/boards/st/nucleo_c031c6/doc/index.rst
@@ -51,45 +51,7 @@ More information about STM32C031C6 can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_c031c6 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| IWDG      | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| WWDG      | on-chip    | window watchdog                     |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | Direct Memory Access                |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_c031c6/nucleo_c031c6_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -110,6 +72,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo C031C6 board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_c031c6`` board configuration can be built and
diff --git a/boards/st/nucleo_c031c6/nucleo_c031c6.yaml b/boards/st/nucleo_c031c6/nucleo_c031c6.yaml
index 7f311f93c48..713f5118a33 100644
--- a/boards/st/nucleo_c031c6/nucleo_c031c6.yaml
+++ b/boards/st/nucleo_c031c6/nucleo_c031c6.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - counter
diff --git a/boards/st/nucleo_c071rb/doc/index.rst b/boards/st/nucleo_c071rb/doc/index.rst
index 7d4637c82a5..4cbeeb2e250 100644
--- a/boards/st/nucleo_c071rb/doc/index.rst
+++ b/boards/st/nucleo_c071rb/doc/index.rst
@@ -55,47 +55,7 @@ More information about STM32C071RB can be found here:
 Supported Features
 ==================
 
-The Zephyr ``nucleo_c071rb`` board supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| IWDG      | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| WWDG      | on-chip    | window watchdog                     |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | Direct Memory Access                |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_c071rb/nucleo_c071rb_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -121,6 +81,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo C071RB board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_c071rb`` board can be built and
diff --git a/boards/st/nucleo_c071rb/nucleo_c071rb.dts b/boards/st/nucleo_c071rb/nucleo_c071rb.dts
index 14ae1e59f5e..3d4bcd0a12e 100644
--- a/boards/st/nucleo_c071rb/nucleo_c071rb.dts
+++ b/boards/st/nucleo_c071rb/nucleo_c071rb.dts
@@ -72,6 +72,10 @@
 	status = "okay";
 };
 
+&clk_hsi {
+	status = "okay";
+};
+
 &rcc {
 	clocks = <&clk_hse>;
 	clock-frequency = <DT_FREQ_M(48)>;
@@ -121,9 +125,16 @@
 	clock-frequency = <I2C_BITRATE_FAST>;
 };
 
+&i2c2 {
+	pinctrl-0 = <&i2c2_scl_pa7 &i2c2_sda_pa6>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
 &spi1 {
-	pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5
-		     &spi1_miso_pa11 &spi1_mosi_pa12>;
+	pinctrl-0 = <&spi1_nss_pb0 &spi1_sck_pb3
+		     &spi1_miso_pb4 &spi1_mosi_pb5>;
 	pinctrl-names = "default";
 	status = "okay";
 };
@@ -131,7 +142,9 @@
 &adc1 {
 	pinctrl-0 = <&adc1_in0_pa0 &adc1_in1_pa1 &adc1_in4_pa4>;
 	pinctrl-names = "default";
-	st,adc-clock-source = "SYNC";
+	st,adc-clock-source = "ASYNC";
+	clocks = <&rcc STM32_CLOCK(APB1_2, 20U)>,
+		 <&rcc STM32_SRC_HSI ADC_SEL(2)>;
 	st,adc-prescaler = <4>;
 	status = "okay";
 	vref-mv = <3300>;
diff --git a/boards/st/nucleo_c071rb/nucleo_c071rb.yaml b/boards/st/nucleo_c071rb/nucleo_c071rb.yaml
index 6332fc1bd1c..50ca9ed00ee 100644
--- a/boards/st/nucleo_c071rb/nucleo_c071rb.yaml
+++ b/boards/st/nucleo_c071rb/nucleo_c071rb.yaml
@@ -5,8 +5,8 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
+  - adc
   - arduino_gpio
   - counter
   - dma
diff --git a/boards/st/nucleo_f030r8/doc/index.rst b/boards/st/nucleo_f030r8/doc/index.rst
index 34abf6f6cb0..41a3f68fbd1 100644
--- a/boards/st/nucleo_f030r8/doc/index.rst
+++ b/boards/st/nucleo_f030r8/doc/index.rst
@@ -29,7 +29,6 @@ Nucleo F030R8 provides the following hardware components:
   - Arduino* Uno V3 connectivity
   - ST morpho extension pin headers for full access to all STM32 I/Os
 
-- ARM* mbed*
 - On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
 
   - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
@@ -50,11 +49,6 @@ Nucleo F030R8 provides the following hardware components:
   - Mass storage
   - Debug port
 
-- Support of wide choice of Integrated Development Environments (IDEs) including:
-
-  - IAR
-  - ARM Keil
-  - GCC-based IDEs
 
 More information about STM32F030R8 can be found here:
 
@@ -64,35 +58,7 @@ More information about STM32F030R8 can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_f030r8 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c controller                      |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC controller                      |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f030r8/nucleo_f030r8_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -127,6 +93,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo F030R8 board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_f030r8`` board configuration can be built and
diff --git a/boards/st/nucleo_f030r8/nucleo_f030r8_1.yaml b/boards/st/nucleo_f030r8/nucleo_f030r8_1.yaml
index 814f2a7fc1b..94e7443c404 100644
--- a/boards/st/nucleo_f030r8/nucleo_f030r8_1.yaml
+++ b/boards/st/nucleo_f030r8/nucleo_f030r8_1.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 8
 flash: 64
 supported:
diff --git a/boards/st/nucleo_f030r8/nucleo_f030r8_2.yaml b/boards/st/nucleo_f030r8/nucleo_f030r8_2.yaml
index 0cdc0e8ee9d..6bff733424e 100644
--- a/boards/st/nucleo_f030r8/nucleo_f030r8_2.yaml
+++ b/boards/st/nucleo_f030r8/nucleo_f030r8_2.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 8
 flash: 64
 supported:
diff --git a/boards/st/nucleo_f031k6/doc/index.rst b/boards/st/nucleo_f031k6/doc/index.rst
index 2da4927aead..f87d39b3a4d 100644
--- a/boards/st/nucleo_f031k6/doc/index.rst
+++ b/boards/st/nucleo_f031k6/doc/index.rst
@@ -41,33 +41,7 @@ More information about STM32F031K6 can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_f031k6 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c controller                      |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi controller                      |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f031k6/nucleo_f031k6_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -96,6 +70,8 @@ For more details please refer to `STM32 Nucleo-32 board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo F031K6 board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_f031k6`` board configuration can be built and
diff --git a/boards/st/nucleo_f031k6/nucleo_f031k6.yaml b/boards/st/nucleo_f031k6/nucleo_f031k6.yaml
index 9b04bd973bf..289875df5b1 100644
--- a/boards/st/nucleo_f031k6/nucleo_f031k6.yaml
+++ b/boards/st/nucleo_f031k6/nucleo_f031k6.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 4
 flash: 32
 supported:
diff --git a/boards/st/nucleo_f042k6/doc/index.rst b/boards/st/nucleo_f042k6/doc/index.rst
index 51145f105e2..8efbf66a8cc 100644
--- a/boards/st/nucleo_f042k6/doc/index.rst
+++ b/boards/st/nucleo_f042k6/doc/index.rst
@@ -41,33 +41,7 @@ More information about STM32F042K6 can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_f042k6 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c controller                      |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi controller                      |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f042k6/nucleo_f042k6_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -96,6 +70,8 @@ For more details please refer to `STM32 Nucleo-32 board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo F042K6 board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_f042k6`` board configuration can be built and
diff --git a/boards/st/nucleo_f042k6/nucleo_f042k6.yaml b/boards/st/nucleo_f042k6/nucleo_f042k6.yaml
index a86f5dddaeb..826ce0b046d 100644
--- a/boards/st/nucleo_f042k6/nucleo_f042k6.yaml
+++ b/boards/st/nucleo_f042k6/nucleo_f042k6.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 6
 flash: 32
 supported:
diff --git a/boards/st/nucleo_f070rb/doc/index.rst b/boards/st/nucleo_f070rb/doc/index.rst
index c198fe28f6e..7db43191d67 100644
--- a/boards/st/nucleo_f070rb/doc/index.rst
+++ b/boards/st/nucleo_f070rb/doc/index.rst
@@ -29,7 +29,6 @@ Nucleo F070RB provides the following hardware components:
   - Arduino* Uno V3 connectivity
   - ST morpho extension pin headers for full access to all STM32 I/Os
 
-- ARM* mbed*
 - On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
 
   - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
@@ -50,11 +49,6 @@ Nucleo F070RB provides the following hardware components:
   - Mass storage
   - Debug port
 
-- Support of wide choice of Integrated Development Environments (IDEs) including:
-
-  - IAR
-  - ARM Keil
-  - GCC-based IDEs
 
 More information about STM32F070RB can be found in
 the `STM32F070 reference manual`_ .
@@ -63,37 +57,7 @@ the `STM32F070 reference manual`_ .
 Supported Features
 ==================
 
-The Zephyr nucleo_f070rb board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c controller                      |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | SPI controller                      |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f070rb/nucleo_f070rb_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -126,6 +90,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo F070RB board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_f070rb`` board configuration can be built and
diff --git a/boards/st/nucleo_f070rb/nucleo_f070rb.yaml b/boards/st/nucleo_f070rb/nucleo_f070rb.yaml
index 5ed0d28dd3d..4745c183399 100644
--- a/boards/st/nucleo_f070rb/nucleo_f070rb.yaml
+++ b/boards/st/nucleo_f070rb/nucleo_f070rb.yaml
@@ -7,7 +7,6 @@ flash: 128
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - arduino_gpio
diff --git a/boards/st/nucleo_f072rb/Kconfig.defconfig b/boards/st/nucleo_f072rb/Kconfig.defconfig
new file mode 100644
index 00000000000..1031692291f
--- /dev/null
+++ b/boards/st/nucleo_f072rb/Kconfig.defconfig
@@ -0,0 +1,12 @@
+# NUCLEO_F072RB board configuration
+
+# Copyright (c) 2025 Alex Fabre
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_NUCLEO_F072RB
+
+config SPI_STM32_INTERRUPT
+	default y
+	depends on SPI
+
+endif # BOARD_NUCLEO_F072RB
diff --git a/boards/st/nucleo_f072rb/Kconfig.nucleo_f072rb b/boards/st/nucleo_f072rb/Kconfig.nucleo_f072rb
new file mode 100644
index 00000000000..165ba6c2902
--- /dev/null
+++ b/boards/st/nucleo_f072rb/Kconfig.nucleo_f072rb
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Alex Fabre
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NUCLEO_F072RB
+	select SOC_STM32F072XB
diff --git a/boards/st/nucleo_f072rb/arduino_r3_connector.dtsi b/boards/st/nucleo_f072rb/arduino_r3_connector.dtsi
new file mode 100644
index 00000000000..6ed2b49ad15
--- /dev/null
+++ b/boards/st/nucleo_f072rb/arduino_r3_connector.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2025 Alex Fabre
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	arduino_header: connector {
+		compatible = "arduino-header-r3";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpioa 0 0>,	/* A0 */
+			   <1 0 &gpioa 1 0>,	/* A1 */
+			   <2 0 &gpioa 4 0>,	/* A2 */
+			   <3 0 &gpiob 0 0>,	/* A3 */
+			   <4 0 &gpioc 1 0>,	/* A4 */
+			   <5 0 &gpioc 0 0>,	/* A5 */
+			   <6 0 &gpioa 3 0>,	/* D0 */
+			   <7 0 &gpioa 2 0>,	/* D1 */
+			   <8 0 &gpioa 10 0>,	/* D2 */
+			   <9 0 &gpiob 3 0>,	/* D3 */
+			   <10 0 &gpiob 5 0>,	/* D4 */
+			   <11 0 &gpiob 4 0>,	/* D5 */
+			   <12 0 &gpiob 10 0>,	/* D6 */
+			   <13 0 &gpioa 8 0>,	/* D7 */
+			   <14 0 &gpioa 9 0>,	/* D8 */
+			   <15 0 &gpioc 7 0>,	/* D9 */
+			   <16 0 &gpiob 6 0>,	/* D10 */
+			   <17 0 &gpioa 7 0>,	/* D11 */
+			   <18 0 &gpioa 6 0>,	/* D12 */
+			   <19 0 &gpioa 5 0>,	/* D13 */
+			   <20 0 &gpiob 9 0>,	/* D14 */
+			   <21 0 &gpiob 8 0>;	/* D15 */
+	};
+};
+
+arduino_i2c: &i2c1 {};
+arduino_spi: &spi1 {};
diff --git a/boards/st/nucleo_f072rb/board.cmake b/boards/st/nucleo_f072rb/board.cmake
new file mode 100644
index 00000000000..136bd345f6a
--- /dev/null
+++ b/boards/st/nucleo_f072rb/board.cmake
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# keep first
+board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
+board_runner_args(jlink "--device=STM32F072RB" "--speed=4000")
+
+# keep first
+include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/st/nucleo_f072rb/board.yml b/boards/st/nucleo_f072rb/board.yml
new file mode 100644
index 00000000000..96a4c251439
--- /dev/null
+++ b/boards/st/nucleo_f072rb/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: nucleo_f072rb
+  full_name: Nucleo F072RB
+  vendor: st
+  socs:
+    - name: stm32f072xb
diff --git a/boards/st/nucleo_f072rb/doc/img/nucleo_f072rb.webp b/boards/st/nucleo_f072rb/doc/img/nucleo_f072rb.webp
new file mode 100644
index 00000000000..36ee2ce83aa
Binary files /dev/null and b/boards/st/nucleo_f072rb/doc/img/nucleo_f072rb.webp differ
diff --git a/boards/st/nucleo_f072rb/doc/img/nucleo_f072rb_connectors.webp b/boards/st/nucleo_f072rb/doc/img/nucleo_f072rb_connectors.webp
new file mode 100644
index 00000000000..db83da75dab
Binary files /dev/null and b/boards/st/nucleo_f072rb/doc/img/nucleo_f072rb_connectors.webp differ
diff --git a/boards/st/nucleo_f072rb/doc/index.rst b/boards/st/nucleo_f072rb/doc/index.rst
new file mode 100644
index 00000000000..a78e0226b8e
--- /dev/null
+++ b/boards/st/nucleo_f072rb/doc/index.rst
@@ -0,0 +1,153 @@
+.. zephyr:board:: nucleo_f072rb
+
+Overview
+********
+The STM32 Nucleo-64 development board with STM32F072RB MCU, supports Arduino and ST morpho connectivity.
+
+The STM32 Nucleo board provides an affordable, and flexible way for users to try out new concepts,
+and build prototypes with the STM32 microcontroller, choosing from the various
+combinations of performance, power consumption, and features.
+
+The Arduino* Uno V3 connectivity support and the ST morpho headers allow easy functionality
+expansion of the STM32 Nucleo open development platform with a wide choice of
+specialized shields.
+
+The STM32 Nucleo board integrates the ST-LINK/V2-1 debugger and programmer.
+
+The STM32 Nucleo board comes with the STM32 comprehensive software HAL library together
+with various packaged software examples.
+
+More information about the board can be found at the `Nucleo F072RB website`_.
+
+Hardware
+********
+Nucleo F072RB provides the following hardware components:
+
+- STM32 microcontroller in QFP64 package
+- Two types of extension resources:
+
+  - Arduino* Uno V3 connectivity
+  - ST morpho extension pin headers for full access to all STM32 I/Os
+
+- On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
+
+  - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
+
+- Flexible board power supply:
+
+  - USB VBUS or external source (3.3V, 5V, 7 - 12V)
+  - Power management access point
+
+- Three LEDs:
+
+  - USB communication (LD1), user LED (LD2), power LED (LD3)
+
+- Two push-buttons: USER and RESET
+- USB re-enumeration capability. Three different interfaces supported on USB:
+
+  - Virtual COM port
+  - Mass storage
+  - Debug port
+
+More information about STM32F072RB can be found in
+the `STM32F072 reference manual`_ .
+
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
+input (with or without pull-up or pull-down), or as peripheral alternate function. Most of the
+GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current
+capable except for analog inputs.
+
+Board connectors:
+-----------------
+.. image:: img/nucleo_f072rb_connectors.webp
+   :align: center
+   :alt: Nucleo F072RB connectors
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+- UART_1 TX/RX : PA9/PA10
+- UART_2 TX/RX : PA2/PA3 (ST-Link Virtual COM Port)
+- I2C1 SCL/SDA : PB8/PB9 (Arduino I2C)
+- I2C2 SCL/SDA : PB10/PB11
+- SPI1 NSS/SCK/MISO/MOSI : PB6/PA5/PA6/PA7 (Arduino SPI)
+- SPI2 SCK/MISO/MOSI : PB13/PB14/PB15
+- USER_PB : PC13
+- LD1 : PA5
+
+For more details please refer to `STM32 Nucleo-64 board User Manual`_.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Nucleo F072RB board includes an ST-LINK/V2-1 embedded debug tool interface.
+
+Applications for the ``nucleo_f072rb`` board configuration can be built and
+flashed in the usual way (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Flashing
+========
+
+The board is configured to be flashed using west `STM32CubeProgrammer`_ runner,
+so its :ref:`installation <stm32cubeprog-flash-host-tools>` is required.
+
+Alternatively, OpenOCD or JLink can also be used to flash the board using
+the ``--runner`` (or ``-r``) option:
+
+.. code-block:: console
+
+   $ west flash --runner openocd
+   $ west flash --runner jlink
+
+Flashing an application to Nucleo F072RB
+----------------------------------------
+
+Here is an example for the :zephyr:code-sample:`blinky` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: nucleo_f072rb
+   :goals: build flash
+
+You will see the LED blinking every second.
+
+Debugging
+=========
+
+You can debug an application in the usual way.  Here is an example for the
+:zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: nucleo_f072rb
+   :maybe-skip-config:
+   :goals: debug
+
+References
+**********
+
+.. target-notes::
+
+.. _Nucleo F072RB website:
+   https://www.st.com/en/evaluation-tools/nucleo-f072rb.html
+
+.. _STM32F072 reference manual:
+   https://www.st.com/resource/en/reference_manual/dm00031936.pdf
+
+.. _STM32 Nucleo-64 board User Manual:
+   https://www.st.com/resource/en/user_manual/dm00105823.pdf
+
+.. _STM32CubeProgrammer:
+   https://www.st.com/en/development-tools/stm32cubeprog.html
diff --git a/boards/st/nucleo_f072rb/nucleo_f072rb.dts b/boards/st/nucleo_f072rb/nucleo_f072rb.dts
new file mode 100644
index 00000000000..207639f73b1
--- /dev/null
+++ b/boards/st/nucleo_f072rb/nucleo_f072rb.dts
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2025 Alex Fabre
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/f0/stm32f072Xb.dtsi>
+#include <st/f0/stm32f072r(8-b)tx-pinctrl.dtsi>
+#include "arduino_r3_connector.dtsi"
+#include "st_morpho_connector.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "STMicroelectronics NUCLEO-F072RB board";
+	compatible = "st,stm32f072rb-nucleo";
+
+	chosen {
+		zephyr,console = &usart2;
+		zephyr,shell-uart = &usart2;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+		green_led_2: led_2 {
+			gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
+			label = "User LD2";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button: button {
+			label = "User";
+			gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	aliases {
+		led0 = &green_led_2;
+		sw0 = &user_button;
+		watchdog0 = &iwdg;
+		die-temp0 = &die_temp;
+		volt-sensor0 = &vref;
+	};
+};
+
+&clk_lse {
+	status = "okay";
+};
+
+&clk_hse {
+	hse-bypass;
+	clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
+	status = "okay";
+};
+
+&pll {
+	clocks = <&clk_hse>;
+	prediv = <1>;
+	mul = <6>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(48)>;
+	ahb-prescaler = <1>;
+	apb1-prescaler = <2>;
+};
+
+&usart1 {
+	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&usart2 {
+	pinctrl-0 = <&usart2_tx_pa2 &usart2_rx_pa3>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&spi1 {
+	pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpiob 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+	status = "okay";
+};
+
+&spi2 {
+	pinctrl-0 = <&spi2_sck_pb13 &spi2_miso_pb14 &spi2_mosi_pb15>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&iwdg {
+	status = "okay";
+};
+
+&adc1 {
+	pinctrl-0 = <&adc_in0_pa0>;
+	pinctrl-names = "default";
+	st,adc-clock-source = "SYNC";
+	st,adc-prescaler = <4>;
+	status = "okay";
+};
+
+&rtc {
+	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
+		 <&rcc STM32_SRC_LSE RTC_SEL(1)>;
+	status = "okay";
+};
+
+&die_temp {
+	status = "okay";
+};
+
+&vref {
+	status = "okay";
+};
diff --git a/boards/st/nucleo_f072rb/nucleo_f072rb.yaml b/boards/st/nucleo_f072rb/nucleo_f072rb.yaml
new file mode 100644
index 00000000000..0a46f541b91
--- /dev/null
+++ b/boards/st/nucleo_f072rb/nucleo_f072rb.yaml
@@ -0,0 +1,24 @@
+identifier: nucleo_f072rb
+name: ST Nucleo F072RB
+type: mcu
+arch: arm
+ram: 16
+flash: 128
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - adc
+  - arduino_gpio
+  - arduino_i2c
+  - arduino_spi
+  - gpio
+  - i2c
+  - spi
+  - watchdog
+  - rtc
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+vendor: st
diff --git a/boards/st/nucleo_f072rb/nucleo_f072rb_defconfig b/boards/st/nucleo_f072rb/nucleo_f072rb_defconfig
new file mode 100644
index 00000000000..c60dfffbc3b
--- /dev/null
+++ b/boards/st/nucleo_f072rb/nucleo_f072rb_defconfig
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# GPIO Controller
+CONFIG_GPIO=y
diff --git a/boards/st/nucleo_f072rb/st_morpho_connector.dtsi b/boards/st/nucleo_f072rb/st_morpho_connector.dtsi
new file mode 100644
index 00000000000..397f3192dac
--- /dev/null
+++ b/boards/st/nucleo_f072rb/st_morpho_connector.dtsi
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2024 Alex Fabre
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/gpio/st-morpho-header.h>
+
+/ {
+	st_morpho_header: st-morpho-header {
+		compatible = "st-morpho-header";
+		#gpio-cells = <2>;
+		gpio-map-mask = <ST_MORPHO_PIN_MASK 0x0>;
+		gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>;
+		gpio-map = <ST_MORPHO_L_1 0 &gpioc 10 0>,
+			   <ST_MORPHO_L_2 0 &gpioc 11 0>,
+			   <ST_MORPHO_L_3 0 &gpioc 12 0>,
+			   <ST_MORPHO_L_4 0 &gpiod 2 0>,
+			   <ST_MORPHO_L_9 0 &gpiof 6 0>,
+			   <ST_MORPHO_L_11 0 &gpiof 7 0>,
+			   <ST_MORPHO_L_13 0 &gpioa 13 0>,
+			   <ST_MORPHO_L_15 0 &gpioa 14 0>,
+			   <ST_MORPHO_L_17 0 &gpioa 15 0>,
+			   <ST_MORPHO_L_21 0 &gpiob 7 0>,
+			   <ST_MORPHO_L_23 0 &gpioc 13 0>,
+			   <ST_MORPHO_L_25 0 &gpioc 14 0>, /* SB49=ON */
+			   <ST_MORPHO_L_27 0 &gpioc 15 0>, /* SB48=ON */
+			   <ST_MORPHO_L_28 0 &gpioa 0 0>,
+			   <ST_MORPHO_L_29 0 &gpiof 0 0>, /* SB55=ON */
+			   <ST_MORPHO_L_30 0 &gpioa 1 0>,
+			   <ST_MORPHO_L_31 0 &gpiof 1 0>, /* SB54=ON */
+			   <ST_MORPHO_L_32 0 &gpioa 4 0>,
+			   <ST_MORPHO_L_34 0 &gpiob 0 0>,
+			   <ST_MORPHO_L_35 0 &gpioc 2 0>,
+			   <ST_MORPHO_L_36 0 &gpioc 1 0>, /* SB56=ON, SB46=OFF */
+			   <ST_MORPHO_L_37 0 &gpioc 3 0>,
+			   <ST_MORPHO_L_38 0 &gpioc 0 0>, /* SB51=ON, SB52=OFF */
+			   <ST_MORPHO_R_1 0 &gpioc 9 0>,
+			   <ST_MORPHO_R_2 0 &gpioc 8 0>,
+			   <ST_MORPHO_R_3 0 &gpiob 8 0>,
+			   <ST_MORPHO_R_4 0 &gpioc 6 0>,
+			   <ST_MORPHO_R_5 0 &gpiob 9 0>,
+			   <ST_MORPHO_R_6 0 &gpioc 5 0>,
+			   <ST_MORPHO_R_10 0 &gpiod 8 0>,
+			   <ST_MORPHO_R_11 0 &gpioa 5 0>, /* SB42=ON, SB29=OFF */
+			   <ST_MORPHO_R_12 0 &gpioa 12 0>,
+			   <ST_MORPHO_R_13 0 &gpioa 6 0>, /* SB41=ON, SB24=OFF */
+			   <ST_MORPHO_R_14 0 &gpioa 11 0>,
+			   <ST_MORPHO_R_15 0 &gpioa 7 0>, /* SB40=ON, SB20=OFF */
+			   <ST_MORPHO_R_16 0 &gpiob 12 0>,
+			   <ST_MORPHO_R_17 0 &gpiob 6 0>,
+			   <ST_MORPHO_R_18 0 &gpiob 11 0>,
+			   <ST_MORPHO_R_19 0 &gpioc 7 0>,
+			   <ST_MORPHO_R_21 0 &gpioa 9 0>,
+			   <ST_MORPHO_R_22 0 &gpiob 2 0>,
+			   <ST_MORPHO_R_23 0 &gpioa 8 0>,
+			   <ST_MORPHO_R_24 0 &gpiob 1 0>,
+			   <ST_MORPHO_R_25 0 &gpiob 10 0>,
+			   <ST_MORPHO_R_26 0 &gpiob 15 0>, /* SB25=ON, SB36=OFF */
+			   <ST_MORPHO_R_27 0 &gpiob 4 0>,
+			   <ST_MORPHO_R_28 0 &gpiob 14 0>, /* SB28=ON, SB39=OFF */
+			   <ST_MORPHO_R_29 0 &gpiob 5 0>,
+			   <ST_MORPHO_R_30 0 &gpiob 13 0>, /* SB35=ON, SB44=OFF */
+			   <ST_MORPHO_R_31 0 &gpiob 3 0>,
+			   <ST_MORPHO_R_33 0 &gpioa 10 0>,
+			   <ST_MORPHO_R_34 0 &gpioc 4 0>,
+			   <ST_MORPHO_R_35 0 &gpioa 2 0>,
+			   <ST_MORPHO_R_36 0 &gpiof 5 0>,
+			   <ST_MORPHO_R_37 0 &gpioa 3 0>,
+			   <ST_MORPHO_R_38 0 &gpiof 4 0>;
+	};
+};
diff --git a/boards/st/nucleo_f072rb/support/openocd.cfg b/boards/st/nucleo_f072rb/support/openocd.cfg
new file mode 100644
index 00000000000..f0d0b22a310
--- /dev/null
+++ b/boards/st/nucleo_f072rb/support/openocd.cfg
@@ -0,0 +1,12 @@
+source [find board/st_nucleo_f0.cfg]
+
+$_TARGETNAME configure -event gdb-attach {
+	echo "Debugger attaching: halting execution"
+	reset halt
+	gdb_breakpoint_override hard
+}
+
+$_TARGETNAME configure -event gdb-detach {
+	echo "Debugger detaching: resuming execution"
+	resume
+}
diff --git a/boards/st/nucleo_f091rc/doc/index.rst b/boards/st/nucleo_f091rc/doc/index.rst
index 60181533aff..a8aded09f47 100644
--- a/boards/st/nucleo_f091rc/doc/index.rst
+++ b/boards/st/nucleo_f091rc/doc/index.rst
@@ -29,7 +29,6 @@ Nucleo F091RC provides the following hardware components:
   - Arduino* Uno V3 connectivity
   - ST morpho extension pin headers for full access to all STM32 I/Os
 
-- ARM* mbed*
 - On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
 
   - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
@@ -50,11 +49,6 @@ Nucleo F091RC provides the following hardware components:
   - Mass storage
   - Debug port
 
-- Support of wide choice of Integrated Development Environments (IDEs) including:
-
-  - IAR
-  - ARM Keil
-  - GCC-based IDEs
 
 More information about STM32F091RC can be found in the
 `STM32F091 reference manual`_
@@ -63,51 +57,7 @@ More information about STM32F091RC can be found in the
 Supported Features
 ==================
 
-The Zephyr nucleo_f091rc board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c controller                      |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | SPI controller                      |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | CAN controller                      |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC controller                      |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | DAC controller                      |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | Direct Memory Access                |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f091rc/nucleo_f091rc_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -143,6 +93,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo F091RC board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_f091rc`` board configuration can be built and
diff --git a/boards/st/nucleo_f091rc/nucleo_f091rc.yaml b/boards/st/nucleo_f091rc/nucleo_f091rc.yaml
index d0ac388b263..f8840d08c96 100644
--- a/boards/st/nucleo_f091rc/nucleo_f091rc.yaml
+++ b/boards/st/nucleo_f091rc/nucleo_f091rc.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
 flash: 256
 supported:
diff --git a/boards/st/nucleo_f103rb/doc/index.rst b/boards/st/nucleo_f103rb/doc/index.rst
index 662fd3ac3cc..05c1c9385e5 100644
--- a/boards/st/nucleo_f103rb/doc/index.rst
+++ b/boards/st/nucleo_f103rb/doc/index.rst
@@ -29,7 +29,6 @@ Nucleo F103RB provides the following hardware components:
   - Arduino* Uno V3 connectivity
   - ST morpho extension pin headers for full access to all STM32 I/Os
 
-- ARM* mbed*
 - On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
 
   - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
@@ -50,11 +49,6 @@ Nucleo F103RB provides the following hardware components:
   - Mass storage
   - Debug port
 
-- Support of wide choice of Integrated Development Environments (IDEs) including:
-
-  - IAR
-  - ARM Keil
-  - GCC-based IDEs
 
 More information about STM32F103RB can be found here:
 
@@ -64,39 +58,7 @@ More information about STM32F103RB can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_f103rb board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | Direct Memory Access                |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f103rb/nucleo_f103rb_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -129,6 +91,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo F103RB board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_f103rb`` board configuration can be built and
diff --git a/boards/st/nucleo_f103rb/nucleo_f103rb.yaml b/boards/st/nucleo_f103rb/nucleo_f103rb.yaml
index e231aa5e1d2..507c2a01f27 100644
--- a/boards/st/nucleo_f103rb/nucleo_f103rb.yaml
+++ b/boards/st/nucleo_f103rb/nucleo_f103rb.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 20
 flash: 128
 supported:
diff --git a/boards/st/nucleo_f207zg/doc/index.rst b/boards/st/nucleo_f207zg/doc/index.rst
index 51082a2cfc6..048cf26b7eb 100644
--- a/boards/st/nucleo_f207zg/doc/index.rst
+++ b/boards/st/nucleo_f207zg/doc/index.rst
@@ -63,52 +63,7 @@ More information about STM32F207ZG can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_207zg board configuration supports the following hardware features:
-
-+-------------+------------+-------------------------------------+
-| Interface   | Controller | Driver/Component                    |
-+=============+============+=====================================+
-| NVIC        | on-chip    | nested vector interrupt controller  |
-+-------------+------------+-------------------------------------+
-| UART        | on-chip    | serial port-polling;                |
-|             |            | serial port-interrupt               |
-+-------------+------------+-------------------------------------+
-| PINMUX      | on-chip    | pinmux                              |
-+-------------+------------+-------------------------------------+
-| GPIO        | on-chip    | gpio                                |
-+-------------+------------+-------------------------------------+
-| ETHERNET    | on-chip    | Ethernet                            |
-+-------------+------------+-------------------------------------+
-| I2C         | on-chip    | i2c                                 |
-+-------------+------------+-------------------------------------+
-| USB         | on-chip    | USB device                          |
-+-------------+------------+-------------------------------------+
-| SPI         | on-chip    | spi                                 |
-+-------------+------------+-------------------------------------+
-| WATCHDOG    | on-chip    | independent watchdog                |
-+-------------+------------+-------------------------------------+
-| ADC         | on-chip    | ADC Controller                      |
-+-------------+------------+-------------------------------------+
-| DAC         | on-chip    | DAC Controller                      |
-+-------------+------------+-------------------------------------+
-| Backup SRAM | on-chip    | Backup SRAM                         |
-+-------------+------------+-------------------------------------+
-| PWM         | on-chip    | PWM                                 |
-+-------------+------------+-------------------------------------+
-| RNG         | on-chip    | Random Number Generator             |
-+-------------+------------+-------------------------------------+
-| DMA         | on-chip    | Direct Memory Access                |
-+-------------+------------+-------------------------------------+
-| die-temp    | on-chip    | die temperature sensor              |
-+-------------+------------+-------------------------------------+
-| RTC         | on-chip    | rtc                                 |
-+-------------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_f207zg/nucleo_f207zg_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -184,6 +139,8 @@ do it by removing ``SB156`` jumper on the back side of the board.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo F207ZG board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Flashing
diff --git a/boards/st/nucleo_f207zg/nucleo_f207zg.dts b/boards/st/nucleo_f207zg/nucleo_f207zg.dts
index 724bf9456cc..c10b1aced00 100644
--- a/boards/st/nucleo_f207zg/nucleo_f207zg.dts
+++ b/boards/st/nucleo_f207zg/nucleo_f207zg.dts
@@ -179,16 +179,27 @@ zephyr_udc0: &usbotg_fs {
 
 &mac {
 	status = "okay";
-	pinctrl-0 = <&eth_mdc_pc1
-		     &eth_rxd0_pc4
+	pinctrl-0 = <&eth_rxd0_pc4
 		     &eth_rxd1_pc5
 		     &eth_ref_clk_pa1
-		     &eth_mdio_pa2
 		     &eth_crs_dv_pa7
 		     &eth_tx_en_pg11
 		     &eth_txd0_pg13
 		     &eth_txd1_pb13>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&phy>;
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
+	pinctrl-names = "default";
+
+	phy: ethernet-phy@0 {
+		compatible = "ethernet-phy";
+		reg = <0x00>;
+	};
 };
 
 &flash0 {
diff --git a/boards/st/nucleo_f207zg/nucleo_f207zg.yaml b/boards/st/nucleo_f207zg/nucleo_f207zg.yaml
index 681cc571c0e..127305024fe 100644
--- a/boards/st/nucleo_f207zg/nucleo_f207zg.yaml
+++ b/boards/st/nucleo_f207zg/nucleo_f207zg.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_gpio
   - arduino_i2c
diff --git a/boards/st/nucleo_f302r8/doc/index.rst b/boards/st/nucleo_f302r8/doc/index.rst
index 9609270cd69..13a0b5b7707 100644
--- a/boards/st/nucleo_f302r8/doc/index.rst
+++ b/boards/st/nucleo_f302r8/doc/index.rst
@@ -67,34 +67,7 @@ More information about the STM32F302R8 can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_f302r8 board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f302r8/nucleo_f302r8_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -141,6 +114,8 @@ to UART2.  Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The Nucleo F302R8 board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Flashing
diff --git a/boards/st/nucleo_f302r8/nucleo_f302r8.yaml b/boards/st/nucleo_f302r8/nucleo_f302r8.yaml
index a5e3758b6a6..b0607440979 100644
--- a/boards/st/nucleo_f302r8/nucleo_f302r8.yaml
+++ b/boards/st/nucleo_f302r8/nucleo_f302r8.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 16
 flash: 64
 supported:
diff --git a/boards/st/nucleo_f303k8/doc/index.rst b/boards/st/nucleo_f303k8/doc/index.rst
index a21cc477b41..dd4750a3ae5 100644
--- a/boards/st/nucleo_f303k8/doc/index.rst
+++ b/boards/st/nucleo_f303k8/doc/index.rst
@@ -63,34 +63,7 @@ More information about the STM32F303K8 can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_f303k8 board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f303k8/nucleo_f303k8_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -132,6 +105,8 @@ to UART2.  Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The Nucleo F303K8 board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Flashing
diff --git a/boards/st/nucleo_f303k8/nucleo_f303k8.yaml b/boards/st/nucleo_f303k8/nucleo_f303k8.yaml
index 3442ef50d0d..848b83324c1 100644
--- a/boards/st/nucleo_f303k8/nucleo_f303k8.yaml
+++ b/boards/st/nucleo_f303k8/nucleo_f303k8.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 12
 flash: 64
 supported:
diff --git a/boards/st/nucleo_f303re/doc/index.rst b/boards/st/nucleo_f303re/doc/index.rst
index 1c8b6363a39..2531643ab64 100644
--- a/boards/st/nucleo_f303re/doc/index.rst
+++ b/boards/st/nucleo_f303re/doc/index.rst
@@ -68,32 +68,7 @@ More information about the STM32F303RE can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_f303re board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f303re/nucleo_f303re_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -135,6 +110,8 @@ to UART2.  Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The Nucleo F303RE board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Flashing
diff --git a/boards/st/nucleo_f303re/nucleo_f303re.yaml b/boards/st/nucleo_f303re/nucleo_f303re.yaml
index 525a83f252a..c8453732df6 100644
--- a/boards/st/nucleo_f303re/nucleo_f303re.yaml
+++ b/boards/st/nucleo_f303re/nucleo_f303re.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 80
 flash: 512
 supported:
diff --git a/boards/st/nucleo_f334r8/doc/index.rst b/boards/st/nucleo_f334r8/doc/index.rst
index 385f4e05094..0f7d4f7edb7 100644
--- a/boards/st/nucleo_f334r8/doc/index.rst
+++ b/boards/st/nucleo_f334r8/doc/index.rst
@@ -30,7 +30,6 @@ Nucleo F334R8 provides the following hardware components:
   - Arduino* Uno V3 connectivity
   - ST morpho extension pin headers for full access to all STM32 I/Os
 
-- ARM* mbed*
 - On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
 
   - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
@@ -51,11 +50,6 @@ Nucleo F334R8 provides the following hardware components:
   - Mass storage
   - Debug port
 
-- Support of wide choice of Integrated Development Environments (IDEs) including:
-
-  - IAR
-  - ARM Keil
-  - GCC-based IDEs
 
 More information about STM32F334R8 can be found in the
 `STM32F334 reference manual`_
@@ -64,31 +58,7 @@ More information about STM32F334R8 can be found in the
 Supported Features
 ==================
 
-The Zephyr nucleo_f334r8 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f334r8/nucleo_f334r8_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -121,6 +91,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo F334R8 board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_f334r8`` board configuration can be built and
diff --git a/boards/st/nucleo_f334r8/nucleo_f334r8.yaml b/boards/st/nucleo_f334r8/nucleo_f334r8.yaml
index a4533b015a0..542686905bb 100644
--- a/boards/st/nucleo_f334r8/nucleo_f334r8.yaml
+++ b/boards/st/nucleo_f334r8/nucleo_f334r8.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 12
 flash: 64
 testing:
diff --git a/boards/st/nucleo_f401re/doc/index.rst b/boards/st/nucleo_f401re/doc/index.rst
index fc64a2e5bfd..17e00604f1e 100644
--- a/boards/st/nucleo_f401re/doc/index.rst
+++ b/boards/st/nucleo_f401re/doc/index.rst
@@ -56,38 +56,7 @@ More information about STM32F401RE can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_401re board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | System Window Watchdog              |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f401re/nucleo_f401re_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -141,6 +110,8 @@ Nucleo F401RE board has up to 3 I2Cs. The default I2C mapping for Zephyr is:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo F401RE board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_f401re`` board configuration can be built and
diff --git a/boards/st/nucleo_f401re/nucleo_f401re.yaml b/boards/st/nucleo_f401re/nucleo_f401re.yaml
index 457c4295196..08af2b481d7 100644
--- a/boards/st/nucleo_f401re/nucleo_f401re.yaml
+++ b/boards/st/nucleo_f401re/nucleo_f401re.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_gpio
   - arduino_i2c
diff --git a/boards/st/nucleo_f410rb/doc/index.rst b/boards/st/nucleo_f410rb/doc/index.rst
index 4b48811fdf9..26018e9eab0 100644
--- a/boards/st/nucleo_f410rb/doc/index.rst
+++ b/boards/st/nucleo_f410rb/doc/index.rst
@@ -57,40 +57,7 @@ More information about STM32F410RB can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_f410rb board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| I2S       | on-chip    | i2s                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | DAC Controller                      |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | window & independent                |
-+-----------+------------+-------------------------------------+
-
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f410rb/nucleo_f410rb_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -146,6 +113,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo F410RB board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_f410rb`` board configuration can be built and
diff --git a/boards/st/nucleo_f410rb/nucleo_f410rb.yaml b/boards/st/nucleo_f410rb/nucleo_f410rb.yaml
index 81eef793cdd..6bbba048f60 100644
--- a/boards/st/nucleo_f410rb/nucleo_f410rb.yaml
+++ b/boards/st/nucleo_f410rb/nucleo_f410rb.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_gpio
   - arduino_i2c
diff --git a/boards/st/nucleo_f411re/doc/index.rst b/boards/st/nucleo_f411re/doc/index.rst
index cdfcd326787..f65d455904e 100644
--- a/boards/st/nucleo_f411re/doc/index.rst
+++ b/boards/st/nucleo_f411re/doc/index.rst
@@ -57,33 +57,7 @@ More information about STM32F411RE can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_f411re board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| I2S       | on-chip    | i2s                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f411re/nucleo_f411re_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -134,6 +108,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo F411RE board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_f411re`` board configuration can be built and
diff --git a/boards/st/nucleo_f411re/nucleo_f411re.yaml b/boards/st/nucleo_f411re/nucleo_f411re.yaml
index 90a57f93720..c86e6cca3e0 100644
--- a/boards/st/nucleo_f411re/nucleo_f411re.yaml
+++ b/boards/st/nucleo_f411re/nucleo_f411re.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_gpio
   - arduino_i2c
diff --git a/boards/st/nucleo_f412zg/doc/index.rst b/boards/st/nucleo_f412zg/doc/index.rst
index 60f5f06531a..8bc9fb26bb2 100644
--- a/boards/st/nucleo_f412zg/doc/index.rst
+++ b/boards/st/nucleo_f412zg/doc/index.rst
@@ -60,34 +60,7 @@ More information about STM32F412ZG can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_412zg board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f412zg/nucleo_f412zg_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -148,6 +121,8 @@ Ethernet over USB is configured as the default network interface
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo F412ZG board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Flashing
diff --git a/boards/st/nucleo_f412zg/nucleo_f412zg.yaml b/boards/st/nucleo_f412zg/nucleo_f412zg.yaml
index 10fd21fc705..8164af0e6a6 100644
--- a/boards/st/nucleo_f412zg/nucleo_f412zg.yaml
+++ b/boards/st/nucleo_f412zg/nucleo_f412zg.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 256
 flash: 1024
 supported:
diff --git a/boards/st/nucleo_f413zh/doc/index.rst b/boards/st/nucleo_f413zh/doc/index.rst
index 0c9bad9f77d..6d948615b8d 100644
--- a/boards/st/nucleo_f413zh/doc/index.rst
+++ b/boards/st/nucleo_f413zh/doc/index.rst
@@ -60,34 +60,7 @@ More information about STM32F413ZH can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_413zh board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f413zh/nucleo_f413zh_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -150,6 +123,8 @@ supports both device and host functions through its micro USB connector
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo F413ZH board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Flashing
diff --git a/boards/st/nucleo_f413zh/nucleo_f413zh.dts b/boards/st/nucleo_f413zh/nucleo_f413zh.dts
index 28769998d86..11623e6d3b1 100644
--- a/boards/st/nucleo_f413zh/nucleo_f413zh.dts
+++ b/boards/st/nucleo_f413zh/nucleo_f413zh.dts
@@ -19,6 +19,7 @@
 		zephyr,shell-uart = &usart3;
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
 	};
 
 	leds: leds {
@@ -115,6 +116,40 @@ zephyr_udc0: &usbotg_fs {
 	status = "okay";
 };
 
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 DT_SIZE_K(64)>;
+			read-only;
+		};
+
+		/*
+		 * The flash starting at offset 0x10000 and ending at
+		 * offset 0x1ffff is reserved for use by the application.
+		 */
+
+		slot0_partition: partition@20000 {
+			label = "image-0";
+			reg = <0x00020000 DT_SIZE_K(256)>;
+		};
+
+		slot1_partition: partition@60000 {
+			label = "image-1";
+			reg = <0x00060000 DT_SIZE_K(256)>;
+		};
+
+		scratch_partition: partition@a0000 {
+			label = "image-scratch";
+			reg = <0x000a0000 DT_SIZE_K(128)>;
+		};
+	};
+};
+
 &timers2 {
 	status = "okay";
 
diff --git a/boards/st/nucleo_f413zh/nucleo_f413zh.yaml b/boards/st/nucleo_f413zh/nucleo_f413zh.yaml
index 4a8dda323d2..e9471e007ea 100644
--- a/boards/st/nucleo_f413zh/nucleo_f413zh.yaml
+++ b/boards/st/nucleo_f413zh/nucleo_f413zh.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 320
 flash: 1536
 supported:
diff --git a/boards/st/nucleo_f429zi/doc/index.rst b/boards/st/nucleo_f429zi/doc/index.rst
index 1fe03b83ced..925528cb9a1 100644
--- a/boards/st/nucleo_f429zi/doc/index.rst
+++ b/boards/st/nucleo_f429zi/doc/index.rst
@@ -70,48 +70,7 @@ More information about STM32F429ZI can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_f429zi board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | Ethernet                            |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | DAC Controller                      |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | Direct Memory Access                |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f429zi/nucleo_f429zi_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -173,6 +132,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The Nucleo F429ZI board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Flashing
diff --git a/boards/st/nucleo_f429zi/nucleo_f429zi.dts b/boards/st/nucleo_f429zi/nucleo_f429zi.dts
index d05081ed839..ee88ed5ce39 100644
--- a/boards/st/nucleo_f429zi/nucleo_f429zi.dts
+++ b/boards/st/nucleo_f429zi/nucleo_f429zi.dts
@@ -176,16 +176,27 @@ zephyr_udc0: &usbotg_fs {
 
 &mac {
 	status = "okay";
-	pinctrl-0 = <&eth_mdc_pc1
-		     &eth_rxd0_pc4
+	pinctrl-0 = <&eth_rxd0_pc4
 		     &eth_rxd1_pc5
 		     &eth_ref_clk_pa1
-		     &eth_mdio_pa2
 		     &eth_crs_dv_pa7
 		     &eth_tx_en_pg11
 		     &eth_txd0_pg13
 		     &eth_txd1_pb13>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
+	pinctrl-names = "default";
+
+	eth_phy: ethernet-phy@0 {
+		compatible = "ethernet-phy";
+		reg = <0x00>;
+	};
 };
 
 &flash0 {
diff --git a/boards/st/nucleo_f429zi/nucleo_f429zi.yaml b/boards/st/nucleo_f429zi/nucleo_f429zi.yaml
index bec17951950..71b0fcbe4be 100644
--- a/boards/st/nucleo_f429zi/nucleo_f429zi.yaml
+++ b/boards/st/nucleo_f429zi/nucleo_f429zi.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 192
 flash: 2048
 supported:
diff --git a/boards/st/nucleo_f439zi/Kconfig.defconfig b/boards/st/nucleo_f439zi/Kconfig.defconfig
new file mode 100644
index 00000000000..f93177dc263
--- /dev/null
+++ b/boards/st/nucleo_f439zi/Kconfig.defconfig
@@ -0,0 +1,15 @@
+# NUCLEO-144 F439ZI board configuration
+
+# Copyright (c) 2025 Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_NUCLEO_F439ZI
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+endif # NETWORKING
+
+endif # BOARD_NUCLEO_F439ZI
diff --git a/boards/st/nucleo_f439zi/Kconfig.nucleo_f439zi b/boards/st/nucleo_f439zi/Kconfig.nucleo_f439zi
new file mode 100644
index 00000000000..11a3dc5b2ac
--- /dev/null
+++ b/boards/st/nucleo_f439zi/Kconfig.nucleo_f439zi
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NUCLEO_F439ZI
+	select SOC_STM32F439XX
diff --git a/boards/st/nucleo_f439zi/arduino_r3_connector.dtsi b/boards/st/nucleo_f439zi/arduino_r3_connector.dtsi
new file mode 100644
index 00000000000..067c3c6c676
--- /dev/null
+++ b/boards/st/nucleo_f439zi/arduino_r3_connector.dtsi
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2019, Christian Taedcke
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	arduino_header: connector {
+		compatible = "arduino-header-r3";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpioa 3 0>,	/* A0 */
+			   <1 0 &gpioc 0 0>,	/* A1 */
+			   <2 0 &gpioc 3 0>,	/* A2 */
+			   <3 0 &gpiof 3 0>,	/* A3 */
+			   <4 0 &gpiof 5 0>,	/* A4 */
+			   <5 0 &gpiof 10 0>,	/* A5 */
+			   <6 0 &gpiog 9 0>,	/* D0 */
+			   <7 0 &gpiog 14 0>,	/* D1 */
+			   <8 0 &gpiof 15 0>,	/* D2 */
+			   <9 0 &gpioe 13 0>,	/* D3 */
+			   <10 0 &gpiof 14 0>,	/* D4 */
+			   <11 0 &gpioe 11 0>,	/* D5 */
+			   <12 0 &gpioe 9 0>,	/* D6 */
+			   <13 0 &gpiof 13 0>,	/* D7 */
+			   <14 0 &gpiof 12 0>,	/* D8 */
+			   <15 0 &gpiod 15 0>,	/* D9 */
+			   <16 0 &gpiod 14 0>,	/* D10 */
+			   <17 0 &gpioa 7 0>,	/* D11 */
+			   <18 0 &gpioa 6 0>,	/* D12 */
+			   <19 0 &gpioa 5 0>,	/* D13 */
+			   <20 0 &gpiob 9 0>,	/* D14 */
+			   <21 0 &gpiob 8 0>;	/* D15 */
+	};
+};
+
+arduino_i2c: &i2c1 {};
+arduino_spi: &spi1 {};
+arduino_serial: &usart6 {};
diff --git a/boards/st/nucleo_f439zi/board.cmake b/boards/st/nucleo_f439zi/board.cmake
new file mode 100644
index 00000000000..b7761f24ff3
--- /dev/null
+++ b/boards/st/nucleo_f439zi/board.cmake
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# keep first
+board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
+board_runner_args(jlink "--device=STM32F439ZI" "--speed=4000")
+
+# keep first
+include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/st/nucleo_f439zi/board.yml b/boards/st/nucleo_f439zi/board.yml
new file mode 100644
index 00000000000..32428f55018
--- /dev/null
+++ b/boards/st/nucleo_f439zi/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: nucleo_f439zi
+  full_name: Nucleo F439ZI
+  vendor: st
+  socs:
+    - name: stm32f439xx
diff --git a/boards/st/nucleo_f439zi/doc/index.rst b/boards/st/nucleo_f439zi/doc/index.rst
new file mode 100644
index 00000000000..e9e5b154dcc
--- /dev/null
+++ b/boards/st/nucleo_f439zi/doc/index.rst
@@ -0,0 +1,86 @@
+.. zephyr:board:: nucleo_f439zi
+
+Overview
+********
+
+The Nucleo F439ZI board features an ARM Cortex-M4 based STM32F439ZI MCU
+with a wide range of connectivity support and configurations. This SoC
+is basically a clone of the STM32F429ZI with a supplementary hardware
+cryptographic accelerator.
+
+More information about STM32F439ZI can be found here:
+
+- `STM32F439ZI on www.st.com`_
+- `STM32F439 reference manual`_
+- `STM32F439 datasheet`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+The Nucleo F439ZI board includes an ST-LINK/V2-1 embedded debug tool interface.
+
+Flashing
+========
+
+The board is configured to be flashed using west `STM32CubeProgrammer`_ runner,
+so its :ref:`installation <stm32cubeprog-flash-host-tools>` is required.
+
+Alternatively, OpenOCD or JLink can also be used to flash the board using
+the ``--runner`` (or ``-r``) option:
+
+.. code-block:: console
+
+   $ west flash --runner openocd
+   $ west flash --runner jlink
+
+Flashing an application to the Nucleo F439ZI
+--------------------------------------------
+
+Here is an example for the :zephyr:code-sample:`blinky` application.
+
+Run a serial host program to connect with your board:
+
+.. code-block:: console
+
+   $ minicom -D /dev/ttyACM0
+
+Build and flash the application:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: nucleo_f439zi
+   :goals: build flash
+
+You should see user led "LD1" blinking.
+
+Debugging
+=========
+
+You can debug an application in the usual way.  Here is an example for the
+:zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: nucleo_f439zi
+   :maybe-skip-config:
+   :goals: debug
+
+.. target-notes::
+.. _STM32F439ZI on www.st.com:
+   https://www.st.com/en/microcontrollers/stm32f439zi.html
+
+.. _STM32F439 reference manual:
+   https://www.st.com/resource/en/reference_manual/dm00031020.pdf
+
+.. _STM32F439 datasheet:
+   https://www.st.com/resource/en/datasheet/stm32f439zi.pdf
+
+.. _STM32CubeProgrammer:
+   https://www.st.com/en/development-tools/stm32cubeprog.html
diff --git a/boards/st/nucleo_f439zi/nucleo_f439zi.dts b/boards/st/nucleo_f439zi/nucleo_f439zi.dts
new file mode 100644
index 00000000000..7c0ee16ad68
--- /dev/null
+++ b/boards/st/nucleo_f439zi/nucleo_f439zi.dts
@@ -0,0 +1,275 @@
+/*
+ * Copyright (c) 2025 Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/f4/stm32f439Xi.dtsi>
+#include <st/f4/stm32f439z(g-i)tx-pinctrl.dtsi>
+#include "arduino_r3_connector.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "STMicroelectronics STM32F439ZI-NUCLEO board";
+	compatible = "st,stm32f439zi-nucleo";
+
+	chosen {
+		zephyr,console = &usart3;
+		zephyr,shell-uart = &usart3;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,ccm = &ccm0;
+		zephyr,code-partition = &slot0_partition;
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		green_led_1: led_1 {
+			gpios = <&gpiob 0 GPIO_ACTIVE_HIGH>;
+			label = "User LD1";
+		};
+
+		blue_led_1: led_2 {
+			gpios = <&gpiob 7 GPIO_ACTIVE_HIGH>;
+			label = "User LD2";
+		};
+
+		red_led_1: led_3 {
+			gpios = <&gpiob 14 GPIO_ACTIVE_HIGH>;
+			label = "User LD3";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		user_button: button {
+			label = "User";
+			gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	aliases {
+		led0 = &green_led_1;
+		led1 = &blue_led_1;
+		led2 = &red_led_1;
+		sw0 = &user_button;
+		watchdog0 = &iwdg;
+		die-temp0 = &die_temp;
+		volt-sensor0 = &vref;
+		volt-sensor1 = &vbat;
+	};
+};
+
+&clk_lsi {
+	status = "okay";
+};
+
+&clk_hse {
+	hse-bypass;
+	clock-frequency = <DT_FREQ_M(8)>; /* STLink 8MHz clock */
+	status = "okay";
+};
+
+&pll {
+	div-m = <8>;
+	mul-n = <336>;
+	div-p = <2>;
+	div-q = <7>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(168)>; /* highest value to get a precise USB clock */
+	ahb-prescaler = <1>;
+	apb1-prescaler = <4>;
+	apb2-prescaler = <2>;
+};
+
+&adc1 {
+	pinctrl-0 = <&adc1_in0_pa0>;
+	pinctrl-names = "default";
+	st,adc-clock-source = "SYNC";
+	st,adc-prescaler = <2>;
+	status = "okay";
+};
+
+&die_temp {
+	status = "okay";
+};
+
+&dac1 {
+	status = "okay";
+	pinctrl-0 = <&dac_out1_pa4>;
+	pinctrl-names = "default";
+};
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb9>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_scl_pb10 &i2c2_sda_pb11>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&spi1 {
+	pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpiod 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+	status = "okay";
+};
+
+&usart3 {
+	pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+&usart6 {
+	pinctrl-0 = <&usart6_tx_pg14 &usart6_rx_pg9>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+zephyr_udc0: &usbotg_fs {
+	pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&timers1 {
+	st,prescaler = <10000>;
+	status = "okay";
+
+	pwm1: pwm {
+		status = "okay";
+		pinctrl-0 = <&tim1_ch3_pe13>;
+		pinctrl-names = "default";
+	};
+};
+
+&rtc {
+	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x10000000>,
+		 <&rcc STM32_SRC_LSI RTC_SEL(2)>;
+	status = "okay";
+};
+
+&iwdg {
+	status = "okay";
+};
+
+&rng {
+	status = "okay";
+};
+
+&dma2 {
+	status = "okay";
+};
+
+&mac {
+	status = "okay";
+	pinctrl-0 = <&eth_rxd0_pc4
+		     &eth_rxd1_pc5
+		     &eth_ref_clk_pa1
+		     &eth_crs_dv_pa7
+		     &eth_tx_en_pg11
+		     &eth_txd0_pg13
+		     &eth_txd1_pb13>;
+	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
+	pinctrl-names = "default";
+
+	eth_phy: ethernet-phy@0 {
+		compatible = "ethernet-phy";
+		reg = <0x00>;
+	};
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* 32KB for bootloader */
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 DT_SIZE_K(32)>;
+			read-only;
+		};
+
+		/*
+		 * nvs subsystem requires 2 sectors with a max total of 32K
+		 * On F4 series, the only option is to use the following
+		 * partition, which is compatible with mcuboot usage.
+		 * Keep it commented in order it is not used by CI.
+		 *
+		 * storage_partition: partition@8000 {
+		 *	label = "storage";
+		 *	reg = <0x0008000 DT_SIZE_K(32)>;
+		 * };
+		 */
+
+		/* free sector: 64KB
+		 *
+		 * free0_partition: partition@10000 {
+		 *	label = "free-0";
+		 *	reg = <0x00010000 DT_SIZE_K(64)>;
+		 * };
+		 */
+
+		/* application image slot: 896KB */
+		slot0_partition: partition@20000 {
+			label = "image-0";
+			reg = <0x00020000 DT_SIZE_K(896)>;
+		};
+
+		/* free sectors: 4 * 16KB + 64KB
+		 *
+		 * free1_partition: partition@100000 {
+		 *	label = "free-1";
+		 *	reg = <0x00100000 DT_SIZE_K(128)>;
+		 * };
+		 */
+
+		/* backup slot: 768KB */
+		slot1_partition: partition@120000 {
+			label = "image-1";
+			reg = <0x00120000 DT_SIZE_K(768)>;
+		};
+
+		/* free sector: 128KB
+		 *
+		 * free2_partition: partition@1e0000 {
+		 *	label = "free-2";
+		 *	reg = <0x0001e0000 DT_SIZE_K(128)>;
+		 * };
+		 */
+	};
+};
+
+&vref {
+	status = "okay";
+};
+
+&vbat {
+	status = "okay";
+};
diff --git a/boards/st/nucleo_f439zi/nucleo_f439zi.yaml b/boards/st/nucleo_f439zi/nucleo_f439zi.yaml
new file mode 100644
index 00000000000..409e131d99c
--- /dev/null
+++ b/boards/st/nucleo_f439zi/nucleo_f439zi.yaml
@@ -0,0 +1,27 @@
+identifier: nucleo_f439zi
+name: ST Nucleo F439ZI
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 192
+flash: 2048
+supported:
+  - arduino_gpio
+  - arduino_i2c
+  - arduino_spi
+  - netif:eth
+  - i2c
+  - spi
+  - gpio
+  - pwm
+  - counter
+  - usb_device
+  - watchdog
+  - adc
+  - dac
+  - dma
+  - rtc
+  - usbd
+vendor: st
diff --git a/boards/st/nucleo_f439zi/nucleo_f439zi_defconfig b/boards/st/nucleo_f439zi/nucleo_f439zi_defconfig
new file mode 100644
index 00000000000..d03e9b54466
--- /dev/null
+++ b/boards/st/nucleo_f439zi/nucleo_f439zi_defconfig
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable console
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
diff --git a/boards/st/nucleo_f439zi/support/openocd.cfg b/boards/st/nucleo_f439zi/support/openocd.cfg
new file mode 100644
index 00000000000..9073ee6db09
--- /dev/null
+++ b/boards/st/nucleo_f439zi/support/openocd.cfg
@@ -0,0 +1,12 @@
+source [find board/st_nucleo_f4.cfg]
+
+$_TARGETNAME configure -event gdb-attach {
+        echo "Debugger attaching: halting execution"
+        reset halt
+        gdb_breakpoint_override hard
+}
+
+$_TARGETNAME configure -event gdb-detach {
+        echo "Debugger detaching: resuming execution"
+        resume
+}
diff --git a/boards/st/nucleo_f446re/doc/index.rst b/boards/st/nucleo_f446re/doc/index.rst
index 0688c3c6f02..09965db0df0 100644
--- a/boards/st/nucleo_f446re/doc/index.rst
+++ b/boards/st/nucleo_f446re/doc/index.rst
@@ -62,33 +62,7 @@ More information about STM32F446RE can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_f446re board configuration supports the following hardware features:
-
-+-------------+------------+-------------------------------------+
-| Interface   | Controller | Driver/Component                    |
-+=============+============+=====================================+
-| NVIC        | on-chip    | nested vector interrupt controller  |
-+-------------+------------+-------------------------------------+
-| UART        | on-chip    | serial port                         |
-+-------------+------------+-------------------------------------+
-| PINMUX      | on-chip    | pinmux                              |
-+-------------+------------+-------------------------------------+
-| GPIO        | on-chip    | gpio                                |
-+-------------+------------+-------------------------------------+
-| PWM         | on-chip    | pwm                                 |
-+-------------+------------+-------------------------------------+
-| I2C         | on-chip    | i2c                                 |
-+-------------+------------+-------------------------------------+
-| Backup SRAM | on-chip    | Backup SRAM                         |
-+-------------+------------+-------------------------------------+
-| CAN 1/2     | on-chip    | Controller Area Network             |
-+-------------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f446re/nucleo_f446re_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -157,6 +131,8 @@ used with `RS485 CAN Shield`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo F446RE board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_f446re`` board configuration can be built and
diff --git a/boards/st/nucleo_f446re/nucleo_f446re.yaml b/boards/st/nucleo_f446re/nucleo_f446re.yaml
index 9d45982d995..b7e2d714cf4 100644
--- a/boards/st/nucleo_f446re/nucleo_f446re.yaml
+++ b/boards/st/nucleo_f446re/nucleo_f446re.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_gpio
   - arduino_i2c
diff --git a/boards/st/nucleo_f446ze/doc/index.rst b/boards/st/nucleo_f446ze/doc/index.rst
index 852ce5bd99b..e3ebe377ef6 100644
--- a/boards/st/nucleo_f446ze/doc/index.rst
+++ b/boards/st/nucleo_f446ze/doc/index.rst
@@ -67,39 +67,7 @@ More information about STM32F446ZE can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_f446ze board configuration supports the following hardware features:
-
-+-------------+------------+-------------------------------------+
-| Interface   | Controller | Driver/Component                    |
-+=============+============+=====================================+
-| NVIC        | on-chip    | nested vector interrupt controller  |
-+-------------+------------+-------------------------------------+
-| UART        | on-chip    | serial port                         |
-+-------------+------------+-------------------------------------+
-| PINMUX      | on-chip    | pinmux                              |
-+-------------+------------+-------------------------------------+
-| GPIO        | on-chip    | gpio                                |
-+-------------+------------+-------------------------------------+
-| PWM         | on-chip    | pwm                                 |
-+-------------+------------+-------------------------------------+
-| I2C         | on-chip    | i2c                                 |
-+-------------+------------+-------------------------------------+
-| USB         | on-chip    | usb                                 |
-+-------------+------------+-------------------------------------+
-| Backup SRAM | on-chip    | Backup SRAM                         |
-+-------------+------------+-------------------------------------+
-| CAN 1/2     | on-chip    | Controller Area Network             |
-+-------------+------------+-------------------------------------+
-| ADC         | on-chip    | Analog Input                        |
-+-------------+------------+-------------------------------------+
-| DAC         | on-chip    | Analog Output                       |
-+-------------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f446ze/nucleo_f446ze_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -182,6 +150,8 @@ The TX/RX wires are connected with pins 25/27 of CN9 connector.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo F446ZE board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_f446ze`` board configuration can be built and
diff --git a/boards/st/nucleo_f446ze/nucleo_f446ze.yaml b/boards/st/nucleo_f446ze/nucleo_f446ze.yaml
index cf62cdd7712..73e4252613f 100644
--- a/boards/st/nucleo_f446ze/nucleo_f446ze.yaml
+++ b/boards/st/nucleo_f446ze/nucleo_f446ze.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - arduino_gpio
diff --git a/boards/st/nucleo_f722ze/doc/index.rst b/boards/st/nucleo_f722ze/doc/index.rst
index b381f20de4c..8a98d09ee18 100644
--- a/boards/st/nucleo_f722ze/doc/index.rst
+++ b/boards/st/nucleo_f722ze/doc/index.rst
@@ -54,61 +54,7 @@ Nucleo F722ZE provides the following hardware components:
 Supported Features
 ==================
 
-+---------------+------------+-------------------------------+
-| Interface     | Controller | Driver/Component              |
-+===============+============+===============================+
-| NVIC          | on-chip    | arch/arm                      |
-+---------------+------------+-------------------------------+
-| MPU           | on-chip    | arch/arm                      |
-+---------------+------------+-------------------------------+
-| ADC           | on-chip    | adc                           |
-+---------------+------------+-------------------------------+
-| CAN           | on-chip    | can                           |
-+---------------+------------+-------------------------------+
-| USART/UART    | on-chip    | console, serial               |
-+---------------+------------+-------------------------------+
-| TIMER         | on-chip    | counter, pwm, timer           |
-+---------------+------------+-------------------------------+
-| DAC           | on-chip    | dac                           |
-+---------------+------------+-------------------------------+
-| DMA           | on-chip    | dma                           |
-+---------------+------------+-------------------------------+
-| GPIO          | on-chip    | gpio                          |
-+---------------+------------+-------------------------------+
-| HWINFO        | on-chip    | hwinfo                        |
-+---------------+------------+-------------------------------+
-| I2C           | on-chip    | i2c                           |
-+---------------+------------+-------------------------------+
-| EXTI          | on-chip    | interrupt_controller          |
-+---------------+------------+-------------------------------+
-| BACKUP_SRAM   | on-chip    | memory                        |
-+---------------+------------+-------------------------------+
-| QUADSPI       | on-chip    | memory                        |
-+---------------+------------+-------------------------------+
-| PINMUX        | on-chip    | pinctrl                       |
-+---------------+------------+-------------------------------+
-| RCC           | on-chip    | reset                         |
-+---------------+------------+-------------------------------+
-| RTC           | on-chip    | rtc                           |
-+---------------+------------+-------------------------------+
-| DIE_TEMP      | on-chip    | sensor                        |
-+---------------+------------+-------------------------------+
-| VREF          | on-chip    | sensor                        |
-+---------------+------------+-------------------------------+
-| VBAT          | on-chip    | sensor                        |
-+---------------+------------+-------------------------------+
-| SPI           | on-chip    | spi                           |
-+---------------+------------+-------------------------------+
-| USBOTG_HS     | on-chip    | usb                           |
-+---------------+------------+-------------------------------+
-| USBOTG_FS     | on-chip    | usb                           |
-+---------------+------------+-------------------------------+
-| IWDG          | on-chip    | watchdog                      |
-+---------------+------------+-------------------------------+
-| WWDG          | on-chip    | watchdog                      |
-+---------------+------------+-------------------------------+
-| RTC           | on-chip    | rtc                           |
-+---------------+------------+-------------------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -173,6 +119,8 @@ using 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The ``nucleo_f722ze`` can be flashed and debugged in the typical manner.
 The Nucleo F722ZE board includes an ST-LINK V2-1 debugger.
 
diff --git a/boards/st/nucleo_f722ze/nucleo_f722ze.yaml b/boards/st/nucleo_f722ze/nucleo_f722ze.yaml
index 4286f55eca9..4af91c9e44b 100644
--- a/boards/st/nucleo_f722ze/nucleo_f722ze.yaml
+++ b/boards/st/nucleo_f722ze/nucleo_f722ze.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - arduino_gpio
diff --git a/boards/st/nucleo_f746zg/doc/index.rst b/boards/st/nucleo_f746zg/doc/index.rst
index 05b436d99e9..e7865368481 100644
--- a/boards/st/nucleo_f746zg/doc/index.rst
+++ b/boards/st/nucleo_f746zg/doc/index.rst
@@ -81,47 +81,7 @@ Nucleo F746ZG provides the following hardware components:
 Supported Features
 ==================
 
-The Zephyr nucleo_f746zg board configuration supports the following hardware
-features:
-
-+-------------+------------+-------------------------------------+
-| Interface   | Controller | Driver/Component                    |
-+=============+============+=====================================+
-| NVIC        | on-chip    | nested vector interrupt controller  |
-+-------------+------------+-------------------------------------+
-| UART        | on-chip    | serial port                         |
-+-------------+------------+-------------------------------------+
-| PINMUX      | on-chip    | pinmux                              |
-+-------------+------------+-------------------------------------+
-| GPIO        | on-chip    | gpio                                |
-+-------------+------------+-------------------------------------+
-| ETHERNET    | on-chip    | ethernet                            |
-+-------------+------------+-------------------------------------+
-| USB         | on-chip    | usb_device                          |
-+-------------+------------+-------------------------------------+
-| COUNTER     | on-chip    | rtc                                 |
-+-------------+------------+-------------------------------------+
-| I2C         | on-chip    | i2c                                 |
-+-------------+------------+-------------------------------------+
-| PWM         | on-chip    | pwm                                 |
-+-------------+------------+-------------------------------------+
-| SPI         | on-chip    | spi                                 |
-+-------------+------------+-------------------------------------+
-| WATCHDOG    | on-chip    | independent watchdog                |
-+-------------+------------+-------------------------------------+
-| ADC         | on-chip    | ADC Controller                      |
-+-------------+------------+-------------------------------------+
-| DAC         | on-chip    | DAC Controller                      |
-+-------------+------------+-------------------------------------+
-| Backup SRAM | on-chip    | Backup SRAM                         |
-+-------------+------------+-------------------------------------+
-| RTC         | on-chip    | rtc                                 |
-+-------------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f746zg/nucleo_f746zg_defconfig`
+.. zephyr:board-supported-hw::
 
 For more details please refer to `STM32 Nucleo-144 board User Manual`_.
 
@@ -172,6 +132,8 @@ do it by removing ``SB156`` jumper on the back side of the board.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo F746ZG board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_f746zg`` board configuration can be built and
diff --git a/boards/st/nucleo_f746zg/nucleo_f746zg.dts b/boards/st/nucleo_f746zg/nucleo_f746zg.dts
index 65416d66d52..f1df608b817 100644
--- a/boards/st/nucleo_f746zg/nucleo_f746zg.dts
+++ b/boards/st/nucleo_f746zg/nucleo_f746zg.dts
@@ -197,16 +197,27 @@ zephyr_udc0: &usbotg_fs {
 
 &mac {
 	status = "okay";
-	pinctrl-0 = <&eth_mdc_pc1
-		     &eth_rxd0_pc4
+	pinctrl-0 = <&eth_rxd0_pc4
 		     &eth_rxd1_pc5
 		     &eth_ref_clk_pa1
-		     &eth_mdio_pa2
 		     &eth_crs_dv_pa7
 		     &eth_tx_en_pg11
 		     &eth_txd0_pg13
 		     &eth_txd1_pb13>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
+	pinctrl-names = "default";
+
+	eth_phy: ethernet-phy@0 {
+		compatible = "ethernet-phy";
+		reg = <0x00>;
+	};
 };
 
 &backup_sram {
diff --git a/boards/st/nucleo_f746zg/nucleo_f746zg.yaml b/boards/st/nucleo_f746zg/nucleo_f746zg.yaml
index ce8b0322fcd..affa0ccc2df 100644
--- a/boards/st/nucleo_f746zg/nucleo_f746zg.yaml
+++ b/boards/st/nucleo_f746zg/nucleo_f746zg.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 256
 flash: 1024
 supported:
diff --git a/boards/st/nucleo_f756zg/doc/index.rst b/boards/st/nucleo_f756zg/doc/index.rst
index 3b90c688ff8..2de8ce752d1 100644
--- a/boards/st/nucleo_f756zg/doc/index.rst
+++ b/boards/st/nucleo_f756zg/doc/index.rst
@@ -81,35 +81,7 @@ Nucleo F756ZG provides the following hardware components:
 Supported Features
 ==================
 
-The Zephyr nucleo_f756zg board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb_device                          |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f756zg/nucleo_f756zg_defconfig`
+.. zephyr:board-supported-hw::
 
 For more details please refer to `STM32 Nucleo-144 board User Manual`_.
 
@@ -153,6 +125,8 @@ assigned to UART3. Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo F756ZG board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_f756zg`` board configuration can be built and
diff --git a/boards/st/nucleo_f756zg/nucleo_f756zg.dts b/boards/st/nucleo_f756zg/nucleo_f756zg.dts
index 234321842ba..da329479c85 100644
--- a/boards/st/nucleo_f756zg/nucleo_f756zg.dts
+++ b/boards/st/nucleo_f756zg/nucleo_f756zg.dts
@@ -141,18 +141,30 @@ zephyr_udc0: &usbotg_fs {
 
 &mac {
 	status = "okay";
-	pinctrl-0 = <&eth_mdc_pc1
-		     &eth_rxd0_pc4
+	pinctrl-0 = <&eth_rxd0_pc4
 		     &eth_rxd1_pc5
 		     &eth_ref_clk_pa1
-		     &eth_mdio_pa2
 		     &eth_crs_dv_pa7
 		     &eth_tx_en_pg11
 		     &eth_txd0_pg13
 		     &eth_txd1_pb13>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
 };
 
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
+	pinctrl-names = "default";
+
+	eth_phy: ethernet-phy@0 {
+		compatible = "ethernet-phy";
+		reg = <0x00>;
+	};
+};
+
+
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
diff --git a/boards/st/nucleo_f756zg/nucleo_f756zg.yaml b/boards/st/nucleo_f756zg/nucleo_f756zg.yaml
index 4b12d824b3b..8b572e86c47 100644
--- a/boards/st/nucleo_f756zg/nucleo_f756zg.yaml
+++ b/boards/st/nucleo_f756zg/nucleo_f756zg.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 256
 flash: 1024
 supported:
diff --git a/boards/st/nucleo_f767zi/doc/index.rst b/boards/st/nucleo_f767zi/doc/index.rst
index d68ae61592f..4afe4cd84e0 100644
--- a/boards/st/nucleo_f767zi/doc/index.rst
+++ b/boards/st/nucleo_f767zi/doc/index.rst
@@ -81,55 +81,15 @@ Nucleo F767ZI provides the following hardware components:
 Supported Features
 ==================
 
-The Zephyr nucleo_f767zi board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | ethernet (*)                        |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb_device                          |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | DAC Controller                      |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-
-(*) nucleo_f767zi with soc cut-A (Device marking A) has some ethernet
+.. zephyr:board-supported-hw::
+
+.. note::
+    nucleo_f767zi with soc cut-A (Device marking A) has some ethernet
     instability (:github:`26519`).
     Use of cut-Z is advised.
     see restrictions errata:
     https://www.st.com/content/ccc/resource/technical/document/errata_sheet/group0/23/a6/11/0b/30/24/46/a5/DM00257543/files/DM00257543.pdf/jcr:content/translations/en.DM00257543.pdf
 
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_f767zi/nucleo_f767zi_defconfig`
-
 For more details please refer to `STM32 Nucleo-144 board User Manual`_.
 
 Default Zephyr Peripheral Mapping:
@@ -173,6 +133,8 @@ assigned to UART3. Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo F767ZI board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_f767zi`` board configuration can be built and
diff --git a/boards/st/nucleo_f767zi/nucleo_f767zi.dts b/boards/st/nucleo_f767zi/nucleo_f767zi.dts
index c7a113fdfcf..3cc05d175e3 100644
--- a/boards/st/nucleo_f767zi/nucleo_f767zi.dts
+++ b/boards/st/nucleo_f767zi/nucleo_f767zi.dts
@@ -188,16 +188,27 @@ zephyr_udc0: &usbotg_fs {
 
 &mac {
 	status = "okay";
-	pinctrl-0 = <&eth_mdc_pc1
-		     &eth_rxd0_pc4
+	pinctrl-0 = <&eth_rxd0_pc4
 		     &eth_rxd1_pc5
 		     &eth_ref_clk_pa1
-		     &eth_mdio_pa2
 		     &eth_crs_dv_pa7
 		     &eth_tx_en_pg11
 		     &eth_txd0_pg13
 		     &eth_txd1_pb13>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
+	pinctrl-names = "default";
+
+	eth_phy: ethernet-phy@0 {
+		compatible = "ethernet-phy";
+		reg = <0x00>;
+	};
 };
 
 &flash0 {
diff --git a/boards/st/nucleo_f767zi/nucleo_f767zi.yaml b/boards/st/nucleo_f767zi/nucleo_f767zi.yaml
index 1ca2d19993f..d23ca5a3336 100644
--- a/boards/st/nucleo_f767zi/nucleo_f767zi.yaml
+++ b/boards/st/nucleo_f767zi/nucleo_f767zi.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 512
 flash: 2048
 supported:
diff --git a/boards/st/nucleo_g031k8/doc/index.rst b/boards/st/nucleo_g031k8/doc/index.rst
index bf985149d83..cc2cba3f929 100644
--- a/boards/st/nucleo_g031k8/doc/index.rst
+++ b/boards/st/nucleo_g031k8/doc/index.rst
@@ -56,31 +56,7 @@ More information about STM32G031K8 can be found in the
 Supported Features
 ==================
 
-The Zephyr nucleo_g031k8 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c controller                      |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi controller                      |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_g031k8/nucleo_g031k8_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -103,6 +79,8 @@ For more details please refer to `STM32 Nucleo-32 board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo G031K8 board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_g031k8`` board configuration can be built and
diff --git a/boards/st/nucleo_g031k8/nucleo_g031k8.yaml b/boards/st/nucleo_g031k8/nucleo_g031k8.yaml
index 34ea35189ab..afc7f150c30 100644
--- a/boards/st/nucleo_g031k8/nucleo_g031k8.yaml
+++ b/boards/st/nucleo_g031k8/nucleo_g031k8.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/st/nucleo_g070rb/doc/index.rst b/boards/st/nucleo_g070rb/doc/index.rst
index f15d559403c..bb20170372d 100644
--- a/boards/st/nucleo_g070rb/doc/index.rst
+++ b/boards/st/nucleo_g070rb/doc/index.rst
@@ -33,7 +33,6 @@ Nucleo G070RB provides the following hardware components:
   - Arduino* Uno V3 connectivity
   - ST morpho extension pin headers for full access to all STM32 I/Os
 
-- ARM* mbed*
 - On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
 
   - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
@@ -54,11 +53,6 @@ Nucleo G070RB provides the following hardware components:
   - Mass storage
   - Debug port
 
-- Support of wide choice of Integrated Development Environments (IDEs) including:
-
-  - IAR
-  - ARM Keil
-  - GCC-based IDEs
 
 More information about STM32G070RB can be found here:
 
@@ -67,45 +61,7 @@ More information about STM32G070RB can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_g070rb board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | arm memory protection unit          |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_g070rb/nucleo_g070rb_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -136,6 +92,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo G070RB board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_g070rb`` board configuration can be built and
diff --git a/boards/st/nucleo_g070rb/nucleo_g070rb.yaml b/boards/st/nucleo_g070rb/nucleo_g070rb.yaml
index 6cac29d4db1..7aae67d18d2 100644
--- a/boards/st/nucleo_g070rb/nucleo_g070rb.yaml
+++ b/boards/st/nucleo_g070rb/nucleo_g070rb.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 36
 flash: 128
 supported:
diff --git a/boards/st/nucleo_g070rb/st_morpho_connector.dtsi b/boards/st/nucleo_g070rb/st_morpho_connector.dtsi
index e3c04c7ecb0..30d474478f6 100644
--- a/boards/st/nucleo_g070rb/st_morpho_connector.dtsi
+++ b/boards/st/nucleo_g070rb/st_morpho_connector.dtsi
@@ -17,9 +17,9 @@
 			   <ST_MORPHO_L_3 0 &gpioc 12 0>,
 			   <ST_MORPHO_L_4 0 &gpiod 2 0>,
 			   <ST_MORPHO_L_7 0 &gpioa 14 0>,
-			   <ST_MORPHO_L_9 0 &gpiod 0>,
-			   <ST_MORPHO_L_10 0 &gpiod 1>,
-			   <ST_MORPHO_L_11 0 &gpiod 3>,
+			   <ST_MORPHO_L_9 0 &gpiod 0 0>,
+			   <ST_MORPHO_L_10 0 &gpiod 1 0>,
+			   <ST_MORPHO_L_11 0 &gpiod 3 0>,
 			   <ST_MORPHO_L_13 0 &gpioa 13 0>,
 			   <ST_MORPHO_L_15 0 &gpiod 4 0>,
 			   <ST_MORPHO_L_17 0 &gpioa 15 0>,
diff --git a/boards/st/nucleo_g071rb/doc/index.rst b/boards/st/nucleo_g071rb/doc/index.rst
index 0ab38d78118..5e7bca2b457 100644
--- a/boards/st/nucleo_g071rb/doc/index.rst
+++ b/boards/st/nucleo_g071rb/doc/index.rst
@@ -33,7 +33,6 @@ Nucleo G071RB provides the following hardware components:
   - Arduino* Uno V3 connectivity
   - ST morpho extension pin headers for full access to all STM32 I/Os
 
-- ARM* mbed*
 - On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
 
   - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
@@ -54,11 +53,6 @@ Nucleo G071RB provides the following hardware components:
   - Mass storage
   - Debug port
 
-- Support of wide choice of Integrated Development Environments (IDEs) including:
-
-  - IAR
-  - ARM Keil
-  - GCC-based IDEs
 
 More information about STM32G071RB can be found here:
 
@@ -69,49 +63,7 @@ More information about STM32G071RB can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_g071rb board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | arm memory protection unit          |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | dac                                 |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_g071rb/nucleo_g071rb_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -142,6 +94,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo G071RB board includes an ST-LINK/V3 embedded debug tool interface.
 
 Applications for the ``nucleo_g071rb`` board configuration can be built and
diff --git a/boards/st/nucleo_g071rb/nucleo_g071rb.yaml b/boards/st/nucleo_g071rb/nucleo_g071rb.yaml
index 8caf70832cd..756d570914f 100644
--- a/boards/st/nucleo_g071rb/nucleo_g071rb.yaml
+++ b/boards/st/nucleo_g071rb/nucleo_g071rb.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 36
 flash: 128
 supported:
diff --git a/boards/st/nucleo_g071rb/st_morpho_connector.dtsi b/boards/st/nucleo_g071rb/st_morpho_connector.dtsi
index e3c04c7ecb0..30d474478f6 100644
--- a/boards/st/nucleo_g071rb/st_morpho_connector.dtsi
+++ b/boards/st/nucleo_g071rb/st_morpho_connector.dtsi
@@ -17,9 +17,9 @@
 			   <ST_MORPHO_L_3 0 &gpioc 12 0>,
 			   <ST_MORPHO_L_4 0 &gpiod 2 0>,
 			   <ST_MORPHO_L_7 0 &gpioa 14 0>,
-			   <ST_MORPHO_L_9 0 &gpiod 0>,
-			   <ST_MORPHO_L_10 0 &gpiod 1>,
-			   <ST_MORPHO_L_11 0 &gpiod 3>,
+			   <ST_MORPHO_L_9 0 &gpiod 0 0>,
+			   <ST_MORPHO_L_10 0 &gpiod 1 0>,
+			   <ST_MORPHO_L_11 0 &gpiod 3 0>,
 			   <ST_MORPHO_L_13 0 &gpioa 13 0>,
 			   <ST_MORPHO_L_15 0 &gpiod 4 0>,
 			   <ST_MORPHO_L_17 0 &gpioa 15 0>,
diff --git a/boards/st/nucleo_g0b1re/doc/index.rst b/boards/st/nucleo_g0b1re/doc/index.rst
index aa68effb93c..73b3d36034a 100644
--- a/boards/st/nucleo_g0b1re/doc/index.rst
+++ b/boards/st/nucleo_g0b1re/doc/index.rst
@@ -67,47 +67,7 @@ More information about STM32G0B1RE can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_g0b1re board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| MPU       | on-chip    | arm memory protection unit          |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | dac                                 |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-| FDCAN     | on-chip    | CAN controller                      |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_g0b1re/nucleo_g0b1re_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -140,6 +100,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo G0B1RE board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_g0b1re`` board configuration can be built and
diff --git a/boards/st/nucleo_g0b1re/nucleo_g0b1re.yaml b/boards/st/nucleo_g0b1re/nucleo_g0b1re.yaml
index f08da37e760..629da4c0df6 100644
--- a/boards/st/nucleo_g0b1re/nucleo_g0b1re.yaml
+++ b/boards/st/nucleo_g0b1re/nucleo_g0b1re.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 144
 flash: 512
 supported:
diff --git a/boards/st/nucleo_g0b1re/st_morpho_connector.dtsi b/boards/st/nucleo_g0b1re/st_morpho_connector.dtsi
index e3c04c7ecb0..30d474478f6 100644
--- a/boards/st/nucleo_g0b1re/st_morpho_connector.dtsi
+++ b/boards/st/nucleo_g0b1re/st_morpho_connector.dtsi
@@ -17,9 +17,9 @@
 			   <ST_MORPHO_L_3 0 &gpioc 12 0>,
 			   <ST_MORPHO_L_4 0 &gpiod 2 0>,
 			   <ST_MORPHO_L_7 0 &gpioa 14 0>,
-			   <ST_MORPHO_L_9 0 &gpiod 0>,
-			   <ST_MORPHO_L_10 0 &gpiod 1>,
-			   <ST_MORPHO_L_11 0 &gpiod 3>,
+			   <ST_MORPHO_L_9 0 &gpiod 0 0>,
+			   <ST_MORPHO_L_10 0 &gpiod 1 0>,
+			   <ST_MORPHO_L_11 0 &gpiod 3 0>,
 			   <ST_MORPHO_L_13 0 &gpioa 13 0>,
 			   <ST_MORPHO_L_15 0 &gpiod 4 0>,
 			   <ST_MORPHO_L_17 0 &gpioa 15 0>,
diff --git a/boards/st/nucleo_g431kb/board.cmake b/boards/st/nucleo_g431kb/board.cmake
index 00ab7c45ccf..7d054ec941f 100644
--- a/boards/st/nucleo_g431kb/board.cmake
+++ b/boards/st/nucleo_g431kb/board.cmake
@@ -3,8 +3,10 @@
 # keep first
 board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
 board_runner_args(pyocd "--target=stm32g431kbtx")
+board_runner_args(jlink "--device=STM32G431KB" "--speed=4000")
 
 # keep first
 include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/st/nucleo_g431kb/doc/index.rst b/boards/st/nucleo_g431kb/doc/index.rst
index d9400a7b38b..80fc06eb78f 100644
--- a/boards/st/nucleo_g431kb/doc/index.rst
+++ b/boards/st/nucleo_g431kb/doc/index.rst
@@ -30,30 +30,7 @@ More information about STM32G431KB can be found here:
 Supported Features
 ==================
 
-The Zephyr ``nucleo_g431kb`` board target supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_g431kb/nucleo_g431kb_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -95,6 +72,8 @@ low power mode.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo G431KB Board includes an ST-Link/V3 embedded debug tool interface.
 
 Applications for the ``nucleo_g431kb`` board target can be built and
diff --git a/boards/st/nucleo_g431kb/nucleo_g431kb.yaml b/boards/st/nucleo_g431kb/nucleo_g431kb.yaml
index eb396a45f57..833a279f73f 100644
--- a/boards/st/nucleo_g431kb/nucleo_g431kb.yaml
+++ b/boards/st/nucleo_g431kb/nucleo_g431kb.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
 flash: 128
 supported:
diff --git a/boards/st/nucleo_g431rb/board.cmake b/boards/st/nucleo_g431rb/board.cmake
index 7a680ee8d4b..19ba91a4a25 100644
--- a/boards/st/nucleo_g431rb/board.cmake
+++ b/boards/st/nucleo_g431rb/board.cmake
@@ -3,8 +3,10 @@
 # keep first
 board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
 board_runner_args(pyocd "--target=stm32g431rbtx")
+board_runner_args(jlink "--device=STM32G431RB" "--speed=4000")
 
 # keep first
 include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/st/nucleo_g431rb/doc/index.rst b/boards/st/nucleo_g431rb/doc/index.rst
index cebd20cc491..4e6e3d9b770 100644
--- a/boards/st/nucleo_g431rb/doc/index.rst
+++ b/boards/st/nucleo_g431rb/doc/index.rst
@@ -88,38 +88,7 @@ More information about STM32G431RB can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_g431rb board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | dac                                 |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | rng                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_g431rb/nucleo_g431rb_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -177,6 +146,8 @@ low power mode.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo G431RB board includes an ST-LINK/V3E embedded debug tool interface.
 
 Applications for the ``nucleo_g431rb`` board configuration can be built and
diff --git a/boards/st/nucleo_g431rb/nucleo_g431rb.yaml b/boards/st/nucleo_g431rb/nucleo_g431rb.yaml
index 71ca5707ac5..7d1ffe6364a 100644
--- a/boards/st/nucleo_g431rb/nucleo_g431rb.yaml
+++ b/boards/st/nucleo_g431rb/nucleo_g431rb.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
 flash: 128
 supported:
diff --git a/boards/st/nucleo_g474re/board.cmake b/boards/st/nucleo_g474re/board.cmake
index 3c3ffc9e7ff..9e4f74239fe 100644
--- a/boards/st/nucleo_g474re/board.cmake
+++ b/boards/st/nucleo_g474re/board.cmake
@@ -3,8 +3,10 @@
 # keep first
 board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
 board_runner_args(pyocd "--target=stm32g474retx")
+board_runner_args(jlink "--device=STM32G474RE" "--speed=4000")
 
 # keep first
 include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/st/nucleo_g474re/doc/index.rst b/boards/st/nucleo_g474re/doc/index.rst
index 2b61e4b2296..fdcd035c412 100644
--- a/boards/st/nucleo_g474re/doc/index.rst
+++ b/boards/st/nucleo_g474re/doc/index.rst
@@ -88,48 +88,7 @@ More information about STM32G474RE can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_g474re board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | DAC Controller                      |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-| FDCAN1    | on-chip    | CAN controller                      |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_g474re/nucleo_g474re_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -191,6 +150,8 @@ low power mode.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo G474RE board includes an ST-LINK/V3E embedded debug tool interface.
 
 Applications for the ``nucleo_g474re`` board configuration can be built and
diff --git a/boards/st/nucleo_g474re/nucleo_g474re.dts b/boards/st/nucleo_g474re/nucleo_g474re.dts
index a3152661131..a0fe283ba58 100644
--- a/boards/st/nucleo_g474re/nucleo_g474re.dts
+++ b/boards/st/nucleo_g474re/nucleo_g474re.dts
@@ -8,6 +8,7 @@
 #include <st/g4/stm32g474Xe.dtsi>
 #include <st/g4/stm32g474r(b-c-e)tx-pinctrl.dtsi>
 #include "arduino_r3_connector.dtsi"
+#include "st_morpho_connector.dtsi"
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 
 / {
diff --git a/boards/st/nucleo_g474re/nucleo_g474re.yaml b/boards/st/nucleo_g474re/nucleo_g474re.yaml
index 26c4254294f..77cb58a31b0 100644
--- a/boards/st/nucleo_g474re/nucleo_g474re.yaml
+++ b/boards/st/nucleo_g474re/nucleo_g474re.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 512
 supported:
diff --git a/boards/st/nucleo_g474re/st_morpho_connector.dtsi b/boards/st/nucleo_g474re/st_morpho_connector.dtsi
new file mode 100644
index 00000000000..100cda300b7
--- /dev/null
+++ b/boards/st/nucleo_g474re/st_morpho_connector.dtsi
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2025 Thomas Günther
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/gpio/st-morpho-header.h>
+
+/ {
+	st_morpho_header: st-morpho-header {
+		compatible = "st-morpho-header";
+		#gpio-cells = <2>;
+		gpio-map-mask = <ST_MORPHO_PIN_MASK 0x0>;
+		gpio-map-pass-thru = <0x0 GPIO_DT_FLAGS_MASK>;
+		gpio-map = <ST_MORPHO_L_1 0 &gpioc 10 0>,
+			   <ST_MORPHO_L_2 0 &gpioc 11 0>,
+			   <ST_MORPHO_L_3 0 &gpioc 12 0>,
+			   <ST_MORPHO_L_4 0 &gpiod 2 0>,
+			   <ST_MORPHO_L_13 0 &gpioa 13 0>,
+			   <ST_MORPHO_L_15 0 &gpioa 14 0>,
+			   <ST_MORPHO_L_17 0 &gpioa 15 0>,
+			   <ST_MORPHO_L_21 0 &gpiob 7 0>,
+			   <ST_MORPHO_L_23 0 &gpioc 13 0>,
+			   <ST_MORPHO_L_25 0 &gpioc 14 0>,
+			   <ST_MORPHO_L_27 0 &gpioc 15 0>,
+			   <ST_MORPHO_L_28 0 &gpioa 0 0>,
+			   <ST_MORPHO_L_29 0 &gpiof 0 0>,
+			   <ST_MORPHO_L_30 0 &gpioa 1 0>,
+			   <ST_MORPHO_L_31 0 &gpiof 1 0>,
+			   <ST_MORPHO_L_32 0 &gpioa 4 0>,
+			   <ST_MORPHO_L_34 0 &gpiob 0 0>,
+			   <ST_MORPHO_L_35 0 &gpioc 2 0>,
+			   <ST_MORPHO_L_36 0 &gpioc 1 0>,
+			   <ST_MORPHO_L_37 0 &gpioc 3 0>,
+			   <ST_MORPHO_L_38 0 &gpioc 0 0>,
+			   <ST_MORPHO_R_1 0 &gpioc 9 0>,
+			   <ST_MORPHO_R_2 0 &gpioc 8 0>,
+			   <ST_MORPHO_R_3 0 &gpiob 8 0>,
+			   <ST_MORPHO_R_4 0 &gpioc 6 0>,
+			   <ST_MORPHO_R_5 0 &gpiob 9 0>,
+			   <ST_MORPHO_R_6 0 &gpioc 5 0>,
+			   <ST_MORPHO_R_11 0 &gpioa 5 0>,
+			   <ST_MORPHO_R_12 0 &gpioa 12 0>,
+			   <ST_MORPHO_R_13 0 &gpioa 6 0>,
+			   <ST_MORPHO_R_14 0 &gpioa 11 0>,
+			   <ST_MORPHO_R_15 0 &gpioa 7 0>,
+			   <ST_MORPHO_R_16 0 &gpiob 12 0>,
+			   <ST_MORPHO_R_17 0 &gpiob 6 0>,
+			   <ST_MORPHO_R_18 0 &gpiob 11 0>,
+			   <ST_MORPHO_R_19 0 &gpioc 7 0>,
+			   <ST_MORPHO_R_21 0 &gpioa 9 0>,
+			   <ST_MORPHO_R_22 0 &gpiob 2 0>,
+			   <ST_MORPHO_R_23 0 &gpioa 8 0>,
+			   <ST_MORPHO_R_24 0 &gpiob 1 0>,
+			   <ST_MORPHO_R_25 0 &gpiob 10 0>,
+			   <ST_MORPHO_R_26 0 &gpiob 15 0>,
+			   <ST_MORPHO_R_27 0 &gpiob 4 0>,
+			   <ST_MORPHO_R_28 0 &gpiob 14 0>,
+			   <ST_MORPHO_R_29 0 &gpiob 5 0>,
+			   <ST_MORPHO_R_30 0 &gpiob 13 0>,
+			   <ST_MORPHO_R_31 0 &gpiob 3 0>,
+			   <ST_MORPHO_R_33 0 &gpioa 10 0>,
+			   <ST_MORPHO_R_34 0 &gpioc 4 0>,
+			   <ST_MORPHO_R_35 0 &gpioa 2 0>,
+			   <ST_MORPHO_R_37 0 &gpioa 3 0>;
+	};
+};
diff --git a/boards/st/nucleo_h503rb/doc/index.rst b/boards/st/nucleo_h503rb/doc/index.rst
index 2be64f7e95a..0ac6e91bb30 100644
--- a/boards/st/nucleo_h503rb/doc/index.rst
+++ b/boards/st/nucleo_h503rb/doc/index.rst
@@ -115,37 +115,7 @@ More information about STM32H533RE can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_h503rb board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c bus                             |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| BKP SRAM  | on-chip    | Backup SRAM                         |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig and dts files:
-
-  - :zephyr_file:`boards/st/nucleo_h503rb/nucleo_h503rb_defconfig`
-  - :zephyr_file:`boards/st/nucleo_h503rb/nucleo_h503rb.dts`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -187,6 +157,8 @@ VBAT can be provided via the left ST Morpho connector's pin 33.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo-H503RB board includes an ST-LINK/V3EC embedded debug tool interface.
 This probe allows to flash the board using various tools.
 
@@ -199,7 +171,7 @@ OpenOCD Support
 
 For now, openocd support  for stm32h5 is not available on upstream OpenOCD.
 You can check `OpenOCD official Github mirror`_.
-In order to use it though, you should clone from the cutomized
+In order to use it though, you should clone from the customized
 `STMicroelectronics OpenOCD Github`_ and compile it following usual README guidelines.
 Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in
 :zephyr_file:`boards/st/nucleo_h563zi/board.cmake` to point the build
diff --git a/boards/st/nucleo_h503rb/nucleo_h503rb.dts b/boards/st/nucleo_h503rb/nucleo_h503rb.dts
index 46eb394c178..f9576eea88e 100644
--- a/boards/st/nucleo_h503rb/nucleo_h503rb.dts
+++ b/boards/st/nucleo_h503rb/nucleo_h503rb.dts
@@ -114,3 +114,9 @@
 	clock-frequency = <I2C_BITRATE_FAST>;
 	status = "okay";
 };
+
+zephyr_udc0: &usb {
+	pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/boards/st/nucleo_h503rb/nucleo_h503rb.yaml b/boards/st/nucleo_h503rb/nucleo_h503rb.yaml
index 355591f3b79..43ef6d17539 100644
--- a/boards/st/nucleo_h503rb/nucleo_h503rb.yaml
+++ b/boards/st/nucleo_h503rb/nucleo_h503rb.yaml
@@ -14,4 +14,5 @@ supported:
   - uart
   - i2c
   - watchdog
+  - usb_device
 vendor: st
diff --git a/boards/st/nucleo_h533re/doc/index.rst b/boards/st/nucleo_h533re/doc/index.rst
index 986cda88c35..6a290a41b92 100644
--- a/boards/st/nucleo_h533re/doc/index.rst
+++ b/boards/st/nucleo_h533re/doc/index.rst
@@ -139,47 +139,7 @@ More information about STM32H533RE can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_h533re board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | PWM                                 |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | Real Time Clock                     |
-+-----------+------------+-------------------------------------+
-| BKP SRAM  | on-chip    | Backup SRAM                         |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB full-speed host/device bus      |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig and dts files:
-
-- Secure target:
-
-  - :zephyr_file:`boards/st/nucleo_h533re/nucleo_h533re_defconfig`
-  - :zephyr_file:`boards/st/nucleo_h533re/nucleo_h533re.dts`
+.. zephyr:board-supported-hw::
 
 Zephyr board options
 ====================
@@ -235,6 +195,8 @@ VBAT can be provided via the left ST Morpho connector's pin 33.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo H533RE board includes an ST-LINK/V3EC embedded debug tool interface.
 This probe allows to flash the board using various tools.
 
@@ -247,7 +209,7 @@ OpenOCD Support
 
 For now, openocd support  for stm32h5 is not available on upstream OpenOCD.
 You can check `OpenOCD official Github mirror`_.
-In order to use it though, you should clone from the cutomized
+In order to use it though, you should clone from the customized
 `STMicroelectronics OpenOCD Github`_ and compile it following usual README guidelines.
 Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in
 :zephyr_file:`boards/st/nucleo_h533re/board.cmake` to point the build
diff --git a/boards/st/nucleo_h563zi/doc/index.rst b/boards/st/nucleo_h563zi/doc/index.rst
index da88685959c..1adc48f7fae 100644
--- a/boards/st/nucleo_h563zi/doc/index.rst
+++ b/boards/st/nucleo_h563zi/doc/index.rst
@@ -136,71 +136,7 @@ More information about STM32H563ZI can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_h563zi board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| BKP SRAM  | on-chip    | Backup SRAM                         |
-+-----------+------------+-------------------------------------+
-| CAN/CANFD | on-chip    | CAN                                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | DAC Controller                      |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | PWM                                 |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | Real Time Clock                     |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi bus                             |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c bus                             |
-+-----------+------------+-------------------------------------+
-| I3C       | on-chip    | i3c bus                             |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB full-speed host/device bus      |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig and dts files:
-
-- Secure target:
-
-  - :zephyr_file:`boards/st/nucleo_h563zi/nucleo_h563zi_defconfig`
-  - :zephyr_file:`boards/st/nucleo_h563zi/nucleo_h563zi.dts`
-
-Zephyr board options
-====================
-
-The STM32H563 is an SoC with Cortex-M33 architecture. Zephyr provides support
-for building for Secure firmware.
-
-The BOARD options are summarized below:
-
-+----------------------+-----------------------------------------------+
-|   BOARD              | Description                                   |
-+======================+===============================================+
-| nucleo_h563zi        | For building Secure firmware                  |
-+----------------------+-----------------------------------------------+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -249,6 +185,8 @@ VBAT can be provided via the left ST Morpho connector's pin 33.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo H563ZI board includes an ST-LINK/V3EC embedded debug tool interface.
 This probe allows to flash the board using various tools.
 
@@ -261,7 +199,7 @@ OpenOCD Support
 
 For now, openocd support  for stm32h5 is not available on upstream OpenOCD.
 You can check `OpenOCD official Github mirror`_.
-In order to use it though, you should clone from the cutomized
+In order to use it though, you should clone from the customized
 `STMicroelectronics OpenOCD Github`_ and compile it following usual README guidelines.
 Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in
 :zephyr_file:`boards/st/nucleo_h563zi/board.cmake` to point the build
diff --git a/boards/st/nucleo_h563zi/nucleo_h563zi.dts b/boards/st/nucleo_h563zi/nucleo_h563zi.dts
index 8acb70d0e6c..add1ea518db 100644
--- a/boards/st/nucleo_h563zi/nucleo_h563zi.dts
+++ b/boards/st/nucleo_h563zi/nucleo_h563zi.dts
@@ -49,6 +49,8 @@
 		     &eth_txd0_pg13
 		     &eth_txd1_pb15>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
 };
 
 &mdio {
@@ -56,9 +58,8 @@
 	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
 	pinctrl-names = "default";
 
-	ethernet-phy@0 {
+	eth_phy: ethernet-phy@0 {
 		compatible = "ethernet-phy";
 		reg = <0x00>;
-		status = "okay";
 	};
 };
diff --git a/boards/st/nucleo_h723zg/doc/index.rst b/boards/st/nucleo_h723zg/doc/index.rst
index 6cd0dc6c568..981228ca8ca 100644
--- a/boards/st/nucleo_h723zg/doc/index.rst
+++ b/boards/st/nucleo_h723zg/doc/index.rst
@@ -80,43 +80,7 @@ Nucleo H723ZG provides the following hardware components:
 Supported Features
 ==================
 
-The Zephyr nucleo_h723zg board configuration supports the following hardware
-features:
-
-+-------------+------------+-------------------------------------+
-| Interface   | Controller | Driver/Component                    |
-+=============+============+=====================================+
-| NVIC        | on-chip    | nested vector interrupt controller  |
-+-------------+------------+-------------------------------------+
-| UART        | on-chip    | serial port                         |
-+-------------+------------+-------------------------------------+
-| PINMUX      | on-chip    | pinmux                              |
-+-------------+------------+-------------------------------------+
-| GPIO        | on-chip    | gpio                                |
-+-------------+------------+-------------------------------------+
-| RTC         | on-chip    | counter                             |
-+-------------+------------+-------------------------------------+
-| I2C         | on-chip    | i2c                                 |
-+-------------+------------+-------------------------------------+
-| SPI         | on-chip    | spi                                 |
-+-------------+------------+-------------------------------------+
-| PWM         | on-chip    | pwm                                 |
-+-------------+------------+-------------------------------------+
-| ETHERNET    | on-chip    | ethernet                            |
-+-------------+------------+-------------------------------------+
-| RNG         | on-chip    | True Random number generator        |
-+-------------+------------+-------------------------------------+
-| Backup SRAM | on-chip    | Backup SRAM                         |
-+-------------+------------+-------------------------------------+
-| RTC         | on-chip    | rtc                                 |
-+-------------+------------+-------------------------------------+
-| FDCAN1      | on-chip    | CAN-FD Controller                   |
-+-------------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig files:
-:zephyr_file:`boards/st/nucleo_h723zg/nucleo_h723zg_defconfig`
+.. zephyr:board-supported-hw::
 
 For more details please refer to `STM32 Nucleo-144 board User Manual`_.
 
@@ -164,6 +128,8 @@ connected to pins PD0 (RX) and PD1 (TX).
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo H723ZG board includes an ST-LINK/V3 embedded debug tool interface.
 
 .. note::
diff --git a/boards/st/nucleo_h723zg/nucleo_h723zg.dts b/boards/st/nucleo_h723zg/nucleo_h723zg.dts
index 72fc5b7f092..8c49c833e71 100644
--- a/boards/st/nucleo_h723zg/nucleo_h723zg.dts
+++ b/boards/st/nucleo_h723zg/nucleo_h723zg.dts
@@ -178,6 +178,8 @@
 		     &eth_txd0_pg13
 		     &eth_txd1_pb13>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
 };
 
 &mdio {
@@ -185,10 +187,9 @@
 	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
 	pinctrl-names = "default";
 
-	phy: ethernet-phy@0 {
+	eth_phy: ethernet-phy@0 {
 		compatible = "ethernet-phy";
 		reg = <0>;
-		status = "okay";
 	};
 };
 
diff --git a/boards/st/nucleo_h723zg/nucleo_h723zg.yaml b/boards/st/nucleo_h723zg/nucleo_h723zg.yaml
index 66161b5b9ff..9ad2b83ba52 100644
--- a/boards/st/nucleo_h723zg/nucleo_h723zg.yaml
+++ b/boards/st/nucleo_h723zg/nucleo_h723zg.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 372
 flash: 1024
 supported:
diff --git a/boards/st/nucleo_h743zi/doc/index.rst b/boards/st/nucleo_h743zi/doc/index.rst
index cb6e58b3b29..2f8008a66b5 100644
--- a/boards/st/nucleo_h743zi/doc/index.rst
+++ b/boards/st/nucleo_h743zi/doc/index.rst
@@ -82,53 +82,7 @@ Nucleo H743ZI provides the following hardware components:
 Supported Features
 ==================
 
-The Zephyr nucleo_h743zi board configuration supports the following hardware
-features:
-
-+-------------+------------+-------------------------------------+
-| Interface   | Controller | Driver/Component                    |
-+=============+============+=====================================+
-| NVIC        | on-chip    | nested vector interrupt controller  |
-+-------------+------------+-------------------------------------+
-| UART        | on-chip    | serial port                         |
-+-------------+------------+-------------------------------------+
-| PINMUX      | on-chip    | pinmux                              |
-+-------------+------------+-------------------------------------+
-| GPIO        | on-chip    | gpio                                |
-+-------------+------------+-------------------------------------+
-| RTC         | on-chip    | counter                             |
-+-------------+------------+-------------------------------------+
-| I2C         | on-chip    | i2c                                 |
-+-------------+------------+-------------------------------------+
-| PWM         | on-chip    | pwm                                 |
-+-------------+------------+-------------------------------------+
-| ADC         | on-chip    | adc                                 |
-+-------------+------------+-------------------------------------+
-| DAC         | on-chip    | DAC Controller                      |
-+-------------+------------+-------------------------------------+
-| RNG         | on-chip    | True Random number generator        |
-+-------------+------------+-------------------------------------+
-| ETHERNET    | on-chip    | ethernet                            |
-+-------------+------------+-------------------------------------+
-| SPI         | on-chip    | spi                                 |
-+-------------+------------+-------------------------------------+
-| Backup SRAM | on-chip    | Backup SRAM                         |
-+-------------+------------+-------------------------------------+
-| WATCHDOG    | on-chip    | independent watchdog                |
-+-------------+------------+-------------------------------------+
-| USB         | on-chip    | usb_device                          |
-+-------------+------------+-------------------------------------+
-| CAN/CANFD   | on-chip    | canbus                              |
-+-------------+------------+-------------------------------------+
-| die-temp    | on-chip    | die temperature sensor              |
-+-------------+------------+-------------------------------------+
-| RTC         | on-chip    | rtc                                 |
-+-------------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_h743zi/nucleo_h743zi_defconfig`
+.. zephyr:board-supported-hw::
 
 For more details please refer to `STM32 Nucleo-144 board User Manual`_.
 
@@ -177,6 +131,8 @@ Requires an external CAN or CANFD transceiver.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo H743ZI board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_h743zi`` board configuration can be built and
diff --git a/boards/st/nucleo_h743zi/nucleo_h743zi.dts b/boards/st/nucleo_h743zi/nucleo_h743zi.dts
index cd47bf9794c..e774b728c21 100644
--- a/boards/st/nucleo_h743zi/nucleo_h743zi.dts
+++ b/boards/st/nucleo_h743zi/nucleo_h743zi.dts
@@ -203,6 +203,8 @@ zephyr_udc0: &usbotg_fs {
 		     &eth_txd0_pg13
 		     &eth_txd1_pb13>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
 };
 
 &mdio {
@@ -210,10 +212,9 @@ zephyr_udc0: &usbotg_fs {
 	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
 	pinctrl-names = "default";
 
-	ethernet-phy@0 {
+	eth_phy: ethernet-phy@0 {
 		compatible = "ethernet-phy";
 		reg = <0x00>;
-		status = "okay";
 	};
 };
 
diff --git a/boards/st/nucleo_h743zi/nucleo_h743zi.yaml b/boards/st/nucleo_h743zi/nucleo_h743zi.yaml
index 8a315b337f5..e76eb486524 100644
--- a/boards/st/nucleo_h743zi/nucleo_h743zi.yaml
+++ b/boards/st/nucleo_h743zi/nucleo_h743zi.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 512
 flash: 2048
 supported:
diff --git a/boards/st/nucleo_h745zi_q/doc/index.rst b/boards/st/nucleo_h745zi_q/doc/index.rst
index 39a74a81ab7..8cb4d3ae78a 100644
--- a/boards/st/nucleo_h745zi_q/doc/index.rst
+++ b/boards/st/nucleo_h745zi_q/doc/index.rst
@@ -84,42 +84,7 @@ Nucleo H745ZI-Q provides the following hardware components:
 Supported Features
 ==================
 
-The Zephyr nucleo_h745zi_q board configuration supports the following hardware
-features:
-
-+-------------+------------+-------------------------------------+
-| Interface   | Controller | Driver/Component                    |
-+=============+============+=====================================+
-| NVIC        | on-chip    | nested vector interrupt controller  |
-+-------------+------------+-------------------------------------+
-| UART        | on-chip    | serial port                         |
-+-------------+------------+-------------------------------------+
-| PINMUX      | on-chip    | pinmux                              |
-+-------------+------------+-------------------------------------+
-| GPIO        | on-chip    | gpio                                |
-+-------------+------------+-------------------------------------+
-| RTC         | on-chip    | counter                             |
-+-------------+------------+-------------------------------------+
-| I2C         | on-chip    | i2c                                 |
-+-------------+------------+-------------------------------------+
-| PWM         | on-chip    | pwm                                 |
-+-------------+------------+-------------------------------------+
-| ETHERNET    | on-chip    | ethernet                            |
-+-------------+------------+-------------------------------------+
-| RNG         | on-chip    | True Random number generator        |
-+-------------+------------+-------------------------------------+
-| USB OTG FS  | on-chip    | USB device                          |
-+-------------+------------+-------------------------------------+
-| SPI         | on-chip    | spi                                 |
-+-------------+------------+-------------------------------------+
-| FDCAN       | on-chip    | CAN-FD Control Area Network         |
-+-------------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration per core can be found in the defconfig files:
-:zephyr_file:`boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7_defconfig` and
-:zephyr_file:`boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4_defconfig`
+.. zephyr:board-supported-hw::
 
 For more details please refer to `STM32 Nucleo-144 board User Manual`_.
 
@@ -168,6 +133,8 @@ two cores. This is done in 3 ways:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo H745ZI-Q board includes an ST-LINK/V3 embedded debug tool interface.
 
 Applications for the ``nucleo_h745zi_q`` board should be built per core target,
diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.yaml b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.yaml
index b17c6d7963b..0cfd777c0c3 100644
--- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.yaml
+++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m4.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 288
 flash: 1024
 supported:
diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts
index c79712968e1..bca10943e9c 100644
--- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts
+++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.dts
@@ -115,6 +115,8 @@
 		     &eth_txd0_pg13
 		     &eth_txd1_pb13>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
 };
 
 &mdio {
@@ -122,10 +124,9 @@
 	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
 	pinctrl-names = "default";
 
-	ethernet-phy@0 {
+	eth_phy: ethernet-phy@0 {
 		compatible = "ethernet-phy";
 		reg = <0x00>;
-		status = "okay";
 	};
 };
 
diff --git a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml
index 259cd29438b..d11a42ae211 100644
--- a/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml
+++ b/boards/st/nucleo_h745zi_q/nucleo_h745zi_q_stm32h745xx_m7.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 512
 flash: 1024
 supported:
diff --git a/boards/st/nucleo_h753zi/doc/index.rst b/boards/st/nucleo_h753zi/doc/index.rst
index a6b8dcf0bf6..fe99931c23c 100644
--- a/boards/st/nucleo_h753zi/doc/index.rst
+++ b/boards/st/nucleo_h753zi/doc/index.rst
@@ -84,43 +84,7 @@ Nucleo H753ZI provides the following hardware components:
 Supported Features
 ==================
 
-The Zephyr nucleo_h753zi board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb_device                          |
-+-----------+------------+-------------------------------------+
-| CAN/CANFD | on-chip    | canbus                              |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_h753zi/nucleo_h753zi_defconfig`
+.. zephyr:board-supported-hw::
 
 For more details please refer to `STM32 Nucleo-144 board User Manual`_.
 
@@ -162,6 +126,8 @@ Requires an external CAN or CANFD transceiver.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo H753ZI board includes an ST-LINK/V3 embedded debug tool interface.
 
 Applications for the ``nucleo_h753zi`` board configuration can be built and
diff --git a/boards/st/nucleo_h753zi/nucleo_h753zi.dts b/boards/st/nucleo_h753zi/nucleo_h753zi.dts
index 83ee70c171d..e411028579b 100644
--- a/boards/st/nucleo_h753zi/nucleo_h753zi.dts
+++ b/boards/st/nucleo_h753zi/nucleo_h753zi.dts
@@ -11,7 +11,7 @@
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 
 / {
-	model = "STMicroelectronics STM32H743ZI-NUCLEO board";
+	model = "STMicroelectronics STM32H753ZI-NUCLEO board";
 	compatible = "st,stm32h753zi-nucleo";
 
 	chosen {
@@ -182,6 +182,8 @@ zephyr_udc0: &usbotg_fs {
 		     &eth_txd0_pg13
 		     &eth_txd1_pb13>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
 };
 
 &mdio {
@@ -189,10 +191,9 @@ zephyr_udc0: &usbotg_fs {
 	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
 	pinctrl-names = "default";
 
-	ethernet-phy@0 {
+	eth_phy: ethernet-phy@0 {
 		compatible = "ethernet-phy";
 		reg = <0x00>;
-		status = "okay";
 	};
 };
 
diff --git a/boards/st/nucleo_h753zi/nucleo_h753zi.yaml b/boards/st/nucleo_h753zi/nucleo_h753zi.yaml
index 7bca456c26e..9574f9fe75e 100644
--- a/boards/st/nucleo_h753zi/nucleo_h753zi.yaml
+++ b/boards/st/nucleo_h753zi/nucleo_h753zi.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 512
 flash: 2048
 supported:
diff --git a/boards/st/nucleo_h755zi_q/doc/index.rst b/boards/st/nucleo_h755zi_q/doc/index.rst
index cc29afb0009..9b26e8aea79 100644
--- a/boards/st/nucleo_h755zi_q/doc/index.rst
+++ b/boards/st/nucleo_h755zi_q/doc/index.rst
@@ -77,40 +77,9 @@ Nucleo H755ZI-Q provides the following hardware components:
 Supported Features
 ==================
 
-The Zephyr nucleo_h755zi_q board configuration supports the following hardware
-features:
-
-+-------------+------------+-------------------------------------+
-| Interface   | Controller | Driver/Component                    |
-+=============+============+=====================================+
-| NVIC        | on-chip    | nested vector interrupt controller  |
-+-------------+------------+-------------------------------------+
-| UART/USART  | on-chip    | serial port                         |
-+-------------+------------+-------------------------------------+
-| PINMUX      | on-chip    | pinmux                              |
-+-------------+------------+-------------------------------------+
-| GPIO        | on-chip    | gpio                                |
-+-------------+------------+-------------------------------------+
-| RTC         | on-chip    | counter                             |
-+-------------+------------+-------------------------------------+
-| I2C         | on-chip    | i2c                                 |
-+-------------+------------+-------------------------------------+
-| PWM         | on-chip    | pwm                                 |
-+-------------+------------+-------------------------------------+
-| ETHERNET    | on-chip    | ethernet                            |
-+-------------+------------+-------------------------------------+
-| RNG         | on-chip    | True Random number generator        |
-+-------------+------------+-------------------------------------+
-| USB OTG FS  | on-chip    | USB device                          |
-+-------------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration per core can be found in the defconfig files:
-:zephyr_file:`boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7_defconfig` and
-:zephyr_file:`boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m4_defconfig`
-
-For mode details please refer to `STM32 Nucleo-144 board User Manual`_.
+.. zephyr:board-supported-hw::
+
+For more details please refer to `STM32 Nucleo-144 board User Manual`_.
 
 Default Zephyr Peripheral Mapping:
 ----------------------------------
@@ -124,6 +93,7 @@ and a ST morpho connector. Board is configured as follows:
 - LD2 : PE1
 - LD3 : PB14
 - I2C : PB8, PB9
+- CAN/CANFD : PD0, PD1
 
 System Clock
 ------------
@@ -138,6 +108,11 @@ Serial Port
 Nucleo H755ZI-Q board has 4 UARTs and 4 USARTs. The Zephyr console output is
 assigned to USART3. Default settings are 115200 8N1.
 
+CAN, CANFD
+----------
+
+Requires an external CAN or CANFD transceiver.
+
 Resources sharing
 -----------------
 
@@ -156,6 +131,8 @@ two cores. This is done in 3 ways:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo H755ZI-Q board includes an ST-LINK/V3 embedded debug tool interface.
 
 Applications for the ``nucleo_h755zi_q`` board should be built per core target,
diff --git a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.dts b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.dts
index d565297ebcb..bda0b08c274 100644
--- a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.dts
+++ b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.dts
@@ -26,6 +26,7 @@
 		zephyr,dtcm = &dtcm;
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
+		zephyr,canbus = &fdcan1;
 	};
 
 	pwmleds {
@@ -68,6 +69,24 @@
 	status = "okay";
 };
 
+&pll2 {
+	div-m = <4>;
+	mul-n = <120>;
+	div-p = <2>;
+	div-q = <3>; /* gives 80MHz to the FDCAN */
+	div-r = <2>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&fdcan1 {
+	clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000100>,
+		 <&rcc STM32_SRC_PLL2_Q FDCAN_SEL(2)>;
+	pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_pd1>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &rcc {
 	clocks = <&pll>;
 	clock-frequency = <DT_FREQ_M(480)>;
@@ -114,6 +133,8 @@
 		     &eth_txd0_pg13
 		     &eth_txd1_pb13>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
 };
 
 &mdio {
@@ -121,10 +142,9 @@
 	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
 	pinctrl-names = "default";
 
-	ethernet-phy@0 {
+	eth_phy: ethernet-phy@0 {
 		compatible = "ethernet-phy";
 		reg = <0x00>;
-		status = "okay";
 	};
 };
 
diff --git a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.yaml b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.yaml
index 63739dff138..0865ea54985 100644
--- a/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.yaml
+++ b/boards/st/nucleo_h755zi_q/nucleo_h755zi_q_stm32h755xx_m7.yaml
@@ -17,4 +17,5 @@ supported:
   - pwm
   - netif:eth
   - usb_device
+  - can
 vendor: st
diff --git a/boards/st/nucleo_h755zi_q/support/openocd.cfg b/boards/st/nucleo_h755zi_q/support/openocd.cfg
index 719125ff149..4635f852bce 100644
--- a/boards/st/nucleo_h755zi_q/support/openocd.cfg
+++ b/boards/st/nucleo_h755zi_q/support/openocd.cfg
@@ -4,8 +4,8 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-# Borrow the nucleo_h745zi openocd configuration as no config exists for the h755 yet.
-source [find board/st_nucleo_h745zi.cfg]
+# Borrow the stm32h745i-disco openocd configuration as no config exists for the h755 yet.
+source [find board/stm32h745i-disco.cfg]
 
 # Use connect_assert_srst here to be able to program
 # even when core is in sleep mode
diff --git a/boards/st/nucleo_h7a3zi_q/doc/index.rst b/boards/st/nucleo_h7a3zi_q/doc/index.rst
index e823191e625..5a251da92fd 100644
--- a/boards/st/nucleo_h7a3zi_q/doc/index.rst
+++ b/boards/st/nucleo_h7a3zi_q/doc/index.rst
@@ -78,37 +78,7 @@ Nucleo H7A3ZI-Q provides the following hardware components:
 Supported Features
 ==================
 
-The Zephyr nucleo_h7a3zi_q board configuration supports the following hardware
-features:
-
-+-------------+------------+------------------------------------+
-| Interface   | Controller | Driver/Component                   |
-+=============+============+====================================+
-| NVIC        | on-chip    | nested vector interrupt controller |
-+-------------+------------+------------------------------------+
-| UART        | on-chip    | serial port                        |
-+-------------+------------+------------------------------------+
-| PINMUX      | on-chip    | pinmux                             |
-+-------------+------------+------------------------------------+
-| GPIO        | on-chip    | gpio                               |
-+-------------+------------+------------------------------------+
-| PWM         | on-chip    | pwm                                |
-+-------------+------------+------------------------------------+
-| ADC         | on-chip    | adc                                |
-+-------------+------------+------------------------------------+
-| Backup SRAM | on-chip    | Backup SRAM                        |
-+-------------+------------+------------------------------------+
-| USB OTG HS  | on-chip    | USB device                         |
-+-------------+------------+------------------------------------+
-| RNG         | on-chip    | True Random number generator       |
-+-------------+------------+------------------------------------+
-
-
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q_defconfig`
+.. zephyr:board-supported-hw::
 
 For more details please refer to `STM32 Nucleo-144 board User Manual`_.
 
@@ -141,6 +111,8 @@ assigned to USART3. Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo H7A3ZI-Q board includes an ST-LINK/V3E embedded debug tool interface.
 
 Applications for the ``nucleo_h7a3zi_q`` board configuration can be built and
diff --git a/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.yaml b/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.yaml
index 65cd30b3e0b..34a554f3b7a 100644
--- a/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.yaml
+++ b/boards/st/nucleo_h7a3zi_q/nucleo_h7a3zi_q.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 1280
 flash: 2048
 supported:
diff --git a/boards/st/nucleo_h7s3l8/doc/index.rst b/boards/st/nucleo_h7s3l8/doc/index.rst
index e869bcbe9ca..0a9a5147811 100644
--- a/boards/st/nucleo_h7s3l8/doc/index.rst
+++ b/boards/st/nucleo_h7s3l8/doc/index.rst
@@ -1,7 +1,4 @@
-.. _nucleo_h7s3l8_board:
-
-ST Nucleo H7S3L8
-################
+.. zephyr:board:: nucleo_h7s3l8
 
 Overview
 ********
@@ -38,11 +35,6 @@ Key Features
 - On-board ST-LINK/V3 debugger/programmer with USB re-enumeration
 - capability: mass storage, virtual COM port and debug port
 
-
-.. image:: img/nucleo_h7s3l8.webp
-   :align: center
-   :alt: Nucleo H7S3L8
-
 More information about the board can be found at the `Nucleo H7S3L8 website`_.
 
 Hardware
@@ -156,39 +148,7 @@ More information about STM32H7S3 can be found here:
 Supported Features
 ==================
 
-The Zephyr ``nucleo_h7s3l8`` board target supports the following hardware
-features:
-
-+-------------+------------+-------------------------------------+
-| Interface   | Controller | Driver/Component                    |
-+=============+============+=====================================+
-| NVIC        | on-chip    | nested vector interrupt controller  |
-+-------------+------------+-------------------------------------+
-| UART        | on-chip    | serial port                         |
-+-------------+------------+-------------------------------------+
-| PINMUX      | on-chip    | pinmux                              |
-+-------------+------------+-------------------------------------+
-| GPIO        | on-chip    | gpio                                |
-+-------------+------------+-------------------------------------+
-| RTC         | on-chip    | counter                             |
-+-------------+------------+-------------------------------------+
-| I2C         | on-chip    | i2c                                 |
-+-------------+------------+-------------------------------------+
-| SPI         | on-chip    | spi                                 |
-+-------------+------------+-------------------------------------+
-| PWM         | on-chip    | pwm                                 |
-+-------------+------------+-------------------------------------+
-| RNG         | on-chip    | True Random number generator        |
-+-------------+------------+-------------------------------------+
-| Backup SRAM | on-chip    | Backup SRAM                         |
-+-------------+------------+-------------------------------------+
-| RTC         | on-chip    | rtc                                 |
-+-------------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig files:
-:zephyr_file:`boards/st/nucleo_h7s3l8/nucleo_h7s3l8_defconfig`
+.. zephyr:board-supported-hw::
 
 For more details please refer to `STM32H7R/S Nucleo-144 board User Manual`_.
 
@@ -228,6 +188,8 @@ do it by removing ``SB13`` jumper on the back side of the board.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo H7S3L8 board includes an ST-LINK/V3 embedded debug tool interface.
 
 .. note::
diff --git a/boards/st/nucleo_l011k4/doc/index.rst b/boards/st/nucleo_l011k4/doc/index.rst
index cb8ad43e2ab..5994d001542 100644
--- a/boards/st/nucleo_l011k4/doc/index.rst
+++ b/boards/st/nucleo_l011k4/doc/index.rst
@@ -28,7 +28,6 @@ Nucleo L011K4 provides the following hardware components:
 
   - Arduino* Nano V3 connectivity
 
-- ARM* mbed*
 - On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
 
   - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
@@ -49,11 +48,6 @@ Nucleo L011K4 provides the following hardware components:
   - Mass storage
   - Debug port
 
-- Support of wide choice of Integrated Development Environments (IDEs) including:
-
-  - IAR
-  - ARM Keil
-  - GCC-based IDEs
 
 More information about STM32L011K4 can be found in the
 `STM32L0x1 reference manual`_
@@ -62,33 +56,7 @@ More information about STM32L011K4 can be found in the
 Supported Features
 ==================
 
-The Zephyr nucleo_l011k4 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c controller                      |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi controller                      |
-+-----------+------------+-------------------------------------+
-| EEPROM    | on-chip    | eeprom                              |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_l011k4/nucleo_l011k4_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -111,6 +79,8 @@ For more details please refer to `STM32 Nucleo-32 board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo L011K4 board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_l011k4`` board configuration can be built and
diff --git a/boards/st/nucleo_l011k4/nucleo_l011k4.yaml b/boards/st/nucleo_l011k4/nucleo_l011k4.yaml
index 482dc095abb..83661ba2eed 100644
--- a/boards/st/nucleo_l011k4/nucleo_l011k4.yaml
+++ b/boards/st/nucleo_l011k4/nucleo_l011k4.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/st/nucleo_l031k6/doc/index.rst b/boards/st/nucleo_l031k6/doc/index.rst
index b5a7727a238..e5572afed00 100644
--- a/boards/st/nucleo_l031k6/doc/index.rst
+++ b/boards/st/nucleo_l031k6/doc/index.rst
@@ -55,33 +55,7 @@ More information about STM32L031K6 can be found in the
 Supported Features
 ==================
 
-The Zephyr nucleo_l031k6 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c controller                      |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi controller                      |
-+-----------+------------+-------------------------------------+
-| EEPROM    | on-chip    | eeprom                              |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_l031k6/nucleo_l031k6_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -104,6 +78,8 @@ For more details please refer to `STM32 Nucleo-32 board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo L031K6 board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_l031k6`` board configuration can be built and
diff --git a/boards/st/nucleo_l031k6/nucleo_l031k6.yaml b/boards/st/nucleo_l031k6/nucleo_l031k6.yaml
index e3ce901c4ee..f6b155460cc 100644
--- a/boards/st/nucleo_l031k6/nucleo_l031k6.yaml
+++ b/boards/st/nucleo_l031k6/nucleo_l031k6.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/st/nucleo_l053r8/doc/index.rst b/boards/st/nucleo_l053r8/doc/index.rst
index 755520a2bfb..a301b02531b 100644
--- a/boards/st/nucleo_l053r8/doc/index.rst
+++ b/boards/st/nucleo_l053r8/doc/index.rst
@@ -29,7 +29,6 @@ Nucleo L053R8 provides the following hardware components:
   - Arduino* Uno V3 connectivity
   - ST morpho extension pin headers for full access to all STM32 I/Os
 
-- ARM* mbed*
 - On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
 
   - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
@@ -50,11 +49,6 @@ Nucleo L053R8 provides the following hardware components:
   - Mass storage
   - Debug port
 
-- Support of wide choice of Integrated Development Environments (IDEs) including:
-
-  - IAR
-  - ARM Keil
-  - GCC-based IDEs
 
 More information about STM32L053R8 can be found in the
 `STM32L0x3 reference manual`_
@@ -63,33 +57,7 @@ More information about STM32L053R8 can be found in the
 Supported Features
 ==================
 
-The Zephyr nucleo_l053r8 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c controller                      |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi controller                      |
-+-----------+------------+-------------------------------------+
-| EEPROM    | on-chip    | eeprom                              |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_l053r8/nucleo_l053r8_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -120,6 +88,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo L053R8 board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_l053r8`` board configuration can be built and
diff --git a/boards/st/nucleo_l053r8/nucleo_l053r8.yaml b/boards/st/nucleo_l053r8/nucleo_l053r8.yaml
index 384d5294913..d6e40a30c62 100644
--- a/boards/st/nucleo_l053r8/nucleo_l053r8.yaml
+++ b/boards/st/nucleo_l053r8/nucleo_l053r8.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_gpio
   - arduino_i2c
diff --git a/boards/st/nucleo_l073rz/doc/index.rst b/boards/st/nucleo_l073rz/doc/index.rst
index 401290d90de..a75313f7d58 100644
--- a/boards/st/nucleo_l073rz/doc/index.rst
+++ b/boards/st/nucleo_l073rz/doc/index.rst
@@ -29,7 +29,6 @@ Nucleo L073RZ provides the following hardware components:
   - Arduino* Uno V3 connectivity
   - ST morpho extension pin headers for full access to all STM32 I/Os
 
-- ARM* mbed*
 - On-board ST-LINK/V2-1 debugger/programmer with SWD connector:
 
   - Selection-mode switch to use the kit as a standalone ST-LINK/V2-1
@@ -50,11 +49,6 @@ Nucleo L073RZ provides the following hardware components:
   - Mass storage
   - Debug port
 
-- Support of wide choice of Integrated Development Environments (IDEs) including:
-
-  - IAR
-  - ARM Keil
-  - GCC-based IDEs
 
 More information about STM32L073RZ can be found in the
 `STM32L0x3 reference manual`_
@@ -63,47 +57,7 @@ More information about STM32L073RZ can be found in the
 Supported Features
 ==================
 
-The Zephyr nucleo_l073rz board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c controller                      |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi controller                      |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | DAC Controller                      |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | Random Number Generator             |
-+-----------+------------+-------------------------------------+
-| EEPROM    | on-chip    | eeprom                              |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_l073rz/nucleo_l073rz_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -136,6 +90,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo L073RZ board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_l073rz`` board configuration can be built and
diff --git a/boards/st/nucleo_l073rz/nucleo_l073rz.yaml b/boards/st/nucleo_l073rz/nucleo_l073rz.yaml
index 2a2ffde92bd..a5cd4360123 100644
--- a/boards/st/nucleo_l073rz/nucleo_l073rz.yaml
+++ b/boards/st/nucleo_l073rz/nucleo_l073rz.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 20
 flash: 192
 supported:
diff --git a/boards/st/nucleo_l152re/doc/index.rst b/boards/st/nucleo_l152re/doc/index.rst
index 1973ffa8e5a..4b6a27f3e75 100644
--- a/boards/st/nucleo_l152re/doc/index.rst
+++ b/boards/st/nucleo_l152re/doc/index.rst
@@ -57,49 +57,7 @@ More information about STM32L152RE can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_l152re board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c controller                      |
-+-----------+------------+-------------------------------------+
-| EEPROM    | on-chip    | eeprom                              |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | DAC Controller                      |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | PWM                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | Direct Memory Access                |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/nucleo_l152re/nucleo_l152re_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -130,6 +88,8 @@ For more details please refer to `STM32 Nucleo-64 board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo L152RE board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_l152re`` board configuration can be built and
diff --git a/boards/st/nucleo_l152re/nucleo_l152re.dts b/boards/st/nucleo_l152re/nucleo_l152re.dts
index d1278873fd8..2d2e048e70d 100644
--- a/boards/st/nucleo_l152re/nucleo_l152re.dts
+++ b/boards/st/nucleo_l152re/nucleo_l152re.dts
@@ -25,7 +25,7 @@
 	leds: leds {
 		compatible = "gpio-leds";
 		green_led_0: led_0 {
-			gpios = <&gpioa 5 GPIO_ACTIVE_LOW>;
+			gpios = <&gpioa 5 GPIO_ACTIVE_HIGH>;
 			label = "User LD2";
 		};
 	};
diff --git a/boards/st/nucleo_l412rb_p/doc/index.rst b/boards/st/nucleo_l412rb_p/doc/index.rst
index 75caa4e9f1b..e20d978dc61 100644
--- a/boards/st/nucleo_l412rb_p/doc/index.rst
+++ b/boards/st/nucleo_l412rb_p/doc/index.rst
@@ -128,34 +128,7 @@ More information about STM32L412RB can be found here:
 Supported Features
 ==================
 
-The Zephyr ``nucleo_l412rb_p`` board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_l412rb_p/nucleo_l412rb_p_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -201,6 +174,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo L412RB-P board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_l412rb_p`` board configuration can be built and
diff --git a/boards/st/nucleo_l412rb_p/nucleo_l412rb_p.yaml b/boards/st/nucleo_l412rb_p/nucleo_l412rb_p.yaml
index 8c663aae012..c2b8c3822ee 100644
--- a/boards/st/nucleo_l412rb_p/nucleo_l412rb_p.yaml
+++ b/boards/st/nucleo_l412rb_p/nucleo_l412rb_p.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 40
 flash: 64
 supported:
diff --git a/boards/st/nucleo_l432kc/doc/index.rst b/boards/st/nucleo_l432kc/doc/index.rst
index ad17c525de5..5348e09d6e2 100644
--- a/boards/st/nucleo_l432kc/doc/index.rst
+++ b/boards/st/nucleo_l432kc/doc/index.rst
@@ -89,35 +89,10 @@ More information about STM32L432KC can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_l432kc board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 .. note:: CAN feature requires CAN transceiver
 
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_l432kc/nucleo_l432kc_defconfig`
-
-
 Connections and IOs
 ===================
 
@@ -161,6 +136,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo L432KC board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_l432kc`` board configuration can be built and
diff --git a/boards/st/nucleo_l432kc/nucleo_l432kc.yaml b/boards/st/nucleo_l432kc/nucleo_l432kc.yaml
index 345fcb7e44f..dbcb3c7e661 100644
--- a/boards/st/nucleo_l432kc/nucleo_l432kc.yaml
+++ b/boards/st/nucleo_l432kc/nucleo_l432kc.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 256
 supported:
diff --git a/boards/st/nucleo_l433rc_p/doc/index.rst b/boards/st/nucleo_l433rc_p/doc/index.rst
index 5b61f6e7718..ffce9d4adeb 100644
--- a/boards/st/nucleo_l433rc_p/doc/index.rst
+++ b/boards/st/nucleo_l433rc_p/doc/index.rst
@@ -90,37 +90,10 @@ More information about STM32L433RC can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_l433rc_p board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 .. note:: CAN feature requires CAN transceiver
 
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_l433rc_p/nucleo_l433rc_p_defconfig`
-
-
 Connections and IOs
 ===================
 
@@ -166,6 +139,8 @@ to LPUART1. Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo L433RC-P board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_l433rc_p`` board configuration can be built and
diff --git a/boards/st/nucleo_l433rc_p/nucleo_l433rc_p.yaml b/boards/st/nucleo_l433rc_p/nucleo_l433rc_p.yaml
index ee3a41bce02..e4f61f712d8 100644
--- a/boards/st/nucleo_l433rc_p/nucleo_l433rc_p.yaml
+++ b/boards/st/nucleo_l433rc_p/nucleo_l433rc_p.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 256
 supported:
diff --git a/boards/st/nucleo_l452re/doc/index.rst b/boards/st/nucleo_l452re/doc/index.rst
index 2995387e8ae..5c5dddd7cae 100644
--- a/boards/st/nucleo_l452re/doc/index.rst
+++ b/boards/st/nucleo_l452re/doc/index.rst
@@ -99,38 +99,10 @@ More information about STM32L452RE can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_l452re board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 .. note:: CAN feature requires CAN transceiver
 
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_l452re/nucleo_l452re_defconfig`
-
-And for Nucleo L452RE-P in this defconfig file:
-:zephyr_file:`boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p_defconfig`
-
-
 Connections and IOs
 ===================
 
@@ -185,6 +157,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo L452RE board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_l452re`` board configuration can be built and
diff --git a/boards/st/nucleo_l452re/nucleo_l452re.yaml b/boards/st/nucleo_l452re/nucleo_l452re.yaml
index 0b3aa645bf4..7cea2149cad 100644
--- a/boards/st/nucleo_l452re/nucleo_l452re.yaml
+++ b/boards/st/nucleo_l452re/nucleo_l452re.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 160
 flash: 512
 supported:
diff --git a/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p.yaml b/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p.yaml
index 86e8a58034f..d4df5c29212 100644
--- a/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p.yaml
+++ b/boards/st/nucleo_l452re/nucleo_l452re_stm32l452xx_p.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 160
 flash: 512
 supported:
diff --git a/boards/st/nucleo_l476rg/doc/index.rst b/boards/st/nucleo_l476rg/doc/index.rst
index 7c0ddb76958..7bdf04eeab1 100644
--- a/boards/st/nucleo_l476rg/doc/index.rst
+++ b/boards/st/nucleo_l476rg/doc/index.rst
@@ -94,34 +94,7 @@ More information about STM32L476RG can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_l476rg board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_l476rg/nucleo_l476rg_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -174,6 +147,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo L476RG board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_l476rg`` board configuration can be built and
diff --git a/boards/st/nucleo_l476rg/nucleo_l476rg.dts b/boards/st/nucleo_l476rg/nucleo_l476rg.dts
index ecc5ea5cf7a..4a63a5ad328 100644
--- a/boards/st/nucleo_l476rg/nucleo_l476rg.dts
+++ b/boards/st/nucleo_l476rg/nucleo_l476rg.dts
@@ -63,6 +63,7 @@
 	div-m = <1>;
 	mul-n = <20>;
 	div-r = <4>;
+	div-q = <8>;
 	clocks = <&clk_hsi>;
 	status = "okay";
 };
@@ -193,3 +194,10 @@ stm32_lp_tick_source: &lptim1 {
 		};
 	};
 };
+
+&rng {
+	/* Change clock source to avoid using MSI */
+	clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
+		 <&rcc STM32_SRC_PLL_Q CLK48_SEL(2)>;
+	status = "okay";
+};
diff --git a/boards/st/nucleo_l476rg/nucleo_l476rg.yaml b/boards/st/nucleo_l476rg/nucleo_l476rg.yaml
index d0330751a75..97821682ab2 100644
--- a/boards/st/nucleo_l476rg/nucleo_l476rg.yaml
+++ b/boards/st/nucleo_l476rg/nucleo_l476rg.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_gpio
   - arduino_i2c
diff --git a/boards/st/nucleo_l496zg/doc/index.rst b/boards/st/nucleo_l496zg/doc/index.rst
index 838bec9905e..97e25d36cdf 100644
--- a/boards/st/nucleo_l496zg/doc/index.rst
+++ b/boards/st/nucleo_l496zg/doc/index.rst
@@ -98,38 +98,7 @@ More information about STM32L496ZG can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_l496zg board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| OTG FS    | on-chip    | USB OTG Full-speed                  |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | System Window Watchdog              |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_l496zg/nucleo_l496zg_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -177,6 +146,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo L496ZG board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_l496zg`` board configuration can be built and
diff --git a/boards/st/nucleo_l4a6zg/doc/index.rst b/boards/st/nucleo_l4a6zg/doc/index.rst
index aced6276860..a5dc14787a5 100644
--- a/boards/st/nucleo_l4a6zg/doc/index.rst
+++ b/boards/st/nucleo_l4a6zg/doc/index.rst
@@ -99,40 +99,7 @@ More information about STM32L4A6ZG can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_l4a6zg board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| AES       | on-chip    | crypto                              |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | System Window Watchdog              |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_l4a6zg/nucleo_l4a6zg_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -174,6 +141,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo L4A6ZG board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_l4a6zg`` board configuration can be built and
diff --git a/boards/st/nucleo_l4r5zi/doc/index.rst b/boards/st/nucleo_l4r5zi/doc/index.rst
index 7ea8f859806..937689ac630 100644
--- a/boards/st/nucleo_l4r5zi/doc/index.rst
+++ b/boards/st/nucleo_l4r5zi/doc/index.rst
@@ -109,39 +109,7 @@ More information about STM32L4R5ZI can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_l4r5zi board configuration supports the following
-hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_l4r5zi/nucleo_l4r5zi_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -214,6 +182,8 @@ Ethernet over USB is configured as the default network interface (EEM)
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The NUCLEO-L4R5ZI board includes a ST-LINK/V2 embedded debug tool interface.
 
 Flashing
diff --git a/boards/st/nucleo_l4r5zi/nucleo_l4r5zi.yaml b/boards/st/nucleo_l4r5zi/nucleo_l4r5zi.yaml
index 5bfd9f26be6..577c8c02b78 100644
--- a/boards/st/nucleo_l4r5zi/nucleo_l4r5zi.yaml
+++ b/boards/st/nucleo_l4r5zi/nucleo_l4r5zi.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_i2c
   - arduino_gpio
diff --git a/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst b/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst
index 9dab9c36a9a..434c1dc4975 100644
--- a/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst
+++ b/boards/st/nucleo_l552ze_q/doc/nucleol552ze_q.rst
@@ -123,55 +123,7 @@ More information about STM32L552ZE can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_l552ze_q board configuration supports the following
-hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | DAC Controller                      |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | Direct Memory Access                |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| TrustZone | on-chip    | Trusted Firmware-M                  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig and dts files:
-
-- Common:
-
-  - :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q-common.dtsi`
-
-- Secure target:
-
-  - :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q_defconfig`
-  - :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q.dts`
-
-- Non-Secure target:
-
-  - :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns_defconfig`
-  - :zephyr_file:`boards/st/nucleo_l552ze_q/nucleo_l552ze_q_stm32l552xx_ns.dts`
+.. zephyr:board-supported-hw::
 
 Zephyr board options
 ====================
@@ -275,6 +227,8 @@ UART2. Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo L552ZE Q board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_l552ze_q`` board configuration can be built and
diff --git a/boards/st/nucleo_n657x0_q/Kconfig.defconfig b/boards/st/nucleo_n657x0_q/Kconfig.defconfig
new file mode 100644
index 00000000000..170ddd3eb37
--- /dev/null
+++ b/boards/st/nucleo_n657x0_q/Kconfig.defconfig
@@ -0,0 +1,15 @@
+# STM32N657X0_Q Nucleo board configuration
+
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_NUCLEO_N657X0_Q
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+endif # NETWORKING
+
+endif # BOARD_NUCLEO_N657X0_Q
diff --git a/boards/st/nucleo_n657x0_q/Kconfig.nucleo_n657x0_q b/boards/st/nucleo_n657x0_q/Kconfig.nucleo_n657x0_q
new file mode 100644
index 00000000000..a1c2528a470
--- /dev/null
+++ b/boards/st/nucleo_n657x0_q/Kconfig.nucleo_n657x0_q
@@ -0,0 +1,7 @@
+# STM32N657X0_Q Nucleo board configuration
+
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NUCLEO_N657X0_Q
+	select SOC_STM32N657XX
diff --git a/boards/st/nucleo_n657x0_q/arduino_r3_connector.dtsi b/boards/st/nucleo_n657x0_q/arduino_r3_connector.dtsi
new file mode 100644
index 00000000000..3d452c84a64
--- /dev/null
+++ b/boards/st/nucleo_n657x0_q/arduino_r3_connector.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/ {
+	arduino_header: connector {
+		compatible = "arduino-header-r3";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpioa 8 0>,	/* A0 */
+			   <1 0 &gpioa 9 0>,	/* A1 */
+			   <2 0 &gpioa 10 0>,	/* A2 */
+			   <3 0 &gpioa 12 0>,	/* A3 */
+			   <4 0 &gpiof 3 0>,	/* A4 */
+			   <5 0 &gpiog 15 0>,	/* A5 */
+			   <6 0 &gpiod 9 0>,	/* D0 */
+			   <7 0 &gpiod 8 0>,	/* D1 */
+			   <8 0 &gpiod 0 0>,	/* D2 */
+			   <9 0 &gpioe 9 0>,	/* D3 */
+			   <10 0 &gpioe 0 0>,	/* D4 */
+			   <11 0 &gpioe 10 0>,	/* D5 */
+			   <12 0 &gpiod 5 0>,	/* D6 */
+			   <13 0 &gpioe 11 0>,	/* D7 */
+			   <14 0 &gpiod 12 0>,	/* D8 */
+			   <15 0 &gpiod 7 0>,	/* D9 */
+			   <16 0 &gpioa 3 0>,	/* D10 */
+			   <17 0 &gpiog 2 0>,	/* D11 */
+			   <18 0 &gpiog 1 0>,	/* D12 */
+			   <19 0 &gpioe 15 0>,	/* D13 */
+			   <20 0 &gpioc 1 0>,	/* D14 */
+			   <21 0 &gpioh 9 0>;	/* D15 */
+	};
+};
+
+arduino_serial: &usart3 {};
+arduino_i2c: &i2c1 {};
+arduino_spi: &spi5 {};
diff --git a/boards/st/nucleo_n657x0_q/board.cmake b/boards/st/nucleo_n657x0_q/board.cmake
new file mode 100644
index 00000000000..a469036845c
--- /dev/null
+++ b/boards/st/nucleo_n657x0_q/board.cmake
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2024 STMicroelectronics
+
+if(CONFIG_STM32N6_BOOT_SERIAL)
+  board_runner_args(stm32cubeprogrammer "--port=usb1")
+  board_runner_args(stm32cubeprogrammer "--download-modifiers=0x1")
+  board_runner_args(stm32cubeprogrammer "--start-modifiers=noack")
+else()
+  board_runner_args(stm32cubeprogrammer "--port=swd")
+  board_runner_args(stm32cubeprogrammer "--tool-opt= mode=HOTPLUG ap=1")
+  board_runner_args(stm32cubeprogrammer "--extload=MX25UM51245G_STM32N6570-NUCLEO.stldr")
+  board_runner_args(stm32cubeprogrammer "--download-address=0x70000000")
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
diff --git a/boards/st/nucleo_n657x0_q/board.yml b/boards/st/nucleo_n657x0_q/board.yml
new file mode 100644
index 00000000000..4261dec1e7b
--- /dev/null
+++ b/boards/st/nucleo_n657x0_q/board.yml
@@ -0,0 +1,8 @@
+board:
+  name: nucleo_n657x0_q
+  full_name: Nucleo N657X0-Q
+  vendor: st
+  socs:
+    - name: stm32n657xx
+      variants:
+        - name: sb
diff --git a/boards/st/nucleo_n657x0_q/doc/img/nucleo_n657x0_q.webp b/boards/st/nucleo_n657x0_q/doc/img/nucleo_n657x0_q.webp
new file mode 100644
index 00000000000..c6d918de66d
Binary files /dev/null and b/boards/st/nucleo_n657x0_q/doc/img/nucleo_n657x0_q.webp differ
diff --git a/boards/st/nucleo_n657x0_q/doc/index.rst b/boards/st/nucleo_n657x0_q/doc/index.rst
new file mode 100644
index 00000000000..866f8f59de7
--- /dev/null
+++ b/boards/st/nucleo_n657x0_q/doc/index.rst
@@ -0,0 +1,290 @@
+.. zephyr:board:: nucleo_n657x0_q
+
+Overview
+********
+
+The NUCLEO-N657X0-Q board provides an affordable and flexible way for users to try out
+new concepts and build prototypes by choosing from the various combinations of performance
+and power consumption features, provided by the STM32 microcontroller. For the compatible boards,
+the internal or external SMPS significantly reduces power consumption in Run mode.
+
+The ST Zio connector, which extends the ARDUINO® Uno V3 connectivity, and the ST morpho headers
+provide an easy means of expanding the functionality of the Nucleo open development platform with
+a wide choice of specialized shields.
+
+The NUCLEO-N657X0-Q board does not require any separate probe as it integrates the ST-LINK
+debugger/programmer.
+
+The STM32 Nucleo-144 board comes with the STM32 comprehensive free software libraries and
+examples available with the STM32Cube MCU Package.
+
+Hardware
+********
+
+- Common features:
+
+  - STM32 microcontroller in an LQFP144, TFBGA225, or VFBGA264 package
+  - 3 user LEDs
+  - 1 user push-button and 1 reset push-button
+  - 32.768 kHz crystal oscillator
+  - Board connectors:
+
+    - SWD
+    - ST morpho expansion connector
+
+  - Flexible power-supply options: ST-LINK USB VBUS, USB connector, or external sources
+
+- Features specific to some of the boards (refer to the ordering information section
+  of the data brief for details);
+
+  - External or internal SMPS to generate Vcore logic supply
+  - Ethernet compliant with IEEE-802.3-2002
+  - USB Device only, USB OTG full speed, or SNK/UFP (full-speed or high-speed mode)
+  - Board connectors:
+
+    - ARDUINO® Uno V3 connector or ST Zio expansion connector including ARDUINO® Uno V3
+    - Camera module FPC
+    - MIPI20 compatible connector with trace signals
+    - USB with Micro-AB or USB Type-C®
+    - Ethernet RJ45
+
+  - On-board ST-LINK (STLINK/V2-1, STLINK-V3E, or STLINK-V3EC) debugger/programmer with
+    USB re-enumeration capability: mass storage, Virtual COM port, and debug port
+
+For more details, please refer to:
+
+* `NUCLEO-N657X0-Q website`_
+* `STM32N657X0 on www.st.com`_
+* `STM32N657 reference manual`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+USB
+===
+
+The USB pin assignments on the STM32N657XX microcontroller are immutable. This means that the specific
+pins designated for USB functionality are fixed and cannot be changed or reassigned to other functions,
+ensuring consistent and reliable USB communication.
+
+USB PIN (IOs)
+=============
+
++------------------+--------------------------------------+
+| Name             | Description                          |
++==================+======================================+
+| OTG1_HSDM        | USB OTG1 High-Speed Data- (negative) |
++------------------+--------------------------------------+
+| OTG1_HSDP        | USB OTG1 High-Speed Data+ (positive) |
++------------------+--------------------------------------+
+| OTG1_ID          | USB OTG1 ID Pin                      |
++------------------+--------------------------------------+
+| OTG1_TXRTUNE     | USB OTG1 Transmit Retune             |
++------------------+--------------------------------------+
+| OTG2_HSDM        | USB OTG2 High-Speed Data- (negative) |
++------------------+--------------------------------------+
+| OTG2_HSDP        | USB OTG2 High-Speed Data+ (positive) |
++------------------+--------------------------------------+
+| OTG2_ID          | USB OTG2 ID Pin                      |
++------------------+--------------------------------------+
+| OTG2_TXRTUNE     | USB OTG2 Transmit Retune             |
++------------------+--------------------------------------+
+
+Connections and IOs
+===================
+
+NUCLEO-N657X0-Q Board has 12 GPIO controllers. These controllers are responsible
+for pin muxing, input/output, pull-up, etc.
+
+For more details please refer to `NUCLEO-N657X0-Q User Manual`_.
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+- ADC1_INP10 : PA9
+- ADC1_INP11 : PA10
+- FDCAN1_TX : PH2
+- FDCAN1_RX : PD0
+- I2C1_SCL : PH9
+- I2C1_SDA : PC1
+- I2C4_SCL : PE13
+- I2C4_SDA : PE14
+- LD1 : PO1
+- LD2 : PG10
+- SPI5_SCK : PE15
+- SPI5_MOSI : PG2
+- SPI5_MISO : PG1
+- SPI5_NSS : PA3
+- USART_1_TX : PE5
+- USART_1_RX : PE6
+- USART_3_TX : PD8
+- USART_3_RX : PD9
+- XSPI2_NCS1 : PN1
+- XSPI2_DQS0 : PN0
+- XSPI2_CLK : PN6
+- XSPI2_IO0 : PN2
+- XSPI2_IO1 : PN3
+- XSPI2_IO2 : PN4
+- XSPI2_IO3 : PN5
+- XSPI2_IO4 : PN8
+- XSPI2_IO5 : PN9
+- XSPI2_IO6 : PN10
+- XSPI2_IO7 : PN11
+
+System Clock
+------------
+
+NUCLEO-N657X0-Q System Clock could be driven by internal or external oscillator,
+as well as main PLL clock. By default System clock is driven by PLL clock at
+400MHz, driven by 64MHz high speed internal oscillator.
+
+Serial Port
+-----------
+
+NUCLEO-N657X0-Q board has 10 U(S)ARTs. The Zephyr console output is assigned to
+USART1. Default settings are 115200 8N1.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+NUCLEO-N657X0-Q board includes an ST-LINK/V3 embedded debug tool interface.
+This probe allows to flash and debug the board using various tools.
+
+
+
+Flashing or loading
+===================
+
+The board is configured to be programmed using west `STM32CubeProgrammer`_ runner,
+so its :ref:`installation <stm32cubeprog-flash-host-tools>` is needed.
+Version 2.18.0 or later of `STM32CubeProgrammer`_ is required.
+
+.. note::
+   Firmware is run in secure mode of execution, which requires a signature.
+   After build, the build system  will automatically generate a signed version of the
+   binary using `STM32CubeProgrammer`_ utility ``STM32_SigningTool_CLI``.
+   This utility is installed along with `STM32CubeProgrammer`_, but make sure it is
+   available in your ``PATH`` variable.
+
+To program the board, there are two options:
+
+- Program the firmware in external flash. At boot, it will then be loaded on RAM
+  and executed from there.
+- Optionally, it can also be taken advantage from the serial boot interface provided
+  by the boot ROM. In that case, firmware is directly loaded in RAM and executed from
+  there. It is not retained.
+
+Programming an application to NUCLEO-N657X0-Q
+---------------------------------------------
+
+Here is an example to build and run :zephyr:code-sample:`hello_world` application.
+
+First, connect the NUCLEO-N657X0-Q to your host computer using the ST-Link USB port.
+
+   .. tabs::
+
+      .. group-tab:: ST-Link
+
+         Build and flash an application using ``nucleo_n657x0_q`` target.
+
+         .. zephyr-app-commands::
+            :zephyr-app: samples/hello_world
+            :board: nucleo_n657x0_q
+            :goals: build flash
+
+         .. note::
+            For flashing, before powering the board, set the boot pins in the following configuration:
+
+            * BOOT0: 0
+            * BOOT1: 1
+
+            After flashing, to run the application, set the boot pins in the following configuration:
+
+            * BOOT1: 0
+
+	    Power off and on the board again.
+
+      .. group-tab:: Serial Boot Loader (USB)
+
+         Additionally, connect the NUCLEO-N657X0-Q to your host computer using the USB port.
+         In this configuration, ST-Link is used to power the board and for serial communication
+         over the Virtual COM Port.
+
+         .. note::
+            Before powering the board, set the boot pins in the following configuration:
+
+            * BOOT0: 1
+            * BOOT1: 0
+
+         Build and load an application using ``nucleo_n657x0_q/stm32n657xx/sb`` target (you
+         can also use the shortened form: ``nucleo_n657x0_q//sb``)
+
+         .. zephyr-app-commands::
+            :zephyr-app: samples/hello_world
+            :board: nucleo_n657x0_q
+            :goals: build flash
+
+
+Run a serial host program to connect to your board:
+
+.. code-block:: console
+
+   $ minicom -D /dev/ttyACM0
+
+You should see the following message on the console:
+
+.. code-block:: console
+
+   Hello World! nucleo_n657x0_q/stm32n657xx
+
+
+Debugging
+=========
+
+For now debugging is only available through STM32CubeIDE:
+
+* Go to File > Import and select C/C++ > STM32 Cortex-M Executable.
+* In Executable field, browse to your <ZEPHYR_PATH>/build/zephyr/zephyr.elf.
+* In MCU field, select STM32N657X0HxQ.
+* Click on Finish.
+* Finally, click on Debug to start the debugging session.
+
+.. note::
+   For debugging, before powering on the board, set the boot pins in the following configuration:
+
+   * BOOT0: 0
+   * BOOT1: 1
+
+
+Running tests with twister
+==========================
+
+Due to the BOOT switches manipulation required when flashing the board using ``nucleo_n657x0_q``
+board target, it is only possible to run twister tests campaign on ``nucleo_n657x0_q/stm32n657xx/sb``
+board target which doesn't require BOOT pins changes to load and execute binaries.
+To do so, it is advised to use Twister's hardware map feature with the following settings:
+
+.. code-block:: yaml
+
+   - platform: nucleo_n657x0_q/stm32n657xx/sb
+     product: BOOT-SERIAL
+     pre_script: <path_to_zephyr>/boards/st/common/scripts/board_power_reset.sh
+     runner: stm32cubeprogrammer
+
+.. _NUCLEO-N657X0-Q website:
+   https://www.st.com/en/evaluation-tools/nucleo-n657x0-q.html
+
+.. _NUCLEO-N657X0-Q User Manual:
+   https://www.st.com/resource/en/user_manual/um3417-stm32n6-nucleo144-board-mb1940-stmicroelectronics.pdf
+.. _STM32N657X0 on www.st.com:
+   https://www.st.com/en/microcontrollers-microprocessors/stm32n657x0.html
+
+.. _STM32N657 reference manual:
+   https://www.st.com/resource/en/reference_manual/rm0486-stm32n647657xx-armbased-32bit-mcus-stmicroelectronics.pdf
+
+.. _STM32CubeProgrammer:
+   https://www.st.com/en/development-tools/stm32cubeprog.html
diff --git a/boards/st/nucleo_n657x0_q/nucleo_n657x0_q.dts b/boards/st/nucleo_n657x0_q/nucleo_n657x0_q.dts
new file mode 100644
index 00000000000..1e6d99ed632
--- /dev/null
+++ b/boards/st/nucleo_n657x0_q/nucleo_n657x0_q.dts
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include "nucleo_n657x0_q_common.dtsi"
+
+/ {
+	model = "STMicroelectronics STM32N657X0-Q-NUCLEO board";
+	compatible = "st,stm32n657x0-q-nucleo";
+};
diff --git a/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi b/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi
new file mode 100644
index 00000000000..b249d2ab847
--- /dev/null
+++ b/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi
@@ -0,0 +1,258 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/n6/stm32n657X0.dtsi>
+#include <st/n6/stm32n657x0hxq-pinctrl.dtsi>
+#include <zephyr/dt-bindings/flash_controller/xspi.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include "arduino_r3_connector.dtsi"
+
+/ {
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+		zephyr,sram = &axisram2;
+		zephyr,canbus = &fdcan1;
+		spi-flash0 = &mx25um51245g;
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		green_led: led_1 {
+			gpios = <&gpiog 0 GPIO_ACTIVE_HIGH>;
+			label = "User LD6";
+		};
+
+		blue_led: led_2 {
+			gpios = <&gpiog 8 GPIO_ACTIVE_HIGH>;
+			label = "User LD7";
+		};
+
+		red_led: led_3 {
+			gpios = <&gpiog 10 GPIO_ACTIVE_HIGH>;
+			label = "User LD5";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		user_button: button_0 {
+			gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
+			label = "User SB1";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	aliases {
+		led0 = &green_led;
+		led1 = &blue_led;
+		led2 = &red_led;
+		sw0 = &user_button;
+	};
+};
+
+&clk_hse {
+	hse-div2;
+	clock-frequency = <DT_FREQ_M(48)>;
+	status = "okay";
+};
+
+&clk_hsi {
+	hsi-div = <1>;
+	status = "okay";
+};
+
+&pll1 {
+	clocks = <&clk_hse>;
+	div-m = <3>;
+	mul-n = <150>;
+	div-p1 = <1>;
+	div-p2 = <1>;
+	status = "okay";
+};
+
+&pll3 {
+	clocks = <&clk_hse>;
+	div-m = <3>;
+	mul-n = <125>;
+	div-p1 = <1>;
+	div-p2 = <1>;
+	status = "okay";
+};
+
+&ic1 {
+	pll-src = <1>;
+	ic-div = <3>;
+	status = "okay";
+};
+
+&ic2 {
+	pll-src = <1>;
+	ic-div = <6>;
+	status = "okay";
+};
+
+&ic3 {
+	pll-src = <1>;
+	ic-div = <6>;
+	status = "okay";
+};
+
+&ic6 {
+	pll-src = <3>;
+	ic-div = <2>;
+	status = "okay";
+};
+
+&ic11 {
+	pll-src = <1>;
+	ic-div = <3>;
+	status = "okay";
+};
+
+&perck {
+	clocks = <&rcc STM32_SRC_HSI PER_SEL(0)>;
+	status = "okay";
+};
+
+&cpusw {
+	clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;
+	clock-frequency = <DT_FREQ_M(800)>;
+	status = "okay";
+};
+
+&rcc {
+	/* ic2, ic6 & ic11 must all be enabled to set ic2 as SYSCLK */
+	clocks = <&ic2>;
+	clock-frequency = <DT_FREQ_M(400)>;
+	ahb-prescaler = <2>;
+	timg-prescaler = <2>;
+};
+
+&adc1 {
+	clocks = <&rcc STM32_CLOCK(AHB1, 5)>,
+		 <&rcc STM32_SRC_CKPER ADC12_SEL(1)>;
+	pinctrl-0 = <&adc1_inp10_pa9 &adc1_inp11_pa10>; /* Arduino A1 & A2 */
+	pinctrl-names = "default";
+	vref-mv = <1800>;
+	status = "okay";
+};
+
+&fdcan1 {
+	clocks = <&rcc STM32_CLOCK(APB1_2, 8)>,
+		 <&rcc STM32_SRC_CKPER FDCAN_SEL(1)>;
+	pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_ph2>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c1 {
+	clocks = <&rcc STM32_CLOCK(APB1, 21)>,
+		 <&rcc STM32_SRC_CKPER I2C1_SEL(1)>;
+	pinctrl-0 = <&i2c1_scl_ph9 &i2c1_sda_pc1>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	status = "okay";
+};
+
+&i2c4 {
+	clocks = <&rcc STM32_CLOCK(APB4, 7)>,
+		 <&rcc STM32_SRC_CKPER I2C4_SEL(1)>;
+	pinctrl-0 = <&i2c4_scl_pe13 &i2c4_sda_pe14>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	status = "okay";
+};
+
+&spi5 {
+	clocks = <&rcc STM32_CLOCK(APB2, 20)>,
+		 <&rcc STM32_SRC_CKPER SPI5_SEL(1)>;
+	pinctrl-0 = <&spi5_nss_pa3 &spi5_sck_pe15 &spi5_miso_pg1 &spi5_mosi_pg2>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usart1 {
+	clocks = <&rcc STM32_CLOCK(APB2, 4)>,
+		 <&rcc STM32_SRC_CKPER USART1_SEL(1)>;
+	pinctrl-0 = <&usart1_tx_pe5 &usart1_rx_pe6>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&usart3 {
+	clocks = <&rcc STM32_CLOCK(APB1, 18)>,
+		 <&rcc STM32_SRC_CKPER USART3_SEL(1)>;
+	pinctrl-0 = <&usart3_tx_pd8 &usart3_rx_pd9>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+zephyr_udc0: &usbotg_hs1 {
+	status = "okay";
+};
+
+&mac {
+	status = "okay";
+	pinctrl-0 = <&eth1_rmii_ref_clk_pf7
+		     &eth1_rmii_crs_dv_pf10
+		     &eth1_rmii_rxd0_pf14
+		     &eth1_rmii_rxd1_pf15
+		     &eth1_rmii_tx_en_pf11
+		     &eth1_rmii_txd0_pf12
+		     &eth1_rmii_txd1_pf13>;
+	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&eth1_mdio_pf4 &eth1_mdc_pg11>;
+	pinctrl-names = "default";
+
+	eth_phy: ethernet-phy@0 {
+		compatible = "ethernet-phy";
+		reg = <0x0>;
+	};
+};
+
+&xspi2 {
+	pinctrl-0 = <&xspim_p2_ncs1_pn1 &xspim_p2_dqs0_pn0 &xspim_p2_clk_pn6
+		     &xspim_p2_io0_pn2 &xspim_p2_io1_pn3 &xspim_p2_io2_pn4
+		     &xspim_p2_io3_pn5 &xspim_p2_io4_pn8 &xspim_p2_io5_pn9
+		     &xspim_p2_io6_pn10 &xspim_p2_io7_pn11>;
+	pinctrl-names = "default";
+	clocks = <&rcc STM32_CLOCK(AHB5, 12)>,
+		 <&rcc STM32_SRC_IC3 XSPI1_SEL(2)>,
+		 <&rcc STM32_CLOCK(AHB5, 13)>;
+	status = "okay";
+
+	mx25um51245g: ospi-nor-flash@70000000 {
+		compatible = "st,stm32-xspi-nor";
+		reg = <0x70000000 DT_SIZE_M(64)>; /* 512 Mbits */
+		ospi-max-frequency = <DT_FREQ_M(200)>;
+		spi-bus-width = <XSPI_OCTO_MODE>;
+		data-rate = <XSPI_DTR_TRANSFER>;
+		four-byte-opcodes;
+		status = "okay";
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			storage_partition: partition@3ff0000 {
+				label = "storage";
+				reg = <0x3ff0000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};
diff --git a/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_defconfig b/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_defconfig
new file mode 100644
index 00000000000..01abfa9c0b7
--- /dev/null
+++ b/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_defconfig
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2024 STMicroelectronics
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# No internal Flash
+CONFIG_XIP=n
diff --git a/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_stm32n657xx_sb.dts b/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_stm32n657xx_sb.dts
new file mode 100644
index 00000000000..e7d5f347304
--- /dev/null
+++ b/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_stm32n657xx_sb.dts
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include "nucleo_n657x0_q_common.dtsi"
+
+/ {
+	model = "STMicroelectronics STM32N657X0-Q-NUCLEO board";
+	compatible = "st,stm32n657x0-q-nucleo-sb";
+};
diff --git a/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_stm32n657xx_sb_defconfig b/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_stm32n657xx_sb_defconfig
new file mode 100644
index 00000000000..33b0f281a2f
--- /dev/null
+++ b/boards/st/nucleo_n657x0_q/nucleo_n657x0_q_stm32n657xx_sb_defconfig
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2024 STMicroelectronics
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# No internal Flash
+CONFIG_XIP=n
+
+# Use serial boot (USB)
+CONFIG_STM32N6_BOOT_SERIAL=y
diff --git a/boards/st/nucleo_n657x0_q/twister.yaml b/boards/st/nucleo_n657x0_q/twister.yaml
new file mode 100644
index 00000000000..1b3b669ae47
--- /dev/null
+++ b/boards/st/nucleo_n657x0_q/twister.yaml
@@ -0,0 +1,26 @@
+name: ST Nucleo N657X0-Q
+type: mcu
+arch: arm
+ram: 1024
+flash: 1024
+supported:
+  - arduino_i2c
+  - arduino_serial
+  - arduino_spi
+  - adc
+  - can
+  - dma
+  - i2c
+  - gpio
+  - spi
+  - uart
+  - usb_device
+  - usbd
+vendor: st
+variants:
+  nucleo_n657x0_q/stm32n657xx:
+    twister: false
+  nucleo_n657x0_q/stm32n657xx/sb:
+    toolchain:
+      - zephyr
+      - gnuarmemb
diff --git a/boards/st/nucleo_u031r8/doc/index.rst b/boards/st/nucleo_u031r8/doc/index.rst
index 6126586000f..f369de0920a 100644
--- a/boards/st/nucleo_u031r8/doc/index.rst
+++ b/boards/st/nucleo_u031r8/doc/index.rst
@@ -128,32 +128,7 @@ More information about STM32U031R8 can be found here:
 Supported Features
 ==================
 
-The Zephyr _nucleo_u031r8_ board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | DAC Controller                      |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_u031r8/nucleo_u031r8_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -191,6 +166,8 @@ USART2. Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo U031R8 board includes an ST-LINK/V3 embedded debug tool interface.
 This probe allows to flash the board using various tools.
 
diff --git a/boards/st/nucleo_u083rc/doc/index.rst b/boards/st/nucleo_u083rc/doc/index.rst
index 7cd2f5db578..5e4e21b4727 100644
--- a/boards/st/nucleo_u083rc/doc/index.rst
+++ b/boards/st/nucleo_u083rc/doc/index.rst
@@ -136,50 +136,7 @@ More information about STM32U083RC can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_u083rc board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | DAC Controller                      |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | Real Time Clock                     |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB full-speed host/device bus      |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | Direct Memory Access Controller     |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| AES       | on-chip    | crypto                              |
-+-----------+------------+-------------------------------------+
-| LPTIM     | on-chip    | Low Power Timer                     |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_u083rc/nucleo_u083rc_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -222,6 +179,8 @@ USART2. Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo U083RC board includes an ST-LINK/V3 embedded debug tool interface.
 This probe allows to flash the board using various tools.
 
diff --git a/boards/st/nucleo_u083rc/nucleo_u083rc.dts b/boards/st/nucleo_u083rc/nucleo_u083rc.dts
index cfe5e149562..b9d1ca27c1b 100644
--- a/boards/st/nucleo_u083rc/nucleo_u083rc.dts
+++ b/boards/st/nucleo_u083rc/nucleo_u083rc.dts
@@ -153,7 +153,7 @@ stm32_lp_tick_source: &lptim1 {
 
 &spi1{
 	pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
-	cs-gpios = <&gpioa 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+	cs-gpios = <&gpiob 6 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
 	pinctrl-names = "default";
 	status = "okay";
 };
diff --git a/boards/st/nucleo_u083rc/nucleo_u083rc.yaml b/boards/st/nucleo_u083rc/nucleo_u083rc.yaml
index 833c40f2e86..8f2e316ba27 100644
--- a/boards/st/nucleo_u083rc/nucleo_u083rc.yaml
+++ b/boards/st/nucleo_u083rc/nucleo_u083rc.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - aes
diff --git a/boards/st/nucleo_u575zi_q/doc/index.rst b/boards/st/nucleo_u575zi_q/doc/index.rst
index 29dc145ce29..9824852f35b 100644
--- a/boards/st/nucleo_u575zi_q/doc/index.rst
+++ b/boards/st/nucleo_u575zi_q/doc/index.rst
@@ -138,47 +138,7 @@ More information about STM32U575ZI can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_u575zi_q board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| CAN/CANFD | on-chip    | canbus                              |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | DAC Controller                      |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| USB FS    | on-chip    | USB Full Speed device               |
-+-----------+------------+-------------------------------------+
-| BKP SRAM  | on-chip    | Backup SRAM                         |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_u575zi_q/nucleo_u575zi_q_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -238,6 +198,8 @@ do it by removing ``SB50`` jumper on the back side of the board.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo U575ZI-Q board includes an ST-LINK/V3 embedded debug tool interface.
 This probe allows to flash the board using various tools.
 
diff --git a/boards/st/nucleo_u5a5zj_q/doc/index.rst b/boards/st/nucleo_u5a5zj_q/doc/index.rst
index 794a2351d82..28e779822f4 100644
--- a/boards/st/nucleo_u5a5zj_q/doc/index.rst
+++ b/boards/st/nucleo_u5a5zj_q/doc/index.rst
@@ -172,47 +172,7 @@ More information about STM32U5A5ZJ can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_u5a5zj_q board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| CAN/CANFD | on-chip    | canbus                              |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | DAC Controller                      |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| BKP SRAM  | on-chip    | Backup SRAM                         |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB 2.0 HS                          |
-+-----------+------------+-------------------------------------+
-
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_u5a5zj_q/nucleo_u5a5zj_q_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -279,6 +239,8 @@ jumper settings.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo U5A5ZJ-Q board includes an ST-LINK/V3 embedded debug tool interface.
 This probe allows to flash the board using various tools.
 
diff --git a/boards/st/nucleo_wb05kz/board.cmake b/boards/st/nucleo_wb05kz/board.cmake
index a6b62f37ce2..84605805bba 100644
--- a/boards/st/nucleo_wb05kz/board.cmake
+++ b/boards/st/nucleo_wb05kz/board.cmake
@@ -1,7 +1,9 @@
 # SPDX-License-Identifier: Apache-2.0
 # keep first
-board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=sw")
+board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=sw" "--start-address=0x10000000")
+board_runner_args(pyocd "--target=stm32wb05kzvx")
 
 # keep first
 include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
diff --git a/boards/st/nucleo_wb05kz/doc/index.rst b/boards/st/nucleo_wb05kz/doc/index.rst
index 0c004e59952..2f7cae97d0a 100644
--- a/boards/st/nucleo_wb05kz/doc/index.rst
+++ b/boards/st/nucleo_wb05kz/doc/index.rst
@@ -30,36 +30,7 @@ More information about STM32WB05KZV can be found here:
 Supported Features
 ==================
 
-The Zephyr ``nucleo_wb05kz`` board target supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | internal flash memory               |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| RADIO     | on-chip    | Bluetooth Low Energy                |
-+-----------+------------+-------------------------------------+
-
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_wb09ke/nucleo_wb09ke_defconfig`
+.. zephyr:board-supported-hw::
 
 Bluetooh support
 ----------------
@@ -92,6 +63,8 @@ For more details, please refer to the `Nucleo WB05KZ board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo WB05KZ board includes an ST-LINK-V3EC embedded debug tool interface.
 
 Applications for the ``nucleo_w05kz`` board target can be built and flashed
@@ -135,6 +108,13 @@ You should see the following message on the console:
 
    Hello World! nucleo_wb05kz/stm32wb05
 
+Usage of the pyOCD runner requires installation of an additional target pack.
+This can be done using the following commands:
+
+.. code-block:: console
+
+   $ pyocd pack update
+   $ pyocd pack install stm32wb0
 
 Debugging
 =========
diff --git a/boards/st/nucleo_wb05kz/nucleo_wb05kz.dts b/boards/st/nucleo_wb05kz/nucleo_wb05kz.dts
index 88f37c00186..5961c1e9705 100644
--- a/boards/st/nucleo_wb05kz/nucleo_wb05kz.dts
+++ b/boards/st/nucleo_wb05kz/nucleo_wb05kz.dts
@@ -39,6 +39,14 @@
 		};
 	};
 
+	pwmleds: pwmleds {
+		compatible = "pwm-leds";
+		status = "okay";
+		pwm_red_led_1: pwm_led_1 {
+			pwms = <&pwm2 3 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+		};
+	};
+
 	gpio_keys {
 		compatible = "gpio-keys";
 		user_button_1: button_0 {
@@ -59,12 +67,15 @@
 	};
 
 	aliases {
+		rtc = &rtc;
 		led0 = &blue_led_1;
 		led1 = &green_led_1;
 		led2 = &red_led_1;
+		pwm-led0 = &pwm_red_led_1;
 		sw0 = &user_button_1;
 		sw1 = &user_button_2;
 		sw2 = &user_button_3;
+		watchdog0 = &iwdg;
 	};
 };
 
@@ -96,6 +107,20 @@
 	slow-clock = <&clk_lse>;
 };
 
+&rtc {
+	/**
+	 * STM32_SRC_LSE reflects the "slow-clock" selected on RCC node.
+	 * NO_SEL reflects STM32WB0's lack of RTC clock mux to configure.
+	 */
+	clocks = <&rcc STM32_CLOCK(APB0, 12)>,
+		<&rcc STM32_SRC_LSE NO_SEL>;
+	status = "okay";
+};
+
+&iwdg {
+	status = "okay";
+};
+
 &bt_hci_wb0 {
 	status = "okay";
 };
@@ -122,6 +147,19 @@
 		<&rcc STM32_SRC_SYSCLK SPI3_I2S3_SEL(3)>;
 };
 
+
+&timers2 {
+	status = "okay";
+	st,prescaler = <10000>;
+
+	pwm2: pwm {
+		/* PWM on red_led_1 */
+		pinctrl-0 = <&tim2_ch3_pb2>;
+		pinctrl-names = "default";
+		status = "okay";
+	};
+};
+
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
diff --git a/boards/st/nucleo_wb05kz/nucleo_wb05kz.yaml b/boards/st/nucleo_wb05kz/nucleo_wb05kz.yaml
index cf931e9bd37..874285b589d 100644
--- a/boards/st/nucleo_wb05kz/nucleo_wb05kz.yaml
+++ b/boards/st/nucleo_wb05kz/nucleo_wb05kz.yaml
@@ -5,16 +5,19 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 24
 flash: 192
 supported:
   - adc
   - arduino_i2c
   - arduino_spi
+  - counter
   - dma
   - gpio
   - i2c
+  - pwm
+  - rtc
   - spi
+  - watchdog
   - bluetooth
 vendor: st
diff --git a/boards/st/nucleo_wb05kz/support/openocd.cfg b/boards/st/nucleo_wb05kz/support/openocd.cfg
index 6d294443fcf..22338abf166 100644
--- a/boards/st/nucleo_wb05kz/support/openocd.cfg
+++ b/boards/st/nucleo_wb05kz/support/openocd.cfg
@@ -1,5 +1,3 @@
+set CHIPNAME bluenrg-lps
 source [find interface/stlink-dap.cfg]
-
-transport select "dapdirect_swd"
-
-source [find target/stm32wb0x.cfg]
+source [find target/bluenrg-x.cfg]
diff --git a/boards/st/nucleo_wb07cc/Kconfig.nucleo_wb07cc b/boards/st/nucleo_wb07cc/Kconfig.nucleo_wb07cc
new file mode 100644
index 00000000000..662643aeea7
--- /dev/null
+++ b/boards/st/nucleo_wb07cc/Kconfig.nucleo_wb07cc
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NUCLEO_WB07CC
+	select SOC_STM32WB07XX
diff --git a/boards/st/nucleo_wb07cc/arduino_r3_connector.dtsi b/boards/st/nucleo_wb07cc/arduino_r3_connector.dtsi
new file mode 100644
index 00000000000..75cb81bccfe
--- /dev/null
+++ b/boards/st/nucleo_wb07cc/arduino_r3_connector.dtsi
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	arduino_header: connector {
+		compatible = "arduino-header-r3";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+
+		/* Some pins are not connected to the Arduino
+		 * connector in default hardware configuration.
+		 * Only the connected pins are provided here.
+		 */
+		gpio-map = <0 0 &gpiob 3 0>,	/* A0 */
+			   <1 0 &gpiob 1 0>,	/* A1 */
+			   <2 0 &gpioa 15 0>,	/* A2 */
+			   <3 0 &gpioa 12 0>,	/* A3 */
+			   <4 0 &gpioa 14 0>,	/* A4 */
+			   <5 0 &gpioa 13 0>,	/* A5 */
+						/* D0 - N/C (PA8 via SB9) */
+						/* D1 - N/C (PA9 via SB7) */
+			   <8 0 &gpiob 15 0>,	/* D2 */
+						/* D3 - N/C (PA0 via SB3) */
+			   <10 0 &gpiob 11 0>,	/* D4 */
+			   <11 0 &gpiob 14 0>,	/* D5 */
+			   <12 0 &gpioa 11 0>,	/* D6 */
+			   <13 0 &gpiob 10 0>,	/* D7 */
+			   <14 0 &gpiob 8 0>,	/* D8 */
+			   <15 0 &gpioa 1 0>,	/* D9 */
+			   <16 0 &gpioa 4 0>,	/* D10 */
+			   <17 0 &gpioa 6 0>,	/* D11 */
+			   <18 0 &gpioa 7 0>,	/* D12 */
+			   <19 0 &gpioa 5 0>,	/* D13 */
+			   <20 0 &gpiob 7 0>,	/* D14 */
+			   <21 0 &gpiob 6 0>;	/* D15 */
+	};
+};
+
+arduino_i2c: &i2c2 {};
+arduino_serial: &usart1 {};
+arduino_spi: &spi2 {};
diff --git a/boards/st/nucleo_wb07cc/board.cmake b/boards/st/nucleo_wb07cc/board.cmake
new file mode 100644
index 00000000000..d68dc289165
--- /dev/null
+++ b/boards/st/nucleo_wb07cc/board.cmake
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+# keep first
+board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=sw" "--start-address=0x10000000")
+board_runner_args(pyocd "--target=stm32wb07ccvx")
+
+# keep first
+include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
diff --git a/boards/st/nucleo_wb07cc/board.yml b/boards/st/nucleo_wb07cc/board.yml
new file mode 100644
index 00000000000..fefbe534fc6
--- /dev/null
+++ b/boards/st/nucleo_wb07cc/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: nucleo_wb07cc
+  full_name: Nucleo WB07CC
+  vendor: st
+  socs:
+    - name: stm32wb07
diff --git a/boards/st/nucleo_wb07cc/doc/img/nucleo_wb07cc.webp b/boards/st/nucleo_wb07cc/doc/img/nucleo_wb07cc.webp
new file mode 100644
index 00000000000..93cefa87db0
Binary files /dev/null and b/boards/st/nucleo_wb07cc/doc/img/nucleo_wb07cc.webp differ
diff --git a/boards/st/nucleo_wb07cc/doc/index.rst b/boards/st/nucleo_wb07cc/doc/index.rst
new file mode 100644
index 00000000000..de36f37eeb4
--- /dev/null
+++ b/boards/st/nucleo_wb07cc/doc/index.rst
@@ -0,0 +1,144 @@
+.. zephyr:board:: nucleo_wb07cc
+
+Overview
+********
+
+The Nucleo WB07CC board is a Bluetooth |reg| Low Energy wireless and ultra-low-power
+board featuring an ARM Cortex |reg|-M0+ based STM32WB07CCV MCU, embedding a
+powerful and ultra-low-power radio compliant with the Bluetooth |reg| Low Energy
+SIG specification v5.4.
+
+More information about the board can be found on the `Nucleo WB07CC webpage`_.
+
+Hardware
+********
+
+Nucleo WB07CC provides the following hardware components:
+
+- STM32WB07CCV in VFQFPN32 package
+- ARM |reg| 32-bit Cortex |reg|-M0+ CPU
+- 64 MHz maximal CPU frequency
+- 256 KB Flash
+- 64 KB SRAM
+
+More information about STM32WB07CCV can be found here:
+
+- `WB07CC on www.st.com`_
+- `STM32WB07 reference manual`_
+
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Bluetooh support
+----------------
+
+BLE support is enabled; however, to build a Zephyr sample using this board,
+you first need to fetch the Bluetooth controller library into Zephyr as a binary BLOB.
+
+To fetch binary BLOBs:
+
+.. code-block:: console
+
+   west blobs fetch hal_stm32
+
+Connections and IOs
+===================
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+- USART1 TX/RX       : PA9/PA8 (ST-Link Virtual COM Port)
+- BUTTON (B1)        : PA0
+- BUTTON (B2)        : PB5
+- BUTTON (B3)        : PB9
+- LED (LD1/BLUE)     : PB0
+- LED (LD2/GREEN)    : PB4
+- LED (LD3/RED)      : PB2
+
+For more details, please refer to the `Nucleo WB07CC board User Manual`_.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Nucleo WB07CC board includes an ST-LINK-V3EC embedded debug tool interface.
+
+Applications for the ``nucleo_wb07cc`` board target can be built and flashed
+in the usual way (see :ref:`build_an_application` and :ref:`application_run`
+for more details).
+
+Flashing
+========
+
+The board is configured to be flashed using the west `STM32CubeProgrammer`_ runner,
+so :ref:`it must be installed <stm32cubeprog-flash-host-tools>` beforehand.
+
+Alternatively, OpenOCD can also be used to flash the board using the
+``--runner`` (or ``-r``) option:
+
+.. code-block:: console
+
+   $ west flash --runner openocd
+
+Flashing an application to Nucleo WB07CC
+----------------------------------------
+
+Connect the Nucleo WB07CC to your host computer using the USB port,
+then run a serial host program to connect with your Nucleo board:
+
+.. code-block:: console
+
+   $ minicom -D /dev/ttyACM0
+
+Now build and flash an application. Here is an example for
+:zephyr:code-sample:`hello_world`.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: nucleo_wb07cc
+   :goals: build flash
+
+You should see the following message on the console:
+
+.. code-block:: console
+
+   Hello World! nucleo_wb07cc/stm32wb07
+
+Usage of the pyOCD runner requires installation of an additional target pack.
+This can be done using the following commands:
+
+.. code-block:: console
+
+   $ pyocd pack update
+   $ pyocd pack install stm32wb0
+
+Debugging
+=========
+
+You can debug an application in the usual way.  Here is an example for the
+:zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: nucleo_wb07cc
+   :maybe-skip-config:
+   :goals: debug
+
+.. _`Nucleo WB07CC webpage`:
+   https://www.st.com/en/evaluation-tools/nucleo-wb07cc.html
+
+.. _`WB07CC on www.st.com`:
+   https://www.st.com/en/microcontrollers-microprocessors/stm32wb07cc.html
+
+.. _`STM32WB07 reference manual`:
+   https://www.st.com/resource/en/reference_manual/rm0530--stm32wb07xc-and-stm32wb06xc-ultralow-power-wireless-32bit-mcus-armbased-cortexm0-with-bluetooth-low-energy-and-24-ghz-radio-solution-stmicroelectronics.pdf
+
+.. _`Nucleo WB07CC board User Manual`:
+   https://www.st.com/resource/en/user_manual/um3344-stm32wb07-nucleo64-board-mb1801-and-mb2119-stmicroelectronics.pdf
+
+.. _STM32CubeProgrammer:
+   https://www.st.com/en/development-tools/stm32cubeprog.html
diff --git a/boards/st/nucleo_wb07cc/nucleo_wb07cc.dts b/boards/st/nucleo_wb07cc/nucleo_wb07cc.dts
new file mode 100644
index 00000000000..7d9d4012b5c
--- /dev/null
+++ b/boards/st/nucleo_wb07cc/nucleo_wb07cc.dts
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/wb0/stm32wb07Xc.dtsi>
+#include <st/wb0/stm32wb07ccvx-pinctrl.dtsi>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+#include "arduino_r3_connector.dtsi"
+
+/ {
+	model = "STMicroelectronics STM32WB07CC-NUCLEO board";
+	compatible = "st,stm32wb07cc-nucleo";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,bt-c2h-uart = &usart1;
+	};
+
+	leds: leds {
+		compatible ="gpio-leds";
+		blue_led_1: led_0 {
+			gpios = <&gpiob 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+		};
+		green_led_1: led_1 {
+			gpios = <&gpiob 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+		};
+		red_led_1: led_2 {
+			gpios = <&gpiob 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+		};
+	};
+
+	pwmleds: pwmleds {
+		compatible = "pwm-leds";
+		pwm_red_led_1: pwm_red_led_1 {
+			pwms = <&pwm1 3 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button_1: button_0 {
+			label = "SW1";
+			gpios = <&gpioa 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+		user_button_2: button_1 {
+			label = "SW2";
+			gpios = <&gpiob 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+		user_button_3: button_2 {
+			label = "SW3";
+			gpios = <&gpiob 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_2>;
+		};
+	};
+
+	aliases {
+		rtc = &rtc;
+		led0 = &blue_led_1;
+		led1 = &green_led_1;
+		led2 = &red_led_1;
+		pwm-led0 = &pwm_red_led_1;
+		sw0 = &user_button_1;
+		sw1 = &user_button_2;
+		sw2 = &user_button_3;
+		watchdog0 = &iwdg;
+	};
+};
+
+&pwrc {
+	smps-mode = "RUN";
+	smps-bom = <3>;
+};
+
+&clk_lse {
+	status = "okay";
+};
+
+&clk_hse {
+	status = "okay";
+};
+
+&clk_hsi {
+	status = "okay";
+};
+
+&pll {
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(64)>;
+	clksys-prescaler = <1>;
+	slow-clock = <&clk_lse>;
+};
+
+&rtc {
+	/**
+	 * STM32_SRC_LSE reflects the "slow-clock" selected on RCC node.
+	 * NO_SEL reflects STM32WB0's lack of RTC clock mux to configure.
+	 */
+	clocks = <&rcc STM32_CLOCK(APB0, 12)>,
+		<&rcc STM32_SRC_LSE NO_SEL>;
+	status = "okay";
+};
+
+&iwdg {
+	status = "okay";
+};
+
+&bt_hci_wb0 {
+	status = "okay";
+};
+
+&usart1 {
+	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa8>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_scl_pb6 &i2c2_sda_pb7>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&spi2 {
+	pinctrl-0 = <&spi2_nss_pa4 &spi2_sck_pa5 &spi2_miso_pa7 &spi2_mosi_pa6>;
+	pinctrl-names = "default";
+	status = "okay";
+	/* Select 32MHz clock for SPI2 */
+	clocks = <&rcc STM32_CLOCK(APB1, 12)>,
+		<&rcc STM32_SRC_SYSCLK SPI2_I2S2_SEL(1)>;
+};
+
+&timers1 {
+	status = "okay";
+	st,prescaler = <10000>;
+
+	pwm1: pwm {
+		status = "okay";
+		pinctrl-0 = <&tim1_ch3_pb2>;
+		pinctrl-names = "default";
+	};
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		/* Set aside 16KB of storage at the end of 256KB flash */
+		storage_partition: partition@3c000 {
+			label = "storage";
+			reg = <0x0003c000 DT_SIZE_K(16)>;
+		};
+	};
+};
diff --git a/boards/st/nucleo_wb07cc/nucleo_wb07cc.yaml b/boards/st/nucleo_wb07cc/nucleo_wb07cc.yaml
new file mode 100644
index 00000000000..bdd54761563
--- /dev/null
+++ b/boards/st/nucleo_wb07cc/nucleo_wb07cc.yaml
@@ -0,0 +1,23 @@
+identifier: nucleo_wb07cc
+name: ST Nucleo WB07CC
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 64
+flash: 256
+supported:
+  - adc
+  - arduino_i2c
+  - arduino_spi
+  - counter
+  - dma
+  - gpio
+  - i2c
+  - pwm
+  - rtc
+  - spi
+  - watchdog
+  - bluetooth
+vendor: st
diff --git a/boards/st/nucleo_wb07cc/nucleo_wb07cc_defconfig b/boards/st/nucleo_wb07cc/nucleo_wb07cc_defconfig
new file mode 100644
index 00000000000..0a45ef65e11
--- /dev/null
+++ b/boards/st/nucleo_wb07cc/nucleo_wb07cc_defconfig
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/st/nucleo_wb07cc/support/openocd.cfg b/boards/st/nucleo_wb07cc/support/openocd.cfg
new file mode 100644
index 00000000000..8c020c9afb6
--- /dev/null
+++ b/boards/st/nucleo_wb07cc/support/openocd.cfg
@@ -0,0 +1,3 @@
+set CHIPNAME bluenrg-lp
+source [find interface/stlink-dap.cfg]
+source [find target/bluenrg-x.cfg]
diff --git a/boards/st/nucleo_wb09ke/board.cmake b/boards/st/nucleo_wb09ke/board.cmake
index a6b62f37ce2..7f80e9325ae 100644
--- a/boards/st/nucleo_wb09ke/board.cmake
+++ b/boards/st/nucleo_wb09ke/board.cmake
@@ -1,7 +1,8 @@
 # SPDX-License-Identifier: Apache-2.0
 # keep first
-board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=sw")
+board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=sw" "--start-address=0x10000000")
+board_runner_args(pyocd "--target=stm32wb09kevx")
 
 # keep first
 include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
-include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
diff --git a/boards/st/nucleo_wb09ke/doc/index.rst b/boards/st/nucleo_wb09ke/doc/index.rst
index bab52ff1ba7..854e83c7ed8 100644
--- a/boards/st/nucleo_wb09ke/doc/index.rst
+++ b/boards/st/nucleo_wb09ke/doc/index.rst
@@ -30,36 +30,7 @@ More information about STM32WB09KEV can be found here:
 Supported Features
 ==================
 
-The Zephyr ``nucleo_wb09ke`` board target supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | internal flash memory               |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| RADIO     | on-chip    | Bluetooth Low Energy                |
-+-----------+------------+-------------------------------------+
-
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_wb09ke/nucleo_wb09ke_defconfig`
+.. zephyr:board-supported-hw::
 
 Bluetooh support
 ----------------
@@ -92,6 +63,8 @@ For more details, please refer to the `Nucleo WB09KE board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo WB09KE board includes an ST-LINK-V3EC embedded debug tool interface.
 
 Applications for the ``nucleo_w09ke`` board target can be built and flashed
@@ -148,6 +121,15 @@ You can debug an application in the usual way.  Here is an example for the
    :maybe-skip-config:
    :goals: debug
 
+.. warning::
+   Application debugging on this board uses the pyOCD runner, which requires an additional pack
+   to be installed beforehand. This can be performed using the following commands:
+
+   .. code-block:: console
+
+      $ pyocd pack update
+      $ pyocd pack install stm32wb0
+
 .. _`Nucleo WB09KE webpage`:
    https://www.st.com/en/evaluation-tools/nucleo-wb09ke.html
 
diff --git a/boards/st/nucleo_wb09ke/nucleo_wb09ke.dts b/boards/st/nucleo_wb09ke/nucleo_wb09ke.dts
index 1b8826ed884..ea7dcd708be 100644
--- a/boards/st/nucleo_wb09ke/nucleo_wb09ke.dts
+++ b/boards/st/nucleo_wb09ke/nucleo_wb09ke.dts
@@ -39,6 +39,14 @@
 		};
 	};
 
+	pwmleds: pwmleds {
+		compatible = "pwm-leds";
+		status = "okay";
+		pwm_red_led_1: pwm_led_1 {
+			pwms = <&pwm2 3 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+		};
+	};
+
 	gpio_keys {
 		compatible = "gpio-keys";
 		user_button_1: button_0 {
@@ -59,12 +67,15 @@
 	};
 
 	aliases {
+		rtc = &rtc;
 		led0 = &blue_led_1;
 		led1 = &green_led_1;
 		led2 = &red_led_1;
+		pwm-led0 = &pwm_red_led_1;
 		sw0 = &user_button_1;
 		sw1 = &user_button_2;
 		sw2 = &user_button_3;
+		watchdog0 = &iwdg;
 	};
 };
 
@@ -96,6 +107,20 @@
 	slow-clock = <&clk_lse>;
 };
 
+&rtc {
+	/**
+	 * STM32_SRC_LSE reflects the "slow-clock" selected on RCC node.
+	 * NO_SEL reflects STM32WB0's lack of RTC clock mux to configure.
+	 */
+	clocks = <&rcc STM32_CLOCK(APB0, 12)>,
+		<&rcc STM32_SRC_LSE NO_SEL>;
+	status = "okay";
+};
+
+&iwdg {
+	status = "okay";
+};
+
 &bt_hci_wb0 {
 	status = "okay";
 };
@@ -122,6 +147,18 @@
 		<&rcc STM32_SRC_SYSCLK SPI3_I2S3_SEL(3)>;
 };
 
+&timers2 {
+	status = "okay";
+	st,prescaler = <10000>;
+
+	pwm2: pwm {
+		/* PWM on red_led_1 */
+		pinctrl-0 = <&tim2_ch3_pb2>;
+		pinctrl-names = "default";
+		status = "okay";
+	};
+};
+
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
diff --git a/boards/st/nucleo_wb09ke/nucleo_wb09ke.yaml b/boards/st/nucleo_wb09ke/nucleo_wb09ke.yaml
index 20c4a33cfec..f8ca581c8d8 100644
--- a/boards/st/nucleo_wb09ke/nucleo_wb09ke.yaml
+++ b/boards/st/nucleo_wb09ke/nucleo_wb09ke.yaml
@@ -5,16 +5,19 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 512
 supported:
   - adc
   - arduino_i2c
   - arduino_spi
+  - counter
   - dma
   - gpio
   - i2c
+  - pwm
+  - rtc
   - spi
+  - watchdog
   - bluetooth
 vendor: st
diff --git a/boards/st/nucleo_wb09ke/support/openocd.cfg b/boards/st/nucleo_wb09ke/support/openocd.cfg
deleted file mode 100644
index 6d294443fcf..00000000000
--- a/boards/st/nucleo_wb09ke/support/openocd.cfg
+++ /dev/null
@@ -1,5 +0,0 @@
-source [find interface/stlink-dap.cfg]
-
-transport select "dapdirect_swd"
-
-source [find target/stm32wb0x.cfg]
diff --git a/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst b/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst
index 0aa7928ca2a..18c9655b54b 100644
--- a/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst
+++ b/boards/st/nucleo_wb55rg/doc/nucleo_wb55rg.rst
@@ -132,47 +132,13 @@ provides the following hardware capabilities:
 More information about STM32WB55RG can be found here:
 
 - `STM32WB55RG on www.st.com`_
-- `STM32WB5RG datasheet`_
-- `STM32WB5RG reference manual`_
+- `STM32WB55RG datasheet`_
+- `STM32WB55RG reference manual`_
 
 Supported Features
 ==================
 
-The Zephyr nucleo_wb55rg board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| RADIO     | on-chip    | Bluetooth Low Energy                |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_wb55rg/nucleo_wb55rg_defconfig`
+.. zephyr:board-supported-hw::
 
 Bluetooth and compatibility with STM32WB Copro Wireless Binaries
 ================================================================
@@ -180,10 +146,11 @@ Bluetooth and compatibility with STM32WB Copro Wireless Binaries
 To operate bluetooth on Nucleo WB55RG, Cortex-M0 core should be flashed with
 a valid STM32WB Coprocessor binaries (either 'Full stack' or 'HCI Layer').
 These binaries are delivered in STM32WB Cube packages, under
-Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/
+``Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/``
+
 For compatibility information with the various versions of these binaries,
-please check `modules/hal/stm32/lib/stm32wb/hci/README <https://github.com/zephyrproject-rtos/hal_stm32/blob/main/lib/stm32wb/hci/README>`__
-in the hal_stm32 repo.
+please check :module_file:`hal_stm32:lib/stm32wb/README.rst`.
+
 Note that since STM32WB Cube package V1.13.2, "full stack" binaries are not compatible
 anymore for a use in Zephyr and only "HCI Only" versions should be used on the M0
 side.
@@ -234,6 +201,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo WB55RG board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``nucleo_wb55rg`` board configuration can be built the
@@ -306,10 +275,10 @@ You can debug an application in the usual way.  Here is an example for the
 .. _STM32WB55RG on www.st.com:
    https://www.st.com/en/microcontrollers-microprocessors/stm32wb55rg.html
 
-.. _STM32WB5RG datasheet:
+.. _STM32WB55RG datasheet:
    https://www.st.com/resource/en/datasheet/stm32wb55rg.pdf
 
-.. _STM32WB5RG reference manual:
+.. _STM32WB55RG reference manual:
    https://www.st.com/resource/en/reference_manual/dm00318631.pdf
 
 .. _STM32CubeProgrammer:
diff --git a/boards/st/nucleo_wb55rg/nucleo_wb55rg.yaml b/boards/st/nucleo_wb55rg/nucleo_wb55rg.yaml
index c99ca8712b4..f4e2a417dca 100644
--- a/boards/st/nucleo_wb55rg/nucleo_wb55rg.yaml
+++ b/boards/st/nucleo_wb55rg/nucleo_wb55rg.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 192
 flash: 808
 supported:
diff --git a/boards/st/nucleo_wba52cg/Kconfig.defconfig b/boards/st/nucleo_wba52cg/Kconfig.defconfig
deleted file mode 100644
index 6bf6d3f610f..00000000000
--- a/boards/st/nucleo_wba52cg/Kconfig.defconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# STM32WBA52CG Nucleo board configuration
-
-# Copyright (c) 2023 STMicroelectronics
-
-# SPDX-License-Identifier: Apache-2.0
-
-if BOARD_NUCLEO_WBA52CG
-
-config SPI_STM32_INTERRUPT
-	default y
-	depends on SPI
-
-endif # BOARD_NUCLEO_WBA52CG
diff --git a/boards/st/nucleo_wba52cg/Kconfig.nucleo_wba52cg b/boards/st/nucleo_wba52cg/Kconfig.nucleo_wba52cg
deleted file mode 100644
index 515685e5715..00000000000
--- a/boards/st/nucleo_wba52cg/Kconfig.nucleo_wba52cg
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright (c) 2023 STMicroelectronics
-# SPDX-License-Identifier: Apache-2.0
-
-config BOARD_NUCLEO_WBA52CG
-	select SOC_STM32WBA52XX
diff --git a/boards/st/nucleo_wba52cg/arduino_r3_connector.dtsi b/boards/st/nucleo_wba52cg/arduino_r3_connector.dtsi
deleted file mode 100644
index 619cebea62a..00000000000
--- a/boards/st/nucleo_wba52cg/arduino_r3_connector.dtsi
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Copyright (c) 2023 STMicroelectronics
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
-	arduino_header: connector {
-		compatible = "arduino-header-r3";
-		#gpio-cells = <2>;
-		gpio-map-mask = <0xffffffff 0xffffffc0>;
-		gpio-map-pass-thru = <0 0x3f>;
-		gpio-map = <0 0 &gpioa 7 0>,	/* A0 */
-			   <1 0 &gpioa 6 0>,	/* A1 */
-			   <2 0 &gpioa 2 0>,	/* A2 */
-			   <3 0 &gpioa 1 0>,	/* A3 */
-			   <4 0 &gpioa 5 0>,	/* A4 */
-			   <5 0 &gpioa 0 0>,	/* A5 */
-			   <6 0 &gpioa 10 0>,	/* D0 */
-			   <7 0 &gpiob 5 0>,	/* D1 */
-			   <8 0 &gpiob 7 0>,	/* D2 */
-			   <9 0 &gpiob 6 0>,	/* D3 */
-			   <10 0 &gpiob 13 0>,	/* D4 */
-			   <11 0 &gpiob 14 0>,	/* D5 */
-			   <12 0 &gpiob 0 0>,	/* D6 */
-			   <13 0 &gpiob 9 0>,	/* D7 */
-			   <14 0 &gpiob 15 0>,	/* D8 */
-			   <15 0 &gpioa 9 0>,	/* D9 */
-			   <16 0 &gpioa 12 0>,	/* D10 */
-			   <17 0 &gpioa 15 0>,	/* D11 */
-			   <18 0 &gpiob 3 0>,	/* D12 */
-			   <19 0 &gpiob 4 0>,	/* D13 */
-			   <20 0 &gpiob 1 0>,	/* D14 */
-			   <21 0 &gpiob 2 0>;	/* D15 */
-	};
-};
-
-arduino_i2c: &i2c1 {};
-arduino_spi: &spi1 {};
diff --git a/boards/st/nucleo_wba52cg/board.cmake b/boards/st/nucleo_wba52cg/board.cmake
deleted file mode 100644
index 9c612e9d0b0..00000000000
--- a/boards/st/nucleo_wba52cg/board.cmake
+++ /dev/null
@@ -1,6 +0,0 @@
-# keep first
-board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
-
-# keep first
-include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
-include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/st/nucleo_wba52cg/board.yml b/boards/st/nucleo_wba52cg/board.yml
deleted file mode 100644
index 0b12139fcf2..00000000000
--- a/boards/st/nucleo_wba52cg/board.yml
+++ /dev/null
@@ -1,6 +0,0 @@
-board:
-  name: nucleo_wba52cg
-  full_name: Nucleo WBA52CG
-  vendor: st
-  socs:
-    - name: stm32wba52xx
diff --git a/boards/st/nucleo_wba52cg/doc/img/nucleowba52cg.jpg b/boards/st/nucleo_wba52cg/doc/img/nucleowba52cg.jpg
deleted file mode 100644
index 67c7d351e99..00000000000
Binary files a/boards/st/nucleo_wba52cg/doc/img/nucleowba52cg.jpg and /dev/null differ
diff --git a/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst b/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst
deleted file mode 100644
index c27dc4a56a5..00000000000
--- a/boards/st/nucleo_wba52cg/doc/nucleo_wba52cg.rst
+++ /dev/null
@@ -1,292 +0,0 @@
-.. zephyr:board:: nucleo_wba52cg
-
-Overview
-********
-
-NUCLEO-WBA52CG is a Bluetooth® Low Energy wireless and ultra-low-power board
-embedding a powerful and ultra-low-power radio compliant with the Bluetooth®
-Low Energy SIG specification v5.3.
-
-The ARDUINO® Uno V3 connectivity support and the ST morpho headers allow the
-easy expansion of the functionality of the STM32 Nucleo open development
-platform with a wide choice of specialized shields.
-
-- Ultra-low-power wireless STM32WBA52CG microcontroller based on the Arm®
-  Cortex®‑M33 core, featuring 1 Mbyte of flash memory and 128 Kbytes of SRAM in
-  a UFQFPN48 package
-
-- MCU RF board (MB1863):
-
-  - 2.4 GHz RF transceiver supporting Bluetooth® specification v5.3
-  - Arm® Cortex® M33 CPU with TrustZone®, MPU, DSP, and FPU
-  - Integrated PCB antenna
-
-- Three user LEDs
-- Three user and one reset push-buttons
-
-- Board connectors:
-
-  - USB Micro-B
-  - ARDUINO® Uno V3 expansion connector
-  - ST morpho headers for full access to all STM32 I/Os
-
-- Flexible power-supply options: ST-LINK USB VBUS or external sources
-- On-board STLINK-V3MODS debugger/programmer with USB re-enumeration capability:
-  mass storage, Virtual COM port, and debug port
-
-More information about the board can be found at the `Nucleo WBA52CG website`_.
-
-Hardware
-********
-
-The STM32WBA52xx multiprotocol wireless and ultralow power devices embed a
-powerful and ultralow power radio compliant with the Bluetooth® SIG Low Energy
-specification 5.3. They contain a high-performance Arm Cortex-M33 32-bit RISC
-core. They operate at a frequency of up to 100 MHz.
-
-- Includes ST state-of-the-art patented technology
-
-- Ultra low power radio:
-
-  - 2.4 GHz radio
-  - RF transceiver supporting Bluetooth® Low Energy 5.3 specification
-  - Proprietary protocols
-  - RX sensitivity: -96 dBm (Bluetooth® Low Energy at 1 Mbps)
-  - Programmable output power, up to +10 dBm with 1 dB steps
-  - Integrated balun to reduce BOM
-  - Suitable for systems requiring compliance with radio frequency regulations
-    ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66
-
-- Ultra low power platform with FlexPowerControl:
-
-  - 1.71 to 3.6 V power supply
-  - - 40 °C to 85 °C temperature range
-  - Autonomous peripherals with DMA, functional down to Stop 1 mode
-  - 140 nA Standby mode (16 wake-up pins)
-  - 200 nA Standby mode with RTC
-  - 2.4 µA Standby mode with 64 KB SRAM
-  - 16.3 µA Stop mode with 64 KB SRAM
-  - 45 µA/MHz Run mode at 3.3 V
-  - Radio: Rx 7.4 mA / Tx at 0 dBm 10.6 mA
-
-- Core: Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, and FPU
-- ART Accelerator™: 8-Kbyte instruction cache allowing 0-wait-state execution
-  from flash memory (frequency up to 100 MHz, 150 DMIPS)
-- Power management: embedded regulator LDO supporting voltage scaling
-
-- Benchmarks:
-
-  - 1.5 DMIPS/MHz (Drystone 2.1)
-  - 407 CoreMark® (4.07 CoreMark/MHz)
-
-- Clock sources:
-
-  - 32 MHz crystal oscillator
-  - 32 kHz crystal oscillator (LSE)
-  - Internal low-power 32 kHz (±5%) RC
-  - Internal 16 MHz factory trimmed RC (±1%)
-  - PLL for system clock and ADC
-
-- Memories:
-
-  - 1 MB flash memory with ECC, including 256 Kbytes with 100 cycles
-  - 128 KB SRAM, including 64 KB with parity check
-  - 512-byte (32 rows) OTP
-
-- Rich analog peripherals (independent supply):
-
-  - 12-bit ADC 2.5 Msps with hardware oversampling
-
-- Communication peripherals:
-
-  - Three UARTs (ISO 7816, IrDA, modem)
-  - Two SPIs
-  - Two I2C Fm+ (1 Mbit/s), SMBus/PMBus®
-
-- System peripherals:
-
-  - Touch sensing controller, up to 20 sensors, supporting touch key, linear,
-     rotary touch sensors
-  - One 16-bit, advanced motor control timer
-  - Three 16-bit timers
-  - One 32-bit timer
-  - Two low-power 16-bit timers (available in Stop mode)
-  - Two Systick timers
-  - Two watchdogs
-  - 8-channel DMA controller, functional in Stop mode
-
-- Security and cryptography:
-
-  - Arm® TrustZone® and securable I/Os, memories, and peripherals
-  - Flexible life cycle scheme with RDP and password protected debug
-  - Root of trust thanks to unique boot entry and secure hide protection area (HDP)
-  - SFI (secure firmware installation) thanks to embedded RSS (root secure services)
-  - Secure data storage with root hardware unique key (RHUK)
-  - Secure firmware upgrade support with TF-M
-  - Two AES co-processors, including one with DPA resistance
-  - Public key accelerator, DPA resistant
-  - HASH hardware accelerator
-  - True random number generator, NIST SP800-90B compliant
-  - 96-bit unique ID
-  - Active tampers
-  - CRC calculation unit
-
-- Up to 35 I/Os (most of them 5 V-tolerant) with interrupt capability
-
-- Development support:
-
-  - Serial wire debug (SWD), JTAG
-
-- ECOPACK2 compliant package
-
-More information about STM32WB55RG can be found here:
-
-- `STM32WBA52CG on www.st.com`_
-- `STM32WBA52CG datasheet`_
-- `STM32WBA52CG reference manual`_
-
-Supported Features
-==================
-
-The Zephyr nucleo_wba52cg board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_wba52cg/nucleo_wba52cg_defconfig`
-
-Connections and IOs
-===================
-
-Nucleo WBA52CG Board has 4 GPIO controllers. These controllers are responsible for pin muxing,
-input/output, pull-up, etc.
-
-Default Zephyr Peripheral Mapping:
-----------------------------------
-
-.. rst-class:: rst-columns
-
-- USART_1 TX/RX : PB12/PA8
-- I2C_1_SCL : PB2
-- I2C_1_SDA : PB1
-- USER_PB : PC13
-- LD1 : PB4
-- SPI_1_NSS : PA12 (arduino_spi)
-- SPI_1_SCK : PB4 (arduino_spi)
-- SPI_1_MISO : PB3 (arduino_spi)
-- SPI_1_MOSI : PA15 (arduino_spi)
-
-System Clock
-------------
-
-Nucleo WBA52CG System Clock could be driven by internal or external oscillator,
-as well as main PLL clock. By default System clock is driven by HSE+PLL clock at 100MHz.
-
-Serial Port
------------
-
-Nucleo WBA52CG board has 1 U(S)ARTs. The Zephyr console output is assigned to USART1.
-Default settings are 115200 8N1.
-
-
-Programming and Debugging
-*************************
-
-Nucleo WBA52CG board includes an ST-LINK/V3 embedded debug tool interface.
-It could be used for flash and debug using either OpenOCD or STM32Cube ecosystem tools.
-
-Flashing
-========
-
-The board is configured to be flashed using west `STM32CubeProgrammer`_ runner,
-so its :ref:`installation <stm32cubeprog-flash-host-tools>` is required.
-
-Alternatively, OpenOCD can also be used to flash the board using
-the ``--runner`` (or ``-r``) option:
-
-.. code-block:: console
-
-   $ west flash --runner openocd
-
-Flashing an application to Nucleo WBA52CG
------------------------------------------
-
-Here is an example for the :zephyr:code-sample:`blinky` application.
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/basic/blinky
-   :board: nucleo_wba52cg
-   :goals: build flash
-
-You will see the LED blinking every second.
-
-Debugging
-=========
-
-Debugging using OpenOCD
------------------------
-
-You can debug an application in the usual way using OpenOCD. Here is an example for the
-:zephyr:code-sample:`blinky` application.
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/basic/blinky
-   :board: nucleo_wba52cg
-   :maybe-skip-config:
-   :goals: debug
-
-Debugging using STM32CubeIDE
-----------------------------
-
-You can debug an application using a STM32WBA compatible version of STM32CubeIDE.
-
-For that:
-
-- Create an empty STM32WBA project by going to File > New > STM32 project
-- Select your MCU, click Next, and select an Empty project.
-- Right click on your project name, select Debug as > Debug configurations
-- In the new window, create a new target in STM32 Cortex-M C/C++ Application
-- Select the new target and enter the path to zephyr.elf file in the C/C++ Application field
-- Check Disable auto build
-- Run debug
-
-.. _Nucleo WBA52CG website:
-   https://www.st.com/en/evaluation-tools/nucleo-wba52cg.html
-
-.. _STM32WBA52CG on www.st.com:
-   https://www.st.com/en/microcontrollers-microprocessors/stm32wba52cg.html
-
-.. _STM32WBA52CG datasheet:
-   https://www.st.com/resource/en/datasheet/stm32wba52cg.pdf
-
-.. _STM32WBA52CG reference manual:
-   https://www.st.com/resource/en/reference_manual/rm0493-multiprotocol-wireless-bluetooth-lowenergy-armbased-32bit-mcu-stmicroelectronics.pdf
-
-.. _OpenOCD official Github mirror:
-   https://github.com/openocd-org/openocd/commit/870769b0ba9f4dae6ada9d8b1a40d75bd83aaa06
-
-.. _STM32CubeProgrammer:
-   https://www.st.com/en/development-tools/stm32cubeprog.html
diff --git a/boards/st/nucleo_wba52cg/nucleo_wba52cg.dts b/boards/st/nucleo_wba52cg/nucleo_wba52cg.dts
deleted file mode 100644
index 08b81dba0dc..00000000000
--- a/boards/st/nucleo_wba52cg/nucleo_wba52cg.dts
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * Copyright (c)  2023 STMicroelectronics
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/dts-v1/;
-#include <st/wba/stm32wba52Xg.dtsi>
-#include <st/wba/stm32wba52cgux-pinctrl.dtsi>
-#include "arduino_r3_connector.dtsi"
-#include <zephyr/dt-bindings/input/input-event-codes.h>
-
-/ {
-	model = "STMicroelectronics STM32WBA52CG-NUCLEO board";
-	compatible = "st,stm32wba52cg-nucleo";
-
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	chosen {
-		zephyr,console = &usart1;
-		zephyr,shell-uart = &usart1;
-		zephyr,sram = &sram0;
-		zephyr,flash = &flash0;
-		zephyr,code-partition = &slot0_partition;
-	};
-
-	leds: leds {
-		compatible = "gpio-leds";
-		blue_led_1: led_1 {
-			gpios = <&gpiob 4 GPIO_ACTIVE_LOW>;
-			label = "User LD1";
-		};
-	};
-
-	gpio_keys {
-		compatible = "gpio-keys";
-		user_button: button {
-			label = "User";
-			gpios = <&gpioc 13 GPIO_ACTIVE_LOW>;
-			zephyr,code = <INPUT_KEY_0>;
-		};
-	};
-
-	aliases {
-		led0 = &blue_led_1;
-		sw0 = &user_button;
-	};
-};
-
-&clk_lsi {
-	status = "okay";
-};
-
-&clk_lse {
-	status = "okay";
-};
-
-&clk_hse {
-	status = "okay";
-};
-
-&clk_hsi {
-	status = "okay";
-};
-
-&pll1 {
-	div-m = <8>;
-	mul-n = <48>;
-	div-q = <2>;
-	div-r = <2>;
-	clocks = <&clk_hse>;
-	status = "okay";
-};
-
-&rcc {
-	clocks = <&pll1>;
-	clock-frequency = <DT_FREQ_M(96)>;
-	ahb-prescaler = <1>;
-	ahb5-prescaler = <4>;
-	apb1-prescaler = <1>;
-	apb2-prescaler = <1>;
-	apb7-prescaler = <1>;
-};
-
-&iwdg {
-	status = "okay";
-};
-
-&rtc {
-	status = "okay";
-	clocks = <&rcc STM32_CLOCK_BUS_APB7 0x00200000>,
-			<&rcc STM32_SRC_LSE RTC_SEL(1)>;
-	prescaler = <32768>;
-};
-
-&usart1 {
-	pinctrl-0 = <&usart1_tx_pb12 &usart1_rx_pa8>;
-	pinctrl-names = "default";
-	current-speed = <115200>;
-	status = "okay";
-};
-
-&lpuart1 {
-	pinctrl-0 = <&lpuart1_tx_pb5 &lpuart1_rx_pa10>;
-	pinctrl-names = "default";
-	current-speed = <115200>;
-	status = "okay";
-};
-
-&spi1 {
-	pinctrl-0 = <&spi1_nss_pa12 &spi1_sck_pb4
-		     &spi1_miso_pb3 &spi1_mosi_pa15>;
-	pinctrl-names = "default";
-	status = "okay";
-};
-
-&i2c1 {
-	pinctrl-0 = <&i2c1_scl_pb2 &i2c1_sda_pb1>;
-	pinctrl-names = "default";
-	status = "okay";
-	clock-frequency = <I2C_BITRATE_FAST>;
-};
-
-&adc4 {
-	pinctrl-0 = <&adc4_in8_pa1>;
-	pinctrl-names = "default";
-	st,adc-clock-source = "ASYNC";
-	st,adc-prescaler = <4>;
-	status = "okay";
-};
-
-stm32_lp_tick_source: &lptim1 {
-	clocks = <&rcc STM32_CLOCK_BUS_APB7 0x00000800>,
-		 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
-	status = "okay";
-};
-
-&rng {
-	status = "okay";
-};
-
-&flash0 {
-	partitions {
-		compatible = "fixed-partitions";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		boot_partition: partition@0 {
-			label = "mcuboot";
-			reg = <0x00000000 DT_SIZE_K(64)>;
-		};
-		slot0_partition: partition@10000 {
-			label = "image-0";
-			reg = <0x00010000 DT_SIZE_K(448)>;
-		};
-		slot1_partition: partition@80000 {
-			label = "image-1";
-			reg = <0x00080000 DT_SIZE_K(448)>;
-		};
-		scratch_partition: partition@f0000 {
-			label = "image-scratch";
-			reg = <0x000f0000 DT_SIZE_K(16)>;
-		};
-		storage_partition: partition@f4000 {
-			label = "storage";
-			reg = <0x000f4000 DT_SIZE_K(48)>;
-		};
-	};
-};
diff --git a/boards/st/nucleo_wba52cg/nucleo_wba52cg.yaml b/boards/st/nucleo_wba52cg/nucleo_wba52cg.yaml
deleted file mode 100644
index 8e075b44ae1..00000000000
--- a/boards/st/nucleo_wba52cg/nucleo_wba52cg.yaml
+++ /dev/null
@@ -1,21 +0,0 @@
-identifier: nucleo_wba52cg
-name: ST Nucleo WBA52CG
-type: mcu
-arch: arm
-toolchain:
-  - zephyr
-  - gnuarmemb
-supported:
-  - gpio
-  - i2c
-  - spi
-  - adc
-  - watchdog
-  - rng
-  - arduino_gpio
-  - arduino_i2c
-  - arduino_spi
-  - counter
-ram: 128
-flash: 1024
-vendor: st
diff --git a/boards/st/nucleo_wba52cg/nucleo_wba52cg_defconfig b/boards/st/nucleo_wba52cg/nucleo_wba52cg_defconfig
deleted file mode 100644
index 8655ea99d42..00000000000
--- a/boards/st/nucleo_wba52cg/nucleo_wba52cg_defconfig
+++ /dev/null
@@ -1,17 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-# enable uart driver
-CONFIG_SERIAL=y
-
-# enable GPIO
-CONFIG_GPIO=y
-
-# console
-CONFIG_CONSOLE=y
-CONFIG_UART_CONSOLE=y
-
-# Enable MPU
-CONFIG_ARM_MPU=y
-
-# Enable HW stack protection
-CONFIG_HW_STACK_PROTECTION=y
diff --git a/boards/st/nucleo_wba52cg/support/openocd.cfg b/boards/st/nucleo_wba52cg/support/openocd.cfg
deleted file mode 100644
index 7c785bec412..00000000000
--- a/boards/st/nucleo_wba52cg/support/openocd.cfg
+++ /dev/null
@@ -1,24 +0,0 @@
-# Note: Using OpenOCD using nucloe_wba52cg requires using STMicroelectronics
-# openocd fork. See board documentation for more information
-
-source [find interface/stlink-dap.cfg]
-
-set WORKAREASIZE 0x8000
-
-transport select "dapdirect_swd"
-
-# Enable debug when in low power modes
-set ENABLE_LOW_POWER 1
-
-# Stop Watchdog counters when halt
-set STOP_WATCHDOG 1
-
-# STlink Debug clock frequency
-set CLOCK_FREQ 8000
-
-# Reset configuration
-# use hardware reset, connect under reset
-# connect_assert_srst needed if low power mode application running (WFI...)
-reset_config srst_only srst_nogate
-
-source [find target/stm32wbax.cfg]
diff --git a/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst b/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst
index affcf8c4c49..c07b352f17f 100644
--- a/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst
+++ b/boards/st/nucleo_wba55cg/doc/nucleo_wba55cg.rst
@@ -144,39 +144,7 @@ More information about STM32WBA series can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_wba55cg board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| RADIO     | on-chip    | Bluetooth Low Energy                |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/nucleo_wba55cg/nucleo_wba55cg_defconfig`
+.. zephyr:board-supported-hw::
 
 Bluetooh support
 ----------------
@@ -228,6 +196,8 @@ Default settings are 115500 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo WBA55CG board includes an ST-LINK/V3 embedded debug tool interface.
 It could be used for flash and debug using either OpenOCD or STM32Cube ecosystem tools.
 
diff --git a/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts b/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts
index 2070611b326..908e2cec593 100644
--- a/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts
+++ b/boards/st/nucleo_wba55cg/nucleo_wba55cg.dts
@@ -43,6 +43,14 @@
 		};
 	};
 
+	pwmleds: pwmleds {
+		compatible = "pwm-leds";
+
+		green_pwm_led: green_pwm_led {
+			pwms = <&pwm3 2 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+		};
+	};
+
 	gpio_keys {
 		compatible = "gpio-keys";
 		user_button_1: button_0 {
@@ -66,6 +74,7 @@
 		led0 = &blue_led_1;
 		led1 = &green_led_2;
 		led2 = &red_led_3;
+		pwm-led0 = &green_pwm_led;
 		sw0 = &user_button_1;
 		sw1 = &user_button_2;
 		sw2 = &user_button_3;
@@ -123,6 +132,16 @@
 	status = "okay";
 };
 
+&usart2 {
+	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00020000>,
+		 <&rcc STM32_SRC_HSI16 USART2_SEL(2)>;
+	pinctrl-0 = <&usart2_tx_pa12 &usart2_rx_pb8>;
+	pinctrl-1 = <&analog_pa12 &analog_pb8>;
+	pinctrl-names = "default", "sleep";
+	current-speed = <115200>;
+	status = "okay";
+};
+
 &lpuart1 {
 	pinctrl-0 = <&lpuart1_tx_pb5 &lpuart1_rx_pa10>;
 	pinctrl-names = "default";
@@ -156,6 +175,17 @@
 	status = "okay";
 };
 
+&timers3 {
+	st,prescaler = <10000>;
+	status = "okay";
+
+	pwm3: pwm {
+		status = "okay";
+		pinctrl-0 = <&tim3_ch2_pa9>;
+		pinctrl-names = "default";
+	};
+};
+
 stm32_lp_tick_source: &lptim1 {
 	clocks = <&rcc STM32_CLOCK_BUS_APB7 0x00000800>,
 		 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
diff --git a/boards/st/nucleo_wba55cg/support/openocd.cfg b/boards/st/nucleo_wba55cg/support/openocd.cfg
index 1715e7d026e..1c3a1523239 100644
--- a/boards/st/nucleo_wba55cg/support/openocd.cfg
+++ b/boards/st/nucleo_wba55cg/support/openocd.cfg
@@ -19,6 +19,6 @@ set CLOCK_FREQ 8000
 # Reset configuration
 # use hardware reset, connect under reset
 # connect_assert_srst needed if low power mode application running (WFI...)
-reset_config srst_only srst_nogate
+reset_config srst_nogate
 
 source [find target/stm32wbax.cfg]
diff --git a/boards/st/nucleo_wba65ri/Kconfig.defconfig b/boards/st/nucleo_wba65ri/Kconfig.defconfig
new file mode 100644
index 00000000000..8e937f2a6ad
--- /dev/null
+++ b/boards/st/nucleo_wba65ri/Kconfig.defconfig
@@ -0,0 +1,13 @@
+# STM32WBA65RI Nucleo board configuration
+
+# Copyright (c) 2025 STMicroelectronics
+
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_NUCLEO_WBA65RI
+
+config SPI_STM32_INTERRUPT
+	default y
+	depends on SPI
+
+endif # BOARD_NUCLEO_WBA65RI
diff --git a/boards/st/nucleo_wba65ri/Kconfig.nucleo_wba65ri b/boards/st/nucleo_wba65ri/Kconfig.nucleo_wba65ri
new file mode 100644
index 00000000000..35b3adb2ab3
--- /dev/null
+++ b/boards/st/nucleo_wba65ri/Kconfig.nucleo_wba65ri
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NUCLEO_WBA65RI
+	select SOC_STM32WBA65XX
diff --git a/boards/st/nucleo_wba65ri/arduino_r3_connector.dtsi b/boards/st/nucleo_wba65ri/arduino_r3_connector.dtsi
new file mode 100644
index 00000000000..44e824e4664
--- /dev/null
+++ b/boards/st/nucleo_wba65ri/arduino_r3_connector.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	arduino_header: connector {
+		compatible = "arduino-header-r3";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpioa 4 0>,	/* A0 */
+			   <1 0 &gpioa 6 0>,	/* A1 */
+			   <2 0 &gpioa 2 0>,	/* A2 */
+			   <3 0 &gpioa 1 0>,	/* A3 */
+			   <4 0 &gpioa 5 0>,	/* A4 */
+			   <5 0 &gpioa 0 0>,	/* A5 */
+			   <6 0 &gpioa 11 0>,	/* D0 */
+			   <7 0 &gpioa 12 0>,	/* D1 */
+			   <8 0 &gpioe 0 0>,	/* D2 */
+			   <9 0 &gpiob 13 0>,	/* D3 */
+			   <10 0 &gpioa 3 0>,	/* D4 */
+			   <11 0 &gpiob 14 0>,	/* D5 */
+			   <12 0 &gpiob 0 0>,	/* D6 */
+			   <13 0 &gpiod 14 0>,	/* D7 */
+			   <14 0 &gpioa 10 0>,	/* D8 */
+			   <15 0 &gpiob 11 0>,	/* D9 */
+			   <16 0 &gpiob 9 0>,	/* D10 */
+			   <17 0 &gpioc 3 0>,	/* D11 */
+			   <18 0 &gpioa 9 0>,	/* D12 */
+			   <19 0 &gpiob 10 0>,	/* D13 */
+			   <20 0 &gpiob 1 0>,	/* D14 */
+			   <21 0 &gpiob 2 0>;	/* D15 */
+	};
+};
+
+arduino_i2c: &i2c1 {};
+arduino_spi: &spi1 {};
diff --git a/boards/st/nucleo_wba65ri/board.cmake b/boards/st/nucleo_wba65ri/board.cmake
new file mode 100644
index 00000000000..5243407fcc0
--- /dev/null
+++ b/boards/st/nucleo_wba65ri/board.cmake
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
+
+include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/st/nucleo_wba65ri/board.yml b/boards/st/nucleo_wba65ri/board.yml
new file mode 100644
index 00000000000..01a51d7715d
--- /dev/null
+++ b/boards/st/nucleo_wba65ri/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: nucleo_wba65ri
+  full_name: Nucleo WBA65RI
+  vendor: st
+  socs:
+    - name: stm32wba65xx
diff --git a/boards/st/nucleo_wba65ri/doc/img/nucleo_wba65ri.webp b/boards/st/nucleo_wba65ri/doc/img/nucleo_wba65ri.webp
new file mode 100644
index 00000000000..a9959ba55a9
Binary files /dev/null and b/boards/st/nucleo_wba65ri/doc/img/nucleo_wba65ri.webp differ
diff --git a/boards/st/nucleo_wba65ri/doc/nucleo_wba65ri.rst b/boards/st/nucleo_wba65ri/doc/nucleo_wba65ri.rst
new file mode 100644
index 00000000000..1452d65987a
--- /dev/null
+++ b/boards/st/nucleo_wba65ri/doc/nucleo_wba65ri.rst
@@ -0,0 +1,241 @@
+.. zephyr:board:: nucleo_wba65ri
+
+Overview
+********
+
+NUCLEO-WBA65RI is a Bluetooth® Low Energy, 802.15.4 and Zigbee® wireless
+and ultra-low-power board embedding a powerful and ultra-low-power radio
+compliant with the Bluetooth® Low Energy SIG specification v5.4
+with IEEE 802.15.4-2015 and Zigbee® specifications.
+
+The ARDUINO® Uno V3 connectivity support and the ST morpho headers allow the
+easy expansion of the functionality of the STM32 Nucleo open development
+platform with a wide choice of specialized shields.
+
+- Ultra-low-power wireless STM32WBA65RI microcontroller based on the Arm®
+  Cortex®‑M33 core, featuring 2 Mbyte of flash memory and 512 Kbytes of SRAM in
+  a VFQFPN68 package
+
+- MCU RF board (MB2130):
+
+  - 2.4 GHz RF transceiver supporting Bluetooth® specification v5.4
+  - Arm® Cortex® M33 CPU with TrustZone®, MPU, DSP, and FPU
+  - Integrated PCB antenna
+
+- Three user LEDs
+- Three user and one reset push-buttons
+
+- Board connectors:
+
+  - 2 USB Type-C
+  - ARDUINO® Uno V3 expansion connector
+  - ST morpho headers for full access to all STM32 I/Os
+
+- Flexible power-supply options: ST-LINK USB VBUS or external sources
+- On-board STLINK-V3MODS debugger/programmer with USB re-enumeration capability:
+  mass storage, Virtual COM port, and debug port
+
+Hardware
+********
+
+The STM32WBA65xx multiprotocol wireless and ultralow power devices embed a
+powerful and ultralow power radio compliant with the Bluetooth® SIG Low Energy
+specification 5.4. They contain a high-performance Arm Cortex-M33 32-bit RISC
+core. They operate at a frequency of up to 100 MHz.
+
+- Includes ST state-of-the-art patented technology
+
+- Ultra low power radio:
+
+  - 2.4 GHz radio
+  - RF transceiver supporting Bluetooth® Low Energy 5.4 specification
+    IEEE 802.15.4-2015 PHY and MAC, supporting Thread, Matter and Zigbee®
+  - Proprietary protocols
+  - RX sensitivity: -96 dBm (Bluetooth® Low Energy at 1 Mbps)
+    and -100 dBm (IEEE 802.15.4 at 250 kbps)
+  - Programmable output power, up to +10 dBm with 1 dB steps
+  - Support for external PA
+  - Integrated balun to reduce BOM
+  - Suitable for systems requiring compliance with radio frequency regulations
+    ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66
+
+- Ultra low power platform with FlexPowerControl:
+
+  - 1.71 to 3.6 V power supply
+  - - 40 °C to 85 °C temperature range
+  - Autonomous peripherals with DMA, functional down to Stop 1 mode
+  - TBD nA Standby mode (16 wake-up pins)
+  - TBD nA Standby mode with RTC
+  - TBD µA Standby mode with 64 KB SRAM
+  - TBD µA Stop 2 mode with 64 KB SRAM
+  - TBD µA/MHz Run mode at 3.3 V
+  - Radio: Rx TBD mA / Tx at 0 dBm TBD mA
+
+- Core: Arm® 32-bit Cortex®-M33 CPU with TrustZone®, MPU, DSP, and FPU
+- ART Accelerator™: 8-Kbyte instruction cache allowing 0-wait-state execution
+  from flash memory (frequency up to 100 MHz, 150 DMIPS)
+- Power management: embedded regulator LDO and SMPS step-down converter
+- Supporting switch on-the-fly and voltage scaling
+
+- Benchmarks:
+
+  - 1.5 DMIPS/MHz (Drystone 2.1)
+  - 410 CoreMark® (4.10 CoreMark/MHz)
+
+- Clock sources:
+
+  - 32 MHz crystal oscillator
+  - 32 kHz crystal oscillator (LSE)
+  - Internal low-power 32 kHz (±5%) RC
+  - Internal 16 MHz factory trimmed RC (±1%)
+  - PLL for system clock and ADC
+
+- Memories:
+
+  - 2 MB flash memory with ECC, including 256 Kbytes with 100 cycles
+  - 512 KB SRAM, including 64 KB with parity check
+  - 512-byte (32 rows) OTP
+
+- Rich analog peripherals (independent supply):
+
+  - 12-bit ADC 2.5 Msps with hardware oversampling
+
+- Communication peripherals:
+
+  - Four UARTs (ISO 7816, IrDA, modem)
+  - Three SPIs
+  - Four I2C Fm+ (1 Mbit/s), SMBus/PMBus®
+
+- System peripherals:
+
+  - Touch sensing controller, up to 24 sensors, supporting touch key, linear,
+     rotary touch sensors
+  - One 16-bit, advanced motor control timer
+  - Three 16-bit timers
+  - Two 32-bit timer
+  - Two low-power 16-bit timers (available in Stop mode)
+  - Two Systick timers
+  - RTC with hardware calendar and calibration
+  - Two watchdogs
+  - 8-channel DMA controller, functional in Stop mode
+
+- Security and cryptography:
+
+  - Arm® TrustZone® and securable I/Os, memories, and peripherals
+  - Flexible life cycle scheme with RDP and password protected debug
+  - Root of trust thanks to unique boot entry and secure hide protection area (HDP)
+  - SFI (secure firmware installation) thanks to embedded RSS (root secure services)
+  - Secure data storage with root hardware unique key (RHUK)
+  - Secure firmware upgrade support with TF-M
+  - Two AES co-processors, including one with DPA resistance
+  - Public key accelerator, DPA resistant
+  - HASH hardware accelerator
+  - True random number generator, NIST SP800-90B compliant
+  - 96-bit unique ID
+  - Active tampers
+  - CRC calculation unit
+
+- Up to 86 I/Os (most of them 5 V-tolerant) with interrupt capability
+
+- Development support:
+
+  - Serial wire debug (SWD), JTAG
+
+- ECOPACK2 compliant package
+
+More information about STM32WBA series can be found here:
+
+- `STM32WBA Series on www.st.com`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+Nucleo WBA65RI Board has 4 GPIO controllers. These controllers are responsible for pin muxing,
+input/output, pull-up, etc.
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+.. rst-class:: rst-columns
+
+- USART_1 TX/RX : PB12/PA8
+- I2C_1_SCL : PB2
+- I2C_1_SDA : PB1
+- USER_PB : PC13
+- LD1 : PD8
+- SPI_1_NSS : PA12 (arduino_spi)
+- SPI_1_SCK : PB4 (arduino_spi)
+- SPI_1_MISO : PB3 (arduino_spi)
+- SPI_1_MOSI : PA15 (arduino_spi)
+
+System Clock
+------------
+
+Nucleo WBA65RI System Clock could be driven by internal or external oscillator,
+as well as main PLL clock. By default System clock is driven by HSE+PLL clock at 100MHz.
+
+Serial Port
+-----------
+
+Nucleo WBA65RI board has 3 U(S)ARTs. The Zephyr console output is assigned to USART1.
+Default settings are 115200 8N1.
+
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Nucleo WBA65RI board includes an ST-LINK/V3 embedded debug tool interface.
+It could be used for flash and debug using either OpenOCD or STM32Cube ecosystem tools.
+
+Flashing
+========
+
+The board is configured to be flashed using west `STM32CubeProgrammer`_ runner,
+so its :ref:`installation <stm32cubeprog-flash-host-tools>` is required.
+
+Alternatively, openocd can also be used to flash the board using
+the ``--runner`` (or ``-r``) option:
+
+.. code-block:: console
+
+   $ west flash --runner openocd
+
+Flashing an application to Nucleo WBA65RI
+-----------------------------------------
+
+Here is an example for the :zephyr:code-sample:`blinky` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: nucleo_wba65ri
+   :goals: build flash
+
+You will see the LED blinking every second.
+
+Debugging
+=========
+
+Debugging using OpenOCD
+-----------------------
+
+You can debug an application in the usual way using OpenOCD. Here is an example for the
+:zephyr:code-sample:`blinky` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: nucleo_wba65ri
+   :maybe-skip-config:
+   :goals: debug
+
+.. _STM32WBA Series on www.st.com:
+   https://www.st.com/en/microcontrollers-microprocessors/stm32wba-series.html
+
+.. _STM32CubeProgrammer:
+   https://www.st.com/en/development-tools/stm32cubeprog.html
diff --git a/boards/st/nucleo_wba65ri/nucleo_wba65ri.dts b/boards/st/nucleo_wba65ri/nucleo_wba65ri.dts
new file mode 100644
index 00000000000..47ddf62fe03
--- /dev/null
+++ b/boards/st/nucleo_wba65ri/nucleo_wba65ri.dts
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c)  2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/wba/stm32wba65Xi.dtsi>
+#include <st/wba/stm32wba65rivx-pinctrl.dtsi>
+#include "arduino_r3_connector.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "STMicroelectronics STM32WBA65RI-NUCLEO board";
+	compatible = "st,stm32wba65ri-nucleo";
+
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	chosen {
+		zephyr,bt-c2h-uart = &usart1;
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		blue_led_1: led_0 {
+			gpios = <&gpiod 8 GPIO_ACTIVE_LOW>;
+			label = "User LD1";
+		};
+
+		green_led_2: led_1 {
+			gpios = <&gpioc 4 GPIO_ACTIVE_LOW>;
+			label = "User LD2";
+		};
+
+		red_led_3: led_2 {
+			gpios = <&gpiob 8 GPIO_ACTIVE_LOW>;
+			label = "User LD3";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		user_button_1: button_0 {
+			label = "User B1";
+			gpios = <&gpioc 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		user_button_2: button_1 {
+			label = "User B2";
+			gpios = <&gpioc 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+
+		user_button_3: button_2 {
+			label = "User B3";
+			gpios = <&gpiob 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_2>;
+		};
+	};
+
+	aliases {
+		led0 = &blue_led_1;
+		led1 = &green_led_2;
+		led2 = &red_led_3;
+		sw0 = &user_button_1;
+		sw1 = &user_button_2;
+		sw2 = &user_button_3;
+		mcuboot-led0 = &blue_led_1;
+		mcuboot-button0 = &user_button_1;
+	};
+};
+
+&clk_lse {
+	status = "okay";
+};
+
+&clk_hse {
+	hse-div2;
+	status = "okay";
+};
+
+&clk_hsi {
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&clk_hse>;
+	clock-frequency = <DT_FREQ_M(16)>;
+	ahb-prescaler = <1>;
+	ahb5-prescaler = <2>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <2>;
+	apb7-prescaler = <1>;
+};
+
+&iwdg {
+	status = "okay";
+};
+
+&rtc {
+	status = "okay";
+	clocks = <&rcc STM32_CLOCK(APB7, 21)>,
+			<&rcc STM32_SRC_LSE RTC_SEL(1)>;
+	prescaler = <32768>;
+};
+
+&usart1 {
+	clocks = <&rcc STM32_CLOCK(APB2, 14)>,
+		 <&rcc STM32_SRC_HSI16 USART1_SEL(2)>;
+	pinctrl-0 = <&usart1_tx_pb12 &usart1_rx_pa8>;
+	pinctrl-1 = <&analog_pb12 &analog_pa8>;
+	pinctrl-names = "default", "sleep";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&spi1 {
+	pinctrl-0 = <&spi1_nss_pa12 &spi1_sck_pb4
+		     &spi1_miso_pb3 &spi1_mosi_pa15>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_scl_pb2 &i2c1_sda_pb1>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&adc4 {
+	pinctrl-0 = <&adc4_in8_pa1>;
+	pinctrl-names = "default";
+	st,adc-clock-source = "ASYNC";
+	st,adc-prescaler = <4>;
+	status = "okay";
+};
+
+stm32_lp_tick_source: &lptim1 {
+	clocks = <&rcc STM32_CLOCK(APB7, 11)>,
+		 <&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
+	status = "okay";
+};
+
+&rng {
+	status = "okay";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		storage_partition: partition@1c0000 {
+			label = "storage";
+			reg = <0x001c0000 DT_SIZE_K(256)>;
+		};
+	};
+};
diff --git a/boards/st/nucleo_wba65ri/nucleo_wba65ri.yaml b/boards/st/nucleo_wba65ri/nucleo_wba65ri.yaml
new file mode 100644
index 00000000000..78617e1b262
--- /dev/null
+++ b/boards/st/nucleo_wba65ri/nucleo_wba65ri.yaml
@@ -0,0 +1,19 @@
+identifier: nucleo_wba65ri
+name: ST Nucleo WBA65RI
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - i2c
+  - spi
+  - adc
+  - rng
+  - arduino_gpio
+  - arduino_i2c
+  - arduino_spi
+ram: 512
+flash: 2048
+vendor: st
diff --git a/boards/st/nucleo_wba65ri/nucleo_wba65ri_defconfig b/boards/st/nucleo_wba65ri/nucleo_wba65ri_defconfig
new file mode 100644
index 00000000000..24ca108f245
--- /dev/null
+++ b/boards/st/nucleo_wba65ri/nucleo_wba65ri_defconfig
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2025 STMicroelectronics
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable clock
+CONFIG_CLOCK_CONTROL=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable the internal SMPS regulator
+CONFIG_POWER_SUPPLY_DIRECT_SMPS=y
diff --git a/boards/st/nucleo_wba65ri/support/openocd.cfg b/boards/st/nucleo_wba65ri/support/openocd.cfg
new file mode 100644
index 00000000000..0532f11f83a
--- /dev/null
+++ b/boards/st/nucleo_wba65ri/support/openocd.cfg
@@ -0,0 +1,26 @@
+# Note: Using OpenOCD using nucleo_wba65ri requires using openocd fork.
+# See board documentation for more information
+
+source [find interface/stlink-dap.cfg]
+
+set WORKAREASIZE 0x8000
+
+transport select "dapdirect_swd"
+
+# Enable debug when in low power modes
+set ENABLE_LOW_POWER 1
+
+# Stop Watchdog counters when halt
+set STOP_WATCHDOG 1
+
+# STlink Debug clock frequency
+set CLOCK_FREQ 8000
+
+# Reset configuration
+# use hardware reset, connect under reset
+# connect_assert_srst needed if low power mode application running (WFI...)
+reset_config srst_only srst_nogate
+
+source [find target/stm32wbax.cfg]
+
+gdb_memory_map disable
diff --git a/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst b/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst
index 72f7147c5b6..56a2fbb8de1 100644
--- a/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst
+++ b/boards/st/nucleo_wl55jc/doc/nucleo_wl55jc.rst
@@ -33,8 +33,6 @@ power consumption, and features.
   mass storage, Virtual COM port, and debug port
 - Comprehensive free software libraries and examples available with the
   STM32CubeWL MCU Package
-- Support of a wide choice of Integrated Development Environments (IDEs)
-  including IAR Embedded Workbench®, MDK-ARM, and STM32CubeIDE
 - Suitable for rapid prototyping of end nodes based on LoRaWAN, Sigfox, wM-Bus,
   and many other proprietary protocols
 - Fully open hardware platform
@@ -164,53 +162,7 @@ More information about STM32WL55JC can be found here:
 Supported Features
 ==================
 
-The Zephyr nucleo_wl55jc board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| AES       | on-chip    | crypto                              |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock_control             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| MPU       | on-chip    | arch/arm                            |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | arch/arm                            |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| RADIO     | on-chip    | LoRa                                |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | DAC Controller                      |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in:
-
-- :zephyr_file:`boards/st/nucleo_wl55jc/nucleo_wl55jc_defconfig`
-- :zephyr_file:`boards/st/nucleo_wl55jc/nucleo_wl55jc.dts`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -251,6 +203,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Nucleo WL55JC board includes an STLINK-V3 embedded debug tool interface.
 
 Applications for the ``nucleo_wl55jc`` board configuration can be built the
diff --git a/boards/st/nucleo_wl55jc/nucleo_wl55jc.yaml b/boards/st/nucleo_wl55jc/nucleo_wl55jc.yaml
index 4eb53ef3324..a0ab9a6f621 100644
--- a/boards/st/nucleo_wl55jc/nucleo_wl55jc.yaml
+++ b/boards/st/nucleo_wl55jc/nucleo_wl55jc.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 256
 supported:
diff --git a/boards/st/sensortile_box/doc/index.rst b/boards/st/sensortile_box/doc/index.rst
index 861b2e559b9..da3931ed8b2 100644
--- a/boards/st/sensortile_box/doc/index.rst
+++ b/boards/st/sensortile_box/doc/index.rst
@@ -70,6 +70,8 @@ on a smartphone/PC to implement applications such as:
 - Compass and inclinometer
 - Sensor data logger
 
+.. zephyr:board-supported-hw::
+
 Connections and IOs
 ===================
 
@@ -121,6 +123,8 @@ functions.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 There are 2 main entry points for flashing STM32FL4Rx SoCs, one using the ROM
 bootloader, and another by using the SWD debug port (which requires additional
 hardware) on FTSH107 connector.
diff --git a/boards/st/sensortile_box/sensortile_box.dts b/boards/st/sensortile_box/sensortile_box.dts
index 9e7acee2e5a..84fee2824b4 100644
--- a/boards/st/sensortile_box/sensortile_box.dts
+++ b/boards/st/sensortile_box/sensortile_box.dts
@@ -72,7 +72,7 @@
 	div-m = <4>;
 	mul-n = <40>;
 	div-p = <7>;
-	div-q = <2>;
+	div-q = <4>;
 	div-r = <2>;
 	clocks = <&clk_hse>;
 	status = "okay";
@@ -244,3 +244,10 @@ zephyr_udc0: &usbotg_fs {
 		};
 	};
 };
+
+&rng {
+	/* Change clock source to avoid using MSI */
+	clocks = <&rcc STM32_CLOCK(AHB2, 18U)>,
+		 <&rcc STM32_SRC_PLL_Q CLK48_SEL(2)>;
+	status = "okay";
+};
diff --git a/boards/st/sensortile_box/sensortile_box.yaml b/boards/st/sensortile_box/sensortile_box.yaml
index aaa655bf84c..47c80ae069c 100644
--- a/boards/st/sensortile_box/sensortile_box.yaml
+++ b/boards/st/sensortile_box/sensortile_box.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - pwm
   - spi
diff --git a/boards/st/sensortile_box_pro/doc/index.rst b/boards/st/sensortile_box_pro/doc/index.rst
index 528e6762a87..63d84cfe7e1 100644
--- a/boards/st/sensortile_box_pro/doc/index.rst
+++ b/boards/st/sensortile_box_pro/doc/index.rst
@@ -31,6 +31,8 @@ on a smartphone/PC to implement applications such as:
 (see `Motion and environmental sensors`_ section for the complete lists of available
 sensors on board)
 
+.. zephyr:board-supported-hw::
+
 Hardware
 ********
 
@@ -247,6 +249,8 @@ Console default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 There are two alternative methods of flashing ST Sensortile.box Pro board:
 
 1. Using DFU software tools
diff --git a/boards/st/sensortile_box_pro/sensortile_box_pro.yaml b/boards/st/sensortile_box_pro/sensortile_box_pro.yaml
index 14624c77f7d..2151012aa8c 100644
--- a/boards/st/sensortile_box_pro/sensortile_box_pro.yaml
+++ b/boards/st/sensortile_box_pro/sensortile_box_pro.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - pwm
   - spi
diff --git a/boards/st/st25dv_mb1283_disco/doc/index.rst b/boards/st/st25dv_mb1283_disco/doc/index.rst
index b1fe8fa35da..1c629ef0318 100644
--- a/boards/st/st25dv_mb1283_disco/doc/index.rst
+++ b/boards/st/st25dv_mb1283_disco/doc/index.rst
@@ -66,6 +66,11 @@ Default Zephyr Peripheral Mapping
 - GPIO : PE15/PE7 (Available on external ST25DV connector J6)
 - GPIO : PE14 (Available on J5 connector)
 
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
 Serial Port
 ===========
 
@@ -76,6 +81,8 @@ Default communication settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``st25dv_mb1283_disco`` board configuration can be built and
 flashed in the usual way (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco.yaml b/boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco.yaml
index b4dcf17f828..899824a3a10 100644
--- a/boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco.yaml
+++ b/boards/st/st25dv_mb1283_disco/st25dv_mb1283_disco.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 192
 flash: 1024
 supported:
diff --git a/boards/st/steval_fcu001v1/doc/index.rst b/boards/st/steval_fcu001v1/doc/index.rst
index aea2ce5ac79..81e31a53ab9 100644
--- a/boards/st/steval_fcu001v1/doc/index.rst
+++ b/boards/st/steval_fcu001v1/doc/index.rst
@@ -39,28 +39,7 @@ can be found in these documents:
 Supported Features
 ==================
 
-The Zephyr steval_fcu001v1 board configuration supports the following hardware features:
-
-+-----------+------------+------------------------------------+
-| Interface | Controller | Driver/Component                   |
-+===========+============+====================================+
-| NVIC      | on-chip    | nested vector interrupt controller |
-+-----------+------------+------------------------------------+
-| UART      | on-chip    | serial port-polling;               |
-|           |            | serial port-interrupt              |
-+-----------+------------+------------------------------------+
-| PINMUX    | on-chip    | pinmux                             |
-+-----------+------------+------------------------------------+
-| GPIO      | on-chip    | gpio                               |
-+-----------+------------+------------------------------------+
-| PWM       | on-chip    | pwm                                |
-+-----------+------------+------------------------------------+
-| I2C       | on-chip    | i2c                                |
-+-----------+------------+------------------------------------+
-
-
-The default configuration can be found in
-:zephyr_file:`boards/st/steval_fcu001v1/steval_fcu001v1_defconfig`
+.. zephyr:board-supported-hw::
 
 Default Zephyr Peripheral Mapping:
 ----------------------------------
@@ -95,6 +74,8 @@ The steval_fcu001v1 board has one I2C. The default I2C mapping for Zephyr is:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``steval_fcu001v1`` board configuration can be built and
 flashed in the usual way (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/st/steval_fcu001v1/steval_fcu001v1.yaml b/boards/st/steval_fcu001v1/steval_fcu001v1.yaml
index 64ac751a2fc..3c90be5ed18 100644
--- a/boards/st/steval_fcu001v1/steval_fcu001v1.yaml
+++ b/boards/st/steval_fcu001v1/steval_fcu001v1.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - pwm
diff --git a/boards/st/steval_stwinbx1/doc/index.rst b/boards/st/steval_stwinbx1/doc/index.rst
index 8ef4c10dcca..1622f07b3af 100644
--- a/boards/st/steval_stwinbx1/doc/index.rst
+++ b/boards/st/steval_stwinbx1/doc/index.rst
@@ -31,6 +31,8 @@ NFC or USB protocols to a host application running on a smartphone/PC to impleme
 (see `Sensing`_ section for the complete lists of available
 sensors on board)
 
+.. zephyr:board-supported-hw::
+
 Hardware
 ********
 
@@ -254,7 +256,9 @@ There are two possible options for Zephyr console output:
 Console default settings are 115200 8N1.
 
 Programming and Debugging
--------------------------
+*************************
+
+.. zephyr:board-supported-runners::
 
 There are two alternative methods of flashing ST Sensortile.box Pro board:
 
@@ -295,7 +299,7 @@ It is recommended to use the latest version of `STM32CubeProgrammer`_
 
 
 Flash an Application to STEVAL-STWINBX1
-------------------------------------------
+---------------------------------------
 
 There are two ways to enter DFU mode:
 
diff --git a/boards/st/stm3210c_eval/doc/index.rst b/boards/st/stm3210c_eval/doc/index.rst
index 43a5bdd4b68..61e8fd3a20b 100644
--- a/boards/st/stm3210c_eval/doc/index.rst
+++ b/boards/st/stm3210c_eval/doc/index.rst
@@ -50,31 +50,7 @@ More information about STM32F107VCT can be found here:
 Supported Features
 ==================
 
-The Zephyr stm3210c_eval board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm3210c_eval/stm3210c_eval_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -100,6 +76,8 @@ Default Zephyr Peripheral Mapping:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/st/stm3210c_eval/stm3210c_eval.yaml b/boards/st/stm3210c_eval/stm3210c_eval.yaml
index ae64ea9fe47..05f966831ca 100644
--- a/boards/st/stm3210c_eval/stm3210c_eval.yaml
+++ b/boards/st/stm3210c_eval/stm3210c_eval.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 256
 supported:
diff --git a/boards/st/stm32373c_eval/doc/index.rst b/boards/st/stm32373c_eval/doc/index.rst
index 10f722c650d..28758854910 100644
--- a/boards/st/stm32373c_eval/doc/index.rst
+++ b/boards/st/stm32373c_eval/doc/index.rst
@@ -54,31 +54,7 @@ More information about STM32F373VCT6 can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32373c_eval board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm32373c_eval/stm32373c_eval_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -104,6 +80,8 @@ Default Zephyr Peripheral Mapping:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``stm32373c_eval`` board configuration can be built and
 flashed in the usual way (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/st/stm32373c_eval/stm32373c_eval.yaml b/boards/st/stm32373c_eval/stm32373c_eval.yaml
index 6d06bffe951..f2b59ecd750 100644
--- a/boards/st/stm32373c_eval/stm32373c_eval.yaml
+++ b/boards/st/stm32373c_eval/stm32373c_eval.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
 supported:
   - watchdog
diff --git a/boards/st/stm32c0116_dk/doc/index.rst b/boards/st/stm32c0116_dk/doc/index.rst
index b955518a776..d5b771c699a 100644
--- a/boards/st/stm32c0116_dk/doc/index.rst
+++ b/boards/st/stm32c0116_dk/doc/index.rst
@@ -39,43 +39,7 @@ More information about STM32C011F6 can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32c0116_dk board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| IWDG      | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| WWDG      | on-chip    | window watchdog                     |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | Direct Memory Access                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm32c0116_dk/stm32c0116_dk_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -99,6 +63,8 @@ The STM32C0116 Discovery board is configured as follows:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32C0116-DK Discovery kit includes an ST-LINK/V2 embedded debug tool interface.
 
 Applications for the ``stm32c0116_dk`` board configuration can be built and
diff --git a/boards/st/stm32f072_eval/doc/index.rst b/boards/st/stm32f072_eval/doc/index.rst
index 43c1eb1e0be..19cf2e4e8f6 100644
--- a/boards/st/stm32f072_eval/doc/index.rst
+++ b/boards/st/stm32f072_eval/doc/index.rst
@@ -68,32 +68,7 @@ More information about STM32F072VB can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32f072_eval board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr porting.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm32f072_eval/stm32f072_eval_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -134,6 +109,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32F072-EVAL Discovery kit includes an ST-LINK/V2 embedded debug tool interface.
 
 Applications for the ``stm32f072_eval`` board configuration can be built and
diff --git a/boards/st/stm32f072_eval/stm32f072_eval.yaml b/boards/st/stm32f072_eval/stm32f072_eval.yaml
index b6655a01722..72b089f67cb 100644
--- a/boards/st/stm32f072_eval/stm32f072_eval.yaml
+++ b/boards/st/stm32f072_eval/stm32f072_eval.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 16
 flash: 128
 supported:
diff --git a/boards/st/stm32f072b_disco/doc/index.rst b/boards/st/stm32f072b_disco/doc/index.rst
index 9790d3f4d0e..3794fc098fa 100644
--- a/boards/st/stm32f072b_disco/doc/index.rst
+++ b/boards/st/stm32f072b_disco/doc/index.rst
@@ -60,40 +60,10 @@ More information about STM32F072RB can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32f072b_disco board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c controller                      |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | SPI controller                      |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | CAN controller                      |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 .. note:: CAN feature requires CAN transceiver, such as `SK Pang CAN breakout board`_.
 
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm32f072b_disco/stm32f072b_disco_defconfig`
-
-
 Pin Mapping
 ===========
 
@@ -137,6 +107,8 @@ is assigned to UART 1. Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32F072B-DISCO board includes an ST-LINK/V2 embedded debug tool interface.
 
 Applications for the ``stm32f072b_disco`` board configuration can be built and
diff --git a/boards/st/stm32f072b_disco/stm32f072b_disco.yaml b/boards/st/stm32f072b_disco/stm32f072b_disco.yaml
index 186d733ca7d..2824e497ae7 100644
--- a/boards/st/stm32f072b_disco/stm32f072b_disco.yaml
+++ b/boards/st/stm32f072b_disco/stm32f072b_disco.yaml
@@ -7,7 +7,6 @@ flash: 128
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/st/stm32f0_disco/doc/index.rst b/boards/st/stm32f0_disco/doc/index.rst
index dccce953fac..afe2789eaf7 100644
--- a/boards/st/stm32f0_disco/doc/index.rst
+++ b/boards/st/stm32f0_disco/doc/index.rst
@@ -40,31 +40,7 @@ More information about STM32F051R8 can be found in the `STM32F0x8 reference manu
 Supported Features
 ==================
 
-The Zephyr stm32f0_disco board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm32f0_disco/stm32f0_disco_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -87,6 +63,8 @@ For more details please refer to `STM32F0DISCOVERY board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32F0DISCOVERY board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``stm32f0_disco`` board configuration can be built and
diff --git a/boards/st/stm32f0_disco/stm32f0_disco.yaml b/boards/st/stm32f0_disco/stm32f0_disco.yaml
index 53954e2a4ed..0f351814295 100644
--- a/boards/st/stm32f0_disco/stm32f0_disco.yaml
+++ b/boards/st/stm32f0_disco/stm32f0_disco.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 8
 supported:
   - watchdog
diff --git a/boards/st/stm32f3_disco/doc/index.rst b/boards/st/stm32f3_disco/doc/index.rst
index 107f3a60964..c73c6768499 100644
--- a/boards/st/stm32f3_disco/doc/index.rst
+++ b/boards/st/stm32f3_disco/doc/index.rst
@@ -67,49 +67,7 @@ More information about STM32F303VC can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32f3_disco board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | CAN                                 |
-+-----------+------------+-------------------------------------+
-| IWDG      | on-chip    | Independent WatchDoG                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | dac                                 |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | Direct Memory Access                |
-+-----------+------------+-------------------------------------+
-| die-temp  | on-chip    | die temperature sensor              |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm32f3_disco/stm32f3_disco_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -194,6 +152,8 @@ transceiver must be connected to ``PD0`` (``CAN1_RX``) and ``PD1``
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32F3DISCOVERY Discovery kit includes a ST-LINK/V2 or ST-LINK/V2-B embedded
 debug tool interface.
 
diff --git a/boards/st/stm32f3_disco/stm32f3_disco.dts b/boards/st/stm32f3_disco/stm32f3_disco.dts
index 01fbad2721f..b47e139c4b8 100644
--- a/boards/st/stm32f3_disco/stm32f3_disco.dts
+++ b/boards/st/stm32f3_disco/stm32f3_disco.dts
@@ -61,7 +61,7 @@
 		compatible = "gpio-keys";
 		user_button: button {
 			label = "User";
-			gpios = <&gpioa 0 GPIO_ACTIVE_LOW>;
+			gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
 			zephyr,code = <INPUT_KEY_0>;
 		};
 	};
diff --git a/boards/st/stm32f3_disco/stm32f3_disco_B.yaml b/boards/st/stm32f3_disco/stm32f3_disco_B.yaml
index ebdbe230d20..b92695027c2 100644
--- a/boards/st/stm32f3_disco/stm32f3_disco_B.yaml
+++ b/boards/st/stm32f3_disco/stm32f3_disco_B.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 40
 supported:
   - gpio
diff --git a/boards/st/stm32f3_disco/stm32f3_disco_stm32f303xc_E.yaml b/boards/st/stm32f3_disco/stm32f3_disco_stm32f303xc_E.yaml
index 9a58627880c..dfb2f094e28 100644
--- a/boards/st/stm32f3_disco/stm32f3_disco_stm32f303xc_E.yaml
+++ b/boards/st/stm32f3_disco/stm32f3_disco_stm32f303xc_E.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 40
 supported:
   - gpio
diff --git a/boards/st/stm32f411e_disco/doc/index.rst b/boards/st/stm32f411e_disco/doc/index.rst
index 3b97cf29012..9c7f25ec56a 100644
--- a/boards/st/stm32f411e_disco/doc/index.rst
+++ b/boards/st/stm32f411e_disco/doc/index.rst
@@ -59,29 +59,7 @@ More information about STM32F411VE can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32f411e_disco board configuration supports the following
-hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm32f411e_disco/stm32f411e_disco_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -117,6 +95,8 @@ assigned to UART2. Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32F411E-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool interface.
 
 Applications for the ``stm32f411e_disco`` board configuration can be built and
diff --git a/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.yaml b/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.yaml
index 480b81537b6..61c203105e9 100644
--- a/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.yaml
+++ b/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_B.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
 vendor: st
diff --git a/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_D.yaml b/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_D.yaml
index 725a9fd46bd..5591f060a93 100644
--- a/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_D.yaml
+++ b/boards/st/stm32f411e_disco/stm32f411e_disco_stm32f411xe_D.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
 vendor: st
diff --git a/boards/st/stm32f412g_disco/doc/index.rst b/boards/st/stm32f412g_disco/doc/index.rst
index db8674826c2..fb7fa80482c 100644
--- a/boards/st/stm32f412g_disco/doc/index.rst
+++ b/boards/st/stm32f412g_disco/doc/index.rst
@@ -72,32 +72,7 @@ More information about STM32F412ZG can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32f412g_disco board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| QSPI NOR  | on-chip    | off-chip flash                      |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm32f412g_disco/stm32f412g_disco_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -133,6 +108,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32F412G-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool interface.
 
 Applications for the ``stm32f412g_disco`` board configuration can be built and
diff --git a/boards/st/stm32f412g_disco/stm32f412g_disco.yaml b/boards/st/stm32f412g_disco/stm32f412g_disco.yaml
index 5bf836929ba..41b728a9526 100644
--- a/boards/st/stm32f412g_disco/stm32f412g_disco.yaml
+++ b/boards/st/stm32f412g_disco/stm32f412g_disco.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_gpio
   - arduino_serial
diff --git a/boards/st/stm32f413h_disco/doc/index.rst b/boards/st/stm32f413h_disco/doc/index.rst
index 49ce176da65..be2433a18c5 100644
--- a/boards/st/stm32f413h_disco/doc/index.rst
+++ b/boards/st/stm32f413h_disco/doc/index.rst
@@ -75,30 +75,7 @@ More information about STM32F413ZH can be found here:
 Supported Features
 ==================
 
-The Zephyr STM32F413H-DISCO board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported by Zephyr.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm32f413h_disco/stm32f413h_disco_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -132,6 +109,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32F413H-DISCO Discovery kit includes an ST-LINK/V2 embedded debug tool interface.
 
 Applications for the STM32F413H-DISCO board configuration can be built and
diff --git a/boards/st/stm32f413h_disco/stm32f413h_disco.yaml b/boards/st/stm32f413h_disco/stm32f413h_disco.yaml
index 27f178934f8..6fd4f5eb331 100644
--- a/boards/st/stm32f413h_disco/stm32f413h_disco.yaml
+++ b/boards/st/stm32f413h_disco/stm32f413h_disco.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_gpio
   - arduino_serial
diff --git a/boards/st/stm32f429i_disc1/doc/index.rst b/boards/st/stm32f429i_disc1/doc/index.rst
index 24780fb6cc0..6bac481d9b2 100644
--- a/boards/st/stm32f429i_disc1/doc/index.rst
+++ b/boards/st/stm32f429i_disc1/doc/index.rst
@@ -68,38 +68,7 @@ More information about STM32F429ZI can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32f429i_disc1 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| FMC       | on-chip    | memc (SDRAM)                        |
-+-----------+------------+-------------------------------------+
-| OTG_HS    | on-chip    | usbotg_hs                           |
-+-----------+------------+-------------------------------------+
-| LTDC      | on-chip    | display                             |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm32f429i_disc1/stm32f429i_disc1_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -153,6 +122,8 @@ and host OTG operation, but only device mode has been tested with Zephyr at this
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The STM32F429I-DISC1 Discovery kit includes a ST-LINK/V2-B embedded debug tool interface.
 Applications for the ``stm32f429i_disc1`` board configuration can be built
 and flashed in the usual way (see :ref:`build_an_application` and
diff --git a/boards/st/stm32f429i_disc1/stm32f429i_disc1.yaml b/boards/st/stm32f429i_disc1/stm32f429i_disc1.yaml
index 5d4b25c8312..10fbd8485d4 100644
--- a/boards/st/stm32f429i_disc1/stm32f429i_disc1.yaml
+++ b/boards/st/stm32f429i_disc1/stm32f429i_disc1.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 192
 flash: 2048
 supported:
diff --git a/boards/st/stm32f469i_disco/doc/index.rst b/boards/st/stm32f469i_disco/doc/index.rst
index 7570831c568..e6830efb2be 100644
--- a/boards/st/stm32f469i_disco/doc/index.rst
+++ b/boards/st/stm32f469i_disco/doc/index.rst
@@ -72,32 +72,7 @@ More information about STM32F469NI can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32f469i_disco board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| SDIO      | on-chip    | SD-card controller                  |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm32f469i_disco/stm32f469i_disco_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -139,6 +114,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``stm32f469i_disco`` board configuration can be built and
 flashed in the usual way (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/st/stm32f469i_disco/stm32f469i_disco.yaml b/boards/st/stm32f469i_disco/stm32f469i_disco.yaml
index fef17c354b8..32f51672d46 100644
--- a/boards/st/stm32f469i_disco/stm32f469i_disco.yaml
+++ b/boards/st/stm32f469i_disco/stm32f469i_disco.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 320
 flash: 2048
 supported:
diff --git a/boards/st/stm32f4_disco/doc/index.rst b/boards/st/stm32f4_disco/doc/index.rst
index f21b1cdc014..18e8ac7e2be 100644
--- a/boards/st/stm32f4_disco/doc/index.rst
+++ b/boards/st/stm32f4_disco/doc/index.rst
@@ -69,37 +69,12 @@ More information about STM32F407VG can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32f4_disco board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb                                 |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | CAN controller                      |
-+-----------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 .. note:: CAN feature requires CAN transceiver, such as `SK Pang CAN breakout board`_.
           Zephyr default configuration uses CAN_2 exclusively, as simultaneous use
           of CAN_1 and CAN_2 is not yet supported.
 
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm32f4_disco/stm32f4_disco_defconfig`
-
-
 Pin Mapping
 ===========
 
@@ -113,8 +88,6 @@ Default Zephyr Peripheral Mapping:
 
 .. rst-class:: rst-columns
 
-- UART_1_TX : PB6
-- UART_1_RX : PB7
 - UART_2_TX : PA2
 - UART_2_RX : PA3
 - USER_PB : PA0
@@ -124,10 +97,14 @@ Default Zephyr Peripheral Mapping:
 - LD6 : PD15
 - USB DM : PA11
 - USB DP : PA12
-- CAN1_RX : PB8
-- CAN1_TX : PB9
 - CAN2_RX : PB5
 - CAN2_TX : PB13
+- I2C1_SDA : PB9
+- I2C1_SCL : PB6
+- I2S3_MCK : PC7
+- I2S3_CK : PC10
+- I2S3_SD : PC12
+- I2S3_WS : PA4
 
 System Clock
 ============
@@ -148,6 +125,8 @@ enable console output you should use a serial cable and connect it to UART2 pins
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32F4DISCOVERY Discovery kit includes an ST-LINK/V2 embedded debug tool interface.
 
 Applications for the ``stm32f4_disco`` board configuration can be built and
diff --git a/boards/st/stm32f4_disco/stm32f4_disco.dts b/boards/st/stm32f4_disco/stm32f4_disco.dts
index 4e5d9ff87f8..10404e49103 100644
--- a/boards/st/stm32f4_disco/stm32f4_disco.dts
+++ b/boards/st/stm32f4_disco/stm32f4_disco.dts
@@ -83,13 +83,6 @@
 	};
 };
 
-&usart1 {
-	pinctrl-0 = <&usart1_tx_pb6 &usart1_rx_pb7>;
-	pinctrl-names = "default";
-	current-speed = <115200>;
-	status = "okay";
-};
-
 &clk_lsi {
 	status = "okay";
 };
@@ -159,12 +152,6 @@ zephyr_udc0: &usbotg_fs {
 	status = "okay";
 };
 
-&can1 {
-	pinctrl-0 = <&can1_rx_pb8 &can1_tx_pb9>;
-	pinctrl-names = "default";
-	status = "disabled";
-};
-
 &can2 {
 	pinctrl-0 = <&can2_rx_pb5 &can2_tx_pb13>;
 	pinctrl-names = "default";
@@ -187,3 +174,42 @@ zephyr_udc0: &usbotg_fs {
 &vbat {
 	status = "okay";
 };
+
+&dma1 {
+	status = "okay";
+};
+
+&plli2s {
+	/* Minimize audio clock error (with i2s mck-enabled) for all of:
+	 * - 22.05kHz / 16b, 24b or 32b
+	 * - 44.1kHz  / 16b, 24b or 32b
+	 * - 88.2kHz  / 16b or 24b
+	 * Note: because the PLLI2S is dependent on the main PLL, the latter
+	 *       should not be changed without checking impact on PLLI2S
+	 */
+	mul-n = <271>;
+	div-r = <2>;
+	status = "okay";
+};
+
+&i2s3 {
+	mck-enabled;
+	pinctrl-0 = <&i2s3_ws_pa4 &i2s3_ck_pc10 &i2s3_sd_pc12 &i2s3_mck_pc7>;
+	pinctrl-names = "default";
+	clocks = <&rcc STM32_CLOCK(APB1, 15U)>,
+		 <&rcc STM32_SRC_PLLI2S_R I2S_SEL(0)>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <I2C_BITRATE_FAST>;
+	pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pb9>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	audio_codec: cs43l22@4a {
+		compatible = "cirrus,cs43l22";
+		reg = <0x4a>;
+		reset-gpios = <&gpiod 4 0>;
+	};
+};
diff --git a/boards/st/stm32f4_disco/stm32f4_disco.yaml b/boards/st/stm32f4_disco/stm32f4_disco.yaml
index b3cca00ab7b..89bc8004804 100644
--- a/boards/st/stm32f4_disco/stm32f4_disco.yaml
+++ b/boards/st/stm32f4_disco/stm32f4_disco.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 1024
 supported:
diff --git a/boards/st/stm32f723e_disco/doc/index.rst b/boards/st/stm32f723e_disco/doc/index.rst
index 412e5998dd0..5ec869f27d7 100644
--- a/boards/st/stm32f723e_disco/doc/index.rst
+++ b/boards/st/stm32f723e_disco/doc/index.rst
@@ -60,31 +60,7 @@ More information about STM32F723IEK6 can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32f723e_disco board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB device                          |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm32f723e_disco/stm32f723e_disco_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -125,6 +101,8 @@ settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32F723E Discovery kit includes an ST-LINK/V2 embedded debug tool interface.
 
 Applications for the ``stm32f723e_disco`` board configuration can be built and
diff --git a/boards/st/stm32f723e_disco/stm32f723e_disco.yaml b/boards/st/stm32f723e_disco/stm32f723e_disco.yaml
index 1908ae26279..61334096389 100644
--- a/boards/st/stm32f723e_disco/stm32f723e_disco.yaml
+++ b/boards/st/stm32f723e_disco/stm32f723e_disco.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 192
 flash: 512
 supported:
diff --git a/boards/st/stm32f746g_disco/Kconfig.defconfig b/boards/st/stm32f746g_disco/Kconfig.defconfig
index e617f92308b..a3b98a61c92 100644
--- a/boards/st/stm32f746g_disco/Kconfig.defconfig
+++ b/boards/st/stm32f746g_disco/Kconfig.defconfig
@@ -24,13 +24,6 @@ config MEMC
 
 endif # DISPLAY
 
-if INPUT
-
-config INPUT_FT5336_INTERRUPT
-	default y
-
-endif # INPUT
-
 config DISK_DRIVER_SDMMC
 	default y if DISK_DRIVERS
 
diff --git a/boards/st/stm32f746g_disco/board.cmake b/boards/st/stm32f746g_disco/board.cmake
index 038a5d7e806..968e8cfa890 100644
--- a/boards/st/stm32f746g_disco/board.cmake
+++ b/boards/st/stm32f746g_disco/board.cmake
@@ -2,6 +2,8 @@
 
 # keep first
 board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
+board_runner_args(stm32cubeprogrammer "--extload=N25Q128A_STM32F746G-DISCO.stldr")
+
 board_runner_args(jlink "--device=STM32F746NG" "--speed=4000")
 
 # keep first
diff --git a/boards/st/stm32f746g_disco/doc/index.rst b/boards/st/stm32f746g_disco/doc/index.rst
index bdd9ee665b6..35d515c4b42 100644
--- a/boards/st/stm32f746g_disco/doc/index.rst
+++ b/boards/st/stm32f746g_disco/doc/index.rst
@@ -77,45 +77,7 @@ More information about STM32F746NGH6 can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32f746g_disco board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | Ethernet                            |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb                                 |
-+-----------+------------+-------------------------------------+
-| SDMMC     | on-chip    | disk access                         |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| QSPI NOR  | on-chip    | off-chip flash                      |
-+-----------+------------+-------------------------------------+
-| FMC       | on-chip    | memc (SDRAM)                        |
-+-----------+------------+-------------------------------------+
-| LTDC      | on-chip    | display                             |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm32f746g_disco/stm32f746g_disco_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -176,6 +138,8 @@ settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32F746G Discovery kit includes an ST-LINK/V2 embedded debug tool interface.
 
 Applications for the ``stm32f746g_disco`` board configuration can be built and
diff --git a/boards/st/stm32f746g_disco/stm32f746g_disco.dts b/boards/st/stm32f746g_disco/stm32f746g_disco.dts
index e224d24beaa..eafd8bd6be2 100644
--- a/boards/st/stm32f746g_disco/stm32f746g_disco.dts
+++ b/boards/st/stm32f746g_disco/stm32f746g_disco.dts
@@ -57,6 +57,15 @@
 		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
 	};
 
+	/* Declare attributes for the External flash Mem to allow code execution there */
+	ext_memory: memory@90000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x90000000 DT_SIZE_M(16)>; /* max addressable area */
+		zephyr,memory-region = "EXTMEM";
+		/* Override ATTR_MPU_EXTMEM with ATTR_MPU_IO to allow access */
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
+	};
+
 	aliases {
 		led0 = &green_led_1;
 		sw0 = &user_button;
@@ -105,7 +114,7 @@
 	ft5336: ft5336@38 {
 		compatible = "focaltech,ft5336";
 		reg = <0x38>;
-		int-gpios = <&gpioi 13 0>;
+		int-gpios = <&gpioi 13 GPIO_ACTIVE_LOW>;
 	};
 };
 
@@ -168,16 +177,27 @@ zephyr_udc0: &usbotg_fs {
 
 &mac {
 	status = "okay";
-	pinctrl-0 = <&eth_mdc_pc1
-		     &eth_rxd0_pc4
+	pinctrl-0 = <&eth_rxd0_pc4
 		     &eth_rxd1_pc5
 		     &eth_ref_clk_pa1
-		     &eth_mdio_pa2
 		     &eth_crs_dv_pa7
 		     &eth_tx_en_pg11
 		     &eth_txd0_pg13
 		     &eth_txd1_pg14>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
+	pinctrl-names = "default";
+
+	eth_phy: ethernet-phy@0 {
+		compatible = "ethernet-phy";
+		reg = <0x00>;
+	};
 };
 
 &quadspi {
diff --git a/boards/st/stm32f746g_disco/stm32f746g_disco.yaml b/boards/st/stm32f746g_disco/stm32f746g_disco.yaml
index 7d58f2b1f2b..adab2d743f0 100644
--- a/boards/st/stm32f746g_disco/stm32f746g_disco.yaml
+++ b/boards/st/stm32f746g_disco/stm32f746g_disco.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 256
 flash: 1024
 supported:
diff --git a/boards/st/stm32f7508_dk/Kconfig.defconfig b/boards/st/stm32f7508_dk/Kconfig.defconfig
index c43b749d79b..1123e294777 100644
--- a/boards/st/stm32f7508_dk/Kconfig.defconfig
+++ b/boards/st/stm32f7508_dk/Kconfig.defconfig
@@ -24,13 +24,6 @@ endif # DISPLAY
 config INPUT
 	default y if LVGL
 
-if INPUT
-
-config INPUT_FT5336_INTERRUPT
-	default y
-
-endif # INPUT
-
 config DISK_DRIVER_SDMMC
 	default y if DISK_DRIVERS
 
diff --git a/boards/st/stm32f7508_dk/doc/index.rst b/boards/st/stm32f7508_dk/doc/index.rst
index fae2512a2f0..11e899d1bcb 100644
--- a/boards/st/stm32f7508_dk/doc/index.rst
+++ b/boards/st/stm32f7508_dk/doc/index.rst
@@ -72,45 +72,7 @@ More information about STM32F750x8 can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32f7508_dk board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | Ethernet                            |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb                                 |
-+-----------+------------+-------------------------------------+
-| SDMMC     | on-chip    | disk access                         |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| QSPI NOR  | on-chip    | off-chip flash                      |
-+-----------+------------+-------------------------------------+
-| FMC       | on-chip    | memc (SDRAM)                        |
-+-----------+------------+-------------------------------------+
-| LTDC      | on-chip    | display                             |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm32f7508_dk/stm32f7508_dk_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -171,6 +133,8 @@ settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32F7508-DK Discovery kit includes an ST-LINK/V2 embedded debug tool interface.
 
 Applications for the ``stm32f7508_dk`` board configuration can be built and
diff --git a/boards/st/stm32f7508_dk/stm32f7508_dk.dts b/boards/st/stm32f7508_dk/stm32f7508_dk.dts
index cf05ebfd479..2add12eb8ec 100644
--- a/boards/st/stm32f7508_dk/stm32f7508_dk.dts
+++ b/boards/st/stm32f7508_dk/stm32f7508_dk.dts
@@ -105,7 +105,7 @@
 	ft5336: ft5336@38 {
 		compatible = "focaltech,ft5336";
 		reg = <0x38>;
-		int-gpios = <&gpioi 13 0>;
+		int-gpios = <&gpioi 13 GPIO_ACTIVE_LOW>;
 	};
 };
 
@@ -164,16 +164,27 @@ zephyr_udc0: &usbotg_fs {
 
 &mac {
 	status = "okay";
-	pinctrl-0 = <&eth_mdc_pc1
-		     &eth_rxd0_pc4
+	pinctrl-0 = <&eth_rxd0_pc4
 		     &eth_rxd1_pc5
 		     &eth_ref_clk_pa1
-		     &eth_mdio_pa2
 		     &eth_crs_dv_pa7
 		     &eth_tx_en_pg11
 		     &eth_txd0_pg13
 		     &eth_txd1_pg14>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
+	pinctrl-names = "default";
+
+	eth_phy: ethernet-phy@0 {
+		compatible = "ethernet-phy";
+		reg = <0x00>;
+	};
 };
 
 &quadspi {
diff --git a/boards/st/stm32f7508_dk/stm32f7508_dk.yaml b/boards/st/stm32f7508_dk/stm32f7508_dk.yaml
index 9415c4660d1..28ff27942f5 100644
--- a/boards/st/stm32f7508_dk/stm32f7508_dk.yaml
+++ b/boards/st/stm32f7508_dk/stm32f7508_dk.yaml
@@ -8,7 +8,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 320
 flash: 64
 supported:
diff --git a/boards/st/stm32f769i_disco/doc/index.rst b/boards/st/stm32f769i_disco/doc/index.rst
index 5324f080bed..7805c58c2e4 100644
--- a/boards/st/stm32f769i_disco/doc/index.rst
+++ b/boards/st/stm32f769i_disco/doc/index.rst
@@ -87,37 +87,7 @@ More information about STM32F769NIH6 can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32f769i_disco board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | Ethernet                            |
-+-----------+------------+-------------------------------------+
-| QSPI NOR  | on-chip    | flash                               |
-+-----------+------------+-------------------------------------+
-| FMC       | on-chip    | memc (SDRAM)                        |
-+-----------+------------+-------------------------------------+
-| TOUCH     | off-chip   | ft5336(FT6202)                      |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm32f769i_disco/stm32f769i_disco_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -158,6 +128,8 @@ settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32F769I Discovery kit includes an ST-LINK/V2 embedded debug tool interface.
 
 Applications for the ``stm32f769i_disco`` board configuration can be built and
diff --git a/boards/st/stm32f769i_disco/stm32f769i_disco.dts b/boards/st/stm32f769i_disco/stm32f769i_disco.dts
index 94dd6f6bb22..ba6837339c8 100644
--- a/boards/st/stm32f769i_disco/stm32f769i_disco.dts
+++ b/boards/st/stm32f769i_disco/stm32f769i_disco.dts
@@ -52,10 +52,6 @@
 			gpios = <&gpioa 12 GPIO_ACTIVE_HIGH>;
 			label = "User LD3";
 		};
-		red_led_4:led_4 {
-			gpios = <&gpiod 4 GPIO_ACTIVE_HIGH>;
-			label = "User LD4";
-		};
 	};
 
 	gpio_keys {
@@ -76,7 +72,6 @@
 		led0 = &red_led_1;
 		led1 = &green_led_2;
 		led2 = &green_led_3;
-		led3 = &red_led_4;
 		sw0 = &user_button;
 	};
 
@@ -144,7 +139,7 @@ arduino_serial: &usart6 {};
 	ft6202: ft6202@2a {
 		compatible = "focaltech,ft5336";
 		reg = <0x2a>;
-		int-gpios = <&gpioi 13 0>;
+		int-gpios = <&gpioi 13 GPIO_ACTIVE_LOW>;
 	};
 };
 
@@ -156,16 +151,27 @@ arduino_serial: &usart6 {};
 
 &mac {
 	status = "okay";
-	pinctrl-0 = <&eth_mdc_pc1
-		     &eth_rxd0_pc4
+	pinctrl-0 = <&eth_rxd0_pc4
 		     &eth_rxd1_pc5
 		     &eth_ref_clk_pa1
-		     &eth_mdio_pa2
 		     &eth_crs_dv_pa7
 		     &eth_tx_en_pg11
 		     &eth_txd0_pg13
 		     &eth_txd1_pg14>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
+	pinctrl-names = "default";
+
+	eth_phy: ethernet-phy@0 {
+		compatible = "ethernet-phy";
+		reg = <0x00>;
+	};
 };
 
 &sdmmc2 {
diff --git a/boards/st/stm32f769i_disco/stm32f769i_disco.yaml b/boards/st/stm32f769i_disco/stm32f769i_disco.yaml
index 69f06949e2a..db78a18bff6 100644
--- a/boards/st/stm32f769i_disco/stm32f769i_disco.yaml
+++ b/boards/st/stm32f769i_disco/stm32f769i_disco.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 384
 flash: 2048
 supported:
@@ -17,5 +16,4 @@ supported:
   - arduino_gpio
   - netif:eth
   - memc
-  - kscan:touch
 vendor: st
diff --git a/boards/st/stm32g0316_disco/doc/index.rst b/boards/st/stm32g0316_disco/doc/index.rst
index 45741fad177..f2694c7ed84 100644
--- a/boards/st/stm32g0316_disco/doc/index.rst
+++ b/boards/st/stm32g0316_disco/doc/index.rst
@@ -30,29 +30,7 @@ For more information about the STM32G03x SoC and the STM32G0316-DISCO board, see
 Supported Features
 ==================
 
-The Zephyr stm32g0316_disco board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by the port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/stm32g0316_disco/stm32g0316_disco_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -74,6 +52,8 @@ Default Zephyr Peripheral Mapping:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The STM32G0316-DISCO board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``stm32g0316_disco`` board configuration can be built the
diff --git a/boards/st/stm32g0316_disco/stm32g0316_disco.yaml b/boards/st/stm32g0316_disco/stm32g0316_disco.yaml
index 3b6cb215ce4..0e557764560 100644
--- a/boards/st/stm32g0316_disco/stm32g0316_disco.yaml
+++ b/boards/st/stm32g0316_disco/stm32g0316_disco.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 8
 flash: 32
 supported:
diff --git a/boards/st/stm32g071b_disco/doc/index.rst b/boards/st/stm32g071b_disco/doc/index.rst
index 6937ea9452e..f5b437e8f93 100644
--- a/boards/st/stm32g071b_disco/doc/index.rst
+++ b/boards/st/stm32g071b_disco/doc/index.rst
@@ -52,29 +52,7 @@ More information about STM32G071RB can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32g071b_disco board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| UCPD      | on-chip    | ucpd                                |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/stm32g071b_disco/stm32g071b_disco_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -108,6 +86,8 @@ For more details please refer to `STM32G0 Discovery board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The STM32G071B Discovery board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``stm32g071b_disco`` board configuration can be built and
diff --git a/boards/st/stm32g071b_disco/stm32g071b_disco.yaml b/boards/st/stm32g071b_disco/stm32g071b_disco.yaml
index 817860f27ac..439412af829 100644
--- a/boards/st/stm32g071b_disco/stm32g071b_disco.yaml
+++ b/boards/st/stm32g071b_disco/stm32g071b_disco.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 36
 flash: 128
 supported:
diff --git a/boards/st/stm32g081b_eval/doc/index.rst b/boards/st/stm32g081b_eval/doc/index.rst
index 27d932b096b..18d9bdedaff 100644
--- a/boards/st/stm32g081b_eval/doc/index.rst
+++ b/boards/st/stm32g081b_eval/doc/index.rst
@@ -93,29 +93,7 @@ More information about STM32G081RB can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32g081b_eval board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| UCPD      | on-chip    + ucpd                                |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/stm32g081b_eval/stm32g081b_eval_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -146,6 +124,8 @@ For more details please refer to `STM32G0 Evaluation board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The STM32G081B Evaluation board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Applications for the ``stm32g081b_eval`` board configuration can be built and
diff --git a/boards/st/stm32g081b_eval/stm32g081b_eval.yaml b/boards/st/stm32g081b_eval/stm32g081b_eval.yaml
index 313faf236a8..13efbbc72f3 100644
--- a/boards/st/stm32g081b_eval/stm32g081b_eval.yaml
+++ b/boards/st/stm32g081b_eval/stm32g081b_eval.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
 flash: 128
 supported:
diff --git a/boards/st/stm32h573i_dk/board.cmake b/boards/st/stm32h573i_dk/board.cmake
index f1a703cda64..dedf7ebcd0a 100644
--- a/boards/st/stm32h573i_dk/board.cmake
+++ b/boards/st/stm32h573i_dk/board.cmake
@@ -10,6 +10,8 @@ endif()
 
 board_runner_args(pyocd "--target=stm32h573iikx")
 
+board_runner_args(probe_rs "--chip=STM32H573II")
+
 board_runner_args(openocd "--tcl-port=6666")
 board_runner_args(openocd --cmd-pre-init "gdb_report_data_abort enable")
 board_runner_args(openocd "--no-halt")
@@ -17,5 +19,6 @@ board_runner_args(openocd "--no-halt")
 # keep first
 include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/probe-rs.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
 # FIXME: official openocd runner not yet available.
diff --git a/boards/st/stm32h573i_dk/doc/index.rst b/boards/st/stm32h573i_dk/doc/index.rst
index c5ae45a9a20..3bbabc2f28f 100644
--- a/boards/st/stm32h573i_dk/doc/index.rst
+++ b/boards/st/stm32h573i_dk/doc/index.rst
@@ -147,62 +147,7 @@ More information about STM32H573 can be found here:
 Supported Features
 ==================
 
-The Zephyr STM32H573I_DK board configuration supports the following
-hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | DAC Controller                      |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | PWM                                 |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | Real Time Clock                     |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c bus                             |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi bus                             |
-+-----------+------------+-------------------------------------+
-| OCTOSPI   | on-chip    | octospi                             |
-+-----------+------------+-------------------------------------+
-| CAN       | on-chip    | can bus                             |
-+-----------+------------+-------------------------------------+
-| AES       | on-chip    | crypto                              |
-+-----------+------------+-------------------------------------+
-| SDMMC     | on-chip    | disk access                         |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB full-speed host/device bus      |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig and dts files:
-
-- Secure target:
-
-  - :zephyr_file:`boards/st/stm32h573i_dk/stm32h573i_dk_defconfig`
-  - :zephyr_file:`boards/st/stm32h573i_dk/stm32h573i_dk.dts`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -239,6 +184,8 @@ assigned to USART1. Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32H573I-DK Discovery board includes an ST-LINK/V3E embedded debug tool interface.
 
 Applications for the ``stm32h573i_dk`` board configuration can be built and
@@ -250,7 +197,7 @@ OpenOCD Support
 
 For now, OpenOCD support  for STM32H5 is not available on upstream OpenOCD.
 You can check `OpenOCD official Github mirror`_.
-In order to use it though, you should clone from the cutomized
+In order to use it though, you should clone from the customized
 `STMicroelectronics OpenOCD Github`_ and compile it following usual README guidelines.
 Once it is done, you can set the OPENOCD and OPENOCD_DEFAULT_PATH variables in
 :zephyr_file:`boards/st/stm32h573i_dk/board.cmake` to point the build
diff --git a/boards/st/stm32h573i_dk/stm32h573i_dk.dts b/boards/st/stm32h573i_dk/stm32h573i_dk.dts
index 97664d80eba..896da6606d2 100644
--- a/boards/st/stm32h573i_dk/stm32h573i_dk.dts
+++ b/boards/st/stm32h573i_dk/stm32h573i_dk.dts
@@ -166,6 +166,8 @@
 		     &eth_txd0_pg13
 		     &eth_txd1_pg12>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
 };
 
 &mdio {
@@ -173,10 +175,9 @@
 	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
 	pinctrl-names = "default";
 
-	ethernet-phy@0 {
+	eth_phy: ethernet-phy@0 {
 		compatible = "ethernet-phy";
 		reg = <0x00>;
-		status = "okay";
 	};
 };
 
diff --git a/boards/st/stm32h735g_disco/doc/index.rst b/boards/st/stm32h735g_disco/doc/index.rst
index 919451922dc..b5f2786a267 100644
--- a/boards/st/stm32h735g_disco/doc/index.rst
+++ b/boards/st/stm32h735g_disco/doc/index.rst
@@ -34,46 +34,7 @@ More information about STM32H735 can be found here:
 Supported Features
 ==================
 
-The current Zephyr stm32h735g_disco board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| FMC       | on-chip    | memc (SDRAM)                        |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| FDCAN1    | on-chip    | CAN-FD Controller                   |
-+-----------+------------+-------------------------------------+
-| FDCAN2    | on-chip    | CAN-FD Controller                   |
-+-----------+------------+-------------------------------------+
-| FDCAN3    | on-chip    | CAN-FD Controller (disabled by      |
-|           |            | default. Solder bridges SB29 and    |
-|           |            | SB30 need to be closed for FDCAN3   |
-|           |            | to work)                            |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb_device                          |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/stm32h735g_disco/stm32h735g_disco_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -107,6 +68,8 @@ COM port interface. Default communication settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32H735G-DISCO board includes an ST-LINK/V3 embedded debug tool interface.
 
 See :ref:`build_an_application` for more information about application builds.
diff --git a/boards/st/stm32h735g_disco/stm32h735g_disco.dts b/boards/st/stm32h735g_disco/stm32h735g_disco.dts
index 0dc2d17f93d..06afe9fb645 100644
--- a/boards/st/stm32h735g_disco/stm32h735g_disco.dts
+++ b/boards/st/stm32h735g_disco/stm32h735g_disco.dts
@@ -138,6 +138,8 @@
 		     &eth_txd0_pb12
 		     &eth_txd1_pb13>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
 	status = "okay";
 };
 
@@ -146,10 +148,9 @@
 	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
 	pinctrl-names = "default";
 
-	ethernet-phy@0 {
+	eth_phy: ethernet-phy@0 {
 		compatible = "ethernet-phy";
 		reg = <0x00>;
-		status = "okay";
 	};
 };
 
diff --git a/boards/st/stm32h735g_disco/stm32h735g_disco.yaml b/boards/st/stm32h735g_disco/stm32h735g_disco.yaml
index cf0bbb425ba..37e3671d9bc 100644
--- a/boards/st/stm32h735g_disco/stm32h735g_disco.yaml
+++ b/boards/st/stm32h735g_disco/stm32h735g_disco.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 368
 flash: 1024
 supported:
diff --git a/boards/st/stm32h745i_disco/Kconfig.defconfig b/boards/st/stm32h745i_disco/Kconfig.defconfig
index 1788447e060..4d89e712958 100644
--- a/boards/st/stm32h745i_disco/Kconfig.defconfig
+++ b/boards/st/stm32h745i_disco/Kconfig.defconfig
@@ -11,13 +11,6 @@ if NETWORKING
 config NET_L2_ETHERNET
 	default y
 
-config ETH_STM32_HAL_MII
-	default y
-
-# STM32H745I-DISCO have PHY connected to address 1
-config ETH_STM32_HAL_PHY_ADDRESS
-	default 1
-
 endif # NETWORKING
 
 config MEMC
diff --git a/boards/st/stm32h745i_disco/doc/index.rst b/boards/st/stm32h745i_disco/doc/index.rst
index 24dab98ae4c..f1b9d60bec0 100644
--- a/boards/st/stm32h745i_disco/doc/index.rst
+++ b/boards/st/stm32h745i_disco/doc/index.rst
@@ -60,43 +60,7 @@ More information about STM32H747XIH6 can be found here:
 Supported Features
 ==================
 
-The current Zephyr stm32h745i_disco board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| QSPI NOR  | on-chip    | off-chip flash                      |
-+-----------+------------+-------------------------------------+
-| FDCAN     | on-chip    | fdcan                               |
-+-----------+------------+-------------------------------------+
-| FMC       | on-chip    | memc (SDRAM)                        |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration per core can be found in the defconfig files:
-:zephyr_file:`boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7_defconfig` and
-:zephyr_file:`boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m4_defconfig`
+.. zephyr:board-supported-hw::
 
 For more details please refer to `STM32H745-Disco UM`_.
 
@@ -143,6 +107,8 @@ two cores. This is done in 3 ways:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32H745I-DISCO board includes an ST-LINK/V3 embedded debug tool interface.
 
 Applications for the ``stm32h745i_disco`` board should be built per core target,
diff --git a/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts b/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts
index f1e7204a864..1d6f188f19a 100644
--- a/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts
+++ b/boards/st/stm32h745i_disco/stm32h745i_disco_stm32h745xx_m7.dts
@@ -144,6 +144,8 @@
 		     &eth_txd0_pg13
 		     &eth_rx_er_pi10>;
 	pinctrl-names = "default";
+	phy-connection-type = "mii";
+	phy-handle = <&eth_phy>;
 };
 
 &mdio {
@@ -151,10 +153,9 @@
 	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
 	pinctrl-names = "default";
 
-	ethernet-phy@1 {
+	eth_phy: ethernet-phy@1 {
 		compatible = "ethernet-phy";
 		reg = <0x01>;
-		status = "okay";
 	};
 };
 
diff --git a/boards/st/stm32h747i_disco/doc/index.rst b/boards/st/stm32h747i_disco/doc/index.rst
index 8d61400060a..ff7b5446ed8 100644
--- a/boards/st/stm32h747i_disco/doc/index.rst
+++ b/boards/st/stm32h747i_disco/doc/index.rst
@@ -41,51 +41,14 @@ More information about STM32H747XIH6 can be found here:
 Supported Features
 ==================
 
-The current Zephyr stm32h747i_disco board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | ethernet  (*)                       |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| FMC       | on-chip    | memc (SDRAM)                        |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| QSPI NOR  | on-chip    | off-chip flash                      |
-+-----------+------------+-------------------------------------+
-| SDMMC     | on-chip    | disk access                         |
-+-----------+------------+-------------------------------------+
-| IPM       | on-chip    | virtual mailbox based on HSEM       |
-+-----------+------------+-------------------------------------+
-| DISPLAY   | on-chip    | MIPI DSI Host with shield (MP1166)  |
-|           |            | st_b_lcd40_dsi1_mb1166              |
-+-----------+------------+-------------------------------------+
-
-(*) From UM2411 Rev 4:
+.. zephyr:board-supported-hw::
+
+.. note:
+   From UM2411 Rev 4:
    With the default setting, the Ethernet feature is not working because of
    a conflict between ETH_MDC and SAI4_D1 of the MEMs digital microphone.
    Make sure you have SB8 closed and SB21 open to get Ethernet working.
 
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration per core can be found in the defconfig files:
-:zephyr_file:`boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7_defconfig` and
-:zephyr_file:`boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4_defconfig`
-
 Pin Mapping
 ===========
 
@@ -192,6 +155,8 @@ two cores. This is done in 3 ways:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32H747I-DISCO board includes an ST-LINK/V3 embedded debug tool interface.
 
 Applications for the ``stm32h747i_disco`` board should be built per core target,
diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4.yaml b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4.yaml
index 2a544e16701..553524ff898 100644
--- a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4.yaml
+++ b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m4.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 288
 flash: 1024
 supported:
diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts
index b5b0ee1cd88..9c01e0ef262 100644
--- a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts
+++ b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.dts
@@ -144,6 +144,8 @@
 		     &eth_txd0_pg13
 		     &eth_txd1_pg12>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
 };
 
 &mdio {
@@ -151,10 +153,9 @@
 	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
 	pinctrl-names = "default";
 
-	ethernet-phy@0 {
+	eth_phy: ethernet-phy@0 {
 		compatible = "ethernet-phy";
 		reg = <0x00>;
-		status = "okay";
 	};
 };
 
@@ -238,6 +239,7 @@ zephyr_udc0: &usbotg_hs {
 			&sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
 	pinctrl-names = "default";
 	cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>;
+	disk-name = "SD";
 };
 
 &quadspi {
diff --git a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.yaml b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.yaml
index d566de9a4ca..a7ff5d4a4bd 100644
--- a/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.yaml
+++ b/boards/st/stm32h747i_disco/stm32h747i_disco_stm32h747xx_m7.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 512
 flash: 1024
 supported:
diff --git a/boards/st/stm32h750b_dk/doc/index.rst b/boards/st/stm32h750b_dk/doc/index.rst
index 8dacd802075..a360cf8543c 100644
--- a/boards/st/stm32h750b_dk/doc/index.rst
+++ b/boards/st/stm32h750b_dk/doc/index.rst
@@ -34,37 +34,7 @@ More information about STM32H750 can be found here:
 Supported Features
 ==================
 
-The current Zephyr stm32h750b_dk board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| QSPI NOR  | on-chip    | off-chip flash                      |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| LTDC      | on-chip    | display                             |
-+-----------+------------+-------------------------------------+
-| QSPI NOR  | on-chip    | off-chip flash                      |
-+-----------+------------+-------------------------------------+
-| FMC       | on-chip    | memc (SDRAM)                        |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/stm32h750b_dk/stm32h750b_dk_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -97,6 +67,8 @@ COM port interface. Default communication settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32H750B Discovery kit includes an ST-LINK-V3E embedded debug tool interface.
 This probe allows flashing and debugging the board using various tools.
 
diff --git a/boards/st/stm32h750b_dk/stm32h750b_dk.dts b/boards/st/stm32h750b_dk/stm32h750b_dk.dts
index b5c9189288b..34a82721b02 100644
--- a/boards/st/stm32h750b_dk/stm32h750b_dk.dts
+++ b/boards/st/stm32h750b_dk/stm32h750b_dk.dts
@@ -21,6 +21,7 @@
 		zephyr,flash = &flash0;
 		zephyr,flash-controller = &mt25ql512ab1;
 		zephyr,display = &ltdc;
+		zephyr,code-partition = &slot0_partition;
 	};
 
 	sdram2: sdram@d0000000 {
@@ -78,6 +79,19 @@
 	status = "okay";
 };
 
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		/* Flash has 128KB sector size */
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 DT_SIZE_K(128)>;
+		};
+	};
+};
+
 &ltdc {
 	pinctrl-0 = <&ltdc_r0_pi15 &ltdc_r1_pj0 &ltdc_r2_pj1 &ltdc_r3_ph9
 		&ltdc_r4_pj3 &ltdc_r5_pj4 &ltdc_r6_pj5 &ltdc_r7_pj6
@@ -165,6 +179,8 @@
 	dual-flash;
 	status = "okay";
 
+	/* Sector erase 64KB uniform granularity */
+	/* Subsector erase 4KB, 32KB granularity */
 	mt25ql512ab1: qspi-nor-flash-1@90000000 {
 		compatible = "st,stm32-qspi-nor";
 		reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
@@ -178,8 +194,19 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			partition@0 {
-				reg = <0x0 DT_SIZE_M(64)>;
+			slot0_partition: partition@0 {
+				label = "image-0";
+				reg = <0x00000000 DT_SIZE_K(2048)>;
+			};
+
+			slot1_partition: partition@200000 {
+				label = "image-1";
+				reg = <0x00200000 DT_SIZE_K(2048)>;
+			};
+
+			storage_partition: partition@400000 {
+				label = "storage";
+				reg = <0x00400000 DT_SIZE_K(128)>;
 			};
 		};
 	};
diff --git a/boards/st/stm32h750b_dk/stm32h750b_dk.yaml b/boards/st/stm32h750b_dk/stm32h750b_dk.yaml
index da7d087b060..24751cc5c13 100644
--- a/boards/st/stm32h750b_dk/stm32h750b_dk.yaml
+++ b/boards/st/stm32h750b_dk/stm32h750b_dk.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 1024
 flash: 128
 supported:
diff --git a/boards/st/stm32h757i_eval/CMakeLists.txt b/boards/st/stm32h757i_eval/CMakeLists.txt
new file mode 100644
index 00000000000..5b63ce05f24
--- /dev/null
+++ b/boards/st/stm32h757i_eval/CMakeLists.txt
@@ -0,0 +1,10 @@
+#
+# Copyright (c) 2023 BrainCo Inc.
+# Copyright (c) 2025 Foss Analytical A/S
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+# Add custom linker section to relocate framebuffers to PSRAM
+zephyr_linker_sources_ifdef(CONFIG_LV_Z_VDB_CUSTOM_SECTION
+  SECTIONS dc_ram.ld)
diff --git a/boards/st/stm32h757i_eval/Kconfig.defconfig b/boards/st/stm32h757i_eval/Kconfig.defconfig
new file mode 100644
index 00000000000..0d868227ea1
--- /dev/null
+++ b/boards/st/stm32h757i_eval/Kconfig.defconfig
@@ -0,0 +1,19 @@
+# STM32H757I EVAL board configuration
+
+# Copyright (c) 2019 Linaro Limited
+# Copyright (c) 2025 Foss Analytical A/S
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_STM32H757I_EVAL
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+endif # NETWORKING
+
+config DISK_DRIVER_SDMMC
+	default y if DISK_DRIVERS
+
+endif # BOARD_STM32H757I_EVAL
diff --git a/boards/st/stm32h757i_eval/Kconfig.stm32h757i_eval b/boards/st/stm32h757i_eval/Kconfig.stm32h757i_eval
new file mode 100644
index 00000000000..d77cfe9280c
--- /dev/null
+++ b/boards/st/stm32h757i_eval/Kconfig.stm32h757i_eval
@@ -0,0 +1,9 @@
+# STM32H757I EVAL board configuration
+
+# Copyright (c) 2019 Linaro Limited
+# Copyright (c) 2025 Foss Analytical A/S
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_STM32H757I_EVAL
+	select SOC_STM32H757XX_M7 if BOARD_STM32H757I_EVAL_STM32H757XX_M7
+	select SOC_STM32H757XX_M4 if BOARD_STM32H757I_EVAL_STM32H757XX_M4
diff --git a/boards/st/stm32h757i_eval/board.cmake b/boards/st/stm32h757i_eval/board.cmake
new file mode 100644
index 00000000000..b0a38149731
--- /dev/null
+++ b/boards/st/stm32h757i_eval/board.cmake
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2019 STMicroelectronics
+# Copyright (c) 2025 Foss Analytical A/S
+
+# keep first
+board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
+
+if(CONFIG_BOARD_STM32H757I_EVAL_STM32H757XX_M7)
+  board_runner_args(jlink "--device=STM32H757XI")
+  board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_stm32h757i_eval_m7.cfg")
+  board_runner_args(openocd --target-handle=_CHIPNAME.cpu0)
+elseif(CONFIG_BOARD_STM32H757I_EVAL_STM32H757XX_M4)
+  board_runner_args(jlink "--device=STM32H757XI_M4")
+  board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd_stm32h757i_eval_m4.cfg")
+  board_runner_args(openocd --target-handle=_CHIPNAME.cpu1)
+endif()
+
+# keep first
+include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/st/stm32h757i_eval/board.yml b/boards/st/stm32h757i_eval/board.yml
new file mode 100644
index 00000000000..5f73c601f91
--- /dev/null
+++ b/boards/st/stm32h757i_eval/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: stm32h757i_eval
+  full_name: STM32H757I Eval
+  vendor: st
+  socs:
+    - name: stm32h757xx
diff --git a/boards/st/stm32h757i_eval/dc_ram.ld b/boards/st/stm32h757i_eval/dc_ram.ld
new file mode 100644
index 00000000000..56db3a2b997
--- /dev/null
+++ b/boards/st/stm32h757i_eval/dc_ram.ld
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2023 BrainCo Inc.
+ * Copyright (c) 2025 Foss Analytical A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(sdram2), okay)
+GROUP_START(SDRAM2)
+
+	SECTION_PROLOGUE(_STM32_SDRAM2_SECTION_NAME, (NOLOAD),)
+	{
+		*(.lvgl_buf)
+	} GROUP_LINK_IN(SDRAM2)
+
+GROUP_END(SDRAM2)
+#endif
diff --git a/boards/st/stm32h757i_eval/doc/img/stm32h757i_eval.webp b/boards/st/stm32h757i_eval/doc/img/stm32h757i_eval.webp
new file mode 100644
index 00000000000..246d4524e14
Binary files /dev/null and b/boards/st/stm32h757i_eval/doc/img/stm32h757i_eval.webp differ
diff --git a/boards/st/stm32h757i_eval/doc/index.rst b/boards/st/stm32h757i_eval/doc/index.rst
new file mode 100644
index 00000000000..f2fe7f1bd5c
--- /dev/null
+++ b/boards/st/stm32h757i_eval/doc/index.rst
@@ -0,0 +1,259 @@
+.. zephyr:board:: stm32h757i_eval
+
+Overview
+********
+
+The evaluation kit enables a wide diversity of applications taking benefit
+from audio, multi-sensor support, graphics, security, video,
+and high-speed connectivity features.
+
+The STM32H7X7I-eval board comes with both the STM32H757XI SoC and the STM32H747XI SoC.
+But in the following documentation, we will focus on the STM32H757XI SoC, but both should work.
+
+The board includes an STM32H757XI SoC with a high-performance DSP, Arm Cortex-M7 + Cortex-M4 MCU,
+with 2MBytes of Flash memory, 1MB RAM, 480 MHz CPU, Art Accelerator, L1 cache, external memory interface,
+large set of peripherals, SMPS, and MIPI-DSI.
+
+Additionally, the board features:
+
+- On-board ST-LINK/V3E supporting USB reenumeration capability
+- USB ST-LINK functions: virtual COM port, mass storage, debug port
+- Flexible power-supply options:
+
+  - ST-LINK USB VBUS, USB OTG HS connector, or external sources
+
+- 4” capacitive touch LCD display module with MIPI® DSI interface
+- Ethernet compliant with IEEE802.3-2002
+- USB OTG HS and OTG FS
+- I2C compatible serial interface
+- RTC with rechargeable backup battery
+- SAI audio DAC
+- ST-MEMS digital microphones
+- 8-Gbyte (or more) SDIO 3.0 interface microSD card
+- 8 M×32bit SDRAM, 1 M×16bit SDRAM and 8 M×16bit NOR flash memory
+- 1-Gbit twin Quad-SPI NOR flash memory or two 512-Mbit Quad-SPI NOR flash memories
+- Potentiometer
+- 4 color user LEDs
+- Reset, wakeup, tamper, or key buttons
+- Joystick with 4-direction control and selector
+
+
+More information about the board can be found at the `STM32H757I-EVAL website`_.
+More information about STM32H757XIH6 can be found here:
+
+- `STM32H757XI on www.st.com`_
+- `STM32H757xx reference manual`_
+- `STM32H757xx datasheet`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Pin Mapping
+===========
+
+STM32H757I Discovery kit has 9 GPIO controllers. These controllers are responsible for pin muxing,
+input/output, pull-up, etc.
+
+For more details please refer to `STM32H757I-EVAL website`_.
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+- UART_1 TX/RX : PA9/PA10 (ST-Link Virtual Port Com)
+- SDMMC_1 D0/D1/D2/D3/CK/CMD: PC8/PC9/PC10/PC11/PC12/PD2
+- LD1 : PK3
+- LD2 : PK4
+- LD3 : PK5
+- LD4 : PK6
+- W-UP : PA0
+- J-CENTER : PB0
+- J-DOWN : PB1
+- J-LEFT : PB2
+- J-RIGHT : PB3
+- J-UP : PB4
+
+System Clock
+============
+
+The STM32H757I System Clock can be driven by an internal or external oscillator,
+as well as by the main PLL clock. By default, the CPU1 (Cortex-M7) System clock
+is driven by the PLL clock at 400MHz, and the CPU2 (Cortex-M4) System clock
+is driven at 200MHz. PLL clock is feed by a 25MHz high speed external clock.
+
+Serial Port
+===========
+
+Default configuration assigns USART1 to the CPU1. The Zephyr console
+output is assigned to UART1 which connected to the onboard ST-LINK/V3.0. Virtual
+COM port interface. Default communication settings are 115200 8N1.
+
+Display
+=======
+
+The STM32H757I Eval kit has a dedicated DSI LCD connector **CN15**, where
+the MB1166 (B-LCD40-DSI1) display extension board can be mounted. Enable display
+support in Zephyr by adding the shield ``st_b_lcd40_dsi1_mb1166`` or
+``st_b_lcd40_dsi1_mb1166_a09`` to your build command, for example:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/drivers/display
+   :board: stm32h757i_eval/stm32h757xx/m7
+   :shield: st_b_lcd40_dsi1_mb1166
+   :goals: build flash
+
+.. note::
+   The shield comes in different hardware revisions, the MB1166-A09
+   is utilizing a NT35510 panel controller and shall specifically
+   use ``st_b_lcd40_dsi1_mb1166_a09`` as SHIELD when building.
+   Prior versions are utilizing an OTM8009a controller and shall
+   use shield name without postfix, that is: ``st_b_lcd40_dsi1_mb1166``.
+   Shield version is printed on a sticker placed below the two bottom
+   mounting holes and has the format: MB1166-Axx.
+
+Resources sharing
+=================
+
+The dual core nature of STM32H757 SoC requires sharing HW resources between the
+two cores. This is done in 3 ways:
+
+- **Compilation**: Clock configuration is only accessible to M7 core. M4 core only
+  has access to bus clock activation and deactivation.
+- **Static pre-compilation assignment**: Peripherals such as a UART are assigned in
+  devicetree before compilation. The user must ensure peripherals are not assigned
+  to both cores at the same time.
+- **Run time protection**: Interrupt-controller and GPIO configurations could be
+  accessed by both cores at run time. Accesses are protected by a hardware semaphore
+  to avoid potential concurrent access issues.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+STM32H757I-EVAL board includes an ST-LINK/V3 embedded debug tool interface.
+
+Applications for the ``stm32h757i_disco`` board should be built per core target,
+using either ``stm32h757i_eval/stm32h757xx/m7`` or ``stm32h757i_eval/stm32h757xx/m4``
+as the target.
+See :ref:`build_an_application` for more information about application builds.
+
+.. note::
+
+   Check if the board's ST-LINK V3 has the newest FW version. It can be updated
+   using `STM32CubeProgrammer`_.
+
+.. note::
+
+   With OpenOCD, sometimes, flashing does not work. It is necessary to
+   erase the flash (with STM32CubeProgrammer for example) to make it work again.
+   Debugging with OpenOCD is currently working for this board only with Cortex M7,
+   not Cortex M4.
+
+
+Flashing
+========
+
+Flashing operation will depend on the target to be flashed and the SoC
+option bytes configuration.
+
+The board is configured to be flashed using west `STM32CubeProgrammer`_ runner
+for both cores, so its :ref:`installation <stm32cubeprog-flash-host-tools>` is required.
+The target core is detected automatically.
+
+Alternatively, OpenOCD or JLink can also be used to flash the board using
+the ``--runner`` (or ``-r``) option:
+
+.. code-block:: console
+
+   $ west flash --runner openocd
+   $ west flash --runner jlink
+
+It is advised to use `STM32CubeProgrammer`_ to check and update option bytes
+configuration.
+
+By default:
+
+  - CPU1 (Cortex-M7) boot address is set to 0x80000000 (OB: BOOT_CM7_ADD0)
+  - CPU2 (Cortex-M4) boot address is set to 0x81000000 (OB: BOOT_CM4_ADD0)
+
+Also, default out of the box board configuration enables CM7 and CM4 boot when
+board is powered (Option bytes BCM7 and BCM4 are checked).
+It is possible to change Option Bytes so that CM7 boots first in stand alone,
+and CM7 will wakeup CM4 after clock initialization.
+Drivers are able to take into account both Option Bytes configurations
+automatically.
+
+Zephyr flash configuration has been set to meet these default settings.
+
+Flashing an application to STM32H757I M7 Core
+---------------------------------------------
+
+First, connect the STM32H757I Eval kit to your host computer using
+the USB port to prepare it for flashing. Then build and flash your application.
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: stm32h757i_eval/stm32h757xx/m7
+   :goals: build flash
+
+Run a serial host program to connect with your board:
+
+.. code-block:: console
+
+   $ minicom -D /dev/ttyACM0
+
+You should see the following message on the console:
+
+.. code-block:: console
+
+   Hello World! stm32h757i_disco
+
+.. note::
+  Sometimes, flashing is not working. It is necessary to erase the flash
+  (with STM32CubeProgrammer for example) to make it work again.
+
+Similarly, you can build and flash samples on the M4 target. For this, please
+take care of the resource sharing (UART port used for console for instance).
+
+Here is an example for the :zephyr:code-sample:`blinky` application on M4 core.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: stm32h757i_eval/stm32h757xx/m7
+   :goals: build flash
+
+Debugging
+=========
+
+You can debug an application on Cortex M7 side in the usual way.  Here is an example
+for the :zephyr:code-sample:`hello_world` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: stm32h757i_eval/stm32h757xx/m7
+   :goals: debug
+
+Debugging a Zephyr application on Cortex M4 side with west is currently not available.
+As a workaround, you can use `STM32CubeIDE`_.
+
+.. _STM32H757I-EVAL website:
+   https://www.st.com/en/evaluation-tools/stm32h757i-eval.html
+
+.. _STM32H757XI on www.st.com:
+   https://www.st.com/en/microcontrollers-microprocessors/stm32h757xi.html
+
+.. _STM32H757xx reference manual:
+   https://www.st.com/resource/en/reference_manual/rm0399-stm32h745755-and-stm32h747757-advanced-armbased-32bit-mcus-stmicroelectronics.pdf
+
+.. _STM32H757xx datasheet:
+   https://www.st.com/resource/en/datasheet/stm32h757xi.pdf
+
+.. _STM32CubeProgrammer:
+   https://www.st.com/en/development-tools/stm32cubeprog.html
+
+.. _STM32CubeIDE:
+   https://www.st.com/en/development-tools/stm32cubeide.html
diff --git a/boards/st/stm32h757i_eval/stm32h757i_eval.dtsi b/boards/st/stm32h757i_eval/stm32h757i_eval.dtsi
new file mode 100644
index 00000000000..822019339f9
--- /dev/null
+++ b/boards/st/stm32h757i_eval/stm32h757i_eval.dtsi
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2019 Linaro Limited
+ * Copyright (c) 2025 Foss Analytical A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	leds {
+		compatible = "gpio-leds";
+
+		green_led_1: led_1 {
+			gpios = <&gpiok 3 GPIO_ACTIVE_LOW>;
+			label = "User LD1";
+			status = "disabled";
+		};
+
+		orange_led_2: led_2 {
+			gpios = <&gpiok 4 GPIO_ACTIVE_LOW>;
+			label = "User LD2";
+			status = "disabled";
+		};
+
+		red_led_3: led_3 {
+			gpios = <&gpiok 5 GPIO_ACTIVE_LOW>;
+			label = "User LD3";
+			status = "disabled";
+		};
+
+		blue_led_4: led_4 {
+			gpios = <&gpiok 6 GPIO_ACTIVE_LOW>;
+			label = "User LD4";
+			status = "disabled";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		wake_up: button_1 {
+			label = "Wakeup";
+			gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
+			status = "disabled";
+			zephyr,code = <INPUT_KEY_WAKEUP>;
+		};
+
+		tamper: button_2 {
+			label = "Tamper";
+			gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>;
+			status = "disabled";
+			zephyr,code = <INPUT_KEY_ENTER>;
+		};
+
+		joy_center: joystick_center {
+			label = "joystick center";
+			gpios = <&gpiob 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			status = "disabled";
+			zephyr,code = <INPUT_KEY_ENTER>;
+		};
+
+		joy_down: joystick_down {
+			label = "joystick down";
+			gpios = <&gpiob 1 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			status = "disabled";
+			zephyr,code = <INPUT_KEY_DOWN>;
+		};
+
+		joy_up: joystick_up {
+			label = "joystick up";
+			gpios = <&gpiob 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			status = "disabled";
+			zephyr,code = <INPUT_KEY_UP>;
+		};
+
+		joy_left: joystick_left {
+			label = "joystick left";
+			gpios = <&gpiob 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			status = "disabled";
+			zephyr,code = <INPUT_KEY_LEFT>;
+		};
+
+		joy_right: joystick_right {
+			label = "joystick right";
+			gpios = <&gpiob 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			status = "disabled";
+			zephyr,code = <INPUT_KEY_RIGHT>;
+		};
+	};
+
+	dsi_lcd_qsh_030: connector_dsi_lcd {
+		compatible = "st,dsi-lcd-qsh-030";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <4 0 &gpiob 14 0>,	/* TOUCH_INT */
+			   <35 0 &gpioe 5 0>,	/* SCLK/MCLK */
+			   <37 0 &gpioe 4 0>,	/* LRCLK */
+			   <39 0 &gpioe 6 0>,	/* I2S */
+			   <40 0 &gpiob 7 0>,	/* I2C4_SDA (=>I2C1_SDA) */
+			   <44 0 &gpiod 12 0>,	/* I2C4_SCL (=>I2C1_SCL) */
+			   <45 0 &gpioa 8 0>,	/* CEC_CLK */
+			   <47 0 &gpioa 15 0>,	/* CEC */
+			   <49 0 &gpioj 2 0>,	/* DSI_TE */
+			   <53 0 &gpioa 6 0>,	/* LCD_BL_CTRL */
+			   <57 0 &gpiof 10 0>;	/* DSI_RESET */
+	};
+};
+
+&rcc {
+	d1cpre = <1>;
+	hpre = <2>;
+	d1ppre = <2>;
+	d2ppre1 = <2>;
+	d2ppre2 = <2>;
+	d3ppre = <2>;
+};
+
+&usart1 {
+	pinctrl-0 = <&usart1_tx_pb14 &usart1_rx_pb15>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+};
diff --git a/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m4.dts b/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m4.dts
new file mode 100644
index 00000000000..4f274e198ec
--- /dev/null
+++ b/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m4.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2019 Linaro Limited
+ * Copyright (c) 2025 Foss Analytical A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/h7/stm32h757Xi_m4.dtsi>
+#include <st/h7/stm32h757xihx-pinctrl.dtsi>
+#include "stm32h757i_eval.dtsi"
+
+/ {
+	model = "STMicroelectronics STM32H757I EVAL board";
+	compatible = "st,stm32h757i-eval";
+
+	/* HW resources are split between CM7 and CM4 */
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+		zephyr,sram = &sram1;
+		zephyr,flash = &flash1;
+	};
+
+	leds {
+		green_led_1: led_1 {
+			status = "okay";
+		};
+
+		orange_led_2: led_2 {
+			status = "okay";
+		};
+
+		red_led_3: led_3 {
+			status = "okay";
+		};
+
+		blue_led_4: led_4 {
+			status = "okay";
+		};
+	};
+
+	gpio_keys {
+		joy_center: joystick_center {
+			status = "okay";
+		};
+	};
+
+	aliases {
+		led0 = &green_led_1;
+		led1 = &orange_led_2;
+		led2 = &red_led_3;
+		led3 = &blue_led_4;
+		sw0 = &joy_center;
+	};
+};
+
+&rcc {
+	clock-frequency = <DT_FREQ_M(200)>;
+};
+
+&usart1 {
+	status = "okay";
+};
diff --git a/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m4.yaml b/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m4.yaml
new file mode 100644
index 00000000000..c4f1095a6f0
--- /dev/null
+++ b/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m4.yaml
@@ -0,0 +1,18 @@
+identifier: stm32h757i_eval/stm32h757xx/m4
+name: ST STM32H757I Eval (M4)
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+ram: 288
+flash: 1024
+supported:
+  - gpio
+testing:
+  ignore_tags:
+    - mpu
+    - nfc
+    - net
+vendor: st
diff --git a/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m4_defconfig b/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m4_defconfig
new file mode 100644
index 00000000000..e6cb73f81b7
--- /dev/null
+++ b/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m4_defconfig
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2019 STMicroelectronics
+# Copyright (c) 2025 Foss Analytical A/S
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# By default CONSOLE is assigned to m7
+#CONFIG_CONSOLE=y
+#CONFIG_UART_CONSOLE=y
diff --git a/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m7.dts b/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m7.dts
new file mode 100644
index 00000000000..4640468048c
--- /dev/null
+++ b/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m7.dts
@@ -0,0 +1,309 @@
+/*
+ * Copyright (c) 2019 Linaro Limited
+ * Copyright (c) 2025 Foss Analytical A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/h7/stm32h757Xi_m7.dtsi>
+#include <st/h7/stm32h757xihx-pinctrl.dtsi>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#include "stm32h757i_eval.dtsi"
+
+
+/ {
+	model = "STMicroelectronics STM32H757I Eval board";
+	compatible = "st,stm32h757i-eval";
+
+	/* HW resources are split between CM7 and CM4 */
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,flash-controller = &mt25ql512ab1;
+		zephyr,code-partition = &slot0_partition;
+	};
+
+	sdram2: sdram@d0000000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		device_type = "memory";
+		reg = <0xd0000000 DT_SIZE_M(32)>;
+		zephyr,memory-region = "SDRAM2";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
+	};
+
+	ext_memory: memory@90000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
+		zephyr,memory-region = "EXTMEM";
+		/* The ATTR_MPU_EXTMEM attribut causing a MPU FAULT */
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
+	};
+
+	leds {
+		green_led_1: led_1 {
+			status = "okay";
+		};
+
+		orange_led_2: led_2 {
+			status = "okay";
+		};
+
+		red_led_3: led_3 {
+			status = "okay";
+		};
+
+		blue_led_4: led_4 {
+			status = "okay";
+		};
+	};
+
+	gpio_keys {
+		wake_up: button_1 {
+			status = "okay";
+		};
+
+		tamper: button_2 {
+			status = "okay";
+		};
+	};
+
+	otghs_ulpi_phy: otghs_ulpis_phy {
+		compatible = "usb-ulpi-phy";
+		#phy-cells = <0>;
+	};
+
+	aliases {
+		led0 = &green_led_1;
+		led1 = &orange_led_2;
+		led2 = &red_led_3;
+		led3 = &blue_led_4;
+		sw0 = &tamper;
+	};
+};
+
+&clk_hse {
+	clock-frequency = <DT_FREQ_M(25)>;
+	status = "okay";
+};
+
+&clk_hsi48 {
+	status = "okay";
+};
+
+&pll {
+	div-m = <5>;
+	mul-n = <160>;
+	div-p = <2>;
+	div-q = <4>;
+	div-r = <2>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&pll2 {
+	div-m = <5>;
+	mul-n = <96>;
+	div-p = <2>;
+	div-q = <4>;
+	div-r = <10>;
+	clocks = <&clk_hse>;  /* Assuming 25MHz HSE */
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(400)>;
+};
+
+&usart1 {
+	status = "okay";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 DT_SIZE_K(128)>;
+		};
+
+		slot0_partition: partition@20000 {
+			label = "image-0";
+			reg = <0x00020000 DT_SIZE_K(896)>;
+		};
+
+		slot1_partition: partition@100000 {
+			label = "image-1";
+			reg = <0x00100000 DT_SIZE_K(896)>;
+		};
+
+		storage_partition: partition@1e0000 {
+			label = "storage";
+			reg = <0x001e0000 DT_SIZE_K(128)>;
+		};
+	};
+};
+
+&mac {
+	status = "okay";
+	pinctrl-0 = <&eth_ref_clk_pa1
+		     &eth_crs_dv_pa7
+		     &eth_rxd0_pc4
+		     &eth_rxd1_pc5
+		     &eth_tx_en_pg11
+		     &eth_txd0_pg13
+		     &eth_txd1_pg12>;
+	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
+	pinctrl-names = "default";
+
+	eth_phy: ethernet-phy@0 {
+		compatible = "ethernet-phy";
+		reg = <0x00>;
+	};
+};
+
+&rng {
+	status = "okay";
+};
+
+&fmc {
+	status = "okay";
+	pinctrl-0 = <&fmc_nbl0_pe0 &fmc_nbl1_pe1 &fmc_nbl2_pi4 &fmc_nbl3_pi5
+		     &fmc_sdclk_pg8 &fmc_sdnwe_ph5 &fmc_sdcke1_ph7
+		     &fmc_sdne1_ph6 &fmc_sdnras_pf11 &fmc_sdncas_pg15
+		     &fmc_a0_pf0 &fmc_a1_pf1 &fmc_a2_pf2 &fmc_a3_pf3 &fmc_a4_pf4
+		     &fmc_a5_pf5 &fmc_a6_pf12 &fmc_a7_pf13 &fmc_a8_pf14
+		     &fmc_a9_pf15 &fmc_a10_pg0 &fmc_a11_pg1 &fmc_a12_pg2
+		     &fmc_a14_pg4 &fmc_a15_pg5 &fmc_d0_pd14 &fmc_d1_pd15
+		     &fmc_d2_pd0 &fmc_d3_pd1 &fmc_d4_pe7 &fmc_d5_pe8 &fmc_d6_pe9
+		     &fmc_d7_pe10 &fmc_d8_pe11 &fmc_d9_pe12 &fmc_d10_pe13
+		     &fmc_d11_pe14 &fmc_d12_pe15 &fmc_d13_pd8 &fmc_d14_pd9
+		     &fmc_d15_pd10 &fmc_d16_ph8 &fmc_d17_ph9 &fmc_d18_ph10
+		     &fmc_d19_ph11 &fmc_d20_ph12 &fmc_d21_ph13 &fmc_d22_ph14
+		     &fmc_d23_ph15 &fmc_d24_pi0 &fmc_d25_pi1 &fmc_d26_pi2
+		     &fmc_d27_pi3 &fmc_d28_pi6 &fmc_d29_pi7 &fmc_d30_pi9
+		     &fmc_d31_pi10>;
+	pinctrl-names = "default";
+
+	sdram {
+		status = "okay";
+
+		power-up-delay = <100>;
+		num-auto-refresh = <8>;
+		mode-register = <0x220>;
+		refresh-rate = <603>;
+
+		bank@1 {
+			reg = <1>;
+
+			st,sdram-control = <STM32_FMC_SDRAM_NC_9
+					    STM32_FMC_SDRAM_NR_12
+					    STM32_FMC_SDRAM_MWID_32
+					    STM32_FMC_SDRAM_NB_4
+					    STM32_FMC_SDRAM_CAS_2
+					    STM32_FMC_SDRAM_SDCLK_PERIOD_2
+					    STM32_FMC_SDRAM_RBURST_ENABLE
+					    STM32_FMC_SDRAM_RPIPE_0>;
+			st,sdram-timing = <2 6 4 6 2 2 2>;
+		};
+	};
+};
+
+zephyr_udc0: &usbotg_hs {
+	pinctrl-0 = <&usb_otg_hs_ulpi_ck_pa5
+			&usb_otg_hs_ulpi_d0_pa3
+			&usb_otg_hs_ulpi_d1_pb0
+			&usb_otg_hs_ulpi_d2_pb1
+			&usb_otg_hs_ulpi_d3_pb10
+			&usb_otg_hs_ulpi_d4_pb11
+			&usb_otg_hs_ulpi_d5_pb12
+			&usb_otg_hs_ulpi_d6_pb13
+			&usb_otg_hs_ulpi_d7_pb5
+			&usb_otg_hs_ulpi_stp_pc0
+			&usb_otg_hs_ulpi_dir_pi11
+			&usb_otg_hs_ulpi_nxt_ph4>;
+	pinctrl-names = "default";
+	maximum-speed = "high-speed";
+	/* Include the USB1ULPIEN clock enable bit */
+	clocks = <&rcc STM32_CLOCK_BUS_AHB1 0x06000000>,
+		 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
+	phys = <&otghs_ulpi_phy>;
+	status = "okay";
+};
+
+&sdmmc1 {
+	status = "okay";
+	clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00010000>,
+			<&rcc STM32_SRC_PLL2_R SDMMC_SEL(1)>;
+	pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
+			&sdmmc1_d2_pc10 &sdmmc1_d3_pc11
+			&sdmmc1_d4_pb8 &sdmmc1_d5_pb9
+			&sdmmc1_d6_pc6 &sdmmc1_d7_pc7
+			&sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
+	pinctrl-names = "default";
+	cd-gpios = <&gpioi 8 GPIO_ACTIVE_LOW>;
+};
+
+&quadspi {
+	pinctrl-0 = <&quadspi_clk_pb2 &quadspi_bk1_ncs_pg6
+		     &quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pf9
+		     &quadspi_bk1_io2_pf7 &quadspi_bk1_io3_pf6
+		     &quadspi_bk2_io0_ph2 &quadspi_bk2_io1_ph3
+		     &quadspi_bk2_io2_pg9 &quadspi_bk2_io3_pg14>;
+	pinctrl-names = "default";
+	dual-flash;
+	status = "okay";
+
+	mt25ql512ab1: qspi-nor-flash-1@90000000 {
+		compatible = "st,stm32-qspi-nor";
+		reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
+		qspi-max-frequency = <72000000>;
+		spi-bus-width = <4>;
+		reset-cmd;
+		status = "okay";
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			partition@0 {
+				reg = <0x0 DT_SIZE_M(64)>;
+			};
+		};
+	};
+
+	mt25ql512ab2: qspi-nor-flash-2@90000000 {
+		compatible = "st,stm32-qspi-nor";
+		reg = <0x90000000 DT_SIZE_M(64)>; /* 512 Mbits */
+		qspi-max-frequency = <72000000>;
+		status = "okay";
+	};
+};
+
+/* alias used by display shields with touch control */
+qsh_030_i2c: &i2c4 {
+	pinctrl-0 = <&i2c4_scl_pd12 &i2c4_sda_pd13>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_FAST>;
+	status = "okay";
+};
+
+/* alias used by display shields */
+zephyr_mipi_dsi: &mipi_dsi {};
+
+/* alias used by LCD display shields */
+zephyr_lcd_controller: &ltdc {};
diff --git a/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m7.yaml b/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m7.yaml
new file mode 100644
index 00000000000..956e5dc0c4f
--- /dev/null
+++ b/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m7.yaml
@@ -0,0 +1,18 @@
+identifier: stm32h757i_eval/stm32h757xx/m7
+name: ST STM32H757I Eval (M7)
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+ram: 2048
+flash: 1024
+supported:
+  - gpio
+  - spi
+  - netif:eth
+  - qspi
+  - memc
+  - usb_device
+vendor: st
diff --git a/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m7_defconfig b/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m7_defconfig
new file mode 100644
index 00000000000..f5ea7cc6213
--- /dev/null
+++ b/boards/st/stm32h757i_eval/stm32h757i_eval_stm32h757xx_m7_defconfig
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2019 STMicroelectronics
+# Copyright (c) 2025 Foss Analytical A/S
+
+# Enable the internal SMPS regulator
+CONFIG_POWER_SUPPLY_DIRECT_SMPS=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Disable following to assign serial ports to m4 core
+
+# Enable uart driver
+CONFIG_SERIAL=y
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/st/stm32h757i_eval/support/openocd_stm32h757i_eval_m4.cfg b/boards/st/stm32h757i_eval/support/openocd_stm32h757i_eval_m4.cfg
new file mode 100644
index 00000000000..9958067dfb3
--- /dev/null
+++ b/boards/st/stm32h757i_eval/support/openocd_stm32h757i_eval_m4.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2025 Foss Analytical A/S
+
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+set DUAL_BANK 1
+
+set DUAL_CORE 1
+
+source [find target/stm32h7x.cfg]
+
+reset_config srst_only srst_nogate connect_assert_srst
diff --git a/boards/st/stm32h757i_eval/support/openocd_stm32h757i_eval_m7.cfg b/boards/st/stm32h757i_eval/support/openocd_stm32h757i_eval_m7.cfg
new file mode 100644
index 00000000000..172b4eb7851
--- /dev/null
+++ b/boards/st/stm32h757i_eval/support/openocd_stm32h757i_eval_m7.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2025 Foss Analytical A/S
+
+source [find interface/stlink.cfg]
+
+transport select hla_swd
+
+source [find target/stm32h7x.cfg]
+
+# Use connect_assert_srst here to be able to program
+# even when core is in sleep mode
+reset_config srst_only srst_nogate connect_assert_srst
+
+$_CHIPNAME.cpu0 configure -event gdb-attach {
+        echo "Debugger attaching: halting execution"
+        gdb_breakpoint_override hard
+}
+
+$_CHIPNAME.cpu0 configure -event gdb-detach {
+        echo "Debugger detaching: resuming execution"
+        resume
+}
+
+# Due to the use of connect_assert_srst, running gdb requires
+# to reset halt just after openocd init.
+rename init old_init
+proc init {} {
+        old_init
+        reset halt
+}
diff --git a/boards/st/stm32h7b3i_dk/Kconfig.defconfig b/boards/st/stm32h7b3i_dk/Kconfig.defconfig
index 37932189b7c..766cff03a3e 100644
--- a/boards/st/stm32h7b3i_dk/Kconfig.defconfig
+++ b/boards/st/stm32h7b3i_dk/Kconfig.defconfig
@@ -9,9 +9,6 @@ if BOARD_STM32H7B3I_DK
 config INPUT
 	default y if LVGL
 
-config INPUT_FT5336_INTERRUPT
-	default y if INPUT_FT5336
-
 # MEMC needs to be enabled in order to store
 # display buffer to external SDRAM connected to FMC
 config MEMC
@@ -25,9 +22,6 @@ config CACHE_MANAGEMENT
 config LV_USE_DRAW_DMA2D
 	default y
 
-config LV_DRAW_DMA2D_HAL_INCLUDE
-	default "stm32h7xx.h"
-
 config STM32_LTDC_FB_NUM
 	default 2
 
diff --git a/boards/st/stm32h7b3i_dk/doc/index.rst b/boards/st/stm32h7b3i_dk/doc/index.rst
index e5ad38f4c2b..13fb0eeea67 100644
--- a/boards/st/stm32h7b3i_dk/doc/index.rst
+++ b/boards/st/stm32h7b3i_dk/doc/index.rst
@@ -94,42 +94,7 @@ More information about STM32H7B3 can be found here:
 Supported Features
 ==================
 
-The current Zephyr stm32h7b3i_dk board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SDMMC     | on-chip    | disk access                         |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| OSPI NOR  | on-chip    | off-chip flash                      |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| FMC       | on-chip    | memc (SDRAM)                        |
-+-----------+------------+-------------------------------------+
-| LTDC      | on-chip    | display                             |
-+-----------+------------+-------------------------------------+
-| CANFD     | on-chip    | can                                 |
-+-----------+------------+-------------------------------------+
-
-
-Other hardware features have not been enabled yet for this board.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/stm32h7b3i_dk/stm32h7b3i_dk_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -189,6 +154,8 @@ default communication settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32H7B3I Discovery kit includes an STLINK-V3E embedded debug tool interface.
 
 Applications for the ``stm32h7b3i_dk`` board configuration can be built and
diff --git a/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts
index 7e4fe7f9c2d..c76f7b7f238 100644
--- a/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts
+++ b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.dts
@@ -75,6 +75,28 @@
 		#phy-cells = <0>;
 	};
 
+	dmci_camera_connector: connector_dcmi_camera {
+		compatible = "st,stm32-dcmi-camera-fpu-330zh";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <3  0 &gpiod 12  0>,  /* I2C4_SCL */
+			   <4  0 &gpiod 13  0>,  /* I2C4_SDA */
+			   <5  0 &gpioa  0  0>,  /* RESET# */
+			   <6  0 &gpioa  7  0>,  /* PWDN_EN */
+			   <12 0 &gpiob  7  0>,  /* DCMI_VSYNC */
+			   <14 0 &gpioa  4  0>,  /* DCMI_HSYNC */
+			   <16 0 &gpioa  6  0>,  /* DCMI_PIXCK */
+			   <20 0 &gpiob  9  0>,  /* DCMI_D7 */
+			   <21 0 &gpiob  8  0>,  /* DCMI_D6 */
+			   <22 0 &gpiod  3  0>,  /* DCMI_D5 */
+			   <23 0 &gpioc 11  0>,  /* DCMI_D4 */
+			   <24 0 &gpioc  9  0>,  /* DCMI_D3 */
+			   <25 0 &gpiog 10  0>,  /* DCMI_D2 */
+			   <26 0 &gpioc  7  0>,  /* DCMI_D1 */
+			   <27 0 &gpioc  6  0>;  /* DCMI_D0 */
+	};
+
 	aliases {
 		led0 = &blue_led;
 		led1 = &red_led;
@@ -147,7 +169,7 @@
 	ft5336: ft5336@38 {
 		compatible = "focaltech,ft5336";
 		reg = <0x38>;
-		int-gpios = <&gpioh 2 0>;
+		int-gpios = <&gpioh 2 GPIO_ACTIVE_LOW>;
 	};
 };
 
@@ -278,3 +300,7 @@
 		};
 	};
 };
+
+st_cam_i2c: &i2c4 {};
+
+st_cam_dvp: &dcmi {};
diff --git a/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.yaml b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.yaml
index 3779381d564..3c0cf307770 100644
--- a/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.yaml
+++ b/boards/st/stm32h7b3i_dk/stm32h7b3i_dk.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 1376
 flash: 2048
 supported:
diff --git a/boards/st/stm32h7s78_dk/doc/index.rst b/boards/st/stm32h7s78_dk/doc/index.rst
index 430b3d9dd0e..ae69379abdd 100644
--- a/boards/st/stm32h7s78_dk/doc/index.rst
+++ b/boards/st/stm32h7s78_dk/doc/index.rst
@@ -147,40 +147,7 @@ More information about STM32H7S7 can be found here:
 Supported Features
 ==================
 
-The Zephyr STM32H7S78_DK board configuration supports the following
-hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi bus                             |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig and dts files:
-
-- Secure target:
-
-  - :zephyr_file:`boards/st/stm32h7s78_dk/stm32h7s78_dk_defconfig`
-  - :zephyr_file:`boards/st/stm32h7s78_dk/stm32h7s78_dk.dts`
+.. zephyr:board-supported-hw::
 
 Zephyr board options
 ====================
@@ -215,6 +182,7 @@ Default Zephyr Peripheral Mapping:
 - LD3 (red) : PM2
 - LD4 (blue) : PM3
 - ADC1 channel 6 input : PF12
+- USB OTG FS DM/DP : PM12/PM11
 
 System Clock
 ------------
@@ -229,10 +197,17 @@ Serial Port
 STM32H7S78-DK Discovery board has 2 U(S)ARTs. The Zephyr console output is
 assigned to USART4. Default settings are 115200 8N1.
 
+USB
+---
+
+STM32H7S78-DK Discovery board has 2 USB Type-C connectors. Currently, only
+USB port2 (FS) is supported.
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32H7S78-DK Discovery board includes an ST-LINK/V3E embedded debug tool interface.
 
 Applications for the ``stm32h7s78_dk`` board configuration can be built and
diff --git a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts
index e4192d41641..5cfbbb449b8 100644
--- a/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts
+++ b/boards/st/stm32h7s78_dk/stm32h7s78_dk.dts
@@ -184,3 +184,11 @@
 &vbat {
 	status = "okay";
 };
+
+usb2: &usbotg_fs {
+	pinctrl-0 = <&usb_otg_fs_dm_pm12 &usb_otg_fs_dp_pm11>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+zephyr_udc0: &usb2 {};
diff --git a/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml b/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml
index e48895cbce1..7e14a410259 100644
--- a/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml
+++ b/boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml
@@ -13,4 +13,6 @@ supported:
   - watchdog
   - entropy
   - adc
+  - usb_device
+  - usbd
 vendor: st
diff --git a/boards/st/stm32l1_disco/doc/index.rst b/boards/st/stm32l1_disco/doc/index.rst
index 6954625564b..621e1611898 100644
--- a/boards/st/stm32l1_disco/doc/index.rst
+++ b/boards/st/stm32l1_disco/doc/index.rst
@@ -47,54 +47,7 @@ More information about STM32L151x can be found in the `STM32L1x reference manual
 Supported Features
 ==================
 
-The Zephyr stm32l1_disco and stm32l152c_disco board configurations support
-the following hardware features:
-
-.. list-table:: Supported hardware
-   :header-rows: 1
-
-   * - Interface
-     - Controller
-     - Driver/component
-   * - NVIC
-     - on-chip
-     - nested vector interrupt controller
-   * - UART
-     - on-chip
-     - serial port-polling
-       serial port-interrupt
-   * - PINMUX
-     - on-chip
-     - pinmux
-   * - GPIO
-     - on-chip
-     - gpio
-   * - CLOCK
-     - on-chip
-     - reset and clock control
-   * - FLASH
-     - on-chip
-     - flash memory
-   * - EEPROM
-     - on-chip
-     - eeprom
-   * - WATCHDOG
-     - on-chip
-     - window watchdog
-   * - I2C
-     - on-chip
-     - i2c
-   * - SPI
-     - on-chip
-     - spi
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The configuration of stm32l1_disco can be found in
-:zephyr_file:`boards/st/stm32l1_disco/stm32l1_disco_defconfig`
-
-Configuration of stm32l152c_disco can be found in
-:zephyr_file:`boards/st/stm32l1_disco/stm32l152c_disco_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -131,6 +84,8 @@ For more details please refer to `STM32L1DISCOVERY board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32L1DISCOVERY and STM32L152CDISCOVERY boards include an ST-LINK/V2 embedded debug tool interface.
 
 Applications for the ``stm32l1_disco`` board configuration can be built and
diff --git a/boards/st/stm32l1_disco/stm32l152c_disco.yaml b/boards/st/stm32l1_disco/stm32l152c_disco.yaml
index 9ada265eed0..738f23ea4bd 100644
--- a/boards/st/stm32l1_disco/stm32l152c_disco.yaml
+++ b/boards/st/stm32l1_disco/stm32l152c_disco.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
 flash: 256
 supported:
diff --git a/boards/st/stm32l1_disco/stm32l1_disco.yaml b/boards/st/stm32l1_disco/stm32l1_disco.yaml
index ac536ecacbb..b5d4711295d 100644
--- a/boards/st/stm32l1_disco/stm32l1_disco.yaml
+++ b/boards/st/stm32l1_disco/stm32l1_disco.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 16
 flash: 128
 supported:
diff --git a/boards/st/stm32l476g_disco/doc/index.rst b/boards/st/stm32l476g_disco/doc/index.rst
index 00c7fdc45d4..868590f7033 100644
--- a/boards/st/stm32l476g_disco/doc/index.rst
+++ b/boards/st/stm32l476g_disco/doc/index.rst
@@ -100,27 +100,7 @@ More information about STM32L476VG can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32l476g_disco board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-
-	:zephyr_file:`boards/st/stm32l476g_disco/stm32l476g_disco_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -155,6 +135,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32L476G Discovery board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Flashing
diff --git a/boards/st/stm32l476g_disco/stm32l476g_disco.yaml b/boards/st/stm32l476g_disco/stm32l476g_disco.yaml
index 671e1738519..49f5036c9c7 100644
--- a/boards/st/stm32l476g_disco/stm32l476g_disco.yaml
+++ b/boards/st/stm32l476g_disco/stm32l476g_disco.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 96
 flash: 1024
 supported:
diff --git a/boards/st/stm32l496g_disco/doc/index.rst b/boards/st/stm32l496g_disco/doc/index.rst
index ce91d694043..09b7207953b 100644
--- a/boards/st/stm32l496g_disco/doc/index.rst
+++ b/boards/st/stm32l496g_disco/doc/index.rst
@@ -115,41 +115,7 @@ More information about STM32L496AG can be found in:
 Supported Features
 ==================
 
-The Zephyr stm32l496g_disco board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SDMMC     | on-chip    | disk access                         |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| QSPI NOR  | on-chip    | off-chip flash                      |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb_device                          |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-
-	:zephyr_file:`boards/st/stm32l496g_disco/stm32l496g_disco_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -191,6 +157,8 @@ Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32L496G Discovery board includes an ST-LINK/V2-1 embedded debug tool interface.
 
 Flashing
diff --git a/boards/st/stm32l496g_disco/stm32l496g_disco.dts b/boards/st/stm32l496g_disco/stm32l496g_disco.dts
index 9027656636a..4a942a5ab06 100644
--- a/boards/st/stm32l496g_disco/stm32l496g_disco.dts
+++ b/boards/st/stm32l496g_disco/stm32l496g_disco.dts
@@ -194,7 +194,7 @@ zephyr_udc0: &usbotg_fs {
 			&quadspi_bk1_ncs_pb11 &quadspi_clk_pa3>;
 	pinctrl-names = "default";
 
-	dmas = <&dma2 7 3 0x480>; /* channel 7 request 3 on DMA2 */
+	dmas = <&dma2 7 3 STM32_DMA_PERIPH_RX>; /* channel 7 request 3 on DMA2 */
 	dma-names = "tx_rx";
 
 	flash-id = <1>;
diff --git a/boards/st/stm32l496g_disco/stm32l496g_disco.yaml b/boards/st/stm32l496g_disco/stm32l496g_disco.yaml
index e6b153cb0e4..70656aa4da2 100644
--- a/boards/st/stm32l496g_disco/stm32l496g_disco.yaml
+++ b/boards/st/stm32l496g_disco/stm32l496g_disco.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 256
 flash: 1024
 supported:
diff --git a/boards/st/stm32l4r9i_disco/doc/index.rst b/boards/st/stm32l4r9i_disco/doc/index.rst
index 0b5b992c059..f6a7417e0b7 100644
--- a/boards/st/stm32l4r9i_disco/doc/index.rst
+++ b/boards/st/stm32l4r9i_disco/doc/index.rst
@@ -25,41 +25,7 @@ More information about STM32L4R9 can be found here:
 Supported Features
 ==================
 
-The current Zephyr stm32l4r9i_disco board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling                 |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | on-chip flash memory;               |
-|           |            | external OctoSPI memory             |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | Real Time Clock                     |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| SDMMC     | on-chip    | sd/mmc                              |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in the defconfig file:
-
-	:zephyr_file:`boards/st/stm32l4r9i_disco/stm32l4r9i_disco_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -84,6 +50,8 @@ ST-LINK Virtual COM port interface. Default communication settings are 115200 8N
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The STM32L4R9I Discovery board includes an ST-LINK/V2-1 debug tool.
 
 Applications for the ``stm32l4r9i_disco`` board configuration can be
diff --git a/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts
index 27cfdb2f0a7..2e6175dd171 100644
--- a/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts
+++ b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.dts
@@ -22,7 +22,10 @@
 
 	leds {
 		compatible = "gpio-leds";
-		/* N.B. LD1 (orange) is not wired to MCU */
+		orange_led: led_1 {
+			gpios = <&mfx 0 GPIO_ACTIVE_LOW>;
+			label = "User LD1";
+		};
 		green_led: led_2 {
 			gpios = <&gpioh 4 GPIO_ACTIVE_LOW>;
 			label = "User LD2";
@@ -36,11 +39,36 @@
 			gpios = <&gpioc 13 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
 			zephyr,code = <INPUT_KEY_ENTER>;
 		};
+		joy_up: joystick_up {
+			label = "joystick up";
+			gpios = <&mfx 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_UP>;
+		};
+		joy_down: joystick_down {
+			label = "joystick down";
+			gpios = <&mfx 2 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_DOWN>;
+		};
+		joy_right: joystick_right {
+			label = "joystick right";
+			gpios = <&mfx 3 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_RIGHT>;
+		};
+		joy_left: joystick_left {
+			label = "joystick left";
+			gpios = <&mfx 4 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_LEFT>;
+		};
 	};
 
 	aliases {
 		led0 = &green_led;
+		led1 = &orange_led;
 		sw0 = &joy_sel;
+		sw1 = &joy_up;
+		sw2 = &joy_down;
+		sw3 = &joy_right;
+		sw4 = &joy_left;
 		die-temp0 = &die_temp;
 		volt-sensor0 = &vref;
 		volt-sensor1 = &vbat;
@@ -155,6 +183,15 @@
 	pinctrl-0 = <&i2c1_scl_pb6 &i2c1_sda_pg13>;
 	pinctrl-names = "default";
 	clock-frequency = <I2C_BITRATE_STANDARD>;
+
+	mfx: gpio@42 {
+		compatible = "st,mfxstm32l152";
+		reg = <0x42>;
+		ngpios = <24>;
+		int-gpios = <&gpioi 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>;
+		gpio-controller;
+		#gpio-cells = <2>;
+	};
 };
 
 &i2c3 {
diff --git a/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.yaml b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.yaml
index 3b4ef674d84..8f8b558ed9f 100644
--- a/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.yaml
+++ b/boards/st/stm32l4r9i_disco/stm32l4r9i_disco.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 192
 flash: 2048
 vendor: st
diff --git a/boards/st/stm32l562e_dk/board.cmake b/boards/st/stm32l562e_dk/board.cmake
index 15e7afc15c0..e3f5f878df2 100644
--- a/boards/st/stm32l562e_dk/board.cmake
+++ b/boards/st/stm32l562e_dk/board.cmake
@@ -15,8 +15,10 @@ endif()
 # keep first
 board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw")
 board_runner_args(pyocd "--target=stm32l562qeixq")
+board_runner_args(jlink "--device=STM32L562QE" "--speed=4000")
 
 # keep first
 include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/pyocd.board.cmake)
 include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/st/stm32l562e_dk/doc/index.rst b/boards/st/stm32l562e_dk/doc/index.rst
index 4e159971936..8abda84af04 100644
--- a/boards/st/stm32l562e_dk/doc/index.rst
+++ b/boards/st/stm32l562e_dk/doc/index.rst
@@ -139,68 +139,8 @@ More information about STM32L562QE can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32l562e_dk board configuration supports the following
-hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| ADC       | on-chip    | ADC Controller                      |
-+-----------+------------+-------------------------------------+
-| AES       | on-chip    | crypto                              |
-+-----------+------------+-------------------------------------+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | DAC Controller                      |
-+-----------+------------+-------------------------------------+
-| DISPLAY   | on-chip    | TFT LCD screen with st7789v driver  |
-|           |            | and touch panel with ft5336 driver  |
-+-----------+------------+-------------------------------------+
-| DMA       | on-chip    | Direct Memory Access                |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | PWM                                 |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | entropy                             |
-+-----------+------------+-------------------------------------+
-| SDMMC     | on-chip    | sd/mmc                              |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| TrustZone | on-chip    | Trusted Firmware-M                  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig and dts files:
-
-- Common:
-
-  - :zephyr_file:`boards/st/stm32l562e_dk/stm32l562e_dk_common.dtsi`
-
-- Secure target:
-
-  - :zephyr_file:`boards/st/stm32l562e_dk/stm32l562e_dk_defconfig`
-  - :zephyr_file:`boards/st/stm32l562e_dk/stm32l562e_dk.dts`
-
-- Non-Secure target:
-
-  - :zephyr_file:`boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns_defconfig`
-  - :zephyr_file:`boards/st/stm32l562e_dk/stm32l562e_dk_stm32l562xx_ns.dts`
+.. zephyr:board-supported-hw::
+
 
 Zephyr board options
 ====================
@@ -290,6 +230,8 @@ They can be tested using :zephyr:code-sample:`lvgl` sample:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32L562E-DK Discovery board includes an ST-LINK/V3E embedded debug tool interface.
 
 Applications for the ``stm32l562e_dk`` board configuration can be built and
diff --git a/boards/st/stm32mp135f_dk/Kconfig.stm32mp135f_dk b/boards/st/stm32mp135f_dk/Kconfig.stm32mp135f_dk
new file mode 100644
index 00000000000..c648af34bc3
--- /dev/null
+++ b/boards/st/stm32mp135f_dk/Kconfig.stm32mp135f_dk
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_STM32MP135F_DK
+	select SOC_STM32MP135FXX
diff --git a/boards/st/stm32mp135f_dk/board.cmake b/boards/st/stm32mp135f_dk/board.cmake
new file mode 100644
index 00000000000..af21b180317
--- /dev/null
+++ b/boards/st/stm32mp135f_dk/board.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+
+board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd.cfg")
diff --git a/boards/st/stm32mp135f_dk/board.yml b/boards/st/stm32mp135f_dk/board.yml
new file mode 100644
index 00000000000..2e3886965ba
--- /dev/null
+++ b/boards/st/stm32mp135f_dk/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: stm32mp135f_dk
+  full_name: STM32MP135F-DK Discovery
+  vendor: st
+  socs:
+    - name: stm32mp135fxx
diff --git a/boards/st/stm32mp135f_dk/doc/img/stm32mp135f_dk.webp b/boards/st/stm32mp135f_dk/doc/img/stm32mp135f_dk.webp
new file mode 100644
index 00000000000..d4e5a32a261
Binary files /dev/null and b/boards/st/stm32mp135f_dk/doc/img/stm32mp135f_dk.webp differ
diff --git a/boards/st/stm32mp135f_dk/doc/index.rst b/boards/st/stm32mp135f_dk/doc/index.rst
new file mode 100644
index 00000000000..d56cb0c4c12
--- /dev/null
+++ b/boards/st/stm32mp135f_dk/doc/index.rst
@@ -0,0 +1,205 @@
+.. zephyr:board:: stm32mp135f_dk
+
+Overview
+********
+The STM32MP135 Discovery kit (STM32MP135F-DK) leverages the capabilities of the
+1 GHz STM32MP135 microprocessors to allow users to develop applications easily with Zephyr RTOS.
+
+It includes an ST-LINK embedded debug tool, LEDs, push-buttons, two 10/100 Mbit/s Ethernet (RMII) connectors, one USB Type-C |reg| connector, four USB Host Type-A connectors, and one microSD™ connector.
+
+To expand the functionality of the STM32MP135 Discovery kit, one GPIO expansion connector is also available for third-party shields.
+
+Additionally, the STM32MP135 Discovery kit features an LCD display with a touch panel, Wi‑Fi |reg| and Bluetooth |reg| Low Energy capability, and a 2-megapixel CMOS camera module.
+
+It also provides secure boot and cryptography features.
+
+Zephyr OS is ported to run on the Cortex |reg|-A7 core.
+
+- STM32MP135FAF7: Arm |reg| Cortex |reg|-A7 32-bit processor at 1 GHz, in a TFBGA320 package
+- ST PMIC STPMIC1
+- 4-Gbit DDR3L, 16 bits, 533 MHz
+- 4.3" 480x272 pixels LCD display module with capacitive touch panel and RGB interface
+- UXGA 2-megapixel CMOS camera module (included) with MIPI CSI-2 |reg| / SMIA CCP2 deserializer
+- Wi-Fi |reg| 802.11b/g/n
+- Bluetooth |reg| Low Energy 4.1
+- Dual 10/100 Mbit/s Ethernet (RMII) compliant with IEEE-802.3u, one with Wake on LAN (WoL) support
+- USB Host 4-port hub
+- USB Type-C |reg| DRP based on an STM32G0 device
+- 4 user LEDs
+- 4 push-buttons (2× user, tamper, and reset)
+- 1 wake-up button
+- Board connectors:
+
+  - Dual-lane MIPI CSI-2 |reg| camera module expansion
+  - 2x Ethernet RJ45
+  - 4x USB Type-A
+  - USB Micro-B
+  - USB Type-C |reg|
+  - microSD™ card holder
+  - GPIO expansion
+  - 5 V / 3 A USB Type-C |reg| power supply input (charger not provided)
+  - VBAT for power backup
+
+- On-board current measurement
+- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability:
+
+  - mass storage
+  - Virtual COM port
+  - debug port
+
+More information about the board can be found at the
+`STM32P135 Discovery website`_.
+
+Hardware
+********
+
+More information about the STM32MP135F_DK board hardware can be found here:
+
+- `STM32MP135F_DK Hardware Description`_
+
+More information about STM32P135F microprocessor can be found here:
+
+- `STM32MP135F on www.st.com`_
+- `STM32MP135F reference manual`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+STM32MP135F-DK Discovery Board schematic is available here:
+`STM32MP135F Discovery board schematics`_.
+
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+- USART_4 TX/RX : PD6/PD8 (UART console)
+
+- USER_BUTTON : PA13
+- LED_3 : PA14
+- LED_4 : PA13
+
+System Clock
+------------
+
+The Cortex |reg|-A7 core is configured to run at a clock speed of up to 1GHz.
+
+Memory mapping
+--------------
+
++------------+-----------------------+----------------+
+| Region     |        Address        |     Size       |
++============+=======================+================+
+| SYSRAM     | 0x2FFE0000-0x2FFFFFFF | 128KB          |
++------------+-----------------------+----------------+
+| SRAM 1     | 0x30000000-0x30003FFF |  16KB          |
++------------+-----------------------+----------------+
+| SRAM 2     | 0x30004000-0x30005FFF |   8KB          |
++------------+-----------------------+----------------+
+| SRAM 3     | 0x30006000-0x30007FFF |   8KB          |
++------------+-----------------------+----------------+
+| DDR        | 0xC0000000-0xDFFFFFFF |   512 MB       |
++------------+-----------------------+----------------+
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Prerequisite
+============
+
+The STM32MP135 has a DDR controller that need to be initialized before loading the Zephyr example.
+
+One method to perform this is to flash the Zephyr executable, along with the DDR initialization script, on an SD card inserted in the board. To do so, you first need to :ref:`install STM32CubeProgrammer <stm32cubeprog-flash-host-tools>` and download the `STM32CubeMP13 package`_.
+
+Signature and flashing
+======================
+
+After building the Zephyr project, you need to sign your binary file using the Stm32ImageAddHeader.py with the following command:
+
+.. code-block:: console
+
+   python3 ${Path_to_STM32CubeMP13}/Utilities/ImageHeader/Python3/Stm32ImageAddHeader.py ${Path_to_build_dir}/zephyr/zephyr.bin ${STM32CubeMP13}/Projects/STM32MP135C-DK/External_Loader/Prebuild_Binaries/SD_Ext_Loader/zephyr_Signed.bin -bt 10 -la C0000000 -ep C0000000
+
+Here -bt specifies the boot type, -la specifies the load address and -ep the entry point for your executable (same as the load address in this case).
+
+Then, copy :zephyr_file:`boards/st/stm32mp135f_dk/support/Zephyr.tsv` to ``${Path_to_STM32CubeMP13}/Projects/STM32MP135C-DK/External_Loader/Prebuild_Binaries/SD_Ext_Loader/``.
+
+Finally using the Cube Programmer select the Zephyr.tsv and flash the SD card with the following command:
+
+.. code-block:: console
+
+   ${Path_to_STM32cube_Programmer}/bin/STM32_Programmer.sh -c port=${ConnectedPort} p=even br=115200 -d ${Path_to_STM32CubeMP13}/Projects/STM32MP135C-DK/External_Loader/Prebuild_Binaries/SD_Ext_Loader/Zephyr.tsv
+
+.. note::
+  You can refer to this example to flash an example to the SD card:
+  `How to install STM32Cube software package on microSD card`_
+
+Debugging
+=========
+
+You can debug an application using OpenOCD and GDB.
+
+- Build the sample:
+
+  .. zephyr-app-commands::
+     :zephyr-app: samples/hello_world
+     :board: stm32mp135f_dk
+     :goals: build
+
+- Flash the SD card using:
+  `How to install STM32Cube software package on microSD card`_
+
+- Run the application from the SD card
+
+- Attach to the target:
+
+  .. code-block:: console
+
+      west attach
+
+.. note::
+  The ``run`` command of GDB isn't supported at the moment for this board.
+
+References
+**********
+
+.. target-notes::
+
+.. _STM32P135 Discovery website:
+   https://www.st.com/en/evaluation-tools/stm32mp135f-dk.html
+
+.. _STM32MP135F Discovery board User Manual:
+   https://www.st.com/resource/en/user_manual/dm00862450.pdf
+
+.. _STM32MP135F Discovery board schematics:
+   https://www.st.com/resource/en/schematic_pack/mb1635-mp135f-e02-schematic.pdf
+
+.. _STM32MP135F on www.st.com:
+   https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-arm-cortex-mpus/stm32mp1-series/stm32mp135/stm32mp135f.html
+
+.. _STM32MP135F reference manual:
+   https://www.st.com/resource/en/reference_manual/DM00670465-.pdf
+
+.. _STM32MP135 STM32Cube software package:
+   https://www.st.com/en/embedded-software/stm32cubemp13.html#get-software
+
+.. _How to install STM32Cube software package on microSD card:
+   https://wiki.st.com/stm32mpu/wiki/How_to_load_and_start_STM32CubeMP13_applications_via_microSD_card
+
+.. _STM32MP135F boot architecture:
+   https://wiki.st.com/stm32mpu/wiki/STM32CubeMP13_package_-_boot_architecture
+
+.. _STM32MP135F baremetal distribution:
+   https://wiki.st.com/stm32mpu/wiki/Category:Bare_metal_-_RTOS_embedded_software
+
+.. _STM32CubeMP13 package:
+   https://github.com/STMicroelectronics/STM32CubeMP13
+
+.. _STM32MP135F_DK Hardware Description:
+   https://wiki.stmicroelectronics.cn/stm32mpu/wiki/STM32MP135x-DK_-_hardware_description
diff --git a/boards/st/stm32mp135f_dk/stm32mp135f_dk.dts b/boards/st/stm32mp135f_dk/stm32mp135f_dk.dts
new file mode 100644
index 00000000000..5d2f3438355
--- /dev/null
+++ b/boards/st/stm32mp135f_dk/stm32mp135f_dk.dts
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <st/mp13/stm32mp135.dtsi>
+#include <st/mp13/stm32mp135faex-pinctrl.dtsi>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "STMicroelectronics STM32MP135-DK board";
+	compatible = "st,stm32mp135f-dk";
+
+	chosen {
+		zephyr,flash = &ddr_code;
+		zephyr,sram = &ddr_data;
+		zephyr,console = &uart4;
+		zephyr,shell-uart = &uart4;
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		user_button: button {
+			label = "User 1";
+			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		blue_led_1: led_1 {
+			gpios = <&gpioa 14 GPIO_ACTIVE_HIGH>;
+			label = "LD3";
+		};
+
+		red_led_2: led_2 {
+			gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>;
+			label = "LD4";
+		};
+	};
+
+	aliases {
+		led0 = &blue_led_1;
+		led1 = &red_led_2;
+		sw0 = &user_button;
+	};
+};
+
+&clk_hsi {
+	clock-frequency = <DT_FREQ_M(64)>;
+	status = "okay";
+};
+
+&clk_hse {
+	clock-frequency = <DT_FREQ_M(24)>;
+	status = "okay";
+};
+
+&cpusw {
+	clocks = <&clk_hsi>;
+	clock-frequency = <DT_FREQ_M(64)>;
+	status = "okay";
+};
+
+&pll1 {
+	clocks = <&clk_hse>;
+	div-m = <2>;
+	mul-n = <83>;
+	div-p = <1>;
+	frac-v = <2730>;
+	status = "okay";
+};
+
+&rcc {
+	clock-frequency = <DT_FREQ_M(1000)>;
+	clocks = <&pll>;
+	ahb-prescaler = <1>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart4_tx_pd6 &uart4_rx_pd8>;
+	current-speed = <115200>;
+	status = "okay";
+};
diff --git a/boards/st/stm32mp135f_dk/stm32mp135f_dk_defconfig b/boards/st/stm32mp135f_dk/stm32mp135f_dk_defconfig
new file mode 100644
index 00000000000..5a7682e99dd
--- /dev/null
+++ b/boards/st/stm32mp135f_dk/stm32mp135f_dk_defconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2025, STMicroelectronics
+
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable UART driver
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Console (remote proc console by default)
+CONFIG_CONSOLE=y
+
+# UART console (overrides remote proc console)
+CONFIG_UART_CONSOLE=y
diff --git a/boards/st/stm32mp135f_dk/support/Zephyr.tsv b/boards/st/stm32mp135f_dk/support/Zephyr.tsv
new file mode 100644
index 00000000000..9f59a34e927
--- /dev/null
+++ b/boards/st/stm32mp135f_dk/support/Zephyr.tsv
@@ -0,0 +1,5 @@
+#Opt	Id	Name	Type	IP	Offset	Binary
+P	0x1	fsbl-openbl	Binary	none	0x0	External_Mem_Loader_A7.stm32
+P	0x3	fsbl-extfl	Binary	none	0x0	SD_Ext_Loader.bin
+P	0x4	fsbl-app	Binary	mmc0	0x0000080	FSBLA_Sdmmc1_A7_Signed.bin
+P	0x5	fsbl-app	Binary	mmc0	0x0000500	zephyr_Signed.bin
diff --git a/boards/st/stm32mp135f_dk/support/openocd.cfg b/boards/st/stm32mp135f_dk/support/openocd.cfg
new file mode 100644
index 00000000000..95aff7bb7ba
--- /dev/null
+++ b/boards/st/stm32mp135f_dk/support/openocd.cfg
@@ -0,0 +1,4 @@
+source [find board/stm32mp13x_dk.cfg]
+
+# Don't reset the SoC to keep DDR configuration
+reset_config none
diff --git a/boards/st/stm32mp135f_dk/twister.yaml b/boards/st/stm32mp135f_dk/twister.yaml
new file mode 100644
index 00000000000..6e2d37a6482
--- /dev/null
+++ b/boards/st/stm32mp135f_dk/twister.yaml
@@ -0,0 +1,14 @@
+identifier: stm32mp135f_dk
+name: ST STM32MP135F-DK Discovery
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - uart
+  - shell
+ram: 256
+flash: 256
+vendor: st
diff --git a/boards/st/stm32mp157c_dk2/doc/stm32mp157_dk2.rst b/boards/st/stm32mp157c_dk2/doc/stm32mp157_dk2.rst
index bd649f2e251..5610262ab23 100644
--- a/boards/st/stm32mp157c_dk2/doc/stm32mp157_dk2.rst
+++ b/boards/st/stm32mp157c_dk2/doc/stm32mp157_dk2.rst
@@ -151,29 +151,7 @@ More information about STM32P157C can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32mp157c_dk2 board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm32mp157c_dk2/stm32mp157c_dk2_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -211,6 +189,9 @@ console settings are 115200 8N1.
 
 Programming and Debugging
 *************************
+
+.. zephyr:board-supported-runners::
+
 The STM32MP157C doesn't have QSPI flash for the Cortex®-M4  and it needs to be
 started by the Cortex®-A7 core. The Cortex®-A7 core is responsible to load the
 Cortex®-M4 binary application into the RAM, and get the Cortex®-M4 out of reset.
diff --git a/boards/st/stm32mp157c_dk2/stm32mp157c_dk2.yaml b/boards/st/stm32mp157c_dk2/stm32mp157c_dk2.yaml
index 91a4aa38fe0..5fcd4f79ce2 100644
--- a/boards/st/stm32mp157c_dk2/stm32mp157c_dk2.yaml
+++ b/boards/st/stm32mp157c_dk2/stm32mp157c_dk2.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - arduino_i2c
   - arduino_gpio
diff --git a/boards/st/stm32n6570_dk/Kconfig.defconfig b/boards/st/stm32n6570_dk/Kconfig.defconfig
new file mode 100644
index 00000000000..2d792ba9657
--- /dev/null
+++ b/boards/st/stm32n6570_dk/Kconfig.defconfig
@@ -0,0 +1,24 @@
+# STM32N6570 DISCOVERY board configuration
+
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_STM32N6570_DK
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+endif # NETWORKING
+
+if DISPLAY
+
+# MEMC needs to be enabled in order to store
+# display frame buffer to external PSRAM
+config MEMC
+	default y
+
+endif # DISPLAY
+
+endif # BOARD_STM32N6570_DK
diff --git a/boards/st/stm32n6570_dk/Kconfig.stm32n6570_dk b/boards/st/stm32n6570_dk/Kconfig.stm32n6570_dk
new file mode 100644
index 00000000000..66726693896
--- /dev/null
+++ b/boards/st/stm32n6570_dk/Kconfig.stm32n6570_dk
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_STM32N6570_DK
+	select SOC_STM32N657XX
diff --git a/boards/st/stm32n6570_dk/arduino_r3_connector.dtsi b/boards/st/stm32n6570_dk/arduino_r3_connector.dtsi
new file mode 100644
index 00000000000..b3309965278
--- /dev/null
+++ b/boards/st/stm32n6570_dk/arduino_r3_connector.dtsi
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	arduino_header: connector {
+		compatible = "arduino-header-r3";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpioa 5 0>,	/* A0 */
+			   <1 0 &gpioa 9 0>,	/* A1 */
+			   <2 0 &gpioa 10 0>,	/* A2 */
+			   <3 0 &gpioa 12 0>,	/* A3 */
+			   <4 0 &gpiof 3 0>,	/* A4 */
+			   <5 0 &gpiob 10 0>,	/* A5 */
+			   <6 0 &gpiof 6 0>,	/* D0 */
+			   <7 0 &gpiod 5 0>,	/* D1 */
+			   <8 0 &gpiod 0 0>,	/* D2 */
+			   <9 0 &gpioe 9 0>,	/* D3 */
+			   <10 0 &gpioh 5 0>,	/* D4 */
+			   <11 0 &gpioe 10 0>,	/* D5 */
+			   <12 0 &gpioe 13 0>,	/* D6 */
+			   <13 0 &gpiod 6 0>,	/* D7 */
+			   <14 0 &gpioe 7 0>,	/* D8 */
+			   <15 0 &gpioe 14 0>,	/* D9 */
+			   <16 0 &gpioa 3 0>,	/* D10 */
+			   <17 0 &gpiog 2 0>,	/* D11 */
+			   <18 0 &gpioh 8 0>,	/* D12 */
+			   <19 0 &gpioe 15 0>,	/* D13 */
+			   <20 0 &gpioc 1 0>,	/* D14 */
+			   <21 0 &gpioh 9 0>;	/* D15 */
+	};
+};
+
+arduino_serial: &usart2 {};
+arduino_i2c: &i2c1 {};
+arduino_spi: &spi5 {};
diff --git a/boards/st/stm32n6570_dk/board.cmake b/boards/st/stm32n6570_dk/board.cmake
new file mode 100644
index 00000000000..becac84524a
--- /dev/null
+++ b/boards/st/stm32n6570_dk/board.cmake
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2024 STMicroelectronics
+
+if(CONFIG_STM32N6_BOOT_SERIAL)
+  board_runner_args(stm32cubeprogrammer "--port=usb1")
+  board_runner_args(stm32cubeprogrammer "--download-modifiers=0x1")
+  board_runner_args(stm32cubeprogrammer "--start-modifiers=noack")
+else()
+  board_runner_args(stm32cubeprogrammer "--port=swd")
+  board_runner_args(stm32cubeprogrammer "--tool-opt= mode=HOTPLUG ap=1")
+  board_runner_args(stm32cubeprogrammer "--extload=MX66UW1G45G_STM32N6570-DK.stldr")
+  board_runner_args(stm32cubeprogrammer "--download-address=0x70000000")
+endif()
+
+include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake)
diff --git a/boards/st/stm32n6570_dk/board.yml b/boards/st/stm32n6570_dk/board.yml
new file mode 100644
index 00000000000..2bdf8abd80e
--- /dev/null
+++ b/boards/st/stm32n6570_dk/board.yml
@@ -0,0 +1,8 @@
+board:
+  name: stm32n6570_dk
+  full_name: STM32N6570-DK
+  vendor: st
+  socs:
+    - name: stm32n657xx
+      variants:
+        - name: sb
diff --git a/boards/st/stm32n6570_dk/doc/img/stm32n6570_dk.webp b/boards/st/stm32n6570_dk/doc/img/stm32n6570_dk.webp
new file mode 100644
index 00000000000..a6788dc3328
Binary files /dev/null and b/boards/st/stm32n6570_dk/doc/img/stm32n6570_dk.webp differ
diff --git a/boards/st/stm32n6570_dk/doc/index.rst b/boards/st/stm32n6570_dk/doc/index.rst
new file mode 100644
index 00000000000..dd66f90d77f
--- /dev/null
+++ b/boards/st/stm32n6570_dk/doc/index.rst
@@ -0,0 +1,320 @@
+.. zephyr:board:: stm32n6570_dk
+
+Overview
+********
+
+The STM32N6570_DK Discovery kit is a complete demonstration and development platform
+for the Arm® Cortex®‑M55 core‑based STM32N657X0H3Q microcontroller.
+
+The STM32N6570_DK Discovery kit includes a full range of hardware features that help
+the user evaluate many peripherals, such as USB Type-C®, Octo‑SPI flash memory and
+Hexadeca‑SPI PSRAM devices, Ethernet, camera module, LCD, microSD™, audio codec,
+digital microphones, ADC, flexible extension connectors, and user button.
+The four flexible extension connectors feature easy and unlimited expansion capabilities
+for specific applications such as wireless connectivity, analog applications, and sensors.
+
+The STM32N657X0H3Q microcontroller features one USB 2.0 high‑speed/full‑speed
+Device/Host/OTG controller, one USB 2.0 high‑speed/full‑speed Device/Host/OTG controller
+with UCPD (USB Type-C® Power Delivery), one Ethernet with TSN (time-sensitive networking),
+four I2Cs, two I3Cs, six SPIs (of which four I2S‑capable), two SAIs, with four DMIC support,
+five USARTs, five UARTs (ISO78916 interface, LIN, IrDA, up to 12.5 Mbit/s), one LPUART,
+two SDMMCs (MMC version 4.0, CE-ATA version 1.0, and SD version 1.0.1), three CAN FD
+with TTCAN capability, JTAG and SWD debugging support, and Embedded Trace Macrocell™ (ETM).
+
+The STM32N6570_DK Discovery kit integrates an STLINK-V3EC embedded in-circuit debugger and
+programmer for the STM32 MCU, with a USB Virtual COM port bridge and the comprehensive MCU Package.
+
+Hardware
+********
+
+- STM32N657X0H3Q Arm® Cortex®‑M55‑based microcontroller featuring ST Neural-ART Accelerator,
+  H264 encoder, NeoChrom 2.5D GPU, and 4.2 Mbytes of contiguous SRAM, in a VFBGA264 package
+- 5" LCD module with capacitive touch panel
+- USB Type-C® with USB 2.0 HS interface, dual‑role‑power (DRP)
+- USB Type-A with USB 2.0 HS interface, host, 0.5 A max
+- 1‑Gbit Ethernet with TSN (time-sensitive networking) compliant with IEEE‑802.3‑2002
+- SAI audio codec
+- One MEMS digital microphone
+- 1‑Gbit Octo‑SPI flash memory
+- 256-Mbit Hexadeca‑SPI PSRAM
+- Two user LEDs
+- User, tamper, and reset push-buttons
+- Board connectors:
+
+  - USB Type-C®
+  - USB Type-A
+  - Ethernet RJ45
+  - Camera module
+  - microSD™ card
+  - LCD
+  - Stereo headset jack including analog microphone input
+  - Audio MEMS daughterboard expansion connector
+  - ARDUINO® Uno R3 expansion connector
+  - STMod+ expansion connector
+
+- On-board STLINK-V3EC debugger/programmer with USB re-enumeration capability:
+  Virtual COM port, and debug port
+
+For more details, please refer to:
+
+* `STM32N6570_DK website`_
+* `STM32N657X0 on www.st.com`_
+* `STM32N657 reference manual`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+USB
+===
+
+The USB pin assignments on the STM32N657XX microcontroller are immutable. This means that the specific
+pins designated for USB functionality are fixed and cannot be changed or reassigned to other functions,
+ensuring consistent and reliable USB communication.
+
+USB PIN (IOs)
+=============
+
++------------------+--------------------------------------+
+| Name             | Description                          |
++==================+======================================+
+| OTG1_HSDM        | USB OTG1 High-Speed Data- (negative) |
++------------------+--------------------------------------+
+| OTG1_HSDP        | USB OTG1 High-Speed Data+ (positive) |
++------------------+--------------------------------------+
+| OTG1_ID          | USB OTG1 ID Pin                      |
++------------------+--------------------------------------+
+| OTG1_TXRTUNE     | USB OTG1 Transmit Retune             |
++------------------+--------------------------------------+
+| OTG2_HSDM        | USB OTG2 High-Speed Data- (negative) |
++------------------+--------------------------------------+
+| OTG2_HSDP        | USB OTG2 High-Speed Data+ (positive) |
++------------------+--------------------------------------+
+| OTG2_ID          | USB OTG2 ID Pin                      |
++------------------+--------------------------------------+
+| OTG2_TXRTUNE     | USB OTG2 Transmit Retune             |
++------------------+--------------------------------------+
+
+Connections and IOs
+===================
+
+STM32N6570_DK Board has 12 GPIO controllers. These controllers are responsible
+for pin muxing, input/output, pull-up, etc.
+
+For more details please refer to `STM32N6570_DK User Manual`_.
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+- ADC1_INP10 : PA9
+- ADC1_INP11 : PA10
+- FDCAN1_TX : PH2
+- FDCAN1_RX : PD0
+- I2C1_SCL : PH9
+- I2C1_SDA : PC1
+- I2C4_SCL : PE13
+- I2C4_SDA : PE14
+- LD1 : PO1
+- LD2 : PG10
+- SDMMC2_CK : PC2
+- SDMMC2_CMD : PC3
+- SDMMC2_D0 : PC4
+- SDMMC2_D1 : PC5
+- SDMMC2_D2 : PC0
+- SDMMC2_D3 : PE4
+- SPI5_SCK : PE15
+- SPI5_MOSI : PG2
+- SPI5_MISO : PH8
+- SPI5_NSS : PA3
+- USART_1_TX : PE5
+- USART_1_RX : PE6
+- USART_2_TX : PD5
+- USART_2_RX : PF6
+- XSPI1_NCS1 : PO0
+- XSPI1_DQS0 : PO2
+- XSPI1_DQS1 : PO3
+- XSPI1_CLK : PO4
+- XSPI1_IO0 : PP0
+- XSPI1_IO1 : PP1
+- XSPI1_IO2 : PP2
+- XSPI1_IO3 : PP3
+- XSPI1_IO4 : PP4
+- XSPI1_IO5 : PP5
+- XSPI1_IO6 : PP6
+- XSPI1_IO7 : PP7
+- XSPI1_IO8 : PP8
+- XSPI1_IO9 : PP9
+- XSPI1_IO10 : PP10
+- XSPI1_IO11 : PP11
+- XSPI1_IO12 : PP12
+- XSPI1_IO13 : PP13
+- XSPI1_IO14 : PP14
+- XSPI1_IO15 : PP15
+- XSPI2_NCS1 : PN1
+- XSPI2_DQS0 : PN0
+- XSPI2_CLK : PN6
+- XSPI2_IO0 : PN2
+- XSPI2_IO1 : PN3
+- XSPI2_IO2 : PN4
+- XSPI2_IO3 : PN5
+- XSPI2_IO4 : PN8
+- XSPI2_IO5 : PN9
+- XSPI2_IO6 : PN10
+- XSPI2_IO7 : PN11
+
+System Clock
+------------
+
+STM32N6570_DK System Clock could be driven by internal or external oscillator,
+as well as main PLL clock. By default System clock is driven by PLL clock at
+400MHz, driven by 64MHz high speed internal oscillator.
+
+Serial Port
+-----------
+
+STM32N6570_DK board has 10 U(S)ARTs. The Zephyr console output is assigned to
+USART1. Default settings are 115200 8N1.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+STM32N6570_DK board includes an ST-LINK/V3 embedded debug tool interface.
+This probe allows to flash and debug the board using various tools.
+
+
+Flashing or loading
+===================
+
+The board is configured to be programmed using west `STM32CubeProgrammer`_ runner,
+so its :ref:`installation <stm32cubeprog-flash-host-tools>` is needed.
+Version 2.18.0 or later of `STM32CubeProgrammer`_ is required.
+
+.. note::
+   Firmware is run in secure mode of execution, which requires a signature.
+   After build, the build system  will automatically generate a signed version of the
+   binary using `STM32CubeProgrammer`_ utility ``STM32_SigningTool_CLI``.
+   This utility is installed along with `STM32CubeProgrammer`_, but make sure it is
+   available in your ``PATH`` variable.
+
+To program the board, there are two options:
+
+- Program the firmware in external flash. At boot, it will then be loaded on RAM
+  and executed from there.
+- Optionally, it can also be taken advantage from the serial boot interface provided
+  by the boot ROM. In that case, firmware is directly loaded in RAM and executed from
+  there. It is not retained.
+
+Programming an application to STM32N6570_DK
+-------------------------------------------
+
+Here is an example to build and run :zephyr:code-sample:`hello_world` application.
+
+First, connect the STM32N6570_DK to your host computer using the ST-Link USB port.
+
+   .. tabs::
+
+      .. group-tab:: ST-Link
+
+         Build and flash an application using ``stm32n6570_dk`` target.
+
+         .. zephyr-app-commands::
+            :zephyr-app: samples/hello_world
+            :board: stm32n6570_dk
+            :goals: build flash
+
+         .. note::
+            For flashing, before powering the board, set the boot pins in the following configuration:
+
+            * BOOT0: 0
+            * BOOT1: 1
+
+            After flashing, to run the application, set the boot pins in the following configuration:
+
+            * BOOT1: 0
+
+	    Power off and on the board again.
+
+      .. group-tab:: Serial Boot Loader (USB)
+
+         Additionally, connect the STM32N6570_DK to your host computer using the USB port.
+         In this configuration, ST-Link is used to power the board and for serial communication
+         over the Virtual COM Port.
+
+         .. note::
+            Before powering the board, set the boot pins in the following configuration:
+
+            * BOOT0: 1
+            * BOOT1: 0
+
+         Build and load an application using ``stm32n6570_dk/stm32n657xx/sb`` target (you
+         can also use the shortened form: ``stm32n6570_dk//sb``)
+
+         .. zephyr-app-commands::
+            :zephyr-app: samples/hello_world
+            :board: stm32n6570_dk//sb
+            :goals: build flash
+
+
+Run a serial host program to connect with your Disco board:
+
+.. code-block:: console
+
+   $ minicom -D /dev/ttyACM0
+
+You should see the following message on the console:
+
+.. code-block:: console
+
+   Hello World! stm32n6570_dk/stm32n657xx
+
+
+Debugging
+=========
+
+For now debugging is only available through STM32CubeIDE:
+
+* Go to File > Import and select C/C++ > STM32 Cortex-M Executable.
+* In Executable field, browse to your <ZEPHYR_PATH>/build/zephyr/zephyr.elf.
+* In MCU field, select STM32N657X0HxQ.
+* Click on Finish.
+* Finally, click on Debug to start the debugging session.
+
+.. note::
+   For debugging, before powering on the board, set the boot pins in the following configuration:
+
+   * BOOT0: 0
+   * BOOT1: 1
+
+
+Running tests with twister
+==========================
+
+Due to the BOOT switches manipulation required when flashing the board using ``stm32n6570_dk``
+board target, it is only possible to run twister tests campaign on ``stm32n6570_dk/stm32n657xx/sb``
+board target which doesn't require BOOT pins changes to load and execute binaries.
+To do so, it is advised to use Twister's hardware map feature with the following settings:
+
+.. code-block:: yaml
+
+   - platform: stm32n6570_dk/stm32n657xx/sb
+     product: BOOT-SERIAL
+     pre_script: <path_to_zephyr>/boards/st/common/scripts/board_power_reset.sh
+     runner: stm32cubeprogrammer
+
+.. _STM32N6570_DK website:
+   https://www.st.com/en/evaluation-tools/stm32n6570-dk.html
+
+.. _STM32N6570_DK User Manual:
+   https://www.st.com/resource/en/user_manual/um3300-discovery-kit-with-stm32n657x0-mcu-stmicroelectronics.pdf
+
+.. _STM32N657X0 on www.st.com:
+   https://www.st.com/en/microcontrollers-microprocessors/stm32n657x0.html
+
+.. _STM32N657 reference manual:
+   https://www.st.com/resource/en/reference_manual/rm0486-stm32n647657xx-armbased-32bit-mcus-stmicroelectronics.pdf
+
+.. _STM32CubeProgrammer:
+   https://www.st.com/en/development-tools/stm32cubeprog.html
diff --git a/boards/st/stm32n6570_dk/stm32n6570_dk.dts b/boards/st/stm32n6570_dk/stm32n6570_dk.dts
new file mode 100644
index 00000000000..82bb8b72dde
--- /dev/null
+++ b/boards/st/stm32n6570_dk/stm32n6570_dk.dts
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include "stm32n6570_dk_common.dtsi"
+
+/ {
+	model = "STMicroelectronics STM32N6570 Discovery Kit board";
+	compatible = "st,stm32n6570-dk";
+};
diff --git a/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi b/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi
new file mode 100644
index 00000000000..48ee7e4a22a
--- /dev/null
+++ b/boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi
@@ -0,0 +1,366 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/n6/stm32n657X0.dtsi>
+#include <st/n6/stm32n657x0hxq-pinctrl.dtsi>
+#include "zephyr/dt-bindings/display/panel.h"
+#include <zephyr/dt-bindings/flash_controller/xspi.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/video/video-interfaces.h>
+#include "arduino_r3_connector.dtsi"
+
+/ {
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+		zephyr,sram = &axisram2;
+		zephyr,canbus = &fdcan1;
+		zephyr,display = &ltdc;
+		spi-flash0 = &mx66uw1g45g;
+	};
+
+	aliases {
+		led0 = &green_led_1;
+	};
+
+	psram: memory@90000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x90000000 DT_SIZE_M(32)>;
+		zephyr,memory-region = "PSRAM";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		green_led_1: led_1 {
+			gpios = <&gpioo 1 GPIO_ACTIVE_HIGH>;
+			label = "User LD1";
+		};
+
+		red_led_1: led_2 {
+			gpios = <&gpiog 10 GPIO_ACTIVE_HIGH>;
+			label = "User LD2";
+		};
+	};
+};
+
+&clk_hse {
+	hse-div2;
+	clock-frequency = <DT_FREQ_M(48)>;
+	status = "okay";
+};
+
+&clk_hsi {
+	hsi-div = <1>;
+	status = "okay";
+};
+
+&pll1 {
+	clocks = <&clk_hse>;
+	div-m = <3>;
+	mul-n = <150>;
+	div-p1 = <1>;
+	div-p2 = <1>;
+	status = "okay";
+};
+
+&pll2 {
+	clocks = <&clk_hsi>;
+	div-m = <2>;
+	mul-n = <48>;
+	div-p1 = <1>;
+	div-p2 = <1>;
+	status = "okay";
+};
+
+&pll3 {
+	clocks = <&clk_hse>;
+	div-m = <3>;
+	mul-n = <125>;
+	div-p1 = <1>;
+	div-p2 = <1>;
+	status = "okay";
+};
+
+&pll4 {
+	clocks = <&clk_hsi>;
+	div-m = <4>;
+	mul-n = <75>;
+	div-p1 = <1>;
+	div-p2 = <1>;
+	status = "okay";
+};
+
+&ic1 {
+	pll-src = <1>;
+	ic-div = <3>;
+	status = "okay";
+};
+
+&ic2 {
+	pll-src = <1>;
+	ic-div = <6>;
+	status = "okay";
+};
+
+&ic3 {
+	pll-src = <1>;
+	ic-div = <6>;
+	status = "okay";
+};
+
+&ic4 {
+	pll-src = <2>;
+	ic-div = <32>;
+	status = "okay";
+};
+
+&ic6 {
+	pll-src = <3>;
+	ic-div = <2>;
+	status = "okay";
+};
+
+&ic11 {
+	pll-src = <1>;
+	ic-div = <3>;
+	status = "okay";
+};
+
+&ic16 {
+	pll-src = <4>;
+	ic-div = <60>;
+	status = "okay";
+};
+
+&perck {
+	clocks = <&rcc STM32_SRC_HSI PER_SEL(0)>;
+	status = "okay";
+};
+
+&cpusw {
+	clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;
+	clock-frequency = <DT_FREQ_M(800)>;
+	status = "okay";
+};
+
+&rcc {
+	/* ic2, ic6 & ic11 must all be enabled to set ic2 as SYSCLK */
+	clocks = <&ic2>;
+	clock-frequency = <DT_FREQ_M(400)>;
+	ahb-prescaler = <2>;
+	timg-prescaler = <2>;
+};
+
+&adc1 {
+	clocks = <&rcc STM32_CLOCK(AHB1, 5)>,
+		 <&rcc STM32_SRC_CKPER ADC12_SEL(1)>;
+	pinctrl-0 = <&adc1_inp10_pa9 &adc1_inp11_pa10>; /* Arduino A1 & A2 */
+	pinctrl-names = "default";
+	vref-mv = <1800>;
+	status = "okay";
+};
+
+&fdcan1 {
+	clocks = <&rcc STM32_CLOCK(APB1_2, 8)>,
+		 <&rcc STM32_SRC_CKPER FDCAN_SEL(1)>;
+	pinctrl-0 = <&fdcan1_rx_pd0 &fdcan1_tx_ph2>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c1 {
+	clocks = <&rcc STM32_CLOCK(APB1, 21)>,
+		 <&rcc STM32_SRC_CKPER I2C1_SEL(1)>;
+	pinctrl-0 = <&i2c1_scl_ph9 &i2c1_sda_pc1>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	status = "okay";
+};
+
+&i2c4 {
+	clocks = <&rcc STM32_CLOCK(APB4, 7)>,
+		 <&rcc STM32_SRC_CKPER I2C4_SEL(1)>;
+	pinctrl-0 = <&i2c4_scl_pe13 &i2c4_sda_pe14>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	status = "okay";
+};
+
+&sdmmc2 {
+	status = "okay";
+	clocks = <&rcc STM32_CLOCK(AHB5, 7)>,
+		 <&rcc STM32_SRC_IC4 SDMMC2_SEL(2)>;
+	pinctrl-0 = <&sdmmc2_d0_pc4 &sdmmc2_d1_pc5
+			&sdmmc2_d2_pc0 &sdmmc2_d3_pe4
+			&sdmmc2_ck_pc2 &sdmmc2_cmd_pc3>;
+	pinctrl-names = "default";
+	bus-width = <4>;
+	cd-gpios = <&gpion 12 GPIO_ACTIVE_HIGH>;
+	pwr-gpios = <&gpioq 7 GPIO_ACTIVE_HIGH>;
+};
+
+&spi5 {
+	clocks = <&rcc STM32_CLOCK(APB2, 20)>,
+		 <&rcc STM32_SRC_CKPER SPI5_SEL(1)>;
+	pinctrl-0 = <&spi5_nss_pa3 &spi5_sck_pe15 &spi5_miso_ph8 &spi5_mosi_pg2>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&usart1 {
+	clocks = <&rcc STM32_CLOCK(APB2, 4)>,
+		 <&rcc STM32_SRC_CKPER USART1_SEL(1)>;
+	pinctrl-0 = <&usart1_tx_pe5 &usart1_rx_pe6>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&usart2 {
+	clocks = <&rcc STM32_CLOCK(APB1, 17)>,
+		 <&rcc STM32_SRC_CKPER USART2_SEL(1)>;
+	pinctrl-0 = <&usart2_tx_pd5 &usart2_rx_pf6>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+zephyr_udc0: &usbotg_hs1 {
+	status = "okay";
+};
+
+&xspi1 {
+	pinctrl-0 = <&xspim_p1_ncs1_po0 &xspim_p1_dqs0_po2
+		     &xspim_p1_dqs1_po3 &xspim_p1_clk_po4
+		     &xspim_p1_io0_pp0 &xspim_p1_io1_pp1 &xspim_p1_io2_pp2
+		     &xspim_p1_io3_pp3 &xspim_p1_io4_pp4 &xspim_p1_io5_pp5
+		     &xspim_p1_io6_pp6 &xspim_p1_io7_pp7 &xspim_p1_io8_pp8
+		     &xspim_p1_io9_pp9 &xspim_p1_io10_pp10 &xspim_p1_io11_pp11
+		     &xspim_p1_io12_pp12 &xspim_p1_io13_pp13 &xspim_p1_io14_pp14
+		     &xspim_p1_io15_pp15>;
+	pinctrl-names = "default";
+	clocks = <&rcc STM32_CLOCK(AHB5, 5)>,
+		 <&rcc STM32_SRC_IC3 XSPI1_SEL(2)>,
+		 <&rcc STM32_CLOCK(AHB5, 13)>;
+	status = "okay";
+
+	memc: aps256xxn_obr: memory@90000000 {
+		compatible = "st,stm32-xspi-psram";
+		reg = <0x90000000 DT_SIZE_M(32)>; /* 256 Mbits */
+		fixed-latency;
+		io-x16-mode;
+		read-latency = <4>;
+		write-latency = <1>;
+		burst-length = <0>;
+		status = "okay";
+	};
+};
+
+&xspi2 {
+	pinctrl-0 = <&xspim_p2_ncs1_pn1 &xspim_p2_dqs0_pn0 &xspim_p2_clk_pn6
+		     &xspim_p2_io0_pn2 &xspim_p2_io1_pn3 &xspim_p2_io2_pn4
+		     &xspim_p2_io3_pn5 &xspim_p2_io4_pn8 &xspim_p2_io5_pn9
+		     &xspim_p2_io6_pn10 &xspim_p2_io7_pn11>;
+	pinctrl-names = "default";
+	clocks = <&rcc STM32_CLOCK(AHB5, 12)>,
+		 <&rcc STM32_SRC_IC3 XSPI1_SEL(2)>,
+		 <&rcc STM32_CLOCK(AHB5, 13)>;
+	status = "okay";
+
+	mx66uw1g45g: ospi-nor-flash@70000000 {
+		compatible = "st,stm32-xspi-nor";
+		reg = <0x70000000 DT_SIZE_M(128)>; /* 1 Gbits */
+		ospi-max-frequency = <DT_FREQ_M(200)>;
+		spi-bus-width = <XSPI_OCTO_MODE>;
+		data-rate = <XSPI_DTR_TRANSFER>;
+		four-byte-opcodes;
+		status = "okay";
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			storage_partition: partition@7ff0000 {
+				label = "storage";
+				reg = <0x7ff0000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};
+
+&mac {
+	status = "okay";
+	pinctrl-0 = <&eth1_rgmii_gtx_clk_pf0
+		     &eth1_rgmii_clk125_pf2
+		     &eth1_rgmii_rx_clk_pf7
+		     &eth1_rgmii_rxd2_pf8
+		     &eth1_rgmii_rxd3_pf9
+		     &eth1_rgmii_rx_ctl_pf10
+		     &eth1_rgmii_tx_ctl_pf11
+		     &eth1_rgmii_txd1_pf13
+		     &eth1_rgmii_txd0_pf12
+		     &eth1_rgmii_rxd0_pf14
+		     &eth1_rgmii_rxd1_pf15
+		     &eth1_rgmii_txd2_pg3
+		     &eth1_rgmii_txd3_pg4
+		     &eth1_phy_intn_pd3>;
+	pinctrl-names = "default";
+	phy-connection-type = "rgmii";
+	phy-handle = <&eth_phy>;
+};
+
+&mdio {
+	status = "okay";
+	pinctrl-0 = <&eth1_mdio_pd12 &eth1_mdc_pd1>;
+	pinctrl-names = "default";
+
+	eth_phy: ethernet-phy@0 {
+		compatible = "ethernet-phy";
+		reg = <0x0>;
+	};
+};
+
+&ltdc {
+	clocks = <&rcc STM32_CLOCK(APB5, 1)>,
+		 <&rcc STM32_SRC_IC16 LTDC_SEL(2)>;
+	pinctrl-0 = <&ltdc_r0_pg0 &ltdc_r1_pd9 &ltdc_r2_pd15 &ltdc_r3_pb4
+			&ltdc_r4_ph4 &ltdc_r5_pa15 &ltdc_r6_pg11 &ltdc_r7_pd8
+			&ltdc_g0_pg12 &ltdc_g1_pg1 &ltdc_g2_pa1 &ltdc_g3_pa0
+			&ltdc_g4_pb15 &ltdc_g5_pb12 &ltdc_g6_pb11 &ltdc_g7_pg8
+			&ltdc_b0_pg15 &ltdc_b1_pa7 &ltdc_b2_pb2 &ltdc_b3_pg6
+			&ltdc_b4_ph3 &ltdc_b5_ph6 &ltdc_b6_pa8 &ltdc_b7_pa2
+			&ltdc_de_pg13 &ltdc_clk_pb13 &ltdc_hsync_pb14 &ltdc_vsync_pe11>;
+	pinctrl-names = "default";
+	disp-on-gpios = <&gpioq 3 GPIO_ACTIVE_HIGH>;
+	bl-ctrl-gpios = <&gpioq 6 GPIO_ACTIVE_HIGH>;
+
+	ext-sdram = <&psram>;
+
+	status = "okay";
+
+	width = <800>;
+	height = <480>;
+	pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
+	display-timings {
+		compatible = "zephyr,panel-timing";
+		de-active = <0>;
+		pixelclk-active = <0>;
+		hsync-active = <0>;
+		vsync-active = <0>;
+		hsync-len = <4>;
+		vsync-len = <4>;
+		hback-porch = <8>;
+		vback-porch = <8>;
+		hfront-porch = <8>;
+		vfront-porch = <8>;
+	};
+	def-back-color-red = <0xFF>;
+	def-back-color-green = <0xFF>;
+	def-back-color-blue = <0xFF>;
+};
diff --git a/boards/st/stm32n6570_dk/stm32n6570_dk_defconfig b/boards/st/stm32n6570_dk/stm32n6570_dk_defconfig
new file mode 100644
index 00000000000..01abfa9c0b7
--- /dev/null
+++ b/boards/st/stm32n6570_dk/stm32n6570_dk_defconfig
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2024 STMicroelectronics
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# No internal Flash
+CONFIG_XIP=n
diff --git a/boards/st/stm32n6570_dk/stm32n6570_dk_stm32n657xx_sb.dts b/boards/st/stm32n6570_dk/stm32n6570_dk_stm32n657xx_sb.dts
new file mode 100644
index 00000000000..967209c2fcc
--- /dev/null
+++ b/boards/st/stm32n6570_dk/stm32n6570_dk_stm32n657xx_sb.dts
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include "stm32n6570_dk_common.dtsi"
+
+/ {
+	model = "STMicroelectronics STM32N6570 Discovery Kit board";
+	compatible = "st,stm32n6570-dk-serial-boot";
+};
diff --git a/boards/st/stm32n6570_dk/stm32n6570_dk_stm32n657xx_sb_defconfig b/boards/st/stm32n6570_dk/stm32n6570_dk_stm32n657xx_sb_defconfig
new file mode 100644
index 00000000000..33b0f281a2f
--- /dev/null
+++ b/boards/st/stm32n6570_dk/stm32n6570_dk_stm32n657xx_sb_defconfig
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2024 STMicroelectronics
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# No internal Flash
+CONFIG_XIP=n
+
+# Use serial boot (USB)
+CONFIG_STM32N6_BOOT_SERIAL=y
diff --git a/boards/st/stm32n6570_dk/twister.yaml b/boards/st/stm32n6570_dk/twister.yaml
new file mode 100644
index 00000000000..27d6d2d7975
--- /dev/null
+++ b/boards/st/stm32n6570_dk/twister.yaml
@@ -0,0 +1,27 @@
+name: STM32N6570 Discovery Kit
+type: mcu
+arch: arm
+ram: 1024
+flash: 1024
+vendor: st
+supported:
+  - arduino_i2c
+  - arduino_serial
+  - arduino_spi
+  - adc
+  - can
+  - dma
+  - i2c
+  - gpio
+  - memc
+  - spi
+  - uart
+  - usb_device
+  - usbd
+variants:
+  stm32n6570_dk/stm32n657xx:
+    twister: false
+  stm32n6570_dk/stm32n657xx/sb:
+    toolchain:
+      - zephyr
+      - gnuarmemb
diff --git a/boards/st/stm32u083c_dk/doc/index.rst b/boards/st/stm32u083c_dk/doc/index.rst
index 81ddcf92a1f..433ba53bf31 100644
--- a/boards/st/stm32u083c_dk/doc/index.rst
+++ b/boards/st/stm32u083c_dk/doc/index.rst
@@ -144,34 +144,7 @@ More information about STM32U083MC can be found here:
 Supported Features
 ==================
 
-The Zephyr stm32u083c_dk board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| DAC       | on-chip    | DAC Controller                      |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/stm32u083c_dk/stm32u083c_dk_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -214,6 +187,8 @@ USART2. Default settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32U083C_DK board includes an ST-LINK/V3 embedded debug tool interface.
 This probe allows to flash the board using various tools.
 
diff --git a/boards/st/stm32u083c_dk/stm32u083c_dk.dts b/boards/st/stm32u083c_dk/stm32u083c_dk.dts
index 4f340422d51..c5cbfb93a2e 100644
--- a/boards/st/stm32u083c_dk/stm32u083c_dk.dts
+++ b/boards/st/stm32u083c_dk/stm32u083c_dk.dts
@@ -9,6 +9,7 @@
 #include <st/u0/stm32u083mctx-pinctrl.dtsi>
 #include "arduino_r3_connector.dtsi"
 #include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/input/stm32-tsc-defines.h>
 
 / {
 	model = "STMicroelectronics STM32U83C-DK board";
@@ -124,3 +125,38 @@
 		status = "okay";
 	};
 };
+
+&tsc {
+	status = "okay";
+	pinctrl-0 = <&tsc_g1_io1_pb12 &tsc_g1_io2_pb13 &tsc_g6_io1_pd10 &tsc_g6_io2_pd11>;
+	pinctrl-names = "default";
+
+	st,pulse-generator-prescaler = <2>;
+	st,charge-transfer-pulse-high = <2>;
+	st,charge-transfer-pulse-low = <2>;
+	st,spread-spectrum;
+	st,spread-spectrum-prescaler = <2>;
+	st,spread-spectrum-deviation = <100>;
+	st,max-count-value = <8191>;
+
+	tsc_group1: g1 {
+		group = <1>;
+		st,use-as-shield;
+		channel-ios = <TSC_IO2>;
+		sampling-io = <TSC_IO1>;
+	};
+
+	tsc_group6: g6 {
+		group = <6>;
+		channel-ios = <TSC_IO2>;
+		sampling-io = <TSC_IO1>;
+		ts1 {
+			compatible = "tsc-keys";
+			sampling-interval-ms = <10>;
+			oversampling = <10>;
+			noise-threshold = <50>;
+			sticky-key-timeout-ms = <10000>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+};
diff --git a/boards/st/stm32u083c_dk/stm32u083c_dk.yaml b/boards/st/stm32u083c_dk/stm32u083c_dk.yaml
index 3db304b10ef..e6add7e72aa 100644
--- a/boards/st/stm32u083c_dk/stm32u083c_dk.yaml
+++ b/boards/st/stm32u083c_dk/stm32u083c_dk.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - arduino_gpio
@@ -16,5 +15,6 @@ supported:
   - i2c
   - pwm
   - usart
+  - tsc
 ram: 40
 flash: 256
diff --git a/boards/st/stm32u5a9j_dk/doc/index.rst b/boards/st/stm32u5a9j_dk/doc/index.rst
index 0851459c268..0f4874d425b 100644
--- a/boards/st/stm32u5a9j_dk/doc/index.rst
+++ b/boards/st/stm32u5a9j_dk/doc/index.rst
@@ -47,48 +47,7 @@ More information about STM32U5A9NJH6Q can be found here:
 Supported Features
 ==================
 
-The current Zephyr stm32u5a9j_dk board configuration supports the following
-hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| LPUART    | on-chip    | low power uart                      |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| SDMMC     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| WATCHDOG  | on-chip    | independent watchdog                |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| TIMER     | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | rtc                                 |
-+-----------+------------+-------------------------------------+
-
-Other hardware features have not been enabled yet for this board.
-
-The default configuration per core can be found in the defconfig file:
-:zephyr_file:`boards/st/stm32u5a9j_dk/stm32u5a9j_dk_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -133,6 +92,8 @@ ST-LINK/V3.0. Virtual COM port interface. Default communication settings are
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32U5A9J Discovery kit includes an ST-LINK/V3 embedded debug tool interface.
 This probe allows to flash and debug the board using various tools.
 
diff --git a/boards/st/stm32vl_disco/doc/index.rst b/boards/st/stm32vl_disco/doc/index.rst
index a2bb8c8baec..386e6d38427 100644
--- a/boards/st/stm32vl_disco/doc/index.rst
+++ b/boards/st/stm32vl_disco/doc/index.rst
@@ -35,50 +35,7 @@ More information about the STM32F100x can be found in the
 Supported Features
 ==================
 
-The Zephyr stm32vl_disco board configuration supports the following hardware features:
-
-.. list-table:: Supported hardware
-   :header-rows: 1
-
-   * - Interface
-     - Controller
-     - Driver/component
-   * - NVIC
-     - on-chip
-     - nested vector interrupt controller
-   * - UART
-     - on-chip
-     - serial port-polling
-       serial port-interrupt
-   * - PINMUX
-     - on-chip
-     - pinmux
-   * - GPIO
-     - on-chip
-     - gpio
-   * - CLOCK
-     - on-chip
-     - reset and clock control
-   * - FLASH
-     - on-chip
-     - flash memory
-   * - WATCHDOG
-     - on-chip
-     - window watchdog
-   * - I2C
-     - on-chip
-     - i2c
-   * - SPI
-     - on-chip
-     - spi
-   * - ADC
-     - on-chip
-     - adc
-
-Other hardware features are not yet supported in this Zephyr port.
-
-The default configuration can be found in
-:zephyr_file:`boards/st/stm32vl_disco/stm32vl_disco_defconfig`
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -117,6 +74,8 @@ For more details please refer to `STM32VLDISCOVERY board User Manual`_.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``stm32vl_disco`` board configuration can be built and
 flashed in the usual way (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/st/stm32vl_disco/stm32vl_disco.yaml b/boards/st/stm32vl_disco/stm32vl_disco.yaml
index 5e37731dfcc..0167ec3e797 100644
--- a/boards/st/stm32vl_disco/stm32vl_disco.yaml
+++ b/boards/st/stm32vl_disco/stm32vl_disco.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 8
 flash: 128
 supported:
diff --git a/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst b/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst
index 3a7bae73f13..94f8e5f3663 100644
--- a/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst
+++ b/boards/st/stm32wb5mm_dk/doc/stm32wb5mm_dk.rst
@@ -98,7 +98,7 @@ enable extended battery life, small coin-cell batteries, and energy harvesting.
     trimmed RC (±1%)
   - 2x PLL for system clock, USB, SAI, ADC
 
-More information about STM32WB55RG can be found here:
+More information about STM32WB5MMG can be found here:
 
 - `STM32WB5MM-DK on www.st.com`_
 - `STM32WB5MMG datasheet`_
@@ -106,22 +106,7 @@ More information about STM32WB55RG can be found here:
 Supported Features
 ==================
 
-The Zephyr STM32WB5MM-DK board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/stm32wb5mm_dk/stm32wb5mm_dk_defconfig`
+.. zephyr:board-supported-hw::
 
 Bluetooth and compatibility with STM32WB Copro Wireless Binaries
 ================================================================
@@ -132,8 +117,7 @@ These binaries are delivered in STM32WB Cube packages, under
 ``Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/``.
 
 For compatibility information with the various versions of these binaries,
-please check `modules/hal/stm32/lib/stm32wb/hci/README`_
-in the ``hal_stm32`` repo.
+please check :module_file:`hal_stm32:lib/stm32wb/README.rst`.
 
 Note that since STM32WB Cube package V1.13.2, "full stack" binaries are not
 compatible anymore for a use in Zephyr and only "HCI Only" versions should be
@@ -182,6 +166,8 @@ and the second to PC13. They have the aliases sw0 and sw1 respectively.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 STM32WB5MM-DK has an on-board ST-Link to flash and debug the firmware on the module.
 
 Applications for the ``stm32wb5mm_dk`` board configuration can be built the
@@ -245,9 +231,6 @@ You can debug an application in the usual way.  Here is an example for the
 .. _STM32WB5MMG datasheet:
    https://www.st.com/resource/en/datasheet/stm32wb5mmg.pdf
 
-.. _modules/hal/stm32/lib/stm32wb/hci/README:
-   https://github.com/zephyrproject-rtos/hal_stm32/blob/main/lib/stm32wb/hci/README
-
 .. _Hello_World:
    https://docs.zephyrproject.org/latest/samples/hello_world/README.html
 
diff --git a/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.yaml b/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.yaml
index a90491d13aa..aa2472a2343 100644
--- a/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.yaml
+++ b/boards/st/stm32wb5mm_dk/stm32wb5mm_dk.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 256
 flash: 876
 supported:
diff --git a/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst b/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst
index f4f2a34cdd1..b9718b73ca8 100644
--- a/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst
+++ b/boards/st/stm32wb5mmg/doc/stm32wb5mmg.rst
@@ -149,7 +149,7 @@ cut 2.2.
    and Bluetooth|reg| Low Energy
  - 48-bit EUI
 
-More information about STM32WB55RG can be found here:
+More information about STM32WB5MMG can be found here:
 
 - `STM32WB5MMG on www.st.com`_
 - `STM32WB5MMG datasheet`_
@@ -157,22 +157,7 @@ More information about STM32WB55RG can be found here:
 Supported Features
 ==================
 
-The Zephyr STM32WB5MMG board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| RADIO     | on-chip    | Bluetooth Low Energy                |
-+-----------+------------+-------------------------------------+
-
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/st/stm32wb5mmg/stm32wb5mmg_defconfig`
+.. zephyr:board-supported-hw::
 
 Bluetooth and compatibility with STM32WB Copro Wireless Binaries
 ================================================================
@@ -180,10 +165,11 @@ Bluetooth and compatibility with STM32WB Copro Wireless Binaries
 To operate bluetooth on STM32WB5MMG, Cortex-M0 core should be flashed with
 a valid STM32WB Coprocessor binaries (either 'Full stack' or 'HCI Layer').
 These binaries are delivered in STM32WB Cube packages, under
-Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/
+``Projects/STM32WB_Copro_Wireless_Binaries/STM32WB5x/``
+
 For compatibility information with the various versions of these binaries,
-please check `modules/hal/stm32/lib/stm32wb/hci/README`_
-in the hal_stm32 repo.
+please check :module_file:`hal_stm32:lib/stm32wb/README.rst`.
+
 Note that since STM32WB Cube package V1.13.2, "full stack" binaries are not compatible
 anymore for a use in Zephyr and only "HCI Only" versions should be used on the M0
 side.
@@ -221,6 +207,8 @@ Rather, users can use the available USB port (CN12) to run virtual com port
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``stm32wb5mmg`` board configuration can be built the
 usual way (see :ref:`build_an_application`).
 
@@ -303,8 +291,5 @@ You can debug an application in the usual way.  Here is an example for the
 .. _STM32WB5MMG datasheet:
    https://www.st.com/resource/en/datasheet/stm32wb5mmg.pdf
 
-.. _modules/hal/stm32/lib/stm32wb/hci/README:
-  https://github.com/zephyrproject-rtos/hal_stm32/blob/main/lib/stm32wb/hci/README
-
 .. _STM32CubeProgrammer:
    https://www.st.com/en/development-tools/stm32cubeprog.html
diff --git a/boards/st/stm32wb5mmg/stm32wb5mmg.yaml b/boards/st/stm32wb5mmg/stm32wb5mmg.yaml
index 2e3667f18d5..5b9de8b09c7 100644
--- a/boards/st/stm32wb5mmg/stm32wb5mmg.yaml
+++ b/boards/st/stm32wb5mmg/stm32wb5mmg.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 256
 flash: 1024
 supported:
diff --git a/boards/starfive/visionfive2/doc/index.rst b/boards/starfive/visionfive2/doc/index.rst
index 24cebc6021c..8c71e2bfb94 100644
--- a/boards/starfive/visionfive2/doc/index.rst
+++ b/boards/starfive/visionfive2/doc/index.rst
@@ -9,6 +9,8 @@ multi-core 64bit RISC-V SoC.
 Programming and debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Building
 ========
 
diff --git a/boards/tdk/robokit1/doc/index.rst b/boards/tdk/robokit1/doc/index.rst
index 4f674a18861..4b588854c63 100644
--- a/boards/tdk/robokit1/doc/index.rst
+++ b/boards/tdk/robokit1/doc/index.rst
@@ -32,75 +32,7 @@ Hardware
 Supported Features
 ==================
 
-The TDK RoboKit1 board supports the following hardware
-features:
-
-.. list-table::
-   : header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO_SAM`
-     - :dtcompatible:`atmel,sam-gpio`
-   * - USART
-     - :kconfig:option:`CONFIG_USART_SAM`
-     - :dtcompatible:`atmel,sam-usart`
-   * - UART
-     - :kconfig:option:`CONFIG_UART_SAM`
-     - :dtcompatible:`atmel,sam-uart`
-   * - SPI
-     - :kconfig:option:`CONFIG_SPI_SAM`
-     - :dtcompatible:`atmel,sam-spi`
-   * - I2C
-     - :kconfig:option:`CONFIG_I2C_SAM_TWIHS`
-     - :dtcompatible:`atmel,sam-i2c-twihs`
-   * - I2S
-     - :kconfig:option:`CONFIG_I2S_SAM_SSC`
-     - :dtcompatible:`atmel,sam-ssc`
-   * - ADC
-     - :kconfig:option:`CONFIG_ADC_SAM_AFEC`
-     - :dtcompatible:`atmel,sam-afec`
-   * - DAC
-     - :kconfig:option:`CONFIG_DAC_SAM`
-     - :dtcompatible:`atmel,sam-dac`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM_SAM`
-     - :dtcompatible:`atmel,sam-pwm`
-   * - CAN
-     - :kconfig:option:`CONFIG_CAN_SAM`
-     - :dtcompatible:`atmel,sam-can`
-   * - USB
-     - :kconfig:option:`CONFIG_USB_DC_SAM_USBHS`
-     - :dtcompatible:`atmel,sam-usbhs`
-   * - WATCHDOG
-     - :kconfig:option:`CONFIG_WDT_SAM`
-     - :dtcompatible:`atmel,sam-watchdog`
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v7m-nvic`
-   * - SYSTICK
-     - N/A
-     - N/A
-   * - COUNTER
-     - :kconfig:option:`CONFIG_COUNTER_SAM_TC`
-     - :dtcompatible:`atmel,sam-tc`
-   * - DMA
-     - :kconfig:option:`CONFIG_DMA_SAM_XDMAC`
-     - :dtcompatible:`atmel,sam-xdmac`
-   * - ENTROPY
-     - :kconfig:option:`CONFIG_ENTROPY_SAM_RNG`
-     - :dtcompatible:`atmel,sam-trng`
-   * - HWINFO (reset cause)
-     - :kconfig:option:`CONFIG_HWINFO_SAM_RSTC`
-     - :dtcompatible:`atmel,sam-rstc`
-   * - HWINFO (device id)
-     - :kconfig:option:`CONFIG_HWINFO_SAM`
-     - N/A
-
-The default configuration can be found in the Kconfig
-:zephyr_file:`boards/tdk/robokit1/robokit1_defconfig`.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -122,6 +54,8 @@ configured for the console and is available as a Virtual COM Port via the USB2 c
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing the Zephyr project onto SAM E70 MCU requires the `OpenOCD tool`_.
 Both west flash and west debug commands should correctly work with both USB0 and USB1
 connected and the board powered.
diff --git a/boards/tdk/robokit1/robokit1.yaml b/boards/tdk/robokit1/robokit1.yaml
index 8cbd19f73a6..1f71210c029 100644
--- a/boards/tdk/robokit1/robokit1.yaml
+++ b/boards/tdk/robokit1/robokit1.yaml
@@ -7,7 +7,6 @@ ram: 384
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - can
   - dma
diff --git a/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.yaml b/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.yaml
index 7baa570c548..231a61b748d 100644
--- a/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.yaml
+++ b/boards/technexion/pico_pi/pico_pi_mcimx7d_m4.yaml
@@ -13,7 +13,6 @@ flash: 32
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 testing:
   ignore_tags:
     - net
diff --git a/boards/telink/tlsr9518adk80d/doc/index.rst b/boards/telink/tlsr9518adk80d/doc/index.rst
index 27a65a04299..b67c40bcad3 100644
--- a/boards/telink/tlsr9518adk80d/doc/index.rst
+++ b/boards/telink/tlsr9518adk80d/doc/index.rst
@@ -38,45 +38,13 @@ The TLSR9518ADK80D default board configuration provides the following hardware c
 Supported Features
 ==================
 
-The Zephyr TLSR9518ADK80D board configuration supports the following hardware features:
-
-+----------------+------------+------------------------------+
-| Interface      | Controller | Driver/Component             |
-+================+============+==============================+
-| PLIC           | on-chip    | interrupt_controller         |
-+----------------+------------+------------------------------+
-| RISC-V Machine | on-chip    | timer                        |
-| Timer (32 KHz) |            |                              |
-+----------------+------------+------------------------------+
-| PINCTRL        | on-chip    | pinctrl                      |
-+----------------+------------+------------------------------+
-| GPIO           | on-chip    | gpio                         |
-+----------------+------------+------------------------------+
-| UART           | on-chip    | serial                       |
-+----------------+------------+------------------------------+
-| PWM            | on-chip    | pwm                          |
-+----------------+------------+------------------------------+
-| TRNG           | on-chip    | entropy                      |
-+----------------+------------+------------------------------+
-| FLASH (MSPI)   | on-chip    | flash                        |
-+----------------+------------+------------------------------+
-| RADIO          | on-chip    | Bluetooth,                   |
-|                |            | ieee802154, OpenThread       |
-+----------------+------------+------------------------------+
-| SPI (Master)   | on-chip    | spi                          |
-+----------------+------------+------------------------------+
-| I2C (Master)   | on-chip    | i2c                          |
-+----------------+------------+------------------------------+
-| ADC            | on-chip    | adc                          |
-+----------------+------------+------------------------------+
+.. zephyr:board-supported-hw::
 
 .. note::
    To support "button" example project PC3-KEY3 (J20-19, J20-20) jumper needs to be removed and KEY3 (J20-19) should be connected to VDD3_DCDC (J51-13) externally.
 
    For the rest example projects use the default jumpers configuration.
 
-Other hardware features and example projects are not supported yet.
-
 Limitations
 -----------
 
@@ -138,6 +106,8 @@ The default settings are 115200 8N1.
 Programming and debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Building
 ========
 
diff --git a/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl.yaml b/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl.yaml
index 57e62c2ddec..eeebe7e0336 100644
--- a/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl.yaml
+++ b/boards/ti/cc1352p1_launchxl/cc1352p1_launchxl.yaml
@@ -7,7 +7,6 @@ flash: 352
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/ti/cc1352p1_launchxl/doc/index.rst b/boards/ti/cc1352p1_launchxl/doc/index.rst
index dc807f55942..f83d42f4f42 100644
--- a/boards/ti/cc1352p1_launchxl/doc/index.rst
+++ b/boards/ti/cc1352p1_launchxl/doc/index.rst
@@ -26,32 +26,7 @@ See the `TI CC1352P Product Page`_ for additional details.
 Supported Features
 ==================
 
-The CC1352P LaunchPad board configuration supports the following hardware
-features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PINMUX    | on-chip    | pinmux               |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-| HWINFO    | on-chip    | hwinfo               |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -122,6 +97,8 @@ aligns with the LaunchPad standard.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Before flashing or debugging ensure the RESET, TMS, TCK, TDO, and TDI jumpers
 are in place. Also place jumpers on the TXD and RXD signals for a serial
 console using the XDS110 application serial port.
diff --git a/boards/ti/cc1352p7_launchpad/cc1352p7_lp.yaml b/boards/ti/cc1352p7_launchpad/cc1352p7_lp.yaml
index fe3a834ebcf..8d438b75ed1 100644
--- a/boards/ti/cc1352p7_launchpad/cc1352p7_lp.yaml
+++ b/boards/ti/cc1352p7_launchpad/cc1352p7_lp.yaml
@@ -7,11 +7,11 @@ flash: 704
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
   - spi
   - watchdog
   - hwinfo
+  - netif:openthread
 vendor: ti
diff --git a/boards/ti/cc1352p7_launchpad/doc/index.rst b/boards/ti/cc1352p7_launchpad/doc/index.rst
index 6ad90f18e86..346bcf6bc3d 100644
--- a/boards/ti/cc1352p7_launchpad/doc/index.rst
+++ b/boards/ti/cc1352p7_launchpad/doc/index.rst
@@ -27,32 +27,7 @@ See the `TI CC1352P7 Product Page`_ for additional details.
 Supported Features
 ==================
 
-The CC1352P7 LaunchPad board configuration supports the following hardware
-features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PINMUX    | on-chip    | pinmux               |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-| HWINFO    | on-chip    | hwinfo               |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -123,6 +98,8 @@ aligns with the LaunchPad standard.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Before flashing or debugging ensure the RESET, TMS, TCK, TDO, and TDI jumpers
 are in place. Also place jumpers on the TXD and RXD signals for a serial
 console using the XDS110 application serial port.
diff --git a/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl.yaml b/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl.yaml
index 7c37a902893..ce8bfb6127f 100644
--- a/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl.yaml
+++ b/boards/ti/cc1352r1_launchxl/cc1352r1_launchxl.yaml
@@ -7,7 +7,6 @@ flash: 352
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/ti/cc1352r1_launchxl/doc/index.rst b/boards/ti/cc1352r1_launchxl/doc/index.rst
index a908e1ceccc..73957926021 100644
--- a/boards/ti/cc1352r1_launchxl/doc/index.rst
+++ b/boards/ti/cc1352r1_launchxl/doc/index.rst
@@ -24,34 +24,7 @@ See the `TI CC1352R Product Page`_ for additional details.
 Supported Features
 ==================
 
-The CC1352R LaunchPad board configuration supports the following hardware
-features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PINMUX    | on-chip    | pinmux               |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-| AUX_ADC   | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| HWINFO    | on-chip    | hwinfo               |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -122,6 +95,8 @@ aligns with the LaunchPad standard.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Before flashing or debugging ensure the RESET, TMS, TCK, TDO, and TDI jumpers
 are in place. Also place jumpers on the TXD and RXD signals for a serial
 console using the XDS110 application serial port.
diff --git a/boards/ti/cc1352r_sensortag/cc1352r_sensortag.yaml b/boards/ti/cc1352r_sensortag/cc1352r_sensortag.yaml
index ab974002e38..dc07fa49190 100644
--- a/boards/ti/cc1352r_sensortag/cc1352r_sensortag.yaml
+++ b/boards/ti/cc1352r_sensortag/cc1352r_sensortag.yaml
@@ -7,7 +7,6 @@ flash: 352
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/ti/cc1352r_sensortag/doc/index.rst b/boards/ti/cc1352r_sensortag/doc/index.rst
index f31c744b7b7..6cedd6e2861 100644
--- a/boards/ti/cc1352r_sensortag/doc/index.rst
+++ b/boards/ti/cc1352r_sensortag/doc/index.rst
@@ -24,42 +24,7 @@ See the `TI CC1352R Product Page`_ for additional details.
 Supported Features
 ==================
 
-The CC1352R SensorTag board configuration supports the following hardware
-features:
-
-+-----------+------------+------------------+
-| Interface | Controller | Driver/Component |
-+===========+============+==================+
-| GPIO      | on-chip    | gpio             |
-+-----------+------------+------------------+
-| MPU       | on-chip    | arch/arm         |
-+-----------+------------+------------------+
-| NVIC      | on-chip    | arch/arm         |
-+-----------+------------+------------------+
-| PINMUX    | on-chip    | pinmux           |
-+-----------+------------+------------------+
-| UART      | on-chip    | serial           |
-+-----------+------------+------------------+
-| I2C       | on-chip    | i2c              |
-+-----------+------------+------------------+
-| SPI       | on-chip    | spi              |
-+-----------+------------+------------------+
-| AUX_ADC   | on-chip    | adc              |
-+-----------+------------+------------------+
-| DIO23     | off-chip   | DRV5032          |
-+-----------+------------+------------------+
-| I2C       | off-chip   | HDC2080          |
-+-----------+------------+------------------+
-| I2C       | off-chip   | OPT3001          |
-+-----------+------------+------------------+
-| SPI       | off-chip   | ADXL362          |
-+-----------+------------+------------------+
-| WDT       | on-chip    | watchdog         |
-+-----------+------------+------------------+
-| HWINFO    | on-chip    | hwinfo           |
-+-----------+------------+------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -130,6 +95,8 @@ aligns with the SensorTag standard.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 TI's supported method of programming and debugging the ``CC1352R SensorTag`` is
 to use it in tandem with a ``CC1352R LaunchPad``, making use of the integrated
 (XDS110) debugger and serial console over USB.
diff --git a/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl.yaml b/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl.yaml
index 1c2bd9d8876..7ae41f0cc03 100644
--- a/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl.yaml
+++ b/boards/ti/cc26x2r1_launchxl/cc26x2r1_launchxl.yaml
@@ -7,7 +7,6 @@ flash: 352
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - gpio
   - i2c
diff --git a/boards/ti/cc26x2r1_launchxl/doc/index.rst b/boards/ti/cc26x2r1_launchxl/doc/index.rst
index c08b2b9a933..037c55ab1d4 100644
--- a/boards/ti/cc26x2r1_launchxl/doc/index.rst
+++ b/boards/ti/cc26x2r1_launchxl/doc/index.rst
@@ -24,34 +24,7 @@ See the `TI CC2652R Product Page`_ for additional details.
 Supported Features
 ==================
 
-The CC26x2R LaunchPad board configuration supports the following hardware
-features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PINMUX    | on-chip    | pinmux               |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-| AUX_ADC   | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| HWINFO    | on-chip    | hwinfo               |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -128,6 +101,8 @@ aligns with the LaunchPad standard.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Before flashing or debugging ensure the RESET, TMS, TCK, TDO, and TDI jumpers
 are in place. Also place jumpers on the TXD and RXD signals for a serial
 console using the XDS110 application serial port.
diff --git a/boards/ti/cc3220sf_launchxl/cc3220sf_launchxl.yaml b/boards/ti/cc3220sf_launchxl/cc3220sf_launchxl.yaml
index 2158d5ec453..09b7343c4b3 100644
--- a/boards/ti/cc3220sf_launchxl/cc3220sf_launchxl.yaml
+++ b/boards/ti/cc3220sf_launchxl/cc3220sf_launchxl.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - netif:wifi
   - i2c
diff --git a/boards/ti/cc3220sf_launchxl/doc/index.rst b/boards/ti/cc3220sf_launchxl/doc/index.rst
index 6ff33afb88b..ef5a3ec6647 100644
--- a/boards/ti/cc3220sf_launchxl/doc/index.rst
+++ b/boards/ti/cc3220sf_launchxl/doc/index.rst
@@ -44,20 +44,7 @@ Complete details of the CC3220SF SoC can be found in the `CC3220 TRM`_.
 Supported Features
 ==================
 
-Zephyr has been ported to the Applications MCU, with basic peripheral
-driver support.
-
-+-----------+------------+-----------------------+
-| Interface | Controller | Driver/Component      |
-+===========+============+=======================+
-| UART      | on-chip    | serial port-interrupt |
-+-----------+------------+-----------------------+
-| GPIO      | on-chip    | gpio                  |
-+-----------+------------+-----------------------+
-| I2C       | on-chip    | i2c                   |
-+-----------+------------+-----------------------+
-| SPI_0     | on-chip    | Wi-Fi host driver     |
-+-----------+------------+-----------------------+
+.. zephyr:board-supported-hw::
 
 .. note::
 
@@ -71,6 +58,8 @@ accessible through the BoosterPack, are not currently supported.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 TI officially supports development on the CC3220SF using the TI
 `CC3220 SDK`_ on Windows and Linux using TI tools: Code Composer
 Studio for debugging and `UniFlash`_ for flashing.
diff --git a/boards/ti/cc3235sf_launchxl/cc3235sf_launchxl.yaml b/boards/ti/cc3235sf_launchxl/cc3235sf_launchxl.yaml
index 4761555359a..7f7e3a9cab3 100644
--- a/boards/ti/cc3235sf_launchxl/cc3235sf_launchxl.yaml
+++ b/boards/ti/cc3235sf_launchxl/cc3235sf_launchxl.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - netif:wifi
   - i2c
diff --git a/boards/ti/cc3235sf_launchxl/doc/index.rst b/boards/ti/cc3235sf_launchxl/doc/index.rst
index 7602a3b2712..d72920bbd55 100644
--- a/boards/ti/cc3235sf_launchxl/doc/index.rst
+++ b/boards/ti/cc3235sf_launchxl/doc/index.rst
@@ -47,17 +47,7 @@ Supported Features
 Zephyr has been ported to the Applications MCU, with basic peripheral
 driver support.
 
-+-----------+------------+-----------------------+
-| Interface | Controller | Driver/Component      |
-+===========+============+=======================+
-| UART      | on-chip    | serial port-interrupt |
-+-----------+------------+-----------------------+
-| GPIO      | on-chip    | gpio                  |
-+-----------+------------+-----------------------+
-| I2C       | on-chip    | i2c                   |
-+-----------+------------+-----------------------+
-| SPI_0     | on-chip    | Wi-Fi host driver     |
-+-----------+------------+-----------------------+
+.. zephyr:board-supported-hw::
 
 .. note::
 
@@ -71,6 +61,8 @@ accessible through the BoosterPack, are not currently supported.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 TI officially supports development on the CC3235SF using the TI
 `CC32xx SDK`_ on Windows and Linux using TI tools: Code Composer
 Studio for debugging and `UniFlash`_ for flashing.
diff --git a/boards/ti/lp_em_cc2340r5/Kconfig.lp_em_cc2340r5 b/boards/ti/lp_em_cc2340r5/Kconfig.lp_em_cc2340r5
new file mode 100644
index 00000000000..fbc90c7ebc8
--- /dev/null
+++ b/boards/ti/lp_em_cc2340r5/Kconfig.lp_em_cc2340r5
@@ -0,0 +1,7 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+# Copyright (c) 2024 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_LP_EM_CC2340R5
+	select SOC_CC2340R5
diff --git a/boards/ti/lp_em_cc2340r5/board.yml b/boards/ti/lp_em_cc2340r5/board.yml
new file mode 100644
index 00000000000..b698c52df85
--- /dev/null
+++ b/boards/ti/lp_em_cc2340r5/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: lp_em_cc2340r5
+  full_name: CC2340R5 LaunchPad
+  vendor: ti
+  socs:
+    - name: cc2340r5
diff --git a/boards/ti/lp_em_cc2340r5/boosterpack_connector.dtsi b/boards/ti/lp_em_cc2340r5/boosterpack_connector.dtsi
new file mode 100644
index 00000000000..f330b8c1e82
--- /dev/null
+++ b/boards/ti/lp_em_cc2340r5/boosterpack_connector.dtsi
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	boosterpack_header: connector {
+		compatible = "ti,boosterpack-header";
+		#gpio-cells = <2>;
+		gpio-map = <3 0 &gpio0 22 0>,
+			   <4 0 &gpio0 20 0>,
+			   <7 0 &gpio0 18 0>,
+			   <8 0 &gpio0 3 0>,
+			   <9 0 &gpio0 24 0>,
+			   <10 0 &gpio0 0 0>,
+
+			   <12 0 &gpio0 9 0>,
+			   <13 0 &gpio0 10 0>,
+			   <14 0 &gpio0 12 0>,
+			   <15 0 &gpio0 13 0>,
+			   <17 0 &gpio0 19 0>,
+			   <18 0 &gpio0 11 0>,
+
+			   <23 0 &gpio0 23 0>,
+			   <24 0 &gpio0 25 0>,
+			   <25 0 &gpio0 1 0>,
+			   <26 0 &gpio0 2 0>,
+			   <27 0 &gpio0 5 0>,
+			   <28 0 &gpio0 7 0>,
+
+			   <36 0 &gpio0 8 0>,
+			   <37 0 &gpio0 21 0>,
+			   <38 0 &gpio0 6 0>,
+			   <39 0 &gpio0 14 0>,
+			   <40 0 &gpio0 15 0>;
+	};
+};
diff --git a/boards/ti/lp_em_cc2340r5/doc/img/lp_em_cc2340r5.webp b/boards/ti/lp_em_cc2340r5/doc/img/lp_em_cc2340r5.webp
new file mode 100644
index 00000000000..df225cf6154
Binary files /dev/null and b/boards/ti/lp_em_cc2340r5/doc/img/lp_em_cc2340r5.webp differ
diff --git a/boards/ti/lp_em_cc2340r5/doc/index.rst b/boards/ti/lp_em_cc2340r5/doc/index.rst
new file mode 100644
index 00000000000..6878ac3d6aa
--- /dev/null
+++ b/boards/ti/lp_em_cc2340r5/doc/index.rst
@@ -0,0 +1,103 @@
+.. zephyr:board:: lp_em_cc2340r5
+
+Overview
+********
+
+The Texas Instruments CC2340R5 LaunchPad |trade| (LP_EM_CC2340R5) is a
+development kit for the SimpleLink |trade| multi-Standard CC2340R5 wireless MCU.
+
+See the `TI CC2340R5 LaunchPad Product Page`_ for details.
+
+Hardware
+********
+
+The CC2340R5 LaunchPad |trade| development kit features the CC2340R5 wireless MCU.
+The board is equipped with two LEDs, two push buttons and BoosterPack connectors
+for expansion.
+
+The CC2340R5 wireless MCU has a 48 MHz Arm |reg| Cortex |reg|-M0+ SoC and an
+integrated 2.4 GHz transceiver supporting multiple protocols including Bluetooth
+|reg| Low Energy and IEEE |reg| 802.15.4.
+
+See the `TI CC2340R5 Product Page`_ for additional details.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+All I/O signals are accessible from the BoosterPack connectors. Pin function
+aligns with the LaunchPad standard.
+
++-------+-----------+---------------------+
+| Pin   | Function  | Usage               |
++=======+===========+=====================+
+| DIO0  | GPIO      |                     |
++-------+-----------+---------------------+
+| DIO1  | ANALOG_IO | A4                  |
++-------+-----------+---------------------+
+| DIO2  | ANALOG_IO | A3                  |
++-------+-----------+---------------------+
+| DIO5  | ANALOG_IO | A5                  |
++-------+-----------+---------------------+
+| DIO6  | SPI_CSN   | SPI CS              |
++-------+-----------+---------------------+
+| DIO7  | ANALOG_IO | A0                  |
++-------+-----------+---------------------+
+| DIO8  | GPIO      |                     |
++-------+-----------+---------------------+
+| DIO9  | GPIO      | Button 2            |
++-------+-----------+---------------------+
+| DIO10 | GPIO      | Button 1            |
++-------+-----------+---------------------+
+| DIO11 | SPI_CSN   | SPI CS              |
++-------+-----------+---------------------+
+| DIO12 | SPI_POCI  | SPI POCI            |
++-------+-----------+---------------------+
+| DIO13 | SPI_PICO  | SPI_PICO            |
++-------+-----------+---------------------+
+| DIO14 | GPIO      | Red LED             |
++-------+-----------+---------------------+
+| DIO15 | GPIO      | Green LED           |
++-------+-----------+---------------------+
+| DIO18 | SPI_CLK   | SPI CLK             |
++-------+-----------+---------------------+
+| DIO19 | GPIO      |                     |
++-------+-----------+---------------------+
+| DIO20 | UART0_TX  | UART TX             |
++-------+-----------+---------------------+
+| DIO21 | GPIO      |                     |
++-------+-----------+---------------------+
+| DIO22 | UART0_RX  | UART RX             |
++-------+-----------+---------------------+
+| DIO23 | ANALOG_IO | A8                  |
++-------+-----------+---------------------+
+| DIO24 | ANALOG_IO | A7                  |
++-------+-----------+---------------------+
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+The LP_EM_CC2340R5 requires an external debug probe such as the LP-XDS110 or
+LP-XDS110ET.
+
+Currently there is no debug support in Zephyr for the LP_EM_CC2340R5, and the
+built binaries for this target must be flashed/debugged using either Uniflash
+or Code Composer Studio.
+
+References
+**********
+
+CC2340R5 LaunchPad Quick Start Guide:
+  https://www.ti.com/lit/pdf/swru588
+
+.. _TI CC2340R5 LaunchPad Product Page:
+   https://www.ti.com/tool/LP-EM-CC2340R5
+
+.. _TI CC2340R5 Product Page:
+   https://www.ti.com/product/CC2340R5
diff --git a/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5-pinctrl.dtsi b/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5-pinctrl.dtsi
new file mode 100644
index 00000000000..eb19f89888f
--- /dev/null
+++ b/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5-pinctrl.dtsi
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/cc23x0-pinctrl.h>
+
+&pinctrl {
+	/* UART0 */
+	uart0_tx_default: uart0_tx_default {
+		pinmux = <20 DIO20_UART0_TXD>;
+		bias-disable;
+	};
+
+	uart0_rx_default: uart0_rx_default {
+		pinmux = <22 DIO22_UART0_RXD>;
+		bias-disable;
+		input-enable;
+	};
+
+	/* SPI0 */
+	spi0_sck_default: spi0_sck_default {
+		pinmux = <18 DIO18_SPI0_SCLK>;
+		bias-disable;
+	};
+
+	spi0_mosi_default: spi0_mosi_default {
+		pinmux = <13 DIO13_SPI0_MOSI>;
+		bias-disable;
+	};
+
+	spi0_miso_default: spi0_miso_default {
+		pinmux = <12 DIO12_SPI0_MISO>;
+		bias-disable;
+		input-enable;
+	};
+
+	spi0_cs_default: spi0_cs_default {
+		pinmux = <11 DIO11_SPI0_CSN>;
+		bias-disable;
+	};
+};
diff --git a/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5.dts b/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5.dts
new file mode 100644
index 00000000000..90288e5ba8f
--- /dev/null
+++ b/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5.dts
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <ti/cc2340r5.dtsi>
+#include "boosterpack_connector.dtsi"
+#include "lp_em_cc2340r5-pinctrl.dtsi"
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "LP_EM_CC2340R5";
+	compatible = "ti,lp_em_cc2340r5";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		sw0 = &btn0;
+		sw1 = &btn1;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led_0 {
+			gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>;
+			label = "Green LED";
+		};
+
+		led1: led_1 {
+			gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
+			label = "Red LED";
+		};
+	};
+
+	keys {
+		compatible = "gpio-keys";
+
+		btn0: btn_0 {
+			gpios = <&gpio0 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			label = "Button 1";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		btn1: btn_1 {
+			gpios = <&gpio0 9 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			label = "Button 2";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart0_rx_default &uart0_tx_default>;
+	pinctrl-names = "default";
+};
+
+&aes {
+	status = "okay";
+};
+
+&dma {
+	status = "okay";
+};
+
+&spi0 {
+	status = "okay";
+	pinctrl-0 = <&spi0_sck_default
+		     &spi0_mosi_default
+		     &spi0_miso_default
+		     &spi0_cs_default>;
+	pinctrl-names = "default";
+};
diff --git a/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5.yaml b/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5.yaml
new file mode 100644
index 00000000000..29cda9cc239
--- /dev/null
+++ b/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5.yaml
@@ -0,0 +1,13 @@
+identifier: lp_em_cc2340r5
+name: TI SimpleLink CC2340R5 LaunchPad
+type: mcu
+arch: arm
+ram: 80
+flash: 512
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - uart
+vendor: ti
diff --git a/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5_defconfig b/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5_defconfig
new file mode 100644
index 00000000000..7f9b629c25f
--- /dev/null
+++ b/boards/ti/lp_em_cc2340r5/lp_em_cc2340r5_defconfig
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+# Copyright (c) 2024 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_GPIO=y
+CONFIG_SERIAL=y
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/ti/msp_exp432p401r_launchxl/doc/index.rst b/boards/ti/msp_exp432p401r_launchxl/doc/index.rst
index 7b0662d6622..61598eb8201 100644
--- a/boards/ti/msp_exp432p401r_launchxl/doc/index.rst
+++ b/boards/ti/msp_exp432p401r_launchxl/doc/index.rst
@@ -24,30 +24,20 @@ MSP-EXP432P401R LaunchXL User's Guide.
 Supported Features
 ==================
 
+.. zephyr:board-supported-hw::
+
 * The on-board 32-kHz crystal allows for lower LPM3 sleep currents and a higher-precision clock source than the
   default internal 32-kHz REFOCLK. Therefore, the presence of the crystal allows the full range of low-power
   modes to be used.
 * The on-board 48-MHz crystal allows the device to run at its maximum operating speed for MCLK and HSMCLK.
 
-The MSP-EXP432P401R LaunchXL development board configuration supports the following hardware features:
-
-+-----------+------------+-----------------------+
-| Interface | Controller | Driver/Component      |
-+===========+============+=======================+
-| NVIC      | on-chip    | nested vectored       |
-|           |            | interrupt controller  |
-+-----------+------------+-----------------------+
-| SYSTICK   | on-chip    | system clock          |
-+-----------+------------+-----------------------+
-| UART      | on-chip    | serial port           |
-+-----------+------------+-----------------------+
-
-More details about the supported peripherals are available in MSP432P4XX TRM
-Other hardware features are not currently supported by the Zephyr kernel.
+More details about the supported peripherals are available in MSP432P4XX TRM.
 
 Building and Flashing
 *********************
 
+.. zephyr:board-supported-runners::
+
 Prerequisites:
 ==============
 
diff --git a/boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.yaml b/boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.yaml
index c60f1b65de8..ac50b615de7 100644
--- a/boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.yaml
+++ b/boards/ti/msp_exp432p401r_launchxl/msp_exp432p401r_launchxl.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 256
 vendor: ti
diff --git a/boards/ti/sk_am62/doc/index.rst b/boards/ti/sk_am62/doc/index.rst
index 5e6cab8439f..248c16e66b6 100644
--- a/boards/ti/sk_am62/doc/index.rst
+++ b/boards/ti/sk_am62/doc/index.rst
@@ -33,21 +33,7 @@ the M4F core and the following listed hardware specifications are used:
 Supported Features
 ==================
 
-The sk_am62 configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| PINCTRL   | on-chip    | pinctrl                             |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial                              |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 Devices
 ========
diff --git a/boards/ti/sk_am62/sk_am62_am6234_m4.dts b/boards/ti/sk_am62/sk_am62_am6234_m4.dts
index 0c3ea26e033..85688607d5d 100644
--- a/boards/ti/sk_am62/sk_am62_am6234_m4.dts
+++ b/boards/ti/sk_am62/sk_am62_am6234_m4.dts
@@ -16,7 +16,8 @@
 		zephyr,sram = &sram0;
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
-		zephyr,sram1 = &ddr0;
+		zephyr,ipc_shm = &ddr0;
+		zephyr,sram1 = &ddr1;
 	};
 
 	cpus {
@@ -26,9 +27,20 @@
 		};
 	};
 
-	ddr0:memory@9CC00000{
+	ddr0: memory@9cb00000 {
+		compatible = "mmio-sram";
+		reg = <0x9cb00000 DT_SIZE_M(1)>;
+	};
+
+	rsc_table: memory@9cc00000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x9cc00000 DT_SIZE_K(4)>;
+		zephyr,memory-region = "RSC_TABLE";
+	};
+
+	ddr1: memory@9cc01000 {
 		compatible = "zephyr,memory-region", "mmio-sram";
-		reg = <0x9CC00000 DT_SIZE_K(4)>;
+		reg = <0x9cc01000 (DT_SIZE_M(15) - DT_SIZE_K(4))>;
 		zephyr,memory-region = "DDR";
 	};
 };
diff --git a/boards/ti/sk_am64/Kconfig.sk_am64 b/boards/ti/sk_am64/Kconfig.sk_am64
new file mode 100644
index 00000000000..5def92ea569
--- /dev/null
+++ b/boards/ti/sk_am64/Kconfig.sk_am64
@@ -0,0 +1,8 @@
+# Texas Instruments SK-AM64
+#
+# Copyright (c) 2025 Texas Instruments Incorporated
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_SK_AM64
+	select SOC_AM6442_M4 if BOARD_SK_AM64_AM6442_M4
diff --git a/boards/ti/sk_am64/board.yml b/boards/ti/sk_am64/board.yml
new file mode 100644
index 00000000000..1e6242f45cb
--- /dev/null
+++ b/boards/ti/sk_am64/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: sk_am64
+  full_name: SK-AM64
+  vendor: ti
+  socs:
+  - name: am6442
diff --git a/boards/ti/sk_am64/doc/assets/sk_am64.webp b/boards/ti/sk_am64/doc/assets/sk_am64.webp
new file mode 100644
index 00000000000..ef86e8dab0d
Binary files /dev/null and b/boards/ti/sk_am64/doc/assets/sk_am64.webp differ
diff --git a/boards/ti/sk_am64/doc/index.rst b/boards/ti/sk_am64/doc/index.rst
new file mode 100644
index 00000000000..fa87ea3590c
--- /dev/null
+++ b/boards/ti/sk_am64/doc/index.rst
@@ -0,0 +1,120 @@
+.. zephyr:board:: sk_am64
+
+Overview
+********
+
+The SK-AM64 board configuration is used by Zephyr applications that run on
+the TI AM64x platform. The board configuration provides support for the ARM
+Cortex-M4F MCU core and the following features:
+
+- Nested Vector Interrupt Controller (NVIC)
+- System Tick System Clock (SYSTICK)
+
+The board configuration also enables support for the semihosting debugging console.
+
+See the `TI AM64 Product Page`_ for details.
+
+Hardware
+********
+The SK-AM64 EVM features the AM64 SoC, which is composed of a dual Cortex-A53
+cluster and a single Cortex-M4 core in the MCU domain. Zephyr is ported to run on
+the M4F core and the following listed hardware specifications are used:
+
+- Low-power ARM Cortex-M4F
+- Memory
+
+   - 256KB of SRAM
+   - 2GB of DDR4
+
+- Debug
+
+   - XDS110 based JTAG
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Devices
+========
+System Clock
+------------
+
+This board configuration uses a system clock frequency of 400 MHz.
+
+DDR RAM
+-------
+
+The board has 2GB of DDR RAM available. This board configuration
+allocates Zephyr 4kB of RAM (only for resource table: 0xa4100000 to 0xa4100400).
+
+Serial Port
+-----------
+
+This board configuration uses a single serial communication channel with the
+MCU domain UART (MCU_UART0).
+
+GPIO
+----
+
+The SK-AM64 has a heartbeat LED connected to MCU_GPIO0_6. It's configured
+to build and run the :zephyr:code-sample:`blinky` sample.
+
+SD Card
+*******
+
+Download TI's official `WIC`_ and flash the WIC file with an etching software
+onto an SD card. This will boot Linux on the A53 application cores of the EVM.
+These cores will then load the zephyr binary on the M4 core using remoteproc.
+
+The default configuration can be found in
+:zephyr_file:`boards/ti/sk_am64/sk_am64_am6442_m4_defconfig`
+
+Flashing
+********
+
+The board can using remoteproc, and uses the OpenAMP resource table to accomplish this.
+
+The testing requires the binary to be copied to the SD card to allow the A53 cores to load it while booting using remoteproc.
+
+To test the M4F core, we build the :zephyr:code-sample:`hello_world` sample with the following command.
+
+.. code-block:: console
+
+   # From the root of the Zephyr repository
+   west build -p -b sk_am64/am6442/m4 samples/hello_world
+
+This builds the program and the binary is present in the :file:`build/zephyr` directory as
+:file:`zephyr.elf`.
+
+We now copy this binary onto the SD card in the :file:`/lib/firmware` directory and name it as
+:file:`am64-mcu-m4f0_0-fw`.
+
+.. code-block:: console
+
+   # Mount the SD card at sdcard for example
+   sudo mount /dev/sdX sdcard
+   # copy the elf to the /lib/firmware directory
+   sudo cp --remove-destination zephyr.elf sdcard/lib/firmware/am64-mcu-m4f0_0-fw
+
+The SD card can now be used for booting. The binary will now be loaded onto the M4F core on boot.
+
+To allow the board to boot using the SD card, set the boot pins to the SD Card boot mode. Refer to `SK-AM64B EVM User's Guide`_.
+
+After changing the boot mode, the board should go through the boot sequence on powering up.
+The binary will run and print Hello world to the MCU_UART0 port.
+
+References
+**********
+
+.. _TI AM64 Product Page:
+   https://www.ti.com/product/AM6442
+
+.. _WIC:
+   https://dr-download.ti.com/software-development/software-development-kit-sdk/MD-yXgchBCk98/10.01.10.04/tisdk-default-image-am64xx-evm-10.01.10.04.rootfs.wic.xz
+
+.. _SK-AM64B EVM User's Guide:
+   https://www.ti.com/lit/ug/spruj64/spruj64.pdf
+
+.. _build OpenOCD from source:
+   https://docs.u-boot.org/en/latest/board/ti/k3.html#building-openocd-from-source
diff --git a/boards/ti/sk_am64/sk_am64_am6442_m4-pinctrl.dtsi b/boards/ti/sk_am64/sk_am64_am6442_m4-pinctrl.dtsi
new file mode 100644
index 00000000000..034c627336e
--- /dev/null
+++ b/boards/ti/sk_am64/sk_am64_am6442_m4-pinctrl.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025 Texas Instruments Incorporated
+ *	Andrew Davis <afd@ti.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
+
+&pinctrl {
+	mcu_uart0_rx_default: mcu_uart0_rx_default {
+		pinmux = <K3_PINMUX(0x028, PIN_INPUT, MUX_MODE_0)>; /* (A9) MCU_UART0_RXD */
+	};
+
+	mcu_uart0_tx_default: mcu_uart0_tx_default {
+		pinmux = <K3_PINMUX(0x002C, PIN_OUTPUT, MUX_MODE_0)>; /* (A8) MCU_UART0_TXD */
+	};
+
+	mcu_gpio0_led_default: mcu_gpio0_led_default {
+		pinmux = <K3_PINMUX(0x0014, PIN_INPUT, MUX_MODE_7)>; /* (A7) MCU_GPIO0_5 */
+	};
+};
diff --git a/boards/ti/sk_am64/sk_am64_am6442_m4.dts b/boards/ti/sk_am64/sk_am64_am6442_m4.dts
new file mode 100644
index 00000000000..93073c26e73
--- /dev/null
+++ b/boards/ti/sk_am64/sk_am64_am6442_m4.dts
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ *	Andrew Davis <afd@ti.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <ti/am64x_m4.dtsi>
+#include "sk_am64_am6442_m4-pinctrl.dtsi"
+
+/ {
+	model = "TI AM64x STARTER KIT (SK) M4";
+	compatible = "ti,am64x_m4_sk", "ti,am6442";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,ipc = &ipc0;
+		zephyr,ipc_shm = &ddr0;
+	};
+
+	aliases {
+		led0 = &heartbeat_led;
+	};
+
+	cpus {
+		cpu@0 {
+			status = "okay";
+			clock-frequency = <DT_FREQ_M(400)>;
+		};
+	};
+
+	ddr0: memory@a4000000 {
+		compatible = "mmio-sram";
+		reg = <0xa4000000 DT_SIZE_M(1)>;
+	};
+
+	rsc_table: memory@a4100000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0xa4100000 DT_SIZE_K(4)>;
+		zephyr,memory-region = "RSC_TABLE";
+	};
+
+	ddr1: memory@a4200000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0xa4200000 (DT_SIZE_M(15) - DT_SIZE_K(4))>;
+		zephyr,memory-region = "DDR";
+	};
+
+	leds: leds {
+		compatible = "gpio-leds";
+
+		heartbeat_led: led_0 {
+			gpios = <&gpio0 5 GPIO_ACTIVE_HIGH>;
+			label = "Heartbeat LED";
+		};
+	};
+
+	ipc0: ipc {
+		compatible = "zephyr,mbox-ipm";
+		mboxes = <&mbox6 0>, <&mbox6 1>;
+		mbox-names = "tx", "rx";
+	};
+};
+
+&uart0 {
+	current-speed = <115200>;
+	pinctrl-0 = <&mcu_uart0_rx_default &mcu_uart0_tx_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&gpio0 {
+	pinctrl-0 = <&mcu_gpio0_led_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/boards/ti/sk_am64/sk_am64_am6442_m4.yaml b/boards/ti/sk_am64/sk_am64_am6442_m4.yaml
new file mode 100644
index 00000000000..88d628dd688
--- /dev/null
+++ b/boards/ti/sk_am64/sk_am64_am6442_m4.yaml
@@ -0,0 +1,8 @@
+identifier: sk_am64/am6442/m4
+name: TI AM64X M4 Starter Kit (SK)
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+ram: 192
+vendor: ti
diff --git a/boards/ti/sk_am64/sk_am64_am6442_m4_defconfig b/boards/ti/sk_am64/sk_am64_am6442_m4_defconfig
new file mode 100644
index 00000000000..6f8f05cb1f7
--- /dev/null
+++ b/boards/ti/sk_am64/sk_am64_am6442_m4_defconfig
@@ -0,0 +1,20 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+#	Andrew Davis <afd@ti.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Platform Configuration
+CONFIG_CORTEX_M_SYSTICK=y
+
+# Zephyr Kernel Configuration
+CONFIG_XIP=n
+
+# Serial Driver
+CONFIG_SERIAL=y
+
+# GPIO Driver
+CONFIG_GPIO=y
+
+# Enable Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.yaml b/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.yaml
index d28eccc9d2b..616be08775c 100644
--- a/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.yaml
+++ b/boards/toradex/colibri_imx7d/colibri_imx7d_mcimx7d_m4.yaml
@@ -13,7 +13,6 @@ flash: 32
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 testing:
   ignore_tags:
     - net
diff --git a/boards/toradex/colibri_imx7d/doc/index.rst b/boards/toradex/colibri_imx7d/doc/index.rst
index ea36ff6b50b..10f0b732a21 100644
--- a/boards/toradex/colibri_imx7d/doc/index.rst
+++ b/boards/toradex/colibri_imx7d/doc/index.rst
@@ -125,6 +125,8 @@ the remaining are not used/tested.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The Colibri iMX7D doesn't have QSPI flash for the M4 and it needs to be started by
 the A7 core. The A7 core is responsible to load the M4 binary application into the
 RAM, put the M4 in reset, set the M4 Program Counter and Stack Pointer, and get
diff --git a/boards/toradex/verdin_imx8mm/doc/index.rst b/boards/toradex/verdin_imx8mm/doc/index.rst
index 112596322bc..9ae5e807b40 100644
--- a/boards/toradex/verdin_imx8mm/doc/index.rst
+++ b/boards/toradex/verdin_imx8mm/doc/index.rst
@@ -132,6 +132,8 @@ The M4 Core is configured to run at a 400 MHz clock speed.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The i.MX8MM doesn't have QSPI flash for the M4 and it needs
 to be started by the A53 core. The A53 core is responsible to load the M4 binary
 application into the RAM, putting the M4 in reset, setting the M4 Program Counter and
diff --git a/boards/toradex/verdin_imx8mm/verdin_imx8mm_mimx8mm6_m4.yaml b/boards/toradex/verdin_imx8mm/verdin_imx8mm_mimx8mm6_m4.yaml
index dc6f24f56d0..b002b13dd54 100644
--- a/boards/toradex/verdin_imx8mm/verdin_imx8mm_mimx8mm6_m4.yaml
+++ b/boards/toradex/verdin_imx8mm/verdin_imx8mm_mimx8mm6_m4.yaml
@@ -13,7 +13,6 @@ flash: 128
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 testing:
   ignore_tags:
     - net
diff --git a/boards/toradex/verdin_imx8mp/doc/index.rst b/boards/toradex/verdin_imx8mp/doc/index.rst
index af78ea49808..cc99a1e7735 100644
--- a/boards/toradex/verdin_imx8mp/doc/index.rst
+++ b/boards/toradex/verdin_imx8mp/doc/index.rst
@@ -172,6 +172,8 @@ used/tested.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The Verdin iMX8M Plus board doesn't have QSPI flash for the M7, and it needs to be started by the
 A53 core. The A53 core is responsible to load the M7 binary application into the RAM, put the M7 in
 reset, set the M7 Program Counter and Stack Pointer, and get the M7 out of reset. The A53 can
diff --git a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.yaml b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.yaml
index e4e77056bc0..cd1e458f684 100644
--- a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.yaml
+++ b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7.yaml
@@ -13,6 +13,5 @@ flash: 128
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - uart
diff --git a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.yaml b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.yaml
index 979dbfa498d..5ba25e228c8 100644
--- a/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.yaml
+++ b/boards/toradex/verdin_imx8mp/verdin_imx8mp_mimx8ml8_m7_ddr.yaml
@@ -13,6 +13,5 @@ flash: 2048
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - uart
diff --git a/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.yaml b/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.yaml
index 910642809d6..9f77ebe0689 100644
--- a/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.yaml
+++ b/boards/u-blox/ubx_bmd300eval/ubx_bmd300eval_nrf52832.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 512
 supported:
diff --git a/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval.yaml b/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval.yaml
index 50d337f1c35..5b7c00f0cc0 100644
--- a/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval.yaml
+++ b/boards/u-blox/ubx_bmd330eval/ubx_bmd330eval.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 24
 flash: 192
 supported:
diff --git a/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.yaml b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.yaml
index eeca79d1e5e..cacac6dc2b3 100644
--- a/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.yaml
+++ b/boards/u-blox/ubx_bmd340eval/ubx_bmd340eval_nrf52840.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - arduino_gpio
diff --git a/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.yaml b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.yaml
index f79940dbbbd..ca5ec522464 100644
--- a/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.yaml
+++ b/boards/u-blox/ubx_bmd345eval/ubx_bmd345eval_nrf52840.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - arduino_i2c
diff --git a/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.yaml b/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.yaml
index 4df9c1172f0..96820eeef2b 100644
--- a/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.yaml
+++ b/boards/u-blox/ubx_bmd360eval/ubx_bmd360eval_nrf52811.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 24
 flash: 192
 supported:
diff --git a/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.yaml b/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.yaml
index a794a4cac05..31e23654cef 100644
--- a/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.yaml
+++ b/boards/u-blox/ubx_bmd380eval/ubx_bmd380eval_nrf52840.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - ble
diff --git a/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.yaml b/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.yaml
index 54af92298d8..2e3748675c1 100644
--- a/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.yaml
+++ b/boards/u-blox/ubx_evkannab1/ubx_evkannab1_nrf52832.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 512
 supported:
diff --git a/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.yaml b/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.yaml
index 286e66b97cb..f1ea3c44ad5 100644
--- a/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.yaml
+++ b/boards/u-blox/ubx_evkninab1/ubx_evkninab1_nrf52832.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 512
 supported:
diff --git a/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.yaml b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.yaml
index 6e01ef035e8..8aad52f8b22 100644
--- a/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.yaml
+++ b/boards/u-blox/ubx_evkninab3/ubx_evkninab3_nrf52840.yaml
@@ -7,7 +7,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - arduino_gpio
diff --git a/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.yaml b/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.yaml
index f7f8cb355a9..a89676bfefa 100644
--- a/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.yaml
+++ b/boards/u-blox/ubx_evkninab4/ubx_evkninab4_nrf52833.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - arduino_gpio
diff --git a/boards/udoo/udoo_neo_full/doc/index.rst b/boards/udoo/udoo_neo_full/doc/index.rst
index 3c9dd90e214..4a2f49ab800 100644
--- a/boards/udoo/udoo_neo_full/doc/index.rst
+++ b/boards/udoo/udoo_neo_full/doc/index.rst
@@ -106,29 +106,7 @@ see these references:
 Supported Features
 ==================
 
-The UDOO Neo Full board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| SYSTICK   | on-chip    | systick                             |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | general purpose input/output        |
-+-----------+------------+-------------------------------------+
-| COUNTER   | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-
-	:zephyr_file:`boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4_defconfig`
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -160,6 +138,8 @@ remaining are used by the A9 core or not used.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The M4 core does not have a flash memory and is not provided a clock
 at power-on-reset. Therefore it needs to be started by the A9 core.
 The A9 core is responsible to load the M4 binary application into the RAM,
diff --git a/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.yaml b/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.yaml
index 4fdd6493309..6a1ee179451 100644
--- a/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.yaml
+++ b/boards/udoo/udoo_neo_full/udoo_neo_full_mcimx6x_m4.yaml
@@ -13,7 +13,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - gpio
diff --git a/boards/up-bridge-the-gap/up_squared/doc/index.rst b/boards/up-bridge-the-gap/up_squared/doc/index.rst
index 62166f2ef38..9acd231d20e 100644
--- a/boards/up-bridge-the-gap/up_squared/doc/index.rst
+++ b/boards/up-bridge-the-gap/up_squared/doc/index.rst
@@ -1,7 +1,4 @@
-.. _up_squared:
-
-UP Squared
-##########
+.. zephyr:board:: up_squared
 
 Overview
 ********
@@ -11,12 +8,6 @@ performance and low power consumption. It features the latest Intel |reg| Apollo
 Lake Celeron |trade| and Pentium |trade| Processors with only 4W of Scenario Design Power and
 a powerful and flexible Intel |reg| FPGA Altera MAX 10 onboard.
 
-.. figure:: img/up_squared.jpg
-   :align: center
-   :alt: UP Squared
-
-   Up Squared (Credit: https://up-board.org)
-
 This board configuration enables kernel support for the `UP Squared`_ board.
 
 .. note::
@@ -53,6 +44,8 @@ for connection diagrams.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Use the following procedures for booting an image on a UP Squared board.
 
 .. contents::
diff --git a/boards/up-bridge-the-gap/up_squared_pro_7000/doc/up_squared_pro_7000.rst b/boards/up-bridge-the-gap/up_squared_pro_7000/doc/up_squared_pro_7000.rst
index 1b2d6bace7b..d3f1fc7cc10 100644
--- a/boards/up-bridge-the-gap/up_squared_pro_7000/doc/up_squared_pro_7000.rst
+++ b/boards/up-bridge-the-gap/up_squared_pro_7000/doc/up_squared_pro_7000.rst
@@ -1,9 +1,4 @@
-:orphan:
-
-.. _up_squared_pro_7000_board:
-
-UP Squared Pro 7000
-###################
+.. zephyr:board:: up_squared_pro_7000
 
 Overview
 ********
@@ -30,6 +25,8 @@ Refer to the `UP Squared Pro 7000`_ website for more information.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Use the following procedures for booting an image for an UP Squared Pro 7000 board.
 
 .. contents::
diff --git a/boards/vcc-gnd/yd_esp32/doc/index.rst b/boards/vcc-gnd/yd_esp32/doc/index.rst
index 425c11c69f0..af9e54c5a65 100644
--- a/boards/vcc-gnd/yd_esp32/doc/index.rst
+++ b/boards/vcc-gnd/yd_esp32/doc/index.rst
@@ -50,45 +50,7 @@ manual at `ESP32 Technical Reference Manual`_.
 Supported Features
 ==================
 
-Current Zephyr's YD-ESP32 board supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| MCPWM      | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| PCNT       | on-chip    | qdec                                |
-+------------+------------+-------------------------------------+
-| SPI DMA    | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| TWAI       | on-chip    | can                                 |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | adc                                 |
-+------------+------------+-------------------------------------+
-| DAC        | on-chip    | dac                                 |
-+------------+------------+-------------------------------------+
-| Wi-Fi      | on-chip    |                                     |
-+------------+------------+-------------------------------------+
-| Bluetooth  | on-chip    |                                     |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 System requirements
 ===================
@@ -110,6 +72,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_appcpu_defconfig b/boards/vcc-gnd/yd_esp32/yd_esp32_appcpu_defconfig
index 9abf2ff0430..48546641cad 100644
--- a/boards/vcc-gnd/yd_esp32/yd_esp32_appcpu_defconfig
+++ b/boards/vcc-gnd/yd_esp32/yd_esp32_appcpu_defconfig
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.dts b/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.dts
index 119e18f222f..b0d7cd944e3 100644
--- a/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.dts
+++ b/boards/vcc-gnd/yd_esp32/yd_esp32_procpu.dts
@@ -140,3 +140,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/vcc-gnd/yd_esp32/yd_esp32_procpu_defconfig b/boards/vcc-gnd/yd_esp32/yd_esp32_procpu_defconfig
index 4fc7d44e085..19979ff26ad 100644
--- a/boards/vcc-gnd/yd_esp32/yd_esp32_procpu_defconfig
+++ b/boards/vcc-gnd/yd_esp32/yd_esp32_procpu_defconfig
@@ -1,8 +1,6 @@
 # Copyright (c) 2023 Julio Cesar <hi@jcsx.dev>
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/vcc-gnd/yd_stm32h750vb/doc/index.rst b/boards/vcc-gnd/yd_stm32h750vb/doc/index.rst
index d11a7e24730..8ce686dc509 100644
--- a/boards/vcc-gnd/yd_stm32h750vb/doc/index.rst
+++ b/boards/vcc-gnd/yd_stm32h750vb/doc/index.rst
@@ -16,27 +16,7 @@ More information about STM32H750 can be found here:
 Supported Features
 ==================
 
-The current Zephyr YD-STM32H750VB board supports the following features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| CLOCK     | on-chip    | reset and clock control             |
-+-----------+------------+-------------------------------------+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port-polling;                |
-|           |            | serial port-interrupt               |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on Zephyr porting.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -62,6 +42,8 @@ is driven by the PLL clock at 480MHz. PLL clock is feed by a 25MHz high speed ex
 Flashing
 ========
 
+.. zephyr:board-supported-runners::
+
 There are 2 main entry points for flashing STM32H750VB SoCs, one using the ROM
 bootloader, and another by using the SWD debug port (which requires additional
 hardware such as ST-Link). Flashing using the ROM bootloader requires a special activation
diff --git a/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.yaml b/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.yaml
index 0ce537a1bd4..fc7d992e2af 100644
--- a/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.yaml
+++ b/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 1024
 flash: 128
 supported:
diff --git a/boards/vngiotlab/nrf51_vbluno51/doc/index.rst b/boards/vngiotlab/nrf51_vbluno51/doc/index.rst
index ad9db23a69e..eac9d110bd2 100644
--- a/boards/vngiotlab/nrf51_vbluno51/doc/index.rst
+++ b/boards/vngiotlab/nrf51_vbluno51/doc/index.rst
@@ -86,6 +86,8 @@ More details
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``nrf51_vbluno51`` board configuration can be
 built and flashed in the usual way (see :ref:`build_an_application`
 and :ref:`application_run` for more details).
diff --git a/boards/vngiotlab/nrf51_vbluno51/nrf51_vbluno51.yaml b/boards/vngiotlab/nrf51_vbluno51/nrf51_vbluno51.yaml
index 7e8cb981eee..f389f34e77d 100644
--- a/boards/vngiotlab/nrf51_vbluno51/nrf51_vbluno51.yaml
+++ b/boards/vngiotlab/nrf51_vbluno51/nrf51_vbluno51.yaml
@@ -5,5 +5,4 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
diff --git a/boards/vngiotlab/nrf52_vbluno52/doc/index.rst b/boards/vngiotlab/nrf52_vbluno52/doc/index.rst
index 2c710421a64..fc1c788fe3d 100644
--- a/boards/vngiotlab/nrf52_vbluno52/doc/index.rst
+++ b/boards/vngiotlab/nrf52_vbluno52/doc/index.rst
@@ -25,31 +25,7 @@ is 64 MHz.
 Supported Features
 ==================
 
-The nrf52_vbluno52 board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| NVIC      | on-chip    | nested vectored      |
-|           |            | interrupt controller |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial port          |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
-| I2C       | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| SPI       | on-chip    | spi                  |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -67,6 +43,8 @@ Push buttons
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/vngiotlab/nrf52_vbluno52/nrf52_vbluno52.yaml b/boards/vngiotlab/nrf52_vbluno52/nrf52_vbluno52.yaml
index dd9971acc31..408109bcd5f 100644
--- a/boards/vngiotlab/nrf52_vbluno52/nrf52_vbluno52.yaml
+++ b/boards/vngiotlab/nrf52_vbluno52/nrf52_vbluno52.yaml
@@ -5,6 +5,5 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 512
diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/doc/index.rst b/boards/waveshare/esp32s3_touch_lcd_1_28/doc/index.rst
index 540ac8a68e6..b9cab2da1d1 100644
--- a/boards/waveshare/esp32s3_touch_lcd_1_28/doc/index.rst
+++ b/boards/waveshare/esp32s3_touch_lcd_1_28/doc/index.rst
@@ -57,37 +57,7 @@ manual at `ESP32-S3 Technical Reference Manual`_.
 Supported Features
 ==================
 
-Current Zephyr's ESP32-S3-Touch-LCD-1.28 board supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| TWAI/CAN   | on-chip    | can                                 |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | adc                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| MCPWM      | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| PCNT       | on-chip    | qdec                                |
-+------------+------------+-------------------------------------+
-| GDMA       | on-chip    | dma                                 |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 Prerequisites
 -------------
@@ -106,6 +76,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu.dts b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu.dts
index 53d70cdc115..e0b45b9ee0a 100644
--- a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu.dts
+++ b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu.dts
@@ -5,7 +5,7 @@
 
 /dts-v1/;
 #include <espressif/esp32s3/esp32s3_r2.dtsi>
-#include <espressif/partitions_0x0_amp.dtsi>
+#include <espressif/partitions_0x0_amp_16M.dtsi>
 
 / {
 	model = "ESP32-S3-Touch-LCD-1.28 APPCPU";
diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu_defconfig b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu_defconfig
index 15e93d6bf4a..6a13f9c9e39 100644
--- a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu_defconfig
+++ b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_appcpu_defconfig
@@ -1,5 +1,4 @@
 # Copyright (c) 2024 Joel Guittet
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_CLOCK_CONTROL=y
diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.dts b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.dts
index 55bd4f1e929..3b502f41609 100644
--- a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.dts
+++ b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu.dts
@@ -9,7 +9,7 @@
 #include <zephyr/dt-bindings/display/panel.h>
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 #include <zephyr/dt-bindings/pwm/pwm.h>
-#include <espressif/partitions_0x0_amp.dtsi>
+#include <espressif/partitions_0x0_amp_16M.dtsi>
 
 / {
 	model = "ESP32-S3-Touch-LCD-1.28 PROCPU";
@@ -74,7 +74,7 @@
 			compatible = "galaxycore,gc9x01x";
 			reg = <0>;
 			mipi-max-frequency = <100000000>;
-			pixel-format = <PANEL_PIXEL_FORMAT_RGB_888>;
+			pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
 			display-inversion;
 			width = <240>;
 			height = <240>;
@@ -157,3 +157,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu_defconfig b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu_defconfig
index 50c7db47465..a763fa8944d 100644
--- a/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu_defconfig
+++ b/boards/waveshare/esp32s3_touch_lcd_1_28/esp32s3_touch_lcd_1_28_esp32s3_procpu_defconfig
@@ -1,7 +1,6 @@
 # Copyright (c) 2024 Joel Guittet
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
 CONFIG_GPIO=y
 CONFIG_REGULATOR=y
 CONFIG_CONSOLE=y
diff --git a/boards/waveshare/nrf51_ble400/doc/index.rst b/boards/waveshare/nrf51_ble400/doc/index.rst
index 5dd3034f9ca..06c8dabe436 100644
--- a/boards/waveshare/nrf51_ble400/doc/index.rst
+++ b/boards/waveshare/nrf51_ble400/doc/index.rst
@@ -156,6 +156,8 @@ UART (USB)
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/waveshare/nrf51_ble400/nrf51_ble400.yaml b/boards/waveshare/nrf51_ble400/nrf51_ble400.yaml
index 93c73fcd84f..681d32ac532 100644
--- a/boards/waveshare/nrf51_ble400/nrf51_ble400.yaml
+++ b/boards/waveshare/nrf51_ble400/nrf51_ble400.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
 supported:
   - ble
diff --git a/boards/waveshare/open103z/doc/index.rst b/boards/waveshare/open103z/doc/index.rst
index 0ba052cc623..9a77af08f4f 100644
--- a/boards/waveshare/open103z/doc/index.rst
+++ b/boards/waveshare/open103z/doc/index.rst
@@ -16,33 +16,13 @@ The Waveshare Open103Z provides the following hardware components:
 Supported Features
 ==================
 
-The Waveshare Open103Z configuration supports the following hardware features:
-
-+-----------+------------+--------------------------------------+
-| Interface | Controller |      Driver/Component                |
-+===========+============+======================================+
-| NVIC      | on-chip    | nested vectored interrupt controller |
-+-----------+------------+--------------------------------------+
-| ADC       | on-chip    | adc                                  |
-+-----------+------------+--------------------------------------+
-| UART      | on-chip    | serial port                          |
-+-----------+------------+--------------------------------------+
-| GPIO      | on-chip    | gpio                                 |
-+-----------+------------+--------------------------------------+
-| FLASH     | on-chip    | flash                                |
-+-----------+------------+--------------------------------------+
-| SPI       | on-chip    | spi                                  |
-+-----------+------------+--------------------------------------+
-| I2C       | on-chip    | i2c                                  |
-+-----------+------------+--------------------------------------+
-| CAN       | on-chip    | can (disabled by default)            |
-+-----------+------------+--------------------------------------+
-| USB       | on-chip    | usb                                  |
-+-----------+------------+--------------------------------------+
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``waveshare_open103z`` board configuration can be built and
 flashed in the usual way.
 
diff --git a/boards/waveshare/open103z/waveshare_open103z.yaml b/boards/waveshare/open103z/waveshare_open103z.yaml
index c4df844c682..ae64dca74f7 100644
--- a/boards/waveshare/open103z/waveshare_open103z.yaml
+++ b/boards/waveshare/open103z/waveshare_open103z.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 64
 flash: 512
 supported:
diff --git a/boards/waveshare/rp2040_zero/doc/index.rst b/boards/waveshare/rp2040_zero/doc/index.rst
index 27e527e32c3..a469e2f502f 100644
--- a/boards/waveshare/rp2040_zero/doc/index.rst
+++ b/boards/waveshare/rp2040_zero/doc/index.rst
@@ -25,56 +25,7 @@ Hardware
 Supported Features
 ==================
 
-The ``rp2040_zero`` board target supports the following hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v6m-nvic`
-   * - UART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`raspberrypi,pico-uart`
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`raspberrypi,pico-gpio`
-   * - ADC
-     - :kconfig:option:`CONFIG_ADC`
-     - :dtcompatible:`raspberrypi,pico-adc`
-   * - I2C
-     - :kconfig:option:`CONFIG_I2C`
-     - :dtcompatible:`snps,designware-i2c`
-   * - SPI
-     - :kconfig:option:`CONFIG_SPI`
-     - :dtcompatible:`raspberrypi,pico-spi`
-   * - USB Device
-     - :kconfig:option:`CONFIG_USB_DEVICE_STACK`
-     - :dtcompatible:`raspberrypi,pico-usbd`
-   * - HWINFO
-     - :kconfig:option:`CONFIG_HWINFO`
-     - N/A
-   * - Watchdog Timer (WDT)
-     - :kconfig:option:`CONFIG_WATCHDOG`
-     - :dtcompatible:`raspberrypi,pico-watchdog`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM`
-     - :dtcompatible:`raspberrypi,pico-pwm`
-   * - Flash
-     - :kconfig:option:`CONFIG_FLASH`
-     - :dtcompatible:`raspberrypi,pico-flash`
-   * - Clock controller
-     - :kconfig:option:`CONFIG_CLOCK_CONTROL`
-     - :dtcompatible:`raspberrypi,pico-clock-controller`
-   * - UART (PIO)
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`raspberrypi,pico-uart-pio`
-   * - SPI (PIO)
-     - :kconfig:option:`CONFIG_SPI`
-     - :dtcompatible:`raspberrypi,pico-spi-pio`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -100,6 +51,8 @@ Default Zephyr Peripheral Mapping:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/waveshare/rp2040_zero/rp2040_zero.dts b/boards/waveshare/rp2040_zero/rp2040_zero.dts
index 88c41f55d2e..6e593f9a5ab 100644
--- a/boards/waveshare/rp2040_zero/rp2040_zero.dts
+++ b/boards/waveshare/rp2040_zero/rp2040_zero.dts
@@ -28,7 +28,7 @@
 };
 
 &flash0 {
-	reg = <0x10000000 DT_SIZE_M(16)>;
+	reg = <0x10000000 DT_SIZE_M(2)>;
 
 	partitions {
 		compatible = "fixed-partitions";
@@ -44,11 +44,11 @@
 
 		/*
 		 * Usable flash. Starts at 0x100, after the bootloader. The partition
-		 * size is 16MB minus the 0x100 bytes taken by the bootloader.
+		 * size is 2MB minus the 0x100 bytes taken by the bootloader.
 		 */
 		code_partition: partition@100 {
 			label = "code-partition";
-			reg = <0x100 (DT_SIZE_M(16) - 0x100)>;
+			reg = <0x100 (DT_SIZE_M(2) - 0x100)>;
 			read-only;
 		};
 	};
diff --git a/boards/waveshare/rp2040_zero/rp2040_zero.yaml b/boards/waveshare/rp2040_zero/rp2040_zero.yaml
index b93e332f7d8..409dd03975f 100644
--- a/boards/waveshare/rp2040_zero/rp2040_zero.yaml
+++ b/boards/waveshare/rp2040_zero/rp2040_zero.yaml
@@ -2,12 +2,11 @@ identifier: rp2040_zero
 name: Waveshare RP2040-Zero
 type: mcu
 arch: arm
-flash: 16384
+flash: 2048
 ram: 264
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - uart
   - gpio
diff --git a/boards/wch/ch32v003evt/ch32v003evt-pinctrl.dtsi b/boards/wch/ch32v003evt/ch32v003evt-pinctrl.dtsi
index 7f33d888e75..db0d39f0ac1 100644
--- a/boards/wch/ch32v003evt/ch32v003evt-pinctrl.dtsi
+++ b/boards/wch/ch32v003evt/ch32v003evt-pinctrl.dtsi
@@ -18,4 +18,12 @@
 			bias-pull-up;
 		};
 	};
+
+	i2c1_default: i2c1_default {
+		group1 {
+			pinmux = <I2C1_SDA_PC1_0>, <I2C1_SCL_PC2_0>;
+			output-high;
+			drive-open-drain;
+		};
+	};
 };
diff --git a/boards/wch/ch32v003evt/ch32v003evt.dts b/boards/wch/ch32v003evt/ch32v003evt.dts
index d702b6d43d0..fef72bcbd37 100644
--- a/boards/wch/ch32v003evt/ch32v003evt.dts
+++ b/boards/wch/ch32v003evt/ch32v003evt.dts
@@ -5,9 +5,12 @@
 
 /dts-v1/;
 
-#include <wch/ch32v00x.dtsi>
+#include <wch/ch32v0/ch32v003f4p.dtsi>
 #include "ch32v003evt-pinctrl.dtsi"
 
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+
 / {
 	model = "ch32v003evt";
 	compatible = "wch,ch32v003";
@@ -53,10 +56,21 @@
 	clocks = <&pll>;
 };
 
+&gpioc {
+	status = "okay";
+};
+
 &gpiod {
 	status = "okay";
 };
 
+&i2c1 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c1_default>;
+	pinctrl-names = "default";
+};
+
 &usart1 {
 	status = "okay";
 	current-speed = <115200>;
diff --git a/boards/wch/ch32v003evt/ch32v003evt.yaml b/boards/wch/ch32v003evt/ch32v003evt.yaml
index 0968fd0b4e7..2b349c49d83 100644
--- a/boards/wch/ch32v003evt/ch32v003evt.yaml
+++ b/boards/wch/ch32v003evt/ch32v003evt.yaml
@@ -9,3 +9,4 @@ ram: 2
 flash: 16
 supported:
   - gpio
+  - i2c
diff --git a/boards/wch/ch32v003evt/doc/index.rst b/boards/wch/ch32v003evt/doc/index.rst
index 0c59c492de2..a0d8b0140a7 100644
--- a/boards/wch/ch32v003evt/doc/index.rst
+++ b/boards/wch/ch32v003evt/doc/index.rst
@@ -22,25 +22,7 @@ external crystal and runs at 48 MHz.
 Supported Features
 ==================
 
-The ``ch32v003evt`` board target supports the following hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| PINCTRL   | on-chip    | pinctrl              |
-+-----------+------------+----------------------+
-| TIMER     | on-chip    | timer                |
-+-----------+------------+----------------------+
-| UART      | on-chip    | uart                 |
-+-----------+------------+----------------------+
-
-Other hardware features have not been enabled yet for this board.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -53,6 +35,8 @@ LED
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``ch32v003evt`` board target can be built and flashed
 in the usual way (see :ref:`build_an_application` and :ref:`application_run`
 for more details); however, an external programmer is required since the board
diff --git a/boards/wch/ch32v003f4p6_dev_board/CMakeLists.txt b/boards/wch/ch32v003f4p6_dev_board/CMakeLists.txt
new file mode 100644
index 00000000000..a1268429b15
--- /dev/null
+++ b/boards/wch/ch32v003f4p6_dev_board/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Andrei-Edward Popa <andrei.popa105@yahoo.com>.
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+zephyr_library_sources(board.c)
diff --git a/boards/wch/ch32v003f4p6_dev_board/Kconfig b/boards/wch/ch32v003f4p6_dev_board/Kconfig
new file mode 100644
index 00000000000..8e159b39cd2
--- /dev/null
+++ b/boards/wch/ch32v003f4p6_dev_board/Kconfig
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Andrei-Edward Popa
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_CH32V003F4P6_DEV_BOARD
+	select BOARD_LATE_INIT_HOOK
diff --git a/boards/wch/ch32v003f4p6_dev_board/Kconfig.ch32v003f4p6_dev_board b/boards/wch/ch32v003f4p6_dev_board/Kconfig.ch32v003f4p6_dev_board
new file mode 100644
index 00000000000..41a1c2543fb
--- /dev/null
+++ b/boards/wch/ch32v003f4p6_dev_board/Kconfig.ch32v003f4p6_dev_board
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Andrei-Edward Popa
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_CH32V003F4P6_DEV_BOARD
+	select SOC_CH32V003
diff --git a/boards/wch/ch32v003f4p6_dev_board/board.c b/boards/wch/ch32v003f4p6_dev_board/board.c
new file mode 100644
index 00000000000..ff48852dc44
--- /dev/null
+++ b/boards/wch/ch32v003f4p6_dev_board/board.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2025 Andrei-Edward Popa <andrei.popa105@yahoo.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/init.h>
+#include <zephyr/drivers/gpio.h>
+
+#include <ch32fun.h>
+
+#define AFIO_SWCFG_MASK    0x07000000
+#define AFIO_SWCFG_SWD_OFF 0x04000000
+
+void board_late_init_hook(void)
+{
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpiod))
+	const struct device *gpiod = DEVICE_DT_GET(DT_NODELABEL(gpiod));
+	uint32_t pcfr1;
+
+	/*
+	 * PD1 is wired to led and to SWDIO pin.
+	 * If PD1 is not put to ground, change the function to GPIO to use
+	 * the led as a user led.
+	 * If PD1 is put to ground, let the pin as SWDIO pin (default) to be
+	 * able to program the board.
+	 */
+	if (gpio_pin_get(gpiod, 1) == 1) {
+		RCC->APB2PCENR |= RCC_AFIOEN;
+		pcfr1 = AFIO->PCFR1;
+		pcfr1 = (pcfr1 & ~AFIO_SWCFG_MASK) | (AFIO_SWCFG_SWD_OFF & AFIO_SWCFG_MASK);
+		AFIO->PCFR1 = pcfr1;
+	}
+#endif
+}
diff --git a/boards/wch/ch32v003f4p6_dev_board/board.cmake b/boards/wch/ch32v003f4p6_dev_board/board.cmake
new file mode 100644
index 00000000000..480e7d3abe0
--- /dev/null
+++ b/boards/wch/ch32v003f4p6_dev_board/board.cmake
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Andrei-Edward Popa
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(minichlink)
+include(${ZEPHYR_BASE}/boards/common/minichlink.board.cmake)
+
+board_runner_args(openocd "--use-elf" "--cmd-reset-halt" "halt")
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
diff --git a/boards/wch/ch32v003f4p6_dev_board/board.yml b/boards/wch/ch32v003f4p6_dev_board/board.yml
new file mode 100644
index 00000000000..a7709ff6d02
--- /dev/null
+++ b/boards/wch/ch32v003f4p6_dev_board/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: ch32v003f4p6_dev_board
+  full_name: WCH CH32V003F4P6 Development Board
+  vendor: wch
+  socs:
+    - name: ch32v003
diff --git a/boards/wch/ch32v003f4p6_dev_board/ch32v003f4p6_dev_board-pinctrl.dtsi b/boards/wch/ch32v003f4p6_dev_board/ch32v003f4p6_dev_board-pinctrl.dtsi
new file mode 100644
index 00000000000..4b203569e47
--- /dev/null
+++ b/boards/wch/ch32v003f4p6_dev_board/ch32v003f4p6_dev_board-pinctrl.dtsi
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2025 Andrei-Edward Popa <andrei.popa105@yahoo.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/ch32v003-pinctrl.h>
+
+&pinctrl {
+	usart1_default: usart1_default {
+		group1 {
+			pinmux = <USART1_TX_PD5_0>;
+			output-high;
+			drive-push-pull;
+			slew-rate = "max-speed-10mhz";
+		};
+
+		group2 {
+			pinmux = <USART1_RX_PD6_0>;
+			bias-pull-up;
+		};
+	};
+
+	i2c1_default: i2c1_default {
+		group1 {
+			pinmux = <I2C1_SDA_PC1_0>, <I2C1_SCL_PC2_0>;
+			output-high;
+			drive-open-drain;
+		};
+	};
+};
diff --git a/boards/wch/ch32v003f4p6_dev_board/ch32v003f4p6_dev_board.dts b/boards/wch/ch32v003f4p6_dev_board/ch32v003f4p6_dev_board.dts
new file mode 100644
index 00000000000..2f83259ffc1
--- /dev/null
+++ b/boards/wch/ch32v003f4p6_dev_board/ch32v003f4p6_dev_board.dts
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2025 Andrei-Edward Popa <andrei.popa105@yahoo.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <wch/ch32v0/ch32v003f4p.dtsi>
+#include "ch32v003f4p6_dev_board-pinctrl.dtsi"
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+
+/ {
+	model = "ch32v003f4p6_dev_board";
+	compatible = "wch,ch32v003";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		red_led: led0 {
+			gpios = <&gpiod 1 GPIO_ACTIVE_LOW>;
+			label = "LED";
+		};
+	};
+
+	aliases {
+		led0 = &red_led;
+	};
+};
+
+&clk_hsi {
+	status = "okay";
+};
+
+&pll {
+	clocks = <&clk_hsi>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+};
+
+&gpioc {
+	status = "okay";
+};
+
+&gpiod {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c1_default>;
+	pinctrl-names = "default";
+};
+
+&usart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&usart1_default>;
+	pinctrl-names = "default";
+};
diff --git a/boards/wch/ch32v003f4p6_dev_board/ch32v003f4p6_dev_board.yaml b/boards/wch/ch32v003f4p6_dev_board/ch32v003f4p6_dev_board.yaml
new file mode 100644
index 00000000000..e4823b08a3a
--- /dev/null
+++ b/boards/wch/ch32v003f4p6_dev_board/ch32v003f4p6_dev_board.yaml
@@ -0,0 +1,13 @@
+identifier: ch32v003f4p6_dev_board
+name: WCH CH32V003F4P6 Development Board
+type: mcu
+arch: riscv
+toolchain:
+  - cross-compile
+  - zephyr
+ram: 2
+flash: 16
+supported:
+  - gpio
+  - uart
+  - i2c
diff --git a/boards/wch/ch32v003f4p6_dev_board/ch32v003f4p6_dev_board_defconfig b/boards/wch/ch32v003f4p6_dev_board/ch32v003f4p6_dev_board_defconfig
new file mode 100644
index 00000000000..99469475200
--- /dev/null
+++ b/boards/wch/ch32v003f4p6_dev_board/ch32v003f4p6_dev_board_defconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Andrei-Edward Popa
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_GPIO=y
+
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/wch/ch32v003f4p6_dev_board/doc/img/ch32v003f4p6_dev_board.webp b/boards/wch/ch32v003f4p6_dev_board/doc/img/ch32v003f4p6_dev_board.webp
new file mode 100644
index 00000000000..a55ccd34818
Binary files /dev/null and b/boards/wch/ch32v003f4p6_dev_board/doc/img/ch32v003f4p6_dev_board.webp differ
diff --git a/boards/wch/ch32v003f4p6_dev_board/doc/index.rst b/boards/wch/ch32v003f4p6_dev_board/doc/index.rst
new file mode 100644
index 00000000000..6646efea06c
--- /dev/null
+++ b/boards/wch/ch32v003f4p6_dev_board/doc/index.rst
@@ -0,0 +1,100 @@
+.. zephyr:board:: ch32v003f4p6_dev_board
+
+Overview
+********
+
+The `WCH`_ CH32V003F4P6 Development Board hardware provides support for
+QingKe 32-bit RISC-V2A processor and the following devices:
+
+* CLOCK
+* :abbr:`GPIO (General Purpose Input Output)`
+* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
+
+The board is equipped with one LED, wired to PD1 and SWIO pins.
+The `WCH webpage on CH32V003`_ contains the processor's information
+and the datasheet.
+
+Hardware
+********
+
+The QingKe 32-bit RISC-V2A processor of the WCH CH32V003F4P6_DEV_BOARD is clocked
+by an internal RC oscillator and runs at 24 MHz.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+LED
+---
+
+* LED1 (red) = PD1
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``ch32v003f4p6_dev_board`` board target can be built and
+flashed in the usual way (see :ref:`build_an_application` and :ref:`application_run`
+for more details); however, an external programmer is required since the board
+does not have any built-in debug support.
+
+The following pins of the external programmer must be connected to the
+following pins on the PCB (see image):
+
+* VCC = VCC (do not power the board from the USB port at the same time)
+* GND = GND
+* SWIO = PD1
+
+Flashing
+========
+
+SWIO pin is connected to PD1 and also to led on the board. By default, the function
+of PD1 is SWD. To use the led on the board, the function of PD1 is changed to GPIO
+if PD1 is not put to ground (see :zephyr_file:`boards/wch/ch32v003f4p6_dev_board/board.c`).
+In order to be able to reflash the board, if some zephyr application is already loaded
+in flash, power on the board with PD1 put to ground to let PD1 as SWIO. After that,
+reconnect the external debugger SWDIO pin to PD1/SWIO to be able to flash the board
+using the external debugger.
+
+You can use ``minichlink`` to flash the board. Once ``minichlink`` has been set
+up, build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Here is an example for the :zephyr:code-sample:`blinky` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: ch32v003f4p6_dev_board
+   :goals: build flash
+
+Debugging
+=========
+
+This board can be debugged via OpenOCD or ``minichlink``.
+
+Testing the LED on the WCH CH32V003F4P6_DEV_BOARD
+*************************************************
+
+There is 1 sample program that allow you to test that the LED on the board is
+working properly with Zephyr:
+
+.. code-block:: console
+
+   samples/basic/blinky
+
+You can build and flash the examples to make sure Zephyr is running
+correctly on your board. The button and LED definition can be found
+in :zephyr_file:`boards/wch/ch32v003f4p6_dev_board/ch32v003f4p6_dev_board.dts`.
+
+References
+**********
+
+.. target-notes::
+
+.. _WCH: http://www.wch-ic.com
+.. _WCH webpage on CH32V003: https://www.wch-ic.com/products/CH32V003.html
diff --git a/boards/wch/ch32v003f4p6_dev_board/support/openocd.cfg b/boards/wch/ch32v003f4p6_dev_board/support/openocd.cfg
new file mode 100644
index 00000000000..ac321f2af66
--- /dev/null
+++ b/boards/wch/ch32v003f4p6_dev_board/support/openocd.cfg
@@ -0,0 +1,14 @@
+adapter driver wlink
+wlink_set
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure  -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+
+flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
+
+echo "Ready for Remote Connections"
diff --git a/boards/wch/linkw/Kconfig.linkw b/boards/wch/linkw/Kconfig.linkw
new file mode 100644
index 00000000000..3cdfe3c66ba
--- /dev/null
+++ b/boards/wch/linkw/Kconfig.linkw
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_LINKW
+	select SOC_CH32V208
diff --git a/boards/wch/linkw/board.cmake b/boards/wch/linkw/board.cmake
new file mode 100644
index 00000000000..cc34377de8f
--- /dev/null
+++ b/boards/wch/linkw/board.cmake
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(openocd "--use-elf" "--cmd-reset-halt" "halt")
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+
+board_runner_args(minichlink)
+include(${ZEPHYR_BASE}/boards/common/minichlink.board.cmake)
diff --git a/boards/wch/linkw/board.yml b/boards/wch/linkw/board.yml
new file mode 100644
index 00000000000..ce9a140eacd
--- /dev/null
+++ b/boards/wch/linkw/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: linkw
+  full_name: WCH LinkW
+  vendor: wch
+  socs:
+    - name: ch32v208
diff --git a/boards/wch/linkw/doc/img/linkw.webp b/boards/wch/linkw/doc/img/linkw.webp
new file mode 100644
index 00000000000..3c719a53074
Binary files /dev/null and b/boards/wch/linkw/doc/img/linkw.webp differ
diff --git a/boards/wch/linkw/doc/img/weaxie_linkw.webp b/boards/wch/linkw/doc/img/weaxie_linkw.webp
new file mode 100644
index 00000000000..c621a0a56c2
Binary files /dev/null and b/boards/wch/linkw/doc/img/weaxie_linkw.webp differ
diff --git a/boards/wch/linkw/doc/index.rst b/boards/wch/linkw/doc/index.rst
new file mode 100644
index 00000000000..4df6283d286
--- /dev/null
+++ b/boards/wch/linkw/doc/index.rst
@@ -0,0 +1,89 @@
+.. zephyr:board:: linkw
+
+Overview
+********
+
+The `WCH`_ LinkW hardware provides support for QingKe 32-bit RISC-V4C
+processor and the following devices:
+
+* CLOCK
+* :abbr:`GPIO (General Purpose Input Output)`
+* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
+
+The board is equipped with two LEDs and two Buttons.
+The `WCH webpage on CH32V208`_ contains the processor's manuals.
+The `WCH webpage on LinkW`_ contains the LinkW's schematic.
+
+Hardware
+********
+
+The QingKe 32-bit RISC-V4C processor of the WCH LinkW is clocked by an external
+32 MHz crystal or the internal 8 MHz oscillator and runs up to 144 MHz.
+The CH32V208 SoC Features 4 USART, 4 GPIO ports, 2 SPI, 2 I2C, ADC, RTC,
+CAN, 2 USB Device, USB Host, OPA, ETH with PHY, several timers, and BLE 5.3.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+LED
+---
+
+* LED0 = Green Mode LED
+* LED1 = Blue Activity LED
+
+Button
+------
+
+* SW0 = Mode Select Button (Active Low)
+* SW1 = Bootstrap Button (Active High)
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``linkw`` board target can be built and flashed
+in the usual way (see :ref:`build_an_application` and :ref:`application_run`
+for more details); however, an external programmer is required since the board
+does not have any built-in debug support.
+
+The following pins of the external programmer must be connected to the
+following pins on the PCB:
+
+* VCC = VCC
+* GND = GND
+* SWIO = PA13
+* SWCLK = PA14
+
+Flashing
+========
+
+You can use ``minichlink`` to flash the board. Once ``minichlink`` has been set
+up, build and flash applications as usual (see :ref:`build_an_application` and
+:ref:`application_run` for more details).
+
+Here is an example for the :zephyr:code-sample:`blinky` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: linkw
+   :goals: build flash
+
+Debugging
+=========
+
+This board can be debugged via OpenOCD or ``minichlink``.
+
+References
+**********
+
+.. target-notes::
+
+.. _WCH: http://www.wch-ic.com
+.. _WCH webpage on CH32V208: https://www.wch-ic.com/products/CH32V208.html
+.. _WCH webpage on LinkW: https://www.wch-ic.com/products/WCH-Link.html
diff --git a/boards/wch/linkw/linkw-pinctrl.dtsi b/boards/wch/linkw/linkw-pinctrl.dtsi
new file mode 100644
index 00000000000..3cbd4ba1645
--- /dev/null
+++ b/boards/wch/linkw/linkw-pinctrl.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/ch32v20x_30x-pinctrl.h>
+
+&pinctrl {
+	usart2_default: usart2_default {
+		group1 {
+			pinmux = <USART2_TX_PA2_0>;
+			output-high;
+			drive-push-pull;
+			slew-rate = "max-speed-10mhz";
+		};
+		group2 {
+			pinmux = <USART2_RX_PA3_0>;
+			bias-pull-up;
+		};
+	};
+};
diff --git a/boards/wch/linkw/linkw.dts b/boards/wch/linkw/linkw.dts
new file mode 100644
index 00000000000..50f749ef28c
--- /dev/null
+++ b/boards/wch/linkw/linkw.dts
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <wch/ch32v208/ch32v208gbu.dtsi>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include "linkw-pinctrl.dtsi"
+
+/ {
+	model = "linkw";
+	compatible = "wch,ch32v208";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &usart2;
+		zephyr,shell-uart = &usart2;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		status = "okay";
+
+		green_led: led0 {
+			gpios = <&gpioc 7 GPIO_ACTIVE_LOW>;
+		};
+
+		blue_led: led1 {
+			gpios = <&gpioc 9 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		mode: sw0 {
+			gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		boot: sw1 {
+			gpios = <&gpiob 8 GPIO_ACTIVE_HIGH>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+
+	aliases {
+		led0 = &blue_led;
+		sw0 = &mode;
+	};
+};
+
+&clk_hse {
+	clock-frequency = <DT_FREQ_M(32)>;
+	status = "okay";
+};
+
+&pll {
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+};
+
+&gpioa {
+	status = "okay";
+};
+
+&gpioc {
+	status = "okay";
+};
+
+&usart2 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&usart2_default>;
+	pinctrl-names = "default";
+};
diff --git a/boards/wch/linkw/linkw.yaml b/boards/wch/linkw/linkw.yaml
new file mode 100644
index 00000000000..042c9cf0e65
--- /dev/null
+++ b/boards/wch/linkw/linkw.yaml
@@ -0,0 +1,11 @@
+identifier: linkw
+name: WCH LinkW
+type: mcu
+arch: riscv
+toolchain:
+  - cross-compile
+  - zephyr
+ram: 64
+flash: 128
+supported:
+  - gpio
diff --git a/boards/wch/linkw/linkw_defconfig b/boards/wch/linkw/linkw_defconfig
new file mode 100644
index 00000000000..ea223eef702
--- /dev/null
+++ b/boards/wch/linkw/linkw_defconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_GPIO=y
+
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
diff --git a/boards/wch/linkw/support/openocd.cfg b/boards/wch/linkw/support/openocd.cfg
new file mode 100644
index 00000000000..65a43f18a16
--- /dev/null
+++ b/boards/wch/linkw/support/openocd.cfg
@@ -0,0 +1,20 @@
+# Tested with WCH openOCD liberated fork (https://github.com/jnk0le/openocd-wch)
+# Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
+# SPDX-License-Identifier: Apache-2.0
+adapter driver wlinke
+adapter speed 6000
+transport select sdi
+
+wlink_set_address 0x00000000
+set _CHIPNAME wch_riscv
+sdi newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 wch_riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure  -work-area-phys 0x20000000 -work-area-size 10000 -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+
+flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
+
+echo "Ready for Remote Connections"
diff --git a/boards/we/oceanus1ev/Kconfig.defconfig b/boards/we/oceanus1ev/Kconfig.defconfig
new file mode 100644
index 00000000000..d644612b5e6
--- /dev/null
+++ b/boards/we/oceanus1ev/Kconfig.defconfig
@@ -0,0 +1,13 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_WE_OCEANUS1EV
+
+if LORA
+
+config MAIN_STACK_SIZE
+	default 2048
+
+endif # LORA
+
+endif # BOARD_WE_OCEANUS1EV
diff --git a/boards/we/oceanus1ev/Kconfig.we_oceanus1ev b/boards/we/oceanus1ev/Kconfig.we_oceanus1ev
new file mode 100644
index 00000000000..67f92ed7cdc
--- /dev/null
+++ b/boards/we/oceanus1ev/Kconfig.we_oceanus1ev
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_WE_OCEANUS1EV
+	select SOC_STM32WLE5XX
diff --git a/boards/we/oceanus1ev/board.cmake b/boards/we/oceanus1ev/board.cmake
new file mode 100644
index 00000000000..4cba054c8a5
--- /dev/null
+++ b/boards/we/oceanus1ev/board.cmake
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(jlink "--device=STM32WLE5CC" "--speed=4000" "--reset-after-load")
+
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
diff --git a/boards/we/oceanus1ev/board.yml b/boards/we/oceanus1ev/board.yml
new file mode 100644
index 00000000000..35c0780bdda
--- /dev/null
+++ b/boards/we/oceanus1ev/board.yml
@@ -0,0 +1,12 @@
+board:
+  name: we_oceanus1ev
+  full_name: Oceanus-I EV
+  vendor: we
+  revision:
+    format: "major.minor.patch"
+    default: "1.1.0"
+    exact: true
+    revisions:
+    - name: "1.1.0"
+  socs:
+  - name: stm32wle5xx
diff --git a/boards/we/oceanus1ev/doc/img/we_oceanus1ev.webp b/boards/we/oceanus1ev/doc/img/we_oceanus1ev.webp
new file mode 100644
index 00000000000..92eade76cdb
Binary files /dev/null and b/boards/we/oceanus1ev/doc/img/we_oceanus1ev.webp differ
diff --git a/boards/we/oceanus1ev/doc/index.rst b/boards/we/oceanus1ev/doc/index.rst
new file mode 100644
index 00000000000..d32be011a39
--- /dev/null
+++ b/boards/we/oceanus1ev/doc/index.rst
@@ -0,0 +1,80 @@
+.. zephyr:board:: we_oceanus1ev
+
+Overview
+********
+
+The we_oceanus1ev board is an evaluation board of the `Oceanus-I`_ radio module.
+It provides support for the `STM32WLE5CC`_ ARM CPU and
+the following devices:
+
+* CLOCK
+* FLASH
+* :abbr:`GPIO (General Purpose Input Output)`
+* :abbr:`I2C (Inter-Integrated Circuit)`
+* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
+* RADIO (LoRa)
+* :abbr:`RTC (STM32 RTC System Clock)`
+* :abbr:`SPI (Serial Peripheral Interface)`
+* :abbr:`UART (Universal asynchronous receiver-transmitter)`
+* :abbr:`WDT (Watchdog Timer)`
+
+Hardware
+********
+
+The board has below hardware features:
+
+- `Oceanus-I`_, 256KB Flash, 64KB RAM with external antenna
+- 1 FTDI chip (USB to UART) converter
+- 1 I2C WE sensor EV-Boards connector
+- 1 SPI WE sensor EV-Boards connector
+- 2 application LEDs
+- 1 application, and 1 reset push-button
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``we_oceanus1ev`` board can be built the
+usual way (see :ref:`build_an_application`).
+
+The board debugged and flashed with an external debug probe connected
+to the SWD pins, current native support is for the JLink debug probe.
+
+Flashing
+========
+
+Connect the board to your host computer and build and flash an application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: we_oceanus1ev
+   :goals: build flash
+
+Run a serial terminal to connect with your board. By default, ``lpuart1`` is
+accessible via the on-board FTDI USB to UART converter.
+
+Debugging
+=========
+
+You can debug an application in the usual way.  Here is an example for the
+:zephyr:code-sample:`blinky` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: we_oceanus1ev
+   :maybe-skip-config:
+   :goals: debug
+
+References
+**********
+
+.. target-notes::
+
+.. _`Oceanus-I`: https://www.we-online.com/katalog/de/OCEANUS-I
+.. _`STM32WLE5CC`: https://www.st.com/en/microcontrollers-microprocessors/stm32wle5cc.html
diff --git a/boards/we/oceanus1ev/we_oceanus1ev.dts b/boards/we/oceanus1ev/we_oceanus1ev.dts
new file mode 100644
index 00000000000..a861c63d0e4
--- /dev/null
+++ b/boards/we/oceanus1ev/we_oceanus1ev.dts
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <we/oceanus1.dtsi>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "Oceanus-I EV";
+	compatible = "we,oceanus1ev";
+
+	chosen {
+		zephyr,console = &lpuart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,code-partition = &slot0_partition;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		yellow_led: led_1 {
+			gpios = <&gpioa 7 GPIO_ACTIVE_HIGH>;
+			label = "LED_1";
+		};
+
+		blue_led: led_2 {
+			gpios = <&gpioa 4 GPIO_ACTIVE_HIGH>;
+			label = "LED_2";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		wake_up_button: button_0 {
+			label = "/WAKE_UP";
+			gpios = <&gpioa 0 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	aliases {
+		led0 = &yellow_led;
+		led1 = &blue_led;
+		sw0 = &wake_up_button;
+		lora0 = &lora;
+		watchdog0 = &iwdg;
+	};
+};
+
+stm32_lp_tick_source: &lptim1 {
+	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
+			<&rcc STM32_SRC_LSE LPTIM1_SEL(3)>;
+	status = "okay";
+};
+
+&clk_lsi {
+	status = "okay";
+};
+
+&pll {
+	div-m = <1>;
+	mul-n = <6>;
+	div-r = <2>;
+	div-q = <2>;
+	clocks = <&clk_hsi>;
+	status = "okay";
+};
+
+&iwdg {
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(48)>;
+	cpu1-prescaler = <1>;
+	ahb3-prescaler = <1>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+};
+
+&lpuart1 {
+	pinctrl-0 = <&lpuart1_tx_pa2 &lpuart1_rx_pa3>;
+	pinctrl-names = "default";
+	current-speed = <9600>;
+	status = "okay";
+};
+
+&usart1 {
+	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&i2c1 {
+	pinctrl-0 = <&i2c1_scl_pb8 &i2c1_sda_pb7>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&spi1 {
+	pinctrl-0 = <&spi1_sck_pb3 &spi1_miso_pb4 &spi1_mosi_pb5>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+&rtc {
+	clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
+		 <&rcc STM32_SRC_LSE RTC_SEL(2)>;
+	status = "okay";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 DT_SIZE_K(32)>;
+			read-only;
+		};
+		slot0_partition: partition@8000 {
+			label = "image-0";
+			reg = <0x00008000 DT_SIZE_K(108)>;
+		};
+		slot1_partition: partition@23000 {
+			label = "image-1";
+			reg = <0x00023000 DT_SIZE_K(108)>;
+		};
+		storage_partition: partition@3e000 {
+			label = "storage";
+			reg = <0x0003e000 DT_SIZE_K(8)>;
+		};
+	};
+};
diff --git a/boards/we/oceanus1ev/we_oceanus1ev_1_1_0.yaml b/boards/we/oceanus1ev/we_oceanus1ev_1_1_0.yaml
new file mode 100644
index 00000000000..600d75ac2bc
--- /dev/null
+++ b/boards/we/oceanus1ev/we_oceanus1ev_1_1_0.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: we_oceanus1ev@1.1.0
+name: Oceanus-I EV (rev 1.1)
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+ram: 64
+flash: 256
+supported:
+  - counter
+  - gpio
+  - i2c
+  - nvs
+  - spi
+  - uart
+  - watchdog
+  - lora
+vendor: we
diff --git a/boards/we/oceanus1ev/we_oceanus1ev_defconfig b/boards/we/oceanus1ev/we_oceanus1ev_defconfig
new file mode 100644
index 00000000000..dddce979cc9
--- /dev/null
+++ b/boards/we/oceanus1ev/we_oceanus1ev_defconfig
@@ -0,0 +1,15 @@
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
diff --git a/boards/we/ophelia1ev/board.yml b/boards/we/ophelia1ev/board.yml
index b69567e089d..263047876a0 100644
--- a/boards/we/ophelia1ev/board.yml
+++ b/boards/we/ophelia1ev/board.yml
@@ -1,6 +1,6 @@
 board:
   name: we_ophelia1ev
   full_name: Ophelia-I EV NRF52805
-  vendor: wurth
+  vendor: we
   socs:
   - name: nrf52805
diff --git a/boards/we/ophelia1ev/doc/index.rst b/boards/we/ophelia1ev/doc/index.rst
index 189e0bdcfc7..54a8ffe2122 100644
--- a/boards/we/ophelia1ev/doc/index.rst
+++ b/boards/we/ophelia1ev/doc/index.rst
@@ -30,40 +30,13 @@ antenna that can be connected to the available SMA connector.
 Supported Features
 ==================
 
-The we_ophelia1ev_nrf52805 board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
+.. zephyr:board-supported-hw::
 
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
diff --git a/boards/we/ophelia1ev/we_ophelia1ev_nrf52805.yaml b/boards/we/ophelia1ev/we_ophelia1ev_nrf52805.yaml
index 5b55a854a0d..6b47fe26a5b 100644
--- a/boards/we/ophelia1ev/we_ophelia1ev_nrf52805.yaml
+++ b/boards/we/ophelia1ev/we_ophelia1ev_nrf52805.yaml
@@ -10,7 +10,6 @@ flash: 192
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - i2c
diff --git a/boards/we/ophelia4ev/Kconfig.defconfig b/boards/we/ophelia4ev/Kconfig.defconfig
new file mode 100644
index 00000000000..ae367b374d7
--- /dev/null
+++ b/boards/we/ophelia4ev/Kconfig.defconfig
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_OPHELIA4EV_NRF54L15_CPUAPP
+
+config ROM_START_OFFSET
+	default 0x800 if BOOTLOADER_MCUBOOT
+
+endif # BOARD_OPHELIA4EV_NRF54L15_CPUAPP
diff --git a/boards/we/ophelia4ev/Kconfig.ophelia4ev b/boards/we/ophelia4ev/Kconfig.ophelia4ev
new file mode 100644
index 00000000000..70937963208
--- /dev/null
+++ b/boards/we/ophelia4ev/Kconfig.ophelia4ev
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_OPHELIA4EV
+	select SOC_NRF54L15_CPUAPP if BOARD_OPHELIA4EV_NRF54L15_CPUAPP
+	select SOC_NRF54L15_CPUFLPR if BOARD_OPHELIA4EV_NRF54L15_CPUFLPR
diff --git a/boards/we/ophelia4ev/board.cmake b/boards/we/ophelia4ev/board.cmake
new file mode 100644
index 00000000000..69dfac8e45e
--- /dev/null
+++ b/boards/we/ophelia4ev/board.cmake
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+include(${ZEPHYR_BASE}/boards/nordic/nrf54l15dk/board.cmake)
diff --git a/boards/we/ophelia4ev/board.yml b/boards/we/ophelia4ev/board.yml
new file mode 100644
index 00000000000..22987b007cb
--- /dev/null
+++ b/boards/we/ophelia4ev/board.yml
@@ -0,0 +1,9 @@
+board:
+  name: ophelia4ev
+  full_name: Ophelia-IV DK
+  vendor: we
+  socs:
+  - name: nrf54l15
+    variants:
+    - name: xip
+      cpucluster: cpuflpr
diff --git a/boards/we/ophelia4ev/doc/img/ophelia4ev.webp b/boards/we/ophelia4ev/doc/img/ophelia4ev.webp
new file mode 100644
index 00000000000..07a2ced30b6
Binary files /dev/null and b/boards/we/ophelia4ev/doc/img/ophelia4ev.webp differ
diff --git a/boards/we/ophelia4ev/doc/index.rst b/boards/we/ophelia4ev/doc/index.rst
new file mode 100644
index 00000000000..ad981f6c01d
--- /dev/null
+++ b/boards/we/ophelia4ev/doc/index.rst
@@ -0,0 +1,92 @@
+.. zephyr:board:: ophelia4ev
+
+Overview
+********
+
+.. note::
+   You can find more information about the nRF54L15 SoC on the `nRF54L15 website`_.
+   For the nRF54L15 technical documentation and other resources (such as
+   SoC Datasheet), see the `nRF54L15 documentation`_ page.
+
+The OPHELIA-IV EV board is an evaluation board of the Ophelia-IV radio module.
+
+Hardware
+********
+
+The Ophelia-IV uses the internal low frequency RC oscillator
+and provides the so called smart antenna connection, that allows
+to choose between the module's integrated PCB antenna and an external
+antenna that can be connected to the available SMA connector.
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Applications for the ``ophelia4ev/nrf54l15/cpuapp`` board target can be
+built, flashed, and debugged in the usual way. See
+:ref:`build_an_application` and :ref:`application_run` for more details on
+building and running.
+
+Applications for the ``ophelia4ev/nrf54l15/cpuflpr`` board target need
+to be built using sysbuild to include the ``vpr_launcher`` image for the application core.
+
+Enter the following command to compile ``hello_world`` for the FLPR core:
+
+.. code-block:: console
+
+   west build -p -b ophelia4ev/nrf54l15/cpuflpr --sysbuild
+
+
+Flashing
+========
+
+As an example, this section shows how to build and flash the :zephyr:code-sample:`hello_world`
+application.
+
+To build and program the sample to the OPHELIA-IV EV, complete the following steps:
+
+First, connect the OPHELIA-IV EV to you computer using the USB port on the board.
+Then connect a segger flasher to the SWD connector available on the board.
+Next, build the sample by running the following command:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: ophelia4ev/nrf54l15/cpuapp
+   :goals: build flash
+
+.. warning::
+
+   When programming the device, you might get an error similar to the following message::
+
+    ERROR: The operation attempted is unavailable due to readback protection in
+    ERROR: your device. Please use --recover to unlock the device.
+
+   This error occurs when readback protection is enabled.
+   To disable the readback protection, you must *recover* your device.
+
+   Enter the following command to recover the core::
+
+    west flash --recover
+
+   The ``--recover`` command erases the flash memory and then writes a small binary into
+   the recovered flash memory.
+   This binary prevents the readback protection from enabling itself again after a pin
+   reset or power cycle.
+
+Follow the instructions in the :ref:`nordic_segger` page to install
+and configure all the necessary software. Further information can be
+found in :ref:`nordic_segger_flashing`.
+
+References
+**********
+
+.. target-notes::
+
+.. _nRF54L15 website: https://www.nordicsemi.com/Products/nRF54L15
+.. _nRF54L15 documentation: https://docs.nordicsemi.com/bundle/ncs-latest/page/nrf/app_dev/device_guides/nrf54l/index.html
diff --git a/boards/we/ophelia4ev/ophelia4ev_common.dtsi b/boards/we/ophelia4ev/ophelia4ev_common.dtsi
new file mode 100644
index 00000000000..313e8f3f39a
--- /dev/null
+++ b/boards/we/ophelia4ev/ophelia4ev_common.dtsi
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "ophelia4ev_nrf54l15-pinctrl.dtsi"
+
+/ {
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led_0 {
+			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 0";
+		};
+
+		led1: led_1 {
+			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 1";
+		};
+
+		led2: led_2 {
+			gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 2";
+		};
+
+		led3: led_3 {
+			gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+			label = "Green LED 3";
+		};
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+
+		/*
+		 * PWM signal can be exposed on GPIO pin only within same domain.
+		 * There is only one domain which contains both PWM and GPIO:
+		 * PWM20/21/22 and GPIO Port P1.
+		 * Only LEDs connected to P1 can work with PWM, for example LED3.
+		 */
+		pwm_led3: pwm_led_3 {
+			pwms = <&pwm20 0 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+		};
+	};
+
+	buttons {
+		compatible = "gpio-keys";
+
+		button0: button_0 {
+			gpios = <&gpio2 3 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 0";
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		button1: button_1 {
+			gpios = <&gpio1 12 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 1";
+			zephyr,code = <INPUT_KEY_1>;
+		};
+
+		button2: button_2 {
+			gpios = <&gpio1 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 2";
+			zephyr,code = <INPUT_KEY_2>;
+		};
+
+		button3: button_3 {
+			gpios = <&gpio1 14 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+			label = "Push button 3";
+			zephyr,code = <INPUT_KEY_3>;
+		};
+	};
+
+	aliases {
+		led0 = &led0;
+		led1 = &led1;
+		led2 = &led2;
+		led3 = &led3;
+		pwm-led0 = &pwm_led3;
+		sw0 = &button0;
+		sw1 = &button1;
+		sw2 = &button2;
+		sw3 = &button3;
+		watchdog0 = &wdt31;
+	};
+};
+
+&uart20 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart20_default>;
+	pinctrl-1 = <&uart20_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&uart30 {
+	current-speed = <115200>;
+	pinctrl-0 = <&uart30_default>;
+	pinctrl-1 = <&uart30_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+&pwm20 {
+	status = "okay";
+	pinctrl-0 = <&pwm20_default>;
+	pinctrl-1 = <&pwm20_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+/* Get a node label for wi-fi spi to use in shield files */
+wifi_spi: &spi22 {};
diff --git a/boards/we/ophelia4ev/ophelia4ev_nrf54l15-pinctrl.dtsi b/boards/we/ophelia4ev/ophelia4ev_nrf54l15-pinctrl.dtsi
new file mode 100644
index 00000000000..4a3b761796b
--- /dev/null
+++ b/boards/we/ophelia4ev/ophelia4ev_nrf54l15-pinctrl.dtsi
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	/omit-if-no-ref/ uart20_default: uart20_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 4)>,
+				<NRF_PSEL(UART_RTS, 1, 6)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 1, 15)>,
+				<NRF_PSEL(UART_CTS, 1, 2)>;
+			bias-pull-up;
+		};
+	};
+
+	/omit-if-no-ref/ uart20_sleep: uart20_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 4)>,
+				<NRF_PSEL(UART_RX, 1, 15)>,
+				<NRF_PSEL(UART_RTS, 1, 6)>,
+				<NRF_PSEL(UART_CTS, 1, 2)>;
+			low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ uart30_default: uart30_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 2, 8)>,
+				<NRF_PSEL(UART_RTS, 2, 10)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 2, 7)>,
+				<NRF_PSEL(UART_CTS, 2, 9)>;
+			bias-pull-up;
+		};
+	};
+
+	/omit-if-no-ref/ uart30_sleep: uart30_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 2, 8)>,
+				<NRF_PSEL(UART_RX, 2, 7)>,
+				<NRF_PSEL(UART_RTS, 2, 10)>,
+				<NRF_PSEL(UART_CTS, 2, 9)>;
+			low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ spi00_default: spi00_default {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 1)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 2)>,
+				<NRF_PSEL(SPIM_MISO, 2, 4)>;
+		};
+	};
+
+	/omit-if-no-ref/ spi00_sleep: spi00_sleep {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 1)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 2)>,
+				<NRF_PSEL(SPIM_MISO, 2, 4)>;
+				low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ pwm20_default: pwm20_default {
+		group1 {
+			psels = <NRF_PSEL(PWM_OUT0, 1, 10)>;
+		};
+	};
+
+	/omit-if-no-ref/ pwm20_sleep: pwm20_sleep {
+		group1 {
+			psels = <NRF_PSEL(PWM_OUT0, 1, 10)>;
+			low-power-enable;
+		};
+	};
+
+	/omit-if-no-ref/ grtc_default: grtc_default {
+		group1 {
+			psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 8)>,
+				<NRF_PSEL(GRTC_CLKOUT_32K, 0, 4)>;
+		};
+	};
+
+	/omit-if-no-ref/ grtc_sleep: grtc_sleep {
+		group1 {
+			psels = <NRF_PSEL(GRTC_CLKOUT_FAST, 1, 8)>,
+				<NRF_PSEL(GRTC_CLKOUT_32K, 0, 4)>;
+			low-power-enable;
+		};
+	};
+};
diff --git a/boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuapp.dts b/boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuapp.dts
new file mode 100644
index 00000000000..73b135891a8
--- /dev/null
+++ b/boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuapp.dts
@@ -0,0 +1,174 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf54l15_cpuapp.dtsi>
+#include "ophelia4ev_common.dtsi"
+
+/ {
+	model = "Ophelia-IV EV Application MCU";
+	compatible = "we,ophelia4ev_nrf54l15-cpuapp";
+
+	chosen {
+		zephyr,console = &uart20;
+		zephyr,shell-uart = &uart20;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,flash = &cpuapp_rram;
+		zephyr,sram = &cpuapp_sram;
+		zephyr,uart-mcumgr = &uart20;
+		zephyr,bt-mon-uart = &uart20;
+		zephyr,bt-c2h-uart = &uart20;
+		zephyr,flash-controller = &rram_controller;
+		zephyr,ieee802154 = &ieee802154;
+	};
+};
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		slot0_partition: partition@10000 {
+			label = "image-0";
+			reg = <0x10000 DT_SIZE_K(324)>;
+		};
+
+		slot0_ns_partition: partition@61000 {
+			label = "image-0-nonsecure";
+			reg = <0x61000 DT_SIZE_K(324)>;
+		};
+
+		slot1_partition: partition@b2000 {
+			label = "image-1";
+			reg = <0xb2000 DT_SIZE_K(324)>;
+		};
+
+		slot1_ns_partition: partition@103000 {
+			label = "image-1-nonsecure";
+			reg = <0x103000 DT_SIZE_K(324)>;
+		};
+
+		/* 32k from 0x154000 to 0x15bfff reserved for TF-M partitions */
+		storage_partition: partition@15c000 {
+			label = "storage";
+			reg = <0x15c000 DT_SIZE_K(36)>;
+		};
+	};
+};
+
+&cpuapp_sram {
+	status = "okay";
+};
+
+&lfxo {
+	load-capacitors = "internal";
+	load-capacitance-femtofarad = <15500>;
+};
+
+&hfxo {
+	load-capacitors = "internal";
+	load-capacitance-femtofarad = <15000>;
+};
+
+&regulators {
+	status = "okay";
+};
+
+&vregmain {
+	status = "okay";
+
+	regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
+};
+
+&grtc {
+	owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
+
+	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
+	child-owned-channels = <3 4 7 8 9 10 11>;
+
+	status = "okay";
+};
+
+&uart20 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};
+
+&radio {
+	status = "okay";
+};
+
+&ieee802154 {
+	status = "okay";
+};
+
+&temp {
+	status = "okay";
+};
+
+&clock {
+	status = "okay";
+};
+
+&spi00 {
+	status = "okay";
+
+	cs-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
+	pinctrl-0 = <&spi00_default>;
+	pinctrl-1 = <&spi00_sleep>;
+	pinctrl-names = "default", "sleep";
+
+	mx25r64: mx25r6435f@0 {
+		compatible = "jedec,spi-nor";
+		status = "okay";
+		reg = <0>;
+		spi-max-frequency = <8000000>;
+
+		jedec-id = [c2 28 17];
+
+		sfdp-bfp = [
+			e5 20 f1 ff  ff ff ff 03  44 eb 08 6b  08 3b 04 bb
+			ee ff ff ff  ff ff 00 ff  ff ff 00 ff  0c 20 0f 52
+			10 d8 00 ff  23 72 f5 00  82 ed 04 cc  44 83 48 44
+			30 b0 30 b0  f7 c4 d5 5c  00 be 29 ff  f0 d0 ff ff
+		];
+
+		size = <67108864>;
+		has-dpd;
+		t-enter-dpd = <10000>;
+		t-exit-dpd = <35000>;
+	};
+};
+
+&adc {
+	status = "okay";
+};
diff --git a/boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuapp.yaml b/boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuapp.yaml
new file mode 100644
index 00000000000..87fee9c3d62
--- /dev/null
+++ b/boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuapp.yaml
@@ -0,0 +1,24 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: ophelia4ev/nrf54l15/cpuapp
+name: Ophelia4-EV-nRF54l15-Application
+type: mcu
+arch: arm
+toolchain:
+  - gnuarmemb
+  - zephyr
+sysbuild: true
+ram: 188
+flash: 324
+supported:
+  - adc
+  - counter
+  - dmic
+  - gpio
+  - i2c
+  - pwm
+  - retained_mem
+  - spi
+  - watchdog
+  - i2s
diff --git a/boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuapp_defconfig b/boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuapp_defconfig
new file mode 100644
index 00000000000..80a40b5a79d
--- /dev/null
+++ b/boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuapp_defconfig
@@ -0,0 +1,21 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable hardware stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Use internal LFCLK
+CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
diff --git a/boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuflpr.dts b/boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuflpr.dts
new file mode 100644
index 00000000000..b47b81affc4
--- /dev/null
+++ b/boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuflpr.dts
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <nordic/nrf54l15_cpuflpr.dtsi>
+#include "ophelia4ev_common.dtsi"
+
+/ {
+	model = "Ophelia-IV EV FLPR MCU";
+	compatible = "we,ophelia4ev_nrf54l15-cpuflpr";
+
+	chosen {
+		zephyr,console = &uart30;
+		zephyr,shell-uart = &uart30;
+		zephyr,code-partition = &cpuflpr_code_partition;
+		zephyr,flash = &cpuflpr_rram;
+		zephyr,sram = &cpuflpr_sram;
+	};
+};
+
+&cpuflpr_sram {
+	status = "okay";
+
+	/* size must be increased due to booting from SRAM */
+	reg = <0x20028000 DT_SIZE_K(96)>;
+
+	ranges = <0x0 0x20028000 0x18000>;
+};
+
+&cpuflpr_rram {
+	partitions {
+		compatible = "fixed-partitions";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cpuflpr_code_partition: partition@0 {
+			label = "image-0";
+			reg = <0x0 DT_SIZE_K(96)>;
+		};
+	};
+};
+
+&grtc {
+	owned-channels = <3 4>;
+
+	status = "okay";
+};
+
+&uart30 {
+	status = "okay";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpiote30 {
+	status = "okay";
+};
diff --git a/boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuflpr.yaml b/boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuflpr.yaml
new file mode 100644
index 00000000000..a302cf4a192
--- /dev/null
+++ b/boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuflpr.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: ophelia4ev/nrf54l15/cpuflpr
+name: Ophelia4-EV-nRF54L15-Fast-Lightweight-Peripheral-Processor
+type: mcu
+arch: riscv
+toolchain:
+  - zephyr
+sysbuild: true
+ram: 96
+flash: 96
+supported:
+  - counter
+  - gpio
+  - i2c
+  - spi
+  - watchdog
diff --git a/boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuflpr_defconfig b/boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuflpr_defconfig
new file mode 100644
index 00000000000..a0e86949608
--- /dev/null
+++ b/boards/we/ophelia4ev/ophelia4ev_nrf54l15_cpuflpr_defconfig
@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable UART driver
+CONFIG_SERIAL=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable GPIO
+CONFIG_GPIO=y
+
+CONFIG_USE_DT_CODE_PARTITION=y
+
+# Execute from SRAM
+CONFIG_XIP=n
+
+# Use internal LFCLK
+CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y
diff --git a/boards/we/orthosie1ev/doc/index.rst b/boards/we/orthosie1ev/doc/index.rst
index f6fdb4d5546..55f0afdb168 100644
--- a/boards/we/orthosie1ev/doc/index.rst
+++ b/boards/we/orthosie1ev/doc/index.rst
@@ -42,41 +42,7 @@ manual at `ESP32-C3 Technical Reference Manual`_.
 Supported Features
 ==================
 
-Currently Zephyr's ``we_orthosie1ev`` board target supports the following features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| USB-JTAG   | on-chip    | hardware interface                  |
-+------------+------------+-------------------------------------+
-| SPI Master | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| Timers     | on-chip    | counter                             |
-+------------+------------+-------------------------------------+
-| Watchdog   | on-chip    | watchdog                            |
-+------------+------------+-------------------------------------+
-| TRNG       | on-chip    | entropy                             |
-+------------+------------+-------------------------------------+
-| LEDC       | on-chip    | pwm                                 |
-+------------+------------+-------------------------------------+
-| SPI DMA    | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| TWAI       | on-chip    | can                                 |
-+------------+------------+-------------------------------------+
-| USB-CDC    | on-chip    | serial                              |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | adc                                 |
-+------------+------------+-------------------------------------+
-| Wi-Fi      | on-chip    |                                     |
-+------------+------------+-------------------------------------+
-| Bluetooth  | on-chip    |                                     |
-+------------+------------+-------------------------------------+
+.. zephyr:board-supported-hw::
 
 System requirements
 *******************
@@ -98,6 +64,8 @@ below to retrieve those files.
 Building & Flashing
 *******************
 
+.. zephyr:board-supported-runners::
+
 Simple boot
 ===========
 
@@ -139,7 +107,7 @@ To build the sample application using sysbuild use the command:
 .. zephyr-app-commands::
    :tool: west
    :zephyr-app: samples/hello_world
-   :board: orthosie1ev
+   :board: we_orthosie1ev
    :goals: build
    :west-args: --sysbuild
    :compact:
@@ -188,16 +156,16 @@ Build and flash applications as usual (see :ref:`build_an_application` and
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: orthosie1ev
+   :board: we_orthosie1ev
    :goals: build
 
-The usual ``flash`` target will work with the ``orthosie1ev`` board
+The usual ``flash`` target will work with the ``we_orthosie1ev`` board
 configuration. Here is an example for the :zephyr:code-sample:`hello_world`
 application.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: orthosie1ev
+   :board: we_orthosie1ev
    :goals: flash
 
 Open the serial monitor using the following command:
@@ -212,7 +180,7 @@ message in the monitor:
 .. code-block:: console
 
    ***** Booting Zephyr OS vx.x.x-xxx-gxxxxxxxxxxxx *****
-   Hello World! orthosie1ev
+   Hello World! we_orthosie1ev
 
 Debugging
 *********
@@ -229,7 +197,7 @@ Here is an example for building the :zephyr:code-sample:`hello_world` applicatio
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: orthosie1ev
+   :board: we_orthosie1ev
    :goals: build flash
    :gen-args: -DOPENOCD=<path/to/bin/openocd> -DOPENOCD_DEFAULT_PATH=<path/to/openocd/share/openocd/scripts>
 
@@ -237,7 +205,7 @@ You can debug an application in the usual way. Here is an example for the :zephy
 
 .. zephyr-app-commands::
    :zephyr-app: samples/hello_world
-   :board: orthosie1ev
+   :board: we_orthosie1ev
    :goals: debug
 
 References
diff --git a/boards/we/orthosie1ev/we_orthosie1ev.dts b/boards/we/orthosie1ev/we_orthosie1ev.dts
index a0c27fc81bb..b6d2b908988 100644
--- a/boards/we/orthosie1ev/we_orthosie1ev.dts
+++ b/boards/we/orthosie1ev/we_orthosie1ev.dts
@@ -107,3 +107,7 @@
 &esp32_bt_hci {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/we/orthosie1ev/we_orthosie1ev_defconfig b/boards/we/orthosie1ev/we_orthosie1ev_defconfig
index ef633ce56a1..187793c76e8 100644
--- a/boards/we/orthosie1ev/we_orthosie1ev_defconfig
+++ b/boards/we/orthosie1ev/we_orthosie1ev_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/we/proteus2ev/board.yml b/boards/we/proteus2ev/board.yml
index d246b6d1b4d..c6848fd786e 100644
--- a/boards/we/proteus2ev/board.yml
+++ b/boards/we/proteus2ev/board.yml
@@ -1,6 +1,6 @@
 board:
   name: we_proteus2ev
   full_name: Proteus-II-EV
-  vendor: wurth
+  vendor: we
   socs:
   - name: nrf52832
diff --git a/boards/we/proteus2ev/doc/index.rst b/boards/we/proteus2ev/doc/index.rst
index 938258249a1..ac65789b21e 100644
--- a/boards/we/proteus2ev/doc/index.rst
+++ b/boards/we/proteus2ev/doc/index.rst
@@ -34,42 +34,7 @@ is 32.768 kHz. The frequency of the main clock is 32 MHz.
 Supported Features
 ==================
 
-The we_proteus2ev/nrf52832 board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth            |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features are not supported by the Zephyr kernel.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -89,6 +54,8 @@ Push buttons
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``we_proteus2ev/nrf52832`` board configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
diff --git a/boards/we/proteus2ev/we_proteus2ev_nrf52832.yaml b/boards/we/proteus2ev/we_proteus2ev_nrf52832.yaml
index e30510176d0..ca37439689f 100644
--- a/boards/we/proteus2ev/we_proteus2ev_nrf52832.yaml
+++ b/boards/we/proteus2ev/we_proteus2ev_nrf52832.yaml
@@ -10,7 +10,6 @@ flash: 512
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - gpio
diff --git a/boards/we/proteus3ev/board.yml b/boards/we/proteus3ev/board.yml
index fa498a28014..e6a496ef0fa 100644
--- a/boards/we/proteus3ev/board.yml
+++ b/boards/we/proteus3ev/board.yml
@@ -1,6 +1,6 @@
 board:
   name: we_proteus3ev
   full_name: Proteus-III-EV
-  vendor: wurth
+  vendor: we
   socs:
   - name: nrf52840
diff --git a/boards/we/proteus3ev/doc/index.rst b/boards/we/proteus3ev/doc/index.rst
index 8c8b855cc5d..b4d8bd0aede 100644
--- a/boards/we/proteus3ev/doc/index.rst
+++ b/boards/we/proteus3ev/doc/index.rst
@@ -36,43 +36,7 @@ clock is 32 MHz.
 Supported Features
 ==================
 
-The we_proteus3ev/nrf52840 board configuration supports the following
-hardware features:
-
-+-----------+------------+----------------------+
-| Interface | Controller | Driver/Component     |
-+===========+============+======================+
-| ADC       | on-chip    | adc                  |
-+-----------+------------+----------------------+
-| CLOCK     | on-chip    | clock_control        |
-+-----------+------------+----------------------+
-| FLASH     | on-chip    | flash                |
-+-----------+------------+----------------------+
-| GPIO      | on-chip    | gpio                 |
-+-----------+------------+----------------------+
-| I2C(M)    | on-chip    | i2c                  |
-+-----------+------------+----------------------+
-| MPU       | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| NVIC      | on-chip    | arch/arm             |
-+-----------+------------+----------------------+
-| PWM       | on-chip    | pwm                  |
-+-----------+------------+----------------------+
-| RADIO     | on-chip    | Bluetooth,           |
-|           |            | ieee802154           |
-+-----------+------------+----------------------+
-| RTC       | on-chip    | system clock         |
-+-----------+------------+----------------------+
-| RTT       | Segger     | console              |
-+-----------+------------+----------------------+
-| SPI(M/S)  | on-chip    | spi                  |
-+-----------+------------+----------------------+
-| UART      | on-chip    | serial               |
-+-----------+------------+----------------------+
-| WDT       | on-chip    | watchdog             |
-+-----------+------------+----------------------+
-
-Other hardware features are not supported by the Zephyr kernel.
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -91,6 +55,8 @@ Push buttons
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``we_proteus3ev/nrf52840`` board configuration can be
 built, flashed, and debugged in the usual way. See
 :ref:`build_an_application` and :ref:`application_run` for more details on
diff --git a/boards/we/proteus3ev/we_proteus3ev_nrf52840.yaml b/boards/we/proteus3ev/we_proteus3ev_nrf52840.yaml
index 5a771ca28b3..2467fb42795 100644
--- a/boards/we/proteus3ev/we_proteus3ev_nrf52840.yaml
+++ b/boards/we/proteus3ev/we_proteus3ev_nrf52840.yaml
@@ -10,7 +10,6 @@ flash: 1024
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - adc
   - ble
diff --git a/boards/weact/blackpill_f401cc/blackpill_f401cc.yaml b/boards/weact/blackpill_f401cc/blackpill_f401cc.yaml
index b8f88615acd..fafe8e0bd8c 100644
--- a/boards/weact/blackpill_f401cc/blackpill_f401cc.yaml
+++ b/boards/weact/blackpill_f401cc/blackpill_f401cc.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - spi
diff --git a/boards/weact/blackpill_f401cc/doc/index.rst b/boards/weact/blackpill_f401cc/doc/index.rst
index e5ea1e7f699..fbd9ab4cfb3 100644
--- a/boards/weact/blackpill_f401cc/doc/index.rst
+++ b/boards/weact/blackpill_f401cc/doc/index.rst
@@ -37,35 +37,7 @@ hardware components:
 Supported Features
 ==================
 
-The Zephyr blackpill_f401cc board configuration supports the following
-hardware features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| NVIC       | on-chip    | nested vector interrupt controller  |
-+------------+------------+-------------------------------------+
-| SYSTICK    | on-chip    | system clock                        |
-+------------+------------+-------------------------------------+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| FLASH      | on-chip    | flash                               |
-+------------+------------+-------------------------------------+
-| SPI        | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| I2C        | on-chip    | i2c                                 |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | ADC Controller                      |
-+------------+------------+-------------------------------------+
-| USB OTG FS | on-chip    | USB device                          |
-+------------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/weact/blackpill_f401cc/blackpill_f401cc_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -101,6 +73,8 @@ to achieve a stable USB clock (42MHz).
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM
 bootloader, and another by using the SWD debug port (which requires additional
 hardware). Flashing using the ROM bootloader requires a special activation
diff --git a/boards/weact/blackpill_f401ce/blackpill_f401ce.yaml b/boards/weact/blackpill_f401ce/blackpill_f401ce.yaml
index 5f44db28d39..7881fc6071a 100644
--- a/boards/weact/blackpill_f401ce/blackpill_f401ce.yaml
+++ b/boards/weact/blackpill_f401ce/blackpill_f401ce.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - spi
diff --git a/boards/weact/blackpill_f401ce/doc/index.rst b/boards/weact/blackpill_f401ce/doc/index.rst
index aa81976e7d9..54045467bef 100644
--- a/boards/weact/blackpill_f401ce/doc/index.rst
+++ b/boards/weact/blackpill_f401ce/doc/index.rst
@@ -37,35 +37,7 @@ hardware components:
 Supported Features
 ==================
 
-The Zephyr blackpill_f401ce board configuration supports the following
-hardware features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| NVIC       | on-chip    | nested vector interrupt controller  |
-+------------+------------+-------------------------------------+
-| SYSTICK    | on-chip    | system clock                        |
-+------------+------------+-------------------------------------+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| FLASH      | on-chip    | flash                               |
-+------------+------------+-------------------------------------+
-| SPI        | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| I2C        | on-chip    | i2c                                 |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | ADC Controller                      |
-+------------+------------+-------------------------------------+
-| USB OTG FS | on-chip    | USB device                          |
-+------------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/weact/blackpill_f401ce/blackpill_f401ce_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -106,6 +78,8 @@ to achieve a stable USB clock (42MHz).
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM
 bootloader, and another by using the SWD debug port (which requires additional
 hardware). Flashing using the ROM bootloader requires a special activation
diff --git a/boards/weact/blackpill_f411ce/blackpill_f411ce.yaml b/boards/weact/blackpill_f411ce/blackpill_f411ce.yaml
index f93ce7397cd..95a2abe9936 100644
--- a/boards/weact/blackpill_f411ce/blackpill_f411ce.yaml
+++ b/boards/weact/blackpill_f411ce/blackpill_f411ce.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - counter
   - spi
diff --git a/boards/weact/blackpill_f411ce/doc/index.rst b/boards/weact/blackpill_f411ce/doc/index.rst
index f045f331b86..74a6df4200f 100644
--- a/boards/weact/blackpill_f411ce/doc/index.rst
+++ b/boards/weact/blackpill_f411ce/doc/index.rst
@@ -37,35 +37,7 @@ hardware components:
 Supported Features
 ==================
 
-The Zephyr blackpill_f411ce board configuration supports the following
-hardware features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| NVIC       | on-chip    | nested vector interrupt controller  |
-+------------+------------+-------------------------------------+
-| SYSTICK    | on-chip    | system clock                        |
-+------------+------------+-------------------------------------+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| FLASH      | on-chip    | flash                               |
-+------------+------------+-------------------------------------+
-| SPI        | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| I2C        | on-chip    | i2c                                 |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | ADC Controller                      |
-+------------+------------+-------------------------------------+
-| USB OTG FS | on-chip    | USB device                          |
-+------------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/weact/blackpill_f411ce/blackpill_f411ce_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -106,6 +78,8 @@ to achieve a stable USB clock (48MHz).
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM
 bootloader, and another by using the SWD debug port (which requires additional
 hardware). Flashing using the ROM bootloader requires a special activation
diff --git a/boards/weact/mini_stm32h743/doc/index.rst b/boards/weact/mini_stm32h743/doc/index.rst
index 9dc96700d5b..c1ca99c2ea8 100644
--- a/boards/weact/mini_stm32h743/doc/index.rst
+++ b/boards/weact/mini_stm32h743/doc/index.rst
@@ -71,34 +71,7 @@ More information about STM32H743 can be found here:
 Supported Features
 ==================
 
-The mini_stm32h743 board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| WDT       | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| QSPI NOR  | on-chip    | off-chip flash                      |
-+-----------+------------+-------------------------------------+
-| SDMMC     | on-chip    | disk access                         |
-+-----------+------------+-------------------------------------+
-| DISPLAY   | on-chip    | display                             |
-+-----------+------------+-------------------------------------+
-
-Other hardware features have not been enabled yet for this board.
-
-The default configuration per core can be found in the defconfig file:
-``boards/weact/mini_stm32h743/mini_stm32h743_defconfig``
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -137,6 +110,8 @@ Virtual COM port interface. Default communication settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The MiniSTM32H743 Core board facilitates firmware flashing via the USB DFU
 bootloader. This method simplifies the process of updating images, although
 it doesn't provide debugging capabilities. However, the board provides header
diff --git a/boards/weact/mini_stm32h743/mini_stm32h743.yaml b/boards/weact/mini_stm32h743/mini_stm32h743.yaml
index 10edcbb5ed2..7e24ed909c9 100644
--- a/boards/weact/mini_stm32h743/mini_stm32h743.yaml
+++ b/boards/weact/mini_stm32h743/mini_stm32h743.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 512
 flash: 2048
 supported:
diff --git a/boards/weact/mini_stm32h7b0/Kconfig.defconfig b/boards/weact/mini_stm32h7b0/Kconfig.defconfig
index 4286c38d989..661935b903c 100644
--- a/boards/weact/mini_stm32h7b0/Kconfig.defconfig
+++ b/boards/weact/mini_stm32h7b0/Kconfig.defconfig
@@ -22,14 +22,6 @@ endif # LVGL
 
 endif # DISPLAY
 
-if USB_DEVICE_STACK
-
-config UART_CONSOLE
-	default CONSOLE
-
-config USB_DEVICE_INITIALIZE_AT_BOOT
-	default y
-
-endif # USB_DEVICE_STACK
+source "boards/common/usb/Kconfig.cdc_acm_serial.defconfig"
 
 endif # BOARD_MINI_STM32H7B0
diff --git a/boards/weact/mini_stm32h7b0/doc/index.rst b/boards/weact/mini_stm32h7b0/doc/index.rst
index 8cf425d5570..9d1e201b13c 100644
--- a/boards/weact/mini_stm32h7b0/doc/index.rst
+++ b/boards/weact/mini_stm32h7b0/doc/index.rst
@@ -72,34 +72,7 @@ More information about STM32H7BO can be found here:
 Supported Features
 ==================
 
-The ``mini_stm32h7b0`` board target supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| WDT       | on-chip    | watchdog                            |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| QSPI NOR  | on-chip    | off-chip flash                      |
-+-----------+------------+-------------------------------------+
-| SDMMC     | on-chip    | disk access                         |
-+-----------+------------+-------------------------------------+
-| DISPLAY   | on-chip    | display                             |
-+-----------+------------+-------------------------------------+
-
-Other hardware features have not been enabled yet for this board.
-
-The default configuration per core can be found in the defconfig file:
-:zephyr_file:`boards/weact/mini_stm32h7b0/mini_stm32h7b0_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -138,6 +111,8 @@ Virtual COM port interface. Default communication settings are 115200 8N1.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The MiniSTM32H7B0 Core board facilitates firmware flashing via the USB DFU
 bootloader. This method simplifies the process of updating images, although
 it doesn't provide debugging capabilities. However, the board provides header
diff --git a/boards/weact/mini_stm32h7b0/mini_stm32h7b0.dts b/boards/weact/mini_stm32h7b0/mini_stm32h7b0.dts
index cc09b5dda68..cce16f72fc3 100644
--- a/boards/weact/mini_stm32h7b0/mini_stm32h7b0.dts
+++ b/boards/weact/mini_stm32h7b0/mini_stm32h7b0.dts
@@ -15,8 +15,6 @@
 	compatible = "weact,mini-stm32h7b0";
 
 	chosen {
-		zephyr,console = &usb_cdc_acm_uart;
-		zephyr,shell-uart = &usb_cdc_acm_uart;
 		zephyr,sram = &sram0;
 		zephyr,flash = &flash0;
 		zephyr,display = &st7735r_160x80;
@@ -132,12 +130,9 @@ zephyr_udc0: &usbotg_hs {
 	pinctrl-0 = <&usb_otg_hs_dm_pa11 &usb_otg_hs_dp_pa12>;
 	pinctrl-names = "default";
 	status = "okay";
-
-	usb_cdc_acm_uart: cdc_acm_uart {
-		compatible = "zephyr,cdc-acm-uart";
-	};
 };
 
+#include <../boards/common/usb/cdc_acm_serial.dtsi>
 
 &octospi1 {
 	pinctrl-names = "default";
diff --git a/boards/weact/mini_stm32h7b0/mini_stm32h7b0.yaml b/boards/weact/mini_stm32h7b0/mini_stm32h7b0.yaml
index d9904423aa6..6dfd11a35bc 100644
--- a/boards/weact/mini_stm32h7b0/mini_stm32h7b0.yaml
+++ b/boards/weact/mini_stm32h7b0/mini_stm32h7b0.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 512
 flash: 2048
 supported:
diff --git a/boards/weact/mini_stm32h7b0/mini_stm32h7b0_defconfig b/boards/weact/mini_stm32h7b0/mini_stm32h7b0_defconfig
index 77c7a720619..723197901d9 100644
--- a/boards/weact/mini_stm32h7b0/mini_stm32h7b0_defconfig
+++ b/boards/weact/mini_stm32h7b0/mini_stm32h7b0_defconfig
@@ -7,17 +7,5 @@ CONFIG_ARM_MPU=y
 # Enable HW stack protection
 CONFIG_HW_STACK_PROTECTION=y
 
-# Enable UART driver
-CONFIG_SERIAL=y
-
-# Enable console
-CONFIG_CONSOLE=y
-
 # Enable GPIO
 CONFIG_GPIO=y
-
-# Logger cannot use itself to log
-CONFIG_USB_CDC_ACM_LOG_LEVEL_OFF=y
-
-# Enable USB
-CONFIG_USB_DEVICE_STACK=y
diff --git a/boards/weact/stm32f405_core/doc/index.rst b/boards/weact/stm32f405_core/doc/index.rst
index 3afc69b79d0..ec237b6faa6 100644
--- a/boards/weact/stm32f405_core/doc/index.rst
+++ b/boards/weact/stm32f405_core/doc/index.rst
@@ -45,35 +45,7 @@ hardware components:
 Supported Features
 ==================
 
-The Zephyr weact_stm32f405_core board configuration supports the following
-hardware features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| NVIC       | on-chip    | nested vector interrupt controller  |
-+------------+------------+-------------------------------------+
-| SYSTICK    | on-chip    | system clock                        |
-+------------+------------+-------------------------------------+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| PINMUX     | on-chip    | pinmux                              |
-+------------+------------+-------------------------------------+
-| FLASH      | on-chip    | flash                               |
-+------------+------------+-------------------------------------+
-| SPI        | on-chip    | spi                                 |
-+------------+------------+-------------------------------------+
-| I2C        | on-chip    | i2c                                 |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | ADC Controller                      |
-+------------+------------+-------------------------------------+
-| USB OTG FS | on-chip    | USB device                          |
-+------------+------------+-------------------------------------+
-
-The default configuration can be found in
-:zephyr_file:`boards/weact/stm32f405_core/weact_stm32f405_core_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -103,6 +75,8 @@ to achieve a stable USB clock (48MHz).
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 There are 2 main entry points for flashing STM32F4X SoCs, one using the ROM
 bootloader, and another by using the SWD debug port (which requires additional
 hardware). Flashing using the ROM bootloader requires a special activation
diff --git a/boards/weact/stm32f405_core/weact_stm32f405_core.yaml b/boards/weact/stm32f405_core/weact_stm32f405_core.yaml
index e1f98a41ce4..c1854ca57f7 100644
--- a/boards/weact/stm32f405_core/weact_stm32f405_core.yaml
+++ b/boards/weact/stm32f405_core/weact_stm32f405_core.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 128
 flash: 1024
 supported:
diff --git a/boards/weact/stm32g431_core/doc/index.rst b/boards/weact/stm32g431_core/doc/index.rst
index 862398794f6..985d00b1a10 100644
--- a/boards/weact/stm32g431_core/doc/index.rst
+++ b/boards/weact/stm32g431_core/doc/index.rst
@@ -28,28 +28,7 @@ considered reserved for USB-C and not available for other applications.
 Supported Features
 ==================
 
-The Zephyr weact_stm32g431_core board configuration supports the following hardware
-features:
-
-+------------+------------+-------------------------------------+
-| Interface  | Controller | Driver/Component                    |
-+============+============+=====================================+
-| NVIC       | on-chip    | nested vector interrupt controller  |
-+------------+------------+-------------------------------------+
-| UART       | on-chip    | serial port                         |
-+------------+------------+-------------------------------------+
-| GPIO       | on-chip    | gpio                                |
-+------------+------------+-------------------------------------+
-| ADC        | on-chip    | ADC Controller                      |
-+------------+------------+-------------------------------------+
-| USB        | on-chip    | USB device                          |
-+------------+------------+-------------------------------------+
-| UCPD       | on-chip    | ucpd                                |
-+------------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-
-:zephyr_file:`boards/weact/stm32g431_core/weact_stm32g431_core_defconfig`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -101,6 +80,8 @@ PLL instead of the internal 48 MHz oscillator.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 The MCU is normally programmed using the ROM bootloader or the exposed SWD port.
 
 Please note that some laptops may not detect the ROM bootloader correctly if the CCx
diff --git a/boards/weact/stm32g431_core/weact_stm32g431_core.yaml b/boards/weact/stm32g431_core/weact_stm32g431_core.yaml
index 91886ad0ea5..5392afdbd4b 100644
--- a/boards/weact/stm32g431_core/weact_stm32g431_core.yaml
+++ b/boards/weact/stm32g431_core/weact_stm32g431_core.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 32
 flash: 128
 supported:
diff --git a/boards/weact/stm32h5_core/Kconfig.weact_stm32h5_core b/boards/weact/stm32h5_core/Kconfig.weact_stm32h5_core
new file mode 100644
index 00000000000..999012b1955
--- /dev/null
+++ b/boards/weact/stm32h5_core/Kconfig.weact_stm32h5_core
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Kacper Brzostowski
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_WEACT_STM32H5_CORE
+	select SOC_STM32H562XX
diff --git a/boards/weact/stm32h5_core/board.cmake b/boards/weact/stm32h5_core/board.cmake
new file mode 100644
index 00000000000..2288b4765ef
--- /dev/null
+++ b/boards/weact/stm32h5_core/board.cmake
@@ -0,0 +1,7 @@
+# Copyright (c) 2025 Kacper Brzostowski
+# SPDX-License-Identifier: Apache-2.0
+
+board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse")
+
+# Keep first
+include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake)
diff --git a/boards/weact/stm32h5_core/board.yml b/boards/weact/stm32h5_core/board.yml
new file mode 100644
index 00000000000..ad89ef70365
--- /dev/null
+++ b/boards/weact/stm32h5_core/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: weact_stm32h5_core
+  full_name: STM32H5 Core Board
+  vendor: weact
+  socs:
+    - name: stm32h562xx
diff --git a/boards/weact/stm32h5_core/doc/index.rst b/boards/weact/stm32h5_core/doc/index.rst
new file mode 100644
index 00000000000..8ff4c916735
--- /dev/null
+++ b/boards/weact/stm32h5_core/doc/index.rst
@@ -0,0 +1,196 @@
+.. zephyr:board:: weact_stm32h5_core
+
+Overview
+********
+
+The ``weact_stm32h5_core`` board is a compact development board equipped with
+an STM32H562RGT6 microcontroller. It features basic set of peripherals:
+user LED and button, microSD |trade| card slot, and combined SWD & UART header.
+
+Key Features
+
+- STM32 microcontroller in LQFP64 package
+- USB OTG or full-speed device
+- 1 user LED
+- User, boot, and reset push-buttons
+- 32.768 kHz and 8MHz HSE crystal oscillators
+- Board connectors:
+
+   - microSD |trade| card
+   - USB Type-C Connector
+   - SWD & UART header for external debugger
+   - 2x 30-pin GPIO connector
+
+More information about the board can be found on the `WeAct GitHub`_.
+
+Hardware
+********
+
+The ``weact_stm32h5_core`` board provides the following hardware components:
+
+   - STM32H562RGT6 in LQFP64 package
+   - ARM 32-bit Cortex-M33 CPU with FPU
+   - CORDIC for trigonometric functions acceleration
+   - FMAC (filter mathematical accelerator)
+   - CRC calculation unit
+   - 240 MHz max CPU frequency
+   - VDD from 1.71 V to 3.6 V
+   - 1MB Flash, 2 banks read-while-write
+   - 640kB SRAM
+   - 4 Kbytes of backup SRAM available in the lowest power modes
+   - 2x watchdogs
+   - 2x SysTick timer
+   - 32-bit timers (2)
+   - 16-bit advanced motor control timers (2)
+   - 16-bit low power timers (6)
+   - 16-bit timers (10)
+   - 1x USB Type-C / USB power-delivery controller
+   - 1x USB 2.0 full-speed host and device
+   - 4x I2C FM+ interfaces (SMBus/PMBus)
+   - 1x I3C interface
+   - 12x U(S)ARTS (ISO7816 interface, LIN, IrDA, modem control)
+   - 1x LP UART
+   - 6x SPIs including 3 muxed with full-duplex I2S
+   - 2x SAI
+   - 1x FDCAN
+   - Flexible external memory controller with up to 16-bit data bus: SRAM, PSRAM, FRAM, SDRAM/LPSDR SDRAM, NOR/NAND memories
+   - 1x OCTOSPI memory interface with on-the-fly decryption and support for serial PSRAM/NAND/NOR, Hyper RAM/Flash frame formats
+   - 1x SD/SDIO/MMC interfaces
+   - 1x HDMI-CEC
+   - 2x 12-bit ADC with up to 5 MSPS in 12-bit
+   - 1x 12-bit D/A with 2 channels
+   - 1x Digital temperature sensor
+
+More information about STM32H562RG can be found here:
+
+- `STM32H562RG on www.st.com`_
+- `STM32H562 reference manual`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Pin Mapping
+===========
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+The ``weact_stm32h5_core`` board is configured as follows
+
+- USER_LED : PB2
+- USER_PB : PC13
+- SDMMC1 CLK/DCMD/CD/D0/D1/D2/D3 : PC12/PD2/PD4/PC8/PC9/PC10/PC11 (microSD card)
+- USB DM/DP : PA11/PA12 (USB CDC ACM)
+- UART on debug header : RX/TX - pA10/PA9
+
+System Clock
+============
+
+The STM32H562RG System Clock can be driven by an internal or external oscillator,
+as well as by the main PLL clock. By default, the System clock is driven
+by the PLL clock at 240MHz. PLL clock is fed by a 8MHz external clock.
+
+Serial Port (USB CDC ACM)
+=========================
+
+The Zephyr console output is assigned to the USB CDC ACM virtual serial port.
+Virtual COM port interface. Default communication settings are 115200 8N1.
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+The ``weact_stm32h5_core`` board facilitates firmware flashing via the USB DFU
+bootloader. This method simplifies the process of updating images, although
+it doesn't provide debugging capabilities. However, the board provides header
+pins for the Serial Wire Debug (SWD) interface, which can be used to connect
+an external debugger, such as ST-Link.
+
+Flashing
+========
+
+To activate the bootloader, follow these steps:
+
+1. Press and hold the BOOT0 key.
+2. While still holding the BOOT0 key, press and release the RESET key.
+3. Wait for 0.5 seconds, then release the BOOT0 key.
+
+Upon successful execution of these steps, the device will transition into
+bootloader mode and present itself as a USB DFU Mode device. You can program
+the device using the west tool or the STM32CubeProgrammer.
+
+Flashing an application to ``weact_stm32h5_core``
+-------------------------------------------------
+
+Here is an example for the :zephyr:code-sample:`hello_world` application.
+
+First, put the board in bootloader mode as described above. Then build and flash
+the application in the usual way. Just add ``CONFIG_BOOT_DELAY=5000`` to the
+configuration, so that USB CDC ACM is initialized before any text is printed,
+as below:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: weact_stm32h5_core
+   :goals: build flash
+   :gen-args: -DCONFIG_BOOT_DELAY=5000
+
+Run a serial host program to connect with your board:
+
+.. code-block:: console
+
+   $ minicom -D <tty_device> -b 115200
+
+Then, press the RESET button, you should see the following message after few seconds:
+
+.. code-block:: console
+
+   Hello World! weact_stm32h5_core
+
+Replace :code:`<tty_device>` with the port where the board can be found.
+For example, under Linux, :code:`/dev/ttyACM0`.
+
+Debugging
+---------
+
+This current Zephyr port does not support debugging.
+
+Testing the LEDs in the ``weact_stm32h5_core``
+**********************************************
+
+There is a sample that allows to test that LED on the board are working
+properly with Zephyr:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: weact_stm32h5_core
+   :goals: build flash
+   :gen-args: -DCONFIG_BOOT_DELAY=5000
+
+You can build and flash the examples to make sure Zephyr is running correctly on
+your board. The LED definitions can be found in
+:zephyr_file:`boards/weact/stm32h5_core/weact_stm32h5_core.dts`.
+
+Testing shell over USB in the ``weact_stm32h5_core``
+****************************************************
+
+There is a sample that allows to test shell interface over USB CDC ACM interface
+with Zephyr:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/subsys/shell/shell_module
+   :board: weact_stm32h5_core
+   :goals: build flash
+   :gen-args: -DCONFIG_BOOT_DELAY=5000
+
+.. _WeAct GitHub:
+   https://github.com/WeActStudio/WeActStudio.STM32H5_64Pin_CoreBoard
+
+.. _STM32H562RG on www.st.com:
+   https://www.st.com/en/microcontrollers-microprocessors/stm32h562rg.html
+
+.. _STM32H562 reference manual:
+   https://www.st.com/resource/en/reference_manual/rm0481-stm32h52333xx-stm32h56263xx-and-stm32h573xx-armbased-32bit-mcus-stmicroelectronics.pdf
diff --git a/boards/weact/stm32h5_core/weact_stm32h5_core.dts b/boards/weact/stm32h5_core/weact_stm32h5_core.dts
new file mode 100644
index 00000000000..1d39eea4c20
--- /dev/null
+++ b/boards/weact/stm32h5_core/weact_stm32h5_core.dts
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2025 Kacper Brzostowski
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/h5/stm32h562Xg.dtsi>
+#include <st/h5/stm32h562rgtx-pinctrl.dtsi>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "WeAct Studio STM32H5 Core Board";
+	compatible = "weact,stm32h5-core";
+
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+		zephyr,code-partition = &slot0_partition;
+		zephyr,sram = &sram1;
+		zephyr,flash = &flash0;
+	};
+
+	aliases {
+		led0 = &led_0;
+		sw0 = &button_0;
+		watchdog0 = &iwdg;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led_0: led0 {
+			gpios = <&gpiob 2 GPIO_ACTIVE_HIGH>;
+			label = "User LED";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		button_0: button0 {
+			label = "User Button";
+			gpios = <&gpioc 13 (GPIO_PULL_DOWN | GPIO_ACTIVE_HIGH)>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+};
+
+&sdmmc1 {
+	pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9
+				&sdmmc1_d2_pc10 &sdmmc1_d3_pc11
+				&sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>;
+	cd-gpios = <&gpioa 8 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default";
+	cd-gpios = <&gpioa 8 (GPIO_ACTIVE_HIGH | GPIO_PULL_UP)>;
+	status = "okay";
+};
+
+&clk_lsi {
+	status = "okay";
+};
+
+&clk_lse {
+	status = "okay";
+};
+
+&clk_hsi {
+	status = "okay";
+};
+
+&clk_hse {
+	status = "okay";
+	clock-frequency = <DT_FREQ_M(8)>;
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(240)>;
+	ahb-prescaler = <1>;
+	apb1-prescaler = <2>;
+	apb2-prescaler = <1>;
+	apb3-prescaler = <2>;
+};
+
+&pll {
+	div-m = <2>;
+	mul-n = <120>;
+	div-p = <2>;
+	div-q = <3>;
+	div-r = <2>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&rtc {
+	clocks = <&rcc STM32_CLOCK_BUS_APB3 0x00200000>,
+			<&rcc STM32_SRC_LSE RTC_SEL(1)>;
+	status = "okay";
+};
+
+stm32_lp_tick_source: &lptim4 {
+	clocks = <&rcc STM32_CLOCK_BUS_APB3 0x2000>,
+			<&rcc STM32_SRC_LSI LPTIM4_SEL(4)>;
+	status = "okay";
+};
+
+&iwdg {
+	status = "okay";
+};
+
+&usart1 {
+	status = "okay";
+	pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+};
+
+&rng {
+	status = "okay";
+};
+
+&spi1 {
+	pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpioa 4 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+	status = "okay";
+};
+
+&fdcan1 {
+	pinctrl-0 = <&fdcan1_rx_pb8 &fdcan1_tx_pb7>;
+	pinctrl-names = "default";
+	clocks = <&rcc STM32_CLOCK_BUS_APB1_2 0x00000200>,
+		<&rcc STM32_SRC_PLL1_Q FDCAN_SEL(1)>;
+	clk-divider = <2>;
+	status = "okay";
+};
+
+zephyr_udc0: &usb {
+	pinctrl-0 = <&usb_dm_pa11 &usb_dp_pa12>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 DT_SIZE_K(64)>;
+		};
+
+		slot0_partition: partition@10000 {
+			label = "image-0";
+			reg = <0x00010000 DT_SIZE_K(448)>;
+		};
+
+		slot1_partition: partition@80000 {
+			label = "image-1";
+			reg = <0x00080000 DT_SIZE_K(448)>;
+		};
+
+		storage_partition: partition@f0000 {
+			label = "storage";
+			reg = <0x000f0000 DT_SIZE_K(64)>;
+		};
+	};
+};
diff --git a/boards/weact/stm32h5_core/weact_stm32h5_core.yaml b/boards/weact/stm32h5_core/weact_stm32h5_core.yaml
new file mode 100644
index 00000000000..942b2f55025
--- /dev/null
+++ b/boards/weact/stm32h5_core/weact_stm32h5_core.yaml
@@ -0,0 +1,20 @@
+identifier: weact_stm32h5_core
+name: WeAct Studio STM32H5 Core Board
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+ram: 640
+flash: 1024
+supported:
+  - gpio
+  - can
+  - uart
+  - entropy
+  - spi
+  - usb_device
+  - rtc
+  - watchdog
+vendor: weact
diff --git a/boards/weact/stm32h5_core/weact_stm32h5_core_defconfig b/boards/weact/stm32h5_core/weact_stm32h5_core_defconfig
new file mode 100644
index 00000000000..4b8a61df364
--- /dev/null
+++ b/boards/weact/stm32h5_core/weact_stm32h5_core_defconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2025 Kacper Brzostowski
+# SPDX-License-Identifier: Apache-2.0
+
+# Enable uart driver
+CONFIG_SERIAL=y
+
+# Console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Enable MPU
+CONFIG_ARM_MPU=y
+
+# Enable HW stack protection
+CONFIG_HW_STACK_PROTECTION=y
+
+# Enable GPIO
+CONFIG_GPIO=y
diff --git a/boards/weact/usb2canfdv1/doc/index.rst b/boards/weact/usb2canfdv1/doc/index.rst
index 1ea39dcd4be..807e44659ce 100644
--- a/boards/weact/usb2canfdv1/doc/index.rst
+++ b/boards/weact/usb2canfdv1/doc/index.rst
@@ -15,28 +15,7 @@ terminal block for connecting to the CAN bus, and three LEDs.
 Supported Features
 ==================
 
-The ``usb2canfdv1`` board configuration supports the following hardware features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| FLASH     | on-chip    | flash memory                        |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | USB                                 |
-+-----------+------------+-------------------------------------+
-| FDCAN1    | on-chip    | CAN controller                      |
-+-----------+------------+-------------------------------------+
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/weact/usb2canfdv1/usb2canfdv1_defconfig`.
-
-Other hardware features are not currently supported by the port.
+.. zephyr:board-supported-hw::
 
 System Clock
 ============
@@ -48,6 +27,8 @@ MHz.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
 
diff --git a/boards/weact/usb2canfdv1/usb2canfdv1.yaml b/boards/weact/usb2canfdv1/usb2canfdv1.yaml
index 8fb61f88e14..34d66235b14 100644
--- a/boards/weact/usb2canfdv1/usb2canfdv1.yaml
+++ b/boards/weact/usb2canfdv1/usb2canfdv1.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 144
 flash: 128
 supported:
diff --git a/boards/wemos/esp32s2_lolin_mini/doc/index.rst b/boards/wemos/esp32s2_lolin_mini/doc/index.rst
index c9ce4b23068..9fadc278205 100644
--- a/boards/wemos/esp32s2_lolin_mini/doc/index.rst
+++ b/boards/wemos/esp32s2_lolin_mini/doc/index.rst
@@ -27,11 +27,19 @@ The features include the following:
   - DAC
   - LED PWM with up to 8 channels
 
+Hardware
+********
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
 System requirements
 *******************
 
 Prerequisites
--------------
+=============
 
 Espressif HAL requires WiFi and Bluetooth binary blobs in order work. Run the command
 below to retrieve those files.
@@ -45,7 +53,9 @@ below to retrieve those files.
    It is recommended running the command above after :file:`west update`.
 
 Building & Flashing
--------------------
+===================
+
+.. zephyr:board-supported-runners::
 
 Build and flash applications as usual (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts
index 66761886e55..3605429bfa4 100644
--- a/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts
+++ b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini.dts
@@ -22,7 +22,7 @@
 	};
 
 	chosen {
-		zephyr,sram = &sram0;
+		zephyr,sram = &sram1;
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
 		zephyr,flash = &flash0;
@@ -89,3 +89,7 @@
 &wdt0 {
 	status = "okay";
 };
+
+&wifi {
+	status = "okay";
+};
diff --git a/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini_defconfig b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini_defconfig
index f029cac9e9e..e192c240251 100644
--- a/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini_defconfig
+++ b/boards/wemos/esp32s2_lolin_mini/esp32s2_lolin_mini_defconfig
@@ -1,7 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
 
-CONFIG_MAIN_STACK_SIZE=2048
-
 CONFIG_CONSOLE=y
 CONFIG_SERIAL=y
 CONFIG_UART_CONSOLE=y
diff --git a/boards/witte/linum/doc/index.rst b/boards/witte/linum/doc/index.rst
index 43466abdfc8..e5da27ad8c6 100644
--- a/boards/witte/linum/doc/index.rst
+++ b/boards/witte/linum/doc/index.rst
@@ -47,50 +47,7 @@ More information about the board, can be found at the `Witte Linum website`_.
 Supported Features
 ==================
 
-The Zephyr Linum board configuration supports the following hardware
-features:
-
-+-----------+------------+-------------------------------------+
-| Interface | Controller | Driver/Component                    |
-+===========+============+=====================================+
-| NVIC      | on-chip    | nested vector interrupt controller  |
-+-----------+------------+-------------------------------------+
-| UART      | on-chip    | serial port                         |
-+-----------+------------+-------------------------------------+
-| PINMUX    | on-chip    | pinmux                              |
-+-----------+------------+-------------------------------------+
-| GPIO      | on-chip    | gpio                                |
-+-----------+------------+-------------------------------------+
-| RTC       | on-chip    | counter                             |
-+-----------+------------+-------------------------------------+
-| I2C       | on-chip    | i2c                                 |
-+-----------+------------+-------------------------------------+
-| PWM       | on-chip    | pwm                                 |
-+-----------+------------+-------------------------------------+
-| ADC       | on-chip    | adc                                 |
-+-----------+------------+-------------------------------------+
-| RNG       | on-chip    | True Random number generator        |
-+-----------+------------+-------------------------------------+
-| ETHERNET  | on-chip    | ethernet                            |
-+-----------+------------+-------------------------------------+
-| SPI       | on-chip    | spi                                 |
-+-----------+------------+-------------------------------------+
-| USB       | on-chip    | usb_device                          |
-+-----------+------------+-------------------------------------+
-| CAN/CANFD | on-chip    | canbus                              |
-+-----------+------------+-------------------------------------+
-| LTDC      | on-chip    | LCD Interface                       |
-+-----------+------------+-------------------------------------+
-| FMC       | on-chip    | memc (SDRAM)                        |
-+-----------+------------+-------------------------------------+
-| SDMMC     | on-chip    | disk access                         |
-+-----------+------------+-------------------------------------+
-
-Other hardware features are not yet supported on this Zephyr port.
-
-The default configuration can be found in the defconfig file:
-:zephyr_file:`boards/witte/linum/linum_defconfig`
-
+.. zephyr:board-supported-hw::
 
 Default Zephyr Peripheral Mapping:
 ----------------------------------
@@ -348,6 +305,8 @@ driven by the PLL clock at 480MHz, driven by an 25MHz high-speed external clock.
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Applications for the ``linum`` board configuration can be built and
 flashed in the usual way (see :ref:`build_an_application` and
 :ref:`application_run` for more details).
diff --git a/boards/witte/linum/linum.dts b/boards/witte/linum/linum.dts
index fe2280ec117..0453b7ab568 100644
--- a/boards/witte/linum/linum.dts
+++ b/boards/witte/linum/linum.dts
@@ -238,6 +238,8 @@ zephyr_udc0: &usbotg_fs {
 		     &eth_txd0_pg13
 		     &eth_txd1_pg14>;
 	pinctrl-names = "default";
+	phy-connection-type = "rmii";
+	phy-handle = <&eth_phy>;
 };
 
 &mdio {
@@ -245,10 +247,9 @@ zephyr_udc0: &usbotg_fs {
 	pinctrl-0 = <&eth_mdio_pa2 &eth_mdc_pc1>;
 	pinctrl-names = "default";
 
-	ethernet-phy@0 {
+	eth_phy: ethernet-phy@0 {
 		compatible = "microchip,ksz8081";
 		reg = <0x00>;
-		status = "okay";
 		microchip,interface-type = "rmii-25MHz";
 	};
 };
diff --git a/boards/witte/linum/linum.yaml b/boards/witte/linum/linum.yaml
index 3242d570583..6b2e6b1b1c7 100644
--- a/boards/witte/linum/linum.yaml
+++ b/boards/witte/linum/linum.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 512
 flash: 2048
 supported:
diff --git a/boards/wiznet/w5500_evb_pico/board.yml b/boards/wiznet/w5500_evb_pico/board.yml
index eb4eed60b88..e80be185286 100644
--- a/boards/wiznet/w5500_evb_pico/board.yml
+++ b/boards/wiznet/w5500_evb_pico/board.yml
@@ -1,6 +1,6 @@
 board:
   name: w5500_evb_pico
-  full_name: W5500 Evaluation Pico
+  full_name: W5500-EVB-Pico
   vendor: wiznet
   socs:
   - name: rp2040
diff --git a/boards/wiznet/w5500_evb_pico/doc/index.rst b/boards/wiznet/w5500_evb_pico/doc/index.rst
index 4763f5e5398..c05edf5a818 100644
--- a/boards/wiznet/w5500_evb_pico/doc/index.rst
+++ b/boards/wiznet/w5500_evb_pico/doc/index.rst
@@ -1,7 +1,4 @@
-.. _w5500_evb_pico:
-
-Wiznet W5500 Evaluation Pico
-############################
+.. zephyr:board:: w5500_evb_pico
 
 Overview
 ********
@@ -30,67 +27,10 @@ Hardware
 - 1 Watchdog timer peripheral
 - Wiznet W5500 Ethernet MAC/PHY
 
-
-.. figure:: img/w5500_evb_pico_side.png
-     :align: center
-     :alt: W5500 Evaluation Board
-
-     Wiznet W5500_EVB_PICO evaluation board (Image courtesy of Wiznet)
-
 Supported Features
 ==================
 
-The w5500_evb_pico board configuration supports the following
-hardware features:
-
-.. list-table::
-   :header-rows: 1
-
-   * - Peripheral
-     - Kconfig option
-     - Devicetree compatible
-   * - NVIC
-     - N/A
-     - :dtcompatible:`arm,v6m-nvic`
-   * - UART
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`raspberrypi,pico-uart`
-   * - GPIO
-     - :kconfig:option:`CONFIG_GPIO`
-     - :dtcompatible:`raspberrypi,pico-gpio`
-   * - ADC
-     - :kconfig:option:`CONFIG_ADC`
-     - :dtcompatible:`raspberrypi,pico-adc`
-   * - I2C
-     - :kconfig:option:`CONFIG_I2C`
-     - :dtcompatible:`snps,designware-i2c`
-   * - SPI
-     - :kconfig:option:`CONFIG_SPI`
-     - :dtcompatible:`raspberrypi,pico-spi`
-   * - USB Device
-     - :kconfig:option:`CONFIG_USB_DEVICE_STACK`
-     - :dtcompatible:`raspberrypi,pico-usbd`
-   * - HWINFO
-     - :kconfig:option:`CONFIG_HWINFO`
-     - N/A
-   * - Watchdog Timer (WDT)
-     - :kconfig:option:`CONFIG_WATCHDOG`
-     - :dtcompatible:`raspberrypi,pico-watchdog`
-   * - PWM
-     - :kconfig:option:`CONFIG_PWM`
-     - :dtcompatible:`raspberrypi,pico-pwm`
-   * - Flash
-     - :kconfig:option:`CONFIG_FLASH`
-     - :dtcompatible:`raspberrypi,pico-flash`
-   * - UART (PIO)
-     - :kconfig:option:`CONFIG_SERIAL`
-     - :dtcompatible:`raspberrypi,pico-uart-pio`
-   * - SPI (PIO)
-     - :kconfig:option:`CONFIG_SPI`
-     - :dtcompatible:`raspberrypi,pico-spi-pio`
-   * - W5500 Ethernet
-     - :kconfig:option:`CONFIG_NETWORKING`
-     - :dtcompatible:`wiznet,w5500`
+.. zephyr:board-supported-hw::
 
 Pin Mapping
 ===========
@@ -134,6 +74,8 @@ Default Zephyr Peripheral Mapping:
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 
@@ -172,7 +114,7 @@ interface that can be used to program and debug the on board RP2040. This
 interface can be utilized by OpenOCD. To use it with the RP2040, OpenOCD
 version 0.12.0 or later is needed.
 
-If you are using a Debian based system (including RaspberryPi OS, Ubuntu. and
+If you are using a Debian based system (including Raspberry Pi OS, Ubuntu, and
 more), using the `pico_setup.sh`_ script is a convenient way to set up the
 forked version of OpenOCD.
 
diff --git a/boards/wiznet/w5500_evb_pico/w5500_evb_pico.yaml b/boards/wiznet/w5500_evb_pico/w5500_evb_pico.yaml
index 85246c0ef1d..aaa9c3637ef 100644
--- a/boards/wiznet/w5500_evb_pico/w5500_evb_pico.yaml
+++ b/boards/wiznet/w5500_evb_pico/w5500_evb_pico.yaml
@@ -7,7 +7,6 @@ ram: 264
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 supported:
   - uart
   - gpio
diff --git a/boards/wiznet/w5500_evb_pico2/Kconfig.defconfig b/boards/wiznet/w5500_evb_pico2/Kconfig.defconfig
new file mode 100644
index 00000000000..1af3e24b6f0
--- /dev/null
+++ b/boards/wiznet/w5500_evb_pico2/Kconfig.defconfig
@@ -0,0 +1,19 @@
+# Copyright (c) 2025 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_W5500_EVB_PICO2
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+endif # NETWORKING
+
+config USB_SELF_POWERED
+	default n
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 150000000
+
+endif # BOARD_W5500_EVB_PICO2
diff --git a/boards/wiznet/w5500_evb_pico2/Kconfig.w5500_evb_pico2 b/boards/wiznet/w5500_evb_pico2/Kconfig.w5500_evb_pico2
new file mode 100644
index 00000000000..ef3da1e97c3
--- /dev/null
+++ b/boards/wiznet/w5500_evb_pico2/Kconfig.w5500_evb_pico2
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_W5500_EVB_PICO2
+	select SOC_RP2350A_M33 if BOARD_W5500_EVB_PICO2_RP2350A_M33
diff --git a/boards/wiznet/w5500_evb_pico2/board.cmake b/boards/wiznet/w5500_evb_pico2/board.cmake
new file mode 100644
index 00000000000..feae063129a
--- /dev/null
+++ b/boards/wiznet/w5500_evb_pico2/board.cmake
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: Apache-2.0
+
+if("${RPI_PICO_DEBUG_ADAPTER}" STREQUAL "")
+	set(RPI_PICO_DEBUG_ADAPTER "cmsis-dap")
+endif()
+
+board_runner_args(openocd --cmd-pre-init "source [find interface/${RPI_PICO_DEBUG_ADAPTER}.cfg]")
+board_runner_args(openocd --cmd-pre-init "source [find target/rp2350.cfg]")
+
+# The adapter speed is expected to be set by interface configuration.
+# The Raspberry Pi's OpenOCD fork doesn't, so match their documentation at
+# https://www.raspberrypi.com/documentation/microcontrollers/debug-probe.html#debugging-with-swd
+board_runner_args(openocd --cmd-pre-init "set_adapter_speed_if_not_set 5000")
+
+board_runner_args(uf2 "--board-id=RP2350")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/uf2.board.cmake)
diff --git a/boards/wiznet/w5500_evb_pico2/board.yml b/boards/wiznet/w5500_evb_pico2/board.yml
new file mode 100644
index 00000000000..61a534601dc
--- /dev/null
+++ b/boards/wiznet/w5500_evb_pico2/board.yml
@@ -0,0 +1,6 @@
+board:
+  name: w5500_evb_pico2
+  full_name: W5500-EVB-Pico2
+  vendor: wiznet
+  socs:
+  - name: rp2350a
diff --git a/boards/wiznet/w5500_evb_pico2/doc/img/w5500_evb_pico2.webp b/boards/wiznet/w5500_evb_pico2/doc/img/w5500_evb_pico2.webp
new file mode 100644
index 00000000000..cd0ced64165
Binary files /dev/null and b/boards/wiznet/w5500_evb_pico2/doc/img/w5500_evb_pico2.webp differ
diff --git a/boards/wiznet/w5500_evb_pico2/doc/index.rst b/boards/wiznet/w5500_evb_pico2/doc/index.rst
new file mode 100644
index 00000000000..4ddcdd8d7f6
--- /dev/null
+++ b/boards/wiznet/w5500_evb_pico2/doc/index.rst
@@ -0,0 +1,138 @@
+.. zephyr:board:: w5500_evb_pico2
+
+Overview
+********
+
+W5500-EVB-Pico2 is a microcontroller evaluation board based on the Raspberry
+Pi RP2350A and fully hardwired TCP/IP controller W5500 - and basically works
+the same as Raspberry Pi Pico2 board but with additional Ethernet via W5500.
+The USB bootloader allows the ability to flash without any adapter, in a
+drag-and-drop manner. It is also possible to flash and debug the boards with
+their SWD interface, using an external adapter.
+
+Hardware
+********
+
+- Dual core Arm Cortex-M33 or Hazard3 processor running up to 133MHz
+- 520KB on-chip SRAM
+- 16MB on-board QSPI flash with XIP capabilities
+- 26 GPIO pins
+- 3 Analog inputs
+- 2 UART peripherals
+- 2 SPI controllers
+- 2 I2C controllers
+- 16 PWM channels
+- USB 1.1 controller (host/device)
+- 3 Programmable I/O (PIO) for custom peripherals
+- On-board LED
+- 1 Watchdog timer peripheral
+- Wiznet W5500 Ethernet MAC/PHY
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Pin Mapping
+===========
+
+The peripherals of the RP2350A SoC can be routed to various pins on the board.
+The configuration of these routes can be modified through DTS. Please refer to
+the datasheet to see the possible routings for each peripheral.
+
+External pin mapping on the W5500_EVB_PICO2 is identical to the Raspberry Pi
+Pico2. Since GPIO 25 is routed to the on-board LED on, similar to the Raspberry
+Pi Pico, the blinky example works as intended. The W5500 is routed to the SPI0
+(P16-P19), with the reset and interrupt signal for the W5500 routed to P20 and
+P21, respectively. All of these are shared with the edge connector on the
+board.
+
+Refer to `W55500 Evaluation Board Pico2 Documentation`_ for a board schematic and
+other certifications.
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+.. rst-class:: rst-columns
+
+- UART0_TX : P0
+- UART0_RX : P1
+- I2C0_SDA : P4
+- I2C0_SCL : P5
+- I2C1_SDA : P14
+- I2C1_SCL : P15
+- SPI0_RX : P16
+- SPI0_CSN : P17
+- SPI0_SCK : P18
+- SPI0_TX : P19
+- W5500 Reset : P20
+- W5500 Interrupt : P21
+- ADC_CH0 : P26
+- ADC_CH1 : P27
+- ADC_CH2 : P28
+- ADC_CH3 : P29
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+Flashing
+========
+
+Using OpenOCD
+-------------
+
+The overall explanation regarding flashing and debugging is the same as or
+``rpi_pico``.
+See :ref:`rpi_pico_flashing_using_openocd`. in ``rpi_pico`` documentation.
+
+A typical build command for w5500_evb_pico2 is as follows.
+This assumes a CMSIS-DAP adapter such as the Raspberry Pi Debug Probe,
+but if you are using something else, specify ``RPI_PICO_DEBUG_ADAPTER``.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: w5500_evb_pico2
+   :goals: build flash
+   :gen-args: -DOPENOCD=/usr/local/bin/openocd
+
+Using UF2
+---------
+
+If you don't have an SWD adapter, you can flash the Raspberry Pi Pico with
+a UF2 file. By default, building an app for this board will generate a
+:file:`build/zephyr/zephyr.uf2` file. If the Pico is powered on with the ``BOOTSEL``
+button pressed, it will appear on the host as a mass storage device. The
+UF2 file should be drag-and-dropped to the device, which will flash the Pico.
+
+Debugging
+=========
+
+The SWD interface can also be used to debug the board. To achieve this, you can
+either use SEGGER JLink or OpenOCD.
+
+Using OpenOCD
+-------------
+
+Install OpenOCD as described for flashing the board.
+
+Here is an example for debugging the :zephyr:code-sample:`blinky` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: w5500_evb_pico2
+   :maybe-skip-config:
+   :goals: debug
+   :gen-args: -DOPENOCD=/usr/local/bin/openocd
+
+.. target-notes::
+
+.. _pico_setup.sh:
+  https://raw.githubusercontent.com/raspberrypi/pico-setup/master/pico_setup.sh
+
+.. _Getting Started with Raspberry Pi Pico:
+  https://datasheets.raspberrypi.com/pico/getting-started-with-pico.pdf
+
+.. _W55500 Evaluation Board Pico2 Documentation:
+  https://docs.wiznet.io/Product/iEthernet/W5500/w5500-evb-pico2
diff --git a/boards/wiznet/w5500_evb_pico2/support/openocd.cfg b/boards/wiznet/w5500_evb_pico2/support/openocd.cfg
new file mode 100644
index 00000000000..0f833247bc6
--- /dev/null
+++ b/boards/wiznet/w5500_evb_pico2/support/openocd.cfg
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+# Checking and set 'adapter speed'.
+# Set the adaptor speed, if unset, and given as an argument.
+proc set_adapter_speed_if_not_set { speed } {
+	puts "checking adapter speed..."
+	if { [catch {adapter speed} ret] } {
+		adapter speed $speed
+	}
+}
diff --git a/boards/wiznet/w5500_evb_pico2/w5500_evb_pico2-pinctrl.dtsi b/boards/wiznet/w5500_evb_pico2/w5500_evb_pico2-pinctrl.dtsi
new file mode 100644
index 00000000000..dffd24d8aea
--- /dev/null
+++ b/boards/wiznet/w5500_evb_pico2/w5500_evb_pico2-pinctrl.dtsi
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2021, Yonatan Schachter
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/rpi-pico-rp2350a-pinctrl.h>
+
+&pinctrl {
+	uart0_default: uart0_default {
+		group1 {
+			pinmux = <UART0_TX_P0>;
+		};
+
+		group2 {
+			pinmux = <UART0_RX_P1>;
+			input-enable;
+		};
+	};
+
+	i2c0_default: i2c0_default {
+		group1 {
+			pinmux = <I2C0_SDA_P4>, <I2C0_SCL_P5>;
+			input-enable;
+			input-schmitt-enable;
+		};
+	};
+
+	i2c1_default: i2c1_default {
+		group1 {
+			pinmux = <I2C1_SDA_P6>, <I2C1_SCL_P7>;
+			input-enable;
+			input-schmitt-enable;
+		};
+	};
+
+	spi0_default: spi0_default {
+		group1 {
+			pinmux = <SPI0_CSN_P17>, <SPI0_SCK_P18>, <SPI0_TX_P19>;
+		};
+
+		group2 {
+			pinmux = <SPI0_RX_P16>;
+			input-enable;
+		};
+	};
+
+	pwm_ch4b_default: pwm_ch4b_default {
+		group1 {
+			pinmux = <PWM_4B_P25>;
+		};
+	};
+
+	adc_default: adc_default {
+		group1 {
+			pinmux = <ADC_CH0_P26>, <ADC_CH1_P27>, <ADC_CH2_P28>, <ADC_CH3_P29>;
+			input-enable;
+		};
+	};
+};
diff --git a/boards/wiznet/w5500_evb_pico2/w5500_evb_pico2.dtsi b/boards/wiznet/w5500_evb_pico2/w5500_evb_pico2.dtsi
new file mode 100644
index 00000000000..5a0959d721e
--- /dev/null
+++ b/boards/wiznet/w5500_evb_pico2/w5500_evb_pico2.dtsi
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <freq.h>
+
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/pwm/pwm.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+#include "w5500_evb_pico2-pinctrl.dtsi"
+
+/ {
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+		zephyr,code-partition = &code_partition;
+	};
+
+	pico_header: connector {
+		compatible = "raspberrypi,pico-header";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map = <0 0 &gpio0 0 0>,	/* GP0 */
+			<1 0 &gpio0 1 0>,	/* GP1 */
+			<2 0 &gpio0 2 0>,	/* GP2 */
+			<3 0 &gpio0 3 0>,	/* GP3 */
+			<4 0 &gpio0 4 0>,	/* GP4 */
+			<5 0 &gpio0 5 0>,	/* GP5 */
+			<6 0 &gpio0 6 0>,	/* GP6 */
+			<7 0 &gpio0 7 0>,	/* GP7 */
+			<8 0 &gpio0 8 0>,	/* GP8 */
+			<9 0 &gpio0 9 0>,	/* GP9 */
+			<10 0 &gpio0 10 0>,	/* GP10 */
+			<11 0 &gpio0 11 0>,	/* GP11 */
+			<12 0 &gpio0 12 0>,	/* GP12 */
+			<13 0 &gpio0 13 0>,	/* GP13 */
+			<14 0 &gpio0 14 0>,	/* GP14 */
+			<15 0 &gpio0 15 0>,	/* GP15 */
+			<16 0 &gpio0 16 0>,	/* GP16 */
+			<17 0 &gpio0 17 0>,	/* GP17 */
+			<18 0 &gpio0 18 0>,	/* GP18 */
+			<19 0 &gpio0 19 0>,	/* GP19 */
+			<20 0 &gpio0 20 0>,	/* GP20 */
+			<21 0 &gpio0 21 0>,	/* GP21 */
+			<22 0 &gpio0 22 0>,	/* GP22 */
+			<26 0 &gpio0 26 0>,	/* GP26 */
+			<27 0 &gpio0 27 0>,	/* GP27 */
+			<28 0 &gpio0 28 0>;	/* GP28 */
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led0: led_0 {
+			gpios = <&gpio0 25 GPIO_ACTIVE_HIGH>;
+			label = "LED";
+		};
+	};
+
+	pwm_leds {
+		compatible = "pwm-leds";
+		status = "disabled";
+
+		pwm_led0: pwm_led_0 {
+			pwms = <&pwm 9 PWM_MSEC(20) PWM_POLARITY_NORMAL>;
+			label = "PWM_LED";
+		};
+	};
+
+	aliases {
+		led0 = &led0;
+		pwm-led0 = &pwm_led0;
+		watchdog0 = &wdt0;
+	};
+};
+
+&flash0 {
+	/* 16MB of flash minus the 0x100 used for
+	 * the second stage bootloader
+	 */
+	reg = <0x10000000 DT_SIZE_M(16)>;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* Reserved memory for the second stage bootloader */
+		second_stage_bootloader: partition@0 {
+			label = "second_stage_bootloader";
+			reg = <0x00000000 0x100>;
+			read-only;
+		};
+
+		/*
+		 * Usable flash. Starts at 0x100, after the bootloader. The partition
+		 * size is 16MB minus the 0x100 bytes taken by the bootloader.
+		 */
+		code_partition: partition@100 {
+			label = "code-partition";
+			reg = <0x100 (DT_SIZE_M(16) - 0x100)>;
+			read-only;
+		};
+	};
+};
+
+&uart0 {
+	current-speed = <115200>;
+	status = "okay";
+	pinctrl-0 = <&uart0_default>;
+	pinctrl-names = "default";
+};
+
+&gpio0 {
+	status = "okay";
+};
+
+&spi0 {
+	clock-frequency = <DT_FREQ_M(8)>;
+	status = "okay";
+	pinctrl-0 = <&spi0_default>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
+
+	ethernet: w5500@0 {
+		compatible = "wiznet,w5500";
+		reg = <0x0>;
+		spi-max-frequency = <50000000>;
+		int-gpios = <&gpio0 21 GPIO_ACTIVE_LOW>;
+		reset-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+		local-mac-address = [00 00 00 01 02 03];
+		status = "okay";
+	};
+};
+
+&i2c0 {
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&adc {
+	pinctrl-0 = <&adc_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&pwm {
+	pinctrl-0 = <&pwm_ch4b_default>;
+	pinctrl-names = "default";
+	divider-int-0 = <255>;
+};
+
+&timer0 {
+	status = "okay";
+};
+
+&wdt0 {
+	status = "okay";
+};
+
+zephyr_udc0: &usbd {
+	status = "okay";
+};
+
+pico_spi: &spi0 {};
+pico_i2c0: &i2c0 {};
+pico_i2c1: &i2c1 {};
+pico_serial: &uart0 {};
diff --git a/boards/wiznet/w5500_evb_pico2/w5500_evb_pico2_rp2350a_m33.dts b/boards/wiznet/w5500_evb_pico2/w5500_evb_pico2_rp2350a_m33.dts
new file mode 100644
index 00000000000..88ba8a6d16c
--- /dev/null
+++ b/boards/wiznet/w5500_evb_pico2/w5500_evb_pico2_rp2350a_m33.dts
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <raspberrypi/rpi_pico/rp2350a.dtsi>
+#include <raspberrypi/rpi_pico/m33.dtsi>
+#include "w5500_evb_pico2.dtsi"
diff --git a/boards/wiznet/w5500_evb_pico2/w5500_evb_pico2_rp2350a_m33.yaml b/boards/wiznet/w5500_evb_pico2/w5500_evb_pico2_rp2350a_m33.yaml
new file mode 100644
index 00000000000..a4073e97463
--- /dev/null
+++ b/boards/wiznet/w5500_evb_pico2/w5500_evb_pico2_rp2350a_m33.yaml
@@ -0,0 +1,22 @@
+identifier: w5500_evb_pico2/rp2350a/m33
+name: Wiznet W5500 Evaluation Board with RP2350
+type: mcu
+arch: arm
+flash: 16384
+ram: 520
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - adc
+  - clock
+  - counter
+  - dma
+  - gpio
+  - hwinfo
+  - i2c
+  - pwm
+  - spi
+  - uart
+  - usbd
+  - watchdog
diff --git a/boards/wiznet/w5500_evb_pico2/w5500_evb_pico2_rp2350a_m33_defconfig b/boards/wiznet/w5500_evb_pico2/w5500_evb_pico2_rp2350a_m33_defconfig
new file mode 100644
index 00000000000..aaaa51cbdb9
--- /dev/null
+++ b/boards/wiznet/w5500_evb_pico2/w5500_evb_pico2_rp2350a_m33_defconfig
@@ -0,0 +1,10 @@
+CONFIG_SERIAL=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_GPIO=y
+CONFIG_USE_DT_CODE_PARTITION=y
+CONFIG_BUILD_OUTPUT_UF2=y
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_RESET=y
+CONFIG_CLOCK_CONTROL=y
diff --git a/cmake/bintools/bintools_template.cmake b/cmake/bintools/bintools_template.cmake
index 6fa63080dd9..6617fd77808 100644
--- a/cmake/bintools/bintools_template.cmake
+++ b/cmake/bintools/bintools_template.cmake
@@ -66,6 +66,7 @@
 #   elfconvert_flag_final         : Flags that must always be applied last at the elfconvert command
 #   elfconvert_flag_strip_all     : Flag that is used for stripping all symbols when converting
 #   elfconvert_flag_strip_debug   : Flag that is used to strip debug symbols when converting
+#   elfconvert_flag_strip_unneeded: Flag that is used to strip all unreferenced symbols when converting
 #   elfconvert_flag_compress_debug_sections: Flag that is used to compress debug sections when converting
 #   elfconvert_flag_intarget      : Flag for specifying target used for infile
 #   elfconvert_flag_outtarget     : Flag for specifying target to use for converted file.
@@ -142,6 +143,8 @@ set_property(TARGET bintools PROPERTY elfconvert_command ${CMAKE_COMMAND} -E ech
 set_property(TARGET bintools PROPERTY elfconvert_formats "")
 set_property(TARGET bintools PROPERTY elfconvert_flag "")
 set_property(TARGET bintools PROPERTY elfconvert_flag_final "")
+set_property(TARGET bintools PROPERTY elfconvert_flag_strip_debug "")
+set_property(TARGET bintools PROPERTY elfconvert_flag_strip_unneeded "")
 set_property(TARGET bintools PROPERTY elfconvert_flag_compress_debug_sections "")
 set_property(TARGET bintools PROPERTY elfconvert_flag_outtarget "")
 set_property(TARGET bintools PROPERTY elfconvert_flag_section_remove "")
diff --git a/cmake/bintools/gnu/target_bintools.cmake b/cmake/bintools/gnu/target_bintools.cmake
index 0fa06ea7c32..6bbe8f8a3cf 100644
--- a/cmake/bintools/gnu/target_bintools.cmake
+++ b/cmake/bintools/gnu/target_bintools.cmake
@@ -7,6 +7,7 @@
 #   elfconvert_flag_final         : empty
 #   elfconvert_flag_strip_all     : -S
 #   elfconvert_flag_strip_debug   : -g
+#   elfconvert_flag_strip_unneeded: --strip-unneeded
 #   elfconvert_flag_compress_debug_sections: --compress-debug-sections
 #   elfconvert_flag_intarget      : --input-target=
 #   elfconvert_flag_outtarget     : --output-target=
@@ -34,6 +35,7 @@ set_property(TARGET bintools PROPERTY elfconvert_flag_final "")
 
 set_property(TARGET bintools PROPERTY elfconvert_flag_strip_all "-S")
 set_property(TARGET bintools PROPERTY elfconvert_flag_strip_debug "-g")
+set_property(TARGET bintools PROPERTY elfconvert_flag_strip_unneeded "--strip-unneeded")
 
 set_property(TARGET bintools PROPERTY elfconvert_flag_compress_debug_sections "--compress-debug-sections")
 
diff --git a/cmake/bintools/iar/target.cmake b/cmake/bintools/iar/target.cmake
new file mode 100644
index 00000000000..0ea594503cc
--- /dev/null
+++ b/cmake/bintools/iar/target.cmake
@@ -0,0 +1,44 @@
+# Copyright (c) 2025 IAR Systems AB
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Configures binary tools as GNU binutils
+include(extensions)
+
+# Specifically choose arm-zephyr-eabi from the zephyr sdk for objcopy and friends
+
+if("${IAR_TOOLCHAIN_VARIANT}" STREQUAL "iccarm")
+  set(IAR_ZEPHYR_HOME ${ZEPHYR_SDK_INSTALL_DIR}/arm-zephyr-eabi/bin)
+  set(IAR_GNU_PREFIX arm-zephyr-eabi-)
+else()
+  message(ERROR "IAR_TOOLCHAIN_VARIANT not set")
+endif()
+find_program(CMAKE_OBJCOPY ${IAR_GNU_PREFIX}objcopy PATHS ${IAR_ZEPHYR_HOME} NO_DEFAULT_PATH)
+find_program(CMAKE_OBJDUMP ${IAR_GNU_PREFIX}objdump PATHS ${IAR_ZEPHYR_HOME} NO_DEFAULT_PATH)
+find_program(CMAKE_AS      ${IAR_GNU_PREFIX}as      PATHS ${IAR_ZEPHYR_HOME} NO_DEFAULT_PATH)
+find_program(CMAKE_AR      ${IAR_GNU_PREFIX}ar      PATHS ${IAR_ZEPHYR_HOME} NO_DEFAULT_PATH)
+find_program(CMAKE_RANLIB  ${IAR_GNU_PREFIX}ranlib  PATHS ${IAR_ZEPHYR_HOME} NO_DEFAULT_PATH)
+find_program(CMAKE_READELF ${IAR_GNU_PREFIX}readelf PATHS ${IAR_ZEPHYR_HOME} NO_DEFAULT_PATH)
+find_program(CMAKE_NM      ${IAR_GNU_PREFIX}nm      PATHS ${IAR_ZEPHYR_HOME} NO_DEFAULT_PATH)
+find_program(CMAKE_STRIP   ${IAR_GNU_PREFIX}strip   PATHS ${IAR_ZEPHYR_HOME} NO_DEFAULT_PATH)
+find_program(CMAKE_GDB     ${IAR_GNU_PREFIX}gdb-py  PATHS ${IAR_ZEPHYR_HOME} NO_DEFAULT_PATH)
+
+if(CMAKE_GDB)
+  execute_process(
+    COMMAND ${CMAKE_GDB} --configuration
+    RESULTS_VARIABLE GDB_CFG_ERR
+    OUTPUT_QUIET
+    ERROR_QUIET
+    )
+endif()
+
+if(NOT CMAKE_GDB OR GDB_CFG_ERR)
+  find_program(CMAKE_GDB_NO_PY ${CROSS_COMPILE}gdb PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH)
+
+  if(CMAKE_GDB_NO_PY)
+    set(CMAKE_GDB ${CMAKE_GDB_NO_PY} CACHE FILEPATH "Path to a program." FORCE)
+  endif()
+endif()
+
+# Include bin tool properties
+include(${ZEPHYR_BASE}/cmake/bintools/iar/target_bintools.cmake)
diff --git a/cmake/bintools/iar/target_bintools.cmake b/cmake/bintools/iar/target_bintools.cmake
new file mode 100644
index 00000000000..087bd518df1
--- /dev/null
+++ b/cmake/bintools/iar/target_bintools.cmake
@@ -0,0 +1,135 @@
+# Copyright (c) 2025 IAR Systems AB
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# - elfconvert  : Name of command for elf file conversion.
+#                 In this implementation `objcopy` is used
+#   elfconvert_formats            : Formats supported: ihex, srec, binary
+#   elfconvert_flag               : empty
+#   elfconvert_flag_final         : empty
+#   elfconvert_flag_strip_all     : -S
+#   elfconvert_flag_strip_debug   : -g
+#   elfconvert_flag_intarget      : --input-target=
+#   elfconvert_flag_outtarget     : --output-target=
+#   elfconvert_flag_section_remove: --remove-section=
+#   elfconvert_flag_section_only  : --only-section=
+#   elfconvert_flag_section_rename: --rename-section;
+#   elfconvert_flag_gapfill       : --gap-fill;
+#                                   Note: The ';' will be transformed into an
+#                                   empty space when executed
+#   elfconvert_flag_srec_len      : --srec-len=
+#   elfconvert_flag_infile        : empty, objcopy doesn't take arguments for filenames
+#   elfconvert_flag_outfile       : empty, objcopy doesn't take arguments for filenames
+#
+
+# elfconvert to use for transforming an elf file into another format,
+# such as intel hex, s-rec, binary, etc.
+set_property(TARGET bintools PROPERTY elfconvert_command ${CMAKE_OBJCOPY})
+
+# List of format the tool supports for converting, for example,
+# GNU tools uses objectcopy, which supports the following: ihex, srec, binary
+set_property(TARGET bintools PROPERTY elfconvert_formats ihex srec binary)
+
+set_property(TARGET bintools PROPERTY elfconvert_flag "")
+set_property(TARGET bintools PROPERTY elfconvert_flag_final "")
+
+set_property(TARGET bintools PROPERTY elfconvert_flag_strip_all "-S")
+set_property(TARGET bintools PROPERTY elfconvert_flag_strip_debug "-g")
+
+set_property(TARGET bintools PROPERTY elfconvert_flag_intarget "--input-target=")
+set_property(TARGET bintools PROPERTY elfconvert_flag_outtarget "--output-target=")
+
+set_property(TARGET bintools PROPERTY elfconvert_flag_section_remove "--remove-section=")
+set_property(TARGET bintools PROPERTY elfconvert_flag_section_only "--only-section=")
+set_property(TARGET bintools PROPERTY elfconvert_flag_section_rename "--rename-section;")
+
+set_property(TARGET bintools PROPERTY elfconvert_flag_lma_adjust "--change-section-lma;")
+
+# Note, placing a ';' at the end results in the following param  to be a list,
+# and hence space separated.
+# Thus the command line argument becomes:
+# `--gap-file <value>` instead of `--gap-fill<value>` (The latter would result in an error)
+set_property(TARGET bintools PROPERTY elfconvert_flag_gapfill "--gap-fill;")
+set_property(TARGET bintools PROPERTY elfconvert_flag_srec_len "--srec-len=")
+
+set_property(TARGET bintools PROPERTY elfconvert_flag_infile "")
+set_property(TARGET bintools PROPERTY elfconvert_flag_outfile "")
+
+#
+# - disassembly : Name of command for disassembly of files
+#                 In this implementation `objdump` is used
+#   disassembly_flag               : -d
+#   disassembly_flag_final         : empty
+#   disassembly_flag_inline_source : -S
+#   disassembly_flag_all           : -SDz
+#   disassembly_flag_infile        : empty, objdump doesn't take arguments for filenames
+#   disassembly_flag_outfile       : '>', objdump doesn't take arguments for output file, but result is printed to standard out, and is redirected.
+
+set_property(TARGET bintools PROPERTY disassembly_command ${CMAKE_OBJDUMP})
+set_property(TARGET bintools PROPERTY disassembly_flag -d)
+set_property(TARGET bintools PROPERTY disassembly_flag_final "")
+set_property(TARGET bintools PROPERTY disassembly_flag_inline_source -S)
+set_property(TARGET bintools PROPERTY disassembly_flag_all -SDz)
+
+set_property(TARGET bintools PROPERTY disassembly_flag_infile "")
+set_property(TARGET bintools PROPERTY disassembly_flag_outfile ">;" )
+
+#
+# - strip: Name of command for stripping symbols
+#          In this implementation `strip` is used
+#   strip_flag         : empty
+#   strip_flag_final   : empty
+#   strip_flag_all     : --strip-all
+#   strip_flag_debug   : --strip-debug
+#   strip_flag_dwo     : --strip-dwo
+#   strip_flag_infile  : empty, strip doesn't take arguments for input file
+#   strip_flag_outfile : -o
+
+# This is using strip from bintools.
+set_property(TARGET bintools PROPERTY strip_command ${CMAKE_STRIP})
+
+# Any flag the strip command requires for processing
+set_property(TARGET bintools PROPERTY strip_flag "")
+set_property(TARGET bintools PROPERTY strip_flag_final "")
+
+set_property(TARGET bintools PROPERTY strip_flag_all --strip-all)
+set_property(TARGET bintools PROPERTY strip_flag_debug --strip-debug)
+set_property(TARGET bintools PROPERTY strip_flag_dwo --strip-dwo)
+set_property(TARGET bintools PROPERTY strip_flag_remove_section -R )
+
+set_property(TARGET bintools PROPERTY strip_flag_infile "")
+set_property(TARGET bintools PROPERTY strip_flag_outfile -o )
+
+#
+# - readelf : Name of command for reading elf files.
+#             In this implementation `readelf` is used
+#   readelf_flag          : empty
+#   readelf_flag_final    : empty
+#   readelf_flag_headers  : -e
+#   readelf_flag_infile   : empty, readelf doesn't take arguments for filenames
+#   readelf_flag_outfile  : '>', readelf doesn't take arguments for output
+#                           file, but result is printed to standard out, and
+#                           is redirected.
+
+# This is using readelf from bintools.
+set_property(TARGET bintools PROPERTY readelf_command ${CMAKE_READELF})
+
+set_property(TARGET bintools PROPERTY readelf_flag "")
+set_property(TARGET bintools PROPERTY readelf_flag_final "")
+set_property(TARGET bintools PROPERTY readelf_flag_headers -e)
+
+set_property(TARGET bintools PROPERTY readelf_flag_infile "")
+set_property(TARGET bintools PROPERTY readelf_flag_outfile ">;" )
+
+# Example on how to support dwarfdump instead of readelf
+#set_property(TARGET bintools PROPERTY readelf_command dwarfdump)
+#set_property(TARGET bintools PROPERTY readelf_flag "")
+#set_property(TARGET bintools PROPERTY readelf_flag_headers -E)
+#set_property(TARGET bintools PROPERTY readelf_flag_infile "")
+#set_property(TARGET bintools PROPERTY readelf_flag_outfile "-O file=" )
+
+set_property(TARGET bintools PROPERTY symbols_command ${CMAKE_NM})
+set_property(TARGET bintools PROPERTY symbols_flag "")
+set_property(TARGET bintools PROPERTY symbols_final "")
+set_property(TARGET bintools PROPERTY symbols_infile "")
+set_property(TARGET bintools PROPERTY symbols_outfile ">;" )
diff --git a/cmake/bintools/llvm/target_bintools.cmake b/cmake/bintools/llvm/target_bintools.cmake
index f310d57bf2b..9d8edc46de9 100644
--- a/cmake/bintools/llvm/target_bintools.cmake
+++ b/cmake/bintools/llvm/target_bintools.cmake
@@ -7,6 +7,7 @@
 #   elfconvert_flag_final         : empty
 #   elfconvert_flag_strip_all     : -S
 #   elfconvert_flag_strip_debug   : -g
+#   elfconvert_flag_strip_unneeded: --strip-unneeded
 #   elfconvert_flag_compress_debug_sections: --compress-debug-sections
 #   elfconvert_flag_intarget      : --input-target=
 #   elfconvert_flag_outtarget     : --output-target=
@@ -34,6 +35,7 @@ set_property(TARGET bintools PROPERTY elfconvert_flag_final "")
 
 set_property(TARGET bintools PROPERTY elfconvert_flag_strip_all "-S")
 set_property(TARGET bintools PROPERTY elfconvert_flag_strip_debug "-g")
+set_property(TARGET bintools PROPERTY elfconvert_flag_strip_unneeded "--strip-unneeded")
 
 set_property(TARGET bintools PROPERTY elfconvert_flag_compress_debug_sections "--compress-debug-sections")
 
@@ -44,6 +46,8 @@ set_property(TARGET bintools PROPERTY elfconvert_flag_section_remove "--remove-s
 set_property(TARGET bintools PROPERTY elfconvert_flag_section_only "--only-section=")
 set_property(TARGET bintools PROPERTY elfconvert_flag_section_rename "--rename-section;")
 
+set_property(TARGET bintools PROPERTY elfconvert_flag_lma_adjust "--change-section-lma;")
+
 # llvm-objcopy doesn't support gap fill argument.
 set_property(TARGET bintools PROPERTY elfconvert_flag_gapfill "")
 set_property(TARGET bintools PROPERTY elfconvert_flag_srec_len "--srec-len=")
diff --git a/cmake/compiler/arcmwdt/compiler_flags.cmake b/cmake/compiler/arcmwdt/compiler_flags.cmake
index 7234afc0c80..2827c954e75 100644
--- a/cmake/compiler/arcmwdt/compiler_flags.cmake
+++ b/cmake/compiler/arcmwdt/compiler_flags.cmake
@@ -14,7 +14,8 @@ list(APPEND CXX_EXCLUDED_OPTIONS
 set_compiler_property(PROPERTY no_optimization -O0)
 set_compiler_property(PROPERTY optimization_debug -O0)
 set_compiler_property(PROPERTY optimization_speed -O2)
-set_compiler_property(PROPERTY optimization_size  -Os)
+set_compiler_property(PROPERTY optimization_size -Os)
+set_compiler_property(PROPERTY optimization_fast -O3)
 
 #######################################################
 # This section covers flags related to warning levels #
@@ -165,6 +166,9 @@ set_compiler_property(PROPERTY coverage "")
 # mwdt compiler flags for imacros. The specific header must be appended by user.
 set_compiler_property(PROPERTY imacros -imacros)
 
+# assembler compiler flags for imacros. The specific header must be appended by user.
+set_property(TARGET asm PROPERTY imacros -imacros)
+
 # Security canaries.
 #no support of -mstack-protector-guard=global"
 set_compiler_property(PROPERTY security_canaries -fstack-protector)
@@ -205,8 +209,9 @@ if(CONFIG_ARCMWDT_LIBC)
   set_property(TARGET asm APPEND PROPERTY required "-I${NOSTDINC}")
 endif()
 
-# Remove after testing that -Wshadow works
+# Update after testing that -Wshadow and -Wno-array-bounds works
 set_compiler_property(PROPERTY warning_shadow_variables)
+set_compiler_property(PROPERTY warning_no_array_bounds)
 
 set_compiler_property(PROPERTY no_builtin -fno-builtin)
 set_compiler_property(PROPERTY no_builtin_malloc -fno-builtin-malloc)
diff --git a/cmake/compiler/clang/compiler_flags.cmake b/cmake/compiler/clang/compiler_flags.cmake
index a64150eb58c..05e08d50646 100644
--- a/cmake/compiler/clang/compiler_flags.cmake
+++ b/cmake/compiler/clang/compiler_flags.cmake
@@ -101,20 +101,11 @@ check_set_compiler_property(APPEND PROPERTY warning_dw_3
 
 check_set_compiler_property(PROPERTY warning_extended
                             #FIXME: need to fix all of those
-                            -Wno-sometimes-uninitialized
-                            -Wno-shift-overflow
-                            -Wno-missing-braces
                             -Wno-self-assign
                             -Wno-address-of-packed-member
-                            -Wno-unused-function
                             -Wno-initializer-overrides
                             -Wno-section
-                            -Wno-unknown-warning-option
-                            -Wno-unused-variable
-                            -Wno-format-invalid-specifier
                             -Wno-gnu
-                            # comparison of unsigned expression < 0 is always false
-                            -Wno-tautological-compare
 )
 
 set_compiler_property(PROPERTY warning_error_coding_guideline
diff --git a/cmake/compiler/compiler_flags_template.cmake b/cmake/compiler/compiler_flags_template.cmake
index 447db04a2d3..bd8733ce9d0 100644
--- a/cmake/compiler/compiler_flags_template.cmake
+++ b/cmake/compiler/compiler_flags_template.cmake
@@ -15,6 +15,8 @@ set_compiler_property(PROPERTY optimization_size)
 
 set_compiler_property(PROPERTY optimization_size_aggressive)
 
+set_compiler_property(PROPERTY optimization_fast)
+
 #######################################################
 # This section covers flags related to warning levels #
 #######################################################
@@ -125,6 +127,9 @@ set_property(TARGET compiler-cpp PROPERTY no_threadsafe_statics)
 # Required ASM flags when compiling
 set_property(TARGET asm PROPERTY required)
 
+# GCC compiler flags for imacros. The specific header must be appended by user.
+set_property(TARGET asm PROPERTY imacros)
+
 # Compiler flag for disabling pointer arithmetic warnings
 set_compiler_property(PROPERTY warning_no_pointer_arithmetic)
 
@@ -138,6 +143,8 @@ set_compiler_property(PROPERTY no_global_merge)
 
 # Compiler flag for warning about shadow variables
 set_compiler_property(PROPERTY warning_shadow_variables)
+# Compiler flag for disabling warning about array bounds
+set_compiler_property(PROPERTY warning_no_array_bounds)
 
 # Compiler flags to avoid recognizing built-in functions
 set_compiler_property(PROPERTY no_builtin)
@@ -149,3 +156,8 @@ set_compiler_property(PROPERTY specs)
 
 # Compiler flag for defining preinclude files.
 set_compiler_property(PROPERTY include_file)
+
+# Compiler flag for trustzone
+set_compiler_property(PROPERTY cmse)
+
+set_property(TARGET asm PROPERTY cmse)
diff --git a/cmake/compiler/gcc/compiler_flags.cmake b/cmake/compiler/gcc/compiler_flags.cmake
index 204df61d01a..48afd244ac7 100644
--- a/cmake/compiler/gcc/compiler_flags.cmake
+++ b/cmake/compiler/gcc/compiler_flags.cmake
@@ -21,6 +21,7 @@ endif()
 set_compiler_property(PROPERTY optimization_speed -O2)
 set_compiler_property(PROPERTY optimization_size  -Os)
 set_compiler_property(PROPERTY optimization_size_aggressive -Oz)
+set_compiler_property(PROPERTY optimization_fast -Ofast)
 
 if(CMAKE_C_COMPILER_VERSION GREATER_EQUAL "4.5.0")
   set_compiler_property(PROPERTY optimization_lto -flto=auto)
@@ -121,7 +122,7 @@ if (NOT CONFIG_NEWLIB_LIBC AND
   set_compiler_property(APPEND PROPERTY nostdinc_include ${NOSTDINC})
 endif()
 
-set_compiler_property(PROPERTY no_printf_return_value -fno-printf-return-value)
+check_set_compiler_property(PROPERTY no_printf_return_value -fno-printf-return-value)
 
 set_property(TARGET compiler-cpp PROPERTY nostdincxx "-nostdinc++")
 
@@ -231,10 +232,11 @@ set_property(TARGET compiler-cpp PROPERTY no_threadsafe_statics "-fno-threadsafe
 # Required ASM flags when using gcc
 set_property(TARGET asm PROPERTY required "-xassembler-with-cpp")
 
+# GCC compiler flags for imacros. The specific header must be appended by user.
+set_property(TARGET asm PROPERTY imacros "-imacros")
+
 # gcc flag for colourful diagnostic messages
-if (NOT COMPILER STREQUAL "xcc")
-set_compiler_property(PROPERTY diagnostic -fdiagnostics-color=always)
-endif()
+check_set_compiler_property(PROPERTY diagnostic -fdiagnostics-color=always)
 
 # Compiler flag for disabling pointer arithmetic warnings
 set_compiler_property(PROPERTY warning_no_pointer_arithmetic "-Wno-pointer-arith")
@@ -248,6 +250,7 @@ set_compiler_property(PROPERTY no_position_independent
 set_compiler_property(PROPERTY no_global_merge "")
 
 set_compiler_property(PROPERTY warning_shadow_variables -Wshadow)
+set_compiler_property(PROPERTY warning_no_array_bounds -Wno-array-bounds)
 
 set_compiler_property(PROPERTY no_builtin -fno-builtin)
 set_compiler_property(PROPERTY no_builtin_malloc -fno-builtin-malloc)
@@ -255,3 +258,7 @@ set_compiler_property(PROPERTY no_builtin_malloc -fno-builtin-malloc)
 set_compiler_property(PROPERTY specs -specs=)
 
 set_compiler_property(PROPERTY include_file -include)
+
+set_compiler_property(PROPERTY cmse -mcmse)
+
+set_property(TARGET asm PROPERTY cmse -mcmse)
diff --git a/cmake/compiler/gcc/target.cmake b/cmake/compiler/gcc/target.cmake
index 7e8ffc48173..2e90f00f659 100644
--- a/cmake/compiler/gcc/target.cmake
+++ b/cmake/compiler/gcc/target.cmake
@@ -5,7 +5,6 @@ set_ifndef(C++ g++)
 # Configures CMake for using GCC, this script is re-used by several
 # GCC-based toolchains
 
-find_package(Deprecated COMPONENTS SPARSE)
 find_program(CMAKE_C_COMPILER ${CROSS_COMPILE}${CC} PATHS ${TOOLCHAIN_HOME} NO_DEFAULT_PATH)
 
 if(${CMAKE_C_COMPILER} STREQUAL CMAKE_C_COMPILER-NOTFOUND)
@@ -39,10 +38,11 @@ endif()
 # Add check for GCC version >= 13.1
 execute_process(
     COMMAND ${CMAKE_C_COMPILER} -dumpfullversion
-    OUTPUT_VARIABLE temp_compiler_version
+    OUTPUT_VARIABLE GCC_COMPILER_VERSION
     )
 
-if("${temp_compiler_version}" VERSION_GREATER_EQUAL 13.1.0)
+if("${GCC_COMPILER_VERSION}" VERSION_LESS 4.3.0 OR
+    "${GCC_COMPILER_VERSION}" VERSION_GREATER_EQUAL 13.1.0)
     set(fix_header_file include/limits.h)
 else()
     set(fix_header_file include-fixed/limits.h)
diff --git a/cmake/compiler/gcc/target_arc.cmake b/cmake/compiler/gcc/target_arc.cmake
index d306fe1550f..7d580e81e8f 100644
--- a/cmake/compiler/gcc/target_arc.cmake
+++ b/cmake/compiler/gcc/target_arc.cmake
@@ -15,9 +15,12 @@ set(LLEXT_REMOVE_FLAGS
   -fno-pie
   -ffunction-sections
   -fdata-sections
-  -g.*
   -Os
 )
 
+set(LLEXT_APPEND_FLAGS
+  -mcpu=${GCC_ARC_TUNED_CPU} # Force compiler and linker match
+)
+
 list(APPEND TOOLCHAIN_C_FLAGS -mcpu=${GCC_ARC_TUNED_CPU})
 list(APPEND TOOLCHAIN_LD_FLAGS -mcpu=${GCC_ARC_TUNED_CPU})
diff --git a/cmake/compiler/gcc/target_arm.cmake b/cmake/compiler/gcc/target_arm.cmake
index 72b6cc03601..7d46a4e9572 100644
--- a/cmake/compiler/gcc/target_arm.cmake
+++ b/cmake/compiler/gcc/target_arm.cmake
@@ -54,7 +54,6 @@ set(LLEXT_REMOVE_FLAGS
   -fno-pie
   -ffunction-sections
   -fdata-sections
-  -g.*
   -Os
 )
 
@@ -67,8 +66,9 @@ set(LLEXT_APPEND_FLAGS
 list(APPEND LLEXT_EDK_REMOVE_FLAGS
     --sysroot=.*
     -fmacro-prefix-map=.*
-    )
+    -g.*
+)
 
 list(APPEND LLEXT_EDK_APPEND_FLAGS
     -nodefaultlibs
-    )
+)
diff --git a/cmake/compiler/gcc/target_arm64.cmake b/cmake/compiler/gcc/target_arm64.cmake
index 2674cac50cc..2bc16e61bc1 100644
--- a/cmake/compiler/gcc/target_arm64.cmake
+++ b/cmake/compiler/gcc/target_arm64.cmake
@@ -22,13 +22,13 @@ set(LLEXT_REMOVE_FLAGS
   -fno-pie
   -ffunction-sections
   -fdata-sections
-  -g.*
   -Os
 )
 
 list(APPEND LLEXT_EDK_REMOVE_FLAGS
   --sysroot=.*
   -fmacro-prefix-map=.*
+  -g.*
 )
 
 list(APPEND LLEXT_EDK_APPEND_FLAGS
diff --git a/cmake/compiler/gcc/target_riscv.cmake b/cmake/compiler/gcc/target_riscv.cmake
index a297a772886..81ed0cafedf 100644
--- a/cmake/compiler/gcc/target_riscv.cmake
+++ b/cmake/compiler/gcc/target_riscv.cmake
@@ -53,6 +53,18 @@ if(CONFIG_RISCV_ISA_EXT_ZIFENCEI)
     string(CONCAT riscv_march ${riscv_march} "_zifencei")
 endif()
 
+# Check whether we already imply Zaamo/Zlrsc by selecting the A extension; if not - check them
+# individually and enable them as needed
+if(NOT CONFIG_RISCV_ISA_EXT_A)
+  if(CONFIG_RISCV_ISA_EXT_ZAAMO)
+    string(CONCAT riscv_march ${riscv_march} "_zaamo")
+  endif()
+
+  if(CONFIG_RISCV_ISA_EXT_ZLRSC)
+    string(CONCAT riscv_march ${riscv_march} "_zlrsc")
+  endif()
+endif()
+
 if(CONFIG_RISCV_ISA_EXT_ZBA)
     string(CONCAT riscv_march ${riscv_march} "_zba")
 endif()
@@ -86,8 +98,12 @@ set(LLEXT_REMOVE_FLAGS
 # Flags to be added to llext code compilation
 # mno-relax is needed to stop gcc from generating R_RISCV_ALIGN relocations,
 # which are currently not supported
+# -msmall-data-limit=0 disables the "small data" sections such as .sbss and .sdata
+# only one NOBITS sections is supported at a time, so having .sbss can cause
+# llext's not to be loadable
 set(LLEXT_APPEND_FLAGS
   -mabi=${riscv_mabi}
   -march=${riscv_march}
   -mno-relax
-)
\ No newline at end of file
+  -msmall-data-limit=0
+)
diff --git a/cmake/compiler/gcc/target_xtensa.cmake b/cmake/compiler/gcc/target_xtensa.cmake
index 0b398023f67..abe0c7be703 100644
--- a/cmake/compiler/gcc/target_xtensa.cmake
+++ b/cmake/compiler/gcc/target_xtensa.cmake
@@ -5,7 +5,6 @@
 set(LLEXT_REMOVE_FLAGS
   -ffunction-sections
   -fdata-sections
-  -g.*
   -Os
   -mcpu=.*
 )
diff --git a/cmake/compiler/iar/compiler_flags.cmake b/cmake/compiler/iar/compiler_flags.cmake
new file mode 100644
index 00000000000..95e66e8cc4a
--- /dev/null
+++ b/cmake/compiler/iar/compiler_flags.cmake
@@ -0,0 +1,193 @@
+# Copyright (c) 2025 IAR Systems AB
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Compiler options for the IAR C/C++ Compiler for Arm
+
+#####################################################
+# This section covers flags related to optimization #
+#####################################################
+set_compiler_property(PROPERTY no_optimization -On)
+
+set_compiler_property(PROPERTY optimization_debug -Ol)
+
+set_compiler_property(PROPERTY optimization_speed -Ohs)
+
+set_compiler_property(PROPERTY optimization_size -Ohz)
+
+set_compiler_property(PROPERTY optimization_size_aggressive -Ohz)
+
+set_compiler_property(PROPERTY optimization_fast --no_size_constraints)
+
+#######################################################
+# This section covers flags related to warning levels #
+#######################################################
+
+# -DW=... settings
+#
+# W=1 - warnings that may be relevant and does not occur too often
+# W=2 - warnings that occur quite often but may still be relevant
+# W=3 - the more obscure warnings, can most likely be ignored
+
+set(IAR_SUPPRESSED_WARNINGS)
+
+# Set basic suppressed warning first
+
+# Pe223: function "xxx" declared implicitly
+# Pe054: too few arguments in invocation of macro
+# Pe1675: unrecognized GCC pragma
+# Pe111: statement is unreachable
+# Pe1143: arithmetic on pointer to void or function type
+# Pe068: integer conversion resulted in a change of sign
+list(APPEND IAR_SUPPRESSED_WARNINGS
+     --diag_suppress=Pe068,Pe1143,Pe111,Pe1675,Pe054,Pe223)
+
+# Since IAR does not turn on warnings we do this backwards
+# by not suppressing warnings on higher levels.
+if(NOT W MATCHES "3")
+  # Pe381: extra ";" ignored
+  list(APPEND IAR_SUPPRESSED_WARNINGS --diag_suppress=Pe381)
+endif()
+if(NOT W MATCHES "2" AND NOT W MATCHES "3")
+  # Pe1097: unknown attribute
+  # Pa082: undefined behavior: the order of volatile accesses is undefined
+  # Pa084: pointless integer comparison, the result is always false
+  # Pe185: dynamic initialization in unreachable code
+  # Pe167: argument of type "onoff_notify_fn" is incompatible with...
+  # Pe144: a value of type "void *" cannot be used to initialize...
+  # Pe177: function "xxx" was declared but never referenced
+  # Pe513: a value of type "void *" cannot be assigned to an
+  #        entity of type "int (*)(int)"
+  list(APPEND IAR_SUPPRESSED_WARNINGS
+       --diag_suppress=Pe513,Pe177,Pe144,Pe167,Pe185,Pa084,Pa082,Pe1097)
+endif()
+if(NOT W MATCHES "1" AND NOT W MATCHES "2" AND NOT W MATCHES "3")
+  # Pe188: enumerated type mixed with another type
+  # Pe128: loop is not reachable
+  # Pe550: variable "res" was set but never used
+  # Pe546: transfer of control bypasses initialization
+  # Pe186: pointless comparison of unsigned integer with zero
+  # Pe054: too few arguments in invocation of macro xxx
+  # Pe144: a value of type "void *" cannot be used to initialize an
+  #        entity of type [...] "void (*)(struct onoff_manager *, int)"
+  # Pe167: argument of type "void *" is incompatible with [...]
+  #        "void (*)(void *, void *, void *)"
+  list(APPEND IAR_SUPPRESSED_WARNINGS
+       --diag_suppress=Pe054,Pe186,Pe546,Pe550,Pe128,Pe188,Pe144,Pe167)
+endif()
+
+set_compiler_property(PROPERTY warning_base ${IAR_SUPPRESSED_WARNINGS})
+
+# Extended warning set supported by the compiler
+set_compiler_property(PROPERTY warning_extended)
+
+# Compiler property that will issue error if a declaration does not specify a type
+set_compiler_property(PROPERTY warning_error_implicit_int)
+
+# Compiler flags to use when compiling according to MISRA
+set_compiler_property(PROPERTY warning_error_misra_sane)
+
+set_property(TARGET compiler PROPERTY warnings_as_errors --warnings_are_errors)
+
+###########################################################################
+# This section covers flags related to C or C++ standards / standard libs #
+###########################################################################
+
+# Compiler flags for C standard. The specific standard must be appended by user.
+# For example, gcc specifies this as: set_compiler_property(PROPERTY cstd -std=)
+# TC-WG: the `cstd99` is used regardless of this flag being useful for iccarm
+# This flag will make it a symbol. Works for C,CXX,ASM
+# Since ICCARM does not use C standard flags, we just make them a defined symbol
+# instead
+set_compiler_property(PROPERTY cstd -D__IAR_CSTD_)
+
+# Compiler flags for disabling C standard include and instead specify include
+# dirs in nostdinc_include to use.
+set_compiler_property(PROPERTY nostdinc)
+set_compiler_property(PROPERTY nostdinc_include)
+
+# Compiler flags for disabling C++ standard include.
+set_compiler_property(TARGET compiler-cpp PROPERTY nostdincxx)
+
+# Required C++ flags when compiling C++ code
+set_property(TARGET compiler-cpp PROPERTY required --c++)
+
+# Compiler flags to use for specific C++ dialects
+set_property(TARGET compiler-cpp PROPERTY dialect_cpp98)
+set_property(TARGET compiler-cpp PROPERTY dialect_cpp11)
+set_property(TARGET compiler-cpp PROPERTY dialect_cpp14)
+set_property(TARGET compiler-cpp PROPERTY dialect_cpp17 --libc++)
+set_property(TARGET compiler-cpp PROPERTY dialect_cpp2a --libc++)
+set_property(TARGET compiler-cpp PROPERTY dialect_cpp20 --libc++)
+set_property(TARGET compiler-cpp PROPERTY dialect_cpp2b --libc++)
+
+# Flag for disabling strict aliasing rule in C and C++
+set_compiler_property(PROPERTY no_strict_aliasing)
+
+# Flag for disabling exceptions in C++
+set_property(TARGET compiler-cpp PROPERTY no_exceptions --no_exceptions)
+
+# Flag for disabling rtti in C++
+set_property(TARGET compiler-cpp PROPERTY no_rtti --no_rtti)
+
+###################################################
+# This section covers all remaining C / C++ flags #
+###################################################
+
+# Flags for coverage generation
+set_compiler_property(PROPERTY coverage)
+
+# Security canaries flags.
+set_compiler_property(PROPERTY security_canaries --stack_protection)
+set_compiler_property(PROPERTY security_canaries_strong --stack_protection)
+set_compiler_property(PROPERTY security_canaries_all --security_canaries_all_is_not_supported)
+set_compiler_property(PROPERTY security_canaries_explicit --security_canaries_explicit_is_not_supported)
+
+if(CONFIG_STACK_CANARIES_TLS)
+  check_set_compiler_property(APPEND PROPERTY security_canaries --stack_protector_guard=tls)
+  check_set_compiler_property(APPEND PROPERTY security_canaries_strong --stack_protector_guard=tls)
+  check_set_compiler_property(APPEND PROPERTY security_canaries_all --stack_protector_guard=tls)
+  check_set_compiler_property(APPEND PROPERTY security_canaries_explicit --stack_protector_guard=tls)
+endif()
+
+set_compiler_property(PROPERTY security_fortify)
+
+# Flag for a hosted (no-freestanding) application
+set_compiler_property(PROPERTY hosted)
+
+# gcc flag for a freestanding application
+set_compiler_property(PROPERTY freestanding)
+
+# Flag to include debugging symbol in compilation
+set_property(TARGET compiler PROPERTY debug --debug)
+set_property(TARGET compiler-cpp PROPERTY debug --debug)
+
+set_compiler_property(PROPERTY no_common)
+
+# Flags for imacros. The specific header must be appended by user.
+set_property(TARGET compiler PROPERTY imacros --preinclude)
+set_property(TARGET compiler-cpp PROPERTY imacros --preinclude)
+set_property(TARGET asm PROPERTY imacros -imacros)
+
+# Compiler flag for turning off thread-safe initialization of local statics
+set_property(TARGET compiler-cpp PROPERTY no_threadsafe_statics)
+
+# Required ASM flags when compiling
+set_property(TARGET asm PROPERTY required)
+
+# Compiler flag for disabling pointer arithmetic warnings
+set_compiler_property(PROPERTY warning_no_pointer_arithmetic)
+# Compiler flag for warning about shadow variables
+set_compiler_property(PROPERTY warning_shadow_variables)
+# Compiler flag for disabling warning about array bounds
+set_compiler_property(PROPERTY warning_no_array_bounds)
+
+# Compiler flags for disabling position independent code / executable
+set_compiler_property(PROPERTY no_position_independent)
+
+# Compiler flag for defining preinclude files.
+set_compiler_property(PROPERTY include_file --preinclude)
+
+set_compiler_property(PROPERTY cmse --cmse)
+
+set_property(TARGET asm PROPERTY cmse -mcmse)
diff --git a/cmake/compiler/iar/generic.cmake b/cmake/compiler/iar/generic.cmake
new file mode 100644
index 00000000000..5d46412770d
--- /dev/null
+++ b/cmake/compiler/iar/generic.cmake
@@ -0,0 +1,15 @@
+# Copyright (c) 2025 IAR Systems AB
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT CMAKE_DTS_PREPROCESSOR)
+  find_program(CMAKE_DTS_PREPROCESSOR arm-zephyr-eabi-gcc PATHS ${ZEPHYR_SDK_INSTALL_DIR}/arm-zephyr-eabi/bin NO_DEFAULT_PATH)
+endif()
+
+if(NOT CMAKE_DTS_PREPROCESSOR)
+  message(FATAL_ERROR "Zephyr was unable to find \`arm-zephyr-eabi-gcc\` for DTS preprocessing")
+endif()
+
+if(CMAKE_C_COMPILER STREQUAL CMAKE_C_COMPILER-NOTFOUND)
+  message(FATAL_ERROR "Zephyr was unable to find the IAR toolchain. Was the environment misconfigured?")
+endif()
diff --git a/cmake/compiler/iar/iccarm-cpu.cmake b/cmake/compiler/iar/iccarm-cpu.cmake
new file mode 100644
index 00000000000..f191bb7e314
--- /dev/null
+++ b/cmake/compiler/iar/iccarm-cpu.cmake
@@ -0,0 +1,91 @@
+# Copyright (c) 2025 IAR Systems AB
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Determines what argument to give to --cpu= based on the
+# KConfig'uration and sets this to ICCARM_CPU
+
+if("${ARCH}" STREQUAL "arm")
+  if(CONFIG_CPU_CORTEX_M0)
+    set(ICCARM_CPU Cortex-M0)
+  elseif(CONFIG_CPU_CORTEX_M0PLUS)
+    set(ICCARM_CPU Cortex-M0+)
+  elseif(CONFIG_CPU_CORTEX_M1)
+    set(ICCARM_CPU Cortex-M1)
+  elseif(CONFIG_CPU_CORTEX_M3)
+    set(ICCARM_CPU Cortex-M3)
+  elseif(CONFIG_CPU_CORTEX_M4)
+    set(ICCARM_CPU Cortex-M4)
+  elseif(CONFIG_CPU_CORTEX_M7)
+    set(ICCARM_CPU Cortex-M7)
+  elseif(CONFIG_CPU_CORTEX_M23)
+    set(ICCARM_CPU Cortex-M23)
+  elseif(CONFIG_CPU_CORTEX_M33)
+    if(CONFIG_ARMV8_M_DSP)
+      set(ICCARM_CPU Cortex-M33)
+    else()
+      set(ICCARM_CPU Cortex-M33.no_dsp)
+    endif()
+  elseif(CONFIG_CPU_CORTEX_M55)
+    if(CONFIG_ARMV8_1_M_MVEF)
+      set(ICCARM_CPU Cortex-M55)
+    elseif(CONFIG_ARMV8_1_M_MVEI)
+      set(ICCARM_CPU Cortex-M55.no_mve)
+    elseif(CONFIG_ARMV8_M_DSP)
+      set(ICCARM_CPU Cortex-M55.no_mve)
+    else()
+      set(ICCARM_CPU Cortex-M55.no_dsp)
+    endif()
+  elseif(CONFIG_CPU_CORTEX_R4)
+    if(CONFIG_FPU AND CONFIG_CPU_HAS_VFP)
+      set(ICCARM_CPU Cortex-R4F)
+    else()
+      set(ICCARM_CPU Cortex-R4)
+    endif()
+  elseif(CONFIG_CPU_CORTEX_R5)
+    set(ICCARM_CPU Cortex-R5)
+    if(CONFIG_FPU AND CONFIG_CPU_HAS_VFP)
+      if(NOT CONFIG_VFP_FEATURE_DOUBLE_PRECISION)
+        set(ICCARM_CPU ${ICCARM_CPU}+fp.sp)
+      endif()
+    else()
+      set(ICCARM_CPU ${ICCARM_CPU}+fp.dp)
+    endif()
+  elseif(CONFIG_CPU_CORTEX_R7)
+    set(ICCARM_CPU Cortex-R7)
+    if(CONFIG_FPU AND CONFIG_CPU_HAS_VFP)
+      if(NOT CONFIG_VFP_FEATURE_DOUBLE_PRECISION)
+        set(ICCARM_CPU ${ICCARM_CPU}+fp.sp)
+      endif()
+    else()
+      set(ICCARM_CPU ${ICCARM_CPU}+fp.dp)
+    endif()
+  elseif(CONFIG_CPU_CORTEX_R52)
+    set(ICCARM_CPU Cortex-R52)
+    if(CONFIG_FPU AND CONFIG_CPU_HAS_VFP)
+      if(NOT CONFIG_VFP_FEATURE_DOUBLE_PRECISION)
+        set(ICCARM_CPU ${ICCARM_CPU}+fp.sp)
+      endif()
+    endif()
+  elseif(CONFIG_CPU_CORTEX_A7)
+    set(ICCARM_CPU Cortex-A7)
+  elseif(CONFIG_CPU_CORTEX_A9)
+    set(ICCARM_CPU Cortex-A9)
+  else()
+    message(FATAL_ERROR "Expected CONFIG_CPU_CORTEX_x to be defined")
+  endif()
+elseif("${ARCH}" STREQUAL "arm64")
+  if(CONFIG_CPU_CORTEX_A53)
+    set(ICCARM_CPU Cortex-A53)
+  elseif(CONFIG_CPU_CORTEX_A55)
+    set(ICCARM_CPU Cortex-A55)
+  elseif(CONFIG_CPU_CORTEX_A76)
+    set(ICCARM_CPU cortex-a76)
+  elseif(CONFIG_CPU_CORTEX_A76_A55)
+    set(ICCARM_CPU cortex-a76)
+  elseif(CONFIG_CPU_CORTEX_A72)
+    set(ICCARM_CPU Cortex-A72)
+  elseif(CONFIG_CPU_CORTEX_R82)
+    set(ICCARM_CPU Cortex-R82)
+  endif()
+endif()
diff --git a/cmake/compiler/iar/iccarm-fpu.cmake b/cmake/compiler/iar/iccarm-fpu.cmake
new file mode 100644
index 00000000000..84b01279922
--- /dev/null
+++ b/cmake/compiler/iar/iccarm-fpu.cmake
@@ -0,0 +1,55 @@
+# Copyright (c) 2025 IAR Systems AB
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Determines what argument to give to --fpu= based on the
+# KConfiguration and sets this to ICCARM_FPU
+
+if(CONFIG_FPU)
+
+  # 32-bit
+  if("${ARCH}" STREQUAL "arm")
+    if(CONFIG_CPU_AARCH32_CORTEX_R)
+      if(CONFIG_CPU_CORTEX_R4 OR CONFIG_CPU_CORTEX_R5) # VFPv3
+        if(CONFIG_VFP_FEATURE_DOUBLE_PRECISION)
+          set(ICCARM_FPU VFPv3_D16)
+        elseif(CONFIG_VFP_FEATURE_SINGLE_PRECISION)
+          set(ICCARM_FPU VFPv3-SP)
+        endif()
+        if(CONFIG_VFP_FEATURE_HALF_PRECISION)
+          set(ICCARM_FPU ${ICCARM_FPU}_Fp16)
+        endif()
+      elseif(CONFIG_CPU_CORTEX_R52)
+        if(CONFIG_VFP_FEATURE_DOUBLE_PRECISION)
+          set(ICCARM_FPU VFPv5_D16)
+        elseif(CONFIG_VFP_FEATURE_SINGLE_PRECISION)
+          set(ICCARM_FPU VFPv5-SP)
+        endif()
+      endif()
+    elseif(CONFIG_CPU_CORTEX_M)
+      # Defines a mapping from ICCARM_CPU to FPU
+      if(CONFIG_CPU_HAS_FPU_DOUBLE_PRECISION)
+        set(PRECISION_TOKEN _D16)
+      else()
+        set(PRECISION_TOKEN _SP)
+      endif()
+
+      set(FPU_FOR_Cortex-M4           FPv4${PRECISION_TOKEN})
+      set(FPU_FOR_Cortex-M7           FPv5${PRECISION_TOKEN})
+      set(FPU_FOR_Cortex-M33          FPv5${PRECISION_TOKEN})
+      set(FPU_FOR_Cortex-M33.no_dsp   FPv5${PRECISION_TOKEN})
+      set(FPU_FOR_Cortex-M55          FPv5${PRECISION_TOKEN})
+      set(FPU_FOR_Cortex-M55.no_mve   FPv5${PRECISION_TOKEN})
+      set(FPU_FOR_Cortex-M55.no_dsp   FPv5${PRECISION_TOKEN})
+      set(FPU_FOR_Cortex-M85          FPv5${PRECISION_TOKEN})
+      set(FPU_FOR_Cortex-M85.no_mve   FPv5${PRECISION_TOKEN})
+      set(FPU_FOR_Cortex-M85.no_dsp   FPv5${PRECISION_TOKEN})
+
+      set(ICCARM_FPU ${FPU_FOR_${ICCARM_CPU}})
+    endif()
+  # 64-bit
+  else()
+    set(ICCARM_FPU none)
+  endif()
+
+endif() #CONFIG_FPU
diff --git a/cmake/compiler/iar/target.cmake b/cmake/compiler/iar/target.cmake
new file mode 100644
index 00000000000..432c1238b70
--- /dev/null
+++ b/cmake/compiler/iar/target.cmake
@@ -0,0 +1,150 @@
+# Copyright (c) 2025 IAR Systems AB
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Avoids running the linker during try_compile()
+set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
+set(NO_BUILD_TYPE_WARNING 1)
+set(CMAKE_NOT_USING_CONFIG_FLAGS 1)
+
+find_program(CMAKE_C_COMPILER
+  NAMES ${IAR_COMPILER}
+  PATHS ${TOOLCHAIN_HOME}
+  PATH_SUFFIXES bin
+  NO_DEFAULT_PATH
+  REQUIRED )
+
+message(STATUS "Found C Compiler ${CMAKE_C_COMPILER}")
+
+find_program(CMAKE_CXX_COMPILER
+  NAMES ${IAR_COMPILER}
+  PATHS ${TOOLCHAIN_HOME}
+  PATH_SUFFIXES bin
+  NO_DEFAULT_PATH
+  REQUIRED )
+
+find_program(CMAKE_AR
+  NAMES iarchive
+  PATHS ${TOOLCHAIN_HOME}
+  PATH_SUFFIXES bin
+  NO_DEFAULT_PATH
+  REQUIRED )
+
+set(CMAKE_ASM_COMPILER)
+if("${IAR_TOOLCHAIN_VARIANT}" STREQUAL "iccarm")
+  find_program(CMAKE_ASM_COMPILER
+    arm-zephyr-eabi-gcc
+    PATHS ${ZEPHYR_SDK_INSTALL_DIR}/arm-zephyr-eabi/bin
+    NO_DEFAULT_PATH )
+else()
+  find_program(CMAKE_ASM_COMPILER
+    riscv64-zephyr-elf-gcc
+    PATHS ${ZEPHYR_SDK_INSTALL_DIR}/riscv64-zephyr-elf/bin
+    NO_DEFAULT_PATH )
+endif()
+
+message(STATUS "Found assembler ${CMAKE_ASM_COMPILER}")
+
+set(ICC_BASE ${ZEPHYR_BASE}/cmake/compiler/iar)
+
+
+if("${IAR_TOOLCHAIN_VARIANT}" STREQUAL "iccarm")
+  # Used for settings correct cpu/fpu option for gnu assembler
+  include(${ZEPHYR_BASE}/cmake/gcc-m-cpu.cmake)
+  include(${ZEPHYR_BASE}/cmake/gcc-m-fpu.cmake)
+
+  # Map KConfig option to icc cpu/fpu
+  include(${ICC_BASE}/iccarm-cpu.cmake)
+  include(${ICC_BASE}/iccarm-fpu.cmake)
+endif()
+
+set(IAR_COMMON_FLAGS)
+# Minimal C compiler flags
+
+list(APPEND IAR_COMMON_FLAGS
+  "SHELL: --preinclude"
+  "${ZEPHYR_BASE}/include/zephyr/toolchain/iar/iar_missing_defs.h"
+  # Enable both IAR and GNU extensions
+  -e
+  --language gnu
+  --do_explicit_init_in_named_sections
+  --macro_positions_in_diagnostics
+  --no_wrap_diagnostics
+)
+
+if("${IAR_TOOLCHAIN_VARIANT}" STREQUAL "iccarm")
+  list(APPEND IAR_COMMON_FLAGS
+    --endian=little
+    --cpu=${ICCARM_CPU}
+    -DRTT_USE_ASM=0        # WA for VAAK-232
+    --diag_suppress=Ta184  # Using zero sized arrays except for as last
+                           # member of a struct is discouraged and
+                           # dereferencing elements in such an array has
+                           # undefined behavior
+  )
+endif()
+
+# Enable VLA if CONFIG_MISRA_SANE is not set and warnings are not enabled.
+if(NOT CONFIG_MISRA_SANE AND NOT DEFINED W)
+  list(APPEND IAR_COMMON_FLAGS --vla)
+endif()
+
+# Minimal ASM compiler flags
+if("${IAR_TOOLCHAIN_VARIANT}" STREQUAL "iccarm")
+  list(APPEND IAR_ASM_FLAGS
+    -mcpu=${GCC_M_CPU}
+    -mabi=aapcs
+    -DRTT_USE_ASM=0       #WA for VAAK-232
+    )
+endif()
+
+# IAR needs Dwarf 4 output
+list(APPEND IAR_ASM_FLAGS -gdwarf-4)
+
+if(DEFINED CONFIG_ARM_SECURE_FIRMWARE)
+  list(APPEND IAR_COMMON_FLAGS --cmse)
+  list(APPEND IAR_ASM_FLAGS -mcmse)
+endif()
+
+# 64-bit
+if("${IAR_TOOLCHAIN_VARIANT}" STREQUAL "iccarm")
+  if(CONFIG_ARM64)
+    list(APPEND IAR_COMMON_FLAGS --abi=lp64)
+    list(APPEND TOOLCHAIN_LD_FLAGS --abi=lp64)
+  # 32-bit
+  else()
+    list(APPEND IAR_COMMON_FLAGS --aeabi)
+    if(CONFIG_COMPILER_ISA_THUMB2)
+      list(APPEND IAR_COMMON_FLAGS --thumb)
+      list(APPEND IAR_ASM_FLAGS -mthumb)
+    endif()
+
+    if(CONFIG_FPU)
+      list(APPEND IAR_COMMON_FLAGS --fpu=${ICCARM_FPU})
+      list(APPEND IAR_ASM_FLAGS -mfpu=${GCC_M_FPU})
+    endif()
+  endif()
+
+  if(CONFIG_IAR_LIBC)
+    # Zephyr requires AEABI portability to ensure correct functioning of the C
+    # library, for example error numbers, errno.h.
+    list(APPEND IAR_COMMON_FLAGS -D__AEABI_PORTABILITY_LEVEL=1)
+  endif()
+endif()
+
+if(CONFIG_IAR_LIBC)
+  message(STATUS "IAR C library used")
+  # Zephyr uses the type FILE for normal LIBC while IAR
+  # only has it for full LIBC support, so always choose
+  # full libc when using IAR C libraries.
+  list(APPEND IAR_COMMON_FLAGS --dlib_config full)
+endif()
+
+foreach(F ${IAR_COMMON_FLAGS})
+  list(APPEND TOOLCHAIN_C_FLAGS $<$<COMPILE_LANGUAGE:C>:${F}>)
+  list(APPEND TOOLCHAIN_C_FLAGS $<$<COMPILE_LANGUAGE:CXX>:${F}>)
+endforeach()
+
+foreach(F ${IAR_ASM_FLAGS})
+  list(APPEND TOOLCHAIN_C_FLAGS $<$<COMPILE_LANGUAGE:ASM>:${F}>)
+endforeach()
diff --git a/cmake/compiler/xt-clang/compiler_flags.cmake b/cmake/compiler/xt-clang/compiler_flags.cmake
index 593e3842843..c70832ebc0f 100644
--- a/cmake/compiler/xt-clang/compiler_flags.cmake
+++ b/cmake/compiler/xt-clang/compiler_flags.cmake
@@ -34,3 +34,12 @@ set_compiler_property(PROPERTY no_position_independent "")
 
 # Remove after testing that -Wshadow works
 set_compiler_property(PROPERTY warning_shadow_variables)
+
+# xt-clang is usually based on older version of clang, and
+# Zephyr main targets more recent versions. Because of this,
+# some newer compiler flags may cause warnings where twister
+# would mark as test being failed. To workaround that,
+# add -Wno-unknown-warning-option to suppress those warnings.
+check_set_compiler_property(APPEND PROPERTY warning_extended
+                            -Wno-unknown-warning-option
+)
diff --git a/cmake/compiler/xt-clang/target.cmake b/cmake/compiler/xt-clang/target.cmake
index 978bc7c7860..73cf348a1fd 100644
--- a/cmake/compiler/xt-clang/target.cmake
+++ b/cmake/compiler/xt-clang/target.cmake
@@ -7,7 +7,6 @@ include(${ZEPHYR_BASE}/cmake/compiler/xcc/target.cmake)
 set(LLEXT_REMOVE_FLAGS
   -ffunction-sections
   -fdata-sections
-  -g.*
   -Os
   -mcpu=.*
 )
diff --git a/cmake/emu/armfvp.cmake b/cmake/emu/armfvp.cmake
index 70fa5dc0aa3..354cc43cbcf 100644
--- a/cmake/emu/armfvp.cmake
+++ b/cmake/emu/armfvp.cmake
@@ -53,9 +53,12 @@ elseif(CONFIG_ARMV8_A_NS)
     --data cluster0.cpu0="${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_BIN_NAME}"@0x88000000
     )
 else()
-  set(ARMFVP_FLAGS ${ARMFVP_FLAGS}
-    -a ${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
+  string(FIND "${ARMFVP_FLAGS}" " -a " ARMFVP_APPARG_POS)
+  if(${ARMFVP_APPARG_POS} EQUAL -1)
+    set(ARMFVP_FLAGS ${ARMFVP_FLAGS}
+      -a ${APPLICATION_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
     )
+  endif()
 endif()
 
 if(CONFIG_ETH_SMSC91X)
diff --git a/cmake/emu/simics.cmake b/cmake/emu/simics.cmake
index f20c09f052a..1c5cc3f96ea 100644
--- a/cmake/emu/simics.cmake
+++ b/cmake/emu/simics.cmake
@@ -11,7 +11,7 @@ find_program(
   )
 
 if(SIMICS STREQUAL SIMICS-NOTFOUND)
-  message(WARNING "Simics simulator environment is not found at SIMICS_PROJECT:'${SIMICS_PROJECT}'")
+  message(WARNING "Simics simulator environment is not found at SIMICS_PROJECT:'$ENV{SIMICS_PROJECT}'")
 else()
   message(STATUS "Found Simics: ${SIMICS}")
 
diff --git a/cmake/gcc-m-cpu.cmake b/cmake/gcc-m-cpu.cmake
index 6f00283b6b8..75b13fa4238 100644
--- a/cmake/gcc-m-cpu.cmake
+++ b/cmake/gcc-m-cpu.cmake
@@ -84,6 +84,8 @@ if("${ARCH}" STREQUAL "arm")
         set(GCC_M_CPU ${GCC_M_CPU}+nofp.dp)
       endif()
     endif()
+  elseif(CONFIG_CPU_CORTEX_A7)
+    set(GCC_M_CPU cortex-a7)
   elseif(CONFIG_CPU_CORTEX_A9)
     set(GCC_M_CPU cortex-a9)
   else()
diff --git a/cmake/gcc-m-fpu.cmake b/cmake/gcc-m-fpu.cmake
index d1ce9655b46..aafe5b75c86 100644
--- a/cmake/gcc-m-fpu.cmake
+++ b/cmake/gcc-m-fpu.cmake
@@ -45,6 +45,10 @@ if("${ARCH}" STREQUAL "arm")
     set(FPU_FOR_cortex-m85+nodsp    auto)
 
     set(GCC_M_FPU ${FPU_FOR_${GCC_M_CPU}})
+  elseif(CONFIG_CPU_AARCH32_CORTEX_A)
+    if(CONFIG_CPU_CORTEX_A7)
+      set(GCC_M_FPU vfpv4-d16)
+    endif()
   endif()
 endif()
 
diff --git a/cmake/linker/armlink/target.cmake b/cmake/linker/armlink/target.cmake
index be2bb8e8977..7a973865c4a 100644
--- a/cmake/linker/armlink/target.cmake
+++ b/cmake/linker/armlink/target.cmake
@@ -29,22 +29,13 @@ macro(configure_linker_script linker_script_gen linker_pass_define)
     set(STEERING_C_ARG "-DSTEERING_C=${STEERING_C}")
   endif()
 
-  file(GENERATE OUTPUT ${cmake_linker_script_settings} CONTENT
-       "set(FORMAT \"$<TARGET_PROPERTY:linker,FORMAT>\" CACHE INTERNAL \"\")\n
-        set(ENTRY \"$<TARGET_PROPERTY:linker,ENTRY>\" CACHE INTERNAL \"\")\n
-        set(MEMORY_REGIONS \"$<TARGET_PROPERTY:linker,MEMORY_REGIONS>\" CACHE INTERNAL \"\")\n
-        set(GROUPS \"$<TARGET_PROPERTY:linker,GROUPS>\" CACHE INTERNAL \"\")\n
-        set(SECTIONS \"$<TARGET_PROPERTY:linker,SECTIONS>\" CACHE INTERNAL \"\")\n
-        set(SECTION_SETTINGS \"$<TARGET_PROPERTY:linker,SECTION_SETTINGS>\" CACHE INTERNAL \"\")\n
-        set(SYMBOLS \"$<TARGET_PROPERTY:linker,SYMBOLS>\" CACHE INTERNAL \"\")\n
-       "
-    )
+  zephyr_linker_generate_linker_settings_file(${cmake_linker_script_settings})
+
   add_custom_command(
     OUTPUT ${linker_script_gen}
            ${STEERING_FILE}
            ${STEERING_C}
     COMMAND ${CMAKE_COMMAND}
-      -C ${DEVICE_API_LINKER_SECTIONS_CMAKE}
       -C ${cmake_linker_script_settings}
       -DPASS="${linker_pass_define}"
       ${STEERING_FILE_ARG}
@@ -52,6 +43,7 @@ macro(configure_linker_script linker_script_gen linker_pass_define)
       -DOUT_FILE=${CMAKE_CURRENT_BINARY_DIR}/${linker_script_gen}
       -P ${ZEPHYR_BASE}/cmake/linker/armlink/scatter_script.cmake
     DEPENDS ${DEVICE_API_LD_TARGET}
+            ${cmake_linker_script_settings}
   )
 
   if("LINKER_ZEPHYR_FINAL" IN_LIST linker_pass_define_list)
diff --git a/cmake/linker/iar/config_file_script.cmake b/cmake/linker/iar/config_file_script.cmake
new file mode 100644
index 00000000000..9d430d5b219
--- /dev/null
+++ b/cmake/linker/iar/config_file_script.cmake
@@ -0,0 +1,919 @@
+# Copyright (c) 2025 IAR Systems AB
+#
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.17)
+
+set(SORT_TYPE_NAME Lexical)
+
+set_property(GLOBAL PROPERTY ILINK_REGION_SYMBOL_ICF)
+
+# This function post process the region for easier use.
+#
+# Tasks:
+# - Symbol translation using a steering file is configured.
+function(process_region)
+  cmake_parse_arguments(REGION "" "OBJECT" "" ${ARGN})
+
+  process_region_common(${ARGN})
+
+  get_property(empty GLOBAL PROPERTY ${REGION_OBJECT}_EMPTY)
+  if(NOT empty)
+    # For scatter files we move any system symbols into first non-empty load section.
+    get_parent(OBJECT ${REGION_OBJECT} PARENT parent TYPE SYSTEM)
+    get_property(symbols GLOBAL PROPERTY ${parent}_SYMBOLS)
+    set_property(GLOBAL APPEND PROPERTY ${REGION_OBJECT}_SYMBOLS ${symbols})
+    set_property(GLOBAL PROPERTY ${parent}_SYMBOLS)
+  endif()
+
+  get_property(sections GLOBAL PROPERTY ${REGION_OBJECT}_SECTION_LIST_ORDERED)
+  foreach(section ${sections})
+
+    get_property(name       GLOBAL PROPERTY ${section}_NAME)
+    get_property(name_clean GLOBAL PROPERTY ${section}_NAME_CLEAN)
+    get_property(noinput    GLOBAL PROPERTY ${section}_NOINPUT)
+    get_property(type       GLOBAL PROPERTY ${section}_TYPE)
+    get_property(nosymbols  GLOBAL PROPERTY ${section}_NOSYMBOLS)
+
+    if(NOT nosymbols)
+      if(${name} STREQUAL .ramfunc)
+        create_symbol(OBJECT ${REGION_OBJECT} SYMBOL __${name_clean}_load_start
+          EXPR "@ADDR(.ramfunc_init)@"
+          )
+      else()
+        create_symbol(OBJECT ${REGION_OBJECT} SYMBOL __${name_clean}_load_start
+          EXPR "@LOADADDR(${name_clean})@"
+          )
+      endif()
+    endif()
+
+    get_property(indicies GLOBAL PROPERTY ${section}_SETTINGS_INDICIES)
+    list(LENGTH indicies length)
+    foreach(idx ${indicies})
+      set(steering_postfixes Base Limit)
+      get_property(symbols GLOBAL PROPERTY ${section}_SETTING_${idx}_SYMBOLS)
+      get_property(sort    GLOBAL PROPERTY ${section}_SETTING_${idx}_SORT)
+      get_property(offset  GLOBAL PROPERTY ${section}_SETTING_${idx}_OFFSET)
+      if(DEFINED offset AND NOT offset EQUAL 0 )
+        # Same behavior as in section_to_string
+      elseif(DEFINED offset AND offset STREQUAL 0 )
+        # Same behavior as in section_to_string
+      elseif(sort)
+        # Treated by labels in the icf or image symbols.
+      elseif(DEFINED symbols AND ${length} EQUAL 1 AND noinput)
+      endif()
+    endforeach()
+
+    # Symbols translation here.
+
+    get_property(symbol_val GLOBAL PROPERTY SYMBOL_TABLE___${name_clean}_end)
+
+    if("${symbol_val}" STREQUAL "${name_clean}")
+      create_symbol(OBJECT ${REGION_OBJECT} SYMBOL __${name_clean}_size
+        EXPR "@SIZE(${name_clean})@"
+        )
+    else()
+      # These seem to be thing that can't be transformed to $$Length
+      set_property(GLOBAL APPEND PROPERTY ILINK_REGION_SYMBOL_ICF
+        "define image symbol __${name_clean}_size = (__${symbol_val} - ADDR(${name_clean}))")
+    endif()
+    set(ZI)
+
+    if(${name_clean} STREQUAL last_ram_section)
+      # A trick to add the symbol for the nxp devices
+      # _flash_used = LOADADDR(.last_section) + SIZEOF(.last_section) - __rom_region_start;
+      create_symbol(OBJECT ${REGION_OBJECT} SYMBOL _flash_used
+        EXPR "(@LOADADDR(last_section)@ + @SIZE(last_section)@ - @__rom_region_start@)"
+        )
+    endif()
+
+    if(${name_clean} STREQUAL rom_start)
+      # The below two symbols is meant to make aliases to the _vector_table symbol.
+      list(GET symbols 0 symbol_start)
+      create_symbol(OBJECT ${REGION_OBJECT} SYMBOL __Vectors
+        EXPR "@ADDR(${symbol_start})@"
+        )
+      create_symbol(OBJECT ${REGION_OBJECT} SYMBOL __vector_table
+        EXPR "@ADDR(${symbol_start})@"
+        )
+    endif()
+
+  endforeach()
+
+  get_property(groups GLOBAL PROPERTY ${REGION_OBJECT}_GROUP_LIST_ORDERED)
+  foreach(group ${groups})
+    get_property(name GLOBAL PROPERTY ${group}_NAME)
+    string(TOLOWER ${name} name)
+
+    get_property(group_type  GLOBAL PROPERTY ${group}_OBJ_TYPE)
+    get_property(parent      GLOBAL PROPERTY ${group}_PARENT)
+    get_property(parent_type GLOBAL PROPERTY ${parent}_OBJ_TYPE)
+    # Need to find the init manually group or parent
+    if(${parent_type} STREQUAL GROUP)
+      get_property(vma GLOBAL PROPERTY ${parent}_VMA)
+      get_property(lma GLOBAL PROPERTY ${parent}_LMA)
+    else()
+      get_property(vma GLOBAL PROPERTY ${group}_VMA)
+      get_property(lma GLOBAL PROPERTY ${group}_LMA)
+    endif()
+
+    get_objects(LIST sections OBJECT ${group} TYPE SECTION)
+    list(GET sections 0 section)
+    get_property(first_section_name GLOBAL PROPERTY ${section}_NAME_CLEAN)
+    list(POP_BACK sections section)
+    get_property(last_section_name GLOBAL PROPERTY ${section}_NAME_CLEAN)
+
+    if(DEFINED vma AND DEFINED lma)
+      # Something to init
+      create_symbol(OBJECT ${REGION_OBJECT} SYMBOL __${name}_load_start
+        EXPR "@ADDR(${first_section_name}_init)@"
+        )
+    else()
+      create_symbol(OBJECT ${REGION_OBJECT} SYMBOL __${name}_load_start
+        EXPR "@LOADADDR(${first_section_name})@"
+        )
+    endif()
+
+    create_symbol(OBJECT ${REGION_OBJECT} SYMBOL __${name}_start
+      EXPR "@ADDR(${first_section_name})@"
+      )
+    create_symbol(OBJECT ${REGION_OBJECT} SYMBOL __${name}_end
+      EXPR "@END(${last_section_name})@"
+      )
+    create_symbol(OBJECT ${REGION_OBJECT} SYMBOL __${name}_size
+      EXPR "(@(__${name}_end)@ - @(__${name}_start)@)"
+      )
+
+  endforeach()
+
+  get_property(symbols GLOBAL PROPERTY ${REGION_OBJECT}_SYMBOLS)
+  foreach(symbol ${symbols})
+    get_property(name GLOBAL PROPERTY ${symbol}_NAME)
+    get_property(expr GLOBAL PROPERTY ${symbol}_EXPR)
+    if(NOT DEFINED expr)
+      create_symbol(OBJECT ${REGION_OBJECT} SYMBOL __${name}_size
+        EXPR "@(ADDR(${name})@"
+        )
+    endif()
+  endforeach()
+
+  # This is only a trick to get the memories
+  set(groups)
+  get_objects(LIST groups OBJECT ${REGION_OBJECT} TYPE GROUP)
+  foreach(group ${groups})
+    get_property(group_type  GLOBAL PROPERTY ${group}_OBJ_TYPE)
+    get_property(parent      GLOBAL PROPERTY ${group}_PARENT)
+    get_property(parent_type GLOBAL PROPERTY ${parent}_OBJ_TYPE)
+
+    if(${group_type} STREQUAL GROUP)
+      get_property(group_name GLOBAL PROPERTY ${group}_NAME)
+      get_property(group_lma  GLOBAL PROPERTY ${group}_LMA)
+      if(${group_name} STREQUAL ROM_REGION)
+        set_property(GLOBAL PROPERTY ILINK_ROM_REGION_NAME ${group_lma})
+      endif()
+    endif()
+
+    if(${parent_type} STREQUAL GROUP)
+      get_property(vma GLOBAL PROPERTY ${parent}_VMA)
+      get_property(lma GLOBAL PROPERTY ${parent}_LMA)
+
+      set_property(GLOBAL PROPERTY ${group}_VMA ${vma})
+      set_property(GLOBAL PROPERTY ${group}_LMA ${lma})
+    endif()
+  endforeach()
+
+endfunction()
+
+#
+# String functions - start
+#
+
+function(system_to_string)
+  cmake_parse_arguments(STRING "" "OBJECT;STRING" "" ${ARGN})
+
+  get_property(name    GLOBAL PROPERTY ${STRING_OBJECT}_NAME)
+  get_property(regions GLOBAL PROPERTY ${STRING_OBJECT}_REGIONS)
+  get_property(format  GLOBAL PROPERTY ${STRING_OBJECT}_FORMAT)
+
+  # Ilink specials
+  # set(${STRING_STRING} "build for rom;\n")
+  set(${STRING_STRING} "build for ram;\n")
+  if("${format}" MATCHES "aarch64")
+    set(${STRING_STRING} "${${STRING_STRING}}define memory mem with size = 16E;\n")
+  else()
+    set(${STRING_STRING} "${${STRING_STRING}}define memory mem with size = 4G;\n")
+  endif()
+
+  foreach(region ${regions})
+    get_property(name    GLOBAL PROPERTY ${region}_NAME)
+    get_property(address GLOBAL PROPERTY ${region}_ADDRESS)
+    get_property(flags   GLOBAL PROPERTY ${region}_FLAGS)
+    get_property(size    GLOBAL PROPERTY ${region}_SIZE)
+
+    if(DEFINED flags)
+      if(${flags} STREQUAL rx)
+        set(flags " rom")
+      elseif(${flags} STREQUAL ro)
+        set(flags " rom")
+      elseif(${flags} STREQUAL wx)
+        set(flags " ram")
+      elseif(${flags} STREQUAL rw)
+        set(flags " ram")
+      endif()
+    endif()
+
+    if(${name} STREQUAL IDT_LIST)
+      # Need to use a untyped region for IDT_LIST
+      set(flags "")
+    endif()
+
+    if(DEFINED address)
+      set(start "${address}")
+    endif()
+
+    if(DEFINED size)
+      set(size "${size}")
+    endif()
+    # define rom region FLASH    = mem:[from 0x0 size 0x40000];
+    set(memory_region "define${flags} region ${name} = mem:[from ${start} size ${size}];")
+
+    set(${STRING_STRING} "${${STRING_STRING}}${memory_region}\n")
+    set(flags)
+  endforeach()
+
+  set(${STRING_STRING} "${${STRING_STRING}}\n\n")
+  set_property(GLOBAL PROPERTY ILINK_SYMBOL_ICF)
+
+  set(${STRING_STRING} "${${STRING_STRING}}\n")
+  foreach(region ${regions})
+    get_property(empty GLOBAL PROPERTY ${region}_EMPTY)
+    if(NOT empty)
+      get_property(name    GLOBAL PROPERTY ${region}_NAME)
+      set(ILINK_CURRENT_NAME ${name})
+      to_string(OBJECT ${region} STRING ${STRING_STRING})
+      set(ILINK_CURRENT_NAME)
+    endif()
+  endforeach()
+  set(${STRING_STRING} "${${STRING_STRING}}\n")
+
+  get_property(symbols_icf GLOBAL PROPERTY ILINK_SYMBOL_ICF)
+  foreach(image_symbol ${symbols_icf})
+    set(${STRING_STRING} "${${STRING_STRING}}define image symbol ${image_symbol};\n")
+  endforeach()
+
+  get_property(symbols_icf GLOBAL PROPERTY ILINK_REGION_SYMBOL_ICF)
+  set(${STRING_STRING} "${${STRING_STRING}}\n")
+  foreach(image_symbol ${symbols_icf})
+    set(${STRING_STRING} "${${STRING_STRING}}${image_symbol};\n")
+  endforeach()
+
+  if(IAR_LIBC)
+    set(${STRING_STRING} "${${STRING_STRING}}if (K_HEAP_MEM_POOL_SIZE>0)\n{\n")
+    set(${STRING_STRING} "${${STRING_STRING}}  define block HEAP with alignment=8 { symbol kheap__system_heap };\n")
+    set(${STRING_STRING} "${${STRING_STRING}}}\nelse\n{\n")
+    set(${STRING_STRING} "${${STRING_STRING}}  define block HEAP with alignment=8, expanding size { };\n")
+    set(${STRING_STRING} "${${STRING_STRING}}}\n")
+    set(${STRING_STRING} "${${STRING_STRING}}\"DLib heap\": place in RAM { block HEAP };\n")
+#    set(${STRING_STRING} "${${STRING_STRING}}define exported symbol HEAP$$Base=kheap__system_heap;\n")
+#    set(${STRING_STRING} "${${STRING_STRING}}define exported symbol HEAP$$Limit=END(kheap__system_heap);\n")
+  endif()
+
+  set(${STRING_STRING} ${${STRING_STRING}} PARENT_SCOPE)
+endfunction()
+
+function(group_to_string)
+  cmake_parse_arguments(STRING "" "OBJECT;STRING" "" ${ARGN})
+
+  get_property(type GLOBAL PROPERTY ${STRING_OBJECT}_OBJ_TYPE)
+  if(${type} STREQUAL REGION)
+    get_property(empty GLOBAL PROPERTY ${STRING_OBJECT}_EMPTY)
+    if(empty)
+      return()
+    endif()
+  endif()
+
+  #_SECTIONS_FIXED need a place at address statement:
+  get_property(sections GLOBAL PROPERTY ${STRING_OBJECT}_SECTIONS_FIXED)
+  foreach(section ${sections})
+    to_string(OBJECT ${section} STRING ${STRING_STRING})
+    get_property(name       GLOBAL PROPERTY ${section}_NAME)
+    get_property(name_clean GLOBAL PROPERTY ${section}_NAME_CLEAN)
+    get_property(section_address GLOBAL PROPERTY ${section}_ADDRESS)
+    set(${STRING_STRING} "${${STRING_STRING}}\"${name}\": place at address mem:${section_address} { block ${name_clean} };\n")
+  endforeach()
+
+  get_property(groups GLOBAL PROPERTY ${STRING_OBJECT}_GROUPS)
+  foreach(group ${groups})
+    to_string(OBJECT ${group} STRING ${STRING_STRING})
+  endforeach()
+
+  get_property(sections GLOBAL PROPERTY ${STRING_OBJECT}_SECTIONS)
+  foreach(section ${sections})
+    to_string(OBJECT ${section} STRING ${STRING_STRING})
+
+    get_property(name     GLOBAL PROPERTY ${section}_NAME)
+
+    get_property(name_clean GLOBAL PROPERTY ${section}_NAME_CLEAN)
+
+    get_property(parent   GLOBAL PROPERTY ${section}_PARENT)
+    get_property(noinit   GLOBAL PROPERTY ${section}_NOINIT)
+    # This is only a trick to get the memories
+    get_property(parent_type GLOBAL PROPERTY ${parent}_OBJ_TYPE)
+    if(${parent_type} STREQUAL GROUP)
+      get_property(vma GLOBAL PROPERTY ${parent}_VMA)
+      get_property(lma GLOBAL PROPERTY ${parent}_LMA)
+    endif()
+
+    if(DEFINED vma)
+      set(ILINK_CURRENT_NAME ${vma})
+    elseif(DEFINED lma)
+      set(ILINK_CURRENT_NAME ${lma})
+    else()
+      # message(FATAL_ERROR "Need either vma or lma")
+    endif()
+
+    set(${STRING_STRING} "${${STRING_STRING}}\"${name}\": place in ${ILINK_CURRENT_NAME} { block ${name_clean} };\n")
+    if(DEFINED vma AND DEFINED lma AND NOT ${noinit})
+      set(${STRING_STRING} "${${STRING_STRING}}\"${name}_init\": place in ${lma} { block ${name_clean}_init };\n")
+    endif()
+
+  endforeach()
+
+  get_parent(OBJECT ${STRING_OBJECT} PARENT parent TYPE SYSTEM)
+  get_property(regions GLOBAL PROPERTY ${parent}_REGIONS)
+  list(REMOVE_ITEM regions ${STRING_OBJECT})
+
+  foreach(region ${regions})
+    get_property(vma GLOBAL PROPERTY ${region}_NAME)
+    get_property(sections GLOBAL PROPERTY ${STRING_OBJECT}_${vma}_SECTIONS_FIXED)
+
+    foreach(section ${sections})
+      to_string(OBJECT ${section} STRING ${STRING_STRING})
+    endforeach()
+
+    get_property(groups GLOBAL PROPERTY ${STRING_OBJECT}_${vma}_GROUPS)
+    foreach(group ${groups})
+      to_string(OBJECT ${group} STRING ${STRING_STRING})
+    endforeach()
+
+    get_property(sections GLOBAL PROPERTY ${STRING_OBJECT}_${vma}_SECTIONS)
+    foreach(section ${sections})
+      to_string(OBJECT ${section} STRING ${STRING_STRING})
+      get_property(name     GLOBAL PROPERTY ${section}_NAME)
+      string(REGEX REPLACE "^[\.]" "" name_clean "${name}")
+      string(REPLACE "." "_" name_clean "${name_clean}")
+      set(${STRING_STRING} "${${STRING_STRING}}\"${name}\": place in ${vma} { block ${name_clean} };\n")
+
+      # Insert 'do not initialize' here
+      get_property(current_sections GLOBAL PROPERTY ILINK_CURRENT_SECTIONS)
+      if(${name} STREQUAL .bss)
+        if(DEFINED current_sections)
+          set(${STRING_STRING} "${${STRING_STRING}}do not initialize\n")
+          set(${STRING_STRING} "${${STRING_STRING}}{\n")
+          foreach(section ${current_sections})
+            set(${STRING_STRING} "${${STRING_STRING}}  ${section},\n")
+          endforeach()
+          set(${STRING_STRING} "${${STRING_STRING}}};\n")
+          set(current_sections)
+          set_property(GLOBAL PROPERTY ILINK_CURRENT_SECTIONS)
+        endif()
+      endif()
+
+      if(${name_clean} STREQUAL last_ram_section)
+        get_property(group_name_lma GLOBAL PROPERTY ILINK_ROM_REGION_NAME)
+        set(${STRING_STRING} "${${STRING_STRING}}\n")
+        if(${CONFIG_LINKER_LAST_SECTION_ID})
+          set(${STRING_STRING} "${${STRING_STRING}}define section last_section_id { udata32 ${CONFIG_LINKER_LAST_SECTION_ID_PATTERN}; };\n")
+          set(${STRING_STRING} "${${STRING_STRING}}define block last_section with fixed order { section last_section_id };\n")
+        else()
+          set(${STRING_STRING} "${${STRING_STRING}}define block last_section with fixed order { };\n")
+        endif()
+        # Not really the right place, we want the last used flash bytes not end of the world!
+        # set(${STRING_STRING} "${${STRING_STRING}}\".last_section\": place at end of ${group_name_lma} { block last_section };\n")
+        set(${STRING_STRING} "${${STRING_STRING}}\".last_section\": place in ${group_name_lma} { block last_section };\n")
+        set(${STRING_STRING} "${${STRING_STRING}}keep { block last_section };\n")
+      endif()
+
+    endforeach()
+  endforeach()
+
+  get_property(symbols GLOBAL PROPERTY ${STRING_OBJECT}_SYMBOLS)
+  set(${STRING_STRING} "${${STRING_STRING}}\n")
+  foreach(symbol ${symbols})
+    to_string(OBJECT ${symbol} STRING ${STRING_STRING})
+  endforeach()
+
+  set(${STRING_STRING} ${${STRING_STRING}} PARENT_SCOPE)
+endfunction()
+
+
+function(section_to_string)
+  cmake_parse_arguments(STRING "" "SECTION;STRING" "" ${ARGN})
+
+  get_property(name     GLOBAL PROPERTY ${STRING_SECTION}_NAME)
+  get_property(address  GLOBAL PROPERTY ${STRING_SECTION}_ADDRESS)
+  get_property(type     GLOBAL PROPERTY ${STRING_SECTION}_TYPE)
+  get_property(align    GLOBAL PROPERTY ${STRING_SECTION}_ALIGN)
+  get_property(subalign GLOBAL PROPERTY ${STRING_SECTION}_SUBALIGN)
+  get_property(endalign GLOBAL PROPERTY ${STRING_SECTION}_ENDALIGN)
+  get_property(vma      GLOBAL PROPERTY ${STRING_SECTION}_VMA)
+  get_property(lma      GLOBAL PROPERTY ${STRING_SECTION}_LMA)
+  get_property(noinput  GLOBAL PROPERTY ${STRING_SECTION}_NOINPUT)
+  get_property(noinit   GLOBAL PROPERTY ${STRING_SECTION}_NOINIT)
+
+  get_property(nosymbols  GLOBAL PROPERTY ${STRING_SECTION}_NOSYMBOLS)
+  get_property(start_syms GLOBAL PROPERTY ${STRING_SECTION}_START_SYMBOLS)
+  get_property(end_syms   GLOBAL PROPERTY ${STRING_SECTION}_END_SYMBOLS)
+
+  get_property(parent   GLOBAL PROPERTY ${STRING_SECTION}_PARENT)
+
+  get_property(parent_type GLOBAL PROPERTY ${parent}_OBJ_TYPE)
+  if(${parent_type} STREQUAL GROUP)
+    get_property(group_parent_vma GLOBAL PROPERTY ${parent}_VMA)
+    get_property(group_parent_lma GLOBAL PROPERTY ${parent}_LMA)
+    if(NOT DEFINED vma)
+      get_property(vma GLOBAL PROPERTY ${parent}_VMA)
+    endif()
+    if(NOT DEFINED lma)
+      get_property(lma GLOBAL PROPERTY ${parent}_LMA)
+    endif()
+  endif()
+
+  if(DEFINED group_parent_vma AND DEFINED group_parent_lma)
+    # Something to init
+    set(part "rw ")
+  else()
+    set(part)
+  endif()
+
+
+  set_property(GLOBAL PROPERTY ILINK_CURRENT_SECTIONS)
+
+  string(REGEX REPLACE "^[\.]" "" name_clean "${name}")
+  string(REPLACE "." "_" name_clean "${name_clean}")
+
+  # WA for 'Error[Lc036]: no block or place matches the pattern "ro data section .tdata_init"'
+  if("${name_clean}" STREQUAL "tdata")
+    set(TEMP "${TEMP}define block ${name_clean}_init { ro section .tdata_init };\n")
+    set(TEMP "${TEMP}\"${name_clean}_init\": place in ${ILINK_CURRENT_NAME} { block ${name_clean}_init };\n\n")
+  endif()
+
+  get_property(indicies GLOBAL PROPERTY ${STRING_SECTION}_SETTINGS_INDICIES)
+  # ZIP_LISTS partner
+  get_property(next_indicies GLOBAL PROPERTY ${STRING_SECTION}_SETTINGS_INDICIES)
+  list(POP_FRONT next_indicies first_index)
+
+  set(first_index_section)
+  set(first_index_section_name)
+  if(DEFINED first_index)
+    # Handle case where the first section has an offset
+    get_property(first_index_offset
+      GLOBAL PROPERTY ${STRING_SECTION}_SETTING_${first_index}_OFFSET)
+    get_property(keep   GLOBAL PROPERTY ${STRING_SECTION}_SETTING_${first_index}_KEEP)
+    if(DEFINED keep)
+      set(root "root ")
+    else()
+      set(root)
+    endif()
+    if(DEFINED first_index_offset AND NOT first_index_offset EQUAL 0 )
+      set(first_index_section_name "${name_clean}_${first_index}_offset")
+      set(first_index_section
+        "define ${root}section ${first_index_section_name} {};")
+    else()
+      set(first_index)
+    endif()
+  endif()
+
+  foreach(start_symbol ${start_syms})
+    set_property(GLOBAL APPEND PROPERTY ILINK_SYMBOL_ICF "${start_symbol} = ADDR(${name_clean})")
+  endforeach()
+  foreach(end_symbol ${end_syms})
+    set_property(GLOBAL APPEND PROPERTY ILINK_SYMBOL_ICF "${end_symbol} = END(${name_clean})")
+  endforeach()
+
+  if(NOT nosymbols)
+    if("${name_clean}" STREQUAL "tdata")
+      set_property(GLOBAL APPEND PROPERTY ILINK_SYMBOL_ICF "__${name_clean}_start = (__iar_tls$$INIT_DATA$$Base)")
+      set_property(GLOBAL APPEND PROPERTY ILINK_SYMBOL_ICF "__${name_clean}_end = (__iar_tls$$INIT_DATA$$Limit)")
+    else()
+      set_property(GLOBAL APPEND PROPERTY ILINK_SYMBOL_ICF "__${name_clean}_start = ADDR(${name_clean})")
+      set_property(GLOBAL APPEND PROPERTY ILINK_SYMBOL_ICF "__${name_clean}_end = END(${name_clean})")
+    endif()
+  endif()
+  # section patterns and blocks to keep { }
+  set(to_be_kept "")
+
+  if(DEFINED first_index_section)
+    set(TEMP "${TEMP}${first_index_section}\n")
+  endif()
+
+  set(TEMP "${TEMP}define block ${name_clean} with fixed order")
+
+  if(align)
+    set(TEMP "${TEMP}, alignment=${align}")
+  elseif(subalign)
+    set(TEMP "${TEMP}, alignment = ${subalign}")
+  elseif(part)
+    set(TEMP "${TEMP}, alignment = input")
+  else()
+    set(TEMP "${TEMP}, alignment=4")
+  endif()
+  if(endalign)
+    set(TEMP "${TEMP}, end alignment=${endalign}")
+  endif()
+
+  set(TEMP "${TEMP}\n{")
+
+  # foreach(start_symbol ${start_syms})
+  #   set(TEMP "${TEMP}\n  section ${start_symbol},")
+  #   set_property(GLOBAL APPEND PROPERTY ILINK_CURRENT_SECTIONS "section ${start_symbol}")
+  # endforeach()
+
+  # if(NOT nosymbols)
+  #   set(TEMP "${TEMP}\n  section __${name_clean}_start,")
+  #   set_property(GLOBAL APPEND PROPERTY ILINK_CURRENT_SECTIONS "section __${name_clean}_start")
+  # endif()
+
+  list(GET indicies -1 last_index)
+  list(LENGTH indicies length)
+
+  if(NOT noinput)
+
+    set(TEMP "${TEMP}\n  block ${name_clean}_winput")
+    if(align)
+      list(APPEND block_attr "alignment = ${align}")
+    elseif(subalign)
+      list(APPEND block_attr "alignment = ${subalign}")
+    elseif(part)
+      # list(APPEND block_attr "alignment = input")
+    else()
+      list(APPEND block_attr "alignment=4")
+    endif()
+    list(APPEND block_attr "fixed order")
+
+    list(JOIN block_attr ", " block_attr_str)
+    if(block_attr_str)
+      set(TEMP "${TEMP} with ${block_attr_str}")
+    endif()
+    set(block_attr)
+    set(block_attr_str)
+
+    set(TEMP "${TEMP} { ${part}section ${name}, ${part}section ${name}.* }")
+    if(${length} GREATER 0)
+      set(TEMP "${TEMP},")
+    endif()
+    set_property(GLOBAL APPEND PROPERTY ILINK_CURRENT_SECTIONS "section ${name}")
+    set_property(GLOBAL APPEND PROPERTY ILINK_CURRENT_SECTIONS "section ${name}.*")
+  endif()
+
+  foreach(idx idx_next IN ZIP_LISTS indicies next_indicies)
+    get_property(align    GLOBAL PROPERTY ${STRING_SECTION}_SETTING_${idx}_ALIGN)
+    get_property(any      GLOBAL PROPERTY ${STRING_SECTION}_SETTING_${idx}_ANY)
+    get_property(first    GLOBAL PROPERTY ${STRING_SECTION}_SETTING_${idx}_FIRST)
+    get_property(keep     GLOBAL PROPERTY ${STRING_SECTION}_SETTING_${idx}_KEEP)
+    get_property(sort     GLOBAL PROPERTY ${STRING_SECTION}_SETTING_${idx}_SORT)
+    get_property(flags    GLOBAL PROPERTY ${STRING_SECTION}_SETTING_${idx}_FLAGS)
+    get_property(input    GLOBAL PROPERTY ${STRING_SECTION}_SETTING_${idx}_INPUT)
+    get_property(symbols  GLOBAL PROPERTY ${STRING_SECTION}_SETTING_${idx}_SYMBOLS)
+    # Get the next offset and use that as this ones size!
+    get_property(offset   GLOBAL PROPERTY ${STRING_SECTION}_SETTING_${idx_next}_OFFSET)
+
+    if(keep)
+      list(APPEND to_be_kept "block ${name_clean}_${idx}")
+      foreach(setting ${input})
+        list(APPEND to_be_kept "section ${setting}")
+      endforeach()
+    endif()
+    if(DEFINED symbols)
+      list(LENGTH symbols symbols_count)
+      if(${symbols_count} GREATER 0)
+        list(GET symbols 0 symbol_start)
+      endif()
+      if(${symbols_count} GREATER 1)
+        list(GET symbols 1 symbol_end)
+      endif()
+    endif()
+
+    if(DEFINED symbol_start)
+      # set(TEMP "${TEMP}\n  section ${symbol_start},")
+      # set_property(GLOBAL APPEND PROPERTY ILINK_CURRENT_SECTIONS "section ${symbol_start}")
+      set_property(GLOBAL APPEND PROPERTY ILINK_SYMBOL_ICF "${symbol_start} = ADDR(${name_clean}_${idx})")
+    endif()
+
+    if(DEFINED first_index AND first_index EQUAL ${idx})
+      # Create the offset
+      set(TEMP "${TEMP}\n  block ${first_index_section_name}")
+      list(APPEND block_attr "size = ${first_index_offset}")
+      if(sort)
+        if(${sort} STREQUAL NAME)
+          list(APPEND block_attr "alphabetical order")
+        endif()
+      endif()
+      if(align)
+        list(APPEND block_attr "alignment = ${align}")
+      elseif(subalign)
+        list(APPEND block_attr "alignment = ${subalign}")
+      elseif(part)
+        # list(APPEND block_attr "alignment = input")
+      else()
+        list(APPEND block_attr "alignment=4")
+      endif()
+      list(APPEND block_attr "fixed order")
+
+      list(JOIN block_attr ", " block_attr_str)
+      if(block_attr_str)
+        set(TEMP "${TEMP} with ${block_attr_str}")
+      endif()
+      set(block_attr)
+      set(block_attr_str)
+
+      set(TEMP "${TEMP} { section ${first_index_section_name} },\n")
+    endif()
+
+    # block init_100 with alphabetical order { section .z_init_EARLY_?_}
+    set(TEMP "${TEMP}\n  block ${name_clean}_${idx}")
+    if(DEFINED offset AND NOT offset EQUAL 0 )
+      list(APPEND block_attr "size = ${offset}")
+    elseif(DEFINED offset AND offset STREQUAL 0 )
+      # Do nothing
+    endif()
+    if(sort)
+      if(${sort} STREQUAL NAME)
+        list(APPEND block_attr "alphabetical order")
+      endif()
+    endif()
+    if(align)
+      list(APPEND block_attr "alignment = ${align}")
+    elseif(subalign)
+      list(APPEND block_attr "alignment = ${subalign}")
+    elseif(part)
+      # list(APPEND block_attr "alignment = input")
+    else()
+      list(APPEND block_attr "alignment=4")
+    endif()
+
+    # LD
+    # There are two ways to include more than one section:
+    #
+    # *(.text .rdata)
+    # *(.text) *(.rdata)
+    #
+    # The difference between these is the order in which
+    # the `.text' and `.rdata' input sections will appear in the output section.
+    # In the first example, they will be intermingled,
+    # appearing in the same order as they are found in the linker input.
+    # In the second example, all `.text' input sections will appear first,
+    # followed by all `.rdata' input sections.
+    #
+    # ILINK solved by adding 'fixed order'
+    if(NOT sort AND NOT first)
+      list(APPEND block_attr "fixed order")
+    endif()
+
+    list(JOIN block_attr ", " block_attr_str)
+    if(block_attr_str)
+      set(TEMP "${TEMP} with ${block_attr_str}")
+    endif()
+    set(block_attr)
+    set(block_attr_str)
+
+    if(empty)
+      set(TEMP "${TEMP}\n  {")
+      set(empty FALSE)
+    endif()
+
+    list(GET input -1 last_input)
+
+    set(TEMP "${TEMP} {")
+    if(NOT DEFINED input AND NOT any)
+      set(TEMP "${TEMP} }")
+    endif()
+
+    foreach(setting ${input})
+      if(first)
+        set(TEMP "${TEMP} first")
+        set(first "")
+      endif()
+
+      set(section_type "")
+
+      # build for ram, no section_type
+      # if("${lma}" STREQUAL "${vma}")
+      #		# if("${vma}" STREQUAL "")
+      #           set(section_type "")
+      #		# else()
+      #		#   set(section_type " readwrite")
+      #		# endif()
+      # elseif(NOT "${vma}" STREQUAL "")
+      #		set(section_type " readwrite")
+      # elseif(NOT "${lma}" STREQUAL "")
+      #		set(section_type " readonly")
+      # else()
+      #		message(FATAL_ERROR "How to handle this? lma=${lma} vma=${vma}")
+      # endif()
+
+      set(TEMP "${TEMP}${section_type} ${part}section ${setting}")
+      set_property(GLOBAL APPEND PROPERTY ILINK_CURRENT_SECTIONS "section ${setting}")
+      set(section_type "")
+
+      if("${setting}" STREQUAL "${last_input}")
+        set(TEMP "${TEMP} }")
+      else()
+        set(TEMP "${TEMP}, ")
+      endif()
+
+      # set(TEMP "${TEMP}\n    *.o(${setting})")
+    endforeach()
+
+    if(any)
+      if(NOT flags)
+        message(FATAL_ERROR ".ANY requires flags to be set.")
+      endif()
+      set(ANY_FLAG "")
+      foreach(flag ${flags})
+        # if("${flag}" STREQUAL +RO OR "${flag}" STREQUAL +XO)
+        #   set(ANY_FLAG "readonly")
+        # # elseif("${flag}" STREQUAL +RW)
+        # #   set(ANY_FLAG "readwrite")
+        # else
+        if("${flag}" STREQUAL +ZI)
+          set(ANY_FLAG "zeroinit")
+          set_property(GLOBAL APPEND PROPERTY ILINK_CURRENT_SECTIONS "${ANY_FLAG}")
+        endif()
+      endforeach()
+      set(TEMP "${TEMP} ${ANY_FLAG} }")
+    endif()
+
+    if(DEFINED symbol_end)
+      # set(TEMP "${TEMP},\n  section ${symbol_end}")
+      # set_property(GLOBAL APPEND PROPERTY ILINK_CURRENT_SECTIONS "section ${symbol_end}")
+      set_property(GLOBAL APPEND PROPERTY ILINK_SYMBOL_ICF "${symbol_end} = END(${name_clean}_${idx})")
+    endif()
+    if(${length} GREATER 0)
+      if(NOT "${idx}" STREQUAL "${last_index}")
+        set(TEMP "${TEMP},")
+      elseif()
+      endif()
+    endif()
+
+    set(symbol_start)
+    set(symbol_end)
+  endforeach()
+  set(next_indicies)
+
+  set(last_index)
+  set(last_input)
+  set(TEMP "${TEMP}")
+
+  # if(NOT nosymbols)
+  #   set(TEMP "${TEMP},\n  section __${name_clean}_end")
+  #   set_property(GLOBAL APPEND PROPERTY ILINK_CURRENT_SECTIONS "section __${name_clean}_end")
+  # endif()
+
+  # foreach(end_symbol ${end_syms})
+  #   set(TEMP "${TEMP},\n  section ${end_symbol}")
+  #   set_property(GLOBAL APPEND PROPERTY ILINK_CURRENT_SECTIONS "section ${end_symbol}")
+  # endforeach()
+
+  set(TEMP "${TEMP}\n};")
+
+  get_property(type GLOBAL PROPERTY ${parent}_OBJ_TYPE)
+  if(${type} STREQUAL REGION)
+    get_property(name GLOBAL PROPERTY ${parent}_NAME)
+    get_property(address GLOBAL PROPERTY ${parent}_ADDRESS)
+    get_property(size GLOBAL PROPERTY ${parent}_SIZE)
+
+  endif()
+
+  get_property(current_sections GLOBAL PROPERTY ILINK_CURRENT_SECTIONS)
+
+  if(DEFINED group_parent_vma AND DEFINED group_parent_lma)
+    if(${noinit})
+      list(JOIN current_sections ", " SELECTORS)
+      set(TEMP "${TEMP}\ndo not initialize {\n${SELECTORS}\n};")
+    else()
+      # Generate the _init block and the initialize manually statement.
+      # Note that we need to have the X_init block defined even if we have
+      # no sections, since there will come a "place in XXX" statement later.
+
+      # "${TEMP}" is there too keep the ';' else it will be a list
+      string(REGEX REPLACE "(block[ \t\r\n]+)([^ \t\r\n]+)" "\\1\\2_init" INIT_TEMP "${TEMP}")
+      string(REGEX REPLACE "(rw)([ \t\r\n]+)(section[ \t\r\n]+)([^ \t\r\n,]+)" "\\1\\2\\3\\4_init" INIT_TEMP "${INIT_TEMP}")
+      string(REGEX REPLACE "(rw)([ \t\r\n]+)(section[ \t\r\n]+)" "ro\\2\\3" INIT_TEMP "${INIT_TEMP}")
+      string(REGEX REPLACE "alphabetical order, " "" INIT_TEMP "${INIT_TEMP}")
+      string(REGEX REPLACE "{ readwrite }" "{ }" INIT_TEMP "${INIT_TEMP}")
+
+      # If any content is marked as keep, is has to be applied to the init block
+      # too, esp. for blocks that are not referenced (e.g. empty blocks wiht min_size)
+      if(to_be_kept)
+        list(APPEND to_be_kept "block ${name_clean}_init")
+      endif()
+      set(TEMP "${TEMP}\n${INIT_TEMP}\n")
+      if(DEFINED current_sections)
+        set(TEMP "${TEMP}\ninitialize manually with copy friendly\n")
+        set(TEMP "${TEMP}{\n")
+        foreach(section ${current_sections})
+          set(TEMP "${TEMP}  ${section},\n")
+        endforeach()
+        set(TEMP "${TEMP}};")
+        set(current_sections)
+      endif()
+    endif()
+  endif()
+
+  # Finally, add the keeps.
+  if(to_be_kept)
+    list(JOIN to_be_kept ", " K)
+    set(TEMP "${TEMP}\nkeep { ${K} };\n")
+  endif()
+
+  set(${STRING_STRING} "${${STRING_STRING}}\n${TEMP}\n" PARENT_SCOPE)
+endfunction()
+
+function(symbol_to_string)
+  cmake_parse_arguments(STRING "" "SYMBOL;STRING" "" ${ARGN})
+
+  get_property(name     GLOBAL PROPERTY ${STRING_SYMBOL}_NAME)
+  get_property(expr     GLOBAL PROPERTY ${STRING_SYMBOL}_EXPR)
+  get_property(size     GLOBAL PROPERTY ${STRING_SYMBOL}_SIZE)
+  get_property(symbol   GLOBAL PROPERTY ${STRING_SYMBOL}_SYMBOL)
+  get_property(subalign GLOBAL PROPERTY ${STRING_SYMBOL}_SUBALIGN)
+
+  string(REPLACE "\\" "" expr "${expr}")
+  string(REGEX MATCHALL "@([^@]*)@" match_res ${expr})
+
+  foreach(match ${match_res})
+    string(REPLACE "@" "" match ${match})
+    get_property(symbol_val GLOBAL PROPERTY SYMBOL_TABLE_${match})
+    string(REPLACE "@${match}@" "${match}" expr ${expr})
+  endforeach()
+
+  list(LENGTH match_res match_res_count)
+
+  if(match_res_count)
+    if(${match_res_count} GREATER 1)
+      set(${STRING_STRING}
+        "${${STRING_STRING}}define image symbol ${symbol} = ${expr};\n"
+        )
+    else()
+      if((expr MATCHES "Base|Limit|Length") OR (expr MATCHES "ADDR\\(|END\\(|SIZE\\("))
+        # Anything like $$Base/$$Limit/$$Length should be an image symbol
+        if( "${symbol}" STREQUAL "__tdata_size")
+          # This will handle the alignment of the TBSS block
+          set(${STRING_STRING}
+            "${${STRING_STRING}}define image symbol ${symbol}=(__iar_tls$$INIT_DATA$$Limit-__iar_tls$$INIT_DATA$$Base);\n"
+            )
+        elseif( "${symbol}" STREQUAL "__tbss_size")
+          # This will handle the alignment of the TBSS block by
+          # pre-padding bytes
+          set(${STRING_STRING}
+            "${${STRING_STRING}}define image symbol ${symbol}=((tbss$$Limit-__iar_tls$$DATA$$Base)-(__iar_tls$$INIT_DATA$$Limit-__iar_tls$$INIT_DATA$$Base));\n"
+            )
+        else()
+          set(${STRING_STRING}
+            "${${STRING_STRING}}define image symbol ${symbol} = ${expr};\n"
+            )
+        endif()
+      else()
+        list(GET match_res 0 match)
+        string(REPLACE "@" "" match ${match})
+        get_property(symbol_val GLOBAL PROPERTY SYMBOL_TABLE_${match})
+        if(symbol_val)
+          set(${STRING_STRING}
+            "${${STRING_STRING}}define image symbol ${symbol} = ${expr};\n"
+            )
+        else()
+          # Treatmen of "zephyr_linker_symbol(SYMBOL z_arm_platform_init EXPR "@SystemInit@")"
+          set_property(GLOBAL APPEND PROPERTY SYMBOL_STEERING_FILE
+            "--redirect ${symbol}=${expr}\n"
+            )
+        endif()
+      endif()
+    endif()
+  else()
+    # Handle things like ADDR(.ramfunc)
+    if(${expr} MATCHES "^[A-Za-z]?ADDR\\(.+\\)")
+      # string(REGEX REPLACE "^[A-Za-z]?ADDR\\((.+)\\)" "(\\1$$Base)" expr ${expr})
+      set(${STRING_STRING}
+        "${${STRING_STRING}}define image symbol ${symbol} = ${expr};\n"
+        )
+    else()
+      set(${STRING_STRING}
+        "${${STRING_STRING}}define exported symbol ${symbol} = ${expr};\n"
+        )
+    endif()
+  endif()
+
+  set(${STRING_STRING} ${${STRING_STRING}} PARENT_SCOPE)
+endfunction()
+
+include(${CMAKE_CURRENT_LIST_DIR}/../linker_script_common.cmake)
+
+if(DEFINED STEERING_FILE)
+  get_property(steering_content GLOBAL PROPERTY SYMBOL_STEERING_FILE)
+  file(WRITE ${STEERING_FILE}  "/* AUTO-GENERATED - Do not modify\n")
+  file(APPEND ${STEERING_FILE} " * AUTO-GENERATED - All changes will be lost\n")
+  file(APPEND ${STEERING_FILE} " */\n")
+
+  file(APPEND ${STEERING_FILE} ${steering_content})
+endif()
diff --git a/cmake/linker/iar/linker_flags.cmake b/cmake/linker/iar/linker_flags.cmake
new file mode 100644
index 00000000000..f65925ff8a8
--- /dev/null
+++ b/cmake/linker/iar/linker_flags.cmake
@@ -0,0 +1,14 @@
+# Copyright (c) 2025 IAR Systems AB
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Override the default CMake's IAR ILINK linker signature
+
+string(APPEND CMAKE_C_LINK_FLAGS --no-wrap-diagnostics  )
+
+foreach(lang C CXX ASM)
+  set(commands "--log modules,libraries,initialization,redirects,sections")
+  set(CMAKE_${lang}_LINK_EXECUTABLE
+  "<CMAKE_LINKER> <CMAKE_${lang}_LINK_FLAGS> <LINK_FLAGS> ${commands} <LINK_LIBRARIES> <OBJECTS> -o <TARGET>")
+  set(commands)
+endforeach()
diff --git a/cmake/linker/iar/target.cmake b/cmake/linker/iar/target.cmake
new file mode 100644
index 00000000000..f2326b60491
--- /dev/null
+++ b/cmake/linker/iar/target.cmake
@@ -0,0 +1,135 @@
+# Copyright (c) 2025 IAR Systems AB
+#
+# SPDX-License-Identifier: Apache-2.0
+
+set_property(TARGET linker PROPERTY devices_start_symbol "_device_list_start")
+find_program(CMAKE_LINKER
+  NAMES ${CROSS_COMPILE}${IAR_LINKER}
+  PATHS ${TOOLCHAIN_HOME}
+  PATH_SUFFIXES bin
+  NO_DEFAULT_PATH
+)
+
+add_custom_target(${IAR_LINKER})
+set(ILINK_THUMB_CALLS_WARNING_SUPPRESSED)
+set(IAR_LIB_USED)
+function(toolchain_ld_force_undefined_symbols "")
+#  foreach(symbol ${ARGN})
+#    zephyr_link_libraries(--place_holder=${symbol})
+#  endforeach()
+endfunction()
+
+# NOTE: ${linker_script_gen} will be produced at build-time; not at configure-time
+macro(configure_linker_script linker_script_gen linker_pass_define)
+  set(extra_dependencies ${ARGN})
+  set(STEERING_FILE "${CMAKE_CURRENT_BINARY_DIR}/${linker_script_gen}.xcl")
+  set(STEERING_FILE_ARG "-DSTEERING_FILE=${STEERING_FILE}")
+  set(cmake_linker_script_settings
+      ${PROJECT_BINARY_DIR}/include/generated/ld_script_settings_${linker_pass_define}.cmake
+  )
+  if("${linker_pass_define}" STREQUAL "LINKER_ZEPHYR_PREBUILT")
+    set(ILINK_THUMB_CALLS_WARNING_SUPPRESSED "--diag_suppress=Lt056")
+  else()
+    set(ILINK_THUMB_CALLS_WARNING_SUPPRESSED "")
+  endif()
+  if(CONFIG_IAR_LIBC OR CONFIG_IAR_LIBCPP)
+    set(IAR_LIB_USED "-DIAR_LIBC=1")
+  else()
+    set(IAR_LIB_USED "")
+  endif()
+
+  file(GENERATE OUTPUT ${cmake_linker_script_settings} CONTENT
+       "set(FORMAT \"$<TARGET_PROPERTY:linker,FORMAT>\" CACHE INTERNAL \"\")\n
+        set(ENTRY \"$<TARGET_PROPERTY:linker,ENTRY>\" CACHE INTERNAL \"\")\n
+        set(MEMORY_REGIONS \"$<TARGET_PROPERTY:linker,MEMORY_REGIONS>\" CACHE INTERNAL \"\")\n
+        set(GROUPS \"$<TARGET_PROPERTY:linker,GROUPS>\" CACHE INTERNAL \"\")\n
+        set(SECTIONS \"$<TARGET_PROPERTY:linker,SECTIONS>\" CACHE INTERNAL \"\")\n
+        set(SECTION_SETTINGS \"$<TARGET_PROPERTY:linker,SECTION_SETTINGS>\" CACHE INTERNAL \"\")\n
+        set(SYMBOLS \"$<TARGET_PROPERTY:linker,SYMBOLS>\" CACHE INTERNAL \"\")\n
+       "
+    )
+  add_custom_command(
+    OUTPUT ${linker_script_gen}
+           ${STEERING_FILE}
+    DEPENDS
+           ${extra_dependencies}
+           ${DEVICE_API_LD_TARGET}
+    COMMAND ${CMAKE_COMMAND}
+      -C ${DEVICE_API_LINKER_SECTIONS_CMAKE}
+      -C ${cmake_linker_script_settings}
+      -DPASS="${linker_pass_define}"
+      ${STEERING_FILE_ARG}
+      -DCONFIG_LINKER_LAST_SECTION_ID=${CONFIG_LINKER_LAST_SECTION_ID}
+      -DCONFIG_LINKER_LAST_SECTION_ID_PATTERN=${CONFIG_LINKER_LAST_SECTION_ID_PATTERN}
+      -DOUT_FILE=${CMAKE_CURRENT_BINARY_DIR}/${linker_script_gen}
+      ${IAR_LIB_USED}
+      -P ${ZEPHYR_BASE}/cmake/linker/iar/config_file_script.cmake
+  )
+
+endmacro()
+
+function(toolchain_ld_link_elf)
+  cmake_parse_arguments(
+    TOOLCHAIN_LD_LINK_ELF                                     # prefix of output variables
+    ""                                                        # list of names of the boolean arguments
+    "TARGET_ELF;OUTPUT_MAP;LINKER_SCRIPT"                     # list of names of scalar arguments
+    "LIBRARIES_PRE_SCRIPT;LIBRARIES_POST_SCRIPT;DEPENDENCIES" # list of names of list arguments
+    ${ARGN}                                                   # input args to parse
+  )
+
+  foreach(lib ${ZEPHYR_LIBS_PROPERTY})
+    list(APPEND ZEPHYR_LIBS_OBJECTS $<TARGET_OBJECTS:${lib}>)
+    list(APPEND ZEPHYR_LIBS_OBJECTS $<TARGET_PROPERTY:${lib},LINK_LIBRARIES>)
+  endforeach()
+
+  set(ILINK_SEMIHOSTING)
+  set(ILINK_BUFFERED_WRITE)
+  if(${CONFIG_IAR_SEMIHOSTING})
+    set(ILINK_SEMIHOSTING "--semihosting")
+  endif()
+  if(${CONFIG_IAR_BUFFERED_WRITE})
+    set(ILINK_BUFFERED_WRITE "--redirect __write=__write_buffered")
+  endif()
+
+  set(ILINK_XCL "-f ${TOOLCHAIN_LD_LINK_ELF_LINKER_SCRIPT}.xcl")
+
+  set(ILINK_TLS_LIBRARY)
+  if(${CONFIG_THREAD_LOCAL_STORAGE})
+    set(ILINK_TLS_LIBRARY "--threaded_lib=manual")
+  endif()
+
+  set(ILINK_TZONE_LIBRARY)
+  # if(${CONFIG_IAR_LIBC})
+  #   set(ILINK_TZONE_LIBRARY "--timezone_lib")
+  # endif()
+
+  target_link_libraries(
+    ${TOOLCHAIN_LD_LINK_ELF_TARGET_ELF}
+    ${TOOLCHAIN_LD_LINK_ELF_LIBRARIES_PRE_SCRIPT}
+    --config=${TOOLCHAIN_LD_LINK_ELF_LINKER_SCRIPT}
+    ${TOOLCHAIN_LD_LINK_ELF_LIBRARIES_POST_SCRIPT}
+    --map=${TOOLCHAIN_LD_LINK_ELF_OUTPUT_MAP}
+    --log_file=${TOOLCHAIN_LD_LINK_ELF_OUTPUT_MAP}.log
+
+    ${ZEPHYR_LIBS_OBJECTS}
+    kernel
+    $<TARGET_OBJECTS:${OFFSETS_LIB}>
+    --entry=$<TARGET_PROPERTY:linker,ENTRY>
+
+    ${ILINK_SEMIHOSTING}
+    ${ILINK_BUFFERED_WRITE}
+    ${ILINK_TLS_LIBRARY}
+    ${ILINK_TZONE_LIBRARY}
+    ${ILINK_THUMB_CALLS_WARNING_SUPPRESSED}
+    # Do not remove symbols
+    #--no_remove
+    ${ILINK_XCL}
+
+    ${TOOLCHAIN_LIBS_OBJECTS}
+
+    ${TOOLCHAIN_LD_LINK_ELF_DEPENDENCIES}
+  )
+endfunction(toolchain_ld_link_elf)
+
+include(${ZEPHYR_BASE}/cmake/linker/ld/target_relocation.cmake)
+include(${ZEPHYR_BASE}/cmake/linker/ld/target_configure.cmake)
diff --git a/cmake/linker/ld/ld_script.cmake b/cmake/linker/ld/ld_script.cmake
index 76cb5b433f1..22fd1b66d62 100644
--- a/cmake/linker/ld/ld_script.cmake
+++ b/cmake/linker/ld/ld_script.cmake
@@ -88,6 +88,10 @@ function(group_to_string)
   cmake_parse_arguments(STRING "" "OBJECT;STRING" "" ${ARGN})
 
   get_property(type GLOBAL PROPERTY ${STRING_OBJECT}_OBJ_TYPE)
+
+  # Output a comment for the section start
+  set(${STRING_STRING} "${${STRING_STRING}}\n  /* ${type} : ${STRING_OBJECT} */")
+
   if(${type} STREQUAL REGION)
     get_property(empty GLOBAL PROPERTY ${STRING_OBJECT}_EMPTY)
     if(empty)
@@ -168,6 +172,16 @@ function(group_to_string)
   set(${STRING_STRING} ${${STRING_STRING}} PARENT_SCOPE)
 endfunction()
 
+# Helper to add size-checks and padding to handle MIN_SIZE and MAX_SIZE
+macro(add_min_max_size TEMP min_size max_size symbol_start symbol_end)
+  if(DEFINED ${min_size})
+    set(${TEMP} "${${TEMP}}\n  . = MAX(${${symbol_start}} + ${${min_size}}, .); /*MIN_SIZE*/")
+  endif()
+  if(DEFINED ${max_size})
+    set(${TEMP} "${${TEMP}}\n  ASSERT( ${${symbol_end}} <= ( ${${symbol_start}} + ${${max_size}}), \"MAX_SIZE\");\n . = MIN( ., ${${symbol_start}} + ${${max_size}}); /*MAX_SIZE*/")
+  endif()
+endmacro()
+
 function(section_to_string)
   cmake_parse_arguments(STRING "" "SECTION;STRING" "" ${ARGN})
 
@@ -185,6 +199,8 @@ function(section_to_string)
   get_property(nosymbols  GLOBAL PROPERTY ${STRING_SECTION}_NOSYMBOLS)
   get_property(parent     GLOBAL PROPERTY ${STRING_SECTION}_PARENT)
   get_property(start_syms GLOBAL PROPERTY ${STRING_SECTION}_START_SYMBOLS)
+  get_property(sect_min_size GLOBAL PROPERTY ${STRING_SECTION}_MIN_SIZE)
+  get_property(sect_max_size GLOBAL PROPERTY ${STRING_SECTION}_MAX_SIZE)
 
   string(REGEX REPLACE "^[\.]" "" name_clean "${name}")
   string(REPLACE "." "_" name_clean "${name_clean}")
@@ -212,12 +228,24 @@ function(section_to_string)
 
   set(TEMP "${name} ${address}${type} :${secalign}\n{")
 
+  # Symbol names for size_check
+  set(sect_symbol_start)
+  set(sect_symbol_end)
+
   foreach(start_symbol ${start_syms})
     set(TEMP "${TEMP}\n  ${start_symbol} = .;")
+    set(sect_symbol_start "${start_symbol}")
   endforeach()
 
   if(NOT nosymbols)
     set(TEMP "${TEMP}\n  __${name_clean}_start = .;")
+    set(sect_symbol_start "__${name_clean}_start")
+  endif()
+
+  # Min and Max size may need symbols too, even if the user did not want them
+  if((DEFINED sect_min_size OR DEFINED sect_max_size)
+    AND NOT DEFINED sect_symbol_start)
+      set(sect_symbol_start "__${name_clean}_size_check_start")
   endif()
 
   if(NOT noinput)
@@ -236,8 +264,10 @@ function(section_to_string)
     get_property(input    GLOBAL PROPERTY ${STRING_SECTION}_SETTING_${idx}_INPUT)
     get_property(symbols  GLOBAL PROPERTY ${STRING_SECTION}_SETTING_${idx}_SYMBOLS)
     get_property(offset   GLOBAL PROPERTY ${STRING_SECTION}_SETTING_${idx}_OFFSET)
+    get_property(min_size   GLOBAL PROPERTY ${STRING_SECTION}_SETTING_${idx}_MIN_SIZE)
+    get_property(max_size   GLOBAL PROPERTY ${STRING_SECTION}_SETTING_${idx}_MAX_SIZE)
 
-    if(DEFINED SETTINGS_ALIGN)
+    if(DEFINED align)
       set(TEMP "${TEMP}\n  . = ALIGN(${align});")
     endif()
 
@@ -250,6 +280,19 @@ function(section_to_string)
         list(GET symbols 1 symbol_end)
       endif()
     endif()
+    # Min and Max size may need symbols too, even if the user did not want them
+    if(DEFINED min_size OR DEFINED max_size)
+      foreach(se "start" "end")
+        if(NOT DEFINED symbol_${se})
+          set(symbol_${se} "__${name_clean}_${idx}_size_check_${se}")
+        endif()
+      endforeach()
+    endif()
+
+    if(DEFINED offset AND NOT ("${offset}" STREQUAL "${current_offset}"))
+      set(TEMP "${TEMP}\n  . = ${offset}; /* OFFSET */")
+      set(current_offset ${offset})
+    endif()
 
     if(DEFINED symbol_start)
       set(TEMP "${TEMP}\n  ${symbol_start} = .;")
@@ -261,34 +304,53 @@ function(section_to_string)
         set(current_offset ${offset})
       endif()
 
-      if(keep AND sort)
-        set(TEMP "${TEMP}\n  KEEP(*(${SORT_TYPE_${sort}}(${setting})));")
-      elseif(SETTINGS_SORT)
-        message(WARNING "Not tested")
-        set(TEMP "${TEMP}\n  *(${SORT_TYPE_${sort}}(${setting}));")
-      elseif(keep)
-        set(TEMP "${TEMP}\n  KEEP(*(${setting}));")
+      #setting may have file-pattern or not.
+      if(setting MATCHES "(.+)\\((.+)\\)")
+        set(file_pattern "${CMAKE_MATCH_1}")
+        set(section_pattern "${CMAKE_MATCH_2}")
       else()
-        set(TEMP "${TEMP}\n  *(${setting})")
+        set(file_pattern "*")
+        set(section_pattern "${setting}")
+      endif()
+
+      if(sort)
+        set(section_pattern "${SORT_TYPE_${sort}}(${section_pattern})")
+      endif()
+      set(pattern "${file_pattern}(${section_pattern})")
+      if(keep)
+        set(pattern "KEEP(${pattern})")
       endif()
+      set(TEMP "${TEMP}\n  ${pattern};")
     endforeach()
 
     if(DEFINED symbol_end)
       set(TEMP "${TEMP}\n  ${symbol_end} = .;")
     endif()
 
+    add_min_max_size(TEMP min_size max_size symbol_start symbol_end)
+
     set(symbol_start)
     set(symbol_end)
   endforeach()
 
   if(NOT nosymbols)
     set(TEMP "${TEMP}\n  __${name_clean}_end = .;")
+    set(sect_symbol_end "__${name_clean}_end")
   endif()
 
   if(DEFINED extra_symbol_end)
     set(TEMP "${TEMP}\n  ${extra_symbol_end} = .;")
+    set(sect_symbol_end "${extra_symbol_end}")
+  endif()
+
+  # Min and Max size may need symbols too, even if the user did not want them
+  if((DEFINED sect_min_size OR DEFINED sect_max_size)
+    AND NOT DEFINED sect_symbol_end)
+      set(sect_symbol_end "__${name_clean}_size_check_end")
   endif()
 
+  add_min_max_size(TEMP sect_min_size sect_max_size sect_symbol_start sect_symbol_end)
+
   set(TEMP "${TEMP}\n}")
 
   get_property(parent_type GLOBAL PROPERTY ${parent}_OBJ_TYPE)
diff --git a/cmake/linker/ld/target.cmake b/cmake/linker/ld/target.cmake
index 6bbc11af14a..cee3dd011bc 100644
--- a/cmake/linker/ld/target.cmake
+++ b/cmake/linker/ld/target.cmake
@@ -23,25 +23,20 @@ macro(configure_linker_script linker_script_gen linker_pass_define)
   )
 
   if(CONFIG_CMAKE_LINKER_GENERATOR)
-    file(GENERATE OUTPUT ${cmake_linker_script_settings} CONTENT
-         "set(FORMAT \"$<TARGET_PROPERTY:linker,FORMAT>\" CACHE INTERNAL \"\")\n
-          set(ENTRY \"$<TARGET_PROPERTY:linker,ENTRY>\" CACHE INTERNAL \"\")\n
-          set(MEMORY_REGIONS \"$<TARGET_PROPERTY:linker,MEMORY_REGIONS>\" CACHE INTERNAL \"\")\n
-          set(GROUPS \"$<TARGET_PROPERTY:linker,GROUPS>\" CACHE INTERNAL \"\")\n
-          set(SECTIONS \"$<TARGET_PROPERTY:linker,SECTIONS>\" CACHE INTERNAL \"\")\n
-          set(SECTION_SETTINGS \"$<TARGET_PROPERTY:linker,SECTION_SETTINGS>\" CACHE INTERNAL \"\")\n
-          set(SYMBOLS \"$<TARGET_PROPERTY:linker,SYMBOLS>\" CACHE INTERNAL \"\")\n
-         "
-    )
+
+    zephyr_linker_generate_linker_settings_file(${cmake_linker_script_settings})
+
     add_custom_command(
       OUTPUT ${linker_script_gen}
+      DEPENDS
+        ${extra_dependencies}
+        ${cmake_linker_script_settings}
+        ${DEVICE_API_LD_TARGET}
       COMMAND ${CMAKE_COMMAND}
-        -C ${DEVICE_API_LINKER_SECTIONS_CMAKE}
         -C ${cmake_linker_script_settings}
         -DPASS="${linker_pass_define}"
         -DOUT_FILE=${CMAKE_CURRENT_BINARY_DIR}/${linker_script_gen}
         -P ${ZEPHYR_BASE}/cmake/linker/ld/ld_script.cmake
-      DEPENDS ${DEVICE_API_LD_TARGET}
     )
   else()
     set(template_script_defines ${linker_pass_define})
diff --git a/cmake/linker/linker_script_common.cmake b/cmake/linker/linker_script_common.cmake
index 017de14cf6b..272fe797777 100644
--- a/cmake/linker/linker_script_common.cmake
+++ b/cmake/linker/linker_script_common.cmake
@@ -1,7 +1,8 @@
+find_package(Zephyr REQUIRED COMPONENTS extensions HINTS ${CMAKE_CURRENT_LIST_DIR}/../../)
+
 #
 # Create functions - start
 #
-
 function(create_system)
   cmake_parse_arguments(OBJECT "" "ENTRY;FORMAT;NAME;OBJECT" "" ${ARGN})
 
@@ -47,6 +48,7 @@ function(get_parent)
     return()
   endif()
 
+  # Follow parent pointers until a GET_PARENT_TYPE is reached
   get_property(parent GLOBAL PROPERTY ${GET_PARENT_OBJECT}_PARENT)
   get_property(type   GLOBAL PROPERTY ${parent}_OBJ_TYPE)
   while(NOT ${type} STREQUAL ${GET_PARENT_TYPE})
@@ -94,15 +96,34 @@ function(create_group)
   set(${OBJECT_OBJECT} GROUP_${OBJECT_NAME} PARENT_SCOPE)
 endfunction()
 
+function(is_active_in_pass ret_ptr current_pass pass_rules)
+  # by validation in zephyr_linker_* we know that if there is a NOT,
+  # it is the first, and the other entries are pass names
+  if(NOT pass_rules)
+    set(result 1)
+  elseif("NOT" IN_LIST pass_rules)
+    set(result 1)
+    if(current_pass IN_LIST pass_rules)
+      set(result 0)
+    endif()
+  else()
+    set(result 0)
+    if(current_pass IN_LIST pass_rules)
+      set(result 1)
+    endif()
+  endif()
+  set(${ret_ptr} ${result} PARENT_SCOPE)
+endfunction()
+
 function(create_section)
-  set(single_args "NAME;ADDRESS;ALIGN_WITH_INPUT;TYPE;ALIGN;ENDALIGN;SUBALIGN;VMA;LMA;NOINPUT;NOINIT;NOSYMBOLS;GROUP;SYSTEM")
+  set(single_args "NAME;ADDRESS;ALIGN_WITH_INPUT;TYPE;ALIGN;ENDALIGN;SUBALIGN;VMA;LMA;NOINPUT;NOINIT;NOSYMBOLS;GROUP;SYSTEM;MIN_SIZE;MAX_SIZE")
   set(multi_args  "PASS")
 
   cmake_parse_arguments(SECTION "" "${single_args}" "${multi_args}" ${ARGN})
 
   if(DEFINED SECTION_PASS)
-    if(NOT (${SECTION_PASS} IN_LIST PASS))
-      # This section is not active in this pass, ignore.
+    is_active_in_pass(active ${PASS} "${SECTION_PASS}")
+    if(NOT active)
       return()
     endif()
   endif()
@@ -119,6 +140,8 @@ function(create_section)
   set_property(GLOBAL PROPERTY SECTION_${SECTION_NAME}_NOINPUT          ${SECTION_NOINPUT})
   set_property(GLOBAL PROPERTY SECTION_${SECTION_NAME}_NOINIT           ${SECTION_NOINIT})
   set_property(GLOBAL PROPERTY SECTION_${SECTION_NAME}_NOSYMBOLS        ${SECTION_NOSYMBOLS})
+  set_property(GLOBAL PROPERTY SECTION_${SECTION_NAME}_MIN_SIZE         ${SECTION_MIN_SIZE})
+  set_property(GLOBAL PROPERTY SECTION_${SECTION_NAME}_MAX_SIZE         ${SECTION_MAX_SIZE})
 
   string(REGEX REPLACE "^[\.]" "" name_clean "${SECTION_NAME}")
   string(REPLACE "." "_" name_clean "${name_clean}")
@@ -130,7 +153,7 @@ function(create_section)
   set_property(GLOBAL PROPERTY SYMBOL_TABLE___${name_clean}_end        ${name_clean})
 
   set(INDEX 100)
-  set(settings_single "ALIGN;ANY;FIRST;KEEP;OFFSET;PRIO;SECTION;SORT")
+  set(settings_single "ALIGN;ANY;FIRST;KEEP;OFFSET;PRIO;SECTION;SORT;MIN_SIZE;MAX_SIZE")
   set(settings_multi  "FLAGS;INPUT;PASS;SYMBOLS")
   foreach(settings ${SECTION_SETTINGS} ${DEVICE_API_SECTION_SETTINGS})
     if("${settings}" MATCHES "^{(.*)}$")
@@ -141,8 +164,8 @@ function(create_section)
       endif()
 
       if(DEFINED SETTINGS_PASS)
-        if(NOT (${SETTINGS_PASS} IN_LIST PASS))
-          # This section setting is not active in this pass, ignore.
+        is_active_in_pass(active ${PASS} "${SETTINGS_PASS}")
+        if(NOT active)
           continue()
         endif()
       endif()
@@ -240,6 +263,7 @@ function(add_region)
   set_property(GLOBAL APPEND PROPERTY ${ADD_REGION_OBJECT}_REGIONS ${ADD_REGION_REGION})
 endfunction()
 
+# add_group OBJECT o GROUP g adds group g to object o
 function(add_group)
   cmake_parse_arguments(ADD_GROUP "" "OBJECT;GROUP" "" ${ARGN})
 
@@ -352,9 +376,12 @@ function(find_object)
   endif()
 endfunction()
 
+# get_object(LIST l OBJECT o TYPE t)
+# sets l to a list of objects of type t that are children of o
 function(get_objects)
   cmake_parse_arguments(GET "" "LIST;OBJECT;TYPE" "" ${ARGN})
 
+  # Get what type of object we are starting from
   get_property(type GLOBAL PROPERTY ${GET_OBJECT}_OBJ_TYPE)
 
   if(${type} STREQUAL SECTION)
@@ -371,11 +398,14 @@ function(get_objects)
 
   set(out)
 
+  # Find (other) regions in our system
   get_parent(OBJECT ${GET_OBJECT} PARENT parent TYPE SYSTEM)
   get_property(regions GLOBAL PROPERTY ${parent}_REGIONS)
   list(REMOVE_ITEM regions ${GET_OBJECT})
 
   if(${GET_TYPE} STREQUAL SECTION)
+    # If we are retrieving sections, then we need to get _SECTIONS_FIXED,
+    # sections from sub-groups, and immediate setion children
     get_property(sections GLOBAL PROPERTY ${GET_OBJECT}_SECTIONS_FIXED)
     list(APPEND out ${sections})
 
@@ -388,6 +418,7 @@ function(get_objects)
     get_property(sections GLOBAL PROPERTY ${GET_OBJECT}_SECTIONS)
     list(APPEND out ${sections})
 
+    # Now pick up sections from each region via the _vma_ properties.
     foreach(region ${regions})
       get_property(vma GLOBAL PROPERTY ${region}_NAME)
 
@@ -406,6 +437,8 @@ function(get_objects)
   endif()
 
   if(${GET_TYPE} STREQUAL GROUP)
+    # For groups we add immediate sub-groups, and all their descendant groups,
+    # and all the _vma_ groups and descendants
     get_property(groups GLOBAL PROPERTY ${GET_OBJECT}_GROUPS)
     list(APPEND out ${groups})
 
@@ -520,6 +553,7 @@ function(process_region_common)
     endif()
   endif()
 
+  # Loop over other regions with the same parent
   get_parent(OBJECT ${REGION_COMMON_OBJECT} PARENT parent TYPE SYSTEM)
   get_property(regions GLOBAL PROPERTY ${parent}_REGIONS)
   list(REMOVE_ITEM regions ${REGION_COMMON_OBJECT})
@@ -617,6 +651,102 @@ endfunction()
 # String functions - end
 #
 
+## Preprocess and gather input
+foreach(VAR ${VARIABLES})
+  if("${VAR}" MATCHES "^{(.*)}$")
+    cmake_parse_arguments(VAR "" "VAR;VALUE" "PASS" ${CMAKE_MATCH_1})
+
+    if(DEFINED VAR_PASS)
+      is_active_in_pass(active ${PASS} "${VAR_PASS}")
+      if(NOT active)
+        continue()
+      endif()
+    endif()
+
+    set(${VAR_VAR} "${VAR_VALUE}" CACHE INTERNAL "")
+  endif()
+endforeach()
+
+# By the input we have INCLUDES defined that contains the files that we need
+# to include depending on linker pass.
+foreach(file ${INCLUDES})
+  if("${file}" MATCHES "^{(.*)}$")
+    cmake_parse_arguments(INC "" "KCONFIG;HEADER;CMAKE" "PASS" ${CMAKE_MATCH_1})
+
+    if(DEFINED INC_PASS)
+      is_active_in_pass(active ${PASS} "${INC_PASS}")
+      if(NOT active)
+        continue()
+      endif()
+    endif()
+
+    if(CMAKE_VERBOSE_MAKEFILE)
+      message("Reading file ${INC_KCONFIG}${INC_HEADER}${INC_CMAKE}")
+    endif()
+
+    if(INC_KCONFIG)
+      import_kconfig(CONFIG ${INC_KCONFIG})
+    elseif(INC_CMAKE)
+      include(${INC_CMAKE})
+    elseif(INC_HEADER)
+      list(APPEND PREPROCESSOR_FILES ${INC_HEADER})
+    endif()
+  endif()
+endforeach()
+
+# For now, lets start with @FOO@ and store each #define FOO value as a global
+# property AT_VAR_FOO (prefix to avoid name clashes).
+# We will do all the replacements in the input lists before giving them to the
+# generator functions.
+set(VAR_DEF_REGEX "#define ([A-Za-z0-9_]+)[ \t\r\n]+(.+)")
+foreach(file IN LISTS PREPROCESSOR_FILES )
+  if(EXISTS ${file})
+    file(STRINGS ${file} defs REGEX ${VAR_DEF_REGEX})
+    foreach(def ${defs})
+      if(${def} MATCHES ${VAR_DEF_REGEX})
+        set("AT_VAR_${CMAKE_MATCH_1}" "${CMAKE_MATCH_2}")
+      endif()
+    endforeach()
+  else()
+    message("Missing file ${file}")
+  endif()
+endforeach()
+
+# To pickup information gathered by the scripts from the previous pass, we use
+# the syntax @FOO@ where FOO is a cmake variable name
+function(do_var_replace_in res_ptr src)
+  string(REGEX MATCHALL "@([^@]*)@" match_res "${src}")
+  foreach(match IN LISTS match_res)
+    string(REPLACE "@" "" expr ${match})
+    # the variable expression is as follows:
+    # @NAME[,undef:VALUE]@ Where the VALUE gets picked if we dont find NAME
+    string(REPLACE "," ";" expr ${expr})
+    list(GET expr 0 var)
+    if(DEFINED "AT_VAR_${var}")
+      set(value "${AT_VAR_${var}}")
+    elseif(DEFINED ${var}) # set by zephyr_linker_include_generated files
+      set(value "${${var}}")
+    elseif("${expr}" MATCHES ";undef:([^,]*)")
+      set(value "${CMAKE_MATCH_1}")
+    else()
+      set(value "${match}")
+      # can't warn here because we can't check for what is relevant in this pass
+      # message(WARNING "Missing definition for ${match}")
+    endif()
+
+    if(CMAKE_VERBOSE_MAKEFILE)
+      message("Using variable ${match} with value ${value}")
+    endif()
+    string(REPLACE "${match}" "${value}" src "${src}")
+  endforeach()
+  set(${res_ptr} "${src}" PARENT_SCOPE)
+endfunction()
+
+foreach(input IN ITEMS "MEMORY_REGIONS" "GROUPS" "SECTIONS" "SECTION_SETTINGS")
+  do_var_replace_in(${input} "${${input}}")
+endforeach()
+
+
 create_system(OBJECT new_system NAME ZEPHYR_LINKER_v1 FORMAT ${FORMAT} ENTRY ${ENTRY})
 
 # Sorting the memory sections in ascending order.
@@ -641,7 +771,6 @@ endforeach()
 foreach(region ${MEMORY_REGIONS_SORTED})
   if("${region}" MATCHES "^{(.*)}$")
     create_region(OBJECT new_region ${CMAKE_MATCH_1})
-
     add_region(OBJECT ${new_system} REGION ${new_region})
   endif()
 endforeach()
diff --git a/cmake/linker_script/arm/linker.cmake b/cmake/linker_script/arm/linker.cmake
index ad639f373cc..94c2af6e4c5 100644
--- a/cmake/linker_script/arm/linker.cmake
+++ b/cmake/linker_script/arm/linker.cmake
@@ -1,14 +1,38 @@
 set(COMMON_ZEPHYR_LINKER_DIR ${ZEPHYR_BASE}/cmake/linker_script/common)
 
-set_ifndef(region_min_align CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE)
+# This should be different for cortex_r or cortex_a....
+# cut from zephyr/include/zephyr/arch/arm/cortex_m/scripts/linker.ld
+if(DEFINED CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE)
+  set_ifndef(region_min_align ${CONFIG_CUSTOM_SECTION_MIN_ALIGN_SIZE})
+endif()
 
 # Set alignment to CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE if not set above
 # to make linker section alignment comply with MPU granularity.
-set_ifndef(region_min_align CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
+if(DEFINED CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE)
+  set_ifndef(region_min_align ${CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE})
+endif()
 
 # If building without MPU support, use default 4-byte alignment.. if not set above.
 set_ifndef(region_min_align 4)
 
+zephyr_linker_include_var(VAR region_min_align)
+if((NOT DEFINED CONFIG_CUSTOM_SECTION_ALIGN) AND DEFINED  CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
+  # define MPU_ALIGN(region_size) \
+  # . = ALIGN(_region_min_align); \
+  # . = ALIGN( 1 << LOG2CEIL(region_size))
+  # Handling this requires us to handle log2ceil() in iar linker since the size
+  # isn't known until then.
+  set(MPU_ALIGN_BYTES ${region_min_align})
+  #message(WARNING "We can not handle . = ALIGN( 1 << LOG2CEIL(region_size))  ")
+else()
+  set(MPU_ALIGN_BYTES ${region_min_align})
+endif()
+# The APP_SHARED_ALIGN and SMEM_PARTITION_ALIGN macros are defined as
+# ". = ALIGN(...)" things.
+# the cmake generator stuff needs an align-size in bytes so:
+zephyr_linker_include_var(VAR APP_SHARED_ALIGN_BYTES VALUE ${region_min_align})
+zephyr_linker_include_var(VAR SMEM_PARTITION_ALIGN_BYTES VALUE ${MPU_ALIGN_BYTES})
+
 # Note, the `+ 0` in formulas below avoids errors in cases where a Kconfig
 #       variable is undefined and thus expands to nothing.
 math(EXPR FLASH_ADDR
@@ -59,6 +83,7 @@ zephyr_linker_group(NAME RAM_REGION VMA RAM LMA ROM_REGION)
 zephyr_linker_group(NAME TEXT_REGION GROUP ROM_REGION SYMBOL SECTION)
 zephyr_linker_group(NAME RODATA_REGION GROUP ROM_REGION)
 zephyr_linker_group(NAME DATA_REGION GROUP RAM_REGION SYMBOL SECTION)
+zephyr_linker_group(NAME NOINIT_REGION GROUP RAM_REGION SYMBOL SECTION)
 
 # should go to a relocation.cmake - from include/linker/rel-sections.ld - start
 zephyr_linker_section(NAME  .rel.plt  HIDDEN)
@@ -82,6 +107,8 @@ zephyr_linker_section(NAME .text         GROUP TEXT_REGION)
 zephyr_linker_section_configure(SECTION .rel.plt  INPUT ".rel.iplt")
 zephyr_linker_section_configure(SECTION .rela.plt INPUT ".rela.iplt")
 
+include(${COMMON_ZEPHYR_LINKER_DIR}/kobject-text.cmake)
+
 zephyr_linker_section_configure(SECTION .text INPUT ".TEXT.*")
 zephyr_linker_section_configure(SECTION .text INPUT ".gnu.linkonce.t.*")
 
@@ -107,9 +134,9 @@ include(${COMMON_ZEPHYR_LINKER_DIR}/thread-local-storage.cmake)
 
 zephyr_linker_section(NAME .rodata GROUP RODATA_REGION)
 zephyr_linker_section_configure(SECTION .rodata INPUT ".gnu.linkonce.r.*")
-if(CONFIG_USERSPACE AND CONFIG_XIP)
-  zephyr_linker_section_configure(SECTION .rodata INPUT ".kobject_data.rodata*")
-endif()
+
+include(${COMMON_ZEPHYR_LINKER_DIR}/kobject-rom.cmake)
+
 zephyr_linker_section_configure(SECTION .rodata ALIGN 4)
 
 # ToDo - . = ALIGN(_region_min_align);
@@ -119,13 +146,33 @@ zephyr_linker_section_configure(SECTION .rodata ALIGN 4)
 zephyr_linker_section(NAME .ramfunc GROUP RAM_REGION SUBALIGN 8)
 # Todo: handle MPU_ALIGN(_ramfunc_size);
 
-# ToDo - handle if(CONFIG_USERSPACE)
+if(CONFIG_USERSPACE)
+  # This is where the app_mem_partition stuff is going to be placed, once it
+  # is generated by gen_app_partitions.py. _app_smem has its own init-copy
+  # handling in z_data_copy, so put it in RAM_REGIOM rather than DATA_REGION
+  zephyr_linker_group(NAME APP_SMEM_GROUP GROUP RAM_REGION SYMBOL SECTION)
+  zephyr_linker_symbol(SYMBOL "_app_smem_size" EXPR "@__app_smem_group_size@")
+	zephyr_linker_symbol(SYMBOL "_app_smem_rom_start" EXPR "@__app_smem_group_load_start@")
+
+
+  zephyr_linker_section(NAME .bss VMA RAM LMA FLASH TYPE BSS)
+  zephyr_linker_section_configure(SECTION .bss INPUT COMMON)
+  zephyr_linker_section_configure(SECTION .bss INPUT ".kernel_bss.*")
+
+  #TODO: the skeletons includes <linker_sram_bss_relocate.ld> here
+
+  # As memory is cleared in words only, it is simpler to ensure the BSS
+  # section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
+  zephyr_linker_section_configure(SECTION .bss ALIGN 4)
+
+  include(${COMMON_ZEPHYR_LINKER_DIR}/common-noinit.cmake)
+endif()
 
-zephyr_linker_section(NAME .data GROUP DATA_REGION)
+zephyr_linker_section(NAME .data GROUP DATA_REGION ALIGN_WITH_INPUT)
 zephyr_linker_section_configure(SECTION .data INPUT ".kernel.*")
 
 include(${COMMON_ZEPHYR_LINKER_DIR}/common-ram.cmake)
-#include(kobject.ld)
+include(${COMMON_ZEPHYR_LINKER_DIR}/kobject-data.cmake)
 
 if(NOT CONFIG_USERSPACE)
   zephyr_linker_section(NAME .bss VMA RAM LMA FLASH TYPE BSS)
@@ -135,7 +182,7 @@ if(NOT CONFIG_USERSPACE)
   # section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
   zephyr_linker_section_configure(SECTION .bss ALIGN 4)
 
-  zephyr_linker_section(NAME .noinit GROUP RAM_REGION TYPE NOLOAD NOINIT)
+  zephyr_linker_section(NAME .noinit GROUP NOINIT_REGION TYPE NOLOAD NOINIT)
   # This section is used for non-initialized objects that
   # will not be cleared during the boot process.
   zephyr_linker_section_configure(SECTION .noinit INPUT ".kernel_noinit.*")
@@ -143,7 +190,7 @@ endif()
 
 include(${COMMON_ZEPHYR_LINKER_DIR}/ram-end.cmake)
 
-zephyr_linker_symbol(SYMBOL __ramfunc_region_start EXPR "ADDR(.ramfunc)")
+zephyr_linker_symbol(SYMBOL __ramfunc_region_start EXPR "(@__ramfunc_start@)")
 zephyr_linker_symbol(SYMBOL __kernel_ram_start EXPR "(@__bss_start@)")
 zephyr_linker_symbol(SYMBOL __kernel_ram_end  EXPR "(${RAM_ADDR} + ${RAM_SIZE})")
 zephyr_linker_symbol(SYMBOL __kernel_ram_size EXPR "(@__kernel_ram_end@ - @__bss_start@)")
diff --git a/cmake/linker_script/common/common-noinit.cmake b/cmake/linker_script/common/common-noinit.cmake
new file mode 100644
index 00000000000..78093250d23
--- /dev/null
+++ b/cmake/linker_script/common/common-noinit.cmake
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: Apache-2.0
+# The contents of this file is based on include/zephyr/linker/common-noinit.ld
+# Please keep in sync
+
+zephyr_linker_section(NAME .noinit GROUP NOINIT_REGION TYPE NOLOAD NOINIT)
+
+if(CONFIG_USERSPACE)
+  zephyr_linker_section_configure(
+    SECTION .noinit
+    INPUT ".user_stacks*"
+    SYMBOLS z_user_stacks_start z_user_stacks_end)
+
+endif()
+# TODO: #include <snippets-noinit.ld>
+include(${COMMON_ZEPHYR_LINKER_DIR}/kobject-priv-stacks.cmake)
diff --git a/cmake/linker_script/common/common-ram.cmake b/cmake/linker_script/common/common-ram.cmake
index 5d2f9d18430..d46376edd03 100644
--- a/cmake/linker_script/common/common-ram.cmake
+++ b/cmake/linker_script/common/common-ram.cmake
@@ -1,4 +1,6 @@
-# originates from common-ram.ld
+# SPDX-License-Identifier: Apache-2.0
+# The contents of this file is based on include/zephyr/linker/common-ram.ld
+# Please keep in sync
 
 if(CONFIG_GEN_SW_ISR_TABLE AND CONFIG_DYNAMIC_INTERRUPTS)
   # ld align has been changed to subalign to provide identical behavior scatter vs. ld.
@@ -10,6 +12,12 @@ if(CONFIG_GEN_SW_ISR_TABLE AND CONFIG_DYNAMIC_INTERRUPTS)
     SECTION sw_isr_table
     INPUT ".gnu.linkonce.sw_isr_table*"
   )
+  if(CONFIG_SHARED_INTERRUPTS)
+    zephyr_linker_section_configure(
+      SECTION sw_isr_table
+      INPUT ".gnu.linkonce.shared_sw_isr_table*"
+    )
+  endif()
 endif()
 
 zephyr_linker_section(NAME device_states GROUP DATA_REGION NOINPUT ${XIP_ALIGN_WITH_INPUT})
@@ -24,85 +32,89 @@ endif()
 zephyr_iterable_section(NAME log_dynamic GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
 
 if(CONFIG_USERSPACE)
+  set(K_OBJECTS_GROUP "K_OBJECTS_IN_DATA_REGION")
   # All kernel objects within are assumed to be either completely
   # initialized at build time, or initialized automatically at runtime
   # via iteration before the POST_KERNEL phase.
   #
-  # These two symbols only used by gen_kobject_list.py
-  #   _static_kernel_objects_begin = .;
-endif()
-
-zephyr_iterable_section(NAME k_timer GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-zephyr_iterable_section(NAME k_mem_slab GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-zephyr_iterable_section(NAME k_heap GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-zephyr_iterable_section(NAME k_mutex GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-zephyr_iterable_section(NAME k_stack GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-zephyr_iterable_section(NAME k_msgq GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-zephyr_iterable_section(NAME k_mbox GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-zephyr_iterable_section(NAME k_pipe GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-zephyr_iterable_section(NAME k_sem GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-zephyr_iterable_section(NAME k_event GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-zephyr_iterable_section(NAME k_queue GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-zephyr_iterable_section(NAME k_fifo GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-zephyr_iterable_section(NAME k_lifo GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-zephyr_iterable_section(NAME k_condvar GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-zephyr_iterable_section(NAME sys_mem_blocks_ptr GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-
-zephyr_iterable_section(NAME net_buf_pool GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+  zephyr_linker_group(NAME ${K_OBJECTS_GROUP} GROUP DATA_REGION SYMBOL SECTION)
+
+  # gen_kobject_list.py expects the start and end symbols to be called
+  # _static_kernel_objects_begin and _static_kernel_objects_end respectively...
+  zephyr_linker_symbol(
+    SYMBOL
+    _static_kernel_objects_begin
+    EXPR
+    "(@__k_objects_in_data_region_start@)"
+    )
+  zephyr_linker_symbol(
+    SYMBOL
+    _static_kernel_objects_end
+    EXPR
+    "(@__k_objects_in_data_region_end@)"
+    )
+else()
+  set(K_OBJECTS_GROUP "DATA_REGION")
+endif()
+
+zephyr_iterable_section(NAME k_timer GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+zephyr_iterable_section(NAME k_mem_slab GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+zephyr_iterable_section(NAME k_heap GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+zephyr_iterable_section(NAME k_mutex GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+zephyr_iterable_section(NAME k_stack GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+zephyr_iterable_section(NAME k_msgq GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+zephyr_iterable_section(NAME k_mbox GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+zephyr_iterable_section(NAME k_pipe GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+zephyr_iterable_section(NAME k_sem GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+zephyr_iterable_section(NAME k_event GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+zephyr_iterable_section(NAME k_queue GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+zephyr_iterable_section(NAME k_fifo GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+zephyr_iterable_section(NAME k_lifo GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+zephyr_iterable_section(NAME k_condvar GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+zephyr_iterable_section(NAME sys_mem_blocks_ptr GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+
+zephyr_iterable_section(NAME net_buf_pool GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
 
 if(CONFIG_NETWORKING)
-  zephyr_iterable_section(NAME net_if     GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-  zephyr_iterable_section(NAME net_if_dev GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-  zephyr_iterable_section(NAME net_l2     GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-  zephyr_iterable_section(NAME eth_bridge GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+  zephyr_iterable_section(NAME net_if     GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+  zephyr_iterable_section(NAME net_if_dev GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+  zephyr_iterable_section(NAME net_l2     GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+  zephyr_iterable_section(NAME eth_bridge GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
 endif()
 
 if(CONFIG_ARM_SCMI)
-  zephyr_iterable_section(NAME scmi_protocol GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+  zephyr_iterable_section(NAME scmi_protocol GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
 endif()
 
 if(CONFIG_SENSING)
-  zephyr_iterable_section(NAME sensing_sensor GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+  zephyr_iterable_section(NAME sensing_sensor GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
 endif()
 
 if(CONFIG_USB_DEVICE_STACK)
-  zephyr_linker_section(NAME usb_descriptor GROUP DATA_REGION NOINPUT ${XIP_ALIGN_WITH_INPUT} SUBALIGN 1)
+  zephyr_linker_section(NAME usb_descriptor GROUP ${K_OBJECTS_GROUP} NOINPUT ${XIP_ALIGN_WITH_INPUT} SUBALIGN 1)
   zephyr_linker_section_configure(SECTION usb_descriptor
     KEEP SORT NAME INPUT ".usb.descriptor*"
   )
 
-  zephyr_iterable_section(NAME usb_cfg_data GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+  zephyr_iterable_section(NAME usb_cfg_data GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
 endif()
 
 if(CONFIG_USB_DEVICE_BOS)
-  zephyr_linker_section(NAME usb_bos_desc GROUP DATA_REGION NOINPUT ${XIP_ALIGN_WITH_INPUT} SUBALIGN 1)
+  zephyr_linker_section(NAME usb_bos_desc GROUP ${K_OBJECTS_GROUP} NOINPUT ${XIP_ALIGN_WITH_INPUT} SUBALIGN 1)
   zephyr_linker_section_configure(SECTION usb_data
     KEEP SORT NAME INPUT ".usb.bos_desc"
   )
 endif()
 
 if(CONFIG_RTIO)
-  zephyr_iterable_section(NAME rtio GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-  zephyr_iterable_section(NAME rtio_iodev GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-  zephyr_iterable_section(NAME rtio_sqe_pool GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-  zephyr_iterable_section(NAME rtio_cqe_pool GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+  zephyr_iterable_section(NAME rtio GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+  zephyr_iterable_section(NAME rtio_iodev GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+  zephyr_iterable_section(NAME rtio_sqe_pool GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+  zephyr_iterable_section(NAME rtio_cqe_pool GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
 endif()
 
 if(CONFIG_SENSING)
-  zephyr_iterable_section(NAME sensing_sensor GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-endif()
-
-#if(CONFIG_USERSPACE)
-#	_static_kernel_objects_end = .;
-#endif()
-#
-
-if(CONFIG_ZTEST)
-  zephyr_iterable_section(NAME ztest_suite_node GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-  zephyr_iterable_section(NAME ztest_suite_stats GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-  zephyr_iterable_section(NAME ztest_unit_test GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-  zephyr_iterable_section(NAME ztest_test_rule GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
-  zephyr_iterable_section(NAME ztest_expected_result_entry GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+  zephyr_iterable_section(NAME sensing_sensor GROUP ${K_OBJECTS_GROUP} ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
 endif()
 
 if(CONFIG_ZBUS)
@@ -113,6 +125,9 @@ if(CONFIG_UVB)
   zephyr_iterable_section(NAME uvb_node GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
 endif()
 
+if(CONFIG_VIDEO)
+  zephyr_iterable_section(NAME video_device GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+endif()
 
 if(CONFIG_LOG)
   zephyr_iterable_section(NAME log_mpsc_pbuf GROUP DATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
diff --git a/cmake/linker_script/common/common-rom.cmake b/cmake/linker_script/common/common-rom.cmake
index 868e9f382d9..3980b1f6f23 100644
--- a/cmake/linker_script/common/common-rom.cmake
+++ b/cmake/linker_script/common/common-rom.cmake
@@ -1,4 +1,7 @@
-# originates from common-rom.ld
+# SPDX-License-Identifier: Apache-2.0
+# The contents of this file is based on include/zephyr/linker/common-rom.ld
+# and som of include/zephyr/linker/common-rom/*.ld
+# Please keep in sync
 
 zephyr_linker_section(NAME init KVMA RAM_REGION GROUP RODATA_REGION)
 zephyr_linker_section_obj_level(SECTION init LEVEL EARLY)
@@ -8,9 +11,6 @@ zephyr_linker_section_obj_level(SECTION init LEVEL POST_KERNEL)
 zephyr_linker_section_obj_level(SECTION init LEVEL APPLICATION)
 zephyr_linker_section_obj_level(SECTION init LEVEL SMP)
 
-zephyr_linker_section(NAME deferred_init_list KVMA RAM_REGION GROUP RODATA_REGION)
-zephyr_linker_section_configure(SECTION deferred_init_list INPUT ".z_deferred_init*" KEEP SORT NAME)
-
 zephyr_iterable_section(NAME device NUMERIC KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
 
 if(CONFIG_GEN_SW_ISR_TABLE AND NOT CONFIG_DYNAMIC_INTERRUPTS)
@@ -20,10 +20,16 @@ if(CONFIG_GEN_SW_ISR_TABLE AND NOT CONFIG_DYNAMIC_INTERRUPTS)
     SECTION sw_isr_table
     INPUT ".gnu.linkonce.sw_isr_table*"
   )
+  if(CONFIG_SHARED_INTERRUPTS)
+    zephyr_linker_section_configure(
+      SECTION sw_isr_table
+      INPUT ".gnu.linkonce.shared_sw_isr_table*"
+    )
+  endif()
 endif()
 
 zephyr_linker_section(NAME initlevel_error KVMA RAM_REGION GROUP RODATA_REGION NOINPUT)
-zephyr_linker_section_configure(SECTION initlevel_error INPUT ".z_init_[_A-Z0-9]*" KEEP SORT NAME)
+zephyr_linker_section_configure(SECTION initlevel_error INPUT ".z_init_*" KEEP SORT NAME)
 # How to do cross linker ?
 # ASSERT(SIZEOF(initlevel_error) == 0, "Undefined initialization levels used.")
 
@@ -69,16 +75,7 @@ endif()
 if(CONFIG_USERSPACE)
   # Build-time assignment of permissions to kernel objects to
   # threads declared with K_THREAD_DEFINE()
-  zephyr_linker_section(
-    NAME k_object_assignment_area
-    VMA FLASH NOINPUT
-    SUBALIGN 4
-  )
-  zephyr_linker_section_configure(
-    SECTION k_object_assignment
-    INPUT ".k_object_assignment.static.*"
-    KEEP SORT NAME
-  )
+  zephyr_iterable_section(NAME k_object_assignment VMA FLASH SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
 endif()
 
 zephyr_linker_section(
@@ -91,6 +88,10 @@ zephyr_linker_section_configure(
   KEEP SORT NAME
 )
 
+if(CONFIG_NETWORKING)
+  zephyr_iterable_section(NAME net_l3_register KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+endif()
+
 if(CONFIG_NET_SOCKETS)
   zephyr_iterable_section(NAME net_socket_register KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
 endif()
@@ -173,6 +174,9 @@ zephyr_iterable_section(NAME log_strings KVMA RAM_REGION GROUP RODATA_REGION SUB
 
 zephyr_iterable_section(NAME log_const KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
 
+zephyr_linker_section(NAME symbol_to_keep GROUP RODATA_REGION NOINPUT)
+zephyr_linker_section_configure(SECTION symbol_to_keep INPUT ".symbol_to_keep*" KEEP SORT NAME)
+
 zephyr_iterable_section(NAME shell KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
 
 zephyr_iterable_section(NAME shell_root_cmds KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
@@ -186,7 +190,7 @@ zephyr_iterable_section(NAME cfb_font KVMA RAM_REGION GROUP RODATA_REGION SUBALI
 zephyr_iterable_section(NAME tracing_backend KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
 
 zephyr_linker_section(NAME zephyr_dbg_info KVMA RAM_REGION GROUP RODATA_REGION NOINPUT ${XIP_ALIGN_WITH_INPUT})
-zephyr_linker_section_configure(SECTION zephyr_dbg_info INPUT ".zephyr_dbg_info" KEEP)
+zephyr_linker_section_configure(SECTION zephyr_dbg_info INPUT ".dbg_thread_info" KEEP)
 
 if(CONFIG_SYMTAB)
   zephyr_linker_section(NAME symtab KVMA FLASH GROUP RODATA_REGION SUBALIGN 4 NOINPUT)
@@ -234,6 +238,13 @@ if(CONFIG_USBD_MSC_CLASS)
   zephyr_iterable_section(NAME usbd_msc_lun KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
 endif()
 
+if(CONFIG_ZTEST)
+  zephyr_iterable_section(NAME ztest_expected_result_entry KVMA RAM_REGION GROUP RODATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+  zephyr_iterable_section(NAME ztest_suite_node KVMA RAM_REGION GROUP RODATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+  zephyr_iterable_section(NAME ztest_unit_test KVMA RAM_REGION GROUP RODATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+  zephyr_iterable_section(NAME ztest_test_rule KVMA RAM_REGION GROUP RODATA_REGION ${XIP_ALIGN_WITH_INPUT} SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
+endif()
+
 if(CONFIG_ZBUS)
   zephyr_iterable_section(NAME zbus_channel KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
   zephyr_iterable_section(NAME zbus_observer KVMA RAM_REGION GROUP RODATA_REGION SUBALIGN ${CONFIG_LINKER_ITERABLE_SUBALIGN})
diff --git a/cmake/linker_script/common/debug-sections.cmake b/cmake/linker_script/common/debug-sections.cmake
index ba6aff11c3a..55a68e1fe7a 100644
--- a/cmake/linker_script/common/debug-sections.cmake
+++ b/cmake/linker_script/common/debug-sections.cmake
@@ -1,4 +1,7 @@
-# Content of this file originates from include/zephyr/linker/debug-sections.ld
+# SPDX-License-Identifier: Apache-2.0
+# The contents of this file is based on include/zephyr/linker/debug-sections.ld
+# Please keep in sync
+
 # Following sections are obtained via 'ld --verbose'
 
 # Stabs debugging sections.
diff --git a/cmake/linker_script/common/kobject-data.cmake b/cmake/linker_script/common/kobject-data.cmake
new file mode 100644
index 00000000000..072dfe635aa
--- /dev/null
+++ b/cmake/linker_script/common/kobject-data.cmake
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: Apache-2.0
+# The contents of this file is based on include/zephyr/linker/kobject-data.ld
+# Please keep in sync
+
+if(CONFIG_USERSPACE)
+
+  zephyr_linker_section(NAME kobject_data GROUP ${K_OBJECTS_GROUP} ALIGN_WITH_INPUT NOINPUT)
+
+  zephyr_linker_section_configure(
+    SECTION kobject_data
+    SYMBOLS z_kobject_data_begin
+    )
+
+  if(CONFIG_DYNAMIC_OBJECTS)
+    # generated by gperf, this avoids errors for the first build.
+    # Also, we dont have KOBJECT_DATA_SZ for the first build
+    zephyr_linker_section_configure(
+      SECTION kobject_data
+      SYMBOLS _thread_idx_map
+      MIN_SIZE ${CONFIG_MAX_THREAD_BYTES}
+      PASS NOT LINKER_ZEPHYR_PREBUILT LINKER_ZEPHYR_FINAL
+      )
+    zephyr_linker_section_configure(
+      SECTION kobject_data
+      SYMBOLS _kobject_data_area_start _kobject_data_area_end
+      PASS NOT LINKER_ZEPHYR_PREBUILT LINKER_ZEPHYR_FINAL
+      )
+  endif()
+
+  # During LINKER_KOBJECT_PREBUILT and LINKER_ZEPHYR_PREBUILT,
+  # space needs to be reserved for the rodata that will be
+  # produced by gperf during the final stages of linking.
+  # The alignment and size are produced by
+  # scripts/build/gen_kobject_placeholders.py. These are here
+  # so the addresses to kobjects would remain the same
+  # during the final stages of linking (LINKER_ZEPHYR_FINAL).
+  if(CONFIG_DYNAMIC_OBJECTS)
+    # in LINKER_ZEPHYR_PREBUILT there is no object file defining _thread_idx_map
+    # so we must have a synthetic one. Note that the size is not set here,
+    # since the space is provided in the section below:
+    zephyr_linker_section_configure(
+      SECTION kobject_data
+      SYMBOLS _thread_idx_map
+      PASS LINKER_ZEPHYR_PREBUILT
+      )
+  endif()
+
+  zephyr_linker_section_configure(
+    SECTION kobject_data
+    INPUT
+    ".kobject_data.data*"
+    ".kobject_data.sdata*"
+    PASS LINKER_ZEPHYR_PREBUILT LINKER_ZEPHYR_FINAL
+    ALIGN @KOBJECT_DATA_ALIGN,undef:4@
+    MIN_SIZE @KOBJECT_DATA_SZ@
+    MAX_SIZE @KOBJECT_DATA_SZ@
+    SYMBOLS _kobject_data_area_start _kobject_data_area_end
+    )
+endif()
diff --git a/cmake/linker_script/common/kobject-priv-stacks.cmake b/cmake/linker_script/common/kobject-priv-stacks.cmake
new file mode 100644
index 00000000000..bfbf7edb5f5
--- /dev/null
+++ b/cmake/linker_script/common/kobject-priv-stacks.cmake
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: Apache-2.0
+# The contents of this file is based on include/zephyr/linker/kobject-priv-stacks.ld
+# Please keep in sync
+
+if(CONFIG_USERSPACE)
+  if(CONFIG_GEN_PRIV_STACKS)
+    # Padding is needed to preserve kobject addresses
+    # if we have reserved more space than needed.
+    zephyr_linker_section(NAME .priv_stacks_noinit GROUP NOINIT_REGION NOINPUT NOINIT
+                MIN_SIZE @KOBJECT_PRIV_STACKS_SZ,undef:0@ MAX_SIZE @KOBJECT_PRIV_STACKS_SZ,undef:0@)
+
+    zephyr_linker_section_configure(
+      SECTION .priv_stacks_noinit
+      SYMBOLS z_priv_stacks_ram_start
+    )
+
+    # During LINKER_KOBJECT_PREBUILT and LINKER_ZEPHYR_PREBUILT,
+    # space needs to be reserved for the rodata that will be
+    # produced by gperf during the final stages of linking.
+    # The alignment and size are produced by
+    # scripts/build/gen_kobject_placeholders.py. These are here
+    # so the addresses to kobjects would remain the same
+    # during the final stages of linking (LINKER_ZEPHYR_FINAL).
+    zephyr_linker_section_configure(
+      SECTION .priv_stacks_noinit
+      ALIGN @KOBJECT_PRIV_STACKS_ALIGN,undef:0@
+      INPUT ".priv_stacks.noinit"
+      KEEP
+      PASS LINKER_ZEPHYR_PREBUILT LINKER_ZEPHYR_FINAL
+      SYMBOLS z_priv_stacks_ram_aligned_start z_priv_stacks_ram_end
+    )
+
+    if(KOBJECT_PRIV_STACKS_ALIGN)
+      zephyr_linker_symbol(
+        SYMBOL z_priv_stacks_ram_used
+        EXPR "(@z_priv_stacks_ram_end@ - @z_priv_stacks_ram_start@)"
+        PASS LINKER_ZEPHYR_FINAL
+      )
+    endif()
+  endif()
+endif()
diff --git a/cmake/linker_script/common/kobject-rom.cmake b/cmake/linker_script/common/kobject-rom.cmake
new file mode 100644
index 00000000000..81360c1edba
--- /dev/null
+++ b/cmake/linker_script/common/kobject-rom.cmake
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: Apache-2.0
+# The contents of this file is based on include/zephyr/linker/kobject-rom.ld
+# Please keep in sync
+
+# During LINKER_KOBJECT_PREBUILT and LINKER_ZEPHYR_PREBUILT,
+# space needs to be reserved for the rodata that will be
+# produced by gperf during the final stages of linking.
+# The alignment and size are produced by
+# scripts/build/gen_kobject_placeholders.py. These are here
+# so the addresses to kobjects would remain the same
+# during the final stages of linking (LINKER_ZEPHYR_FINAL).
+
+if(CONFIG_USERSPACE)
+  # By the magic of MIN_SIZE the space will be there
+  zephyr_linker_section_configure(SECTION .rodata KEEP INPUT ".kobject_data.rodata*"
+    MIN_SIZE @KOBJECT_RODATA_SZ@
+    ALIGN @KOBJECT_RODATA_ALIGN@
+    PASS LINKER_ZEPHYR_PREBUILT LINKER_ZEPHYR_FINAL
+  )
+endif()
diff --git a/cmake/linker_script/common/kobject-text.cmake b/cmake/linker_script/common/kobject-text.cmake
new file mode 100644
index 00000000000..9fdf08b478f
--- /dev/null
+++ b/cmake/linker_script/common/kobject-text.cmake
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: Apache-2.0
+# The contents of this file is based on include/zephyr/linker/kobject-text.ld
+# Please keep in sync
+
+if(CONFIG_USERSPACE)
+  zephyr_linker_section(NAME _kobject_text_area
+                        GROUP TEXT_REGION NOINPUT)
+
+  zephyr_linker_section_configure(
+    SECTION
+    _kobject_text_area
+    INPUT
+    ".kobject_data.literal*"
+    ".kobject_data.text*"
+    MIN_SIZE ${CONFIG_KOBJECT_TEXT_AREA}
+    MAX_SIZE ${CONFIG_KOBJECT_TEXT_AREA}
+    SYMBOLS
+    _kobject_text_area_start
+    _kobject_text_area_end
+    )
+  zephyr_linker_symbol(
+    SYMBOL
+    _kobject_text_area_used
+    EXPR
+    "(@_kobject_text_area_end@ - @_kobject_text_area_start@)"
+    )
+
+  if(CONFIG_DYNAMIC_OBJECTS)
+    zephyr_linker_section_configure(
+      SECTION
+      _kobject_text_area
+      SYMBOLS
+      z_object_gperf_find
+      z_object_gperf_wordlist_foreach
+      PASS NOT LINKER_ZEPHYR_FINAL
+      )
+  else()
+    zephyr_linker_section_configure(
+      SECTION
+      _kobject_text_area
+      SYMBOLS
+      k_object_find
+      k_object_wordlist_foreach
+      PASS NOT LINKER_ZEPHYR_FINAL
+      )
+  endif()
+
+endif()
\ No newline at end of file
diff --git a/cmake/linker_script/common/thread-local-storage.cmake b/cmake/linker_script/common/thread-local-storage.cmake
index 229fc0900d1..6eb8dd417af 100644
--- a/cmake/linker_script/common/thread-local-storage.cmake
+++ b/cmake/linker_script/common/thread-local-storage.cmake
@@ -1,4 +1,5 @@
-# originates from thread-local-storage.ld
+# The contents of this file is based on include/zephyr/linker/thread-local-storage.ld
+# Please keep in sync
 
 if(CONFIG_THREAD_LOCAL_STORAGE)
   zephyr_linker_section(NAME .tdata LMA FLASH NOINPUT)
diff --git a/cmake/llext-edk.cmake b/cmake/llext-edk.cmake
index e78498c7845..1475931968d 100644
--- a/cmake/llext-edk.cmake
+++ b/cmake/llext-edk.cmake
@@ -11,32 +11,26 @@
 # directories (build/zephyr, zephyr base, west top dir and application source
 # dir), to avoid leaking any information about the host system.
 #
-# The following arguments are expected:
-# - llext_edk_name: Name of the extension, used to name the tarball and the
-#   install directory variable for Makefile.
-# - INTERFACE_INCLUDE_DIRECTORIES: List of include directories to copy headers
-#   from. It should simply be the INTERFACE_INCLUDE_DIRECTORIES property of the
-#   zephyr_interface target.
-# - llext_edk_file: Output file name for the tarball.
-# - llext_edk_cflags: Flags to be used for source compile commands.
-# - ZEPHYR_BASE: Path to the zephyr base directory.
-# - WEST_TOPDIR: Path to the west top directory.
-# - APPLICATION_SOURCE_DIR: Path to the application source directory.
-# - PROJECT_BINARY_DIR: Path to the project binary build directory.
-# - CONFIG_LLEXT_EDK_USERSPACE_ONLY: Whether to copy syscall headers from the
-#   edk directory. This is necessary when building an extension that only
-#   supports userspace, as the syscall headers are regenerated in the edk
-#   directory.
+# The script expects a build_info.yml file in the project binary directory.
+# This file should contain the following entries:
+#  - cmake application source-dir
+#  - cmake board name
+#  - cmake board qualifiers
+#  - cmake board revision
+#  - cmake llext-edk cflags
+#  - cmake llext-edk file
+#  - cmake llext-edk include-dirs
+#  - west topdir
 
 cmake_minimum_required(VERSION 3.20.0)
 
-if (CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID)
-  message(FATAL_ERROR
-    "The LLEXT EDK is not compatible with CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID.")
-endif()
+# initialize the same paths as the main CMakeLists.txt for consistency
+set(PROJECT_BINARY_DIR ${CMAKE_BINARY_DIR})
+set(ZEPHYR_BASE ${CMAKE_CURRENT_LIST_DIR}/../)
+list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_LIST_DIR}/modules")
 
-set(llext_edk ${PROJECT_BINARY_DIR}/${llext_edk_name})
-set(llext_edk_inc ${llext_edk}/include)
+include(extensions)
+include(yaml)
 
 # Usage:
 #   relative_dir(<dir> <relative_out> <bindir_out>)
@@ -89,28 +83,123 @@ function(relative_dir dir relative_out bindir_out)
     endif()
 endfunction()
 
-string(REGEX REPLACE "[^a-zA-Z0-9]" "_" llext_edk_name_sane ${llext_edk_name})
-string(TOUPPER ${llext_edk_name_sane} llext_edk_name_sane)
-set(install_dir_var "${llext_edk_name_sane}_INSTALL_DIR")
+# Usage:
+#   edk_escape(<target> <str_in> <str_out>)
+#
+# Escape problematic characters in the string <str_in> and store the result in
+# <str_out>. The escaping is done to make the string suitable for <target>.
+function(edk_escape target str_in str_out)
+    string(REPLACE "\\" "\\\\" str_escaped "${str_in}")
+    string(REPLACE "\"" "\\\"" str_escaped "${str_escaped}")
+    set(${str_out} "${str_escaped}" PARENT_SCOPE)
+endfunction()
+
+# Usage:
+#   edk_write_header(<target>)
+#
+# Initialize the file associated with <target> and write its header.
+function(edk_write_header target)
+    file(WRITE ${edk_file_${target}} "")
+endfunction()
+
+# Usage:
+#   edk_write_comment(<target> <text>)
+#
+# Write to the file associated with <target> the string <text> as a comment.
+function(edk_write_comment target text)
+    file(APPEND ${edk_file_${target}} "\n# ${text}\n")
+endfunction()
+
+# Usage:
+#   edk_write_var(<target> <var_name> <var_value>)
+#
+# Write to the file associated with <target> an entry where <var_name> is
+# assigned the value <var_value>.
+function(edk_write_var target var_name var_value)
+    if(target STREQUAL "CMAKE")
+        # CMake: export assignments of the form:
+        #
+        #   set(var "value1;value2;...")
+        #
+        set(DASHIMACROS "-imacros\${CMAKE_CURRENT_LIST_DIR}/")
+        set(DASHI "-I\${CMAKE_CURRENT_LIST_DIR}/")
+        edk_escape(${target} "${var_value}" var_value)
+        string(CONFIGURE "${var_value}" exp_var_value @ONLY)
+        # The list is otherwise exported verbatim, surrounded by quotes.
+        file(APPEND ${edk_file_${target}} "set(${var_name} \"${exp_var_value}\")\n")
+    elseif(target STREQUAL "MAKEFILE")
+        # Makefile: export assignments of the form:
+        #
+        #   var = "value1" "value2" ...
+        #
+        set(DASHIMACROS "-imacros\$(${install_dir_var})/")
+        set(DASHI "-I\$(${install_dir_var})/")
+        edk_escape(${target} "${var_value}" var_value)
+        string(CONFIGURE "${var_value}" exp_var_value @ONLY)
+        # Each element of the list is wrapped in quotes and is separated by a space.
+        list(JOIN exp_var_value "\" \"" exp_var_value_str)
+        file(APPEND ${edk_file_${target}} "${var_name} = \"${exp_var_value_str}\"\n")
+    endif()
+endfunction()
+
 
-separate_arguments(llext_edk_cflags NATIVE_COMMAND ${llext_edk_cflags})
+
+# read in computed build configuration
+import_kconfig(CONFIG ${PROJECT_BINARY_DIR}/.config)
+
+if (CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID)
+  message(FATAL_ERROR
+    "The LLEXT EDK is not compatible with CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID.")
+endif()
+
+set(build_info_file ${PROJECT_BINARY_DIR}/../build_info.yml)
+yaml_load(FILE ${build_info_file} NAME build_info)
+
+yaml_get(llext_edk_cflags NAME build_info KEY cmake llext-edk cflags)
+yaml_get(llext_edk_file NAME build_info KEY cmake llext-edk file)
+yaml_get(INTERFACE_INCLUDE_DIRECTORIES NAME build_info KEY cmake llext-edk include-dirs)
+yaml_get(APPLICATION_SOURCE_DIR NAME build_info KEY cmake application source-dir)
+yaml_get(WEST_TOPDIR NAME build_info KEY west topdir)
+
+yaml_get(board_name NAME build_info KEY cmake board name)
+yaml_get(board_qualifiers NAME build_info KEY cmake board qualifiers)
+yaml_get(board_revision NAME build_info KEY cmake board revision)
+zephyr_build_string(normalized_board_target
+    BOARD ${board_name}
+    BOARD_QUALIFIERS ${board_qualifiers})
+
+set(llext_edk_name ${CONFIG_LLEXT_EDK_NAME})
+set(llext_edk ${PROJECT_BINARY_DIR}/${llext_edk_name})
+set(llext_edk_inc ${llext_edk}/include)
+
+zephyr_string(SANITIZE TOUPPER var_prefix ${llext_edk_name})
+set(install_dir_var "${var_prefix}_INSTALL_DIR")
 
 set(make_relative FALSE)
 foreach(flag ${llext_edk_cflags})
-    if (flag STREQUAL "-imacros")
+    # Detect all combinations of 'imacros' flag:
+    # - with one or two preceding dashes
+    # - separated from the argument, joined by '=', or joined (no separator)
+    if(flag MATCHES "^--?imacros$")
+        # imacros followed by a space, convert next argument
         set(make_relative TRUE)
-    elseif (make_relative)
+        continue()
+    elseif(flag MATCHES "^--?imacros=?([^=].*)$")
+        # imacros=<stuff> or imacros<stuff>, immediately convert <stuff>
+        set(flag ${CMAKE_MATCH_1})
+        set(make_relative TRUE)
+    endif()
+
+    if(make_relative)
         set(make_relative FALSE)
         cmake_path(GET flag PARENT_PATH parent)
         cmake_path(GET flag FILENAME name)
         relative_dir(${parent} dest bindir)
         cmake_path(RELATIVE_PATH dest BASE_DIRECTORY ${llext_edk} OUTPUT_VARIABLE dest_rel)
         if(bindir)
-            list(APPEND imacros_gen_make "-imacros\$(${install_dir_var})/${dest_rel}/${name}")
-            list(APPEND imacros_gen_cmake "-imacros\${CMAKE_CURRENT_LIST_DIR}/${dest_rel}/${name}")
+            list(APPEND imacros_gen "@DASHIMACROS@${dest_rel}/${name}")
         else()
-            list(APPEND imacros_make "-imacros\$(${install_dir_var})/${dest_rel}/${name}")
-            list(APPEND imacros_cmake "-imacros\${CMAKE_CURRENT_LIST_DIR}/${dest_rel}/${name}")
+            list(APPEND imacros "@DASHIMACROS@${dest_rel}/${name}")
         endif()
     else()
         list(APPEND new_cflags ${flag})
@@ -118,12 +207,10 @@ foreach(flag ${llext_edk_cflags})
 endforeach()
 set(llext_edk_cflags ${new_cflags})
 
-list(APPEND base_flags_make ${llext_edk_cflags} ${imacros_make})
-list(APPEND base_flags_cmake ${llext_edk_cflags} ${imacros_cmake})
+list(APPEND base_flags ${llext_edk_cflags} ${imacros})
 
-separate_arguments(include_dirs NATIVE_COMMAND ${INTERFACE_INCLUDE_DIRECTORIES})
 file(MAKE_DIRECTORY ${llext_edk_inc})
-foreach(dir ${include_dirs})
+foreach(dir ${INTERFACE_INCLUDE_DIRECTORIES})
     if (NOT EXISTS ${dir})
         continue()
     endif()
@@ -137,61 +224,61 @@ foreach(dir ${include_dirs})
 
     cmake_path(RELATIVE_PATH dest BASE_DIRECTORY ${llext_edk} OUTPUT_VARIABLE dest_rel)
     if(bindir)
-        list(APPEND inc_gen_flags_make "-I\$(${install_dir_var})/${dest_rel}")
-        list(APPEND inc_gen_flags_cmake "-I\${CMAKE_CURRENT_LIST_DIR}/${dest_rel}")
+        list(APPEND gen_inc_flags "@DASHI@${dest_rel}")
     else()
-        list(APPEND inc_flags_make "-I\$(${install_dir_var})/${dest_rel}")
-        list(APPEND inc_flags_cmake "-I\${CMAKE_CURRENT_LIST_DIR}/${dest_rel}")
+        list(APPEND inc_flags "@DASHI@${dest_rel}")
     endif()
-    list(APPEND all_inc_flags_make "-I\$(${install_dir_var})/${dest_rel}")
-    list(APPEND all_inc_flags_cmake "-I\${CMAKE_CURRENT_LIST_DIR}/${dest_rel}")
+    list(APPEND all_inc_flags "@DASHI@${dest_rel}")
 endforeach()
 
+list(APPEND all_flags ${base_flags} ${imacros_gen} ${all_inc_flags})
+
 if(CONFIG_LLEXT_EDK_USERSPACE_ONLY)
     # Copy syscall headers from edk directory, as they were regenerated there.
     file(COPY ${PROJECT_BINARY_DIR}/edk/include/generated/ DESTINATION ${llext_edk_inc}/zephyr/include/generated)
 endif()
 
-# Generate flags for Makefile
-list(APPEND all_flags_make ${base_flags_make} ${imacros_gen_make} ${all_inc_flags_make})
-list(JOIN all_flags_make " " all_flags_str)
-file(WRITE ${llext_edk}/Makefile.cflags "LLEXT_CFLAGS = ${all_flags_str}")
-
-list(JOIN all_inc_flags_make " " all_inc_flags_str)
-file(APPEND ${llext_edk}/Makefile.cflags "\n\nLLEXT_ALL_INCLUDE_CFLAGS = ${all_inc_flags_str}")
-
-list(JOIN inc_flags_make " " inc_flags_str)
-file(APPEND ${llext_edk}/Makefile.cflags "\n\nLLEXT_INCLUDE_CFLAGS = ${inc_flags_str}")
-
-list(JOIN inc_gen_flags_make " " inc_gen_flags_str)
-file(APPEND ${llext_edk}/Makefile.cflags "\n\nLLEXT_GENERATED_INCLUDE_CFLAGS = ${inc_gen_flags_str}")
-
-list(JOIN base_flags_make " " base_flags_str)
-file(APPEND ${llext_edk}/Makefile.cflags "\n\nLLEXT_BASE_CFLAGS = ${base_flags_str}")
-
-list(JOIN imacros_gen_make " " imacros_gen_str)
-file(APPEND ${llext_edk}/Makefile.cflags "\n\nLLEXT_GENERATED_IMACROS_CFLAGS = ${imacros_gen_str}")
-
-# Generate flags for CMake
-list(APPEND all_flags_cmake ${base_flags_cmake} ${imacros_gen_cmake} ${all_inc_flags_cmake})
-file(WRITE ${llext_edk}/cmake.cflags "set(LLEXT_CFLAGS ${all_flags_cmake})")
+#
+# Generate the EDK flags files
+#
 
-file(APPEND ${llext_edk}/cmake.cflags "\n\nset(LLEXT_ALL_INCLUDE_CFLAGS ${all_inc_flags_cmake})")
+set(edk_targets MAKEFILE CMAKE)
+set(edk_file_MAKEFILE ${llext_edk}/Makefile.cflags)
+set(edk_file_CMAKE ${llext_edk}/cmake.cflags)
 
-file(APPEND ${llext_edk}/cmake.cflags "\n\nset(LLEXT_INCLUDE_CFLAGS ${inc_flags_cmake})")
+foreach(target ${edk_targets})
+    edk_write_header(${target})
 
-file(APPEND ${llext_edk}/cmake.cflags "\n\nset(LLEXT_GENERATED_INCLUDE_CFLAGS ${inc_gen_flags_cmake})")
+    edk_write_comment(${target} "Target information")
+    edk_write_var(${target} "${var_prefix}_BOARD_NAME" "${board_name}")
+    edk_write_var(${target} "${var_prefix}_BOARD_QUALIFIERS" "${board_qualifiers}")
+    edk_write_var(${target} "${var_prefix}_BOARD_REVISION" "${board_revision}")
+    edk_write_var(${target} "${var_prefix}_BOARD_TARGET" "${normalized_board_target}")
 
-file(APPEND ${llext_edk}/cmake.cflags "\n\nset(LLEXT_BASE_CFLAGS ${base_flags_cmake})")
+    edk_write_comment(${target} "Compile flags")
+    edk_write_var(${target} "LLEXT_CFLAGS" "${all_flags}")
+    edk_write_var(${target} "LLEXT_ALL_INCLUDE_CFLAGS" "${all_inc_flags}")
+    edk_write_var(${target} "LLEXT_INCLUDE_CFLAGS" "${inc_flags}")
+    edk_write_var(${target} "LLEXT_GENERATED_INCLUDE_CFLAGS" "${gen_inc_flags}")
+    edk_write_var(${target} "LLEXT_BASE_CFLAGS" "${base_flags}")
+    edk_write_var(${target} "LLEXT_GENERATED_IMACROS_CFLAGS" "${imacros_gen}")
+endforeach()
 
-file(APPEND ${llext_edk}/cmake.cflags "\n\nset(LLEXT_GENERATED_IMACROS_CFLAGS ${imacros_gen_cmake})")
+if(CONFIG_LLEXT_EDK_FORMAT_TAR_XZ)
+  set(llext_edk_format FORMAT gnutar COMPRESSION XZ)
+elseif(CONFIG_LLEXT_EDK_FORMAT_TAR_ZSTD)
+  set(llext_edk_format FORMAT gnutar COMPRESSION Zstd)
+elseif(CONFIG_LLEXT_EDK_FORMAT_ZIP)
+  set(llext_edk_format FORMAT zip)
+else()
+  message(FATAL_ERROR "Unsupported LLEXT_EDK_FORMAT choice")
+endif()
 
 # Generate the tarball
 file(ARCHIVE_CREATE
     OUTPUT ${llext_edk_file}
     PATHS ${llext_edk}
-    FORMAT gnutar
-    COMPRESSION XZ
+    ${llext_edk_format}
 )
 
 file(REMOVE_RECURSE ${llext_edk})
diff --git a/cmake/mcuboot.cmake b/cmake/mcuboot.cmake
index 99f6af9e239..d2fcf68e889 100644
--- a/cmake/mcuboot.cmake
+++ b/cmake/mcuboot.cmake
@@ -19,6 +19,8 @@ endfunction()
 function(zephyr_mcuboot_tasks)
   set(keyfile "${CONFIG_MCUBOOT_SIGNATURE_KEY_FILE}")
   set(keyfile_enc "${CONFIG_MCUBOOT_ENCRYPTION_KEY_FILE}")
+  string(CONFIGURE "${keyfile}" keyfile)
+  string(CONFIGURE "${keyfile_enc}" keyfile_enc)
 
   if(NOT "${CONFIG_MCUBOOT_GENERATE_UNSIGNED_IMAGE}")
     # Check for misconfiguration.
@@ -29,28 +31,50 @@ function(zephyr_mcuboot_tasks)
                       "CONFIG_MCUBOOT_SIGNATURE_KEY_FILE are set, the generated build will not be "
                       "bootable by MCUboot unless it is signed manually/externally.")
       return()
+    elseif(NOT (CONFIG_BUILD_OUTPUT_BIN OR CONFIG_BUILD_OUTPUT_HEX))
+      message(FATAL_ERROR "Can't sign images for MCUboot: Neither "
+                          "CONFIG_BUILD_OUTPUT_BIN nor CONFIG_BUILD_OUTPUT_HEX "
+                          "is enabled, so there's nothing to sign.")
     endif()
-  endif()
 
-  if(NOT WEST)
-    # This feature requires west.
-    message(FATAL_ERROR "Can't sign images for MCUboot: west not found. To fix, install west and ensure it's on PATH.")
-  endif()
+    foreach(file keyfile keyfile_enc)
+      if("${${file}}" STREQUAL "")
+        continue()
+      endif()
 
-  foreach(file keyfile keyfile_enc)
-    if(NOT "${${file}}" STREQUAL "")
+      # Find the key files in the order of preference for a simple search
+      # modeled by the if checks across the various locations
+      #
+      #  1. absolute
+      #  2. application config
+      #  3. west topdir (optional when the workspace is not west managed)
+      #
       if(NOT IS_ABSOLUTE "${${file}}")
-        # Relative paths are relative to 'west topdir'.
-        set(${file} "${WEST_TOPDIR}/${${file}}")
+        if(EXISTS "${APPLICATION_CONFIG_DIR}/${${file}}")
+          set(${file} "${APPLICATION_CONFIG_DIR}/${${file}}")
+        else()
+          # Relative paths are relative to 'west topdir'.
+          #
+          # This is the only file that has a relative check to topdir likely
+          # from the historical callouts to "west" itself before using
+          # imgtool. So, this is maintained here for backward compatibility
+          #
+          if(NOT WEST OR NOT WEST_TOPDIR)
+            message(FATAL_ERROR "Can't sign images for MCUboot: west workspace undefined. "
+                                "To fix, ensure `west topdir` is a valid workspace directory.")
+          endif()
+          set(${file} "${WEST_TOPDIR}/${${file}}")
+        endif()
       endif()
 
-      if(NOT EXISTS "${${file}}" AND NOT "${CONFIG_MCUBOOT_GENERATE_UNSIGNED_IMAGE}")
-        message(FATAL_ERROR "west sign can't find file ${${file}} (Note: Relative paths are relative to the west workspace topdir \"${WEST_TOPDIR}\")")
-      elseif(NOT (CONFIG_BUILD_OUTPUT_BIN OR CONFIG_BUILD_OUTPUT_HEX))
-        message(FATAL_ERROR "Can't sign images for MCUboot: Neither CONFIG_BUILD_OUTPUT_BIN nor CONFIG_BUILD_OUTPUT_HEX is enabled, so there's nothing to sign.")
+      if(NOT EXISTS "${${file}}")
+        message(FATAL_ERROR "Can't sign images for MCUboot: can't find file ${${file}} "
+                            "(Note: Relative paths are searched through "
+                            "APPLICATION_CONFIG_DIR=\"${APPLICATION_CONFIG_DIR}\" "
+                            "and WEST_TOPDIR=\"${WEST_TOPDIR}\")")
       endif()
-    endif()
-  endforeach()
+    endforeach()
+  endif()
 
   # No imgtool, no signed binaries.
   if(NOT DEFINED IMGTOOL)
@@ -71,7 +95,8 @@ function(zephyr_mcuboot_tasks)
 
   # If single slot mode, or if in firmware updater mode and this is the firmware updater image,
   # use slot 0 information
-  if(NOT CONFIG_MCUBOOT_BOOTLOADER_MODE_SINGLE_APP AND (NOT CONFIG_MCUBOOT_BOOTLOADER_MODE_FIRMWARE_UPDATER OR CONFIG_MCUBOOT_APPLICATION_FIRMWARE_UPDATER))
+  if(NOT CONFIG_MCUBOOT_BOOTLOADER_MODE_SINGLE_APP AND (NOT CONFIG_MCUBOOT_BOOTLOADER_MODE_FIRMWARE_UPDATER OR CONFIG_MCUBOOT_APPLICATION_FIRMWARE_UPDATER)
+      AND NOT CONFIG_MCUBOOT_BOOTLOADER_MODE_SINGLE_APP_RAM_LOAD)
     # Slot 1 size is used instead of slot 0 size
     set(slot_size)
     dt_nodelabel(slot1_flash NODELABEL "slot1_partition" REQUIRED)
@@ -114,6 +139,15 @@ function(zephyr_mcuboot_tasks)
     set(imgtool_args --align 1 --load-addr ${chosen_ram_address} ${imgtool_args})
     set(imgtool_args_alt_slot ${imgtool_args} --hex-addr ${slot1_partition_address})
     set(imgtool_args ${imgtool_args} --hex-addr ${slot0_partition_address})
+  elseif(CONFIG_MCUBOOT_BOOTLOADER_MODE_SINGLE_APP_RAM_LOAD)
+    dt_chosen(ram_load_dev PROPERTY "mcuboot,ram-load-dev")
+    if(DEFINED ram_load_dev)
+      dt_reg_addr(load_address PATH ${ram_load_dev})
+    else()
+      dt_chosen(chosen_ram PROPERTY "zephyr,sram")
+      dt_reg_addr(load_address PATH ${chosen_ram})
+    endif()
+    set(imgtool_args --align 1 --load-addr ${load_address} ${imgtool_args})
   else()
     set(imgtool_args --align ${write_block_size} ${imgtool_args})
   endif()
@@ -136,6 +170,7 @@ function(zephyr_mcuboot_tasks)
 
     if(CONFIG_MCUBOOT_GENERATE_CONFIRMED_IMAGE)
       list(APPEND byproducts ${output}.signed.confirmed.bin)
+      zephyr_runner_file(bin ${output}.signed.confirmed.bin)
       set(BYPRODUCT_KERNEL_SIGNED_CONFIRMED_BIN_NAME "${output}.signed.confirmed.bin"
           CACHE FILEPATH "Signed and confirmed kernel bin file" FORCE
       )
@@ -183,11 +218,22 @@ function(zephyr_mcuboot_tasks)
     set(BYPRODUCT_KERNEL_SIGNED_HEX_NAME "${output}.signed.hex"
         CACHE FILEPATH "Signed kernel hex file" FORCE
     )
-    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND
-                 ${imgtool_sign} ${imgtool_args} ${output}.hex ${output}.signed.hex)
+
+    if(NOT "${keyfile_enc}" STREQUAL "")
+      # When encryption is enabled, set the encrypted bit when signing the image but do not
+      # encrypt the data, this means that when the image is moved out of the primary into the
+      # secondary, it will be encrypted rather than being in unencrypted
+      set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND
+                   ${imgtool_sign} ${imgtool_args} --encrypt "${keyfile_enc}" --clear
+                   ${output}.hex ${output}.signed.hex)
+    else()
+      set_property(GLOBAL APPEND PROPERTY extra_post_build_commands COMMAND
+                   ${imgtool_sign} ${imgtool_args} ${output}.hex ${output}.signed.hex)
+    endif()
 
     if(CONFIG_MCUBOOT_GENERATE_CONFIRMED_IMAGE)
       list(APPEND byproducts ${output}.signed.confirmed.hex)
+      zephyr_runner_file(hex ${output}.signed.confirmed.hex)
       set(BYPRODUCT_KERNEL_SIGNED_CONFIRMED_HEX_NAME "${output}.signed.confirmed.hex"
           CACHE FILEPATH "Signed and confirmed kernel hex file" FORCE
       )
diff --git a/cmake/modules/FindDeprecated.cmake b/cmake/modules/FindDeprecated.cmake
index df0b6a3df51..23357760034 100644
--- a/cmake/modules/FindDeprecated.cmake
+++ b/cmake/modules/FindDeprecated.cmake
@@ -37,68 +37,6 @@ if("${Deprecated_FIND_COMPONENTS}" STREQUAL "")
   message(WARNING "find_package(Deprecated) missing required COMPONENTS keyword")
 endif()
 
-if("CROSS_COMPILE" IN_LIST Deprecated_FIND_COMPONENTS)
-  list(REMOVE_ITEM Deprecated_FIND_COMPONENTS CROSS_COMPILE)
-  # This code was deprecated after Zephyr v3.1.0
-  if(NOT DEFINED ZEPHYR_TOOLCHAIN_VARIANT)
-    set(ZEPHYR_TOOLCHAIN_VARIANT $ENV{ZEPHYR_TOOLCHAIN_VARIANT})
-  endif()
-
-  if(NOT ZEPHYR_TOOLCHAIN_VARIANT AND
-     (CROSS_COMPILE OR (DEFINED ENV{CROSS_COMPILE})))
-      set(ZEPHYR_TOOLCHAIN_VARIANT cross-compile CACHE STRING "Zephyr toolchain variant" FORCE)
-      message(DEPRECATION  "Setting CROSS_COMPILE without setting ZEPHYR_TOOLCHAIN_VARIANT is deprecated."
-                           "Please set ZEPHYR_TOOLCHAIN_VARIANT to 'cross-compile'"
-      )
-  endif()
-endif()
-
-if("XTOOLS" IN_LIST Deprecated_FIND_COMPONENTS)
-  list(REMOVE_ITEM Deprecated_FIND_COMPONENTS XTOOLS)
-  # This code was deprecated after Zephyr v3.3.0
-  # When removing support for `xtools`, remember to also remove:
-  # cmake/toolchain/xtools (folder with files)
-  # doc/develop/toolchains/crosstool_ng.rst and update the index.rst file.
-  message(DEPRECATION "XTOOLS toolchain variant is deprecated. "
-                      "Please set ZEPHYR_TOOLCHAIN_VARIANT to 'zephyr'")
-endif()
-
-if("SPARSE" IN_LIST Deprecated_FIND_COMPONENTS)
-  list(REMOVE_ITEM Deprecated_FIND_COMPONENTS SPARSE)
-  # This code was deprecated after Zephyr v3.2.0
-  if(SPARSE)
-    message(DEPRECATION
-        "Setting SPARSE='${SPARSE}' is deprecated. "
-        "Please set ZEPHYR_SCA_VARIANT to 'sparse'"
-    )
-    if("${SPARSE}" STREQUAL "y")
-      set_ifndef(ZEPHYR_SCA_VARIANT sparse)
-    endif()
-  endif()
-endif()
-
-if("SOURCES" IN_LIST Deprecated_FIND_COMPONENTS)
-  list(REMOVE_ITEM Deprecated_FIND_COMPONENTS SOURCES)
-  if(SOURCES)
-    message(DEPRECATION
-        "Setting SOURCES prior to calling find_package() for unit tests is deprecated."
-        " To add sources after find_package() use:\n"
-        "    target_sources(testbinary PRIVATE <source-file.c>)")
-  endif()
-endif()
-
-if("PYTHON_PREFER" IN_LIST Deprecated_FIND_COMPONENTS)
-  # This code was deprecated after Zephyr v3.4.0
-  list(REMOVE_ITEM Deprecated_FIND_COMPONENTS PYTHON_PREFER)
-  if(DEFINED PYTHON_PREFER)
-    message(DEPRECATION "'PYTHON_PREFER' variable is deprecated. Please use "
-                        "Python3_EXECUTABLE instead.")
-    if(NOT DEFINED Python3_EXECUTABLE)
-      set(Python3_EXECUTABLE ${PYTHON_PREFER})
-    endif()
-  endif()
-endif()
-
 if("toolchain_ld_base" IN_LIST Deprecated_FIND_COMPONENTS)
   # This code was deprecated after Zephyr v4.0.0
   list(REMOVE_ITEM Deprecated_FIND_COMPONENTS toolchain_ld_base)
@@ -152,23 +90,5 @@ if(NOT "${Deprecated_FIND_COMPONENTS}" STREQUAL "")
                  "${Deprecated_FIND_COMPONENTS}")
 endif()
 
-if("SEARCHED_LINKER_SCRIPT" IN_LIST Deprecated_FIND_COMPONENTS)
-  # This code was deprecated after Zephyr v3.5.0
-  list(REMOVE_ITEM Deprecated_FIND_COMPONENTS SEARCHED_LINKER_SCRIPT)
-
-  # Try a board specific linker file
-  set(LINKER_SCRIPT ${BOARD_DIR}/linker.ld)
-  if(NOT EXISTS ${LINKER_SCRIPT})
-    # If not available, try an SoC specific linker file
-    set(LINKER_SCRIPT ${SOC_FULL_DIR}/linker.ld)
-  endif()
-  message(DEPRECATION
-      "Pre-defined `linker.ld` script is deprecated. Please set "
-      "BOARD_LINKER_SCRIPT or SOC_LINKER_SCRIPT to point to ${LINKER_SCRIPT} "
-      "or one of the Zephyr provided common linker scripts for the ${ARCH} "
-      "architecture."
-  )
-endif()
-
 set(Deprecated_FOUND True)
 set(DEPRECATED_FOUND True)
diff --git a/cmake/modules/FindGnuLd.cmake b/cmake/modules/FindGnuLd.cmake
index 9ee42cc82fe..937218ecc1b 100644
--- a/cmake/modules/FindGnuLd.cmake
+++ b/cmake/modules/FindGnuLd.cmake
@@ -87,10 +87,11 @@ if(GNULD_LINKER)
     # - "GNU ld (GNU Binutils for Ubuntu) 2.34"
     # - "GNU ld (Zephyr SDK 0.15.2) 2.38"
     # - "GNU ld (Gentoo 2.39 p5) 2.39.0"
+    # - "GNU ld version 2.17.50.0.9 20070103"
     string(REGEX MATCH
-           "GNU ld \\(.+\\) ([0-9]+[.][0-9]+[.]?[0-9]*).*"
+           "GNU ld (\\(.+\\)|version) ([0-9]+[.][0-9]+[.]?[0-9]*).*"
            out_var ${gnuld_version_output})
-    set(GNULD_VERSION_STRING ${CMAKE_MATCH_1} CACHE STRING "GNU ld version" FORCE)
+    set(GNULD_VERSION_STRING ${CMAKE_MATCH_2} CACHE STRING "GNU ld version" FORCE)
   endif()
 endif()
 
diff --git a/cmake/modules/FindHostTools.cmake b/cmake/modules/FindHostTools.cmake
index f0954a26b75..a73d52956aa 100644
--- a/cmake/modules/FindHostTools.cmake
+++ b/cmake/modules/FindHostTools.cmake
@@ -48,8 +48,6 @@ if(HostTools_FOUND)
   return()
 endif()
 
-find_package(Deprecated COMPONENTS CROSS_COMPILE)
-
 find_package(Zephyr-sdk 0.16)
 
 # gperf is an optional dependency
diff --git a/cmake/modules/arch_v2.cmake b/cmake/modules/arch.cmake
similarity index 100%
rename from cmake/modules/arch_v2.cmake
rename to cmake/modules/arch.cmake
diff --git a/cmake/modules/arch_v1.cmake b/cmake/modules/arch_v1.cmake
deleted file mode 100644
index 613182f0723..00000000000
--- a/cmake/modules/arch_v1.cmake
+++ /dev/null
@@ -1,54 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-#
-# Copyright (c) 2022, Nordic Semiconductor ASA
-
-#
-# This CMake module is only valid for hw model v1.
-# In hw model v1, then arch is determined by the board folder structure.
-#
-# Configure ARCH settings based on board directory and arch root.
-#
-# This CMake module will set the following variables in the build system based
-# on board directory and arch root.
-#
-# If no implementation is available for the current arch an error will be raised.
-#
-# Outcome:
-# The following variables will be defined when this CMake module completes:
-#
-# - ARCH:      Name of the arch in use.
-# - ARCH_DIR:  Directory containing the arch implementation.
-# - ARCH_ROOT: ARCH_ROOT with ZEPHYR_BASE appended
-#
-# Variable dependencies:
-# - ARCH_ROOT: CMake list of arch roots containing arch implementations
-# - BOARD_DIR: CMake variable specifying the directory of the selected BOARD
-#
-# Variables set by this module and not mentioned above are considered internal
-# use only and may be removed, renamed, or re-purposed without prior notice.
-
-include_guard(GLOBAL)
-
-if(HWMv1)
-  # 'ARCH_ROOT' is a prioritized list of directories where archs may be
-  # found. It always includes ${ZEPHYR_BASE} at the lowest priority (except for unittesting).
-  if(NOT unittest IN_LIST Zephyr_FIND_COMPONENTS)
-    list(APPEND ARCH_ROOT ${ZEPHYR_BASE})
-  endif()
-
-  cmake_path(GET BOARD_DIR PARENT_PATH board_arch_dir)
-  cmake_path(GET board_arch_dir FILENAME ARCH)
-
-  foreach(root ${ARCH_ROOT})
-    if(EXISTS ${root}/arch/${ARCH}/CMakeLists.txt)
-      set(ARCH_DIR ${root}/arch)
-      break()
-    endif()
-  endforeach()
-
-  if(NOT ARCH_DIR)
-    message(FATAL_ERROR "Could not find ARCH=${ARCH} for BOARD=${BOARD}, \
-please check your installation. ARCH roots searched: \n\
-${ARCH_ROOT}")
-  endif()
-endif()
diff --git a/cmake/modules/boards.cmake b/cmake/modules/boards.cmake
index 3f086dca948..9d75ff377ff 100644
--- a/cmake/modules/boards.cmake
+++ b/cmake/modules/boards.cmake
@@ -141,8 +141,7 @@ Hints:
   endif()
 endforeach()
 
-if((HWMv1 AND NOT EXISTS ${BOARD_DIR}/${BOARD}_defconfig)
-   OR (HWMv2 AND NOT EXISTS ${BOARD_DIR}/board.yml))
+if(HWMv2 AND NOT EXISTS ${BOARD_DIR}/board.yml)
   message(WARNING "BOARD_DIR: ${BOARD_DIR} has been moved or deleted. "
                   "Trying to find new location."
   )
@@ -209,9 +208,8 @@ if(NOT "${ret_board}" STREQUAL "")
   endforeach()
 
   # Create two CMake variables identifying the hw model.
-  # CMake variable: HWM=[v1,v2]
-  # CMake variable: HWMv1=True, when HWMv1 is in use.
-  # CMake variable: HWMv2=True, when HWMv2 is in use.
+  # CMake variable: HWM=v2
+  # CMake variable: HWMv2=True
   set(HWM       ${LIST_BOARD_HWM} CACHE INTERNAL "Zephyr hardware model version")
   set(HWM${HWM} True   CACHE INTERNAL "Zephyr hardware model")
 elseif(BOARD_DIR)
@@ -228,86 +226,67 @@ else()
   message(FATAL_ERROR "Invalid BOARD; see above.")
 endif()
 
-if(HWMv1 AND DEFINED BOARD_QUALIFIERS)
-  message(FATAL_ERROR
-          "Board '${BOARD}' does not support board qualifiers, ${BOARD}${BOARD_QUALIFIERS}.\n"
-          "Please specify board without qualifiers.\n"
-  )
-endif()
-
 cmake_path(IS_PREFIX ZEPHYR_BASE "${BOARD_DIR}" NORMALIZE in_zephyr_tree)
 if(NOT in_zephyr_tree)
   set(USING_OUT_OF_TREE_BOARD 1)
 endif()
 
-if(HWMv1)
-  if(EXISTS ${BOARD_DIR}/revision.cmake)
-    # Board provides revision handling.
+if(LIST_BOARD_REVISION_FORMAT)
+  if(LIST_BOARD_REVISION_FORMAT STREQUAL "custom")
     include(${BOARD_DIR}/revision.cmake)
-  elseif(BOARD_REVISION)
-    message(WARNING "Board revision ${BOARD_REVISION} specified for ${BOARD}, \
-                     but board has no revision so revision will be ignored.")
-  endif()
-elseif(HWMv2)
-  if(LIST_BOARD_REVISION_FORMAT)
-    if(LIST_BOARD_REVISION_FORMAT STREQUAL "custom")
-      include(${BOARD_DIR}/revision.cmake)
-    else()
-      if(EXISTS ${BOARD_DIR}/revision.cmake)
-        message(WARNING
-          "revision.cmake ignored, revision.cmake is only used for revision format: 'custom'"
-        )
-      endif()
-
-      string(TOUPPER "${LIST_BOARD_REVISION_FORMAT}" rev_format)
-      if(LIST_BOARD_REVISION_EXACT)
-        set(rev_exact EXACT)
-      endif()
-
-      board_check_revision(
-        FORMAT ${rev_format}
-        DEFAULT_REVISION ${LIST_BOARD_REVISION_DEFAULT}
-        VALID_REVISIONS ${LIST_BOARD_REVISIONS}
-        ${rev_exact}
-      )
-    endif()
-  elseif(DEFINED BOARD_REVISION)
+  else()
     if(EXISTS ${BOARD_DIR}/revision.cmake)
       message(WARNING
-        "revision.cmake is not used, revisions must be defined in '${BOARD_DIR}/board.yml'"
+        "revision.cmake ignored, revision.cmake is only used for revision format: 'custom'"
       )
     endif()
 
-    message(FATAL_ERROR "Invalid board revision: ${BOARD_REVISION}\n"
-                        "Board '${BOARD}' does not define any revisions."
+    string(TOUPPER "${LIST_BOARD_REVISION_FORMAT}" rev_format)
+    if(LIST_BOARD_REVISION_EXACT)
+      set(rev_exact EXACT)
+    endif()
+
+    board_check_revision(
+      FORMAT ${rev_format}
+      DEFAULT_REVISION ${LIST_BOARD_REVISION_DEFAULT}
+      VALID_REVISIONS ${LIST_BOARD_REVISIONS}
+      ${rev_exact}
+    )
+  endif()
+elseif(DEFINED BOARD_REVISION)
+  if(EXISTS ${BOARD_DIR}/revision.cmake)
+    message(WARNING
+      "revision.cmake is not used, revisions must be defined in '${BOARD_DIR}/board.yml'"
     )
   endif()
 
-  if(LIST_BOARD_QUALIFIERS)
-    # Allow users to omit the SoC when building for a board with a single SoC.
-    list(LENGTH LIST_BOARD_SOCS socs_length)
-    if(socs_length EQUAL 1)
-      set(BOARD_SINGLE_SOC TRUE)
-      set(BOARD_${BOARD}_SINGLE_SOC TRUE)
-      if(NOT DEFINED BOARD_QUALIFIERS)
-        set(BOARD_QUALIFIERS "/${LIST_BOARD_SOCS}")
-      elseif("${BOARD_QUALIFIERS}" MATCHES "^//.*")
-        string(REGEX REPLACE "^//" "/${LIST_BOARD_SOCS}/" BOARD_QUALIFIERS "${BOARD_QUALIFIERS}")
-      endif()
-    endif()
+  message(FATAL_ERROR "Invalid board revision: ${BOARD_REVISION}\n"
+                      "Board '${BOARD}' does not define any revisions."
+  )
+endif()
 
-    set(board_targets ${LIST_BOARD_QUALIFIERS})
-    list(TRANSFORM board_targets PREPEND "${BOARD}/")
-    if(NOT ("${BOARD}${BOARD_QUALIFIERS}" IN_LIST board_targets))
-      string(REPLACE ";" "\n" board_targets "${board_targets}")
-      unset(CACHED_BOARD CACHE)
-      message(FATAL_ERROR "Board qualifiers `${BOARD_QUALIFIERS}` for board \
-            `${BOARD}` not found. Please specify a valid board target.\n"
-            "Valid board targets for ${LIST_BOARD_NAME} are:\n${board_targets}\n")
+if(LIST_BOARD_QUALIFIERS)
+  # Allow users to omit the SoC when building for a board with a single SoC.
+  list(LENGTH LIST_BOARD_SOCS socs_length)
+  if(socs_length EQUAL 1)
+    set(BOARD_SINGLE_SOC TRUE)
+    set(BOARD_${BOARD}_SINGLE_SOC TRUE)
+    if(NOT DEFINED BOARD_QUALIFIERS)
+      set(BOARD_QUALIFIERS "/${LIST_BOARD_SOCS}")
+    elseif("${BOARD_QUALIFIERS}" MATCHES "^//.*")
+      string(REGEX REPLACE "^//" "/${LIST_BOARD_SOCS}/" BOARD_QUALIFIERS "${BOARD_QUALIFIERS}")
     endif()
   endif()
-else()
-  message(FATAL_ERROR "Unknown hw model (${HWM}) for board: ${BOARD}.")
+
+  set(board_targets ${LIST_BOARD_QUALIFIERS})
+  list(TRANSFORM board_targets PREPEND "${BOARD}/")
+  if(NOT ("${BOARD}${BOARD_QUALIFIERS}" IN_LIST board_targets))
+    string(REPLACE ";" "\n" board_targets "${board_targets}")
+    unset(CACHED_BOARD CACHE)
+    message(FATAL_ERROR "Board qualifiers `${BOARD_QUALIFIERS}` for board \
+          `${BOARD}` not found. Please specify a valid board target.\n"
+          "Valid board targets for ${LIST_BOARD_NAME} are:\n${board_targets}\n")
+  endif()
 endif()
 
 set(board_message "Board: ${BOARD}")
diff --git a/cmake/modules/configuration_files.cmake b/cmake/modules/configuration_files.cmake
index ff7a172445c..fe1ff3bf16f 100644
--- a/cmake/modules/configuration_files.cmake
+++ b/cmake/modules/configuration_files.cmake
@@ -47,10 +47,6 @@ else()
   if(${CONF_FILE_LENGTH} EQUAL 1)
     get_filename_component(CONF_FILE_NAME ${CONF_FILE} NAME)
     if(${CONF_FILE_NAME} MATCHES "prj_(.*).conf")
-      set(CONF_FILE_BUILD_TYPE ${CMAKE_MATCH_1})
-      zephyr_file(CONF_FILES ${APPLICATION_CONFIG_DIR}/boards KCONF CONF_FILE
-                  BUILD ${CONF_FILE_BUILD_TYPE}
-      )
       set(CONF_FILE_FORCE_CACHE FORCE)
     endif()
   endif()
diff --git a/cmake/modules/dts.cmake b/cmake/modules/dts.cmake
index 4ab76989f74..49408730dcd 100644
--- a/cmake/modules/dts.cmake
+++ b/cmake/modules/dts.cmake
@@ -329,8 +329,7 @@ execute_process(
   COMMAND_ERROR_IS_FATAL ANY
   )
 zephyr_file_copy(${DEVICETREE_GENERATED_H}.new ${DEVICETREE_GENERATED_H} ONLY_IF_DIFFERENT)
-file(REMOVE ${ZEPHYR_DTS}.new ${DEVICETREE_GENERATED_H}.new)
-message(STATUS "Generated zephyr.dts: ${ZEPHYR_DTS}")
+file(REMOVE ${DEVICETREE_GENERATED_H}.new)
 message(STATUS "Generated devicetree_generated.h: ${DEVICETREE_GENERATED_H}")
 
 #
@@ -416,17 +415,9 @@ execute_process(
   ${ZEPHYR_DTS}
   OUTPUT_QUIET # Discard stdout
   WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
-  RESULT_VARIABLE ret
-  ERROR_VARIABLE stderr
+  COMMAND_ERROR_IS_FATAL ANY
   )
 
-if(NOT "${ret}" STREQUAL "0")
-  message(FATAL_ERROR "dtc failed with return code: ${ret}")
-elseif(stderr)
-  # dtc printed warnings on stderr but did not fail.
-  # Display them as CMake warnings to draw attention.
-  message(WARNING "dtc raised one or more warnings:\n${stderr}")
-endif()
 endif(DTC)
 
 build_info(devicetree files PATH ${dts_files})
diff --git a/cmake/modules/extensions.cmake b/cmake/modules/extensions.cmake
index d33f3cdf187..4d09c7eda3e 100644
--- a/cmake/modules/extensions.cmake
+++ b/cmake/modules/extensions.cmake
@@ -336,6 +336,12 @@ function(process_flags lang input output)
 
   foreach(flag ${${input}})
     set(is_compile_lang_generator_expression 0)
+    # SHELL is used to avoid de-duplication, but when process flags
+    # then this tag must be removed to return real compile/linker flags.
+    if(flag MATCHES "^SHELL:[ ]*(.*)")
+      separate_arguments(flag UNIX_COMMAND ${CMAKE_MATCH_1})
+    endif()
+
     foreach(l ${languages})
       if(flag MATCHES "<COMPILE_LANGUAGE:${l}>:([^>]+)>")
         set(updated_flag ${CMAKE_MATCH_1})
@@ -356,11 +362,6 @@ function(process_flags lang input output)
     endforeach()
 
     if(NOT is_compile_lang_generator_expression)
-      # SHELL is used to avoid de-duplication, but when process flags
-      # then this tag must be removed to return real compile/linker flags.
-      if(flag MATCHES "SHELL:[ ]*(.*)")
-        separate_arguments(flag UNIX_COMMAND ${CMAKE_MATCH_1})
-      endif()
       # Flags may be placed inside generator expression, therefore any flag
       # which is not already a generator expression must have commas converted.
       if(NOT flag MATCHES "\\\$<.*>")
@@ -475,8 +476,9 @@ endmacro()
 #        placed directly at the ZEPHYR_MODULE's root directory or for cases
 #        where the module integration file is located in a 'MODULE_EXT_ROOT'.
 #
-# Note, in order to ensure correct library when amending, the folder structure in the
-# Zephyr module must resemble the structure used in Zephyr, as example:
+# Note, in order to ensure correct library when amending, the folder structure
+# in the Zephyr module or '<dir>' base directory must resemble the structure
+# used in Zephyr, as example:
 #
 # Example: to amend the zephyr library created in
 # ZEPHYR_BASE/drivers/entropy/CMakeLists.txt
@@ -1599,8 +1601,8 @@ function(pow2round n)
   set(${n} ${${n}} PARENT_SCOPE)
 endfunction()
 
-# Function to create a build string based on BOARD, BOARD_REVISION, and BUILD
-# type.
+# Function to create a build string based on BOARD, BOARD_REVISION, and
+# BOARD_QUALIFIER.
 #
 # This is a common function to ensure that build strings are always created
 # in a uniform way.
@@ -1615,8 +1617,6 @@ endfunction()
 # - Build string with cpuset removed in addition
 # - Build string with soc removed in addition
 #
-# If BUILD is supplied, then build type will be appended to each entry in the
-# list above.
 # If REVISION is supplied or obtained as system wide setting a build string
 # with the sanitized revision string will be added in addition to the
 # non-revisioned entry for each entry.
@@ -1627,12 +1627,10 @@ endfunction()
 #                       [SHORT <out-variable>]
 #                       [BOARD_QUALIFIERS <qualifiers>]
 #                       [BOARD_REVISION <revision>]
-#                       [BUILD <type>]
 #                       [MERGE [REVERSE]]
 #   )
 #   zephyr_build_string(<out-variable>
 #                       BOARD_QUALIFIERS <qualifiers>
-#                       [BUILD <type>]
 #                       [MERGE [REVERSE]]
 #   )
 #
@@ -1640,18 +1638,17 @@ endfunction()
 # SHORT <out-variable>:      Output variable where the shortened build string will be returned.
 # BOARD <board>:             Board name to use when creating the build string.
 # BOARD_REVISION <revision>: Board revision to use when creating the build string.
-# BUILD <type>:              Build type to use when creating the build string.
 # MERGE:                     Return a list of build strings instead of a single build string.
 # REVERSE:                   Reverse the list before returning it.
 #
 # Examples
 # calling
-#   zephyr_build_string(build_string BOARD alpha BUILD debug)
-# will return the string `alpha_debug` in `build_string` parameter.
+#   zephyr_build_string(build_string BOARD alpha)
+# will return the string `alpha` in `build_string` parameter.
 #
 # calling
-#   zephyr_build_string(build_string BOARD alpha BOARD_REVISION 1.0.0 BUILD debug)
-# will return the string `alpha_1_0_0_debug` in `build_string` parameter.
+#   zephyr_build_string(build_string BOARD alpha BOARD_REVISION 1.0.0)
+# will return the string `alpha_1_0_0` in `build_string` parameter.
 #
 # calling
 #   zephyr_build_string(build_string BOARD alpha BOARD_QUALIFIERS /soc/bar)
@@ -1674,7 +1671,7 @@ endfunction()
 #
 function(zephyr_build_string outvar)
   set(options MERGE REVERSE)
-  set(single_args BOARD BOARD_QUALIFIERS BOARD_REVISION BUILD SHORT)
+  set(single_args BOARD BOARD_QUALIFIERS BOARD_REVISION SHORT)
 
   cmake_parse_arguments(BUILD_STR "${options}" "${single_args}" "" ${ARGN})
   if(BUILD_STR_UNPARSED_ARGUMENTS)
@@ -1708,10 +1705,10 @@ function(zephyr_build_string outvar)
   string(REPLACE "/" ";" str_segment_list "${BUILD_STR_BOARD_QUALIFIERS}")
   string(REPLACE "." "_" revision_string "${BUILD_STR_BOARD_REVISION}")
 
-  string(JOIN "_" ${outvar} ${BUILD_STR_BOARD} ${str_segment_list} ${revision_string} ${BUILD_STR_BUILD})
+  string(JOIN "_" ${outvar} ${BUILD_STR_BOARD} ${str_segment_list} ${revision_string})
 
   if(BUILD_STR_MERGE)
-    string(JOIN "_" variant_string ${BUILD_STR_BOARD} ${str_segment_list} ${BUILD_STR_BUILD})
+    string(JOIN "_" variant_string ${BUILD_STR_BOARD} ${str_segment_list})
 
     if(NOT "${variant_string}" IN_LIST ${outvar})
       list(APPEND ${outvar} "${variant_string}")
@@ -1727,10 +1724,10 @@ function(zephyr_build_string outvar)
     string(REGEX REPLACE "^/[^/]*(.*)" "\\1" shortened_qualifiers "${BOARD_QUALIFIERS}")
     string(REPLACE "/" ";" str_short_segment_list "${shortened_qualifiers}")
     string(JOIN "_" ${BUILD_STR_SHORT}
-           ${BUILD_STR_BOARD} ${str_short_segment_list} ${revision_string} ${BUILD_STR_BUILD}
+           ${BUILD_STR_BOARD} ${str_short_segment_list} ${revision_string}
     )
     if(BUILD_STR_MERGE)
-      string(JOIN "_" variant_string ${BUILD_STR_BOARD} ${str_short_segment_list} ${BUILD_STR_BUILD})
+      string(JOIN "_" variant_string ${BUILD_STR_BOARD} ${str_short_segment_list})
 
       if(NOT "${variant_string}" IN_LIST ${BUILD_STR_SHORT})
         list(APPEND ${BUILD_STR_SHORT} "${variant_string}")
@@ -2676,7 +2673,7 @@ endfunction()
 # Usage:
 #   zephyr_file(CONF_FILES <paths> [DTS <list>] [KCONF <list>]
 #               [BOARD <board> [BOARD_REVISION <revision>] | NAMES <name> ...]
-#               [BUILD <type>] [SUFFIX <suffix>] [REQUIRED]
+#               [SUFFIX <suffix>] [REQUIRED]
 #   )
 #
 # CONF_FILES <paths>: Find all configuration files in the list of paths and
@@ -2703,10 +2700,6 @@ endfunction()
 #                     DTS <list>:    List to append DTS overlay files in <path> to
 #                     KCONF <list>:  List to append Kconfig fragment files in <path> to
 #                     DEFCONF <list>: List to append _defconfig files in <path> to
-#                     BUILD <type>:  Build type to include for search.
-#                                    For example:
-#                                    BUILD debug, will look for <board>_debug.conf
-#                                    and <board>_debug.overlay, instead of <board>.conf
 #                     SUFFIX <name>: Suffix name to check for instead of the default name
 #                                    but with a fallback to the default name if not found.
 #                                    For example:
@@ -2726,7 +2719,7 @@ Please provide one of following: APPLICATION_ROOT, CONF_FILES")
     set(single_args APPLICATION_ROOT BASE_DIR)
   elseif(${ARGV0} STREQUAL CONF_FILES)
     set(options QUALIFIERS REQUIRED)
-    set(single_args BOARD BOARD_REVISION BOARD_QUALIFIERS DTS KCONF DEFCONFIG BUILD SUFFIX)
+    set(single_args BOARD BOARD_REVISION BOARD_QUALIFIERS DTS KCONF DEFCONFIG SUFFIX)
     set(multi_args CONF_FILES NAMES)
   endif()
 
@@ -2805,13 +2798,11 @@ Relative paths are only allowed with `-D${ARGV1}=<path>`")
                             BOARD ${ZFILE_BOARD}
                             BOARD_REVISION ${ZFILE_BOARD_REVISION}
                             BOARD_QUALIFIERS ${ZFILE_BOARD_QUALIFIERS}
-                            BUILD ${ZFILE_BUILD}
                             MERGE REVERSE
         )
       else()
         zephyr_build_string(filename_list
                             BOARD_QUALIFIERS ${ZFILE_BOARD_QUALIFIERS}
-                            BUILD ${ZFILE_BUILD}
                             MERGE REVERSE
         )
       endif()
@@ -2847,10 +2838,6 @@ Relative paths are only allowed with `-D${ARGV1}=<path>`")
             list(APPEND found_dts_files ${test_file_0})
             list(APPEND found_dts_files ${test_file_1})
 
-            if(DEFINED ZFILE_BUILD)
-              set(deprecated_file_found y)
-            endif()
-
             if(ZFILE_NAMES)
               break()
             endif()
@@ -2898,10 +2885,6 @@ Relative paths are only allowed with `-D${ARGV1}=<path>`")
             list(APPEND found_conf_files ${test_file_0})
             list(APPEND found_conf_files ${test_file_1})
 
-            if(DEFINED ZFILE_BUILD)
-              set(deprecated_file_found y)
-            endif()
-
             if(ZFILE_NAMES)
               break()
             endif()
@@ -2939,11 +2922,6 @@ Relative paths are only allowed with `-D${ARGV1}=<path>`")
       )
     endif()
 
-    if(deprecated_file_found)
-      message(DEPRECATION "prj_<build>.conf was deprecated after Zephyr 3.5,"
-                          " you should switch to using -DFILE_SUFFIX instead")
-    endif()
-
     if(ZFILE_DEFCONFIG)
       set(found_defconf_files)
       foreach(path ${ZFILE_CONF_FILES})
@@ -3071,28 +3049,28 @@ endfunction()
 #
 # Zephyr string function extension.
 # This function extends the CMake string function by providing additional
-# manipulation arguments to CMake string.
-#
-# ESCAPE:   Ensure that any single '\', except '\"', in the input string is
-#           escaped with the escape char '\'. For example the string 'foo\bar'
-#           will be escaped so that it becomes 'foo\\bar'.
-#           Backslashes which are already escaped will not be escaped further,
-#           for example 'foo\\bar' will not be modified.
-#           This is useful for handling of windows path separator in strings or
-#           when strings contains newline escapes such as '\n' and this can
-#           cause issues when writing to a file where a '\n' is desired in the
-#           string instead of a newline.
+# manipulation options for the <mode> argument:
+#
+# ESCAPE: Ensure that every character of the input arguments is considered
+#         by CMake as a literal by prefixing the escape character '\' where
+#         appropriate. This is useful for handling Windows path separators in
+#         strings, or when it is desired to write "\n" as an actual string of
+#         four characters instead of a single newline.
+#         Note that this operation must be performed exactly once during the
+#         lifetime of a string, or previous escape characters will be treated
+#         as literals and escaped further.
 #
 # SANITIZE: Ensure that the output string does not contain any special
 #           characters. Special characters, such as -, +, =, $, etc. are
-#           converted to underscores '_'.
+#           converted to underscores '_'. Multiple arguments are concatenated.
 #
 # SANITIZE TOUPPER: Ensure that the output string does not contain any special
-#                   characters. Special characters, such as -, +, =, $, etc. are
-#                   converted to underscores '_'.
+#                   characters. Special characters, such as -, +, =, $, etc.
+#                   are converted to underscores '_'. Multiple arguments are
+#                   concatenated.
 #                   The sanitized string will be returned in UPPER case.
 #
-# returns the updated string
+# Returns the updated string in <out-var>.
 function(zephyr_string)
   set(options SANITIZE TOUPPER ESCAPE)
   cmake_parse_arguments(ZEPHYR_STRING "${options}" "" "" ${ARGN})
@@ -3106,21 +3084,20 @@ function(zephyr_string)
   list(GET ZEPHYR_STRING_UNPARSED_ARGUMENTS 0 return_arg)
   list(REMOVE_AT ZEPHYR_STRING_UNPARSED_ARGUMENTS 0)
 
-  list(JOIN ZEPHYR_STRING_UNPARSED_ARGUMENTS "" work_string)
-
   if(ZEPHYR_STRING_SANITIZE)
+    list(JOIN ZEPHYR_STRING_UNPARSED_ARGUMENTS "" work_string)
     string(REGEX REPLACE "[^a-zA-Z0-9_]" "_" work_string ${work_string})
-  endif()
-
-  if(ZEPHYR_STRING_TOUPPER)
-    string(TOUPPER ${work_string} work_string)
-  endif()
-
-  if(ZEPHYR_STRING_ESCAPE)
-    # If a single '\' is discovered, such as 'foo\bar', then it must be escaped like: 'foo\\bar'
-    # \\1 and \\2 are keeping the match patterns, the \\\\ --> \\ meaning an escaped '\',
-    # which then becomes a single '\' in the final string.
-    string(REGEX REPLACE "([^\\][\\])([^\\\"])" "\\1\\\\\\2" work_string "${ZEPHYR_STRING_UNPARSED_ARGUMENTS}")
+    if(ZEPHYR_STRING_TOUPPER)
+      string(TOUPPER ${work_string} work_string)
+    endif()
+  elseif(ZEPHYR_STRING_ESCAPE)
+    # Escape every instance of '\' or '"' in the <input> arguments.
+    # Note that:
+    #  - backslashes must be replaced first to avoid duplicating the '\' in \"
+    #  - "\\\\" is seen by CMake as \\, meaning an escaped '\', which then
+    #    becomes a single '\' in the final string.
+    string(REGEX REPLACE "\\\\" "\\\\\\\\" work_string "${ZEPHYR_STRING_UNPARSED_ARGUMENTS}")
+    string(REGEX REPLACE "\"" "\\\\\"" work_string "${work_string}")
   endif()
 
   set(${return_arg} ${work_string} PARENT_SCOPE)
@@ -3735,11 +3712,11 @@ function(topological_sort)
 endfunction()
 
 # Usage:
-#   build_info(<tag>... VALUE <value>... )
-#   build_info(<tag>... PATH  <path>... )
+#   build_info(<tag>... VALUE <value>...)
+#   build_info(<tag>... PATH  <path>...)
 #
-# This function populates updates the build_info.yml info file with exchangable build information
-# related to the current build.
+# This function populates the build_info.yml info file with exchangable build
+# information related to the current build.
 #
 # Example:
 #   build_info(devicetree files VALUE file1.dts file2.dts file3.dts)
@@ -3769,6 +3746,14 @@ function(build_info)
     message(FATAL_ERROR "${CMAKE_CURRENT_FUNCTION}(...) missing a required argument: VALUE or PATH")
   endif()
 
+  string(GENEX_STRIP "${arg_list}" arg_list_no_genexes)
+  if (NOT "${arg_list}" STREQUAL "${arg_list_no_genexes}")
+    if (convert_path)
+      message(FATAL_ERROR "build_info: generator expressions unsupported on PATH entries")
+    endif()
+    set(genex_flag GENEX)
+  endif()
+
   yaml_context(EXISTS NAME build_info result)
   if(NOT result)
     yaml_load(FILE ${ZEPHYR_BASE}/scripts/schemas/build-schema.yml NAME build_info_schema)
@@ -3811,7 +3796,7 @@ function(build_info)
     endif()
   endif()
 
-  yaml_set(NAME build_info KEY cmake ${keys} ${type} "${values}")
+  yaml_set(NAME build_info KEY cmake ${keys} ${type} "${values}" ${genex_flag})
 endfunction()
 
 ########################################################
@@ -4870,7 +4855,7 @@ function(zephyr_linker_dts_section)
 
   dt_reg_addr(addr PATH ${DTS_SECTION_PATH})
 
-  zephyr_linker_section(NAME ${name} ADDRESS ${addr} VMA ${name} TYPE NOLOAD)
+  zephyr_linker_section(NAME ${name} VMA ${name} TYPE NOLOAD)
 
 endfunction()
 
@@ -5070,8 +5055,9 @@ endfunction()
 #                         [VMA <region|group>] [LMA <region|group>]
 #                         [ADDRESS <address>] [ALIGN <alignment>]
 #                         [SUBALIGN <alignment>] [FLAGS <flags>]
+#                         [MIN_SIZE <minimum size>] [MAX_SIZE <maximum size>]
 #                         [HIDDEN] [NOINPUT] [NOINIT]
-#                         [PASS [NOT] <name>]
+#                         [PASS [NOT] [<name>]]
 #   )
 #
 # Zephyr linker output section.
@@ -5123,23 +5109,23 @@ endfunction()
 #  Note: Regarding all alignment attributes. Not all linkers may handle alignment
 #        in identical way. For example the Scatter file will align both load and
 #        execution address (LMA and VMA) to be aligned when given the ALIGN attribute.
+# MIN_SIZE <size>     : Pad section so that it at least <size> bytes in size.
+# MAX_SIZE <size>     : Check that the sections is not larger than <size> bytes.
 # NOINPUT             : No default input sections will be defined, to setup input
 #                       sections for section <name>, the corresponding
 #                       `zephyr_linker_section_configure()` must be used.
-# PASS [NOT] <name>   : Linker pass iteration where this section should be active.
-#                       Default a section will be present during all linker passes
-#                       but in cases a section shall only be present at a specific
-#                       pass, this argument can be used. For example to only have
-#                       this section present on the `TEST` linker pass, use `PASS TEST`.
-#                       It is possible to negate <name>, such as `PASS NOT <name>`.
-#                       For example, `PASS NOT TEST` means the call is effective
-#                       on all but the `TEST` linker pass iteration.
-#
+# PASS [NOT] [<name> ..]: Linker pass where this section should be active.
+#                       By default a section will be present during all linker
+#                       passes.
+#                       PASS [<p1>] [<p2>...] makes the section present only in
+#                       the given passes. Empty list means no passes.
+#                       PASS NOT [<p1>] [<p2>...] makes the section present in
+#                       all but the given passes. Empty list means all passes.
 # Note: VMA and LMA are mutual exclusive with GROUP
 #
 function(zephyr_linker_section)
   set(options     "ALIGN_WITH_INPUT;HIDDEN;NOINIT;NOINPUT")
-  set(single_args "ADDRESS;ALIGN;ENDALIGN;GROUP;KVMA;LMA;NAME;SUBALIGN;TYPE;VMA")
+  set(single_args "ADDRESS;ALIGN;ENDALIGN;GROUP;KVMA;LMA;NAME;SUBALIGN;TYPE;VMA;MIN_SIZE;MAX_SIZE")
   set(multi_args  "PASS")
   cmake_parse_arguments(SECTION "${options}" "${single_args}" "${multi_args}" ${ARGN})
 
@@ -5171,16 +5157,7 @@ function(zephyr_linker_section)
     endif()
   endif()
 
-  if(DEFINED SECTION_PASS)
-    list(LENGTH SECTION_PASS pass_length)
-    if(${pass_length} GREATER 1)
-      list(GET SECTION_PASS 0 pass_elem_0)
-      if((NOT (${pass_elem_0} STREQUAL "NOT")) OR (${pass_length} GREATER 2))
-        message(FATAL_ERROR "zephyr_linker_section(PASS takes maximum "
-          "a single argument of the form: '<pass name>' or 'NOT <pass_name>'.")
-      endif()
-    endif()
-  endif()
+  zephyr_linker_check_pass_param("${SECTION_PASS}")
 
   set(SECTION)
   zephyr_linker_arg_val_list(SECTION "${single_args}")
@@ -5281,7 +5258,11 @@ function(zephyr_iterable_section)
   endif()
 
   if(SECTION_NUMERIC)
-    set(INPUT "._${SECTION_NAME}.static.*_?_*;._${SECTION_NAME}.static.*_??_*")
+    set(INPUT "._${SECTION_NAME}.static.*_?_*;"
+              "._${SECTION_NAME}.static.*_??_*;"
+              "._${SECTION_NAME}.static.*_???_*;"
+              "._${SECTION_NAME}.static.*_????_*;"
+              "._${SECTION_NAME}.static.*_?????_*")
   else()
     set(INPUT "._${SECTION_NAME}.static.*")
   endif()
@@ -5311,8 +5292,8 @@ endfunction()
 # This is useful content such as struct devices.
 #
 # For example: zephyr_linker_section_obj_level(SECTION init LEVEL PRE_KERNEL_1)
-# will create an input section matching `.z_init_PRE_KERNEL_1?_` and
-# `.z_init_PRE_KERNEL_1??_`.
+# will create an input section matching `.z_init_PRE_KERNEL_P_1_SUB_?_`,
+# `.z_init_PRE_KERNEL_P_1_SUB_??_`, and `.z_init_PRE_KERNEL_P_1_SUB_???_`.
 #
 # SECTION <section>: Section in which the objects shall be placed
 # LEVEL <level>    : Priority level, all input sections matching the level
@@ -5336,13 +5317,18 @@ function(zephyr_linker_section_obj_level)
 
   zephyr_linker_section_configure(
     SECTION ${OBJ_SECTION}
-    INPUT ".z_${OBJ_SECTION}_${OBJ_LEVEL}?_*"
+    INPUT ".z_${OBJ_SECTION}_${OBJ_LEVEL}_P_?_*"
     SYMBOLS __${OBJ_SECTION}_${OBJ_LEVEL}_start
     KEEP SORT NAME
   )
   zephyr_linker_section_configure(
     SECTION ${OBJ_SECTION}
-    INPUT ".z_${OBJ_SECTION}_${OBJ_LEVEL}??_*"
+    INPUT ".z_${OBJ_SECTION}_${OBJ_LEVEL}_P_??_*"
+    KEEP SORT NAME
+  )
+  zephyr_linker_section_configure(
+    SECTION ${OBJ_SECTION}
+    INPUT ".z_${OBJ_SECTION}_${OBJ_LEVEL}_P_???_*"
     KEEP SORT NAME
   )
 endfunction()
@@ -5350,7 +5336,8 @@ endfunction()
 # Usage:
 #   zephyr_linker_section_configure(SECTION <section> [ALIGN <alignment>]
 #                                   [PASS [NOT] <name>] [PRIO <no>] [SORT <sort>]
-#                                   [ANY] [FIRST] [KEEP]
+#                                   [MIN_SIZE <minimum size>] [MAX_SIZE <maximum size>]
+#                                   [ANY] [FIRST] [KEEP] [INPUT <input>] [SYMBOLS [<start>[<end>]]]
 #   )
 #
 # Configure an output section with additional input sections.
@@ -5366,6 +5353,8 @@ endfunction()
 #                       first section in output.
 # SORT <NAME>         : Sort the input sections according to <type>.
 #                       Currently only `NAME` is supported.
+# MIN_SIZE <size>     : Pad section so that it at least <size> bytes in size.
+# MAX_SIZE <size>     : Check that the sections is not larger than <size> bytes.
 # KEEP                : Do not eliminate input section during linking
 # PRIO                : The priority of the input section. Per default, input
 #                       sections order is not guaranteed by all linkers, but
@@ -5378,19 +5367,20 @@ endfunction()
 #                       you may use `PRIO 50`, `PRIO 20` and so on.
 #                       To ensure an input section is at the end, it is advised
 #                       to use `PRIO 200` and above.
-# PASS [NOT] <name>   : The call should only be considered for linker pass where
-#                       <name> is defined. It is possible to negate <name>, such
-#                       as `PASS NOT <name>.
-#                       For example, `PASS TEST` means the call is only effective
-#                       on the `TEST` linker pass iteration. `PASS NOT TEST` on
-#                       all iterations the are not `TEST`.
+# PASS [NOT] [<pass>..]: Control in which linker passes this piece is present
+#                       See zephyr_linker_section(PASS) for details.
 # FLAGS <flags>       : Special section flags such as "+RO", +XO, "+ZI".
 # ANY                 : ANY section flag in scatter file.
 #                       The FLAGS and ANY arguments only has effect for scatter files.
+# INPUT <input>       : Input section name or list of input section names.
+#                       <input> is either just a section name ".data*" or
+#                       <file-pattern>(<section-patterns>... )
+#                       <file-pattern> is [library.a:]file
+#                       e.g. foo.a:bar.o(.data*)
 #
 function(zephyr_linker_section_configure)
   set(options     "ANY;FIRST;KEEP")
-  set(single_args "ALIGN;OFFSET;PRIO;SECTION;SORT")
+  set(single_args "ALIGN;OFFSET;PRIO;SECTION;SORT;MIN_SIZE;MAX_SIZE")
   set(multi_args  "FLAGS;INPUT;PASS;SYMBOLS")
   cmake_parse_arguments(SECTION "${options}" "${single_args}" "${multi_args}" ${ARGN})
 
@@ -5406,16 +5396,7 @@ function(zephyr_linker_section_configure)
     endif()
   endif()
 
-  if(DEFINED SECTION_PASS)
-    list(LENGTH SECTION_PASS pass_length)
-    if(${pass_length} GREATER 1)
-      list(GET SECTION_PASS 0 pass_elem_0)
-      if((NOT (${pass_elem_0} STREQUAL "NOT")) OR (${pass_length} GREATER 2))
-        message(FATAL_ERROR "zephyr_linker_section_configure(PASS takes maximum "
-          "a single argument of the form: '<pass name>' or 'NOT <pass_name>'.")
-      endif()
-    endif()
-  endif()
+  zephyr_linker_check_pass_param("${SECTION_PASS}")
 
   set(SECTION)
   zephyr_linker_arg_val_list(SECTION "${single_args}")
@@ -5464,6 +5445,98 @@ function(zephyr_linker_symbol)
   )
 endfunction()
 
+# Usage:
+#   zephyr_linker_include_generated(CMAKE|KCONFIG|HEADER <name> [PASS [NOT] <pass>])
+#
+# Add file that is generated at build-time to be included when running the
+# linker script generator.
+#
+# CMAKE <name>     : includes the given cmake file
+# KCONFIG <name>   : import_kconfig() the given Kconfig file. gives
+#                    @variable@ access to all the CONFIG_FOO settings
+# HEADER <name>    : finds all #define FOO value in name. Plain regex, no
+#                    proper preprocessing.
+# PASS [NOT] [<pass>]: Rule for which PASSES to include file.
+#                    see zephyr_linker_section(PASS)
+function(zephyr_linker_include_generated)
+  set(single_args "KCONFIG;HEADER;CMAKE")
+  set(multi_args "PASS")
+  cmake_parse_arguments(INCLUDE "" "${single_args}" "${multi_args}" ${ARGN})
+
+  #check that we have exactly one of CMAKE KCONFIG or HEADER
+  set(files)
+  list(APPEND files ${INCLUDE_CMAKE} ${INCLUDE_KCONFIG} ${INCLUDE_HEADER})
+  list(LENGTH files files_count)
+  if(NOT ${files_count} EQUAL 1)
+    message(FATAL_ERROR "zephyr_linker_include_generated(${ARGV0} ...) must have one of CMAKE, KCONFIG or HEADER")
+  endif()
+
+  zephyr_linker_check_pass_param("${INCLUDE_PASS}")
+
+  set(INCLUDE)
+  zephyr_linker_arg_val_list(INCLUDE "${single_args}")
+  zephyr_linker_arg_val_list(INCLUDE "${multi_args}")
+  string(REPLACE ";" "\;" INCLUDE "${INCLUDE}")
+  set_property(TARGET linker
+               APPEND PROPERTY INCLUDES "{${INCLUDE}}")
+endfunction()
+
+# Usage:
+#   zephyr_linker_include_var(VAR <name> [VALUE <value>] [PASS [NOT] <pass>])
+#
+# Save the value of <name> for when the generator is running at build-time.
+# If VALUE isn't set, the current value of the variable is used
+#
+# Save the value of <name> for when the generator is running at build-time.
+# If VALUE isn't set, the current value of the variable is used
+#
+# VAR <name>       : Variable to be set
+# VALUE <value>    : The value
+# PASS [NOT] <pass>: Rule for which PASSES to include variable see
+#                    zephyr_linker_section(PASS) for details.
+function(zephyr_linker_include_var)
+  set(single_args "VAR;VALUE")
+  set(multi_args "PASS")
+  cmake_parse_arguments(VAR "" "${single_args}" "${multi_args}" ${ARGN})
+  if(NOT DEFINED VAR_VAR)
+    message(FATAL_ERROR "zephyr_linker_include_var(${ARGV0} ...) must have VAR <variable> ")
+  endif()
+  if(NOT DEFINED VAR_VALUE)
+    if(DEFINED ${VAR_VAR})
+      set(VAR_VALUE ${${VAR_VAR}})
+    else()
+      message(FATAL_ERROR "zephyr_linker_include_var(${ARGV0} ...) value not set ")
+    endif()
+  endif()
+  zephyr_linker_check_pass_param("${VAR_PASS}")
+  set(VAR)
+  zephyr_linker_arg_val_list(VAR "${single_args}")
+  zephyr_linker_arg_val_list(VAR "${multi_args}")
+  string(REPLACE ";" "\;" VAR "${VAR}")
+  set_property(TARGET linker
+              APPEND PROPERTY VARIABLES "{${VAR}}")
+endfunction()
+
+# Usage:
+#   zephyr_linker_generate_linker_settings_file(file_name)
+#
+# Generate a file for the settings to the linker file generator script.
+# file_name      : File to be created
+#
+function(zephyr_linker_generate_linker_settings_file FILE)
+  file(GENERATE OUTPUT ${FILE} CONTENT
+         "set(FORMAT \"$<TARGET_PROPERTY:linker,FORMAT>\" CACHE INTERNAL \"\")\n
+          set(ENTRY \"$<TARGET_PROPERTY:linker,ENTRY>\" CACHE INTERNAL \"\")\n
+          set(MEMORY_REGIONS \"$<TARGET_PROPERTY:linker,MEMORY_REGIONS>\" CACHE INTERNAL \"\")\n
+          set(GROUPS \"$<TARGET_PROPERTY:linker,GROUPS>\" CACHE INTERNAL \"\")\n
+          set(SECTIONS \"$<TARGET_PROPERTY:linker,SECTIONS>\" CACHE INTERNAL \"\")\n
+          set(SECTION_SETTINGS \"$<TARGET_PROPERTY:linker,SECTION_SETTINGS>\" CACHE INTERNAL \"\")\n
+          set(SYMBOLS \"$<TARGET_PROPERTY:linker,SYMBOLS>\" CACHE INTERNAL \"\")\n
+          set(INCLUDES \"$<TARGET_PROPERTY:linker,INCLUDES>\" CACHE INTERNAL \"\")\n
+          set(VARIABLES \"$<TARGET_PROPERTY:linker,VARIABLES>\" CACHE INTERNAL \"\")\n
+         ")
+endfunction()
+
 # Internal helper macro for zephyr_linker*() functions.
 # The macro will create a list of argument-value pairs for defined arguments
 # that can be passed on to linker script generators and processed as a CMake
@@ -5484,6 +5557,16 @@ macro(zephyr_linker_arg_val_list list arguments)
   endforeach()
 endmacro()
 
+
+# Internal helper that checks if we have consistent PASS arguments.
+# Allow PASS [NOT] [<pass>...]
+function(zephyr_linker_check_pass_param PASSES)
+  list(POP_FRONT PASSES)
+  if("NOT" IN_LIST PASSES)
+    message(FATAL_ERROR "NOT only allowed before first <pass> value, like this: PASS [NOT] <pass>...")
+  endif()
+endfunction()
+
 ########################################################
 # 6. Function helper macros
 ########################################################
@@ -5715,7 +5798,7 @@ function(add_llext_target target_name)
   if(CONFIG_LLEXT_TYPE_ELF_OBJECT)
 
     # Create an object library to compile the source file
-    add_library(${llext_lib_target} OBJECT ${source_files})
+    add_library(${llext_lib_target} EXCLUDE_FROM_ALL OBJECT ${source_files})
     set(llext_lib_output $<TARGET_OBJECTS:${llext_lib_target}>)
 
   elseif(CONFIG_LLEXT_TYPE_ELF_RELOCATABLE)
@@ -5731,6 +5814,7 @@ function(add_llext_target target_name)
     target_link_options(${llext_lib_target} PRIVATE
       $<TARGET_PROPERTY:linker,partial_linking>)
     set_target_properties(${llext_lib_target} PROPERTIES
+      RUNTIME_OUTPUT_DIRECTORY ${PROJECT_BINARY_DIR}/llext
       SUFFIX ${CMAKE_C_OUTPUT_EXTENSION})
     set(llext_lib_output $<TARGET_FILE:${llext_lib_target}>)
 
@@ -5742,7 +5826,10 @@ function(add_llext_target target_name)
   elseif(CONFIG_LLEXT_TYPE_ELF_SHAREDLIB)
 
     # Create a shared library
-    add_library(${llext_lib_target} SHARED ${source_files})
+    add_library(${llext_lib_target} EXCLUDE_FROM_ALL SHARED ${source_files})
+    set_target_properties(${llext_lib_target} PROPERTIES
+      LIBRARY_OUTPUT_DIRECTORY ${PROJECT_BINARY_DIR}/llext
+    )
     set(llext_lib_output $<TARGET_FILE:${llext_lib_target}>)
 
     # Add the llext flags to the linking step as well
@@ -5771,11 +5858,14 @@ function(add_llext_target target_name)
     zephyr_generated_headers
   )
 
+  # Make sure the intermediate output directory exists.
+  file(MAKE_DIRECTORY ${PROJECT_BINARY_DIR}/llext)
+
   # Set up an intermediate processing step between compilation and packaging
   # to be used to support POST_BUILD commands on targets that do not use a
   # dynamic library.
   set(llext_proc_target ${target_name}_llext_proc)
-  set(llext_pkg_input ${PROJECT_BINARY_DIR}/${target_name}.llext.pkg_input)
+  set(llext_pkg_input ${PROJECT_BINARY_DIR}/llext/${target_name}_debug.elf)
   add_custom_target(${llext_proc_target} DEPENDS ${llext_pkg_input})
   set_property(TARGET ${llext_proc_target} PROPERTY has_post_build_cmds 0)
 
@@ -5808,49 +5898,19 @@ function(add_llext_target target_name)
     set(slid_inject_cmd ${CMAKE_COMMAND} -E true)
   endif()
 
-  # Type-specific packaging of the built binary file into an .llext file
-  if(CONFIG_LLEXT_TYPE_ELF_OBJECT)
-
-    # No packaging required, simply copy the object file
-    add_custom_command(
-      OUTPUT ${llext_pkg_output}
-      COMMAND ${CMAKE_COMMAND} -E copy ${llext_pkg_input} ${llext_pkg_output}
-      COMMAND ${slid_inject_cmd}
-      DEPENDS ${llext_proc_target} ${llext_pkg_input}
-    )
-
-  elseif(CONFIG_LLEXT_TYPE_ELF_RELOCATABLE)
-
-    # Need to remove just some sections from the relocatable object
-    # (using strip in this case would remove _all_ symbols)
-    add_custom_command(
-      OUTPUT ${llext_pkg_output}
-      COMMAND $<TARGET_PROPERTY:bintools,elfconvert_command>
-              $<TARGET_PROPERTY:bintools,elfconvert_flag>
-              $<TARGET_PROPERTY:bintools,elfconvert_flag_section_remove>.xt.*
-              $<TARGET_PROPERTY:bintools,elfconvert_flag_infile>${llext_pkg_input}
-              $<TARGET_PROPERTY:bintools,elfconvert_flag_outfile>${llext_pkg_output}
-              $<TARGET_PROPERTY:bintools,elfconvert_flag_final>
-      COMMAND ${slid_inject_cmd}
-      DEPENDS ${llext_proc_target} ${llext_pkg_input}
-    )
-
-  elseif(CONFIG_LLEXT_TYPE_ELF_SHAREDLIB)
-
-    # Need to strip the shared library of some sections
-    add_custom_command(
-      OUTPUT ${llext_pkg_output}
-      COMMAND $<TARGET_PROPERTY:bintools,strip_command>
-              $<TARGET_PROPERTY:bintools,strip_flag>
-              $<TARGET_PROPERTY:bintools,strip_flag_remove_section>.xt.*
-              $<TARGET_PROPERTY:bintools,strip_flag_infile>${llext_pkg_input}
-              $<TARGET_PROPERTY:bintools,strip_flag_outfile>${llext_pkg_output}
-              $<TARGET_PROPERTY:bintools,strip_flag_final>
-      COMMAND ${slid_inject_cmd}
-      DEPENDS ${llext_proc_target} ${llext_pkg_input}
-    )
-
-  endif()
+  # Remove sections that are unused by the llext loader
+  add_custom_command(
+    OUTPUT ${llext_pkg_output}
+    COMMAND $<TARGET_PROPERTY:bintools,elfconvert_command>
+            $<TARGET_PROPERTY:bintools,elfconvert_flag>
+            $<TARGET_PROPERTY:bintools,elfconvert_flag_strip_unneeded>
+            $<TARGET_PROPERTY:bintools,elfconvert_flag_section_remove>.xt.*
+            $<TARGET_PROPERTY:bintools,elfconvert_flag_infile>${llext_pkg_input}
+            $<TARGET_PROPERTY:bintools,elfconvert_flag_outfile>${llext_pkg_output}
+            $<TARGET_PROPERTY:bintools,elfconvert_flag_final>
+    COMMAND ${slid_inject_cmd}
+    DEPENDS ${llext_proc_target} ${llext_pkg_input}
+  )
 
   # Add user-visible target and dependency, and fill in properties
   get_filename_component(output_name ${llext_pkg_output} NAME)
@@ -5908,7 +5968,7 @@ function(add_llext_command)
   # ARM uses an object file representation so there is no link step.
   if(CONFIG_ARM AND LLEXT_PRE_BUILD)
     message(FATAL_ERROR
-	    "add_llext_command: PRE_BUILD not supported on this arch")
+            "add_llext_command: PRE_BUILD not supported on this arch")
   endif()
 
   # Determine the build step and the target to attach the command to
@@ -5995,7 +6055,7 @@ endfunction()
 # depending on the exact use of the function in script mode.
 #
 # Current Zephyr CMake scripts which includes `extensions.cmake` in script mode
-# are: package_helper.cmake, verify-toolchain.cmake
+# are: package_helper.cmake, verify-toolchain.cmake, llext-edk.cmake
 #
 
 if(CMAKE_SCRIPT_MODE_FILE)
diff --git a/cmake/modules/kconfig.cmake b/cmake/modules/kconfig.cmake
index af8c1e33fa7..d4d22508d0b 100644
--- a/cmake/modules/kconfig.cmake
+++ b/cmake/modules/kconfig.cmake
@@ -24,30 +24,6 @@ set_ifndef(KCONFIG_BINARY_DIR ${CMAKE_CURRENT_BINARY_DIR}/Kconfig)
 set(KCONFIG_BOARD_DIR ${KCONFIG_BINARY_DIR}/boards)
 file(MAKE_DIRECTORY ${KCONFIG_BINARY_DIR})
 
-if(HWMv1)
-  # HWMv1 only supoorts a single board dir which points directly to the board dir.
-  set(KCONFIG_BOARD_DIR ${BOARD_DIR})
-  # Support multiple SOC_ROOT
-  file(MAKE_DIRECTORY ${KCONFIG_BINARY_DIR}/soc)
-  set(kconfig_soc_root ${SOC_ROOT})
-  list(REMOVE_ITEM kconfig_soc_root ${ZEPHYR_BASE})
-  set(soc_defconfig_file ${KCONFIG_BINARY_DIR}/soc/Kconfig.defconfig)
-
-  set(OPERATION WRITE)
-  foreach(root ${kconfig_soc_root})
-    file(APPEND ${soc_defconfig_file}
-         "osource \"${root}/soc/$(ARCH)/*/Kconfig.defconfig\"\n")
-    file(${OPERATION} ${KCONFIG_BINARY_DIR}/soc/Kconfig.soc.choice
-         "osource \"${root}/soc/$(ARCH)/*/Kconfig.soc\"\n"
-    )
-    file(${OPERATION} ${KCONFIG_BINARY_DIR}/soc/Kconfig.soc.arch
-         "osource \"${root}/soc/$(ARCH)/Kconfig\"\n"
-         "osource \"${root}/soc/$(ARCH)/*/Kconfig\"\n"
-    )
-    set(OPERATION APPEND)
-  endforeach()
-endif()
-
 # Support multiple shields in BOARD_ROOT, remove ZEPHYR_BASE as that is always sourced.
 set(kconfig_board_root ${BOARD_ROOT})
 list(REMOVE_ITEM kconfig_board_root ${ZEPHYR_BASE})
@@ -176,20 +152,13 @@ set(COMMON_KCONFIG_ENV_SETTINGS
   ${ZEPHYR_KCONFIG_MODULES_DIR}
 )
 
-if(HWMv1)
-  list(APPEND COMMON_KCONFIG_ENV_SETTINGS
-    ARCH=${ARCH}
-    ARCH_DIR=${ARCH_DIR}
-  )
-else()
-  # For HWMv2 we should in future generate a Kconfig.arch.v2 which instead
-  # glob-sources all arch roots, but for Zephyr itself, the current approach is
-  # sufficient.
-  list(APPEND COMMON_KCONFIG_ENV_SETTINGS
-    ARCH=*
-    ARCH_DIR=${ZEPHYR_BASE}/arch
-  )
-endif()
+# For HWMv2 we should in future generate a Kconfig.arch.v2 which instead
+# glob-sources all arch roots, but for Zephyr itself, the current approach is
+# sufficient.
+list(APPEND COMMON_KCONFIG_ENV_SETTINGS
+  ARCH=*
+  ARCH_DIR=${ZEPHYR_BASE}/arch
+)
 
 # Allow out-of-tree users to add their own Kconfig python frontend
 # targets by appending targets to the CMake list
diff --git a/cmake/modules/kernel.cmake b/cmake/modules/kernel.cmake
index db07a04b921..6bbd564c9e8 100644
--- a/cmake/modules/kernel.cmake
+++ b/cmake/modules/kernel.cmake
@@ -142,8 +142,12 @@ enable_language(ASM)
 # Verify that the toolchain can compile a dummy file, if it is not we
 # won't be able to test for compatibility with certain C flags.
 zephyr_check_compiler_flag(C "" toolchain_is_ok)
+set(log_file "CMakeConfigureLog.yaml")
+if(CMAKE_VERSION VERSION_LESS "3.26.0")
+  set(log_file "CMakeError.log")
+endif()
 assert(toolchain_is_ok "The toolchain is unable to build a dummy C file.\
- Move ${USER_CACHE_DIR}, re-run and look at CMakeError.log")
+ Move ${USER_CACHE_DIR}, re-run and look at ${log_file}")
 
 include(${ZEPHYR_BASE}/cmake/target_toolchain_flags.cmake)
 
diff --git a/cmake/modules/pre_dt.cmake b/cmake/modules/pre_dt.cmake
index 982cdc6e4a7..f8e2a80ec56 100644
--- a/cmake/modules/pre_dt.cmake
+++ b/cmake/modules/pre_dt.cmake
@@ -60,13 +60,9 @@ function(pre_dt_module_run)
   # Finalize DTS_ROOT.
   list(REMOVE_DUPLICATES DTS_ROOT)
 
-  if(HWMv1)
-    set(arch_include dts/${ARCH})
-  else()
-    foreach(arch ${ARCH_V2_NAME_LIST})
-      list(APPEND arch_include dts/${arch})
-    endforeach()
-  endif()
+  foreach(arch ${ARCH_V2_NAME_LIST})
+    list(APPEND arch_include dts/${arch})
+  endforeach()
 
   # Finalize DTS_ROOT_SYSTEM_INCLUDE_DIRS.
   set(DTS_ROOT_SYSTEM_INCLUDE_DIRS)
diff --git a/cmake/modules/python.cmake b/cmake/modules/python.cmake
index ffebec7d5c2..e01d3192120 100644
--- a/cmake/modules/python.cmake
+++ b/cmake/modules/python.cmake
@@ -13,8 +13,6 @@ endif()
 
 set(PYTHON_MINIMUM_REQUIRED 3.10)
 
-find_package(Deprecated COMPONENTS PYTHON_PREFER)
-
 if(NOT DEFINED Python3_EXECUTABLE AND DEFINED WEST_PYTHON)
   set(Python3_EXECUTABLE "${WEST_PYTHON}")
 endif()
diff --git a/cmake/modules/snippets.cmake b/cmake/modules/snippets.cmake
index fba7818c650..b897067667e 100644
--- a/cmake/modules/snippets.cmake
+++ b/cmake/modules/snippets.cmake
@@ -94,7 +94,20 @@ function(zephyr_process_snippets)
     ERROR_VARIABLE output
     RESULT_VARIABLE ret)
   if(${ret})
-    message(FATAL_ERROR "${output}")
+    list(JOIN SNIPPET_ROOT "\n    " snippet_root_paths)
+    set(snippet_root_paths "\n    ${snippet_root_paths}")
+
+    if(SYSBUILD)
+      zephyr_get(SYSBUILD_NAME SYSBUILD GLOBAL)
+      set(extra_output "Snippet roots for image ${SYSBUILD_NAME}:${snippet_root_paths}\n"
+          "Note that snippets will be applied to all images unless prefixed with the image name "
+          "e.g. `-D${SYSBUILD_NAME}_SNIPPET=...`, local snippet roots for one image are not set "
+          "for other images in a build")
+    else()
+      set(extra_output "Snippet roots for application:${snippet_root_paths}")
+    endif()
+
+    message(FATAL_ERROR "${output}" ${extra_output})
   endif()
   include(${snippets_generated})
 
diff --git a/cmake/modules/soc_v2.cmake b/cmake/modules/soc.cmake
similarity index 100%
rename from cmake/modules/soc_v2.cmake
rename to cmake/modules/soc.cmake
diff --git a/cmake/modules/soc_v1.cmake b/cmake/modules/soc_v1.cmake
deleted file mode 100644
index e2004f32255..00000000000
--- a/cmake/modules/soc_v1.cmake
+++ /dev/null
@@ -1,75 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-#
-# Copyright (c) 2021, Nordic Semiconductor ASA
-
-# Configure SoC settings based on Kconfig settings and SoC root.
-#
-# This CMake module will set the following variables in the build system based
-# on Kconfig settings and selected SoC.
-#
-# If no implementation is available for the selected SoC an error will be raised.
-#
-# Outcome:
-# The following variables will be defined when this CMake module completes:
-#
-# - SOC_NAME:   Name of the SoC in use, identical to CONFIG_SOC
-# - SOC_SERIES: Name of the SoC series in use, identical to CONFIG_SOC_SERIES
-# - SOC_FAMILY: Name of the SoC family, identical to CONFIG_SOC_FAMILY
-# - SOC_PATH:   Path fragment defined by either SOC_NAME or SOC_FAMILY/SOC_SERIES.
-# - SOC_DIR:    Directory containing the SoC implementation
-# - SOC_ROOT:   SOC_ROOT with ZEPHYR_BASE appended
-#
-# Variable dependencies:
-# - SOC_ROOT: CMake list of SoC roots containing SoC implementations
-#
-# Variables set by this module and not mentioned above are considered internal
-# use only and may be removed, renamed, or re-purposed without prior notice.
-
-include_guard(GLOBAL)
-
-include(kconfig)
-
-if(HWMv1)
-  # 'SOC_ROOT' is a prioritized list of directories where socs may be
-  # found. It always includes ${ZEPHYR_BASE}/soc at the lowest priority.
-  list(APPEND SOC_ROOT ${ZEPHYR_BASE})
-
-  set(SOC_NAME   ${CONFIG_SOC})
-  set(SOC_SERIES ${CONFIG_SOC_SERIES})
-  set(SOC_TOOLCHAIN_NAME ${CONFIG_SOC_TOOLCHAIN_NAME})
-  set(SOC_FAMILY ${CONFIG_SOC_FAMILY})
-
-  if("${SOC_SERIES}" STREQUAL "")
-    set(SOC_PATH ${SOC_NAME})
-  else()
-    set(SOC_PATH ${SOC_FAMILY}/${SOC_SERIES})
-  endif()
-
-  # Use SOC to search for a 'CMakeLists.txt' file.
-  # e.g. zephyr/soc/xtensa/intel_adsp/CMakeLists.txt.
-  foreach(root ${SOC_ROOT})
-    # Check that the root looks reasonable.
-    if(NOT IS_DIRECTORY "${root}/soc")
-      message(WARNING "\nSOC_ROOT element(s) without a 'soc' subdirectory:
-  ${root}
-  Hints:
-    - if your SoC family directory is '/foo/bar/soc/<ARCH>/my_soc_family', then add '/foo/bar' to SOC_ROOT, not the entire SoC family path
-    - if in doubt, use absolute paths\n")
-    endif()
-
-    if(EXISTS ${root}/soc/${ARCH}/${SOC_PATH})
-      set(SOC_DIR ${root}/soc)
-      break()
-    endif()
-  endforeach()
-
-  if(NOT SOC_DIR)
-    message(FATAL_ERROR "Could not find SOC=${SOC_NAME} for BOARD=${BOARD},\n"
-            "please check your installation.\n"
-            "SOC roots searched:\n"
-            "${SOC_ROOT}\n"
-    )
-  endif()
-
-  set(SOC_FULL_DIR ${SOC_DIR}/${ARCH}/${SOC_PATH})
-endif()
diff --git a/cmake/modules/unittest.cmake b/cmake/modules/unittest.cmake
index d981559ea65..4c80283aa0e 100644
--- a/cmake/modules/unittest.cmake
+++ b/cmake/modules/unittest.cmake
@@ -12,8 +12,8 @@ include(hwm_v2)
 include(configuration_files)
 
 include(kconfig)
-include(arch_v2)
-include(soc_v2)
+include(arch)
+include(soc)
 
 find_package(TargetTools)
 
@@ -44,8 +44,6 @@ if((NOT DEFINED ZEPHYR_BASE) AND (DEFINED ENV_ZEPHYR_BASE))
   set(ZEPHYR_BASE ${ENV_ZEPHYR_BASE} CACHE PATH "Zephyr base")
 endif()
 
-find_package(Deprecated COMPONENTS SOURCES)
-
 if(NOT SOURCES AND EXISTS main.c)
   set(SOURCES main.c)
 endif()
@@ -162,6 +160,13 @@ if(VALGRIND_PROGRAM)
     )
 endif()
 
+add_custom_target(run
+  COMMAND
+  $<TARGET_FILE:testbinary>
+  DEPENDS testbinary
+  WORKING_DIRECTORY ${APPLICATION_BINARY_DIR}
+  )
+
 add_custom_target(run-test
   COMMAND
   ${VALGRIND} ${VALGRIND_FLAGS}
diff --git a/cmake/modules/version.cmake b/cmake/modules/version.cmake
index d35b3be0623..b3a9a3c937b 100644
--- a/cmake/modules/version.cmake
+++ b/cmake/modules/version.cmake
@@ -63,7 +63,7 @@ foreach(type file IN ZIP_LISTS VERSION_TYPE VERSION_FILE)
   string(REGEX MATCH "VERSION_TWEAK = ([0-9]*)" _ ${ver})
   set(${type}_VERSION_TWEAK ${CMAKE_MATCH_1})
 
-  string(REGEX MATCH "EXTRAVERSION = ([a-z0-9]*)" _ ${ver})
+  string(REGEX MATCH "EXTRAVERSION = ([a-z0-9\.\-]*)" _ ${ver})
   set(${type}_VERSION_EXTRA ${CMAKE_MATCH_1})
 
   # Validate all version fields fit in a single byte
diff --git a/cmake/modules/yaml.cmake b/cmake/modules/yaml.cmake
index a509567bc5d..17afcd0ef0b 100644
--- a/cmake/modules/yaml.cmake
+++ b/cmake/modules/yaml.cmake
@@ -96,13 +96,6 @@ function(internal_yaml_list_append var genex key)
       internal_yaml_list_initializer(subjson TRUE)
       if(${arraylength} GREATER 0)
         math(EXPR arraystop "${arraylength} - 1")
-        list(GET ARG_YAML_LIST 0 entry_0)
-        if(entry_0 STREQUAL MAP)
-          message(FATAL_ERROR "${function}(GENEX ${argument} ) is not valid at this position.\n"
-                    "Syntax is 'LIST MAP \"key1: value1.1, ...\" MAP \"key1: value1.2, ...\""
-            )
-        endif()
-
         foreach(i RANGE 0 ${arraystop})
           string(JSON item GET "${json_content}" ${key} ${i})
           list(APPEND subjson ${item})
@@ -129,12 +122,12 @@ function(internal_yaml_list_append var genex key)
           endif()
           list(POP_FRONT ARG_YAML_LIST map_value)
           string(REGEX REPLACE "([^\\])," "\\1;" pair_list "${map_value}")
-          set(qouted_map_value)
+          set(quoted_map_value)
           foreach(pair ${pair_list})
             if(NOT pair MATCHES "[^ ]*:[^ ]*")
               message(FATAL_ERROR "yaml_set(MAP ${map_value} ) is malformed.\n"
                     "Syntax is 'LIST MAP \"key1: value1.1, ...\" MAP \"key1: value1.2, ...\"\n"
-                    "If value contains comma ',' then ensure the value field is properly qouted "
+                    "If value contains comma ',' then ensure the value field is properly quoted "
                     "and escaped"
               )
             endif()
@@ -145,10 +138,10 @@ function(internal_yaml_list_append var genex key)
               message(FATAL_ERROR "value: ${value} is not properly quoted")
             endif()
             string(REGEX REPLACE "\\\\," "," value "${value}")
-            list(APPEND qouted_map_value "\"${map_key}\": \"${value}\"")
+            list(APPEND quoted_map_value "\"${map_key}\": \"${value}\"")
           endforeach()
-          list(JOIN qouted_map_value "," qouted_map_value)
-          string(JSON json_content SET "${json_content}" ${key} ${i} "{${qouted_map_value}}")
+          list(JOIN quoted_map_value "," quoted_map_value)
+          string(JSON json_content SET "${json_content}" ${key} ${i} "{${quoted_map_value}}")
         endforeach()
       else()
         math(EXPR stop "${index} + ${length} - 1")
@@ -491,7 +484,11 @@ function(yaml_save)
 
   zephyr_get_scoped(genex ${ARG_YAML_NAME} GENEX)
   zephyr_get_scoped(json_content ${ARG_YAML_NAME} JSON)
-  to_yaml("${json_content}" 0 yaml_out ${genex})
+  if(genex)
+    to_yaml("${json_content}" 0 yaml_out DIRECT_GENEX)
+   else()
+    to_yaml("${json_content}" 0 yaml_out DIRECT)
+   endif()
 
   if(EXISTS ${yaml_file})
     FILE(RENAME ${yaml_file} ${yaml_file}.bak)
@@ -499,7 +496,7 @@ function(yaml_save)
   FILE(WRITE ${yaml_file} "${yaml_out}")
 
   set(save_target ${ARG_YAML_NAME}_yaml_saved)
-  if (NOT TARGET ${save_target})
+  if(NOT TARGET ${save_target})
     # Create a target for the completion of the YAML save operation.
     # This will be a dummy unless genexes are used.
     add_custom_target(${save_target} ALL DEPENDS ${yaml_file})
@@ -509,16 +506,16 @@ function(yaml_save)
     )
   endif()
 
-  if (genex)
+  if(genex)
     get_property(genex_save_count TARGET ${save_target} PROPERTY genex_save_count)
-    if (${genex_save_count} EQUAL 0)
+    if(${genex_save_count} EQUAL 0)
       # First yaml_save() for this context with genexes enabled
       add_custom_command(
         OUTPUT ${yaml_file}
-        DEPENDS $<TARGET_PROPERTY:${save_target},json_file>
+        DEPENDS $<TARGET_PROPERTY:${save_target},expanded_file>
         COMMAND ${CMAKE_COMMAND}
-                -DJSON_FILE="$<TARGET_PROPERTY:${save_target},json_file>"
-                -DYAML_FILE="${yaml_file}"
+                -DEXPANDED_FILE="$<TARGET_PROPERTY:${save_target},expanded_file>"
+                -DOUTPUT_FILE="${yaml_file}"
                 -DTEMP_FILES="$<TARGET_PROPERTY:${save_target},temp_files>"
                 -P ${ZEPHYR_BASE}/cmake/yaml-filter.cmake
       )
@@ -529,21 +526,45 @@ function(yaml_save)
 
     cmake_path(SET yaml_path "${yaml_file}")
     cmake_path(GET yaml_path STEM yaml_file_no_ext)
-    set(json_file ${yaml_file_no_ext}_${genex_save_count}.json)
-    set_property(TARGET ${save_target} PROPERTY json_file ${json_file})
+    set(expanded_file ${yaml_file_no_ext}_${genex_save_count}.yaml)
+    set_property(TARGET ${save_target} PROPERTY expanded_file ${expanded_file})
 
-    # comment this to keep the temporary JSON files
-    set_property(TARGET ${save_target} APPEND PROPERTY temp_files ${json_file})
+    # comment this to keep the temporary files
+    set_property(TARGET ${save_target} APPEND PROPERTY temp_files ${expanded_file})
 
-    FILE(GENERATE OUTPUT ${json_file}
-      CONTENT "${json_content}"
-    )
+    to_yaml("${json_content}" 0 yaml_out TEMP_GENEX)
+    FILE(GENERATE OUTPUT ${expanded_file} CONTENT "${yaml_out}")
+    FILE(TOUCH ${expanded_file}) # ensure timestamp is updated even if nothing changed
   endif()
 endfunction()
 
-function(to_yaml in_json level yaml genex)
-  zephyr_string(ESCAPE json "${in_json}")
-  if(level GREATER 0)
+function(to_yaml json level yaml mode)
+  if(mode STREQUAL "DIRECT")
+    # Direct output mode, no genexes: write a standard YAML
+    set(expand_lists TRUE)
+    set(escape_quotes TRUE)
+    set(comment_genexes FALSE)
+  elseif(mode STREQUAL "DIRECT_GENEX" OR mode STREQUAL "FINAL_GENEX")
+    # Direct output mode with genexes enabled, or final write of post-processed
+    # file: write a standard YAML, comment entries with genexes if they are
+    # (still) present in the file
+    set(expand_lists TRUE)
+    set(escape_quotes TRUE)
+    set(comment_genexes TRUE)
+  elseif(mode STREQUAL "TEMP_GENEX")
+    # Temporary output mode for genex expansion: save single quotes with no
+    # special processing, since they will be fixed up by yaml-filter.cmake
+    set(expand_lists FALSE)
+    set(escape_quotes FALSE)
+    set(comment_genexes FALSE)
+  else()
+    message(FATAL_ERROR "to_yaml(... ${mode} ) is malformed.")
+  endif()
+
+  if(level EQUAL 0)
+    # Top-level call, initialize the YAML output variable
+    set(${yaml} "" PARENT_SCOPE)
+  else()
     math(EXPR level_dec "${level} - 1")
     set(indent_${level} "${indent_${level_dec}}  ")
   endif()
@@ -564,7 +585,7 @@ function(to_yaml in_json level yaml genex)
       # JSON object -> YAML dictionary
       set(${yaml} "${${yaml}}${indent_${level}}${member}:\n")
       math(EXPR sublevel "${level} + 1")
-      to_yaml("${subjson}" ${sublevel} ${yaml} ${genex})
+      to_yaml("${subjson}" ${sublevel} ${yaml} ${mode})
     elseif(type STREQUAL ARRAY)
       # JSON array -> YAML list
       set(${yaml} "${${yaml}}${indent_${level}}${member}:")
@@ -581,12 +602,16 @@ function(to_yaml in_json level yaml genex)
           string(JSON length ERROR_VARIABLE ignore LENGTH "${item}")
           if(length)
             set(non_indent_yaml)
-            to_yaml("${item}" 0 non_indent_yaml FALSE)
+            to_yaml("${item}" 0 non_indent_yaml ${mode})
             string(REGEX REPLACE "\n$" "" non_indent_yaml "${non_indent_yaml}")
             string(REPLACE "\n" "\n${indent_${level}}   " indent_yaml "${non_indent_yaml}")
             set(${yaml} "${${yaml}}${indent_${level}} - ${indent_yaml}\n")
           else()
-            set(${yaml} "${${yaml}}${indent_${level}} - ${item}\n")
+            # Assume a string, escape single quotes when required (see comment below).
+            if(escape_quotes)
+              string(REPLACE "'" "''" item "${item}")
+            endif()
+            set(${yaml} "${${yaml}}${indent_${level}} - '${item}'\n")
           endif()
         endforeach()
       endif()
@@ -595,11 +620,17 @@ function(to_yaml in_json level yaml genex)
       # - with unexpanded generator expressions: save as YAML comment
       # - if it matches the special prefix: convert to YAML list
       # - otherwise: save as YAML scalar
-      if (subjson MATCHES "\\$<.*>" AND ${genex})
+      # Single quotes must be escaped in the value _unless_ this will be used
+      # to expand generator expressions, because then the escaping will be
+      # addressed once in the yaml-filter.cmake script.
+      if(escape_quotes)
+        string(REPLACE "'" "''" subjson "${subjson}")
+      endif()
+      if(subjson MATCHES "\\$<.*>" AND comment_genexes)
         # Yet unexpanded generator expression: save as comment
         string(SUBSTRING ${indent_${level}} 1 -1 short_indent)
-        set(${yaml} "${${yaml}}#${short_indent}${member}: ${subjson}\n")
-      elseif(subjson MATCHES "^@YAML-LIST@")
+        set(${yaml} "${${yaml}}#${short_indent}${member}: '${subjson}'\n")
+      elseif(subjson MATCHES "^@YAML-LIST@" AND expand_lists)
         # List-as-string: convert to list
         set(${yaml} "${${yaml}}${indent_${level}}${member}:")
         list(POP_FRONT subjson)
@@ -608,12 +639,12 @@ function(to_yaml in_json level yaml genex)
         else()
           set(${yaml} "${${yaml}}\n")
           foreach(item ${subjson})
-            set(${yaml} "${${yaml}}${indent_${level}} - ${item}\n")
+            set(${yaml} "${${yaml}}${indent_${level}} - '${item}'\n")
           endforeach()
         endif()
       else()
         # Raw strings: save as is
-        set(${yaml} "${${yaml}}${indent_${level}}${member}: ${subjson}\n")
+        set(${yaml} "${${yaml}}${indent_${level}}${member}: '${subjson}'\n")
       endif()
     else()
       # Other JSON data type -> YAML scalar, as-is
diff --git a/cmake/modules/zephyr_default.cmake b/cmake/modules/zephyr_default.cmake
index 2afef934057..087e9d77c6d 100644
--- a/cmake/modules/zephyr_default.cmake
+++ b/cmake/modules/zephyr_default.cmake
@@ -97,7 +97,6 @@ list(APPEND zephyr_cmake_modules zephyr_module)
 list(APPEND zephyr_cmake_modules boards)
 list(APPEND zephyr_cmake_modules shields)
 list(APPEND zephyr_cmake_modules snippets)
-list(APPEND zephyr_cmake_modules arch_v1)
 list(APPEND zephyr_cmake_modules hwm_v2)
 list(APPEND zephyr_cmake_modules configuration_files)
 list(APPEND zephyr_cmake_modules generated_file_directories)
@@ -110,9 +109,8 @@ list(APPEND zephyr_cmake_modules "\${pre_dt_board}")
 # kconfig and dts should be available at the same time.
 list(APPEND zephyr_cmake_modules dts)
 list(APPEND zephyr_cmake_modules kconfig)
-list(APPEND zephyr_cmake_modules arch_v2)
-list(APPEND zephyr_cmake_modules soc_v1)
-list(APPEND zephyr_cmake_modules soc_v2)
+list(APPEND zephyr_cmake_modules arch)
+list(APPEND zephyr_cmake_modules soc)
 
 foreach(component ${SUB_COMPONENTS})
   if(NOT ${component} IN_LIST zephyr_cmake_modules)
diff --git a/cmake/sca/gcc/sca.cmake b/cmake/sca/gcc/sca.cmake
index c106933c101..4d0bf491e57 100644
--- a/cmake/sca/gcc/sca.cmake
+++ b/cmake/sca/gcc/sca.cmake
@@ -1,5 +1,36 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 # Copyright (c) 2024 Intel Corporation
+# Copyright (c) 2025 Alex Fabre
 
+# Check GCC version
+# GCC static analyzer requires GCC version >= 10.0.0
+if("${GCC_COMPILER_VERSION}" VERSION_LESS 10.0.0)
+  message(FATAL_ERROR "GCC static analyzer requires GCC >= v10.0")
+endif()
+
+
+# Enable GCC static analyzer
 list(APPEND TOOLCHAIN_C_FLAGS -fanalyzer)
+
+# Add GCC analyzer user options
+zephyr_get(GCC_SCA_OPTS)
+zephyr_get(USE_CCACHE)
+
+if(DEFINED GCC_SCA_OPTS)
+  foreach(analyzer_option IN LISTS GCC_SCA_OPTS)
+
+    if(analyzer_option STREQUAL "-fdiagnostics-format=sarif-file" OR analyzer_option STREQUAL "-fdiagnostics-format=json-file")
+      # Beginning with GCC 14, users can use the -fdiagnostics-format option
+      # to output analyzer diagnostics as SARIF or JSON files.
+      # This option encounters a specific issue[1] when used with ccache.
+      # Therefore, currently, the build process is halted if 'ccache' is enabled.
+      # [1] https://github.com/ccache/ccache/issues/1466
+      if(NOT USE_CCACHE STREQUAL "0")
+        message(FATAL_ERROR "GCC SCA requires 'ccache' to be disabled for output file generation. Disable 'ccache' by setting USE_CCACHE=0.")
+      endif()
+    endif()
+
+    list(APPEND TOOLCHAIN_C_FLAGS ${analyzer_option})
+  endforeach()
+endif()
diff --git a/cmake/toolchain/iar/Kconfig b/cmake/toolchain/iar/Kconfig
new file mode 100644
index 00000000000..056fa5d499f
--- /dev/null
+++ b/cmake/toolchain/iar/Kconfig
@@ -0,0 +1,40 @@
+# Copyright (c) 2025 IAR Systems AB
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config LD_LINKER_SCRIPT_SUPPORTED
+	default n
+
+choice LINKER_SCRIPT
+	default CMAKE_LINKER_GENERATOR
+endchoice
+
+menu "IAR library options"
+
+config IAR_SEMIHOSTING
+	bool "Use the IAR semihosting implementation."
+	depends on IAR_LIBC
+	help
+	  Use the semihosting implementation in the IAR library
+	  instead of the Zephyr implementation.
+
+config IAR_BUFFERED_WRITE
+	bool "Use buffered write"
+	depends on IAR_SEMIHOSTING
+	help
+	  Instead of printing one character at a time
+	  this option uses a buffer to print a line
+	  at a time instead, increasing speed of printout.
+
+endmenu
+
+config TOOLCHAIN_IAR_SUPPORTS_THREAD_LOCAL_STORAGE
+	def_bool y
+	select TOOLCHAIN_SUPPORTS_THREAD_LOCAL_STORAGE
+
+# Should we set this? It doesn't seem to be used
+# We support most but don't set __GNUC__
+#
+config TOOLCHAIN_IAR_SUPPORTS_GNU_EXTENSIONS
+	def_bool y
+	select TOOLCHAIN_SUPPORTS_GNU_EXTENSIONS
diff --git a/cmake/toolchain/iar/Kconfig.defconfig b/cmake/toolchain/iar/Kconfig.defconfig
new file mode 100644
index 00000000000..64d78470c75
--- /dev/null
+++ b/cmake/toolchain/iar/Kconfig.defconfig
@@ -0,0 +1,46 @@
+# Copyright (c) 2025 IAR Systems AB
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config TOOLCHAIN_SUPPORTS_VLA_IN_STATEMENTS
+	default n
+
+config PICOLIBC_SUPPORTED
+	default n
+
+config IAR_LIBC_SUPPORTED
+	default y
+
+config COMPILER_FREESTANDING
+	default y
+
+config CBPRINTF_LIBC_SUBSTS
+	default y
+
+# IAR has slightly different types
+config ENFORCE_ZEPHYR_STDINT
+	default n
+
+# IAR uses a little bit more stack than GCC
+config TEST_EXTRA_STACK_SIZE
+	default 64
+
+# ICCARM does not support relaxation
+config LINKER_USE_NO_RELAX
+	default y
+
+# ICCARM support C17 with some additional features from C23
+config REQUIRES_STD_C17
+	default y
+
+config CODING_GUIDELINE_CHECK
+	default n
+	help
+	  Not applicable to ICCARM
+
+config TC_PROVIDES_POSIX_C_LANG_SUPPORT_R
+	default n
+
+# ICCARM does not support <threads.h>
+config COMMON_LIBC_THRD
+	default n
diff --git a/cmake/toolchain/iar/generic.cmake b/cmake/toolchain/iar/generic.cmake
new file mode 100644
index 00000000000..645ba19ecb9
--- /dev/null
+++ b/cmake/toolchain/iar/generic.cmake
@@ -0,0 +1,46 @@
+# Copyright (c) 2025 IAR Systems AB
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_get(IAR_TOOLCHAIN_PATH)
+assert(IAR_TOOLCHAIN_PATH "IAR_TOOLCHAIN_PATH is not set")
+
+set(IAR_TOOLCHAIN_VARIANT none)
+if(NOT EXISTS ${IAR_TOOLCHAIN_PATH})
+  message(FATAL_ERROR "Nothing found at IAR_TOOLCHAIN_PATH: '${IAR_TOOLCHAIN_PATH}'")
+endif()
+
+if(EXISTS ${IAR_TOOLCHAIN_PATH}/bin/iccarm)
+  message(STATUS "Found toolchain: IAR C/C++ Compiler for Arm (${IAR_TOOLCHAIN_PATH})")
+  set(IAR_COMPILER iccarm)
+  set(IAR_LINKER ilinkarm)
+elseif(EXISTS ${IAR_TOOLCHAIN_PATH}/bin/iccarm.exe)
+  message(STATUS "Found toolchain: IAR C/C++ Compiler for Arm (${IAR_TOOLCHAIN_PATH})")
+  set(IAR_COMPILER iccarm)
+  set(IAR_LINKER ilinkarm)
+endif()
+
+set(IAR_TOOLCHAIN_VARIANT ${IAR_COMPILER})
+
+# iar relies on Zephyr SDK for the use of C preprocessor (devicetree) and objcopy
+find_package(Zephyr-sdk 0.16 REQUIRED)
+message(STATUS "Found Zephyr SDK at ${ZEPHYR_SDK_INSTALL_DIR}")
+
+set(TOOLCHAIN_HOME ${IAR_TOOLCHAIN_PATH})
+
+# Handling to be improved in Zephyr SDK, to avoid overriding ZEPHYR_TOOLCHAIN_VARIANT by
+# find_package(Zephyr-sdk) if it's already set
+set(ZEPHYR_TOOLCHAIN_VARIANT iar)
+
+set(COMPILER iar)
+set(LINKER iar)
+set(BINTOOLS iar)
+
+if("${IAR_TOOLCHAIN_VARIANT}" STREQUAL "iccarm")
+  set(SYSROOT_TARGET arm)
+else()
+  set(SYSROOT_TARGET riscv)
+endif()
+set(CROSS_COMPILE ${TOOLCHAIN_HOME}/bin/)
+
+set(TOOLCHAIN_HAS_NEWLIB OFF CACHE BOOL "True if toolchain supports NewLib")
diff --git a/cmake/toolchain/iar/target.cmake b/cmake/toolchain/iar/target.cmake
new file mode 100644
index 00000000000..b11635894a6
--- /dev/null
+++ b/cmake/toolchain/iar/target.cmake
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 IAR Systems AB
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Intentionally left blank.
diff --git a/cmake/toolchain/xtools/Kconfig b/cmake/toolchain/xtools/Kconfig
deleted file mode 100644
index c96baacbcc7..00000000000
--- a/cmake/toolchain/xtools/Kconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-# Copyright © 2022 Keith Packard
-# SPDX-License-Identifier: Apache-2.0
-
-config TOOLCHAIN_XTOOLS_SUPPORTS_THREAD_LOCAL_STORAGE
-	def_bool y
-	select TOOLCHAIN_SUPPORTS_THREAD_LOCAL_STORAGE
-
-config NEWLIB_LIBC_SUPPORTED
-	def_bool y
-	help
-	  Crosstools is assumed to support newlib for C and C++ development.
diff --git a/cmake/toolchain/xtools/generic.cmake b/cmake/toolchain/xtools/generic.cmake
deleted file mode 100644
index be0075adede..00000000000
--- a/cmake/toolchain/xtools/generic.cmake
+++ /dev/null
@@ -1,41 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-find_package(Deprecated COMPONENTS XTOOLS)
-
-zephyr_get(XTOOLS_TOOLCHAIN_PATH)
-assert(    XTOOLS_TOOLCHAIN_PATH      "XTOOLS_TOOLCHAIN_PATH is not set")
-
-set(TOOLCHAIN_HOME ${XTOOLS_TOOLCHAIN_PATH})
-
-set(COMPILER gcc)
-set(LINKER ld)
-set(BINTOOLS gnu)
-
-# Choose one of the toolchains in 'TOOLCHAIN_HOME' at random to use as
-# a 'generic' toolchain until we know for sure which toolchain we
-# should use. Note that we can't use ARCH to distinguish between
-# toolchains because choosing between iamcu and non-iamcu is dependent
-# on Kconfig, not ARCH.
-if("${ARCH}" STREQUAL "xtensa")
-  file(GLOB toolchain_paths ${TOOLCHAIN_HOME}/xtensa/*/*)
-else()
-  file(GLOB toolchain_paths ${TOOLCHAIN_HOME}/*)
-endif()
-list(REMOVE_ITEM toolchain_paths ${TOOLCHAIN_HOME}/sources)
-list(GET  toolchain_paths 0 some_toolchain_path)
-
-get_filename_component(some_toolchain_root "${some_toolchain_path}" DIRECTORY)
-get_filename_component(some_toolchain "${some_toolchain_path}" NAME)
-
-set(CROSS_COMPILE_TARGET ${some_toolchain})
-
-set(SYSROOT_TARGET ${CROSS_COMPILE_TARGET})
-
-set(CROSS_COMPILE ${some_toolchain_root}/${CROSS_COMPILE_TARGET}/bin/${CROSS_COMPILE_TARGET}-)
-set(SYSROOT_DIR   ${some_toolchain_root}/${SYSROOT_TARGET}/${SYSROOT_TARGET})
-set(TOOLCHAIN_HAS_NEWLIB ON CACHE BOOL "True if toolchain supports newlib")
-
-unset(some_toolchain_root)
-unset(some_toolchain)
-
-message(STATUS "Found toolchain: xtools (${XTOOLS_TOOLCHAIN_PATH})")
diff --git a/cmake/toolchain/xtools/target.cmake b/cmake/toolchain/xtools/target.cmake
deleted file mode 100644
index fab28b7463c..00000000000
--- a/cmake/toolchain/xtools/target.cmake
+++ /dev/null
@@ -1,32 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-set(CROSS_COMPILE_TARGET_arm        arm-zephyr-eabi)
-set(CROSS_COMPILE_TARGET_arm64   aarch64-zephyr-elf)
-set(CROSS_COMPILE_TARGET_nios2     nios2-zephyr-elf)
-set(CROSS_COMPILE_TARGET_riscv   riscv64-zephyr-elf)
-set(CROSS_COMPILE_TARGET_mips     mipsel-zephyr-elf)
-set(CROSS_COMPILE_TARGET_xtensa   xtensa-zephyr-elf)
-set(CROSS_COMPILE_TARGET_arc         arc-zephyr-elf)
-set(CROSS_COMPILE_TARGET_x86      x86_64-zephyr-elf)
-set(CROSS_COMPILE_TARGET_sparc     sparc-zephyr-elf)
-
-set(CROSS_COMPILE_TARGET ${CROSS_COMPILE_TARGET_${ARCH}})
-set(SYSROOT_TARGET       ${CROSS_COMPILE_TARGET})
-
-if("${ARCH}" STREQUAL "xtensa")
-  set(SYSROOT_DIR ${TOOLCHAIN_HOME}/xtensa/${SOC_NAME}/${SYSROOT_TARGET})
-  set(CROSS_COMPILE ${TOOLCHAIN_HOME}/xtensa/${SOC_NAME}/${CROSS_COMPILE_TARGET}/bin/${CROSS_COMPILE_TARGET}-)
-else()
-  set(SYSROOT_DIR   ${TOOLCHAIN_HOME}/${SYSROOT_TARGET}/${SYSROOT_TARGET})
-  set(CROSS_COMPILE ${TOOLCHAIN_HOME}/${CROSS_COMPILE_TARGET}/bin/${CROSS_COMPILE_TARGET}-)
-endif()
-
-if("${ARCH}" STREQUAL "x86")
-  if(CONFIG_X86_64)
-    list(APPEND TOOLCHAIN_C_FLAGS -m64)
-    list(APPEND TOOLCHAIN_LD_FLAGS -m64)
-  else()
-    list(APPEND TOOLCHAIN_C_FLAGS -m32)
-    list(APPEND TOOLCHAIN_LD_FLAGS -m32)
-  endif()
-endif()
diff --git a/cmake/yaml-filter.cmake b/cmake/yaml-filter.cmake
index c7733be6485..9873514d0c0 100644
--- a/cmake/yaml-filter.cmake
+++ b/cmake/yaml-filter.cmake
@@ -1,21 +1,28 @@
 # Copyright (c) 2024 Arduino SA
 # SPDX-License-Identifier: Apache-2.0
 
-# Simple second stage filter for YAML generation, used when generator
-# expressions have been used for some of the data and the conversion to
-# YAML needs to happen after cmake has completed processing.
+# Second stage filter for YAML generation, called when generator expressions
+# have been used in some of the data and cleanup needs to happen after CMake
+# has completed processing.
 #
-# This scripts expects as input:
-# - JSON_FILE: the name of the input file, in JSON format, that contains
-#              the expanded generator expressions.
-# - YAML_FILE: the name of the final output YAML file.
+# Two issues are addressed here:
+#
+#  - the intermediate YAML may have non-escaped single quotes in its strings.
+#    These may have been introduced directly via yaml_set() in the main CMake
+#    script or by some generator expressions; at this stage they are however
+#    finalized and can be escaped in one single pass.
+#
+#  - in the input YAML, lists have been stored as a CMake-format string to
+#    allow generator expressions to seamlessly expand into multiple items.
+#    These now need to be converted back into a proper YAML list.
+#
+# This scripts expects as input the following variables:
+#
+# - EXPANDED_FILE: the name of the file that contains the expanded generator
+#                  expressions.
+# - OUTPUT_FILE: the name of the final output YAML file.
 # - TEMP_FILES: a list of temporary files that need to be removed after
 #               the conversion is done.
-#
-# This script loads the Zephyr yaml module and reuses its `to_yaml()`
-# function to convert the fully expanded JSON content to YAML, taking
-# into account the special format that was used to store lists.
-# Temporary files are then removed.
 
 cmake_minimum_required(VERSION 3.20.0)
 
@@ -23,13 +30,40 @@ set(ZEPHYR_BASE ${CMAKE_CURRENT_LIST_DIR}/../)
 list(APPEND CMAKE_MODULE_PATH "${CMAKE_CURRENT_LIST_DIR}/modules")
 include(yaml)
 
-file(READ ${JSON_FILE} json_content)
-to_yaml("${json_content}" 0 yaml_out TRUE)
-file(WRITE ${YAML_FILE} "${yaml_out}")
+# Fix all quotes in the input YAML file. Strings in it will be in one of the
+# following formats:
+#
+#   name: 'string with 'single quotes' in it'
+#       - 'string with 'single quotes' in it'
+#
+# To address this, every single quote is duplicated, then the first and last
+# occurrences of two single quotes are removed (they are the string beginning
+# and end markers). The result is written to a temporary file.
+file(STRINGS ${EXPANDED_FILE} yaml_content)
+foreach(line ${yaml_content})
+  string(REPLACE "'" "''" line "${line}") # escape every single quote in the string
+  string(REGEX REPLACE "^([^']* )''" "\\1'" line "${line}") # fix opening quote
+  string(REGEX REPLACE "''$" "'" line "${line}") # fix closing quote
+  # semicolons in the string are not to be confused with string separators
+  string(REPLACE ";" "\\;" line "${line}")
+  list(APPEND tmp_content "${line}")
+endforeach()
+list(JOIN tmp_content "\n" tmp_content)
+file(WRITE ${EXPANDED_FILE}.tmp "${tmp_content}")
+
+# Load the now-fixed YAML file and convert the CMake-format lists back into
+# proper YAML format using the to_yaml() function. The result is written to
+# the final destination file.
+yaml_load(FILE ${EXPANDED_FILE}.tmp NAME yaml_saved)
+zephyr_get_scoped(json_content yaml_saved JSON)
+to_yaml("${json_content}" 0 yaml_out FINAL_GENEX)
+file(WRITE ${OUTPUT_FILE} "${yaml_out}")
 
-# Remove unused temporary files. JSON_FILE needs to be kept, or the
-# build system will complain there is no rule to rebuild it
-list(REMOVE_ITEM TEMP_FILES ${JSON_FILE})
+# Remove unused temporary files. EXPANDED_FILE needs to be kept, or the
+# build system will complain there is no rule to rebuild it, but the
+# .tmp file that was just created can be removed.
+list(REMOVE_ITEM TEMP_FILES ${EXPANDED_FILE})
+list(APPEND TEMP_FILES ${EXPANDED_FILE}.tmp)
 foreach(file ${TEMP_FILES})
   file(REMOVE ${file})
 endforeach()
diff --git a/doc/CMakeLists.txt b/doc/CMakeLists.txt
index bcabb520a79..cb54555824d 100644
--- a/doc/CMakeLists.txt
+++ b/doc/CMakeLists.txt
@@ -16,6 +16,7 @@ set(SPHINXOPTS "-j auto -W --keep-going -T" CACHE STRING "Default Sphinx Options
 set(SPHINXOPTS_EXTRA "" CACHE STRING "Extra Sphinx Options (added to defaults)")
 set(LATEXMKOPTS "-halt-on-error -no-shell-escape" CACHE STRING "Default latexmk options")
 set(DT_TURBO_MODE OFF CACHE BOOL "Enable DT turbo mode")
+set(HW_FEATURES_TURBO_MODE OFF CACHE BOOL "Enable HW features turbo mode")
 set(DOC_TAG "development" CACHE STRING "Documentation tag")
 set(DTS_ROOTS "${ZEPHYR_BASE}" CACHE STRING "DT bindings root folders")
 
@@ -149,6 +150,16 @@ set_property(DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS ${GEN_DEVICETREE_
 #-------------------------------------------------------------------------------
 # html
 
+set(SPHINX_TAGS "${DOC_TAG}")
+if(HW_FEATURES_TURBO_MODE)
+  list(APPEND SPHINX_TAGS "hw_features_turbo")
+endif()
+
+set(SPHINX_TAGS_ARGS "")
+foreach(tag ${SPHINX_TAGS})
+  list(APPEND SPHINX_TAGS_ARGS "-t" "${tag}")
+endforeach()
+
 add_doc_target(
   html
   COMMAND ${CMAKE_COMMAND} -E env ${SPHINX_ENV} OUTPUT_DIR=${DOCS_HTML_DIR}
@@ -157,7 +168,7 @@ add_doc_target(
     -c ${DOCS_CFG_DIR}
     -d ${DOCS_DOCTREE_DIR}
     -w ${DOCS_BUILD_DIR}/html.log
-    -t ${DOC_TAG}
+    ${SPHINX_TAGS_ARGS}
     ${SPHINXOPTS}
     ${SPHINXOPTS_EXTRA}
     ${DOCS_SRC_DIR}
@@ -179,7 +190,7 @@ add_dependencies(html devicetree)
 
 add_doc_target(
   html-live
-  COMMAND ${CMAKE_COMMAND} -E env ${SPHINX_ENV}
+  COMMAND ${CMAKE_COMMAND} -E env ${SPHINX_ENV} OUTPUT_DIR=${DOCS_HTML_DIR}
   ${SPHINXAUTOBUILD}
     --watch ${DOCS_CFG_DIR}
     --ignore ${DOCS_BUILD_DIR}
@@ -187,7 +198,7 @@ add_doc_target(
     -c ${DOCS_CFG_DIR}
     -d ${DOCS_DOCTREE_DIR}
     -w ${DOCS_BUILD_DIR}/html.log
-    -t ${DOC_TAG}
+    ${SPHINX_TAGS_ARGS}
     ${SPHINXOPTS}
     ${SPHINXOPTS_EXTRA}
     ${DOCS_SRC_DIR}
@@ -214,7 +225,7 @@ add_doc_target(
     -c ${DOCS_CFG_DIR}
     -d ${DOCS_DOCTREE_DIR}
     -w ${DOCS_BUILD_DIR}/latex.log
-    -t ${DOC_TAG}
+    ${SPHINX_TAGS_ARGS}
     -t convertimages
     ${SPHINXOPTS}
     ${SPHINXOPTS_EXTRA}
@@ -266,7 +277,7 @@ add_doc_target(
     -c ${DOCS_CFG_DIR}
     -d ${DOCS_DOCTREE_DIR}
     -w ${DOCS_BUILD_DIR}/linkcheck.log
-    -t ${DOC_TAG}
+    ${SPHINX_TAGS_ARGS}
     ${SPHINXOPTS}
     ${SPHINXOPTS_EXTRA}
     ${DOCS_SRC_DIR}
diff --git a/doc/LICENSING.rst b/doc/LICENSING.rst
index d2674a7b327..f267160c8d3 100644
--- a/doc/LICENSING.rst
+++ b/doc/LICENSING.rst
@@ -59,8 +59,8 @@ ENE KB1200_EVB Board OpenOCD Configuration
 ------------------------------------------
 
 * *Licensing:* `GPLv2 License`_
-* *Impact:* This file is used by `OpenOCD`_ when programming and debugging the :ref:`ene_kb1200_evb`
-  board. It is never linked into the firmware.
+* *Impact:* This file is used by `OpenOCD`_ when programming and debugging the
+  :zephyr:board:`kb1200_evb` board. It is never linked into the firmware.
 * *Files:*
 
   * :zephyr_file:`boards/ene/kb1200_evb/support/openocd.cfg`
@@ -99,6 +99,15 @@ OpenThread Spinel HDLC RCP Host Interface Files
   * :zephyr_file:`modules/openthread/platform/radio_spinel.cpp`
   * :zephyr_file:`modules/openthread/platform/hdlc_interface.cpp`
 
+Python Devicetree library test files
+------------------------------------
+
+* *Licensing:* `BSD-3-clause`_
+* *Impact:* These are only used for testing and never linked with the firmware.
+* *Files*:
+
+  * Various yaml files under ``scripts/dts/python-devicetree/tests``
+
 .. _Apache 2.0 License:
    https://github.com/zephyrproject-rtos/zephyr/blob/main/LICENSE
 
diff --git a/doc/Makefile b/doc/Makefile
index e1dd82d59cb..4ce22f280f4 100644
--- a/doc/Makefile
+++ b/doc/Makefile
@@ -8,6 +8,7 @@ SPHINXOPTS ?= -j auto -W --keep-going -T
 SPHINXOPTS_EXTRA ?=
 LATEXMKOPTS ?= -halt-on-error -no-shell-escape
 DT_TURBO_MODE ?= 0
+HW_FEATURES_TURBO_MODE ?= 0
 
 # ------------------------------------------------------------------------------
 # Documentation targets
@@ -15,10 +16,10 @@ DT_TURBO_MODE ?= 0
 .PHONY: configure clean html html-fast html-live html-live-fast latex pdf doxygen
 
 html-fast:
-	${MAKE} html DT_TURBO_MODE=1
+	${MAKE} html DT_TURBO_MODE=1 HW_FEATURES_TURBO_MODE=1
 
 html-live-fast:
-	${MAKE} html-live DT_TURBO_MODE=1
+	${MAKE} html-live DT_TURBO_MODE=1 HW_FEATURES_TURBO_MODE=1
 
 html html-live latex pdf linkcheck doxygen: configure
 	cmake --build ${BUILDDIR} --target $@
@@ -32,7 +33,8 @@ configure:
 		-DSPHINXOPTS="${SPHINXOPTS}" \
 		-DSPHINXOPTS_EXTRA="${SPHINXOPTS_EXTRA}" \
 		-DLATEXMKOPTS="${LATEXMKOPTS}" \
-		-DDT_TURBO_MODE=${DT_TURBO_MODE}
+		-DDT_TURBO_MODE=${DT_TURBO_MODE} \
+		-DHW_FEATURES_TURBO_MODE=${HW_FEATURES_TURBO_MODE}
 
 clean:
 	cmake --build ${BUILDDIR} --target clean
diff --git a/doc/_doxygen/groups.dox b/doc/_doxygen/groups.dox
index 38edbb052b2..6365dd4c63b 100644
--- a/doc/_doxygen/groups.dox
+++ b/doc/_doxygen/groups.dox
@@ -39,6 +39,12 @@
 @{
 @}
 
+@brief Debug Services
+@defgroup debug Debug
+@ingroup os_services
+@{
+@}
+
 @brief Connectivity
 @defgroup connectivity Connectivity
 @{
@@ -79,14 +85,4 @@
 @{
 @}
 
-@brief Tests
-@defgroup all_tests Tests
-@{
-@}
-
-@defgroup kernel_memprotect_tests Memory Protection
-@ingroup all_tests
-@{
-@}
-
 */
diff --git a/doc/_extensions/zephyr/application.py b/doc/_extensions/zephyr/application.py
index 4b2867b6ab0..41e34bac182 100644
--- a/doc/_extensions/zephyr/application.py
+++ b/doc/_extensions/zephyr/application.py
@@ -44,6 +44,9 @@ class ZephyrAppCommandsDirective(Directive):
         'compact': directives.flag,
         'west-args': directives.unchanged,
         'flash-args': directives.unchanged,
+        'debug-args': directives.unchanged,
+        'debugserver-args': directives.unchanged,
+        'attach-args': directives.unchanged,
     }
 
     TOOLS = ['cmake', 'west', 'all']
@@ -76,6 +79,9 @@ def run(self):
         compact = 'compact' in self.options
         west_args = self.options.get('west-args', None)
         flash_args = self.options.get('flash-args', None)
+        debug_args = self.options.get('debug-args', None)
+        debugserver_args = self.options.get('debugserver-args', None)
+        attach_args = self.options.get('attach-args', None)
 
         if tool not in self.TOOLS:
             raise self.error(f'Unknown tool {tool}; choose from: {self.TOOLS}')
@@ -146,6 +152,9 @@ def run(self):
             'generator': generator,
             'west_args': west_args,
             'flash_args': flash_args,
+            'debug_args': debug_args,
+            'debugserver_args': debugserver_args,
+            'attach_args': attach_args,
             }
 
         if 'west' in tools:
@@ -199,6 +208,9 @@ def _generate_west(self, **kwargs):
         build_args = kwargs["build_args"]
         west_args = kwargs['west_args']
         flash_args = kwargs['flash_args']
+        debug_args = kwargs['debug_args']
+        debugserver_args = kwargs['debugserver_args']
+        attach_args = kwargs['attach_args']
         kwargs['board'] = None
         # west always defaults to ninja
         gen_arg = ' -G\'Unix Makefiles\'' if generator == 'make' else ''
@@ -207,6 +219,9 @@ def _generate_west(self, **kwargs):
         build_args = "".join(f" -o {b}" for b in build_args) if build_args else ""
         west_args = f' {west_args}' if west_args else ''
         flash_args = f' {flash_args}' if flash_args else ''
+        debug_args = f' {debug_args}' if debug_args else ''
+        debugserver_args = f' {debugserver_args}' if debugserver_args else ''
+        attach_args = f' {attach_args}' if attach_args else ''
         snippet_args = ''.join(f' -S {s}' for s in snippets) if snippets else ''
         shield_args = ''.join(f' --shield {s}' for s in shield) if shield else ''
         # ignore zephyr_app since west needs to run within
@@ -255,11 +270,11 @@ def _generate_west(self, **kwargs):
             elif goal == 'flash':
                 content.append(f'west flash{flash_args}{dst}')
             elif goal == 'debug':
-                content.append(f'west debug{dst}')
+                content.append(f'west debug{debug_args}{dst}')
             elif goal == 'debugserver':
-                content.append(f'west debugserver{dst}')
+                content.append(f'west debugserver{debugserver_args}{dst}')
             elif goal == 'attach':
-                content.append(f'west attach{dst}')
+                content.append(f'west attach{attach_args}{dst}')
             else:
                 content.append(f'west build -t {goal}{dst}')
 
diff --git a/doc/_extensions/zephyr/domain/__init__.py b/doc/_extensions/zephyr/domain/__init__.py
index b598ef3a3e5..462b5652763 100644
--- a/doc/_extensions/zephyr/domain/__init__.py
+++ b/doc/_extensions/zephyr/domain/__init__.py
@@ -2,7 +2,7 @@
 Zephyr Extension
 ################
 
-Copyright (c) 2023 The Linux Foundation
+Copyright (c) 2023-2025 The Linux Foundation
 SPDX-License-Identifier: Apache-2.0
 
 This extension adds a new ``zephyr`` domain for handling the documentation of various entities
@@ -16,6 +16,10 @@
 - ``zephyr:code-sample-listing::`` - Shows a listing of code samples found in a given category.
 - ``zephyr:board-catalog::`` - Shows a listing of boards supported by Zephyr.
 - ``zephyr:board::`` - Flags a document as being the documentation page for a board.
+- ``zephyr:board-supported-hw::`` - Shows a table of supported hardware features for all the targets
+  of the board documented in the current page.
+- ``zephyr:board-supported-runners::`` - Shows a table of supported runners for the board documented
+  in the current page.
 
 Roles
 -----
@@ -27,6 +31,7 @@
 """
 
 import json
+import re
 import sys
 from collections.abc import Iterator
 from os import path
@@ -35,7 +40,7 @@
 
 from anytree import ChildResolverError, Node, PreOrderIter, Resolver, search
 from docutils import nodes
-from docutils.parsers.rst import directives
+from docutils.parsers.rst import directives, roles
 from docutils.statemachine import StringList
 from sphinx import addnodes
 from sphinx.application import Sphinx
@@ -57,6 +62,7 @@
 
 
 sys.path.insert(0, str(Path(__file__).parents[4] / "scripts/dts/python-devicetree/src"))
+sys.path.insert(0, str(Path(__file__).parents[4] / "scripts/west_commands"))
 sys.path.insert(0, str(Path(__file__).parents[3] / "_scripts"))
 
 from gen_boards_catalog import get_catalog
@@ -65,6 +71,43 @@
 TEMPLATES_DIR = Path(__file__).parent / "templates"
 RESOURCES_DIR = Path(__file__).parent / "static"
 
+# Load and parse binding types from text file
+BINDINGS_TXT_PATH = ZEPHYR_BASE / "dts" / "bindings" / "binding-types.txt"
+ACRONYM_PATTERN = re.compile(r'([a-zA-Z0-9-]+)\s*\((.*?)\)')
+BINDING_TYPE_TO_DOCUTILS_NODE = {}
+
+
+def parse_text_with_acronyms(text):
+    """Parse text that may contain acronyms into a list of nodes."""
+    result = nodes.inline()
+    last_end = 0
+
+    for match in ACRONYM_PATTERN.finditer(text):
+        # Add any text before the acronym
+        if match.start() > last_end:
+            result += nodes.Text(text[last_end : match.start()])
+
+        # Add the acronym
+        abbr, explanation = match.groups()
+        result += nodes.abbreviation(abbr, abbr, explanation=explanation)
+        last_end = match.end()
+
+    # Add any remaining text
+    if last_end < len(text):
+        result += nodes.Text(text[last_end:])
+
+    return result
+
+
+with open(BINDINGS_TXT_PATH) as f:
+    for line in f:
+        line = line.strip()
+        if not line or line.startswith('#'):
+            continue
+
+        key, value = line.split('\t', 1)
+        BINDING_TYPE_TO_DOCUTILS_NODE[key] = parse_text_with_acronyms(value)
+
 logger = logging.getLogger(__name__)
 
 
@@ -268,6 +311,21 @@ def convert_node(self, node):
                 field += field_body
                 field_list += field
 
+            gh_link = gh_link_get_url(self.app, self.env.docname)
+            gh_link_button = nodes.raw(
+                "",
+                f"""
+                <div id="board-github-link">
+                    <a href="{gh_link}/../.." class="btn btn-info fa fa-github"
+                        target="_blank">
+                        Browse board sources
+                    </a>
+                </div>
+                """,
+                format="html",
+            )
+            sidebar += gh_link_button
+
             # Move the sibling nodes under the new section
             new_section.extend(siblings_to_move)
 
@@ -662,6 +720,7 @@ def run(self):
             )
             return []
         else:
+            self.env.domaindata["zephyr"]["has_board"][self.env.docname] = True
             board = boards[board_name]
             # flag board in the domain data as now having a documentation page so that it can be
             # cross-referenced etc.
@@ -670,9 +729,14 @@ def run(self):
             board_node = BoardNode(id=board_name)
             board_node["full_name"] = board["full_name"]
             board_node["vendor"] = vendors.get(board["vendor"], board["vendor"])
+            board_node["revision_default"] = board["revision_default"]
+            board_node["supported_features"] = board["supported_features"]
             board_node["archs"] = board["archs"]
             board_node["socs"] = board["socs"]
             board_node["image"] = board["image"]
+            board_node["supported_runners"] = board["supported_runners"]
+            board_node["flash_runner"] = board["flash_runner"]
+            board_node["debug_runner"] = board["debug_runner"]
             return [board_node]
 
 
@@ -693,6 +757,7 @@ def run(self):
                     "boards": domain_data["boards"],
                     "vendors": domain_data["vendors"],
                     "socs": domain_data["socs"],
+                    "hw_features_present": self.env.app.config.zephyr_generate_hw_features,
                 },
             )
             return [nodes.raw("", rendered, format="html")]
@@ -700,6 +765,356 @@ def run(self):
             return [nodes.paragraph(text="Board catalog is only available in HTML.")]
 
 
+class BoardSupportedHardwareDirective(SphinxDirective):
+    """A directive for showing the supported hardware features of a board."""
+
+    has_content = False
+    required_arguments = 0
+    optional_arguments = 0
+
+    def run(self):
+        env = self.env
+        docname = env.docname
+
+        matcher = NodeMatcher(BoardNode)
+        board_nodes = list(self.state.document.traverse(matcher))
+        if not board_nodes:
+            logger.warning(
+                "board-supported-hw directive must be used in a board documentation page.",
+                location=(docname, self.lineno),
+            )
+            return []
+
+        board_node = board_nodes[0]
+        supported_features = board_node["supported_features"]
+        result_nodes = []
+
+        paragraph = nodes.paragraph()
+        paragraph += nodes.Text("The ")
+        paragraph += nodes.literal(text=board_node["id"])
+        paragraph += nodes.Text(" board supports the hardware features listed below.")
+        result_nodes.append(paragraph)
+
+        if not env.app.config.zephyr_generate_hw_features:
+            note = nodes.admonition()
+            note += nodes.title(text="Note")
+            note["classes"].append("warning")
+            note += nodes.paragraph(
+                text="The list of supported hardware features was not generated. Run a full "
+                "documentation build for the required metadata to be available."
+            )
+            result_nodes.append(note)
+            return result_nodes
+
+        html_contents = """<div class="legend admonition">
+  <dl class="supported-hardware field-list">
+    <dt>
+      <span class="location-chip onchip">on-chip</span> /
+      <span class="location-chip onboard">on-board</span>
+    </dt>
+    <dd>
+      Feature integrated in the SoC / present on the board.
+    </dd>
+    <dt>
+      <span class="count okay-count">2</span> /
+      <span class="count disabled-count">2</span>
+    </dt>
+    <dd>
+      Number of instances that are enabled / disabled. <br/>
+      Click on the label to see the first instance of this feature in the board/SoC DTS files.
+    </dd>
+    <dt>
+      <code class="docutils literal notranslate"><span class="pre">vnd,foo</span></code>
+    </dt>
+    <dd>
+      Compatible string for the Devicetree binding matching the feature. <br/>
+      Click on the link to view the binding documentation.
+    </dd>
+  </dl>
+</div>"""
+        result_nodes.append(nodes.raw("", html_contents, format="html"))
+
+        tables_container = nodes.container(ids=[f"{board_node['id']}-hw-features"])
+        result_nodes.append(tables_container)
+
+        board_json = json.dumps(
+            {
+                "board_name": board_node["id"],
+                "revision_default": board_node["revision_default"],
+                "targets": list(supported_features.keys()),
+            }
+        )
+        result_nodes.append(
+            nodes.raw(
+                "",
+                f"""<script>board_data = {board_json}</script>""",
+                format="html",
+            )
+        )
+
+        for target, features in sorted(supported_features.items()):
+            if not features:
+                continue
+
+            target_heading = nodes.section(ids=[f"{board_node['id']}-{target}-hw-features-section"])
+            heading = nodes.title()
+            heading += nodes.literal(text=target)
+            heading += nodes.Text(" target")
+            target_heading += heading
+            tables_container += target_heading
+
+            table = nodes.table(
+                classes=["colwidths-given", "hardware-features"],
+                ids=[f"{board_node['id']}-{target}-hw-features-table"],
+            )
+            tgroup = nodes.tgroup(cols=4)
+
+            tgroup += nodes.colspec(colwidth=15, classes=["type"])
+            tgroup += nodes.colspec(colwidth=12, classes=["location"])
+            tgroup += nodes.colspec(colwidth=53, classes=["description"])
+            tgroup += nodes.colspec(colwidth=20, classes=["compatible"])
+
+            thead = nodes.thead()
+            row = nodes.row()
+            headers = ["Type", "Location", "Description", "Compatible"]
+            for header in headers:
+                entry = nodes.entry(classes=[header.lower()])
+                entry += nodes.paragraph(text=header)
+                row += entry
+            thead += row
+            tgroup += thead
+
+            tbody = nodes.tbody()
+
+            def feature_sort_key(feature):
+                # Put "CPU" first. Later updates might also give priority to features
+                # like "sensor"s, for example.
+                if feature == "cpu":
+                    return (0, feature)
+                return (1, feature)
+
+            sorted_features = sorted(features.keys(), key=feature_sort_key)
+
+            for feature in sorted_features:
+                items = list(features[feature].items())
+                num_items = len(items)
+
+                for i, (key, value) in enumerate(items):
+                    row = nodes.row()
+
+                    # TYPE column
+                    if i == 0:
+                        type_entry = nodes.entry(morerows=num_items - 1, classes=["type"])
+                        type_entry += nodes.paragraph(
+                            "",
+                            "",
+                            BINDING_TYPE_TO_DOCUTILS_NODE.get(
+                                feature, nodes.Text(feature)
+                            ).deepcopy(),
+                        )
+                        row += type_entry
+
+                    # LOCATION column
+                    location_entry = nodes.entry(classes=["location"])
+                    location_para = nodes.paragraph()
+
+                    if "board" in value["locations"]:
+                        location_chip = nodes.inline(
+                            classes=["location-chip", "onboard"],
+                            text="on-board",
+                        )
+                        location_para += location_chip
+                    elif "soc" in value["locations"]:
+                        location_chip = nodes.inline(
+                            classes=["location-chip", "onchip"],
+                            text="on-chip",
+                        )
+                        location_para += location_chip
+
+                    location_entry += location_para
+                    row += location_entry
+
+                    # DESCRIPTION column
+                    desc_entry = nodes.entry(classes=["description"])
+                    desc_para = nodes.paragraph(classes=["status"])
+                    desc_para += nodes.Text(value["description"])
+
+                    # Add count indicators for okay and not-okay instances
+                    okay_nodes = value.get("okay_nodes", [])
+                    disabled_nodes = value.get("disabled_nodes", [])
+
+                    role_fn, _ = roles.role(
+                        "zephyr_file", self.state_machine.language, self.lineno, self.state.reporter
+                    )
+
+                    def create_count_indicator(nodes_list, class_type, role_function=role_fn):
+                        if not nodes_list:
+                            return None
+
+                        count = len(nodes_list)
+
+                        if role_function is None:
+                            return nodes.inline(
+                                classes=["count", f"{class_type}-count"], text=str(count)
+                            )
+
+                        # Create a reference to the first node in the list
+                        first_node = nodes_list[0]
+                        file_ref = f"{count} <{first_node['filename']}#L{first_node['lineno']}>"
+
+                        role_nodes, _ = role_function(
+                            "zephyr_file", file_ref, file_ref, self.lineno, self.state.inliner
+                        )
+
+                        count_node = role_nodes[0]
+                        count_node["classes"] = ["count", f"{class_type}-count"]
+
+                        return count_node
+
+                    desc_para += create_count_indicator(okay_nodes, "okay")
+                    desc_para += create_count_indicator(disabled_nodes, "disabled")
+
+                    desc_entry += desc_para
+                    row += desc_entry
+
+                    # COMPATIBLE column
+                    compatible_entry = nodes.entry(classes=["compatible"])
+                    xref = addnodes.pending_xref(
+                        "",
+                        refdomain="std",
+                        reftype="dtcompatible",
+                        reftarget=key,
+                        refexplicit=False,
+                        refwarn=(not value.get("custom_binding", False)),
+                    )
+                    xref += nodes.literal(text=key)
+                    compatible_entry += nodes.paragraph("", "", xref)
+                    row += compatible_entry
+
+                    tbody += row
+
+            tgroup += tbody
+            table += tgroup
+            tables_container += table
+
+        return result_nodes
+
+
+class BoardSupportedRunnersDirective(SphinxDirective):
+    """A directive for showing the supported runners of a board."""
+
+    has_content = False
+    required_arguments = 0
+    optional_arguments = 0
+
+    def run(self):
+        env = self.env
+        docname = env.docname
+
+        matcher = NodeMatcher(BoardNode)
+        board_nodes = list(self.state.document.traverse(matcher))
+        if not board_nodes:
+            logger.warning(
+                "board-supported-runners directive must be used in a board documentation page.",
+                location=(docname, self.lineno),
+            )
+            return []
+
+        if not env.app.config.zephyr_generate_hw_features:
+            note = nodes.admonition()
+            note += nodes.title(text="Note")
+            note["classes"].append("warning")
+            note += nodes.paragraph(
+                text="The list of supported runners was not generated. Run a full documentation "
+                "build for the required metadata to be available."
+            )
+            return [note]
+
+        board_node = board_nodes[0]
+        runners = board_node["supported_runners"]
+        flash_runner = board_node["flash_runner"]
+        debug_runner = board_node["debug_runner"]
+
+        result_nodes = []
+
+        paragraph = nodes.paragraph()
+        paragraph += nodes.Text("The ")
+        paragraph += nodes.literal(text=board_node["id"])
+        paragraph += nodes.Text(
+            " board supports the runners and associated west commands listed below."
+        )
+        result_nodes.append(paragraph)
+
+        env_runners = env.domaindata["zephyr"]["runners"]
+        commands = ["flash", "debug"]
+        for runner in env_runners:
+            if runner in board_node["supported_runners"]:
+                for cmd in env_runners[runner].get("commands", []):
+                    if cmd not in commands:
+                        commands.append(cmd)
+
+        # create the table
+        table = nodes.table(classes=["colwidths-given", "runners-table"])
+        tgroup = nodes.tgroup(cols=len(commands) + 1)  # +1 for the Runner column
+
+        # Add colspec for Runner column
+        tgroup += nodes.colspec(colwidth=15, classes=["type"])
+        # Add colspecs for command columns
+        for _ in commands:
+            tgroup += nodes.colspec(colwidth=15, classes=["type"])
+
+        thead = nodes.thead()
+        row = nodes.row()
+        entry = nodes.entry()
+        row += entry
+        headers = [*commands]
+        for header in headers:
+            entry = nodes.entry(classes=[header.lower()])
+            entry += addnodes.literal_strong(text=header, classes=["command"])
+            row += entry
+        thead += row
+        tgroup += thead
+
+        tbody = nodes.tbody()
+
+        # add a row for each runner
+        for runner in sorted(runners):
+            row = nodes.row()
+            # First column - Runner name
+            entry = nodes.entry()
+
+            xref = addnodes.pending_xref(
+                "",
+                refdomain="std",
+                reftype="ref",
+                reftarget=f"runner_{runner}",
+                refexplicit=True,
+                refwarn=False,
+            )
+            xref += nodes.Text(runner)
+            entry += addnodes.literal_strong("", "", xref)
+            row += entry
+
+            # Add columns for each command
+            for command in commands:
+                entry = nodes.entry()
+                if command in env_runners[runner].get("commands", []):
+                    entry += nodes.Text("✅")
+                    if (command == "flash" and runner == flash_runner) or (
+                        command == "debug" and runner == debug_runner
+                    ):
+                        entry += nodes.Text(" (default)")
+                row += entry
+            tbody += row
+
+        tgroup += tbody
+        table += tgroup
+
+        result_nodes.append(table)
+
+        return result_nodes
+
+
 class ZephyrDomain(Domain):
     """Zephyr domain"""
 
@@ -718,6 +1133,8 @@ class ZephyrDomain(Domain):
         "code-sample-category": CodeSampleCategoryDirective,
         "board-catalog": BoardCatalogDirective,
         "board": BoardDirective,
+        "board-supported-hw": BoardSupportedHardwareDirective,
+        "board-supported-runners": BoardSupportedRunnersDirective,
     }
 
     object_types: dict[str, ObjType] = {
@@ -733,6 +1150,7 @@ class ZephyrDomain(Domain):
         # keep track of documents containing special directives
         "has_code_sample_listing": {},  # docname -> bool
         "has_board_catalog": {},  # docname -> bool
+        "has_board": {},  # docname -> bool
     }
 
     def clear_doc(self, docname: str) -> None:
@@ -752,6 +1170,7 @@ def clear_doc(self, docname: str) -> None:
 
         self.data["has_code_sample_listing"].pop(docname, None)
         self.data["has_board_catalog"].pop(docname, None)
+        self.data["has_board"].pop(docname, None)
 
     def merge_domaindata(self, docnames: list[str], otherdata: dict) -> None:
         self.data["code-samples"].update(otherdata["code-samples"])
@@ -784,6 +1203,7 @@ def merge_domaindata(self, docnames: list[str], otherdata: dict) -> None:
             self.data["has_board_catalog"][docname] = otherdata["has_board_catalog"].get(
                 docname, False
             )
+            self.data["has_board"][docname] = otherdata["has_board"].get(docname, False)
 
     def get_objects(self):
         for _, code_sample in self.data["code-samples"].items():
@@ -836,7 +1256,7 @@ def resolve_xref(self, env, fromdocname, builder, type, target, node, contnode):
         else:
             return
 
-        if elem:
+        if elem and "docname" in elem:
             if not node.get("refexplicit"):
                 contnode = [nodes.Text(elem["name"] if type != "board" else elem["full_name"])]
 
@@ -937,16 +1357,26 @@ def install_static_assets_as_needed(
         app.add_css_file("css/board-catalog.css")
         app.add_js_file("js/board-catalog.js")
 
+    if app.env.domaindata["zephyr"]["has_board"].get(pagename, False):
+        app.add_css_file("css/board.css")
+        app.add_js_file("js/board.js")
+
 
 def load_board_catalog_into_domain(app: Sphinx) -> None:
-    board_catalog = get_catalog()
+    board_catalog = get_catalog(
+        generate_hw_features=(
+            app.builder.format == "html" and app.config.zephyr_generate_hw_features
+        )
+    )
     app.env.domaindata["zephyr"]["boards"] = board_catalog["boards"]
     app.env.domaindata["zephyr"]["vendors"] = board_catalog["vendors"]
     app.env.domaindata["zephyr"]["socs"] = board_catalog["socs"]
+    app.env.domaindata["zephyr"]["runners"] = board_catalog["runners"]
 
 
 def setup(app):
     app.add_config_value("zephyr_breathe_insert_related_samples", False, "env")
+    app.add_config_value("zephyr_generate_hw_features", False, "env")
 
     app.add_domain(ZephyrDomain)
 
diff --git a/doc/_extensions/zephyr/domain/static/css/board-catalog.css b/doc/_extensions/zephyr/domain/static/css/board-catalog.css
index 9e5e33f7e7f..36768a1be4e 100644
--- a/doc/_extensions/zephyr/domain/static/css/board-catalog.css
+++ b/doc/_extensions/zephyr/domain/static/css/board-catalog.css
@@ -1,5 +1,5 @@
 /**
- * Copyright (c) 2024, The Linux Foundation.
+ * Copyright (c) 2024-2025, The Linux Foundation.
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -82,6 +82,49 @@
   white-space: nowrap;
 }
 
+.tag-container {
+  display: flex;
+  flex-wrap: wrap;
+  border: 1px solid #ccc;
+  border-radius: 50px;
+  padding: 5px 18px;
+}
+
+.tag-container:focus-within {
+  border-color: var(--input-focus-border-color);
+}
+
+.tag {
+  background-color: var(--admonition-note-background-color);
+  color: var(--admonition-note-color);
+  padding: 2px 12px 4px 16px;
+  border-radius: 30px;
+  display: inline-flex;
+  align-items: center;
+  cursor: pointer;
+  font-size: 14px;
+  margin-right: 8px;
+}
+
+.tag:hover {
+  background-color: #0056b3;
+}
+
+.tag::after {
+  content: '\00D7'; /* multiplication sign */
+  margin-left: 8px;
+  font-size: 12px;
+  cursor: pointer;
+}
+
+.filter-form input.tag-input {
+  flex: 1;
+  border: none;
+  padding: 5px;
+  outline: none;
+  background-color: transparent;
+}
+
 #catalog {
   display: flex;
   flex-wrap: wrap;
diff --git a/doc/_extensions/zephyr/domain/static/css/board.css b/doc/_extensions/zephyr/domain/static/css/board.css
new file mode 100644
index 00000000000..d2d90b9fe5c
--- /dev/null
+++ b/doc/_extensions/zephyr/domain/static/css/board.css
@@ -0,0 +1,297 @@
+/**
+ * Copyright (c) 2024-2025, The Linux Foundation.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Board overview "card" on board documentation pages */
+.sidebar.board-overview {
+    border-radius: 12px;
+    padding: 0px;
+    background: var(--admonition-note-background-color);
+    color: var(--admonition-note-title-color);
+    border-color: var(--admonition-note-title-background-color);
+}
+
+@media screen and (max-width: 480px) {
+    .sidebar.board-overview {
+        float: none;
+        margin-left: 0;
+    }
+}
+
+.sidebar.board-overview {
+    color: var(--admonition-note-color);
+}
+
+.sidebar.board-overview .sidebar-title {
+    font-family: var(--header-font-family);
+    background: var(--admonition-note-title-background-color);
+    color: var(--admonition-note-title-color);
+    border-radius: 12px 12px 0px 0px;
+    margin: 0px;
+    text-align: center;
+}
+
+.sidebar.board-overview figure {
+    padding: 1rem;
+    margin-bottom: -1rem;
+}
+
+.sidebar.board-overview figure img {
+    height: auto !important;
+}
+
+.sidebar.board-overview figure figcaption p {
+    margin-bottom: 0px;
+}
+
+.sidebar.board-overview dl.field-list {
+    align-items: center;
+    margin-top: 12px !important;
+    margin-bottom: 12px !important;
+    grid-template-columns: auto 1fr !important;
+    padding-right: 1em;
+}
+
+.sidebar.board-overview dl.field-list>dt {
+    background: transparent !important;
+}
+
+.sidebar.board-overview dl.field-list>dd {
+    margin-left: 1em;
+    text-overflow: ellipsis;
+    overflow: hidden;
+}
+
+.sidebar.board-overview dl.field-list>dd code {
+    font-size: 0.9em;
+}
+
+.sidebar.board-overview #board-github-link {
+    text-align: center;
+    margin-bottom: 1em;
+    font-size: 0.9em;
+}
+
+.sidebar.board-overview #board-github-link a {
+    display: inline-block;
+    white-space: nowrap;
+    overflow: hidden;
+    text-overflow: ellipsis;
+    max-width: 80%;
+}
+
+.legend {
+    font-size: 0.9em;
+    border-radius: 6px;
+    margin: auto;
+
+    .supported-hardware {
+        margin-bottom: 0px !important;
+        grid-template-columns: auto auto !important;
+
+        dt {
+            display: table-cell !important;
+            padding-left: 0em;
+            padding-bottom: 0.5em;
+            text-align: center;
+            background: none !important;
+        }
+
+        dd {
+            margin-top:4px;
+            line-height: 1.1em;
+        }
+    }
+}
+
+.board-target-selector {
+    margin-bottom: 1em;
+    padding: 15px;
+    display: flex;
+    align-items: center;
+    gap: 8px;
+    flex-wrap: wrap;
+    position: relative;
+}
+
+.board-target-selector > div {
+    display: flex;
+    flex-direction: column;
+    gap: 5px;
+}
+
+.static-value {
+    padding: 5px 0px;
+    color: var(--body-color);
+    font-family: var(--monospace-font-family);
+    font-size: 0.9em;
+}
+
+.separator {
+    font-size: 16px;
+    font-weight: bold;
+    margin: 0 4px;
+}
+
+.board-target-selector select {
+    background-color: var(--input-background-color);
+    color: var(--body-color);
+    border-radius: 4px;
+    font-family: var(--monospace-font-family);
+    font-size: 0.9em;
+    box-shadow: none;
+    transition: none;
+}
+
+.board-target-selector select:focus {
+    border-color: var(--input-focus-border-color);
+}
+
+.copy-button {
+    background: transparent;
+    border: 1px solid var(--input-border-color);
+    border-radius: 4px;
+    padding: 4px 8px;
+    cursor: pointer;
+    font-size: 0.8em;
+    color: var(--body-color);
+    display: flex;
+    align-items: center;
+    gap: 4px;
+    transition: all 0.2s ease;
+}
+
+.copy-button:hover {
+    background: var(--input-background-color);
+    border-color: var(--input-focus-border-color);
+}
+
+.copy-button.copied {
+    background: var(--admonition-note-title-background-color);
+    color: var(--admonition-note-title-color);
+    border-color: var(--admonition-note-title-color);
+}
+
+.copy-button svg {
+    width: 18px;
+    height: 18px;
+    fill: currentColor;
+}
+
+.hardware-features {
+    th {
+        background: var(--navbar-background-color);
+        color: var(--navbar-level-1-color);
+        border: none !important;
+        font-weight: 600;
+        text-transform: uppercase;
+        font-size: 0.8em;
+        letter-spacing: 0.5px;
+    }
+
+    td,
+    th {
+        padding: 8px 12px;
+        border-left: none !important;
+        text-align: left;
+    }
+
+    td {
+        font-size: 0.85em;
+        background: transparent !important;
+        vertical-align: middle;
+
+        p {
+            white-space: normal;
+        }
+    }
+
+    /* Column widths and specific styling */
+    .type {
+        font-weight: 600;
+    }
+
+    .location {
+        font-size: 0.9em;
+    }
+
+    .description {
+    }
+
+    .compatible {
+        font-family: var(--monospace-font-family);
+
+        code {
+            background: transparent;
+            border: none;
+            padding: 0;
+            font-size: 0.9em;
+        }
+
+        code.literal {
+            display: inline-block;
+            width:190px;
+            white-space: nowrap;
+            text-overflow: ellipsis;
+            overflow: hidden;
+        }
+    }
+}
+
+.count {
+    line-height: 1rem;
+    display: inline-flex;
+    align-items: center;
+    padding: 1px 4px;
+    border-radius: 4px;
+    font-size: 0.7em;
+    font-weight: 600;
+    margin-left: 4px;
+    padding-right: 6px !important;
+
+    &::before {
+        content: "×";
+        margin-right: 2px;
+    }
+
+    &.okay-count {
+        background: rgba(46, 204, 113, 1);
+        color: white;
+    }
+
+    &.disabled-count {
+        background: rgba(241, 196, 15, 1);
+        color: black;
+    }
+}
+
+.location-chip {
+    line-height: 1em;
+    display: inline-block;
+    width: 7em;
+    padding: 0.6em;
+    border-radius: 12px;
+    font-size: 0.8em;
+    font-weight: 600;
+    text-transform: lowercase;
+    text-align: center;
+    white-space: nowrap;
+
+    &.onboard {
+        background: var(--admonition-note-title-background-color);
+        color: var(--admonition-note-title-color);
+    }
+
+    &.onchip {
+        background: var(--admonition-tip-title-background-color);
+        color: var(--admonition-tip-title-color);
+    }
+}
+
+/* Status indicators */
+.status {
+    display: flex;
+    align-items: center;
+    gap: 6px;
+}
diff --git a/doc/_extensions/zephyr/domain/static/js/board-catalog.js b/doc/_extensions/zephyr/domain/static/js/board-catalog.js
index 6ac7ae946b8..0e8c2767c7f 100644
--- a/doc/_extensions/zephyr/domain/static/js/board-catalog.js
+++ b/doc/_extensions/zephyr/domain/static/js/board-catalog.js
@@ -1,5 +1,5 @@
 /**
- * Copyright (c) 2024, The Linux Foundation.
+ * Copyright (c) 2024-2025, The Linux Foundation.
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -29,6 +29,29 @@ function populateFormFromURL() {
     }
   });
 
+  // Restore supported features from URL
+  if (hashParams.has("features")) {
+    const features = hashParams.get("features").split(",");
+    setTimeout(() => {
+      features.forEach(feature => {
+        const tagContainer = document.getElementById('tag-container');
+        const tagInput = document.getElementById('tag-input');
+
+        const tagElement = document.createElement('span');
+        tagElement.classList.add('tag');
+        tagElement.textContent = feature;
+        tagElement.onclick = () => {
+          const selectedTags = [...document.querySelectorAll('.tag')].map(tag => tag.textContent);
+          selectedTags.splice(selectedTags.indexOf(feature), 1);
+          tagElement.remove();
+          filterBoards();
+        };
+        tagContainer.insertBefore(tagElement, tagInput);
+      });
+      filterBoards();
+    }, 0);
+  }
+
   filterBoards();
 }
 
@@ -47,6 +70,10 @@ function updateURL() {
     }
   });
 
+  // Add supported features to URL
+  const selectedTags = [...document.querySelectorAll('.tag')].map(tag => tag.textContent);
+  selectedTags.length ? hashParams.set("features", selectedTags.join(",")) : hashParams.delete("features");
+
   window.history.replaceState({}, "", `#${hashParams.toString()}`);
 }
 
@@ -84,6 +111,81 @@ function fillSocSocSelect(families, series = undefined, selectOnFill = false) {
   });
 }
 
+function setupHWCapabilitiesField() {
+  let selectedTags = [];
+
+  const tagContainer = document.getElementById('tag-container');
+  const tagInput = document.getElementById('tag-input');
+  const datalist = document.getElementById('tag-list');
+
+  const tagCounts = Array.from(document.querySelectorAll('.board-card')).reduce((acc, board) => {
+    board.getAttribute('data-supported-features').split(' ').forEach(tag => {
+      acc[tag] = (acc[tag] || 0) + 1;
+    });
+    return acc;
+  }, {});
+
+  const allTags = Object.keys(tagCounts).sort();
+
+  function addTag(tag) {
+    if (selectedTags.includes(tag) || tag === "" || !allTags.includes(tag)) return;
+    selectedTags.push(tag);
+
+    const tagElement = document.createElement('span');
+    tagElement.classList.add('tag');
+    tagElement.textContent = tag;
+    tagElement.onclick = () => removeTag(tag);
+    tagContainer.insertBefore(tagElement, tagInput);
+
+    tagInput.value = '';
+    updateDatalist();
+  }
+
+  function removeTag(tag) {
+    selectedTags = selectedTags.filter(t => t !== tag);
+    document.querySelectorAll('.tag').forEach(el => {
+      if (el.textContent.includes(tag)) el.remove();
+    });
+    updateDatalist();
+  }
+
+  function updateDatalist() {
+    datalist.innerHTML = '';
+    const filteredTags = allTags.filter(tag => !selectedTags.includes(tag));
+
+    filteredTags.forEach(tag => {
+      const option = document.createElement('option');
+      option.value = tag;
+      datalist.appendChild(option);
+    });
+
+    filterBoards();
+  }
+
+  tagInput.addEventListener('input', () => {
+    if (allTags.includes(tagInput.value)) {
+      addTag(tagInput.value);
+    }
+  });
+
+  // Add tag when pressing the Enter key
+  tagInput.addEventListener('keydown', (e) => {
+    if (e.key === 'Enter' && allTags.includes(tagInput.value)) {
+      addTag(tagInput.value);
+      e.preventDefault();
+    }
+  });
+
+  // Delete tag when pressing the Backspace key
+  tagInput.addEventListener('keydown', (e) => {
+    if (e.key === 'Backspace' && tagInput.value === '' && selectedTags.length > 0) {
+      removeTag(selectedTags[selectedTags.length - 1]);
+    }
+  });
+
+  updateDatalist();
+}
+
 document.addEventListener("DOMContentLoaded", function () {
   const form = document.querySelector(".filter-form");
 
@@ -101,9 +203,10 @@ document.addEventListener("DOMContentLoaded", function () {
   fillSocFamilySelect();
   fillSocSeriesSelect();
   fillSocSocSelect();
-
   populateFormFromURL();
 
+  setupHWCapabilitiesField();
+
   socFamilySelect = document.getElementById("family");
   socFamilySelect.addEventListener("change", () => {
     const selectedFamilies = [...socFamilySelect.selectedOptions].map(({ value }) => value);
@@ -142,6 +245,11 @@ function resetForm() {
   fillSocFamilySelect();
   fillSocSeriesSelect();
   fillSocSocSelect();
+
+  // Clear supported features
+  document.querySelectorAll('.tag').forEach(tag => tag.remove());
+  document.getElementById('tag-input').value = '';
+
   filterBoards();
 }
 
@@ -160,8 +268,10 @@ function filterBoards() {
   const vendorSelect = document.getElementById("vendor").value;
   const socSocSelect = document.getElementById("soc");
 
+  const selectedTags = [...document.querySelectorAll('.tag')].map(tag => tag.textContent);
+
   const resetFiltersBtn = document.getElementById("reset-filters");
-  if (nameInput || archSelect || vendorSelect || socSocSelect.selectedOptions.length) {
+  if (nameInput || archSelect || vendorSelect || socSocSelect.selectedOptions.length || selectedTags.length) {
     resetFiltersBtn.classList.remove("btn-disabled");
   } else {
     resetFiltersBtn.classList.add("btn-disabled");
@@ -174,6 +284,7 @@ function filterBoards() {
     const boardArchs = board.getAttribute("data-arch").split(" ");
     const boardVendor = board.getAttribute("data-vendor");
     const boardSocs = board.getAttribute("data-socs").split(" ");
+    const boardSupportedFeatures = board.getAttribute("data-supported-features").split(" ");
 
     let matches = true;
 
@@ -183,7 +294,8 @@ function filterBoards() {
       !(nameInput && !boardName.includes(nameInput)) &&
       !(archSelect && !boardArchs.includes(archSelect)) &&
       !(vendorSelect && boardVendor !== vendorSelect) &&
-      (selectedSocs.length === 0 || selectedSocs.some((soc) => boardSocs.includes(soc)));
+      (selectedSocs.length === 0 || selectedSocs.some((soc) => boardSocs.includes(soc))) &&
+      (selectedTags.length === 0 || selectedTags.every((tag) => boardSupportedFeatures.includes(tag)));
 
     board.classList.toggle("hidden", !matches);
   });
diff --git a/doc/_extensions/zephyr/domain/static/js/board.js b/doc/_extensions/zephyr/domain/static/js/board.js
new file mode 100644
index 00000000000..6ff36a5b0f2
--- /dev/null
+++ b/doc/_extensions/zephyr/domain/static/js/board.js
@@ -0,0 +1,248 @@
+/**
+ * Copyright (c) 2025, The Linux Foundation.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+(() => {
+  // SVG icons for copy button
+  const COPY_ICON = `<svg viewBox="0 0 24 24"><path d="M16 1H4c-1.1 0-2 .9-2 2v14h2V3h12V1zm3 4H8c-1.1 0-2 .9-2 2v14c0 1.1.9 2 2 2h11c1.1 0 2-.9 2-2V7c0-1.1-.9-2-2-2zm0 16H8V7h11v14z"/></svg>`;
+  const CHECK_ICON = `<svg viewBox="0 0 24 24"><path d="M9 16.17L4.83 12l-1.42 1.41L9 19 21 7l-1.41-1.41L9 16.17z"/></svg>`;
+
+  // DOM element creation helper
+  const createElement = (tag, className, text) => {
+    const element = document.createElement(tag);
+    if (className) element.className = className;
+    if (text) element.textContent = text;
+    return element;
+  };
+
+  // Target parsing helper
+  const parseTargetString = (targetString) => {
+    const [boardWithRev, ...qualifiers] = targetString.split('/');
+    const [board, revision] = boardWithRev.split('@');
+    return {
+      board: board || '',
+      revision: revision || '',
+      qualifier: qualifiers.join('/') || ''
+    };
+  };
+
+  // Select element creation helper
+  const createSelect = (options, selectedValue) => {
+    const select = createElement('select');
+    options.sort().forEach(value => {
+      const option = createElement('option', null, value);
+      option.value = value;
+      option.selected = (value === selectedValue);
+      select.appendChild(option);
+    });
+    return select;
+  };
+
+  // Main initialization function
+  const initializeBoardSelector = () => {
+    const container = document.querySelector('.container[id$="-hw-features"]');
+    if (!container) return console.error('Container element not found');
+
+    const components = {
+      boards: new Set([board_data.board_name]),
+      revisions: new Set(),
+      qualifiers: new Set()
+    };
+
+    board_data.targets.forEach(target => {
+      const { revision, qualifier } = parseTargetString(target);
+      if (revision) components.revisions.add(revision);
+      if (qualifier) components.qualifiers.add(qualifier);
+    });
+
+    const initialValues = parseTargetString(board_data.targets[0]);
+    if (board_data.revision_default) {
+      initialValues.revision = board_data.revision_default;
+    }
+
+    const selector = createElement('div', 'board-target-selector');
+    selector.appendChild(createElement('div', 'static-value', initialValues.board));
+
+    // Add revision selector if needed
+    let revisionSelect;
+    if (components.revisions.size > 0) {
+      selector.appendChild(createElement('div', 'separator', '@'));
+      revisionSelect = createSelect(
+        Array.from(components.revisions),
+        initialValues.revision
+      );
+      selector.appendChild(revisionSelect);
+    }
+
+    // Add qualifier selector or static value
+    let qualifierSelect;
+    if (components.qualifiers.size > 0) {
+      selector.appendChild(createElement('div', 'separator', '/'));
+      if (components.qualifiers.size === 1) {
+        selector.appendChild(createElement('div', 'static-value', initialValues.qualifier));
+      } else {
+        qualifierSelect = createSelect(
+          Array.from(components.qualifiers),
+          null
+        );
+        selector.appendChild(qualifierSelect);
+      }
+    }
+
+    // Add copy button
+    const copyButton = createElement('button', 'copy-button');
+    copyButton.innerHTML = COPY_ICON;
+    copyButton.addEventListener('click', handleCopyButtonClick(
+      initialValues,
+      revisionSelect,
+      qualifierSelect,
+      copyButton
+    ));
+    selector.appendChild(copyButton);
+
+    // Insert selector into DOM and set up event listeners
+    container.parentNode.insertBefore(selector, container);
+    selector.querySelectorAll('select').forEach(select => {
+      select.addEventListener('change', () => {
+        updateSelectOptions(initialValues, revisionSelect, qualifierSelect);
+        updateDisplayedTable(revisionSelect, qualifierSelect);
+
+      });
+    });
+
+    // Initial display setup
+    initializeDisplay();
+    // updateDisplayedTable(revisionSelect, qualifierSelect);
+  };
+
+  // Copy button click handler
+  const handleCopyButtonClick = (initialValues, revisionSelect, qualifierSelect, button) => async () => {
+    try {
+      const target = buildTargetString(initialValues, revisionSelect, qualifierSelect);
+      await navigator.clipboard.writeText(target);
+
+      button.classList.add('copied');
+      button.innerHTML = CHECK_ICON;
+
+      setTimeout(() => {
+        button.classList.remove('copied');
+        button.innerHTML = COPY_ICON;
+      }, 1000);
+    } catch (error) {
+      console.error('Failed to copy text:', error);
+    }
+  };
+
+  // Build target string from current selections
+  const buildTargetString = (initialValues, revisionSelect, qualifierSelect) => {
+    const parts = [initialValues.board];
+
+    if (revisionSelect) {
+      parts.push(`@${revisionSelect.value}`);
+    } else if (initialValues.revision) {
+      parts.push(`@${initialValues.revision}`);
+    }
+
+    if (qualifierSelect) {
+      parts.push(`/${qualifierSelect.value}`);
+    } else if (initialValues.qualifier) {
+      parts.push(`/${initialValues.qualifier}`);
+    }
+
+    return parts.join('');
+  };
+
+  // Update displayed table based on selections
+  const updateDisplayedTable = (revisionSelect, qualifierSelect) => {
+    const currentTarget = buildTargetString(
+      parseTargetString(board_data.targets[0]),
+      revisionSelect,
+      qualifierSelect
+    );
+
+    console.log(currentTarget);
+
+    document.querySelectorAll('section[id$="-hw-features-section"]').forEach(section => {
+      // Find the matching target in board_data.targets
+      const isMatch = section.id.replace(/${board_data.name}/).replace(/-hw-features-section$/, '').endsWith(currentTarget);
+
+      const table = document.querySelector(`table[id="${section.id.replace('-section', '-table')}"]`);
+      const wrapper = table?.closest('.wy-table-responsive');
+
+
+      if (table) table.style.display = isMatch ? 'table' : 'none';
+      if (wrapper) wrapper.style.display = isMatch ? 'block' : 'none';
+    });
+  };
+
+  // Initial display setup
+  const initializeDisplay = () => {
+    document.querySelectorAll('section[id$="-hw-features-section"]').forEach(section => section.style.display = 'none');
+    document.querySelectorAll('table.hardware-features').forEach((table, index) => {
+      const wrapper = table.closest('.wy-table-responsive');
+      table.style.display = index === 0 ? 'table' : 'none';
+      if (wrapper) wrapper.style.display = index === 0 ? 'block' : 'none';
+    });
+    updateDisplayedTable(revisionSelect, qualifierSelect);
+  };
+
+  // Update select options based on valid combinations
+  const updateSelectOptions = (initialValues, revisionSelect, qualifierSelect) => {
+    if (revisionSelect) {
+      const currentBoard = initialValues.board;
+      const validRevisions = new Set();
+
+      // Find valid revisions for current board
+      board_data.targets.forEach(target => {
+        const { board, revision } = parseTargetString(target);
+        if (board === currentBoard && revision) {
+          validRevisions.add(revision);
+        }
+      });
+
+      // Update revision select options
+      Array.from(revisionSelect.options).forEach(option => {
+        option.disabled = !validRevisions.has(option.value);
+        if (option.disabled && option.selected) {
+          // If current selection is invalid, select first valid option
+          const firstValid = Array.from(revisionSelect.options).find(opt => !opt.disabled);
+          if (firstValid) firstValid.selected = true;
+        }
+      });
+    }
+
+    if (qualifierSelect) {
+      const currentBoard = initialValues.board;
+      const currentRevision = revisionSelect ? revisionSelect.value : initialValues.revision;
+      const validQualifiers = new Set();
+
+      // Find valid qualifiers for current board and revision
+      board_data.targets.forEach(target => {
+        const { board, revision, qualifier } = parseTargetString(target);
+        if (board === currentBoard &&
+          (!revision || revision === currentRevision) &&
+          qualifier) {
+          validQualifiers.add(qualifier);
+        }
+      });
+
+      // Update qualifier select options
+      Array.from(qualifierSelect.options).forEach(option => {
+        option.disabled = !validQualifiers.has(option.value);
+        if (option.disabled && option.selected) {
+          // If current selection is invalid, select first valid option
+          const firstValid = Array.from(qualifierSelect.options).find(opt => !opt.disabled);
+          if (firstValid) firstValid.selected = true;
+        }
+      });
+    }
+  };
+
+  // Start initialization when DOM is ready
+  if (document.readyState === 'loading') {
+    document.addEventListener('DOMContentLoaded', initializeBoardSelector);
+  } else {
+    initializeBoardSelector();
+  }
+})();
diff --git a/doc/_extensions/zephyr/domain/templates/board-card.html b/doc/_extensions/zephyr/domain/templates/board-card.html
index 4c16a3c0cc5..0e4808b85a7 100644
--- a/doc/_extensions/zephyr/domain/templates/board-card.html
+++ b/doc/_extensions/zephyr/domain/templates/board-card.html
@@ -1,5 +1,5 @@
 {#
-  Copyright (c) 2024, The Linux Foundation.
+  Copyright (c) 2024-2025, The Linux Foundation.
   SPDX-License-Identifier: Apache-2.0
 #}
 
@@ -15,7 +15,17 @@
   data-arch="{{ board.archs | join(" ") }}"
   data-vendor="{{ board.vendor }}"
   data-socs="{{ board.socs | join(" ") }}"
-  tabindex="0">
+  data-supported-features="
+    {%- set feature_types = [] -%}
+    {%- for target_features in board.supported_features.values() -%}
+      {%- for feature_type in target_features.keys() -%}
+        {%- if feature_type not in feature_types -%}
+          {%- set _ = feature_types.append(feature_type) -%}
+        {%- endif -%}
+      {%- endfor -%}
+    {%- endfor -%}
+    {{- feature_types|join(' ') -}}
+  " tabindex="0">
   <div class="vendor">{{ vendors[board.vendor] }}</div>
   {% if board.image -%}
   <img alt="A picture of the {{ board.full_name }} board"
diff --git a/doc/_extensions/zephyr/domain/templates/board-catalog.html b/doc/_extensions/zephyr/domain/templates/board-catalog.html
index dc3c9147fed..4436d3ae091 100644
--- a/doc/_extensions/zephyr/domain/templates/board-catalog.html
+++ b/doc/_extensions/zephyr/domain/templates/board-catalog.html
@@ -1,5 +1,5 @@
 {#
-  Copyright (c) 2024, The Linux Foundation.
+  Copyright (c) 2024-2025, The Linux Foundation.
   SPDX-License-Identifier: Apache-2.0
 #}
 
@@ -60,6 +60,20 @@
     <select id="soc" name="soc" size="10" multiple></select>
   </div>
 
+  <div class="form-group" style="flex-basis: 100%">
+    <label for="hw-capabilities">Supported Hardware Capabilities</label>
+    <div class="tag-container" id="tag-container">
+      <input list="tag-list" class="tag-input" id="tag-input"
+             placeholder="{% if hw_features_present -%}
+               Type a tag...
+             {%- else -%}
+               List of supported hardware capabilities is not available
+             {%- endif %}"
+             {% if not hw_features_present %}disabled{% endif %}>
+      <datalist id="tag-list"></datalist>
+    </div>
+  </div>
+
 </form>
 
 <div id="form-options" style="text-align: center; margin-bottom: 20px">
diff --git a/doc/_extensions/zephyr/gh_utils.py b/doc/_extensions/zephyr/gh_utils.py
index 67998cd4382..a2774faa1cd 100644
--- a/doc/_extensions/zephyr/gh_utils.py
+++ b/doc/_extensions/zephyr/gh_utils.py
@@ -211,6 +211,8 @@ def git_info_filter(app: Sphinx, pagename) -> tuple[str, str] | None:
             .decode("utf-8")
             .strip()
         )
+        if not date_and_sha1: # added but not committed
+            return None
         date, sha1 = date_and_sha1.split(" ", 1)
         date_object = datetime.fromtimestamp(int(date))
         last_update_fmt = app.config.html_last_updated_fmt
diff --git a/doc/_extensions/zephyr/kconfig/__init__.py b/doc/_extensions/zephyr/kconfig/__init__.py
index fe037d1c894..13ebd0b7d01 100644
--- a/doc/_extensions/zephyr/kconfig/__init__.py
+++ b/doc/_extensions/zephyr/kconfig/__init__.py
@@ -26,6 +26,10 @@
 - kconfig_ext_paths: A list of base paths where to search for external modules
   Kconfig files when they use ``kconfig-ext: True``. The extension will look for
   ${BASE_PATH}/modules/${MODULE_NAME}/Kconfig.
+- kconfig_gh_link_base_url: The base URL for the GitHub links. This is used to
+  generate links to the Kconfig files on GitHub.
+- kconfig_zephyr_version: The Zephyr version. This is used to generate links to
+  the Kconfig files on GitHub.
 """
 
 import argparse
@@ -152,11 +156,18 @@ def kconfig_load(app: Sphinx) -> tuple[kconfiglib.Kconfig, dict[str, str]]:
             if not build_conf:
                 continue
 
+            # Module Kconfig file has already been specified
+            if f"ZEPHYR_{name_var}_KCONFIG" in os.environ:
+                continue
+
             if build_conf.get("kconfig"):
                 kconfig = Path(module.project) / build_conf["kconfig"]
                 os.environ[f"ZEPHYR_{name_var}_KCONFIG"] = str(kconfig)
             elif build_conf.get("kconfig-ext"):
                 for path in app.config.kconfig_ext_paths:
+                    # Assume that the kconfig file exists at this path.
+                    # Technically the cmake variable can be constructed arbitarily
+                    # by "{ext_path}/modules/modules.cmake"
                     kconfig = Path(path) / "modules" / name / "Kconfig"
                     if kconfig.exists():
                         os.environ[f"ZEPHYR_{name_var}_KCONFIG"] = str(kconfig)
@@ -429,8 +440,14 @@ def kconfig_build_resources(app: Sphinx) -> None:
 
         kconfig_db_file = outdir / "kconfig.json"
 
+        kconfig_db = {
+            "gh_base_url": app.config.kconfig_gh_link_base_url,
+            "zephyr_version": app.config.kconfig_zephyr_version,
+            "symbols": db,
+        }
+
         with open(kconfig_db_file, "w") as f:
-            json.dump(db, f)
+            json.dump(kconfig_db, f)
 
     app.config.html_extra_path.append(kconfig_db_file.as_posix())
     app.config.html_static_path.append(RESOURCES_DIR.as_posix())
@@ -461,6 +478,8 @@ def kconfig_install(
 def setup(app: Sphinx):
     app.add_config_value("kconfig_generate_db", False, "env")
     app.add_config_value("kconfig_ext_paths", [], "env")
+    app.add_config_value("kconfig_gh_link_base_url", "", "")
+    app.add_config_value("kconfig_zephyr_version", "", "")
 
     app.add_node(
         KconfigSearchNode,
diff --git a/doc/_extensions/zephyr/kconfig/static/kconfig.mjs b/doc/_extensions/zephyr/kconfig/static/kconfig.mjs
index 6c94845a107..f76bf8baa92 100644
--- a/doc/_extensions/zephyr/kconfig/static/kconfig.mjs
+++ b/doc/_extensions/zephyr/kconfig/static/kconfig.mjs
@@ -5,6 +5,8 @@
 
 const DB_FILE = 'kconfig.json';
 const RESULTS_PER_PAGE_OPTIONS = [10, 25, 50];
+let zephyr_gh_base_url;
+let zephyr_version;
 
 /* search state */
 let db;
@@ -57,13 +59,38 @@ function showProgress(message) {
     p.appendChild(pText);
 }
 
+/**
+ * Generate a GitHub link for a given file path in the Zephyr repository.
+ * @param {string} path - The file path in the repository.
+ * @param {number} [line] - Optional line number to link to.
+ * @param {string} [mode=blob] - The mode (blob or edit). Defaults to 'blob'.
+ * @param {string} [revision=main] - The branch, tag, or commit hash. Defaults to 'main'.
+ * @returns {string} - The generated GitHub URL.
+ */
+function getGithubLink(path, line, mode = "blob", revision = "main") {
+    let url = [
+        zephyr_gh_base_url,
+        mode,
+        revision,
+        path
+    ].join("/");
+
+    if (line !== undefined){
+        url +=  `#L${line}`;
+    }
+
+    return url;
+}
+
+
 /**
  * Render a Kconfig literal property.
  * @param {Element} parent Parent element.
  * @param {String} title Title.
- * @param {String} content Content.
+ * @param {Element} contentElement Content Element.
  */
-function renderKconfigPropLiteral(parent, title, content) {
+function renderKconfigPropLiteralElement(parent, title, contentElement)
+{
     const term = document.createElement('dt');
     parent.appendChild(term);
 
@@ -81,8 +108,18 @@ function renderKconfigPropLiteral(parent, title, content) {
     literal.className = 'pre';
     code.appendChild(literal);
 
-    const literalText = document.createTextNode(content);
-    literal.appendChild(literalText);
+    literal.appendChild(contentElement);
+}
+
+/**
+ * Render a Kconfig literal property.
+ * @param {Element} parent Parent element.
+ * @param {String} title Title.
+ * @param {String} content Content.
+ */
+function renderKconfigPropLiteral(parent, title, content) {
+    const contentElement = document.createTextNode(content);
+    renderKconfigPropLiteralElement(parent, title, contentElement);
 }
 
 /**
@@ -268,7 +305,17 @@ function renderKconfigEntry(entry) {
     renderKconfigPropList(props, 'Implied by', entry.implied_by, true);
     renderKconfigPropList(props, 'Ranges', entry.ranges, false);
     renderKconfigPropList(props, 'Choices', entry.choices, false);
-    renderKconfigPropLiteral(props, 'Location', `${entry.filename}:${entry.linenr}`);
+
+    /* symbol location with permalink */
+    const locationPermalink = document.createElement('a');
+    locationPermalink.href = getGithubLink(entry.filename, entry.linenr, "blob", zephyr_version);
+
+    const locationElement = document.createTextNode(`${entry.filename}:${entry.linenr}`);
+    locationElement.class = "pre";
+    locationPermalink.appendChild(locationElement);
+
+    renderKconfigPropLiteralElement(props, 'Location', locationPermalink);
+
     renderKconfigPropLiteral(props, 'Menu path', entry.menupath);
 
     return container;
@@ -483,7 +530,9 @@ function setupKconfigSearch() {
     fetch(DB_FILE)
         .then(response => response.json())
         .then(json => {
-            db = json;
+            db = json["symbols"];
+            zephyr_gh_base_url = json["gh_base_url"];
+            zephyr_version = json["zephyr_version"];
 
             results.replaceChildren();
 
diff --git a/doc/_extensions/zephyr/link-roles.py b/doc/_extensions/zephyr/link-roles.py
index 64877b63830..b07c36d96aa 100644
--- a/doc/_extensions/zephyr/link-roles.py
+++ b/doc/_extensions/zephyr/link-roles.py
@@ -84,6 +84,12 @@ def role(
             link_text = text
             link = text
 
+        line_ref = ""
+        line_match = re.search(r"(.+?)(?:#(L\d+(?:-L\d+)?))?$", link)
+        if line_match and line_match.group(2):
+            link = line_match.group(1)
+            line_ref = f"?plain=1#{line_match.group(2)}"
+
         module_match = re.search(r"(.+?):\s*(.+)", link)
         if module_match:
             module = module_match.group(1).strip()
@@ -124,7 +130,7 @@ def role(
                     f"{link} not found in {config.link_roles_manifest_project} {trace}"
                 )
 
-        url = f"{baseurl}/{format}/{rev}/{link}"
+        url = f"{baseurl}/{format}/{rev}/{link}{line_ref}"
         node = nodes.reference(rawtext, link_text, refuri=url, **options)
         return [node], []
 
diff --git a/doc/_scripts/gen_boards_catalog.py b/doc/_scripts/gen_boards_catalog.py
old mode 100644
new mode 100755
index db17c67314f..a22ad111176
--- a/doc/_scripts/gen_boards_catalog.py
+++ b/doc/_scripts/gen_boards_catalog.py
@@ -1,7 +1,12 @@
-# Copyright (c) 2024 The Linux Foundation
+# Copyright (c) 2024-2025 The Linux Foundation
 # SPDX-License-Identifier: Apache-2.0
 
 import logging
+import os
+import pickle
+import re
+import subprocess
+import sys
 from collections import namedtuple
 from pathlib import Path
 
@@ -10,12 +15,68 @@
 import yaml
 import zephyr_module
 from gen_devicetree_rest import VndLookup
+from runners.core import ZephyrBinaryRunner
 
 ZEPHYR_BASE = Path(__file__).parents[2]
+ZEPHYR_BINDINGS = ZEPHYR_BASE / "dts/bindings"
+EDT_PICKLE_PATHS = [
+    "zephyr/edt.pickle",
+    "hello_world/zephyr/edt.pickle"  # for board targets using sysbuild
+]
+RUNNERS_YAML_PATHS = [
+    "zephyr/runners.yaml",
+    "hello_world/zephyr/runners.yaml"  # for board targets using sysbuild
+]
 
 logger = logging.getLogger(__name__)
 
 
+class DeviceTreeUtils:
+    _compat_description_cache = {}
+
+    @classmethod
+    def get_first_sentence(cls, text):
+        """Extract the first sentence from a text block (typically a node description).
+
+        Args:
+            text: The text to extract the first sentence from.
+
+        Returns:
+            The first sentence found in the text, or the entire text if no sentence
+            boundary is found.
+        """
+        if not text:
+            return ""
+
+        text = text.replace('\n', ' ')
+        # Split by double spaces to get paragraphs
+        paragraphs = text.split('  ')
+        first_paragraph = paragraphs[0].strip()
+
+        # Look for a period followed by a space in the first paragraph
+        period_match = re.search(r'(.*?)\.(?:\s|$)', first_paragraph)
+        if period_match:
+            return period_match.group(1).strip()
+
+        # If no period in the first paragraph, return the entire first paragraph
+        return first_paragraph
+
+    @classmethod
+    def get_cached_description(cls, node):
+        """Get the cached description for a devicetree node.
+
+        Args:
+            node: A devicetree node object with matching_compat and description attributes.
+
+        Returns:
+            The cached description for the node's compatible, creating it if needed.
+        """
+        return cls._compat_description_cache.setdefault(
+            node.matching_compat,
+            cls.get_first_sentence(node.description)
+        )
+
+
 def guess_file_from_patterns(directory, patterns, name, extensions):
     for pattern in patterns:
         for ext in extensions:
@@ -38,6 +99,7 @@ def guess_image(board_or_shield):
 
     return (img_file.relative_to(ZEPHYR_BASE)).as_posix() if img_file else None
 
+
 def guess_doc_page(board_or_shield):
     patterns = [
         "doc/index.{ext}",
@@ -51,7 +113,117 @@ def guess_doc_page(board_or_shield):
     return doc_file
 
 
-def get_catalog():
+def gather_board_build_info(twister_out_dir):
+    """Gather EDT objects and runners info for each board from twister output directory.
+
+    Args:
+        twister_out_dir: Path object pointing to twister output directory
+
+    Returns:
+        A tuple of two dictionaries:
+           - A dictionary mapping board names to a dictionary of board targets and their EDT.
+             objects.
+             The structure is: {board_name: {board_target: edt_object}}
+           - A dictionary mapping board names to a dictionary of board targets and their runners
+             info.
+             The structure is: {board_name: {board_target: runners_info}}
+    """
+    board_devicetrees = {}
+    board_runners = {}
+    if not twister_out_dir.exists():
+        return board_devicetrees, board_runners
+
+    # Find all build_info.yml files in twister-out
+    build_info_files = list(twister_out_dir.glob("*/**/build_info.yml"))
+
+    for build_info_file in build_info_files:
+        edt_pickle_file = None
+        for pickle_path in EDT_PICKLE_PATHS:
+            maybe_file = build_info_file.parent / pickle_path
+            if maybe_file.exists():
+                edt_pickle_file = maybe_file
+                break
+
+        if not edt_pickle_file:
+            continue
+
+        runners_yaml_file = None
+        for runners_yaml_path in RUNNERS_YAML_PATHS:
+            maybe_file = build_info_file.parent / runners_yaml_path
+            if maybe_file.exists():
+                runners_yaml_file = maybe_file
+                break
+
+        try:
+            with open(build_info_file) as f:
+                build_info = yaml.safe_load(f)
+                board_info = build_info.get('cmake', {}).get('board', {})
+                board_name = board_info.get('name')
+                qualifier = board_info.get('qualifiers', '')
+                revision = board_info.get('revision', '')
+
+                board_target = board_name
+                if revision != '':
+                    board_target = f"{board_target}@{revision}"
+                if qualifier:
+                    board_target = f"{board_target}/{qualifier}"
+
+                with open(edt_pickle_file, 'rb') as f:
+                    edt = pickle.load(f)
+                    board_devicetrees.setdefault(board_name, {})[board_target] = edt
+
+                if runners_yaml_file:
+                    with open(runners_yaml_file) as f:
+                        runners_yaml = yaml.safe_load(f)
+                        board_runners.setdefault(board_name, {})[board_target] = (
+                            runners_yaml
+                        )
+
+        except Exception as e:
+            logger.error(f"Error processing build info file {build_info_file}: {e}")
+
+    return board_devicetrees, board_runners
+
+
+def run_twister_cmake_only(outdir):
+    """Run twister in cmake-only mode to generate build info files.
+
+    Args:
+        outdir: Directory where twister should output its files
+    """
+    twister_cmd = [
+        sys.executable,
+        f"{ZEPHYR_BASE}/scripts/twister",
+        "-T", "samples/hello_world/",
+        "--all",
+        "-M",
+        *[arg for path in EDT_PICKLE_PATHS for arg in ('--keep-artifacts', path)],
+        *[arg for path in RUNNERS_YAML_PATHS for arg in ('--keep-artifacts', path)],
+        "--cmake-only",
+        "--outdir", str(outdir),
+    ]
+
+    minimal_env = {
+        'PATH': os.environ.get('PATH', ''),
+        'ZEPHYR_BASE': str(ZEPHYR_BASE),
+        'HOME': os.environ.get('HOME', ''),
+        'PYTHONPATH': os.environ.get('PYTHONPATH', '')
+    }
+
+    try:
+        subprocess.run(twister_cmd, check=True, cwd=ZEPHYR_BASE, env=minimal_env)
+    except subprocess.CalledProcessError as e:
+        logger.warning(f"Failed to run Twister, list of hw features might be incomplete.\n{e}")
+
+
+def get_catalog(generate_hw_features=False):
+    """Get the board catalog.
+
+    Args:
+        generate_hw_features: If True, run twister to generate hardware features information.
+    """
+    import tempfile
+
     vnd_lookup = VndLookup(ZEPHYR_BASE / "dts/bindings/vendor-prefixes.txt", [])
 
     module_settings = {
@@ -78,6 +250,16 @@ def get_catalog():
     boards = list_boards.find_v2_boards(args_find_boards)
     systems = list_hardware.find_v2_systems(args_find_boards)
     board_catalog = {}
+    board_devicetrees = {}
+    board_runners = {}
+
+    if generate_hw_features:
+        logger.info("Running twister in cmake-only mode to get Devicetree files for all boards")
+        with tempfile.TemporaryDirectory() as tmp_dir:
+            run_twister_cmake_only(tmp_dir)
+            board_devicetrees, board_runners = gather_board_build_info(Path(tmp_dir))
+    else:
+        logger.info("Skipping generation of supported hardware features.")
 
     for board in boards.values():
         # We could use board.vendor but it is often incorrect. Instead, deduce vendor from
@@ -91,6 +273,82 @@ def get_catalog():
                 vendor = folder.name
                 break
 
+        socs = {soc.name for soc in board.socs}
+        full_name = board.full_name or board.name
+        doc_page = guess_doc_page(board)
+
+        supported_features = {}
+
+        # Use pre-gathered build info and DTS files
+        if board.name in board_devicetrees:
+            for board_target, edt in board_devicetrees[board.name].items():
+                features = {}
+                for node in edt.nodes:
+                    if node.binding_path is None:
+                        continue
+
+                    binding_path = Path(node.binding_path)
+                    is_custom_binding = False
+                    if binding_path.is_relative_to(ZEPHYR_BINDINGS):
+                        binding_type = binding_path.relative_to(ZEPHYR_BINDINGS).parts[0]
+                    else:
+                        binding_type = "misc"
+                        is_custom_binding = True
+
+
+                    if node.matching_compat is None:
+                        continue
+
+                    # skip "zephyr,xxx" compatibles
+                    if node.matching_compat.startswith("zephyr,"):
+                        continue
+
+                    description = DeviceTreeUtils.get_cached_description(node)
+                    filename = node.filename
+                    lineno = node.lineno
+                    locations = set()
+                    if Path(filename).is_relative_to(ZEPHYR_BASE):
+                        filename = Path(filename).relative_to(ZEPHYR_BASE)
+                        if filename.parts[0] == "boards":
+                            locations.add("board")
+                        else:
+                            locations.add("soc")
+
+                    existing_feature = features.get(binding_type, {}).get(
+                        node.matching_compat
+                    )
+
+                    node_info = {"filename": str(filename), "lineno": lineno}
+                    node_list_key = "okay_nodes" if node.status == "okay" else "disabled_nodes"
+
+                    if existing_feature:
+                        locations.update(existing_feature["locations"])
+                        existing_feature.setdefault(node_list_key, []).append(node_info)
+                        continue
+
+                    feature_data = {
+                        "description": description,
+                        "custom_binding": is_custom_binding,
+                        "locations": locations,
+                        "okay_nodes": [],
+                        "disabled_nodes": [],
+                    }
+                    feature_data[node_list_key].append(node_info)
+
+                    features.setdefault(binding_type, {})[node.matching_compat] = feature_data
+
+                # Store features for this specific target
+                supported_features[board_target] = features
+
+        board_runner_info = {}
+        if board.name in board_runners:
+            # Assume all board targets have the same runners so only consider the runners
+            # for the first board target.
+            r = list(board_runners[board.name].values())[0]
+            board_runner_info["runners"] = r.get("runners")
+            board_runner_info["flash-runner"] = r.get("flash-runner")
+            board_runner_info["debug-runner"] = r.get("debug-runner")
+
         # Grab all the twister files for this board and use them to figure out all the archs it
         # supports.
         archs = set()
@@ -103,18 +361,25 @@ def get_catalog():
             except Exception as e:
                 logger.error(f"Error parsing twister file {twister_file}: {e}")
 
-        socs = {soc.name for soc in board.socs}
-        full_name = board.full_name or board.name
-        doc_page = guess_doc_page(board)
+        if doc_page and doc_page.is_relative_to(ZEPHYR_BASE):
+            doc_page_path = doc_page.relative_to(ZEPHYR_BASE).as_posix()
+        else:
+            doc_page_path = None
 
         board_catalog[board.name] = {
             "name": board.name,
             "full_name": full_name,
-            "doc_page": doc_page.relative_to(ZEPHYR_BASE).as_posix() if doc_page else None,
+            "doc_page": doc_page_path,
             "vendor": vendor,
             "archs": list(archs),
             "socs": list(socs),
+            "revision_default": board.revision_default,
+            "supported_features": supported_features,
             "image": guess_image(board),
+            # runners
+            "supported_runners": board_runner_info.get("runners", []),
+            "flash_runner": board_runner_info.get("flash-runner", ""),
+            "debug_runner": board_runner_info.get("debug-runner", ""),
         }
 
     socs_hierarchy = {}
@@ -123,8 +388,16 @@ def get_catalog():
         series = soc.series or "<no series>"
         socs_hierarchy.setdefault(family, {}).setdefault(series, []).append(soc.name)
 
+    available_runners = {}
+    for runner in ZephyrBinaryRunner.get_runners():
+        available_runners[runner.name()] = {
+            "name": runner.name(),
+            "commands": runner.capabilities().commands,
+        }
+
     return {
         "boards": board_catalog,
         "vendors": {**vnd_lookup.vnd2vendor, "others": "Other/Unknown"},
         "socs": socs_hierarchy,
+        "runners": available_runners,
     }
diff --git a/doc/_scripts/gen_devicetree_rest.py b/doc/_scripts/gen_devicetree_rest.py
index 9a28b591f29..908cfb0278b 100644
--- a/doc/_scripts/gen_devicetree_rest.py
+++ b/doc/_scripts/gen_devicetree_rest.py
@@ -580,7 +580,14 @@ def print_binding_page(binding, base_names, vnd_lookup, driver_sources,dup_compa
 
     {bus_help}
     ''', string_io)
-    print(to_code_block(binding.description.strip()), file=string_io)
+
+    if binding.title:
+        description = ("\n\n"
+                       .join([binding.title, binding.description])
+                       .strip())
+    else:
+        description = binding.description.strip()
+    print(to_code_block(description), file=string_io)
 
     # Properties.
     print_block('''\
diff --git a/doc/_scripts/redirects.py b/doc/_scripts/redirects.py
index 87d54e5032e..72ae07b5d54 100644
--- a/doc/_scripts/redirects.py
+++ b/doc/_scripts/redirects.py
@@ -193,7 +193,6 @@
     ('reference/peripherals/i2c', 'hardware/peripherals/i2c'),
     ('reference/peripherals/index', 'hardware/peripherals/index'),
     ('reference/peripherals/ipm', 'hardware/peripherals/ipm'),
-    ('reference/peripherals/kscan', 'hardware/peripherals/kscan'),
     ('reference/peripherals/led', 'hardware/peripherals/led'),
     ('reference/peripherals/mbox', 'hardware/peripherals/mbox'),
     ('reference/peripherals/mdio', 'hardware/peripherals/mdio'),
@@ -210,7 +209,7 @@
     ('reference/peripherals/uart', 'hardware/peripherals/uart'),
     ('reference/peripherals/video', 'hardware/peripherals/video'),
     ('reference/pm/index', 'services/pm/api/index'),
-    ('reference/settings/index', 'services/settings/index'),
+    ('reference/settings/index', 'services/storage/settings/index'),
     ('reference/shell/index', 'services/shell/index'),
     ('reference/storage/fcb/fcb', 'services/storage/fcb/fcb'),
     ('reference/storage/index', 'services/storage/index'),
@@ -284,7 +283,6 @@
     ('samples/boards/stm32/sensortile_box_pro/sensors-on-board/README', 'samples/boards/st/sensortile_box_pro/sensors-on-board/README'),
     ('samples/boards/stm32/steval_stwinbx1/sensors/README', 'samples/boards/st/steval_stwinbx1/sensors/README'),
     ('samples/drivers/adc/README', 'samples/drivers/adc/adc_dt/README'),
-    ('samples/drivers/kscan_touch', 'samples/subsys/input/input'),
     ('samples/drivers/led_apa102/README', 'samples/drivers/led_strip/README'),
     ('samples/drivers/led_is31fl3194/README', 'samples/drivers/led/is31fl3194/README'),
     ('samples/drivers/led_is31fl3216a/README', 'samples/drivers/led/is31fl3216a/README'),
@@ -308,5 +306,7 @@
     ('samples/subsys/video/video', 'samples/drivers/video/video'),
     ('services/crypto/tinycrypt', 'services/crypto/psa_crypto'),
     ('services/portability/posix', 'services/portability/posix/index'),
+    ('services/secure_storage', 'services/storage/secure_storage/index'),
+    ('services/settings/index', 'services/storage/settings/index'),
     # zephyr-keep-sorted-stop
 ]
diff --git a/doc/_static/css/custom.css b/doc/_static/css/custom.css
index 1bc107e11c2..2fd1045d81e 100644
--- a/doc/_static/css/custom.css
+++ b/doc/_static/css/custom.css
@@ -1,6 +1,7 @@
 /**
  * Copyright (c) 2019-2020, Juan Linietsky, Ariel Manzur and the Godot community
  * Copyright (c) 2021, Teslabs Engineering S.L.
+ * Copyright (c) 2023-2025, The Linux Foundation.
  * SPDX-License-Identifier: CC-BY-3.0
  *
  * Various tweaks to the Read the Docs theme to better conform with Zephyr's
@@ -11,6 +12,7 @@
      /* Use system font stacks for better performance (no Web fonts required) */
      --system-font-family: system-ui, -apple-system, "Segoe UI", Roboto, "Helvetica Neue", Arial, "Noto Sans", sans-serif, "Apple Color Emoji", "Segoe UI Emoji", "Segoe UI Symbol", "Noto Color Emoji";
      --header-font-family: Seravek, 'Gill Sans Nova', Ubuntu, Calibri, 'DejaVu Sans', source-sans-pro, sans-serif;
+     --monospace-font-family: 'SF Mono', 'Monaco', 'Inconsolata', 'Fira Mono', 'Droid Sans Mono', 'Source Code Pro', monospace;
  }
 
 body,
@@ -921,6 +923,10 @@ dark-mode-toggle::part(toggleLabel){
   font-size: unset;
 }
 
+div.graphviz > object {
+    filter: var(--graphviz-filter);
+}
+
 /* Home page grid display */
 .grid {
     list-style-type: none !important;
@@ -1111,67 +1117,3 @@ li>a.code-sample-link.reference.internal {
 li>a.code-sample-link.reference.internal.current {
     text-decoration: underline;
 }
-
-/* Board overview "card" on board documentation pages */
-.sidebar.board-overview {
-    border-radius: 12px;
-    padding: 0px;
-    background: var(--admonition-note-background-color);
-    color: var(--admonition-note-title-color);
-    border-color: var(--admonition-note-title-background-color);
-}
-
-@media screen and (max-width: 480px) {
-    .sidebar.board-overview {
-        float: none;
-        margin-left: 0;
-    }
-}
-
-.sidebar.board-overview .sidebar-title {
-    font-family: var(--header-font-family);
-    background: var(--admonition-note-title-background-color);
-    color: var(--admonition-note-title-color);
-    border-radius: 12px 12px 0px 0px;
-    margin: 0px;
-    text-align: center;
-}
-
-.sidebar.board-overview * {
-    color: var(--admonition-note-color);
-}
-
-.sidebar.board-overview figure {
-    padding: 1rem;
-    margin-bottom: -1rem;
-}
-
-.sidebar.board-overview figure img {
-    height: auto !important;
-}
-
-.sidebar.board-overview figure figcaption p {
-    margin-bottom: 0px;
-}
-
-.sidebar.board-overview dl.field-list {
-    align-items: center;
-    margin-top: 12px !important;
-    margin-bottom: 12px !important;
-    grid-template-columns: auto 1fr !important;
-    padding-right: 1em;
-}
-
-.sidebar.board-overview dl.field-list > dt {
-    background: transparent !important;
-}
-
-.sidebar.board-overview dl.field-list>dd {
-    margin-left: 1em;
-    text-overflow: ellipsis;
-    overflow: hidden;
-}
-
-.sidebar.board-overview dl.field-list>dd code {
-    font-size: 0.9em;
-}
diff --git a/doc/_static/css/dark.css b/doc/_static/css/dark.css
index 47d555242f6..bb1c20c0b5c 100644
--- a/doc/_static/css/dark.css
+++ b/doc/_static/css/dark.css
@@ -93,4 +93,6 @@
     --btn-neutral-background-color: #404040;
     --btn-neutral-hover-background-color: #505050;
     --footer-color: #aaa;
+
+    --graphviz-filter: invert(0.9) brightness(1.2);
 }
diff --git a/doc/_static/css/light.css b/doc/_static/css/light.css
index 0389650278c..757ec6f1e1b 100644
--- a/doc/_static/css/light.css
+++ b/doc/_static/css/light.css
@@ -91,4 +91,6 @@
     --btn-neutral-background-color: #f3f6f6;
     --btn-neutral-hover-background-color: #e5ebeb;
     --footer-color: #808080;
+
+    --graphviz-filter: none;
 }
diff --git a/doc/build/cmake/index.rst b/doc/build/cmake/index.rst
index ee9bde7206f..2b180eaa5d9 100644
--- a/doc/build/cmake/index.rst
+++ b/doc/build/cmake/index.rst
@@ -43,6 +43,9 @@ source file :file:`src/main.c`, behavior that we surely do not want. The
 ``PUBLIC`` keyword could however be useful when modifying the include
 paths of a target library.
 
+When introducing build system code using CMake or adding new CMake files,
+please follow the style guidelines outlined :ref:`here <cmake-style>`.
+
 
 Build and Configuration Phases
 ==============================
diff --git a/doc/build/dts/api/api.rst b/doc/build/dts/api/api.rst
index f604f29d9e0..6fe1fb7fd1b 100644
--- a/doc/build/dts/api/api.rst
+++ b/doc/build/dts/api/api.rst
@@ -422,6 +422,9 @@ device.
      - A node whose ``reg`` is used by the OpenAMP subsystem to determine the
        base address and size of the shared memory (SHM) usable for
        interprocess-communication (IPC)
+   * - zephyr,ipc_rsc_table
+     - Specifies a memory region that will be used for the OpenAMP resource table.
+       Only needed if :kconfig:option:`CONFIG_OPENAMP_COPY_RSC_TABLE` is enabled.
    * - zephyr,itcm
      - Instruction Tightly Coupled Memory node on some Arm SoCs
    * - zephyr,log-uart
@@ -459,3 +462,11 @@ device.
        WS2812 GPIO driver
    * - zephyr,touch
      - touchscreen controller device node.
+   * - mcuboot,ram-load-dev
+     - When a Zephyr application is built to be loaded to RAM by MCUboot, with
+       :kconfig:option:`CONFIG_MCUBOOT_BOOTLOADER_MODE_SINGLE_APP_RAM_LOAD`,
+       this property is used to tell MCUboot the load address of the image, which
+       will be the ``reg`` of the chosen node.
+   * - zephyr,boot-mode
+     - Used for :ref:`boot_mode_api` selection, part of :ref:`retention_api`, which specifies
+       what image on a device should be booted.
diff --git a/doc/build/dts/bindings-syntax.rst b/doc/build/dts/bindings-syntax.rst
index def71687fb3..fea69ee5911 100644
--- a/doc/build/dts/bindings-syntax.rst
+++ b/doc/build/dts/bindings-syntax.rst
@@ -19,6 +19,16 @@ like this:
 
 .. code-block:: yaml
 
+   # When the description text is too long, this field can
+   # be used to improve readability, e.g.:
+   #
+   # title: Binding the device's hardware model.
+   #
+   # description |
+   #   A piece of content with 20 lines.
+   #   ...
+   title: Concise title for the long description [optional]
+
    # A high level description of the device the binding applies to:
    description: |
       This is the Vendomatic company's foo-device.
@@ -58,6 +68,14 @@ like this:
 
 These keys are explained in the following sections.
 
+.. _dt-bindings-title:
+
+Title
+*****
+
+Short description of the bound device, typically the hardware model.
+(It's optional.)
+
 .. _dt-bindings-description:
 
 Description
diff --git a/doc/build/dts/bindings-upstream.rst b/doc/build/dts/bindings-upstream.rst
index b33b7f92452..6a9cb666a42 100644
--- a/doc/build/dts/bindings-upstream.rst
+++ b/doc/build/dts/bindings-upstream.rst
@@ -83,6 +83,8 @@ style:
 
 .. code-block:: yaml
 
+   title: I'm sure you need a short title.
+
    description: |
      My very long string
      goes here.
diff --git a/doc/build/dts/phandles.rst b/doc/build/dts/phandles.rst
index 65d8a16d7e1..a3760864f55 100644
--- a/doc/build/dts/phandles.rst
+++ b/doc/build/dts/phandles.rst
@@ -324,7 +324,7 @@ specifier space ``foo``. For example:
      pwms:
        type: phandle-array
 
-The ``dmas`` property's specifier space is "dma". The ``pwm`` property's
+The ``dmas`` property's specifier space is "dma". The ``pwms`` property's
 specifier space is ``pwm``.
 
 Special case: GPIO
diff --git a/doc/build/dts/zephyr-user-node.rst b/doc/build/dts/zephyr-user-node.rst
index 9cd0226eb9a..f2fcea6f94b 100644
--- a/doc/build/dts/zephyr-user-node.rst
+++ b/doc/build/dts/zephyr-user-node.rst
@@ -79,19 +79,16 @@ device pointers like this:
    const struct device *my_device =
    	DEVICE_DT_GET(DT_PROP(ZEPHYR_USER_NODE, handle));
 
-   #define PHANDLE_TO_DEVICE(node_id, prop, idx) \
-        DEVICE_DT_GET(DT_PHANDLE_BY_IDX(node_id, prop, idx)),
-
    /*
     * Same thing as:
     *
     * ... *my_devices[] = {
     *         DEVICE_DT_GET(DT_NODELABEL(gpio0)),
-    *         DEVICE_DT_GET(DT_NODELABEL(gpio1)),
+    *         DEVICE_DT_GET(DT_NODELABEL(gpio1))
     * };
     */
    const struct device *my_devices[] = {
-   	DT_FOREACH_PROP_ELEM(ZEPHYR_USER_NODE, handles, PHANDLE_TO_DEVICE)
+        DT_FOREACH_PROP_ELEM_SEP(ZEPHYR_USER_NODE, handles, DEVICE_DT_GET_BY_IDX, (,))
    };
 
 GPIOs
diff --git a/doc/build/kconfig/setting.rst b/doc/build/kconfig/setting.rst
index 7d6d1acdc14..6fe1feaed7d 100644
--- a/doc/build/kconfig/setting.rst
+++ b/doc/build/kconfig/setting.rst
@@ -147,13 +147,6 @@ used.
 
    3. From the CMake variable cache
 
-   Furthermore if ``CONF_FILE`` is set as single configuration file of the
-   form :file:`prj_<build>.conf` and if file
-   :file:`boards/<BOARD>_<build>.conf` exists in same folder as file
-   :file:`prj_<build>.conf`, the result of merging :file:`prj_<build>.conf` and
-   :file:`boards/<BOARD>_<build>.conf` is used - note that this feature is
-   deprecated, :ref:`application-file-suffixes` should be used instead.
-
 #. Otherwise, if :file:`boards/<BOARD>.conf` exists in the application
    configuration directory, the result of merging it with :file:`prj.conf` is
    used.
diff --git a/doc/build/kconfig/tips.rst b/doc/build/kconfig/tips.rst
index d79c5d122d7..1225d849147 100644
--- a/doc/build/kconfig/tips.rst
+++ b/doc/build/kconfig/tips.rst
@@ -876,31 +876,10 @@ For a Kconfig symbol that enables a driver/subsystem FOO, consider having just
 usually be clear in the context of an option that can be toggled on/off, and
 makes things consistent.
 
+Style
+=====
 
-Header comments and other nits
-==============================
-
-A few formatting nits, to help keep things consistent:
-
-- Use this format for any header comments at the top of ``Kconfig`` files:
-
-  .. code-block:: none
-
-     # <Overview of symbols defined in the file, preferably in plain English>
-     (Blank line)
-     # Copyright (c) 2019 ...
-     # SPDX-License-Identifier: <License>
-     (Blank line)
-     (Kconfig definitions)
-
-- Format comments as ``# Comment`` rather than ``#Comment``
-
-- Put a blank line before/after each top-level ``if`` and ``endif``
-
-- Use a single tab for each indentation
-
-- Indent help text with two extra spaces
-
+See :ref:`coding_style` for style guidelines.
 
 Lesser-known/used Kconfig features
 **********************************
diff --git a/doc/build/sysbuild/images.rst b/doc/build/sysbuild/images.rst
new file mode 100644
index 00000000000..3ccfd873e16
--- /dev/null
+++ b/doc/build/sysbuild/images.rst
@@ -0,0 +1,441 @@
+.. _sysbuild_images:
+
+Sysbuild images
+###############
+
+Sysbuild can be used to add additional images to builds, these can be added by projects or boards
+though at present must be Zephyr applications.
+
+Methods of adding images
+************************
+
+Images can be added to project or projects in various ways, multiple ways can be used
+simultaneously, they can be added in the following ways:
+
+Applications
+============
+
+Applications can add sysbuild images using the ``sysbuild.cmake`` file in the application
+directory, the inclusion of images can be controlled with a ``Kconfig.sysbuild`` file in the
+application directory.
+
+Boards
+======
+
+Boards can add sysbuild images by using the ``sysbuild.cmake`` file in the board directory, the
+inclusion of images can be controlled with a ``Kconfig.sysbuild`` file in the board directory.
+
+SoCs
+====
+
+SoCs can add sysbuild images by using the ``sysbuild.cmake`` file in the soc directory.
+
+Modules
+=======
+
+:ref:`modules` can add sysbuild images with the ``sysbuild-cmake`` and ``sysbuild-kconfig``
+options in a ``module.yml`` file, see :ref:`sysbuild_module_integration` for details.
+
+Adding images
+*************
+
+Images can be added in one of two ways:
+
+Single unchangeable image
+=========================
+
+With this setup, the image to be added is fixed to a specific application and cannot be changed
+(although it cannot be changed to another image, the version of the image itself can be changed by
+use of a west manifest bringing in a different version of the application repo or from an
+alternate source, assuming that the image is in it's own repository).
+
+.. note::
+
+   This method should only be used if the image is locked to a specific interface and has no
+   extensibility.
+
+An example of how to create such an image, this assumes that a
+:ref:`Zephyr application has been created <application>`:
+
+.. tabs::
+
+   .. group-tab:: ``Kconfig.sysbuild``
+
+      .. code-block:: kconfig
+
+         config MY_IMAGE
+                 bool "Include my amazing image"
+                 help
+                   If enabled, will include my amazing image in the build which does...
+
+      .. note::
+
+         Remember to have ``source "share/sysbuild/Kconfig"`` in the file if this
+         is being applied in an application ``Kconfig.sysbuild`` file.
+
+
+   .. group-tab:: ``sysbuild.cmake``
+
+      .. code-block:: cmake
+
+         if(SB_CONFIG_MY_IMAGE)
+           ExternalZephyrProject_Add(
+             APPLICATION my_image
+             SOURCE_DIR ${ZEPHYR_MY_IMAGE_MODULE_DIR}/path/to/my_image
+           )
+         endif()
+
+Additional dependency ordering can be set here if needed, see
+:ref:`sysbuild_zephyr_application_dependencies` for details, image configuration can also be set
+here, see :ref:`sysbuild_images_config` for details.
+
+This image can be enabled when building with west like so:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: <app>
+   :board: nrf52840dk/nrf52840
+   :goals: build
+   :west-args: --sysbuild
+   :gen-args: -DSB_CONFIG_MY_IMAGE=y
+   :compact:
+
+Extensible changeable image
+===========================
+
+With this setup, the image to be added can be one of any number of possible applications which the
+user has selection over, this list of selections can also be extended downstream to add additional
+options for out-of-tree specific applications that are not available in upstream Zephyr. This is
+more complex to create but is the preferred method for adding images to upstream Zephyr.
+
+.. tabs::
+
+   .. group-tab:: ``Kconfig.sysbuild``
+
+      .. code-block:: kconfig
+
+         config SUPPORT_OTHER_APP
+                 bool
+                 # Conditions can be placed here if this application type is only usable on certain platforms
+                 default y
+
+         config SUPPORT_OTHER_APP_MY_IMAGE
+                 bool
+                 # Conditions can be placed here if this image is only usable on certain platforms
+                 default y
+
+         choice OTHER_APP
+                 prompt "Other app image"
+                 # Defaults can be specified here if a default image should be loaded if e.g. it is supported
+                 default OTHER_APP_NONE
+                 depends on SUPPORT_OTHER_APP
+
+         config OTHER_APP_IMAGE_NONE
+                 bool "None"
+                 help
+                   Do not Include an other app image in the build.
+
+         config OTHER_APP_IMAGE_MY_IMAGE
+                 bool "my_image"
+                 depends on SUPPORT_OTHER_APP_MY_IMAGE
+                 help
+                   Include my amazing image as the other app image to use, which does...
+
+         endchoice
+
+         config OTHER_APP_IMAGE_NAME
+                 string
+                 default "my_image" if OTHER_APP_IMAGE_MY_IMAGE
+                 help
+                   Name of other app image.
+
+         config OTHER_APP_IMAGE_PATH
+                 string
+                 default "${ZEPHYR_MY_IMAGE_MODULE_DIR}/path/to/my_image" if OTHER_APP_IMAGE_MY_IMAGE
+                 help
+                   Source directory of other app image.
+
+      .. note::
+
+         Remember to have ``source "${ZEPHYR_BASE}/share/sysbuild/Kconfig"`` in the file if this
+         is being applied in an application ``Kconfig.sysbuild`` file.
+
+   .. group-tab:: ``sysbuild.cmake``
+
+      .. code-block:: cmake
+
+         if(SB_CONFIG_OTHER_APP_IMAGE_PATH)
+           ExternalZephyrProject_Add(
+             APPLICATION ${SB_CONFIG_OTHER_APP_IMAGE_NAME}
+             SOURCE_DIR ${SB_CONFIG_OTHER_APP_IMAGE_PATH}
+           )
+         endif()
+
+Additional dependency ordering can be set here if needed, see
+:ref:`sysbuild_zephyr_application_dependencies` for details, image configuration can also be set
+here, see :ref:`sysbuild_images_config` for details.
+
+This secondary image can be enabled when building with west like so:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: <app>
+   :board: nrf52840dk/nrf52840
+   :goals: build
+   :west-args: --sysbuild
+   :gen-args: -DSB_CONFIG_MY_IMAGE=y
+   :compact:
+
+This can then be extended by :ref:`modules` like so:
+
+.. tabs::
+
+   .. group-tab:: ``Kconfig.sysbuild``
+
+      .. code-block:: kconfig
+
+         config SUPPORT_OTHER_APP_MY_SECOND_IMAGE
+                 bool
+                 default y
+
+         choice OTHER_APP
+
+         config OTHER_APP_IMAGE_MY_SECOND_IMAGE
+                 bool "my_second_image"
+                 depends on SUPPORT_OTHER_APP_MY_SECOND_IMAGE
+                 help
+                   Include my other amazing image as the other app image to use, which does...
+
+         endchoice
+
+         config OTHER_APP_IMAGE_NAME
+                 default "my_second_image" if OTHER_APP_IMAGE_MY_SECOND_IMAGE
+
+         config OTHER_APP_IMAGE_PATH
+                 default "${ZEPHYR_MY_SECOND_IMAGE_MODULE_DIR}/path/to/my_second_image" if OTHER_APP_IMAGE_MY_SECOND_IMAGE
+
+As can be seen, no additional CMake changes are needed to add an alternative image as the base
+CMake code will add the replacement image instead of the original image, if selected.
+
+This alternative secondary image can be enabled when building with west like so:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: <app>
+   :board: nrf52840dk/nrf52840
+   :goals: build
+   :west-args: --sysbuild
+   :gen-args: -DSB_CONFIG_MY_SECOND_IMAGE=y
+   :compact:
+
+.. _sysbuild_images_config:
+
+Image configuration
+*******************
+
+Sysbuild supports being able to set image configuration (Kconfig options) and also supports
+reading the output of image configuration (Kconfig) which can be used to allow an
+option to be added to sysbuild itself and then to configure it globally or selectively.
+
+Setting image configuration
+===========================
+
+Kconfig
+-------
+
+Sysbuild can be used to set image configuration **before the CMake configuration of images takes
+place**. An important note about setting Kconfig options in images is that these are persistent
+and cannot be changed by the images. The following functions can be used to set configuration on
+an image:
+
+.. code-block:: cmake
+
+   set_config_bool(<image> CONFIG_<setting> <value>)
+   set_config_string(<image> CONFIG_<setting> <value>)
+   set_config_int(<image> CONFIG_<setting> <value>)
+
+For example, to change the default image to output a hex file:
+
+.. code-block:: cmake
+
+   set_config_bool(${DEFAULT_IMAGE} CONFIG_BUILD_OUTPUT_HEX y)
+
+These can safely be used in an application, board or SoC ``sysbuild.cmake`` file, as that file is
+included before the image CMake processes are invoked. When extending
+:ref:`sysbuild using modules <sysbuild_module_integration>` the pre-CMake hook should be used
+instead, for example:
+
+.. code-block:: cmake
+
+   function(${SYSBUILD_CURRENT_MODULE_NAME}_pre_cmake)
+     cmake_parse_arguments(PRE_CMAKE "" "" "IMAGES" ${ARGN})
+
+     foreach(image ${PRE_CMAKE_IMAGES})
+       set_config_bool(${image} CONFIG_BUILD_OUTPUT_HEX y)
+     endforeach()
+   endfunction()
+
+Image configuration script
+==========================
+
+An image configuration script is a CMake file that can be used to configure an image with common
+configuration values, multiple can be used per image, the configuration should be transferrable to
+different images to correctly configure them based upon options set in sysbuild. MCUboot
+configuration options are configured in both the application the MCUboot image using this method
+which allows sysbuild to be the central location for things like the signing key which are then
+kept in-sync in the main application bootloader images.
+
+Inside image configuration scripts, the ``ZCMAKE_APPLICATION`` variable is set to the name of the
+application being configured, the ``set_config_*`` sysbuild CMake functions can be used to set
+configuration and the sysbuild Kconfig can be read, for example:
+
+.. code-block:: cmake
+
+   if(SB_CONFIG_BOOTLOADER_MCUBOOT AND "${SB_CONFIG_SIGNATURE_TYPE}" STREQUAL "NONE")
+     set_config_bool(${ZCMAKE_APPLICATION} CONFIG_MCUBOOT_GENERATE_UNSIGNED_IMAGE y)
+   endif()
+
+Image configuration script (module/application)
+-----------------------------------------------
+
+Module/application image configuration scripts can be set from module or application code, this
+must be done in a ``sysbuild.cmake`` file for an application. This can be used to add an image
+configuration script as follows:
+
+.. tabs::
+
+   .. group-tab:: ``sysbuild.cmake``
+
+      .. code-block:: cmake
+
+         # This applies the image configuration script to the default image only
+         get_property(tmp_conf_scripts TARGET ${DEFAULT_IMAGE} PROPERTY IMAGE_CONF_SCRIPT)
+         list(APPEND tmp_conf_scripts "${CMAKE_SOURCE_DIR}/image_configurations/MY_CUSTOM_TYPE_image_default.cmake")
+         set_target_properties(${DEFAULT_IMAGE} PROPERTIES IMAGE_CONF_SCRIPT "${tmp_conf_scripts}")
+
+
+   .. group-tab:: Module CMake
+
+      .. code-block:: cmake
+
+         function(${SYSBUILD_CURRENT_MODULE_NAME}_pre_cmake)
+           cmake_parse_arguments(PRE_CMAKE "" "" "IMAGES" ${ARGN})
+
+           # This applies the image configuration script to all images
+           foreach(image ${PRE_CMAKE_IMAGES})
+             get_property(tmp_conf_scripts TARGET ${image} PROPERTY IMAGE_CONF_SCRIPT)
+             list(APPEND tmp_conf_scripts "${CMAKE_SOURCE_DIR}/image_configurations/MY_CUSTOM_TYPE_image_default.cmake")
+             set_target_properties(${image} PROPERTIES IMAGE_CONF_SCRIPT "${tmp_conf_scripts}")
+           endforeach()
+         endfunction(${SYSBUILD_CURRENT_MODULE_NAME}_pre_cmake)
+
+Image configuration script (Zephyr-wide)
+----------------------------------------
+
+Global Zephyr provided image configuration scripts, which allow specifying the type when using
+``ExternalZephyrProject_Add()`` require changes to sysbuild code in Zephyr. This should only be
+added to when adding a new type that any project should be able to select, generally this should
+only be needed for upstream Zephyr though forked versions of Zephyr might use this to add
+additional types without restriction.
+
+Image configuration has an allow-list of names which must be set in the Zephyr file
+:zephyr_file:`share/sysbuild/cmake/modules/sysbuild_extensions.cmake` in the
+``ExternalZephyrProject_Add`` function. After adding a new type, it can be used when adding a
+sysbuild image, for example:
+
+.. tabs::
+
+   .. group-tab:: ``sysbuild_extensions.cmake``
+
+      Full file path: ``share/sysbuild/cmake/modules/sysbuild_extensions.cmake``
+
+      .. code-block:: cmake
+
+         # ...
+         # Usage:
+         #   ExternalZephyrProject_Add(APPLICATION <name>
+         #                             SOURCE_DIR <dir>
+         #                             [BOARD <board> [BOARD_REVISION <revision>]]
+         #                             [APP_TYPE <MAIN|BOOTLOADER|MY_CUSTOM_TYPE>]
+         #   )
+         # ...
+         # APP_TYPE <MAIN|BOOTLOADER|MY_CUSTOM_TYPE>: Application type.
+         #                                            MAIN indicates this application is the main application
+         #                                            and where user defined settings should be passed on as-is
+         #                                            except for multi image build flags.
+         #                                            For example, -DCONF_FILES=<files> will be passed on to the
+         #                                            MAIN_APP unmodified.
+         #                                            BOOTLOADER indicates this app is a bootloader
+         #                                            MY_CUSTOM_TYPE indicates this app is...
+         # ...
+         function(ExternalZephyrProject_Add)
+           set(app_types MAIN BOOTLOADER MY_CUSTOM_TYPE)
+         # ...
+
+   .. group-tab:: ``sysbuild.cmake``
+
+      .. code-block:: cmake
+
+         if(SB_CONFIG_OTHER_APP_IMAGE_PATH)
+           ExternalZephyrProject_Add(
+             APPLICATION ${SB_CONFIG_OTHER_APP_IMAGE_NAME}
+             SOURCE_DIR ${SB_CONFIG_OTHER_APP_IMAGE_PATH}
+             APP_TYPE MY_CUSTOM_TYPE
+           )
+         endif()
+
+
+   .. group-tab:: ``MY_CUSTOM_TYPE_image_default.cmake``
+
+      Full file path: ``share/sysbuild/image_configurations/MY_CUSTOM_TYPE_image_default.cmake``
+
+      .. code-block:: cmake
+
+         # Here, the ZCMAKE_APPLICATION variable will be replaced with the image being configured
+         set_config_bool(${ZCMAKE_APPLICATION} CONFIG_BUILD_OUTPUT_HEX y)
+
+Reading image configuration
+===========================
+
+Kconfig
+-------
+
+Kconfig values from images can be read by sysbuild **after the CMake configuration of images has
+taken place**. This can be used to check configuration or to adjust additional sysbuild tasks
+depending upon configuration. The following function can be used for this purpose:
+
+.. code-block:: cmake
+
+   sysbuild_get(<variable> IMAGE <image> [VAR <image-variable>] KCONFIG)
+
+This function can only be used when
+:ref:`sysbuild is extended by a module <sysbuild_module_integration>` or inside of a ``sysbuild/CMakeLists.txt`` file after ``find_package(Sysbuild)`` has been used. An example of outputting
+values from all images is shown:
+
+.. tabs::
+
+   .. group-tab:: Module CMake
+
+      .. code-block:: cmake
+
+         function(${SYSBUILD_CURRENT_MODULE_NAME}_post_cmake)
+           cmake_parse_arguments(POST_CMAKE "" "" "IMAGES" ${ARGN})
+
+           foreach(image ${POST_CMAKE_IMAGES})
+             # Note that the variable to read in to must not be set before using the sysbuild_get() function
+             set(tmp_val)
+             sysbuild_get(tmp_val IMAGE ${image} VAR CONFIG_BUILD_OUTPUT_HEX KCONFIG)
+             message(STATUS "Image ${image} build hex: ${tmp_val}")
+           endforeach()
+         endfunction()
+
+   .. group-tab:: ``sysbuild/CMakeLists.txt``
+
+      .. code-block:: cmake
+
+         find_package(Sysbuild REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+         project(sysbuild LANGUAGES)
+
+         sysbuild_get(tmp_val IMAGE ${DEFAULT_IMAGE} VAR CONFIG_BUILD_OUTPUT_HEX KCONFIG)
+         message(STATUS "Image ${DEFAULT_IMAGE} build hex: ${tmp_val}")
diff --git a/doc/build/sysbuild/index.rst b/doc/build/sysbuild/index.rst
index 6618194baa6..51675569e08 100644
--- a/doc/build/sysbuild/index.rst
+++ b/doc/build/sysbuild/index.rst
@@ -442,8 +442,8 @@ Dedicated image build targets
 Not all build targets for images are given equivalent prefixed build targets
 when sysbuild is used, for example build targets like ``ram_report``,
 ``rom_report``, ``footprint``, ``puncover`` and ``pahole`` are not exposed.
-When using :ref:`Trusted Firmware <tfm_build_system>`, this includes build
-targets prefix with ``tfm_`` and ``bl2_``, for example: ``tfm_rom_report``
+When using :ref:`Trusted Firmware <tfm_build_system>`, the build targets prefixed
+with ``tfm_`` and ``bl2_`` are also not exposed, for example: ``tfm_rom_report``
 and ``bl2_ram_report``. To run these build targets, the build directory of the
 image can be provided to west/ninja/make along with the name of the build
 target to execute and it will run.
@@ -461,6 +461,13 @@ target to execute and it will run.
 
          west build -d build/mcuboot -t rom_report
 
+      For TF-M projects using TF-M targets, the application build directory is
+      used like so:
+
+      .. code-block:: shell
+
+         west build -d build/<app_name> -t tfm_rom_report
+
    .. group-tab:: ``ninja``
 
       Assuming that a project has been configured using ``cmake`` and built
@@ -471,6 +478,13 @@ target to execute and it will run.
 
          ninja -C mcuboot rom_report
 
+      For TF-M projects using TF-M targets, the application build directory is
+      used like so:
+
+      .. code-block:: shell
+
+         ninja -C <app_name> -t tfm_rom_report
+
    .. group-tab:: ``make``
 
       Assuming that a project has been configured using ``cmake`` and built
@@ -481,6 +495,13 @@ target to execute and it will run.
 
          make -C mcuboot rom_report
 
+      For TF-M projects using TF-M targets, the application build directory is
+      used like so:
+
+      .. code-block:: shell
+
+         make -C <app_name> -t tfm_rom_report
+
 .. _sysbuild_zephyr_application:
 
 Adding Zephyr applications to sysbuild
@@ -514,7 +535,7 @@ In sysbuild and Zephyr CMake build system a board may refer to:
 
 * A physical board with a single core SoC.
 * A specific core on a physical board with a multi-core SoC, such as
-  :ref:`nrf5340dk_nrf5340`.
+  :zephyr:board:`nrf5340dk`.
 * A specific SoC on a physical board with multiple SoCs, such as
   :ref:`nrf9160dk_nrf9160` and :ref:`nrf9160dk_nrf52840`.
 
@@ -799,6 +820,46 @@ debug the application.
 .. _MCUboot with Zephyr: https://docs.mcuboot.com/readme-zephyr
 .. _ExternalProject: https://cmake.org/cmake/help/latest/module/ExternalProject.html
 
+.. _sysbuild_var_override:
+
+Configuring sysbuild internal state
+***********************************
+
+Because sysbuild is a CMake project in it's own right, it runs and sets up itself similar to a
+Zephyr application but using it's own CMake code. This means that some features, for example
+specifying variables in an application ``CMakeLists.txt`` (such as ``BOARD_ROOT``) will not work,
+instead these must be set by using a :ref:`a module <modules_build_settings>` or by using a custom
+sysbuild project file as ``<application>/sysbuild/CMakeLists.txt``, for example:
+
+.. code-block:: cmake
+
+   # Place pre-sysbuild configuration items here
+
+   # For changing configuration that sysbuild itself uses:
+   # set(<var> <value>)
+   # list(APPEND <list> <value>)
+
+   # For changing configuration of other images:
+   # set(<image>_<var> <value> CACHE INTERNAL "<description>")
+
+   # Finds the sysbuild project and includes it with the new configuration
+   find_package(Sysbuild REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+   project(sysbuild LANGUAGES)
+
+An example of adding a ``BOARD_ROOT``:
+
+.. code-block:: cmake
+
+   list(APPEND BOARD_ROOT ${CMAKE_CURRENT_SOURCE_DIR}/../<extra-board-root>)
+
+   find_package(Sysbuild REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+   project(sysbuild LANGUAGES)
+
+This will pass the board root on to all images as part of a project, it does not need to be
+repeated in each image's ``CMakeLists.txt`` file.
+
 Extending sysbuild
 ******************
 
@@ -813,3 +874,9 @@ each image that is part of a project. Alternatively, there are
 which can be used to include CMake and Kconfig files for the overall sysbuild
 image itself, this is where e.g. a custom image for a particular board or SoC
 can be added.
+
+
+.. toctree::
+    :maxdepth: 1
+
+    images.rst
diff --git a/doc/build/version/index.rst b/doc/build/version/index.rst
index 1725e1a6646..bd5f205aed2 100644
--- a/doc/build/version/index.rst
+++ b/doc/build/version/index.rst
@@ -39,19 +39,19 @@ field to a single byte (note that there may be further restrictions depending up
 is used for, e.g. bootloaders might only support some of these fields or might place limits on the
 maximum values of fields):
 
-+---------------+----------------------------------------+
-| Field         | Data type                              |
-+---------------+----------------------------------------+
-| VERSION_MAJOR | Numerical (0-255)                      |
-+---------------+----------------------------------------+
-| VERSION_MINOR | Numerical (0-255)                      |
-+---------------+----------------------------------------+
-| PATCHLEVEL    | Numerical (0-255)                      |
-+---------------+----------------------------------------+
-| VERSION_TWEAK | Numerical (0-255)                      |
-+---------------+----------------------------------------+
-| EXTRAVERSION  | Alphanumerical (Lowercase a-z and 0-9) |
-+---------------+----------------------------------------+
++---------------+-------------------------------------------------------+
+| Field         | Data type                                             |
++---------------+-------------------------------------------------------+
+| VERSION_MAJOR | Numerical (0-255)                                     |
++---------------+-------------------------------------------------------+
+| VERSION_MINOR | Numerical (0-255)                                     |
++---------------+-------------------------------------------------------+
+| PATCHLEVEL    | Numerical (0-255)                                     |
++---------------+-------------------------------------------------------+
+| VERSION_TWEAK | Numerical (0-255)                                     |
++---------------+-------------------------------------------------------+
+| EXTRAVERSION  | Alphanumerical (Lowercase a-z and 0-9) and "." or "-" |
++---------------+-------------------------------------------------------+
 
 When an application is configured using CMake, the version file will be automatically processed,
 and will be checked automatically each time the version is changed, so CMake does not need to be
@@ -65,7 +65,7 @@ For the sections below, examples are provided for the following :file:`VERSION`
    VERSION_MINOR = 2
    PATCHLEVEL = 3
    VERSION_TWEAK = 4
-   EXTRAVERSION = unstable
+   EXTRAVERSION = unstable.5
 
 Use in code
 ===========
@@ -74,120 +74,120 @@ To use the version information in application code, the version file must be inc
 fields can be freely used. The include file name is :file:`app_version.h` (no path is needed), the
 following defines are available:
 
-+-----------------------------+-------------------+------------------------------------------------------+-------------------------+
-| Define                      | Type              | Field(s)                                             | Example                 |
-+-----------------------------+-------------------+------------------------------------------------------+-------------------------+
-| APPVERSION                  | Numerical         | ``VERSION_MAJOR`` (left shifted by 24 bits), |br|    | 0x1020304               |
-|                             |                   | ``VERSION_MINOR`` (left shifted by 16 bits), |br|    |                         |
-|                             |                   | ``PATCHLEVEL`` (left shifted by 8 bits), |br|        |                         |
-|                             |                   | ``VERSION_TWEAK``                                    |                         |
-+-----------------------------+-------------------+------------------------------------------------------+-------------------------+
-| APP_VERSION_NUMBER          | Numerical         | ``VERSION_MAJOR`` (left shifted by 16 bits), |br|    | 0x10203                 |
-|                             |                   | ``VERSION_MINOR`` (left shifted by 8 bits), |br|     |                         |
-|                             |                   | ``PATCHLEVEL``                                       |                         |
-+-----------------------------+-------------------+------------------------------------------------------+-------------------------+
-| APP_VERSION_MAJOR           | Numerical         | ``VERSION_MAJOR``                                    | 1                       |
-+-----------------------------+-------------------+------------------------------------------------------+-------------------------+
-| APP_VERSION_MINOR           | Numerical         | ``VERSION_MINOR``                                    | 2                       |
-+-----------------------------+-------------------+------------------------------------------------------+-------------------------+
-| APP_PATCHLEVEL              | Numerical         | ``PATCHLEVEL``                                       | 3                       |
-+-----------------------------+-------------------+------------------------------------------------------+-------------------------+
-| APP_TWEAK                   | Numerical         | ``VERSION_TWEAK``                                    | 4                       |
-+-----------------------------+-------------------+------------------------------------------------------+-------------------------+
-| APP_VERSION_STRING          | String (quoted)   | ``VERSION_MAJOR``, |br|                              | "1.2.3-unstable"        |
-|                             |                   | ``VERSION_MINOR``, |br|                              |                         |
-|                             |                   | ``PATCHLEVEL``, |br|                                 |                         |
-|                             |                   | ``EXTRAVERSION`` |br|                                |                         |
-+-----------------------------+-------------------+------------------------------------------------------+-------------------------+
-| APP_VERSION_EXTENDED_STRING | String (quoted)   | ``VERSION_MAJOR``, |br|                              | "1.2.3-unstable+4"      |
-|                             |                   | ``VERSION_MINOR``, |br|                              |                         |
-|                             |                   | ``PATCHLEVEL``, |br|                                 |                         |
-|                             |                   | ``EXTRAVERSION`` |br|                                |                         |
-|                             |                   | ``VERSION_TWEAK`` |br|                               |                         |
-+-----------------------------+-------------------+------------------------------------------------------+-------------------------+
-| APP_VERSION_TWEAK_STRING    | String (quoted)   | ``VERSION_MAJOR``, |br|                              | "1.2.3+4"               |
-|                             |                   | ``VERSION_MINOR``, |br|                              |                         |
-|                             |                   | ``PATCHLEVEL``, |br|                                 |                         |
-|                             |                   | ``VERSION_TWEAK`` |br|                               |                         |
-+-----------------------------+-------------------+------------------------------------------------------+-------------------------+
-| APP_BUILD_VERSION           | String (unquoted) | None (value of ``git describe --abbrev=12 --always`` | v3.3.0-18-g2c85d9224fca |
-|                             |                   | from application repository)                         |                         |
-+-----------------------------+-------------------+------------------------------------------------------+-------------------------+
++-----------------------------+-------------------+------------------------------------------------------+---------------------------+
+| Define                      | Type              | Field(s)                                             | Example                   |
++-----------------------------+-------------------+------------------------------------------------------+---------------------------+
+| APPVERSION                  | Numerical         | ``VERSION_MAJOR`` (left shifted by 24 bits), |br|    | 0x1020304                 |
+|                             |                   | ``VERSION_MINOR`` (left shifted by 16 bits), |br|    |                           |
+|                             |                   | ``PATCHLEVEL`` (left shifted by 8 bits), |br|        |                           |
+|                             |                   | ``VERSION_TWEAK``                                    |                           |
++-----------------------------+-------------------+------------------------------------------------------+---------------------------+
+| APP_VERSION_NUMBER          | Numerical         | ``VERSION_MAJOR`` (left shifted by 16 bits), |br|    | 0x10203                   |
+|                             |                   | ``VERSION_MINOR`` (left shifted by 8 bits), |br|     |                           |
+|                             |                   | ``PATCHLEVEL``                                       |                           |
++-----------------------------+-------------------+------------------------------------------------------+---------------------------+
+| APP_VERSION_MAJOR           | Numerical         | ``VERSION_MAJOR``                                    | 1                         |
++-----------------------------+-------------------+------------------------------------------------------+---------------------------+
+| APP_VERSION_MINOR           | Numerical         | ``VERSION_MINOR``                                    | 2                         |
++-----------------------------+-------------------+------------------------------------------------------+---------------------------+
+| APP_PATCHLEVEL              | Numerical         | ``PATCHLEVEL``                                       | 3                         |
++-----------------------------+-------------------+------------------------------------------------------+---------------------------+
+| APP_TWEAK                   | Numerical         | ``VERSION_TWEAK``                                    | 4                         |
++-----------------------------+-------------------+------------------------------------------------------+---------------------------+
+| APP_VERSION_STRING          | String (quoted)   | ``VERSION_MAJOR``, |br|                              | "1.2.3-unstable.5"        |
+|                             |                   | ``VERSION_MINOR``, |br|                              |                           |
+|                             |                   | ``PATCHLEVEL``, |br|                                 |                           |
+|                             |                   | ``EXTRAVERSION`` |br|                                |                           |
++-----------------------------+-------------------+------------------------------------------------------+---------------------------+
+| APP_VERSION_EXTENDED_STRING | String (quoted)   | ``VERSION_MAJOR``, |br|                              | "1.2.3-unstable.5+4"      |
+|                             |                   | ``VERSION_MINOR``, |br|                              |                           |
+|                             |                   | ``PATCHLEVEL``, |br|                                 |                           |
+|                             |                   | ``EXTRAVERSION`` |br|                                |                           |
+|                             |                   | ``VERSION_TWEAK`` |br|                               |                           |
++-----------------------------+-------------------+------------------------------------------------------+---------------------------+
+| APP_VERSION_TWEAK_STRING    | String (quoted)   | ``VERSION_MAJOR``, |br|                              | "1.2.3+4"                 |
+|                             |                   | ``VERSION_MINOR``, |br|                              |                           |
+|                             |                   | ``PATCHLEVEL``, |br|                                 |                           |
+|                             |                   | ``VERSION_TWEAK`` |br|                               |                           |
++-----------------------------+-------------------+------------------------------------------------------+---------------------------+
+| APP_BUILD_VERSION           | String (unquoted) | None (value of ``git describe --abbrev=12 --always`` | v3.3.0-18-g2c85d9224fca   |
+|                             |                   | from application repository)                         |                           |
++-----------------------------+-------------------+------------------------------------------------------+---------------------------+
 
 Use in Kconfig
 ==============
 
 The following variables are available for usage in Kconfig files:
 
-+--------------------------------+-----------+--------------------------+------------------+
-| Variable                       | Type      | Field(s)                 | Example          |
-+--------------------------------+-----------+--------------------------+------------------+
-| $(VERSION_MAJOR)               | Numerical | ``VERSION_MAJOR``        | 1                |
-+--------------------------------+-----------+--------------------------+------------------+
-| $(VERSION_MINOR)               | Numerical | ``VERSION_MINOR``        | 2                |
-+--------------------------------+-----------+--------------------------+------------------+
-| $(PATCHLEVEL)                  | Numerical | ``PATCHLEVEL``           | 3                |
-+--------------------------------+-----------+--------------------------+------------------+
-| $(VERSION_TWEAK)               | Numerical | ``VERSION_TWEAK``        | 4                |
-+--------------------------------+-----------+--------------------------+------------------+
-| $(APPVERSION)                  | String    | ``VERSION_MAJOR``, |br|  | 1.2.3-unstable   |
-|                                |           | ``VERSION_MINOR``, |br|  |                  |
-|                                |           | ``PATCHLEVEL``, |br|     |                  |
-|                                |           | ``EXTRAVERSION``         |                  |
-+--------------------------------+-----------+--------------------------+------------------+
-| $(APP_VERSION_EXTENDED_STRING) | String    | ``VERSION_MAJOR``, |br|  | 1.2.3-unstable+4 |
-|                                |           | ``VERSION_MINOR``, |br|  |                  |
-|                                |           | ``PATCHLEVEL``, |br|     |                  |
-|                                |           | ``EXTRAVERSION``, |br|   |                  |
-|                                |           | ``VERSION_TWEAK``        |                  |
-+--------------------------------+-----------+--------------------------+------------------+
-| $(APP_VERSION_TWEAK_STRING)    | String    | ``VERSION_MAJOR``, |br|  | 1.2.3+4          |
-|                                |           | ``VERSION_MINOR``, |br|  |                  |
-|                                |           | ``PATCHLEVEL``, |br|     |                  |
-|                                |           | ``VERSION_TWEAK``        |                  |
-+--------------------------------+-----------+--------------------------+------------------+
++--------------------------------+-----------+--------------------------+--------------------+
+| Variable                       | Type      | Field(s)                 | Example            |
++--------------------------------+-----------+--------------------------+--------------------+
+| $(VERSION_MAJOR)               | Numerical | ``VERSION_MAJOR``        | 1                  |
++--------------------------------+-----------+--------------------------+--------------------+
+| $(VERSION_MINOR)               | Numerical | ``VERSION_MINOR``        | 2                  |
++--------------------------------+-----------+--------------------------+--------------------+
+| $(PATCHLEVEL)                  | Numerical | ``PATCHLEVEL``           | 3                  |
++--------------------------------+-----------+--------------------------+--------------------+
+| $(VERSION_TWEAK)               | Numerical | ``VERSION_TWEAK``        | 4                  |
++--------------------------------+-----------+--------------------------+--------------------+
+| $(APPVERSION)                  | String    | ``VERSION_MAJOR``, |br|  | 1.2.3-unstable.5   |
+|                                |           | ``VERSION_MINOR``, |br|  |                    |
+|                                |           | ``PATCHLEVEL``, |br|     |                    |
+|                                |           | ``EXTRAVERSION``         |                    |
++--------------------------------+-----------+--------------------------+--------------------+
+| $(APP_VERSION_EXTENDED_STRING) | String    | ``VERSION_MAJOR``, |br|  | 1.2.3-unstable.5+4 |
+|                                |           | ``VERSION_MINOR``, |br|  |                    |
+|                                |           | ``PATCHLEVEL``, |br|     |                    |
+|                                |           | ``EXTRAVERSION``, |br|   |                    |
+|                                |           | ``VERSION_TWEAK``        |                    |
++--------------------------------+-----------+--------------------------+--------------------+
+| $(APP_VERSION_TWEAK_STRING)    | String    | ``VERSION_MAJOR``, |br|  | 1.2.3+4            |
+|                                |           | ``VERSION_MINOR``, |br|  |                    |
+|                                |           | ``PATCHLEVEL``, |br|     |                    |
+|                                |           | ``VERSION_TWEAK``        |                    |
++--------------------------------+-----------+--------------------------+--------------------+
 
 Use in CMake
 ============
 
 The following variable are available for usage in CMake files:
 
-+-----------------------------+-----------------+---------------------------------------------------+------------------+
-| Variable                    | Type            | Field(s)                                          | Example          |
-+-----------------------------+-----------------+---------------------------------------------------+------------------+
-| APPVERSION                  | Numerical (hex) | ``VERSION_MAJOR`` (left shifted by 24 bits), |br| | 0x1020304        |
-|                             |                 | ``VERSION_MINOR`` (left shifted by 16 bits), |br| |                  |
-|                             |                 | ``PATCHLEVEL`` (left shifted by 8 bits), |br|     |                  |
-|                             |                 | ``VERSION_TWEAK``                                 |                  |
-+-----------------------------+-----------------+---------------------------------------------------+------------------+
-| APP_VERSION_NUMBER          | Numerical (hex) | ``VERSION_MAJOR`` (left shifted by 16 bits), |br| | 0x10203          |
-|                             |                 | ``VERSION_MINOR`` (left shifted by 8 bits), |br|  |                  |
-|                             |                 | ``PATCHLEVEL``                                    |                  |
-+-----------------------------+-----------------+---------------------------------------------------+------------------+
-| APP_VERSION_MAJOR           | Numerical       | ``VERSION_MAJOR``                                 | 1                |
-+-----------------------------+-----------------+---------------------------------------------------+------------------+
-| APP_VERSION_MINOR           | Numerical       | ``VERSION_MINOR``                                 | 2                |
-+-----------------------------+-----------------+---------------------------------------------------+------------------+
-| APP_PATCHLEVEL              | Numerical       | ``PATCHLEVEL``                                    | 3                |
-+-----------------------------+-----------------+---------------------------------------------------+------------------+
-| APP_VERSION_TWEAK           | Numerical       | ``VERSION_TWEAK``                                 | 4                |
-+-----------------------------+-----------------+---------------------------------------------------+------------------+
-| APP_VERSION_STRING          | String          | ``VERSION_MAJOR``, |br|                           | 1.2.3-unstable   |
-|                             |                 | ``VERSION_MINOR``, |br|                           |                  |
-|                             |                 | ``PATCHLEVEL``, |br|                              |                  |
-|                             |                 | ``EXTRAVERSION``                                  |                  |
-+-----------------------------+-----------------+---------------------------------------------------+------------------+
-| APP_VERSION_EXTENDED_STRING | String          | ``VERSION_MAJOR``, |br|                           | 1.2.3-unstable+4 |
-|                             |                 | ``VERSION_MINOR``, |br|                           |                  |
-|                             |                 | ``PATCHLEVEL``, |br|                              |                  |
-|                             |                 | ``EXTRAVERSION``, |br|                            |                  |
-|                             |                 | ``VERSION_TWEAK``                                 |                  |
-+-----------------------------+-----------------+---------------------------------------------------+------------------+
-| APP_VERSION_TWEAK_STRING    | String          | ``VERSION_MAJOR``, |br|                           | 1.2.3+4          |
-|                             |                 | ``VERSION_MINOR``, |br|                           |                  |
-|                             |                 | ``PATCHLEVEL``, |br|                              |                  |
-|                             |                 | ``VERSION_TWEAK``                                 |                  |
-+-----------------------------+-----------------+---------------------------------------------------+------------------+
++-----------------------------+-----------------+---------------------------------------------------+--------------------+
+| Variable                    | Type            | Field(s)                                          | Example            |
++-----------------------------+-----------------+---------------------------------------------------+--------------------+
+| APPVERSION                  | Numerical (hex) | ``VERSION_MAJOR`` (left shifted by 24 bits), |br| | 0x1020304          |
+|                             |                 | ``VERSION_MINOR`` (left shifted by 16 bits), |br| |                    |
+|                             |                 | ``PATCHLEVEL`` (left shifted by 8 bits), |br|     |                    |
+|                             |                 | ``VERSION_TWEAK``                                 |                    |
++-----------------------------+-----------------+---------------------------------------------------+--------------------+
+| APP_VERSION_NUMBER          | Numerical (hex) | ``VERSION_MAJOR`` (left shifted by 16 bits), |br| | 0x10203            |
+|                             |                 | ``VERSION_MINOR`` (left shifted by 8 bits), |br|  |                    |
+|                             |                 | ``PATCHLEVEL``                                    |                    |
++-----------------------------+-----------------+---------------------------------------------------+--------------------+
+| APP_VERSION_MAJOR           | Numerical       | ``VERSION_MAJOR``                                 | 1                  |
++-----------------------------+-----------------+---------------------------------------------------+--------------------+
+| APP_VERSION_MINOR           | Numerical       | ``VERSION_MINOR``                                 | 2                  |
++-----------------------------+-----------------+---------------------------------------------------+--------------------+
+| APP_PATCHLEVEL              | Numerical       | ``PATCHLEVEL``                                    | 3                  |
++-----------------------------+-----------------+---------------------------------------------------+--------------------+
+| APP_VERSION_TWEAK           | Numerical       | ``VERSION_TWEAK``                                 | 4                  |
++-----------------------------+-----------------+---------------------------------------------------+--------------------+
+| APP_VERSION_STRING          | String          | ``VERSION_MAJOR``, |br|                           | 1.2.3-unstable.5   |
+|                             |                 | ``VERSION_MINOR``, |br|                           |                    |
+|                             |                 | ``PATCHLEVEL``, |br|                              |                    |
+|                             |                 | ``EXTRAVERSION``                                  |                    |
++-----------------------------+-----------------+---------------------------------------------------+--------------------+
+| APP_VERSION_EXTENDED_STRING | String          | ``VERSION_MAJOR``, |br|                           | 1.2.3-unstable.5+4 |
+|                             |                 | ``VERSION_MINOR``, |br|                           |                    |
+|                             |                 | ``PATCHLEVEL``, |br|                              |                    |
+|                             |                 | ``EXTRAVERSION``, |br|                            |                    |
+|                             |                 | ``VERSION_TWEAK``                                 |                    |
++-----------------------------+-----------------+---------------------------------------------------+--------------------+
+| APP_VERSION_TWEAK_STRING    | String          | ``VERSION_MAJOR``, |br|                           | 1.2.3+4            |
+|                             |                 | ``VERSION_MINOR``, |br|                           |                    |
+|                             |                 | ``PATCHLEVEL``, |br|                              |                    |
+|                             |                 | ``VERSION_TWEAK``                                 |                    |
++-----------------------------+-----------------+---------------------------------------------------+--------------------+
 
 Use in MCUboot-supported applications
 =====================================
diff --git a/doc/conf.py b/doc/conf.py
index c8f43e7d703..fdafbdafd9a 100644
--- a/doc/conf.py
+++ b/doc/conf.py
@@ -35,7 +35,7 @@
 # -- Project --------------------------------------------------------------
 
 project = "Zephyr Project"
-copyright = "2015-2024 Zephyr Project members and individual contributors"
+copyright = "2015-2025 Zephyr Project members and individual contributors"
 author = "The Zephyr Project Contributors"
 
 # parse version from 'VERSION' file
@@ -196,9 +196,9 @@
     "current_version": version,
     "versions": (
         ("latest", "/"),
+        ("4.1.0", "/4.1.0/"),
         ("4.0.0", "/4.0.0/"),
         ("3.7.0 (LTS)", "/3.7.0/"),
-        ("2.7.6 (LTS)", "/2.7.6/"),
     ),
     "display_gh_links": True,
     "reference_links": {
@@ -299,6 +299,8 @@
 
 kconfig_generate_db = True
 kconfig_ext_paths = [ZEPHYR_BASE]
+kconfig_gh_link_base_url = "https://github.com/zephyrproject-rtos/zephyr"
+kconfig_zephyr_version = f"v{version}" if is_release else "main"
 
 # -- Options for zephyr.external_content ----------------------------------
 
@@ -324,6 +326,7 @@
 # -- Options for zephyr.domain --------------------------------------------
 
 zephyr_breathe_insert_related_samples = True
+zephyr_generate_hw_features = not tags.has("hw_features_turbo")  # pylint: disable=undefined-variable  # noqa: F821
 
 # -- Options for sphinx.ext.graphviz --------------------------------------
 
@@ -336,6 +339,9 @@
     "-Ncolor=gray60",
     "-Nfontcolor=gray25",
     "-Ecolor=gray60",
+    "-Gfontname=system-ui,-apple-system,Segoe UI,Roboto,Helvetica Neue,Arial,Noto Sans,sans-serif",
+    "-Nfontname=system-ui,-apple-system,Segoe UI,Roboto,Helvetica Neue,Arial,Noto Sans,sans-serif",
+    "-Efontname=SFMono-Regular,Menlo,Monaco,Consolas,Liberation Mono,Courier New,Courier,monospace",
 ]
 
 # -- Options for sphinx_copybutton ----------------------------------------
diff --git a/doc/connectivity/bluetooth/api/audio/bluetooth-le-audio-arch.rst b/doc/connectivity/bluetooth/api/audio/bluetooth-le-audio-arch.rst
index 7eac2171a32..f5da0681880 100644
--- a/doc/connectivity/bluetooth/api/audio/bluetooth-le-audio-arch.rst
+++ b/doc/connectivity/bluetooth/api/audio/bluetooth-le-audio-arch.rst
@@ -698,19 +698,19 @@ Bluetooth Audio Stack.
    +--------+-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
    | Module | Role                          | Version | Added in Release | Status                | Remaining                                        |
    +========+===============================+=========+==================+=======================+==================================================+
-   | VCP    | Volume Renderer               | 1.0     | 2.6              | - Feature complete    | - Sample Application                             |
+   | VCP    | Volume Renderer               | 1.0.0   | 2.6              | - Feature complete    | - Sample Application                             |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        +-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   |        | Volume Controller             | 1.0     | 2.6              | - Feature complete    | - Sample Application                             |
+   |        | Volume Controller             | 1.0.0   | 2.6              | - Feature complete    | - Sample Application                             |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    +--------+-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   | MICP   | Microphone Device             | 1.0     | 2.7              | - Feature complete    | - Sample Application                             |
+   | MICP   | Microphone Device             | 1.0.0   | 2.7              | - Feature complete    | - Sample Application                             |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        +-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   |        | Microphone Controller         | 1.0     | 2.7              | - Feature complete    | - Sample Application                             |
+   |        | Microphone Controller         | 1.0.0   | 2.7              | - Feature complete    | - Sample Application                             |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    +--------+-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
@@ -722,19 +722,19 @@ Bluetooth Audio Stack.
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    +--------+-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   | CCP    | Call Control Server           | 1.0     | 3.0              | - Feature complete    | - API refactor (in progress)                     |
+   | CCP    | Call Control Server           | 1.0.0   | 3.0              | - Feature complete    | - API refactor (in progress)                     |
    |        |                               |         |                  | - Shell Module        | - Sample Application (in progress)               |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        +-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   |        | Call Control Client           | 1.0     | 3.0              | - Feature complete    | - API refactor                                   |
-   |        |                               |         |                  | - Shell Module        | - Sample Application                             |
+   |        | Call Control Client           | 1.0.0   | 3.0              | - Feature complete    | - API refactor (in progress)                     |
+   |        |                               |         |                  | - Shell Module        | - Sample Application (in progress)               |
    |        |                               |         |                  | - BSIM test           |                                                  |
    +--------+-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   | MCP    | Media Control Server          | 1.0     | 3.0              | - Feature complete    | - API refactor                                   |
+   | MCP    | Media Control Server          | 1.0.0   | 3.0              | - Feature complete    | - API refactor                                   |
    |        |                               |         |                  | - Shell Module        | - Support for multiple instances and connections |
    |        |                               |         |                  | - BSIM test           | - Sample Application                             |
    |        +-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   |        | Media Control Client          | 1.0     | 3.0              | - Feature complete    | - API refactor                                   |
+   |        | Media Control Client          | 1.0.0   | 3.0              | - Feature complete    | - API refactor                                   |
    |        |                               |         |                  | - Shell Module        | - Sample Application                             |
    |        |                               |         |                  | - BSIM test           |                                                  |
    +--------+-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
@@ -768,12 +768,12 @@ Bluetooth Audio Stack.
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        |                               |         |                  | - Sample Application  |                                                  |
    +--------+-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   | CAP    | Acceptor                      | 1.0     | 3.2              | - Feature complete    |                                                  |
+   | CAP    | Acceptor                      | 1.0.1   | 3.2              | - Feature complete    |                                                  |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        |                               |         |                  | - Sample Application  |                                                  |
    |        +-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   |        | Initiator                     | 1.0     | 3.3              | - Feature complete    |                                                  |
+   |        | Initiator                     | 1.0.1   | 3.3              | - Feature complete    |                                                  |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        |                               |         |                  | - Sample Application  |                                                  |
@@ -783,12 +783,12 @@ Bluetooth Audio Stack.
    |        |                               |         |                  |                       | - BSIM test                                      |
    |        |                               |         |                  |                       | - Sample Application                             |
    +--------+-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   | HAP    | Hearing Aid                   | 1.0     | 3.1              | - Feature complete    |                                                  |
+   | HAP    | Hearing Aid                   | 1.0.0   | 3.1              | - Feature complete    |                                                  |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        |                               |         |                  | - Sample Application  |                                                  |
    |        +-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   |        | Hearing Aid Unicast Client    | 1.0     | 3.1              | - Feature complete    |                                                  |
+   |        | Hearing Aid Unicast Client    | 1.0.0   | 3.1              | - Feature complete    |                                                  |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        |                               |         |                  | - Sample Application  |                                                  |
@@ -798,42 +798,42 @@ Bluetooth Audio Stack.
    |        |                               |         |                  |                       | - BSIM test                                      |
    |        |                               |         |                  |                       | - Sample Application                             |
    +--------+-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   | TMAP   | Call Gateway                  | 1.0     | 3.4              | - Feature complete    |                                                  |
+   | TMAP   | Call Gateway                  | 1.0.0   | 3.4              | - Feature complete    |                                                  |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        |                               |         |                  | - Sample Application  |                                                  |
    |        +-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   |        | Call Terminal                 | 1.0     | 3.4              | - Feature complete    |                                                  |
+   |        | Call Terminal                 | 1.0.0   | 3.4              | - Feature complete    |                                                  |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        |                               |         |                  | - Sample Application  |                                                  |
    |        +-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   |        | Unicast Media Sender          | 1.0     | 3.4              | - Feature complete    |                                                  |
+   |        | Unicast Media Sender          | 1.0.0   | 3.4              | - Feature complete    |                                                  |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        |                               |         |                  | - Sample Application  |                                                  |
    |        +-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   |        | Unicast Media Receiver        | 1.0     | 3.4              | - Feature complete    |                                                  |
+   |        | Unicast Media Receiver        | 1.0.0   | 3.4              | - Feature complete    |                                                  |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        |                               |         |                  | - Sample Application  |                                                  |
    |        +-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   |        | Broadcast Media Sender        | 1.0     | 3.4              | - Feature complete    |                                                  |
+   |        | Broadcast Media Sender        | 1.0.0   | 3.4              | - Feature complete    |                                                  |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        |                               |         |                  | - Sample Application  |                                                  |
    |        +-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   |        | Broadcast Media Receiver      | 1.0     | 3.4              | - Feature complete    |                                                  |
+   |        | Broadcast Media Receiver      | 1.0.0   | 3.4              | - Feature complete    |                                                  |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        |                               |         |                  | - Sample Application  |                                                  |
    +--------+-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   | PBP    | Public Broadcast Source       |         | 3.5              | - Feature complete    |                                                  |
+   | PBP    | Public Broadcast Source       | 1.0.0   | 3.5              | - Feature complete    |                                                  |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        |                               |         |                  | - Sample Application  |                                                  |
    |        +-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   |        | Public Broadcast Sink         |         | 3.5              | - Feature complete    |                                                  |
+   |        | Public Broadcast Sink         | 1.0.0   | 3.5              | - Feature complete    |                                                  |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        |                               |         |                  | - Sample Application  |                                                  |
@@ -843,22 +843,22 @@ Bluetooth Audio Stack.
    |        |                               |         |                  |                       | - BSIM test                                      |
    |        |                               |         |                  |                       | - Sample Application                             |
    +--------+-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   | GMAP   | Unicast Game Gateway          |         | 3.5              | - Feature complete    | - Sample Application                             |
+   | GMAP   | Unicast Game Gateway          | 1.0.0   | 3.5              | - Feature complete    | - Sample Application                             |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        |                               |         |                  |                       |                                                  |
    |        +-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   |        | Unicast Game Terminal         |         | 3.5              | - Feature complete    | - Sample Application                             |
+   |        | Unicast Game Terminal         | 1.0.0   | 3.5              | - Feature complete    | - Sample Application                             |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        |                               |         |                  |                       |                                                  |
    |        +-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   |        | Broadcast Game Sender         |         | 3.5              | - Feature complete    | - Sample Application                             |
+   |        | Broadcast Game Sender         | 1.0.0   | 3.5              | - Feature complete    | - Sample Application                             |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        |                               |         |                  |                       |                                                  |
    |        +-------------------------------+---------+------------------+-----------------------+--------------------------------------------------+
-   |        | Broadcast Game Receiver       |         | 3.5              | - Feature complete    | - Sample Application                             |
+   |        | Broadcast Game Receiver       | 1.0.0   | 3.5              | - Feature complete    | - Sample Application                             |
    |        |                               |         |                  | - Shell Module        |                                                  |
    |        |                               |         |                  | - BSIM test           |                                                  |
    |        |                               |         |                  |                       |                                                  |
@@ -1238,10 +1238,10 @@ The LE audio channel on Discord
 
 Zephyr has a specific Discord channel for LE Audio development, which is open to all.
 Find it here at https://discordapp.com/channels/720317445772017664/1207326649591271434 or simply
-search for "ble-audio" from within Discord.
-Since the ``#ble-audio`` channel is open for all,
+search for "bt-audio" from within Discord.
+Since the ``#bt-audio`` channel is open for all,
 we cannot discuss any specifications that are in development in that channel.
-For discussions that require a Bluetooth SIG membership we refer to the ``#bluetooth-sig``
+For discussions that require a Bluetooth SIG membership we refer to the ``#bt-sig``
 Discord channel found at https://discordapp.com/channels/720317445772017664/869172014018097162.
 
 Zephyr weekly meetings
diff --git a/doc/connectivity/bluetooth/api/hci.txt b/doc/connectivity/bluetooth/api/hci.txt
index ee75f0799f9..2ad17bfae5e 100644
--- a/doc/connectivity/bluetooth/api/hci.txt
+++ b/doc/connectivity/bluetooth/api/hci.txt
@@ -805,7 +805,7 @@ event shall be generated.
 Zephyr Write Tx Power Level (per Role/Connection) Command
 =========================================================
 
-This command dynamically modifies BLE Tx power level given a handle and a
+This command dynamically modifies Bluetooth Tx power level given a handle and a
 handle type (advertiser, scanner, connection).
 
 +--------------------------+-------+--------------------+--------------------+
@@ -818,8 +818,8 @@ handle type (advertiser, scanner, connection).
 |                          |       |                    | Selected_Tx_Power  |
 +--------------------------+-------+--------------------+--------------------+
 
-The Tx power of the BLE radio interface is modified for any low-level link by
-the controller with a high degree of flexibility. The BLE link whose power is
+The Tx power of the Bluetooth radio interface is modified for any low-level link by
+the controller with a high degree of flexibility. The Bluetooth link whose power is
 set is identified based on a handle type (advertiser, scanner, connection) and
 handle pair.
 
@@ -927,10 +927,10 @@ event shall be generated.
 Zephyr Read Tx Power Level (per Role/Connection) Command
 ========================================================
 
-This command reads the BLE Tx power level. In contrast to the standardized HCI
+This command reads the Bluetooth Tx power level. In contrast to the standardized HCI
 command, i.e. Read_Transmit_Power_Level, which returns the transmitted power
 level only for a specified connection handle, this command operates for both
-connected and unconnected states. It gets the BLE Tx power level for any given
+connected and unconnected states. It gets the Bluetooth Tx power level for any given
 handle type (advertiser, scanner, connection) and handle.
 
 +--------------------------+-------+--------------------+--------------------+
@@ -943,7 +943,7 @@ handle type (advertiser, scanner, connection) and handle.
 |                          |       |                    | Tx_Power_Level     |
 +--------------------------+-------+--------------------+--------------------+
 
-The Tx power of the BLE radio interface used for a low-level link identified
+The Tx power of the Bluetooth radio interface used for a low-level link identified
 by a pair of Handle_Type and Handle is retrieved from the controller.
 
 The role/state defining input parameter is the Handle_Type, whereas its
diff --git a/doc/connectivity/bluetooth/bluetooth-arch.rst b/doc/connectivity/bluetooth/bluetooth-arch.rst
index eeb2f5bbd6d..1ae6ce9ff4d 100644
--- a/doc/connectivity/bluetooth/bluetooth-arch.rst
+++ b/doc/connectivity/bluetooth/bluetooth-arch.rst
@@ -10,15 +10,14 @@ This page describes the software architecture of Zephyr's Bluetooth protocol
 stack.
 
 .. note::
-   Zephyr supports mainly Bluetooth Low Energy (BLE), the low-power
+   Zephyr supports mainly Bluetooth Low Energy (LE), the low-power
    version of the Bluetooth specification. Zephyr also has limited support
-   for portions of the BR/EDR Host. Throughout this architecture document we
-   use BLE interchangeably for Bluetooth except when noted.
+   for portions of the BR/EDR Host.
 
 .. _bluetooth-layers:
 
-BLE Layers
-==========
+Bluetooth LE Layers
+===================
 
 There are 3 main layers that together constitute a full Bluetooth Low Energy
 protocol stack:
@@ -62,7 +61,7 @@ following configurations are commonly used:
 
 * **Single-chip configuration**: In this configuration, a single microcontroller
   implements all three layers and the application itself. This can also be called a
-  system-on-chip (SoC) implementation. In this case the BLE Host and the BLE
+  system-on-chip (SoC) implementation. In this case the Bluetooth Host and the Bluetooth
   Controller communicate directly through function calls and queues in RAM. The
   Bluetooth specification does not specify how HCI is implemented in this
   single-chip configuration and so how HCI commands, events, and data flows between
@@ -75,11 +74,11 @@ following configurations are commonly used:
   configuration. This configuration allows for a wider variety of combinations of
   Hosts when using the Zephyr OS as a Controller. Since HCI ensures
   interoperability among Host and Controller implementations, including of course
-  Zephyr's very own BLE Host and Controller, users of the Zephyr Controller can
+  Zephyr's very own Bluetooth Host and Controller, users of the Zephyr Controller can
   choose to use whatever Host running on any platform they prefer. For example,
-  the host can be the Linux BLE Host stack (BlueZ) running on any processor
+  the host can be the Linux Bluetooth Host stack (BlueZ) running on any processor
   capable of supporting Linux. The Host processor may of course also run Zephyr
-  and the Zephyr OS BLE Host. Conversely, combining an IC running the Zephyr
+  and the Zephyr OS Bluetooth Host. Conversely, combining an IC running the Zephyr
   Host with an external Controller that does not run Zephyr is also supported.
 
 .. _bluetooth-build-types:
@@ -88,12 +87,12 @@ Build Types
 ===========
 
 The Zephyr software stack as an RTOS is highly configurable, and in particular,
-the BLE subsystem can be configured in multiple ways during the build process to
+the Bluetooth subsystem can be configured in multiple ways during the build process to
 include only the features and layers that are required to reduce RAM and ROM
 footprint as well as power consumption. Here's a short list of the different
-BLE-enabled builds that can be produced from the Zephyr project codebase:
+Bluetooth-enabled builds that can be produced from the Zephyr project codebase:
 
-* **Controller-only build**: When built as a BLE Controller, Zephyr includes
+* **Controller-only build**: When built as a Bluetooth Controller, Zephyr includes
   the Link Layer and a special application. This application is different
   depending on the physical transport chosen for HCI:
 
@@ -114,7 +113,7 @@ BLE-enabled builds that can be produced from the Zephyr project codebase:
   corresponding device tree node is enabled.
 
 * **Host-only build**: A Zephyr OS Host build will contain the Application and
-  the BLE Host, along with an HCI driver (UART or SPI) to interface with an
+  the Bluetooth Host, along with an HCI driver (UART or SPI) to interface with an
   external Controller chip.
   A build of this type sets the following Kconfig option values:
 
@@ -143,12 +142,12 @@ BLE-enabled builds that can be produced from the Zephyr project codebase:
   used for Controller-only builds can be built as Combined
 
 The picture below shows the SoC or single-chip configuration when using a Zephyr
-combined build (a build that includes both a BLE Host and a Controller in the
+combined build (a build that includes both a Bluetooth Host and a Controller in the
 same firmware image that is programmed onto the chip):
 
 .. figure:: img/ble_cfg_single.png
    :align: center
-   :alt: BLE Combined build on a single chip
+   :alt: Bluetooth Combined build on a single chip
 
    A Combined build on a Single-Chip configuration
 
@@ -157,25 +156,25 @@ combinations are possible, some of which are depicted below:
 
 .. figure:: img/ble_cfg_dual.png
    :align: center
-   :alt: BLE dual-chip configuration builds
+   :alt: Bluetooth dual-chip configuration builds
 
    Host-only and Controller-only builds on dual-chip configurations
 
 When using a Zephyr Host (left side of image), two instances of Zephyr OS
 must be built with different configurations, yielding two separate images that
 must be programmed into each of the chips respectively. The Host build image
-contains the application, the BLE Host and the selected HCI driver (UART or
+contains the application, the Bluetooth Host and the selected HCI driver (UART or
 SPI), while the Controller build runs either the
 :zephyr:code-sample:`bluetooth_hci_uart`, or the
 :zephyr:code-sample:`bluetooth_hci_spi` app to provide an interface to
-the BLE Controller.
+the Bluetooth Controller.
 
 This configuration is not limited to using a Zephyr OS Host, as the right side
 of the image shows. One can indeed take one of the many existing GNU/Linux
-distributions, most of which include Linux's own BLE Host (BlueZ), to connect it
+distributions, most of which include Linux's own Bluetooth Host (BlueZ), to connect it
 via UART or USB to one or more instances of the Zephyr OS Controller build.
 BlueZ as a Host supports multiple Controllers simultaneously for applications
-that require more than one BLE radio operating at the same time but sharing the
+that require more than one Bluetooth radio operating at the same time but sharing the
 same Host stack.
 
 Source tree layout
diff --git a/doc/connectivity/bluetooth/bluetooth-dev.rst b/doc/connectivity/bluetooth/bluetooth-dev.rst
index afefaf45a7e..999eb8f3d41 100644
--- a/doc/connectivity/bluetooth/bluetooth-dev.rst
+++ b/doc/connectivity/bluetooth/bluetooth-dev.rst
@@ -139,7 +139,7 @@ Simulated nRF5x with BabbleSim
 The :ref:`nrf52_bsim <nrf52_bsim>` and :ref:`nrf5340bsim <nrf5340bsim>` boards,
 are simulated target boards
 which emulate the necessary peripherals of a nRF52/53 SOC to be able to develop
-and test BLE applications.
+and test Bluetooth LE applications.
 These boards, use:
 
    * `BabbleSim`_ to simulate the nRF5x modem and the radio environment.
diff --git a/doc/connectivity/bluetooth/bluetooth-le-host.rst b/doc/connectivity/bluetooth/bluetooth-le-host.rst
index 26665ada3c3..53dc7d420c4 100644
--- a/doc/connectivity/bluetooth/bluetooth-le-host.rst
+++ b/doc/connectivity/bluetooth/bluetooth-le-host.rst
@@ -21,7 +21,7 @@ host, and vice-versa.
 
 Perhaps the most important block above the HCI handling is the Generic
 Access Profile (GAP). GAP simplifies Bluetooth LE access by defining
-four distinct roles of BLE usage:
+four distinct roles of Bluetooth usage:
 
 * Connection-oriented roles
 
@@ -31,9 +31,9 @@ four distinct roles of BLE usage:
 
 * Connection-less roles
 
-  * Broadcaster (sending out BLE advertisements, e.g. a smart beacon)
+  * Broadcaster (sending out Bluetooth LE advertisements, e.g. a smart beacon)
 
-  * Observer (scanning for BLE advertisements)
+  * Observer (scanning for Bluetooth LE advertisements)
 
 Each role comes with its own build-time configuration option:
 :kconfig:option:`CONFIG_BT_PERIPHERAL`, :kconfig:option:`CONFIG_BT_CENTRAL`,
@@ -49,7 +49,7 @@ section.
 Peripheral role
 ===============
 
-Most Zephyr-based BLE devices will most likely be peripheral-role
+Most Zephyr-based Bluetooth LE devices will most likely be peripheral-role
 devices. This means that they perform connectable advertising and expose
 one or more GATT services. After registering services using the
 :c:func:`bt_gatt_service_register` API the application will typically
diff --git a/doc/connectivity/bluetooth/bluetooth-tools.rst b/doc/connectivity/bluetooth/bluetooth-tools.rst
index 6e194adaa88..3d8c314a3f9 100644
--- a/doc/connectivity/bluetooth/bluetooth-tools.rst
+++ b/doc/connectivity/bluetooth/bluetooth-tools.rst
@@ -40,7 +40,7 @@ Using BlueZ with Zephyr
 ***********************
 
 The Linux Bluetooth Protocol Stack, BlueZ, comes with a very useful set of
-tools that can be used to debug and interact with Zephyr's BLE Host and
+tools that can be used to debug and interact with Zephyr's Bluetooth Host and
 Controller. In order to benefit from these tools you will need to make sure
 that you are running a recent version of the Linux Kernel and BlueZ:
 
@@ -62,7 +62,7 @@ You can then find :file:`btattach`, :file:`btmgt` and :file:`btproxy` in the
 :file:`tools/` folder and :file:`btmon` in the :file:`monitor/` folder.
 
 You'll need to enable BlueZ's experimental features so you can access its
-most recent BLE functionality. Do this by editing the file
+most recent Bluetooth functionality. Do this by editing the file
 :file:`/lib/systemd/system/bluetooth.service`
 and making sure to include the :literal:`-E` option in the daemon's execution
 start line:
@@ -160,11 +160,11 @@ building and running a sample:
 
      $ sudo ./build/zephyr/zephyr.exe --bt-dev=hci0
 
-Using a Zephyr-based BLE Controller
-===================================
+Using a Zephyr-based Bluetooth Controller
+=========================================
 
 Depending on which hardware you have available, you can choose between two
-transports when building a single-mode, Zephyr-based BLE Controller:
+transports when building a single-mode, Zephyr-based Bluetooth Controller:
 
 * UART: Use the :zephyr:code-sample:`bluetooth_hci_uart` sample and follow
   the instructions in :ref:`bluetooth-hci-uart-qemu-posix`.
@@ -309,7 +309,7 @@ peripheral samples such as :zephyr:code-sample:`ble_peripheral_hr` or
 Using Zephyr-based Controllers with BlueZ
 *****************************************
 
-If you want to test a Zephyr-powered BLE Controller using BlueZ's Bluetooth
+If you want to test a Zephyr-powered Bluetooth Controller using BlueZ's Bluetooth
 Host, you will need a few tools described in the :ref:`bluetooth_bluez` section.
 Once you have installed the tools you can then use them to interact with your
 Zephyr-based controller:
diff --git a/doc/connectivity/bluetooth/features.rst b/doc/connectivity/bluetooth/features.rst
index b51678ed7d7..ed94b100355 100644
--- a/doc/connectivity/bluetooth/features.rst
+++ b/doc/connectivity/bluetooth/features.rst
@@ -8,10 +8,10 @@ Supported features
     :depth: 2
 
 Since its inception, Zephyr has had a strong focus on Bluetooth and, in
-particular, on Bluetooth Low Energy (BLE). Through the contributions of
+particular, on Bluetooth Low Energy (LE). Through the contributions of
 several companies and individuals involved in existing open source
 implementations of the Bluetooth specification (Linux's BlueZ) as well as the
-design and development of BLE radio hardware, the protocol stack in Zephyr has
+design and development of Bluetooth LE radio hardware, the protocol stack in Zephyr has
 grown to be mature and feature-rich, as can be seen in the section below.
 
 * Bluetooth v5.3 compliant
@@ -41,7 +41,7 @@ grown to be mature and feature-rich, as can be seen in the section below.
   * All v5.3 specification features supported (except a few minor items)
   * Concurrent multi-protocol support ready
   * Intelligent scheduling of roles to minimize overlap
-  * Portable design to any open BLE radio, currently supports Nordic
+  * Portable design to any open Bluetooth LE radio, currently supports Nordic
     Semiconductor nRF52x and nRF53x SoC Series, as well as proprietary radios
   * Supports little and big endian architectures, and abstracts the hard
     real-time specifics so that they can be encapsulated in a hardware-specific
diff --git a/doc/connectivity/bluetooth/shell/audio/ccp.rst b/doc/connectivity/bluetooth/shell/audio/ccp.rst
index 1dc256a78be..0fbf3ed2181 100644
--- a/doc/connectivity/bluetooth/shell/audio/ccp.rst
+++ b/doc/connectivity/bluetooth/shell/audio/ccp.rst
@@ -33,3 +33,28 @@ Setup
    Registered GTBS bearer
    Registered bearer[1]
    uart:~$ bt connect xx:xx:xx:xx:xx:xx public
+
+Call Control Client
+*******************
+The Call Control Client is a role that typically resides on resource constrained devices such as
+earbuds or headsets.
+
+Using the Call Control Client
+=============================
+The Client can control a remote CCP server device.
+For example a remote device may have an incoming call that can be accepted by the Client.
+
+.. code-block:: console
+
+   uart:~$ ccp_call_control_client --help
+   ccp_call_control_client - Bluetooth CCP Call Control Client shell commands
+   Subcommands:
+     discover  : Discover GTBS and TBS on remote device
+
+Example Usage when connected
+============================
+
+.. code-block:: console
+
+   uart:~$ ccp_call_control_client discover
+   Discovery completed with GTBS and 1 TBS bearers
diff --git a/doc/connectivity/networking/api/apis.rst b/doc/connectivity/networking/api/apis.rst
index 12929088ac0..05804c47333 100644
--- a/doc/connectivity/networking/api/apis.rst
+++ b/doc/connectivity/networking/api/apis.rst
@@ -7,6 +7,7 @@ Network APIs
    :maxdepth: 1
 
    sockets.rst
+   socket_service.rst
    ip_4_6.rst
    dns_resolve.rst
    net_mgmt.rst
diff --git a/doc/connectivity/networking/api/http_server.rst b/doc/connectivity/networking/api/http_server.rst
index 9514e5ab8f7..2a357a35a07 100644
--- a/doc/connectivity/networking/api/http_server.rst
+++ b/doc/connectivity/networking/api/http_server.rst
@@ -29,6 +29,12 @@ Currently, the following resource types are supported:
 * Static resources - content defined compile-time, cannot be modified at runtime
   (:c:enumerator:`HTTP_RESOURCE_TYPE_STATIC`).
 
+* Static file system resources - the path at which the filesystem is mounted,
+  and the URL at which the filesystem is made available are fixed at build time,
+  but the content within the filesystem can be changed dynamically. This means that
+  the files can be created, modified or deleted by some other code outside the HTTP
+  server (:c:enumerator:`HTTP_RESOURCE_TYPE_STATIC_FS`).
+
 * Dynamic resources - content provided at runtime by respective application
   callback (:c:enumerator:`HTTP_RESOURCE_TYPE_DYNAMIC`).
 
@@ -101,7 +107,7 @@ macro:
 
     static uint16_t http_service_port = 80;
 
-    HTTP_SERVICE_DEFINE(my_service, "0.0.0.0", &http_service_port, 1, 10, NULL);
+    HTTP_SERVICE_DEFINE(my_service, "0.0.0.0", &http_service_port, 1, 10, NULL, NULL);
 
 Alternatively, an HTTPS service can be defined with
 :c:macro:`HTTPS_SERVICE_DEFINE`:
@@ -119,7 +125,43 @@ Alternatively, an HTTPS service can be defined with
     };
 
     HTTPS_SERVICE_DEFINE(my_service, "0.0.0.0", &https_service_port, 1, 10,
-                         NULL, sec_tag_list, sizeof(sec_tag_list));
+                         NULL, NULL, sec_tag_list, sizeof(sec_tag_list));
+
+The ``_res_fallback`` parameter can be used when defining an HTTP/HTTPS service to
+specify a fallback resource which will be used if no other resource matches the
+URL. This can be used for example to serve an index page for all unknown paths
+(useful for a single-page app which handles routing in the frontend), or for a
+customised 404 response.
+
+.. code-block:: c
+
+    static int default_handler(struct http_client_ctx *client, enum http_data_status status,
+		       const struct http_request_ctx *request_ctx,
+		       struct http_response_ctx *response_ctx, void *user_data)
+    {
+        static const char response_404[] = "Oops, page not found!";
+
+        if (status == HTTP_SERVER_DATA_FINAL) {
+            response_ctx->status = 404;
+            response_ctx->body = response_404;
+            response_ctx->body_len = sizeof(response_404) - 1;
+            response_ctx->final_chunk = true;
+        }
+
+        return 0;
+    }
+
+    static struct http_resource_detail_dynamic default_detail = {
+        .common = {
+            .type = HTTP_RESOURCE_TYPE_DYNAMIC,
+            .bitmask_of_supported_http_methods = BIT(HTTP_GET),
+        },
+        .cb = default_handler,
+        .user_data = NULL,
+    };
+
+    /* Register a fallback resource to handle any unknown path */
+    HTTP_SERVICE_DEFINE(my_service, "0.0.0.0", &http_service_port, 1, 10, NULL, &default_detail);
 
 .. note::
 
@@ -190,7 +232,8 @@ where ``src/index.html`` is the location of the webpage to be compressed.
 Static filesystem resources
 ===========================
 
-Static filesystem resource content is defined build-time and is immutable. The following
+Static filesystem resource content is defined build-time and is immutable. Note that only
+``GET`` operation is supported, user is not able to upload files to the filesystem. The following
 example shows how the path can be defined as a static resource in the application:
 
 .. code-block:: c
@@ -342,7 +385,7 @@ release it when done.
     static int ws_socket;
     static uint8_t ws_recv_buffer[1024];
 
-    int ws_setup(int sock, void *user_data)
+    int ws_setup(int sock, struct http_request_ctx *request_ctx, void *user_data)
     {
         ws_socket = sock;
         return 0;
diff --git a/doc/connectivity/networking/api/lwm2m.rst b/doc/connectivity/networking/api/lwm2m.rst
index cc48086613f..35952511b4a 100644
--- a/doc/connectivity/networking/api/lwm2m.rst
+++ b/doc/connectivity/networking/api/lwm2m.rst
@@ -504,7 +504,7 @@ Enabling and configuring
 
 Enable data cache by selecting :kconfig:option:`CONFIG_LWM2M_RESOURCE_DATA_CACHE_SUPPORT`.
 Application needs to allocate an array of :c:struct:`lwm2m_time_series_elem` structures and then
-enable the cache by calling :c:func:`lwm2m_engine_enable_cache` for a given resource. Each resource
+enable the cache by calling :c:func:`lwm2m_enable_cache` for a given resource. Each resource
 must be enabled separately and each resource needs their own storage.
 
 .. code-block:: c
@@ -512,7 +512,7 @@ must be enabled separately and each resource needs their own storage.
   /* Allocate data cache storage */
   static struct lwm2m_time_series_elem temperature_cache[10];
   /* Enable data cache */
-  lwm2m_engine_enable_cache(LWM2M_PATH(IPSO_OBJECT_TEMP_SENSOR_ID, 0, SENSOR_VALUE_RID),
+  lwm2m_enable_cache(LWM2M_OBJ(IPSO_OBJECT_TEMP_SENSOR_ID, 0, SENSOR_VALUE_RID),
           temperature_cache, ARRAY_SIZE(temperature_cache));
 
 LwM2M engine have room for four resources that have cache enabled. Limit can be increased by
diff --git a/doc/connectivity/networking/api/net_shell.rst b/doc/connectivity/networking/api/net_shell.rst
index 710b544eb7b..a6ab2ccd482 100644
--- a/doc/connectivity/networking/api/net_shell.rst
+++ b/doc/connectivity/networking/api/net_shell.rst
@@ -26,6 +26,8 @@ The following net-shell commands are implemented:
    resolve a DNS name. Only available if :kconfig:option:`CONFIG_DNS_RESOLVER` is set."
    "net events", "Enable network event monitoring. Only available if
    :kconfig:option:`CONFIG_NET_MGMT_EVENT_MONITOR` is set."
+   "net filter", "View network packet filter rules. Only available if
+   :kconfig:option:`CONFIG_NET_PKT_FILTER` is set."
    "net gptp", "Print information about gPTP support. Only available if
    :kconfig:option:`CONFIG_NET_GPTP` is set."
    "net iface", "Print information about network interfaces."
diff --git a/doc/connectivity/networking/api/socket_service.rst b/doc/connectivity/networking/api/socket_service.rst
new file mode 100644
index 00000000000..9ef85e3459d
--- /dev/null
+++ b/doc/connectivity/networking/api/socket_service.rst
@@ -0,0 +1,219 @@
+.. _socket_service_interface:
+
+Socket Services
+###############
+
+.. contents::
+    :local:
+    :depth: 2
+
+Overview
+********
+
+The socket service API can be used to install a handler that is called if there
+is data received on a socket. The API helps to avoid creating a dedicated thread
+for each TCP or UDP service that the application provides. Instead one thread
+is created that serves data to multiple listening sockets which saves memory
+as only one thread needs to be created in the system in this case.
+
+See :zephyr:code-sample:`sockets-service-echo` sample application to learn how
+to create a simple BSD socket based server application using the sockets service API.
+The source code for this sample application can be found at:
+:zephyr_file:`samples/net/sockets/echo_service`.
+
+API Description
+***************
+
+Socket service API is enabled using :kconfig:option:`CONFIG_NET_SOCKETS_SERVICE`
+config option and implements the following operations:
+
+* :c:macro:`NET_SOCKET_SERVICE_SYNC_DEFINE`
+
+  Define a network socket service. This socket service is created with extern
+  scope so it can be used from multiple C source files.
+
+* :c:macro:`NET_SOCKET_SERVICE_SYNC_DEFINE_STATIC`
+
+  Define a network socket service with static scope. This socket service can only
+  be used within one C source file.
+
+* :c:func:`net_socket_service_register`
+
+  Register pollable sockets for this service. User must create the sockets
+  before this call.
+
+* :c:func:`net_socket_service_unregister`
+
+  Remove pollable sockets for this service. User can close the sockets after
+  this call.
+
+* :c:type:`net_socket_service_handler_t`
+
+  User specified callback which is called when data is received on the
+  listening socket.
+
+Application Overview
+********************
+
+If the socket service API is enabled, an application must create the service like
+this:
+
+.. code-block:: c
+
+   #define MAX_BUF_LEN 1500
+   #define MAX_SERVICES 1
+
+   static void udp_service_handler(struct net_socket_service_event *pev)
+   {
+	struct pollfd *pfd = &pev->event;
+	int client = pfd->fd;
+	struct sockaddr_in6 addr;
+	socklen_t addrlen = sizeof(addr);
+
+	/* In this example we use one static buffer in order to avoid
+	 * having a large stack.
+	 */
+	static char buf[MAX_BUF_LEN];
+
+	len = recvfrom(client, buf, sizeof(buf), 0,
+		       (struct sockaddr *)&addr, &addrlen);
+	if (len <= 0) {
+		/* Error */
+		...
+		return;
+	}
+
+	/* Do something with the received data. The pev variable contains
+	 * user data that was stored in the socket service when it was
+	 * registered.
+	 */
+   }
+
+   NET_SOCKET_SERVICE_SYNC_DEFINE_STATIC(service_udp, udp_service_handler, MAX_SERVICES);
+
+The application needs to create the sockets, then register them to the socket
+service after which the socket service thread will start to call the callback
+for any incoming data.
+
+.. code-block:: c
+
+   /* Create one or multiple sockets */
+
+   struct pollfd sockfd_udp[1] = { 0 };
+   int sock, ret;
+
+   sock = socket(AF_INET6, SOCK_DGRAM, IPPROTO_UDP);
+   if (sock < 0) {
+	LOG_ERR("socket: %d", -errno);
+	return -errno;
+   }
+
+   /* Set possible socket options after creation */
+   ...
+
+   /* Then bind the socket to local address */
+   if (bind(sock, (struct sockaddr *)addr, sizeof(*addr)) < 0) {
+	LOG_ERR("bind: %d", -errno);
+	return -errno;
+   }
+
+   /* Set the polled sockets */
+   sockfd_udp[0].fd = sock;
+   sockfd_udp[0].events = POLLIN;
+
+   /* Register UDP socket to service handler */
+   ret = net_socket_service_register(&service_udp, sockfd_udp,
+				     ARRAY_SIZE(sockfd_udp), NULL);
+   if (ret < 0) {
+	LOG_ERR("Cannot register socket service handler (%d)", ret);
+	return ret;
+   }
+
+   /* Application logic happens here. When application is ready to
+    * quit, one should unregister the socket service and close the
+    * socket.
+    */
+
+   (void)net_socket_service_unregister(&service_udp);
+   close(sock);
+
+The TCP socket needs slightly different logic as we need to add any
+accepted socket to the listening socket by calling the
+:c:func:`net_socket_service_register` for the accepted socket.
+
+.. code-block:: c
+
+   struct sockaddr_in6 client_addr;
+   socklen_t client_addr_len = sizeof(client_addr);
+   struct pollfd sockfd_tcp[1] = { 0 };
+   int client;
+
+   /* TCP socket service is created similar way as the UDP one */
+   sock = socket(AF_INET6, SOCK_STREAM, IPPROTO_TCP);
+   if (sock < 0) {
+	LOG_ERR("socket: %d", -errno);
+	return -errno;
+   }
+
+   if (bind(sock, (struct sockaddr *)addr, sizeof(*addr)) < 0) {
+	LOG_ERR("bind: %d", -errno);
+	return -errno;
+   }
+
+   if (listen(sock, 5) < 0) {
+	LOG_ERR("listen: %d", -errno);
+	return -errno;
+   }
+
+   while (1) {
+	client = accept(tcp_sock, (struct sockaddr *)&client_addr,
+			&client_addr_len);
+	if (client < 0) {
+		LOG_ERR("accept: %d", -errno);
+		continue;
+	}
+
+	inet_ntop(client_addr.sin6_family, &client_addr.sin6_addr,
+		  addr_str, sizeof(addr_str));
+	LOG_INF("Connection from %s (%d)", addr_str, client);
+
+	sockfd_tcp[0].fd = client;
+	sockfd_tcp[0].events = POLLIN;
+
+	/* Register all the sockets to service handler */
+	ret = net_socket_service_register(&service_tcp, sockfd_tcp,
+					  ARRAY_SIZE(sockfd_tcp), NULL);
+	if (ret < 0) {
+		LOG_ERR("Cannot register socket service handler (%d)", ret);
+		break;
+	}
+   }
+
+For any closed TCP client connection we need to remove the closed
+socket from the polled socket list.
+
+.. code-block:: c
+
+   /* If the TCP socket is closed while reading the data in the handler,
+    * mark it as non pollable.
+    */
+   if (sockfd_tcp[0].fd == client) {
+	sockfd_tcp[0].fd = -1;
+
+	/* Update the handler so that client connection is
+	 * not monitored any more.
+	 */
+	 (void)net_socket_service_register(&service_tcp, sockfd_tcp,
+					   ARRAY_SIZE(sockfd_tcp), NULL);
+	 close(client);
+
+	 LOG_INF("Connection from %s closed", addr_str);
+   }
+
+Please see a more complete example in the ``echo_service`` sample source
+code at :zephyr_file:`samples/net/sockets/echo_service/src/main.c`.
+
+API Reference
+*************
+
+.. doxygengroup:: bsd_socket_service
diff --git a/doc/connectivity/networking/api/sockets.rst b/doc/connectivity/networking/api/sockets.rst
index 7a56f74a2aa..d5f5970a121 100644
--- a/doc/connectivity/networking/api/sockets.rst
+++ b/doc/connectivity/networking/api/sockets.rst
@@ -23,7 +23,7 @@ compatible API implementation for Zephyr:
   names like ``close()``, which may be part of libc or other POSIX
   compatibility libraries.
   If enabled by :kconfig:option:`CONFIG_POSIX_API`, it will also
-  expose native POSIX names.
+  expose POSIX compatible APIs.
 
 BSD Sockets compatible API is enabled using :kconfig:option:`CONFIG_NET_SOCKETS`
 config option and implements the following operations: ``socket()``, ``close()``,
@@ -57,6 +57,41 @@ there is a table mapping file descriptors to internal object pointers.
 The file descriptor table is used by the BSD Sockets API even if the rest
 of the POSIX subsystem (filesystem, stdin/stdout) is not enabled.
 
+Zephyr supports multiple types of BSD sockets, the following table summarizes
+what socket types are available:
+
++--------------+-------------+------------------+---------------------------------------------------------------------------+
+| Family       | Type        | Protocol         | Description                                                               |
++==============+=============+==================+===========================================================================+
+| AF_INET |br| | SOCK_DGRAM  | IPPROTO_UDP      | Enabled if :kconfig:option:`CONFIG_NET_UDP` is set. |br|                  |
+| AF_INET6     |             |                  | Allows to send and receive UDP datagrams.                                 |
+|              |             +------------------+---------------------------------------------------------------------------+
+|              |             | IPPROTO_DTLS_1_x | Enabled if :kconfig:option:`CONFIG_NET_SOCKETS_ENABLE_DTLS` is set. |br|  |
+|              |             |                  | Allows to send and receive DTLS datagrams.                                |
+|              +-------------+------------------+---------------------------------------------------------------------------+
+|              | SOCK_STREAM | IPPROTO_TCP      | Enabled if :kconfig:option:`CONFIG_NET_TCP` is set. |br|                  |
+|              |             |                  | Allows to send and receive TCP data stream.                               |
+|              |             +------------------+---------------------------------------------------------------------------+
+|              |             | IPPROTO_TLS_1_x  | Enabled if :kconfig:option:`CONFIG_NET_SOCKETS_SOCKOPT_TLS` is set. |br|  |
+|              |             |                  | Allows to send and receive TLS data stream.                               |
+|              +-------------+------------------+---------------------------------------------------------------------------+
+|              | SOCK_RAW    | IPPROTO_IP |br|  | Enabled if :kconfig:option:`CONFIG_NET_SOCKETS_INET_RAW` is set. |br|     |
+|              |             | <proto>          | Allows to send and receive IPv4/IPv6 datagrams. |br|                      |
+|              |             |                  | Packets are filtered by L4 protocol specified.                            |
+|              |             |                  | IPPROTO_IP is a wildcard protocol to receive all IP datagrams.            |
++--------------+-------------+------------------+---------------------------------------------------------------------------+
+| AF_PACKET    | SOCK_DGRAM  | ETH_P_ALL |br|   | Enabled if :kconfig:option:`CONFIG_NET_SOCKETS_PACKET_DGRAM` is set. |br| |
+|              |             | <proto>          | Allows to send and receive packets without L2 header. |br|                |
+|              |             |                  | Packets are filtered by L3 protocol specified.                            |
+|              |             |                  | ETH_P_ALL is a wildcard protocol to receive all packets.                  |
+|              +-------------+------------------+---------------------------------------------------------------------------+
+|              | SOCK_RAW    | ETH_P_ALL        | Enabled if :kconfig:option:`CONFIG_NET_SOCKETS_PACKET` is set. |br|       |
+|              |             |                  | Allows to send and receive packets with L2 header included.               |
++--------------+-------------+------------------+---------------------------------------------------------------------------+
+| AF_CAN       | SOCK_RAW    | CAN_RAW          | Enabled if :kconfig:option:`CONFIG_NET_SOCKETS_CAN` is set. |br|          |
+|              |             |                  | Allows to send and receive CAN packets.                                   |
++--------------+-------------+------------------+---------------------------------------------------------------------------+
+
 See :zephyr:code-sample:`sockets-echo-server` and :zephyr:code-sample:`sockets-echo-client`
 sample applications to learn how to create a simple server or client BSD socket based
 application.
diff --git a/doc/connectivity/networking/api/wifi.rst b/doc/connectivity/networking/api/wifi.rst
index 7e7d435a9d3..e480f25a3b8 100644
--- a/doc/connectivity/networking/api/wifi.rst
+++ b/doc/connectivity/networking/api/wifi.rst
@@ -42,16 +42,31 @@ Test certificates in PEM format are committed to the repo at :zephyr_file:`sampl
 build process the certificates are converted to a C header file that is included by the Wi-Fi shell
 module.
 
+If you want to use your own certificates, you can replace the existing certificates with your own certificates in the same directory.
+
 .. code-block:: bash
 
-    $ cp client.pem samples/net/wifi/test_certs/
-    $ cp client-key.pem samples/net/wifi/test_certs/
-    $ cp ca.pem samples/net/wifi/test_certs/
-    $ cp client2.pem samples/net/wifi/test_certs/
-    $ cp client-key2.pem samples/net/wifi/test_certs/
-    $ cp ca2.pem samples/net/wifi/test_certs/
+    $ export WIFI_TEST_CERTS_DIR=samples/net/wifi/test_certs/rsa3k
+    $ cp client.pem $WIFI_TEST_CERTS_DIR
+    $ cp client-key.pem $WIFI_TEST_CERTS_DIR
+    $ cp ca.pem $WIFI_TEST_CERTS_DIR
+    $ cp client2.pem $WIFI_TEST_CERTS_DIR
+    $ cp client-key2.pem $WIFI_TEST_CERTS_DIR
+    $ cp ca2.pem $WIFI_TEST_CERTS_DIR
     $ west build -p -b <board> samples/net/wifi -S wifi-enterprise
 
+or alternatively copy ``rsa2k`` certificates by changing the ``WIFI_TEST_CERTS_DIR`` environment variable.
+
+.. code-block:: bash
+
+    $ export WIFI_TEST_CERTS_DIR=samples/net/wifi/test_certs/rsa2k
+
+or you can set the :envvar:`WIFI_TEST_CERTS_DIR` environment variable to point to the directory containing your certificates.
+
+.. code-block:: bash
+
+    $ west build -p -b <board> samples/net/wifi -S wifi-enterprise -- -DWIFI_TEST_CERTS_DIR=<path_to_your_certificates>
+
 Run time certificates
 ---------------------
 
diff --git a/doc/connectivity/networking/api/zperf.rst b/doc/connectivity/networking/api/zperf.rst
index fe09823c057..02e774d778f 100644
--- a/doc/connectivity/networking/api/zperf.rst
+++ b/doc/connectivity/networking/api/zperf.rst
@@ -13,13 +13,8 @@ Overview
 zperf is a shell utility which allows to generate network traffic in Zephyr. The
 tool may be used to evaluate network bandwidth.
 
-zperf is compatible with iPerf_2.0.5. Note that in newer iPerf versions,
-an error message like this is printed and the server reported statistics
-are missing.
-
-.. code-block:: console
-
-   LAST PACKET NOT RECEIVED!!!
+zperf is compatible with iPerf 2.0.10 and newer. For compatability with older versions,
+enable :kconfig:option:`CONFIG_NET_ZPERF_LEGACY_HEADER_COMPAT`.
 
 zperf can be enabled in any application, a dedicated sample is also present
 in Zephyr. See :zephyr:code-sample:`zperf sample application <zperf>` for details.
@@ -101,3 +96,143 @@ and this if you are testing TCP:
 
 iPerf output can be limited by using the -b option if Zephyr is not
 able to receive all the packets in orderly manner.
+
+Session Management
+******************
+
+If :kconfig:option:`CONFIG_ZPERF_SESSION_PER_THREAD` option is set, then
+multiple upload sessions can be done at the same time if user supplies ``-a``
+option when starting the upload. Each session will have their own work queue
+to run the test. The session test results can be viewed also after the tests
+have finished. The sessions can be started with ``-w`` option which then
+lets the worker threads to wait a start signal so that all the threads can
+be started at the same time. This will prevent the case where the zperf shell
+cannot run because it is running in lower priority than the already started
+session thread. If you have only one upload session, then the ``-w`` is not
+really needed.
+
+Following zperf shell commands are available for session management:
+
+.. csv-table::
+   :header: "zperf shell command", "Description"
+   :widths: auto
+
+   "``jobs``", "Show currently active or finished sessions"
+   "``jobs all``", "Show statistics of finished sessions"
+   "``jobs clear``", "Clear finished session statistics"
+   "``jobs start``", "Start all the waiting sessions"
+
+Example:
+
+.. code-block:: console
+
+   uart:~$ zperf udp upload -a -t 5 192.0.2.2 5001 10 1K 1M
+   Remote port is 5001
+   Connecting to 192.0.2.2
+   Duration:       10.00 s
+   Packet size:    1000 bytes
+   Rate:           1000 kbps
+   Starting...
+   Rate:           1.00 Mbps
+   Packet duration 7 ms
+
+   uart:~$ zperf jobs all
+   No sessions sessions found
+   uart:~$ zperf jobs
+              Thread    Remaining
+   Id  Proto  Priority  time (sec)
+   [1] UDP    5            4
+
+   Active sessions have not yet finished
+   -
+   Upload completed!
+   Statistics:             server  (client)
+   Duration:               30.01 s (30.01 s)
+   Num packets:            3799    (3799)
+   Num packets out order:  0
+   Num packets lost:       0
+   Jitter:                 63 us
+   Rate:                   1.01 Mbps       (1.01 Mbps)
+   Thread priority:        5
+   Protocol:               UDP
+   Session id:             1
+
+   uart:~$ zperf jobs all
+   -
+   Upload completed!
+   Statistics:             server  (client)
+   Duration:               30.01 s (30.01 s)
+   Num packets:            3799    (3799)
+   Num packets out order:  0
+   Num packets lost:       0
+   Jitter:                 63 us
+   Rate:                   1.01 Mbps       (1.01 Mbps)
+   Thread priority:        5
+   Protocol:               UDP
+   Session id:             1
+   Total 1 sessions done
+
+   uart:~$ zperf jobs clear
+   Cleared data from 1 sessions
+
+   uart:~$ zperf jobs
+   No active upload sessions
+   No finished sessions found
+
+The ``-w`` option can be used like this to delay the startup of the jobs.
+
+.. code-block:: console
+
+   uart:~$ zperf tcp upload -a -t 6 -w 192.0.2.2 5001 10 1K
+   Remote port is 5001
+   Connecting to 192.0.2.2
+   Duration:       10.00 s
+   Packet size:    1000 bytes
+   Rate:           10 kbps
+   Waiting "zperf jobs start" command.
+   [01:06:51.392,288] <inf> net_zperf: [0] TCP waiting for start
+
+   uart:~$ zperf udp upload -a -t 6 -w 192.0.2.2 5001 10 1K 10M
+   Remote port is 5001
+   Connecting to 192.0.2.2
+   Duration:       10.00 s
+   Packet size:    1000 bytes
+   Rate:           10000 kbps
+   Waiting "zperf jobs start" command.
+   Rate:           10.00 Mbps
+   Packet duration 781 us
+   [01:06:58.064,552] <inf> net_zperf: [0] UDP waiting for start
+
+   uart:~$ zperf jobs start
+   -
+   Upload completed!
+   -
+   Upload completed!
+
+   # Note that the output may be garbled as two threads printed
+   # output at the same time. Just print out the fresh listing
+   # like this.
+
+   uart:~$ zperf jobs all
+   -
+   Upload completed!
+   Statistics:             server  (client)
+   Duration:               9.99 s  (10.00 s)
+   Num packets:            11429   (11429)
+   Num packets out order:  0
+   Num packets lost:       0
+   Jitter:                 164 us
+   Rate:                   9.14 Mbps       (9.14 Mbps)
+   Thread priority:        6
+   Protocol:               UDP
+   Session id:             0
+   -
+   Upload completed!
+   Duration:               10.00 s
+   Num packets:            15487
+   Num errors:             0 (retry or fail)
+   Rate:                   12.38 Mbps
+   Thread priority:        6
+   Protocol:               TCP
+   Session id:             0
+   Total 2 sessions done
diff --git a/doc/connectivity/networking/dsa.rst b/doc/connectivity/networking/dsa.rst
new file mode 100644
index 00000000000..b4d3c79f443
--- /dev/null
+++ b/doc/connectivity/networking/dsa.rst
@@ -0,0 +1,129 @@
+.. _dsa:
+
+Distributed Switch Architecture (DSA)
+#####################################
+
+.. contents::
+    :local:
+    :depth: 2
+
+Distributed Switch Architecture (DSA) is not something new. It has been a mature
+subsystem in Linux for many years. This document just skips the background,
+terms and any knowledge related description, as user may find all of these in
+`Linux DSA documentation`_.
+
+
+DSA switch TX/RX process
+************************
+
+The DSA switch TX/RX process is as below.
+
+.. image:: dsa_txrx_process.svg
+
+Host interface
+**************
+
+Host interface network devices use regular and unmodified ethernet driver working
+as DSA conduit port, which manages the switch through processor.
+
+Switch interface
+****************
+
+The switch interfaces are also exposed as standard ethernet interfaces in zephyr.
+The one connected to conduit port work as CPU port, and the others for user purpose
+work as user ports.
+
+Switch tagging protocols
+************************
+
+Generally, switch tagging protocols are vendor specific. They all contain something which:
+
+- identifies which port the Ethernet frame came from/should be sent to
+- provides a reason why this frame was forwarded to the management interface
+
+And tag on the packets to give them a switch frame header. But there are also tag-less case.
+It depends on the vendor.
+
+Networking stack process
+************************
+
+In order to have the DSA subsystem process the Ethernet switch specific tagging protocol
+via conduit port.
+
+For RX path, put ``dsa_recv()`` at beginning of ``net_recv_data()`` in ``subsys/net/ip/net_core.c``
+to handle first for untagging and re-directing interface.
+
+For TX path, the switch interfaces register as standard ethernet devices with ``dsa_xmit()``
+as ``ethernet_api->send``. The ``dsa_xmit()`` processes the tagging and re-directing to conduit
+port work.
+
+DSA device driver support
+*************************
+
+As the DSA core driver interacts with subsystems/drivers including MDIO, PHY and device tree to
+to support the common DSA setup and working process. The device driver support is much easy.
+
+For device tree, the switch description should be following the ``dts/bindings/dsa/dsa.yaml``.
+
+For device driver, all needed to prepare are :c:struct:`dsa_api`, private data if has, and
+:c:struct:`dsa_port_config`. The macro functions could be utilized. And below is an example
+of i.MX NETC.
+
+- :c:macro:`DSA_SWITCH_INST_INIT`
+- :c:macro:`DSA_PORT_INST_INIT`
+
+.. code-block:: c
+
+   #define DSA_NETC_PORT_INST_INIT(port, n)                                                    \
+           COND_CODE_1(DT_NUM_PINCTRL_STATES(port),                                            \
+                           (PINCTRL_DT_DEFINE(port);), (EMPTY))                                \
+           struct dsa_netc_port_config dsa_netc_##n##_##port##_config = {                      \
+                   .pincfg = COND_CODE_1(DT_NUM_PINCTRL_STATES(port),                          \
+                                   (PINCTRL_DT_DEV_CONFIG_GET(port)), NULL),                   \
+                   .phy_mode = NETC_PHY_MODE(port),                                            \
+           };                                                                                  \
+           struct dsa_port_config dsa_##n##_##port##_config = {                                \
+                   .use_random_mac_addr = DT_NODE_HAS_PROP(port, zephyr_random_mac_address),   \
+                   .mac_addr = DT_PROP_OR(port, local_mac_address, {0}),                       \
+                   .port_idx = DT_REG_ADDR(port),                                              \
+                   .phy_dev = DEVICE_DT_GET_OR_NULL(DT_PHANDLE(port, phy_handle)),             \
+                   .phy_mode = DT_PROP_OR(port, phy_connection_type, ""),                      \
+                   .ethernet_connection = DEVICE_DT_GET_OR_NULL(DT_PHANDLE(port, ethernet)),   \
+                   .prv_config = &dsa_netc_##n##_##port##_config,                              \
+           };                                                                                  \
+           DSA_PORT_INST_INIT(port, n, &dsa_##n##_##port##_config)
+
+   #define DSA_NETC_DEVICE(n)                                                                  \
+           AT_NONCACHEABLE_SECTION_ALIGN(static netc_cmd_bd_t dsa_netc_##n##_cmd_bd[8],        \
+                                         NETC_BD_ALIGN);                                       \
+           static struct dsa_netc_data dsa_netc_data_##n = {                                   \
+                   .cmd_bd = dsa_netc_##n##_cmd_bd,                                            \
+           };                                                                                  \
+           DSA_SWITCH_INST_INIT(n, &dsa_netc_api, &dsa_netc_data_##n, DSA_NETC_PORT_INST_INIT);
+
+Common pitfalls using DSA setups
+********************************
+
+This is copied from Linux DSA documentation. It applies to zephyr too. Although conduit port and
+cpu port exposed as ethernet device in zephyr, they are not able to be used.
+
+.. note::
+
+  Once a conduit network device is configured to use DSA (dev->dsa_ptr becomes non-NULL), and
+  the switch behind it expects a tagging protocol, this network interface can only exclusively
+  be used as a conduit interface. Sending packets directly through this interface (e.g.: opening
+  a socket using this interface) will not make us go through the switch tagging protocol transmit
+  function, so the Ethernet switch on the other end, expecting a tag will typically drop this frame.
+
+TODO work
+*********
+
+Comparing to Linux, there are too much features to support in/based on zephyr DSA. But basically
+bridge layer should be supported. Then DSA could provide two options for users to use switch ports.
+
+- Standalone mode: all user ports work as regular ethernet devices. No switching.
+- Bridge mode: switch mode enabled with adding user ports into virtual bridge device. IP address could
+  be assigned to the bridge.
+
+.. _Linux DSA documentation:
+   https://www.kernel.org/doc/html/latest/networking/dsa/dsa.html
diff --git a/doc/connectivity/networking/dsa_txrx_process.svg b/doc/connectivity/networking/dsa_txrx_process.svg
new file mode 100644
index 00000000000..8c55d4bd1a9
--- /dev/null
+++ b/doc/connectivity/networking/dsa_txrx_process.svg
@@ -0,0 +1 @@
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diff --git a/doc/connectivity/networking/eth_bridge_native_sim_setup.rst b/doc/connectivity/networking/eth_bridge_native_sim_setup.rst
index 69c8fa7845f..20554e376db 100644
--- a/doc/connectivity/networking/eth_bridge_native_sim_setup.rst
+++ b/doc/connectivity/networking/eth_bridge_native_sim_setup.rst
@@ -58,10 +58,10 @@ Then create a sample and enable Ethernet bridging support. In this example we cr
 
    west build -p -b native_sim -d ../build/echo-server \
       samples/net/sockets/echo_server -- \
-      -DCONFIG_NATIVE_UART_AUTOATTACH_DEFAULT_CMD="\"gnome-terminal -- screen %s\"" \
+      -DCONFIG_UART_NATIVE_PTY_AUTOATTACH_DEFAULT_CMD="\"gnome-terminal -- screen %s\"" \
       -DCONFIG_NET_ETHERNET_BRIDGE=y \
       -DCONFIG_NET_ETHERNET_BRIDGE_SHELL=y \
-      -DCONFIG_ETH_NATIVE_POSIX_INTERFACE_COUNT=2 \
+      -DCONFIG_ETH_NATIVE_TAP_INTERFACE_COUNT=2 \
       -DCONFIG_NET_IF_MAX_IPV6_COUNT=2 \
       -DCONFIG_NET_IF_MAX_IPV4_COUNT=2
    ../build/echo-server/zephyr/zephyr.exe -attach_uart
diff --git a/doc/connectivity/networking/index.rst b/doc/connectivity/networking/index.rst
index 2a34c1330ec..18e3032978b 100644
--- a/doc/connectivity/networking/index.rst
+++ b/doc/connectivity/networking/index.rst
@@ -18,3 +18,4 @@ operation of the stacks and how they were implemented.
    network_tracing.rst
    api/index.rst
    conn_mgr/index.rst
+   dsa.rst
diff --git a/doc/connectivity/networking/native_sim_setup.rst b/doc/connectivity/networking/native_sim_setup.rst
index 70f6469abcb..4e6257d22d4 100644
--- a/doc/connectivity/networking/native_sim_setup.rst
+++ b/doc/connectivity/networking/native_sim_setup.rst
@@ -145,18 +145,29 @@ For TCP test, type:
 
    ./echo-client -t 127.0.0.1
 
-Setting interface name from command line
-****************************************
+Setting interface name and IPv4 parameters from command line
+************************************************************
 
 By default the Ethernet interface name used by native_sim is determined by
-:kconfig:option:`CONFIG_ETH_NATIVE_POSIX_DRV_NAME`, but is also possible
+:kconfig:option:`CONFIG_ETH_NATIVE_TAP_DRV_NAME`, but is also possible
 to set it from the command line using ``--eth-if=<interface_name>``.
+
+The same applies to the IPv4 address, gateway and netmask. They can be set
+from the command line using ``--ipv4-addr=<ip_address>``,
+``--ipv4-gw=<gateway>`` and ``--ipv4-nm=<netmask>``.
+
+Note that the configuration :kconfig:option:`CONFIG_NET_CONFIG_MY_IPV4_ADDR`
+and the command line arguments work in parallel. This means that if both are
+set, the interface might end up with two IP addresses. In most cases, it does
+make sense to only use one of both at the same time.
+
 This can be useful if the application has to be
 run in multiple instances and recompiling it for each instance would be
 troublesome.
 
 .. code-block:: console
 
-   ./zephyr.exe --eth-if=zeth2
+   ./zephyr.exe --eth-if=zeth2 --ipv4-addr=192.0.2.2 --ipv4-gw=192.0.0.1
+   --ipv4-nm=255.255.0.0
 
 .. _`net-tools`: https://github.com/zephyrproject-rtos/net-tools
diff --git a/doc/connectivity/networking/network_monitoring.rst b/doc/connectivity/networking/network_monitoring.rst
index 6a41dafea40..a389f621506 100644
--- a/doc/connectivity/networking/network_monitoring.rst
+++ b/doc/connectivity/networking/network_monitoring.rst
@@ -117,7 +117,7 @@ In terminal #3, type:
    :zephyr-app: samples/net/capture
    :host-os: unix
    :board: native_sim
-   :gen-args: -DCONFIG_NATIVE_UART_AUTOATTACH_DEFAULT_CMD=\""gnome-terminal -- screen %s"\"
+   :gen-args: -DCONFIG_UART_NATIVE_PTY_AUTOATTACH_DEFAULT_CMD=\""gnome-terminal -- screen %s"\"
    :goals: build
    :compact:
 
diff --git a/doc/connectivity/networking/networking_with_multiple_instances.rst b/doc/connectivity/networking/networking_with_multiple_instances.rst
index 225d50ebb39..064ed4b730f 100644
--- a/doc/connectivity/networking/networking_with_multiple_instances.rst
+++ b/doc/connectivity/networking/networking_with_multiple_instances.rst
@@ -153,9 +153,9 @@ or if you want to use native_sim board, type this:
       -DCONFIG_NET_CONFIG_MY_IPV6_ADDR=\"2001:db8:100::1\" \
       -DCONFIG_NET_CONFIG_PEER_IPV6_ADDR=\"2001:db8:200::1\" \
       -DCONFIG_NET_CONFIG_MY_IPV4_GW=\"203.0.113.1\" \
-      -DCONFIG_ETH_NATIVE_POSIX_DRV_NAME=\"zeth.1\" \
-      -DCONFIG_ETH_NATIVE_POSIX_MAC_ADDR=\"00:00:5e:00:53:01\" \
-      -DCONFIG_ETH_NATIVE_POSIX_RANDOM_MAC=n
+      -DCONFIG_ETH_NATIVE_TAP_DRV_NAME=\"zeth.1\" \
+      -DCONFIG_ETH_NATIVE_TAP_MAC_ADDR=\"00:00:5e:00:53:01\" \
+      -DCONFIG_ETH_NATIVE_TAP_RANDOM_MAC=n
 
 
 In terminal #5, if you are using QEMU, type this:
@@ -184,9 +184,9 @@ or if you want to use native_sim board, type this:
       -DCONFIG_NET_CONFIG_MY_IPV6_ADDR=\"2001:db8:200::1\" \
       -DCONFIG_NET_CONFIG_PEER_IPV6_ADDR=\"2001:db8:100::1\" \
       -DCONFIG_NET_CONFIG_MY_IPV4_GW=\"198.51.100.1\" \
-      -DCONFIG_ETH_NATIVE_POSIX_DRV_NAME=\"zeth.2\" \
-      -DCONFIG_ETH_NATIVE_POSIX_MAC_ADDR=\"00:00:5e:00:53:02\" \
-      -DCONFIG_ETH_NATIVE_POSIX_RANDOM_MAC=n
+      -DCONFIG_ETH_NATIVE_TAP_DRV_NAME=\"zeth.2\" \
+      -DCONFIG_ETH_NATIVE_TAP_MAC_ADDR=\"00:00:5e:00:53:02\" \
+      -DCONFIG_ETH_NATIVE_TAP_RANDOM_MAC=n
 
 
 Also if you have firewall enabled in your host, you need to allow traffic
diff --git a/doc/connectivity/usb/device/usb_device.rst b/doc/connectivity/usb/device/usb_device.rst
index 2e5649edbe1..37da1f464f6 100644
--- a/doc/connectivity/usb/device/usb_device.rst
+++ b/doc/connectivity/usb/device/usb_device.rst
@@ -27,9 +27,9 @@ over time. It provides the following functionalities:
 
 .. note::
    It is planned to deprecate all APIs listed in :ref:`usb_api` and the
-   functions that depend on them between Zephyr v4.0.0 and v4.1.0, and remove
-   them in v4.3.0. The new USB device support, represented by the APIs in
-   :ref:`usb_device_next_api`, will become the default in Zephyr v4.1.0.
+   functions that depend on them between Zephyr v4.1.0 and v4.2.0, and remove
+   them in v4.4.0. The new USB device support, represented by the APIs in
+   :ref:`usb_device_next_api`, will become the default in Zephyr v4.2.0.
 
 Supported USB classes
 *********************
@@ -391,61 +391,6 @@ BOS descriptor and handled by the stack.
 
 See :zephyr:code-sample:`webusb` sample for reference.
 
-Implementing a non-standard USB class
-*************************************
-
-The configuration of USB device is done in the stack layer.
-
-The following structures and callbacks need to be defined:
-
-* Part of USB Descriptor table
-* USB Endpoint configuration table
-* USB Device configuration structure
-* Endpoint callbacks
-* Optionally class, vendor and custom handlers
-
-For example, for the USB loopback application:
-
-.. literalinclude:: ../../../../subsys/usb/device/class/loopback.c
-   :language: c
-   :start-after: usb.rst config structure start
-   :end-before: usb.rst config structure end
-   :linenos:
-
-Endpoint configuration:
-
-.. literalinclude:: ../../../../subsys/usb/device/class/loopback.c
-   :language: c
-   :start-after: usb.rst endpoint configuration start
-   :end-before: usb.rst endpoint configuration end
-   :linenos:
-
-USB Device configuration structure:
-
-.. literalinclude:: ../../../../subsys/usb/device/class/loopback.c
-   :language: c
-   :start-after: usb.rst device config data start
-   :end-before: usb.rst device config data end
-   :linenos:
-
-
-The vendor device requests are forwarded by the USB stack core driver to the
-class driver through the registered vendor handler.
-
-For the loopback class driver, :c:func:`loopback_vendor_handler` processes
-the vendor requests:
-
-.. literalinclude:: ../../../../subsys/usb/device/class/loopback.c
-   :language: c
-   :start-after: usb.rst vendor handler start
-   :end-before:  usb.rst vendor handler end
-   :linenos:
-
-The class driver waits for the :makevar:`USB_DC_CONFIGURED` device status code
-before transmitting any data.
-
-.. _testing_USB_native_sim:
-
 Interface number and endpoint address assignment
 ************************************************
 
@@ -510,6 +455,8 @@ prevent you from implementing a hardware-clone firmware. Instead, if possible,
 the host driver implementation should be fixed to use values from the interface
 and endpoint descriptor.
 
+.. _testing_USB_native_sim:
+
 Testing over USBIP in native_sim
 ********************************
 
diff --git a/doc/connectivity/usb/device_next/api/index.rst b/doc/connectivity/usb/device_next/api/index.rst
index 26065820664..8b5c3d730e4 100644
--- a/doc/connectivity/usb/device_next/api/index.rst
+++ b/doc/connectivity/usb/device_next/api/index.rst
@@ -11,3 +11,5 @@ New USB device support APIs
    usbd_hid_device.rst
    uac2_device.rst
    usbd_msc_device.rst
+   usbd_midi2.rst
+   usbd_dfu.rst
diff --git a/doc/connectivity/usb/device_next/api/usbd_dfu.rst b/doc/connectivity/usb/device_next/api/usbd_dfu.rst
new file mode 100644
index 00000000000..4059fca099f
--- /dev/null
+++ b/doc/connectivity/usb/device_next/api/usbd_dfu.rst
@@ -0,0 +1,11 @@
+.. _usbd_dfu:
+
+USB DFU device API
+##################
+
+USB DFU device specific API defined in :zephyr_file:`include/zephyr/usb/class/usbd_dfu.h`.
+
+API Reference
+*************
+
+.. doxygengroup:: usbd_dfu
diff --git a/doc/connectivity/usb/device_next/api/usbd_midi2.rst b/doc/connectivity/usb/device_next/api/usbd_midi2.rst
new file mode 100644
index 00000000000..d774f538961
--- /dev/null
+++ b/doc/connectivity/usb/device_next/api/usbd_midi2.rst
@@ -0,0 +1,12 @@
+.. _usbd_midi2:
+
+MIDI 2.0 Class device API
+#########################
+
+USB MIDI 2.0 device specific API defined in :zephyr_file:`include/zephyr/usb/class/usbd_midi2.h`.
+
+API Reference
+*************
+
+.. doxygengroup:: usbd_midi2
+.. doxygengroup:: midi_ump
diff --git a/doc/connectivity/usb/host/usbip.rst b/doc/connectivity/usb/host/usbip.rst
new file mode 100644
index 00000000000..5c6495406cc
--- /dev/null
+++ b/doc/connectivity/usb/host/usbip.rst
@@ -0,0 +1,79 @@
+.. _usbip:
+
+USB/IP protocol support
+#######################
+
+Overview
+********
+
+New USB support includes initial support for the USB/IP protocol. It is still
+under development and is currently limited to supporting only one device
+connected to the host controller being exported.
+
+USB/IP uses TCP/IP. Both of the underlying connectivity stacks, USB and
+networking, require significant memory resources, which must be considered when
+choosing a platform.
+
+In the USB/IP protocol, a server exports the USB devices and a client imports
+them. USB/IP support in the Zephyr RTOS implements server functionality and
+exports a device connected to a host controller on a device running the Zephyr
+RTOS. A client, typically running the Linux kernel, imports this device. The
+USB/IP protocol is described in `USB/IP protocol documentation`_.
+
+To use USB/IP support, make sure the required modules are loaded on the client side.
+
+.. code-block:: console
+
+   modprobe vhci_hcd
+   modprobe usbip-core
+   modprobe usbip-host
+
+On the client side, you will also need the **usbip** user tool. It can be installed
+using your Linux distribution's package management system or built from Linux
+kernel sources.
+
+There are a few basic commands for everyday use. To list exported USB devices,
+run the following command:
+
+.. code-block:: console
+
+   $ usbip list -r 192.0.2.1
+   Exportable USB devices
+   ======================
+    - 192.0.2.1
+           1-1: NordicSemiconductor : unknown product (2fe3:0001)
+              : /sys/bus/usb/devices/usb1/1-1
+              : Miscellaneous Device / ? / Interface Association (ef/02/01)
+              :  0 - Communications / Abstract (modem) / None (02/02/00)
+              :  1 - CDC Data / Unused / unknown protocol (0a/00/00)
+
+To attach an exported device with busid 1-1:
+
+.. code-block:: console
+
+   $ sudo usbip attach -r 192.0.2.1 -b 1-1
+
+To detach an exported device on port 0:
+
+.. code-block:: console
+
+   $ sudo usbip detach -p 0
+
+USB/IP with native_sim
+**********************
+
+The preferred method to develop with USB/IP support enabled is to use
+:ref:`native_sim <native_sim>`. Use on real hardware is not really tested yet.
+USB/IP requires a network connection, see :ref:`networking_with_native_sim`
+for how to set up the interface on the client side.
+
+Building and running a sample with USB/IP requires extensive configuration,
+you can use usbip-native-sim snippet to configure host and USB/IP support.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/subsys/usb/cdc_acm
+   :board: native_sim/native/64
+   :gen-args: -DSNIPPET=usbip-native-sim -DEXTRA_DTC_OVERLAY_FILE=app.overlay
+   :goals: build
+
+.. _USB/IP protocol documentation: https://www.kernel.org/doc/html/latest/usb/usbip_protocol.html
diff --git a/doc/connectivity/usb/index.rst b/doc/connectivity/usb/index.rst
index b24bcb9954b..74d880ed839 100644
--- a/doc/connectivity/usb/index.rst
+++ b/doc/connectivity/usb/index.rst
@@ -19,6 +19,7 @@ USB
    device_next/usb_device.rst
    device_next/api/index.rst
    host/api/index.rst
+   host/usbip.rst
 
 **USB Power Delivery support**
 
diff --git a/doc/contribute/coding_guidelines/index.rst b/doc/contribute/coding_guidelines/index.rst
index 3c74ee2a324..131a7f31b1c 100644
--- a/doc/contribute/coding_guidelines/index.rst
+++ b/doc/contribute/coding_guidelines/index.rst
@@ -3,42 +3,6 @@
 Coding Guidelines
 #################
 
-The project TSC and the Safety Committee of the project agreed to implement
-a staged and incremental approach for complying with a set of coding rules (AKA
-Coding Guidelines) to improve quality and consistency of the code base. Below
-are the agreed upon stages:
-
-Stage I (COMPLETED)
-  Coding guideline rules are available to be followed and referenced,
-  but not enforced. Rules are not yet enforced in CI and pull-requests cannot be
-  blocked by reviewers/approvers due to violations.
-
-Stage II
-  Begin enforcement on a limited scope of the code base. Initially, this would be
-  the safety certification scope. For rules easily applied across codebase, we
-  should not limit compliance to initial scope. This step requires tooling,
-  CI setup and an enforcement strategy.
-
-Stage III
-  Revisit the coding guideline rules and based on experience from previous
-  stages, refine/iterate on selected rules.
-
-Stage IV
-   Expand enforcement to the wider codebase. Exceptions may be granted on some
-   areas of the codebase with a proper justification. Exception would require
-   TSC approval.
-
-.. note::
-
-    Coding guideline rules may be removed/changed at any time by filing a
-    GH issue/RFC.
-
-.. important::
-
-    **Current stage:**
-    The prerequisites for entering **Stage II** are currently being looked at:
-    The tooling is in evaluation, CI setup and `enforcement strategy
-    <https://github.com/zephyrproject-rtos/zephyr/issues/58903>`__ is being worked on.
 
 Main rules
 **********
@@ -1111,385 +1075,344 @@ Additional rules
 
 Rule A.1: Conditional Compilation
 =================================
-
 Severity
---------
-
-Required
+  Required
 
 Description
------------
-
-Do not conditionally compile function declarations in header files.  Do not
-conditionally compile structure declarations in header files.  You may
-conditionally exclude fields within structure definitions to avoid wasting
-memory when the feature they support is not enabled.
+  Do not conditionally compile function declarations in header files. Do not
+  conditionally compile structure declarations in header files. You may
+  conditionally exclude fields within structure definitions to avoid wasting
+  memory when the feature they support is not enabled.
 
 Rationale
----------
-
-Excluding declarations from the header based on compile-time options may prevent
-their documentation from being generated. Their absence also prevents use of
-``if (IS_ENABLED(CONFIG_FOO)) {}`` as an alternative to preprocessor
-conditionals when the code path should change based on the selected options.
+  Excluding declarations from the header based on compile-time options may prevent
+  their documentation from being generated. Their absence also prevents use of
+  ``if (IS_ENABLED(CONFIG_FOO)) {}`` as an alternative to preprocessor
+  conditionals when the code path should change based on the selected options.
 
 .. _coding_guideline_inclusive_language:
 
 Rule A.2: Inclusive Language
 ============================
-
 Severity
---------
-
-Required
+  Required
 
 Description
------------
+  Do not introduce new usage of offensive terms listed below. This rule applies
+  but is not limited to source code, comments, documentation, and branch names.
+  Replacement terms may vary by area or subsystem, but should aim to follow
+  updated industry standards when possible.
 
-Do not introduce new usage of offensive terms listed below. This rule applies
-but is not limited to source code, comments, documentation, and branch names.
-Replacement terms may vary by area or subsystem, but should aim to follow
-updated industry standards when possible.
+  Exceptions are allowed for maintaining existing implementations or adding new
+  implementations of industry standard specifications governed externally to the
+  Zephyr Project.
 
-Exceptions are allowed for maintaining existing implementations or adding new
-implementations of industry standard specifications governed externally to the
-Zephyr Project.
+  Existing usage is recommended to change as soon as updated industry standard
+  specifications become available or new terms are publicly announced by the
+  governing body, or immediately if no specifications apply.
 
-Existing usage is recommended to change as soon as updated industry standard
-specifications become available or new terms are publicly announced by the
-governing body, or immediately if no specifications apply.
+  .. list-table::
+     :header-rows: 1
 
-.. list-table::
-   :header-rows: 1
+     * - Offensive Terms
+       - Recommended Replacements
 
-   * - Offensive Terms
-     - Recommended Replacements
+     * - ``{master,leader} / slave``
+       - - ``{primary,main} / {secondary,replica}``
+         - ``{initiator,requester} / {target,responder}``
+         - ``{controller,host} / {device,worker,proxy,target}``
+         - ``director / performer``
+         - ``central / peripheral``
 
-   * - ``{master,leader} / slave``
-     - - ``{primary,main} / {secondary,replica}``
-       - ``{initiator,requester} / {target,responder}``
-       - ``{controller,host} / {device,worker,proxy,target}``
-       - ``director / performer``
-       - ``central / peripheral``
+     * - ``blacklist / whitelist``
+       - * ``denylist / allowlist``
+         * ``blocklist / allowlist``
+         * ``rejectlist / acceptlist``
 
-   * - ``blacklist / whitelist``
-     - * ``denylist / allowlist``
-       * ``blocklist / allowlist``
-       * ``rejectlist / acceptlist``
-
-   * - ``grandfather policy``
-     - * ``legacy``
-
-   * - ``sanity``
-     - * ``coherence``
-       * ``confidence``
+     * - ``grandfather policy``
+       - * ``legacy``
 
+     * - ``sanity``
+       - * ``coherence``
+         * ``confidence``
 
 Rationale
----------
-
-Offensive terms do not create an inclusive community environment and therefore
-violate the Zephyr Project `Code of Conduct`_. This coding rule was inspired by
-a similar rule in `Linux`_.
+  Offensive terms do not create an inclusive community environment and therefore
+  violate the Zephyr Project `Code of Conduct`_. This coding rule was inspired by
+  a similar rule in `Linux`_.
 
-.. _Code of Conduct: https://github.com/zephyrproject-rtos/zephyr/blob/main/CODE_OF_CONDUCT.md
-.. _Linux: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=49decddd39e5f6132ccd7d9fdc3d7c470b0061bb
+  .. _Code of Conduct: https://github.com/zephyrproject-rtos/zephyr/blob/main/CODE_OF_CONDUCT.md
+  .. _Linux: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=49decddd39e5f6132ccd7d9fdc3d7c470b0061bb
 
 Status
-------
-
-Related GitHub Issues and Pull Requests are tagged with the `Inclusive Language Label`_.
-
-.. list-table::
-   :header-rows: 1
-
-   * - Area
-     - Selected Replacements
-     - Status
-
-   * - :ref:`Bluetooth <bluetooth_api>`
-     - See `Bluetooth Appropriate Language Mapping Tables`_
-     -
-
-   * - CAN
-     - This `CAN in Automation Inclusive Language news post`_ has a list of general
-       recommendations. See `CAN in Automation Inclusive Language`_ for terms to
-       be used in specification document updates.
-     -
-
-   * - eSPI
-     - * ``master / slave`` => ``controller / target``
-     - Refer to `eSPI Specification`_ for new terminology
-
-   * - gPTP
-     - * ``master / slave`` => TBD
-     -
+  Related GitHub Issues and Pull Requests are tagged with the `Inclusive Language Label`_.
+
+  .. list-table::
+     :header-rows: 1
+
+     * - Area
+       - Selected Replacements
+       - Status
+
+     * - :ref:`Bluetooth <bluetooth_api>`
+       - See `Bluetooth Appropriate Language Mapping Tables`_
+       -
+
+     * - CAN
+       - This `CAN in Automation Inclusive Language news post`_ has a list of general
+         recommendations. See `CAN in Automation Inclusive Language`_ for terms to
+         be used in specification document updates.
+       -
+
+     * - eSPI
+       - * ``master / slave`` => ``controller / target``
+       - Refer to `eSPI Specification`_ for new terminology
+
+     * - gPTP
+       - * ``master / slave`` => TBD
+       -
+
+     * - :ref:`i2c_api`
+       - * ``master / slave`` => TBD
+       - NXP publishes the `I2C Specification`_ and has selected ``controller /
+         target`` as replacement terms, but the timing to publish an announcement
+         or new specification is TBD. Zephyr will update I2C when replacement
+         terminology is confirmed by a public announcement or updated
+         specification.
+
+         See :github:`Zephyr issue 27033 <27033>`.
+
+     * - :ref:`i2s_api`
+       - * ``master / slave`` => TBD
+       -
+
+     * - SMP/AMP
+       - * ``master / slave`` => TBD
+       -
+
+     * - :ref:`spi_api`
+       - * ``master / slave`` => ``controller / peripheral``
+         * ``MOSI / MISO / SS`` => ``SDO / SDI / CS``
+       - The Open Source Hardware Association has selected these replacement
+         terms. See `OSHWA Resolution to Redefine SPI Signal Names`_
+
+     * - :ref:`twister_script`
+       - * ``platform_whitelist`` => ``platform_allow``
+         * ``sanitycheck`` => ``twister``
+       -
+
+  .. _Inclusive Language Label: https://github.com/zephyrproject-rtos/zephyr/issues?q=label%3A%22Inclusive+Language%22
+  .. _I2C Specification: https://www.nxp.com/docs/en/user-guide/UM10204.pdf
+  .. _Bluetooth Appropriate Language Mapping Tables: https://specificationrefs.bluetooth.com/language-mapping/Appropriate_Language_Mapping_Table.pdf
+  .. _OSHWA Resolution to Redefine SPI Signal Names: https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names/
+  .. _CAN in Automation Inclusive Language news post: https://www.can-cia.org/news/archive/view/?tx_news_pi1%5Bnews%5D=699&tx_news_pi1%5Bday%5D=6&tx_news_pi1%5Bmonth%5D=12&tx_news_pi1%5Byear%5D=2020&cHash=784e79eb438141179386cf7c29ed9438
+  .. _CAN in Automation Inclusive Language: https://can-newsletter.org/canopen/categories/
+  .. _eSPI Specification: https://downloadmirror.intel.com/27055/327432%20espi_base_specification%20R1-5.pdf
 
-   * - :ref:`i2c_api`
-     - * ``master / slave`` => TBD
-     - NXP publishes the `I2C Specification`_ and has selected ``controller /
-       target`` as replacement terms, but the timing to publish an announcement
-       or new specification is TBD. Zephyr will update I2C when replacement
-       terminology is confirmed by a public announcement or updated
-       specification.
-
-       See :github:`Zephyr issue 27033 <27033>`.
-
-   * - :ref:`i2s_api`
-     - * ``master / slave`` => TBD
-     -
-
-   * - SMP/AMP
-     - * ``master / slave`` => TBD
-     -
-
-   * - :ref:`spi_api`
-     - * ``master / slave`` => ``controller / peripheral``
-       * ``MOSI / MISO / SS`` => ``SDO / SDI / CS``
-     - The Open Source Hardware Association has selected these replacement
-       terms. See `OSHWA Resolution to Redefine SPI Signal Names`_
-
-   * - :ref:`twister_script`
-     - * ``platform_whitelist`` => ``platform_allow``
-       * ``sanitycheck`` => ``twister``
-     -
-
-.. _Inclusive Language Label: https://github.com/zephyrproject-rtos/zephyr/issues?q=label%3A%22Inclusive+Language%22
-.. _I2C Specification: https://www.nxp.com/docs/en/user-guide/UM10204.pdf
-.. _Bluetooth Appropriate Language Mapping Tables: https://specificationrefs.bluetooth.com/language-mapping/Appropriate_Language_Mapping_Table.pdf
-.. _OSHWA Resolution to Redefine SPI Signal Names: https://www.oshwa.org/a-resolution-to-redefine-spi-signal-names/
-.. _CAN in Automation Inclusive Language news post: https://www.can-cia.org/news/archive/view/?tx_news_pi1%5Bnews%5D=699&tx_news_pi1%5Bday%5D=6&tx_news_pi1%5Bmonth%5D=12&tx_news_pi1%5Byear%5D=2020&cHash=784e79eb438141179386cf7c29ed9438
-.. _CAN in Automation Inclusive Language: https://can-newsletter.org/canopen/categories/
-.. _eSPI Specification: https://downloadmirror.intel.com/27055/327432%20espi_base_specification%20R1-5.pdf
 
+.. _coding_guideline_libc_usage_restrictions_in_zephyr_kernel:
 
 Rule A.3: Macro name collisions
 ===============================
-
 Severity
---------
-
-Required
+  Required
 
 Description
------------
-
-Macros with commonly used names such as  ``MIN``, ``MAX``, ``ARRAY_SIZE``, must
-not be modified or protected to avoid name collisions with other
-implementations. In particular, they must not be prefixed to place them in a
-Zephyr-specific namespace, re-defined using ``#undef``, or conditionally
-excluded from compilation using ``#ifndef``.  Instead, if a conflict arises with
-an existing definition originating from a :ref:`module <modules>`, the module's
-code itself needs to be modified (ideally upstream, alternatively via a change
-in Zephyr's own fork).
-This rule applies to Zephyr as a project in general, regardless of the time of
-introduction of the macro or its current name in the tree. If a macro name is
-commonly used in several other well-known open source projects then the
-implementation in Zephyr should use that name. While there is a subjective and
-non-measurable component to what "commonly used" means, the ultimate goal is
-to offer users familiar macros.
-Finally, this rule applies to inter-module name collisions as well: in that case
-both modules, prior to their inclusion, should be modified to use
-module-specific versions of the macro name that collides.
+  Macros with commonly used names such as ``MIN``, ``MAX``, ``ARRAY_SIZE``, must not be modified or
+  protected to avoid name collisions with other implementations. In particular, they must not be
+  prefixed to place them in a Zephyr-specific namespace, re-defined using ``#undef``, or
+  conditionally excluded from compilation using ``#ifndef``. Instead, if a conflict arises with an
+  existing definition originating from a :ref:`module <modules>`, the module's code itself needs to
+  be modified (ideally upstream, alternatively via a change in Zephyr's own fork).
+
+  This rule applies to Zephyr as a project in general, regardless of the time of introduction of the
+  macro or its current name in the tree. If a macro name is commonly used in several other well-known
+  open source projects then the implementation in Zephyr should use that name. While there is a
+  subjective and non-measurable component to what "commonly used" means, the ultimate goal is to offer
+  users familiar macros.
+
+  Finally, this rule applies to inter-module name collisions as well: in that case both modules, prior
+  to their inclusion, should be modified to use module-specific versions of the macro name that
+  collides.
 
 Rationale
----------
-
-Zephyr is an RTOS that comes with additional functionality and dependencies in
-the form of modules. Those modules are typically independent projects that may
-use macro names that can conflict with other modules or with Zephyr itself.
-Since, in the context of this documentation, Zephyr is considered the central or
-main project, it should implement the non-namespaced versions of the
-macros. Given that Zephyr uses a fork of the corresponding upstream for each
-module, it is always possible to patch the macro implementation in each module
-to avoid collisions.
-
-.. _coding_guideline_libc_usage_restrictions_in_zephyr_kernel:
+  Zephyr is an RTOS that comes with additional functionality and dependencies in the form of modules.
+  Those modules are typically independent projects that may use macro names that can conflict with
+  other modules or with Zephyr itself. Since, in the context of this documentation, Zephyr is
+  considered the central or main project, it should implement the non-namespaced versions of the
+  macros. Given that Zephyr uses a fork of the corresponding upstream for each module, it is always
+  possible to patch the macro implementation in each module to avoid collisions.
 
 Rule A.4: C Standard Library Usage Restrictions in Zephyr Kernel
 ================================================================
-
 Severity
---------
-
-Required
+  Required
 
 Description
------------
-
-The use of the C standard library functions and macros in the Zephyr kernel
-shall be limited to the following functions and macros from the ISO/IEC
-9899:2011 standard, also known as C11, and their extensions:
-
-.. csv-table:: List of allowed libc functions and macros in the Zephyr kernel
-   :header: Function,Source
-   :widths: auto
-
-   abort(),ISO/IEC 9899:2011
-   abs(),ISO/IEC 9899:2011
-   aligned_alloc(),ISO/IEC 9899:2011
-   assert(),ISO/IEC 9899:2011
-   atoi(),ISO/IEC 9899:2011
-   bsearch(),ISO/IEC 9899:2011
-   calloc(),ISO/IEC 9899:2011
-   exit(),ISO/IEC 9899:2011
-   fprintf(),ISO/IEC 9899:2011
-   fputc(),ISO/IEC 9899:2011
-   fputs(),ISO/IEC 9899:2011
-   free(),ISO/IEC 9899:2011
-   fwrite(),ISO/IEC 9899:2011
-   gmtime(),ISO/IEC 9899:2011
-   isalnum(),ISO/IEC 9899:2011
-   isalpha(),ISO/IEC 9899:2011
-   iscntrl(),ISO/IEC 9899:2011
-   isdigit(),ISO/IEC 9899:2011
-   isgraph(),ISO/IEC 9899:2011
-   isprint(),ISO/IEC 9899:2011
-   isspace(),ISO/IEC 9899:2011
-   isupper(),ISO/IEC 9899:2011
-   isxdigit(),ISO/IEC 9899:2011
-   labs(),ISO/IEC 9899:2011
-   llabs(),ISO/IEC 9899:2011
-   malloc(),ISO/IEC 9899:2011
-   memchr(),ISO/IEC 9899:2011
-   memcmp(),ISO/IEC 9899:2011
-   memcpy(),ISO/IEC 9899:2011
-   memmove(),ISO/IEC 9899:2011
-   memset(),ISO/IEC 9899:2011
-   perror(),ISO/IEC 9899:2011
-   printf(),ISO/IEC 9899:2011
-   putc(),ISO/IEC 9899:2011
-   putchar(),ISO/IEC 9899:2011
-   puts(),ISO/IEC 9899:2011
-   qsort(),ISO/IEC 9899:2011
-   rand(),ISO/IEC 9899:2011
-   realloc(),ISO/IEC 9899:2011
-   snprintf(),ISO/IEC 9899:2011
-   sprintf(),ISO/IEC 9899:2011
-   sqrt(),ISO/IEC 9899:2011
-   sqrtf(),ISO/IEC 9899:2011
-   srand(),ISO/IEC 9899:2011
-   strcat(),ISO/IEC 9899:2011
-   strchr(),ISO/IEC 9899:2011
-   strcmp(),ISO/IEC 9899:2011
-   strcpy(),ISO/IEC 9899:2011
-   strcspn(),ISO/IEC 9899:2011
-   strerror(),ISO/IEC 9899:2011
-   strlen(),ISO/IEC 9899:2011
-   strncat(),ISO/IEC 9899:2011
-   strncmp(),ISO/IEC 9899:2011
-   strncpy(),ISO/IEC 9899:2011
-   `strnlen()`_,POSIX.1-2008
-   strrchr(),ISO/IEC 9899:2011
-   strspn(),ISO/IEC 9899:2011
-   strstr(),ISO/IEC 9899:2011
-   strtol(),ISO/IEC 9899:2011
-   strtoll(),ISO/IEC 9899:2011
-   strtoul(),ISO/IEC 9899:2011
-   strtoull(),ISO/IEC 9899:2011
-   time(),ISO/IEC 9899:2011
-   tolower(),ISO/IEC 9899:2011
-   toupper(),ISO/IEC 9899:2011
-   vfprintf(),ISO/IEC 9899:2011
-   vprintf(),ISO/IEC 9899:2011
-   vsnprintf(),ISO/IEC 9899:2011
-   vsprintf(),ISO/IEC 9899:2011
-
-All of the functions listed above must be implemented by the
-:ref:`minimal libc <c_library_minimal>` to ensure that the Zephyr kernel can
-build with the minimal libc.
-
-In addition, any functions from the above list that are not part of the
-ISO/IEC 9899:2011 standard must be implemented by the
-:ref:`common libc <c_library_common>` to ensure their availability across
-multiple C standard libraries.
-
-Introducing new C standard library functions to the Zephyr kernel is allowed
-with justification given that the above requirements are satisfied.
-
-Note that the use of the functions listed above are subject to secure and safe
-coding practices and it should not be assumed that their use in the Zephyr
-kernel is unconditionally permitted by being listed in this rule.
-
-The "Zephyr kernel" in this context consists of the following components:
-
-* Kernel (:file:`kernel`)
-* OS Library (:file:`lib/os`)
-* Architecture Port (:file:`arch`)
-* Logging Subsystem (:file:`subsys/logging`)
+  The use of the C standard library functions and macros in the Zephyr kernel
+  shall be limited to the following functions and macros from the ISO/IEC
+  9899:2011 standard, also known as C11, and their extensions:
+
+  .. csv-table:: List of allowed libc functions and macros in the Zephyr kernel
+     :header: Function,Source
+     :widths: auto
+
+     abort(),ISO/IEC 9899:2011
+     abs(),ISO/IEC 9899:2011
+     aligned_alloc(),ISO/IEC 9899:2011
+     assert(),ISO/IEC 9899:2011
+     atoi(),ISO/IEC 9899:2011
+     bsearch(),ISO/IEC 9899:2011
+     calloc(),ISO/IEC 9899:2011
+     exit(),ISO/IEC 9899:2011
+     fprintf(),ISO/IEC 9899:2011
+     fputc(),ISO/IEC 9899:2011
+     fputs(),ISO/IEC 9899:2011
+     free(),ISO/IEC 9899:2011
+     fwrite(),ISO/IEC 9899:2011
+     gmtime(),ISO/IEC 9899:2011
+     isalnum(),ISO/IEC 9899:2011
+     isalpha(),ISO/IEC 9899:2011
+     iscntrl(),ISO/IEC 9899:2011
+     isdigit(),ISO/IEC 9899:2011
+     isgraph(),ISO/IEC 9899:2011
+     isprint(),ISO/IEC 9899:2011
+     isspace(),ISO/IEC 9899:2011
+     isupper(),ISO/IEC 9899:2011
+     isxdigit(),ISO/IEC 9899:2011
+     labs(),ISO/IEC 9899:2011
+     llabs(),ISO/IEC 9899:2011
+     malloc(),ISO/IEC 9899:2011
+     memchr(),ISO/IEC 9899:2011
+     memcmp(),ISO/IEC 9899:2011
+     memcpy(),ISO/IEC 9899:2011
+     memmove(),ISO/IEC 9899:2011
+     memset(),ISO/IEC 9899:2011
+     perror(),ISO/IEC 9899:2011
+     printf(),ISO/IEC 9899:2011
+     putc(),ISO/IEC 9899:2011
+     putchar(),ISO/IEC 9899:2011
+     puts(),ISO/IEC 9899:2011
+     qsort(),ISO/IEC 9899:2011
+     rand(),ISO/IEC 9899:2011
+     realloc(),ISO/IEC 9899:2011
+     snprintf(),ISO/IEC 9899:2011
+     sprintf(),ISO/IEC 9899:2011
+     sqrt(),ISO/IEC 9899:2011
+     sqrtf(),ISO/IEC 9899:2011
+     srand(),ISO/IEC 9899:2011
+     strcat(),ISO/IEC 9899:2011
+     strchr(),ISO/IEC 9899:2011
+     strcmp(),ISO/IEC 9899:2011
+     strcpy(),ISO/IEC 9899:2011
+     strcspn(),ISO/IEC 9899:2011
+     strerror(),ISO/IEC 9899:2011
+     strlen(),ISO/IEC 9899:2011
+     strncat(),ISO/IEC 9899:2011
+     strncmp(),ISO/IEC 9899:2011
+     strncpy(),ISO/IEC 9899:2011
+     `strnlen()`_,POSIX.1-2008
+     strrchr(),ISO/IEC 9899:2011
+     strspn(),ISO/IEC 9899:2011
+     strstr(),ISO/IEC 9899:2011
+     strtol(),ISO/IEC 9899:2011
+     strtoll(),ISO/IEC 9899:2011
+     strtoul(),ISO/IEC 9899:2011
+     strtoull(),ISO/IEC 9899:2011
+     time(),ISO/IEC 9899:2011
+     tolower(),ISO/IEC 9899:2011
+     toupper(),ISO/IEC 9899:2011
+     vfprintf(),ISO/IEC 9899:2011
+     vprintf(),ISO/IEC 9899:2011
+     vsnprintf(),ISO/IEC 9899:2011
+     vsprintf(),ISO/IEC 9899:2011
+
+  All of the functions listed above must be implemented by the
+  :ref:`minimal libc <c_library_minimal>` to ensure that the Zephyr kernel can
+  build with the minimal libc.
+
+  In addition, any functions from the above list that are not part of the
+  ISO/IEC 9899:2011 standard must be implemented by the
+  :ref:`common libc <c_library_common>` to ensure their availability across
+  multiple C standard libraries.
+
+  Introducing new C standard library functions to the Zephyr kernel is allowed
+  with justification given that the above requirements are satisfied.
+
+  Note that the use of the functions listed above are subject to secure and safe
+  coding practices and it should not be assumed that their use in the Zephyr
+  kernel is unconditionally permitted by being listed in this rule.
+
+  The "Zephyr kernel" in this context consists of the following components:
+
+  * Kernel (:file:`kernel`)
+  * OS Library (:file:`lib/os`)
+  * Architecture Port (:file:`arch`)
+  * Logging Subsystem (:file:`subsys/logging`)
 
 Rationale
----------
-
-Zephyr kernel must be able to build with the
-:ref:`minimal libc <c_library_minimal>`, a limited C standard library
-implementation that is part of the Zephyr RTOS and maintained by the Zephyr
-Project, to allow self-contained testing and verification of the kernel and
-core OS services.
+  Zephyr kernel must be able to build with the
+  :ref:`minimal libc <c_library_minimal>`, a limited C standard library
+  implementation that is part of the Zephyr RTOS and maintained by the Zephyr
+  Project, to allow self-contained testing and verification of the kernel and
+  core OS services.
 
-In order to ensure that the Zephyr kernel can build with the minimal libc, it
-is necessary to restrict the use of the C standard library functions and macros
-in the Zephyr kernel to the functions and macros that are available as part of
-the minimal libc.
+  In order to ensure that the Zephyr kernel can build with the minimal libc, it
+  is necessary to restrict the use of the C standard library functions and macros
+  in the Zephyr kernel to the functions and macros that are available as part of
+  the minimal libc.
 
 Rule A.5: C Standard Library Usage Restrictions in Zephyr Codebase
 ==================================================================
-
 Severity
---------
-
-Required
+  Required
 
 Description
------------
-
-The use of the C standard library functions and macros in the Zephyr codebase
-shall be limited to the functions, excluding the Annex K "Bounds-checking
-interfaces", from the ISO/IEC 9899:2011 standard, also known as C11, unless
-exempted by this rule.
-
-The "Zephyr codebase" in this context refers to all embedded source code files committed
-to the `main Zephyr repository`_, except the Zephyr kernel as defined by the
-:ref:`coding_guideline_libc_usage_restrictions_in_zephyr_kernel`.
-With embedded source code we refer to code which is meant to be executed in embedded
-targets, and therefore excludes host tooling, and code specific for the
-:ref:`native <boards_posix>` test targets.
-
-The following non-ISO 9899:2011, hereinafter referred to as non-standard,
-functions and macros are exempt from this rule and allowed to be used in the
-Zephyr codebase:
-
-.. csv-table:: List of allowed non-standard libc functions
-   :header: Function,Source
-   :widths: auto
-
-   `gmtime_r()`_,POSIX.1-2001
-   `strnlen()`_,POSIX.1-2008
-   `strtok_r()`_,POSIX.1-2001
-
-All non-standard functions and macros listed above must be implemented by the
-:ref:`common libc <c_library_common>` in order to make sure that these
-functions can be made available when using a C standard library that does not
-implement these functions.
-
-Adding a new non-standard function from common C standard libraries to the
-above list is allowed with justification, given that the above requirement is
-satisfied. However, when there exists a standard function that is functionally
-equivalent, the standard function shall be used.
+  The use of the C standard library functions and macros in the Zephyr codebase
+  shall be limited to the functions, excluding the Annex K "Bounds-checking
+  interfaces", from the ISO/IEC 9899:2011 standard, also known as C11, unless
+  exempted by this rule.
+
+  The "Zephyr codebase" in this context refers to all embedded source code files committed
+  to the `main Zephyr repository`_, except the Zephyr kernel as defined by the
+  :ref:`coding_guideline_libc_usage_restrictions_in_zephyr_kernel`.
+  With embedded source code we refer to code which is meant to be executed in embedded
+  targets, and therefore excludes host tooling, and code specific for the
+  :ref:`native <boards_posix>` test targets.
+
+  The following non-ISO 9899:2011, hereinafter referred to as non-standard,
+  functions and macros are exempt from this rule and allowed to be used in the
+  Zephyr codebase:
+
+  .. csv-table:: List of allowed non-standard libc functions
+     :header: Function,Source
+     :widths: auto
+
+     `gmtime_r()`_,POSIX.1-2001
+     `strnlen()`_,POSIX.1-2008
+     `strtok_r()`_,POSIX.1-2001
+
+  All non-standard functions and macros listed above must be implemented by the
+  :ref:`common libc <c_library_common>` in order to make sure that these
+  functions can be made available when using a C standard library that does not
+  implement these functions.
+
+  Adding a new non-standard function from common C standard libraries to the
+  above list is allowed with justification, given that the above requirement is
+  satisfied. However, when there exists a standard function that is functionally
+  equivalent, the standard function shall be used.
 
 Rationale
----------
-
-Some C standard libraries, such as Newlib and Picolibc, include additional
-functions and macros that are defined by the standards and de-facto standards
-that extend the ISO C standard (e.g. POSIX, Linux).
-
-The ISO/IEC 9899:2011 standard does not require C compiler toolchains to
-include the support for these non-standard functions, and therefore using
-these functions can lead to compatibility issues with the third-party
-toolchains that come with their own C standard libraries.
-
-.. _main Zephyr repository: https://github.com/zephyrproject-rtos/zephyr
-.. _gmtime_r(): https://pubs.opengroup.org/onlinepubs/9699919799/functions/gmtime_r.html
-.. _strnlen(): https://pubs.opengroup.org/onlinepubs/9699919799/functions/strlen.html
-.. _strtok_r(): https://pubs.opengroup.org/onlinepubs/9699919799/functions/strtok.html
+  Some C standard libraries, such as Newlib and Picolibc, include additional
+  functions and macros that are defined by the standards and de-facto standards
+  that extend the ISO C standard (e.g. POSIX, Linux).
+
+  The ISO/IEC 9899:2011 standard does not require C compiler toolchains to
+  include the support for these non-standard functions, and therefore using
+  these functions can lead to compatibility issues with the third-party
+  toolchains that come with their own C standard libraries.
+
+  .. _main Zephyr repository: https://github.com/zephyrproject-rtos/zephyr
+  .. _gmtime_r(): https://pubs.opengroup.org/onlinepubs/9699919799/functions/gmtime_r.html
+  .. _strnlen(): https://pubs.opengroup.org/onlinepubs/9699919799/functions/strlen.html
+  .. _strtok_r(): https://pubs.opengroup.org/onlinepubs/9699919799/functions/strtok.html
diff --git a/doc/contribute/contributor_expectations.rst b/doc/contribute/contributor_expectations.rst
index 8f88093582a..8c650a47268 100644
--- a/doc/contribute/contributor_expectations.rst
+++ b/doc/contribute/contributor_expectations.rst
@@ -87,26 +87,78 @@ Changes which require an RFC proposal include:
 Maintainers have the discretion to request that contributors create an RFC for
 PRs that are too large or complicated.
 
+.. _pr_requirements:
+
 PR Requirements
 ***************
 
 - Each commit in the PR must provide a commit message following the
   :ref:`commit-guidelines`.
 
+- No fixup or merge commits are allowed, see :ref:`Contribution workflow` for
+  more information.
+
 - The PR description must include a summary of the changes and their rationales.
 
 - All files in the PR must comply with :ref:`Licensing
   Requirements<licensing_requirements>`.
 
-- Follow the Zephyr :ref:`coding_style` and :ref:`coding_guidelines`.
+- The code must follow the Zephyr :ref:`coding_style` and :ref:`coding_guidelines`.
 
-- PRs must pass all CI checks. This is a requirement to merge the PR.
+- The PR must pass all CI checks, as described in :ref:`merge_criteria`.
   Contributors may mark a PR as draft and explicitly request reviewers to
   provide early feedback, even with failing CI checks.
 
-- When breaking a PR into multiple commits, each commit must build cleanly. The
-  CI system does not enforce this policy, so it is the PR author's
-  responsibility to verify.
+- Commits in a pull request should represent clear, logical units of change that are easy to review
+  and maintain bisectability. The following guidelines expand on this principle:
+
+  1. Distinct, Logical Units of Change
+
+     Each commit should correspond to a self-contained, meaningful change. For example, adding a
+     feature, fixing a bug, or refactoring existing code should be separate commits. Avoid mixing
+     different types of changes (e.g., feature implementation and unrelated refactoring) in the same
+     commit.
+
+  2. Retain Bisectability
+
+     Every commit in the pull request must build successfully and pass all relevant tests. This
+     ensures that git bisect can be used effectively to identify the specific commit that introduced
+     a bug or issue.
+
+  3. Squash Intermediary or Non-Final Development History
+
+     During development, commits may include intermediary changes (e.g., partial implementations,
+     temporary files, or debugging code). These should be squashed or rewritten before submitting the
+     pull request. Remove non-final artifacts, such as:
+
+     * Temporary renaming of files that are later renamed again.
+     * Code that was rewritten or significantly changed in later commits.
+
+  4. Ensure Clean History Before Submission
+
+     Use interactive rebasing (git rebase -i) to clean up the commit history before submitting the
+     pull request. This helps in:
+
+     * Squashing small, incomplete commits into a single cohesive commit.
+     * Ensuring that each commit remains bisectable.
+     * Maintaining proper attribution of authorship while improving clarity.
+
+  5. Renaming and Code Rewrites
+
+     If files or code are renamed or rewritten in later commits during development, squash or rewrite
+     earlier commits to reflect the final structure. This ensures that:
+
+     * The history remains clean and easy to follow.
+     * Bisectability is preserved by eliminating redundant renaming or partial rewrites.
+
+  6. Attribution of Authorship
+
+     While cleaning up the commit history, ensure that authorship attribution remains accurate.
+
+  7. Readable and Reviewable History
+
+     The final commit history should be easy to understand for future maintainers. Logical units of
+     change should be grouped into commits that tell a clear, coherent story of the work done.
 
 - When major new functionality is added, tests for the new functionality shall
   be added to the automated test suite. All API functions should have test cases
@@ -133,6 +185,13 @@ PR Requirements
 - Changes to APIs must increment the API version number according to the API
   version rules.
 
+- Documentation must be added and/or updated to reflect the changes in the code
+  introduced by the PR. The documentation changes must use the proper
+  terminology as present in the existing pages, and must be written in American
+  English. If you include images as part of the documentation, those must follow
+  the rules in :ref:`doc_images`. Please refer to :ref:`doc_guidelines` for
+  additional information.
+
 - PRs must also satisfy all :ref:`merge_criteria` before a member of the release
   engineering team merges the PR into the zephyr tree.
 
@@ -259,62 +318,3 @@ the steps below:
 .. _Architecture Project: https://github.com/zephyrproject-rtos/zephyr/projects/18
 
 .. _Architecture Working Group: https://github.com/zephyrproject-rtos/zephyr/wiki/Architecture-Working-Group
-
-
-.. _reviewer-expectations:
-
-Reviewer Expectations
-*********************
-
-- Be respectful when commenting on PRs. Refer to the Zephyr `Code of Conduct`_
-  for more details.
-
-- The Zephyr Project recognizes that reviewers and maintainers have limited
-  bandwidth. As a reviewer, prioritize review requests in the following order:
-
-    #. PRs related to items in the `Zephyr Release Plan`_ or those targeting
-       the next release during the stabilization period (after RC1).
-    #. PRs where the reviewer has requested blocking changes.
-    #. PRs assigned to the reviewer as the area maintainer.
-    #. All other PRs.
-
-- Reviewers shall strive to advance the PR to a mergeable state with their
-  feedback and engagement with the PR author.
-
-- Try to provide feedback on the entire PR in one shot. This provides the
-  contributor an opportunity to address all comments in the next PR update.
-
-- Partial reviews are permitted, but the reviewer must add a comment indicating
-  what portion of the PR they reviewed. Examples of useful partial reviews
-  include:
-
-  - Domain specific reviews (e.g. Devicetree).
-  - Code style changes that impact the readability of the PR.
-  - Reviewing commits separately when the requested changes cascade into the
-    later commits.
-
-- Avoid increasing scope of the PR by requesting new features, especially when
-  there is a corresponding :ref:`RFC <rfcs>` associated with the PR. Instead,
-  reviewers should add suggestions as a comment to the :ref:`RFC <rfcs>`. This
-  also encourages more collaboration as it is easier for multiple contributors
-  to work on a feature once the minimum implementation has merged.
-
-- When using the "Request Changes" option, mark trivial, non-functional,
-  requests as "Non-blocking" in the comment. Reviewers should approve PRs once
-  only non-blocking changes remain. The PR author has discretion as to whether
-  they address all non-blocking comments. PR authors should acknowledge every
-  review comment in some way, even if it's just with an emoticon.
-
-- Reviewers shall be *clear* and *concise* what changes they are requesting when the
-  "Request Changes" option is used. Requested changes shall be in the scope of
-  the PR in question and following the contribution and style guidelines of the
-  project.
-
-- Reviewers shall not close a PR due to technical or structural disagreement.
-  If requested changes cannot be resolved within the review process, the
-  :ref:`pr_technical_escalation` path shall be used for any potential resolution
-  path, which may include closing the PR.
-
-.. _Code of Conduct: https://github.com/zephyrproject-rtos/zephyr/blob/main/CODE_OF_CONDUCT.md
-
-.. _Zephyr Release Plan: https://github.com/orgs/zephyrproject-rtos/projects/13
diff --git a/doc/contribute/documentation/generation.rst b/doc/contribute/documentation/generation.rst
index 8c567533323..cad9201b113 100644
--- a/doc/contribute/documentation/generation.rst
+++ b/doc/contribute/documentation/generation.rst
@@ -188,9 +188,9 @@ folder, here are the commands to generate the html content locally:
 .. code-block:: console
 
    # On Linux/macOS
-   cd ~/zephyr/doc
+   cd ~/zephyrproject/zephyr/doc
    # On Windows
-   cd %userprofile%\zephyr\doc
+   cd %userprofile%\zephyrproject\zephyr\doc
 
    # Use cmake to configure a Ninja-based build system:
    cmake -GNinja -B_build .
@@ -234,7 +234,7 @@ build the documentation directly from there:
 
 .. code-block:: console
 
-   cd ~/zephyr/doc
+   cd ~/zephyrproject/zephyr/doc
 
    # To generate HTML output
    make html
@@ -253,11 +253,19 @@ To enable this mode, set the following option when invoking cmake::
 
    -DDT_TURBO_MODE=1
 
-or invoke make with the following target::
+Another step that typically takes a long time is the generation of the list of
+supported features for each board. This can be disabled by setting the following
+option when invoking cmake::
 
-   cd ~/zephyr/doc
+   -DHW_FEATURES_TURBO_MODE=1
 
-   # To generate HTML output without detailed Kconfig
+Invoking :command:`make` with the following target will build the documentation
+without either of the aforementioned features::
+
+   cd ~/zephyrproject/zephyr/doc
+
+   # To generate HTML output without detailed Devicetree bindings documentation
+   # and supported features index
    make html-fast
 
 Viewing generated documentation locally
diff --git a/doc/contribute/documentation/guidelines.rst b/doc/contribute/documentation/guidelines.rst
index 621c779a6d0..6c6b37a12f9 100644
--- a/doc/contribute/documentation/guidelines.rst
+++ b/doc/contribute/documentation/guidelines.rst
@@ -700,6 +700,8 @@ Cross-referencing C documentation
 Visual Elements
 ***************
 
+.. _doc_images:
+
 Images
 ======
 
@@ -881,6 +883,21 @@ Application build commands
 
       If set, additional arguments to the flash invocation.
 
+   .. rst:directive:option:: debug-args
+      :type: string
+
+      If set, additional arguments to the debug invocation.
+
+   .. rst:directive:option:: debugserver-args
+      :type: string
+
+      If set, additional arguments to the debugserver invocation.
+
+   .. rst:directive:option:: attach-args
+      :type: string
+
+      If set, additional arguments to the attach invocation.
+
    .. rst:directive:option:: snippets
       :type: string
 
@@ -928,15 +945,7 @@ Cross-referencing files in the Zephyr tree
 ==========================================
 
 Special roles are available to reference files in the Zephyr tree. For example, referencing this
-very file can be done using the :rst:role:`zephyr_file` role, like this::
-
-   Check out :zephyr_file:`doc/contribute/documentation/guidelines.rst` for more information.
-
-This would render as:
-
-   Check out :zephyr_file:`doc/contribute/documentation/guidelines.rst` for more information.
-
-You may use the :rst:role:`zephyr_raw` role instead if you want to reference the "raw" content.
+very file can be done using the :rst:role:`zephyr_file` role.
 
 .. rst:role:: zephyr_file
 
@@ -948,6 +957,27 @@ You may use the :rst:role:`zephyr_raw` role instead if you want to reference the
 
       Check out :zephyr_file:`doc/contribute/documentation/guidelines.rst` for more information.
 
+   You can reference specific lines or line ranges in a file by appending :samp:`#L{line_number}` or
+   :samp:`#L{start_line}-L{end_line}` to the file path::
+
+      See :zephyr_file:`doc/contribute/documentation/guidelines.rst#L3` for the main heading of
+      this document.
+
+   Will render as:
+
+      See :zephyr_file:`doc/contribute/documentation/guidelines.rst#L3` for the main heading of
+      this document.
+
+   The role automatically verifies that the referenced file exists in the Zephyr tree and will
+   generate a warning during documentation build if the file is not found.
+
+   .. note::
+
+      Use the line references sparingly as keeping them accurate over time can be challenging as the
+      content of the linked file is subject to change.
+
+   You may use the :rst:role:`zephyr_raw` role instead if you want to reference the "raw" content.
+
 .. rst:role:: zephyr_raw
 
    This role is used to reference the raw content of a file in the Zephyr tree. For example::
@@ -968,6 +998,7 @@ You may use the :rst:role:`zephyr_raw` role instead if you want to reference the
 
          Check out :module_file:`hal_stm32:CMakeLists.txt` for more information.
 
+   Similar to :rst:role:`zephyr_file`, you can reference specific lines or line ranges in a file.
 
 Cross-referencing GitHub issues and pull requests
 =================================================
@@ -1235,6 +1266,35 @@ Boards
    This directive is used to generate a catalog of Zephyr-supported boards that can be used to
    quickly browse the list of all supported boards and filter them according to various criteria.
 
+.. rst:directive:: .. zephyr:board-supported-hw::
+
+   This directive is used to show supported hardware features for all the targets of the board
+   documented in the current page. The tables are automatically generated based on the board's
+   Devicetree.
+
+   The directive must be used in a document that also contains a :rst:dir:`zephyr:board` directive,
+   as it relies on the board information to generate the table.
+
+   .. note::
+
+      This directive requires that the documentation is built with hardware features generation enabled
+      (``zephyr_generate_hw_features`` config option set to ``True``). If disabled, a warning message
+      will be shown instead of the hardware features tables.
+
+.. rst:directive:: .. zephyr:board-supported-runners::
+
+   This directive is used to show the supported runners for the board documented in the current
+   page, including which runner is the default for flashing and debugging.
+
+   The directive must be used in a document that also contains a :rst:dir:`zephyr:board` directive,
+   as it relies on the board information to generate the table.
+
+   .. note::
+
+      Similar to :rst:dir:`zephyr:board-supported-hw`, this directive requires hardware features
+      generation to be enabled (``zephyr_generate_hw_features`` config option set to ``True``) to
+      produce a complete table. If disabled, a warning message will be shown instead of the runners
+      tables.
 
 References
 **********
diff --git a/doc/contribute/guidelines.rst b/doc/contribute/guidelines.rst
index af7dd7ed8c2..e02db855e5d 100644
--- a/doc/contribute/guidelines.rst
+++ b/doc/contribute/guidelines.rst
@@ -12,6 +12,34 @@ This document explains how to participate in project conversations, log bugs
 and enhancement requests, and submit patches to the project so your patch will
 be accepted quickly in the codebase.
 
+
+Prerequisites
+*************
+
+.. _Zephyr Project website: https://zephyrproject.org
+
+As a contributor, you'll want to be familiar with the Zephyr project, how to
+configure, install, and use it as explained in the `Zephyr Project website`_
+and how to set up your development environment as introduced in the Zephyr
+:ref:`getting_started`.
+
+You should be familiar with common developer tools such as Git and CMake, and
+platforms such as GitHub.
+
+If you haven't already done so, you'll need to create a (free) GitHub account
+on https://github.com and have Git tools available on your development system.
+
+.. note::
+   The Zephyr development workflow supports all 3 major operating systems
+   (Linux, macOS, and Windows) but some of the tools used in the sections below
+   are only available on Linux and macOS. On Windows, instead of running these
+   tools yourself, you will need to rely on the Continuous Integration (CI)
+   service using Github Actions, which runs automatically on GitHub when you submit
+   your Pull Request (PR).  You can see any failure results in the workflow
+   details link near the end of the PR conversation list. See
+   `Continuous Integration`_ for more information
+
+
 .. _licensing_requirements:
 
 Licensing
@@ -76,9 +104,14 @@ this contributing and review process for imported components.
 Copyrights Notices
 *******************
 
-Please follow this `Community Best Practice`_ for Copyright Notices from the
-Linux Foundation.
+The Zephyr Project follows the `Community Best Practice`_ for Copyright Notices from the Linux
+Foundation.
+
+We recommend using the following copyright notice:
 
+.. code-block:: C
+
+    Copyright The Zephyr Project Contributors
 
 .. _Community Best Practice:
    https://www.linuxfoundation.org/blog/copyright-notices-in-open-source-software-projects/
@@ -156,54 +189,6 @@ Additional requirements:
 - If you are altering an existing commit created by someone else, you must add
   your Signed-off-by: line without removing the existing one.
 
-- If you forget to add the Signed-off-by: line, you can add it to your previous
-  commit by running ``git commit --amend -s``.
-
-- If you've pushed your changes to GitHub already you'll need to force push
-  your branch after this with ``git push -f``.
-
-Notes
-=====
-
-Any contributions made as part of submitted pull requests are considered free
-for the Project to use. Developers are permitted to cherry-pick patches that
-are included in pull requests submitted by other contributors. It is expected
-that
-
-* the content of the patches will not be substantially modified,
-* the cherry-picked commits or portions of a commit shall preserve the original
-  sign-off messages and the author identity.
-
-:ref:`modifying_contributions` describes additional recommended policies
-around working with contributions submitted by other developers.
-
-
-Prerequisites
-*************
-
-.. _Zephyr Project website: https://zephyrproject.org
-
-As a contributor, you'll want to be familiar with the Zephyr project, how to
-configure, install, and use it as explained in the `Zephyr Project website`_
-and how to set up your development environment as introduced in the Zephyr
-:ref:`getting_started`.
-
-You should be familiar with common developer tools such as Git and CMake, and
-platforms such as GitHub.
-
-If you haven't already done so, you'll need to create a (free) GitHub account
-on https://github.com and have Git tools available on your development system.
-
-.. note::
-   The Zephyr development workflow supports all 3 major operating systems
-   (Linux, macOS, and Windows) but some of the tools used in the sections below
-   are only available on Linux and macOS. On Windows, instead of running these
-   tools yourself, you will need to rely on the Continuous Integration (CI)
-   service using Github Actions, which runs automatically on GitHub when you submit
-   your Pull Request (PR).  You can see any failure results in the workflow
-   details link near the end of the PR conversation list. See
-   `Continuous Integration`_ for more information
-
 .. _source_tree_v2:
 
 Source Tree Structure
@@ -390,11 +375,6 @@ this:
 You need to change text in square brackets (``[like this]``) above to
 fit your commit.
 
-Examples and more details follow.
-
-Example
--------
-
 Here is an example of a good commit message.
 
 .. code-block:: none
@@ -531,98 +511,6 @@ reference manuals, etc.
 
    Link: https://github.com/zephyrproject-rtos/zephyr/issues/<issue number>
 
-.. _coding_style:
-
-Coding Style
-============
-
-.. _Linux kernel coding style:
-   https://kernel.org/doc/html/latest/process/coding-style.html
-
-In general, follow the `Linux kernel coding style`_, with the following
-exceptions:
-
-* The line length is 100 columns or fewer. In the documentation, longer lines
-  for URL references are an allowed exception.
-* Add braces to every ``if``, ``else``, ``do``, ``while``, ``for`` and
-  ``switch`` body, even for single-line code blocks.
-* Use spaces instead of tabs to align comments after declarations, as needed.
-* Use C89-style single line comments, ``/*  */``. The C99-style single line
-  comment, ``//``, is not allowed.
-* Use ``/**  */`` for doxygen comments that need to appear in the documentation.
-* Avoid using binary literals (constants starting with ``0b``).
-* Avoid using non-ASCII symbols in code, unless it significantly improves
-  clarity, avoid emojis in any case.
-
-Use these coding guidelines to ensure that your development complies with the
-project's style and naming conventions.
-
-The Linux kernel GPL-licensed tool ``checkpatch`` is used to check
-coding style conformity.
-
-.. note::
-   checkpatch does not currently run on Windows.
-
-Checkpatch is available in the scripts directory. To invoke it when committing
-code, make the file *$ZEPHYR_BASE/.git/hooks/pre-commit* executable and edit
-it to contain:
-
-.. code-block:: bash
-
-    #!/bin/sh
-    set -e exec
-    exec git diff --cached | ${ZEPHYR_BASE}/scripts/checkpatch.pl -
-
-Instead of running checkpatch at each commit, you may prefer to run it only
-before pushing on zephyr repo. To do this, make the file
-*$ZEPHYR_BASE/.git/hooks/pre-push* executable and edit it to contain:
-
-.. code-block:: bash
-
-    #!/bin/sh
-    remote="$1"
-    url="$2"
-
-    z40=0000000000000000000000000000000000000000
-
-    echo "Run push hook"
-
-    while read local_ref local_sha remote_ref remote_sha
-    do
-        args="$remote $url $local_ref $local_sha $remote_ref $remote_sha"
-        exec ${ZEPHYR_BASE}/scripts/series-push-hook.sh $args
-    done
-
-    exit 0
-
-If you want to override checkpatch verdict and push you branch despite reported
-issues, you can add option --no-verify to the git push command.
-
-A more complete alternative to this is using :ref:`check_compliance_py` script.
-
-clang-format
-------------
-
-The `clang-format tool <https://clang.llvm.org/docs/ClangFormat.html>`_ can
-be helpful to quickly reformat large amounts of new source code to our
-`Coding Style`_ standards together with the ``.clang-format`` configuration file
-provided in the repository. ``clang-format`` is well integrated into most
-editors, but you can also run it manually like this:
-
-.. code-block:: bash
-
-   clang-format -i my_source_file.c
-
-``clang-format`` is part of LLVM, which can be downloaded from the project
-`releases page <https://github.com/llvm/llvm-project/releases>`_. Note that if
-you are a Linux user, ``clang-format`` will likely be available as a package in
-your distribution repositories.
-
-When there are differences between the `Coding Style`_ guidelines and the
-formatting generated by code formatting tools, the `Coding Style`_ guidelines
-take precedence. If there is ambiguity between formatting tools and the
-guidelines, maintainers may decide which style should be adopted.
-
 .. _Continuous Integration:
 
 Continuous Integration (CI)
@@ -678,12 +566,19 @@ before opening a new Pull Request:
 
    ./scripts/ci/check_compliance.py -c upstream/main..
 
+.. note::
+   On Windows if the .pl extension has not yet been associated with an
+   application, then the first time a .pl file is run without specifying an
+   interpreter, Windows will ask what application will open Perl files.
+   Set the default app to Strawberry Perl. By default the executable is
+   installed at ``C:\Strawberry\perl\bin\perl.exe``.
+
 twister
 -------
 
 .. note::
    twister is only fully supported on Linux; on Windows and MacOS the execution
-   of tests is not supported, only building.
+   of tests is not supported on all target devices.
 
 If you think your change may break some test, you can submit your PR as a draft
 and let the project CI automatically run the :ref:`twister_script` for you.
@@ -854,13 +749,6 @@ workflow here:
    review.  Email will be sent as review comments are made, or you can check
    on your pull request at https://github.com/zephyrproject-rtos/zephyr/pulls.
 
-   .. note:: As more commits are merged upstream, the GitHub PR page will show
-      a ``This branch is out-of-date with the base branch`` message and a
-      ``Update branch`` button on the PR page. That message should be ignored,
-      as the commits will be rebased as part of merging anyway, and triggering
-      a branch update from the GitHub UI will cause the PR approvals to be
-      dropped.
-
 #. While you're waiting for your pull request to be accepted and merged, you
    can create another branch to work on another issue. (Be sure to make your
    new branch off of ``main`` and not the previous branch.)::
@@ -953,30 +841,6 @@ attention needed and it will be ready for merge sooner than later:
    sure you click the "Re-request review" button on the GitHub UI to notify
    those who asked for the changes
 
-
-Submitting Proposals
-====================
-
-You can request a new feature or submit a proposal by submitting an issue to
-our GitHub Repository.
-If you would like to implement a new feature, please submit an issue with a
-proposal (RFC) for your work first, to be sure that we can use it. Please
-consider what kind of change it is:
-
-* For a Major Feature, first open an issue and outline your proposal so that it
-  can be discussed. This will also allow us to better coordinate our efforts,
-  prevent duplication of work, and help you to craft the change so that it is
-  successfully accepted into the project. Providing the following information
-  will increase the chances of your issue being dealt with quickly:
-
-  * Overview of the Proposal
-  * Motivation for or Use Case
-  * Design Details
-  * Alternatives
-  * Test Strategy
-
-* Small Features can be crafted and directly submitted as a Pull Request.
-
 Identifying Contribution Origin
 ===============================
 
diff --git a/doc/contribute/index.rst b/doc/contribute/index.rst
index 19f872226a5..a6c2998a818 100644
--- a/doc/contribute/index.rst
+++ b/doc/contribute/index.rst
@@ -15,9 +15,13 @@ General Guidelines
    :hidden:
 
    guidelines.rst
+   contributor_expectations.rst
+   reviewer_expectations.rst
    coding_guidelines/index.rst
+   style/index.rst
    proposals_and_rfcs.rst
-   contributor_expectations.rst
+   modifying_contributions.rst
+
 
 :ref:`contribute_guidelines`
    Learn about the overall process and guidelines for contributing to the Zephyr project.
@@ -30,17 +34,26 @@ General Guidelines
    This document is another mandatory read that describes the expected behavior of *all*
    contributors to the project.
 
+:ref:`reviewer-expectations`
+   This document is another mandatory read that describes the expected behavior when revieweing
+   contributions to the project.
+
 :ref:`coding_guidelines`
    Code contributions are expected to follow a set of coding guidelines to ensure consistency and
    readability across the code base.
 
-   This page describes these guidelines and introduces important considerations regarding the use of
-   :ref:`inclusive language <coding_guideline_inclusive_language>`.
+:ref:`coding_style`
+   Code contributions are expected to follow a set of style guidelines to ensure consistency and
+   readability across the code base.
 
 :ref:`rfcs`
    Learn when and how to submit RFCs (Request for Comments) for new features and changes to the
    project.
 
+:ref:`modifying_contributions`
+   Guidelines for modifying contributions made by other developers and how to deal with stale pull
+   requests.
+
 Documentation
 =============
 
@@ -88,16 +101,6 @@ Dealing with external components
    in binary form, this page describes the process and guidelines for :ref:`contributing binary
    blobs <blobs-process>` to the project.
 
-Zephyr Contributor Badge
-========================
-
-When your first contribution to the Zephyr project gets merged, you'll become eligible to claim your
-Zephyr Contributor Badge. This digital badge can be displayed on your website, blog, social media
-profile, etc. It will allow you to showcase your involvement in the Zephyr project and help raise
-its awareness.
-
-You may apply for your Contributor Badge by filling out the `Zephyr Contributor Badge form`_.
-
 Need help along the way?
 ========================
 
@@ -107,4 +110,3 @@ You may join our Discord_ channel or use the `Developer Mailing List`_.
 
 .. _Discord: https://chat.zephyrproject.org
 .. _Developer Mailing List: https://lists.zephyrproject.org/g/devel
-.. _Zephyr Contributor Badge form: https://forms.gle/oCw9iAPLhUsHTapc8
diff --git a/doc/project/modifying_contributions.rst b/doc/contribute/modifying_contributions.rst
similarity index 100%
rename from doc/project/modifying_contributions.rst
rename to doc/contribute/modifying_contributions.rst
diff --git a/doc/contribute/proposals_and_rfcs.rst b/doc/contribute/proposals_and_rfcs.rst
index 8b76b44a096..d87647e0744 100644
--- a/doc/contribute/proposals_and_rfcs.rst
+++ b/doc/contribute/proposals_and_rfcs.rst
@@ -33,8 +33,22 @@ feature as it is being designed, and incorporate important constraints into the
 design while it's easier to change, before the design has been fully
 implemented.
 
-Some changes do not require an RFC:
+For a Major Feature, first open an issue and outline your proposal so that it
+can be discussed. This will also allow us to better coordinate our efforts,
+prevent duplication of work, and help you to craft the change so that it is
+successfully accepted into the project. Providing the following information
+will increase the chances of your issue being dealt with quickly:
 
+  * Overview of the Proposal
+  * Motivation for or Use Case
+  * Design Details
+  * Alternatives
+  * Test Strategy
+
+Some changes or contributions do not require an RFC, the rationale and details
+of the changes should however be part of the pull-request:
+
+- Small enhancements and modifications to existing and established subsystems.
 - Rephrasing, reorganizing or refactoring
 - Addition or removal of warnings
 - Addition of new boards, SoCs or drivers to existing subsystems
diff --git a/doc/contribute/reviewer_expectations.rst b/doc/contribute/reviewer_expectations.rst
new file mode 100644
index 00000000000..b22ea7b9ea7
--- /dev/null
+++ b/doc/contribute/reviewer_expectations.rst
@@ -0,0 +1,74 @@
+.. _reviewer-expectations:
+
+Reviewer Expectations
+#####################
+
+- Be respectful when commenting on PRs. Refer to the Zephyr `Code of Conduct`_
+  for more details.
+
+- The Zephyr Project recognizes that reviewers and maintainers have limited
+  bandwidth. As a reviewer, prioritize review requests in the following order:
+
+    #. PRs related to items in the `Zephyr Release Plan`_ or those targeting
+       the next release during the stabilization period (after RC1).
+    #. PRs where the reviewer has requested blocking changes.
+    #. PRs assigned to the reviewer as the area maintainer.
+    #. All other PRs.
+
+- Reviewers shall strive to advance the PR to a mergeable state with their
+  feedback and engagement with the PR author.
+
+- Try to provide feedback on the entire PR in one shot. This provides the
+  contributor an opportunity to address all comments in the next PR update.
+
+- Partial reviews are permitted, but the reviewer must add a comment indicating
+  what portion of the PR they reviewed. Examples of useful partial reviews
+  include:
+
+  - Domain specific reviews (e.g. Devicetree).
+  - Code style changes that impact the readability of the PR.
+  - Reviewing commits separately when the requested changes cascade into the
+    later commits.
+
+- Avoid increasing scope of the PR by requesting new features, especially when
+  there is a corresponding :ref:`RFC <rfcs>` associated with the PR. Instead,
+  reviewers should add suggestions as a comment to the :ref:`RFC <rfcs>`. This
+  also encourages more collaboration as it is easier for multiple contributors
+  to work on a feature once the minimum implementation has merged.
+
+- When using the "Request Changes" option, mark trivial, non-functional,
+  requests as "Non-blocking" in the comment. Reviewers should approve PRs once
+  only non-blocking changes remain. The PR author has discretion as to whether
+  they address all non-blocking comments. PR authors should acknowledge every
+  review comment in some way, even if it's just with an emoticon.
+
+- Style changes that the reviewer disagrees with but that are not documented as
+  part of the project can be pointed out as non-blocking, but cannot constitute
+  a reason for a request for changes. The reviewer can optionally correct any
+  potential inconsistencies in the tree, document the new guidelines or rules,
+  and then enforce them as part of the review.
+
+- Whenever requesting style related changes, reviewers should be able to point
+  out the corresponding guideline, rule or rationale in the project's
+  documentation.  This does not apply to certain types of requests for changes,
+  notably those specific to the changes being submitted (e.g. the use of a
+  particular data structure or the choice of locking primitives).
+
+- Reviewers shall be *clear* about what changes they are requesting when the
+  "Request Changes" option is used. Requested changes shall be in the scope of
+  the PR in question and following the contribution and style guidelines of the
+  project. Furthermore, reviewers must be able to point back to the exact issues
+  in the PR that triggered a request for changes.
+
+- Reviewers should not request changes for issues which are automatically
+  caught by CI, as this causes the pull request to remain blocked even after CI
+  failures have been addressed and may unnecessarily delay it from being merged.
+
+- Reviewers shall not close a PR due to technical or structural disagreement.
+  If requested changes cannot be resolved within the review process, the
+  :ref:`pr_technical_escalation` path shall be used for any potential resolution
+  path, which may include closing the PR.
+
+.. _Code of Conduct: https://github.com/zephyrproject-rtos/zephyr/blob/main/CODE_OF_CONDUCT.md
+
+.. _Zephyr Release Plan: https://github.com/orgs/zephyrproject-rtos/projects/13
diff --git a/doc/contribute/style/cmake.rst b/doc/contribute/style/cmake.rst
new file mode 100644
index 00000000000..0fff4273416
--- /dev/null
+++ b/doc/contribute/style/cmake.rst
@@ -0,0 +1,139 @@
+:orphan:
+
+.. _cmake-style:
+
+CMake Style Guidelines
+######################
+
+General Formatting
+******************
+
+- **Indentation**: Use **2 spaces** for indentation. Avoid tabs to ensure
+  consistency across different environments.
+- **Line Length**: Limit line length to **100 characters** where possible.
+- **Empty Lines**: Use empty lines to separate logically distinct sections
+  within a CMake file.
+- **No Space Before Opening Brackets**: Do not add a space between a command
+  and the opening parenthesis.
+  Use ``if(...)`` instead of ``if (...)``.
+
+  .. code-block:: cmake
+
+     # Good:
+     if(ENABLE_TESTS)
+       add_subdirectory(tests)
+     endif()
+
+     # Bad:
+     if (ENABLE_TESTS)
+       add_subdirectory(tests)
+     endif()
+
+Commands and Syntax
+*******************
+
+- **Lowercase Commands**: Always use **lowercase** CMake commands (e.g.,
+  ``add_executable``, ``find_package``). This improves readability and
+  consistency.
+
+  .. code-block:: cmake
+
+     # Good:
+     add_library(my_lib STATIC src/my_lib.cpp)
+
+     # Bad:
+     ADD_LIBRARY(my_lib STATIC src/my_lib.cpp)
+
+- **One File Argument per Line**: Break the file arguments across multiple
+  lines to make it easier to scan and identify each source file or item.
+
+  .. code-block:: cmake
+
+     # Good:
+     target_sources(my_target PRIVATE
+       src/file1.cpp
+       src/file2.cpp
+     )
+
+      # Bad:
+     target_sources(my_target PRIVATE src/file1.cpp src/file2.cpp)
+
+Variable Naming
+***************
+
+- **Use Uppercase for Cache Variables or variables shared across CMake files**:
+  When defining cache variables using ``option`` or ``set(... CACHE ...)``, use
+  **UPPERCASE names**.
+
+  .. code-block:: cmake
+
+     option(ENABLE_TESTS "Enable test suite" ON)
+     set(CMAKE_CXX_STANDARD 17 CACHE STRING "C++ standard version")
+
+- **Use Lowercase for Local Variables**: For local variables within CMake
+  files, use **lowercase** or **snake_case**.
+
+  .. code-block:: cmake
+
+     set(output_dir "${CMAKE_BINARY_DIR}/output")
+
+- **Consistent Prefixing**: Use consistent prefixes for variables to avoid name
+  conflicts, especially in large projects.
+
+  .. code-block:: cmake
+
+     set(MYPROJECT_SRC_DIR "${CMAKE_SOURCE_DIR}/src")
+
+Quoting
+*******
+
+- **Quote Strings and Variables**: Always quote string literals and variables
+  to prevent unintended behavior, especially when dealing with paths or
+  arguments that may contain spaces.
+
+  .. code-block:: cmake
+
+     # Good:
+     set(my_path "${CMAKE_SOURCE_DIR}/include")
+
+     # Bad:
+     set(my_path ${CMAKE_SOURCE_DIR}/include)
+
+- **Do Not Quote Boolean Values**: For boolean values (``ON``, ``OFF``,
+  ``TRUE``, ``FALSE``), avoid quoting them.
+
+  .. code-block:: cmake
+
+     option(BUILD_SHARED_LIBS "Build shared libraries" OFF)
+
+Avoid Hardcoding Paths
+**********************
+
+- Use CMake variables (``CMAKE_SOURCE_DIR``, ``CMAKE_BINARY_DIR``,
+  ``CMAKE_CURRENT_SOURCE_DIR``) instead of hardcoding paths.
+
+  .. code-block:: cmake
+
+     set(output_dir "${CMAKE_BINARY_DIR}/bin")
+
+Conditional Logic
+*****************
+
+- Use ``if``, ``elseif``, and ``else`` with proper indentation, and close with
+  ``endif()``.
+
+  .. code-block:: cmake
+
+     if(ENABLE_TESTS)
+       add_subdirectory(tests)
+     endif()
+
+Documentation
+*************
+
+- Use comments to document complex logic in the CMake files.
+
+  .. code-block:: cmake
+
+     # Find LlvmLld components required for building with llvm
+     find_package(LlvmLld 14.0.0 REQUIRED)
diff --git a/doc/contribute/style/code.rst b/doc/contribute/style/code.rst
new file mode 100644
index 00000000000..59a363ee509
--- /dev/null
+++ b/doc/contribute/style/code.rst
@@ -0,0 +1,38 @@
+.. _general_code_style:
+
+C Code and General Style Guidelines
+###################################
+
+Coding style is enforced on any new or modified code, but contributors are
+not expected to correct the style on existing code that they are not
+modifying.
+
+For style aspects where the guidelines don't offer explicit guidance or
+permit multiple valid ways to express something, contributors should follow
+the style of existing code in the tree, with higher importance given to
+"nearby" code (first look at the function, then the same file, then
+subsystem, etc).
+
+In general, follow the `Linux kernel coding style`_, with the following
+exceptions and clarifications:
+
+* Use `snake case`_ for code and variables.
+* The line length is 100 columns or fewer. In the documentation, longer lines
+  for URL references are an allowed exception.
+* Add braces to every ``if``, ``else``, ``do``, ``while``, ``for`` and
+  ``switch`` body, even for single-line code blocks.
+* Use spaces instead of tabs to align comments after declarations, as needed.
+* Use C89-style single line comments, ``/*  */``. The C99-style single line
+  comment, ``//``, is not allowed.
+* Use ``/**  */`` for doxygen comments that need to appear in the documentation.
+* Avoid using binary literals (constants starting with ``0b``).
+* Avoid using non-ASCII symbols in code, unless it significantly improves
+  clarity, avoid emojis in any case.
+* Use proper capitalization of nouns in code comments (e.g. ``UART`` and not
+  ``uart``, ``CMake`` and not ``cmake``).
+
+.. _Linux kernel coding style:
+   https://kernel.org/doc/html/latest/process/coding-style.html
+
+.. _snake case:
+   https://en.wikipedia.org/wiki/Snake_case
diff --git a/doc/contribute/style/devicetree.rst b/doc/contribute/style/devicetree.rst
new file mode 100644
index 00000000000..9578a750f7a
--- /dev/null
+++ b/doc/contribute/style/devicetree.rst
@@ -0,0 +1,19 @@
+.. _devicetree_style:
+
+Devicetree Style Guidelines
+###########################
+
+  * Indent with tabs.
+  * Follow the Devicetree specification conventions and rules.
+  * If the Linux kernel rules in
+    `Devicetree Sources (DTS) Coding Style <https://docs.kernel.org/devicetree/bindings/dts-coding-style.html>`_
+    make a recommendation, it's the preferred style in Zephyr too.
+  * You can split related groups of properties into "paragraphs" by
+    separating them with one empty line (two newline characters) if it aids
+    readability.
+  * Use dashes (``-``) as word separators for node and property names.
+  * Use underscores (``_``) as word separators in node labels.
+  * Leave a single space on each side of the equal sign (``=``) in property
+    definitions.
+  * Don't insert empty lines before a dedenting ``};``.
+  * Insert a single empty line to separate nodes at the same hierarchy level.
diff --git a/doc/contribute/style/index.rst b/doc/contribute/style/index.rst
new file mode 100644
index 00000000000..d0ff1814d4c
--- /dev/null
+++ b/doc/contribute/style/index.rst
@@ -0,0 +1,87 @@
+.. _coding_style:
+
+
+Coding Style Guidelines
+#######################
+
+.. toctree::
+   :maxdepth: 1
+
+   code.rst
+   cmake.rst
+   devicetree.rst
+   kconfig.rst
+
+
+Style Tools
+***********
+
+Checkpatch
+==========
+
+The Linux kernel GPL-licensed tool ``checkpatch`` is used to check
+coding style conformity.
+
+.. note::
+   checkpatch does not currently run on Windows.
+
+Checkpatch is available in the scripts directory. To invoke it when committing
+code, make the file *$ZEPHYR_BASE/.git/hooks/pre-commit* executable and edit
+it to contain:
+
+.. code-block:: bash
+
+    #!/bin/sh
+    set -e exec
+    exec git diff --cached | ${ZEPHYR_BASE}/scripts/checkpatch.pl -
+
+Instead of running checkpatch at each commit, you may prefer to run it only
+before pushing on zephyr repo. To do this, make the file
+*$ZEPHYR_BASE/.git/hooks/pre-push* executable and edit it to contain:
+
+.. code-block:: bash
+
+    #!/bin/sh
+    remote="$1"
+    url="$2"
+
+    z40=0000000000000000000000000000000000000000
+
+    echo "Run push hook"
+
+    while read local_ref local_sha remote_ref remote_sha
+    do
+        args="$remote $url $local_ref $local_sha $remote_ref $remote_sha"
+        exec ${ZEPHYR_BASE}/scripts/series-push-hook.sh $args
+    done
+
+    exit 0
+
+If you want to override checkpatch verdict and push you branch despite reported
+issues, you can add option --no-verify to the git push command.
+
+A different way for running ``checkpatch`` is by using :ref:`check_compliance_py`
+script, which does additional style and compliance related checks.
+
+clang-format
+============
+
+The `clang-format tool <https://clang.llvm.org/docs/ClangFormat.html>`_ can
+be helpful to quickly reformat large amounts of new source code to our
+`Coding Style Guidelines`_ standards together with the ``.clang-format`` configuration file
+provided in the repository. ``clang-format`` is well integrated into most
+editors, but you can also run it manually like this:
+
+.. code-block:: bash
+
+   clang-format -i my_source_file.c
+
+``clang-format`` is part of LLVM, which can be downloaded from the project
+`releases page <https://github.com/llvm/llvm-project/releases>`_. Note that if
+you are a Linux user, ``clang-format`` will likely be available as a package in
+your distribution repositories.
+
+When there are differences between the `Coding Style Guidelines`_ guidelines and the
+formatting generated by code formatting tools, the `Coding Style Guidelines`_ guidelines
+take precedence. If there is ambiguity between formatting tools and the
+guidelines, maintainers may decide which style should be adopted.
diff --git a/doc/contribute/style/kconfig.rst b/doc/contribute/style/kconfig.rst
new file mode 100644
index 00000000000..f73165e28d4
--- /dev/null
+++ b/doc/contribute/style/kconfig.rst
@@ -0,0 +1,14 @@
+.. _kconfig_style:
+
+Kconfig Style Guidelines
+########################
+
+  * Line length of 100 columns or fewer.
+  * Indent with tabs, except for ``help`` entry text which should be placed at
+    one tab plus two extra spaces.
+  * Leave a single empty line between option declarations.
+  * Use Statements like ``select`` carefully, see
+    :ref:`kconfig_tips_and_tricks` for more information.
+  * Format comments as ``# Comment`` rather than ``#Comment``
+  * Insert an empty line before/after each top-level ``if`` and ``endif``
+    statement.
diff --git a/doc/develop/application/index.rst b/doc/develop/application/index.rst
index 6bf3620adfd..42d53040bd2 100644
--- a/doc/develop/application/index.rst
+++ b/doc/develop/application/index.rst
@@ -721,12 +721,6 @@ Given the following example project layout:
 * If this is build with ``FILE_SUFFIX`` set to ``mouse`` for ``qemu_cortex_m3`` then
   ``prj_mouse.conf`` will be used and ``boards/qemu_cortex_m3_mouse.overlay`` will be used.
 
-.. note::
-
-   When ``CONF_FILE`` is set in the form of ``prj_X.conf`` then the ``X`` will be used as the
-   build type. If this is combined with ``FILE_SUFFIX`` then the file suffix option will take
-   priority over the build type.
-
 Application-Specific Code
 *************************
 
@@ -1202,6 +1196,11 @@ boilerplate with ``find_package(Zephyr ...)``.
    When using ``-DBOARD_ROOT=<board-root>`` both absolute and relative paths can
    be used. Relative paths are treated relatively to the application directory.
 
+.. note::
+
+   When using sysbuild, then ``BOARD_ROOT`` must defined in a module or in the sysbuild
+   ``CMakeLists.txt`` file, see :ref:`sysbuild_var_override` for details.
+
 SOC Definitions
 ===============
 
diff --git a/doc/develop/beyond-GSG.rst b/doc/develop/beyond-GSG.rst
index ab0a1aba84f..fe7e646e9e8 100644
--- a/doc/develop/beyond-GSG.rst
+++ b/doc/develop/beyond-GSG.rst
@@ -136,6 +136,8 @@ Keeping Zephyr updated
 To update the Zephyr project source code, you need to get the latest
 changes via ``git``. Afterwards, run ``west update`` as mentioned in
 the previous paragraph.
+Additionally, in the case of updated or added Python dependencies, running
+``west packages pip --install`` will make sure these are up-to-date.
 
 .. code-block:: console
 
@@ -143,6 +145,7 @@ the previous paragraph.
    cd zephyrproject/zephyr
    git pull
    west update
+   west packages pip --install
 
 Export Zephyr CMake package
 ***************************
diff --git a/doc/develop/flash_debug/host-tools.rst b/doc/develop/flash_debug/host-tools.rst
index e0788734091..dfe04626946 100644
--- a/doc/develop/flash_debug/host-tools.rst
+++ b/doc/develop/flash_debug/host-tools.rst
@@ -13,6 +13,7 @@ file declares that support properly. See :ref:`west-build-flash-debug` for
 more information on these commands.
 
 .. _atmel_sam_ba_bootloader:
+.. _runner_bossac:
 
 SAM Boot Assistant (SAM-BA)
 ***************************
@@ -185,8 +186,8 @@ As a quick reference, see these three board documentation pages:
 
   - :zephyr:board:`sam4e_xpro` (ROM bootloader)
   - :zephyr:board:`adafruit_feather_m0_basic_proto` (Adafruit UF2 bootloader)
-  - :ref:`arduino_nano_33_iot` (Arduino bootloader)
-  - :ref:`arduino_nano_33_ble` (Arduino legacy bootloader)
+  - :zephyr:board:`arduino_nano_33_iot` (Arduino bootloader)
+  - :zephyr:board:`arduino_nano_33_ble` (Arduino legacy bootloader)
 
 Enabling BOSSAC on Windows Native [Experimental]
 ------------------------------------------------
@@ -207,6 +208,7 @@ Windows PATH. A specific bossac executable can be used by passing the
 
 
 .. _linkserver-debug-host-tools:
+.. _runner_linkserver:
 
 LinkServer Debug  Host Tools
 ****************************
@@ -282,6 +284,7 @@ LinkServer west runner   ``--probe`` option to pass the probe index.
    will need to add a breakpoint at ``main`` or the reset handler manually.
 
 .. _jlink-debug-host-tools:
+.. _runner_jlink:
 
 J-Link Debug Host Tools
 ***********************
@@ -312,6 +315,7 @@ required.
 Note that the J-Link GDB server does not yet support Zephyr RTOS-awareness.
 
 .. _openocd-debug-host-tools:
+.. _runner_openocd:
 
 OpenOCD Debug Host Tools
 ************************
@@ -339,6 +343,7 @@ Check if your SoC is listed in `OpenOCD Supported Devices`_.
    - Add ``C:\Program Files\OpenOCD\bin`` to 'PATH' environment variable
 
 .. _pyocd-debug-host-tools:
+.. _runner_pyocd:
 
 pyOCD Debug Host Tools
 **********************
@@ -358,6 +363,7 @@ These debug host tools are compatible with the following debug probes:
 Check if your SoC is listed in `pyOCD Supported Devices`_.
 
 .. _lauterbach-trace32-debug-host-tools:
+.. _runner_trace32:
 
 Lauterbach TRACE32 Debug Host Tools
 ***********************************
@@ -409,6 +415,7 @@ To enable Zephyr RTOS awareness follow the steps described in
 `Lauterbach TRACE32 Zephyr OS Awareness Manual`_.
 
 .. _nxp-s32-debug-host-tools:
+.. _runner_nxp_s32dbg:
 
 NXP S32 Debug Probe Host Tools
 ******************************
@@ -471,6 +478,8 @@ afterwards detach the debug session:
 
    west debug --tool-opt='--batch'
 
+.. _runner_probe_rs:
+
 probe-rs Debug Host Tools
 *************************
 
@@ -482,7 +491,29 @@ Check `probe-rs Installation`_ for more setup details.
 
 Check if your SoC is listed in `probe-rs Supported Devices`_.
 
+.. _runner_rfp:
+
+Renesas Flash Programmer (RFP) Host Tools
+*****************************************
+
+Renesas provides `Renesas Flash Programmer`_ as an official programming tool for Renesas boards
+using the Renesas standard boot firmware. It is available as a GUI and CLI.
+
+For boards configured with the ``rfp`` west runner, the RFP CLI can be easily used to flash Zephyr.
+
+Supported west commands:
+
+1. flash
+
+Once downloaded, if ``rfp-cli`` is not placed somewhere in your system PATH, you can pass the location
+to ``rfp-cli`` when flashing:
+
+.. code-block:: console
+
+   west flash --rfp-cli ~/Downloads/RFP_CLI_Linux_V31800_x64/linux-x64/rfp-cli
+
 .. _stm32cubeprog-flash-host-tools:
+.. _runner_stm32cubeprogrammer:
 
 STM32CubeProgrammer Flash Host Tools
 ************************************
@@ -572,6 +603,9 @@ For advanced usage via the GUI or CLI, check out the `STM32CubeProgrammer User M
 .. _NXP S32 Design Studio for S32 Platform:
    https://www.nxp.com/design/software/development-software/s32-design-studio-ide/s32-design-studio-for-s32-platform:S32DS-S32PLATFORM
 
+.. _Renesas Flash Programmer:
+   https://www.renesas.com/en/software-tool/renesas-flash-programmer-programming-gui
+
 .. _S32 Design Studio for S32 Platform Installation User Guide:
    https://www.nxp.com/webapp/Download?colCode=S32DSIG
 
diff --git a/doc/develop/flash_debug/nordic_segger.rst b/doc/develop/flash_debug/nordic_segger.rst
index 083601f91aa..13fe81f6a01 100644
--- a/doc/develop/flash_debug/nordic_segger.rst
+++ b/doc/develop/flash_debug/nordic_segger.rst
@@ -109,13 +109,13 @@ temporarily disable ModemManager by running these commands:
    systemctl stop ModemManager.service
    systemctl disable ModemManager.service
 
-You can also `blacklist Segger devices by editing udev rules`_ so ModemManager
+You can also `blocklist Segger devices by editing udev rules`_ so ModemManager
 ignores them, by running:
 
 .. code-block:: bash
 
    sudo sh -c 'echo "ATTRS{idVendor}==\"1366\", ENV{ID_MM_DEVICE_IGNORE}=\"1\" " \
-     >> /etc/udev/rules.d/99-segger-modemmanager-blacklist.rules'
+     >> /etc/udev/rules.d/99-segger-modemmanager-blocklist.rules'
    sudo service udev restart
 
 A fix for this is expected in ModemManager 1.8 and new firmware for the Segger IMCUs.
@@ -245,6 +245,6 @@ References
 .. _Segger Ozone Download: https://www.segger.com/downloads/jlink#Ozone
 
 .. _ModemManager send AT commands to TTY-like devices: https://bugs.freedesktop.org/show_bug.cgi?id=85007
-.. _blacklist Segger devices by editing udev rules: http://www.at91.com/linux4sam/bin/view/Linux4SAM/SoftwareTools#Device_or_resource_busy_dev_ttyA
+.. _blocklist Segger devices by editing udev rules: http://www.at91.com/linux4sam/bin/view/Linux4SAM/SoftwareTools#Device_or_resource_busy_dev_ttyA
 
 .. _J-Link Software and documentation pack: https://www.segger.com/jlink-software.html
diff --git a/doc/develop/getting_started/index.rst b/doc/develop/getting_started/index.rst
index a79b3489acc..78f43e70b5f 100644
--- a/doc/develop/getting_started/index.rst
+++ b/doc/develop/getting_started/index.rst
@@ -95,6 +95,11 @@ The current minimum required version for the main dependencies are:
               python3-dev python3-pip python3-setuptools python3-tk python3-wheel xz-utils file \
               make gcc gcc-multilib g++-multilib libsdl2-dev libmagic1
 
+         .. note::
+
+            Due to the unavailability of ``gcc-multilib`` and ``g++-multilib`` on AArch64
+            (ARM64) systems, you may need to remove them from the list of packages to install.
+
       #. Verify the versions of the main dependencies installed on your system by entering:
 
          .. code-block:: bash
@@ -155,48 +160,42 @@ The current minimum required version for the main dependencies are:
 
          Therefore, we don't recommend using WSL when getting started.
 
-      These instructions must be run in a ``cmd.exe`` command prompt terminal window.
       In modern version of Windows (10 and later) it is recommended to install the Windows Terminal
-      application from the Microsoft Store. The required commands differ on PowerShell.
+      application from the Microsoft Store. Instructions are provided for a ``cmd.exe`` or
+      PowerShell command prompts.
 
-      These instructions rely on `Chocolatey`_. If Chocolatey isn't an option,
-      you can install dependencies from their respective websites and ensure
-      the command line tools are on your :envvar:`PATH` :ref:`environment
-      variable <env_vars>`.
+      These instructions rely on Windows' official package manager, `winget`_.
+      If using winget isn't an option, you can install dependencies from their
+      respective websites and ensure the command line tools are on your
+      :envvar:`PATH` :ref:`environment variable <env_vars>`.
 
       |p|
 
       .. _install_dependencies_windows:
 
-      #. `Install chocolatey`_.
+      #. In modern Windows versions, winget is already pre-installed by default.
+         You can verify that this is the case by typing ``winget`` in a terminal
+         window. If that fails, you can then `install winget`_.
 
-      #. Open a ``cmd.exe`` terminal window as **Administrator**. To do so, press the Windows key,
-         type ``cmd.exe``, right-click the :guilabel:`Command Prompt` search result, and choose
-         :guilabel:`Run as Administrator`.
+      #. Open a Command Prompt (``cmd.exe``) or PowerShell terminal window.
+         To do so, press the Windows key, type ``cmd.exe`` or PowerShell and
+         click on the result.
 
-      #. Disable global confirmation to avoid having to confirm the
-         installation of individual programs:
+      #. Use ``winget`` to install the required dependencies:
 
          .. code-block:: bat
 
-            choco feature enable -n allowGlobalConfirmation
-
-      #. Use ``choco`` to install the required dependencies:
+            winget install Kitware.CMake Ninja-build.Ninja oss-winget.gperf python Git.Git oss-winget.dtc wget 7zip.7zip
 
-         .. code-block:: bat
-
-            choco install cmake --installargs 'ADD_CMAKE_TO_PATH=System'
-            choco install ninja gperf python311 git dtc-msys2 wget 7zip
+      #. Close the terminal window.
 
-         .. warning::
+      .. note::
 
-            As of November 2024, Python 3.13 is not recommended for Zephyr development on Windows,
-            as some required Python dependencies may be difficult to install.
+         You may need to add the 7zip installation folder to your ``PATH``.
 
-      #. Close the terminal window.
 
-.. _Chocolatey: https://chocolatey.org/
-.. _Install chocolatey: https://chocolatey.org/install
+.. _winget: https://learn.microsoft.com/en-us/windows/package-manager/
+.. _install winget: https://aka.ms/getwinget
 
 .. _get_the_code:
 .. _clone-zephyr:
@@ -207,8 +206,10 @@ Get Zephyr and install Python dependencies
 ******************************************
 
 Next, clone Zephyr and its :ref:`modules <modules>` into a new :ref:`west
-<west>` workspace named :file:`zephyrproject`. You'll also install Zephyr's
-additional Python dependencies in a `Python virtual environment`_.
+<west>` workspace. In the following instructions the name :file:`zephyrproject`
+is used for the workspace, however in practice its name and location can be freely
+chosen. You'll also install Zephyr's additional Python dependencies in a
+`Python virtual environment`_.
 
 .. _Python virtual environment: https://docs.python.org/3/library/venv.html
 
@@ -326,20 +327,33 @@ additional Python dependencies in a `Python virtual environment`_.
 
    .. group-tab:: Windows
 
-      #. Open a ``cmd.exe`` terminal window **as a regular user**
+      #. Open a ``cmd.exe`` or PowerShell terminal window **as a regular user**
 
       #. Create a new virtual environment:
 
-         .. code-block:: bat
+         .. tabs::
+
+            .. code-tab:: bat
 
-            cd %HOMEPATH%
-            python -m venv zephyrproject\.venv
+               cd %HOMEPATH%
+               python -m venv zephyrproject\.venv
+
+            .. code-tab:: powershell
+
+               cd $Env:HOMEPATH
+               python -m venv zephyrproject\.venv
 
       #. Activate the virtual environment:
 
-         .. code-block:: bat
+         .. tabs::
 
-            zephyrproject\.venv\Scripts\activate.bat
+            .. code-tab:: bat
+
+               zephyrproject\.venv\Scripts\activate.bat
+
+            .. code-tab:: powershell
+
+               zephyrproject\.venv\Scripts\Activate.ps1
 
          Once activated your shell will be prefixed with ``(.venv)``. The
          virtual environment can be deactivated at any time by running
@@ -427,10 +441,17 @@ that are used to emulate, flash and debug Zephyr applications.
 
       Install the Zephyr SDK using the ``west sdk install``.
 
-         .. code-block:: bat
+         .. tabs::
 
-            cd %HOMEPATH%\zephyrproject\zephyr
-            west sdk install
+            .. code-tab:: bat
+
+               cd %HOMEPATH%\zephyrproject\zephyr
+               west sdk install
+
+            .. code-tab:: powershell
+
+               cd $Env:HOMEPATH\zephyrproject\zephyr
+               west sdk install
 
       .. tip::
 
@@ -478,10 +499,17 @@ Build the :zephyr:code-sample:`blinky` with :ref:`west build <west-building>`, c
 
    .. group-tab:: Windows
 
-      .. code-block:: bat
+      .. tabs::
+
+         .. code-tab:: bat
+
+            cd %HOMEPATH%\zephyrproject\zephyr
+            west build -p always -b <your-board-name> samples\basic\blinky
+
+         .. code-tab:: powershell
 
-         cd %HOMEPATH%\zephyrproject\zephyr
-         west build -p always -b <your-board-name> samples\basic\blinky
+            cd $Env:HOMEPATH\zephyrproject\zephyr
+            west build -p always -b <your-board-name> samples\basic\blinky
 
 The ``-p always`` option forces a pristine build, and is recommended for new
 users. Users may also use the ``-p auto`` option, which will use
@@ -495,7 +523,7 @@ another sample.
    When building for such boards it is necessary to specify the SoC or CPU
    cluster for which the sample must be built.
    For example to build :zephyr:code-sample:`blinky` for the ``cpuapp`` core on
-   the :ref:`nRF5340DK <nrf5340dk_nrf5340>` the board must be provided as:
+   the :zephyr:board:`nrf5340dk` the board must be provided as:
    ``nrf5340dk/nrf5340/cpuapp``. See also :ref:`board_terminology` for more
    details.
 
diff --git a/doc/develop/languages/index.rst b/doc/develop/languages/index.rst
index 033b9084ac4..b1b54355f1a 100644
--- a/doc/develop/languages/index.rst
+++ b/doc/develop/languages/index.rst
@@ -8,3 +8,4 @@ Language Support
 
    c/index.rst
    cpp/index.rst
+   rust/index.rst
diff --git a/doc/develop/languages/rust/index.rst b/doc/develop/languages/rust/index.rst
new file mode 100644
index 00000000000..8363fc7797d
--- /dev/null
+++ b/doc/develop/languages/rust/index.rst
@@ -0,0 +1,100 @@
+.. _language_rust:
+
+Rust Language Support
+#####################
+
+Rust is a modern systems programming language designed to provide memory safety, concurrency, and
+performance without sacrificing low-level control. It achieves this through a unique ownership model
+that eliminates common bugs like null pointer dereferencing and data races at compile time.
+
+Rust's emphasis on safety and correctness makes it particularly well-suited for embedded systems and
+environments where reliability is critical.
+Additionally, Rust offers powerful abstractions without a runtime or garbage collector, allowing
+developers to write both high-level code and low-level hardware interactions with confidence and
+efficiency.
+
+These attributes make Rust a strong choice for projects on Zephyr, where resource constraints and
+system stability are paramount.
+
+Enabling Rust Support
+*********************
+
+In order to enable Rust support in a Zephyr application, a few things need to be done:
+
+1.  As Rust is currently an optional module, the module needs to be enabled.  The easiest way to do
+    this is with west:
+
+    .. code-block:: shell
+
+       west config manifest.project-filter +zephyr-lang-rust
+       west update
+
+    This should cause the Rust language support to be placed in :samp:`modules/lang/rust` in your
+    Zephyr workspace.
+
+2.  Enable Rust support, via :kconfig:option:`CONFIG_RUST` in the :file:`prj.conf`. The easiest way
+    to do this (as well as the CMake setup from the next step) is to start with one of the samples
+    in :module_file:`modules/lang/rust/samples <zephyr-lang-rust:samples>`.
+
+3.  Configure the application's :file:`CMakeLists.txt` file to support Rust.  Again this is easiest
+    to copy from a sample, but this will look something like:
+
+    .. code-block:: cmake
+
+       cmake_minimum_required(VERSION 3.20.0)
+
+       find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+       project(my_app)
+       rust_cargo_application()
+
+4.  Create a :file:`Cargo.toml` that describes how to build the Rust application. From the Hello
+    World sample:
+
+    .. code-block:: toml
+
+       [package]
+       # This must be rustapp for now.
+       name = "rustapp"
+       version = "0.1.0"
+       edition = "2021"
+       description = "The description of my app"
+       license = "Apache-2.0 or MIT"
+
+       [lib]
+       crate-type = ["staticlib"]
+
+       [dependencies]
+       zephyr = "0.1.0"
+       log = "0.4.22"
+
+    The only required dependency is ``zephyr`` which provides the zephyr crate that is used to
+    interface with Zephyr.
+
+5.  Build as you would any other Zephyr application.  Only a few targets currently support Rust
+    (these can be seen in the
+    :module_file:`modules/lang/rust/etc/platforms.txt <zephyr-lang-rust:etc/platforms.txt>` file).
+
+API Documentation
+*****************
+
+The `API Documentation`_ for the latest version in the module is kept on gh-pages.
+
+.. _`API Documentation`:
+   https://zephyrproject-rtos.github.io/zephyr-lang-rust/nostd/zephyr/index.html
+
+This documentation is generated for a general target, with all features enabled.  Once you have an
+application that is buildable, you can generate documentation specifically for your target:
+
+.. code-block:: shell
+
+   west build -t rustdoc
+
+   ...
+
+   Generated /my/path/app/zephyr/build/doc/rust/target/riscv32i-unknown-none-elf/doc/rustapp/index.html
+
+The path printed at the end can be opened in a browser.  This top level docs will be for your
+application itself.  Look for the 'zephyr' crate on the left side bar, and this will take you to the
+docs for Zephyr.  This page will also generate local docs for any dependencies used by your
+application, directly or indirectly.
diff --git a/doc/develop/optimizations/footprint.rst b/doc/develop/optimizations/footprint.rst
index b826bc26fbe..fbe416157af 100644
--- a/doc/develop/optimizations/footprint.rst
+++ b/doc/develop/optimizations/footprint.rst
@@ -40,14 +40,16 @@ peripherals in your project configuration, for example::
 Various Debug/Informational Options
 ***********************************
 
-The following options are enabled by default to provide more information about
-the running application and to provide means for debugging and error handling:
+The following options output more information about
+the running application and provide means for debugging and error handling:
 
 :kconfig:option:`CONFIG_BOOT_BANNER`
   This option can be disabled to save a few bytes.
 
 :kconfig:option:`CONFIG_DEBUG`
-  This option can be disabled for production builds
+  This option can be enabled for debug builds.
+
+Note that the boot banner is enabled by default.
 
 
 MPU/MMU Support
diff --git a/doc/develop/sca/gcc.rst b/doc/develop/sca/gcc.rst
index 4ae852c81ad..1123772b722 100644
--- a/doc/develop/sca/gcc.rst
+++ b/doc/develop/sca/gcc.rst
@@ -13,6 +13,58 @@ Run GCC static analysis
 To run GCC static analysis, :ref:`west build <west-building>` should be
 called with a ``-DZEPHYR_SCA_VARIANT=gcc`` parameter, e.g.
 
-.. code-block:: shell
+.. zephyr-app-commands::
+   :zephyr-app: samples/userspace/hello_world_user
+   :board: qemu_x86
+   :gen-args: -DZEPHYR_SCA_VARIANT=gcc
+   :goals: build
+   :compact:
 
-    west build -b qemu_x86 samples/userspace/hello_world_user -- -DZEPHYR_SCA_VARIANT=gcc
+Configuring GCC static analyzer
+*******************************
+
+GCC static analyzer can be controlled using specific options.
+
+* `Options controlling the
+  analyzer <https://gcc.gnu.org/onlinedocs/gcc/Static-Analyzer-Options.html>`__
+* `Options controlling the diagnostic message
+  formatting <https://gcc.gnu.org/onlinedocs/gcc/Diagnostic-Message-Formatting-Options.html>`__
+
+.. list-table::
+   :header-rows: 1
+
+   * - Parameter
+     - Description
+   * - ``GCC_SCA_OPTS``
+     - A semicolon separated list of GCC analyzer options.
+
+These parameters can be passed on the command line, or be set as environment variables.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: stm32h573i_dk
+   :gen-args: -DZEPHYR_SCA_VARIANT=gcc -DGCC_SCA_OPTS="-fdiagnostics-format=json;-fanalyzer-verbosity=3"
+   :goals: build
+   :compact:
+
+.. note::
+
+   GCC static analyzer is under active development, and each new release comes with new options.
+   This `page <https://gcc.gnu.org/wiki/StaticAnalyzer>`__ gives an overview of options and fix
+   introduced with each new release of the analyzer.
+
+
+Latest version of the analyzer
+******************************
+
+Since the Zephyr toolchain may not include the most recent version of the GCC static analyzer,
+the GCC static analysis can be run with a more recent `GNU Arm embedded toolchain
+<https://docs.zephyrproject.org/latest/develop/toolchains/gnu_arm_embedded.html>`__
+to take advantage of the latest analyzer version.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: stm32h573i_dk
+   :gen-args: -DZEPHYR_SCA_VARIANT=gcc -DZEPHYR_TOOLCHAIN_VARIANT=gnuarmemb -DGNUARMEMB_TOOLCHAIN_PATH=...
+   :goals: build
+   :compact:
diff --git a/doc/develop/test/bsim.rst b/doc/develop/test/bsim.rst
index 0bdc7d0fecc..d5484df51b5 100644
--- a/doc/develop/test/bsim.rst
+++ b/doc/develop/test/bsim.rst
@@ -7,11 +7,11 @@ BabbleSim and Zephyr
 ********************
 
 In the Zephyr project we use the `Babblesim`_ simulator to test some of the Zephyr radio protocols,
-including the BLE stack, 802.15.4, and some of the networking stack.
+including the Bluetooth LE stack, 802.15.4, and some of the networking stack.
 
 BabbleSim_ is a physical layer simulator, which in combination with the Zephyr
 :ref:`bsim boards<bsim boards>`
-can be used to simulate a network of BLE and 15.4 devices.
+can be used to simulate a network of Bluetooth LE and 15.4 devices.
 When we build Zephyr targeting a :ref:`bsim board<bsim boards>` we produce a Linux
 executable, which includes the application, Zephyr OS, and models of the HW.
 
diff --git a/doc/develop/test/coverage.rst b/doc/develop/test/coverage.rst
index 5c86adda1b3..1811990b273 100644
--- a/doc/develop/test/coverage.rst
+++ b/doc/develop/test/coverage.rst
@@ -60,34 +60,42 @@ These steps will produce an HTML coverage report for a single application.
 
    .. code-block:: console
 
-      ninja -Cbuild run | tee log.log
+     $ ninja -Cbuild run | tee log.log
 
    or
 
    .. code-block:: console
 
-      ninja -Cbuild run | tee log.log
+     $ ninja -Cbuild run | tee log.log
 
 #. Generate the gcov ``.gcda`` and ``.gcno`` files from the log file that was
-   saved::
+   saved:
+
+   .. code-block:: console
 
      $ python3 scripts/gen_gcov_files.py -i log.log
 
 #. Find the gcov binary placed in the SDK. You will need to pass the path to
    the gcov binary for the appropriate architecture when you later invoke
-   ``gcovr``::
+   ``gcovr``:
+
+   .. code-block:: console
 
      $ find $ZEPHYR_SDK_INSTALL_DIR -iregex ".*gcov"
 
-#. Create an output directory for the reports::
+#. Create an output directory for the reports:
+
+   .. code-block:: console
 
      $ mkdir -p gcov_report
 
-#. Run ``gcovr`` to get the reports::
+#. Run ``gcovr`` to get the reports:
+
+   .. code-block:: console
 
      $ gcovr -r $ZEPHYR_BASE . --html -o gcov_report/coverage.html --html-details --gcov-executable <gcov_path_in_SDK>
 
-.. _coverage_posix:
+   .. _coverage_posix:
 
 Coverage reports using the POSIX architecture
 *********************************************
@@ -117,8 +125,8 @@ You may postprocess these with your preferred tools. For example:
 
    $ ./build/zephyr/zephyr.exe
    # Press Ctrl+C to exit
-   lcov --capture --directory ./ --output-file lcov.info -q --rc lcov_branch_coverage=1
-   genhtml lcov.info --output-directory lcov_html -q --ignore-errors source --branch-coverage --highlight --legend
+   $ lcov --capture --directory ./ --output-file lcov.info -q --rc lcov_branch_coverage=1
+   $ genhtml lcov.info --output-directory lcov_html -q --ignore-errors source --branch-coverage --highlight --legend
 
 .. note::
 
@@ -134,11 +142,15 @@ Zephyr's :ref:`twister script <twister_script>` can automatically
 generate a coverage report from the tests which were executed.
 You just need to invoke it with the ``--coverage`` command line option.
 
-For example, you may invoke::
+For example, you may invoke:
+
+.. code-block:: console
 
     $ twister --coverage -p qemu_x86 -T tests/kernel
 
-or::
+or:
+
+.. code-block:: console
 
     $ twister --coverage -p native_sim -T tests/bluetooth
 
@@ -148,13 +160,36 @@ the coverage data collected by ``gcovr`` tool in ``twister-out/coverage.json``.
 Other reports might be chosen with ``--coverage-tool`` and ``--coverage-formats``
 command line options.
 
+To generate code coverage report including Zephyr sources as well as your application
+code outside of Zephyr repository (see :ref:`Application Types <zephyr-app-types>`)
+call Twister from your project directory with ``--coverage-basedir $ZEPHYR_BASE``
+command line option, for example:
+
+.. code-block:: console
+
+   $ $ZEPHYR_BASE/scripts/twister --coverage -p native_sim --coverage_basedir $ZEPHYR_BASE -T your_project_dir
+
+.. note::
+
+   By default, Twister calls ``gcovr`` tool which filters source files assuming real paths
+   are everywhere with `all symlinks resolved <gcovr_symlinks_>`_, so when your development
+   environment has directories with symlinks then, to avoid incomplete ``gcovr`` reports,
+   either your :ref:`ZEPHYR_BASE <important-build-vars>` should contain a real path,
+   or ``lcov`` tool used instead of ``gcovr`` with additional Twister command line
+   option ``--coverage-tool lcov``.
+
 The process differs for unit tests, which are built with the host
-toolchain and require a different board::
+toolchain and require a different board:
 
-    $ twister --coverage -p unit_testing -T tests/unit
+.. code-block:: console
+
+   $ twister --coverage -p unit_testing -T tests/unit
 
 which produces a report in the same location as non-unit testing.
 
+.. _gcovr_symlinks:
+   https://github.com/gcovr/gcovr/blob/main/doc/source/guide/filters.rst#filters-for-symlinks
+
 .. _gcov:
    https://gcc.gnu.org/onlinedocs/gcc/Gcov.html
 
diff --git a/doc/develop/test/twister.rst b/doc/develop/test/twister.rst
index 8831904ee6d..948a487439a 100644
--- a/doc/develop/test/twister.rst
+++ b/doc/develop/test/twister.rst
@@ -116,7 +116,6 @@ required for best test coverage for this specific board:
   toolchain:
     - zephyr
     - gnuarmemb
-    - xtools
   supported:
     - arduino_gpio
     - arduino_i2c
@@ -560,30 +559,10 @@ harness: <string>
     - pytest
     - gtest
     - robot
+    - ctest
+    - shell
 
-    Harnesses ``ztest``, ``gtest`` and ``console`` are based on parsing of the
-    output and matching certain phrases. ``ztest`` and ``gtest`` harnesses look
-    for pass/fail/etc. frames defined in those frameworks. Use ``gtest``
-    harness if you've already got tests written in the gTest framework and do
-    not wish to update them to zTest. The ``console`` harness tells Twister to
-    parse a test's text output for a regex defined in the test's YAML file.
-    The ``robot`` harness is used to execute Robot Framework test suites
-    in the Renode simulation framework.
-
-    Some widely used harnesses that are not supported yet:
-
-    - keyboard
-    - net
-    - bluetooth
-
-    Harness ``bsim`` is implemented in limited way - it helps only to copy the
-    final executable (``zephyr.exe``) from build directory to BabbleSim's
-    ``bin`` directory (``${BSIM_OUT_PATH}/bin``). This action is useful to allow
-    BabbleSim's tests to directly run after. By default, the executable file
-    name is (with dots and slashes replaced by underscores):
-    ``bs_<platform_name>_<test_path>_<test_scenario_name>``.
-    This name can be overridden with the ``bsim_exe_name`` option in
-    ``harness_config`` section.
+    See :ref:`twister_harnesses` for more information.
 
 platform_key: <list of platform attributes>
     Often a test needs to only be built and run once to qualify as passing.
@@ -612,71 +591,6 @@ harness_config: <harness configuration options>
     what features it supports. This option will enable the test to run on
     only those platforms that fulfill this external dependency.
 
-    The following options are currently supported:
-
-    type: <one_line|multi_line> (required)
-        Depends on the regex string to be matched
-
-    regex: <list of regular expressions> (required)
-        Strings with regular expressions to match with the test's output
-        to confirm the test runs as expected.
-
-    ordered: <True|False> (default False)
-        Check the regular expression strings in orderly or randomly fashion
-
-    record: <recording options> (optional)
-      regex: <regular expression> (required)
-        The regular expression with named subgroups to match data fields
-        at the test's output lines where the test provides some custom data
-        for further analysis. These records will be written into the build
-        directory ``recording.csv`` file as well as ``recording`` property
-        of the test suite object in ``twister.json``.
-
-        For example, to extract three data fields ``metric``, ``cycles``,
-        ``nanoseconds``:
-
-        .. code-block:: yaml
-
-          record:
-            regex: "(?P<metric>.*):(?P<cycles>.*) cycles, (?P<nanoseconds>.*) ns"
-
-      as_json: <list of regex subgroup names> (optional)
-        Data fields, extracted by the regular expression into named subgroups,
-        which will be additionally parsed as JSON encoded strings and written
-        into ``twister.json`` as nested ``recording`` object properties.
-        The corresponding ``recording.csv`` columns will contain strings as-is.
-
-        Using this option, a test log can convey layered data structures
-        passed from the test image for further analysis with summary results,
-        traces, statistics, etc.
-
-        For example, this configuration:
-
-        .. code-block:: yaml
-
-          record:
-            regex: "RECORD:(?P<type>.*):DATA:(?P<metrics>.*)"
-            as_json: [metrics]
-
-        when matched to a test log string:
-
-        .. code-block:: none
-
-          RECORD:jitter_drift:DATA:{"rollovers":0, "mean_us":1000.0}
-
-        will be reported in ``twister.json`` as:
-
-        .. code-block:: json
-
-          "recording":[
-              {
-                   "type":"jitter_drift",
-                   "metrics":{
-                       "rollovers":0,
-                       "mean_us":1000.0
-                   }
-              }
-          ]
 
     fixture: <expression>
         Specify a test scenario dependency on an external device(e.g., sensor),
@@ -689,94 +603,6 @@ harness_config: <harness configuration options>
         Only one fixture can be defined per test scenario and the fixture name has to
         be unique across all tests in the test suite.
 
-.. _pytest_root:
-
-    pytest_root: <list of pytest testpaths> (default pytest)
-        Specify a list of pytest directories, files or subtests that need to be
-        executed when a test scenario begins to run. The default pytest directory is
-        ``pytest``. After the pytest run is finished, Twister will check if
-        the test scenario passed or failed according to the pytest report.
-        As an example, a list of valid pytest roots is presented below:
-
-        .. code-block:: yaml
-
-            harness_config:
-              pytest_root:
-                - "pytest/test_shell_help.py"
-                - "../shell/pytest/test_shell.py"
-                - "/tmp/test_shell.py"
-                - "~/tmp/test_shell.py"
-                - "$ZEPHYR_BASE/samples/subsys/testsuite/pytest/shell/pytest/test_shell.py"
-                - "pytest/test_shell_help.py::test_shell2_sample"  # select pytest subtest
-                - "pytest/test_shell_help.py::test_shell2_sample[param_a]"  # select pytest parametrized subtest
-
-.. _pytest_args:
-
-    pytest_args: <list of arguments> (default empty)
-        Specify a list of additional arguments to pass to ``pytest`` e.g.:
-        ``pytest_args: [‘-k=test_method’, ‘--log-level=DEBUG’]``. Note that
-        ``--pytest-args`` can be passed multiple times to pass several arguments
-        to the pytest.
-
-.. _pytest_dut_scope:
-
-    pytest_dut_scope: <function|class|module|package|session> (default function)
-        The scope for which ``dut`` and ``shell`` pytest fixtures are shared.
-        If the scope is set to ``function``, DUT is launched for every test case
-        in python script. For ``session`` scope, DUT is launched only once.
-
-    robot_testsuite: <robot file path> (default empty)
-        Specify one or more paths to a file containing a Robot Framework test suite to be run.
-
-    robot_option: <robot option> (default empty)
-        One or more options to be send to robotframework.
-
-    bsim_exe_name: <string>
-        If provided, the executable filename when copying to BabbleSim's bin
-        directory, will be ``bs_<platform_name>_<bsim_exe_name>`` instead of the
-        default based on the test path and scenario name.
-
-    The following is an example yaml file with a few harness_config options.
-
-    .. code-block:: yaml
-
-         sample:
-           name: HTS221 Temperature and Humidity Monitor
-         common:
-           tags: sensor
-           harness: console
-           harness_config:
-             type: multi_line
-             ordered: false
-             regex:
-               - "Temperature:(.*)C"
-               - "Relative Humidity:(.*)%"
-             fixture: i2c_hts221
-         tests:
-           test:
-             tags: sensors
-             depends_on: i2c
-
-    The following is an example yaml file with pytest harness_config options,
-    default pytest_root name "pytest" will be used if pytest_root not specified.
-    please refer the examples in samples/subsys/testsuite/pytest/.
-
-    .. code-block:: yaml
-
-        common:
-          harness: pytest
-        tests:
-          pytest.example.directories:
-            harness_config:
-              pytest_root:
-                - pytest_dir1
-                - $ENV_VAR/samples/test/pytest_dir2
-          pytest.example.files_and_subtests:
-            harness_config:
-              pytest_root:
-                - pytest/test_file_1.py
-                - test_file_2.py::test_A
-                - test_file_2.py::test_B[param_a]
 
     The following is an example yaml file with robot harness_config options.
 
@@ -908,6 +734,11 @@ required_snippets: <list of needed snippets>
               - cdc-acm-console
               - user-snippet-example
 
+expect_reboot: <True|False> (default False)
+    Notify twister that the test scenario is expected to reboot while executing.
+    When enabled, twister will suppress warnings about unexpected multiple runs
+    of a testsuite or testcase.
+
 The set of test scenarios that actually run depends on directives in the test scenario
 filed and options passed in on the command line. If there is any confusion,
 running with ``-v`` or examining the discard report
@@ -924,6 +755,283 @@ line break instead of white spaces.
 
 Most everyday users will run with no arguments.
 
+.. _twister_harnesses:
+
+Harnesses
+*********
+
+Harnesses ``ztest``, ``gtest`` and ``console`` are based on parsing of the
+output and matching certain phrases. ``ztest`` and ``gtest`` harnesses look
+for pass/fail/etc. frames defined in those frameworks.
+
+Some widely used harnesses that are not supported yet:
+
+- keyboard
+- net
+- bluetooth
+
+The following is an example yaml file with a few harness_config options.
+
+.. code-block:: yaml
+
+      sample:
+        name: HTS221 Temperature and Humidity Monitor
+      common:
+        tags: sensor
+        harness: console
+        harness_config:
+          type: multi_line
+          ordered: false
+          regex:
+            - "Temperature:(.*)C"
+            - "Relative Humidity:(.*)%"
+          fixture: i2c_hts221
+      tests:
+        test:
+          tags: sensors
+          depends_on: i2c
+
+Ctest
+=====
+
+ctest_args: <list of arguments> (default empty)
+    Specify a list of additional arguments to pass to ``ctest`` e.g.:
+    ``ctest_args: [‘--repeat until-pass:5’]``. Note that
+    ``--ctest-args`` can be passed multiple times to pass several arguments
+    to the ctest.
+
+
+Gtest
+=====
+
+Use ``gtest`` harness if you've already got tests written in the gTest
+framework and do not wish to update them to zTest.
+
+Pytest
+======
+
+The :ref:`pytest harness <integration_with_pytest>` is used to execute pytest
+test suites in the Zephyr test. The following options apply to the pytest harness:
+
+.. _pytest_root:
+
+pytest_root: <list of pytest testpaths> (default pytest)
+    Specify a list of pytest directories, files or subtests that need to be
+    executed when a test scenario begins to run. The default pytest directory is
+    ``pytest``. After the pytest run is finished, Twister will check if
+    the test scenario passed or failed according to the pytest report.
+    As an example, a list of valid pytest roots is presented below:
+
+    .. code-block:: yaml
+
+        harness_config:
+          pytest_root:
+            - "pytest/test_shell_help.py"
+            - "../shell/pytest/test_shell.py"
+            - "/tmp/test_shell.py"
+            - "~/tmp/test_shell.py"
+            - "$ZEPHYR_BASE/samples/subsys/testsuite/pytest/shell/pytest/test_shell.py"
+            - "pytest/test_shell_help.py::test_shell2_sample"  # select pytest subtest
+            - "pytest/test_shell_help.py::test_shell2_sample[param_a]"  # select pytest parametrized subtest
+
+.. _pytest_args:
+
+pytest_args: <list of arguments> (default empty)
+    Specify a list of additional arguments to pass to ``pytest`` e.g.:
+    ``pytest_args: [‘-k=test_method’, ‘--log-level=DEBUG’]``. Note that
+    ``--pytest-args`` can be passed multiple times to pass several arguments
+    to the pytest.
+
+.. _pytest_dut_scope:
+
+pytest_dut_scope: <function|class|module|package|session> (default function)
+    The scope for which ``dut`` and ``shell`` pytest fixtures are shared.
+    If the scope is set to ``function``, DUT is launched for every test case
+    in python script. For ``session`` scope, DUT is launched only once.
+
+
+  The following is an example yaml file with pytest harness_config options,
+  default pytest_root name "pytest" will be used if pytest_root not specified.
+  please refer the examples in samples/subsys/testsuite/pytest/.
+
+  .. code-block:: yaml
+
+      common:
+        harness: pytest
+      tests:
+        pytest.example.directories:
+          harness_config:
+            pytest_root:
+              - pytest_dir1
+              - $ENV_VAR/samples/test/pytest_dir2
+        pytest.example.files_and_subtests:
+          harness_config:
+            pytest_root:
+              - pytest/test_file_1.py
+              - test_file_2.py::test_A
+              - test_file_2.py::test_B[param_a]
+
+Console
+=======
+
+The ``console`` harness tells Twister to parse a test's text output for a
+regex defined in the test's YAML file.
+
+The following options are currently supported:
+
+type: <one_line|multi_line> (required)
+    Depends on the regex string to be matched
+
+regex: <list of regular expressions> (required)
+    Strings with regular expressions to match with the test's output
+    to confirm the test runs as expected.
+
+ordered: <True|False> (default False)
+    Check the regular expression strings in orderly or randomly fashion
+
+record: <recording options> (optional)
+  regex: <list of regular expressions> (required)
+    Regular expressions with named subgroups to match data fields found
+    in the test instance's output lines where it provides some custom data
+    for further analysis. These records will be written into the build
+    directory ``recording.csv`` file as well as ``recording`` property
+    of the test suite object in ``twister.json``.
+
+    With several regular expressions given, each of them will be applied
+    to each output line producing either several different records from
+    the same output line, or different records from different lines,
+    or similar records from different lines.
+
+    The .CSV file will have as many columns as there are fields detected
+    in all records; missing values are filled by empty strings.
+
+    For example, to extract three data fields ``metric``, ``cycles``,
+    ``nanoseconds``:
+
+    .. code-block:: yaml
+
+      record:
+        regex:
+          - "(?P<metric>.*):(?P<cycles>.*) cycles, (?P<nanoseconds>.*) ns"
+
+  merge: <True|False> (default False)
+    Allows to keep only one record in a test instance with all the data
+    fields extracted by the regular expressions. Fields with the same name
+    will be put into lists ordered as their appearance in recordings.
+    It is possible for such multi value fields to have different number
+    of values depending on the regex rules and the test's output.
+
+  as_json: <list of regex subgroup names> (optional)
+    Data fields, extracted by the regular expressions into named subgroups,
+    which will be additionally parsed as JSON encoded strings and written
+    into ``twister.json`` as nested ``recording`` object properties.
+    The corresponding ``recording.csv`` columns will contain JSON strings
+    as-is.
+
+    Using this option, a test log can convey layered data structures
+    passed from the test image for further analysis with summary results,
+    traces, statistics, etc.
+
+    For example, this configuration:
+
+    .. code-block:: yaml
+
+      record:
+        regex: "RECORD:(?P<type>.*):DATA:(?P<metrics>.*)"
+        as_json: [metrics]
+
+    when matched to a test log string:
+
+    .. code-block:: none
+
+      RECORD:jitter_drift:DATA:{"rollovers":0, "mean_us":1000.0}
+
+    will be reported in ``twister.json`` as:
+
+    .. code-block:: json
+
+      "recording":[
+          {
+                "type":"jitter_drift",
+                "metrics":{
+                    "rollovers":0,
+                    "mean_us":1000.0
+                }
+          }
+      ]
+
+Robot
+=====
+
+The ``robot`` harness is used to execute Robot Framework test suites
+in the Renode simulation framework.
+
+robot_testsuite: <robot file path> (default empty)
+    Specify one or more paths to a file containing a Robot Framework test suite to be run.
+
+robot_option: <robot option> (default empty)
+    One or more options to be send to robotframework.
+
+Bsim
+====
+
+Harness ``bsim`` is implemented in limited way - it helps only to copy the
+final executable (``zephyr.exe``) from build directory to BabbleSim's
+``bin`` directory (``${BSIM_OUT_PATH}/bin``).
+
+This action is useful to allow BabbleSim's tests to directly run after.
+By default, the executable file name is (with dots and slashes
+replaced by underscores): ``bs_<platform_name>_<test_path>_<test_scenario_name>``.
+This name can be overridden with the ``bsim_exe_name`` option in
+``harness_config`` section.
+
+bsim_exe_name: <string>
+    If provided, the executable filename when copying to BabbleSim's bin
+    directory, will be ``bs_<platform_name>_<bsim_exe_name>`` instead of the
+    default based on the test path and scenario name.
+
+Shell
+=====
+
+The shell harness is used to execute shell commands and parse the output and utilizes the pytest
+framework and the pytest harness of twister.
+
+The following options apply to the shell harness:
+
+shell_commands: <list of pairs of commands and their expected output> (default empty)
+    Specify a list of shell commands to be executed and their expected output.
+    For example:
+
+    .. code-block:: yaml
+
+        harness_config:
+          shell_commands:
+          - command: "kernel cycles"
+            expected: "cycles: .* hw cycles"
+          - command: "kernel version"
+            expected: "Zephyr version .*"
+          - command: "kernel sleep 100"
+
+
+    If expected output is not provided, the command will be executed and the output
+    will be logged.
+
+shell_commands_file: <string> (default empty)
+    Specify a file containing test parameters to be used in the test.
+    The file should contain a list of commands and their expected output. For example:
+
+    .. code-block:: yaml
+
+      - command: "mpu mtest 1"
+        expected: "The value is: 0x.*"
+      - command: "mpu mtest 2"
+        expected: "The value is: 0x.*"
+
+
+    If no file is specified, the shell harness will use the default file
+    ``test_shell.yml`` in the test directory.
+    ``shell_commands`` will take precedence over ``shell_commands_file``.
+
 Selecting platform scope
 ************************
 
@@ -1388,10 +1496,11 @@ The current status of tests on the quarantine list can also be verified by addin
 ``--quarantine-verify`` to the above argument. This will make twister skip all tests
 which are not on the given list.
 
-A quarantine yaml has to be a sequence of dictionaries. Each dictionary has to have
-``scenarios`` and ``platforms`` entries listing combinations of scenarios and platforms
-to put under quarantine. In addition, an optional entry ``comment`` can be used, where
-some more details can be given (e.g. link to a reported issue). These comments will also
+A quarantine yaml is a sequence of dictionaries. Each dictionary must have
+at least one of the following keys: ``scenarios``, ``platforms``, ``architectures``
+or ``simulations``. A combination of these entries is allowed.
+An optional ``comment`` entry can be used to provide more details
+(e.g., a link to a reported issue). These comments will also
 be added to the output reports.
 
 When quarantining a class of tests or many scenarios in a single testsuite or
@@ -1415,15 +1524,15 @@ An example of entries in a quarantine yaml:
         - .*_cortex_.*
         - native_sim
 
-To exclude a platform, use the following syntax:
-
-.. code-block:: yaml
-
     - platforms:
-      - qemu_x86
-      comment: "broken qemu"
+        - qemu_x86
+      comment: "filter out qemu_x86"
+
+    - architectures:
+        - riscv
 
-Additionally you can quarantine entire architectures or a specific simulator for executing tests.
+    - simulations:
+        - armfvp
 
 Test Configuration
 ******************
diff --git a/doc/develop/toolchains/crosstool_ng.rst b/doc/develop/toolchains/crosstool_ng.rst
deleted file mode 100644
index dc51b9b36fc..00000000000
--- a/doc/develop/toolchains/crosstool_ng.rst
+++ /dev/null
@@ -1,49 +0,0 @@
-.. _toolchain_xtools:
-
-Crosstool-NG (Deprecated)
-#########################
-
-.. warning::
-
-   ``xtools`` toolchain variant is deprecated. The
-   :ref:`cross-compile toolchain variant <other_x_compilers>` should be used
-   when using a custom toolchain built with Crosstool-NG.
-
-You can build toolchains from source code using crosstool-NG.
-
-#. Follow the steps on the crosstool-NG website to `prepare your host
-   <http://crosstool-ng.github.io/docs/os-setup/>`_.
-
-#. Follow the `Zephyr SDK with Crosstool NG instructions
-   <https://github.com/zephyrproject-rtos/sdk-ng/blob/master/README.md>`_ to
-   build your toolchain. Repeat as necessary to build toolchains for multiple
-   target architectures.
-
-   You will need to clone the ``sdk-ng`` repo and run the following command:
-
-   .. code-block:: console
-
-      ./go.sh <arch>
-
-   .. note::
-
-      Currently, only i586 and Arm toolchain builds are verified.
-
-#. :ref:`Set these environment variables <env_vars>`:
-
-   - Set :envvar:`ZEPHYR_TOOLCHAIN_VARIANT` to ``xtools``.
-   - Set :envvar:`XTOOLS_TOOLCHAIN_PATH` to the toolchain build directory.
-
-#. To check that you have set these variables correctly in your current
-   environment, follow these example shell sessions (the
-   :envvar:`XTOOLS_TOOLCHAIN_PATH` values may be different on your system):
-
-   .. code-block:: console
-
-      # Linux, macOS:
-      $ echo $ZEPHYR_TOOLCHAIN_VARIANT
-      xtools
-      $ echo $XTOOLS_TOOLCHAIN_PATH
-      /Volumes/CrossToolNGNew/build/output/
-
-.. _crosstool-ng site: http://crosstool-ng.org
diff --git a/doc/develop/toolchains/iar_arm_toolchain.rst b/doc/develop/toolchains/iar_arm_toolchain.rst
new file mode 100644
index 00000000000..33f5e3795af
--- /dev/null
+++ b/doc/develop/toolchains/iar_arm_toolchain.rst
@@ -0,0 +1,62 @@
+.. _toolchain_iar_arm:
+
+IAR Arm Toolchain
+#################
+
+#. Download and install a release of  `IAR Arm Toolchain`_ (EWARM/CXARM) on your host.
+
+.. note::
+   As of now, a Development version of the IAR build tools for Arm is required to work with Zephyr.
+   It is distributed to selected partners and customers for evaluation. If you are interested in being
+   part of this program, please send a request to the IAR FAE team at fae.emea@iar.com.
+
+#. Make sure you have :ref:`Zephyr SDK <toolchain_zephyr_sdk>` installed on your host.
+
+.. note::
+   A Zephyr SDK is used as a source of tools like device tree compiler (DTC), QEMU, etc… Even though
+   IAR Arm toolchain is used for Zephyr RTOS build, still the GNU preprocessor & GNU objcopy might
+   be used for some steps like device tree preprocessing and .bin file generation.
+
+#. :ref:`Set these environment variables <env_vars>`:
+
+   - Set :envvar:`ZEPHYR_TOOLCHAIN_VARIANT` to ``iar``.
+   - Set :envvar:`IAR_TOOLCHAIN_PATH` to the toolchain installation directory.
+
+#. The IAR Toolchain needs the :envvar:`IAR_LMS_BEARER_TOKEN` environment
+   variable to be set to a valid ``license bearer token``.
+
+For example:
+
+   .. code-block:: bash
+
+      # Linux (default installation path):
+      export IAR_TOOLCHAIN_PATH=/opt/iarsystems/bxarm/arm
+      export ZEPHYR_TOOLCHAIN_VARIANT=iar
+      export IAR_LMS_BEARER_TOKEN="<BEARER-TOKEN>"
+
+   .. code-block:: batch
+
+      # Windows:
+      set IAR_TOOLCHAIN_PATH=c:\<path>\arm
+      set ZEPHYR_TOOLCHAIN_VARIANT=iar
+      set IAR_LMS_BEARER_TOKEN="<BEARER-TOKEN>"
+
+.. note::
+
+   The IAR Toolchain uses ``ilink`` for linking. This is incompatible with Zephyr’s
+   linker script template, which works with GNU ld. Zephyr’s IAR Arm Toolchain depends on
+   Zephyr’s CMake linker script generator, which supports generating icf-files.
+   Basic icf-file support is in place, but there are still areas which are not fully
+   supported by the CMake linker script generator.
+
+.. note::
+
+   The IAR Toolchain uses the GNU Assembler which is distributed with the Zephyr SDK
+   for ``.S-files``.
+
+.. note::
+
+   Some Zephyr subsystems or modules may also contain C or assembly code that relies
+   on GNU intrinsics and have not yet been updated to work fully with ``iar``.
+
+.. _IAR Arm Toolchain: https://www.iar.com/products/architectures/arm/
diff --git a/doc/develop/toolchains/index.rst b/doc/develop/toolchains/index.rst
index 4310e22f19a..e085a1fbe1c 100644
--- a/doc/develop/toolchains/index.rst
+++ b/doc/develop/toolchains/index.rst
@@ -14,9 +14,9 @@ Guides on how to set up toolchains for Zephyr development.
    cadence_xcc.rst
    designware_arc_mwdt.rst
    gnu_arm_embedded.rst
+   iar_arm_toolchain.rst
    intel_oneapi_toolkit.rst
 
-   crosstool_ng.rst
    host.rst
    other_x_compilers.rst
    custom_cmake.rst
diff --git a/doc/develop/tools/img/stm32cube_import_project.webp b/doc/develop/tools/img/stm32cube_import_project.webp
new file mode 100644
index 00000000000..81bbc632cab
Binary files /dev/null and b/doc/develop/tools/img/stm32cube_import_project.webp differ
diff --git a/doc/develop/tools/img/stm32cube_menu_import.webp b/doc/develop/tools/img/stm32cube_menu_import.webp
new file mode 100644
index 00000000000..dc70bd89ecf
Binary files /dev/null and b/doc/develop/tools/img/stm32cube_menu_import.webp differ
diff --git a/doc/develop/tools/stm32cubeide.rst b/doc/develop/tools/stm32cubeide.rst
index 73e160ee1eb..2b1eae3a01c 100644
--- a/doc/develop/tools/stm32cubeide.rst
+++ b/doc/develop/tools/stm32cubeide.rst
@@ -87,6 +87,33 @@ Project Setup
    The project can be run using the :guilabel:`Run` button, as well as debugged
    using the :guilabel:`Debug` button.
 
+Debugging only
+**************
+
+If you only want to use STM32CubeIDE to debug your project you can proceed as follows:
+
+#. First, make sure to compile your project and have the ``zephyr.elf`` available.
+
+#. Run STM32CubeIDE and import your project by going to :menuselection:`File --> Import...`:
+
+   .. figure:: img/stm32cube_menu_import.webp
+      :align: center
+      :alt: Import project
+
+#. Select :menuselection:`C/C++ --> STM32 Cortex-M Executable`, then click :guilabel:`Next`:
+
+   .. figure:: img/stm32cube_import_project.webp
+      :align: center
+      :alt: Import project selection
+
+#. Click on :guilabel:`Browse` to browse to your build folder and select your ``zephyr.elf``.
+
+#. Click on :guilabel:`Select` to select your MCU. If relevant, choose also your CPU and/or core.
+
+#. Click on :guilabel:`Finish`.
+
+#. The project can now be debugged using the :guilabel:`Debug` button.
+
 Troubleshooting
 ***************
 
diff --git a/doc/develop/west/workspaces.rst b/doc/develop/west/workspaces.rst
index 5c182658df9..d3dadc2b369 100644
--- a/doc/develop/west/workspaces.rst
+++ b/doc/develop/west/workspaces.rst
@@ -321,3 +321,25 @@ v2.5.0 and its modules, then add the ``app1`` and ``app2`` projects:
 
 You can also do this "by hand" by copy/pasting :file:`zephyr/west.yml`
 as shown :ref:`above <west-t2>` for the T2 topology, with the same caveats.
+
+.. _workspace-as-git-repo:
+
+Not supported: workspace topdir as .git repository
+**************************************************
+
+Some users have asked for support making the workspace :ref:`topdir
+<west-workspace>` a git repository, like this example:
+
+.. code-block:: none
+
+   my-workspace/                  # workspace topdir
+   ├── .git/                      # puts the entire workspace in a git repository
+   ├── .west/                     # marks the location of the topdir
+   └── [ ... other projects ...]
+
+This is **not** an officially supported topology. As a design decision, west
+assumes that the workspace topdir itself is not a git repository.
+
+You may be able to make something like this "work" for yourself and your own
+goals. However, future versions of west might contain changes which can "break"
+your setup.
diff --git a/doc/develop/west/zephyr-cmds.rst b/doc/develop/west/zephyr-cmds.rst
index 0c665c7f64a..b4ef9532cff 100644
--- a/doc/develop/west/zephyr-cmds.rst
+++ b/doc/develop/west/zephyr-cmds.rst
@@ -219,3 +219,52 @@ You can list all known standard descriptor names using::
 You can print the offset of the descriptors inside the image using::
 
    west bindesc get_offset
+
+Indexing the sources with GNU Global: ``west gtags``
+****************************************************
+
+.. important:: You must install the ``gtags`` and ``global`` programs provided
+               by `GNU Global`_ to use this command.
+
+The ``west gtags`` command lets you create a GNU Global tags file for the entire
+west workspace::
+
+  west gtags
+
+.. _GNU Global: https://www.gnu.org/software/global/
+
+This will create a tags file named ``GTAGS`` in the workspace :ref:`topdir
+<west-workspace>` (it will also create other Global-related metadata files
+named ``GPATH`` and ``GRTAGS`` in the same place).
+
+You can then run the ``global`` command anywhere inside the
+workspace to search for symbol locations using this tags file.
+
+For example, to search for definitions of the ``arch_system_halt()`` function,
+starting from the ``zephyr/drivers`` directory::
+
+  $ cd zephyr/drivers
+  $ global -x arch_system_halt
+  arch_system_halt   65 ../arch/arc/core/fatal.c FUNC_NORETURN void arch_system_halt(unsigned int reason)
+  arch_system_halt  455 ../arch/arm64/core/fatal.c FUNC_NORETURN void arch_system_halt(unsigned int reason)
+  arch_system_halt  137 ../arch/nios2/core/fatal.c FUNC_NORETURN void arch_system_halt(unsigned int reason)
+  arch_system_halt   18 ../arch/posix/core/fatal.c FUNC_NORETURN void arch_system_halt(unsigned int reason)
+  arch_system_halt   17 ../arch/x86/core/fatal.c FUNC_NORETURN void arch_system_halt(unsigned int reason)
+  arch_system_halt  126 ../arch/xtensa/core/fatal.c FUNC_NORETURN void arch_system_halt(unsigned int reason)
+  arch_system_halt   21 ../kernel/fatal.c FUNC_NORETURN __weak void arch_system_halt(unsigned int reason)
+
+This prints the search symbol, the line it is defined on, a relative path to
+the file it is defined in, and the line itself, for all places where the symbol
+is defined.
+
+Additional tips:
+
+- This can also be useful to search for vendor HAL function definitions.
+
+- See the ``global`` command's manual page for more information on how to use
+  this tool.
+
+- You should run ``global``, **not** ``west global``. There is no need for a
+  separate ``west global`` command since ``global`` already searches for the
+  ``GTAGS`` file starting from your current working directory. This is why you
+  need to run ``global`` from inside the workspace.
diff --git a/doc/hardware/arch/arm-scmi.rst b/doc/hardware/arch/arm-scmi.rst
index 65dad1bffce..1055f5d6b89 100644
--- a/doc/hardware/arch/arm-scmi.rst
+++ b/doc/hardware/arch/arm-scmi.rst
@@ -135,9 +135,23 @@ Protocols
 
 Currently, Zephyr has support for the following standard protocols:
 
+	#. **Power domain management**
 	#. **Clock management**
 	#. **Pin Control**
 
+NXP-specific protocols:
+	#. **CPU domain management**
+
+Power domain management
+***********************
+
+This protocol is intended for management of power states of power domains.
+This is done via a set of functions implementing various commands, for
+example, ``POWER_STATE_GET`` and ``POWER_STATE_SET``.
+
+.. note::
+	This driver is vendor-agnostic. As such, it may be used on any
+	system that uses SCMI for power domain management operations.
 
 Clock management protocol
 *************************
@@ -166,6 +180,16 @@ supported command is ``PINCTRL_SETTINGS_CONFIGURE``.
 	call into the SCMI pin control protocol function implementing the
 	``PINCTRL_SETTINGS_CONFIGURE`` command.
 
+NXP - CPU domain management
+***************************
+
+This protocol is intended for management of cpu states.
+This is done via a set of functions implementing various commands, for
+example, ``CPU_SLEEP_MODE_SET``.
+
+.. note::
+	This driver is NXP-specific. As such, it may only be used on NXP
+	system that uses SCMI for cpu domain management operations.
 
 Enabling the SCMI support
 *************************
diff --git a/doc/hardware/arch/arm_cortex_m.rst b/doc/hardware/arch/arm_cortex_m.rst
index 7eef8e7f2f5..4bfb05d8026 100644
--- a/doc/hardware/arch/arm_cortex_m.rst
+++ b/doc/hardware/arch/arm_cortex_m.rst
@@ -55,6 +55,8 @@ Arm Cortex-M implementation variants.
 +---------------------------------+-----------------------------------+-----------------+---------+--------+-----------+--------+---------+------------+------------+
 |                                 | HW-assisted stack limit checking  |        N        |   N     |   N    |    N      |    N   |Y [#f2]_ |     Y      |   Y        |
 +---------------------------------+-----------------------------------+-----------------+---------+--------+-----------+--------+---------+------------+------------+
+|                                 | Privileged Execute Never          |        N        |   N     |   N    |    N      |    N   |    N    |     N      |   Y [#f3]_ |
++---------------------------------+-----------------------------------+-----------------+---------+--------+-----------+--------+---------+------------+------------+
 | HW-assisted null-pointer        |                                   |                 |         |        |           |        |         |            |            |
 | dereference detection           |                                   |        N        |   N     |   Y    |    Y      |    Y   |    Y    |     Y      |   Y        |
 +---------------------------------+-----------------------------------+-----------------+---------+--------+-----------+--------+---------+------------+------------+
@@ -86,6 +88,7 @@ Notes
 
 .. [#f1] SysTick is optional in Cortex-M1
 .. [#f2] Stack limit checking only in Secure builds in Cortex-M23
+.. [#f3] https://developer.arm.com/documentation/107655/100/RTOS-and-Secure-software-design-considerations/Secure-software-development-design-considerations/Security-and-privilege-combination/Using-PXN-bit?lang=en
 
 OS features
 ***********
diff --git a/doc/hardware/arch/risc-v.rst b/doc/hardware/arch/risc-v.rst
index 1484781f658..473b614b44b 100644
--- a/doc/hardware/arch/risc-v.rst
+++ b/doc/hardware/arch/risc-v.rst
@@ -32,6 +32,8 @@ combinations.
 SMP support
 ***********
 
-SMP is supported on RISC-V, but currently only on Qemu platforms. In
-order to test the SMP support, one can use ``qemu_riscv32_smp`` or
-``qemu_riscv64_smp`` boards.
+SMP is supported on RISC-V for both QEMU-virtualized and hardware-based
+platforms. In order to test the SMP support, one can use
+:zephyr:board:`qemu_riscv32` or :zephyr:board:`qemu_riscv64` for QEMU-based
+platforms, or :zephyr:board:`beaglev_fire` or :zephyr:board:`mpfs_icicle` for
+hardware-based platforms.
diff --git a/doc/hardware/arch/semihost.rst b/doc/hardware/arch/semihost.rst
index f8bc8610adf..bbfce075725 100644
--- a/doc/hardware/arch/semihost.rst
+++ b/doc/hardware/arch/semihost.rst
@@ -52,7 +52,7 @@ directory of the running process.
    semihost_close(fd);
 
 Additional Functionality
-########################
+************************
 
 Additional functionality is available by running semihosting instructions
 directly with :c:func:`semihost_exec` with one of the instructions defined
diff --git a/doc/hardware/cache/config.rst b/doc/hardware/cache/config.rst
new file mode 100644
index 00000000000..2c913972e11
--- /dev/null
+++ b/doc/hardware/cache/config.rst
@@ -0,0 +1,70 @@
+.. _cache_config:
+
+Cache Control Configuration
+###########################
+
+This is a high-level guide to Zephyr's cache interface and Kconfig options related to
+cache controllers. See :ref:`cache_api` for API reference material.
+
+Zephyr has different Kconfig options to control how the cache controller is
+implemented and controlled.
+
+* :kconfig:option:`CONFIG_CPU_HAS_DCACHE` /
+  :kconfig:option:`CONFIG_CPU_HAS_ICACHE`: these hidden options should be
+  selected at SoC / platform level when the CPU actually supports a data or
+  instruction cache. The cache controller can be in the core or can be an
+  external cache controller for which a driver is provided.
+
+  These options have the goal to document an available hardware feature and
+  should be set whether we plan to support and use the cache control in Zephyr
+  or not.
+
+* :kconfig:option:`CONFIG_DCACHE` / :kconfig:option:`CONFIG_ICACHE`: these
+  options must be selected when support for data or instruction cache is
+  present and working in zephyr. Note that if these options are disabled,
+  caching may still be enabled depending on the hardware defaults.
+
+  All the code paths related to cache control must be conditionally enabled
+  depending on these symbols. When the symbol is set the cache is considered
+  enabled and used.
+
+  These symbols say nothing about the actual API interface exposed to the user.
+  For example a platform using the data cache can enable the
+  :kconfig:option:`CONFIG_DCACHE` symbol and use some HAL exported function in
+  some platform-specific code to enable and manage the d-cache.
+
+* :kconfig:option:`CONFIG_CACHE_MANAGEMENT`: this option must be selected when
+  the cache operations are exposed to the user through a standard API (see
+  :ref:`cache_api`).
+
+  When this option is enabled we assume that all the cache functions are
+  implemented in the architectural code or in an external cache controller
+  driver.
+
+* :kconfig:option:`CONFIG_MEM_ATTR`: this option allows the user to
+  specify (using :ref:`memory region attributes<mem_mgmt_api>`) a fixed region
+  in memory that will have caching disabled once the kernel has initialized.
+
+* :kconfig:option:`CONFIG_NOCACHE_MEMORY`: this option allows the user to
+  specify individual global variables as uncached using ``__nocache``. This will
+  instruct the linker to place any marked variables into a special ``nocache``
+  region in memory and the MPU driver will configure that region as uncached.
+
+* :kconfig:option:`CONFIG_ARCH_CACHE`/:kconfig:option:`CONFIG_EXTERNAL_CACHE`:
+  mutually exclusive options for :kconfig:option:`CACHE_TYPE` used to define
+  whether the cache operations are implemented at arch level or using an
+  external cache controller with a provided driver.
+
+  * :kconfig:option:`CONFIG_ARCH_CACHE`: the cache API is implemented by the
+    arch code
+
+  * :kconfig:option:`CONFIG_EXTERNAL_CACHE`: the cache API is implemented by a
+    driver that supports the external cache controller. In this case the driver
+    must be located as usual in the :file:`drivers/cache/` directory
+
+.. _cache_api:
+
+Cache API
+*********
+
+.. doxygengroup:: cache_interface
diff --git a/doc/hardware/cache/index.rst b/doc/hardware/cache/index.rst
index 9e1ab1890ef..2dd6c40a499 100644
--- a/doc/hardware/cache/index.rst
+++ b/doc/hardware/cache/index.rst
@@ -1,70 +1,10 @@
-.. _cache_config:
+.. _cache:
 
-Cache Control Configuration
-###########################
+Caching
+#######
 
-This is a high-level guide to Zephyr's cache interface and Kconfig options related to
-cache controllers. See :ref:`cache_api` for API reference material.
+.. toctree::
+   :maxdepth: 1
 
-Zephyr has different Kconfig options to control how the cache controller is
-implemented and controlled.
-
-* :kconfig:option:`CONFIG_CPU_HAS_DCACHE` /
-  :kconfig:option:`CONFIG_CPU_HAS_ICACHE`: these hidden options should be
-  selected at SoC / platform level when the CPU actually supports a data or
-  instruction cache. The cache controller can be in the core or can be an
-  external cache controller for which a driver is provided.
-
-  These options have the goal to document an available hardware feature and
-  should be set whether we plan to support and use the cache control in Zephyr
-  or not.
-
-* :kconfig:option:`CONFIG_DCACHE` / :kconfig:option:`CONFIG_ICACHE`: these
-  options must be selected when support for data or instruction cache is
-  present and working in zephyr. Note that if these options are disabled,
-  caching may still be enabled depending on the hardware defaults.
-
-  All the code paths related to cache control must be conditionally enabled
-  depending on these symbols. When the symbol is set the cache is considered
-  enabled and used.
-
-  These symbols say nothing about the actual API interface exposed to the user.
-  For example a platform using the data cache can enable the
-  :kconfig:option:`CONFIG_DCACHE` symbol and use some HAL exported function in
-  some platform-specific code to enable and manage the d-cache.
-
-* :kconfig:option:`CONFIG_CACHE_MANAGEMENT`: this option must be selected when
-  the cache operations are exposed to the user through a standard API (see
-  :ref:`cache_api`).
-
-  When this option is enabled we assume that all the cache functions are
-  implemented in the architectural code or in an external cache controller
-  driver.
-
-* :kconfig:option:`CONFIG_MEM_ATTR`: this option allows the user to
-  specify (using :ref:`memory region attributes<mem_mgmt_api>`) a fixed region
-  in memory that will have caching disabled once the kernel has initialized.
-
-* :kconfig:option:`CONFIG_NOCACHE_MEMORY`: this option allows the user to
-  specify individual global variables as uncached using ``__nocache``. This will
-  instruct the linker to place any marked variables into a special ``nocache``
-  region in memory and the MPU driver will configure that region as uncached.
-
-* :kconfig:option:`CONFIG_ARCH_CACHE`/:kconfig:option:`CONFIG_EXTERNAL_CACHE`:
-  mutually exclusive options for :kconfig:option:`CACHE_TYPE` used to define
-  whether the cache operations are implemented at arch level or using an
-  external cache controller with a provided driver.
-
-  * :kconfig:option:`CONFIG_ARCH_CACHE`: the cache API is implemented by the
-    arch code
-
-  * :kconfig:option:`CONFIG_EXTERNAL_CACHE`: the cache API is implemented by a
-    driver that supports the external cache controller. In this case the driver
-    must be located as usual in the :file:`drivers/cache/` directory
-
-.. _cache_api:
-
-Cache API
-#########
-
-.. doxygengroup:: cache_interface
+   config.rst
+   guide.rst
diff --git a/doc/hardware/peripherals/can/controller.rst b/doc/hardware/peripherals/can/controller.rst
index e8710201349..99cda14a361 100644
--- a/doc/hardware/peripherals/can/controller.rst
+++ b/doc/hardware/peripherals/can/controller.rst
@@ -70,7 +70,7 @@ in case, abort their transmission.
 This effectively gives lower number identifiers priority over higher number
 identifiers.
 
-Filters are used to whitelist identifiers that are of interest for the specific
+Filters are used to allowlist identifiers that are of interest for the specific
 node. An identifier that doesn't match any filter is ignored.
 Filters can either match exactly or a specified part of the identifier.
 This method is called masking.
diff --git a/doc/hardware/peripherals/i3c.rst b/doc/hardware/peripherals/i3c.rst
index 476c23fcdaa..c2882efc825 100644
--- a/doc/hardware/peripherals/i3c.rst
+++ b/doc/hardware/peripherals/i3c.rst
@@ -347,7 +347,6 @@ Configuration Options
 Related configuration options:
 
 * :kconfig:option:`CONFIG_I3C`
-* :kconfig:option:`CONFIG_I3C_USE_GROUP_ADDR`
 * :kconfig:option:`CONFIG_I3C_USE_IBI`
 * :kconfig:option:`CONFIG_I3C_IBI_MAX_PAYLOAD_SIZE`
 * :kconfig:option:`CONFIG_I3C_CONTROLLER_INIT_PRIORITY`
diff --git a/doc/hardware/peripherals/index.rst b/doc/hardware/peripherals/index.rst
index 2a7405aced2..acb12942c23 100644
--- a/doc/hardware/peripherals/index.rst
+++ b/doc/hardware/peripherals/index.rst
@@ -38,7 +38,6 @@ Peripherals
    i3c.rst
    i2c.rst
    ipm.rst
-   kscan.rst
    led.rst
    mdio.rst
    mipi_dbi.rst
diff --git a/doc/hardware/peripherals/kscan.rst b/doc/hardware/peripherals/kscan.rst
deleted file mode 100644
index 1ac9e808f99..00000000000
--- a/doc/hardware/peripherals/kscan.rst
+++ /dev/null
@@ -1,35 +0,0 @@
-.. _kscan_api:
-
-
-Keyboard Scan
-#############
-
-.. note:: Kscan APIs are deprecated, any driver and applications should be
-   ported over to use :ref:`input` instead.
-
-Overview
-********
-
-The kscan driver (keyboard scan matrix) is used for detecting a key press in a
-connected matrix keyboard or any device with buttons such as joysticks.
-Typically, matrix keyboards are implemented using a two-dimensional
-configuration in order to sense several keys.  This allows interfacing to
-many keys through fewer physical pins. Keyboard matrix
-drivers read the rows while applying power through the columns one at a time
-with the purpose of detecting key events.
-There is no correlation between the physical and electrical layout of keys.
-For, example, the physical layout may be one array of 16 or fewer keys, which
-may be electrically connected to a 4 x 4 array. In addition, key values are
-defined by a keymap provided by the keyboard manufacturer.
-
-Configuration Options
-*********************
-
-Related configuration options:
-
-* :kconfig:option:`CONFIG_KSCAN`
-
-API Reference
-*************
-
-.. doxygengroup:: kscan_interface
diff --git a/doc/hardware/peripherals/rtc.rst b/doc/hardware/peripherals/rtc.rst
index ae69df0b446..e4837f6f9a9 100644
--- a/doc/hardware/peripherals/rtc.rst
+++ b/doc/hardware/peripherals/rtc.rst
@@ -30,20 +30,61 @@ RTCs usually contain one or more alarms which can be configured to
 trigger at a given time. These alarms are commonly used to wake up the
 system from a low power state.
 
-History of RTCs in Zephyr
-*************************
+Devicetree bindings
+*******************
 
-RTCs have been supported before this API was created, using the
-:ref:`counter_api` API. The unix timestamp was used to convert
-between broken-down time and the unix timestamp within the RTC
-drivers, which internally used the broken-down time representation.
+RTC bindings must include the ``rtc-device.yaml`` binding, which
+includes the ``base.yaml`` binding and the required ``alarms-count``
+property.
 
-The disadvantages of this approach were that hardware counters could
-not be set to a specific count, requiring all RTCs to use device
-specific APIs to set the time, converting from unix time to
-broken-down time, unnecessarily in some cases, and some common
-features missing, like input clock calibration and the update
-callback.
+.. code-block:: yaml
+
+   include: rtc-device.yaml
+
+Device driver design
+********************
+
+Driver init
+===========
+
+RTCs are never powered off by the system. On init, drivers should
+expect the RTC is either:
+
+* Powered, configured, and running.
+* Powered, unconfigured, and stopped.
+
+On init, drivers shall ensure the RTC is configured correctly, while
+preserving the time, alarms, and running status.
+
+Time is set by calling :c:func:`rtc_set_time`, at which point the
+RTC will start running. Alarms pending status is cleared by
+:c:func:`rtc_alarm_is_pending` or by an alarm callback resulting
+from :c:func:`rtc_alarm_set_callback`.
+
+GPIO routed interrupts
+======================
+
+RTCs with connected interrupt output pins shall configure and enable
+them on init. The host may enable and disable interrupts for its
+GPIOs, but RTC interrupt output pins must remain enabled.
+
+This ensures consistent behavior between internally and externally
+connected RTCs, and allows for system wakeup through GPIO on any
+enabled RTC event like alarms or update.
+
+.. note::
+
+   RTCs with unconnected interrupt output pins are not allowed to
+   periodically poll the RTC to emulate it being connected.
+   :c:func:`rtc_alarm_set_callback` and
+   :c:func:`rtc_update_set_callback` shall return ``-ENOTSUP`` in
+   this case.
+
+Clock output
+============
+
+If supported, the clock output configuration is defined in the
+devicetree. The output is configured by the driver on init.
 
 Configuration Options
 *********************
@@ -147,3 +188,18 @@ application is reset.
 The emulated RTC device driver is built for the compatible
 :dtcompatible:`zephyr,rtc-emul` and will be included if :kconfig:option:`CONFIG_RTC`
 is selected.
+
+History of RTCs in Zephyr
+*************************
+
+RTCs have been supported before this API was created, using the
+:ref:`counter_api` API. The unix timestamp was used to convert
+between broken-down time and the unix timestamp within the RTC
+drivers, which internally used the broken-down time representation.
+
+The disadvantages of this approach were that hardware counters could
+not be set to a specific count, requiring all RTCs to use device
+specific APIs to set the time, converting from unix time to
+broken-down time, unnecessarily in some cases, and some common
+features missing, like input clock calibration and the update
+callback.
diff --git a/doc/hardware/peripherals/sdhc.rst b/doc/hardware/peripherals/sdhc.rst
index 55667862b37..4f881127f61 100644
--- a/doc/hardware/peripherals/sdhc.rst
+++ b/doc/hardware/peripherals/sdhc.rst
@@ -1,30 +1,31 @@
 .. _sdhc_api:
 
-
-Secure Digital High Capacity (SDHC)
+Secure Digital (SD card) interface
 ###################################
 
-The SDHC api offers a generic interface for interacting with an SD host
-controller device. It is used by the SD subsystem, and is not intended to be
-directly used by the application
+Zephyr can communicate with an attached SD card either using a system's native
+SD card interface or over SPI (Serial Peripheral Interface). Some devices can
+also communicate with MMC (MultiMediaCard) devices.
+
+Applications can use Zephyr's :ref:`the disk access API <disk_access_api>`
+to use SD cards as storage devices, or Zephyr's SD card subsystem to
+directly read from and write to a card.
 
-Basic Operation
-***************
+SD Host Controller (SDHC)
+*************************
 
-SD Host Controller
-==================
+An SD host controller (SDHC) is a device capable of sending commands to an
+SD card. These commands can be sent using a system's native SD card interface,
+or over SPI.
 
-An SD host controller is a device capable of sending SD commands to an attached
-SD card. These commands can be sent using the native SD protocol, or over SPI.
-Some SD host controllers are also capable of communicating with MMC devices.
-The SDHC api is designed to provide a generic way to send commands to and
-interact with attached SD devices.
+Applications should generally not use the SD host controller API directly,
+instead they should use Zephyr's SD card subsystem.
 
 Requests
 ========
 
-The core of the SDHC api is the :c:func:`sdhc_request` api. Requests contain a
-:c:struct:`sdhc_command` command structure, and an optional
+The core of the SD host controller (SDHC) API is the :c:func:`sdhc_request` API.
+Requests contain a :c:struct:`sdhc_command` command structure, and an optional
 :c:struct:`sdhc_data` data structure. The caller may check the return code,
 or the ``response`` field of the SD command structure to determine if the
 SDHC request succeeded. The data structure allows the caller to specify a
@@ -35,7 +36,7 @@ command opcode provided.
 Host Controller I/O
 ===================
 
-The :c:func:`sdhc_set_io` api allows the user to change I/O settings of the SD
+The :c:func:`sdhc_set_io` API allows the user to change I/O settings of the SD
 host controller, such as clock frequency, I/O voltage, and card power. Not all
 controllers will support applying all I/O settings. For example, SPI mode
 controllers typically cannot toggle power to the SD card.
diff --git a/doc/hardware/peripherals/sensor/triggers.rst b/doc/hardware/peripherals/sensor/triggers.rst
index 6dd78701032..c4a5c9536a2 100644
--- a/doc/hardware/peripherals/sensor/triggers.rst
+++ b/doc/hardware/peripherals/sensor/triggers.rst
@@ -5,7 +5,7 @@ Sensor Triggers
 
 :dfn:`Triggers`, enumerated in :c:enum:`sensor_trigger_type`, are sensor
 generated events. Typically sensors allow setting up these events to cause
-digital line signaling for easy capture by a micro controller. The events can
+digital line signaling for easy capture by a microcontroller. The events can
 then commonly be inspected by reading registers to determine which event caused
 the digital line signaling to occur.
 
diff --git a/doc/hardware/peripherals/stepper.rst b/doc/hardware/peripherals/stepper.rst
index 3b24198a461..16d103421dd 100644
--- a/doc/hardware/peripherals/stepper.rst
+++ b/doc/hardware/peripherals/stepper.rst
@@ -12,15 +12,16 @@ Configure Stepper Driver
   and :c:func:`stepper_get_micro_step_res`.
 - Configure **reference position** in microsteps using :c:func:`stepper_set_reference_position`
   and :c:func:`stepper_get_actual_position`.
-- Set **max velocity** in micro-steps per second using :c:func:`stepper_set_max_velocity`
+- Set **step interval** in nanoseconds between steps using :c:func:`stepper_set_microstep_interval`
 - **Enable** the stepper driver using :c:func:`stepper_enable`.
+- **Disable** the stepper driver using :c:func:`stepper_disable`.
 
 Control Stepper
 ===============
 
 - **Move by** +/- micro-steps also known as **relative movement** using :c:func:`stepper_move_by`.
 - **Move to** a specific position also known as **absolute movement** using :c:func:`stepper_move_to`.
-- Run continuously with a **constant velocity** in a specific direction until
+- Run continuously with a **constant step interval** in a specific direction until
   a stop is detected using :c:func:`stepper_run`.
 - Check if the stepper is **moving** using :c:func:`stepper_is_moving`.
 - Register an **event callback** using :c:func:`stepper_set_event_callback`.
@@ -37,7 +38,7 @@ be used in a boards devicetree to configure a stepper driver to its initial stat
 See examples in:
 
 - :dtcompatible:`zephyr,gpio-stepper`
-- :dtcompatible:`adi,tmc5041`
+- :dtcompatible:`adi,tmc50xx`
 
 Discord
 =======
@@ -47,6 +48,45 @@ is open to all.
 
 .. _stepper-api-reference:
 
+Stepper API Test Suite
+======================
+
+The stepper API test suite provides a set of tests that can be used to verify the functionality of
+stepper drivers.
+
+.. zephyr-app-commands::
+   :zephyr-app: tests/drivers/stepper/stepper_api
+   :board: <board>
+   :west-args: --extra-dtc-overlay <path/to/board.overlay>
+   :goals: build flash
+
+Sample Output
+=============
+
+Below is a snippet of the test output for the tmc50xx stepper driver. Since
+:c:func:`stepper_set_microstep_interval` is not implemented by the driver the corresponding tests
+have been skipped.
+
+.. code-block:: console
+
+   ===================================================================
+   TESTSUITE stepper succeeded
+
+   ------ TESTSUITE SUMMARY START ------
+
+   SUITE PASS - 100.00% [stepper]: pass = 4, fail = 0, skip = 2, total = 6 duration = 0.069 seconds
+    - PASS - [stepper.test_actual_position] duration = 0.016 seconds
+    - PASS - [stepper.test_get_micro_step_res] duration = 0.013 seconds
+    - SKIP - [stepper.test_set_micro_step_interval_invalid_zero] duration = 0.007 seconds
+    - PASS - [stepper.test_set_micro_step_res_incorrect] duration = 0.010 seconds
+    - PASS - [stepper.test_stop] duration = 0.016 seconds
+    - SKIP - [stepper.test_target_position_w_fixed_step_interval] duration = 0.007 seconds
+
+   ------ TESTSUITE SUMMARY END ------
+
+   ===================================================================
+   PROJECT EXECUTION SUCCESSFUL
+
 API Reference
 *************
 
diff --git a/doc/hardware/porting/arch.rst b/doc/hardware/porting/arch.rst
index 339b6642a25..7c3e4ff9975 100644
--- a/doc/hardware/porting/arch.rst
+++ b/doc/hardware/porting/arch.rst
@@ -83,7 +83,7 @@ Some examples of architecture-specific steps that have to be taken:
   in an unknown or broken state.
 * Initialize a board-specific watchdog on Cortex-M3/4.
 * Switch stacks from MSP to PSP on Cortex-M.
-* Use a different approach than calling into _Swap() on Cortex-M to prevent
+* Use a different approach than calling into z_swap() on Cortex-M to prevent
   race conditions.
 * Setup FIRQ and regular IRQ handling on ARCv2.
 
@@ -149,8 +149,8 @@ parameter.
   parameter from the separate table. This approach is commonly used in the ARC
   and ARM architectures via the :kconfig:option:`CONFIG_GEN_ISR_TABLES` implementation.
   You can find examples of the stubs by looking at :code:`_interrupt_enter()` in
-  x86, :code:`_IntExit()` in ARM, :code:`_isr_wrapper()` in ARM, or the full
-  implementation description for ARC in :zephyr_file:`arch/arc/core/isr_wrapper.S`.
+  x86, :code:`_isr_wrapper()` in ARM, or the full implementation description for
+  ARC in :zephyr_file:`arch/arc/core/isr_wrapper.S`.
 
 Each architecture also has to implement primitives for interrupt control:
 
@@ -176,15 +176,16 @@ Thread Context Switching
 ************************
 
 Multi-threading is the basic purpose to have a kernel at all. Zephyr supports
-two types of threads: preemptible and cooperative.
+two types of threads: preemptible and cooperative. The rules for determining
+the next thread to schedule are handled by the kernel. However, it is up to
+the architecture port to implement the method of the context switch itself.
 
-Two crucial concepts when writing an architecture port are the following:
-
-* Cooperative threads run at a higher priority than preemptible ones, and
-  always preempt them.
-
-* After handling an interrupt, if a cooperative thread was interrupted, the
-  kernel always goes back to running that thread, since it is not preemptible.
+Zephyr provides two mutually exclusive interfaces for context switching. The
+preferred interface to use is :code:`arch_switch` which is selected when
+:kconfig:option:`CONFIG_USE_SWITCH` is enabled. The alternative interface is
+:code:`arch_swap`--selected when :kconfig:option:`CONFIG_USE_SWITCH`
+is disabled. When porting to a new architecture, only one of these needs to
+implemented; however, for SMP platforms it must be :code:`arch_switch`.
 
 A context switch can happen in several circumstances:
 
@@ -204,9 +205,6 @@ A context switch can happen in several circumstances:
 
 Therefore, the context switching must thus be able to handle all these cases.
 
-The kernel keeps the next thread to run in a "cache", and thus the context
-switching code only has to fetch from that cache to select which thread to run.
-
 There are two types of context switches: :dfn:`cooperative` and :dfn:`preemptive`.
 
 * A *cooperative* context switch happens when a thread willfully gives the
@@ -228,58 +226,47 @@ There are two types of context switches: :dfn:`cooperative` and :dfn:`preemptive
   running thread.
 
 A cooperative context switch is always done by having a thread call the
-:code:`_Swap()` kernel internal symbol. When :code:`_Swap` is called, the
-kernel logic knows that a context switch has to happen: :code:`_Swap` does not
-check to see if a context switch must happen. Rather, :code:`_Swap` decides
-what thread to context switch in. :code:`_Swap` is called by the kernel logic
-when an object being operated on is unavailable, and some thread
-yielding/sleeping primitives.
+internal kernel routine :code:`z_swap` (or one of its variants). This in turn
+will call either :code:`arch_switch` or :code:`arch_swap` as appropriate.
+When these are called, no checks are done to determine if the context switch is
+to happen--the context switch must happen.
 
 .. note::
 
-  On x86 and Nios2, :code:`_Swap` is generic enough and the architecture
-  flexible enough that :code:`_Swap` can be called when exiting an interrupt
-  to provoke the context switch. This should not be taken as a rule, since
-  neither the ARM Cortex-M or ARCv2 port do this.
+  On x86 and Nios2, :code:`arch_swap` is generic enough and the architecture
+  flexible enough that it can be called when exiting an interrupt to provoke
+  the context switch. This should not be taken as a rule, since
+  neither the ARM Cortex-M nor ARCv2 port do this.
 
-Since :code:`_Swap` is cooperative, the caller-saved registers from the ABI are
+Since :code:`z_swap` is cooperative, the caller-saved registers from the ABI are
 already on the stack. There is no need to save them in the k_thread structure.
 
 A context switch can also be performed preemptively. This happens upon exiting
 an ISR, in the kernel interrupt exit stub:
 
 * :code:`_interrupt_enter` on x86 after the handler is called.
-* :code:`_IntExit` on ARM.
+* :code:`z_arm_exc_exit` and :code:`z_arm_int_exit` on ARM.
 * :code:`_firq_exit` and :code:`_rirq_exit` on ARCv2.
 
-In this case, the context switch must only be invoked when the interrupted
-thread was preemptible, not when it was a cooperative one, and only when the
-current interrupt is not nested.
+The decision logic to invoke the context switch is simple and is only performed
+when exiting a non-nested interrupt:
+
+When :kconfig:option:`CONFIG_USE_SWITCH` is enabled ...
 
-The kernel also has the concept of "locking the scheduler". This is a concept
-similar to locking the interrupts, but lighter-weight since interrupts can
-still occur. If a thread has locked the scheduler, is it temporarily
-non-preemptible.
+* The interrupt exit code shall call :c:func:`z_get_next_switch_handle`, and
+  return to the thread context identified by the returned switch handle
 
-So, the decision logic to invoke the context switch when exiting an interrupt
-is simple:
+When :kconfig:option:`CONFIG_USE_SWITCH` is not enabled ...
 
-* If the interrupted thread is not preemptible, do not invoke it.
-* Else, fetch the cached thread from the ready queue, and:
+* The interrupt exit code shall fetch the cached thread from the ready queue, and:
 
   * If the cached thread is not the current thread, invoke the context switch.
-  * Else, do not invoke it.
+  * Otherwise do not invoke it.
 
 This is simple, but crucial: if this is not implemented correctly, the kernel
 will not function as intended and will experience bizarre crashes, mostly due
 to stack corruption.
 
-.. note::
-
-  If running a coop-only system, i.e. if :kconfig:option:`CONFIG_NUM_PREEMPT_PRIORITIES`
-  is 0, no preemptive context switch ever happens. The interrupt code can be
-  optimized to not take any scheduling decision when this is the case.
-
 Thread Creation and Termination
 *******************************
 
diff --git a/doc/hardware/porting/board_porting.rst b/doc/hardware/porting/board_porting.rst
index 5d84c937c9d..37ec26f172a 100644
--- a/doc/hardware/porting/board_porting.rst
+++ b/doc/hardware/porting/board_porting.rst
@@ -93,13 +93,13 @@ the :term:`SoC series` and :term:`SoC family` levels are not always used.
    +--------------------------------------------+--------------------------+-------------+--------------------+--------------------+----------------+----------------------+
    | :term:`board name`                         | :term:`board qualifiers` | :term:`SoC` | :term:`SoC Series` | :term:`SoC family` | CPU core       | :term:`architecture` |
    +============================================+==========================+=============+====================+====================+================+======================+
-   | :ref:`nrf52dk <nrf52dk_nrf52832>`          | nrf52832                 | nRF52832    | nRF52              | Nordic nRF         | Arm Cortex-M4  | ARMv7-M              |
+   | :zephyr:board:`nrf52dk`                    | nrf52832                 | nRF52832    | nRF52              | Nordic nRF         | Arm Cortex-M4  | ARMv7-M              |
    +--------------------------------------------+--------------------------+-------------+--------------------+--------------------+----------------+----------------------+
    | :zephyr:board:`frdm_k64f <frdm_k64f>`      | mk64f12                  | MK64F12     | Kinetis K6x        | NXP Kinetis        | Arm Cortex-M4  | ARMv7-M              |
    +--------------------------------------------+--------------------------+-------------+--------------------+--------------------+----------------+----------------------+
    | :zephyr:board:`rv32m1_vega <rv32m1_vega>`  | openisa_rv32m1/ri5cy     | RV32M1      | (Not used)         | (Not used)         | RI5CY          | RISC-V RV32          |
    +--------------------------------------------+--------------------------+-------------+--------------------+--------------------+----------------+----------------------+
-   | :ref:`nrf5340dk <nrf5340dk_nrf5340>`       | nrf5340/cpuapp           | nRF5340     | nRF53              | Nordic nRF         | Arm Cortex-M33 | ARMv8-M              |
+   | :zephyr:board:`nrf5340dk`                  | nrf5340/cpuapp           | nRF5340     | nRF53              | Nordic nRF         | Arm Cortex-M33 | ARMv8-M              |
    |                                            +--------------------------+-------------+--------------------+--------------------+----------------+----------------------+
    |                                            | nrf5340/cpunet           | nRF5340     | nRF53              | Nordic nRF         | Arm Cortex-M33 | ARMv8-M              |
    +--------------------------------------------+--------------------------+-------------+--------------------+--------------------+----------------+----------------------+
@@ -168,7 +168,7 @@ The board qualifiers ``nrf5340/cpuapp/ns`` can be read as:
   Zephyr denoting a non-secure build for boards supporting :ref:`tfm`.
 
 Not all SoCs define CPU clusters or variants. For example a simple board
-like the :ref:`thingy52_nrf52832` contains a single SoC with no CPU clusters and
+like the :zephyr:board:`thingy52` contains a single SoC with no CPU clusters and
 no variants.
 For ``thingy52`` the board target ``thingy52/nrf52832`` can be read as:
 
@@ -281,7 +281,7 @@ The mandatory files are:
 #. :file:`plank_<qualifiers>.dts`: a hardware description
    in :ref:`devicetree <dt-guide>` format. This declares your SoC, connectors,
    and any other hardware components such as LEDs, buttons, sensors, or
-   communication peripherals (USB, BLE controller, etc).
+   communication peripherals (USB, Bluetooth controller, etc).
 
 #. :file:`Kconfig.plank`: the base software configuration for selecting SoC and
    other board and SoC related settings. Kconfig settings outside of the board
@@ -651,7 +651,7 @@ while porting.
   using the ``zephyr,console`` chosen node in the devicetree.
   Development boards with a built-in debug adapter or USB-to-UART adapter should
   by default configure and use the UART controller connected to that adapter.
-  For boards like :ref:`nRF52840 Dongle <nrf52840dongle_nrf52840>`, that do not
+  For boards like :zephyr:board:`nrf52840dongle`, that do not
   have a debug adapter, but a USB device controller, there is a common
   :zephyr_file:`Kconfig file <boards/common/usb/Kconfig.cdc_acm_serial.defconfig>`
   that must be included in the board's Kconfig.defconfig file and
diff --git a/doc/kernel/drivers/index.rst b/doc/kernel/drivers/index.rst
index 07069942557..762ddb94b28 100644
--- a/doc/kernel/drivers/index.rst
+++ b/doc/kernel/drivers/index.rst
@@ -366,7 +366,7 @@ initialization levels:
 
 Within each initialization level you may specify a priority level, relative to
 other devices in the same initialization level. The priority level is specified
-as an integer value in the range 0 to 99; lower values indicate earlier
+as an integer value in the range 0 to 999; lower values indicate earlier
 initialization.  The priority level must be a decimal integer literal without
 leading zeroes or sign (e.g. 32), or an equivalent symbolic name (e.g.
 ``\#define MY_INIT_PRIO 32``); symbolic expressions are *not* permitted (e.g.
diff --git a/doc/kernel/services/data_passing/pipes.rst b/doc/kernel/services/data_passing/pipes.rst
index b3130687db5..2a8c1ed0bd0 100644
--- a/doc/kernel/services/data_passing/pipes.rst
+++ b/doc/kernel/services/data_passing/pipes.rst
@@ -4,8 +4,8 @@ Pipes
 #####
 
 A :dfn:`pipe` is a kernel object that allows a thread to send a byte stream
-to another thread. Pipes can be used to synchronously transfer chunks of data
-in whole or in part.
+to another thread. Pipes enable efficient inter-thread communication and can
+be used to synchronously transfer chunks of data in whole or in part.
 
 .. contents::
     :local:
@@ -14,192 +14,179 @@ in whole or in part.
 Concepts
 ********
 
-The pipe can be configured with a ring buffer which holds data that has been
-sent but not yet received; alternatively, the pipe may have no ring buffer.
-
-Any number of pipes can be defined (limited only by available RAM). Each pipe is
-referenced by its memory address.
+Any number of pipes can be defined, limited only by available RAM. Each pipe
+is referenced by its memory address.
 
 A pipe has the following key property:
 
-* A **size** that indicates the size of the pipe's ring buffer. Note that a
+* A **size** that indicates the capacity of the pipe's ring buffer. Note that a
   size of zero defines a pipe with no ring buffer.
 
-A pipe must be initialized before it can be used. The pipe is initially empty.
-
-Data is synchronously **sent** either in whole or in part to a pipe by a
-thread. If the specified minimum number of bytes can not be immediately
-satisfied, then the operation will either fail immediately or attempt to send
-as many bytes as possible and then pend in the hope that the send can be
-completed later. Accepted data is either copied to the pipe's ring buffer
-or directly to the waiting reader(s).
-
-Data is synchronously **received** from a pipe by a thread. If the specified
-minimum number of bytes can not be immediately satisfied, then the operation
-will either fail immediately or attempt to receive as many bytes as possible
-and then pend in the hope that the receive can be completed later. Accepted
-data is either copied from the pipe's ring buffer or directly from the
-waiting sender(s).
-
-Data may also be **flushed** from a pipe by a thread. Flushing can be performed
-either on the entire pipe or on only its ring buffer. Flushing the entire pipe
-is equivalent to reading all the information in the ring buffer **and** waiting
-to be written into a giant temporary buffer which is then discarded. Flushing
-the ring buffer is equivalent to reading **only** the data in the ring buffer
-into a temporary buffer which is then discarded. Flushing the ring buffer does
-not guarantee that the ring buffer will stay empty; flushing it may allow a
-pended writer to fill the ring buffer.
-
-.. note::
-    Flushing does not in practice allocate or use additional buffers.
-
-.. note::
-    The kernel does allow for an ISR to flush a pipe from an ISR. It also
-    allows it to send/receive data to/from one provided it does not attempt
-    to wait for space/data.
+A pipe must be initialized before it can be used. When initialized, the pipe
+is empty.
+
+Threads interact with the pipe as follows:
+
+- **Writing**: Data is synchronously written, either in whole or in part, to
+  a pipe by a thread. Accepted data is either copied directly to the waiting
+  reader(s) or to the pipe's ring buffer. If the ring buffer is full or simply
+  absent, the operation blocks until sufficient space becomes available or
+  the specified timeout expires.
+
+- **Reading**: Data is synchronously read, either in whole or in part, from a
+  pipe by a thread. Accepted data is either copied from the pipe's ring buffer
+  or directly from the waiting sender(s). If the ring buffer is empty or simply
+  absent, the operation blocks until data becomes available or the specified
+  timeout expires.
+
+- **Resetting**: A thread can reset a pipe, which resets its internal state and
+  ends all pending read and write operations with an error code.
+
+Pipes are well-suited for scenarios like producer-consumer patterns or
+streaming data between threads.
 
 Implementation
 **************
 
-A pipe is defined using a variable of type :c:struct:`k_pipe` and an
-optional character buffer of type ``unsigned char``. It must then be
-initialized by calling :c:func:`k_pipe_init`.
-
-The following code defines and initializes an empty pipe that has a ring
-buffer capable of holding 100 bytes and is aligned to a 4-byte boundary.
+A pipe is defined using a variable of type :c:struct:`k_pipe` and a
+byte buffer. The pipe must then be initialized by calling :c:func:`k_pipe_init`.
 
+The following code defines and initializes an empty pipe with a ring buffer
+capable of holding 100 bytes, aligned to a 4-byte boundary:
 
 .. code-block:: c
 
-    unsigned char __aligned(4) my_ring_buffer[100];
+    uint8_t __aligned(4) my_ring_buffer[100];
     struct k_pipe my_pipe;
 
     k_pipe_init(&my_pipe, my_ring_buffer, sizeof(my_ring_buffer));
 
-Alternatively, a pipe can be defined and initialized at compile time by
-calling :c:macro:`K_PIPE_DEFINE`.
-
-The following code has the same effect as the code segment above. Observe
-that macro defines both the pipe and its ring buffer.
+Alternatively, a pipe can be defined and initialized at compile time using
+the :c:macro:`K_PIPE_DEFINE` macro, which defines both the pipe and its
+ring buffer:
 
 .. code-block:: c
 
     K_PIPE_DEFINE(my_pipe, 100, 4);
 
+This has the same effect as the code above.
+
+When no ring buffer is used, the buffer pointer argument should be NULL and
+the size argument should be 0.
+
 Writing to a Pipe
 =================
 
-Data is added to a pipe by calling :c:func:`k_pipe_put`.
+Data is added to a pipe by calling :c:func:`k_pipe_write`.
 
-The following code builds on the example above, and uses the pipe to pass
-data from a producing thread to one or more consuming threads. If the pipe's
-ring buffer fills up because the consumers can't keep up, the producing thread
-waits for a specified amount of time.
+The following example demonstrates using a pipe to send data from a producer
+thread to one or more consumer threads. If the pipe's ring buffer fills up,
+the producer thread waits for a specified amount of time.
 
 .. code-block:: c
 
-    struct message_header {
-        ...
-    };
-
-    void producer_thread(void)
-    {
-        unsigned char *data;
-        size_t total_size;
-        size_t bytes_written;
-        int    rc;
-        ...
-
-        while (1) {
-            /* Craft message to send in the pipe */
-            data = ...;
-            total_size = ...;
-
-            /* send data to the consumers */
-            rc = k_pipe_put(&my_pipe, data, total_size, &bytes_written,
-                            sizeof(struct message_header), K_NO_WAIT);
-
-            if (rc < 0) {
-                /* Incomplete message header sent */
-                ...
-            } else if (bytes_written < total_size) {
-                /* Some of the data was sent */
-                ...
-            } else {
-                /* All data sent */
-                ...
-            }
-        }
-    }
+   struct message_header {
+       size_t num_data_bytes; /* Example field */
+       ...
+   };
+
+   void producer_thread(void)
+   {
+       int rc;
+       uint8_t *data;
+       size_t total_size;
+       size_t bytes_written;
+
+       while (1) {
+           /* Craft message to send in the pipe */
+           make_message(data, &total_size);
+           bytes_written = 0;
+
+           /* Write data to the pipe, handling partial writes */
+           while (bytes_written < total_size) {
+               rc = k_pipe_write(&my_pipe, &data[bytes_written], total_size - bytes_written, K_NO_WAIT);
+
+               if (rc < 0) {
+                   /* Error occurred */
+                   ...
+                   break;
+               } else {
+                   /* Partial or full write succeeded; adjust for next iteration */
+                   bytes_written += rc;
+               }
+           }
+
+           /* Reset bytes_written for the next message */
+           bytes_written = 0;
+           ...
+       }
+   }
 
 Reading from a Pipe
 ===================
 
-Data is read from the pipe by calling :c:func:`k_pipe_get`.
-
-The following code builds on the example above, and uses the pipe to
-process data items generated by one or more producing threads.
-
-.. code-block:: c
-
-    void consumer_thread(void)
-    {
-        unsigned char buffer[120];
-        size_t   bytes_read;
-        struct message_header  *header = (struct message_header *)buffer;
-
-        while (1) {
-            rc = k_pipe_get(&my_pipe, buffer, sizeof(buffer), &bytes_read,
-                            sizeof(*header), K_MSEC(100));
-
-            if ((rc < 0) || (bytes_read < sizeof (*header))) {
-                /* Incomplete message header received */
-                ...
-            } else if (header->num_data_bytes + sizeof(*header) > bytes_read) {
-                /* Only some data was received */
-                ...
-            } else {
-                /* All data was received */
-                ...
-            }
-        }
-    }
-
-Use a pipe to send streams of data between threads.
-
-.. note::
-    A pipe can be used to transfer long streams of data if desired.  However
-    it is often preferable to send pointers to large data items to avoid
-    copying the data.
-
-Flushing a Pipe's Buffer
-========================
+Data is retrieved from the pipe by calling :c:func:`k_pipe_read`.
 
-Data is flushed from the pipe's ring buffer by calling
-:c:func:`k_pipe_buffer_flush`.
-
-The following code builds on the examples above, and flushes the pipe's
-buffer.
+The following example builds on the producer thread example above. It shows
+a consumer thread that processes data generated by the producer.
 
 .. code-block:: c
 
-    void monitor_thread(void)
-    {
-        while (1) {
-            ...
-            /* Pipe buffer contains stale data. Flush it. */
-            k_pipe_buffer_flush(&my_pipe);
-            ...
-        }
-    }
-
-Flushing a Pipe
-===============
-
-All data in the pipe is flushed by calling :c:func:`k_pipe_flush`.
-
-The following code builds on the examples above, and flushes all the
-data in the pipe.
+   struct message_header {
+       size_t num_data_bytes; /* Example field */
+       ...
+   };
+
+   void consumer_thread(void)
+   {
+       int rc;
+       uint8_t buffer[128];
+       size_t bytes_read = 0;
+       struct message_header *header = (struct message_header *)buffer;
+
+       while (1) {
+           /* Step 1: Read the message header */
+           bytes_read = 0;
+      read_header:
+           while (bytes_read < sizeof(*header)) {
+               rc = k_pipe_read(&my_pipe, &buffer[bytes_read], sizeof(*header) - bytes_read, &bytes_read, K_NO_WAIT);
+
+               if (rc < 0) {
+                   /* Error occurred */
+                   ...
+                   goto read_header;
+               }
+
+               /* Adjust for partial reads */
+               bytes_read += rc;
+           }
+
+           /* Step 2: Read the message body */
+           bytes_read = 0;
+           while (bytes_read < header->num_data_bytes) {
+               rc = k_pipe_read(&my_pipe, &buffer[sizeof(*header) + bytes_read], header->num_data_bytes - bytes_read, K_NO_WAIT);
+
+               if (rc < 0) {
+                   /* Error occurred */
+                   ...
+                   goto read_header;
+               }
+
+               /* Adjust for partial reads */
+               bytes_read += rc;
+           }
+           /* Successfully received the complete message */
+       }
+   }
+
+Resetting a Pipe
+================
+
+The pipe can be reset by calling :c:func:`k_pipe_reset`. Resetting a pipe
+resets its internal state and ends all pending operations with an error code.
+
+The following example demonstrates resetting a pipe in response to a critical
+error:
 
 .. code-block:: c
 
@@ -207,31 +194,21 @@ data in the pipe.
     {
         while (1) {
             ...
-            /* Critical error detected. Flush the entire pipe to reset it. */
-            k_pipe_flush(&my_pipe);
+            /* Critical error detected: reset the entire pipe to reset it. */
+            k_pipe_reset(&my_pipe);
             ...
         }
     }
 
-
-Suggested uses
+Suggested Uses
 **************
 
-Use a pipe to send streams of data between threads.
-
-.. note::
-    A pipe can be used to transfer long streams of data if desired. However it
-    is often preferable to send pointers to large data items to avoid copying
-    the data. Copying large data items will negatively impact interrupt latency
-    as a spinlock is held while copying that data.
-
-
-Configuration Options
-*********************
-
-Related configuration options:
+Pipes are useful for sending streams of data between threads. Typical
+applications include:
 
-* :kconfig:option:`CONFIG_PIPES`
+- Implementing producer-consumer patterns.
+- Streaming logs or packets between threads.
+- Handling variable-length message passing in real-time systems.
 
 API Reference
 *************
diff --git a/doc/kernel/services/interrupts.rst b/doc/kernel/services/interrupts.rst
index 044e9ddea1f..f598d4ba838 100644
--- a/doc/kernel/services/interrupts.rst
+++ b/doc/kernel/services/interrupts.rst
@@ -325,9 +325,10 @@ for some low-latency use-cases. Specifically:
   potentially make a scheduling decision.
 
 Zephyr supports so-called 'direct' interrupts, which are installed via
-:c:macro:`IRQ_DIRECT_CONNECT`. These direct interrupts have some special
-implementation requirements and a reduced feature set; see the definition
-of :c:macro:`IRQ_DIRECT_CONNECT` for details.
+:c:macro:`IRQ_DIRECT_CONNECT` and whose handlers are declared using
+:c:macro:`ISR_DIRECT_DECLARE`. These direct interrupts have some special
+implementation requirements and a reduced feature set; see the definitions
+of :c:macro:`IRQ_DIRECT_CONNECT` and :c:macro:`ISR_DIRECT_DECLARE` for details.
 
 The following code demonstrates a direct ISR:
 
diff --git a/doc/kernel/services/other/fatal.rst b/doc/kernel/services/other/fatal.rst
index f46fdaef1e6..c2b006ba377 100644
--- a/doc/kernel/services/other/fatal.rst
+++ b/doc/kernel/services/other/fatal.rst
@@ -120,8 +120,8 @@ discouraged.
 Build Assertions
 ================
 
-Zephyr provides two macros for performing build-time assertion checks.
-These are evaluated completely at compile-time, and are always checked.
+Zephyr provides a macro for performing build-time assertion checks.
+It is evaluated completely at compile-time and always checked.
 
 BUILD_ASSERT()
 --------------
diff --git a/doc/kernel/services/scheduling/index.rst b/doc/kernel/services/scheduling/index.rst
index 4c8b445b245..28319539582 100644
--- a/doc/kernel/services/scheduling/index.rst
+++ b/doc/kernel/services/scheduling/index.rst
@@ -13,8 +13,10 @@ The scheduler determines which thread is allowed to execute
 at any point in time; this thread is known as the **current thread**.
 
 There are various points in time when the scheduler is given an
-opportunity to change the identity of the current thread.  These points
-are called **reschedule points**. Some potential reschedule points are:
+opportunity to change the identity of the current thread, meaning
+when the scheduler switches the CPU's execution from one thread
+to another. These points are called **reschedule points**.
+Some potential reschedule points are:
 
 - transition of a thread from running state to a suspended or waiting
   state, for example by :c:func:`k_sem_take` or :c:func:`k_sleep`.
diff --git a/doc/kernel/services/threads/index.rst b/doc/kernel/services/threads/index.rst
index b9dd1fb3ba8..1edc7593cff 100644
--- a/doc/kernel/services/threads/index.rst
+++ b/doc/kernel/services/threads/index.rst
@@ -189,8 +189,12 @@ require their regions to be of some power of two in size, and aligned to its
 own size.
 
 Because of this, portable code can't simply pass an arbitrary character buffer
-to :c:func:`k_thread_create`. Special macros exist to instantiate stacks,
-prefixed with ``K_KERNEL_STACK`` and ``K_THREAD_STACK``.
+to :c:func:`k_thread_create`. Special macros exist to instantiate stacks
+statically, prefixed with ``K_KERNEL_STACK`` and ``K_THREAD_STACK``.
+
+Additionally, stacks may be instantiated dynamically using
+:c:func:`k_thread_stack_alloc` and subsequently freed with
+:c:func:`k_thread_stack_free`.
 
 Kernel-only Stacks
 ==================
@@ -411,8 +415,9 @@ Spawning a Thread
 A thread is spawned by defining its stack area and its thread control block,
 and then calling :c:func:`k_thread_create`.
 
-The stack area must be defined using :c:macro:`K_THREAD_STACK_DEFINE` or
-:c:macro:`K_KERNEL_STACK_DEFINE` to ensure it is properly set up in memory.
+The stack area may be statically allocated using
+:c:macro:`K_THREAD_STACK_DEFINE` or :c:macro:`K_KERNEL_STACK_DEFINE` to ensure
+it is properly set up in memory.
 
 The size parameter for the stack must be one of three values:
 
@@ -426,6 +431,9 @@ The size parameter for the stack must be one of three values:
   macros, the return value of :c:macro:`K_KERNEL_STACK_SIZEOF()` for that
   object.
 
+Alternatively, the stack area may be dynamically allocated using
+:c:func:`k_thread_stack_alloc` and freed using :c:func:`k_thread_stack_free`.
+
 The thread spawning function returns its thread id, which can be used
 to reference the thread.
 
@@ -470,6 +478,25 @@ The following code has the same effect as the code segment above.
    thread immediately. The corresponding parameter to :c:macro:`K_THREAD_DEFINE`
    is a duration in integral milliseconds, so the equivalent argument is 0.
 
+The following code dynamically allocates a thread stack, waits until the thread
+has joined, and then frees the dynamically allocated thread stack.
+
+.. code-block:: c
+
+    extern void my_entry_point(void *, void *, void *);
+
+    k_tid_t my_tid;
+    void *my_stack_area;
+
+    my_stack_area = k_thread_stack_alloc(CONFIG_DYNAMIC_THREAD_STACK_SIZE);
+    my_tid = k_thread_create(&my_thread_data, my_stack_area,
+                              CONFIG_DYNAMIC_THREAD_STACK_SIZE,
+                              my_entry_point,
+                              NULL, NULL, NULL,
+                              MY_PRIORITY, 0, K_NO_WAIT);
+    k_thread_join(my_tid, K_FOREVER);
+    k_thread_stack_free(my_stack_area);
+
 User Mode Constraints
 ---------------------
 
diff --git a/doc/kernel/services/threads/priorities.svg b/doc/kernel/services/threads/priorities.svg
index 2e9a85d4ad5..00475e6e982 100644
--- a/doc/kernel/services/threads/priorities.svg
+++ b/doc/kernel/services/threads/priorities.svg
@@ -1,4 +1,4 @@
 <?xml version="1.0" encoding="UTF-8"?>
-<!-- Do not edit this file with editors other than diagrams.net -->
+<!-- Do not edit this file with editors other than draw.io -->
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\ No newline at end of file
diff --git a/doc/kernel/services/threads/system_threads.rst b/doc/kernel/services/threads/system_threads.rst
index 74da3c0a033..b46ab4d3c83 100644
--- a/doc/kernel/services/threads/system_threads.rst
+++ b/doc/kernel/services/threads/system_threads.rst
@@ -35,9 +35,6 @@ The kernel spawns the following system threads:
     and never terminates.
 
     The idle thread always uses the lowest configured thread priority.
-    If this makes it a cooperative thread, the idle thread repeatedly
-    yields the CPU to allow the application's other threads to run when
-    they need to.
 
     The idle thread is an essential thread, which means a fatal system error
     is raised if the thread aborts.
diff --git a/doc/project/dev_env_and_tools.rst b/doc/project/dev_env_and_tools.rst
index 2095192d4d5..9485d152050 100644
--- a/doc/project/dev_env_and_tools.rst
+++ b/doc/project/dev_env_and_tools.rst
@@ -65,55 +65,45 @@ Categories/Labels
 -----------------
 
 Hotfix
-++++++
+  Any change that is a fix to an issue that blocks developers from doing their
+  daily work, for example CI breakage, Test breakage, Minor documentation fixes
+  that impact the user experience.
 
-Any change that is a fix to an issue that blocks developers from doing their
-daily work, for example CI breakage, Test breakage, Minor documentation fixes
-that impact the user experience.
-
-Such fixes can be merged at any time after they have passed CI checks. Depending
-on the fix, severity, and availability of someone to review them (other than the
-author) they can be merged with justification without review by one of the
-project owners.
+  Such fixes can be merged at any time after they have passed CI checks. Depending
+  on the fix, severity, and availability of someone to review them (other than the
+  author) they can be merged with justification without review by one of the
+  project owners.
 
 Trivial
-+++++++
-
-Trivial changes are those that appear obvious enough and do not require maintainer or code-owner
-involvement. Such changes should not change the logic or the design of a
-subsystem or component. For example a trivial change can be:
+  Trivial changes are those that appear obvious enough and do not require maintainer or code-owner
+  involvement. Such changes should not change the logic or the design of a
+  subsystem or component. For example a trivial change can be:
 
-- Documentation changes
-- Configuration changes
-- Minor Build System tweaks
-- Minor optimization to code logic without changing the logic
-- Test changes and fixes
-- Sample modifications to support additional configuration or boards etc.
+  - Documentation changes
+  - Configuration changes
+  - Minor Build System tweaks
+  - Minor optimization to code logic without changing the logic
+  - Test changes and fixes
+  - Sample modifications to support additional configuration or boards etc.
 
 Maintainer
-+++++++++++
-
-Any changes that touch the logic or the original design of a subsystem or
-component will need to be reviewed by the code owner or the designated subsystem
-maintainer. If the code changes is initiated by a contributor or developer other
-than the owner the pull request needs to be assigned to the code owner who will
-have to drive the pull request to a mergeable state by giving feedback to the
-author and asking for more reviews from other developers.
+  Any changes that touch the logic or the original design of a subsystem or
+  component will need to be reviewed by the code owner or the designated subsystem
+  maintainer. If the code changes is initiated by a contributor or developer other
+  than the owner the pull request needs to be assigned to the code owner who will
+  have to drive the pull request to a mergeable state by giving feedback to the
+  author and asking for more reviews from other developers.
 
 Security
-+++++++++++
-
-Changes that appear to have an impact to the overall security of the system need
-to be reviewed by a security expert from the security working group.
+  Changes that appear to have an impact to the overall security of the system need
+  to be reviewed by a security expert from the security working group.
 
 TSC and Working Groups
-++++++++++++++++++++++
-
-Changes that introduce new features or functionality or change the way the
-overall system works need to be reviewed by the TSC or the responsible Working
-Group. For example for :ref:`breaking API changes <breaking_api_changes>`, the
-proposal needs to be presented in the Architecture meeting so that the relevant
-stakeholders are made aware of the change.
+  Changes that introduce new features or functionality or change the way the
+  overall system works need to be reviewed by the TSC or the responsible Working
+  Group. For example for :ref:`breaking API changes <breaking_api_changes>`, the
+  proposal needs to be presented in the Architecture meeting so that the relevant
+  stakeholders are made aware of the change.
 
 A Pull-Request should have an Assignee
 =======================================
diff --git a/doc/project/index.rst b/doc/project/index.rst
index dda70ca575f..84ade4c32fa 100644
--- a/doc/project/index.rst
+++ b/doc/project/index.rst
@@ -13,7 +13,6 @@ Project and Governance
    release_process
    proposals
    code_flow
-   modifying_contributions.rst
    dev_env_and_tools
    issues
    communication
diff --git a/doc/project/project_roles.rst b/doc/project/project_roles.rst
index 02760af95f0..bccf3bc2c4c 100644
--- a/doc/project/project_roles.rst
+++ b/doc/project/project_roles.rst
@@ -71,6 +71,16 @@ Contributor change requests or approval on pull requests are not counted with
 respect to accepting and merging a pull request. However, Contributors comments
 and requested changes should still be considered by the pull request author.
 
+Zephyr Contributor Badge
+++++++++++++++++++++++++
+
+When your first contribution to the Zephyr project gets merged, you'll become eligible to claim your
+Zephyr Contributor Badge. This digital badge can be displayed on your website, blog, social media
+profile, etc. It will allow you to showcase your involvement in the Zephyr project and help raise
+its awareness.
+
+You may apply for your Contributor Badge by filling out the `Zephyr Contributor Badge form`_.
+
 .. _collaborator:
 
 Collaborator
@@ -350,6 +360,7 @@ Release Activity
 Merge Criteria
 ++++++++++++++
 
+* All :ref:`pr_requirements` must be met.
 * Minimal of 2 approvals, including an approval by the designated assignee.
 * Pull requests should be reviewed by at least a maintainer or collaborator of
   each affected area; Unless the changes to a given area are considered trivial
@@ -402,3 +413,6 @@ Merge Criteria
   * Coding Guidelines
   * Static Analysis (Coverity)
   * Documentation coverage (APIs)
+
+
+.. _Zephyr Contributor Badge form: https://forms.gle/oCw9iAPLhUsHTapc8
diff --git a/doc/releases/index.rst b/doc/releases/index.rst
index a8ad05df530..a9c6d812554 100644
--- a/doc/releases/index.rst
+++ b/doc/releases/index.rst
@@ -55,17 +55,26 @@ For more information, see  :ref:`Security Vulnerability Reporting <reporting>`.
 Supported Releases
 ******************
 
-+-----------------+----------------+---------------+
-| Release         | Release date   | EOL           |
-+=================+================+===============+
-| `Zephyr 2.7.6`_ | 2024-03-01     | 2025-01-26    |
-+-----------------+----------------+---------------+
-| `Zephyr 3.7.0`_ | 2024-07-26     | 2027-01-26    |
-+-----------------+----------------+---------------+
-| `Zephyr 4.0.0`_ | 2024-11-15     | 2025-07-18    |
-+-----------------+----------------+---------------+
-
-As of 2022-01-01, LTS1 (1.14.x) is not supported and has reached end of life (EOL).
++------------------------+----------------+---------------+
+| Release                | Release date   | EOL           |
++========================+================+===============+
+| `Zephyr 4.1.0`_        | 2025-03-07     | 2025-11-14    |
++------------------------+----------------+---------------+
+| `Zephyr 4.0.0`_        | 2024-11-15     | 2025-07-18    |
++------------------------+----------------+---------------+
+| `Zephyr 3.7.0 (LTS3)`_ | 2024-07-26     | 2029-07-27    |
++------------------------+----------------+---------------+
+
+Previous LTS
+************
+
++-------------------------+---------------+
+| Release                 | EOL           |
++=========================+===============+
+| `Zephyr 2.7.6 (LTS2)`_  | 2025-01-26    |
++-------------------------+---------------+
+| `Zephyr 1.14.1 (LTS1)`_ | 2022-01-01    |
++-------------------------+---------------+
 
 Release Notes
 *************
@@ -76,14 +85,18 @@ Changes that require the user to modify their own application to support the new
 release may be mentioned in the release notes, but the details regarding *what*
 needs to be changed are to be detailed in the release's migration guide.
 
+Updates to the release notes post release cycle is permitted but limited to
+style, typographical fixes and to upmerge the notes from maintenance release
+branches with the sole purpose of keeping the latest documentation consistent
+with the changes in the project.
+
 .. toctree::
    :maxdepth: 1
    :glob:
    :reversed:
 
-   release-notes-2.7
    release-notes-3.7
-   release-notes-4.[0-1]
+   release-notes-4.[0-2]
 
 Migration Guides
 ****************
@@ -115,7 +128,7 @@ to be able to understand the context of the change.
    :reversed:
 
    migration-guide-3.[6-7]
-   migration-guide-4.[0-1]
+   migration-guide-4.[0-2]
 
 End-of-life Releases
 ********************
@@ -131,6 +144,8 @@ Release notes and migration guides for end-of-life releases of Zephyr RTOS can b
 
 .. _`GitHub repository`: https://github.com/zephyrproject-rtos/zephyr
 .. _`GitHub tagged releases`: https://github.com/zephyrproject-rtos/zephyr/tags
-.. _`Zephyr 2.7.6`: https://docs.zephyrproject.org/2.7.6/
-.. _`Zephyr 3.7.0`: https://docs.zephyrproject.org/3.7.0/
+.. _`Zephyr 1.14.1 (LTS1)`: https://docs.zephyrproject.org/1.14.1/
+.. _`Zephyr 2.7.6 (LTS2)`: https://docs.zephyrproject.org/2.7.6/
+.. _`Zephyr 3.7.0 (LTS3)`: https://docs.zephyrproject.org/3.7.0/
 .. _`Zephyr 4.0.0`: https://docs.zephyrproject.org/4.0.0/
+.. _`Zephyr 4.1.0`: https://docs.zephyrproject.org/4.1.0/
diff --git a/doc/releases/migration-guide-3.6.rst b/doc/releases/migration-guide-3.6.rst
index 99d24896103..3c0e42b0284 100644
--- a/doc/releases/migration-guide-3.6.rst
+++ b/doc/releases/migration-guide-3.6.rst
@@ -241,7 +241,7 @@ Bluetooth HCI
 Controller Area Network (CAN)
 =============================
 
-* The native Linux SocketCAN driver, which can now be used in both :ref:`native_posix<native_posix>`
+* The native Linux SocketCAN driver, which can now be used in both ``native_posix``
   and :ref:`native_sim<native_sim>` with or without an embedded C-library, has been renamed to
   reflect this:
 
diff --git a/doc/releases/migration-guide-4.0.rst b/doc/releases/migration-guide-4.0.rst
index b6866438735..4a7b500c187 100644
--- a/doc/releases/migration-guide-4.0.rst
+++ b/doc/releases/migration-guide-4.0.rst
@@ -33,7 +33,7 @@ Kernel
 Boards
 ******
 
-* :ref:`native_posix<native_posix>` has been deprecated in favour of
+* ``native_posix`` has been deprecated in favour of
   :ref:`native_sim<native_sim>` (:github:`76898`).
 * Nordic nRF53 and nRF91 based boards can use the common devicetree overlays in ``dts/common/nordic``
   to define default flash and ram partitioning based on TF-M.
@@ -505,7 +505,7 @@ Networking
   will take network interface pointer as a first parameter. (:github:`77987`)
 
 * To facilitate use outside of the networking subsystem, the network buffer header file was renamed
-  from :zephyr_file:`include/zephyr/net/buf.h` to :zephyr_file:`include/zephyr/net_buf.h` and the
+  from ``include/zephyr/net/buf.h`` to :zephyr_file:`include/zephyr/net_buf.h` and the
   implementation moved to :zephyr_file:`lib/net_buf/`. (:github:`78009`)
 
 * The ``work_q`` parameter to ``NET_SOCKET_SERVICE_SYNC_DEFINE`` and
diff --git a/doc/releases/migration-guide-4.1.rst b/doc/releases/migration-guide-4.1.rst
index ab6355ed77d..8be63d19540 100644
--- a/doc/releases/migration-guide-4.1.rst
+++ b/doc/releases/migration-guide-4.1.rst
@@ -1,9 +1,14 @@
 :orphan:
 
+..
+  See
+  https://docs.zephyrproject.org/latest/releases/index.html#migration-guides
+  for details of what is supposed to go into this document.
+
 .. _migration_4.1:
 
-Migration guide to Zephyr v4.1.0 (Working Draft)
-################################################
+Migration guide to Zephyr v4.1.0
+################################
 
 This document describes the changes required when migrating your application from Zephyr v4.0.0 to
 Zephyr v4.1.0.
@@ -18,6 +23,15 @@ the :ref:`release notes<zephyr_4.1>`.
 Build System
 ************
 
+* Support for the build type feature which was deprecated in Zephyr 3.6 has been removed,
+  :ref:`application-file-suffixes`/:ref:`sysbuild_file_suffixes` has replaced this.
+
+* Sysbuild
+
+  * The Kconfig ``SB_CONFIG_MCUBOOT_MODE_SWAP_WITHOUT_SCRATCH`` has been deprecated and replaced
+    with ``SB_CONFIG_MCUBOOT_MODE_SWAP_USING_MOVE``, applications should be updated to select this
+    new symbol if they were selecting the old symbol.
+
 BOSSA Runner
 ============
 
@@ -27,6 +41,45 @@ perform a full erase, pass the ``--erase`` option when executing ``west flash``.
 Kernel
 ******
 
+
+k_pipe API
+==========
+
+The k_pipe API has been reworked and the API used in ``CONFIG_PIPES`` is now deprecated.
+The k_pipe API is enabled by default when ``CONFIG_MULTITHREADING`` is set.
+Function renames and modifications:
+
+.. list-table::
+   :header-rows: 1
+
+   * - Old API
+     - New API
+     - Changes
+   * - ``k_pipe_put(..)``
+     - ``k_pipe_write(..)``
+     - Removed ``min_xfer`` parameter (partial transfers based on thresholds are no longer supported)
+       ``bytes_written`` is now the return value
+   * - ``k_pipe_get(..)``
+     - ``k_pipe_read(..)``
+     - Removed ``min_xfer`` parameter (partial transfers based on thresholds are no longer supported)
+       ``bytes_read`` is now the return value
+   * - ``k_pipe_flush(..)`` & ``k_pipe_buffer_flush(..)``
+     - ``k_pipe_reset(..)``
+     - Reset the pipe, discarding all data in the pipe, non blocking.
+   * - ``k_pipe_alloc_init(..)``, ``k_pipe_cleanup(..)``
+     - **Removed**
+     - Dynamic allocation of pipes is no longer supported
+   * - ``k_pipe_read_avail(..)``, ``k_pipe_write_avail(..)``
+     - **Removed**
+     - Querying the number of bytes in the pipe is no longer supported
+   * - None
+     - ``k_pipe_close(..)``
+     - Close a pipe, waking up all pending readers and writers with an error code. No further
+       reading or writing is allowed on the pipe. The pipe can be re-opened by calling
+       ``k_pipe_init(..)`` again. **Note**, all data in the pipe is available to readers until the
+       pipe is emptied.
+
+
 Security
 ********
 
@@ -53,6 +106,10 @@ Boards
   always erase only the sectors of the external flash used by the new firmware,
   and the ``nrfutil`` one would always erase the whole external flash.
 
+* CAN1 and USART1 have been disabled on the ``stm32f4_disco``, because of
+  conflicting pinctrl on I2C1, which is now used to control the audio codec
+  connected to the audio jack output.
+
 Devicetree
 **********
 
@@ -80,6 +137,9 @@ STM32
   as it was introduced earlier.
   The Kconfig method for configuration is now removed.
 
+* ADC properties ``st,adc-sequencer`` and ``st,adc-clock-source`` now uses
+  string values instead of integer values.
+
 Modules
 *******
 
@@ -121,17 +181,31 @@ Device Drivers and Devicetree
   The :c:macro:`DEVICE_API()` macro should be used by out-of-tree driver implementations for
   all the upstream driver classes.
 
-* The :c:func:`video_buffer_alloc` and :c:func:`video_buffer_aligned_alloc` functions in the
-  video API now take an additional timeout parameter.
-
 ADC
 ===
 
 * Renamed the ``compatible`` from ``nxp,kinetis-adc12`` to :dtcompatible:`nxp,adc12`.
 
+Clock
+=====
+* Renamed the devicetree property ``freqs_mhz`` to ``freqs-mhz``.
+* Renamed the devicetree property ``cg_reg`` to ``cg-reg``.
+* Renamed the devicetree property ``pll_ctrl_reg`` to ``pll-ctrl-reg``.
+
+Counter
+=======
+
+* Renamed the devicetree property ``primary_source`` to ``primary-source``.
+* Renamed the devicetree property ``secondary_source`` to ``secondary-source``.
+* Renamed the devicetree property ``filter_count`` to ``filter-count``.
+* Renamed the devicetree property ``filter_period`` to ``filter-period``.
+
 Controller Area Network (CAN)
 =============================
 
+* Renamed the :dtcompatible:`infineon,xmc4xxx-can-node` devicetree property ``clock_div8`` to
+  ``clock-div8`` (:github:`83782`).
+
 Display
 =======
 
@@ -157,6 +231,14 @@ Display
         ...
     };
 
+* Renamed the devicetree propertys ``pclk_pol`` and ``data_cmd-gpios``
+  to ``pclk-pol`` and ``data-cmd-gpios``.
+
+DAC
+===
+
+* Renamed the devicetree properties ``voltage_reference`` and ``power_down_mode``
+  to ``voltage-reference`` and ``power-down-mode``.
 
 Enhanced Serial Peripheral Interface (eSPI)
 ===========================================
@@ -170,17 +252,64 @@ Entropy
   processor needs to get random data before BT is fully enabled.
   (:github:`79931`)
 
+Ethernet
+========
+
+* Deprecated eth_mcux driver was removed.
+* Silabs gecko ethernet changes:
+
+  * Renamed the devicetree property ``location-phy_mdc`` to ``location-phy-mdc``.
+  * Renamed the devicetree property ``location-phy_mdio`` to ``location-phy-mdio``.
+  * Renamed the devicetree property ``location-rmii_refclk`` to ``location-phy-refclk``.
+  * Renamed the devicetree property ``location-rmii_crs_dv`` to ``location-phy-crs-dv``.
+  * Renamed the devicetree property ``location-rmii_txd0`` to ``location-phy-txd0``.
+  * Renamed the devicetree property ``location-rmii_txd1`` to ``location-phy-txd1``.
+  * Renamed the devicetree property ``location-rmii_tx_en`` to ``location-phy-tx-en``.
+  * Renamed the devicetree property ``location-rmii_rxd0`` to ``location-phy-rxd0``.
+  * Renamed the devicetree property ``location-rmii_rxd1`` to ``location-phy-rxd1``.
+  * Renamed the devicetree property ``location-rmii_rx_er`` to ``location-phy-rx-er``.
+  * Renamed the devicetree property ``location-phy_pwr_enable`` to ``location-phy-pwr-enable``.
+  * Renamed the devicetree property ``location-phy_reset`` to ``location-phy-reset``.
+  * Renamed the devicetree property ``location-phy_interrupt`` to ``location-phy-interrupt``.
+
 GNSS
 ====
 
+GPIO
+====
+
+* Renamed the device tree property ``pin_mask`` to ``pin-mask``.
+* Renamed the device tree property ``pinmux_mask`` to ``pinmux-mask``.
+* Renamed the device tree property ``vbatts_pins`` to ``vbatts-pins``.
+* Renamed the device tree property ``bit_per_gpio`` to ``bit-per-gpio``.
+* Renamed the device tree property ``off_val`` to ``off-val``.
+* Renamed the device tree property ``on_val`` to ``on-val``.
+* Renamed the ``compatible`` from ``ti,ads114s0x-gpio`` to :dtcompatible:`ti,ads1x4s0x-gpio`.
+
+HWSPINLOCK
+==========
+
+* Renamed the DeviceTree property ``num_locks`` to ``num-locks``.
+
 I2C
 ===
 
 * Renamed the ``compatible`` from ``nxp,imx-lpi2c`` to :dtcompatible:`nxp,lpi2c`.
+* Renamed the device tree property ``port_sel`` to ``port-sel```.
+
+I2S
+===
+
+* Renamed the device tree property from ``fifo_depth`` to ``fifo-depth``.
 
 Input
 =====
 
+LED
+===
+
+* Renamed the device tree property ``max_curr_opt`` to ``max-curr-opt``.`
+
 PWM
 ===
 
@@ -192,6 +321,22 @@ Interrupt Controller
 LED Strip
 =========
 
+Misc
+====
+
+* All the functions in the ft8xx driver take an additional ``const struct *device`` parameter
+  to allow for multiple instances of the driver.
+
+  The exception to this is the functions and macros defined in the
+  :zephyr_file:`include/zephyr/drivers/misc/ft8xx/ft8xx_reference_api.h` file, which translate the
+  API to a single-instance model, compatible with the API defined in the FT8xx programming guide.
+  These functions have not been modified.
+
+* The :c:func:`ft8xx_register_int` function now takes an additional ``void *user_data`` parameter
+  to allow user-defined data to be passed to the interrupt handler.
+  Additionally, the signature of the ft8xx interrupt handler has changed to include the
+  ``void *user_data`` parameter.
+
 MMU/MPU
 =======
 
@@ -234,13 +379,78 @@ PWM
 
 * Renamed the ``compatible`` from ``nxp,kinetis-ftm-pwm`` to :dtcompatible:`nxp,ftm-pwm`.
 
+SDHC
+====
+
+* Renamed the device tree property from ``power_delay_ms`` to ``power-delay-ms```
+* Renamed the device tree property from ``max_current_330`` to ``max-current-330``
+
 Sensors
 =======
 
+  * The :dtcompatible:`we,wsen-pads` driver has been renamed to
+    :dtcompatible:`we,wsen-pads-2511020213301`.
+    The Device Tree can be configured as follows:
+
+    .. code-block:: devicetree
+
+      &i2c0 {
+        pads:pads-2511020213301@5d {
+          compatible = "we,wsen-pads-2511020213301";
+          reg = <0x5d>;
+          odr = < 10 >;
+          interrupt-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
+        };
+      };
+
+  * The :dtcompatible:`we,wsen-pdus` driver has been renamed to
+    :dtcompatible:`we,wsen-pdus-25131308XXXXX`.
+    The Device Tree can be configured as follows:
+
+    .. code-block:: devicetree
+
+      &i2c0 {
+        pdus:pdus-25131308XXXXX@78 {
+          compatible = "we,wsen-pdus-25131308XXXXX";
+          reg = < 0x78 >;
+          sensor-type = < 4 >;
+        };
+      };
+
+  * The :dtcompatible:`we,wsen-tids` driver has been renamed to
+    :dtcompatible:`we,wsen-tids-2521020222501`.
+    The Device Tree can be configured as follows:
+
+    .. code-block:: devicetree
+
+      &i2c0 {
+        tids:tids-2521020222501@3F {
+          compatible = "we,wsen-tids-2521020222501";
+          reg = < 0x3F >;
+          odr = < 25 >;
+          interrupt-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
+        };
+      };
+
+  * The :dtcompatible:`invensense,icp10125` driver has been renamed to
+    :dtcompatible:`invensense,icp101xx`.
+    The Device Tree can be configured as follows:
+
+    .. code-block:: devicetree
+
+      &i2c0 {
+        icp101xx:icp101xx@63 {
+           compatible = "invensense,icp101xx";
+           reg = <0x63>;
+        };
+      };
+
 Serial
 ======
 
 * Renamed the ``compatible`` from ``nxp,kinetis-lpuart`` to :dtcompatible:`nxp,lpuart`.
+* Silabs Usart driver has been split for Series 2 :dtcompatible:`silabs,usart-uart`
+  and  Series 0/1 ``silabs,gecko-usart``
 
 Stepper
 =======
@@ -248,16 +458,36 @@ Stepper
   * Renamed the ``compatible`` from ``zephyr,gpio-steppers`` to :dtcompatible:`zephyr,gpio-stepper`.
   * Renamed the ``stepper_set_actual_position`` function to :c:func:`stepper_set_reference_position`.
   * Renamed the ``stepper_enable_constant_velocity_mode`` function to :c:func:`stepper_run`.
+    The function does not take a velocity parameter anymore. Set the desired speed using the
+    :c:func:`stepper_set_microstep_interval` function beforehand.
   * Renamed the ``stepper_move`` function to :c:func:`stepper_move_by`.
   * Renamed the ``stepper_set_target_position`` function to :c:func:`stepper_move_to`.
+  * Renamed the ``stepper_set_max_velocity`` function to :c:func:`stepper_set_microstep_interval`.
+    The function now takes the step interval in nanoseconds. This allows for a more precise control.
+  * Deprecating setting max velocity via :c:func:`stepper_run`.
   * The :kconfig:option:`STEPPER_ADI_TMC_RAMP_GEN` is now deprecated and is replaced with the new
-    :kconfig:option:`STEPPER_ADI_TMC5041_RAMP_GEN` option.
+    :kconfig:option:`STEPPER_ADI_TMC50XX_RAMP_GEN` option.
+  * Renamed tmc5041 stepper driver to tmc50xx.
+  * To control the velocity for :dtcompatible:`adi,tmc50xx` stepper driver, use
+    :c:func:`tmc50xx_stepper_set_max_velocity` or :c:func:`tmc50xx_stepper_set_ramp`.
+  * Renamed the DeviceTree property ``en_spreadcycle`` to ``en-spreadcycle``.
+  * Renamed the DeviceTree property ``i_scale_analog`` to ``i-scale-analog``.
+  * Renamed the DeviceTree property ``index_optw`` to ``index-otpw``.
+  * Renamed the DeviceTree property ``ìndex_step`` to ``index-step``.
+  * Renamed the DeviceTree property ``internal_rsense`` to ``internal-rsense``.
+  * Renamed the DeviceTree property ``lock_gconf`` to ``lock-gconf``.
+  * Renamed the DeviceTree property ``mstep_reg_select`` to ``mstep-reg-select``.
+  * Renamed the DeviceTree property ``pdn_disable`` to ``pdn-disable``.
+  * Renamed the DeviceTree property ``poscmp_enable`` to ``poscmp-enable``.
+  * Renamed the DeviceTree property ``test_mode`` to ``test-mode``.
 
 SPI
 ===
 
 * Renamed the ``compatible`` from ``nxp,imx-lpspi`` to :dtcompatible:`nxp,lpspi`.
 * Renamed the ``compatible`` from ``nxp,kinetis-dspi`` to :dtcompatible:`nxp,dspi`.
+* Renamed the ``compatible`` from ``silabs,gecko-spi-usart`` to :dtcompatible:`silabs,usart-spi`.
+* Renamed the ``compatible`` from ``silabs,gecko-spi-eusart`` to :dtcompatible:`silabs,eusart-spi`.
 
 Regulator
 =========
@@ -272,6 +502,12 @@ Timer
 
 * Renamed the ``compatible`` from ``nxp,kinetis-ftm`` to :dtcompatible:`nxp,ftm` and relocate it
   under ``dts/bindings/timer``.
+* Renamed the device tree property from ``ticks_us`` to ``ticks-us``.
+
+USB
+===
+
+* Renamed the devicetree property names ``phy_handle`` to ``phy-handle``.
 
 Video
 =====
@@ -283,14 +519,26 @@ Video
   The new ``video-controls.h`` source now contains description of each control ID to help
   disambiguating.
 
+* The ``video_pix_fmt_bpp()`` function was returning a byte count, this got replaced by
+  ``video_bits_per_pixel()`` which return a bit count. For instance, invocations such as
+  ``pitch = width * video_pix_fmt_bpp(pixfmt)`` needs to be replaced by an equivalent
+  ``pitch = width * video_bits_per_pixel(pixfmt) / BITS_PER_BYTE``.
+
+* The :c:func:`video_buffer_alloc` and :c:func:`video_buffer_aligned_alloc` functions in the
+  video API now take an additional timeout parameter.
+
+* The :c:func:`video_stream_start` and :c:func:`video_stream_stop` driver APIs are now merged
+  into the new :c:func:`video_set_stream` driver API. The user APIs are however unchanged to
+  keep backward compatibility with downstream applications.
+
 Watchdog
 ========
 
+* Renamed the ``compatible`` from ``nxp,kinetis-wdog32`` to :dtcompatible:`nxp,wdog32`.
+
 Wi-Fi
 =====
 
-* Renamed the ``compatible`` from ``nxp,kinetis-wdog32`` to :dtcompatible:`nxp,wdog32`.
-
 * The config options :kconfig:option:`CONFIG_NXP_WIFI_BUILD_ONLY_MODE` and
   :kconfig:option:`CONFIG_NRF_WIFI_BUILD_ONLY_MODE` are now unified under
   :kconfig:option:`CONFIG_BUILD_ONLY_NO_BLOBS` making it a common entry point
@@ -347,6 +595,16 @@ Bluetooth Audio
     * :kconfig:option:`CONFIG_BT_PAC_SNK`
     * :kconfig:option:`CONFIG_BT_PAC_SRC`
 
+* PACS have been changed to support dynamic, runtime configuration. This means that PACS now has
+  to be registered with :c:func:`bt_pacs_register` before it can be used. In addition,
+  :c:func:`bt_pacs_register` also have to be called before :c:func:`bt_ascs_register` can be
+  be called. All Kconfig options still remain. Runtime configuration cannot override a disabled
+  Kconfig option. (:github:`83730`)
+
+* Several services and service client (AICS, ASCS, CSIP, HAS, MCS, PACS, TBS, VCP and VOCS) now
+  depend on :kconfig:option:`CONFIG_BT_SMP` and may need to be explicitly enabled.
+  (:github:`84994``)
+
 Bluetooth Classic
 =================
 
@@ -376,6 +634,16 @@ Bluetooth Host
 Bluetooth Crypto
 ================
 
+Bluetooth Services
+==================
+
+* The :kconfig:option:`CONFIG_BT_DIS_MODEL` and :kconfig:option:`CONFIG_BT_DIS_MANUF` have been
+  deprecated. Application developers should now use the
+  :kconfig:option:`CONFIG_BT_DIS_MODEL_NUMBER_STR` and
+  :kconfig:option:`CONFIG_BT_DIS_MANUF_NAME_STR` Kconfig options to set the string values in the
+  Model Number String and Manufacturer Name String characteristics that are part of the Device
+  Information Service (DIS).
+
 Networking
 **********
 
@@ -396,22 +664,51 @@ Networking
   rather than directly in the :c:struct:`http_client_ctx` to correctly handle concurrent requests
   on different HTTP/2 streams.
 
+* The HTTP server public API function signature for the :c:type:`http_resource_websocket_cb_t` has
+  changed, a :c:struct:`http_request_ctx` parameter has been added. The application may use this to
+  access the request headers of the HTTP upgrade request, which may be useful in deciding whether
+  to accept or reject a websocket connection.
+
+* An additional ``_res_fallback`` parameter has been added to the :c:macro:`HTTP_SERVICE_DEFINE`
+  and :c:macro:`HTTPS_SERVICE_DEFINE` macros, allowing a fallback resource to be served if no other
+  resources match the requested path. To retain the existing behaviour, ``NULL`` can be passed as the
+  additional parameter.
+
 * The :kconfig:option:`CONFIG_NET_L2_OPENTHREAD` symbol no longer implies the
   :kconfig:option:`CONFIG_NVS` Kconfig option. Platforms using OpenThread must explicitly enable
   either the :kconfig:option:`CONFIG_NVS` or :kconfig:option:`CONFIG_ZMS` Kconfig option.
 
+* ``CONFIG_NET_TC_SKIP_FOR_HIGH_PRIO`` was deprecated in favour of
+  :kconfig:option:`CONFIG_NET_TC_TX_SKIP_FOR_HIGH_PRIO` to avoid naming ambiguity.
+
 Other Subsystems
 ****************
 
 Flash map
 =========
 
+Filesystem
+==========
+
+* The EXT2 Kconfig symbol ``CONFIG_MAX_FILES`` has been renamed to
+  :kconfig:option:`CONFIG_EXT2_MAX_FILES`.
+
 hawkBit
 =======
 
+* The Kconfig symbols :kconfig:option:`CONFIG_SMF` and
+  :kconfig:option:`CONFIG_SMF_ANCESTOR_SUPPORT` are now required to be enabled to use the
+  hawkBit subsystem.
+
 MCUmgr
 ======
 
+* The Kconfig :kconfig:option:`CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_WITHOUT_SCRATCH` has been
+  deprecated and replaced with :kconfig:option:`CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_USING_MOVE`,
+  applications should be updated to select this new symbol if they were selecting the old symbol.
+
+* The deprecated macro ``MGMT_CB_ERROR_RET`` has been removed.
+
 Modem
 =====
 
@@ -422,6 +719,15 @@ LoRa
   additional ``user_data`` parameter, which is a void pointer. This parameter can be used to reference
   any user-defined data structure. To maintain the current behavior, set this parameter to ``NULL``.
 
+Secure Storage
+==============
+
+* Store backends no longer automatically enable their dependencies through ``select`` or ``imply``.
+  Users must ensure that the depencies are enabled in their applications.
+  :kconfig:option:`CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_SETTINGS` previously enabled NVS
+  and settings, which means the NVS settings backend would get used by default if ZMS wasn't
+  enabled. (:github:`86181`)
+
 Stream Flash
 ============
 
diff --git a/doc/releases/migration-guide-4.2.rst b/doc/releases/migration-guide-4.2.rst
index 99a0ca65fba..732c4b08fea 100644
--- a/doc/releases/migration-guide-4.2.rst
+++ b/doc/releases/migration-guide-4.2.rst
@@ -38,9 +38,196 @@ Boards
   nRF Util can be found
   `here <https://docs.nordicsemi.com/bundle/nrfutil/page/README.html>`_.
 
+* All boards based on a Nordic IC of the nRF54L series now default to not
+  erasing any part of the internal storage when flashing. If you'd like to
+  revert to the previous default of erasing the pages that will be written to by
+  the firmware to be flashed you can set the new ``--erase-mode`` command-line
+  switch when invoking ``west flash`` to ``ranges``.
+  Note that RRAM on nRF54L devices is not physically paged, and paging is
+  only artificially provided, with a page size of 4096 bytes, for an easier
+  transition of nRF52 software to nRF54L devices.
+
+* The config option :kconfig:option:`CONFIG_NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME` has been deprecated
+  in favor of :kconfig:option:`CONFIG_NATIVE_SIM_SLOWDOWN_TO_REAL_TIME`.
+
+* The DT binding :dtcompatible:`zephyr,native-posix-cpu` has been deprecated in favor of
+  :dtcompatible:`zephyr,native-sim-cpu`.
+
+* Zephyr now supports version 1.11.2 of the :zephyr:board:`neorv32`. NEORV32 processor (SoC)
+  implementations need to be updated to this version to be compatible with Zephyr v4.2.0.
+
+* The :zephyr:board:`neorv32` now targets NEORV32 processor (SoC) templates via board variants. The
+  old ``neorv32`` board target is now named ``neorv32/neorv32/up5kdemo``.
+
+* ``arduino_uno_r4_minima``, ``arduino_uno_r4_wifi``, and ``mikroe_clicker_ra4m1`` have migrated to
+  new FSP-based configurations.
+  While there are no major functional changes, the device tree structure has been significantly revised.
+  The following device tree bindings are now removed:
+  ``renesas,ra-gpio``, ``renesas,ra-uart-sci``, ``renesas,ra-pinctrl``,
+  ``renesas,ra-clock-generation-circuit``, and ``renesas,ra-interrupt-controller-unit``.
+  Instead, use the following replacements:
+  - :dtcompatible:`renesas,ra-gpio-ioport`
+  - :dtcompatible:`renesas,ra-sci-uart`
+  - :dtcompatible:`renesas,ra-pinctrl-pfs`
+  - :dtcompatible:`renesas,ra-cgc-pclk-block`
+
+* Nucleo WBA52CG board (``nucleo_wba52cg``) is not supported anymore since it is NRND
+  (Not Recommended for New Design) and it is not supported anymore in the STM32CubeWBA from
+  version 1.1.0 (July 2023). The migration to :zephyr:board:`nucleo_wba55cg` (``nucleo_wba55cg``)
+  is recommended and it could be done without any change.
+
 Device Drivers and Devicetree
 *****************************
 
+DAI
+===
+
+* Renamed the devicetree property ``dai_id`` to ``dai-id``.
+* Renamed the devicetree property ``afe_name`` to ``afe-name``.
+* Renamed the devicetree property ``agent_disable`` to ``agent-disable``.
+* Renamed the devicetree property ``ch_num`` to ``ch-num``.
+* Renamed the devicetree property ``mono_invert`` to ``mono-invert``.
+* Renamed the devicetree property ``quad_ch`` to ``quad-ch``.
+* Renamed the devicetree property ``int_odd`` to ``int-odd``.
+
+DMA
+===
+
+* Renamed the devicetree property ``nxp,a_on`` to ``nxp,a-on``.
+* Renamed the devicetree property ``dma_channels`` to ``dma-channels``.
+
+Counter
+=======
+
+* ``counter_native_posix`` has been renamed ``counter_native_sim``, and with it its
+  kconfig options and DT binding. :dtcompatible:`zephyr,native-posix-counter`  has been deprecated
+  in favor of :dtcompatible:`zephyr,native-sim-counter`.
+  And :kconfig:option:`CONFIG_COUNTER_NATIVE_POSIX` and its related options with
+  :kconfig:option:`CONFIG_COUNTER_NATIVE_SIM` (:github:`86616`).
+
+Entropy
+=======
+
+* ``fake_entropy_native_posix`` has been renamed ``fake_entropy_native_sim``, and with it its
+  kconfig options and DT binding. :dtcompatible:`zephyr,native-posix-rng`  has been deprecated
+  in favor of :dtcompatible:`zephyr,native-sim-rng`.
+  And :kconfig:option:`CONFIG_FAKE_ENTROPY_NATIVE_POSIX` and its related options with
+  :kconfig:option:`CONFIG_FAKE_ENTROPY_NATIVE_SIM` (:github:`86615`).
+
+Eeprom
+========
+
+* :dtcompatible:`ti,tmp116-eeprom` has been renamed to :dtcompatible:`ti,tmp11x-eeprom` because it
+  supports both tmp117 and tmp119.
+
+Ethernet
+========
+
+* Removed Kconfig option ``ETH_STM32_HAL_MII`` (:github:`86074`).
+  PHY interface type is now selected via the ``phy-connection-type`` property in the device tree.
+
+* The :dtcompatible:`st,stm32-ethernet` driver now requires the ``phy-handle`` phandle to be
+  set to the according PHY node in the device tree (:github:`87593`).
+
+* The Kconfig options ``ETH_STM32_HAL_PHY_ADDRESS``, ``ETH_STM32_CARRIER_CHECK``,
+  ``ETH_STM32_CARRIER_CHECK_RX_IDLE_TIMEOUT_MS``, ``ETH_STM32_AUTO_NEGOTIATION_ENABLE``,
+  ``ETH_STM32_SPEED_10M``, ``ETH_STM32_MODE_HALFDUPLEX`` have been removed, as they are no longer
+  needed, and the driver now uses the ethernet phy api to communicate with the phy driver, which
+  is resposible for configuring the phy settings (:github:`87593`).
+
+* ``ethernet_native_posix`` has been renamed ``ethernet_native_tap``, and with it its
+  kconfig options: :kconfig:option:`CONFIG_ETH_NATIVE_POSIX` and its related options have been
+  deprecated in favor of :kconfig:option:`CONFIG_ETH_NATIVE_TAP` (:github:`86578`).
+
+* NuMaker Ethernet driver ``eth_numaker.c`` now supports ``gen_random_mac``,
+  and the EMAC data flash feature has been removed (:github:`87953`).
+
+* The enum ``ETHERNET_DSA_MASTER_PORT`` and ``ETHERNET_DSA_SLAVE_PORT`` in
+  :zephyr_file:`include/zephyr/net/ethernet.h` have been renamed
+  to ``ETHERNET_DSA_CONDUIT_PORT`` and ``ETHERNET_DSA_USER_PORT``.
+
+Enhanced Serial Peripheral Interface (eSPI)
+===========================================
+
+* Renamed the devicetree property ``io_girq`` to ``io-girq``.
+* Renamed the devicetree property ``vw_girqs`` to ``vw-girqs``.
+* Renamed the devicetree property ``pc_girq`` to ``pc-girq``.
+* Renamed the devicetree property ``poll_timeout`` to ``poll-timeout``.
+* Renamed the devicetree property ``poll_interval`` to ``poll-interval``.
+* Renamed the devicetree property ``consec_rd_timeout`` to ``consec-rd-timeout``.
+* Renamed the devicetree property ``sus_chk_delay`` to ``sus-chk-delay``.
+* Renamed the devicetree property ``sus_rsm_interval`` to ``sus-rsm-interval``.
+
+GPIO
+====
+
+* To support the RP2350B, which has many pins, the Raspberry Pi-GPIO configuration has
+  been changed. The previous role of :dtcompatible:`raspberrypi,rpi-gpio` has been migrated to
+  :dtcompatible:`raspberrypi,rpi-gpio-port`, and :dtcompatible:`raspberrypi,rpi-gpio` is
+  now left as a placeholder and mapper.
+  The labels have also been changed along, so no changes are necessary for regular use.
+
+I2S
+===
+* The :dtcompatible:`nxp,mcux-i2s` driver added property ``mclk-output``. Set this property to
+* configure the MCLK signal as an output.  Older driver versions used the macro
+* ``I2S_OPT_BIT_CLK_SLAVE`` to configure the MCLK signal direction. (:github:`88554`)
+
+Sensors
+=======
+
+* ``ltr`` vendor prefix has been renamed to ``liteon``, and with it the
+  :dtcompatible:`ltr,f216a` name has been replaced by :dtcompatible:`liteon,ltrf216a`.
+  The choice :kconfig:option:`DT_HAS_LTR_F216A_ENABLED` has been replaced with
+  :kconfig:option:`DT_HAS_LITEON_LTRF216A_ENABLED` (:github:`85453`)
+
+* :dtcompatible:`ti,tmp116` has been renamed to :dtcompatible:`ti,tmp11x` because it supports
+  tmp116, tmp117 and tmp119.
+
+* :dtcompatible:`meas,ms5837` has been replaced by :dtcompatible:`meas,ms5837-30ba`
+  and :dtcompatible:`meas,ms5837-02ba`. In order to use one of the two variants, the
+  status property needs to be used as well.
+
+Serial
+=======
+
+* ``uart_native_posix`` has been renamed ``uart_native_pty``, and with it its
+  kconfig options and DT binding. :dtcompatible:`zephyr,native-posix-uart`  has been deprecated
+  in favor of :dtcompatible:`zephyr,native-pty-uart`.
+  :kconfig:option:`CONFIG_UART_NATIVE_POSIX` and its related options with
+  :kconfig:option:`CONFIG_UART_NATIVE_PTY`.
+  The choice :kconfig:option:`CONFIG_NATIVE_UART_0` has been replaced with
+  :kconfig:option:`CONFIG_UART_NATIVE_PTY_0`, but now, it is also possible to select if a UART is
+  connected to the process stdin/out instead of a PTY at runtime with the command line option
+  ``--<uart_name>_stdinout``.
+  :kconfig:option:`CONFIG_NATIVE_UART_AUTOATTACH_DEFAULT_CMD` has been replaced with
+  :kconfig:option:`CONFIG_UART_NATIVE_PTY_AUTOATTACH_DEFAULT_CMD`.
+  :kconfig:option:`CONFIG_UART_NATIVE_WAIT_PTS_READY_ENABLE` has been deprecated. The functionality
+  it enabled is now always enabled as there is no drawbacks from it.
+  :kconfig:option:`CONFIG_UART_NATIVE_POSIX_PORT_1_ENABLE` has been deprecated. This option does
+  nothing now. Instead users should instantiate as many :dtcompatible:`zephyr,native-pty-uart` nodes
+  as native PTY UART instances they want. (:github:`86739`)
+
+Timer
+=====
+
+* ``native_posix_timer`` has been renamed ``native_sim_timer``, and so its kconfig option
+  :kconfig:option:`CONFIG_NATIVE_POSIX_TIMER` has been deprecated in favor of
+  :kconfig:option:`CONFIG_NATIVE_SIM_TIMER`, (:github:`86612`).
+
+Modem
+=====
+
+* Removed Kconfig option :kconfig:option:`CONFIG_MODEM_CELLULAR_CMUX_MAX_FRAME_SIZE` in favor of
+  :kconfig:option:`CONFIG_MODEM_CMUX_WORK_BUFFER_SIZE` and :kconfig:option:`CONFIG_MODEM_CMUX_MTU`.
+
+
+Stepper
+=======
+
+* Refactored the ``stepper_enable(const struct device * dev, bool enable)`` function to
+  :c:func:`stepper_enable` & :c:func:`stepper_disable`.
+
 Bluetooth
 *********
 
@@ -57,6 +244,28 @@ Bluetooth Host
   :zephyr_file:`include/zephyr/bluetooth/conn.h` have been renamed
   to ``BT_LE_CS_TONE_ANTENNA_CONFIGURATION_A<NUMBER>_B<NUMBER>``.
 
+* The ISO data paths are not longer setup automatically, and shall explicitly be setup and removed
+  by the application by calling :c:func:`bt_iso_setup_data_path` and
+  :c:func:`bt_iso_remove_data_path` respectively. (:github:`75549`)
+
+* ``BT_ISO_CHAN_TYPE_CONNECTED`` has been split into ``BT_ISO_CHAN_TYPE_CENTRAL`` and
+  ``BT_ISO_CHAN_TYPE_PERIPHERAL`` to better describe the type of the ISO channel, as behavior for
+  each role may be different. Any existing uses/checks for ``BT_ISO_CHAN_TYPE_CONNECTED``
+  can be replaced with an ``||`` of the two. (:github:`75549`)
+
+* The ``struct _bt_gatt_ccc`` in :zephyr_file:`include/zephyr/bluetooth/gatt.h` has been renamed to
+  struct :c:struct:`bt_gatt_ccc_managed_user_data`. (:github:`88652`)
+
+* The macro ``BT_GATT_CCC_INITIALIZER`` in :zephyr_file:`include/zephyr/bluetooth/gatt.h`
+  has been renamed to :c:macro:`BT_GATT_CCC_MANAGED_USER_DATA_INIT`. (:github:`88652`)
+
+Bluetooth Classic
+=================
+
+* The parameters of HFP AG callback ``sco_disconnected`` of the struct :c:struct:`bt_hfp_ag_cb`
+  have been changed to SCO connection object ``struct bt_conn *sco_conn`` and the disconnection
+  reason of the SCO connection ``uint8_t reason``.
+
 Networking
 **********
 
@@ -76,6 +285,29 @@ Networking
   more generic :c:enumerator:`TLS_CREDENTIAL_PUBLIC_CERTIFICATE` to better
   reflect the purpose of this credential type.
 
+* The MQTT public API function :c:func:`mqtt_disconnect` has changed. The function
+  now accepts additional ``param`` parameter to support MQTT 5.0 case. The parameter
+  is optional and not used with older MQTT versions - MQTT 3.1.1 users should pass
+  NULL as an argument.
+
+* The ``AF_PACKET/SOCK_RAW/IPPROTO_RAW`` socket combination is no longer supported,
+  as ``AF_PACKET`` sockets should only accept IEEE 802.3 protocol numbers. As an
+  alternative, ``AF_PACKET/SOCK_DGRAM/ETH_P_ALL`` or ``AF_INET(6)/SOCK_RAW/IPPROTO_IP``
+  sockets can be used, depending on the actual use case.
+
+* The HTTP server now respects the configured ``_concurrent`` and  ``_backlog`` values. Check that
+  you provide applicable values to :c:macro:`HTTP_SERVICE_DEFINE_EMPTY`,
+  :c:macro:`HTTPS_SERVICE_DEFINE_EMPTY`, :c:macro:`HTTP_SERVICE_DEFINE` and
+  :c:macro:`HTTPS_SERVICE_DEFINE`.
+
+* :kconfig:option:`NET_ZPERF` no longer includes server support by default. To use
+  the server commands, enable :kconfig:option:`NET_ZPERF_SERVER`. If server support
+  is not needed, :kconfig:option:`ZVFS_POLL_MAX` can possibly be reduced.
+
+* The OpenThread-related Kconfig options from ``subsys/net/l2/openthread/Kconfig`` have been moved to
+  ``modules/openthread/Kconfig``. All the Kconfig options remain the same. You can still use them in the
+  same way as before, but to modify them, use the new path in the menuconfig or guiconfig.
+
 SPI
 ===
 
@@ -85,8 +317,21 @@ SPI
 Other subsystems
 ****************
 
+ZBus
+====
+
+* The function :c:func:`zbus_chan_add_obs` now requires a :c:struct:`zbus_observer_node` as an argument,
+  which was previously allocated through :c:func:`k_malloc` internally. The structure must remain valid
+  in memory until :c:func:`zbus_chan_rem_obs` is called.
+
 Modules
 *******
 
 Architectures
 *************
+
+* Moved :kconfig:option:`CONFIG_SRAM_VECTOR_TABLE` from ``zephyr/Kconfig.zephyr`` to
+  ``zephyr/arch/Kconfig`` and added dependency to :kconfig:option:`CONFIG_XIP`,
+  :kconfig:option:`CONFIG_ARCH_HAS_VECTOR_TABLE_RELOCATION` and
+  :kconfig:option:`CONFIG_ROMSTART_RELOCATION_ROM` to support relocation
+  of vector table in RAM.
diff --git a/doc/releases/release-notes-1.14.rst b/doc/releases/release-notes-1.14.rst
index 4d8100c24ff..70bf8daa54f 100644
--- a/doc/releases/release-notes-1.14.rst
+++ b/doc/releases/release-notes-1.14.rst
@@ -704,7 +704,7 @@ Boards & SoC Support
 Drivers and Sensors
 *******************
 
-* Added new drivers and backends for :ref:`native_posix <native_posix>`:
+* Added new drivers and backends for ``native_posix``:
 
   * A UART driver that maps the Zephyr UART to a new host PTY
   * A USB driver that can expose a host connected USB device
diff --git a/doc/releases/release-notes-3.2.rst b/doc/releases/release-notes-3.2.rst
index 11e923b0f8e..a7852db2e06 100644
--- a/doc/releases/release-notes-3.2.rst
+++ b/doc/releases/release-notes-3.2.rst
@@ -505,7 +505,7 @@ Drivers and Sensors
 
 * CAN
 
-  * A driver for bridging from :ref:`native_posix` to Linux SocketCAN has been added.
+  * A driver for bridging from ``native_posix`` to Linux SocketCAN has been added.
   * A driver for the Espressif ESP32 TWAI has been added. See the
     :dtcompatible:`espressif,esp32-twai` devicetree binding for more information.
   * The STM32 CAN-FD CAN driver clock configuration has been moved from Kconfig to :ref:`devicetree
@@ -1112,7 +1112,7 @@ Devicetree
     * :dtcompatible:`microchip,xec-espi`
     * :dtcompatible:`microchip,xec-i2c`
     * :dtcompatible:`microchip,xec-qmspi`
-    * :dtcompatible:`neorv32-machine-timer`
+    * :dtcompatible:`neorv32,machine-timer`
     * :dtcompatible:`nordic,nrf-ieee802154`
     * :dtcompatible:`nuclei,systimer`
     * :dtcompatible:`nuvoton,npcx-leakage-io`
@@ -1613,7 +1613,7 @@ MCUboot
 * Edited the DFU detection's GPIO-pin configuration to be done through DTS using the ``mcuboot-button0`` pin alias.
 * Edited the LED usage to prefer DTS' ``mcuboot-led0`` alias over the ``bootloader-led0`` alias.
 * Removed :c:func:`device_get_binding()` usage in favor of :c:func:`DEVICE_DT_GET()`.
-* Added support for generic `watchdog0` alias.
+* Added support for generic ``watchdog0`` alias.
 * Enabled watchdog feed by default.
 * Dropped the :kconfig:option:`CONFIG_BOOT_IMAGE_ACCESS_HOOKS_FILE` option.
   The inclusion of the Hooks implementation file is now up to the project's customization.
diff --git a/doc/releases/release-notes-3.3.rst b/doc/releases/release-notes-3.3.rst
index 9867ff7cdea..c752ff01cbd 100644
--- a/doc/releases/release-notes-3.3.rst
+++ b/doc/releases/release-notes-3.3.rst
@@ -186,7 +186,7 @@ Removed APIs in this release
 Deprecated in this release
 ==========================
 
-* :ref:`xtools toolchain variant <toolchain_xtools>` is now deprecated. When using a
+* ``xtools`` toolchain variant is now deprecated. When using a
   custom toolchain built with Crosstool-NG, the
   :ref:`cross-compile toolchain variant <other_x_compilers>` should be used instead.
 
diff --git a/doc/releases/release-notes-3.4.rst b/doc/releases/release-notes-3.4.rst
index a8c3b6608e9..927850d8445 100644
--- a/doc/releases/release-notes-3.4.rst
+++ b/doc/releases/release-notes-3.4.rst
@@ -150,12 +150,12 @@ Changes in this release
   * ``gpio_keys``: moved out of ``gpio``, replaced the custom API to use input
     events instead, the :dtcompatible:`zephyr,gpio-keys` binding is unchanged
     but now requires ``zephyr,code`` to be set.
-  * ``ft5336``: moved from :ref:`kscan_api` to :ref:`input`, renamed the Kconfig
+  * ``ft5336``: moved from ``kscan_api`` to :ref:`input`, renamed the Kconfig
     options from ``CONFIG_KSCAN_FT5336``, ``CONFIG_KSCAN_FT5336_PERIOD`` and
     ``KSCAN_FT5336_INTERRUPT`` to :kconfig:option:`CONFIG_INPUT_FT5336`,
     :kconfig:option:`CONFIG_INPUT_FT5336_PERIOD` and
     :kconfig:option:`CONFIG_INPUT_FT5336_INTERRUPT`.
-  * ``kscan_sdl``: moved from :ref:`kscan_api` to :ref:`input`, renamed the Kconfig
+  * ``kscan_sdl``: moved from ``kscan_api`` to :ref:`input`, renamed the Kconfig
     option from ``KSCAN_SDL`` to :kconfig:option:`CONFIG_INPUT_SDL_TOUCH` and the
     compatible from ``zephyr,sdl-kscan`` to
     :dtcompatible:`zephyr,input-sdl-touch`.
diff --git a/doc/releases/release-notes-3.5.rst b/doc/releases/release-notes-3.5.rst
index aea5c731abb..d643d4b5dba 100644
--- a/doc/releases/release-notes-3.5.rst
+++ b/doc/releases/release-notes-3.5.rst
@@ -1022,7 +1022,7 @@ Bindings
     * The ``riscv,isa`` property used by RISC-V CPU bindings no longer has an
       ``enum`` value.
 
-    * :dtcompatible:`neorv32-cpu`:
+    * :dtcompatible:`neorv32,cpu`:
 
           * new property: ``mmu-type``
           * new property: ``riscv,isa``
@@ -2180,7 +2180,7 @@ Libraries / Subsystems
     the heap.
   * Added a new type of observer called Message Subscriber. ZBus' VDED will send a copy of the
     message during the publication/notification process.
-  * Changed the VDED delivery sequence. Check the ref:`documentation<zbus delivery sequence>`.
+  * Changed the VDED delivery sequence. Check the :ref:`documentation <zbus delivery sequence>`.
   * ZBus runtime observers now rely on the heap instead of a memory pool.
   * Added new iterable section iterators APIs (for channels and observers) can now receive a
     ``user_data`` pointer to keep context between the function calls.
@@ -2322,8 +2322,8 @@ Documentation
 Tests and Samples
 *****************
 
-* Created common sample for file systems (`fs_sample`). It originates from sample for FAT
-  (`fat_fs`) and supports both FAT and ext2 file systems.
+* Created common sample for file systems (``fs_sample``). It originates from sample for FAT
+  (``fat_fs``) and supports both FAT and ext2 file systems.
 
 * Created the zbus confirmed channel sample to demonstrate how to implement a delivery-guaranteed
   channel using subscribers.
diff --git a/doc/releases/release-notes-3.6.rst b/doc/releases/release-notes-3.6.rst
index 8bbec8f1be3..06c587298f3 100644
--- a/doc/releases/release-notes-3.6.rst
+++ b/doc/releases/release-notes-3.6.rst
@@ -1301,9 +1301,9 @@ Additionally, the following changes in Zephyr were done:
 Tests and Samples
 *****************
 
-* :ref:`native_sim<native_sim>` has replaced :ref:`native_posix<native_posix>` as the default
+* :ref:`native_sim<native_sim>` has replaced ``native_posix`` as the default
   test platform.
-  :ref:`native_posix<native_posix>` remains supported and used in testing but will be deprecated
+  ``native_posix`` remains supported and used in testing but will be deprecated
   in a future release.
 
 * Bluetooth split stacks tests, where the BT host and controller are run in separate MCUs, are
diff --git a/doc/releases/release-notes-3.7.rst b/doc/releases/release-notes-3.7.rst
index 30749ad0380..9f81deebf40 100644
--- a/doc/releases/release-notes-3.7.rst
+++ b/doc/releases/release-notes-3.7.rst
@@ -412,8 +412,8 @@ Boards & SoC Support
   * Added support for :zephyr:board:`Raspberry Pi 5 board <rpi_5>`: ``rpi_5``.
   * Added support for :zephyr:board:`Seeed Studio XIAO RP2040 board <xiao_rp2040>`: ``xiao_rp2040``.
   * Added support for :zephyr:board:`Mikroe RA4M1 Clicker board <mikroe_clicker_ra4m1>`: ``mikroe_clicker_ra4m1``.
-  * Added support for :ref:`Arduino UNO R4 WiFi board <arduino_uno_r4>`: ``arduino_uno_r4_wifi``.
-  * Added support for :ref:`Renesas EK-RA8M1 board <ek_ra8m1>`: ``ek_ra8m1``.
+  * Added support for :zephyr:board:`Arduino UNO R4 WiFi board <arduino_uno_r4>`: ``arduino_uno_r4_wifi``.
+  * Added support for :zephyr:board:`Renesas EK-RA8M1 board <ek_ra8m1>`: ``ek_ra8m1``.
   * Added support for :zephyr:board:`ST Nucleo H533RE <nucleo_h533re>`: ``nucleo_h533re``.
   * Added support for :zephyr:board:`ST STM32C0116-DK Discovery Kit <stm32c0116_dk>`: ``stm32c0116_dk``.
   * Added support for :zephyr:board:`ST STM32H745I Discovery <stm32h745i_disco>`: ``stm32h745i_disco``.
@@ -452,8 +452,8 @@ Boards & SoC Support
   * Introduced the simulated :ref:`nrf54l15bsim<nrf54l15bsim>` target.
   * The nrf5x bsim targets now support BT LE Coded PHY.
   * LLVM fuzzing support has been refactored while adding support for it in native_sim.
-  * nRF54H20 PDK (pre-release) converted to :ref:`nrf54h20dk_nrf54h20`
-  * PPR core target in :ref:`nrf54h20dk_nrf54h20` runs from RAM by default. A
+  * nRF54H20 PDK (pre-release) converted to :zephyr:board:`nrf54h20dk`
+  * PPR core target in :zephyr:board:`nrf54h20dk` runs from RAM by default. A
     new ``xip`` variant has been introduced which runs from MRAM (XIP).
   * Refactored :zephyr:board:`beagleconnect_freedom` external antenna switch handling.
   * Added Arduino dts node labels for the nRF5340 Audio DK.
diff --git a/doc/releases/release-notes-4.0.rst b/doc/releases/release-notes-4.0.rst
index 8b9ede8f11e..6b8ab573009 100644
--- a/doc/releases/release-notes-4.0.rst
+++ b/doc/releases/release-notes-4.0.rst
@@ -105,22 +105,20 @@ Removed APIs in this release
 Deprecated in this release
 ==========================
 
-* Deprecated the :c:func:`net_buf_put` and :c:func:`net_buf_get` API functions in favor of
+* Deprecated the ``net_buf_put()`` and ``net_buf_get()`` API functions in favor of
   :c:func:`k_fifo_put` and :c:func:`k_fifo_get`.
 
-* The :ref:`kscan_api` subsystem has been marked as deprecated.
+* The ``kscan_api`` subsystem has been marked as deprecated.
 
 * Deprecated the TinyCrypt shim driver ``CONFIG_CRYPTO_TINYCRYPT_SHIM``.
 
-* :ref:`native_posix<native_posix>` has been deprecated in favour of
+* ``native_posix`` has been deprecated in favour of
   :ref:`native_sim<native_sim>`.
 
 * ``include/zephyr/net/buf.h`` is deprecated in favor of
   ``include/zephyr/net_buf.h>``. The old header will be removed in future releases
   and its usage should be avoided.
 
-* Deprecated the :c:func:`net_buf_put` and :c:func:`net_buf_get` API functions.
-
 Architectures
 *************
 
@@ -281,7 +279,7 @@ Boards & SoC Support
    * :zephyr:board:`ADI MAX32666FTHR <max32666fthr>` (``max32666fthr``)
    * :zephyr:board:`ADI MAX32675EVKIT <max32675evkit>` (``max32675evkit``)
    * :zephyr:board:`ADI MAX32690FTHR <max32690fthr>` (``max32690fthr``)
-   * :ref:`Arduino Nicla Vision <arduino_nicla_vision_board>` (``arduino_nicla_vision``)
+   * :zephyr:board:`arduino_nicla_vision` (``arduino_nicla_vision``)
    * :zephyr:board:`BeagleBone AI-64 <beaglebone_ai64>` (``beaglebone_ai64``)
    * :zephyr:board:`BeaglePlay (CC1352) <beagleplay>` (``beagleplay``)
    * :zephyr:board:`DPTechnics Walter <walter>` (``walter``)
@@ -291,9 +289,9 @@ Boards & SoC Support
    * :zephyr:board:`Espressif ESP8684-DevKitM <esp8684_devkitm>` (``esp8684_devkitm``)
    * :zephyr:board:`Gardena Smart Garden Radio Module <sgrm>` (``sgrm``)
    * :zephyr:board:`mikroe STM32 M4 Clicker <mikroe_stm32_m4_clicker>` (``mikroe_stm32_m4_clicker``)
-   * :ref:`Nordic Semiconductor nRF54L15 DK <nrf54l15dk_nrf54l15>` (``nrf54l15dk``)
-   * :ref:`Nordic Semiconductor nRF54L20 PDK <nrf54l20pdk_nrf54l20>` (``nrf54l20pdk``)
-   * :ref:`Nordic Semiconductor nRF7002 DK <nrf7002dk_nrf5340>` (``nrf7002dk``)
+   * :zephyr:board:`Nordic Semiconductor nRF54L15 DK <nrf54l15dk>` (``nrf54l15dk``)
+   * :zephyr:board:`Nordic Semiconductor nRF54L20 PDK <nrf54l20pdk>` (``nrf54l20pdk``)
+   * :zephyr:board:`Nordic Semiconductor nRF7002 DK <nrf7002dk>` (``nrf7002dk``)
    * :zephyr:board:`Nuvoton NPCM400_EVB <npcm400_evb>` (``npcm400_evb``)
    * :zephyr:board:`NXP FRDM-MCXA156 <frdm_mcxa156>` (``frdm_mcxa156``)
    * :zephyr:board:`NXP FRDM-MCXC242 <frdm_mcxc242>` (``frdm_mcxc242``)
@@ -303,21 +301,21 @@ Boards & SoC Support
    * :zephyr:board:`NXP i.MX95 EVK <imx95_evk>` (``imx95_evk``)
    * :zephyr:board:`NXP MIMXRT1180-EVK <mimxrt1180_evk>` (``mimxrt1180_evk``)
    * :ref:`PHYTEC phyBOARD-Nash i.MX93 <phyboard_nash>` (``phyboard_nash``)
-   * :ref:`Renesas RA2A1 Evaluation Kit <ek_ra2a1>` (``ek_ra2a1``)
-   * :ref:`Renesas RA4E2 Evaluation Kit <ek_ra4e2>` (``ek_ra4e2``)
-   * :ref:`Renesas RA4M2 Evaluation Kit <ek_ra4m2>` (``ek_ra4m2``)
-   * :ref:`Renesas RA4M3 Evaluation Kit <ek_ra4m3>` (``ek_ra4m3``)
-   * :ref:`Renesas RA4W1 Evaluation Kit <ek_ra4w1>` (``ek_ra4w1``)
-   * :ref:`Renesas RA6E2 Evaluation Kit <ek_ra6e2>` (``ek_ra6e2``)
-   * :ref:`Renesas RA6M1 Evaluation Kit <ek_ra6m1>` (``ek_ra6m1``)
-   * :ref:`Renesas RA6M2 Evaluation Kit <ek_ra6m2>` (``ek_ra6m2``)
-   * :ref:`Renesas RA6M3 Evaluation Kit <ek_ra6m3>` (``ek_ra6m3``)
-   * :ref:`Renesas RA6M4 Evaluation Kit <ek_ra6m4>` (``ek_ra6m4``)
-   * :ref:`Renesas RA6M5 Evaluation Kit <ek_ra6m5>` (``ek_ra6m5``)
-   * :ref:`Renesas RA8D1 Evaluation Kit <ek_ra8d1>` (``ek_ra8d1``)
-   * :ref:`Renesas RA6E1 Fast Prototyping Board <fpb_ra6e1>` (``fpb_ra6e1``)
-   * :ref:`Renesas RA6E2 Fast Prototyping Board <fpb_ra6e2>` (``fpb_ra6e2``)
-   * :ref:`Renesas RA8T1 Evaluation Kit <mcb_ra8t1>` (``mck_ra8t1``)
+   * :zephyr:board:`Renesas RA2A1 Evaluation Kit <ek_ra2a1>` (``ek_ra2a1``)
+   * :zephyr:board:`Renesas RA4E2 Evaluation Kit <ek_ra4e2>` (``ek_ra4e2``)
+   * :zephyr:board:`Renesas RA4M2 Evaluation Kit <ek_ra4m2>` (``ek_ra4m2``)
+   * :zephyr:board:`Renesas RA4M3 Evaluation Kit <ek_ra4m3>` (``ek_ra4m3``)
+   * :zephyr:board:`Renesas RA4W1 Evaluation Kit <ek_ra4w1>` (``ek_ra4w1``)
+   * :zephyr:board:`Renesas RA6E2 Evaluation Kit <ek_ra6e2>` (``ek_ra6e2``)
+   * :zephyr:board:`Renesas RA6M1 Evaluation Kit <ek_ra6m1>` (``ek_ra6m1``)
+   * :zephyr:board:`Renesas RA6M2 Evaluation Kit <ek_ra6m2>` (``ek_ra6m2``)
+   * :zephyr:board:`Renesas RA6M3 Evaluation Kit <ek_ra6m3>` (``ek_ra6m3``)
+   * :zephyr:board:`Renesas RA6M4 Evaluation Kit <ek_ra6m4>` (``ek_ra6m4``)
+   * :zephyr:board:`Renesas RA6M5 Evaluation Kit <ek_ra6m5>` (``ek_ra6m5``)
+   * :zephyr:board:`Renesas RA8D1 Evaluation Kit <ek_ra8d1>` (``ek_ra8d1``)
+   * :zephyr:board:`Renesas RA6E1 Fast Prototyping Board <fpb_ra6e1>` (``fpb_ra6e1``)
+   * :zephyr:board:`Renesas RA6E2 Fast Prototyping Board <fpb_ra6e2>` (``fpb_ra6e2``)
+   * :zephyr:board:`Renesas RA8T1 Motor Control Kit <mck_ra8t1>` (``mck_ra8t1``)
    * :zephyr:board:`Renode Cortex-R8 Virtual <cortex_r8_virtual>` (``cortex_r8_virtual``)
    * :zephyr:board:`Seeed XIAO ESP32-S3 Sense Variant <xiao_esp32s3>`: ``xiao_esp32s3``.
    * :ref:`sensry.io Ganymed Break-Out-Board (BOB) <ganymed_bob>` (``ganymed_bob``)
@@ -346,7 +344,7 @@ Boards & SoC Support
   * STM32: Deprecated MCO configuration via Kconfig in favour of setting it through Devicetree.
     See ``samples/boards/st/mco`` sample.
   * STM32: STM32CubeProgrammer is now the default runner on all STMicroelectronics STM32 boards.
-  * Removed the ``nrf54l15pdk`` board, use :ref:`nrf54l15dk_nrf54l15` instead.
+  * Removed the ``nrf54l15pdk`` board, use :zephyr:board:`nrf54l15dk` instead.
   * PHYTEC: ``mimx8mp_phyboard_pollux`` has been renamed to :ref:`phyboard_pollux<phyboard_pollux>`,
     with the old name marked as deprecated.
   * PHYTEC: ``mimx8mm_phyboard_polis`` has been renamed to :ref:`phyboard_polis<phyboard_polis>`,
@@ -1543,7 +1541,7 @@ zcbor
 Tests and Samples
 *****************
 
-* Together with the deprecation of :ref:`native_posix<native_posix>`, many tests which were
+* Together with the deprecation of ``native_posix``, many tests which were
   explicitly run in native_posix now run in :ref:`native_sim<native_sim>` instead.
   native_posix as a platform remains tested though.
 * Extended the tests of counter_basic_api with a testcase for counters without alarms
diff --git a/doc/releases/release-notes-4.1.rst b/doc/releases/release-notes-4.1.rst
index 98ac6c4bd8b..8d2649bd295 100644
--- a/doc/releases/release-notes-4.1.rst
+++ b/doc/releases/release-notes-4.1.rst
@@ -1,14 +1,68 @@
 :orphan:
 
+..
+  What goes here: removed/deprecated apis, new boards, new drivers, notable
+  features. If you feel like something new can be useful to a user, put it
+  under "Other Enhancements" in the first paragraph, if you feel like something
+  is worth mentioning in the project media (release blog post, release
+  livestream) put it under "Major enhancement".
+..
+  If you are describing a feature or functionality, consider adding it to the
+  actual project documentation rather than the release notes, so that the
+  information does not get lost in time.
+..
+  No list of bugfixes, minor changes, those are already in the git log, this is
+  not a changelog.
+..
+  Does the entry have a link that contains the details? Just add the link, if
+  you think it needs more details, put them in the content that shows up on the
+  link.
+..
+  Are you thinking about generating this? Don't put anything at all.
+..
+  Does the thing require the user to change their application? Put it on the
+  migration guide instead. (TODO: move the removed APIs section in the
+  migration guide)
+
 .. _zephyr_4.1:
 
-Zephyr 4.1.0 (Working Draft)
-############################
+Zephyr 4.1.0
+############
 
 We are pleased to announce the release of Zephyr version 4.1.0.
-
 Major enhancements with this release include:
 
+**Performance improvements**
+  Multiple performance improvements of core Zephyr kernel functions have been implemented,
+  benefiting all supported hardware architectures.
+
+  An official port of the :zephyr_file:`thread_metric <tests/benchmarks/thread_metric>` RTOS
+  benchmark has also been added to make it easier for developers to measure the performance of
+  Zephyr on their hardware and compare it to other RTOSes.
+
+**Experimental support for IAR compiler**
+  :ref:`toolchain_iar_arm` can now be used to build Zephyr applications. This is an experimental
+  feature that is expected to be improved in future releases.
+
+**Initial support for Rust on Zephyr**
+  It is now possible to write Zephyr applications in Rust. :ref:`language_rust` is available through
+  an optional Zephyr module, and several code samples are available as a starting point.
+
+**USB MIDI Class Driver**
+  Introduction of a new :ref:`USB MIDI 2.0 <usbd_midi2>` device driver, allowing Zephyr devices to
+  communicate with MIDI controllers and instruments over USB.
+
+**Expanded Board Support**
+  Support for 70 :ref:`new boards <boards_added_in_zephyr_4_1>` and 11
+  :ref:`new shields <shields_added_in_zephyr_4_1>` has been added in this release.
+
+  This includes highly popular boards such as :zephyr:board:`rpi_pico2` and
+  :zephyr:board:`ch32v003evt`, several boards with CAN+USB capabilities making them good candidates
+  for running the Zephyr-based open source `CANnectivity`_ firmware, and dozens of other boards
+  across all supported architectures.
+
+.. _CANnectivity: https://cannectivity.org/
+
 An overview of the changes required or recommended when migrating your application from Zephyr
 v4.0.0 to Zephyr v4.1.0 can be found in the separate :ref:`migration guide<migration_4.1>`.
 
@@ -16,421 +70,930 @@ The following sections provide detailed lists of changes by component.
 
 Security Vulnerability Related
 ******************************
+
 The following CVEs are addressed by this release:
 
+* :cve:`2025-1673` `Zephyr project bug tracker GHSA-jjhx-rrh4-j8mx
+  <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-jjhx-rrh4-j8mx>`_
+
+* :cve:`2025-1674` `Zephyr project bug tracker GHSA-x975-8pgf-qh66
+  <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-x975-8pgf-qh66>`_
+
+* :cve:`2025-1675` `Zephyr project bug tracker GHSA-2m84-5hfw-m8v4
+  <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-2m84-5hfw-m8v4>`_
+
 More detailed information can be found in:
 https://docs.zephyrproject.org/latest/security/vulnerabilities.html
 
 API Changes
 ***********
 
- * Stream Flash initialization function :c:func:`stream_flash_init` no longer does
-   device size autodetection and instead requires user to explicitly provide size
-   of area available for Stream Flash instance operation.
-
-Removed APIs in this release
-============================
+Removed APIs and options
+========================
 
- * The deprecated Bluetooth HCI driver API has been removed. It has been replaced by a
-   :c:group:`new API<bt_hci_api>` that follows the normal Zephyr driver model.
- * The deprecated ``CAN_MAX_STD_ID`` (replaced by :c:macro:`CAN_STD_ID_MASK`) and ``CAN_MAX_EXT_ID``
-   (replaced by :c:macro:`CAN_EXT_ID_MASK`) CAN API macros have been removed.
- * The deprecated ``can_get_min_bitrate()`` (replaced by :c:func:`can_get_bitrate_min`) and
-   ``can_get_max_bitrate()`` (replaced by :c:func:`can_get_bitrate_max`) CAN API functions have been
-   removed.
- * The deprecated ``can_calc_prescaler()`` CAN API function has been removed.
+* The legacy Bluetooth HCI driver API has been removed. It has been replaced
+  by a :c:group:`new API<bt_hci_api>` that follows the normal Zephyr driver
+  model.
 
-Deprecated in this release
-==========================
+* The ``CAN_MAX_STD_ID`` (replaced by :c:macro:`CAN_STD_ID_MASK`) and
+  ``CAN_MAX_EXT_ID`` (replaced by :c:macro:`CAN_EXT_ID_MASK`) CAN API macros
+  have been removed.
 
-* Deprecated the :c:func:`bt_le_set_auto_conn` API function. Application developers can achieve
-  the same functionality in their application code by reconnecting to the peer when the
-  :c:member:`bt_conn_cb.disconnected` callback is invoked.
+* The ``can_get_min_bitrate()`` (replaced by :c:func:`can_get_bitrate_min`)
+  and ``can_get_max_bitrate()`` (replaced by :c:func:`can_get_bitrate_max`)
+  CAN API functions have been removed.
 
-* Deprecated TinyCrypt library. The reasons for this are (:github:`43712`):
+* The ``can_calc_prescaler()`` CAN API function has been removed.
 
-  * The upstream version of this library is no longer maintained.
-  * Reducing the number of cryptographic libraries in Zephyr to reduce maintenance overhead.
-  * The PSA Crypto API is the recommended cryptographic library for Zephyr.
+* The :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` option has been
+  removed.  It was a legacy option and was used to allow user to call BSD
+  socket API while not enabling POSIX API.  This removal means that in order
+  to use POSIX API socket calls, one needs to enable the
+  :kconfig:option:`CONFIG_POSIX_API` option.  If the application does not want
+  or is not able to enable that option, then the socket API calls need to be
+  prefixed by a ``zsock_`` string.
 
-Architectures
-*************
+* Removed ``video_pix_fmt_bpp()`` function that was returning a *byte* count
+  and only supported 8-bit depth to :c:func:`video_bits_per_pixel()` returning
+  the *bit* count and supporting any color depth.
 
-* Common
+* The ``video_stream_start()`` and ``video_stream_stop()`` driver APIs have been
+  replaced by ``video_set_stream()``.
 
-  * Introduced :kconfig:option:`CONFIG_ARCH_HAS_CUSTOM_CURRENT_IMPL`, which can be selected when
-    an architecture implements :c:func:`arch_current_thread` and
-    :c:func:`arch_current_thread_set` functions for faster retrieval of the current CPU's thread
-    pointer. When enabled, the ``_current`` symbol will be routed to
-    :c:func:`arch_current_thread` (:github:`80716`).
+* :kconfig:option:`CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO`
 
-* ARC
+* The :kconfig:option:`CONFIG_PM_DEVICE_RUNTIME_EXCLUSIVE` option has been removed
+  after being deprecated in favor of :kconfig:option:`CONFIG_PM_DEVICE_SYSTEM_MANAGED`.
 
-* ARM
+* The ``z_pm_save_idle_exit()`` PM API function has been removed.
 
-* ARM64
+* Struct ``z_arch_esf_t`` has been removed. Use ``struct arch_esf`` instead.
 
-* RISC-V
+* The following networking options have been removed:
 
-  * Implements :c:func:`arch_current_thread_set` & :c:func:`arch_current_thread`, which can be enabled
-    by :kconfig:option:`CONFIG_RISCV_CURRENT_VIA_GP` (:github:`80716`).
+    * ``CONFIG_NET_PKT_BUF_DATA_POOL_SIZE``
+    * ``CONFIG_NET_TCP_ACK_TIMEOUT``
 
-* Xtensa
 
-* native/POSIX
+Deprecated APIs and options
+===========================
 
-  * :kconfig:option:`CONFIG_NATIVE_APPLICATION` has been deprecated.
-  * For the native_sim target :kconfig:option:`CONFIG_NATIVE_SIM_NATIVE_POSIX_COMPAT` has been
-    switched to ``n`` by default, and this option has been deprecated.
+* the :c:func:`bt_le_set_auto_conn` API function. Application developers can achieve
+  the same functionality in their application code by reconnecting to the peer when the
+  :c:member:`bt_conn_cb.disconnected` callback is invoked.
 
-Kernel
-******
+* :kconfig:option:`CONFIG_NATIVE_APPLICATION` has been deprecated.
 
-Bluetooth
-*********
+* Deprecated the :c:func:`stream_flash_erase_page` from Stream Flash API. The same functionality
+  can be achieved using :c:func:`flash_area_erase` or :c:func:`flash_erase`. Nevertheless
+  erasing of a device, while stream flash is supposed to do so, as configured, will result in
+  data lost from stream flash. There are only two situations where device should be erased
+  directly:
 
-* Audio
+  1. when Stream Flash is not configured to do erase on its own
+  2. when erase is used for removal of a data prior or after Stream Flash uses the designated area.
 
-* Host
+* The pipe API has been reworked.
+  The new API is enabled by default when ``CONFIG_MULTITHREADING`` is set.
 
-  * :kconfig:option:`CONFIG_BT_BUF_ACL_RX_COUNT` has been deprecated and
-    :kconfig:option:`CONFIG_BT_BUF_ACL_RX_COUNT_EXTRA` has been added.
+  * Deprecates the ``CONFIG_PIPES`` Kconfig option.
+  * Introduces the ``k_pipe_close(..)`` function.
+  * ``k_pipe_put(..)`` translates to ``k_pipe_write(..)``.
+  * ``k_pipe_get(..)`` translates to ``k_pipe_read(..)``.
+  * ``k_pipe_flush(..)`` & ``k_pipe_buffer_flush()`` can be translated to ``k_pipe_reset(..)``.
 
-  * The ECDH HCI command/event emulation layer has been removed, meaning the host will now always
-    do direct calls to PSA to perform these operations.
+  * Dynamic allocation of pipes is no longer supported.
 
-* HCI Drivers
+    - ``k_pipe_alloc_init(..)`` API has been removed.
+    - ``k_pipe_cleanup(..)`` API has been removed.
 
-* Mesh
+  * Querying the number of bytes in the pipe is no longer supported.
 
-  * Introduced a :c:member:`bt_mesh_health_cli::update` callback which is used to update the message
-    published periodically.
+    - ``k_pipe_read_avail(..)`` API has been removed.
+    - ``k_pipe_write_avail(..)`` API has been removed.
 
-Boards & SoC Support
-********************
 
-* Added support for these SoC series:
+* For the native_sim target :kconfig:option:`CONFIG_NATIVE_SIM_NATIVE_POSIX_COMPAT` has been
+  switched to ``n`` by default, and this option has been deprecated.
 
-  * Added Raspberry Pi RP2350
+* :kconfig:option:`CONFIG_BT_BUF_ACL_RX_COUNT`
 
-* Made these changes in other SoC series:
+* All HWMv1 board name aliases which were added as deprecated in v3.7 are now removed
+  (:github:`82247`).
 
-* Added support for these boards:
+* The TinyCrypt library has been deprecated as the upstream version is no longer maintained.
+  PSA Crypto API is now the recommended cryptographic library for Zephyr.
 
-   * :zephyr:board:`Raspberry Pi Pico 2 <rpi_pico2>`: ``rpi_pico2``
-   * :zephyr:board:`Adafruit QT Py ESP32-S3 <adafruit_qt_py_esp32s3>`: ``adafruit_qt_py_esp32s3``
+* The :kconfig:option:`CONFIG_BT_DIS_MODEL` and :kconfig:option:`CONFIG_BT_DIS_MANUF` have been
+  deprecated. Application developers can achieve the same configuration by using the new
+  :kconfig:option:`CONFIG_BT_DIS_MODEL_NUMBER_STR` and
+  :kconfig:option:`CONFIG_BT_DIS_MANUF_NAME_STR` Kconfig options.
 
-* Made these board changes:
+New APIs and options
+====================
 
-  * All HWMv1 board name aliases which were added as deprecated in v3.7 are now removed
-    (:github:`82247`).
-  * ``mimxrt1050_evk`` and ``mimxrt1060_evk`` revisions for ``qspi`` and ``hyperflash`` have been
-    converted into variants. ``mimxrt1060_evkb`` has been converted into revision ``B`` of
-    ``mimxrt1060_evk``.
-  * Enabled USB, RTC on NXP ``frdm_mcxn236``
+..
+  Link to new APIs here, in a group if you think it's necessary, no need to get
+  fancy just list the link, that should contain the documentation. If you feel
+  like you need to add more details, add them in the API documentation code
+  instead.
 
-* Added support for the following shields:
+* Architectures
 
-Build system and Infrastructure
-*******************************
+  * :kconfig:option:`CONFIG_ARCH_HAS_CUSTOM_CURRENT_IMPL`
+  * :kconfig:option:`CONFIG_RISCV_CURRENT_VIA_GP`
 
-* Space-separated lists support has been removed from Twister configuration
-  files. This feature was deprecated a long time ago. Projects that do still use
-  them can use the :zephyr_file:`scripts/utils/twister_to_list.py` script to
-  automatically migrate Twister configuration files.
+* Bluetooth
 
-* Twister
+  * Audio
 
-  * Test Case names for Ztest now include Ztest suite name, so the resulting identifier has
-    three sections and looks like: ``<test_scenario_name>.<ztest_suite_name>.<ztest_name>``.
-    These extended identifiers are used in log output, twister.json and testplan.json,
-    as well as for ``--sub-test`` command line parameters (:github:`80088`).
-  * The ``--no-detailed-test-id`` command line option also shortens Ztest Test Case names excluding
-    its Test Scenario name prefix which is the same as the parent Test Suite id (:github:`82302`).
-    Twister XML reports have full testsuite name as ``testcase.classname property`` resolving
-    possible duplicate testcase elements in ``twister_report.xml`` testsuite container.
+    * :c:func:`bt_bap_broadcast_source_register_cb`
+    * :c:func:`bt_bap_broadcast_source_unregister_cb`
+    * :c:func:`bt_cap_commander_distribute_broadcast_code`
+    * ``bt_ccp`` API (in progress)
+    * :c:func:`bt_pacs_register`
+    * :c:func:`bt_pacs_unregister`
 
-Drivers and Sensors
-*******************
+  * Host
 
-* ADC
+    * :c:func:`bt_conn_is_type`
 
-* Battery
+  * Mesh
 
-* CAN
+    * :c:member:`bt_mesh_health_cli::update` callback can be used to periodically update the message
+      published by the Health Client.
 
-* Charger
+  * Services
 
-* Clock control
+    * The :kconfig:option:`CONFIG_BT_DIS_MODEL_NUMBER` and
+      :kconfig:option:`CONFIG_BT_DIS_MANUF_NAME` Kconfig options can be used to control the
+      presence of the Model Number String and Manufacturer Name String characteristics inside
+      the Device Information Service (DIS). The :kconfig:option:`CONFIG_BT_DIS_MODEL_NUMBER_STR`
+      and :kconfig:option:`CONFIG_BT_DIS_MANUF_NAME_STR` Kconfig options are now used to set the
+      string values in these characteristics. They replace the functionality of the deprecated
+      :kconfig:option:`CONFIG_BT_DIS_MODEL` and :kconfig:option:`CONFIG_BT_DIS_MANUF` Kconfigs.
 
-* Counter
+* Build system
 
-* DAC
+  * Sysbuild
 
-* Disk
+    * The newly introduced MCUboot swap using offset mode can be selected from sysbuild by using
+      ``SB_CONFIG_MCUBOOT_MODE_SWAP_USING_OFFSET``, this mode is experimental.
 
-* Display
+* Crypto
 
-  * Added flag ``frame_incomplete`` to ``display_write`` that indicates whether a write is the last
-    write of the frame, allowing display drivers to implement double buffering / tearing enable
-    signal handling (:github:`81250`)
-  * Added ``frame_incomplete`` handling to SDL display driver (:dtcompatible:`zephyr,sdl-dc`)
-    (:github:`81250`)
-  * Added transparency support to SDL display driver (:dtcompatible:`zephyr,sdl-dc`) (:github:`81184`)
+  * :kconfig:option:`CONFIG_MBEDTLS_PSA_STATIC_KEY_SLOTS`
+  * :kconfig:option:`CONFIG_MBEDTLS_PSA_KEY_SLOT_COUNT`
 
-* Ethernet
+* I3C
 
-* Flash
+  * :kconfig:option:`CONFIG_I3C_TARGET_BUFFER_MODE`
+  * :kconfig:option:`CONFIG_I3C_RTIO`
+  * :c:func:`i3c_ibi_hj_response`
+  * :c:func:`i3c_ccc_do_getacccr`
+  * :c:func:`i3c_device_controller_handoff`
 
-  * NXP MCUX FlexSPI: Add support for 4-byte addressing mode of Micron MT25Q flash family (:github:`82532`)
+* Management
 
-* FPGA
+  * hawkBit
 
-  * Extracted from :dtcompatible:`lattice,ice40-fpga` the compatible and driver for
-    :dtcompatible:`lattice,ice40-fpga-bitbang`. This replaces the original ``load_mode`` property from
-    the binding, which selected either the SPI or GPIO bitbang load mode.
+    * The hawkBit subsystem now uses the State Machine Framework internally.
+    * :kconfig:option:`CONFIG_HAWKBIT_TENANT`
+    * :kconfig:option:`CONFIG_HAWKBIT_EVENT_CALLBACKS`
+    * :kconfig:option:`CONFIG_HAWKBIT_SAVE_PROGRESS`
 
-* GNSS
+  * MCUmgr
 
-* GPIO
+    * Image management :c:macro:`MGMT_EVT_OP_IMG_MGMT_DFU_CONFIRMED` now has image data field
+      :c:struct:`img_mgmt_image_confirmed`.
 
-* Hardware info
+* MCUboot
 
-* I2C
+  * Signed hex files where an encryption key Kconfig is set now have the encrypted flag set in
+    the image header.
 
-* I2S
+* Networking:
 
-* I3C
+  * CoAP
 
-* Input
+    * :c:func:`coap_client_cancel_request`
 
-* LED
+  * DHCP
 
-  * Added a new set of devicetree based LED APIs, see :c:struct:`led_dt_spec`.
-  * lp5569: added use of auto-increment functionality.
-  * lp5569: implemented ``write_channels`` api.
-  * lp5569: demonstrate ``led_write_channels`` in the sample.
+    * :kconfig:option:`CONFIG_NET_DHCPV4_SERVER_OPTION_ROUTER`
+    * :kconfig:option:`CONFIG_NET_DHCPV4_OPTION_DNS_ADDRESS`
+    * :kconfig:option:`CONFIG_NET_DHCPV6_OPTION_DNS_ADDRESS`
 
-* LED Strip
+  * DNS
 
-* LoRa
+    * :kconfig:option:`CONFIG_MDNS_RESPONDER_PROBE`
 
-* Mailbox
+  * Ethernet
 
-* MDIO
+    * Allow user to specify protocol extensions when receiving data from Ethernet network.
+      This makes it possible to register a handler for Ethernet protocol type without changing
+      core Zephyr network code. :c:macro:`NET_L3_REGISTER`
+    * :kconfig:option:`CONFIG_NET_L2_ETHERNET_RESERVE_HEADER`
 
-* MFD
+  * HTTP
 
-* Modem
+    * Extended :c:macro:`HTTP_SERVICE_DEFINE` to allow to specify a default
+      fallback resource handler.
+    * :kconfig:option:`CONFIG_HTTP_SERVER_REPORT_FAILURE_REASON`
+    * :kconfig:option:`CONFIG_HTTP_SERVER_TLS_USE_ALPN`
 
-* MIPI-DBI
+  * IPv4
 
-* MSPI
+    * :kconfig:option:`CONFIG_NET_IPV4_PMTU`
 
-* Pin control
+  * IPv6
 
-  * Added new driver for Silabs Series 2 (:dtcompatible:`silabs,dbus-pinctrl`).
+    * :kconfig:option:`CONFIG_NET_IPV6_PMTU`
 
-* PWM
+  * LwM2M
 
-* Regulators
+    * :c:func:`lwm2m_pull_context_set_sockopt_callback`
 
-* Reset
+  * MQTT-SN
 
-* RTC
+    * Added Gateway Advertisement and Discovery support:
 
-* RTIO
+      * :c:func:`mqtt_sn_add_gw`
+      * :c:func:`mqtt_sn_search`
 
-* SDHC
+  * OpenThread
 
-* Sensors
+    * :kconfig:option:`CONFIG_OPENTHREAD_WAKEUP_COORDINATOR`
+    * :kconfig:option:`CONFIG_OPENTHREAD_WAKEUP_END_DEVICE`
+    * :kconfig:option:`CONFIG_OPENTHREAD_PLATFORM_MESSAGE_MANAGEMENT`
+    * :kconfig:option:`CONFIG_OPENTHREAD_TCAT_MULTIRADIO_CAPABILITIES`
 
-* Serial
+  * Sockets
 
-* SPI
+    * Added support for new socket options:
 
-* Stepper
+      * :c:macro:`IP_LOCAL_PORT_RANGE`
+      * :c:macro:`IP_MULTICAST_IF`
+      * :c:macro:`IPV6_MULTICAST_IF`
+      * :c:macro:`IP_MTU`
+      * :c:macro:`IPV6_MTU`
 
-  * Added driver for ADI TMC2209. :dtcompatible:`adi,tmc2209`.
-  * Added driver for TI DRV8424. :dtcompatible:`ti,drv8424`.
-  * Added :kconfig:option:`CONFIG_STEP_DIR_STEPPER` to enable common functions for step/dir steppers.
+  * Other
 
-* USB
+    * :kconfig:option:`CONFIG_NET_STATISTICS_VIA_PROMETHEUS`
 
 * Video
 
-  * Changed :file:`include/zephyr/drivers/video-controls.h` to have control IDs (CIDs) matching
-    those present in the Linux kernel.
+  * :c:func:`video_set_stream()` driver API has replaced :c:func:`video_stream_start()` and
+    :c:func:`video_stream_stop()` driver APIs.
 
-* Watchdog
+* Other
 
-  * Added :kconfig:option:`CONFIG_HAS_WDT_NO_CALLBACKS` which drivers select when they do not support
-    a callback being provided in :c:struct:`wdt_timeout_cfg`.
+  * :kconfig:option:`CONFIG_BT_BUF_ACL_RX_COUNT_EXTRA`
+  * :c:macro:`DT_ANY_INST_HAS_BOOL_STATUS_OKAY`
+  * :c:struct:`led_dt_spec`
+  * :kconfig:option:`CONFIG_STEP_DIR_STEPPER`
 
-* Wi-Fi
+.. _boards_added_in_zephyr_4_1:
 
-Networking
+New Boards
 **********
+..
+  You may update this list as you contribute a new board during the release cycle, in order to make
+  it visible to people who might be looking at the working draft of the release notes. However, note
+  that this list will be recomputed at the time of the release, so you don't *have* to update it.
+  In any case, just link the board, further details go in the board description.
 
-* ARP:
+* Adafruit Industries, LLC
 
-* CoAP:
+   * :zephyr:board:`adafruit_feather_m4_express` (``adafruit_feather_m4_express``)
+   * :zephyr:board:`adafruit_macropad_rp2040` (``adafruit_macropad_rp2040``)
+   * :zephyr:board:`adafruit_qt_py_esp32s3` (``adafruit_qt_py_esp32s3``)
 
-* Connection manager:
+* Advanced Micro Devices (AMD), Inc.
 
-* DHCPv4:
+   * :zephyr:board:`acp_6_0_adsp` (``acp_6_0_adsp``)
 
-* DHCPv6:
+* Analog Devices, Inc.
 
-* DNS/mDNS/LLMNR:
+   * :zephyr:board:`ad_swiot1l_sl` (``ad_swiot1l_sl``)
+   * :zephyr:board:`max32650evkit` (``max32650evkit``)
+   * :zephyr:board:`max32650fthr` (``max32650fthr``)
+   * :zephyr:board:`max32660evsys` (``max32660evsys``)
+   * :zephyr:board:`max78000evkit` (``max78000evkit``)
+   * :zephyr:board:`max78000fthr` (``max78000fthr``)
+   * :zephyr:board:`max78002evkit` (``max78002evkit``)
 
-* gPTP/PTP:
+* Antmicro
 
-* HTTP:
+   * :zephyr:board:`myra_sip_baseboard` (``myra_sip_baseboard``)
 
-* IPSP:
+* BeagleBoard.org Foundation
 
-* IPv4:
+   * :zephyr:board:`beagley_ai` (``beagley_ai``)
 
-* IPv6:
+* FANKE Technology Co., Ltd.
 
-* LwM2M:
+   * :zephyr:board:`fk750m1_vbt6` (``fk750m1_vbt6``)
 
-* Misc:
+* Google, Inc.
 
-* MQTT:
+   * :zephyr:board:`google_icetower` (``google_icetower``)
+   * :zephyr:board:`google_quincy` (``google_quincy``)
 
-* Network Interface:
+* Infineon Technologies
 
-* OpenThread:
+   * :zephyr:board:`cy8ckit_062s2_ai` (``cy8ckit_062s2_ai``)
 
-  * Removed the implicit enabling of the :kconfig:option:`CONFIG_NVS` Kconfig option by the :kconfig:option:`CONFIG_NET_L2_OPENTHREAD` symbol.
+* Khadas
 
-* PPP
+   * :zephyr:board:`khadas_edge2` (``khadas_edge2``)
 
-* Shell:
+* Lilygo Shenzhen Xinyuan Electronic Technology Co., Ltd
 
-* Sockets:
+   * :zephyr:board:`ttgo_t7v1_5` (``ttgo_t7v1_5``)
+   * :zephyr:board:`ttgo_t8s3` (``ttgo_t8s3``)
 
-  * The deprecated :kconfig:option:`CONFIG_NET_SOCKETS_POSIX_NAMES` option has been removed.
-    It was a legacy option and was used to allow user to call BSD socket API while not enabling POSIX API.
-    This removal means that in order to use POSIX API socket calls, one needs to enable the
-    :kconfig:option:`CONFIG_POSIX_API` option.
-    If the application does not want or is not able to enable that option, then the socket API
-    calls need to be prefixed by a ``zsock_`` string.
+* M5Stack
 
-* Syslog:
+   * :zephyr:board:`m5stack_cores3` (``m5stack_cores3``)
 
-* TCP:
+* Makerbase Co., Ltd.
 
-* Websocket:
+   * :zephyr:board:`mks_canable_v20` (``mks_canable_v20``)
 
-* Wi-Fi:
+* MediaTek Inc.
 
-  * hostap: Removed the unused default Crypto module :kconfig:option:`CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO` Kconfig option.
+   * MT8186 (``mt8186``)
+   * MT8188 (``mt8188``)
+   * MT8196 (``mt8196``)
 
-* zperf:
+* NXP Semiconductors
 
-USB
-***
+   * :zephyr:board:`frdm_mcxw72` (``frdm_mcxw72``)
+   * :zephyr:board:`imx91_evk` (``imx91_evk``)
+   * :zephyr:board:`mcxw72_evk` (``mcxw72_evk``)
+   * :zephyr:board:`mimxrt700_evk` (``mimxrt700_evk``)
 
-Devicetree
-**********
+* Nordic Semiconductor
 
-* Added :c:macro:`DT_ANY_INST_HAS_BOOL_STATUS_OKAY`.
+   * :zephyr:board:`nrf54l09pdk` (``nrf54l09pdk``)
 
-Kconfig
-*******
+* Norik Systems
 
-Libraries / Subsystems
-**********************
+   * :zephyr:board:`octopus_io_board` (``octopus_io_board``)
+   * :zephyr:board:`octopus_som` (``octopus_som``)
 
-* Debug
+* Panasonic Corporation
 
-* Demand Paging
+   * :zephyr:board:`panb511evb` (``panb511evb``)
 
-* Formatted output
+* Peregrine Consultoria e Servicos
 
-* Management
+   * :zephyr:board:`sam4l_wm400_cape` (``sam4l_wm400_cape``)
 
-* Logging
+* Qorvo, Inc.
 
-* Modem modules
+   * :zephyr:board:`decawave_dwm3001cdk` (``decawave_dwm3001cdk``)
 
-* Power management
+* RAKwireless Technology Limited
 
-* Crypto
+   * :zephyr:board:`rak3172` (``rak3172``)
+
+* Raspberry Pi Foundation
 
-  * The Kconfig symbol :kconfig:option:`CONFIG_MBEDTLS_PSA_STATIC_KEY_SLOTS` was
-    added to allow Mbed TLS to use statically allocated buffers to store key material
-    in its PSA Crypto core instead of heap-allocated ones. This can help reduce
-    (or remove, if no other component makes use of it) heap memory requirements
-    from the final application.
+   * :zephyr:board:`rpi_pico2` (``rpi_pico2``)
 
-  * The Kconfig symbol :kconfig:option:`CONFIG_MBEDTLS_PSA_KEY_SLOT_COUNT` was
-    added to allow selecting the number of key slots available in the Mbed TLS
-    implementation of the PSA Crypto core. It defaults to 16. Since each
-    slot consumes RAM memory even if unused, this value can be tweaked in order
-    to minimize RAM usage.
+* Realtek Semiconductor Corp.
 
-* CMSIS-NN
+   * :zephyr:board:`rts5912_evb` (``rts5912_evb``)
 
-* FPGA
+* Renesas Electronics Corporation
 
-* Random
+   * :zephyr:board:`ek_ra2l1` (``ek_ra2l1``)
+   * :zephyr:board:`ek_ra4l1` (``ek_ra4l1``)
+   * :zephyr:board:`ek_ra4m1` (``ek_ra4m1``)
+   * :zephyr:board:`fpb_ra4e1` (``fpb_ra4e1``)
+   * :zephyr:board:`rzg3s_smarc` (``rzg3s_smarc``)
+   * :zephyr:board:`voice_ra4e1` (``voice_ra4e1``)
 
-* SD
+* STMicroelectronics
 
-* State Machine Framework
+   * :zephyr:board:`nucleo_c071rb` (``nucleo_c071rb``)
+   * :zephyr:board:`nucleo_f072rb` (``nucleo_f072rb``)
+   * :zephyr:board:`nucleo_h7s3l8` (``nucleo_h7s3l8``)
+   * :zephyr:board:`nucleo_n657x0_q` (``nucleo_n657x0_q``)
+   * :zephyr:board:`nucleo_wb07cc` (``nucleo_wb07cc``)
+   * :zephyr:board:`stm32f413h_disco` (``stm32f413h_disco``)
+   * :zephyr:board:`stm32n6570_dk` (``stm32n6570_dk``)
 
-* Storage
+* Seeed Technology Co., Ltd
 
-  * Shell: :kconfig:option:`CONFIG_FILE_SYSTEM_SHELL_MOUNT_COMMAND` was added,
-    allowing the mount subcommand to be optionally disabled. This can reduce
-    flash and RAM usage since it requires the heap to be present.
+   * :zephyr:board:`xiao_esp32c6` (``xiao_esp32c6``)
 
-* Task Watchdog
+* Shenzhen Fuyuansheng Electronic Technology Co., Ltd.
 
-* POSIX API
+   * :zephyr:board:`ucan` (``ucan``)
 
-* LoRa/LoRaWAN
+* Silicon Laboratories
 
-* ZBus
+   * :zephyr:board:`siwx917_rb4338a` (``siwx917_rb4338a``)
+   * :zephyr:board:`xg23_rb4210a` (``xg23_rb4210a``)
+   * :zephyr:board:`xg24_ek2703a` (``xg24_ek2703a``)
+   * :zephyr:board:`xg29_rb4412a` (``xg29_rb4412a``)
 
-HALs
-****
+* Texas Instruments
 
-* Nordic
+   * :zephyr:board:`lp_em_cc2340r5` (``lp_em_cc2340r5``)
 
-* STM32
+* Toradex AG
 
-* ADI
+   * :zephyr:board:`verdin_imx8mm` (``verdin_imx8mm``)
 
-* Espressif
+* Waveshare Electronics
 
-MCUboot
-*******
+   * :zephyr:board:`rp2040_zero` (``rp2040_zero``)
 
-OSDP
-****
+* WeAct Studio
 
-Trusted Firmware-M
-******************
+   * :zephyr:board:`mini_stm32h7b0` (``mini_stm32h7b0``)
+   * :zephyr:board:`weact_stm32h5_core` (``weact_stm32h5_core``)
 
-LVGL
-****
+* WinChipHead
 
-* Added ``frame_incomplete`` support to indicate whether a write is the last
-  write of the frame (:github:`81250`)
+   * :zephyr:board:`ch32v003evt` (``ch32v003evt``)
 
-Tests and Samples
-*****************
+* Würth Elektronik GmbH.
 
-* Fixed incorrect alpha values in :zephyr_file:`samples/drivers/display`. (:github:`81184`)
-* Added :zephyr_file:`samples/modules/lvgl/screen_transparency`. (:github:`81184`)
+   * :zephyr:board:`we_oceanus1ev` (``we_oceanus1ev``)
+   * :zephyr:board:`we_orthosie1ev` (``we_orthosie1ev``)
 
-Issue Related Items
-*******************
+* Others
 
-Known Issues
+   * :zephyr:board:`canbardo` (``canbardo``)
+   * :zephyr:board:`candlelight` (``candlelight``)
+   * :zephyr:board:`candlelightfd` (``candlelightfd``)
+   * :zephyr:board:`esp32c3_supermini` (``esp32c3_supermini``)
+   * :zephyr:board:`promicro_nrf52840` (``promicro_nrf52840``)
+
+.. _shields_added_in_zephyr_4_1:
+
+New shields
 ============
+
+  * :ref:`Abrobot ESP32 C3 OLED Shield <abrobot_esp32c3oled_shield>`
+  * :ref:`Adafruit Adalogger Featherwing Shield <adafruit_adalogger_featherwing_shield>`
+  * :ref:`Adafruit AW9523 GPIO Expander and LED Driver <adafruit_aw9523>`
+  * :ref:`MikroElektronika ETH 3 Click <mikroe_eth3_click>`
+  * :ref:`P3T1755DP Arduino® Shield Evaluation Board <p3t1755dp_ard_i2c_shield>`
+  * :ref:`P3T1755DP Arduino® Shield Evaluation Board <p3t1755dp_ard_i3c_shield>`
+  * :ref:`Digilent Pmod SD <pmod_sd>`
+  * :ref:`Renesas DA14531 Pmod Board <renesas_us159_da14531evz_shield>`
+  * :ref:`RTKMIPILCDB00000BE MIPI Display <rtkmipilcdb00000be>`
+  * :ref:`Seeed W5500 Ethernet Shield <seeed_w5500>`
+  * :ref:`ST B-CAMS-OMV-MB1683 <st_b_cams_omv_mb1683>`
+
+New Drivers
+***********
+..
+  Same as above for boards, this will also be recomputed at the time of the release.
+  Just link the driver, further details go in the binding description
+
+* :abbr:`ADC (Analog to Digital Converter)`
+
+   * :dtcompatible:`adi,ad4114-adc`
+   * :dtcompatible:`adi,ad7124-adc`
+   * :dtcompatible:`st,stm32n6-adc`
+   * :dtcompatible:`ti,ads114s06`
+   * :dtcompatible:`ti,ads124s06`
+   * :dtcompatible:`ti,ads124s08`
+   * :dtcompatible:`ti,ads131m02`
+   * :dtcompatible:`ti,tla2022`
+   * :dtcompatible:`ti,tla2024`
+
+* ARM architecture
+
+   * :dtcompatible:`nxp,nbu`
+
+* Audio
+
+   * :dtcompatible:`cirrus,cs43l22`
+   * :dtcompatible:`intel,adsp-mic-privacy`
+
+* Bluetooth
+
+   * :dtcompatible:`renesas,bt-hci-da1453x`
+   * :dtcompatible:`silabs,siwx91x-bt-hci`
+   * :dtcompatible:`st,hci-stm32wb0`
+
+* Charger
+
+   * :dtcompatible:`nxp,pf1550-charger`
+
+* Clock control
+
+   * :dtcompatible:`atmel,sam0-gclk`
+   * :dtcompatible:`atmel,sam0-mclk`
+   * :dtcompatible:`atmel,sam0-osc32kctrl`
+   * :dtcompatible:`nordic,nrf-hsfll-global`
+   * :dtcompatible:`nuvoton,npcm-pcc`
+   * :dtcompatible:`realtek,rts5912-sccon`
+   * :dtcompatible:`renesas,rz-cpg`
+   * :dtcompatible:`st,stm32n6-cpu-clock-mux`
+   * :dtcompatible:`st,stm32n6-hse-clock`
+   * :dtcompatible:`st,stm32n6-ic-clock-mux`
+   * :dtcompatible:`st,stm32n6-pll-clock`
+   * :dtcompatible:`st,stm32n6-rcc`
+   * :dtcompatible:`wch,ch32v00x-hse-clock`
+   * :dtcompatible:`wch,ch32v00x-hsi-clock`
+   * :dtcompatible:`wch,ch32v00x-pll-clock`
+   * :dtcompatible:`wch,rcc`
+
+* Comparator
+
+   * :dtcompatible:`silabs,acmp`
+
+* Counter
+
+   * :dtcompatible:`adi,max32-rtc-counter`
+   * :dtcompatible:`renesas,rz-gtm-counter`
+
+* CPU
+
+   * :dtcompatible:`wch,qingke-v2`
+
+* :abbr:`DAC (Digital to Analog Converter)`
+
+   * :dtcompatible:`adi,max22017-dac`
+   * :dtcompatible:`renesas,ra-dac`
+   * :dtcompatible:`renesas,ra-dac-global`
+
+* :abbr:`DAI (Digital Audio Interface)`
+
+   * :dtcompatible:`mediatek,afe`
+   * :dtcompatible:`nxp,dai-micfil`
+
+* Display
+
+   * :dtcompatible:`ilitek,ili9806e-dsi`
+   * :dtcompatible:`renesas,ra-glcdc`
+   * :dtcompatible:`solomon,ssd1309fb`
+
+* :abbr:`DMA (Direct Memory Access)`
+
+   * :dtcompatible:`infineon,cat1-dma`
+   * :dtcompatible:`nxp,sdma`
+   * :dtcompatible:`silabs,ldma`
+   * :dtcompatible:`silabs,siwx91x-dma`
+   * :dtcompatible:`xlnx,axi-dma-1.00.a`
+   * :dtcompatible:`xlnx,eth-dma`
+
+* :abbr:`DSA (Distributed Switch Architecture)`
+
+   * :dtcompatible:`nxp,netc-switch`
+
+* :abbr:`EEPROM (Electrically Erasable Programmable Read-Only Memory)`
+
+  *  :dtcompatible:`fujitsu,mb85rsxx`
+
+* Ethernet
+
+   * :dtcompatible:`davicom,dm8806-phy`
+   * :dtcompatible:`microchip,lan9250`
+   * :dtcompatible:`microchip,t1s-phy`
+   * :dtcompatible:`microchip,vsc8541`
+   * :dtcompatible:`renesas,ra-ethernet`
+   * :dtcompatible:`sensry,sy1xx-mac`
+
+* Firmware
+
+   * :dtcompatible:`arm,scmi-power`
+
+* Flash controller
+
+   * :dtcompatible:`silabs,siwx91x-flash-controller`
+   * :dtcompatible:`ti,cc23x0-flash-controller`
+
+* :abbr:`FPGA (Field Programmable Gate Array)`
+
+   * :dtcompatible:`lattice,ice40-fpga-base`
+   * :dtcompatible:`lattice,ice40-fpga-bitbang`
+
+* :abbr:`GPIO (General Purpose Input/Output)`
+
+   * :dtcompatible:`adi,max22017-gpio`
+   * :dtcompatible:`adi,max22190-gpio`
+   * :dtcompatible:`awinic,aw9523b-gpio`
+   * :dtcompatible:`ite,it8801-gpio`
+   * :dtcompatible:`microchip,mec5-gpio`
+   * :dtcompatible:`nordic,npm2100-gpio`
+   * :dtcompatible:`nxp,pca6416`
+   * :dtcompatible:`raspberrypi,rp1-gpio`
+   * :dtcompatible:`realtek,rts5912-gpio`
+   * :dtcompatible:`renesas,ra-gpio-mipi-header`
+   * :dtcompatible:`renesas,rz-gpio`
+   * :dtcompatible:`renesas,rz-gpio-int`
+   * :dtcompatible:`sensry,sy1xx-gpio`
+   * :dtcompatible:`silabs,siwx91x-gpio`
+   * :dtcompatible:`silabs,siwx91x-gpio-port`
+   * :dtcompatible:`silabs,siwx91x-gpio-uulp`
+   * :dtcompatible:`st,dcmi-camera-fpu-330zh`
+   * :dtcompatible:`st,mfxstm32l152`
+   * :dtcompatible:`stemma-qt-connector`
+   * :dtcompatible:`ti,cc23x0-gpio`
+   * :dtcompatible:`wch,gpio`
+
+* IEEE 802.15.4 HDLC RCP interface
+
+   * :dtcompatible:`nxp,hdlc-rcp-if`
+   * :dtcompatible:`uart,hdlc-rcp-if`
+
+* :abbr:`I2C (Inter-Integrated Circuit)`
+
+   * :dtcompatible:`nordic,nrf-twis`
+   * :dtcompatible:`nxp,ii2c`
+   * :dtcompatible:`ti,omap-i2c`
+   * :dtcompatible:`ti,tca9544a`
+
+* :abbr:`I3C (Improved Inter-Integrated Circuit)`
+
+   * :dtcompatible:`snps,designware-i3c`
+   * :dtcompatible:`st,stm32-i3c`
+
+* IEEE 802.15.4
+
+   * :dtcompatible:`nxp,mcxw-ieee802154`
+
+* Input
+
+   * :dtcompatible:`cypress,cy8cmbr3xxx`
+   * :dtcompatible:`ite,it8801-kbd`
+   * :dtcompatible:`microchip,cap12xx`
+   * :dtcompatible:`nintendo,nunchuk`
+
+* Interrupt controller
+
+   * :dtcompatible:`renesas,rz-ext-irq`
+   * :dtcompatible:`wch,pfic`
+
+* Mailbox
+
+   * :dtcompatible:`linaro,ivshmem-mbox`
+   * :dtcompatible:`ti,omap-mailbox`
+
+* :abbr:`MDIO (Management Data Input/Output)`
+
+   * :dtcompatible:`microchip,lan865x-mdio`
+   * :dtcompatible:`renesas,ra-mdio`
+   * :dtcompatible:`sensry,sy1xx-mdio`
+
+* Memory controller
+
+   * :dtcompatible:`renesas,ra-sdram`
+
+* :abbr:`MFD (Multi-Function Device)`
+
+   * :dtcompatible:`adi,max22017`
+   * :dtcompatible:`awinic,aw9523b`
+   * :dtcompatible:`ite,it8801-altctrl`
+   * :dtcompatible:`ite,it8801-mfd`
+   * :dtcompatible:`ite,it8801-mfd-map`
+   * :dtcompatible:`maxim,ds3231-mfd`
+   * :dtcompatible:`nordic,npm2100`
+   * :dtcompatible:`nxp,pf1550`
+
+* :abbr:`MIPI DSI (Mobile Industry Processor Interface Display Serial Interface)`
+
+   * :dtcompatible:`renesas,ra-mipi-dsi`
+
+* Miscellaneous
+
+   * :dtcompatible:`nordic,nrf-bicr`
+   * :dtcompatible:`nordic,nrf-ppib`
+   * :dtcompatible:`renesas,ra-external-interrupt`
+
+* :abbr:`MMU / MPU (Memory Management Unit / Memory Protection Unit)`
+
+   * :dtcompatible:`nxp,sysmpu`
+
+* :abbr:`MTD (Memory Technology Device)`
+
+   * :dtcompatible:`nxp,s32-qspi-hyperflash`
+   * :dtcompatible:`nxp,xspi-mx25um51345g`
+   * :dtcompatible:`ti,cc23x0-ccfg-flash`
+
+* Networking
+
+   * :dtcompatible:`silabs,series2-radio`
+
+* :abbr:`PCIe (Peripheral Component Interconnect Express)`
+
+   * :dtcompatible:`brcm,brcmstb-pcie`
+
+* PHY
+
+   * :dtcompatible:`renesas,ra-usbphyc`
+   * :dtcompatible:`st,stm32u5-otghs-phy`
+
+* Pin control
+
+   * :dtcompatible:`realtek,rts5912-pinctrl`
+   * :dtcompatible:`renesas,rzg-pinctrl`
+   * :dtcompatible:`sensry,sy1xx-pinctrl`
+   * :dtcompatible:`silabs,dbus-pinctrl`
+   * :dtcompatible:`silabs,siwx91x-pinctrl`
+   * :dtcompatible:`ti,cc23x0-pinctrl`
+   * :dtcompatible:`wch,afio`
+
+* :abbr:`PWM (Pulse Width Modulation)`
+
+   * :dtcompatible:`atmel,sam0-tc-pwm`
+   * :dtcompatible:`ite,it8801-pwm`
+   * :dtcompatible:`renesas,rz-gpt-pwm`
+   * :dtcompatible:`zephyr,fake-pwm`
+
+* Quad SPI
+
+   * :dtcompatible:`nxp,s32-qspi-sfp-frad`
+   * :dtcompatible:`nxp,s32-qspi-sfp-mdad`
+
+* Regulator
+
+   * :dtcompatible:`nordic,npm2100-regulator`
+   * :dtcompatible:`nxp,pf1550-regulator`
+
+* :abbr:`RNG (Random Number Generator)`
+
+   * :dtcompatible:`nordic,nrf-cracen-ctrdrbg`
+   * :dtcompatible:`nxp,ele-trng`
+   * :dtcompatible:`renesas,ra-sce5-rng`
+   * :dtcompatible:`renesas,ra-sce7-rng`
+   * :dtcompatible:`renesas,ra-sce9-rng`
+   * :dtcompatible:`renesas,ra-trng`
+   * :dtcompatible:`sensry,sy1xx-trng`
+   * :dtcompatible:`silabs,siwx91x-rng`
+   * :dtcompatible:`st,stm32-rng-noirq`
+
+* :abbr:`RTC (Real Time Clock)`
+
+   * :dtcompatible:`epson,rx8130ce-rtc`
+   * :dtcompatible:`maxim,ds1337`
+   * :dtcompatible:`maxim,ds3231-rtc`
+   * :dtcompatible:`microcrystal,rv8803`
+   * :dtcompatible:`ti,bq32002`
+
+* SDHC
+
+   * :dtcompatible:`renesas,ra-sdhc`
+
+* Sensors
+
+   * :dtcompatible:`adi,adxl366`
+   * :dtcompatible:`hc-sr04`
+   * :dtcompatible:`invensense,icm42370p`
+   * :dtcompatible:`invensense,icm42670s`
+   * :dtcompatible:`invensense,icp101xx`
+   * :dtcompatible:`maxim,ds3231-sensor`
+   * :dtcompatible:`melexis,mlx90394`
+   * :dtcompatible:`nordic,npm2100-vbat`
+   * :dtcompatible:`phosense,xbr818`
+   * :dtcompatible:`renesas,hs400x`
+   * :dtcompatible:`sensirion,scd40`
+   * :dtcompatible:`sensirion,scd41`
+   * :dtcompatible:`sensirion,sts4x`
+   * :dtcompatible:`st,lis2duxs12`
+   * :dtcompatible:`st,lsm6dsv16x`
+   * :dtcompatible:`ti,tmag3001`
+   * :dtcompatible:`ti,tmp435`
+   * :dtcompatible:`we,wsen-pads-2511020213301`
+   * :dtcompatible:`we,wsen-pdus-25131308XXXXX`
+   * :dtcompatible:`we,wsen-tids-2521020222501`
+
+* Serial controller
+
+   * :dtcompatible:`microchip,mec5-uart`
+   * :dtcompatible:`realtek,rts5912-uart`
+   * :dtcompatible:`renesas,rz-scif-uart`
+   * :dtcompatible:`silabs,eusart-uart`
+   * :dtcompatible:`silabs,usart-uart`
+   * :dtcompatible:`ti,cc23x0-uart`
+   * :dtcompatible:`wch,usart`
+
+* :abbr:`SPI (Serial Peripheral Interface)`
+
+   * :dtcompatible:`ite,it8xxx2-spi`
+   * :dtcompatible:`nxp,lpspi`
+   * :dtcompatible:`nxp,xspi`
+   * :dtcompatible:`renesas,ra-spi`
+
+* Stepper
+
+   * :dtcompatible:`adi,tmc2209`
+   * :dtcompatible:`ti,drv8424`
+
+* :abbr:`TCPC (USB Type-C Port Controller)`
+
+   * :dtcompatible:`richtek,rt1715`
+
+* Timer
+
+   * :dtcompatible:`mediatek,ostimer64`
+   * :dtcompatible:`realtek,rts5912-rtmr`
+   * :dtcompatible:`realtek,rts5912-slwtimer`
+   * :dtcompatible:`renesas,rz-gpt`
+   * :dtcompatible:`renesas,rz-gtm`
+   * :dtcompatible:`riscv,machine-timer`
+   * :dtcompatible:`ti,cc23x0-systim-timer`
+   * :dtcompatible:`wch,systick`
+
+* USB
+
+   * :dtcompatible:`ambiq,usb`
+   * :dtcompatible:`renesas,ra-udc`
+   * :dtcompatible:`renesas,ra-usbfs`
+   * :dtcompatible:`renesas,ra-usbhs`
+   * :dtcompatible:`zephyr,midi2-device`
+
+* Video
+
+   * :dtcompatible:`zephyr,video-emul-imager`
+   * :dtcompatible:`zephyr,video-emul-rx`
+
+* Watchdog
+
+   * :dtcompatible:`atmel,sam4l-watchdog`
+   * :dtcompatible:`nordic,npm2100-wdt`
+   * :dtcompatible:`nxp,rtwdog`
+
+* Wi-Fi
+
+   * :dtcompatible:`infineon,airoc-wifi`
+   * :dtcompatible:`silabs,siwx91x-wifi`
+
+New Samples
+***********
+
+..
+  Same as above for boards and drivers, this will also be recomputed at the time of the release.
+ Just link the sample, further details go in the sample documentation itself.
+
+* :zephyr:code-sample:`6dof_motion_drdy`
+* :zephyr:code-sample:`ble_cs`
+* :zephyr:code-sample:`bluetooth_ccp_call_control_client`
+* :zephyr:code-sample:`bluetooth_ccp_call_control_server`
+* :zephyr:code-sample:`coresight_stm_sample`
+* :zephyr:code-sample:`dfu-next`
+* :zephyr:code-sample:`i2c-rtio-loopback`
+* :zephyr:code-sample:`lvgl-screen-transparency`
+* :zephyr:code-sample:`mctp_endpoint_sample`
+* :zephyr:code-sample:`mctp_host_sample`
+* :zephyr:code-sample:`openthread-shell`
+* :zephyr:code-sample:`ot-coap`
+* :zephyr:code-sample:`rtc`
+* :zephyr:code-sample:`sensor_batch_processing`
+* :zephyr:code-sample:`sensor_clock`
+* :zephyr:code-sample:`stream_fifo`
+* :zephyr:code-sample:`tdk_apex`
+* :zephyr:code-sample:`tmc50xx`
+* :zephyr:code-sample:`uart`
+* :zephyr:code-sample:`usb-midi2-device`
+* :zephyr:code-sample:`usbd-cdc-acm-console`
+* :zephyr:code-sample:`webusb-next`
+
+Other notable changes
+*********************
+
+..
+  Any more descriptive subsystem or driver changes. Do you really want to write
+  a paragraph or is it enough to link to the api/driver/Kconfig/board page above?
+
+* A header file has been introduced to allocate ID ranges for persistent keys in the PSA Crypto API.
+  It defines the ID ranges allocated to different users of the API (application, subsystems...).
+  Users of the API must now use this header file to construct persistent key IDs.
+  See :zephyr_file:`include/zephyr/psa/key_ids.h` for more information. (:github:`85581`)
+
+* Space-separated lists support has been removed from Twister configuration
+  files. This feature was deprecated a long time ago. Projects that do still use
+  them can use the :zephyr_file:`scripts/utils/twister_to_list.py` script to
+  automatically migrate Twister configuration files.
+
+* Test case names for Ztest now include the Ztest suite name, meaning the resulting identifier has
+  three sections and looks like: ``<test_scenario_name>.<ztest_suite_name>.<ztest_name>``.
+  These extended identifiers are used in log output, twister.json and testplan.json,
+  as well as for ``--sub-test`` command line parameters.
+
+* The ``--no-detailed-test-id`` command line option can be used to shorten the test case name
+  by excluding the test scenario name prefix which is the same as the parent test suite id.
+
+* Added support for HTTP PUT/PATCH/DELETE methods for HTTP server dynamic resources.
+
+* Driver API structures are now available through iterable sections and a new
+  :c:macro:`DEVICE_API_IS` macro has been introduced to allow to check if a device supports a
+  given API. Many shell commands now use this to provide "smarter" auto-completion and only list
+  compatible devices when they expect a device argument.
+
+* Zephyr's :ref:`interactive board catalog <boards>` has been extended to allow searching for boards
+  based on supported hardware features. A new :rst:dir:`zephyr:board-supported-hw` Sphinx directive
+  can now be used in boards' documentation pages to automatically include a list of the hardware
+  features supported by a board, and many boards have already adopted this new feature in their
+  documentation.
diff --git a/doc/releases/release-notes-4.2.rst b/doc/releases/release-notes-4.2.rst
index 1ce44da41d9..0514cf8a77d 100644
--- a/doc/releases/release-notes-4.2.rst
+++ b/doc/releases/release-notes-4.2.rst
@@ -40,8 +40,16 @@ The following sections provide detailed lists of changes by component.
 
 Security Vulnerability Related
 ******************************
+
 The following CVEs are addressed by this release:
 
+* :cve:`2025-27809` `TLS clients may unwittingly skip server authentication
+  <https://mbed-tls.readthedocs.io/en/latest/security-advisories/mbedtls-security-advisory-2025-03-1/>`_
+* :cve:`2025-27810` `Potential authentication bypass in TLS handshake
+  <https://mbed-tls.readthedocs.io/en/latest/security-advisories/mbedtls-security-advisory-2025-03-2/>`_
+
+* :cve:`2025-2962` Under embargo until 2025-06-07
+
 More detailed information can be found in:
 https://docs.zephyrproject.org/latest/security/vulnerabilities.html
 
@@ -51,20 +59,67 @@ API Changes
 Removed APIs and options
 ========================
 
+* Removed the deprecated the ``net_buf_put()`` and ``net_buf_get()`` API functions.
+
+* Removed the deprecated ``include/zephyr/net/buf.h`` header file.
+
+* Removed the ``--disable-unrecognized-section-test`` Twister option. Test has been removed and the
+  option became the default behavior.
+
+* Removed the deprecated ``kscan`` subsystem.
+
+* Removed :dtcompatible:`meas,ms5837` and replaced with :dtcompatible:`meas,ms5837-30ba`
+  and :dtcompatible:`meas,ms5837-02ba`.
+
+* Removed the ``get_ctrl`` video driver API
+
 Deprecated APIs and options
+===========================
 
 * The scheduler Kconfig options CONFIG_SCHED_DUMB and CONFIG_WAITQ_DUMB were
   renamed and deprecated. Use :kconfig:option:`CONFIG_SCHED_SIMPLE` and
   :kconfig:option:`CONFIG_WAITQ_SIMPLE` instead.
 
+* The :kconfig:option:`CONFIG_LWM2M_ENGINE_MESSAGE_HEADER_SIZE` Kconfig option has been removed.
+  The required header size should be included in the message size, configured using
+  :kconfig:option:`CONFIG_LWM2M_COAP_MAX_MSG_SIZE`. Special care should be taken to ensure that
+  used CoAP block size :kconfig:option:`CONFIG_LWM2M_COAP_BLOCK_SIZE` can fit given message size
+  with headers. Previous headroom was 48 bytes.
+
 * TLS credential type ``TLS_CREDENTIAL_SERVER_CERTIFICATE`` was renamed and
   deprecated, use :c:enumerator:`TLS_CREDENTIAL_PUBLIC_CERTIFICATE` instead.
 
-===========================
+* ``arduino_uno_r4_minima`` and ``arduino_uno_r4_wifi`` board targets have been deprecated in favor
+  of a new ``arduino_uno_r4`` board with revisions (``arduino_uno_r4@minima`` and
+  ``arduino_uno_r4@wifi``).
+
+* ``esp32c6_devkitc`` board target has been deprecated and renamed to
+  ``esp32c6_devkitc/esp32c6/hpcore``.
+
+* ``xiao_esp32c6`` board target has been deprecated and renamed to
+  ``xiao_esp32c6/esp32c6/hpcore``.
+
+* :kconfig:option:`CONFIG_HAWKBIT_DDI_NO_SECURITY` Kconfig option has been
+  deprecated, because support for anonymous authentication had been removed from the
+  hawkBit server in version 0.8.0.
 
 New APIs and options
 ====================
 
+* Architectures
+
+  * :kconfig:option:`ARCH_HAS_VECTOR_TABLE_RELOCATION`
+  * :kconfig:option:`CONFIG_SRAM_VECTOR_TABLE` moved from ``zephyr/Kconfig.zephyr`` to
+    ``zephyr/arch/Kconfig`` and added dependencies to it.
+
+* Kernel
+
+ * :c:macro:`K_TIMEOUT_ABS_SEC`
+
+* I2C
+
+  * :c:func:`i2c_configure_dt`.
+
 ..
   Link to new APIs here, in a group if you think it's necessary, no need to get
   fancy just list the link, that should contain the documentation. If you feel
@@ -90,8 +145,72 @@ New APIs and options
   * Host
 
     * :c:func:`bt_le_get_local_features`
-
+    * :c:func:`bt_le_bond_exists`
+    * :c:func:`bt_br_bond_exists`
+    * :c:func:`bt_conn_lookup_addr_br`
+    * :c:func:`bt_conn_get_dst_br`
     * LE Connection Subrating is no longer experimental.
+    * Remove deletion of the classic bonding information from :c:func:`bt_unpair`, and add
+      :c:func:`bt_br_unpair`.
+    * Remove query of the classic bonding information from :c:func:`bt_foreach_bond`, and add
+      :c:func:`bt_br_foreach_bond`.
+
+* Display
+
+  * :c:func:`display_clear`
+
+* Networking:
+
+  * IPv4
+
+    * :kconfig:option:`CONFIG_NET_IPV4_MTU`
+
+  * MQTT
+
+    * :kconfig:option:`CONFIG_MQTT_VERSION_5_0`
+
+  * Sockets
+
+    * :kconfig:option:`CONFIG_NET_SOCKETS_INET_RAW`
+
+  * OpenThread
+
+    * Moved OpenThread-related Kconfig options from ``subsys/net/l2/openthread/Kconfig`` to ``modules/openthread/Kconfig``.
+
+* Sensor
+
+  * :c:func:`sensor_value_to_deci`
+  * :c:func:`sensor_value_to_centi`
+
+* Stepper
+
+  * :c:func:`stepper_stop()`
+
+* Storage
+
+  * :c:func:`flash_area_copy()`
+
+* Counter
+
+  * :c:func:`counter_reset`
+
+* Sys
+
+  * :c:func:`util_eq`
+  * :c:func:`util_memeq`
+
+* LoRaWAN
+   * :c:func:`lorawan_request_link_check`
+
+* Video
+
+  * :c:func:`video_api_ctrl_t`
+  * :c:func:`video_query_ctrl`
+  * :c:func:`video_print_ctrl`
+
+* PCIe
+
+   * :kconfig:option:`CONFIG_NVME_PRP_PAGE_SIZE`
 
 New Boards
 **********
@@ -102,6 +221,117 @@ New Boards
   that this list will be recomputed at the time of the release, so you don't *have* to update it.
   In any case, just link the board, further details go in the board description.
 
+* Adafruit Industries, LLC
+
+   * :zephyr:board:`adafruit_feather_esp32s2` (``adafruit_feather_esp32s2``)
+   * :zephyr:board:`adafruit_feather_esp32s2_tft` (``adafruit_feather_esp32s2_tft``)
+   * :zephyr:board:`adafruit_feather_esp32s2_tft_reverse` (``adafruit_feather_esp32s2_tft_reverse``)
+   * :zephyr:board:`adafruit_feather_esp32s3` (``adafruit_feather_esp32s3``)
+   * :zephyr:board:`adafruit_feather_esp32s3_tft` (``adafruit_feather_esp32s3_tft``)
+
+* Advanced Micro Devices (AMD), Inc.
+
+   * :zephyr:board:`versalnet_rpu` (``versalnet_rpu``)
+
+* Blues Wireless
+
+   * :zephyr:board:`cygnet` (``cygnet``)
+
+* FANKE Technology Co., Ltd.
+
+   * :zephyr:board:`fk743m5_xih6` (``fk743m5_xih6``)
+
+* IAR Systems AB
+
+   * :zephyr:board:`stm32f429ii_aca` (``stm32f429ii_aca``)
+
+* Intel Corporation
+
+   * :zephyr:board:`intel_btl_s_crb` (``intel_btl_s_crb``)
+
+* ITE Tech. Inc.
+
+   * :zephyr:board:`it515xx_evb` (``it515xx_evb``)
+
+* KWS Computersysteme Gmbh
+
+   * :zephyr:board:`pico2_spe` (``pico2_spe``)
+   * :zephyr:board:`pico_spe` (``pico_spe``)
+
+* Lilygo Shenzhen Xinyuan Electronic Technology Co., Ltd
+
+   * :zephyr:board:`tdongle_s3` (``tdongle_s3``)
+   * :zephyr:board:`ttgo_tbeam` (``ttgo_tbeam``)
+   * :zephyr:board:`ttgo_toiplus` (``ttgo_toiplus``)
+   * :zephyr:board:`twatch_s3` (``twatch_s3``)
+
+* Nuvoton Technology Corporation
+
+   * :zephyr:board:`numaker_m55m1` (``numaker_m55m1``)
+
+* NXP Semiconductors
+
+   * :zephyr:board:`frdm_mcxa166` (``frdm_mcxa166``)
+   * :zephyr:board:`frdm_mcxa276` (``frdm_mcxa276``)
+
+* Octavo Systems LLC
+
+   * :zephyr:board:`osd32mp1_brk` (``osd32mp1_brk``)
+
+* OpenHW Group
+
+   * :zephyr:board:`cv32a6_genesys_2` (``cv32a6_genesys_2``)
+   * :zephyr:board:`cv64a6_genesys_2` (``cv64a6_genesys_2``)
+
+* Pimoroni Ltd.
+
+   * :zephyr:board:`pico_plus2` (``pico_plus2``)
+
+* Renesas Electronics Corporation
+
+   * :zephyr:board:`rza3ul_smarc` (``rza3ul_smarc``)
+   * :zephyr:board:`rzg2l_smarc` (``rzg2l_smarc``)
+   * :zephyr:board:`rzn2l_rsk` (``rzn2l_rsk``)
+   * :zephyr:board:`rzt2l_rsk` (``rzt2l_rsk``)
+   * :zephyr:board:`rzt2m_rsk` (``rzt2m_rsk``)
+   * :zephyr:board:`rzv2l_smarc` (``rzv2l_smarc``)
+
+* Seeed Technology Co., Ltd
+
+   * :zephyr:board:`xiao_mg24` (``xiao_mg24``)
+   * :zephyr:board:`xiao_ra4m1` (``xiao_ra4m1``)
+
+* sensry.io
+
+   * :zephyr:board:`ganymed_sk` (``ganymed_sk``)
+
+* Silicon Laboratories
+
+   * :zephyr:board:`slwrb4180b` (``slwrb4180b``)
+
+* STMicroelectronics
+
+   * :zephyr:board:`nucleo_f439zi` (``nucleo_f439zi``)
+   * :zephyr:board:`stm32h757i_eval` (``stm32h757i_eval``)
+   * :zephyr:board:`stm32mp135f_dk` (``stm32mp135f_dk``)
+
+* Texas Instruments
+
+   * :zephyr:board:`sk_am64` (``sk_am64``)
+
+* WinChipHead
+
+   * :zephyr:board:`ch32v003f4p6_dev_board` (``ch32v003f4p6_dev_board``)
+   * :zephyr:board:`linkw` (``linkw``)
+
+* WIZnet Co., Ltd.
+
+   * :zephyr:board:`w5500_evb_pico2` (``w5500_evb_pico2``)
+
+* Würth Elektronik GmbH.
+
+   * :zephyr:board:`ophelia4ev` (``ophelia4ev``)
+
 New Drivers
 ***********
 
@@ -109,6 +339,224 @@ New Drivers
   Same as above for boards, this will also be recomputed at the time of the release.
   Just link the driver, further details go in the binding description
 
+* :abbr:`ADC (Analog to Digital Converter)`
+
+   * :dtcompatible:`adi,ad4050-adc`
+   * :dtcompatible:`adi,ad4052-adc`
+   * :dtcompatible:`adi,ad4130-adc`
+   * :dtcompatible:`renesas,rz-adc`
+
+* Audio
+
+   * :dtcompatible:`ti,tlv320aic3110`
+
+* Charger
+
+   * :dtcompatible:`ti,bq25713`
+
+* Clock control
+
+   * :dtcompatible:`ite,it51xxx-ecpm`
+   * :dtcompatible:`nordic,nrfs-audiopll`
+   * :dtcompatible:`st,stm32mp13-cpu-clock-mux`
+   * :dtcompatible:`st,stm32mp13-pll-clock`
+   * :dtcompatible:`wch,ch32v20x_30x-pll-clock`
+
+* Comparator
+
+   * :dtcompatible:`renesas,ra-acmphs`
+   * :dtcompatible:`renesas,ra-acmphs-global`
+
+* Counter
+
+   * :dtcompatible:`ite,it8xxx2-counter`
+   * :dtcompatible:`zephyr,native-sim-counter`
+
+* CPU
+
+   * :dtcompatible:`intel,bartlett-lake`
+   * :dtcompatible:`wch,qingke-v4c`
+   * :dtcompatible:`zephyr,native-sim-cpu`
+
+* Cryptographic accelerator
+
+   * :dtcompatible:`ti,cc23x0-aes`
+
+* :abbr:`DAC (Digital to Analog Converter)`
+
+   * :dtcompatible:`ti,dac161s997`
+
+* Display
+
+   * :dtcompatible:`sitronix,st7567`
+   * :dtcompatible:`sitronix,st7701`
+
+* :abbr:`DMA (Direct Memory Access)`
+
+   * :dtcompatible:`renesas,rz-dma`
+   * :dtcompatible:`ti,cc23x0-dma`
+   * :dtcompatible:`wch,wch-dma`
+
+* Ethernet
+
+   * :dtcompatible:`st,stm32-ethernet-controller`
+   * :dtcompatible:`st,stm32n6-ethernet`
+   * :dtcompatible:`ti,dp83867`
+   * :dtcompatible:`xlnx,axi-ethernet-1.00.a`
+
+* Flash controller
+
+   * :dtcompatible:`silabs,series2-flash-controller`
+
+* File system
+
+   * :dtcompatible:`zephyr,fstab,fatfs`
+
+* :abbr:`GPIO (General Purpose Input/Output)` and Headers
+
+   * :dtcompatible:`adi,max14915-gpio`
+   * :dtcompatible:`adi,max14917-gpio`
+   * :dtcompatible:`adi,max22199-gpio`
+   * :dtcompatible:`ite,it51xxx-gpio`
+   * :dtcompatible:`nxp,lcd-pmod`
+   * :dtcompatible:`raspberrypi,pico-gpio-port`
+   * :dtcompatible:`renesas,ra-parallel-graphics-header`
+
+* :abbr:`I2C (Inter-Integrated Circuit)`
+
+   * :dtcompatible:`cdns,i2c`
+   * :dtcompatible:`litex,litei2c`
+   * :dtcompatible:`renesas,ra-i2c-sci-b`
+   * :dtcompatible:`renesas,rz-riic`
+   * :dtcompatible:`sensry,sy1xx-i2c`
+
+* Input
+
+   * :dtcompatible:`realtek,rts5912-kbd`
+   * :dtcompatible:`st,stm32-tsc`
+   * :dtcompatible:`tsc-keys`
+
+* Interrupt controller
+
+   * :dtcompatible:`ite,it51xxx-intc`
+   * :dtcompatible:`ite,it51xxx-wuc`
+   * :dtcompatible:`ite,it51xxx-wuc-map`
+
+* Mailbox
+
+   * :dtcompatible:`arm,mhuv3`
+   * :dtcompatible:`renesas,rz-mhu-mbox`
+
+* :abbr:`MDIO (Management Data Input/Output)`
+
+   * :dtcompatible:`xlnx,axi-ethernet-1.00.a-mdio`
+
+* Memory controller
+
+   * :dtcompatible:`realtek,rts5912-bbram`
+   * :dtcompatible:`st,stm32-xspi-psram`
+
+* :abbr:`MFD (Multi-Function Device)`
+
+   * :dtcompatible:`adi,maxq10xx`
+   * :dtcompatible:`ambiq,iom`
+   * :dtcompatible:`x-powers,axp2101`
+
+* Miscellaneous
+
+   * :dtcompatible:`nordic,nrf-mpc`
+   * :dtcompatible:`renesas,ra-ulpt`
+   * :dtcompatible:`renesas,rz-sci`
+
+* Multi-bit SPI
+
+   * :dtcompatible:`snps,designware-ssi`
+
+* :abbr:`MTD (Memory Technology Device)`
+
+   * :dtcompatible:`jedec,mspi-nor`
+
+* Networking
+
+   * :dtcompatible:`nordic,nrf-nfct-v2`
+
+* Pin control
+
+   * :dtcompatible:`arm,mps2-pinctrl`
+   * :dtcompatible:`arm,mps3-pinctrl`
+   * :dtcompatible:`arm,v2m_beetle-pinctrl`
+   * :dtcompatible:`renesas,rza-pinctrl`
+   * :dtcompatible:`renesas,rzn-pinctrl`
+   * :dtcompatible:`renesas,rzt-pinctrl`
+   * :dtcompatible:`renesas,rzv-pinctrl`
+   * :dtcompatible:`wch,20x_30x-afio`
+
+* :abbr:`PWM (Pulse Width Modulation)`
+
+   * :dtcompatible:`arduino-header-pwm`
+   * :dtcompatible:`silabs,siwx91x-pwm`
+
+* Regulator
+
+   * :dtcompatible:`x-powers,axp2101-regulator`
+
+* Reset controller
+
+   * :dtcompatible:`reset-mmio`
+
+* :abbr:`RNG (Random Number Generator)`
+
+   * :dtcompatible:`adi,maxq10xx-trng`
+   * :dtcompatible:`zephyr,native-sim-rng`
+
+* :abbr:`RTC (Real Time Clock)`
+
+   * :dtcompatible:`nxp,pcf2123`
+   * :dtcompatible:`realtek,rts5912-rtc`
+
+* SDHC
+
+   * :dtcompatible:`ambiq,sdio`
+
+* Sensors
+
+   * :dtcompatible:`bosch,bmm350`
+   * :dtcompatible:`everlight,als-pt19`
+   * :dtcompatible:`invensense,icm45686`
+   * :dtcompatible:`invensense,icp201xx`
+   * :dtcompatible:`liteon,ltr329`
+   * :dtcompatible:`meas,ms5837-02ba`
+   * :dtcompatible:`meas,ms5837-30ba`
+   * :dtcompatible:`pixart,paa3905`
+   * :dtcompatible:`pixart,pat9136`
+   * :dtcompatible:`st,lsm6dsv32x`
+   * :dtcompatible:`vishay,veml6031`
+
+* Serial controller
+
+   * :dtcompatible:`ite,it51xxx-uart`
+   * :dtcompatible:`renesas,rz-sci-uart`
+   * :dtcompatible:`zephyr,native-pty-uart`
+
+* :abbr:`SPI (Serial Peripheral Interface)`
+
+   * :dtcompatible:`cdns,spi`
+
+* Timer
+
+   * :dtcompatible:`ite,it51xxx-timer`
+   * :dtcompatible:`renesas,ra-ulpt-timer`
+
+* USB
+
+   * :dtcompatible:`adi,max32-usbhs`
+
+* Watchdog
+
+   * :dtcompatible:`realtek,rts5912-watchdog`
+   * :dtcompatible:`renesas,ra-wdt`
+   * :dtcompatible:`silabs,siwx91x-wdt`
+
 New Samples
 ***********
 
@@ -116,9 +564,37 @@ New Samples
   Same as above for boards and drivers, this will also be recomputed at the time of the release.
  Just link the sample, further details go in the sample documentation itself.
 
+* :zephyr:code-sample:`bmg160`
+* :zephyr:code-sample:`debug-ulp`
+* :zephyr:code-sample:`echo-ulp`
+* :zephyr:code-sample:`fatfs-fstab`
+* :zephyr:code-sample:`pressure_interrupt`
+* :zephyr:code-sample:`pressure_polling`
+* :zephyr:code-sample:`renesas_comparator`
+* :zephyr:code-sample:`rz-openamp-linux-zephyr`
+* :zephyr:code-sample:`spis-wakeup`
+* :zephyr:code-sample:`stepper`
+* :zephyr:code-sample:`veml6031`
+
 Other notable changes
 *********************
 
 ..
   Any more descriptive subsystem or driver changes. Do you really want to write
   a paragraph or is it enough to link to the api/driver/Kconfig/board page above?
+
+* Added support for Armv8.1-M MPU's PXN (Privileged Execute Never) attribute.
+  With this, the MPU attributes for ``__ramfunc`` and ``__ram_text_reloc`` were modified such that,
+  PXN attribute is set for these regions if compiled with ``CONFIG_ARM_MPU_PXN`` and ``CONFIG_USERSPACE``.
+  This results in a change in behaviour for code being executed from these regions because,
+  if these regions have pxn attribute set in them, they cannot be executed in privileged mode.
+
+* Removed support for Nucleo WBA52CG board (``nucleo_wba52cg``) since it is NRND (Not Recommended
+  for New Design) and it is not supported anymore in the STM32CubeWBA from version 1.1.0 (July 2023).
+  The migration to :zephyr:board:`nucleo_wba55cg` (``nucleo_wba55cg``) is recommended instead.
+
+* Updated Mbed TLS to version 3.6.3 (from 3.6.2). The release notes can be found at:
+  https://github.com/Mbed-TLS/mbedtls/releases/tag/mbedtls-3.6.3
+
+* Updated TF-M to version 2.1.2 (from 2.1.1). The release notes can be found at:
+  https://trustedfirmware-m.readthedocs.io/en/tf-mv2.1.2/releases/2.1.2.html
diff --git a/doc/requirements.in b/doc/requirements.in
new file mode 100644
index 00000000000..36bb61a00c8
--- /dev/null
+++ b/doc/requirements.in
@@ -0,0 +1,29 @@
+# DOC: used to generate docs
+
+sphinx<8.3.0
+sphinx_rtd_theme~=3.0
+sphinx-tabs
+sphinxcontrib-svg2pdfconverter
+pygments>=2.9,!=2.19.0
+sphinx-notfound-page
+sphinx-copybutton
+sphinx-togglebutton
+sphinx-sitemap
+sphinx-autobuild
+
+# YAML validation. Used by zephyr_module.
+PyYAML>=6.0
+pykwalify
+
+# Used by pytest-twister-harness plugin (imported by autodoc)
+pytest
+pyserial
+
+# Doxygen doxmlparser
+doxmlparser
+
+# Used by the Zephyr domain to organize code samples
+anytree
+
+# Used to generate API coverage reports
+coverxygen
diff --git a/doc/requirements.txt b/doc/requirements.txt
index b5a5d306540..c10b390651a 100644
--- a/doc/requirements.txt
+++ b/doc/requirements.txt
@@ -1,26 +1,835 @@
-# DOC: used to generate docs
-
-sphinx
-sphinx_rtd_theme~=3.0
-sphinx-tabs
-sphinxcontrib-svg2pdfconverter
-pygments>=2.9,!=2.19.0
-sphinx-notfound-page
-sphinx-copybutton
-sphinx-togglebutton
-sphinx-sitemap
-sphinx-autobuild
-
-# YAML validation. Used by zephyr_module.
-PyYAML>=6.0
-pykwalify
-
-# Used by pytest-twister-harness plugin (imported by autodoc)
-pytest
-pyserial
-
-# Doxygen doxmlparser
-doxmlparser
-
-# Used by the Zephyr domain to organize code samples
-anytree
+# This file was autogenerated by uv via the following command:
+#    uv pip compile --universal --python-version 3.10 --generate-hashes requirements.in --output-file requirements.txt
+alabaster==1.0.0 \
+    --hash=sha256:c00dca57bca26fa62a6d7d0a9fcce65f3e026e9bfe33e9c538fd3fbb2144fd9e \
+    --hash=sha256:fc6786402dc3fcb2de3cabd5fe455a2db534b371124f1f21de8731783dec828b
+    # via sphinx
+anyio==4.9.0 \
+    --hash=sha256:673c0c244e15788651a4ff38710fea9675823028a6f08a5eda409e0c9840a028 \
+    --hash=sha256:9f76d541cad6e36af7beb62e978876f3b41e3e04f2c1fbf0884604c0a9c4d93c
+    # via
+    #   starlette
+    #   watchfiles
+anytree==2.12.1 \
+    --hash=sha256:244def434ccf31b668ed282954e5d315b4e066c4940b94aff4a7962d85947830 \
+    --hash=sha256:5ea9e61caf96db1e5b3d0a914378d2cd83c269dfce1fb8242ce96589fa3382f0
+    # via -r requirements.in
+babel==2.17.0 \
+    --hash=sha256:0c54cffb19f690cdcc52a3b50bcbf71e07a808d1c80d549f2459b9d2cf0afb9d \
+    --hash=sha256:4d0b53093fdfb4b21c92b5213dba5a1b23885afa8383709427046b21c366e5f2
+    # via sphinx
+certifi==2025.1.31 \
+    --hash=sha256:3d5da6925056f6f18f119200434a4780a94263f10d1c21d032a6f6b2baa20651 \
+    --hash=sha256:ca78db4565a652026a4db2bcdf68f2fb589ea80d0be70e03929ed730746b84fe
+    # via requests
+charset-normalizer==3.4.1 \
+    --hash=sha256:0167ddc8ab6508fe81860a57dd472b2ef4060e8d378f0cc555707126830f2537 \
+    --hash=sha256:01732659ba9b5b873fc117534143e4feefecf3b2078b0a6a2e925271bb6f4cfa \
+    --hash=sha256:01ad647cdd609225c5350561d084b42ddf732f4eeefe6e678765636791e78b9a \
+    --hash=sha256:04432ad9479fa40ec0f387795ddad4437a2b50417c69fa275e212933519ff294 \
+    --hash=sha256:0907f11d019260cdc3f94fbdb23ff9125f6b5d1039b76003b5b0ac9d6a6c9d5b \
+    --hash=sha256:0924e81d3d5e70f8126529951dac65c1010cdf117bb75eb02dd12339b57749dd \
+    --hash=sha256:09b26ae6b1abf0d27570633b2b078a2a20419c99d66fb2823173d73f188ce601 \
+    --hash=sha256:09b5e6733cbd160dcc09589227187e242a30a49ca5cefa5a7edd3f9d19ed53fd \
+    --hash=sha256:0af291f4fe114be0280cdd29d533696a77b5b49cfde5467176ecab32353395c4 \
+    --hash=sha256:0f55e69f030f7163dffe9fd0752b32f070566451afe180f99dbeeb81f511ad8d \
+    --hash=sha256:1a2bc9f351a75ef49d664206d51f8e5ede9da246602dc2d2726837620ea034b2 \
+    --hash=sha256:22e14b5d70560b8dd51ec22863f370d1e595ac3d024cb8ad7d308b4cd95f8313 \
+    --hash=sha256:234ac59ea147c59ee4da87a0c0f098e9c8d169f4dc2a159ef720f1a61bbe27cd \
+    --hash=sha256:2369eea1ee4a7610a860d88f268eb39b95cb588acd7235e02fd5a5601773d4fa \
+    --hash=sha256:237bdbe6159cff53b4f24f397d43c6336c6b0b42affbe857970cefbb620911c8 \
+    --hash=sha256:28bf57629c75e810b6ae989f03c0828d64d6b26a5e205535585f96093e405ed1 \
+    --hash=sha256:2967f74ad52c3b98de4c3b32e1a44e32975e008a9cd2a8cc8966d6a5218c5cb2 \
+    --hash=sha256:2a75d49014d118e4198bcee5ee0a6f25856b29b12dbf7cd012791f8a6cc5c496 \
+    --hash=sha256:2bdfe3ac2e1bbe5b59a1a63721eb3b95fc9b6817ae4a46debbb4e11f6232428d \
+    --hash=sha256:2d074908e1aecee37a7635990b2c6d504cd4766c7bc9fc86d63f9c09af3fa11b \
+    --hash=sha256:2fb9bd477fdea8684f78791a6de97a953c51831ee2981f8e4f583ff3b9d9687e \
+    --hash=sha256:311f30128d7d333eebd7896965bfcfbd0065f1716ec92bd5638d7748eb6f936a \
+    --hash=sha256:329ce159e82018d646c7ac45b01a430369d526569ec08516081727a20e9e4af4 \
+    --hash=sha256:345b0426edd4e18138d6528aed636de7a9ed169b4aaf9d61a8c19e39d26838ca \
+    --hash=sha256:363e2f92b0f0174b2f8238240a1a30142e3db7b957a5dd5689b0e75fb717cc78 \
+    --hash=sha256:3a3bd0dcd373514dcec91c411ddb9632c0d7d92aed7093b8c3bbb6d69ca74408 \
+    --hash=sha256:3bed14e9c89dcb10e8f3a29f9ccac4955aebe93c71ae803af79265c9ca5644c5 \
+    --hash=sha256:44251f18cd68a75b56585dd00dae26183e102cd5e0f9f1466e6df5da2ed64ea3 \
+    --hash=sha256:44ecbf16649486d4aebafeaa7ec4c9fed8b88101f4dd612dcaf65d5e815f837f \
+    --hash=sha256:4532bff1b8421fd0a320463030c7520f56a79c9024a4e88f01c537316019005a \
+    --hash=sha256:49402233c892a461407c512a19435d1ce275543138294f7ef013f0b63d5d3765 \
+    --hash=sha256:4c0907b1928a36d5a998d72d64d8eaa7244989f7aaaf947500d3a800c83a3fd6 \
+    --hash=sha256:4d86f7aff21ee58f26dcf5ae81a9addbd914115cdebcbb2217e4f0ed8982e146 \
+    --hash=sha256:5777ee0881f9499ed0f71cc82cf873d9a0ca8af166dfa0af8ec4e675b7df48e6 \
+    --hash=sha256:5df196eb874dae23dcfb968c83d4f8fdccb333330fe1fc278ac5ceeb101003a9 \
+    --hash=sha256:619a609aa74ae43d90ed2e89bdd784765de0a25ca761b93e196d938b8fd1dbbd \
+    --hash=sha256:6e27f48bcd0957c6d4cb9d6fa6b61d192d0b13d5ef563e5f2ae35feafc0d179c \
+    --hash=sha256:6ff8a4a60c227ad87030d76e99cd1698345d4491638dfa6673027c48b3cd395f \
+    --hash=sha256:73d94b58ec7fecbc7366247d3b0b10a21681004153238750bb67bd9012414545 \
+    --hash=sha256:7461baadb4dc00fd9e0acbe254e3d7d2112e7f92ced2adc96e54ef6501c5f176 \
+    --hash=sha256:75832c08354f595c760a804588b9357d34ec00ba1c940c15e31e96d902093770 \
+    --hash=sha256:7709f51f5f7c853f0fb938bcd3bc59cdfdc5203635ffd18bf354f6967ea0f824 \
+    --hash=sha256:78baa6d91634dfb69ec52a463534bc0df05dbd546209b79a3880a34487f4b84f \
+    --hash=sha256:7974a0b5ecd505609e3b19742b60cee7aa2aa2fb3151bc917e6e2646d7667dcf \
+    --hash=sha256:7a4f97a081603d2050bfaffdefa5b02a9ec823f8348a572e39032caa8404a487 \
+    --hash=sha256:7b1bef6280950ee6c177b326508f86cad7ad4dff12454483b51d8b7d673a2c5d \
+    --hash=sha256:7d053096f67cd1241601111b698f5cad775f97ab25d81567d3f59219b5f1adbd \
+    --hash=sha256:804a4d582ba6e5b747c625bf1255e6b1507465494a40a2130978bda7b932c90b \
+    --hash=sha256:807f52c1f798eef6cf26beb819eeb8819b1622ddfeef9d0977a8502d4db6d534 \
+    --hash=sha256:80ed5e856eb7f30115aaf94e4a08114ccc8813e6ed1b5efa74f9f82e8509858f \
+    --hash=sha256:8417cb1f36cc0bc7eaba8ccb0e04d55f0ee52df06df3ad55259b9a323555fc8b \
+    --hash=sha256:8436c508b408b82d87dc5f62496973a1805cd46727c34440b0d29d8a2f50a6c9 \
+    --hash=sha256:89149166622f4db9b4b6a449256291dc87a99ee53151c74cbd82a53c8c2f6ccd \
+    --hash=sha256:8bfa33f4f2672964266e940dd22a195989ba31669bd84629f05fab3ef4e2d125 \
+    --hash=sha256:8c60ca7339acd497a55b0ea5d506b2a2612afb2826560416f6894e8b5770d4a9 \
+    --hash=sha256:91b36a978b5ae0ee86c394f5a54d6ef44db1de0815eb43de826d41d21e4af3de \
+    --hash=sha256:955f8851919303c92343d2f66165294848d57e9bba6cf6e3625485a70a038d11 \
+    --hash=sha256:97f68b8d6831127e4787ad15e6757232e14e12060bec17091b85eb1486b91d8d \
+    --hash=sha256:9b23ca7ef998bc739bf6ffc077c2116917eabcc901f88da1b9856b210ef63f35 \
+    --hash=sha256:9f0b8b1c6d84c8034a44893aba5e767bf9c7a211e313a9605d9c617d7083829f \
+    --hash=sha256:aabfa34badd18f1da5ec1bc2715cadc8dca465868a4e73a0173466b688f29dda \
+    --hash=sha256:ab36c8eb7e454e34e60eb55ca5d241a5d18b2c6244f6827a30e451c42410b5f7 \
+    --hash=sha256:b010a7a4fd316c3c484d482922d13044979e78d1861f0e0650423144c616a46a \
+    --hash=sha256:b1ac5992a838106edb89654e0aebfc24f5848ae2547d22c2c3f66454daa11971 \
+    --hash=sha256:b7b2d86dd06bfc2ade3312a83a5c364c7ec2e3498f8734282c6c3d4b07b346b8 \
+    --hash=sha256:b97e690a2118911e39b4042088092771b4ae3fc3aa86518f84b8cf6888dbdb41 \
+    --hash=sha256:bc2722592d8998c870fa4e290c2eec2c1569b87fe58618e67d38b4665dfa680d \
+    --hash=sha256:c0429126cf75e16c4f0ad00ee0eae4242dc652290f940152ca8c75c3a4b6ee8f \
+    --hash=sha256:c30197aa96e8eed02200a83fba2657b4c3acd0f0aa4bdc9f6c1af8e8962e0757 \
+    --hash=sha256:c4c3e6da02df6fa1410a7680bd3f63d4f710232d3139089536310d027950696a \
+    --hash=sha256:c75cb2a3e389853835e84a2d8fb2b81a10645b503eca9bcb98df6b5a43eb8886 \
+    --hash=sha256:c96836c97b1238e9c9e3fe90844c947d5afbf4f4c92762679acfe19927d81d77 \
+    --hash=sha256:d7f50a1f8c450f3925cb367d011448c39239bb3eb4117c36a6d354794de4ce76 \
+    --hash=sha256:d973f03c0cb71c5ed99037b870f2be986c3c05e63622c017ea9816881d2dd247 \
+    --hash=sha256:d98b1668f06378c6dbefec3b92299716b931cd4e6061f3c875a71ced1780ab85 \
+    --hash=sha256:d9c3cdf5390dcd29aa8056d13e8e99526cda0305acc038b96b30352aff5ff2bb \
+    --hash=sha256:dad3e487649f498dd991eeb901125411559b22e8d7ab25d3aeb1af367df5efd7 \
+    --hash=sha256:dccbe65bd2f7f7ec22c4ff99ed56faa1e9f785482b9bbd7c717e26fd723a1d1e \
+    --hash=sha256:dd78cfcda14a1ef52584dbb008f7ac81c1328c0f58184bf9a84c49c605002da6 \
+    --hash=sha256:e218488cd232553829be0664c2292d3af2eeeb94b32bea483cf79ac6a694e037 \
+    --hash=sha256:e358e64305fe12299a08e08978f51fc21fac060dcfcddd95453eabe5b93ed0e1 \
+    --hash=sha256:ea0d8d539afa5eb2728aa1932a988a9a7af94f18582ffae4bc10b3fbdad0626e \
+    --hash=sha256:eab677309cdb30d047996b36d34caeda1dc91149e4fdca0b1a039b3f79d9a807 \
+    --hash=sha256:eb8178fe3dba6450a3e024e95ac49ed3400e506fd4e9e5c32d30adda88cbd407 \
+    --hash=sha256:ecddf25bee22fe4fe3737a399d0d177d72bc22be6913acfab364b40bce1ba83c \
+    --hash=sha256:eea6ee1db730b3483adf394ea72f808b6e18cf3cb6454b4d86e04fa8c4327a12 \
+    --hash=sha256:f08ff5e948271dc7e18a35641d2f11a4cd8dfd5634f55228b691e62b37125eb3 \
+    --hash=sha256:f30bf9fd9be89ecb2360c7d94a711f00c09b976258846efe40db3d05828e8089 \
+    --hash=sha256:fa88b843d6e211393a37219e6a1c1df99d35e8fd90446f1118f4216e307e48cd \
+    --hash=sha256:fc54db6c8593ef7d4b2a331b58653356cf04f67c960f584edb7c3d8c97e8f39e \
+    --hash=sha256:fd4ec41f914fa74ad1b8304bbc634b3de73d2a0889bd32076342a573e0779e00 \
+    --hash=sha256:ffc9202a29ab3920fa812879e95a9e78b2465fd10be7fcbd042899695d75e616
+    # via requests
+click==8.1.8 \
+    --hash=sha256:63c132bbbed01578a06712a2d1f497bb62d9c1c0d329b7903a866228027263b2 \
+    --hash=sha256:ed53c9d8990d83c2a27deae68e4ee337473f6330c040a31d4225c9574d16096a
+    # via uvicorn
+colorama==0.4.6 \
+    --hash=sha256:08695f5cb7ed6e0531a20572697297273c47b8cae5a63ffc6d6ed5c201be6e44 \
+    --hash=sha256:4f1d9991f5acc0ca119f9d443620b77f9d6b33703e51011c16baf57afb285fc6
+    # via
+    #   click
+    #   pytest
+    #   sphinx
+    #   sphinx-autobuild
+coverxygen==1.8.1 \
+    --hash=sha256:d1c2f6569e8df8823ae313b1f7876e88ff20b4372c6d02f04c51fb5dc424576f
+    # via -r requirements.in
+docopt==0.6.2 \
+    --hash=sha256:49b3a825280bd66b3aa83585ef59c4a8c82f2c8a522dbe754a8bc8d08c85c491
+    # via pykwalify
+docutils==0.21.2 \
+    --hash=sha256:3a6b18732edf182daa3cd12775bbb338cf5691468f91eeeb109deff6ebfa986f \
+    --hash=sha256:dafca5b9e384f0e419294eb4d2ff9fa826435bf15f15b7bd45723e8ad76811b2
+    # via
+    #   sphinx
+    #   sphinx-rtd-theme
+    #   sphinx-tabs
+    #   sphinx-togglebutton
+doxmlparser==1.13.2 \
+    --hash=sha256:65ab126e7d3f77b1bb15fa6886663614f68d0473b48831e1fb822f533243eb68
+    # via -r requirements.in
+exceptiongroup==1.2.2 ; python_full_version < '3.11' \
+    --hash=sha256:3111b9d131c238bec2f8f516e123e14ba243563fb135d3fe885990585aa7795b \
+    --hash=sha256:47c2edf7c6738fafb49fd34290706d1a1a2f4d1c6df275526b62cbb4aa5393cc
+    # via
+    #   anyio
+    #   pytest
+h11==0.14.0 \
+    --hash=sha256:8f19fbbe99e72420ff35c00b27a34cb9937e902a8b810e2c88300c6f0a3b699d \
+    --hash=sha256:e3fe4ac4b851c468cc8363d500db52c2ead036020723024a109d37346efaa761
+    # via uvicorn
+idna==3.10 \
+    --hash=sha256:12f65c9b470abda6dc35cf8e63cc574b1c52b11df2c86030af0ac09b01b13ea9 \
+    --hash=sha256:946d195a0d259cbba61165e88e65941f16e9b36ea6ddb97f00452bae8b1287d3
+    # via
+    #   anyio
+    #   requests
+imagesize==1.4.1 \
+    --hash=sha256:0d8d18d08f840c19d0ee7ca1fd82490fdc3729b7ac93f49870406ddde8ef8d8b \
+    --hash=sha256:69150444affb9cb0d5cc5a92b3676f0b2fb7cd9ae39e947a5e11a36b4497cd4a
+    # via sphinx
+iniconfig==2.1.0 \
+    --hash=sha256:3abbd2e30b36733fee78f9c7f7308f2d0050e88f0087fd25c2645f63c773e1c7 \
+    --hash=sha256:9deba5723312380e77435581c6bf4935c94cbfab9b1ed33ef8d238ea168eb760
+    # via pytest
+jinja2==3.1.6 \
+    --hash=sha256:0137fb05990d35f1275a587e9aee6d56da821fc83491a0fb838183be43f66d6d \
+    --hash=sha256:85ece4451f492d0c13c5dd7c13a64681a86afae63a5f347908daf103ce6d2f67
+    # via sphinx
+lxml==5.3.1 \
+    --hash=sha256:016b96c58e9a4528219bb563acf1aaaa8bc5452e7651004894a973f03b84ba81 \
+    --hash=sha256:05123fad495a429f123307ac6d8fd6f977b71e9a0b6d9aeeb8f80c017cb17131 \
+    --hash=sha256:057e30d0012439bc54ca427a83d458752ccda725c1c161cc283db07bcad43cf9 \
+    --hash=sha256:06a20d607a86fccab2fc15a77aa445f2bdef7b49ec0520a842c5c5afd8381576 \
+    --hash=sha256:094b28ed8a8a072b9e9e2113a81fda668d2053f2ca9f2d202c2c8c7c2d6516b1 \
+    --hash=sha256:0bcfadea3cdc68e678d2b20cb16a16716887dd00a881e16f7d806c2138b8ff0c \
+    --hash=sha256:0d6b2fa86becfa81f0a0271ccb9eb127ad45fb597733a77b92e8a35e53414914 \
+    --hash=sha256:0f2cfae0688fd01f7056a17367e3b84f37c545fb447d7282cf2c242b16262607 \
+    --hash=sha256:106b7b5d2977b339f1e97efe2778e2ab20e99994cbb0ec5e55771ed0795920c8 \
+    --hash=sha256:133f3493253a00db2c870d3740bc458ebb7d937bd0a6a4f9328373e0db305709 \
+    --hash=sha256:136bf638d92848a939fd8f0e06fcf92d9f2e4b57969d94faae27c55f3d85c05b \
+    --hash=sha256:155e1a5693cf4b55af652f5c0f78ef36596c7f680ff3ec6eb4d7d85367259b2c \
+    --hash=sha256:1637fa31ec682cd5760092adfabe86d9b718a75d43e65e211d5931809bc111e7 \
+    --hash=sha256:172d65f7c72a35a6879217bcdb4bb11bc88d55fb4879e7569f55616062d387c2 \
+    --hash=sha256:17b5d7f8acf809465086d498d62a981fa6a56d2718135bb0e4aa48c502055f5c \
+    --hash=sha256:198bb4b4dd888e8390afa4f170d4fa28467a7eaf857f1952589f16cfbb67af27 \
+    --hash=sha256:1b6f92e35e2658a5ed51c6634ceb5ddae32053182851d8cad2a5bc102a359b33 \
+    --hash=sha256:1b92fe86e04f680b848fff594a908edfa72b31bfc3499ef7433790c11d4c8cd8 \
+    --hash=sha256:1bcc211542f7af6f2dfb705f5f8b74e865592778e6cafdfd19c792c244ccce19 \
+    --hash=sha256:1c93ed3c998ea8472be98fb55aed65b5198740bfceaec07b2eba551e55b7b9ae \
+    --hash=sha256:203b1d3eaebd34277be06a3eb880050f18a4e4d60861efba4fb946e31071a295 \
+    --hash=sha256:22ec2b3c191f43ed21f9545e9df94c37c6b49a5af0a874008ddc9132d49a2d9c \
+    --hash=sha256:231cf4d140b22a923b1d0a0a4e0b4f972e5893efcdec188934cc65888fd0227b \
+    --hash=sha256:236610b77589faf462337b3305a1be91756c8abc5a45ff7ca8f245a71c5dab70 \
+    --hash=sha256:29bfc8d3d88e56ea0a27e7c4897b642706840247f59f4377d81be8f32aa0cfbf \
+    --hash=sha256:2b8969dbc8d09d9cd2ae06362c3bad27d03f433252601ef658a49bd9f2b22d79 \
+    --hash=sha256:2dd0b80ac2d8f13ffc906123a6f20b459cb50a99222d0da492360512f3e50f84 \
+    --hash=sha256:2df7ed5edeb6bd5590914cd61df76eb6cce9d590ed04ec7c183cf5509f73530d \
+    --hash=sha256:2e4a570f6a99e96c457f7bec5ad459c9c420ee80b99eb04cbfcfe3fc18ec6423 \
+    --hash=sha256:2f1be45d4c15f237209bbf123a0e05b5d630c8717c42f59f31ea9eae2ad89394 \
+    --hash=sha256:2f23cf50eccb3255b6e913188291af0150d89dab44137a69e14e4dcb7be981f1 \
+    --hash=sha256:3031e4c16b59424e8d78522c69b062d301d951dc55ad8685736c3335a97fc270 \
+    --hash=sha256:33e06717c00c788ab4e79bc4726ecc50c54b9bfb55355eae21473c145d83c2d2 \
+    --hash=sha256:364de8f57d6eda0c16dcfb999af902da31396949efa0e583e12675d09709881b \
+    --hash=sha256:3715cdf0dd31b836433af9ee9197af10e3df41d273c19bb249230043667a5dfd \
+    --hash=sha256:3bb8149840daf2c3f97cebf00e4ed4a65a0baff888bf2605a8d0135ff5cf764e \
+    --hash=sha256:3c3c8b55c7fc7b7e8877b9366568cc73d68b82da7fe33d8b98527b73857a225f \
+    --hash=sha256:3d68eeef7b4d08a25e51897dac29bcb62aba830e9ac6c4e3297ee7c6a0cf6439 \
+    --hash=sha256:3dddf0fb832486cc1ea71d189cb92eb887826e8deebe128884e15020bb6e3f61 \
+    --hash=sha256:3edbb9c9130bac05d8c3fe150c51c337a471cc7fdb6d2a0a7d3a88e88a829314 \
+    --hash=sha256:3effe081b3135237da6e4c4530ff2a868d3f80be0bda027e118a5971285d42d0 \
+    --hash=sha256:422c179022ecdedbe58b0e242607198580804253da220e9454ffe848daa1cfd2 \
+    --hash=sha256:42978a68d3825eaac55399eb37a4d52012a205c0c6262199b8b44fcc6fd686e8 \
+    --hash=sha256:4399b4226c4785575fb20998dc571bc48125dc92c367ce2602d0d70e0c455eb0 \
+    --hash=sha256:45fbb70ccbc8683f2fb58bea89498a7274af1d9ec7995e9f4af5604e028233fc \
+    --hash=sha256:4867361c049761a56bd21de507cab2c2a608c55102311d142ade7dab67b34f32 \
+    --hash=sha256:48fd46bf7155def2e15287c6f2b133a2f78e2d22cdf55647269977b873c65499 \
+    --hash=sha256:4b0d5cdba1b655d5b18042ac9c9ff50bda33568eb80feaaca4fc237b9c4fbfde \
+    --hash=sha256:4df0ec814b50275ad6a99bc82a38b59f90e10e47714ac9871e1b223895825468 \
+    --hash=sha256:4e52e1b148867b01c05e21837586ee307a01e793b94072d7c7b91d2c2da02ffe \
+    --hash=sha256:514fe78fc4b87e7a7601c92492210b20a1b0c6ab20e71e81307d9c2e377c64de \
+    --hash=sha256:524ccfded8989a6595dbdda80d779fb977dbc9a7bc458864fc9a0c2fc15dc877 \
+    --hash=sha256:528f3a0498a8edc69af0559bdcf8a9f5a8bf7c00051a6ef3141fdcf27017bbf5 \
+    --hash=sha256:52d82b0d436edd6a1d22d94a344b9a58abd6c68c357ed44f22d4ba8179b37629 \
+    --hash=sha256:5412500e0dc5481b1ee9cf6b38bb3b473f6e411eb62b83dc9b62699c3b7b79f7 \
+    --hash=sha256:585c4dc429deebc4307187d2b71ebe914843185ae16a4d582ee030e6cfbb4d8a \
+    --hash=sha256:5865b270b420eda7b68928d70bb517ccbe045e53b1a428129bb44372bf3d7dd5 \
+    --hash=sha256:5881aaa4bf3a2d086c5f20371d3a5856199a0d8ac72dd8d0dbd7a2ecfc26ab73 \
+    --hash=sha256:5885bc586f1edb48e5d68e7a4b4757b5feb2a496b64f462b4d65950f5af3364f \
+    --hash=sha256:5a11b16a33656ffc43c92a5343a28dc71eefe460bcc2a4923a96f292692709f6 \
+    --hash=sha256:5a997b784a639e05b9d4053ef3b20c7e447ea80814a762f25b8ed5a89d261eac \
+    --hash=sha256:5be8f5e4044146a69c96077c7e08f0709c13a314aa5315981185c1f00235fe65 \
+    --hash=sha256:63d57fc94eb0bbb4735e45517afc21ef262991d8758a8f2f05dd6e4174944519 \
+    --hash=sha256:673b9d8e780f455091200bba8534d5f4f465944cbdd61f31dc832d70e29064a5 \
+    --hash=sha256:67d2f8ad9dcc3a9e826bdc7802ed541a44e124c29b7d95a679eeb58c1c14ade8 \
+    --hash=sha256:67f5e80adf0aafc7b5454f2c1cb0cde920c9b1f2cbd0485f07cc1d0497c35c5d \
+    --hash=sha256:68018c4c67d7e89951a91fbd371e2e34cd8cfc71f0bb43b5332db38497025d51 \
+    --hash=sha256:6c4dd3bfd0c82400060896717dd261137398edb7e524527438c54a8c34f736bf \
+    --hash=sha256:71f31eda4e370f46af42fc9f264fafa1b09f46ba07bdbee98f25689a04b81c20 \
+    --hash=sha256:7512b4d0fc5339d5abbb14d1843f70499cab90d0b864f790e73f780f041615d7 \
+    --hash=sha256:75fa3d6946d317ffc7016a6fcc44f42db6d514b7fdb8b4b28cbe058303cb6e53 \
+    --hash=sha256:779e851fd0e19795ccc8a9bb4d705d6baa0ef475329fe44a13cf1e962f18ff1e \
+    --hash=sha256:796520afa499732191e39fc95b56a3b07f95256f2d22b1c26e217fb69a9db5b5 \
+    --hash=sha256:7aae7a3d63b935babfdc6864b31196afd5145878ddd22f5200729006366bc4d5 \
+    --hash=sha256:7b82e67c5feb682dbb559c3e6b78355f234943053af61606af126df2183b9ef9 \
+    --hash=sha256:7c0536bd9178f754b277a3e53f90f9c9454a3bd108b1531ffff720e082d824f2 \
+    --hash=sha256:7eda194dd46e40ec745bf76795a7cccb02a6a41f445ad49d3cf66518b0bd9cff \
+    --hash=sha256:82a4bb10b0beef1434fb23a09f001ab5ca87895596b4581fd53f1e5145a8934a \
+    --hash=sha256:85c4f11be9cf08917ac2a5a8b6e1ef63b2f8e3799cec194417e76826e5f1de9c \
+    --hash=sha256:88b72eb7222d918c967202024812c2bfb4048deeb69ca328363fb8e15254c549 \
+    --hash=sha256:89934f9f791566e54c1d92cdc8f8fd0009447a5ecdb1ec6b810d5f8c4955f6be \
+    --hash=sha256:8b1942b3e4ed9ed551ed3083a2e6e0772de1e5e3aca872d955e2e86385fb7ff9 \
+    --hash=sha256:8ffb141361108e864ab5f1813f66e4e1164181227f9b1f105b042729b6c15125 \
+    --hash=sha256:8fffc08de02071c37865a155e5ea5fce0282e1546fd5bde7f6149fcaa32558ac \
+    --hash=sha256:91fb6a43d72b4f8863d21f347a9163eecbf36e76e2f51068d59cd004c506f332 \
+    --hash=sha256:928e75a7200a4c09e6efc7482a1337919cc61fe1ba289f297827a5b76d8969c2 \
+    --hash=sha256:96eef5b9f336f623ffc555ab47a775495e7e8846dde88de5f941e2906453a1ce \
+    --hash=sha256:a0611da6b07dd3720f492db1b463a4d1175b096b49438761cc9f35f0d9eaaef5 \
+    --hash=sha256:a091026c3bf7519ab1e64655a3f52a59ad4a4e019a6f830c24d6430695b1cf6a \
+    --hash=sha256:a22f66270bd6d0804b02cd49dae2b33d4341015545d17f8426f2c4e22f557a23 \
+    --hash=sha256:a243132767150a44e6a93cd1dde41010036e1cbc63cc3e9fe1712b277d926ce3 \
+    --hash=sha256:a31fa7536ec1fb7155a0cd3a4e3d956c835ad0a43e3610ca32384d01f079ea1c \
+    --hash=sha256:a364e8e944d92dcbf33b6b494d4e0fb3499dcc3bd9485beb701aa4b4201fa414 \
+    --hash=sha256:a4058f16cee694577f7e4dd410263cd0ef75644b43802a689c2b3c2a7e69453b \
+    --hash=sha256:a4b382e0e636ed54cd278791d93fe2c4f370772743f02bcbe431a160089025c9 \
+    --hash=sha256:a83d3adea1e0ee36dac34627f78ddd7f093bb9cfc0a8e97f1572a949b695cb98 \
+    --hash=sha256:a8ade0363f776f87f982572c2860cc43c65ace208db49c76df0a21dde4ddd16e \
+    --hash=sha256:aa59974880ab5ad8ef3afaa26f9bda148c5f39e06b11a8ada4660ecc9fb2feb3 \
+    --hash=sha256:aa826340a609d0c954ba52fd831f0fba2a4165659ab0ee1a15e4aac21f302406 \
+    --hash=sha256:aaca5a812f050ab55426c32177091130b1e49329b3f002a32934cd0245571307 \
+    --hash=sha256:ae82fce1d964f065c32c9517309f0c7be588772352d2f40b1574a214bd6e6098 \
+    --hash=sha256:aed57b541b589fa05ac248f4cb1c46cbb432ab82cbd467d1c4f6a2bdc18aecf9 \
+    --hash=sha256:afa578b6524ff85fb365f454cf61683771d0170470c48ad9d170c48075f86725 \
+    --hash=sha256:b0884e3f22d87c30694e625b1e62e6f30d39782c806287450d9dc2fdf07692fd \
+    --hash=sha256:b2aca14c235c7a08558fe0a4786a1a05873a01e86b474dfa8f6df49101853a4e \
+    --hash=sha256:b450d7cabcd49aa7ab46a3c6aa3ac7e1593600a1a0605ba536ec0f1b99a04322 \
+    --hash=sha256:b725e70d15906d24615201e650d5b0388b08a5187a55f119f25874d0103f90dd \
+    --hash=sha256:bfbbab9316330cf81656fed435311386610f78b6c93cc5db4bebbce8dd146675 \
+    --hash=sha256:c093c7088b40d8266f57ed71d93112bd64c6724d31f0794c1e52cc4857c28e0e \
+    --hash=sha256:c2e49dc23a10a1296b04ca9db200c44d3eb32c8d8ec532e8c1fd24792276522a \
+    --hash=sha256:c4393600915c308e546dc7003d74371744234e8444a28622d76fe19b98fa59d1 \
+    --hash=sha256:c5ae125276f254b01daa73e2c103363d3e99e3e10505686ac7d9d2442dd4627a \
+    --hash=sha256:c6aacf00d05b38a5069826e50ae72751cb5bc27bdc4d5746203988e429b385bb \
+    --hash=sha256:c76722b5ed4a31ba103e0dc77ab869222ec36efe1a614e42e9bcea88a36186fe \
+    --hash=sha256:c809eef167bf4a57af4b03007004896f5c60bd38dc3852fcd97a26eae3d4c9e6 \
+    --hash=sha256:c92ea6d9dd84a750b2bae72ff5e8cf5fdd13e58dda79c33e057862c29a8d5b50 \
+    --hash=sha256:cb659702a45136c743bc130760c6f137870d4df3a9e14386478b8a0511abcfca \
+    --hash=sha256:ce0930a963ff593e8bb6fda49a503911accc67dee7e5445eec972668e672a0f0 \
+    --hash=sha256:d0751528b97d2b19a388b302be2a0ee05817097bab46ff0ed76feeec24951f78 \
+    --hash=sha256:d184f85ad2bb1f261eac55cddfcf62a70dee89982c978e92b9a74a1bfef2e367 \
+    --hash=sha256:d2a3e412ce1849be34b45922bfef03df32d1410a06d1cdeb793a343c2f1fd666 \
+    --hash=sha256:d61ec60945d694df806a9aec88e8f29a27293c6e424f8ff91c80416e3c617645 \
+    --hash=sha256:db0c742aad702fd5d0c6611a73f9602f20aec2007c102630c06d7633d9c8f09a \
+    --hash=sha256:db4743e30d6f5f92b6d2b7c86b3ad250e0bad8dee4b7ad8a0c44bfb276af89a3 \
+    --hash=sha256:dbf7bebc2275016cddf3c997bf8a0f7044160714c64a9b83975670a04e6d2252 \
+    --hash=sha256:de1fc314c3ad6bc2f6bd5b5a5b9357b8c6896333d27fdbb7049aea8bd5af2d79 \
+    --hash=sha256:df7e5edac4778127f2bf452e0721a58a1cfa4d1d9eac63bdd650535eb8543615 \
+    --hash=sha256:e220f7b3e8656ab063d2eb0cd536fafef396829cafe04cb314e734f87649058f \
+    --hash=sha256:e3c623923967f3e5961d272718655946e5322b8d058e094764180cdee7bab1af \
+    --hash=sha256:e69add9b6b7b08c60d7ff0152c7c9a6c45b4a71a919be5abde6f98f1ea16421c \
+    --hash=sha256:e8e0d177b1fe251c3b1b914ab64135475c5273c8cfd2857964b2e3bb0fe196a7 \
+    --hash=sha256:ef45f31aec9be01379fc6c10f1d9c677f032f2bac9383c827d44f620e8a88407 \
+    --hash=sha256:f1208c1c67ec9e151d78aa3435aa9b08a488b53d9cfac9b699f15255a3461ef2 \
+    --hash=sha256:f12582b8d3b4c6be1d298c49cb7ae64a3a73efaf4c2ab4e37db182e3545815ac \
+    --hash=sha256:f1de541a9893cf8a1b1db9bf0bf670a2decab42e3e82233d36a74eda7822b4c9 \
+    --hash=sha256:f4eac0584cdc3285ef2e74eee1513a6001681fd9753b259e8159421ed28a72e5 \
+    --hash=sha256:f7b64fcd670bca8800bc10ced36620c6bbb321e7bc1214b9c0c0df269c1dddc2 \
+    --hash=sha256:fb7c61d4be18e930f75948705e9718618862e6fc2ed0d7159b2262be73f167a2
+    # via doxmlparser
+markupsafe==3.0.2 \
+    --hash=sha256:0bff5e0ae4ef2e1ae4fdf2dfd5b76c75e5c2fa4132d05fc1b0dabcd20c7e28c4 \
+    --hash=sha256:0f4ca02bea9a23221c0182836703cbf8930c5e9454bacce27e767509fa286a30 \
+    --hash=sha256:1225beacc926f536dc82e45f8a4d68502949dc67eea90eab715dea3a21c1b5f0 \
+    --hash=sha256:131a3c7689c85f5ad20f9f6fb1b866f402c445b220c19fe4308c0b147ccd2ad9 \
+    --hash=sha256:15ab75ef81add55874e7ab7055e9c397312385bd9ced94920f2802310c930396 \
+    --hash=sha256:1a9d3f5f0901fdec14d8d2f66ef7d035f2157240a433441719ac9a3fba440b13 \
+    --hash=sha256:1c99d261bd2d5f6b59325c92c73df481e05e57f19837bdca8413b9eac4bd8028 \
+    --hash=sha256:1e084f686b92e5b83186b07e8a17fc09e38fff551f3602b249881fec658d3eca \
+    --hash=sha256:2181e67807fc2fa785d0592dc2d6206c019b9502410671cc905d132a92866557 \
+    --hash=sha256:2cb8438c3cbb25e220c2ab33bb226559e7afb3baec11c4f218ffa7308603c832 \
+    --hash=sha256:3169b1eefae027567d1ce6ee7cae382c57fe26e82775f460f0b2778beaad66c0 \
+    --hash=sha256:3809ede931876f5b2ec92eef964286840ed3540dadf803dd570c3b7e13141a3b \
+    --hash=sha256:38a9ef736c01fccdd6600705b09dc574584b89bea478200c5fbf112a6b0d5579 \
+    --hash=sha256:3d79d162e7be8f996986c064d1c7c817f6df3a77fe3d6859f6f9e7be4b8c213a \
+    --hash=sha256:444dcda765c8a838eaae23112db52f1efaf750daddb2d9ca300bcae1039adc5c \
+    --hash=sha256:48032821bbdf20f5799ff537c7ac3d1fba0ba032cfc06194faffa8cda8b560ff \
+    --hash=sha256:4aa4e5faecf353ed117801a068ebab7b7e09ffb6e1d5e412dc852e0da018126c \
+    --hash=sha256:52305740fe773d09cffb16f8ed0427942901f00adedac82ec8b67752f58a1b22 \
+    --hash=sha256:569511d3b58c8791ab4c2e1285575265991e6d8f8700c7be0e88f86cb0672094 \
+    --hash=sha256:57cb5a3cf367aeb1d316576250f65edec5bb3be939e9247ae594b4bcbc317dfb \
+    --hash=sha256:5b02fb34468b6aaa40dfc198d813a641e3a63b98c2b05a16b9f80b7ec314185e \
+    --hash=sha256:6381026f158fdb7c72a168278597a5e3a5222e83ea18f543112b2662a9b699c5 \
+    --hash=sha256:6af100e168aa82a50e186c82875a5893c5597a0c1ccdb0d8b40240b1f28b969a \
+    --hash=sha256:6c89876f41da747c8d3677a2b540fb32ef5715f97b66eeb0c6b66f5e3ef6f59d \
+    --hash=sha256:6e296a513ca3d94054c2c881cc913116e90fd030ad1c656b3869762b754f5f8a \
+    --hash=sha256:70a87b411535ccad5ef2f1df5136506a10775d267e197e4cf531ced10537bd6b \
+    --hash=sha256:7e94c425039cde14257288fd61dcfb01963e658efbc0ff54f5306b06054700f8 \
+    --hash=sha256:846ade7b71e3536c4e56b386c2a47adf5741d2d8b94ec9dc3e92e5e1ee1e2225 \
+    --hash=sha256:88416bd1e65dcea10bc7569faacb2c20ce071dd1f87539ca2ab364bf6231393c \
+    --hash=sha256:88b49a3b9ff31e19998750c38e030fc7bb937398b1f78cfa599aaef92d693144 \
+    --hash=sha256:8c4e8c3ce11e1f92f6536ff07154f9d49677ebaaafc32db9db4620bc11ed480f \
+    --hash=sha256:8e06879fc22a25ca47312fbe7c8264eb0b662f6db27cb2d3bbbc74b1df4b9b87 \
+    --hash=sha256:9025b4018f3a1314059769c7bf15441064b2207cb3f065e6ea1e7359cb46db9d \
+    --hash=sha256:93335ca3812df2f366e80509ae119189886b0f3c2b81325d39efdb84a1e2ae93 \
+    --hash=sha256:9778bd8ab0a994ebf6f84c2b949e65736d5575320a17ae8984a77fab08db94cf \
+    --hash=sha256:9e2d922824181480953426608b81967de705c3cef4d1af983af849d7bd619158 \
+    --hash=sha256:a123e330ef0853c6e822384873bef7507557d8e4a082961e1defa947aa59ba84 \
+    --hash=sha256:a904af0a6162c73e3edcb969eeeb53a63ceeb5d8cf642fade7d39e7963a22ddb \
+    --hash=sha256:ad10d3ded218f1039f11a75f8091880239651b52e9bb592ca27de44eed242a48 \
+    --hash=sha256:b424c77b206d63d500bcb69fa55ed8d0e6a3774056bdc4839fc9298a7edca171 \
+    --hash=sha256:b5a6b3ada725cea8a5e634536b1b01c30bcdcd7f9c6fff4151548d5bf6b3a36c \
+    --hash=sha256:ba8062ed2cf21c07a9e295d5b8a2a5ce678b913b45fdf68c32d95d6c1291e0b6 \
+    --hash=sha256:ba9527cdd4c926ed0760bc301f6728ef34d841f405abf9d4f959c478421e4efd \
+    --hash=sha256:bbcb445fa71794da8f178f0f6d66789a28d7319071af7a496d4d507ed566270d \
+    --hash=sha256:bcf3e58998965654fdaff38e58584d8937aa3096ab5354d493c77d1fdd66d7a1 \
+    --hash=sha256:c0ef13eaeee5b615fb07c9a7dadb38eac06a0608b41570d8ade51c56539e509d \
+    --hash=sha256:cabc348d87e913db6ab4aa100f01b08f481097838bdddf7c7a84b7575b7309ca \
+    --hash=sha256:cdb82a876c47801bb54a690c5ae105a46b392ac6099881cdfb9f6e95e4014c6a \
+    --hash=sha256:cfad01eed2c2e0c01fd0ecd2ef42c492f7f93902e39a42fc9ee1692961443a29 \
+    --hash=sha256:d16a81a06776313e817c951135cf7340a3e91e8c1ff2fac444cfd75fffa04afe \
+    --hash=sha256:d8213e09c917a951de9d09ecee036d5c7d36cb6cb7dbaece4c71a60d79fb9798 \
+    --hash=sha256:e07c3764494e3776c602c1e78e298937c3315ccc9043ead7e685b7f2b8d47b3c \
+    --hash=sha256:e17c96c14e19278594aa4841ec148115f9c7615a47382ecb6b82bd8fea3ab0c8 \
+    --hash=sha256:e444a31f8db13eb18ada366ab3cf45fd4b31e4db1236a4448f68778c1d1a5a2f \
+    --hash=sha256:e6a2a455bd412959b57a172ce6328d2dd1f01cb2135efda2e4576e8a23fa3b0f \
+    --hash=sha256:eaa0a10b7f72326f1372a713e73c3f739b524b3af41feb43e4921cb529f5929a \
+    --hash=sha256:eb7972a85c54febfb25b5c4b4f3af4dcc731994c7da0d8a0b4a6eb0640e1d178 \
+    --hash=sha256:ee55d3edf80167e48ea11a923c7386f4669df67d7994554387f84e7d8b0a2bf0 \
+    --hash=sha256:f3818cb119498c0678015754eba762e0d61e5b52d34c8b13d770f0719f7b1d79 \
+    --hash=sha256:f8b3d067f2e40fe93e1ccdd6b2e1d16c43140e76f02fb1319a05cf2b79d99430 \
+    --hash=sha256:fcabf5ff6eea076f859677f5f0b6b5c1a51e70a376b0579e0eadef8db48c6b50
+    # via jinja2
+packaging==24.2 \
+    --hash=sha256:09abb1bccd265c01f4a3aa3f7a7db064b36514d2cba19a2f694fe6150451a759 \
+    --hash=sha256:c228a6dc5e932d346bc5739379109d49e8853dd8223571c7c5b55260edc0b97f
+    # via
+    #   pytest
+    #   sphinx
+pluggy==1.5.0 \
+    --hash=sha256:2cffa88e94fdc978c4c574f15f9e59b7f4201d439195c3715ca9e2486f1d0cf1 \
+    --hash=sha256:44e1ad92c8ca002de6377e165f3e0f1be63266ab4d554740532335b9d75ea669
+    # via pytest
+pygments==2.19.1 \
+    --hash=sha256:61c16d2a8576dc0649d9f39e089b5f02bcd27fba10d8fb4dcc28173f7a45151f \
+    --hash=sha256:9ea1544ad55cecf4b8242fab6dd35a93bbce657034b0611ee383099054ab6d8c
+    # via
+    #   -r requirements.in
+    #   sphinx
+    #   sphinx-tabs
+pykwalify==1.8.0 \
+    --hash=sha256:731dfa87338cca9f559d1fca2bdea37299116e3139b73f78ca90a543722d6651 \
+    --hash=sha256:796b2ad3ed4cb99b88308b533fb2f559c30fa6efb4fa9fda11347f483d245884
+    # via -r requirements.in
+pyserial==3.5 \
+    --hash=sha256:3c77e014170dfffbd816e6ffc205e9842efb10be9f58ec16d3e8675b4925cddb \
+    --hash=sha256:c4451db6ba391ca6ca299fb3ec7bae67a5c55dde170964c7a14ceefec02f2cf0
+    # via -r requirements.in
+pytest==8.3.5 \
+    --hash=sha256:c69214aa47deac29fad6c2a4f590b9c4a9fdb16a403176fe154b79c0b4d4d820 \
+    --hash=sha256:f4efe70cc14e511565ac476b57c279e12a855b11f48f212af1080ef2263d3845
+    # via -r requirements.in
+python-dateutil==2.9.0.post0 \
+    --hash=sha256:37dd54208da7e1cd875388217d5e00ebd4179249f90fb72437e91a35459a0ad3 \
+    --hash=sha256:a8b2bc7bffae282281c8140a97d3aa9c14da0b136dfe83f850eea9a5f7470427
+    # via pykwalify
+pyyaml==6.0.2 \
+    --hash=sha256:01179a4a8559ab5de078078f37e5c1a30d76bb88519906844fd7bdea1b7729ff \
+    --hash=sha256:0833f8694549e586547b576dcfaba4a6b55b9e96098b36cdc7ebefe667dfed48 \
+    --hash=sha256:0a9a2848a5b7feac301353437eb7d5957887edbf81d56e903999a75a3d743086 \
+    --hash=sha256:0b69e4ce7a131fe56b7e4d770c67429700908fc0752af059838b1cfb41960e4e \
+    --hash=sha256:0ffe8360bab4910ef1b9e87fb812d8bc0a308b0d0eef8c8f44e0254ab3b07133 \
+    --hash=sha256:11d8f3dd2b9c1207dcaf2ee0bbbfd5991f571186ec9cc78427ba5bd32afae4b5 \
+    --hash=sha256:17e311b6c678207928d649faa7cb0d7b4c26a0ba73d41e99c4fff6b6c3276484 \
+    --hash=sha256:1e2120ef853f59c7419231f3bf4e7021f1b936f6ebd222406c3b60212205d2ee \
+    --hash=sha256:1f71ea527786de97d1a0cc0eacd1defc0985dcf6b3f17bb77dcfc8c34bec4dc5 \
+    --hash=sha256:23502f431948090f597378482b4812b0caae32c22213aecf3b55325e049a6c68 \
+    --hash=sha256:24471b829b3bf607e04e88d79542a9d48bb037c2267d7927a874e6c205ca7e9a \
+    --hash=sha256:29717114e51c84ddfba879543fb232a6ed60086602313ca38cce623c1d62cfbf \
+    --hash=sha256:2e99c6826ffa974fe6e27cdb5ed0021786b03fc98e5ee3c5bfe1fd5015f42b99 \
+    --hash=sha256:39693e1f8320ae4f43943590b49779ffb98acb81f788220ea932a6b6c51004d8 \
+    --hash=sha256:3ad2a3decf9aaba3d29c8f537ac4b243e36bef957511b4766cb0057d32b0be85 \
+    --hash=sha256:3b1fdb9dc17f5a7677423d508ab4f243a726dea51fa5e70992e59a7411c89d19 \
+    --hash=sha256:41e4e3953a79407c794916fa277a82531dd93aad34e29c2a514c2c0c5fe971cc \
+    --hash=sha256:43fa96a3ca0d6b1812e01ced1044a003533c47f6ee8aca31724f78e93ccc089a \
+    --hash=sha256:50187695423ffe49e2deacb8cd10510bc361faac997de9efef88badc3bb9e2d1 \
+    --hash=sha256:5ac9328ec4831237bec75defaf839f7d4564be1e6b25ac710bd1a96321cc8317 \
+    --hash=sha256:5d225db5a45f21e78dd9358e58a98702a0302f2659a3c6cd320564b75b86f47c \
+    --hash=sha256:6395c297d42274772abc367baaa79683958044e5d3835486c16da75d2a694631 \
+    --hash=sha256:688ba32a1cffef67fd2e9398a2efebaea461578b0923624778664cc1c914db5d \
+    --hash=sha256:68ccc6023a3400877818152ad9a1033e3db8625d899c72eacb5a668902e4d652 \
+    --hash=sha256:70b189594dbe54f75ab3a1acec5f1e3faa7e8cf2f1e08d9b561cb41b845f69d5 \
+    --hash=sha256:797b4f722ffa07cc8d62053e4cff1486fa6dc094105d13fea7b1de7d8bf71c9e \
+    --hash=sha256:7c36280e6fb8385e520936c3cb3b8042851904eba0e58d277dca80a5cfed590b \
+    --hash=sha256:7e7401d0de89a9a855c839bc697c079a4af81cf878373abd7dc625847d25cbd8 \
+    --hash=sha256:80bab7bfc629882493af4aa31a4cfa43a4c57c83813253626916b8c7ada83476 \
+    --hash=sha256:82d09873e40955485746739bcb8b4586983670466c23382c19cffecbf1fd8706 \
+    --hash=sha256:8388ee1976c416731879ac16da0aff3f63b286ffdd57cdeb95f3f2e085687563 \
+    --hash=sha256:8824b5a04a04a047e72eea5cec3bc266db09e35de6bdfe34c9436ac5ee27d237 \
+    --hash=sha256:8b9c7197f7cb2738065c481a0461e50ad02f18c78cd75775628afb4d7137fb3b \
+    --hash=sha256:9056c1ecd25795207ad294bcf39f2db3d845767be0ea6e6a34d856f006006083 \
+    --hash=sha256:936d68689298c36b53b29f23c6dbb74de12b4ac12ca6cfe0e047bedceea56180 \
+    --hash=sha256:9b22676e8097e9e22e36d6b7bda33190d0d400f345f23d4065d48f4ca7ae0425 \
+    --hash=sha256:a4d3091415f010369ae4ed1fc6b79def9416358877534caf6a0fdd2146c87a3e \
+    --hash=sha256:a8786accb172bd8afb8be14490a16625cbc387036876ab6ba70912730faf8e1f \
+    --hash=sha256:a9f8c2e67970f13b16084e04f134610fd1d374bf477b17ec1599185cf611d725 \
+    --hash=sha256:bc2fa7c6b47d6bc618dd7fb02ef6fdedb1090ec036abab80d4681424b84c1183 \
+    --hash=sha256:c70c95198c015b85feafc136515252a261a84561b7b1d51e3384e0655ddf25ab \
+    --hash=sha256:cc1c1159b3d456576af7a3e4d1ba7e6924cb39de8f67111c735f6fc832082774 \
+    --hash=sha256:ce826d6ef20b1bc864f0a68340c8b3287705cae2f8b4b1d932177dcc76721725 \
+    --hash=sha256:d584d9ec91ad65861cc08d42e834324ef890a082e591037abe114850ff7bbc3e \
+    --hash=sha256:d7fded462629cfa4b685c5416b949ebad6cec74af5e2d42905d41e257e0869f5 \
+    --hash=sha256:d84a1718ee396f54f3a086ea0a66d8e552b2ab2017ef8b420e92edbc841c352d \
+    --hash=sha256:d8e03406cac8513435335dbab54c0d385e4a49e4945d2909a581c83647ca0290 \
+    --hash=sha256:e10ce637b18caea04431ce14fabcf5c64a1c61ec9c56b071a4b7ca131ca52d44 \
+    --hash=sha256:ec031d5d2feb36d1d1a24380e4db6d43695f3748343d99434e6f5f9156aaa2ed \
+    --hash=sha256:ef6107725bd54b262d6dedcc2af448a266975032bc85ef0172c5f059da6325b4 \
+    --hash=sha256:efdca5630322a10774e8e98e1af481aad470dd62c3170801852d752aa7a783ba \
+    --hash=sha256:f753120cb8181e736c57ef7636e83f31b9c0d1722c516f7e86cf15b7aa57ff12 \
+    --hash=sha256:ff3824dc5261f50c9b0dfb3be22b4567a6f938ccce4587b38952d85fd9e9afe4
+    # via -r requirements.in
+requests==2.32.3 \
+    --hash=sha256:55365417734eb18255590a9ff9eb97e9e1da868d4ccd6402399eaf68af20a760 \
+    --hash=sha256:70761cfe03c773ceb22aa2f671b4757976145175cdfca038c02654d061d6dcc6
+    # via sphinx
+roman-numerals-py==3.1.0 ; python_full_version >= '3.11' \
+    --hash=sha256:9da2ad2fb670bcf24e81070ceb3be72f6c11c440d73bd579fbeca1e9f330954c \
+    --hash=sha256:be4bf804f083a4ce001b5eb7e3c0862479d10f94c936f6c4e5f250aa5ff5bd2d
+    # via sphinx
+ruamel-yaml==0.18.10 \
+    --hash=sha256:20c86ab29ac2153f80a428e1254a8adf686d3383df04490514ca3b79a362db58 \
+    --hash=sha256:30f22513ab2301b3d2b577adc121c6471f28734d3d9728581245f1e76468b4f1
+    # via pykwalify
+ruamel-yaml-clib==0.2.12 ; python_full_version < '3.13' and platform_python_implementation == 'CPython' \
+    --hash=sha256:040ae85536960525ea62868b642bdb0c2cc6021c9f9d507810c0c604e66f5a7b \
+    --hash=sha256:0467c5965282c62203273b838ae77c0d29d7638c8a4e3a1c8bdd3602c10904e4 \
+    --hash=sha256:0b7e75b4965e1d4690e93021adfcecccbca7d61c7bddd8e22406ef2ff20d74ef \
+    --hash=sha256:11f891336688faf5156a36293a9c362bdc7c88f03a8a027c2c1d8e0bcde998e5 \
+    --hash=sha256:1492a6051dab8d912fc2adeef0e8c72216b24d57bd896ea607cb90bb0c4981d3 \
+    --hash=sha256:20b0f8dc160ba83b6dcc0e256846e1a02d044e13f7ea74a3d1d56ede4e48c632 \
+    --hash=sha256:22353049ba4181685023b25b5b51a574bce33e7f51c759371a7422dcae5402a6 \
+    --hash=sha256:2c59aa6170b990d8d2719323e628aaf36f3bfbc1c26279c0eeeb24d05d2d11c7 \
+    --hash=sha256:32621c177bbf782ca5a18ba4d7af0f1082a3f6e517ac2a18b3974d4edf349680 \
+    --hash=sha256:3bc2a80e6420ca8b7d3590791e2dfc709c88ab9152c00eeb511c9875ce5778bf \
+    --hash=sha256:3eac5a91891ceb88138c113f9db04f3cebdae277f5d44eaa3651a4f573e6a5da \
+    --hash=sha256:4a6679521a58256a90b0d89e03992c15144c5f3858f40d7c18886023d7943db6 \
+    --hash=sha256:4c8c5d82f50bb53986a5e02d1b3092b03622c02c2eb78e29bec33fd9593bae1a \
+    --hash=sha256:4f6f3eac23941b32afccc23081e1f50612bdbe4e982012ef4f5797986828cd01 \
+    --hash=sha256:5a0e060aace4c24dcaf71023bbd7d42674e3b230f7e7b97317baf1e953e5b519 \
+    --hash=sha256:6442cb36270b3afb1b4951f060eccca1ce49f3d087ca1ca4563a6eb479cb3de6 \
+    --hash=sha256:6c8fbb13ec503f99a91901ab46e0b07ae7941cd527393187039aec586fdfd36f \
+    --hash=sha256:749c16fcc4a2b09f28843cda5a193e0283e47454b63ec4b81eaa2242f50e4ccd \
+    --hash=sha256:7dd5adc8b930b12c8fc5b99e2d535a09889941aa0d0bd06f4749e9a9397c71d2 \
+    --hash=sha256:811ea1594b8a0fb466172c384267a4e5e367298af6b228931f273b111f17ef52 \
+    --hash=sha256:932205970b9f9991b34f55136be327501903f7c66830e9760a8ffb15b07f05cd \
+    --hash=sha256:943f32bc9dedb3abff9879edc134901df92cfce2c3d5c9348f172f62eb2d771d \
+    --hash=sha256:95c3829bb364fdb8e0332c9931ecf57d9be3519241323c5274bd82f709cebc0c \
+    --hash=sha256:96777d473c05ee3e5e3c3e999f5d23c6f4ec5b0c38c098b3a5229085f74236c6 \
+    --hash=sha256:a274fb2cb086c7a3dea4322ec27f4cb5cc4b6298adb583ab0e211a4682f241eb \
+    --hash=sha256:a52d48f4e7bf9005e8f0a89209bf9a73f7190ddf0489eee5eb51377385f59f2a \
+    --hash=sha256:a606ef75a60ecf3d924613892cc603b154178ee25abb3055db5062da811fd969 \
+    --hash=sha256:ab007f2f5a87bd08ab1499bdf96f3d5c6ad4dcfa364884cb4549aa0154b13a28 \
+    --hash=sha256:b82a7c94a498853aa0b272fd5bc67f29008da798d4f93a2f9f289feb8426a58d \
+    --hash=sha256:bb43a269eb827806502c7c8efb7ae7e9e9d0573257a46e8e952f4d4caba4f31e \
+    --hash=sha256:bc5f1e1c28e966d61d2519f2a3d451ba989f9ea0f2307de7bc45baa526de9e45 \
+    --hash=sha256:bd0a08f0bab19093c54e18a14a10b4322e1eacc5217056f3c063bd2f59853ce4 \
+    --hash=sha256:beffaed67936fbbeffd10966a4eb53c402fafd3d6833770516bf7314bc6ffa12 \
+    --hash=sha256:bf165fef1f223beae7333275156ab2022cffe255dcc51c27f066b4370da81e31 \
+    --hash=sha256:cf12567a7b565cbf65d438dec6cfbe2917d3c1bdddfce84a9930b7d35ea59642 \
+    --hash=sha256:d84318609196d6bd6da0edfa25cedfbabd8dbde5140a0a23af29ad4b8f91fb1e \
+    --hash=sha256:d85252669dc32f98ebcd5d36768f5d4faeaeaa2d655ac0473be490ecdae3c285 \
+    --hash=sha256:e143ada795c341b56de9418c58d028989093ee611aa27ffb9b7f609c00d813ed \
+    --hash=sha256:e188d2699864c11c36cdfdada94d781fd5d6b0071cd9c427bceb08ad3d7c70e1 \
+    --hash=sha256:e2f1c3765db32be59d18ab3953f43ab62a761327aafc1594a2a1fbe038b8b8a7 \
+    --hash=sha256:e5b8daf27af0b90da7bb903a876477a9e6d7270be6146906b276605997c7e9a3 \
+    --hash=sha256:e7e3736715fbf53e9be2a79eb4db68e4ed857017344d697e8b9749444ae57475 \
+    --hash=sha256:e8c4ebfcfd57177b572e2040777b8abc537cdef58a2120e830124946aa9b42c5 \
+    --hash=sha256:f66efbc1caa63c088dead1c4170d148eabc9b80d95fb75b6c92ac0aad2437d76 \
+    --hash=sha256:fc4b630cd3fa2cf7fce38afa91d7cfe844a9f75d7f0f36393fa98815e911d987 \
+    --hash=sha256:fd5415dded15c3822597455bc02bcd66e81ef8b7a48cb71a33628fc9fdde39df
+    # via ruamel-yaml
+setuptools==78.1.0 \
+    --hash=sha256:18fd474d4a82a5f83dac888df697af65afa82dec7323d09c3e37d1f14288da54 \
+    --hash=sha256:3e386e96793c8702ae83d17b853fb93d3e09ef82ec62722e61da5cd22376dcd8
+    # via sphinx-togglebutton
+six==1.17.0 \
+    --hash=sha256:4721f391ed90541fddacab5acf947aa0d3dc7d27b2e1e8eda2be8970586c3274 \
+    --hash=sha256:ff70335d468e7eb6ec65b95b99d3a2836546063f63acc5171de367e834932a81
+    # via
+    #   anytree
+    #   doxmlparser
+    #   python-dateutil
+sniffio==1.3.1 \
+    --hash=sha256:2f6da418d1f1e0fddd844478f41680e794e6051915791a034ff65e5f100525a2 \
+    --hash=sha256:f4324edc670a0f49750a81b895f35c3adb843cca46f0530f79fc1babb23789dc
+    # via anyio
+snowballstemmer==2.2.0 \
+    --hash=sha256:09b16deb8547d3412ad7b590689584cd0fe25ec8db3be37788be3810cbf19cb1 \
+    --hash=sha256:c8e1716e83cc398ae16824e5572ae04e0d9fc2c6b985fb0f900f5f0c96ecba1a
+    # via sphinx
+sphinx==8.1.3 ; python_full_version < '3.11' \
+    --hash=sha256:09719015511837b76bf6e03e42eb7595ac8c2e41eeb9c29c5b755c6b677992a2 \
+    --hash=sha256:43c1911eecb0d3e161ad78611bc905d1ad0e523e4ddc202a58a821773dc4c927
+    # via
+    #   -r requirements.in
+    #   sphinx-autobuild
+    #   sphinx-copybutton
+    #   sphinx-notfound-page
+    #   sphinx-rtd-theme
+    #   sphinx-sitemap
+    #   sphinx-tabs
+    #   sphinx-togglebutton
+    #   sphinxcontrib-jquery
+    #   sphinxcontrib-svg2pdfconverter
+sphinx==8.2.3 ; python_full_version >= '3.11' \
+    --hash=sha256:398ad29dee7f63a75888314e9424d40f52ce5a6a87ae88e7071e80af296ec348 \
+    --hash=sha256:4405915165f13521d875a8c29c8970800a0141c14cc5416a38feca4ea5d9b9c3
+    # via
+    #   -r requirements.in
+    #   sphinx-autobuild
+    #   sphinx-copybutton
+    #   sphinx-notfound-page
+    #   sphinx-rtd-theme
+    #   sphinx-sitemap
+    #   sphinx-tabs
+    #   sphinx-togglebutton
+    #   sphinxcontrib-jquery
+    #   sphinxcontrib-svg2pdfconverter
+sphinx-autobuild==2024.10.3 \
+    --hash=sha256:158e16c36f9d633e613c9aaf81c19b0fc458ca78b112533b20dafcda430d60fa \
+    --hash=sha256:248150f8f333e825107b6d4b86113ab28fa51750e5f9ae63b59dc339be951fb1
+    # via -r requirements.in
+sphinx-copybutton==0.5.2 \
+    --hash=sha256:4cf17c82fb9646d1bc9ca92ac280813a3b605d8c421225fd9913154103ee1fbd \
+    --hash=sha256:fb543fd386d917746c9a2c50360c7905b605726b9355cd26e9974857afeae06e
+    # via -r requirements.in
+sphinx-notfound-page==1.1.0 \
+    --hash=sha256:835dc76ff7914577a1f58d80a2c8418fb6138c0932c8da8adce4d9096fbcd389 \
+    --hash=sha256:913e1754370bb3db201d9300d458a8b8b5fb22e9246a816643a819a9ea2b8067
+    # via -r requirements.in
+sphinx-rtd-theme==3.0.2 \
+    --hash=sha256:422ccc750c3a3a311de4ae327e82affdaf59eb695ba4936538552f3b00f4ee13 \
+    --hash=sha256:b7457bc25dda723b20b086a670b9953c859eab60a2a03ee8eb2bb23e176e5f85
+    # via -r requirements.in
+sphinx-sitemap==2.6.0 \
+    --hash=sha256:5e0c66b9f2e371ede80c659866a9eaad337d46ab02802f9c7e5f7bc5893c28d2 \
+    --hash=sha256:7478e417d141f99c9af27ccd635f44c03a471a08b20e778a0f9daef7ace1d30b
+    # via -r requirements.in
+sphinx-tabs==3.4.7 \
+    --hash=sha256:991ad4a424ff54119799ba1491701aa8130dd43509474aef45a81c42d889784d \
+    --hash=sha256:c12d7a36fd413b369e9e9967a0a4015781b71a9c393575419834f19204bd1915
+    # via -r requirements.in
+sphinx-togglebutton==0.3.2 \
+    --hash=sha256:9647ba7874b7d1e2d43413d8497153a85edc6ac95a3fea9a75ef9c1e08aaae2b \
+    --hash=sha256:ab0c8b366427b01e4c89802d5d078472c427fa6e9d12d521c34fa0442559dc7a
+    # via -r requirements.in
+sphinxcontrib-applehelp==2.0.0 \
+    --hash=sha256:2f29ef331735ce958efa4734873f084941970894c6090408b079c61b2e1c06d1 \
+    --hash=sha256:4cd3f0ec4ac5dd9c17ec65e9ab272c9b867ea77425228e68ecf08d6b28ddbdb5
+    # via sphinx
+sphinxcontrib-devhelp==2.0.0 \
+    --hash=sha256:411f5d96d445d1d73bb5d52133377b4248ec79db5c793ce7dbe59e074b4dd1ad \
+    --hash=sha256:aefb8b83854e4b0998877524d1029fd3e6879210422ee3780459e28a1f03a8a2
+    # via sphinx
+sphinxcontrib-htmlhelp==2.1.0 \
+    --hash=sha256:166759820b47002d22914d64a075ce08f4c46818e17cfc9470a9786b759b19f8 \
+    --hash=sha256:c9e2916ace8aad64cc13a0d233ee22317f2b9025b9cf3295249fa985cc7082e9
+    # via sphinx
+sphinxcontrib-jquery==4.1 \
+    --hash=sha256:1620739f04e36a2c779f1a131a2dfd49b2fd07351bf1968ced074365933abc7a \
+    --hash=sha256:f936030d7d0147dd026a4f2b5a57343d233f1fc7b363f68b3d4f1cb0993878ae
+    # via sphinx-rtd-theme
+sphinxcontrib-jsmath==1.0.1 \
+    --hash=sha256:2ec2eaebfb78f3f2078e73666b1415417a116cc848b72e5172e596c871103178 \
+    --hash=sha256:a9925e4a4587247ed2191a22df5f6970656cb8ca2bd6284309578f2153e0c4b8
+    # via sphinx
+sphinxcontrib-qthelp==2.0.0 \
+    --hash=sha256:4fe7d0ac8fc171045be623aba3e2a8f613f8682731f9153bb2e40ece16b9bbab \
+    --hash=sha256:b18a828cdba941ccd6ee8445dbe72ffa3ef8cbe7505d8cd1fa0d42d3f2d5f3eb
+    # via sphinx
+sphinxcontrib-serializinghtml==2.0.0 \
+    --hash=sha256:6e2cb0eef194e10c27ec0023bfeb25badbbb5868244cf5bc5bdc04e4464bf331 \
+    --hash=sha256:e9d912827f872c029017a53f0ef2180b327c3f7fd23c87229f7a8e8b70031d4d
+    # via sphinx
+sphinxcontrib-svg2pdfconverter==1.3.0 \
+    --hash=sha256:5df6b0895e2e2101d720bfd08841bb56d74c57b1f86229a7c18b771dfdf4ffbb \
+    --hash=sha256:6411a4cc2f57eed96a0d7bbfa139f68cbe7983018881e1e6d7c46053cd69911f
+    # via -r requirements.in
+starlette==0.46.1 \
+    --hash=sha256:3c88d58ee4bd1bb807c0d1acb381838afc7752f9ddaec81bbe4383611d833230 \
+    --hash=sha256:77c74ed9d2720138b25875133f3a2dae6d854af2ec37dceb56aef370c1d8a227
+    # via sphinx-autobuild
+tomli==2.2.1 ; python_full_version < '3.11' \
+    --hash=sha256:023aa114dd824ade0100497eb2318602af309e5a55595f76b626d6d9f3b7b0a6 \
+    --hash=sha256:02abe224de6ae62c19f090f68da4e27b10af2b93213d36cf44e6e1c5abd19fdd \
+    --hash=sha256:286f0ca2ffeeb5b9bd4fcc8d6c330534323ec51b2f52da063b11c502da16f30c \
+    --hash=sha256:2d0f2fdd22b02c6d81637a3c95f8cd77f995846af7414c5c4b8d0545afa1bc4b \
+    --hash=sha256:33580bccab0338d00994d7f16f4c4ec25b776af3ffaac1ed74e0b3fc95e885a8 \
+    --hash=sha256:400e720fe168c0f8521520190686ef8ef033fb19fc493da09779e592861b78c6 \
+    --hash=sha256:40741994320b232529c802f8bc86da4e1aa9f413db394617b9a256ae0f9a7f77 \
+    --hash=sha256:465af0e0875402f1d226519c9904f37254b3045fc5084697cefb9bdde1ff99ff \
+    --hash=sha256:4a8f6e44de52d5e6c657c9fe83b562f5f4256d8ebbfe4ff922c495620a7f6cea \
+    --hash=sha256:4e340144ad7ae1533cb897d406382b4b6fede8890a03738ff1683af800d54192 \
+    --hash=sha256:678e4fa69e4575eb77d103de3df8a895e1591b48e740211bd1067378c69e8249 \
+    --hash=sha256:6972ca9c9cc9f0acaa56a8ca1ff51e7af152a9f87fb64623e31d5c83700080ee \
+    --hash=sha256:7fc04e92e1d624a4a63c76474610238576942d6b8950a2d7f908a340494e67e4 \
+    --hash=sha256:889f80ef92701b9dbb224e49ec87c645ce5df3fa2cc548664eb8a25e03127a98 \
+    --hash=sha256:8d57ca8095a641b8237d5b079147646153d22552f1c637fd3ba7f4b0b29167a8 \
+    --hash=sha256:8dd28b3e155b80f4d54beb40a441d366adcfe740969820caf156c019fb5c7ec4 \
+    --hash=sha256:9316dc65bed1684c9a98ee68759ceaed29d229e985297003e494aa825ebb0281 \
+    --hash=sha256:a198f10c4d1b1375d7687bc25294306e551bf1abfa4eace6650070a5c1ae2744 \
+    --hash=sha256:a38aa0308e754b0e3c67e344754dff64999ff9b513e691d0e786265c93583c69 \
+    --hash=sha256:a92ef1a44547e894e2a17d24e7557a5e85a9e1d0048b0b5e7541f76c5032cb13 \
+    --hash=sha256:ac065718db92ca818f8d6141b5f66369833d4a80a9d74435a268c52bdfa73140 \
+    --hash=sha256:b82ebccc8c8a36f2094e969560a1b836758481f3dc360ce9a3277c65f374285e \
+    --hash=sha256:c954d2250168d28797dd4e3ac5cf812a406cd5a92674ee4c8f123c889786aa8e \
+    --hash=sha256:cb55c73c5f4408779d0cf3eef9f762b9c9f147a77de7b258bef0a5628adc85cc \
+    --hash=sha256:cd45e1dc79c835ce60f7404ec8119f2eb06d38b1deba146f07ced3bbc44505ff \
+    --hash=sha256:d3f5614314d758649ab2ab3a62d4f2004c825922f9e370b29416484086b264ec \
+    --hash=sha256:d920f33822747519673ee656a4b6ac33e382eca9d331c87770faa3eef562aeb2 \
+    --hash=sha256:db2b95f9de79181805df90bedc5a5ab4c165e6ec3fe99f970d0e302f384ad222 \
+    --hash=sha256:e59e304978767a54663af13c07b3d1af22ddee3bb2fb0618ca1593e4f593a106 \
+    --hash=sha256:e85e99945e688e32d5a35c1ff38ed0b3f41f43fad8df0bdf79f72b2ba7bc5272 \
+    --hash=sha256:ece47d672db52ac607a3d9599a9d48dcb2f2f735c6c2d1f34130085bb12b112a \
+    --hash=sha256:f4039b9cbc3048b2416cc57ab3bda989a6fcf9b36cf8937f01a6e731b64f80d7
+    # via
+    #   pytest
+    #   sphinx
+typing-extensions==4.13.0 ; python_full_version < '3.13' \
+    --hash=sha256:0a4ac55a5820789d87e297727d229866c9650f6521b64206413c4fbada24d95b \
+    --hash=sha256:c8dd92cc0d6425a97c18fbb9d1954e5ff92c1ca881a309c45f06ebc0b79058e5
+    # via
+    #   anyio
+    #   uvicorn
+urllib3==2.3.0 \
+    --hash=sha256:1cee9ad369867bfdbbb48b7dd50374c0967a0bb7710050facf0dd6911440e3df \
+    --hash=sha256:f8c5449b3cf0861679ce7e0503c7b44b5ec981bec0d1d3795a07f1ba96f0204d
+    # via requests
+uvicorn==0.34.0 \
+    --hash=sha256:023dc038422502fa28a09c7a30bf2b6991512da7dcdb8fd35fe57cfc154126f4 \
+    --hash=sha256:404051050cd7e905de2c9a7e61790943440b3416f49cb409f965d9dcd0fa73e9
+    # via sphinx-autobuild
+watchfiles==1.0.4 \
+    --hash=sha256:02a526ee5b5a09e8168314c905fc545c9bc46509896ed282aeb5a8ba9bd6ca27 \
+    --hash=sha256:05d341c71f3d7098920f8551d4df47f7b57ac5b8dad56558064c3431bdfc0b74 \
+    --hash=sha256:076f293100db3b0b634514aa0d294b941daa85fc777f9c698adb1009e5aca0b1 \
+    --hash=sha256:0799ae68dfa95136dde7c472525700bd48777875a4abb2ee454e3ab18e9fc712 \
+    --hash=sha256:0986902677a1a5e6212d0c49b319aad9cc48da4bd967f86a11bde96ad9676ca1 \
+    --hash=sha256:0bc80d91ddaf95f70258cf78c471246846c1986bcc5fd33ccc4a1a67fcb40f9a \
+    --hash=sha256:13c2ce7b72026cfbca120d652f02c7750f33b4c9395d79c9790b27f014c8a5a2 \
+    --hash=sha256:1941b4e39de9b38b868a69b911df5e89dc43767feeda667b40ae032522b9b5f1 \
+    --hash=sha256:1eacd91daeb5158c598fe22d7ce66d60878b6294a86477a4715154990394c9b3 \
+    --hash=sha256:229e6ec880eca20e0ba2f7e2249c85bae1999d330161f45c78d160832e026ee2 \
+    --hash=sha256:22bb55a7c9e564e763ea06c7acea24fc5d2ee5dfc5dafc5cfbedfe58505e9f90 \
+    --hash=sha256:278aaa395f405972e9f523bd786ed59dfb61e4b827856be46a42130605fd0899 \
+    --hash=sha256:2a9f93f8439639dc244c4d2902abe35b0279102bca7bbcf119af964f51d53c19 \
+    --hash=sha256:308ac265c56f936636e3b0e3f59e059a40003c655228c131e1ad439957592303 \
+    --hash=sha256:31f1a379c9dcbb3f09cf6be1b7e83b67c0e9faabed0471556d9438a4a4e14202 \
+    --hash=sha256:32b026a6ab64245b584acf4931fe21842374da82372d5c039cba6bf99ef722f3 \
+    --hash=sha256:342622287b5604ddf0ed2d085f3a589099c9ae8b7331df3ae9845571586c4f3d \
+    --hash=sha256:39f4914548b818540ef21fd22447a63e7be6e24b43a70f7642d21f1e73371590 \
+    --hash=sha256:3f68d8e9d5a321163ddacebe97091000955a1b74cd43724e346056030b0bacee \
+    --hash=sha256:43b168bba889886b62edb0397cab5b6490ffb656ee2fcb22dec8bfeb371a9e12 \
+    --hash=sha256:47eb32ef8c729dbc4f4273baece89398a4d4b5d21a1493efea77a17059f4df8a \
+    --hash=sha256:4810ea2ae622add560f4aa50c92fef975e475f7ac4900ce5ff5547b2434642d8 \
+    --hash=sha256:4e997802d78cdb02623b5941830ab06f8860038faf344f0d288d325cc9c5d2ff \
+    --hash=sha256:4ebbeca9360c830766b9f0df3640b791be569d988f4be6c06d6fae41f187f105 \
+    --hash=sha256:4f8c4998506241dedf59613082d1c18b836e26ef2a4caecad0ec41e2a15e4226 \
+    --hash=sha256:55ccfd27c497b228581e2838d4386301227fc0cb47f5a12923ec2fe4f97b95af \
+    --hash=sha256:5717021b199e8353782dce03bd8a8f64438832b84e2885c4a645f9723bf656d9 \
+    --hash=sha256:5c11ea22304d17d4385067588123658e9f23159225a27b983f343fcffc3e796a \
+    --hash=sha256:5e0227b8ed9074c6172cf55d85b5670199c99ab11fd27d2c473aa30aec67ee42 \
+    --hash=sha256:62c9953cf85529c05b24705639ffa390f78c26449e15ec34d5339e8108c7c407 \
+    --hash=sha256:6ba473efd11062d73e4f00c2b730255f9c1bdd73cd5f9fe5b5da8dbd4a717205 \
+    --hash=sha256:740d103cd01458f22462dedeb5a3382b7f2c57d07ff033fbc9465919e5e1d0f3 \
+    --hash=sha256:74cb3ca19a740be4caa18f238298b9d472c850f7b2ed89f396c00a4c97e2d9ff \
+    --hash=sha256:7b75fee5a16826cf5c46fe1c63116e4a156924d668c38b013e6276f2582230f0 \
+    --hash=sha256:7cf684aa9bba4cd95ecb62c822a56de54e3ae0598c1a7f2065d51e24637a3c5d \
+    --hash=sha256:8012bd820c380c3d3db8435e8cf7592260257b378b649154a7948a663b5f84e9 \
+    --hash=sha256:857f5fc3aa027ff5e57047da93f96e908a35fe602d24f5e5d8ce64bf1f2fc733 \
+    --hash=sha256:8b1f135238e75d075359cf506b27bf3f4ca12029c47d3e769d8593a2024ce161 \
+    --hash=sha256:8d0d0630930f5cd5af929040e0778cf676a46775753e442a3f60511f2409f48f \
+    --hash=sha256:90192cdc15ab7254caa7765a98132a5a41471cf739513cc9bcf7d2ffcc0ec7b2 \
+    --hash=sha256:95b42cac65beae3a362629950c444077d1b44f1790ea2772beaea95451c086bb \
+    --hash=sha256:9745a4210b59e218ce64c91deb599ae8775c8a9da4e95fb2ee6fe745fc87d01a \
+    --hash=sha256:9d1ef56b56ed7e8f312c934436dea93bfa3e7368adfcf3df4c0da6d4de959a1e \
+    --hash=sha256:9eea33ad8c418847dd296e61eb683cae1c63329b6d854aefcd412e12d94ee235 \
+    --hash=sha256:9f25d0ba0fe2b6d2c921cf587b2bf4c451860086534f40c384329fb96e2044d1 \
+    --hash=sha256:9fe37a2de80aa785d340f2980276b17ef697ab8db6019b07ee4fd28a8359d2f3 \
+    --hash=sha256:a38320582736922be8c865d46520c043bff350956dfc9fbaee3b2df4e1740a4b \
+    --hash=sha256:a462490e75e466edbb9fc4cd679b62187153b3ba804868452ef0577ec958f5ff \
+    --hash=sha256:a5ae5706058b27c74bac987d615105da17724172d5aaacc6c362a40599b6de43 \
+    --hash=sha256:aa216f87594f951c17511efe5912808dfcc4befa464ab17c98d387830ce07b60 \
+    --hash=sha256:ab0311bb2ffcd9f74b6c9de2dda1612c13c84b996d032cd74799adb656af4e8b \
+    --hash=sha256:ab594e75644421ae0a2484554832ca5895f8cab5ab62de30a1a57db460ce06c6 \
+    --hash=sha256:aee397456a29b492c20fda2d8961e1ffb266223625346ace14e4b6d861ba9c80 \
+    --hash=sha256:b045c800d55bc7e2cadd47f45a97c7b29f70f08a7c2fa13241905010a5493f94 \
+    --hash=sha256:b77d5622ac5cc91d21ae9c2b284b5d5c51085a0bdb7b518dba263d0af006132c \
+    --hash=sha256:ba5bb3073d9db37c64520681dd2650f8bd40902d991e7b4cfaeece3e32561d08 \
+    --hash=sha256:bdef5a1be32d0b07dcea3318a0be95d42c98ece24177820226b56276e06b63b0 \
+    --hash=sha256:c2acfa49dd0ad0bf2a9c0bb9a985af02e89345a7189be1efc6baa085e0f72d7c \
+    --hash=sha256:c7cce76c138a91e720d1df54014a047e680b652336e1b73b8e3ff3158e05061e \
+    --hash=sha256:cc27a65069bcabac4552f34fd2dce923ce3fcde0721a16e4fb1b466d63ec831f \
+    --hash=sha256:cdbd912a61543a36aef85e34f212e5d2486e7c53ebfdb70d1e0b060cc50dd0bf \
+    --hash=sha256:cdcc92daeae268de1acf5b7befcd6cfffd9a047098199056c72e4623f531de18 \
+    --hash=sha256:d3452c1ec703aa1c61e15dfe9d482543e4145e7c45a6b8566978fbb044265a21 \
+    --hash=sha256:d6097538b0ae5c1b88c3b55afa245a66793a8fec7ada6755322e465fb1a0e8cc \
+    --hash=sha256:d8d3d9203705b5797f0af7e7e5baa17c8588030aaadb7f6a86107b7247303817 \
+    --hash=sha256:e0611d244ce94d83f5b9aff441ad196c6e21b55f77f3c47608dcf651efe54c4a \
+    --hash=sha256:f12969a3765909cf5dc1e50b2436eb2c0e676a3c75773ab8cc3aa6175c16e902 \
+    --hash=sha256:f44a39aee3cbb9b825285ff979ab887a25c5d336e5ec3574f1506a4671556a8d \
+    --hash=sha256:f9ce064e81fe79faa925ff03b9f4c1a98b0bbb4a1b8c1b015afa93030cb21a49 \
+    --hash=sha256:fb2c46e275fbb9f0c92e7654b231543c7bbfa1df07cdc4b99fa73bedfde5c844 \
+    --hash=sha256:fc2eb5d14a8e0d5df7b36288979176fbb39672d45184fc4b1c004d7c3ce29317
+    # via sphinx-autobuild
+websockets==15.0.1 \
+    --hash=sha256:0701bc3cfcb9164d04a14b149fd74be7347a530ad3bbf15ab2c678a2cd3dd9a2 \
+    --hash=sha256:0a34631031a8f05657e8e90903e656959234f3a04552259458aac0b0f9ae6fd9 \
+    --hash=sha256:0af68c55afbd5f07986df82831c7bff04846928ea8d1fd7f30052638788bc9b5 \
+    --hash=sha256:0c9e74d766f2818bb95f84c25be4dea09841ac0f734d1966f415e4edfc4ef1c3 \
+    --hash=sha256:0f3c1e2ab208db911594ae5b4f79addeb3501604a165019dd221c0bdcabe4db8 \
+    --hash=sha256:0fdfe3e2a29e4db3659dbd5bbf04560cea53dd9610273917799f1cde46aa725e \
+    --hash=sha256:1009ee0c7739c08a0cd59de430d6de452a55e42d6b522de7aa15e6f67db0b8e1 \
+    --hash=sha256:1234d4ef35db82f5446dca8e35a7da7964d02c127b095e172e54397fb6a6c256 \
+    --hash=sha256:16b6c1b3e57799b9d38427dda63edcbe4926352c47cf88588c0be4ace18dac85 \
+    --hash=sha256:2034693ad3097d5355bfdacfffcbd3ef5694f9718ab7f29c29689a9eae841880 \
+    --hash=sha256:21c1fa28a6a7e3cbdc171c694398b6df4744613ce9b36b1a498e816787e28123 \
+    --hash=sha256:229cf1d3ca6c1804400b0a9790dc66528e08a6a1feec0d5040e8b9eb14422375 \
+    --hash=sha256:27ccee0071a0e75d22cb35849b1db43f2ecd3e161041ac1ee9d2352ddf72f065 \
+    --hash=sha256:363c6f671b761efcb30608d24925a382497c12c506b51661883c3e22337265ed \
+    --hash=sha256:39c1fec2c11dc8d89bba6b2bf1556af381611a173ac2b511cf7231622058af41 \
+    --hash=sha256:3b1ac0d3e594bf121308112697cf4b32be538fb1444468fb0a6ae4feebc83411 \
+    --hash=sha256:3be571a8b5afed347da347bfcf27ba12b069d9d7f42cb8c7028b5e98bbb12597 \
+    --hash=sha256:3c714d2fc58b5ca3e285461a4cc0c9a66bd0e24c5da9911e30158286c9b5be7f \
+    --hash=sha256:3d00075aa65772e7ce9e990cab3ff1de702aa09be3940d1dc88d5abf1ab8a09c \
+    --hash=sha256:3e90baa811a5d73f3ca0bcbf32064d663ed81318ab225ee4f427ad4e26e5aff3 \
+    --hash=sha256:47819cea040f31d670cc8d324bb6435c6f133b8c7a19ec3d61634e62f8d8f9eb \
+    --hash=sha256:47b099e1f4fbc95b701b6e85768e1fcdaf1630f3cbe4765fa216596f12310e2e \
+    --hash=sha256:4a9fac8e469d04ce6c25bb2610dc535235bd4aa14996b4e6dbebf5e007eba5ee \
+    --hash=sha256:4b826973a4a2ae47ba357e4e82fa44a463b8f168e1ca775ac64521442b19e87f \
+    --hash=sha256:4c2529b320eb9e35af0fa3016c187dffb84a3ecc572bcee7c3ce302bfeba52bf \
+    --hash=sha256:54479983bd5fb469c38f2f5c7e3a24f9a4e70594cd68cd1fa6b9340dadaff7cf \
+    --hash=sha256:558d023b3df0bffe50a04e710bc87742de35060580a293c2a984299ed83bc4e4 \
+    --hash=sha256:5756779642579d902eed757b21b0164cd6fe338506a8083eb58af5c372e39d9a \
+    --hash=sha256:592f1a9fe869c778694f0aa806ba0374e97648ab57936f092fd9d87f8bc03665 \
+    --hash=sha256:595b6c3969023ecf9041b2936ac3827e4623bfa3ccf007575f04c5a6aa318c22 \
+    --hash=sha256:5a939de6b7b4e18ca683218320fc67ea886038265fd1ed30173f5ce3f8e85675 \
+    --hash=sha256:5d54b09eba2bada6011aea5375542a157637b91029687eb4fdb2dab11059c1b4 \
+    --hash=sha256:5df592cd503496351d6dc14f7cdad49f268d8e618f80dce0cd5a36b93c3fc08d \
+    --hash=sha256:5f4c04ead5aed67c8a1a20491d54cdfba5884507a48dd798ecaf13c74c4489f5 \
+    --hash=sha256:64dee438fed052b52e4f98f76c5790513235efaa1ef7f3f2192c392cd7c91b65 \
+    --hash=sha256:66dd88c918e3287efc22409d426c8f729688d89a0c587c88971a0faa2c2f3792 \
+    --hash=sha256:678999709e68425ae2593acf2e3ebcbcf2e69885a5ee78f9eb80e6e371f1bf57 \
+    --hash=sha256:67f2b6de947f8c757db2db9c71527933ad0019737ec374a8a6be9a956786aaf9 \
+    --hash=sha256:693f0192126df6c2327cce3baa7c06f2a117575e32ab2308f7f8216c29d9e2e3 \
+    --hash=sha256:746ee8dba912cd6fc889a8147168991d50ed70447bf18bcda7039f7d2e3d9151 \
+    --hash=sha256:756c56e867a90fb00177d530dca4b097dd753cde348448a1012ed6c5131f8b7d \
+    --hash=sha256:76d1f20b1c7a2fa82367e04982e708723ba0e7b8d43aa643d3dcd404d74f1475 \
+    --hash=sha256:7f493881579c90fc262d9cdbaa05a6b54b3811c2f300766748db79f098db9940 \
+    --hash=sha256:823c248b690b2fd9303ba00c4f66cd5e2d8c3ba4aa968b2779be9532a4dad431 \
+    --hash=sha256:82544de02076bafba038ce055ee6412d68da13ab47f0c60cab827346de828dee \
+    --hash=sha256:8dd8327c795b3e3f219760fa603dcae1dcc148172290a8ab15158cf85a953413 \
+    --hash=sha256:8fdc51055e6ff4adeb88d58a11042ec9a5eae317a0a53d12c062c8a8865909e8 \
+    --hash=sha256:a625e06551975f4b7ea7102bc43895b90742746797e2e14b70ed61c43a90f09b \
+    --hash=sha256:abdc0c6c8c648b4805c5eacd131910d2a7f6455dfd3becab248ef108e89ab16a \
+    --hash=sha256:ac017dd64572e5c3bd01939121e4d16cf30e5d7e110a119399cf3133b63ad054 \
+    --hash=sha256:ac1e5c9054fe23226fb11e05a6e630837f074174c4c2f0fe442996112a6de4fb \
+    --hash=sha256:ac60e3b188ec7574cb761b08d50fcedf9d77f1530352db4eef1707fe9dee7205 \
+    --hash=sha256:b359ed09954d7c18bbc1680f380c7301f92c60bf924171629c5db97febb12f04 \
+    --hash=sha256:b7643a03db5c95c799b89b31c036d5f27eeb4d259c798e878d6937d71832b1e4 \
+    --hash=sha256:ba9e56e8ceeeedb2e080147ba85ffcd5cd0711b89576b83784d8605a7df455fa \
+    --hash=sha256:c338ffa0520bdb12fbc527265235639fb76e7bc7faafbb93f6ba80d9c06578a9 \
+    --hash=sha256:cad21560da69f4ce7658ca2cb83138fb4cf695a2ba3e475e0559e05991aa8122 \
+    --hash=sha256:d08eb4c2b7d6c41da6ca0600c077e93f5adcfd979cd777d747e9ee624556da4b \
+    --hash=sha256:d50fd1ee42388dcfb2b3676132c78116490976f1300da28eb629272d5d93e905 \
+    --hash=sha256:d591f8de75824cbb7acad4e05d2d710484f15f29d4a915092675ad3456f11770 \
+    --hash=sha256:d5f6b181bb38171a8ad1d6aa58a67a6aa9d4b38d0f8c5f496b9e42561dfc62fe \
+    --hash=sha256:d63efaa0cd96cf0c5fe4d581521d9fa87744540d4bc999ae6e08595a1014b45b \
+    --hash=sha256:d99e5546bf73dbad5bf3547174cd6cb8ba7273062a23808ffea025ecb1cf8562 \
+    --hash=sha256:e09473f095a819042ecb2ab9465aee615bd9c2028e4ef7d933600a8401c79561 \
+    --hash=sha256:e8b56bdcdb4505c8078cb6c7157d9811a85790f2f2b3632c7d1462ab5783d215 \
+    --hash=sha256:ee443ef070bb3b6ed74514f5efaa37a252af57c90eb33b956d35c8e9c10a1931 \
+    --hash=sha256:f29d80eb9a9263b8d109135351caf568cc3f80b9928bccde535c235de55c22d9 \
+    --hash=sha256:f7a866fbc1e97b5c617ee4116daaa09b722101d4a3c170c787450ba409f9736f \
+    --hash=sha256:fcd5cf9e305d7b8338754470cf69cf81f420459dbae8a3b40cee57417f4614a7
+    # via sphinx-autobuild
+wheel==0.45.1 \
+    --hash=sha256:661e1abd9198507b1409a20c02106d9670b2576e916d58f520316666abca6729 \
+    --hash=sha256:708e7481cc80179af0e556bbf0cc00b8444c7321e2700b8d8580231d13017248
+    # via sphinx-togglebutton
diff --git a/doc/safety/safety_overview.rst b/doc/safety/safety_overview.rst
index d3e907f340d..16106582a39 100644
--- a/doc/safety/safety_overview.rst
+++ b/doc/safety/safety_overview.rst
@@ -147,6 +147,46 @@ system.
 Also the **IEC 61508 standard** sets a pre-condition and recommendation towards the use of coding
 standards / guidelines to reduce likelihood of errors.
 
+The project TSC and the Safety Committee of the project agreed to implement
+a staged and incremental approach for complying with a set of coding rules (AKA
+Coding Guidelines) to improve quality and consistency of the code base. Below
+are the agreed upon stages:
+
+Stage I (COMPLETED)
+  Coding guideline rules are available to be followed and referenced,
+  but not enforced. Rules are not yet enforced in CI and pull-requests cannot be
+  blocked by reviewers/approvers due to violations.
+
+Stage II
+  Reviewers/approvers can block pull-requests due to violations of the coding guidelines
+  in pull-requests across the codebase.
+
+  Begin enforcement on a limited scope of the code base. Initially, this would be
+  the safety certification scope. For rules easily applied across codebase, we
+  should not limit compliance to initial scope. This step requires tooling,
+  CI setup and an enforcement strategy.
+
+Stage III
+  Revisit the coding guideline rules and based on experience from previous
+  stages, refine/iterate on selected rules.
+
+Stage IV
+   Expand enforcement to the wider codebase. Exceptions may be granted on some
+   areas of the codebase with a proper justification. Exception would require
+   TSC approval.
+
+.. note::
+
+    Coding guideline rules may be removed/changed at any time by filing a
+    GH issue/RFC.
+
+.. important::
+
+    **Current stage:**
+    The prerequisites to complete **Stage II** are currently being looked at:
+    The tooling is in evaluation, CI setup and `enforcement strategy
+    <https://github.com/zephyrproject-rtos/zephyr/issues/58903>`__ is being worked on.
+
 Requirements and requirements tracing
 -------------------------------------
 
diff --git a/doc/security/secure-coding.rst b/doc/security/secure-coding.rst
index 579622999b4..e9c9c8340e2 100644
--- a/doc/security/secure-coding.rst
+++ b/doc/security/secure-coding.rst
@@ -176,10 +176,10 @@ including the 8 principles from [SALT75]_:
 - limited attack surface (the set of the
   different points where an attacker can try to enter or extract data)
 
-- input validation with whitelists (inputs should typically be checked
+- input validation with allowlists (inputs should typically be checked
   to determine if they are valid before they are accepted; this
-  validation should use whitelists (which only accept known-good
-  values), not blacklists (which attempt to list known-bad values)).
+  validation should use allowlists (which only accept known-good
+  values), not blocklists (which attempt to list known-bad values)).
 
 Vulnerability Knowledge
 =======================
diff --git a/doc/security/vulnerabilities.rst b/doc/security/vulnerabilities.rst
index 0d75d120aa7..68c2f7ff634 100644
--- a/doc/security/vulnerabilities.rst
+++ b/doc/security/vulnerabilities.rst
@@ -1599,8 +1599,8 @@ This has been fixed in main for v3.6.0
 :cve:`2024-3077`
 ----------------
 
-Bluetooth: Integer underflow in gatt_find_info_rsp. A malicious BLE
-device can crash BLE victim device by sending malformed gatt packet.
+Bluetooth: Integer underflow in gatt_find_info_rsp. A malicious Bluetooth LE
+device can crash Bluetooth LE victim device by sending malformed gatt packet.
 
 - `Zephyr project bug tracker GHSA-gmfv-4vfh-2mh8
   <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-gmfv-4vfh-2mh8>`_
@@ -1615,8 +1615,8 @@ This has been fixed in main for v3.7.0
 
 Bluetooth: DoS caused by null pointer dereference.
 
-A malicious BLE device can send a specific order of packet
-sequence to cause a DoS attack on the victim BLE device.
+A malicious Bluetooth LE device can send a specific order of packet
+sequence to cause a DoS attack on the victim Bluetooth LE device.
 
 - `Zephyr project bug tracker GHSA-jmr9-xw2v-5vf4
   <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-jmr9-xw2v-5vf4>`_
@@ -1804,7 +1804,20 @@ This has been fixed in main for v4.0.0
 :cve:`2024-10395`
 -----------------
 
-Under embargo until 2025-01-23
+net: lib: http_server: Buffer Under-read
+
+No proper validation of the length of user input in
+http_server_get_content_type_from_extension could cause a
+segmentation fault or crash by causing memory to be read
+outside of the bounds of the buffer.
+
+- `Zephyr project bug tracker GHSA-hfww-j92m-x8fv
+  <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-hfww-j92m-x8fv>`_
+
+This has been fixed in main for v4.0.0
+
+- `PR 80396 fix for main
+  <https://github.com/zephyrproject-rtos/zephyr/pull/80396>`_
 
 :cve:`2024-11263`
 -----------------
@@ -1824,3 +1837,75 @@ This has been fixed in main for v4.0.0
 
 - `PR 81370 fix for 3.7
   <https://github.com/zephyrproject-rtos/zephyr/pull/81370>`_
+
+:cve:`2025-1673`
+----------------
+
+Out of bounds read when calling crc16_ansi and strlen in dns_validate_msg
+
+A malicious or malformed DNS packet without a payload can cause an out-of-bounds
+read, resulting in a crash (denial of service) or an incorrect computation.
+
+- `Zephyr project bug tracker GHSA-jjhx-rrh4-j8mx
+  <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-jjhx-rrh4-j8mx>`_
+
+This has been fixed in main for v4.1.0
+
+- `PR 82072 fix for main
+  <https://github.com/zephyrproject-rtos/zephyr/pull/82072>`_
+
+- `PR 82289 fix for 4.0
+  <https://github.com/zephyrproject-rtos/zephyr/pull/82289>`_
+
+- `PR 82288 fix for 3.7
+  <https://github.com/zephyrproject-rtos/zephyr/pull/82288>`_
+
+:cve:`2025-1674`
+----------------
+
+Out of bounds read when unpacking DNS answers
+
+A lack of input validation allows for out of bounds reads caused by malicious or
+malformed packets.
+
+- `Zephyr project bug tracker GHSA-x975-8pgf-qh66
+  <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-x975-8pgf-qh66>`_
+
+This has been fixed in main for v4.1.0
+
+- `PR 82072 fix for main
+  <https://github.com/zephyrproject-rtos/zephyr/pull/82072>`_
+
+- `PR 82289 fix for 4.0
+  <https://github.com/zephyrproject-rtos/zephyr/pull/82289>`_
+
+- `PR 82288 fix for 3.7
+  <https://github.com/zephyrproject-rtos/zephyr/pull/82288>`_
+
+:cve:`2025-1675`
+----------------
+
+Out of bounds read in dns_copy_qname
+
+The function dns_copy_qname in dns_pack.c performs performs a memcpy operation
+with an untrusted field and does not check if the source buffer is large enough
+to contain the copied data.
+
+- `Zephyr project bug tracker GHSA-2m84-5hfw-m8v4
+  <https://github.com/zephyrproject-rtos/zephyr/security/advisories/GHSA-2m84-5hfw-m8v4>`_
+
+This has been fixed in main for v4.1.0
+
+- `PR 82072 fix for main
+  <https://github.com/zephyrproject-rtos/zephyr/pull/82072>`_
+
+- `PR 82289 fix for 4.0
+  <https://github.com/zephyrproject-rtos/zephyr/pull/82289>`_
+
+- `PR 82288 fix for 3.7
+  <https://github.com/zephyrproject-rtos/zephyr/pull/82288>`_
+
+:cve:`2025-2962`
+----------------
+
+Under embargo until 2025-06-07
diff --git a/doc/services/debugging/cpu_load.rst b/doc/services/debugging/cpu_load.rst
new file mode 100644
index 00000000000..07b7cc755b6
--- /dev/null
+++ b/doc/services/debugging/cpu_load.rst
@@ -0,0 +1,26 @@
+.. _cpu_load:
+
+CPU load
+########
+
+Module can be used to track how much time is spent in idle. It is using tracing hooks
+which are called before and after CPU goes to idle. Compared to :ref:`thread_analyzer`
+it is more accurate since it takes into account time spent in the interrupt context as well.
+
+Function :c:func:`cpu_load_get` is used to get the latest value. It is also used to reset
+the measurement. By default, module is using :c:func:`k_cycle_get_32` but in cases when higher
+precision is needed a :ref:`counter_api` device can be used.
+
+Load can also be reported periodically using a logging message. Period is configured using :kconfig:option:`CONFIG_CPU_LOAD_LOG_PERIODICALLY`.
+
+Using counter device
+********************
+
+In order to use :ref:`counter_api` device :kconfig:option:`CONFIG_CPU_LOAD_USE_COUNTER` must be
+enabled and chosen in devicetree must be set.
+
+.. code-block:: devicetree
+
+   chosen {
+     zephyr,cpu-load-counter = &counter_device;
+   };
diff --git a/doc/services/debugging/index.rst b/doc/services/debugging/index.rst
index 1a1e4f91893..36864412d34 100644
--- a/doc/services/debugging/index.rst
+++ b/doc/services/debugging/index.rst
@@ -7,6 +7,7 @@ Debugging
    :maxdepth: 1
 
    thread-analyzer.rst
+   cpu_load.rst
    coredump.rst
    gdbstub.rst
    debugmon.rst
diff --git a/doc/services/device_mgmt/index.rst b/doc/services/device_mgmt/index.rst
index 1063743e87a..09d5aeb4da9 100644
--- a/doc/services/device_mgmt/index.rst
+++ b/doc/services/device_mgmt/index.rst
@@ -15,18 +15,3 @@ Device Management
     dfu.rst
     ota.rst
     ec_host_cmd.rst
-
-SMP Groups
-==========
-
-.. toctree::
-    :maxdepth: 1
-
-    smp_groups/smp_group_0.rst
-    smp_groups/smp_group_1.rst
-    smp_groups/smp_group_2.rst
-    smp_groups/smp_group_3.rst
-    smp_groups/smp_group_8.rst
-    smp_groups/smp_group_9.rst
-    smp_groups/smp_group_10.rst
-    smp_groups/smp_group_63.rst
diff --git a/doc/services/device_mgmt/mcumgr.rst b/doc/services/device_mgmt/mcumgr.rst
index b554d6777f1..aa3ebb403bb 100644
--- a/doc/services/device_mgmt/mcumgr.rst
+++ b/doc/services/device_mgmt/mcumgr.rst
@@ -19,7 +19,7 @@ The following management operations are available:
 
 over the following transports:
 
-* BLE (Bluetooth Low Energy)
+* Bluetooth Low Energy (LE)
 * Serial (UART)
 * UDP over IP
 
@@ -32,7 +32,7 @@ The management subsystem is located in :zephyr_file:`subsys/mgmt/` inside of
 the Zephyr tree.
 
 Additionally, there is a :zephyr:code-sample:`sample <smp-svr>` server that provides
-management functionality over BLE and serial.
+management functionality over Bluetooth LE and serial.
 
 .. _mcumgr_tools_libraries:
 
@@ -136,7 +136,7 @@ On boards where a J-Link OB is present which has both CDC and MSC (virtual Mass
 Storage Device, also known as drag-and-drop) support, the MSD functionality can
 prevent MCUmgr commands over the CDC UART port from working due to how USB
 endpoints are configured in the J-Link firmware (for example on the
-:ref:`Nordic nrf52840dk/nrf52840 board <nrf52840dk_nrf52840>`) because of
+:zephyr:board:`nrf52840dk` board) because of
 limiting the maximum packet size (most likely to occur when using image
 management commands for updating firmware). This issue can be
 resolved by disabling MSD functionality on the J-Link device, follow the
diff --git a/doc/services/device_mgmt/ota.rst b/doc/services/device_mgmt/ota.rst
index 4548ce8b028..911be1d1ba7 100644
--- a/doc/services/device_mgmt/ota.rst
+++ b/doc/services/device_mgmt/ota.rst
@@ -62,7 +62,7 @@ SMP Server
 ==========
 
 A Simple Management Protocol (SMP) server can be used to update firmware via
-Bluetooth Low Energy (BLE) or UDP. :ref:`mcu_mgr` is used to send a signed
+Bluetooth Low Energy (LE) or UDP. :ref:`mcu_mgr` is used to send a signed
 firmware binary to the remote device where it is verified by MCUboot before the
 upgrade occurs.
 
diff --git a/doc/services/device_mgmt/smp_groups/smp_group_1.rst b/doc/services/device_mgmt/smp_groups/smp_group_1.rst
index 5651e126c35..a7ff01807cc 100644
--- a/doc/services/device_mgmt/smp_groups/smp_group_1.rst
+++ b/doc/services/device_mgmt/smp_groups/smp_group_1.rst
@@ -519,6 +519,8 @@ where:
     :c:enumerator:`MGMT_ERR_EBADSTATE`, which means that the secondary
     image has been marked for next boot already and may not be erased.
 
+.. _mcumgr_smp_group_1_slot_info:
+
 Slot info
 *********
 
diff --git a/doc/services/device_mgmt/smp_protocol.rst b/doc/services/device_mgmt/smp_protocol.rst
index 1ad4634d6e7..fd9d5579673 100644
--- a/doc/services/device_mgmt/smp_protocol.rst
+++ b/doc/services/device_mgmt/smp_protocol.rst
@@ -220,3 +220,5 @@ Specifications of management groups supported by Zephyr
     smp_groups/smp_group_3.rst
     smp_groups/smp_group_8.rst
     smp_groups/smp_group_9.rst
+    smp_groups/smp_group_10.rst
+    smp_groups/smp_group_63.rst
diff --git a/doc/services/device_mgmt/smp_transport.rst b/doc/services/device_mgmt/smp_transport.rst
index 644ef7c484e..a6a00fed9f3 100644
--- a/doc/services/device_mgmt/smp_transport.rst
+++ b/doc/services/device_mgmt/smp_transport.rst
@@ -8,10 +8,10 @@ side SMP transports.
 
 .. _mcumgr_smp_transport_ble:
 
-BLE (Bluetooth Low Energy)
-**************************
+Bluetooth Low Energy (LE)
+*************************
 
-MCUmgr Clients need to use following BLE Characteristics, when implementing
+MCUmgr Clients need to use following Bluetooth Characteristics, when implementing
 SMP client:
 
 - **Service UUID**: ``8D53DC1D-1DB7-4CD3-868B-8A527460AA84``
diff --git a/doc/services/file_system/index.rst b/doc/services/file_system/index.rst
index 3c038847916..b04cb950ff6 100644
--- a/doc/services/file_system/index.rst
+++ b/doc/services/file_system/index.rst
@@ -51,11 +51,11 @@ Samples for the VFS are mainly supplied in ``samples/subsys/fs``, although vario
 VFS usage are provided as important functionalities in samples for different subsystems.
 Here is the list of samples worth looking at:
 
-- ``samples/subsys/fs/fat_fs`` is an example of FAT file system usage with SDHC media;
-- ``samples/subsys/shell/fs`` is an example of Shell fs subsystem, using internal flash partition
-	formatted to LittleFS;
-- ``samples/subsys/usb/mass/`` example of USB Mass Storage device that uses FAT FS driver with RAM
-	or SPI connected FLASH, or LittleFS in flash, depending on the sample configuration.
+- :zephyr:code-sample:`fs` is an example of FAT file system usage with SDHC media;
+- :zephyr:code-sample:`shell-fs` is an example of Shell fs subsystem, using internal flash partition
+  formatted to LittleFS;
+- :zephyr:code-sample:`usb-mass` example of USB Mass Storage device that uses FAT FS driver with RAM
+  or SPI connected FLASH, or LittleFS in flash, depending on the sample configuration.
 
 API Reference
 *************
diff --git a/doc/services/index.rst b/doc/services/index.rst
index d1c456151a2..69050cb784f 100644
--- a/doc/services/index.rst
+++ b/doc/services/index.rst
@@ -29,10 +29,8 @@ OS Services
    portability/index.rst
    poweroff.rst
    profiling/index.rst
-   secure_storage.rst
    shell/index.rst
    serialization/index.rst
-   settings/index.rst
    smf/index.rst
    storage/index.rst
    sensing/index.rst
diff --git a/doc/services/input/index.rst b/doc/services/input/index.rst
index e2e28430185..1145b64a8e8 100644
--- a/doc/services/input/index.rst
+++ b/doc/services/input/index.rst
@@ -63,29 +63,6 @@ this purpose, the :c:func:`input_to_hid_code` and
 :c:func:`input_to_hid_modifier` functions can be used to map input codes to HID
 codes and modifiers.
 
-Kscan Compatibility
-*******************
-
-Input devices generating X/Y/Touch events can be used in existing applications
-based on the :ref:`kscan_api` API by enabling both
-:kconfig:option:`CONFIG_INPUT` and :kconfig:option:`CONFIG_KSCAN`, defining a
-:dtcompatible:`zephyr,kscan-input` node as a child node of the corresponding
-input device and pointing the ``zephyr,keyboard-scan`` chosen node to the
-compatibility device node, for example:
-
-.. code-block:: devicetree
-
-    chosen {
-        zephyr,keyboard-scan = &kscan_input;
-    };
-
-    ft5336@38 {
-        ...
-        kscan_input: kscan-input {
-            compatible = "zephyr,kscan-input";
-        };
-    };
-
 General Purpose Drivers
 ***********************
 
diff --git a/doc/services/ipc/ipc_service/backends/ipc_service_icmsg.rst b/doc/services/ipc/ipc_service/backends/ipc_service_icmsg.rst
index 251a332027a..369929a876f 100644
--- a/doc/services/ipc/ipc_service/backends/ipc_service_icmsg.rst
+++ b/doc/services/ipc/ipc_service/backends/ipc_service_icmsg.rst
@@ -83,8 +83,7 @@ connected through the IPC instance:
    memory.
 #. It then sends a signal to the other domain or CPU, informing that the data
    has been written. Sending the signal to the other domain or CPU is repeated
-   with timeout specified by
-   :kconfig:option:`CONFIG_IPC_SERVICE_ICMSG_BOND_NOTIFY_REPEAT_TO_MS` option.
+   with timeout.
 #. When the signal from the other domain or CPU is received, the magic number
    is read from ``rx-region``. If it is correct, the bonding process is finished
    and the backend informs the application by calling
diff --git a/doc/services/llext/api.rst b/doc/services/llext/api.rst
index b3d8d64152b..c4227ca2d8a 100644
--- a/doc/services/llext/api.rst
+++ b/doc/services/llext/api.rst
@@ -6,3 +6,5 @@ API Reference
 .. doxygengroup:: llext_symbols
 
 .. doxygengroup:: llext_loader_apis
+
+.. doxygengroup:: llext_inspect_apis
diff --git a/doc/services/llext/build.rst b/doc/services/llext/build.rst
index eae96259d24..6eb8da9dc71 100644
--- a/doc/services/llext/build.rst
+++ b/doc/services/llext/build.rst
@@ -152,15 +152,34 @@ directory. It's a tarball that contains the headers and compile flags needed
 to build extensions. The extension developer can then include the headers
 and use the compile flags in their build system to build the extension.
 
+EDK definition files
+--------------------
+
+The EDK includes several convenience files which define a set of variables that
+contain the compile flags needed by the project, as well as other build-related
+information, when enabled. The information is currently exported in the
+following formats:
+
+- ``Makefile.cflags``, for Makefile-based projects;
+- ``cmake.cflags``, for CMake-based projects.
+
+Paths to the headers and flags are prefixed by the EDK root directory. This is
+automatically obtained for CMake projects from ``CMAKE_CURRENT_LIST_DIR``;
+other formats refer to an ``LLEXT_EDK_INSTALL_DIR`` variable, which must be set
+by the user with the path where the EDK is installed before including the
+generated file.
+
+.. note::
+   The ``LLEXT_EDK`` prefix in the variable name may be changed with the
+   :kconfig:option:`CONFIG_LLEXT_EDK_NAME` option.
+
 Compile flags
 -------------
 
-The EDK includes the convenience files ``cmake.cflags`` (for CMake-based
-projects) and ``Makefile.cflags`` (for Make-based ones), which define a set of
-variables that contain the compile flags needed by the project. The full list
-of flags needed to build an extension is provided by ``LLEXT_CFLAGS``. Also
-provided is a more granular set of flags that can be used in support of
-different use cases, such as when building mocks for unit tests:
+The full list of flags needed to build an extension is provided by
+``LLEXT_CFLAGS``. Also provided is a more granular set of flags that can be
+used in support of different use cases, such as when building mocks for unit
+tests:
 
 ``LLEXT_INCLUDE_CFLAGS``
 
@@ -194,6 +213,29 @@ different use cases, such as when building mocks for unit tests:
         ``LLEXT_ALL_INCLUDE_CFLAGS``, ``LLEXT_GENERATED_IMACROS_CFLAGS`` and
         ``LLEXT_BASE_CFLAGS``.
 
+Target information
+------------------
+
+The EDK includes information that identifies the target of the current Zephyr
+build. The following variables are currently defined and mirror the information
+available in the Zephyr build system:
+
+``LLEXT_EDK_BOARD_NAME``
+    The board name used in the Zephyr build.
+
+``LLEXT_EDK_BOARD_QUALIFIERS``
+    The board qualifiers, if provided, used in the Zephyr build.
+
+``LLEXT_EDK_BOARD_REVISION``
+    The board revision, if provided, used in the Zephyr build.
+
+``LLEXT_EDK_BOARD_TARGET``
+    The fully qualified board target used in the Zephyr build.
+
+.. note::
+   The ``LLEXT_EDK`` prefix in the variable names may be changed with the
+   :kconfig:option:`CONFIG_LLEXT_EDK_NAME` option.
+
 .. _llext_kconfig_edk:
 
 LLEXT EDK Kconfig options
@@ -202,7 +244,8 @@ LLEXT EDK Kconfig options
 The LLEXT EDK can be configured using the following Kconfig options:
 
 :kconfig:option:`CONFIG_LLEXT_EDK_NAME`
-    The name of the generated EDK tarball.
+    The name of the generated EDK tarball. This is also used as the prefix for
+    several variables defined in the EDK files.
 
 :kconfig:option:`CONFIG_LLEXT_EDK_USERSPACE_ONLY`
     If set, the EDK will include headers that do not contain code to route
diff --git a/doc/services/llext/debug.rst b/doc/services/llext/debug.rst
new file mode 100644
index 00000000000..2389c078dc9
--- /dev/null
+++ b/doc/services/llext/debug.rst
@@ -0,0 +1,359 @@
+.. _llext_debug:
+
+Debugging extensions
+####################
+
+Debugging extensions is a complex task. Since the extension code is by
+definition not built with the Zephyr application, the final Zephyr ELF file
+does not contain the symbols for extension code. Furthermore, the extension is
+dynamically relocated by :c:func:`llext_load` at runtime, so even if the
+symbols were available, it would be impossible for the debugger to know the
+final locations of the symbols in the extension code.
+
+Setting up the debugger session properly in this case requires a few manual
+steps. The following sections will provide some tips on how to do it with the
+Zephyr SDK and the debug features provided by ``west``, but the instructions
+can be adapted to any GDB-based debugging environment.
+
+Extension debugging process
+===========================
+
+1. Make sure the project is set up to display the verbose LLEXT debug output
+   (:kconfig:option:`CONFIG_LOG` and :kconfig:option:`CONFIG_LLEXT_LOG_LEVEL_DBG`
+   are set).
+
+2. Build the Zephyr application and the extensions.
+
+   For each target ``name`` included in the current build, two files will be
+   generated into the ``llext`` subdirectory of the build root:
+
+   ``name_ext_debug.elf``
+
+        An intermediate ELF file with full debugging information.
+
+   ``name.llext``
+
+        The final extension binary, stripped to the essential data required for
+        loading into the Zephyr application.
+
+   Other files may be present, depending on the target architecture and the
+   build configuration.
+
+3. Start a debugging session of the main Zephyr application. This is described
+   in the :ref:`Debugging <west-debugging>` section of the documentation; on
+   supported boards it is as easy as running ``west debug``, perhaps with some
+   additional arguments.
+
+4. Set a breakpoint just after the :c:func:`llext_load` function in your code
+   and let it run. This will load the extension into memory and relocate it.
+   The output logs will contain a line with ``gdb add-symbol-file flags:``,
+   followed by lines all starting with ``-s``.
+
+5. Type this command in the GDB console to load this extension's symbols:
+
+   .. code-block::
+
+      add-symbol-file <path-to-debug.elf> <load-addresses>
+
+   where ``<path-to-debug.elf>`` is the full path of the ELF file with debug
+   information identified in step 2, and ``<load-addresses>`` is a space
+   separated list of all the ``-s`` lines collected from the log in the
+   previous step.
+
+6. The extension symbols are now available to the debugger. You can set
+   breakpoints, inspect variables, and step through the code as usual.
+
+Steps 4-6 can be repeated for every extension that is loaded by the
+application, if there are several.
+
+Symbol lookup issues
+====================
+
+.. warning::
+
+   It is almost certain that the loaded symbols will be shadowed by others in
+   the main application; for example, they may be located inside the memory
+   area of the ELF buffer or the LLEXT heap.
+
+   In this case GDB chooses the first known symbol and therefore associates the
+   addresses to some ``elf_buffer+0x123`` instead of an expected ``ext_fn``.
+   This further confuses its high-level operations like source stepping or
+   inspecting locals, since they are meaningless in that context.
+
+Two possible solutions to this problem are discussed in the following
+paragraphs.
+
+Discard all Zephyr symbols
+--------------------------
+
+The simplest option is to drop all the Zephyr application symbols from GDB by
+invoking ``add-symbol-file`` with no arguments, before step 5. This will
+however focus the debugging session to the llext only, as all information about
+the Zephyr application will be lost. For example, the debugger may not be able to
+properly follow stack traces outside the extension code.
+
+It is possible to use the same technique multiple times in the same session to
+switch between the main and extension symbol tables as required, but it rapidly
+becomes cumbersome.
+
+Edit the ELF file
+-----------------
+
+This alternative is more complex but allows for a more seamless debugging
+experience. The idea is to edit the main Zephyr ELF file to remove information
+about the symbols that overlap with the extension that is to be debugged, so
+that when the extension symbols are loaded, GDB will not have any ambiguity.
+This can be done by using ``objcopy`` with the ``-N <symbol>`` option.
+
+Identifying the offending symbols is however an iterative trial-and-error
+procedure, as there can be many different layers; for example, the ELF buffer
+may be itself contained in a symbol for the data segment. Fortunately, this
+knowledge can then be used several times as the list is unlikely to change for
+a given project.
+
+Example debugging session
+=========================
+
+This example demonstrates how to debug the ``detached_fn`` extension in the
+``tests/subsys/llext`` project (specifically, the ``writable`` case), on an
+emulated ``mps2/an385`` board which is based on an ARM Cortex-M3.
+
+.. note::
+
+   The logs below have been obtained using Zephyr version 4.1 and the Zephyr
+   SDK version 0.17.0. However, the exact addresses may still vary between
+   runs even when using the same versions. Adjust the commands below to
+   match the results of your own session.
+
+The following command will build the project and start the emulator in
+debugging mode:
+
+.. code-block::
+   :caption: Terminal 1 (build, QEMU emulator, GDB server)
+
+   zephyr$ west build -p -b mps2/an385 tests/subsys/llext/ -T llext.writable -t debugserver_qemu
+   -- west build: generating a build system
+   [...]
+   -- west build: running target debugserver_qemu
+   [...]
+   [186/187] To exit from QEMU enter: 'CTRL+a, x'[QEMU] CPU: cortex-m3
+
+On a separate terminal, set ``ZEPHYR_SDK_INSTALL_DIR`` to the directory for the
+Zephyr SDK on your installation, then start the GDB client for the target:
+
+.. code-block::
+   :caption: Terminal 2 (GDB client)
+
+   zephyr$ export LLEXT_SDK_INSTALL_DIR=/opt/zephyr-sdk-0.17.0
+   zephyr$ ${LLEXT_SDK_INSTALL_DIR}/arm-zephyr-eabi/bin/arm-zephyr-eabi-gdb build/zephyr/zephyr.elf
+   GNU gdb (Zephyr SDK 0.17.0) 12.1
+   [...]
+   Reading symbols from build/zephyr/zephyr.elf...
+   (gdb)
+
+Connect, set a breakpoint on the ``llext_load`` function and run until it
+finishes:
+
+.. code-block::
+   :caption: Terminal 2 (GDB client)
+
+   (gdb) target extended-remote :1234
+   Remote debugging using :1234
+   z_arm_reset () at zephyr/arch/arm/core/cortex_m/reset.S:124
+   124         movs.n r0, #_EXC_IRQ_DEFAULT_PRIO
+   (gdb) break llext_load
+   Breakpoint 1 at 0x236c: file zephyr/subsys/llext/llext.c, line 168.
+   (gdb) continue
+   Continuing.
+
+   Breakpoint 1, llext_load (ldr=ldr@entry=0x2000bef0 <ztest_thread_stack+3488>,
+                             name=name@entry=0x9d98 "test_detached",
+                             ext=ext@entry=0x2000abb8 <detached_llext>,
+                             ldr_parm=ldr_parm@entry=0x2000bee8 <ztest_thread_stack+3480>)
+                 at zephyr/subsys/llext/llext.c:168
+   168             *ext = llext_by_name(name);
+   (gdb) finish
+   Run till exit from #0  llext_load ([...])
+       at zephyr/subsys/llext/llext.c:168
+   llext_test_detached () at zephyr/tests/subsys/llext/src/test_llext.c:481
+   481             zassert_ok(res, "load should succeed");
+
+The first terminal will have printed lots of debugging information related to
+the extension loading. Find the section with the addresses:
+
+.. code-block::
+   :caption: Terminal 1 (build, QEMU emulator, GDB server)
+
+   [...]
+   D: Allocate and copy regions...
+   [...]
+   D: gdb add-symbol-file flags:
+   D: -s .text 0x20000034
+   D: -s .data 0x200000b4
+   D: -s .bss 0x2000c2e0
+   D: -s .rodata 0x200000b8
+   D: -s .detach 0x200001d0
+   D: Counting exported symbols...
+   [...]
+
+Use these addresses to load the symbols into GDB:
+
+.. code-block::
+   :caption: Terminal 2 (GDB client)
+
+   (gdb) add-symbol-file build/llext/detached_fn_ext_debug.elf -s .text 0x20000034 -s .data 0x200000b4 -s .bss 0x2000c2e0 -s .rodata 0x200000b8 -s .detach 0x200001d0
+   add symbol table from file "build/llext/detached_fn_ext_debug.elf" at
+           .text_addr = 0x20000034
+           .data_addr = 0x200000b4
+           .bss_addr = 0x2000c2e0
+           .rodata_addr = 0x200000b8
+           .detach_addr = 0x200001d0
+   (y or n) y
+   Reading symbols from build/llext/detached_fn_ext_debug.elf...
+   (gdb) break detached_entry
+   Breakpoint 2 at 0x200001d0 (2 locations)
+   (gdb) continue
+   Continuing.
+
+   Breakpoint 2, 0x200001d0 in test_detached_ext ()
+   (gdb) backtrace
+   #0  0x200001d0 in test_detached_ext ()
+   #1  0x200000ac in test_detached_ext ()
+   #2  0x00000706 in llext_test_detached () at zephyr/tests/subsys/llext/src/test_llext.c:496
+   #3  0x00001a36 in run_test_functions (suite=0x92bc <z_ztest_test_node_llext>, data=0x0 <cbvprintf_package>, test=0x92d8 <z_ztest_unit_test.llext.test_detached>) at zephyr/subsys/testsuite/ztest/src/ztest.c:328
+   #4  test_cb (a=0x92bc <z_ztest_test_node_llext>, b=0x92d8 <z_ztest_unit_test.llext.test_detached>, c=0x0 <cbvprintf_package>) at zephyr/subsys/testsuite/ztest/src/ztest.c:662
+   #5  0x00000e96 in z_thread_entry (entry=0x1a05 <test_cb>, p1=0x92bc <z_ztest_test_node_llext>, p2=0x92d8 <z_ztest_unit_test.llext.test_detached>, p3=0x0 <cbvprintf_package>) at zephyr/lib/os/thread_entry.c:48
+   #6  0x00000000 in ?? ()
+
+The symbol associated with the breakpoint location and the last stack frames
+mistakenly reference the ELF buffer in the Zephyr application instead of the
+extension symbols. Note that GDB however knows both:
+
+.. code-block::
+   :caption: Terminal 2 (GDB client)
+
+   (gdb) info sym 0x200001d0
+   test_detached_ext + 464 in section datas of zephyr/build/zephyr/zephyr.elf
+   detached_entry in section .detach of zephyr/build/llext/detached_fn_ext_debug.elf
+   (gdb) info sym 0x200000ac
+   test_detached_ext + 172 in section datas of zephyr/build/zephyr/zephyr.elf
+   test_entry + 8 in section .text of zephyr/build/llext/detached_fn_ext_debug.elf
+
+It is also impossible to inspect the variables in the extension or step through
+code properly:
+
+.. code-block::
+   :caption: Terminal 2 (GDB client)
+
+   (gdb) print bss_cnt
+   No symbol "bss_cnt" in current context.
+   (gdb) print data_cnt
+   No symbol "data_cnt" in current context.
+   (gdb) next
+   Single stepping until exit from function test_detached_ext,
+   which has no line number information.
+
+   Breakpoint 2, 0x200001ea in test_detached_ext ()
+   (gdb)
+
+Discarding symbols
+------------------
+
+Discarding the Zephyr symbols and only focusing on the extension restores full
+debugging functionality at the cost of losing the global context (note the
+backtrace stops outside the extension):
+
+.. code-block::
+   :caption: Terminal 2 (GDB client)
+
+   (gdb) symbol-file
+   Discard symbol table from `zephyr/build/zephyr/zephyr.elf'? (y or n) y
+   Error in re-setting breakpoint 1: No symbol table is loaded.  Use the "file" command.
+   No symbol file now.
+   (gdb) add-symbol-file build/llext/detached_fn_ext_debug.elf -s .text 0x20000034 -s .data 0x200000b4 -s .bss 0x2000c2e0 -s .rodata 0x200000b8 -s .detach 0x200001d0
+   add symbol table from file "build/llext/detached_fn_ext_debug.elf" at
+           .text_addr = 0x20000034
+           .data_addr = 0x200000b4
+           .bss_addr = 0x2000c2e0
+           .rodata_addr = 0x200000b8
+           .detach_addr = 0x200001d0
+   (y or n) y
+   Reading symbols from build/llext/detached_fn_ext_debug.elf...
+   (gdb) backtrace
+   #0  detached_entry () at zephyr/tests/subsys/llext/src/detached_fn_ext.c:18
+   #1  0x200000ac in test_entry () at zephyr/tests/subsys/llext/src/detached_fn_ext.c:26
+   #2  0x00000706 in ?? ()
+   Backtrace stopped: previous frame identical to this frame (corrupt stack?)
+   (gdb) next
+   19              zassert_true(data_cnt < 0);
+   (gdb) print bss_cnt
+   $1 = 1
+   (gdb) print data_cnt
+   $2 = -2
+   (gdb)
+
+
+Editing the ELF file
+--------------------
+
+In this alternative approach, the patches to the Zephyr ELF file must be
+performed after building the Zephyr binary and starting the emulator on
+Terminal 1, but before starting the GDB client on Terminal 2.
+
+The above debugging session already identified ``test_detached_ext``, the char
+array that holds the ELF file, as an offending symbol, so that will be removed
+in a first pass. Performing the same steps multiple times, ``__data_start`` and
+``__data_region_start`` can also be found to overlap the memory area of
+interest.
+
+The following commands will remove all of these from the Zephyr ELF file, then
+start a debugging session on the modified file:
+
+.. code-block::
+   :caption: Terminal 2 (GDB client)
+
+   zephyr$ export LLEXT_SDK_INSTALL_DIR=/opt/zephyr-sdk-0.17.0
+   zephyr$ ${LLEXT_SDK_INSTALL_DIR}/arm-zephyr-eabi/bin/arm-zephyr-eabi-objcopy -N test_detached_ext -N __data_start -N __data_region_start build/zephyr/zephyr.elf build/zephyr/zephyr-edit.elf
+   zephyr$ ${LLEXT_SDK_INSTALL_DIR}/arm-zephyr-eabi/bin/arm-zephyr-eabi-gdb build/zephyr/zephyr-edit.elf
+   GNU gdb (Zephyr SDK 0.17.0) 12.1
+   [...]
+   Reading symbols from build/zephyr/zephyr-edit.elf...
+   (gdb)
+
+The same steps used in the previous run can be performed again to attach to the
+GDB server and load both the extension and its debug symbols. This time, however,
+the result is rather different:
+
+ * the ``break`` command includes line number information;
+
+ * the output from ``backtrace`` contains functions from both the extension and
+   the Zephyr application;
+
+ * the local variables can be properly inspected.
+
+.. code-block::
+   :caption: Terminal 2 (GDB client)
+
+   (gdb) add-symbol-file build/llext/detached_fn_ext_debug.elf [...]
+   [...]
+   Reading symbols from build/llext/detached_fn_ext_debug.elf...
+   (gdb) break detached_entry
+   Breakpoint 2 at 0x200001d6: file zephyr/tests/subsys/llext/src/detached_fn_ext.c, line 17.
+   (gdb) continue
+   Continuing.
+
+   Breakpoint 2, detached_entry () at zephyr/tests/subsys/llext/src/detached_fn_ext.c:17
+   17              printk("bss %u @ %p\n", bss_cnt++, &bss_cnt);
+   (gdb) backtrace
+   #0  detached_entry () at zephyr/tests/subsys/llext/src/detached_fn_ext.c:17
+   #1  0x200000ac in test_entry () at zephyr/tests/subsys/llext/src/detached_fn_ext.c:26
+   #2  0x00000706 in llext_test_detached () at zephyr/tests/subsys/llext/src/test_llext.c:496
+   #3  0x00001a36 in run_test_functions (suite=0x92bc <z_ztest_test_node_llext>, data=0x0 <cbvprintf_package>, test=0x92d8 <z_ztest_unit_test.llext.test_detached>) at zephyr/subsys/testsuite/ztest/src/ztest.c:328
+   #4  test_cb (a=0x92bc <z_ztest_test_node_llext>, b=0x92d8 <z_ztest_unit_test.llext.test_detached>, c=0x0 <cbvprintf_package>) at zephyr/subsys/testsuite/ztest/src/ztest.c:662
+   #5  0x00000e96 in z_thread_entry (entry=0x1a05 <test_cb>, p1=0x92bc <z_ztest_test_node_llext>, p2=0x92d8 <z_ztest_unit_test.llext.test_detached>, p3=0x0 <cbvprintf_package>) at zephyr/lib/os/thread_entry.c:48
+   #6  0x00000000 in ?? ()
+   (gdb) print bss_cnt
+   $1 = 0
+   (gdb) print data_cnt
+   $2 = -3
+   (gdb)
diff --git a/doc/services/llext/index.rst b/doc/services/llext/index.rst
index ea63738ba3c..13bfe78316b 100644
--- a/doc/services/llext/index.rst
+++ b/doc/services/llext/index.rst
@@ -16,6 +16,7 @@ and introspected to some degree, as well as unloaded when no longer needed.
    config
    build
    load
+   debug
    api
 
 .. note::
diff --git a/doc/services/llext/load.rst b/doc/services/llext/load.rst
index 78fc897b87d..5438b58f17b 100644
--- a/doc/services/llext/load.rst
+++ b/doc/services/llext/load.rst
@@ -11,9 +11,17 @@ Loading an extension
 An extension may be loaded using any implementation of a :c:struct:`llext_loader`
 which has a set of function pointers that provide the necessary functionality
 to read the ELF data. A loader also provides some minimal context (memory)
-needed by the :c:func:`llext_load` function. An implementation over a buffer
-containing an ELF in addressable memory in memory is available as
-:c:struct:`llext_buf_loader`.
+needed by the :c:func:`llext_load` function. Several loaders are already provided:
+
+ * An implementation over a buffer containing an ELF in addressable memory in
+   memory is available as :c:struct:`llext_buf_loader`. To use this kind of
+   loader, it is helpful to use one of the :c:macro:`LLEXT_TEMPORARY_BUF_LOADER`,
+   :c:macro:`LLEXT_PERSISTENT_BUF_LOADER`, or :c:macro:`LLEXT_WRITABLE_BUF_LOADER`
+   macros to tell LLEXT the appropriate type of memory buffer.
+
+ * An implementation that reads data from a file in the filesystem is available
+   as the :c:struct:`llext_fs_loader`. The path to the file must be provided
+   when creating the loader with the :c:macro:`LLEXT_FS_LOADER` macro.
 
 The extensions are loaded with a call to the :c:func:`llext_load` function,
 passing in the extension name and the configured loader. Once that completes
@@ -60,6 +68,10 @@ The returned ``void *`` can then be cast to the appropriate type and used.
 A wrapper for calling a function with no arguments is provided in
 :c:func:`llext_call_fn`.
 
+Advanced users that need direct access to areas of the newly loaded extension
+may want to refer to :c:func:`llext_get_section_info` and other LLEXT
+inspection APIs.
+
 Cleaning up after use
 =====================
 
@@ -94,13 +106,7 @@ If any of this happens, the following tips may help understand the issue:
   the issue.
 
 * Use a debugger to inspect the memory and registers to try to understand what
-  is happening.
-
-  .. note::
-     When using GDB, the ``add_symbol_file`` command may be used to load the
-     debugging information and symbols from the ELF file. Make sure to specify
-     the proper offset (usually the start of the ``.text`` section, reported
-     as ``region 0`` in the debug logs.)
+  is happening. See :ref:`Debugging extensions <llext_debug>` for more details.
 
 If the issue persists, please open an issue in the GitHub repository, including
 all the above information.
diff --git a/doc/services/logging/index.rst b/doc/services/logging/index.rst
index 5aa868362b8..86f5e97d8c9 100644
--- a/doc/services/logging/index.rst
+++ b/doc/services/logging/index.rst
@@ -758,8 +758,8 @@ Please refer to the :zephyr:code-sample:`logging-dictionary` sample to learn mor
 the log parser.
 
 
-Recommendations
-***************
+Recommendations and limitations
+*******************************
 
 The are following recommendations:
 
@@ -771,7 +771,7 @@ The are following recommendations:
   format specifier and it points to a constant string.
 * It is recommended to cast pointer to ``char *`` when it is used with ``%s``
   format specifier and it points to a transient string.
-* It is recommended to cast character pointer to non character pointer
+* It is required to cast a character pointer to non character pointer
   (e.g., ``void *``) when it is used with ``%p`` format specifier.
 
 .. code-block:: c
@@ -779,6 +779,11 @@ The are following recommendations:
    LOG_WRN("%s", str);
    LOG_WRN("%p", (void *)str);
 
+There are following limitations:
+
+* Logging does not support string format specifier with width (e.g., ``%.*s`` or ``%8s``). That
+  is because format string content is not used to build a log message, only argument types.
+
 Benchmark
 *********
 
@@ -836,9 +841,6 @@ When :kconfig:option:`CONFIG_LOG_MODE_IMMEDIATE` is used then log message is pro
 which includes string formatting. In case of that mode, stack usage will depend on which backends
 are used.
 
-:zephyr_file:`tests/subsys/logging/log_stack` test is used to characterize stack usage depending
-on mode, optimization and platform used. Test is using only the default backend.
-
 Some of the platforms characterization for log message with two ``integer`` arguments listed below:
 
 +---------------+----------+----------------------------+-----------+-----------------------------+
diff --git a/doc/services/misc.rst b/doc/services/misc.rst
index 95cb27b5bd0..2c9ea5792f8 100644
--- a/doc/services/misc.rst
+++ b/doc/services/misc.rst
@@ -34,3 +34,16 @@ this API is limited to creating the simplistic tokens needed to
 authenticate with the Google Core IoT infrastructure.
 
 .. doxygengroup:: jwt
+
+Identifier APIs
+***************
+
+UUID
+====
+
+Universally Unique Identifiers (UUID), also known as Globally Unique
+IDentifiers (GUIDs) are an open, industry standard [RFC
+9562](https://tools.ietf.org/html/rfc9562) 128 bits long identifiers
+intended to guarantee uniqueness across space and time.
+
+.. doxygengroup:: uuid
diff --git a/doc/services/portability/posix/aep/index.rst b/doc/services/portability/posix/aep/index.rst
index 50f96b4c123..2eed8163c44 100644
--- a/doc/services/portability/posix/aep/index.rst
+++ b/doc/services/portability/posix/aep/index.rst
@@ -63,7 +63,7 @@ The *Minimal Realtime System Profile* (PSE51) includes all of the
     :ref:`_POSIX_MEMLOCK <posix_option_memlock>`, 200809L, :kconfig:option:`CONFIG_POSIX_MEMLOCK` :ref:`†<posix_undefined_behaviour>`
     :ref:`_POSIX_MEMLOCK_RANGE <posix_option_memlock_range>`, 200809L, :kconfig:option:`CONFIG_POSIX_MEMLOCK_RANGE`
     :ref:`_POSIX_MONOTONIC_CLOCK <posix_option_monotonic_clock>`, 200809L, :kconfig:option:`CONFIG_POSIX_MONOTONIC_CLOCK`
-    :ref:`_POSIX_SHARED_MEMORY_OBJECTS <posix_shared_memory_objects>`, 200809L, :kconfig:option:`CONFIG_POSIX_SHARED_MEMORY_OBJECTS`
+    :ref:`_POSIX_SHARED_MEMORY_OBJECTS <posix_option_shared_memory_objects>`, 200809L, :kconfig:option:`CONFIG_POSIX_SHARED_MEMORY_OBJECTS`
     :ref:`_POSIX_SYNCHRONIZED_IO <posix_option_synchronized_io>`, 200809L, :kconfig:option:`CONFIG_POSIX_SYNCHRONIZED_IO`
     :ref:`_POSIX_THREAD_ATTR_STACKADDR<posix_option_thread_attr_stackaddr>`, 200809L, :kconfig:option:`CONFIG_POSIX_THREAD_ATTR_STACKADDR`
     :ref:`_POSIX_THREAD_ATTR_STACKSIZE<posix_option_thread_attr_stacksize>`, 200809L, :kconfig:option:`CONFIG_POSIX_THREAD_ATTR_STACKSIZE`
diff --git a/doc/services/portability/posix/conformance/index.rst b/doc/services/portability/posix/conformance/index.rst
index e809ae08401..5581fbaa2bf 100644
--- a/doc/services/portability/posix/conformance/index.rst
+++ b/doc/services/portability/posix/conformance/index.rst
@@ -77,7 +77,7 @@ POSIX System Interfaces
     _POSIX_PRIORITIZED_IO, -1,
     :ref:`_POSIX_PRIORITY_SCHEDULING<posix_option_priority_scheduling>`, 200809L, :kconfig:option:`CONFIG_POSIX_PRIORITY_SCHEDULING`
     :ref:`_POSIX_RAW_SOCKETS<posix_option_raw_sockets>`, 200809L, :kconfig:option:`CONFIG_POSIX_RAW_SOCKETS`
-    :ref:`_POSIX_SHARED_MEMORY_OBJECTS <posix_shared_memory_objects>`, 200809L, :kconfig:option:`CONFIG_POSIX_SHARED_MEMORY_OBJECTS`
+    :ref:`_POSIX_SHARED_MEMORY_OBJECTS <posix_option_shared_memory_objects>`, 200809L, :kconfig:option:`CONFIG_POSIX_SHARED_MEMORY_OBJECTS`
     _POSIX_SPAWN, -1, :ref:`†<posix_undefined_behaviour>`
     _POSIX_SPORADIC_SERVER, -1, :ref:`†<posix_undefined_behaviour>`
     :ref:`_POSIX_SYNCHRONIZED_IO <posix_option_synchronized_io>`, 200809L, :kconfig:option:`CONFIG_POSIX_SYNCHRONIZED_IO`
@@ -95,7 +95,7 @@ POSIX System Interfaces
     _POSIX_TRACE_LOG, -1,
     _POSIX_TYPED_MEMORY_OBJECTS, -1,
     _XOPEN_CRYPT, -1,
-    _XOPEN_REALTIME, -1,
+    :ref:`_XOPEN_REALTIME <posix_option_group_xsi_realtime>`, 700, :kconfig:option:`CONFIG_XSI_REALTIME`
     _XOPEN_REALTIME_THREADS, -1,
     :ref:`_XOPEN_STREAMS<posix_option_xopen_streams>`, 200809L, :kconfig:option:`CONFIG_XOPEN_STREAMS`
     _XOPEN_UNIX, -1,
diff --git a/doc/services/portability/posix/option_groups/index.rst b/doc/services/portability/posix/option_groups/index.rst
index e1e2b930cc8..542ef326303 100644
--- a/doc/services/portability/posix/option_groups/index.rst
+++ b/doc/services/portability/posix/option_groups/index.rst
@@ -72,6 +72,25 @@ Group.
 For more information on developing Zephyr applications in the C programming language, please refer
 to :ref:`details<language_support>`.
 
+.. _posix_option_group_c_lang_support_r:
+
+POSIX_C_LANG_SUPPORT_R
+++++++++++++++++++++++
+
+Enable this option group with :kconfig:option:`CONFIG_POSIX_C_LANG_SUPPORT_R`.
+
+.. csv-table:: POSIX_C_LANG_SUPPORT_R
+   :header: API, Supported
+   :widths: 50,10
+
+    asctime_r(),yes
+    ctime_r(),yes
+    gmtime_r(),yes
+    localtime_r(),yes
+    rand_r(),yes
+    strerror_r(),yes
+    strtok_r(),yes
+
 .. _posix_option_group_c_lib_ext:
 
 POSIX_C_LIB_EXT
@@ -641,6 +660,24 @@ Enable this option group with :kconfig:option:`CONFIG_POSIX_TIMERS`.
     timer_getoverrun(),yes
     timer_settime(),yes
 
+.. _posix_option_group_xsi_realtime:
+
+XSI_REALTIME
+++++++++++++
+
+The ``XSI_REALTIME`` option group indicates that the :ref:`_POSIX_FSYNC<posix_option_fsync>`,
+:ref:`_POSIX_MEMLOCK<posix_option_memlock>`,
+:ref:`_POSIX_MEMLOCK_RANGE<posix_option_memlock_range>`,
+:ref:`_POSIX_MESSAGE_PASSING<posix_option_message_passing>`,
+:ref:`_POSIX_PRIORITY_SCHEDULING<posix_option_priority_scheduling>`,
+:ref:`_POSIX_SHARED_MEMORY_OBJECTS<posix_option_shared_memory_objects>`, and
+:ref:`_POSIX_SYNCHRONIZED_IO<posix_option_synchronized_io>` options are enabled.
+
+Enable this option group with :kconfig:option:`CONFIG_XSI_REALTIME`.
+
+When this option group is enabled, the ``_XOPEN_REALTIME`` feature test macro will be defined to a
+value other than -1.
+
 .. _posix_option_group_xsi_system_logging:
 
 XSI_SYSTEM_LOGGING
@@ -866,8 +903,12 @@ Enable this option with :kconfig:option:`CONFIG_POSIX_READER_WRITER_LOCKS`.
     pthread_rwlockattr_init(),yes
     pthread_rwlockattr_setpshared(),yes
 
+..
+   this link is "deprecated" - mainly left here so that older links still work
 .. _posix_shared_memory_objects:
 
+.. _posix_option_shared_memory_objects:
+
 _POSIX_SHARED_MEMORY_OBJECTS
 ++++++++++++++++++++++++++++
 
diff --git a/doc/services/retention/blinfo.rst b/doc/services/retention/blinfo.rst
index db9c548e9c7..b3422f273e3 100644
--- a/doc/services/retention/blinfo.rst
+++ b/doc/services/retention/blinfo.rst
@@ -15,7 +15,7 @@ Devicetree setup
 To use the bootloader information subsystem, a retention area needs to be
 created which has a retained data section as its parent, generally non-init RAM
 is used for this purpose. See the following example (examples in this guide are
-based on the :ref:`nrf52840dk_nrf52840` board and memory layout):
+based on the :zephyr:board:`nrf52840dk` board and memory layout):
 
 .. code-block:: devicetree
 
diff --git a/doc/services/retention/index.rst b/doc/services/retention/index.rst
index 1f6de06eae2..b4ba1564dbb 100644
--- a/doc/services/retention/index.rst
+++ b/doc/services/retention/index.rst
@@ -33,7 +33,7 @@ RAM as non-init for this purpose. The retention system is then initialised as a
 child node of this device 1 or more times - note that the memory region will
 need to be decremented to account for this reserved portion of RAM. See the
 following example (examples in this guide are based on the
-:ref:`nrf52840dk_nrf52840` board and memory layout):
+:zephyr:board:`nrf52840dk` board and memory layout):
 
 .. code-block:: devicetree
 
@@ -114,8 +114,8 @@ using:
 	#include <zephyr/device.h>
 	#include <zephyr/retention/retention.h>
 
+	const struct device *retention0 = DEVICE_DT_GET(DT_NODELABEL(retention0));
 	const struct device *retention1 = DEVICE_DT_GET(DT_NODELABEL(retention1));
-	const struct device *retention2 = DEVICE_DT_GET(DT_NODELABEL(retention2));
 
 When the write function is called, the magic header and checksum (if enabled)
 will be set on the area, and it will be marked as valid from that point
diff --git a/doc/services/secure_storage.rst b/doc/services/secure_storage.rst
deleted file mode 100644
index 5f7b90943b6..00000000000
--- a/doc/services/secure_storage.rst
+++ /dev/null
@@ -1,119 +0,0 @@
-.. _secure_storage:
-
-Secure storage
-##############
-
-| The secure storage subsystem provides an implementation of the functions defined in the
-  `Platform Security Architecture (PSA) Secure Storage API <https://arm-software.github.io/psa-api/storage/>`_.
-| It can be enabled on :term:`board targets<board target>`
-  that don't already have an implementation of the API.
-
-Overview
-********
-
-The secure storage subsystem makes the PSA Secure Storage API available on all board targets with
-non-volatile memory support.
-As such, it provides an implementation of the API on those that don't already have one, ensuring
-functional support for the API.
-Board targets with :ref:`tfm` enabled (ending in ``/ns``), for instance,
-cannot enable the subsystem because TF-M already provides an implementation of the API.
-
-| In addition to providing functional support for the API, depending on
-  device-specific security features and the configuration, the subsystem
-  may secure the data stored via the PSA Secure Storage API at rest.
-| Keep in mind, however, that it's preferable to use a secure processing environment like TF-M when
-  possible because it's able to provide more security due to isolation guarantees.
-
-Limitations
-***********
-
-The secure storage subsystem's implementation of the PSA Secure Storage API:
-
-* does not aim at full compliance with the specification.
-
-  | Its foremost goal is functional support for the API on all board targets.
-  | See below for important ways the implementation deviates from the specification.
-
-* does not guarantee that the data it stores will be secure at rest in all cases.
-
-  This depends on device-specific security features and the configuration.
-
-* does not yet provide an implementation of the Protected Storage (PS) API as of this writing.
-
-  Instead, the PS API directly calls into the Internal Trusted Storage (ITS) API
-  (unless a `custom implementation <#whole-api>`_ of the PS API is provided).
-
-Below are some ways the implementation deviates from the specification
-and an explanation why. This is not an exhaustive list.
-
-* The data stored in the ITS is by default encrypted and authenticated (Against ``1.`` in
-  `3.2. Internal Trusted Storage requirements <https://arm-software.github.io/psa-api/storage/1.0/overview/requirements.html#internal-trusted-storage-requirements>`_.)
-
-  | The specification considers the storage underlying the ITS to be
-    ``implicitly confidential and protected from replay``
-    (`2.4. The Internal Trusted Storage API <https://arm-software.github.io/psa-api/storage/1.0/overview/architecture.html#the-internal-trusted-storage-api>`_)
-    because ``most embedded microprocessors (MCU) have on-chip flash storage that can be made
-    inaccessible except to software running on the MCU``
-    (`2.2. Technical Background <https://arm-software.github.io/psa-api/storage/1.0/overview/architecture.html#technical-background>`_).
-  | This is not the case on all MCUs. Thus, additional protection is provided to the stored data.
-
-  However, this does not guarantee that the data stored will be secure at rest in all cases,
-  because this depends on device-specific security features and the configuration.
-  It requires a random entropy source and especially a secure encryption key provider
-  (:kconfig:option:`CONFIG_SECURE_STORAGE_ITS_TRANSFORM_AEAD_KEY_PROVIDER`).
-
-  In addition, the data stored in the ITS is not protected against replay attacks,
-  because this requires storage that is protected by hardware.
-
-* The data stored via the PSA Secure Storage API is not protected from direct
-  read/write by software or debugging. (Against ``2.`` and ``10.`` in
-  `3.2. Internal Trusted Storage requirements <https://arm-software.github.io/psa-api/storage/1.0/overview/requirements.html#internal-trusted-storage-requirements>`_.)
-
-  It is only secured at rest. Protecting it at runtime as well
-  requires specific hardware mechanisms to support this.
-
-Configuration
-*************
-
-To configure the implementation of the PSA Secure Storage API provided by Zephyr, have a look at the
-``CONFIG_SECURE_STORAGE_.*`` Kconfig options. They are defined in the various Kconfig files found
-under ``subsys/secure_storage/``.
-
-Customization
-*************
-
-Custom implementations can also replace those of Zephyr at different levels
-if the functionality provided by the existing implementations isn't enough.
-
-Whole API
-=========
-
-If you already have an implementation of the whole ITS or PS API and want to make use of it, you
-can do so by enabling the following Kconfig option and implementing the relevant functions:
-
-* :kconfig:option:`CONFIG_SECURE_STORAGE_ITS_IMPLEMENTATION_CUSTOM`, for the ITS API.
-* :kconfig:option:`CONFIG_SECURE_STORAGE_PS_IMPLEMENTATION_CUSTOM`, for the PS API.
-
-ITS API
-=======
-
-Zephyr's implementation of the ITS API
-(:kconfig:option:`CONFIG_SECURE_STORAGE_ITS_IMPLEMENTATION_ZEPHYR`)
-makes use of the ITS transform and store modules, which can be configured and customized separately.
-Have a look at the ``CONFIG_SECURE_STORAGE_ITS_(STORE|TRANSFORM)_.*_CUSTOM``
-Kconfig options to see the different customization possibilities.
-
-It's especially recommended to implement a custom encryption key provider
-(:kconfig:option:`CONFIG_SECURE_STORAGE_ITS_TRANSFORM_AEAD_KEY_PROVIDER_CUSTOM`)
-that is more secure than the available options, if possible.
-
-Samples
-*******
-
-* :zephyr:code-sample:`persistent_key`
-* :zephyr:code-sample:`psa_its`
-
-PSA Secure Storage API reference
-********************************
-
-.. doxygengroup:: psa_secure_storage
diff --git a/doc/services/shell/index.rst b/doc/services/shell/index.rst
index d1aa82dc7a3..c747c00fc84 100644
--- a/doc/services/shell/index.rst
+++ b/doc/services/shell/index.rst
@@ -110,7 +110,7 @@ Details on the configuration settings are captured in the following files:
 - :zephyr_file:`snippets/nus-console/nus-console.conf`.
 - :zephyr_file:`snippets/nus-console/nus-console.overlay`.
 
-Segget RTT
+Segger RTT
 ==========
 
 To configure Segger RTT backend, add the following configurations to your build:
diff --git a/doc/services/storage/index.rst b/doc/services/storage/index.rst
index f6e069ecf2a..0fe31e8edcc 100644
--- a/doc/services/storage/index.rst
+++ b/doc/services/storage/index.rst
@@ -12,3 +12,5 @@ Storage
    flash_map/flash_map.rst
    fcb/fcb.rst
    stream/stream_flash.rst
+   secure_storage/index.rst
+   settings/index.rst
diff --git a/doc/services/storage/secure_storage/index.rst b/doc/services/storage/secure_storage/index.rst
new file mode 100644
index 00000000000..83eb7aa4dac
--- /dev/null
+++ b/doc/services/storage/secure_storage/index.rst
@@ -0,0 +1,119 @@
+.. _secure_storage:
+
+Secure Storage
+##############
+
+| The secure storage subsystem provides an implementation of the functions defined in the
+  `Platform Security Architecture (PSA) Secure Storage API <https://arm-software.github.io/psa-api/storage/>`_.
+| It can be enabled on :term:`board targets<board target>`
+  that don't already have an implementation of the API.
+
+Overview
+********
+
+The secure storage subsystem makes the PSA Secure Storage API available on all board targets with
+non-volatile memory support.
+As such, it provides an implementation of the API on those that don't already have one, ensuring
+functional support for the API.
+Board targets with :ref:`tfm` enabled (ending in ``/ns``), for instance,
+cannot enable the subsystem because TF-M already provides an implementation of the API.
+
+| In addition to providing functional support for the API, depending on
+  device-specific security features and the configuration, the subsystem
+  may secure the data stored via the PSA Secure Storage API at rest.
+| Keep in mind, however, that it's preferable to use a secure processing environment like TF-M when
+  possible because it's able to provide more security due to isolation guarantees.
+
+Limitations
+***********
+
+The secure storage subsystem's implementation of the PSA Secure Storage API:
+
+* does not aim at full compliance with the specification.
+
+  | Its foremost goal is functional support for the API on all board targets.
+  | See below for important ways the implementation deviates from the specification.
+
+* does not guarantee that the data it stores will be secure at rest in all cases.
+
+  This depends on device-specific security features and the configuration.
+
+* does not yet provide an implementation of the Protected Storage (PS) API as of this writing.
+
+  Instead, the PS API directly calls into the Internal Trusted Storage (ITS) API
+  (unless a `custom implementation <#whole-api>`_ of the PS API is provided).
+
+Below are some ways the implementation deviates from the specification
+and an explanation why. This is not an exhaustive list.
+
+* The data stored in the ITS is by default encrypted and authenticated (Against ``1.`` in
+  `3.2. Internal Trusted Storage requirements <https://arm-software.github.io/psa-api/storage/1.0/overview/requirements.html#internal-trusted-storage-requirements>`_.)
+
+  | The specification considers the storage underlying the ITS to be
+    ``implicitly confidential and protected from replay``
+    (`2.4. The Internal Trusted Storage API <https://arm-software.github.io/psa-api/storage/1.0/overview/architecture.html#the-internal-trusted-storage-api>`_)
+    because ``most embedded microprocessors (MCU) have on-chip flash storage that can be made
+    inaccessible except to software running on the MCU``
+    (`2.2. Technical Background <https://arm-software.github.io/psa-api/storage/1.0/overview/architecture.html#technical-background>`_).
+  | This is not the case on all MCUs. Thus, additional protection is provided to the stored data.
+
+  However, this does not guarantee that the data stored will be secure at rest in all cases,
+  because this depends on device-specific security features and the configuration.
+  It requires a random entropy source and especially a secure encryption key provider
+  (:kconfig:option:`CONFIG_SECURE_STORAGE_ITS_TRANSFORM_AEAD_KEY_PROVIDER`).
+
+  In addition, the data stored in the ITS is not protected against replay attacks,
+  because this requires storage that is protected by hardware.
+
+* The data stored via the PSA Secure Storage API is not protected from direct
+  read/write by software or debugging. (Against ``2.`` and ``10.`` in
+  `3.2. Internal Trusted Storage requirements <https://arm-software.github.io/psa-api/storage/1.0/overview/requirements.html#internal-trusted-storage-requirements>`_.)
+
+  It is only secured at rest. Protecting it at runtime as well
+  requires specific hardware mechanisms to support this.
+
+Configuration
+*************
+
+To configure the implementation of the PSA Secure Storage API provided by Zephyr, have a look at the
+``CONFIG_SECURE_STORAGE_.*`` Kconfig options. They are defined in the various Kconfig files found
+under ``subsys/secure_storage/``.
+
+Customization
+*************
+
+Custom implementations can also replace those of Zephyr at different levels
+if the functionality provided by the existing implementations isn't enough.
+
+Whole API
+=========
+
+If you already have an implementation of the whole ITS or PS API and want to make use of it, you
+can do so by enabling the following Kconfig option and implementing the relevant functions:
+
+* :kconfig:option:`CONFIG_SECURE_STORAGE_ITS_IMPLEMENTATION_CUSTOM`, for the ITS API.
+* :kconfig:option:`CONFIG_SECURE_STORAGE_PS_IMPLEMENTATION_CUSTOM`, for the PS API.
+
+ITS API
+=======
+
+Zephyr's implementation of the ITS API
+(:kconfig:option:`CONFIG_SECURE_STORAGE_ITS_IMPLEMENTATION_ZEPHYR`)
+makes use of the ITS transform and store modules, which can be configured and customized separately.
+Have a look at the ``CONFIG_SECURE_STORAGE_ITS_(STORE|TRANSFORM)_.*_CUSTOM``
+Kconfig options to see the different customization possibilities.
+
+It's especially recommended to implement a custom encryption key provider
+(:kconfig:option:`CONFIG_SECURE_STORAGE_ITS_TRANSFORM_AEAD_KEY_PROVIDER_CUSTOM`)
+that is more secure than the available options, if possible.
+
+Samples
+*******
+
+* :zephyr:code-sample:`persistent_key`
+* :zephyr:code-sample:`psa_its`
+
+PSA Secure Storage API reference
+********************************
+
+.. doxygengroup:: psa_secure_storage
diff --git a/doc/services/settings/index.rst b/doc/services/storage/settings/index.rst
similarity index 100%
rename from doc/services/settings/index.rst
rename to doc/services/storage/settings/index.rst
diff --git a/doc/services/tfm/requirements.rst b/doc/services/tfm/requirements.rst
index 0221683d4a1..180d0c821eb 100644
--- a/doc/services/tfm/requirements.rst
+++ b/doc/services/tfm/requirements.rst
@@ -18,7 +18,7 @@ The following are some of the boards that can be used with TF-M:
      - ``lpcxpresso55s69_ns``
    * - :ref:`nrf9160dk_nrf9160`
      - ``nrf9160dk/nrf9160/ns``
-   * - :ref:`nrf5340dk_nrf5340`
+   * - :zephyr:board:`nrf5340dk`
      - ``nrf5340dk/nrf5340/cpuapp/ns``
    * - :zephyr:board:`b_u585i_iot02a`
      - ``b_u585i_iot02a/stm32u585xx/ns``
diff --git a/doc/services/tracing/index.rst b/doc/services/tracing/index.rst
index 45ee08c1432..61ac2e790ea 100644
--- a/doc/services/tracing/index.rst
+++ b/doc/services/tracing/index.rst
@@ -41,7 +41,7 @@ also provides one generic named tracing function for convenience purposes,
 as well as to demonstrate how tracing frameworks could be extended.
 
 Users can generate a custom trace event by calling
-:c:func:`sys_tracing_named_event`, which takes an event name as well as two
+:c:func:`sys_trace_named_event`, which takes an event name as well as two
 arbitrary 4 byte arguments. Tracing backends may truncate the provided event
 name if it is too long for the serialization format they support.
 
diff --git a/doc/services/zbus/index.rst b/doc/services/zbus/index.rst
index 1cc053ce75d..a7d6b7c55c4 100644
--- a/doc/services/zbus/index.rst
+++ b/doc/services/zbus/index.rst
@@ -636,6 +636,34 @@ the defined channels and observers.
     ZBUS_CHAN_DECLARE(acc_chan, version_chan);
 
 
+Unique channel identifiers
+--------------------------
+
+To simplify integrations with external entities, it is possible to assign a unique numeric identifier
+to a channel. Users can then retrieve the channel reference by using the identifier with
+:c:func:`zbus_chan_from_id`, rather than needing to obtain the reference at compile time with
+:c:macro:`ZBUS_CHAN_DECLARE`. Channels using this feature are declared with
+:c:func:`ZBUS_CHAN_DEFINE_WITH_ID`.
+
+.. code-block:: c
+
+    ZBUS_CHAN_DEFINE_WITH_ID(control_chan,    /* Name */
+        0x12345678,              /* Unique channel identifier */
+        struct control_msg,      /* Message type */
+        control_validator,       /* Validator */
+        &message_count,          /* User data */
+        ZBUS_OBSERVERS_EMPTY,    /* observers */
+        ZBUS_MSG_INIT(.move = 0) /* Initial value */
+    );
+
+    static void channel_retrieve(void)
+    {
+        const struct zbus_channel *chan = zbus_chan_from_id(0x12345678);
+
+        ...
+    }
+
+
 Iterating over channels and observers
 =====================================
 
@@ -820,25 +848,28 @@ The following code has the exact behavior of the code in :ref:`reading from a ch
 Runtime observer registration
 -----------------------------
 
-It is possible to add observers to channels in runtime. This feature uses the heap to allocate the
-nodes dynamically. The heap size limits the number of dynamic observers zbus can create. Therefore,
-set the :kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS` to enable the feature. It is possible to
-adjust the heap size by changing the configuration :kconfig:option:`CONFIG_HEAP_MEM_POOL_SIZE`. The
-following example illustrates the runtime registration usage.
-
-
+It is possible to add observers to channels at runtime if
+:kconfig:option:`CONFIG_ZBUS_RUNTIME_OBSERVERS` is enabled. In addition to the channel and observer
+references, :c:func:`zbus_chan_add_obs` also requires a :c:struct:`zbus_observer_node` to link the two
+together, which must remain valid in memory for the duration that the observer is attached to the
+channel. The simplest way to achieve this is to make the structure ``static``.
 
 .. code-block:: c
 
     ZBUS_LISTENER_DEFINE(my_listener, callback);
     // ...
     void thread_entry(void) {
+            static struct zbus_observer_node obs_node;
             // ...
             /* Adding the observer to channel chan1 */
-            zbus_chan_add_obs(&chan1, &my_listener, K_NO_WAIT);
+            zbus_chan_add_obs(&chan1, &my_listener, &obs_node, K_NO_WAIT);
             /* Removing the observer from channel chan1 */
             zbus_chan_rm_obs(&chan1, &my_listener, K_NO_WAIT);
 
+.. warning::
+
+  The :c:struct:`zbus_observer_node` can only be re-used in :c:func:`zbus_chan_add_obs` after removing
+  the channel observer it was first associated with through :c:func:`zbus_chan_rm_obs`.
 
 Samples
 *******
diff --git a/doc/templates/board.tmpl b/doc/templates/board.tmpl
index 96201094eed..38aa0fafa1d 100644
--- a/doc/templates/board.tmpl
+++ b/doc/templates/board.tmpl
@@ -17,7 +17,8 @@ Hardware
 
 Supported Features
 ==================
-[List of supported features and level of support in Zephyr]
+
+.. zephyr:board-supported-hw::
 
 Connections and IOs
 ===================
@@ -28,6 +29,8 @@ to connect external components]
 Programming and Debugging
 *************************
 
+.. zephyr:board-supported-runners::
+
 Flashing
 ========
 [How to use this board with Zephyr and how to flash a Zephyr binary on this
diff --git a/doc/zephyr.doxyfile.in b/doc/zephyr.doxyfile.in
index dfd9251bb7b..11b1da30688 100644
--- a/doc/zephyr.doxyfile.in
+++ b/doc/zephyr.doxyfile.in
@@ -1039,7 +1039,8 @@ RECURSIVE              = YES
 # run.
 
 EXCLUDE                = @ZEPHYR_BASE@/include/zephyr/portability/cmsis_os.h \
-                         @ZEPHYR_BASE@/include/zephyr/portability/cmsis_os2.h
+                         @ZEPHYR_BASE@/include/zephyr/portability/cmsis_os2.h \
+                         @ZEPHYR_BASE@/include/zephyr/drivers/wifi/nrf_wifi
 
 # The EXCLUDE_SYMLINKS tag can be used to select whether or not files or
 # directories that are symbolic links (a Unix file system feature) are excluded
diff --git a/drivers/CMakeLists.txt b/drivers/CMakeLists.txt
index 2536e201171..50f64359a39 100644
--- a/drivers/CMakeLists.txt
+++ b/drivers/CMakeLists.txt
@@ -53,8 +53,8 @@ add_subdirectory_ifdef(CONFIG_I2S i2s)
 add_subdirectory_ifdef(CONFIG_I3C i3c)
 add_subdirectory_ifdef(CONFIG_IEEE802154 ieee802154)
 add_subdirectory_ifdef(CONFIG_INPUT input)
+add_subdirectory_ifdef(CONFIG_INTEL_ADSP_MIC_PRIVACY audio/mic_privacy/intel)
 add_subdirectory_ifdef(CONFIG_IPM ipm)
-add_subdirectory_ifdef(CONFIG_KSCAN kscan)
 add_subdirectory_ifdef(CONFIG_LED led)
 add_subdirectory_ifdef(CONFIG_LED_STRIP led_strip)
 add_subdirectory_ifdef(CONFIG_LORA lora)
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 65f097f2acc..401220c4917 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -8,6 +8,7 @@ menu "Device Drivers"
 # zephyr-keep-sorted-start
 source "drivers/adc/Kconfig"
 source "drivers/audio/Kconfig"
+source "drivers/audio/mic_privacy/intel/Kconfig.mic_privacy"
 source "drivers/auxdisplay/Kconfig"
 source "drivers/bbram/Kconfig"
 source "drivers/bluetooth/Kconfig"
@@ -49,7 +50,6 @@ source "drivers/input/Kconfig"
 source "drivers/interrupt_controller/Kconfig"
 source "drivers/interrupt_controller/Kconfig.shared_irq"
 source "drivers/ipm/Kconfig"
-source "drivers/kscan/Kconfig"
 source "drivers/led/Kconfig"
 source "drivers/led_strip/Kconfig"
 source "drivers/lora/Kconfig"
diff --git a/drivers/adc/CMakeLists.txt b/drivers/adc/CMakeLists.txt
index f0e5707e3ff..fb224a603ad 100644
--- a/drivers/adc/CMakeLists.txt
+++ b/drivers/adc/CMakeLists.txt
@@ -6,6 +6,7 @@ zephyr_library()
 
 zephyr_library_sources_ifdef(CONFIG_ADC			adc_common.c)
 zephyr_library_sources_ifdef(CONFIG_ADC_TELINK_B91	adc_b91.c)
+zephyr_library_sources_ifdef(CONFIG_ADC_ITE_IT51XXX	adc_ite_it51xxx.c)
 zephyr_library_sources_ifdef(CONFIG_ADC_ITE_IT8XXX2	adc_ite_it8xxx2.c)
 zephyr_library_sources_ifdef(CONFIG_ADC_SHELL		adc_shell.c)
 zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_ADC12	adc_mcux_adc12.c)
@@ -34,7 +35,7 @@ zephyr_library_sources_ifdef(CONFIG_ADC_GD32		adc_gd32.c)
 zephyr_library_sources_ifdef(CONFIG_ADC_ADS1112		adc_ads1112.c)
 zephyr_library_sources_ifdef(CONFIG_ADC_ADS1119		adc_ads1119.c)
 zephyr_library_sources_ifdef(CONFIG_ADC_ADS7052		adc_ads7052.c)
-zephyr_library_sources_ifdef(CONFIG_ADC_ADS114S0X		adc_ads114s0x.c)
+zephyr_library_sources_ifdef(CONFIG_ADC_ADS1X4S0X		adc_ads1x4s0x.c)
 zephyr_library_sources_ifdef(CONFIG_ADC_ADS131M02		adc_ads131m02.c)
 zephyr_library_sources_ifdef(CONFIG_ADC_RPI_PICO	adc_rpi_pico.c)
 zephyr_library_sources_ifdef(CONFIG_ADC_XMC4XXX		adc_xmc4xxx.c)
@@ -55,4 +56,10 @@ zephyr_library_sources_ifdef(CONFIG_ADC_ENE_KB1200	adc_ene_kb1200.c)
 zephyr_library_sources_ifdef(CONFIG_ADC_MCUX_GAU	adc_mcux_gau_adc.c)
 zephyr_library_sources_ifdef(CONFIG_ADC_AMBIQ           adc_ambiq.c)
 zephyr_library_sources_ifdef(CONFIG_ADC_RENESAS_RA	adc_renesas_ra.c)
+zephyr_library_sources_ifdef(CONFIG_ADC_RENESAS_RZ  adc_renesas_rz.c)
 zephyr_library_sources_ifdef(CONFIG_ADC_MAX32		adc_max32.c)
+zephyr_library_sources_ifdef(CONFIG_ADC_AD4114      adc_ad4114.c)
+zephyr_library_sources_ifdef(CONFIG_ADC_AD7124		adc_ad7124.c)
+zephyr_library_sources_ifdef(CONFIG_ADC_AD405X		adc_ad405x.c)
+zephyr_library_sources_ifdef(CONFIG_ADC_AD4130		adc_ad4130.c)
+zephyr_library_sources_ifdef(CONFIG_ADC_REALTEK_RTS5912 adc_realtek_rts5912.c)
diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig
index ceaa8611572..9332cfeb723 100644
--- a/drivers/adc/Kconfig
+++ b/drivers/adc/Kconfig
@@ -56,6 +56,8 @@ source "subsys/logging/Kconfig.template.log_config"
 
 source "drivers/adc/Kconfig.b91"
 
+source "drivers/adc/Kconfig.it51xxx"
+
 source "drivers/adc/Kconfig.it8xxx2"
 
 source "drivers/adc/Kconfig.mcux"
@@ -100,7 +102,7 @@ source "drivers/adc/Kconfig.ads1119"
 
 source "drivers/adc/Kconfig.ads7052"
 
-source "drivers/adc/Kconfig.ads114s0x"
+source "drivers/adc/Kconfig.ads1x4s0x"
 
 source "drivers/adc/Kconfig.ads131m02"
 
@@ -134,6 +136,18 @@ source "drivers/adc/Kconfig.ambiq"
 
 source "drivers/adc/Kconfig.renesas_ra"
 
+source "drivers/adc/Kconfig.renesas_rz"
+
 source "drivers/adc/Kconfig.max32"
 
+source "drivers/adc/Kconfig.ad4114"
+
+source "drivers/adc/Kconfig.ad7124"
+
+source "drivers/adc/Kconfig.ad405x"
+
+source "drivers/adc/Kconfig.ad4130"
+
+source "drivers/adc/Kconfig.rts5912"
+
 endif # ADC
diff --git a/drivers/adc/Kconfig.ad405x b/drivers/adc/Kconfig.ad405x
new file mode 100644
index 00000000000..5abc89a8dd5
--- /dev/null
+++ b/drivers/adc/Kconfig.ad405x
@@ -0,0 +1,18 @@
+# ADI SoC ADC configuration options
+
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config ADC_AD405X
+	bool "AD405X ADC driver"
+	depends on DT_HAS_ADI_AD4052_ADC_ENABLED || DT_HAS_ADI_AD4050_ADC_ENABLED
+	select SPI
+	default y
+	help
+	  Enable ADC driver for ADI AD405X.
+
+config AD405X_TRIGGER
+	bool "AD405X interrupts"
+	default n
+	help
+	  Enable interrupts for ADI AD405X.
diff --git a/drivers/adc/Kconfig.ad4114 b/drivers/adc/Kconfig.ad4114
new file mode 100644
index 00000000000..3f57d23d1ac
--- /dev/null
+++ b/drivers/adc/Kconfig.ad4114
@@ -0,0 +1,25 @@
+# Copyright (c) 2023 Grinn
+# SPDX-License-Identifier: Apache-2.0
+
+config ADC_AD4114
+	bool "AD4114 ADC driver"
+	default y
+	depends on DT_HAS_ADI_AD4114_ADC_ENABLED
+	select SPI
+	help
+	  Enable the AD4114 ADC driver.
+
+config ADC_AD4114_ACQUISITION_THREAD_STACK_SIZE
+	int "Stack size for the ADC data acquisition thread"
+	depends on ADC_AD4114
+	default 512
+	help
+	  Size of the stack used for the internal data acquisition
+	  thread.
+
+config ADC_AD4114_ACQUISITION_THREAD_PRIO
+	int "Priority for the ADC data acquisition thread"
+	depends on ADC_AD4114
+	default 0
+	help
+	  Priority level for the internal ADC data acquisition thread.
diff --git a/drivers/adc/Kconfig.ad4130 b/drivers/adc/Kconfig.ad4130
new file mode 100644
index 00000000000..e1db1fee5af
--- /dev/null
+++ b/drivers/adc/Kconfig.ad4130
@@ -0,0 +1,25 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config ADC_AD4130
+	bool "ADI AD4130 Analog-to-Digital Converter"
+	default y
+	depends on DT_HAS_ADI_AD4130_ADC_ENABLED
+	select SPI
+	select ADC_CONFIGURABLE_INPUTS
+	help
+	  Enable the AD4130 ADC driver. It is SPI based
+	  Ultra Low Power, 24-Bit Sigma-Delta ADC.
+
+config ADI_AD4130_ADC_ACQUISITION_THREAD_PRIO
+	int "ADC data acquisition thread priority"
+	default 90
+	depends on ADC_AD4130 && ADC_ASYNC
+
+config ADI_AD4130_ADC_ACQUISITION_THREAD_STACK_SIZE
+	int "Stack size for the ADC data acquisition thread"
+	default 400
+	depends on ADC_AD4130 && ADC_ASYNC
+	help
+	  Size of the stack used for the internal data acquisition
+	  thread.
diff --git a/drivers/adc/Kconfig.ad7124 b/drivers/adc/Kconfig.ad7124
new file mode 100644
index 00000000000..6344f5c3372
--- /dev/null
+++ b/drivers/adc/Kconfig.ad7124
@@ -0,0 +1,25 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config ADC_AD7124
+	bool "ADI AD7124 Analog-to-Digital Converter"
+	default y
+	depends on DT_HAS_ADI_AD7124_ADC_ENABLED
+	select SPI
+	select CRC
+	select ADC_CONFIGURABLE_INPUTS
+	help
+	  Enable the ad7124 adc
+
+config ADI_AD7124_ADC_ACQUISITION_THREAD_INIT_PRIO
+	int "ADC data acquisition thread priority"
+	default 0
+	depends on ADC_AD7124 && ADC_ASYNC
+
+config ADI_AD7124_ADC_ACQUISITION_THREAD_STACK_SIZE
+	int "Stack size for the ADC data acquisition thread"
+	default 400
+	depends on ADC_AD7124 && ADC_ASYNC
+	help
+	  Size of the stack used for the internal data acquisition
+	  thread.
diff --git a/drivers/adc/Kconfig.ads114s0x b/drivers/adc/Kconfig.ads114s0x
deleted file mode 100644
index 45191bb92ea..00000000000
--- a/drivers/adc/Kconfig.ads114s0x
+++ /dev/null
@@ -1,44 +0,0 @@
-# Copyright (c) 2023 SILA  Embedded Solutions GmbH
-#
-# SPDX-License-Identifier: Apache-2.0
-
-menuconfig ADC_ADS114S0X
-	bool "Texas instruments ADS114S0x"
-	default y
-	depends on DT_HAS_TI_ADS114S08_ENABLED
-	select SPI
-	select ADC_CONFIGURABLE_INPUTS
-	select ADC_CONFIGURABLE_EXCITATION_CURRENT_SOURCE_PIN
-	select ADC_CONFIGURABLE_VBIAS_PIN
-	help
-	  Enable the driver implementation for the ADS114S0X family
-
-config ADC_ADS114S0X_ASYNC_THREAD_INIT_PRIO
-	int "ADC ADS114S0x async thread priority"
-	default 0
-	depends on ADC_ADS114S0X
-
-config ADC_ADS114S0X_ACQUISITION_THREAD_STACK_SIZE
-	int "Stack size for the ADC data acquisition thread"
-	default 400
-	depends on ADC_ADS114S0X
-	help
-	  Size of the stack used for the internal data acquisition
-	  thread.
-
-config ADC_ADS114S0X_GPIO
-	bool "GPIO support"
-	default n
-	depends on GPIO && ADC_ADS114S0X
-	help
-	  Enable GPIO child device support in the ADS114S0x ADC driver.
-
-	  The GPIO functionality is handled by the ADS114S0x GPIO
-	  driver.
-
-config ADC_ADS114S0X_WAIT_FOR_COMPLETION_TIMEOUT_MS
-	int "Timeout for wait for completion of a read in ms"
-	default 1000
-	depends on ADC_ADS114S0X
-	help
-	  This is the wait time in ms until a read is completed.
diff --git a/drivers/adc/Kconfig.ads1x4s0x b/drivers/adc/Kconfig.ads1x4s0x
new file mode 100644
index 00000000000..ecf38cf2de7
--- /dev/null
+++ b/drivers/adc/Kconfig.ads1x4s0x
@@ -0,0 +1,45 @@
+# Copyright (c) 2023 SILA  Embedded Solutions GmbH
+#
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig ADC_ADS1X4S0X
+	bool "Texas instruments ADS1X4S0X"
+	default y
+	depends on DT_HAS_TI_ADS114S06_ENABLED || DT_HAS_TI_ADS114S08_ENABLED \
+		|| DT_HAS_TI_ADS124S06_ENABLED || DT_HAS_TI_ADS124S08_ENABLED
+	select SPI
+	select ADC_CONFIGURABLE_INPUTS
+	select ADC_CONFIGURABLE_EXCITATION_CURRENT_SOURCE_PIN
+	select ADC_CONFIGURABLE_VBIAS_PIN
+	help
+	  Enable the driver implementation for the ADS1X4S0X family
+
+config ADC_ADS1X4S0X_ASYNC_THREAD_INIT_PRIO
+	int "ADC ADS1X4S0X async thread priority"
+	default 0
+	depends on ADC_ADS1X4S0X
+
+config ADC_ADS1X4S0X_ACQUISITION_THREAD_STACK_SIZE
+	int "Stack size for the ADC data acquisition thread"
+	default 400
+	depends on ADC_ADS1X4S0X
+	help
+	  Size of the stack used for the internal data acquisition
+	  thread.
+
+config ADC_ADS1X4S0X_GPIO
+	bool "GPIO support"
+	default n
+	depends on GPIO && ADC_ADS1X4S0X
+	help
+	  Enable GPIO child device support in the ADS1X4S0X ADC driver.
+
+	  The GPIO functionality is handled by the ADS1X4S0X GPIO
+	  driver.
+
+config ADC_ADS1X4S0X_WAIT_FOR_COMPLETION_TIMEOUT_MS
+	int "Timeout for wait for completion of a read in ms"
+	default 1000
+	depends on ADC_ADS1X4S0X
+	help
+	  This is the wait time in ms until a read is completed.
diff --git a/drivers/adc/Kconfig.it51xxx b/drivers/adc/Kconfig.it51xxx
new file mode 100644
index 00000000000..a0a8efd452c
--- /dev/null
+++ b/drivers/adc/Kconfig.it51xxx
@@ -0,0 +1,27 @@
+# ADC configuration options
+
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config ADC_ITE_IT51XXX
+	bool "ITE IT51XXX ADC driver"
+	default y
+	depends on DT_HAS_ITE_IT51XXX_ADC_ENABLED
+	select PINCTRL
+	help
+	  This option enables the ADC driver for IT51XXX
+	  family of processors.
+	  Voltage range 0 to 3300mV.
+	  Support 12-bit resolution.
+	  Support 8 channels: ch0~ch7.
+
+if ADC_ITE_IT51XXX
+
+config ADC_IT51XXX_VOL_FULL_SCALE
+	bool "ADC internal voltage as full-scale"
+	default y
+	help
+	  This option enables ADC internal reference
+	  voltage as full-scale 3300mV.
+
+endif # ADC_ITE_IT51XXX
diff --git a/drivers/adc/Kconfig.renesas_rz b/drivers/adc/Kconfig.renesas_rz
new file mode 100644
index 00000000000..75146acf6d5
--- /dev/null
+++ b/drivers/adc/Kconfig.renesas_rz
@@ -0,0 +1,12 @@
+# Renesas RZ Family
+
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config ADC_RENESAS_RZ
+	bool "Renesas RZ ADC Driver"
+	default y
+	depends on DT_HAS_RENESAS_RZ_ADC_ENABLED
+	select USE_RZ_FSP_ADC
+	help
+	  Enable the RZ ADC driver.
diff --git a/drivers/adc/Kconfig.rts5912 b/drivers/adc/Kconfig.rts5912
new file mode 100644
index 00000000000..fdceea6f43a
--- /dev/null
+++ b/drivers/adc/Kconfig.rts5912
@@ -0,0 +1,10 @@
+# Copyright (c) 2025, Realtek, SIBG-SD7
+# SPDX-License-Identifier: Apache-2.0
+
+config ADC_REALTEK_RTS5912
+	bool "Realtek RTS5912 ADC drivers"
+	default y
+	depends on DT_HAS_REALTEK_RTS5912_ADC_ENABLED
+	select PINCTRL
+	help
+	  This option enables the ADC driver for Realtek RTS5912 of processors.
diff --git a/drivers/adc/adc_ad405x.c b/drivers/adc/adc_ad405x.c
new file mode 100644
index 00000000000..d45355781e1
--- /dev/null
+++ b/drivers/adc/adc_ad405x.c
@@ -0,0 +1,957 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/byteorder.h>
+
+LOG_MODULE_REGISTER(adc_ad405x, CONFIG_ADC_LOG_LEVEL);
+
+#define ADC_CONTEXT_USES_KERNEL_TIMER
+#include "adc_context.h"
+
+#define AD4050_CHIP_ID 4050
+#define AD4052_CHIP_ID 4052
+
+#define AD4050_ADC_RESOLUTION 12U
+#define AD4052_ADC_RESOLUTION 16U
+
+#define AD405X_REG_INTERFACE_CONFIG_A 0x00U
+#define AD405X_REG_DEVICE_CONFIG      0x02U
+#define AD405X_REG_DEVICE_TYPE        0x03U
+#define AD405X_REG_PRODUCT_ID_L       0x04U
+#define AD405X_REG_PRODUCT_ID_H       0x05U
+#define AD405X_REG_VENDOR_L           0x0CU
+#define AD405X_REG_VENDOR_H           0x0DU
+#define AD405X_REG_MODE_SET           0x20U
+#define AD405X_REG_ADC_MODES          0x21U
+#define AD405X_REG_AVG_CONFIG         0x23U
+#define AD405X_REG_GP_PIN_CONF        0x24U
+#define AD405X_REG_TIMER_CONFIG       0x27U
+
+#define AD405X_REG_INTERFACE_CONFIG_A_VAL       0x10U
+#define AD405X_REG_DEVICE_TYPE_VAL              0x07U
+#define AD4052_REG_PRODUCT_ID_VAL               0x0072U
+#define AD4050_REG_PRODUCT_ID_VAL               0x0070U
+#define AD405X_REG_VENDOR_VAL                   0x0456U
+#define AD405X_REG_INTERFACE_CONFIG_A_RESET_VAL 0x81U
+
+/** AD405X_REG_ADC_MODES Bit definition */
+#define AD405X_ADC_MODES_MSK        GENMASK(2, 0)
+#define AD405X_BURST_AVERAGING_MODE BIT(0)
+#define AD405X_AVERAGING_MODE       BIT(1)
+
+/** AD405X_REG_MODE_SET Bit definition */
+#define AD405X_ENTER_ADC_MODE_MSK BIT(0)
+#define AD405X_ENTER_ADC_MODE     BIT(0)
+#define AD405X_ENTER_SLEEP_MODE   BIT(1) | BIT(0)
+#define AD405X_ENTER_ACTIVE_MODE  0x0U
+
+/** AD405X_REG_AVG_CONFIG Bit Definitions */
+#define AD405X_AVG_WIN_LEN_MSK GENMASK(3, 0)
+
+#define AD405X_SINGLE_DIFFERENTIAL_MSK BIT(7)
+
+#define AD405X_WRITE_CMD 0x0U
+#define AD405X_READ_CMD  0x80U
+
+#define AD405X_SW_RESET_MSK   BIT(7) | BIT(0)
+
+#define AD405X_GP1_MODE_MSK GENMASK(6, 4)
+#define AD405X_GP0_MODE_MSK GENMASK(2, 0)
+#define AD405X_GP1          0x1U
+#define AD405X_GP0          0x0U
+
+#define AD405X_SINGLE_ENDED  0x0U
+#define AD405X_DIFFERENTIAL  BIT(7)
+
+/** AD405X_REG_TIMER_CONFIG Bit Definitions */
+#define AD405X_FS_BURST_AUTO_MSK GENMASK(7, 4)
+
+union ad405x_bus {
+	struct spi_dt_spec spi;
+};
+
+enum ad405x_gpx_mode {
+	AD405X_DISABLED = 0,
+	AD405X_GP0_1_INTR = 1,
+	AD405X_DATA_READY = 2,
+	AD405X_DEV_ENABLE = 3,
+	AD405X_CHOP = 4,
+	AD405X_LOGIC_LOW = 5,
+	AD405X_LOGIC_HIGH = 6,
+	AD405X_DEV_READY = 7
+};
+
+/** AD405X modes of operations */
+enum ad405x_operation_mode {
+	AD405X_SAMPLE_MODE_OP = 0,
+	AD405X_BURST_AVERAGING_MODE_OP = 1,
+	AD405X_AVERAGING_MODE_OP = 2,
+	AD405X_MONITOR_AUTO_MODE_OP = 3,
+	AD405X_CONFIG_MODE_OP = 4,
+	AD405X_SLEEP_MODE_OP = 5,
+	AD405X_TRIGGER_AUTO_MODE_OP = 7
+};
+
+/** AD405X sample rate for burst and autonomous modes */
+enum ad405x_sample_rate {
+	AD405X_2_MSPS,
+	AD405X_1_MSPS,
+	AD405X_333_KSPS,
+	AD405X_100_KSPS,
+	AD405X_33_KSPS,
+	AD405X_10_KSPS,
+	AD405X_3_KSPS,
+	AD405X_1_KSPS,
+	AD405X_500_SPS,
+	AD405X_333_SPS,
+	AD405X_250_SPS,
+	AD405X_200_SPS,
+	AD405X_166_SPS,
+	AD405X_140_SPS,
+	AD405X_125_SPS,
+	AD405X_111_SPS
+};
+
+/** AD405X averaging filter window length */
+enum ad405x_avg_filter_l {
+	AD405X_LENGTH_2,
+	AD405X_LENGTH_4,
+	AD405X_LENGTH_8,
+	AD405X_LENGTH_16,
+	AD405X_LENGTH_32,
+	AD405X_LENGTH_64,
+	AD405X_LENGTH_128,
+	AD405X_LENGTH_256,
+	AD405X_LENGTH_512,
+	AD405X_LENGTH_1024,
+	AD405X_LENGTH_2048,
+	AD405X_LENGTH_4096
+};
+static const int avg_filter_values[] = {2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048, 4096};
+
+struct adc_ad405x_config {
+	const union ad405x_bus bus;
+	enum ad405x_operation_mode active_mode;
+#ifdef CONFIG_AD405X_TRIGGER
+	struct gpio_dt_spec gp1_interrupt;
+	struct gpio_dt_spec gp0_interrupt;
+	uint8_t has_gp1;
+	uint8_t has_gp0;
+#endif
+	struct gpio_dt_spec conversion;
+	uint16_t chip_id;
+	const struct adc_dt_spec spec;
+};
+
+struct adc_ad405x_data {
+	struct adc_context ctx;
+	const struct device *dev;
+	uint8_t adc_conf;
+	uint8_t diff;
+	uint8_t channels;
+	uint16_t *buffer;
+	uint16_t *repeat_buffer;
+	enum ad405x_operation_mode operation_mode;
+	struct k_sem sem_devrdy;
+	const struct device *gpio_dev;
+	enum ad405x_gpx_mode gp1_mode;
+	enum ad405x_gpx_mode gp0_mode;
+	uint8_t dev_en_pol;
+	enum ad405x_sample_rate rate;
+	enum ad405x_avg_filter_l filter_length;
+#if CONFIG_AD405X_TRIGGER
+	struct gpio_callback gpio1_cb;
+	struct gpio_callback gpio0_cb;
+	struct k_sem sem_drdy;
+	uint8_t has_drdy;
+#endif
+};
+
+static bool ad405x_bus_is_ready_spi(const union ad405x_bus *bus)
+{
+	bool ret = spi_is_ready_dt(&bus->spi);
+
+	return ret;
+}
+
+int ad405x_reg_access_spi(const struct device *dev, uint8_t cmd, uint8_t reg_addr, uint8_t *data,
+			size_t length)
+{
+	const struct adc_ad405x_config *cfg = dev->config;
+	uint8_t access = reg_addr | cmd;
+	const struct spi_buf buf[2] = {{.buf = &access, .len = 1}, {.buf = data, .len = length}};
+	const struct spi_buf_set rx = {.buffers = buf, .count = ARRAY_SIZE(buf)};
+	struct spi_buf_set tx = {
+		.buffers = buf,
+		.count = 2,
+	};
+	int ret;
+
+	if (cmd == AD405X_READ_CMD) {
+		tx.count = 1;
+		ret = spi_transceive_dt(&cfg->bus.spi, &tx, &rx);
+	} else {
+		ret = spi_write_dt(&cfg->bus.spi, &tx);
+	}
+	return ret;
+}
+
+int ad405x_reset_pattern_cmd(const struct device *dev)
+{
+	const struct adc_ad405x_config *cfg = dev->config;
+#if CONFIG_AD405X_TRIGGER
+	struct adc_ad405x_data *data = dev->data;
+#endif
+	uint8_t access[18] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF,
+				0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE};
+	const struct spi_buf buf[1] = {{.buf = &access, .len = ARRAY_SIZE(access)}};
+	struct spi_buf_set tx = {
+		.buffers = buf,
+		.count = 1,
+	};
+
+	int ret = spi_write_dt(&cfg->bus.spi, &tx);
+
+	if (ret < 0) {
+		return ret;
+	}
+#if CONFIG_AD405X_TRIGGER
+	if (cfg->has_gp1 != 0) {
+		k_sem_take(&data->sem_devrdy, K_FOREVER);
+	} else {
+		k_msleep(5);
+	}
+#else
+	k_msleep(5);
+#endif
+	return ret;
+
+}
+
+int ad405x_read_raw(const struct device *dev, uint8_t *data, size_t len)
+{
+	const struct adc_ad405x_config *cfg = dev->config;
+	int ret = 0;
+	const struct spi_buf buf[1] = {{.buf = data, .len = len}};
+	const struct spi_buf_set rx = {.buffers = buf, .count = ARRAY_SIZE(buf)};
+
+	ret = spi_transceive_dt(&cfg->bus.spi, NULL, &rx);
+
+	return ret;
+}
+
+int ad405x_reg_access(const struct device *dev, uint8_t cmd, uint8_t addr, uint8_t *data,
+			size_t len)
+{
+	return ad405x_reg_access_spi(dev, cmd, addr, data, len);
+}
+
+int ad405x_reg_write(const struct device *dev, uint8_t addr, uint8_t *data, uint8_t len)
+{
+
+	return ad405x_reg_access(dev, AD405X_WRITE_CMD, addr, data, len);
+}
+
+int ad405x_reg_read(const struct device *dev, uint8_t addr, uint8_t *data, uint8_t len)
+{
+
+	return ad405x_reg_access(dev, AD405X_READ_CMD, addr, data, len);
+}
+
+int ad405x_reg_write_byte(const struct device *dev, uint8_t addr, uint8_t val)
+{
+	return ad405x_reg_write(dev, addr, &val, 1);
+}
+
+int ad405x_reg_read_byte(const struct device *dev, uint8_t addr, uint8_t *buf)
+
+{
+	return ad405x_reg_read(dev, addr, buf, 1);
+}
+
+int ad405x_reg_update_bits(const struct device *dev, uint8_t addr, uint8_t mask, uint8_t val)
+{
+	int ret;
+	uint8_t byte = 0;
+
+	ret = ad405x_reg_read_byte(dev, addr, &byte);
+	if (ret < 0) {
+		return ret;
+	}
+
+	byte &= ~mask;
+	byte |= val;
+
+	return ad405x_reg_write_byte(dev, addr, byte);
+}
+
+#if CONFIG_AD405X_TRIGGER
+static void ad405x_gpio1_callback(const struct device *dev, struct gpio_callback *cb,
+				uint32_t pins)
+{
+	struct adc_ad405x_data *drv_data = CONTAINER_OF(cb, struct adc_ad405x_data, gpio1_cb);
+	const struct adc_ad405x_config *cfg = drv_data->dev->config;
+	gpio_flags_t gpio_flag = GPIO_INT_EDGE_TO_ACTIVE;
+
+	gpio_pin_interrupt_configure_dt(&cfg->gp1_interrupt, GPIO_INT_DISABLE);
+
+	switch (drv_data->gp1_mode) {
+	case AD405X_DEV_READY:
+		k_sem_give(&drv_data->sem_devrdy);
+		break;
+	case AD405X_DATA_READY:
+		k_sem_give(&drv_data->sem_drdy);
+		gpio_flag = GPIO_INT_EDGE_TO_INACTIVE;
+		break;
+	default: /* TODO */
+		break;
+	}
+
+	gpio_pin_interrupt_configure_dt(&cfg->gp1_interrupt, gpio_flag);
+}
+
+static void ad405x_gpio0_callback(const struct device *dev, struct gpio_callback *cb,
+				uint32_t pins)
+{
+	struct adc_ad405x_data *drv_data = CONTAINER_OF(cb, struct adc_ad405x_data, gpio0_cb);
+	const struct adc_ad405x_config *cfg = drv_data->dev->config;
+	gpio_flags_t gpio_flag = GPIO_INT_EDGE_TO_ACTIVE;
+
+	gpio_pin_interrupt_configure_dt(&cfg->gp0_interrupt, GPIO_INT_DISABLE);
+
+	switch (drv_data->gp0_mode) {
+	case AD405X_DATA_READY:
+		k_sem_give(&drv_data->sem_drdy);
+		gpio_flag = GPIO_INT_EDGE_TO_INACTIVE;
+		break;
+	default:
+		break;
+	}
+
+	gpio_pin_interrupt_configure_dt(&cfg->gp0_interrupt, gpio_flag);
+
+}
+#endif
+
+int ad405x_init_conv(const struct device *dev)
+{
+	const struct adc_ad405x_config *cfg = dev->config;
+	struct adc_ad405x_data *drv_data = dev->data;
+	int ret;
+
+	if (!gpio_is_ready_dt(&cfg->conversion)) {
+		LOG_ERR("GPIO port %s not ready", cfg->conversion.port->name);
+		return -EINVAL;
+	}
+
+	ret = gpio_pin_configure_dt(&cfg->conversion, GPIO_OUTPUT_INACTIVE);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = gpio_pin_set_dt(&cfg->conversion, 0);
+	drv_data->dev = dev;
+	return ret;
+}
+
+#if CONFIG_AD405X_TRIGGER
+int ad405x_init_interrupt(const struct device *dev)
+{
+	const struct adc_ad405x_config *cfg = dev->config;
+	struct adc_ad405x_data *drv_data = dev->data;
+	int ret;
+
+	if (cfg->has_gp1 != 0) {
+
+		if (!gpio_is_ready_dt(&cfg->gp1_interrupt)) {
+			LOG_ERR("GPIO port %s not ready", cfg->gp1_interrupt.port->name);
+			return -EINVAL;
+		}
+
+		ret = gpio_pin_configure_dt(&cfg->gp1_interrupt, GPIO_INPUT);
+		if (ret != 0) {
+			return ret;
+		}
+
+		gpio_init_callback(&drv_data->gpio1_cb, ad405x_gpio1_callback,
+					BIT(cfg->gp1_interrupt.pin));
+
+		ret = gpio_add_callback(cfg->gp1_interrupt.port, &drv_data->gpio1_cb);
+		if (ret != 0) {
+			LOG_ERR("Failed to set gpio callback!");
+			return ret;
+		}
+
+		gpio_pin_interrupt_configure_dt(&cfg->gp1_interrupt, GPIO_INT_EDGE_TO_ACTIVE);
+	}
+
+	if (cfg->has_gp0 != 0) {
+
+		if (!gpio_is_ready_dt(&cfg->gp0_interrupt)) {
+			LOG_ERR("GPIO port %s not ready", cfg->gp0_interrupt.port->name);
+			return -EINVAL;
+		}
+
+		ret = gpio_pin_configure_dt(&cfg->gp0_interrupt, GPIO_INPUT);
+		if (ret != 0) {
+			return ret;
+		}
+
+		gpio_init_callback(&drv_data->gpio0_cb, ad405x_gpio0_callback,
+					BIT(cfg->gp0_interrupt.pin));
+
+		ret = gpio_add_callback(cfg->gp0_interrupt.port, &drv_data->gpio0_cb);
+		if (ret != 0) {
+			LOG_ERR("Failed to set gpio callback!");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+#endif
+
+static int ad405x_channel_setup(const struct device *dev,
+				const struct adc_channel_cfg *channel_cfg)
+{
+	const struct adc_ad405x_config *cfg = dev->config;
+	if (channel_cfg->channel_id != 0) {
+		LOG_ERR("invalid channel id %d", channel_cfg->channel_id);
+		return -EINVAL;
+	}
+	if (channel_cfg->differential != cfg->spec.channel_cfg.differential) {
+		LOG_ERR("invalid mode %d", channel_cfg->differential);
+		return -EINVAL;
+	}
+
+	uint8_t diff_mode = AD405X_SINGLE_ENDED;
+
+	if (channel_cfg->differential) {
+		diff_mode = AD405X_DIFFERENTIAL;
+	}
+	return ad405x_reg_update_bits(dev, AD405X_REG_ADC_MODES,
+				AD405X_SINGLE_DIFFERENTIAL_MSK, diff_mode);
+}
+
+static int adc_ad405x_validate_buffer_size(const struct device *dev,
+					const struct adc_sequence *sequence)
+{
+	uint8_t channels;
+	size_t needed;
+
+	channels = POPCOUNT(sequence->channels);
+	needed = channels * sizeof(uint16_t);
+
+	if (sequence->buffer_size < needed) {
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+int ad405x_conv_start(const struct device *dev)
+{
+	const struct adc_ad405x_config *cfg = dev->config;
+	int ret;
+
+	ret = gpio_pin_set_dt(&cfg->conversion, 1);
+	if (ret != 0) {
+		return ret;
+	}
+
+	/** CNV High Time min 10 ns */
+	k_busy_wait(1);
+	ret = gpio_pin_set_dt(&cfg->conversion, 0);
+	if (ret != 0) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static void adc_context_start_sampling(struct adc_context *ctx)
+{
+
+	struct adc_ad405x_data *data = CONTAINER_OF(ctx, struct adc_ad405x_data, ctx);
+	const struct adc_ad405x_config *cfg = (struct adc_ad405x_config *)data->dev->config;
+
+	uint8_t reg_val_x[3] = {0};
+	uint32_t data_be;
+	size_t len = 0;
+
+	switch (data->operation_mode) {
+	case AD405X_SAMPLE_MODE_OP:
+		len = 2;
+		ad405x_conv_start(data->dev);
+		break;
+	case AD405X_BURST_AVERAGING_MODE_OP:
+		if (cfg->chip_id == AD4052_CHIP_ID) {
+			len = 3;
+		}
+		ad405x_conv_start(data->dev);
+		break;
+	case AD405X_AVERAGING_MODE_OP:
+		if (cfg->chip_id == AD4052_CHIP_ID) {
+			len = 3;
+		}
+		uint16_t conv_avg = avg_filter_values[data->filter_length];
+
+		for (int i = 0; i < conv_avg; i++) {
+			ad405x_conv_start(data->dev);
+		}
+		break;
+	default:
+		len = 2;
+		break;
+	}
+
+#if CONFIG_AD405X_TRIGGER
+	if (data->has_drdy != 0) {
+		k_sem_take(&data->sem_drdy, K_FOREVER);
+	}
+#endif
+	ad405x_read_raw(data->dev, reg_val_x, len);
+	switch (len) {
+	case 2:
+		/* translate valid bytes to BE format */
+		data_be = sys_get_be16(reg_val_x);
+		break;
+	case 3:
+		data_be = sys_get_be24(reg_val_x);
+		break;
+	default:
+		data_be = sys_get_be16(reg_val_x);
+		break;
+	}
+	memcpy(ctx->sequence.buffer, &data_be, len);
+
+	adc_context_on_sampling_done(&data->ctx, data->dev);
+}
+
+int ad405x_set_sample_rate(const struct device *dev, enum ad405x_sample_rate rate)
+{
+	struct adc_ad405x_data *data = dev->data;
+	int ret;
+
+	ret = ad405x_reg_update_bits(dev, AD405X_REG_TIMER_CONFIG, AD405X_FS_BURST_AUTO_MSK, rate);
+	if (ret != 0) {
+		return ret;
+	}
+
+	data->rate = rate;
+
+	return 0;
+}
+
+int ad405x_set_averaging_filter_length(const struct device *dev, enum ad405x_avg_filter_l length)
+{
+	const struct adc_ad405x_config *cfg = dev->config;
+	struct adc_ad405x_data *data = dev->data;
+	int ret;
+
+	/* Restrict filter length depending on active device selected */
+	if (cfg->chip_id == AD4050_CHIP_ID) {
+		if (length > AD405X_LENGTH_256) {
+			return -EINVAL;
+		}
+	}
+	ret = ad405x_reg_update_bits(dev, AD405X_REG_AVG_CONFIG, AD405X_AVG_WIN_LEN_MSK, length);
+	if (ret) {
+		return ret;
+	}
+
+	data->filter_length = length;
+
+	return 0;
+}
+
+int ad405x_exit_command(const struct device *dev)
+{
+	int ret;
+
+	const struct adc_ad405x_config *cfg = dev->config;
+	struct adc_ad405x_data *data = dev->data;
+	uint8_t access[1] = {0xA8};
+	const struct spi_buf buf[1] = {{.buf = &access, .len = ARRAY_SIZE(access)}};
+	struct spi_buf_set tx = {
+		.buffers = buf,
+		.count = 1,
+	};
+
+	ret = spi_write_dt(&cfg->bus.spi, &tx);
+	if (!ret) {
+		data->operation_mode = AD405X_CONFIG_MODE_OP;
+	}
+
+	return ret;
+}
+
+int ad405x_set_operation_mode(const struct device *dev, enum ad405x_operation_mode operation_mode)
+{
+	struct adc_ad405x_data *data = dev->data;
+	int ret;
+
+	if (data->operation_mode == AD405X_SLEEP_MODE_OP) {
+		if (operation_mode != AD405X_SLEEP_MODE_OP) {
+			ret = ad405x_reg_write_byte(dev, AD405X_REG_DEVICE_CONFIG,
+						AD405X_ENTER_ACTIVE_MODE);
+			if (ret != 0) {
+				return ret;
+			}
+			if (operation_mode != AD405X_CONFIG_MODE_OP) {
+				/* Set Operation mode. */
+				ret = ad405x_reg_update_bits(dev, AD405X_REG_ADC_MODES,
+							  AD405X_ADC_MODES_MSK, operation_mode);
+				if (ret != 0) {
+					return ret;
+				}
+				/* Enter ADC_MODE. */
+				ret = ad405x_reg_update_bits(dev, AD405X_REG_MODE_SET,
+							     AD405X_ENTER_ADC_MODE_MSK,
+							     AD405X_ENTER_ADC_MODE);
+				if (ret != 0) {
+					return ret;
+				}
+			}
+		}
+	} else if (data->operation_mode == AD405X_CONFIG_MODE_OP) {
+		if (operation_mode == AD405X_SLEEP_MODE_OP) {
+			ret = ad405x_reg_write_byte(dev, AD405X_REG_DEVICE_CONFIG,
+						AD405X_ENTER_SLEEP_MODE);
+			if (ret != 0) {
+				return ret;
+			}
+		} else {
+			/* Set Operation mode. */
+			ret = ad405x_reg_update_bits(dev, AD405X_REG_ADC_MODES,
+						  AD405X_ADC_MODES_MSK, operation_mode);
+			if (ret != 0) {
+				return ret;
+			}
+			/* Enter ADC_MODE. */
+			ret = ad405x_reg_update_bits(dev, AD405X_REG_MODE_SET,
+						     AD405X_ENTER_ADC_MODE_MSK,
+						     AD405X_ENTER_ADC_MODE);
+			if (ret != 0) {
+				return ret;
+			}
+		}
+	} else {
+		ret = ad405x_exit_command(dev);
+		if (ret != 0) {
+			return ret;
+		};
+		if (operation_mode == AD405X_SLEEP_MODE_OP) {
+			ret = ad405x_reg_write_byte(dev, AD405X_REG_DEVICE_CONFIG,
+						AD405X_ENTER_SLEEP_MODE);
+			if (ret != 0) {
+				return ret;
+			}
+		} else if (operation_mode != AD405X_CONFIG_MODE_OP) {
+			ret = ad405x_reg_update_bits(dev, AD405X_REG_ADC_MODES,
+						AD405X_ADC_MODES_MSK, operation_mode);
+			if (ret != 0) {
+				return ret;
+			}
+			/* Enter ADC_MODE. */
+			ret = ad405x_reg_update_bits(dev, AD405X_REG_MODE_SET,
+						     AD405X_ENTER_ADC_MODE_MSK,
+						     AD405X_ENTER_ADC_MODE);
+			if (ret != 0) {
+				return ret;
+			}
+		}
+	}
+	data->operation_mode = operation_mode;
+	return 0;
+}
+
+#if CONFIG_AD405X_TRIGGER
+int ad405x_set_gpx_mode(const struct device *dev, uint8_t gp0_1, enum ad405x_gpx_mode gpx_mode)
+{
+	const struct adc_ad405x_config *cfg = dev->config;
+	struct adc_ad405x_data *data = dev->data;
+	uint8_t mask = AD405X_GP1_MODE_MSK;
+	int ret;
+	enum ad405x_gpx_mode gpx_mode_tmp = gpx_mode;
+
+	if (gp0_1 == AD405X_GP0) {
+		mask = AD405X_GP0_MODE_MSK;
+		if (gpx_mode == AD405X_DEV_READY) {
+			return -EINVAL;
+		}
+	} else {
+		gpx_mode_tmp = gpx_mode_tmp << 4;
+	}
+
+	ret = ad405x_reg_update_bits(dev, AD405X_REG_GP_PIN_CONF, mask, gpx_mode_tmp);
+
+	if (ret == 0) {
+		if (gp0_1 == AD405X_GP0) {
+			if (gpx_mode == AD405X_DATA_READY) {
+				gpio_pin_interrupt_configure_dt(&cfg->gp0_interrupt,
+								GPIO_INT_EDGE_TO_INACTIVE);
+			}
+			data->gp0_mode = gpx_mode;
+		} else {
+			if (gpx_mode == AD405X_DATA_READY) {
+				gpio_pin_interrupt_configure_dt(&cfg->gp1_interrupt,
+								GPIO_INT_EDGE_TO_INACTIVE);
+			}
+			data->gp1_mode = gpx_mode;
+		}
+	}
+	return ret;
+}
+#endif
+
+static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
+{
+	struct adc_ad405x_data *data = CONTAINER_OF(ctx, struct adc_ad405x_data, ctx);
+
+	if (repeat_sampling) {
+		data->buffer = data->repeat_buffer;
+	}
+}
+
+static int adc_ad405x_start_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+	const struct adc_ad405x_config *cfg = dev->config;
+	struct adc_ad405x_data *data = dev->data;
+	int ret;
+
+	if (cfg->chip_id == AD4050_CHIP_ID) {
+		if (sequence->resolution != cfg->spec.resolution) {
+			LOG_ERR("invalid resolution %d", sequence->resolution);
+			return -EINVAL;
+		}
+	}
+	if (cfg->chip_id == AD4052_CHIP_ID) {
+		if (sequence->resolution != cfg->spec.resolution) {
+			LOG_ERR("invalid resolution %d", sequence->resolution);
+			return -EINVAL;
+		}
+	}
+
+	ret = adc_ad405x_validate_buffer_size(dev, sequence);
+	if (ret < 0) {
+		LOG_ERR("insufficient buffer size");
+		return ret;
+	}
+
+	ad405x_set_operation_mode(dev, cfg->active_mode);
+
+	data->buffer = sequence->buffer;
+	adc_context_start_read(&data->ctx, sequence);
+
+	return adc_context_wait_for_completion(&data->ctx);
+}
+
+static int adc_ad405x_read_async(const struct device *dev, const struct adc_sequence *sequence,
+				struct k_poll_signal *async)
+{
+	struct adc_ad405x_data *data = dev->data;
+	int ret;
+
+	adc_context_lock(&data->ctx, async ? true : false, async);
+	ret = adc_ad405x_start_read(dev, sequence);
+	adc_context_release(&data->ctx, ret);
+
+	return ret;
+}
+
+static int ad405x_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+	return adc_ad405x_read_async(dev, sequence, NULL);
+}
+
+static inline bool adc_ad405x_bus_is_ready(const struct device *dev)
+{
+	const struct adc_ad405x_config *cfg = dev->config;
+
+	return ad405x_bus_is_ready_spi(&cfg->bus);
+}
+
+int ad405x_soft_reset(const struct device *dev)
+{
+	int ret;
+
+	ret = ad405x_reg_update_bits(dev, AD405X_REG_INTERFACE_CONFIG_A, AD405X_SW_RESET_MSK,
+					AD405X_REG_INTERFACE_CONFIG_A_RESET_VAL);
+	if (ret < 0) {
+		return ret;
+	}
+
+	return ad405x_reg_update_bits(dev, AD405X_REG_INTERFACE_CONFIG_A, AD405X_SW_RESET_MSK, 0);
+}
+
+static int adc_ad405x_init(const struct device *dev)
+{
+	const struct adc_ad405x_config *cfg = dev->config;
+	struct adc_ad405x_data *data = dev->data;
+	int ret;
+	uint8_t reg_val;
+	uint8_t reg_val_hi;
+	uint16_t reg_val_res;
+
+	if (!adc_ad405x_bus_is_ready(dev)) {
+		LOG_ERR("bus not ready");
+		return -ENODEV;
+	}
+
+#if CONFIG_AD405X_TRIGGER
+	ret = ad405x_init_interrupt(dev);
+	if (ret != 0) {
+		LOG_ERR("Failed to initialize interrupt!");
+		return -EIO;
+	}
+#else
+	data->gp0_mode = AD405X_DISABLED;
+#endif
+	ad405x_init_conv(dev);
+	data->gp1_mode = AD405X_DEV_READY;
+	data->operation_mode = AD405X_CONFIG_MODE_OP;
+	data->filter_length = AD405X_LENGTH_2;
+	k_sem_init(&data->sem_devrdy, 0, 1);
+	adc_context_init(&data->ctx);
+
+	/* Reset */
+	ret = ad405x_reset_pattern_cmd(dev);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = ad405x_reg_read_byte(dev, AD405X_REG_PRODUCT_ID_L, &reg_val);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = ad405x_reg_read_byte(dev, AD405X_REG_PRODUCT_ID_H, &reg_val_hi);
+	if (ret < 0) {
+		return ret;
+	}
+
+	reg_val_res = (reg_val_hi << 8) | reg_val;
+	if ((reg_val_res != AD4052_REG_PRODUCT_ID_VAL) &
+	    (reg_val_res != AD4050_REG_PRODUCT_ID_VAL)) {
+		LOG_ERR("Invalid product id");
+		return -ENODEV;
+	}
+
+	ret = ad405x_reg_read_byte(dev, AD405X_REG_DEVICE_TYPE, &reg_val);
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (reg_val != AD405X_REG_DEVICE_TYPE_VAL) {
+		LOG_ERR("Invalid device type");
+		return -ENODEV;
+	}
+
+	ret = ad405x_reg_read_byte(dev, AD405X_REG_VENDOR_L, &reg_val);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = ad405x_reg_read_byte(dev, AD405X_REG_VENDOR_H, &reg_val_hi);
+	if (ret < 0) {
+		return ret;
+	}
+
+	reg_val_res = (reg_val_hi << 8) | reg_val;
+	if (reg_val_res != AD405X_REG_VENDOR_VAL) {
+		LOG_ERR("Invalid vendor value");
+		return -ENODEV;
+	}
+
+	if (cfg->chip_id == AD4050_CHIP_ID) {
+		if (cfg->spec.resolution != AD4050_ADC_RESOLUTION) {
+			LOG_ERR("Invalid resolution %d", cfg->spec.resolution);
+			return -EINVAL;
+		}
+	} else {
+		if (cfg->spec.resolution != AD4052_ADC_RESOLUTION) {
+			LOG_ERR("Invalid resolution %d", cfg->spec.resolution);
+			return -EINVAL;
+		}
+	}
+
+#if CONFIG_AD405X_TRIGGER
+	if (cfg->has_gp1 != 0) {
+		ad405x_set_gpx_mode(dev, AD405X_GP1, AD405X_DATA_READY);
+		k_sem_init(&data->sem_drdy, 0, 1);
+		data->has_drdy = 1;
+	}
+#endif
+
+	adc_context_unlock_unconditionally(&data->ctx);
+	data->dev = dev;
+	return ret;
+}
+
+static DEVICE_API(adc, ad405x_api_funcs) = {
+	.channel_setup = ad405x_channel_setup,
+	.read = ad405x_read,
+	.ref_internal = 2500,
+#ifdef CONFIG_ADC_ASYNC
+	.read_async = ad405x_adc_read_async,
+#endif
+};
+
+#define AD405X_SPI_CFG SPI_WORD_SET(8) | SPI_TRANSFER_MSB
+
+#define DT_INST_AD405X(inst, t) DT_INST(inst, adi_ad##t##_adc)
+
+#define AD405X_GPIO_PROPS1(n)                                                                    \
+	.gp1_interrupt = GPIO_DT_SPEC_INST_GET_OR(n, gp1_gpios, {0}),                            \
+	.has_gp1 = 1,                                                                            \
+
+#define AD405X_GPIO_PROPS0(n)                                                                    \
+	.gp0_interrupt = GPIO_DT_SPEC_INST_GET_OR(n, gp0_gpios, {0}),                            \
+	.has_gp0 = 1,                                                                            \
+
+#define AD405X_GPIO(t, n)                                                                        \
+	IF_ENABLED(DT_NODE_HAS_PROP(DT_INST_AD405X(n, t), gp1_gpios),                            \
+		   (AD405X_GPIO_PROPS1(n)))                                                      \
+	IF_ENABLED(DT_NODE_HAS_PROP(DT_INST_AD405X(n, t), gp0_gpios),                            \
+		   (AD405X_GPIO_PROPS0(n)))
+
+#define AD405X_INIT(t, n) \
+	static struct adc_ad405x_data ad##t##_data_##n = {};                                     \
+	static const struct adc_ad405x_config ad##t##_config_##n =  {                            \
+		.bus = {.spi = SPI_DT_SPEC_GET(DT_INST_AD405X(n, t), AD405X_SPI_CFG, 0)},        \
+		.conversion = GPIO_DT_SPEC_GET_BY_IDX(DT_INST_AD405X(n, t), conversion_gpios, 0),\
+		IF_ENABLED(CONFIG_AD405X_TRIGGER, (AD405X_GPIO(t, n)))                           \
+		.chip_id = t,                                                                    \
+		.active_mode = AD405X_SAMPLE_MODE_OP,                                            \
+		.spec = ADC_DT_SPEC_STRUCT(DT_INST(n, DT_DRV_COMPAT), 0)                         \
+		};                                                                               \
+	DEVICE_DT_DEFINE(DT_INST_AD405X(n, t), adc_ad405x_init, NULL, &ad##t##_data_##n,         \
+			&ad##t##_config_##n, POST_KERNEL,                                        \
+			CONFIG_ADC_INIT_PRIORITY, &ad405x_api_funcs);
+
+/*
+ * AD4052: 16 bit
+ */
+#define AD4052_INIT(n) AD405X_INIT(AD4052_CHIP_ID, n)
+#undef DT_DRV_COMPAT
+#define DT_DRV_COMPAT adi_ad4052_adc
+DT_INST_FOREACH_STATUS_OKAY(AD4052_INIT)
+
+/*
+ * AD4050: 12 bit
+ */
+#define AD4050_INIT(n) AD405X_INIT(AD4050_CHIP_ID, n)
+#undef DT_DRV_COMPAT
+#define DT_DRV_COMPAT adi_ad4050_adc
+DT_INST_FOREACH_STATUS_OKAY(AD4050_INIT)
diff --git a/drivers/adc/adc_ad4114.c b/drivers/adc/adc_ad4114.c
new file mode 100644
index 00000000000..7623b22761b
--- /dev/null
+++ b/drivers/adc/adc_ad4114.c
@@ -0,0 +1,452 @@
+/*
+ * Copyright (c) 2024 Pierrick Curt
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util.h>
+
+#define ADC_CONTEXT_USES_KERNEL_TIMER
+#include "adc_context.h"
+
+LOG_MODULE_REGISTER(ADC_AD4114, CONFIG_ADC_LOG_LEVEL);
+
+#define DT_DRV_COMPAT adi_ad4114_adc
+
+#define AD4114_CMD_READ       0x40
+#define AD4114_CMD_WRITE      0x0
+#define AD4114_CHAN_NUMBER    16
+#define AD4114_ADC_RESOLUTION 24U
+
+enum ad4114_reg {
+	AD4114_STATUS_REG = 0x00,
+	AD4114_MODE_REG = 0x01,
+	AD4114_IFMODE_REG = 0x02,
+	AD4114_REGCHECK = 0x03,
+	AD4114_DATA_REG = 0x04,
+	AD4114_GPIOCON_REG = 0x06,
+	AD4114_ID_REG = 0x07,
+	AD4114_CHANNEL_0_REG = 0x10,
+	AD4114_CHANNEL_1_REG = 0x11,
+	AD4114_CHANNEL_2_REG = 0x12,
+	AD4114_CHANNEL_3_REG = 0x13,
+	AD4114_CHANNEL_4_REG = 0x14,
+	AD4114_CHANNEL_5_REG = 0x15,
+	AD4114_CHANNEL_6_REG = 0x16,
+	AD4114_CHANNEL_7_REG = 0x17,
+	AD4114_CHANNEL_8_REG = 0x18,
+	AD4114_CHANNEL_9_REG = 0x19,
+	AD4114_CHANNEL_10_REG = 0x1A,
+	AD4114_CHANNEL_11_REG = 0x1B,
+	AD4114_CHANNEL_12_REG = 0x1C,
+	AD4114_CHANNEL_13_REG = 0x1D,
+	AD4114_CHANNEL_14_REG = 0x1E,
+	AD4114_CHANNEL_15_REG = 0x1F,
+	AD4114_SETUPCON0_REG = 0x20,
+	AD4114_SETUPCON1_REG = 0x21,
+	AD4114_SETUPCON2_REG = 0x22,
+	AD4114_SETUPCON3_REG = 0x23,
+	AD4114_SETUPCON4_REG = 0x24,
+	AD4114_SETUPCON5_REG = 0x25,
+	AD4114_SETUPCON6_REG = 0x26,
+	AD4114_SETUPCON7_REG = 0x27,
+	AD4114_FILTCON0_REG = 0x28,
+	AD4114_FILTCON1_REG = 0x29,
+	AD4114_FILTCON2_REG = 0x2A,
+	AD4114_FILTCON3_REG = 0x2B,
+	AD4114_FILTCON4_REG = 0x2C,
+	AD4114_FILTCON5_REG = 0x2D,
+	AD4114_FILTCON6_REG = 0x2E,
+	AD4114_FILTCON7_REG = 0x2F,
+	AD4114_OFFSET0_REG = 0x30,
+	AD4114_OFFSET1_REG = 0x31,
+	AD4114_OFFSET2_REG = 0x32,
+	AD4114_OFFSET3_REG = 0x33,
+	AD4114_OFFSET4_REG = 0x34,
+	AD4114_OFFSET5_REG = 0x35,
+	AD4114_OFFSET6_REG = 0x36,
+	AD4114_OFFSET7_REG = 0x37,
+	AD4114_GAIN0_REG = 0x38,
+	AD4114_GAIN1_REG = 0x39,
+	AD4114_GAIN2_REG = 0x3A,
+	AD4114_GAIN3_REG = 0x3B,
+	AD4114_GAIN4_REG = 0x3C,
+	AD4114_GAIN5_REG = 0x3D,
+	AD4114_GAIN6_REG = 0x3E,
+	AD4114_GAIN7_REG = 0x3F,
+};
+
+struct adc_ad4114_config {
+	struct spi_dt_spec spi;
+	uint16_t resolution;
+	uint16_t map_input[AD4114_CHAN_NUMBER];
+};
+
+struct adc_ad4114_data {
+	struct adc_context ctx;
+	const struct device *dev;
+	struct k_thread thread;
+	struct k_sem sem;
+	uint16_t channels;
+	uint16_t channels_cfg;
+	uint32_t *buffer;
+	uint32_t *repeat_buffer;
+
+	K_KERNEL_STACK_MEMBER(stack, CONFIG_ADC_AD4114_ACQUISITION_THREAD_STACK_SIZE);
+};
+
+static int ad4114_write_reg(const struct device *dev, enum ad4114_reg reg_addr, uint8_t *buffer,
+			    size_t reg_size)
+{
+	int ret;
+	const struct adc_ad4114_config *config = dev->config;
+	uint8_t buffer_tx[5] = {0}; /* One byte command, max 4 bytes data */
+
+	const struct spi_buf tx_buf[] = {{
+		.buf = buffer_tx,
+		.len = ARRAY_SIZE(buffer_tx),
+	}};
+	const struct spi_buf_set tx = {
+		.buffers = tx_buf,
+		.count = ARRAY_SIZE(tx_buf),
+	};
+
+	buffer_tx[0] = AD4114_CMD_WRITE | reg_addr;
+
+	if (reg_size > 4) {
+		LOG_ERR("Invalid size, max data write size is 4");
+		return -ENOMEM;
+	}
+	/* Fill the data */
+	for (uint8_t index = 0; index < reg_size; index++) {
+		buffer_tx[1 + index] = buffer[index];
+	}
+
+	ret = spi_write_dt(&config->spi, &tx);
+	if (ret != 0) {
+		LOG_ERR("%s: error writing register 0x%X (%d)", dev->name, reg_addr, ret);
+		return ret;
+	}
+
+	return ret;
+}
+
+static int ad4114_read_reg(const struct device *dev, enum ad4114_reg reg_addr, uint8_t *buffer,
+			   size_t reg_size)
+{
+	int ret;
+	const struct adc_ad4114_config *config = dev->config;
+
+	uint8_t buffer_tx[6] = {0};
+	uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)] = {0xFF};
+	const struct spi_buf tx_buf[] = {{
+		.buf = buffer_tx,
+		.len = ARRAY_SIZE(buffer_tx),
+	}};
+	const struct spi_buf rx_buf[] = {{
+		.buf = buffer_rx,
+		.len = ARRAY_SIZE(buffer_rx),
+	}};
+	const struct spi_buf_set tx = {
+		.buffers = tx_buf,
+		.count = ARRAY_SIZE(tx_buf),
+	};
+	const struct spi_buf_set rx = {
+		.buffers = rx_buf,
+		.count = ARRAY_SIZE(rx_buf),
+	};
+	buffer_tx[0] = AD4114_CMD_READ | reg_addr;
+
+	ret = spi_transceive_dt(&config->spi, &tx, &rx);
+	if (ret != 0) {
+		LOG_ERR("%s: error reading register 0x%X (%d)", dev->name, reg_addr, ret);
+		return ret;
+	}
+
+	/* Copy received data in output buffer */
+	for (uint8_t index = 0; index < reg_size; index++) {
+		buffer[index] = buffer_rx[index + 1];
+	}
+
+	return ret;
+}
+
+static void adc_context_start_sampling(struct adc_context *ctx)
+{
+	struct adc_ad4114_data *data = CONTAINER_OF(ctx, struct adc_ad4114_data, ctx);
+
+	data->channels = ctx->sequence.channels;
+	data->repeat_buffer = data->buffer;
+
+	k_sem_give(&data->sem);
+}
+
+static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
+{
+	struct adc_ad4114_data *data = CONTAINER_OF(ctx, struct adc_ad4114_data, ctx);
+
+	if (repeat_sampling) {
+		data->buffer = data->repeat_buffer;
+	}
+}
+
+static int adc_ad4114x_validate_buffer_size(const struct device *dev,
+					    const struct adc_sequence *sequence)
+{
+	uint8_t channels;
+	size_t needed;
+
+	channels = POPCOUNT(sequence->channels);
+	needed = channels * sizeof(uint32_t);
+
+	if (sequence->buffer_size < needed) {
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static int adc_ad4114_start_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+	struct adc_ad4114_data *data = dev->data;
+	const struct adc_ad4114_config *config = dev->config;
+	int ret;
+	uint8_t write_reg[2];
+	uint8_t status;
+
+	ret = adc_ad4114x_validate_buffer_size(dev, sequence);
+	if (ret < 0) {
+		LOG_ERR("insufficient buffer size");
+		return ret;
+	}
+
+	data->channels_cfg = sequence->channels;
+	for (uint32_t i = 0U; i < AD4114_CHAN_NUMBER; i++) {
+		if ((BIT(i) & sequence->channels) != 0) {
+			write_reg[0] = 0x80 | (uint8_t)((config->map_input[i] >> 8) & 0xFF);
+			write_reg[1] = (uint8_t)(config->map_input[i] & 0xFF);
+			LOG_DBG("Enable channel %d with mapping %X %X, raw %X", i, write_reg[0],
+				write_reg[1], config->map_input[i]);
+			ad4114_write_reg(dev, AD4114_CHANNEL_0_REG + i, write_reg, 2);
+		} else {
+			LOG_DBG("Disable channel %d", i);
+			write_reg[0] = 0x0;
+			write_reg[1] = 0x0;
+			ad4114_write_reg(dev, AD4114_CHANNEL_0_REG + i, write_reg, 2);
+		}
+	}
+
+	/* Configure the buffer */
+	data->buffer = sequence->buffer;
+
+	while ((status & 0x80) != 0x80) {
+		/* Wait for acquiistion start */
+		ad4114_read_reg(dev, AD4114_STATUS_REG, &status, 1);
+		/* Wait 10us between two status read */
+		k_usleep(10);
+	}
+
+	adc_context_start_read(&data->ctx, sequence);
+
+	return adc_context_wait_for_completion(&data->ctx);
+}
+
+static void adc_ad4114_acquisition_thread(struct adc_ad4114_data *data)
+{
+	uint8_t value[4] = {0};
+	uint32_t buffer_values[AD4114_CHAN_NUMBER];
+	bool is_ended = false;
+
+	while (true) {
+		k_sem_take(&data->sem, K_FOREVER);
+
+		while (data->channels != 0) {
+			ad4114_read_reg(data->dev, AD4114_DATA_REG, value, 4);
+			/* Check the read channel */
+			if ((value[3] & 0xF0) != 0) {
+				LOG_DBG("Error read on :  %X ", value[3]);
+			} else {
+				LOG_DBG("Success read on %d: value  %X ", value[3],
+					(value[2] << 16 | value[1] << 8 | value[0]));
+				/* success read, store it */
+				buffer_values[value[3]] =
+					(value[0] << 16 | value[1] << 8 | value[2]);
+				WRITE_BIT(data->channels, value[3], 0);
+				/* Disable the channel after read success */
+				uint8_t write_reg[2] = {0};
+
+				ad4114_write_reg(data->dev, AD4114_CHANNEL_0_REG + value[3],
+						 write_reg, 2);
+			}
+			if (data->channels == 0) {
+				is_ended = true;
+			}
+			/* Wait before next status ready check: the minimal acquisition time for a
+			 * channel is 100us. So wait 10us betwen each check to avoid to use CPU for
+			 * nothing.
+			 */
+			k_usleep(10);
+		}
+
+		if (is_ended) {
+			is_ended = false;
+			for (uint8_t i = 0U; i < AD4114_CHAN_NUMBER; i++) {
+				if ((BIT(i) & data->channels_cfg) != 0) {
+					*data->buffer++ = buffer_values[i];
+					LOG_DBG("Read channel %d value :  %X ", i,
+						buffer_values[i]);
+				}
+			}
+			adc_context_on_sampling_done(&data->ctx, data->dev);
+		}
+		/* Wait 1ms before checking if a new sequence acquisition is asked */
+		k_usleep(1000);
+	}
+}
+
+static int adc_ad4114_channel_setup(const struct device *dev,
+				    const struct adc_channel_cfg *channel_cfg)
+{
+
+	/* Todo in the futur we can manage here :
+	 * filters
+	 * gain
+	 * offsets
+	 * special configuration : we can update map_input here to override the device
+	 * tree setup
+	 */
+	if (channel_cfg->channel_id >= AD4114_CHAN_NUMBER) {
+		LOG_ERR("invalid channel id %d", channel_cfg->channel_id);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int adc_ad4114_read_async(const struct device *dev, const struct adc_sequence *sequence,
+				 struct k_poll_signal *async)
+{
+	struct adc_ad4114_data *data = dev->data;
+	int ret;
+
+	adc_context_lock(&data->ctx, async ? true : false, async);
+	ret = adc_ad4114_start_read(dev, sequence);
+	adc_context_release(&data->ctx, ret);
+
+	return ret;
+}
+
+static int adc_ad4114_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+	return adc_ad4114_read_async(dev, sequence, NULL);
+}
+
+static int adc_ad4114_init(const struct device *dev)
+{
+	int err;
+	const struct adc_ad4114_config *config = dev->config;
+	struct adc_ad4114_data *data = dev->data;
+	uint8_t id[2] = {0};
+	uint8_t gain[3];
+	uint8_t write_reg[2];
+	uint8_t status = 0;
+	k_tid_t tid;
+
+	data->dev = dev;
+	k_sem_init(&data->sem, 0, 1);
+	adc_context_init(&data->ctx);
+
+	if (!spi_is_ready_dt(&config->spi)) {
+		LOG_ERR("spi bus %s not ready", config->spi.bus->name);
+		return -ENODEV;
+	}
+
+	ad4114_read_reg(dev, AD4114_ID_REG, id, 2);
+	/* Check that this is the expected ID : 0x30DX, where x is don’t care */
+	if ((((id[0] << 8) | id[1]) & 0xFFF0) != 0x30D0) {
+		LOG_ERR("Read wrong ID register 0x%X 0x%X", id[0], id[1]);
+		return -EIO;
+	}
+
+	ad4114_read_reg(dev, AD4114_STATUS_REG, &status, 1);
+	LOG_INF("Found AD4114 with status %d", status);
+
+	/* Configure gain to 0x400000 */
+	gain[0] = 0x40;
+	gain[1] = 0x00;
+	gain[2] = 0x00;
+	ad4114_write_reg(dev, AD4114_GAIN0_REG, gain, 3);
+	ad4114_write_reg(dev, AD4114_GAIN1_REG, gain, 3);
+
+	/* Bit 6: DATA_STAT = 1 */
+	write_reg[0] = 0x0;
+	write_reg[1] = 0x40;
+	ad4114_write_reg(dev, AD4114_IFMODE_REG, write_reg, 2);
+
+	/* Bit 12: BI_UNIPOLARx = 0
+	 * Bit 9:8 INBUFx = 11
+	 */
+	write_reg[0] = 0x3;
+	write_reg[1] = 0x0;
+	ad4114_write_reg(dev, AD4114_SETUPCON0_REG, write_reg, 2);
+
+	/* Bit 12: BI_UNIPOLARx = 1
+	 * Bit 9:8 INBUFx = 11
+	 */
+	write_reg[0] = 0x13;
+	write_reg[1] = 0x0;
+	ad4114_write_reg(dev, AD4114_SETUPCON1_REG, write_reg, 2);
+
+	/* Bit 15: REF_EN = 1
+	 * Bit 3:2: CLOCKSEL = 11
+	 */
+	write_reg[0] = 0x80;
+	write_reg[1] = 0xC;
+	ad4114_write_reg(dev, AD4114_MODE_REG, write_reg, 2);
+
+	tid = k_thread_create(&data->thread, data->stack, K_KERNEL_STACK_SIZEOF(data->stack),
+			      (k_thread_entry_t)adc_ad4114_acquisition_thread, data, NULL, NULL,
+			      CONFIG_ADC_AD4114_ACQUISITION_THREAD_PRIO, 0, K_NO_WAIT);
+
+	if (IS_ENABLED(CONFIG_THREAD_NAME)) {
+		err = k_thread_name_set(tid, "adc_ad4114");
+		if (err < 0) {
+			return err;
+		}
+	}
+
+	adc_context_unlock_unconditionally(&data->ctx);
+	return 0;
+}
+
+static DEVICE_API(adc, adc_ad4114_api) = {
+	.channel_setup = adc_ad4114_channel_setup,
+	.read = adc_ad4114_read,
+};
+
+#define FILL_MAP_INPUTS(node_id, prop, idx)                                                        \
+	{                                                                                          \
+		.key_index = DT_NODE_CHILD_IDX(node_id),                                           \
+		.press_mv = DT_PROP_BY_IDX(node_id, prop, idx),                                    \
+	}
+
+#define ADC_AD4114_DEVICE(inst)                                                                    \
+	static struct adc_ad4114_data adc_ad4114_data_##inst;                                      \
+	static const struct adc_ad4114_config adc_ad4114_config_##inst = {                         \
+		.spi = SPI_DT_SPEC_INST_GET(inst, SPI_WORD_SET(8), 0),                             \
+		.resolution = AD4114_ADC_RESOLUTION,                                               \
+		.map_input = DT_INST_PROP(inst, map_inputs),                                       \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(inst, adc_ad4114_init, NULL, &adc_ad4114_data_##inst,                \
+			      &adc_ad4114_config_##inst, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY,    \
+			      &adc_ad4114_api)                                                     \
+	BUILD_ASSERT(DT_INST_PROP_LEN(inst, map_inputs) == AD4114_CHAN_NUMBER);
+
+DT_INST_FOREACH_STATUS_OKAY(ADC_AD4114_DEVICE)
diff --git a/drivers/adc/adc_ad4130.c b/drivers/adc/adc_ad4130.c
new file mode 100644
index 00000000000..1c74efd01a0
--- /dev/null
+++ b/drivers/adc/adc_ad4130.c
@@ -0,0 +1,1071 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT adi_ad4130_adc
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/byteorder.h>
+
+LOG_MODULE_REGISTER(adc_ad4130, CONFIG_ADC_LOG_LEVEL);
+
+#define ADC_CONTEXT_USES_KERNEL_TIMER
+#include "adc_context.h"
+
+/* ---------------------------------------
+ * AD4130 Register Addresses
+ * ---------------------------------------
+ */
+
+#define AD4130_STATUS_REG       0x00
+#define AD4130_ADC_CONTROL_REG  0x01
+#define AD4130_DATA_REG         0x02
+#define AD4130_IO_CONTROL_REG   0x03
+#define AD4130_VBIAS_REG        0x04
+#define AD4130_ID_REG           0x05
+#define AD4130_ERROR_REG        0x06
+#define AD4130_ERROR_EN_REG     0x07
+#define AD4130_MCLK_COUNT_REG   0x08
+#define AD4130_CHANNEL_X_REG(x) (0x09 + (x))
+#define AD4130_CONFIG_X_REG(x)  (0x19 + (x))
+#define AD4130_FILTER_X_REG(x)  (0x21 + (x))
+
+/* ---------------------------------------
+ * AD4130 Status Flags and Bit Masks
+ * ---------------------------------------
+ */
+
+#define AD4130_STATUS_REG_DATA_READY BIT(7)
+#define AD4130_COMMS_READ_MASK       BIT(6)
+
+/* ---------------------------------------
+ * AD4130 ADC Control Bit Masks
+ * ---------------------------------------
+ */
+
+#define AD4130_ADC_CONTROL_BIPOLAR_MASK     BIT(14)
+#define AD4130_ADC_CONTROL_INT_REF_VAL_MASK BIT(13)
+#define AD4130_ADC_CONTROL_CSB_EN_MASK      BIT(9)
+#define AD4130_ADC_CONTROL_INT_REF_EN_MASK  BIT(8)
+#define AD4130_ADC_CONTROL_MODE_MASK        GENMASK(5, 2)
+#define AD4130_ADC_CONTROL_MCLK_SEL_MASK    GENMASK(1, 0)
+
+/* ---------------------------------------
+ * AD4130 Channel Configuration Bit Masks
+ * ---------------------------------------
+ */
+
+#define AD4130_CHANNEL_EN_MASK    BIT(23)
+#define AD4130_CHANNEL_SETUP_MASK GENMASK(22, 20)
+#define AD4130_CHANNEL_AINP_MASK  GENMASK(17, 13)
+#define AD4130_CHANNEL_AINM_MASK  GENMASK(12, 8)
+
+/* ---------------------------------------
+ * AD4130 Configuration Register Bit Masks
+ * ---------------------------------------
+ */
+
+#define AD4130_CONFIG_REF_SEL_MASK GENMASK(5, 4)
+#define AD4130_CONFIG_PGA_MASK     GENMASK(3, 1)
+
+/* ---------------------------------------
+ * AD4130 Device-Specific Parameters
+ * ---------------------------------------
+ */
+
+#define AD4130_MAX_CHANNELS 16
+#define AD4130_MAX_SETUPS   8
+
+/* ---------------------------------------
+ * AD4130 Reset Parameters
+ * ---------------------------------------
+ */
+
+#define AD4130_RESET_BUF_SIZE 8
+#define AD4130_RESET_SLEEP_MS (160 * 1000 / AD4130_MCLK_FREQ_76_8KHZ)
+
+/* ---------------------------------------
+ * AD4130 Error Values
+ * ---------------------------------------
+ */
+
+#define AD4130_INVALID_CHANNEL -1
+#define AD4130_INVALID_SLOT    -1
+
+/* ---------------------------------------
+ * AD4130 Electrical Characteristics
+ * ---------------------------------------
+ */
+
+#define AD4130_INT_REF_2_5V      2500U
+#define AD4130_ADC_RESOLUTION    24
+#define AD4130_MCLK_FREQ_76_8KHZ 76800
+
+/* ---------------------------------------
+ * AD4130-8 Identification
+ * ---------------------------------------
+ */
+
+#define AD4130_8_ID 0x04 /* AD4130-8 Device ID */
+
+static const unsigned int ad4130_reg_size[] = {
+	[AD4130_STATUS_REG] = 1,
+	[AD4130_ADC_CONTROL_REG] = 2,
+	[AD4130_DATA_REG] = 3,
+	[AD4130_VBIAS_REG] = 2,
+	[AD4130_ID_REG] = 1,
+	[AD4130_CHANNEL_X_REG(0)... AD4130_CHANNEL_X_REG(AD4130_MAX_CHANNELS - 1)] = 3,
+	[AD4130_CONFIG_X_REG(0)... AD4130_CONFIG_X_REG(AD4130_MAX_SETUPS - 1)] = 2,
+	[AD4130_FILTER_X_REG(0)... AD4130_FILTER_X_REG(AD4130_MAX_SETUPS - 1)] = 3,
+};
+
+enum ad4130_input {
+	AD4130_AIN0,
+	AD4130_AIN1,
+	AD4130_AIN2,
+	AD4130_AIN3,
+	AD4130_AIN4,
+	AD4130_AIN5,
+	AD4130_AIN6,
+	AD4130_AIN7,
+	AD4130_AIN8,
+	AD4130_AIN9,
+	AD4130_AIN10,
+	AD4130_AIN11,
+	AD4130_AIN12,
+	AD4130_AIN13,
+	AD4130_AIN14,
+	AD4130_AIN15,
+	AD4130_TEMP,
+	AD4130_AVSS,
+	AD4130_INT_REF,
+	AD4130_DGND,
+	AD4130_AVDD_AVSS_6P,
+	AD4130_AVDD_AVSS_6M,
+	AD4130_IOVDD_DGND_6P,
+	AD4130_IOVDD_DGND_6M,
+	AD4130_ALDO_AVSS_6P,
+	AD4130_ALDO_AVSS_6M,
+	AD4130_DLDO_DGND_6P,
+	AD4130_DLDO_DGND_6M,
+	AD4130_V_MV_P,
+	AD4130_V_MV_M,
+};
+
+enum ad4130_int_ref {
+	AD4130_INT_REF_VAL_2_5V,
+	AD4130_INT_REF_VAL_1_25V,
+};
+
+enum ad4130_setup {
+	AD4130_SETUP_0,
+	AD4130_SETUP_1,
+	AD4130_SETUP_2,
+	AD4130_SETUP_3,
+	AD4130_SETUP_4,
+	AD4130_SETUP_5,
+	AD4130_SETUP_6,
+	AD4130_SETUP_7
+};
+
+enum ad4130_mclk_sel {
+	AD4130_MCLK_76_8KHZ,
+	AD4130_MCLK_76_8KHZ_OUT,
+	AD4130_MCLK_76_8KHZ_EXT,
+	AD4130_MCLK_153_6KHZ_EXT,
+};
+
+enum ad4130_ref_sel {
+	AD4130_REF_REFIN1,
+	AD4130_REF_REFIN2,
+	AD4130_REF_REFOUT_AVSS,
+	AD4130_REF_AVDD_AVSS,
+	AD4130_REF_SEL_MAX
+};
+
+enum ad4130_adc_mode {
+	AD4130_MODE_CONTINUOUS = 0b0000,
+	AD4130_STANDBY_MODE = 0b0010,
+	AD4130_MODE_IDLE = 0b0100,
+};
+
+enum ad4130_gain {
+	AD4130_GAIN_1,
+	AD4130_GAIN_2,
+	AD4130_GAIN_4,
+	AD4130_GAIN_8,
+	AD4130_GAIN_16,
+	AD4130_GAIN_32,
+	AD4130_GAIN_64,
+	AD4130_GAIN_128,
+};
+
+struct ad4130_config_props {
+	enum ad4130_ref_sel ref_sel;
+	enum ad4130_gain gain;
+};
+
+struct ad4130_channel_config {
+	struct ad4130_config_props props;
+	uint8_t cfg_slot;
+	bool live_cfg;
+};
+
+struct ad4130_config {
+	struct spi_dt_spec bus;
+	uint8_t resolution;
+	bool bipolar;
+	enum ad4130_int_ref int_ref;
+	enum ad4130_adc_mode adc_mode;
+	enum ad4130_mclk_sel mclk_sel;
+};
+
+struct adc_ad4130_data {
+	const struct device *dev;
+	struct adc_context ctx;
+	struct ad4130_channel_config channel_setup_cfg[AD4130_MAX_SETUPS];
+	uint8_t setup_cfg_slots;
+	struct k_sem acquire_signal;
+	uint16_t channels;
+	uint32_t *buffer;
+	uint32_t *repeat_buffer;
+#if CONFIG_ADC_ASYNC
+	struct k_thread thread;
+
+	K_KERNEL_STACK_MEMBER(stack, CONFIG_ADI_AD4130_ADC_ACQUISITION_THREAD_STACK_SIZE);
+#endif /* CONFIG_ADC_ASYNC */
+};
+
+static size_t ad4130_get_reg_size(unsigned int reg_addr, size_t *reg_size)
+{
+	if (reg_addr >= ARRAY_SIZE(ad4130_reg_size)) {
+		return -EINVAL;
+	}
+
+	*reg_size = ad4130_reg_size[reg_addr];
+	return 0;
+}
+
+static int ad4130_reg_write(const struct device *dev, unsigned int reg_addr, unsigned int val)
+{
+	const struct ad4130_config *config = dev->config;
+	const struct spi_dt_spec *spec = &config->bus;
+
+	uint8_t reg_write_tx_buf[4] = {0};
+	size_t reg_size = 0;
+	int ret;
+
+	ret = ad4130_get_reg_size(reg_addr, &reg_size);
+	if (ret) {
+		return ret;
+	}
+
+	reg_write_tx_buf[0] = reg_addr;
+
+	switch (reg_size) {
+	case 1:
+		reg_write_tx_buf[1] = val;
+		break;
+	case 2:
+		sys_put_be16(val, &reg_write_tx_buf[1]);
+		break;
+	case 3:
+		sys_put_be24(val, &reg_write_tx_buf[1]);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	const struct spi_buf tx_buf = {.buf = reg_write_tx_buf, .len = reg_size + 1};
+	const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1};
+
+	return spi_write_dt(spec, &tx);
+}
+
+static int ad4130_reg_read(const struct device *dev, unsigned int reg_addr, unsigned int *val)
+{
+	const struct ad4130_config *config = dev->config;
+	const struct spi_dt_spec *spec = &config->bus;
+	int ret;
+
+	uint8_t reg_read_tx_buf[1] = {AD4130_COMMS_READ_MASK | reg_addr};
+	uint8_t reg_read_rx_buf[4] = {0};
+	size_t reg_size = 0;
+
+	ret = ad4130_get_reg_size(reg_addr, &reg_size);
+	if (ret) {
+		return ret;
+	}
+
+	const struct spi_buf tx_buf = {.buf = reg_read_tx_buf, .len = 1};
+	const struct spi_buf rx_buf = {.buf = reg_read_rx_buf, .len = reg_size + 1};
+	const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1};
+	const struct spi_buf_set rx = {.buffers = &rx_buf, .count = 1};
+
+	ret = spi_transceive_dt(spec, &tx, &rx);
+	if (ret) {
+		return ret;
+	}
+
+	switch (reg_size) {
+	case 1:
+		*val = reg_read_rx_buf[1];
+		break;
+	case 2:
+		*val = sys_get_be16(&reg_read_rx_buf[1]);
+		break;
+	case 3:
+		*val = sys_get_be24(&reg_read_rx_buf[1]);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int ad4130_reg_write_msk(const struct device *dev, unsigned int reg_addr, unsigned int data,
+				unsigned int mask)
+{
+	uint32_t reg_data;
+	int ret;
+
+	ret = ad4130_reg_read(dev, reg_addr, &reg_data);
+	if (ret) {
+		return ret;
+	}
+
+	reg_data &= ~mask;
+	reg_data |= data;
+
+	return ad4130_reg_write(dev, reg_addr, reg_data);
+}
+
+static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
+{
+	struct adc_ad4130_data *data = CONTAINER_OF(ctx, struct adc_ad4130_data, ctx);
+
+	if (repeat_sampling) {
+		data->buffer = data->repeat_buffer;
+	}
+}
+
+static void adc_context_start_sampling(struct adc_context *ctx)
+{
+	struct adc_ad4130_data *data = CONTAINER_OF(ctx, struct adc_ad4130_data, ctx);
+
+	data->repeat_buffer = data->buffer;
+	k_sem_give(&data->acquire_signal);
+}
+
+static int adc_ad4130_set_ref(const struct device *dev, enum ad4130_ref_sel ref,
+			      enum ad4130_setup setup_id)
+{
+	bool internal_reference;
+	int ret;
+
+	if (ref == AD4130_REF_REFOUT_AVSS) {
+		internal_reference = true;
+	} else {
+		internal_reference = false;
+	}
+
+	ret = ad4130_reg_write_msk(
+		dev, AD4130_ADC_CONTROL_REG,
+		FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_EN_MASK, internal_reference),
+		AD4130_ADC_CONTROL_INT_REF_EN_MASK);
+	if (ret) {
+		return ret;
+	}
+
+	return ad4130_reg_write_msk(dev, AD4130_CONFIG_X_REG(setup_id),
+				    FIELD_PREP(AD4130_CONFIG_REF_SEL_MASK, ref),
+				    AD4130_CONFIG_REF_SEL_MASK);
+}
+
+static int adc_ad4130_set_gain(const struct device *dev, enum ad4130_gain gain,
+			       enum ad4130_setup setup_id)
+{
+	return ad4130_reg_write_msk(dev, AD4130_CONFIG_X_REG(setup_id),
+				    FIELD_PREP(AD4130_CONFIG_PGA_MASK, gain),
+				    AD4130_CONFIG_PGA_MASK);
+}
+
+static int adc_ad4130_setup_cfg(const struct device *dev, const struct ad4130_channel_config *cfg)
+{
+	int ret;
+
+	ret = adc_ad4130_set_ref(dev, cfg->props.ref_sel, cfg->cfg_slot);
+	if (ret) {
+		return ret;
+	}
+
+	ret = adc_ad4130_set_gain(dev, cfg->props.gain, cfg->cfg_slot);
+	if (ret) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static int adc_ad4130_find_similar_configuration(const struct device *dev,
+						 const struct ad4130_channel_config *cfg,
+						 uint8_t channel_id)
+{
+	struct adc_ad4130_data *data = dev->data;
+	int similar_channel_index = AD4130_INVALID_CHANNEL;
+
+	for (int i = 0; i < AD4130_MAX_CHANNELS; i++) {
+		if (!data->channel_setup_cfg[i].live_cfg && i == channel_id) {
+			continue;
+		}
+
+		if (memcmp(&cfg->props, &data->channel_setup_cfg[i].props,
+			   sizeof(struct ad4130_config_props)) == 0) {
+			similar_channel_index = i;
+			break;
+		}
+	}
+
+	return similar_channel_index;
+}
+
+static int adc_ad4130_find_new_slot(const struct device *dev)
+{
+	struct adc_ad4130_data *data = dev->data;
+	uint8_t slot = data->setup_cfg_slots;
+
+	for (int i = 0; i < AD4130_MAX_SETUPS; i++) {
+		if (!(slot & (1 << i))) {
+			return i;
+		}
+	}
+
+	return AD4130_INVALID_SLOT;
+}
+
+static int adc_ad4130_create_new_cfg(const struct device *dev, const struct adc_channel_cfg *cfg,
+				     struct ad4130_channel_config *new_cfg)
+{
+	enum ad4130_ref_sel ref_source;
+	enum ad4130_gain gain;
+
+	if (cfg->channel_id >= AD4130_MAX_CHANNELS) {
+		LOG_ERR("Invalid channel (%u)", cfg->channel_id);
+		return -EINVAL;
+	}
+
+	if (cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
+		LOG_ERR("invalid acquisition time %i", cfg->acquisition_time);
+		return -EINVAL;
+	}
+
+	switch (cfg->reference) {
+	case ADC_REF_INTERNAL:
+		ref_source = AD4130_REF_REFOUT_AVSS;
+		break;
+	case ADC_REF_EXTERNAL0:
+		ref_source = AD4130_REF_REFIN1;
+		break;
+	case ADC_REF_EXTERNAL1:
+		ref_source = AD4130_REF_REFIN2;
+		break;
+	case ADC_REF_VDD_1:
+		ref_source = AD4130_REF_AVDD_AVSS;
+		break;
+	default:
+		LOG_ERR("Invalid reference source (%u)", cfg->reference);
+		return -EINVAL;
+	}
+
+	new_cfg->props.ref_sel = ref_source;
+
+	switch (cfg->gain) {
+	case ADC_GAIN_1:
+		gain = AD4130_GAIN_1;
+		break;
+	case ADC_GAIN_2:
+		gain = AD4130_GAIN_2;
+		break;
+	case ADC_GAIN_4:
+		gain = AD4130_GAIN_4;
+		break;
+	case ADC_GAIN_8:
+		gain = AD4130_GAIN_8;
+		break;
+	case ADC_GAIN_16:
+		gain = AD4130_GAIN_16;
+		break;
+	case ADC_GAIN_32:
+		gain = AD4130_GAIN_32;
+		break;
+	case ADC_GAIN_64:
+		gain = AD4130_GAIN_64;
+		break;
+	case ADC_GAIN_128:
+		gain = AD4130_GAIN_128;
+		break;
+	default:
+		LOG_ERR("Invalid gain value (%u)", cfg->gain);
+		return -EINVAL;
+	}
+
+	new_cfg->props.gain = gain;
+
+	return 0;
+}
+
+static int adc_ad4130_set_channel_setup(const struct device *dev, uint8_t channel_id,
+					enum ad4130_setup setup_id)
+{
+	return ad4130_reg_write_msk(dev, AD4130_CHANNEL_X_REG(channel_id),
+				    FIELD_PREP(AD4130_CHANNEL_SETUP_MASK, setup_id),
+				    AD4130_CHANNEL_SETUP_MASK);
+}
+
+static int adc_ad4130_channel_en(const struct device *dev, uint8_t channel_id, bool enable)
+{
+	return ad4130_reg_write_msk(dev, AD4130_CHANNEL_X_REG(channel_id),
+				    FIELD_PREP(AD4130_CHANNEL_EN_MASK, enable),
+				    AD4130_CHANNEL_EN_MASK);
+}
+
+static int adc_ad4130_connect_analog_input(const struct device *dev, uint8_t channel_id,
+					   enum ad4130_input ainp, enum ad4130_input ainm)
+{
+	if (ainp < AD4130_AIN0 || ainp > AD4130_V_MV_M || ainm < AD4130_AIN0 ||
+	    ainm > AD4130_V_MV_M) {
+		return -EINVAL;
+	}
+
+	int ret = ad4130_reg_write_msk(dev, AD4130_CHANNEL_X_REG(channel_id),
+				       FIELD_PREP(AD4130_CHANNEL_AINP_MASK, ainp),
+				       AD4130_CHANNEL_AINP_MASK);
+	if (ret) {
+		return ret;
+	}
+
+	return ad4130_reg_write_msk(dev, AD4130_CHANNEL_X_REG(channel_id),
+				    FIELD_PREP(AD4130_CHANNEL_AINM_MASK, ainm),
+				    AD4130_CHANNEL_AINM_MASK);
+}
+
+static int adc_ad4130_channel_setup(const struct device *dev, const struct adc_channel_cfg *cfg)
+{
+	struct adc_ad4130_data *data = dev->data;
+	struct ad4130_channel_config new_cfg;
+	int similar_channel_index;
+	int new_slot;
+	int ret;
+
+	data->channel_setup_cfg[cfg->channel_id].live_cfg = false;
+
+	ret = adc_ad4130_create_new_cfg(dev, cfg, &new_cfg);
+	if (ret) {
+		return ret;
+	}
+
+	/* AD4130 supports only 8 different configurations for 16 channels*/
+	new_slot = adc_ad4130_find_new_slot(dev);
+
+	if (new_slot == AD4130_INVALID_SLOT) {
+		similar_channel_index =
+			adc_ad4130_find_similar_configuration(dev, &new_cfg, cfg->channel_id);
+		if (similar_channel_index == AD4130_INVALID_CHANNEL) {
+			return -EINVAL;
+		}
+		new_cfg.cfg_slot = data->channel_setup_cfg[similar_channel_index].cfg_slot;
+	} else {
+		new_cfg.cfg_slot = new_slot;
+		WRITE_BIT(data->setup_cfg_slots, new_slot, true);
+	}
+
+	new_cfg.live_cfg = true;
+
+	memcpy(&data->channel_setup_cfg[cfg->channel_id], &new_cfg,
+	       sizeof(struct ad4130_channel_config));
+
+	/* Setup the channel configuration */
+	ret = adc_ad4130_setup_cfg(dev, &data->channel_setup_cfg[cfg->channel_id]);
+	if (ret) {
+		LOG_ERR("Error setting up configuration");
+		return ret;
+	}
+
+	/* Setup the channel */
+	ret = adc_ad4130_connect_analog_input(dev, cfg->channel_id, cfg->input_positive,
+					      cfg->input_negative);
+	if (ret) {
+		return ret;
+	}
+
+	ret = adc_ad4130_set_channel_setup(dev, cfg->channel_id, new_cfg.cfg_slot);
+	if (ret) {
+		LOG_ERR("Error setting up configuration");
+		return ret;
+	}
+
+	ret = adc_ad4130_channel_en(dev, cfg->channel_id, true);
+	if (ret) {
+		LOG_ERR("Error setting up configuration");
+		return ret;
+	}
+
+	WRITE_BIT(data->channels, cfg->channel_id, true);
+
+	return 0;
+}
+
+static int adc_ad4130_reset(const struct device *dev)
+{
+	const struct ad4130_config *config = dev->config;
+	const struct spi_dt_spec *spec = &config->bus;
+	int ret;
+
+	uint8_t buffer_write_tx[AD4130_RESET_BUF_SIZE] = {0xFF, 0xFF, 0xFF, 0xFF,
+							  0xFF, 0xFF, 0xFF, 0xFF};
+	struct spi_buf tx_buf = {
+		.buf = buffer_write_tx,
+		.len = ARRAY_SIZE(buffer_write_tx),
+	};
+
+	const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1};
+
+	/*
+	 * Send 8 times 0xFF to reset the ADC
+	 */
+	ret = spi_write_dt(spec, &tx);
+	if (ret) {
+		return ret;
+	}
+
+	k_sleep(K_MSEC(AD4130_RESET_SLEEP_MS));
+
+	return 0;
+}
+
+static int adc_ad4130_set_int_ref(const struct device *dev, enum ad4130_int_ref int_ref)
+{
+	int ret;
+
+	switch (int_ref) {
+	case AD4130_INT_REF_VAL_2_5V:
+		ret = ad4130_reg_write_msk(dev, AD4130_ADC_CONTROL_REG, 0U,
+					   AD4130_ADC_CONTROL_INT_REF_VAL_MASK);
+		break;
+
+	case AD4130_INT_REF_VAL_1_25V:
+		ret = ad4130_reg_write_msk(dev, AD4130_ADC_CONTROL_REG,
+					   FIELD_PREP(AD4130_ADC_CONTROL_INT_REF_VAL_MASK, 1),
+					   AD4130_ADC_CONTROL_INT_REF_VAL_MASK);
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+static int adc_ad4130_set_adc_mode(const struct device *dev, enum ad4130_adc_mode mode)
+{
+	return ad4130_reg_write_msk(dev, AD4130_ADC_CONTROL_REG,
+				    FIELD_PREP(AD4130_ADC_CONTROL_MODE_MASK, mode),
+				    AD4130_ADC_CONTROL_MODE_MASK);
+}
+
+static int adc_ad4130_check_chip_id(const struct device *dev)
+{
+	uint32_t reg_data;
+	int ret;
+
+	ret = ad4130_reg_read(dev, AD4130_ID_REG, &reg_data);
+	if (ret) {
+		return ret;
+	}
+
+	return reg_data == AD4130_8_ID ? 0 : -EINVAL;
+}
+
+static int adc_ad4130_set_polarity(const struct device *dev, bool enable)
+{
+	return ad4130_reg_write_msk(dev, AD4130_ADC_CONTROL_REG,
+				    FIELD_PREP(AD4130_ADC_CONTROL_BIPOLAR_MASK, enable),
+				    AD4130_ADC_CONTROL_BIPOLAR_MASK);
+}
+
+static int adc_ad4130_set_mclk(const struct device *dev, enum ad4130_mclk_sel clk)
+{
+	return ad4130_reg_write_msk(dev, AD4130_ADC_CONTROL_REG,
+				    FIELD_PREP(AD4130_ADC_CONTROL_MCLK_SEL_MASK, clk),
+				    AD4130_ADC_CONTROL_MCLK_SEL_MASK);
+}
+
+static int adc_ad4130_setup(const struct device *dev)
+{
+	const struct ad4130_config *config = dev->config;
+	uint32_t reg_data;
+	int ret;
+
+	/* Reset the device interface */
+	ret = adc_ad4130_reset(dev);
+	if (ret) {
+		return ret;
+	}
+
+	ret = ad4130_reg_read(dev, AD4130_STATUS_REG, &reg_data);
+	if (ret) {
+		return ret;
+	}
+
+	/* Change SPI to 4 wire*/
+	ret = ad4130_reg_write_msk(dev, AD4130_ADC_CONTROL_REG, AD4130_ADC_CONTROL_CSB_EN_MASK,
+				   AD4130_ADC_CONTROL_CSB_EN_MASK);
+	if (ret) {
+		return ret;
+	}
+
+	/* Check the device ID */
+	ret = adc_ad4130_check_chip_id(dev);
+	if (ret) {
+		return ret;
+	}
+
+	/* Disable channel 0 */
+	ret = adc_ad4130_channel_en(dev, 0, false);
+	if (ret) {
+		return ret;
+	}
+
+	ret = adc_ad4130_set_polarity(dev, config->bipolar);
+	if (ret) {
+		return ret;
+	}
+
+	ret = adc_ad4130_set_int_ref(dev, config->int_ref);
+	if (ret) {
+		return ret;
+	}
+
+	ret = adc_ad4130_set_adc_mode(dev, config->adc_mode);
+	if (ret) {
+		return ret;
+	}
+
+	ret = adc_ad4130_set_mclk(dev, config->mclk_sel);
+	if (ret) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static bool get_next_ch_idx(uint16_t ch_mask, uint16_t last_idx, uint16_t *new_idx)
+{
+	last_idx++;
+	if (last_idx >= AD4130_MAX_CHANNELS) {
+		return 0;
+	}
+	ch_mask >>= last_idx;
+	if (!ch_mask) {
+		*new_idx = AD4130_INVALID_CHANNEL;
+		return 0;
+	}
+	while (!(ch_mask & 1)) {
+		last_idx++;
+		ch_mask >>= 1;
+	}
+	*new_idx = last_idx;
+
+	return 1;
+}
+
+static int adc_ad4130_get_read_channel_id(const struct device *dev, uint16_t *channel_id)
+{
+	int ret;
+	uint32_t reg_temp;
+
+	ret = ad4130_reg_read(dev, AD4130_STATUS_REG, &reg_temp);
+	if (ret) {
+		return ret;
+	}
+
+	*channel_id = reg_temp & 0xF;
+
+	return 0;
+}
+
+static int adc_ad4130_wait_for_conv_ready(const struct device *dev)
+{
+	bool ready = false;
+	uint32_t reg_val;
+	int ret = 0;
+
+	while (!ready) {
+
+		ret = ad4130_reg_read(dev, AD4130_STATUS_REG, &reg_val);
+		if (ret) {
+			return ret;
+		}
+
+		ready = (reg_val & AD4130_STATUS_REG_DATA_READY) == 0;
+	}
+
+	return 0;
+}
+
+static int adc_ad4130_perform_read(const struct device *dev)
+{
+	int ret;
+	struct adc_ad4130_data *data = dev->data;
+	uint16_t ch_idx = AD4130_INVALID_CHANNEL;
+	uint16_t prev_ch_idx = AD4130_INVALID_CHANNEL;
+	uint16_t adc_ch_id = 0;
+	bool status;
+
+	k_sem_take(&data->acquire_signal, K_FOREVER);
+
+	do {
+		prev_ch_idx = ch_idx;
+
+		status = get_next_ch_idx(data->ctx.sequence.channels, ch_idx, &ch_idx);
+		if (!status) {
+			break;
+		}
+
+		adc_ad4130_wait_for_conv_ready(dev);
+
+		ret = ad4130_reg_read(dev, AD4130_DATA_REG, data->buffer);
+		if (ret) {
+			LOG_ERR("reading sample failed");
+			adc_context_complete(&data->ctx, ret);
+			return ret;
+		}
+
+		ret = adc_ad4130_get_read_channel_id(dev, &adc_ch_id);
+		if (ret) {
+			LOG_ERR("reading channel id failed");
+			adc_context_complete(&data->ctx, ret);
+			return ret;
+		}
+
+		if (ch_idx == adc_ch_id) {
+			data->buffer++;
+		} else {
+			ch_idx = prev_ch_idx;
+		}
+
+	} while (true);
+
+	adc_context_on_sampling_done(&data->ctx, dev);
+
+	return ret;
+}
+
+static int adc_ad4130_validate_sequence(const struct device *dev,
+					const struct adc_sequence *sequence)
+{
+	const struct ad4130_config *config = dev->config;
+	struct adc_ad4130_data *data = dev->data;
+	const size_t channel_maximum = AD4130_MAX_SETUPS * sizeof(sequence->channels);
+	uint32_t num_requested_channels;
+	size_t necessary;
+
+	if (sequence->resolution != config->resolution) {
+		LOG_ERR("invalid resolution");
+		return -EINVAL;
+	}
+
+	if (!sequence->channels) {
+		LOG_ERR("no channel selected");
+		return -EINVAL;
+	}
+
+	if (sequence->oversampling) {
+		LOG_ERR("oversampling is not supported");
+		return -EINVAL;
+	}
+
+	num_requested_channels = POPCOUNT(sequence->channels);
+	necessary = num_requested_channels * sizeof(int32_t);
+
+	if (sequence->options) {
+		necessary *= (1 + sequence->options->extra_samplings);
+	}
+
+	if (sequence->buffer_size < necessary) {
+		LOG_ERR("buffer size %u is too small, need %u", sequence->buffer_size, necessary);
+		return -ENOMEM;
+	}
+
+	for (size_t i = 0; i < channel_maximum; ++i) {
+		if ((BIT(i) & sequence->channels) == 0) {
+			continue;
+		}
+
+		if ((BIT(i) & sequence->channels) && !(BIT(i) & data->channels)) {
+			LOG_ERR("Channel-%d not enabled", i);
+			return -EINVAL;
+		}
+
+		if (i >= AD4130_MAX_CHANNELS) {
+			LOG_ERR("invalid channel selection");
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static int adc_ad4130_start_read(const struct device *dev, const struct adc_sequence *sequence,
+				 bool wait)
+{
+	int result;
+	struct adc_ad4130_data *data = dev->data;
+
+	result = adc_ad4130_validate_sequence(dev, sequence);
+	if (result != 0) {
+		LOG_ERR("sequence validation failed");
+		return result;
+	}
+
+	data->buffer = sequence->buffer;
+
+	adc_context_start_read(&data->ctx, sequence);
+
+	if (wait) {
+		result = adc_context_wait_for_completion(&data->ctx);
+	}
+
+	return result;
+}
+
+#if CONFIG_ADC_ASYNC
+static int adc_ad4130_read_async(const struct device *dev, const struct adc_sequence *sequence,
+				 struct k_poll_signal *async)
+{
+	int status;
+	struct adc_ad4130_data *data = dev->data;
+
+	adc_context_lock(&data->ctx, true, async);
+	status = adc_ad4130_start_read(dev, sequence, true);
+	adc_context_release(&data->ctx, status);
+
+	return status;
+}
+
+static int adc_ad4130_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+	int status;
+	struct adc_ad4130_data *data = dev->data;
+
+	adc_context_lock(&data->ctx, false, NULL);
+	status = adc_ad4130_start_read(dev, sequence, true);
+	adc_context_release(&data->ctx, status);
+
+	return status;
+}
+
+#else
+static int adc_ad4130_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+	int status;
+	struct adc_ad4130_data *data = dev->data;
+
+	adc_context_lock(&data->ctx, false, NULL);
+
+	status = adc_ad4130_start_read(dev, sequence, false);
+
+	while (status == 0 && k_sem_take(&data->ctx.sync, K_NO_WAIT) != 0) {
+		status = adc_ad4130_perform_read(dev);
+	}
+
+	adc_context_release(&data->ctx, status);
+
+	return status;
+}
+#endif
+
+#if CONFIG_ADC_ASYNC
+static void adc_ad4130_acquisition_thread(void *p1, void *p2, void *p3)
+{
+	ARG_UNUSED(p2);
+	ARG_UNUSED(p3);
+
+	const struct device *dev = p1;
+
+	while (true) {
+		adc_ad4130_perform_read(dev);
+	}
+}
+#endif /* CONFIG_ADC_ASYNC */
+
+static int ad4130_init(const struct device *dev)
+{
+	const struct ad4130_config *config = dev->config;
+	struct adc_ad4130_data *data = dev->data;
+	int ret;
+
+	data->dev = dev;
+
+	k_sem_init(&data->acquire_signal, 0, 1);
+
+	if (!spi_is_ready_dt(&config->bus)) {
+		LOG_ERR("spi bus %s not ready", config->bus.bus->name);
+		return -ENODEV;
+	}
+
+	ret = adc_ad4130_setup(dev);
+	if (ret) {
+		return ret;
+	}
+
+#if CONFIG_ADC_ASYNC
+	k_tid_t tid = k_thread_create(
+		&data->thread, data->stack, CONFIG_ADI_AD4130_ADC_ACQUISITION_THREAD_STACK_SIZE,
+		adc_ad4130_acquisition_thread, (void *)dev, NULL, NULL,
+		CONFIG_ADI_AD4130_ADC_ACQUISITION_THREAD_PRIO, 0, K_NO_WAIT);
+	k_thread_name_set(tid, "adc_ad4130");
+#endif /* CONFIG_ADC_ASYNC */
+
+	adc_context_unlock_unconditionally(&data->ctx);
+
+	return 0;
+}
+
+static DEVICE_API(adc, adc_ad4130_driver_api) = {
+	.channel_setup = adc_ad4130_channel_setup,
+	.read = adc_ad4130_read,
+	.ref_internal = AD4130_INT_REF_2_5V,
+#ifdef CONFIG_ADC_ASYNC
+	.read_async = adc_ad4130_read_async,
+#endif
+};
+
+#define AD4130_ADC_INIT(inst)                                                                      \
+	static const struct ad4130_config ad4130_config_##inst = {                                 \
+		.bus = SPI_DT_SPEC_GET(DT_INST(inst, adi_ad4130_adc),                              \
+				       SPI_OP_MODE_MASTER | SPI_WORD_SET(8) | SPI_TRANSFER_MSB,    \
+				       1),                                                         \
+		.resolution = AD4130_ADC_RESOLUTION,                                               \
+		.bipolar = DT_INST_PROP_OR(inst, bipolar, 1),                                      \
+		.int_ref = DT_INST_PROP_OR(inst, internal_reference_value, 0),                     \
+		.adc_mode = DT_INST_PROP_OR(inst, adc_mode, 0),                                    \
+		.mclk_sel = DT_INST_PROP_OR(inst, clock_type, 0),                                  \
+	};                                                                                         \
+	static struct adc_ad4130_data adc_ad4130_data_##inst = {                                   \
+		ADC_CONTEXT_INIT_LOCK(adc_ad4130_data_##inst, ctx),                                \
+		ADC_CONTEXT_INIT_TIMER(adc_ad4130_data_##inst, ctx),                               \
+		ADC_CONTEXT_INIT_SYNC(adc_ad4130_data_##inst, ctx),                                \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(inst, &ad4130_init, NULL, &adc_ad4130_data_##inst,                   \
+			      &ad4130_config_##inst, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY,        \
+			      &adc_ad4130_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(AD4130_ADC_INIT)
diff --git a/drivers/adc/adc_ad7124.c b/drivers/adc/adc_ad7124.c
new file mode 100644
index 00000000000..ea1a507f2cd
--- /dev/null
+++ b/drivers/adc/adc_ad7124.c
@@ -0,0 +1,1377 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT adi_ad7124_adc
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/crc.h>
+
+LOG_MODULE_REGISTER(adc_ad7124, CONFIG_ADC_LOG_LEVEL);
+
+#define ADC_CONTEXT_USES_KERNEL_TIMER
+#include "adc_context.h"
+
+#define AD7124_MAX_RETURNED_DATA_SIZE 6
+#define AD7124_ADC_VREF_MV            2500U
+#define AD7124_RESOLUTION             24
+#define AD7124_SPI_RDY_POLL_CNT       10000
+
+/* Maximum number of channels */
+#define AD7124_MAX_CHANNELS 16
+/* Total Number of Setups */
+#define AD7124_MAX_SETUPS   8
+
+/* AD7124-4 Standard Device ID */
+#define AD7124_4_STD_ID     0x04
+/* AD7124-4 B Grade Device ID */
+#define AD7124_4_B_GRADE_ID 0x06
+/* Device ID for the re-designed die in the AD7124-4 standard part and B-grade */
+#define AD7124_4_NEW_ID     0x07
+
+/* AD7124-8 Standard Device ID */
+#define AD7124_8_STD_ID       0x14
+/* AD7124-8 B and W Grade Device ID */
+#define AD7124_8_B_W_GRADE_ID 0x16
+/* Device ID for the re-designed die in the AD7124-8 standard part, B-grade and W-grade */
+#define AD7124_8_NEW_ID       0x17
+
+/* ODR */
+#define ADC_ODR_DEFAULT_VALUE  0xA    /* 10SPS */
+#define ADC_ODR_MIN_VALUE      0xA    /* 10SPS */
+#define ADC_ODR_LOW_POWER_MAX  0x960  /* 2400SPS */
+#define ADC_ODR_MID_POWER_MAX  0x12C0 /* 4800SPS */
+#define ADC_ODR_HIGH_POWER_MAX 0x4B00 /* 19200SPS */
+
+#define ADC_ODR_SEL_BITS_MAX 0x7FF
+#define ADC_ODR_SEL_BITS_MIN 0x1
+
+/* AD7124 registers */
+#define AD7124_STATUS      0x00
+#define AD7124_ADC_CONTROL 0x01
+#define AD7124_DATA        0x02
+#define AD7124_ID          0x05
+#define AD7124_ERROR       0x06
+#define AD7124_ERROR_EN    0x07
+#define AD7124_CHANNEL(x)  (0x09 + (x))
+#define AD7124_CONFIG(x)   (0x19 + (x))
+#define AD7124_FILTER(x)   (0x21 + (x))
+
+/* Configuration Registers 0-7 bits */
+#define AD7124_CFG_REG_BIPOLAR   BIT(11)
+#define AD7124_CFG_REG_REF_BUFP  BIT(8)
+#define AD7124_CFG_REG_REF_BUFM  BIT(7)
+#define AD7124_CFG_REG_AIN_BUFP  BIT(6)
+#define AD7124_CFG_REG_AINN_BUFM BIT(5)
+
+#define AD7124_REF_BUF_MSK                GENMASK(8, 7)
+#define AD7124_AIN_BUF_MSK                GENMASK(6, 5)
+#define AD7124_SETUP_CONF_REG_REF_SEL_MSK GENMASK(4, 3)
+#define AD7124_SETUP_CONF_PGA_MSK         GENMASK(2, 0)
+#define AD7124_ALL_BUF_MSK                GENMASK(8, 0)
+
+#define AD7124_SETUP_CONFIGURATION_MASK (AD7124_CFG_REG_BIPOLAR | AD7124_ALL_BUF_MSK)
+
+/* ADC_Control Register bits */
+#define AD7124_ADC_CTRL_REG_DATA_STATUS BIT(10)
+#define AD7124_ADC_CTRL_REG_REF_EN      BIT(8)
+
+/* CRC */
+#define AD7124_CRC8_POLYNOMIAL_REPRESENTATION 0x07 /* x8 + x2 + x + 1 */
+
+/* Communication Register bits */
+#define AD7124_COMM_REG_WEN   (0 << 7)
+#define AD7124_COMM_REG_WR    (0 << 6)
+#define AD7124_COMM_REG_RD    BIT(6)
+#define AD7124_COMM_REG_RA(x) ((x) & 0x3F)
+
+/* Filter register bits */
+#define AD7124_FILTER_CONF_REG_FILTER_MSK GENMASK(23, 21)
+#define AD7124_FILTER_FS_MSK              GENMASK(10, 0)
+
+/* Channel register bits */
+#define AD7124_CH_MAP_REG_CH_ENABLE    BIT(15)
+#define AD7124_CHMAP_REG_SETUP_SEL_MSK GENMASK(14, 12)
+#define AD7124_CHMAP_REG_AINPOS_MSK    GENMASK(9, 5)
+#define AD7124_CHMAP_REG_AINNEG_MSK    GENMASK(4, 0)
+
+/* Status register bits */
+#define AD7124_STATUS_REG_RDY          BIT(7)
+#define AD7124_STATUS_REG_POR_FLAG     BIT(4)
+#define AD7124_STATUS_REG_CH_ACTIVE(x) ((x) & 0xF)
+
+/* Error_En register bits */
+#define AD7124_ERREN_REG_SPI_IGNORE_ERR_EN BIT(6)
+#define AD7124_ERREN_REG_SPI_CRC_ERR_EN    BIT(2)
+
+/* ADC control register bits */
+#define AD7124_POWER_MODE_MSK        GENMASK(7, 6)
+#define AD7124_ADC_CTRL_REG_MODE_MSK GENMASK(5, 2)
+
+/* Error register bits */
+#define AD7124_ERR_REG_SPI_IGNORE_ERR BIT(6)
+
+enum ad7124_register_lengths {
+	AD7124_STATUS_REG_LEN = 1,
+	AD7124_ADC_CONTROL_REG_LEN = 2,
+	AD7124_DATA_REG_LEN = 3,
+	AD7124_ID_REG_LEN = 1,
+	AD7124_ERROR_REG_LEN = 3,
+	AD7124_ERROR_EN_REG_LEN = 3,
+	AD7124_CHANNEL_REG_LEN = 2,
+	AD7124_CONFIG_REG_LEN = 2,
+	AD7124_FILTER_REG_LEN = 3,
+};
+
+enum ad7124_mode {
+	AD7124_CONTINUOUS,
+	AD7124_SINGLE,
+	AD7124_STANDBY,
+	AD7124_POWER_DOWN,
+	AD7124_IDLE,
+	AD7124_IN_ZERO_SCALE_OFF,
+	AD7124_IN_FULL_SCALE_GAIN,
+	AD7124_SYS_ZERO_SCALE_OFF,
+	AD7124_SYS_ZERO_SCALE_GAIN,
+};
+
+enum ad7124_power_mode {
+	AD7124_LOW_POWER_MODE,
+	AD7124_MID_POWER_MODE,
+	AD7124_HIGH_POWER_MODE
+};
+
+enum adc_ad7124_master_clk_freq_hz {
+	AD7124_LOW_POWER_CLK = 76800,
+	AD7124_MID_POWER_CLK = 153600,
+	AD7124_HIGH_POWER_CLK = 614400,
+};
+
+enum ad7124_device_type {
+	ID_AD7124_4,
+	ID_AD7124_8
+};
+
+struct ad7124_control_status {
+	uint16_t value;
+	bool is_read;
+};
+
+enum ad7124_reference_source {
+	/* External Reference REFIN1+/-*/
+	EXTERNAL_REFIN1,
+	/* External Reference REFIN2+/-*/
+	EXTERNAL_REFIN2,
+	/* Internal 2.5V Reference */
+	INTERNAL_REF,
+	/* AVDD - AVSS */
+	AVDD_AVSS,
+};
+
+enum ad7124_gain {
+	AD7124_GAIN_1,
+	AD7124_GAIN_2,
+	AD7124_GAIN_4,
+	AD7124_GAIN_8,
+	AD7124_GAIN_16,
+	AD7124_GAIN_32,
+	AD7124_GAIN_64,
+	AD7124_GAIN_128
+};
+
+enum ad7124_filter_type {
+	AD7124_FILTER_SINC4,
+	AD7124_FILTER_SINC3 = 2U,
+};
+
+struct ad7124_config_props {
+	enum ad7124_reference_source refsel;
+	enum ad7124_gain pga_bits;
+	enum ad7124_filter_type filter_type;
+	uint16_t odr_sel_bits;
+	bool bipolar;
+	bool inbuf_enable;
+	bool refbuf_enable;
+};
+
+struct ad7124_channel_config {
+	struct ad7124_config_props props;
+	uint8_t cfg_slot;
+	bool live_cfg;
+};
+
+struct adc_ad7124_config {
+	struct spi_dt_spec bus;
+	uint16_t filter_type_mask;
+	uint16_t bipolar_mask;
+	uint16_t inbuf_enable_mask;
+	uint16_t refbuf_enable_mask;
+	enum ad7124_mode adc_mode;
+	enum ad7124_power_mode power_mode;
+	enum ad7124_device_type active_device;
+	uint8_t resolution;
+	bool ref_en;
+};
+
+struct adc_ad7124_data {
+	const struct device *dev;
+	struct adc_context ctx;
+	struct ad7124_control_status adc_control_status;
+	struct ad7124_channel_config channel_setup_cfg[AD7124_MAX_CHANNELS];
+	uint8_t setup_cfg_slots;
+	struct k_sem acquire_signal;
+	uint16_t channels;
+	uint32_t *buffer;
+	uint32_t *repeat_buffer;
+	bool crc_enable;
+	bool spi_ready;
+#if CONFIG_ADC_ASYNC
+	struct k_thread thread;
+
+	K_KERNEL_STACK_MEMBER(stack, CONFIG_ADI_AD7124_ADC_ACQUISITION_THREAD_STACK_SIZE);
+#endif /* CONFIG_ADC_ASYNC */
+};
+
+static int adc_ad7124_read_reg(const struct device *dev, uint32_t reg,
+			       enum ad7124_register_lengths len, uint32_t *val);
+
+static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
+{
+	struct adc_ad7124_data *data = CONTAINER_OF(ctx, struct adc_ad7124_data, ctx);
+
+	if (repeat_sampling) {
+		data->buffer = data->repeat_buffer;
+	}
+}
+
+static void adc_context_start_sampling(struct adc_context *ctx)
+{
+	struct adc_ad7124_data *data = CONTAINER_OF(ctx, struct adc_ad7124_data, ctx);
+
+	data->repeat_buffer = data->buffer;
+	k_sem_give(&data->acquire_signal);
+}
+
+static int adc_ad7124_acq_time_to_odr(const struct device *dev, uint16_t acq_time, uint16_t *odr)
+{
+	const struct adc_ad7124_config *config = dev->config;
+	uint16_t acquisition_time_value = ADC_ACQ_TIME_VALUE(acq_time);
+	uint16_t acquisition_time_unit = ADC_ACQ_TIME_UNIT(acq_time);
+
+	/* The AD7124 uses samples per seconds units with the lowest being 10SPS
+	 * regardless of the selected power mode and with acquisition_time only
+	 * having 14b for time, this will not fit within here for microsecond units.
+	 * Use Tick units and allow the user to specify the ODR directly.
+	 */
+
+	if (acq_time == ADC_ACQ_TIME_DEFAULT) {
+		*odr = ADC_ODR_DEFAULT_VALUE;
+		return 0;
+	}
+
+	if (acquisition_time_unit != ADC_ACQ_TIME_TICKS) {
+		LOG_ERR("%s: invalid acquisition time %i", dev->name, acquisition_time_value);
+		return -EINVAL;
+	}
+
+	if (acquisition_time_value < ADC_ODR_MIN_VALUE) {
+		LOG_ERR("%s: invalid acquisition time %i", dev->name, acquisition_time_value);
+		return -EINVAL;
+	} else if (config->power_mode == AD7124_HIGH_POWER_MODE &&
+		   acquisition_time_value > ADC_ODR_HIGH_POWER_MAX) {
+		LOG_ERR("%s: invalid acquisition time %i", dev->name, acquisition_time_value);
+		return -EINVAL;
+	} else if (config->power_mode == AD7124_MID_POWER_MODE &&
+		   acquisition_time_value > ADC_ODR_MID_POWER_MAX) {
+		LOG_ERR("%s: invalid acquisition time %i", dev->name, acquisition_time_value);
+		return -EINVAL;
+	} else if (config->power_mode == AD7124_LOW_POWER_MODE &&
+		   acquisition_time_value > ADC_ODR_LOW_POWER_MAX) {
+		LOG_ERR("%s: invalid acquisition time %i", dev->name, acquisition_time_value);
+		return -EINVAL;
+	}
+
+	*odr = acquisition_time_value;
+
+	return 0;
+}
+
+static uint16_t adc_ad7124_odr_to_fs(const struct device *dev, int16_t odr)
+{
+	const struct adc_ad7124_config *config = dev->config;
+	uint16_t odr_sel_bits;
+	uint32_t master_clk_freq;
+
+	switch (config->power_mode) {
+	case AD7124_HIGH_POWER_MODE:
+		master_clk_freq = AD7124_HIGH_POWER_CLK;
+		break;
+	case AD7124_MID_POWER_MODE:
+		master_clk_freq = AD7124_MID_POWER_CLK;
+		break;
+	case AD7124_LOW_POWER_MODE:
+		master_clk_freq = AD7124_LOW_POWER_CLK;
+		break;
+	default:
+		LOG_ERR("Invalid power mode (%u)", config->power_mode);
+		return -EINVAL;
+	}
+
+	odr_sel_bits = DIV_ROUND_CLOSEST(master_clk_freq, odr * 32);
+
+	if (odr_sel_bits < ADC_ODR_SEL_BITS_MIN) {
+		odr_sel_bits = ADC_ODR_SEL_BITS_MIN;
+	} else if (odr_sel_bits > ADC_ODR_SEL_BITS_MAX) {
+		odr_sel_bits = ADC_ODR_SEL_BITS_MAX;
+	}
+
+	return odr_sel_bits;
+}
+
+static int adc_ad7124_create_new_cfg(const struct device *dev, const struct adc_channel_cfg *cfg,
+				     struct ad7124_channel_config *new_cfg)
+{
+	const struct adc_ad7124_config *config = dev->config;
+	uint16_t odr;
+	enum ad7124_reference_source ref_source;
+	enum ad7124_gain gain;
+	int ret;
+
+	if (cfg->channel_id >= AD7124_MAX_CHANNELS) {
+		LOG_ERR("Invalid channel (%u)", cfg->channel_id);
+		return -EINVAL;
+	}
+
+	switch (cfg->reference) {
+	case ADC_REF_INTERNAL:
+		ref_source = INTERNAL_REF;
+		break;
+	case ADC_REF_EXTERNAL0:
+		ref_source = EXTERNAL_REFIN1;
+		break;
+	case ADC_REF_EXTERNAL1:
+		ref_source = EXTERNAL_REFIN2;
+		break;
+	case ADC_REF_VDD_1:
+		ref_source = AVDD_AVSS;
+		break;
+	default:
+		LOG_ERR("Invalid reference source (%u)", cfg->reference);
+		return -EINVAL;
+	}
+
+	new_cfg->props.refsel = ref_source;
+
+	switch (cfg->gain) {
+	case ADC_GAIN_1:
+		gain = AD7124_GAIN_1;
+		break;
+	case ADC_GAIN_2:
+		gain = AD7124_GAIN_2;
+		break;
+	case ADC_GAIN_4:
+		gain = AD7124_GAIN_4;
+		break;
+	case ADC_GAIN_8:
+		gain = AD7124_GAIN_8;
+		break;
+	case ADC_GAIN_16:
+		gain = AD7124_GAIN_16;
+		break;
+	case ADC_GAIN_32:
+		gain = AD7124_GAIN_32;
+		break;
+	case ADC_GAIN_64:
+		gain = AD7124_GAIN_64;
+		break;
+	case ADC_GAIN_128:
+		gain = AD7124_GAIN_128;
+		break;
+	default:
+		LOG_ERR("Invalid gain value (%u)", cfg->gain);
+		return -EINVAL;
+	}
+
+	new_cfg->props.pga_bits = gain;
+
+	ret = adc_ad7124_acq_time_to_odr(dev, cfg->acquisition_time, &odr);
+	if (ret) {
+		return ret;
+	}
+
+	if (config->filter_type_mask & BIT(cfg->channel_id)) {
+		new_cfg->props.filter_type = AD7124_FILTER_SINC3;
+	} else {
+		new_cfg->props.filter_type = AD7124_FILTER_SINC4;
+	}
+
+	new_cfg->props.odr_sel_bits = adc_ad7124_odr_to_fs(dev, odr);
+	new_cfg->props.bipolar = config->bipolar_mask & BIT(cfg->channel_id);
+	new_cfg->props.inbuf_enable = config->inbuf_enable_mask & BIT(cfg->channel_id);
+	new_cfg->props.refbuf_enable = config->refbuf_enable_mask & BIT(cfg->channel_id);
+
+	return 0;
+}
+
+static int adc_ad7124_find_new_slot(const struct device *dev)
+{
+	struct adc_ad7124_data *data = dev->data;
+	uint8_t slot = data->setup_cfg_slots;
+
+	int cnt = 0;
+
+	while (slot) {
+		if ((slot & 0x1) == 0) {
+			return cnt;
+		}
+		slot >>= 1;
+		cnt++;
+	}
+
+	if (cnt == AD7124_MAX_SETUPS) {
+		return -1;
+	}
+
+	return cnt;
+}
+
+static int adc_ad7124_find_similar_configuration(const struct device *dev,
+						 const struct ad7124_channel_config *cfg,
+						 int channel_id)
+{
+	struct adc_ad7124_data *data = dev->data;
+	int similar_channel_index = -1;
+
+	for (int i = 0; i < AD7124_MAX_CHANNELS; i++) {
+		if (!data->channel_setup_cfg[i].live_cfg && i == channel_id) {
+			continue;
+		}
+
+		if (memcmp(&cfg->props, &data->channel_setup_cfg[i].props,
+			   sizeof(struct ad7124_config_props)) == 0) {
+			similar_channel_index = i;
+			break;
+		}
+	}
+
+	return similar_channel_index;
+}
+
+static int adc_ad7124_wait_for_spi_ready(const struct device *dev)
+{
+	int ret = 0;
+	uint32_t read_val = 0;
+	bool ready = false;
+	uint16_t spi_ready_try_count = AD7124_SPI_RDY_POLL_CNT;
+
+	while (!ready && --spi_ready_try_count) {
+		ret = adc_ad7124_read_reg(dev, AD7124_ERROR, AD7124_ERROR_REG_LEN, &read_val);
+		if (ret) {
+			return ret;
+		}
+
+		ready = (read_val & AD7124_ERR_REG_SPI_IGNORE_ERR) == 0;
+	}
+
+	if (!spi_ready_try_count) {
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static int adc_ad7124_read_reg(const struct device *dev, uint32_t reg,
+			       enum ad7124_register_lengths len, uint32_t *val)
+{
+	const struct adc_ad7124_config *config = dev->config;
+	struct adc_ad7124_data *data = dev->data;
+	const struct spi_dt_spec *spec = &config->bus;
+
+	int ret;
+	uint32_t cntrl_value = 0;
+	uint8_t add_status_length = 0;
+	uint8_t buffer_tx[AD7124_MAX_RETURNED_DATA_SIZE] = {0};
+	uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)];
+	uint8_t crc_check;
+
+	if (reg != AD7124_ERROR && data->spi_ready) {
+		ret = adc_ad7124_wait_for_spi_ready(dev);
+		if (ret) {
+			return ret;
+		}
+	}
+
+	if (reg == AD7124_DATA) {
+
+		if (data->adc_control_status.is_read) {
+			cntrl_value = data->adc_control_status.value;
+		} else {
+			ret = adc_ad7124_read_reg(dev, AD7124_ADC_CONTROL,
+						  AD7124_ADC_CONTROL_REG_LEN, &cntrl_value);
+			if (ret) {
+				return ret;
+			}
+		}
+
+		if (cntrl_value & AD7124_ADC_CTRL_REG_DATA_STATUS) {
+			add_status_length = 1;
+		}
+	}
+
+	struct spi_buf tx_buf[] = {{
+		.buf = buffer_tx,
+		.len = 1,
+	}};
+	struct spi_buf rx_buf[] = {{
+		.buf = buffer_rx,
+		.len = ((data->crc_enable) ? len + 1 : len) + 1 + add_status_length,
+	}};
+	const struct spi_buf_set tx = {.buffers = tx_buf, .count = ARRAY_SIZE(tx_buf)};
+	const struct spi_buf_set rx = {.buffers = rx_buf, .count = ARRAY_SIZE(rx_buf)};
+
+	buffer_tx[0] = AD7124_COMM_REG_WEN | AD7124_COMM_REG_RD | AD7124_COMM_REG_RA(reg);
+
+	ret = spi_transceive_dt(spec, &tx, &rx);
+	if (ret) {
+		return ret;
+	}
+
+	if (data->crc_enable) {
+		buffer_rx[0] = AD7124_COMM_REG_WEN | AD7124_COMM_REG_RD | AD7124_COMM_REG_RA(reg);
+
+		crc_check = crc8(buffer_rx, len + 2 + add_status_length,
+				 AD7124_CRC8_POLYNOMIAL_REPRESENTATION, 0, false);
+		if (crc_check) {
+			return -EBADMSG;
+		}
+	}
+
+	switch (len) {
+	case 1:
+		*val = buffer_rx[1];
+		break;
+	case 2:
+		*val = sys_get_be16(&buffer_rx[1]);
+		break;
+	case 3:
+		*val = sys_get_be24(&buffer_rx[1]);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (reg == AD7124_ADC_CONTROL) {
+		data->adc_control_status.value = *val;
+		data->adc_control_status.is_read = true;
+	}
+
+	return 0;
+}
+
+static int adc_ad7124_write_reg(const struct device *dev, uint32_t reg,
+				enum ad7124_register_lengths len, uint32_t val)
+{
+	const struct adc_ad7124_config *config = dev->config;
+	struct adc_ad7124_data *data = dev->data;
+	const struct spi_dt_spec *spec = &config->bus;
+
+	int ret;
+	uint8_t buffer_tx[AD7124_MAX_RETURNED_DATA_SIZE] = {0};
+	uint8_t crc;
+
+	if (data->spi_ready) {
+		ret = adc_ad7124_wait_for_spi_ready(dev);
+		if (ret) {
+			return ret;
+		}
+	}
+
+	buffer_tx[0] = AD7124_COMM_REG_WEN | AD7124_COMM_REG_WR | AD7124_COMM_REG_RA(reg);
+
+	switch (len) {
+	case 1:
+		buffer_tx[1] = val;
+		break;
+	case 2:
+		sys_put_be16(val, &buffer_tx[1]);
+		break;
+	case 3:
+		sys_put_be24(val, &buffer_tx[1]);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (data->crc_enable) {
+		crc = crc8(buffer_tx, len + 1, AD7124_CRC8_POLYNOMIAL_REPRESENTATION, 0, false);
+		buffer_tx[len + 1] = crc;
+	}
+
+	struct spi_buf tx_buf[] = {{
+		.buf = buffer_tx,
+		.len = ((data->crc_enable) ? len + 1 : len) + 1,
+	}};
+
+	const struct spi_buf_set tx = {.buffers = tx_buf, .count = ARRAY_SIZE(tx_buf)};
+
+	ret = spi_transceive_dt(spec, &tx, NULL);
+	if (ret) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static int adc_ad7124_reg_write_msk(const struct device *dev, uint32_t reg,
+				    enum ad7124_register_lengths len, uint32_t data, uint32_t mask)
+{
+	int ret;
+	uint32_t reg_data;
+
+	ret = adc_ad7124_read_reg(dev, reg, len, &reg_data);
+	if (ret) {
+		return ret;
+	}
+
+	reg_data &= ~mask;
+	reg_data |= data;
+
+	ret = adc_ad7124_write_reg(dev, reg, len, reg_data);
+	if (ret) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static int adc_ad7124_setup_cfg(const struct device *dev, const struct ad7124_channel_config *cfg)
+{
+	const struct adc_ad7124_config *config = dev->config;
+	int ret;
+	int configuration_setup = 0;
+	int configuration_mask = 0;
+	int ref_internal = 0;
+
+	if (cfg->props.bipolar) {
+		configuration_setup |= AD7124_CFG_REG_BIPOLAR;
+	}
+
+	if (cfg->props.inbuf_enable) {
+		configuration_setup |= AD7124_CFG_REG_AIN_BUFP | AD7124_CFG_REG_AINN_BUFM;
+	}
+
+	if (cfg->props.refbuf_enable) {
+		configuration_setup |= AD7124_CFG_REG_REF_BUFP | AD7124_CFG_REG_REF_BUFM;
+	}
+
+	configuration_setup |= FIELD_PREP(AD7124_SETUP_CONF_REG_REF_SEL_MSK, cfg->props.refsel);
+	configuration_setup |= FIELD_PREP(AD7124_SETUP_CONF_PGA_MSK, cfg->props.pga_bits);
+	configuration_mask |= AD7124_SETUP_CONFIGURATION_MASK;
+
+	ret = adc_ad7124_reg_write_msk(dev, AD7124_CONFIG(cfg->cfg_slot), AD7124_CONFIG_REG_LEN,
+				       configuration_setup, configuration_mask);
+	if (ret) {
+		return ret;
+	}
+
+	if (config->ref_en) {
+		ref_internal = AD7124_ADC_CTRL_REG_REF_EN;
+	}
+
+	if (cfg->props.refsel == INTERNAL_REF) {
+		ret = adc_ad7124_reg_write_msk(dev, AD7124_ADC_CONTROL, AD7124_ADC_CONTROL_REG_LEN,
+					       ref_internal, AD7124_ADC_CTRL_REG_REF_EN);
+		if (ret) {
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int adc_ad7124_filter_cfg(const struct device *dev, const struct ad7124_channel_config *cfg)
+{
+	int filter_setup = 0;
+	int filter_mask = 0;
+	int ret;
+
+	filter_setup = FIELD_PREP(AD7124_FILTER_CONF_REG_FILTER_MSK, cfg->props.filter_type) |
+		       FIELD_PREP(AD7124_FILTER_FS_MSK, cfg->props.odr_sel_bits);
+	filter_mask = AD7124_FILTER_CONF_REG_FILTER_MSK | AD7124_FILTER_FS_MSK;
+
+	/* Set filter type and odr*/
+	ret = adc_ad7124_reg_write_msk(dev, AD7124_FILTER(cfg->cfg_slot), AD7124_FILTER_REG_LEN,
+				       filter_setup, filter_mask);
+	if (ret) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static int adc_ad7124_connect_analog_input(const struct device *dev, uint8_t chn_num, uint8_t ainp,
+					   uint8_t ainm)
+{
+	int ret;
+
+	ret = adc_ad7124_reg_write_msk(dev, AD7124_CHANNEL(chn_num), AD7124_CHANNEL_REG_LEN,
+				       FIELD_PREP(AD7124_CHMAP_REG_AINPOS_MSK, ainp),
+				       AD7124_CHMAP_REG_AINPOS_MSK);
+	if (ret) {
+		return ret;
+	}
+
+	ret = adc_ad7124_reg_write_msk(dev, AD7124_CHANNEL(chn_num), AD7124_CHANNEL_REG_LEN,
+				       FIELD_PREP(AD7124_CHMAP_REG_AINNEG_MSK, ainm),
+				       AD7124_CHMAP_REG_AINNEG_MSK);
+	if (ret) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static int adc_ad7124_set_channel_status(const struct device *dev, uint8_t chn_num,
+					 bool channel_status)
+{
+	int ret;
+	uint16_t status;
+
+	if (channel_status) {
+		status = AD7124_CH_MAP_REG_CH_ENABLE;
+	} else {
+		status = 0x0U;
+	}
+
+	ret = adc_ad7124_reg_write_msk(dev, AD7124_CHANNEL(chn_num), AD7124_CHANNEL_REG_LEN, status,
+				       AD7124_CH_MAP_REG_CH_ENABLE);
+	if (ret) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static int adc_ad7124_channel_cfg(const struct device *dev, const struct adc_channel_cfg *cfg)
+{
+	struct adc_ad7124_data *data = dev->data;
+	int ret;
+
+	ret = adc_ad7124_connect_analog_input(dev, cfg->channel_id, cfg->input_positive,
+					      cfg->input_negative);
+	if (ret) {
+		return ret;
+	}
+
+	/* Assign setup */
+	ret = adc_ad7124_reg_write_msk(
+		dev, AD7124_CHANNEL(cfg->channel_id), AD7124_CHANNEL_REG_LEN,
+		FIELD_PREP(AD7124_CHMAP_REG_SETUP_SEL_MSK,
+			   data->channel_setup_cfg[cfg->channel_id].cfg_slot),
+		AD7124_CHMAP_REG_SETUP_SEL_MSK);
+	if (ret) {
+		return ret;
+	}
+
+	ret = adc_ad7124_set_channel_status(dev, cfg->channel_id, true);
+	if (ret) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static int adc_ad7124_channel_setup(const struct device *dev, const struct adc_channel_cfg *cfg)
+{
+	struct adc_ad7124_data *data = dev->data;
+	struct ad7124_channel_config new_cfg;
+	int new_slot;
+	int ret;
+	int similar_channel_index;
+
+	data->channel_setup_cfg[cfg->channel_id].live_cfg = false;
+
+	ret = adc_ad7124_create_new_cfg(dev, cfg, &new_cfg);
+	if (ret) {
+		return ret;
+	}
+
+	/* AD7124 supports only 8 different configurations for 16 channels*/
+	new_slot = adc_ad7124_find_new_slot(dev);
+
+	if (new_slot == -1) {
+		similar_channel_index =
+			adc_ad7124_find_similar_configuration(dev, &new_cfg, cfg->channel_id);
+		if (similar_channel_index == -1) {
+			return -EINVAL;
+		}
+		new_cfg.cfg_slot = data->channel_setup_cfg[similar_channel_index].cfg_slot;
+	} else {
+		new_cfg.cfg_slot = new_slot;
+		WRITE_BIT(data->setup_cfg_slots, new_slot, true);
+	}
+
+	new_cfg.live_cfg = true;
+
+	memcpy(&data->channel_setup_cfg[cfg->channel_id], &new_cfg,
+	       sizeof(struct ad7124_channel_config));
+
+	/* Setup the channel configuration */
+	ret = adc_ad7124_setup_cfg(dev, &data->channel_setup_cfg[cfg->channel_id]);
+	if (ret) {
+		LOG_ERR("Error setting up configuration");
+		return ret;
+	}
+
+	/* Setup the filter configuration */
+	ret = adc_ad7124_filter_cfg(dev, &data->channel_setup_cfg[cfg->channel_id]);
+	if (ret) {
+		LOG_ERR("Error setting up filter");
+		return ret;
+	}
+
+	/* Setup the channel */
+	ret = adc_ad7124_channel_cfg(dev, cfg);
+	if (ret) {
+		LOG_ERR("Error setting up channel");
+		return ret;
+	}
+
+	WRITE_BIT(data->channels, cfg->channel_id, true);
+
+	return 0;
+}
+
+int adc_ad7124_wait_to_power_up(const struct device *dev)
+{
+	int ret = 0;
+	uint32_t read_val = 0;
+	bool powered_on = false;
+	uint16_t spi_ready_try_count = AD7124_SPI_RDY_POLL_CNT;
+
+	while (!powered_on && --spi_ready_try_count) {
+
+		ret = adc_ad7124_read_reg(dev, AD7124_STATUS, AD7124_STATUS_REG_LEN, &read_val);
+		if (ret) {
+			return ret;
+		}
+
+		powered_on = (read_val & AD7124_STATUS_REG_POR_FLAG) == 0;
+	}
+
+	if (!spi_ready_try_count) {
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+int adc_ad7124_reset(const struct device *dev)
+{
+	const struct adc_ad7124_config *config = dev->config;
+	const struct spi_dt_spec *spec = &config->bus;
+
+	int ret;
+	uint8_t buffer_tx[8] = {0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF};
+
+	struct spi_buf tx_buf[] = {{
+		.buf = buffer_tx,
+		.len = ARRAY_SIZE(buffer_tx),
+	}};
+
+	const struct spi_buf_set tx = {.buffers = tx_buf, .count = ARRAY_SIZE(tx_buf)};
+
+	ret = spi_transceive_dt(spec, &tx, NULL);
+	if (ret) {
+		return ret;
+	}
+
+	ret = adc_ad7124_wait_to_power_up(dev);
+	if (ret) {
+		return ret;
+	}
+
+	return ret;
+}
+
+static int adc_ad7124_update_crc(const struct device *dev)
+{
+	struct adc_ad7124_data *data = dev->data;
+
+	int ret = 0;
+	uint32_t reg_temp = 0;
+
+	ret = adc_ad7124_read_reg(dev, AD7124_ERROR_EN, AD7124_ERROR_EN_REG_LEN, &reg_temp);
+	if (ret) {
+		return ret;
+	}
+
+	if (reg_temp & AD7124_ERREN_REG_SPI_CRC_ERR_EN) {
+		data->crc_enable = true;
+	} else {
+		data->crc_enable = false;
+	}
+
+	return 0;
+}
+
+static int adc_ad7124_update_spi_check_ready(const struct device *dev)
+{
+	struct adc_ad7124_data *data = dev->data;
+
+	int ret = 0;
+	uint32_t reg_temp = 0;
+
+	ret = adc_ad7124_read_reg(dev, AD7124_ERROR_EN, AD7124_ERROR_EN_REG_LEN, &reg_temp);
+	if (ret) {
+		return ret;
+	}
+
+	if (reg_temp & AD7124_ERREN_REG_SPI_IGNORE_ERR_EN) {
+		data->spi_ready = true;
+	} else {
+		data->spi_ready = false;
+	}
+
+	return 0;
+}
+
+static int adc_ad7124_check_chip_id(const struct device *dev)
+{
+	const struct adc_ad7124_config *config = dev->config;
+	uint32_t reg_temp = 0;
+	int ret;
+
+	ret = adc_ad7124_read_reg(dev, AD7124_ID, AD7124_ID_REG_LEN, &reg_temp);
+	if (ret) {
+		return ret;
+	}
+
+	if (config->active_device == ID_AD7124_4) {
+		switch (reg_temp) {
+		case AD7124_4_STD_ID:
+		case AD7124_4_B_GRADE_ID:
+		case AD7124_4_NEW_ID:
+			break;
+
+		default:
+			return -ENODEV;
+		}
+	} else if (config->active_device == ID_AD7124_8) {
+		switch (reg_temp) {
+		case AD7124_8_STD_ID:
+		case AD7124_8_B_W_GRADE_ID:
+		case AD7124_8_NEW_ID:
+			break;
+
+		default:
+			return -ENODEV;
+		}
+	} else {
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static int adc_ad7124_set_adc_mode(const struct device *dev, enum ad7124_mode adc_mode)
+{
+	int ret;
+
+	ret = adc_ad7124_reg_write_msk(dev, AD7124_ADC_CONTROL, AD7124_ADC_CONTROL_REG_LEN,
+				       FIELD_PREP(AD7124_ADC_CTRL_REG_MODE_MSK, adc_mode),
+				       AD7124_ADC_CTRL_REG_MODE_MSK);
+	if (ret) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static int adc_ad7124_set_power_mode(const struct device *dev, enum ad7124_power_mode power_mode)
+{
+	int ret;
+
+	ret = adc_ad7124_reg_write_msk(dev, AD7124_ADC_CONTROL, AD7124_ADC_CONTROL_REG_LEN,
+				       FIELD_PREP(AD7124_POWER_MODE_MSK, power_mode),
+				       AD7124_POWER_MODE_MSK);
+	if (ret) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static int adc_ad7124_setup(const struct device *dev)
+{
+	const struct adc_ad7124_config *config = dev->config;
+	int ret;
+
+	/* Reset the device interface */
+	ret = adc_ad7124_reset(dev);
+	if (ret) {
+		return ret;
+	}
+
+	/* Get CRC State */
+	ret = adc_ad7124_update_crc(dev);
+	if (ret) {
+		return ret;
+	}
+
+	ret = adc_ad7124_update_spi_check_ready(dev);
+	if (ret) {
+		return ret;
+	}
+
+	/* Check the device ID */
+	ret = adc_ad7124_check_chip_id(dev);
+	if (ret) {
+		return ret;
+	}
+
+	/* Disable channel 0 */
+	ret = adc_ad7124_set_channel_status(dev, 0, false);
+	if (ret) {
+		return ret;
+	}
+
+	ret = adc_ad7124_set_adc_mode(dev, config->adc_mode);
+	if (ret) {
+		return ret;
+	}
+
+	ret = adc_ad7124_set_power_mode(dev, config->power_mode);
+	if (ret) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static int adc_ad7124_wait_for_conv_ready(const struct device *dev)
+{
+	int ret = 0;
+	uint32_t read_val = 0;
+	bool ready = false;
+	uint16_t spi_ready_try_count = AD7124_SPI_RDY_POLL_CNT;
+
+	while (!ready && --spi_ready_try_count) {
+
+		ret = adc_ad7124_read_reg(dev, AD7124_STATUS, AD7124_STATUS_REG_LEN, &read_val);
+		if (ret) {
+			return ret;
+		}
+
+		ready = (read_val & AD7124_STATUS_REG_RDY) == 0;
+	}
+
+	if (!spi_ready_try_count) {
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static bool get_next_ch_idx(uint16_t ch_mask, uint16_t last_idx, uint16_t *new_idx)
+{
+	last_idx++;
+	if (last_idx >= AD7124_MAX_CHANNELS) {
+		return 0;
+	}
+	ch_mask >>= last_idx;
+	if (!ch_mask) {
+		*new_idx = -1;
+		return 0;
+	}
+	while (!(ch_mask & 1)) {
+		last_idx++;
+		ch_mask >>= 1;
+	}
+	*new_idx = last_idx;
+
+	return 1;
+}
+
+static int adc_ad7124_get_read_chan_id(const struct device *dev, uint16_t *chan_id)
+{
+	int ret;
+	uint32_t reg_temp;
+
+	ret = adc_ad7124_read_reg(dev, AD7124_STATUS, AD7124_STATUS_REG_LEN, &reg_temp);
+	if (ret) {
+		return ret;
+	}
+
+	*chan_id = reg_temp & AD7124_STATUS_REG_CH_ACTIVE(0xF);
+
+	return 0;
+}
+
+static int adc_ad7124_perform_read(const struct device *dev)
+{
+	int ret;
+	struct adc_ad7124_data *data = dev->data;
+	uint16_t ch_idx = -1;
+	uint16_t prev_ch_idx = -1;
+	uint16_t adc_ch_id = 0;
+	bool status;
+
+	k_sem_take(&data->acquire_signal, K_FOREVER);
+
+	do {
+		prev_ch_idx = ch_idx;
+
+		status = get_next_ch_idx(data->ctx.sequence.channels, ch_idx, &ch_idx);
+		if (!status) {
+			break;
+		}
+
+		ret = adc_ad7124_wait_for_conv_ready(dev);
+		if (ret) {
+			LOG_ERR("waiting for conversion ready failed");
+			adc_context_complete(&data->ctx, ret);
+			return ret;
+		}
+
+		ret = adc_ad7124_read_reg(dev, AD7124_DATA, AD7124_DATA_REG_LEN, data->buffer);
+		if (ret) {
+			LOG_ERR("reading sample failed");
+			adc_context_complete(&data->ctx, ret);
+			return ret;
+		}
+
+		ret = adc_ad7124_get_read_chan_id(dev, &adc_ch_id);
+		if (ret) {
+			LOG_ERR("reading channel id failed");
+			adc_context_complete(&data->ctx, ret);
+			return ret;
+		}
+
+		if (ch_idx == adc_ch_id) {
+			data->buffer++;
+		} else {
+			ch_idx = prev_ch_idx;
+		}
+
+	} while (true);
+
+	adc_context_on_sampling_done(&data->ctx, dev);
+
+	return ret;
+}
+
+static int adc_ad7124_validate_sequence(const struct device *dev,
+					const struct adc_sequence *sequence)
+{
+	const struct adc_ad7124_config *config = dev->config;
+	struct adc_ad7124_data *data = dev->data;
+	const size_t channel_maximum = 8 * sizeof(sequence->channels);
+	uint32_t num_requested_channels;
+	size_t necessary;
+
+	if (sequence->resolution != config->resolution) {
+		LOG_ERR("invalid resolution");
+		return -EINVAL;
+	}
+
+	if (!sequence->channels) {
+		LOG_ERR("no channel selected");
+		return -EINVAL;
+	}
+
+	if (sequence->oversampling) {
+		LOG_ERR("oversampling is not supported");
+		return -EINVAL;
+	}
+
+	num_requested_channels = POPCOUNT(sequence->channels);
+	necessary = num_requested_channels * sizeof(int32_t);
+
+	if (sequence->options) {
+		necessary *= (1 + sequence->options->extra_samplings);
+	}
+
+	if (sequence->buffer_size < necessary) {
+		LOG_ERR("buffer size %u is too small, need %u", sequence->buffer_size, necessary);
+		return -ENOMEM;
+	}
+
+	for (size_t i = 0; i < channel_maximum; ++i) {
+		if ((BIT(i) & sequence->channels) == 0) {
+			continue;
+		}
+
+		if ((BIT(i) & sequence->channels) && !(BIT(i) & data->channels)) {
+			LOG_ERR("Channel-%d not enabled", i);
+			return -EINVAL;
+		}
+
+		if (i >= AD7124_MAX_CHANNELS) {
+			LOG_ERR("invalid channel selection");
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static int adc_ad7124_start_read(const struct device *dev, const struct adc_sequence *sequence,
+				 bool wait)
+{
+	int result;
+	struct adc_ad7124_data *data = dev->data;
+
+	result = adc_ad7124_validate_sequence(dev, sequence);
+	if (result != 0) {
+		LOG_ERR("sequence validation failed");
+		return result;
+	}
+
+	data->buffer = sequence->buffer;
+
+	adc_context_start_read(&data->ctx, sequence);
+
+	if (wait) {
+		result = adc_context_wait_for_completion(&data->ctx);
+	}
+
+	return result;
+}
+
+#if CONFIG_ADC_ASYNC
+static int adc_ad7124_read_async(const struct device *dev, const struct adc_sequence *sequence,
+				 struct k_poll_signal *async)
+{
+	int status;
+	struct adc_ad7124_data *data = dev->data;
+
+	adc_context_lock(&data->ctx, true, async);
+	status = adc_ad7124_start_read(dev, sequence, true);
+	adc_context_release(&data->ctx, status);
+
+	return status;
+}
+
+static int adc_ad7124_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+	int status;
+	struct adc_ad7124_data *data = dev->data;
+
+	adc_context_lock(&data->ctx, false, NULL);
+	status = adc_ad7124_start_read(dev, sequence, true);
+	adc_context_release(&data->ctx, status);
+
+	return status;
+}
+
+#else
+static int adc_ad7124_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+	int status;
+	struct adc_ad7124_data *data = dev->data;
+
+	adc_context_lock(&data->ctx, false, NULL);
+
+	status = adc_ad7124_start_read(dev, sequence, false);
+
+	while (status == 0 && k_sem_take(&data->ctx.sync, K_NO_WAIT) != 0) {
+		status = adc_ad7124_perform_read(dev);
+	}
+
+	adc_context_release(&data->ctx, status);
+
+	return status;
+}
+#endif
+
+#if CONFIG_ADC_ASYNC
+static void adc_ad7124_acquisition_thread(void *p1, void *p2, void *p3)
+{
+	ARG_UNUSED(p2);
+	ARG_UNUSED(p3);
+
+	const struct device *dev = p1;
+
+	while (true) {
+		adc_ad7124_perform_read(dev);
+	}
+}
+#endif /* CONFIG_ADC_ASYNC */
+
+static int adc_ad7124_init(const struct device *dev)
+{
+	const struct adc_ad7124_config *config = dev->config;
+	struct adc_ad7124_data *data = dev->data;
+	int ret;
+
+	data->dev = dev;
+
+	k_sem_init(&data->acquire_signal, 0, 1);
+
+	if (!spi_is_ready_dt(&config->bus)) {
+		LOG_ERR("spi bus %s not ready", config->bus.bus->name);
+		return -ENODEV;
+	}
+
+	ret = adc_ad7124_setup(dev);
+	if (ret) {
+		return ret;
+	}
+
+#if CONFIG_ADC_ASYNC
+	k_tid_t tid = k_thread_create(
+		&data->thread, data->stack, CONFIG_ADI_AD7124_ADC_ACQUISITION_THREAD_STACK_SIZE,
+		adc_ad7124_acquisition_thread, (void *)dev, NULL, NULL,
+		CONFIG_ADI_AD7124_ADC_ACQUISITION_THREAD_INIT_PRIO, 0, K_NO_WAIT);
+	k_thread_name_set(tid, "adc_ad7124");
+#endif /* CONFIG_ADC_ASYNC */
+
+	adc_context_unlock_unconditionally(&data->ctx);
+
+	return 0;
+}
+
+static DEVICE_API(adc, adc_ad7124_api) = {
+	.channel_setup = adc_ad7124_channel_setup,
+	.read = adc_ad7124_read,
+#ifdef CONFIG_ADC_ASYNC
+	.read_async = adc_ad7124_read_async,
+#endif
+	.ref_internal = AD7124_ADC_VREF_MV,
+};
+
+#define ADC_AD7124_INST_DEFINE(inst)                                                               \
+	static const struct adc_ad7124_config adc_ad7124_config##inst = {                          \
+		.bus = SPI_DT_SPEC_INST_GET(                                                       \
+			inst,                                                                      \
+			SPI_OP_MODE_MASTER | SPI_MODE_CPOL | SPI_MODE_CPHA | SPI_WORD_SET(8), 0),  \
+		.resolution = AD7124_RESOLUTION,                                                   \
+		.filter_type_mask = DT_INST_PROP(inst, filter_type_mask),                          \
+		.bipolar_mask = DT_INST_PROP(inst, bipolar_mask),                                  \
+		.inbuf_enable_mask = DT_INST_PROP(inst, inbuf_enable_mask),                        \
+		.refbuf_enable_mask = DT_INST_PROP(inst, refbuf_enable_mask),                      \
+		.adc_mode = DT_INST_PROP(inst, adc_mode),                                          \
+		.power_mode = DT_INST_PROP(inst, power_mode),                                      \
+		.active_device = DT_INST_PROP(inst, active_device),                                \
+		.ref_en = DT_INST_PROP(inst, reference_enable),                                    \
+	};                                                                                         \
+	static struct adc_ad7124_data adc_ad7124_data##inst = {                                    \
+		ADC_CONTEXT_INIT_LOCK(adc_ad7124_data##inst, ctx),                                 \
+		ADC_CONTEXT_INIT_TIMER(adc_ad7124_data##inst, ctx),                                \
+		ADC_CONTEXT_INIT_SYNC(adc_ad7124_data##inst, ctx),                                 \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(inst, adc_ad7124_init, NULL, &adc_ad7124_data##inst,                 \
+			      &adc_ad7124_config##inst, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY,     \
+			      &adc_ad7124_api);
+
+DT_INST_FOREACH_STATUS_OKAY(ADC_AD7124_INST_DEFINE)
diff --git a/drivers/adc/adc_ads114s0x.c b/drivers/adc/adc_ads114s0x.c
deleted file mode 100644
index 36e3eaefac4..00000000000
--- a/drivers/adc/adc_ads114s0x.c
+++ /dev/null
@@ -1,1508 +0,0 @@
-/*
- * Copyright (c) 2023 SILA Embedded Solutions GmbH
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#include <zephyr/device.h>
-#include <zephyr/devicetree.h>
-#include <zephyr/drivers/adc.h>
-#include <zephyr/drivers/adc/ads114s0x.h>
-#include <zephyr/drivers/spi.h>
-#include <zephyr/drivers/gpio.h>
-#include <zephyr/dt-bindings/adc/ads114s0x_adc.h>
-#include <zephyr/logging/log.h>
-#include <zephyr/kernel.h>
-#include <zephyr/sys/__assert.h>
-#include <zephyr/sys/byteorder.h>
-#include <zephyr/sys/util.h>
-
-#define ADC_CONTEXT_USES_KERNEL_TIMER 1
-#define ADC_CONTEXT_WAIT_FOR_COMPLETION_TIMEOUT                                                    \
-	K_MSEC(CONFIG_ADC_ADS114S0X_WAIT_FOR_COMPLETION_TIMEOUT_MS)
-#include "adc_context.h"
-
-LOG_MODULE_REGISTER(ads114s0x, CONFIG_ADC_LOG_LEVEL);
-
-#define ADS114S0X_CLK_FREQ_IN_KHZ                           4096
-#define ADS114S0X_RESET_LOW_TIME_IN_CLOCK_CYCLES            4
-#define ADS114S0X_START_SYNC_PULSE_DURATION_IN_CLOCK_CYCLES 4
-#define ADS114S0X_SETUP_TIME_IN_CLOCK_CYCLES                32
-#define ADS114S0X_INPUT_SELECTION_AINCOM                    12
-#define ADS114S0X_RESOLUTION                                16
-#define ADS114S0X_REF_INTERNAL                              2500
-#define ADS114S0X_GPIO_MAX                                  3
-#define ADS114S0X_POWER_ON_RESET_TIME_IN_US                 2200
-#define ADS114S0X_VBIAS_PIN_MAX                             7
-#define ADS114S0X_VBIAS_PIN_MIN                             0
-
-/* Not mentioned in the datasheet, but instead determined experimentally. */
-#define ADS114S0X_RESET_DELAY_TIME_SAFETY_MARGIN_IN_US 1000
-#define ADS114S0X_RESET_DELAY_TIME_IN_US                                                           \
-	(4096 * 1000 / ADS114S0X_CLK_FREQ_IN_KHZ + ADS114S0X_RESET_DELAY_TIME_SAFETY_MARGIN_IN_US)
-
-#define ADS114S0X_RESET_LOW_TIME_IN_US                                                             \
-	(ADS114S0X_RESET_LOW_TIME_IN_CLOCK_CYCLES * 1000 / ADS114S0X_CLK_FREQ_IN_KHZ)
-#define ADS114S0X_START_SYNC_PULSE_DURATION_IN_US                                                  \
-	(ADS114S0X_START_SYNC_PULSE_DURATION_IN_CLOCK_CYCLES * 1000 / ADS114S0X_CLK_FREQ_IN_KHZ)
-#define ADS114S0X_SETUP_TIME_IN_US                                                                 \
-	(ADS114S0X_SETUP_TIME_IN_CLOCK_CYCLES * 1000 / ADS114S0X_CLK_FREQ_IN_KHZ)
-
-enum ads114s0x_command {
-	ADS114S0X_COMMAND_NOP = 0x00,
-	ADS114S0X_COMMAND_WAKEUP = 0x02,
-	ADS114S0X_COMMAND_POWERDOWN = 0x04,
-	ADS114S0X_COMMAND_RESET = 0x06,
-	ADS114S0X_COMMAND_START = 0x08,
-	ADS114S0X_COMMAND_STOP = 0x0A,
-	ADS114S0X_COMMAND_SYOCAL = 0x16,
-	ADS114S0X_COMMAND_SYGCAL = 0x17,
-	ADS114S0X_COMMAND_SFOCAL = 0x19,
-	ADS114S0X_COMMAND_RDATA = 0x12,
-	ADS114S0X_COMMAND_RREG = 0x20,
-	ADS114S0X_COMMAND_WREG = 0x40,
-};
-
-enum ads114s0x_register {
-	ADS114S0X_REGISTER_ID = 0x00,
-	ADS114S0X_REGISTER_STATUS = 0x01,
-	ADS114S0X_REGISTER_INPMUX = 0x02,
-	ADS114S0X_REGISTER_PGA = 0x03,
-	ADS114S0X_REGISTER_DATARATE = 0x04,
-	ADS114S0X_REGISTER_REF = 0x05,
-	ADS114S0X_REGISTER_IDACMAG = 0x06,
-	ADS114S0X_REGISTER_IDACMUX = 0x07,
-	ADS114S0X_REGISTER_VBIAS = 0x08,
-	ADS114S0X_REGISTER_SYS = 0x09,
-	ADS114S0X_REGISTER_OFCAL0 = 0x0B,
-	ADS114S0X_REGISTER_OFCAL1 = 0x0C,
-	ADS114S0X_REGISTER_FSCAL0 = 0x0E,
-	ADS114S0X_REGISTER_FSCAL1 = 0x0F,
-	ADS114S0X_REGISTER_GPIODAT = 0x10,
-	ADS114S0X_REGISTER_GPIOCON = 0x11,
-};
-
-#define ADS114S0X_REGISTER_GET_VALUE(value, pos, length)                                           \
-	FIELD_GET(GENMASK(pos + length - 1, pos), value)
-#define ADS114S0X_REGISTER_SET_VALUE(target, value, pos, length)                                   \
-	target &= ~GENMASK(pos + length - 1, pos);                                                 \
-	target |= FIELD_PREP(GENMASK(pos + length - 1, pos), value)
-
-#define ADS114S0X_REGISTER_ID_DEV_ID_LENGTH 3
-#define ADS114S0X_REGISTER_ID_DEV_ID_POS    0
-#define ADS114S0X_REGISTER_ID_DEV_ID_GET(value)                                                    \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_ID_DEV_ID_POS,                      \
-				     ADS114S0X_REGISTER_ID_DEV_ID_LENGTH)
-#define ADS114S0X_REGISTER_ID_DEV_ID_SET(target, value)                                            \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_ID_DEV_ID_POS,              \
-				     ADS114S0X_REGISTER_ID_DEV_ID_LENGTH)
-#define ADS114S0X_REGISTER_STATUS_FL_POR_LENGTH 1
-#define ADS114S0X_REGISTER_STATUS_FL_POR_POS    7
-#define ADS114S0X_REGISTER_STATUS_FL_POR_GET(value)                                                \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_POR_POS,                  \
-				     ADS114S0X_REGISTER_STATUS_FL_POR_LENGTH)
-#define ADS114S0X_REGISTER_STATUS_FL_POR_SET(target, value)                                        \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_POR_POS,          \
-				     ADS114S0X_REGISTER_STATUS_FL_POR_LENGTH)
-#define ADS114S0X_REGISTER_STATUS_NOT_RDY_LENGTH 1
-#define ADS114S0X_REGISTER_STATUS_NOT_RDY_POS    6
-#define ADS114S0X_REGISTER_STATUS_NOT_RDY_GET(value)                                               \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_NOT_RDY_POS,                 \
-				     ADS114S0X_REGISTER_STATUS_NOT_RDY_LENGTH)
-#define ADS114S0X_REGISTER_STATUS_NOT_RDY_SET(target, value)                                       \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_NOT_RDY_POS,         \
-				     ADS114S0X_REGISTER_STATUS_NOT_RDY_LENGTH)
-#define ADS114S0X_REGISTER_STATUS_FL_P_RAILP_LENGTH 1
-#define ADS114S0X_REGISTER_STATUS_FL_P_RAILP_POS    5
-#define ADS114S0X_REGISTER_STATUS_FL_P_RAILP_GET(value)                                            \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_P_RAILP_POS,              \
-				     ADS114S0X_REGISTER_STATUS_FL_P_RAILP_LENGTH)
-#define ADS114S0X_REGISTER_STATUS_FL_P_RAILP_SET(target, value)                                    \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_P_RAILP_POS,      \
-				     ADS114S0X_REGISTER_STATUS_FL_P_RAILP_LENGTH)
-#define ADS114S0X_REGISTER_STATUS_FL_P_RAILN_LENGTH 1
-#define ADS114S0X_REGISTER_STATUS_FL_P_RAILN_POS    4
-#define ADS114S0X_REGISTER_STATUS_FL_P_RAILN_GET(value)                                            \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_P_RAILN_POS,              \
-				     ADS114S0X_REGISTER_STATUS_FL_P_RAILN_LENGTH)
-#define ADS114S0X_REGISTER_STATUS_FL_P_RAILN_SET(target, value)                                    \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_P_RAILN_POS,      \
-				     ADS114S0X_REGISTER_STATUS_FL_P_RAILN_LENGTH)
-#define ADS114S0X_REGISTER_STATUS_FL_N_RAILP_LENGTH 1
-#define ADS114S0X_REGISTER_STATUS_FL_N_RAILP_POS    3
-#define ADS114S0X_REGISTER_STATUS_FL_N_RAILP_GET(value)                                            \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_N_RAILP_POS,              \
-				     ADS114S0X_REGISTER_STATUS_FL_N_RAILP_LENGTH)
-#define ADS114S0X_REGISTER_STATUS_FL_N_RAILP_SET(target, value)                                    \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_N_RAILP_POS,      \
-				     ADS114S0X_REGISTER_STATUS_FL_N_RAILP_LENGTH)
-#define ADS114S0X_REGISTER_STATUS_FL_N_RAILN_LENGTH 1
-#define ADS114S0X_REGISTER_STATUS_FL_N_RAILN_POS    2
-#define ADS114S0X_REGISTER_STATUS_FL_N_RAILN_GET(value)                                            \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_N_RAILN_POS,              \
-				     ADS114S0X_REGISTER_STATUS_FL_N_RAILN_LENGTH)
-#define ADS114S0X_REGISTER_STATUS_FL_N_RAILN_SET(target, value)                                    \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_N_RAILN_POS,      \
-				     ADS114S0X_REGISTER_STATUS_FL_N_RAILN_LENGTH)
-#define ADS114S0X_REGISTER_STATUS_FL_REF_L1_LENGTH 1
-#define ADS114S0X_REGISTER_STATUS_FL_REF_L1_POS    1
-#define ADS114S0X_REGISTER_STATUS_FL_REF_L1_GET(value)                                             \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_REF_L1_POS,               \
-				     ADS114S0X_REGISTER_STATUS_FL_REF_L1_LENGTH)
-#define ADS114S0X_REGISTER_STATUS_FL_REF_L1_SET(target, value)                                     \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_REF_L1_POS,       \
-				     ADS114S0X_REGISTER_STATUS_FL_REF_L1_LENGTH)
-#define ADS114S0X_REGISTER_STATUS_FL_REF_L0_LENGTH 1
-#define ADS114S0X_REGISTER_STATUS_FL_REF_L0_POS    0
-#define ADS114S0X_REGISTER_STATUS_FL_REF_L0_GET(value)                                             \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_STATUS_FL_REF_L0_POS,               \
-				     ADS114S0X_REGISTER_STATUS_FL_REF_L0_LENGTH)
-#define ADS114S0X_REGISTER_STATUS_FL_REF_L0_SET(target, value)                                     \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_STATUS_FL_REF_L0_POS,       \
-				     ADS114S0X_REGISTER_STATUS_FL_REF_L0_LENGTH)
-#define ADS114S0X_REGISTER_INPMUX_MUXP_LENGTH 4
-#define ADS114S0X_REGISTER_INPMUX_MUXP_POS    4
-#define ADS114S0X_REGISTER_INPMUX_MUXP_GET(value)                                                  \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_INPMUX_MUXP_POS,                    \
-				     ADS114S0X_REGISTER_INPMUX_MUXP_LENGTH)
-#define ADS114S0X_REGISTER_INPMUX_MUXP_SET(target, value)                                          \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_INPMUX_MUXP_POS,            \
-				     ADS114S0X_REGISTER_INPMUX_MUXP_LENGTH)
-#define ADS114S0X_REGISTER_INPMUX_MUXN_LENGTH 4
-#define ADS114S0X_REGISTER_INPMUX_MUXN_POS    0
-#define ADS114S0X_REGISTER_INPMUX_MUXN_GET(value)                                                  \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_INPMUX_MUXN_POS,                    \
-				     ADS114S0X_REGISTER_INPMUX_MUXN_LENGTH)
-#define ADS114S0X_REGISTER_INPMUX_MUXN_SET(target, value)                                          \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_INPMUX_MUXN_POS,            \
-				     ADS114S0X_REGISTER_INPMUX_MUXN_LENGTH)
-#define ADS114S0X_REGISTER_PGA_DELAY_LENGTH 3
-#define ADS114S0X_REGISTER_PGA_DELAY_POS    5
-#define ADS114S0X_REGISTER_PGA_DELAY_GET(value)                                                    \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_PGA_DELAY_POS,                      \
-				     ADS114S0X_REGISTER_PGA_DELAY_LENGTH)
-#define ADS114S0X_REGISTER_PGA_DELAY_SET(target, value)                                            \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_PGA_DELAY_POS,              \
-				     ADS114S0X_REGISTER_PGA_DELAY_LENGTH)
-#define ADS114S0X_REGISTER_PGA_PGA_EN_LENGTH 2
-#define ADS114S0X_REGISTER_PGA_PGA_EN_POS    3
-#define ADS114S0X_REGISTER_PGA_PGA_EN_GET(value)                                                   \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_PGA_PGA_EN_POS,                     \
-				     ADS114S0X_REGISTER_PGA_PGA_EN_LENGTH)
-#define ADS114S0X_REGISTER_PGA_PGA_EN_SET(target, value)                                           \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_PGA_PGA_EN_POS,             \
-				     ADS114S0X_REGISTER_PGA_PGA_EN_LENGTH)
-#define ADS114S0X_REGISTER_PGA_GAIN_LENGTH 3
-#define ADS114S0X_REGISTER_PGA_GAIN_POS    0
-#define ADS114S0X_REGISTER_PGA_GAIN_GET(value)                                                     \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_PGA_GAIN_POS,                       \
-				     ADS114S0X_REGISTER_PGA_GAIN_LENGTH)
-#define ADS114S0X_REGISTER_PGA_GAIN_SET(target, value)                                             \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_PGA_GAIN_POS,               \
-				     ADS114S0X_REGISTER_PGA_GAIN_LENGTH)
-#define ADS114S0X_REGISTER_DATARATE_G_CHOP_LENGTH 1
-#define ADS114S0X_REGISTER_DATARATE_G_CHOP_POS    7
-#define ADS114S0X_REGISTER_DATARATE_G_CHOP_GET(value)                                              \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_G_CHOP_POS,                \
-				     ADS114S0X_REGISTER_DATARATE_G_CHOP_LENGTH)
-#define ADS114S0X_REGISTER_DATARATE_G_CHOP_SET(target, value)                                      \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_G_CHOP_POS,        \
-				     ADS114S0X_REGISTER_DATARATE_G_CHOP_LENGTH)
-#define ADS114S0X_REGISTER_DATARATE_CLK_LENGTH 1
-#define ADS114S0X_REGISTER_DATARATE_CLK_POS    6
-#define ADS114S0X_REGISTER_DATARATE_CLK_GET(value)                                                 \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_CLK_POS,                   \
-				     ADS114S0X_REGISTER_DATARATE_CLK_LENGTH)
-#define ADS114S0X_REGISTER_DATARATE_CLK_SET(target, value)                                         \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_CLK_POS,           \
-				     ADS114S0X_REGISTER_DATARATE_CLK_LENGTH)
-#define ADS114S0X_REGISTER_DATARATE_MODE_LENGTH 1
-#define ADS114S0X_REGISTER_DATARATE_MODE_POS    5
-#define ADS114S0X_REGISTER_DATARATE_MODE_GET(value)                                                \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_MODE_POS,                  \
-				     ADS114S0X_REGISTER_DATARATE_MODE_LENGTH)
-#define ADS114S0X_REGISTER_DATARATE_MODE_SET(target, value)                                        \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_MODE_POS,          \
-				     ADS114S0X_REGISTER_DATARATE_MODE_LENGTH)
-#define ADS114S0X_REGISTER_DATARATE_FILTER_LENGTH 1
-#define ADS114S0X_REGISTER_DATARATE_FILTER_POS    4
-#define ADS114S0X_REGISTER_DATARATE_FILTER_GET(value)                                              \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_FILTER_POS,                \
-				     ADS114S0X_REGISTER_DATARATE_FILTER_LENGTH)
-#define ADS114S0X_REGISTER_DATARATE_FILTER_SET(target, value)                                      \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_FILTER_POS,        \
-				     ADS114S0X_REGISTER_DATARATE_FILTER_LENGTH)
-#define ADS114S0X_REGISTER_DATARATE_DR_LENGTH 4
-#define ADS114S0X_REGISTER_DATARATE_DR_POS    0
-#define ADS114S0X_REGISTER_DATARATE_DR_GET(value)                                                  \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_DATARATE_DR_POS,                    \
-				     ADS114S0X_REGISTER_DATARATE_DR_LENGTH)
-#define ADS114S0X_REGISTER_DATARATE_DR_SET(target, value)                                          \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_DATARATE_DR_POS,            \
-				     ADS114S0X_REGISTER_DATARATE_DR_LENGTH)
-#define ADS114S0X_REGISTER_REF_FL_REF_EN_LENGTH 2
-#define ADS114S0X_REGISTER_REF_FL_REF_EN_POS    6
-#define ADS114S0X_REGISTER_REF_FL_REF_EN_GET(value)                                                \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_FL_REF_EN_POS,                  \
-				     ADS114S0X_REGISTER_REF_FL_REF_EN_LENGTH)
-#define ADS114S0X_REGISTER_REF_FL_REF_EN_SET(target, value)                                        \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_FL_REF_EN_POS,          \
-				     ADS114S0X_REGISTER_REF_FL_REF_EN_LENGTH)
-#define ADS114S0X_REGISTER_REF_NOT_REFP_BUF_LENGTH 1
-#define ADS114S0X_REGISTER_REF_NOT_REFP_BUF_POS    5
-#define ADS114S0X_REGISTER_REF_NOT_REFP_BUF_GET(value)                                             \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_NOT_REFP_BUF_POS,               \
-				     ADS114S0X_REGISTER_REF_NOT_REFP_BUF_LENGTH)
-#define ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(target, value)                                     \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_NOT_REFP_BUF_POS,       \
-				     ADS114S0X_REGISTER_REF_NOT_REFP_BUF_LENGTH)
-#define ADS114S0X_REGISTER_REF_NOT_REFN_BUF_LENGTH 1
-#define ADS114S0X_REGISTER_REF_NOT_REFN_BUF_POS    4
-#define ADS114S0X_REGISTER_REF_NOT_REFN_BUF_GET(value)                                             \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_NOT_REFN_BUF_POS,               \
-				     ADS114S0X_REGISTER_REF_NOT_REFN_BUF_LENGTH)
-#define ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(target, value)                                     \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_NOT_REFN_BUF_POS,       \
-				     ADS114S0X_REGISTER_REF_NOT_REFN_BUF_LENGTH)
-#define ADS114S0X_REGISTER_REF_REFSEL_LENGTH 2
-#define ADS114S0X_REGISTER_REF_REFSEL_POS    2
-#define ADS114S0X_REGISTER_REF_REFSEL_GET(value)                                                   \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_REFSEL_POS,                     \
-				     ADS114S0X_REGISTER_REF_REFSEL_LENGTH)
-#define ADS114S0X_REGISTER_REF_REFSEL_SET(target, value)                                           \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_REFSEL_POS,             \
-				     ADS114S0X_REGISTER_REF_REFSEL_LENGTH)
-#define ADS114S0X_REGISTER_REF_REFCON_LENGTH 2
-#define ADS114S0X_REGISTER_REF_REFCON_POS    0
-#define ADS114S0X_REGISTER_REF_REFCON_GET(value)                                                   \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_REF_REFCON_POS,                     \
-				     ADS114S0X_REGISTER_REF_REFCON_LENGTH)
-#define ADS114S0X_REGISTER_REF_REFCON_SET(target, value)                                           \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_REF_REFCON_POS,             \
-				     ADS114S0X_REGISTER_REF_REFCON_LENGTH)
-#define ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_LENGTH 1
-#define ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_POS    7
-#define ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_GET(value)                                           \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_POS,             \
-				     ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_LENGTH)
-#define ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_SET(target, value)                                   \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_POS,     \
-				     ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_LENGTH)
-#define ADS114S0X_REGISTER_IDACMAG_PSW_LENGTH 1
-#define ADS114S0X_REGISTER_IDACMAG_PSW_POS    6
-#define ADS114S0X_REGISTER_IDACMAG_PSW_GET(value)                                                  \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMAG_PSW_POS,                    \
-				     ADS114S0X_REGISTER_IDACMAG_PSW_LENGTH)
-#define ADS114S0X_REGISTER_IDACMAG_PSW_SET(target, value)                                          \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMAG_PSW_POS,            \
-				     ADS114S0X_REGISTER_IDACMAG_PSW_LENGTH)
-#define ADS114S0X_REGISTER_IDACMAG_IMAG_LENGTH 4
-#define ADS114S0X_REGISTER_IDACMAG_IMAG_POS    0
-#define ADS114S0X_REGISTER_IDACMAG_IMAG_GET(value)                                                 \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMAG_IMAG_POS,                   \
-				     ADS114S0X_REGISTER_IDACMAG_IMAG_LENGTH)
-#define ADS114S0X_REGISTER_IDACMAG_IMAG_SET(target, value)                                         \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMAG_IMAG_POS,           \
-				     ADS114S0X_REGISTER_IDACMAG_IMAG_LENGTH)
-#define ADS114S0X_REGISTER_IDACMUX_I2MUX_LENGTH 4
-#define ADS114S0X_REGISTER_IDACMUX_I2MUX_POS    4
-#define ADS114S0X_REGISTER_IDACMUX_I2MUX_GET(value)                                                \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMUX_I2MUX_POS,                  \
-				     ADS114S0X_REGISTER_IDACMUX_I2MUX_LENGTH)
-#define ADS114S0X_REGISTER_IDACMUX_I2MUX_SET(target, value)                                        \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMUX_I2MUX_POS,          \
-				     ADS114S0X_REGISTER_IDACMUX_I2MUX_LENGTH)
-#define ADS114S0X_REGISTER_IDACMUX_I1MUX_LENGTH 4
-#define ADS114S0X_REGISTER_IDACMUX_I1MUX_POS    0
-#define ADS114S0X_REGISTER_IDACMUX_I1MUX_GET(value)                                                \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_IDACMUX_I1MUX_POS,                  \
-				     ADS114S0X_REGISTER_IDACMUX_I1MUX_LENGTH)
-#define ADS114S0X_REGISTER_IDACMUX_I1MUX_SET(target, value)                                        \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_IDACMUX_I1MUX_POS,          \
-				     ADS114S0X_REGISTER_IDACMUX_I1MUX_LENGTH)
-#define ADS114S0X_REGISTER_VBIAS_VB_LEVEL_LENGTH 1
-#define ADS114S0X_REGISTER_VBIAS_VB_LEVEL_POS    7
-#define ADS114S0X_REGISTER_VBIAS_VB_LEVEL_GET(value)                                               \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_VBIAS_VB_LEVEL_POS,                 \
-				     ADS114S0X_REGISTER_VBIAS_VB_LEVEL_LENGTH)
-#define ADS114S0X_REGISTER_VBIAS_VB_LEVEL_SET(target, value)                                       \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_VBIAS_VB_LEVEL_POS,         \
-				     ADS114S0X_REGISTER_VBIAS_VB_LEVEL_LENGTH)
-#define ADS114S0X_REGISTER_GPIODAT_DIR_LENGTH 4
-#define ADS114S0X_REGISTER_GPIODAT_DIR_POS    4
-#define ADS114S0X_REGISTER_GPIODAT_DIR_GET(value)                                                  \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_GPIODAT_DIR_POS,                    \
-				     ADS114S0X_REGISTER_GPIODAT_DIR_LENGTH)
-#define ADS114S0X_REGISTER_GPIODAT_DIR_SET(target, value)                                          \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_GPIODAT_DIR_POS,            \
-				     ADS114S0X_REGISTER_GPIODAT_DIR_LENGTH)
-#define ADS114S0X_REGISTER_GPIODAT_DAT_LENGTH 4
-#define ADS114S0X_REGISTER_GPIODAT_DAT_POS    0
-#define ADS114S0X_REGISTER_GPIODAT_DAT_GET(value)                                                  \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_GPIODAT_DAT_POS,                    \
-				     ADS114S0X_REGISTER_GPIODAT_DAT_LENGTH)
-#define ADS114S0X_REGISTER_GPIODAT_DAT_SET(target, value)                                          \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_GPIODAT_DAT_POS,            \
-				     ADS114S0X_REGISTER_GPIODAT_DAT_LENGTH)
-#define ADS114S0X_REGISTER_GPIOCON_CON_LENGTH 4
-#define ADS114S0X_REGISTER_GPIOCON_CON_POS    0
-#define ADS114S0X_REGISTER_GPIOCON_CON_GET(value)                                                  \
-	ADS114S0X_REGISTER_GET_VALUE(value, ADS114S0X_REGISTER_GPIOCON_CON_POS,                    \
-				     ADS114S0X_REGISTER_GPIOCON_CON_LENGTH)
-#define ADS114S0X_REGISTER_GPIOCON_CON_SET(target, value)                                          \
-	ADS114S0X_REGISTER_SET_VALUE(target, value, ADS114S0X_REGISTER_GPIOCON_CON_POS,            \
-				     ADS114S0X_REGISTER_GPIOCON_CON_LENGTH)
-
-/*
- * - AIN0 as positive input
- * - AIN1 as negative input
- */
-#define ADS114S0X_REGISTER_INPMUX_SET_DEFAULTS(target)                                             \
-	ADS114S0X_REGISTER_INPMUX_MUXP_SET(target, 0b0000);                                        \
-	ADS114S0X_REGISTER_INPMUX_MUXN_SET(target, 0b0001)
-/*
- * - disable reference monitor
- * - enable positive reference buffer
- * - disable negative reference buffer
- * - use internal reference
- * - enable internal voltage reference
- */
-#define ADS114S0X_REGISTER_REF_SET_DEFAULTS(target)                                                \
-	ADS114S0X_REGISTER_REF_FL_REF_EN_SET(target, 0b00);                                        \
-	ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(target, 0b0);                                      \
-	ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(target, 0b1);                                      \
-	ADS114S0X_REGISTER_REF_REFSEL_SET(target, 0b10);                                           \
-	ADS114S0X_REGISTER_REF_REFCON_SET(target, 0b01)
-/*
- * - disable global chop
- * - use internal oscillator
- * - single shot conversion mode
- * - low latency filter
- * - 20 samples per second
- */
-#define ADS114S0X_REGISTER_DATARATE_SET_DEFAULTS(target)                                           \
-	ADS114S0X_REGISTER_DATARATE_G_CHOP_SET(target, 0b0);                                       \
-	ADS114S0X_REGISTER_DATARATE_CLK_SET(target, 0b0);                                          \
-	ADS114S0X_REGISTER_DATARATE_MODE_SET(target, 0b1);                                         \
-	ADS114S0X_REGISTER_DATARATE_FILTER_SET(target, 0b1);                                       \
-	ADS114S0X_REGISTER_DATARATE_DR_SET(target, 0b0100)
-/*
- * - delay of 14*t_mod
- * - disable gain
- * - gain 1
- */
-#define ADS114S0X_REGISTER_PGA_SET_DEFAULTS(target)                                                \
-	ADS114S0X_REGISTER_PGA_DELAY_SET(target, 0b000);                                           \
-	ADS114S0X_REGISTER_PGA_PGA_EN_SET(target, 0b00);                                           \
-	ADS114S0X_REGISTER_PGA_GAIN_SET(target, 0b000)
-/*
- * - disable PGA output rail flag
- * - low-side power switch
- * - IDAC off
- */
-#define ADS114S0X_REGISTER_IDACMAG_SET_DEFAULTS(target)                                            \
-	ADS114S0X_REGISTER_IDACMAG_FL_RAIL_EN_SET(target, 0b0);                                    \
-	ADS114S0X_REGISTER_IDACMAG_PSW_SET(target, 0b0);                                           \
-	ADS114S0X_REGISTER_IDACMAG_IMAG_SET(target, 0b0000)
-/*
- * - disconnect IDAC1
- * - disconnect IDAC2
- */
-#define ADS114S0X_REGISTER_IDACMUX_SET_DEFAULTS(target)                                            \
-	ADS114S0X_REGISTER_IDACMUX_I1MUX_SET(target, 0b1111);                                      \
-	ADS114S0X_REGISTER_IDACMUX_I2MUX_SET(target, 0b1111)
-
-struct ads114s0x_config {
-	struct spi_dt_spec bus;
-#if CONFIG_ADC_ASYNC
-	k_thread_stack_t *stack;
-#endif
-	const struct gpio_dt_spec gpio_reset;
-	const struct gpio_dt_spec gpio_data_ready;
-	const struct gpio_dt_spec gpio_start_sync;
-	int idac_current;
-	uint8_t vbias_level;
-};
-
-struct ads114s0x_data {
-	struct adc_context ctx;
-#if CONFIG_ADC_ASYNC
-	struct k_thread thread;
-#endif /* CONFIG_ADC_ASYNC */
-	struct gpio_callback callback_data_ready;
-	struct k_sem data_ready_signal;
-	struct k_sem acquire_signal;
-	int16_t *buffer;
-	int16_t *buffer_ptr;
-#if CONFIG_ADC_ADS114S0X_GPIO
-	struct k_mutex gpio_lock;
-	uint8_t gpio_enabled;   /* one bit per GPIO, 1 = enabled */
-	uint8_t gpio_direction; /* one bit per GPIO, 1 = input */
-	uint8_t gpio_value;     /* one bit per GPIO, 1 = high */
-#endif                          /* CONFIG_ADC_ADS114S0X_GPIO */
-};
-
-static void ads114s0x_data_ready_handler(const struct device *dev, struct gpio_callback *gpio_cb,
-					 uint32_t pins)
-{
-	ARG_UNUSED(dev);
-	ARG_UNUSED(pins);
-
-	struct ads114s0x_data *data =
-		CONTAINER_OF(gpio_cb, struct ads114s0x_data, callback_data_ready);
-
-	k_sem_give(&data->data_ready_signal);
-}
-
-static int ads114s0x_read_register(const struct device *dev,
-				   enum ads114s0x_register register_address, uint8_t *value)
-{
-	const struct ads114s0x_config *config = dev->config;
-	uint8_t buffer_tx[3];
-	uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)];
-	const struct spi_buf tx_buf[] = {{
-		.buf = buffer_tx,
-		.len = ARRAY_SIZE(buffer_tx),
-	}};
-	const struct spi_buf rx_buf[] = {{
-		.buf = buffer_rx,
-		.len = ARRAY_SIZE(buffer_rx),
-	}};
-	const struct spi_buf_set tx = {
-		.buffers = tx_buf,
-		.count = ARRAY_SIZE(tx_buf),
-	};
-	const struct spi_buf_set rx = {
-		.buffers = rx_buf,
-		.count = ARRAY_SIZE(rx_buf),
-	};
-
-	buffer_tx[0] = ((uint8_t)ADS114S0X_COMMAND_RREG) | ((uint8_t)register_address);
-	/* read one register */
-	buffer_tx[1] = 0x00;
-
-	int result = spi_transceive_dt(&config->bus, &tx, &rx);
-
-	if (result != 0) {
-		LOG_ERR("%s: spi_transceive failed with error %i", dev->name, result);
-		return result;
-	}
-
-	*value = buffer_rx[2];
-	LOG_DBG("%s: read from register 0x%02X value 0x%02X", dev->name, register_address, *value);
-
-	return 0;
-}
-
-static int ads114s0x_write_register(const struct device *dev,
-				    enum ads114s0x_register register_address, uint8_t value)
-{
-	const struct ads114s0x_config *config = dev->config;
-	uint8_t buffer_tx[3];
-	const struct spi_buf tx_buf[] = {{
-		.buf = buffer_tx,
-		.len = ARRAY_SIZE(buffer_tx),
-	}};
-	const struct spi_buf_set tx = {
-		.buffers = tx_buf,
-		.count = ARRAY_SIZE(tx_buf),
-	};
-
-	buffer_tx[0] = ((uint8_t)ADS114S0X_COMMAND_WREG) | ((uint8_t)register_address);
-	/* write one register */
-	buffer_tx[1] = 0x00;
-	buffer_tx[2] = value;
-
-	LOG_DBG("%s: writing to register 0x%02X value 0x%02X", dev->name, register_address, value);
-	int result = spi_write_dt(&config->bus, &tx);
-
-	if (result != 0) {
-		LOG_ERR("%s: spi_write failed with error %i", dev->name, result);
-		return result;
-	}
-
-	return 0;
-}
-
-static int ads114s0x_write_multiple_registers(const struct device *dev,
-					      enum ads114s0x_register *register_addresses,
-					      uint8_t *values, size_t count)
-{
-	const struct ads114s0x_config *config = dev->config;
-	uint8_t buffer_tx[2];
-	const struct spi_buf tx_buf[] = {
-		{
-			.buf = buffer_tx,
-			.len = ARRAY_SIZE(buffer_tx),
-		},
-		{
-			.buf = values,
-			.len = count,
-		},
-	};
-	const struct spi_buf_set tx = {
-		.buffers = tx_buf,
-		.count = ARRAY_SIZE(tx_buf),
-	};
-
-	if (count == 0) {
-		LOG_WRN("%s: ignoring the command to write 0 registers", dev->name);
-		return -EINVAL;
-	}
-
-	buffer_tx[0] = ((uint8_t)ADS114S0X_COMMAND_WREG) | ((uint8_t)register_addresses[0]);
-	buffer_tx[1] = count - 1;
-
-	LOG_HEXDUMP_DBG(register_addresses, count, "writing to registers");
-	LOG_HEXDUMP_DBG(values, count, "values");
-
-	/* ensure that the register addresses are in the correct order */
-	for (size_t i = 1; i < count; ++i) {
-		__ASSERT(register_addresses[i - 1] + 1 == register_addresses[i],
-			 "register addresses are not consecutive");
-	}
-
-	int result = spi_write_dt(&config->bus, &tx);
-
-	if (result != 0) {
-		LOG_ERR("%s: spi_write failed with error %i", dev->name, result);
-		return result;
-	}
-
-	return 0;
-}
-
-static int ads114s0x_send_command(const struct device *dev, enum ads114s0x_command command)
-{
-	const struct ads114s0x_config *config = dev->config;
-	uint8_t buffer_tx[1];
-	const struct spi_buf tx_buf[] = {{
-		.buf = buffer_tx,
-		.len = ARRAY_SIZE(buffer_tx),
-	}};
-	const struct spi_buf_set tx = {
-		.buffers = tx_buf,
-		.count = ARRAY_SIZE(tx_buf),
-	};
-
-	buffer_tx[0] = (uint8_t)command;
-
-	LOG_DBG("%s: sending command 0x%02X", dev->name, command);
-	int result = spi_write_dt(&config->bus, &tx);
-
-	if (result != 0) {
-		LOG_ERR("%s: spi_write failed with error %i", dev->name, result);
-		return result;
-	}
-
-	return 0;
-}
-
-static int ads114s0x_channel_setup(const struct device *dev,
-				   const struct adc_channel_cfg *channel_cfg)
-{
-	const struct ads114s0x_config *config = dev->config;
-	uint8_t input_mux = 0;
-	uint8_t reference_control = 0;
-	uint8_t data_rate = 0;
-	uint8_t gain = 0;
-	uint8_t idac_magnitude = 0;
-	uint8_t idac_mux = 0;
-	uint8_t pin_selections[4];
-	uint8_t vbias = 0;
-	size_t pin_selections_size;
-	int result;
-	enum ads114s0x_register register_addresses[7];
-	uint8_t values[ARRAY_SIZE(register_addresses)];
-	uint16_t acquisition_time_value = ADC_ACQ_TIME_VALUE(channel_cfg->acquisition_time);
-	uint16_t acquisition_time_unit = ADC_ACQ_TIME_UNIT(channel_cfg->acquisition_time);
-
-	ADS114S0X_REGISTER_INPMUX_SET_DEFAULTS(gain);
-	ADS114S0X_REGISTER_REF_SET_DEFAULTS(reference_control);
-	ADS114S0X_REGISTER_DATARATE_SET_DEFAULTS(data_rate);
-	ADS114S0X_REGISTER_PGA_SET_DEFAULTS(gain);
-	ADS114S0X_REGISTER_IDACMAG_SET_DEFAULTS(idac_magnitude);
-	ADS114S0X_REGISTER_IDACMUX_SET_DEFAULTS(idac_mux);
-
-	if (channel_cfg->channel_id != 0) {
-		LOG_ERR("%s: only one channel is supported", dev->name);
-		return -EINVAL;
-	}
-
-	/* The ADS114 uses samples per seconds units with the lowest being 2.5SPS
-	 * and with acquisition_time only having 14b for time, this will not fit
-	 * within here for microsecond units. Use Tick units and allow the user to
-	 * specify the ODR directly.
-	 */
-	if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT &&
-	    acquisition_time_unit != ADC_ACQ_TIME_TICKS) {
-		LOG_ERR("%s: invalid acquisition time %i", dev->name,
-			channel_cfg->acquisition_time);
-		return -EINVAL;
-	}
-
-	if (channel_cfg->acquisition_time == ADC_ACQ_TIME_DEFAULT) {
-		ADS114S0X_REGISTER_DATARATE_DR_SET(data_rate, ADS114S0X_CONFIG_DR_20);
-	} else {
-		ADS114S0X_REGISTER_DATARATE_DR_SET(data_rate, acquisition_time_value);
-	}
-
-	switch (channel_cfg->reference) {
-	case ADC_REF_INTERNAL:
-		/* disable negative reference buffer */
-		ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b1);
-		/* disable positive reference buffer */
-		ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b1);
-		/* use internal reference */
-		ADS114S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b10);
-		break;
-	case ADC_REF_EXTERNAL0:
-		/* enable negative reference buffer */
-		ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b0);
-		/* enable positive reference buffer */
-		ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b0);
-		/* use external reference 0*/
-		ADS114S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b00);
-		break;
-	case ADC_REF_EXTERNAL1:
-		/* enable negative reference buffer */
-		ADS114S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b0);
-		/* enable positive reference buffer */
-		ADS114S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b0);
-		/* use external reference 0*/
-		ADS114S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b01);
-		break;
-	default:
-		LOG_ERR("%s: reference %i is not supported", dev->name, channel_cfg->reference);
-		return -EINVAL;
-	}
-
-	if (channel_cfg->differential) {
-		LOG_DBG("%s: configuring channel for a differential measurement from the pins (p, "
-			"n) (%i, %i)",
-			dev->name, channel_cfg->input_positive, channel_cfg->input_negative);
-		if (channel_cfg->input_positive >= ADS114S0X_INPUT_SELECTION_AINCOM) {
-			LOG_ERR("%s: positive channel input %i is invalid", dev->name,
-				channel_cfg->input_positive);
-			return -EINVAL;
-		}
-
-		if (channel_cfg->input_negative >= ADS114S0X_INPUT_SELECTION_AINCOM) {
-			LOG_ERR("%s: negative channel input %i is invalid", dev->name,
-				channel_cfg->input_negative);
-			return -EINVAL;
-		}
-
-		if (channel_cfg->input_positive == channel_cfg->input_negative) {
-			LOG_ERR("%s: negative and positive channel inputs must be different",
-				dev->name);
-			return -EINVAL;
-		}
-
-		ADS114S0X_REGISTER_INPMUX_MUXP_SET(input_mux, channel_cfg->input_positive);
-		ADS114S0X_REGISTER_INPMUX_MUXN_SET(input_mux, channel_cfg->input_negative);
-		pin_selections[0] = channel_cfg->input_positive;
-		pin_selections[1] = channel_cfg->input_negative;
-	} else {
-		LOG_DBG("%s: configuring channel for single ended measurement from input %i",
-			dev->name, channel_cfg->input_positive);
-		if (channel_cfg->input_positive >= ADS114S0X_INPUT_SELECTION_AINCOM) {
-			LOG_ERR("%s: channel input %i is invalid", dev->name,
-				channel_cfg->input_positive);
-			return -EINVAL;
-		}
-
-		ADS114S0X_REGISTER_INPMUX_MUXP_SET(input_mux, channel_cfg->input_positive);
-		ADS114S0X_REGISTER_INPMUX_MUXN_SET(input_mux, ADS114S0X_INPUT_SELECTION_AINCOM);
-		pin_selections[0] = channel_cfg->input_positive;
-		pin_selections[1] = ADS114S0X_INPUT_SELECTION_AINCOM;
-	}
-
-	switch (channel_cfg->gain) {
-	case ADC_GAIN_1:
-		/* set gain value */
-		ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b000);
-		break;
-	case ADC_GAIN_2:
-		ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b001);
-		break;
-	case ADC_GAIN_4:
-		ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b010);
-		break;
-	case ADC_GAIN_8:
-		ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b011);
-		break;
-	case ADC_GAIN_16:
-		ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b100);
-		break;
-	case ADC_GAIN_32:
-		ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b101);
-		break;
-	case ADC_GAIN_64:
-		ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b110);
-		break;
-	case ADC_GAIN_128:
-		ADS114S0X_REGISTER_PGA_GAIN_SET(gain, 0b111);
-		break;
-	default:
-		LOG_ERR("%s: gain value %i not supported", dev->name, channel_cfg->gain);
-		return -EINVAL;
-	}
-
-	if (channel_cfg->gain != ADC_GAIN_1) {
-		/* enable gain */
-		ADS114S0X_REGISTER_PGA_PGA_EN_SET(gain, 0b01);
-	}
-
-	switch (config->idac_current) {
-	case 0:
-		ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0000);
-		break;
-	case 10:
-		ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0001);
-		break;
-	case 50:
-		ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0010);
-		break;
-	case 100:
-		ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0011);
-		break;
-	case 250:
-		ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0100);
-		break;
-	case 500:
-		ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0101);
-		break;
-	case 750:
-		ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0110);
-		break;
-	case 1000:
-		ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0111);
-		break;
-	case 1500:
-		ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b1000);
-		break;
-	case 2000:
-		ADS114S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b1001);
-		break;
-	default:
-		LOG_ERR("%s: IDAC magnitude %i not supported", dev->name, config->idac_current);
-		return -EINVAL;
-	}
-
-	if (channel_cfg->current_source_pin_set) {
-		LOG_DBG("%s: current source pin set to %i and %i", dev->name,
-			channel_cfg->current_source_pin[0], channel_cfg->current_source_pin[1]);
-		if (channel_cfg->current_source_pin[0] > 0b1111) {
-			LOG_ERR("%s: invalid selection %i for I1MUX", dev->name,
-				channel_cfg->current_source_pin[0]);
-			return -EINVAL;
-		}
-
-		if (channel_cfg->current_source_pin[1] > 0b1111) {
-			LOG_ERR("%s: invalid selection %i for I2MUX", dev->name,
-				channel_cfg->current_source_pin[1]);
-			return -EINVAL;
-		}
-
-		ADS114S0X_REGISTER_IDACMUX_I1MUX_SET(idac_mux, channel_cfg->current_source_pin[0]);
-		ADS114S0X_REGISTER_IDACMUX_I2MUX_SET(idac_mux, channel_cfg->current_source_pin[1]);
-		pin_selections[2] = channel_cfg->current_source_pin[0];
-		pin_selections[3] = channel_cfg->current_source_pin[1];
-		pin_selections_size = 4;
-	} else {
-		LOG_DBG("%s: current source pins not set", dev->name);
-		pin_selections_size = 2;
-	}
-
-	for (size_t i = 0; i < pin_selections_size; ++i) {
-		if (pin_selections[i] > ADS114S0X_INPUT_SELECTION_AINCOM) {
-			continue;
-		}
-
-		for (size_t j = i + 1; j < pin_selections_size; ++j) {
-			if (pin_selections[j] > ADS114S0X_INPUT_SELECTION_AINCOM) {
-				continue;
-			}
-
-			if (pin_selections[i] == pin_selections[j]) {
-				LOG_ERR("%s: pins for inputs and current sources must be different",
-					dev->name);
-				return -EINVAL;
-			}
-		}
-	}
-
-	ADS114S0X_REGISTER_VBIAS_VB_LEVEL_SET(vbias, config->vbias_level);
-
-	if ((channel_cfg->vbias_pins &
-	     ~GENMASK(ADS114S0X_VBIAS_PIN_MAX, ADS114S0X_VBIAS_PIN_MIN)) != 0) {
-		LOG_ERR("%s: invalid VBIAS pin selection 0x%08X", dev->name,
-			channel_cfg->vbias_pins);
-		return -EINVAL;
-	}
-
-	vbias |= channel_cfg->vbias_pins;
-
-	register_addresses[0] = ADS114S0X_REGISTER_INPMUX;
-	register_addresses[1] = ADS114S0X_REGISTER_PGA;
-	register_addresses[2] = ADS114S0X_REGISTER_DATARATE;
-	register_addresses[3] = ADS114S0X_REGISTER_REF;
-	register_addresses[4] = ADS114S0X_REGISTER_IDACMAG;
-	register_addresses[5] = ADS114S0X_REGISTER_IDACMUX;
-	register_addresses[6] = ADS114S0X_REGISTER_VBIAS;
-	BUILD_ASSERT(ARRAY_SIZE(register_addresses) == 7);
-	values[0] = input_mux;
-	values[1] = gain;
-	values[2] = data_rate;
-	values[3] = reference_control;
-	values[4] = idac_magnitude;
-	values[5] = idac_mux;
-	values[6] = vbias;
-	BUILD_ASSERT(ARRAY_SIZE(values) == 7);
-
-	result = ads114s0x_write_multiple_registers(dev, register_addresses, values,
-						    ARRAY_SIZE(values));
-
-	if (result != 0) {
-		LOG_ERR("%s: unable to configure registers", dev->name);
-		return result;
-	}
-
-	return 0;
-}
-
-static int ads114s0x_validate_buffer_size(const struct adc_sequence *sequence)
-{
-	size_t needed = sizeof(int16_t);
-
-	if (sequence->options) {
-		needed *= (1 + sequence->options->extra_samplings);
-	}
-
-	if (sequence->buffer_size < needed) {
-		return -ENOMEM;
-	}
-
-	return 0;
-}
-
-static int ads114s0x_validate_sequence(const struct device *dev,
-				       const struct adc_sequence *sequence)
-{
-	if (sequence->resolution != ADS114S0X_RESOLUTION) {
-		LOG_ERR("%s: invalid resolution", dev->name);
-		return -EINVAL;
-	}
-
-	if (sequence->channels != BIT(0)) {
-		LOG_ERR("%s: invalid channel", dev->name);
-		return -EINVAL;
-	}
-
-	if (sequence->oversampling) {
-		LOG_ERR("%s: oversampling is not supported", dev->name);
-		return -EINVAL;
-	}
-
-	return ads114s0x_validate_buffer_size(sequence);
-}
-
-static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
-{
-	struct ads114s0x_data *data = CONTAINER_OF(ctx, struct ads114s0x_data, ctx);
-
-	if (repeat_sampling) {
-		data->buffer = data->buffer_ptr;
-	}
-}
-
-static void adc_context_start_sampling(struct adc_context *ctx)
-{
-	struct ads114s0x_data *data = CONTAINER_OF(ctx, struct ads114s0x_data, ctx);
-
-	data->buffer_ptr = data->buffer;
-	k_sem_give(&data->acquire_signal);
-}
-
-static int ads114s0x_adc_start_read(const struct device *dev, const struct adc_sequence *sequence,
-				    bool wait)
-{
-	int result;
-	struct ads114s0x_data *data = dev->data;
-
-	result = ads114s0x_validate_sequence(dev, sequence);
-
-	if (result != 0) {
-		LOG_ERR("%s: sequence validation failed", dev->name);
-		return result;
-	}
-
-	data->buffer = sequence->buffer;
-
-	adc_context_start_read(&data->ctx, sequence);
-
-	if (wait) {
-		result = adc_context_wait_for_completion(&data->ctx);
-	}
-
-	return result;
-}
-
-static int ads114s0x_send_start_read(const struct device *dev)
-{
-	const struct ads114s0x_config *config = dev->config;
-	int result;
-
-	if (config->gpio_start_sync.port == 0) {
-		result = ads114s0x_send_command(dev, ADS114S0X_COMMAND_START);
-		if (result != 0) {
-			LOG_ERR("%s: unable to send START/SYNC command", dev->name);
-			return result;
-		}
-	} else {
-		result = gpio_pin_set_dt(&config->gpio_start_sync, 1);
-
-		if (result != 0) {
-			LOG_ERR("%s: unable to start ADC operation", dev->name);
-			return result;
-		}
-
-		k_sleep(K_USEC(ADS114S0X_START_SYNC_PULSE_DURATION_IN_US +
-			       ADS114S0X_SETUP_TIME_IN_US));
-
-		result = gpio_pin_set_dt(&config->gpio_start_sync, 0);
-
-		if (result != 0) {
-			LOG_ERR("%s: unable to start ADC operation", dev->name);
-			return result;
-		}
-	}
-
-	return 0;
-}
-
-static int ads114s0x_wait_data_ready(const struct device *dev)
-{
-	struct ads114s0x_data *data = dev->data;
-
-	return k_sem_take(&data->data_ready_signal, ADC_CONTEXT_WAIT_FOR_COMPLETION_TIMEOUT);
-}
-
-static int ads114s0x_read_sample(const struct device *dev, uint16_t *buffer)
-{
-	const struct ads114s0x_config *config = dev->config;
-	uint8_t buffer_tx[3];
-	uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)];
-	const struct spi_buf tx_buf[] = {{
-		.buf = buffer_tx,
-		.len = ARRAY_SIZE(buffer_tx),
-	}};
-	const struct spi_buf rx_buf[] = {{
-		.buf = buffer_rx,
-		.len = ARRAY_SIZE(buffer_rx),
-	}};
-	const struct spi_buf_set tx = {
-		.buffers = tx_buf,
-		.count = ARRAY_SIZE(tx_buf),
-	};
-	const struct spi_buf_set rx = {
-		.buffers = rx_buf,
-		.count = ARRAY_SIZE(rx_buf),
-	};
-
-	buffer_tx[0] = (uint8_t)ADS114S0X_COMMAND_RDATA;
-
-	int result = spi_transceive_dt(&config->bus, &tx, &rx);
-
-	if (result != 0) {
-		LOG_ERR("%s: spi_transceive failed with error %i", dev->name, result);
-		return result;
-	}
-
-	*buffer = sys_get_be16(buffer_rx + 1);
-	LOG_DBG("%s: read ADC sample %i", dev->name, *buffer);
-
-	return 0;
-}
-
-static int ads114s0x_adc_perform_read(const struct device *dev)
-{
-	int result;
-	struct ads114s0x_data *data = dev->data;
-
-	k_sem_take(&data->acquire_signal, K_FOREVER);
-	k_sem_reset(&data->data_ready_signal);
-
-	result = ads114s0x_send_start_read(dev);
-	if (result != 0) {
-		LOG_ERR("%s: unable to start ADC conversion", dev->name);
-		adc_context_complete(&data->ctx, result);
-		return result;
-	}
-
-	result = ads114s0x_wait_data_ready(dev);
-	if (result != 0) {
-		LOG_ERR("%s: waiting for data to be ready failed", dev->name);
-		adc_context_complete(&data->ctx, result);
-		return result;
-	}
-
-	result = ads114s0x_read_sample(dev, data->buffer);
-	if (result != 0) {
-		LOG_ERR("%s: reading sample failed", dev->name);
-		adc_context_complete(&data->ctx, result);
-		return result;
-	}
-
-	data->buffer++;
-
-	adc_context_on_sampling_done(&data->ctx, dev);
-
-	return result;
-}
-
-#if CONFIG_ADC_ASYNC
-static int ads114s0x_adc_read_async(const struct device *dev, const struct adc_sequence *sequence,
-				    struct k_poll_signal *async)
-{
-	int result;
-	struct ads114s0x_data *data = dev->data;
-
-	adc_context_lock(&data->ctx, true, async);
-	result = ads114s0x_adc_start_read(dev, sequence, true);
-	adc_context_release(&data->ctx, result);
-
-	return result;
-}
-
-static int ads114s0x_read(const struct device *dev, const struct adc_sequence *sequence)
-{
-	int result;
-	struct ads114s0x_data *data = dev->data;
-
-	adc_context_lock(&data->ctx, false, NULL);
-	result = ads114s0x_adc_start_read(dev, sequence, true);
-	adc_context_release(&data->ctx, result);
-
-	return result;
-}
-
-#else
-static int ads114s0x_read(const struct device *dev, const struct adc_sequence *sequence)
-{
-	int result;
-	struct ads114s0x_data *data = dev->data;
-
-	adc_context_lock(&data->ctx, false, NULL);
-	result = ads114s0x_adc_start_read(dev, sequence, false);
-
-	while (result == 0 && k_sem_take(&data->ctx.sync, K_NO_WAIT) != 0) {
-		result = ads114s0x_adc_perform_read(dev);
-	}
-
-	adc_context_release(&data->ctx, result);
-	return result;
-}
-#endif
-
-#if CONFIG_ADC_ASYNC
-static void ads114s0x_acquisition_thread(void *p1, void *p2, void *p3)
-{
-	ARG_UNUSED(p2);
-	ARG_UNUSED(p3);
-
-	const struct device *dev = p1;
-	while (true) {
-		ads114s0x_adc_perform_read(dev);
-	}
-}
-#endif
-
-#ifdef CONFIG_ADC_ADS114S0X_GPIO
-static int ads114s0x_gpio_write_config(const struct device *dev)
-{
-	struct ads114s0x_data *data = dev->data;
-	enum ads114s0x_register register_addresses[2];
-	uint8_t register_values[ARRAY_SIZE(register_addresses)];
-	uint8_t gpio_dat = 0;
-	uint8_t gpio_con = 0;
-
-	ADS114S0X_REGISTER_GPIOCON_CON_SET(gpio_con, data->gpio_enabled);
-	ADS114S0X_REGISTER_GPIODAT_DAT_SET(gpio_dat, data->gpio_value);
-	ADS114S0X_REGISTER_GPIODAT_DIR_SET(gpio_dat, data->gpio_direction);
-
-	register_values[0] = gpio_dat;
-	register_values[1] = gpio_con;
-	register_addresses[0] = ADS114S0X_REGISTER_GPIODAT;
-	register_addresses[1] = ADS114S0X_REGISTER_GPIOCON;
-	return ads114s0x_write_multiple_registers(dev, register_addresses, register_values,
-						  ARRAY_SIZE(register_values));
-}
-
-static int ads114s0x_gpio_write_value(const struct device *dev)
-{
-	struct ads114s0x_data *data = dev->data;
-	uint8_t gpio_dat = 0;
-
-	ADS114S0X_REGISTER_GPIODAT_DAT_SET(gpio_dat, data->gpio_value);
-	ADS114S0X_REGISTER_GPIODAT_DIR_SET(gpio_dat, data->gpio_direction);
-
-	return ads114s0x_write_register(dev, ADS114S0X_REGISTER_GPIODAT, gpio_dat);
-}
-
-int ads114s0x_gpio_set_output(const struct device *dev, uint8_t pin, bool initial_value)
-{
-	struct ads114s0x_data *data = dev->data;
-	int result = 0;
-
-	if (pin > ADS114S0X_GPIO_MAX) {
-		LOG_ERR("%s: invalid pin %i", dev->name, pin);
-		return -EINVAL;
-	}
-
-	k_mutex_lock(&data->gpio_lock, K_FOREVER);
-
-	data->gpio_enabled |= BIT(pin);
-	data->gpio_direction &= ~BIT(pin);
-
-	if (initial_value) {
-		data->gpio_value |= BIT(pin);
-	} else {
-		data->gpio_value &= ~BIT(pin);
-	}
-
-	result = ads114s0x_gpio_write_config(dev);
-
-	k_mutex_unlock(&data->gpio_lock);
-
-	return result;
-}
-
-int ads114s0x_gpio_set_input(const struct device *dev, uint8_t pin)
-{
-	struct ads114s0x_data *data = dev->data;
-	int result = 0;
-
-	if (pin > ADS114S0X_GPIO_MAX) {
-		LOG_ERR("%s: invalid pin %i", dev->name, pin);
-		return -EINVAL;
-	}
-
-	k_mutex_lock(&data->gpio_lock, K_FOREVER);
-
-	data->gpio_enabled |= BIT(pin);
-	data->gpio_direction |= BIT(pin);
-	data->gpio_value &= ~BIT(pin);
-
-	result = ads114s0x_gpio_write_config(dev);
-
-	k_mutex_unlock(&data->gpio_lock);
-
-	return result;
-}
-
-int ads114s0x_gpio_deconfigure(const struct device *dev, uint8_t pin)
-{
-	struct ads114s0x_data *data = dev->data;
-	int result = 0;
-
-	if (pin > ADS114S0X_GPIO_MAX) {
-		LOG_ERR("%s: invalid pin %i", dev->name, pin);
-		return -EINVAL;
-	}
-
-	k_mutex_lock(&data->gpio_lock, K_FOREVER);
-
-	data->gpio_enabled &= ~BIT(pin);
-	data->gpio_direction |= BIT(pin);
-	data->gpio_value &= ~BIT(pin);
-
-	result = ads114s0x_gpio_write_config(dev);
-
-	k_mutex_unlock(&data->gpio_lock);
-
-	return result;
-}
-
-int ads114s0x_gpio_set_pin_value(const struct device *dev, uint8_t pin, bool value)
-{
-	struct ads114s0x_data *data = dev->data;
-	int result = 0;
-
-	if (pin > ADS114S0X_GPIO_MAX) {
-		LOG_ERR("%s: invalid pin %i", dev->name, pin);
-		return -EINVAL;
-	}
-
-	k_mutex_lock(&data->gpio_lock, K_FOREVER);
-
-	if ((BIT(pin) & data->gpio_enabled) == 0) {
-		LOG_ERR("%s: gpio pin %i not configured", dev->name, pin);
-		result = -EINVAL;
-	} else if ((BIT(pin) & data->gpio_direction) != 0) {
-		LOG_ERR("%s: gpio pin %i not configured as output", dev->name, pin);
-		result = -EINVAL;
-	} else {
-		data->gpio_value |= BIT(pin);
-
-		result = ads114s0x_gpio_write_value(dev);
-	}
-
-	k_mutex_unlock(&data->gpio_lock);
-
-	return result;
-}
-
-int ads114s0x_gpio_get_pin_value(const struct device *dev, uint8_t pin, bool *value)
-{
-	struct ads114s0x_data *data = dev->data;
-	int result = 0;
-	uint8_t gpio_dat;
-
-	if (pin > ADS114S0X_GPIO_MAX) {
-		LOG_ERR("%s: invalid pin %i", dev->name, pin);
-		return -EINVAL;
-	}
-
-	k_mutex_lock(&data->gpio_lock, K_FOREVER);
-
-	if ((BIT(pin) & data->gpio_enabled) == 0) {
-		LOG_ERR("%s: gpio pin %i not configured", dev->name, pin);
-		result = -EINVAL;
-	} else if ((BIT(pin) & data->gpio_direction) == 0) {
-		LOG_ERR("%s: gpio pin %i not configured as input", dev->name, pin);
-		result = -EINVAL;
-	} else {
-		result = ads114s0x_read_register(dev, ADS114S0X_REGISTER_GPIODAT, &gpio_dat);
-		data->gpio_value = ADS114S0X_REGISTER_GPIODAT_DAT_GET(gpio_dat);
-		*value = (BIT(pin) & data->gpio_value) != 0;
-	}
-
-	k_mutex_unlock(&data->gpio_lock);
-
-	return result;
-}
-
-int ads114s0x_gpio_port_get_raw(const struct device *dev, gpio_port_value_t *value)
-{
-	struct ads114s0x_data *data = dev->data;
-	int result = 0;
-	uint8_t gpio_dat;
-
-	k_mutex_lock(&data->gpio_lock, K_FOREVER);
-
-	result = ads114s0x_read_register(dev, ADS114S0X_REGISTER_GPIODAT, &gpio_dat);
-	data->gpio_value = ADS114S0X_REGISTER_GPIODAT_DAT_GET(gpio_dat);
-	*value = data->gpio_value;
-
-	k_mutex_unlock(&data->gpio_lock);
-
-	return result;
-}
-
-int ads114s0x_gpio_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
-				       gpio_port_value_t value)
-{
-	struct ads114s0x_data *data = dev->data;
-	int result = 0;
-
-	k_mutex_lock(&data->gpio_lock, K_FOREVER);
-
-	data->gpio_value = ((data->gpio_value & ~mask) | (mask & value)) & data->gpio_enabled &
-			   ~data->gpio_direction;
-	result = ads114s0x_gpio_write_value(dev);
-
-	k_mutex_unlock(&data->gpio_lock);
-
-	return result;
-}
-
-int ads114s0x_gpio_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
-{
-	struct ads114s0x_data *data = dev->data;
-	int result = 0;
-
-	k_mutex_lock(&data->gpio_lock, K_FOREVER);
-
-	data->gpio_value = (data->gpio_value ^ pins) & data->gpio_enabled & ~data->gpio_direction;
-	result = ads114s0x_gpio_write_value(dev);
-
-	k_mutex_unlock(&data->gpio_lock);
-
-	return result;
-}
-
-#endif /* CONFIG_ADC_ADS114S0X_GPIO */
-
-static int ads114s0x_init(const struct device *dev)
-{
-	uint8_t status = 0;
-	uint8_t reference_control = 0;
-	uint8_t reference_control_read;
-	int result;
-	const struct ads114s0x_config *config = dev->config;
-	struct ads114s0x_data *data = dev->data;
-
-	adc_context_init(&data->ctx);
-
-	k_sem_init(&data->data_ready_signal, 0, 1);
-	k_sem_init(&data->acquire_signal, 0, 1);
-
-#ifdef CONFIG_ADC_ADS114S0X_GPIO
-	k_mutex_init(&data->gpio_lock);
-#endif /* CONFIG_ADC_ADS114S0X_GPIO */
-
-	if (!spi_is_ready_dt(&config->bus)) {
-		LOG_ERR("%s: SPI device is not ready", dev->name);
-		return -ENODEV;
-	}
-
-	if (config->gpio_reset.port != NULL) {
-		result = gpio_pin_configure_dt(&config->gpio_reset, GPIO_OUTPUT_ACTIVE);
-		if (result != 0) {
-			LOG_ERR("%s: failed to initialize GPIO for reset", dev->name);
-			return result;
-		}
-	}
-
-	if (config->gpio_start_sync.port != NULL) {
-		result = gpio_pin_configure_dt(&config->gpio_start_sync, GPIO_OUTPUT_INACTIVE);
-		if (result != 0) {
-			LOG_ERR("%s: failed to initialize GPIO for start/sync", dev->name);
-			return result;
-		}
-	}
-
-	result = gpio_pin_configure_dt(&config->gpio_data_ready, GPIO_INPUT);
-	if (result != 0) {
-		LOG_ERR("%s: failed to initialize GPIO for data ready", dev->name);
-		return result;
-	}
-
-	result = gpio_pin_interrupt_configure_dt(&config->gpio_data_ready, GPIO_INT_EDGE_TO_ACTIVE);
-	if (result != 0) {
-		LOG_ERR("%s: failed to configure data ready interrupt", dev->name);
-		return -EIO;
-	}
-
-	gpio_init_callback(&data->callback_data_ready, ads114s0x_data_ready_handler,
-			   BIT(config->gpio_data_ready.pin));
-	result = gpio_add_callback(config->gpio_data_ready.port, &data->callback_data_ready);
-	if (result != 0) {
-		LOG_ERR("%s: failed to add data ready callback", dev->name);
-		return -EIO;
-	}
-
-#if CONFIG_ADC_ASYNC
-	k_tid_t tid = k_thread_create(&data->thread, config->stack,
-				      CONFIG_ADC_ADS114S0X_ACQUISITION_THREAD_STACK_SIZE,
-				      ads114s0x_acquisition_thread, (void *)dev, NULL, NULL,
-				      CONFIG_ADC_ADS114S0X_ASYNC_THREAD_INIT_PRIO, 0, K_NO_WAIT);
-	k_thread_name_set(tid, "adc_ads114s0x");
-#endif
-
-	k_busy_wait(ADS114S0X_POWER_ON_RESET_TIME_IN_US);
-
-	if (config->gpio_reset.port == NULL) {
-		result = ads114s0x_send_command(dev, ADS114S0X_COMMAND_RESET);
-		if (result != 0) {
-			LOG_ERR("%s: unable to send RESET command", dev->name);
-			return result;
-		}
-	} else {
-		k_busy_wait(ADS114S0X_RESET_LOW_TIME_IN_US);
-		gpio_pin_set_dt(&config->gpio_reset, 0);
-	}
-
-	k_busy_wait(ADS114S0X_RESET_DELAY_TIME_IN_US);
-
-	result = ads114s0x_read_register(dev, ADS114S0X_REGISTER_STATUS, &status);
-	if (result != 0) {
-		LOG_ERR("%s: unable to read status register", dev->name);
-		return result;
-	}
-
-	if (ADS114S0X_REGISTER_STATUS_NOT_RDY_GET(status) == 0x01) {
-		LOG_ERR("%s: ADS114 is not yet ready", dev->name);
-		return -EBUSY;
-	}
-
-	/*
-	 * Activate internal voltage reference during initialization to
-	 * avoid the necessary setup time for it to settle later on.
-	 */
-	ADS114S0X_REGISTER_REF_SET_DEFAULTS(reference_control);
-
-	result = ads114s0x_write_register(dev, ADS114S0X_REGISTER_REF, reference_control);
-	if (result != 0) {
-		LOG_ERR("%s: unable to set default reference control values", dev->name);
-		return result;
-	}
-
-	/*
-	 * Ensure that the internal voltage reference is active.
-	 */
-	result = ads114s0x_read_register(dev, ADS114S0X_REGISTER_REF, &reference_control_read);
-	if (result != 0) {
-		LOG_ERR("%s: unable to read reference control values", dev->name);
-		return result;
-	}
-
-	if (reference_control != reference_control_read) {
-		LOG_ERR("%s: reference control register is incorrect: 0x%02X", dev->name,
-			reference_control_read);
-		return -EIO;
-	}
-
-#ifdef CONFIG_ADC_ADS114S0X_GPIO
-	data->gpio_enabled = 0x00;
-	data->gpio_direction = 0x0F;
-	data->gpio_value = 0x00;
-
-	result = ads114s0x_gpio_write_config(dev);
-
-	if (result != 0) {
-		LOG_ERR("%s: unable to configure defaults for GPIOs", dev->name);
-		return result;
-	}
-#endif
-
-	adc_context_unlock_unconditionally(&data->ctx);
-
-	return result;
-}
-
-static DEVICE_API(adc, api) = {
-	.channel_setup = ads114s0x_channel_setup,
-	.read = ads114s0x_read,
-	.ref_internal = ADS114S0X_REF_INTERNAL,
-#ifdef CONFIG_ADC_ASYNC
-	.read_async = ads114s0x_adc_read_async,
-#endif
-};
-
-BUILD_ASSERT(CONFIG_ADC_INIT_PRIORITY > CONFIG_SPI_INIT_PRIORITY,
-	     "CONFIG_ADC_INIT_PRIORITY must be higher than CONFIG_SPI_INIT_PRIORITY");
-
-#define DT_DRV_COMPAT ti_ads114s08
-
-#define ADC_ADS114S0X_INST_DEFINE(n)                                                               \
-	IF_ENABLED(                                                                                \
-		CONFIG_ADC_ASYNC,                                                                  \
-		(static K_KERNEL_STACK_DEFINE(                                                     \
-			 thread_stack_##n, CONFIG_ADC_ADS114S0X_ACQUISITION_THREAD_STACK_SIZE);))  \
-	static const struct ads114s0x_config config_##n = {                                        \
-		.bus = SPI_DT_SPEC_INST_GET(                                                       \
-			n, SPI_OP_MODE_MASTER | SPI_MODE_CPHA | SPI_WORD_SET(8), 0),               \
-		IF_ENABLED(CONFIG_ADC_ASYNC, (.stack = thread_stack_##n,))                         \
-		.gpio_reset = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {0}),                       \
-		.gpio_data_ready = GPIO_DT_SPEC_INST_GET(n, drdy_gpios),                           \
-		.gpio_start_sync = GPIO_DT_SPEC_INST_GET_OR(n, start_sync_gpios, {0}),             \
-		.idac_current = DT_INST_PROP(n, idac_current),                                     \
-		.vbias_level = DT_INST_PROP(n, vbias_level),                                       \
-	};                                                                                         \
-	static struct ads114s0x_data data_##n;                                                     \
-	DEVICE_DT_INST_DEFINE(n, ads114s0x_init, NULL, &data_##n, &config_##n, POST_KERNEL,        \
-			      CONFIG_ADC_INIT_PRIORITY, &api);
-
-DT_INST_FOREACH_STATUS_OKAY(ADC_ADS114S0X_INST_DEFINE);
diff --git a/drivers/adc/adc_ads131m02.c b/drivers/adc/adc_ads131m02.c
index bda053840ef..cde5aedda36 100644
--- a/drivers/adc/adc_ads131m02.c
+++ b/drivers/adc/adc_ads131m02.c
@@ -648,7 +648,7 @@ int ads131m02_set_power_mode(const struct device *dev,
 	return ads131m02_reg_write(dev, ADS131M02_CLOCK_REG, temp);
 }
 
-static const struct adc_driver_api ads131m02_api = {
+static DEVICE_API(adc, ads131m02_api) = {
 	.channel_setup = ads131m02_channel_setup,
 	.read = ads131m02_read,
 	.ref_internal = ADS131M02_REF_INTERNAL,
diff --git a/drivers/adc/adc_ads1x4s0x.c b/drivers/adc/adc_ads1x4s0x.c
new file mode 100644
index 00000000000..c5d15d072e3
--- /dev/null
+++ b/drivers/adc/adc_ads1x4s0x.c
@@ -0,0 +1,1630 @@
+/*
+ * Copyright (c) 2023 SILA Embedded Solutions GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/adc/ads1x4s0x.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/dt-bindings/adc/ads1x4s0x_adc.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util.h>
+
+#define ADS1X4S0X_HAS_16_BIT_DEV                                                                   \
+	(DT_HAS_COMPAT_STATUS_OKAY(ti_ads114s06) || DT_HAS_COMPAT_STATUS_OKAY(ti_ads114s08))
+#define ADS1X4S0X_HAS_24_BIT_DEV                                                                   \
+	(DT_HAS_COMPAT_STATUS_OKAY(ti_ads124s06) || DT_HAS_COMPAT_STATUS_OKAY(ti_ads124s08))
+
+#define ADC_CONTEXT_USES_KERNEL_TIMER 1
+#define ADC_CONTEXT_WAIT_FOR_COMPLETION_TIMEOUT                                                    \
+	K_MSEC(CONFIG_ADC_ADS1X4S0X_WAIT_FOR_COMPLETION_TIMEOUT_MS)
+#include "adc_context.h"
+
+LOG_MODULE_REGISTER(ads1x4s0x, CONFIG_ADC_LOG_LEVEL);
+
+#define ADS1X4S0X_CLK_FREQ_IN_KHZ                           4096
+#define ADS1X4S0X_RESET_LOW_TIME_IN_CLOCK_CYCLES            4
+#define ADS1X4S0X_START_SYNC_PULSE_DURATION_IN_CLOCK_CYCLES 4
+#define ADS1X4S0X_SETUP_TIME_IN_CLOCK_CYCLES                32
+#define ADS1X4S0X_INPUT_SELECTION_AINCOM                    12
+#define ADS1X4S0X_REF_INTERNAL                              2500
+#define ADS1X4S0X_GPIO_MAX                                  3
+#define ADS1X4S0X_POWER_ON_RESET_TIME_IN_US                 2200
+#define ADS1X4S0X_VBIAS_PIN_MAX                             7
+#define ADS1X4S0X_VBIAS_PIN_MIN                             0
+
+/* Not mentioned in the datasheet, but instead determined experimentally. */
+#define ADS1X4S0X_RESET_DELAY_TIME_SAFETY_MARGIN_IN_US 1000
+#define ADS1X4S0X_RESET_DELAY_TIME_IN_US                                                           \
+	(4096 * 1000 / ADS1X4S0X_CLK_FREQ_IN_KHZ + ADS1X4S0X_RESET_DELAY_TIME_SAFETY_MARGIN_IN_US)
+
+#define ADS1X4S0X_RESET_LOW_TIME_IN_US                                                             \
+	(ADS1X4S0X_RESET_LOW_TIME_IN_CLOCK_CYCLES * 1000 / ADS1X4S0X_CLK_FREQ_IN_KHZ)
+#define ADS1X4S0X_START_SYNC_PULSE_DURATION_IN_US                                                  \
+	(ADS1X4S0X_START_SYNC_PULSE_DURATION_IN_CLOCK_CYCLES * 1000 / ADS1X4S0X_CLK_FREQ_IN_KHZ)
+#define ADS1X4S0X_SETUP_TIME_IN_US                                                                 \
+	(ADS1X4S0X_SETUP_TIME_IN_CLOCK_CYCLES * 1000 / ADS1X4S0X_CLK_FREQ_IN_KHZ)
+
+enum ads1x4s0x_command {
+	ADS1X4S0X_COMMAND_NOP = 0x00,
+	ADS1X4S0X_COMMAND_WAKEUP = 0x02,
+	ADS1X4S0X_COMMAND_POWERDOWN = 0x04,
+	ADS1X4S0X_COMMAND_RESET = 0x06,
+	ADS1X4S0X_COMMAND_START = 0x08,
+	ADS1X4S0X_COMMAND_STOP = 0x0A,
+	ADS1X4S0X_COMMAND_SYOCAL = 0x16,
+	ADS1X4S0X_COMMAND_SYGCAL = 0x17,
+	ADS1X4S0X_COMMAND_SFOCAL = 0x19,
+	ADS1X4S0X_COMMAND_RDATA = 0x12,
+	ADS1X4S0X_COMMAND_RREG = 0x20,
+	ADS1X4S0X_COMMAND_WREG = 0x40,
+};
+
+enum ads1x4s0x_register {
+	ADS1X4S0X_REGISTER_ID = 0x00,
+	ADS1X4S0X_REGISTER_STATUS = 0x01,
+	ADS1X4S0X_REGISTER_INPMUX = 0x02,
+	ADS1X4S0X_REGISTER_PGA = 0x03,
+	ADS1X4S0X_REGISTER_DATARATE = 0x04,
+	ADS1X4S0X_REGISTER_REF = 0x05,
+	ADS1X4S0X_REGISTER_IDACMAG = 0x06,
+	ADS1X4S0X_REGISTER_IDACMUX = 0x07,
+	ADS1X4S0X_REGISTER_VBIAS = 0x08,
+	ADS1X4S0X_REGISTER_SYS = 0x09,
+	ADS1X4S0X_REGISTER_GPIODAT = 0x10,
+	ADS1X4S0X_REGISTER_GPIOCON = 0x11,
+	ADS114S0X_REGISTER_OFCAL0 = 0x0B,
+	ADS114S0X_REGISTER_OFCAL1 = 0x0C,
+	ADS114S0X_REGISTER_FSCAL0 = 0x0E,
+	ADS114S0X_REGISTER_FSCAL1 = 0x0F,
+	ADS124S0X_REGISTER_OFCAL0 = 0x0A,
+	ADS124S0X_REGISTER_OFCAL1 = 0x0B,
+	ADS124S0X_REGISTER_OFCAL2 = 0x0C,
+	ADS124S0X_REGISTER_FSCAL0 = 0x0E,
+	ADS124S0X_REGISTER_FSCAL1 = 0x0F,
+	ADS124S0X_REGISTER_FSCAL2 = 0x0F,
+};
+
+#define ADS1X4S0X_REGISTER_GET_VALUE(value, pos, length)                                           \
+	FIELD_GET(GENMASK(pos + length - 1, pos), value)
+#define ADS1X4S0X_REGISTER_SET_VALUE(target, value, pos, length)                                   \
+	target &= ~GENMASK(pos + length - 1, pos);                                                 \
+	target |= FIELD_PREP(GENMASK(pos + length - 1, pos), value)
+
+#define ADS1X4S0X_REGISTER_ID_DEV_ID_LENGTH 3
+#define ADS1X4S0X_REGISTER_ID_DEV_ID_POS    0
+#define ADS1X4S0X_REGISTER_ID_DEV_ID_GET(value)                                                    \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_ID_DEV_ID_POS,                      \
+				     ADS1X4S0X_REGISTER_ID_DEV_ID_LENGTH)
+#define ADS1X4S0X_REGISTER_ID_DEV_ID_SET(target, value)                                            \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_ID_DEV_ID_POS,              \
+				     ADS1X4S0X_REGISTER_ID_DEV_ID_LENGTH)
+#define ADS1X4S0X_REGISTER_STATUS_FL_POR_LENGTH 1
+#define ADS1X4S0X_REGISTER_STATUS_FL_POR_POS    7
+#define ADS1X4S0X_REGISTER_STATUS_FL_POR_GET(value)                                                \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_STATUS_FL_POR_POS,                  \
+				     ADS1X4S0X_REGISTER_STATUS_FL_POR_LENGTH)
+#define ADS1X4S0X_REGISTER_STATUS_FL_POR_SET(target, value)                                        \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_STATUS_FL_POR_POS,          \
+				     ADS1X4S0X_REGISTER_STATUS_FL_POR_LENGTH)
+#define ADS1X4S0X_REGISTER_STATUS_NOT_RDY_LENGTH 1
+#define ADS1X4S0X_REGISTER_STATUS_NOT_RDY_POS    6
+#define ADS1X4S0X_REGISTER_STATUS_NOT_RDY_GET(value)                                               \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_STATUS_NOT_RDY_POS,                 \
+				     ADS1X4S0X_REGISTER_STATUS_NOT_RDY_LENGTH)
+#define ADS1X4S0X_REGISTER_STATUS_NOT_RDY_SET(target, value)                                       \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_STATUS_NOT_RDY_POS,         \
+				     ADS1X4S0X_REGISTER_STATUS_NOT_RDY_LENGTH)
+#define ADS1X4S0X_REGISTER_STATUS_FL_P_RAILP_LENGTH 1
+#define ADS1X4S0X_REGISTER_STATUS_FL_P_RAILP_POS    5
+#define ADS1X4S0X_REGISTER_STATUS_FL_P_RAILP_GET(value)                                            \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_STATUS_FL_P_RAILP_POS,              \
+				     ADS1X4S0X_REGISTER_STATUS_FL_P_RAILP_LENGTH)
+#define ADS1X4S0X_REGISTER_STATUS_FL_P_RAILP_SET(target, value)                                    \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_STATUS_FL_P_RAILP_POS,      \
+				     ADS1X4S0X_REGISTER_STATUS_FL_P_RAILP_LENGTH)
+#define ADS1X4S0X_REGISTER_STATUS_FL_P_RAILN_LENGTH 1
+#define ADS1X4S0X_REGISTER_STATUS_FL_P_RAILN_POS    4
+#define ADS1X4S0X_REGISTER_STATUS_FL_P_RAILN_GET(value)                                            \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_STATUS_FL_P_RAILN_POS,              \
+				     ADS1X4S0X_REGISTER_STATUS_FL_P_RAILN_LENGTH)
+#define ADS1X4S0X_REGISTER_STATUS_FL_P_RAILN_SET(target, value)                                    \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_STATUS_FL_P_RAILN_POS,      \
+				     ADS1X4S0X_REGISTER_STATUS_FL_P_RAILN_LENGTH)
+#define ADS1X4S0X_REGISTER_STATUS_FL_N_RAILP_LENGTH 1
+#define ADS1X4S0X_REGISTER_STATUS_FL_N_RAILP_POS    3
+#define ADS1X4S0X_REGISTER_STATUS_FL_N_RAILP_GET(value)                                            \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_STATUS_FL_N_RAILP_POS,              \
+				     ADS1X4S0X_REGISTER_STATUS_FL_N_RAILP_LENGTH)
+#define ADS1X4S0X_REGISTER_STATUS_FL_N_RAILP_SET(target, value)                                    \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_STATUS_FL_N_RAILP_POS,      \
+				     ADS1X4S0X_REGISTER_STATUS_FL_N_RAILP_LENGTH)
+#define ADS1X4S0X_REGISTER_STATUS_FL_N_RAILN_LENGTH 1
+#define ADS1X4S0X_REGISTER_STATUS_FL_N_RAILN_POS    2
+#define ADS1X4S0X_REGISTER_STATUS_FL_N_RAILN_GET(value)                                            \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_STATUS_FL_N_RAILN_POS,              \
+				     ADS1X4S0X_REGISTER_STATUS_FL_N_RAILN_LENGTH)
+#define ADS1X4S0X_REGISTER_STATUS_FL_N_RAILN_SET(target, value)                                    \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_STATUS_FL_N_RAILN_POS,      \
+				     ADS1X4S0X_REGISTER_STATUS_FL_N_RAILN_LENGTH)
+#define ADS1X4S0X_REGISTER_STATUS_FL_REF_L1_LENGTH 1
+#define ADS1X4S0X_REGISTER_STATUS_FL_REF_L1_POS    1
+#define ADS1X4S0X_REGISTER_STATUS_FL_REF_L1_GET(value)                                             \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_STATUS_FL_REF_L1_POS,               \
+				     ADS1X4S0X_REGISTER_STATUS_FL_REF_L1_LENGTH)
+#define ADS1X4S0X_REGISTER_STATUS_FL_REF_L1_SET(target, value)                                     \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_STATUS_FL_REF_L1_POS,       \
+				     ADS1X4S0X_REGISTER_STATUS_FL_REF_L1_LENGTH)
+#define ADS1X4S0X_REGISTER_STATUS_FL_REF_L0_LENGTH 1
+#define ADS1X4S0X_REGISTER_STATUS_FL_REF_L0_POS    0
+#define ADS1X4S0X_REGISTER_STATUS_FL_REF_L0_GET(value)                                             \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_STATUS_FL_REF_L0_POS,               \
+				     ADS1X4S0X_REGISTER_STATUS_FL_REF_L0_LENGTH)
+#define ADS1X4S0X_REGISTER_STATUS_FL_REF_L0_SET(target, value)                                     \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_STATUS_FL_REF_L0_POS,       \
+				     ADS1X4S0X_REGISTER_STATUS_FL_REF_L0_LENGTH)
+#define ADS1X4S0X_REGISTER_INPMUX_MUXP_LENGTH 4
+#define ADS1X4S0X_REGISTER_INPMUX_MUXP_POS    4
+#define ADS1X4S0X_REGISTER_INPMUX_MUXP_GET(value)                                                  \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_INPMUX_MUXP_POS,                    \
+				     ADS1X4S0X_REGISTER_INPMUX_MUXP_LENGTH)
+#define ADS1X4S0X_REGISTER_INPMUX_MUXP_SET(target, value)                                          \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_INPMUX_MUXP_POS,            \
+				     ADS1X4S0X_REGISTER_INPMUX_MUXP_LENGTH)
+#define ADS1X4S0X_REGISTER_INPMUX_MUXN_LENGTH 4
+#define ADS1X4S0X_REGISTER_INPMUX_MUXN_POS    0
+#define ADS1X4S0X_REGISTER_INPMUX_MUXN_GET(value)                                                  \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_INPMUX_MUXN_POS,                    \
+				     ADS1X4S0X_REGISTER_INPMUX_MUXN_LENGTH)
+#define ADS1X4S0X_REGISTER_INPMUX_MUXN_SET(target, value)                                          \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_INPMUX_MUXN_POS,            \
+				     ADS1X4S0X_REGISTER_INPMUX_MUXN_LENGTH)
+#define ADS1X4S0X_REGISTER_PGA_DELAY_LENGTH 3
+#define ADS1X4S0X_REGISTER_PGA_DELAY_POS    5
+#define ADS1X4S0X_REGISTER_PGA_DELAY_GET(value)                                                    \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_PGA_DELAY_POS,                      \
+				     ADS1X4S0X_REGISTER_PGA_DELAY_LENGTH)
+#define ADS1X4S0X_REGISTER_PGA_DELAY_SET(target, value)                                            \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_PGA_DELAY_POS,              \
+				     ADS1X4S0X_REGISTER_PGA_DELAY_LENGTH)
+#define ADS1X4S0X_REGISTER_PGA_PGA_EN_LENGTH 2
+#define ADS1X4S0X_REGISTER_PGA_PGA_EN_POS    3
+#define ADS1X4S0X_REGISTER_PGA_PGA_EN_GET(value)                                                   \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_PGA_PGA_EN_POS,                     \
+				     ADS1X4S0X_REGISTER_PGA_PGA_EN_LENGTH)
+#define ADS1X4S0X_REGISTER_PGA_PGA_EN_SET(target, value)                                           \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_PGA_PGA_EN_POS,             \
+				     ADS1X4S0X_REGISTER_PGA_PGA_EN_LENGTH)
+#define ADS1X4S0X_REGISTER_PGA_GAIN_LENGTH 3
+#define ADS1X4S0X_REGISTER_PGA_GAIN_POS    0
+#define ADS1X4S0X_REGISTER_PGA_GAIN_GET(value)                                                     \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_PGA_GAIN_POS,                       \
+				     ADS1X4S0X_REGISTER_PGA_GAIN_LENGTH)
+#define ADS1X4S0X_REGISTER_PGA_GAIN_SET(target, value)                                             \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_PGA_GAIN_POS,               \
+				     ADS1X4S0X_REGISTER_PGA_GAIN_LENGTH)
+#define ADS1X4S0X_REGISTER_DATARATE_G_CHOP_LENGTH 1
+#define ADS1X4S0X_REGISTER_DATARATE_G_CHOP_POS    7
+#define ADS1X4S0X_REGISTER_DATARATE_G_CHOP_GET(value)                                              \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_DATARATE_G_CHOP_POS,                \
+				     ADS1X4S0X_REGISTER_DATARATE_G_CHOP_LENGTH)
+#define ADS1X4S0X_REGISTER_DATARATE_G_CHOP_SET(target, value)                                      \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_DATARATE_G_CHOP_POS,        \
+				     ADS1X4S0X_REGISTER_DATARATE_G_CHOP_LENGTH)
+#define ADS1X4S0X_REGISTER_DATARATE_CLK_LENGTH 1
+#define ADS1X4S0X_REGISTER_DATARATE_CLK_POS    6
+#define ADS1X4S0X_REGISTER_DATARATE_CLK_GET(value)                                                 \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_DATARATE_CLK_POS,                   \
+				     ADS1X4S0X_REGISTER_DATARATE_CLK_LENGTH)
+#define ADS1X4S0X_REGISTER_DATARATE_CLK_SET(target, value)                                         \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_DATARATE_CLK_POS,           \
+				     ADS1X4S0X_REGISTER_DATARATE_CLK_LENGTH)
+#define ADS1X4S0X_REGISTER_DATARATE_MODE_LENGTH 1
+#define ADS1X4S0X_REGISTER_DATARATE_MODE_POS    5
+#define ADS1X4S0X_REGISTER_DATARATE_MODE_GET(value)                                                \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_DATARATE_MODE_POS,                  \
+				     ADS1X4S0X_REGISTER_DATARATE_MODE_LENGTH)
+#define ADS1X4S0X_REGISTER_DATARATE_MODE_SET(target, value)                                        \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_DATARATE_MODE_POS,          \
+				     ADS1X4S0X_REGISTER_DATARATE_MODE_LENGTH)
+#define ADS1X4S0X_REGISTER_DATARATE_FILTER_LENGTH 1
+#define ADS1X4S0X_REGISTER_DATARATE_FILTER_POS    4
+#define ADS1X4S0X_REGISTER_DATARATE_FILTER_GET(value)                                              \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_DATARATE_FILTER_POS,                \
+				     ADS1X4S0X_REGISTER_DATARATE_FILTER_LENGTH)
+#define ADS1X4S0X_REGISTER_DATARATE_FILTER_SET(target, value)                                      \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_DATARATE_FILTER_POS,        \
+				     ADS1X4S0X_REGISTER_DATARATE_FILTER_LENGTH)
+#define ADS1X4S0X_REGISTER_DATARATE_DR_LENGTH 4
+#define ADS1X4S0X_REGISTER_DATARATE_DR_POS    0
+#define ADS1X4S0X_REGISTER_DATARATE_DR_GET(value)                                                  \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_DATARATE_DR_POS,                    \
+				     ADS1X4S0X_REGISTER_DATARATE_DR_LENGTH)
+#define ADS1X4S0X_REGISTER_DATARATE_DR_SET(target, value)                                          \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_DATARATE_DR_POS,            \
+				     ADS1X4S0X_REGISTER_DATARATE_DR_LENGTH)
+#define ADS1X4S0X_REGISTER_REF_FL_REF_EN_LENGTH 2
+#define ADS1X4S0X_REGISTER_REF_FL_REF_EN_POS    6
+#define ADS1X4S0X_REGISTER_REF_FL_REF_EN_GET(value)                                                \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_REF_FL_REF_EN_POS,                  \
+				     ADS1X4S0X_REGISTER_REF_FL_REF_EN_LENGTH)
+#define ADS1X4S0X_REGISTER_REF_FL_REF_EN_SET(target, value)                                        \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_REF_FL_REF_EN_POS,          \
+				     ADS1X4S0X_REGISTER_REF_FL_REF_EN_LENGTH)
+#define ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_LENGTH 1
+#define ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_POS    5
+#define ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_GET(value)                                             \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_POS,               \
+				     ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_LENGTH)
+#define ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_SET(target, value)                                     \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_POS,       \
+				     ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_LENGTH)
+#define ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_LENGTH 1
+#define ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_POS    4
+#define ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_GET(value)                                             \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_POS,               \
+				     ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_LENGTH)
+#define ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_SET(target, value)                                     \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_POS,       \
+				     ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_LENGTH)
+#define ADS1X4S0X_REGISTER_REF_REFSEL_LENGTH 2
+#define ADS1X4S0X_REGISTER_REF_REFSEL_POS    2
+#define ADS1X4S0X_REGISTER_REF_REFSEL_GET(value)                                                   \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_REF_REFSEL_POS,                     \
+				     ADS1X4S0X_REGISTER_REF_REFSEL_LENGTH)
+#define ADS1X4S0X_REGISTER_REF_REFSEL_SET(target, value)                                           \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_REF_REFSEL_POS,             \
+				     ADS1X4S0X_REGISTER_REF_REFSEL_LENGTH)
+#define ADS1X4S0X_REGISTER_REF_REFCON_LENGTH 2
+#define ADS1X4S0X_REGISTER_REF_REFCON_POS    0
+#define ADS1X4S0X_REGISTER_REF_REFCON_GET(value)                                                   \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_REF_REFCON_POS,                     \
+				     ADS1X4S0X_REGISTER_REF_REFCON_LENGTH)
+#define ADS1X4S0X_REGISTER_REF_REFCON_SET(target, value)                                           \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_REF_REFCON_POS,             \
+				     ADS1X4S0X_REGISTER_REF_REFCON_LENGTH)
+#define ADS1X4S0X_REGISTER_IDACMAG_FL_RAIL_EN_LENGTH 1
+#define ADS1X4S0X_REGISTER_IDACMAG_FL_RAIL_EN_POS    7
+#define ADS1X4S0X_REGISTER_IDACMAG_FL_RAIL_EN_GET(value)                                           \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_IDACMAG_FL_RAIL_EN_POS,             \
+				     ADS1X4S0X_REGISTER_IDACMAG_FL_RAIL_EN_LENGTH)
+#define ADS1X4S0X_REGISTER_IDACMAG_FL_RAIL_EN_SET(target, value)                                   \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_IDACMAG_FL_RAIL_EN_POS,     \
+				     ADS1X4S0X_REGISTER_IDACMAG_FL_RAIL_EN_LENGTH)
+#define ADS1X4S0X_REGISTER_IDACMAG_PSW_LENGTH 1
+#define ADS1X4S0X_REGISTER_IDACMAG_PSW_POS    6
+#define ADS1X4S0X_REGISTER_IDACMAG_PSW_GET(value)                                                  \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_IDACMAG_PSW_POS,                    \
+				     ADS1X4S0X_REGISTER_IDACMAG_PSW_LENGTH)
+#define ADS1X4S0X_REGISTER_IDACMAG_PSW_SET(target, value)                                          \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_IDACMAG_PSW_POS,            \
+				     ADS1X4S0X_REGISTER_IDACMAG_PSW_LENGTH)
+#define ADS1X4S0X_REGISTER_IDACMAG_IMAG_LENGTH 4
+#define ADS1X4S0X_REGISTER_IDACMAG_IMAG_POS    0
+#define ADS1X4S0X_REGISTER_IDACMAG_IMAG_GET(value)                                                 \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_IDACMAG_IMAG_POS,                   \
+				     ADS1X4S0X_REGISTER_IDACMAG_IMAG_LENGTH)
+#define ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(target, value)                                         \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_IDACMAG_IMAG_POS,           \
+				     ADS1X4S0X_REGISTER_IDACMAG_IMAG_LENGTH)
+#define ADS1X4S0X_REGISTER_IDACMUX_I2MUX_LENGTH 4
+#define ADS1X4S0X_REGISTER_IDACMUX_I2MUX_POS    4
+#define ADS1X4S0X_REGISTER_IDACMUX_I2MUX_GET(value)                                                \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_IDACMUX_I2MUX_POS,                  \
+				     ADS1X4S0X_REGISTER_IDACMUX_I2MUX_LENGTH)
+#define ADS1X4S0X_REGISTER_IDACMUX_I2MUX_SET(target, value)                                        \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_IDACMUX_I2MUX_POS,          \
+				     ADS1X4S0X_REGISTER_IDACMUX_I2MUX_LENGTH)
+#define ADS1X4S0X_REGISTER_IDACMUX_I1MUX_LENGTH 4
+#define ADS1X4S0X_REGISTER_IDACMUX_I1MUX_POS    0
+#define ADS1X4S0X_REGISTER_IDACMUX_I1MUX_GET(value)                                                \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_IDACMUX_I1MUX_POS,                  \
+				     ADS1X4S0X_REGISTER_IDACMUX_I1MUX_LENGTH)
+#define ADS1X4S0X_REGISTER_IDACMUX_I1MUX_SET(target, value)                                        \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_IDACMUX_I1MUX_POS,          \
+				     ADS1X4S0X_REGISTER_IDACMUX_I1MUX_LENGTH)
+#define ADS1X4S0X_REGISTER_VBIAS_VB_LEVEL_LENGTH 1
+#define ADS1X4S0X_REGISTER_VBIAS_VB_LEVEL_POS    7
+#define ADS1X4S0X_REGISTER_VBIAS_VB_LEVEL_GET(value)                                               \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_VBIAS_VB_LEVEL_POS,                 \
+				     ADS1X4S0X_REGISTER_VBIAS_VB_LEVEL_LENGTH)
+#define ADS1X4S0X_REGISTER_VBIAS_VB_LEVEL_SET(target, value)                                       \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_VBIAS_VB_LEVEL_POS,         \
+				     ADS1X4S0X_REGISTER_VBIAS_VB_LEVEL_LENGTH)
+#define ADS1X4S0X_REGISTER_GPIODAT_DIR_LENGTH 4
+#define ADS1X4S0X_REGISTER_GPIODAT_DIR_POS    4
+#define ADS1X4S0X_REGISTER_GPIODAT_DIR_GET(value)                                                  \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_GPIODAT_DIR_POS,                    \
+				     ADS1X4S0X_REGISTER_GPIODAT_DIR_LENGTH)
+#define ADS1X4S0X_REGISTER_GPIODAT_DIR_SET(target, value)                                          \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_GPIODAT_DIR_POS,            \
+				     ADS1X4S0X_REGISTER_GPIODAT_DIR_LENGTH)
+#define ADS1X4S0X_REGISTER_GPIODAT_DAT_LENGTH 4
+#define ADS1X4S0X_REGISTER_GPIODAT_DAT_POS    0
+#define ADS1X4S0X_REGISTER_GPIODAT_DAT_GET(value)                                                  \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_GPIODAT_DAT_POS,                    \
+				     ADS1X4S0X_REGISTER_GPIODAT_DAT_LENGTH)
+#define ADS1X4S0X_REGISTER_GPIODAT_DAT_SET(target, value)                                          \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_GPIODAT_DAT_POS,            \
+				     ADS1X4S0X_REGISTER_GPIODAT_DAT_LENGTH)
+#define ADS1X4S0X_REGISTER_GPIOCON_CON_LENGTH 4
+#define ADS1X4S0X_REGISTER_GPIOCON_CON_POS    0
+#define ADS1X4S0X_REGISTER_GPIOCON_CON_GET(value)                                                  \
+	ADS1X4S0X_REGISTER_GET_VALUE(value, ADS1X4S0X_REGISTER_GPIOCON_CON_POS,                    \
+				     ADS1X4S0X_REGISTER_GPIOCON_CON_LENGTH)
+#define ADS1X4S0X_REGISTER_GPIOCON_CON_SET(target, value)                                          \
+	ADS1X4S0X_REGISTER_SET_VALUE(target, value, ADS1X4S0X_REGISTER_GPIOCON_CON_POS,            \
+				     ADS1X4S0X_REGISTER_GPIOCON_CON_LENGTH)
+
+/*
+ * - AIN0 as positive input
+ * - AIN1 as negative input
+ */
+#define ADS1X4S0X_REGISTER_INPMUX_SET_DEFAULTS(target)                                             \
+	ADS1X4S0X_REGISTER_INPMUX_MUXP_SET(target, 0b0000);                                        \
+	ADS1X4S0X_REGISTER_INPMUX_MUXN_SET(target, 0b0001)
+/*
+ * - disable reference monitor
+ * - enable positive reference buffer
+ * - disable negative reference buffer
+ * - use internal reference
+ * - enable internal voltage reference
+ */
+#define ADS1X4S0X_REGISTER_REF_SET_DEFAULTS(target)                                                \
+	ADS1X4S0X_REGISTER_REF_FL_REF_EN_SET(target, 0b00);                                        \
+	ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_SET(target, 0b0);                                      \
+	ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_SET(target, 0b1);                                      \
+	ADS1X4S0X_REGISTER_REF_REFSEL_SET(target, 0b10);                                           \
+	ADS1X4S0X_REGISTER_REF_REFCON_SET(target, 0b01)
+/*
+ * - disable global chop
+ * - use internal oscillator
+ * - single shot conversion mode
+ * - low latency filter
+ * - 20 samples per second
+ */
+#define ADS1X4S0X_REGISTER_DATARATE_SET_DEFAULTS(target)                                           \
+	ADS1X4S0X_REGISTER_DATARATE_G_CHOP_SET(target, 0b0);                                       \
+	ADS1X4S0X_REGISTER_DATARATE_CLK_SET(target, 0b0);                                          \
+	ADS1X4S0X_REGISTER_DATARATE_MODE_SET(target, 0b1);                                         \
+	ADS1X4S0X_REGISTER_DATARATE_FILTER_SET(target, 0b1);                                       \
+	ADS1X4S0X_REGISTER_DATARATE_DR_SET(target, 0b0100)
+/*
+ * - delay of 14*t_mod
+ * - disable gain
+ * - gain 1
+ */
+#define ADS1X4S0X_REGISTER_PGA_SET_DEFAULTS(target)                                                \
+	ADS1X4S0X_REGISTER_PGA_DELAY_SET(target, 0b000);                                           \
+	ADS1X4S0X_REGISTER_PGA_PGA_EN_SET(target, 0b00);                                           \
+	ADS1X4S0X_REGISTER_PGA_GAIN_SET(target, 0b000)
+/*
+ * - disable PGA output rail flag
+ * - low-side power switch
+ * - IDAC off
+ */
+#define ADS1X4S0X_REGISTER_IDACMAG_SET_DEFAULTS(target)                                            \
+	ADS1X4S0X_REGISTER_IDACMAG_FL_RAIL_EN_SET(target, 0b0);                                    \
+	ADS1X4S0X_REGISTER_IDACMAG_PSW_SET(target, 0b0);                                           \
+	ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(target, 0b0000)
+/*
+ * - disconnect IDAC1
+ * - disconnect IDAC2
+ */
+#define ADS1X4S0X_REGISTER_IDACMUX_SET_DEFAULTS(target)                                            \
+	ADS1X4S0X_REGISTER_IDACMUX_I1MUX_SET(target, 0b1111);                                      \
+	ADS1X4S0X_REGISTER_IDACMUX_I2MUX_SET(target, 0b1111)
+
+struct ads1x4s0x_config {
+	struct spi_dt_spec bus;
+#if CONFIG_ADC_ASYNC
+	k_thread_stack_t *stack;
+#endif
+	const struct gpio_dt_spec gpio_reset;
+	const struct gpio_dt_spec gpio_data_ready;
+	const struct gpio_dt_spec gpio_start_sync;
+	int idac_current;
+	uint8_t vbias_level;
+	uint8_t channels;
+	uint8_t resolution;
+};
+
+struct ads1x4s0x_data {
+	struct adc_context ctx;
+#if CONFIG_ADC_ASYNC
+	struct k_thread thread;
+#endif /* CONFIG_ADC_ASYNC */
+	struct gpio_callback callback_data_ready;
+	struct k_sem data_ready_signal;
+	struct k_sem acquire_signal;
+	void *buffer;
+	void *buffer_ptr;
+#if CONFIG_ADC_ADS1X4S0X_GPIO
+	struct k_mutex gpio_lock;
+	uint8_t gpio_enabled;   /* one bit per GPIO, 1 = enabled */
+	uint8_t gpio_direction; /* one bit per GPIO, 1 = input */
+	uint8_t gpio_value;     /* one bit per GPIO, 1 = high */
+#endif                          /* CONFIG_ADC_ADS1X4S0X_GPIO */
+};
+
+static void ads1x4s0x_data_ready_handler(const struct device *dev, struct gpio_callback *gpio_cb,
+					 uint32_t pins)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(pins);
+
+	struct ads1x4s0x_data *data =
+		CONTAINER_OF(gpio_cb, struct ads1x4s0x_data, callback_data_ready);
+
+	k_sem_give(&data->data_ready_signal);
+}
+
+static int ads1x4s0x_read_register(const struct device *dev,
+				   enum ads1x4s0x_register register_address, uint8_t *value)
+{
+	const struct ads1x4s0x_config *config = dev->config;
+	uint8_t buffer_tx[3];
+	uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)];
+	const struct spi_buf tx_buf[] = {{
+		.buf = buffer_tx,
+		.len = ARRAY_SIZE(buffer_tx),
+	}};
+	const struct spi_buf rx_buf[] = {{
+		.buf = buffer_rx,
+		.len = ARRAY_SIZE(buffer_rx),
+	}};
+	const struct spi_buf_set tx = {
+		.buffers = tx_buf,
+		.count = ARRAY_SIZE(tx_buf),
+	};
+	const struct spi_buf_set rx = {
+		.buffers = rx_buf,
+		.count = ARRAY_SIZE(rx_buf),
+	};
+
+	buffer_tx[0] = ((uint8_t)ADS1X4S0X_COMMAND_RREG) | ((uint8_t)register_address);
+	/* read one register */
+	buffer_tx[1] = 0x00;
+
+	int result = spi_transceive_dt(&config->bus, &tx, &rx);
+
+	if (result != 0) {
+		LOG_ERR("%s: spi_transceive failed with error %i", dev->name, result);
+		return result;
+	}
+
+	*value = buffer_rx[2];
+	LOG_DBG("%s: read from register 0x%02X value 0x%02X", dev->name, register_address, *value);
+
+	return 0;
+}
+
+static int ads1x4s0x_write_register(const struct device *dev,
+				    enum ads1x4s0x_register register_address, uint8_t value)
+{
+	const struct ads1x4s0x_config *config = dev->config;
+	uint8_t buffer_tx[3];
+	const struct spi_buf tx_buf[] = {{
+		.buf = buffer_tx,
+		.len = ARRAY_SIZE(buffer_tx),
+	}};
+	const struct spi_buf_set tx = {
+		.buffers = tx_buf,
+		.count = ARRAY_SIZE(tx_buf),
+	};
+
+	buffer_tx[0] = ((uint8_t)ADS1X4S0X_COMMAND_WREG) | ((uint8_t)register_address);
+	/* write one register */
+	buffer_tx[1] = 0x00;
+	buffer_tx[2] = value;
+
+	LOG_DBG("%s: writing to register 0x%02X value 0x%02X", dev->name, register_address, value);
+	int result = spi_write_dt(&config->bus, &tx);
+
+	if (result != 0) {
+		LOG_ERR("%s: spi_write failed with error %i", dev->name, result);
+		return result;
+	}
+
+	return 0;
+}
+
+static int ads1x4s0x_write_multiple_registers(const struct device *dev,
+					      enum ads1x4s0x_register *register_addresses,
+					      uint8_t *values, size_t count)
+{
+	const struct ads1x4s0x_config *config = dev->config;
+	uint8_t buffer_tx[2];
+	const struct spi_buf tx_buf[] = {
+		{
+			.buf = buffer_tx,
+			.len = ARRAY_SIZE(buffer_tx),
+		},
+		{
+			.buf = values,
+			.len = count,
+		},
+	};
+	const struct spi_buf_set tx = {
+		.buffers = tx_buf,
+		.count = ARRAY_SIZE(tx_buf),
+	};
+
+	if (count == 0) {
+		LOG_WRN("%s: ignoring the command to write 0 registers", dev->name);
+		return -EINVAL;
+	}
+
+	buffer_tx[0] = ((uint8_t)ADS1X4S0X_COMMAND_WREG) | ((uint8_t)register_addresses[0]);
+	buffer_tx[1] = count - 1;
+
+	LOG_HEXDUMP_DBG(register_addresses, count, "writing to registers");
+	LOG_HEXDUMP_DBG(values, count, "values");
+
+	/* ensure that the register addresses are in the correct order */
+	for (size_t i = 1; i < count; ++i) {
+		__ASSERT(register_addresses[i - 1] + 1 == register_addresses[i],
+			 "register addresses are not consecutive");
+	}
+
+	int result = spi_write_dt(&config->bus, &tx);
+
+	if (result != 0) {
+		LOG_ERR("%s: spi_write failed with error %i", dev->name, result);
+		return result;
+	}
+
+	return 0;
+}
+
+static int ads1x4s0x_send_command(const struct device *dev, enum ads1x4s0x_command command)
+{
+	const struct ads1x4s0x_config *config = dev->config;
+	uint8_t buffer_tx[1];
+	const struct spi_buf tx_buf[] = {{
+		.buf = buffer_tx,
+		.len = ARRAY_SIZE(buffer_tx),
+	}};
+	const struct spi_buf_set tx = {
+		.buffers = tx_buf,
+		.count = ARRAY_SIZE(tx_buf),
+	};
+
+	buffer_tx[0] = (uint8_t)command;
+
+	LOG_DBG("%s: sending command 0x%02X", dev->name, command);
+	int result = spi_write_dt(&config->bus, &tx);
+
+	if (result != 0) {
+		LOG_ERR("%s: spi_write failed with error %i", dev->name, result);
+		return result;
+	}
+
+	return 0;
+}
+
+static int ads1x4s0x_channel_setup(const struct device *dev,
+				   const struct adc_channel_cfg *channel_cfg)
+{
+	const struct ads1x4s0x_config *config = dev->config;
+	uint8_t input_mux = 0;
+	uint8_t reference_control = 0;
+	uint8_t data_rate = 0;
+	uint8_t gain = 0;
+	uint8_t idac_magnitude = 0;
+	uint8_t idac_mux = 0;
+	uint8_t pin_selections[4];
+	uint8_t vbias = 0;
+	size_t pin_selections_size;
+	int result;
+	enum ads1x4s0x_register register_addresses[7];
+	uint8_t values[ARRAY_SIZE(register_addresses)];
+	uint16_t acquisition_time_value = ADC_ACQ_TIME_VALUE(channel_cfg->acquisition_time);
+	uint16_t acquisition_time_unit = ADC_ACQ_TIME_UNIT(channel_cfg->acquisition_time);
+
+	ADS1X4S0X_REGISTER_INPMUX_SET_DEFAULTS(gain);
+	ADS1X4S0X_REGISTER_REF_SET_DEFAULTS(reference_control);
+	ADS1X4S0X_REGISTER_DATARATE_SET_DEFAULTS(data_rate);
+	ADS1X4S0X_REGISTER_PGA_SET_DEFAULTS(gain);
+	ADS1X4S0X_REGISTER_IDACMAG_SET_DEFAULTS(idac_magnitude);
+	ADS1X4S0X_REGISTER_IDACMUX_SET_DEFAULTS(idac_mux);
+
+	if (channel_cfg->channel_id != 0) {
+		LOG_ERR("%s: only one channel is supported", dev->name);
+		return -EINVAL;
+	}
+
+	/* The ADS114 uses samples per seconds units with the lowest being 2.5SPS
+	 * and with acquisition_time only having 14b for time, this will not fit
+	 * within here for microsecond units. Use Tick units and allow the user to
+	 * specify the ODR directly.
+	 */
+	if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT &&
+	    acquisition_time_unit != ADC_ACQ_TIME_TICKS) {
+		LOG_ERR("%s: invalid acquisition time %i", dev->name,
+			channel_cfg->acquisition_time);
+		return -EINVAL;
+	}
+
+	if (channel_cfg->acquisition_time == ADC_ACQ_TIME_DEFAULT) {
+		ADS1X4S0X_REGISTER_DATARATE_DR_SET(data_rate, ADS1X4S0X_CONFIG_DR_20);
+	} else {
+		ADS1X4S0X_REGISTER_DATARATE_DR_SET(data_rate, acquisition_time_value);
+	}
+
+	switch (channel_cfg->reference) {
+	case ADC_REF_INTERNAL:
+		/* disable negative reference buffer */
+		ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b1);
+		/* disable positive reference buffer */
+		ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b1);
+		/* use internal reference */
+		ADS1X4S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b10);
+		break;
+	case ADC_REF_EXTERNAL0:
+		/* enable negative reference buffer */
+		ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b0);
+		/* enable positive reference buffer */
+		ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b0);
+		/* use external reference 0*/
+		ADS1X4S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b00);
+		break;
+	case ADC_REF_EXTERNAL1:
+		/* enable negative reference buffer */
+		ADS1X4S0X_REGISTER_REF_NOT_REFN_BUF_SET(reference_control, 0b0);
+		/* enable positive reference buffer */
+		ADS1X4S0X_REGISTER_REF_NOT_REFP_BUF_SET(reference_control, 0b0);
+		/* use external reference 0*/
+		ADS1X4S0X_REGISTER_REF_REFSEL_SET(reference_control, 0b01);
+		break;
+	default:
+		LOG_ERR("%s: reference %i is not supported", dev->name, channel_cfg->reference);
+		return -EINVAL;
+	}
+
+	if (channel_cfg->differential) {
+		LOG_DBG("%s: configuring channel for a differential measurement from the pins (p, "
+			"n) (%i, %i)",
+			dev->name, channel_cfg->input_positive, channel_cfg->input_negative);
+		if (channel_cfg->input_positive >= config->channels &&
+		    channel_cfg->input_positive != ADS1X4S0X_INPUT_SELECTION_AINCOM) {
+			LOG_ERR("%s: positive channel input %i is invalid", dev->name,
+				channel_cfg->input_positive);
+			return -EINVAL;
+		}
+
+		if (channel_cfg->input_negative >= config->channels &&
+		    channel_cfg->input_negative != ADS1X4S0X_INPUT_SELECTION_AINCOM) {
+			LOG_ERR("%s: negative channel input %i is invalid", dev->name,
+				channel_cfg->input_negative);
+			return -EINVAL;
+		}
+
+		if (channel_cfg->input_positive == channel_cfg->input_negative) {
+			LOG_ERR("%s: negative and positive channel inputs must be different",
+				dev->name);
+			return -EINVAL;
+		}
+
+		ADS1X4S0X_REGISTER_INPMUX_MUXP_SET(input_mux, channel_cfg->input_positive);
+		ADS1X4S0X_REGISTER_INPMUX_MUXN_SET(input_mux, channel_cfg->input_negative);
+		pin_selections[0] = channel_cfg->input_positive;
+		pin_selections[1] = channel_cfg->input_negative;
+	} else {
+		LOG_DBG("%s: configuring channel for single ended measurement from input %i",
+			dev->name, channel_cfg->input_positive);
+		if (channel_cfg->input_positive >= config->channels &&
+		    channel_cfg->input_positive != ADS1X4S0X_INPUT_SELECTION_AINCOM) {
+			LOG_ERR("%s: channel input %i is invalid", dev->name,
+				channel_cfg->input_positive);
+			return -EINVAL;
+		}
+
+		ADS1X4S0X_REGISTER_INPMUX_MUXP_SET(input_mux, channel_cfg->input_positive);
+		ADS1X4S0X_REGISTER_INPMUX_MUXN_SET(input_mux, ADS1X4S0X_INPUT_SELECTION_AINCOM);
+		pin_selections[0] = channel_cfg->input_positive;
+		pin_selections[1] = ADS1X4S0X_INPUT_SELECTION_AINCOM;
+	}
+
+	switch (channel_cfg->gain) {
+	case ADC_GAIN_1:
+		/* set gain value */
+		ADS1X4S0X_REGISTER_PGA_GAIN_SET(gain, 0b000);
+		break;
+	case ADC_GAIN_2:
+		ADS1X4S0X_REGISTER_PGA_GAIN_SET(gain, 0b001);
+		break;
+	case ADC_GAIN_4:
+		ADS1X4S0X_REGISTER_PGA_GAIN_SET(gain, 0b010);
+		break;
+	case ADC_GAIN_8:
+		ADS1X4S0X_REGISTER_PGA_GAIN_SET(gain, 0b011);
+		break;
+	case ADC_GAIN_16:
+		ADS1X4S0X_REGISTER_PGA_GAIN_SET(gain, 0b100);
+		break;
+	case ADC_GAIN_32:
+		ADS1X4S0X_REGISTER_PGA_GAIN_SET(gain, 0b101);
+		break;
+	case ADC_GAIN_64:
+		ADS1X4S0X_REGISTER_PGA_GAIN_SET(gain, 0b110);
+		break;
+	case ADC_GAIN_128:
+		ADS1X4S0X_REGISTER_PGA_GAIN_SET(gain, 0b111);
+		break;
+	default:
+		LOG_ERR("%s: gain value %i not supported", dev->name, channel_cfg->gain);
+		return -EINVAL;
+	}
+
+	if (channel_cfg->gain != ADC_GAIN_1) {
+		/* enable gain */
+		ADS1X4S0X_REGISTER_PGA_PGA_EN_SET(gain, 0b01);
+	}
+
+	switch (config->idac_current) {
+	case 0:
+		ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0000);
+		break;
+	case 10:
+		ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0001);
+		break;
+	case 50:
+		ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0010);
+		break;
+	case 100:
+		ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0011);
+		break;
+	case 250:
+		ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0100);
+		break;
+	case 500:
+		ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0101);
+		break;
+	case 750:
+		ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0110);
+		break;
+	case 1000:
+		ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b0111);
+		break;
+	case 1500:
+		ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b1000);
+		break;
+	case 2000:
+		ADS1X4S0X_REGISTER_IDACMAG_IMAG_SET(idac_magnitude, 0b1001);
+		break;
+	default:
+		LOG_ERR("%s: IDAC magnitude %i not supported", dev->name, config->idac_current);
+		return -EINVAL;
+	}
+
+	if (channel_cfg->current_source_pin_set) {
+		LOG_DBG("%s: current source pin set to %i and %i", dev->name,
+			channel_cfg->current_source_pin[0], channel_cfg->current_source_pin[1]);
+		if (channel_cfg->current_source_pin[0] > 0b1111) {
+			LOG_ERR("%s: invalid selection %i for I1MUX", dev->name,
+				channel_cfg->current_source_pin[0]);
+			return -EINVAL;
+		}
+
+		if (channel_cfg->current_source_pin[1] > 0b1111) {
+			LOG_ERR("%s: invalid selection %i for I2MUX", dev->name,
+				channel_cfg->current_source_pin[1]);
+			return -EINVAL;
+		}
+
+		ADS1X4S0X_REGISTER_IDACMUX_I1MUX_SET(idac_mux, channel_cfg->current_source_pin[0]);
+		ADS1X4S0X_REGISTER_IDACMUX_I2MUX_SET(idac_mux, channel_cfg->current_source_pin[1]);
+		pin_selections[2] = channel_cfg->current_source_pin[0];
+		pin_selections[3] = channel_cfg->current_source_pin[1];
+		pin_selections_size = 4;
+	} else {
+		LOG_DBG("%s: current source pins not set", dev->name);
+		pin_selections_size = 2;
+	}
+
+	for (size_t i = 0; i < pin_selections_size; ++i) {
+		if (pin_selections[i] > ADS1X4S0X_INPUT_SELECTION_AINCOM) {
+			continue;
+		}
+
+		for (size_t j = i + 1; j < pin_selections_size; ++j) {
+			if (pin_selections[j] > ADS1X4S0X_INPUT_SELECTION_AINCOM) {
+				continue;
+			}
+
+			if (pin_selections[i] == pin_selections[j]) {
+				LOG_ERR("%s: pins for inputs and current sources must be different",
+					dev->name);
+				return -EINVAL;
+			}
+		}
+	}
+
+	ADS1X4S0X_REGISTER_VBIAS_VB_LEVEL_SET(vbias, config->vbias_level);
+
+	if ((channel_cfg->vbias_pins &
+	     ~GENMASK(ADS1X4S0X_VBIAS_PIN_MAX, ADS1X4S0X_VBIAS_PIN_MIN)) != 0) {
+		LOG_ERR("%s: invalid VBIAS pin selection 0x%08X", dev->name,
+			channel_cfg->vbias_pins);
+		return -EINVAL;
+	}
+
+	vbias |= channel_cfg->vbias_pins;
+
+	register_addresses[0] = ADS1X4S0X_REGISTER_INPMUX;
+	register_addresses[1] = ADS1X4S0X_REGISTER_PGA;
+	register_addresses[2] = ADS1X4S0X_REGISTER_DATARATE;
+	register_addresses[3] = ADS1X4S0X_REGISTER_REF;
+	register_addresses[4] = ADS1X4S0X_REGISTER_IDACMAG;
+	register_addresses[5] = ADS1X4S0X_REGISTER_IDACMUX;
+	register_addresses[6] = ADS1X4S0X_REGISTER_VBIAS;
+	BUILD_ASSERT(ARRAY_SIZE(register_addresses) == 7);
+	values[0] = input_mux;
+	values[1] = gain;
+	values[2] = data_rate;
+	values[3] = reference_control;
+	values[4] = idac_magnitude;
+	values[5] = idac_mux;
+	values[6] = vbias;
+	BUILD_ASSERT(ARRAY_SIZE(values) == 7);
+
+	result = ads1x4s0x_write_multiple_registers(dev, register_addresses, values,
+						    ARRAY_SIZE(values));
+
+	if (result != 0) {
+		LOG_ERR("%s: unable to configure registers", dev->name);
+		return result;
+	}
+
+	return 0;
+}
+
+static int ads1x4s0x_validate_buffer_size(const struct device *dev,
+					  const struct adc_sequence *sequence)
+{
+	const struct ads1x4s0x_config *config = dev->config;
+	size_t needed;
+
+	needed = (config->resolution > 16) ? sizeof(int32_t) : sizeof(int16_t);
+
+	if (sequence->options) {
+		needed *= (1 + sequence->options->extra_samplings);
+	}
+
+	if (sequence->buffer_size < needed) {
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static int ads1x4s0x_validate_sequence(const struct device *dev,
+				       const struct adc_sequence *sequence)
+{
+	const struct ads1x4s0x_config *config = dev->config;
+
+	if (sequence->resolution != config->resolution) {
+		LOG_ERR("%s: invalid resolution", dev->name);
+		return -EINVAL;
+	}
+
+	if (sequence->channels != BIT(0)) {
+		LOG_ERR("%s: invalid channel", dev->name);
+		return -EINVAL;
+	}
+
+	if (sequence->oversampling) {
+		LOG_ERR("%s: oversampling is not supported", dev->name);
+		return -EINVAL;
+	}
+
+	return ads1x4s0x_validate_buffer_size(dev, sequence);
+}
+
+static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
+{
+	struct ads1x4s0x_data *data = CONTAINER_OF(ctx, struct ads1x4s0x_data, ctx);
+
+	if (repeat_sampling) {
+		data->buffer = data->buffer_ptr;
+	}
+}
+
+static void adc_context_start_sampling(struct adc_context *ctx)
+{
+	struct ads1x4s0x_data *data = CONTAINER_OF(ctx, struct ads1x4s0x_data, ctx);
+
+	data->buffer_ptr = data->buffer;
+	k_sem_give(&data->acquire_signal);
+}
+
+static int ads1x4s0x_adc_start_read(const struct device *dev, const struct adc_sequence *sequence,
+				    bool wait)
+{
+	int result;
+	struct ads1x4s0x_data *data = dev->data;
+
+	result = ads1x4s0x_validate_sequence(dev, sequence);
+
+	if (result != 0) {
+		LOG_ERR("%s: sequence validation failed", dev->name);
+		return result;
+	}
+
+	data->buffer = sequence->buffer;
+
+	adc_context_start_read(&data->ctx, sequence);
+
+	if (wait) {
+		result = adc_context_wait_for_completion(&data->ctx);
+	}
+
+	return result;
+}
+
+static int ads1x4s0x_send_start_read(const struct device *dev)
+{
+	const struct ads1x4s0x_config *config = dev->config;
+	int result;
+
+	if (config->gpio_start_sync.port == 0) {
+		result = ads1x4s0x_send_command(dev, ADS1X4S0X_COMMAND_START);
+		if (result != 0) {
+			LOG_ERR("%s: unable to send START/SYNC command", dev->name);
+			return result;
+		}
+	} else {
+		result = gpio_pin_set_dt(&config->gpio_start_sync, 1);
+
+		if (result != 0) {
+			LOG_ERR("%s: unable to start ADC operation", dev->name);
+			return result;
+		}
+
+		k_sleep(K_USEC(ADS1X4S0X_START_SYNC_PULSE_DURATION_IN_US +
+			       ADS1X4S0X_SETUP_TIME_IN_US));
+
+		result = gpio_pin_set_dt(&config->gpio_start_sync, 0);
+
+		if (result != 0) {
+			LOG_ERR("%s: unable to start ADC operation", dev->name);
+			return result;
+		}
+	}
+
+	return 0;
+}
+
+static int ads1x4s0x_wait_data_ready(const struct device *dev)
+{
+	struct ads1x4s0x_data *data = dev->data;
+
+	return k_sem_take(&data->data_ready_signal, ADC_CONTEXT_WAIT_FOR_COMPLETION_TIMEOUT);
+}
+
+#if ADS1X4S0X_HAS_16_BIT_DEV
+static int ads1x4s0x_read_sample_16(const struct device *dev, int16_t *buffer)
+{
+	const struct ads1x4s0x_config *config = dev->config;
+	uint8_t buffer_tx[3];
+	uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)];
+	const struct spi_buf tx_buf[] = {{
+		.buf = buffer_tx,
+		.len = 3,
+	}};
+	const struct spi_buf rx_buf[] = {{
+		.buf = buffer_rx,
+		.len = 3,
+	}};
+	const struct spi_buf_set tx = {
+		.buffers = tx_buf,
+		.count = ARRAY_SIZE(tx_buf),
+	};
+	const struct spi_buf_set rx = {
+		.buffers = rx_buf,
+		.count = ARRAY_SIZE(rx_buf),
+	};
+
+	buffer_tx[0] = (uint8_t)ADS1X4S0X_COMMAND_RDATA;
+
+	int result = spi_transceive_dt(&config->bus, &tx, &rx);
+
+	if (result != 0) {
+		LOG_ERR("%s: spi_transceive failed with error %i", dev->name, result);
+		return result;
+	}
+
+	*buffer = sys_get_be16(buffer_rx + 1);
+	LOG_DBG("%s: read ADC sample %i", dev->name, *buffer);
+
+	return 0;
+}
+#endif
+
+#if ADS1X4S0X_HAS_24_BIT_DEV
+static int ads1x4s0x_read_sample_24(const struct device *dev, int32_t *buffer)
+{
+	const struct ads1x4s0x_config *config = dev->config;
+	uint8_t buffer_tx[5] = {0};
+	uint8_t buffer_rx[ARRAY_SIZE(buffer_tx)];
+	const struct spi_buf tx_buf[] = {{
+		.buf = buffer_tx,
+		.len = 4,
+	}};
+	const struct spi_buf rx_buf[] = {{
+		.buf = buffer_rx,
+		.len = 4,
+	}};
+	const struct spi_buf_set tx = {
+		.buffers = tx_buf,
+		.count = ARRAY_SIZE(tx_buf),
+	};
+	const struct spi_buf_set rx = {
+		.buffers = rx_buf,
+		.count = ARRAY_SIZE(rx_buf),
+	};
+
+	buffer_tx[0] = (uint8_t)ADS1X4S0X_COMMAND_RDATA;
+
+	int result = spi_transceive_dt(&config->bus, &tx, &rx);
+
+	if (result != 0) {
+		LOG_ERR("%s: spi_transceive failed with error %i", dev->name, result);
+		return result;
+	}
+
+	*buffer = (int32_t)sys_get_be32(buffer_rx + 1) >> 8;
+
+	LOG_DBG("%s: read ADC sample 0x%02X%02X%02X", dev->name, *(buffer_rx + 1), *(buffer_rx + 2),
+		*(buffer_rx + 3));
+
+	return 0;
+}
+#endif
+
+static int ads1x4s0x_adc_perform_read(const struct device *dev)
+{
+	int result;
+	const struct ads1x4s0x_config *config = dev->config;
+	struct ads1x4s0x_data *data = dev->data;
+	void *buffer = data->buffer;
+
+	k_sem_take(&data->acquire_signal, K_FOREVER);
+	k_sem_reset(&data->data_ready_signal);
+
+	result = ads1x4s0x_send_start_read(dev);
+	if (result != 0) {
+		LOG_ERR("%s: unable to start ADC conversion", dev->name);
+		adc_context_complete(&data->ctx, result);
+		return result;
+	}
+
+	result = ads1x4s0x_wait_data_ready(dev);
+	if (result != 0) {
+		LOG_ERR("%s: waiting for data to be ready failed", dev->name);
+		adc_context_complete(&data->ctx, result);
+		return result;
+	}
+
+#if ADS1X4S0X_HAS_24_BIT_DEV
+	if (config->resolution == 24) {
+		result = ads1x4s0x_read_sample_24(dev, (int32_t *)data->buffer);
+
+		if (result == 0) {
+			buffer = (int32_t *)buffer + 1;
+			adc_context_on_sampling_done(&data->ctx, dev);
+			return 0;
+		}
+
+	}
+#endif
+
+#if ADS1X4S0X_HAS_16_BIT_DEV
+	if (config->resolution == 16) {
+		result = ads1x4s0x_read_sample_16(dev, (int16_t *)data->buffer);
+
+		if (result == 0) {
+			buffer = (int16_t *)buffer + 1;
+			adc_context_on_sampling_done(&data->ctx, dev);
+			return 0;
+		}
+
+	}
+#endif
+
+	LOG_ERR("%s: reading sample failed", dev->name);
+	adc_context_complete(&data->ctx, result);
+	return result;
+}
+
+#if CONFIG_ADC_ASYNC
+static int ads1x4s0x_adc_read_async(const struct device *dev, const struct adc_sequence *sequence,
+				    struct k_poll_signal *async)
+{
+	int result;
+	struct ads1x4s0x_data *data = dev->data;
+
+	adc_context_lock(&data->ctx, true, async);
+	result = ads1x4s0x_adc_start_read(dev, sequence, true);
+	adc_context_release(&data->ctx, result);
+
+	return result;
+}
+
+static int ads1x4s0x_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+	int result;
+	struct ads1x4s0x_data *data = dev->data;
+
+	adc_context_lock(&data->ctx, false, NULL);
+	result = ads1x4s0x_adc_start_read(dev, sequence, true);
+	adc_context_release(&data->ctx, result);
+
+	return result;
+}
+
+#else
+static int ads1x4s0x_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+	int result;
+	struct ads1x4s0x_data *data = dev->data;
+
+	adc_context_lock(&data->ctx, false, NULL);
+	result = ads1x4s0x_adc_start_read(dev, sequence, false);
+
+	while (result == 0 && k_sem_take(&data->ctx.sync, K_NO_WAIT) != 0) {
+		result = ads1x4s0x_adc_perform_read(dev);
+	}
+
+	adc_context_release(&data->ctx, result);
+	return result;
+}
+#endif
+
+#if CONFIG_ADC_ASYNC
+static void ads1x4s0x_acquisition_thread(void *p1, void *p2, void *p3)
+{
+	ARG_UNUSED(p2);
+	ARG_UNUSED(p3);
+
+	const struct device *dev = p1;
+
+	while (true) {
+		ads1x4s0x_adc_perform_read(dev);
+	}
+}
+#endif
+
+#ifdef CONFIG_ADC_ADS1X4S0X_GPIO
+static int ads1x4s0x_gpio_write_config(const struct device *dev)
+{
+	struct ads1x4s0x_data *data = dev->data;
+	enum ads1x4s0x_register register_addresses[2];
+	uint8_t register_values[ARRAY_SIZE(register_addresses)];
+	uint8_t gpio_dat = 0;
+	uint8_t gpio_con = 0;
+
+	ADS1X4S0X_REGISTER_GPIOCON_CON_SET(gpio_con, data->gpio_enabled);
+	ADS1X4S0X_REGISTER_GPIODAT_DAT_SET(gpio_dat, data->gpio_value);
+	ADS1X4S0X_REGISTER_GPIODAT_DIR_SET(gpio_dat, data->gpio_direction);
+
+	register_values[0] = gpio_dat;
+	register_values[1] = gpio_con;
+	register_addresses[0] = ADS1X4S0X_REGISTER_GPIODAT;
+	register_addresses[1] = ADS1X4S0X_REGISTER_GPIOCON;
+	return ads1x4s0x_write_multiple_registers(dev, register_addresses, register_values,
+						  ARRAY_SIZE(register_values));
+}
+
+static int ads1x4s0x_gpio_write_value(const struct device *dev)
+{
+	struct ads1x4s0x_data *data = dev->data;
+	uint8_t gpio_dat = 0;
+
+	ADS1X4S0X_REGISTER_GPIODAT_DAT_SET(gpio_dat, data->gpio_value);
+	ADS1X4S0X_REGISTER_GPIODAT_DIR_SET(gpio_dat, data->gpio_direction);
+
+	return ads1x4s0x_write_register(dev, ADS1X4S0X_REGISTER_GPIODAT, gpio_dat);
+}
+
+int ads1x4s0x_gpio_set_output(const struct device *dev, uint8_t pin, bool initial_value)
+{
+	struct ads1x4s0x_data *data = dev->data;
+	int result = 0;
+
+	if (pin > ADS1X4S0X_GPIO_MAX) {
+		LOG_ERR("%s: invalid pin %i", dev->name, pin);
+		return -EINVAL;
+	}
+
+	k_mutex_lock(&data->gpio_lock, K_FOREVER);
+
+	data->gpio_enabled |= BIT(pin);
+	data->gpio_direction &= ~BIT(pin);
+
+	if (initial_value) {
+		data->gpio_value |= BIT(pin);
+	} else {
+		data->gpio_value &= ~BIT(pin);
+	}
+
+	result = ads1x4s0x_gpio_write_config(dev);
+
+	k_mutex_unlock(&data->gpio_lock);
+
+	return result;
+}
+
+int ads1x4s0x_gpio_set_input(const struct device *dev, uint8_t pin)
+{
+	struct ads1x4s0x_data *data = dev->data;
+	int result = 0;
+
+	if (pin > ADS1X4S0X_GPIO_MAX) {
+		LOG_ERR("%s: invalid pin %i", dev->name, pin);
+		return -EINVAL;
+	}
+
+	k_mutex_lock(&data->gpio_lock, K_FOREVER);
+
+	data->gpio_enabled |= BIT(pin);
+	data->gpio_direction |= BIT(pin);
+	data->gpio_value &= ~BIT(pin);
+
+	result = ads1x4s0x_gpio_write_config(dev);
+
+	k_mutex_unlock(&data->gpio_lock);
+
+	return result;
+}
+
+int ads1x4s0x_gpio_deconfigure(const struct device *dev, uint8_t pin)
+{
+	struct ads1x4s0x_data *data = dev->data;
+	int result = 0;
+
+	if (pin > ADS1X4S0X_GPIO_MAX) {
+		LOG_ERR("%s: invalid pin %i", dev->name, pin);
+		return -EINVAL;
+	}
+
+	k_mutex_lock(&data->gpio_lock, K_FOREVER);
+
+	data->gpio_enabled &= ~BIT(pin);
+	data->gpio_direction |= BIT(pin);
+	data->gpio_value &= ~BIT(pin);
+
+	result = ads1x4s0x_gpio_write_config(dev);
+
+	k_mutex_unlock(&data->gpio_lock);
+
+	return result;
+}
+
+int ads1x4s0x_gpio_set_pin_value(const struct device *dev, uint8_t pin, bool value)
+{
+	struct ads1x4s0x_data *data = dev->data;
+	int result = 0;
+
+	if (pin > ADS1X4S0X_GPIO_MAX) {
+		LOG_ERR("%s: invalid pin %i", dev->name, pin);
+		return -EINVAL;
+	}
+
+	k_mutex_lock(&data->gpio_lock, K_FOREVER);
+
+	if ((BIT(pin) & data->gpio_enabled) == 0) {
+		LOG_ERR("%s: gpio pin %i not configured", dev->name, pin);
+		result = -EINVAL;
+	} else if ((BIT(pin) & data->gpio_direction) != 0) {
+		LOG_ERR("%s: gpio pin %i not configured as output", dev->name, pin);
+		result = -EINVAL;
+	} else {
+		data->gpio_value |= BIT(pin);
+
+		result = ads1x4s0x_gpio_write_value(dev);
+	}
+
+	k_mutex_unlock(&data->gpio_lock);
+
+	return result;
+}
+
+int ads1x4s0x_gpio_get_pin_value(const struct device *dev, uint8_t pin, bool *value)
+{
+	struct ads1x4s0x_data *data = dev->data;
+	int result = 0;
+	uint8_t gpio_dat;
+
+	if (pin > ADS1X4S0X_GPIO_MAX) {
+		LOG_ERR("%s: invalid pin %i", dev->name, pin);
+		return -EINVAL;
+	}
+
+	k_mutex_lock(&data->gpio_lock, K_FOREVER);
+
+	if ((BIT(pin) & data->gpio_enabled) == 0) {
+		LOG_ERR("%s: gpio pin %i not configured", dev->name, pin);
+		result = -EINVAL;
+	} else if ((BIT(pin) & data->gpio_direction) == 0) {
+		LOG_ERR("%s: gpio pin %i not configured as input", dev->name, pin);
+		result = -EINVAL;
+	} else {
+		result = ads1x4s0x_read_register(dev, ADS1X4S0X_REGISTER_GPIODAT, &gpio_dat);
+		data->gpio_value = ADS1X4S0X_REGISTER_GPIODAT_DAT_GET(gpio_dat);
+		*value = (BIT(pin) & data->gpio_value) != 0;
+	}
+
+	k_mutex_unlock(&data->gpio_lock);
+
+	return result;
+}
+
+int ads1x4s0x_gpio_port_get_raw(const struct device *dev, gpio_port_value_t *value)
+{
+	struct ads1x4s0x_data *data = dev->data;
+	int result = 0;
+	uint8_t gpio_dat;
+
+	k_mutex_lock(&data->gpio_lock, K_FOREVER);
+
+	result = ads1x4s0x_read_register(dev, ADS1X4S0X_REGISTER_GPIODAT, &gpio_dat);
+	data->gpio_value = ADS1X4S0X_REGISTER_GPIODAT_DAT_GET(gpio_dat);
+	*value = data->gpio_value;
+
+	k_mutex_unlock(&data->gpio_lock);
+
+	return result;
+}
+
+int ads1x4s0x_gpio_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
+				       gpio_port_value_t value)
+{
+	struct ads1x4s0x_data *data = dev->data;
+	int result = 0;
+
+	k_mutex_lock(&data->gpio_lock, K_FOREVER);
+
+	data->gpio_value = ((data->gpio_value & ~mask) | (mask & value)) & data->gpio_enabled &
+			   ~data->gpio_direction;
+	result = ads1x4s0x_gpio_write_value(dev);
+
+	k_mutex_unlock(&data->gpio_lock);
+
+	return result;
+}
+
+int ads1x4s0x_gpio_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
+{
+	struct ads1x4s0x_data *data = dev->data;
+	int result = 0;
+
+	k_mutex_lock(&data->gpio_lock, K_FOREVER);
+
+	data->gpio_value = (data->gpio_value ^ pins) & data->gpio_enabled & ~data->gpio_direction;
+	result = ads1x4s0x_gpio_write_value(dev);
+
+	k_mutex_unlock(&data->gpio_lock);
+
+	return result;
+}
+
+#endif /* CONFIG_ADC_ADS1X4S0X_GPIO */
+
+static int ads1x4s0x_init(const struct device *dev)
+{
+	uint8_t status = 0;
+	uint8_t reference_control = 0;
+	uint8_t reference_control_read;
+	int result;
+	const struct ads1x4s0x_config *config = dev->config;
+	struct ads1x4s0x_data *data = dev->data;
+
+	adc_context_init(&data->ctx);
+
+	k_sem_init(&data->data_ready_signal, 0, 1);
+	k_sem_init(&data->acquire_signal, 0, 1);
+
+#ifdef CONFIG_ADC_ADS1X4S0X_GPIO
+	k_mutex_init(&data->gpio_lock);
+#endif /* CONFIG_ADC_ADS1X4S0X_GPIO */
+
+	if (!spi_is_ready_dt(&config->bus)) {
+		LOG_ERR("%s: SPI device is not ready", dev->name);
+		return -ENODEV;
+	}
+
+	if (config->gpio_reset.port != NULL) {
+		result = gpio_pin_configure_dt(&config->gpio_reset, GPIO_OUTPUT_ACTIVE);
+		if (result != 0) {
+			LOG_ERR("%s: failed to initialize GPIO for reset", dev->name);
+			return result;
+		}
+	}
+
+	if (config->gpio_start_sync.port != NULL) {
+		result = gpio_pin_configure_dt(&config->gpio_start_sync, GPIO_OUTPUT_INACTIVE);
+		if (result != 0) {
+			LOG_ERR("%s: failed to initialize GPIO for start/sync", dev->name);
+			return result;
+		}
+	}
+
+	result = gpio_pin_configure_dt(&config->gpio_data_ready, GPIO_INPUT);
+	if (result != 0) {
+		LOG_ERR("%s: failed to initialize GPIO for data ready", dev->name);
+		return result;
+	}
+
+	result = gpio_pin_interrupt_configure_dt(&config->gpio_data_ready, GPIO_INT_EDGE_TO_ACTIVE);
+	if (result != 0) {
+		LOG_ERR("%s: failed to configure data ready interrupt", dev->name);
+		return -EIO;
+	}
+
+	gpio_init_callback(&data->callback_data_ready, ads1x4s0x_data_ready_handler,
+			   BIT(config->gpio_data_ready.pin));
+	result = gpio_add_callback(config->gpio_data_ready.port, &data->callback_data_ready);
+	if (result != 0) {
+		LOG_ERR("%s: failed to add data ready callback", dev->name);
+		return -EIO;
+	}
+
+#if CONFIG_ADC_ASYNC
+	k_tid_t tid = k_thread_create(&data->thread, config->stack,
+				      CONFIG_ADC_ADS1X4S0X_ACQUISITION_THREAD_STACK_SIZE,
+				      ads1x4s0x_acquisition_thread, (void *)dev, NULL, NULL,
+				      CONFIG_ADC_ADS1X4S0X_ASYNC_THREAD_INIT_PRIO, 0, K_NO_WAIT);
+	k_thread_name_set(tid, "adc_ads1x4s0x");
+#endif
+
+	k_busy_wait(ADS1X4S0X_POWER_ON_RESET_TIME_IN_US);
+
+	if (config->gpio_reset.port == NULL) {
+		result = ads1x4s0x_send_command(dev, ADS1X4S0X_COMMAND_RESET);
+		if (result != 0) {
+			LOG_ERR("%s: unable to send RESET command", dev->name);
+			return result;
+		}
+	} else {
+		k_busy_wait(ADS1X4S0X_RESET_LOW_TIME_IN_US);
+		gpio_pin_set_dt(&config->gpio_reset, 0);
+	}
+
+	k_busy_wait(ADS1X4S0X_RESET_DELAY_TIME_IN_US);
+
+	result = ads1x4s0x_read_register(dev, ADS1X4S0X_REGISTER_STATUS, &status);
+	if (result != 0) {
+		LOG_ERR("%s: unable to read status register", dev->name);
+		return result;
+	}
+
+	if (ADS1X4S0X_REGISTER_STATUS_NOT_RDY_GET(status) == 0x01) {
+		LOG_ERR("%s: ADS114 is not yet ready", dev->name);
+		return -EBUSY;
+	}
+
+	/*
+	 * Activate internal voltage reference during initialization to
+	 * avoid the necessary setup time for it to settle later on.
+	 */
+	ADS1X4S0X_REGISTER_REF_SET_DEFAULTS(reference_control);
+
+	result = ads1x4s0x_write_register(dev, ADS1X4S0X_REGISTER_REF, reference_control);
+	if (result != 0) {
+		LOG_ERR("%s: unable to set default reference control values", dev->name);
+		return result;
+	}
+
+	/*
+	 * Ensure that the internal voltage reference is active.
+	 */
+	result = ads1x4s0x_read_register(dev, ADS1X4S0X_REGISTER_REF, &reference_control_read);
+	if (result != 0) {
+		LOG_ERR("%s: unable to read reference control values", dev->name);
+		return result;
+	}
+
+	if (reference_control != reference_control_read) {
+		LOG_ERR("%s: reference control register is incorrect: 0x%02X", dev->name,
+			reference_control_read);
+		return -EIO;
+	}
+
+#ifdef CONFIG_ADC_ADS1X4S0X_GPIO
+	data->gpio_enabled = 0x00;
+	data->gpio_direction = 0x0F;
+	data->gpio_value = 0x00;
+
+	result = ads1x4s0x_gpio_write_config(dev);
+
+	if (result != 0) {
+		LOG_ERR("%s: unable to configure defaults for GPIOs", dev->name);
+		return result;
+	}
+#endif
+
+	adc_context_unlock_unconditionally(&data->ctx);
+
+	return result;
+}
+
+static DEVICE_API(adc, api) = {
+	.channel_setup = ads1x4s0x_channel_setup,
+	.read = ads1x4s0x_read,
+	.ref_internal = ADS1X4S0X_REF_INTERNAL,
+#ifdef CONFIG_ADC_ASYNC
+	.read_async = ads1x4s0x_adc_read_async,
+#endif
+};
+BUILD_ASSERT(CONFIG_ADC_INIT_PRIORITY > CONFIG_SPI_INIT_PRIORITY,
+	     "CONFIG_ADC_INIT_PRIORITY must be higher than CONFIG_SPI_INIT_PRIORITY");
+
+#define ADC_ADS1X4S0X_INST_DEFINE(n, name, ch, res)                                               \
+	IF_ENABLED(                                                                               \
+		CONFIG_ADC_ASYNC,                                                                 \
+		(static K_KERNEL_STACK_DEFINE(                                                    \
+			 thread_stack_##name##_##n,                                               \
+			 CONFIG_ADC_ADS1X4S0X_ACQUISITION_THREAD_STACK_SIZE);)                    \
+	)                                                                                         \
+	static const struct ads1x4s0x_config config_##name##_##n = {                              \
+		.bus = SPI_DT_SPEC_INST_GET(                                                      \
+			n, SPI_OP_MODE_MASTER | SPI_MODE_CPHA | SPI_WORD_SET(8), 0),              \
+		IF_ENABLED(CONFIG_ADC_ASYNC, (.stack = thread_stack_##name##_##n,))               \
+		.gpio_reset = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {0}),                      \
+		.gpio_data_ready = GPIO_DT_SPEC_INST_GET(n, drdy_gpios),                          \
+		.gpio_start_sync = GPIO_DT_SPEC_INST_GET_OR(n, start_sync_gpios, {0}),            \
+		.idac_current = DT_INST_PROP(n, idac_current),                                    \
+		.vbias_level = DT_INST_PROP(n, vbias_level),                                      \
+		.resolution = res,                                                                \
+		.channels = ch,                                                                   \
+	};                                                                                        \
+	static struct ads1x4s0x_data data_##name##_##n;                                           \
+	DEVICE_DT_INST_DEFINE(n, ads1x4s0x_init, NULL, &data_##name##_##n, &config_##name##_##n,  \
+			      POST_KERNEL, CONFIG_ADC_INIT_PRIORITY, &api);
+
+/*
+ * ADS114S06: 16 bit, 6 channels
+ */
+#define DT_DRV_COMPAT ti_ads114s06
+#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
+#define ADC_ADS114S06_INST_DEFINE(n) ADC_ADS1X4S0X_INST_DEFINE(n, ti_ads114s06, 6, 16)
+DT_INST_FOREACH_STATUS_OKAY(ADC_ADS114S06_INST_DEFINE);
+#endif
+
+/*
+ * ADS114S08: 16 bit, 12 channels
+ */
+#undef DT_DRV_COMPAT
+#define DT_DRV_COMPAT ti_ads114s08
+#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
+#define ADC_ADS114S08_INST_DEFINE(n) ADC_ADS1X4S0X_INST_DEFINE(n, ti_ads114s08, 12, 16)
+DT_INST_FOREACH_STATUS_OKAY(ADC_ADS114S08_INST_DEFINE);
+#endif
+
+/*
+ * ADS124S06: 24 bit, 6 channels
+ */
+#undef DT_DRV_COMPAT
+#define DT_DRV_COMPAT ti_ads124s06
+#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
+#define ADC_ADS124S06_INST_DEFINE(n) ADC_ADS1X4S0X_INST_DEFINE(n, ti_ads124s06, 6, 24)
+DT_INST_FOREACH_STATUS_OKAY(ADC_ADS124S06_INST_DEFINE);
+#endif
+
+/*
+ * ADS124S08: 24 bit, 12 channels
+ */
+#undef DT_DRV_COMPAT
+#define DT_DRV_COMPAT ti_ads124s08
+#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
+#define ADC_ADS124S08_INST_DEFINE(n) ADC_ADS1X4S0X_INST_DEFINE(n, ti_ads124s08, 12, 24)
+DT_INST_FOREACH_STATUS_OKAY(ADC_ADS124S08_INST_DEFINE);
+#endif
diff --git a/drivers/adc/adc_ambiq.c b/drivers/adc/adc_ambiq.c
index 66c40efac83..5af7b1301b1 100644
--- a/drivers/adc/adc_ambiq.c
+++ b/drivers/adc/adc_ambiq.c
@@ -16,13 +16,11 @@
 #include "adc_context.h"
 
 /* ambiq-sdk includes */
-#include <am_mcu_apollo.h>
+#include <soc.h>
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(adc_ambiq, CONFIG_ADC_LOG_LEVEL);
 
-typedef int (*ambiq_adc_pwr_func_t)(void);
-#define PWRCTRL_MAX_WAIT_US   5
 /* Number of slots available. */
 #define AMBIQ_ADC_SLOT_NUMBER AM_HAL_ADC_MAX_SLOTS
 
@@ -32,7 +30,6 @@ struct adc_ambiq_config {
 	uint8_t num_channels;
 	void (*irq_config_func)(void);
 	const struct pinctrl_dev_config *pin_cfg;
-	ambiq_adc_pwr_func_t pwr_func;
 };
 
 struct adc_ambiq_data {
@@ -290,7 +287,7 @@ static int adc_ambiq_init(const struct device *dev)
 	}
 
 	/* power on ADC*/
-	ret = cfg->pwr_func();
+	ret = am_hal_adc_power_control(data->adcHandle, AM_HAL_SYSCTRL_WAKE, false);
 
 	/* Set up the ADC configuration parameters. These settings are reasonable
 	 *  for accurate measurements at a low sample rate.
@@ -404,14 +401,6 @@ static int adc_ambiq_pm_action(const struct device *dev, enum pm_device_action a
 #define ADC_AMBIQ_INIT(n)                                                                          \
 	PINCTRL_DT_INST_DEFINE(n);                                                                 \
 	ADC_AMBIQ_DRIVER_API(n);                                                                   \
-	static int pwr_on_ambiq_adc_##n(void)                                                      \
-	{                                                                                          \
-		uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) +                    \
-				DT_INST_PHA(n, ambiq_pwrcfg, offset);                              \
-		sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr);        \
-		k_busy_wait(PWRCTRL_MAX_WAIT_US);                                                  \
-		return 0;                                                                          \
-	}                                                                                          \
 	static void adc_irq_config_func_##n(void)                                                  \
 	{                                                                                          \
 		IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), adc_ambiq_isr,              \
@@ -429,7 +418,6 @@ static int adc_ambiq_pm_action(const struct device *dev, enum pm_device_action a
 		.num_channels = DT_PROP(DT_DRV_INST(n), channel_count),                            \
 		.irq_config_func = adc_irq_config_func_##n,                                        \
 		.pin_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                      \
-		.pwr_func = pwr_on_ambiq_adc_##n,                                                  \
 	};                                                                                         \
 	PM_DEVICE_DT_INST_DEFINE(n, adc_ambiq_pm_action);                                          \
 	DEVICE_DT_INST_DEFINE(n, &adc_ambiq_init, PM_DEVICE_DT_INST_GET(n), &adc_ambiq_data_##n,   \
diff --git a/drivers/adc/adc_emul.c b/drivers/adc/adc_emul.c
index e697206e512..a74fc011fa7 100644
--- a/drivers/adc/adc_emul.c
+++ b/drivers/adc/adc_emul.c
@@ -394,24 +394,34 @@ static int adc_emul_start_read(const struct device *dev,
 	return adc_context_wait_for_completion(&data->ctx);
 }
 
-static int adc_emul_read_async(const struct device *dev,
+static int adc_emul_read_common(const struct device *dev,
 			       const struct adc_sequence *sequence,
+			       bool is_async,
 			       struct k_poll_signal *async)
 {
 	struct adc_emul_data *data = dev->data;
 	int err;
 
-	adc_context_lock(&data->ctx, async ? true : false, async);
+	adc_context_lock(&data->ctx, is_async, async);
 	err = adc_emul_start_read(dev, sequence);
 	adc_context_release(&data->ctx, err);
 
 	return err;
 }
 
+#ifdef CONFIG_ADC_ASYNC
+static int adc_emul_read_async(const struct device *dev,
+			       const struct adc_sequence *sequence,
+			       struct k_poll_signal *async)
+{
+	return adc_emul_read_common(dev, sequence, true, async);
+}
+#endif
+
 static int adc_emul_read(const struct device *dev,
 			 const struct adc_sequence *sequence)
 {
-	return adc_emul_read_async(dev, sequence, NULL);
+	return adc_emul_read_common(dev, sequence, false, NULL);
 }
 
 static void adc_context_start_sampling(struct adc_context *ctx)
diff --git a/drivers/adc/adc_esp32.c b/drivers/adc/adc_esp32.c
index e6d43b0c7e7..8ffeb5539f7 100644
--- a/drivers/adc/adc_esp32.c
+++ b/drivers/adc/adc_esp32.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 Espressif Systems (Shanghai) CO LTD
+ * Copyright (c) 2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,9 +8,11 @@
 
 #include <errno.h>
 #include <hal/adc_hal.h>
+#include <hal/adc_oneshot_hal.h>
 #include <hal/adc_types.h>
 #include <soc/adc_periph.h>
-#include <esp_adc_cal.h>
+#include <esp_adc/adc_cali.h>
+#include <esp_adc/adc_cali_scheme.h>
 #include <esp_clk_tree.h>
 #include <esp_private/periph_ctrl.h>
 #include <esp_private/sar_periph_ctrl.h>
@@ -28,52 +30,42 @@
 #include <zephyr/device.h>
 #include <zephyr/drivers/adc.h>
 #include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/clock_control.h>
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(adc_esp32, CONFIG_ADC_LOG_LEVEL);
 
-#define ADC_RESOLUTION_MIN	SOC_ADC_DIGI_MIN_BITWIDTH
-#define ADC_RESOLUTION_MAX	SOC_ADC_DIGI_MAX_BITWIDTH
+#define ADC_RESOLUTION_MIN SOC_ADC_DIGI_MIN_BITWIDTH
+#define ADC_RESOLUTION_MAX SOC_ADC_DIGI_MAX_BITWIDTH
 
-#if CONFIG_SOC_SERIES_ESP32
-#define ADC_CALI_SCHEME		ESP_ADC_CAL_VAL_EFUSE_VREF
-/* Due to significant measurement discrepancy in higher voltage range, we
- * clip the value instead of yet another correction. The IDF implementation
- * for ESP32-S2 is doing it, so we copy that approach in Zephyr driver
- */
-#define ADC_CLIP_MVOLT_12DB     2550
-#elif CONFIG_SOC_SERIES_ESP32S3
-#define ADC_CALI_SCHEME		ESP_ADC_CAL_VAL_EFUSE_TP_FIT
-#else
-#define ADC_CALI_SCHEME		ESP_ADC_CAL_VAL_EFUSE_TP
-#endif
-
-/* Validate if resolution in bits is within allowed values */
 #define VALID_RESOLUTION(r) ((r) >= ADC_RESOLUTION_MIN && (r) <= ADC_RESOLUTION_MAX)
-#define INVALID_RESOLUTION(r) (!VALID_RESOLUTION(r))
 
 /* Default internal reference voltage */
 #define ADC_ESP32_DEFAULT_VREF_INTERNAL (1100)
 
-#define ADC_DMA_BUFFER_SIZE	DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED
+#define ADC_DMA_BUFFER_SIZE DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED
+
+#define ADC_CLIP_MVOLT_12DB	2550
 
 struct adc_esp32_conf {
+	const struct device *clock_dev;
+	const clock_control_subsys_t clock_subsys;
 	adc_unit_t unit;
 	uint8_t channel_count;
-#if defined(CONFIG_ADC_ESP32_DMA)
 	const struct device *gpio_port;
+#if defined(CONFIG_ADC_ESP32_DMA)
 	const struct device *dma_dev;
 	uint8_t dma_channel;
 #endif /* defined(CONFIG_ADC_ESP32_DMA) */
 };
 
 struct adc_esp32_data {
+	adc_oneshot_hal_ctx_t hal;
 	adc_atten_t attenuation[SOC_ADC_MAX_CHANNEL_NUM];
 	uint8_t resolution[SOC_ADC_MAX_CHANNEL_NUM];
-	esp_adc_cal_characteristics_t chars[SOC_ADC_MAX_CHANNEL_NUM];
+	adc_cali_handle_t cal_handle[SOC_ADC_MAX_CHANNEL_NUM];
 	uint16_t meas_ref_internal;
 	uint16_t *buffer;
-	bool calibrate;
 #if defined(CONFIG_ADC_ESP32_DMA)
 	adc_hal_dma_ctx_t adc_hal_dma_ctx;
 	uint8_t *dma_buffer;
@@ -104,27 +96,39 @@ static inline int gain_to_atten(enum adc_gain gain, adc_atten_t *atten)
 }
 
 #if !defined(CONFIG_ADC_ESP32_DMA)
+
 /* Convert voltage by inverted attenuation to support zephyr gain values */
 static void atten_to_gain(adc_atten_t atten, uint32_t *val_mv)
 {
+	uint32_t num, den;
+
 	if (!val_mv) {
 		return;
 	}
+
 	switch (atten) {
-	case ADC_ATTEN_DB_2_5:
-		*val_mv = (*val_mv * 4) / 5; /* 1/ADC_GAIN_4_5 */
+	case ADC_ATTEN_DB_2_5: /* 1/ADC_GAIN_4_5 */
+		num = 4;
+		den = 5;
 		break;
-	case ADC_ATTEN_DB_6:
-		*val_mv = *val_mv >> 1; /* 1/ADC_GAIN_1_2 */
+	case ADC_ATTEN_DB_6: /* 1/ADC_GAIN_1_2 */
+		num = 1;
+		den = 2;
 		break;
-	case ADC_ATTEN_DB_12:
-		*val_mv = *val_mv / 4; /* 1/ADC_GAIN_1_4 */
+	case ADC_ATTEN_DB_12: /* 1/ADC_GAIN_1_4 */
+		num = 1;
+		den = 4;
 		break;
 	case ADC_ATTEN_DB_0: /* 1/ADC_GAIN_1 */
 	default:
+		num = 1;
+		den = 1;
 		break;
 	}
+
+	*val_mv = (*val_mv * num) / den;
 }
+
 #endif /* !defined(CONFIG_ADC_ESP32_DMA) */
 
 static void adc_hw_calibration(adc_unit_t unit)
@@ -143,26 +147,6 @@ static void adc_hw_calibration(adc_unit_t unit)
 #endif /* SOC_ADC_CALIBRATION_V1_SUPPORTED */
 }
 
-static bool adc_calibration_init(const struct device *dev)
-{
-	switch (esp_adc_cal_check_efuse(ADC_CALI_SCHEME)) {
-	case ESP_ERR_NOT_SUPPORTED:
-		LOG_WRN("Skip software calibration - Not supported!");
-		break;
-	case ESP_ERR_INVALID_VERSION:
-		LOG_WRN("Skip software calibration - Invalid version!");
-		break;
-	case ESP_OK:
-		LOG_DBG("Software calibration possible");
-		return true;
-	default:
-		LOG_ERR("Invalid arg");
-		break;
-	}
-
-	return false;
-}
-
 #if defined(CONFIG_ADC_ESP32_DMA)
 
 static void IRAM_ATTR adc_esp32_dma_conv_done(const struct device *dma_dev, void *user_data,
@@ -180,7 +164,6 @@ static void IRAM_ATTR adc_esp32_dma_conv_done(const struct device *dma_dev, void
 static int adc_esp32_dma_start(const struct device *dev, uint8_t *buf, size_t len)
 {
 	const struct adc_esp32_conf *conf = dev->config;
-	struct adc_esp32_data *data = dev->data;
 
 	int err = 0;
 	struct dma_config dma_cfg = {0};
@@ -243,13 +226,14 @@ static int adc_esp32_dma_stop(const struct device *dev)
 }
 
 static int adc_esp32_fill_digi_pattern(const struct device *dev, const struct adc_sequence *seq,
-			void *pattern_config, uint32_t *pattern_len, uint32_t *unit_attenuation)
+				       void *pattern_config, uint32_t *pattern_len,
+				       uint32_t *unit_attenuation)
 {
 	const struct adc_esp32_conf *conf = dev->config;
 	struct adc_esp32_data *data = dev->data;
 
 	adc_digi_pattern_config_t *adc_digi_pattern_config =
-					(adc_digi_pattern_config_t *)pattern_config;
+		(adc_digi_pattern_config_t *)pattern_config;
 	const uint32_t unit_atten_uninit = 999;
 	uint32_t channel_mask = 1, channels_copy = seq->channels;
 
@@ -300,7 +284,7 @@ static void adc_esp32_digi_start(const struct device *dev, void *pattern_config,
 
 #if SOC_ADC_CALIBRATION_V1_SUPPORTED
 	adc_set_hw_calibration_code(conf->unit, unit_attenuation);
-#endif  /* SOC_ADC_CALIBRATION_V1_SUPPORTED */
+#endif /* SOC_ADC_CALIBRATION_V1_SUPPORTED */
 
 #if SOC_ADC_ARBITER_SUPPORTED
 	if (conf->unit == ADC_UNIT_2) {
@@ -308,7 +292,7 @@ static void adc_esp32_digi_start(const struct device *dev, void *pattern_config,
 
 		adc_hal_arbiter_config(&config);
 	}
-#endif  /* SOC_ADC_ARBITER_SUPPORTED */
+#endif /* SOC_ADC_ARBITER_SUPPORTED */
 
 	adc_hal_digi_ctrlr_cfg_t adc_hal_digi_ctrlr_cfg;
 	soc_module_clk_t clk_src = ADC_DIGI_CLK_SRC_DEFAULT;
@@ -318,7 +302,7 @@ static void adc_esp32_digi_start(const struct device *dev, void *pattern_config,
 				     &clk_src_freq_hz);
 
 	adc_hal_digi_ctrlr_cfg.conv_mode =
-		(conf->unit == ADC_UNIT_1)?ADC_CONV_SINGLE_UNIT_1:ADC_CONV_SINGLE_UNIT_2;
+		(conf->unit == ADC_UNIT_1) ? ADC_CONV_SINGLE_UNIT_1 : ADC_CONV_SINGLE_UNIT_2;
 	adc_hal_digi_ctrlr_cfg.clk_src = clk_src;
 	adc_hal_digi_ctrlr_cfg.clk_src_freq_hz = clk_src_freq_hz;
 	adc_hal_digi_ctrlr_cfg.sample_freq_hz = sample_freq_hz;
@@ -384,10 +368,7 @@ static int adc_esp32_wait_for_dma_conv_done(const struct device *dev)
 
 static int adc_esp32_read(const struct device *dev, const struct adc_sequence *seq)
 {
-	const struct adc_esp32_conf *conf = dev->config;
 	struct adc_esp32_data *data = dev->data;
-	int reading;
-	uint32_t cal, cal_mv;
 
 	uint8_t channel_id = find_lsb_set(seq->channels) - 1;
 
@@ -417,7 +398,7 @@ static int adc_esp32_read(const struct device *dev, const struct adc_sequence *s
 #endif /* !defined(CONFIG_ADC_ESP32_DMA) */
 	}
 
-	if (INVALID_RESOLUTION(seq->resolution)) {
+	if (!VALID_RESOLUTION(seq->resolution)) {
 		LOG_ERR("unsupported resolution (%d)", seq->resolution);
 		return -ENOTSUP;
 	}
@@ -430,55 +411,49 @@ static int adc_esp32_read(const struct device *dev, const struct adc_sequence *s
 
 	data->resolution[channel_id] = seq->resolution;
 
-#if CONFIG_SOC_SERIES_ESP32C3
-	/* NOTE: nothing to set on ESP32C3 SoC */
-	if (conf->unit == ADC_UNIT_1) {
-		adc1_config_width(ADC_WIDTH_BIT_DEFAULT);
-	}
-#else
-	adc_set_data_width(conf->unit, data->resolution[channel_id]);
-#endif /* CONFIG_SOC_SERIES_ESP32C3 */
-
 #if !defined(CONFIG_ADC_ESP32_DMA)
-	/* Read raw value */
-	if (conf->unit == ADC_UNIT_1) {
-		reading = adc1_get_raw(channel_id);
-	}
-	if (conf->unit == ADC_UNIT_2) {
-		if (adc2_get_raw(channel_id, ADC_WIDTH_BIT_DEFAULT, &reading)) {
-			LOG_ERR("Conversion timeout on '%s' channel %d", dev->name, channel_id);
-			return -ETIMEDOUT;
-		}
-	}
 
-	/* Calibration scheme is available */
-	if (data->calibrate) {
-		data->chars[channel_id].bit_width = data->resolution[channel_id];
-		/* Get corrected voltage output */
-		cal = cal_mv = esp_adc_cal_raw_to_voltage(reading, &data->chars[channel_id]);
+	uint32_t acq_raw;
+
+	adc_oneshot_hal_setup(&data->hal, channel_id);
+
+#if SOC_ADC_CALIBRATION_V1_SUPPORTED
+	adc_set_hw_calibration_code(data->hal.unit, data->attenuation[channel_id]);
+#endif /* SOC_ADC_CALIBRATION_V1_SUPPORTED */
+
+	adc_oneshot_hal_convert(&data->hal, &acq_raw);
+
+	if (data->cal_handle[channel_id]) {
+		if (data->meas_ref_internal > 0) {
+			uint32_t acq_mv;
+
+			adc_cali_raw_to_voltage(data->cal_handle[channel_id], acq_raw, &acq_mv);
+
+			LOG_DBG("ADC acquisition [unit: %u, chan: %u, acq_raw: %u, acq_mv: %u]",
+				data->hal.unit, channel_id, acq_raw, acq_mv);
 
 #if CONFIG_SOC_SERIES_ESP32
 		if (data->attenuation[channel_id] == ADC_ATTEN_DB_12) {
-			if (cal > ADC_CLIP_MVOLT_12DB) {
-				cal = ADC_CLIP_MVOLT_12DB;
+			if (acq_mv > ADC_CLIP_MVOLT_12DB) {
+				acq_mv = ADC_CLIP_MVOLT_12DB;
 			}
 		}
 #endif /* CONFIG_SOC_SERIES_ESP32 */
 
-		/* Fit according to selected attenuation */
-		atten_to_gain(data->attenuation[channel_id], &cal);
-		if (data->meas_ref_internal > 0) {
-			cal = (cal << data->resolution[channel_id]) / data->meas_ref_internal;
+			/* Fit according to selected attenuation */
+			atten_to_gain(data->attenuation[channel_id], &acq_mv);
+			acq_raw = acq_mv * ((1 << data->resolution[channel_id]) - 1) /
+				  data->meas_ref_internal;
+		} else {
+			LOG_WRN("ADC reading is uncompensated");
 		}
 	} else {
-		LOG_DBG("Using uncalibrated values!");
-		/* Uncalibrated raw value */
-		cal = reading;
+		LOG_WRN("ADC reading is uncompensated");
 	}
 
 	/* Store result */
-	data->buffer = (uint16_t *) seq->buffer;
-	data->buffer[0] = cal;
+	data->buffer = (uint16_t *)seq->buffer;
+	data->buffer[0] = acq_raw;
 
 #else /* !defined(CONFIG_ADC_ESP32_DMA) */
 
@@ -486,15 +461,14 @@ static int adc_esp32_read(const struct device *dev, const struct adc_sequence *s
 	uint32_t adc_pattern_len, unit_attenuation;
 	adc_digi_pattern_config_t adc_digi_pattern_config[SOC_ADC_MAX_CHANNEL_NUM];
 
-	err = adc_esp32_fill_digi_pattern(dev, seq, &adc_digi_pattern_config,
-						 &adc_pattern_len,  &unit_attenuation);
+	err = adc_esp32_fill_digi_pattern(dev, seq, &adc_digi_pattern_config, &adc_pattern_len,
+					  &unit_attenuation);
 	if (err || adc_pattern_len == 0) {
 		return -EINVAL;
 	}
 
 	const struct adc_sequence_options *options = seq->options;
-	uint32_t sample_freq_hz = SOC_ADC_SAMPLE_FREQ_THRES_HIGH,
-		 number_of_samplings = 1;
+	uint32_t sample_freq_hz = SOC_ADC_SAMPLE_FREQ_THRES_HIGH, number_of_samplings = 1;
 
 	if (options != NULL) {
 		number_of_samplings = seq->buffer_size / (adc_pattern_len * sizeof(uint16_t));
@@ -509,7 +483,7 @@ static int adc_esp32_read(const struct device *dev, const struct adc_sequence *s
 		return -EINVAL;
 	}
 
-	if (sample_freq_hz < SOC_ADC_SAMPLE_FREQ_THRES_LOW  ||
+	if (sample_freq_hz < SOC_ADC_SAMPLE_FREQ_THRES_LOW ||
 	    sample_freq_hz > SOC_ADC_SAMPLE_FREQ_THRES_HIGH) {
 		LOG_ERR("ADC sampling frequency out of range: %uHz", sample_freq_hz);
 		return -EINVAL;
@@ -517,7 +491,7 @@ static int adc_esp32_read(const struct device *dev, const struct adc_sequence *s
 
 	uint32_t number_of_adc_samples = number_of_samplings * adc_pattern_len;
 	uint32_t number_of_adc_dma_data_bytes =
-			number_of_adc_samples * SOC_ADC_DIGI_DATA_BYTES_PER_CONV;
+		number_of_adc_samples * SOC_ADC_DIGI_DATA_BYTES_PER_CONV;
 
 	if (number_of_adc_dma_data_bytes > ADC_DMA_BUFFER_SIZE) {
 		LOG_ERR("dma buffer size insufficient to store a complete sequence!");
@@ -552,8 +526,7 @@ static int adc_esp32_read(const struct device *dev, const struct adc_sequence *s
 }
 
 #ifdef CONFIG_ADC_ASYNC
-static int adc_esp32_read_async(const struct device *dev,
-				const struct adc_sequence *sequence,
+static int adc_esp32_read_async(const struct device *dev, const struct adc_sequence *sequence,
 				struct k_poll_signal *async)
 {
 	(void)(dev);
@@ -567,7 +540,8 @@ static int adc_esp32_read_async(const struct device *dev,
 static int adc_esp32_channel_setup(const struct device *dev, const struct adc_channel_cfg *cfg)
 {
 	const struct adc_esp32_conf *conf = (const struct adc_esp32_conf *)dev->config;
-	struct adc_esp32_data *data = (struct adc_esp32_data *) dev->data;
+	struct adc_esp32_data *data = (struct adc_esp32_data *)dev->data;
+	adc_atten_t old_atten = data->attenuation[cfg->channel_id];
 
 	if (cfg->channel_id >= conf->channel_count) {
 		LOG_ERR("Unsupported channel id '%d'", cfg->channel_id);
@@ -594,33 +568,68 @@ static int adc_esp32_channel_setup(const struct device *dev, const struct adc_ch
 		return -ENOTSUP;
 	}
 
-	/* Prepare channel */
-	if (conf->unit == ADC_UNIT_1) {
-		adc1_config_channel_atten(cfg->channel_id, data->attenuation[cfg->channel_id]);
-	}
-	if (conf->unit == ADC_UNIT_2) {
-		adc2_config_channel_atten(cfg->channel_id, data->attenuation[cfg->channel_id]);
-	}
-
-	if (data->calibrate) {
-		esp_adc_cal_value_t cal = esp_adc_cal_characterize(conf->unit,
-						data->attenuation[cfg->channel_id],
-						data->resolution[cfg->channel_id],
-						data->meas_ref_internal,
-						&data->chars[cfg->channel_id]);
-		if (cal >= ESP_ADC_CAL_VAL_NOT_SUPPORTED) {
-			LOG_ERR("Calibration error or not supported");
-			return -EIO;
+	adc_oneshot_hal_chan_cfg_t config = {
+		.atten = data->attenuation[cfg->channel_id],
+		.bitwidth = data->resolution[cfg->channel_id],
+	};
+
+	adc_oneshot_hal_channel_config(&data->hal, &config, cfg->channel_id);
+
+	if ((data->cal_handle[cfg->channel_id] == NULL) ||
+	    (data->attenuation[cfg->channel_id] != old_atten)) {
+#if ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED
+		adc_cali_curve_fitting_config_t cal_config = {
+			.unit_id = conf->unit,
+			.chan = cfg->channel_id,
+			.atten = data->attenuation[cfg->channel_id],
+			.bitwidth = data->resolution[cfg->channel_id],
+		};
+
+		LOG_DBG("Curve fitting calib [unit_id: %u, chan: %u, atten: %u, bitwidth: %u]",
+			conf->unit, cfg->channel_id, data->attenuation[cfg->channel_id],
+			data->resolution[cfg->channel_id]);
+
+		if (data->cal_handle[cfg->channel_id] != NULL) {
+			/* delete pre-existing calib scheme */
+			adc_cali_delete_scheme_curve_fitting(data->cal_handle[cfg->channel_id]);
+		}
+
+		adc_cali_create_scheme_curve_fitting(&cal_config,
+						     &data->cal_handle[cfg->channel_id]);
+#endif /* ADC_CALI_SCHEME_CURVE_FITTING_SUPPORTED */
+
+#if ADC_CALI_SCHEME_LINE_FITTING_SUPPORTED
+		adc_cali_line_fitting_config_t cal_config = {
+			.unit_id = conf->unit,
+			.atten = data->attenuation[cfg->channel_id],
+			.bitwidth = data->resolution[cfg->channel_id],
+#if CONFIG_SOC_SERIES_ESP32
+			.default_vref = data->meas_ref_internal
+#endif
+		};
+
+		LOG_DBG("Line fitting calib [unit_id: %u, chan: %u, atten: %u, bitwidth: %u]",
+			conf->unit, cfg->channel_id, data->attenuation[cfg->channel_id],
+			data->resolution[cfg->channel_id]);
+
+		if (data->cal_handle[cfg->channel_id] != NULL) {
+			/* delete pre-existing calib scheme */
+			adc_cali_delete_scheme_line_fitting(data->cal_handle[cfg->channel_id]);
 		}
-		LOG_DBG("Using ADC calibration method %d", cal);
+
+		adc_cali_create_scheme_line_fitting(&cal_config,
+						    &data->cal_handle[cfg->channel_id]);
+#endif /* ADC_CALI_SCHEME_LINE_FITTING_SUPPORTED */
 	}
 
 #if defined(CONFIG_ADC_ESP32_DMA)
-
 	if (!SOC_ADC_DIG_SUPPORTED_UNIT(conf->unit)) {
 		LOG_ERR("ADC2 dma mode is no longer supported, please use ADC1!");
 		return -EINVAL;
 	}
+#endif /* defined(CONFIG_ADC_ESP32_DMA) */
+
+	/* GPIO config for ADC mode */
 
 	int io_num = adc_channel_io_map[conf->unit][cfg->channel_id];
 
@@ -642,37 +651,50 @@ static int adc_esp32_channel_setup(const struct device *dev, const struct adc_ch
 		return err;
 	}
 
-#endif /* defined(CONFIG_ADC_ESP32_DMA) */
-
 	return 0;
 }
 
 static int adc_esp32_init(const struct device *dev)
 {
-	struct adc_esp32_data *data = (struct adc_esp32_data *) dev->data;
-	const struct adc_esp32_conf *conf = (struct adc_esp32_conf *) dev->config;
+	struct adc_esp32_data *data = (struct adc_esp32_data *)dev->data;
+	const struct adc_esp32_conf *conf = (struct adc_esp32_conf *)dev->config;
+	uint32_t clock_src_hz;
 
-	adc_hw_calibration(conf->unit);
-
-#if CONFIG_SOC_SERIES_ESP32S2 || CONFIG_SOC_SERIES_ESP32C3
-	if (conf->unit == ADC_UNIT_2) {
-		adc2_init_code_calibration();
+#if SOC_ADC_DIG_CTRL_SUPPORTED && !SOC_ADC_RTC_CTRL_SUPPORTED
+	if (!device_is_ready(conf->clock_dev)) {
+		return -ENODEV;
 	}
-#endif /* CONFIG_SOC_SERIES_ESP32S2 || CONFIG_SOC_SERIES_ESP32C3 */
 
-#if defined(CONFIG_ADC_ESP32_DMA)
+	clock_control_on(conf->clock_dev, conf->clock_subsys);
+#endif
+
+	esp_clk_tree_src_get_freq_hz(ADC_DIGI_CLK_SRC_DEFAULT,
+				     ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &clock_src_hz);
+
+	adc_oneshot_hal_cfg_t config = {
+		.unit = conf->unit,
+		.work_mode = ADC_HAL_SINGLE_READ_MODE,
+		.clk_src = ADC_DIGI_CLK_SRC_DEFAULT,
+		.clk_src_freq_hz = clock_src_hz,
+	};
+
+	adc_oneshot_hal_init(&data->hal, &config);
+
+	sar_periph_ctrl_adc_oneshot_power_acquire();
+
 	if (!device_is_ready(conf->gpio_port)) {
 		LOG_ERR("gpio0 port not ready");
 		return -ENODEV;
 	}
 
+#if defined(CONFIG_ADC_ESP32_DMA)
+
 	if (k_sem_init(&data->dma_conv_wait_lock, 0, 1)) {
 		LOG_ERR("dma_conv_wait_lock initialization failed!");
 		return -EINVAL;
 	}
 
-	data->adc_hal_dma_ctx.rx_desc = k_aligned_alloc(sizeof(uint32_t),
-							sizeof(dma_descriptor_t));
+	data->adc_hal_dma_ctx.rx_desc = k_aligned_alloc(sizeof(uint32_t), sizeof(dma_descriptor_t));
 	if (!data->adc_hal_dma_ctx.rx_desc) {
 		LOG_ERR("rx_desc allocation failed!");
 		return -ENOMEM;
@@ -689,66 +711,64 @@ static int adc_esp32_init(const struct device *dev)
 
 #endif /* defined(CONFIG_ADC_ESP32_DMA) */
 
-	for (uint8_t i = 0; i < ARRAY_SIZE(data->resolution); i++) {
+	for (uint8_t i = 0; i < SOC_ADC_MAX_CHANNEL_NUM; i++) {
 		data->resolution[i] = ADC_RESOLUTION_MAX;
-	}
-
-	for (uint8_t i = 0; i < ARRAY_SIZE(data->attenuation); i++) {
 		data->attenuation[i] = ADC_ATTEN_DB_0;
+		data->cal_handle[i] = NULL;
 	}
 
 	/* Default reference voltage. This could be calibrated externaly */
 	data->meas_ref_internal = ADC_ESP32_DEFAULT_VREF_INTERNAL;
 
-	/* Check if calibration is possible */
-	data->calibrate = adc_calibration_init(dev);
+	adc_hw_calibration(conf->unit);
 
 	return 0;
 }
 
 static DEVICE_API(adc, api_esp32_driver_api) = {
 	.channel_setup = adc_esp32_channel_setup,
-	.read          = adc_esp32_read,
+	.read = adc_esp32_read,
 #ifdef CONFIG_ADC_ASYNC
-	.read_async    = adc_esp32_read_async,
+	.read_async = adc_esp32_read_async,
 #endif /* CONFIG_ADC_ASYNC */
-	.ref_internal  = ADC_ESP32_DEFAULT_VREF_INTERNAL,
+	.ref_internal = ADC_ESP32_DEFAULT_VREF_INTERNAL,
 };
 
-#if defined(CONFIG_ADC_ESP32_DMA)
+#define ADC_ESP32_CONF_GPIO_PORT_INIT .gpio_port = DEVICE_DT_GET(DT_NODELABEL(gpio0)),
 
-#define ADC_ESP32_CONF_GPIO_PORT_INIT	.gpio_port = DEVICE_DT_GET(DT_NODELABEL(gpio0)),
+#if defined(CONFIG_ADC_ESP32_DMA)
 
-#define ADC_ESP32_CONF_DMA_INIT(n)	.dma_dev = COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas),     \
+#define ADC_ESP32_CONF_DMA_INIT(n)                                                                 \
+	.dma_dev = COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas),     \
 					(DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_IDX(n, 0))),           \
-					(NULL)),                                                   \
-					.dma_channel = COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \
+					(NULL)),                          \
+		 .dma_channel = COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), \
 					(DT_INST_DMAS_CELL_BY_IDX(n, 0, channel)),                 \
 					(0xff)),
 #else
 
-#define ADC_ESP32_CONF_GPIO_PORT_INIT
 #define ADC_ESP32_CONF_DMA_INIT(inst)
 
 #endif /* defined(CONFIG_ADC_ESP32_DMA) */
 
-#define ESP32_ADC_INIT(inst)							\
-										\
-	static const struct adc_esp32_conf adc_esp32_conf_##inst = {		\
-		.unit = DT_PROP(DT_DRV_INST(inst), unit) - 1,			\
-		.channel_count = DT_PROP(DT_DRV_INST(inst), channel_count),	\
-		ADC_ESP32_CONF_GPIO_PORT_INIT                                   \
-		ADC_ESP32_CONF_DMA_INIT(inst)                                   \
-	};									\
-										\
-	static struct adc_esp32_data adc_esp32_data_##inst = {			\
-	};									\
-										\
-DEVICE_DT_INST_DEFINE(inst, &adc_esp32_init, NULL,				\
-		&adc_esp32_data_##inst,						\
-		&adc_esp32_conf_##inst,						\
-		POST_KERNEL,							\
-		CONFIG_ADC_INIT_PRIORITY,					\
-		&api_esp32_driver_api);
+#define ESP32_ADC_INIT(inst)                                                                       \
+                                                                                                   \
+	static const struct adc_esp32_conf adc_esp32_conf_##inst = {                               \
+		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)),                             \
+		.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(inst, offset),         \
+		.unit = DT_PROP(DT_DRV_INST(inst), unit) - 1,                                      \
+		.channel_count = DT_PROP(DT_DRV_INST(inst), channel_count),                        \
+		ADC_ESP32_CONF_GPIO_PORT_INIT ADC_ESP32_CONF_DMA_INIT(inst)};                      \
+                                                                                                   \
+	static struct adc_esp32_data adc_esp32_data_##inst = {                                     \
+		.hal =                                                                             \
+			{                                                                          \
+				.dev = (adc_oneshot_soc_handle_t)DT_INST_REG_ADDR(inst),           \
+			},                                                                         \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(inst, &adc_esp32_init, NULL, &adc_esp32_data_##inst,                 \
+			      &adc_esp32_conf_##inst, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY,       \
+			      &api_esp32_driver_api);
 
 DT_INST_FOREACH_STATUS_OKAY(ESP32_ADC_INIT)
diff --git a/drivers/adc/adc_ifx_cat1.c b/drivers/adc/adc_ifx_cat1.c
index e247ee96209..3a4aa9f8746 100644
--- a/drivers/adc/adc_ifx_cat1.c
+++ b/drivers/adc/adc_ifx_cat1.c
@@ -22,32 +22,73 @@
 LOG_MODULE_REGISTER(ifx_cat1_adc, CONFIG_ADC_LOG_LEVEL);
 
 #if defined(PASS_SARMUX_PADS0_PORT)
-	#define _ADCSAR_PORT PASS_SARMUX_PADS0_PORT
+#define _ADC_PORT PASS_SARMUX_PADS0_PORT
+#elif defined(ADCMIC_GPIO_ADC_IN0_PORT)
+#define _ADC_PORT ADCMIC_GPIO_ADC_IN0_PORT
 #else
-	#error The selected device does not supported ADC
+#error The selected device does not supported ADC
 #endif
 
 #define ADC_CAT1_EVENTS_MASK (CYHAL_ADC_EOS | CYHAL_ADC_ASYNC_READ_COMPLETE)
 
 #define ADC_CAT1_DEFAULT_ACQUISITION_NS (1000u)
+#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1A)
 #define ADC_CAT1_RESOLUTION             (12u)
 #define ADC_CAT1_REF_INTERNAL_MV        (1200u)
+#elif defined(CONFIG_SOC_FAMILY_INFINEON_CAT1B)
+#define ADC_CAT1_RESOLUTION             (16u)
+#define ADC_CAT1_REF_INTERNAL_MV        (3600u)
+#endif
+
+#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1B)
+#define IFX_ADC_NUM_CHANNELS                                                                       \
+	ARRAY_SIZE(cyhal_pin_map_adcmic_gpio_adc_in)
+#else
+#define IFX_ADC_NUM_CHANNELS CY_SAR_SEQ_NUM_CHANNELS
+#endif
 
 struct ifx_cat1_adc_data {
 	struct adc_context ctx;
 	const struct device *dev;
 	cyhal_adc_t adc_obj;
-	cyhal_adc_channel_t adc_chan_obj[CY_SAR_SEQ_NUM_CHANNELS];
+	cyhal_adc_channel_t adc_chan_obj[IFX_ADC_NUM_CHANNELS];
 	uint16_t *buffer;
 	uint16_t *repeat_buffer;
 	uint32_t channels;
 	uint32_t channels_mask;
+#ifdef CONFIG_SOC_FAMILY_INFINEON_CAT1B
+	struct k_work adc_worker_thread;
+#endif
 };
 
 struct ifx_cat1_adc_config {
 	uint8_t irq_priority;
 };
 
+#ifdef CONFIG_SOC_FAMILY_INFINEON_CAT1B
+static void ifx_cat1_adc_worker(struct k_work *adc_worker_thread)
+{
+	struct ifx_cat1_adc_data *data =
+		CONTAINER_OF(adc_worker_thread, struct ifx_cat1_adc_data, adc_worker_thread);
+
+	uint32_t channels = data->channels;
+	int32_t result;
+	uint32_t channel_id;
+
+	while (channels != 0) {
+		channel_id = find_lsb_set(channels) - 1;
+		channels &= ~BIT(channel_id);
+
+		result = cyhal_adc_read(&data->adc_chan_obj[channel_id]);
+		/* Legacy API for BWC. Convert from signed to unsigned by adding 0x800 to
+		 * convert the lowest signed 12-bit number to 0x0.
+		 */
+		*data->buffer = (uint16_t)(result + 0x800);
+		data->buffer++;
+	}
+	adc_context_on_sampling_done(&data->ctx, data->dev);
+}
+#else
 static void _cyhal_adc_event_callback(void *callback_arg, cyhal_adc_event_t event)
 {
 	const struct device *dev = (const struct device *) callback_arg;
@@ -73,6 +114,7 @@ static void _cyhal_adc_event_callback(void *callback_arg, cyhal_adc_event_t even
 
 	LOG_DBG("%s ISR triggered.", dev->name);
 }
+#endif
 
 static void adc_context_start_sampling(struct adc_context *ctx)
 {
@@ -80,7 +122,11 @@ static void adc_context_start_sampling(struct adc_context *ctx)
 
 	data->repeat_buffer = data->buffer;
 
+#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1B)
+	k_work_submit(&data->adc_worker_thread);
+#else
 	Cy_SAR_StartConvert(data->adc_obj.base, CY_SAR_START_CONVERT_SINGLE_SHOT);
+#endif
 }
 
 static void adc_context_update_buffer_pointer(struct adc_context *ctx,
@@ -99,10 +145,10 @@ static int ifx_cat1_adc_channel_setup(const struct device *dev,
 	struct ifx_cat1_adc_data *data = dev->data;
 	cy_rslt_t result;
 
-	cyhal_gpio_t vplus = CYHAL_GET_GPIO(_ADCSAR_PORT, channel_cfg->input_positive);
-	cyhal_gpio_t vminus = channel_cfg->differential ?
-			      CYHAL_GET_GPIO(_ADCSAR_PORT, channel_cfg->input_negative) :
-			      CYHAL_ADC_VNEG;
+	cyhal_gpio_t vplus = CYHAL_GET_GPIO(_ADC_PORT, channel_cfg->input_positive);
+	cyhal_gpio_t vminus = channel_cfg->differential
+				      ? CYHAL_GET_GPIO(_ADC_PORT, channel_cfg->input_negative)
+				      : CYHAL_ADC_VNEG;
 	uint32_t acquisition_ns = ADC_CAT1_DEFAULT_ACQUISITION_NS;
 
 	if (channel_cfg->reference != ADC_REF_INTERNAL) {
@@ -158,7 +204,7 @@ static int validate_buffer_size(const struct adc_sequence *sequence)
 	int active_channels = 0;
 	int total_buffer_size;
 
-	for (int i = 0; i < CY_SAR_SEQ_NUM_CHANNELS; i++) {
+	for (int i = 0; i < IFX_ADC_NUM_CHANNELS; i++) {
 		if (sequence->channels & BIT(i)) {
 			active_channels++;
 		}
@@ -250,7 +296,7 @@ static int ifx_cat1_adc_init(const struct device *dev)
 	data->dev = dev;
 
 	/* Initialize ADC. The ADC block which can connect to the input pin is selected */
-	result = cyhal_adc_init(&data->adc_obj, CYHAL_GET_GPIO(_ADCSAR_PORT, 0), NULL);
+	result = cyhal_adc_init(&data->adc_obj, CYHAL_GET_GPIO(_ADC_PORT, 0), NULL);
 	if (result != CY_RSLT_SUCCESS) {
 		LOG_ERR("ADC initialization failed. Error: 0x%08X\n", (unsigned int)result);
 		return -EIO;
@@ -259,7 +305,10 @@ static int ifx_cat1_adc_init(const struct device *dev)
 	/* Enable ADC Interrupt */
 	cyhal_adc_enable_event(&data->adc_obj, (cyhal_adc_event_t)ADC_CAT1_EVENTS_MASK,
 			       config->irq_priority, true);
+
+#ifndef CONFIG_SOC_FAMILY_INFINEON_CAT1B
 	cyhal_adc_register_callback(&data->adc_obj, _cyhal_adc_event_callback, (void *) dev);
+#endif
 
 	adc_context_unlock_unconditionally(&data->ctx);
 
@@ -274,23 +323,25 @@ static DEVICE_API(adc, adc_cat1_driver_api) = {
 	#endif
 	.ref_internal = ADC_CAT1_REF_INTERNAL_MV
 };
+#ifdef CONFIG_SOC_FAMILY_INFINEON_CAT1B
+#define ADC_WORKER_THREAD_INIT() .adc_worker_thread = Z_WORK_INITIALIZER(ifx_cat1_adc_worker),
+#else
+#define ADC_WORKER_THREAD_INIT()
+#endif
 
 /* Macros for ADC instance declaration */
-#define INFINEON_CAT1_ADC_INIT(n)					       \
-	static struct ifx_cat1_adc_data ifx_cat1_adc_data##n = {	       \
-		ADC_CONTEXT_INIT_TIMER(ifx_cat1_adc_data##n, ctx),	       \
-		ADC_CONTEXT_INIT_LOCK(ifx_cat1_adc_data##n, ctx),	       \
-		ADC_CONTEXT_INIT_SYNC(ifx_cat1_adc_data##n, ctx),	       \
-	};								       \
-									       \
-	static const struct ifx_cat1_adc_config adc_cat1_cfg_##n = {	       \
-		.irq_priority = DT_INST_IRQ(n, priority),		       \
-	};								       \
-									       \
-	DEVICE_DT_INST_DEFINE(n, ifx_cat1_adc_init,			       \
-			      NULL, &ifx_cat1_adc_data##n,		       \
-			      &adc_cat1_cfg_##n,			       \
-			      POST_KERNEL, CONFIG_ADC_INIT_PRIORITY,	       \
+#define INFINEON_CAT1_ADC_INIT(n)                                                                  \
+	static struct ifx_cat1_adc_data ifx_cat1_adc_data##n = {                                   \
+		ADC_CONTEXT_INIT_TIMER(ifx_cat1_adc_data##n, ctx),                                 \
+		ADC_CONTEXT_INIT_LOCK(ifx_cat1_adc_data##n, ctx),                                  \
+		ADC_CONTEXT_INIT_SYNC(ifx_cat1_adc_data##n, ctx), ADC_WORKER_THREAD_INIT()};       \
+                                                                                                   \
+	static const struct ifx_cat1_adc_config adc_cat1_cfg_##n = {                               \
+		.irq_priority = DT_INST_IRQ(n, priority),                                          \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, ifx_cat1_adc_init, NULL, &ifx_cat1_adc_data##n,                   \
+			      &adc_cat1_cfg_##n, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY,            \
 			      &adc_cat1_driver_api);
 
 DT_INST_FOREACH_STATUS_OKAY(INFINEON_CAT1_ADC_INIT)
diff --git a/drivers/adc/adc_ite_it51xxx.c b/drivers/adc/adc_ite_it51xxx.c
new file mode 100644
index 00000000000..a057d1d2971
--- /dev/null
+++ b/drivers/adc/adc_ite_it51xxx.c
@@ -0,0 +1,470 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ite_it51xxx_adc
+
+#include <assert.h>
+#include <errno.h>
+#include <soc_dt.h>
+#include <soc.h>
+#include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/irq.h>
+
+#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(adc_ite_it51xxx);
+
+#define ADC_CONTEXT_USES_KERNEL_TIMER
+#include "adc_context.h"
+
+/* ADC internal reference voltage (Unit:mV) */
+#ifdef CONFIG_ADC_IT51XXX_VOL_FULL_SCALE
+#define IT51XXX_ADC_VREF_VOL 3300
+#else
+#define IT51XXX_ADC_VREF_VOL 3000
+#endif
+
+/* ADC sample time delay (Unit:us) */
+#define IT51XXX_ADC_SAMPLE_TIME_US      500
+/* Wait next clock rising (Clock source 32.768K) */
+#define IT51XXX_WAIT_NEXT_CLOCK_TIME_US 31
+
+/* ADC channels disabled */
+#define IT51XXX_ADC_CHANNEL_DISABLED 0x1F
+
+#ifdef CONFIG_ADC_IT51XXX_VOL_FULL_SCALE
+#define ADC_0_7_FULL_SCALE_MASK GENMASK(7, 0)
+#endif
+
+/* (45xxh) Analog to Digital Converter (ADC) registers */
+/* 0x00: Voltage Channel 0 Control */
+#define VCH0CTL     0x00
+/* 0x01: Voltage Channel 0 Data Buffer LSB */
+#define VCH0DATL    0x01
+/* 0x02: Voltage Channel 0 Data Buffer MSB */
+#define VCH0DATM    0x02
+/* 0x30: ADC Status 2 */
+#define ADCSTS2     0x30
+/* 0x31: ADC Clock Control */
+#define ADCCTL      0x31
+/* 0x32: ADC Clock Control 2 */
+#define ADCCTL2     0x32
+/* 0x34: ADC Input Voltage Mapping Full-Scale Code Selection 1 */
+#define ADCIVMFSCS1 0x34
+/* 0x35: ADC Input Voltage Mapping Full-Scale Code Selection 2 */
+#define ADCIVMFSCS2 0x35
+/* 0xC1: ADC Resolution Selection Register (ADCRSR) */
+#define ADCRSR      0xC1
+
+/* Automatic hardware calibration enable @ ADCCTL2 */
+#define IT51XXX_ADC_AHCE    BIT(6)
+/* ADC data buffer keep enable @ ADCCTL2 */
+#define IT51XXX_ADC_DBKEN   BIT(5)
+/* ADC conversion time select 0 @ ADCCTL2 */
+#define IT51XXX_ADC_ADCCTS0 BIT(3)
+
+/* ADC module enable @ ADCCTL */
+#define IT51XXX_ADC_ADCEN BIT(0)
+
+/* ADC conversion time select 1 @ ADCSTS2 */
+#define IT51XXX_ADC_ADCCTS1 BIT(7)
+/* Analog accuracy initialization @ ADCSTS2 */
+#define IT51XXX_ADC_AINITB  BIT(3)
+
+/* W/C data valid flag @ VCHnCTL */
+#define IT51XXX_ADC_DATVAL  BIT(7)
+/* Data valid interrupt of adc @ VCHnCTL */
+#define IT51XXX_ADC_INTDVEN BIT(5)
+
+/* 12-bit ADC Resolution Selection @ ADCRSR */
+#define IT51XXX_ADC_12bit BIT(0)
+
+struct adc_it51xxx_data {
+	struct adc_context ctx;
+	struct k_sem sem;
+	/* Channel ID */
+	uint32_t ch;
+	/* Save ADC result to the buffer. */
+	uint16_t *buffer;
+	/*
+	 * The sample buffer pointer should be prepared
+	 * for writing of next sampling results.
+	 */
+	uint16_t *repeat_buffer;
+};
+
+/*
+ * Structure adc_it51xxx_cfg is about the setting of adc
+ * this config will be used at initial time
+ */
+struct adc_it51xxx_cfg {
+	mm_reg_t base;
+	uint8_t channel_count;
+	/* ADC alternate configuration */
+	const struct pinctrl_dev_config *pcfg;
+};
+
+static int adc_it51xxx_channel_setup(const struct device *dev,
+				     const struct adc_channel_cfg *channel_cfg)
+{
+	uint8_t channel_id = channel_cfg->channel_id;
+
+	if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
+		LOG_ERR("Selected ADC acquisition time is not valid");
+		return -EINVAL;
+	}
+
+	/* Support channels 0~7 */
+	if (!(channel_id >= 0 && channel_id <= 7)) {
+		LOG_ERR("Channel %d is not valid", channel_id);
+		return -EINVAL;
+	}
+
+	if (channel_cfg->gain != ADC_GAIN_1) {
+		LOG_ERR("Invalid channel gain");
+		return -EINVAL;
+	}
+
+	if (channel_cfg->reference != ADC_REF_INTERNAL) {
+		LOG_ERR("Invalid channel reference");
+		return -EINVAL;
+	}
+
+	LOG_DBG("Channel setup succeeded!");
+
+	return 0;
+}
+
+static void adc_disable_measurement(const struct device *dev)
+{
+	const struct adc_it51xxx_cfg *config = dev->config;
+
+	/*
+	 * Disable measurement.
+	 * bit(4:0) = 0x1f : channel disable
+	 */
+	sys_write8(IT51XXX_ADC_DATVAL | IT51XXX_ADC_CHANNEL_DISABLED, config->base + VCH0CTL);
+
+	/* ADC module disable */
+	sys_write8(sys_read8(config->base + ADCCTL) & ~IT51XXX_ADC_ADCEN, config->base + ADCCTL);
+
+	/* disable adc interrupt */
+	irq_disable(DT_INST_IRQN(0));
+}
+
+static int adc_data_valid(const struct device *dev)
+{
+	const struct adc_it51xxx_cfg *config = dev->config;
+
+	return sys_read8(config->base + VCH0CTL) & IT51XXX_ADC_DATVAL;
+}
+
+/* Get result for each ADC selected channel. */
+static void adc_it51xxx_get_sample(const struct device *dev)
+{
+	struct adc_it51xxx_data *data = dev->data;
+	const struct adc_it51xxx_cfg *config = dev->config;
+	const uintptr_t base = config->base;
+
+	if (adc_data_valid(dev)) {
+		/* Read adc raw data of msb and lsb */
+		*data->buffer++ = FIELD_GET(GENMASK(7, 4), sys_read8(base + VCH0DATM)) << 8 |
+				  sys_read8(base + VCH0DATL);
+	} else {
+		LOG_WRN("ADC failed to read (regs=0x%x, ch=%d)", sys_read8(base + VCH0CTL),
+			data->ch);
+	}
+
+	adc_disable_measurement(dev);
+}
+
+static void adc_poll_valid_data(void)
+{
+	const struct device *const dev = DEVICE_DT_INST_GET(0);
+	int valid = 0;
+
+	/*
+	 * If the polling waits for a valid data longer than
+	 * the sampling time limit, the program will return.
+	 */
+	for (int i = 0U; i < (IT51XXX_ADC_SAMPLE_TIME_US / IT51XXX_WAIT_NEXT_CLOCK_TIME_US); i++) {
+		/* Wait next clock time (1/32.768K~=30.5us) */
+		k_busy_wait(IT51XXX_WAIT_NEXT_CLOCK_TIME_US);
+
+		if (adc_data_valid(dev)) {
+			valid = 1;
+			break;
+		}
+	}
+
+	if (valid) {
+		adc_it51xxx_get_sample(dev);
+	} else {
+		LOG_ERR("Sampling timeout.");
+		return;
+	}
+}
+
+static void adc_enable_measurement(uint32_t ch)
+{
+	const struct device *const dev = DEVICE_DT_INST_GET(0);
+	const struct adc_it51xxx_cfg *config = dev->config;
+	struct adc_it51xxx_data *data = dev->data;
+
+	/* Select and enable a voltage channel input for measurement */
+	sys_write8((IT51XXX_ADC_DATVAL | IT51XXX_ADC_INTDVEN) + ch, config->base + VCH0CTL);
+
+	/* ADC module enable */
+	sys_write8(sys_read8(config->base + ADCCTL) | IT51XXX_ADC_ADCEN, config->base + ADCCTL);
+
+	/*
+	 * In the sampling process, it is possible to read multiple channels
+	 * at a time. The ADC sampling of it51xxx needs to read each channel
+	 * in sequence, so it needs to wait for an interrupt to read data in
+	 * the loop through k_sem_take(). But k_timer_start() is used in the
+	 * interval test in test_adc.c, so we need to use polling wait instead
+	 * of k_sem_take() to wait, otherwise it will cause kernel panic.
+	 *
+	 * k_is_in_isr() can determine whether to use polling or k_sem_take()
+	 * at present.
+	 */
+	if (k_is_in_isr()) {
+		/* polling wait for a valid data */
+		adc_poll_valid_data();
+	} else {
+		/* Enable adc interrupt */
+		irq_enable(DT_INST_IRQN(0));
+		/* Wait for an interrupt to read valid data. */
+		k_sem_take(&data->sem, K_FOREVER);
+	}
+}
+
+static int check_buffer_size(const struct adc_sequence *sequence, uint8_t active_channels)
+{
+	size_t needed_buffer_size;
+
+	needed_buffer_size = active_channels * sizeof(uint16_t);
+	if (sequence->options) {
+		needed_buffer_size *= (1 + sequence->options->extra_samplings);
+	}
+
+	if (sequence->buffer_size < needed_buffer_size) {
+		LOG_ERR("Provided buffer is too small (%u/%u)", sequence->buffer_size,
+			needed_buffer_size);
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static int adc_it51xxx_start_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+	const struct adc_it51xxx_cfg *config = dev->config;
+	struct adc_it51xxx_data *data = dev->data;
+	struct adc_context *ctx = &data->ctx;
+	uint32_t channels = ctx->sequence.channels;
+	uint32_t channel_mask = sequence->channels;
+	uint8_t channel_count = 0;
+
+	if (!channel_mask || channel_mask & ~BIT_MASK(config->channel_count)) {
+		LOG_ERR("Invalid selection of channels");
+		return -EINVAL;
+	}
+
+	if (!sequence->resolution) {
+		LOG_ERR("ADC resolution is not valid");
+		return -EINVAL;
+	}
+
+	/*
+	 * The ADC sampling of it51xxx needs to read each channel
+	 * in sequence.
+	 */
+	while (channels) {
+		data->ch = find_lsb_set(channels) - 1;
+		channels &= ~BIT(data->ch);
+
+		adc_enable_measurement(data->ch);
+
+		channel_count++;
+	}
+
+	if (check_buffer_size(&ctx->sequence, channel_count)) {
+		return -ENOMEM;
+	}
+
+	data->buffer = sequence->buffer;
+
+	adc_context_start_read(&data->ctx, sequence);
+
+	return adc_context_wait_for_completion(&data->ctx);
+}
+
+static void adc_context_start_sampling(struct adc_context *ctx)
+{
+	struct adc_it51xxx_data *data = CONTAINER_OF(ctx, struct adc_it51xxx_data, ctx);
+
+	data->repeat_buffer = data->buffer;
+
+	adc_context_on_sampling_done(&data->ctx, DEVICE_DT_INST_GET(0));
+}
+
+static int adc_it51xxx_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+	struct adc_it51xxx_data *data = dev->data;
+	int err;
+
+	adc_context_lock(&data->ctx, false, NULL);
+	err = adc_it51xxx_start_read(dev, sequence);
+	adc_context_release(&data->ctx, err);
+
+	return err;
+}
+
+#ifdef CONFIG_ADC_ASYNC
+static int adc_it51xxx_read_async(const struct device *dev, const struct adc_sequence *sequence,
+				  struct k_poll_signal *async)
+{
+	struct adc_it51xxx_data *data = dev->data;
+	int err;
+
+	adc_context_lock(&data->ctx, true, async);
+	err = adc_it51xxx_start_read(dev, sequence);
+	adc_context_release(&data->ctx, err);
+
+	return err;
+}
+#endif /* CONFIG_ADC_ASYNC */
+
+static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
+{
+	struct adc_it51xxx_data *data = CONTAINER_OF(ctx, struct adc_it51xxx_data, ctx);
+
+	if (repeat_sampling) {
+		data->buffer = data->repeat_buffer;
+	}
+}
+
+static void adc_it51xxx_isr(const struct device *dev)
+{
+	struct adc_it51xxx_data *data = dev->data;
+
+	adc_it51xxx_get_sample(dev);
+
+	k_sem_give(&data->sem);
+}
+
+static DEVICE_API(adc, api_it51xxx_driver_api) = {
+	.channel_setup = adc_it51xxx_channel_setup,
+	.read = adc_it51xxx_read,
+#ifdef CONFIG_ADC_ASYNC
+	.read_async = adc_it51xxx_read_async,
+#endif
+	.ref_internal = IT51XXX_ADC_VREF_VOL,
+};
+
+/*
+ * ADC analog accuracy initialization (only once after VSTBY power on)
+ *
+ * Write 1 to this bit and write 0 to this bit immediately once and
+ * only once during the firmware initialization and do not write 1 again
+ * after initialization since IT51XXX takes much power consumption
+ * if this bit is set as 1
+ */
+static void adc_accuracy_initialization(const struct device *dev)
+{
+	const struct adc_it51xxx_cfg *config = dev->config;
+
+	/* Start adc accuracy initialization */
+	sys_write8(sys_read8(config->base + ADCSTS2) | IT51XXX_ADC_AINITB, config->base + ADCSTS2);
+	/* Enable automatic HW calibration. */
+	sys_write8(sys_read8(config->base + ADCCTL2) | IT51XXX_ADC_AHCE, config->base + ADCCTL2);
+	/* Stop adc accuracy initialization */
+	sys_write8(sys_read8(config->base + ADCSTS2) & ~IT51XXX_ADC_AINITB, config->base + ADCSTS2);
+}
+
+static int adc_it51xxx_init(const struct device *dev)
+{
+	const struct adc_it51xxx_cfg *config = dev->config;
+	struct adc_it51xxx_data *data = dev->data;
+	int status;
+
+#ifdef CONFIG_ADC_IT51XXX_VOL_FULL_SCALE
+	/* ADC input voltage 0V ~ AVCC (3.3V) is mapped into 0h-3FFh */
+	sys_write8(ADC_0_7_FULL_SCALE_MASK, config->base + ADCIVMFSCS1);
+#endif
+
+	/* 12-bit ADC Resolution Selection */
+	sys_write8(sys_read8(config->base + ADCRSR) | IT51XXX_ADC_12bit, config->base + ADCRSR);
+
+	/* ADC analog accuracy initialization */
+	adc_accuracy_initialization(dev);
+
+	/* Set the pin to ADC alternate function. */
+	status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+	if (status < 0) {
+		LOG_ERR("Failed to configure ADC pins");
+		return status;
+	}
+
+	/*
+	 * The ADC channel conversion time is 30.8*(SCLKDIV+1) us.
+	 * (Current setting is 61.6us)
+	 *
+	 * NOTE: A sample time delay (60us) also need to be included in
+	 * conversion time.
+	 * In addition, the ADC has a waiting time of 202.8us for
+	 * voltage stabilization.
+	 *
+	 * So the final ADC sample time result is ~= 324.4us.
+	 */
+	sys_write8(sys_read8(config->base + ADCSTS2) & ~IT51XXX_ADC_ADCCTS1,
+		   config->base + ADCSTS2);
+	sys_write8(sys_read8(config->base + ADCCTL2) & ~IT51XXX_ADC_ADCCTS0,
+		   config->base + ADCCTL2);
+
+	/*
+	 * bit[7-2]@ADCCTL : SCLKDIV
+	 * SCLKDIV has to be equal to or greater than 1h;
+	 *
+	 * Default value of SCLKDIV is 15h
+	 * Set SCLKDIV to 1h
+	 *
+	 */
+	sys_write8((sys_read8(config->base + ADCCTL) & GENMASK(1, 0)) | BIT(2),
+		   config->base + ADCCTL);
+
+	/*
+	 * Enable this bit, and data of VCHxDATL/VCHxDATM will be
+	 * kept until data valid is cleared.
+	 */
+	sys_write8(sys_read8(config->base + ADCCTL2) | IT51XXX_ADC_DBKEN, config->base + ADCCTL2);
+
+	IRQ_CONNECT(DT_INST_IRQN(0), 0, adc_it51xxx_isr, DEVICE_DT_INST_GET(0), 0);
+
+	k_sem_init(&data->sem, 0, 1);
+	adc_context_unlock_unconditionally(&data->ctx);
+
+	return 0;
+}
+
+static struct adc_it51xxx_data adc_it51xxx_data_0 = {
+	ADC_CONTEXT_INIT_TIMER(adc_it51xxx_data_0, ctx),
+	ADC_CONTEXT_INIT_LOCK(adc_it51xxx_data_0, ctx),
+	ADC_CONTEXT_INIT_SYNC(adc_it51xxx_data_0, ctx),
+};
+
+PINCTRL_DT_INST_DEFINE(0);
+
+static const struct adc_it51xxx_cfg adc_it51xxx_cfg_0 = {
+	.base = DT_INST_REG_ADDR(0),
+	.channel_count = DT_INST_PROP(0, channel_count),
+	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
+};
+
+DEVICE_DT_INST_DEFINE(0, adc_it51xxx_init, NULL, &adc_it51xxx_data_0, &adc_it51xxx_cfg_0,
+		      PRE_KERNEL_1, CONFIG_ADC_INIT_PRIORITY, &api_it51xxx_driver_api);
diff --git a/drivers/adc/adc_realtek_rts5912.c b/drivers/adc/adc_realtek_rts5912.c
new file mode 100644
index 00000000000..5f517209a7b
--- /dev/null
+++ b/drivers/adc/adc_realtek_rts5912.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2025 Realtek, SIBG-SD7
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT realtek_rts5912_adc
+
+#include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/clock_control_rts5912.h>
+#include <zephyr/drivers/pinctrl.h>
+
+#include "reg/reg_adc.h"
+
+#define ADC_CONTEXT_USES_KERNEL_TIMER
+#include "adc_context.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(adc_rts5912, CONFIG_ADC_LOG_LEVEL);
+
+#define RTS5912_ADC_MAX_CHAN        12
+#define RTS5912_ADC_POLLING_TIME_MS 1
+#define RTS5912_ADC_ENABLE_TIMEOUT  100
+
+struct adc_rts5912_config {
+	volatile struct adc_regs *regs;
+	const struct pinctrl_dev_config *pcfg;
+#ifdef CONFIG_CLOCK_CONTROL
+	const struct device *clk_dev;
+	struct rts5912_sccon_subsys sccon_cfg;
+#endif
+};
+
+struct adc_rts5912_data {
+	struct adc_context ctx;
+	const struct device *adc_dev;
+	volatile uint16_t *buffer;
+	volatile uint16_t *repeat_buffer;
+	uint32_t channels;
+};
+
+static void adc_context_start_sampling(struct adc_context *ctx)
+{
+	struct adc_rts5912_data *data = CONTAINER_OF(ctx, struct adc_rts5912_data, ctx);
+	const struct device *adc_dev = data->adc_dev;
+	const struct adc_rts5912_config *const cfg = adc_dev->config;
+	volatile struct adc_regs *regs = cfg->regs;
+
+	data->repeat_buffer = data->buffer;
+
+	regs->ctrl |= ADC_CTRL_SGLDNINTEN;
+	regs->ctrl |= ADC_CTRL_START;
+}
+
+static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
+{
+	struct adc_rts5912_data *data = CONTAINER_OF(ctx, struct adc_rts5912_data, ctx);
+
+	if (repeat_sampling) {
+		data->buffer = data->repeat_buffer;
+	}
+}
+
+static int adc_rts5912_channel_setup(const struct device *dev,
+				     const struct adc_channel_cfg *channel_cfg)
+{
+	const struct adc_rts5912_config *const cfg = dev->config;
+	volatile struct adc_regs *regs = cfg->regs;
+
+	if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
+		LOG_ERR("Conversion time not supported!");
+		return -EINVAL;
+	}
+
+	if (channel_cfg->channel_id >= RTS5912_ADC_MAX_CHAN) {
+		LOG_ERR("Channel %d not supported!", channel_cfg->channel_id);
+		return -EINVAL;
+	}
+
+	if (channel_cfg->gain != ADC_GAIN_1) {
+		LOG_ERR("ADC gain not supported!");
+		return -EINVAL;
+	}
+
+	uint8_t channel_id = channel_cfg->channel_id;
+
+	regs->chctrl |= ((0x01ul << channel_id) | (ADC_CHCTRL_LPFBP << channel_id));
+	LOG_DBG("CHCTRL = 0x%08x", regs->chctrl);
+
+	return 0;
+}
+
+static bool adc_rts5912_validate_buffer_size(const struct adc_sequence *sequence)
+{
+	int chan_count = 0;
+	size_t buff_need;
+	uint32_t chan_mask;
+
+	for (chan_mask = 0x80; chan_mask != 0; chan_mask >>= 1) {
+		if (chan_mask & sequence->channels) {
+			chan_count++;
+		}
+	}
+
+	buff_need = chan_count * sizeof(uint16_t);
+
+	if (sequence->options) {
+		buff_need *= 1 + sequence->options->extra_samplings;
+	}
+
+	if (buff_need > sequence->buffer_size) {
+		return false;
+	}
+
+	return true;
+}
+
+static int adc_rts5912_enable(const struct device *dev)
+{
+	const struct adc_rts5912_config *const cfg = dev->config;
+	volatile struct adc_regs *regs = cfg->regs;
+	int64_t st = k_uptime_get();
+
+	regs->ctrl |= ADC_CTRL_EN;
+	while ((k_uptime_get() - st) < RTS5912_ADC_ENABLE_TIMEOUT) {
+		if (regs->sts & ADC_STS_RDY) {
+			return 0;
+		}
+		k_msleep(RTS5912_ADC_POLLING_TIME_MS);
+	}
+
+	LOG_ERR("ADC enable timeout");
+	regs->ctrl &= ~ADC_CTRL_EN;
+
+	return -EIO;
+}
+
+static int adc_rts5912_start_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+	struct adc_rts5912_data *const data = dev->data;
+
+	if (sequence->channels & ~BIT_MASK(RTS5912_ADC_MAX_CHAN)) {
+		LOG_ERR("Incorrect channels, bitmask 0x%x", sequence->channels);
+		return -EINVAL;
+	}
+
+	if (sequence->channels == 0UL) {
+		LOG_ERR("No channel selected");
+		return -EINVAL;
+	}
+
+	if (!adc_rts5912_validate_buffer_size(sequence)) {
+		LOG_ERR("Incorrect buffer size");
+		return -ENOMEM;
+	}
+
+	data->channels = sequence->channels;
+	data->buffer = sequence->buffer;
+
+	if (adc_rts5912_enable(dev) < 0) {
+		return -EIO;
+	}
+
+	adc_context_start_read(&data->ctx, sequence);
+
+	return adc_context_wait_for_completion(&data->ctx);
+}
+
+static int adc_rts5912_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+	struct adc_rts5912_data *const data = dev->data;
+	int error;
+
+	adc_context_lock(&data->ctx, false, NULL);
+	error = adc_rts5912_start_read(dev, sequence);
+	adc_context_release(&data->ctx, error);
+
+	return error;
+}
+
+static void rts5912_adc_get_sample(const struct device *dev)
+{
+	const struct adc_rts5912_config *const cfg = dev->config;
+	volatile struct adc_regs *regs = cfg->regs;
+	struct adc_rts5912_data *const data = dev->data;
+	uint32_t idx;
+	uint32_t channels = data->channels;
+	uint32_t bit;
+
+	/*
+	 * Using the enabled channel bit set, from
+	 * lowest channel number to highest, find out
+	 * which channel is enabled and copy the ADC
+	 * values from hardware registers to the data
+	 * buffer.
+	 */
+	bit = find_lsb_set(channels);
+
+	while (bit != 0) {
+		idx = bit - 1;
+
+		*data->buffer = ((uint16_t)regs->chdata[idx] & ADC_CHDATA_RESULT_Msk);
+		data->buffer++;
+
+		LOG_DBG("idx=%d, data=%x", idx, regs->chdata[idx]);
+
+		channels &= ~BIT(idx);
+		bit = find_lsb_set(channels);
+	}
+}
+
+static void adc_rts5912_single_isr(const struct device *dev)
+{
+	const struct adc_rts5912_config *const cfg = dev->config;
+	volatile struct adc_regs *regs = cfg->regs;
+	struct adc_rts5912_data *const data = dev->data;
+
+	if (regs->sts & ADC_STS_SGLDN) {
+		LOG_DBG("single done interrupt triggered.");
+
+		regs->ctrl &= ~(ADC_CTRL_SGLDNINTEN);
+		regs->sts &= regs->sts;
+
+		rts5912_adc_get_sample(dev);
+
+		regs->ctrl &= ~ADC_CTRL_EN;
+		adc_context_on_sampling_done(&data->ctx, dev);
+	}
+}
+
+static int adc_rts5912_init(const struct device *dev)
+{
+	const struct adc_rts5912_config *const cfg = dev->config;
+	struct adc_rts5912_data *const data = dev->data;
+	volatile struct adc_regs *regs = cfg->regs;
+
+	int ret;
+
+	data->adc_dev = dev;
+
+	ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret != 0) {
+		LOG_ERR("rts5912 ADC pinctrl setup failed (%d)", ret);
+		return ret;
+	}
+
+#ifdef CONFIG_CLOCK_CONTROL
+	if (!device_is_ready(cfg->clk_dev)) {
+		LOG_ERR("clock \"%s\" device not ready", cfg->clk_dev->name);
+		return -ENODEV;
+	}
+
+	ret = clock_control_on(cfg->clk_dev, (clock_control_subsys_t)&cfg->sccon_cfg);
+	if (ret != 0) {
+		LOG_ERR("clock power on fail");
+		return ret;
+	}
+#endif
+
+	regs->ctrl = ADC_CTRL_RST;
+
+	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), adc_rts5912_single_isr,
+		    DEVICE_DT_INST_GET(0), 0);
+	irq_enable(DT_INST_IRQN(0));
+
+	adc_context_unlock_unconditionally(&data->ctx);
+
+	return 0;
+}
+
+#define DEV_CONFIG_CLK_DEV_INIT(n)                                                                 \
+	.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),                                          \
+	.sccon_cfg = {                                                                             \
+		.clk_grp = DT_INST_CLOCKS_CELL(n, clk_grp),                                        \
+		.clk_idx = DT_INST_CLOCKS_CELL(n, clk_idx),                                        \
+	}
+
+#define ADC_RTS5912_INIT(n)                                                                        \
+	PINCTRL_DT_INST_DEFINE(n);                                                                 \
+                                                                                                   \
+	static DEVICE_API(adc, adc_rts5912_api_##n) = {                                            \
+		.channel_setup = adc_rts5912_channel_setup,                                        \
+		.read = adc_rts5912_read,                                                          \
+		.ref_internal = DT_INST_PROP(n, vref_mv),                                          \
+	};                                                                                         \
+                                                                                                   \
+	static struct adc_rts5912_config adc_rts5912_dev_cfg_##n = {                               \
+		.regs = (struct adc_regs *)(DT_INST_REG_ADDR(n)),                                  \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                         \
+		DEV_CONFIG_CLK_DEV_INIT(n)};                                                       \
+                                                                                                   \
+	static struct adc_rts5912_data adc_rts5912_dev_data_##n = {                                \
+		ADC_CONTEXT_INIT_TIMER(adc_rts5912_dev_data_##n, ctx),                             \
+		ADC_CONTEXT_INIT_LOCK(adc_rts5912_dev_data_##n, ctx),                              \
+		ADC_CONTEXT_INIT_SYNC(adc_rts5912_dev_data_##n, ctx),                              \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, adc_rts5912_init, NULL, &adc_rts5912_dev_data_##n,                \
+			      &adc_rts5912_dev_cfg_##n, PRE_KERNEL_1, CONFIG_ADC_INIT_PRIORITY,    \
+			      &adc_rts5912_api_##n);
+
+DT_INST_FOREACH_STATUS_OKAY(ADC_RTS5912_INIT)
diff --git a/drivers/adc/adc_renesas_ra.c b/drivers/adc/adc_renesas_ra.c
index 9eadfc7a427..e448fcb4c40 100644
--- a/drivers/adc/adc_renesas_ra.c
+++ b/drivers/adc/adc_renesas_ra.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -36,8 +36,6 @@ void adc_scan_end_isr(void);
  * This structure contains constant data for given instance of RA ADC.
  */
 struct adc_ra_config {
-	/** Number of supported channels */
-	uint8_t num_channels;
 	/** Mask for channels existed in each board */
 	uint32_t channel_available_mask;
 	/** pinctrl configs */
@@ -155,16 +153,10 @@ static void adc_ra_isr(const struct device *dev)
  */
 static int adc_ra_check_buffer_size(const struct device *dev, const struct adc_sequence *sequence)
 {
-	const struct adc_ra_config *config = dev->config;
 	uint8_t channels = 0;
 	size_t needed;
-	uint32_t mask;
 
-	for (mask = BIT(config->num_channels - 1); mask != 0; mask >>= 1) {
-		if (mask & sequence->channels) {
-			channels++;
-		}
-	}
+	channels = POPCOUNT(sequence->channels);
 
 	needed = channels * sizeof(uint16_t);
 	if (sequence->options) {
@@ -202,7 +194,7 @@ static int adc_ra_start_read(const struct device *dev, const struct adc_sequence
 		return -ENOTSUP;
 	}
 
-	if (find_msb_set(sequence->channels) > config->num_channels) {
+	if ((sequence->channels & ~config->channel_available_mask) != 0) {
 		LOG_ERR("unsupported channels in mask: 0x%08x", sequence->channels);
 		return -ENOTSUP;
 	}
@@ -319,11 +311,12 @@ static int adc_ra_init(const struct device *dev)
 	return 0;
 }
 
+#define EVENT_ADC_SCAN_END(idx) BSP_PRV_IELS_ENUM(CONCAT(EVENT_ADC, idx, _SCAN_END))
+
 #define IRQ_CONFIGURE_FUNC(idx)                                                                    \
 	static void adc_ra_configure_func_##idx(void)                                              \
 	{                                                                                          \
-		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(idx, scanend, irq)] =                             \
-			ELC_EVENT_ADC##idx##_SCAN_END;                                             \
+		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(idx, scanend, irq)] = EVENT_ADC_SCAN_END(idx);    \
 		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, scanend, irq),                                \
 			    DT_INST_IRQ_BY_NAME(idx, scanend, priority), adc_ra_isr,               \
 			    DEVICE_DT_INST_GET(idx), 0);                                           \
@@ -354,7 +347,6 @@ static int adc_ra_init(const struct device *dev)
 		.ref_internal = DT_INST_PROP(idx, vref_mv),                                        \
 		IF_ENABLED(CONFIG_ADC_ASYNC, (.read_async = adc_ra_read_async))};                  \
 	static const struct adc_ra_config adc_ra_config_##idx = {                                  \
-		.num_channels = DT_INST_PROP(idx, channel_count),                                  \
 		.channel_available_mask = DT_INST_PROP(idx, channel_available_mask),               \
 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx),                                       \
 		IRQ_CONFIGURE_DEFINE(idx),                                                         \
diff --git a/drivers/adc/adc_renesas_rz.c b/drivers/adc/adc_renesas_rz.c
new file mode 100644
index 00000000000..2e18c04984e
--- /dev/null
+++ b/drivers/adc/adc_renesas_rz.c
@@ -0,0 +1,366 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_rz_adc
+
+#include <zephyr/drivers/adc.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+#include "r_adc_c.h"
+
+LOG_MODULE_REGISTER(adc_renesas_rz, CONFIG_ADC_LOG_LEVEL);
+
+#define ADC_CONTEXT_USES_KERNEL_TIMER
+#include "adc_context.h"
+
+#define ADC_RZ_MAX_RESOLUTION 12
+
+void adc_c_scan_end_isr(void);
+
+/**
+ * @brief RZ ADC config
+ *
+ * This structure contains constant config data for given instance of RZ ADC.
+ */
+struct adc_rz_config {
+	/** Mask for channels existed in each board */
+	uint32_t channel_available_mask;
+	/** Structure that handle FSP API */
+	const adc_api_t *fsp_api;
+};
+
+/**
+ * @brief RZ ADC data
+ *
+ * This structure contains data structures used by a RZ ADC.
+ */
+struct adc_rz_data {
+	/** Structure that handle state of ongoing read operation */
+	struct adc_context ctx;
+	/** Pointer to RZ ADC own device structure */
+	const struct device *dev;
+	/** Structure that handle fsp ADC */
+	adc_c_instance_ctrl_t fsp_ctrl;
+	/** Structure that handle fsp ADC config */
+	struct st_adc_cfg fsp_cfg;
+	/** Structure that handle fsp ADC channel config */
+	adc_c_channel_cfg_t fsp_channel_cfg;
+	/** Pointer to memory where next sample will be written */
+	uint16_t *buf;
+	/** Mask with channels that will be sampled */
+	uint32_t channels;
+	/** Buffer id */
+	uint16_t buf_id;
+};
+
+/**
+ * @brief Setup channels before starting to scan ADC
+ *
+ * @param dev RZ ADC device
+ * @param channel_cfg channel configuration (user-defined)
+ *
+ * @return 0 on success
+ * @return -ENOTSUP if channel id or differential is wrong value
+ * @return -EINVAL if channel configuration is invalid
+ */
+static int adc_rz_channel_setup(const struct device *dev, const struct adc_channel_cfg *channel_cfg)
+{
+
+	fsp_err_t fsp_err = FSP_SUCCESS;
+	struct adc_rz_data *data = dev->data;
+	const struct adc_rz_config *config = dev->config;
+
+	if (!((config->channel_available_mask & BIT(channel_cfg->channel_id)) != 0)) {
+		LOG_ERR("unsupported channel id '%d'", channel_cfg->channel_id);
+		return -ENOTSUP;
+	}
+
+	if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
+		LOG_ERR("Unsupported channel acquisition time");
+		return -ENOTSUP;
+	}
+
+	if (channel_cfg->differential) {
+		LOG_ERR("Differential channels are not supported");
+		return -ENOTSUP;
+	}
+
+	if (channel_cfg->gain != ADC_GAIN_1) {
+		LOG_ERR("Unsupported channel gain %d", channel_cfg->gain);
+		return -ENOTSUP;
+	}
+
+	if (channel_cfg->reference != ADC_REF_INTERNAL) {
+		LOG_ERR("Unsupported channel reference");
+		return -ENOTSUP;
+	}
+	data->fsp_channel_cfg.scan_mask |= (1U << channel_cfg->channel_id);
+	/** Enable channels. */
+	config->fsp_api->scanCfg(&data->fsp_ctrl, &data->fsp_channel_cfg);
+
+	if (FSP_SUCCESS != fsp_err) {
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+/**
+ * Interrupt handler
+ */
+static void adc_rz_isr(const struct device *dev)
+{
+	struct adc_rz_data *data = dev->data;
+	const struct adc_rz_config *config = dev->config;
+	fsp_err_t fsp_err = FSP_SUCCESS;
+	adc_channel_t channel_id = 0;
+	uint32_t channels = 0;
+	int16_t *sample_buffer = (int16_t *)data->buf;
+
+	channels = data->channels;
+	for (channel_id = 0; channels > 0; channel_id++) {
+		/** Get channel ids from scan mask "channels"  */
+		if ((channels & 0x01) != 0) {
+			/** Read converted data */
+			config->fsp_api->read(&data->fsp_ctrl, channel_id,
+					      &sample_buffer[data->buf_id]);
+			if (FSP_SUCCESS != fsp_err) {
+				break;
+			}
+			data->buf_id = data->buf_id + 1;
+		}
+		channels = channels >> 1;
+	}
+	adc_c_scan_end_isr();
+	adc_context_on_sampling_done(&data->ctx, dev);
+}
+
+/**
+ * @brief Check if buffer in @p sequence is big enough to hold all ADC samples
+ *
+ * @param dev RZ ADC device
+ * @param sequence ADC sequence description
+ *
+ * @return 0 on success
+ * @return -ENOMEM if buffer is not big enough
+ */
+static int adc_rz_check_buffer_size(const struct device *dev, const struct adc_sequence *sequence)
+{
+	uint8_t channels = 0;
+	size_t needed;
+
+	channels = POPCOUNT(sequence->channels);
+	needed = channels * sizeof(uint16_t);
+
+	if (sequence->options) {
+		needed *= (1 + sequence->options->extra_samplings);
+	}
+
+	if (sequence->buffer_size < needed) {
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Start processing read request
+ *
+ * @param dev RZ ADC device
+ * @param sequence ADC sequence description
+ *
+ * @return 0 on success
+ * @return -ENOTSUP if requested resolution or channel is out side of supported
+ *         range
+ * @return -ENOMEM if buffer is not big enough
+ *         (see @ref adc_rz_check_buffer_size)
+ * @return other error code returned by adc_context_wait_for_completion
+ */
+static int adc_rz_start_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+	const struct adc_rz_config *config = dev->config;
+	struct adc_rz_data *data = dev->data;
+	int err;
+
+	if (sequence->resolution > ADC_RZ_MAX_RESOLUTION || sequence->resolution == 0) {
+		LOG_ERR("unsupported resolution %d", sequence->resolution);
+		return -ENOTSUP;
+	}
+
+	if ((sequence->channels & ~config->channel_available_mask) != 0) {
+		LOG_ERR("unsupported channels in mask: 0x%08x", sequence->channels);
+		return -ENOTSUP;
+	}
+	err = adc_rz_check_buffer_size(dev, sequence);
+
+	if (err) {
+		LOG_ERR("buffer size too small");
+		return err;
+	}
+	data->buf_id = 0;
+	data->buf = sequence->buffer;
+	adc_context_start_read(&data->ctx, sequence);
+	adc_context_wait_for_completion(&data->ctx);
+
+	return 0;
+}
+
+/**
+ * @brief Start processing read request asynchronously.
+ *
+ * @param dev RZ ADC device
+ * @param sequence ADC sequence description
+ * @param async async pointer to asynchronous signal
+ *
+ * @return 0 on success
+ * @return -ENOTSUP if requested resolution or channel is out side of supported
+ *         range
+ * @return -ENOMEM if buffer is not big enough
+ *         (see @ref adc_rz_check_buffer_size)
+ * @return other error code returned by adc_context_wait_for_completion
+ */
+static int adc_rz_read_async(const struct device *dev, const struct adc_sequence *sequence,
+			     struct k_poll_signal *async)
+{
+	struct adc_rz_data *data = dev->data;
+	int err;
+
+	adc_context_lock(&data->ctx, async ? true : false, async);
+	err = adc_rz_start_read(dev, sequence);
+	adc_context_release(&data->ctx, err);
+
+	return err;
+}
+
+/**
+ * @brief Start processing read request synchronously.
+ *
+ * @param dev RZ ADC device
+ * @param sequence ADC sequence description
+ *
+ * @return 0 on success
+ * @return -ENOTSUP if requested resolution or channel is out side of supported
+ *         range
+ * @return -ENOMEM if buffer is not big enough
+ *         (see @ref adc_rz_check_buffer_size)
+ * @return other error code returned by adc_context_wait_for_completion
+ */
+static int adc_rz_read(const struct device *dev, const struct adc_sequence *sequence)
+{
+	return adc_rz_read_async(dev, sequence, NULL);
+}
+
+static void adc_context_start_sampling(struct adc_context *ctx)
+{
+	struct adc_rz_data *data = CONTAINER_OF(ctx, struct adc_rz_data, ctx);
+	const struct device *dev = data->dev;
+	const struct adc_rz_config *config = dev->config;
+
+	data->channels = ctx->sequence.channels;
+	/** Start a scan */
+	config->fsp_api->scanStart(&data->fsp_ctrl);
+}
+
+static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
+{
+	struct adc_rz_data *data = CONTAINER_OF(ctx, struct adc_rz_data, ctx);
+
+	if (repeat_sampling) {
+		data->buf_id = 0;
+	}
+}
+
+/**
+ * @brief Function called on init for each RZ ADC device. It setups all
+ *        channels.
+ *
+ * @param dev RZ ADC device
+ *
+ * @return -EIO if error
+ *
+ * @return 0 on success
+ */
+static int adc_rz_init(const struct device *dev)
+{
+	const struct adc_rz_config *config = dev->config;
+	struct adc_rz_data *data = dev->data;
+	fsp_err_t fsp_err = FSP_SUCCESS;
+	/**Open the ADC module */
+	config->fsp_api->open(&data->fsp_ctrl, &data->fsp_cfg);
+
+	if (FSP_SUCCESS != fsp_err) {
+		return -EIO;
+	}
+	/** Release context unconditionally */
+	adc_context_unlock_unconditionally(&data->ctx);
+
+	return 0;
+}
+
+/**
+ * ************************* DRIVER REGISTER SECTION ***************************
+ */
+
+#define ADC_RZG_IRQ_CONNECT(idx, irq_name, isr)                                                    \
+	do {                                                                                       \
+		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, irq_name, irq),                               \
+			    DT_INST_IRQ_BY_NAME(idx, irq_name, priority), isr,                     \
+			    DEVICE_DT_INST_GET(idx), 0);                                           \
+		irq_enable(DT_INST_IRQ_BY_NAME(idx, irq_name, irq));                               \
+	} while (0)
+
+#define ADC_RZG_CONFIG_FUNC(idx) ADC_RZG_IRQ_CONNECT(idx, scanend, adc_rz_isr);
+
+#define ADC_RZG_INIT(idx)                                                                          \
+	static const adc_c_extended_cfg_t g_adc##idx##_cfg_extend = {                              \
+		.trigger_mode = ADC_C_TRIGGER_MODE_SOFTWARE,                                       \
+		.trigger_source = ADC_C_ACTIVE_TRIGGER_EXTERNAL,                                   \
+		.trigger_edge = ADC_C_TRIGGER_EDGE_FALLING,                                        \
+		.input_mode = ADC_C_INPUT_MODE_AUTO,                                               \
+		.operating_mode = ADC_C_OPERATING_MODE_SCAN,                                       \
+		.buffer_mode = ADC_C_BUFFER_MODE_1,                                                \
+		.sampling_time = 100,                                                              \
+		.external_trigger_filter = ADC_C_FILTER_STAGE_SETTING_DISABLE,                     \
+	};                                                                                         \
+	static DEVICE_API(adc, adc_rz_api_##idx) = {                                               \
+		.channel_setup = adc_rz_channel_setup,                                             \
+		.read = adc_rz_read,                                                               \
+		.ref_internal = DT_INST_PROP(idx, vref_mv),                                        \
+		IF_ENABLED(CONFIG_ADC_ASYNC,                                                       \
+					  (.read_async = adc_rz_read_async))};                     \
+	static const struct adc_rz_config adc_rz_config_##idx = {                                  \
+		.channel_available_mask = DT_INST_PROP(idx, channel_available_mask),               \
+		.fsp_api = &g_adc_on_adc,                                                          \
+	};                                                                                         \
+	static struct adc_rz_data adc_rz_data_##idx = {                                            \
+		ADC_CONTEXT_INIT_TIMER(adc_rz_data_##idx, ctx),                                    \
+		ADC_CONTEXT_INIT_LOCK(adc_rz_data_##idx, ctx),                                     \
+		ADC_CONTEXT_INIT_SYNC(adc_rz_data_##idx, ctx),                                     \
+		.dev = DEVICE_DT_INST_GET(idx),                                                    \
+		.fsp_cfg =                                                                         \
+			{                                                                          \
+				.mode = ADC_MODE_SINGLE_SCAN,                                      \
+				.p_callback = NULL,                                                \
+				.p_context = NULL,                                                 \
+				.p_extend = &g_adc##idx##_cfg_extend,                              \
+				.scan_end_irq = DT_INST_IRQ_BY_NAME(idx, scanend, irq),            \
+				.scan_end_ipl = DT_INST_IRQ_BY_NAME(idx, scanend, priority),       \
+			},                                                                         \
+		.fsp_channel_cfg =                                                                 \
+			{                                                                          \
+				.scan_mask = 0,                                                    \
+				.interrupt_setting = ADC_C_INTERRUPT_CHANNEL_SETTING_ENABLE,       \
+			},                                                                         \
+	};                                                                                         \
+	static int adc_rz_init_##idx(const struct device *dev)                                     \
+	{                                                                                          \
+		ADC_RZG_CONFIG_FUNC(idx)                                                           \
+		return adc_rz_init(dev);                                                           \
+	}                                                                                          \
+	DEVICE_DT_INST_DEFINE(idx, adc_rz_init_##idx, NULL, &adc_rz_data_##idx,                    \
+			      &adc_rz_config_##idx, POST_KERNEL, CONFIG_ADC_INIT_PRIORITY,         \
+			      &adc_rz_api_##idx)
+
+DT_INST_FOREACH_STATUS_OKAY(ADC_RZG_INIT);
diff --git a/drivers/adc/adc_rpi_pico.c b/drivers/adc/adc_rpi_pico.c
index 5dffdd6ba00..f2a5b73356e 100644
--- a/drivers/adc/adc_rpi_pico.c
+++ b/drivers/adc/adc_rpi_pico.c
@@ -27,9 +27,9 @@ LOG_MODULE_REGISTER(adc_rpi, CONFIG_ADC_LOG_LEVEL);
 #define ADC_RPI_CHANNEL_NUM (ADC_CS_RROBIN_MSB - ADC_CS_RROBIN_LSB + 1)
 
 /**
- * @brief RaspberryPi Pico ADC config
+ * @brief Raspberry Pi Pico ADC config
  *
- * This structure contains constant data for given instance of RaspberryPi Pico ADC.
+ * This structure contains constant data for given instance of Raspberry Pi Pico ADC.
  */
 struct adc_rpi_config {
 	/** Number of supported channels */
@@ -47,14 +47,14 @@ struct adc_rpi_config {
 };
 
 /**
- * @brief RaspberryPi Pico ADC data
+ * @brief Raspberry Pi Pico ADC data
  *
- * This structure contains data structures used by a RaspberryPi Pico ADC.
+ * This structure contains data structures used by a Raspberry Pi Pico ADC.
  */
 struct adc_rpi_data {
 	/** Structure that handle state of ongoing read operation */
 	struct adc_context ctx;
-	/** Pointer to RaspberryPi Pico ADC own device structure */
+	/** Pointer to Raspberry Pi Pico ADC own device structure */
 	const struct device *dev;
 	/** Pointer to memory where next sample will be written */
 	uint16_t *buf;
@@ -127,7 +127,7 @@ static int adc_rpi_channel_setup(const struct device *dev,
 /**
  * @brief Check if buffer in @p sequence is big enough to hold all ADC samples
  *
- * @param dev RaspberryPi Pico ADC device
+ * @param dev Raspberry Pi Pico ADC device
  * @param sequence ADC sequence description
  *
  * @return 0 on success
@@ -162,7 +162,7 @@ static int adc_rpi_check_buffer_size(const struct device *dev,
 /**
  * @brief Start processing read request
  *
- * @param dev RaspberryPi Pico ADC device
+ * @param dev Raspberry Pi Pico ADC device
  * @param sequence ADC sequence description
  *
  * @return 0 on success
@@ -290,10 +290,10 @@ static void adc_context_update_buffer_pointer(struct adc_context *ctx,
 }
 
 /**
- * @brief Function called on init for each RaspberryPi Pico ADC device. It setups all
+ * @brief Function called on init for each Raspberry Pi Pico ADC device. It setups all
  *        channels to return constant 0 mV and create acquisition thread.
  *
- * @param dev RaspberryPi Pico ADC device
+ * @param dev Raspberry Pi Pico ADC device
  *
  * @return 0 on success
  */
diff --git a/drivers/adc/adc_sam0.c b/drivers/adc/adc_sam0.c
index 7cf31bc2ef5..bc766b7278f 100644
--- a/drivers/adc/adc_sam0.c
+++ b/drivers/adc/adc_sam0.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
+ * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -14,6 +15,8 @@
 #include <zephyr/irq.h>
 LOG_MODULE_REGISTER(adc_sam0, CONFIG_ADC_LOG_LEVEL);
 
+/* clang-format off */
+
 #define ADC_CONTEXT_USES_KERNEL_TIMER
 #include "adc_context.h"
 
@@ -46,18 +49,12 @@ struct adc_sam0_data {
 struct adc_sam0_cfg {
 	Adc *regs;
 	const struct pinctrl_dev_config *pcfg;
-
-#ifdef MCLK
+	volatile uint32_t *mclk;
 	uint32_t mclk_mask;
-	uint32_t gclk_mask;
+	uint32_t gclk_gen;
 	uint16_t gclk_id;
-#else
-	uint32_t gclk;
-#endif
-
 	uint32_t freq;
 	uint16_t prescaler;
-
 	void (*config_func)(const struct device *dev);
 };
 
@@ -180,7 +177,6 @@ static int adc_sam0_channel_setup(const struct device *dev,
 #endif
 	}
 
-
 	uint32_t inputctrl = 0;
 
 	switch (channel_cfg->gain) {
@@ -258,7 +254,6 @@ static int adc_sam0_channel_setup(const struct device *dev,
 		break;
 	}
 
-
 	return 0;
 }
 
@@ -328,6 +323,12 @@ static int start_read(const struct device *dev,
 	}
 
 	adc->AVGCTRL.reg = ADC_AVGCTRL_SAMPLENUM(sequence->oversampling);
+	if (sequence->oversampling < 4) {
+		adc->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(sequence->oversampling);
+	} else {
+		adc->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(4);
+	}
+
 	/* AVGCTRL is not synchronized */
 
 #ifdef CONFIG_SOC_SERIES_SAMD20
@@ -449,14 +450,15 @@ static int adc_sam0_init(const struct device *dev)
 	Adc *const adc = cfg->regs;
 	int retval;
 
-#ifdef MCLK
-	GCLK->PCHCTRL[cfg->gclk_id].reg = cfg->gclk_mask | GCLK_PCHCTRL_CHEN;
+	*cfg->mclk |= cfg->mclk_mask;
 
-	MCLK_ADC |= cfg->mclk_mask;
+#ifdef MCLK
+	GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_CHEN
+					| GCLK_PCHCTRL_GEN(cfg->gclk_gen);
 #else
-	PM->APBCMASK.bit.ADC_ = 1;
-
-	GCLK->CLKCTRL.reg = cfg->gclk | GCLK_CLKCTRL_CLKEN;
+	GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
+			  | GCLK_CLKCTRL_GEN(cfg->gclk_gen)
+			  | GCLK_CLKCTRL_ID(cfg->gclk_id);
 #endif
 
 	retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
@@ -515,81 +517,82 @@ static DEVICE_API(adc, adc_sam0_api) = {
 
 #ifdef MCLK
 
-#define ADC_SAM0_CLOCK_CONTROL(n)					\
-	.mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)),	\
-	.gclk_mask = UTIL_CAT(GCLK_PCHCTRL_GEN_GCLK,			\
-			      DT_INST_PROP(n, gclk)),			\
-	.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),	\
-	.prescaler = UTIL_CAT(ADC_CTRLx_PRESCALER_DIV,			\
-			      UTIL_CAT(DT_INST_PROP(n, prescaler), _Val)),
-
-#define ADC_SAM0_CONFIGURE(n)						\
-do {									\
-	const struct adc_sam0_cfg *const cfg = dev->config;		\
-	Adc * const adc = cfg->regs;					\
-	adc->CALIB.reg = ADC_SAM0_BIASCOMP(n)				\
-			 | ADC_SAM0_BIASR2R(n)				\
-			 | ADC_SAM0_BIASREFBUF(n);			\
+#define ADC_SAM0_CONFIGURE(n)							\
+do {										\
+	const struct adc_sam0_cfg *const cfg = dev->config;			\
+	Adc * const adc = cfg->regs;						\
+	adc->CALIB.reg = ADC_SAM0_BIASCOMP(n)					\
+			 | ADC_SAM0_BIASR2R(n)					\
+			 | ADC_SAM0_BIASREFBUF(n);				\
 } while (false)
 
 #else
 
-#define ADC_SAM0_CLOCK_CONTROL(n)					\
-	.gclk = UTIL_CAT(GCLK_CLKCTRL_GEN_GCLK,	DT_INST_PROP(n, gclk)) |\
-			 GCLK_CLKCTRL_ID_ADC,				\
-	.prescaler = UTIL_CAT(ADC_CTRLx_PRESCALER_DIV,			\
-			      UTIL_CAT(DT_INST_PROP(n, prescaler), _Val)),
-
-#define ADC_SAM0_CONFIGURE(n)						\
-do {									\
-	const struct adc_sam0_cfg *const cfg = dev->config;		\
-	Adc * const adc = cfg->regs;					\
-	/* Linearity is split across two words */			\
+#define ADC_SAM0_CONFIGURE(n)							\
+do {										\
+	const struct adc_sam0_cfg *const cfg = dev->config;			\
+	Adc * const adc = cfg->regs;						\
+	/* Linearity is split across two words */				\
 	uint32_t lin = ((*(uint32_t *)ADC_FUSES_LINEARITY_0_ADDR) &		\
-		     ADC_FUSES_LINEARITY_0_Msk) >>			\
-		     ADC_FUSES_LINEARITY_0_Pos;				\
-	lin |= (((*(uint32_t *)ADC_FUSES_LINEARITY_1_ADDR) &		\
-		 ADC_FUSES_LINEARITY_1_Msk) >>				\
-		 ADC_FUSES_LINEARITY_1_Pos) << 4;			\
+		     ADC_FUSES_LINEARITY_0_Msk) >>				\
+		     ADC_FUSES_LINEARITY_0_Pos;					\
+	lin |= (((*(uint32_t *)ADC_FUSES_LINEARITY_1_ADDR) &			\
+		 ADC_FUSES_LINEARITY_1_Msk) >>					\
+		 ADC_FUSES_LINEARITY_1_Pos) << 4;				\
 	uint32_t bias = ((*(uint32_t *)ADC_FUSES_BIASCAL_ADDR) &		\
-		      ADC_FUSES_BIASCAL_Msk) >> ADC_FUSES_BIASCAL_Pos;	\
-	adc->CALIB.reg = ADC_CALIB_BIAS_CAL(bias) |			\
-			 ADC_CALIB_LINEARITY_CAL(lin);			\
+		      ADC_FUSES_BIASCAL_Msk) >> ADC_FUSES_BIASCAL_Pos;		\
+	adc->CALIB.reg = ADC_CALIB_BIAS_CAL(bias) |				\
+			 ADC_CALIB_LINEARITY_CAL(lin);				\
 } while (false)
 
 #endif
 
-#define ADC_SAM0_DEVICE(n)						\
-	PINCTRL_DT_INST_DEFINE(n);					\
-	static void adc_sam0_config_##n(const struct device *dev);	\
-	static const struct adc_sam0_cfg adc_sam_cfg_##n = {		\
-		.regs = (Adc *)DT_INST_REG_ADDR(n),			\
-		ADC_SAM0_CLOCK_CONTROL(n)				\
-		.freq = UTIL_CAT(UTIL_CAT(SOC_ATMEL_SAM0_GCLK,		\
-					  DT_INST_PROP(n, gclk)),	\
-					  _FREQ_HZ) /			\
-			DT_INST_PROP(n, prescaler),			\
-		.config_func = &adc_sam0_config_##n,			\
-		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),		\
-	};								\
-	static struct adc_sam0_data adc_sam_data_##n = {		\
-		ADC_CONTEXT_INIT_TIMER(adc_sam_data_##n, ctx),		\
-		ADC_CONTEXT_INIT_LOCK(adc_sam_data_##n, ctx),		\
-		ADC_CONTEXT_INIT_SYNC(adc_sam_data_##n, ctx),		\
-	};								\
-	DEVICE_DT_INST_DEFINE(n, adc_sam0_init, NULL,			\
-			    &adc_sam_data_##n,				\
-			    &adc_sam_cfg_##n, POST_KERNEL,		\
-			    CONFIG_ADC_INIT_PRIORITY,			\
-			    &adc_sam0_api);				\
-	static void adc_sam0_config_##n(const struct device *dev)	\
-	{								\
-		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, resrdy, irq),	\
-			    DT_INST_IRQ_BY_NAME(n, resrdy, priority),	\
-			    adc_sam0_isr,				\
-			    DEVICE_DT_INST_GET(n), 0);			\
-		irq_enable(DT_INST_IRQ_BY_NAME(n, resrdy, irq));	\
-		ADC_SAM0_CONFIGURE(n);					\
+#define ASSIGNED_CLOCKS_CELL_BY_NAME						\
+	ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_NAME
+
+#define ADC_SAM0_GCLK_FREQ(n)							\
+	UTIL_CAT(UTIL_CAT(SOC_ATMEL_SAM0_GCLK,					\
+			  ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen)),		\
+		 _FREQ_HZ)
+
+#define ADC_SAM0_FREQ(n)							\
+	.prescaler = UTIL_CAT(ADC_CTRLx_PRESCALER_DIV,				\
+			      UTIL_CAT(DT_INST_PROP(n, prescaler), _Val)),	\
+	.freq = ADC_SAM0_GCLK_FREQ(n) / DT_INST_PROP(n, prescaler)
+
+#define ADC_SAM0_DEVICE(n)							\
+	PINCTRL_DT_INST_DEFINE(n);						\
+	static void adc_sam0_config_##n(const struct device *dev);		\
+	static const struct adc_sam0_cfg adc_sam_cfg_##n = {			\
+		.regs = (Adc *)DT_INST_REG_ADDR(n),				\
+		.gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen),		\
+		.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id),		\
+		.mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n),		\
+		.mclk_mask = ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(n, bit),	\
+		ADC_SAM0_FREQ(n),						\
+		.config_func = &adc_sam0_config_##n,				\
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
+	};									\
+	static struct adc_sam0_data adc_sam_data_##n = {			\
+		ADC_CONTEXT_INIT_TIMER(adc_sam_data_##n, ctx),			\
+		ADC_CONTEXT_INIT_LOCK(adc_sam_data_##n, ctx),			\
+		ADC_CONTEXT_INIT_SYNC(adc_sam_data_##n, ctx),			\
+	};									\
+	DEVICE_DT_INST_DEFINE(n, adc_sam0_init, NULL,				\
+			    &adc_sam_data_##n,					\
+			    &adc_sam_cfg_##n, POST_KERNEL,			\
+			    CONFIG_ADC_INIT_PRIORITY,				\
+			    &adc_sam0_api);					\
+	static void adc_sam0_config_##n(const struct device *dev)		\
+	{									\
+		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, resrdy, irq),		\
+			    DT_INST_IRQ_BY_NAME(n, resrdy, priority),		\
+			    adc_sam0_isr,					\
+			    DEVICE_DT_INST_GET(n), 0);				\
+		irq_enable(DT_INST_IRQ_BY_NAME(n, resrdy, irq));		\
+		ADC_SAM0_CONFIGURE(n);						\
 	}
 
 DT_INST_FOREACH_STATUS_OKAY(ADC_SAM0_DEVICE)
+
+/* clang-format on */
diff --git a/drivers/adc/adc_shell.c b/drivers/adc/adc_shell.c
index a3f11647cc0..b4501fd1343 100644
--- a/drivers/adc/adc_shell.c
+++ b/drivers/adc/adc_shell.c
@@ -75,6 +75,7 @@ static struct adc_hdl {
 	uint8_t resolution;
 } adc_list[] = {
 	/* zephyr-keep-sorted-start */
+	DT_FOREACH_STATUS_OKAY(adi_ad4114_adc, ADC_HDL_LIST_ENTRY)
 	DT_FOREACH_STATUS_OKAY(adi_ad559x_adc, ADC_HDL_LIST_ENTRY)
 	DT_FOREACH_STATUS_OKAY(atmel_sam0_adc, ADC_HDL_LIST_ENTRY)
 	DT_FOREACH_STATUS_OKAY(atmel_sam_adc, ADC_HDL_LIST_ENTRY)
@@ -83,6 +84,7 @@ static struct adc_hdl {
 	DT_FOREACH_STATUS_OKAY(gd_gd32_adc, ADC_HDL_LIST_ENTRY)
 	DT_FOREACH_STATUS_OKAY(infineon_cat1_adc, ADC_HDL_LIST_ENTRY)
 	DT_FOREACH_STATUS_OKAY(infineon_xmc4xxx_adc, ADC_HDL_LIST_ENTRY)
+	DT_FOREACH_STATUS_OKAY(ite_it51xxx_adc, ADC_HDL_LIST_ENTRY)
 	DT_FOREACH_STATUS_OKAY(ite_it8xxx2_adc, ADC_HDL_LIST_ENTRY)
 	DT_FOREACH_STATUS_OKAY(lltc_ltc2451, ADC_HDL_LIST_ENTRY)
 	DT_FOREACH_STATUS_OKAY(maxim_max11102, ADC_HDL_LIST_ENTRY)
diff --git a/drivers/adc/adc_stm32.c b/drivers/adc/adc_stm32.c
index 1e246668bb6..fd800823470 100644
--- a/drivers/adc/adc_stm32.c
+++ b/drivers/adc/adc_stm32.c
@@ -18,12 +18,14 @@
 #include <zephyr/device.h>
 #include <zephyr/kernel.h>
 #include <zephyr/init.h>
+#include <zephyr/toolchain.h>
 #include <soc.h>
 #include <zephyr/pm/device.h>
 #include <zephyr/pm/policy.h>
 #include <stm32_ll_adc.h>
 #include <stm32_ll_system.h>
-#if defined(CONFIG_SOC_SERIES_STM32U5X)
+#if defined(CONFIG_SOC_SERIES_STM32N6X) || \
+	defined(CONFIG_SOC_SERIES_STM32U5X)
 #include <stm32_ll_pwr.h>
 #endif /* CONFIG_SOC_SERIES_STM32U5X */
 
@@ -52,12 +54,7 @@ LOG_MODULE_REGISTER(adc_stm32);
 #include <stm32_ll_system.h>
 #endif
 
-#ifdef CONFIG_NOCACHE_MEMORY
 #include <zephyr/linker/linker-defs.h>
-#elif defined(CONFIG_CACHE_MANAGEMENT)
-#include <zephyr/arch/cache.h>
-#endif /* CONFIG_NOCACHE_MEMORY */
-
 
 /* Here are some redefinitions of ADC versions for better readability */
 #if defined(CONFIG_SOC_SERIES_STM32F3X)
@@ -157,11 +154,17 @@ struct stream {
 };
 #endif /* CONFIG_ADC_STM32_DMA */
 
+#if defined(CONFIG_SOC_SERIES_STM32N6X)
+typedef uint32_t adc_data_size_t;
+#else
+typedef uint16_t adc_data_size_t;
+#endif
+
 struct adc_stm32_data {
 	struct adc_context ctx;
 	const struct device *dev;
-	uint16_t *buffer;
-	uint16_t *repeat_buffer;
+	adc_data_size_t *buffer;
+	adc_data_size_t *repeat_buffer;
 
 	uint8_t resolution;
 	uint32_t channels;
@@ -196,7 +199,9 @@ static void adc_stm32_enable_dma_support(ADC_TypeDef *adc)
 	/* Allow ADC to create DMA request and set to one-shot mode as implemented in HAL drivers */
 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
 	LL_ADC_REG_SetDMATransfer(adc, LL_ADC_REG_DMA_TRANSFER_UNLIMITED);
-#elif defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32U5X)
+#elif defined(CONFIG_SOC_SERIES_STM32H7X) || \
+	defined(CONFIG_SOC_SERIES_STM32N6X) || \
+	defined(CONFIG_SOC_SERIES_STM32U5X)
 	/* H72x ADC3 and U5 ADC4 are different from the rest, but this call works also for them,
 	 * so no need to call their specific function
 	 */
@@ -221,7 +226,7 @@ static int adc_stm32_dma_start(const struct device *dev,
 	blk_cfg = &dma->dma_blk_cfg;
 
 	/* prepare the block */
-	blk_cfg->block_size = channel_count * sizeof(int16_t);
+	blk_cfg->block_size = channel_count * sizeof(adc_data_size_t);
 
 	/* Source and destination */
 	blk_cfg->source_address = (uint32_t)LL_ADC_DMA_GetRegAddr(adc, LL_ADC_DMA_REG_REGULAR_DATA);
@@ -272,7 +277,7 @@ static int adc_stm32_dma_start(const struct device *dev,
  *		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) | ... )>;
  *	};
  */
-static bool buf_in_nocache(uintptr_t buf, size_t len_bytes)
+static bool buf_in_nocache(uintptr_t buf __maybe_unused, size_t len_bytes __maybe_unused)
 {
 	bool buf_within_nocache = false;
 
@@ -284,8 +289,10 @@ static bool buf_in_nocache(uintptr_t buf, size_t len_bytes)
 	}
 #endif /* CONFIG_NOCACHE_MEMORY */
 
+#ifdef CONFIG_MEM_ATTR
 	buf_within_nocache = mem_attr_check_buf(
 		(void *)buf, len_bytes, DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)) == 0;
+#endif /* CONFIG_MEM_ATTR */
 
 	return buf_within_nocache;
 }
@@ -296,7 +303,7 @@ static int check_buffer(const struct adc_sequence *sequence,
 {
 	size_t needed_buffer_size;
 
-	needed_buffer_size = active_channels * sizeof(uint16_t);
+	needed_buffer_size = active_channels * sizeof(adc_data_size_t);
 
 	if (sequence->options) {
 		needed_buffer_size *= (1 + sequence->options->extra_samplings);
@@ -469,6 +476,41 @@ static void adc_stm32_calibration_delay(const struct device *dev)
 	}
 }
 
+#if defined(CONFIG_SOC_SERIES_STM32N6X)
+/* Number of ADC measurement during calibration procedure */
+#define ADC_CALIBRATION_STEPS (8U)
+
+static void adc_stm32_calibration_measure(ADC_TypeDef *adc, uint32_t *calibration_factor)
+{
+	uint32_t calib_step;
+	uint32_t calib_factor_avg = 0;
+	uint8_t done = 0;
+
+	do {
+		for (calib_step = 0; calib_step < ADC_CALIBRATION_STEPS; calib_step++) {
+			LL_ADC_REG_StartConversion(adc);
+			while (LL_ADC_REG_IsConversionOngoing(adc) != 0UL) {
+			}
+
+			calib_factor_avg += LL_ADC_REG_ReadConversionData32(adc);
+		}
+
+		/* Compute the average data */
+		calib_factor_avg /= ADC_CALIBRATION_STEPS;
+
+		if ((calib_factor_avg == 0) && (LL_ADC_IsCalibrationOffsetEnabled(adc) == 0UL)) {
+			/* If average is 0 and offset is disabled
+			 * set offset and repeat measurements
+			 */
+			LL_ADC_EnableCalibrationOffset(adc);
+		} else {
+			*calibration_factor = (uint32_t)(calib_factor_avg);
+			done = 1;
+		}
+	} while (done == 0);
+}
+#endif
+
 static void adc_stm32_calibration_start(const struct device *dev)
 {
 	const struct adc_stm32_cfg *config =
@@ -517,6 +559,17 @@ static void adc_stm32_calibration_start(const struct device *dev)
 	LL_ADC_StartCalibration(adc, LL_ADC_CALIB_OFFSET);
 #elif defined(CONFIG_SOC_SERIES_STM32H7X)
 	LL_ADC_StartCalibration(adc, LL_ADC_CALIB_OFFSET, LL_ADC_SINGLE_ENDED);
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+	uint32_t calibration_factor;
+	/* Start ADC calibration */
+	LL_ADC_StartCalibration(adc, LL_ADC_SINGLE_ENDED);
+	/* Disable additional offset before calibration start */
+	LL_ADC_DisableCalibrationOffset(adc);
+
+	adc_stm32_calibration_measure(adc, &calibration_factor);
+
+	LL_ADC_SetCalibrationFactor(adc, LL_ADC_SINGLE_ENDED, calibration_factor);
+	LL_ADC_StopCalibration(adc);
 #endif
 	/* Make sure ADCAL is cleared before returning for proper operations
 	 * on the ADC control register, for enabling the peripheral for example
@@ -551,7 +604,8 @@ static int adc_stm32_calibrate(const struct device *dev)
 #endif /* CONFIG_SOC_SERIES_* */
 #endif /* CONFIG_ADC_STM32_DMA */
 
-#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
+#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \
+	!defined(CONFIG_SOC_SERIES_STM32N6X)
 	adc_stm32_disable(adc);
 	adc_stm32_calibration_start(dev);
 	adc_stm32_calibration_delay(dev);
@@ -562,7 +616,8 @@ static int adc_stm32_calibrate(const struct device *dev)
 		return err;
 	}
 
-#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) || \
+	defined(CONFIG_SOC_SERIES_STM32N6X)
 	adc_stm32_calibration_delay(dev);
 	adc_stm32_calibration_start(dev);
 #endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) */
@@ -868,7 +923,9 @@ static int set_sequencer(const struct device *dev)
 
 #if ANY_ADC_SEQUENCER_TYPE_IS(FULLY_CONFIGURABLE)
 		if (config->sequencer_type == FULLY_CONFIGURABLE) {
-#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32U5X)
+#if defined(CONFIG_SOC_SERIES_STM32H7X) || \
+	defined(CONFIG_SOC_SERIES_STM32N6X) || \
+	defined(CONFIG_SOC_SERIES_STM32U5X)
 			/*
 			 * Each channel in the sequence must be previously enabled in PCSEL.
 			 * This register controls the analog switch integrated in the IO level.
@@ -1021,10 +1078,7 @@ static void adc_context_start_sampling(struct adc_context *ctx)
 		CONTAINER_OF(ctx, struct adc_stm32_data, ctx);
 	const struct device *dev = data->dev;
 	const struct adc_stm32_cfg *config = dev->config;
-	ADC_TypeDef *adc = config->base;
-
-	/* Remove warning for some series */
-	ARG_UNUSED(adc);
+	__maybe_unused ADC_TypeDef *adc = config->base;
 
 	data->repeat_buffer = data->buffer;
 
@@ -1095,7 +1149,7 @@ static void adc_context_on_complete(struct adc_context *ctx, int status)
 	struct adc_stm32_data *data =
 		CONTAINER_OF(ctx, struct adc_stm32_data, ctx);
 	const struct adc_stm32_cfg *config = data->dev->config;
-	ADC_TypeDef *adc = config->base;
+	__maybe_unused ADC_TypeDef *adc = config->base;
 
 	ARG_UNUSED(status);
 
@@ -1106,8 +1160,6 @@ static void adc_context_on_complete(struct adc_context *ctx, int status)
 #if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32U5X)
 	/* Reset channel preselection register */
 	LL_ADC_SetChannelPreselection(adc, 0);
-#else
-	ARG_UNUSED(adc);
 #endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32U5X */
 }
 
@@ -1178,7 +1230,7 @@ static int adc_stm32_sampling_time_setup(const struct device *dev, uint8_t id,
 	const struct adc_stm32_cfg *config =
 		(const struct adc_stm32_cfg *)dev->config;
 	ADC_TypeDef *adc = config->base;
-	struct adc_stm32_data *data = dev->data;
+	__maybe_unused struct adc_stm32_data *data = dev->data;
 
 	int acq_time_index;
 
@@ -1196,7 +1248,6 @@ static int adc_stm32_sampling_time_setup(const struct device *dev, uint8_t id,
 	switch (config->num_sampling_time_common_channels) {
 	case 0:
 #if ANY_NUM_COMMON_SAMPLING_TIME_CHANNELS_IS(0)
-		ARG_UNUSED(data);
 		LL_ADC_SetChannelSamplingTime(adc,
 					      __LL_ADC_DECIMAL_NB_TO_CHANNEL(id),
 					      (uint32_t)acq_time_index);
@@ -1432,11 +1483,9 @@ static int adc_stm32_set_clock(const struct device *dev)
 {
 	const struct adc_stm32_cfg *config = dev->config;
 	const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
-	ADC_TypeDef *adc = config->base;
+	__maybe_unused ADC_TypeDef *adc = config->base;
 	int ret = 0;
 
-	ARG_UNUSED(adc); /* Necessary to avoid warnings on some series */
-
 	if (clock_control_on(clk,
 		(clock_control_subsys_t) &config->pclken[0]) != 0) {
 		return -EIO;
@@ -1451,6 +1500,7 @@ static int adc_stm32_set_clock(const struct device *dev)
 		}
 	}
 
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(st_adc_clock_source)
 #if defined(CONFIG_SOC_SERIES_STM32F0X)
 	LL_ADC_SetClock(adc, config->clk_prescaler);
 #elif defined(ADC_STM32_HAS_INDIVIDUAL_CLOCKS)
@@ -1461,7 +1511,7 @@ static int adc_stm32_set_clock(const struct device *dev)
 				      config->clk_prescaler);
 		LL_ADC_SetClock(adc, LL_ADC_CLOCK_ASYNC);
 	}
-#elif !DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
+#else
 	LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(adc),
 			      config->clk_prescaler);
 
@@ -1470,20 +1520,39 @@ static int adc_stm32_set_clock(const struct device *dev)
 	ret = adc_stm32h7_setup_boost(config, adc, clk);
 #endif
 #endif
+#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(st_adc_clock_source) */
 
 	return ret;
 }
 
+static void adc_stm32_enable_analog_supply(void)
+{
+#if defined(CONFIG_SOC_SERIES_STM32N6X)
+	LL_PWR_EnableVddADC();
+#elif defined(CONFIG_SOC_SERIES_STM32U5X)
+	LL_PWR_EnableVDDA();
+#endif /* CONFIG_SOC_SERIES_STM32U5X */
+}
+
+#ifdef CONFIG_PM_DEVICE
+static void adc_stm32_disable_analog_supply(void)
+{
+#if defined(CONFIG_SOC_SERIES_STM32N6X)
+	LL_PWR_DisableVddADC();
+#elif defined(CONFIG_SOC_SERIES_STM32U5X)
+	LL_PWR_DisableVDDA();
+#endif /* CONFIG_SOC_SERIES_STM32U5X */
+}
+#endif
+
 static int adc_stm32_init(const struct device *dev)
 {
 	struct adc_stm32_data *data = dev->data;
 	const struct adc_stm32_cfg *config = dev->config;
 	const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
-	ADC_TypeDef *adc = config->base;
+	__maybe_unused ADC_TypeDef *adc = config->base;
 	int err;
 
-	ARG_UNUSED(adc); /* Necessary to avoid warnings on some series */
-
 	LOG_DBG("Initializing %s", dev->name);
 
 	if (!device_is_ready(clk)) {
@@ -1519,10 +1588,7 @@ static int adc_stm32_init(const struct device *dev)
 		return err;
 	}
 
-#if defined(CONFIG_SOC_SERIES_STM32U5X)
-	/* Enable the independent analog supply */
-	LL_PWR_EnableVDDA();
-#endif /* CONFIG_SOC_SERIES_STM32U5X */
+	adc_stm32_enable_analog_supply();
 
 #ifdef CONFIG_ADC_STM32_DMA
 	if ((data->dma.dma_dev != NULL) &&
@@ -1539,6 +1605,7 @@ static int adc_stm32_init(const struct device *dev)
 	defined(CONFIG_SOC_SERIES_STM32H5X) || \
 	defined(CONFIG_SOC_SERIES_STM32H7X) || \
 	defined(CONFIG_SOC_SERIES_STM32H7RSX) || \
+	defined(CONFIG_SOC_SERIES_STM32N6X) || \
 	defined(CONFIG_SOC_SERIES_STM32U5X)
 	/*
 	 * L4, WB, G4, H5, H7 and U5 series STM32 needs to be awaken from deep sleep
@@ -1554,7 +1621,8 @@ static int adc_stm32_init(const struct device *dev)
 	 */
 #if !defined(CONFIG_SOC_SERIES_STM32F0X) && \
 	!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \
-	!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
+	!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc) && \
+	!defined(CONFIG_SOC_SERIES_STM32N6X)
 	LL_ADC_EnableInternalRegulator(adc);
 	/* Wait for Internal regulator stabilisation
 	 * Some series have a dedicated status bit, others relie on a delay
@@ -1604,7 +1672,8 @@ static int adc_stm32_suspend_setup(const struct device *dev)
 
 #if !defined(CONFIG_SOC_SERIES_STM32F0X) && \
 	!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc) && \
-	!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc)
+	!DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_adc) && \
+	!defined(CONFIG_SOC_SERIES_STM32N6X)
 	/* Disable ADC internal voltage regulator */
 	LL_ADC_DisableInternalRegulator(adc);
 	while (LL_ADC_IsInternalRegulatorEnabled(adc) == 1U) {
@@ -1618,6 +1687,7 @@ static int adc_stm32_suspend_setup(const struct device *dev)
 	defined(CONFIG_SOC_SERIES_STM32H5X) || \
 	defined(CONFIG_SOC_SERIES_STM32H7X) || \
 	defined(CONFIG_SOC_SERIES_STM32H7RSX) || \
+	defined(CONFIG_SOC_SERIES_STM32N6X) || \
 	defined(CONFIG_SOC_SERIES_STM32U5X)
 	/*
 	 * L4, WB, G4, H5, H7 and U5 series STM32 needs to be put into
@@ -1627,10 +1697,7 @@ static int adc_stm32_suspend_setup(const struct device *dev)
 	LL_ADC_EnableDeepPowerDown(adc);
 #endif
 
-#if defined(CONFIG_SOC_SERIES_STM32U5X)
-	/* Disable the independent analog supply */
-	LL_PWR_DisableVDDA();
-#endif /* CONFIG_SOC_SERIES_STM32U5X */
+	adc_stm32_disable_analog_supply();
 
 	/* Stop device clock. Note: fixed clocks are not handled yet. */
 	err = clock_control_off(clk, (clock_control_subsys_t)&config->pclken[0]);
@@ -1680,6 +1747,9 @@ static DEVICE_API(adc, api_stm32_driver_api) = {
 	.ref_internal = STM32_ADC_VREF_MV, /* VREF is usually connected to VDD */
 };
 
+/* Macros for ADC clock source and prescaler */
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(st_adc_clock_source)
+
 #if defined(CONFIG_SOC_SERIES_STM32F0X)
 /* LL_ADC_CLOCK_ASYNC_DIV1 doesn't exist in F0 LL. Define it here. */
 #define LL_ADC_CLOCK_ASYNC_DIV1 LL_ADC_CLOCK_ASYNC
@@ -1696,17 +1766,20 @@ static DEVICE_API(adc, api_stm32_driver_api) = {
 		(LL_ADC_CLOCK_ASYNC_DIV))
 
 /* Concat prefix (1st element) and DIV value (2nd element) of st,adc-prescaler */
-#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_adc)
-#define ADC_STM32_DT_PRESC(x)	0
-#define ADC_STM32_CHECK_DT_CLOCK(x)
-#else
 #define ADC_STM32_DT_PRESC(x)	\
 	_CONCAT(ADC_STM32_CLOCK_PREFIX(x), ADC_STM32_DIV(x))
+
 /* Macro to check if the ADC instance clock setup is correct */
 #define ADC_STM32_CHECK_DT_CLOCK(x)								\
 	BUILD_ASSERT(IS_EQ(ADC_STM32_CLOCK(x), SYNC) || (DT_INST_NUM_CLOCKS(x) > 1),		\
 		     "ASYNC clock mode defined without ASYNC clock defined in device tree")
-#endif
+
+#else /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(st_adc_clock_source) */
+
+#define ADC_STM32_DT_PRESC(x)	0
+#define ADC_STM32_CHECK_DT_CLOCK(x)
+
+#endif /* !DT_ANY_INST_HAS_PROP_STATUS_OKAY(st_adc_clock_source) */
 
 
 #if defined(CONFIG_ADC_STM32_DMA)
diff --git a/drivers/adc/iadc_gecko.c b/drivers/adc/iadc_gecko.c
index 3e76794d55e..ee8d3804734 100644
--- a/drivers/adc/iadc_gecko.c
+++ b/drivers/adc/iadc_gecko.c
@@ -7,9 +7,12 @@
 #define DT_DRV_COMPAT silabs_gecko_iadc
 
 #include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/clock_control_silabs.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/pm/device.h>
 
 #include <em_iadc.h>
-#include <em_cmu.h>
 
 #define ADC_CONTEXT_USES_KERNEL_TIMER
 #include "adc_context.h"
@@ -43,6 +46,9 @@ struct adc_gecko_data {
 struct adc_gecko_config {
 	IADC_Config_t config;
 	IADC_TypeDef *base;
+	const struct pinctrl_dev_config *pcfg;
+	const struct device *clock_dev;
+	const struct silabs_clock_control_cmu_config clock_cfg;
 	void (*irq_cfg_func)(void);
 };
 
@@ -277,80 +283,6 @@ static int adc_gecko_read_async(const struct device *dev,
 }
 #endif
 
-static void adc_gecko_gpio_busalloc_pos(IADC_PosInput_t input)
-{
-	uint32_t port = ((input << _IADC_SCAN_PINPOS_SHIFT) &
-			_IADC_SCAN_PORTPOS_MASK) >> _IADC_SCAN_PORTPOS_SHIFT;
-	uint32_t pin = ((input << _IADC_SCAN_PINPOS_SHIFT) &
-			_IADC_SCAN_PINPOS_MASK) >> _IADC_SCAN_PINPOS_SHIFT;
-
-	switch (port) {
-	case _IADC_SCAN_PORTPOS_PORTA:
-		if (pin & 1) {
-			GPIO->ABUSALLOC |= GPIO_ABUSALLOC_AODD0_ADC0;
-		} else {
-			GPIO->ABUSALLOC |= GPIO_ABUSALLOC_AEVEN0_ADC0;
-		}
-		break;
-
-	case _IADC_SCAN_PORTPOS_PORTB:
-		if (pin & 1) {
-			GPIO->BBUSALLOC |= GPIO_BBUSALLOC_BODD0_ADC0;
-		} else {
-			GPIO->BBUSALLOC |= GPIO_BBUSALLOC_BEVEN0_ADC0;
-		}
-		break;
-
-	case _IADC_SCAN_PORTPOS_PORTC:
-	case _IADC_SCAN_PORTPOS_PORTD:
-		if (pin & 1) {
-			GPIO->CDBUSALLOC |= GPIO_CDBUSALLOC_CDODD0_ADC0;
-		} else {
-			GPIO->CDBUSALLOC |= GPIO_CDBUSALLOC_CDEVEN0_ADC0;
-		}
-		break;
-
-	default:
-	}
-}
-
-static void adc_gecko_gpio_busalloc_neg(IADC_NegInput_t input)
-{
-	uint32_t port = ((input << _IADC_SCAN_PINNEG_SHIFT) &
-			_IADC_SCAN_PORTNEG_MASK) >> _IADC_SCAN_PORTNEG_SHIFT;
-	uint32_t pin = ((input << _IADC_SCAN_PINNEG_SHIFT) &
-			_IADC_SCAN_PINNEG_MASK) >> _IADC_SCAN_PINNEG_SHIFT;
-
-	switch (port) {
-	case _IADC_SCAN_PORTNEG_PORTA:
-		if (pin & 1) {
-			GPIO->ABUSALLOC |= GPIO_ABUSALLOC_AODD0_ADC0;
-		} else {
-			GPIO->ABUSALLOC |= GPIO_ABUSALLOC_AEVEN0_ADC0;
-		}
-		break;
-
-	case _IADC_SCAN_PORTNEG_PORTB:
-		if (pin & 1) {
-			GPIO->BBUSALLOC |= GPIO_BBUSALLOC_BODD0_ADC0;
-		} else {
-			GPIO->BBUSALLOC |= GPIO_BBUSALLOC_BEVEN0_ADC0;
-		}
-		break;
-
-	case _IADC_SCAN_PORTNEG_PORTC:
-	case _IADC_SCAN_PORTNEG_PORTD:
-		if (pin & 1) {
-			GPIO->CDBUSALLOC |= GPIO_CDBUSALLOC_CDODD0_ADC0;
-		} else {
-			GPIO->CDBUSALLOC |= GPIO_CDBUSALLOC_CDEVEN0_ADC0;
-		}
-		break;
-
-	default:
-	}
-}
-
 static int adc_gecko_channel_setup(const struct device *dev,
 				const struct adc_channel_cfg *channel_cfg)
 {
@@ -424,25 +356,50 @@ static int adc_gecko_channel_setup(const struct device *dev,
 		return -ENOTSUP;
 	}
 
-	/* Setup GPIO xBUSALLOC registers if channel uses GPIO pin */
-	adc_gecko_gpio_busalloc_pos(channel_config->input_positive);
-	adc_gecko_gpio_busalloc_neg(channel_config->input_negative);
-
 	channel_config->initialized = true;
 	LOG_DBG("Channel setup succeeded!");
 
 	return 0;
 }
 
-static int adc_gecko_init(const struct device *dev)
+static int adc_gecko_pm_action(const struct device *dev, enum pm_device_action action)
 {
+	int err;
 	const struct adc_gecko_config *config = dev->config;
-	struct adc_gecko_data *data = dev->data;
 
-	CMU_ClockEnable(cmuClock_IADC0, true);
+	if (action == PM_DEVICE_ACTION_RESUME) {
+		err = clock_control_on(config->clock_dev,
+				       (clock_control_subsys_t)&config->clock_cfg);
+		if (err < 0) {
+			return err;
+		}
 
-	/* Select clock for IADC */
-	CMU_ClockSelectSet(cmuClock_IADCCLK, cmuSelect_FSRCO);  /* FSRCO - 20MHz */
+		err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+		if (err < 0 && err != -ENOENT) {
+			return err;
+		}
+	} else if (IS_ENABLED(CONFIG_PM_DEVICE) && (action == PM_DEVICE_ACTION_SUSPEND)) {
+		err = clock_control_off(config->clock_dev,
+					(clock_control_subsys_t)&config->clock_cfg);
+		if (err < 0) {
+			return err;
+		}
+
+		err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
+		if (err < 0 && err != -ENOENT) {
+			return err;
+		}
+	} else {
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static int adc_gecko_init(const struct device *dev)
+{
+	const struct adc_gecko_config *config = dev->config;
+	struct adc_gecko_data *data = dev->data;
 
 	data->dev = dev;
 
@@ -450,7 +407,7 @@ static int adc_gecko_init(const struct device *dev)
 
 	adc_context_unlock_unconditionally(&data->ctx);
 
-	return 0;
+	return pm_device_driver_init(dev, adc_gecko_pm_action);
 }
 
 static DEVICE_API(adc, api_gecko_adc_driver_api) = {
@@ -463,11 +420,16 @@ static DEVICE_API(adc, api_gecko_adc_driver_api) = {
 };
 
 #define GECKO_IADC_INIT(n)						\
+	PINCTRL_DT_INST_DEFINE(n);					\
+	PM_DEVICE_DT_INST_DEFINE(n, adc_gecko_pm_action);		\
 									\
 	static void adc_gecko_config_func_##n(void);			\
 									\
 	const static struct adc_gecko_config adc_gecko_config_##n = {	\
 		.base = (IADC_TypeDef *)DT_INST_REG_ADDR(n),\
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),		\
+		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),	\
+		.clock_cfg = SILABS_DT_INST_CLOCK_CFG(n),		\
 		.irq_cfg_func = adc_gecko_config_func_##n,		\
 	};								\
 	static struct adc_gecko_data adc_gecko_data_##n = {		\
@@ -483,7 +445,7 @@ static DEVICE_API(adc, api_gecko_adc_driver_api) = {
 		irq_enable(DT_INST_IRQN(n));	\
 	}; \
 	DEVICE_DT_INST_DEFINE(n,					 \
-			      &adc_gecko_init, NULL,			 \
+			      &adc_gecko_init, PM_DEVICE_DT_INST_GET(n), \
 			      &adc_gecko_data_##n, &adc_gecko_config_##n,\
 			      POST_KERNEL, CONFIG_ADC_INIT_PRIORITY,	 \
 			      &api_gecko_adc_driver_api);
diff --git a/drivers/audio/CMakeLists.txt b/drivers/audio/CMakeLists.txt
index 0396ae23e48..9fb0dfe912a 100644
--- a/drivers/audio/CMakeLists.txt
+++ b/drivers/audio/CMakeLists.txt
@@ -2,6 +2,7 @@
 
 zephyr_library()
 
+zephyr_library_sources_ifdef(CONFIG_AUDIO_TLV320AIC3110	tlv320aic3110.c)
 zephyr_library_sources_ifdef(CONFIG_AUDIO_TLV320DAC	tlv320dac310x.c)
 zephyr_library_sources_ifdef(CONFIG_AUDIO_MPXXDTYY	mpxxdtyy.c)
 zephyr_library_sources_ifdef(CONFIG_AUDIO_MPXXDTYY	mpxxdtyy-i2s.c)
@@ -10,3 +11,4 @@ zephyr_library_sources_ifdef(CONFIG_AUDIO_TAS6422DAC tas6422dac.c)
 zephyr_library_sources_ifdef(CONFIG_AUDIO_CODEC_SHELL	codec_shell.c)
 zephyr_library_sources_ifdef(CONFIG_AUDIO_DMIC_MCUX dmic_mcux.c)
 zephyr_library_sources_ifdef(CONFIG_AUDIO_CODEC_WM8904 wm8904.c)
+zephyr_library_sources_ifdef(CONFIG_AUDIO_CODEC_CS43L22 cs43l22.c)
diff --git a/drivers/audio/Kconfig b/drivers/audio/Kconfig
index 70d02b5320a..ffd29112492 100644
--- a/drivers/audio/Kconfig
+++ b/drivers/audio/Kconfig
@@ -35,7 +35,9 @@ module = AUDIO_CODEC
 module-str = audio codec
 source "subsys/logging/Kconfig.template.log_config"
 
+source "drivers/audio/Kconfig.cs43l22"
 source "drivers/audio/Kconfig.tas6422dac"
+source "drivers/audio/Kconfig.tlv320aic3110"
 source "drivers/audio/Kconfig.tlv320dac"
 source "drivers/audio/Kconfig.wm8904"
 
diff --git a/drivers/audio/Kconfig.cs43l22 b/drivers/audio/Kconfig.cs43l22
new file mode 100644
index 00000000000..6fa65a451b9
--- /dev/null
+++ b/drivers/audio/Kconfig.cs43l22
@@ -0,0 +1,12 @@
+# Copyright (c) 2025 Titouan Christophe
+# SPDX-License-Identifier: Apache-2.0
+
+config AUDIO_CODEC_CS43L22
+	bool "Cirrus CS43L22 driver"
+	default y
+	select I2C
+	depends on GPIO
+	depends on DT_HAS_CIRRUS_CS43L22_ENABLED
+	help
+	  Enable the driver for the Cirrus CS43L22 low Power, stereo DAC
+	  with headphone & speaker amplifiers
diff --git a/drivers/audio/Kconfig.tlv320aic3110 b/drivers/audio/Kconfig.tlv320aic3110
new file mode 100644
index 00000000000..3a86b888382
--- /dev/null
+++ b/drivers/audio/Kconfig.tlv320aic3110
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 PHYTEC America LLC
+# SPDX-License-Identifier: Apache-2.0
+
+config AUDIO_TLV320AIC3110
+	bool "TLV320AIC3110 AIC support"
+	default y
+	depends on DT_HAS_TI_TLV320AIC3110_ENABLED
+	select I2C
+	help
+	  Enable TLV320AIC3110 support on the selected board
diff --git a/drivers/audio/codec_shell.c b/drivers/audio/codec_shell.c
index 0fd14bafff2..f63d4c90e53 100644
--- a/drivers/audio/codec_shell.c
+++ b/drivers/audio/codec_shell.c
@@ -39,6 +39,8 @@ static const char *const codec_channel_name[] = {
 	[AUDIO_CHANNEL_REAR_CENTER] = "rear_center",
 	[AUDIO_CHANNEL_SIDE_LEFT] = "side_left",
 	[AUDIO_CHANNEL_SIDE_RIGHT] = "side_right",
+	[AUDIO_CHANNEL_HEADPHONE_LEFT] = "headphone_left",
+	[AUDIO_CHANNEL_HEADPHONE_RIGHT] = "headphone_right",
 	[AUDIO_CHANNEL_ALL] = "all",
 };
 
diff --git a/drivers/audio/cs43l22.c b/drivers/audio/cs43l22.c
new file mode 100644
index 00000000000..0da2af130b4
--- /dev/null
+++ b/drivers/audio/cs43l22.c
@@ -0,0 +1,311 @@
+/*
+ * Copyright (c) 2025 Titouan Christophe
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/audio/codec.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(cirrus_cs43l22);
+
+#define DT_DRV_COMPAT cirrus_cs43l22
+
+/*
+ * See datasheet: https://statics.cirrus.com/pubs/proDatasheet/CS43L22_F2.pdf
+ */
+
+/* (datasheet) 6. REGISTER QUICK REFERENCE */
+#define REG_ID                       0x01
+#define REG_POWER_CTL_1              0x02
+#define REG_POWER_CTL_2              0x04
+#define REG_CLOCKING_CTL             0x05
+#define REG_INTERFACE_CTL_1          0x06
+#define REG_INTERFACE_CTL_2          0x07
+#define REG_PASSTHROUGH_A            0x08
+#define REG_PASSTHROUGH_B            0x09
+#define REG_ANALOG_ZC_AND_SR         0x0a
+#define REG_PASSTHROUGH_GANG_CONTROL 0x0c
+#define REG_PLAYBACK_CTL_1           0x0d
+#define REG_MISC_CTL                 0x0e
+#define REG_PLAYBACK_CTL_2           0x0f
+#define REG_PASSTHROUGH_A_VOL        0x14
+#define REG_PASSTHROUGH_B_VOL        0x15
+#define REG_PCMA_VOL                 0x1a
+#define REG_PCMB_VOL                 0x1b
+#define REG_BEEP_FREQ                0x1c
+#define REG_BEEP_VOL                 0x1d
+#define REG_BEEP_TONE                0x1e
+#define REG_TONE_CTL                 0x1f
+#define REG_MASTER_A_VOL             0x20
+#define REG_MASTER_B_VOL             0x21
+#define REG_HEADPHONES_A_VOL         0x22
+#define REG_HEADPHONES_B_VOL         0x23
+#define REG_SPEAKER_A_VOL            0x22
+#define REG_SPEAKER_B_VOL            0x23
+#define REG_LIMITER_CTL_1            0x27
+#define REG_LIMITER_CTL_2            0x28
+#define REG_STATUS                   0x2e
+#define REG_SPEAKER_STATUS           0x31
+
+/* (datasheet) 7.5.4 DAC Interface Format */
+#define DAC_IF_FORMAT_LEFT_JUSTIFIED  0
+#define DAC_IF_FORMAT_I2S             1
+#define DAC_IF_FORMAT_RIGHT_JUSTIFIED 2
+
+/* (datasheet) 7.5.5 Audio Word Length */
+#define WORDLEN_32       0
+#define WORDLEN_24       1
+#define WORDLEN_20       2
+#define WORDLEN_16       3
+#define WORDLEN_RIGHT_24 0
+#define WORDLEN_RIGHT_20 1
+#define WORDLEN_RIGHT_18 2
+#define WORDLEN_RIGHT_16 3
+
+/* (datasheet) 7.12 Playback Control 2 */
+#define HEADPHONES_B_MUTE (1 << 7)
+#define HEADPHONES_A_MUTE (1 << 6)
+#define SPEAKER_B_MUTE    (1 << 5)
+#define SPEAKER_A_MUTE    (1 << 4)
+
+#define cs43l22_write(_i2c, _reg, _value) \
+	cs43l22_write_masked(_i2c, _reg, _value, 0xff)
+
+static inline int cs43l22_write_masked(const struct i2c_dt_spec *i2c, uint8_t reg,
+				       uint8_t value, uint8_t mask)
+{
+	int ret;
+	uint8_t actual_value = 0;
+
+	if (mask != 0xff) {
+		ret = i2c_burst_read_dt(i2c, reg, &actual_value, 1);
+		if (ret) {
+			LOG_ERR("Unable to get actual register value [%02X]", reg);
+			return ret;
+		}
+	}
+	actual_value = (actual_value & ~mask) | (value & mask);
+
+	return i2c_burst_write_dt(i2c, reg, &actual_value, 1);
+}
+
+#define cs43l22_soft_power_down(_i2c) cs43l22_write(_i2c, REG_POWER_CTL_1, 0x01)
+#define cs43l22_soft_power_up(_i2c)   cs43l22_write(_i2c, REG_POWER_CTL_1, 0x9e)
+
+struct cs43l22_config {
+	struct i2c_dt_spec i2c;
+	struct gpio_dt_spec reset_gpio;
+};
+
+static int cs43l22_configure(const struct device *dev, struct audio_codec_cfg *audiocfg)
+{
+	uint8_t format, wordlen;
+	const struct cs43l22_config *cfg = dev->config;
+
+	if (audiocfg->dai_route != AUDIO_ROUTE_PLAYBACK) {
+		return -ENOTSUP;
+	}
+
+	switch (audiocfg->dai_type) {
+	case AUDIO_DAI_TYPE_LEFT_JUSTIFIED:
+		format = DAC_IF_FORMAT_LEFT_JUSTIFIED;
+		break;
+	case AUDIO_DAI_TYPE_I2S:
+		format = DAC_IF_FORMAT_I2S;
+		break;
+	case AUDIO_DAI_TYPE_RIGHT_JUSTIFIED:
+		format = DAC_IF_FORMAT_RIGHT_JUSTIFIED;
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	if (format == DAC_IF_FORMAT_RIGHT_JUSTIFIED) {
+		switch (audiocfg->dai_cfg.i2s.word_size) {
+		case 16:
+			wordlen = WORDLEN_RIGHT_16;
+			break;
+		case 18:
+			wordlen = WORDLEN_RIGHT_18;
+			break;
+		case 20:
+			wordlen = WORDLEN_RIGHT_20;
+			break;
+		case 24:
+			wordlen = WORDLEN_RIGHT_24;
+			break;
+		default:
+			return -ENOTSUP;
+		}
+	} else {
+		switch (audiocfg->dai_cfg.i2s.word_size) {
+		case 16:
+			wordlen = WORDLEN_16;
+			break;
+		case 20:
+			wordlen = WORDLEN_20;
+			break;
+		case 24:
+			wordlen = WORDLEN_24;
+			break;
+		case 32:
+			wordlen = WORDLEN_32;
+			break;
+		default:
+			return -ENOTSUP;
+		}
+	}
+
+	if (cs43l22_soft_power_down(&cfg->i2c)) {
+		return -EIO;
+	}
+	/* Set automatic clock detection */
+	if (cs43l22_write(&cfg->i2c, REG_CLOCKING_CTL, (1 << 7))) {
+		return -EIO;
+	}
+	/* Set input audio format */
+	if (cs43l22_write_masked(&cfg->i2c, REG_INTERFACE_CTL_1, (format << 2) | wordlen, 0xdf)) {
+		return -EIO;
+	}
+	if (cs43l22_soft_power_up(&cfg->i2c)) {
+		return -EIO;
+	}
+	return 0;
+}
+
+static void cs43l22_start_output(const struct device *dev)
+{
+}
+
+static void cs43l22_stop_output(const struct device *dev)
+{
+}
+
+static int cs43l22_apply_properties(const struct device *dev)
+{
+	return 0;
+}
+
+static inline int cs43l22_set_mute(const struct i2c_dt_spec *i2c,
+				   audio_channel_t channel, bool mute)
+{
+	uint8_t chan_mute_mask = 0;
+
+	switch (channel) {
+	case AUDIO_CHANNEL_ALL:
+		chan_mute_mask = HEADPHONES_A_MUTE
+			       | HEADPHONES_B_MUTE
+			       | SPEAKER_A_MUTE
+			       | SPEAKER_B_MUTE;
+		break;
+	case AUDIO_CHANNEL_HEADPHONE_LEFT:
+		chan_mute_mask = HEADPHONES_A_MUTE;
+		break;
+	case AUDIO_CHANNEL_HEADPHONE_RIGHT:
+		chan_mute_mask = HEADPHONES_B_MUTE;
+		break;
+	case AUDIO_CHANNEL_FRONT_LEFT:
+		chan_mute_mask = SPEAKER_A_MUTE;
+		break;
+	case AUDIO_CHANNEL_FRONT_RIGHT:
+		chan_mute_mask = SPEAKER_B_MUTE;
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	return cs43l22_write_masked(i2c, REG_PLAYBACK_CTL_2,
+				    mute * chan_mute_mask, chan_mute_mask);
+}
+
+static inline int cs43l22_set_volume(const struct i2c_dt_spec *i2c,
+				     audio_channel_t channel, int vol)
+{
+	uint8_t reg;
+	uint8_t volume_scaled = 65 + (191 * vol / 100);
+
+	switch (channel) {
+	case AUDIO_CHANNEL_HEADPHONE_LEFT:
+		reg = REG_HEADPHONES_A_VOL;
+		break;
+	case AUDIO_CHANNEL_HEADPHONE_RIGHT:
+		reg = REG_HEADPHONES_B_VOL;
+		break;
+	case AUDIO_CHANNEL_FRONT_LEFT:
+		reg = REG_SPEAKER_A_VOL;
+		break;
+	case AUDIO_CHANNEL_FRONT_RIGHT:
+		reg = REG_SPEAKER_B_VOL;
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	return cs43l22_write(i2c, reg, volume_scaled);
+}
+
+static int cs43l22_set_property(const struct device *dev, audio_property_t property,
+				audio_channel_t channel, audio_property_value_t val)
+{
+	const struct cs43l22_config *cfg = dev->config;
+
+	switch (property) {
+	case AUDIO_PROPERTY_OUTPUT_MUTE:
+		return cs43l22_set_mute(&cfg->i2c, channel, val.mute);
+	case AUDIO_PROPERTY_OUTPUT_VOLUME:
+		return cs43l22_set_volume(&cfg->i2c, channel, val.vol);
+	default:
+		return -ENOTSUP;
+	}
+
+}
+
+static const struct audio_codec_api cs43l22_api = {
+	.configure = cs43l22_configure,
+	.start_output = cs43l22_start_output,
+	.stop_output = cs43l22_stop_output,
+	.set_property = cs43l22_set_property,
+	.apply_properties = cs43l22_apply_properties,
+};
+
+static int cs43l22_init(const struct device *dev)
+{
+	uint8_t regval;
+	const struct cs43l22_config *cfg = dev->config;
+	int ret;
+
+	ret = gpio_pin_configure_dt(&cfg->reset_gpio, GPIO_OUTPUT_ACTIVE);
+	if (ret) {
+		return -EIO;
+	}
+
+	ret = i2c_burst_read_dt(&cfg->i2c, REG_ID, &regval, 1);
+	if (ret) {
+		LOG_ERR("Unable to read device ID");
+		return -ENODEV;
+	}
+
+	if ((regval >> 3) != 0x1C) {
+		LOG_ERR("Wrong Chip ID");
+		return -ENODEV;
+	}
+
+	LOG_DBG("Found CS43L22 (chip=%02X, rev=%c%d)",
+		regval >> 3, 'A' + ((regval >> 1) & 3), regval & 1);
+
+	return 0;
+}
+
+#define CS43L22_INIT(inst)                                                \
+	static const struct cs43l22_config cs43l22_config_##inst = {      \
+		.i2c = I2C_DT_SPEC_INST_GET(inst),                        \
+		.reset_gpio = GPIO_DT_SPEC_INST_GET(inst, reset_gpios),   \
+	};                                                                \
+	DEVICE_DT_INST_DEFINE(inst, cs43l22_init, NULL, NULL,             \
+			      &cs43l22_config_##inst, POST_KERNEL,        \
+			      CONFIG_AUDIO_CODEC_INIT_PRIORITY,           \
+			      &cs43l22_api);
+
+DT_INST_FOREACH_STATUS_OKAY(CS43L22_INIT)
diff --git a/drivers/audio/mic_privacy/intel/CMakeLists.txt b/drivers/audio/mic_privacy/intel/CMakeLists.txt
new file mode 100644
index 00000000000..63f9d81bec9
--- /dev/null
+++ b/drivers/audio/mic_privacy/intel/CMakeLists.txt
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+zephyr_library_sources_ifdef(CONFIG_INTEL_ADSP_MIC_PRIVACY mic_privacy.c)
diff --git a/drivers/audio/mic_privacy/intel/Kconfig.mic_privacy b/drivers/audio/mic_privacy/intel/Kconfig.mic_privacy
new file mode 100644
index 00000000000..aea9ed7b00d
--- /dev/null
+++ b/drivers/audio/mic_privacy/intel/Kconfig.mic_privacy
@@ -0,0 +1,11 @@
+# SOF Microphone Privacy configuration options
+
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config INTEL_ADSP_MIC_PRIVACY
+	bool "MIC PRIVACY device driver support"
+	default y
+	depends on DT_HAS_INTEL_ADSP_MIC_PRIVACY_ENABLED
+	help
+	  Enable MIC PRIVACY device driver
diff --git a/drivers/audio/mic_privacy/intel/mic_privacy.c b/drivers/audio/mic_privacy/intel/mic_privacy.c
new file mode 100644
index 00000000000..71b4bca2278
--- /dev/null
+++ b/drivers/audio/mic_privacy/intel/mic_privacy.c
@@ -0,0 +1,240 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include "mic_privacy_registers.h"
+#include <zephyr/drivers/mic_privacy/intel/mic_privacy.h>
+#include <zephyr/irq.h>
+#include <zephyr/device.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/pm/device.h>
+
+#define LOG_DOMAIN mic_priv_zephyr
+
+LOG_MODULE_REGISTER(LOG_DOMAIN);
+
+#define DT_DRV_COMPAT intel_adsp_mic_privacy
+
+#define DMICPVC_ADDRESS      (DT_INST_REG_ADDR(0))
+#define DFMICPVCP_ADDRESS    (DMICPVC_ADDRESS)
+#define DFMICPVCS_ADDRESS    (DMICPVC_ADDRESS + 0x0004)
+#define DFFWMICPVCCS_ADDRESS (DMICPVC_ADDRESS + 0x0006)
+
+#define DMICVSSX_ADDRESS     (0x16000)
+#define DMICXLVSCTL_ADDRESS  (DMICVSSX_ADDRESS + 0x0004)
+#define DMICXPVCCS_ADDRESS   (DMICVSSX_ADDRESS + 0x0010)
+
+static inline void ace_mic_priv_intc_unmask(void)
+{
+	ACE_DINT[0].ie[ACE_INTL_MIC_PRIV] = BIT(0);
+}
+
+static inline void ace_dmic_intc_unmask(void)
+{
+	ACE_DINT[0].ie[ACE_INTL_DMIC] = BIT(0);
+}
+
+static void mic_privacy_enable_fw_managed_irq(bool enable_irq, const void *fn)
+{
+	union DFFWMICPVCCS pv_ccs;
+
+	pv_ccs.full = sys_read16(DFFWMICPVCCS_ADDRESS);
+	if (enable_irq) {
+		pv_ccs.part.mdstschgie = 1;
+	} else {
+		pv_ccs.part.mdstschgie = 0;
+	}
+	sys_write16(pv_ccs.full, DFFWMICPVCCS_ADDRESS);
+
+	if (enable_irq && !irq_is_enabled(DT_INST_IRQN(0))) {
+
+		irq_connect_dynamic(DT_INST_IRQN(0), 0,
+			fn,
+			DEVICE_DT_INST_GET(0), 0);
+
+		irq_enable(DT_INST_IRQN(0));
+		ace_mic_priv_intc_unmask();
+	}
+}
+
+static void mic_privacy_clear_fw_managed_irq(void)
+{
+	union DFFWMICPVCCS pv_ccs;
+
+	pv_ccs.full = sys_read16(DFFWMICPVCCS_ADDRESS);
+	pv_ccs.part.mdstschg = 1;
+	sys_write16(pv_ccs.full, DFFWMICPVCCS_ADDRESS);
+}
+
+static void mic_privacy_enable_dmic_irq(bool enable_irq, const void *fn)
+{
+	union DFFWMICPVCCS pv_ccs;
+
+	pv_ccs.full = sys_read16(DMICXPVCCS_ADDRESS);
+	if (enable_irq) {
+		pv_ccs.part.mdstschgie = 1;
+	} else {
+		pv_ccs.part.mdstschgie = 0;
+	}
+	sys_write16(pv_ccs.full, DMICXPVCCS_ADDRESS);
+
+	if (enable_irq) {
+		irq_connect_dynamic(ACE_INTL_DMIC, 0,
+			fn,
+			NULL, 0);
+		irq_enable(ACE_INTL_DMIC);
+		ace_dmic_intc_unmask();
+	} else {
+		irq_disable(ACE_INTL_DMIC);
+	}
+}
+
+static bool mic_privacy_get_dmic_irq_status(void)
+{
+	union DFFWMICPVCCS pv_ccs;
+
+	pv_ccs.full = sys_read16(DMICXPVCCS_ADDRESS);
+	return pv_ccs.part.mdstschg;
+}
+
+static void mic_privacy_clear_dmic_irq_status(void)
+{
+	union DFFWMICPVCCS pv_ccs;
+
+	pv_ccs.full = sys_read16(DMICXPVCCS_ADDRESS);
+	pv_ccs.part.mdstschg = 1;
+	sys_write16(pv_ccs.full, DMICXPVCCS_ADDRESS);
+}
+
+static enum mic_privacy_policy mic_privacy_get_policy(void)
+{
+	union DFMICPVCP micpvcp;
+
+	micpvcp.full = sys_read32(DFMICPVCP_ADDRESS);
+
+	if (micpvcp.part.ddze == 2 && micpvcp.part.ddzpl == 1) {
+		return MIC_PRIVACY_HW_MANAGED;
+	} else if (micpvcp.part.ddze == 2 && micpvcp.part.ddzpl == 0) {
+		return MIC_PRIVACY_FW_MANAGED;
+	} else if (micpvcp.part.ddze == 3) {
+		return MIC_PRIVACY_FORCE_MIC_DISABLED;
+	} else {
+		return MIC_PRIVACY_DISABLED;
+	}
+}
+
+static uint32_t mic_privacy_get_privacy_policy_register_raw_value(void)
+{
+	return sys_read32(DFMICPVCP_ADDRESS);
+}
+
+static uint32_t mic_privacy_get_dma_data_zeroing_wait_time(void)
+{
+	union DFMICPVCP micpvcp;
+
+	micpvcp.full = sys_read32(DFMICPVCP_ADDRESS);
+	return micpvcp.part.ddzwt;
+}
+
+static uint32_t mic_privacy_get_dma_data_zeroing_link_select(void)
+{
+	union DFMICPVCP micpvcp;
+
+	micpvcp.full = sys_read32(DFMICPVCP_ADDRESS);
+	return micpvcp.part.ddzls;
+}
+
+static uint32_t mic_privacy_get_dmic_mic_disable_status(void)
+{
+	union DMICXPVCCS pvccs;
+
+	pvccs.full = sys_read32(DMICXPVCCS_ADDRESS);
+	return pvccs.part.mdsts;
+}
+
+static uint32_t mic_privacy_get_fw_managed_mic_disable_status(void)
+{
+	union DFFWMICPVCCS pv_ccs;
+
+	pv_ccs.full = sys_read16(DFFWMICPVCCS_ADDRESS);
+	return pv_ccs.part.mdsts;
+}
+
+static void mic_privacy_set_fw_managed_mode(bool is_fw_managed_enabled)
+{
+	union DFFWMICPVCCS pv_ccs;
+
+	pv_ccs.full = sys_read16(DFFWMICPVCCS_ADDRESS);
+	if (is_fw_managed_enabled) {
+		pv_ccs.part.fmmd = 1;
+	} else {
+		pv_ccs.part.fmmd = 0;
+	}
+	sys_write16(pv_ccs.full, DFFWMICPVCCS_ADDRESS);
+}
+
+static void mic_privacy_set_fw_mic_disable_status(bool fw_mic_disable_status)
+{
+	union DFFWMICPVCCS pv_ccs;
+
+	pv_ccs.full = sys_read16(DFFWMICPVCCS_ADDRESS);
+	if (fw_mic_disable_status) {
+		pv_ccs.part.fmdsts = 1;
+	} else {
+		pv_ccs.part.fmdsts = 0;
+	}
+	sys_write16(pv_ccs.full, DFFWMICPVCCS_ADDRESS);
+}
+
+static uint32_t mic_privacy_get_fw_mic_disable_status(void)
+{
+	union DFFWMICPVCCS pv_ccs;
+
+	pv_ccs.full = sys_read16(DFFWMICPVCCS_ADDRESS);
+	return pv_ccs.part.fmdsts;
+}
+
+static int intel_adsp_mic_priv_init(const struct device *dev)
+{
+	return 0;
+};
+
+static const struct mic_privacy_api_funcs mic_privacy_ops = {
+	.enable_fw_managed_irq = mic_privacy_enable_fw_managed_irq,
+	.clear_fw_managed_irq = mic_privacy_clear_fw_managed_irq,
+	.enable_dmic_irq = mic_privacy_enable_dmic_irq,
+	.get_dmic_irq_status = mic_privacy_get_dmic_irq_status,
+	.clear_dmic_irq_status = mic_privacy_clear_dmic_irq_status,
+	.get_policy = mic_privacy_get_policy,
+	.get_privacy_policy_register_raw_value = mic_privacy_get_privacy_policy_register_raw_value,
+	.get_dma_data_zeroing_wait_time = mic_privacy_get_dma_data_zeroing_wait_time,
+	.get_dma_data_zeroing_link_select = mic_privacy_get_dma_data_zeroing_link_select,
+	.get_dmic_mic_disable_status = mic_privacy_get_dmic_mic_disable_status,
+	.get_fw_managed_mic_disable_status = mic_privacy_get_fw_managed_mic_disable_status,
+	.set_fw_managed_mode = mic_privacy_set_fw_managed_mode,
+	.set_fw_mic_disable_status = mic_privacy_set_fw_mic_disable_status,
+	.get_fw_mic_disable_status = mic_privacy_get_fw_mic_disable_status
+};
+
+#define INTEL_ADSP_MIC_PRIVACY_INIT(inst)							\
+												\
+	static const struct intel_adsp_mic_priv_cfg intel_adsp_mic_priv##inst##_config = {	\
+		.base = DT_INST_REG_ADDR(inst),							\
+		.regblock_size  = DT_INST_REG_SIZE(inst),					\
+	};											\
+												\
+	static struct intel_adsp_mic_priv_data intel_adsp_mic_priv##inst##_data = {};		\
+												\
+	DEVICE_DT_INST_DEFINE(inst, &intel_adsp_mic_priv_init,					\
+			      NULL,								\
+			      &intel_adsp_mic_priv##inst##_data,				\
+			      &intel_adsp_mic_priv##inst##_config, POST_KERNEL,			\
+			      0,								\
+			      &mic_privacy_ops);						\
+												\
+
+DT_INST_FOREACH_STATUS_OKAY(INTEL_ADSP_MIC_PRIVACY_INIT)
diff --git a/drivers/audio/mic_privacy/intel/mic_privacy_registers.h b/drivers/audio/mic_privacy/intel/mic_privacy_registers.h
new file mode 100644
index 00000000000..360c75004e0
--- /dev/null
+++ b/drivers/audio/mic_privacy/intel/mic_privacy_registers.h
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INTEL_DRIVER_MIC_PRIVACY_REGISTERS_H__
+#define __INTEL_DRIVER_MIC_PRIVACY_REGISTERS_H__
+
+#include <stdint.h>
+#include <zephyr/arch/cpu.h>
+#include <zephyr/arch/common/sys_io.h>
+
+/**
+ * DFMICPVCP
+ * Microphone Privacy Policy
+ *
+ * Offset: 00h
+ * Block: DfMICPVC
+ *
+ * This register controls the microphone privacy DMA data zeroing feature HW policy.
+ */
+union DFMICPVCP {
+	uint32_t full;
+	struct {
+	/**
+	 * DMA Data Zeroing Wait Time
+	 * type: RW/L, rst: 0b, rst domain: PLTRST
+	 *
+	 * Indicates the time-out duration to wait before forcing the actual
+	 * microphone privacy DMA data zeroing. Unit in number of RTC clocks.
+	 * Valid and static when DDZE = 10. For DDZE = 0x or 11 case, time-out
+	 * is not necessary as it will not be enabled or force mic disable statically.
+	 * Locked when DDZPL = 1.
+	 */
+	uint32_t ddzwt : 16;
+	/**
+	 * DMA Data Zeroing Enable
+	 * type: RW/L, rst: 00b, rst domain: PLTRST
+	 *
+	 * Indicates the policy setting for HW to force the microphone privacy DMA data zeroing.
+	 * 0x: Disabled
+	 * 10: Enabled (mic disable dynamically depending on privacy signaling input)
+	 * 11: Enabled (force mic disable statically)
+	 * Locked when DDZPL = 1.
+	 */
+	uint32_t ddze : 2;
+	/**
+	 * De-glitcher Enable
+	 * type: RW/L, rst: 0b, rst domain: PLTRST
+	 *
+	 * De-glitcher enable for privacy signaling GPIO input running on resume clock domain.
+	 * Locked when DDZPL = 1.
+	 */
+	uint32_t dge : 1;
+	/**
+	 * DMA Data Zeroing Policy Lock
+	 * type: RW/L, rst: 0b, rst domain: PLTRST
+	 *
+	 * When set to 1, it locks the privacy DMA data zeroing policy setting.
+	 */
+	uint32_t ddzpl : 1;
+
+	/**
+	 * DMA Data Zeroing Link Select
+	 * type: RW/L, rst: 0b, rst domain: PLTRST
+	 *
+	 * Select 1 or more audio link to apply the microphone privacy DMA data zeroing.
+	 * 1 bit per audio link.
+	 * [6:0]: SoundWire link segment
+	 * [7]: DMIC
+	 * Valid and static when DDZE = 1.
+	 * Locked when DDZPL = 1.
+	 */
+	uint32_t ddzls : 8;
+	/**
+	 * Reserved (Preserved)
+	 * type: RO, rst: 000 0000h, rst domain: nan
+	 *
+	 * SW must preserve the original value when writing.
+	 */
+	uint32_t rsvd31 : 4;
+	} part;
+};
+
+/**
+ * DFMICPVCS
+ * Microphone Privacy Status
+ *
+ * Offset: 04h
+ * Block: DfMICPVC
+ *
+ * This register reports the microphone privacy DMA data zeroing status.
+ */
+union DFMICPVCS {
+	uint16_t full;
+	struct {
+		/**
+		 * Mic Disabled Indicator Output
+		 * type: RO/V, rst: 0b, rst domain: nan
+		 *
+		 * Indicates the mic disabled status output to GPIO (i.e. the privacy
+		 * indicator output).
+		 */
+		uint16_t mdio : 1;
+		/**
+		 * Reserved (Zero)
+		 * type: RO, rst: 0000h, rst domain: nan
+		 *
+		 * SW must use zeros for writes.
+		 */
+		uint16_t rsvd15 : 15;
+	} part;
+};
+
+/**
+ * DFFWMICPVCCS
+ * FW Microphone Privacy Control & Status
+ *
+ * Offset: 06h
+ * Block: DfMICPVC
+ *
+ * This register allows DSP FW to manage the mic privacy operation (if not locked by trusted host).
+ */
+union DFFWMICPVCCS {
+	uint16_t full;
+	struct {
+	/**
+	 * Mic Disable Status Changed Interrupt Enabled
+	 * type: RW, rst: 0b, rst domain: DSPLRST
+	 *
+	 * When set to 1, it allows MDSTSCHG bit to be propagated as mic privacy interrupt
+	 *  to the DSP Cores.
+	 */
+	uint16_t mdstschgie : 1;
+	/**
+	 * FW Managed Mic Disable
+	 * type: RW/L, rst: 0b, rst domain: DSPLRST
+	 *
+	 * When set to 1, it indicates FW will manage its own time-out, decide which related link
+	 * DMA should zero out the data (through DGLISxCS.DDZ), and update the privacy signaling
+	 * output (through FMDSTS).
+	 * HW will NOT control any of the DMIC / SoundWire link level DMA data zeroing or privacy
+	 * signaling output in this case. Locked when DfMICPVCCGP. DDZPL = 1.
+	 */
+	uint16_t fmmd : 1;
+	/**
+	 * FW Mic Disable Status
+	 * type: RW, rst: 0b, rst domain: DSPLRST
+	 *
+	 * When set to 1, it indicates FW has quiesced the mic input stream gracefully and
+	 * instructs HW to set privacy indicator output (no dependency on privacy
+	 * signaling input). Valid if FMMD = 1.
+	 */
+	uint16_t fmdsts : 1;
+	/**
+	 * Reserved (Preserved)
+	 * type: RO, rst: 00h, rst domain: nan
+	 *
+	 * SW must preserve the original value when writing.
+	 */
+	uint16_t rsvd7 : 5;
+	/**
+	 * Mic Disable Status Changed
+	 * type: RW/1C, rst: 0b, rst domain: DSPLRST
+	 *
+	 * Asserted when mic disable status has changed state (independent of MDSTSCHGIE setting),
+	 * and trigger interrupt if enabled.
+	 *
+	 * Note: If MDSTS change again before the current MDSTSCHG is acknowledged by DSP FW,
+	 * the bit will still remain set until cleared by DSP FW.
+	 */
+	uint16_t mdstschg : 1;
+	/**
+	 * Mic Disable Status
+	 * type: RO/V, rst: 0b, rst domain: nan
+	 *
+	 * Indicates the live mic disable status input from GPIO (if FMMD = 1).  When asserted and
+	 * the microphone privacy DMA data zeroing policy is enabled, FW will manage its
+	 * own time-out and decide which related link DMA should zero out the data
+	 * (DGLISxCS.DDZ = 1), followed by setting the mic privacy indicator output (FMDSTS = 1).
+	 * When de-asserted, FW should remove the DMA data zeroing (DGLISxCS.DDZ = 0) and clear
+	 * the privacy indicator output (FMDSTS = 0) as soon as possible.
+	 */
+	uint16_t mdsts : 1;
+	/**
+	 * Reserved (Preserved)
+	 * type: RO, rst: 00h, rst domain: nan
+	 *
+	 * SW must preserve the original value when writing.
+	 */
+	uint16_t rsvd15 : 6;
+	} part;
+};
+
+/**
+ * DMICXPVCCS
+ * Digital Microphone x Privacy Control & Status
+ *
+ * Offset: 10h
+ * Block: DMICVSSX_AON
+ *
+ * This register controls the status reporting structure of the microphone privacy DMA data
+ * zeroing feature.
+ */
+union DMICXPVCCS {
+	uint16_t full;
+	struct {
+		/**
+		 * Mic Disable Status Changed Interrupt Enabled
+		 * type: RW, rst: 0h, rst domain: FLR
+		 *
+		 * When set to 1, it allows MDSTSCHG bit to be propagated as DMIC
+		 * / SoundWire interrupt to the DSP Cores / host CPU.
+		 */
+		uint16_t    mdstschgie : 1;
+		/**
+		 * Reserved
+		 * type: RO, rst: 00h, rst domain: N/A
+		 */
+		uint16_t rsvd7 : 7;
+		/**
+		 * Mic Disable Status Changed
+		 * type: RW/1C, rst: 0h, rst domain: FLR
+		 *
+		 * Asserted when mic disable status has changed state (independent of MDSTSCHGIE
+		 * setting), and trigger interrupt if enabled.
+		 * Note: If MDSTS change again before the current MDSTSCHG is acknowledged by
+		 * DSP FW / host SW, the bit will still remain set until cleared by
+		 * DSP FW / host SW.
+		 */
+		uint16_t mdstschg: 1;
+		/**
+		 * Mic Disable Status
+		 * type: RO/V, rst: 0h, rst domain: N/A
+		 *
+		 * Indicates the live mic disable status input from GPIO
+		 * (for the selected mic audio link per DFMICPVCP.DDZLS).
+		 * When asserted and the microphone privacy DMA data zeroing policy is enabled,
+		 * the timer will start counting and force the selected mic data to zero
+		 * (after time-out). When de-asserted,
+		 * it remove the DMA data zeroing immediately (including stopping the timer
+		 * if it has not expired).
+		 */
+		uint16_t mdsts: 1;
+		/**
+		 * Force Mic Disable
+		 * type: RO/V, rst: 0h, rst domain: N/A
+		 *
+		 * Indicates the microphone endpoint
+		 * (for the selected mic audio link per DFMICPVCP.DDZLS)
+		 * is statically force mic disable by trusted agent and SW / FW should hide
+		 * the endpoint from being exposed to OS.
+		 */
+		uint16_t fmdis: 1;
+		/**
+		 * Reserved
+		 * type: RO, rst: 00h, rst domain: N/A
+		 */
+		uint16_t rsvd15: 5;
+	} part;
+};
+#endif /* __INTEL_DAI_DRIVER_MIC_PRIVACY_REGISTERS_H__ */
diff --git a/drivers/audio/tlv320aic3110.c b/drivers/audio/tlv320aic3110.c
new file mode 100644
index 00000000000..d51cd602e85
--- /dev/null
+++ b/drivers/audio/tlv320aic3110.c
@@ -0,0 +1,582 @@
+/*
+ * Copyright (c) 2025 PHYTEC America LLC
+ * Author: Florijan Plohl <florijan.plohl@norik.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ti_tlv320aic3110
+
+#include <errno.h>
+
+#include <zephyr/sys/util.h>
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/audio/codec.h>
+#include <zephyr/drivers/clock_control.h>
+#include "tlv320aic3110.h"
+
+#define LOG_LEVEL CONFIG_AUDIO_CODEC_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(tlv320aic3110);
+
+#define CODEC_OUTPUT_VOLUME_MAX 0
+#define CODEC_OUTPUT_VOLUME_MIN (-78 * 2)
+
+struct codec_driver_config {
+	struct i2c_dt_spec bus;
+	int clock_source;
+	const struct device *mclk_dev;
+	clock_control_subsys_t mclk_name;
+};
+
+struct codec_driver_data {
+	struct reg_addr reg_addr_cache;
+};
+
+static void codec_write_reg(const struct device *dev, struct reg_addr reg, uint8_t val);
+static void codec_read_reg(const struct device *dev, struct reg_addr reg, uint8_t *val);
+static void codec_update_reg(const struct device *dev, struct reg_addr reg, uint8_t mask,
+			     uint8_t val);
+static void codec_soft_reset(const struct device *dev);
+static int codec_configure_dai(const struct device *dev, audio_dai_cfg_t *cfg);
+static int codec_configure_clocks(const struct device *dev, struct audio_codec_cfg *cfg);
+static int codec_configure_filters(const struct device *dev, audio_dai_cfg_t *cfg);
+static void codec_configure_output(const struct device *dev);
+static void codec_configure_input(const struct device *dev);
+static int codec_set_output_volume(const struct device *dev, audio_channel_t channel, int vol);
+
+#if (LOG_LEVEL >= LOG_LEVEL_DEBUG)
+static void codec_read_all_regs(const struct device *dev);
+#define CODEC_DUMP_REGS(dev) codec_read_all_regs((dev))
+#else
+#define CODEC_DUMP_REGS(dev)
+#endif
+
+static int codec_configure(const struct device *dev, struct audio_codec_cfg *cfg)
+{
+	int ret;
+
+	if (cfg->dai_type != AUDIO_DAI_TYPE_I2S) {
+		LOG_ERR("dai_type must be AUDIO_DAI_TYPE_I2S");
+		return -EINVAL;
+	}
+
+	codec_soft_reset(dev);
+
+	ret = codec_configure_clocks(dev, cfg);
+	if (ret) {
+		LOG_ERR("Failed to configure clocks: %d", ret);
+		return ret;
+	}
+
+	ret = codec_configure_dai(dev, &cfg->dai_cfg);
+	if (ret) {
+		LOG_ERR("Failed to configure DAI: %d", ret);
+		return ret;
+	}
+
+	ret = codec_configure_filters(dev, &cfg->dai_cfg);
+	if (ret) {
+		LOG_ERR("Failed to configure filters: %d", ret);
+		return ret;
+	}
+
+	codec_configure_input(dev);
+	codec_configure_output(dev);
+
+	return ret;
+}
+
+static void codec_start_output(const struct device *dev)
+{
+	/* powerup DAC channels */
+	codec_write_reg(dev, DATA_PATH_SETUP_ADDR, DAC_LR_POWERUP_DEFAULT);
+
+	/* unmute DAC channels */
+	codec_write_reg(dev, VOL_CTRL_ADDR, VOL_CTRL_UNMUTE_DEFAULT);
+
+	CODEC_DUMP_REGS(dev);
+}
+
+static void codec_stop_output(const struct device *dev)
+{
+	/* mute DAC channels */
+	codec_write_reg(dev, VOL_CTRL_ADDR, VOL_CTRL_MUTE_DEFAULT);
+
+	/* powerdown DAC channels */
+	codec_write_reg(dev, DATA_PATH_SETUP_ADDR, DAC_LR_POWERDN_DEFAULT);
+}
+
+static void codec_mute_output(const struct device *dev, audio_channel_t channel, bool mute)
+{
+	/* mute channel */
+	switch (channel) {
+	case AUDIO_CHANNEL_HEADPHONE_LEFT:
+		/**/
+		codec_update_reg(dev, HPL_DRV_GAIN_CTRL_ADDR, HPX_DRV_UNMUTE,
+				 (mute << 2) | HPX_DRV_RESERVED);
+		break;
+
+	case AUDIO_CHANNEL_HEADPHONE_RIGHT:
+		codec_update_reg(dev, HPR_DRV_GAIN_CTRL_ADDR, HPX_DRV_UNMUTE,
+				 (mute << 2) | HPX_DRV_RESERVED);
+		break;
+
+	case AUDIO_CHANNEL_FRONT_LEFT:
+		codec_update_reg(dev, SPL_DRV_GAIN_CTRL_ADDR, SPX_DRV_UNMUTE, mute << 2);
+		break;
+
+	case AUDIO_CHANNEL_FRONT_RIGHT:
+		codec_update_reg(dev, SPR_DRV_GAIN_CTRL_ADDR, SPX_DRV_UNMUTE, mute << 2);
+		break;
+
+	case AUDIO_CHANNEL_ALL:
+		codec_update_reg(dev, HPL_DRV_GAIN_CTRL_ADDR, HPX_DRV_UNMUTE,
+				 (mute << 2) | HPX_DRV_RESERVED);
+		codec_update_reg(dev, HPR_DRV_GAIN_CTRL_ADDR, HPX_DRV_UNMUTE,
+				 (mute << 2) | HPX_DRV_RESERVED);
+		codec_update_reg(dev, SPL_DRV_GAIN_CTRL_ADDR, SPX_DRV_UNMUTE, mute << 2);
+		codec_update_reg(dev, SPR_DRV_GAIN_CTRL_ADDR, SPX_DRV_UNMUTE, mute << 2);
+		break;
+
+	default:
+		LOG_ERR("channel %u invalid.", channel);
+		break;
+	}
+}
+
+static int codec_set_property(const struct device *dev, audio_property_t property,
+			      audio_channel_t channel, audio_property_value_t val)
+{
+	switch (property) {
+	case AUDIO_PROPERTY_OUTPUT_VOLUME:
+		return codec_set_output_volume(dev, channel, val.vol);
+
+	case AUDIO_PROPERTY_OUTPUT_MUTE:
+		codec_mute_output(dev, channel, !val.mute);
+		return 0;
+
+	default:
+		break;
+	}
+
+	return -EINVAL;
+}
+
+static int codec_apply_properties(const struct device *dev)
+{
+	/* nothing to do because there is nothing cached */
+	return 0;
+}
+
+static void codec_write_reg(const struct device *dev, struct reg_addr reg, uint8_t val)
+{
+	struct codec_driver_data *const dev_data = dev->data;
+	const struct codec_driver_config *const dev_cfg = dev->config;
+
+	/* set page if different */
+	if (dev_data->reg_addr_cache.page != reg.page) {
+		i2c_reg_write_byte_dt(&dev_cfg->bus, 0, reg.page);
+		dev_data->reg_addr_cache.page = reg.page;
+	}
+
+	i2c_reg_write_byte_dt(&dev_cfg->bus, reg.reg_addr, val);
+	LOG_DBG("WR PG:%u REG:%02u VAL:0x%02x", reg.page, reg.reg_addr, val);
+}
+
+static void codec_read_reg(const struct device *dev, struct reg_addr reg, uint8_t *val)
+{
+	struct codec_driver_data *const dev_data = dev->data;
+	const struct codec_driver_config *const dev_cfg = dev->config;
+
+	/* set page if different */
+	if (dev_data->reg_addr_cache.page != reg.page) {
+		i2c_reg_write_byte_dt(&dev_cfg->bus, 0, reg.page);
+		dev_data->reg_addr_cache.page = reg.page;
+	}
+
+	i2c_reg_read_byte_dt(&dev_cfg->bus, reg.reg_addr, val);
+	LOG_DBG("RD PG:%u REG:%02u VAL:0x%02x", reg.page, reg.reg_addr, *val);
+}
+
+static void codec_update_reg(const struct device *dev, struct reg_addr reg, uint8_t mask,
+			     uint8_t val)
+{
+	uint8_t reg_val;
+
+	codec_read_reg(dev, reg, &reg_val);
+	reg_val = (reg_val & ~mask) | (val & mask);
+	codec_write_reg(dev, reg, reg_val);
+}
+
+static void codec_soft_reset(const struct device *dev)
+{
+	/* soft reset the AIC */
+	codec_write_reg(dev, SOFT_RESET_ADDR, SOFT_RESET_ASSERT);
+}
+
+static int codec_configure_dai(const struct device *dev, audio_dai_cfg_t *cfg)
+{
+	uint8_t val;
+
+	/* configure I2S interface */
+	val = IF_CTRL_IFTYPE(IF_CTRL_IFTYPE_I2S);
+	if (cfg->i2s.options & I2S_OPT_BIT_CLK_MASTER) {
+		val |= IF_CTRL_BCLK_OUT;
+	}
+
+	if (cfg->i2s.options & I2S_OPT_FRAME_CLK_MASTER) {
+		val |= IF_CTRL_WCLK_OUT;
+	}
+
+	switch (cfg->i2s.word_size) {
+	case AUDIO_PCM_WIDTH_16_BITS:
+		val |= IF_CTRL_WLEN(IF_CTRL_WLEN_16);
+		break;
+	case AUDIO_PCM_WIDTH_20_BITS:
+		val |= IF_CTRL_WLEN(IF_CTRL_WLEN_20);
+		break;
+	case AUDIO_PCM_WIDTH_24_BITS:
+		val |= IF_CTRL_WLEN(IF_CTRL_WLEN_24);
+		break;
+	case AUDIO_PCM_WIDTH_32_BITS:
+		val |= IF_CTRL_WLEN(IF_CTRL_WLEN_32);
+		break;
+	default:
+		LOG_ERR("Unsupported PCM sample bit width %u", cfg->i2s.word_size);
+		return -EINVAL;
+	}
+
+	codec_write_reg(dev, IF_CTRL1_ADDR, val);
+	return 0;
+}
+
+static int codec_configure_clocks(const struct device *dev, struct audio_codec_cfg *cfg)
+{
+	struct i2s_config *i2s;
+	const struct codec_driver_config *const dev_cfg = dev->config;
+	uint32_t rate;
+	int madc, nadc, aosr, mdac, ndac, dosr, bclk_div, mclk_div;
+	int p, r, j, d;
+	int i, ret;
+
+	i2s = &cfg->dai_cfg.i2s;
+
+	/* get MCLK rate */
+	if (dev_cfg->clock_source == 0) {
+		ret = clock_control_get_rate(dev_cfg->mclk_dev, dev_cfg->mclk_name,
+					     &cfg->mclk_freq);
+		if (ret < 0) {
+			LOG_ERR("MCLK clock source freq acquire fail: %d", ret);
+		}
+	}
+
+	LOG_DBG("MCLK %u Hz Sampling Rate: %u Hz", cfg->mclk_freq, i2s->frame_clk_freq);
+
+	/* use pll div table to get all values */
+	rate = i2s->frame_clk_freq;
+	for (i = 0; i < ARRAY_SIZE(pll_div_table); i++) {
+		if (rate == pll_div_table[i].rate && cfg->mclk_freq == pll_div_table[i].mclk) {
+			break;
+		}
+	}
+
+	if (i == ARRAY_SIZE(pll_div_table)) {
+		LOG_ERR("Unable to find PLL dividers for MCLK %u Hz PCM Rate: %u Hz",
+			cfg->mclk_freq, i2s->frame_clk_freq);
+		return -EINVAL;
+	}
+
+	p = pll_div_table[i].pll_p;
+	r = 1;
+	j = pll_div_table[i].pll_j;
+	d = pll_div_table[i].pll_d;
+
+	/* set the dividers */
+	codec_write_reg(dev, PLL_P_R_ADDR, (1 << 7) | PLL_P(p) | PLL_R(r));
+	codec_write_reg(dev, PLL_J_ADDR, j);
+	codec_write_reg(dev, PLL_D_MSB_ADDR, (uint8_t)(d >> 8));
+	codec_write_reg(dev, PLL_D_LSB_ADDR, (uint8_t)(d & 0xFF));
+
+	madc = pll_div_table[i].madc;
+	nadc = pll_div_table[i].nadc;
+	aosr = pll_div_table[i].aosr;
+
+	ndac = pll_div_table[i].ndac;
+	mdac = pll_div_table[i].mdac;
+	dosr = pll_div_table[i].dosr;
+
+	LOG_DBG("PLLP: %u PLLJ: %u PLLD: %u", pll_div_table[i].pll_p, pll_div_table[i].pll_j,
+		pll_div_table[i].pll_d);
+	LOG_DBG("MDAC: %u NDAC: %u DOSR: %u", mdac, ndac, dosr);
+	LOG_DBG("MADC: %u NADC: %u AOSR: %u", madc, nadc, aosr);
+
+	if (i2s->options & I2S_OPT_BIT_CLK_MASTER) {
+		bclk_div = dosr * mdac / (i2s->word_size * 2U); /* stereo */
+		if ((bclk_div * i2s->word_size * 2) != (dosr * mdac)) {
+			LOG_ERR("Unable to generate BCLK %u from MCLK %u",
+				i2s->frame_clk_freq * i2s->word_size * 2U, cfg->mclk_freq);
+			return -EINVAL;
+		}
+		LOG_DBG("I2S Master BCLKDIV: %u", bclk_div);
+		codec_write_reg(dev, BCLK_DIV_ADDR, BCLK_DIV_POWER_UP | BCLK_DIV(bclk_div));
+	}
+
+	/* Set clock gen mux and turn on PLL */
+	codec_write_reg(dev, CLOCK_GEN_MUX_ADDR, CLOCK_GEN_MUX_DEFAULT);
+	codec_update_reg(dev, PLL_P_R_ADDR, PLL_POWER_UP, PLL_POWER_UP);
+
+	/* set NDAC, then MDAC, followed by OSR */
+	codec_write_reg(dev, NDAC_DIV_ADDR, (uint8_t)(NDAC_DIV(ndac) | NDAC_POWER_UP_MASK));
+	codec_write_reg(dev, MDAC_DIV_ADDR, (uint8_t)(MDAC_DIV(mdac) | MDAC_POWER_UP_MASK));
+	codec_write_reg(dev, OSR_MSB_ADDR, (uint8_t)((dosr >> 8) & OSR_MSB_MASK));
+	codec_write_reg(dev, OSR_LSB_ADDR, (uint8_t)(dosr & OSR_LSB_MASK));
+
+	/* set NADC, MADC, OSR */
+	codec_write_reg(dev, NADC_DIV_ADDR, (uint8_t)(NADC_DIV(nadc) | NADC_POWER_UP_MASK));
+	codec_write_reg(dev, MADC_DIV_ADDR, (uint8_t)(MADC_DIV(madc) | MADC_POWER_UP_MASK));
+	codec_write_reg(dev, AOSR_ADDR, (uint8_t)aosr);
+
+	if (i2s->options & I2S_OPT_BIT_CLK_MASTER) {
+		codec_write_reg(dev, BCLK_DIV_ADDR, BCLK_DIV(bclk_div) | BCLK_DIV_POWER_UP);
+	}
+
+	/* calculate MCLK divider to get ~1MHz */
+	mclk_div = DIV_ROUND_UP(cfg->mclk_freq, 1000000);
+	/* setup timer clock to be MCLK divided */
+	codec_write_reg(dev, TIMER_MCLK_DIV_ADDR,
+			TIMER_MCLK_DIV_EN_EXT | TIMER_MCLK_DIV_VAL(mclk_div));
+	LOG_DBG("Timer MCLK Divider: %u", mclk_div);
+
+	return 0;
+}
+
+static int codec_configure_filters(const struct device *dev, audio_dai_cfg_t *cfg)
+{
+	enum dac_proc_block dac_proc_blk;
+	enum adc_proc_block adc_proc_blk;
+
+	/* determine decimation filter type */
+	if (cfg->i2s.frame_clk_freq >= AUDIO_PCM_RATE_192K) {
+		dac_proc_blk = PRB_P17_DECIMATION_C;
+		adc_proc_blk = PRB_R16_DECIMATION_C;
+		LOG_INF("PCM Rate: %u Filter C PRB P17/R16 selected", cfg->i2s.frame_clk_freq);
+	} else if (cfg->i2s.frame_clk_freq >= AUDIO_PCM_RATE_96K) {
+		dac_proc_blk = PRB_P7_DECIMATION_B;
+		adc_proc_blk = PRB_R10_DECIMATION_B;
+		LOG_INF("PCM Rate: %u Filter B PRB P7/R10 selected", cfg->i2s.frame_clk_freq);
+	} else {
+		dac_proc_blk = PRB_P1_DECIMATION_A;
+		adc_proc_blk = PRB_R4_DECIMATION_A;
+		LOG_INF("PCM Rate: %u Filter A PRB P1/R4 selected", cfg->i2s.frame_clk_freq);
+	}
+
+	codec_write_reg(dev, DAC_PROC_BLK_SEL_ADDR, dac_proc_blk);
+	codec_write_reg(dev, ADC_PROC_BLK_SEL_ADDR, adc_proc_blk);
+	return 0;
+}
+
+static void codec_configure_output(const struct device *dev)
+{
+	uint8_t val;
+
+	/*
+	 * set common mode voltage to 1.65V (half of AVDD)
+	 * AVDD is typically 3.3V
+	 */
+	codec_read_reg(dev, HEADPHONE_DRV_ADDR, &val);
+	val &= ~HEADPHONE_DRV_CM_MASK;
+	val |= HEADPHONE_DRV_CM(CM_VOLTAGE_1P65) | HEADPHONE_DRV_RESERVED;
+	codec_write_reg(dev, HEADPHONE_DRV_ADDR, val);
+
+	/* enable pop removal on power down/up */
+	codec_read_reg(dev, HP_OUT_POP_RM_ADDR, &val);
+	codec_write_reg(dev, HP_OUT_POP_RM_ADDR, val | HP_OUT_POP_RM_ENABLE);
+
+	/* route DAC output to mixer */
+	val = OUTPUT_ROUTING_MIXER;
+	codec_write_reg(dev, OUTPUT_ROUTING_ADDR, val);
+
+	/* enable volume control on Headphone out and Speaker out */
+	codec_write_reg(dev, HPL_ANA_VOL_CTRL_ADDR, HPX_ANA_VOL(HPX_ANA_VOL_DEFAULT));
+	codec_write_reg(dev, HPR_ANA_VOL_CTRL_ADDR, HPX_ANA_VOL(HPX_ANA_VOL_DEFAULT));
+	codec_write_reg(dev, SPL_ANA_VOL_CTRL_ADDR, SPX_ANA_VOL(SPX_ANA_VOL_DEFAULT));
+	codec_write_reg(dev, SPR_ANA_VOL_CTRL_ADDR, SPX_ANA_VOL(SPX_ANA_VOL_DEFAULT));
+
+	/* unmute headphone and speaker drivers */
+	codec_write_reg(dev, HPL_DRV_GAIN_CTRL_ADDR, HPX_DRV_UNMUTE | HPX_DRV_RESERVED);
+	codec_write_reg(dev, HPR_DRV_GAIN_CTRL_ADDR, HPX_DRV_UNMUTE | HPX_DRV_RESERVED);
+	codec_write_reg(dev, SPL_DRV_GAIN_CTRL_ADDR, SPX_DRV_UNMUTE);
+	codec_write_reg(dev, SPR_DRV_GAIN_CTRL_ADDR, SPX_DRV_UNMUTE);
+
+	/* power up headphone drivers */
+	codec_read_reg(dev, HEADPHONE_DRV_ADDR, &val);
+	val |= HEADPHONE_DRV_POWERUP | HEADPHONE_DRV_RESERVED;
+	codec_write_reg(dev, HEADPHONE_DRV_ADDR, val);
+
+	/* power up speaker drivers */
+	codec_read_reg(dev, SPEAKER_DRV_ADDR, &val);
+	val |= SPEAKER_DRV_POWERUP | SPEAKER_DRV_RESERVED;
+	codec_write_reg(dev, SPEAKER_DRV_ADDR, val);
+	LOG_INF("Headphone driver and Class-D amplifier powered up");
+}
+
+static void codec_configure_input(const struct device *dev)
+{
+	uint8_t val;
+
+	/* power up ADC channel */
+	codec_write_reg(dev, MIC_ADC_CTRL_ADDR, MIC_ADC_POWERUP);
+
+	/* set microphone bias - THIS SHOULD BE FIXED*/
+	codec_write_reg(dev, MIC_BIAS_ADDR, MICBIAS_DEFAULT);
+
+	/* unmute microphone input */
+	codec_write_reg(dev, MIC_FCTRL_ADDR, MIC_FCTRL_DEFAULT);
+
+	/* set PGA, D7 enables PGA control, D6-D0 sets volume */
+	codec_write_reg(dev, MIC_PGA_ADDR, MIC_PGA_VOL_DEFAULT);
+
+	/* select both MIC inputs for PGA and their resistance */
+	val = MIC_PGAPI_L_DEFAULT | MIC_PGAPI_R_DEFAULT;
+	codec_write_reg(dev, MIC_PGAPI_ADDR, val);
+	LOG_INF("Microphone bias and PGA configured");
+}
+
+static int codec_set_output_volume(const struct device *dev, audio_channel_t channel, int vol)
+{
+	struct reg_addr reg;
+	uint8_t vol_val;
+	int vol_index;
+	uint8_t vol_array[] = {107, 108, 110, 113, 116, 120, 125, 128, 132, 138, 144};
+
+	if ((vol > CODEC_OUTPUT_VOLUME_MAX) || (vol < CODEC_OUTPUT_VOLUME_MIN)) {
+		LOG_ERR("Invalid volume %d.%d dB", vol >> 1, ((uint32_t)vol & 1) ? 5 : 0);
+		return -EINVAL;
+	}
+
+	/* remove sign */
+	vol = -vol;
+
+	/* if volume is near floor, set minimum */
+	if (vol > HPX_ANA_VOL_FLOOR) {
+		vol_val = HPX_ANA_VOL_FLOOR;
+	} else if (vol > HPX_ANA_VOL_LOW_THRESH) {
+		/* lookup low volume values */
+		for (vol_index = 0; vol_index < ARRAY_SIZE(vol_array); vol_index++) {
+			if (vol_array[vol_index] >= vol) {
+				break;
+			}
+		}
+		vol_val = HPX_ANA_VOL_LOW_THRESH + vol_index + 1;
+	} else {
+		vol_val = (uint8_t)vol;
+	}
+	LOG_INF("Writing value to %u channel: %u", channel, vol_val);
+
+	switch (channel) {
+	case AUDIO_CHANNEL_HEADPHONE_LEFT:
+		reg = HPL_ANA_VOL_CTRL_ADDR;
+		break;
+
+	case AUDIO_CHANNEL_HEADPHONE_RIGHT:
+		reg = HPR_ANA_VOL_CTRL_ADDR;
+		break;
+
+	case AUDIO_CHANNEL_FRONT_LEFT:
+		reg = SPL_ANA_VOL_CTRL_ADDR;
+		break;
+
+	case AUDIO_CHANNEL_FRONT_RIGHT:
+		reg = SPR_ANA_VOL_CTRL_ADDR;
+		break;
+
+	case AUDIO_CHANNEL_ALL:
+		codec_write_reg(dev, HPL_ANA_VOL_CTRL_ADDR, HPX_ANA_VOL(vol_val));
+		codec_write_reg(dev, HPR_ANA_VOL_CTRL_ADDR, HPX_ANA_VOL(vol_val));
+		codec_write_reg(dev, SPL_ANA_VOL_CTRL_ADDR, SPX_ANA_VOL(vol_val));
+		codec_write_reg(dev, SPR_ANA_VOL_CTRL_ADDR, SPX_ANA_VOL(vol_val));
+		return 0;
+
+	default:
+		LOG_ERR("channel %u invalid.", channel);
+		return -EINVAL;
+	}
+
+	codec_write_reg(dev, reg, HPX_ANA_VOL(vol_val));
+	return 0;
+}
+
+#if (LOG_LEVEL >= LOG_LEVEL_DEBUG)
+static void codec_read_all_regs(const struct device *dev)
+{
+	uint8_t val;
+
+	codec_read_reg(dev, SOFT_RESET_ADDR, &val);
+	codec_read_reg(dev, PLL_P_R_ADDR, &val);
+	codec_read_reg(dev, PLL_J_ADDR, &val);
+	codec_read_reg(dev, PLL_D_MSB_ADDR, &val);
+	codec_read_reg(dev, PLL_D_LSB_ADDR, &val);
+	codec_read_reg(dev, NDAC_DIV_ADDR, &val);
+	codec_read_reg(dev, MDAC_DIV_ADDR, &val);
+	codec_read_reg(dev, OSR_MSB_ADDR, &val);
+	codec_read_reg(dev, OSR_LSB_ADDR, &val);
+	codec_read_reg(dev, NADC_DIV_ADDR, &val);
+	codec_read_reg(dev, MADC_DIV_ADDR, &val);
+	codec_read_reg(dev, AOSR_ADDR, &val);
+	codec_read_reg(dev, IF_CTRL1_ADDR, &val);
+	codec_read_reg(dev, BCLK_DIV_ADDR, &val);
+	codec_read_reg(dev, OVF_FLAG_ADDR, &val);
+	codec_read_reg(dev, DAC_PROC_BLK_SEL_ADDR, &val);
+	codec_read_reg(dev, ADC_PROC_BLK_SEL_ADDR, &val);
+	codec_read_reg(dev, DATA_PATH_SETUP_ADDR, &val);
+	codec_read_reg(dev, VOL_CTRL_ADDR, &val);
+	codec_read_reg(dev, L_DIG_VOL_CTRL_ADDR, &val);
+
+	codec_read_reg(dev, MIC_PGA_ADDR, &val);
+
+	codec_read_reg(dev, DRC_CTRL1_ADDR, &val);
+	codec_read_reg(dev, L_BEEP_GEN_ADDR, &val);
+	codec_read_reg(dev, R_BEEP_GEN_ADDR, &val);
+	codec_read_reg(dev, BEEP_LEN_MSB_ADDR, &val);
+	codec_read_reg(dev, BEEP_LEN_MIB_ADDR, &val);
+	codec_read_reg(dev, BEEP_LEN_LSB_ADDR, &val);
+
+	codec_read_reg(dev, HEADPHONE_DRV_ADDR, &val);
+	codec_read_reg(dev, HP_OUT_POP_RM_ADDR, &val);
+	codec_read_reg(dev, OUTPUT_ROUTING_ADDR, &val);
+	codec_read_reg(dev, HPL_ANA_VOL_CTRL_ADDR, &val);
+	codec_read_reg(dev, HPR_ANA_VOL_CTRL_ADDR, &val);
+	codec_read_reg(dev, HPL_DRV_GAIN_CTRL_ADDR, &val);
+	codec_read_reg(dev, HPR_DRV_GAIN_CTRL_ADDR, &val);
+	codec_read_reg(dev, HEADPHONE_DRV_CTRL_ADDR, &val);
+
+	codec_read_reg(dev, SPL_DRV_GAIN_CTRL_ADDR, &val);
+	codec_read_reg(dev, SPR_DRV_GAIN_CTRL_ADDR, &val);
+
+	codec_read_reg(dev, TIMER_MCLK_DIV_ADDR, &val);
+}
+#endif
+
+static const struct audio_codec_api codec_driver_api = {
+	.configure = codec_configure,
+	.start_output = codec_start_output,
+	.stop_output = codec_stop_output,
+	.set_property = codec_set_property,
+	.apply_properties = codec_apply_properties,
+};
+
+#define TLV320AIC3110_INIT(n)                                                                      \
+	static const struct codec_driver_config codec_device_config_##n = {                        \
+		.bus = I2C_DT_SPEC_INST_GET(n),                                                    \
+		.clock_source = 0,                                                                 \
+		.mclk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_NAME(n, mclk)),                   \
+		.mclk_name = (clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, name)};  \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, NULL, NULL, NULL, &codec_device_config_##n, POST_KERNEL,          \
+			      CONFIG_AUDIO_CODEC_INIT_PRIORITY, &codec_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(TLV320AIC3110_INIT)
diff --git a/drivers/audio/tlv320aic3110.h b/drivers/audio/tlv320aic3110.h
new file mode 100644
index 00000000000..3f34605150f
--- /dev/null
+++ b/drivers/audio/tlv320aic3110.h
@@ -0,0 +1,300 @@
+/*
+ * Copyright (c) 2025 PHYTEC America LLC
+ * Author: Florijan Plohl <florijan.plohl@norik.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_AUDIO_TLV320DAC310X_H_
+#define ZEPHYR_DRIVERS_AUDIO_TLV320DAC310X_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Register addresses */
+#define PAGE_CONTROL_ADDR	0
+
+/* Register addresses {page, address} and fields */
+#define SOFT_RESET_ADDR		(struct reg_addr){0, 1}
+#define SOFT_RESET_ASSERT	(1)
+
+#define CLOCK_GEN_MUX_ADDR	(struct reg_addr){0, 4}
+#define CLOCK_GEN_MUX_DEFAULT	(0x3)
+
+#define PLL_P_R_ADDR		(struct reg_addr){0, 5}
+#define PLL_POWER_UP		BIT(7)
+#define PLL_POWER_UP_MASK	BIT(7)
+#define PLL_P_MASK		BIT_MASK(3)
+#define PLL_P(val)		(((val) & PLL_P_MASK) << 4)
+#define PLL_R_MASK		BIT_MASK(4)
+#define PLL_R(val)		((val) & PLL_R_MASK)
+
+#define PLL_J_ADDR		(struct reg_addr){0, 6}
+
+#define PLL_D_MSB_ADDR		(struct reg_addr){0, 7}
+#define PLL_D_LSB_ADDR		(struct reg_addr){0, 8}
+
+#define NDAC_DIV_ADDR		(struct reg_addr){0, 11}
+#define NDAC_POWER_UP		BIT(7)
+#define NDAC_POWER_UP_MASK	BIT(7)
+#define NDAC_DIV_MASK		BIT_MASK(7)
+#define NDAC_DIV(val)		((val) & NDAC_DIV_MASK)
+
+#define MDAC_DIV_ADDR		(struct reg_addr){0, 12}
+#define MDAC_POWER_UP		BIT(7)
+#define MDAC_POWER_UP_MASK	BIT(7)
+#define MDAC_DIV_MASK		BIT_MASK(7)
+#define MDAC_DIV(val)		((val) & MDAC_DIV_MASK)
+
+#define OSR_MSB_ADDR		(struct reg_addr){0, 13}
+#define OSR_MSB_MASK		BIT_MASK(2)
+
+#define OSR_LSB_ADDR		(struct reg_addr){0, 14}
+#define OSR_LSB_MASK		BIT_MASK(8)
+
+#define NADC_DIV_ADDR		(struct reg_addr){0, 18}
+#define NADC_POWER_UP		BIT(7)
+#define NADC_POWER_UP_MASK	BIT(7)
+#define NADC_DIV_MASK		BIT_MASK(7)
+#define NADC_DIV(val)		((val) & NADC_DIV_MASK)
+
+#define MADC_DIV_ADDR		(struct reg_addr){0, 19}
+#define MADC_POWER_UP		BIT(7)
+#define MADC_POWER_UP_MASK	BIT(7)
+#define MADC_DIV_MASK		BIT_MASK(7)
+#define MADC_DIV(val)		((val) & MADC_DIV_MASK)
+
+#define AOSR_ADDR		(struct reg_addr){0, 20}
+
+#define IF_CTRL1_ADDR		(struct reg_addr){0, 27}
+#define IF_CTRL_IFTYPE_MASK	BIT_MASK(1)
+#define IF_CTRL_IFTYPE_I2S	0
+#define IF_CTRL_IFTYPE_DSP	1
+#define IF_CTRL_IFTYPE_RJF	2
+#define IF_CTRL_IFTYPE_LJF	3
+#define IF_CTRL_IFTYPE(val)	(((val) & IF_CTRL_IFTYPE_MASK) << 6)
+#define IF_CTRL_WLEN_MASK	BIT_MASK(2)
+#define IF_CTRL_WLEN(val)	(((val) & IF_CTRL_WLEN_MASK) << 4)
+#define IF_CTRL_WLEN_16		0
+#define IF_CTRL_WLEN_20		1
+#define IF_CTRL_WLEN_24		2
+#define IF_CTRL_WLEN_32		3
+#define IF_CTRL_BCLK_OUT	BIT(3)
+#define IF_CTRL_WCLK_OUT	BIT(2)
+#define IF_CTRL_DOUT_HIGH_Z	BIT(0)
+
+#define BCLK_DIV_ADDR		(struct reg_addr){0, 30}
+#define BCLK_DIV_POWER_UP	BIT(7)
+#define BCLK_DIV_POWER_UP_MASK	BIT(7)
+#define BCLK_DIV_MASK		BIT_MASK(7)
+#define BCLK_DIV(val)		((val) & MDAC_DIV_MASK)
+
+#define OVF_FLAG_ADDR		(struct reg_addr){0, 39}
+
+#define DAC_PROC_BLK_SEL_ADDR	(struct reg_addr){0, 60}
+#define	DAC_PROC_BLK_SEL_MASK	BIT_MASK(5)
+#define	DAC_PROC_BLK_SEL(val)	((val) & DAC_PROC_BLK_SEL_MASK)
+
+#define ADC_PROC_BLK_SEL_ADDR	(struct reg_addr){0, 61}
+#define	ADC_PROC_BLK_SEL_MASK	BIT_MASK(5)
+#define	ADC_PROC_BLK_SEL(val)	((val) & ADC_PROC_BLK_SEL_MASK)
+
+#define DATA_PATH_SETUP_ADDR	(struct reg_addr){0, 63}
+#define DAC_LR_POWERUP_DEFAULT	(BIT(7) | BIT(6) | BIT(4) | BIT(2))
+#define DAC_LR_POWERDN_DEFAULT	(BIT(4) | BIT(2))
+
+#define VOL_CTRL_ADDR		(struct reg_addr){0, 64}
+#define VOL_CTRL_UNMUTE_DEFAULT	(0)
+#define VOL_CTRL_MUTE_DEFAULT	(BIT(3) | BIT(2))
+
+#define L_DIG_VOL_CTRL_ADDR	(struct reg_addr){0, 65}
+#define DRC_CTRL1_ADDR		(struct reg_addr){0, 68}
+#define L_BEEP_GEN_ADDR		(struct reg_addr){0, 71}
+#define BEEP_GEN_EN_BEEP	(BIT(7))
+#define R_BEEP_GEN_ADDR		(struct reg_addr){0, 72}
+#define BEEP_LEN_MSB_ADDR	(struct reg_addr){0, 73}
+#define BEEP_LEN_MIB_ADDR	(struct reg_addr){0, 74}
+#define BEEP_LEN_LSB_ADDR	(struct reg_addr){0, 75}
+
+/* Page 1 registers */
+/* Headphone driver registers */
+#define HEADPHONE_DRV_ADDR	(struct reg_addr){1, 31}
+#define HEADPHONE_DRV_POWERUP	(BIT(7) | BIT(6))
+#define HEADPHONE_DRV_CM_MASK	(BIT_MASK(2) << 3)
+#define HEADPHONE_DRV_CM(val)	(((val) << 3) & HEADPHONE_DRV_CM_MASK)
+#define HEADPHONE_DRV_RESERVED	(BIT(2))
+
+#define HP_OUT_POP_RM_ADDR	(struct reg_addr){1, 33}
+#define HP_OUT_POP_RM_ENABLE	(BIT(7))
+
+#define OUTPUT_ROUTING_ADDR	(struct reg_addr){1, 35}
+#define OUTPUT_ROUTING_HPL	BIT(7)
+#define OUTPUT_ROUTING_HPR	BIT(3)
+
+#define HPL_ANA_VOL_CTRL_ADDR	(struct reg_addr){1, 36}
+#define HPR_ANA_VOL_CTRL_ADDR	(struct reg_addr){1, 37}
+#define HPX_ANA_VOL_ENABLE	BIT(7)
+#define HPX_ANA_VOL_MASK	BIT_MASK(7)
+#define HPX_ANA_VOL(val)	(((val) & HPX_ANA_VOL_MASK) |	\
+		HPX_ANA_VOL_ENABLE)
+#define HPX_ANA_VOL_MAX		(0)
+#define HPX_ANA_VOL_DEFAULT	(0)
+#define HPX_ANA_VOL_MIN		(127)
+#define HPX_ANA_VOL_MUTE	(HPX_ANA_VOL_MIN | ~HPX_ANA_VOL_ENABLE)
+#define HPX_ANA_VOL_LOW_THRESH	(105)
+#define HPX_ANA_VOL_FLOOR	(144)
+
+#define HPL_DRV_GAIN_CTRL_ADDR	(struct reg_addr){1, 40}
+#define HPR_DRV_GAIN_CTRL_ADDR	(struct reg_addr){1, 41}
+#define	HPX_DRV_UNMUTE		(BIT(2))
+#define HPX_DRV_RESERVED	(BIT(1)) /* Write only 1 */
+
+#define HEADPHONE_DRV_CTRL_ADDR	(struct reg_addr){1, 44}
+#define HEADPHONE_DRV_LINEOUT	(BIT(1) | BIT(2))
+
+/* Class-D speaker amplifier registers */
+#define SPEAKER_DRV_ADDR	(struct reg_addr){1, 32}
+#define SPEAKER_DRV_POWERUP	BIT(7) | BIT(6)
+#define SPEAKER_DRV_RESERVED	BIT(2) | BIT(1)
+
+#define OUTPUT_ROUTING_MIXER	BIT(6) | BIT(2)
+
+#define SPL_ANA_VOL_CTRL_ADDR	(struct reg_addr){1, 38}
+#define SPR_ANA_VOL_CTRL_ADDR	(struct reg_addr){1, 39}
+#define SPX_ANA_VOL_ENABLE	BIT(7)
+#define SPX_ANA_VOL_MASK	(BIT_MASK(7))
+#define SPX_ANA_VOL(val)	(((val) & SPX_ANA_VOL_MASK) |	\
+		SPX_ANA_VOL_ENABLE)
+#define SPX_ANA_VOL_MAX		(0)
+#define SPX_ANA_VOL_DEFAULT	(0)
+#define SPX_ANA_VOL_MIN		(127)
+#define SPX_ANA_VOL_MUTE	(SPX_ANA_VOL_MIN | ~SPX_ANA_VOL_ENABLE)
+#define SPX_ANA_VOL_LOW_THRESH	(105)
+#define SPX_ANA_VOL_FLOOR	(144)
+
+#define SPL_DRV_GAIN_CTRL_ADDR	(struct reg_addr){1, 42}
+#define SPR_DRV_GAIN_CTRL_ADDR	(struct reg_addr){1, 43}
+#define	SPX_DRV_UNMUTE		(BIT(2))
+#define	SPX_DRV_RESERVED	(BIT(1)) /* Write only 0 */
+
+/* ADC Mic registers */
+#define MIC_ADC_CTRL_ADDR	(struct reg_addr){0, 81}
+#define MIC_ADC_POWERUP		BIT(7)
+#define MIC_ADC_FLAG_ADDR	(struct reg_addr){0, 36}
+
+#define MIC_FCTRL_ADDR		(struct reg_addr){0, 82}
+#define MIC_FCTRL_DEFAULT	0x0
+
+#define MIC_CCTRL_ADDR		(struct reg_addr){0, 83}
+#define MIC_CCTRL_DEFAULT	0x0
+
+#define MIC_BIAS_ADDR		(struct reg_addr){1, 46}
+#define MICBIAS_DEFAULT		(BIT(3) | BIT(1))
+
+#define MIC_PGA_ADDR		(struct reg_addr){1, 47} /* Missing in datasheet */
+#define MIC_PGA_VOL_DEFAULT	0x0 /* 0.5 dB/bit, max volume: 59.5 dB */
+#define MIC_PGAPI_ADDR		(struct reg_addr){1, 48}
+#define MIC_PGAPI_L_DEFAULT	(BIT(7) | BIT(6))
+#define MIC_PGAPI_R_DEFAULT	(BIT(5) | BIT(4))
+#define MIC_PGAMI_ADDR		(struct reg_addr){1, 49}
+#define MIC_ICM_ADDR		(struct reg_addr){1, 50}
+
+/* Page 3 registers */
+#define TIMER_MCLK_DIV_ADDR	(struct reg_addr){3, 16}
+#define TIMER_MCLK_DIV_EN_EXT	(BIT(7))
+#define TIMER_MCLK_DIV_MASK	(BIT_MASK(7))
+#define TIMER_MCLK_DIV_VAL(val)	((val) & TIMER_MCLK_DIV_MASK)
+
+struct reg_addr {
+	uint8_t page; /* page number */
+	uint8_t reg_addr; /* register address */
+};
+
+enum dac_proc_block {
+	PRB_P1_DECIMATION_A = 1,
+	PRB_P7_DECIMATION_B = 7,
+	PRB_P17_DECIMATION_C = 17,
+};
+
+enum adc_proc_block {
+	PRB_R4_DECIMATION_A = 4,
+	PRB_R10_DECIMATION_B = 10,
+	PRB_R16_DECIMATION_C = 16,
+};
+
+enum cm_voltage {
+	CM_VOLTAGE_1P35 = 0,
+	CM_VOLTAGE_1P5 = 1,
+	CM_VOLTAGE_1P65 = 2,
+	CM_VOLTAGE_1P8 = 3,
+};
+
+struct tlv320aic3110_rate_divs {
+	uint32_t mclk;
+	uint32_t rate;
+	uint8_t pll_p;
+	uint8_t pll_j;
+	uint16_t pll_d;
+	uint8_t dosr;
+	uint8_t ndac;
+	uint8_t mdac;
+	uint8_t aosr;
+	uint8_t nadc;
+	uint8_t madc;
+};
+
+/* PLL configurations */
+static const struct tlv320aic3110_rate_divs pll_div_table[] = {
+	/* mclk rate pll: p j d dosr ndac mdac aors nadc madc */
+	/* 8k rate */
+	{12000000, 8000, 1, 8, 1920, 128, 48, 2, 128, 48, 2},
+	{24000000, 8000, 2, 8, 1920, 128, 48, 2, 128, 48, 2},
+	{25000000, 8000, 2, 7, 8643, 128, 48, 2, 128, 48, 2},
+	/* 11.025k rate */
+	{12000000, 11025, 1, 7, 5264, 128, 32, 2, 128, 32, 2},
+	{24000000, 11025, 2, 7, 5264, 128, 32, 2, 128, 32, 2},
+	{25000000, 11025, 2, 7, 2253, 128, 32, 2, 128, 32, 2},
+	/* 16k rate */
+	{12000000, 16000, 1, 8, 1920, 128, 24, 2, 128, 24, 2},
+	{24000000, 16000, 2, 8, 1920, 128, 24, 2, 128, 24, 2},
+	{25000000, 16000, 2, 7, 8643, 128, 24, 2, 128, 24, 2},
+	/* 22.05k rate */
+	{12000000, 22050, 1, 7, 5264, 128, 16, 2, 128, 16, 2},
+	{24000000, 22050, 2, 7, 5264, 128, 16, 2, 128, 16, 2},
+	{25000000, 22050, 2, 7, 2253, 128, 16, 2, 128, 16, 2},
+	/* 32k rate */
+	{12000000, 32000, 1, 8, 1920, 128, 12, 2, 128, 12, 2},
+	{24000000, 32000, 2, 8, 1920, 128, 12, 2, 128, 12, 2},
+	{25000000, 32000, 2, 7, 8643, 128, 12, 2, 128, 12, 2},
+	/* 44.1k rate */
+	{12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2},
+	{24000000, 44100, 2, 7, 5264, 128, 8, 2, 128, 8, 2},
+	{25000000, 44100, 2, 7, 2253, 128, 8, 2, 128, 8, 2},
+	/* 48k rate */
+	{12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2},
+	{24000000, 48000, 2, 8, 1920, 128, 8, 2, 128, 8, 2},
+	{25000000, 48000, 2, 7, 8643, 128, 8, 2, 128, 8, 2},
+	/* 88.2k rate */
+	{12000000, 88200, 1, 7, 5264, 64, 8, 2, 64, 8, 2},
+	{24000000, 88200, 2, 7, 5264, 64, 8, 2, 64, 8, 2},
+	{25000000, 88200, 2, 7, 2253, 64, 8, 2, 64, 8, 2},
+	/* 96k rate */
+	{12000000, 96000, 1, 8, 1920, 64, 8, 2, 64, 8, 2},
+	{24000000, 96000, 2, 8, 1920, 64, 8, 2, 64, 8, 2},
+	{25000000, 96000, 2, 7, 8643, 64, 8, 2, 64, 8, 2},
+	/* 176.4k rate */
+	{12000000, 176400, 1, 7, 5264, 32, 8, 2, 32, 8, 2},
+	{24000000, 176400, 2, 7, 5264, 32, 8, 2, 32, 8, 2},
+	{25000000, 176400, 2, 7, 2253, 32, 8, 2, 32, 8, 2},
+	/* 192k rate */
+	{12000000, 192000, 1, 8, 1920, 32, 8, 2, 32, 8, 2},
+	{24000000, 192000, 2, 8, 1920, 32, 8, 2, 32, 8, 2},
+	{25000000, 192000, 2, 7, 8643, 32, 8, 2, 32, 8, 2},
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_DRIVERS_AUDIO_TLV320DAC310X_H_ */
diff --git a/drivers/audio/wm8904.c b/drivers/audio/wm8904.c
index 8cfe9db900a..29d71a220c3 100644
--- a/drivers/audio/wm8904.c
+++ b/drivers/audio/wm8904.c
@@ -264,9 +264,9 @@ static int wm8904_in_update(
 static int wm8904_in_volume_config(const struct device *dev, audio_channel_t channel, int volume)
 {
 	const uint16_t val = WM8904_REGVAL_IN_VOL(0, volume);
-	const uint16_t mask = WM8904_REGMASK_IN_MUTE;
+	const uint16_t mask = WM8904_REGMASK_IN_VOLUME;
 
-	return wm8904_in_update(dev, channel, val, mask);
+	return wm8904_in_update(dev, channel, mask, val);
 }
 
 static int wm8904_in_mute_config(const struct device *dev, audio_channel_t channel, bool mute)
@@ -274,7 +274,7 @@ static int wm8904_in_mute_config(const struct device *dev, audio_channel_t chann
 	const uint16_t val = WM8904_REGVAL_IN_VOL(mute, 0);
 	const uint16_t mask = WM8904_REGMASK_IN_MUTE;
 
-	return wm8904_in_update(dev, channel, val, mask);
+	return wm8904_in_update(dev, channel, mask, val);
 }
 
 static int wm8904_route_input(const struct device *dev, audio_channel_t channel, uint32_t input)
diff --git a/drivers/audio/wm8904.h b/drivers/audio/wm8904.h
index da01fb00df1..1224ee7f84b 100644
--- a/drivers/audio/wm8904.h
+++ b/drivers/audio/wm8904.h
@@ -102,7 +102,7 @@
  * [1:0] - x_MODE: Input mode
  */
 #define WM8904_REGVAL_INSEL(cm, nin, pin, mode) \
-	(((cm) & 0b1) << 6) | (((nin) & 0b11) << 4)
+	(((cm) & 0b1) << 6) | (((nin) & 0b11) << 4) | (((pin) & 0b11) << 2)
 #define WM8904_REGMASK_INSEL_CMENA		0b01000000
 #define WM8904_REGMASK_INSEL_IP_SEL_N	0b00110000
 #define WM8904_REGMASK_INSEL_IP_SEL_P	0b00001100
diff --git a/drivers/bbram/CMakeLists.txt b/drivers/bbram/CMakeLists.txt
index 9027ab548b3..87a41054ce8 100644
--- a/drivers/bbram/CMakeLists.txt
+++ b/drivers/bbram/CMakeLists.txt
@@ -17,3 +17,4 @@ zephyr_library_sources_ifdef(CONFIG_BBRAM_MICROCHIP_MCP7940N bbram_microchip_mcp
 zephyr_library_sources_ifdef(CONFIG_BBRAM_MICROCHIP_MCP7940N_EMUL bbram_microchip_mcp7940n_emul.c)
 zephyr_library_sources_ifdef(CONFIG_BBRAM_XEC bbram_xec.c)
 zephyr_library_sources_ifdef(CONFIG_BBRAM_STM32 bbram_stm32.c)
+zephyr_library_sources_ifdef(CONFIG_BBRAM_RTS5912 bbram_rts5912.c)
diff --git a/drivers/bbram/Kconfig b/drivers/bbram/Kconfig
index 011c90e03de..5c2bb6bc4a1 100644
--- a/drivers/bbram/Kconfig
+++ b/drivers/bbram/Kconfig
@@ -42,4 +42,6 @@ source "drivers/bbram/Kconfig.xec"
 
 source "drivers/bbram/Kconfig.stm32"
 
+source "drivers/bbram/Kconfig.rts5912"
+
 endif # BBRAM
diff --git a/drivers/bbram/Kconfig.npcx b/drivers/bbram/Kconfig.npcx
index e529022213e..d5190d7d805 100644
--- a/drivers/bbram/Kconfig.npcx
+++ b/drivers/bbram/Kconfig.npcx
@@ -15,3 +15,12 @@ config BBRAM_NPCX_EMUL
 	depends on EMUL
 	help
 	  Enable the emulator for the NPCX BBRAM.
+
+config BBRAM_NPCX_STATUS_REG_WRITE_WORKAROUND
+	bool
+	default y if SOC_SERIES_NPCX4
+	help
+	  Workaround the issue documented in NPCX49nF errata rev1_5, No.2.30.
+	  A write operation to the BKUP_STS register might disable write to all
+	  the Battery-Backed RAM. The workaround is to read the BKUP_STS
+	  register after every write to this register.
diff --git a/drivers/bbram/Kconfig.rts5912 b/drivers/bbram/Kconfig.rts5912
new file mode 100644
index 00000000000..8291b3cebca
--- /dev/null
+++ b/drivers/bbram/Kconfig.rts5912
@@ -0,0 +1,9 @@
+# Copyright (c) 2025, Realtek, SIBG-SD7
+# SPDX-License-Identifier: Apache-2.0
+
+config BBRAM_RTS5912
+	bool "Realtek RTS5912 Battery-backed RAM drivers"
+	default y
+	depends on DT_HAS_REALTEK_RTS5912_BBRAM_ENABLED
+	help
+	  This option enables the BBRAM driver for Realtek RTS5912 of processors.
diff --git a/drivers/bbram/bbram_npcx.c b/drivers/bbram/bbram_npcx.c
index c40a577fabf..d085633fe83 100644
--- a/drivers/bbram/bbram_npcx.c
+++ b/drivers/bbram/bbram_npcx.c
@@ -35,6 +35,12 @@ static int get_bit_and_reset(const struct device *dev, int mask)
 	DRV_STATUS(dev) &= ~mask;
 #else
 	DRV_STATUS(dev) = mask;
+
+	if (IS_ENABLED(CONFIG_BBRAM_NPCX_STATUS_REG_WRITE_WORKAROUND)) {
+		uint8_t __unused read_unused;
+
+		read_unused = DRV_STATUS(dev);
+	}
 #endif
 
 	return result;
@@ -72,7 +78,6 @@ static int bbram_npcx_read(const struct device *dev, size_t offset, size_t size,
 		return -EINVAL;
 	}
 
-
 	bytecpy(data, ((uint8_t *)config->base_addr + offset), size);
 	return 0;
 }
diff --git a/drivers/bbram/bbram_rts5912.c b/drivers/bbram/bbram_rts5912.c
new file mode 100644
index 00000000000..8616d60913f
--- /dev/null
+++ b/drivers/bbram/bbram_rts5912.c
@@ -0,0 +1,99 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 Realtek Semiconductor Corporation, SIBG-SD7
+ * Author: Elmo Lan <elmo_lan@realtek.com>
+ */
+
+#define DT_DRV_COMPAT realtek_rts5912_bbram
+
+#include <zephyr/drivers/bbram.h>
+#include <errno.h>
+#include <zephyr/sys/util.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(rts5912_bbram, CONFIG_BBRAM_LOG_LEVEL);
+
+struct bbram_rts5912_config {
+	uintptr_t base;
+	int size;
+};
+
+static int bbram_rts5912_get_size(const struct device *dev, size_t *size)
+{
+	const struct bbram_rts5912_config *config = dev->config;
+
+	*size = config->size;
+	LOG_INF("size: 0x%08x", *size);
+	return 0;
+}
+
+static int bbram_rts5912_read(const struct device *dev, size_t offset, size_t size, uint8_t *data)
+{
+	const struct bbram_rts5912_config *config = dev->config;
+
+	uint32_t word;
+	size_t start_offset, bytes_to_read;
+
+	if (size < 1 || offset + size > config->size) {
+		LOG_ERR("Invalid params");
+		return -EFAULT;
+	}
+
+	/* The bbram in RTS5912 only accepts word-access.
+	 * Read it as a word, then split it into bytes.
+	 */
+	for (int i = 0; i < size;) {
+		word = *(uint32_t *)(config->base + ROUND_DOWN((offset + i), 4));
+		start_offset = (offset + i) % 4;
+		bytes_to_read = MIN(4 - start_offset, size - i);
+		memcpy(&data[i], ((uint8_t *)&word) + start_offset, bytes_to_read);
+		i += bytes_to_read;
+	}
+
+	return 0;
+}
+
+static int bbram_rts5912_write(const struct device *dev, size_t offset, size_t size,
+			       const uint8_t *data)
+{
+	const struct bbram_rts5912_config *config = dev->config;
+
+	uint32_t word;
+	size_t start_offset, bytes_to_write;
+
+	if (size < 1 || offset + size > config->size) {
+		LOG_ERR("Invalid params");
+		return -EFAULT;
+	}
+
+	/* The BBRAM in RTS5912 only accepts word-access. Read it as a word,
+	 * then modify the byte field, and finally write it back as a word
+	 */
+	for (int i = 0; i < size;) {
+		word = *(uint32_t *)(config->base + ROUND_DOWN((offset + i), 4));
+		start_offset = (offset + i) % 4;
+		bytes_to_write = MIN(4 - start_offset, size - i);
+		memcpy(((uint8_t *)&word) + start_offset, &data[i], bytes_to_write);
+		*(uint32_t *)(config->base + ROUND_DOWN((offset + i), 4)) = word;
+		i += bytes_to_write;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(bbram, bbram_rts5912_driver_api) = {
+	.get_size = bbram_rts5912_get_size,
+	.read = bbram_rts5912_read,
+	.write = bbram_rts5912_write,
+};
+
+#define BBRAM_INIT(inst)                                                                           \
+	static const struct bbram_rts5912_config bbram_cfg_##inst = {                              \
+		.base = DT_INST_REG_ADDR(inst),                                                    \
+		.size = DT_INST_REG_SIZE(inst),                                                    \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(inst, NULL, NULL, NULL, &bbram_cfg_##inst, PRE_KERNEL_1,             \
+			      CONFIG_BBRAM_INIT_PRIORITY, &bbram_rts5912_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(BBRAM_INIT);
diff --git a/drivers/bluetooth/hci/CMakeLists.txt b/drivers/bluetooth/hci/CMakeLists.txt
index 5f10d6566cb..35c97fa79b8 100644
--- a/drivers/bluetooth/hci/CMakeLists.txt
+++ b/drivers/bluetooth/hci/CMakeLists.txt
@@ -25,6 +25,10 @@ if(CONFIG_DT_HAS_INFINEON_CAT1_BLESS_HCI_ENABLED)
   zephyr_blobs_verify(MODULE hal_infineon REQUIRED)
 endif()
 
+if(CONFIG_DT_HAS_RENESAS_BT_HCI_DA1469X_ENABLED)
+  zephyr_blobs_verify(MODULE hal_renesas REQUIRED)
+endif()
+
 endif() # CONFIG_BUILD_ONLY_NO_BLOBS
 
 zephyr_library_sources_ifdef(CONFIG_BT_ESP32       hci_esp32.c)
@@ -38,8 +42,8 @@ zephyr_library_sources_ifdef(CONFIG_BT_CYW208XX  hci_ifx_cyw208xx.c)
 zephyr_library_sources_ifdef(CONFIG_BT_STM32_IPM   ipm_stm32wb.c)
 zephyr_library_sources_ifdef(CONFIG_BT_STM32WBA    hci_stm32wba.c)
 zephyr_library_sources_ifdef(CONFIG_BT_STM32WB0    hci_stm32wb0.c)
-zephyr_library_sources_ifdef(CONFIG_BT_USERCHAN    userchan.c)
 zephyr_library_sources_ifdef(CONFIG_BT_SILABS_EFR32 hci_silabs_efr32.c)
+zephyr_library_sources_ifdef(CONFIG_BT_SILABS_SIWX91X hci_silabs_siwx91x.c)
 zephyr_library_sources_ifdef(CONFIG_BT_PSOC6_BLESS hci_ifx_psoc6_bless.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_NRF5340_CPUAPP nrf53_support.c)
 zephyr_library_sources_ifdef(CONFIG_BT_AMBIQ_HCI   hci_ambiq.c apollox_blue.c)
@@ -47,3 +51,12 @@ zephyr_library_sources_ifdef(CONFIG_BT_DA1453X     hci_da1453x.c)
 zephyr_library_sources_ifdef(CONFIG_BT_DA1469X     hci_da1469x.c)
 zephyr_library_sources_ifdef(CONFIG_BT_NXP         hci_nxp.c)
 zephyr_library_sources_ifdef(CONFIG_BT_H4_NXP_CTLR hci_nxp_setup.c)
+
+if(CONFIG_BT_USERCHAN)
+  zephyr_library_sources(userchan.c)
+  if (CONFIG_NATIVE_LIBRARY)
+    target_sources(native_simulator INTERFACE userchan_bottom.c)
+  else()
+    zephyr_library_sources(userchan_bottom.c)
+  endif()
+endif()
diff --git a/drivers/bluetooth/hci/Kconfig b/drivers/bluetooth/hci/Kconfig
index 76fd043d249..0e4b2a6c38a 100644
--- a/drivers/bluetooth/hci/Kconfig
+++ b/drivers/bluetooth/hci/Kconfig
@@ -81,6 +81,16 @@ config BT_SPI_INIT_PRIORITY
 	depends on BT_SPI
 	default 75
 
+config BT_SPI_BOOT_TIMEOUT_SEC
+	int "Seconds to wait for SPI device to report ready"
+	depends on BT_SPI_ZEPHYR || BT_SPI_BLUENRG
+	default 30
+	help
+	  Maximum duration for a HCI SPI Controller to report ready through the
+	  Zephyr Project defined `EVT_BLUE_INITIALIZED` HCI vendor event.
+	  Default is 30 seconds to support a bootloader image swap on the
+	  Controller.
+
 config BT_SPI_ZEPHYR
 	bool
 	default y
@@ -142,7 +152,7 @@ config BT_STM32WB0
 	  ST STM32WB0 HCI Bluetooth interface
 
 config BT_SILABS_EFR32
-	bool
+	bool "Silabs EFR32 HCI driver"
 	default y
 	depends on DT_HAS_SILABS_BT_HCI_EFR32_ENABLED
 	depends on ZEPHYR_HAL_SILABS_MODULE_BLOBS || BUILD_ONLY_NO_BLOBS
@@ -163,15 +173,31 @@ config BT_SILABS_EFR32
 	  Use Silicon Labs binary Bluetooth library to connect to the
 	  controller.
 
+source "drivers/bluetooth/hci/Kconfig.silabs"
+
+config BT_SILABS_SIWX91X
+	bool "Silabs SiWx91x Bluetooth interface"
+	default y
+	depends on DT_HAS_SILABS_SIWX91X_BT_HCI_ENABLED
+	select WISECONNECT_NETWORK_STACK
+	select ENTROPY_GENERATOR
+	help
+	  Use Silicon Labs Wiseconnect 3.x Bluetooth library to connect to the controller.
+
+	# SiWx917 BLE controller currently does not support HCI Command: Host Number of Completed Packets
+	configdefault BT_HCI_ACL_FLOW_CONTROL
+		default n if BT_SILABS_SIWX91X
+
 config BT_USERCHAN
 	bool
-	depends on (BOARD_NATIVE_POSIX || BOARD_NATIVE_SIM)
+	depends on BOARD_NATIVE_SIM
 	default y
 	depends on DT_HAS_ZEPHYR_BT_HCI_USERCHAN_ENABLED
+	select NATIVE_USE_NSI_ERRNO
 	help
 	  This driver provides access to the local Linux host's Bluetooth
 	  adapter using a User Channel HCI socket to the Linux kernel. It
-	  is only intended to be used with the native POSIX build of Zephyr.
+	  is only intended to be used with the native_sim[//64] build of Zephyr.
 	  The Bluetooth adapter must be powered off in order for Zephyr to
 	  be able to use it.
 
@@ -180,6 +206,15 @@ config BT_ESP32
 	default y
 	depends on DT_HAS_ESPRESSIF_ESP32_BT_HCI_ENABLED
 	depends on ZEPHYR_HAL_ESPRESSIF_MODULE_BLOBS || BUILD_ONLY_NO_BLOBS
+	select HAS_BT_CTLR
+	select BT_CTLR_PRIVACY_SUPPORT
+	select BT_CTLR_EXT_SCAN_FP_SUPPORT
+	select BT_CTLR_DATA_LEN_UPDATE_SUPPORT
+	select BT_CTLR_ADV_EXT_SUPPORT if SOC_SERIES_ESP32S3 || SOC_SERIES_ESP32C3
+	select BT_CTLR_PHY_UPDATE_SUPPORT if SOC_SERIES_ESP32S3 || SOC_SERIES_ESP32C3
+	select BT_CTLR_EXT_REJ_IND_SUPPORT if SOC_SERIES_ESP32S3 || SOC_SERIES_ESP32C3
+	select BT_CTLR_PHY_2M_SUPPORT if SOC_SERIES_ESP32S3 || SOC_SERIES_ESP32C3
+	select BT_CTLR_CHAN_SEL_2_SUPPORT if SOC_SERIES_ESP32S3 || SOC_SERIES_ESP32C3
 	help
 	  Espressif HCI bluetooth interface
 
@@ -234,6 +269,7 @@ config BT_AMBIQ_HCI
 	select GPIO if SOC_SERIES_APOLLO4X
 	select CLOCK_CONTROL if SOC_SERIES_APOLLO4X
 	select BT_HCI_SETUP
+	select AMBIQ_COMPONENT_USE_BT
 	help
 	  Supports Ambiq Bluetooth SoC using SPI as the communication protocol.
 	  HCI packets are sent and received as single Byte transfers.
@@ -319,18 +355,10 @@ config BT_DRV_RX_STACK_SIZE
 	default BT_RX_STACK_SIZE if (BT_H4 || BT_HCI_RAW_H4)
 	default BT_STM32_IPM_RX_STACK_SIZE if BT_STM32_IPM
 	default HCI_NXP_RX_STACK_SIZE if HCI_NXP_RX_THREAD
-	default 256
+	default 512
 	help
 	  Stack size for the HCI driver's RX thread.
 
-config BT_SILABS_EFR32_BUFFER_MEMORY
-	int "Silicon Labs Bluetooth Library memory buffer size"
-	depends on BT_SILABS_EFR32
-	default 6144
-	help
-	  Select the size of allocated memory buffer for the Silicon Labs
-	  Bluetooth Library.
-
 config BT_H4_NXP_CTLR
 	bool "NXP Bluetooth Controller"
 	select GPIO
diff --git a/drivers/bluetooth/hci/Kconfig.esp32 b/drivers/bluetooth/hci/Kconfig.esp32
index ad7a53d5de3..294b6a1cd84 100644
--- a/drivers/bluetooth/hci/Kconfig.esp32
+++ b/drivers/bluetooth/hci/Kconfig.esp32
@@ -2,16 +2,19 @@
 
 if BT_ESP32
 
+config HEAP_MEM_POOL_ADD_SIZE_ESP_BT
+	int
+	default 25600 if ESP_BT_HEAP_SYSTEM
+	default 0
+	help
+	  Make sure there is a minimal heap available for BT driver.
+
 choice ESP_BT_HEAP
 	prompt "Bluetooth adapter heap in use"
-	default ESP_BT_HEAP_RUNTIME
-
-	config ESP_BT_HEAP_RUNTIME
-		bool "Bluetooth adapter use ESP runtime heap"
-		depends on ESP_HEAP_RUNTIME
+	default ESP_BT_HEAP_SYSTEM
 
 	config ESP_BT_HEAP_SYSTEM
-		bool "Bluetooth adapter use system heap"
+		bool "Bluetooth adapter use the kernel mempool heap (k_malloc)"
 
 endchoice # ESP_BT_HEAP
 
diff --git a/drivers/bluetooth/hci/Kconfig.nxp b/drivers/bluetooth/hci/Kconfig.nxp
index 28b9baa2064..d5f72a0d720 100644
--- a/drivers/bluetooth/hci/Kconfig.nxp
+++ b/drivers/bluetooth/hci/Kconfig.nxp
@@ -71,8 +71,14 @@ endif # BT_NXP
 
 if BT_H4_NXP_CTLR
 
+choice BT_NXP_MODULE
+	# All NXP Bluetooth modules controlled by BT_H4_NXP_CTLR should be added to this section
+	# similar with BT_NXP_NW612.
+	prompt "NXP Bluetooth Module"
+	default BT_NXP_NW612
+
 config BT_NXP_NW612
-	bool "NXP IW612 Chipset"
+	bool "NW612 firmware for NXP IW612 Chipset"
 	help
 	  NXP IW612 Chipset supports Wi-Fi? 802.11a/b/g/n/ac/ax + Bluetooth? 5.3
 	  BR/EDR/LE + IEEE802.1.5.4 up to 601 Mbps data rate on Wi-Fi? and 2Mbps
@@ -83,4 +89,6 @@ config BT_NXP_NW612
 	  dual-band-1x1-wi-fi-6-802-11ax-plus-bluetooth-5-4-plus-802-15-4-tri-
 	  radio-solution:IW612.
 
+endchoice # BT_NXP_MODULE
+
 endif # BT_H4_NXP_CTLR
diff --git a/drivers/bluetooth/hci/Kconfig.silabs b/drivers/bluetooth/hci/Kconfig.silabs
new file mode 100644
index 00000000000..482131c51f7
--- /dev/null
+++ b/drivers/bluetooth/hci/Kconfig.silabs
@@ -0,0 +1,54 @@
+# Copyright (c) 2025 Silicon Laboratories Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+menu "EFR32 Bluetooth Controller Configuration"
+	depends on BT_SILABS_EFR32
+
+config BT_SILABS_EFR32_HCI_VS
+	bool "Silicon Labs vendor specific HCI extensions"
+	help
+	  Enable Silicon Labs vendor specific HCI extensions.
+
+config BT_SILABS_EFR32_BUFFER_MEMORY
+	int "Memory buffer size"
+	default 6144
+	help
+	  Select the size of allocated memory buffer for the Silicon Labs
+	  Bluetooth Library. If set too low the capacity of the link layer may
+	  suffer.
+
+config BT_SILABS_EFR32_USER_ADVERTISERS
+	int "User advertisement sets"
+	default 1
+	help
+	  Amount of advertisement sets reserved for application.
+
+config BT_SILABS_EFR32_ACCEPT_LIST_SIZE
+	int "Accept list size"
+	default 1
+	help
+	  Accept list size.
+
+config BT_SILABS_EFR32_COMPLETED_PACKETS_THRESHOLD
+	int "Completed packet reporting threshold"
+	default 1
+	help
+	  Completed packet reporting threshold value.
+
+config BT_SILABS_EFR32_COMPLETED_PACKETS_TIMEOUT
+	int "Completed packet report event timeout"
+	default 3
+	help
+	  Completed packet report event timeout.
+
+config BT_SILABS_EFR32_ACCEPT_LINK_LAYER_STACK_SIZE
+	int "Link layer stack size"
+	default 1024
+	help
+	  Link layer stack size.
+
+config BT_SILABS_EFR32_LL_THREAD_PRIO
+	# Hidden option for Co-Operative Link Layer thread priority
+	def_int 0
+
+endmenu
diff --git a/drivers/bluetooth/hci/apollox_blue.c b/drivers/bluetooth/hci/apollox_blue.c
index ab9abd07d4a..1fb2ab33fb1 100644
--- a/drivers/bluetooth/hci/apollox_blue.c
+++ b/drivers/bluetooth/hci/apollox_blue.c
@@ -25,7 +25,7 @@ LOG_MODULE_REGISTER(bt_apollox_driver);
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/drivers/clock_control/clock_control_ambiq.h>
 
-#include <am_mcu_apollo.h>
+#include <soc.h>
 #include "apollox_blue.h"
 #if (CONFIG_SOC_SERIES_APOLLO4X)
 #include "am_devices_cooper.h"
diff --git a/drivers/bluetooth/hci/h4.c b/drivers/bluetooth/hci/h4.c
index 4ca495e2abe..34dea69852f 100644
--- a/drivers/bluetooth/hci/h4.c
+++ b/drivers/bluetooth/hci/h4.c
@@ -193,6 +193,11 @@ static inline void copy_hdr(struct h4_data *h4)
 
 static void reset_rx(struct h4_data *h4)
 {
+	if (h4->rx.buf) {
+		net_buf_unref(h4->rx.buf);
+		h4->rx.buf = NULL;
+	}
+
 	h4->rx.type = BT_HCI_H4_NONE;
 	h4->rx.remaining = 0U;
 	h4->rx.have_hdr = false;
@@ -545,6 +550,35 @@ static int h4_open(const struct device *dev, bt_hci_recv_t recv)
 	return 0;
 }
 
+int __weak bt_hci_transport_teardown(const struct device *dev)
+{
+	return 0;
+}
+
+static int h4_close(const struct device *dev)
+{
+	const struct h4_config *cfg = dev->config;
+	struct h4_data *h4 = dev->data;
+	int err;
+
+	LOG_DBG("");
+
+	uart_irq_rx_disable(cfg->uart);
+	uart_irq_tx_disable(cfg->uart);
+
+	err = bt_hci_transport_teardown(cfg->uart);
+	if (err < 0) {
+		return err;
+	}
+
+	/* Abort RX thread */
+	k_thread_abort(cfg->rx_thread);
+
+	h4->recv = NULL;
+
+	return 0;
+}
+
 #if defined(CONFIG_BT_HCI_SETUP)
 static int h4_setup(const struct device *dev, const struct bt_hci_setup_params *params)
 {
@@ -567,6 +601,7 @@ static int h4_setup(const struct device *dev, const struct bt_hci_setup_params *
 static DEVICE_API(bt_hci, h4_driver_api) = {
 	.open = h4_open,
 	.send = h4_send,
+	.close = h4_close,
 #if defined(CONFIG_BT_HCI_SETUP)
 	.setup = h4_setup,
 #endif
diff --git a/drivers/bluetooth/hci/h4_ifx_cyw43xxx.c b/drivers/bluetooth/hci/h4_ifx_cyw43xxx.c
index ae98a8e51e2..6bc563fb9f2 100644
--- a/drivers/bluetooth/hci/h4_ifx_cyw43xxx.c
+++ b/drivers/bluetooth/hci/h4_ifx_cyw43xxx.c
@@ -15,6 +15,8 @@
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/drivers/uart.h>
 
diff --git a/drivers/bluetooth/hci/hci_da1453x.c b/drivers/bluetooth/hci/hci_da1453x.c
index 668dd8aaa18..8e63e377cb7 100644
--- a/drivers/bluetooth/hci/hci_da1453x.c
+++ b/drivers/bluetooth/hci/hci_da1453x.c
@@ -41,7 +41,7 @@ int bt_hci_transport_setup(const struct device *h4)
 	k_sleep(K_MSEC(DT_INST_PROP_OR(0, reset_assert_duration_ms, 0)));
 
 	/* Release the DA1453x from reset */
-	err = gpio_pin_set_dt(&bt_reset, 0);
+	err = gpio_pin_configure_dt(&bt_reset, GPIO_OUTPUT_INACTIVE);
 	if (err) {
 		return err;
 	}
diff --git a/drivers/bluetooth/hci/hci_nxp.c b/drivers/bluetooth/hci/hci_nxp.c
index 1b9eb60b229..153130d9525 100644
--- a/drivers/bluetooth/hci/hci_nxp.c
+++ b/drivers/bluetooth/hci/hci_nxp.c
@@ -16,6 +16,7 @@
 #include <zephyr/drivers/flash.h>
 #include <zephyr/bluetooth/hci_types.h>
 #include <soc.h>
+#include <zephyr/pm/policy.h>
 
 #include <fwk_platform_ble.h>
 #include <fwk_platform.h>
@@ -71,6 +72,12 @@ LOG_MODULE_REGISTER(bt_driver);
 #if !defined(CONFIG_BT_HCI_SET_PUBLIC_ADDR)
 #define bt_nxp_set_mac_address(public_addr) 0
 #endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(standby), okay) && defined(CONFIG_PM) &&\
+	defined(CONFIG_HCI_NXP_ENABLE_AUTO_SLEEP)
+#define HCI_NXP_LOCK_STANDBY_BEFORE_SEND
+#endif
+
 /* -------------------------------------------------------------------------- */
 /*                              Public prototypes                             */
 /* -------------------------------------------------------------------------- */
@@ -413,7 +420,18 @@ static int bt_nxp_send(const struct device *dev, struct net_buf *buf)
 	}
 
 	net_buf_push_u8(buf, packetType);
+#if defined(HCI_NXP_LOCK_STANDBY_BEFORE_SEND)
+	/* Sending an HCI message requires to wake up the controller core if it's asleep.
+	 * Platform controllers may send reponses using non wakeable interrupts which can
+	 * be lost during standby usage.
+	 * Blocking standby usage until the HCI message is sent.
+	 */
+	pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
+#endif
 	PLATFORM_SendHciMessage(buf->data, buf->len);
+#if defined(HCI_NXP_LOCK_STANDBY_BEFORE_SEND)
+	pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
+#endif
 
 	net_buf_unref(buf);
 
diff --git a/drivers/bluetooth/hci/hci_nxp_setup.c b/drivers/bluetooth/hci/hci_nxp_setup.c
index bacc9f3ca5b..6bd0e5d5764 100644
--- a/drivers/bluetooth/hci/hci_nxp_setup.c
+++ b/drivers/bluetooth/hci/hci_nxp_setup.c
@@ -194,6 +194,7 @@ struct nxp_ctlr_fw_upload_state {
 	bool is_error_case;
 	bool is_cmd7_req;
 	bool is_entry_point_req;
+	bool is_setup_done;
 
 	uint8_t last_5bytes_buffer[6];
 };
@@ -1171,11 +1172,15 @@ static int bt_nxp_ctlr_init(void)
 
 int bt_hci_transport_setup(const struct device *dev)
 {
+	int ret = 0;
 	if (dev != uart_dev) {
 		return -EINVAL;
 	}
 
-	return bt_nxp_ctlr_init();
+	if (!fw_upload.is_setup_done) {
+		ret = bt_nxp_ctlr_init();
+	}
+	return ret;
 }
 
 #define BT_HCI_VSC_BAUDRATE_UPDATE_LENGTH 4
@@ -1228,13 +1233,15 @@ int bt_h4_vnd_setup(const struct device *dev)
 		return 0;
 	}
 
-	err = bt_hci_baudrate_update(dev, operation_speed);
-	if (err) {
-		return err;
-	}
+	if (!fw_upload.is_setup_done) {
+		err = bt_hci_baudrate_update(dev, operation_speed);
+		if (err) {
+			return err;
+		}
 
-	/* BT waiting time after controller bandrate updated */
-	(void)k_msleep(CONFIG_BT_H4_NXP_CTLR_WAIT_TIME_AFTER_BAUDRATE_UPDATE);
+		/* BT waiting time after controller bandrate updated */
+		(void)k_msleep(CONFIG_BT_H4_NXP_CTLR_WAIT_TIME_AFTER_BAUDRATE_UPDATE);
+	}
 
 	err = fw_upload_uart_reconfig(operation_speed, flowcontrol_of_hci);
 	if (err) {
@@ -1242,5 +1249,7 @@ int bt_h4_vnd_setup(const struct device *dev)
 		return err;
 	}
 
+	fw_upload.is_setup_done = true;
+
 	return 0;
 }
diff --git a/drivers/bluetooth/hci/hci_silabs_efr32.c b/drivers/bluetooth/hci/hci_silabs_efr32.c
index f148c8eadfa..c528b3b6910 100644
--- a/drivers/bluetooth/hci/hci_silabs_efr32.c
+++ b/drivers/bluetooth/hci/hci_silabs_efr32.c
@@ -5,6 +5,7 @@
  */
 
 #include <zephyr/drivers/bluetooth.h>
+#include <zephyr/kernel.h>
 
 #include <sl_btctrl_linklayer.h>
 #include <sl_hci_common_transport.h>
@@ -21,27 +22,37 @@ struct hci_data {
 	bt_hci_recv_t recv;
 };
 
-#define SL_BT_CONFIG_ACCEPT_LIST_SIZE				1
-#define SL_BT_CONFIG_MAX_CONNECTIONS				1
-#define SL_BT_CONFIG_USER_ADVERTISERS				1
-#define SL_BT_CONTROLLER_BUFFER_MEMORY				CONFIG_BT_SILABS_EFR32_BUFFER_MEMORY
-#define SL_BT_CONTROLLER_LE_BUFFER_SIZE_MAX			CONFIG_BT_BUF_ACL_TX_COUNT
-#define SL_BT_CONTROLLER_COMPLETED_PACKETS_THRESHOLD		1
-#define SL_BT_CONTROLLER_COMPLETED_PACKETS_EVENTS_TIMEOUT	3
-#define SL_BT_SILABS_LL_STACK_SIZE				1024
+#if defined(CONFIG_BT_MAX_CONN)
+#define MAX_CONN CONFIG_BT_MAX_CONN
+#else
+#define MAX_CONN 0
+#endif
+
+#if defined(CONFIG_BT_CTLR_RL_SIZE)
+#define CTLR_RL_SIZE CONFIG_BT_CTLR_RL_SIZE
+#else
+#define CTLR_RL_SIZE 0
+#endif
 
-static K_KERNEL_STACK_DEFINE(slz_ll_stack, SL_BT_SILABS_LL_STACK_SIZE);
+static K_KERNEL_STACK_DEFINE(slz_ll_stack, CONFIG_BT_SILABS_EFR32_ACCEPT_LINK_LAYER_STACK_SIZE);
 static struct k_thread slz_ll_thread;
 
+static K_KERNEL_STACK_DEFINE(slz_rx_stack, CONFIG_BT_DRV_RX_STACK_SIZE);
+static struct k_thread slz_rx_thread;
+
 /* Semaphore for Link Layer */
 K_SEM_DEFINE(slz_ll_sem, 0, 1);
 
 /* Events mask for Link Layer */
 static atomic_t sli_btctrl_events;
 
+/* FIFO for received HCI packets */
+static struct k_fifo slz_rx_fifo;
+
 /* FIXME: these functions should come from the SiSDK headers! */
 void BTLE_LL_EventRaise(uint32_t events);
 void BTLE_LL_Process(uint32_t events);
+int16_t BTLE_LL_SetMaxPower(int16_t power);
 bool sli_pending_btctrl_events(void);
 RAIL_Handle_t BTLE_LL_GetRadioHandle(void);
 
@@ -61,6 +72,82 @@ void rail_isr_installer(void)
 	IRQ_CONNECT(AGC_IRQn, 0, AGC_IRQHandler, NULL, 0);
 }
 
+static bool slz_is_evt_discardable(const struct bt_hci_evt_hdr *hdr, const uint8_t *params,
+				   int16_t params_len)
+{
+	switch (hdr->evt) {
+	case BT_HCI_EVT_LE_META_EVENT: {
+		struct bt_hci_evt_le_meta_event *meta_evt = (void *)params;
+
+		if (params_len < sizeof(*meta_evt)) {
+			return false;
+		}
+		params += sizeof(*meta_evt);
+		params_len -= sizeof(*meta_evt);
+
+		switch (meta_evt->subevent) {
+		case BT_HCI_EVT_LE_ADVERTISING_REPORT:
+			return true;
+		case BT_HCI_EVT_LE_EXT_ADVERTISING_REPORT: {
+			struct bt_hci_evt_le_ext_advertising_report *evt = (void *)params;
+
+			if (!IS_ENABLED(CONFIG_BT_EXT_ADV)) {
+				return false;
+			}
+
+			if (params_len < sizeof(*evt) + sizeof(*evt->adv_info)) {
+				return false;
+			}
+
+			/* Never discard if the event could be part of a multi-part report event,
+			 * because the missing part could confuse the BT host.
+			 */
+			return (evt->num_reports == 1) &&
+			       ((evt->adv_info[0].evt_type & BT_HCI_LE_ADV_EVT_TYPE_LEGACY) != 0);
+		}
+		default:
+			return false;
+		}
+	}
+	default:
+		return false;
+	}
+}
+
+static struct net_buf *slz_bt_recv_evt(const uint8_t *data, const int16_t len)
+{
+	struct net_buf *buf;
+	bool discardable;
+	const struct bt_hci_evt_hdr *hdr = (void *)data;
+	const uint8_t *params = &data[sizeof(*hdr)];
+	const int16_t params_len = len - sizeof(*hdr);
+
+	if (len < sizeof(*hdr)) {
+		LOG_ERR("Event header is missing");
+		return NULL;
+	}
+
+	discardable = slz_is_evt_discardable(hdr, params, params_len);
+	buf = bt_buf_get_evt(hdr->evt, discardable, discardable ? K_NO_WAIT : K_FOREVER);
+	if (!buf) {
+		LOG_DBG("Discardable buffer pool full, ignoring event");
+		return buf;
+	}
+
+	net_buf_add_mem(buf, data, len);
+
+	return buf;
+}
+
+static struct net_buf *slz_bt_recv_acl(const uint8_t *data, const int16_t len)
+{
+	struct net_buf *buf = bt_buf_get_rx(BT_BUF_ACL_IN, K_FOREVER);
+
+	net_buf_add_mem(buf, data, len);
+
+	return buf;
+}
+
 /**
  * @brief Transmit HCI message using the currently used transport layer.
  * The HCI calls this function to transmit a full HCI message.
@@ -70,33 +157,36 @@ void rail_isr_installer(void)
  */
 uint32_t hci_common_transport_transmit(uint8_t *data, int16_t len)
 {
-	const struct device *dev = DEVICE_DT_GET(DT_DRV_INST(0));
-	struct hci_data *hci = dev->data;
 	struct net_buf *buf;
-	uint8_t packet_type = data[0];
-	uint8_t event_code;
+	uint8_t packet_type;
 
 	LOG_HEXDUMP_DBG(data, len, "host packet data:");
 
+	if (len < 1) {
+		LOG_ERR("HCI packet type is missing");
+		return -EINVAL;
+	}
+
+	packet_type = data[0];
 	/* drop packet type from the frame buffer - it is no longer needed */
-	data = &data[1];
+	data += 1;
 	len -= 1;
 
 	switch (packet_type) {
 	case BT_HCI_H4_EVT:
-		event_code = data[0];
-		buf = bt_buf_get_evt(event_code, false, K_FOREVER);
+		buf = slz_bt_recv_evt(data, len);
 		break;
 	case BT_HCI_H4_ACL:
-		buf = bt_buf_get_rx(BT_BUF_ACL_IN, K_FOREVER);
+		buf = slz_bt_recv_acl(data, len);
 		break;
 	default:
 		LOG_ERR("Unknown HCI type: %d", packet_type);
 		return -EINVAL;
 	}
 
-	net_buf_add_mem(buf, data, len);
-	hci->recv(dev, buf);
+	if (buf) {
+		k_fifo_put(&slz_rx_fifo, buf);
+	}
 
 	sl_btctrl_hci_transmit_complete(0);
 
@@ -137,7 +227,7 @@ static int slz_bt_send(const struct device *dev, struct net_buf *buf)
  * or an HCI event to pass upstairs. The BTLE_LL_Process function call will
  * take care of all of them, and add HCI events to the HCI queue when applicable.
  */
-static void slz_thread_func(void *p1, void *p2, void *p3)
+static void slz_ll_thread_func(void *p1, void *p2, void *p3)
 {
 	ARG_UNUSED(p1);
 	ARG_UNUSED(p2);
@@ -152,17 +242,52 @@ static void slz_thread_func(void *p1, void *p2, void *p3)
 	}
 }
 
+static void slz_rx_thread_func(void *p1, void *p2, void *p3)
+{
+	const struct device *dev = p1;
+	struct hci_data *hci = dev->data;
+
+	ARG_UNUSED(p2);
+	ARG_UNUSED(p3);
+
+	while (true) {
+		struct net_buf *buf = k_fifo_get(&slz_rx_fifo, K_FOREVER);
+
+		hci->recv(dev, buf);
+	}
+}
+
+static void slz_set_tx_power(int16_t max_power_dbm)
+{
+	const int16_t max_power_cbm = max_power_dbm * 10;
+	const int16_t actual_max_power_cbm = BTLE_LL_SetMaxPower(max_power_cbm);
+	const int16_t actual_max_power_dbm = DIV_ROUND_CLOSEST(actual_max_power_cbm, 10);
+
+	if (actual_max_power_dbm != max_power_dbm) {
+		LOG_WRN("Unable to set max TX power to %d dBm, actual max is %d dBm", max_power_dbm,
+			actual_max_power_dbm);
+	}
+}
+
 static int slz_bt_open(const struct device *dev, bt_hci_recv_t recv)
 {
 	struct hci_data *hci = dev->data;
 	int ret;
 
-	/* Start RX thread */
-	k_thread_create(&slz_ll_thread, slz_ll_stack,
-			K_KERNEL_STACK_SIZEOF(slz_ll_stack),
-			slz_thread_func, NULL, NULL, NULL,
-			K_PRIO_COOP(CONFIG_BT_DRIVER_RX_HIGH_PRIO), 0,
-			K_NO_WAIT);
+	BUILD_ASSERT(CONFIG_NUM_METAIRQ_PRIORITIES > 0,
+		     "Config NUM_METAIRQ_PRIORITIES must be greater than 0");
+	BUILD_ASSERT(CONFIG_BT_SILABS_EFR32_LL_THREAD_PRIO < CONFIG_NUM_METAIRQ_PRIORITIES,
+		     "Config BT_SILABS_EFR32_LL_THREAD_PRIO must be a meta-IRQ priority");
+
+	k_fifo_init(&slz_rx_fifo);
+
+	k_thread_create(&slz_ll_thread, slz_ll_stack, K_KERNEL_STACK_SIZEOF(slz_ll_stack),
+			slz_ll_thread_func, NULL, NULL, NULL,
+			K_PRIO_COOP(CONFIG_BT_SILABS_EFR32_LL_THREAD_PRIO), 0, K_NO_WAIT);
+
+	k_thread_create(&slz_rx_thread, slz_rx_stack, K_KERNEL_STACK_SIZEOF(slz_rx_stack),
+			slz_rx_thread_func, (void *)dev, NULL, NULL,
+			K_PRIO_COOP(CONFIG_BT_DRIVER_RX_HIGH_PRIO), 0, K_NO_WAIT);
 
 	rail_isr_installer();
 	sl_rail_util_pa_init();
@@ -172,13 +297,18 @@ static int slz_bt_open(const struct device *dev, bt_hci_recv_t recv)
 	sl_btctrl_disable_coded_phy();
 
 	/* sl_btctrl_init_mem returns the number of memory buffers allocated */
-	ret = sl_btctrl_init_mem(SL_BT_CONTROLLER_BUFFER_MEMORY);
+	ret = sl_btctrl_init_mem(CONFIG_BT_SILABS_EFR32_BUFFER_MEMORY);
 	if (!ret) {
 		LOG_ERR("Failed to allocate memory %d", ret);
 		return -ENOMEM;
 	}
 
-	sl_btctrl_configure_le_buffer_size(SL_BT_CONTROLLER_LE_BUFFER_SIZE_MAX);
+	sl_btctrl_configure_le_buffer_size(CONFIG_BT_BUF_ACL_TX_COUNT);
+
+	if (IS_ENABLED(CONFIG_BT_CTLR_PRIVACY)) {
+		sl_btctrl_allocate_resolving_list_memory(CTLR_RL_SIZE);
+		sl_btctrl_init_privacy();
+	}
 
 	ret = sl_btctrl_init_ll();
 	if (ret) {
@@ -186,50 +316,40 @@ static int slz_bt_open(const struct device *dev, bt_hci_recv_t recv)
 		goto deinit;
 	}
 
-	if (IS_ENABLED(CONFIG_BT_BROADCASTER) || IS_ENABLED(CONFIG_BT_PERIPHERAL)) {
-		sl_btctrl_init_adv();
-	}
-	if (IS_ENABLED(CONFIG_BT_CENTRAL) || IS_ENABLED(CONFIG_BT_OBSERVER)) {
-		sl_btctrl_init_scan();
-	}
-	if (IS_ENABLED(CONFIG_BT_CONN)) {
-		sl_btctrl_init_conn();
-	}
+	slz_set_tx_power(CONFIG_BT_CTLR_TX_PWR_ANTENNA);
+
+	sl_btctrl_init_adv();
+	sl_btctrl_init_scan();
+	sl_btctrl_init_conn();
 	sl_btctrl_init_phy();
 
 	if (IS_ENABLED(CONFIG_BT_EXT_ADV)) {
-		if (IS_ENABLED(CONFIG_BT_BROADCASTER) || IS_ENABLED(CONFIG_BT_PERIPHERAL)) {
-			sl_btctrl_init_adv_ext();
-		}
-		if (IS_ENABLED(CONFIG_BT_CENTRAL) || IS_ENABLED(CONFIG_BT_OBSERVER)) {
-			sl_btctrl_init_scan_ext();
-		}
+		sl_btctrl_init_adv_ext();
+		sl_btctrl_init_scan_ext();
 	}
 
-	ret = sl_btctrl_init_basic(SL_BT_CONFIG_MAX_CONNECTIONS,
-			SL_BT_CONFIG_USER_ADVERTISERS,
-			SL_BT_CONFIG_ACCEPT_LIST_SIZE);
+	ret = sl_btctrl_init_basic(MAX_CONN, CONFIG_BT_SILABS_EFR32_USER_ADVERTISERS + MAX_CONN,
+				   CONFIG_BT_SILABS_EFR32_ACCEPT_LIST_SIZE);
 	if (ret) {
 		LOG_ERR("Failed to initialize the controller %d", ret);
 		goto deinit;
 	}
 
 	sl_btctrl_configure_completed_packets_reporting(
-		SL_BT_CONTROLLER_COMPLETED_PACKETS_THRESHOLD,
-		SL_BT_CONTROLLER_COMPLETED_PACKETS_EVENTS_TIMEOUT);
+		CONFIG_BT_SILABS_EFR32_COMPLETED_PACKETS_THRESHOLD,
+		CONFIG_BT_SILABS_EFR32_COMPLETED_PACKETS_TIMEOUT);
 
 	sl_bthci_init_upper();
 	sl_btctrl_hci_parser_init_default();
-	if (IS_ENABLED(CONFIG_BT_CONN)) {
-		sl_btctrl_hci_parser_init_conn();
-	}
-	if (IS_ENABLED(CONFIG_BT_BROADCASTER) || IS_ENABLED(CONFIG_BT_PERIPHERAL)) {
-		sl_btctrl_hci_parser_init_adv();
-	}
+	sl_btctrl_hci_parser_init_conn();
+	sl_btctrl_hci_parser_init_adv();
 	sl_btctrl_hci_parser_init_phy();
 
-#ifdef CONFIG_PM
-	{
+	if (IS_ENABLED(CONFIG_BT_SILABS_EFR32_HCI_VS)) {
+		sl_bthci_init_vs();
+	}
+
+	if (IS_ENABLED(CONFIG_PM)) {
 		RAIL_ConfigSleep(BTLE_LL_GetRadioHandle(), RAIL_SLEEP_CONFIG_TIMERSYNC_ENABLED);
 		RAIL_Status_t status = RAIL_InitPowerManager();
 
@@ -240,7 +360,10 @@ static int slz_bt_open(const struct device *dev, bt_hci_recv_t recv)
 			goto deinit;
 		}
 	}
-#endif
+
+	if (IS_ENABLED(CONFIG_BT_CTLR_PRIVACY)) {
+		sl_btctrl_hci_parser_init_privacy();
+	}
 
 	hci->recv = recv;
 
diff --git a/drivers/bluetooth/hci/hci_silabs_siwx91x.c b/drivers/bluetooth/hci/hci_silabs_siwx91x.c
new file mode 100644
index 00000000000..3d40a38208a
--- /dev/null
+++ b/drivers/bluetooth/hci/hci_silabs_siwx91x.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/bluetooth.h>
+
+#define DT_DRV_COMPAT silabs_siwx91x_bt_hci
+#define LOG_LEVEL     CONFIG_BT_HCI_DRIVER_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(bt_hci_driver_siwg917);
+
+#include "rsi_ble.h"
+
+static void siwx91x_bt_resp_rcvd(uint16_t status, rsi_ble_event_rcp_rcvd_info_t *resp_buf);
+
+struct hci_data {
+	bt_hci_recv_t recv;
+	rsi_data_packet_t rsi_data_packet;
+};
+
+static int siwx91x_bt_open(const struct device *dev, bt_hci_recv_t recv)
+{
+	struct hci_data *hci = dev->data;
+	int status = rsi_ble_enhanced_gap_extended_register_callbacks(RSI_BLE_ON_RCP_EVENT,
+								      (void *)siwx91x_bt_resp_rcvd);
+
+	if (!status) {
+		hci->recv = recv;
+	}
+	return status ? -EIO : 0;
+}
+
+static int siwx91x_bt_send(const struct device *dev, struct net_buf *buf)
+{
+	struct hci_data *hci = dev->data;
+	int sc = -EOVERFLOW;
+	uint8_t packet_type = BT_HCI_H4_NONE;
+
+	switch (bt_buf_get_type(buf)) {
+	case BT_BUF_ACL_OUT:
+		packet_type = BT_HCI_H4_ACL;
+		break;
+	case BT_BUF_CMD:
+		packet_type = BT_HCI_H4_CMD;
+		break;
+	default:
+		sc = -EINVAL;
+		break;
+	}
+
+	if ((packet_type != BT_HCI_H4_NONE) && (buf->len < sizeof(hci->rsi_data_packet.data))) {
+		net_buf_push_u8(buf, packet_type);
+		memcpy(&hci->rsi_data_packet, buf->data, buf->len);
+		sc = rsi_bt_driver_send_cmd(RSI_BLE_REQ_HCI_RAW, &hci->rsi_data_packet, NULL);
+		/* TODO SILABS ZEPHYR Convert to errno. A common function from rsi/sl_status should
+		 * be introduced
+		 */
+		if (sc) {
+			LOG_ERR("BT command send failure: %d", sc);
+			sc = -EIO;
+		}
+	}
+	net_buf_unref(buf);
+	return sc;
+}
+
+static void siwx91x_bt_resp_rcvd(uint16_t status, rsi_ble_event_rcp_rcvd_info_t *resp_buf)
+{
+	const struct device *dev = DEVICE_DT_GET(DT_DRV_INST(0));
+	struct hci_data *hci = dev->data;
+	uint8_t packet_type = BT_HCI_H4_NONE;
+	size_t len = 0;
+	struct net_buf *buf = NULL;
+
+	/* TODO SILABS ZEPHYR This horror expression is from the WiseConnect from the HCI example...
+	 * No workaround have been found until now.
+	 */
+	memcpy(&packet_type, (resp_buf->data - 12), 1);
+	switch (packet_type) {
+	case BT_HCI_H4_EVT: {
+		struct bt_hci_evt_hdr *hdr = (void *)resp_buf->data;
+
+		len = hdr->len + sizeof(*hdr);
+		buf = bt_buf_get_evt(hdr->evt, false, K_FOREVER);
+		break;
+	}
+	case BT_HCI_H4_ACL: {
+		struct bt_hci_acl_hdr *hdr = (void *)resp_buf->data;
+
+		len = hdr->len + sizeof(*hdr);
+		buf = bt_buf_get_rx(BT_BUF_ACL_IN, K_FOREVER);
+		break;
+	}
+	default:
+		LOG_ERR("Unknown/Unhandled HCI type: %d", packet_type);
+		break;
+	}
+
+	if (buf && (len <= net_buf_tailroom(buf))) {
+		net_buf_add_mem(buf, resp_buf->data, len);
+		hci->recv(dev, buf);
+	}
+}
+
+static DEVICE_API(bt_hci, siwx91x_api) = {
+	.open = siwx91x_bt_open,
+	.send = siwx91x_bt_send,
+};
+
+#define HCI_DEVICE_INIT(inst)                                                                      \
+	static struct hci_data hci_data_##inst;                                                    \
+	DEVICE_DT_INST_DEFINE(inst, NULL, NULL, &hci_data_##inst, NULL, POST_KERNEL,               \
+			      CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &siwx91x_api)
+
+/* Only one instance supported right now */
+HCI_DEVICE_INIT(0)
diff --git a/drivers/bluetooth/hci/hci_spi_st.c b/drivers/bluetooth/hci/hci_spi_st.c
index 4b8e25fe43d..faa158a2ef9 100644
--- a/drivers/bluetooth/hci/hci_spi_st.c
+++ b/drivers/bluetooth/hci/hci_spi_st.c
@@ -631,7 +631,9 @@ static int bt_spi_send(const struct device *dev, struct net_buf *buf)
 	 * EVT_BLUE_INITIALIZED as an indication that it is safe to proceed.
 	 */
 	if (bt_spi_get_cmd(buf->data) == BT_HCI_OP_RESET) {
-		k_sem_take(&sem_initialised, K_FOREVER);
+		if (k_sem_take(&sem_initialised, K_SECONDS(CONFIG_BT_SPI_BOOT_TIMEOUT_SEC)) < 0) {
+			ret = -EIO;
+		}
 	}
 #endif /* DT_HAS_COMPAT_STATUS_OKAY(st_hci_spi_v1) */
 	net_buf_unref(buf);
@@ -682,7 +684,9 @@ static int bt_spi_open(const struct device *dev, bt_hci_recv_t recv)
 			0, K_NO_WAIT);
 
 	/* Device will let us know when it's ready */
-	k_sem_take(&sem_initialised, K_FOREVER);
+	if (k_sem_take(&sem_initialised, K_SECONDS(CONFIG_BT_SPI_BOOT_TIMEOUT_SEC)) < 0) {
+		return -EIO;
+	}
 
 #if defined(CONFIG_BT_HCI_RAW) && defined(CONFIG_BT_BLUENRG_ACI)
 	/* force BlueNRG to be on controller mode */
diff --git a/drivers/bluetooth/hci/ipc.c b/drivers/bluetooth/hci/ipc.c
index f7091e207c3..3bc98750161 100644
--- a/drivers/bluetooth/hci/ipc.c
+++ b/drivers/bluetooth/hci/ipc.c
@@ -10,6 +10,7 @@
 
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/drivers/bluetooth.h>
 
 #include <zephyr/device.h>
@@ -19,6 +20,9 @@
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(bt_hci_driver);
 
+BUILD_ASSERT(!IS_ENABLED(CONFIG_BT_CONN) || IS_ENABLED(CONFIG_BT_HCI_ACL_FLOW_CONTROL),
+	     "HCI IPC driver can drop ACL data without Controller-to-Host ACL flow control");
+
 #define DT_DRV_COMPAT zephyr_bt_hci_ipc
 
 #define IPC_BOUND_TIMEOUT_IN_MS K_MSEC(CONFIG_BT_HCI_IPC_ENDPOINT_BOUND_TIMEOUT_MS)
@@ -83,7 +87,7 @@ static struct net_buf *bt_ipc_evt_recv(const uint8_t *data, size_t remaining)
 	size_t buf_tailroom;
 
 	if (remaining < sizeof(hdr)) {
-		LOG_ERR("Not enough data for event header");
+		LOG_ERR("Not enough data (%u) for event header (%zu)", remaining, sizeof(hdr));
 		return NULL;
 	}
 
@@ -94,7 +98,7 @@ static struct net_buf *bt_ipc_evt_recv(const uint8_t *data, size_t remaining)
 	remaining -= sizeof(hdr);
 
 	if (remaining != hdr.len) {
-		LOG_ERR("Event payload length is not correct");
+		LOG_ERR("Event payload length is not correct (%u != %u)", remaining, hdr.len);
 		return NULL;
 	}
 	LOG_DBG("len %u", hdr.len);
@@ -131,7 +135,7 @@ static struct net_buf *bt_ipc_acl_recv(const uint8_t *data, size_t remaining)
 	size_t buf_tailroom;
 
 	if (remaining < sizeof(hdr)) {
-		LOG_ERR("Not enough data for ACL header");
+		LOG_ERR("Not enough data (%u) for ACL header (%zu)", remaining, sizeof(hdr));
 		return NULL;
 	}
 
@@ -148,7 +152,8 @@ static struct net_buf *bt_ipc_acl_recv(const uint8_t *data, size_t remaining)
 	}
 
 	if (remaining != sys_le16_to_cpu(hdr.len)) {
-		LOG_ERR("ACL payload length is not correct");
+		LOG_ERR("ACL payload length is not correct (%u != %u)", remaining,
+			sys_le16_to_cpu(hdr.len));
 		net_buf_unref(buf);
 		return NULL;
 	}
@@ -174,7 +179,7 @@ static struct net_buf *bt_ipc_iso_recv(const uint8_t *data, size_t remaining)
 	size_t buf_tailroom;
 
 	if (remaining < sizeof(hdr)) {
-		LOG_ERR("Not enough data for ISO header");
+		LOG_ERR("Not enough data (%u) for ISO header (%zu)", remaining, sizeof(hdr));
 		return NULL;
 	}
 
@@ -198,7 +203,8 @@ static struct net_buf *bt_ipc_iso_recv(const uint8_t *data, size_t remaining)
 	}
 
 	if (remaining != bt_iso_hdr_len(sys_le16_to_cpu(hdr.len))) {
-		LOG_ERR("ISO payload length is not correct");
+		LOG_ERR("ISO payload length is not correct (%u != %lu)", remaining,
+			bt_iso_hdr_len(sys_le16_to_cpu(hdr.len)));
 		net_buf_unref(buf);
 		return NULL;
 	}
diff --git a/drivers/bluetooth/hci/spi.c b/drivers/bluetooth/hci/spi.c
index 3ce62548ea0..57009c4376b 100644
--- a/drivers/bluetooth/hci/spi.c
+++ b/drivers/bluetooth/hci/spi.c
@@ -416,7 +416,9 @@ static int bt_spi_open(const struct device *dev, bt_hci_recv_t recv)
 	k_thread_name_set(&spi_rx_thread_data, "bt_spi_rx_thread");
 
 	/* Device will let us know when it's ready */
-	k_sem_take(&sem_initialised, K_FOREVER);
+	if (k_sem_take(&sem_initialised, K_SECONDS(CONFIG_BT_SPI_BOOT_TIMEOUT_SEC)) < 0) {
+		return -EIO;
+	}
 
 	return 0;
 }
diff --git a/drivers/bluetooth/hci/userchan.c b/drivers/bluetooth/hci/userchan.c
index 50c3165809d..c46647fabd0 100644
--- a/drivers/bluetooth/hci/userchan.c
+++ b/drivers/bluetooth/hci/userchan.c
@@ -14,19 +14,15 @@
 #include <errno.h>
 #include <stddef.h>
 #include <stdlib.h>
-#include <poll.h>
-#include <errno.h>
-#include <sys/socket.h>
 #include <string.h>
-#include <unistd.h>
 #include <stdio.h>
-#include <limits.h>
-#include <netinet/in.h>
-#include <arpa/inet.h>
 #include <zephyr/sys/byteorder.h>
 
+#include "nsi_host_trampolines.h"
+#include "nsi_errno.h"
 #include "soc.h"
-#include "cmdline.h" /* native_posix command line options header */
+#include "cmdline.h" /* native_sim command line options header */
+#include "userchan_bottom.h"
 
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/hci.h>
@@ -41,19 +37,8 @@ LOG_MODULE_REGISTER(bt_driver);
 struct uc_data {
 	int           fd;
 	bt_hci_recv_t recv;
-
 };
 
-#define BTPROTO_HCI      1
-struct sockaddr_hci {
-	sa_family_t     hci_family;
-	unsigned short  hci_dev;
-	unsigned short  hci_channel;
-};
-#define HCI_CHANNEL_USER 1
-
-#define SOL_HCI          0
-
 static K_KERNEL_STACK_DEFINE(rx_thread_stack,
 			     CONFIG_ARCH_POSIX_RECOMMENDED_STACK_SIZE);
 static struct k_thread rx_thread_data;
@@ -179,13 +164,6 @@ static int32_t hci_packet_complete(const uint8_t *buf, uint16_t buf_len)
 	return (int32_t)header_len + payload_len;
 }
 
-static bool uc_ready(int fd)
-{
-	struct pollfd pollfd = { .fd = fd, .events = POLLIN };
-
-	return (poll(&pollfd, 1, 0) == 1);
-}
-
 static void rx_thread(void *p1, void *p2, void *p3)
 {
 	const struct device *dev = p1;
@@ -196,32 +174,32 @@ static void rx_thread(void *p1, void *p2, void *p3)
 
 	LOG_DBG("started");
 
-	ssize_t frame_size = 0;
+	long frame_size = 0;
 
 	while (1) {
 		static uint8_t frame[512];
 		struct net_buf *buf;
 		size_t buf_tailroom;
 		size_t buf_add_len;
-		ssize_t len;
+		long len;
 		const uint8_t *frame_start = frame;
 
-		if (!uc_ready(uc->fd)) {
+		if (!user_chan_rx_ready(uc->fd)) {
 			k_sleep(K_MSEC(1));
 			continue;
 		}
 
 		LOG_DBG("calling read()");
 
-		len = read(uc->fd, frame + frame_size, sizeof(frame) - frame_size);
+		len = nsi_host_read(uc->fd, frame + frame_size, sizeof(frame) - frame_size);
 		if (len < 0) {
-			if (errno == EINTR) {
+			if (nsi_host_get_errno() == EINTR) {
 				k_yield();
 				continue;
 			}
 
 			LOG_ERR("Reading socket failed, errno %d", errno);
-			close(uc->fd);
+			(void)nsi_host_close(uc->fd);
 			uc->fd = -1;
 			return;
 		}
@@ -315,66 +293,14 @@ static int uc_send(const struct device *dev, struct net_buf *buf)
 		return -EINVAL;
 	}
 
-	if (write(uc->fd, buf->data, buf->len) < 0) {
-		return -errno;
+	if (nsi_host_write(uc->fd, buf->data, buf->len) < 0) {
+		return -nsi_host_get_errno();
 	}
 
 	net_buf_unref(buf);
 	return 0;
 }
 
-static int user_chan_open(void)
-{
-	int fd;
-
-	if (hci_socket) {
-		struct sockaddr_hci addr;
-
-		fd = socket(PF_BLUETOOTH, SOCK_RAW | SOCK_CLOEXEC | SOCK_NONBLOCK,
-			    BTPROTO_HCI);
-		if (fd < 0) {
-			return -errno;
-		}
-
-		(void)memset(&addr, 0, sizeof(addr));
-		addr.hci_family = AF_BLUETOOTH;
-		addr.hci_dev = bt_dev_index;
-		addr.hci_channel = HCI_CHANNEL_USER;
-
-		if (bind(fd, (struct sockaddr *)&addr, sizeof(addr)) < 0) {
-			int err = -errno;
-
-			close(fd);
-			return err;
-		}
-	} else {
-		struct sockaddr_in addr;
-
-		fd = socket(AF_INET, SOCK_STREAM, 0);
-		if (fd < 0) {
-			return -errno;
-		}
-
-		addr.sin_family = AF_INET;
-		addr.sin_port = htons(port);
-		if (inet_pton(AF_INET, ip_addr, &(addr.sin_addr)) <= 0) {
-			int err = -errno;
-
-			close(fd);
-			return err;
-		}
-
-		if (connect(fd, (struct sockaddr *)&addr, sizeof(addr)) < 0) {
-			int err = -errno;
-
-			close(fd);
-			return err;
-		}
-	}
-
-	return fd;
-}
-
 static int uc_open(const struct device *dev, bt_hci_recv_t recv)
 {
 	struct uc_data *uc = dev->data;
@@ -385,9 +311,13 @@ static int uc_open(const struct device *dev, bt_hci_recv_t recv)
 		LOG_DBG("hci %s:%d", ip_addr, port);
 	}
 
-	uc->fd = user_chan_open();
+	if (hci_socket) {
+		uc->fd = user_chan_socket_open(bt_dev_index);
+	} else {
+		uc->fd = user_chan_net_connect(ip_addr, port);
+	}
 	if (uc->fd < 0) {
-		return uc->fd;
+		return -nsi_errno_from_mid(-uc->fd);
 	}
 
 	uc->recv = recv;
@@ -449,9 +379,8 @@ static void cmd_bt_dev_found(char *argv, int offset)
 			posix_print_error_and_exit("Error: IP port for bluetooth "
 						   "hci tcp server is out of range.\n");
 		}
-		struct in_addr addr;
 
-		if (inet_pton(AF_INET, ip_addr, &addr) != 1) {
+		if (user_chan_is_ipaddr_ok(ip_addr) != 1) {
 			posix_print_error_and_exit("Error: IP address for bluetooth "
 						   "hci tcp server is incorrect.\n");
 		}
diff --git a/drivers/bluetooth/hci/userchan_bottom.c b/drivers/bluetooth/hci/userchan_bottom.c
new file mode 100644
index 00000000000..38b0a0b2908
--- /dev/null
+++ b/drivers/bluetooth/hci/userchan_bottom.c
@@ -0,0 +1,99 @@
+/**
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * "Bottom"/Linux/Host side of the userchannel driver. This file is built in the native_simulator
+ * runner context with the host libC, but it's functionality can be called from the "embedded" side
+ */
+
+#include <stdbool.h>
+#include <string.h>
+#include <errno.h>
+#include <poll.h>
+#include <unistd.h>
+#include <sys/socket.h>
+#include <limits.h>
+#include <netinet/in.h>
+#include <arpa/inet.h>
+#include <nsi_errno.h>
+
+#define BTPROTO_HCI      1
+#define HCI_CHANNEL_USER 1
+
+struct sockaddr_hci {
+	sa_family_t    hci_family;
+	unsigned short hci_dev;
+	unsigned short hci_channel;
+};
+
+bool user_chan_rx_ready(int fd)
+{
+	struct pollfd pollfd = {.fd = fd, .events = POLLIN};
+
+	return (poll(&pollfd, 1, 0) == 1);
+}
+
+int user_chan_is_ipaddr_ok(char ip_addr[])
+{
+	struct in_addr addr;
+
+	return inet_pton(AF_INET, ip_addr, &addr);
+}
+
+int user_chan_socket_open(unsigned short bt_dev_index)
+{
+	int fd;
+	struct sockaddr_hci addr;
+
+	fd = socket(PF_BLUETOOTH, SOCK_RAW | SOCK_CLOEXEC | SOCK_NONBLOCK, BTPROTO_HCI);
+	if (fd < 0) {
+		return -nsi_errno_to_mid(errno);
+	}
+
+	(void)memset(&addr, 0, sizeof(addr));
+	addr.hci_family = AF_BLUETOOTH;
+	addr.hci_dev = bt_dev_index;
+	addr.hci_channel = HCI_CHANNEL_USER;
+
+	if (bind(fd, (struct sockaddr *)&addr, sizeof(addr)) < 0) {
+		int err = -nsi_errno_to_mid(errno);
+
+		close(fd);
+		return err;
+	}
+
+	return fd;
+}
+
+
+int user_chan_net_connect(char ip_addr[], unsigned int port)
+{
+	int fd;
+	struct sockaddr_in addr;
+
+	fd = socket(AF_INET, SOCK_STREAM, 0);
+	if (fd < 0) {
+		return -nsi_errno_to_mid(errno);
+	}
+
+	addr.sin_family = AF_INET;
+	addr.sin_port = htons(port);
+	if (inet_pton(AF_INET, ip_addr, &(addr.sin_addr)) <= 0) {
+		int err = -nsi_errno_to_mid(errno);
+
+		close(fd);
+		return err;
+	}
+
+	if (connect(fd, (struct sockaddr *)&addr, sizeof(addr)) < 0) {
+		int err = -nsi_errno_to_mid(errno);
+
+		close(fd);
+		return err;
+	}
+
+	return fd;
+}
diff --git a/drivers/bluetooth/hci/userchan_bottom.h b/drivers/bluetooth/hci/userchan_bottom.h
new file mode 100644
index 00000000000..732f0970c2b
--- /dev/null
+++ b/drivers/bluetooth/hci/userchan_bottom.h
@@ -0,0 +1,25 @@
+/**
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef DRIVERS_BLUETOOTH_HCI_USERCHAN_BOTTOM_H
+#define DRIVERS_BLUETOOTH_HCI_USERCHAN_BOTTOM_H
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+bool user_chan_rx_ready(int fd);
+int user_chan_is_ipaddr_ok(char ip_addr[]);
+int user_chan_socket_open(unsigned short bt_dev_index);
+int user_chan_net_connect(char ip_addr[], unsigned int port);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DRIVERS_BLUETOOTH_HCI_USERCHAN_BOTTOM_H */
diff --git a/drivers/cache/CMakeLists.txt b/drivers/cache/CMakeLists.txt
index a10d98ce68f..51a1940c173 100644
--- a/drivers/cache/CMakeLists.txt
+++ b/drivers/cache/CMakeLists.txt
@@ -9,3 +9,5 @@ zephyr_library_sources_ifdef(CONFIG_CACHE_ASPEED	cache_aspeed.c)
 zephyr_library_sources_ifdef(CONFIG_CACHE_ANDES 	cache_andes.c)
 zephyr_library_sources_ifdef(CONFIG_USERSPACE		cache_handlers.c)
 zephyr_library_sources_ifdef(CONFIG_CACHE_NRF_CACHE	cache_nrf.c)
+zephyr_library_sources_ifdef(CONFIG_CACHE_NXP_XCACHE	cache_nxp_xcache.c)
+zephyr_library_sources_ifdef(CONFIG_CACHE_STM32	cache_stm32.c)
diff --git a/drivers/cache/Kconfig b/drivers/cache/Kconfig
index be3fc2ce193..eb8dfae76ca 100644
--- a/drivers/cache/Kconfig
+++ b/drivers/cache/Kconfig
@@ -21,5 +21,7 @@ comment "Device Drivers"
 source "drivers/cache/Kconfig.aspeed"
 source "drivers/cache/Kconfig.nrf"
 source "drivers/cache/Kconfig.andes"
+source "drivers/cache/Kconfig.nxp_xcache"
+source "drivers/cache/Kconfig.stm32"
 
 endif # CACHE
diff --git a/drivers/cache/Kconfig.nxp_xcache b/drivers/cache/Kconfig.nxp_xcache
new file mode 100644
index 00000000000..f9844793e30
--- /dev/null
+++ b/drivers/cache/Kconfig.nxp_xcache
@@ -0,0 +1,10 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config CACHE_NXP_XCACHE
+	bool "NXP external cache driver for xcache controller"
+	default y
+	select CACHE_HAS_DRIVER
+	depends on HAS_MCUX_XCACHE
+	help
+	  This option enables the XCACHE driver for NXP SOC's.
diff --git a/drivers/cache/Kconfig.stm32 b/drivers/cache/Kconfig.stm32
new file mode 100644
index 00000000000..6d468f98548
--- /dev/null
+++ b/drivers/cache/Kconfig.stm32
@@ -0,0 +1,24 @@
+# Copyright (c) 2025 Henrik Lindblom <henrik.lindblom@vaisala.com>
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig CACHE_STM32
+	bool "STM32 cache driver"
+	select CACHE_HAS_DRIVER
+	depends on CACHE_MANAGEMENT
+	help
+	  Enable support for the STM32 ICACHE / DCACHE peripheral present in some STM32 chips.
+
+if CACHE_STM32
+
+# "default n" for L5 is legacy - could be removed?
+config CACHE_STM32_ICACHE_DIRECT_MAPPING
+	bool "Use 1-way associative mapping for ICACHE"
+	default n if SOC_SERIES_STM32L5X
+	default y
+	help
+	  Use ICACHE in direct mapping (1-way associative) mode instead of the default n-way
+	  associative cache mode.
+
+	  This option reduces power consumption but slightly reduces cache's performance.
+
+endif # CACHE_STM32
diff --git a/drivers/cache/cache_nxp_xcache.c b/drivers/cache/cache_nxp_xcache.c
new file mode 100644
index 00000000000..59dd7ce2af6
--- /dev/null
+++ b/drivers/cache/cache_nxp_xcache.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/cache.h>
+#include <zephyr/logging/log.h>
+#include <soc.h>
+#include <fsl_cache.h>
+
+LOG_MODULE_REGISTER(cache_nxp_xcache, CONFIG_CACHE_LOG_LEVEL);
+
+#if !defined(NXP_XCACHE_INSTR)
+#define NXP_XCACHE_INSTR XCACHE_PC
+#endif
+
+#if !defined(NXP_XCACHE_DATA)
+#define NXP_XCACHE_DATA XCACHE_PS
+#endif
+
+void cache_data_enable(void)
+{
+	XCACHE_EnableCache(NXP_XCACHE_DATA);
+}
+
+void cache_data_disable(void)
+{
+	XCACHE_DisableCache(NXP_XCACHE_DATA);
+}
+
+int cache_data_flush_all(void)
+{
+	XCACHE_CleanCache(NXP_XCACHE_DATA);
+
+	return 0;
+}
+
+int cache_data_invd_all(void)
+{
+	XCACHE_InvalidateCache(NXP_XCACHE_DATA);
+
+	return 0;
+}
+
+int cache_data_flush_and_invd_all(void)
+{
+	XCACHE_CleanInvalidateCache(NXP_XCACHE_DATA);
+
+	return 0;
+}
+
+int cache_data_flush_range(void *addr, size_t size)
+{
+	XCACHE_CleanCacheByRange((uint32_t)addr, size);
+
+	return 0;
+}
+
+int cache_data_invd_range(void *addr, size_t size)
+{
+	XCACHE_InvalidateCacheByRange((uint32_t)addr, size);
+
+	return 0;
+}
+
+int cache_data_flush_and_invd_range(void *addr, size_t size)
+{
+	XCACHE_CleanInvalidateCacheByRange((uint32_t)addr, size);
+
+	return 0;
+}
+
+void cache_instr_enable(void)
+{
+	XCACHE_EnableCache(NXP_XCACHE_INSTR);
+}
+
+void cache_instr_disable(void)
+{
+	XCACHE_DisableCache(NXP_XCACHE_INSTR);
+}
+
+int cache_instr_flush_all(void)
+{
+	XCACHE_CleanCache(NXP_XCACHE_INSTR);
+
+	return 0;
+}
+
+int cache_instr_invd_all(void)
+{
+	XCACHE_InvalidateCache(NXP_XCACHE_INSTR);
+
+	return 0;
+}
+
+int cache_instr_flush_and_invd_all(void)
+{
+	XCACHE_CleanInvalidateCache(NXP_XCACHE_INSTR);
+
+	return 0;
+}
+
+int cache_instr_flush_range(void *addr, size_t size)
+{
+	XCACHE_CleanCacheByRange((uint32_t)addr, size);
+
+	return 0;
+}
+
+int cache_instr_invd_range(void *addr, size_t size)
+{
+	XCACHE_InvalidateCacheByRange((uint32_t)addr, size);
+
+	return 0;
+}
+
+int cache_instr_flush_and_invd_range(void *addr, size_t size)
+{
+	XCACHE_CleanInvalidateCacheByRange((uint32_t)addr, size);
+
+	return 0;
+}
diff --git a/drivers/cache/cache_stm32.c b/drivers/cache/cache_stm32.c
new file mode 100644
index 00000000000..8dc07c1a2c6
--- /dev/null
+++ b/drivers/cache/cache_stm32.c
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2025 Henrik Lindblom <henrik.lindblom@vaisala.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/cache.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/math_extras.h>
+#include <stm32_ll_dcache.h>
+#include <stm32_ll_icache.h>
+
+LOG_MODULE_REGISTER(cache_stm32, CONFIG_CACHE_LOG_LEVEL);
+
+#ifdef CONFIG_DCACHE
+
+void cache_data_enable(void)
+{
+	LL_DCACHE_Enable(DCACHE1);
+#if defined(DCACHE2)
+	LL_DCACHE_Enable(DCACHE2);
+#endif
+}
+
+void cache_data_disable(void)
+{
+	cache_data_flush_all();
+
+	while (LL_DCACHE_IsActiveFlag_BUSYCMD(DCACHE1)) {
+	}
+
+	LL_DCACHE_Disable(DCACHE1);
+	LL_DCACHE_ClearFlag_BSYEND(DCACHE1);
+
+#if defined(DCACHE2)
+	while (LL_DCACHE_IsActiveFlag_BUSYCMD(DCACHE2)) {
+	}
+
+	LL_DCACHE_Disable(DCACHE2);
+	LL_DCACHE_ClearFlag_BSYEND(DCACHE2);
+#endif
+}
+
+static int cache_data_manage_range(void *addr, size_t size, uint32_t command)
+{
+	/*
+	 * This is a simple approach to invalidate the range. The address might be in either DCACHE1
+	 * or DCACHE2 (if present). The cache invalidation algorithm checks the TAG memory for the
+	 * specified address range so there's little harm in just checking both caches.
+	 */
+	uint32_t start = (uint32_t)addr;
+	uint32_t end;
+
+	if (u32_add_overflow(start, size, &end)) {
+		return -EOVERFLOW;
+	}
+
+	LL_DCACHE_SetStartAddress(DCACHE1, start);
+	LL_DCACHE_SetEndAddress(DCACHE1, end);
+	LL_DCACHE_SetCommand(DCACHE1, command);
+	LL_DCACHE_StartCommand(DCACHE1);
+#if defined(DCACHE2)
+	LL_DCACHE_SetStartAddress(DCACHE2, start);
+	LL_DCACHE_SetEndAddress(DCACHE2, end);
+	LL_DCACHE_SetCommand(DCACHE2, command);
+	LL_DCACHE_StartCommand(DCACHE2);
+#endif
+	return 0;
+}
+
+int cache_data_flush_range(void *addr, size_t size)
+{
+	return cache_data_manage_range(addr, size, LL_DCACHE_COMMAND_CLEAN_BY_ADDR);
+}
+
+int cache_data_invd_range(void *addr, size_t size)
+{
+	return cache_data_manage_range(addr, size, LL_DCACHE_COMMAND_INVALIDATE_BY_ADDR);
+}
+
+int cache_data_flush_and_invd_range(void *addr, size_t size)
+{
+	return cache_data_manage_range(addr, size, LL_DCACHE_COMMAND_CLEAN_INVALIDATE_BY_ADDR);
+}
+
+int cache_data_flush_all(void)
+{
+	return cache_data_flush_range(0, UINT32_MAX);
+}
+
+int cache_data_invd_all(void)
+{
+	LL_DCACHE_Invalidate(DCACHE1);
+#if defined(DCACHE2)
+	LL_DCACHE_Invalidate(DCACHE2);
+#endif
+	return 0;
+}
+
+int cache_data_flush_and_invd_all(void)
+{
+	return cache_data_flush_and_invd_range(0, UINT32_MAX);
+}
+
+#endif /* CONFIG_DCACHE */
+
+static inline void wait_for_icache(void)
+{
+	while (LL_ICACHE_IsActiveFlag_BUSY()) {
+	}
+
+	/* Clear BSYEND to avoid an extra interrupt if somebody enables them. */
+	LL_ICACHE_ClearFlag_BSYEND();
+}
+
+void cache_instr_enable(void)
+{
+	if (IS_ENABLED(CONFIG_CACHE_STM32_ICACHE_DIRECT_MAPPING)) {
+		LL_ICACHE_SetMode(LL_ICACHE_1WAY);
+	}
+
+	/*
+	 * Need to wait until any pending cache invalidation operations finish. This is recommended
+	 * in the reference manual to ensure execution timing determinism.
+	 */
+	wait_for_icache();
+	LL_ICACHE_Enable();
+}
+
+void cache_instr_disable(void)
+{
+	LL_ICACHE_Disable();
+
+	while (LL_ICACHE_IsEnabled()) {
+		/**
+		 * Wait until the ICACHE is disabled (CR.EN=0), at which point
+		 * all requests bypass the cache and are forwarded directly
+		 * from the ICACHE slave port to the ICACHE master port(s).
+		 *
+		 * The cache invalidation will start once disabled, but we allow
+		 * it to proceed in the background since it doesn't need to be
+		 * complete for requests to bypass the ICACHE.
+		 */
+	}
+}
+
+int cache_instr_flush_all(void)
+{
+	return -ENOTSUP;
+}
+
+int cache_instr_invd_all(void)
+{
+	LL_ICACHE_Invalidate();
+	return 0;
+}
+
+int cache_instr_flush_and_invd_all(void)
+{
+	return -ENOTSUP;
+}
+
+int cache_instr_flush_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+	return -ENOTSUP;
+}
+
+int cache_instr_invd_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+	return -ENOTSUP;
+}
+
+int cache_instr_flush_and_invd_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+	return -ENOTSUP;
+}
diff --git a/drivers/can/CMakeLists.txt b/drivers/can/CMakeLists.txt
index 1398309e914..c84884df8b5 100644
--- a/drivers/can/CMakeLists.txt
+++ b/drivers/can/CMakeLists.txt
@@ -3,33 +3,39 @@
 zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/can.h)
 
 zephyr_library()
-zephyr_sources_ifdef(CONFIG_CAN_MCUX_MCAN    can_mcux_mcan.c)
 
+# CAN subsystem common files
+# zephyr-keep-sorted-start
 zephyr_library_sources_ifdef(CONFIG_CAN                     can_common.c)
+zephyr_library_sources_ifdef(CONFIG_CAN_SHELL               can_shell.c)
+zephyr_library_sources_ifdef(CONFIG_USERSPACE               can_handlers.c)
+# zephyr-keep-sorted-stop
+
+# CAN subsystem driver files
+# zephyr-keep-sorted-start
+zephyr_library_sources_ifdef(CONFIG_CAN_ESP32_TWAI          can_esp32_twai.c)
 zephyr_library_sources_ifdef(CONFIG_CAN_FAKE                can_fake.c)
+zephyr_library_sources_ifdef(CONFIG_CAN_KVASER_PCI          can_kvaser_pci.c)
 zephyr_library_sources_ifdef(CONFIG_CAN_LOOPBACK            can_loopback.c)
 zephyr_library_sources_ifdef(CONFIG_CAN_MCAN                can_mcan.c)
 zephyr_library_sources_ifdef(CONFIG_CAN_MCP2515             can_mcp2515.c)
 zephyr_library_sources_ifdef(CONFIG_CAN_MCP251XFD           can_mcp251xfd.c)
 zephyr_library_sources_ifdef(CONFIG_CAN_MCUX_FLEXCAN        can_mcux_flexcan.c)
+zephyr_library_sources_ifdef(CONFIG_CAN_MCUX_MCAN           can_mcux_mcan.c)
+zephyr_library_sources_ifdef(CONFIG_CAN_NRF                 can_nrf.c)
+zephyr_library_sources_ifdef(CONFIG_CAN_NUMAKER             can_numaker.c)
+zephyr_library_sources_ifdef(CONFIG_CAN_NXP_S32_CANXL       can_nxp_s32_canxl.c)
+zephyr_library_sources_ifdef(CONFIG_CAN_RCAR                can_rcar.c)
+zephyr_library_sources_ifdef(CONFIG_CAN_RENESAS_RA_CANFD    can_renesas_ra.c)
 zephyr_library_sources_ifdef(CONFIG_CAN_SAM                 can_sam.c)
 zephyr_library_sources_ifdef(CONFIG_CAN_SAM0                can_sam0.c)
+zephyr_library_sources_ifdef(CONFIG_CAN_SJA1000             can_sja1000.c)
+zephyr_library_sources_ifdef(CONFIG_CAN_STM32H7_FDCAN       can_stm32h7_fdcan.c)
 zephyr_library_sources_ifdef(CONFIG_CAN_STM32_BXCAN         can_stm32_bxcan.c)
 zephyr_library_sources_ifdef(CONFIG_CAN_STM32_FDCAN         can_stm32_fdcan.c)
-zephyr_library_sources_ifdef(CONFIG_CAN_STM32H7_FDCAN       can_stm32h7_fdcan.c)
 zephyr_library_sources_ifdef(CONFIG_CAN_TCAN4X5X            can_tcan4x5x.c)
-zephyr_library_sources_ifdef(CONFIG_CAN_RCAR                can_rcar.c)
-zephyr_library_sources_ifdef(CONFIG_CAN_NUMAKER             can_numaker.c)
 zephyr_library_sources_ifdef(CONFIG_CAN_XMC4XXX             can_xmc4xxx.c)
-zephyr_library_sources_ifdef(CONFIG_CAN_SJA1000             can_sja1000.c)
-zephyr_library_sources_ifdef(CONFIG_CAN_ESP32_TWAI          can_esp32_twai.c)
-zephyr_library_sources_ifdef(CONFIG_CAN_KVASER_PCI          can_kvaser_pci.c)
-zephyr_library_sources_ifdef(CONFIG_CAN_NRF                 can_nrf.c)
-zephyr_library_sources_ifdef(CONFIG_CAN_RENESAS_RA_CANFD    can_renesas_ra.c)
-
-zephyr_library_sources_ifdef(CONFIG_USERSPACE        can_handlers.c)
-zephyr_library_sources_ifdef(CONFIG_CAN_SHELL        can_shell.c)
-zephyr_library_sources_ifdef(CONFIG_CAN_NXP_S32_CANXL    can_nxp_s32_canxl.c)
+# zephyr-keep-sorted-stop
 
 if(CONFIG_CAN_NATIVE_LINUX)
   if(${CMAKE_HOST_SYSTEM_NAME} STREQUAL Linux)
diff --git a/drivers/can/Kconfig.stm32 b/drivers/can/Kconfig.stm32
index 65da04a7225..7a9bfae3a73 100644
--- a/drivers/can/Kconfig.stm32
+++ b/drivers/can/Kconfig.stm32
@@ -54,7 +54,6 @@ config CAN_STM32_FDCAN
 	depends on DT_HAS_ST_STM32_FDCAN_ENABLED
 	select CAN_MCAN
 	select PINCTRL
-	select USE_STM32_LL_RCC
 
 if CAN_STM32_FDCAN
 
@@ -82,4 +81,3 @@ config CAN_STM32H7_FDCAN
 	depends on DT_HAS_ST_STM32H7_FDCAN_ENABLED
 	select CAN_MCAN
 	select PINCTRL
-	select USE_STM32_LL_RCC
diff --git a/drivers/can/can_mcp251xfd.c b/drivers/can/can_mcp251xfd.c
index 19dc618e3c2..3335eceb276 100644
--- a/drivers/can/can_mcp251xfd.c
+++ b/drivers/can/can_mcp251xfd.c
@@ -1394,6 +1394,12 @@ static inline int mcp251xfd_init_iocon_reg(const struct device *dev)
 		tmp |= MCP251XFD_REG_IOCON_SOF;
 	}
 
+	if (dev_cfg->xstby_enable) {
+		tmp &= ~MCP251XFD_REG_IOCON_TRIS0;
+		tmp &= ~MCP251XFD_REG_IOCON_PM0;
+		tmp |= MCP251XFD_REG_IOCON_XSTBYEN;
+	}
+
 	*reg = sys_cpu_to_le32(tmp);
 
 	return  mcp251xfd_write(dev, MCP251XFD_REG_IOCON, MCP251XFD_REG_SIZE);
@@ -1749,6 +1755,7 @@ static DEVICE_API(can, mcp251xfd_api_funcs) = {
 		.int_gpio_dt = GPIO_DT_SPEC_INST_GET(inst, int_gpios),                             \
                                                                                                    \
 		.sof_on_clko = DT_INST_PROP(inst, sof_on_clko),                                    \
+		.xstby_enable = DT_INST_PROP(inst, xstby_enable),                                  \
 		.clko_div = DT_INST_ENUM_IDX(inst, clko_div),                                      \
 		.pll_enable = DT_INST_PROP(inst, pll_enable),                                      \
 		.timestamp_prescaler = DT_INST_PROP(inst, timestamp_prescaler),                    \
diff --git a/drivers/can/can_mcp251xfd.h b/drivers/can/can_mcp251xfd.h
index 249631b33d3..43920796856 100644
--- a/drivers/can/can_mcp251xfd.h
+++ b/drivers/can/can_mcp251xfd.h
@@ -524,6 +524,7 @@ struct mcp251xfd_config {
 
 	/* IO Config */
 	bool sof_on_clko;
+	bool xstby_enable;
 	bool pll_enable;
 	uint8_t clko_div;
 
diff --git a/drivers/can/can_native_linux_adapt.h b/drivers/can/can_native_linux_adapt.h
index 6ad06f6a879..b92a7a08e7d 100644
--- a/drivers/can/can_native_linux_adapt.h
+++ b/drivers/can/can_native_linux_adapt.h
@@ -5,7 +5,7 @@
  */
 
 /** @file
- * @brief Private functions for native posix canbus driver.
+ * @brief Private functions for native_linux canbus driver.
  */
 
 #ifndef ZEPHYR_DRIVERS_CAN_NATIVE_LINUX_ADAPT_H_
diff --git a/drivers/can/can_nrf.c b/drivers/can/can_nrf.c
index b4e6dbd49be..c538291ecb4 100644
--- a/drivers/can/can_nrf.c
+++ b/drivers/can/can_nrf.c
@@ -13,9 +13,14 @@
 #include <zephyr/drivers/can.h>
 #include <zephyr/drivers/can/can_mcan.h>
 #include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/nrf_clock_control.h>
 #include <zephyr/drivers/pinctrl.h>
 #include <zephyr/irq.h>
 
+#ifdef CONFIG_SOC_NRF54H20_GPD
+#include <nrf/gpd.h>
+#endif
+
 /* nRF CAN wrapper offsets */
 #define CAN_TASKS_START	  offsetof(NRF_CAN_Type, TASKS_START)
 #define CAN_EVENTS_CORE_0 offsetof(NRF_CAN_Type, EVENTS_CORE[0])
@@ -27,7 +32,8 @@ struct can_nrf_config {
 	uint32_t mcan;
 	uint32_t mrba;
 	uint32_t mram;
-	const struct device *clock;
+	const struct device *auxpll;
+	const struct device *hsfll;
 	const struct pinctrl_dev_config *pcfg;
 	void (*irq_configure)(void);
 	uint16_t irq;
@@ -54,7 +60,7 @@ static int can_nrf_get_core_clock(const struct device *dev, uint32_t *rate)
 	const struct can_mcan_config *mcan_config = dev->config;
 	const struct can_nrf_config *config = mcan_config->custom;
 
-	return clock_control_get_rate(config->clock, NULL, rate);
+	return clock_control_get_rate(config->auxpll, NULL, rate);
 }
 
 static DEVICE_API(can, can_nrf_api) = {
@@ -131,17 +137,41 @@ static const struct can_mcan_ops can_mcan_nrf_ops = {
 	.clear_mram = can_nrf_clear_mram,
 };
 
+static int configure_hsfll(const struct device *dev, bool on)
+{
+	const struct can_mcan_config *mcan_config = dev->config;
+	const struct can_nrf_config *config = mcan_config->custom;
+	struct nrf_clock_spec spec = { 0 };
+
+	/* If CAN is on, HSFLL frequency >= AUXPLL frequency */
+	if (on) {
+		int ret;
+
+		ret = clock_control_get_rate(dev, NULL, &spec.frequency);
+		if (ret < 0) {
+			return ret;
+		}
+	}
+
+	return nrf_clock_control_request_sync(config->hsfll, &spec, K_FOREVER);
+}
+
 static int can_nrf_init(const struct device *dev)
 {
 	const struct can_mcan_config *mcan_config = dev->config;
 	const struct can_nrf_config *config = mcan_config->custom;
 	int ret;
 
-	if (!device_is_ready(config->clock)) {
+	if (!device_is_ready(config->auxpll) || !device_is_ready(config->hsfll)) {
 		return -ENODEV;
 	}
 
-	ret = clock_control_on(config->clock, NULL);
+	ret = configure_hsfll(dev, true);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = clock_control_on(config->auxpll, NULL);
 	if (ret < 0) {
 		return ret;
 	}
@@ -151,11 +181,19 @@ static int can_nrf_init(const struct device *dev)
 		return ret;
 	}
 
+
 	sys_write32(0U, config->wrapper + CAN_EVENTS_CORE_0);
 	sys_write32(0U, config->wrapper + CAN_EVENTS_CORE_1);
 	sys_write32(CAN_INTEN_CORE0_Msk | CAN_INTEN_CORE1_Msk, config->wrapper + CAN_INTEN);
 	sys_write32(1U, config->wrapper + CAN_TASKS_START);
 
+#ifdef CONFIG_SOC_NRF54H20_GPD
+	ret = nrf_gpd_retain_pins_set(config->pcfg, false);
+	if (ret < 0) {
+		return ret;
+	}
+#endif
+
 	config->irq_configure();
 
 	ret = can_mcan_configure_mram(dev, config->mrba, config->mram);
@@ -186,8 +224,9 @@ static int can_nrf_init(const struct device *dev)
 		.mcan = CAN_MCAN_DT_INST_MCAN_ADDR(n),                                             \
 		.mrba = CAN_MCAN_DT_INST_MRBA(n),                                                  \
 		.mram = CAN_MCAN_DT_INST_MRAM_ADDR(n),                                             \
-		.clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),                                    \
+		.auxpll = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_NAME(n, auxpll)),                   \
 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                         \
+		.hsfll = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_NAME(n, hsfll)),                     \
 		.irq = DT_INST_IRQN(n),                                                            \
 		.irq_configure = can_nrf_irq_configure##n,                                         \
 	};                                                                                         \
diff --git a/drivers/can/can_renesas_ra.c b/drivers/can/can_renesas_ra.c
index 8a4239275e6..c7fcf712325 100644
--- a/drivers/can/can_renesas_ra.c
+++ b/drivers/can/can_renesas_ra.c
@@ -88,7 +88,7 @@ LOG_MODULE_REGISTER(can_renesas_ra, CONFIG_CAN_LOG_LEVEL);
 #define CANFD_CFG_GLOBAL                                                                           \
 	((0U << R_CANFD_CFDGCFG_TPRI_Pos) | /* Transmission Priority: ID priority */               \
 	 (0U << R_CANFD_CFDGCFG_DCE_Pos) |  /* DLC check disabled */                               \
-	 (1U << R_CANFD_CFDGCFG_DCS_Pos))   /* DLL Clock Select: CANFDCLK */
+	 (0U << R_CANFD_CFDGCFG_DCS_Pos))   /* DLL Clock Select: CANFDCLK */
 
 /*
  * TX Message Buffer Interrupt Enable Configuration: refer to '34.2.43 CFDTMIEC : TX Message Buffer
@@ -142,6 +142,8 @@ struct can_renesas_ra_global_cfg {
 	const struct device *ram_clk;
 	const struct clock_control_ra_subsys_cfg op_subsys;
 	const struct clock_control_ra_subsys_cfg ram_subsys;
+	const unsigned int dll_min_freq;
+	const unsigned int dll_max_freq;
 };
 
 struct can_renesas_ra_filter {
@@ -902,19 +904,33 @@ static inline int can_renesas_module_clock_init(const struct device *dev)
 		return ret;
 	}
 
+	if (dll_rate < global_cfg->dll_min_freq || dll_rate > global_cfg->dll_max_freq) {
+		LOG_ERR("%s frequency is out of supported range: %d < %s freq < %d",
+			cfg->dll_clk->name, global_cfg->dll_min_freq, cfg->dll_clk->name,
+			global_cfg->dll_max_freq);
+		return -ENOTSUP;
+	}
+
 	/* Clock constraint: refer to '34.1.2 Clock restriction' - RA8M1 MCU group HWM */
 	/*
 	 * Operation clock rate must be at least 40Mhz in case CANFD mode.
 	 * Otherwise, it must be at least 32MHz.
 	 */
-	if (IS_ENABLED(CONFIG_CAN_FD_MODE) ? op_rate < 40000000 : op_rate < 32000000) {
+	if (IS_ENABLED(CONFIG_CAN_FD_MODE) ? op_rate < MHZ(40) : op_rate < MHZ(32)) {
+		LOG_ERR("%s frequency should be at least %d", global_cfg->op_clk->name,
+			IS_ENABLED(CONFIG_CAN_FD_MODE) ? MHZ(40) : MHZ(32));
 		return -ENOTSUP;
 	}
+
 	/*
 	 * (RAM clock rate / 2) >= DLL rate
 	 * (CANFD operation clock rate) >= DLL rate
 	 */
 	if ((ram_rate / 2) < dll_rate || op_rate < dll_rate) {
+		LOG_ERR("%s frequency should be less than half of %s and %s frequency should "
+			"be less than %s",
+			global_cfg->ram_clk->name, cfg->dll_clk->name, global_cfg->op_clk->name,
+			cfg->dll_clk->name);
 		return -ENOTSUP;
 	}
 
@@ -995,15 +1011,13 @@ static DEVICE_API(can, can_renesas_ra_driver_api) = {
 };
 
 #define CAN_RENESAS_RA_GLOBAL_IRQ_INIT()                                                           \
-	R_ICU->IELSR_b[VECTOR_NUMBER_CAN_GLERR].IELS = ELC_EVENT_CAN_GLERR;                        \
-	R_ICU->IELSR_b[VECTOR_NUMBER_CAN_RXF].IELS = ELC_EVENT_CAN_RXF;                            \
+	R_ICU->IELSR_b[VECTOR_NUMBER_CAN_GLERR].IELS = BSP_PRV_IELS_ENUM(EVENT_CAN_GLERR);         \
+	R_ICU->IELSR_b[VECTOR_NUMBER_CAN_RXF].IELS = BSP_PRV_IELS_ENUM(EVENT_CAN_RXF);             \
 	IRQ_CONNECT(VECTOR_NUMBER_CAN_GLERR,                                                       \
-		    DT_IRQ_BY_NAME(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), glerr,  \
-				   priority),                                                      \
+		    DT_IRQ_BY_NAME(DT_INST(0, renesas_ra_canfd_global), glerr, priority),          \
 		    canfd_error_isr, NULL, 0);                                                     \
 	IRQ_CONNECT(VECTOR_NUMBER_CAN_RXF,                                                         \
-		    DT_IRQ_BY_NAME(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), rxf,    \
-				   priority),                                                      \
+		    DT_IRQ_BY_NAME(DT_INST(0, renesas_ra_canfd_global), rxf, priority),            \
 		    canfd_rx_fifo_isr, NULL, 0);                                                   \
 	irq_enable(VECTOR_NUMBER_CAN_RXF);                                                         \
 	irq_enable(VECTOR_NUMBER_CAN_GLERR);
@@ -1012,30 +1026,26 @@ static canfd_global_cfg_t g_canfd_global_cfg = {
 	.global_interrupts = CANFD_CFG_GLERR_IRQ,
 	.global_config = CANFD_CFG_GLOBAL,
 	.rx_mb_config = CANFD_CFG_RXMB,
-	.global_err_ipl = DT_IRQ_BY_NAME(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global),
-					 glerr, priority),
-	.rx_fifo_ipl = DT_IRQ_BY_NAME(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), rxf,
-				      priority),
+	.global_err_ipl = DT_IRQ_BY_NAME(DT_INST(0, renesas_ra_canfd_global), glerr, priority),
+	.rx_fifo_ipl = DT_IRQ_BY_NAME(DT_INST(0, renesas_ra_canfd_global), rxf, priority),
 	.rx_fifo_config = CANFD_CFG_RXFIFO,
 	.common_fifo_config = CANFD_CFG_COMMONFIFO,
 };
 
 static const struct can_renesas_ra_global_cfg g_can_renesas_ra_global_cfg = {
-	.op_clk = DEVICE_DT_GET(DT_CLOCKS_CTLR_BY_NAME(
-		DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), opclk)),
-	.ram_clk = DEVICE_DT_GET(DT_CLOCKS_CTLR_BY_NAME(
-		DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), ramclk)),
-	.op_subsys = {.mstp = DT_CLOCKS_CELL_BY_NAME(
-			      DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), opclk, mstp),
-		      .stop_bit = DT_CLOCKS_CELL_BY_NAME(
-			      DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), opclk,
-			      stop_bit)},
-	.ram_subsys = {.mstp = DT_CLOCKS_CELL_BY_NAME(
-			       DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), ramclk,
-			       mstp),
-		       .stop_bit = DT_CLOCKS_CELL_BY_NAME(
-			       DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), ramclk,
-			       stop_bit)},
+	.op_clk = DEVICE_DT_GET(DT_CLOCKS_CTLR_BY_NAME(DT_INST(0, renesas_ra_canfd_global), opclk)),
+	.ram_clk =
+		DEVICE_DT_GET(DT_CLOCKS_CTLR_BY_NAME(DT_INST(0, renesas_ra_canfd_global), ramclk)),
+	.op_subsys = {.mstp = DT_CLOCKS_CELL_BY_NAME(DT_INST(0, renesas_ra_canfd_global), opclk,
+						     mstp),
+		      .stop_bit = DT_CLOCKS_CELL_BY_NAME(DT_INST(0, renesas_ra_canfd_global), opclk,
+							 stop_bit)},
+	.ram_subsys = {.mstp = DT_CLOCKS_CELL_BY_NAME(DT_INST(0, renesas_ra_canfd_global), ramclk,
+						      mstp),
+		       .stop_bit = DT_CLOCKS_CELL_BY_NAME(DT_INST(0, renesas_ra_canfd_global),
+							  ramclk, stop_bit)},
+	.dll_min_freq = DT_PROP_OR(DT_INST(0, renesas_ra_canfd_global), dll_min_freq, 0),
+	.dll_max_freq = DT_PROP_OR(DT_INST(0, renesas_ra_canfd_global), dll_max_freq, UINT_MAX),
 };
 
 static int can_renesas_ra_global_init(const struct device *dev)
@@ -1064,22 +1074,18 @@ DEVICE_DT_DEFINE(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_canfd_global), can_ren
 		 NULL, NULL, &g_can_renesas_ra_global_cfg, PRE_KERNEL_2, CONFIG_CAN_INIT_PRIORITY,
 		 NULL)
 
-#define _ELC_EVENT_CAN_COMFRX(channel) ELC_EVENT_CAN##channel##_COMFRX
-#define _ELC_EVENT_CAN_TX(channel)     ELC_EVENT_CAN##channel##_TX
-#define _ELC_EVENT_CAN_CHERR(channel)  ELC_EVENT_CAN##channel##_CHERR
-
-#define ELC_EVENT_CAN_COMFRX(channel) _ELC_EVENT_CAN_COMFRX(channel)
-#define ELC_EVENT_CAN_TX(channel)     _ELC_EVENT_CAN_TX(channel)
-#define ELC_EVENT_CAN_CHERR(channel)  _ELC_EVENT_CAN_CHERR(channel)
+#define EVENT_CAN_COMFRX(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_CAN, channel, _COMFRX))
+#define EVENT_CAN_TX(channel)     BSP_PRV_IELS_ENUM(CONCAT(EVENT_CAN, channel, _TX))
+#define EVENT_CAN_CHERR(channel)  BSP_PRV_IELS_ENUM(CONCAT(EVENT_CAN, channel, _CHERR))
 
 #define CAN_RENESAS_RA_CHANNEL_IRQ_INIT(index)                                                     \
 	{                                                                                          \
 		R_ICU->IELSR_b[DT_INST_IRQ_BY_NAME(index, rx, irq)].IELS =                         \
-			ELC_EVENT_CAN_COMFRX(DT_INST_PROP(index, channel));                        \
+			EVENT_CAN_COMFRX(DT_INST_PROP(index, channel));                            \
 		R_ICU->IELSR_b[DT_INST_IRQ_BY_NAME(index, tx, irq)].IELS =                         \
-			ELC_EVENT_CAN_TX(DT_INST_PROP(index, channel));                            \
+			EVENT_CAN_TX(DT_INST_PROP(index, channel));                                \
 		R_ICU->IELSR_b[DT_INST_IRQ_BY_NAME(index, err, irq)].IELS =                        \
-			ELC_EVENT_CAN_CHERR(DT_INST_PROP(index, channel));                         \
+			EVENT_CAN_CHERR(DT_INST_PROP(index, channel));                             \
                                                                                                    \
 		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, rx, irq),                                   \
 			    DT_INST_IRQ_BY_NAME(index, rx, priority), canfd_common_fifo_rx_isr,    \
diff --git a/drivers/can/can_sam0.c b/drivers/can/can_sam0.c
index 74532748e2e..4680fc63a71 100644
--- a/drivers/can/can_sam0.c
+++ b/drivers/can/can_sam0.c
@@ -3,6 +3,7 @@
  * Copyright (c) 2021 Alexander Wachter
  * Copyright (c) 2022 Kamil Serwus
  * Copyright (c) 2023 Sebastian Schlupp
+ * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,6 +18,8 @@
 
 LOG_MODULE_REGISTER(can_sam0, CONFIG_CAN_LOG_LEVEL);
 
+/* clang-format off */
+
 #define DT_DRV_COMPAT atmel_sam0_can
 
 struct can_sam0_config {
@@ -26,7 +29,8 @@ struct can_sam0_config {
 	const struct pinctrl_dev_config *pcfg;
 	volatile uint32_t *mclk;
 	uint32_t mclk_mask;
-	uint16_t gclk_core_id;
+	uint32_t gclk_gen;
+	uint16_t gclk_id;
 	int divider;
 };
 
@@ -109,6 +113,11 @@ static int can_sam0_get_core_clock(const struct device *dev, uint32_t *rate)
 
 static void can_sam0_clock_enable(const struct can_sam0_config *cfg)
 {
+	*cfg->mclk |= cfg->mclk_mask;
+
+	GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_CHEN
+					| GCLK_PCHCTRL_GEN(cfg->gclk_gen);
+
 	/* Enable the GLCK7 with DIV*/
 #if defined(CONFIG_SOC_SERIES_SAME51) || defined(CONFIG_SOC_SERIES_SAME54)
 	/*DFFL has to be used as clock source for the ATSAME51/54 family of SoCs*/
@@ -121,13 +130,6 @@ static void can_sam0_clock_enable(const struct can_sam0_config *cfg)
 			     | GCLK_GENCTRL_DIV(cfg->divider)
 			     | GCLK_GENCTRL_GENEN;
 #endif
-
-	/* Route channel */
-	GCLK->PCHCTRL[cfg->gclk_core_id].reg = GCLK_PCHCTRL_GEN_GCLK7
-					     | GCLK_PCHCTRL_CHEN;
-
-	/* Enable CAN clock in MCLK */
-	*cfg->mclk |= cfg->mclk_mask;
 }
 
 static int can_sam0_init(const struct device *dev)
@@ -204,6 +206,9 @@ static void config_can_##inst##_irq(void)						\
 	irq_enable(DT_INST_IRQ_BY_NAME(inst, int0, irq));				\
 }
 
+#define ASSIGNED_CLOCKS_CELL_BY_NAME							\
+	ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_NAME
+
 #define CAN_SAM0_CFG_INST(inst)								\
 	CAN_MCAN_DT_INST_CALLBACKS_DEFINE(inst, can_sam0_cbs_##inst);			\
 	CAN_MCAN_DT_INST_MRAM_DEFINE(inst, can_sam0_mram_##inst);			\
@@ -211,9 +216,10 @@ static void config_can_##inst##_irq(void)						\
 	static const struct can_sam0_config can_sam0_cfg_##inst = {			\
 		.base = CAN_MCAN_DT_INST_MCAN_ADDR(inst),				\
 		.mram = (mem_addr_t)POINTER_TO_UINT(&can_sam0_mram_##inst),		\
-		.mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(inst),		\
-		.mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(inst, mclk, bit)),		\
-		.gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, periph_ch),	\
+		.gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(inst, gclk, gen),		\
+		.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, id),			\
+		.mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(inst),		\
+		.mclk_mask = ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(inst, bit),		\
 		.divider = DT_INST_PROP(inst, divider),					\
 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),				\
 		.config_irq = config_can_##inst##_irq,					\
@@ -243,3 +249,5 @@ static void config_can_##inst##_irq(void)						\
 	CAN_SAM0_DEVICE_INST(inst)
 
 DT_INST_FOREACH_STATUS_OKAY(CAN_SAM0_INST)
+
+/* clang-format on */
diff --git a/drivers/can/can_shell.c b/drivers/can/can_shell.c
index 9b8ebef0917..eb257f027ef 100644
--- a/drivers/can/can_shell.c
+++ b/drivers/can/can_shell.c
@@ -1031,7 +1031,7 @@ static void cmd_can_mode(size_t idx, struct shell_static_entry *entry)
 
 static void cmd_can_device_name_mode(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_lookup(idx, NULL);
+	const struct device *dev = shell_device_filter(idx, can_device_check);
 
 	entry->syntax = (dev != NULL) ? dev->name : NULL;
 	entry->handler = NULL;
diff --git a/drivers/can/can_stm32_bxcan.c b/drivers/can/can_stm32_bxcan.c
index cdbd3f96e1e..66d15beda9a 100644
--- a/drivers/can/can_stm32_bxcan.c
+++ b/drivers/can/can_stm32_bxcan.c
@@ -599,7 +599,6 @@ static int can_stm32_init(const struct device *dev)
 	CAN_TypeDef *can = cfg->can;
 	struct can_timing timing = { 0 };
 	const struct device *clock;
-	uint32_t bank_offset;
 	int ret;
 
 	k_mutex_init(&filter_mutex);
@@ -645,10 +644,19 @@ static int can_stm32_init(const struct device *dev)
 	}
 
 	/* configure scale of filter banks < CONFIG_CAN_MAX_EXT_ID_FILTER for ext ids */
-	bank_offset = (cfg->can == cfg->master_can) ? 0 : CAN_STM32_NUM_FILTER_BANKS;
-	cfg->master_can->FMR |= CAN_FMR_FINIT;
-	cfg->master_can->FS1R |= ((1U << CONFIG_CAN_MAX_EXT_ID_FILTER) - 1) << bank_offset;
-	cfg->master_can->FMR &= ~CAN_FMR_FINIT;
+	/* We have to have set filters after initializing master CAN */
+	if (cfg->can == cfg->master_can) {
+		cfg->master_can->FMR |= CAN_FMR_FINIT;
+		cfg->master_can->FS1R |= ((1U << CONFIG_CAN_MAX_EXT_ID_FILTER) - 1);
+
+#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 1
+		/* reserve ext_id filters on slave CAN device */
+		cfg->master_can->FS1R |= ((1U << CONFIG_CAN_MAX_EXT_ID_FILTER) - 1)
+					 << CAN_STM32_NUM_FILTER_BANKS;
+#endif /* DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 1 */
+
+		cfg->master_can->FMR &= ~CAN_FMR_FINIT;
+	}
 
 	can->MCR &= ~CAN_MCR_TTCM & ~CAN_MCR_ABOM & ~CAN_MCR_AWUM &
 		    ~CAN_MCR_NART & ~CAN_MCR_RFLM & ~CAN_MCR_TXFP;
diff --git a/drivers/can/can_stm32_fdcan.c b/drivers/can/can_stm32_fdcan.c
index 44605a3237a..ebed4c6939b 100644
--- a/drivers/can/can_stm32_fdcan.c
+++ b/drivers/can/can_stm32_fdcan.c
@@ -13,7 +13,6 @@
 #include <zephyr/kernel.h>
 #include <zephyr/sys/__assert.h>
 #include <soc.h>
-#include <stm32_ll_rcc.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/irq.h>
 
@@ -403,13 +402,30 @@ static int can_stm32fd_clear_mram(const struct device *dev, uint16_t offset, siz
 
 static int can_stm32fd_get_core_clock(const struct device *dev, uint32_t *rate)
 {
-	const uint32_t rate_tmp = LL_RCC_GetFDCANClockFreq(LL_RCC_FDCAN_CLKSOURCE);
+	uint32_t rate_tmp;
+	const struct can_mcan_config *mcan_cfg = dev->config;
+	const struct can_stm32fd_config *stm32fd_cfg = mcan_cfg->custom;
+	const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
 
 	ARG_UNUSED(dev);
+	if (!device_is_ready(clk)) {
+		return -ENODEV;
+	}
 
-	if (rate_tmp == LL_RCC_PERIPH_FREQUENCY_NO) {
-		LOG_ERR("Can't read core clock");
-		return -EIO;
+	if (IS_ENABLED(STM32_CANFD_DOMAIN_CLOCK_SUPPORT) && (stm32fd_cfg->pclk_len > 1)) {
+		if (clock_control_get_rate(clk,
+			 (clock_control_subsys_t) &stm32fd_cfg->pclken[1],
+			  &rate_tmp) < 0) {
+			LOG_ERR("Failed call clock_control_get_rate(pclk[1])");
+			return -EIO;
+		}
+	} else {
+		if (clock_control_get_rate(clk,
+			 (clock_control_subsys_t) &stm32fd_cfg->pclken[0],
+			  &rate_tmp) < 0) {
+			LOG_ERR("Failed call clock_control_get_rate(pclk[0])");
+			return -EIO;
+		}
 	}
 
 	if (FDCAN_CONFIG->CKDIV == 0) {
diff --git a/drivers/can/can_stm32h7_fdcan.c b/drivers/can/can_stm32h7_fdcan.c
index 912358b1462..9e3c5ceb055 100644
--- a/drivers/can/can_stm32h7_fdcan.c
+++ b/drivers/can/can_stm32h7_fdcan.c
@@ -11,7 +11,6 @@
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/drivers/pinctrl.h>
 #include <zephyr/kernel.h>
-#include <stm32_ll_rcc.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/irq.h>
 #include <zephyr/sys/util.h>
@@ -84,16 +83,33 @@ static int can_stm32h7_clear_mram(const struct device *dev, uint16_t offset, siz
 
 static int can_stm32h7_get_core_clock(const struct device *dev, uint32_t *rate)
 {
-	const uint32_t rate_tmp = LL_RCC_GetFDCANClockFreq(LL_RCC_FDCAN_CLKSOURCE);
+	uint32_t rate_tmp;
+	const struct can_mcan_config *mcan_cfg = dev->config;
+	const struct can_stm32h7_config *stm32h7_cfg = mcan_cfg->custom;
+	const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
 	uint32_t cdiv;
 
 	ARG_UNUSED(dev);
-
-	if (rate_tmp == LL_RCC_PERIPH_FREQUENCY_NO) {
-		LOG_ERR("Can't read core clock");
-		return -EIO;
+	if (!device_is_ready(clk)) {
+		LOG_ERR("clock control device not ready");
+		return -ENODEV;
 	}
 
+	if (IS_ENABLED(STM32H7_FDCAN_DOMAIN_CLOCK_SUPPORT) && (stm32h7_cfg->pclk_len > 1)) {
+		if (clock_control_get_rate(clk,
+			 (clock_control_subsys_t) &stm32h7_cfg->pclken[1],
+			  &rate_tmp) < 0) {
+			LOG_ERR("Failed call clock_control_get_rate(pclk[1])");
+			return -EIO;
+		}
+	} else {
+		if (clock_control_get_rate(clk,
+			 (clock_control_subsys_t) &stm32h7_cfg->pclken[0],
+			  &rate_tmp) < 0) {
+			LOG_ERR("Failed call clock_control_get_rate(pclk[0])");
+			return -EIO;
+		}
+	}
 	cdiv = FIELD_GET(FDCANCCU_CCFG_CDIV, FDCAN_CCU->CCFG);
 	if (cdiv == 0U) {
 		*rate = rate_tmp;
diff --git a/drivers/can/can_tcan4x5x.c b/drivers/can/can_tcan4x5x.c
index d92efa20455..2abd0467a5e 100644
--- a/drivers/can/can_tcan4x5x.c
+++ b/drivers/can/can_tcan4x5x.c
@@ -508,8 +508,10 @@ static int tcan4x5x_wake(const struct device *dev)
 
 static int tcan4x5x_reset(const struct device *dev)
 {
+#if TCAN4X5X_RST_GPIO_SUPPORT
 	const struct can_mcan_config *mcan_config = dev->config;
 	const struct tcan4x5x_config *tcan_config = mcan_config->custom;
+#endif /* TCAN4X5X_RST_GPIO_SUPPORT */
 	int err;
 
 	err = tcan4x5x_wake(dev);
diff --git a/drivers/charger/CMakeLists.txt b/drivers/charger/CMakeLists.txt
index 60b80b0ed25..3c5dbe1f7e0 100644
--- a/drivers/charger/CMakeLists.txt
+++ b/drivers/charger/CMakeLists.txt
@@ -3,9 +3,12 @@
 zephyr_library()
 zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/charger.h)
 
+zephyr_library_sources_ifdef(CONFIG_CHARGER_AXP2101 charger_axp2101.c)
 zephyr_library_sources_ifdef(CONFIG_CHARGER_BQ24190 charger_bq24190.c)
 zephyr_library_sources_ifdef(CONFIG_CHARGER_BQ25180 charger_bq25180.c)
+zephyr_library_sources_ifdef(CONFIG_CHARGER_BQ25713 charger_bq25713.c)
 zephyr_library_sources_ifdef(CONFIG_CHARGER_MAX20335 charger_max20335.c)
+zephyr_library_sources_ifdef(CONFIG_CHARGER_PF1550 charger_pf1550.c)
 zephyr_library_sources_ifdef(CONFIG_SBS_CHARGER sbs_charger.c)
 zephyr_library_sources_ifdef(CONFIG_USERSPACE charger_handlers.c)
 zephyr_library_sources_ifdef(CONFIG_EMUL_SBS_CHARGER emul_sbs_charger.c)
diff --git a/drivers/charger/Kconfig b/drivers/charger/Kconfig
index 4e0b6b3c7a7..2c6956278dc 100644
--- a/drivers/charger/Kconfig
+++ b/drivers/charger/Kconfig
@@ -1,4 +1,5 @@
 # Copyright 2023 Cirrus Logic, Inc.
+# Copyright 2025 Palta Tech, S.A
 #
 # SPDX-License-Identifier: Apache-2.0
 
@@ -50,9 +51,12 @@ config CHARGER_SYSTEM_VOLTAGE_NOTIFICATIONS
 	  Enables support for system voltage notifications
 endmenu
 
+source "drivers/charger/Kconfig.axp2101"
 source "drivers/charger/Kconfig.sbs_charger"
 source "drivers/charger/Kconfig.bq24190"
 source "drivers/charger/Kconfig.bq25180"
+source "drivers/charger/Kconfig.bq25713"
 source "drivers/charger/Kconfig.max20335"
+source "drivers/charger/Kconfig.pf1550"
 
 endif # CHARGER
diff --git a/drivers/charger/Kconfig.axp2101 b/drivers/charger/Kconfig.axp2101
new file mode 100644
index 00000000000..70675625865
--- /dev/null
+++ b/drivers/charger/Kconfig.axp2101
@@ -0,0 +1,12 @@
+# Copyright (c) 2025 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+config CHARGER_AXP2101
+	bool "X-Powers AXP2101 PMIC charger driver"
+	default y
+	depends on DT_HAS_X_POWERS_AXP2101_CHARGER_ENABLED
+	depends on DT_HAS_X_POWERS_AXP2101_ENABLED
+	select I2C
+	select MFD
+	help
+	  Enable the AXP2101 PMIC charger driver
diff --git a/drivers/charger/Kconfig.bq25713 b/drivers/charger/Kconfig.bq25713
new file mode 100644
index 00000000000..747dc46d9e4
--- /dev/null
+++ b/drivers/charger/Kconfig.bq25713
@@ -0,0 +1,11 @@
+# Copyright 2025 Palta Tech, S.A
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config CHARGER_BQ25713
+	bool "BQ25713 Battery Charger"
+	default y
+	depends on DT_HAS_TI_BQ25713_ENABLED
+	select I2C
+	help
+	  Enable BQ25713 battery charger driver.
diff --git a/drivers/charger/Kconfig.pf1550 b/drivers/charger/Kconfig.pf1550
new file mode 100644
index 00000000000..f81e0b085b9
--- /dev/null
+++ b/drivers/charger/Kconfig.pf1550
@@ -0,0 +1,12 @@
+# Copyright 2024 Arduino SA
+# SPDX-License-Identifier: Apache-2.0
+
+config CHARGER_PF1550
+	bool "NXP PF1550 battery charger driver"
+	default y
+	depends on DT_HAS_NXP_PF1550_CHARGER_ENABLED
+	select GPIO
+	select I2C
+	select MFD
+	help
+	  Enable the NXP PF1550 battery charger driver.
diff --git a/drivers/charger/charger_axp2101.c b/drivers/charger/charger_axp2101.c
new file mode 100644
index 00000000000..5396c2cce45
--- /dev/null
+++ b/drivers/charger/charger_axp2101.c
@@ -0,0 +1,404 @@
+/*
+ * Copyright 2025 BayLibre SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT x_powers_axp2101_charger
+
+#include <errno.h>
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/charger.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(charger_axp2101, CONFIG_CHARGER_LOG_LEVEL);
+
+#define AXP2101_PMU_STATUS1			0x00
+	#define VBUS_GOOD_INDICATION		BIT(5)
+
+#define AXP2101_PMU_STATUS2			0x01
+	#define CHARGING_STATUS			GENMASK(2, 0)
+	#define TRICKLE_CHARGE			0x0
+	#define PRE_CHARGE			0x1
+	#define CONSTANT_CURRENT		0x2
+	#define CONSTANT_VOLTAGE		0x3
+	#define CHARGE_DONE			0x4
+	#define NOT_CHARGING			0x5
+
+#define AXP2101_CHARGER_CONTROL			0x18
+	#define BUTTON_BATTERY_CHARGE_ENABLE	BIT(2)
+	#define CELL_BATTERY_CHARGE_ENABLE	BIT(1)
+
+#define AXP2101_IPRECH_CHARGER_SETTING		0x61
+	#define PRE_CHARGE_CURRENT_STEP_UA	25000
+
+#define AXP2101_ICC_CHARGER_SETTING		0x62
+#define AXP2101_ITERM_CHARGER_SETTING		0x63
+	#define CHARGE_TERMINATION_ENABLE	BIT(4)
+	#define TERMINATION_CURRENT_LIMIT	GENMASK(3, 0)
+	#define TERMINATION_CURRENT_STEP_UA	25000
+
+#define AXP2101_CV_CHARGER_VOLTAGE		0x64
+
+struct axp2101_config {
+	struct i2c_dt_spec i2c;
+	bool vbackup_enable;
+};
+
+struct axp2101_data {
+	uint32_t cc_current_ua;
+	uint32_t cc_voltage_uv;
+	uint32_t termination_current_ua;
+};
+
+static const uint32_t constant_charge_current_lut[] = {
+	[0] = 0,
+	[1] = 0,
+	[2] = 0,
+	[3] = 0,
+	[4] = 100000,
+	[5] = 125000,
+	[6] = 150000,
+	[7] = 175000,
+	[8] = 200000,
+	[9] = 300000,
+	[10] = 400000,
+	[11] = 500000,
+	[12] = 600000,
+	[13] = 700000,
+	[14] = 800000,
+	[15] = 900000,
+	[16] = 1000000,
+};
+
+static const uint32_t constant_charge_voltage_lut[] = {
+	[0] = 0,
+	[1] = 4000000,
+	[2] = 4100000,
+	[3] = 4200000,
+	[4] = 4350000,
+	[5] = 4400000,
+};
+
+static int get_index_in_lut(uint32_t value, const uint32_t *lut, size_t lut_len)
+{
+	int i;
+
+	for (i = 0; i < (int) lut_len; i++) {
+		if (value == lut[i]) {
+			return i;
+		}
+	}
+
+	return -1;
+}
+
+static enum charger_online is_charger_online(const struct device *dev, union charger_propval *val)
+{
+	const struct axp2101_config *const config = dev->config;
+	uint8_t tmp;
+	int ret;
+
+	ret = i2c_reg_read_byte_dt(&config->i2c, AXP2101_PMU_STATUS1, &tmp);
+	if (ret < 0) {
+		return ret;
+	}
+
+	val->online = (tmp & VBUS_GOOD_INDICATION) ?
+		      CHARGER_ONLINE_FIXED : CHARGER_ONLINE_OFFLINE;
+
+	return 0;
+}
+
+static int get_constant_charge_current_ua(const struct device *dev, union charger_propval *val)
+{
+	const struct axp2101_config *const config = dev->config;
+	uint8_t tmp;
+	int ret;
+
+	ret = i2c_reg_read_byte_dt(&config->i2c, AXP2101_ICC_CHARGER_SETTING, &tmp);
+	if (ret < 0) {
+		return ret;
+	}
+
+	val->const_charge_current_ua = constant_charge_current_lut[tmp];
+
+	return 0;
+}
+
+static int set_constant_charge_current_ua(const struct device *dev,
+					  const union charger_propval *val)
+{
+	const struct axp2101_config *const config = dev->config;
+	struct axp2101_data *data = dev->data;
+	int lut_index;
+
+	lut_index = get_index_in_lut(val->const_charge_current_ua,
+				     constant_charge_current_lut,
+				     ARRAY_SIZE(constant_charge_current_lut));
+	if (lut_index < 0) {
+		return -EINVAL;
+	}
+
+	data->cc_current_ua = constant_charge_current_lut[lut_index];
+
+	return i2c_reg_write_byte_dt(&config->i2c, AXP2101_ICC_CHARGER_SETTING,
+				     (uint8_t) lut_index);
+}
+
+static int get_pre_charge_current_ua(const struct device *dev, union charger_propval *val)
+{
+	const struct axp2101_config *const config = dev->config;
+	uint8_t tmp;
+	int ret;
+
+	ret = i2c_reg_read_byte_dt(&config->i2c, AXP2101_IPRECH_CHARGER_SETTING, &tmp);
+	if (ret < 0) {
+		return ret;
+	}
+	val->precharge_current_ua = PRE_CHARGE_CURRENT_STEP_UA * ((uint32_t) tmp);
+
+	return 0;
+}
+
+static int get_termination_current_ua(const struct device *dev,
+				      union charger_propval *val)
+{
+	const struct axp2101_config *const config = dev->config;
+	uint8_t tmp;
+	int ret;
+
+	ret = i2c_reg_read_byte_dt(&config->i2c, AXP2101_ITERM_CHARGER_SETTING, &tmp);
+	if (ret < 0) {
+		return ret;
+	}
+
+	if ((tmp & CHARGE_TERMINATION_ENABLE) == 0) {
+		val->charge_term_current_ua = 0;
+	} else {
+		tmp = tmp & TERMINATION_CURRENT_LIMIT;
+		val->charge_term_current_ua = TERMINATION_CURRENT_STEP_UA * ((uint32_t) tmp);
+	}
+
+	return 0;
+}
+
+static int set_termination_current_ua(const struct device *dev,
+				      const union charger_propval *val)
+{
+	const struct axp2101_config *const config = dev->config;
+	uint32_t mask, tmp = 0;
+
+	tmp = val->charge_term_current_ua;
+	if ((tmp > 200000) || ((tmp % TERMINATION_CURRENT_STEP_UA) != 0)) {
+		return -EINVAL;
+	}
+
+	if (tmp != 0) {
+		tmp = (uint8_t) (tmp / TERMINATION_CURRENT_STEP_UA);
+		tmp |= CHARGE_TERMINATION_ENABLE;
+	}
+
+	mask = TERMINATION_CURRENT_LIMIT | CHARGE_TERMINATION_ENABLE;
+
+	return i2c_reg_update_byte_dt(&config->i2c, AXP2101_ITERM_CHARGER_SETTING,
+				      mask, tmp);
+}
+
+static int get_constant_charge_voltage_uv(const struct device *dev, union charger_propval *val)
+{
+	const struct axp2101_config *const config = dev->config;
+	uint8_t tmp;
+	int ret;
+
+	ret = i2c_reg_read_byte_dt(&config->i2c, AXP2101_CV_CHARGER_VOLTAGE, &tmp);
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (tmp > ARRAY_SIZE(constant_charge_voltage_lut)) {
+		return -EINVAL;
+	}
+
+	val->const_charge_voltage_uv = constant_charge_voltage_lut[tmp];
+
+	return 0;
+}
+
+static int set_constant_charge_voltage_uv(const struct device *dev,
+					  const union charger_propval *val)
+{
+	const struct axp2101_config *const config = dev->config;
+	int lut_index;
+
+	lut_index = get_index_in_lut(val->const_charge_voltage_uv,
+				     constant_charge_voltage_lut,
+				     ARRAY_SIZE(constant_charge_voltage_lut));
+	if (lut_index < 0) {
+		return -EINVAL;
+	}
+
+	return i2c_reg_write_byte_dt(&config->i2c, AXP2101_CV_CHARGER_VOLTAGE, (uint8_t) lut_index);
+}
+
+static int get_status(const struct device *dev, union charger_propval *val)
+{
+	const struct axp2101_config *const config = dev->config;
+	uint8_t tmp;
+	int ret;
+
+	ret = i2c_reg_read_byte_dt(&config->i2c, AXP2101_PMU_STATUS2, &tmp);
+	if (ret < 0) {
+		return ret;
+	}
+
+	tmp = tmp & CHARGING_STATUS;
+	if ((tmp >= TRICKLE_CHARGE) && (tmp <= CONSTANT_VOLTAGE)) {
+		val->status = CHARGER_STATUS_CHARGING;
+	} else if (tmp == CHARGE_DONE) {
+		val->status = CHARGER_STATUS_FULL;
+	} else if (tmp == NOT_CHARGING) {
+		val->status = CHARGER_STATUS_NOT_CHARGING;
+	} else {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int get_charge_type(const struct device *dev, union charger_propval *val)
+{
+	const struct axp2101_config *const config = dev->config;
+	uint8_t tmp;
+	int ret;
+
+	ret = i2c_reg_read_byte_dt(&config->i2c, AXP2101_PMU_STATUS2, &tmp);
+	if (ret < 0) {
+		return ret;
+	}
+
+	tmp = tmp & CHARGING_STATUS;
+	if ((tmp == TRICKLE_CHARGE) || (tmp == PRE_CHARGE)) {
+		val->charge_type = CHARGER_CHARGE_TYPE_TRICKLE;
+	} else if ((tmp >= CONSTANT_CURRENT) && (tmp <= CHARGE_DONE)) {
+		val->charge_type = CHARGER_CHARGE_TYPE_STANDARD;
+	} else if (tmp == NOT_CHARGING) {
+		val->charge_type = CHARGER_CHARGE_TYPE_UNKNOWN;
+	} else {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int axp2101_get_prop(const struct device *dev, charger_prop_t prop,
+			    union charger_propval *val)
+{
+	switch (prop) {
+	case CHARGER_PROP_ONLINE:
+		return is_charger_online(dev, val);
+	case CHARGER_PROP_CONSTANT_CHARGE_CURRENT_UA:
+		return get_constant_charge_current_ua(dev, val);
+	case CHARGER_PROP_CONSTANT_CHARGE_VOLTAGE_UV:
+		return get_constant_charge_voltage_uv(dev, val);
+	case CHARGER_PROP_PRECHARGE_CURRENT_UA:
+		return get_pre_charge_current_ua(dev, val);
+	case CHARGER_PROP_CHARGE_TERM_CURRENT_UA:
+		return get_termination_current_ua(dev, val);
+	case CHARGER_PROP_CHARGE_TYPE:
+		return get_charge_type(dev, val);
+	case CHARGER_PROP_STATUS:
+		return get_status(dev, val);
+	default:
+		return -ENOTSUP;
+	}
+}
+
+static int axp2101_set_prop(const struct device *dev, charger_prop_t prop,
+			    const union charger_propval *val)
+{
+	switch (prop) {
+	case CHARGER_PROP_CONSTANT_CHARGE_CURRENT_UA:
+		return set_constant_charge_current_ua(dev, val);
+	case CHARGER_PROP_CONSTANT_CHARGE_VOLTAGE_UV:
+		return set_constant_charge_voltage_uv(dev, val);
+	case CHARGER_PROP_CHARGE_TERM_CURRENT_UA:
+		return set_termination_current_ua(dev, val);
+	default:
+		return -ENOTSUP;
+	}
+}
+
+static int axp2101_charge_enable(const struct device *dev, const bool enable)
+{
+	const struct axp2101_config *const config = dev->config;
+
+	return i2c_reg_update_byte_dt(&config->i2c, AXP2101_CHARGER_CONTROL,
+				      CELL_BATTERY_CHARGE_ENABLE,
+				      (enable) ? CELL_BATTERY_CHARGE_ENABLE : 0);
+}
+
+static int axp2101_init(const struct device *dev)
+{
+	const struct axp2101_config *const config = dev->config;
+	struct axp2101_data *data = dev->data;
+	union charger_propval val;
+	int ret;
+
+	if (config->vbackup_enable) {
+		ret = i2c_reg_update_byte_dt(&config->i2c, AXP2101_CHARGER_CONTROL,
+					     BUTTON_BATTERY_CHARGE_ENABLE,
+					     BUTTON_BATTERY_CHARGE_ENABLE);
+		if (ret < 0) {
+			return ret;
+		}
+	}
+
+	val.const_charge_current_ua = data->cc_current_ua;
+	ret = set_constant_charge_current_ua(dev, &val);
+	if (ret < 0) {
+		return ret;
+	}
+
+	val.const_charge_voltage_uv = data->cc_voltage_uv;
+	ret = set_constant_charge_voltage_uv(dev, &val);
+	if (ret < 0) {
+		return ret;
+	}
+
+	val.charge_term_current_ua = data->termination_current_ua;
+	ret = set_termination_current_ua(dev, &val);
+	if (ret < 0) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(charger, axp2101_driver_api) = {
+	.get_property = axp2101_get_prop,
+	.set_property = axp2101_set_prop,
+	.charge_enable = axp2101_charge_enable,
+};
+
+#define AXP2101_INIT(inst)                                                                         \
+	static const struct axp2101_config axp2101_config_##inst = {                               \
+		.i2c = I2C_DT_SPEC_GET(DT_PARENT(DT_INST(inst, DT_DRV_COMPAT))),                   \
+		.vbackup_enable = DT_INST_PROP(inst, vbackup_enable),                              \
+	};                                                                                         \
+	static struct axp2101_data axp2101_data_##inst = {                                         \
+		.cc_current_ua = DT_INST_PROP(inst, constant_charge_current_max_microamp),         \
+		.cc_voltage_uv = DT_INST_PROP(inst, constant_charge_voltage_max_microvolt),        \
+		.termination_current_ua = DT_INST_PROP_OR(inst, charge-term-current-microamp,      \
+							  125000),                                 \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(inst, axp2101_init, NULL, &axp2101_data_##inst,                      \
+			      &axp2101_config_##inst, POST_KERNEL,                                 \
+			      CONFIG_CHARGER_INIT_PRIORITY,                                        \
+			      &axp2101_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(AXP2101_INIT)
diff --git a/drivers/charger/charger_bq24190.c b/drivers/charger/charger_bq24190.c
index b7672a88807..0fdf861c5af 100644
--- a/drivers/charger/charger_bq24190.c
+++ b/drivers/charger/charger_bq24190.c
@@ -18,7 +18,7 @@
 #include "zephyr/logging/log.h"
 #include <zephyr/drivers/gpio.h>
 
-LOG_MODULE_REGISTER(ti_bq24190);
+LOG_MODULE_REGISTER(ti_bq24190, CONFIG_CHARGER_LOG_LEVEL);
 
 struct bq24190_config {
 	struct i2c_dt_spec i2c;
diff --git a/drivers/charger/charger_bq25713.c b/drivers/charger/charger_bq25713.c
new file mode 100644
index 00000000000..20d6ceb8f79
--- /dev/null
+++ b/drivers/charger/charger_bq25713.c
@@ -0,0 +1,463 @@
+/*
+ * Copyright 2025 Palta Tech, S.A
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * BQ25713 Datasheet: https://www.ti.com/lit/ds/symlink/bq25713.pdf
+ */
+
+#define DT_DRV_COMPAT ti_bq25713
+
+#include <errno.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/charger.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/sys/byteorder.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(ti_bq25713, CONFIG_CHARGER_LOG_LEVEL);
+
+/* Charge Option 0 */
+#define BQ25713_REG_CO0_LOW          0x00
+#define BQ25713_REG_CO0_INHIBIT      0x01
+#define BQ25713_REG_CO0_INHIBIT_MASK BIT(0)
+
+/* Charge Current */
+#define BQ25713_REG_CC_LOW                    0x02
+#define BQ25713_REG_CC_CHARGE_CURRENT_MASK    GENMASK(12, 6)
+#define BQ25713_REG_CC_CHARGE_CURRENT_STEP_UA 64000
+#define BQ25713_REG_CC_CHARGE_CURRENT_MIN_UA  0
+#define BQ25713_REG_CC_CHARGE_CURRENT_MAX_UA  8128000
+
+/* Charger Status */
+#define BQ25713_REG_CS_HIGH            0x21
+#define BQ25713_REG_CS_AC_STAT         0x01
+#define BQ25713_REG_CS_AC_STAT_MASK    BIT(7)
+#define BQ25713_REG_CS_PRE_FAST_CHARGE GENMASK(2, 1)
+#define BQ25713_REG_CS_PRECHARGE       BIT(1)
+#define BQ25713_REG_CS_FASTCHARGE      BIT(2)
+
+/* Max Charge Voltage */
+#define BQ25713_REG_CV_LOW                    0x04
+#define BQ25713_REG_CV_CHARGE_VOLTAGE_MASK    GENMASK(14, 3)
+#define BQ25713_REG_CV_CHARGE_VOLTAGE_STEP_UV 8000
+#define BQ25713_REG_CV_CHARGE_VOLTAGE_MIN_UV  1024000
+#define BQ25713_REG_CV_CHARGE_VOLTAGE_MAX_UV  19200000
+
+/* Input current set by host IDPM */
+#define BQ25713_REG_IIN_HOST_HIGH    0x0F
+#define BQ25713_REG_IIN_HOST_MASK    GENMASK(7, 0)
+#define BQ25713_REG_IIN_HOST_STEP_UA 50000
+#define BQ25713_REG_IIN_HOST_MIN_UV  BQ25713_REG_IIN_HOST_STEP_UA
+#define BQ25713_REG_IIN_HOST_MAX_UV  6400000
+
+/*  Input voltage IDPM */
+#define BQ25713_REG_IIN_DPM_HIGH    0x25
+#define BQ25713_REG_IIN_DPM_MASK    BQ25713_REG_IIN_HOST_MASK
+#define BQ25713_REG_IIN_DPM_STEP_UA BQ25713_REG_IIN_HOST_STEP_UA
+
+/* Mininum system voltage */
+#define BQ25713_REG_MIN_SYS_VOLTAGE_HI      0x0D
+#define BQ25713_REG_MIN_SYS_VOLTAGE_MASK    GENMASK(5, 0)
+#define BQ25713_REG_MIN_SYS_VOLTAGE_STEP_UV 256000
+#define BQ25713_REG_MIN_SYS_VOLTAGE_MIN_UV  1024000
+#define BQ25713_REG_MIN_SYS_VOLTAGE_MAX_UV  16128000
+
+/*  Input voltage VDPM */
+#define BQ25713_REG_VIN_LOW                0x0A
+#define BQ25713_REG_VIN_DPM_MASK           GENMASK(13, 6)
+#define BQ25713_REG_VIN_DPM_STEP_UV        64000
+#define BQ25713_REG_VIN_DPM_OFFSET_UV      3200000
+#define BQ25713_REG_VIN_DPM_VOLTAGE_MIN_UV BQ25713_REG_VIN_DPM_OFFSET_UV
+#define BQ25713_REG_VIN_DPM_VOLTAGE_MAX_UV 195200000
+
+/* Manufacture ID */
+#define BQ25713_REG_ID_LOW       0x2E
+#define BQ25713_REG_ID_PN_25713  0x4088
+#define BQ25713_REG_ID_PN_25713B 0x408A
+
+#define BQ25713_FACTOR_U_TO_M 1000
+
+struct bq25713_config {
+	struct i2c_dt_spec i2c;
+	uint32_t vsys_min_uv;
+	uint32_t ichg_ua;
+	uint32_t vreg_uv;
+};
+
+static inline int bq25713_write8(const struct device *dev, uint8_t reg, uint8_t value)
+{
+	const struct bq25713_config *const config = dev->config;
+
+	return i2c_reg_write_byte_dt(&config->i2c, reg, value);
+}
+
+static inline int bq25713_read8(const struct device *dev, uint8_t reg, uint8_t *value)
+{
+	const struct bq25713_config *const config = dev->config;
+	int ret;
+
+	ret = i2c_reg_read_byte_dt(&config->i2c, reg, value);
+	if (ret < 0) {
+		LOG_ERR("Unable to read register");
+	}
+	return ret;
+}
+
+static inline int bq25713_update8(const struct device *dev, uint8_t reg, uint8_t mask,
+				  uint8_t value)
+{
+	const struct bq25713_config *const config = dev->config;
+	int ret;
+
+	ret = i2c_reg_update_byte_dt(&config->i2c, reg, mask, value);
+	if (ret < 0) {
+		LOG_ERR("Unable to update register");
+	}
+	return ret;
+}
+
+static inline int bq25713_write16(const struct device *dev, uint8_t reg, uint16_t value)
+{
+	const struct bq25713_config *const config = dev->config;
+	uint8_t buf[3];
+
+	buf[0] = reg;
+	sys_put_le16(value, &buf[1]);
+
+	return i2c_write_dt(&config->i2c, buf, sizeof(buf));
+}
+
+static inline int bq25713_read16(const struct device *dev, uint8_t reg, uint16_t *value)
+{
+	const struct bq25713_config *config = dev->config;
+	uint8_t i2c_data[2];
+	int ret;
+
+	ret = i2c_burst_read_dt(&config->i2c, reg, i2c_data, sizeof(i2c_data));
+	if (ret < 0) {
+		LOG_ERR("Unable to read register");
+		return ret;
+	}
+
+	*value = sys_get_be16(i2c_data);
+
+	return 0;
+}
+
+static int bq25713_set_minimum_system_voltage(const struct device *dev, uint32_t voltage_uv)
+{
+	if (!IN_RANGE(voltage_uv, BQ25713_REG_MIN_SYS_VOLTAGE_MIN_UV,
+		      BQ25713_REG_MIN_SYS_VOLTAGE_MAX_UV)) {
+		LOG_WRN("minimum system voltage out of range: %umV, "
+			"clamping to the nearest limit",
+			voltage_uv / BQ25713_FACTOR_U_TO_M);
+	}
+
+	uint32_t v;
+
+	voltage_uv = CLAMP(voltage_uv, BQ25713_REG_MIN_SYS_VOLTAGE_MIN_UV,
+			   BQ25713_REG_MIN_SYS_VOLTAGE_MAX_UV);
+	v = voltage_uv / BQ25713_REG_MIN_SYS_VOLTAGE_STEP_UV;
+	v = FIELD_PREP(BQ25713_REG_MIN_SYS_VOLTAGE_MASK, v);
+	return bq25713_write8(dev, BQ25713_REG_MIN_SYS_VOLTAGE_HI, v);
+}
+
+static int bq25713_set_constant_charge_current(const struct device *dev, uint32_t current_ua)
+{
+	if (!IN_RANGE(current_ua, BQ25713_REG_CC_CHARGE_CURRENT_MIN_UA,
+		      BQ25713_REG_CC_CHARGE_CURRENT_MAX_UA)) {
+		LOG_WRN("charging current out of range: %umA, "
+			"clamping to the nearest limit",
+			current_ua / BQ25713_FACTOR_U_TO_M);
+	}
+	current_ua = CLAMP(current_ua, BQ25713_REG_CC_CHARGE_CURRENT_MIN_UA,
+			   BQ25713_REG_CC_CHARGE_CURRENT_MAX_UA);
+	uint32_t v;
+
+	v = current_ua / BQ25713_REG_CC_CHARGE_CURRENT_STEP_UA;
+	v = FIELD_PREP(BQ25713_REG_CC_CHARGE_CURRENT_MASK, v);
+
+	return bq25713_write16(dev, BQ25713_REG_CC_LOW, v);
+}
+
+static int bq25713_set_constant_charge_voltage(const struct device *dev, uint32_t voltage_uv)
+{
+	if (!IN_RANGE(voltage_uv, BQ25713_REG_CV_CHARGE_VOLTAGE_MIN_UV,
+		      BQ25713_REG_CV_CHARGE_VOLTAGE_MAX_UV)) {
+		LOG_WRN("charging voltage out of range: %umV, "
+			"clamping to the nearest limit",
+			voltage_uv / BQ25713_FACTOR_U_TO_M);
+	}
+
+	uint32_t v;
+
+	voltage_uv = CLAMP(voltage_uv, BQ25713_REG_CV_CHARGE_VOLTAGE_MIN_UV,
+			   BQ25713_REG_CV_CHARGE_VOLTAGE_MAX_UV);
+	v = voltage_uv / BQ25713_REG_CV_CHARGE_VOLTAGE_STEP_UV;
+	v = FIELD_PREP(BQ25713_REG_CV_CHARGE_VOLTAGE_MASK, v);
+	return bq25713_write16(dev, BQ25713_REG_CV_LOW, v);
+}
+
+static int bq25713_set_iindpm(const struct device *dev, uint32_t current_ua)
+{
+	if (!IN_RANGE(current_ua, BQ25713_REG_IIN_HOST_MIN_UV, BQ25713_REG_IIN_HOST_MAX_UV)) {
+		LOG_WRN("input current regulation out of range: %umA, "
+			"clamping to the nearest limit",
+			current_ua / BQ25713_FACTOR_U_TO_M);
+	}
+
+	uint32_t v;
+
+	current_ua = CLAMP(current_ua, BQ25713_REG_IIN_HOST_MIN_UV, BQ25713_REG_IIN_HOST_MAX_UV);
+	v = current_ua / BQ25713_REG_IIN_HOST_STEP_UA;
+	v = FIELD_PREP(BQ25713_REG_IIN_HOST_MASK, v);
+	return bq25713_write8(dev, BQ25713_REG_IIN_HOST_HIGH, v);
+}
+
+static int bq25713_set_vindpm(const struct device *dev, uint32_t voltage_ua)
+{
+	if (!IN_RANGE(voltage_ua, BQ25713_REG_VIN_DPM_VOLTAGE_MIN_UV,
+		      BQ25713_REG_VIN_DPM_VOLTAGE_MAX_UV)) {
+		LOG_WRN("input voltage regulation of range: %umV, "
+			"clamping to the nearest limit",
+			voltage_ua / BQ25713_FACTOR_U_TO_M);
+	}
+
+	uint32_t v;
+
+	voltage_ua = CLAMP(voltage_ua, BQ25713_REG_VIN_DPM_VOLTAGE_MIN_UV,
+			   BQ25713_REG_VIN_DPM_VOLTAGE_MAX_UV);
+	v = (voltage_ua - BQ25713_REG_VIN_DPM_OFFSET_UV) / BQ25713_REG_VIN_DPM_STEP_UV;
+	v = FIELD_PREP(BQ25713_REG_VIN_DPM_MASK, v);
+	return bq25713_write16(dev, BQ25713_REG_VIN_LOW, v);
+}
+
+static int bq25713_get_constant_charge_current(const struct device *dev, uint32_t *current_ua)
+{
+	uint16_t v;
+	int ret;
+
+	ret = bq25713_read16(dev, BQ25713_REG_CC_LOW, &v);
+	if (ret < 0) {
+		return ret;
+	}
+
+	v = FIELD_GET(BQ25713_REG_CC_CHARGE_CURRENT_MASK, v);
+
+	*current_ua = v * BQ25713_REG_CC_CHARGE_CURRENT_STEP_UA;
+
+	return 0;
+}
+
+static int bq25713_get_constant_charge_voltage(const struct device *dev, uint32_t *voltage_uv)
+{
+	uint16_t value;
+	int ret;
+
+	ret = bq25713_read16(dev, BQ25713_REG_CV_LOW, &value);
+	if (ret < 0) {
+		return ret;
+	}
+	value = FIELD_GET(BQ25713_REG_CV_CHARGE_VOLTAGE_MASK, value);
+
+	*voltage_uv = value * BQ25713_REG_CV_CHARGE_VOLTAGE_STEP_UV;
+
+	return 0;
+}
+
+static int bq25713_get_iindpm(const struct device *dev, uint32_t *current_ua)
+{
+	uint8_t value;
+	int ret;
+
+	ret = bq25713_read8(dev, BQ25713_REG_IIN_DPM_HIGH, &value);
+	if (ret < 0) {
+		return ret;
+	}
+	value = FIELD_GET(BQ25713_REG_IIN_DPM_MASK, value);
+
+	*current_ua = value * BQ25713_REG_IIN_DPM_STEP_UA;
+
+	return 0;
+}
+
+static int bq25713_get_vindpm(const struct device *dev, uint32_t *voltage_uv)
+{
+	uint16_t value;
+	int ret;
+
+	ret = bq25713_read16(dev, BQ25713_REG_VIN_LOW, &value);
+	if (ret < 0) {
+		return ret;
+	}
+	value = FIELD_GET(BQ25713_REG_VIN_DPM_MASK, value);
+
+	*voltage_uv = (value * BQ25713_REG_VIN_DPM_STEP_UV) + BQ25713_REG_VIN_DPM_OFFSET_UV;
+
+	return 0;
+}
+
+static int bq25713_get_status(const struct device *dev, enum charger_status *status)
+{
+	uint8_t charge_status;
+	int ret;
+
+	ret = bq25713_read8(dev, BQ25713_REG_CS_HIGH, &charge_status);
+	if (ret < 0) {
+		return ret;
+	}
+
+	switch (FIELD_GET(BQ25713_REG_CS_PRE_FAST_CHARGE, charge_status)) {
+	case BQ25713_REG_CS_FASTCHARGE:
+		__fallthrough;
+	case BQ25713_REG_CS_PRECHARGE:
+		*status = CHARGER_STATUS_CHARGING;
+		break;
+	default:
+		*status = CHARGER_STATUS_UNKNOWN;
+		break;
+	}
+
+	return 0;
+}
+
+static int bq25713_get_online(const struct device *dev, enum charger_online *online)
+{
+	uint8_t status;
+	int ret;
+
+	ret = bq25713_read8(dev, BQ25713_REG_CS_HIGH, &status);
+	if (ret < 0) {
+		return ret;
+	}
+
+	status = FIELD_GET(BQ25713_REG_CS_AC_STAT_MASK, status);
+	if (status == BQ25713_REG_CS_AC_STAT) {
+		*online = CHARGER_ONLINE_FIXED;
+	} else {
+		*online = CHARGER_ONLINE_OFFLINE;
+	}
+
+	return 0;
+}
+
+static int bq25713_charger_get_charge_type(const struct device *dev,
+					   enum charger_charge_type *charge_type)
+{
+	*charge_type = CHARGER_CHARGE_TYPE_UNKNOWN;
+	return 0;
+}
+
+static int bq25713_get_prop(const struct device *dev, charger_prop_t prop,
+			    union charger_propval *value)
+{
+	switch (prop) {
+	case CHARGER_PROP_ONLINE:
+		return bq25713_get_online(dev, &value->online);
+	case CHARGER_PROP_CHARGE_TYPE:
+		return bq25713_charger_get_charge_type(dev, &value->charge_type);
+	case CHARGER_PROP_STATUS:
+		return bq25713_get_status(dev, &value->status);
+	case CHARGER_PROP_CONSTANT_CHARGE_CURRENT_UA:
+		return bq25713_get_constant_charge_current(dev, &value->const_charge_current_ua);
+	case CHARGER_PROP_CONSTANT_CHARGE_VOLTAGE_UV:
+		return bq25713_get_constant_charge_voltage(dev, &value->const_charge_voltage_uv);
+	case CHARGER_PROP_INPUT_REGULATION_CURRENT_UA:
+		return bq25713_get_iindpm(dev, &value->input_current_regulation_current_ua);
+	case CHARGER_PROP_INPUT_REGULATION_VOLTAGE_UV:
+		return bq25713_get_vindpm(dev, &value->input_voltage_regulation_voltage_uv);
+	default:
+		return -ENOTSUP;
+	}
+}
+
+static int bq25713_set_prop(const struct device *dev, charger_prop_t prop,
+			    const union charger_propval *value)
+{
+	switch (prop) {
+	case CHARGER_PROP_CONSTANT_CHARGE_CURRENT_UA:
+		return bq25713_set_constant_charge_current(dev, value->const_charge_current_ua);
+	case CHARGER_PROP_CONSTANT_CHARGE_VOLTAGE_UV:
+		return bq25713_set_constant_charge_voltage(dev, value->const_charge_voltage_uv);
+	case CHARGER_PROP_INPUT_REGULATION_CURRENT_UA:
+		return bq25713_set_iindpm(dev, value->input_current_regulation_current_ua);
+	case CHARGER_PROP_INPUT_REGULATION_VOLTAGE_UV:
+		return bq25713_set_vindpm(dev, value->input_voltage_regulation_voltage_uv);
+	default:
+		return -ENOTSUP;
+	}
+}
+
+static int bq25713_charge_enable(const struct device *dev, const bool enable)
+{
+	uint8_t value = enable ? 0 : BQ25713_REG_CO0_INHIBIT;
+
+	return bq25713_update8(dev, BQ25713_REG_CO0_LOW, BQ25713_REG_CO0_INHIBIT_MASK, value);
+}
+
+static int bq25713_set_config(const struct device *dev)
+{
+	const struct bq25713_config *const config = dev->config;
+	union charger_propval value;
+	int ret;
+
+	value.const_charge_current_ua = config->ichg_ua;
+
+	ret = bq25713_set_constant_charge_current(dev, value.const_charge_current_ua);
+	if (ret < 0) {
+		return ret;
+	}
+
+	value.const_charge_voltage_uv = config->vreg_uv;
+
+	ret = bq25713_set_constant_charge_voltage(dev, value.const_charge_voltage_uv);
+	if (ret < 0) {
+		return ret;
+	}
+
+	return bq25713_set_minimum_system_voltage(dev, config->vsys_min_uv);
+}
+
+static int bq25713_init(const struct device *dev)
+{
+	uint16_t value;
+	int ret;
+
+	ret = bq25713_read16(dev, BQ25713_REG_ID_LOW, &value);
+	if (ret < 0) {
+		return ret;
+	}
+
+	switch (value) {
+	case BQ25713_REG_ID_PN_25713:
+		__fallthrough;
+	case BQ25713_REG_ID_PN_25713B:
+		break;
+	default:
+		LOG_ERR("Error unknown model: 0x%04x\n", value);
+		return -ENODEV;
+	}
+
+	return bq25713_set_config(dev);
+}
+
+static DEVICE_API(charger, bq7513_driver_api) = {
+	.get_property = bq25713_get_prop,
+	.set_property = bq25713_set_prop,
+	.charge_enable = bq25713_charge_enable,
+};
+
+#define BQ25713_INIT(inst)                                                                         \
+                                                                                                   \
+	static const struct bq25713_config bq25713_config_##inst = {                               \
+		.i2c = I2C_DT_SPEC_INST_GET(inst),                                                 \
+		.ichg_ua = DT_INST_PROP(inst, constant_charge_current_max_microamp),               \
+		.vreg_uv = DT_INST_PROP(inst, constant_charge_voltage_max_microvolt),              \
+		.vsys_min_uv = DT_INST_PROP(inst, system_voltage_min_threshold_microvolt),         \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(inst, bq25713_init, NULL, NULL, &bq25713_config_##inst, POST_KERNEL, \
+			      CONFIG_CHARGER_INIT_PRIORITY, &bq7513_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(BQ25713_INIT)
diff --git a/drivers/charger/charger_max20335.c b/drivers/charger/charger_max20335.c
index 43d65bf9f80..ff6ccd59c7d 100644
--- a/drivers/charger/charger_max20335.c
+++ b/drivers/charger/charger_max20335.c
@@ -15,7 +15,7 @@
 #include <zephyr/sys/linear_range.h>
 
 #include "zephyr/logging/log.h"
-LOG_MODULE_REGISTER(max20335_charger);
+LOG_MODULE_REGISTER(max20335_charger, CONFIG_CHARGER_LOG_LEVEL);
 
 #define MAX20335_REG_STATUSA 0x02
 #define MAX20335_REG_STATUSB 0x03
diff --git a/drivers/charger/charger_pf1550.c b/drivers/charger/charger_pf1550.c
new file mode 100644
index 00000000000..e53785a6298
--- /dev/null
+++ b/drivers/charger/charger_pf1550.c
@@ -0,0 +1,691 @@
+/*
+ * Copyright 2024 Arduino SA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_pf1550_charger
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/charger.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/linear_range.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(pf1550_charger, CONFIG_CHARGER_LOG_LEVEL);
+
+#define INT_ENABLE_DELAY K_MSEC(500)
+
+#define CHARGER_CHG_INT           (0x80 + 0x00)
+#define CHARGER_CHG_INT_MASK      (0x80 + 0x02)
+#define CHARGER_CHG_INT_OK        (0x80 + 0x04)
+#define CHARGER_VBUS_SNS          (0x80 + 0x06)
+#define CHARGER_CHG_SNS           (0x80 + 0x07)
+#define CHARGER_BATT_SNS          (0x80 + 0x08)
+#define CHARGER_CHG_OPER          (0x80 + 0x09)
+#define CHARGER_CHG_TMR           (0x80 + 0x0A)
+#define CHARGER_CHG_EOC_CNFG      (0x80 + 0x0D)
+#define CHARGER_CHG_CURR_CNFG     (0x80 + 0x0E)
+#define CHARGER_BATT_REG          (0x80 + 0x0F)
+#define CHARGER_BATFET_CNFG       (0x80 + 0x11)
+#define CHARGER_THM_REG_CNFG      (0x80 + 0x12)
+#define CHARGER_VBUS_INLIM_CNFG   (0x80 + 0x14)
+#define CHARGER_VBUS_LIN_DPM      (0x80 + 0x15)
+#define CHARGER_USB_PHY_LDO_CNFG  (0x80 + 0x16)
+#define CHARGER_DBNC_DELAY_TIME   (0x80 + 0x18)
+#define CHARGER_CHG_INT_CNFG      (0x80 + 0x19)
+#define CHARGER_THM_ADJ_SETTING   (0x80 + 0x1A)
+#define CHARGER_VBUS2SYS_CNFG     (0x80 + 0x1B)
+#define CHARGER_LED_PWM           (0x80 + 0x1C)
+#define CHARGER_FAULT_BATFET_CNFG (0x80 + 0x1D)
+#define CHARGER_LED_CNFG          (0x80 + 0x1E)
+#define CHARGER_CHGR_KEY2         (0x80 + 0x1F)
+
+#define PF1550_BAT_IRQ      BIT(2)
+#define PF1550_CHG_IRQ      BIT(3)
+#define PF1550_VBUS_IRQ     BIT(5)
+#define PF1550_VBUS_DPM_IRQ BIT(5)
+#define CHG_INT_ENABLE_ALL  (0xFF)
+
+#define LED_PWM_LED_EN          BIT(7)
+#define LED_PWM_FULL_ON         BIT(5)
+
+#define LED_CNFG_LED_CFG        BIT(4)
+#define LED_CNFG_LEDOVRD        BIT(5)
+
+#define CHG_OPER_CHG_OPER_MASK          GENMASK(1, 0)
+#define CHG_CURR_CNFG_CHG_CC_MASK       GENMASK(4, 0)
+#define CHG_SNS_CHG_SNS_MASK            GENMASK(3, 0)
+#define VBUS_INLIM_CNFG_VBUS_INLIM_MASK GENMASK(7, 3)
+#define BATT_REG_CHGCV_MASK             GENMASK(5, 0)
+#define BATT_REG_VSYSMIN_MASK           GENMASK(7, 6)
+#define THM_REG_CNFG_THM_CNFG_MASK      GENMASK(1, 0)
+
+#define CHG_OPER_CHARGER_OFF_LINEAR_OFF     0
+#define CHG_OPER_CHARGER_OFF_LINEAR_ON      1
+#define CHG_OPER_CHARGER_ON_LINEAR_ON       2
+
+enum charger_pf1550_therm_mode {
+	PF1550_THERM_MODE_DISABLED,
+	PF1550_THERM_MODE_THERMISTOR,
+	PF1550_THERM_MODE_JEITA_1,
+	PF1550_THERM_MODE_JEITA_2,
+	PF1550_THERM_MODE_UNKNOWN,
+};
+
+/* synced with YAML binding */
+enum charger_pf1550_led_behaviour {
+	PF1550_LED_ON_IN_CHARGING_FLASH_IN_FAULT,
+	PF1550_LED_FLASH_IN_CHARGING_ON_IN_FAULT,
+	PF1550_LED_MANUAL_OFF
+};
+
+struct charger_pf1550_led_config {
+	bool enabled;
+	bool manual;
+	enum charger_pf1550_led_behaviour behaviour;
+};
+
+struct charger_pf1550_config {
+	struct i2c_dt_spec bus;
+	struct gpio_dt_spec int_gpio;
+	char *therm_mon_mode;
+	uint32_t charge_current_ua;
+	uint32_t vbus_ilim_ua;
+	uint32_t charge_voltage_max_uv;
+	uint32_t vsys_min_uv;
+};
+
+struct charger_pf1550_data {
+	const struct device *dev;
+	struct gpio_callback gpio_cb;
+	struct k_work int_routine_work;
+	struct k_work_delayable int_enable_work;
+	enum charger_status charger_status;
+	enum charger_online charger_online;
+	charger_status_notifier_t charger_status_notifier;
+	charger_online_notifier_t charger_online_notifier;
+	bool charger_enabled;
+	uint32_t charge_current_ua;
+	uint32_t vbus_ilim_ua;
+	struct charger_pf1550_led_config *led_config;
+};
+
+static const struct linear_range charger_vbus_ilim_range[] = {
+	LINEAR_RANGE_INIT(10000, 5000, 0, 8),
+	LINEAR_RANGE_INIT(100000, 50000, 9, 10),
+	LINEAR_RANGE_INIT(200000, 100000, 11, 19),
+	LINEAR_RANGE_INIT(1500000, 0, 20, 20),
+};
+
+static const struct linear_range charger_fast_charge_ua_range[] = {
+	LINEAR_RANGE_INIT(100000, 50000, 0, 18),
+};
+
+static const struct linear_range charger_battery_termination_uv_range[] = {
+	LINEAR_RANGE_INIT(3500000, 20000, 8, 55),
+};
+
+static const struct linear_range charger_vsysmin_uv[] = {
+	LINEAR_RANGE_INIT(3500000, 0, 0, 0),
+	LINEAR_RANGE_INIT(3700000, 0, 1, 1),
+	LINEAR_RANGE_INIT(4300000, 0, 2, 2),
+};
+
+static int pf1550_get_charger_status(const struct device *dev, enum charger_status *status)
+{
+	enum chg_sns {
+		PF1550_CHARGER_PRECHARGE,
+		PF1550_FAST_CHARGE_CONSTANT_CURRENT,
+		PF1550_FAST_CHARGE_CONSTANT_VOLTAGE,
+		PF1550_END_OF_CHARGE,
+		PF1550_CHARGE_DONE,
+		PF1550_TIMER_FAULT = 6,
+		PF1550_THERMISTOR_SUSPEND,
+		PF1550_CHARGER_OFF_INVALID_INPUT,
+		PF1550_BATTERY_OVERVOLTAGE,
+		PF1550_BATTERY_OVERTEMPERATURE,
+		PF1550_CHARGER_OFF_LINEAR_MODE = 12,
+	};
+
+	const struct charger_pf1550_config *const config = dev->config;
+	uint8_t val;
+	int ret;
+
+	ret = i2c_reg_read_byte_dt(&config->bus, CHARGER_CHG_SNS, &val);
+	if (ret) {
+		return ret;
+	}
+
+	val = FIELD_GET(CHG_SNS_CHG_SNS_MASK, val);
+
+	if (val == PF1550_CHARGE_DONE) {
+		*status = CHARGER_STATUS_FULL;
+	} else if (val < PF1550_CHARGE_DONE) {
+		*status = CHARGER_STATUS_CHARGING;
+	} else {
+		*status = CHARGER_STATUS_NOT_CHARGING;
+	}
+
+	return 0;
+}
+
+static int pf1550_get_charger_online(const struct device *dev, enum charger_online *online)
+{
+	const struct charger_pf1550_config *const config = dev->config;
+	uint8_t val;
+	int ret;
+
+	ret = i2c_reg_read_byte_dt(&config->bus, CHARGER_CHG_OPER, &val);
+	if (ret) {
+		return ret;
+	}
+
+	val = FIELD_GET(CHG_OPER_CHG_OPER_MASK, val);
+
+	switch (val) {
+	case CHG_OPER_CHARGER_ON_LINEAR_ON:
+		*online = CHARGER_ONLINE_FIXED;
+		break;
+	default:
+		*online = CHARGER_ONLINE_OFFLINE;
+		break;
+	};
+
+	return 0;
+}
+
+static int pf1550_set_constant_charge_current(const struct device *dev, uint32_t current_ua)
+{
+	const struct charger_pf1550_config *const config = dev->config;
+	uint16_t idx;
+	uint8_t val;
+	int ret;
+
+	ret = linear_range_group_get_index(charger_fast_charge_ua_range,
+					   ARRAY_SIZE(charger_fast_charge_ua_range), current_ua,
+					   &idx);
+	if (ret < 0) {
+		return ret;
+	}
+
+	val = FIELD_PREP(CHG_CURR_CNFG_CHG_CC_MASK, idx);
+
+	return i2c_reg_update_byte_dt(&config->bus, CHARGER_CHG_CURR_CNFG,
+				      CHG_CURR_CNFG_CHG_CC_MASK, val);
+}
+
+static int pf1550_set_vbus_ilim(const struct device *dev, uint32_t current_ua)
+{
+	const struct charger_pf1550_config *const config = dev->config;
+	uint16_t idx;
+	uint8_t val;
+	int ret;
+
+	ret = linear_range_group_get_index(charger_vbus_ilim_range,
+					   ARRAY_SIZE(charger_vbus_ilim_range), current_ua, &idx);
+	if (ret < 0) {
+		return ret;
+	}
+
+	val = FIELD_PREP(VBUS_INLIM_CNFG_VBUS_INLIM_MASK, idx);
+
+	return i2c_reg_update_byte_dt(&config->bus, CHARGER_VBUS_INLIM_CNFG,
+				      VBUS_INLIM_CNFG_VBUS_INLIM_MASK, val);
+}
+
+static int pf1550_set_vsys_min(const struct device *dev, uint32_t voltage_uv)
+{
+	const struct charger_pf1550_config *const config = dev->config;
+	uint16_t idx;
+	uint8_t val;
+	int ret;
+
+	ret = linear_range_group_get_index(charger_vsysmin_uv, ARRAY_SIZE(charger_vsysmin_uv),
+					   voltage_uv, &idx);
+	if (ret < 0) {
+		return ret;
+	}
+
+	val = FIELD_PREP(BATT_REG_VSYSMIN_MASK, idx);
+
+	return i2c_reg_update_byte_dt(&config->bus, CHARGER_BATT_REG, BATT_REG_VSYSMIN_MASK, val);
+}
+
+static int pf1550_set_charge_termination_uv(const struct device *dev, uint32_t voltage_uv)
+{
+	const struct charger_pf1550_config *const config = dev->config;
+	uint16_t idx;
+	uint8_t val;
+	int ret;
+
+	ret = linear_range_group_get_index(charger_battery_termination_uv_range,
+					   ARRAY_SIZE(charger_battery_termination_uv_range),
+					   voltage_uv, &idx);
+	if (ret < 0) {
+		return ret;
+	}
+
+	val = FIELD_PREP(BATT_REG_CHGCV_MASK, idx);
+
+	return i2c_reg_update_byte_dt(&config->bus, CHARGER_BATT_REG, BATT_REG_CHGCV_MASK, val);
+}
+
+static int pf1550_set_thermistor_mode(const struct device *dev, enum charger_pf1550_therm_mode mode)
+{
+	const struct charger_pf1550_config *const config = dev->config;
+	uint8_t val;
+
+	val = FIELD_PREP(THM_REG_CNFG_THM_CNFG_MASK, mode);
+
+	return i2c_reg_update_byte_dt(&config->bus, CHARGER_THM_REG_CNFG,
+				      THM_REG_CNFG_THM_CNFG_MASK, val);
+}
+
+static int pf1550_set_enabled(const struct device *dev, bool enable)
+{
+	struct charger_pf1550_data *data = dev->data;
+	const struct charger_pf1550_config *const config = dev->config;
+
+	int ret = i2c_reg_update_byte_dt(&config->bus, CHARGER_CHG_OPER, CHG_OPER_CHG_OPER_MASK,
+					 enable ? 2 : 0);
+
+	if (ret == 0) {
+		data->charger_enabled = enable;
+	}
+
+	return ret;
+}
+
+static int pf1550_get_interrupt_source(const struct device *dev, uint8_t *int_a)
+{
+	const struct charger_pf1550_config *config = dev->config;
+	uint8_t buf = 0;
+	int ret;
+
+	ret = i2c_reg_read_byte_dt(&config->bus, CHARGER_CHG_INT, &buf);
+
+	if (int_a) {
+		*int_a = buf;
+	}
+	return ret;
+}
+
+static int pf1550_enable_interrupts(const struct device *dev)
+{
+	const struct charger_pf1550_config *config = dev->config;
+	int ret;
+
+	ret = pf1550_get_interrupt_source(dev, NULL);
+	if (ret < 0) {
+		LOG_WRN("Failed to clear pending interrupts: %d", ret);
+		return ret;
+	}
+
+	return i2c_reg_write_byte_dt(&config->bus, CHARGER_CHG_INT_MASK, CHG_INT_ENABLE_ALL);
+}
+
+static int pf1550_led_config(const struct device *dev)
+{
+	struct charger_pf1550_data *data = dev->data;
+	const struct charger_pf1550_config *config = dev->config;
+	struct charger_pf1550_led_config *cfg = data->led_config;
+	int ret;
+	uint8_t val;
+
+	cfg->enabled = true;
+
+	if (cfg->behaviour == PF1550_LED_MANUAL_OFF) {
+		cfg->manual = true;
+		cfg->enabled = false;
+	}
+
+	val = (cfg->enabled ? LED_PWM_LED_EN : 0) | LED_PWM_FULL_ON;
+
+	ret = i2c_reg_write_byte_dt(&config->bus, CHARGER_LED_PWM, val);
+	if (ret < 0) {
+		return ret;
+	}
+
+	val = (cfg->manual ? LED_CNFG_LEDOVRD : 0) |
+	      (cfg->behaviour == PF1550_LED_FLASH_IN_CHARGING_ON_IN_FAULT ?
+	       LED_CNFG_LED_CFG : 0);
+
+	return i2c_reg_write_byte_dt(&config->bus, CHARGER_LED_CNFG, val);
+}
+
+static int pf1550_init_properties(const struct device *dev)
+{
+	struct charger_pf1550_data *data = dev->data;
+	const struct charger_pf1550_config *config = dev->config;
+	int ret;
+
+	data->charger_enabled = true;
+	data->charge_current_ua = config->charge_current_ua;
+	data->vbus_ilim_ua = config->vbus_ilim_ua;
+
+	ret = pf1550_get_charger_status(dev, &data->charger_status);
+	if (ret < 0) {
+		LOG_ERR("Failed to read charger status: %d", ret);
+		return ret;
+	}
+
+	ret = pf1550_get_charger_online(dev, &data->charger_online);
+	if (ret < 0) {
+		LOG_ERR("Failed to read charger online: %d", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+enum charger_pf1550_therm_mode pf1550_string_to_therm_mode(const char *mode_string)
+{
+	static const char *const modes[] = {
+		[PF1550_THERM_MODE_DISABLED] = "disabled",
+		[PF1550_THERM_MODE_THERMISTOR] = "thermistor",
+		[PF1550_THERM_MODE_JEITA_1] = "JEITA-1",
+		[PF1550_THERM_MODE_JEITA_2] = "JEITA-2",
+	};
+	enum charger_pf1550_therm_mode i;
+
+	for (i = PF1550_THERM_MODE_DISABLED; i < ARRAY_SIZE(modes); i++) {
+		if (strncmp(mode_string, modes[i], strlen(modes[i])) == 0) {
+			return i;
+		}
+	}
+
+	return PF1550_THERM_MODE_UNKNOWN;
+}
+
+static int pf1550_update_properties(const struct device *dev)
+{
+	struct charger_pf1550_data *data = dev->data;
+	const struct charger_pf1550_config *config = dev->config;
+	enum charger_pf1550_therm_mode therm_mode;
+	int ret;
+
+	ret = pf1550_set_vbus_ilim(dev, config->vbus_ilim_ua);
+	if (ret < 0) {
+		LOG_ERR("Failed to set vbus current limit: %d", ret);
+		return ret;
+	}
+
+	ret = pf1550_set_vsys_min(dev, config->vsys_min_uv);
+	if (ret < 0) {
+		LOG_ERR("Failed to set minimum system voltage threshold: %d", ret);
+		return ret;
+	}
+
+	ret = pf1550_set_charge_termination_uv(dev, config->charge_voltage_max_uv);
+	if (ret < 0) {
+		LOG_ERR("Failed to set recharge threshold: %d", ret);
+		return ret;
+	}
+
+	therm_mode = pf1550_string_to_therm_mode(config->therm_mon_mode);
+	ret = pf1550_set_thermistor_mode(dev, therm_mode);
+	if (ret < 0) {
+		LOG_ERR("Failed to set thermistor mode: %d", ret);
+		return ret;
+	}
+
+	ret = pf1550_set_constant_charge_current(dev, data->charge_current_ua);
+	if (ret < 0) {
+		LOG_ERR("Failed to set charge voltage: %d", ret);
+		return ret;
+	}
+
+	ret = pf1550_set_enabled(dev, data->charger_enabled);
+	if (ret < 0) {
+		LOG_ERR("Failed to set enabled: %d", ret);
+		return ret;
+	}
+
+	ret = pf1550_led_config(dev);
+	if (ret < 0) {
+		LOG_ERR("Failed to configure led: %d", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int pf1550_get_prop(const struct device *dev, charger_prop_t prop,
+			   union charger_propval *val)
+{
+	struct charger_pf1550_data *data = dev->data;
+
+	switch (prop) {
+	case CHARGER_PROP_ONLINE:
+		val->online = data->charger_online;
+		return 0;
+	case CHARGER_PROP_STATUS:
+		val->status = data->charger_status;
+		return 0;
+	case CHARGER_PROP_CONSTANT_CHARGE_CURRENT_UA:
+		val->const_charge_current_ua = data->charge_current_ua;
+		return 0;
+	default:
+		return -ENOTSUP;
+	}
+}
+
+static int pf1550_set_prop(const struct device *dev, charger_prop_t prop,
+			   const union charger_propval *val)
+{
+	struct charger_pf1550_data *data = dev->data;
+	int ret;
+
+	switch (prop) {
+	case CHARGER_PROP_CONSTANT_CHARGE_CURRENT_UA:
+		ret = pf1550_set_constant_charge_current(dev, val->const_charge_current_ua);
+		if (ret == 0) {
+			data->charge_current_ua = val->const_charge_current_ua;
+		}
+		return ret;
+	case CHARGER_PROP_INPUT_REGULATION_CURRENT_UA:
+		ret = pf1550_set_vbus_ilim(dev, val->input_current_regulation_current_ua);
+		if (ret == 0) {
+			data->vbus_ilim_ua = val->input_current_regulation_current_ua;
+		}
+		return ret;
+	case CHARGER_PROP_STATUS_NOTIFICATION:
+		data->charger_status_notifier = val->status_notification;
+		return 0;
+	case CHARGER_PROP_ONLINE_NOTIFICATION:
+		data->charger_online_notifier = val->online_notification;
+		return 0;
+	default:
+		return -ENOTSUP;
+	}
+}
+
+static int pf1550_enable_interrupt_pin(const struct device *dev, bool enabled)
+{
+	const struct charger_pf1550_config *const config = dev->config;
+	gpio_flags_t flags;
+	int ret;
+
+	flags = enabled ? GPIO_INT_EDGE_TO_ACTIVE : GPIO_INT_DISABLE;
+
+	ret = gpio_pin_interrupt_configure_dt(&config->int_gpio, flags);
+	if (ret < 0) {
+		LOG_ERR("Could not %s interrupt GPIO callback: %d", enabled ? "enable" : "disable",
+			ret);
+	}
+
+	return ret;
+}
+
+static void pf1550_gpio_callback(const struct device *dev, struct gpio_callback *cb, uint32_t pins)
+{
+	struct charger_pf1550_data *data = CONTAINER_OF(cb, struct charger_pf1550_data, gpio_cb);
+	int ret;
+
+	(void)pf1550_enable_interrupt_pin(data->dev, false);
+
+	ret = k_work_submit(&data->int_routine_work);
+	if (ret < 0) {
+		LOG_WRN("Could not submit int work: %d", ret);
+	}
+}
+
+static void pf1550_int_routine_work_handler(struct k_work *work)
+{
+	struct charger_pf1550_data *data =
+		CONTAINER_OF(work, struct charger_pf1550_data, int_routine_work);
+	uint8_t int_src;
+	int ret;
+
+	ret = pf1550_get_interrupt_source(data->dev, &int_src);
+	if (ret < 0) {
+		LOG_WRN("Failed to read interrupt source: %d", ret);
+		return;
+	}
+
+	LOG_DBG("Interrupt received: %x", int_src);
+
+	ret = pf1550_get_charger_status(data->dev, &data->charger_status);
+	if (ret < 0) {
+		LOG_WRN("Failed to read charger status: %d", ret);
+		return;
+	}
+
+	ret = pf1550_get_charger_online(data->dev, &data->charger_online);
+	if (ret < 0) {
+		LOG_WRN("Failed to read charger online %d", ret);
+		return;
+	}
+
+	if (data->charger_status_notifier != NULL) {
+		data->charger_status_notifier(data->charger_status);
+	}
+	if (data->charger_online_notifier != NULL) {
+		data->charger_online_notifier(data->charger_online);
+	}
+
+	if (data->charger_online != CHARGER_ONLINE_OFFLINE) {
+		(void)pf1550_update_properties(data->dev);
+	}
+
+	ret = k_work_reschedule(&data->int_enable_work, INT_ENABLE_DELAY);
+	if (ret < 0) {
+		LOG_WRN("Could not reschedule int_enable_work: %d", ret);
+	}
+}
+
+static void pf1550_int_enable_work_handler(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct charger_pf1550_data *data =
+		CONTAINER_OF(dwork, struct charger_pf1550_data, int_enable_work);
+
+	(void)pf1550_enable_interrupt_pin(data->dev, true);
+}
+
+static int pf1550_configure_interrupt_pin(const struct device *dev)
+{
+	struct charger_pf1550_data *data = dev->data;
+	const struct charger_pf1550_config *config = dev->config;
+	int ret;
+
+	ret = gpio_is_ready_dt(&config->int_gpio) ? 0 : -ENODEV;
+	if (ret < 0) {
+		LOG_ERR("Interrupt GPIO device not ready: %d", ret);
+		return ret;
+	}
+
+	ret = gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT);
+	if (ret < 0) {
+		LOG_ERR("Could not configure interrupt GPIO: %d", ret);
+		return ret;
+	}
+
+	gpio_init_callback(&data->gpio_cb, pf1550_gpio_callback, BIT(config->int_gpio.pin));
+	ret = gpio_add_callback_dt(&config->int_gpio, &data->gpio_cb);
+	if (ret < 0) {
+		LOG_ERR("Could not add interrupt GPIO callback: %d", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int pf1550_init(const struct device *dev)
+{
+	struct charger_pf1550_data *data = dev->data;
+	const struct charger_pf1550_config *config = dev->config;
+	int ret;
+
+	if (!i2c_is_ready_dt(&config->bus)) {
+		return -ENODEV;
+	}
+
+	data->dev = dev;
+
+	ret = pf1550_init_properties(dev);
+	if (ret < 0) {
+		return ret;
+	}
+
+	k_work_init(&data->int_routine_work, pf1550_int_routine_work_handler);
+	k_work_init_delayable(&data->int_enable_work, pf1550_int_enable_work_handler);
+
+	ret = pf1550_configure_interrupt_pin(dev);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = pf1550_enable_interrupt_pin(dev, true);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = pf1550_enable_interrupts(dev);
+	if (ret < 0) {
+		LOG_ERR("Failed to enable interrupts: %d", ret);
+		return ret;
+	}
+
+	ret = pf1550_update_properties(dev);
+	if (ret < 0) {
+		LOG_ERR("Failed to setup charger: %d", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(charger, pf1550_driver_api) = {
+	.get_property = pf1550_get_prop,
+	.set_property = pf1550_set_prop,
+	.charge_enable = pf1550_set_enabled,
+};
+
+#define PF1550_DEFINE(inst)                                                                        \
+	static struct charger_pf1550_led_config charger_pf1550_led_config_##inst = {               \
+		.behaviour = DT_INST_ENUM_IDX(inst, pf1550_led_behaviour),                         \
+	};                                                                                         \
+	static struct charger_pf1550_data charger_pf1550_data_##inst = {                           \
+		.led_config = &charger_pf1550_led_config_##inst,                                   \
+	};                                                                                         \
+	static const struct charger_pf1550_config charger_pf1550_config_##inst = {                 \
+		.bus = I2C_DT_SPEC_GET(DT_INST_PARENT(inst)),                                      \
+		.int_gpio = GPIO_DT_SPEC_INST_GET(inst, pf1550_int_gpios),                         \
+		.charge_current_ua = DT_INST_PROP(inst, constant_charge_current_max_microamp),     \
+		.vsys_min_uv = DT_INST_PROP(inst, pf1550_system_voltage_min_threshold_microvolt),  \
+		.therm_mon_mode = DT_INST_PROP(inst, pf1550_thermistor_monitoring_mode),           \
+		.vbus_ilim_ua = DT_INST_PROP(inst, pf1550_vbus_current_limit_microamp),            \
+		.charge_voltage_max_uv =                                                           \
+			DT_INST_PROP(inst, constant_charge_voltage_max_microvolt),                 \
+	};                                                                                         \
+												   \
+	DEVICE_DT_INST_DEFINE(inst, &pf1550_init, NULL, &charger_pf1550_data_##inst,               \
+			      &charger_pf1550_config_##inst, POST_KERNEL,                          \
+			      CONFIG_MFD_INIT_PRIORITY, &pf1550_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(PF1550_DEFINE)
diff --git a/drivers/charger/emul_sbs_charger.c b/drivers/charger/emul_sbs_charger.c
index 90c64b908ab..7e5202b6f79 100644
--- a/drivers/charger/emul_sbs_charger.c
+++ b/drivers/charger/emul_sbs_charger.c
@@ -17,7 +17,7 @@
 
 #include "sbs_charger.h"
 
-LOG_MODULE_REGISTER(sbs_sbs_charger);
+LOG_MODULE_REGISTER(sbs_sbs_charger, CONFIG_CHARGER_LOG_LEVEL);
 
 /** Static configuration for the emulator */
 struct sbs_charger_emul_cfg {
diff --git a/drivers/charger/sbs_charger.c b/drivers/charger/sbs_charger.c
index 3dc7f874a2d..15a5eeea773 100644
--- a/drivers/charger/sbs_charger.c
+++ b/drivers/charger/sbs_charger.c
@@ -17,7 +17,7 @@ struct sbs_charger_config {
 	struct i2c_dt_spec i2c;
 };
 
-LOG_MODULE_REGISTER(sbs_charger);
+LOG_MODULE_REGISTER(sbs_charger, CONFIG_CHARGER_LOG_LEVEL);
 
 static int sbs_cmd_reg_read(const struct device *dev, uint8_t reg_addr, uint16_t *val)
 {
diff --git a/drivers/clock_control/CMakeLists.txt b/drivers/clock_control/CMakeLists.txt
index 33ad557742a..bf2312736db 100644
--- a/drivers/clock_control/CMakeLists.txt
+++ b/drivers/clock_control/CMakeLists.txt
@@ -26,6 +26,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_DRIVER_CALIBRATION nrf_clo
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RV32M1_PCC          clock_control_rv32m1_pcc.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_INFINEON_CAT1       clock_control_ifx_cat1.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SAM                 clock_control_sam_pmc.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SILABS_SIWX91X      clock_control_silabs_siwx91x.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SILABS_SERIES       clock_control_silabs_series.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_PLL            clock_control_si32_pll.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SI32_AHB            clock_control_si32_ahb.c)
@@ -34,12 +35,14 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SMARTBOND           clock_cont
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NUMAKER_SCC         clock_control_numaker_scc.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NXP_S32             clock_control_nxp_s32.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA_CGC      clock_control_renesas_ra_cgc.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RZ_CPG      clock_control_renesas_rz_cpg.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AMBIQ               clock_control_ambiq.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_PWM                 clock_control_pwm.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RPI_PICO            clock_control_rpi_pico.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL   clock_control_nrf2_global_hsfll.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RTS5912_SCCON       clock_control_rts5912_sccon.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF2_AUDIOPLL       clock_control_nrf2_audiopll.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_IT51XXX             clock_control_it51xxx.c)
 
 if(CONFIG_CLOCK_CONTROL_NRF2)
   zephyr_library_sources(clock_control_nrf2_common.c)
@@ -49,17 +52,26 @@ if(CONFIG_CLOCK_CONTROL_NRF2)
   zephyr_library_sources(clock_control_nrf2_lfclk.c)
 endif()
 
+if(CONFIG_CLOCK_CONTROL_RENESAS_RZA2M_CPG)
+  zephyr_library_sources(clock_control_renesas_rza2m_cpg.c)
+  zephyr_library_sources(clock_control_renesas_rza2m_cpg_lld.c)
+endif()
+
 if(CONFIG_CLOCK_CONTROL_STM32_CUBE)
   zephyr_library_sources_ifdef(CONFIG_CLOCK_STM32_MUX clock_stm32_mux.c)
   zephyr_library_sources_ifdef(CONFIG_CLOCK_STM32_MCO clock_stm32_mco.c)
 if(CONFIG_SOC_SERIES_STM32MP1X)
   zephyr_library_sources(clock_stm32_ll_mp1.c)
+elseif(CONFIG_SOC_SERIES_STM32MP13X)
+  zephyr_library_sources(clock_stm32_ll_mp13.c)
 elseif(CONFIG_SOC_SERIES_STM32H7X)
   zephyr_library_sources(clock_stm32_ll_h7.c)
 elseif(CONFIG_SOC_SERIES_STM32H7RSX)
   zephyr_library_sources(clock_stm32_ll_h7.c)
 elseif(CONFIG_SOC_SERIES_STM32H5X)
   zephyr_library_sources(clock_stm32_ll_h5.c)
+elseif(CONFIG_SOC_SERIES_STM32N6X)
+  zephyr_library_sources(clock_stm32_ll_n6.c)
 elseif(CONFIG_SOC_SERIES_STM32U5X)
   zephyr_library_sources(clock_stm32_ll_u5.c)
 elseif(CONFIG_SOC_SERIES_STM32WB0X)
diff --git a/drivers/clock_control/Kconfig b/drivers/clock_control/Kconfig
index eec9b11c188..229a45792e8 100644
--- a/drivers/clock_control/Kconfig
+++ b/drivers/clock_control/Kconfig
@@ -88,6 +88,8 @@ source "drivers/clock_control/Kconfig.agilex5"
 
 source "drivers/clock_control/Kconfig.renesas_ra_cgc"
 
+source "drivers/clock_control/Kconfig.renesas_rz_cpg"
+
 source "drivers/clock_control/Kconfig.max32"
 
 source "drivers/clock_control/Kconfig.ambiq"
@@ -102,6 +104,10 @@ source "drivers/clock_control/Kconfig.arm_scmi"
 
 source "drivers/clock_control/Kconfig.silabs"
 
+source "drivers/clock_control/Kconfig.siwx91x"
+
 source "drivers/clock_control/Kconfig.wch_rcc"
 
+source "drivers/clock_control/Kconfig.it51xxx"
+
 endif # CLOCK_CONTROL
diff --git a/drivers/clock_control/Kconfig.it51xxx b/drivers/clock_control/Kconfig.it51xxx
new file mode 100644
index 00000000000..2619f96f6c2
--- /dev/null
+++ b/drivers/clock_control/Kconfig.it51xxx
@@ -0,0 +1,17 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config CLOCK_CONTROL_IT51XXX
+	bool "ITE IT51XXX clock controller driver"
+	default y
+	depends on DT_HAS_ITE_IT51XXX_ECPM_ENABLED
+	help
+	  This option enables the clock controller driver for IT51XXX.
+
+if CLOCK_CONTROL_IT51XXX
+
+config IT51XXX_PLL_SEQUENCE_PRIORITY
+	int
+	default 1
+
+endif # CLOCK_CONTROL_IT51XXX
diff --git a/drivers/clock_control/Kconfig.nrf b/drivers/clock_control/Kconfig.nrf
index f113a3284c2..0a3c7f652fb 100644
--- a/drivers/clock_control/Kconfig.nrf
+++ b/drivers/clock_control/Kconfig.nrf
@@ -202,12 +202,17 @@ config CLOCK_CONTROL_NRF2
 	depends on SOC_SERIES_NRF54HX && !RISCV_CORE_NORDIC_VPR
 	select ONOFF
 	select NRFS if HAS_NRFS
-	imply NRFS_LOCAL_DOMAIN_DVFS_SCALE_DOWN_AFTER_INIT if NRFS_DVFS_LOCAL_DOMAIN
 	help
 	  Support for nRF clock control devices.
 
 if CLOCK_CONTROL_NRF2
 
+config CLOCK_CONTROL_NRF2_HSFLL_REQ_LOW_FREQ
+	bool "Local domain scale down after init"
+	default y if NRFS_DVFS_LOCAL_DOMAIN
+	help
+	  Request the lowest operating point after DVFS initialization.
+
 config CLOCK_CONTROL_NRF2_NRFS_DVFS_TIMEOUT_MS
 	int "Timeout waiting for nrfs dvfs service callback in milliseconds"
 	default 2000
diff --git a/drivers/clock_control/Kconfig.renesas_rz_cpg b/drivers/clock_control/Kconfig.renesas_rz_cpg
new file mode 100644
index 00000000000..cca74792823
--- /dev/null
+++ b/drivers/clock_control/Kconfig.renesas_rz_cpg
@@ -0,0 +1,19 @@
+# Copyright (c) 2024-2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config CLOCK_CONTROL_RENESAS_RZ_CPG
+	bool "Renesas RZ/G Clock Control Driver"
+	default y
+	depends on DT_HAS_RENESAS_RZ_CPG_ENABLED
+	select USE_RZ_FSP_CPG
+	help
+	  Enable support for Renesas RZ CPG Clock Pulse Generator (CPG) driver.
+	  The CPG driver supports only module's clocks.
+	  The PLLs and core clocks are not configured by the CPG driver.
+
+config CLOCK_CONTROL_RENESAS_RZA2M_CPG
+	bool "Renesas RZ/A2M Clock Control Driver"
+	default y
+	depends on DT_HAS_RENESAS_RZA2M_CPG_ENABLED
+	help
+	  Enable support for Renesas RZ/A2M CPG Clock Pulse Generator (CPG) driver.
diff --git a/drivers/clock_control/Kconfig.rts5912 b/drivers/clock_control/Kconfig.rts5912
index ec5547cb91d..2ad6374c8d2 100644
--- a/drivers/clock_control/Kconfig.rts5912
+++ b/drivers/clock_control/Kconfig.rts5912
@@ -5,6 +5,7 @@
 
 config CLOCK_CONTROL_RTS5912_SCCON
 	bool "Realtek RTS5912 system clock controller driver"
+	depends on SOC_SERIES_RTS5912
 	default y if DT_HAS_REALTEK_RTS5912_SCCON_ENABLED
 	help
 	  Enable support for RTS5912 system clock controller driver
diff --git a/drivers/clock_control/Kconfig.siwx91x b/drivers/clock_control/Kconfig.siwx91x
new file mode 100644
index 00000000000..0aa0fc240b8
--- /dev/null
+++ b/drivers/clock_control/Kconfig.siwx91x
@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config CLOCK_CONTROL_SILABS_SIWX91X
+	bool "SiWx91x clock control driver"
+	default y
+	depends on DT_HAS_SILABS_SIWX91X_CLOCK_ENABLED
+	help
+	 Enable clock management on Silicon Labs SiWx91x chips. This driver
+	 includes support for HP (High Performace), ULP (Ultra Low Power), and
+	 ULP VBAT clocks.
+
+	 The original hardware allow to customize the various clocks offered for
+	 every devices. This driver does not provide such  customizations. It
+	 just hardcodes sane default parameters for every devices.
diff --git a/drivers/clock_control/Kconfig.stm32 b/drivers/clock_control/Kconfig.stm32
index 47a1b790a7b..9dacd04dbea 100644
--- a/drivers/clock_control/Kconfig.stm32
+++ b/drivers/clock_control/Kconfig.stm32
@@ -9,8 +9,9 @@ menuconfig CLOCK_CONTROL_STM32_CUBE
 	depends on SOC_FAMILY_STM32
 	default y
 	select USE_STM32_LL_UTILS
-	select USE_STM32_LL_RCC if (SOC_SERIES_STM32MP1X || SOC_SERIES_STM32H7X || \
-		SOC_SERIES_STM32H7RSX || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X)
+	select USE_STM32_LL_RCC if (SOC_SERIES_STM32MP1X || SOC_SERIES_STM32MP13X || SOC_SERIES_STM32H7X || \
+		SOC_SERIES_STM32H7RSX || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || \
+		SOC_SERIES_STM32N6X)
 	select RUNTIME_NMI if ($(dt_nodelabel_enabled,clk_hse) && \
 		$(dt_nodelabel_has_prop,clk_hse,css-enabled))
 	help
diff --git a/drivers/clock_control/clock_control_ambiq.c b/drivers/clock_control/clock_control_ambiq.c
index 77fdcbad6bd..436b5234fa3 100644
--- a/drivers/clock_control/clock_control_ambiq.c
+++ b/drivers/clock_control/clock_control_ambiq.c
@@ -11,7 +11,7 @@
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/drivers/pinctrl.h>
 #include <zephyr/drivers/clock_control/clock_control_ambiq.h>
-#include <am_mcu_apollo.h>
+#include <soc.h>
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(clock_control_ambiq, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
diff --git a/drivers/clock_control/clock_control_esp32.c b/drivers/clock_control/clock_control_esp32.c
index c594055d937..6ee615b9bba 100644
--- a/drivers/clock_control/clock_control_esp32.c
+++ b/drivers/clock_control/clock_control_esp32.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2020 Mohamed ElShahawi.
- * Copyright (c) 2021-2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2021-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -105,7 +105,8 @@ static void esp32_clock_perip_init(void)
 	soc_reset_reason_t rst_reason = esp_rom_get_reset_reason(0);
 
 	if ((rst_reason != RESET_REASON_CPU0_MWDT0) && (rst_reason != RESET_REASON_CPU0_MWDT1) &&
-	    (rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT)) {
+	    (rst_reason != RESET_REASON_CPU0_SW) && (rst_reason != RESET_REASON_CPU0_RTC_WDT) &&
+	    (rst_reason != RESET_REASON_CPU0_JTAG)) {
 
 		periph_ll_disable_clk_set_rst(PERIPH_UART1_MODULE);
 		periph_ll_disable_clk_set_rst(PERIPH_I2C0_MODULE);
@@ -193,10 +194,10 @@ static void esp32_clock_perip_init(void)
 		common_perip_clk =
 #if defined(CONFIG_SOC_SERIES_ESP32C2)
 			SYSTEM_SPI2_CLK_EN |
-#if ESP_CONSOLE_UART_NUM != 0
+#if CONFIG_ESP_CONSOLE_UART_NUM != 0
 			SYSTEM_UART_CLK_EN |
 #endif
-#if ESP_CONSOLE_UART_NUM != 1
+#if CONFIG_ESP_CONSOLE_UART_NUM != 1
 			SYSTEM_UART1_CLK_EN |
 #endif
 			SYSTEM_LEDC_CLK_EN |
@@ -205,14 +206,14 @@ static void esp32_clock_perip_init(void)
 #elif (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
 			SYSTEM_WDG_CLK_EN |
 			SYSTEM_I2S0_CLK_EN |
-#if ESP_CONSOLE_UART_NUM != 0
+#if CONFIG_ESP_CONSOLE_UART_NUM != 0
 			SYSTEM_UART_CLK_EN |
 #endif
-#if ESP_CONSOLE_UART_NUM != 1
+#if CONFIG_ESP_CONSOLE_UART_NUM != 1
 			SYSTEM_UART1_CLK_EN |
 #endif
 #if defined(CONFIG_SOC_SERIES_ESP32S3)
-#if ESP_CONSOLE_UART_NUM != 2
+#if CONFIG_ESP_CONSOLE_UART_NUM != 2
 			SYSTEM_UART2_CLK_EN |
 #endif
 			SYSTEM_USB_CLK_EN |
@@ -313,23 +314,23 @@ static void esp32_clock_perip_init(void)
 	common_perip_clk |=
 #if defined(CONFIG_SOC_SERIES_ESP32C2)
 			SYSTEM_SPI2_CLK_EN |
-#if ESP_CONSOLE_UART_NUM != 0
+#if CONFIG_ESP_CONSOLE_UART_NUM != 0
 			SYSTEM_UART_CLK_EN |
 #endif
-#if ESP_CONSOLE_UART_NUM != 1
+#if CONFIG_ESP_CONSOLE_UART_NUM != 1
 			SYSTEM_UART1_CLK_EN |
 #endif
 			SYSTEM_I2C_EXT0_CLK_EN;
 #elif (defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32S3))
 			SYSTEM_I2S0_CLK_EN |
-#if ESP_CONSOLE_UART_NUM != 0
+#if CONFIG_ESP_CONSOLE_UART_NUM != 0
 			SYSTEM_UART_CLK_EN |
 #endif
-#if ESP_CONSOLE_UART_NUM != 1
+#if CONFIG_ESP_CONSOLE_UART_NUM != 1
 			SYSTEM_UART1_CLK_EN |
 #endif
 #if defined(CONFIG_SOC_SERIES_ESP32S3)
-#if ESP_CONSOLE_UART_NUM != 2
+#if CONFIG_ESP_CONSOLE_UART_NUM != 2
 			SYSTEM_UART2_CLK_EN |
 #endif
 			SYSTEM_USB_CLK_EN |
@@ -354,15 +355,15 @@ static void esp32_clock_perip_init(void)
 			DPORT_UHCI1_CLK_EN |
 			DPORT_SPI3_CLK_EN |
 			DPORT_I2C_EXT1_CLK_EN |
-#if ESP_CONSOLE_UART_NUM != 0
+#if CONFIG_ESP_CONSOLE_UART_NUM != 0
 			DPORT_UART_CLK_EN |
 #endif
-#if ESP_CONSOLE_UART_NUM != 1
+#if CONFIG_ESP_CONSOLE_UART_NUM != 1
 			DPORT_UART1_CLK_EN |
 #endif
 #if defined(CONFIG_SOC_SERIES_ESP32)
 			DPORT_SPI_DMA_CLK_EN |
-#if ESP_CONSOLE_UART_NUM != 2
+#if CONFIG_ESP_CONSOLE_UART_NUM != 2
 			DPORT_UART2_CLK_EN |
 #endif
 #endif /* CONFIG_SOC_SERIES_ESP32 */
@@ -637,7 +638,7 @@ static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cf
 	rtc_clk_cfg.xtal_freq = cpu_cfg->xtal_freq;
 	rtc_clk_cfg.cpu_freq_mhz = cpu_cfg->cpu_freq;
 
-	esp_rom_uart_tx_wait_idle(ESP_CONSOLE_UART_NUM);
+	esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
 
 #if defined(CONFIG_SOC_SERIES_ESP32C6)
 	rtc_clk_modem_clock_domain_active_state_icg_map_preinit();
@@ -702,15 +703,15 @@ static int esp32_cpu_clock_configure(const struct esp32_cpu_clock_config *cpu_cf
 	esp_cpu_set_cycle_count((uint64_t)esp_cpu_get_cycle_count() * rtc_clk_cfg.cpu_freq_mhz /
 				old_config.freq_mhz);
 
-#if !defined(ESP_CONSOLE_UART_NONE)
+#if defined(CONFIG_ESP_CONSOLE_UART)
 #if !defined(CONFIG_SOC_SERIES_ESP32C2) && !defined(CONFIG_SOC_SERIES_ESP32C6)
 #if defined(CONFIG_MCUBOOT) && defined(ESP_ROM_UART_CLK_IS_XTAL)
 	uint32_t uart_clock_src_hz = (uint32_t)rtc_clk_xtal_freq_get() * MHZ(1);
 #else
 	uint32_t uart_clock_src_hz = esp_clk_apb_freq();
 #endif
-	esp_rom_uart_set_clock_baudrate(ESP_CONSOLE_UART_NUM, uart_clock_src_hz,
-					ESP_CONSOLE_UART_BAUDRATE);
+	esp_rom_uart_set_clock_baudrate(CONFIG_ESP_CONSOLE_UART_NUM, uart_clock_src_hz,
+					CONFIG_ESP_CONSOLE_UART_BAUDRATE);
 #endif
 #endif
 	return 0;
diff --git a/drivers/clock_control/clock_control_ifx_cat1.c b/drivers/clock_control/clock_control_ifx_cat1.c
index 7ed8493131c..071eb0e9559 100644
--- a/drivers/clock_control/clock_control_ifx_cat1.c
+++ b/drivers/clock_control/clock_control_ifx_cat1.c
@@ -533,9 +533,16 @@ static int clock_control_infineon_cat1_init(const struct device *dev)
 	clock_source_obj = _get_hal_obj_from_ord(GET_CLK_SOURCE_ORD(clk_hf3));
 	clock_div = DT_PROP(DT_NODELABEL(clk_hf3), clock_div);
 
+#if defined(CONFIG_SOC_FAMILY_INFINEON_CAT1B) && \
+		defined(CONFIG_USE_INFINEON_ADC)
+	Cy_SysClk_ClkHfSetSource(3, CY_SYSCLK_CLKHF_IN_CLKPATH1);
+	Cy_SysClk_ClkHfSetDivider(3, CY_SYSCLK_CLKHF_DIVIDE_BY_2);
+	Cy_SysClk_ClkHfEnable(3);
+#else
 	if (_configure_clk_hf(clock_obj, clock_source_obj, &CYHAL_CLOCK_HF[3], clock_div)) {
 		return -EIO;
 	}
+#endif
 #endif
 
 	/* Configure the HF[4] to source defined in tree device 'clk_hf4' node */
diff --git a/drivers/clock_control/clock_control_it51xxx.c b/drivers/clock_control/clock_control_it51xxx.c
new file mode 100644
index 00000000000..4cb5fdffef3
--- /dev/null
+++ b/drivers/clock_control/clock_control_it51xxx.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ite_it51xxx_ecpm
+
+#include <soc.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/dt-bindings/clock/ite-it51xxx-clock.h>
+#include <zephyr/dt-bindings/interrupt-controller/ite-it51xxx-intc.h>
+#include <zephyr/irq.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(clock_control_it51xxx, LOG_LEVEL_ERR);
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
+	     "only one ite,it51xxx-ecpm compatible node can be supported");
+
+/* it51xxx ECPM registers definition */
+/* 0x02: Clock Gating Control 2 register */
+#define ECPM_CGCTRL2R     0x02
+#define ECPM_CIRCG        BIT(5)
+#define ECPM_SWUCCG       BIT(4)
+/* 0x03: PLL Control */
+#define ECPM_PLLCTRL      0x03
+/* 0x04: Auto Clock Gating */
+#define ECPM_AUTOCG       0x04
+#define ECPM_AUART1CG     BIT(6)
+#define ECPM_AUART2CG     BIT(5)
+#define ECPM_ASSPICG      BIT(4)
+#define ECPM_ACIRCG       BIT(2)
+/* 0x02: Clock Gating Control 5 register */
+#define ECPM_CGCTRL3R     0x05
+#define ECPM_PECICG       BIT(3)
+#define ECPM_SSPICG       BIT(1)
+/* 0x06: PLL Frequency */
+#define ECPM_PLLFREQR     0x06
+#define ECPM_PLLFREQ_MASK GENMASK(3, 0)
+
+static const uint8_t pll_cfg[] = {
+	[PLL_18400_KHZ] = 0x01,
+	[PLL_32300_KHZ] = 0x03,
+	[PLL_64500_KHZ] = 0x07,
+	[PLL_48000_KHZ] = 0x09,
+};
+
+struct clock_control_it51xxx_data {
+	const uint8_t *pll_configuration;
+};
+
+/* Driver config */
+struct clock_control_it51xxx_config {
+	mm_reg_t ecpm_base;
+	int pll_freq;
+};
+
+/* Clock controller local functions */
+static inline int clock_control_it51xxx_on(const struct device *dev,
+					   clock_control_subsys_t sub_system)
+{
+	const struct clock_control_it51xxx_config *const config = dev->config;
+	struct ite_clk_cfg *clk_cfg = (struct ite_clk_cfg *)(sub_system);
+
+	/* Enable the clock of this module */
+	sys_write8(sys_read8(config->ecpm_base + clk_cfg->ctrl) & ~(clk_cfg->bits),
+		   config->ecpm_base + clk_cfg->ctrl);
+
+	return 0;
+}
+
+static inline int clock_control_it51xxx_off(const struct device *dev,
+					    clock_control_subsys_t sub_system)
+{
+	const struct clock_control_it51xxx_config *const config = dev->config;
+	struct ite_clk_cfg *clk_cfg = (struct ite_clk_cfg *)(sub_system);
+	uint8_t tmp_mask = 0;
+
+	/* CGCTRL3R, bit 6, must always write a 1. */
+	tmp_mask = (clk_cfg->ctrl == IT51XXX_ECPM_CGCTRL3R_OFF) ? 0x40 : 0x00;
+	sys_write8(sys_read8(config->ecpm_base + clk_cfg->ctrl) | clk_cfg->bits | tmp_mask,
+		   config->ecpm_base + clk_cfg->ctrl);
+
+	return 0;
+}
+
+static int clock_control_it51xxx_get_rate(const struct device *dev,
+					  clock_control_subsys_t sub_system, uint32_t *rate)
+{
+	const struct clock_control_it51xxx_config *const config = dev->config;
+	int reg_val = sys_read8(config->ecpm_base + ECPM_PLLFREQR) & ECPM_PLLFREQ_MASK;
+
+	switch (reg_val) {
+	case 0x01:
+		*rate = KHZ(18400);
+		break;
+	case 0x03:
+		*rate = KHZ(32300);
+		break;
+	case 0x07:
+		*rate = KHZ(64500);
+		break;
+	case 0x09:
+		*rate = KHZ(48000);
+		break;
+	default:
+		return -ERANGE;
+	}
+
+	return 0;
+}
+
+static void pll_change_isr(const void *unused)
+{
+	ARG_UNUSED(unused);
+
+	/*
+	 * We are here because we have completed changing PLL sequence,
+	 * so disabled PLL frequency change event interrupt.
+	 */
+	irq_disable(IT51XXX_IRQ_PLL_CHANGE);
+}
+
+static void chip_configure_pll(const struct device *dev, uint8_t pll)
+{
+	const struct clock_control_it51xxx_config *config = dev->config;
+
+	/* Set pll frequency change event */
+	IRQ_CONNECT(IT51XXX_IRQ_PLL_CHANGE, 0, pll_change_isr, NULL, IRQ_TYPE_EDGE_RISING);
+	/* Clear interrupt status of pll frequency change event */
+	ite_intc_isr_clear(IT51XXX_IRQ_PLL_CHANGE);
+
+	irq_enable(IT51XXX_IRQ_PLL_CHANGE);
+	/*
+	 * Configure PLL clock dividers.
+	 * Writing data to these registers doesn't change the PLL frequency immediately until the
+	 * status is changed into wakeup from the sleep mode.
+	 * The following code is intended to make the system enter sleep mode, and wait PLL
+	 * frequency change event to wakeup chip to complete PLL update.
+	 */
+	sys_write8(pll, config->ecpm_base + ECPM_PLLFREQR);
+
+	/* Chip sleep after wait for interrupt (wfi) instruction */
+	chip_pll_ctrl(CHIP_PLL_SLEEP);
+	/* Chip sleep and wait timer wake it up */
+	__asm__ volatile("wfi");
+	/* Chip sleep and wait timer wake it up */
+	chip_pll_ctrl(CHIP_PLL_DOZE);
+}
+
+static int clock_control_it51xxx_init(const struct device *dev)
+{
+	const struct clock_control_it51xxx_config *config = dev->config;
+	struct clock_control_it51xxx_data *data = dev->data;
+	int reg_val = sys_read8(config->ecpm_base + ECPM_PLLFREQR) & ECPM_PLLFREQ_MASK;
+	uint8_t autocg;
+
+	/* Disable auto gating and enable it by the respective module. */
+	autocg = sys_read8(config->ecpm_base + ECPM_AUTOCG);
+	sys_write8(autocg & ~(ECPM_AUART1CG | ECPM_AUART2CG | ECPM_ASSPICG | ECPM_ACIRCG),
+		   config->ecpm_base + ECPM_AUTOCG);
+
+	/* The following modules are gated in the initial state */
+	sys_write8(ECPM_CIRCG | ECPM_SWUCCG, config->ecpm_base + ECPM_CGCTRL2R);
+	sys_write8(sys_read8(config->ecpm_base + ECPM_CGCTRL3R) | ECPM_PECICG | ECPM_SSPICG,
+		   config->ecpm_base + ECPM_CGCTRL3R);
+
+	if (IS_ENABLED(CONFIG_ITE_IT51XXX_INTC)) {
+		ite_intc_save_and_disable_interrupts();
+	}
+
+	if (reg_val != data->pll_configuration[config->pll_freq]) {
+		/* configure PLL clock */
+		chip_configure_pll(dev, data->pll_configuration[config->pll_freq]);
+	}
+
+	if (IS_ENABLED(CONFIG_ITE_IT51XXX_INTC)) {
+		ite_intc_restore_interrupts();
+	}
+
+	return 0;
+}
+
+/* Clock controller driver registration */
+static DEVICE_API(clock_control, clock_control_it51xxx_api) = {
+	.on = clock_control_it51xxx_on,
+	.off = clock_control_it51xxx_off,
+	.get_rate = clock_control_it51xxx_get_rate,
+};
+
+static struct clock_control_it51xxx_data clock_control_it51xxx_data = {
+	.pll_configuration = pll_cfg,
+};
+
+static const struct clock_control_it51xxx_config clock_control_it51xxx_cfg = {
+	.ecpm_base = DT_INST_REG_ADDR(0),
+	.pll_freq = DT_INST_PROP(0, pll_frequency),
+};
+
+DEVICE_DT_INST_DEFINE(0, clock_control_it51xxx_init, NULL, &clock_control_it51xxx_data,
+		      &clock_control_it51xxx_cfg, PRE_KERNEL_1,
+		      CONFIG_IT51XXX_PLL_SEQUENCE_PRIORITY, &clock_control_it51xxx_api);
diff --git a/drivers/clock_control/clock_control_mcux_ccm.c b/drivers/clock_control/clock_control_mcux_ccm.c
index fa00eb18192..5ae8d71d979 100644
--- a/drivers/clock_control/clock_control_mcux_ccm.c
+++ b/drivers/clock_control/clock_control_mcux_ccm.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017,2024 NXP
+ * Copyright 2017, 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -81,6 +81,18 @@ static const clock_ip_name_t sai_clocks[] = {
 #endif
 #endif /* CONFIG_DAI_NXP_SAI */
 
+#if defined(CONFIG_I2C_NXP_II2C)
+static const clock_ip_name_t i2c_clk_root[] = {
+	kCLOCK_RootI2c1,
+	kCLOCK_RootI2c2,
+	kCLOCK_RootI2c3,
+	kCLOCK_RootI2c4,
+#ifdef CONFIG_SOC_MIMX8ML8
+	kCLOCK_RootI2c5,
+	kCLOCK_RootI2c6,
+#endif
+};
+#endif
 
 static int mcux_ccm_on(const struct device *dev,
 			      clock_control_subsys_t sub_system)
@@ -447,6 +459,31 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
 			(CLOCK_GetRootPostDivider(kCLOCK_RootEcspi3));
 		break;
 #endif /* CONFIG_SPI_MCUX_ECSPI */
+
+#if defined(CONFIG_I2C_NXP_II2C)
+	case IMX_CCM_I2C1_CLK:
+	case IMX_CCM_I2C2_CLK:
+	case IMX_CCM_I2C3_CLK:
+	case IMX_CCM_I2C4_CLK:
+#ifdef CONFIG_SOC_MIMX8ML8
+	case IMX_CCM_I2C5_CLK:
+	case IMX_CCM_I2C6_CLK:
+#endif
+	{
+		uint32_t instance = clock_name & IMX_CCM_INSTANCE_MASK;
+		uint32_t i2c_mux = CLOCK_GetRootMux(i2c_clk_root[instance]);
+
+		if (i2c_mux == 0) {
+			*rate = MHZ(24);
+		} else if (i2c_mux == 1) {
+			*rate = CLOCK_GetPllFreq(kCLOCK_SystemPll1Ctrl) /
+				(CLOCK_GetRootPreDivider(i2c_clk_root[instance])) /
+				(CLOCK_GetRootPostDivider(i2c_clk_root[instance])) /
+				5; /* SYSTEM PLL1 DIV5 */
+		}
+
+	} break;
+#endif
 	}
 
 	return 0;
diff --git a/drivers/clock_control/clock_control_mcux_ccm_rev2.c b/drivers/clock_control/clock_control_mcux_ccm_rev2.c
index 3151429fe03..dcca3f4eca9 100644
--- a/drivers/clock_control/clock_control_mcux_ccm_rev2.c
+++ b/drivers/clock_control/clock_control_mcux_ccm_rev2.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2021,2024 NXP
+ * Copyright 2021,2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -82,10 +82,16 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
 #endif
 
 #ifdef CONFIG_SPI_MCUX_LPSPI
+#if defined(CONFIG_SOC_SERIES_IMXRT118X)
+	case IMX_CCM_LPSPI0102_CLK:
+		clock_root = kCLOCK_Root_Lpspi0102 + instance;
+		break;
+#else
 	case IMX_CCM_LPSPI1_CLK:
 		clock_root = kCLOCK_Root_Lpspi1 + instance;
 		break;
-#endif
+#endif /* CONFIG_SOC_SERIES_IMXRT118X */
+#endif /* CONFIG_SPI_MCUX_LPSPI */
 
 #ifdef CONFIG_UART_MCUX_LPUART
 #if defined(CONFIG_SOC_SERIES_IMXRT118X)
@@ -117,6 +123,15 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
 		break;
 #endif
 
+#ifdef CONFIG_DMA_MCUX_EDMA_V4
+	case IMX_CCM_EDMA3_CLK:
+		clock_root = kCLOCK_Root_M33;
+		break;
+	case IMX_CCM_EDMA4_CLK:
+		clock_root = kCLOCK_Root_Wakeup_Axi;
+		break;
+#endif
+
 #ifdef CONFIG_PWM_MCUX
 #if defined(CONFIG_SOC_SERIES_IMXRT118X)
 	case IMX_CCM_PWM_CLK:
@@ -272,7 +287,7 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
 	default:
 		return -EINVAL;
 	}
-#ifdef CONFIG_SOC_MIMX9352
+#if defined(CONFIG_SOC_MIMX9352) || defined(CONFIG_SOC_MIMX9131)
 	*rate = CLOCK_GetIpFreq(clock_root);
 #else
 	*rate = CLOCK_GetRootClockFreq(clock_root);
diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c
index 2fb8acd79eb..ef0c83d3141 100644
--- a/drivers/clock_control/clock_control_mcux_syscon.c
+++ b/drivers/clock_control/clock_control_mcux_syscon.c
@@ -25,7 +25,7 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev,
 #endif /* defined(CONFIG_CAN_MCUX_MCAN) */
 #if defined(CONFIG_COUNTER_NXP_MRT)
 	if ((uint32_t)sub_system == MCUX_MRT_CLK) {
-#if defined(CONFIG_SOC_FAMILY_LPC) || defined(CONFIG_SOC_SERIES_RW6XX) ||\
+#if defined(CONFIG_SOC_FAMILY_LPC) || defined(CONFIG_SOC_SERIES_RW6XX) ||                          \
 	defined(CONFIG_SOC_SERIES_MCXN)
 		CLOCK_EnableClock(kCLOCK_Mrt);
 #elif defined(CONFIG_SOC_FAMILY_NXP_IMXRT)
@@ -59,9 +59,11 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev,
 	case MCUX_PORT3_CLK:
 		CLOCK_EnableClock(kCLOCK_GatePORT3);
 		break;
+#if (defined(FSL_FEATURE_SOC_PORT_COUNT) && (FSL_FEATURE_SOC_PORT_COUNT > 4))
 	case MCUX_PORT4_CLK:
 		CLOCK_EnableClock(kCLOCK_GatePORT4);
 		break;
+#endif /* defined(FSL_FEATURE_SOC_PORT_COUNT) */
 #else
 	case MCUX_PORT0_CLK:
 		CLOCK_EnableClock(kCLOCK_Port0);
@@ -242,14 +244,65 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de
 		*rate = CLOCK_GetLPFlexCommClkFreq(9);
 		break;
 
+	case MCUX_FLEXCOMM10_CLK:
+		*rate = CLOCK_GetLPFlexCommClkFreq(10);
+		break;
+
+	case MCUX_FLEXCOMM11_CLK:
+		*rate = CLOCK_GetLPFlexCommClkFreq(11);
+		break;
+
+	case MCUX_FLEXCOMM12_CLK:
+		*rate = CLOCK_GetLPFlexCommClkFreq(12);
+		break;
+
+	case MCUX_FLEXCOMM13_CLK:
+		*rate = CLOCK_GetLPFlexCommClkFreq(13);
+		break;
+
+	case MCUX_FLEXCOMM17_CLK:
+		*rate = CLOCK_GetLPFlexCommClkFreq(17);
+		break;
+
+	case MCUX_FLEXCOMM18_CLK:
+		*rate = CLOCK_GetLPFlexCommClkFreq(18);
+		break;
+
+	case MCUX_FLEXCOMM19_CLK:
+		*rate = CLOCK_GetLPFlexCommClkFreq(19);
+		break;
+
+	case MCUX_FLEXCOMM20_CLK:
+		*rate = CLOCK_GetLPFlexCommClkFreq(20);
+		break;
+#endif
+
+		/* On RT7xx, flexcomm14 and 16 only can be LPSPI, flexcomm15 only can be I2C. */
+#if defined(CONFIG_SOC_SERIES_IMXRT7XX) && defined(CONFIG_SOC_FAMILY_NXP_IMXRT)
+	case MCUX_LPSPI14_CLK:
+		*rate = CLOCK_GetLPSpiClkFreq(14);
+		break;
+	case MCUX_LPI2C15_CLK:
+		*rate = CLOCK_GetLPI2cClkFreq(15);
+		break;
+	case MCUX_LPSPI16_CLK:
+		*rate = CLOCK_GetLPSpiClkFreq(16);
+		break;
 #endif
 
 #if (defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT)
 
-#if CONFIG_SOC_SERIES_MCXN
+#if defined(CONFIG_SOC_SERIES_MCXN)
 	case MCUX_USDHC1_CLK:
 		*rate = CLOCK_GetUsdhcClkFreq();
 		break;
+#elif defined(CONFIG_SOC_SERIES_IMXRT7XX)
+	case MCUX_USDHC1_CLK:
+		*rate = CLOCK_GetUsdhcClkFreq(0);
+		break;
+	case MCUX_USDHC2_CLK:
+		*rate = CLOCK_GetUsdhcClkFreq(1);
+		break;
 #else
 	case MCUX_USDHC1_CLK:
 		*rate = CLOCK_GetSdioClkFreq(0);
@@ -289,6 +342,15 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de
 	case MCUX_CTIMER4_CLK:
 		*rate = CLOCK_GetCTimerClkFreq(4);
 		break;
+	case MCUX_CTIMER5_CLK:
+		*rate = CLOCK_GetCTimerClkFreq(5);
+		break;
+	case MCUX_CTIMER6_CLK:
+		*rate = CLOCK_GetCTimerClkFreq(6);
+		break;
+	case MCUX_CTIMER7_CLK:
+		*rate = CLOCK_GetCTimerClkFreq(7);
+		break;
 #endif
 
 #if defined(CONFIG_COUNTER_NXP_MRT)
@@ -314,6 +376,8 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de
 	case MCUX_I3C_CLK:
 #if CONFIG_SOC_SERIES_MCXN
 		*rate = CLOCK_GetI3cClkFreq(0);
+#elif CONFIG_SOC_SERIES_MCXA
+		*rate = CLOCK_GetI3CFClkFreq();
 #else
 		*rate = CLOCK_GetI3cClkFreq();
 #endif
@@ -338,7 +402,11 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de
 		*rate = CLOCK_GetMipiDphyEscTxClkFreq();
 		break;
 	case MCUX_LCDIF_PIXEL_CLK:
+#if defined(CONFIG_SOC_SERIES_IMXRT7XX) && defined(CONFIG_SOC_FAMILY_NXP_IMXRT)
+		*rate = CLOCK_GetLcdifClkFreq();
+#else
 		*rate = CLOCK_GetDcPixelClkFreq();
+#endif
 		break;
 #endif
 #if defined(CONFIG_AUDIO_DMIC_MCUX)
@@ -361,6 +429,21 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de
 #endif
 #endif /* CONFIG_MEMC_MCUX_FLEXSPI */
 
+#if defined(CONFIG_I2S_MCUX_SAI)
+	case MCUX_SAI0_CLK:
+#if (FSL_FEATURE_SOC_I2S_COUNT == 1)
+		*rate = CLOCK_GetSaiClkFreq();
+#else
+		*rate = CLOCK_GetSaiClkFreq(0);
+#endif
+		break;
+#if (FSL_FEATURE_SOC_I2S_COUNT == 2)
+	case MCUX_SAI1_CLK:
+		*rate = CLOCK_GetSaiClkFreq(1);
+		break;
+#endif
+#endif /* CONFIG_I2S_MCUX_SAI */
+
 #ifdef CONFIG_ETH_NXP_ENET_QOS
 	case MCUX_ENET_QOS_CLK:
 		*rate = CLOCK_GetFreq(kCLOCK_BusClk);
@@ -455,6 +538,27 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de
 		*rate = CLOCK_GetLpi2cClkFreq(3);
 		break;
 #endif /* defined(CONFIG_I2C_MCUX_LPI2C) */
+
+#if defined(CONFIG_DT_HAS_NXP_XSPI_ENABLED)
+	case MCUX_XSPI0_CLK:
+		*rate = CLOCK_GetXspiClkFreq(0);
+		break;
+	case MCUX_XSPI1_CLK:
+		*rate = CLOCK_GetXspiClkFreq(1);
+		break;
+	case MCUX_XSPI2_CLK:
+		*rate = CLOCK_GetXspiClkFreq(2);
+		break;
+#endif /* defined(CONFIG_DT_HAS_NXP_XSPI_ENABLED) */
+
+#if (defined(CONFIG_SPI_MCUX_LPSPI) && CONFIG_SOC_SERIES_MCXA)
+	case MCUX_LPSPI0_CLK:
+		*rate = CLOCK_GetLpspiClkFreq(0);
+		break;
+	case MCUX_LPSPI1_CLK:
+		*rate = CLOCK_GetLpspiClkFreq(1);
+		break;
+#endif /* defined(CONFIG_SPI_MCUX_LPSPI) */
 	}
 
 	return 0;
diff --git a/drivers/clock_control/clock_control_nrf2_global_hsfll.c b/drivers/clock_control/clock_control_nrf2_global_hsfll.c
index e79957eea71..69053c99ff2 100644
--- a/drivers/clock_control/clock_control_nrf2_global_hsfll.c
+++ b/drivers/clock_control/clock_control_nrf2_global_hsfll.c
@@ -132,7 +132,7 @@ static int api_cancel_or_release_global_hsfll(const struct device *dev,
 	return -EINVAL;
 }
 
-static struct nrf_clock_control_driver_api driver_api = {
+static DEVICE_API(nrf_clock_control, driver_api) = {
 	.std_api = {
 		.on = api_nosys_on_off,
 		.off = api_nosys_on_off,
diff --git a/drivers/clock_control/clock_control_nrf2_hsfll.c b/drivers/clock_control/clock_control_nrf2_hsfll.c
index 12ca616fad3..f67373070f1 100644
--- a/drivers/clock_control/clock_control_nrf2_hsfll.c
+++ b/drivers/clock_control/clock_control_nrf2_hsfll.c
@@ -218,6 +218,21 @@ static DEVICE_API(nrf_clock_control, hsfll_drv_api) = {
 static struct hsfll_dev_data hsfll_data;
 #endif
 
+#ifdef CONFIG_CLOCK_CONTROL_NRF2_HSFLL_REQ_LOW_FREQ
+static int dvfs_low_init(void)
+{
+	static const k_timeout_t timeout = K_MSEC(CONFIG_CLOCK_CONTROL_NRF2_NRFS_DVFS_TIMEOUT_MS);
+	static const struct device *hsfll_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_NODELABEL(cpu)));
+	static const struct nrf_clock_spec clk_spec = {
+		.frequency = HSFLL_FREQ_LOW
+	};
+
+	return nrf_clock_control_request_sync(hsfll_dev, &clk_spec, timeout);
+}
+
+SYS_INIT(dvfs_low_init, APPLICATION, 0);
+#endif
+
 DEVICE_DT_INST_DEFINE(0, hsfll_init, NULL,
 		      COND_CODE_1(CONFIG_NRFS_DVFS_LOCAL_DOMAIN,
 				  (&hsfll_data),
diff --git a/drivers/clock_control/clock_control_numaker_scc.c b/drivers/clock_control/clock_control_numaker_scc.c
index 1973030dd09..fe00c108b86 100644
--- a/drivers/clock_control/clock_control_numaker_scc.c
+++ b/drivers/clock_control/clock_control_numaker_scc.c
@@ -22,6 +22,39 @@ struct numaker_scc_config {
 	uint32_t core_clock;
 };
 
+#if defined(CONFIG_SOC_SERIES_M55M1X)
+static const uint64_t numaker_clkmodidx_tab[] = {
+	0x0000000000000000, 0x0000000000000400, 0x0000800000000000, 0x0001008000800000,
+	0x0001008000800480, 0x0001810203FF8000, 0x0001810203FF8488, 0x0002018003800000,
+	0x0002800000000000, 0x0003000000000000, 0x0003800000000000, 0x0004028283FF8000,
+	0x0004028001800080, 0x0004830301FF8000, 0x0005000000000000, 0x0005800000000000,
+	0x0005800000000400, 0x0005800000000800, 0x0005800000000C00, 0x0006000000000000,
+	0x0006838000800000, 0x0006838000800480, 0x0007000000000000, 0x0007000000000400,
+	0x0007000000000800, 0x0007000000000C00, 0x0007840000800000, 0x0007800000004000,
+	0x0008000000000000, 0x0008800000000000, 0x0008800000000400, 0x0008800000000800,
+	0x0008800000000C00, 0x0008800000001000, 0x0008800000001400, 0x0008800000001800,
+	0x0008800000001C00, 0x0008800000002000, 0x0008800000002400, 0x0009000000000000,
+	0x0009800000000000, 0x000A000000000000, 0x000A800000000000, 0x000A800000000400,
+	0x000A800000000800, 0x000A800000000C00, 0x000B048383FF8000, 0x000B048383FF8488,
+	0x000B850000800000, 0x000C000000000000, 0x000C858401FF8000, 0x000D000000000000,
+	0x000D860481FF8000, 0x000E000000000000, 0x000E800000000000, 0x000F000000000000,
+	0x000F868001800000, 0x0010000000000000, 0x0010870003800000, 0x0010870003800480,
+	0x0011078503878000, 0x0011800000000000, 0x0012800000000000, 0x0013000000000000,
+	0x0013800000000000, 0x0013800000000400, 0x0014080583FF8000, 0x0014888003800000,
+	0x0014888003800480, 0x0015000000000000, 0x0015890603FF8000, 0x0015890603FF8488,
+	0x0015890603FF8910, 0x0016000000000000, 0x0016898683FF8000, 0x0016898683FF8488,
+	0x00170A0003800000, 0x00170A0003800480, 0x00170A0003800900, 0x00170A0003800D80,
+	0x0017800000000000, 0x0018000000000000, 0x0018000000000400, 0x0018000000000800,
+	0x0018000000000C00, 0x0019800000000000, 0x001A8B0003800000, 0x001A8B0003800480,
+	0x001A8B0003800900, 0x001A8B0003800D80, 0x001B000000000000, 0x001B8B8003800000,
+	0x001B8B8003800480, 0x001C0C0783878000, 0x001C0C0783878484, 0x001C0C0783878908,
+	0x001C0C0783878D8C, 0x001C0C0783879210, 0x001C0C0783879694, 0x001C0C0783879B18,
+	0x001C0C0783879F9C, 0x001C0C880387A000, 0x001C0C880387A484, 0x001C8D0880878000,
+	0x001D0D0880878000, 0x001D800000000000, 0x001E000000000000, 0x001E8D8000800000,
+	0x001E8D8000800480, 0x001F0F8000800000, 0x001F0F8000800480,
+};
+#endif
+
 static inline int numaker_scc_on(const struct device *dev, clock_control_subsys_t subsys)
 {
 	ARG_UNUSED(dev);
@@ -30,7 +63,12 @@ static inline int numaker_scc_on(const struct device *dev, clock_control_subsys_
 
 	if (scc_subsys->subsys_id == NUMAKER_SCC_SUBSYS_ID_PCC) {
 		SYS_UnlockReg();
+#if defined(CONFIG_SOC_SERIES_M55M1X)
+		__ASSERT_NO_MSG(scc_subsys->pcc.clk_modidx < ARRAY_SIZE(numaker_clkmodidx_tab));
+		CLK_EnableModuleClock(numaker_clkmodidx_tab[scc_subsys->pcc.clk_modidx]);
+#else
 		CLK_EnableModuleClock(scc_subsys->pcc.clk_modidx);
+#endif
 		SYS_LockReg();
 	} else {
 		return -EINVAL;
@@ -47,7 +85,12 @@ static inline int numaker_scc_off(const struct device *dev, clock_control_subsys
 
 	if (scc_subsys->subsys_id == NUMAKER_SCC_SUBSYS_ID_PCC) {
 		SYS_UnlockReg();
+#if defined(CONFIG_SOC_SERIES_M55M1X)
+		__ASSERT_NO_MSG(scc_subsys->pcc.clk_modidx < ARRAY_SIZE(numaker_clkmodidx_tab));
+		CLK_DisableModuleClock(numaker_clkmodidx_tab[scc_subsys->pcc.clk_modidx]);
+#else
 		CLK_DisableModuleClock(scc_subsys->pcc.clk_modidx);
+#endif
 		SYS_LockReg();
 	} else {
 		return -EINVAL;
@@ -84,8 +127,15 @@ static inline int numaker_scc_configure(const struct device *dev, clock_control_
 
 	if (scc_subsys->subsys_id == NUMAKER_SCC_SUBSYS_ID_PCC) {
 		SYS_UnlockReg();
+#if defined(CONFIG_SOC_SERIES_M55M1X)
+		__ASSERT_NO_MSG(scc_subsys->pcc.clk_modidx < ARRAY_SIZE(numaker_clkmodidx_tab));
+		CLK_SetModuleClock(numaker_clkmodidx_tab[scc_subsys->pcc.clk_modidx],
+				   scc_subsys->pcc.clk_src,
+				   scc_subsys->pcc.clk_div);
+#else
 		CLK_SetModuleClock(scc_subsys->pcc.clk_modidx, scc_subsys->pcc.clk_src,
 				   scc_subsys->pcc.clk_div);
+#endif
 		SYS_LockReg();
 	} else {
 		return -EINVAL;
diff --git a/drivers/clock_control/clock_control_renesas_ra_cgc.c b/drivers/clock_control/clock_control_renesas_ra_cgc.c
index c58f090c903..23875fcc71a 100644
--- a/drivers/clock_control/clock_control_renesas_ra_cgc.c
+++ b/drivers/clock_control/clock_control_renesas_ra_cgc.c
@@ -23,6 +23,20 @@ static volatile uint32_t *mstp_regs[] = {
 static volatile uint32_t *mstp_regs[] = {};
 #endif
 
+#if defined(CONFIG_CORTEX_M_SYSTICK)
+/* If a CPU clock exists in the system, it will be the source for the CPU */
+#if BSP_FEATURE_CGC_HAS_CPUCLK
+#define sys_clk DT_NODELABEL(cpuclk)
+#else
+#define sys_clk DT_NODELABEL(iclk)
+#endif
+
+#define SYS_CLOCK_HZ (BSP_STARTUP_SOURCE_CLOCK_HZ / DT_PROP(sys_clk, div))
+
+BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == SYS_CLOCK_HZ,
+	     "CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC must match the configuration of the clock "
+	     "supplying the CPU ");
+#endif
 static int clock_control_renesas_ra_on(const struct device *dev, clock_control_subsys_t sys)
 {
 	struct clock_control_ra_subsys_cfg *subsys_clk = (struct clock_control_ra_subsys_cfg *)sys;
diff --git a/drivers/clock_control/clock_control_renesas_rz_cpg.c b/drivers/clock_control/clock_control_renesas_rz_cpg.c
new file mode 100644
index 00000000000..f220cc2e4d0
--- /dev/null
+++ b/drivers/clock_control/clock_control_renesas_rz_cpg.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/dt-bindings/clock/renesas_rzg_clock.h>
+#include <zephyr/kernel.h>
+
+#define DT_DRV_COMPAT renesas_rz_cpg
+
+static int clock_control_renesas_rz_on(const struct device *dev, clock_control_subsys_t sys)
+{
+	if (!dev || !sys) {
+		return -EINVAL;
+	}
+
+	uint32_t *clock_id = (uint32_t *)sys;
+
+	uint32_t ip = (*clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT;
+	uint32_t ch = (*clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT;
+
+	switch (ip) {
+	case RZ_IP_GTM:
+		R_BSP_MODULE_START(FSP_IP_GTM, ch);
+		break;
+	case RZ_IP_GPT:
+		R_BSP_MODULE_START(FSP_IP_GPT, ch);
+		break;
+	case RZ_IP_SCIF:
+		R_BSP_MODULE_START(FSP_IP_SCIF, ch);
+		break;
+	case RZ_IP_RIIC:
+		R_BSP_MODULE_START(FSP_IP_RIIC, ch);
+		break;
+	case RZ_IP_RSPI:
+		R_BSP_MODULE_START(FSP_IP_RSPI, ch);
+		break;
+	case RZ_IP_MHU:
+		R_BSP_MODULE_START(FSP_IP_MHU, ch);
+		break;
+	case RZ_IP_DMAC:
+		R_BSP_MODULE_START(FSP_IP_DMAC, ch);
+		break;
+	case RZ_IP_CANFD:
+		R_BSP_MODULE_START(FSP_IP_CANFD, ch);
+		break;
+	case RZ_IP_ADC:
+		R_BSP_MODULE_START(FSP_IP_ADC, ch);
+		break;
+	default:
+		return -EINVAL; /* Invalid FSP IP Module */
+	}
+
+	return 0;
+}
+
+static int clock_control_renesas_rz_off(const struct device *dev, clock_control_subsys_t sys)
+{
+	if (!dev || !sys) {
+		return -EINVAL;
+	}
+
+	uint32_t *clock_id = (uint32_t *)sys;
+
+	uint32_t ip = (*clock_id & RZ_IP_MASK) >> RZ_IP_SHIFT;
+	uint32_t ch = (*clock_id & RZ_IP_CH_MASK) >> RZ_IP_CH_SHIFT;
+
+	switch (ip) {
+	case RZ_IP_GTM:
+		R_BSP_MODULE_STOP(FSP_IP_GTM, ch);
+		break;
+	case RZ_IP_GPT:
+		R_BSP_MODULE_STOP(FSP_IP_GPT, ch);
+		break;
+	case RZ_IP_SCIF:
+		R_BSP_MODULE_STOP(FSP_IP_SCIF, ch);
+		break;
+	case RZ_IP_RIIC:
+		R_BSP_MODULE_STOP(FSP_IP_RIIC, ch);
+		break;
+	case RZ_IP_RSPI:
+		R_BSP_MODULE_STOP(FSP_IP_RSPI, ch);
+		break;
+	case RZ_IP_MHU:
+		R_BSP_MODULE_STOP(FSP_IP_MHU, ch);
+		break;
+	case RZ_IP_DMAC:
+		R_BSP_MODULE_STOP(FSP_IP_DMAC, ch);
+		break;
+	case RZ_IP_CANFD:
+		R_BSP_MODULE_STOP(FSP_IP_CANFD, ch);
+		break;
+	case RZ_IP_ADC:
+		R_BSP_MODULE_STOP(FSP_IP_ADC, ch);
+		break;
+	default:
+		return -EINVAL; /* Invalid */
+	}
+	return 0;
+}
+
+static int clock_control_renesas_rz_get_rate(const struct device *dev, clock_control_subsys_t sys,
+					     uint32_t *rate)
+{
+	if (!dev || !sys || !rate) {
+		return -EINVAL;
+	}
+
+	uint32_t *clock_id = (uint32_t *)sys;
+
+	fsp_priv_clock_t clk_src = (*clock_id & RZ_CLOCK_MASK) >> RZ_CLOCK_SHIFT;
+	uint32_t clk_div = (*clock_id & RZ_CLOCK_DIV_MASK) >> RZ_CLOCK_DIV_SHIFT;
+
+	uint32_t clk_hz = R_FSP_SystemClockHzGet(clk_src);
+	*rate = clk_hz / clk_div;
+	return 0;
+}
+
+static DEVICE_API(clock_control, rz_clock_control_driver_api) = {
+	.on = clock_control_renesas_rz_on,
+	.off = clock_control_renesas_rz_off,
+	.get_rate = clock_control_renesas_rz_get_rate,
+};
+
+static int clock_control_rz_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+	return 0;
+}
+
+DEVICE_DT_INST_DEFINE(0, clock_control_rz_init, NULL, NULL, NULL, PRE_KERNEL_1,
+		      CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &rz_clock_control_driver_api);
diff --git a/drivers/clock_control/clock_control_renesas_rza2m_cpg.c b/drivers/clock_control/clock_control_renesas_rza2m_cpg.c
new file mode 100644
index 00000000000..b7ee5316895
--- /dev/null
+++ b/drivers/clock_control/clock_control_renesas_rza2m_cpg.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_rza2m_cpg
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/clock_control.h>
+#include "clock_control_renesas_rza2m_cpg_lld.h"
+
+static int clock_control_renesas_rza2m_on_off(const struct device *dev, clock_control_subsys_t sys,
+					      bool enable)
+{
+	if (!dev || !sys) {
+		return -EINVAL;
+	}
+
+	int ret = -EINVAL;
+	uint32_t *clock_id = (uint32_t *)sys;
+	uint32_t clk_module = RZA2M_GET_MODULE(*clock_id);
+
+	ret = rza2m_cpg_mstp_clock_endisable(dev, clk_module, enable);
+
+	return ret;
+}
+
+static int clock_control_renesas_rza2m_on(const struct device *dev, clock_control_subsys_t sys)
+{
+	/* Enable the specified clock */
+	return clock_control_renesas_rza2m_on_off(dev, sys, true);
+}
+
+static int clock_control_renesas_rza2m_off(const struct device *dev, clock_control_subsys_t sys)
+{
+	/* Disable the specified clock */
+	return clock_control_renesas_rza2m_on_off(dev, sys, false);
+}
+
+static int clock_control_renesas_rza2m_get_rate(const struct device *dev,
+						clock_control_subsys_t sys, uint32_t *rate)
+{
+	if (!dev || !sys || !rate) {
+		return -EINVAL;
+	}
+
+	int ret = -EINVAL;
+	uint32_t *clock_id = (uint32_t *)sys;
+	enum rza2m_cpg_get_freq_src clk_src = RZA2M_GET_CLOCK_SRC(*clock_id);
+
+	ret = rza2m_cpg_get_clock(dev, clk_src, rate);
+
+	return ret;
+}
+
+static int clock_control_renesas_rza2m_set_rate(const struct device *dev,
+						clock_control_subsys_t sys,
+						clock_control_subsys_rate_t rate)
+{
+	int ret;
+	enum rza2m_cp_sub_clock clock_name = (enum rza2m_cp_sub_clock)sys;
+	uint32_t clock_rate = (uint32_t)rate;
+
+	ret = rza2m_cpg_set_sub_clock_divider(dev, clock_name, clock_rate);
+
+	return ret;
+}
+
+static int clock_control_renesas_rza2m_init(const struct device *dev)
+{
+	const struct rza2m_cpg_clock_config *config = dev->config;
+	uint16_t reg_val;
+
+	DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
+	rza2m_cpg_calculate_pll_frequency(dev);
+	/* Select Bφ Clock output for CLKIO */
+	sys_write16(0, CPG_REG_ADDR(CPG_CKIOSEL_OFFSET));
+
+	/* Enable CLKIO as Low-level output */
+	reg_val = sys_read16(CPG_REG_ADDR(CPG_FRQCR_OFFSET));
+	reg_val &= ~(CPG_FRQCR_CKOEN | CPG_FRQCR_CKOEN2);
+	reg_val |= (1U << CPG_FRQCR_CKOEN_SHIFT) | (1U << CPG_FRQCR_CKOEN2_SHIFT);
+	sys_write16(reg_val, CPG_REG_ADDR(CPG_FRQCR_OFFSET));
+
+	rza2m_cpg_set_sub_clock_divider(dev, CPG_SUB_CLOCK_ICLK, config->cpg_iclk_freq_hz_cfg);
+	rza2m_cpg_set_sub_clock_divider(dev, CPG_SUB_CLOCK_BCLK, config->cpg_bclk_freq_hz_cfg);
+	rza2m_cpg_set_sub_clock_divider(dev, CPG_SUB_CLOCK_P1CLK, config->cpg_p1clk_freq_hz_cfg);
+
+	return 0;
+}
+static DEVICE_API(clock_control, rza2m_clock_control_driver_api) = {
+	.on = clock_control_renesas_rza2m_on,
+	.off = clock_control_renesas_rza2m_off,
+	.get_rate = clock_control_renesas_rza2m_get_rate,
+	.set_rate = clock_control_renesas_rza2m_set_rate,
+};
+
+static const struct rza2m_cpg_clock_config g_rza2m_cpg_clock_config = {
+	DEVICE_MMIO_ROM_INIT(DT_DRV_INST(0)),
+	.cpg_extal_freq_hz_cfg = DT_INST_PROP_BY_PHANDLE(0, clocks, clock_frequency),
+	.cpg_iclk_freq_hz_cfg = DT_PROP(DT_NODELABEL(iclk), clock_frequency),
+	.cpg_bclk_freq_hz_cfg = DT_PROP(DT_NODELABEL(bclk), clock_frequency),
+	.cpg_p1clk_freq_hz_cfg = DT_PROP(DT_NODELABEL(p1clk), clock_frequency),
+};
+
+static struct rza2m_cpg_clock_data g_rza2m_cpg_clock_data;
+
+DEVICE_DT_INST_DEFINE(0, clock_control_renesas_rza2m_init, NULL, &g_rza2m_cpg_clock_data,
+		      &g_rza2m_cpg_clock_config, PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
+		      &rza2m_clock_control_driver_api);
diff --git a/drivers/clock_control/clock_control_renesas_rza2m_cpg_lld.c b/drivers/clock_control/clock_control_renesas_rza2m_cpg_lld.c
new file mode 100644
index 00000000000..da78dc2992c
--- /dev/null
+++ b/drivers/clock_control/clock_control_renesas_rza2m_cpg_lld.c
@@ -0,0 +1,438 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include "clock_control_renesas_rza2m_cpg_lld.h"
+
+static const struct rza2m_stb_module_info gs_stbcr[] = {
+	{MODULE_CORESIGHT, STBCR2_OFFSET, CPG_STBCR2_MSTP20},
+	{MODULE_OSTM0, STBCR3_OFFSET, CPG_STBCR3_MSTP36},
+	{MODULE_OSTM1, STBCR3_OFFSET, CPG_STBCR3_MSTP35},
+	{MODULE_OSTM2, STBCR3_OFFSET, CPG_STBCR3_MSTP34},
+	{MODULE_MTU3, STBCR3_OFFSET, CPG_STBCR3_MSTP33},
+	{MODULE_CANFD, STBCR3_OFFSET, CPG_STBCR3_MSTP32},
+	{MODULE_ADC, STBCR5_OFFSET, CPG_STBCR5_MSTP57},
+	{MODULE_GPT, STBCR3_OFFSET, CPG_STBCR3_MSTP30},
+	{MODULE_SCIFA0, STBCR4_OFFSET, CPG_STBCR4_MSTP47},
+	{MODULE_SCIFA1, STBCR4_OFFSET, CPG_STBCR4_MSTP46},
+	{MODULE_SCIFA2, STBCR4_OFFSET, CPG_STBCR4_MSTP45},
+	{MODULE_SCIFA3, STBCR4_OFFSET, CPG_STBCR4_MSTP44},
+	{MODULE_SCIFA4, STBCR4_OFFSET, CPG_STBCR4_MSTP43},
+	{MODULE_SCI0, STBCR4_OFFSET, CPG_STBCR4_MSTP42},
+	{MODULE_SCI1, STBCR4_OFFSET, CPG_STBCR4_MSTP41},
+	{MODULE_IrDA, STBCR4_OFFSET, CPG_STBCR4_MSTP40},
+	{MODULE_CEU, STBCR5_OFFSET, CPG_STBCR5_MSTP56},
+	{MODULE_RTC0, STBCR5_OFFSET, CPG_STBCR5_MSTP53},
+	{MODULE_RTC1, STBCR5_OFFSET, CPG_STBCR5_MSTP52},
+	{MODULE_JCU, STBCR5_OFFSET, CPG_STBCR5_MSTP51},
+	{MODULE_VIN, STBCR6_OFFSET, CPG_STBCR6_MSTP66},
+	{MODULE_ETHER, STBCR6_OFFSET,
+	 CPG_STBCR6_MSTP65 | CPG_STBCR6_MSTP64 | CPG_STBCR6_MSTP63 | CPG_STBCR6_MSTP62},
+	{MODULE_USB0, STBCR6_OFFSET, CPG_STBCR6_MSTP61},
+	{MODULE_USB1, STBCR6_OFFSET, CPG_STBCR6_MSTP60},
+	{MODULE_IMR2, STBCR7_OFFSET, CPG_STBCR7_MSTP77},
+	{MODULE_DRW, STBCR7_OFFSET, CPG_STBCR7_MSTP76},
+	{MODULE_MIPI, STBCR7_OFFSET, CPG_STBCR7_MSTP75},
+	{MODULE_SSIF0, STBCR7_OFFSET, CPG_STBCR7_MSTP73},
+	{MODULE_SSIF1, STBCR7_OFFSET, CPG_STBCR7_MSTP72},
+	{MODULE_SSIF2, STBCR7_OFFSET, CPG_STBCR7_MSTP71},
+	{MODULE_SSIF3, STBCR7_OFFSET, CPG_STBCR7_MSTP70},
+	{MODULE_I2C0, STBCR8_OFFSET, CPG_STBCR8_MSTP87},
+	{MODULE_I2C1, STBCR8_OFFSET, CPG_STBCR8_MSTP86},
+	{MODULE_I2C2, STBCR8_OFFSET, CPG_STBCR8_MSTP85},
+	{MODULE_I2C3, STBCR8_OFFSET, CPG_STBCR8_MSTP84},
+	{MODULE_SPIBSC, STBCR8_OFFSET, CPG_STBCR8_MSTP83},
+	{MODULE_VDC6, STBCR8_OFFSET, CPG_STBCR8_MSTP81},
+	{MODULE_RSPI0, STBCR9_OFFSET, CPG_STBCR9_MSTP97},
+	{MODULE_RSPI1, STBCR9_OFFSET, CPG_STBCR9_MSTP96},
+	{MODULE_RSPI2, STBCR9_OFFSET, CPG_STBCR9_MSTP95},
+	{MODULE_HYPERBUS, STBCR9_OFFSET, CPG_STBCR9_MSTP93},
+	{MODULE_OCTAMEM, STBCR9_OFFSET, CPG_STBCR9_MSTP92},
+	{MODULE_RSPDIF, STBCR9_OFFSET, CPG_STBCR9_MSTP91},
+	{MODULE_DRP, STBCR9_OFFSET, CPG_STBCR9_MSTP90},
+	{MODULE_TSIP, STBCR10_OFFSET, CPG_STBCR10_MSTP107},
+	{MODULE_NAND, STBCR10_OFFSET, CPG_STBCR10_MSTP104},
+	{MODULE_SDMMC0, STBCR10_OFFSET, CPG_STBCR10_MSTP103 | CPG_STBCR10_MSTP102},
+	{MODULE_SDMMC1, STBCR10_OFFSET, CPG_STBCR10_MSTP101 | CPG_STBCR10_MSTP100},
+};
+
+static const struct rza2m_stb_module_info gs_stbreq[] = {
+	{MODULE_CORESIGHT, STBREQ1_OFFSET, CPG_STBREQ1_STBRQ15},
+	{MODULE_CEU, STBREQ1_OFFSET, CPG_STBREQ1_STBRQ10},
+	{MODULE_JCU, STBREQ1_OFFSET, CPG_STBREQ1_STBRQ13},
+	{MODULE_VIN, STBREQ2_OFFSET, CPG_STBREQ2_STBRQ27},
+	{MODULE_ETHER, STBREQ2_OFFSET, CPG_STBREQ2_STBRQ26},
+	{MODULE_USB0, STBREQ3_OFFSET, CPG_STBREQ3_STBRQ31 | CPG_STBREQ3_STBRQ30},
+	{MODULE_USB1, STBREQ3_OFFSET, CPG_STBREQ3_STBRQ33 | CPG_STBREQ3_STBRQ32},
+	{MODULE_IMR2, STBREQ2_OFFSET, CPG_STBREQ2_STBRQ23},
+	{MODULE_DRW, STBREQ2_OFFSET, CPG_STBREQ2_STBRQ21 | CPG_STBREQ2_STBRQ20},
+	{MODULE_VDC6, STBREQ2_OFFSET, CPG_STBREQ2_STBRQ25},
+	{MODULE_DRP, STBREQ2_OFFSET, CPG_STBREQ2_STBRQ24},
+	{MODULE_NAND, STBREQ2_OFFSET, CPG_STBREQ2_STBRQ22},
+	{MODULE_SDMMC0, STBREQ1_OFFSET, CPG_STBREQ1_STBRQ12},
+	{MODULE_SDMMC1, STBREQ1_OFFSET, CPG_STBREQ1_STBRQ11},
+};
+
+static const struct rza2m_stb_module_info gs_stback[] = {
+	{MODULE_CORESIGHT, STBACK1_OFFSET, CPG_STBACK1_STBAK15},
+	{MODULE_CEU, STBACK1_OFFSET, CPG_STBACK1_STBAK10},
+	{MODULE_JCU, STBACK1_OFFSET, CPG_STBACK1_STBAK13},
+	{MODULE_VIN, STBACK2_OFFSET, CPG_STBACK2_STBAK27},
+	{MODULE_ETHER, STBACK2_OFFSET, CPG_STBACK2_STBAK26},
+	{MODULE_USB0, STBACK3_OFFSET, CPG_STBACK3_STBAK31 | CPG_STBACK3_STBAK30},
+	{MODULE_USB1, STBACK3_OFFSET, CPG_STBACK3_STBAK33 | CPG_STBACK3_STBAK32},
+	{MODULE_IMR2, STBACK2_OFFSET, CPG_STBACK2_STBAK23},
+	{MODULE_DRW, STBACK2_OFFSET, CPG_STBACK2_STBAK21 | CPG_STBACK2_STBAK20},
+	{MODULE_VDC6, STBACK2_OFFSET, CPG_STBACK2_STBAK25},
+	{MODULE_DRP, STBACK2_OFFSET, CPG_STBACK2_STBAK24},
+	{MODULE_NAND, STBACK2_OFFSET, CPG_STBACK2_STBAK22},
+	{MODULE_SDMMC0, STBACK1_OFFSET, CPG_STBACK1_STBAK12},
+	{MODULE_SDMMC1, STBACK1_OFFSET, CPG_STBACK1_STBAK11},
+};
+
+void rza2m_pl310_set_standby_mode(void)
+{
+	uint32_t reg_val;
+
+	/* Read current register value */
+	reg_val = sys_read32(PL310_BASE_ADDR + PL310_PWR_CTRL_OFFSET);
+
+	/* Set standby mode enable bit */
+	reg_val |= BIT(PL310_PWR_CTRL_STANDBY_MODE_EN_SHIFT);
+
+	sys_write32(reg_val, PL310_BASE_ADDR + PL310_PWR_CTRL_OFFSET);
+	sys_read32(PL310_BASE_ADDR + PL310_PWR_CTRL_OFFSET);
+}
+
+void rza2m_cpg_calculate_pll_frequency(const struct device *dev)
+{
+	const struct rza2m_cpg_clock_config *config = dev->config;
+	struct rza2m_cpg_clock_data *data = dev->data;
+
+	data->cpg_extal_frequency_hz = config->cpg_extal_freq_hz_cfg;
+
+	if ((data->cpg_extal_frequency_hz >= RZA2M_CPG_MHZ(10)) &&
+	    (data->cpg_extal_frequency_hz <= RZA2M_CPG_MHZ(12))) {
+		data->cpg_pll_frequency_hz = data->cpg_extal_frequency_hz * 88;
+	} else if ((data->cpg_extal_frequency_hz >= RZA2M_CPG_MHZ(20)) &&
+		   (data->cpg_extal_frequency_hz <= RZA2M_CPG_MHZ(24))) {
+		data->cpg_pll_frequency_hz = data->cpg_extal_frequency_hz * 44;
+	}
+}
+
+static void rza2m_cpg_change_reg_bits(mem_addr_t reg, uint8_t bitmask, bool enable)
+{
+	uint8_t reg_val;
+
+	reg_val = sys_read8(reg);
+
+	if (enable) {
+		reg_val &= ~bitmask;
+	} else {
+		reg_val |= bitmask;
+	}
+
+	sys_write8(reg_val, reg);
+	sys_read8(reg);
+}
+
+static const struct rza2m_stb_module_info *rza2m_cpg_get_stbcr_info(enum rza2m_stb_module module)
+{
+	size_t index;
+	size_t count = ARRAY_SIZE(gs_stbcr);
+
+	for (index = 0; index < count; index++) {
+		if (module == gs_stbcr[index].module) {
+			return &gs_stbcr[index];
+		}
+	}
+
+	/* Return NULL if not found */
+	return NULL;
+}
+
+static const struct rza2m_stb_module_info *rza2m_cpg_get_stbreq_info(enum rza2m_stb_module module)
+{
+	size_t index;
+	size_t count = ARRAY_SIZE(gs_stbreq);
+
+	for (index = 0; index < count; index++) {
+		if (module == gs_stbreq[index].module) {
+			return &gs_stbreq[index];
+		}
+	}
+
+	/* Return NULL if not found */
+	return NULL;
+}
+
+static const struct rza2m_stb_module_info *rza2m_cpg_get_stback_info(enum rza2m_stb_module module)
+{
+	size_t index;
+	size_t count = ARRAY_SIZE(gs_stback);
+
+	for (index = 0; index < count; index++) {
+		if (module == gs_stback[index].module) {
+			return &gs_stback[index];
+		}
+	}
+
+	/* Return NULL if not found */
+	return NULL;
+}
+
+static uint8_t rza2m_cpg_wait_bit_val(uint32_t reg_addr, uint8_t bit_mask, uint8_t bits_val,
+				      int32_t us_wait)
+{
+	uint8_t reg_val;
+	int32_t wait_cnt = (us_wait / 5);
+
+	do {
+		reg_val = sys_read8(reg_addr) & bit_mask;
+
+		if (reg_val == bits_val) {
+			break;
+		}
+
+		if (wait_cnt > 0) {
+			k_busy_wait(5);
+		}
+	} while (wait_cnt-- > 0);
+
+	return reg_val;
+}
+
+int rza2m_cpg_mstp_clock_endisable(const struct device *dev, enum rza2m_stb_module module,
+				   bool enable)
+{
+	uint8_t reg_val = 0;
+	const struct rza2m_stb_module_info *p_stbcr;
+	const struct rza2m_stb_module_info *p_stbreq;
+	const struct rza2m_stb_module_info *p_stback;
+
+	/* Obtain the STBCR information */
+	p_stbcr = rza2m_cpg_get_stbcr_info(module);
+
+	/* Check if unsupported module */
+	if (NULL != p_stbcr) {
+		rza2m_cpg_change_reg_bits(CPG_REG_ADDR(p_stbcr->reg_offset), p_stbcr->mask, enable);
+	} else {
+		return -ENOTSUP;
+	}
+
+	p_stbreq = rza2m_cpg_get_stbreq_info(module);
+	p_stback = rza2m_cpg_get_stback_info(module);
+
+	if ((NULL != p_stback) && (NULL != p_stbreq)) {
+		rza2m_cpg_change_reg_bits(CPG_REG_ADDR(p_stbreq->reg_offset), p_stbreq->mask,
+					  enable);
+		reg_val = rza2m_cpg_wait_bit_val(CPG_REG_ADDR(p_stback->reg_offset), p_stbreq->mask,
+						 0, STBACK_REG_WAIT_US);
+		if (reg_val) {
+			return -EIO;
+		}
+	}
+
+	return 0;
+}
+
+static int rza2m_cpg_modify_frqcr(const struct device *dev, enum rza2m_cp_sub_clock clk_sub_src,
+				  uint32_t sub_clk_frequency_hz, uint16_t *p_frqcr)
+{
+	struct rza2m_cpg_clock_data *data = dev->data;
+	uint16_t div_d;
+	uint16_t fc;
+
+	/* Avoid divide by zero */
+	if (sub_clk_frequency_hz == 0) {
+		return -EINVAL;
+	}
+
+	div_d = data->cpg_pll_frequency_hz / sub_clk_frequency_hz;
+
+	if (CPG_SUB_CLOCK_ICLK == clk_sub_src) {
+		if (div_d == 2) {
+			fc = 0;
+		} else if (div_d == 4) {
+			fc = 1;
+		} else if (div_d == 8) {
+			fc = 2;
+		} else if (div_d == 16) {
+			fc = 3;
+		} else {
+			return -EINVAL;
+		}
+		/* Clear IFC bit */
+		(*p_frqcr) &= (uint16_t)(~CPG_FRQCR_IFC);
+
+		/* Modify IFC bit */
+		(*p_frqcr) |= (uint16_t)(fc << CPG_FRQCR_IFC_SHIFT);
+	} else if (CPG_SUB_CLOCK_BCLK == clk_sub_src) {
+		if (div_d == 8) {
+			fc = 1;
+		} else if (div_d == 16) {
+			fc = 2;
+		} else if (div_d == 32) {
+			fc = 3;
+		} else {
+			return -EINVAL;
+		}
+
+		/* Clear BFC bit */
+		(*p_frqcr) &= (uint16_t)(~CPG_FRQCR_BFC);
+
+		/* Modify BFC bit */
+		(*p_frqcr) |= (uint16_t)(fc << CPG_FRQCR_BFC_SHIFT);
+	} else if (CPG_SUB_CLOCK_P1CLK == clk_sub_src) {
+		if (div_d == 16) {
+			fc = 2;
+		} else if (div_d == 32) {
+			fc = 3;
+		} else {
+			return -EINVAL;
+		}
+
+		/* Clear PFC bit */
+		(*p_frqcr) &= (uint16_t)(~CPG_FRQCR_PFC);
+
+		/* Modify PFC bit */
+		(*p_frqcr) |= (uint16_t)(fc << CPG_FRQCR_PFC_SHIFT);
+	} else {
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+int rza2m_cpg_set_sub_clock_divider(const struct device *dev, enum rza2m_cp_sub_clock clk_sub_src,
+				    uint32_t sub_clk_frequency_hz)
+{
+	struct rza2m_cpg_clock_data *data = dev->data;
+	uint16_t frqcr;
+	uint16_t check_frqcr;
+	int ret;
+
+	/* Read previous settings */
+	frqcr = sys_read16(CPG_REG_ADDR(CPG_FRQCR_OFFSET));
+
+	ret = rza2m_cpg_modify_frqcr(dev, clk_sub_src, sub_clk_frequency_hz, &frqcr);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* Check unless valid combination */
+	check_frqcr = frqcr & (CPG_FRQCR_IFC | CPG_FRQCR_BFC | CPG_FRQCR_PFC);
+	switch (check_frqcr) {
+	case 0x012: /* "VALID":do nothing, fall through */
+	case 0x112: /* "VALID":do nothing, fall through */
+	case 0x212: /* "VALID":do nothing, fall through */
+	case 0x322: /* "VALID":do nothing, fall through */
+	case 0x333: /* "VALID":do nothing, fall through */
+		break;
+	default:
+		return !EINVAL;
+	}
+
+	/* Update local divisor variables based on the clock type */
+	switch (clk_sub_src) {
+	case CPG_SUB_CLOCK_ICLK:
+		switch ((frqcr & CPG_FRQCR_IFC) >> CPG_FRQCR_IFC_SHIFT) {
+		case 0:
+			data->cpg_iclk_divisor = 2;
+			break;
+		case 1:
+			data->cpg_iclk_divisor = 4;
+			break;
+		case 2:
+			data->cpg_iclk_divisor = 8;
+			break;
+		case 3:
+			data->cpg_iclk_divisor = 16;
+			break;
+		default:
+			break;
+		}
+		data->cpg_iclk_frequency_hz = data->cpg_pll_frequency_hz / data->cpg_iclk_divisor;
+		break;
+
+	case CPG_SUB_CLOCK_BCLK:
+		switch ((frqcr & CPG_FRQCR_BFC) >> CPG_FRQCR_BFC_SHIFT) {
+		case 1:
+			data->cpg_bclk_divisor = 8;
+			break;
+		case 2:
+			data->cpg_bclk_divisor = 16;
+			break;
+		case 3:
+			data->cpg_bclk_divisor = 32;
+			break;
+		default:
+			break;
+		}
+		data->cpg_bclk_frequency_hz = data->cpg_pll_frequency_hz / data->cpg_bclk_divisor;
+		break;
+
+	case CPG_SUB_CLOCK_P1CLK:
+		switch ((frqcr & CPG_FRQCR_PFC) >> CPG_FRQCR_PFC_SHIFT) {
+		case 2:
+			data->cpg_p1clk_divisor = 16;
+			break;
+		case 3:
+			data->cpg_p1clk_divisor = 32;
+			break;
+		default:
+			break;
+		}
+		data->cpg_p1clk_frequency_hz = data->cpg_pll_frequency_hz / data->cpg_p1clk_divisor;
+		break;
+
+	default:
+		return -ENOTSUP;
+	}
+
+	rza2m_pl310_set_standby_mode();
+	sys_write16(frqcr, CPG_REG_ADDR(CPG_FRQCR_OFFSET));
+	sys_read16(CPG_REG_ADDR(CPG_FRQCR_OFFSET));
+
+	return 0;
+}
+
+int rza2m_cpg_get_clock(const struct device *dev, enum rza2m_cpg_get_freq_src src, uint32_t *p_freq)
+{
+	struct rza2m_cpg_clock_data *data = dev->data;
+
+	if (NULL == p_freq) {
+		return -EINVAL;
+	}
+
+	switch (src) {
+	case CPG_FREQ_EXTAL:
+		*p_freq = data->cpg_extal_frequency_hz;
+		break;
+	case CPG_FREQ_ICLK:
+		*p_freq = data->cpg_iclk_frequency_hz;
+		break;
+	case CPG_FREQ_GCLK:
+		*p_freq = (data->cpg_pll_frequency_hz * 2) / data->cpg_bclk_divisor;
+		break;
+	case CPG_FREQ_BCLK:
+		*p_freq = data->cpg_bclk_frequency_hz;
+		break;
+	case CPG_FREQ_P1CLK:
+		*p_freq = data->cpg_p1clk_frequency_hz;
+		break;
+	case CPG_FREQ_P0CLK:
+		*p_freq = data->cpg_pll_frequency_hz / 32;
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
diff --git a/drivers/clock_control/clock_control_renesas_rza2m_cpg_lld.h b/drivers/clock_control/clock_control_renesas_rza2m_cpg_lld.h
new file mode 100644
index 00000000000..7944fe50d77
--- /dev/null
+++ b/drivers/clock_control/clock_control_renesas_rza2m_cpg_lld.h
@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RZA2M_CPG_LLD_H_
+#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RZA2M_CPG_LLD_H_
+
+#include <stdint.h>
+#include <zephyr/dt-bindings/clock/renesas_rza2m_clock.h>
+
+struct rza2m_cpg_clock_config {
+	DEVICE_MMIO_ROM;
+	uint32_t cpg_extal_freq_hz_cfg;
+	uint32_t cpg_iclk_freq_hz_cfg;
+	uint32_t cpg_bclk_freq_hz_cfg;
+	uint32_t cpg_p1clk_freq_hz_cfg;
+};
+
+struct rza2m_cpg_clock_data {
+	DEVICE_MMIO_RAM;
+	uint32_t cpg_extal_frequency_hz;
+	uint32_t cpg_pll_frequency_hz;
+	uint32_t cpg_iclk_divisor;
+	uint32_t cpg_iclk_frequency_hz;
+	uint32_t cpg_bclk_divisor;
+	uint32_t cpg_bclk_frequency_hz;
+	uint32_t cpg_p1clk_divisor;
+	uint32_t cpg_p1clk_frequency_hz;
+};
+
+#define PL310_BASE_ADDR                      0x1F003000UL
+#define PL310_PWR_CTRL_OFFSET                0xF80UL
+#define PL310_PWR_CTRL_STANDBY_MODE_EN_SHIFT 0UL
+
+#define STBACK_REG_WAIT_US 50
+#define RZA2M_CPG_KHZ(khz) ((khz) * 1000U)
+#define RZA2M_CPG_MHZ(mhz) (RZA2M_CPG_KHZ(mhz) * 1000U)
+
+#define CPG_BASE_ADDR      DEVICE_MMIO_GET(dev)
+#define CPG_FRQCR_OFFSET   0x0UL
+#define CPG_CKIOSEL_OFFSET 0xF0UL
+#define CPG_SCLKSEL_OFFSET 0xF4UL
+#define CPG_REG_ADDR(off)  ((mm_reg_t)(CPG_BASE_ADDR + (off)))
+
+#define RZA2M_GET_MODULE(clock_id)    ((clock_id >> RZA2M_MODULE_SHIFT) & 0xFF)
+#define RZA2M_GET_CLOCK_SRC(clock_id) ((clock_id >> RZA2M_CLOCK_SRC_SHIFT) & 0xFF)
+
+#define STBCR1_OFFSET  0x10UL
+#define STBCR2_OFFSET  0x14UL
+#define STBCR3_OFFSET  0x410UL
+#define STBCR4_OFFSET  0x414UL
+#define STBCR5_OFFSET  0x418UL
+#define STBCR6_OFFSET  0x41CUL
+#define STBCR7_OFFSET  0x420UL
+#define STBCR8_OFFSET  0x424UL
+#define STBCR9_OFFSET  0x428UL
+#define STBCR10_OFFSET 0x42CUL
+
+#define STBREQ1_OFFSET 0x20UL
+#define STBREQ2_OFFSET 0x24UL
+#define STBREQ3_OFFSET 0x28UL
+
+#define STBACK1_OFFSET 0x30UL
+#define STBACK2_OFFSET 0x34UL
+#define STBACK3_OFFSET 0x38UL
+
+#define CPG_FRQCR_PFC          0x0003UL
+#define CPG_FRQCR_PFC_SHIFT    0UL
+#define CPG_FRQCR_BFC          0x0030UL
+#define CPG_FRQCR_BFC_SHIFT    4UL
+#define CPG_FRQCR_IFC          0x0300UL
+#define CPG_FRQCR_IFC_SHIFT    8UL
+#define CPG_FRQCR_CKOEN        0x3000UL
+#define CPG_FRQCR_CKOEN_SHIFT  12UL
+#define CPG_FRQCR_CKOEN2       0x4000UL
+#define CPG_FRQCR_CKOEN2_SHIFT 14UL
+#define CPG_STBCR2_MSTP20      0x01UL
+#define CPG_STBREQ1_STBRQ10    0x01UL
+#define CPG_STBREQ1_STBRQ11    0x02UL
+#define CPG_STBREQ1_STBRQ12    0x04UL
+#define CPG_STBREQ1_STBRQ13    0x08UL
+#define CPG_STBREQ1_STBRQ15    0x20UL
+#define CPG_STBREQ2_STBRQ20    0x01UL
+#define CPG_STBREQ2_STBRQ21    0x02UL
+#define CPG_STBREQ2_STBRQ22    0x04UL
+#define CPG_STBREQ2_STBRQ23    0x08UL
+#define CPG_STBREQ2_STBRQ24    0x10UL
+#define CPG_STBREQ2_STBRQ25    0x20UL
+#define CPG_STBREQ2_STBRQ26    0x40UL
+#define CPG_STBREQ2_STBRQ27    0x80UL
+#define CPG_STBREQ3_STBRQ30    0x01UL
+#define CPG_STBREQ3_STBRQ31    0x02UL
+#define CPG_STBREQ3_STBRQ32    0x04UL
+#define CPG_STBREQ3_STBRQ33    0x08UL
+#define CPG_STBACK1_STBAK10    0x01UL
+#define CPG_STBACK1_STBAK11    0x02UL
+#define CPG_STBACK1_STBAK12    0x04UL
+#define CPG_STBACK1_STBAK13    0x08UL
+#define CPG_STBACK1_STBAK15    0x20UL
+#define CPG_STBACK2_STBAK20    0x01UL
+#define CPG_STBACK2_STBAK21    0x02UL
+#define CPG_STBACK2_STBAK22    0x04UL
+#define CPG_STBACK2_STBAK23    0x08UL
+#define CPG_STBACK2_STBAK24    0x10UL
+#define CPG_STBACK2_STBAK25    0x20UL
+#define CPG_STBACK2_STBAK26    0x40UL
+#define CPG_STBACK2_STBAK27    0x80UL
+#define CPG_STBACK3_STBAK30    0x01UL
+#define CPG_STBACK3_STBAK31    0x02UL
+#define CPG_STBACK3_STBAK32    0x04UL
+#define CPG_STBACK3_STBAK33    0x08UL
+#define CPG_CKIOSEL_CKIOSEL    0x0003UL
+#define CPG_SCLKSEL_SPICR      0x0003UL
+#define CPG_SCLKSEL_HYMCR      0x0030UL
+#define CPG_SCLKSEL_OCTCR      0x0300UL
+#define CPG_STBCR3_MSTP30      0x01UL
+#define CPG_STBCR3_MSTP32      0x04UL
+#define CPG_STBCR3_MSTP33      0x08UL
+#define CPG_STBCR3_MSTP34      0x10UL
+#define CPG_STBCR3_MSTP35      0x20UL
+#define CPG_STBCR3_MSTP36      0x40UL
+#define CPG_STBCR4_MSTP40      0x01UL
+#define CPG_STBCR4_MSTP41      0x02UL
+#define CPG_STBCR4_MSTP42      0x04UL
+#define CPG_STBCR4_MSTP43      0x08UL
+#define CPG_STBCR4_MSTP44      0x10UL
+#define CPG_STBCR4_MSTP45      0x20UL
+#define CPG_STBCR4_MSTP46      0x40UL
+#define CPG_STBCR4_MSTP47      0x80UL
+#define CPG_STBCR5_MSTP51      0x02UL
+#define CPG_STBCR5_MSTP52      0x04UL
+#define CPG_STBCR5_MSTP53      0x08UL
+#define CPG_STBCR5_MSTP56      0x40UL
+#define CPG_STBCR5_MSTP57      0x80UL
+#define CPG_STBCR6_MSTP60      0x01UL
+#define CPG_STBCR6_MSTP61      0x02UL
+#define CPG_STBCR6_MSTP62      0x04UL
+#define CPG_STBCR6_MSTP63      0x08UL
+#define CPG_STBCR6_MSTP64      0x10UL
+#define CPG_STBCR6_MSTP65      0x20UL
+#define CPG_STBCR6_MSTP66      0x40UL
+#define CPG_STBCR7_MSTP70      0x01UL
+#define CPG_STBCR7_MSTP71      0x02UL
+#define CPG_STBCR7_MSTP72      0x04UL
+#define CPG_STBCR7_MSTP73      0x08UL
+#define CPG_STBCR7_MSTP75      0x20UL
+#define CPG_STBCR7_MSTP76      0x40UL
+#define CPG_STBCR7_MSTP77      0x80UL
+#define CPG_STBCR8_MSTP81      0x02UL
+#define CPG_STBCR8_MSTP83      0x08UL
+#define CPG_STBCR8_MSTP84      0x10UL
+#define CPG_STBCR8_MSTP85      0x20UL
+#define CPG_STBCR8_MSTP86      0x40UL
+#define CPG_STBCR8_MSTP87      0x80UL
+#define CPG_STBCR9_MSTP90      0x01UL
+#define CPG_STBCR9_MSTP91      0x02UL
+#define CPG_STBCR9_MSTP92      0x04UL
+#define CPG_STBCR9_MSTP93      0x08UL
+#define CPG_STBCR9_MSTP95      0x20UL
+#define CPG_STBCR9_MSTP96      0x40UL
+#define CPG_STBCR9_MSTP97      0x80UL
+#define CPG_STBCR10_MSTP100    0x01UL
+#define CPG_STBCR10_MSTP101    0x02UL
+#define CPG_STBCR10_MSTP102    0x04UL
+#define CPG_STBCR10_MSTP103    0x08UL
+#define CPG_STBCR10_MSTP104    0x10UL
+#define CPG_STBCR10_MSTP107    0x80UL
+
+enum rza2m_stb_module {
+	MODULE_CORESIGHT = 1,
+	MODULE_OSTM0,
+	MODULE_OSTM1,
+	MODULE_OSTM2,
+	MODULE_MTU3,
+	MODULE_CANFD,
+	MODULE_ADC,
+	MODULE_GPT,
+	MODULE_SCIFA0,
+	MODULE_SCIFA1,
+	MODULE_SCIFA2,
+	MODULE_SCIFA3,
+	MODULE_SCIFA4,
+	MODULE_SCI0,
+	MODULE_SCI1,
+	MODULE_IrDA,
+	MODULE_CEU,
+	MODULE_RTC0,
+	MODULE_RTC1,
+	MODULE_JCU,
+	MODULE_VIN,
+	MODULE_ETHER,
+	MODULE_USB0,
+	MODULE_USB1,
+	MODULE_IMR2,
+	MODULE_DRW,
+	MODULE_MIPI,
+	MODULE_SSIF0,
+	MODULE_SSIF1,
+	MODULE_SSIF2,
+	MODULE_SSIF3,
+	MODULE_I2C0,
+	MODULE_I2C1,
+	MODULE_I2C2,
+	MODULE_I2C3,
+	MODULE_SPIBSC,
+	MODULE_VDC6,
+	MODULE_RSPI0,
+	MODULE_RSPI1,
+	MODULE_RSPI2,
+	MODULE_HYPERBUS,
+	MODULE_OCTAMEM,
+	MODULE_RSPDIF,
+	MODULE_DRP,
+	MODULE_TSIP,
+	MODULE_NAND,
+	MODULE_SDMMC0,
+	MODULE_SDMMC1,
+	MODULE_MAX,
+};
+
+struct rza2m_stb_module_info {
+	enum rza2m_stb_module module;
+	uint32_t reg_offset;
+	uint8_t mask;
+};
+
+/* For setting any system sub-clock */
+enum rza2m_cp_sub_clock {
+	CPG_SUB_CLOCK_ICLK = 0u, /*!< CPU Clock */
+	CPG_SUB_CLOCK_BCLK,      /*!< Internal Bus Clock */
+	CPG_SUB_CLOCK_P1CLK,     /*!< Peripheral Clock */
+};
+
+/* For retrieve clock frequency */
+enum rza2m_cpg_get_freq_src {
+	CPG_FREQ_EXTAL = 0,
+	CPG_FREQ_ICLK,
+	CPG_FREQ_GCLK,
+	CPG_FREQ_BCLK,
+	CPG_FREQ_P1CLK,
+	CPG_FREQ_P0CLK,
+};
+
+int rza2m_cpg_set_sub_clock_divider(const struct device *dev, enum rza2m_cp_sub_clock clk_sub_src,
+				    uint32_t sub_clk_frequency_hz);
+int rza2m_cpg_mstp_clock_endisable(const struct device *dev, enum rza2m_stb_module module,
+				   bool enable);
+int rza2m_cpg_get_clock(const struct device *dev, enum rza2m_cpg_get_freq_src src,
+			uint32_t *p_freq);
+void rza2m_cpg_calculate_pll_frequency(const struct device *dev);
+void rza2m_pl310_set_standby_mode(void);
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RZA2M_CPG_LLD_H_ */
diff --git a/drivers/clock_control/clock_control_rpi_pico.c b/drivers/clock_control/clock_control_rpi_pico.c
index 02f2c867c31..762e72677ee 100644
--- a/drivers/clock_control/clock_control_rpi_pico.c
+++ b/drivers/clock_control/clock_control_rpi_pico.c
@@ -676,7 +676,7 @@ static int clock_control_rpi_pico_init(const struct device *dev)
 			     RESETS_RESET_USBCTRL_BITS));
 
 	/* Start tick in watchdog */
-	watchdog_start_tick(cycles_per_tick);
+	tick_start(TICK_WATCHDOG, cycles_per_tick);
 #if defined(CONFIG_SOC_SERIES_RP2350)
 	tick_start(TICK_TIMER0, cycles_per_tick);
 	tick_start(TICK_TIMER1, cycles_per_tick);
diff --git a/drivers/clock_control/clock_control_silabs_siwx91x.c b/drivers/clock_control/clock_control_silabs_siwx91x.c
new file mode 100644
index 00000000000..57c703f6936
--- /dev/null
+++ b/drivers/clock_control/clock_control_silabs_siwx91x.c
@@ -0,0 +1,206 @@
+/* Copyright (c) 2024 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Poor man driver for 917 clocks. 917 includes High Performace (HP) clock
+ * (@46000000), Ultra Lower Power (ULP) clock (@24041400) and ULP VBAT (@24048000)
+ *
+ */
+#include <zephyr/dt-bindings/clock/silabs/siwx91x-clock.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/logging/log.h>
+
+#include "rsi_power_save.h"
+#include "rsi_rom_ulpss_clk.h"
+#include "rsi_rom_clks.h"
+#include "rsi_sysrtc.h"
+#include "clock_update.h"
+#include "sl_si91x_clock_manager.h"
+
+#define DT_DRV_COMPAT silabs_siwx91x_clock
+#define DT_DRV_COMPAT          silabs_siwx91x_clock
+#define LF_FSM_CLOCK_FREQUENCY 32768
+
+LOG_MODULE_REGISTER(siwx91x_clock, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
+
+struct siwx91x_clock_data {
+	uint32_t enable;
+};
+
+static int siwx91x_clock_on(const struct device *dev, clock_control_subsys_t sys)
+{
+	struct siwx91x_clock_data *data = dev->data;
+	uintptr_t clockid = (uintptr_t)sys;
+
+	switch (clockid) {
+	case SIWX91X_CLK_ULP_UART:
+		RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_UART);
+		RSI_ULPSS_UlpUartClkConfig(ULPCLK, ENABLE_STATIC_CLK,
+					   false, ULP_UART_ULP_MHZ_RC_CLK, 1);
+		break;
+	case SIWX91X_CLK_ULP_I2C:
+		RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_I2C);
+		RSI_ULPSS_PeripheralEnable(ULPCLK, ULP_I2C_CLK, ENABLE_STATIC_CLK);
+		break;
+	case SIWX91X_CLK_ULP_DMA:
+		RSI_PS_UlpssPeriPowerUp(ULPSS_PWRGATE_ULP_UDMA);
+		RSI_ULPSS_PeripheralEnable(ULPCLK, ULP_UDMA_CLK, ENABLE_STATIC_CLK);
+		break;
+	case SIWX91X_CLK_UART0:
+		RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI);
+		/* RSI_CLK_UsartClkConfig() calls RSI_CLK_PeripheralClkEnable(); */
+		RSI_CLK_UsartClkConfig(M4CLK, ENABLE_STATIC_CLK, 0, USART1, 0, 1);
+		break;
+	case SIWX91X_CLK_UART1:
+		RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI);
+		/* RSI_CLK_UsartClkConfig() calls RSI_CLK_PeripheralClkEnable(); */
+		RSI_CLK_UsartClkConfig(M4CLK, ENABLE_STATIC_CLK, 0, USART2, 0, 1);
+		break;
+	case SIWX91X_CLK_I2C0:
+		RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI);
+		RSI_CLK_I2CClkConfig(M4CLK, true, 0);
+		break;
+	case SIWX91X_CLK_I2C1:
+		RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI);
+		RSI_CLK_I2CClkConfig(M4CLK, true, 1);
+		break;
+	case SIWX91X_CLK_DMA0:
+		RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI);
+		RSI_CLK_PeripheralClkEnable(M4CLK, UDMA_CLK, ENABLE_STATIC_CLK);
+		break;
+	case SIWX91X_CLK_PWM:
+		RSI_PS_M4ssPeriPowerUp(M4SS_PWRGATE_ULP_EFUSE_PERI);
+		RSI_CLK_PeripheralClkEnable(M4CLK, PWM_CLK, ENABLE_STATIC_CLK);
+		break;
+	case SIWX91X_CLK_WATCHDOG:
+		/* Both SYSRTC and WDT are clocked using LF-FSM XTAL which is initialized in
+		 * SystemCoreClockUpdate(). This function allows clock to stabilize before use.
+		 */
+		rsi_sysrtc_clk_set(RSI_SYSRTC_CLK_32kHz_Xtal, 0);
+		break;
+	default:
+		return -EINVAL;
+	}
+	data->enable |= BIT(clockid);
+
+	return 0;
+}
+
+static int siwx91x_clock_off(const struct device *dev, clock_control_subsys_t sys)
+{
+	struct siwx91x_clock_data *data = dev->data;
+	uintptr_t clockid = (uintptr_t)sys;
+
+	switch (clockid) {
+	case SIWX91X_CLK_ULP_I2C:
+		RSI_ULPSS_PeripheralDisable(ULPCLK, ULP_I2C_CLK);
+		break;
+	case SIWX91X_CLK_ULP_DMA:
+		RSI_ULPSS_PeripheralDisable(ULPCLK, ULP_UDMA_CLK);
+		break;
+	case SIWX91X_CLK_UART0:
+		RSI_CLK_PeripheralClkDisable(M4CLK, USART1_CLK);
+		break;
+	case SIWX91X_CLK_UART1:
+		RSI_CLK_PeripheralClkDisable(M4CLK, USART2_CLK);
+		break;
+	case SIWX91X_CLK_DMA0:
+		RSI_CLK_PeripheralClkDisable(M4CLK, UDMA_CLK);
+		break;
+	case SIWX91X_CLK_ULP_UART:
+	case SIWX91X_CLK_I2C0:
+	case SIWX91X_CLK_I2C1:
+		/* Not supported */
+		return 0;
+	default:
+		return -EINVAL;
+	}
+
+	data->enable &= ~BIT(clockid);
+	return 0;
+}
+
+static int siwx91x_clock_get_rate(const struct device *dev, clock_control_subsys_t sys,
+				  uint32_t *rate)
+{
+	uintptr_t clockid = (uintptr_t)sys;
+
+	switch (clockid) {
+	case SIWX91X_CLK_ULP_UART:
+		*rate = RSI_CLK_GetBaseClock(ULPSS_UART);
+		return 0;
+	case SIWX91X_CLK_UART0:
+		*rate = RSI_CLK_GetBaseClock(M4_USART0);
+		return 0;
+	case SIWX91X_CLK_UART1:
+		*rate = RSI_CLK_GetBaseClock(M4_UART1);
+		return 0;
+	case SIWX91X_CLK_PWM:
+		/* PWM peripheral operates at the system clock frequency */
+		*rate = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
+		return 0;
+	case SIWX91X_CLK_WATCHDOG:
+		*rate = LF_FSM_CLOCK_FREQUENCY;
+		return 0;
+	default:
+		/* For now, no other driver need clock rate */
+		return -EINVAL;
+	}
+}
+
+static enum clock_control_status siwx91x_clock_get_status(const struct device *dev,
+							  clock_control_subsys_t sys)
+{
+	struct siwx91x_clock_data *data = dev->data;
+	uintptr_t clockid = (uintptr_t)sys;
+
+	if (data->enable & BIT(clockid)) {
+		return CLOCK_CONTROL_STATUS_ON;
+	} else {
+		return CLOCK_CONTROL_STATUS_OFF;
+	}
+}
+
+static int siwx91x_clock_init(const struct device *dev)
+{
+	SystemCoreClockUpdate();
+
+	/* Use SoC PLL at configured frequency as core clock */
+	sl_si91x_clock_manager_m4_set_core_clk(M4_SOCPLLCLK, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
+
+	/* Use interface PLL at configured frequency as peripheral clock */
+	sl_si91x_clock_manager_set_pll_freq(INFT_PLL, CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
+					    PLL_REF_CLK_VAL_XTAL);
+
+	/* FIXME: Currently the clock consumer use clocks without power on them.
+	 * This should be fixed in drivers. Meanwhile, get the list of required
+	 * clocks using DT labels.
+	 */
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(ulpi2c), okay)
+	siwx91x_clock_on(dev, (clock_control_subsys_t)SIWX91X_CLK_ULP_I2C);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c0), okay)
+	siwx91x_clock_on(dev, (clock_control_subsys_t)SIWX91X_CLK_I2C0);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(i2c1), okay)
+	siwx91x_clock_on(dev, (clock_control_subsys_t)SIWX91X_CLK_I2C1);
+#endif
+
+	return 0;
+}
+
+static DEVICE_API(clock_control, siwx91x_clock_api) = {
+	.on = siwx91x_clock_on,
+	.off = siwx91x_clock_off,
+	.get_rate = siwx91x_clock_get_rate,
+	.get_status = siwx91x_clock_get_status,
+};
+
+#define SIWX91X_CLOCK_INIT(p)                                                                \
+	static struct siwx91x_clock_data siwx91x_clock_data_##p;                             \
+	DEVICE_DT_INST_DEFINE(p, siwx91x_clock_init, NULL, &siwx91x_clock_data_##p, NULL,    \
+			      PRE_KERNEL_1, CONFIG_CLOCK_CONTROL_INIT_PRIORITY,              \
+			      &siwx91x_clock_api);
+
+DT_INST_FOREACH_STATUS_OKAY(SIWX91X_CLOCK_INIT)
diff --git a/drivers/clock_control/clock_control_smartbond.c b/drivers/clock_control/clock_control_smartbond.c
index 33e7f3407ae..41e5291465e 100644
--- a/drivers/clock_control/clock_control_smartbond.c
+++ b/drivers/clock_control/clock_control_smartbond.c
@@ -39,7 +39,7 @@ struct lpc_clock_state {
 #define CALIBRATION_INTERVAL CONFIG_SMARTBOND_LP_OSC_CALIBRATION_INTERVAL
 
 #ifdef CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
-extern int z_clock_hw_cycles_per_sec;
+extern unsigned int z_clock_hw_cycles_per_sec;
 #endif
 
 static void calibration_work_cb(struct k_work *work);
diff --git a/drivers/clock_control/clock_control_wch_rcc.c b/drivers/clock_control/clock_control_wch_rcc.c
index d51b9ae6846..9275fd0bc82 100644
--- a/drivers/clock_control/clock_control_wch_rcc.c
+++ b/drivers/clock_control/clock_control_wch_rcc.c
@@ -19,29 +19,23 @@
 #define WCH_RCC_CLOCK_ID_OFFSET(id) (((id) >> 5) & 0xFF)
 #define WCH_RCC_CLOCK_ID_BIT(id)    ((id) & 0x1F)
 
-#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll)) && DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks)
-#define DT_PLL_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(pll))
-#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
-#define WCH_RCC_PLL_SRC_IS_HSI 1
-#endif
-#if DT_SAME_NODE(DT_PLL_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
-#define WCH_RCC_PLL_SRC_IS_HSE 1
-#endif
-#endif
-
-#define DT_RCC_CLOCKS_CTRL DT_CLOCKS_CTLR(DT_NODELABEL(rcc))
-#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(pll))
+#if DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(0), wch_ch32v00x_pll_clock) ||                          \
+	DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(0), wch_ch32v20x_30x_pll_clock)
 #define WCH_RCC_SRC_IS_PLL 1
+#if DT_NODE_HAS_COMPAT(DT_CLOCKS_CTLR(DT_INST_CLOCKS_CTLR(0)), wch_ch32v00x_hse_clock)
+#define WCH_RCC_PLL_SRC_IS_HSE 1
+#elif DT_NODE_HAS_COMPAT(DT_CLOCKS_CTLR(DT_INST_CLOCKS_CTLR(0)), wch_ch32v00x_hsi_clock)
+#define WCH_RCC_PLL_SRC_IS_HSI 1
 #endif
-#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
-#define WCH_RCC_SRC_IS_HSI 1
-#endif
-#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
+#elif DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(0), wch_ch32v00x_hse_clock)
 #define WCH_RCC_SRC_IS_HSE 1
+#elif DT_NODE_HAS_COMPAT(DT_INST_CLOCKS_CTLR(0), wch_ch32v00x_hsi_clock)
+#define WCH_RCC_SRC_IS_HSI 1
 #endif
 
 struct clock_control_wch_rcc_config {
 	RCC_TypeDef *regs;
+	uint8_t mul;
 };
 
 static int clock_control_wch_rcc_on(const struct device *dev, clock_control_subsys_t sys)
@@ -91,7 +85,10 @@ static DEVICE_API(clock_control, clock_control_wch_rcc_api) = {
 
 static int clock_control_wch_rcc_init(const struct device *dev)
 {
-	if (IS_ENABLED(CONFIG_DT_HAS_WCH_CH32V00X_PLL_CLOCK_ENABLED)) {
+	const struct clock_control_wch_rcc_config *config = dev->config;
+
+	if (IS_ENABLED(CONFIG_DT_HAS_WCH_CH32V00X_PLL_CLOCK_ENABLED) ||
+	    IS_ENABLED(CONFIG_DT_HAS_WCH_CH32V20X_30X_PLL_CLOCK_ENABLED)) {
 		/* Disable the PLL before potentially changing the input clocks. */
 		RCC->CTLR &= ~RCC_PLLON;
 	}
@@ -123,6 +120,17 @@ static int clock_control_wch_rcc_init(const struct device *dev)
 		while ((RCC->CTLR & RCC_PLLRDY) == 0) {
 		}
 	}
+	if (IS_ENABLED(CONFIG_DT_HAS_WCH_CH32V20X_30X_PLL_CLOCK_ENABLED)) {
+		if (IS_ENABLED(WCH_RCC_PLL_SRC_IS_HSE)) {
+			RCC->CFGR0 |= RCC_PLLSRC;
+		} else if (IS_ENABLED(WCH_RCC_PLL_SRC_IS_HSI)) {
+			RCC->CFGR0 &= ~RCC_PLLSRC;
+		}
+		RCC->CFGR0 |= (config->mul == 18 ? 0xF : (config->mul - 2)) << 0x12;
+		RCC->CTLR |= RCC_PLLON;
+		while ((RCC->CTLR & RCC_PLLRDY) == 0) {
+		}
+	}
 
 	if (IS_ENABLED(WCH_RCC_SRC_IS_HSI)) {
 		RCC->CFGR0 = (RCC->CFGR0 & ~RCC_SW) | RCC_SW_HSI;
@@ -137,8 +145,10 @@ static int clock_control_wch_rcc_init(const struct device *dev)
 	RCC->INTR = RCC_CSSC | RCC_PLLRDYC | RCC_HSERDYC | RCC_LSIRDYC;
 	/* HCLK = SYSCLK = APB1 */
 	RCC->CFGR0 = (RCC->CFGR0 & ~RCC_HPRE) | RCC_HPRE_DIV1;
+#if defined(CONFIG_SOC_CH32V003)
 	/* Set the Flash to 0 wait state */
 	FLASH->ACTLR = (FLASH->ACTLR & ~FLASH_ACTLR_LATENCY) | FLASH_ACTLR_LATENCY_1;
+#endif
 
 	return 0;
 }
@@ -146,9 +156,11 @@ static int clock_control_wch_rcc_init(const struct device *dev)
 #define CLOCK_CONTROL_WCH_RCC_INIT(idx)                                                            \
 	static const struct clock_control_wch_rcc_config clock_control_wch_rcc_##idx##_config = {  \
 		.regs = (RCC_TypeDef *)DT_INST_REG_ADDR(idx),                                      \
+		.mul = DT_PROP_OR(DT_INST_CLOCKS_CTLR(idx), mul, 1),                               \
 	};                                                                                         \
 	DEVICE_DT_INST_DEFINE(idx, clock_control_wch_rcc_init, NULL, NULL,                         \
 			      &clock_control_wch_rcc_##idx##_config, PRE_KERNEL_1,                 \
 			      CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_control_wch_rcc_api);
 
-DT_INST_FOREACH_STATUS_OKAY(CLOCK_CONTROL_WCH_RCC_INIT)
+/* There is only ever one RCC */
+CLOCK_CONTROL_WCH_RCC_INIT(0)
diff --git a/drivers/clock_control/clock_stm32_ll_common.c b/drivers/clock_control/clock_stm32_ll_common.c
index 6a137f061ba..338ce0ed5c6 100644
--- a/drivers/clock_control/clock_stm32_ll_common.c
+++ b/drivers/clock_control/clock_stm32_ll_common.c
@@ -122,10 +122,8 @@ int enabled_clock(uint32_t src_clk)
 	int r = 0;
 
 	switch (src_clk) {
-#if defined(STM32_SRC_SYSCLK)
 	case STM32_SRC_SYSCLK:
 		break;
-#endif /* STM32_SRC_SYSCLK */
 #if defined(STM32_SRC_PCLK)
 	case STM32_SRC_PCLK:
 		break;
@@ -249,15 +247,14 @@ int enabled_clock(uint32_t src_clk)
 	return r;
 }
 
-static inline int stm32_clock_control_on(const struct device *dev,
-					 clock_control_subsys_t sub_system)
+static int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
 	volatile int temp;
 
 	ARG_UNUSED(dev);
 
-	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
+	if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
 		/* Attempt to change a wrong periph clock bit */
 		return -ENOTSUP;
 	}
@@ -273,14 +270,13 @@ static inline int stm32_clock_control_on(const struct device *dev,
 	return 0;
 }
 
-static inline int stm32_clock_control_off(const struct device *dev,
-					  clock_control_subsys_t sub_system)
+static int stm32_clock_control_off(const struct device *dev, clock_control_subsys_t sub_system)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
 
 	ARG_UNUSED(dev);
 
-	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
+	if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
 		/* Attempt to toggle a wrong periph clock bit */
 		return -ENOTSUP;
 	}
@@ -291,11 +287,10 @@ static inline int stm32_clock_control_off(const struct device *dev,
 	return 0;
 }
 
-static inline int stm32_clock_control_configure(const struct device *dev,
-						clock_control_subsys_t sub_system,
-						void *data)
+static int stm32_clock_control_configure(const struct device *dev,
+					 clock_control_subsys_t sub_system,
+					 void *data)
 {
-#if defined(STM32_SRC_SYSCLK)
 	/* At least one alt src clock available */
 	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
 	int err;
@@ -314,16 +309,14 @@ static inline int stm32_clock_control_configure(const struct device *dev,
 		return 0;
 	}
 
-	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
-		       STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
-	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
-		     STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
+	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
+		       STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
+			STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
+	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
+		     STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
+			STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
 
 	return 0;
-#else
-	/* No src clock available: Not supported */
-	return -ENOTSUP;
-#endif
 }
 
 static int stm32_clock_control_get_subsys_rate(const struct device *clock,
@@ -395,11 +388,9 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
 		*rate = ahb3_clock;
 		break;
 #endif
-#if defined(STM32_SRC_SYSCLK)
 	case STM32_SRC_SYSCLK:
 		*rate = SystemCoreClock * STM32_CORE_PRESCALER;
 		break;
-#endif
 #if defined(STM32_SRC_PLLCLK) & defined(STM32_SYSCLK_SRC_PLL)
 	case STM32_SRC_PLLCLK:
 		if (get_pllout_frequency() == 0) {
@@ -432,7 +423,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
 					      STM32_PLL_R_DIVISOR);
 		break;
 #endif
-#if defined(STM32_SRC_PLLI2S_Q) & STM32_PLLI2S_ENABLED
+#if defined(STM32_SRC_PLLI2S_Q) & STM32_PLLI2S_Q_ENABLED & STM32_PLLI2S_ENABLED
 	case STM32_SRC_PLLI2S_Q:
 		*rate = get_pll_div_frequency(get_pllsrc_frequency(),
 					      STM32_PLLI2S_M_DIVISOR,
@@ -505,7 +496,7 @@ static enum clock_control_status stm32_clock_control_get_status(const struct dev
 
 	ARG_UNUSED(dev);
 
-	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == true) {
+	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
 		/* Gated clocks */
 		if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr)
 		    == pclken->enr) {
diff --git a/drivers/clock_control/clock_stm32_ll_h5.c b/drivers/clock_control/clock_stm32_ll_h5.c
index 3eb4b12ac04..f0679ce2725 100644
--- a/drivers/clock_control/clock_stm32_ll_h5.c
+++ b/drivers/clock_control/clock_stm32_ll_h5.c
@@ -144,15 +144,14 @@ int enabled_clock(uint32_t src_clk)
 	return -ENOTSUP;
 }
 
-static inline int stm32_clock_control_on(const struct device *dev,
-					 clock_control_subsys_t sub_system)
+static int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
 	volatile int temp;
 
 	ARG_UNUSED(dev);
 
-	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
+	if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
 		/* Attempt to toggle a wrong periph clock bit */
 		return -ENOTSUP;
 	}
@@ -166,14 +165,13 @@ static inline int stm32_clock_control_on(const struct device *dev,
 	return 0;
 }
 
-static inline int stm32_clock_control_off(const struct device *dev,
-					  clock_control_subsys_t sub_system)
+static int stm32_clock_control_off(const struct device *dev, clock_control_subsys_t sub_system)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
 
 	ARG_UNUSED(dev);
 
-	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
+	if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
 		/* Attempt to toggle a wrong periph clock bit */
 		return -ENOTSUP;
 	}
@@ -184,9 +182,9 @@ static inline int stm32_clock_control_off(const struct device *dev,
 	return 0;
 }
 
-static inline int stm32_clock_control_configure(const struct device *dev,
-						clock_control_subsys_t sub_system,
-						void *data)
+static int stm32_clock_control_configure(const struct device *dev,
+					 clock_control_subsys_t sub_system,
+					 void *data)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
 	int err;
@@ -200,8 +198,9 @@ static inline int stm32_clock_control_configure(const struct device *dev,
 		return err;
 	}
 
-	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
-		     STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
+	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
+		     STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
+			STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
 
 	return 0;
 }
@@ -478,6 +477,10 @@ static int set_up_plls(void)
 	LL_RCC_PLL1_SetN(STM32_PLL_N_MULTIPLIER);
 
 	LL_RCC_PLL1FRACN_Disable();
+	if (IS_ENABLED(STM32_PLL_FRACN_ENABLED)) {
+		LL_RCC_PLL1_SetFRACN(STM32_PLL_FRACN_VALUE);
+		LL_RCC_PLL1FRACN_Enable();
+	}
 
 	if (IS_ENABLED(STM32_PLL_P_ENABLED)) {
 		LL_RCC_PLL1_SetP(STM32_PLL_P_DIVISOR);
diff --git a/drivers/clock_control/clock_stm32_ll_h7.c b/drivers/clock_control/clock_stm32_ll_h7.c
index 5819eb5017b..5d6bcb72fa9 100644
--- a/drivers/clock_control/clock_stm32_ll_h7.c
+++ b/drivers/clock_control/clock_stm32_ll_h7.c
@@ -249,27 +249,6 @@ static uint32_t get_hclk_frequency(void)
 
 static int32_t prepare_regulator_voltage_scale(void)
 {
-	/* Apply system power supply configuration */
-#if defined(SMPS) && defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
-	LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
-#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO)
-	LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_LDO);
-#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO)
-	LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_LDO);
-#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO)
-	LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO);
-#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO)
-	LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO);
-#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT)
-	LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT);
-#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT)
-	LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT);
-#elif defined(CONFIG_POWER_SUPPLY_EXTERNAL_SOURCE)
-	LL_PWR_ConfigSupply(LL_PWR_EXTERNAL_SOURCE_SUPPLY);
-#else
-	LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
-#endif
-
 	/* Make sure to put the CPU in highest Voltage scale during clock configuration */
 	/* Highest voltage is SCALE0 */
 	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
@@ -279,6 +258,7 @@ static int32_t prepare_regulator_voltage_scale(void)
 	while (LL_PWR_IsActiveFlag_VOS() == 0) {
 #endif
 	}
+
 	return 0;
 }
 
@@ -292,25 +272,6 @@ static int32_t optimize_regulator_voltage_scale(uint32_t sysclk_freq)
 	/* LL_PWR_REGULATOR_SCALE3 is lowest power consumption */
 	/* Must be done in accordance to the Maximum allowed frequency vs VOS*/
 	/* See RM0433 page 352 for more details */
-#if defined(SMPS) && defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
-	LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
-#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO)
-	LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_LDO);
-#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO)
-	LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_LDO);
-#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO)
-	LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO);
-#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO)
-	LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO);
-#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT)
-	LL_PWR_ConfigSupply(LL_PWR_SMPS_1V8_SUPPLIES_EXT);
-#elif defined(SMPS) && defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT)
-	LL_PWR_ConfigSupply(LL_PWR_SMPS_2V5_SUPPLIES_EXT);
-#elif defined(CONFIG_POWER_SUPPLY_EXTERNAL_SOURCE)
-	LL_PWR_ConfigSupply(LL_PWR_EXTERNAL_SOURCE_SUPPLY);
-#else
-	LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
-#endif
 	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
 #if defined(CONFIG_SOC_SERIES_STM32H7RSX)
 	while (LL_PWR_IsActiveFlag_VOSRDY() == 0) {
@@ -318,6 +279,7 @@ static int32_t optimize_regulator_voltage_scale(uint32_t sysclk_freq)
 	while (LL_PWR_IsActiveFlag_VOS() == 0) {
 #endif
 	};
+
 	return 0;
 }
 
@@ -382,15 +344,14 @@ int enabled_clock(uint32_t src_clk)
 	return -ENOTSUP;
 }
 
-static inline int stm32_clock_control_on(const struct device *dev,
-					 clock_control_subsys_t sub_system)
+static int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
 	volatile int temp;
 
 	ARG_UNUSED(dev);
 
-	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
+	if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
 		/* Attempt to toggle a wrong periph clock bit */
 		return -ENOTSUP;
 	}
@@ -409,14 +370,13 @@ static inline int stm32_clock_control_on(const struct device *dev,
 	return 0;
 }
 
-static inline int stm32_clock_control_off(const struct device *dev,
-					  clock_control_subsys_t sub_system)
+static int stm32_clock_control_off(const struct device *dev, clock_control_subsys_t sub_system)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
 
 	ARG_UNUSED(dev);
 
-	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
+	if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
 		/* Attempt to toggle a wrong periph clock bit */
 		return -ENOTSUP;
 	}
@@ -430,9 +390,9 @@ static inline int stm32_clock_control_off(const struct device *dev,
 	return 0;
 }
 
-static inline int stm32_clock_control_configure(const struct device *dev,
-						clock_control_subsys_t sub_system,
-						void *data)
+static int stm32_clock_control_configure(const struct device *dev,
+					 clock_control_subsys_t sub_system,
+					 void *data)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
 	int err;
@@ -446,12 +406,19 @@ static inline int stm32_clock_control_configure(const struct device *dev,
 		return err;
 	}
 
+	if (pclken->enr == NO_SEL) {
+		/* Domain clock is fixed. Nothing to set. Exit */
+		return 0;
+	}
+
 	z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
 
-	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
-		       STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
-	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
-		     STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
+	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
+		       STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
+			STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
+	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
+		     STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
+			STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
 
 	z_stm32_hsem_unlock(CFG_HW_RCC_SEMID);
 
@@ -685,7 +652,7 @@ static void set_up_fixed_clock_sources(void)
 
 	if (IS_ENABLED(STM32_HSI_ENABLED)) {
 		if (IS_ENABLED(STM32_PLL_SRC_HSI) || IS_ENABLED(STM32_PLL2_SRC_HSI) ||
-+		    IS_ENABLED(STM32_PLL3_SRC_HSI)) {
+		    IS_ENABLED(STM32_PLL3_SRC_HSI)) {
 			/* HSI calibration */
 			LL_RCC_HSI_SetCalibTrimming(RCC_HSICALIBRATION_DEFAULT);
 		}
@@ -988,91 +955,6 @@ static int set_up_plls(void)
 	return 0;
 }
 
-#if defined(CONFIG_SOC_SERIES_STM32H7RSX)
-/*  adapted from the stm32cube SystemCoreClockUpdate*/
-void stm32_system_clock_update(void)
-{
-	uint32_t sysclk, hsivalue, pllsource, pllm, pllp, core_presc;
-	float_t pllfracn, pllvco;
-
-	/* Get SYSCLK source */
-	switch (RCC->CFGR & RCC_CFGR_SWS) {
-	case 0x00: /* HSI used as system clock source (default after reset) */
-		sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)
-			>> RCC_CR_HSIDIV_Pos));
-		break;
-
-	case 0x08: /* CSI used as system clock source */
-		sysclk = CSI_VALUE;
-		break;
-
-	case 0x10: /* HSE used as system clock source */
-		sysclk = HSE_VALUE;
-		break;
-
-	case 0x18:  /* PLL1 used as system clock  source */
-		/*
-		 * PLL1_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
-		 * SYSCLK = PLL1_VCO / PLL1R
-		 */
-		pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
-		pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos);
-
-		if ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) != 0U) {
-			pllfracn = (float_t)(uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN)
-			>> RCC_PLL1FRACR_FRACN_Pos));
-		} else {
-			pllfracn = (float_t)0U;
-		}
-
-		if (pllm != 0U) {
-			switch (pllsource) {
-			case 0x02: /* HSE used as PLL1 clock source */
-				pllvco = ((float_t)HSE_VALUE / (float_t)pllm) *
-					((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) +
-					(pllfracn/(float_t)0x2000) + (float_t)1);
-				break;
-
-			case 0x01: /* CSI used as PLL1 clock source */
-				pllvco = ((float_t)CSI_VALUE / (float_t)pllm) *
-				((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) +
-				(pllfracn/(float_t)0x2000) + (float_t)1);
-				break;
-
-			case 0x00: /* HSI used as PLL1 clock source */
-			default:
-				hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >>
-					RCC_CR_HSIDIV_Pos));
-				pllvco = ((float_t)hsivalue / (float_t)pllm) *
-					((float_t)(uint32_t)(RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVN) +
-					(pllfracn/(float_t)0x2000) + (float_t)1);
-				break;
-			}
-
-			pllp = (((RCC->PLL1DIVR1 & RCC_PLL1DIVR1_DIVP) >>
-				RCC_PLL1DIVR1_DIVP_Pos) + 1U);
-			sysclk =  (uint32_t)(float_t)(pllvco/(float_t)pllp);
-		} else {
-			sysclk = 0U;
-		}
-		break;
-
-	default: /* Unexpected, default to HSI used as system clk source (default after reset) */
-		sysclk = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> RCC_CR_HSIDIV_Pos));
-		break;
-	}
-
-	/* system clock frequency : CM7 CPU frequency  */
-	core_presc = (RCC->CDCFGR & RCC_CDCFGR_CPRE);
-
-	if (core_presc >= 8U) {
-		SystemCoreClock = (sysclk >> (core_presc - RCC_CDCFGR_CPRE_3 + 1U));
-	} else {
-		SystemCoreClock = sysclk;
-	}
-}
-#endif /* CONFIG_SOC_SERIES_STM32H7RSX */
-
 int stm32_clock_control_init(const struct device *dev)
 {
 	int r = 0;
diff --git a/drivers/clock_control/clock_stm32_ll_mp1.c b/drivers/clock_control/clock_stm32_ll_mp1.c
index e87d4c94b77..d13ec2ecb27 100644
--- a/drivers/clock_control/clock_stm32_ll_mp1.c
+++ b/drivers/clock_control/clock_stm32_ll_mp1.c
@@ -14,8 +14,7 @@
 /**
  * @brief fill in AHB/APB buses configuration structure
  */
-static inline int stm32_clock_control_on(const struct device *dev,
-					 clock_control_subsys_t sub_system)
+static int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
 
@@ -65,8 +64,7 @@ static inline int stm32_clock_control_on(const struct device *dev,
 	return 0;
 }
 
-static inline int stm32_clock_control_off(const struct device *dev,
-					  clock_control_subsys_t sub_system)
+static int stm32_clock_control_off(const struct device *dev, clock_control_subsys_t sub_system)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
 
diff --git a/drivers/clock_control/clock_stm32_ll_mp13.c b/drivers/clock_control/clock_stm32_ll_mp13.c
new file mode 100644
index 00000000000..6c8da819e51
--- /dev/null
+++ b/drivers/clock_control/clock_stm32_ll_mp13.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc.h>
+
+#include <stm32_ll_bus.h>
+#include <stm32_ll_pwr.h>
+#include <stm32_ll_rcc.h>
+#include <stm32_ll_system.h>
+#include <stm32_ll_utils.h>
+
+#include <zephyr/arch/cpu.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/stm32_clock_control.h>
+#include <zephyr/sys/util.h>
+
+static int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
+{
+	struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
+	volatile int temp;
+
+	ARG_UNUSED(dev);
+
+	if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
+		/* Attempt to toggle a wrong periph clock bit */
+		return -ENOTSUP;
+	}
+
+	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, pclken->enr);
+	/* Ensure that the write operation is completed */
+	temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);
+	UNUSED(temp);
+
+	return 0;
+}
+
+static int stm32_clock_control_off(const struct device *dev, clock_control_subsys_t sub_system)
+{
+	struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
+	volatile int temp;
+
+	ARG_UNUSED(dev);
+
+	if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
+		/* Attempt to toggle a wrong periph clock bit */
+		return -ENOTSUP;
+	}
+
+	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus, pclken->enr);
+	/* Ensure that the write operation is completed */
+	temp = sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus);
+	UNUSED(temp);
+
+	return 0;
+}
+
+static int stm32_clock_control_get_subsys_rate(const struct device *dev,
+					       clock_control_subsys_t sub_system, uint32_t *rate)
+{
+	struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
+
+	ARG_UNUSED(dev);
+
+	switch (pclken->bus) {
+	case STM32_CLOCK_BUS_APB1:
+		switch (pclken->enr) {
+		case LL_APB1_GRP1_PERIPH_UART4:
+			*rate = LL_RCC_GetUARTClockFreq(LL_RCC_UART4_CLKSOURCE);
+			break;
+		default:
+			return -ENOTSUP;
+		}
+		break;
+	default:
+		return -ENOTSUP;
+	}
+	return 0;
+}
+
+static const struct clock_control_driver_api stm32_clock_control_api = {
+	.on = stm32_clock_control_on,
+	.off = stm32_clock_control_off,
+	.get_rate = stm32_clock_control_get_subsys_rate,
+};
+
+static void set_up_fixed_clock_sources(void)
+{
+	if (IS_ENABLED(STM32_HSE_ENABLED)) {
+		/* Enable HSE */
+		LL_RCC_HSE_Enable();
+		while (LL_RCC_HSE_IsReady() != 1) {
+			/* Wait for HSE ready */
+		}
+	}
+
+	if (IS_ENABLED(STM32_HSI_ENABLED)) {
+		/* Enable HSI if not enabled */
+		if (LL_RCC_HSI_IsReady() != 1) {
+			/* Enable HSI */
+			LL_RCC_HSI_Enable();
+			while (LL_RCC_HSI_IsReady() != 1) {
+			/* Wait for HSI ready */
+			}
+		}
+	}
+}
+
+static int stm32_clock_control_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	set_up_fixed_clock_sources();
+
+#if STM32_SYSCLK_SRC_HSE
+
+	LL_RCC_SetMPUClkSource(LL_RCC_MPU_CLKSOURCE_HSE);
+	while (LL_RCC_GetMPUClkSource() != LL_RCC_MPU_CLKSOURCE_HSE) {
+	}
+
+#elif STM32_SYSCLK_SRC_HSI
+
+	LL_RCC_SetMPUClkSource(LL_RCC_MPU_CLKSOURCE_HSI);
+	while (LL_RCC_GetMPUClkSource() != LL_RCC_MPU_CLKSOURCE_HSI) {
+	}
+
+#elif STM32_SYSCLK_SRC_PLL
+
+	BUILD_ASSERT(IS_ENABLED(STM32_HSE_ENABLED),
+		     "STM32MP13 PLL requires HSE to be enabled!");
+
+	/* The default system clock source is HSI, but the bootloader may have switched it. */
+	/* Switch back to HSE for clock setup as PLL1 configuration must not be modified */
+	/* while active.*/
+
+	LL_RCC_SetMPUClkSource(LL_RCC_MPU_CLKSOURCE_HSE);
+	while ((READ_BIT(RCC->MPCKSELR, RCC_MPCKSELR_MPUSRCRDY) != RCC_MPCKSELR_MPUSRCRDY)) {
+	}
+
+	CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN);
+	while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN) == RCC_PLL1CR_DIVPEN) {
+	};
+
+	CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVQEN);
+	while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVQEN) == RCC_PLL1CR_DIVQEN) {
+	};
+
+	CLEAR_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVREN);
+	while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVREN) == RCC_PLL1CR_DIVREN) {
+	};
+
+	uint32_t pll1_n = DT_PROP(DT_NODELABEL(pll1), mul_n);
+	uint32_t pll1_m = DT_PROP(DT_NODELABEL(pll1), div_m);
+	uint32_t pll1_p = DT_PROP(DT_NODELABEL(pll1), div_p);
+	uint32_t pll1_v = DT_PROP(DT_NODELABEL(pll1), frac_v);
+
+	LL_RCC_PLL1_SetN(pll1_n);
+	while (LL_RCC_PLL1_GetN() != pll1_n) {
+	}
+	LL_RCC_PLL1_SetM(pll1_m);
+	while (LL_RCC_PLL1_GetM() != pll1_m) {
+	}
+	LL_RCC_PLL1_SetP(pll1_p);
+	while (LL_RCC_PLL1_GetP() != pll1_p) {
+	}
+	LL_RCC_PLL1_SetFRACV(pll1_v);
+	while (LL_RCC_PLL1_GetFRACV() != pll1_v) {
+	}
+
+	LL_RCC_PLL1_Enable();
+	while (LL_RCC_PLL1_IsReady() != 1) {
+	}
+
+	SET_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN);
+	while (READ_BIT(RCC->PLL1CR, RCC_PLL1CR_DIVPEN) != RCC_PLL1CR_DIVPEN) {
+	};
+
+	LL_RCC_SetMPUClkSource(LL_RCC_MPU_CLKSOURCE_PLL1);
+	while (LL_RCC_GetMPUClkSource() != LL_RCC_MPU_CLKSOURCE_PLL1) {
+	}
+
+#endif
+
+	return 0;
+}
+
+/**
+ * @brief RCC device, note that priority is intentionally set to 1 so
+ * that the device init runs just after SOC init
+ */
+DEVICE_DT_DEFINE(DT_NODELABEL(rcc),
+		 stm32_clock_control_init,
+		 NULL,
+		 NULL, NULL,
+		 PRE_KERNEL_1,
+		 CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
+		 &stm32_clock_control_api);
diff --git a/drivers/clock_control/clock_stm32_ll_n6.c b/drivers/clock_control/clock_stm32_ll_n6.c
new file mode 100644
index 00000000000..938166fb692
--- /dev/null
+++ b/drivers/clock_control/clock_stm32_ll_n6.c
@@ -0,0 +1,1008 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <soc.h>
+#include <stm32_ll_bus.h>
+#include <stm32_ll_pwr.h>
+#include <stm32_ll_rcc.h>
+#include <stm32_ll_utils.h>
+#include <stm32_ll_system.h>
+#include <zephyr/arch/cpu.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/stm32_clock_control.h>
+#include <zephyr/sys/util.h>
+
+/* Macros to fill up prescaler values */
+#define z_ic_src_pll(v) LL_RCC_ICCLKSOURCE_PLL ## v
+#define ic_src_pll(v) z_ic_src_pll(v)
+
+#define z_hsi_divider(v) LL_RCC_HSI_DIV_ ## v
+#define hsi_divider(v) z_hsi_divider(v)
+
+#define z_ahb_prescaler(v) LL_RCC_AHB_DIV_ ## v
+#define ahb_prescaler(v) z_ahb_prescaler(v)
+
+#define z_apb1_prescaler(v) LL_RCC_APB1_DIV_ ## v
+#define apb1_prescaler(v) z_apb1_prescaler(v)
+
+#define z_apb2_prescaler(v) LL_RCC_APB2_DIV_ ## v
+#define apb2_prescaler(v) z_apb2_prescaler(v)
+
+#define z_apb4_prescaler(v) LL_RCC_APB4_DIV_ ## v
+#define apb4_prescaler(v) z_apb4_prescaler(v)
+
+#define z_apb5_prescaler(v) LL_RCC_APB5_DIV_ ## v
+#define apb5_prescaler(v) z_apb5_prescaler(v)
+
+#define z_timg_prescaler(v) LL_RCC_TIM_PRESCALER_ ## v
+#define timg_prescaler(v) z_timg_prescaler(v)
+
+#define PLL1_ID		1
+#define PLL2_ID		2
+#define PLL3_ID		3
+#define PLL4_ID		4
+
+
+static uint32_t get_bus_clock(uint32_t clock, uint32_t prescaler)
+{
+	return clock / prescaler;
+}
+
+__unused
+/** @brief returns the pll source frequency of given pll_id */
+static uint32_t get_pllsrc_frequency(int pll_id)
+{
+	if ((IS_ENABLED(STM32_PLL_SRC_HSI) && pll_id == PLL1_ID) ||
+	    (IS_ENABLED(STM32_PLL2_SRC_HSI) && pll_id == PLL2_ID) ||
+	    (IS_ENABLED(STM32_PLL3_SRC_HSI) && pll_id == PLL3_ID) ||
+	    (IS_ENABLED(STM32_PLL4_SRC_HSI) && pll_id == PLL4_ID)) {
+		return STM32_HSI_FREQ;
+	} else if ((IS_ENABLED(STM32_PLL_SRC_HSE) && pll_id == PLL1_ID) ||
+		   (IS_ENABLED(STM32_PLL2_SRC_HSE) && pll_id == PLL2_ID) ||
+		   (IS_ENABLED(STM32_PLL3_SRC_HSE) && pll_id == PLL3_ID) ||
+		   (IS_ENABLED(STM32_PLL4_SRC_HSE) && pll_id == PLL4_ID)) {
+		return STM32_HSE_FREQ;
+	}
+
+	__ASSERT(0, "No PLL Source configured");
+	return 0;
+}
+
+static uint32_t get_pllout_frequency(int pll_id)
+{
+	uint32_t pllsrc_freq = get_pllsrc_frequency(pll_id);
+	int pllm_div;
+	int plln_mul;
+	int pllout_div1;
+	int pllout_div2;
+
+	switch (pll_id) {
+#if defined(STM32_PLL1_ENABLED)
+	case PLL1_ID:
+		pllm_div = STM32_PLL1_M_DIVISOR;
+		plln_mul = STM32_PLL1_N_MULTIPLIER;
+		pllout_div1 = STM32_PLL1_P1_DIVISOR;
+		pllout_div2 = STM32_PLL1_P2_DIVISOR;
+		break;
+#endif /* STM32_PLL1_ENABLED */
+#if defined(STM32_PLL2_ENABLED)
+	case PLL2_ID:
+		pllm_div = STM32_PLL2_M_DIVISOR;
+		plln_mul = STM32_PLL2_N_MULTIPLIER;
+		pllout_div1 = STM32_PLL2_P1_DIVISOR;
+		pllout_div2 = STM32_PLL2_P2_DIVISOR;
+		break;
+#endif /* STM32_PLL2_ENABLED */
+#if defined(STM32_PLL3_ENABLED)
+	case PLL3_ID:
+		pllm_div = STM32_PLL3_M_DIVISOR;
+		plln_mul = STM32_PLL3_N_MULTIPLIER;
+		pllout_div1 = STM32_PLL3_P1_DIVISOR;
+		pllout_div2 = STM32_PLL3_P2_DIVISOR;
+		break;
+#endif /* STM32_PLL3_ENABLED */
+#if defined(STM32_PLL4_ENABLED)
+	case PLL4_ID:
+		pllm_div = STM32_PLL4_M_DIVISOR;
+		plln_mul = STM32_PLL4_N_MULTIPLIER;
+		pllout_div1 = STM32_PLL4_P1_DIVISOR;
+		pllout_div2 = STM32_PLL4_P2_DIVISOR;
+		break;
+#endif /* STM32_PLL4_ENABLED */
+	default:
+		__ASSERT(0, "No PLL configured");
+		return 0;
+	}
+
+	__ASSERT_NO_MSG(pllm_div && pllout_div1 && pllout_div2);
+
+	return (pllsrc_freq / pllm_div) * plln_mul / (pllout_div1 * pllout_div2);
+}
+
+__unused uint32_t get_icout_frequency(uint32_t icsrc, int div)
+{
+	if (icsrc == LL_RCC_ICCLKSOURCE_PLL1) {
+		return get_pllout_frequency(PLL1_ID) / div;
+	} else if (icsrc == LL_RCC_ICCLKSOURCE_PLL2) {
+		return get_pllout_frequency(PLL2_ID) / div;
+	} else if (icsrc == LL_RCC_ICCLKSOURCE_PLL3) {
+		return get_pllout_frequency(PLL3_ID) / div;
+	} else if (icsrc == LL_RCC_ICCLKSOURCE_PLL4) {
+		return get_pllout_frequency(PLL4_ID) / div;
+	}
+
+	__ASSERT(0, "No IC Source configured");
+	return 0;
+}
+
+static uint32_t get_sysclk_frequency(void)
+{
+#if defined(STM32_SYSCLK_SRC_HSE)
+	return STM32_HSE_FREQ;
+#elif defined(STM32_SYSCLK_SRC_HSI)
+	return STM32_HSI_FREQ;
+#elif defined(STM32_SYSCLK_SRC_IC2)
+	return get_icout_frequency(LL_RCC_IC2_GetSource(), STM32_IC2_DIV);
+#else
+	__ASSERT(0, "No SYSCLK Source configured");
+	return 0;
+#endif
+
+}
+
+
+/** @brief Verifies clock is part of active clock configuration */
+static int enabled_clock(uint32_t src_clk)
+{
+	if ((src_clk == STM32_SRC_SYSCLK) ||
+	    (src_clk == STM32_SRC_HCLK1) ||
+	    (src_clk == STM32_SRC_HCLK2) ||
+	    (src_clk == STM32_SRC_HCLK3) ||
+	    (src_clk == STM32_SRC_HCLK4) ||
+	    (src_clk == STM32_SRC_HCLK5) ||
+	    (src_clk == STM32_SRC_PCLK1) ||
+	    (src_clk == STM32_SRC_PCLK2) ||
+	    (src_clk == STM32_SRC_PCLK4) ||
+	    (src_clk == STM32_SRC_PCLK5) ||
+	    (src_clk == STM32_SRC_TIMG) ||
+	    ((src_clk == STM32_SRC_LSE) && IS_ENABLED(STM32_LSE_ENABLED)) ||
+	    ((src_clk == STM32_SRC_LSI) && IS_ENABLED(STM32_LSI_ENABLED)) ||
+	    ((src_clk == STM32_SRC_HSE) && IS_ENABLED(STM32_HSE_ENABLED)) ||
+	    ((src_clk == STM32_SRC_HSI) && IS_ENABLED(STM32_HSI_ENABLED)) ||
+	    ((src_clk == STM32_SRC_HSI_DIV) && IS_ENABLED(STM32_HSI_ENABLED)) ||
+	    ((src_clk == STM32_SRC_PLL1) && IS_ENABLED(STM32_PLL1_ENABLED)) ||
+	    ((src_clk == STM32_SRC_PLL2) && IS_ENABLED(STM32_PLL2_ENABLED)) ||
+	    ((src_clk == STM32_SRC_PLL3) && IS_ENABLED(STM32_PLL3_ENABLED)) ||
+	    ((src_clk == STM32_SRC_PLL4) && IS_ENABLED(STM32_PLL4_ENABLED)) ||
+	    ((src_clk == STM32_SRC_CKPER) && IS_ENABLED(STM32_CKPER_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC1) && IS_ENABLED(STM32_IC1_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC2) && IS_ENABLED(STM32_IC2_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC3) && IS_ENABLED(STM32_IC3_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC4) && IS_ENABLED(STM32_IC4_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC5) && IS_ENABLED(STM32_IC5_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC6) && IS_ENABLED(STM32_IC6_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC7) && IS_ENABLED(STM32_IC7_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC8) && IS_ENABLED(STM32_IC8_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC9) && IS_ENABLED(STM32_IC9_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC10) && IS_ENABLED(STM32_IC10_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC11) && IS_ENABLED(STM32_IC11_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC12) && IS_ENABLED(STM32_IC12_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC13) && IS_ENABLED(STM32_IC13_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC14) && IS_ENABLED(STM32_IC14_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC15) && IS_ENABLED(STM32_IC15_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC16) && IS_ENABLED(STM32_IC16_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC17) && IS_ENABLED(STM32_IC17_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC18) && IS_ENABLED(STM32_IC18_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC19) && IS_ENABLED(STM32_IC19_ENABLED)) ||
+	    ((src_clk == STM32_SRC_IC20) && IS_ENABLED(STM32_IC20_ENABLED))) {
+		return 0;
+	}
+
+	return -ENOTSUP;
+}
+
+static int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
+{
+	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
+
+	ARG_UNUSED(dev);
+
+	if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
+		/* Attempt to toggle a wrong periph clock bit */
+		return -ENOTSUP;
+	}
+
+	/* Set Run clock */
+	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,
+		     pclken->enr);
+
+	/* Set Low Power clock */
+	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus + STM32_CLOCK_LP_BUS_SHIFT,
+		     pclken->enr);
+
+	return 0;
+}
+
+static int stm32_clock_control_off(const struct device *dev, clock_control_subsys_t sub_system)
+{
+	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
+
+	ARG_UNUSED(dev);
+
+	if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
+		/* Attempt to toggle a wrong periph clock bit */
+		return -ENOTSUP;
+	}
+
+	/* Clear Run clock */
+	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus,
+		       pclken->enr);
+
+	/* Clear Low Power clock */
+	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus + STM32_CLOCK_LP_BUS_SHIFT,
+		       pclken->enr);
+
+	return 0;
+}
+
+static int stm32_clock_control_configure(const struct device *dev,
+					 clock_control_subsys_t sub_system,
+					 void *data)
+{
+	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
+	int err;
+
+	ARG_UNUSED(dev);
+	ARG_UNUSED(data);
+
+	err = enabled_clock(pclken->bus);
+	if (err < 0) {
+		/* Attempt to configure a src clock not available or not valid */
+		return err;
+	}
+
+	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
+		       STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
+			STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
+	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
+		     STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
+			STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
+
+	return 0;
+}
+
+static int stm32_clock_control_get_subsys_rate(const struct device *dev,
+					       clock_control_subsys_t sys,
+					       uint32_t *rate)
+{
+	struct stm32_pclken *pclken = (struct stm32_pclken *)(sys);
+
+	uint32_t sys_clock = get_sysclk_frequency();
+	uint32_t ahb_clock = get_bus_clock(sys_clock, STM32_AHB_PRESCALER);
+
+	ARG_UNUSED(dev);
+
+	switch (pclken->bus) {
+	case STM32_SRC_SYSCLK:
+		*rate = get_sysclk_frequency();
+		break;
+	case STM32_SRC_HCLK1:
+	case STM32_SRC_HCLK2:
+	case STM32_SRC_HCLK3:
+	case STM32_SRC_HCLK4:
+	case STM32_SRC_HCLK5:
+	case STM32_CLOCK_BUS_AHB1:
+	case STM32_CLOCK_BUS_AHB2:
+	case STM32_CLOCK_BUS_AHB3:
+	case STM32_CLOCK_BUS_AHB4:
+	case STM32_CLOCK_BUS_AHB5:
+		*rate = ahb_clock;
+		break;
+	case STM32_SRC_PCLK1:
+	case STM32_CLOCK_BUS_APB1:
+	case STM32_CLOCK_BUS_APB1_2:
+		*rate = get_bus_clock(ahb_clock, STM32_APB1_PRESCALER);
+		break;
+	case STM32_SRC_PCLK2:
+	case STM32_CLOCK_BUS_APB2:
+		*rate = get_bus_clock(ahb_clock, STM32_APB2_PRESCALER);
+		break;
+	case STM32_SRC_PCLK4:
+	case STM32_CLOCK_BUS_APB4:
+	case STM32_CLOCK_BUS_APB4_2:
+		*rate = get_bus_clock(ahb_clock, STM32_APB4_PRESCALER);
+		break;
+	case STM32_SRC_PCLK5:
+	case STM32_CLOCK_BUS_APB5:
+		*rate = get_bus_clock(ahb_clock, STM32_APB5_PRESCALER);
+		break;
+#if defined(STM32_LSE_ENABLED)
+	case STM32_SRC_LSE:
+		*rate = STM32_LSE_FREQ;
+		break;
+#endif /* STM32_LSE_ENABLED */
+#if defined(STM32_LSI_ENABLED)
+	case STM32_SRC_LSI:
+		*rate = STM32_LSI_FREQ;
+		break;
+#endif /* STM32_LSI_ENABLED */
+#if defined(STM32_HSE_ENABLED)
+	case STM32_SRC_HSE:
+		*rate = STM32_HSE_FREQ;
+		break;
+#endif /* STM32_HSE_ENABLED */
+#if defined(STM32_HSI_ENABLED)
+	case STM32_SRC_HSI:
+		*rate = STM32_HSI_FREQ;
+		break;
+	case STM32_SRC_HSI_DIV:
+		*rate = STM32_HSI_FREQ / STM32_HSI_DIVISOR;
+		break;
+#endif /* STM32_HSI_ENABLED */
+	case STM32_SRC_PLL1:
+		*rate = get_pllout_frequency(PLL1_ID);
+		break;
+	case STM32_SRC_PLL2:
+		*rate = get_pllout_frequency(PLL2_ID);
+		break;
+	case STM32_SRC_PLL3:
+		*rate = get_pllout_frequency(PLL3_ID);
+		break;
+	case STM32_SRC_PLL4:
+		*rate = get_pllout_frequency(PLL4_ID);
+		break;
+#if defined(STM32_CKPER_ENABLED)
+	case STM32_SRC_CKPER:
+		*rate = LL_RCC_GetCLKPClockFreq(LL_RCC_CLKP_CLKSOURCE);
+		break;
+#endif /* STM32_CKPER_ENABLED */
+#if defined(STM32_IC1_ENABLED)
+	case STM32_SRC_IC1:
+		*rate = get_icout_frequency(LL_RCC_IC1_GetSource(), STM32_IC1_DIV);
+		break;
+#endif /* STM32_IC1_ENABLED */
+#if defined(STM32_IC2_ENABLED)
+	case STM32_SRC_IC2:
+		*rate = get_icout_frequency(LL_RCC_IC2_GetSource(), STM32_IC2_DIV);
+		break;
+#endif /* STM32_IC2_ENABLED */
+#if defined(STM32_IC3_ENABLED)
+	case STM32_SRC_IC3:
+		*rate = get_icout_frequency(LL_RCC_IC3_GetSource(), STM32_IC3_DIV);
+		break;
+#endif /* STM32_IC3_ENABLED */
+#if defined(STM32_IC4_ENABLED)
+	case STM32_SRC_IC4:
+		*rate = get_icout_frequency(LL_RCC_IC4_GetSource(), STM32_IC4_DIV);
+		break;
+#endif /* STM32_IC4_ENABLED */
+#if defined(STM32_IC5_ENABLED)
+	case STM32_SRC_IC5:
+		*rate = get_icout_frequency(LL_RCC_IC5_GetSource(), STM32_IC5_DIV);
+		break;
+#endif /* STM32_IC5_ENABLED */
+#if defined(STM32_IC6_ENABLED)
+	case STM32_SRC_IC6:
+		*rate = get_icout_frequency(LL_RCC_IC6_GetSource(), STM32_IC6_DIV);
+		break;
+#endif /* STM32_IC6_ENABLED */
+#if defined(STM32_IC7_ENABLED)
+	case STM32_SRC_IC7:
+		*rate = get_icout_frequency(LL_RCC_IC7_GetSource(), STM32_IC7_DIV);
+		break;
+#endif /* STM32_IC7_ENABLED */
+#if defined(STM32_IC8_ENABLED)
+	case STM32_SRC_IC8:
+		*rate = get_icout_frequency(LL_RCC_IC8_GetSource(), STM32_IC8_DIV);
+		break;
+#endif /* STM32_IC8_ENABLED */
+#if defined(STM32_IC9_ENABLED)
+	case STM32_SRC_IC9:
+		*rate = get_icout_frequency(LL_RCC_IC9_GetSource(), STM32_IC9_DIV);
+		break;
+#endif /* STM32_IC9_ENABLED */
+#if defined(STM32_IC10_ENABLED)
+	case STM32_SRC_IC10:
+		*rate = get_icout_frequency(LL_RCC_IC10_GetSource(), STM32_IC10_DIV);
+		break;
+#endif /* STM32_IC10_ENABLED */
+#if defined(STM32_IC11_ENABLED)
+	case STM32_SRC_IC11:
+		*rate = get_icout_frequency(LL_RCC_IC11_GetSource(), STM32_IC11_DIV);
+		break;
+#endif /* STM32_IC11_ENABLED */
+#if defined(STM32_IC12_ENABLED)
+	case STM32_SRC_IC12:
+		*rate = get_icout_frequency(LL_RCC_IC12_GetSource(), STM32_IC12_DIV);
+		break;
+#endif /* STM32_IC12_ENABLED */
+#if defined(STM32_IC13_ENABLED)
+	case STM32_SRC_IC13:
+		*rate = get_icout_frequency(LL_RCC_IC13_GetSource(), STM32_IC13_DIV);
+		break;
+#endif /* STM32_IC13_ENABLED */
+#if defined(STM32_IC14_ENABLED)
+	case STM32_SRC_IC14:
+		*rate = get_icout_frequency(LL_RCC_IC14_GetSource(), STM32_IC14_DIV);
+		break;
+#endif /* STM32_IC14_ENABLED */
+#if defined(STM32_IC15_ENABLED)
+	case STM32_SRC_IC15:
+		*rate = get_icout_frequency(LL_RCC_IC15_GetSource(), STM32_IC15_DIV);
+		break;
+#endif /* STM32_IC15_ENABLED */
+#if defined(STM32_IC16_ENABLED)
+	case STM32_SRC_IC16:
+		*rate = get_icout_frequency(LL_RCC_IC16_GetSource(), STM32_IC16_DIV);
+		break;
+#endif /* STM32_IC16_ENABLED */
+#if defined(STM32_IC17_ENABLED)
+	case STM32_SRC_IC17:
+		*rate = get_icout_frequency(LL_RCC_IC17_GetSource(), STM32_IC17_DIV);
+		break;
+#endif /* STM32_IC17_ENABLED */
+#if defined(STM32_IC18_ENABLED)
+	case STM32_SRC_IC18:
+		*rate = get_icout_frequency(LL_RCC_IC18_GetSource(), STM32_IC18_DIV);
+		break;
+#endif /* STM32_IC18_ENABLED */
+#if defined(STM32_IC19_ENABLED)
+	case STM32_SRC_IC19:
+		*rate = get_icout_frequency(LL_RCC_IC19_GetSource(), STM32_IC19_DIV);
+		break;
+#endif /* STM32_IC19_ENABLED */
+#if defined(STM32_IC20_ENABLED)
+	case STM32_SRC_IC20:
+		*rate = get_icout_frequency(LL_RCC_IC20_GetSource(), STM32_IC20_DIV);
+		break;
+#endif /* STM32_IC20_ENABLED */
+	case STM32_SRC_TIMG:
+		*rate = sys_clock / STM32_TIMG_PRESCALER;
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	if (pclken->div) {
+		*rate /= (pclken->div + 1);
+	}
+
+	return 0;
+}
+
+static enum clock_control_status stm32_clock_control_get_status(const struct device *dev,
+								clock_control_subsys_t sub_system)
+{
+	struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
+
+	ARG_UNUSED(dev);
+
+	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == true) {
+		/* Gated clocks */
+		if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr)
+		    == pclken->enr) {
+			return CLOCK_CONTROL_STATUS_ON;
+		} else {
+			return CLOCK_CONTROL_STATUS_OFF;
+		}
+	} else {
+		/* Domain clock sources */
+		if (enabled_clock(pclken->bus) == 0) {
+			return CLOCK_CONTROL_STATUS_ON;
+		} else {
+			return CLOCK_CONTROL_STATUS_OFF;
+		}
+	}
+}
+
+static DEVICE_API(clock_control, stm32_clock_control_api) = {
+	.on = stm32_clock_control_on,
+	.off = stm32_clock_control_off,
+	.get_rate = stm32_clock_control_get_subsys_rate,
+	.get_status = stm32_clock_control_get_status,
+	.configure = stm32_clock_control_configure,
+};
+
+/*
+ * Unconditionally switch the system clock source to HSI.
+ */
+__unused
+static void stm32_clock_switch_to_hsi(void)
+{
+	/* Enable HSI if not enabled */
+	if (LL_RCC_HSI_IsReady() != 1) {
+		/* Enable HSI */
+		LL_RCC_HSI_Enable();
+		while (LL_RCC_HSI_IsReady() != 1) {
+			/* Wait for HSI ready */
+		}
+	}
+
+	/* Set HSI as SYSCLCK source */
+	LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSI);
+	while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSI) {
+	}
+
+	LL_RCC_SetCpuClkSource(LL_RCC_CPU_CLKSOURCE_HSI);
+	while (LL_RCC_GetCpuClkSource() != LL_RCC_CPU_CLKSOURCE_STATUS_HSI) {
+	}
+}
+
+static int set_up_ics(void)
+{
+#if defined(STM32_IC1_ENABLED)
+	LL_RCC_IC1_SetSource(ic_src_pll(STM32_IC1_PLL_SRC));
+	LL_RCC_IC1_SetDivider(STM32_IC1_DIV);
+	LL_RCC_IC1_Enable();
+#endif
+
+#if defined(STM32_IC2_ENABLED)
+	LL_RCC_IC2_SetSource(ic_src_pll(STM32_IC2_PLL_SRC));
+	LL_RCC_IC2_SetDivider(STM32_IC2_DIV);
+	LL_RCC_IC2_Enable();
+#endif
+
+#if defined(STM32_IC3_ENABLED)
+	LL_RCC_IC3_SetSource(ic_src_pll(STM32_IC3_PLL_SRC));
+	LL_RCC_IC3_SetDivider(STM32_IC3_DIV);
+	LL_RCC_IC3_Enable();
+#endif
+
+#if defined(STM32_IC4_ENABLED)
+	LL_RCC_IC4_SetSource(ic_src_pll(STM32_IC4_PLL_SRC));
+	LL_RCC_IC4_SetDivider(STM32_IC4_DIV);
+	LL_RCC_IC4_Enable();
+#endif
+
+#if defined(STM32_IC5_ENABLED)
+	LL_RCC_IC5_SetSource(ic_src_pll(STM32_IC5_PLL_SRC));
+	LL_RCC_IC5_SetDivider(STM32_IC5_DIV);
+	LL_RCC_IC5_Enable();
+#endif
+
+#if defined(STM32_IC6_ENABLED)
+	LL_RCC_IC6_SetSource(ic_src_pll(STM32_IC6_PLL_SRC));
+	LL_RCC_IC6_SetDivider(STM32_IC6_DIV);
+	LL_RCC_IC6_Enable();
+#endif
+
+#if defined(STM32_IC7_ENABLED)
+	LL_RCC_IC7_SetSource(ic_src_pll(STM32_IC7_PLL_SRC));
+	LL_RCC_IC7_SetDivider(STM32_IC7_DIV);
+	LL_RCC_IC7_Enable();
+#endif
+
+#if defined(STM32_IC8_ENABLED)
+	LL_RCC_IC8_SetSource(ic_src_pll(STM32_IC8_PLL_SRC));
+	LL_RCC_IC8_SetDivider(STM32_IC8_DIV);
+	LL_RCC_IC8_Enable();
+#endif
+
+#if defined(STM32_IC9_ENABLED)
+	LL_RCC_IC9_SetSource(ic_src_pll(STM32_IC9_PLL_SRC));
+	LL_RCC_IC9_SetDivider(STM32_IC9_DIV);
+	LL_RCC_IC9_Enable();
+#endif
+
+#if defined(STM32_IC10_ENABLED)
+	LL_RCC_IC10_SetSource(ic_src_pll(STM32_IC10_PLL_SRC));
+	LL_RCC_IC10_SetDivider(STM32_IC10_DIV);
+	LL_RCC_IC10_Enable();
+#endif
+
+#if defined(STM32_IC11_ENABLED)
+	LL_RCC_IC11_SetSource(ic_src_pll(STM32_IC11_PLL_SRC));
+	LL_RCC_IC11_SetDivider(STM32_IC11_DIV);
+	LL_RCC_IC11_Enable();
+#endif
+
+#if defined(STM32_IC12_ENABLED)
+	LL_RCC_IC12_SetSource(ic_src_pll(STM32_IC12_PLL_SRC));
+	LL_RCC_IC12_SetDivider(STM32_IC12_DIV);
+	LL_RCC_IC12_Enable();
+#endif
+
+#if defined(STM32_IC13_ENABLED)
+	LL_RCC_IC13_SetSource(ic_src_pll(STM32_IC13_PLL_SRC));
+	LL_RCC_IC13_SetDivider(STM32_IC13_DIV);
+	LL_RCC_IC13_Enable();
+#endif
+
+#if defined(STM32_IC14_ENABLED)
+	LL_RCC_IC14_SetSource(ic_src_pll(STM32_IC14_PLL_SRC));
+	LL_RCC_IC14_SetDivider(STM32_IC14_DIV);
+	LL_RCC_IC14_Enable();
+#endif
+
+#if defined(STM32_IC15_ENABLED)
+	LL_RCC_IC15_SetSource(ic_src_pll(STM32_IC15_PLL_SRC));
+	LL_RCC_IC15_SetDivider(STM32_IC15_DIV);
+	LL_RCC_IC15_Enable();
+#endif
+
+#if defined(STM32_IC16_ENABLED)
+	LL_RCC_IC16_SetSource(ic_src_pll(STM32_IC16_PLL_SRC));
+	LL_RCC_IC16_SetDivider(STM32_IC16_DIV);
+	LL_RCC_IC16_Enable();
+#endif
+
+#if defined(STM32_IC17_ENABLED)
+	LL_RCC_IC17_SetSource(ic_src_pll(STM32_IC17_PLL_SRC));
+	LL_RCC_IC17_SetDivider(STM32_IC17_DIV);
+	LL_RCC_IC17_Enable();
+#endif
+
+#if defined(STM32_IC18_ENABLED)
+	LL_RCC_IC18_SetSource(ic_src_pll(STM32_IC18_PLL_SRC));
+	LL_RCC_IC18_SetDivider(STM32_IC18_DIV);
+	LL_RCC_IC18_Enable();
+#endif
+
+#if defined(STM32_IC19_ENABLED)
+	LL_RCC_IC19_SetSource(ic_src_pll(STM32_IC19_PLL_SRC));
+	LL_RCC_IC19_SetDivider(STM32_IC19_DIV);
+	LL_RCC_IC19_Enable();
+#endif
+
+#if defined(STM32_IC20_ENABLED)
+	LL_RCC_IC20_SetSource(ic_src_pll(STM32_IC20_PLL_SRC));
+	LL_RCC_IC20_SetDivider(STM32_IC20_DIV);
+	LL_RCC_IC20_Enable();
+#endif
+
+	return 0;
+}
+
+static int set_up_plls(void)
+{
+#if defined(STM32_PLL1_ENABLED)
+	/* TODO: Do not switch systematically on HSI if not needed */
+	stm32_clock_switch_to_hsi();
+
+	LL_RCC_PLL1_Disable();
+
+	/* Configure PLL source : Can be HSE, HSI, MSI */
+	if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
+		/* Main PLL configuration and activation */
+		LL_RCC_PLL1_SetSource(LL_RCC_PLLSOURCE_HSE);
+	} else if (IS_ENABLED(STM32_PLL_SRC_MSI)) {
+		/* Main PLL configuration and activation */
+		LL_RCC_PLL1_SetSource(LL_RCC_PLLSOURCE_MSI);
+	} else if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
+		/* Main PLL configuration and activation */
+		LL_RCC_PLL1_SetSource(LL_RCC_PLLSOURCE_HSI);
+	} else {
+		return -ENOTSUP;
+	}
+
+	/* Disable PLL1 modulation spread-spectrum */
+	LL_RCC_PLL1_DisableModulationSpreadSpectrum();
+
+	/* Disable bypass to use the PLL VCO */
+	if (LL_RCC_PLL1_IsEnabledBypass()) {
+		LL_RCC_PLL1_DisableBypass();
+	}
+
+	/* Configure PLL */
+	LL_RCC_PLL1_SetM(STM32_PLL1_M_DIVISOR);
+	LL_RCC_PLL1_SetN(STM32_PLL1_N_MULTIPLIER);
+	LL_RCC_PLL1_SetP1(STM32_PLL1_P1_DIVISOR);
+	LL_RCC_PLL1_SetP2(STM32_PLL1_P2_DIVISOR);
+
+	/* Disable fractional mode */
+	LL_RCC_PLL1_SetFRACN(0);
+	LL_RCC_PLL1_DisableFractionalModulationSpreadSpectrum();
+
+	LL_RCC_PLL1_AssertModulationSpreadSpectrumReset();
+
+	/* Enable post division */
+	if (!LL_RCC_PLL1P_IsEnabled()) {
+		LL_RCC_PLL1P_Enable();
+	}
+
+	LL_RCC_PLL1_Enable();
+	while (LL_RCC_PLL1_IsReady() != 1U) {
+	}
+#endif /* STM32_PLL1_ENABLED */
+
+#if defined(STM32_PLL2_ENABLED)
+	LL_RCC_PLL2_Disable();
+
+	/* Configure PLL source : Can be HSE, HSI, MSI */
+	if (IS_ENABLED(STM32_PLL2_SRC_HSE)) {
+		/* Main PLL configuration and activation */
+		LL_RCC_PLL2_SetSource(LL_RCC_PLLSOURCE_HSE);
+	} else if (IS_ENABLED(STM32_PLL2_SRC_MSI)) {
+		/* Main PLL configuration and activation */
+		LL_RCC_PLL2_SetSource(LL_RCC_PLLSOURCE_MSI);
+	} else if (IS_ENABLED(STM32_PLL2_SRC_HSI)) {
+		/* Main PLL configuration and activation */
+		LL_RCC_PLL2_SetSource(LL_RCC_PLLSOURCE_HSI);
+	} else {
+		return -ENOTSUP;
+	}
+
+	/* Disable PLL2 modulation spread-spectrum */
+	LL_RCC_PLL2_DisableModulationSpreadSpectrum();
+
+	/* Disable bypass to use the PLL VCO */
+	if (LL_RCC_PLL2_IsEnabledBypass()) {
+		LL_RCC_PLL2_DisableBypass();
+	}
+
+	/* Configure PLL */
+	LL_RCC_PLL2_SetM(STM32_PLL2_M_DIVISOR);
+	LL_RCC_PLL2_SetN(STM32_PLL2_N_MULTIPLIER);
+	LL_RCC_PLL2_SetP1(STM32_PLL2_P1_DIVISOR);
+	LL_RCC_PLL2_SetP2(STM32_PLL2_P2_DIVISOR);
+
+	/* Disable fractional mode */
+	LL_RCC_PLL2_SetFRACN(0);
+	LL_RCC_PLL2_DisableFractionalModulationSpreadSpectrum();
+
+	LL_RCC_PLL2_AssertModulationSpreadSpectrumReset();
+
+	/* Enable post division */
+	if (!LL_RCC_PLL2P_IsEnabled()) {
+		LL_RCC_PLL2P_Enable();
+	}
+
+	LL_RCC_PLL2_Enable();
+	while (LL_RCC_PLL2_IsReady() != 1U) {
+	}
+#endif
+
+#if defined(STM32_PLL3_ENABLED)
+	LL_RCC_PLL3_Disable();
+
+	/* Configure PLL source : Can be HSE, HSI, MSIS */
+	if (IS_ENABLED(STM32_PLL3_SRC_HSE)) {
+		/* Main PLL configuration and activation */
+		LL_RCC_PLL3_SetSource(LL_RCC_PLLSOURCE_HSE);
+	} else if (IS_ENABLED(STM32_PLL3_SRC_MSI)) {
+		/* Main PLL configuration and activation */
+		LL_RCC_PLL3_SetSource(LL_RCC_PLLSOURCE_MSI);
+	} else if (IS_ENABLED(STM32_PLL3_SRC_HSI)) {
+		/* Main PLL configuration and activation */
+		LL_RCC_PLL3_SetSource(LL_RCC_PLLSOURCE_HSI);
+	} else {
+		return -ENOTSUP;
+	}
+
+	/* Disable PLL3 modulation spread-spectrum */
+	LL_RCC_PLL3_DisableModulationSpreadSpectrum();
+
+	/* Disable bypass to use the PLL VCO */
+	if (LL_RCC_PLL3_IsEnabledBypass()) {
+		LL_RCC_PLL3_DisableBypass();
+	}
+
+	/* Configure PLL */
+	LL_RCC_PLL3_SetM(STM32_PLL3_M_DIVISOR);
+	LL_RCC_PLL3_SetN(STM32_PLL3_N_MULTIPLIER);
+	LL_RCC_PLL3_SetP1(STM32_PLL3_P1_DIVISOR);
+	LL_RCC_PLL3_SetP2(STM32_PLL3_P2_DIVISOR);
+
+	/* Disable fractional mode */
+	LL_RCC_PLL3_SetFRACN(0);
+	LL_RCC_PLL3_DisableFractionalModulationSpreadSpectrum();
+
+	LL_RCC_PLL3_AssertModulationSpreadSpectrumReset();
+
+	/* Enable post division */
+	if (!LL_RCC_PLL3P_IsEnabled()) {
+		LL_RCC_PLL3P_Enable();
+	}
+
+	LL_RCC_PLL3_Enable();
+	while (LL_RCC_PLL3_IsReady() != 1U) {
+	}
+#endif
+
+#if defined(STM32_PLL4_ENABLED)
+	LL_RCC_PLL4_Disable();
+
+	/* Configure PLL source : Can be HSE, HSI, MSIS */
+	if (IS_ENABLED(STM32_PLL4_SRC_HSE)) {
+		/* Main PLL configuration and activation */
+		LL_RCC_PLL4_SetSource(LL_RCC_PLLSOURCE_HSE);
+	} else if (IS_ENABLED(STM32_PLL4_SRC_MSI)) {
+		/* Main PLL configuration and activation */
+		LL_RCC_PLL4_SetSource(LL_RCC_PLLSOURCE_MSI);
+	} else if (IS_ENABLED(STM32_PLL4_SRC_HSI)) {
+		/* Main PLL configuration and activation */
+		LL_RCC_PLL4_SetSource(LL_RCC_PLLSOURCE_HSI);
+	} else {
+		return -ENOTSUP;
+	}
+
+	/* Disable PLL4 modulation spread-spectrum */
+	LL_RCC_PLL4_DisableModulationSpreadSpectrum();
+
+	/* Disable bypass to use the PLL VCO */
+	if (LL_RCC_PLL4_IsEnabledBypass()) {
+		LL_RCC_PLL4_DisableBypass();
+	}
+
+	/* Configure PLL */
+	LL_RCC_PLL4_SetM(STM32_PLL4_M_DIVISOR);
+	LL_RCC_PLL4_SetN(STM32_PLL4_N_MULTIPLIER);
+	LL_RCC_PLL4_SetP1(STM32_PLL4_P1_DIVISOR);
+	LL_RCC_PLL4_SetP2(STM32_PLL4_P2_DIVISOR);
+
+	/* Disable fractional mode */
+	LL_RCC_PLL4_SetFRACN(0);
+	LL_RCC_PLL4_DisableFractionalModulationSpreadSpectrum();
+
+	LL_RCC_PLL4_AssertModulationSpreadSpectrumReset();
+
+	/* Enable post division */
+	if (!LL_RCC_PLL4P_IsEnabled()) {
+		LL_RCC_PLL4P_Enable();
+	}
+
+	LL_RCC_PLL4_Enable();
+	while (LL_RCC_PLL4_IsReady() != 1U) {
+	}
+#endif
+
+	return 0;
+}
+
+static void set_up_fixed_clock_sources(void)
+{
+	if (IS_ENABLED(STM32_HSE_ENABLED)) {
+		/* Check if need to enable HSE bypass feature or not */
+		if (IS_ENABLED(STM32_HSE_BYPASS)) {
+			LL_RCC_HSE_EnableBypass();
+		} else {
+			LL_RCC_HSE_DisableBypass();
+		}
+
+		if (IS_ENABLED(STM32_HSE_DIV2)) {
+			LL_RCC_HSE_SelectHSEDiv2AsDiv2Clock();
+		} else {
+			LL_RCC_HSE_SelectHSEAsDiv2Clock();
+		}
+
+		/* Enable HSE */
+		LL_RCC_HSE_Enable();
+		while (LL_RCC_HSE_IsReady() != 1) {
+		/* Wait for HSE ready */
+		}
+	}
+
+	if (IS_ENABLED(STM32_HSI_ENABLED)) {
+		/* Enable HSI oscillator */
+		LL_RCC_HSI_Enable();
+		while (LL_RCC_HSI_IsReady() != 1) {
+		}
+		/* HSI divider configuration */
+		LL_RCC_HSI_SetDivider(hsi_divider(STM32_HSI_DIVISOR));
+	}
+
+	if (IS_ENABLED(STM32_LSE_ENABLED)) {
+		/* Enable the power interface clock */
+		LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
+
+		if (!LL_PWR_IsEnabledBkUpAccess()) {
+			/* Enable write access to Backup domain */
+			LL_PWR_EnableBkUpAccess();
+			while (!LL_PWR_IsEnabledBkUpAccess()) {
+				/* Wait for Backup domain access */
+			}
+		}
+
+		/* Configure driving capability */
+		LL_RCC_LSE_SetDriveCapability(STM32_LSE_DRIVING << RCC_LSECFGR_LSEDRV_Pos);
+
+		if (IS_ENABLED(STM32_LSE_BYPASS)) {
+			/* Configure LSE bypass */
+			LL_RCC_LSE_EnableBypass();
+		}
+
+		/* Enable LSE Oscillator */
+		LL_RCC_LSE_Enable();
+		/* Wait for LSE ready */
+		while (!LL_RCC_LSE_IsReady()) {
+		}
+
+		LL_PWR_DisableBkUpAccess();
+	}
+
+	if (IS_ENABLED(STM32_LSI_ENABLED)) {
+		/* Enable LSI oscillator */
+		LL_RCC_LSI_Enable();
+		while (LL_RCC_LSI_IsReady() != 1) {
+		}
+	}
+}
+
+int stm32_clock_control_init(const struct device *dev)
+{
+	int r = 0;
+
+	ARG_UNUSED(dev);
+
+	/* For now, enable clocks (including low_power ones) of all RAM */
+	uint32_t all_ram = LL_MEM_AXISRAM1 | LL_MEM_AXISRAM2 | LL_MEM_AXISRAM3 | LL_MEM_AXISRAM4 |
+			   LL_MEM_AXISRAM5 | LL_MEM_AXISRAM6 | LL_MEM_AHBSRAM1 | LL_MEM_AHBSRAM2 |
+			   LL_MEM_BKPSRAM | LL_MEM_FLEXRAM | LL_MEM_CACHEAXIRAM | LL_MEM_VENCRAM;
+	LL_MEM_EnableClock(all_ram);
+	LL_MEM_EnableClockLowPower(all_ram);
+
+	/* Set up individual enabled clocks */
+	set_up_fixed_clock_sources();
+
+	/* Set up PLLs */
+	r = set_up_plls();
+	if (r < 0) {
+		return r;
+	}
+
+	/* Preset the prescalers prior to chosing SYSCLK */
+	/* Prevents APB clock to go over limits */
+	/* Set buses (AHB, APB1, APB2, APB4 & APB5) prescalers */
+	LL_RCC_SetAHBPrescaler(ahb_prescaler(STM32_AHB_PRESCALER));
+	LL_RCC_SetAPB1Prescaler(apb1_prescaler(STM32_APB1_PRESCALER));
+	LL_RCC_SetAPB2Prescaler(apb2_prescaler(STM32_APB2_PRESCALER));
+	LL_RCC_SetAPB4Prescaler(apb4_prescaler(STM32_APB4_PRESCALER));
+	LL_RCC_SetAPB5Prescaler(apb5_prescaler(STM32_APB5_PRESCALER));
+
+	/* Set TIMG presclar */
+	LL_RCC_SetTIMPrescaler(timg_prescaler(STM32_TIMG_PRESCALER));
+
+	if (IS_ENABLED(STM32_CKPER_ENABLED)) {
+		LL_MISC_EnableClock(LL_PER);
+		LL_MISC_EnableClockLowPower(LL_PER);
+		while (LL_MISC_IsEnabledClock(LL_PER) != 1) {
+		}
+	}
+
+	/* Set up ICs */
+	r = set_up_ics();
+	if (r < 0) {
+		return r;
+	}
+
+	/* Set up sys clock */
+	if (IS_ENABLED(STM32_SYSCLK_SRC_HSE)) {
+		/* Set sysclk source to HSE */
+		LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSE);
+		while (LL_RCC_GetSysClkSource() !=
+					LL_RCC_SYS_CLKSOURCE_STATUS_HSE) {
+		}
+	} else if (IS_ENABLED(STM32_SYSCLK_SRC_HSI)) {
+		/* Set sysclk source to HSI */
+		stm32_clock_switch_to_hsi();
+	} else if (IS_ENABLED(STM32_SYSCLK_SRC_IC2)) {
+		/* Set sysclk source to IC2 */
+		LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_IC2_IC6_IC11);
+		while (LL_RCC_GetSysClkSource() !=
+					LL_RCC_SYS_CLKSOURCE_STATUS_IC2_IC6_IC11) {
+		}
+	} else {
+		return -ENOTSUP;
+	}
+
+	/* Update CMSIS variable */
+	SystemCoreClock = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
+
+	return r;
+}
+
+/**
+ * @brief RCC device, note that priority is intentionally set to 1 so
+ * that the device init runs just after SOC init
+ */
+DEVICE_DT_DEFINE(DT_NODELABEL(rcc),
+		    &stm32_clock_control_init,
+		    NULL,
+		    NULL, NULL,
+		    PRE_KERNEL_1,
+		    CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
+		    &stm32_clock_control_api);
diff --git a/drivers/clock_control/clock_stm32_ll_u5.c b/drivers/clock_control/clock_stm32_ll_u5.c
index c32c72820cf..94448d51416 100644
--- a/drivers/clock_control/clock_stm32_ll_u5.c
+++ b/drivers/clock_control/clock_stm32_ll_u5.c
@@ -150,15 +150,14 @@ int enabled_clock(uint32_t src_clk)
 	return -ENOTSUP;
 }
 
-static inline int stm32_clock_control_on(const struct device *dev,
-					 clock_control_subsys_t sub_system)
+static int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
 	volatile int temp;
 
 	ARG_UNUSED(dev);
 
-	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
+	if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
 		/* Attempt to toggle a wrong periph clock bit */
 		return -ENOTSUP;
 	}
@@ -172,14 +171,13 @@ static inline int stm32_clock_control_on(const struct device *dev,
 	return 0;
 }
 
-static inline int stm32_clock_control_off(const struct device *dev,
-					  clock_control_subsys_t sub_system)
+static int stm32_clock_control_off(const struct device *dev, clock_control_subsys_t sub_system)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
 
 	ARG_UNUSED(dev);
 
-	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
+	if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
 		/* Attempt to toggle a wrong periph clock bit */
 		return -ENOTSUP;
 	}
@@ -190,9 +188,9 @@ static inline int stm32_clock_control_off(const struct device *dev,
 	return 0;
 }
 
-static inline int stm32_clock_control_configure(const struct device *dev,
-						clock_control_subsys_t sub_system,
-						void *data)
+static int stm32_clock_control_configure(const struct device *dev,
+					 clock_control_subsys_t sub_system,
+					 void *data)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
 	int err;
@@ -206,10 +204,12 @@ static inline int stm32_clock_control_configure(const struct device *dev,
 		return err;
 	}
 
-	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
-		       STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
-	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
-		     STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
+	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
+		       STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
+			STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
+	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
+		     STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
+			STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
 
 	return 0;
 }
@@ -371,7 +371,7 @@ static enum clock_control_status stm32_clock_control_get_status(const struct dev
 
 	ARG_UNUSED(dev);
 
-	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == true) {
+	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
 		/* Gated clocks */
 		if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr)
 		    == pclken->enr) {
diff --git a/drivers/clock_control/clock_stm32_ll_wb0.c b/drivers/clock_control/clock_stm32_ll_wb0.c
index f5375d2d8b3..e4e856c784d 100644
--- a/drivers/clock_control/clock_stm32_ll_wb0.c
+++ b/drivers/clock_control/clock_stm32_ll_wb0.c
@@ -206,8 +206,7 @@ int enabled_clock(uint32_t src_clk)
 	return r;
 }
 
-static inline int stm32_clock_control_on(const struct device *dev,
-					 clock_control_subsys_t sub_system)
+static int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
 	const mem_addr_t reg = RCC_REG(pclken->bus);
@@ -230,8 +229,7 @@ static inline int stm32_clock_control_on(const struct device *dev,
 	return 0;
 }
 
-static inline int stm32_clock_control_off(const struct device *dev,
-					  clock_control_subsys_t sub_system)
+static int stm32_clock_control_off(const struct device *dev, clock_control_subsys_t sub_system)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
 	const mem_addr_t reg = RCC_REG(pclken->bus);
@@ -247,13 +245,13 @@ static inline int stm32_clock_control_off(const struct device *dev,
 	return 0;
 }
 
-static inline int stm32_clock_control_configure(const struct device *dev,
-						clock_control_subsys_t sub_system,
-						void *data)
+static int stm32_clock_control_configure(const struct device *dev,
+					 clock_control_subsys_t sub_system,
+					 void *data)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)sub_system;
-	const uint32_t shift = STM32_CLOCK_SHIFT_GET(pclken->enr);
-	mem_addr_t reg = RCC_REG(STM32_CLOCK_REG_GET(pclken->enr));
+	const uint32_t shift = STM32_DT_CLKSEL_SHIFT_GET(pclken->enr);
+	mem_addr_t reg = RCC_REG(STM32_DT_CLKSEL_REG_GET(pclken->enr));
 	int err;
 
 	ARG_UNUSED(dev);
@@ -265,13 +263,13 @@ static inline int stm32_clock_control_configure(const struct device *dev,
 		return err;
 	}
 
-	sys_clear_bits(reg, STM32_CLOCK_MASK_GET(pclken->enr) << shift);
-	sys_set_bits(reg, STM32_CLOCK_VAL_GET(pclken->enr) << shift);
+	sys_clear_bits(reg, STM32_DT_CLKSEL_MASK_GET(pclken->enr) << shift);
+	sys_set_bits(reg, STM32_DT_CLKSEL_VAL_GET(pclken->enr) << shift);
 
 	return 0;
 }
 
-static inline int get_apb0_periph_clkrate(struct stm32_pclken *pclken,
+static int get_apb0_periph_clkrate(struct stm32_pclken *pclken,
 	uint32_t *rate, uint32_t slow_clock, uint32_t sysclk, uint32_t clk_sys)
 {
 	switch (pclken->enr) {
@@ -312,8 +310,7 @@ static inline int get_apb0_periph_clkrate(struct stm32_pclken *pclken,
 	return 0;
 }
 
-static inline int get_apb1_periph_clkrate(struct stm32_pclken *pclken,
-	uint32_t *rate, uint32_t clk_sys)
+static int get_apb1_periph_clkrate(struct stm32_pclken *pclken, uint32_t *rate, uint32_t clk_sys)
 {
 	switch (pclken->enr) {
 #if defined(SPI1)
@@ -603,7 +600,7 @@ static void set_up_fixed_clock_sources(void)
  * @brief Converts the Kconfig STM32_WB0_CLKSYS_PRESCALER option
  * to a LL_RCC_RC64MPLL_DIV_x value understandable by the LL.
  */
-static inline uint32_t kconfig_to_ll_prescaler(uint32_t kcfg_pre)
+static uint32_t kconfig_to_ll_prescaler(uint32_t kcfg_pre)
 {
 	switch (kcfg_pre) {
 	case 1:
diff --git a/drivers/clock_control/clock_stm32_ll_wba.c b/drivers/clock_control/clock_stm32_ll_wba.c
index 323d0f1ae5f..ca888b690e8 100644
--- a/drivers/clock_control/clock_stm32_ll_wba.c
+++ b/drivers/clock_control/clock_stm32_ll_wba.c
@@ -62,15 +62,14 @@ int enabled_clock(uint32_t src_clk)
 	return -ENOTSUP;
 }
 
-static inline int stm32_clock_control_on(const struct device *dev,
-					 clock_control_subsys_t sub_system)
+static int stm32_clock_control_on(const struct device *dev, clock_control_subsys_t sub_system)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
 	volatile int temp;
 
 	ARG_UNUSED(dev);
 
-	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
+	if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
 		/* Attempt to toggle a wrong periph clock bit */
 		return -ENOTSUP;
 	}
@@ -84,14 +83,13 @@ static inline int stm32_clock_control_on(const struct device *dev,
 	return 0;
 }
 
-static inline int stm32_clock_control_off(const struct device *dev,
-					  clock_control_subsys_t sub_system)
+static int stm32_clock_control_off(const struct device *dev, clock_control_subsys_t sub_system)
 {
 	struct stm32_pclken *pclken = (struct stm32_pclken *)(sub_system);
 
 	ARG_UNUSED(dev);
 
-	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == 0) {
+	if (!IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
 		/* Attempt to toggle a wrong periph clock bit */
 		return -ENOTSUP;
 	}
@@ -102,9 +100,9 @@ static inline int stm32_clock_control_off(const struct device *dev,
 	return 0;
 }
 
-static inline int stm32_clock_control_configure(const struct device *dev,
-						clock_control_subsys_t sub_system,
-						void *data)
+static int stm32_clock_control_configure(const struct device *dev,
+					 clock_control_subsys_t sub_system,
+					 void *data)
 {
 #if defined(STM32_SRC_CLOCK_MIN)
 	/* At least one alt src clock available */
@@ -120,10 +118,12 @@ static inline int stm32_clock_control_configure(const struct device *dev,
 		return err;
 	}
 
-	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
-		       STM32_CLOCK_MASK_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
-	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_CLOCK_REG_GET(pclken->enr),
-		     STM32_CLOCK_VAL_GET(pclken->enr) << STM32_CLOCK_SHIFT_GET(pclken->enr));
+	sys_clear_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
+		       STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
+			STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
+	sys_set_bits(DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
+		     STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
+			STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
 
 	return 0;
 #else
@@ -285,7 +285,7 @@ static enum clock_control_status stm32_clock_control_get_status(const struct dev
 
 	ARG_UNUSED(dev);
 
-	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX) == true) {
+	if (IN_RANGE(pclken->bus, STM32_PERIPH_BUS_MIN, STM32_PERIPH_BUS_MAX)) {
 		/* Gated clocks */
 		if ((sys_read32(DT_REG_ADDR(DT_NODELABEL(rcc)) + pclken->bus) & pclken->enr)
 		    == pclken->enr) {
diff --git a/drivers/clock_control/clock_stm32_mco.c b/drivers/clock_control/clock_stm32_mco.c
index 0e8d6faec26..1a524d74c59 100644
--- a/drivers/clock_control/clock_stm32_mco.c
+++ b/drivers/clock_control/clock_stm32_mco.c
@@ -41,24 +41,24 @@ static int stm32_mco_init(const struct device *dev)
 
 	/* MCO source */
 	sys_clear_bits(
-		DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_MCO_CFGR_REG_GET(pclken->enr),
-		STM32_MCO_CFGR_MASK_GET(pclken->enr) <<
-			STM32_MCO_CFGR_SHIFT_GET(pclken->enr));
+		DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
+		STM32_DT_CLKSEL_MASK_GET(pclken->enr) <<
+			STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
 	sys_set_bits(
-		DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_MCO_CFGR_REG_GET(pclken->enr),
-		STM32_MCO_CFGR_VAL_GET(pclken->enr) <<
-			STM32_MCO_CFGR_SHIFT_GET(pclken->enr));
+		DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(pclken->enr),
+		STM32_DT_CLKSEL_VAL_GET(pclken->enr) <<
+			STM32_DT_CLKSEL_SHIFT_GET(pclken->enr));
 
 #if defined(HAS_PRESCALER)
 	/* MCO prescaler */
 	sys_clear_bits(
-		DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_MCO_CFGR_REG_GET(config->prescaler),
-		STM32_MCO_CFGR_MASK_GET(config->prescaler) <<
-			STM32_MCO_CFGR_SHIFT_GET(config->prescaler));
+		DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(config->prescaler),
+		STM32_DT_CLKSEL_MASK_GET(config->prescaler) <<
+			STM32_DT_CLKSEL_SHIFT_GET(config->prescaler));
 	sys_set_bits(
-		DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_MCO_CFGR_REG_GET(config->prescaler),
-		STM32_MCO_CFGR_VAL_GET(config->prescaler) <<
-			STM32_MCO_CFGR_SHIFT_GET(config->prescaler));
+		DT_REG_ADDR(DT_NODELABEL(rcc)) + STM32_DT_CLKSEL_REG_GET(config->prescaler),
+		STM32_DT_CLKSEL_VAL_GET(config->prescaler) <<
+			STM32_DT_CLKSEL_SHIFT_GET(config->prescaler));
 #endif
 
 	return pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
diff --git a/drivers/clock_control/clock_stm32f2_f4_f7.c b/drivers/clock_control/clock_stm32f2_f4_f7.c
index 59f78867542..c391d508b30 100644
--- a/drivers/clock_control/clock_stm32f2_f4_f7.c
+++ b/drivers/clock_control/clock_stm32f2_f4_f7.c
@@ -157,7 +157,8 @@ void config_plli2s(void)
 				       STM32_PLLI2S_N_MULTIPLIER,
 				       plli2sr(STM32_PLLI2S_R_DIVISOR));
 
-#if STM32_PLLI2S_Q_ENABLED
+#if STM32_PLLI2S_Q_ENABLED && \
+	(defined(RCC_PLLI2SCFGR_PLLI2SQ) && !defined(RCC_DCKCFGR_PLLI2SDIVQ))
 	/* There is a Q divider on the PLLI2S to configure the PLL48CK */
 	LL_RCC_PLLI2S_ConfigDomain_48M(get_pll_source(),
 				       plli2sm(STM32_PLLI2S_M_DIVISOR),
diff --git a/drivers/comparator/CMakeLists.txt b/drivers/comparator/CMakeLists.txt
index 43462d64288..5d8ef055461 100644
--- a/drivers/comparator/CMakeLists.txt
+++ b/drivers/comparator/CMakeLists.txt
@@ -6,8 +6,10 @@ zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/comparator.h)
 zephyr_library()
 
 zephyr_library_sources_ifdef(CONFIG_USERSPACE comparator_handlers.c)
+zephyr_library_sources_ifdef(CONFIG_COMPARATOR_SILABS_ACMP comparator_silabs_acmp.c)
 zephyr_library_sources_ifdef(CONFIG_COMPARATOR_FAKE_COMP comparator_fake_comp.c)
 zephyr_library_sources_ifdef(CONFIG_COMPARATOR_MCUX_ACMP comparator_mcux_acmp.c)
 zephyr_library_sources_ifdef(CONFIG_COMPARATOR_NRF_COMP comparator_nrf_comp.c)
 zephyr_library_sources_ifdef(CONFIG_COMPARATOR_NRF_LPCOMP comparator_nrf_lpcomp.c)
 zephyr_library_sources_ifdef(CONFIG_COMPARATOR_SHELL comparator_shell.c)
+zephyr_library_sources_ifdef(CONFIG_COMPARATOR_RENESAS_RA comparator_renesas_ra.c)
diff --git a/drivers/comparator/Kconfig b/drivers/comparator/Kconfig
index 978adc03251..2cc02c24085 100644
--- a/drivers/comparator/Kconfig
+++ b/drivers/comparator/Kconfig
@@ -19,9 +19,11 @@ config COMPARATOR_INIT_PRIORITY
 	  Comparator device driver initialization priority.
 
 rsource "Kconfig.fake_comp"
+rsource "Kconfig.silabs_acmp"
 rsource "Kconfig.mcux_acmp"
 rsource "Kconfig.nrf_comp"
 rsource "Kconfig.nrf_lpcomp"
 rsource "Kconfig.shell"
+rsource "Kconfig.renesas_ra"
 
 endif # COMPARATOR
diff --git a/drivers/comparator/Kconfig.mcux_acmp b/drivers/comparator/Kconfig.mcux_acmp
index 8109cb1cdd2..be4467c8e43 100644
--- a/drivers/comparator/Kconfig.mcux_acmp
+++ b/drivers/comparator/Kconfig.mcux_acmp
@@ -6,4 +6,3 @@ config COMPARATOR_MCUX_ACMP
 	default y
 	depends on DT_HAS_NXP_KINETIS_ACMP_ENABLED
 	select PINCTRL
-	select MCUX_ACMP
diff --git a/drivers/comparator/Kconfig.renesas_ra b/drivers/comparator/Kconfig.renesas_ra
new file mode 100644
index 00000000000..f66390a32ab
--- /dev/null
+++ b/drivers/comparator/Kconfig.renesas_ra
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config COMPARATOR_RENESAS_RA
+	bool "Renesas RA ACMPHS"
+	default y
+	depends on DT_HAS_RENESAS_RA_ACMPHS_ENABLED
+	select USE_RA_FSP_ACMPHS
+	select PINCTRL
+	help
+	  Enable Renesas RA ACMPHS Driver.
diff --git a/drivers/comparator/Kconfig.silabs_acmp b/drivers/comparator/Kconfig.silabs_acmp
new file mode 100644
index 00000000000..db684e91f9b
--- /dev/null
+++ b/drivers/comparator/Kconfig.silabs_acmp
@@ -0,0 +1,12 @@
+# Copyright (c) 2025 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+config COMPARATOR_SILABS_ACMP
+	bool "Silabs ACMP comparator driver"
+	default y
+	depends on DT_HAS_SILABS_ACMP_ENABLED
+	select PINCTRL
+	select SOC_SILABS_ACMP
+	help
+	  Enable the comparator driver for the Analog Comparator hardware block
+	  present on Silicon Labs devices. This block is commonly used to
+	  monitor the power supply.
diff --git a/drivers/comparator/comparator_renesas_ra.c b/drivers/comparator/comparator_renesas_ra.c
new file mode 100644
index 00000000000..6b0cb98249b
--- /dev/null
+++ b/drivers/comparator/comparator_renesas_ra.c
@@ -0,0 +1,282 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_ra_acmphs
+
+#include <zephyr/drivers/comparator.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/kernel.h>
+#include <zephyr/irq.h>
+#include <soc.h>
+#include "r_acmphs.h"
+
+LOG_MODULE_REGISTER(acmphs_renesas_ra, CONFIG_COMPARATOR_LOG_LEVEL);
+
+#define ACMPHS_RENESAS_RA_FLAG_HS BIT(0)
+
+void comp_hs_int_isr(void);
+
+struct acmphs_renesas_ra_global_config {
+	const struct pinctrl_dev_config *pcfg;
+};
+
+struct acmphs_renesas_ra_config {
+	const struct pinctrl_dev_config *pcfg;
+};
+
+struct acmphs_renesas_ra_data {
+	const struct device *dev;
+	acmphs_instance_ctrl_t acmphs;
+	comparator_cfg_t fsp_config;
+	comparator_callback_t user_cb;
+	void *user_cb_data;
+	atomic_t flags;
+};
+
+static int acmphs_renesas_get_output(const struct device *dev)
+{
+	struct acmphs_renesas_ra_data *data = dev->data;
+	comparator_status_t status;
+	fsp_err_t fsp_err;
+
+	fsp_err = R_ACMPHS_StatusGet(&data->acmphs, &status);
+	if (FSP_SUCCESS != fsp_err) {
+		return -EIO;
+	}
+
+	switch (status.state) {
+	case COMPARATOR_STATE_OUTPUT_LOW:
+		return 0;
+
+	case COMPARATOR_STATE_OUTPUT_HIGH:
+		return 1;
+
+	case COMPARATOR_STATE_OUTPUT_DISABLED:
+		LOG_ERR("Need to set trigger to open comparator first");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int acmphs_renesas_set_trigger(const struct device *dev, enum comparator_trigger trigger)
+{
+	struct acmphs_renesas_ra_data *data = dev->data;
+
+	/* Disable interrupt */
+	data->acmphs.p_reg->CMPCTL &= ~R_ACMPHS0_CMPCTL_CEG_Msk;
+
+	switch (trigger) {
+	case COMPARATOR_TRIGGER_RISING_EDGE:
+		data->fsp_config.trigger = COMPARATOR_TRIGGER_RISING;
+		break;
+
+	case COMPARATOR_TRIGGER_FALLING_EDGE:
+		data->fsp_config.trigger = COMPARATOR_TRIGGER_FALLING;
+		break;
+
+	case COMPARATOR_TRIGGER_BOTH_EDGES:
+		data->fsp_config.trigger = COMPARATOR_TRIGGER_BOTH_EDGE;
+		break;
+
+	case COMPARATOR_TRIGGER_NONE:
+		data->fsp_config.trigger = COMPARATOR_TRIGGER_NO_EDGE;
+		break;
+	}
+
+	data->acmphs.p_reg->CMPCTL |= (data->fsp_config.trigger << R_ACMPHS0_CMPCTL_CEG_Pos);
+
+	return 0;
+}
+
+static int acmphs_renesas_set_trigger_callback(const struct device *dev,
+					       comparator_callback_t callback, void *user_data)
+{
+	struct acmphs_renesas_ra_data *data = dev->data;
+
+	/* Disable interrupt */
+	data->acmphs.p_reg->CMPCTL &= ~R_ACMPHS0_CMPCTL_CEG_Msk;
+
+	data->user_cb = callback;
+	data->user_cb_data = user_data;
+
+	/* Enable interrupt */
+	data->acmphs.p_reg->CMPCTL |= (data->fsp_config.trigger << R_ACMPHS0_CMPCTL_CEG_Pos);
+
+	return 0;
+}
+
+static int acmphs_renesas_trigger_is_pending(const struct device *dev)
+{
+	struct acmphs_renesas_ra_data *data = dev->data;
+
+	if (data->flags & ACMPHS_RENESAS_RA_FLAG_HS) {
+		atomic_and(&data->flags, ~ACMPHS_RENESAS_RA_FLAG_HS);
+		return 1;
+	}
+
+	return 0;
+}
+
+static void acmphs_renesas_ra_hs_isr(comparator_callback_args_t *fsp_args)
+{
+	const struct device *dev = fsp_args->p_context;
+	struct acmphs_renesas_ra_data *data = dev->data;
+	comparator_callback_t cb = data->user_cb;
+
+	if (cb != NULL) {
+		cb(dev, data->user_cb_data);
+		return;
+	}
+
+	atomic_or(&data->flags, ACMPHS_RENESAS_RA_FLAG_HS);
+}
+
+static int acmphs_renesas_ra_global_init(const struct device *dev)
+{
+	const struct acmphs_renesas_ra_global_config *cfg = dev->config;
+	int ret;
+
+	ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret < 0) {
+		LOG_DBG("pin VCOUT initial failed");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int acmphs_renesas_ra_init(const struct device *dev)
+{
+	struct acmphs_renesas_ra_data *data = dev->data;
+	const struct acmphs_renesas_ra_config *cfg = dev->config;
+	fsp_err_t fsp_err;
+	int ret;
+
+	ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret < 0) {
+		LOG_DBG("pin default initial failed");
+		return ret;
+	}
+
+	data->fsp_config.p_context = dev;
+
+	fsp_err = R_ACMPHS_Open(&data->acmphs, &data->fsp_config);
+	if (FSP_SUCCESS != fsp_err) {
+		return -EIO;
+	}
+
+	/*
+	 * Once the analog comparator is configurate, the program must wait
+	 * for the ACMPHS stabilization time (300ns enabling + 200ns input switching)
+	 * before using the comparator.
+	 */
+	k_usleep(5);
+
+	fsp_err = R_ACMPHS_OutputEnable(&data->acmphs);
+	if (FSP_SUCCESS != fsp_err) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(comparator, acmphs_renesas_ra_api) = {
+	.get_output = acmphs_renesas_get_output,
+	.set_trigger = acmphs_renesas_set_trigger,
+	.set_trigger_callback = acmphs_renesas_set_trigger_callback,
+	.trigger_is_pending = acmphs_renesas_trigger_is_pending,
+};
+
+PINCTRL_DT_DEFINE(DT_INST(0, renesas_ra_acmphs_global));
+
+static const struct acmphs_renesas_ra_global_config acmphs_renesas_ra_global_config = {
+	.pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST(0, renesas_ra_acmphs_global)),
+};
+
+DEVICE_DT_DEFINE(DT_COMPAT_GET_ANY_STATUS_OKAY(renesas_ra_acmphs_global),
+		 acmphs_renesas_ra_global_init, NULL, NULL, &acmphs_renesas_ra_global_config,
+		 PRE_KERNEL_2, CONFIG_COMPARATOR_INIT_PRIORITY, NULL)
+
+#define ACMPHS_RENESAS_RA_IRQ_INIT(idx)                                                            \
+	{                                                                                          \
+		R_ICU->IELSR_b[DT_INST_IRQ_BY_NAME(idx, hs, irq)].IELS =                           \
+			BSP_PRV_IELS_ENUM(CONCAT(EVENT_ACMPHS, DT_INST_PROP(idx, channel), _INT)); \
+                                                                                                   \
+		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, hs, irq),                                     \
+			    DT_INST_IRQ_BY_NAME(idx, hs, priority), comp_hs_int_isr,               \
+			    DEVICE_DT_INST_GET(idx), 0);                                           \
+                                                                                                   \
+		irq_enable(DT_INST_IRQ_BY_NAME(idx, hs, irq));                                     \
+	}
+
+#define FILTER_PARAMETER(idx)                                                                      \
+	COND_CODE_1(IS_EQ(DT_INST_PROP(idx, noise_filter), 1),                                     \
+	(COMPARATOR_FILTER_OFF), (UTIL_CAT(COMPARATOR_FILTER_, DT_INST_PROP(idx, noise_filter))))
+
+#define INVERT_PARAMETER(idx)                                                                      \
+	COND_CODE_1(DT_INST_PROP(idx, output_invert_polarity),                                     \
+	(COMPARATOR_POLARITY_INVERT_ON), (COMPARATOR_POLARITY_INVERT_OFF))
+
+#define PIN_OUTPUT_PARAMETER(idx)                                                                  \
+	COND_CODE_1(DT_INST_PROP(idx, pin_output_enable),                                          \
+	(COMPARATOR_PIN_OUTPUT_ON), (COMPARATOR_PIN_OUTPUT_OFF))
+
+#define IRQ_PARAMETER(idx)                                                                         \
+	COND_CODE_1(DT_INST_IRQ_HAS_NAME(idx, hs),                                                 \
+	(DT_INST_IRQ_BY_NAME(idx, hs, irq)), (FSP_INVALID_VECTOR))
+
+#define IPL_PARAMETER(idx)                                                                         \
+	COND_CODE_1(DT_INST_IRQ_HAS_NAME(idx, hs),                                                 \
+	(DT_INST_IRQ_BY_NAME(idx, hs, priority)), (BSP_IRQ_DISABLED))
+
+#define IRQ_INIT_MACRO_FUNCTION(idx)                                                               \
+	COND_CODE_1(DT_INST_IRQ_HAS_NAME(idx, hs), (ACMPHS_RENESAS_RA_IRQ_INIT(idx);), ())
+
+#define ACMPHS_RENESAS_RA_INIT(idx)                                                                \
+	PINCTRL_DT_INST_DEFINE(idx);                                                               \
+	static r_acmphs_extended_cfg_t g_acmphs_cfg_extend_##idx = {                               \
+		.input_voltage = UTIL_CAT(ACMPHS_INPUT_,                                           \
+					  DT_INST_STRING_UPPER_TOKEN(idx, compare_input_source)),  \
+		.reference_voltage =                                                               \
+			UTIL_CAT(ACMPHS_REFERENCE_,                                                \
+				 DT_INST_STRING_UPPER_TOKEN(idx, reference_input_source)),         \
+		.maximum_status_retries = 1024,                                                    \
+	};                                                                                         \
+	static const struct acmphs_renesas_ra_config acmphs_renesas_ra_config_##idx = {            \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx),                                       \
+	};                                                                                         \
+	static struct acmphs_renesas_ra_data acmphs_renesas_ra_data_##idx = {                      \
+		.dev = DEVICE_DT_INST_GET(idx),                                                    \
+		.fsp_config =                                                                      \
+			{                                                                          \
+				.channel = DT_INST_PROP(idx, channel),                             \
+				.mode = COMPARATOR_MODE_NORMAL,                                    \
+				.trigger = COMPARATOR_TRIGGER_NO_EDGE,                             \
+				.filter = FILTER_PARAMETER(idx),                                   \
+				.invert = INVERT_PARAMETER(idx),                                   \
+				.pin_output = PIN_OUTPUT_PARAMETER(idx),                           \
+				.p_extend = &g_acmphs_cfg_extend_##idx,                            \
+				.irq = IRQ_PARAMETER(idx),                                         \
+				.ipl = IPL_PARAMETER(idx),                                         \
+				.p_callback = acmphs_renesas_ra_hs_isr,                            \
+			},                                                                         \
+		.flags = 0,                                                                        \
+	};                                                                                         \
+	static int acmphs_renesas_ra_init##idx(const struct device *dev)                           \
+	{                                                                                          \
+		IRQ_INIT_MACRO_FUNCTION(idx)                                                       \
+		return acmphs_renesas_ra_init(dev);                                                \
+	}                                                                                          \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(idx, acmphs_renesas_ra_init##idx, NULL,                              \
+			      &acmphs_renesas_ra_data_##idx, &acmphs_renesas_ra_config_##idx,      \
+			      POST_KERNEL, CONFIG_COMPARATOR_INIT_PRIORITY,                        \
+			      &acmphs_renesas_ra_api)
+
+DT_INST_FOREACH_STATUS_OKAY(ACMPHS_RENESAS_RA_INIT);
diff --git a/drivers/comparator/comparator_shell.c b/drivers/comparator/comparator_shell.c
index d8dafc35973..2723e170cef 100644
--- a/drivers/comparator/comparator_shell.c
+++ b/drivers/comparator/comparator_shell.c
@@ -216,9 +216,9 @@ static int cmd_trigger_is_pending(const struct shell *sh, size_t argc, char **ar
 	return 0;
 }
 
-static bool device_is_comp_and_ready(const struct device *dev)
+static bool device_is_comp(const struct device *dev)
 {
-	return device_is_ready(dev) && DEVICE_API_IS(comparator, dev);
+	return DEVICE_API_IS(comparator, dev);
 }
 
 static void dsub_set_trigger_lookup_1(size_t idx, struct shell_static_entry *entry)
@@ -233,7 +233,7 @@ SHELL_DYNAMIC_CMD_CREATE(dsub_set_trigger_1, dsub_set_trigger_lookup_1);
 
 static void dsub_set_trigger_lookup_0(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_filter(idx, device_is_comp_and_ready);
+	const struct device *dev = shell_device_filter(idx, device_is_comp);
 
 	entry->syntax = dev != NULL ? dev->name : NULL;
 	entry->handler = NULL;
@@ -245,7 +245,7 @@ SHELL_DYNAMIC_CMD_CREATE(dsub_set_trigger_0, dsub_set_trigger_lookup_0);
 
 static void dsub_device_lookup_0(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_filter(idx, device_is_comp_and_ready);
+	const struct device *dev = shell_device_filter(idx, device_is_comp);
 
 	entry->syntax = (dev != NULL) ? dev->name : NULL;
 	entry->handler = NULL;
diff --git a/drivers/comparator/comparator_silabs_acmp.c b/drivers/comparator/comparator_silabs_acmp.c
new file mode 100644
index 00000000000..4cbf880d5f1
--- /dev/null
+++ b/drivers/comparator/comparator_silabs_acmp.c
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <em_device.h>
+#include <em_acmp.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/comparator.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/clock_control_silabs.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/irq.h>
+#include <zephyr/pm/device.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(silabs_acmp, CONFIG_COMPARATOR_LOG_LEVEL);
+
+#define DT_DRV_COMPAT silabs_acmp
+
+struct acmp_config {
+	ACMP_TypeDef *base;
+	const struct pinctrl_dev_config *pincfg;
+	const struct device *clock_dev;
+	const struct silabs_clock_control_cmu_config clock_cfg;
+	void (*irq_init)(void);
+	ACMP_Init_TypeDef init;
+	int input_negative;
+	int input_positive;
+};
+
+struct acmp_data {
+	uint32_t interrupt_mask;
+	comparator_callback_t callback;
+	void *user_data;
+};
+
+static int acmp_pm_action(const struct device *dev, enum pm_device_action action)
+{
+	const struct acmp_config *config = dev->config;
+	int err;
+
+	if (action == PM_DEVICE_ACTION_RESUME) {
+		err = clock_control_on(config->clock_dev,
+				       (clock_control_subsys_t)&config->clock_cfg);
+		if (err < 0 && err != -EALREADY) {
+			return err;
+		}
+
+		err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
+		if (err < 0 && err != -ENOENT) {
+			LOG_ERR("failed to allocate silabs,analog-bus via pinctrl");
+			return err;
+		}
+
+		ACMP_Enable(config->base);
+	} else if (IS_ENABLED(CONFIG_PM_DEVICE) && (action == PM_DEVICE_ACTION_SUSPEND)) {
+		ACMP_Disable(config->base);
+
+		err = clock_control_off(config->clock_dev,
+					(clock_control_subsys_t)&config->clock_cfg);
+		if (err < 0) {
+			return err;
+		}
+
+		err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_SLEEP);
+		if (err < 0 && err != -ENOENT) {
+			return err;
+		}
+	} else {
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static int acmp_init(const struct device *dev)
+{
+	int err;
+	const struct acmp_config *config = dev->config;
+
+	/* Enable ACMP Clock */
+	err = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_cfg);
+	if (err < 0) {
+		return err;
+	}
+
+	err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
+	if (err < 0 && err != -ENOENT) {
+		LOG_ERR("failed to allocate silabs,analog-bus via pinctrl");
+		return err;
+	}
+
+	/* Initialize the ACMP */
+	ACMP_Init(config->base, &config->init);
+
+	/* Configure the ACMP Input Channels */
+	ACMP_ChannelSet(config->base, config->input_negative, config->input_positive);
+
+	/* After initialization, the comparator should not yet be enabled. It was temporarily
+	 * enabled to perform input configuration since the INPUTCTRL register has the SYNC type,
+	 * disable it again here. It will be enabled by the PM resume action.
+	 */
+	ACMP_Disable(config->base);
+
+	/* Initialize the irq handler */
+	config->irq_init();
+
+	return pm_device_driver_init(dev, acmp_pm_action);
+}
+
+static int acmp_get_output(const struct device *dev)
+{
+	const struct acmp_config *config = dev->config;
+
+	return config->base->STATUS & ACMP_STATUS_ACMPOUT;
+}
+
+static int acmp_set_trigger(const struct device *dev, enum comparator_trigger trigger)
+{
+	const struct acmp_config *config = dev->config;
+	struct acmp_data *data = dev->data;
+
+	/* Disable ACMP trigger interrupts */
+	ACMP_IntDisable(config->base, ACMP_IEN_RISE | ACMP_IEN_FALL);
+
+	/* Clear ACMP trigger interrupt flags */
+	ACMP_IntClear(config->base, ACMP_IEN_RISE | ACMP_IEN_FALL);
+
+	switch (trigger) {
+	case COMPARATOR_TRIGGER_BOTH_EDGES:
+		data->interrupt_mask = ACMP_IEN_RISE | ACMP_IEN_FALL;
+		break;
+	case COMPARATOR_TRIGGER_RISING_EDGE:
+		data->interrupt_mask = ACMP_IEN_RISE;
+		break;
+	case COMPARATOR_TRIGGER_FALLING_EDGE:
+		data->interrupt_mask = ACMP_IEN_FALL;
+		break;
+	case COMPARATOR_TRIGGER_NONE:
+		data->interrupt_mask = 0;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Only enable interrupts when the trigger is not none and if a
+	 * callback is set.
+	 */
+	if (data->interrupt_mask && data->callback != NULL) {
+		ACMP_IntEnable(config->base, data->interrupt_mask);
+	}
+
+	return 0;
+}
+
+static int acmp_set_trigger_callback(const struct device *dev, comparator_callback_t callback,
+				     void *user_data)
+{
+	const struct acmp_config *config = dev->config;
+	struct acmp_data *data = dev->data;
+
+	/* Disable ACMP trigger interrupts while setting callback */
+	ACMP_IntDisable(config->base, ACMP_IEN_RISE | ACMP_IEN_FALL);
+
+	data->callback = callback;
+	data->user_data = user_data;
+
+	if (data->callback == NULL) {
+		return 0;
+	}
+
+	/* Re-enable currently set ACMP trigger interrupts */
+	if (data->interrupt_mask) {
+		ACMP_IntEnable(config->base, data->interrupt_mask);
+	}
+
+	return 0;
+}
+
+static int acmp_trigger_is_pending(const struct device *dev)
+{
+	const struct acmp_config *config = dev->config;
+	const struct acmp_data *data = dev->data;
+
+	if (ACMP_IntGet(config->base) & data->interrupt_mask) {
+		ACMP_IntClear(config->base, data->interrupt_mask);
+		return 1;
+	}
+
+	return 0;
+}
+
+static void acmp_irq_handler(const struct device *dev)
+{
+	const struct acmp_config *config = dev->config;
+	struct acmp_data *data = dev->data;
+
+	ACMP_IntClear(config->base, ACMP_IF_RISE | ACMP_IF_FALL);
+
+	if (data->callback == NULL) {
+		return;
+	}
+
+	data->callback(dev, data->user_data);
+}
+
+static DEVICE_API(comparator, acmp_api) = {
+	.get_output = acmp_get_output,
+	.set_trigger = acmp_set_trigger,
+	.set_trigger_callback = acmp_set_trigger_callback,
+	.trigger_is_pending = acmp_trigger_is_pending,
+};
+
+#define ACMP_DEVICE(inst)                                                                          \
+	PINCTRL_DT_INST_DEFINE(inst);                                                              \
+	PM_DEVICE_DT_INST_DEFINE(inst, acmp_pm_action);                                            \
+                                                                                                   \
+	static void acmp_irq_init##inst(void)                                                      \
+	{                                                                                          \
+		IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), acmp_irq_handler,     \
+			    DEVICE_DT_INST_GET(inst), 0);                                          \
+                                                                                                   \
+		irq_enable(DT_INST_IRQN(inst));                                                    \
+	}                                                                                          \
+                                                                                                   \
+	static struct acmp_data acmp_data##inst;                                                   \
+                                                                                                   \
+	static const struct acmp_config acmp_config##inst = {                                      \
+		.base = (ACMP_TypeDef *)DT_INST_REG_ADDR(inst),                                    \
+		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),                                    \
+		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)),                             \
+		.clock_cfg = SILABS_DT_INST_CLOCK_CFG(inst),                                       \
+		.irq_init = acmp_irq_init##inst,                                                   \
+		.init.biasProg = DT_INST_PROP(inst, bias),                                         \
+		.init.inputRange = DT_INST_ENUM_IDX(inst, input_range),                            \
+		.init.accuracy = DT_INST_ENUM_IDX(inst, accuracy_mode),                            \
+		.init.hysteresisLevel = DT_INST_ENUM_IDX(inst, hysteresis_mode),                   \
+		.init.inactiveValue = false,                                                       \
+		.init.vrefDiv = DT_INST_PROP(inst, vref_divider),                                  \
+		.init.enable = true,                                                               \
+		.input_negative = DT_INST_PROP(inst, input_negative),                              \
+		.input_positive = DT_INST_PROP(inst, input_positive),                              \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(inst, acmp_init, PM_DEVICE_DT_INST_GET(inst), &acmp_data##inst,      \
+			      &acmp_config##inst, POST_KERNEL, CONFIG_COMPARATOR_INIT_PRIORITY,    \
+			      &acmp_api);
+
+DT_INST_FOREACH_STATUS_OKAY(ACMP_DEVICE)
diff --git a/drivers/console/Kconfig b/drivers/console/Kconfig
index 98ae6f7f843..17e45604b43 100644
--- a/drivers/console/Kconfig
+++ b/drivers/console/Kconfig
@@ -284,6 +284,8 @@ config WINSTREAM_CONSOLE
 
 	  See the WINSTREAM Kconfig help for more information.
 
+if WINSTREAM_CONSOLE
+
 config WINSTREAM_CONSOLE_STATIC
 	bool "Use static/linkable memory for the winstream console"
 	default y if !SOC_FAMILY_INTEL_ADSP
@@ -300,4 +302,6 @@ config WINSTREAM_CONSOLE_STATIC_SIZE
 	help
 	  Size of winstream console buffer, in bytes
 
+endif # WINSTREAM_CONSOLE
+
 endif # CONSOLE
diff --git a/drivers/console/uart_mcumgr.c b/drivers/console/uart_mcumgr.c
index 2b068e6810c..b162f0bc27d 100644
--- a/drivers/console/uart_mcumgr.c
+++ b/drivers/console/uart_mcumgr.c
@@ -19,7 +19,7 @@ static const struct device *const uart_mcumgr_dev =
 	DEVICE_DT_GET(DT_CHOSEN(zephyr_uart_mcumgr));
 
 /** Callback to execute when a valid fragment has been received. */
-static uart_mcumgr_recv_fn *uart_mgumgr_recv_cb;
+static uart_mcumgr_recv_fn *uart_mcumgr_recv_cb;
 
 /** Contains the fragment currently being received. */
 static struct uart_mcumgr_rx_buf *uart_mcumgr_cur_buf;
@@ -140,7 +140,7 @@ static void uart_mcumgr_async(const struct device *dev, struct uart_event *evt,
 		for (int i = 0; i < len; i++) {
 			rx_buf = uart_mcumgr_rx_byte(p[i]);
 			if (rx_buf != NULL) {
-				uart_mgumgr_recv_cb(rx_buf);
+				uart_mcumgr_recv_cb(rx_buf);
 			}
 		}
 		break;
@@ -190,7 +190,7 @@ static void uart_mcumgr_isr(const struct device *unused, void *user_data)
 		for (i = 0; i < chunk_len; i++) {
 			rx_buf = uart_mcumgr_rx_byte(buf[i]);
 			if (rx_buf != NULL) {
-				uart_mgumgr_recv_cb(rx_buf);
+				uart_mcumgr_recv_cb(rx_buf);
 			}
 		}
 	}
@@ -239,7 +239,7 @@ static void uart_mcumgr_setup(const struct device *uart)
 
 void uart_mcumgr_register(uart_mcumgr_recv_fn *cb)
 {
-	uart_mgumgr_recv_cb = cb;
+	uart_mcumgr_recv_cb = cb;
 
 	if (device_is_ready(uart_mcumgr_dev)) {
 		uart_mcumgr_setup(uart_mcumgr_dev);
diff --git a/drivers/console/winstream_console.c b/drivers/console/winstream_console.c
index 08b0206a4d8..9a238326854 100644
--- a/drivers/console/winstream_console.c
+++ b/drivers/console/winstream_console.c
@@ -12,7 +12,7 @@
 #include <zephyr/devicetree.h>
 #include <zephyr/cache.h>
 
-#ifdef SOC_FAMILY_INTEL_ADSP
+#ifdef CONFIG_SOC_FAMILY_INTEL_ADSP
 #include <adsp_memory.h>
 #include <mem_window.h>
 #endif
@@ -95,7 +95,7 @@ static int winstream_console_init(void)
 	void *buf = NULL;
 	size_t size = 0;
 
-#ifdef SOC_FAMILY_INTEL_ADSP
+#ifdef CONFIG_SOC_FAMILY_INTEL_ADSP
 	/* These have a SOC-specific "mem_window" device.  FIXME: The
 	 * type handling is backwards here.  We shouldn't be grabbing
 	 * an arbitrary DTS alias and assuming it's a mem_window at
diff --git a/drivers/counter/CMakeLists.txt b/drivers/counter/CMakeLists.txt
index d406f7e2d62..b2c63652280 100644
--- a/drivers/counter/CMakeLists.txt
+++ b/drivers/counter/CMakeLists.txt
@@ -15,6 +15,7 @@ zephyr_library_sources_ifdef(CONFIG_COUNTER_AMBIQ               counter_ambiq_ti
 zephyr_library_sources_ifdef(CONFIG_COUNTER_GECKO_RTCC          counter_gecko_rtcc.c)
 zephyr_library_sources_ifdef(CONFIG_COUNTER_GECKO_STIMER        counter_gecko_stimer.c)
 zephyr_library_sources_ifdef(CONFIG_COUNTER_IMX_EPIT            counter_imx_epit.c)
+zephyr_library_sources_ifdef(CONFIG_COUNTER_ITE_IT8XXX2         counter_ite_it8xxx2.c)
 zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_CTIMER         counter_mcux_ctimer.c)
 zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_RTC            counter_mcux_rtc.c)
 zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_LPC_RTC        counter_mcux_lpc_rtc.c)
@@ -32,7 +33,7 @@ zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_TPM            counter_mcux_tpm
 zephyr_library_sources_ifdef(CONFIG_COUNTER_XEC                 counter_mchp_xec.c)
 zephyr_library_sources_ifdef(CONFIG_COUNTER_MCUX_LPTMR          counter_mcux_lptmr.c)
 zephyr_library_sources_ifdef(CONFIG_COUNTER_MAXIM_DS3231        maxim_ds3231.c)
-zephyr_library_sources_ifdef(CONFIG_COUNTER_NATIVE_POSIX        counter_native_posix.c)
+zephyr_library_sources_ifdef(CONFIG_COUNTER_NATIVE_SIM          counter_native_sim.c)
 zephyr_library_sources_ifdef(CONFIG_USERSPACE                   counter_handlers.c)
 zephyr_library_sources_ifdef(CONFIG_COUNTER_NXP_PIT             counter_nxp_pit.c)
 zephyr_library_sources_ifdef(CONFIG_COUNTER_XLNX_AXI_TIMER      counter_xlnx_axi_timer.c)
@@ -53,3 +54,6 @@ zephyr_library_sources_ifdef(CONFIG_COUNTER_TIMER_MAX32         counter_max32_ti
 zephyr_library_sources_ifdef(CONFIG_COUNTER_RTC_MAX32           counter_max32_rtc.c)
 zephyr_library_sources_ifdef(CONFIG_COUNTER_NXP_MRT             counter_nxp_mrt.c)
 zephyr_library_sources_ifdef(CONFIG_COUNTER_RA_AGT              counter_renesas_ra_agt.c)
+zephyr_library_sources_ifdef(CONFIG_COUNTER_RENESAS_RZ_GTM      counter_renesas_rz_gtm.c)
+zephyr_library_sources_ifdef(CONFIG_COUNTER_REALTEK_RTS5912_SLWTMR     counter_realtek_rts5912_slwtmr.c)
+zephyr_library_sources_ifdef(CONFIG_COUNTER_REALTEK_RTS5912     counter_realtek_rts5912.c)
diff --git a/drivers/counter/Kconfig b/drivers/counter/Kconfig
index 32baf8255ce..2cff7c5f51e 100644
--- a/drivers/counter/Kconfig
+++ b/drivers/counter/Kconfig
@@ -42,6 +42,8 @@ source "drivers/counter/Kconfig.nrfx"
 
 source "drivers/counter/Kconfig.imx_epit"
 
+source "drivers/counter/Kconfig.ite_it8xxx2"
+
 source "drivers/counter/Kconfig.stm32_rtc"
 
 source "drivers/counter/Kconfig.stm32_timer"
@@ -68,7 +70,7 @@ source "drivers/counter/Kconfig.mcux_lptmr"
 
 source "drivers/counter/Kconfig.maxim_ds3231"
 
-source "drivers/counter/Kconfig.native_posix"
+source "drivers/counter/Kconfig.native_sim"
 
 source "drivers/counter/Kconfig.nxp_pit"
 
@@ -104,4 +106,10 @@ source "drivers/counter/Kconfig.nxp_mrt"
 
 source "drivers/counter/Kconfig.renesas_ra"
 
+source "drivers/counter/Kconfig.renesas_rz"
+
+source "drivers/counter/Kconfig.rts5912_slwtmr"
+
+source "drivers/counter/Kconfig.rts5912"
+
 endif # COUNTER
diff --git a/drivers/counter/Kconfig.ite_it8xxx2 b/drivers/counter/Kconfig.ite_it8xxx2
new file mode 100644
index 00000000000..a1f34da4ccf
--- /dev/null
+++ b/drivers/counter/Kconfig.ite_it8xxx2
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config COUNTER_ITE_IT8XXX2
+	bool "ITE IT8XXX2 Timer driver"
+	default y
+	depends on DT_HAS_ITE_IT8XXX2_COUNTER_ENABLED
+	help
+	  Enable counter support for the ITE IT8XXX2.
diff --git a/drivers/counter/Kconfig.mcux_lptmr b/drivers/counter/Kconfig.mcux_lptmr
index af961c790e1..11f387eef3c 100644
--- a/drivers/counter/Kconfig.mcux_lptmr
+++ b/drivers/counter/Kconfig.mcux_lptmr
@@ -6,17 +6,6 @@
 config COUNTER_MCUX_LPTMR
 	bool "MCUX LPTMR driver"
 	default y
-	depends on DT_HAS_NXP_LPTMR_ENABLED || \
-		   COUNTER_MCUX_KINETIS_LPTMR
+	depends on DT_HAS_NXP_LPTMR_ENABLED
 	help
 	  Enable support for the MCUX Low Power Timer (LPTMR).
-
-config COUNTER_MCUX_KINETIS_LPTMR
-	bool
-	default y
-	depends on DT_HAS_NXP_KINETIS_LPTMR_ENABLED
-	select DEPRECATED
-	help
-	  The compatible string "nxp,kinetis-lptmr" should
-	  be swiched to "nxp,lptmr" in DT. The former will
-	  be removed eventually.
diff --git a/drivers/counter/Kconfig.native_posix b/drivers/counter/Kconfig.native_posix
deleted file mode 100644
index a342ed07a30..00000000000
--- a/drivers/counter/Kconfig.native_posix
+++ /dev/null
@@ -1,17 +0,0 @@
-# Copyright (c) 2020, Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-config COUNTER_NATIVE_POSIX
-	bool "Counter on COUNTER_0"
-	default y
-	depends on DT_HAS_ZEPHYR_NATIVE_POSIX_COUNTER_ENABLED
-
-config COUNTER_NATIVE_POSIX_FREQUENCY
-	int "native_posix counter frequency in Hz"
-	default 1000
-	depends on COUNTER_NATIVE_POSIX
-
-config COUNTER_NATIVE_POSIX_NBR_CHANNELS
-	int "native counter, number of channels"
-	default 4
-	depends on COUNTER_NATIVE_POSIX
diff --git a/drivers/counter/Kconfig.native_sim b/drivers/counter/Kconfig.native_sim
new file mode 100644
index 00000000000..cc5a7148190
--- /dev/null
+++ b/drivers/counter/Kconfig.native_sim
@@ -0,0 +1,29 @@
+# Copyright (c) 2020, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config COUNTER_NATIVE_SIM
+	bool "Counter on COUNTER_0"
+	default y
+	depends on (DT_HAS_ZEPHYR_NATIVE_SIM_COUNTER_ENABLED || DT_HAS_ZEPHYR_NATIVE_POSIX_COUNTER_ENABLED)
+
+config COUNTER_NATIVE_SIM_FREQUENCY
+	int "native_sim counter frequency in Hz"
+	default COUNTER_NATIVE_POSIX_FREQUENCY
+	depends on COUNTER_NATIVE_SIM
+
+config COUNTER_NATIVE_SIM_NBR_CHANNELS
+	int "native_sim counter: number of channels"
+	default COUNTER_NATIVE_POSIX_NBR_CHANNELS
+	depends on COUNTER_NATIVE_SIM
+
+config COUNTER_NATIVE_POSIX
+	bool "Counter on COUNTER_0 (deprecated)"
+	select DEPRECATED
+
+config COUNTER_NATIVE_POSIX_FREQUENCY
+	int "native_posix counter frequency in Hz (deprecated)"
+	default 1000
+
+config COUNTER_NATIVE_POSIX_NBR_CHANNELS
+	int "native counter, number of channels (deprecated)"
+	default 4
diff --git a/drivers/counter/Kconfig.renesas_rz b/drivers/counter/Kconfig.renesas_rz
new file mode 100644
index 00000000000..4be934e33a9
--- /dev/null
+++ b/drivers/counter/Kconfig.renesas_rz
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config COUNTER_RENESAS_RZ_GTM
+	bool "Renesas RZ General Timer (GTM) Counter driver"
+	default y
+	depends on DT_HAS_RENESAS_RZ_GTM_COUNTER_ENABLED
+	select USE_RZ_FSP_GTM
+	help
+	  Enable the counter driver for the Renesas RZ General Timer (GTM).
diff --git a/drivers/counter/Kconfig.rts5912 b/drivers/counter/Kconfig.rts5912
new file mode 100644
index 00000000000..da025e96450
--- /dev/null
+++ b/drivers/counter/Kconfig.rts5912
@@ -0,0 +1,12 @@
+# Realtek counter configuration options
+
+# Copyright (c) 2025 Realtek Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config COUNTER_REALTEK_RTS5912
+	bool "Realtek rts5912 series counter driver"
+	default y
+	depends on DT_HAS_REALTEK_RTS5912_TIMER_ENABLED
+	help
+	  Enable counter driver for Realtek RTS5912 MCU series. Such driver
+	  will expose the basic timer devices present on the MCU.
diff --git a/drivers/counter/Kconfig.rts5912_slwtmr b/drivers/counter/Kconfig.rts5912_slwtmr
new file mode 100644
index 00000000000..47b6ab72f1b
--- /dev/null
+++ b/drivers/counter/Kconfig.rts5912_slwtmr
@@ -0,0 +1,12 @@
+# Realtek counter configuration options
+
+# Copyright (c) 2025 Realtek Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config COUNTER_REALTEK_RTS5912_SLWTMR
+	bool "Realtek rts5912 series slow timer counter driver"
+	default y
+	depends on DT_HAS_REALTEK_RTS5912_SLWTIMER_ENABLED
+	help
+	  Enable counter driver for Realtek RTS5912 MCU series. Such driver
+	  will expose the slow timer devices present on the MCU.
diff --git a/drivers/counter/Kconfig.stm32_rtc b/drivers/counter/Kconfig.stm32_rtc
index 6bab7a93e76..e7c7c1bea97 100644
--- a/drivers/counter/Kconfig.stm32_rtc
+++ b/drivers/counter/Kconfig.stm32_rtc
@@ -7,10 +7,8 @@ menuconfig COUNTER_RTC_STM32
 	bool "STM32 Counter RTC driver"
 	default y if !RTC
 	depends on DT_HAS_ST_STM32_RTC_ENABLED
+	depends on !SOC_SERIES_STM32WB0X
 	select USE_STM32_LL_RTC
-	select USE_STM32_LL_PWR
-	select USE_STM32_LL_RCC
-	select USE_STM32_LL_EXTI
 	help
 	  Build RTC driver for STM32 SoCs.
 	  Tested on STM32 C0, F0, F2, F3, F4, F7, G0, G4, H7, L1, L4, L5, U5 series
diff --git a/drivers/counter/counter_ambiq_timer.c b/drivers/counter/counter_ambiq_timer.c
index 2b3459ec5e9..b9323c5f5a3 100644
--- a/drivers/counter/counter_ambiq_timer.c
+++ b/drivers/counter/counter_ambiq_timer.c
@@ -12,7 +12,7 @@
 #include <zephyr/device.h>
 #include <zephyr/logging/log.h>
 /* ambiq-sdk includes */
-#include <am_mcu_apollo.h>
+#include <soc.h>
 
 LOG_MODULE_REGISTER(ambiq_counter, CONFIG_COUNTER_LOG_LEVEL);
 
diff --git a/drivers/counter/counter_esp32_rtc.c b/drivers/counter/counter_esp32_rtc.c
index ebbdd207541..bf751f64414 100644
--- a/drivers/counter/counter_esp32_rtc.c
+++ b/drivers/counter/counter_esp32_rtc.c
@@ -1,15 +1,11 @@
 /*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2022-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #define DT_DRV_COMPAT espressif_esp32_rtc_timer
 
-/*
- * Include esp-idf headers first to avoid
- * redefining BIT() macro
- */
 #include "soc/rtc_cntl_reg.h"
 #include "soc/rtc.h"
 #include <esp_rom_sys.h>
@@ -21,22 +17,11 @@
 #include <zephyr/kernel.h>
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/drivers/clock_control/esp32_clock_control.h>
-
-#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3)
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-#else
 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
-#endif
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(esp32_counter_rtc, CONFIG_COUNTER_LOG_LEVEL);
 
-#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3)
-#define ESP32_COUNTER_RTC_ISR_HANDLER isr_handler_t
-#else
-#define ESP32_COUNTER_RTC_ISR_HANDLER intr_handler_t
-#endif
-
 static void counter_esp32_isr(void *arg);
 
 struct counter_esp32_config {
@@ -65,9 +50,10 @@ static int counter_esp32_init(const struct device *dev)
 			       &data->clk_src_freq);
 
 	flags = ESP_PRIO_TO_FLAGS(cfg->irq_priority) | ESP_INT_FLAGS_CHECK(cfg->irq_flags) |
-		ESP_INTR_FLAG_SHARED;
+			     ESP_INTR_FLAG_SHARED;
+
 	ret = esp_intr_alloc(cfg->irq_source, flags,
-			     (ESP32_COUNTER_RTC_ISR_HANDLER)counter_esp32_isr, (void *)dev, NULL);
+			     (intr_handler_t)counter_esp32_isr, (void *)dev, NULL);
 
 	if (ret != 0) {
 		LOG_ERR("could not allocate interrupt (err %d)", ret);
@@ -246,6 +232,6 @@ DEVICE_DT_INST_DEFINE(0,
 		      NULL,
 		      &counter_data,
 		      &counter_config,
-		      POST_KERNEL,
+		      PRE_KERNEL_2,
 		      CONFIG_COUNTER_INIT_PRIORITY,
 		      &rtc_timer_esp32_api);
diff --git a/drivers/counter/counter_esp32_tmr.c b/drivers/counter/counter_esp32_tmr.c
index 3131b45a42b..45143dc51dc 100644
--- a/drivers/counter/counter_esp32_tmr.c
+++ b/drivers/counter/counter_esp32_tmr.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -14,22 +14,12 @@
 #include <zephyr/drivers/counter.h>
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/kernel.h>
-#if defined(CONFIG_RISCV)
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-#else
 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
-#endif
 #include <zephyr/device.h>
 #include <zephyr/logging/log.h>
 
 LOG_MODULE_REGISTER(esp32_counter, CONFIG_COUNTER_LOG_LEVEL);
 
-#if defined(CONFIG_RISCV)
-#define ISR_HANDLER isr_handler_t
-#else
-#define ISR_HANDLER intr_handler_t
-#endif
-
 static void counter_esp32_isr(void *arg);
 
 typedef bool (*timer_isr_t)(void *);
@@ -97,7 +87,7 @@ static int counter_esp32_init(const struct device *dev)
 	int ret = esp_intr_alloc(cfg->irq_source,
 				 ESP_PRIO_TO_FLAGS(cfg->irq_priority) |
 					 ESP_INT_FLAGS_CHECK(cfg->irq_flags),
-				 (ISR_HANDLER)counter_esp32_isr, (void *)dev, NULL);
+				 (intr_handler_t)counter_esp32_isr, (void *)dev, NULL);
 
 	if (ret != 0) {
 		LOG_ERR("could not allocate interrupt (err %d)", ret);
diff --git a/drivers/counter/counter_ite_it8xxx2.c b/drivers/counter/counter_ite_it8xxx2.c
new file mode 100644
index 00000000000..cbd34a605ff
--- /dev/null
+++ b/drivers/counter/counter_ite_it8xxx2.c
@@ -0,0 +1,334 @@
+/*
+ * Copyright (c) 2025 ITE Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ite_it8xxx2_counter
+
+#include <soc.h>
+#include <zephyr/drivers/counter.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(counter_it8xxx2, CONFIG_COUNTER_LOG_LEVEL);
+
+/* IT8XXX2 Timer registers offsets */
+#define ET7CTRL   0x00
+#define ET7PSR    0x01
+#define ET7CNTLLR 0x04
+#define ET8CTRL   0x08
+#define ET8PSR    0x09
+#define ET8CNTLLR 0x0C
+#define ET7CNTOLR 0x28
+#define ET8CNTOLR 0x2C
+
+/* ETnCTLR bit definitions (for n = 7 ~ 8) */
+#define ET_COMB BIT(3) /* only defined in ET7CTRL */
+#define ET_TC   BIT(2)
+#define ET_RST  BIT(1)
+#define ET_EN   BIT(0)
+
+/* ETnPSR bit definitions (for n = 7 ~ 8) */
+#define ETnPSR_32768HZ 0x00
+
+struct counter_it8xxx2_config {
+	struct counter_config_info info;
+	mm_reg_t base;
+	/* alarm timer irq */
+	int alarm_irq;
+	/* top timer irq */
+	int top_irq;
+	void (*irq_config_func)(const struct device *dev);
+};
+
+struct counter_it8xxx2_data {
+	counter_top_callback_t top_callback;
+	void *top_user_data;
+	counter_alarm_callback_t alarm_callback;
+	void *alarm_user_data;
+};
+
+static inline uint32_t counter_it8xxx2_read8(const struct device *dev, mm_reg_t offset)
+{
+	const struct counter_it8xxx2_config *config = dev->config;
+
+	return sys_read8(config->base + offset);
+}
+
+static inline uint32_t counter_it8xxx2_read32(const struct device *dev, mm_reg_t offset)
+{
+	const struct counter_it8xxx2_config *config = dev->config;
+
+	return sys_read32(config->base + offset);
+}
+
+static inline void counter_it8xxx2_write8(const struct device *dev, uint32_t value, mm_reg_t offset)
+{
+	const struct counter_it8xxx2_config *config = dev->config;
+
+	sys_write8(value, config->base + offset);
+}
+
+static inline void counter_it8xxx2_write32(const struct device *dev, uint32_t value,
+					   mm_reg_t offset)
+{
+	const struct counter_it8xxx2_config *config = dev->config;
+
+	sys_write32(value, config->base + offset);
+}
+
+static inline void counter_it8xxx2_alarm_timer_disable(const struct device *dev)
+{
+	const struct counter_it8xxx2_config *config = dev->config;
+
+	irq_disable(config->alarm_irq);
+	counter_it8xxx2_write8(dev, counter_it8xxx2_read8(dev, ET7CTRL) & ~ET_EN, ET7CTRL);
+	ite_intc_isr_clear(config->alarm_irq);
+}
+
+static int counter_it8xxx2_start(const struct device *dev)
+{
+	LOG_DBG("starting top timer");
+
+	counter_it8xxx2_write8(dev, ET_EN | ET_RST, ET8CTRL);
+
+	return 0;
+}
+
+static int counter_it8xxx2_stop(const struct device *dev)
+{
+	LOG_DBG("stopping timer");
+
+	counter_it8xxx2_write8(dev, counter_it8xxx2_read8(dev, ET8CTRL) & ~ET_EN, ET8CTRL);
+
+	return 0;
+}
+
+static int counter_it8xxx2_get_value(const struct device *dev, uint32_t *ticks)
+{
+	*ticks = counter_it8xxx2_read32(dev, ET8CNTOLR);
+
+	return 0;
+}
+
+static int counter_it8xxx2_set_alarm(const struct device *dev, uint8_t chan_id,
+				     const struct counter_alarm_cfg *alarm_cfg)
+{
+	const struct counter_it8xxx2_config *config = dev->config;
+	struct counter_it8xxx2_data *data = dev->data;
+
+	ARG_UNUSED(chan_id);
+
+	/* Interrupts are only triggered when the counter reaches 0.
+	 * So only relative alarms are supported.
+	 */
+	if (alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) {
+		return -ENOTSUP;
+	}
+
+	if (data->alarm_callback != NULL) {
+		return -EBUSY;
+	}
+
+	if (alarm_cfg->callback == NULL) {
+		return -EINVAL;
+	}
+
+	if (alarm_cfg->ticks > counter_it8xxx2_read32(dev, ET8CNTLLR)) {
+		return -EINVAL;
+	}
+
+	LOG_DBG("triggering alarm in 0x%08x ticks", alarm_cfg->ticks);
+
+	irq_disable(config->alarm_irq);
+
+	counter_it8xxx2_write32(dev, alarm_cfg->ticks, ET7CNTLLR);
+
+	data->alarm_callback = alarm_cfg->callback;
+	data->alarm_user_data = alarm_cfg->user_data;
+
+	LOG_DBG("%p Counter alarm set to %u ticks", dev, alarm_cfg->ticks);
+
+	counter_it8xxx2_write8(dev, counter_it8xxx2_read8(dev, ET7CTRL) | ET_EN | ET_RST, ET7CTRL);
+
+	ite_intc_isr_clear(config->alarm_irq);
+
+	irq_enable(config->alarm_irq);
+
+	return 0;
+}
+
+static int counter_it8xxx2_cancel_alarm(const struct device *dev, uint8_t chan_id)
+{
+	struct counter_it8xxx2_data *data = dev->data;
+
+	if (chan_id != 0) {
+		LOG_ERR("Invalid channel id %u", chan_id);
+		return -ENOTSUP;
+	}
+
+	counter_it8xxx2_alarm_timer_disable(dev);
+
+	data->alarm_callback = NULL;
+	data->alarm_user_data = NULL;
+
+	LOG_DBG("%p Counter alarm canceled", dev);
+
+	return 0;
+}
+
+static int counter_it8xxx2_set_top_value(const struct device *dev,
+					 const struct counter_top_cfg *top_cfg)
+{
+	const struct counter_it8xxx2_config *config = dev->config;
+	struct counter_it8xxx2_data *data = dev->data;
+
+	if (top_cfg == NULL) {
+		LOG_ERR("Invalid top value configuration");
+		return -EINVAL;
+	}
+
+	if (top_cfg->ticks == 0) {
+		return -EINVAL;
+	}
+
+	if (top_cfg->ticks > config->info.max_top_value) {
+		return -ENOTSUP;
+	}
+
+	if (data->alarm_callback) {
+		return -EBUSY;
+	}
+
+	/* top value cannot be updated without reset */
+	if (top_cfg->flags & COUNTER_TOP_CFG_DONT_RESET) {
+		LOG_ERR("Updating top value without reset is not supported");
+		return -ENOTSUP;
+	}
+
+	LOG_DBG("setting top value to 0x%08x", top_cfg->ticks);
+
+	data->top_callback = top_cfg->callback;
+	data->top_user_data = top_cfg->user_data;
+
+	irq_disable(config->top_irq);
+
+	/* set new top value */
+	counter_it8xxx2_write32(dev, top_cfg->ticks, ET8CNTLLR);
+
+	/* re-enable and reset timer */
+	counter_it8xxx2_write8(dev, counter_it8xxx2_read8(dev, ET8CTRL) | ET_EN | ET_RST, ET8CTRL);
+
+	ite_intc_isr_clear(config->top_irq);
+
+	irq_enable(config->top_irq);
+
+	return 0;
+}
+
+static uint32_t counter_it8xxx2_get_top_value(const struct device *dev)
+{
+	return counter_it8xxx2_read32(dev, ET8CNTLLR);
+}
+
+static void counter_it8xxx2_alarm_isr(const struct device *dev)
+{
+	struct counter_it8xxx2_data *data = dev->data;
+	counter_alarm_callback_t alarm_cb;
+	void *user_data;
+	uint32_t ticks;
+
+	LOG_DBG("%p alarm timer ISR", dev);
+
+	/* Alarm is one-shot, so disable interrupt and callback */
+	if (data->alarm_callback) {
+		alarm_cb = data->alarm_callback;
+		data->alarm_callback = NULL;
+		user_data = data->alarm_user_data;
+
+		ticks = counter_it8xxx2_read32(dev, ET8CNTOLR);
+
+		alarm_cb(dev, 0, ticks, user_data);
+	}
+
+	counter_it8xxx2_alarm_timer_disable(dev);
+}
+
+static void counter_it8xxx2_top_isr(const struct device *dev)
+{
+	const struct counter_it8xxx2_config *config = dev->config;
+	struct counter_it8xxx2_data *data = dev->data;
+
+	LOG_DBG("%p top timer ISR", dev);
+
+	if (data->top_callback) {
+		data->top_callback(dev, data->top_user_data);
+	}
+
+	/* read clear timer 8 terminal count */
+	counter_it8xxx2_read8(dev, ET8CTRL);
+
+	ite_intc_isr_clear(config->top_irq);
+}
+
+static int counter_it8xxx2_init(const struct device *dev)
+{
+	const struct counter_it8xxx2_config *config = dev->config;
+
+	LOG_DBG("max top value = 0x%08x", config->info.max_top_value);
+	LOG_DBG("frequency = %d", config->info.freq);
+	LOG_DBG("channels = %d", config->info.channels);
+
+	/* set the top value of top timer  */
+	counter_it8xxx2_write32(dev, config->info.max_top_value, ET8CNTLLR);
+
+	/* set the frequencies of alarm timer and top timer */
+	counter_it8xxx2_write8(dev, ETnPSR_32768HZ, ET7PSR);
+	counter_it8xxx2_write8(dev, ETnPSR_32768HZ, ET8PSR);
+
+	config->irq_config_func(dev);
+
+	return 0;
+}
+
+static DEVICE_API(counter, counter_it8xxx2_driver_api) = {
+	.start = counter_it8xxx2_start,
+	.stop = counter_it8xxx2_stop,
+	.get_value = counter_it8xxx2_get_value,
+	.set_alarm = counter_it8xxx2_set_alarm,
+	.cancel_alarm = counter_it8xxx2_cancel_alarm,
+	.set_top_value = counter_it8xxx2_set_top_value,
+	.get_top_value = counter_it8xxx2_get_top_value,
+};
+
+#define COUNTER_IT8XXX2_INIT(n)                                                                    \
+	static void counter_it8xxx2_cfg_func_##n(const struct device *dev)                         \
+	{                                                                                          \
+		IRQ_CONNECT(DT_INST_IRQN_BY_IDX(n, 0), 0, counter_it8xxx2_alarm_isr,               \
+			    DEVICE_DT_INST_GET(n), 0);                                             \
+		IRQ_CONNECT(DT_INST_IRQN_BY_IDX(n, 1), 0, counter_it8xxx2_top_isr,                 \
+			    DEVICE_DT_INST_GET(n), 0);                                             \
+	}                                                                                          \
+                                                                                                   \
+	static struct counter_it8xxx2_config counter_it8xxx2_config_##n = {                        \
+		.info =                                                                            \
+			{                                                                          \
+				.max_top_value = UINT32_MAX,                                       \
+				.freq = 32768,                                                     \
+				.flags = 0,                                                        \
+				.channels = 1,                                                     \
+			},                                                                         \
+		.base = DT_INST_REG_ADDR(n),                                                       \
+		.alarm_irq = DT_INST_IRQN_BY_IDX(n, 0),                                            \
+		.top_irq = DT_INST_IRQN_BY_IDX(n, 1),                                              \
+		.irq_config_func = counter_it8xxx2_cfg_func_##n,                                   \
+	};                                                                                         \
+                                                                                                   \
+	static struct counter_it8xxx2_data counter_it8xxx2_data_##n;                               \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, &counter_it8xxx2_init, NULL, &counter_it8xxx2_data_##n,           \
+			      &counter_it8xxx2_config_##n, POST_KERNEL,                            \
+			      CONFIG_COUNTER_INIT_PRIORITY, &counter_it8xxx2_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(COUNTER_IT8XXX2_INIT)
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
+	     "only one ite,it8xxx2-counter compatible node can be supported");
diff --git a/drivers/counter/counter_ll_stm32_timer.c b/drivers/counter/counter_ll_stm32_timer.c
index dab9d4b167f..c7a6216ac66 100644
--- a/drivers/counter/counter_ll_stm32_timer.c
+++ b/drivers/counter/counter_ll_stm32_timer.c
@@ -383,7 +383,10 @@ static int counter_stm32_get_tim_clk(const struct stm32_pclken *pclken, uint32_t
 		return r;
 	}
 
-#if defined(CONFIG_SOC_SERIES_STM32H7X)
+#if defined(CONFIG_SOC_SERIES_STM32WB0X)
+	/* Timers are clocked by SYSCLK on STM32WB0 */
+	apb_psc = 1;
+#elif defined(CONFIG_SOC_SERIES_STM32H7X)
 	if (pclken->bus == STM32_CLOCK_BUS_APB1) {
 		apb_psc = STM32_D2PPRE1;
 	} else {
diff --git a/drivers/counter/counter_max32_rtc.c b/drivers/counter/counter_max32_rtc.c
index 74e5c86f3b6..832a1394508 100644
--- a/drivers/counter/counter_max32_rtc.c
+++ b/drivers/counter/counter_max32_rtc.c
@@ -38,11 +38,6 @@ struct max32_rtc_config {
 
 static int api_start(const struct device *dev)
 {
-	/* Ensure that both sec and subsec are reset to 0 */
-	while (MXC_RTC_Init(0, 0) == E_BUSY) {
-		;
-	}
-
 	while (MXC_RTC_Start() == E_BUSY) {
 		;
 	}
diff --git a/drivers/counter/counter_mcux_gpt.c b/drivers/counter/counter_mcux_gpt.c
index 3ea46c5b3a2..c0e714ea41d 100644
--- a/drivers/counter/counter_mcux_gpt.c
+++ b/drivers/counter/counter_mcux_gpt.c
@@ -28,6 +28,7 @@ struct mcux_gpt_config {
 	const struct device *clock_dev;
 	clock_control_subsys_t clock_subsys;
 	clock_name_t clock_source;
+	void (*irq_config_func)(void);
 };
 
 struct mcux_gpt_data {
@@ -210,6 +211,8 @@ static int mcux_gpt_init(const struct device *dev)
 	base = get_base(dev);
 	GPT_Init(base, &gptConfig);
 
+	config->irq_config_func();
+
 	return 0;
 }
 
@@ -226,6 +229,7 @@ static DEVICE_API(counter, mcux_gpt_driver_api) = {
 
 #define GPT_DEVICE_INIT_MCUX(n)						\
 	static struct mcux_gpt_data mcux_gpt_data_ ## n;		\
+	static void mcux_gpt_irq_config_ ## n(void);			\
 									\
 	static const struct mcux_gpt_config mcux_gpt_config_ ## n = {	\
 		DEVICE_MMIO_NAMED_ROM_INIT(gpt_mmio, DT_DRV_INST(n)),	\
@@ -238,11 +242,11 @@ static DEVICE_API(counter, mcux_gpt_driver_api) = {
 			.channels = 1,					\
 			.flags = COUNTER_CONFIG_INFO_COUNT_UP,		\
 		},							\
+		.irq_config_func = mcux_gpt_irq_config_ ## n,		\
 	};								\
 									\
-	static int mcux_gpt_## n ##_init(const struct device *dev);	\
 	DEVICE_DT_INST_DEFINE(n,					\
-			    mcux_gpt_## n ##_init,			\
+			    mcux_gpt_init,				\
 			    NULL,					\
 			    &mcux_gpt_data_ ## n,			\
 			    &mcux_gpt_config_ ## n,			\
@@ -250,13 +254,12 @@ static DEVICE_API(counter, mcux_gpt_driver_api) = {
 			    CONFIG_COUNTER_INIT_PRIORITY,		\
 			    &mcux_gpt_driver_api);			\
 									\
-	static int mcux_gpt_## n ##_init(const struct device *dev)	\
+	static void mcux_gpt_irq_config_ ## n(void)			\
 	{								\
 		IRQ_CONNECT(DT_INST_IRQN(n),				\
 			    DT_INST_IRQ(n, priority),			\
 			    mcux_gpt_isr, DEVICE_DT_INST_GET(n), 0);	\
 		irq_enable(DT_INST_IRQN(n));				\
-		return mcux_gpt_init(dev);				\
 	}								\
 
 DT_INST_FOREACH_STATUS_OKAY(GPT_DEVICE_INIT_MCUX)
diff --git a/drivers/counter/counter_mcux_lptmr.c b/drivers/counter/counter_mcux_lptmr.c
index de78cc896dc..3f55a8601d3 100644
--- a/drivers/counter/counter_mcux_lptmr.c
+++ b/drivers/counter/counter_mcux_lptmr.c
@@ -4,14 +4,10 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/devicetree.h>
-#include <zephyr/sys/util.h>
-#if DT_HAS_COMPAT_STATUS_OKAY(nxp_kinetis_lptmr)
-#define DT_DRV_COMPAT nxp_kinetis_lptmr
-#else
 #define DT_DRV_COMPAT nxp_lptmr
-#endif
 
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/util.h>
 #include <zephyr/drivers/counter.h>
 #include <zephyr/irq.h>
 #include <fsl_lptmr.h>
diff --git a/drivers/counter/counter_mcux_rtc.c b/drivers/counter/counter_mcux_rtc.c
index f72fa689f33..eb0d964a96d 100644
--- a/drivers/counter/counter_mcux_rtc.c
+++ b/drivers/counter/counter_mcux_rtc.c
@@ -14,6 +14,16 @@
 #include <fsl_rtc.h>
 #include <zephyr/logging/log.h>
 
+/*
+ * FSL_FEATURE_* is defined with paranethesis
+ * which is not acceptable when using the IS_ENABLED() macro
+ */
+#if (defined(FSL_FEATURE_RTC_HAS_LPO_ADJUST) && FSL_FEATURE_RTC_HAS_LPO_ADJUST)
+#define NXP_RTC_HAS_LPO_ADJUST 1
+#else
+#define NXP_RTC_HAS_LPO_ADJUST 0
+#endif
+
 LOG_MODULE_REGISTER(mcux_rtc, CONFIG_COUNTER_LOG_LEVEL);
 
 struct mcux_rtc_data {
@@ -241,9 +251,10 @@ static int mcux_rtc_init(const struct device *dev)
 	 * "LPO": 1
 	 */
 	BUILD_ASSERT((((DT_INST_ENUM_IDX(0, clock_source) == 1) &&
-		FSL_FEATURE_RTC_HAS_LPO_ADJUST) ||
+		NXP_RTC_HAS_LPO_ADJUST) ||
 		DT_INST_ENUM_IDX(0, clock_source) == 0),
 		"Cannot choose the LPO clock for that instance of the RTC");
+
 #if (defined(FSL_FEATURE_RTC_HAS_LPO_ADJUST) && FSL_FEATURE_RTC_HAS_LPO_ADJUST)
 	/* The RTC prescaler increments using the LPO 1 kHz clock
 	 * instead of the RTC clock
diff --git a/drivers/counter/counter_mcux_tpm.c b/drivers/counter/counter_mcux_tpm.c
index 51b0d95aec1..059b057ada2 100644
--- a/drivers/counter/counter_mcux_tpm.c
+++ b/drivers/counter/counter_mcux_tpm.c
@@ -28,6 +28,7 @@ struct mcux_tpm_config {
 
 	tpm_clock_source_t tpm_clock_source;
 	tpm_clock_prescale_t prescale;
+	void (*irq_config_func)(void);
 };
 
 struct mcux_tpm_data {
@@ -248,6 +249,8 @@ static int mcux_tpm_init(const struct device *dev)
 	/* Set the modulo to max value. */
 	base->MOD = TPM_MAX_COUNTER_VALUE(base);
 
+	config->irq_config_func();
+
 	return 0;
 }
 
@@ -267,6 +270,7 @@ static DEVICE_API(counter, mcux_tpm_driver_api) = {
 
 #define TPM_DEVICE_INIT_MCUX(n)							\
 	static struct mcux_tpm_data mcux_tpm_data_ ## n;			\
+	static void mcux_tpm_irq_config_ ## n(void);				\
 										\
 	static const struct mcux_tpm_config mcux_tpm_config_ ## n = {		\
 		DEVICE_MMIO_NAMED_ROM_INIT(tpm_mmio, DT_DRV_INST(n)),		\
@@ -281,11 +285,11 @@ static DEVICE_API(counter, mcux_tpm_driver_api) = {
 			.channels = 1,						\
 			.flags = COUNTER_CONFIG_INFO_COUNT_UP,			\
 		},								\
+		.irq_config_func = mcux_tpm_irq_config_ ## n,			\
 	};									\
 										\
-	static int mcux_tpm_## n ##_init(const struct device *dev);		\
 	DEVICE_DT_INST_DEFINE(n,						\
-			mcux_tpm_## n ##_init,					\
+			mcux_tpm_init,						\
 			NULL,							\
 			&mcux_tpm_data_ ## n,					\
 			&mcux_tpm_config_ ## n,					\
@@ -293,13 +297,12 @@ static DEVICE_API(counter, mcux_tpm_driver_api) = {
 			CONFIG_COUNTER_INIT_PRIORITY,				\
 			&mcux_tpm_driver_api);					\
 										\
-	static int mcux_tpm_## n ##_init(const struct device *dev)		\
+	static void mcux_tpm_irq_config_ ## n(void)				\
 	{									\
 		IRQ_CONNECT(DT_INST_IRQN(n),					\
 			DT_INST_IRQ(n, priority),				\
 			mcux_tpm_isr, DEVICE_DT_INST_GET(n), 0);		\
 		irq_enable(DT_INST_IRQN(n));					\
-		return mcux_tpm_init(dev);					\
 	}									\
 
 DT_INST_FOREACH_STATUS_OKAY(TPM_DEVICE_INIT_MCUX)
diff --git a/drivers/counter/counter_native_posix.c b/drivers/counter/counter_native_posix.c
deleted file mode 100644
index 949a08a9f99..00000000000
--- a/drivers/counter/counter_native_posix.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- * Copyright (c) 2020, Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DT_DRV_COMPAT zephyr_native_posix_counter
-
-#include <string.h>
-#include <zephyr/device.h>
-#include <zephyr/drivers/counter.h>
-#include <zephyr/irq.h>
-#include <soc.h>
-#include <hw_counter.h>
-#include <limits.h>
-
-#define DRIVER_CONFIG_INFO_FLAGS (COUNTER_CONFIG_INFO_COUNT_UP)
-#define DRIVER_CONFIG_INFO_CHANNELS CONFIG_COUNTER_NATIVE_POSIX_NBR_CHANNELS
-#define COUNTER_NATIVE_POSIX_IRQ_FLAGS (0)
-#define COUNTER_NATIVE_POSIX_IRQ_PRIORITY (2)
-
-#define COUNTER_PERIOD (USEC_PER_SEC / CONFIG_COUNTER_NATIVE_POSIX_FREQUENCY)
-#define TOP_VALUE (UINT_MAX)
-
-static struct counter_alarm_cfg pending_alarm[DRIVER_CONFIG_INFO_CHANNELS];
-static bool is_alarm_pending[DRIVER_CONFIG_INFO_CHANNELS];
-static struct counter_top_cfg top;
-static bool is_top_set;
-static const struct device *device;
-
-static void schedule_next_isr(void)
-{
-	int64_t current_value = hw_counter_get_value();
-	uint32_t next_time = top.ticks; /* top.ticks is TOP_VALUE if is_top_set == false */
-
-	if (current_value == top.ticks) {
-		current_value = -1;
-	}
-
-	for (int i = 0; i < DRIVER_CONFIG_INFO_CHANNELS; i++) {
-		if (is_alarm_pending[i]) {
-			if (pending_alarm[i].ticks > current_value) {
-				/* If the alarm is not after a wrap */
-				next_time = MIN(pending_alarm[i].ticks, next_time);
-			}
-		}
-	}
-
-	/* We will at least get an interrupt at top.ticks even if is_top_set == false,
-	 * which is fine. We may use that to set the next alarm if needed
-	 */
-	hw_counter_set_target(next_time);
-}
-
-static void counter_isr(const void *arg)
-{
-	ARG_UNUSED(arg);
-	uint32_t current_value = hw_counter_get_value();
-
-	for (int i = 0; i < DRIVER_CONFIG_INFO_CHANNELS; i++) {
-		if (is_alarm_pending[i] && (current_value == pending_alarm[i].ticks)) {
-			is_alarm_pending[i] = false;
-			if (pending_alarm[i].callback) {
-				pending_alarm[i].callback(device, i, current_value,
-							  pending_alarm[i].user_data);
-			}
-		}
-	}
-
-	if (is_top_set && (current_value == top.ticks)) {
-		if (top.callback) {
-			top.callback(device, top.user_data);
-		}
-	}
-
-	schedule_next_isr();
-}
-
-static int ctr_init(const struct device *dev)
-{
-	device = dev;
-	memset(is_alarm_pending, 0, sizeof(is_alarm_pending));
-	is_top_set = false;
-	top.ticks = TOP_VALUE;
-
-	IRQ_CONNECT(COUNTER_EVENT_IRQ, COUNTER_NATIVE_POSIX_IRQ_PRIORITY,
-		    counter_isr, NULL, COUNTER_NATIVE_POSIX_IRQ_FLAGS);
-	irq_enable(COUNTER_EVENT_IRQ);
-	hw_counter_set_period(COUNTER_PERIOD);
-	hw_counter_set_wrap_value((uint64_t)top.ticks + 1);
-	hw_counter_reset();
-
-	return 0;
-}
-
-static int ctr_start(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-	schedule_next_isr();
-	hw_counter_start();
-	return 0;
-}
-
-static int ctr_stop(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-	hw_counter_stop();
-	return 0;
-}
-
-static int ctr_get_value(const struct device *dev, uint32_t *ticks)
-{
-	ARG_UNUSED(dev);
-
-	*ticks = hw_counter_get_value();
-	return 0;
-}
-
-static uint32_t ctr_get_pending_int(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-	return 0;
-}
-
-static bool is_any_alarm_pending(void)
-{
-	for (int i = 0; i < DRIVER_CONFIG_INFO_CHANNELS; i++) {
-		if (is_alarm_pending[i]) {
-			return true;
-		}
-	}
-	return false;
-}
-
-static int ctr_set_top_value(const struct device *dev,
-			     const struct counter_top_cfg *cfg)
-{
-	ARG_UNUSED(dev);
-
-	if (is_any_alarm_pending()) {
-		posix_print_warning("Can't set top value while alarm is active\n");
-		return -EBUSY;
-	}
-
-	uint32_t current_value = hw_counter_get_value();
-
-	if (cfg->flags & COUNTER_TOP_CFG_DONT_RESET) {
-		if (current_value >= cfg->ticks) {
-			if (cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) {
-				hw_counter_reset();
-			}
-			return -ETIME;
-		}
-	} else {
-		hw_counter_reset();
-	}
-
-	top = *cfg;
-	hw_counter_set_wrap_value((uint64_t)top.ticks + 1);
-
-	if ((cfg->ticks == TOP_VALUE) && !cfg->callback) {
-		is_top_set = false;
-	} else {
-		is_top_set = true;
-	}
-
-	schedule_next_isr();
-
-	return 0;
-}
-
-static uint32_t ctr_get_top_value(const struct device *dev)
-{
-	return top.ticks;
-}
-
-static int ctr_set_alarm(const struct device *dev, uint8_t chan_id,
-			 const struct counter_alarm_cfg *alarm_cfg)
-{
-	ARG_UNUSED(dev);
-
-	if (is_alarm_pending[chan_id]) {
-		return -EBUSY;
-	}
-
-	uint32_t ticks = alarm_cfg->ticks;
-
-	if (ticks > top.ticks) {
-		posix_print_warning("Alarm ticks %u exceed top ticks %u\n", ticks,
-				top.ticks);
-		return -EINVAL;
-	}
-
-	if (!(alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE)) {
-		uint32_t current_value = hw_counter_get_value();
-
-		ticks += current_value;
-		if (ticks > top.ticks) { /* Handle wrap arounds */
-			ticks -= (top.ticks + 1); /* The count period is top.ticks + 1 */
-		}
-	}
-
-	pending_alarm[chan_id] = *alarm_cfg;
-	pending_alarm[chan_id].ticks = ticks;
-	is_alarm_pending[chan_id] = true;
-
-	schedule_next_isr();
-
-	return 0;
-}
-
-static int ctr_cancel_alarm(const struct device *dev, uint8_t chan_id)
-{
-	ARG_UNUSED(dev);
-
-	if (!hw_counter_is_started()) {
-		posix_print_warning("Counter not started\n");
-		return -ENOTSUP;
-	}
-
-	is_alarm_pending[chan_id] = false;
-
-	schedule_next_isr();
-
-	return 0;
-}
-
-static DEVICE_API(counter, ctr_api) = {
-	.start = ctr_start,
-	.stop = ctr_stop,
-	.get_value = ctr_get_value,
-	.set_alarm = ctr_set_alarm,
-	.cancel_alarm = ctr_cancel_alarm,
-	.set_top_value = ctr_set_top_value,
-	.get_pending_int = ctr_get_pending_int,
-	.get_top_value = ctr_get_top_value,
-};
-
-static const struct counter_config_info ctr_config = {
-	.max_top_value = UINT_MAX,
-	.freq = CONFIG_COUNTER_NATIVE_POSIX_FREQUENCY,
-	.channels = DRIVER_CONFIG_INFO_CHANNELS,
-	.flags = DRIVER_CONFIG_INFO_FLAGS
-};
-
-DEVICE_DT_INST_DEFINE(0, ctr_init,
-		    NULL, NULL, &ctr_config, PRE_KERNEL_1,
-		    CONFIG_COUNTER_INIT_PRIORITY, &ctr_api);
diff --git a/drivers/counter/counter_native_sim.c b/drivers/counter/counter_native_sim.c
new file mode 100644
index 00000000000..c044f8eef3d
--- /dev/null
+++ b/drivers/counter/counter_native_sim.c
@@ -0,0 +1,265 @@
+/*
+ * Copyright (c) 2020, Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#if DT_HAS_COMPAT_STATUS_OKAY(zephyr_native_posix_counter)
+#define DT_DRV_COMPAT zephyr_native_posix_counter
+#warning "zephyr,native-posix-counter is deprecated in favor of zephyr,native-sim-counter"
+#else
+#define DT_DRV_COMPAT zephyr_native_sim_counter
+#endif
+
+#include <string.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/counter.h>
+#include <zephyr/irq.h>
+#include <soc.h>
+#include <hw_counter.h>
+#include <limits.h>
+
+#define DRIVER_CONFIG_INFO_FLAGS (COUNTER_CONFIG_INFO_COUNT_UP)
+#define DRIVER_CONFIG_INFO_CHANNELS CONFIG_COUNTER_NATIVE_SIM_NBR_CHANNELS
+#define COUNTER_NATIVE_SIM_IRQ_FLAGS (0)
+#define COUNTER_NATIVE_SIM_IRQ_PRIORITY (2)
+
+#define COUNTER_PERIOD (USEC_PER_SEC / CONFIG_COUNTER_NATIVE_SIM_FREQUENCY)
+#define TOP_VALUE (UINT_MAX)
+
+static struct counter_alarm_cfg pending_alarm[DRIVER_CONFIG_INFO_CHANNELS];
+static bool is_alarm_pending[DRIVER_CONFIG_INFO_CHANNELS];
+static struct counter_top_cfg top;
+static bool is_top_set;
+static const struct device *device;
+
+static void schedule_next_isr(void)
+{
+	int64_t current_value = hw_counter_get_value();
+	uint32_t next_time = top.ticks; /* top.ticks is TOP_VALUE if is_top_set == false */
+
+	if (current_value == top.ticks) {
+		current_value = -1;
+	}
+
+	for (int i = 0; i < DRIVER_CONFIG_INFO_CHANNELS; i++) {
+		if (is_alarm_pending[i]) {
+			if (pending_alarm[i].ticks > current_value) {
+				/* If the alarm is not after a wrap */
+				next_time = MIN(pending_alarm[i].ticks, next_time);
+			}
+		}
+	}
+
+	/* We will at least get an interrupt at top.ticks even if is_top_set == false,
+	 * which is fine. We may use that to set the next alarm if needed
+	 */
+	hw_counter_set_target(next_time);
+}
+
+static void counter_isr(const void *arg)
+{
+	ARG_UNUSED(arg);
+	uint32_t current_value = hw_counter_get_value();
+
+	for (int i = 0; i < DRIVER_CONFIG_INFO_CHANNELS; i++) {
+		if (is_alarm_pending[i] && (current_value == pending_alarm[i].ticks)) {
+			is_alarm_pending[i] = false;
+			if (pending_alarm[i].callback) {
+				pending_alarm[i].callback(device, i, current_value,
+							  pending_alarm[i].user_data);
+			}
+		}
+	}
+
+	if (is_top_set && (current_value == top.ticks)) {
+		if (top.callback) {
+			top.callback(device, top.user_data);
+		}
+	}
+
+	schedule_next_isr();
+}
+
+static int ctr_init(const struct device *dev)
+{
+	device = dev;
+	memset(is_alarm_pending, 0, sizeof(is_alarm_pending));
+	is_top_set = false;
+	top.ticks = TOP_VALUE;
+
+	IRQ_CONNECT(COUNTER_EVENT_IRQ, COUNTER_NATIVE_SIM_IRQ_PRIORITY,
+		    counter_isr, NULL, COUNTER_NATIVE_SIM_IRQ_FLAGS);
+	irq_enable(COUNTER_EVENT_IRQ);
+	hw_counter_set_period(COUNTER_PERIOD);
+	hw_counter_set_wrap_value((uint64_t)top.ticks + 1);
+	hw_counter_reset();
+
+	return 0;
+}
+
+static int ctr_start(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	schedule_next_isr();
+	hw_counter_start();
+	return 0;
+}
+
+static int ctr_stop(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	hw_counter_stop();
+	return 0;
+}
+
+static int ctr_get_value(const struct device *dev, uint32_t *ticks)
+{
+	ARG_UNUSED(dev);
+
+	*ticks = hw_counter_get_value();
+	return 0;
+}
+
+static int ctr_reset(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	hw_counter_reset();
+	return 0;
+}
+
+static uint32_t ctr_get_pending_int(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+	return 0;
+}
+
+static bool is_any_alarm_pending(void)
+{
+	for (int i = 0; i < DRIVER_CONFIG_INFO_CHANNELS; i++) {
+		if (is_alarm_pending[i]) {
+			return true;
+		}
+	}
+	return false;
+}
+
+static int ctr_set_top_value(const struct device *dev,
+			     const struct counter_top_cfg *cfg)
+{
+	ARG_UNUSED(dev);
+
+	if (is_any_alarm_pending()) {
+		posix_print_warning("Can't set top value while alarm is active\n");
+		return -EBUSY;
+	}
+
+	uint32_t current_value = hw_counter_get_value();
+
+	if (cfg->flags & COUNTER_TOP_CFG_DONT_RESET) {
+		if (current_value >= cfg->ticks) {
+			if (cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) {
+				hw_counter_reset();
+			}
+			return -ETIME;
+		}
+	} else {
+		hw_counter_reset();
+	}
+
+	top = *cfg;
+	hw_counter_set_wrap_value((uint64_t)top.ticks + 1);
+
+	if ((cfg->ticks == TOP_VALUE) && !cfg->callback) {
+		is_top_set = false;
+	} else {
+		is_top_set = true;
+	}
+
+	schedule_next_isr();
+
+	return 0;
+}
+
+static uint32_t ctr_get_top_value(const struct device *dev)
+{
+	return top.ticks;
+}
+
+static int ctr_set_alarm(const struct device *dev, uint8_t chan_id,
+			 const struct counter_alarm_cfg *alarm_cfg)
+{
+	ARG_UNUSED(dev);
+
+	if (is_alarm_pending[chan_id]) {
+		return -EBUSY;
+	}
+
+	uint32_t ticks = alarm_cfg->ticks;
+
+	if (ticks > top.ticks) {
+		posix_print_warning("Alarm ticks %u exceed top ticks %u\n", ticks,
+				top.ticks);
+		return -EINVAL;
+	}
+
+	if (!(alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE)) {
+		uint32_t current_value = hw_counter_get_value();
+
+		ticks += current_value;
+		if (ticks > top.ticks) { /* Handle wrap arounds */
+			ticks -= (top.ticks + 1); /* The count period is top.ticks + 1 */
+		}
+	}
+
+	pending_alarm[chan_id] = *alarm_cfg;
+	pending_alarm[chan_id].ticks = ticks;
+	is_alarm_pending[chan_id] = true;
+
+	schedule_next_isr();
+
+	return 0;
+}
+
+static int ctr_cancel_alarm(const struct device *dev, uint8_t chan_id)
+{
+	ARG_UNUSED(dev);
+
+	if (!hw_counter_is_started()) {
+		posix_print_warning("Counter not started\n");
+		return -ENOTSUP;
+	}
+
+	is_alarm_pending[chan_id] = false;
+
+	schedule_next_isr();
+
+	return 0;
+}
+
+static DEVICE_API(counter, ctr_api) = {
+	.start = ctr_start,
+	.stop = ctr_stop,
+	.get_value = ctr_get_value,
+	.reset = ctr_reset,
+	.set_alarm = ctr_set_alarm,
+	.cancel_alarm = ctr_cancel_alarm,
+	.set_top_value = ctr_set_top_value,
+	.get_pending_int = ctr_get_pending_int,
+	.get_top_value = ctr_get_top_value,
+};
+
+static const struct counter_config_info ctr_config = {
+	.max_top_value = UINT_MAX,
+	.freq = CONFIG_COUNTER_NATIVE_SIM_FREQUENCY,
+	.channels = DRIVER_CONFIG_INFO_CHANNELS,
+	.flags = DRIVER_CONFIG_INFO_FLAGS
+};
+
+DEVICE_DT_INST_DEFINE(0, ctr_init,
+		    NULL, NULL, &ctr_config, PRE_KERNEL_1,
+		    CONFIG_COUNTER_INIT_PRIORITY, &ctr_api);
diff --git a/drivers/counter/counter_nrfx_timer.c b/drivers/counter/counter_nrfx_timer.c
index 6af5a31ad15..52e525717a9 100644
--- a/drivers/counter/counter_nrfx_timer.c
+++ b/drivers/counter/counter_nrfx_timer.c
@@ -110,7 +110,13 @@ static int stop(const struct device *dev)
 {
 	const struct counter_nrfx_config *config = dev->config;
 
+#if NRF_TIMER_HAS_SHUTDOWN
+	nrf_timer_task_trigger(config->timer, NRF_TIMER_TASK_SHUTDOWN);
+#else
 	nrf_timer_task_trigger(config->timer, NRF_TIMER_TASK_STOP);
+	nrf_timer_task_trigger(config->timer, NRF_TIMER_TASK_CLEAR);
+#endif
+
 #ifdef COUNTER_ANY_FAST
 	struct counter_nrfx_data *data = dev->data;
 
@@ -152,6 +158,14 @@ static int get_value(const struct device *dev, uint32_t *ticks)
 	return 0;
 }
 
+static int reset(const struct device *dev)
+{
+	const struct counter_nrfx_config *config = dev->config;
+
+	nrf_timer_task_trigger(config->timer, NRF_TIMER_TASK_CLEAR);
+	return 0;
+}
+
 static uint32_t ticks_add(uint32_t val1, uint32_t val2, uint32_t top)
 {
 	uint32_t to_top;
@@ -446,6 +460,7 @@ static DEVICE_API(counter, counter_nrfx_driver_api) = {
 	.start = start,
 	.stop = stop,
 	.get_value = get_value,
+	.reset = reset,
 	.set_alarm = set_alarm,
 	.cancel_alarm = cancel_alarm,
 	.set_top_value = set_top_value,
diff --git a/drivers/counter/counter_realtek_rts5912.c b/drivers/counter/counter_realtek_rts5912.c
new file mode 100644
index 00000000000..40505d66132
--- /dev/null
+++ b/drivers/counter/counter_realtek_rts5912.c
@@ -0,0 +1,357 @@
+/*
+ * Copyright (c) 2025 Realtek Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT realtek_rts5912_timer
+
+/**
+ * @file
+ * @brief Realtek RTS5912 Counter driver
+ *
+ * This is the driver for the 32-bit counters on the Realtek SoCs.
+ *
+ * Notes:
+ * - The counters are running in down counting mode.
+ * - Interrupts are triggered (if enabled) when the counter
+ *   reaches zero.
+ * - These are not free running counters where there are separate
+ *   compare values for interrupts. When setting single shot alarms,
+ *   the counter values are changed so that interrupts are triggered
+ *   when the counters reach zero.
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/counter.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/clock_control_rts5912.h>
+#include "reg/reg_timer.h"
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(counter_realtek_rts5912, CONFIG_COUNTER_LOG_LEVEL);
+struct counter_rts5912_config {
+	struct counter_config_info info;
+	void (*config_func)(void);
+	volatile struct timer32_type *base_address;
+	uint16_t prescaler;
+	uint32_t clk_grp;
+	uint32_t clk_idx;
+	const struct device *clk_dev;
+};
+
+struct counter_rts5912_data {
+	counter_alarm_callback_t alarm_cb;
+	counter_top_callback_t top_cb;
+	void *user_data;
+};
+
+#define COUNTER_RTS5912_REG_BASE(_dev)                                                             \
+	((const struct counter_rts5912_config *const)_dev->config)->base_address
+
+static int counter_rts5912_start(const struct device *dev)
+{
+	const struct counter_rts5912_config *config = dev->config;
+	volatile struct timer32_type *counter = config->base_address;
+
+	if (counter->ctrl & TIMER32_CTRL_EN) {
+		return 0;
+	}
+
+	counter->ctrl |= (TIMER32_CTRL_EN);
+
+	LOG_DBG("%p Counter started", dev);
+
+	return 0;
+}
+
+static int counter_rts5912_stop(const struct device *dev)
+{
+	const struct counter_rts5912_config *config = dev->config;
+	volatile struct timer32_type *counter = config->base_address;
+
+	if (!(counter->ctrl & TIMER32_CTRL_EN)) {
+		/* Already stopped, nothing to do */
+		return 0;
+	}
+	/* disable timer and disable interrupt. */
+	counter->ctrl = TIMER32_CTRL_INTEN_DIS;
+	counter->cnt = counter->ldcnt;
+	/* w1c interrupt pending status */
+	counter->intclr |= TIMER32_INTCLR_INTCLR;
+
+	LOG_DBG("%p Counter stopped", dev);
+
+	return 0;
+}
+
+static int counter_rts5912_get_value(const struct device *dev, uint32_t *ticks)
+{
+	const struct counter_rts5912_config *config = dev->config;
+	volatile struct timer32_type *counter = config->base_address;
+
+	*ticks = counter->cnt + 1;
+	return 0;
+}
+
+static int counter_rts5912_set_alarm(const struct device *dev, uint8_t chan_id,
+				     const struct counter_alarm_cfg *alarm_cfg)
+{
+	struct counter_rts5912_data *data = dev->data;
+	const struct counter_rts5912_config *counter_cfg = dev->config;
+	volatile struct timer32_type *counter = counter_cfg->base_address;
+	uint32_t value;
+
+	if (chan_id != 0) {
+		LOG_ERR("Invalid channel id %u", chan_id);
+		return -ENOTSUP;
+	}
+
+	/* Interrupts are only triggered when the counter reaches 0.
+	 * So only relative alarms are supported.
+	 */
+	if (alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) {
+		return -ENOTSUP;
+	}
+
+	if (data->alarm_cb != NULL) {
+		return -EBUSY;
+	}
+
+	if (!alarm_cfg->callback) {
+		return -EINVAL;
+	}
+
+	if (alarm_cfg->ticks > counter_cfg->info.max_top_value) {
+		return -EINVAL;
+	}
+	/* disable timer */
+	counter->ctrl &= ~TIMER32_CTRL_EN;
+	/* disable interrupt */
+	counter->ctrl |= TIMER32_CTRL_INTEN_DIS;
+	/* set in one-shot mode */
+	counter->ctrl &= ~TIMER32_CTRL_MDSELS_PERIOD;
+	/* set load counter */
+	counter->ldcnt = alarm_cfg->ticks;
+
+	data->alarm_cb = alarm_cfg->callback;
+	data->user_data = alarm_cfg->user_data;
+	/* w1c interrupt status */
+	counter->intclr |= TIMER32_INTCLR_INTCLR;
+	/* enable interrupt */
+	counter->ctrl &= ~TIMER32_CTRL_INTEN_DIS;
+
+	LOG_DBG("%p Counter alarm set to %u ticks", dev, alarm_cfg->ticks);
+	/* enable timer and re-load PRCNT to CNT */
+	counter->ctrl |= TIMER32_CTRL_EN;
+	/* read count value to update register */
+	value = counter->cnt;
+
+	return 0;
+}
+
+static int counter_rts5912_cancel_alarm(const struct device *dev, uint8_t chan_id)
+{
+	struct counter_rts5912_data *data = dev->data;
+	const struct counter_rts5912_config *config = dev->config;
+	volatile struct timer32_type *counter = config->base_address;
+
+	if (chan_id != 0) {
+		LOG_ERR("Invalid channel id %u", chan_id);
+		return -ENOTSUP;
+	}
+
+	counter->ctrl = 0;
+
+	data->alarm_cb = NULL;
+	data->user_data = NULL;
+
+	LOG_DBG("%p Counter alarm canceled", dev);
+
+	return 0;
+}
+
+static uint32_t counter_rts5912_get_pending_int(const struct device *dev)
+{
+	const struct counter_rts5912_config *config = dev->config;
+	volatile struct timer32_type *counter = config->base_address;
+
+	return counter->intsts;
+}
+
+static uint32_t counter_rts5912_get_top_value(const struct device *dev)
+{
+	const struct counter_rts5912_config *config = dev->config;
+	volatile struct timer32_type *counter = config->base_address;
+
+	return counter->ldcnt;
+}
+
+static int counter_rts5912_set_top_value(const struct device *dev,
+					 const struct counter_top_cfg *cfg)
+{
+	const struct counter_rts5912_config *counter_cfg = dev->config;
+	struct counter_rts5912_data *data = dev->data;
+	volatile struct timer32_type *counter = counter_cfg->base_address;
+	uint32_t value;
+	int ret = 0;
+
+	if (data->alarm_cb) {
+		return -EBUSY;
+	}
+
+	if (cfg->ticks > counter_cfg->info.max_top_value) {
+		return -EINVAL;
+	}
+
+	counter->ctrl &= ~TIMER32_CTRL_EN;
+	counter->ctrl |= TIMER32_CTRL_INTEN_DIS;
+
+	counter->ldcnt = cfg->ticks;
+
+	data->top_cb = cfg->callback;
+	data->user_data = cfg->user_data;
+
+	if (data->top_cb) {
+		/* w1c interrupt status */
+		counter->intclr |= TIMER32_INTCLR_INTCLR;
+		/* enable interrupt */
+		counter->ctrl &= ~TIMER32_CTRL_INTEN_DIS;
+		/* enable periodic alarm mode */
+		counter->ctrl |= TIMER32_CTRL_MDSELS_PERIOD;
+	} else {
+		counter->ctrl = TIMER32_CTRL_INTEN_DIS;
+	}
+
+	LOG_DBG("%p Counter top value was set to %u", dev, cfg->ticks);
+
+	counter->ctrl |= TIMER32_CTRL_EN;
+	/* read count value to update register */
+	value = counter->cnt;
+
+	return ret;
+}
+
+static void counter_rts5912_isr(const struct device *dev)
+{
+	struct counter_rts5912_data *data = dev->data;
+	const struct counter_rts5912_config *config = dev->config;
+	volatile struct timer32_type *counter = config->base_address;
+	counter_alarm_callback_t alarm_cb;
+	void *user_data;
+	uint32_t value;
+
+	/* disable timer */
+	counter->ctrl &= ~TIMER32_CTRL_EN;
+	/* disable interrupt */
+	counter->ctrl |= TIMER32_CTRL_INTEN_DIS;
+	/* clear interrupt pending status */
+	counter->intclr |= TIMER32_INTCLR_INTCLR;
+
+	LOG_DBG("%p Counter ISR", dev);
+
+	if (data->alarm_cb) {
+		/* Alarm is one-shot, so disable callback */
+		alarm_cb = data->alarm_cb;
+		data->alarm_cb = NULL;
+		user_data = data->user_data;
+
+		alarm_cb(dev, 0, counter->cnt + 1, user_data);
+	} else if (data->top_cb) {
+		data->top_cb(dev, data->user_data);
+		/* periodic alarm mode, enable interrupt */
+		counter->ctrl &= ~TIMER32_CTRL_INTEN_DIS;
+		/* enable timer again */
+		counter->ctrl |= TIMER32_CTRL_EN;
+		/* read count value to update register */
+		value = counter->cnt;
+	}
+}
+
+static uint32_t counter_rts5912_get_freq(const struct device *dev)
+{
+	const struct counter_rts5912_config *counter_cfg = dev->config;
+
+	return counter_cfg->info.freq;
+}
+
+static DEVICE_API(counter, counter_rts5912_api) = {
+	.start = counter_rts5912_start,
+	.stop = counter_rts5912_stop,
+	.get_value = counter_rts5912_get_value,
+	.set_alarm = counter_rts5912_set_alarm,
+	.cancel_alarm = counter_rts5912_cancel_alarm,
+	.set_top_value = counter_rts5912_set_top_value,
+	.get_pending_int = counter_rts5912_get_pending_int,
+	.get_top_value = counter_rts5912_get_top_value,
+	.get_freq = counter_rts5912_get_freq,
+};
+
+static int counter_rts5912_init(const struct device *dev)
+{
+	const struct counter_rts5912_config *counter_cfg = dev->config;
+	volatile struct timer32_type *counter = counter_cfg->base_address;
+	int rc;
+	struct rts5912_sccon_subsys sccon_subsys = {
+		.clk_grp = counter_cfg->clk_grp,
+		.clk_idx = counter_cfg->clk_idx,
+	};
+
+	if (!device_is_ready(counter_cfg->clk_dev)) {
+		LOG_ERR("device is not ready");
+		return -ENODEV;
+	}
+
+	rc = clock_control_on(counter_cfg->clk_dev, (clock_control_subsys_t)&sccon_subsys);
+	if (rc != 0) {
+		LOG_ERR("clock power on fail");
+		return rc;
+	}
+
+	counter_rts5912_stop(dev);
+
+	/* Set preload and actually pre-load the counter */
+	counter->ldcnt = counter_cfg->info.max_top_value;
+	counter->cnt = counter_cfg->info.max_top_value;
+
+	counter_cfg->config_func();
+	LOG_DBG("Init complete!");
+	return 0;
+}
+
+#define DEV_CONFIG_CLK_DEV_INIT(n)                                                                 \
+	.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),                                          \
+	.clk_grp = DT_INST_CLOCKS_CELL_BY_NAME(n, tmr32, clk_grp),                                 \
+	.clk_idx = DT_INST_CLOCKS_CELL_BY_NAME(n, tmr32, clk_idx),
+
+#define COUNTER_RTS5912_INIT(inst)                                                                 \
+	static void counter_rts5912_irq_config_##inst(void);                                       \
+                                                                                                   \
+	static struct counter_rts5912_data counter_rts5912_dev_data_##inst;                        \
+                                                                                                   \
+	static struct counter_rts5912_config counter_rts5912_dev_config_##inst = {                 \
+		.info =                                                                            \
+			{                                                                          \
+				.max_top_value = DT_INST_PROP(inst, max_value),                    \
+				.freq = DT_INST_PROP(inst, clock_frequency) /                      \
+					(1 << DT_INST_PROP(inst, prescaler)),                      \
+				.flags = 0,                                                        \
+				.channels = 1,                                                     \
+			},                                                                         \
+                                                                                                   \
+		.config_func = counter_rts5912_irq_config_##inst,                                  \
+		.base_address = (struct timer32_type *)DT_INST_REG_ADDR(inst),                     \
+		.prescaler = DT_INST_PROP(inst, prescaler),                                        \
+		DEV_CONFIG_CLK_DEV_INIT(inst)};                                                    \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(inst, counter_rts5912_init, NULL, &counter_rts5912_dev_data_##inst,  \
+			      &counter_rts5912_dev_config_##inst, PRE_KERNEL_1,                    \
+			      CONFIG_COUNTER_INIT_PRIORITY, &counter_rts5912_api);                 \
+                                                                                                   \
+	static void counter_rts5912_irq_config_##inst(void)                                        \
+	{                                                                                          \
+		IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), counter_rts5912_isr,  \
+			    DEVICE_DT_INST_GET(inst), 0);                                          \
+		irq_enable(DT_INST_IRQN(inst));                                                    \
+	}
+
+DT_INST_FOREACH_STATUS_OKAY(COUNTER_RTS5912_INIT)
diff --git a/drivers/counter/counter_realtek_rts5912_slwtmr.c b/drivers/counter/counter_realtek_rts5912_slwtmr.c
new file mode 100644
index 00000000000..d9741779f69
--- /dev/null
+++ b/drivers/counter/counter_realtek_rts5912_slwtmr.c
@@ -0,0 +1,339 @@
+/*
+ * Copyright (c) 2025 Realtek Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT realtek_rts5912_slwtimer
+
+/**
+ * @file
+ * @brief Realtek RTS5912 Counter driver
+ *
+ * This is the driver for the 32-bit counters on the Realtek SoCs.
+ *
+ * Notes:
+ * - The counters are running in down counting mode.
+ * - Interrupts are triggered (if enabled) when the counter
+ *   reaches zero.
+ * - These are not free running counters where there are separate
+ *   compare values for interrupts. When setting single shot alarms,
+ *   the counter values are changed so that interrupts are triggered
+ *   when the counters reach zero.
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/counter.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/clock_control_rts5912.h>
+#include <zephyr/logging/log.h>
+#include "reg/reg_slwtmr.h"
+LOG_MODULE_REGISTER(counter_realtek_rts5912_slwtmr, CONFIG_COUNTER_LOG_LEVEL);
+
+struct counter_rts5912_config {
+	struct counter_config_info info;
+	void (*config_func)(void);
+	volatile struct slwtmr_type *base_address;
+	uint16_t prescaler;
+#if (CONFIG_CLOCK_CONTROL)
+	const struct device *clk_dev;
+	struct rts5912_sccon_subsys sccon_cfg;
+#endif
+};
+
+struct counter_rts5912_data {
+	counter_alarm_callback_t alarm_cb;
+	counter_top_callback_t top_cb;
+	void *user_data;
+};
+
+static int counter_rts5912_start(const struct device *dev)
+{
+	const struct counter_rts5912_config *config = dev->config;
+	volatile struct slwtmr_type *counter = config->base_address;
+
+	if (counter->ctrl & SLWTMR_CTRL_EN) {
+		return -EALREADY;
+	}
+
+	counter->ctrl |= SLWTMR_CTRL_EN;
+
+	LOG_DBG("%p Counter started", dev);
+
+	return 0;
+}
+
+static int counter_rts5912_stop(const struct device *dev)
+{
+	const struct counter_rts5912_config *config = dev->config;
+	volatile struct slwtmr_type *counter = config->base_address;
+
+	if (!(counter->ctrl & SLWTMR_CTRL_EN)) {
+		/* Already stopped, nothing to do */
+		return 0;
+	}
+
+	/* disable timer and disable interrupt. */
+	counter->ctrl = 0;
+	counter->ldcnt = counter->cnt;
+
+	/* w1c interrupt pending status */
+	counter->insts |= SLWTMR_INTSTS_STS;
+
+	LOG_DBG("%p Counter stopped", dev);
+
+	return 0;
+}
+
+static int counter_rts5912_get_value(const struct device *dev, uint32_t *ticks)
+{
+	const struct counter_rts5912_config *config = dev->config;
+	volatile struct slwtmr_type *counter = config->base_address;
+
+	*ticks = counter->cnt;
+	return 0;
+}
+
+static int counter_rts5912_set_alarm(const struct device *dev, uint8_t chan_id,
+				     const struct counter_alarm_cfg *alarm_cfg)
+{
+	const struct counter_rts5912_config *config = dev->config;
+	volatile struct slwtmr_type *counter = config->base_address;
+	struct counter_rts5912_data *data = dev->data;
+
+	if (chan_id != 0) {
+		LOG_ERR("Invalid channel id %u", chan_id);
+		return -ENOTSUP;
+	}
+
+	/* Interrupts are only triggered when the counter reaches 0.
+	 * So only relative alarms are supported.
+	 */
+	if (alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE) {
+		return -ENOTSUP;
+	}
+
+	if (data->alarm_cb != NULL) {
+		return -EBUSY;
+	}
+
+	if (!alarm_cfg->callback) {
+		return -EINVAL;
+	}
+
+	if (alarm_cfg->ticks > config->info.max_top_value) {
+		return -EINVAL;
+	}
+	/* disable timer and disable interrupt */
+	counter->ctrl = 0;
+
+	counter->ldcnt = alarm_cfg->ticks;
+
+	data->alarm_cb = alarm_cfg->callback;
+	data->user_data = alarm_cfg->user_data;
+	/* w1c interrupt status */
+	counter->insts |= SLWTMR_INTSTS_STS;
+	/* enable interrupt */
+	counter->ctrl |= SLWTMR_CTRL_INTEN_EN;
+
+	LOG_DBG("%p Counter alarm set to %u ticks", dev, alarm_cfg->ticks);
+	/* enable timer and re-load PRcnt to cnt */
+	counter->ctrl |= SLWTMR_CTRL_EN;
+
+	return 0;
+}
+
+static int counter_rts5912_cancel_alarm(const struct device *dev, uint8_t chan_id)
+{
+	const struct counter_rts5912_config *config = dev->config;
+	volatile struct slwtmr_type *counter = config->base_address;
+	struct counter_rts5912_data *data = dev->data;
+
+	if (chan_id != 0) {
+		LOG_ERR("Invalid channel id %u", chan_id);
+		return -ENOTSUP;
+	}
+
+	counter->ctrl = 0;
+
+	data->alarm_cb = NULL;
+	data->user_data = NULL;
+
+	LOG_DBG("%p Counter alarm canceled", dev);
+
+	return 0;
+}
+
+static uint32_t counter_rts5912_get_pending_int(const struct device *dev)
+{
+	const struct counter_rts5912_config *config = dev->config;
+	volatile struct slwtmr_type *counter = config->base_address;
+
+	return counter->insts;
+}
+
+static uint32_t counter_rts5912_get_top_value(const struct device *dev)
+{
+	const struct counter_rts5912_config *config = dev->config;
+	volatile struct slwtmr_type *counter = config->base_address;
+
+	return counter->ldcnt;
+}
+
+static int counter_rts5912_set_top_value(const struct device *dev,
+					 const struct counter_top_cfg *cfg)
+{
+	const struct counter_rts5912_config *config = dev->config;
+	volatile struct slwtmr_type *counter = config->base_address;
+	struct counter_rts5912_data *data = dev->data;
+	int ret = 0;
+
+	if (data->alarm_cb) {
+		return -EBUSY;
+	}
+
+	if (cfg->ticks > config->info.max_top_value) {
+		return -EINVAL;
+	}
+
+	counter->ctrl = 0;
+
+	counter->ldcnt = cfg->ticks;
+
+	data->top_cb = cfg->callback;
+	data->user_data = cfg->user_data;
+
+	if (data->top_cb) {
+		/* w1c interrupt status */
+		counter->insts |= SLWTMR_INTSTS_STS;
+		/* enable interrupt */
+		counter->ctrl |= SLWTMR_CTRL_INTEN_EN;
+		/* enable periodic alarm mode */
+		counter->ctrl |= SLWTMR_CTRL_MDSELS_PERIOD;
+	} else {
+		/* disable interrupt */
+		counter->ctrl &= ~SLWTMR_CTRL_INTEN_EN;
+	}
+
+	LOG_DBG("%p Counter top value was set to %u", dev, cfg->ticks);
+
+	counter->ctrl |= SLWTMR_CTRL_EN;
+	return ret;
+}
+
+static void counter_rts5912_isr(const struct device *dev)
+{
+	const struct counter_rts5912_config *config = dev->config;
+	volatile struct slwtmr_type *counter = config->base_address;
+	struct counter_rts5912_data *data = dev->data;
+	counter_alarm_callback_t alarm_cb;
+	void *user_data;
+	/* disable timer */
+	counter->ctrl &= ~SLWTMR_CTRL_EN;
+	/* disable interrupt */
+	counter->ctrl &= ~SLWTMR_CTRL_INTEN_EN;
+	/* clear interrupt pending status */
+	counter->insts |= SLWTMR_INTSTS_STS;
+
+	LOG_DBG("%p Counter ISR", dev);
+
+	if (data->alarm_cb) {
+		/* Alarm is one-shot, so disable callback */
+		alarm_cb = data->alarm_cb;
+		data->alarm_cb = NULL;
+		user_data = data->user_data;
+
+		alarm_cb(dev, 0, counter->cnt, user_data);
+	} else if (data->top_cb) {
+		data->top_cb(dev, data->user_data);
+		/* periodic alarm mode, enable interrupt */
+		counter->ctrl |= SLWTMR_CTRL_INTEN_EN;
+		/* enable timer again */
+		counter->ctrl |= SLWTMR_CTRL_EN;
+	}
+}
+
+static uint32_t counter_rts5912_get_freq(const struct device *dev)
+{
+	const struct counter_rts5912_config *config = dev->config;
+
+	return config->info.freq;
+}
+
+static DEVICE_API(counter, counter_rts5912_api) = {
+	.start = counter_rts5912_start,
+	.stop = counter_rts5912_stop,
+	.get_value = counter_rts5912_get_value,
+	.set_alarm = counter_rts5912_set_alarm,
+	.cancel_alarm = counter_rts5912_cancel_alarm,
+	.set_top_value = counter_rts5912_set_top_value,
+	.get_pending_int = counter_rts5912_get_pending_int,
+	.get_top_value = counter_rts5912_get_top_value,
+	.get_freq = counter_rts5912_get_freq,
+};
+
+static int counter_rts5912_init(const struct device *dev)
+{
+	const struct counter_rts5912_config *config = dev->config;
+	volatile struct slwtmr_type *counter = config->base_address;
+	int ret;
+
+#if defined(CONFIG_CLOCK_CONTROL)
+	if (!device_is_ready(config->clk_dev)) {
+		return -ENODEV;
+	}
+	ret = clock_control_on(config->clk_dev, (clock_control_subsys_t)&config->sccon_cfg);
+	if (ret != 0) {
+		return ret;
+	}
+#endif
+
+	counter_rts5912_stop(dev);
+	/* Set preload and actually pre-load the counter */
+	counter->ldcnt = config->info.max_top_value;
+	counter->cnt = config->info.max_top_value;
+
+	config->config_func();
+	LOG_DBG("Init Complete");
+	return 0;
+}
+
+#define DEV_CONFIG_CLK_DEV_INIT(n)                                                                 \
+	.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),                                          \
+	.sccon_cfg = {                                                                             \
+		.clk_grp = DT_INST_CLOCKS_CELL_BY_NAME(n, slwtmr, clk_grp),                        \
+		.clk_idx = DT_INST_CLOCKS_CELL_BY_NAME(n, slwtmr, clk_idx),                        \
+	}
+
+#define COUNTER_RTS5912_INIT(inst)                                                                 \
+	static void counter_rts5912_irq_config_##inst(void);                                       \
+                                                                                                   \
+	static struct counter_rts5912_data counter_rts5912_dev_data_##inst;                        \
+                                                                                                   \
+	static struct counter_rts5912_config counter_rts5912_dev_config_##inst = {                 \
+		.info =                                                                            \
+			{                                                                          \
+				.max_top_value = DT_INST_PROP(inst, max_value),                    \
+				.freq = DT_INST_PROP(inst, clock_frequency) /                      \
+					(1 << DT_INST_PROP(inst, prescaler)),                      \
+				.flags = 0,                                                        \
+				.channels = 1,                                                     \
+			},                                                                         \
+                                                                                                   \
+		.config_func = counter_rts5912_irq_config_##inst,                                  \
+		.base_address = (struct slwtmr_type *)DT_INST_REG_ADDR(inst),                      \
+		.prescaler = DT_INST_PROP(inst, prescaler),                                        \
+		DEV_CONFIG_CLK_DEV_INIT(inst)};                                                    \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(inst, counter_rts5912_init, NULL, &counter_rts5912_dev_data_##inst,  \
+			      &counter_rts5912_dev_config_##inst, POST_KERNEL,                     \
+			      CONFIG_COUNTER_INIT_PRIORITY, &counter_rts5912_api);                 \
+                                                                                                   \
+	static void counter_rts5912_irq_config_##inst(void)                                        \
+	{                                                                                          \
+		IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), counter_rts5912_isr,  \
+			    DEVICE_DT_INST_GET(inst), 0);                                          \
+		irq_enable(DT_INST_IRQN(inst));                                                    \
+	}
+
+DT_INST_FOREACH_STATUS_OKAY(COUNTER_RTS5912_INIT)
diff --git a/drivers/counter/counter_renesas_ra_agt.c b/drivers/counter/counter_renesas_ra_agt.c
index be12ac539a8..535e37086c6 100644
--- a/drivers/counter/counter_renesas_ra_agt.c
+++ b/drivers/counter/counter_renesas_ra_agt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -535,11 +535,8 @@ static DEVICE_API(counter, ra_agt_driver_api) = {
 
 #define TIMER(idx) DT_INST_PARENT(idx)
 
-#define _ELC_EVENT_AGT_INT(channel)       ELC_EVENT_AGT##channel##_INT
-#define _ELC_EVENT_AGT_COMPARE_A(channel) ELC_EVENT_AGT##channel##_COMPARE_A
-
-#define ELC_EVENT_AGT_INT(channel)       _ELC_EVENT_AGT_INT(channel)
-#define ELC_EVENT_AGT_COMPARE_A(channel) _ELC_EVENT_AGT_COMPARE_A(channel)
+#define EVENT_AGT_INT(channel)       BSP_PRV_IELS_ENUM(CONCAT(EVENT_AGT, channel, _INT))
+#define EVENT_AGT_COMPARE_A(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_AGT, channel, _COMPARE_A))
 
 #define AGT_DEVICE_INIT_RA(n)                                                                      \
 	static const struct counter_ra_agt_config ra_agt_config_##n = {                            \
@@ -570,14 +567,14 @@ static DEVICE_API(counter, ra_agt_driver_api) = {
 	static int counter_ra_agt_##n##_init(const struct device *dev)                             \
 	{                                                                                          \
 		R_ICU->IELSR[DT_IRQ_BY_NAME(TIMER(n), agti, irq)] =                                \
-			ELC_EVENT_AGT_INT(DT_PROP(TIMER(n), channel));                             \
+			EVENT_AGT_INT(DT_PROP(TIMER(n), channel));                                 \
 		IRQ_CONNECT(DT_IRQ_BY_NAME(TIMER(n), agti, irq),                                   \
 			    DT_IRQ_BY_NAME(TIMER(n), agti, priority), counter_ra_agt_agti_isr,     \
 			    DEVICE_DT_INST_GET(n), 0);                                             \
 		irq_enable(DT_IRQ_BY_NAME(TIMER(n), agti, irq));                                   \
                                                                                                    \
 		R_ICU->IELSR[DT_IRQ_BY_NAME(TIMER(n), agtcmai, irq)] =                             \
-			ELC_EVENT_AGT_COMPARE_A(DT_PROP(TIMER(n), channel));                       \
+			EVENT_AGT_COMPARE_A(DT_PROP(TIMER(n), channel));                           \
 		IRQ_CONNECT(DT_IRQ_BY_NAME(TIMER(n), agtcmai, irq),                                \
 			    DT_IRQ_BY_NAME(TIMER(n), agtcmai, priority),                           \
 			    counter_ra_agt_agtcmai_isr, DEVICE_DT_INST_GET(n), 0);                 \
diff --git a/drivers/counter/counter_renesas_rz_gtm.c b/drivers/counter/counter_renesas_rz_gtm.c
new file mode 100644
index 00000000000..836d213d776
--- /dev/null
+++ b/drivers/counter/counter_renesas_rz_gtm.c
@@ -0,0 +1,553 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_rz_gtm_counter
+
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/counter.h>
+#include <r_gtm.h>
+
+#define RZ_GTM_TOP_VALUE UINT32_MAX
+
+#define counter_rz_gtm_clear_pending(irq) NVIC_ClearPendingIRQ(irq)
+#define counter_rz_gtm_set_pending(irq)   NVIC_SetPendingIRQ(irq)
+#define counter_rz_gtm_is_pending(irq)    NVIC_GetPendingIRQ(irq)
+
+struct counter_rz_gtm_config {
+	struct counter_config_info config_info;
+	const timer_api_t *fsp_api;
+	uint8_t irqn;
+};
+
+struct counter_rz_gtm_data {
+	timer_cfg_t *fsp_cfg;
+	gtm_instance_ctrl_t *fsp_ctrl;
+	/* top callback function */
+	counter_top_callback_t top_cb;
+	/* alarm callback function */
+	counter_alarm_callback_t alarm_cb;
+	void *user_data;
+	uint32_t clk_freq;
+	struct k_spinlock lock;
+	uint32_t guard_period;
+	uint32_t top_val;
+	bool is_started;
+	bool is_periodic;
+};
+
+static int counter_rz_gtm_get_value(const struct device *dev, uint32_t *ticks)
+{
+	const struct counter_rz_gtm_config *cfg = dev->config;
+	struct counter_rz_gtm_data *data = dev->data;
+	timer_status_t timer_status;
+	fsp_err_t err;
+
+	err = cfg->fsp_api->statusGet(data->fsp_ctrl, &timer_status);
+	if (err != FSP_SUCCESS) {
+		return err;
+	}
+	uint32_t value = (uint32_t)timer_status.counter;
+	*ticks = value;
+
+	return 0;
+}
+
+static void counter_rz_gtm_irq_handler(timer_callback_args_t *p_args)
+{
+	const struct device *dev = p_args->p_context;
+	struct counter_rz_gtm_data *data = dev->data;
+	counter_alarm_callback_t alarm_callback = data->alarm_cb;
+	k_spinlock_key_t key;
+
+	key = k_spin_lock(&data->lock);
+
+	if (alarm_callback) {
+		uint32_t now;
+
+		counter_rz_gtm_get_value(dev, &now);
+		data->alarm_cb = NULL;
+		alarm_callback(dev, 0, now, data->user_data);
+	} else if (data->top_cb) {
+		data->top_cb(dev, data->user_data);
+	}
+
+	k_spin_unlock(&data->lock, key);
+}
+
+static int counter_rz_gtm_init(const struct device *dev)
+{
+	struct counter_rz_gtm_data *data = dev->data;
+	const struct counter_rz_gtm_config *cfg = dev->config;
+	int err;
+
+	data->top_val = data->fsp_cfg->period_counts;
+
+	err = cfg->fsp_api->open(data->fsp_ctrl, data->fsp_cfg);
+	if (err != FSP_SUCCESS) {
+		return err;
+	}
+	return err;
+}
+
+static void counter_rz_gtm_start_freerun(const struct device *dev)
+{
+	/* enable counter in free running mode */
+	const struct counter_rz_gtm_config *cfg = dev->config;
+	struct counter_rz_gtm_data *data = dev->data;
+
+	gtm_extended_cfg_t *fsp_cfg_extend = (gtm_extended_cfg_t *)data->fsp_cfg->p_extend;
+
+	fsp_cfg_extend->gtm_mode = GTM_TIMER_MODE_FREERUN;
+	cfg->fsp_api->close(data->fsp_ctrl);
+	cfg->fsp_api->open(data->fsp_ctrl, data->fsp_cfg);
+	cfg->fsp_api->start(data->fsp_ctrl);
+}
+
+static void counter_rz_gtm_start_interval(const struct device *dev)
+{
+	/* start timer in interval mode */
+	const struct counter_rz_gtm_config *cfg = dev->config;
+	struct counter_rz_gtm_data *data = dev->data;
+
+	gtm_extended_cfg_t *fsp_cfg_extend = (gtm_extended_cfg_t *)data->fsp_cfg->p_extend;
+
+	fsp_cfg_extend->gtm_mode = GTM_TIMER_MODE_INTERVAL;
+	cfg->fsp_api->close(data->fsp_ctrl);
+	cfg->fsp_api->open(data->fsp_ctrl, data->fsp_cfg);
+	cfg->fsp_api->start(data->fsp_ctrl);
+}
+
+static int counter_rz_gtm_start(const struct device *dev)
+{
+	const struct counter_rz_gtm_config *cfg = dev->config;
+	struct counter_rz_gtm_data *data = dev->data;
+	k_spinlock_key_t key;
+
+	key = k_spin_lock(&data->lock);
+
+	if (data->is_started) {
+		k_spin_unlock(&data->lock, key);
+		return -EALREADY;
+	}
+
+	if (data->is_periodic) {
+		data->fsp_cfg->period_counts = data->top_val;
+		counter_rz_gtm_start_interval(dev);
+	} else {
+		counter_rz_gtm_start_freerun(dev);
+	}
+
+	counter_rz_gtm_clear_pending(cfg->irqn);
+	data->is_started = true;
+	if (data->top_cb) {
+		irq_enable(cfg->irqn);
+	}
+
+	k_spin_unlock(&data->lock, key);
+
+	return 0;
+}
+
+static int counter_rz_gtm_stop(const struct device *dev)
+{
+	const struct counter_rz_gtm_config *cfg = dev->config;
+	struct counter_rz_gtm_data *data = dev->data;
+	k_spinlock_key_t key;
+
+	key = k_spin_lock(&data->lock);
+
+	if (!data->is_started) {
+		k_spin_unlock(&data->lock, key);
+		return 0;
+	}
+
+	fsp_err_t err = FSP_SUCCESS;
+
+	/* Stop timer */
+	err = cfg->fsp_api->stop(data->fsp_ctrl);
+
+	/* dis irq */
+	irq_disable(cfg->irqn);
+	counter_rz_gtm_clear_pending(cfg->irqn);
+
+	data->top_cb = NULL;
+	data->alarm_cb = NULL;
+	data->user_data = NULL;
+
+	data->is_started = false;
+
+	k_spin_unlock(&data->lock, key);
+
+	return err;
+}
+
+static int counter_rz_gtm_set_alarm(const struct device *dev, uint8_t chan,
+				    const struct counter_alarm_cfg *alarm_cfg)
+{
+	const struct counter_rz_gtm_config *cfg = dev->config;
+	struct counter_rz_gtm_data *data = dev->data;
+
+	bool absolute = alarm_cfg->flags & COUNTER_ALARM_CFG_ABSOLUTE;
+	uint32_t val = alarm_cfg->ticks;
+	k_spinlock_key_t key;
+	bool irq_on_late;
+	uint32_t max_rel_val;
+	uint32_t now, diff;
+	int err = 0;
+
+	if (!alarm_cfg) {
+		return -EINVAL;
+	}
+	/* Alarm callback is mandatory */
+	if (!alarm_cfg->callback) {
+		return -EINVAL;
+	}
+
+	key = k_spin_lock(&data->lock);
+
+	if (!data->is_started) {
+		k_spin_unlock(&data->lock, key);
+		return -EINVAL;
+	}
+
+	/** Alarm_cb need equal NULL before */
+	if (data->alarm_cb) {
+		k_spin_unlock(&data->lock, key);
+		return -EBUSY;
+	}
+
+	/** Timer is currently in interval mode*/
+	if (data->is_periodic) {
+		/** return error because val exceeded the limit set alarm */
+		if (val > data->fsp_cfg->period_counts) {
+			k_spin_unlock(&data->lock, key);
+			return -EINVAL;
+		}
+
+		/* restore free running mode */
+		irq_disable(cfg->irqn);
+		data->top_cb = NULL;
+		data->alarm_cb = alarm_cfg->callback;
+		data->user_data = NULL;
+		data->top_val = RZ_GTM_TOP_VALUE;
+		data->is_periodic = false;
+
+		if (data->is_started) {
+			data->fsp_cfg->period_counts = data->top_val;
+			counter_rz_gtm_start_freerun(dev);
+		}
+	}
+
+	counter_rz_gtm_get_value(dev, &now);
+	data->alarm_cb = alarm_cfg->callback;
+	data->user_data = alarm_cfg->user_data;
+
+	if (absolute) {
+		max_rel_val = RZ_GTM_TOP_VALUE - data->guard_period;
+		irq_on_late = alarm_cfg->flags & COUNTER_ALARM_CFG_EXPIRE_WHEN_LATE;
+	} else {
+		/* If relative value is smaller than half of the counter range
+		 * it is assumed that there is a risk of setting value too late
+		 * and late detection algorithm must be applied. When late
+		 * setting is detected, interrupt shall be triggered for
+		 * immediate expiration of the timer. Detection is performed
+		 * by limiting relative distance between CC and counter.
+		 *
+		 * Note that half of counter range is an arbitrary value.
+		 */
+		irq_on_late = val < (RZ_GTM_TOP_VALUE / 2U);
+		/* limit max to detect short relative being set too late. */
+		max_rel_val = irq_on_late ? RZ_GTM_TOP_VALUE / 2U : RZ_GTM_TOP_VALUE;
+		val = (now + val) & RZ_GTM_TOP_VALUE;
+	}
+
+	/** Set new period */
+	data->fsp_cfg->period_counts = val;
+	err = cfg->fsp_api->periodSet(data->fsp_ctrl, data->fsp_cfg->period_counts);
+	if (err != FSP_SUCCESS) {
+		k_spin_unlock(&data->lock, key);
+		return err;
+	}
+
+	uint32_t read_counter_again = 0;
+
+	counter_rz_gtm_get_value(dev, &read_counter_again);
+	diff = ((val - 1U) - read_counter_again) & RZ_GTM_TOP_VALUE;
+	if (diff > max_rel_val) {
+		if (absolute) {
+			err = -ETIME;
+		}
+
+		/* Interrupt is triggered always for relative alarm and
+		 * for absolute depending on the flag.
+		 */
+		if (irq_on_late) {
+			irq_enable(cfg->irqn);
+			counter_rz_gtm_set_pending(cfg->irqn);
+		} else {
+			data->alarm_cb = NULL;
+		}
+	} else {
+		if (diff == 0) {
+			/* RELOAD value could be set just in time for interrupt
+			 * trigger or too late. In any case time is interrupt
+			 * should be triggered. No need to enable interrupt
+			 * on TIMER just make sure interrupt is pending.
+			 */
+			irq_enable(cfg->irqn);
+			counter_rz_gtm_set_pending(cfg->irqn);
+		} else {
+			counter_rz_gtm_clear_pending(cfg->irqn);
+			irq_enable(cfg->irqn);
+		}
+	}
+
+	k_spin_unlock(&data->lock, key);
+
+	return err;
+}
+
+static int counter_rz_gtm_cancel_alarm(const struct device *dev, uint8_t chan)
+{
+	const struct counter_rz_gtm_config *cfg = dev->config;
+	struct counter_rz_gtm_data *data = dev->data;
+	k_spinlock_key_t key;
+
+	ARG_UNUSED(chan);
+
+	key = k_spin_lock(&data->lock);
+
+	if (!data->is_started) {
+		k_spin_unlock(&data->lock, key);
+		return -EINVAL;
+	}
+
+	if (!data->alarm_cb) {
+		k_spin_unlock(&data->lock, key);
+		return 0;
+	}
+
+	irq_disable(cfg->irqn);
+	counter_rz_gtm_clear_pending(cfg->irqn);
+	data->alarm_cb = NULL;
+	data->user_data = NULL;
+
+	k_spin_unlock(&data->lock, key);
+
+	return 0;
+}
+
+static int counter_rz_gtm_set_top_value(const struct device *dev,
+					const struct counter_top_cfg *top_cfg)
+{
+	const struct counter_rz_gtm_config *cfg = dev->config;
+	struct counter_rz_gtm_data *data = dev->data;
+	k_spinlock_key_t key;
+	uint32_t cur_tick;
+	int ret = 0;
+
+	if (!top_cfg) {
+		return -EINVAL;
+	}
+
+	/** -EBUSY if any alarm is active */
+	if (data->alarm_cb) {
+		return -EBUSY;
+	}
+
+	key = k_spin_lock(&data->lock);
+
+	if (!data->is_periodic && top_cfg->ticks == RZ_GTM_TOP_VALUE) {
+		goto exit_unlock;
+	}
+
+	if (top_cfg->ticks == RZ_GTM_TOP_VALUE) {
+		/* restore free running mode */
+		irq_disable(cfg->irqn);
+		counter_rz_gtm_clear_pending(cfg->irqn);
+		data->top_cb = NULL;
+		data->user_data = NULL;
+		data->top_val = RZ_GTM_TOP_VALUE;
+		data->is_periodic = false;
+
+		if (data->is_started) {
+			counter_rz_gtm_start_freerun(dev);
+			counter_rz_gtm_clear_pending(cfg->irqn);
+		}
+		goto exit_unlock;
+	}
+
+	data->top_cb = top_cfg->callback;
+	data->user_data = top_cfg->user_data;
+	data->top_val = top_cfg->ticks;
+
+	if (!data->is_started) {
+		data->is_periodic = true;
+		goto exit_unlock;
+	}
+
+	if (!data->is_periodic) {
+		/* switch to interval mode first time, restart timer */
+		ret = cfg->fsp_api->stop(data->fsp_ctrl);
+		irq_disable(cfg->irqn);
+		data->is_periodic = true;
+		data->fsp_cfg->period_counts = data->top_val;
+		counter_rz_gtm_start_interval(dev);
+
+		if (data->top_cb) {
+			counter_rz_gtm_clear_pending(cfg->irqn);
+			irq_enable(cfg->irqn);
+		}
+		goto exit_unlock;
+	}
+
+	if (!data->top_cb) {
+		/* new top cfg is without callback - stop IRQs */
+		irq_disable(cfg->irqn);
+		counter_rz_gtm_clear_pending(cfg->irqn);
+	}
+	/* timer already in interval mode - only change top value */
+	data->fsp_cfg->period_counts = data->top_val;
+	cfg->fsp_api->periodSet(&data->fsp_ctrl, data->fsp_cfg->period_counts);
+
+	/* check if counter reset is required */
+	if (top_cfg->flags & COUNTER_TOP_CFG_DONT_RESET) {
+		/* Don't reset counter */
+		counter_rz_gtm_get_value(dev, &cur_tick);
+
+		if (cur_tick >= data->top_val) {
+			ret = -ETIME;
+			if (top_cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) {
+				/* Reset counter if current is late */
+				cfg->fsp_api->stop(data->fsp_ctrl);
+				cfg->fsp_api->start(data->fsp_ctrl);
+			}
+		}
+	} else {
+		/* reset counter */
+		cfg->fsp_api->stop(data->fsp_ctrl);
+		cfg->fsp_api->start(data->fsp_ctrl);
+	}
+
+exit_unlock:
+	k_spin_unlock(&data->lock, key);
+	return ret;
+}
+
+static uint32_t counter_rz_gtm_get_pending_int(const struct device *dev)
+{
+	const struct counter_rz_gtm_config *cfg = dev->config;
+
+	/* There is no register to check TIMER peripheral to check for interrupt
+	 * pending, check directly in NVIC.
+	 */
+	return counter_rz_gtm_is_pending(cfg->irqn);
+}
+
+static uint32_t counter_rz_gtm_get_top_value(const struct device *dev)
+{
+	struct counter_rz_gtm_data *data = dev->data;
+	const struct counter_rz_gtm_config *cfg = dev->config;
+	uint32_t top_val = RZ_GTM_TOP_VALUE;
+
+	if (data->is_periodic) {
+		timer_info_t info;
+
+		cfg->fsp_api->infoGet(data->fsp_ctrl, &info);
+		top_val = info.period_counts;
+	}
+
+	return top_val;
+}
+static uint32_t counter_rz_gtm_get_guard_period(const struct device *dev, uint32_t flags)
+{
+	struct counter_rz_gtm_data *data = dev->data;
+
+	ARG_UNUSED(flags);
+	return data->guard_period;
+}
+
+static int counter_rz_gtm_set_guard_period(const struct device *dev, uint32_t guard, uint32_t flags)
+{
+	struct counter_rz_gtm_data *data = dev->data;
+
+	ARG_UNUSED(flags);
+	__ASSERT_NO_MSG(guard < counter_rz_gtm_get_top_value(dev));
+
+	data->guard_period = guard;
+
+	return 0;
+}
+
+static uint32_t counter_rz_gtm_get_freq(const struct device *dev)
+{
+	struct counter_rz_gtm_data *data = dev->data;
+	const struct counter_rz_gtm_config *cfg = dev->config;
+	timer_info_t info;
+
+	cfg->fsp_api->infoGet(data->fsp_ctrl, &info);
+
+	return info.clock_frequency;
+}
+
+static DEVICE_API(counter, counter_rz_gtm_driver_api) = {
+	.start = counter_rz_gtm_start,
+	.stop = counter_rz_gtm_stop,
+	.get_value = counter_rz_gtm_get_value,
+	.set_alarm = counter_rz_gtm_set_alarm,
+	.cancel_alarm = counter_rz_gtm_cancel_alarm,
+	.set_top_value = counter_rz_gtm_set_top_value,
+	.get_pending_int = counter_rz_gtm_get_pending_int,
+	.get_top_value = counter_rz_gtm_get_top_value,
+	.get_guard_period = counter_rz_gtm_get_guard_period,
+	.set_guard_period = counter_rz_gtm_set_guard_period,
+	.get_freq = counter_rz_gtm_get_freq,
+};
+
+extern void gtm_int_isr(void);
+
+#define GTM(idx) DT_INST_PARENT(idx)
+
+#define COUNTER_RZG_GTM_INIT(inst)                                                                 \
+	static gtm_instance_ctrl_t g_timer##inst##_ctrl;                                           \
+	static gtm_extended_cfg_t g_timer##inst##_extend = {                                       \
+		.generate_interrupt_when_starts = GTM_GIWS_TYPE_DISABLED,                          \
+		.gtm_mode = GTM_TIMER_MODE_FREERUN,                                                \
+	};                                                                                         \
+	static timer_cfg_t g_timer##inst##_cfg = {                                                 \
+		.mode = TIMER_MODE_PERIODIC,                                                       \
+		.period_counts = (uint32_t)RZ_GTM_TOP_VALUE,                                       \
+		.channel = DT_PROP(GTM(inst), channel),                                            \
+		.p_callback = counter_rz_gtm_irq_handler,                                          \
+		.p_context = DEVICE_DT_GET(DT_DRV_INST(inst)),                                     \
+		.p_extend = &g_timer##inst##_extend,                                               \
+		.cycle_end_ipl = DT_IRQ_BY_NAME(GTM(inst), overflow, priority),                    \
+		.cycle_end_irq = DT_IRQ_BY_NAME(GTM(inst), overflow, irq),                         \
+	};                                                                                         \
+	static const struct counter_rz_gtm_config counter_rz_gtm_config_##inst = {                 \
+		.config_info =                                                                     \
+			{                                                                          \
+				.max_top_value = RZ_GTM_TOP_VALUE,                                 \
+				.flags = COUNTER_CONFIG_INFO_COUNT_UP,                             \
+				.channels = 1,                                                     \
+			},                                                                         \
+		.fsp_api = &g_timer_on_gtm,                                                        \
+		.irqn = DT_IRQ_BY_NAME(GTM(inst), overflow, irq),                                  \
+	};                                                                                         \
+	static struct counter_rz_gtm_data counter_rz_gtm_data_##inst = {                           \
+		.fsp_cfg = &g_timer##inst##_cfg, .fsp_ctrl = &g_timer##inst##_ctrl};               \
+	static int counter_rz_gtm_init_##inst(const struct device *dev)                            \
+	{                                                                                          \
+		IRQ_CONNECT(DT_IRQ_BY_NAME(GTM(inst), overflow, irq),                              \
+			    DT_IRQ_BY_NAME(GTM(inst), overflow, priority), gtm_int_isr,            \
+			    DEVICE_DT_INST_GET(inst), 0);                                          \
+		return counter_rz_gtm_init(dev);                                                   \
+	}                                                                                          \
+	DEVICE_DT_INST_DEFINE(inst, counter_rz_gtm_init_##inst, NULL, &counter_rz_gtm_data_##inst, \
+			      &counter_rz_gtm_config_##inst, PRE_KERNEL_1,                         \
+			      CONFIG_COUNTER_INIT_PRIORITY, &counter_rz_gtm_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(COUNTER_RZG_GTM_INIT)
diff --git a/drivers/counter/counter_rpi_pico_timer.c b/drivers/counter/counter_rpi_pico_timer.c
index 81dd5672c50..ae07dc678a1 100644
--- a/drivers/counter/counter_rpi_pico_timer.c
+++ b/drivers/counter/counter_rpi_pico_timer.c
@@ -68,7 +68,9 @@ static uint32_t counter_rpi_pico_timer_get_top_value(const struct device *dev)
 
 static int counter_rpi_pico_timer_get_value(const struct device *dev, uint32_t *ticks)
 {
-	*ticks = time_us_32();
+	const struct counter_rpi_pico_timer_config *config = dev->config;
+
+	*ticks = timer_time_us_32(config->timer);
 	return 0;
 }
 
@@ -158,6 +160,7 @@ static int counter_rpi_pico_timer_set_guard_period(const struct device *dev, uin
 static void counter_rpi_pico_irq_handle(uint32_t ch, void *arg)
 {
 	struct device *dev = arg;
+	const struct counter_rpi_pico_timer_config *config = dev->config;
 	struct counter_rpi_pico_timer_data *data = dev->data;
 	counter_alarm_callback_t cb = data->ch_data[ch].callback;
 	void *user_data = data->ch_data[ch].user_data;
@@ -165,7 +168,7 @@ static void counter_rpi_pico_irq_handle(uint32_t ch, void *arg)
 	if (cb) {
 		data->ch_data[ch].callback = NULL;
 		data->ch_data[ch].user_data = NULL;
-		cb(dev, ch, time_us_32(), user_data);
+		cb(dev, ch, timer_time_us_32(config->timer), user_data);
 	}
 }
 
diff --git a/drivers/counter/counter_sam0_tc32.c b/drivers/counter/counter_sam0_tc32.c
index 2965fb5c5da..4656000003b 100644
--- a/drivers/counter/counter_sam0_tc32.c
+++ b/drivers/counter/counter_sam0_tc32.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
+ * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,6 +16,8 @@
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(counter_sam0_tc32, CONFIG_COUNTER_LOG_LEVEL);
 
+/* clang-format off */
+
 struct counter_sam0_tc32_ch_data {
 	counter_alarm_callback_t callback;
 	void *user_data;
@@ -31,16 +34,11 @@ struct counter_sam0_tc32_config {
 	struct counter_config_info info;
 	TcCount32 *regs;
 	const struct pinctrl_dev_config *pcfg;
-#ifdef MCLK
 	volatile uint32_t *mclk;
 	uint32_t mclk_mask;
+	uint32_t gclk_gen;
 	uint16_t gclk_id;
-#else
-	uint32_t pm_apbcmask;
-	uint16_t gclk_clkctrl_id;
-#endif
 	uint16_t prescaler;
-
 	void (*irq_config_func)(const struct device *dev);
 };
 
@@ -336,20 +334,15 @@ static int counter_sam0_tc32_initialize(const struct device *dev)
 	TcCount32 *tc = cfg->regs;
 	int retval;
 
-#ifdef MCLK
-	/* Enable the GCLK */
-	GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_GEN_GCLK0 |
-					  GCLK_PCHCTRL_CHEN;
-
-	/* Enable TC clock in MCLK */
 	*cfg->mclk |= cfg->mclk_mask;
-#else
-	/* Enable the GCLK */
-	GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 |
-			    GCLK_CLKCTRL_CLKEN;
 
-	/* Enable clock in PM */
-	PM->APBCMASK.reg |= cfg->pm_apbcmask;
+#ifdef MCLK
+	GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_CHEN
+					| GCLK_PCHCTRL_GEN(cfg->gclk_gen);
+#else
+	GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
+			  | GCLK_CLKCTRL_GEN(cfg->gclk_gen)
+			  | GCLK_CLKCTRL_ID(cfg->gclk_id);
 #endif
 
 	/*
@@ -403,60 +396,57 @@ static DEVICE_API(counter, counter_sam0_tc32_driver_api) = {
 };
 
 
-#ifdef MCLK
-#define COUNTER_SAM0_TC32_CLOCK_CONTROL(n)				\
-	.mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(n),	\
-	.mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)),	\
-	.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),
-#else
-#define COUNTER_SAM0_TC32_CLOCK_CONTROL(n)				\
-	.pm_apbcmask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, pm, bit)),	\
-	.gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id),
-#endif
+#define ASSIGNED_CLOCKS_CELL_BY_NAME						\
+	ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_NAME
 
-#define SAM0_TC32_PRESCALER(n)						\
-	COND_CODE_1(DT_INST_NODE_HAS_PROP(n, prescaler),		\
+#define SAM0_TC32_PRESCALER(n)							\
+	COND_CODE_1(DT_INST_NODE_HAS_PROP(n, prescaler),			\
 		    (DT_INST_PROP(n, prescaler)), (1))
 
-#define COUNTER_SAM0_TC32_DEVICE(n)					\
-	PINCTRL_DT_INST_DEFINE(n);					\
-	static void counter_sam0_tc32_config_##n(const struct device *dev); \
-	static const struct counter_sam0_tc32_config			\
-									\
-	counter_sam0_tc32_dev_config_##n = {				\
-		.info = {						\
-			.max_top_value = UINT32_MAX,			\
-			.freq = SOC_ATMEL_SAM0_GCLK0_FREQ_HZ /		\
-				SAM0_TC32_PRESCALER(n),			\
-			.flags = COUNTER_CONFIG_INFO_COUNT_UP,		\
-			.channels = 1					\
-		},							\
-		.regs = (TcCount32 *)DT_INST_REG_ADDR(n),		\
-		COUNTER_SAM0_TC32_CLOCK_CONTROL(n)			\
-		.prescaler = UTIL_CAT(TC_CTRLA_PRESCALER_DIV,		\
-				      SAM0_TC32_PRESCALER(n)),		\
-		.irq_config_func = &counter_sam0_tc32_config_##n,	\
-		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),		\
-	};								\
-									\
-	static struct counter_sam0_tc32_data counter_sam0_tc32_dev_data_##n;\
-									\
-	DEVICE_DT_INST_DEFINE(n,					\
-			    &counter_sam0_tc32_initialize,		\
-			    NULL,					\
-			    &counter_sam0_tc32_dev_data_##n,		\
-			    &counter_sam0_tc32_dev_config_##n,		\
-			    PRE_KERNEL_1,				\
-			    CONFIG_COUNTER_INIT_PRIORITY,		\
-			    &counter_sam0_tc32_driver_api);		\
-									\
-	static void counter_sam0_tc32_config_##n(const struct device *dev) \
-	{								\
-		IRQ_CONNECT(DT_INST_IRQN(n),				\
-			    DT_INST_IRQ(n, priority),			\
-			    counter_sam0_tc32_isr,			\
-			    DEVICE_DT_INST_GET(n), 0);			\
-		irq_enable(DT_INST_IRQN(n));				\
+#define COUNTER_SAM0_TC32_DEVICE(n)						\
+	PINCTRL_DT_INST_DEFINE(n);						\
+	static void counter_sam0_tc32_config_##n(const struct device *dev);	\
+	static const struct counter_sam0_tc32_config				\
+										\
+	counter_sam0_tc32_dev_config_##n = {					\
+		.info = {							\
+			.max_top_value = UINT32_MAX,				\
+			.freq = SOC_ATMEL_SAM0_GCLK0_FREQ_HZ /			\
+				SAM0_TC32_PRESCALER(n),				\
+			.flags = COUNTER_CONFIG_INFO_COUNT_UP,			\
+			.channels = 1						\
+		},								\
+		.regs = (TcCount32 *)DT_INST_REG_ADDR(n),			\
+		.gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen),		\
+		.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id),		\
+		.mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n),		\
+		.mclk_mask = ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(n, bit),	\
+		.prescaler = UTIL_CAT(TC_CTRLA_PRESCALER_DIV,			\
+				      SAM0_TC32_PRESCALER(n)),			\
+		.irq_config_func = &counter_sam0_tc32_config_##n,		\
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
+	};									\
+										\
+	static struct counter_sam0_tc32_data counter_sam0_tc32_dev_data_##n;	\
+										\
+	DEVICE_DT_INST_DEFINE(n,						\
+			    &counter_sam0_tc32_initialize,			\
+			    NULL,						\
+			    &counter_sam0_tc32_dev_data_##n,			\
+			    &counter_sam0_tc32_dev_config_##n,			\
+			    PRE_KERNEL_1,					\
+			    CONFIG_COUNTER_INIT_PRIORITY,			\
+			    &counter_sam0_tc32_driver_api);			\
+										\
+	static void counter_sam0_tc32_config_##n(const struct device *dev)	\
+	{									\
+		IRQ_CONNECT(DT_INST_IRQN(n),					\
+			    DT_INST_IRQ(n, priority),				\
+			    counter_sam0_tc32_isr,				\
+			    DEVICE_DT_INST_GET(n), 0);				\
+		irq_enable(DT_INST_IRQN(n));					\
 	}
 
 DT_INST_FOREACH_STATUS_OKAY(COUNTER_SAM0_TC32_DEVICE)
+
+/* clang-format on */
diff --git a/drivers/counter/counter_sam_tc.c b/drivers/counter/counter_sam_tc.c
index 16dd6f1fa6a..57ae3c6dd67 100644
--- a/drivers/counter/counter_sam_tc.c
+++ b/drivers/counter/counter_sam_tc.c
@@ -74,14 +74,14 @@ struct counter_sam_dev_data {
 };
 
 static const uint32_t sam_tc_input_freq_table[] = {
-#if defined(CONFIG_SOC_SERIES_SAME70) || defined(CONFIG_SOC_SERIES_SAMV71)
+#if defined(CONFIG_SOC_SERIES_SAMX7X)
 	USEC_PER_SEC,
 	SOC_ATMEL_SAM_MCK_FREQ_HZ / 8,
 	SOC_ATMEL_SAM_MCK_FREQ_HZ / 32,
 	SOC_ATMEL_SAM_MCK_FREQ_HZ / 128,
 	32768,
 #elif defined(CONFIG_SOC_SERIES_SAM4L)
-	USEC_PER_SEC,
+	1024,
 	SOC_ATMEL_SAM_MCK_FREQ_HZ / 2,
 	SOC_ATMEL_SAM_MCK_FREQ_HZ / 8,
 	SOC_ATMEL_SAM_MCK_FREQ_HZ / 32,
diff --git a/drivers/counter/counter_timer_shell.c b/drivers/counter/counter_timer_shell.c
index e9e020e79d4..d1e81e8a9fb 100644
--- a/drivers/counter/counter_timer_shell.c
+++ b/drivers/counter/counter_timer_shell.c
@@ -197,10 +197,15 @@ static int cmd_timer_periodic(const struct shell *shctx, size_t argc, char **arg
 	return 0;
 }
 
+static bool device_is_counter(const struct device *dev)
+{
+	return DEVICE_API_IS(counter, dev);
+}
+
 /* Device name autocompletion support */
 static void device_name_get(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_lookup(idx, "timer");
+	const struct device *dev = shell_device_filter(idx, device_is_counter);
 
 	entry->syntax = (dev != NULL) ? dev->name : NULL;
 	entry->handler = NULL;
diff --git a/drivers/crypto/CMakeLists.txt b/drivers/crypto/CMakeLists.txt
index 59d02d44ad9..5094377abb1 100644
--- a/drivers/crypto/CMakeLists.txt
+++ b/drivers/crypto/CMakeLists.txt
@@ -14,4 +14,5 @@ zephyr_library_sources_ifdef(CONFIG_CRYPTO_IT8XXX2_SHA		crypto_it8xxx2_sha.c)
 zephyr_library_sources_ifdef(CONFIG_CRYPTO_IT8XXX2_SHA_V2	crypto_it8xxx2_sha_v2.c)
 zephyr_library_sources_ifdef(CONFIG_CRYPTO_MCUX_DCP		crypto_mcux_dcp.c)
 zephyr_library_sources_ifdef(CONFIG_CRYPTO_SI32 		crypto_si32.c)
+zephyr_library_sources_ifdef(CONFIG_CRYPTO_CC23X0		crypto_cc23x0.c)
 zephyr_library_link_libraries_ifdef(CONFIG_MBEDTLS mbedTLS)
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index a1b147b12bf..9a7bdb89b54 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -84,5 +84,6 @@ source "drivers/crypto/Kconfig.it8xxx2"
 source "drivers/crypto/Kconfig.mcux_dcp"
 source "drivers/crypto/Kconfig.si32"
 source "drivers/crypto/Kconfig.smartbond"
+source "drivers/crypto/Kconfig.cc23x0"
 
 endif # CRYPTO
diff --git a/drivers/crypto/Kconfig.cc23x0 b/drivers/crypto/Kconfig.cc23x0
new file mode 100644
index 00000000000..8e2cae28536
--- /dev/null
+++ b/drivers/crypto/Kconfig.cc23x0
@@ -0,0 +1,15 @@
+# CC23X0 AES accelerator configuration options
+
+# Copyright (c) 2024 BayLibre, SAS
+# SPDX-License-Identifier: Apache-2.0
+
+config CRYPTO_CC23X0
+	bool "CC23X0 AES accelerator driver"
+	default y
+	depends on DT_HAS_TI_CC23X0_AES_ENABLED
+	help
+	  Enable TI CC23X0 AES accelerator driver.
+	  This driver supports the following modes:
+	  - ECB (Electronic Code Book) encryption only (decryption not supported by the hardware)
+	  - CTR (Counter)
+	  - CCM (CTR with CBC-MAC)
diff --git a/drivers/crypto/crypto_cc23x0.c b/drivers/crypto/crypto_cc23x0.c
new file mode 100644
index 00000000000..09f79567d57
--- /dev/null
+++ b/drivers/crypto/crypto_cc23x0.c
@@ -0,0 +1,689 @@
+/*
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ti_cc23x0_aes
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(crypto_cc23x0, CONFIG_CRYPTO_LOG_LEVEL);
+
+#include <zephyr/crypto/crypto.h>
+#include <zephyr/device.h>
+#include <zephyr/irq.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/util.h>
+
+#include <string.h>
+
+#include <driverlib/aes.h>
+#include <driverlib/clkctl.h>
+
+#define CRYPTO_CC23_CAP		(CAP_RAW_KEY | CAP_SEPARATE_IO_BUFS | \
+				 CAP_SYNC_OPS | CAP_NO_IV_PREFIX)
+
+#define CRYPTO_CC23_INT_MASK	AES_IMASK_AESDONE
+
+/* CCM mode: see https://datatracker.ietf.org/doc/html/rfc3610 for reference */
+#define CCM_CC23_MSG_LEN_SIZE_MIN	2
+#define CCM_CC23_MSG_LEN_SIZE_MAX	8
+
+#define CCM_CC23_NONCE_LEN_SIZE_MIN	(AES_BLOCK_SIZE - CCM_CC23_MSG_LEN_SIZE_MAX - 1)
+#define CCM_CC23_NONCE_LEN_SIZE_MAX	(AES_BLOCK_SIZE - CCM_CC23_MSG_LEN_SIZE_MIN - 1)
+
+#define CCM_CC23_AD_LEN_SIZE		2
+#define CCM_CC23_AD_DATA_SIZE_MAX	(AES_BLOCK_SIZE - CCM_CC23_AD_LEN_SIZE)
+
+#define CCM_CC23_TAG_SIZE_MIN		4
+#define CCM_CC23_TAG_SIZE_MAX		16
+
+#define CCM_CC23_BYTE_GET(idx, val)	FIELD_GET(0xff << ((idx) << 3), (val))
+
+#define CCM_CC23_B0_GET(ad_len, tag_len, len_size) \
+			(((ad_len) ? 1 << 6 : 0) + (((tag_len) - 2) << 2) + ((len_size) - 1))
+
+/*
+ * The Finite State Machine (FSM) processes the data in a column-fashioned way,
+ * processing 2 columns/cycle, completing 10 rounds in 20 cycles. With three cycles
+ * of pre-processing, the execution/encryption time is 23 cycles.
+ */
+#define CRYPTO_CC23_OP_TIMEOUT	K_CYC(23 << 1)
+
+struct crypto_cc23x0_data {
+	struct k_mutex device_mutex;
+	struct k_sem aes_done;
+};
+
+static void crypto_cc23x0_isr(const struct device *dev)
+{
+	struct crypto_cc23x0_data *data = dev->data;
+	uint32_t status;
+
+	status = AESGetMaskedInterruptStatus();
+
+	if (status & AES_IMASK_AESDONE) {
+		k_sem_give(&data->aes_done);
+	}
+
+	AESClearInterrupt(status);
+}
+
+static void crypto_cc23x0_cleanup(void)
+{
+	AESClearAUTOCFGTrigger();
+	AESClearAUTOCFGBusHalt();
+	AESClearTXTAndBUF();
+}
+
+static int crypto_cc23x0_ecb_encrypt(struct cipher_ctx *ctx, struct cipher_pkt *pkt)
+{
+	const struct device *dev = ctx->device;
+	struct crypto_cc23x0_data *data = dev->data;
+	int in_bytes_processed = 0;
+	int out_bytes_processed = 0;
+	int ret;
+
+	if (pkt->out_buf_max < ROUND_UP(pkt->in_len, AES_BLOCK_SIZE)) {
+		LOG_ERR("Output buffer too small");
+		return -EINVAL;
+	}
+
+	k_mutex_lock(&data->device_mutex, K_FOREVER);
+
+	/* Load key */
+	AESWriteKEY(ctx->key.bit_stream);
+
+	/* Configure source buffer and encryption triggers */
+	AESSetAUTOCFG(AES_AUTOCFG_AESSRC_BUF |
+		      AES_AUTOCFG_TRGAES_RDTXT3 |
+		      AES_AUTOCFG_TRGAES_WRBUF3S);
+
+	/* Write first block of input to trigger encryption */
+	AESWriteBUF(pkt->in_buf);
+	in_bytes_processed += AES_BLOCK_SIZE;
+
+	do {
+		if (in_bytes_processed < pkt->in_len) {
+			/* Preload next input block */
+			AESWriteBUF(&pkt->in_buf[in_bytes_processed]);
+			in_bytes_processed += AES_BLOCK_SIZE;
+		} else {
+			/* Avoid triggering a spurious encryption upon reading the final output */
+			AESClearAUTOCFGTrigger();
+		}
+
+		/* Wait for AES operation completion */
+		ret = k_sem_take(&data->aes_done, CRYPTO_CC23_OP_TIMEOUT);
+		if (ret) {
+			goto cleanup;
+		}
+
+		LOG_DBG("AES operation completed");
+
+		/*
+		 * Read output and trigger encryption of next input that was
+		 * preloaded at the start of this loop.
+		 */
+		AESReadTXT(&pkt->out_buf[out_bytes_processed]);
+		out_bytes_processed += AES_BLOCK_SIZE;
+	} while (out_bytes_processed < pkt->in_len);
+
+cleanup:
+	crypto_cc23x0_cleanup();
+	k_mutex_unlock(&data->device_mutex);
+	pkt->out_len = out_bytes_processed;
+
+	return ret;
+}
+
+static int crypto_cc23x0_ctr(struct cipher_ctx *ctx, struct cipher_pkt *pkt, uint8_t *iv)
+{
+	const struct device *dev = ctx->device;
+	struct crypto_cc23x0_data *data = dev->data;
+	uint32_t ctr_len = ctx->mode_params.ctr_info.ctr_len >> 3;
+	uint8_t ctr[AES_BLOCK_SIZE] = { 0 };
+	uint8_t last_buf[AES_BLOCK_SIZE] = { 0 };
+	int bytes_remaining = pkt->in_len;
+	int bytes_processed = 0;
+	int block_size;
+	int iv_len;
+	int ret;
+
+	if (pkt->out_buf_max < ROUND_UP(pkt->in_len, AES_BLOCK_SIZE)) {
+		LOG_ERR("Output buffer too small");
+		return -EINVAL;
+	}
+
+	k_mutex_lock(&data->device_mutex, K_FOREVER);
+
+	/* Load key */
+	AESWriteKEY(ctx->key.bit_stream);
+
+	/* Configure source buffer and encryption triggers */
+	AESSetAUTOCFG(AES_AUTOCFG_AESSRC_BUF |
+		      AES_AUTOCFG_TRGAES_RDTXT3 |
+		      AES_AUTOCFG_TRGAES_WRBUF3S |
+		      AES_AUTOCFG_CTRENDN_BIGENDIAN |
+		      AES_AUTOCFG_CTRSIZE_CTR128);
+
+	/* Write the counter value to the AES engine to trigger first encryption */
+	iv_len = (ctx->ops.cipher_mode == CRYPTO_CIPHER_MODE_CCM) ?
+		  AES_BLOCK_SIZE : (ctx->keylen - ctr_len);
+	memcpy(ctr, iv, iv_len);
+	AESWriteBUF(ctr);
+
+	do {
+		/* Wait for AES operation completion */
+		ret = k_sem_take(&data->aes_done, CRYPTO_CC23_OP_TIMEOUT);
+		if (ret) {
+			goto cleanup;
+		}
+
+		LOG_DBG("AES operation completed");
+
+		/* XOR input data with encrypted counter block to form ciphertext */
+		if (bytes_remaining > AES_BLOCK_SIZE) {
+			block_size = AES_BLOCK_SIZE;
+			AESWriteTXTXOR(&pkt->in_buf[bytes_processed]);
+		} else {
+			block_size = bytes_remaining;
+			memcpy(last_buf, &pkt->in_buf[bytes_processed], block_size);
+			AESWriteTXTXOR(last_buf);
+
+			/*
+			 * Do not auto-trigger encrypt and increment of counter
+			 * value for last block of data.
+			 */
+			AESClearAUTOCFGTrigger();
+		}
+
+		/*
+		 * Read the output ciphertext and trigger the encryption
+		 * of the next counter block
+		 */
+		AESReadTXT(&pkt->out_buf[bytes_processed]);
+
+		bytes_processed += block_size;
+		bytes_remaining -= block_size;
+	} while (bytes_remaining > 0);
+
+cleanup:
+	crypto_cc23x0_cleanup();
+	k_mutex_unlock(&data->device_mutex);
+	pkt->out_len = bytes_processed;
+
+	return ret;
+}
+
+static int crypto_cc23x0_cmac(struct cipher_ctx *ctx, struct cipher_pkt *pkt,
+			      uint8_t *b0, uint8_t *b1)
+{
+	const struct device *dev = ctx->device;
+	struct crypto_cc23x0_data *data = dev->data;
+	uint32_t iv[AES_BLOCK_SIZE_WORDS] = { 0 };
+	uint8_t last_buf[AES_BLOCK_SIZE] = { 0 };
+	int bytes_remaining = pkt->in_len;
+	int bytes_processed = 0;
+	int block_size;
+	int ret;
+
+	if (pkt->out_buf_max < AES_BLOCK_SIZE) {
+		LOG_ERR("Output buffer too small");
+		return -EINVAL;
+	}
+
+	k_mutex_lock(&data->device_mutex, K_FOREVER);
+
+	/* Load key */
+	AESWriteKEY(ctx->key.bit_stream);
+
+	/* Configure source buffer and encryption triggers */
+	AESSetAUTOCFG(AES_AUTOCFG_AESSRC_TXTXBUF |
+		      AES_AUTOCFG_TRGAES_WRBUF3 |
+		      AES_AUTOCFG_BUSHALT_EN);
+
+	/* Write zero'd IV */
+	AESWriteIV32(iv);
+
+	if (b0) {
+		/* Load input block */
+		AESWriteBUF(b0);
+
+		/* Wait for AES operation completion */
+		ret = k_sem_take(&data->aes_done, CRYPTO_CC23_OP_TIMEOUT);
+		if (ret) {
+			goto out;
+		}
+
+		LOG_DBG("AES operation completed (block 0)");
+	}
+
+	if (b1) {
+		/* Load input block */
+		AESWriteBUF(b1);
+
+		/* Wait for AES operation completion */
+		ret = k_sem_take(&data->aes_done, CRYPTO_CC23_OP_TIMEOUT);
+		if (ret) {
+			goto out;
+		}
+
+		LOG_DBG("AES operation completed (block 1)");
+	}
+
+	do {
+		/* Load input block */
+		if (bytes_remaining >= AES_BLOCK_SIZE) {
+			block_size = AES_BLOCK_SIZE;
+			AESWriteBUF(&pkt->in_buf[bytes_processed]);
+		} else {
+			block_size = bytes_remaining;
+			memcpy(last_buf, &pkt->in_buf[bytes_processed], block_size);
+			AESWriteBUF(last_buf);
+		}
+
+		/* Wait for AES operation completion */
+		ret = k_sem_take(&data->aes_done, CRYPTO_CC23_OP_TIMEOUT);
+		if (ret) {
+			goto out;
+		}
+
+		LOG_DBG("AES operation completed (data)");
+
+		bytes_processed += block_size;
+		bytes_remaining -= block_size;
+	} while (bytes_remaining > 0);
+
+	/* Read tag */
+	AESReadTag(pkt->out_buf);
+
+out:
+	crypto_cc23x0_cleanup();
+	k_mutex_unlock(&data->device_mutex);
+	pkt->out_len = bytes_processed;
+
+	return ret;
+}
+
+static int crypto_cc23x0_ccm_check_param(struct cipher_ctx *ctx, struct cipher_aead_pkt *aead_op)
+{
+	uint16_t ad_len = aead_op->ad_len;
+	uint16_t tag_len = ctx->mode_params.ccm_info.tag_len;
+	uint16_t nonce_len = ctx->mode_params.ccm_info.nonce_len;
+
+	if (aead_op->pkt->out_buf_max < ROUND_UP(aead_op->pkt->in_len, AES_BLOCK_SIZE)) {
+		LOG_ERR("Output buffer too small");
+		return -EINVAL;
+	}
+
+	if (tag_len < CCM_CC23_TAG_SIZE_MIN || tag_len > CCM_CC23_TAG_SIZE_MAX || tag_len & 1) {
+		LOG_ERR("CCM parameter invalid (tag_len must be an even value from %d to %d)",
+			CCM_CC23_TAG_SIZE_MIN, CCM_CC23_TAG_SIZE_MAX);
+		return -EINVAL;
+	}
+
+	if (nonce_len < CCM_CC23_NONCE_LEN_SIZE_MIN || nonce_len > CCM_CC23_NONCE_LEN_SIZE_MAX) {
+		LOG_ERR("CCM parameter invalid (nonce_len must be a value from %d to %d)",
+			CCM_CC23_NONCE_LEN_SIZE_MIN, CCM_CC23_NONCE_LEN_SIZE_MAX);
+		return -EINVAL;
+	}
+
+	if (ad_len > CCM_CC23_AD_DATA_SIZE_MAX) {
+		LOG_ERR("CCM parameter invalid (ad_len max = %d)", CCM_CC23_AD_DATA_SIZE_MAX);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int crypto_cc23x0_ccm_encrypt(struct cipher_ctx *ctx,
+				     struct cipher_aead_pkt *aead_op, uint8_t *nonce)
+{
+	struct cipher_pkt tag_pkt = { 0 };
+	struct cipher_pkt data_pkt = { 0 };
+	uint8_t tag[AES_BLOCK_SIZE] = { 0 };
+	uint8_t b0[AES_BLOCK_SIZE] = { 0 };
+	uint8_t b1[AES_BLOCK_SIZE] = { 0 };
+	uint8_t ctri[AES_BLOCK_SIZE] = { 0 };
+	uint32_t msg_len = aead_op->pkt->in_len;
+	uint16_t ad_len = aead_op->ad_len;
+	uint16_t tag_len = ctx->mode_params.ccm_info.tag_len;
+	uint16_t nonce_len = ctx->mode_params.ccm_info.nonce_len;
+	uint8_t len_size = AES_BLOCK_SIZE - nonce_len - 1;
+	int ret;
+	int i;
+
+	ret = crypto_cc23x0_ccm_check_param(ctx, aead_op);
+	if (ret) {
+		return ret;
+	}
+
+	/*
+	 * Build the first block B0 required for CMAC computation.
+	 * ============================================
+	 * Block B0 formatting per RFC3610:
+	 *    Octet Number   Contents
+	 *    ------------   ---------
+	 *    0		     Flags
+	 *    1 ... 15-L     Nonce N
+	 *    16-L ... 15    l(m), MSB first
+	 *
+	 * Flags in octet 0 of B0:
+	 *    Bit Number   Contents
+	 *    ----------   ----------------------
+	 *    7		   Reserved (always zero)
+	 *    6		   Adata = 1 if l(a) > 0, 0 otherwise
+	 *    5 ... 3	   M' = (M - 2) / 2 where M = Number of octets in authentication field
+	 *    2 ... 0	   L' = L - 1 where L = Number of octets in length field
+	 * ============================================
+	 */
+	b0[0] = CCM_CC23_B0_GET(aead_op->ad_len, tag_len, len_size);
+
+	for (i = 0 ; i < sizeof(msg_len) ; i++) {
+		b0[AES_BLOCK_SIZE - 1 - i] = CCM_CC23_BYTE_GET(i, msg_len);
+	}
+
+	memcpy(&b0[1], nonce, nonce_len);
+
+	/*
+	 * Build the second block B1 for additional data (header).
+	 * ============================================
+	 * Block B1 formatting per RFC3610, for 0 < l(a) < (2^16 - 2^8):
+	 *    Octet Number   Contents
+	 *    ------------   ---------
+	 *    0 ... 1	     l(a), MSB first
+	 *    2 ... N	     Header data
+	 *    N+1 ... 15     Zero padding
+	 * ============================================
+	 */
+	for (i = 0 ; i < sizeof(ad_len) ; i++) {
+		b1[CCM_CC23_AD_LEN_SIZE - 1 - i] = CCM_CC23_BYTE_GET(i, ad_len);
+	}
+
+	memcpy(&b1[CCM_CC23_AD_LEN_SIZE], aead_op->ad, ad_len);
+
+	/* Calculate the authentication tag by passing B0, B1, and data to CMAC function. */
+	LOG_DBG("Compute CMAC");
+
+	data_pkt.in_buf = aead_op->pkt->in_buf;
+	data_pkt.in_len = aead_op->pkt->in_len;
+	data_pkt.out_buf = tag;
+	data_pkt.out_buf_max = AES_BLOCK_SIZE;
+
+	ret = crypto_cc23x0_cmac(ctx, &data_pkt, b0, b1);
+	if (ret) {
+		return ret;
+	}
+
+	/*
+	 * Prepare the initial counter block CTR1 for the CTR mode.
+	 * ============================================
+	 * Block CTRi formatting per RFC3610:
+	 *    Octet Number   Contents
+	 *    ------------   ---------
+	 *    0              Flags
+	 *    1 ... 15-L     Nonce N
+	 *    16-L ... 15    Counter i, MSB first
+	 *
+	 * Flags in octet 0 of CTR0:
+	 *    Bit Number   Contents
+	 *    ----------   ----------------------
+	 *    7            Reserved (always zero)
+	 *    6            Reserved (always zero)
+	 *    5 ... 3      Zero
+	 *    2 ... 0      L' = L - 1 where L = Number of octets in length field
+	 * ============================================
+	 */
+	ctri[0] = len_size - 1;
+	memcpy(&ctri[1], nonce, nonce_len);
+	ctri[AES_BLOCK_SIZE - 1] = 1;
+
+	/* Encrypt the data using the counter block CTR1. */
+	LOG_DBG("Encrypt data");
+
+	ret = crypto_cc23x0_ctr(ctx, aead_op->pkt, ctri);
+	if (ret) {
+		return ret;
+	}
+
+	/* Encrypt the authentication tag using the counter block CTR0. */
+	LOG_DBG("Encrypt tag");
+
+	ctri[AES_BLOCK_SIZE - 1] = 0;
+
+	tag_pkt.in_buf = tag;
+	tag_pkt.in_len = tag_len;
+	tag_pkt.out_buf = aead_op->tag;
+	tag_pkt.out_buf_max = AES_BLOCK_SIZE;
+
+	return crypto_cc23x0_ctr(ctx, &tag_pkt, ctri);
+}
+
+static int crypto_cc23x0_ccm_decrypt(struct cipher_ctx *ctx,
+				     struct cipher_aead_pkt *aead_op, uint8_t *nonce)
+{
+	struct cipher_pkt tag_pkt = { 0 };
+	struct cipher_pkt data_pkt = { 0 };
+	uint8_t enc_tag[AES_BLOCK_SIZE] = { 0 };
+	uint8_t calc_tag[AES_BLOCK_SIZE] = { 0 };
+	uint8_t b0[AES_BLOCK_SIZE] = { 0 };
+	uint8_t b1[AES_BLOCK_SIZE] = { 0 };
+	uint8_t ctri[AES_BLOCK_SIZE] = { 0 };
+	uint32_t msg_len = aead_op->pkt->in_len;
+	uint16_t ad_len = aead_op->ad_len;
+	uint16_t tag_len = ctx->mode_params.ccm_info.tag_len;
+	uint16_t nonce_len = ctx->mode_params.ccm_info.nonce_len;
+	uint8_t len_size = AES_BLOCK_SIZE - nonce_len - 1;
+	int ret;
+	int i;
+
+	ret = crypto_cc23x0_ccm_check_param(ctx, aead_op);
+	if (ret) {
+		return ret;
+	}
+
+	/* Prepare the initial counter block CTR1 for the CTR mode. */
+	ctri[0] = len_size - 1;
+	memcpy(&ctri[1], nonce, nonce_len);
+	ctri[AES_BLOCK_SIZE - 1] = 1;
+
+	/* Decrypt the data using the counter block CTR1. */
+	LOG_DBG("Decrypt data");
+
+	ret = crypto_cc23x0_ctr(ctx, aead_op->pkt, ctri);
+	if (ret) {
+		goto clear_out_buf;
+	}
+
+	/* Build the first block B0 required for CMAC computation. */
+	b0[0] = CCM_CC23_B0_GET(aead_op->ad_len, tag_len, len_size);
+
+	for (i = 0 ; i < sizeof(msg_len) ; i++) {
+		b0[AES_BLOCK_SIZE - 1 - i] = CCM_CC23_BYTE_GET(i, msg_len);
+	}
+
+	memcpy(&b0[1], nonce, nonce_len);
+
+	/* Build the second block B1 for additional data (header). */
+	for (i = 0 ; i < sizeof(ad_len) ; i++) {
+		b1[CCM_CC23_AD_LEN_SIZE - 1 - i] = CCM_CC23_BYTE_GET(i, ad_len);
+	}
+
+	memcpy(&b1[CCM_CC23_AD_LEN_SIZE], aead_op->ad, ad_len);
+
+	/*
+	 * Calculate the authentication tag by passing B0, B1, and decrypted data
+	 * to CMAC function.
+	 */
+	LOG_DBG("Compute CMAC");
+
+	data_pkt.in_buf = aead_op->pkt->out_buf;
+	data_pkt.in_len = aead_op->pkt->out_len;
+	data_pkt.out_buf = calc_tag;
+	data_pkt.out_buf_max = AES_BLOCK_SIZE;
+
+	ret = crypto_cc23x0_cmac(ctx, &data_pkt, b0, b1);
+	if (ret) {
+		goto clear_out_buf;
+	}
+
+	/* Encrypt the recalculated authentication tag using the counter block CTR0. */
+	LOG_DBG("Encrypt tag");
+
+	ctri[AES_BLOCK_SIZE - 1] = 0;
+
+	tag_pkt.in_buf = calc_tag;
+	tag_pkt.in_len = tag_len;
+	tag_pkt.out_buf = enc_tag;
+	tag_pkt.out_buf_max = AES_BLOCK_SIZE;
+
+	ret = crypto_cc23x0_ctr(ctx, &tag_pkt, ctri);
+	if (ret) {
+		goto clear_out_buf;
+	}
+
+	/*
+	 * Compare the recalculated encrypted authentication tag with the one supplied by the app.
+	 * If they match, the decrypted data is returned. Otherwise, the authentication has failed
+	 * and the output buffer is zero'd.
+	 */
+	LOG_DBG("Check tag");
+
+	if (!memcmp(enc_tag, aead_op->tag, tag_len)) {
+		return 0;
+	}
+
+	LOG_ERR("Invalid tag");
+	ret = -EINVAL;
+
+clear_out_buf:
+	memset(aead_op->pkt->out_buf, 0, msg_len);
+
+	return ret;
+}
+
+static int crypto_cc23x0_session_setup(const struct device *dev,
+				       struct cipher_ctx *ctx,
+				       enum cipher_algo algo,
+				       enum cipher_mode mode,
+				       enum cipher_op op_type)
+{
+	if (ctx->flags & ~(CRYPTO_CC23_CAP)) {
+		LOG_ERR("Unsupported feature");
+		return -EINVAL;
+	}
+
+	if (algo != CRYPTO_CIPHER_ALGO_AES) {
+		LOG_ERR("Unsupported algo");
+		return -EINVAL;
+	}
+
+	if (mode != CRYPTO_CIPHER_MODE_ECB &&
+	    mode != CRYPTO_CIPHER_MODE_CTR &&
+	    mode != CRYPTO_CIPHER_MODE_CCM) {
+		LOG_ERR("Unsupported mode");
+		return -EINVAL;
+	}
+
+	if (ctx->keylen != 16U) {
+		LOG_ERR("%u key size is not supported", ctx->keylen);
+		return -EINVAL;
+	}
+
+	if (!ctx->key.bit_stream) {
+		LOG_ERR("No key provided");
+		return -EINVAL;
+	}
+
+	if (op_type == CRYPTO_CIPHER_OP_ENCRYPT) {
+		switch (mode) {
+		case CRYPTO_CIPHER_MODE_ECB:
+			ctx->ops.block_crypt_hndlr = crypto_cc23x0_ecb_encrypt;
+			break;
+		case CRYPTO_CIPHER_MODE_CTR:
+			ctx->ops.ctr_crypt_hndlr = crypto_cc23x0_ctr;
+			break;
+		case CRYPTO_CIPHER_MODE_CCM:
+			ctx->ops.ccm_crypt_hndlr = crypto_cc23x0_ccm_encrypt;
+			break;
+		default:
+			return -EINVAL;
+		}
+	} else {
+		switch (mode) {
+		case CRYPTO_CIPHER_MODE_ECB:
+			LOG_ERR("ECB decryption not supported by the hardware");
+			return -EINVAL;
+		case CRYPTO_CIPHER_MODE_CTR:
+			ctx->ops.ctr_crypt_hndlr = crypto_cc23x0_ctr;
+			break;
+		case CRYPTO_CIPHER_MODE_CCM:
+			ctx->ops.ccm_crypt_hndlr = crypto_cc23x0_ccm_decrypt;
+			break;
+		default:
+			return -EINVAL;
+		}
+	}
+
+	ctx->ops.cipher_mode = mode;
+	ctx->device = dev;
+
+	return 0;
+}
+
+static int crypto_cc23x0_session_free(const struct device *dev,
+				      struct cipher_ctx *ctx)
+{
+	ARG_UNUSED(dev);
+
+	ctx->ops.ccm_crypt_hndlr = NULL;
+	ctx->device = NULL;
+
+	return 0;
+}
+
+static int crypto_cc23x0_query_caps(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return CRYPTO_CC23_CAP;
+}
+
+static int crypto_cc23x0_init(const struct device *dev)
+{
+	struct crypto_cc23x0_data *data = dev->data;
+
+	IRQ_CONNECT(DT_INST_IRQN(0),
+		    DT_INST_IRQ(0, priority),
+		    crypto_cc23x0_isr,
+		    DEVICE_DT_INST_GET(0),
+		    0);
+	irq_enable(DT_INST_IRQN(0));
+
+	CLKCTLEnable(CLKCTL_BASE, CLKCTL_LAES);
+
+	AESSetIMASK(CRYPTO_CC23_INT_MASK);
+
+	k_mutex_init(&data->device_mutex);
+	k_sem_init(&data->aes_done, 0, 1);
+
+	return 0;
+}
+
+static DEVICE_API(crypto, crypto_enc_funcs) = {
+	.cipher_begin_session = crypto_cc23x0_session_setup,
+	.cipher_free_session = crypto_cc23x0_session_free,
+	.query_hw_caps = crypto_cc23x0_query_caps,
+};
+
+static struct crypto_cc23x0_data crypto_cc23x0_dev_data;
+
+DEVICE_DT_INST_DEFINE(0,
+		      crypto_cc23x0_init,
+		      NULL,
+		      &crypto_cc23x0_dev_data,
+		      NULL,
+		      POST_KERNEL,
+		      CONFIG_CRYPTO_INIT_PRIORITY,
+		      &crypto_enc_funcs);
diff --git a/drivers/crypto/crypto_stm32.c b/drivers/crypto/crypto_stm32.c
index c453e3a0e65..b1c7cf59b03 100644
--- a/drivers/crypto/crypto_stm32.c
+++ b/drivers/crypto/crypto_stm32.c
@@ -123,7 +123,7 @@ static int do_aes(struct cipher_ctx *ctx, hal_cryp_aes_op_func_t fn, uint8_t *in
 
 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32l4_aes)
 	/* Device is initialized from the configuration in the encryption/decryption function
-	 * called bellow.
+	 * called below.
 	 */
 	memcpy(&data->hcryp.Init, &session->config, sizeof(session->config));
 #else
diff --git a/drivers/dac/CMakeLists.txt b/drivers/dac/CMakeLists.txt
index eec91be800a..cd719fa7185 100644
--- a/drivers/dac/CMakeLists.txt
+++ b/drivers/dac/CMakeLists.txt
@@ -10,6 +10,7 @@ zephyr_library_sources_ifdef(CONFIG_DAC_MCUX_DAC32	dac_mcux_dac32.c)
 zephyr_library_sources_ifdef(CONFIG_DAC_STM32		dac_stm32.c)
 zephyr_library_sources_ifdef(CONFIG_DAC_SAM		dac_sam.c)
 zephyr_library_sources_ifdef(CONFIG_DAC_SAM0		dac_sam0.c)
+zephyr_library_sources_ifdef(CONFIG_DAC_DAC161S997	dac_dac161s997.c)
 zephyr_library_sources_ifdef(CONFIG_DAC_DACX0501	dac_dacx0501.c)
 zephyr_library_sources_ifdef(CONFIG_DAC_DACX0508	dac_dacx0508.c)
 zephyr_library_sources_ifdef(CONFIG_DAC_DACX3608	dac_dacx3608.c)
@@ -25,3 +26,5 @@ zephyr_library_sources_ifdef(CONFIG_DAC_AD569X		dac_ad569x.c)
 zephyr_library_sources_ifdef(CONFIG_USERSPACE		dac_handlers.c)
 zephyr_library_sources_ifdef(CONFIG_DAC_MCUX_GAU	dac_mcux_gau.c)
 zephyr_library_sources_ifdef(CONFIG_DAC_TEST		dac_test.c)
+zephyr_library_sources_ifdef(CONFIG_DAC_MAX22017	dac_max22017.c)
+zephyr_library_sources_ifdef(CONFIG_DAC_RENESAS_RA	dac_renesas_ra.c)
diff --git a/drivers/dac/Kconfig b/drivers/dac/Kconfig
index 26b17f1a31d..21c2f174c9c 100644
--- a/drivers/dac/Kconfig
+++ b/drivers/dac/Kconfig
@@ -37,6 +37,8 @@ source "drivers/dac/Kconfig.sam"
 
 source "drivers/dac/Kconfig.sam0"
 
+source "drivers/dac/Kconfig.dac161s997"
+
 source "drivers/dac/Kconfig.dacx0501"
 
 source "drivers/dac/Kconfig.dacx0508"
@@ -61,4 +63,8 @@ source "drivers/dac/Kconfig.ad569x"
 
 source "drivers/dac/Kconfig.test"
 
+source "drivers/dac/Kconfig.max22017"
+
+source "drivers/dac/Kconfig.renesas_ra"
+
 endif # DAC
diff --git a/drivers/dac/Kconfig.dac161s997 b/drivers/dac/Kconfig.dac161s997
new file mode 100644
index 00000000000..c055f00fd49
--- /dev/null
+++ b/drivers/dac/Kconfig.dac161s997
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Vitrolife A/S
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config DAC_DAC161S997
+	bool "TI DAC161S997 DAC driver"
+	default y
+	select SPI
+	depends on DT_HAS_TI_DAC161S997_ENABLED
+	help
+	  Enable the driver for the TI DAC161S997.
diff --git a/drivers/dac/Kconfig.max22017 b/drivers/dac/Kconfig.max22017
new file mode 100644
index 00000000000..d7a46229f02
--- /dev/null
+++ b/drivers/dac/Kconfig.max22017
@@ -0,0 +1,21 @@
+# Copyright (c) 2024 Analog Devices Inc.
+# Copyright (c) 2024 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+config DAC_MAX22017
+	bool "Analog Devices MAX22017 DAC"
+	default y
+	depends on DT_HAS_ADI_MAX22017_DAC_ENABLED
+	select MFD
+	help
+	  Enable the driver for the Analog Devices MAX22017 DAC
+
+if DAC_MAX22017
+
+config DAC_MAX22017_INIT_PRIORITY
+	int "Init priority"
+	default 80
+	help
+	  Analog Devices MAX22017 DAC device driver initialization priority.
+
+endif # DAC_MAX22017
diff --git a/drivers/dac/Kconfig.renesas_ra b/drivers/dac/Kconfig.renesas_ra
new file mode 100644
index 00000000000..40e9ce68121
--- /dev/null
+++ b/drivers/dac/Kconfig.renesas_ra
@@ -0,0 +1,43 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config DAC_RENESAS_RA
+	bool "Renesas RA DAC"
+	default y
+	depends on DT_HAS_RENESAS_RA_DAC_ENABLED
+	select USE_RA_FSP_DAC
+	select PINCTRL
+	help
+	  Enable Renesas RA DAC Driver.
+
+if DAC_RENESAS_RA
+config DAC_RENESAS_RA_DA_AD_SYNCHRONIZE
+	bool "D/A A/D Synchronous Conversion"
+	help
+	  - n: Do not synchronize DAC12 with ADC (unit 1) operation
+	  (disable interference reduction between D/A and A/D conversion).
+	  - y: Synchronize DAC12 with ADC (unit 1) operation
+	  (enable interference reduction between D/A and A/D conversion).
+
+choice DAC_RENESAS_RA_DAVREFCR
+	prompt "D/A Reference Voltage"
+	depends on $(dt_nodelabel_bool_prop,dac_global,has-davrefcr)
+	default DAC_RENESAS_RA_DAVREFCR_AVCC0_AVSS0
+
+config DAC_RENESAS_RA_DAVREFCR_NONE
+	bool "No reference voltage selected"
+	help
+	  No reference voltage selected
+
+config DAC_RENESAS_RA_DAVREFCR_AVCC0_AVSS0
+	bool "Using AVCC0/AVSS0 for reference voltage source"
+	help
+	  AVCC0/AVSS0 selected
+
+config DAC_RENESAS_RA_DAVREFCR_VREFH_VREFL
+	bool "Using VREFH/VREFL for reference voltage source"
+	help
+	  VREFH/VREFL selected
+
+endchoice #DAC_RENESAS_RA_DAVREFCR
+endif # DAC_RENESAS_RA
diff --git a/drivers/dac/dac_dac161s997.c b/drivers/dac/dac_dac161s997.c
new file mode 100644
index 00000000000..7d7666c68b7
--- /dev/null
+++ b/drivers/dac/dac_dac161s997.c
@@ -0,0 +1,309 @@
+/*
+ * Copyright (c) 2025 Vitrolife A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ti_dac161s997
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/drivers/dac.h>
+#include <zephyr/drivers/dac/dac161s997.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util_macro.h>
+
+LOG_MODULE_REGISTER(dac_dac161s997, CONFIG_DAC_LOG_LEVEL);
+
+#define DAC161S997_CHANNELS   1
+#define DAC161S997_RESOLUTION 16
+
+enum dac161s997_reg {
+	DAC161S997_REG_XFER = 1,
+	DAC161S997_REG_NOP,
+	DAC161S997_REG_WR_MODE,
+	DAC161S997_REG_DACCODE,
+	DAC161S997_REG_ERR_CONFIG,
+	DAC161S997_REG_ERR_LOW,
+	DAC161S997_REG_ERR_HIGH,
+	DAC161S997_REG_RESET,
+	DAC161S997_REG_STATUS,
+};
+
+struct dac161s997_config {
+	struct spi_dt_spec bus;
+	const struct gpio_dt_spec gpio_errb;
+};
+
+struct dac161s997_data {
+	const struct device *dev;
+	struct k_sem lock;
+	struct gpio_callback gpio_errb_cb;
+	struct k_work gpio_errb_work;
+	dac161s997_error_callback_t error_cb;
+};
+
+int dac161s997_set_error_callback(const struct device *dev, dac161s997_error_callback_t cb)
+{
+	const struct dac161s997_config *config = dev->config;
+	struct dac161s997_data *data = dev->data;
+	int ret;
+
+	ret = k_sem_take(&data->lock, K_FOREVER);
+	if (ret != 0) {
+		return ret;
+	}
+
+	if (config->gpio_errb.port != NULL) {
+		data->error_cb = cb;
+	} else {
+		ret = -ENOTSUP;
+	}
+
+	k_sem_give(&data->lock);
+
+	return ret;
+}
+
+static int dac161s997_read_reg(const struct device *dev, enum dac161s997_reg reg, uint16_t *val)
+{
+	const struct dac161s997_config *config = dev->config;
+	int res;
+
+	uint8_t reg_read = BIT(7) | reg;
+	uint8_t tx_buf[3] = {reg_read};
+	const struct spi_buf tx_buffers[] = {{.buf = tx_buf, .len = ARRAY_SIZE(tx_buf)}};
+	const struct spi_buf_set tx_bufs = {.buffers = tx_buffers, .count = ARRAY_SIZE(tx_buffers)};
+	uint8_t rx_buf[3];
+	const struct spi_buf rx_buffers[] = {{.buf = rx_buf, .len = ARRAY_SIZE(rx_buf)}};
+	const struct spi_buf_set rx_bufs = {.buffers = rx_buffers, .count = ARRAY_SIZE(rx_buffers)};
+
+	res = spi_write_dt(&config->bus, &tx_bufs);
+	if (res != 0) {
+		LOG_ERR("Read 0x%02x setup failed: %d", reg, res);
+		return res;
+	}
+
+	tx_buf[0] = DAC161S997_REG_NOP;
+	res = spi_transceive_dt(&config->bus, &tx_bufs, &rx_bufs);
+	if (res != 0) {
+		LOG_ERR("Read from 0x%02x failed: %d", reg, res);
+		return res;
+	}
+
+	if (reg_read != rx_buf[0]) {
+		LOG_ERR("Read 0x%02x addr mismatch: 0x%02x", reg_read, rx_buf[0]);
+		return -EIO;
+	}
+
+	*val = sys_get_be16(&rx_buf[1]);
+
+	LOG_DBG("Reg 0x%02x: 0x%02x", reg, *val);
+
+	return 0;
+}
+
+static int dac161s997_write_reg(const struct device *dev, enum dac161s997_reg reg, uint16_t val)
+{
+	const struct dac161s997_config *config = dev->config;
+
+	uint8_t tx_buf[3] = {reg, val >> 8, val};
+	const struct spi_buf tx_buffers[] = {{.buf = tx_buf, .len = ARRAY_SIZE(tx_buf)}};
+	const struct spi_buf_set tx_bufs = {.buffers = tx_buffers, .count = ARRAY_SIZE(tx_buffers)};
+
+	int ret = spi_write_dt(&config->bus, &tx_bufs);
+
+	if (ret != 0) {
+		LOG_ERR("Write to reg 0x%02x failed: %i", reg, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int dac161s997_channel_setup(const struct device *dev,
+				    const struct dac_channel_cfg *channel_cfg)
+{
+	if (channel_cfg->channel_id >= DAC161S997_CHANNELS) {
+		LOG_ERR("Channel %d is not valid", channel_cfg->channel_id);
+		return -EINVAL;
+	}
+
+	if (channel_cfg->resolution != DAC161S997_RESOLUTION) {
+		LOG_ERR("Only %d bit resolution is supported", DAC161S997_RESOLUTION);
+		return -ENOTSUP;
+	}
+
+	if (channel_cfg->internal) {
+		LOG_ERR("Internal channels not supported");
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static int dac161s997_write_value(const struct device *dev, uint8_t channel, uint32_t value)
+{
+	struct dac161s997_data *data = dev->data;
+	int ret;
+
+	if (channel >= DAC161S997_CHANNELS) {
+		LOG_ERR("Channel %d is not valid", channel);
+		return -EINVAL;
+	}
+
+	if (value > BIT(DAC161S997_RESOLUTION) - 1) {
+		LOG_ERR("Value %d out of range", value);
+		return -EINVAL;
+	}
+
+	ret = k_sem_take(&data->lock, K_FOREVER);
+	if (ret != 0) {
+		LOG_WRN("Write value lock failed: %d", ret);
+		return ret;
+	}
+
+	ret = dac161s997_write_reg(dev, DAC161S997_REG_DACCODE, value);
+
+	k_sem_give(&data->lock);
+
+	return ret;
+}
+
+static int dac161s997_read_status(const struct device *dev, union dac161s997_status *status)
+{
+	int ret;
+	uint16_t tmp;
+
+	ret = dac161s997_read_reg(dev, DAC161S997_REG_STATUS, &tmp);
+	if (ret == 0) {
+		status->raw = tmp;
+	}
+
+	return ret;
+}
+
+static void dac161s997_gpio_errb_work_handler(struct k_work *work)
+{
+	struct dac161s997_data *data = CONTAINER_OF(work, struct dac161s997_data, gpio_errb_work);
+	const struct device *dev = data->dev;
+	union dac161s997_status status;
+	int ret;
+
+	ret = k_sem_take(&data->lock, K_FOREVER);
+	if (ret != 0) {
+		LOG_WRN("ERRB handler take lock failed: %d", ret);
+		return;
+	}
+
+	ret = dac161s997_read_status(dev, &status);
+
+	if (data->error_cb != NULL) {
+		data->error_cb(dev, ret == 0 ? &status : NULL);
+	}
+
+	k_sem_give(&data->lock);
+}
+
+static void dac161s997_gpio_errb_cb(const struct device *dev, struct gpio_callback *cb,
+				    gpio_port_pins_t pins)
+{
+	struct dac161s997_data *data = CONTAINER_OF(cb, struct dac161s997_data, gpio_errb_cb);
+	int ret;
+
+	ret = k_work_submit(&data->gpio_errb_work);
+	if (ret != 1) {
+		LOG_WRN("ERRB work not queued: %d", ret);
+	}
+}
+
+static int dac161s997_init(const struct device *dev)
+{
+	const struct dac161s997_config *config = dev->config;
+	struct dac161s997_data *data = dev->data;
+	union dac161s997_status status;
+	int ret;
+
+	data->dev = dev;
+
+	if (!spi_is_ready_dt(&config->bus)) {
+		LOG_ERR("SPI bus %s not ready", config->bus.bus->name);
+		return -ENODEV;
+	}
+
+	k_sem_init(&data->lock, 1, 1);
+
+	ret = dac161s997_write_reg(dev, DAC161S997_REG_RESET, 0xc33c);
+	if (ret != 0) {
+		return ret;
+	}
+	ret = dac161s997_write_reg(dev, DAC161S997_REG_NOP, 0);
+	if (ret != 0) {
+		return ret;
+	}
+
+	/* Read status to clear any sticky error caused during boot or reboot */
+	ret = dac161s997_read_status(dev, &status);
+	if (ret != 0) {
+		return ret;
+	}
+
+	/* Check that DAC_RES bits are all set */
+	if (status.dac_resolution != 0x7) {
+		LOG_ERR("Unexpected DAC resolution value: 0x%02x", status.dac_resolution);
+		return ret;
+	}
+
+	if (config->gpio_errb.port != NULL) {
+		if (!gpio_is_ready_dt(&config->gpio_errb)) {
+			LOG_ERR("ERRB GPIO is not ready");
+			return -ENODEV;
+		}
+
+		k_work_init(&data->gpio_errb_work, dac161s997_gpio_errb_work_handler);
+
+		gpio_init_callback(&data->gpio_errb_cb, dac161s997_gpio_errb_cb,
+				   BIT(config->gpio_errb.pin));
+
+		ret = gpio_pin_configure_dt(&config->gpio_errb, GPIO_INPUT);
+		if (ret != 0) {
+			LOG_ERR("Configure ERRB GPIO failed: %d", ret);
+			return ret;
+		}
+
+		ret = gpio_pin_interrupt_configure_dt(&config->gpio_errb, GPIO_INT_EDGE_TO_ACTIVE);
+		if (ret) {
+			LOG_ERR("Configure ERRB interrupt failed: %d", ret);
+			return ret;
+		}
+
+		ret = gpio_add_callback_dt(&config->gpio_errb, &data->gpio_errb_cb);
+		if (ret != 0) {
+			LOG_ERR("Configure ERRB callback failed: %d", ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static DEVICE_API(dac, dac161s997_driver_api) = {
+	.channel_setup = dac161s997_channel_setup,
+	.write_value = dac161s997_write_value,
+};
+
+#define DAC_DAC161S997_INIT(n)                                                                     \
+	static const struct dac161s997_config dac161s997_config_##n = {                            \
+		.bus = SPI_DT_SPEC_INST_GET(n, SPI_TRANSFER_MSB | SPI_WORD_SET(8), 0),             \
+		.gpio_errb = GPIO_DT_SPEC_INST_GET_OR(n, errb_gpios, {0}),                         \
+	};                                                                                         \
+                                                                                                   \
+	static struct dac161s997_data dac161s997_data_##n;                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, dac161s997_init, NULL, &dac161s997_data_##n,                      \
+			      &dac161s997_config_##n, POST_KERNEL, CONFIG_DAC_INIT_PRIORITY,       \
+			      &dac161s997_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(DAC_DAC161S997_INIT);
diff --git a/drivers/dac/dac_max22017.c b/drivers/dac/dac_max22017.c
new file mode 100644
index 00000000000..a7c5f07dd32
--- /dev/null
+++ b/drivers/dac/dac_max22017.c
@@ -0,0 +1,237 @@
+/*
+ * Copyright (c) 2024 Analog Devices Inc.
+ * Copyright (c) 2024 Baylibre SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/drivers/dac.h>
+
+#include <zephyr/drivers/mfd/max22017.h>
+#include <zephyr/logging/log.h>
+
+#define DT_DRV_COMPAT adi_max22017_dac
+LOG_MODULE_REGISTER(dac_max22017, CONFIG_DAC_LOG_LEVEL);
+
+struct dac_adi_max22017_config {
+	const struct device *parent;
+	uint8_t resolution;
+	uint8_t nchannels;
+	const struct gpio_dt_spec gpio_ldac;
+	const struct gpio_dt_spec gpio_busy;
+	uint8_t latch_mode[MAX22017_MAX_CHANNEL];
+	uint8_t polarity_mode[MAX22017_MAX_CHANNEL];
+	uint8_t dac_mode[MAX22017_MAX_CHANNEL];
+	uint8_t ovc_mode[MAX22017_MAX_CHANNEL];
+	uint16_t timeout;
+};
+
+static int max22017_channel_setup(const struct device *dev,
+				  const struct dac_channel_cfg *channel_cfg)
+{
+	int ret;
+	uint16_t ao_cnfg, gen_cnfg;
+	uint8_t chan = channel_cfg->channel_id;
+	const struct dac_adi_max22017_config *config = dev->config;
+	const struct device *parent = config->parent;
+	struct max22017_data *data = parent->data;
+
+	if (chan > config->nchannels - 1) {
+		LOG_ERR("Unsupported channel %d", chan);
+		return -ENOTSUP;
+	}
+
+	if (channel_cfg->resolution != config->resolution) {
+		LOG_ERR("Unsupported resolution %d", chan);
+		return -ENOTSUP;
+	}
+
+	k_mutex_lock(&data->lock, K_FOREVER);
+	ret = max22017_reg_read(parent, MAX22017_AO_CNFG_OFF, &ao_cnfg);
+	if (ret) {
+		goto fail;
+	}
+
+	ao_cnfg |= FIELD_PREP(MAX22017_AO_CNFG_AO_EN, BIT(chan));
+
+	if (!config->latch_mode[chan]) {
+		ao_cnfg |= FIELD_PREP(MAX22017_AO_CNFG_AO_LD_CNFG, BIT(chan));
+	}
+
+	if (config->polarity_mode[chan]) {
+		ao_cnfg |= FIELD_PREP(MAX22017_AO_CNFG_AO_UNI, BIT(chan));
+	}
+
+	if (config->dac_mode[chan]) {
+		ao_cnfg |= FIELD_PREP(MAX22017_AO_CNFG_AO_MODE, BIT(chan));
+	}
+
+	ret = max22017_reg_write(parent, MAX22017_AO_CNFG_OFF, ao_cnfg);
+	if (ret) {
+		goto fail;
+	}
+
+	ret = max22017_reg_read(parent, MAX22017_GEN_CNFG_OFF, &gen_cnfg);
+	if (ret) {
+		goto fail;
+	}
+
+	if (config->ovc_mode[chan]) {
+		gen_cnfg |= FIELD_PREP(MAX22017_GEN_CNFG_OVC_CNFG, BIT(chan));
+		/* Over current shutdown mode */
+		if (config->ovc_mode[chan] == 2) {
+			gen_cnfg |= FIELD_PREP(MAX22017_GEN_CNFG_OVC_SHDN_CNFG, BIT(chan));
+		}
+	}
+
+	ret = max22017_reg_write(parent, MAX22017_GEN_CNFG_OFF, gen_cnfg);
+fail:
+	k_mutex_unlock(&data->lock);
+	return ret;
+}
+
+static int max22017_write_value(const struct device *dev, uint8_t channel, uint32_t value)
+{
+	int ret;
+	uint16_t ao_sta;
+	const struct dac_adi_max22017_config *config = dev->config;
+	const struct device *parent = config->parent;
+	struct max22017_data *data = parent->data;
+
+	if (channel > config->nchannels - 1) {
+		LOG_ERR("unsupported channel %d", channel);
+		return ENOTSUP;
+	}
+
+	if (value >= (1 << config->resolution)) {
+		LOG_ERR("Value %d out of range", value);
+		return -EINVAL;
+	}
+
+	k_mutex_lock(&data->lock, K_FOREVER);
+	if (config->gpio_busy.port) {
+		if (gpio_pin_get_dt(&config->gpio_busy)) {
+			ret = -EBUSY;
+			goto fail;
+		}
+	} else {
+		ret = max22017_reg_read(parent, MAX22017_AO_STA_OFF, &ao_sta);
+		if (ret) {
+			goto fail;
+		}
+		if (FIELD_GET(MAX22017_AO_STA_BUSY_STA, ao_sta)) {
+			ret = -EBUSY;
+			goto fail;
+		}
+	}
+
+	ret = max22017_reg_write(parent, MAX22017_AO_DATA_CHn_OFF(channel),
+				 FIELD_PREP(MAX22017_AO_DATA_CHn_AO_DATA_CH, value));
+	if (ret) {
+		goto fail;
+	}
+
+	if (config->latch_mode[channel]) {
+		if (config->gpio_ldac.port) {
+			gpio_pin_set_dt(&config->gpio_ldac, false);
+			k_sleep(K_USEC(MAX22017_LDAC_TOGGLE_TIME));
+			gpio_pin_set_dt(&config->gpio_ldac, true);
+		} else {
+			ret = max22017_reg_write(
+				parent, MAX22017_AO_CMD_OFF,
+				FIELD_PREP(MAX22017_AO_CMD_AO_LD_CTRL, BIT(channel)));
+		}
+	}
+fail:
+	k_mutex_unlock(&data->lock);
+	return ret;
+}
+
+static int max22017_init(const struct device *dev)
+{
+	int ret;
+	uint16_t gen_cnfg = 0, gen_int_en = 0;
+	const struct dac_adi_max22017_config *config = dev->config;
+	const struct device *parent = config->parent;
+	struct max22017_data *data = config->parent->data;
+
+	if (!device_is_ready(config->parent)) {
+		LOG_ERR("parent adi_max22017 MFD device '%s' not ready", config->parent->name);
+		return -EINVAL;
+	}
+
+	k_mutex_lock(&data->lock, K_FOREVER);
+
+	ret = max22017_reg_read(parent, MAX22017_GEN_CNFG_OFF, &gen_cnfg);
+	if (ret) {
+		goto fail;
+	}
+
+	ret = max22017_reg_read(parent, MAX22017_GEN_INTEN_OFF, &gen_int_en);
+	if (ret) {
+		goto fail;
+	}
+
+	if (config->timeout) {
+		gen_cnfg |= FIELD_PREP(MAX22017_GEN_CNFG_TMOUT_EN, 1) |
+			    FIELD_PREP(MAX22017_GEN_CNFG_TMOUT_SEL, (config->timeout / 100) - 1);
+		gen_int_en |= FIELD_PREP(MAX22017_GEN_INTEN_TMOUT_INTEN, 1);
+	}
+
+	ret = max22017_reg_write(parent, MAX22017_GEN_CNFG_OFF, gen_cnfg);
+	if (ret) {
+		goto fail;
+	}
+
+	ret = max22017_reg_write(parent, MAX22017_GEN_INTEN_OFF, gen_int_en);
+	if (ret) {
+		goto fail;
+	}
+
+	if (config->gpio_ldac.port) {
+		ret = gpio_pin_configure_dt(&config->gpio_ldac, GPIO_OUTPUT_ACTIVE);
+		if (ret) {
+			LOG_ERR("failed to initialize GPIO ldac pin");
+			goto fail;
+		}
+	}
+
+	if (config->gpio_busy.port) {
+		ret = gpio_pin_configure_dt(&config->gpio_busy, GPIO_INPUT);
+		if (ret) {
+			LOG_ERR("failed to initialize GPIO busy pin");
+			goto fail;
+		}
+	}
+
+fail:
+	k_mutex_unlock(&data->lock);
+	return ret;
+}
+
+static DEVICE_API(dac, max22017_driver_api) = {
+	.channel_setup = max22017_channel_setup,
+	.write_value = max22017_write_value,
+};
+
+#define DAC_MAX22017_DEVICE(id)                                                                    \
+	static const struct dac_adi_max22017_config dac_adi_max22017_config_##id = {               \
+		.parent = DEVICE_DT_GET(DT_INST_PARENT(id)),                                       \
+		.resolution = DT_INST_PROP_OR(id, resolution, 16),                                 \
+		.nchannels = DT_INST_PROP_OR(id, num_channels, 2),                                 \
+		.gpio_busy = GPIO_DT_SPEC_INST_GET_OR(id, busy_gpios, {0}),                        \
+		.gpio_ldac = GPIO_DT_SPEC_INST_GET_OR(id, ldac_gpios, {0}),                        \
+		.latch_mode = DT_INST_PROP_OR(id, latch_mode, {0}),                                \
+		.polarity_mode = DT_INST_PROP_OR(id, polarity_mode, {0}),                          \
+		.dac_mode = DT_INST_PROP_OR(id, dac_mode, {0}),                                    \
+		.ovc_mode = DT_INST_PROP_OR(id, overcurrent_mode, {0}),                            \
+		.timeout = DT_INST_PROP_OR(id, timeout, 0),                                        \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(id, max22017_init, NULL, NULL, &dac_adi_max22017_config_##id,        \
+			      POST_KERNEL, CONFIG_DAC_MAX22017_INIT_PRIORITY,                      \
+			      &max22017_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(DAC_MAX22017_DEVICE);
diff --git a/drivers/dac/dac_renesas_ra.c b/drivers/dac/dac_renesas_ra.c
new file mode 100644
index 00000000000..5078a4f0384
--- /dev/null
+++ b/drivers/dac/dac_renesas_ra.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_ra_dac
+
+#include <zephyr/drivers/dac.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/logging/log.h>
+#include "r_dac_api.h"
+#include "r_dac.h"
+
+LOG_MODULE_REGISTER(dac_renesas_ra, CONFIG_DAC_LOG_LEVEL);
+
+#define HAS_CHARGEPUMP       DT_PROP(DT_PARENT(DT_DRV_INST(0)), has_chargepump)
+#define HAS_OUTPUT_AMPLIFIER DT_PROP(DT_PARENT(DT_DRV_INST(0)), has_output_amplifier)
+#define HAS_INTERNAL_OUTPUT  DT_PROP(DT_PARENT(DT_DRV_INST(0)), has_internal_output)
+
+struct dac_renesas_ra_config {
+	const struct pinctrl_dev_config *pcfg;
+};
+
+struct dac_renesas_ra_data {
+	const struct device *dev;
+	dac_instance_ctrl_t dac;
+	struct st_dac_cfg f_config;
+};
+
+static int dac_renesas_ra_write_value(const struct device *dev, uint8_t channel, uint32_t value)
+{
+	struct dac_renesas_ra_data *data = dev->data;
+	fsp_err_t fsp_err;
+
+	if (channel != 0) {
+		LOG_ERR("wrong channel id '%hhu'", channel);
+		return -ENOTSUP;
+	}
+
+	fsp_err = R_DAC_Write(&data->dac, value);
+	if (FSP_SUCCESS != fsp_err) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int dac_renesas_ra_channel_setup(const struct device *dev,
+					const struct dac_channel_cfg *channel_cfg)
+{
+	struct dac_renesas_ra_data *data = dev->data;
+#if (HAS_OUTPUT_AMPLIFIER || HAS_CHARGEPUMP || HAS_INTERNAL_OUTPUT)
+	dac_extended_cfg_t *config_extend = (dac_extended_cfg_t *)data->f_config.p_extend;
+#endif
+	fsp_err_t fsp_err;
+
+	if (channel_cfg->channel_id != 0) {
+		LOG_ERR("wrong channel id '%hhu'", channel_cfg->channel_id);
+		return -ENOTSUP;
+	}
+
+	if (channel_cfg->resolution != 12) {
+		LOG_ERR("Resolution not supported");
+		return -ENOTSUP;
+	}
+
+	if (data->dac.channel_opened != 0) {
+		fsp_err = R_DAC_Close(&data->dac);
+		if (FSP_SUCCESS != fsp_err) {
+			return -EIO;
+		}
+	}
+
+#if HAS_OUTPUT_AMPLIFIER
+	config_extend->output_amplifier_enabled = channel_cfg->buffered;
+#elif HAS_CHARGEPUMP
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(moco))
+	config_extend->enable_charge_pump = channel_cfg->buffered;
+#else
+	if (channel_cfg->buffered) {
+		LOG_ERR("Requires MOCO clock enabled to support the buffer feature");
+		return -ENOTSUP;
+	}
+#endif
+#else
+	if (channel_cfg->buffered) {
+		LOG_ERR("The MCU doesn't support the buffer feature");
+		return -ENOTSUP;
+	}
+#endif
+
+#if HAS_INTERNAL_OUTPUT
+	config_extend->internal_output_enabled = channel_cfg->internal;
+#else
+	if (channel_cfg->internal) {
+		LOG_ERR("The MCU doesn't support the internal output feature");
+		return -ENOTSUP;
+	}
+#endif
+
+	fsp_err = R_DAC_Open(&data->dac, &data->f_config);
+	if (FSP_SUCCESS != fsp_err) {
+		return -EIO;
+	}
+
+	fsp_err = R_DAC_Start(&data->dac);
+	if (FSP_SUCCESS != fsp_err) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int dac_renesas_ra_init(const struct device *dev)
+{
+	const struct dac_renesas_ra_config *config = dev->config;
+	int ret;
+
+	ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret < 0) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(dac, dac_renesas_ra_api) = {
+	.channel_setup = dac_renesas_ra_channel_setup,
+	.write_value = dac_renesas_ra_write_value,
+};
+
+#ifdef CONFIG_DAC_RENESAS_RA_DAVREFCR_AVCC0_AVSS0
+#define DAC_RENESAS_RA_DAVREFCR DAC_VREF_AVCC0_AVSS0
+#elif defined(CONFIG_DAC_RENESAS_RA_DAVREFCR_VREFH_VREFL)
+#define DAC_RENESAS_RA_DAVREFCR DAC_VREF_VREFH_VREFL
+#elif defined(CONFIG_DAC_RENESAS_RA_DAVREFCR_NONE)
+#define DAC_RENESAS_RA_DAVREFCR DAC_VREF_NONE
+#else
+#define DAC_RENESAS_RA_DAVREFCR 0
+#endif
+
+#define DAC_RENESAS_RA_INIT(idx)                                                                   \
+	PINCTRL_DT_INST_DEFINE(idx);                                                               \
+	static dac_extended_cfg_t g_dac_cfg_extend_##idx = {                                       \
+		.data_format = DAC_DATA_FORMAT_FLUSH_RIGHT,                                        \
+		.enable_charge_pump = true,                                                        \
+		.output_amplifier_enabled = true,                                                  \
+		.internal_output_enabled = false,                                                  \
+		.ref_volt_sel = DAC_RENESAS_RA_DAVREFCR,                                           \
+	};                                                                                         \
+	static const struct dac_renesas_ra_config dac_renesas_ra_config_##idx = {                  \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx),                                       \
+	};                                                                                         \
+	static struct dac_renesas_ra_data dac_renesas_ra_data_##idx = {                            \
+		.dev = DEVICE_DT_INST_GET(idx),                                                    \
+		.f_config =                                                                        \
+			{                                                                          \
+				.channel = DT_INST_REG_ADDR(idx),                                  \
+				.ad_da_synchronized =                                              \
+					IS_ENABLED(CONFIG_DAC_RENESAS_RA_DA_AD_SYNCHRONIZE),       \
+				.p_extend = &g_dac_cfg_extend_##idx,                               \
+			},                                                                         \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(idx, dac_renesas_ra_init, NULL, &dac_renesas_ra_data_##idx,          \
+			      &dac_renesas_ra_config_##idx, POST_KERNEL, CONFIG_DAC_INIT_PRIORITY, \
+			      &dac_renesas_ra_api)
+
+DT_INST_FOREACH_STATUS_OKAY(DAC_RENESAS_RA_INIT);
diff --git a/drivers/dac/dac_sam.c b/drivers/dac/dac_sam.c
index 40cd7cadade..c39d137dc51 100644
--- a/drivers/dac/dac_sam.c
+++ b/drivers/dac/dac_sam.c
@@ -5,10 +5,6 @@
 
 /** @file
  * @brief DAC driver for Atmel SAM MCU family.
- *
- * Remarks:
- * Only SAME70, SAMV71 series devices are currently supported. Please submit a
- * patch.
  */
 
 #define DT_DRV_COMPAT atmel_sam_dac
@@ -25,10 +21,6 @@
 #include <zephyr/irq.h>
 LOG_MODULE_REGISTER(dac_sam, CONFIG_DAC_LOG_LEVEL);
 
-BUILD_ASSERT(IS_ENABLED(CONFIG_SOC_SERIES_SAME70) ||
-	     IS_ENABLED(CONFIG_SOC_SERIES_SAMV71),
-	     "Only SAME70, SAMV71 series devices are currently supported.");
-
 #define DAC_CHANNEL_NO  2
 
 /* Device constant configuration parameters */
@@ -47,7 +39,11 @@ struct dac_channel {
 
 /* Device run time data */
 struct dac_sam_dev_data {
+#if defined(CONFIG_SOC_SERIES_SAMX7X)
 	struct dac_channel dac_channels[DAC_CHANNEL_NO];
+#else
+	struct dac_channel dac_channel;
+#endif
 };
 
 static void dac_sam_isr(const struct device *dev)
@@ -60,6 +56,7 @@ static void dac_sam_isr(const struct device *dev)
 	/* Retrieve interrupt status */
 	int_stat = dac->DACC_ISR & dac->DACC_IMR;
 
+#if defined(CONFIG_SOC_SERIES_SAMX7X)
 	if ((int_stat & DACC_ISR_TXRDY0) != 0) {
 		/* Disable Transmit Ready Interrupt */
 		dac->DACC_IDR = DACC_IDR_TXRDY0;
@@ -70,6 +67,13 @@ static void dac_sam_isr(const struct device *dev)
 		dac->DACC_IDR = DACC_IDR_TXRDY1;
 		k_sem_give(&dev_data->dac_channels[1].sem);
 	}
+#else
+	if ((int_stat & DACC_ISR_TXRDY) != 0) {
+		/* Disable Transmit Ready Interrupt */
+		dac->DACC_IDR = DACC_IDR_TXRDY;
+		k_sem_give(&dev_data->dac_channel.sem);
+	}
+#endif
 }
 
 static int dac_sam_channel_setup(const struct device *dev,
@@ -106,7 +110,11 @@ static int dac_sam_write_value(const struct device *dev, uint8_t channel,
 		return -EINVAL;
 	}
 
+#if defined(CONFIG_SOC_SERIES_SAMX7X)
 	if (dac->DACC_IMR & (DACC_IMR_TXRDY0 << channel)) {
+#else
+	if (dac->DACC_IMR & DACC_IMR_TXRDY) {
+#endif
 		/* Attempting to send data on channel that's already in use */
 		return -EINVAL;
 	}
@@ -116,6 +124,7 @@ static int dac_sam_write_value(const struct device *dev, uint8_t channel,
 		return -EINVAL;
 	}
 
+#if defined(CONFIG_SOC_SERIES_SAMX7X)
 	k_sem_take(&dev_data->dac_channels[channel].sem, K_FOREVER);
 
 	/* Trigger conversion */
@@ -123,6 +132,18 @@ static int dac_sam_write_value(const struct device *dev, uint8_t channel,
 
 	/* Enable Transmit Ready Interrupt */
 	dac->DACC_IER = DACC_IER_TXRDY0 << channel;
+#else
+	k_sem_take(&dev_data->dac_channel.sem, K_FOREVER);
+
+	/* Select the channel */
+	dac->DACC_MR = DACC_MR_USER_SEL(channel) | DACC_MR_ONE;
+
+	/* Trigger conversion */
+	dac->DACC_CDR = DACC_CDR_DATA(value);
+
+	/* Enable Transmit Ready Interrupt */
+	dac->DACC_IER = DACC_IER_TXRDY;
+#endif
 
 	return 0;
 }
@@ -131,16 +152,22 @@ static int dac_sam_init(const struct device *dev)
 {
 	const struct dac_sam_dev_cfg *const dev_cfg = dev->config;
 	struct dac_sam_dev_data *const dev_data = dev->data;
-	Dacc *const dac = dev_cfg->regs;
 	int retval;
+#if defined(CONFIG_SOC_SERIES_SAMX7X)
+	Dacc *const dac = dev_cfg->regs;
+#endif
 
 	/* Configure interrupts */
 	dev_cfg->irq_config();
 
 	/* Initialize semaphores */
+#if defined(CONFIG_SOC_SERIES_SAMX7X)
 	for (int i = 0; i < ARRAY_SIZE(dev_data->dac_channels); i++) {
 		k_sem_init(&dev_data->dac_channels[i].sem, 1, 1);
 	}
+#else
+	k_sem_init(&dev_data->dac_channel.sem, 1, 1);
+#endif
 
 	/* Enable DAC clock in PMC */
 	(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
@@ -151,8 +178,10 @@ static int dac_sam_init(const struct device *dev)
 		return retval;
 	}
 
+#if defined(CONFIG_SOC_SERIES_SAMX7X)
 	/* Set Mode Register */
 	dac->DACC_MR = DACC_MR_PRESCALER(dev_cfg->prescaler);
+#endif
 
 	/* Enable module's IRQ */
 	irq_enable(dev_cfg->irq_id);
diff --git a/drivers/dac/dac_sam0.c b/drivers/dac/dac_sam0.c
index 02013ac9dcb..dc307cfe98e 100644
--- a/drivers/dac/dac_sam0.c
+++ b/drivers/dac/dac_sam0.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2020 Google LLC.
+ * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -14,6 +15,8 @@
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(dac_sam0, CONFIG_DAC_LOG_LEVEL);
 
+/* clang-format off */
+
 /*
  * Maps between the DTS reference property names and register values.  Note that
  * the ASF uses the 09/2015 names which differ from the 03/2020 datasheet.
@@ -27,8 +30,10 @@ LOG_MODULE_REGISTER(dac_sam0, CONFIG_DAC_LOG_LEVEL);
 struct dac_sam0_cfg {
 	Dac *regs;
 	const struct pinctrl_dev_config *pcfg;
-	uint8_t pm_apbc_bit;
-	uint8_t gclk_clkctrl_id;
+	volatile uint32_t *mclk;
+	uint32_t mclk_mask;
+	uint32_t gclk_gen;
+	uint16_t gclk_id;
 	uint8_t refsel;
 };
 
@@ -77,18 +82,22 @@ static int dac_sam0_init(const struct device *dev)
 	Dac *regs = cfg->regs;
 	int retval;
 
-	/* Enable the GCLK */
-	GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 |
-			    GCLK_CLKCTRL_CLKEN;
+	*cfg->mclk |= cfg->mclk_mask;
+
+#ifdef MCLK
+	GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_CHEN
+					| GCLK_PCHCTRL_GEN(cfg->gclk_gen);
+#else
+	GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
+			  | GCLK_CLKCTRL_GEN(cfg->gclk_gen)
+			  | GCLK_CLKCTRL_ID(cfg->gclk_id);
+#endif
 
 	retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
 	if (retval < 0) {
 		return retval;
 	}
 
-	/* Enable the clock in PM */
-	PM->APBCMASK.reg |= 1 << cfg->pm_apbc_bit;
-
 	/* Reset then configure the DAC */
 	regs->CTRLA.bit.SWRST = 1;
 	while (regs->STATUS.bit.SYNCBUSY) {
@@ -110,24 +119,30 @@ static DEVICE_API(dac, api_sam0_driver_api) = {
 	.write_value = dac_sam0_write_value
 };
 
-#define SAM0_DAC_REFSEL(n)						       \
-	COND_CODE_1(DT_INST_NODE_HAS_PROP(n, reference),		       \
+#define ASSIGNED_CLOCKS_CELL_BY_NAME						\
+	ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_NAME
+
+#define SAM0_DAC_REFSEL(n)							\
+	COND_CODE_1(DT_INST_NODE_HAS_PROP(n, reference),			\
 		    (DT_INST_ENUM_IDX(n, reference)), (0))
 
-#define SAM0_DAC_INIT(n)						       \
-	PINCTRL_DT_INST_DEFINE(n);					       \
-	static const struct dac_sam0_cfg dac_sam0_cfg_##n = {		       \
-		.regs = (Dac *)DT_INST_REG_ADDR(n),			       \
-		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),		       \
-		.pm_apbc_bit = DT_INST_CLOCKS_CELL_BY_NAME(n, pm, bit),	       \
-		.gclk_clkctrl_id =					       \
-			DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id),      \
-		.refsel = UTIL_CAT(SAM0_DAC_REFSEL_, SAM0_DAC_REFSEL(n)),      \
-	};								       \
-									       \
-	DEVICE_DT_INST_DEFINE(n, &dac_sam0_init, NULL, NULL,		       \
-			    &dac_sam0_cfg_##n, POST_KERNEL,		       \
-			    CONFIG_DAC_INIT_PRIORITY,			       \
+#define SAM0_DAC_INIT(n)							\
+	PINCTRL_DT_INST_DEFINE(n);						\
+	static const struct dac_sam0_cfg dac_sam0_cfg_##n = {			\
+		.regs = (Dac *)DT_INST_REG_ADDR(n),				\
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
+		.gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen),		\
+		.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id),		\
+		.mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n),		\
+		.mclk_mask = ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(n, bit),	\
+		.refsel = UTIL_CAT(SAM0_DAC_REFSEL_, SAM0_DAC_REFSEL(n)),	\
+	};									\
+										\
+	DEVICE_DT_INST_DEFINE(n, &dac_sam0_init, NULL, NULL,			\
+			    &dac_sam0_cfg_##n, POST_KERNEL,			\
+			    CONFIG_DAC_INIT_PRIORITY,				\
 			    &api_sam0_driver_api)
 
 DT_INST_FOREACH_STATUS_OKAY(SAM0_DAC_INIT);
+
+/* clang-format on */
diff --git a/drivers/dac/dac_shell.c b/drivers/dac/dac_shell.c
index 97d9feb7e5c..12260ad634a 100644
--- a/drivers/dac/dac_shell.c
+++ b/drivers/dac/dac_shell.c
@@ -94,14 +94,31 @@ static int cmd_write_value(const struct shell *sh, size_t argc, char **argv)
 	return 0;
 }
 
+static bool device_is_dac(const struct device *dev)
+{
+	return DEVICE_API_IS(dac, dev);
+}
+
+static void device_name_get(size_t idx, struct shell_static_entry *entry)
+{
+	const struct device *dev = shell_device_filter(idx, device_is_dac);
+
+	entry->syntax = (dev != NULL) ? dev->name : NULL;
+	entry->handler = NULL;
+	entry->help = NULL;
+	entry->subcmd = NULL;
+}
+
+SHELL_DYNAMIC_CMD_CREATE(dsub_device_name, device_name_get);
+
 SHELL_STATIC_SUBCMD_SET_CREATE(dac_cmds,
-	SHELL_CMD_ARG(setup, NULL,
+	SHELL_CMD_ARG(setup, &dsub_device_name,
 		      "Setup DAC channel\n"
 		      "Usage: setup <device> <channel> <resolution> [-b] [-i]\n"
 		      "-b Enable output buffer\n"
 		      "-i Connect internally",
 		      cmd_setup, 4, 2),
-	SHELL_CMD_ARG(write_value, NULL,
+	SHELL_CMD_ARG(write_value, &dsub_device_name,
 		      "Write DAC value\n"
 		      "Usage: write <device> <channel> <value>",
 		      cmd_write_value, 4, 0),
diff --git a/drivers/dai/CMakeLists.txt b/drivers/dai/CMakeLists.txt
index 506c2a54335..2196c11485f 100644
--- a/drivers/dai/CMakeLists.txt
+++ b/drivers/dai/CMakeLists.txt
@@ -6,3 +6,4 @@ add_subdirectory_ifdef(CONFIG_DAI_INTEL_DMIC intel/dmic)
 add_subdirectory_ifdef(CONFIG_DAI_INTEL_HDA intel/hda)
 add_subdirectory_ifdef(CONFIG_DAI_NXP_SAI nxp/sai)
 add_subdirectory_ifdef(CONFIG_DAI_NXP_ESAI nxp/esai)
+add_subdirectory_ifdef(CONFIG_DAI_NXP_MICFIL nxp/micfil)
diff --git a/drivers/dai/Kconfig b/drivers/dai/Kconfig
index 05877efd88e..fc3972a9896 100644
--- a/drivers/dai/Kconfig
+++ b/drivers/dai/Kconfig
@@ -31,5 +31,6 @@ source "drivers/dai/intel/dmic/Kconfig.dmic"
 source "drivers/dai/intel/hda/Kconfig.hda"
 source "drivers/dai/nxp/sai/Kconfig.sai"
 source "drivers/dai/nxp/esai/Kconfig.esai"
+source "drivers/dai/nxp/micfil/Kconfig.micfil"
 
 endif # DAI
diff --git a/drivers/dai/intel/dmic/dmic.c b/drivers/dai/intel/dmic/dmic.c
index e1a93da91b4..ed84cb22fda 100644
--- a/drivers/dai/intel/dmic/dmic.c
+++ b/drivers/dai/intel/dmic/dmic.c
@@ -257,33 +257,6 @@ static void dai_dmic_stop_fifo_packers(struct dai_intel_dmic *dmic,
 			     OUTCONTROL_FINIT);
 }
 
-/* On DMIC IRQ event trace the status register that contains the status and
- * error bit fields.
- */
-static void dai_dmic_irq_handler(const void *data)
-{
-	struct dai_intel_dmic *dmic = ((struct device *)data)->data;
-	uint32_t val0;
-	uint32_t val1;
-
-	/* Trace OUTSTAT0 register */
-	val0 = dai_dmic_read(dmic, OUTSTAT);
-	val1 = dai_dmic_read(dmic, OUTSTAT + PDM_CHANNEL_REGS_SIZE);
-	LOG_DBG("dmic_irq_handler(), OUTSTAT0 = 0x%x, OUTSTAT1 = 0x%x", val0, val1);
-
-	if (val0 & OUTSTAT_ROR) {
-		LOG_ERR("dmic_irq_handler(): full fifo A or PDM overrun");
-		dai_dmic_write(dmic, OUTSTAT, val0);
-		dai_dmic_stop_fifo_packers(dmic, 0);
-	}
-
-	if (val1 & OUTSTAT_ROR) {
-		LOG_ERR("dmic_irq_handler(): full fifo B or PDM overrun");
-		dai_dmic_write(dmic, OUTSTAT + PDM_CHANNEL_REGS_SIZE, val1);
-		dai_dmic_stop_fifo_packers(dmic, 1);
-	}
-}
-
 static inline void dai_dmic_dis_clk_gating(const struct dai_intel_dmic *dmic)
 {
 	/* Disable DMIC clock gating */
@@ -366,8 +339,6 @@ static int dai_dmic_probe(struct dai_intel_dmic *dmic)
 	/* DMIC Owner Select to DSP */
 	dai_dmic_claim_ownership(dmic);
 
-	irq_enable(dmic->irq);
-
 	return 0;
 }
 
@@ -376,10 +347,6 @@ static int dai_dmic_remove(struct dai_intel_dmic *dmic)
 	uint32_t active_fifos_mask = dai_dmic_global.active_fifos_mask;
 	uint32_t pause_mask = dai_dmic_global.pause_mask;
 
-	LOG_INF("dmic_remove()");
-
-	irq_disable(dmic->irq);
-
 	LOG_INF("dmic_remove(), dmic_active_fifos_mask = 0x%x, dmic_pause_mask = 0x%x",
 		active_fifos_mask, pause_mask);
 
@@ -585,7 +552,6 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic)
 	for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) {
 		mic_a = dmic->enable[i] & 1;
 		mic_b = (dmic->enable[i] & 2) >> 1;
-		start_fir = dmic->enable[i] > 0;
 
 		/* If both microphones are needed start them simultaneously
 		 * to start them in sync. The reset may be cleared for another
@@ -618,7 +584,10 @@ static void dai_dmic_start(struct dai_intel_dmic *dmic)
 					     MIC_CONTROL_PDM_EN_B,
 					     FIELD_PREP(MIC_CONTROL_PDM_EN_B, 1));
 		}
+	}
 
+	for (i = 0; i < CONFIG_DAI_DMIC_HW_CONTROLLERS; i++) {
+		start_fir = dmic->enable[i] > 0;
 		dai_dmic_update_bits(dmic, dmic_base[i] + FIR_CHANNEL_REGS_SIZE *
 				     dmic->dai_config_params.dai_index + FIR_CONTROL,
 				     FIR_CONTROL_START,
@@ -889,13 +858,6 @@ DEVICE_API(dai, dai_dmic_ops) = {
 
 static int dai_dmic_initialize_device(const struct device *dev)
 {
-	IRQ_CONNECT(
-		DT_INST_IRQN(0),
-		IRQ_DEFAULT_PRIORITY,
-		dai_dmic_irq_handler,
-		DEVICE_DT_INST_GET(0),
-		0);
-
 	return pm_device_driver_init(dev, dmic_pm_action);
 };
 
diff --git a/drivers/dai/intel/ssp/ssp.c b/drivers/dai/intel/ssp/ssp.c
index 8ee618b0350..bd0f6479fba 100644
--- a/drivers/dai/intel/ssp/ssp.c
+++ b/drivers/dai/intel/ssp/ssp.c
@@ -743,7 +743,8 @@ static int dai_ssp_poll_for_register_delay(uint32_t reg, uint32_t mask,
 					   uint32_t val, uint64_t us)
 {
 	if (!WAIT_FOR((sys_read32(reg) & mask) == val, us, k_busy_wait(1))) {
-		LOG_ERR("poll timeout reg %u mask %u val %u us %u", reg, mask, val, (uint32_t)us);
+		LOG_ERR("poll timeout reg[%#x]=%#x, waited for: mask %#x, val %#x, us %u", reg,
+			sys_read32(reg), mask, val, (uint32_t)us);
 		return -EIO;
 	}
 
@@ -864,7 +865,7 @@ static void dai_ssp_program_channel_map(struct dai_intel_ssp *dp,
 	 /* Set upper slot number from configuration */
 	pcmsycm = pcmsycm | (dp->ssp_plat_data->params.tdm_slots - 1) << 4;
 
-	if (DAI_INTEL_SSP_IS_BIT_SET(cfg->link_config, 15)) {
+	if (IS_BIT_SET(cfg->link_config, 15)) {
 		uint32_t reg_add = dai_ip_base(dp) + 0x1000 * ssp_index + PCMS0CM_OFFSET;
 		/* Program HDA output stream parameters */
 		sys_write16((pcmsycm & 0xffff), reg_add);
@@ -880,7 +881,7 @@ static void dai_ssp_program_channel_map(struct dai_intel_ssp *dp,
 	uint16_t pcmsycm = cfg->link_config;
 	uint8_t slot_count = 0;
 
-	if (DAI_INTEL_SSP_IS_BIT_SET(cfg->link_config, 15)) {
+	if (IS_BIT_SET(cfg->link_config, 15)) {
 		if (blob30->version == SSP_BLOB_VER_3_0) {
 			time_slot_map =
 				blob30->i2s_ssp_config.ssmidytsa[cfg->tdm_slot_group];
@@ -2327,29 +2328,29 @@ static void dai_ssp_start(struct dai_intel_ssp *dp, int direction)
 
 
 	/* enable DMA */
-#if SSP_IP_VER > SSP_IP_VER_2_0
 	if (direction == DAI_DIR_PLAYBACK) {
+		LOG_INF("SSP%d TX", dp->dai_index);
+#if SSP_IP_VER > SSP_IP_VER_2_0
 		dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group),
 				    SSMODyCS_TSRE, SSMODyCS_TSRE);
 		dai_ssp_update_bits(dp, SSMODyCS(dp->tdm_slot_group),
 				    SSMODyCS_TXEN, SSMODyCS_TXEN);
+#else
+		dai_ssp_update_bits(dp, SSCR1, SSCR1_TSRE, SSCR1_TSRE);
+		dai_ssp_update_bits(dp, SSTSA, SSTSA_TXEN, SSTSA_TXEN);
+#endif
 	} else {
+		LOG_INF("SSP%d RX", dp->dai_index);
+#if SSP_IP_VER > SSP_IP_VER_2_0
 		dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group),
 				    SSMIDyCS_RSRE, SSMIDyCS_RSRE);
 		dai_ssp_update_bits(dp, SSMIDyCS(dp->tdm_slot_group),
 				    SSMIDyCS_RXEN, SSMIDyCS_RXEN);
-	}
 #else
-	if (direction == DAI_DIR_PLAYBACK) {
-		LOG_INF("SSP%d TX", dp->dai_index);
-		dai_ssp_update_bits(dp, SSCR1, SSCR1_TSRE, SSCR1_TSRE);
-		dai_ssp_update_bits(dp, SSTSA, SSTSA_TXEN, SSTSA_TXEN);
-	} else {
-		LOG_INF("SSP%d RX", dp->dai_index);
 		dai_ssp_update_bits(dp, SSCR1, SSCR1_RSRE, SSCR1_RSRE);
 		dai_ssp_update_bits(dp, SSRSA, SSRSA_RXEN, SSRSA_RXEN);
-	}
 #endif
+	}
 
 	dp->state[direction] = DAI_STATE_RUNNING;
 
diff --git a/drivers/dai/intel/ssp/ssp.h b/drivers/dai/intel/ssp/ssp.h
index 4190e0f21b9..de0ba4ef9af 100644
--- a/drivers/dai/intel/ssp/ssp.h
+++ b/drivers/dai/intel/ssp/ssp.h
@@ -39,7 +39,6 @@
 	(((x) & (1ULL << (b))) >> (b))
 #define DAI_INTEL_SSP_GET_BITS(b_hi, b_lo, x) \
 	(((x) & MASK(b_hi, b_lo)) >> (b_lo))
-#define DAI_INTEL_SSP_IS_BIT_SET(reg, bit)	(((reg >> bit) & (0x1)) != 0)
 
 /* ssp_freq array constants */
 #define DAI_INTEL_SSP_NUM_FREQ			3
diff --git a/drivers/dai/nxp/micfil/CMakeLists.txt b/drivers/dai/nxp/micfil/CMakeLists.txt
new file mode 100644
index 00000000000..50ea62e9327
--- /dev/null
+++ b/drivers/dai/nxp/micfil/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+zephyr_library_sources(micfil.c)
diff --git a/drivers/dai/nxp/micfil/Kconfig.micfil b/drivers/dai/nxp/micfil/Kconfig.micfil
new file mode 100644
index 00000000000..7e5e0cd8beb
--- /dev/null
+++ b/drivers/dai/nxp/micfil/Kconfig.micfil
@@ -0,0 +1,10 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config DAI_NXP_MICFIL
+	bool "NXP Pulse Density Modulation Microphone Interface (MICFIL) driver"
+	default y
+	depends on DT_HAS_NXP_DAI_MICFIL_ENABLED
+	select PINCTRL
+	help
+		Select this to enable NXP PDM MICFIL driver.
diff --git a/drivers/dai/nxp/micfil/micfil.c b/drivers/dai/nxp/micfil/micfil.c
new file mode 100644
index 00000000000..364be9ac28a
--- /dev/null
+++ b/drivers/dai/nxp/micfil/micfil.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/drivers/dai.h>
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/logging/log.h>
+
+#include "fsl_pdm.h"
+
+#define DT_DRV_COMPAT nxp_dai_micfil
+LOG_MODULE_REGISTER(nxp_dai_micfil);
+
+#define MICFIL_CLK_ROOT 24576000
+#define MICFIL_OSR_DEFAULT	16
+
+#define UINT_TO_MICFIL(x) ((PDM_Type *)(uintptr_t)(x))
+
+#define MICFIL_FIFO_BASE(inst) \
+	POINTER_TO_UINT(&(UINT_TO_MICFIL(DT_INST_REG_ADDR(inst))->DATACH[0]))
+
+#define MICFIL_DMA_HANDSHAKE(inst) \
+	((DT_INST_DMAS_CELL_BY_IDX(inst, 0, channel) & GENMASK(7, 0)) | \
+	((DT_INST_DMAS_CELL_BY_IDX(inst, 0, mux) << 8) & GENMASK(15, 8)))
+
+struct dai_nxp_micfil_data {
+	struct dai_config cfg;
+};
+
+struct dai_nxp_micfil_config {
+	PDM_Type *base;
+	const struct dai_properties *rx_props;
+	const struct pinctrl_dev_config *pincfg;
+};
+
+/* this needs to match SOF struct sof_ipc_dai_micfil_params */
+struct micfil_bespoke_config {
+	uint32_t pdm_rate;
+	uint32_t pdm_ch;
+};
+
+static void dai_nxp_micfil_trigger_start(const struct device *dev)
+{
+	const struct dai_nxp_micfil_config *cfg = dev->config;
+
+	/* enable DMA requests */
+	PDM_EnableDMA(cfg->base, true);
+	/* enable the module */
+	PDM_Enable(cfg->base, true);
+}
+
+static void dai_nxp_micfil_trigger_stop(const struct device *dev)
+{
+	const struct dai_nxp_micfil_config *cfg = dev->config;
+
+	/* disable DMA requests */
+	PDM_EnableDMA(cfg->base, false);
+	/* disable module */
+	PDM_Enable(cfg->base, false);
+}
+
+static const struct dai_properties
+*dai_nxp_micfil_get_properties(const struct device *dev, enum dai_dir dir, int stream_id)
+{
+	const struct dai_nxp_micfil_config *cfg = dev->config;
+
+	if (dir == DAI_DIR_RX) {
+		return cfg->rx_props;
+	}
+
+	LOG_ERR("invalid direction %d", dir);
+	return NULL;
+}
+
+static int dai_nxp_micfil_trigger(const struct device *dev, enum dai_dir dir,
+				  enum dai_trigger_cmd cmd)
+{
+	if (dir != DAI_DIR_RX) {
+		LOG_ERR("invalid direction %d", dir);
+		return -EINVAL;
+	}
+
+	switch (cmd) {
+	case DAI_TRIGGER_START:
+		dai_nxp_micfil_trigger_start(dev);
+		break;
+	case DAI_TRIGGER_STOP:
+	case DAI_TRIGGER_PAUSE:
+		dai_nxp_micfil_trigger_stop(dev);
+		break;
+	case DAI_TRIGGER_PRE_START:
+	case DAI_TRIGGER_COPY:
+		return 0;
+	default:
+		LOG_ERR("invalid trigger cmd %d", cmd);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int dai_nxp_micfil_get_config(const struct device *dev, struct dai_config *cfg,
+				     enum dai_dir dir)
+{
+	struct dai_nxp_micfil_data *micfil_data = dev->data;
+
+	memcpy(cfg, &micfil_data->cfg, sizeof(*cfg));
+	return 0;
+}
+
+static int dai_nxp_micfil_set_config(const struct device *dev,
+		const struct dai_config *cfg, const void *bespoke_cfg)
+
+{
+	const struct micfil_bespoke_config *bespoke = bespoke_cfg;
+	const struct dai_nxp_micfil_config *micfil_cfg = dev->config;
+	pdm_channel_config_t chan_config = { 0 };
+	pdm_config_t global_config = { 0 };
+	int ret, i;
+
+	if (cfg->type != DAI_IMX_MICFIL) {
+		LOG_ERR("wrong DAI type: %d", cfg->type);
+		return -EINVAL;
+	}
+
+	global_config.fifoWatermark = micfil_cfg->rx_props->fifo_depth - 1;
+	global_config.qualityMode = kPDM_QualityModeVeryLow0;
+	global_config.cicOverSampleRate = MICFIL_OSR_DEFAULT;
+
+	PDM_Init(micfil_cfg->base, &global_config);
+
+	for (i = 0; i < bespoke->pdm_ch; i++) {
+		chan_config.gain = kPDM_DfOutputGain2;
+		chan_config.cutOffFreq = kPDM_DcRemoverBypass;
+		PDM_SetChannelConfig(micfil_cfg->base, i, &chan_config);
+	}
+
+	ret = PDM_SetSampleRateConfig(micfil_cfg->base, MICFIL_CLK_ROOT, bespoke->pdm_rate);
+	if (ret == kStatus_Fail) {
+		LOG_ERR("Failure to set samplerate config rate %d", bespoke->pdm_rate);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int dai_nxp_micfil_probe(const struct device *dev)
+{
+	/* nothing do to here, but mandatory to exist */
+	return 0;
+}
+
+static int dai_nxp_micfil_remove(const struct device *dev)
+{
+	/* nothing do to here, but mandatory to exist */
+	return 0;
+}
+
+static DEVICE_API(dai, dai_nxp_micfil_ops) = {
+	.probe			= dai_nxp_micfil_probe,
+	.remove			= dai_nxp_micfil_remove,
+	.config_set		= dai_nxp_micfil_set_config,
+	.config_get		= dai_nxp_micfil_get_config,
+	.get_properties		= dai_nxp_micfil_get_properties,
+	.trigger		= dai_nxp_micfil_trigger,
+};
+
+static int micfil_init(const struct device *dev)
+{
+	const struct dai_nxp_micfil_config *cfg = dev->config;
+	int ret;
+
+	/* pinctrl is optional so do not return an error if not defined */
+	ret = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);
+	if (ret < 0 && ret != -ENOENT) {
+		return ret;
+	}
+
+	return 0;
+}
+
+#define DAI_NXP_MICFIL_INIT(inst)						\
+PINCTRL_DT_INST_DEFINE(inst);							\
+static struct dai_nxp_micfil_data dai_nxp_micfil_data_##inst = {		\
+	.cfg.type = DAI_IMX_MICFIL,						\
+	.cfg.dai_index = DT_INST_PROP_OR(inst, dai_index, 0),			\
+};										\
+										\
+static const struct dai_properties micfil_rx_props_##inst = {			\
+	.fifo_address = MICFIL_FIFO_BASE(inst),					\
+	.fifo_depth = DT_INST_PROP(inst, fifo_depth),			\
+	.dma_hs_id = MICFIL_DMA_HANDSHAKE(inst),				\
+};										\
+										\
+static const struct dai_nxp_micfil_config dai_nxp_micfil_config_##inst = {	\
+	.base = UINT_TO_MICFIL(DT_INST_REG_ADDR(inst)),				\
+	.rx_props = &micfil_rx_props_##inst,					\
+	.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),				\
+};										\
+										\
+DEVICE_DT_INST_DEFINE(inst, &micfil_init, NULL,					\
+	      &dai_nxp_micfil_data_##inst, &dai_nxp_micfil_config_##inst,	\
+	      POST_KERNEL, CONFIG_DAI_INIT_PRIORITY,				\
+	      &dai_nxp_micfil_ops);						\
+
+DT_INST_FOREACH_STATUS_OKAY(DAI_NXP_MICFIL_INIT)
diff --git a/drivers/disk/Kconfig.sdmmc b/drivers/disk/Kconfig.sdmmc
index 42d82676b18..651fdbc8b6a 100644
--- a/drivers/disk/Kconfig.sdmmc
+++ b/drivers/disk/Kconfig.sdmmc
@@ -51,7 +51,8 @@ config SDMMC_STM32_HWFC
 		   SOC_SERIES_STM32H7X || \
 		   SOC_SERIES_STM32F7X || \
 		   SOC_SERIES_STM32L4X || \
-		   SOC_SERIES_STM32L5X
+		   SOC_SERIES_STM32L5X || \
+		   SOC_SERIES_STM32N6X
 	help
 	  Enable SDMMC Hardware Flow Control to avoid FIFO underrun (TX mode) and
 	  overrun (RX mode) errors.
diff --git a/drivers/disk/nvme/Kconfig b/drivers/disk/nvme/Kconfig
index a2f6bedddd7..4ab51992c1b 100644
--- a/drivers/disk/nvme/Kconfig
+++ b/drivers/disk/nvme/Kconfig
@@ -52,6 +52,13 @@ config NVME_REQUEST_TIMEOUT
 	  This sets the waiting time for a request to succeed.
 	  Do not touch this unless you know what you are doing.
 
+config NVME_PRP_PAGE_SIZE
+	hex "NVMe PRP Page Size"
+	default MMU_PAGE_SIZE if MMU
+	default 0x1000
+	help
+	  Set the PRP page size. If MMU is enabled, this will default to the MMU page size.
+
 config NVME_PRP_LIST_AMOUNT
 	int "Number of allocated PRP list"
 	default 2
diff --git a/drivers/disk/nvme/nvme_cmd.c b/drivers/disk/nvme/nvme_cmd.c
index aecb41b77d4..0873e9a4aa8 100644
--- a/drivers/disk/nvme/nvme_cmd.c
+++ b/drivers/disk/nvme/nvme_cmd.c
@@ -555,9 +555,9 @@ static int nvme_cmd_qpair_fill_prp_list(struct nvme_cmd_qpair *qpair,
 
 	p_addr = (uintptr_t)request->payload;
 	request->cmd.dptr.prp1 =
-		(uint64_t)sys_cpu_to_le64(p_addr);
+		sys_cpu_to_le64((uint64_t)p_addr);
 	request->cmd.dptr.prp2 =
-		(uint64_t)sys_cpu_to_le64(&prp_list->prp);
+		sys_cpu_to_le64((uint64_t)(uintptr_t)&prp_list->prp);
 	p_addr = NVME_PRP_NEXT_PAGE(p_addr);
 
 	for (idx = 0; idx < n_prp; idx++) {
@@ -576,13 +576,13 @@ static int compute_n_prp(uintptr_t addr, uint32_t size)
 
 	/* See Common Command Format, Data Pointer (DPTR) field */
 
-	n_prp = size / CONFIG_MMU_PAGE_SIZE;
+	n_prp = size / CONFIG_NVME_PRP_PAGE_SIZE;
 	if (n_prp == 0) {
 		n_prp = 1;
 	}
 
-	if (size != CONFIG_MMU_PAGE_SIZE) {
-		size = size % CONFIG_MMU_PAGE_SIZE;
+	if (size != CONFIG_NVME_PRP_PAGE_SIZE) {
+		size = size % CONFIG_NVME_PRP_PAGE_SIZE;
 	}
 
 	if (n_prp == 1) {
@@ -602,7 +602,7 @@ static int nvme_cmd_qpair_fill_dptr(struct nvme_cmd_qpair *qpair,
 	switch (request->type) {
 	case NVME_REQUEST_NULL:
 		break;
-	case NVME_REQUEST_VADDR:
+	case NVME_REQUEST_VADDR: {
 		int n_prp;
 
 		if (request->payload_size > qpair->ctrlr->max_xfer_size) {
@@ -614,7 +614,7 @@ static int nvme_cmd_qpair_fill_dptr(struct nvme_cmd_qpair *qpair,
 				      request->payload_size);
 		if (n_prp <= 2) {
 			request->cmd.dptr.prp1 =
-				(uint64_t)sys_cpu_to_le64(request->payload);
+				sys_cpu_to_le64((uint64_t)(uintptr_t)request->payload);
 			if (n_prp == 2) {
 				request->cmd.dptr.prp2 = (uint64_t)sys_cpu_to_le64(
 					NVME_PRP_NEXT_PAGE(
@@ -627,6 +627,7 @@ static int nvme_cmd_qpair_fill_dptr(struct nvme_cmd_qpair *qpair,
 		}
 
 		return nvme_cmd_qpair_fill_prp_list(qpair, request, n_prp);
+	}
 	default:
 		break;
 	}
diff --git a/drivers/disk/nvme/nvme_cmd.h b/drivers/disk/nvme/nvme_cmd.h
index 969e7c3f566..583a1364c4c 100644
--- a/drivers/disk/nvme/nvme_cmd.h
+++ b/drivers/disk/nvme/nvme_cmd.h
@@ -309,14 +309,14 @@ enum nvme_feature {
 #define CACHE_LINE_SIZE				CONFIG_DCACHE_LINE_SIZE
 #endif
 
-#define NVME_PBAO_MASK (CONFIG_MMU_PAGE_SIZE - 1)
+#define NVME_PBAO_MASK (CONFIG_NVME_PRP_PAGE_SIZE - 1)
 
 #define NVME_PRP_NEXT_PAGE(_addr)				\
-	((_addr & ~NVME_PBAO_MASK) + CONFIG_MMU_PAGE_SIZE)
+	((_addr & ~NVME_PBAO_MASK) + CONFIG_NVME_PRP_PAGE_SIZE)
 
 struct nvme_prp_list {
-	uintptr_t prp[CONFIG_MMU_PAGE_SIZE / sizeof(uintptr_t)]
-						__aligned(CONFIG_MMU_PAGE_SIZE);
+	uintptr_t prp[CONFIG_NVME_PRP_PAGE_SIZE / sizeof(uintptr_t)]
+						__aligned(CONFIG_NVME_PRP_PAGE_SIZE);
 	sys_dnode_t node;
 };
 
diff --git a/drivers/disk/sdmmc_stm32.c b/drivers/disk/sdmmc_stm32.c
index 114e7d6b467..b0f3503b6c7 100644
--- a/drivers/disk/sdmmc_stm32.c
+++ b/drivers/disk/sdmmc_stm32.c
@@ -537,7 +537,7 @@ static const struct disk_operations stm32_sdmmc_ops = {
 };
 
 static struct disk_info stm32_sdmmc_info = {
-	.name = "SD",
+	.name = DT_INST_PROP_OR(0, disk_name, "SD"),
 	.ops = &stm32_sdmmc_ops,
 };
 
diff --git a/drivers/disk/sdmmc_subsys.c b/drivers/disk/sdmmc_subsys.c
index 500471d4d65..6fc8d7fd6e3 100644
--- a/drivers/disk/sdmmc_subsys.c
+++ b/drivers/disk/sdmmc_subsys.c
@@ -21,12 +21,13 @@ enum sd_status {
 
 struct sdmmc_config {
 	const struct device *host_controller;
+	const char *name;
 };
 
 struct sdmmc_data {
 	struct sd_card card;
 	enum sd_status status;
-	struct disk_info *disk_info;
+	struct disk_info disk_info;
 };
 
 
@@ -113,27 +114,24 @@ static const struct disk_operations sdmmc_disk_ops = {
 
 static int disk_sdmmc_init(const struct device *dev)
 {
+	const struct sdmmc_config *config = dev->config;
 	struct sdmmc_data *data = dev->data;
 
 	data->status = SD_UNINIT;
+	data->disk_info.name = config->name;
+	data->disk_info.ops = &sdmmc_disk_ops;
+	data->disk_info.dev = dev;
 
-	return disk_access_register(data->disk_info);
+	return disk_access_register(&data->disk_info);
 }
 
 #define DISK_ACCESS_SDMMC_INIT(n)						\
 	static const struct sdmmc_config sdmmc_config_##n = {			\
 		.host_controller = DEVICE_DT_GET(DT_INST_PARENT(n)),		\
-	};									\
-										\
-	static struct disk_info sdmmc_disk_##n = {                              \
 		.name = DT_INST_PROP(n, disk_name),                             \
-		.ops = &sdmmc_disk_ops,                                         \
-		.dev = DEVICE_DT_INST_GET(n),                                   \
 	};									\
 										\
-	static struct sdmmc_data sdmmc_data_##n = {				\
-		.disk_info = &sdmmc_disk_##n,					\
-	};									\
+	static struct sdmmc_data sdmmc_data_##n;                                \
 										\
 	DEVICE_DT_INST_DEFINE(n,						\
 			&disk_sdmmc_init,					\
diff --git a/drivers/display/CMakeLists.txt b/drivers/display/CMakeLists.txt
index 185e3a1b2b4..5123faeafd0 100644
--- a/drivers/display/CMakeLists.txt
+++ b/drivers/display/CMakeLists.txt
@@ -20,6 +20,7 @@ zephyr_library_sources_ifdef(CONFIG_SSD1306		ssd1306.c)
 zephyr_library_sources_ifdef(CONFIG_SSD1327		ssd1327.c)
 zephyr_library_sources_ifdef(CONFIG_SSD16XX		ssd16xx.c)
 zephyr_library_sources_ifdef(CONFIG_SSD1322		ssd1322.c)
+zephyr_library_sources_ifdef(CONFIG_ST7567		display_st7567.c)
 zephyr_library_sources_ifdef(CONFIG_ST7789V		display_st7789v.c)
 zephyr_library_sources_ifdef(CONFIG_ST7735R		display_st7735r.c)
 zephyr_library_sources_ifdef(CONFIG_ST7796S		display_st7796s.c)
@@ -33,6 +34,7 @@ zephyr_library_sources_ifdef(CONFIG_DISPLAY_RENESAS_LCDC display_renesas_lcdc.c)
 zephyr_library_sources_ifdef(CONFIG_NT35510		display_nt35510.c)
 zephyr_library_sources_ifdef(CONFIG_RENESAS_RA_GLCDC		display_renesas_ra.c)
 zephyr_library_sources_ifdef(CONFIG_ILI9806E_DSI		display_ili9806e_dsi.c)
+zephyr_library_sources_ifdef(CONFIG_ST7701 display_st7701.c)
 
 zephyr_library_sources_ifdef(CONFIG_MICROBIT_DISPLAY
 	mb_display.c
diff --git a/drivers/display/Kconfig b/drivers/display/Kconfig
index 593c34dc163..08de8a09ce5 100644
--- a/drivers/display/Kconfig
+++ b/drivers/display/Kconfig
@@ -30,6 +30,7 @@ source "drivers/display/Kconfig.ssd1306"
 source "drivers/display/Kconfig.ssd1327"
 source "drivers/display/Kconfig.ssd16xx"
 source "drivers/display/Kconfig.ssd1322"
+source "drivers/display/Kconfig.st7567"
 source "drivers/display/Kconfig.st7735r"
 source "drivers/display/Kconfig.st7789v"
 source "drivers/display/Kconfig.st7796s"
@@ -50,5 +51,6 @@ source "drivers/display/Kconfig.renesas_lcdc"
 source "drivers/display/Kconfig.nt35510"
 source "drivers/display/Kconfig.renesas_ra"
 source "drivers/display/Kconfig.ili9806e_dsi"
+source "drivers/display/Kconfig.st7701"
 
 endif # DISPLAY
diff --git a/drivers/display/Kconfig.ili9xxx b/drivers/display/Kconfig.ili9xxx
index d1710d176e9..f203e614d20 100644
--- a/drivers/display/Kconfig.ili9xxx
+++ b/drivers/display/Kconfig.ili9xxx
@@ -12,13 +12,13 @@ config ILI9XXX
 
 config ILI9XXX_READ
 	bool "Allow display_read API with ILI9XXX"
+	depends on ILI9XXX
 	help
 	  Support display_read API with ILI9XXX controllers. This API is opt-in,
 	  because it adds code overhead and is not very performant due to
 	  the requirement to bitshift data read from the ILI9XXX. Note the
 	  API only supports RGB565 mode.
 
-
 config ILI9340
 	bool "ILI9340 display driver"
 	default y
diff --git a/drivers/display/Kconfig.mcux_dcnano_lcdif b/drivers/display/Kconfig.mcux_dcnano_lcdif
index 6390539c089..0b33923693e 100644
--- a/drivers/display/Kconfig.mcux_dcnano_lcdif
+++ b/drivers/display/Kconfig.mcux_dcnano_lcdif
@@ -58,4 +58,4 @@ config MCUX_DCNANO_LCDIF_EXTERNAL_FB_ADDR
 
 endif # MCUX_DCNANO_LCDIF_EXTERNAL_FB_MEM
 
-endif # DISPLAY_MCUX_ELCDIF
+endif # DISPLAY_MCUX_DCNANO_LCDIF
diff --git a/drivers/display/Kconfig.renesas_ra b/drivers/display/Kconfig.renesas_ra
index 4eaaeb99196..8bd872b240f 100644
--- a/drivers/display/Kconfig.renesas_ra
+++ b/drivers/display/Kconfig.renesas_ra
@@ -1,6 +1,6 @@
 # Renesas RA Family
 
-# Copyright (c) 2024 Renesas Electronics Corporation
+# Copyright (c) 2024-2025 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 config RENESAS_RA_GLCDC
@@ -23,6 +23,14 @@ config RENESAS_RA_GLCDC_FB_NUM
 	    - 1 single frame buffer in RENESAS RA GLCDC driver.
 	    - 2 double frame buffer in RENESAS RA GLCDC driver.
 
+config RENESAS_RA_GLCDC_FRAME_BUFFER_SECTION
+	string "RAM memory section to place frame buffer"
+	depends on RENESAS_RA_GLCDC_FB_NUM > 0
+	help
+	  RAM memory section name to place frame buffer.
+	  Example: to place display frame buffer in external SDRAM (.sdram section)
+	    CONFIG_RENESAS_RA_GLCDC_FRAME_BUFFER_SECTION=".sdram"
+
 if LVGL
 
 # Force display buffers to be aligned to cache line size (64 bytes)
diff --git a/drivers/display/Kconfig.sdl b/drivers/display/Kconfig.sdl
index d1ed25bf537..3c41b2848ab 100644
--- a/drivers/display/Kconfig.sdl
+++ b/drivers/display/Kconfig.sdl
@@ -37,6 +37,9 @@ choice SDL_DISPLAY_DEFAULT_PIXEL_FORMAT
 	config SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_BGR_565
 		bool "BGR 565"
 
+	config SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_L_8
+		bool "Grayscale 8bit"
+
 endchoice
 
 config SDL_DISPLAY_ZOOM_PCT
@@ -59,6 +62,14 @@ config SDL_DISPLAY_MONO_MSB_FIRST
 	  If selected, set the MSB to represent the first pixel.
 	  This applies when the pixel format is MONO01/MONO10.
 
+config SDL_DISPLAY_MONO_VTILED
+	bool "Configure data octet representation"
+	default y
+	help
+	  If selected, set the data octet to represent 8 pixels ordered vertically.
+	  Otherwise, horizontally.
+	  This applies when the pixel format is MONO01/MONO10.
+
 config SDL_DISPLAY_TRANSPARENCY_GRID_CELL_SIZE
 	int "Transparency grid cell size"
 	default 8
@@ -77,4 +88,10 @@ config SDL_DISPLAY_TRANSPARENCY_GRID_CELL_COLOR_2
 	help
 	  The color of the even cells in the transparency grid.
 
+config SDL_DISPLAY_THREAD_PRIORITY
+	int "SDL display thread priority"
+	default NUM_PREEMPT_PRIORITIES
+	help
+	  Drawing thread priority.
+
 endif # SDL_DISPLAY
diff --git a/drivers/display/Kconfig.ssd1306 b/drivers/display/Kconfig.ssd1306
index 413e32d8f33..f067f572371 100644
--- a/drivers/display/Kconfig.ssd1306
+++ b/drivers/display/Kconfig.ssd1306
@@ -6,9 +6,11 @@
 menuconfig SSD1306
 	bool "SSD1306 display driver"
 	default y
-	depends on DT_HAS_SOLOMON_SSD1306FB_ENABLED || DT_HAS_SINOWEALTH_SH1106_ENABLED
+	depends on DT_HAS_SOLOMON_SSD1306FB_ENABLED || DT_HAS_SOLOMON_SSD1309FB_ENABLED || DT_HAS_SINOWEALTH_SH1106_ENABLED
 	select I2C if $(dt_compat_on_bus,$(DT_COMPAT_SOLOMON_SSD1306FB),i2c)
 	select SPI if $(dt_compat_on_bus,$(DT_COMPAT_SOLOMON_SSD1306FB),spi)
+	select I2C if $(dt_compat_on_bus,$(DT_COMPAT_SOLOMON_SSD1309FB),i2c)
+	select SPI if $(dt_compat_on_bus,$(DT_COMPAT_SOLOMON_SSD1309FB),spi)
 	select I2C if $(dt_compat_on_bus,$(DT_COMPAT_SINOWEALTH_SH1106),i2c)
 	select SPI if $(dt_compat_on_bus,$(DT_COMPAT_SINOWEALTH_SH1106),spi)
 	help
diff --git a/drivers/display/Kconfig.st7567 b/drivers/display/Kconfig.st7567
new file mode 100644
index 00000000000..1a8b5d7e559
--- /dev/null
+++ b/drivers/display/Kconfig.st7567
@@ -0,0 +1,22 @@
+# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig ST7567
+	bool "ST7567 display controller"
+	default y
+	depends on DT_HAS_SITRONIX_ST7567_ENABLED
+	select I2C if $(dt_compat_on_bus,$(DT_COMPAT_SITRONIX_ST7567),i2c)
+	select SPI if $(dt_compat_on_bus,$(DT_COMPAT_SITRONIX_ST7567),spi)
+	help
+	  Enable driver for ST7567 display controller.
+
+if ST7567
+
+config ST7567_DEFAULT_CONTRAST
+	int "ST7567 default contrast"
+	default 8
+	range 0 15
+	help
+	  ST7567 default contrast.
+
+endif # ST7567
diff --git a/drivers/display/Kconfig.st7701 b/drivers/display/Kconfig.st7701
new file mode 100644
index 00000000000..6a71f1f68af
--- /dev/null
+++ b/drivers/display/Kconfig.st7701
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Arduino SA
+# SPDX-License-Identifier: Apache-2.0
+
+config ST7701
+	bool "ST7701 display controller driver"
+	default y
+	depends on DT_HAS_SITRONIX_ST7701_ENABLED
+	select MIPI_DSI
+	help
+	  Enable driver for ST7701 display driver.
diff --git a/drivers/display/Kconfig.stm32_ltdc b/drivers/display/Kconfig.stm32_ltdc
index 980642edc3f..6b74d3d0e79 100644
--- a/drivers/display/Kconfig.stm32_ltdc
+++ b/drivers/display/Kconfig.stm32_ltdc
@@ -8,6 +8,7 @@ menuconfig STM32_LTDC
 	default y
 	depends on DT_HAS_ST_STM32_LTDC_ENABLED
 	select USE_STM32_HAL_LTDC
+	select USE_STM32_HAL_RIF if SOC_SERIES_STM32N6X
 	select CACHE_MANAGEMENT if CPU_HAS_DCACHE
 	select PINCTRL
 	help
@@ -52,6 +53,9 @@ config STM32_LTDC_FB_NUM
 	    - 1 single frame buffer in stm32 ltdc driver.
 	    - 2 double frame buffer in stm32 ltdc driver.
 
+config STM32_LTDC_FB_USE_SHARED_MULTI_HEAP
+	bool "Use shared multi heap for the display buffer"
+
 config STM32_LTDC_DISABLE_FMC_BANK1
 	bool "Disable FMC bank1 for STM32F7/H7 series"
 	depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32F7X
diff --git a/drivers/display/display_ili9806e_dsi.c b/drivers/display/display_ili9806e_dsi.c
index ed54d413119..6c9a59a9bd5 100644
--- a/drivers/display/display_ili9806e_dsi.c
+++ b/drivers/display/display_ili9806e_dsi.c
@@ -212,7 +212,28 @@ static int ili9806e_write_reg(const struct device *dev, uint8_t reg, const uint8
 	int ret;
 	const struct ili9806e_config *cfg = dev->config;
 
-	ret = mipi_dsi_dcs_write(cfg->mipi_dsi, cfg->channel, reg, buf, len);
+	struct mipi_dsi_msg msg = {
+		.cmd = reg,
+		.tx_buf = buf,
+		.tx_len = len,
+		.flags = MIPI_DSI_MSG_USE_LPM,
+	};
+
+	switch (len) {
+	case 0U:
+		msg.type = MIPI_DSI_DCS_SHORT_WRITE;
+		break;
+
+	case 1U:
+		msg.type = MIPI_DSI_DCS_SHORT_WRITE_PARAM;
+		break;
+
+	default:
+		msg.type = MIPI_DSI_DCS_LONG_WRITE;
+		break;
+	}
+
+	ret = mipi_dsi_transfer(cfg->mipi_dsi, cfg->channel, &msg);
 	if (ret < 0) {
 		LOG_ERR("Failed writing reg: 0x%x result: (%d)", reg, ret);
 		return ret;
@@ -384,7 +405,7 @@ static int ili9806e_init(const struct device *dev)
 		mdev.pixfmt = MIPI_DSI_PIXFMT_RGB888;
 	}
 	mdev.data_lanes = cfg->data_lanes;
-	mdev.mode_flags = MIPI_DSI_MODE_VIDEO;
+	mdev.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM;
 	mdev.timings.hactive = cfg->width;
 	mdev.timings.hbp = ILITEK_ILI9806E_HBP;
 	mdev.timings.hfp = ILITEK_ILI9806E_HFP;
diff --git a/drivers/display/display_mcux_dcnano_lcdif.c b/drivers/display/display_mcux_dcnano_lcdif.c
index b9e90438303..084cb11893e 100644
--- a/drivers/display/display_mcux_dcnano_lcdif.c
+++ b/drivers/display/display_mcux_dcnano_lcdif.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2023 NXP
+ * Copyright 2023,2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -110,6 +110,11 @@ static int mcux_dcnano_lcdif_write(const struct device *dev, const uint16_t x,
 		(uint32_t)data->active_fb);
 	LCDIF_SetFrameBufferConfig(config->base, 0, &data->fb_config);
 
+#if DT_ENUM_IDX_OR(DT_NODELABEL(lcdif), version, 0) == 1
+	LCDIF_Start(config->base);
+	LCDIF_SetUpdateReady(config->base);
+#endif
+
 #if CONFIG_MCUX_DCNANO_LCDIF_FB_NUM != 0
 	/* Update index of active framebuffer */
 	data->next_idx = (data->next_idx + 1) % CONFIG_MCUX_DCNANO_LCDIF_FB_NUM;
@@ -139,7 +144,11 @@ static void mcux_dcnano_lcdif_get_capabilities(const struct device *dev,
 		 */
 		capabilities->current_pixel_format = PIXEL_FORMAT_BGR_565;
 		break;
+#if DT_ENUM_IDX_OR(DT_NODELABEL(lcdif), version, 0) == 1
+	case kLCDIF_PixelFormatARGB8888:
+#else
 	case kLCDIF_PixelFormatXRGB8888:
+#endif
 		capabilities->current_pixel_format = PIXEL_FORMAT_ARGB_8888;
 		break;
 	default:
@@ -185,7 +194,11 @@ static int mcux_dcnano_lcdif_set_pixel_format(const struct device *dev,
 		data->pixel_bytes = 2;
 		break;
 	case PIXEL_FORMAT_ARGB_8888:
+#if DT_ENUM_IDX_OR(DT_NODELABEL(lcdif), version, 0) == 1
+		data->fb_config.format = kLCDIF_PixelFormatARGB8888;
+#else
 		data->fb_config.format = kLCDIF_PixelFormatXRGB8888;
+#endif
 		data->pixel_bytes = 4;
 		break;
 	default:
@@ -228,6 +241,13 @@ static int mcux_dcnano_lcdif_init(const struct device *dev)
 
 	LCDIF_DpiModeSetConfig(config->base, 0, &config->dpi_config);
 
+#if DT_ENUM_IDX_OR(DT_NODELABEL(lcdif), version, 0) == 1
+	lcdif_panel_config_t panel_config;
+
+	LCDIF_PanelGetDefaultConfig(&panel_config);
+	LCDIF_SetPanelConfig(config->base, 0, &panel_config);
+#endif
+
 	LCDIF_EnableInterrupts(config->base, kLCDIF_Display0FrameDoneInterrupt);
 	config->irq_config_func(dev);
 
@@ -256,7 +276,7 @@ static DEVICE_API(display, mcux_dcnano_lcdif_api) = {
 	.get_framebuffer = mcux_dcnano_lcdif_get_framebuffer,
 };
 
-#define MCUX_DCNANO_LCDIF_PIXEL_BYTES(n)                                                           \
+#define MCUX_DCNANO_LCDIF_PIXEL_BYTES(n)					\
 	(DISPLAY_BITS_PER_PIXEL(DT_INST_PROP(n, pixel_format)) / BITS_PER_BYTE)
 #define MCUX_DCNANO_LCDIF_FB_SIZE(n) DT_INST_PROP(n, width) *			\
 	DT_INST_PROP(n, height) * MCUX_DCNANO_LCDIF_PIXEL_BYTES(n)
@@ -278,6 +298,29 @@ static DEVICE_API(display, mcux_dcnano_lcdif_api) = {
 #define MCUX_DCNANO_LCDIF_FRAMEBUFFER(n) mcux_dcnano_lcdif_frame_buffer_##n
 #endif
 
+#if DT_ENUM_IDX_OR(DT_NODELABEL(lcdif), version, 0) == 1
+#define MCUX_DCNANO_LCDIF_FB_CONFIG(n)						\
+		.fb_config = {							\
+			.enable = true,						\
+			.inOrder = kLCDIF_PixelInputOrderARGB,			\
+			.rotateFlipMode = kLCDIF_Rotate0,			\
+			.alpha.enable = false,					\
+			.colorkey.enable = false,				\
+			.topLeftX = 0U,						\
+			.topLeftY = 0U,						\
+			.width = DT_INST_PROP(n, width),			\
+			.height = DT_INST_PROP(n, height),			\
+			.format = DT_INST_PROP(n, pixel_format),		\
+		},
+#else
+#define MCUX_DCNANO_LCDIF_FB_CONFIG(n)						\
+		.fb_config = {							\
+			.enable = true,						\
+			.enableGamma = false,					\
+			.format = DT_INST_PROP(n, pixel_format),		\
+		},
+#endif
+
 #define MCUX_DCNANO_LCDIF_DEVICE_INIT(n)					\
 	static void mcux_dcnano_lcdif_config_func_##n(const struct device *dev)	\
 	{									\
@@ -290,11 +333,7 @@ static DEVICE_API(display, mcux_dcnano_lcdif_api) = {
 	}									\
 	MCUX_DCNANO_LCDIF_FRAMEBUFFER_DECL(n);					\
 	struct mcux_dcnano_lcdif_data mcux_dcnano_lcdif_data_##n = {		\
-		.fb_config = {							\
-			.enable = true,						\
-			.enableGamma = false,					\
-			.format = DT_INST_PROP(n, pixel_format),		\
-		},								\
+		MCUX_DCNANO_LCDIF_FB_CONFIG(n)					\
 		.next_idx = 0,							\
 		.pixel_bytes = MCUX_DCNANO_LCDIF_PIXEL_BYTES(n),		\
 	};									\
diff --git a/drivers/display/display_mcux_elcdif.c b/drivers/display/display_mcux_elcdif.c
index 9a600421f8e..8de6fb56ab9 100644
--- a/drivers/display/display_mcux_elcdif.c
+++ b/drivers/display/display_mcux_elcdif.c
@@ -30,7 +30,8 @@ LOG_MODULE_REGISTER(display_mcux_elcdif, CONFIG_DISPLAY_LOG_LEVEL);
 /* Define the heap size. 512 bytes of padding are included for kernel heap structures */
 K_HEAP_DEFINE(display_heap, CONFIG_MCUX_ELCDIF_FB_NUM * CONFIG_MCUX_ELCDIF_FB_SIZE + 512);
 
-static const uint32_t supported_fmts = PIXEL_FORMAT_BGR_565 | PIXEL_FORMAT_ARGB_8888;
+static const uint32_t supported_fmts =
+	PIXEL_FORMAT_BGR_565 | PIXEL_FORMAT_ARGB_8888 | PIXEL_FORMAT_RGB_888;
 
 struct mcux_elcdif_config {
 	LCDIF_Type *base;
@@ -223,16 +224,26 @@ static int mcux_elcdif_write(const struct device *dev, const uint16_t x, const u
 
 static int mcux_elcdif_display_blanking_off(const struct device *dev)
 {
+	#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(backlight_gpio)
 	const struct mcux_elcdif_config *config = dev->config;
+	if (config->backlight_gpio.port) {
+		return gpio_pin_set_dt(&config->backlight_gpio, 1);
+	}
+	#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(backlight_gpio) */
 
-	return gpio_pin_set_dt(&config->backlight_gpio, 1);
+	return -ENOSYS;
 }
 
 static int mcux_elcdif_display_blanking_on(const struct device *dev)
 {
+	#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(backlight_gpio)
 	const struct mcux_elcdif_config *config = dev->config;
+	if (config->backlight_gpio.port) {
+		return gpio_pin_set_dt(&config->backlight_gpio, 0);
+	}
+	#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(backlight_gpio) */
 
-	return gpio_pin_set_dt(&config->backlight_gpio, 0);
+	return -ENOSYS;
 }
 
 static int mcux_elcdif_set_pixel_format(const struct device *dev,
@@ -327,10 +338,14 @@ static int mcux_elcdif_init(const struct device *dev)
 		return err;
 	}
 
-	err = gpio_pin_configure_dt(&config->backlight_gpio, GPIO_OUTPUT_ACTIVE);
-	if (err) {
-		return err;
+	#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(backlight_gpio)
+	if (config->backlight_gpio.port) {
+		err = gpio_pin_configure_dt(&config->backlight_gpio, GPIO_OUTPUT_ACTIVE);
+		if (err) {
+			return err;
+		}
 	}
+	#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios) */
 
 	k_sem_init(&dev_data->sem, 0, 1);
 #ifdef CONFIG_MCUX_ELCDIF_PXP
@@ -397,9 +412,9 @@ static DEVICE_API(display, mcux_elcdif_api) = {
 					DT_INST_ENUM_IDX(id, data_bus_width)),                     \
 			},                                                                         \
 		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(id),                                      \
-		.backlight_gpio = GPIO_DT_SPEC_INST_GET(id, backlight_gpios),                      \
+		.backlight_gpio = GPIO_DT_SPEC_INST_GET_OR(id, backlight_gpios, {0}),              \
 		IF_ENABLED(CONFIG_MCUX_ELCDIF_PXP,                                                 \
-			   (.pxp = DEVICE_DT_GET(DT_INST_PHANDLE(id, nxp_pxp)),))};               \
+			   (.pxp = DEVICE_DT_GET(DT_INST_PHANDLE(id, nxp_pxp)),))};                \
 	static struct mcux_elcdif_data mcux_elcdif_data_##id = {                                   \
 		.next_idx = 0,                                                                     \
 		.pixel_format = DT_INST_PROP(id, pixel_format),                                    \
diff --git a/drivers/display/display_nrf_led_matrix.c b/drivers/display/display_nrf_led_matrix.c
index 64068ea488f..79ae6652807 100644
--- a/drivers/display/display_nrf_led_matrix.c
+++ b/drivers/display/display_nrf_led_matrix.c
@@ -339,7 +339,7 @@ static void timer_irq_handler(void *arg)
 	const struct display_drv_config *dev_config = dev->config;
 	uint8_t iteration = dev_data->iteration;
 	uint8_t pixel_idx;
-	uint8_t row_idx;
+	uint8_t row_idx = 0;
 
 	/* The timer is automagically stopped and cleared by shortcuts
 	 * on the same event (COMPARE0) that generates this interrupt.
diff --git a/drivers/display/display_renesas_ra.c b/drivers/display/display_renesas_ra.c
index ea5cfdaec81..9d53aa55e83 100644
--- a/drivers/display/display_renesas_ra.c
+++ b/drivers/display/display_renesas_ra.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,7 +17,6 @@
 
 LOG_MODULE_REGISTER(display_renesas_ra, CONFIG_DISPLAY_LOG_LEVEL);
 
-void glcdc_line_detect_isr(void);
 struct display_ra_config {
 	const struct pinctrl_dev_config *pincfg;
 	const struct gpio_dt_spec backlight_gpio;
@@ -25,31 +24,40 @@ struct display_ra_config {
 	struct clock_control_ra_subsys_cfg clock_glcdc_subsys;
 	uint16_t height;
 	uint16_t width;
-	uint32_t display_frame_size;
-	enum display_pixel_format pixel_format;
 	void (*irq_configure)(void);
 };
 
 struct display_ra_data {
 	glcdc_instance_ctrl_t display_ctrl;
 	display_cfg_t display_fsp_cfg;
-	uint8_t *p_base;
-	uint32_t frame_buffer_len;
 	const uint8_t *pend_buf;
 	const uint8_t *front_buf;
 	uint8_t pixel_size;
+	enum display_pixel_format current_pixel_format;
 	uint8_t *frame_buffer;
-	struct k_sem sem;
+	uint32_t frame_buffer_len;
+	struct k_sem frame_buf_sem;
 };
 
+extern void glcdc_line_detect_isr(void);
+
 static void renesas_ra_glcdc_isr(const struct device *dev)
 {
+	ARG_UNUSED(dev);
+	glcdc_line_detect_isr();
+}
+
+static void renesas_ra_callback_adapter(display_callback_args_t *p_args)
+{
+	const struct device *dev = p_args->p_context;
 	struct display_ra_data *data = dev->data;
 
-	glcdc_line_detect_isr();
-	if (data->front_buf != data->pend_buf) {
-		data->front_buf = data->pend_buf;
-		k_sem_give(&data->sem);
+	if (p_args->event == DISPLAY_EVENT_LINE_DETECTION) {
+		if (data->front_buf != data->pend_buf) {
+			data->front_buf = data->pend_buf;
+		}
+
+		k_sem_give(&data->frame_buf_sem);
 	}
 }
 
@@ -58,24 +66,31 @@ static int ra_display_write(const struct device *dev, const uint16_t x, const ui
 {
 	struct display_ra_data *data = dev->data;
 	const struct display_ra_config *config = dev->config;
-	uint8_t *dst = NULL;
-	const uint8_t *src = buf;
 	const uint8_t *l_pend_buf = NULL;
-	uint16_t row;
-	int err;
+	bool vsync_wait = false;
+	fsp_err_t err;
 
-	__ASSERT(desc->width <= desc->pitch, "Pitch is smaller than width");
-	__ASSERT((desc->pitch * BYTE_PER_PIXEL * desc->height) <= desc->buf_size,
-		 "Input buffer too small");
+	if (desc->pitch < desc->width) {
+		LOG_ERR("Pitch is smaller than width");
+		return -EINVAL;
+	}
 
-	if (x == 0 && y == 0 && desc->height == DISPLAY_VSIZE && desc->width == DISPLAY_HSIZE &&
-	    desc->pitch == DISPLAY_HSIZE) {
+	if ((desc->pitch * data->pixel_size * desc->height) > desc->buf_size) {
+		LOG_ERR("Input buffer too small");
+		return -EINVAL;
+	}
+
+	if (x == 0 && y == 0 && desc->height == config->height && desc->width == config->width) {
 		l_pend_buf = buf;
 	} else {
-		if (CONFIG_RENESAS_RA_GLCDC_FB_NUM == 0) {
-			LOG_ERR("Partial write requires internal frame buffer");
-			return -ENOTSUP;
-		}
+#if CONFIG_RENESAS_RA_GLCDC_FB_NUM == 0
+		LOG_ERR("Partial write requires internal frame buffer");
+		return -ENOTSUP;
+#else
+		const uint8_t *src = buf;
+		uint8_t *dst = NULL;
+		uint16_t row;
+
 		dst = data->frame_buffer;
 
 		if (CONFIG_RENESAS_RA_GLCDC_FB_NUM == 2) {
@@ -99,24 +114,37 @@ static int ra_display_write(const struct device *dev, const uint16_t x, const ui
 			dst += (config->width * data->pixel_size);
 			src += (desc->pitch * data->pixel_size);
 		}
+#endif /* CONFIG_RENESAS_RA_GLCDC_FB_NUM == 0 */
 	}
 
-	if (data->front_buf == l_pend_buf) {
-		return 0;
-	}
+	k_sem_reset(&data->frame_buf_sem);
 
-	k_sem_reset(&data->sem);
+	if (data->front_buf != l_pend_buf) {
+		data->pend_buf = l_pend_buf;
 
-	data->pend_buf = l_pend_buf;
+		err = R_GLCDC_BufferChange(&data->display_ctrl, (uint8_t *)data->pend_buf,
+					   DISPLAY_FRAME_LAYER_1);
+		if (err != FSP_SUCCESS) {
+			LOG_ERR("GLCDC buffer change failed");
+			return -EIO;
+		}
 
-	err = R_GLCDC_BufferChange(&data->display_ctrl, (uint8_t *)data->pend_buf,
-				   DISPLAY_FRAME_LAYER_1);
-	if (err) {
-		LOG_ERR("GLCDC buffer change failed");
-		return -EIO;
+		vsync_wait = true;
+	}
+
+	if (data->display_ctrl.state != DISPLAY_STATE_DISPLAYING) {
+		err = R_GLCDC_Start(&data->display_ctrl);
+		if (err != FSP_SUCCESS) {
+			LOG_ERR("GLCDC start failed");
+			return -EIO;
+		}
+
+		vsync_wait = true;
 	}
 
-	k_sem_take(&data->sem, K_FOREVER);
+	if (vsync_wait) {
+		k_sem_take(&data->frame_buf_sem, K_FOREVER);
+	}
 
 	return 0;
 }
@@ -146,65 +174,179 @@ static int ra_display_read(const struct device *dev, const uint16_t x, const uin
 static int ra_display_blanking_on(const struct device *dev)
 {
 	const struct display_ra_config *config = dev->config;
-	int err;
+	int ret = 0;
 
 	if (config->backlight_gpio.port != NULL) {
-		err = gpio_pin_set_dt(&config->backlight_gpio, 0);
-		if (err) {
-			LOG_ERR("Disable backlight failed! (%d)", err);
-			return err;
-		}
+		ret = gpio_pin_set_dt(&config->backlight_gpio, 0);
 	} else {
-		return -ENOTSUP;
+		ret = -ENOTSUP;
 	}
 
-	return 0;
+	return ret;
 }
 
 static int ra_display_blanking_off(const struct device *dev)
 {
 	const struct display_ra_config *config = dev->config;
-	int err;
+	int ret = 0;
 
 	if (config->backlight_gpio.port != NULL) {
-		err = gpio_pin_set_dt(&config->backlight_gpio, 1);
-		if (err) {
-			LOG_ERR("Enable backlight failed! (%d)", err);
-			return err;
-		}
+		ret = gpio_pin_set_dt(&config->backlight_gpio, 1);
 	} else {
-		return -ENOTSUP;
+		ret = -ENOTSUP;
 	}
 
-	return 0;
+	return ret;
 }
 
 static void ra_display_get_capabilities(const struct device *dev,
 					struct display_capabilities *capabilities)
 {
 	const struct display_ra_config *config = dev->config;
+	struct display_ra_data *data = dev->data;
 
-	memset(capabilities, 0, sizeof(struct display_capabilities));
 	capabilities->x_resolution = config->width;
 	capabilities->y_resolution = config->height;
 	capabilities->current_orientation = DISPLAY_ORIENTATION_NORMAL;
 	capabilities->supported_pixel_formats =
 		PIXEL_FORMAT_RGB_888 | PIXEL_FORMAT_ARGB_8888 | PIXEL_FORMAT_RGB_565;
-	capabilities->current_pixel_format = (config->pixel_format == PIXEL_FORMAT_RGB_888)
-						     ? PIXEL_FORMAT_ARGB_8888
-						     : config->pixel_format;
+	capabilities->current_pixel_format = data->current_pixel_format;
+	capabilities->screen_info = 0U;
 }
 
 static int ra_display_set_pixel_format(const struct device *dev,
 				       const enum display_pixel_format pixel_format)
 {
 	const struct display_ra_config *config = dev->config;
+	struct display_ra_data *data = dev->data;
+	display_runtime_cfg_t layer_cfg;
+	enum display_pixel_format set_pixel_format;
+	display_in_format_t hardware_pixel_format;
+	uint32_t buf_len;
+	fsp_err_t err;
 
-	if (pixel_format == config->pixel_format) {
+	if (pixel_format == data->current_pixel_format) {
 		return 0;
 	}
-	LOG_ERR("Pixel format changes must be set in dts at build time.");
-	return -ENOTSUP;
+
+	if (data->display_ctrl.state == DISPLAY_STATE_DISPLAYING) {
+		LOG_ERR("Cannot change the display format while displaying");
+		return -EWOULDBLOCK;
+	}
+
+	switch (pixel_format) {
+	case PIXEL_FORMAT_RGB_888:
+		set_pixel_format = PIXEL_FORMAT_ARGB_8888;
+		hardware_pixel_format = DISPLAY_IN_FORMAT_32BITS_RGB888;
+		break;
+
+	case PIXEL_FORMAT_ARGB_8888:
+		set_pixel_format = PIXEL_FORMAT_ARGB_8888;
+		hardware_pixel_format = DISPLAY_IN_FORMAT_32BITS_ARGB8888;
+		break;
+
+	case PIXEL_FORMAT_RGB_565:
+		set_pixel_format = PIXEL_FORMAT_RGB_565;
+		hardware_pixel_format = DISPLAY_IN_FORMAT_16BITS_RGB565;
+		break;
+
+	default:
+		return -ENOTSUP;
+	}
+
+	buf_len = (config->height * config->width * DISPLAY_BITS_PER_PIXEL(set_pixel_format)) >> 3;
+
+	if (buf_len > data->frame_buffer_len) {
+		LOG_ERR("Frame buffer is smaller than new pixel format require");
+		return -ENOTSUP;
+	}
+
+	memcpy(&layer_cfg.input, &data->display_fsp_cfg.input[0], sizeof(display_input_cfg_t));
+	memcpy(&layer_cfg.layer, &data->display_fsp_cfg.layer[0], sizeof(display_layer_t));
+	layer_cfg.input.format = hardware_pixel_format;
+	layer_cfg.input.hstride =
+		ROUND_UP(layer_cfg.input.hsize * DISPLAY_BITS_PER_PIXEL(set_pixel_format),
+			 NUM_BITS(uint64_t)) /
+		DISPLAY_BITS_PER_PIXEL(set_pixel_format);
+
+	err = R_GLCDC_LayerChange(&data->display_ctrl, &layer_cfg, DISPLAY_FRAME_LAYER_1);
+	if (err != FSP_SUCCESS) {
+		LOG_ERR("Failed to change the pixel format");
+		return -EIO;
+	}
+
+	data->current_pixel_format = pixel_format;
+	data->pixel_size = DISPLAY_BITS_PER_PIXEL(set_pixel_format) >> 3;
+
+	return 0;
+}
+
+static int ra_display_color_config(const struct device *dev,
+				   const display_correction_t *display_color_cfg)
+{
+	struct display_ra_data *data = dev->data;
+	fsp_err_t err;
+	int ret;
+
+	err = R_GLCDC_ColorCorrection(&data->display_ctrl, display_color_cfg);
+	switch (err) {
+	case FSP_SUCCESS:
+		ret = 0;
+		break;
+	case FSP_ERR_INVALID_UPDATE_TIMING:
+		ret = -EWOULDBLOCK;
+		break;
+	default:
+		ret = -EIO;
+		break;
+	}
+
+	return ret;
+}
+
+#define RENESAS_RA_GLCDC_BRIGHTNESS_MAX 1023U
+
+static int ra_display_set_brightness(const struct device *dev, const uint8_t brightness)
+{
+	struct display_ra_data *data = dev->data;
+	const uint32_t brightness_adj =
+		DIV_ROUND_CLOSEST(brightness * RENESAS_RA_GLCDC_BRIGHTNESS_MAX, UINT8_MAX);
+	display_correction_t display_color_cfg;
+
+	if (brightness_adj == 0) {
+		return -EINVAL;
+	}
+
+	memcpy(&display_color_cfg.contrast, &data->display_fsp_cfg.output.contrast,
+	       sizeof(display_contrast_t));
+	display_color_cfg.brightness = (display_brightness_t){
+		.enable = true, .r = brightness_adj, .g = brightness_adj, .b = brightness_adj};
+
+	return ra_display_color_config(dev, &display_color_cfg);
+}
+
+static int ra_display_set_contrast(const struct device *dev, const uint8_t contrast)
+{
+	struct display_ra_data *data = dev->data;
+	display_correction_t display_color_cfg;
+
+	if (contrast == 0) {
+		return -EINVAL;
+	}
+
+	memcpy(&display_color_cfg.brightness, &data->display_fsp_cfg.output.brightness,
+	       sizeof(display_brightness_t));
+	display_color_cfg.contrast =
+		(display_contrast_t){.enable = true, .r = contrast, .g = contrast, .b = contrast};
+
+	return ra_display_color_config(dev, &display_color_cfg);
+}
+
+static void *ra_display_get_framebuffer(const struct device *dev)
+{
+	struct display_ra_data *data = dev->data;
+
+	return (void *)data->front_buf;
 }
 
 static DEVICE_API(display, display_api) = {
@@ -214,6 +356,9 @@ static DEVICE_API(display, display_api) = {
 	.set_pixel_format = ra_display_set_pixel_format,
 	.write = ra_display_write,
 	.read = ra_display_read,
+	.set_brightness = ra_display_set_brightness,
+	.set_contrast = ra_display_set_contrast,
+	.get_framebuffer = ra_display_get_framebuffer,
 };
 
 static int display_init(const struct device *dev)
@@ -235,12 +380,16 @@ static int display_init(const struct device *dev)
 	R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
 
 #endif
-	err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
-	if (err) {
-		LOG_ERR("pin function initial failed");
-		return err;
+
+	if (config->pincfg != NULL) {
+		err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
+		if (err) {
+			LOG_ERR("pin function initial failed");
+			return err;
+		}
 	}
-	k_sem_init(&data->sem, 0, 1);
+
+	k_sem_init(&data->frame_buf_sem, 0, 1);
 
 	err = clock_control_on(config->clock_dev,
 			       (clock_control_subsys_t)&config->clock_glcdc_subsys);
@@ -261,12 +410,6 @@ static int display_init(const struct device *dev)
 		return err;
 	}
 
-	err = R_GLCDC_Start(&data->display_ctrl);
-	if (err) {
-		LOG_ERR("GLCDC start failed");
-		return -EIO;
-	}
-
 	config->irq_configure();
 
 	return 0;
@@ -275,7 +418,8 @@ static int display_init(const struct device *dev)
 #define IRQ_CONFIGURE_FUNC(id)                                                                     \
 	static void glcdc_renesas_ra_configure_func_##id(void)                                     \
 	{                                                                                          \
-		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(id, line, irq)] = ELC_EVENT_GLCDC_LINE_DETECT;    \
+		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(id, line, irq)] =                                 \
+			BSP_PRV_IELS_ENUM(EVENT_GLCDC_LINE_DETECT);                                \
 		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(id, line, irq),                                    \
 			    DT_INST_IRQ_BY_NAME(id, line, priority), renesas_ra_glcdc_isr,         \
 			    DEVICE_DT_INST_GET(id), 0);                                            \
@@ -285,146 +429,83 @@ static int display_init(const struct device *dev)
 #define IRQ_CONFIGURE_DEFINE(id) .irq_configure = glcdc_renesas_ra_configure_func_##id
 
 #define RENESAS_RA_FRAME_BUFFER_LEN(id)                                                            \
-	(BYTE_PER_PIXEL * DT_INST_PROP(id, height) * DT_INST_PROP(id, width))
+	(RENESAS_RA_GLCDC_PIXEL_BYTE_SIZE(id) * DT_INST_PROP(id, height) * DT_INST_PROP(id, width))
+
+#ifdef CONFIG_RENESAS_RA_GLCDC_FRAME_BUFFER_SECTION
+#define FRAME_BUFFER_SECTION Z_GENERIC_SECTION(CONFIG_RENESAS_RA_GLCDC_FRAME_BUFFER_SECTION)
+#else
+#define FRAME_BUFFER_SECTION
+#endif /* CONFIG_RENESAS_RA_GLCDC_FRAME_BUFFER_SECTION */
+
+#define RENESAS_RA_GLCDC_DEVICE_PINCTRL_INIT(n)                                                    \
+	COND_CODE_1(DT_INST_NODE_HAS_PROP(n, pinctrl_0), (PINCTRL_DT_INST_DEFINE(n)), ())
+
+#define RENESAS_RA_GLCDC_DEVICE_PINCTRL_GET(n)                                                     \
+	COND_CODE_1(DT_INST_NODE_HAS_PROP(n, pinctrl_0), (PINCTRL_DT_INST_DEV_CONFIG_GET(n)),      \
+		    (NULL))
 
 #define RENESAS_RA_DEVICE_INIT(id)                                                                 \
-	PINCTRL_DT_INST_DEFINE(id);                                                                \
+	RENESAS_RA_GLCDC_DEVICE_PINCTRL_INIT(id);                                                  \
 	IRQ_CONFIGURE_FUNC(id)                                                                     \
-	Z_GENERIC_SECTION(".sdram")                                                                \
-	static uint8_t __aligned(64)                                                               \
+	FRAME_BUFFER_SECTION static uint8_t __aligned(64)                                          \
 	fb_background##id[CONFIG_RENESAS_RA_GLCDC_FB_NUM * RENESAS_RA_FRAME_BUFFER_LEN(id)];       \
 	static const glcdc_extended_cfg_t display_extend_cfg##id = {                               \
-		.tcon_hsync = GLCDC_TCON_PIN_1,                                                    \
-		.tcon_vsync = GLCDC_TCON_PIN_0,                                                    \
-		.tcon_de = GLCDC_TCON_PIN_2,                                                       \
+		.tcon_hsync = RENESAS_RA_GLCDC_TCON_HSYNC_PIN(id),                                 \
+		.tcon_vsync = RENESAS_RA_GLCDC_TCON_VSYNC_PIN(id),                                 \
+		.tcon_de = RENESAS_RA_GLCDC_TCON_DE_PIN(id),                                       \
 		.correction_proc_order = GLCDC_CORRECTION_PROC_ORDER_BRIGHTNESS_CONTRAST2GAMMA,    \
 		.clksrc = GLCDC_CLK_SRC_INTERNAL,                                                  \
-		.clock_div_ratio = GLCDC_PANEL_CLK_DIVISOR_8,                                      \
-		.dithering_mode = GLCDC_DITHERING_MODE_TRUNCATE,                                   \
-		.dithering_pattern_A = GLCDC_DITHERING_PATTERN_11,                                 \
-		.dithering_pattern_B = GLCDC_DITHERING_PATTERN_11,                                 \
-		.dithering_pattern_C = GLCDC_DITHERING_PATTERN_11,                                 \
-		.dithering_pattern_D = GLCDC_DITHERING_PATTERN_11,                                 \
-		.phy_layer = NULL,                                                                 \
-	};                                                                                         \
+		.clock_div_ratio = RENESAS_RA_GLCDC_OUTPUT_CLOCK_DIV(id),                          \
+		.phy_layer = NULL};                                                                \
 	static struct display_ra_data ra_data##id = {                                              \
 		.frame_buffer = fb_background##id,                                                 \
 		.frame_buffer_len = RENESAS_RA_FRAME_BUFFER_LEN(id),                               \
 		.front_buf = fb_background##id,                                                    \
 		.pend_buf = fb_background##id,                                                     \
-		.pixel_size = BYTE_PER_PIXEL,                                                      \
-		.p_base = (uint8_t *)&fb_background##id,                                           \
+		.pixel_size = RENESAS_RA_GLCDC_PIXEL_BYTE_SIZE(id),                                \
+		.current_pixel_format = RENESAS_RA_DISPLAY_GET_PIXEL_FORMAT(id),                   \
 		.display_fsp_cfg = {                                                               \
-			.input[0] = {.p_base = (uint32_t *)&fb_background##id,                     \
-				     .hsize = DISPLAY_HSIZE,                                       \
-				     .vsize = DISPLAY_VSIZE,                                       \
-				     .hstride = DISPLAY_BUFFER_STRIDE_PIXELS_INPUT0,               \
-				     .format =                                                     \
-					     (INPUT_FORMAT_PIXEL == PANEL_PIXEL_FORMAT_RGB_565)    \
-						     ? DISPLAY_IN_FORMAT_16BITS_RGB565             \
-					     : (INPUT_FORMAT_PIXEL == PANEL_PIXEL_FORMAT_RGB_888)  \
-						     ? DISPLAY_IN_FORMAT_32BITS_RGB888             \
-						     : DISPLAY_IN_FORMAT_32BITS_ARGB8888,          \
-				     .line_descending_enable = false,                              \
-				     .lines_repeat_enable = false,                                 \
-				     .lines_repeat_times = 0},                                     \
-			.input[1] = {.p_base = NULL,                                               \
-				     .hsize = DISPLAY_HSIZE,                                       \
-				     .vsize = DISPLAY_VSIZE,                                       \
-				     .hstride = DISPLAY_BUFFER_STRIDE_PIXELS_INPUT1,               \
-				     .format = DISPLAY_IN_FORMAT_16BITS_RGB565,                    \
+			.input[0] = {.p_base = (uint32_t *)fb_background##id,                      \
+				     .hsize = DISPLAY_HSIZE(id),                                   \
+				     .vsize = DISPLAY_VSIZE(id),                                   \
+				     .hstride = RENESAS_RA_DISPLAY_BUFFER_HSTRIDE_BYTE(id),        \
+				     .format = RENESAS_RA_GLCDC_IN_PIXEL_FORMAT(id),               \
 				     .line_descending_enable = false,                              \
 				     .lines_repeat_enable = false,                                 \
 				     .lines_repeat_times = 0},                                     \
 			.layer[0] = {.coordinate = {.x = 0, .y = 0},                               \
-				     .bg_color = {.byte = {.a = LAYER_ALPHA,                       \
-							   .r = LAYER_RED,                         \
-							   .g = LAYER_GREEN,                       \
-							   .b = LAYER_BLUE}},                      \
-				     .fade_control = DISPLAY_FADE_CONTROL_NONE,                    \
-				     .fade_speed = 0},                                             \
-			.layer[1] = {.coordinate = {.x = 0, .y = 0},                               \
-				     .bg_color = {.byte = {.a = LAYER_ALPHA,                       \
-							   .r = LAYER_RED,                         \
-							   .g = LAYER_GREEN,                       \
-							   .b = LAYER_BLUE}},                      \
+				     .bg_color = RENESAS_RA_GLCDC_BG_COLOR(id),                    \
 				     .fade_control = DISPLAY_FADE_CONTROL_NONE,                    \
 				     .fade_speed = 0},                                             \
-			.output = {.htiming = {.total_cyc =                                        \
-						       DT_INST_PROP(id, width) +                   \
-						       DT_PROP(DT_INST_CHILD(id, display_timings), \
-							       hback_porch) +                      \
-						       DT_PROP(DT_INST_CHILD(id, display_timings), \
-							       hfront_porch) +                     \
-						       DT_PROP(DT_INST_CHILD(id, display_timings), \
-							       hsync_len),                         \
-					       .display_cyc = DT_INST_PROP(id, width),             \
-					       .back_porch =                                       \
-						       DT_PROP(DT_INST_CHILD(id, display_timings), \
-							       hback_porch),                       \
-					       .sync_width =                                       \
-						       DT_PROP(DT_INST_CHILD(id, display_timings), \
-							       hsync_len),                         \
-					       .sync_polarity =                                    \
-						       DT_PROP(DT_INST_CHILD(id, display_timings), \
-							       hsync_active)},                     \
-				   .vtiming = {.total_cyc =                                        \
-						       DT_INST_PROP(id, height) +                  \
-						       DT_PROP(DT_INST_CHILD(id, display_timings), \
-							       vback_porch) +                      \
-						       DT_PROP(DT_INST_CHILD(id, display_timings), \
-							       vfront_porch) +                     \
-						       DT_PROP(DT_INST_CHILD(id, display_timings), \
-							       vsync_len),                         \
-					       .display_cyc = DT_INST_PROP(id, height),            \
-					       .back_porch =                                       \
-						       DT_PROP(DT_INST_CHILD(id, display_timings), \
-							       vback_porch),                       \
-					       .sync_width =                                       \
-						       DT_PROP(DT_INST_CHILD(id, display_timings), \
-							       vsync_len),                         \
-					       .sync_polarity =                                    \
-						       DT_PROP(DT_INST_CHILD(id, display_timings), \
-							       vsync_active)},                     \
-				   .format = (OUTPUT_FORMAT_PIXEL == PANEL_PIXEL_FORMAT_RGB_565)   \
-						     ? DISPLAY_OUT_FORMAT_16BITS_RGB565            \
-						     : DISPLAY_OUT_FORMAT_24BITS_RGB888,           \
-				   .endian = DISPLAY_ENDIAN_LITTLE,                                \
-				   .color_order = DISPLAY_COLOR_ORDER_RGB,                         \
-				   .data_enable_polarity = DISPLAY_SIGNAL_POLARITY_HIACTIVE,       \
-				   .sync_edge = DISPLAY_SIGNAL_SYNC_EDGE_FALLING,                  \
-				   .bg_color = {.byte = {.a = OUTPUT_ALPHA,                        \
-							 .r = OUTPUT_RED,                          \
-							 .g = OUTPUT_GREEN,                        \
-							 .b = OUTPUT_BLUE}},                       \
-				   .brightness = {.enable = false,                                 \
-						  .r = OUTPUT_RED,                                 \
-						  .g = OUTPUT_GREEN,                               \
-						  .b = OUTPUT_BLUE},                               \
-				   .contrast = {.enable = false,                                   \
-						.r = OUTPUT_RED,                                   \
-						.g = OUTPUT_GREEN,                                 \
-						.b = OUTPUT_BLUE},                                 \
+			.input[1] = {.p_base = NULL},                                              \
+			.output = {.htiming = RENESAS_RA_GLCDC_HTIMING(id),                        \
+				   .vtiming = RENESAS_RA_GLCDC_VTIMING(id),                        \
+				   .format = RENESAS_RA_GLCDC_OUT_PIXEL_FORMAT(id),                \
+				   .endian = RENESAS_RA_GLCDC_OUTPUT_ENDIAN(id),                   \
+				   .color_order = RENESAS_RA_GLCDC_OUTPUT_COLOR_ODER(id),          \
+				   .data_enable_polarity =                                         \
+					   RENESAS_RA_GLCDC_OUTPUT_DE_POLARITY(id),                \
+				   .sync_edge = RENESAS_RA_GLCDC_OUTPUT_SYNC_EDGE(id),             \
+				   .bg_color = RENESAS_RA_GLCDC_BG_COLOR(id),                      \
+				   .brightness = {.enable = false},                                \
+				   .contrast = {.enable = false},                                  \
 				   .dithering_on = false},                                         \
-			.p_callback = NULL,                                                        \
-			.p_context = NULL,                                                         \
+			.p_callback = renesas_ra_callback_adapter,                                 \
+			.p_context = DEVICE_DT_INST_GET(id),                                       \
 			.p_extend = (void *)(&display_extend_cfg##id),                             \
-			.line_detect_ipl = BSP_IRQ_DISABLED,                                       \
-			.underflow_1_ipl = BSP_IRQ_DISABLED,                                       \
-			.underflow_2_ipl = BSP_IRQ_DISABLED}};                                     \
+			.line_detect_irq = DT_INST_IRQ_BY_NAME(id, line, irq),                     \
+			.line_detect_ipl = DT_INST_IRQ_BY_NAME(id, line, priority),                \
+			.underflow_1_irq = BSP_IRQ_DISABLED,                                       \
+			.underflow_2_irq = BSP_IRQ_DISABLED}};                                     \
 	static struct display_ra_config ra_config##id = {                                          \
 		IRQ_CONFIGURE_DEFINE(id),                                                          \
-		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(id),                                      \
-		.backlight_gpio = GPIO_DT_SPEC_INST_GET(id, backlight_gpios),                      \
+		.pincfg = RENESAS_RA_GLCDC_DEVICE_PINCTRL_GET(id),                                 \
+		.backlight_gpio = GPIO_DT_SPEC_INST_GET_OR(id, backlight_gpios, NULL),             \
 		.height = DT_INST_PROP(id, height),                                                \
 		.width = DT_INST_PROP(id, width),                                                  \
-		.pixel_format = DT_INST_PROP(id, input_pixel_format),                              \
-		.display_frame_size =                                                              \
-			(DT_INST_PROP(id, width)) * (DT_INST_PROP(id, height)) * BYTE_PER_PIXEL,   \
 		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)),                               \
 		.clock_glcdc_subsys = {.mstp = (uint32_t)DT_INST_CLOCKS_CELL_BY_IDX(id, 0, mstp),  \
-				       .stop_bit = DT_INST_CLOCKS_CELL_BY_IDX(id, 0, stop_bit)},   \
-	};                                                                                         \
+				       .stop_bit = DT_INST_CLOCKS_CELL_BY_IDX(id, 0, stop_bit)}};  \
 	DEVICE_DT_INST_DEFINE(id, &display_init, NULL, &ra_data##id, &ra_config##id, POST_KERNEL,  \
 			      CONFIG_DISPLAY_INIT_PRIORITY, &display_api);
 
diff --git a/drivers/display/display_renesas_ra.h b/drivers/display/display_renesas_ra.h
index e3cddbcc3b7..d7695255fc3 100644
--- a/drivers/display/display_renesas_ra.h
+++ b/drivers/display/display_renesas_ra.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,42 +9,92 @@
 
 #include <zephyr/drivers/display.h>
 
-#define INPUT_FORMAT_PIXEL  DT_INST_PROP(0, input_pixel_format)
-#define OUTPUT_FORMAT_PIXEL DT_INST_PROP(0, output_pixel_format)
-
-#if (INPUT_FORMAT_PIXEL == PANEL_PIXEL_FORMAT_RGB_565)
-#define BYTE_PER_PIXEL                (2)
-#define DISPLAY_BITS_PER_PIXEL_INPUT0 (16)
-#elif (INPUT_FORMAT_PIXEL == PANEL_PIXEL_FORMAT_RGB_888)
-#define BYTE_PER_PIXEL                (4)
-#define DISPLAY_BITS_PER_PIXEL_INPUT0 (32)
-#elif (INPUT_FORMAT_PIXEL == PANEL_PIXEL_FORMAT_ARGB_8888)
-#define BYTE_PER_PIXEL                (4)
-#define DISPLAY_BITS_PER_PIXEL_INPUT0 (32)
-#endif
-
-#define DISPLAY_BITS_PER_PIXEL_INPUT1 (16)
-#define DISPLAY_HSIZE                 DT_INST_PROP(0, width)
-#define DISPLAY_VSIZE                 DT_INST_PROP(0, height)
-#define DISPLAY_BUFFER_STRIDE_BYTES_INPUT0                                                         \
-	(((DISPLAY_HSIZE * DISPLAY_BITS_PER_PIXEL_INPUT0 + 0x1FF) >> 9) << 6)
-#define DISPLAY_BUFFER_STRIDE_PIXELS_INPUT0                                                        \
-	((DISPLAY_BUFFER_STRIDE_BYTES_INPUT0 * 8) / DISPLAY_BITS_PER_PIXEL_INPUT0)
-#define DISPLAY_BUFFER_STRIDE_BYTES_INPUT1                                                         \
-	(((DISPLAY_HSIZE * DISPLAY_BITS_PER_PIXEL_INPUT1 + 0x1FF) >> 9) << 6)
-#define DISPLAY_BUFFER_STRIDE_PIXELS_INPUT1                                                        \
-	((DISPLAY_BUFFER_STRIDE_BYTES_INPUT1 * 8) / DISPLAY_BITS_PER_PIXEL_INPUT1)
-
-#define LAYER_GREEN          (255)
-#define LAYER_RED            (255)
-#define LAYER_BLUE           (255)
-#define LAYER_ALPHA          (255)
-#define OUTPUT_GREEN         (0)
-#define OUTPUT_RED           (0)
-#define OUTPUT_BLUE          (0)
-#define OUTPUT_ALPHA         (255)
-#define GLCDC_BRIGHTNESS_MAX (1023U)
-#define BRIGHTNESS_MAX       (255U)
-#define GLCDC_CONTRAST_MAX   (255U)
+#define ROUND_UP_64BYTES(x)    ROUND_UP(x, NUM_BITS(uint64_t))
+#define INPUT_FORMAT_PIXEL(n)  DT_INST_PROP(n, input_pixel_format)
+#define OUTPUT_FORMAT_PIXEL(n) DT_INST_PROP(n, output_pixel_format)
+
+#define RENESAS_RA_GLCDC_IN_PIXEL_FORMAT_1  (DISPLAY_IN_FORMAT_32BITS_RGB888)
+#define RENESAS_RA_GLCDC_IN_PIXEL_FORMAT_8  (DISPLAY_IN_FORMAT_32BITS_ARGB8888)
+#define RENESAS_RA_GLCDC_IN_PIXEL_FORMAT_16 (DISPLAY_IN_FORMAT_16BITS_RGB565)
+
+#define RENESAS_RA_GLCDC_OUT_PIXEL_FORMAT_1  (DISPLAY_OUT_FORMAT_24BITS_RGB888)
+#define RENESAS_RA_GLCDC_OUT_PIXEL_FORMAT_16 (DISPLAY_OUT_FORMAT_16BITS_RGB565)
+
+#define RENESAS_RA_DISPLAY_GET_PIXEL_FORMAT(n)                                                     \
+	(DT_INST_PROP(n, input_pixel_format) == PANEL_PIXEL_FORMAT_RGB_888                         \
+		 ? PANEL_PIXEL_FORMAT_ARGB_8888                                                    \
+		 : DT_INST_PROP(n, input_pixel_format))
+
+#define DISPLAY_HSIZE(n) (DT_INST_PROP(n, width))
+#define DISPLAY_VSIZE(n) (DT_INST_PROP(n, height))
+
+#define RENESAS_RA_GLCDC_IN_PIXEL_FORMAT(n)                                                        \
+	UTIL_CAT(RENESAS_RA_GLCDC_IN_PIXEL_FORMAT_, INPUT_FORMAT_PIXEL(n))
+
+#define RENESAS_RA_GLCDC_OUT_PIXEL_FORMAT(n)                                                       \
+	UTIL_CAT(RENESAS_RA_GLCDC_OUT_PIXEL_FORMAT_, OUTPUT_FORMAT_PIXEL(n))
+
+#define RENESAS_RA_GLCDC_PIXEL_BYTE_SIZE(n)                                                        \
+	(DISPLAY_BITS_PER_PIXEL(RENESAS_RA_DISPLAY_GET_PIXEL_FORMAT(n)) >> 3)
+
+#define RENESAS_RA_DISPLAY_BUFFER_HSTRIDE_BYTE(n)                                                  \
+	(ROUND_UP_64BYTES(DISPLAY_HSIZE(n) * DISPLAY_BITS_PER_PIXEL(INPUT_FORMAT_PIXEL(n))) /      \
+	 DISPLAY_BITS_PER_PIXEL(INPUT_FORMAT_PIXEL(n)))
+
+#define RENESAS_RA_GLCDC_HTIMING(n)                                                                \
+	{.total_cyc = DT_INST_PROP(n, width) +                                                     \
+		      DT_PROP(DT_INST_CHILD(n, display_timings), hback_porch) +                    \
+		      DT_PROP(DT_INST_CHILD(n, display_timings), hfront_porch) +                   \
+		      DT_PROP(DT_INST_CHILD(n, display_timings), hsync_len),                       \
+	 .display_cyc = DT_INST_PROP(n, width),                                                    \
+	 .back_porch = DT_PROP(DT_INST_CHILD(n, display_timings), hback_porch),                    \
+	 .sync_width = DT_PROP(DT_INST_CHILD(n, display_timings), hsync_len),                      \
+	 .sync_polarity = DT_PROP(DT_INST_CHILD(n, display_timings), hsync_active)}
+
+#define RENESAS_RA_GLCDC_VTIMING(n)                                                                \
+	{.total_cyc = DT_INST_PROP(n, height) +                                                    \
+		      DT_PROP(DT_INST_CHILD(n, display_timings), vback_porch) +                    \
+		      DT_PROP(DT_INST_CHILD(n, display_timings), vfront_porch) +                   \
+		      DT_PROP(DT_INST_CHILD(n, display_timings), vsync_len),                       \
+	 .display_cyc = DT_INST_PROP(n, height),                                                   \
+	 .back_porch = DT_PROP(DT_INST_CHILD(n, display_timings), vback_porch),                    \
+	 .sync_width = DT_PROP(DT_INST_CHILD(n, display_timings), vsync_len),                      \
+	 .sync_polarity = DT_PROP(DT_INST_CHILD(n, display_timings), vsync_active)}
+
+#define RENESAS_RA_GLCDC_OUTPUT_ENDIAN(n)                                                          \
+	UTIL_CAT(DISPLAY_ENDIAN_, DT_INST_STRING_UPPER_TOKEN_OR(n, output_endian, LITTLE))
+
+#define RENESAS_RA_GLCDC_OUTPUT_COLOR_ODER(n)                                                      \
+	UTIL_CAT(DISPLAY_COLOR_ORDER_, DT_INST_STRING_UPPER_TOKEN_OR(n, output_color_oder, RGB))
+
+#define RENESAS_RA_GLCDC_OUTPUT_DE_POLARITY(n)                                                     \
+	UTIL_CAT(DISPLAY_SIGNAL_POLARITY_,                                                         \
+		 DT_INST_STRING_UPPER_TOKEN_OR(n, output_data_signal_polarity, HIACTIVE))
+
+#define RENESAS_RA_GLCDC_OUTPUT_SYNC_EDGE(n)                                                       \
+	UTIL_CAT(DISPLAY_SIGNAL_SYNC_EDGE_,                                                        \
+		 DT_INST_STRING_UPPER_TOKEN_OR(n, output_signal_sync_edge, FALLING))
+
+#define RENESAS_RA_GLCDC_BG_COLOR(n)                                                               \
+	{                                                                                          \
+		.byte = {                                                                          \
+			.a = DT_INST_PROP_OR(n, def_back_color_alpha, 255),                        \
+			.r = DT_INST_PROP_OR(n, def_back_color_red, 255),                          \
+			.g = DT_INST_PROP_OR(n, def_back_color_green, 255),                        \
+			.b = DT_INST_PROP_OR(n, def_back_color_blue, 255)                          \
+		}                                                                                  \
+	}
+
+#define RENESAS_RA_GLCDC_TCON_HSYNC_PIN(n)                                                         \
+	UTIL_CAT(GLCDC_, DT_INST_STRING_UPPER_TOKEN_OR(n, output_pin_hsync, TCON_PIN_1))
+
+#define RENESAS_RA_GLCDC_TCON_VSYNC_PIN(n)                                                         \
+	UTIL_CAT(GLCDC_, DT_INST_STRING_UPPER_TOKEN_OR(n, output_pin_vsync, TCON_PIN_0))
+
+#define RENESAS_RA_GLCDC_TCON_DE_PIN(n)                                                            \
+	UTIL_CAT(GLCDC_, DT_INST_STRING_UPPER_TOKEN_OR(n, output_pin_de, TCON_PIN_2))
+
+#define RENESAS_RA_GLCDC_OUTPUT_CLOCK_DIV(n)                                                       \
+	UTIL_CAT(GLCDC_PANEL_CLK_DIVISOR_, DT_INST_PROP_OR(n, output_clock_divisor, 8))
 
 #endif /* ZEPHYR_DRIVERS_DISPLAY_RENESAS_RA_H_ */
diff --git a/drivers/display/display_sdl.c b/drivers/display/display_sdl.c
index bbae94c75e0..e24e6ea6692 100644
--- a/drivers/display/display_sdl.c
+++ b/drivers/display/display_sdl.c
@@ -7,8 +7,10 @@
 
 #define DT_DRV_COMPAT zephyr_sdl_dc
 
+#include <zephyr/kernel.h>
 #include <zephyr/drivers/display.h>
 
+#include <nsi_tracing.h>
 #include <string.h>
 #include <stdlib.h>
 #include <soc.h>
@@ -22,6 +24,26 @@ LOG_MODULE_REGISTER(display_sdl);
 
 static uint32_t sdl_display_zoom_pct;
 
+enum sdl_display_op {
+	SDL_WRITE,
+	SDL_BLANKING_OFF,
+	SDL_BLANKING_ON,
+};
+
+struct sdl_display_write {
+	uint16_t x;
+	uint16_t y;
+	const struct display_buffer_descriptor *desc;
+};
+
+struct sdl_display_task {
+	enum sdl_display_op op;
+	union {
+		struct sdl_display_write write;
+	};
+};
+
+
 struct sdl_display_config {
 	uint16_t height;
 	uint16_t width;
@@ -38,6 +60,12 @@ struct sdl_display_data {
 	enum display_pixel_format current_pixel_format;
 	uint8_t *buf;
 	uint8_t *read_buf;
+	struct k_thread sdl_thread;
+
+	K_KERNEL_STACK_MEMBER(sdl_thread_stack, CONFIG_ARCH_POSIX_RECOMMENDED_STACK_SIZE);
+	struct k_msgq *task_msgq;
+	struct k_sem task_sem;
+	struct k_mutex task_mutex;
 };
 
 static inline uint32_t mono_pixel_order(uint32_t order)
@@ -49,14 +77,73 @@ static inline uint32_t mono_pixel_order(uint32_t order)
 	}
 }
 
-static int sdl_display_init(const struct device *dev)
+static void exec_sdl_task(const struct device *dev, const struct sdl_display_task *task)
 {
+	struct sdl_display_data *disp_data = dev->data;
+
+	switch (task->op) {
+	case SDL_WRITE:
+		sdl_display_write_bottom(task->write.desc->height, task->write.desc->width,
+					 task->write.x, task->write.y, disp_data->renderer,
+					 disp_data->mutex, disp_data->texture,
+					 disp_data->background_texture, disp_data->buf,
+					 disp_data->display_on,
+					 task->write.desc->frame_incomplete);
+		break;
+	case SDL_BLANKING_OFF:
+		sdl_display_blanking_off_bottom(disp_data->renderer, disp_data->texture,
+						disp_data->background_texture);
+		break;
+	case SDL_BLANKING_ON:
+		sdl_display_blanking_on_bottom(disp_data->renderer);
+		break;
+	default:
+		LOG_ERR("Unknown SDL task");
+		break;
+	}
+}
+
+static void sdl_task_thread(void *p1, void *p2, void *p3)
+{
+	const struct device *dev = p1;
+	struct sdl_display_data *disp_data = dev->data;
 	const struct sdl_display_config *config = dev->config;
+	struct sdl_display_task task;
+	bool use_accelerator =
+		IS_ENABLED(CONFIG_SDL_DISPLAY_USE_HARDWARE_ACCELERATOR);
+
+	if (sdl_display_zoom_pct == UINT32_MAX) {
+		sdl_display_zoom_pct = CONFIG_SDL_DISPLAY_ZOOM_PCT;
+	}
+
+	int rc = sdl_display_init_bottom(config->height, config->width, sdl_display_zoom_pct,
+					 use_accelerator, &disp_data->window, dev,
+					 &disp_data->renderer, &disp_data->mutex,
+					 &disp_data->texture, &disp_data->read_texture,
+					 &disp_data->background_texture,
+					 CONFIG_SDL_DISPLAY_TRANSPARENCY_GRID_CELL_COLOR_1,
+					 CONFIG_SDL_DISPLAY_TRANSPARENCY_GRID_CELL_COLOR_2,
+					 CONFIG_SDL_DISPLAY_TRANSPARENCY_GRID_CELL_SIZE);
+
+	if (rc != 0) {
+		nsi_print_error_and_exit("Failed to create SDL display");
+		return;
+	}
+
+	disp_data->display_on = false;
+
+	while (1) {
+		k_msgq_get(disp_data->task_msgq, &task, K_FOREVER);
+		exec_sdl_task(dev, &task);
+		k_sem_give(&disp_data->task_sem);
+	}
+}
+
+static int sdl_display_init(const struct device *dev)
+{
 	struct sdl_display_data *disp_data = dev->data;
-	bool use_accelerator = true;
-	LOG_DBG("Initializing display driver");
 
-	IF_DISABLED(CONFIG_SDL_DISPLAY_USE_HARDWARE_ACCELERATOR, (use_accelerator = false));
+	LOG_DBG("Initializing display driver");
 
 	disp_data->current_pixel_format =
 #if defined(CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_RGB_888)
@@ -69,29 +156,19 @@ static int sdl_display_init(const struct device *dev)
 		PIXEL_FORMAT_RGB_565
 #elif defined(CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_BGR_565)
 		PIXEL_FORMAT_BGR_565
-#else /* SDL_DISPLAY_DEFAULT_PIXEL_FORMAT */
+#elif defined(CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_L_8)
+		PIXEL_FORMAT_L_8
+#else  /* SDL_DISPLAY_DEFAULT_PIXEL_FORMAT */
 		PIXEL_FORMAT_ARGB_8888
 #endif /* SDL_DISPLAY_DEFAULT_PIXEL_FORMAT */
 		;
 
-	if (sdl_display_zoom_pct == UINT32_MAX) {
-		sdl_display_zoom_pct = CONFIG_SDL_DISPLAY_ZOOM_PCT;
-	}
-
-	int rc = sdl_display_init_bottom(config->height, config->width, sdl_display_zoom_pct,
-					 use_accelerator, &disp_data->window, &disp_data->renderer,
-					 &disp_data->mutex, &disp_data->texture,
-					 &disp_data->read_texture, &disp_data->background_texture,
-					 CONFIG_SDL_DISPLAY_TRANSPARENCY_GRID_CELL_COLOR_1,
-					 CONFIG_SDL_DISPLAY_TRANSPARENCY_GRID_CELL_COLOR_2,
-					 CONFIG_SDL_DISPLAY_TRANSPARENCY_GRID_CELL_SIZE);
-
-	if (rc != 0) {
-		LOG_ERR("Failed to create SDL display");
-		return -EIO;
-	}
-
-	disp_data->display_on = false;
+	k_sem_init(&disp_data->task_sem, 0, 1);
+	k_mutex_init(&disp_data->task_mutex);
+	k_thread_create(&disp_data->sdl_thread, disp_data->sdl_thread_stack,
+			K_KERNEL_STACK_SIZEOF(disp_data->sdl_thread_stack),
+			sdl_task_thread, (void *)dev, NULL, NULL,
+			CONFIG_SDL_DISPLAY_THREAD_PRIORITY, 0, K_NO_WAIT);
 
 	return 0;
 }
@@ -202,24 +279,62 @@ static void sdl_display_write_mono(uint8_t *disp_buf,
 		one_color = 0x00FFFFFF;
 	}
 
-	for (tile_idx = 0U; tile_idx < desc->height/8U; ++tile_idx) {
-		for (w_idx = 0U; w_idx < desc->width; ++w_idx) {
-			byte_ptr = (const uint8_t *)buf +
-				((tile_idx * desc->pitch) + w_idx);
-			disp_buf_start = disp_buf;
-			for (h_idx = 0U; h_idx < 8; ++h_idx) {
-				if ((*byte_ptr & mono_pixel_order(h_idx)) != 0U)  {
-					pixel = one_color;
-				} else {
-					pixel = ~one_color;
+	if (IS_ENABLED(CONFIG_SDL_DISPLAY_MONO_VTILED)) {
+		for (tile_idx = 0U; tile_idx < desc->height / 8U; ++tile_idx) {
+			for (w_idx = 0U; w_idx < desc->width; ++w_idx) {
+				byte_ptr =
+					(const uint8_t *)buf + ((tile_idx * desc->pitch) + w_idx);
+				disp_buf_start = disp_buf;
+				for (h_idx = 0U; h_idx < 8; ++h_idx) {
+					if ((*byte_ptr & mono_pixel_order(h_idx)) != 0U) {
+						pixel = one_color;
+					} else {
+						pixel = ~one_color;
+					}
+					*((uint32_t *)disp_buf) = pixel | 0xFF000000;
+					disp_buf += (desc->width * 4U);
 				}
-				*((uint32_t *)disp_buf) = pixel | 0xFF000000;
-				disp_buf += (desc->width * 4U);
+				disp_buf = disp_buf_start;
+				disp_buf += 4;
 			}
-			disp_buf = disp_buf_start;
+			disp_buf += 7 * (desc->width * 4U);
+		}
+	} else {
+		for (h_idx = 0; h_idx < desc->height; h_idx++) {
+			for (tile_idx = 0; tile_idx < desc->width / 8; tile_idx++) {
+				byte_ptr = (const uint8_t *)buf +
+					   ((h_idx * desc->width / 8) + tile_idx);
+				for (w_idx = 0; w_idx < 8; w_idx++) {
+					if ((*byte_ptr & mono_pixel_order(w_idx)) != 0U) {
+						pixel = one_color;
+					} else {
+						pixel = ~one_color;
+					}
+					*((uint32_t *)disp_buf + w_idx) = pixel | 0xFF000000;
+				}
+				disp_buf += 8 * sizeof(uint32_t);
+			}
+		}
+	}
+}
+
+static void sdl_display_write_l8(uint8_t *disp_buf, const struct display_buffer_descriptor *desc,
+				 const void *buf)
+{
+	uint32_t w_idx;
+	uint32_t h_idx;
+	uint32_t pixel;
+	const uint8_t *byte_ptr;
+
+	__ASSERT((desc->pitch * desc->height) <= desc->buf_size, "Input buffer too small");
+
+	for (h_idx = 0U; h_idx < desc->height; ++h_idx) {
+		for (w_idx = 0U; w_idx < desc->width; ++w_idx) {
+			byte_ptr = (const uint8_t *)buf + ((h_idx * desc->pitch) + w_idx);
+			pixel = *byte_ptr;
+			*((uint32_t *)disp_buf) = pixel | (pixel << 8) | (pixel << 16) | 0xFF000000;
 			disp_buf += 4;
 		}
-		disp_buf += 7 * (desc->width * 4U);
 	}
 }
 
@@ -230,6 +345,14 @@ static int sdl_display_write(const struct device *dev, const uint16_t x,
 {
 	const struct sdl_display_config *config = dev->config;
 	struct sdl_display_data *disp_data = dev->data;
+	struct sdl_display_task task = {
+		.op = SDL_WRITE,
+		.write = {
+			.x = x,
+			.y = y,
+			.desc = desc,
+		},
+	};
 
 	LOG_DBG("Writing %dx%d (w,h) bitmap @ %dx%d (x,y)", desc->width,
 			desc->height, x, y);
@@ -250,6 +373,7 @@ static int sdl_display_write(const struct device *dev, const uint16_t x,
 		return -EINVAL;
 	}
 
+	k_mutex_lock(&disp_data->task_mutex, K_FOREVER);
 	if (disp_data->current_pixel_format == PIXEL_FORMAT_ARGB_8888) {
 		sdl_display_write_argb8888(disp_data->buf, desc, buf);
 	} else if (disp_data->current_pixel_format == PIXEL_FORMAT_RGB_888) {
@@ -262,12 +386,18 @@ static int sdl_display_write(const struct device *dev, const uint16_t x,
 		sdl_display_write_rgb565(disp_data->buf, desc, buf);
 	} else if (disp_data->current_pixel_format == PIXEL_FORMAT_BGR_565) {
 		sdl_display_write_bgr565(disp_data->buf, desc, buf);
+	} else if (disp_data->current_pixel_format == PIXEL_FORMAT_L_8) {
+		sdl_display_write_l8(disp_data->buf, desc, buf);
+	}
+
+	if (k_current_get() == &disp_data->sdl_thread) {
+		exec_sdl_task(dev, &task);
+	} else {
+		k_msgq_put(disp_data->task_msgq, &task, K_FOREVER);
+		k_sem_take(&disp_data->task_sem, K_FOREVER);
 	}
 
-	sdl_display_write_bottom(desc->height, desc->width, x, y, disp_data->renderer,
-				 disp_data->mutex, disp_data->texture,
-				 disp_data->background_texture, disp_data->buf,
-				 disp_data->display_on, desc->frame_incomplete);
+	k_mutex_unlock(&disp_data->task_mutex);
 
 	return 0;
 }
@@ -388,10 +518,29 @@ static void sdl_display_read_mono(const uint8_t *read_buf,
 	}
 }
 
-static int sdl_display_read(const struct device *dev, const uint16_t x,
-			    const uint16_t y,
-			    const struct display_buffer_descriptor *desc,
-			    void *buf)
+static void sdl_display_read_l8(const uint8_t *read_buf,
+				const struct display_buffer_descriptor *desc, void *buf)
+{
+	uint32_t w_idx;
+	uint32_t h_idx;
+	uint8_t *buf8;
+	const uint32_t *pix_ptr;
+
+	__ASSERT((desc->pitch * desc->height) <= desc->buf_size, "Read buffer is too small");
+
+	for (h_idx = 0U; h_idx < desc->height; ++h_idx) {
+		buf8 = ((uint8_t *)buf) + desc->pitch * h_idx;
+
+		for (w_idx = 0U; w_idx < desc->width; ++w_idx) {
+			pix_ptr = (const uint32_t *)read_buf + ((h_idx * desc->pitch) + w_idx);
+			*buf8 = *pix_ptr & 0xFF;
+			buf8 += 1;
+		}
+	}
+}
+
+static int sdl_display_read(const struct device *dev, const uint16_t x, const uint16_t y,
+			    const struct display_buffer_descriptor *desc, void *buf)
 {
 	struct sdl_display_data *disp_data = dev->data;
 	int err;
@@ -401,6 +550,7 @@ static int sdl_display_read(const struct device *dev, const uint16_t x,
 
 	__ASSERT(desc->width <= desc->pitch, "Pitch is smaller than width");
 
+	k_mutex_lock(&disp_data->task_mutex, K_FOREVER);
 	memset(disp_data->read_buf, 0, desc->pitch * desc->height * 4);
 
 	err = sdl_display_read_bottom(desc->height, desc->width, x, y, disp_data->renderer,
@@ -408,6 +558,7 @@ static int sdl_display_read(const struct device *dev, const uint16_t x,
 				      disp_data->texture, disp_data->read_texture);
 
 	if (err) {
+		k_mutex_unlock(&disp_data->task_mutex);
 		return err;
 	}
 
@@ -423,7 +574,52 @@ static int sdl_display_read(const struct device *dev, const uint16_t x,
 		sdl_display_read_rgb565(disp_data->read_buf, desc, buf);
 	} else if (disp_data->current_pixel_format == PIXEL_FORMAT_BGR_565) {
 		sdl_display_read_bgr565(disp_data->read_buf, desc, buf);
+	} else if (disp_data->current_pixel_format == PIXEL_FORMAT_L_8) {
+		sdl_display_read_l8(disp_data->read_buf, desc, buf);
+	}
+	k_mutex_unlock(&disp_data->task_mutex);
+
+	return 0;
+}
+
+static int sdl_display_clear(const struct device *dev)
+{
+	const struct sdl_display_config *config = dev->config;
+	struct sdl_display_data *disp_data = dev->data;
+	uint8_t bgcolor = 0x00u;
+	size_t size;
+
+	LOG_DBG("Clearing display screen to black");
+
+	switch (disp_data->current_pixel_format) {
+	case PIXEL_FORMAT_ARGB_8888:
+		size = config->width * config->height * 4U;
+		bgcolor = 0xFFu;
+		break;
+	case PIXEL_FORMAT_RGB_888:
+		size = config->width * config->height * 3U;
+		break;
+	case PIXEL_FORMAT_MONO10:
+		size = config->height * DIV_ROUND_UP(config->width,
+						NUM_BITS(uint8_t));
+		break;
+	case PIXEL_FORMAT_MONO01:
+		size = config->height * DIV_ROUND_UP(config->width,
+						NUM_BITS(uint8_t));
+		bgcolor = 0xFFu;
+		break;
+	case PIXEL_FORMAT_RGB_565:
+	case PIXEL_FORMAT_BGR_565:
+		size = config->width * config->height * 2U;
+		break;
+	default:
+		__ASSERT_MSG_INFO("Pixel format not supported");
+		return -EINVAL;
 	}
+	LOG_DBG("size: %zu, bgcolor: %hhu", size, bgcolor);
+	k_mutex_lock(&disp_data->task_mutex, K_FOREVER);
+	memset(disp_data->buf, bgcolor, size);
+	k_mutex_unlock(&disp_data->task_mutex);
 
 	return 0;
 }
@@ -431,13 +627,22 @@ static int sdl_display_read(const struct device *dev, const uint16_t x,
 static int sdl_display_blanking_off(const struct device *dev)
 {
 	struct sdl_display_data *disp_data = dev->data;
+	struct sdl_display_task task = {
+		.op = SDL_BLANKING_OFF,
+	};
 
 	LOG_DBG("Turning display blacking off");
-
 	disp_data->display_on = true;
+	k_mutex_lock(&disp_data->task_mutex, K_FOREVER);
 
-	sdl_display_blanking_off_bottom(disp_data->renderer, disp_data->texture,
-					disp_data->background_texture);
+	if (k_current_get() == &disp_data->sdl_thread) {
+		exec_sdl_task(dev, &task);
+	} else {
+		k_msgq_put(disp_data->task_msgq, &task, K_FOREVER);
+		k_sem_take(&disp_data->task_sem, K_FOREVER);
+	}
+
+	k_mutex_unlock(&disp_data->task_mutex);
 
 	return 0;
 }
@@ -445,12 +650,23 @@ static int sdl_display_blanking_off(const struct device *dev)
 static int sdl_display_blanking_on(const struct device *dev)
 {
 	struct sdl_display_data *disp_data = dev->data;
+	struct sdl_display_task task = {
+		.op = SDL_BLANKING_ON,
+	};
 
 	LOG_DBG("Turning display blanking on");
-
 	disp_data->display_on = false;
+	k_mutex_lock(&disp_data->task_mutex, K_FOREVER);
+
+	if (k_current_get() == &disp_data->sdl_thread) {
+		exec_sdl_task(dev, &task);
+	} else {
+		k_msgq_put(disp_data->task_msgq, &task, K_FOREVER);
+		k_sem_take(&disp_data->task_sem, K_FOREVER);
+	}
+
+	k_mutex_unlock(&disp_data->task_mutex);
 
-	sdl_display_blanking_on_bottom(disp_data->renderer);
 	return 0;
 }
 
@@ -468,9 +684,11 @@ static void sdl_display_get_capabilities(
 		PIXEL_FORMAT_MONO01 |
 		PIXEL_FORMAT_MONO10 |
 		PIXEL_FORMAT_RGB_565 |
-		PIXEL_FORMAT_BGR_565;
+		PIXEL_FORMAT_BGR_565 |
+		PIXEL_FORMAT_L_8;
 	capabilities->current_pixel_format = disp_data->current_pixel_format;
-	capabilities->screen_info = SCREEN_INFO_MONO_VTILED |
+	capabilities->screen_info =
+		(IS_ENABLED(CONFIG_SDL_DISPLAY_MONO_VTILED) ? SCREEN_INFO_MONO_VTILED : 0) |
 		(IS_ENABLED(CONFIG_SDL_DISPLAY_MONO_MSB_FIRST) ? SCREEN_INFO_MONO_MSB_FIRST : 0);
 }
 
@@ -486,6 +704,7 @@ static int sdl_display_set_pixel_format(const struct device *dev,
 	case PIXEL_FORMAT_MONO10:
 	case PIXEL_FORMAT_RGB_565:
 	case PIXEL_FORMAT_BGR_565:
+	case PIXEL_FORMAT_L_8:
 		disp_data->current_pixel_format = pixel_format;
 		return 0;
 	default:
@@ -506,6 +725,7 @@ static DEVICE_API(display, sdl_display_api) = {
 	.blanking_off = sdl_display_blanking_off,
 	.write = sdl_display_write,
 	.read = sdl_display_read,
+	.clear = sdl_display_clear,
 	.get_capabilities = sdl_display_get_capabilities,
 	.set_pixel_format = sdl_display_set_pixel_format,
 };
@@ -520,9 +740,11 @@ static DEVICE_API(display, sdl_display_api) = {
 				   * DT_INST_PROP(n, width)];		\
 	static uint8_t sdl_read_buf_##n[4 * DT_INST_PROP(n, height)	\
 					* DT_INST_PROP(n, width)];	\
+	K_MSGQ_DEFINE(sdl_task_msgq_##n, sizeof(struct sdl_display_task), 1, 4); \
 	static struct sdl_display_data sdl_data_##n = {			\
 		.buf = sdl_buf_##n,					\
 		.read_buf = sdl_read_buf_##n,				\
+		.task_msgq = &sdl_task_msgq_##n,			\
 	};								\
 									\
 	DEVICE_DT_INST_DEFINE(n, &sdl_display_init, NULL,		\
diff --git a/drivers/display/display_sdl_bottom.c b/drivers/display/display_sdl_bottom.c
index e7b259cda09..da50ad81c91 100644
--- a/drivers/display/display_sdl_bottom.c
+++ b/drivers/display/display_sdl_bottom.c
@@ -14,10 +14,10 @@
 #include "nsi_tracing.h"
 
 int sdl_display_init_bottom(uint16_t height, uint16_t width, uint16_t zoom_pct,
-			    bool use_accelerator, void **window, void **renderer, void **mutex,
-			    void **texture, void **read_texture, void **background_texture,
-			    uint32_t transparency_grid_color1, uint32_t transparency_grid_color2,
-			    uint16_t transparency_grid_cell_size)
+			    bool use_accelerator, void **window, const void *window_user_data,
+			    void **renderer, void **mutex, void **texture, void **read_texture,
+			    void **background_texture, uint32_t transparency_grid_color1,
+			    uint32_t transparency_grid_color2, uint16_t transparency_grid_cell_size)
 {
 	*window = SDL_CreateWindow("Zephyr Display", SDL_WINDOWPOS_UNDEFINED,
 				   SDL_WINDOWPOS_UNDEFINED, width * zoom_pct / 100,
@@ -26,6 +26,7 @@ int sdl_display_init_bottom(uint16_t height, uint16_t width, uint16_t zoom_pct,
 		nsi_print_warning("Failed to create SDL window: %s", SDL_GetError());
 		return -1;
 	}
+	SDL_SetWindowData(*window, "zephyr_display", (void *)window_user_data);
 
 	if (use_accelerator) {
 		*renderer = SDL_CreateRenderer(*window, -1, SDL_RENDERER_ACCELERATED);
diff --git a/drivers/display/display_sdl_bottom.h b/drivers/display/display_sdl_bottom.h
index 16a6a2ce603..4ce795f64e3 100644
--- a/drivers/display/display_sdl_bottom.h
+++ b/drivers/display/display_sdl_bottom.h
@@ -21,9 +21,10 @@ extern "C" {
 /* Note: None of these functions are public interfaces. But internal to the SDL display driver */
 
 int sdl_display_init_bottom(uint16_t height, uint16_t width, uint16_t zoom_pct,
-			    bool use_accelerator, void **window, void **renderer, void **mutex,
-			    void **texture, void **read_texture, void **background_texture,
-			    uint32_t transparency_grid_color1, uint32_t transparency_grid_color2,
+			    bool use_accelerator, void **window, const void *window_user_data,
+			    void **renderer, void **mutex, void **texture, void **read_texture,
+			    void **background_texture, uint32_t transparency_grid_color1,
+			    uint32_t transparency_grid_color2,
 			    uint16_t transparency_grid_cell_size);
 void sdl_display_write_bottom(const uint16_t height, const uint16_t width, const uint16_t x,
 			      const uint16_t y, void *renderer, void *mutex, void *texture,
diff --git a/drivers/display/display_st7567.c b/drivers/display/display_st7567.c
new file mode 100644
index 00000000000..15491f05618
--- /dev/null
+++ b/drivers/display/display_st7567.c
@@ -0,0 +1,491 @@
+/*
+ * Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(display_st7567, CONFIG_DISPLAY_LOG_LEVEL);
+
+#include <string.h>
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/drivers/display.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/kernel.h>
+
+#include "display_st7567_regs.h"
+
+union st7567_bus {
+	struct i2c_dt_spec i2c;
+	struct spi_dt_spec spi;
+};
+
+typedef bool (*st7567_bus_ready_fn)(const struct device *dev);
+typedef int (*st7567_write_bus_fn)(const struct device *dev, uint8_t *buf, size_t len,
+				   bool command);
+typedef const char *(*st7567_bus_name_fn)(const struct device *dev);
+
+struct st7567_config {
+	union st7567_bus bus;
+	struct gpio_dt_spec data_cmd;
+	struct gpio_dt_spec reset;
+	st7567_bus_ready_fn bus_ready;
+	st7567_write_bus_fn write_bus;
+	st7567_bus_name_fn bus_name;
+	uint16_t height;
+	uint16_t width;
+	uint8_t column_offset;
+	uint8_t line_offset;
+	uint8_t regulation_ratio;
+	bool com_invdir;
+	bool segment_invdir;
+	bool inversion_on;
+	bool bias;
+};
+
+struct st7567_data {
+	enum display_pixel_format pf;
+};
+
+#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(sitronix_st7567, i2c)
+
+static bool st7567_bus_ready_i2c(const struct device *dev)
+{
+	const struct st7567_config *config = dev->config;
+
+	return i2c_is_ready_dt(&config->bus.i2c);
+}
+
+static int st7567_write_bus_i2c(const struct device *dev, uint8_t *buf, size_t len, bool command)
+{
+	const struct st7567_config *config = dev->config;
+
+	return i2c_burst_write_dt(
+		&config->bus.i2c,
+		command ? ST7567_CONTROL_ALL_BYTES_CMD : ST7567_CONTROL_ALL_BYTES_DATA, buf, len);
+}
+
+static const char *st7567_bus_name_i2c(const struct device *dev)
+{
+	const struct st7567_config *config = dev->config;
+
+	return config->bus.i2c.bus->name;
+}
+
+#endif
+
+#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(sitronix_st7567, spi)
+
+static bool st7567_bus_ready_spi(const struct device *dev)
+{
+	const struct st7567_config *config = dev->config;
+
+	if (gpio_pin_configure_dt(&config->data_cmd, GPIO_OUTPUT_INACTIVE) < 0) {
+		return false;
+	}
+
+	return spi_is_ready_dt(&config->bus.spi);
+}
+
+static int st7567_write_bus_spi(const struct device *dev, uint8_t *buf, size_t len, bool command)
+{
+	const struct st7567_config *config = dev->config;
+	int ret;
+
+	gpio_pin_set_dt(&config->data_cmd, command ? 0 : 1);
+	struct spi_buf tx_buf = {.buf = buf, .len = len};
+
+	struct spi_buf_set tx_bufs = {.buffers = &tx_buf, .count = 1};
+
+	ret = spi_write_dt(&config->bus.spi, &tx_bufs);
+
+	return ret;
+}
+
+static const char *st7567_bus_name_spi(const struct device *dev)
+{
+	const struct st7567_config *config = dev->config;
+
+	return config->bus.spi.bus->name;
+}
+
+#endif
+
+static inline bool st7567_bus_ready(const struct device *dev)
+{
+	const struct st7567_config *config = dev->config;
+
+	return config->bus_ready(dev);
+}
+
+static inline int st7567_write_bus(const struct device *dev, uint8_t *buf, size_t len, bool command)
+{
+	const struct st7567_config *config = dev->config;
+
+	return config->write_bus(dev, buf, len, command);
+}
+
+static inline int st7567_set_panel_orientation(const struct device *dev)
+{
+	const struct st7567_config *config = dev->config;
+	uint8_t cmd_buf[] = {(config->segment_invdir ? ST7567_SET_SEGMENT_MAP_FLIPPED
+						     : ST7567_SET_SEGMENT_MAP_NORMAL),
+			     (config->com_invdir ? ST7567_SET_COM_OUTPUT_SCAN_FLIPPED
+						 : ST7567_SET_COM_OUTPUT_SCAN_NORMAL)};
+
+	return st7567_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
+}
+
+static inline int st7567_set_hardware_config(const struct device *dev)
+{
+	const struct st7567_config *config = dev->config;
+	int ret;
+	uint8_t cmd_buf[1];
+
+	cmd_buf[0] = ST7567_SET_BIAS | (config->bias ? 1 : 0);
+	ret = st7567_write_bus(dev, cmd_buf, 1, true);
+	if (ret < 0) {
+		return ret;
+	}
+
+	cmd_buf[0] = ST7567_POWER_CONTROL | ST7567_POWER_CONTROL_VB;
+	ret = st7567_write_bus(dev, cmd_buf, 1, true);
+	if (ret < 0) {
+		return ret;
+	}
+
+	cmd_buf[0] = ST7567_POWER_CONTROL | ST7567_POWER_CONTROL_VB | ST7567_POWER_CONTROL_VR;
+	ret = st7567_write_bus(dev, cmd_buf, 1, true);
+	if (ret < 0) {
+		return ret;
+	}
+
+	cmd_buf[0] = ST7567_POWER_CONTROL | ST7567_POWER_CONTROL_VB | ST7567_POWER_CONTROL_VR |
+		     ST7567_POWER_CONTROL_VF;
+	ret = st7567_write_bus(dev, cmd_buf, 1, true);
+	if (ret < 0) {
+		return ret;
+	}
+
+	cmd_buf[0] = ST7567_SET_REGULATION_RATIO | (config->regulation_ratio & 0x7);
+	ret = st7567_write_bus(dev, cmd_buf, 1, true);
+	if (ret < 0) {
+		return ret;
+	}
+
+	cmd_buf[0] = ST7567_LINE_SCROLL | (config->line_offset & 0x3F);
+	ret = st7567_write_bus(dev, cmd_buf, 1, true);
+	if (ret < 0) {
+		return ret;
+	}
+
+	return ret;
+}
+
+static int st7567_resume(const struct device *dev)
+{
+	uint8_t cmd_buf[] = {
+		ST7567_DISPLAY_ALL_PIXEL_NORMAL,
+		ST7567_DISPLAY_ON,
+	};
+
+	return st7567_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
+}
+
+static int st7567_suspend(const struct device *dev)
+{
+	uint8_t cmd_buf[] = {
+		ST7567_DISPLAY_OFF,
+		ST7567_DISPLAY_ALL_PIXEL_ON,
+	};
+
+	return st7567_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
+}
+
+static int st7567_write_default(const struct device *dev, const uint16_t x, const uint16_t y,
+				const struct display_buffer_descriptor *desc, const void *buf,
+				const size_t buf_len)
+{
+	int ret;
+	uint8_t cmd_buf[3];
+
+	for (int i = 0; i < desc->height / 8; i++) {
+		cmd_buf[0] = ST7567_COLUMN_LSB | (x & 0xF);
+		cmd_buf[1] = ST7567_COLUMN_MSB | ((x >> 4) & 0xF);
+		cmd_buf[2] = ST7567_PAGE | ((y >> 3) + i);
+		ret = st7567_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
+		if (ret < 0) {
+			return ret;
+		}
+		ret = st7567_write_bus(dev, ((uint8_t *)buf + i * desc->pitch), desc->pitch, false);
+		if (ret < 0) {
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+static int st7567_write(const struct device *dev, const uint16_t x, const uint16_t y,
+			const struct display_buffer_descriptor *desc, const void *buf)
+{
+	size_t buf_len;
+
+	if (desc->pitch < desc->width) {
+		LOG_ERR("Pitch is smaller than width");
+		return -EINVAL;
+	}
+
+	buf_len = MIN(desc->buf_size, desc->height * desc->width / 8);
+	if (buf == NULL || buf_len == 0U) {
+		LOG_ERR("Display buffer is not available");
+		return -EINVAL;
+	}
+
+	if (desc->pitch > desc->width) {
+		LOG_ERR("Unsupported mode");
+		return -EINVAL;
+	}
+
+	if ((y & 0x7) != 0U) {
+		LOG_ERR("Y coordinate must be aligned on page boundary");
+		return -EINVAL;
+	}
+
+	LOG_DBG("x %u, y %u, pitch %u, width %u, height %u, buf_len %u", x, y, desc->pitch,
+		desc->width, desc->height, buf_len);
+
+	return st7567_write_default(dev, x, y, desc, buf, buf_len);
+}
+
+static int st7567_set_contrast(const struct device *dev, const uint8_t contrast)
+{
+	uint8_t cmd_buf[] = {
+		ST7567_SET_CONTRAST_CTRL,
+		contrast,
+	};
+
+	return st7567_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
+}
+
+static void st7567_get_capabilities(const struct device *dev, struct display_capabilities *caps)
+{
+	const struct st7567_config *config = dev->config;
+	struct st7567_data *data = dev->data;
+
+	caps->x_resolution = config->width;
+	caps->y_resolution = config->height;
+	caps->supported_pixel_formats = PIXEL_FORMAT_MONO10 | PIXEL_FORMAT_MONO01;
+	caps->current_pixel_format = data->pf;
+	caps->screen_info = SCREEN_INFO_MONO_VTILED;
+	caps->current_orientation = DISPLAY_ORIENTATION_NORMAL;
+}
+
+static int st7567_set_pixel_format(const struct device *dev, const enum display_pixel_format pf)
+{
+	struct st7567_data *data = dev->data;
+	const struct st7567_config *config = dev->config;
+	uint8_t cmd;
+	int ret;
+
+	if (pf == data->pf) {
+		return 0;
+	}
+
+	if (pf == PIXEL_FORMAT_MONO10) {
+		cmd = config->inversion_on ? ST7567_SET_REVERSE_DISPLAY : ST7567_SET_NORMAL_DISPLAY;
+	} else if (pf == PIXEL_FORMAT_MONO01) {
+		cmd = config->inversion_on ? ST7567_SET_NORMAL_DISPLAY : ST7567_SET_REVERSE_DISPLAY;
+	} else {
+		LOG_WRN("Unsupported pixel format");
+		return -ENOTSUP;
+	}
+
+	ret = st7567_write_bus(dev, &cmd, 1, true);
+	if (ret) {
+		LOG_WRN("Couldn't set inversion");
+		return ret;
+	}
+
+	data->pf = pf;
+
+	return 0;
+}
+
+static int st7567_reset(const struct device *dev)
+{
+	const struct st7567_config *config = dev->config;
+	uint8_t cmd_buf[] = {
+		ST7567_DISPLAY_OFF,
+		(config->inversion_on ? ST7567_SET_REVERSE_DISPLAY : ST7567_SET_NORMAL_DISPLAY),
+	};
+
+	/* Reset if pin connected */
+	if (config->reset.port) {
+		k_sleep(K_MSEC(ST7567_RESET_DELAY));
+		gpio_pin_set_dt(&config->reset, 1);
+		k_sleep(K_MSEC(ST7567_RESET_DELAY));
+		gpio_pin_set_dt(&config->reset, 0);
+		k_sleep(K_MSEC(ST7567_RESET_DELAY));
+	}
+
+	return st7567_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
+}
+
+static int st7567_clear(const struct device *dev)
+{
+	const struct st7567_config *config = dev->config;
+	int ret;
+	uint8_t buf = 0;
+
+	uint8_t cmd_buf[] = {
+		ST7567_COLUMN_LSB,
+		ST7567_COLUMN_MSB,
+		ST7567_PAGE,
+	};
+
+	for (int y = 0; y < config->height; y += 8) {
+		for (int x = 0; x < config->width; x++) {
+			cmd_buf[0] = ST7567_COLUMN_LSB | (x & 0xF);
+			cmd_buf[1] = ST7567_COLUMN_MSB | ((x >> 4) & 0xF);
+			cmd_buf[2] = ST7567_PAGE | (y >> 3);
+			ret = st7567_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
+			if (ret < 0) {
+				LOG_ERR("Error clearing display");
+				return ret;
+			}
+			ret = st7567_write_bus(dev, (uint8_t *)&buf, 1, false);
+			if (ret < 0) {
+				LOG_ERR("Error clearing display");
+				return ret;
+			}
+		}
+	}
+	return ret;
+}
+
+static int st7567_init_device(const struct device *dev)
+{
+	const struct st7567_config *config = dev->config;
+	struct st7567_data *data = dev->data;
+	int ret;
+	uint8_t cmd_buf[] = {
+		ST7567_DISPLAY_OFF,
+		(config->inversion_on ? ST7567_SET_REVERSE_DISPLAY : ST7567_SET_NORMAL_DISPLAY),
+	};
+
+	ret = st7567_reset(dev);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = st7567_suspend(dev);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = st7567_set_hardware_config(dev);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = st7567_set_panel_orientation(dev);
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* Set inversion */
+	ret = st7567_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
+	if (ret < 0) {
+		return ret;
+	}
+
+	data->pf = config->inversion_on ? PIXEL_FORMAT_MONO10 : PIXEL_FORMAT_MONO01;
+
+	ret = st7567_set_contrast(dev, CONFIG_ST7567_DEFAULT_CONTRAST);
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* Clear display, RAM is undefined at power up */
+	ret = st7567_clear(dev);
+	if (ret < 0) {
+		return ret;
+	}
+	ret = st7567_resume(dev);
+
+	return ret;
+}
+
+static int st7567_init(const struct device *dev)
+{
+	const struct st7567_config *config = dev->config;
+	int ret;
+
+	if (!st7567_bus_ready(dev)) {
+		LOG_ERR("Bus device %s not ready!", config->bus_name(dev));
+		return -EINVAL;
+	}
+
+	if (config->reset.port) {
+		ret = gpio_pin_configure_dt(&config->reset, GPIO_OUTPUT_INACTIVE);
+		if (ret < 0) {
+			LOG_ERR("Couldn't configure reset pin");
+			return ret;
+		}
+		if (!gpio_is_ready_dt(&config->reset)) {
+			LOG_ERR("Reset GPIO device not ready");
+			return -ENODEV;
+		}
+	}
+
+	if (st7567_init_device(dev)) {
+		LOG_ERR("Failed to initialize device!");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(display, st7567_driver_api) = {
+	.blanking_on = st7567_suspend,
+	.blanking_off = st7567_resume,
+	.write = st7567_write,
+	.set_contrast = st7567_set_contrast,
+	.get_capabilities = st7567_get_capabilities,
+	.set_pixel_format = st7567_set_pixel_format,
+};
+
+#define ST7567_CONFIG_SPI(node_id)                                                                 \
+	.bus = {.spi = SPI_DT_SPEC_GET(                                                            \
+			node_id, SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8), 0)},     \
+	.bus_ready = st7567_bus_ready_spi, .write_bus = st7567_write_bus_spi,                      \
+	.bus_name = st7567_bus_name_spi, .data_cmd = GPIO_DT_SPEC_GET(node_id, data_cmd_gpios),
+
+#define ST7567_CONFIG_I2C(node_id)                                                                 \
+	.bus = {.i2c = I2C_DT_SPEC_GET(node_id)}, .bus_ready = st7567_bus_ready_i2c,               \
+	.write_bus = st7567_write_bus_i2c, .bus_name = st7567_bus_name_i2c, .data_cmd = {0},
+
+#define ST7567_DEFINE(node_id)                                                                     \
+	static struct st7567_data data##node_id;                                                   \
+	static const struct st7567_config config##node_id = {                                      \
+		.reset = GPIO_DT_SPEC_GET_OR(node_id, reset_gpios, {0}),                           \
+		.height = DT_PROP(node_id, height),                                                \
+		.width = DT_PROP(node_id, width),                                                  \
+		.column_offset = DT_PROP(node_id, column_offset),                                  \
+		.line_offset = DT_PROP(node_id, line_offset),                                      \
+		.segment_invdir = DT_PROP(node_id, segment_invdir),                                \
+		.com_invdir = DT_PROP(node_id, com_invdir),                                        \
+		.inversion_on = DT_PROP(node_id, inversion_on),                                    \
+		.bias = DT_PROP(node_id, bias),                                                    \
+		.regulation_ratio = DT_PROP(node_id, regulation_ratio),                            \
+		COND_CODE_1(DT_ON_BUS(node_id, spi), (ST7567_CONFIG_SPI(node_id)),                 \
+			    (ST7567_CONFIG_I2C(node_id))) }; \
+                                                                                                   \
+	DEVICE_DT_DEFINE(node_id, st7567_init, NULL, &data##node_id, &config##node_id,             \
+			 POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, &st7567_driver_api);
+
+DT_FOREACH_STATUS_OKAY(sitronix_st7567, ST7567_DEFINE)
diff --git a/drivers/display/display_st7567_regs.h b/drivers/display/display_st7567_regs.h
new file mode 100644
index 00000000000..e963e3cf490
--- /dev/null
+++ b/drivers/display/display_st7567_regs.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __DISPLAY_ST7567_REGS_H__
+#define __DISPLAY_ST7567_REGS_H__
+
+/* All following bytes will contain commands */
+#define ST7567_CONTROL_ALL_BYTES_CMD     0x00
+/* All following bytes will contain data */
+#define ST7567_CONTROL_ALL_BYTES_DATA    0x40
+/* The next byte will contain a command, then expect another control byte */
+#define ST7567_CONTROL_CONTINUE_BYTE_CMD 0x80
+
+#define ST7567_DISPLAY_OFF              0xAE
+#define ST7567_DISPLAY_ON               0xAF
+#define ST7567_DISPLAY_ALL_PIXEL_ON     0xA5
+#define ST7567_DISPLAY_ALL_PIXEL_NORMAL 0xA4
+#define ST7567_SET_CONTRAST_CTRL        0x81
+#define ST7567_SET_BIAS                 0xA2
+#define ST7567_SET_REGULATION_RATIO     0x20
+
+/* Inversion controls */
+#define ST7567_SET_NORMAL_DISPLAY  0xA6
+#define ST7567_SET_REVERSE_DISPLAY 0xA7
+
+/* COM invdir */
+#define ST7567_SET_COM_OUTPUT_SCAN_FLIPPED 0xC8
+#define ST7567_SET_COM_OUTPUT_SCAN_NORMAL  0xC0
+
+/* SEG invdir */
+#define ST7567_SET_SEGMENT_MAP_FLIPPED 0xA1
+#define ST7567_SET_SEGMENT_MAP_NORMAL  0xA0
+
+/* Power Control */
+#define ST7567_POWER_CONTROL    0x28
+#define ST7567_POWER_CONTROL_VF 0x1
+#define ST7567_POWER_CONTROL_VR 0x2
+#define ST7567_POWER_CONTROL_VB 0x4
+
+/* Offsets */
+#define ST7567_COLUMN_MSB  0x10
+#define ST7567_COLUMN_LSB  0x0
+#define ST7567_PAGE        0xB0
+#define ST7567_LINE_SCROLL 0x40
+
+#define ST7567_RESET_DELAY 1
+#define ST7567_RESET       0xE2
+
+#endif /* __DISPLAY_ST7567_REGS_H__ */
diff --git a/drivers/display/display_st7701.c b/drivers/display/display_st7701.c
new file mode 100644
index 00000000000..22fc96c1bf0
--- /dev/null
+++ b/drivers/display/display_st7701.c
@@ -0,0 +1,494 @@
+/*
+ * Copyright (c) 2025 Arduino SA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT sitronix_st7701
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/display.h>
+#include <zephyr/drivers/mipi_dsi.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(st7701, CONFIG_DISPLAY_LOG_LEVEL);
+
+/* Command2 BKx selection command */
+#define DSI_CMD2BKX_SEL      0xFF
+#define DSI_CMD2BK1_SEL      0x11
+#define DSI_CMD2BK0_SEL      0x10
+#define DSI_CMD2BKX_SEL_NONE 0x00
+
+/* Command2, BK0 commands */
+#define DSI_CMD2_BK0_PVGAMCTRL 0xB0 /* Positive Voltage Gamma Control */
+#define DSI_CMD2_BK0_NVGAMCTRL 0xB1 /* Negative Voltage Gamma Control */
+#define DSI_CMD2_BK0_LNESET    0xC0 /* Display Line setting */
+#define DSI_CMD2_BK0_PORCTRL   0xC1 /* Porch control */
+#define DSI_CMD2_BK0_INVSEL    0xC2 /* Inversion selection, Frame Rate Control */
+
+/* Command2, BK1 commands */
+#define DSI_CMD2_BK1_VRHS     0xB0 /* Vop amplitude setting */
+#define DSI_CMD2_BK1_VCOM     0xB1 /* VCOM amplitude setting */
+#define DSI_CMD2_BK1_VGHSS    0xB2 /* VGH Voltage setting */
+#define DSI_CMD2_BK1_TESTCMD  0xB3 /* TEST Command Setting */
+#define DSI_CMD2_BK1_VGLS     0xB5 /* VGL Voltage setting */
+#define DSI_CMD2_BK1_PWCTLR1  0xB7 /* Power Control 1 */
+#define DSI_CMD2_BK1_PWCTLR2  0xB8 /* Power Control 2 */
+#define DSI_CMD2_BK1_SPD1     0xC1 /* Source pre_drive timing set1 */
+#define DSI_CMD2_BK1_SPD2     0xC2 /* Source EQ2 Setting */
+#define DSI_CMD2_BK1_MIPISET1 0xD0 /* MIPI Setting 1 */
+
+#define ST7701_CMD_ID1 0xDA
+#define ST7701_ID      0xFF
+
+/* Write Control Display: brightness control. */
+#define ST7701_WRCTRLD_BCTRL BIT(5)
+/* Write Control Display: display dimming. */
+#define ST7701_WRCTRLD_DD    BIT(3)
+/* Write Control Display: backlight. */
+#define ST7701_WRCTRLD_BL    BIT(2)
+
+/* Adaptive Brightness Control: off. */
+#define ST7701_WRCABC_OFF 0x00U
+/* Adaptive Brightness Control: user interface. */
+#define ST7701_WRCABC_UI  0x01U
+/* Adaptive Brightness Control: still picture. */
+#define ST7701_WRCABC_ST  0x02U
+/* Adaptive Brightness Control: moving image. */
+#define ST7701_WRCABC_MV  0x03U
+
+struct st7701_config {
+	const struct device *mipi_dsi;
+	const struct gpio_dt_spec reset;
+	const struct gpio_dt_spec backlight;
+	uint8_t data_lanes;
+	uint16_t width;
+	uint16_t height;
+	uint8_t channel;
+	uint16_t rotation;
+	uint32_t hbp;
+	uint32_t hsync;
+	uint32_t hfp;
+	uint32_t vbp;
+	uint32_t vsync;
+	uint32_t vfp;
+	uint8_t gip_e0[4];
+	uint8_t gip_e1[12];
+	uint8_t gip_e2[14];
+	uint8_t gip_e3[5];
+	uint8_t gip_e4[3];
+	uint8_t gip_e5[17];
+	uint8_t gip_e6[5];
+	uint8_t gip_e7[3];
+	uint8_t gip_e8[17];
+	uint8_t gip_eb[8];
+	uint8_t gip_ec[3];
+	uint8_t gip_ed[17];
+	uint8_t pvgamctrl[17];
+	uint8_t nvgamctrl[17];
+};
+
+struct st7701_data {
+	uint16_t xres;
+	uint16_t yres;
+	uint8_t dsi_pixel_format;
+	enum display_pixel_format pixel_format;
+	enum display_orientation orientation;
+};
+
+static inline int st7701_dcs_write(const struct device *dev, uint8_t cmd, const void *buf,
+				   size_t len)
+{
+	const struct st7701_config *cfg = dev->config;
+	int ret;
+
+	ret = mipi_dsi_dcs_write(cfg->mipi_dsi, cfg->channel, cmd, buf, len);
+	if (ret < 0) {
+		LOG_ERR("DCS 0x%x write failed! (%d)", cmd, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int st7701_short_write_1p(const struct device *dev, uint8_t cmd, uint8_t val)
+{
+	const struct st7701_config *cfg = dev->config;
+	int ret;
+	uint8_t buf[] = {cmd, val};
+
+	ret = mipi_dsi_generic_write(cfg->mipi_dsi, cfg->channel, buf, sizeof(val));
+	if (ret < 0) {
+		LOG_ERR("Short write failed! (%d)", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int st7701_generic_write(const struct device *dev, const void *buf, size_t len)
+{
+	const struct st7701_config *cfg = dev->config;
+	int ret;
+
+	ret = mipi_dsi_generic_write(cfg->mipi_dsi, cfg->channel, buf, len);
+	if (ret < 0) {
+		LOG_ERR("Generic write failed! (%d)", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int st7701_check_id(const struct device *dev)
+{
+	const struct st7701_config *cfg = dev->config;
+	uint32_t id = 0;
+	int ret;
+
+	ret = mipi_dsi_dcs_read(cfg->mipi_dsi, cfg->channel, ST7701_CMD_ID1, &id, sizeof(id));
+	if (ret != sizeof(id)) {
+		LOG_ERR("Read panel ID failed! (%d)", ret);
+		return -EIO;
+	}
+
+	if (id != ST7701_ID) {
+		LOG_ERR("ID 0x%x (should 0x%x)", id, ST7701_ID);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int st7701_configure(const struct device *dev)
+{
+	struct st7701_data *data = dev->data;
+	const struct st7701_config *cfg = dev->config;
+	uint8_t buf[4];
+	int ret;
+
+	const uint8_t ff1[] = {DSI_CMD2BKX_SEL, 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK1_SEL};
+	const uint8_t ff2[] = {DSI_CMD2BKX_SEL, 0x77, 0x01, 0x00, 0x00, DSI_CMD2BKX_SEL_NONE};
+
+	const uint8_t control0[] = {DSI_CMD2BKX_SEL, 0x77, 0x01, 0x00, 0x00, DSI_CMD2BK0_SEL};
+	const uint8_t control1[] = {0xC0, 0x63, 0x00};
+	const uint8_t control2[] = {0xC1, 0x11, 0x02};
+	const uint8_t control3[] = {0xC2, 0x01, 0x08};
+	const uint8_t control4[] = {0xCC, 0x18};
+
+	st7701_generic_write(dev, control0, sizeof(control0));
+	st7701_generic_write(dev, control1, sizeof(control1));
+	st7701_generic_write(dev, control2, sizeof(control2));
+	st7701_generic_write(dev, control3, sizeof(control3));
+	st7701_generic_write(dev, control4, sizeof(control4));
+
+	/* Gamma Cluster Setting */
+	st7701_generic_write(dev, cfg->pvgamctrl, sizeof(cfg->pvgamctrl));
+	st7701_generic_write(dev, cfg->nvgamctrl, sizeof(cfg->nvgamctrl));
+
+	/* Initial power control registers */
+	st7701_generic_write(dev, ff1, sizeof(ff1));
+
+	st7701_short_write_1p(dev, DSI_CMD2_BK1_VRHS, 0x65);
+	st7701_short_write_1p(dev, DSI_CMD2_BK1_VCOM, 0x34);
+	st7701_short_write_1p(dev, DSI_CMD2_BK1_VGHSS, 0x87);
+	st7701_short_write_1p(dev, DSI_CMD2_BK1_TESTCMD, 0x80);
+
+	st7701_short_write_1p(dev, DSI_CMD2_BK1_VGLS, 0x49);
+	st7701_short_write_1p(dev, DSI_CMD2_BK1_PWCTLR1, 0x85);
+
+	st7701_short_write_1p(dev, DSI_CMD2_BK1_PWCTLR2, 0x20);
+	st7701_short_write_1p(dev, 0xB9, 0x10);
+	st7701_short_write_1p(dev, DSI_CMD2_BK1_SPD1, 0x78);
+	st7701_short_write_1p(dev, DSI_CMD2_BK1_SPD2, 0x78);
+	st7701_short_write_1p(dev, DSI_CMD2_BK1_MIPISET1, 0x88);
+	k_msleep(100);
+
+	/* GIP Setting */
+	st7701_generic_write(dev, cfg->gip_e0, sizeof(cfg->gip_e0));
+	st7701_generic_write(dev, cfg->gip_e1, sizeof(cfg->gip_e1));
+	st7701_generic_write(dev, cfg->gip_e2, sizeof(cfg->gip_e2));
+	st7701_generic_write(dev, cfg->gip_e3, sizeof(cfg->gip_e3));
+	st7701_generic_write(dev, cfg->gip_e4, sizeof(cfg->gip_e4));
+	st7701_generic_write(dev, cfg->gip_e5, sizeof(cfg->gip_e5));
+	st7701_generic_write(dev, cfg->gip_e6, sizeof(cfg->gip_e6));
+	st7701_generic_write(dev, cfg->gip_e7, sizeof(cfg->gip_e7));
+	st7701_generic_write(dev, cfg->gip_e8, sizeof(cfg->gip_e8));
+	st7701_generic_write(dev, cfg->gip_eb, sizeof(cfg->gip_eb));
+	st7701_generic_write(dev, cfg->gip_ec, sizeof(cfg->gip_ec));
+	st7701_generic_write(dev, cfg->gip_ed, sizeof(cfg->gip_ed));
+
+	/* Bank1 setting */
+	st7701_generic_write(dev, ff2, sizeof(ff2));
+
+	/* Exit sleep mode */
+	ret = st7701_dcs_write(dev, MIPI_DCS_EXIT_SLEEP_MODE, NULL, 0);
+	if (ret < 0) {
+		return ret;
+	}
+
+	k_msleep(50);
+
+	/* Set pixel color format */
+	switch (data->dsi_pixel_format) {
+	case MIPI_DSI_PIXFMT_RGB565:
+		buf[0] = MIPI_DCS_PIXEL_FORMAT_16BIT;
+		break;
+	case MIPI_DSI_PIXFMT_RGB888:
+		buf[0] = MIPI_DCS_PIXEL_FORMAT_24BIT;
+		break;
+	default:
+		LOG_ERR("Unsupported pixel format 0x%x!", data->dsi_pixel_format);
+		return -ENOTSUP;
+	}
+
+	ret = st7701_dcs_write(dev, MIPI_DCS_SET_PIXEL_FORMAT, buf, 1);
+	if (ret < 0) {
+		return ret;
+	}
+
+	buf[0] = 0x00;
+	buf[1] = 0x00;
+	sys_put_be16(data->xres, (uint8_t *)&buf[2]);
+	ret = st7701_dcs_write(dev, MIPI_DCS_SET_COLUMN_ADDRESS, buf, 4);
+	if (ret < 0) {
+		return ret;
+	}
+
+	buf[0] = 0x00;
+	buf[1] = 0x00;
+	sys_put_be16(data->yres, (uint8_t *)&buf[2]);
+	ret = st7701_dcs_write(dev, MIPI_DCS_SET_PAGE_ADDRESS, buf, 4);
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* Backlight control */
+	buf[0] = ST7701_WRCTRLD_BCTRL | ST7701_WRCTRLD_DD | ST7701_WRCTRLD_BL;
+	ret = st7701_dcs_write(dev, MIPI_DCS_WRITE_CONTROL_DISPLAY, buf, 1);
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* Adaptive brightness control */
+	buf[0] = ST7701_WRCABC_UI;
+	ret = st7701_dcs_write(dev, MIPI_DCS_WRITE_POWER_SAVE, buf, 1);
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* Adaptive brightness control minimum brightness */
+	buf[0] = 0xFF;
+	ret = st7701_dcs_write(dev, MIPI_DCS_SET_CABC_MIN_BRIGHTNESS, buf, 1);
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* Brightness */
+	buf[0] = 0xFF;
+	ret = st7701_dcs_write(dev, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, buf, 1);
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* Display On */
+	ret = st7701_dcs_write(dev, MIPI_DCS_SET_DISPLAY_ON, NULL, 0);
+	if (ret < 0) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static int st7701_blanking_on(const struct device *dev)
+{
+	const struct st7701_config *cfg = dev->config;
+	int ret;
+
+	if (cfg->backlight.port != NULL) {
+		ret = gpio_pin_set_dt(&cfg->backlight, 0);
+		if (ret) {
+			LOG_ERR("Disable backlight failed! (%d)", ret);
+			return ret;
+		}
+	}
+
+	return st7701_dcs_write(dev, MIPI_DCS_SET_DISPLAY_OFF, NULL, 0);
+}
+
+static int st7701_blanking_off(const struct device *dev)
+{
+	const struct st7701_config *cfg = dev->config;
+	int ret;
+
+	if (cfg->backlight.port != NULL) {
+		ret = gpio_pin_set_dt(&cfg->backlight, 1);
+		if (ret) {
+			LOG_ERR("Enable backlight failed! (%d)", ret);
+			return ret;
+		}
+	}
+
+	return st7701_dcs_write(dev, MIPI_DCS_SET_DISPLAY_ON, NULL, 0);
+}
+
+static int st7701_set_brightness(const struct device *dev, uint8_t brightness)
+{
+	return st7701_dcs_write(dev, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, &brightness, 1);
+}
+
+static void st7701_get_capabilities(const struct device *dev,
+				    struct display_capabilities *capabilities)
+{
+	const struct st7701_config *cfg = dev->config;
+	struct st7701_data *data = dev->data;
+
+	if (!capabilities) {
+		return;
+	}
+
+	memset(capabilities, 0, sizeof(struct display_capabilities));
+	capabilities->x_resolution = cfg->width;
+	capabilities->y_resolution = cfg->height;
+	capabilities->supported_pixel_formats = data->pixel_format;
+	capabilities->current_pixel_format = data->pixel_format;
+	capabilities->current_orientation = data->orientation;
+}
+
+static DEVICE_API(display, st7701_api) = {
+	.blanking_on = st7701_blanking_on,
+	.blanking_off = st7701_blanking_off,
+	.set_brightness = st7701_set_brightness,
+	.get_capabilities = st7701_get_capabilities,
+};
+
+static int st7701_init(const struct device *dev)
+{
+	const struct st7701_config *cfg = dev->config;
+	struct st7701_data *data = dev->data;
+	struct mipi_dsi_device mdev;
+	int ret;
+
+	if (cfg->reset.port) {
+		if (!gpio_is_ready_dt(&cfg->reset)) {
+			LOG_ERR("Reset GPIO device is not ready!");
+			return -ENODEV;
+		}
+
+		ret = gpio_pin_configure_dt(&cfg->reset, GPIO_OUTPUT_INACTIVE);
+		if (ret < 0) {
+			LOG_ERR("Reset display failed! (%d)", ret);
+			return ret;
+		}
+
+		k_msleep(10);
+		ret = gpio_pin_set_dt(&cfg->reset, 1);
+		if (ret < 0) {
+			LOG_ERR("Enable display failed! (%d)", ret);
+			return ret;
+		}
+
+		k_msleep(100);
+	}
+
+	/* store x/y resolution & rotation */
+	if (cfg->rotation == 0) {
+		data->xres = cfg->width;
+		data->yres = cfg->height;
+		data->orientation = DISPLAY_ORIENTATION_NORMAL;
+	} else if (cfg->rotation == 90) {
+		data->xres = cfg->height;
+		data->yres = cfg->width;
+		data->orientation = DISPLAY_ORIENTATION_ROTATED_90;
+	} else if (cfg->rotation == 180) {
+		data->xres = cfg->width;
+		data->yres = cfg->height;
+		data->orientation = DISPLAY_ORIENTATION_ROTATED_180;
+	} else if (cfg->rotation == 270) {
+		data->xres = cfg->height;
+		data->yres = cfg->width;
+		data->orientation = DISPLAY_ORIENTATION_ROTATED_270;
+	}
+
+	/* attach to MIPI-DSI host */
+	mdev.data_lanes = cfg->data_lanes;
+	mdev.pixfmt = data->dsi_pixel_format;
+	mdev.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | MIPI_DSI_MODE_LPM;
+
+	mdev.timings.hactive = cfg->width;
+	mdev.timings.hbp = cfg->hbp;
+	mdev.timings.hsync = cfg->hsync;
+	mdev.timings.hfp = cfg->hfp;
+	mdev.timings.vactive = cfg->height;
+	mdev.timings.vbp = cfg->vbp;
+	mdev.timings.vsync = cfg->vsync;
+	mdev.timings.vfp = cfg->vfp;
+
+	ret = mipi_dsi_attach(cfg->mipi_dsi, cfg->channel, &mdev);
+	if (ret < 0) {
+		LOG_ERR("MIPI-DSI attach failed! (%d)", ret);
+		return ret;
+	}
+
+	ret = st7701_check_id(dev);
+	if (ret) {
+		LOG_ERR("Panel ID check failed! (%d)", ret);
+		return ret;
+	}
+
+	ret = st7701_configure(dev);
+	if (ret) {
+		LOG_ERR("DSI init sequence failed! (%d)", ret);
+		return ret;
+	}
+
+	ret = st7701_blanking_off(dev);
+	if (ret) {
+		LOG_ERR("Display blanking off failed! (%d)", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+#define ST7701_DEVICE(inst)                                                                        \
+	static const struct st7701_config st7701_config_##inst = {                                 \
+		.mipi_dsi = DEVICE_DT_GET(DT_INST_BUS(inst)),                                      \
+		.reset = GPIO_DT_SPEC_INST_GET_OR(inst, reset_gpios, {0}),                         \
+		.backlight = GPIO_DT_SPEC_INST_GET_OR(inst, bl_gpios, {0}),                        \
+		.data_lanes = DT_INST_PROP_BY_IDX(inst, data_lanes, 0),                            \
+		.width = DT_INST_PROP(inst, width),                                                \
+		.height = DT_INST_PROP(inst, height),                                              \
+		.channel = DT_INST_REG_ADDR(inst),                                                 \
+		.rotation = DT_INST_PROP(inst, rotation),                                          \
+		.hbp = DT_PROP(DT_INST_CHILD(inst, display_timings), hback_porch),                 \
+		.hsync = DT_PROP(DT_INST_CHILD(inst, display_timings), hsync_len),                 \
+		.hfp = DT_PROP(DT_INST_CHILD(inst, display_timings), hfront_porch),                \
+		.vbp = DT_PROP(DT_INST_CHILD(inst, display_timings), vback_porch),                 \
+		.vsync = DT_PROP(DT_INST_CHILD(inst, display_timings), vsync_len),                 \
+		.vfp = DT_PROP(DT_INST_CHILD(inst, display_timings), vfront_porch),                \
+		.gip_e0 = DT_INST_PROP_OR(inst, gip_e0, {}),                                       \
+		.gip_e1 = DT_INST_PROP_OR(inst, gip_e1, {}),                                       \
+		.gip_e2 = DT_INST_PROP_OR(inst, gip_e2, {}),                                       \
+		.gip_e3 = DT_INST_PROP_OR(inst, gip_e3, {}),                                       \
+		.gip_e4 = DT_INST_PROP_OR(inst, gip_e4, {}),                                       \
+		.gip_e5 = DT_INST_PROP_OR(inst, gip_e5, {}),                                       \
+		.gip_e6 = DT_INST_PROP_OR(inst, gip_e6, {}),                                       \
+		.gip_e7 = DT_INST_PROP_OR(inst, gip_e7, {}),                                       \
+		.gip_e8 = DT_INST_PROP_OR(inst, gip_e8, {}),                                       \
+		.gip_eb = DT_INST_PROP_OR(inst, gip_eb, {}),                                       \
+		.gip_ec = DT_INST_PROP_OR(inst, gip_ec, {}),                                       \
+		.gip_ed = DT_INST_PROP_OR(inst, gip_ed, {}),                                       \
+		.pvgamctrl = DT_INST_PROP_OR(inst, pvgamctrl, {}),                                 \
+		.nvgamctrl = DT_INST_PROP_OR(inst, nvgamctrl, {}),                                 \
+	};                                                                                         \
+	static struct st7701_data st7701_data_##inst = {                                           \
+		.dsi_pixel_format = DT_INST_PROP(inst, pixel_format),                              \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(inst, &st7701_init, NULL, &st7701_data_##inst,                       \
+			      &st7701_config_##inst, POST_KERNEL,                                  \
+			      CONFIG_DISPLAY_INIT_PRIORITY, &st7701_api);
+
+DT_INST_FOREACH_STATUS_OKAY(ST7701_DEVICE)
diff --git a/drivers/display/display_st7789v.c b/drivers/display/display_st7789v.c
index 2dab4bb17a2..084d48a3e54 100644
--- a/drivers/display/display_st7789v.c
+++ b/drivers/display/display_st7789v.c
@@ -45,6 +45,7 @@ struct st7789v_config {
 	uint8_t rgb_param[3];
 	uint16_t height;
 	uint16_t width;
+	uint8_t ready_time_ms;
 };
 
 struct st7789v_data {
@@ -67,22 +68,29 @@ static void st7789v_set_lcd_margins(const struct device *dev,
 	data->y_offset = y_offset;
 }
 
-static void st7789v_transmit(const struct device *dev, uint8_t cmd,
-			     uint8_t *tx_data, size_t tx_count)
+static int st7789v_transmit(const struct device *dev, uint8_t cmd,
+			    uint8_t *tx_data, size_t tx_count)
 {
 	const struct st7789v_config *config = dev->config;
 
-	mipi_dbi_command_write(config->mipi_dbi, &config->dbi_config, cmd,
-			       tx_data, tx_count);
+	return mipi_dbi_command_write(config->mipi_dbi, &config->dbi_config,
+				      cmd, tx_data, tx_count);
 }
 
-static void st7789v_exit_sleep(const struct device *dev)
+static int st7789v_exit_sleep(const struct device *dev)
 {
-	st7789v_transmit(dev, ST7789V_CMD_SLEEP_OUT, NULL, 0);
+	int ret;
+
+	ret = st7789v_transmit(dev, ST7789V_CMD_SLEEP_OUT, NULL, 0);
+	if (ret < 0) {
+		return ret;
+	}
+
 	k_sleep(K_MSEC(120));
+	return ret;
 }
 
-static void st7789v_reset_display(const struct device *dev)
+static int st7789v_reset_display(const struct device *dev)
 {
 	const struct st7789v_config *config = dev->config;
 	int ret;
@@ -93,26 +101,29 @@ static void st7789v_reset_display(const struct device *dev)
 	ret = mipi_dbi_reset(config->mipi_dbi, 6);
 	if (ret == -ENOTSUP) {
 		/* Send software reset command */
-		st7789v_transmit(dev, ST7789V_CMD_SW_RESET, NULL, 0);
+		ret = st7789v_transmit(dev, ST7789V_CMD_SW_RESET, NULL, 0);
+		if (ret < 0) {
+			return ret;
+		}
 		k_sleep(K_MSEC(5));
 	} else {
 		k_sleep(K_MSEC(20));
 	}
+
+	return ret;
 }
 
 static int st7789v_blanking_on(const struct device *dev)
 {
-	st7789v_transmit(dev, ST7789V_CMD_DISP_OFF, NULL, 0);
-	return 0;
+	return st7789v_transmit(dev, ST7789V_CMD_DISP_OFF, NULL, 0);
 }
 
 static int st7789v_blanking_off(const struct device *dev)
 {
-	st7789v_transmit(dev, ST7789V_CMD_DISP_ON, NULL, 0);
-	return 0;
+	return st7789v_transmit(dev, ST7789V_CMD_DISP_ON, NULL, 0);
 }
 
-static void st7789v_set_mem_area(const struct device *dev, const uint16_t x,
+static int st7789v_set_mem_area(const struct device *dev, const uint16_t x,
 				 const uint16_t y, const uint16_t w, const uint16_t h)
 {
 	struct st7789v_data *data = dev->data;
@@ -121,13 +132,18 @@ static void st7789v_set_mem_area(const struct device *dev, const uint16_t x,
 	uint16_t ram_x = x + data->x_offset;
 	uint16_t ram_y = y + data->y_offset;
 
+	int ret;
+
 	spi_data[0] = sys_cpu_to_be16(ram_x);
 	spi_data[1] = sys_cpu_to_be16(ram_x + w - 1);
-	st7789v_transmit(dev, ST7789V_CMD_CASET, (uint8_t *)&spi_data[0], 4);
+	ret = st7789v_transmit(dev, ST7789V_CMD_CASET, (uint8_t *)&spi_data[0], 4);
+	if (ret < 0) {
+		return ret;
+	}
 
 	spi_data[0] = sys_cpu_to_be16(ram_y);
 	spi_data[1] = sys_cpu_to_be16(ram_y + h - 1);
-	st7789v_transmit(dev, ST7789V_CMD_RASET, (uint8_t *)&spi_data[0], 4);
+	return st7789v_transmit(dev, ST7789V_CMD_RASET, (uint8_t *)&spi_data[0], 4);
 }
 
 static int st7789v_write(const struct device *dev,
@@ -142,6 +158,7 @@ static int st7789v_write(const struct device *dev,
 	uint16_t nbr_of_writes;
 	uint16_t write_h;
 	enum display_pixel_format pixfmt;
+	int ret;
 
 	__ASSERT(desc->width <= desc->pitch, "Pitch is smaller than width");
 	__ASSERT((desc->pitch * ST7789V_PIXEL_SIZE * desc->height) <= desc->buf_size,
@@ -149,7 +166,10 @@ static int st7789v_write(const struct device *dev,
 
 	LOG_DBG("Writing %dx%d (w,h) @ %dx%d (x,y)",
 		desc->width, desc->height, x, y);
-	st7789v_set_mem_area(dev, x, y, desc->width, desc->height);
+	ret = st7789v_set_mem_area(dev, x, y, desc->width, desc->height);
+	if (ret < 0) {
+		return ret;
+	}
 
 	if (desc->pitch > desc->width) {
 		write_h = 1U;
@@ -175,16 +195,22 @@ static int st7789v_write(const struct device *dev,
 	mipi_desc.pitch = desc->width;
 
 	/* Send RAMWR command */
-	st7789v_transmit(dev, ST7789V_CMD_RAMWR, NULL, 0);
+	ret = st7789v_transmit(dev, ST7789V_CMD_RAMWR, NULL, 0);
+	if (ret < 0) {
+		return ret;
+	}
 
 	for (uint16_t write_cnt = 0U; write_cnt < nbr_of_writes; ++write_cnt) {
-		mipi_dbi_write_display(config->mipi_dbi, &config->dbi_config,
-				       write_data_start, &mipi_desc, pixfmt);
+		ret = mipi_dbi_write_display(config->mipi_dbi, &config->dbi_config,
+					     write_data_start, &mipi_desc, pixfmt);
+		if (ret < 0) {
+			return ret;
+		}
 
 		write_data_start += (desc->pitch * ST7789V_PIXEL_SIZE);
 	}
 
-	return 0;
+	return ret;
 }
 
 static void st7789v_get_capabilities(const struct device *dev,
@@ -235,121 +261,196 @@ static int st7789v_set_orientation(const struct device *dev,
 	return -ENOTSUP;
 }
 
-static void st7789v_lcd_init(const struct device *dev)
+static int st7789v_lcd_init(const struct device *dev)
 {
 	struct st7789v_data *data = dev->data;
 	const struct st7789v_config *config = dev->config;
 	uint8_t tmp;
+	int ret;
 
 	st7789v_set_lcd_margins(dev, data->x_offset,
 				data->y_offset);
 
-	st7789v_transmit(dev, ST7789V_CMD_CMD2EN,
-			 (uint8_t *)config->cmd2en_param,
-			 sizeof(config->cmd2en_param));
+	ret = st7789v_transmit(dev, ST7789V_CMD_CMD2EN,
+			       (uint8_t *)config->cmd2en_param,
+			       sizeof(config->cmd2en_param));
+	if (ret < 0) {
+		return ret;
+	}
 
-	st7789v_transmit(dev, ST7789V_CMD_PORCTRL,
-			 (uint8_t *)config->porch_param,
-			 sizeof(config->porch_param));
+	ret = st7789v_transmit(dev, ST7789V_CMD_PORCTRL,
+			       (uint8_t *)config->porch_param,
+			       sizeof(config->porch_param));
+	if (ret < 0) {
+		return ret;
+	}
 
 	/* Digital Gamma Enable, default disabled */
 	tmp = 0x00;
-	st7789v_transmit(dev, ST7789V_CMD_DGMEN, &tmp, 1);
+	ret = st7789v_transmit(dev, ST7789V_CMD_DGMEN, &tmp, 1);
+	if (ret < 0) {
+		return ret;
+	}
 
 	/* Frame Rate Control in Normal Mode, default value */
 	tmp = 0x0f;
-	st7789v_transmit(dev, ST7789V_CMD_FRCTRL2, &tmp, 1);
+	ret = st7789v_transmit(dev, ST7789V_CMD_FRCTRL2, &tmp, 1);
+	if (ret < 0) {
+		return ret;
+	}
 
 	tmp = config->gctrl;
-	st7789v_transmit(dev, ST7789V_CMD_GCTRL, &tmp, 1);
+	ret = st7789v_transmit(dev, ST7789V_CMD_GCTRL, &tmp, 1);
+	if (ret < 0) {
+		return ret;
+	}
 
 	tmp = config->vcom;
-	st7789v_transmit(dev, ST7789V_CMD_VCOMS, &tmp, 1);
+	ret = st7789v_transmit(dev, ST7789V_CMD_VCOMS, &tmp, 1);
+	if (ret < 0) {
+		return ret;
+	}
 
 	if (config->vdv_vrh_enable) {
 		tmp = 0x01;
-		st7789v_transmit(dev, ST7789V_CMD_VDVVRHEN, &tmp, 1);
+		ret = st7789v_transmit(dev, ST7789V_CMD_VDVVRHEN, &tmp, 1);
+		if (ret < 0) {
+			return ret;
+		}
 
 		tmp = config->vrh_value;
-		st7789v_transmit(dev, ST7789V_CMD_VRH, &tmp, 1);
+		ret = st7789v_transmit(dev, ST7789V_CMD_VRH, &tmp, 1);
+		if (ret < 0) {
+			return ret;
+		}
 
 		tmp = config->vdv_value;
-		st7789v_transmit(dev, ST7789V_CMD_VDS, &tmp, 1);
+		ret = st7789v_transmit(dev, ST7789V_CMD_VDS, &tmp, 1);
+		if (ret < 0) {
+			return ret;
+		}
 	}
 
-	st7789v_transmit(dev, ST7789V_CMD_PWCTRL1,
-			 (uint8_t *)config->pwctrl1_param,
-			 sizeof(config->pwctrl1_param));
+	ret = st7789v_transmit(dev, ST7789V_CMD_PWCTRL1,
+			       (uint8_t *)config->pwctrl1_param,
+			       sizeof(config->pwctrl1_param));
+	if (ret < 0) {
+		return ret;
+	}
 
 	/* Memory Data Access Control */
 	tmp = config->mdac;
-	st7789v_transmit(dev, ST7789V_CMD_MADCTL, &tmp, 1);
+	ret = st7789v_transmit(dev, ST7789V_CMD_MADCTL, &tmp, 1);
+	if (ret < 0) {
+		return ret;
+	}
 
 	/* Interface Pixel Format */
 	tmp = config->colmod;
-	st7789v_transmit(dev, ST7789V_CMD_COLMOD, &tmp, 1);
+	ret = st7789v_transmit(dev, ST7789V_CMD_COLMOD, &tmp, 1);
+	if (ret < 0) {
+		return ret;
+	}
 
 	tmp = config->lcm;
-	st7789v_transmit(dev, ST7789V_CMD_LCMCTRL, &tmp, 1);
+	ret = st7789v_transmit(dev, ST7789V_CMD_LCMCTRL, &tmp, 1);
+	if (ret < 0) {
+		return ret;
+	}
 
 	tmp = config->gamma;
-	st7789v_transmit(dev, ST7789V_CMD_GAMSET, &tmp, 1);
+	ret = st7789v_transmit(dev, ST7789V_CMD_GAMSET, &tmp, 1);
+	if (ret < 0) {
+		return ret;
+	}
 
 	if (config->inversion_on) {
-		st7789v_transmit(dev, ST7789V_CMD_INV_ON, NULL, 0);
+		ret = st7789v_transmit(dev, ST7789V_CMD_INV_ON, NULL, 0);
 	} else {
-		st7789v_transmit(dev, ST7789V_CMD_INV_OFF, NULL, 0);
+		ret = st7789v_transmit(dev, ST7789V_CMD_INV_OFF, NULL, 0);
+	}
+	if (ret < 0) {
+		return ret;
 	}
 
-	st7789v_transmit(dev, ST7789V_CMD_PVGAMCTRL,
-			 (uint8_t *)config->pvgam_param,
-			 sizeof(config->pvgam_param));
+	ret = st7789v_transmit(dev, ST7789V_CMD_PVGAMCTRL,
+			       (uint8_t *)config->pvgam_param,
+			       sizeof(config->pvgam_param));
+	if (ret < 0) {
+		return ret;
+	}
 
-	st7789v_transmit(dev, ST7789V_CMD_NVGAMCTRL,
-			 (uint8_t *)config->nvgam_param,
-			 sizeof(config->nvgam_param));
+	ret = st7789v_transmit(dev, ST7789V_CMD_NVGAMCTRL,
+			       (uint8_t *)config->nvgam_param,
+			       sizeof(config->nvgam_param));
+	if (ret < 0) {
+		return ret;
+	}
 
-	st7789v_transmit(dev, ST7789V_CMD_RAMCTRL,
-			 (uint8_t *)config->ram_param,
-			 sizeof(config->ram_param));
+	ret = st7789v_transmit(dev, ST7789V_CMD_RAMCTRL,
+			       (uint8_t *)config->ram_param,
+			       sizeof(config->ram_param));
+	if (ret < 0) {
+		return ret;
+	}
 
-	st7789v_transmit(dev, ST7789V_CMD_RGBCTRL,
-			 (uint8_t *)config->rgb_param,
-			 sizeof(config->rgb_param));
+	ret = st7789v_transmit(dev, ST7789V_CMD_RGBCTRL,
+			       (uint8_t *)config->rgb_param,
+			       sizeof(config->rgb_param));
+	return ret;
 }
 
 static int st7789v_init(const struct device *dev)
 {
 	const struct st7789v_config *config = dev->config;
+	int ret;
 
 	if (!device_is_ready(config->mipi_dbi)) {
 		LOG_ERR("MIPI DBI device not ready");
 		return -ENODEV;
 	}
 
-	st7789v_reset_display(dev);
+	k_sleep(K_TIMEOUT_ABS_MS(config->ready_time_ms));
 
-	st7789v_blanking_on(dev);
+	ret = st7789v_reset_display(dev);
+	if (ret < 0) {
+		LOG_ERR("Failed to reset display (%d)", ret);
+		return ret;
+	}
 
-	st7789v_lcd_init(dev);
+	ret = st7789v_blanking_on(dev);
+	if (ret < 0) {
+		LOG_ERR("Failed to turn blanking on (%d)", ret);
+		return ret;
+	}
 
-	st7789v_exit_sleep(dev);
+	ret = st7789v_lcd_init(dev);
+	if (ret < 0) {
+		LOG_ERR("Failed to init display (%d)", ret);
+		return ret;
+	}
 
-	return 0;
+	ret = st7789v_exit_sleep(dev);
+	if (ret < 0) {
+		LOG_ERR("Failed to exit the sleep mode (%d)", ret);
+		return ret;
+	}
+
+	return ret;
 }
 
 #ifdef CONFIG_PM_DEVICE
 static int st7789v_pm_action(const struct device *dev,
 			     enum pm_device_action action)
 {
-	int ret = 0;
+	int ret;
 
 	switch (action) {
 	case PM_DEVICE_ACTION_RESUME:
-		st7789v_exit_sleep(dev);
+		ret = st7789v_exit_sleep(dev);
 		break;
 	case PM_DEVICE_ACTION_SUSPEND:
-		st7789v_transmit(dev, ST7789V_CMD_SLEEP_IN, NULL, 0);
+		ret = st7789v_transmit(dev, ST7789V_CMD_SLEEP_IN, NULL, 0);
 		break;
 	default:
 		ret = -ENOTSUP;
@@ -398,6 +499,7 @@ static DEVICE_API(display, st7789v_api) = {
 		.rgb_param = DT_INST_PROP(inst, rgb_param),				\
 		.width = DT_INST_PROP(inst, width),					\
 		.height = DT_INST_PROP(inst, height),					\
+		.ready_time_ms = DT_INST_PROP(inst, ready_time_ms),			\
 	};										\
 											\
 	static struct st7789v_data st7789v_data_ ## inst = {				\
diff --git a/drivers/display/display_stm32_ltdc.c b/drivers/display/display_stm32_ltdc.c
index e9e61da7496..2de41651fd9 100644
--- a/drivers/display/display_stm32_ltdc.c
+++ b/drivers/display/display_stm32_ltdc.c
@@ -21,6 +21,9 @@
 #include <zephyr/pm/device.h>
 #include <zephyr/sys/barrier.h>
 #include <zephyr/cache.h>
+#if defined(CONFIG_STM32_LTDC_FB_USE_SHARED_MULTI_HEAP)
+#include <zephyr/multi_heap/shared_multi_heap.h>
+#endif
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(display_stm32_ltdc, CONFIG_DISPLAY_LOG_LEVEL);
@@ -73,7 +76,8 @@ struct display_stm32_ltdc_config {
 	uint32_t height;
 	struct gpio_dt_spec disp_on_gpio;
 	struct gpio_dt_spec bl_ctrl_gpio;
-	struct stm32_pclken pclken;
+	const struct stm32_pclken *pclken;
+	size_t pclk_len;
 	const struct reset_dt_spec reset;
 	const struct pinctrl_dev_config *pctrl;
 	void (*irq_config_func)(const struct device *dev);
@@ -294,11 +298,22 @@ static int stm32_ltdc_display_blanking_on(const struct device *dev)
 	return display_blanking_on(display_dev);
 }
 
+/* This symbol takes the value 1 if one of the device instances */
+/* is configured in dts with a domain clock */
+#if STM32_DT_INST_DEV_DOMAIN_CLOCK_SUPPORT
+#define STM32_LTDC_DOMAIN_CLOCK_SUPPORT 1
+#else
+#define STM32_LTDC_DOMAIN_CLOCK_SUPPORT 0
+#endif
+
 static int stm32_ltdc_init(const struct device *dev)
 {
 	int err;
 	const struct display_stm32_ltdc_config *config = dev->config;
 	struct display_stm32_ltdc_data *data = dev->data;
+#if defined(CONFIG_SOC_SERIES_STM32N6X)
+	RIMC_MasterConfig_t rimc = {0};
+#endif
 
 	/* Configure and set display on/off GPIO */
 	if (config->disp_on_gpio.port) {
@@ -334,12 +349,23 @@ static int stm32_ltdc_init(const struct device *dev)
 
 	/* Turn on LTDC peripheral clock */
 	err = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
-				(clock_control_subsys_t) &config->pclken);
+				(clock_control_subsys_t) &config->pclken[0]);
 	if (err < 0) {
 		LOG_ERR("Could not enable LTDC peripheral clock");
 		return err;
 	}
 
+	if (IS_ENABLED(STM32_LTDC_DOMAIN_CLOCK_SUPPORT) && (config->pclk_len > 1)) {
+		/* Enable LTDC clock source */
+		err = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+					      (clock_control_subsys_t) &config->pclken[1],
+					      NULL);
+		if (err < 0) {
+			LOG_ERR("Could not configure LTDC peripheral clock");
+			return err;
+		}
+	}
+
 #if defined(CONFIG_SOC_SERIES_STM32F4X)
 	LL_RCC_PLLSAI_Disable();
 	LL_RCC_PLLSAI_ConfigDomain_LTDC(LL_RCC_PLLSOURCE_HSE,
@@ -391,6 +417,21 @@ static int stm32_ltdc_init(const struct device *dev)
 		return err;
 	}
 
+#if defined(CONFIG_STM32_LTDC_FB_USE_SHARED_MULTI_HEAP)
+	data->frame_buffer = shared_multi_heap_aligned_alloc(
+			CONFIG_VIDEO_BUFFER_SMH_ATTRIBUTE,
+			32,
+			CONFIG_STM32_LTDC_FB_NUM * data->frame_buffer_len);
+
+	if (data->frame_buffer == NULL) {
+		return -ENOMEM;
+	}
+
+	data->pend_buf = data->frame_buffer;
+	data->front_buf = data->frame_buffer;
+	data->hltdc.LayerCfg[0].FBStartAdress = (uint32_t) data->frame_buffer;
+#endif
+
 	/* Configure layer 1 (only one layer is used) */
 	/* LTDC starts fetching pixels and sending them to display after this call */
 	err = HAL_LTDC_ConfigLayer(&data->hltdc, &data->hltdc.LayerCfg[0], LTDC_LAYER_1);
@@ -398,6 +439,15 @@ static int stm32_ltdc_init(const struct device *dev)
 		return err;
 	}
 
+#if defined(CONFIG_SOC_SERIES_STM32N6X)
+	/* Configure RIF for LTDC layer 1 */
+	rimc.MasterCID = RIF_CID_1;
+	rimc.SecPriv = RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV;
+	HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_LTDC1 , &rimc);
+	HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_LTDCL1,
+					      RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
+#endif
+
 	/* Disable layer 2, since it not used */
 	__HAL_LTDC_LAYER_DISABLE(&data->hltdc, LTDC_LAYER_2);
 
@@ -437,7 +487,7 @@ static int stm32_ltdc_suspend(const struct device *dev)
 
 	/* Turn off LTDC peripheral clock */
 	err = clock_control_off(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
-				(clock_control_subsys_t) &config->pclken);
+				(clock_control_subsys_t) &config->pclken[0]);
 
 	return err;
 }
@@ -483,8 +533,10 @@ static DEVICE_API(display, stm32_ltdc_display_api) = {
 #define FRAME_BUFFER_SECTION __stm32_sdram1_section
 #elif DT_SAME_NODE(DT_INST_PHANDLE(0, ext_sdram), DT_NODELABEL(sdram2))
 #define FRAME_BUFFER_SECTION __stm32_sdram2_section
+#elif DT_SAME_NODE(DT_INST_PHANDLE(0, ext_sdram), DT_NODELABEL(psram))
+#define FRAME_BUFFER_SECTION __stm32_psram_section
 #else
-#error "LTDC ext-sdram property in device tree does not reference SDRAM1 or SDRAM2 node"
+#error "LTDC ext-sdram property in device tree does not reference SDRAM1 or SDRAM2 node or PSRAM node"
 #define FRAME_BUFFER_SECTION
 #endif /* DT_SAME_NODE(DT_INST_PHANDLE(0, ext_sdram), DT_NODELABEL(sdram1)) */
 
@@ -503,7 +555,19 @@ static DEVICE_API(display, stm32_ltdc_display_api) = {
 #define STM32_LTDC_FRAME_BUFFER_LEN(inst)							\
 	(STM32_LTDC_INIT_PIXEL_SIZE * DT_INST_PROP(inst, height) * DT_INST_PROP(inst, width))	\
 
+#if defined(CONFIG_STM32_LTDC_FB_USE_SHARED_MULTI_HEAP)
+#define STM32_LTDC_FRAME_BUFFER_ADDR(inst)  (NULL)
+#define STM32_LTDC_FRAME_BUFFER_DEFINE(inst)
+#else
+#define STM32_LTDC_FRAME_BUFFER_ADDR(inst)  frame_buffer_##inst
+#define STM32_LTDC_FRAME_BUFFER_DEFINE(inst)    \
+	/* frame buffer aligned to cache line width for optimal cache flushing */                  \
+	FRAME_BUFFER_SECTION static uint8_t __aligned(32)                                          \
+		frame_buffer_##inst[CONFIG_STM32_LTDC_FB_NUM * STM32_LTDC_FRAME_BUFFER_LEN(inst)];
+#endif
+
 #define STM32_LTDC_DEVICE(inst)									\
+	STM32_LTDC_FRAME_BUFFER_DEFINE(inst);                       \
 	STM32_LTDC_DEVICE_PINCTRL_INIT(inst);							\
 	PM_DEVICE_DT_INST_DEFINE(inst, stm32_ltdc_pm_action);					\
 	static void stm32_ltdc_irq_config_func_##inst(const struct device *dev)			\
@@ -515,15 +579,11 @@ static DEVICE_API(display, stm32_ltdc_display_api) = {
 			    0);									\
 		irq_enable(DT_INST_IRQN(inst));							\
 	}											\
-	/* frame buffer aligned to cache line width for optimal cache flushing */		\
-	FRAME_BUFFER_SECTION static uint8_t __aligned(32)					\
-				frame_buffer_##inst[CONFIG_STM32_LTDC_FB_NUM *			\
-							STM32_LTDC_FRAME_BUFFER_LEN(inst)];	\
 	static struct display_stm32_ltdc_data stm32_ltdc_data_##inst = {			\
-		.frame_buffer = frame_buffer_##inst,						\
+		.frame_buffer = STM32_LTDC_FRAME_BUFFER_ADDR(inst),				\
 		.frame_buffer_len = STM32_LTDC_FRAME_BUFFER_LEN(inst),				\
-		.front_buf = frame_buffer_##inst,						\
-		.pend_buf = frame_buffer_##inst,						\
+		.front_buf = STM32_LTDC_FRAME_BUFFER_ADDR(inst),				\
+		.pend_buf = STM32_LTDC_FRAME_BUFFER_ADDR(inst),					\
 		.hltdc = {									\
 			.Instance = (LTDC_TypeDef *) DT_INST_REG_ADDR(inst),			\
 			.Init = {								\
@@ -594,7 +654,7 @@ static DEVICE_API(display, stm32_ltdc_display_api) = {
 				.Alpha0 = 0,							\
 				.BlendingFactor1 = LTDC_BLENDING_FACTOR1_PAxCA,			\
 				.BlendingFactor2 = LTDC_BLENDING_FACTOR2_PAxCA,			\
-				.FBStartAdress = (uint32_t) frame_buffer_##inst,		\
+				.FBStartAdress = (uint32_t) STM32_LTDC_FRAME_BUFFER_ADDR(inst), \
 				.ImageWidth = DT_INST_PROP(inst, width),			\
 				.ImageHeight = DT_INST_PROP(inst, height),			\
 				.Backcolor.Red =						\
@@ -606,6 +666,9 @@ static DEVICE_API(display, stm32_ltdc_display_api) = {
 			},									\
 		},										\
 	};											\
+	static const struct stm32_pclken pclken_##inst[] =			\
+					 STM32_DT_INST_CLOCKS(inst);		\
+										\
 	static const struct display_stm32_ltdc_config stm32_ltdc_config_##inst = {		\
 		.width = DT_INST_PROP(inst, width),						\
 		.height = DT_INST_PROP(inst, height),						\
@@ -614,10 +677,8 @@ static DEVICE_API(display, stm32_ltdc_display_api) = {
 		.bl_ctrl_gpio = COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, bl_ctrl_gpios),		\
 				(GPIO_DT_SPEC_INST_GET(inst, bl_ctrl_gpios)), ({ 0 })),		\
 		.reset = RESET_DT_SPEC_INST_GET(0),						\
-		.pclken = {									\
-			.enr = DT_INST_CLOCKS_CELL(inst, bits),					\
-			.bus = DT_INST_CLOCKS_CELL(inst, bus)					\
-		},										\
+		.pclken = pclken_##inst,					\
+		.pclk_len = DT_INST_NUM_CLOCKS(inst),				\
 		.pctrl = STM32_LTDC_DEVICE_PINCTRL_GET(inst),					\
 		.irq_config_func = stm32_ltdc_irq_config_func_##inst,				\
 		.display_controller = DEVICE_DT_GET_OR_NULL(					\
diff --git a/drivers/display/ssd1306.c b/drivers/display/ssd1306.c
index 7d01b4fbd4e..8fe6a929313 100644
--- a/drivers/display/ssd1306.c
+++ b/drivers/display/ssd1306.c
@@ -23,6 +23,8 @@ LOG_MODULE_REGISTER(ssd1306, CONFIG_DISPLAY_LOG_LEVEL);
 #define SSD1306_PANEL_VCOM_DESEL_LEVEL	0x20
 #define SSD1306_PANEL_PUMP_VOLTAGE	SSD1306_SET_PUMP_VOLTAGE_90
 
+#define SSD1306_PANEL_VCOM_DESEL_LEVEL_SSD1309  0x34
+
 #ifndef SSD1306_ADDRESSING_MODE
 #define SSD1306_ADDRESSING_MODE		(SSD1306_SET_MEM_ADDRESSING_HORIZONTAL)
 #endif
@@ -41,6 +43,7 @@ struct ssd1306_config {
 	union ssd1306_bus bus;
 	struct gpio_dt_spec data_cmd;
 	struct gpio_dt_spec reset;
+	struct gpio_dt_spec supply;
 	ssd1306_bus_ready_fn bus_ready;
 	ssd1306_write_bus_fn write_bus;
 	ssd1306_bus_name_fn bus_name;
@@ -55,6 +58,7 @@ struct ssd1306_config {
 	bool com_invdir;
 	bool com_sequential;
 	bool color_inversion;
+	bool ssd1309_compatible;
 	bool sh1106_compatible;
 	int ready_time_ms;
 	bool use_internal_iref;
@@ -65,6 +69,7 @@ struct ssd1306_data {
 };
 
 #if (DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(solomon_ssd1306fb, i2c) || \
+	DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(solomon_ssd1309fb, i2c) || \
 	DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(sinowealth_sh1106, i2c))
 static bool ssd1306_bus_ready_i2c(const struct device *dev)
 {
@@ -92,6 +97,7 @@ static const char *ssd1306_bus_name_i2c(const struct device *dev)
 #endif
 
 #if (DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(solomon_ssd1306fb, spi) || \
+	DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(solomon_ssd1309fb, spi) || \
 	DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(sinowealth_sh1106, spi))
 static bool ssd1306_bus_ready_spi(const struct device *dev)
 {
@@ -167,7 +173,8 @@ static inline int ssd1306_set_timing_setting(const struct device *dev)
 			     SSD1306_SET_CHARGE_PERIOD,
 			     config->prechargep,
 			     SSD1306_SET_VCOM_DESELECT_LEVEL,
-			     SSD1306_PANEL_VCOM_DESEL_LEVEL};
+			     config->ssd1309_compatible ? SSD1306_PANEL_VCOM_DESEL_LEVEL_SSD1309 :
+				SSD1306_PANEL_VCOM_DESEL_LEVEL};
 
 	return ssd1306_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
 }
@@ -220,19 +227,33 @@ static inline int ssd1306_set_iref_mode(const struct device *dev)
 
 static int ssd1306_resume(const struct device *dev)
 {
+	const struct ssd1306_config *config = dev->config;
 	uint8_t cmd_buf[] = {
 		SSD1306_DISPLAY_ON,
 	};
 
+	/* Turn on supply if pin connected */
+	if (config->supply.port) {
+		gpio_pin_set_dt(&config->supply, 1);
+		k_sleep(K_MSEC(SSD1306_SUPPLY_DELAY));
+	}
+
 	return ssd1306_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
 }
 
 static int ssd1306_suspend(const struct device *dev)
 {
+	const struct ssd1306_config *config = dev->config;
 	uint8_t cmd_buf[] = {
 		SSD1306_DISPLAY_OFF,
 	};
 
+	/* Turn off supply if pin connected */
+	if (config->supply.port) {
+		gpio_pin_set_dt(&config->supply, 0);
+		k_sleep(K_MSEC(SSD1306_SUPPLY_DELAY));
+	}
+
 	return ssd1306_write_bus(dev, cmd_buf, sizeof(cmd_buf), true);
 }
 
@@ -402,6 +423,11 @@ static int ssd1306_init_device(const struct device *dev)
 	};
 
 	data->pf = config->color_inversion ? PIXEL_FORMAT_MONO10 : PIXEL_FORMAT_MONO01;
+	/* Turn on supply if pin connected */
+	if (config->supply.port) {
+		gpio_pin_set_dt(&config->supply, 1);
+		k_sleep(K_MSEC(SSD1306_SUPPLY_DELAY));
+	}
 
 	/* Reset if pin connected */
 	if (config->reset.port) {
@@ -428,12 +454,14 @@ static int ssd1306_init_device(const struct device *dev)
 		return -EIO;
 	}
 
-	if (ssd1306_set_charge_pump(dev)) {
-		return -EIO;
-	}
+	if (!config->ssd1309_compatible) {
+		if (ssd1306_set_charge_pump(dev)) {
+			return -EIO;
+		}
 
-	if (ssd1306_set_iref_mode(dev)) {
-		return -EIO;
+		if (ssd1306_set_iref_mode(dev)) {
+			return -EIO;
+		}
 	}
 
 	if (ssd1306_write_bus(dev, cmd_buf, sizeof(cmd_buf), true)) {
@@ -452,6 +480,7 @@ static int ssd1306_init_device(const struct device *dev)
 static int ssd1306_init(const struct device *dev)
 {
 	const struct ssd1306_config *config = dev->config;
+	int ret;
 
 	k_sleep(K_TIMEOUT_ABS_MS(config->ready_time_ms));
 
@@ -460,14 +489,28 @@ static int ssd1306_init(const struct device *dev)
 		return -EINVAL;
 	}
 
-	if (config->reset.port) {
-		int ret;
+	if (config->supply.port) {
+		ret = gpio_pin_configure_dt(&config->supply,
+					    GPIO_OUTPUT_INACTIVE);
+		if (ret < 0) {
+			return ret;
+		}
+		if (!gpio_is_ready_dt(&config->supply)) {
+			LOG_ERR("Supply GPIO device not ready");
+			return -ENODEV;
+		}
+	}
 
+	if (config->reset.port) {
 		ret = gpio_pin_configure_dt(&config->reset,
 					    GPIO_OUTPUT_INACTIVE);
 		if (ret < 0) {
 			return ret;
 		}
+		if (!gpio_is_ready_dt(&config->reset)) {
+			LOG_ERR("Reset GPIO device not ready");
+			return -ENODEV;
+		}
 	}
 
 	if (ssd1306_init_device(dev)) {
@@ -506,6 +549,7 @@ static DEVICE_API(display, ssd1306_driver_api) = {
 	static struct ssd1306_data data##node_id;                                                  \
 	static const struct ssd1306_config config##node_id = {                                     \
 		.reset = GPIO_DT_SPEC_GET_OR(node_id, reset_gpios, {0}),                           \
+		.supply = GPIO_DT_SPEC_GET_OR(node_id, supply_gpios, {0}),                         \
 		.height = DT_PROP(node_id, height),                                                \
 		.width = DT_PROP(node_id, width),                                                  \
 		.segment_offset = DT_PROP(node_id, segment_offset),                                \
@@ -517,6 +561,7 @@ static DEVICE_API(display, ssd1306_driver_api) = {
 		.com_sequential = DT_PROP(node_id, com_sequential),                                \
 		.prechargep = DT_PROP(node_id, prechargep),                                        \
 		.color_inversion = DT_PROP(node_id, inversion_on),                                 \
+		.ssd1309_compatible = DT_NODE_HAS_COMPAT(node_id, solomon_ssd1309fb),              \
 		.sh1106_compatible = DT_NODE_HAS_COMPAT(node_id, sinowealth_sh1106),               \
 		.ready_time_ms = DT_PROP(node_id, ready_time_ms),                                  \
 		.use_internal_iref = DT_PROP(node_id, use_internal_iref),                          \
@@ -528,4 +573,5 @@ static DEVICE_API(display, ssd1306_driver_api) = {
 			 POST_KERNEL, CONFIG_DISPLAY_INIT_PRIORITY, &ssd1306_driver_api);
 
 DT_FOREACH_STATUS_OKAY(solomon_ssd1306fb, SSD1306_DEFINE)
+DT_FOREACH_STATUS_OKAY(solomon_ssd1309fb, SSD1306_DEFINE)
 DT_FOREACH_STATUS_OKAY(sinowealth_sh1106, SSD1306_DEFINE)
diff --git a/drivers/display/ssd1306_regs.h b/drivers/display/ssd1306_regs.h
index c2982c1fae6..87dc3b6ba5b 100644
--- a/drivers/display/ssd1306_regs.h
+++ b/drivers/display/ssd1306_regs.h
@@ -118,5 +118,6 @@
 
 /* time constants in ms */
 #define SSD1306_RESET_DELAY			1
+#define SSD1306_SUPPLY_DELAY			20
 
 #endif
diff --git a/drivers/dma/CMakeLists.txt b/drivers/dma/CMakeLists.txt
index 58cc85e5c4e..8e82bc8719b 100644
--- a/drivers/dma/CMakeLists.txt
+++ b/drivers/dma/CMakeLists.txt
@@ -33,13 +33,16 @@ zephyr_library_sources_ifdef(CONFIG_DMA_ESP32		dma_esp32_gdma.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_MCHP_XEC	dma_mchp_xec.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_XMC4XXX		dma_xmc4xxx.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_RPI_PICO	dma_rpi_pico.c)
+zephyr_library_sources_ifdef(CONFIG_DMA_RENESAS_RZ	dma_renesas_rz.c)
 zephyr_library_sources_ifdef(CONFIG_MCUX_PXP		dma_mcux_pxp.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_MAX32		dma_max32.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_MCUX_SMARTDMA	dma_mcux_smartdma.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_ANDES_ATCDMAC300	dma_andes_atcdmac300.c)
+zephyr_library_sources_ifdef(CONFIG_DMA_INFINEON_CAT1	dma_ifx_cat1.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_SEDI		dma_sedi.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_SI32		dma_si32.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_SILABS_LDMA		dma_silabs_ldma.c)
+zephyr_library_sources_ifdef(CONFIG_DMA_SILABS_SIWX91X	dma_silabs_siwx91x.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_SMARTBOND   dma_smartbond.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_NXP_SOF_HOST_DMA dma_nxp_sof_host_dma.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_EMUL	    dma_emul.c)
@@ -47,3 +50,5 @@ zephyr_library_sources_ifdef(CONFIG_DMA_NXP_EDMA dma_nxp_edma.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_DW_AXI		dma_dw_axi.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_XILINX_AXI_DMA		dma_xilinx_axi_dma.c)
 zephyr_library_sources_ifdef(CONFIG_DMA_NXP_SDMA dma_nxp_sdma.c)
+zephyr_library_sources_ifdef(CONFIG_DMA_WCH             dma_wch.c)
+zephyr_library_sources_ifdef(CONFIG_DMA_TI_CC23X0	dma_ti_cc23x0.c)
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 1af7067dfb3..0bba13fb04f 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -58,6 +58,10 @@ source "drivers/dma/Kconfig.xmc4xxx"
 
 source "drivers/dma/Kconfig.rpi_pico"
 
+source "drivers/dma/Kconfig.renesas_rz"
+
+source "drivers/dma/Kconfig.ifx_cat1"
+
 source "drivers/dma/Kconfig.intel_lpss"
 
 source "drivers/dma/Kconfig.mcux_pxp"
@@ -74,6 +78,8 @@ source "drivers/dma/Kconfig.si32"
 
 source "drivers/dma/Kconfig.silabs"
 
+source "drivers/dma/Kconfig.siwx91x"
+
 source "drivers/dma/Kconfig.smartbond"
 
 source "drivers/dma/Kconfig.nxp_sof_host_dma"
@@ -87,4 +93,8 @@ source "drivers/dma/Kconfig.xilinx_axi_dma"
 
 source "drivers/dma/Kconfig.nxp_sdma"
 
+source "drivers/dma/Kconfig.wch"
+
+source "drivers/dma/Kconfig.ti_cc23x0"
+
 endif # DMA
diff --git a/drivers/dma/Kconfig.ifx_cat1 b/drivers/dma/Kconfig.ifx_cat1
new file mode 100644
index 00000000000..18066589773
--- /dev/null
+++ b/drivers/dma/Kconfig.ifx_cat1
@@ -0,0 +1,14 @@
+# Infineon CAT1 DMA configuration options
+
+# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
+# an affiliate of Cypress Semiconductor Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config DMA_INFINEON_CAT1
+	bool "Infineon CAT1 DMA driver"
+	default y
+	depends on DT_HAS_INFINEON_CAT1_DMA_ENABLED
+	select USE_INFINEON_DMA
+	help
+	  This option enables the DMA driver for Infineon CAT1 family.
diff --git a/drivers/dma/Kconfig.intel_adsp_hda b/drivers/dma/Kconfig.intel_adsp_hda
index 3090d8cb574..3c6ce8e045f 100644
--- a/drivers/dma/Kconfig.intel_adsp_hda
+++ b/drivers/dma/Kconfig.intel_adsp_hda
@@ -44,7 +44,7 @@ config DMA_INTEL_ADSP_HDA
 
 config DMA_INTEL_ADSP_HDA_TIMING_L1_EXIT
 	bool "Intel ADSP HDA Host L1 Exit Interrupt"
-	default y if SOC_INTEL_ACE15_MTPM || SOC_INTEL_ACE20_LNL || SOC_INTEL_ACE30
+	default y if SOC_SERIES_INTEL_ADSP_ACE
 	depends on DMA_INTEL_ADSP_HDA_HOST_IN || DMA_INTEL_ADSP_HDA_HOST_OUT
 	help
 	  Intel ADSP HDA Host Interrupt for L1 exit.
diff --git a/drivers/dma/Kconfig.mcux_edma b/drivers/dma/Kconfig.mcux_edma
index d6bd7b42cdf..e6014bb04ab 100644
--- a/drivers/dma/Kconfig.mcux_edma
+++ b/drivers/dma/Kconfig.mcux_edma
@@ -10,7 +10,7 @@ config DMA_MCUX_EDMA
 	bool "MCUX DMA driver"
 	default y
 	depends on $(dt_compat_any_has_prop,$(EDMA_COMPAT),$(REV_PROP),2)
-	imply NOCACHE_MEMORY if HAS_MCUX_CACHE
+	imply NOCACHE_MEMORY if CPU_HAS_DCACHE
 	help
 	  DMA driver for MCUX series SoCs.
 
diff --git a/drivers/dma/Kconfig.renesas_rz b/drivers/dma/Kconfig.renesas_rz
new file mode 100644
index 00000000000..fd40f348ace
--- /dev/null
+++ b/drivers/dma/Kconfig.renesas_rz
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config DMA_RENESAS_RZ
+	bool "Renesas RZ DMAC"
+	default y
+	depends on DT_HAS_RENESAS_RZ_DMA_ENABLED
+	select USE_RZ_FSP_DMA
+	help
+	  Enable Renesas RZ DMA Driver.
diff --git a/drivers/dma/Kconfig.rpi_pico b/drivers/dma/Kconfig.rpi_pico
index 434ac9fdf14..b491a9e02ab 100644
--- a/drivers/dma/Kconfig.rpi_pico
+++ b/drivers/dma/Kconfig.rpi_pico
@@ -9,4 +9,4 @@ config DMA_RPI_PICO
 	select PICOSDK_USE_CLAIM
 	depends on RESET
 	help
-	  DMA driver for RaspberryPi Pico.
+	  DMA driver for Raspberry Pi Pico.
diff --git a/drivers/dma/Kconfig.siwx91x b/drivers/dma/Kconfig.siwx91x
new file mode 100644
index 00000000000..a13491aa9ef
--- /dev/null
+++ b/drivers/dma/Kconfig.siwx91x
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config DMA_SILABS_SIWX91X
+	bool "Silabs SiWx91x DMA driver"
+	default y
+	select SYS_MEM_BLOCKS
+	depends on DT_HAS_SILABS_SIWX91X_DMA_ENABLED
+	help
+	  Enable the High Power(HP)/Ultra Low Power(ULP) DMA driver for the Silabs SiWx91x SoC series.
+
+if DMA_SILABS_SIWX91X
+
+config DMA_SILABS_SIWX91X_SG_BUFFER_COUNT
+	int "The maximum allowable number of buffers for scatter-gather transfers"
+	default 30
+
+endif
diff --git a/drivers/dma/Kconfig.ti_cc23x0 b/drivers/dma/Kconfig.ti_cc23x0
new file mode 100644
index 00000000000..eeac23f0b27
--- /dev/null
+++ b/drivers/dma/Kconfig.ti_cc23x0
@@ -0,0 +1,11 @@
+# TI CC23X0 DMA configuration options
+
+# Copyright (c) 2024 BayLibre, SAS
+# SPDX-License-Identifier: Apache-2.0
+
+config DMA_TI_CC23X0
+	bool "TI CC23X0 DMA driver"
+	default y
+	depends on DT_HAS_TI_CC23X0_DMA_ENABLED
+	help
+	  DMA driver for TI CC23X0 MCUs.
diff --git a/drivers/dma/Kconfig.wch b/drivers/dma/Kconfig.wch
new file mode 100644
index 00000000000..ed1d4e02f80
--- /dev/null
+++ b/drivers/dma/Kconfig.wch
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Paul Wedeck <paulwedeck@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config DMA_WCH
+	bool "CH32V DMA driver"
+	default y
+	depends on DT_HAS_WCH_WCH_DMA_ENABLED
+	help
+	  DMA driver for the WCH CH32V SoC family.
diff --git a/drivers/dma/Kconfig.xmc4xxx b/drivers/dma/Kconfig.xmc4xxx
index a2cf0a2e211..dd5feb3163b 100644
--- a/drivers/dma/Kconfig.xmc4xxx
+++ b/drivers/dma/Kconfig.xmc4xxx
@@ -9,3 +9,11 @@ config DMA_XMC4XXX
 	depends on DT_HAS_INFINEON_XMC4XXX_DMA_ENABLED
 	help
 	  DMA driver for Infineon xmc4xxx series MCUs.
+
+config DMA_XMC4XXX_NUM_DESCRIPTORS
+	int "Max DMA descriptors in a linked list"
+	default 4
+	depends on DMA_XMC4XXX
+	help
+	  Maximum number of blocks in a DMA block transfer configuration.
+	  Only supported by dma0 channels 0 and 1.
diff --git a/drivers/dma/dma_emul.c b/drivers/dma/dma_emul.c
index bdb5245ae46..6320d1c1620 100644
--- a/drivers/dma/dma_emul.c
+++ b/drivers/dma/dma_emul.c
@@ -70,11 +70,6 @@ static void dma_emul_work_handler(struct k_work *work);
 
 LOG_MODULE_REGISTER(dma_emul, CONFIG_DMA_LOG_LEVEL);
 
-static inline bool dma_emul_xfer_is_error_status(int status)
-{
-	return status < 0;
-}
-
 static inline const char *const dma_emul_channel_state_to_string(enum dma_emul_channel_state state)
 {
 	switch (state) {
diff --git a/drivers/dma/dma_esp32_gdma.c b/drivers/dma/dma_esp32_gdma.c
index c7874a65ce8..da7905fa574 100644
--- a/drivers/dma/dma_esp32_gdma.c
+++ b/drivers/dma/dma_esp32_gdma.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2022-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -21,17 +21,7 @@ LOG_MODULE_REGISTER(dma_esp32_gdma, CONFIG_DMA_LOG_LEVEL);
 #include <zephyr/drivers/dma.h>
 #include <zephyr/drivers/dma/dma_esp32.h>
 #include <zephyr/drivers/clock_control.h>
-#if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-#else
 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
-#endif
-
-#if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
-#define ISR_HANDLER isr_handler_t
-#else
-#define ISR_HANDLER intr_handler_t
-#endif
 
 #define DMA_MAX_CHANNEL SOC_GDMA_PAIRS_PER_GROUP
 
@@ -81,23 +71,23 @@ static void IRAM_ATTR dma_esp32_isr_handle_rx(const struct device *dev,
 					      struct dma_esp32_channel *rx, uint32_t intr_status)
 {
 	struct dma_esp32_data *data = (struct dma_esp32_data *const)(dev)->data;
-	uint32_t status;
 
 	gdma_ll_rx_clear_interrupt_status(data->hal.dev, rx->channel_id, intr_status);
+	if (rx->cb) {
+		int status;
 
-	if (intr_status == (GDMA_LL_EVENT_RX_SUC_EOF | GDMA_LL_EVENT_RX_DONE)) {
-		status = DMA_STATUS_COMPLETE;
-	} else if (intr_status == GDMA_LL_EVENT_RX_DONE) {
-		status = DMA_STATUS_BLOCK;
+		if (intr_status == (GDMA_LL_EVENT_RX_SUC_EOF | GDMA_LL_EVENT_RX_DONE)) {
+			status = DMA_STATUS_COMPLETE;
+		} else if (intr_status == GDMA_LL_EVENT_RX_DONE) {
+			status = DMA_STATUS_BLOCK;
 #if defined(CONFIG_SOC_SERIES_ESP32S3)
-	} else if (intr_status == GDMA_LL_EVENT_RX_WATER_MARK) {
-		status = DMA_STATUS_BLOCK;
+		} else if (intr_status == GDMA_LL_EVENT_RX_WATER_MARK) {
+			status = DMA_STATUS_BLOCK;
 #endif
-	} else {
-		status = -intr_status;
-	}
+		} else {
+			status = -intr_status;
+		}
 
-	if (rx->cb) {
 		rx->cb(dev, rx->user_data, rx->channel_id * 2, status);
 	}
 }
@@ -108,15 +98,15 @@ static void IRAM_ATTR dma_esp32_isr_handle_tx(const struct device *dev,
 	struct dma_esp32_data *data = (struct dma_esp32_data *const)(dev)->data;
 
 	gdma_ll_tx_clear_interrupt_status(data->hal.dev, tx->channel_id, intr_status);
-
-	intr_status &= ~(GDMA_LL_EVENT_TX_TOTAL_EOF | GDMA_LL_EVENT_TX_DONE | GDMA_LL_EVENT_TX_EOF);
-
 	if (tx->cb) {
+		intr_status &= ~(GDMA_LL_EVENT_TX_TOTAL_EOF | GDMA_LL_EVENT_TX_DONE |
+				 GDMA_LL_EVENT_TX_EOF);
+
 		tx->cb(dev, tx->user_data, tx->channel_id * 2 + 1, -intr_status);
 	}
 }
 
-#if !defined(CONFIG_SOC_SERIES_ESP32C6) && !defined(CONFIG_SOC_SERIES_ESP32S3)
+#if defined(SOC_GDMA_TX_RX_SHARE_INTERRUPT)
 static void IRAM_ATTR dma_esp32_isr_handle(const struct device *dev, uint8_t rx_id, uint8_t tx_id)
 {
 	struct dma_esp32_config *config = (struct dma_esp32_config *)dev->config;
@@ -137,46 +127,82 @@ static void IRAM_ATTR dma_esp32_isr_handle(const struct device *dev, uint8_t rx_
 }
 #endif
 
-static int dma_esp32_config_rx_descriptor(struct dma_esp32_channel *dma_channel,
-						struct dma_block_config *block)
+static int dma_esp32_config_descriptor(struct dma_esp32_channel *dma_channel,
+					struct dma_block_config *block)
 {
 	if (!block) {
 		LOG_ERR("At least one dma block is required");
 		return -EINVAL;
 	}
 
-	if (!esp_ptr_dma_capable((uint32_t *)block->dest_address)
+	uint32_t target_address = 0, block_size = 0;
+	dma_descriptor_t *desc_iter = dma_channel->desc_list;
+
+	for (int i = 0; i < CONFIG_DMA_ESP32_MAX_DESCRIPTOR_NUM; ++i) {
+		if (block_size == 0) {
+			if (dma_channel->dir == DMA_TX) {
+				target_address = block->source_address;
+			} else {
+				target_address = block->dest_address;
+			}
+
+			if (!esp_ptr_dma_capable((uint32_t *)target_address)
 #if defined(CONFIG_ESP_SPIRAM)
-	&& !esp_ptr_dma_ext_capable((uint32_t *)block->dest_address)
+			&& !esp_ptr_dma_ext_capable((uint32_t *)target_address)
 #endif
-	) {
-		LOG_ERR("Rx buffer not in DMA capable memory: %p", (uint32_t *)block->dest_address);
-		return -EINVAL;
-	}
+			) {
+				if (dma_channel->dir == DMA_TX) {
+					LOG_ERR("Tx buffer not in DMA capable memory: %p",
+						(uint32_t *)target_address);
+				} else {
+					LOG_ERR("Rx buffer not in DMA capable memory: %p",
+						(uint32_t *)target_address);
+				}
+
+				return -EINVAL;
+			}
 
-	dma_descriptor_t *desc_iter = dma_channel->desc_list;
+			block_size = block->block_size;
+		}
 
-	for (int i = 0; i < CONFIG_DMA_ESP32_MAX_DESCRIPTOR_NUM; ++i) {
-		if (block->block_size > DMA_DESCRIPTOR_BUFFER_MAX_SIZE) {
-			LOG_ERR("Size of block %d is too large", i);
-			return -EINVAL;
+		uint32_t buffer_size;
+
+		if (block_size > DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED) {
+			buffer_size = DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED;
+		} else {
+			buffer_size = block_size;
 		}
+
 		memset(desc_iter, 0, sizeof(dma_descriptor_t));
-		desc_iter->buffer = (void *)block->dest_address;
-		desc_iter->dw0.size = block->block_size;
+		desc_iter->buffer = (void *)target_address;
+		desc_iter->dw0.size = buffer_size;
+		if (dma_channel->dir == DMA_TX) {
+			desc_iter->dw0.length = buffer_size;
+		}
 		desc_iter->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
-		if (!block->next_block) {
-			desc_iter->next = NULL;
-			break;
+
+		target_address += buffer_size;
+		block_size -= buffer_size;
+
+		if (!block_size) {
+			if (block->next_block) {
+				block = block->next_block;
+			} else {
+				desc_iter->next = NULL;
+				if (dma_channel->dir == DMA_TX) {
+					desc_iter->dw0.suc_eof = 1;
+				}
+				break;
+			}
 		}
+
 		desc_iter->next = desc_iter + 1;
 		desc_iter += 1;
-		block = block->next_block;
 	}
 
 	if (desc_iter->next) {
 		memset(dma_channel->desc_list, 0, sizeof(dma_channel->desc_list));
-		LOG_ERR("Too many dma blocks. Increase CONFIG_DMA_ESP32_MAX_DESCRIPTOR_NUM");
+		LOG_ERR("Run out of DMA descriptors. Increase CONFIG_DMA_ESP32_MAX_DESCRIPTOR_NUM");
 		return -EINVAL;
 	}
 
@@ -213,60 +239,13 @@ static int dma_esp32_config_rx(const struct device *dev, struct dma_esp32_channe
 	dma_channel->cb = config_dma->dma_callback;
 	dma_channel->user_data = config_dma->user_data;
 
-	gdma_ll_rx_clear_interrupt_status(data->hal.dev, dma_channel->channel_id, UINT32_MAX);
-	gdma_ll_rx_enable_interrupt(data->hal.dev, dma_channel->channel_id, UINT32_MAX,
-				    config_dma->dma_callback != NULL);
+	gdma_ll_rx_enable_interrupt(data->hal.dev, dma_channel->channel_id, GDMA_LL_RX_EVENT_MASK,
+				    false);
 
-	return dma_esp32_config_rx_descriptor(dma_channel, config_dma->head_block);
-}
+	gdma_ll_rx_clear_interrupt_status(data->hal.dev, dma_channel->channel_id,
+					  GDMA_LL_RX_EVENT_MASK);
 
-static int dma_esp32_config_tx_descriptor(struct dma_esp32_channel *dma_channel,
-						struct dma_block_config *block)
-{
-	if (!block) {
-		LOG_ERR("At least one dma block is required");
-		return -EINVAL;
-	}
-
-	if (!esp_ptr_dma_capable((uint32_t *)block->source_address)
-#if defined(CONFIG_ESP_SPIRAM)
-	&& !esp_ptr_dma_ext_capable((uint32_t *)block->source_address)
-#endif
-	) {
-		LOG_ERR("Tx buffer not in DMA capable memory: %p",
-			(uint32_t *)block->source_address);
-		return -EINVAL;
-	}
-
-	dma_descriptor_t *desc_iter = dma_channel->desc_list;
-
-	for (int i = 0; i < CONFIG_DMA_ESP32_MAX_DESCRIPTOR_NUM; ++i) {
-		if (block->block_size > DMA_DESCRIPTOR_BUFFER_MAX_SIZE) {
-			LOG_ERR("Size of block %d is too large", i);
-			return -EINVAL;
-		}
-		memset(desc_iter, 0, sizeof(dma_descriptor_t));
-		desc_iter->buffer = (void *)block->source_address;
-		desc_iter->dw0.size = block->block_size;
-		desc_iter->dw0.length = block->block_size;
-		desc_iter->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
-		if (!block->next_block) {
-			desc_iter->next = NULL;
-			desc_iter->dw0.suc_eof = 1;
-			break;
-		}
-		desc_iter->next = desc_iter + 1;
-		desc_iter += 1;
-		block = block->next_block;
-	}
-
-	if (desc_iter->next) {
-		memset(dma_channel->desc_list, 0, sizeof(dma_channel->desc_list));
-		LOG_ERR("Too many dma blocks. Increase CONFIG_DMA_ESP32_MAX_DESCRIPTOR_NUM");
-		return -EINVAL;
-	}
-
-	return 0;
+	return dma_esp32_config_descriptor(dma_channel, config_dma->head_block);
 }
 
 static int dma_esp32_config_tx(const struct device *dev, struct dma_esp32_channel *dma_channel,
@@ -296,12 +275,13 @@ static int dma_esp32_config_tx(const struct device *dev, struct dma_esp32_channe
 	dma_channel->cb = config_dma->dma_callback;
 	dma_channel->user_data = config_dma->user_data;
 
-	gdma_ll_tx_clear_interrupt_status(data->hal.dev, dma_channel->channel_id, UINT32_MAX);
+	gdma_ll_tx_enable_interrupt(data->hal.dev, dma_channel->channel_id, GDMA_LL_TX_EVENT_MASK,
+				    false);
 
-	gdma_ll_tx_enable_interrupt(data->hal.dev, dma_channel->channel_id, GDMA_LL_EVENT_TX_EOF,
-				    config_dma->dma_callback != NULL);
+	gdma_ll_tx_clear_interrupt_status(data->hal.dev, dma_channel->channel_id,
+					  GDMA_LL_TX_EVENT_MASK);
 
-	return dma_esp32_config_tx_descriptor(dma_channel, config_dma->head_block);
+	return dma_esp32_config_descriptor(dma_channel, config_dma->head_block);
 }
 
 static int dma_esp32_config(const struct device *dev, uint32_t channel,
@@ -382,7 +362,7 @@ static int dma_esp32_start(const struct device *dev, uint32_t channel)
 			&config->dma_channel[(dma_channel->channel_id * 2) + 1];
 
 		gdma_ll_rx_enable_interrupt(data->hal.dev, dma_channel->channel_id,
-					UINT32_MAX, true);
+					GDMA_LL_EVENT_RX_SUC_EOF | GDMA_LL_EVENT_RX_DONE, true);
 		gdma_ll_tx_enable_interrupt(data->hal.dev, dma_channel->channel_id,
 					GDMA_LL_EVENT_TX_EOF, true);
 
@@ -396,13 +376,14 @@ static int dma_esp32_start(const struct device *dev, uint32_t channel)
 	} else {
 		if (dma_channel->dir == DMA_RX) {
 			gdma_ll_rx_enable_interrupt(data->hal.dev, dma_channel->channel_id,
-					UINT32_MAX, true);
+						    GDMA_LL_EVENT_RX_SUC_EOF |
+						    GDMA_LL_EVENT_RX_DONE, true);
 			gdma_ll_rx_set_desc_addr(data->hal.dev, dma_channel->channel_id,
 						 (int32_t)dma_channel->desc_list);
 			gdma_ll_rx_start(data->hal.dev, dma_channel->channel_id);
 		} else if (dma_channel->dir == DMA_TX) {
 			gdma_ll_tx_enable_interrupt(data->hal.dev, dma_channel->channel_id,
-					GDMA_LL_EVENT_TX_EOF, true);
+						    GDMA_LL_EVENT_TX_EOF, true);
 			gdma_ll_tx_set_desc_addr(data->hal.dev, dma_channel->channel_id,
 						 (int32_t)dma_channel->desc_list);
 			gdma_ll_tx_start(data->hal.dev, dma_channel->channel_id);
@@ -428,20 +409,20 @@ static int dma_esp32_stop(const struct device *dev, uint32_t channel)
 
 	if (dma_channel->periph_id == SOC_GDMA_TRIG_PERIPH_M2M0) {
 		gdma_ll_rx_enable_interrupt(data->hal.dev, dma_channel->channel_id,
-				UINT32_MAX, false);
+					    GDMA_LL_RX_EVENT_MASK, false);
 		gdma_ll_tx_enable_interrupt(data->hal.dev, dma_channel->channel_id,
-				GDMA_LL_EVENT_TX_EOF, false);
+					    GDMA_LL_TX_EVENT_MASK, false);
 		gdma_ll_rx_stop(data->hal.dev, dma_channel->channel_id);
 		gdma_ll_tx_stop(data->hal.dev, dma_channel->channel_id);
 	}
 
 	if (dma_channel->dir == DMA_RX) {
 		gdma_ll_rx_enable_interrupt(data->hal.dev, dma_channel->channel_id,
-				UINT32_MAX, false);
+					    GDMA_LL_RX_EVENT_MASK, false);
 		gdma_ll_rx_stop(data->hal.dev, dma_channel->channel_id);
 	} else if (dma_channel->dir == DMA_TX) {
 		gdma_ll_tx_enable_interrupt(data->hal.dev, dma_channel->channel_id,
-				GDMA_LL_EVENT_TX_EOF, false);
+					    GDMA_LL_TX_EVENT_MASK, false);
 		gdma_ll_tx_stop(data->hal.dev, dma_channel->channel_id);
 	}
 
@@ -517,9 +498,9 @@ static int dma_esp32_reload(const struct device *dev, uint32_t channel, uint32_t
 
 	for (int i = 0; i < ARRAY_SIZE(dma_channel->desc_list); ++i) {
 		memset(desc_iter, 0, sizeof(dma_descriptor_t));
-		desc_iter->buffer = (void *)(buf + DMA_DESCRIPTOR_BUFFER_MAX_SIZE * i);
+		desc_iter->buffer = (void *)(buf + DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED * i);
 		desc_iter->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
-		if (size < DMA_DESCRIPTOR_BUFFER_MAX_SIZE) {
+		if (size <= DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED) {
 			desc_iter->dw0.size = size;
 			if (dma_channel->dir == DMA_TX) {
 				desc_iter->dw0.length = size;
@@ -528,11 +509,11 @@ static int dma_esp32_reload(const struct device *dev, uint32_t channel, uint32_t
 			desc_iter->next = NULL;
 			break;
 		}
-		desc_iter->dw0.size = DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
+		desc_iter->dw0.size = DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED;
 		if (dma_channel->dir == DMA_TX) {
-			desc_iter->dw0.length = DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
+			desc_iter->dw0.length = DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED;
 		}
-		size -= DMA_DESCRIPTOR_BUFFER_MAX_SIZE;
+		size -= DMA_DESCRIPTOR_BUFFER_MAX_SIZE_4B_ALIGNED;
 		desc_iter->next = desc_iter + 1;
 		desc_iter += 1;
 	}
@@ -549,15 +530,35 @@ static int dma_esp32_reload(const struct device *dev, uint32_t channel, uint32_t
 static int dma_esp32_configure_irq(const struct device *dev)
 {
 	struct dma_esp32_config *config = (struct dma_esp32_config *)dev->config;
+	struct dma_esp32_data *data = (struct dma_esp32_data *)dev->data;
 	struct irq_config *irq_cfg = (struct irq_config *)config->irq_config;
+	volatile uint32_t *status_reg;
+	uint32_t status_mask;
 
 	for (uint8_t i = 0; i < config->irq_size; i++) {
-		int ret = esp_intr_alloc(irq_cfg[i].irq_source,
+#if defined(SOC_GDMA_TX_RX_SHARE_INTERRUPT)
+		status_reg = gdma_ll_rx_get_interrupt_status_reg(data->hal.dev, i);
+		status_mask = (GDMA_LL_RX_EVENT_MASK | GDMA_LL_TX_EVENT_MASK);
+#else
+		/* We assume device tree to feature RX/TX pairs */
+		if (i % 2) {
+			status_reg = gdma_ll_tx_get_interrupt_status_reg(data->hal.dev, i / 2);
+			status_mask = GDMA_LL_TX_EVENT_MASK;
+		} else {
+			status_reg = gdma_ll_rx_get_interrupt_status_reg(data->hal.dev, i / 2);
+			status_mask = GDMA_LL_RX_EVENT_MASK;
+		}
+#endif
+
+		int ret = esp_intr_alloc_intrstatus(irq_cfg[i].irq_source,
 			ESP_PRIO_TO_FLAGS(irq_cfg[i].irq_priority) |
 				ESP_INT_FLAGS_CHECK(irq_cfg[i].irq_flags) | ESP_INTR_FLAG_IRAM,
-			(ISR_HANDLER)config->irq_handlers[i],
+			(uint32_t)status_reg,
+			status_mask,
+			(intr_handler_t)config->irq_handlers[i],
 			(void *)dev,
 			NULL);
+
 		if (ret != 0) {
 			LOG_ERR("Could not allocate interrupt handler");
 			return ret;
@@ -613,7 +614,16 @@ static DEVICE_API(dma, dma_esp32_api) = {
 	.reload = dma_esp32_reload,
 };
 
-#if defined(CONFIG_SOC_SERIES_ESP32C6) || defined(CONFIG_SOC_SERIES_ESP32S3)
+#if defined(SOC_GDMA_TX_RX_SHARE_INTERRUPT)
+
+#define DMA_ESP32_DEFINE_IRQ_HANDLER(channel)                                                      \
+	__attribute__((unused)) static void IRAM_ATTR dma_esp32_isr_##channel(                     \
+		const struct device *dev)                                                          \
+	{                                                                                          \
+		dma_esp32_isr_handle(dev, channel * 2, channel * 2 + 1);                           \
+	}
+
+#else
 
 #define DMA_ESP32_DEFINE_IRQ_HANDLER(channel)                                                      \
 	__attribute__((unused)) static void IRAM_ATTR dma_esp32_isr_##channel##_rx(                \
@@ -640,21 +650,12 @@ static DEVICE_API(dma, dma_esp32_api) = {
 		}                                                                                  \
 	}
 
-#else
-
-#define DMA_ESP32_DEFINE_IRQ_HANDLER(channel)                                                      \
-	__attribute__((unused)) static void IRAM_ATTR dma_esp32_isr_##channel(                     \
-		const struct device *dev)                                                          \
-	{                                                                                          \
-		dma_esp32_isr_handle(dev, channel * 2, channel * 2 + 1);                           \
-	}
-
 #endif
 
-#if defined(CONFIG_SOC_SERIES_ESP32C6) || defined(CONFIG_SOC_SERIES_ESP32S3)
-#define ESP32_DMA_HANDLER(channel) dma_esp32_isr_##channel##_rx, dma_esp32_isr_##channel##_tx
-#else
+#if defined(SOC_GDMA_TX_RX_SHARE_INTERRUPT)
 #define ESP32_DMA_HANDLER(channel) dma_esp32_isr_##channel
+#else
+#define ESP32_DMA_HANDLER(channel) dma_esp32_isr_##channel##_rx, dma_esp32_isr_##channel##_tx
 #endif
 
 DMA_ESP32_DEFINE_IRQ_HANDLER(0)
@@ -702,6 +703,6 @@ static void *irq_handlers[] = {
 	};                                                                                         \
 												   \
 	DEVICE_DT_INST_DEFINE(idx, &dma_esp32_init, NULL, &dma_data_##idx, &dma_config_##idx,      \
-			      PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY, &dma_esp32_api);
+			      PRE_KERNEL_2, CONFIG_DMA_INIT_PRIORITY, &dma_esp32_api);
 
 DT_INST_FOREACH_STATUS_OKAY(DMA_ESP32_INIT)
diff --git a/drivers/dma/dma_ifx_cat1.c b/drivers/dma/dma_ifx_cat1.c
new file mode 100644
index 00000000000..0c1aaf89ef6
--- /dev/null
+++ b/drivers/dma/dma_ifx_cat1.c
@@ -0,0 +1,749 @@
+/*
+ * Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief DMA driver for Infineon CAT1 MCU family.
+ */
+
+#define DT_DRV_COMPAT infineon_cat1_dma
+
+#include <zephyr/device.h>
+#include <soc.h>
+#include <zephyr/drivers/dma.h>
+#include <zephyr/drivers/gpio.h>
+
+#include <zephyr/logging/log.h>
+#include <zephyr/irq.h>
+
+#include <cy_pdl.h>
+#include <cyhal_dma_dw.h>
+
+#if CYHAL_DRIVER_AVAILABLE_SYSPM && CONFIG_PM
+#include "cyhal_syspm_impl.h"
+#endif
+
+#include <zephyr/devicetree.h>
+LOG_MODULE_REGISTER(ifx_cat1_dma, CONFIG_DMA_LOG_LEVEL);
+
+#define CH_NUM               32
+#define DESCRIPTOR_POOL_SIZE CH_NUM + 5 /* TODO: add parameter to Kconfig */
+#define DMA_LOOP_X_COUNT_MAX CY_DMA_LOOP_COUNT_MAX
+#define DMA_LOOP_Y_COUNT_MAX CY_DMA_LOOP_COUNT_MAX
+
+#if CONFIG_SOC_FAMILY_INFINEON_CAT1B
+/* For CAT1B we must use SBUS instead CBUS when operate with
+ * flash area, so convert address from CBUS to SBUS
+ */
+#define IFX_CAT1B_FLASH_SBUS_ADDR (0x60000000)
+#define IFX_CAT1B_FLASH_CBUS_ADDR (0x8000000)
+#define IFX_CAT1_DMA_SRC_ADDR(v)                                                                   \
+	(void *)(((uint32_t)v & IFX_CAT1B_FLASH_CBUS_ADDR)                                         \
+			 ? (IFX_CAT1B_FLASH_SBUS_ADDR + ((uint32_t)v - IFX_CAT1B_FLASH_CBUS_ADDR)) \
+			 : (uint32_t)v)
+#else
+#define IFX_CAT1_DMA_SRC_ADDR(v) ((void *)v)
+#endif
+
+struct ifx_cat1_dma_channel {
+	uint32_t channel_direction: 3;
+	uint32_t error_callback_dis: 1;
+
+	cy_stc_dma_descriptor_t *descr;
+	IRQn_Type irq;
+
+	/* store config data from dma_config structure */
+	dma_callback_t callback;
+	void *user_data;
+};
+
+struct ifx_cat1_dma_data {
+	struct dma_context ctx;
+	struct ifx_cat1_dma_channel *channels;
+
+#if CYHAL_DRIVER_AVAILABLE_SYSPM && CONFIG_PM
+	cyhal_syspm_callback_data_t syspm_callback_args;
+#endif
+};
+
+struct ifx_cat1_dma_config {
+	uint8_t num_channels;
+	DW_Type *regs;
+	void (*irq_configure)(void);
+};
+
+/* Descriptors pool */
+K_MEM_SLAB_DEFINE_STATIC(ifx_cat1_dma_descriptors_pool_slab, sizeof(cy_stc_dma_descriptor_t),
+			 DESCRIPTOR_POOL_SIZE, 4);
+
+static int32_t _get_hw_block_num(DW_Type *reg_addr)
+{
+#if (CPUSS_DW0_PRESENT == 1)
+	if ((uint32_t)reg_addr == DW0_BASE) {
+		return 0;
+	}
+#endif
+
+#if (CPUSS_DW1_PRESENT == 1)
+	if ((uint32_t)reg_addr == DW1_BASE) {
+		return 1;
+	}
+#endif
+	return 0;
+}
+
+static int _dma_alloc_descriptor(void **descr)
+{
+	int ret = k_mem_slab_alloc(&ifx_cat1_dma_descriptors_pool_slab, (void **)descr, K_NO_WAIT);
+
+	if (!ret) {
+		memset(*descr, 0, sizeof(cy_stc_dma_descriptor_t));
+	}
+
+	return ret;
+}
+
+void _dma_free_descriptor(cy_stc_dma_descriptor_t *descr)
+{
+	k_mem_slab_free(&ifx_cat1_dma_descriptors_pool_slab, descr);
+}
+
+void _dma_free_linked_descriptors(cy_stc_dma_descriptor_t *descr)
+{
+	if (descr == NULL) {
+		return;
+	}
+	cy_stc_dma_descriptor_t *descr_to_remove = descr;
+	cy_stc_dma_descriptor_t *descr_to_remove_next = NULL;
+
+	do {
+		descr_to_remove_next = (cy_stc_dma_descriptor_t *)descr_to_remove->nextPtr;
+		_dma_free_descriptor(descr_to_remove);
+		descr_to_remove = descr_to_remove_next;
+
+	} while (descr_to_remove);
+}
+
+int ifx_cat1_dma_ex_connect_digital(const struct device *dev, uint32_t channel,
+				    cyhal_source_t source, cyhal_dma_input_t input)
+{
+	const struct ifx_cat1_dma_config *const cfg = dev->config;
+
+	cyhal_dma_t dma_obj = {
+		.resource.type = CYHAL_RSC_DW,
+		.resource.block_num = _get_hw_block_num(cfg->regs),
+		.resource.channel_num = channel,
+	};
+
+	cy_rslt_t rslt = cyhal_dma_connect_digital(&dma_obj, source, input);
+
+	return rslt ? -EIO : 0;
+}
+
+int ifx_cat1_dma_ex_enable_output(const struct device *dev, uint32_t channel,
+				  cyhal_dma_output_t output, cyhal_source_t *source)
+{
+	const struct ifx_cat1_dma_config *const cfg = dev->config;
+
+	cyhal_dma_t dma_obj = {
+		.resource.type = CYHAL_RSC_DW,
+		.resource.block_num = _get_hw_block_num(cfg->regs),
+		.resource.channel_num = channel,
+	};
+
+	cy_rslt_t rslt = cyhal_dma_enable_output(&dma_obj, output, source);
+
+	return rslt ? -EIO : 0;
+}
+
+static cy_en_dma_data_size_t _convert_dma_data_size_z_to_pdl(struct dma_config *config)
+{
+	cy_en_dma_data_size_t pdl_dma_data_size = CY_DMA_BYTE;
+
+	switch (config->source_data_size) {
+	case 1:
+		/* One byte */
+		pdl_dma_data_size = CY_DMA_BYTE;
+		break;
+	case 2:
+		/* Half word (two bytes) */
+		pdl_dma_data_size = CY_DMA_HALFWORD;
+		break;
+	case 4:
+		/* Full word (four bytes) */
+		pdl_dma_data_size = CY_DMA_WORD;
+		break;
+	}
+	return pdl_dma_data_size;
+}
+
+static int _convert_dma_xy_increment_z_to_pdl(uint32_t addr_adj)
+{
+	switch (addr_adj) {
+	case DMA_ADDR_ADJ_INCREMENT:
+		return 1;
+
+	case DMA_ADDR_ADJ_DECREMENT:
+		return -1;
+
+	case DMA_ADDR_ADJ_NO_CHANGE:
+		return 0;
+
+	default:
+		return 0;
+	}
+}
+
+static int _initialize_descriptor(cy_stc_dma_descriptor_t *descriptor, struct dma_config *config,
+				  struct dma_block_config *block_config, uint32_t block_num,
+				  uint32_t bytes, uint32_t offset)
+{
+	cy_en_dma_status_t dma_status;
+	cy_stc_dma_descriptor_config_t descriptor_config = {0u};
+
+	/* Retrigger descriptor immediately */
+	descriptor_config.retrigger = CY_DMA_RETRIG_IM;
+
+	/* Setup Interrupt Type */
+	descriptor_config.interruptType = CY_DMA_DESCR_CHAIN;
+
+	if (((offset + bytes) == block_config->block_size) &&
+	    (block_num + 1 == config->block_count)) {
+		descriptor_config.channelState = CY_DMA_CHANNEL_DISABLED;
+	} else {
+		descriptor_config.channelState = CY_DMA_CHANNEL_ENABLED;
+	}
+
+	/* TODO: should be able to configure triggerInType/triggerOutType */
+	descriptor_config.triggerOutType = CY_DMA_1ELEMENT;
+
+	if (config->channel_direction == MEMORY_TO_MEMORY) {
+		descriptor_config.triggerInType = CY_DMA_DESCR_CHAIN;
+	} else {
+		descriptor_config.triggerInType = CY_DMA_1ELEMENT;
+	}
+
+	/* Set data size byte / 2 bytes / word */
+	descriptor_config.dataSize = _convert_dma_data_size_z_to_pdl(config);
+
+	/* By default, transfer what the user set for dataSize. However, if transferring between
+	 * memory and a peripheral, make sure the peripheral access is using words.
+	 */
+	descriptor_config.srcTransferSize = CY_DMA_TRANSFER_SIZE_DATA;
+	descriptor_config.dstTransferSize = CY_DMA_TRANSFER_SIZE_DATA;
+
+	if (config->channel_direction == PERIPHERAL_TO_MEMORY) {
+		descriptor_config.srcTransferSize = CY_DMA_TRANSFER_SIZE_WORD;
+	} else if (config->channel_direction == MEMORY_TO_PERIPHERAL) {
+		descriptor_config.dstTransferSize = CY_DMA_TRANSFER_SIZE_WORD;
+	}
+
+	/* Setup destination increment for X source loop */
+	descriptor_config.srcXincrement =
+		_convert_dma_xy_increment_z_to_pdl(block_config->source_addr_adj);
+
+	/* Setup destination increment for X destination loop */
+	descriptor_config.dstXincrement =
+		_convert_dma_xy_increment_z_to_pdl(block_config->dest_addr_adj);
+
+	/* Setup 1D/2D descriptor for each data block */
+	if (bytes >= DMA_LOOP_X_COUNT_MAX) {
+		descriptor_config.descriptorType = CY_DMA_2D_TRANSFER;
+		descriptor_config.xCount = DMA_LOOP_X_COUNT_MAX;
+		descriptor_config.yCount = DIV_ROUND_UP(bytes, DMA_LOOP_X_COUNT_MAX);
+		descriptor_config.srcYincrement =
+			descriptor_config.srcXincrement * DMA_LOOP_X_COUNT_MAX;
+		descriptor_config.dstYincrement =
+			descriptor_config.dstXincrement * DMA_LOOP_X_COUNT_MAX;
+	} else {
+		descriptor_config.descriptorType = CY_DMA_1D_TRANSFER;
+		descriptor_config.xCount = bytes;
+		descriptor_config.yCount = 1;
+		descriptor_config.srcYincrement = 0;
+		descriptor_config.dstYincrement = 0;
+	}
+
+	/* Set source and destination for descriptor */
+	descriptor_config.srcAddress = IFX_CAT1_DMA_SRC_ADDR(
+		(block_config->source_address + (descriptor_config.srcXincrement ? offset : 0)));
+	descriptor_config.dstAddress = (void *)(block_config->dest_address +
+						(descriptor_config.dstXincrement ? offset : 0));
+
+	/* initialize descriptor */
+	dma_status = Cy_DMA_Descriptor_Init(descriptor, &descriptor_config);
+	if (dma_status != CY_DMA_SUCCESS) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/* Configure a channel v2 */
+static int ifx_cat1_dma_configure(const struct device *dev, uint32_t channel,
+				  struct dma_config *config)
+{
+	bool use_dt_config = false;
+	cy_en_dma_status_t dma_status;
+	struct ifx_cat1_dma_data *data = dev->data;
+	const struct ifx_cat1_dma_config *const cfg = dev->config;
+
+	cy_stc_dma_channel_config_t channel_config = {0u};
+	cy_stc_dma_descriptor_t *descriptor = NULL;
+	cy_stc_dma_descriptor_t *prev_descriptor = NULL;
+
+	if (channel >= cfg->num_channels) {
+		LOG_ERR("Unsupported channel");
+		return -EINVAL;
+	}
+
+	/* Support only the same data width for source and dest */
+	if (config->dest_data_size != config->source_data_size) {
+		LOG_ERR("Source and dest data size differ.");
+		return -EINVAL;
+	}
+
+	if ((config->dest_data_size != 1) && (config->dest_data_size != 2) &&
+	    (config->dest_data_size != 4)) {
+		LOG_ERR("dest_data_size must be 1, 2, or 4 (%" PRIu32 ")", config->dest_data_size);
+		return -EINVAL;
+	}
+
+	if (config->complete_callback_en > 1) {
+		LOG_ERR("Callback on each block not implemented");
+		return -ENOTSUP;
+	}
+
+	data->channels[channel].callback = config->dma_callback;
+	data->channels[channel].user_data = config->user_data;
+	data->channels[channel].channel_direction = config->channel_direction;
+	data->channels[channel].error_callback_dis = config->error_callback_dis;
+
+	/* Remove all allocated linked descriptors */
+	_dma_free_linked_descriptors(data->channels[channel].descr);
+	data->channels[channel].descr = NULL;
+
+	/* Lock and page in the channel configuration */
+	uint32_t key = irq_lock();
+
+	struct dma_block_config *block_config = config->head_block;
+
+	for (uint32_t i = 0u; i < config->block_count; i++) {
+		uint32_t block_pending_bytes = block_config->block_size;
+		uint32_t offset = 0;
+
+		do {
+			/* Configure descriptors for one block */
+			uint32_t bytes;
+
+			/* allocate new descriptor */
+			if (_dma_alloc_descriptor((void **)&descriptor)) {
+				LOG_ERR("Can't allocate new descriptor");
+				return -EINVAL;
+			}
+
+			if (data->channels[channel].descr == NULL) {
+				/* Store first descriptor in data structure */
+				data->channels[channel].descr = descriptor;
+			}
+
+			/* Mendotary chain descriptors in scope of one pack */
+			if (prev_descriptor != NULL) {
+				Cy_DMA_Descriptor_SetNextDescriptor(prev_descriptor, descriptor);
+			}
+
+			/* Calculate bytes, block_pending_bytes for 1D/2D descriptor */
+			if (block_pending_bytes <= DMA_LOOP_X_COUNT_MAX) {
+				/* Calculate bytes for 1D descriptor */
+				bytes = block_pending_bytes;
+				block_pending_bytes = 0;
+			} else {
+				/* Calculate bytes for 2D descriptor */
+				if (block_pending_bytes >
+				    (DMA_LOOP_X_COUNT_MAX * DMA_LOOP_Y_COUNT_MAX)) {
+					bytes = DMA_LOOP_X_COUNT_MAX * DMA_LOOP_Y_COUNT_MAX;
+				} else {
+					bytes = DMA_LOOP_Y_COUNT_MAX *
+						(block_pending_bytes / DMA_LOOP_Y_COUNT_MAX);
+				}
+				block_pending_bytes -= bytes;
+			}
+
+			_initialize_descriptor(descriptor, config, block_config,
+					       /* block_num */ i, bytes, offset);
+			offset += bytes;
+			prev_descriptor = descriptor;
+
+		} while (block_pending_bytes > 0);
+
+		block_config = block_config->next_block;
+	}
+
+	/* Set a descriptor for the specified DMA channel */
+	channel_config.descriptor = data->channels[channel].descr;
+
+	/* Set a priority for the DMA channel */
+	if (use_dt_config == false) {
+		Cy_DMA_Channel_SetPriority(cfg->regs, channel, config->channel_priority);
+	}
+
+	/* Initialize channel */
+	dma_status = Cy_DMA_Channel_Init(cfg->regs, channel, &channel_config);
+	if (dma_status != CY_DMA_SUCCESS) {
+		return -EIO;
+	}
+
+	irq_unlock(key);
+	return 0;
+}
+
+DW_Type *ifx_cat1_dma_get_regs(const struct device *dev)
+{
+	const struct ifx_cat1_dma_config *const cfg = dev->config;
+
+	return cfg->regs;
+}
+
+static int ifx_cat1_dma_start(const struct device *dev, uint32_t channel)
+{
+	const struct ifx_cat1_dma_config *const cfg = dev->config;
+	struct ifx_cat1_dma_data *data = dev->data;
+
+	if (channel >= cfg->num_channels) {
+		LOG_ERR("Unsupported channel");
+		return -EINVAL;
+	}
+
+	/* Enable DMA interrupt source. */
+	Cy_DMA_Channel_SetInterruptMask(cfg->regs, channel, CY_DMA_INTR_MASK);
+
+	/* Enable the interrupt  */
+	irq_enable(data->channels[channel].irq);
+
+	/* Enable DMA channel */
+	Cy_DMA_Channel_Enable(cfg->regs, channel);
+	if ((data->channels[channel].channel_direction == MEMORY_TO_MEMORY) ||
+	    (data->channels[channel].channel_direction == MEMORY_TO_PERIPHERAL)) {
+		cyhal_dma_t dma_obj = {
+			.resource.type = CYHAL_RSC_DW,
+			.resource.block_num = _get_hw_block_num(cfg->regs),
+			.resource.channel_num = channel,
+		};
+		(void)cyhal_dma_start_transfer(&dma_obj);
+	}
+	return 0;
+}
+
+static int ifx_cat1_dma_stop(const struct device *dev, uint32_t channel)
+{
+	const struct ifx_cat1_dma_config *const cfg = dev->config;
+
+	if (channel >= cfg->num_channels) {
+		LOG_ERR("Unsupported channel");
+		return -EINVAL;
+	}
+
+	/* Disable DMA channel */
+	Cy_DMA_Channel_Disable(cfg->regs, channel);
+
+	return 0;
+}
+
+int ifx_cat1_dma_reload(const struct device *dev, uint32_t channel, uint32_t src, uint32_t dst,
+			size_t size)
+{
+	struct ifx_cat1_dma_data *data = dev->data;
+	const struct ifx_cat1_dma_config *const cfg = dev->config;
+	cy_stc_dma_descriptor_t *descriptor = data->channels[channel].descr;
+
+	if (channel >= cfg->num_channels) {
+		LOG_ERR("Unsupported channel");
+		return -EINVAL;
+	}
+
+	/* Disable Channel */
+	Cy_DMA_Channel_Disable(cfg->regs, channel);
+
+	/* Update source/destination address for the specified descriptor */
+	descriptor->src = (uint32_t)IFX_CAT1_DMA_SRC_ADDR(src);
+	descriptor->dst = dst;
+
+	/* Initialize channel */
+	Cy_DMA_Channel_Enable(cfg->regs, channel);
+
+	return 0;
+}
+
+uint32_t get_total_size(const struct device *dev, uint32_t channel)
+{
+	struct ifx_cat1_dma_data *data = dev->data;
+	uint32_t total_size = 0;
+	uint32_t x_size = 0;
+	uint32_t y_size = 0;
+	cy_stc_dma_descriptor_t *curr_descr = data->channels[channel].descr;
+
+	while (curr_descr != NULL) {
+		x_size = Cy_DMA_Descriptor_GetXloopDataCount(curr_descr);
+
+		if (CY_DMA_2D_TRANSFER == Cy_DMA_Descriptor_GetDescriptorType(curr_descr)) {
+			y_size = Cy_DMA_Descriptor_GetYloopDataCount(curr_descr);
+		} else {
+			y_size = 0;
+		}
+
+		total_size += y_size != 0 ? x_size * y_size : x_size;
+		curr_descr = Cy_DMA_Descriptor_GetNextDescriptor(curr_descr);
+	}
+
+	return total_size;
+}
+
+uint32_t get_transferred_size(const struct device *dev, uint32_t channel)
+{
+	struct ifx_cat1_dma_data *data = dev->data;
+	const struct ifx_cat1_dma_config *const cfg = dev->config;
+	uint32_t transferred_data_size = 0;
+	uint32_t x_size = 0;
+	uint32_t y_size = 0;
+
+	cy_stc_dma_descriptor_t *next_descr = data->channels[channel].descr;
+	cy_stc_dma_descriptor_t *curr_descr =
+		Cy_DMA_Channel_GetCurrentDescriptor(ifx_cat1_dma_get_regs(dev), channel);
+
+	/* Calculates all processed descriptors */
+	while ((next_descr != NULL) && (next_descr != curr_descr)) {
+		x_size = Cy_DMA_Descriptor_GetXloopDataCount(next_descr);
+		y_size = Cy_DMA_Descriptor_GetYloopDataCount(next_descr);
+		transferred_data_size += y_size != 0 ? x_size * y_size : x_size;
+		next_descr = Cy_DMA_Descriptor_GetNextDescriptor(next_descr);
+	}
+
+	/* Calculates current descriptors (in progress) */
+	transferred_data_size +=
+		_FLD2VAL(DW_CH_STRUCT_CH_IDX_X_IDX, DW_CH_IDX(cfg->regs, channel)) +
+		(_FLD2VAL(DW_CH_STRUCT_CH_IDX_Y_IDX, DW_CH_IDX(cfg->regs, channel)) *
+		 Cy_DMA_Descriptor_GetXloopDataCount(curr_descr));
+
+	return transferred_data_size;
+}
+
+static int ifx_cat1_dma_get_status(const struct device *dev, uint32_t channel,
+				   struct dma_status *stat)
+{
+	struct ifx_cat1_dma_data *data = dev->data;
+	const struct ifx_cat1_dma_config *const cfg = dev->config;
+	uint32_t pending_status = 0;
+
+	if (channel >= cfg->num_channels) {
+		LOG_ERR("Unsupported channel");
+		return -EINVAL;
+	}
+
+	if (stat != NULL) {
+		/* Check is current DMA channel busy or idle */
+#if CONFIG_SOC_FAMILY_INFINEON_CAT1A
+		pending_status = DW_CH_STATUS(cfg->regs, channel) &
+				 (1UL << DW_CH_STRUCT_V2_CH_STATUS_PENDING_Pos);
+#elif CONFIG_SOC_FAMILY_INFINEON_CAT1B
+		pending_status = DW_CH_STATUS(cfg->regs, channel) &
+				 (1UL << DW_CH_STRUCT_CH_STATUS_PENDING_Pos);
+#endif
+		/* busy status info */
+		stat->busy = pending_status ? true : false;
+
+		if (data->channels[channel].descr != NULL) {
+			uint32_t total_transfer_size = get_total_size(dev, channel);
+			uint32_t transferred_size = get_transferred_size(dev, channel);
+
+			stat->pending_length = total_transfer_size - transferred_size;
+		} else {
+			stat->pending_length = 0;
+		}
+
+		/* direction info */
+		stat->dir = data->channels[channel].channel_direction;
+	}
+
+	return 0;
+}
+
+#if CYHAL_DRIVER_AVAILABLE_SYSPM && CONFIG_PM
+
+static bool _cyhal_dma_dmac_pm_callback(cyhal_syspm_callback_state_t state,
+					cyhal_syspm_callback_mode_t mode, void *callback_arg)
+{
+	CY_UNUSED_PARAMETER(state);
+	bool block_transition = false;
+	struct ifx_cat1_dma_config *conf = (struct ifx_cat1_dma_config *)callback_arg;
+	uint8_t i;
+
+	switch (mode) {
+	case CYHAL_SYSPM_CHECK_READY:
+		for (i = 0u; i < conf->num_channels; i++) {
+#if CONFIG_SOC_FAMILY_INFINEON_CAT1A
+			block_transition |= DW_CH_STATUS(conf->regs, i) &
+					    (1UL << DW_CH_STRUCT_V2_CH_STATUS_PENDING_Pos);
+#elif CONFIG_SOC_FAMILY_INFINEON_CAT1B
+			block_transition |= DW_CH_STATUS(conf->regs, i) &
+					    (1UL << DW_CH_STRUCT_CH_STATUS_PENDING_Pos);
+#endif
+		}
+		break;
+	case CYHAL_SYSPM_CHECK_FAIL:
+	case CYHAL_SYSPM_AFTER_TRANSITION:
+		break;
+	default:
+		CY_ASSERT(false);
+		break;
+	}
+
+	return !block_transition;
+}
+#endif
+
+static int ifx_cat1_dma_init(const struct device *dev)
+{
+	const struct ifx_cat1_dma_config *const cfg = dev->config;
+
+#if CYHAL_DRIVER_AVAILABLE_SYSPM && CONFIG_PM
+	struct ifx_cat1_dma_data *data = dev->data;
+
+	_cyhal_syspm_register_peripheral_callback(&data->syspm_callback_args);
+#endif
+
+	/* Enable DMA block to start descriptor execution process */
+	Cy_DMA_Enable(cfg->regs);
+
+	/* Configure IRQ */
+	cfg->irq_configure();
+
+	return 0;
+}
+
+/* Handles DMA interrupts and dispatches to the individual channel */
+struct ifx_cat1_dma_irq_context {
+	const struct device *dev;
+	uint32_t channel;
+};
+
+static void ifx_cat1_dma_isr(struct ifx_cat1_dma_irq_context *irq_context)
+{
+	uint32_t channel = irq_context->channel;
+	struct ifx_cat1_dma_data *data = irq_context->dev->data;
+	const struct ifx_cat1_dma_config *cfg = irq_context->dev->config;
+	dma_callback_t callback = data->channels[channel].callback;
+	int status;
+
+	/* Remove all allocated linked descriptors */
+	_dma_free_linked_descriptors(data->channels[channel].descr);
+	data->channels[channel].descr = NULL;
+
+	uint32_t intr_status = Cy_DMA_Channel_GetStatus(cfg->regs, channel);
+
+	/* Clear all interrupts */
+	Cy_DMA_Channel_ClearInterrupt(cfg->regs, channel);
+
+	/* Get interrupt type and call users event callback if they have enabled that event */
+	switch (intr_status) {
+	case CY_DMA_INTR_CAUSE_COMPLETION:
+		status = 0;
+		break;
+	case CY_DMA_INTR_CAUSE_DESCR_BUS_ERROR: /* Descriptor bus error */
+	case CY_DMA_INTR_CAUSE_SRC_BUS_ERROR:   /* Source bus error */
+	case CY_DMA_INTR_CAUSE_DST_BUS_ERROR:   /* Destination bus error */
+		status = -EPERM;
+		break;
+	case CY_DMA_INTR_CAUSE_SRC_MISAL: /* Source address is not aligned */
+	case CY_DMA_INTR_CAUSE_DST_MISAL: /* Destination address is not aligned */
+		status = -EPERM;
+		break;
+	case CY_DMA_INTR_CAUSE_CURR_PTR_NULL:      /* Current descr pointer is NULL */
+	case CY_DMA_INTR_CAUSE_ACTIVE_CH_DISABLED: /* Active channel is disabled */
+	default:
+		status = -EIO;
+		break;
+	}
+
+	if ((callback != NULL && status == 0) ||
+	    (callback != NULL && data->channels[channel].error_callback_dis)) {
+		void *callback_arg = data->channels[channel].user_data;
+
+		callback(irq_context->dev, callback_arg, channel, status);
+	}
+}
+
+static DEVICE_API(dma, ifx_cat1_dma_api) = {
+	.config = ifx_cat1_dma_configure,
+	.start = ifx_cat1_dma_start,
+	.stop = ifx_cat1_dma_stop,
+	.reload = ifx_cat1_dma_reload,
+	.get_status = ifx_cat1_dma_get_status,
+};
+
+#define IRQ_CONFIGURE(n, inst)                                                                     \
+	static const struct ifx_cat1_dma_irq_context irq_context##inst##n = {                      \
+		.dev = DEVICE_DT_INST_GET(inst),                                                   \
+		.channel = n,                                                                      \
+	};                                                                                         \
+                                                                                                   \
+	IRQ_CONNECT(DT_INST_IRQ_BY_IDX(inst, n, irq), DT_INST_IRQ_BY_IDX(inst, n, priority),       \
+		    ifx_cat1_dma_isr, &irq_context##inst##n, 0);                                   \
+                                                                                                   \
+	ifx_cat1_dma_channels##inst[n].irq = DT_INST_IRQ_BY_IDX(inst, n, irq);
+
+#define CONFIGURE_ALL_IRQS(inst, n) LISTIFY(n, IRQ_CONFIGURE, (), inst)
+
+#if CYHAL_DRIVER_AVAILABLE_SYSPM && CONFIG_PM
+#define SYSPM_CALLBACK_ARGS(n)                                                                     \
+	.syspm_callback_args = {                                                                   \
+		.callback = &_cyhal_dma_dmac_pm_callback,                                          \
+		.states = (cyhal_syspm_callback_state_t)(CYHAL_SYSPM_CB_CPU_DEEPSLEEP |            \
+							 CYHAL_SYSPM_CB_CPU_DEEPSLEEP_RAM |        \
+							 CYHAL_SYSPM_CB_SYSTEM_HIBERNATE),         \
+		.next = NULL,                                                                      \
+		.args = (void *)&ifx_cat1_dma_config##n,                                           \
+		.ignore_modes =                                                                    \
+			(cyhal_syspm_callback_mode_t)(CYHAL_SYSPM_BEFORE_TRANSITION |              \
+						      CYHAL_SYSPM_AFTER_DS_WFI_TRANSITION)},
+#else
+#define SYSPM_CALLBACK_ARGS(n)
+#endif
+
+#define INFINEON_CAT1_DMA_INIT(n)                                                                  \
+                                                                                                   \
+	static void ifx_cat1_dma_irq_configure##n(void);                                           \
+                                                                                                   \
+                                                                                                   \
+	static struct ifx_cat1_dma_channel                                                         \
+		ifx_cat1_dma_channels##n[DT_INST_PROP(n, dma_channels)];                           \
+                                                                                                   \
+	static const struct ifx_cat1_dma_config ifx_cat1_dma_config##n = {                         \
+		.num_channels = DT_INST_PROP(n, dma_channels),                                     \
+		.regs = (DW_Type *)DT_INST_REG_ADDR(n),                                            \
+		.irq_configure = ifx_cat1_dma_irq_configure##n,                                    \
+	};                                                                                         \
+                                                                                                   \
+	ATOMIC_DEFINE(ifx_cat1_dma_##n, DT_INST_PROP(n, dma_channels));                            \
+	static __aligned(32) struct ifx_cat1_dma_data ifx_cat1_dma_data##n = {                     \
+		.ctx =                                                                             \
+			{                                                                          \
+				.magic = DMA_MAGIC,                                                \
+				.atomic = ifx_cat1_dma_##n,                                        \
+				.dma_channels = DT_INST_PROP(n, dma_channels),                     \
+			},                                                                         \
+		.channels = ifx_cat1_dma_channels##n,                                              \
+		SYSPM_CALLBACK_ARGS(n)};                                                           \
+                                                                                                   \
+	static void ifx_cat1_dma_irq_configure##n(void)                                            \
+	{                                                                                          \
+		extern struct ifx_cat1_dma_channel ifx_cat1_dma_channels##n[];                     \
+		CONFIGURE_ALL_IRQS(n, DT_NUM_IRQS(DT_DRV_INST(n)));                                \
+	}                                                                                          \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, &ifx_cat1_dma_init, NULL, &ifx_cat1_dma_data##n,                  \
+			      &ifx_cat1_dma_config##n, PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY,     \
+			      &ifx_cat1_dma_api);
+
+DT_INST_FOREACH_STATUS_OKAY(INFINEON_CAT1_DMA_INIT)
diff --git a/drivers/dma/dma_mcux_edma.c b/drivers/dma/dma_mcux_edma.c
index 5575cb2a73f..ab818cd18ec 100644
--- a/drivers/dma/dma_mcux_edma.c
+++ b/drivers/dma/dma_mcux_edma.c
@@ -277,6 +277,28 @@ static void dma_mcux_edma_error_irq_handler(const struct device *dev)
 }
 #endif
 
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(channels_shared_irq_mask)
+static void dma_mcux_edma_multi_channels_irq_handler(const struct device *dev, uint32_t idx,
+			uint32_t *buf, uint32_t mask_width)
+{
+	uint32_t *num = &buf[mask_width * idx];
+	uint32_t count = 0;
+
+	for (int _i = 0; _i < mask_width; _i++) {
+		uint32_t value = (*num);
+
+		while (value > 0) {
+			if ((value & 0x1) == 1) {
+				dma_mcux_edma_irq_handler(dev, count);
+			}
+			value = value >> 1;
+			count++;
+		}
+		num++;
+	}
+}
+#endif
+
 /* Configure a channel */
 static int dma_mcux_edma_configure(const struct device *dev, uint32_t channel,
 				   struct dma_config *config)
@@ -861,10 +883,22 @@ static int dma_mcux_edma_init(const struct device *dev)
 			    irq_enable(DT_INST_IRQ_BY_IDX(n, idx, irq));	\
 	}
 
+#define EDMA_CHANNELS_MASK(n) static uint32_t edma_channel_mask_##n[] =  \
+				DT_PROP(DT_DRV_INST(n), channels_shared_irq_mask);
+
+#define GET_EDMA_CHANNEL_SHARED_IRQ_MASK_WIDTH(n) \
+			(DT_INST_PROP(n, dma_channels) / 32)
+
+#define EDMA_CHANNELS_SHARED_REGISTER_IN_IRQ(dev, idx, n) \
+		dma_mcux_edma_multi_channels_irq_handler(dev, idx, edma_channel_mask_##n, \
+			GET_EDMA_CHANNEL_SHARED_IRQ_MASK_WIDTH(n));
+
 #define DMA_MCUX_EDMA_IRQ_DEFINE(idx, n)					\
 	static void dma_mcux_edma_##n##_irq_##idx(const struct device *dev)	\
 	{									\
-		dma_mcux_edma_irq_handler(dev, idx);				\
+		COND_CODE_1(DT_INST_NODE_HAS_PROP(n, channels_shared_irq_mask), \
+			(EDMA_CHANNELS_SHARED_REGISTER_IN_IRQ(dev, idx, n)),	\
+			(dma_mcux_edma_irq_handler(dev, idx);))	\
 										\
 		IF_ENABLED(UTIL_BOOL(DT_INST_PROP(n, irq_shared_offset)),	\
 			  (dma_mcux_edma_irq_handler(dev,			\
@@ -877,6 +911,8 @@ static int dma_mcux_edma_init(const struct device *dev)
 	IRQ_CONFIG(n, idx, dma_mcux_edma_##n##_irq_##idx)
 
 #define DMA_MCUX_EDMA_CONFIG_FUNC(n)						\
+	IF_ENABLED(DT_INST_NODE_HAS_PROP(n, channels_shared_irq_mask), \
+				(EDMA_CHANNELS_MASK(n))) \
 	LISTIFY(NUM_IRQS_WITHOUT_ERROR_IRQ(n), DMA_MCUX_EDMA_IRQ_DEFINE, (), n) \
 	static void dma_imx_config_func_##n(const struct device *dev)		\
 	{									\
diff --git a/drivers/dma/dma_mcux_lpc.c b/drivers/dma/dma_mcux_lpc.c
index fde97055284..c4d51d3926a 100644
--- a/drivers/dma/dma_mcux_lpc.c
+++ b/drivers/dma/dma_mcux_lpc.c
@@ -402,7 +402,7 @@ static int dma_mcux_lpc_configure(const struct device *dev, uint32_t channel,
 	switch (config->channel_direction) {
 	case MEMORY_TO_MEMORY:
 		is_periph = false;
-		if (block_config->source_gather_en) {
+		if (block_config->source_gather_en && (block_config->source_gather_interval != 0)) {
 			src_inc = block_config->source_gather_interval / width;
 			/* The current controller only supports incrementing the
 			 * source and destination up to 4 time transfer width
@@ -412,7 +412,7 @@ static int dma_mcux_lpc_configure(const struct device *dev, uint32_t channel,
 			}
 		}
 
-		if (block_config->dest_scatter_en) {
+		if (block_config->dest_scatter_en && (block_config->dest_scatter_interval != 0)) {
 			dst_inc = block_config->dest_scatter_interval / width;
 			/* The current controller only supports incrementing the
 			 * source and destination up to 4 time transfer width
diff --git a/drivers/dma/dma_mcux_smartdma.c b/drivers/dma/dma_mcux_smartdma.c
index af7fb600be9..edc1645c6ea 100644
--- a/drivers/dma/dma_mcux_smartdma.c
+++ b/drivers/dma/dma_mcux_smartdma.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2023 NXP
+ * Copyright 2023, 2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,7 +13,6 @@
 #include <soc.h>
 #include <fsl_smartdma.h>
 #include <fsl_inputmux.h>
-#include <fsl_power.h>
 
 #define DT_DRV_COMPAT nxp_smartdma
 
diff --git a/drivers/dma/dma_nxp_sdma.c b/drivers/dma/dma_nxp_sdma.c
index 380a9411c9e..ab45927247d 100644
--- a/drivers/dma/dma_nxp_sdma.c
+++ b/drivers/dma/dma_nxp_sdma.c
@@ -202,7 +202,9 @@ void dma_nxp_sdma_callback(sdma_handle_t *handle, void *userData, bool TransferD
 		break;
 	}
 
+	/* prepare next BD for transfer */
 	bd = &chan_data->bd_pool[bdIndex];
+	bd->count = xfer_size;
 	bd->status |= (uint8_t)kSDMA_BDStatusDone;
 
 	SDMA_StartChannelSoftware(dev_cfg->base, chan_data->index);
@@ -266,6 +268,7 @@ static void dma_nxp_sdma_setup_bd(const struct device *dev, uint32_t channel,
 static int dma_nxp_sdma_config(const struct device *dev, uint32_t channel,
 			       struct dma_config *config)
 {
+	const struct sdma_dev_cfg *dev_cfg = dev->config;
 	struct sdma_dev_data *dev_data = dev->data;
 	struct sdma_channel_data *chan_data;
 	struct dma_block_config *block_cfg;
@@ -293,6 +296,14 @@ static int dma_nxp_sdma_config(const struct device *dev, uint32_t channel,
 		return ret;
 	}
 
+	if (chan_data->peripheral == kSDMA_PeripheralMultiFifoPDM) {
+		unsigned int n_fifos = 4; /* TODO: make this configurable */
+
+		SDMA_SetMultiFifoConfig(&chan_data->transfer_cfg, n_fifos, 0);
+		SDMA_EnableSwDone(dev_cfg->base, &chan_data->transfer_cfg, 0,
+				  chan_data->peripheral);
+	}
+
 	dma_nxp_sdma_setup_bd(dev, channel, config);
 	ret = dma_nxp_sdma_init_stat(chan_data);
 	if (ret < 0) {
@@ -421,6 +432,7 @@ static bool sdma_channel_filter(const struct device *dev, int chan_id, void *par
 
 	dev_data->chan[chan_id].event_source = *((int *)param);
 	dev_data->chan[chan_id].index = chan_id;
+	dev_data->chan[chan_id].capacity = 0;
 
 	return true;
 }
diff --git a/drivers/dma/dma_renesas_rz.c b/drivers/dma/dma_renesas_rz.c
new file mode 100644
index 00000000000..258561ae95e
--- /dev/null
+++ b/drivers/dma/dma_renesas_rz.c
@@ -0,0 +1,639 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#define DT_DRV_COMPAT renesas_rz_dma
+
+#include <zephyr/drivers/dma.h>
+#include "r_dmac_b.h"
+#include <zephyr/logging/log.h>
+#include "dma_renesas_rz.h"
+LOG_MODULE_REGISTER(renesas_rz_dma);
+
+/* FSP DMAC handler should be called within DMA ISR */
+void dmac_b_int_isr(void);
+void dmac_b_err_isr(void);
+
+struct dmac_cb_ctx {
+	const struct device *dmac_dev;
+	uint32_t channel;
+};
+
+struct dma_channel_data {
+	transfer_ctrl_t *fsp_ctrl;
+	transfer_cfg_t fsp_cfg;
+
+	/* INTID associated with the channel */
+	int irq;
+	int irq_ipl;
+
+	/* DMA call back */
+	dma_callback_t user_cb;
+	void *user_data;
+	struct dmac_cb_ctx cb_ctx;
+
+	bool is_configured;
+	uint32_t direction;
+};
+
+struct dma_renesas_rz_config {
+	uint8_t unit;
+	uint8_t num_channels;
+	void (*irq_configure)(void);
+	const transfer_api_t *fsp_api;
+};
+
+struct dma_renesas_rz_data {
+	/* Dma context should be the first in data structure */
+	struct dma_context ctx;
+	struct dma_channel_data *channels;
+};
+
+static void dmac_rz_cb_handler(dmac_b_callback_args_t *args)
+{
+	struct dmac_cb_ctx *cb_ctx = (struct dmac_cb_ctx *)args->p_context;
+	uint32_t channel = cb_ctx->channel;
+	const struct device *dev = cb_ctx->dmac_dev;
+	struct dma_renesas_rz_data *data = dev->data;
+	dma_callback_t user_cb = data->channels[channel].user_cb;
+	void *user_data = data->channels[channel].user_data;
+
+	if (user_cb) {
+		user_cb(dev, user_data, channel, args->event);
+	}
+}
+
+static int dma_channel_common_checks(const struct device *dev, uint32_t channel)
+{
+	const struct dma_renesas_rz_config *config = dev->config;
+	struct dma_renesas_rz_data *data = dev->data;
+
+	if (channel >= config->num_channels) {
+		LOG_ERR("%d: Invalid DMA channel %d.", __LINE__, channel);
+		return -EINVAL;
+	}
+
+	if (!data->channels[channel].is_configured) {
+		LOG_ERR("%d: DMA channel %d should first be configured.", __LINE__, channel);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static inline int dma_channel_config_check_parameters(const struct device *dev,
+						      struct dma_config *cfg)
+{
+	if ((cfg == NULL) || (cfg->head_block == NULL)) {
+		LOG_ERR("%d: Missing configuration structure.", __LINE__);
+		return -EFAULT;
+	}
+
+	if (1 < cfg->block_count) {
+		LOG_ERR("%d: Link Mode is not supported, but only support 1 block per transfer",
+			__LINE__);
+		return -ENOTSUP;
+	}
+
+	if (cfg->source_chaining_en || cfg->dest_chaining_en) {
+		LOG_ERR("%d:Channel Chainning is not supported.", __LINE__);
+		return -ENOTSUP;
+	}
+
+	if (cfg->head_block->dest_scatter_count || cfg->head_block->source_gather_count ||
+	    cfg->head_block->source_gather_interval || cfg->head_block->dest_scatter_interval) {
+		LOG_ERR("%d: Scater and gather are not supported.", __LINE__);
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static int dma_channel_set_size(uint32_t size)
+{
+	int transfer_size;
+
+	switch (size) {
+	case 1:
+		transfer_size = TRANSFER_SIZE_1_BYTE;
+		break;
+	case 2:
+		transfer_size = TRANSFER_SIZE_2_BYTE;
+		break;
+	case 4:
+		transfer_size = TRANSFER_SIZE_4_BYTE;
+		break;
+	case 8:
+		transfer_size = TRANSFER_SIZE_8_BYTE;
+		break;
+	case 32:
+		transfer_size = TRANSFER_SIZE_32_BYTE;
+		break;
+	case 64:
+		transfer_size = TRANSFER_SIZE_64_BYTE;
+		break;
+	case 128:
+		transfer_size = TRANSFER_SIZE_128_BYTE;
+		break;
+	default:
+		LOG_ERR("%d: Unsupported data width.", __LINE__);
+		return -ENOTSUP;
+	}
+
+	return transfer_size;
+}
+
+static inline int dma_channel_config_save_parameters(const struct device *dev, uint32_t channel,
+						     struct dma_config *cfg)
+{
+	const struct dma_renesas_rz_config *config = dev->config;
+	struct dma_renesas_rz_data *data = dev->data;
+	transfer_info_t *p_info = data->channels[channel].fsp_cfg.p_info;
+	dmac_b_extended_cfg_t *p_extend =
+		(dmac_b_extended_cfg_t *)data->channels[channel].fsp_cfg.p_extend;
+
+	memset(p_info, 0, sizeof(*p_info));
+	memset(p_extend, 0, sizeof(*p_extend));
+
+	/* Save transfer properties required by FSP */
+	switch (cfg->head_block->dest_addr_adj) {
+	case DMA_ADDR_ADJ_NO_CHANGE:
+		p_info->dest_addr_mode = TRANSFER_ADDR_MODE_FIXED;
+		break;
+	case DMA_ADDR_ADJ_INCREMENT:
+		p_info->dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED;
+		break;
+	default:
+		LOG_ERR("%d, Unsupported destination address adjustemnt.", __LINE__);
+		return -ENOTSUP;
+	}
+
+	switch (cfg->head_block->source_addr_adj) {
+	case DMA_ADDR_ADJ_NO_CHANGE:
+		p_info->src_addr_mode = TRANSFER_ADDR_MODE_FIXED;
+		break;
+	case DMA_ADDR_ADJ_INCREMENT:
+		p_info->src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED;
+		break;
+	default:
+		LOG_ERR("%d, Unsupported source address adjustemnt.", __LINE__);
+		return -ENOTSUP;
+	}
+
+	/* Convert data size following FSP convention */
+	p_info->src_size = dma_channel_set_size(cfg->source_data_size);
+	p_info->dest_size = dma_channel_set_size(cfg->dest_data_size);
+
+	/* Save transfer properties required by FSP */
+	p_info->p_src = (void const *volatile)cfg->head_block->source_address;
+	p_info->p_dest = (void *volatile)cfg->head_block->dest_address;
+	p_info->length = cfg->head_block->block_size;
+
+	/*
+	 * Properties of next 1 registers are assigned default value following FSP because transfer
+	 * continuous is not supported.
+	 */
+	p_info->p_next1_src = NULL;
+	p_info->p_next1_dest = NULL;
+	p_info->next1_length = 1;
+	p_extend->continuous_setting = DMAC_B_CONTINUOUS_SETTING_TRANSFER_ONCE;
+
+	/* Save DMAC properties required by FSP */
+	p_extend->unit = config->unit;
+	p_extend->channel = channel;
+
+	/* Save INTID and priority */
+	p_extend->dmac_int_irq = data->channels[channel].irq;
+	p_extend->dmac_int_ipl = data->channels[channel].irq_ipl;
+
+	/* Save callback and data and use the generic handler. */
+	data->channels[channel].user_cb = cfg->dma_callback;
+	data->channels[channel].user_data = cfg->user_data;
+	data->channels[channel].cb_ctx.dmac_dev = dev;
+	data->channels[channel].cb_ctx.channel = channel;
+	p_extend->p_callback = dmac_rz_cb_handler;
+	p_extend->p_context = (void *)&data->channels[channel].cb_ctx;
+
+	/* Save default value following FSP version */
+	p_extend->ack_mode = DMAC_B_ACK_MODE_MASK_DACK_OUTPUT;
+	p_extend->external_detection_mode = DMAC_B_EXTERNAL_DETECTION_NO_DETECTION;
+	p_extend->internal_detection_mode = DMAC_B_INTERNAL_DETECTION_NO_DETECTION;
+
+	/* Save properties with respect to a specific case */
+	switch (cfg->channel_direction) {
+	case MEMORY_TO_MEMORY:
+		p_info->mode = TRANSFER_MODE_BLOCK;
+		p_extend->activation_request_source_select =
+			DMAC_B_REQUEST_DIRECTION_DESTINATION_MODULE;
+		p_extend->activation_source = DMAC_TRIGGER_EVENT_SOFTWARE_TRIGGER;
+		break;
+	case PERIPHERAL_TO_MEMORY:
+		p_info->mode = TRANSFER_MODE_NORMAL;
+		p_extend->activation_request_source_select =
+			DMAC_B_REQUEST_DIRECTION_DESTINATION_MODULE;
+		p_extend->activation_source = cfg->dma_slot;
+		break;
+	case MEMORY_TO_PERIPHERAL:
+		p_info->mode = TRANSFER_MODE_NORMAL;
+		p_extend->activation_request_source_select = DMAC_B_REQUEST_DIRECTION_SOURCE_MODULE;
+		p_extend->activation_source = cfg->dma_slot;
+		break;
+	default:
+		LOG_ERR("%d: Unsupported direction mode.", __LINE__);
+		return -ENOTSUP;
+	}
+
+	data->channels[channel].direction = cfg->channel_direction;
+
+	/*
+	 * Only support two priority modes, 0 is the highest priority with respect to FIXED
+	 * Priority, Round Robin otherwise.
+	 */
+	if (cfg->channel_priority == 0) {
+		p_extend->channel_scheduling = DMAC_B_CHANNEL_SCHEDULING_FIXED;
+	} else {
+		p_extend->channel_scheduling = DMAC_B_CHANNEL_SCHEDULING_ROUND_ROBIN;
+	}
+
+	if (1 < cfg->block_count) {
+		LOG_ERR("%d: Link Mode is not supported.", __LINE__);
+	} else {
+		p_extend->dmac_mode = DMAC_B_MODE_SELECT_REGISTER;
+	}
+
+	return 0;
+}
+
+static int dma_renesas_rz_get_status(const struct device *dev, uint32_t channel,
+				     struct dma_status *status)
+{
+	const struct dma_renesas_rz_config *config = dev->config;
+	struct dma_renesas_rz_data *data = dev->data;
+
+	int ret = dma_channel_common_checks(dev, channel);
+
+	if (ret) {
+		return ret;
+	}
+
+	transfer_info_t *p_info;
+
+	p_info = data->channels[channel].fsp_cfg.p_info;
+	transfer_properties_t properties;
+
+	ret = config->fsp_api->infoGet(data->channels[channel].fsp_ctrl, &properties);
+	if (FSP_SUCCESS != (fsp_err_t)ret) {
+		LOG_ERR("%d: Failed to get info dma channel %d info with status %d.", __LINE__,
+			channel, ret);
+		return -EIO;
+	}
+
+	memset(status, 0, sizeof(*status));
+
+	status->dir = data->channels[channel].direction;
+	status->pending_length = properties.transfer_length_remaining;
+	status->busy = status->pending_length ? true : false;
+	status->total_copied = p_info->length - properties.transfer_length_remaining;
+
+	return 0;
+}
+
+static int dma_renesas_rz_suspend(const struct device *dev, uint32_t channel)
+{
+	struct dma_renesas_rz_data *data = dev->data;
+
+	int ret = dma_channel_common_checks(dev, channel);
+
+	if (ret) {
+		return ret;
+	}
+
+	dmac_b_instance_ctrl_t *p_ctrl = (dmac_b_instance_ctrl_t *)data->channels[channel].fsp_ctrl;
+
+	uint8_t group = DMA_PRV_GROUP(channel);
+	uint8_t prv_channel = DMA_PRV_CHANNEL(channel);
+
+	/* Set transfer status is suspend */
+	p_ctrl->p_reg->GRP[group].CH[prv_channel].CHCTRL = R_DMAC_B0_GRP_CH_CHCTRL_SETSUS_Msk;
+
+	/* Check whether a transfer is suspended. */
+	FSP_HARDWARE_REGISTER_WAIT(p_ctrl->p_reg->GRP[group].CH[prv_channel].CHSTAT_b.SUS, 1);
+
+	return 0;
+}
+
+static int dma_renesas_rz_resume(const struct device *dev, uint32_t channel)
+{
+	struct dma_renesas_rz_data *data = dev->data;
+
+	int ret = dma_channel_common_checks(dev, channel);
+
+	if (ret) {
+		return ret;
+	}
+
+	dmac_b_instance_ctrl_t *p_ctrl = (dmac_b_instance_ctrl_t *)data->channels[channel].fsp_ctrl;
+
+	uint8_t group = DMA_PRV_GROUP(channel);
+	uint8_t prv_channel = DMA_PRV_CHANNEL(channel);
+
+	/* Check whether a transfer is suspended. */
+	if (0 == p_ctrl->p_reg->GRP[group].CH[prv_channel].CHSTAT_b.SUS) {
+		LOG_ERR("%d: DMA channel not suspend.", channel);
+		return -EINVAL;
+	}
+
+	/* Restore transfer status from suspend */
+	p_ctrl->p_reg->GRP[group].CH[prv_channel].CHCTRL |= R_DMAC_B0_GRP_CH_CHCTRL_CLRSUS_Msk;
+
+	return 0;
+}
+
+static int dma_renesas_rz_stop(const struct device *dev, uint32_t channel)
+{
+	const struct dma_renesas_rz_config *config = dev->config;
+	struct dma_renesas_rz_data *data = dev->data;
+
+	int ret = dma_channel_common_checks(dev, channel);
+
+	if (ret) {
+		return ret;
+	}
+
+	ret = config->fsp_api->disable(data->channels[channel].fsp_ctrl);
+
+	if (FSP_SUCCESS != (fsp_err_t)ret) {
+		LOG_ERR("%d: Failed to stop dma channel %d info with status %d.", __LINE__, channel,
+			ret);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int dma_renesas_rz_start(const struct device *dev, uint32_t channel)
+{
+	const struct dma_renesas_rz_config *config = dev->config;
+	struct dma_renesas_rz_data *data = dev->data;
+	dmac_b_extended_cfg_t const *p_extend;
+
+	int ret = dma_channel_common_checks(dev, channel);
+
+	if (ret) {
+		return ret;
+	}
+
+	p_extend = data->channels[channel].fsp_cfg.p_extend;
+
+	ret = config->fsp_api->enable(data->channels[channel].fsp_ctrl);
+
+	if (FSP_SUCCESS != (fsp_err_t)ret) {
+		LOG_ERR("%d: Failed to start %d dma channel with status %d.", __LINE__, channel,
+			ret);
+		return -EIO;
+	}
+
+	if (DMAC_TRIGGER_EVENT_SOFTWARE_TRIGGER == p_extend->activation_source) {
+		ret = config->fsp_api->softwareStart(data->channels[channel].fsp_ctrl,
+						     (transfer_start_mode_t)NULL);
+
+		if (FSP_SUCCESS != (fsp_err_t)ret) {
+			LOG_ERR("%d: Failed to trigger %d dma channel with status %d.", __LINE__,
+				channel, ret);
+			return -EIO;
+		}
+	}
+
+	return 0;
+}
+static int dma_renesas_rz_config(const struct device *dev, uint32_t channel,
+				 struct dma_config *dma_cfg)
+{
+	const struct dma_renesas_rz_config *config = dev->config;
+	struct dma_renesas_rz_data *data = dev->data;
+	struct dma_channel_data *channel_cfg;
+	int ret;
+
+	if (channel >= config->num_channels) {
+		LOG_ERR("%d: Invalid DMA channel %d.", __LINE__, channel);
+		return -EINVAL;
+	}
+
+	ret = dma_channel_config_check_parameters(dev, dma_cfg);
+
+	if (ret) {
+		return ret;
+	}
+
+	ret = dma_channel_config_save_parameters(dev, channel, dma_cfg);
+	if (ret) {
+		return ret;
+	}
+
+	channel_cfg = &data->channels[channel];
+
+	/* To avoid assertions we should first close the driver instance if already enabled
+	 */
+	if (data->channels[channel].is_configured) {
+		config->fsp_api->close(channel_cfg->fsp_ctrl);
+	}
+
+	ret = config->fsp_api->open(channel_cfg->fsp_ctrl, &channel_cfg->fsp_cfg);
+
+	if (FSP_SUCCESS != (fsp_err_t)ret) {
+		LOG_ERR("%d: Failed to configure %d dma channel with status %d.", __LINE__, channel,
+			ret);
+		return -EIO;
+	}
+	/* Mark that requested channel is configured successfully. */
+	data->channels[channel].is_configured = true;
+	return 0;
+}
+
+static int dma_renesas_rz_reload(const struct device *dev, uint32_t channel, uint32_t src,
+				 uint32_t dst, size_t size)
+{
+	const struct dma_renesas_rz_config *config = dev->config;
+	struct dma_renesas_rz_data *data = dev->data;
+
+	int ret = dma_channel_common_checks(dev, channel);
+
+	if (ret) {
+		return ret;
+	}
+
+	if (size == 0) {
+		LOG_ERR("%d: Size must to not equal to 0 %d.", __LINE__, size);
+		return -EINVAL;
+	}
+
+	transfer_info_t *p_info = data->channels[channel].fsp_cfg.p_info;
+
+	p_info->length = size;
+	p_info->p_src = (void const *volatile)src;
+	p_info->p_dest = (void *volatile)dst;
+
+	ret = config->fsp_api->reconfigure(data->channels[channel].fsp_ctrl, p_info);
+
+	if (FSP_SUCCESS != (fsp_err_t)ret) {
+		LOG_ERR("%d: Failed to reload %d dma channel with status %d.", __LINE__, channel,
+			ret);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int dma_renesas_rz_get_attribute(const struct device *dev, uint32_t type, uint32_t *val)
+{
+	if (val == NULL) {
+		LOG_ERR("%d: Invalid attribute context.", __LINE__);
+		return -EINVAL;
+	}
+
+	switch (type) {
+	case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
+	case DMA_ATTR_BUFFER_SIZE_ALIGNMENT:
+	case DMA_ATTR_COPY_ALIGNMENT:
+		return -ENOSYS;
+	case DMA_ATTR_MAX_BLOCK_COUNT:
+		/*
+		 * this is restricted to 1 because SG and Link Mode configurations are not
+		 * supported
+		 */
+		*val = 1;
+		break;
+	default:
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static bool dma_renesas_rz_channel_filter(const struct device *dev, int channel, void *filter_param)
+{
+	ARG_UNUSED(filter_param);
+
+	const struct dma_renesas_rz_config *config = dev->config;
+	struct dma_renesas_rz_data *data = dev->data;
+
+	if (channel >= config->num_channels) {
+		LOG_ERR("%d: Invalid DMA channel %d.", __LINE__, channel);
+		return -EINVAL;
+	}
+
+	irq_enable(data->channels[channel].irq);
+	/* All DMA channels support triggered by periodic sources so always return true */
+	return true;
+}
+
+static void dma_renesas_rz_channel_release(const struct device *dev, uint32_t channel)
+{
+	const struct dma_renesas_rz_config *config = dev->config;
+	struct dma_renesas_rz_data *data = dev->data;
+	fsp_err_t ret;
+
+	if (channel >= config->num_channels) {
+		LOG_ERR("%d: Invalid DMA channel %d.", __LINE__, channel);
+	}
+
+	irq_disable(data->channels[channel].irq);
+	ret = config->fsp_api->close(data->channels[channel].fsp_ctrl);
+
+	if (ret != FSP_SUCCESS) {
+		LOG_ERR("%d: Failed to release %d dma channel with status %d.", __LINE__, channel,
+			ret);
+	}
+}
+
+static DEVICE_API(dma, dma_api) = {
+	.reload = dma_renesas_rz_reload,
+	.config = dma_renesas_rz_config,
+	.start = dma_renesas_rz_start,
+	.stop = dma_renesas_rz_stop,
+	.suspend = dma_renesas_rz_suspend,
+	.resume = dma_renesas_rz_resume,
+	.get_status = dma_renesas_rz_get_status,
+	.get_attribute = dma_renesas_rz_get_attribute,
+	.chan_filter = dma_renesas_rz_channel_filter,
+	.chan_release = dma_renesas_rz_channel_release,
+};
+
+static int renesas_rz_dma_init(const struct device *dev)
+{
+	const struct dma_renesas_rz_config *config = dev->config;
+
+	config->irq_configure();
+
+	return 0;
+}
+
+static void dmac_err_isr(const void *arg)
+{
+	ARG_UNUSED(arg);
+
+	/* Call FSP DMAC ERR ISR */
+	dmac_b_err_isr();
+}
+
+static void dmac_irq_isr(const void *arg)
+{
+	ARG_UNUSED(arg);
+
+	/* Call FSP DMAC ISR */
+	dmac_b_int_isr();
+}
+
+#define IRQ_ERR_CONFIGURE(inst, name)                                                              \
+	IRQ_CONNECT(                                                                               \
+		DT_INST_IRQ_BY_NAME(inst, name, irq), DT_INST_IRQ_BY_NAME(inst, name, priority),   \
+		dmac_err_isr, DEVICE_DT_INST_GET(inst),                                            \
+		COND_CODE_1(DT_IRQ_HAS_CELL_AT_NAME(DT_DRV_INST(inst), name, flags),           \
+				(DT_INST_IRQ_BY_NAME(inst, name, flags)), (0)));  \
+	irq_enable(DT_INST_IRQ_BY_NAME(inst, name, irq));
+
+#define IRQ_CONFIGURE(n, inst)                                                                     \
+	IRQ_CONNECT(DT_INST_IRQ_BY_IDX(inst, n, irq), DT_INST_IRQ_BY_IDX(inst, n, priority),       \
+		    dmac_irq_isr, DEVICE_DT_INST_GET(inst),                                        \
+		    COND_CODE_1(DT_IRQ_HAS_CELL_AT_IDX(DT_DRV_INST(inst), n, flags),               \
+				(DT_INST_IRQ_BY_IDX(inst, n, flags)), (0)));
+
+#define CONFIGURE_ALL_IRQS(inst, n) LISTIFY(n, IRQ_CONFIGURE, (), inst)
+
+#define DMA_RZ_INIT(inst)                                                                          \
+	static void dma_rz_##inst##_irq_configure(void)                                            \
+	{                                                                                          \
+		CONFIGURE_ALL_IRQS(inst, DT_INST_PROP(inst, dma_channels));                        \
+		COND_CODE_1(DT_INST_IRQ_HAS_NAME(inst, err1),					\
+			    (IRQ_ERR_CONFIGURE(inst, err1)), ())                                \
+	}                                                                                          \
+                                                                                                   \
+	static const struct dma_renesas_rz_config dma_renesas_rz_config_##inst = {                 \
+		.unit = inst,                                                                      \
+		.num_channels = DT_INST_PROP(inst, dma_channels),                                  \
+		.irq_configure = dma_rz_##inst##_irq_configure,                                    \
+		.fsp_api = &g_transfer_on_dmac_b};                                                 \
+                                                                                                   \
+	static dmac_b_instance_ctrl_t g_transfer_ctrl[DT_INST_PROP(inst, dma_channels)];           \
+	static transfer_info_t g_transfer_info[DT_INST_PROP(inst, dma_channels)];                  \
+	static dmac_b_extended_cfg_t g_transfer_extend[DT_INST_PROP(inst, dma_channels)];          \
+	static struct dma_channel_data                                                             \
+		dma_rz_##inst##_channels[DT_INST_PROP(inst, dma_channels)] =                       \
+			DMA_CHANNEL_ARRAY(inst);                                                   \
+                                                                                                   \
+	ATOMIC_DEFINE(dma_rz_atomic##inst, DT_INST_PROP(inst, dma_channels));                      \
+                                                                                                   \
+	static struct dma_renesas_rz_data dma_renesas_rz_data_##inst = {                           \
+		.ctx =                                                                             \
+			{                                                                          \
+				.magic = DMA_MAGIC,                                                \
+				.atomic = dma_rz_atomic##inst,                                     \
+				.dma_channels = DT_INST_PROP(inst, dma_channels),                  \
+			},                                                                         \
+		.channels = dma_rz_##inst##_channels};                                             \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(inst, renesas_rz_dma_init, NULL, &dma_renesas_rz_data_##inst,        \
+			      &dma_renesas_rz_config_##inst, PRE_KERNEL_1,                         \
+			      CONFIG_DMA_INIT_PRIORITY, &dma_api);
+
+DT_INST_FOREACH_STATUS_OKAY(DMA_RZ_INIT);
diff --git a/drivers/dma/dma_renesas_rz.h b/drivers/dma/dma_renesas_rz.h
new file mode 100644
index 00000000000..30a9fee135f
--- /dev/null
+++ b/drivers/dma/dma_renesas_rz.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/device.h>
+
+/* used to store interrupt and priority for channels */
+#define DMA_CHANNEL_DECLARE(n, inst)                                                               \
+	{                                                                                          \
+		.fsp_ctrl = (transfer_ctrl_t *)&g_transfer_ctrl[n],                                \
+		.fsp_cfg =                                                                         \
+			{                                                                          \
+				.p_info = &g_transfer_info[n],                                     \
+				.p_extend = &g_transfer_extend[n],                                 \
+			},                                                                         \
+		.irq = DT_INST_IRQ_BY_IDX(inst, n, irq),                                           \
+		.irq_ipl = DT_INST_IRQ_BY_IDX(inst, n, priority),                                  \
+	}
+
+/* Generate an array of DMA channel data structures */
+#define DMA_CHANNEL_ARRAY(inst)                                                                    \
+	{LISTIFY(DT_INST_PROP(inst, dma_channels), DMA_CHANNEL_DECLARE, (,), inst) }
+
+#define DMA_PRV_CHANNEL(channel) (channel % 8)
+#define DMA_PRV_GROUP(channel)   (channel / 8)
diff --git a/drivers/dma/dma_sam0.c b/drivers/dma/dma_sam0.c
index e5535e438c0..359162290c0 100644
--- a/drivers/dma/dma_sam0.c
+++ b/drivers/dma/dma_sam0.c
@@ -415,7 +415,9 @@ static int dma_sam0_init(const struct device *dev)
 
 	/* Reset the DMA controller */
 	DMAC->CTRL.bit.DMAENABLE = 0;
+#ifdef DMAC_CTRL_CRCENABLE
 	DMAC->CTRL.bit.CRCENABLE = 0;
+#endif
 	DMAC->CTRL.bit.SWRST = 1;
 	while (DMAC->CTRL.bit.SWRST) {
 	}
diff --git a/drivers/dma/dma_sedi.c b/drivers/dma/dma_sedi.c
index d7093259b6c..14ee67af850 100644
--- a/drivers/dma/dma_sedi.c
+++ b/drivers/dma/dma_sedi.c
@@ -376,7 +376,7 @@ static int dma_sedi_init(const struct device *dev)
 		.chn_num = DT_INST_PROP(inst, dma_channels), \
 		.irq_config = dma_sedi_##inst##_irq_config \
 	}; \
-	DEVICE_DT_DEFINE(DT_INST(inst, DT_DRV_COMPAT), &dma_sedi_init, \
+	DEVICE_DT_INST_DEFINE(inst, &dma_sedi_init, \
 	      NULL, &dma_sedi_dev_data_##inst, &dma_sedi_config_data_##inst, PRE_KERNEL_2, \
 	      CONFIG_KERNEL_INIT_PRIORITY_DEVICE, (void *)&dma_funcs); \
 									\
diff --git a/drivers/dma/dma_silabs_ldma.c b/drivers/dma/dma_silabs_ldma.c
index 5baaac18b24..358b90b3f48 100644
--- a/drivers/dma/dma_silabs_ldma.c
+++ b/drivers/dma/dma_silabs_ldma.c
@@ -9,11 +9,13 @@
 
 #include <zephyr/device.h>
 #include <zephyr/drivers/dma.h>
+#include <zephyr/drivers/dma/dma_silabs_ldma.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/irq.h>
 #include <zephyr/sys/mem_blocks.h>
 
 #include "em_ldma.h"
+#include "dmadrv.h"
 
 #define DT_DRV_COMPAT silabs_ldma
 
@@ -104,7 +106,9 @@ static int dma_silabs_block_to_descriptor(struct dma_config *config,
 
 	memset(desc, 0, sizeof(*desc));
 
-	desc->xfer.structReq = 1;
+	if (config->channel_direction == MEMORY_TO_MEMORY) {
+		desc->xfer.structReq = 1;
+	}
 
 	if (config->source_data_size != config->dest_data_size) {
 		LOG_ERR("Source data size(%u) and destination data size(%u) must be equal",
@@ -146,8 +150,17 @@ static int dma_silabs_block_to_descriptor(struct dma_config *config,
 	 * in the list (block for zephyr)
 	 */
 	desc->xfer.doneIfs = config->complete_callback_en;
-	desc->xfer.reqMode = ldmaCtrlReqModeAll;
-	desc->xfer.ignoreSrec = block->flow_control_mode;
+
+	if (config->channel_direction == PERIPHERAL_TO_MEMORY ||
+	    config->channel_direction == MEMORY_TO_PERIPHERAL) {
+		if (block->flow_control_mode) {
+			desc->xfer.reqMode = ldmaCtrlReqModeAll;
+		} else {
+			desc->xfer.reqMode = ldmaCtrlReqModeBlock;
+		}
+	} else {
+		desc->xfer.reqMode = ldmaCtrlReqModeAll;
+	}
 
 	/* In silabs LDMA, increment sign is managed with the transfer configuration
 	 * which is common for all descs of the channel. Zephyr DMA API allows
@@ -257,10 +270,9 @@ static int dma_silabs_configure_descriptor(struct dma_config *config, struct dma
 	return 0;
 err:
 	/* Free all eventually allocated descriptor */
-	(void)dma_silabs_release_descriptor(data, chan_conf->desc);
+	dma_silabs_release_descriptor(data, chan_conf->desc);
 
 	return ret;
-
 }
 
 static void dma_silabs_irq_handler(const struct device *dev, uint32_t id)
@@ -292,6 +304,16 @@ static void dma_silabs_irq_handler(const struct device *dev, uint32_t id)
 				atomic_clear(&chan->busy);
 			}
 
+			/*
+			 * In the case that the transfer is done but we have append a new
+			 * descriptor, we need to manually load the next descriptor
+			 */
+			if (LDMA_TransferDone(chnum) &&
+			    LDMA->CH[chnum].LINK & _LDMA_CH_LINK_LINK_MASK) {
+				sys_clear_bit((mem_addr_t)&LDMA->CHDONE, chnum);
+				LDMA->LINKLOAD = BIT(chnum);
+			}
+
 			if (chan->cb) {
 				chan->cb(dev, chan->user_data, chnum, status);
 			}
@@ -350,7 +372,7 @@ static int dma_silabs_configure(const struct device *dev, uint32_t channel,
 		break;
 	case PERIPHERAL_TO_MEMORY:
 	case MEMORY_TO_PERIPHERAL:
-		xfer_config->ldmaReqSel = config->dma_slot;
+		xfer_config->ldmaReqSel = SILABS_LDMA_SLOT_TO_REQSEL(config->dma_slot);
 		break;
 	case PERIPHERAL_TO_PERIPHERAL:
 	case HOST_TO_MEMORY:
@@ -407,7 +429,6 @@ static int dma_silabs_configure(const struct device *dev, uint32_t channel,
 
 static int dma_silabs_start(const struct device *dev, uint32_t channel)
 {
-
 	const struct dma_silabs_data *data = dev->data;
 	struct dma_silabs_channel *chan = &data->dma_chan_table[channel];
 
@@ -453,24 +474,34 @@ static int dma_silabs_get_status(const struct device *dev, uint32_t channel,
 		return -EINVAL;
 	}
 
+	status->pending_length = LDMA_TransferRemainingCount(channel);
 	status->busy = data->dma_chan_table[channel].busy;
 	status->dir = data->dma_chan_table[channel].dir;
 
 	return 0;
 }
 
+bool dma_silabs_chan_filter(const struct device *dev, int channel, void *filter_param)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(filter_param);
+	return (DMADRV_AllocateChannelById(channel, 0) == ECODE_EMDRV_DMADRV_OK);
+}
+
+void dma_silabs_chan_release(const struct device *dev, uint32_t channel)
+{
+	ARG_UNUSED(dev);
+	Ecode_t __maybe_unused err = DMADRV_FreeChannel(channel);
+
+	__ASSERT_NO_MSG(err == ECODE_EMDRV_DMADRV_OK);
+}
+
 static int dma_silabs_init(const struct device *dev)
 {
 	const struct dma_silabs_config *config = dev->config;
-	LDMA_Init_t dmaInit = {
-		/*  0x7 indicate that the 8 channels have round robin priority. */
-		.ldmaInitCtrlNumFixed = 0x7,
-		.ldmaInitIrqPriority = DMA_IRQ_PRIORITY,
-	};
 
 	/* Clock is managed by em_ldma */
-
-	LDMA_Init(&dmaInit);
+	DMADRV_Init();
 
 	/* LDMA_Init configure IRQ but we want IRQ to match with configured one in the dts*/
 	config->config_irq(dev);
@@ -482,9 +513,69 @@ static DEVICE_API(dma, dma_funcs) = {
 	.config = dma_silabs_configure,
 	.start = dma_silabs_start,
 	.stop = dma_silabs_stop,
-	.get_status = dma_silabs_get_status
+	.get_status = dma_silabs_get_status,
+	.chan_filter = dma_silabs_chan_filter,
+	.chan_release = dma_silabs_chan_release
 };
 
+int silabs_ldma_append_block(const struct device *dev, uint32_t channel, struct dma_config *config)
+{
+	const struct dma_silabs_data *data = dev->data;
+	struct dma_silabs_channel *chan_conf = &data->dma_chan_table[channel];
+	struct dma_block_config *block_config = config->head_block;
+	LDMA_Descriptor_t *desc = data->dma_chan_table[channel].desc;
+	unsigned int key;
+	int ret;
+
+	__ASSERT(!((uintptr_t)desc & ~_LDMA_CH_LINK_LINKADDR_MASK),
+		 "DMA Descriptor is not 32 bits aligned");
+
+	if (channel > data->dma_ctx.dma_channels) {
+		return -EINVAL;
+	}
+
+	if (!atomic_test_bit(data->dma_ctx.atomic, channel)) {
+		return -EINVAL;
+	}
+
+	/* DMA Channel already have loaded a descriptor with a linkaddr
+	 * so we can't append a new block just after the current transfer.
+	 * You can't also append a descriptor list.
+	 * This check is here to not use the function in a wrong way
+	 */
+	if (desc->xfer.linkAddr || config->head_block->next_block) {
+		return -EINVAL;
+	}
+
+	/* A link is already set by a previous call to the function */
+	if (sys_test_bit((mem_addr_t)&LDMA->CH[channel].LINK, _LDMA_CH_LINK_LINK_SHIFT)) {
+		return -EINVAL;
+	}
+
+	ret = dma_silabs_block_to_descriptor(config, chan_conf, block_config, desc);
+	if (ret) {
+		return ret;
+	}
+
+	key = irq_lock();
+	if (!LDMA_TransferDone(channel)) {
+		/*
+		 * It is voluntary to split this 2 lines in order to separate the write of the link
+		 * addr and the write of the link bit. In this way, there is always a linkAddr when
+		 * the link bit is set.
+		 */
+		sys_write32((uintptr_t)desc, (mem_addr_t)&LDMA->CH[channel].LINK);
+		sys_set_bit((mem_addr_t)&LDMA->CH[channel].LINK, _LDMA_CH_LINK_LINK_SHIFT);
+		irq_unlock(key);
+
+	} else {
+		irq_unlock(key);
+		LDMA_StartTransfer(channel, &chan_conf->xfer_config, desc);
+	}
+
+	return 0;
+}
+
 #define SILABS_DMA_IRQ_CONNECT(n, inst)                                                            \
 	IRQ_CONNECT(DT_INST_IRQ_BY_IDX(inst, n, irq), DT_INST_IRQ_BY_IDX(inst, n, priority),       \
 		    dma_silabs_irq_handler, DEVICE_DT_INST_GET(inst), 0);                          \
diff --git a/drivers/dma/dma_silabs_siwx91x.c b/drivers/dma/dma_silabs_siwx91x.c
new file mode 100644
index 00000000000..5796f335600
--- /dev/null
+++ b/drivers/dma/dma_silabs_siwx91x.c
@@ -0,0 +1,705 @@
+/*
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <zephyr/irq.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/sys_io.h>
+#include <zephyr/sys/mem_blocks.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/dma.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/types.h>
+#include "rsi_rom_udma.h"
+#include "rsi_rom_udma_wrapper.h"
+#include "rsi_udma.h"
+#include "sl_status.h"
+
+#define DT_DRV_COMPAT                    silabs_siwx91x_dma
+#define DMA_MAX_TRANSFER_COUNT           1024
+#define DMA_CH_PRIORITY_HIGH             1
+#define DMA_CH_PRIORITY_LOW              0
+#define UDMA_ADDR_INC_NONE               0x03
+#define UDMA_MODE_PER_ALT_SCATTER_GATHER 0x07
+
+LOG_MODULE_REGISTER(si91x_dma, CONFIG_DMA_LOG_LEVEL);
+
+enum dma_xfer_dir {
+	TRANSFER_MEM_TO_MEM,
+	TRANSFER_TO_OR_FROM_PER,
+	TRANSFER_DIR_INVALID = -1,
+};
+
+struct dma_siwx91x_channel_info {
+	dma_callback_t dma_callback;        /* User callback */
+	void *cb_data;                      /* User callback data */
+	RSI_UDMA_DESC_T *sg_desc_addr_info; /* Scatter-Gather table start address */
+	enum dma_xfer_dir xfer_direction;   /* mem<->mem ot per<->mem */
+};
+
+struct dma_siwx91x_config {
+	UDMA0_Type *reg;                 /* UDMA register base address */
+	uint8_t irq_number;              /* IRQ number */
+	RSI_UDMA_DESC_T *sram_desc_addr; /* SRAM Address for UDMA Descriptor Storage */
+	const struct device *clock_dev;
+	clock_control_subsys_t clock_subsys;
+	void (*irq_configure)(void);     /* IRQ configure function */
+};
+
+struct dma_siwx91x_data {
+	struct dma_context dma_ctx;
+	UDMA_Channel_Info *chan_info;
+	struct dma_siwx91x_channel_info *zephyr_channel_info;
+	struct sys_mem_blocks *dma_desc_pool; /* Pointer to the memory pool for DMA descriptor */
+	RSI_UDMA_DATACONTEXT_T udma_handle;  /* Buffer to store UDMA handle
+					      * related information
+					      */
+};
+
+static enum dma_xfer_dir siwx91x_transfer_direction(uint32_t dir)
+{
+	if (dir == MEMORY_TO_MEMORY) {
+		return TRANSFER_MEM_TO_MEM;
+	}
+
+	if (dir == MEMORY_TO_PERIPHERAL || dir == PERIPHERAL_TO_MEMORY) {
+		return TRANSFER_TO_OR_FROM_PER;
+	}
+
+	return TRANSFER_DIR_INVALID;
+}
+
+static bool siwx91x_is_data_width_valid(uint32_t data_width)
+{
+	switch (data_width) {
+	case 1:
+	case 2:
+	case 4:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static int siwx91x_burst_length(uint32_t blen)
+{
+	switch (blen) {
+	case 1:
+		return SRC_INC_8;
+	case 2:
+		return SRC_INC_16;
+	case 4:
+		return SRC_INC_32;
+	default:
+		return -EINVAL;
+	}
+}
+
+static int siwx91x_addr_adjustment(uint32_t adjustment)
+{
+	switch (adjustment) {
+	case 0:
+		return 0; /* Addr Increment */
+	case 2:
+		return UDMA_ADDR_INC_NONE; /* No Address increment */
+	default:
+		return -EINVAL;
+	}
+}
+
+/* Sets up the scatter-gather descriptor table for a DMA transfer */
+static int siwx91x_sg_fill_desc(RSI_UDMA_DESC_T *descs, const struct dma_config *config_zephyr)
+{
+	const struct dma_block_config *block_addr = config_zephyr->head_block;
+	RSI_UDMA_CHA_CONFIG_DATA_T *cfg_91x;
+
+	for (int i = 0; i < config_zephyr->block_count; i++) {
+		sys_write32((uint32_t)&descs[i].vsUDMAChaConfigData1, (mem_addr_t)&cfg_91x);
+
+		if (siwx91x_addr_adjustment(block_addr->source_addr_adj) == UDMA_ADDR_INC_NONE) {
+			descs[i].pSrcEndAddr = (void *)block_addr->source_address;
+		} else {
+			descs[i].pSrcEndAddr = (void *)(block_addr->source_address +
+							(block_addr->block_size -
+							 config_zephyr->source_burst_length));
+		}
+		if (siwx91x_addr_adjustment(block_addr->dest_addr_adj) == UDMA_ADDR_INC_NONE) {
+			descs[i].pDstEndAddr = (void *)block_addr->dest_address;
+		} else {
+			descs[i].pDstEndAddr = (void *)(block_addr->dest_address +
+							(block_addr->block_size -
+							 config_zephyr->dest_burst_length));
+		}
+
+		cfg_91x->srcSize = siwx91x_burst_length(config_zephyr->source_burst_length);
+		cfg_91x->dstSize = siwx91x_burst_length(config_zephyr->dest_burst_length);
+
+		/* Calculate the number of DMA transfers required */
+		if (block_addr->block_size / config_zephyr->source_burst_length >
+		    DMA_MAX_TRANSFER_COUNT) {
+			return -EINVAL;
+		}
+
+		cfg_91x->totalNumOfDMATrans =
+			block_addr->block_size / config_zephyr->source_burst_length - 1;
+
+		/* Set the transfer type based on whether it is a peripheral request */
+		if (siwx91x_transfer_direction(config_zephyr->channel_direction) ==
+		    TRANSFER_TO_OR_FROM_PER) {
+			cfg_91x->transferType = UDMA_MODE_PER_ALT_SCATTER_GATHER;
+		} else {
+			cfg_91x->transferType = UDMA_MODE_MEM_ALT_SCATTER_GATHER;
+		}
+
+		cfg_91x->rPower = ARBSIZE_1;
+
+		if (siwx91x_addr_adjustment(block_addr->source_addr_adj) < 0 ||
+		    siwx91x_addr_adjustment(block_addr->dest_addr_adj) < 0) {
+			return -EINVAL;
+		}
+
+		if (siwx91x_addr_adjustment(block_addr->source_addr_adj) == UDMA_ADDR_INC_NONE) {
+			cfg_91x->srcInc = UDMA_SRC_INC_NONE;
+		} else {
+			cfg_91x->srcInc = siwx91x_burst_length(config_zephyr->source_burst_length);
+		}
+
+		if (siwx91x_addr_adjustment(block_addr->dest_addr_adj) == UDMA_ADDR_INC_NONE) {
+			cfg_91x->dstInc = UDMA_DST_INC_NONE;
+		} else {
+			cfg_91x->dstInc = siwx91x_burst_length(config_zephyr->dest_burst_length);
+		}
+
+		/* Move to the next block */
+		block_addr = block_addr->next_block;
+	}
+
+	if (block_addr != NULL) {
+		/* next_block address for last block must be null */
+		return -EINVAL;
+	}
+
+	/* Set the transfer type for the last descriptor */
+	switch (siwx91x_transfer_direction(config_zephyr->channel_direction)) {
+	case TRANSFER_TO_OR_FROM_PER:
+		descs[config_zephyr->block_count - 1].vsUDMAChaConfigData1.transferType =
+			UDMA_MODE_BASIC;
+		break;
+	case TRANSFER_MEM_TO_MEM:
+		descs[config_zephyr->block_count - 1].vsUDMAChaConfigData1.transferType =
+			UDMA_MODE_AUTO;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+/* Configure DMA for scatter-gather transfer */
+static int siwx91x_sg_chan_config(const struct device *dev, RSI_UDMA_HANDLE_T udma_handle,
+				  uint32_t channel, const struct dma_config *config)
+{
+	const struct dma_siwx91x_config *cfg = dev->config;
+	struct dma_siwx91x_data *data = dev->data;
+	RSI_UDMA_DESC_T *sg_desc_base_addr = NULL;
+	uint8_t transfer_type;
+	enum dma_xfer_dir xfer_dir;
+
+	xfer_dir = siwx91x_transfer_direction(config->channel_direction);
+	if (xfer_dir == TRANSFER_DIR_INVALID) {
+		return -EINVAL;
+	}
+	if (xfer_dir == TRANSFER_TO_OR_FROM_PER) {
+		transfer_type = UDMA_MODE_PER_SCATTER_GATHER;
+	} else {
+		transfer_type = UDMA_MODE_MEM_SCATTER_GATHER;
+	}
+
+	if (!siwx91x_is_data_width_valid(config->source_data_size) ||
+	    !siwx91x_is_data_width_valid(config->dest_data_size)) {
+		return -EINVAL;
+	}
+
+	if (siwx91x_burst_length(config->source_burst_length) < 0 ||
+	    siwx91x_burst_length(config->dest_burst_length) < 0) {
+		return -EINVAL;
+	}
+
+	/* Request start index for scatter-gather descriptor table */
+	if (sys_mem_blocks_alloc_contiguous(data->dma_desc_pool, config->block_count,
+					    (void **)&sg_desc_base_addr)) {
+		return -EINVAL;
+	}
+
+	if (siwx91x_sg_fill_desc(sg_desc_base_addr, config)) {
+		return -EINVAL;
+	}
+
+	/* This channel information is used to distinguish scatter-gather transfers and
+	 * free the allocated descriptors in sg_transfer_desc_block
+	 */
+	data->chan_info[channel].Cnt = config->block_count;
+	data->zephyr_channel_info[channel].sg_desc_addr_info = sg_desc_base_addr;
+
+	/* Store the transfer direction. This is used to trigger SW request for
+	 * Memory to Memory transfers.
+	 */
+	data->zephyr_channel_info[channel].xfer_direction = xfer_dir;
+
+	RSI_UDMA_InterruptClear(udma_handle, channel);
+	RSI_UDMA_ErrorStatusClear(udma_handle);
+
+	if (cfg->reg == UDMA0) {
+		/* UDMA0 is accessible by both TA and M4, so an interrupt should be configured in
+		 * the TA-M4 common register set to signal the TA when UDMA0 is actively in use.
+		 */
+		sys_write32((BIT(channel) | M4SS_UDMA_INTR_SEL), (mem_addr_t)&M4SS_UDMA_INTR_SEL);
+	} else {
+		sys_set_bit((mem_addr_t)&cfg->reg->UDMA_INTR_MASK_REG, channel);
+	}
+
+	sys_write32(BIT(channel), (mem_addr_t)&cfg->reg->CHNL_PRI_ALT_SET);
+	sys_write32(BIT(channel), (mem_addr_t)&cfg->reg->CHNL_REQ_MASK_CLR);
+
+	RSI_UDMA_SetChannelScatterGatherTransfer(udma_handle, channel, config->block_count,
+						 sg_desc_base_addr, transfer_type);
+	return 0;
+}
+
+static int siwx91x_direct_chan_config(const struct device *dev, RSI_UDMA_HANDLE_T udma_handle,
+				      uint32_t channel, const struct dma_config *config)
+{
+	uint32_t dma_transfer_num = config->head_block->block_size / config->source_burst_length;
+	const struct dma_siwx91x_config *cfg = dev->config;
+	struct dma_siwx91x_data *data = dev->data;
+	UDMA_RESOURCES udma_resources = {
+		.reg = cfg->reg,
+		.udma_irq_num = cfg->irq_number,
+		/* SRAM address where UDMA descriptor is stored */
+		.desc = cfg->sram_desc_addr,
+	};
+	RSI_UDMA_CHA_CONFIG_DATA_T channel_control = {
+		.transferType = UDMA_MODE_BASIC,
+	};
+	RSI_UDMA_CHA_CFG_T channel_config = {};
+	enum dma_xfer_dir xfer_dir;
+	int status;
+
+	xfer_dir = siwx91x_transfer_direction(config->channel_direction);
+	if (xfer_dir == TRANSFER_DIR_INVALID) {
+		return -EINVAL;
+	}
+
+	channel_config.channelPrioHigh = config->channel_priority;
+	channel_config.periphReq = siwx91x_transfer_direction(config->channel_direction);
+	channel_config.dmaCh = channel;
+
+	if (channel_config.periphReq) {
+		/* Arbitration power for peripheral<->memory transfers */
+		channel_control.rPower = ARBSIZE_1;
+	} else {
+		/* Arbitration power for mem-mem transfers */
+		channel_control.rPower = ARBSIZE_1024;
+	}
+
+	/* Obtain the number of transfers */
+	if (dma_transfer_num >= DMA_MAX_TRANSFER_COUNT) {
+		/* Maximum number of transfers is 1024 */
+		channel_control.totalNumOfDMATrans = DMA_MAX_TRANSFER_COUNT - 1;
+	} else {
+		channel_control.totalNumOfDMATrans = dma_transfer_num;
+	}
+
+	if (!siwx91x_is_data_width_valid(config->source_data_size) ||
+	    !siwx91x_is_data_width_valid(config->dest_data_size)) {
+		return -EINVAL;
+	}
+	if (siwx91x_burst_length(config->source_burst_length) < 0 ||
+	    siwx91x_burst_length(config->dest_burst_length) < 0) {
+		return -EINVAL;
+	}
+
+	channel_control.srcSize = siwx91x_burst_length(config->source_burst_length);
+	channel_control.dstSize = siwx91x_burst_length(config->dest_burst_length);
+	if (siwx91x_addr_adjustment(config->head_block->source_addr_adj) < 0 ||
+	    siwx91x_addr_adjustment(config->head_block->dest_addr_adj) < 0) {
+		return -EINVAL;
+	}
+
+	if (siwx91x_addr_adjustment(config->head_block->source_addr_adj) == 0) {
+		channel_control.srcInc = siwx91x_burst_length(config->source_burst_length);
+	} else {
+		channel_control.srcInc = UDMA_SRC_INC_NONE;
+	}
+
+	if (siwx91x_addr_adjustment(config->head_block->dest_addr_adj) == 0) {
+		channel_control.dstInc = siwx91x_burst_length(config->dest_burst_length);
+	} else {
+		channel_control.dstInc = UDMA_DST_INC_NONE;
+	}
+
+	/* Clear the CHNL_PRI_ALT_CLR to use primary DMA descriptor structure */
+	sys_write32(BIT(channel), (mem_addr_t)&cfg->reg->CHNL_PRI_ALT_CLR);
+
+	status = UDMAx_ChannelConfigure(&udma_resources, (uint8_t)channel,
+					config->head_block->source_address,
+					config->head_block->dest_address,
+					dma_transfer_num, channel_control,
+					&channel_config, NULL, data->chan_info,
+					udma_handle);
+	if (status) {
+		return -EIO;
+	}
+
+	/* Store the transfer direction. This is used to trigger SW request for
+	 * Memory to Memory transfers.
+	 */
+	data->zephyr_channel_info[channel].xfer_direction = xfer_dir;
+
+	return 0;
+}
+
+/* Function to configure UDMA channel for transfer */
+static int siwx91x_dma_configure(const struct device *dev, uint32_t channel,
+				 struct dma_config *config)
+{
+	struct dma_siwx91x_data *data = dev->data;
+	void *udma_handle = &data->udma_handle;
+	int status;
+
+	/* Expecting a fixed channel number between 0-31 for dma0 and 0-11 for ulpdma */
+	if (channel >= data->dma_ctx.dma_channels) {
+		return -EINVAL;
+	}
+
+	/* Disable the channel before configuring */
+	if (RSI_UDMA_ChannelDisable(udma_handle, channel) != 0) {
+		return -EIO;
+	}
+
+	if (config->channel_priority != DMA_CH_PRIORITY_LOW &&
+	    config->channel_priority != DMA_CH_PRIORITY_HIGH) {
+		return -EINVAL;
+	}
+
+	if (config->cyclic || config->complete_callback_en) {
+		/* Cyclic DMA feature and completion callback for each block
+		 * is not supported
+		 */
+		return -EINVAL;
+	}
+
+	/* Configure dma channel for transfer */
+	if (config->head_block->next_block != NULL) {
+		/* Configure DMA for a Scatter-Gather transfer */
+		status = siwx91x_sg_chan_config(dev, udma_handle, channel, config);
+	} else {
+		status = siwx91x_direct_chan_config(dev, udma_handle, channel, config);
+	}
+	if (status) {
+		return status;
+	}
+
+	data->zephyr_channel_info[channel].dma_callback = config->dma_callback;
+	data->zephyr_channel_info[channel].cb_data = config->user_data;
+
+	atomic_set_bit(data->dma_ctx.atomic, channel);
+
+	return 0;
+}
+
+/* Function to reload UDMA channel for new transfer */
+static int siwx91x_dma_reload(const struct device *dev, uint32_t channel, uint32_t src,
+			      uint32_t dst, size_t size)
+{
+	const struct dma_siwx91x_config *cfg = dev->config;
+	struct dma_siwx91x_data *data = dev->data;
+	void *udma_handle = &data->udma_handle;
+	uint32_t desc_src_addr;
+	uint32_t desc_dst_addr;
+	uint32_t length;
+	RSI_UDMA_DESC_T *udma_table = cfg->sram_desc_addr;
+
+	/* Expecting a fixed channel number between 0-31 for dma0 and 0-11 for ulpdma */
+	if (channel >= data->dma_ctx.dma_channels) {
+		return -EINVAL;
+	}
+
+	/* Disable the channel before reloading transfer */
+	if (RSI_UDMA_ChannelDisable(udma_handle, channel) != 0) {
+		return -EIO;
+	}
+
+	/* Update new channel info to dev->data structure */
+	data->chan_info[channel].SrcAddr = src;
+	data->chan_info[channel].DestAddr = dst;
+	data->chan_info[channel].Size = size;
+
+	/* Update new transfer size to dev->data structure */
+	if (size >= DMA_MAX_TRANSFER_COUNT) {
+		data->chan_info[channel].Cnt = DMA_MAX_TRANSFER_COUNT - 1;
+	} else {
+		data->chan_info[channel].Cnt = size;
+	}
+
+	/* Program the DMA descriptors with new transfer data information. */
+	if (udma_table[channel].vsUDMAChaConfigData1.srcInc != UDMA_SRC_INC_NONE) {
+		length = data->chan_info[channel].Cnt
+			 << udma_table[channel].vsUDMAChaConfigData1.srcInc;
+		desc_src_addr = src + (length - 1);
+		udma_table[channel].pSrcEndAddr = (void *)desc_src_addr;
+	}
+
+	if (udma_table[channel].vsUDMAChaConfigData1.dstInc != UDMA_SRC_INC_NONE) {
+		length = data->chan_info[channel].Cnt
+			 << udma_table[channel].vsUDMAChaConfigData1.dstInc;
+		desc_dst_addr = dst + (length - 1);
+		udma_table[channel].pDstEndAddr = (void *)desc_dst_addr;
+	}
+
+	udma_table[channel].vsUDMAChaConfigData1.totalNumOfDMATrans = data->chan_info[channel].Cnt;
+	udma_table[channel].vsUDMAChaConfigData1.transferType = UDMA_MODE_BASIC;
+
+	return 0;
+}
+
+/* Function to start a DMA transfer */
+static int siwx91x_dma_start(const struct device *dev, uint32_t channel)
+{
+	const struct dma_siwx91x_config *cfg = dev->config;
+	struct dma_siwx91x_data *data = dev->data;
+	void *udma_handle = &data->udma_handle;
+
+	/* Expecting a fixed channel number between 0-31 for dma0 and 0-11 for ulpdma */
+	if (channel >= data->dma_ctx.dma_channels) {
+		return -EINVAL;
+	}
+
+	if (RSI_UDMA_ChannelEnable(udma_handle, channel) != 0) {
+		return -EINVAL;
+	}
+
+	/* Check if the transfer type is memory-memory */
+	if (data->zephyr_channel_info[channel].xfer_direction == TRANSFER_MEM_TO_MEM) {
+		/* Apply software trigger to start transfer */
+		sys_set_bit((mem_addr_t)&cfg->reg->CHNL_SW_REQUEST, channel);
+	}
+
+	return 0;
+}
+
+/* Function to stop a DMA transfer */
+static int siwx91x_dma_stop(const struct device *dev, uint32_t channel)
+{
+	struct dma_siwx91x_data *data = dev->data;
+	void *udma_handle = &data->udma_handle;
+
+	/* Expecting a fixed channel number between 0-31 for dma0 and 0-11 for ulpdma */
+	if (channel >= data->dma_ctx.dma_channels) {
+		return -EINVAL;
+	}
+
+	if (RSI_UDMA_ChannelDisable(udma_handle, channel) != 0) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/* Function to fetch DMA channel status */
+static int siwx91x_dma_get_status(const struct device *dev, uint32_t channel,
+				  struct dma_status *stat)
+{
+	const struct dma_siwx91x_config *cfg = dev->config;
+	struct dma_siwx91x_data *data = dev->data;
+	RSI_UDMA_DESC_T *udma_table = cfg->sram_desc_addr;
+
+	/* Expecting a fixed channel number between 0-31 for dma0 and 0-11 for ulpdma */
+	if (channel >= data->dma_ctx.dma_channels) {
+		return -EINVAL;
+	}
+
+	if (!atomic_test_bit(data->dma_ctx.atomic, channel)) {
+		return -EINVAL;
+	}
+
+	/* Read the channel status register */
+	stat->busy = sys_test_bit((mem_addr_t)&cfg->reg->CHANNEL_STATUS_REG, channel);
+
+	/* Obtain the transfer direction from channel descriptors */
+	if (udma_table[channel].vsUDMAChaConfigData1.srcInc == UDMA_SRC_INC_NONE) {
+		stat->dir = PERIPHERAL_TO_MEMORY;
+	} else if (udma_table[channel].vsUDMAChaConfigData1.dstInc == UDMA_DST_INC_NONE) {
+		stat->dir = MEMORY_TO_PERIPHERAL;
+	} else {
+		stat->dir = MEMORY_TO_MEMORY;
+	}
+
+	return 0;
+}
+
+bool siwx91x_dma_chan_filter(const struct device *dev, int channel, void *filter_param)
+{
+	ARG_UNUSED(dev);
+
+	if (!filter_param) {
+		return false;
+	}
+
+	if (*(int *)filter_param == channel) {
+		return true;
+	} else {
+		return false;
+	}
+}
+
+/* Function to initialize DMA peripheral */
+static int siwx91x_dma_init(const struct device *dev)
+{
+	const struct dma_siwx91x_config *cfg = dev->config;
+	struct dma_siwx91x_data *data = dev->data;
+	void *udma_handle = NULL;
+	UDMA_RESOURCES udma_resources = {
+		.reg = cfg->reg, /* UDMA register base address */
+		.udma_irq_num = cfg->irq_number,
+		.desc = cfg->sram_desc_addr,
+	};
+	int ret;
+
+	ret = clock_control_on(cfg->clock_dev, cfg->clock_subsys);
+	if (ret) {
+		return ret;
+	}
+
+	udma_handle = UDMAx_Initialize(&udma_resources, udma_resources.desc, NULL,
+				       (uint32_t *)&data->udma_handle);
+	if (udma_handle != &data->udma_handle) {
+		return -EINVAL;
+	}
+
+	/* Connect the DMA interrupt */
+	cfg->irq_configure();
+
+	if (UDMAx_DMAEnable(&udma_resources, udma_handle) != 0) {
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
+static void siwx91x_dma_isr(const struct device *dev)
+{
+	const struct dma_siwx91x_config *cfg = dev->config;
+	struct dma_siwx91x_data *data = dev->data;
+	UDMA_RESOURCES udma_resources = {
+		.reg = cfg->reg,
+		.udma_irq_num = cfg->irq_number,
+		.desc = cfg->sram_desc_addr,
+	};
+	uint8_t channel;
+
+	/* Disable the IRQ to prevent the ISR from being triggered by
+	 * interrupts from other DMA channels.
+	 */
+	irq_disable(cfg->irq_number);
+
+	channel = find_lsb_set(cfg->reg->UDMA_DONE_STATUS_REG);
+	/* Identify the interrupt channel */
+	if (!channel || channel > data->dma_ctx.dma_channels) {
+		goto out;
+	}
+	/* find_lsb_set() returns 1 indexed value */
+	channel -= 1;
+
+	if (data->zephyr_channel_info[channel].sg_desc_addr_info) {
+		/* A Scatter-Gather transfer is completed, free the allocated descriptors */
+		if (sys_mem_blocks_free_contiguous(
+			    data->dma_desc_pool,
+			    (void *)data->zephyr_channel_info[channel].sg_desc_addr_info,
+			    data->chan_info[channel].Cnt)) {
+			sys_write32(BIT(channel), (mem_addr_t)&cfg->reg->UDMA_DONE_STATUS_REG);
+			goto out;
+		}
+		data->chan_info[channel].Cnt = 0;
+		data->chan_info[channel].Size = 0;
+		data->zephyr_channel_info[channel].sg_desc_addr_info = NULL;
+	}
+
+	if (data->chan_info[channel].Cnt == data->chan_info[channel].Size) {
+		if (data->zephyr_channel_info[channel].dma_callback) {
+			/* Transfer complete, call user callback */
+			data->zephyr_channel_info[channel].dma_callback(
+				dev, data->zephyr_channel_info[channel].cb_data, channel, 0);
+		}
+		sys_write32(BIT(channel), (mem_addr_t)&cfg->reg->UDMA_DONE_STATUS_REG);
+	} else {
+		/* Call UDMA ROM IRQ handler. */
+		ROMAPI_UDMA_WRAPPER_API->uDMAx_IRQHandler(&udma_resources, udma_resources.desc,
+							  data->chan_info);
+		/* Is a Memory-to-memory Transfer */
+		if (udma_resources.desc[channel].vsUDMAChaConfigData1.srcInc != UDMA_SRC_INC_NONE &&
+		    udma_resources.desc[channel].vsUDMAChaConfigData1.dstInc != UDMA_DST_INC_NONE) {
+			/* Set the software trigger bit for starting next transfer */
+			sys_set_bit((mem_addr_t)&cfg->reg->CHNL_SW_REQUEST, channel);
+		}
+	}
+
+out:
+	/* Enable the IRQ to restore interrupt functionality for other DMA channels */
+	irq_enable(cfg->irq_number);
+}
+
+/* Store the Si91x DMA APIs */
+static DEVICE_API(dma, siwx91x_dma_api) = {
+	.config = siwx91x_dma_configure,
+	.reload = siwx91x_dma_reload,
+	.start = siwx91x_dma_start,
+	.stop = siwx91x_dma_stop,
+	.get_status = siwx91x_dma_get_status,
+	.chan_filter = siwx91x_dma_chan_filter,
+};
+
+#define SIWX91X_DMA_INIT(inst)                                                                     \
+	static ATOMIC_DEFINE(dma_channels_atomic_##inst, DT_INST_PROP(inst, dma_channels));        \
+	static UDMA_Channel_Info dma_channel_info_##inst[DT_INST_PROP(inst, dma_channels)];        \
+	SYS_MEM_BLOCKS_DEFINE_STATIC(desc_pool_##inst, sizeof(RSI_UDMA_DESC_T),                    \
+				     CONFIG_DMA_SILABS_SIWX91X_SG_BUFFER_COUNT, 4);                \
+	COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, silabs_sram_region),                               \
+		    (),                                                                            \
+		    (static __aligned(1024) RSI_UDMA_DESC_T                                        \
+			     siwx91x_dma_chan_desc##inst[DT_INST_PROP(inst, dma_channels) * 2];))  \
+	static struct dma_siwx91x_channel_info                                                     \
+		zephyr_channel_info_##inst[DT_INST_PROP(inst, dma_channels)];                      \
+	static struct dma_siwx91x_data dma_data_##inst = {                                         \
+		.dma_ctx.magic = DMA_MAGIC,                                                        \
+		.dma_ctx.dma_channels = DT_INST_PROP(inst, dma_channels),                          \
+		.dma_ctx.atomic = dma_channels_atomic_##inst,                                      \
+		.chan_info = dma_channel_info_##inst,                                              \
+		.zephyr_channel_info = zephyr_channel_info_##inst,                                 \
+		.dma_desc_pool = &desc_pool_##inst,                                                \
+	};                                                                                         \
+	static void siwx91x_dma_irq_configure_##inst(void)                                         \
+	{                                                                                          \
+		IRQ_CONNECT(DT_INST_IRQ(inst, irq), DT_INST_IRQ(inst, priority), siwx91x_dma_isr,  \
+			    DEVICE_DT_INST_GET(inst), 0);                                          \
+		irq_enable(DT_INST_IRQ(inst, irq));                                                \
+	}                                                                                          \
+	static const struct dma_siwx91x_config dma_cfg_##inst = {                                  \
+		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)),                             \
+		.clock_subsys = (clock_control_subsys_t)DT_INST_PHA(inst, clocks, clkid),          \
+		.reg = (UDMA0_Type *)DT_INST_REG_ADDR(inst),                                       \
+		.irq_number = DT_INST_PROP_BY_IDX(inst, interrupts, 0),                            \
+		.sram_desc_addr = COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, silabs_sram_region),     \
+					      ((RSI_UDMA_DESC_T *)DT_REG_ADDR(DT_INST_PHANDLE(inst, silabs_sram_region))), \
+					      (siwx91x_dma_chan_desc##inst)),                      \
+		.irq_configure = siwx91x_dma_irq_configure_##inst,                                 \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(inst, &siwx91x_dma_init, NULL, &dma_data_##inst, &dma_cfg_##inst,    \
+			      POST_KERNEL, CONFIG_DMA_INIT_PRIORITY, &siwx91x_dma_api);
+
+DT_INST_FOREACH_STATUS_OKAY(SIWX91X_DMA_INIT)
diff --git a/drivers/dma/dma_stm32.h b/drivers/dma/dma_stm32.h
index 54e7ac45524..a0d0674de7d 100644
--- a/drivers/dma/dma_stm32.h
+++ b/drivers/dma/dma_stm32.h
@@ -44,6 +44,9 @@ struct dma_stm32_config {
 	uint8_t offset; /* position in the list of dmamux channel list */
 #endif
 	struct dma_stm32_stream *streams;
+#ifdef CONFIG_DMA_STM32U5
+	volatile uint32_t *linked_list_buffer;
+#endif
 };
 
 uint32_t dma_stm32_id_to_stream(uint32_t id);
@@ -52,7 +55,8 @@ uint32_t dma_stm32_slot_to_channel(uint32_t id);
 #endif
 
 typedef void (*dma_stm32_clear_flag_func)(DMA_TypeDef *DMAx);
-#if !defined(CONFIG_SOC_SERIES_STM32G0X) && \
+#if !defined(CONFIG_SOC_SERIES_STM32C0X) && \
+	!defined(CONFIG_SOC_SERIES_STM32G0X) && \
 	!defined(CONFIG_SOC_SERIES_STM32H7X) && \
 	!defined(CONFIG_SOC_SERIES_STM32U0X)
 typedef uint32_t (*dma_stm32_check_flag_func)(DMA_TypeDef *DMAx);
diff --git a/drivers/dma/dma_stm32u5.c b/drivers/dma/dma_stm32u5.c
index 57c3f63ecdc..db9b9f102a9 100644
--- a/drivers/dma/dma_stm32u5.c
+++ b/drivers/dma/dma_stm32u5.c
@@ -24,6 +24,8 @@ LOG_MODULE_REGISTER(dma_stm32, CONFIG_DMA_LOG_LEVEL);
 
 #define DT_DRV_COMPAT st_stm32u5_dma
 
+#define STM32U5_DMA_LINKED_LIST_NODE_SIZE (2)
+
 static const uint32_t table_src_size[] = {
 	LL_DMA_SRC_DATAWIDTH_BYTE,
 	LL_DMA_SRC_DATAWIDTH_HALFWORD,
@@ -274,7 +276,9 @@ static void dma_stm32_irq_handler(const struct device *dev, uint32_t id)
 		stream->dma_callback(dev, stream->user_data, callback_arg, DMA_STATUS_BLOCK);
 	} else if (stm32_dma_is_tc_irq_active(dma, id)) {
 		/* Assuming not cyclic transfer */
-		stream->busy = false;
+		if (stream->cyclic == false) {
+			stream->busy = false;
+		}
 		/* Let HAL DMA handle flags on its own */
 		if (!stream->hal_override) {
 			dma_stm32_clear_tc(dma, id);
@@ -348,11 +352,10 @@ static int dma_stm32_configure(const struct device *dev,
 	struct dma_stm32_stream *stream =
 				&dev_config->streams[id - STM32_DMA_STREAM_OFFSET];
 	DMA_TypeDef *dma = (DMA_TypeDef *)dev_config->base;
-	LL_DMA_InitTypeDef DMA_InitStruct;
+	uint32_t ll_priority;
+	uint32_t ll_direction;
 	int ret;
 
-	LL_DMA_StructInit(&DMA_InitStruct);
-
 	/* Give channel from index 0 */
 	id = id - STM32_DMA_STREAM_OFFSET;
 
@@ -406,16 +409,6 @@ static int dma_stm32_configure(const struct device *dev,
 		return -EINVAL;
 	}
 
-	/* Continuous transfers are supported by hardware but not implemented
-	 * by this driver
-	 */
-	if (config->head_block->source_reload_en ||
-		config->head_block->dest_reload_en) {
-		LOG_ERR("source_reload_en and dest_reload_en not "
-			"implemented.");
-		return -EINVAL;
-	}
-
 	stream->busy		= true;
 	stream->dma_callback	= config->dma_callback;
 	stream->direction	= config->channel_direction;
@@ -432,30 +425,28 @@ static int dma_stm32_configure(const struct device *dev,
 		LOG_WRN("dest_buffer address is null.");
 	}
 
-	DMA_InitStruct.SrcAddress = config->head_block->source_address;
-	DMA_InitStruct.DestAddress = config->head_block->dest_address;
-	DMA_InitStruct.BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST;
-	DMA_InitStruct.DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD;
+	LL_DMA_ConfigAddresses(dma, dma_stm32_id_to_stream(id), config->head_block->source_address,
+			       config->head_block->dest_address);
 
-	ret = dma_stm32_get_priority(config->channel_priority,
-				     &DMA_InitStruct.Priority);
+	ret = dma_stm32_get_priority(config->channel_priority, &ll_priority);
 	if (ret < 0) {
 		return ret;
 	}
+	LL_DMA_SetChannelPriorityLevel(dma, dma_stm32_id_to_stream(id), ll_priority);
 
-	ret = dma_stm32_get_direction(config->channel_direction,
-				      &DMA_InitStruct.Direction);
+	ret = dma_stm32_get_direction(config->channel_direction, &ll_direction);
 	if (ret < 0) {
 		return ret;
 	}
+	LL_DMA_SetDataTransferDirection(dma, dma_stm32_id_to_stream(id), ll_direction);
 
 	/* This part is for source */
 	switch (config->head_block->source_addr_adj) {
 	case DMA_ADDR_ADJ_INCREMENT:
-		DMA_InitStruct.SrcIncMode = LL_DMA_SRC_INCREMENT;
+		LL_DMA_SetSrcIncMode(dma, dma_stm32_id_to_stream(id), LL_DMA_SRC_INCREMENT);
 		break;
 	case DMA_ADDR_ADJ_NO_CHANGE:
-		DMA_InitStruct.SrcIncMode = LL_DMA_SRC_FIXED;
+		LL_DMA_SetSrcIncMode(dma, dma_stm32_id_to_stream(id), LL_DMA_SRC_FIXED);
 		break;
 	case DMA_ADDR_ADJ_DECREMENT:
 		return -ENOTSUP;
@@ -464,16 +455,16 @@ static int dma_stm32_configure(const struct device *dev,
 			config->head_block->source_addr_adj);
 		return -EINVAL;
 	}
-	LOG_DBG("Channel (%d) src inc (%x).",
-				id, DMA_InitStruct.SrcIncMode);
+	LOG_DBG("Channel (%d) src inc (%x).", id,
+		LL_DMA_GetSrcIncMode(dma, dma_stm32_id_to_stream(id)));
 
 	/* This part is for dest */
 	switch (config->head_block->dest_addr_adj) {
 	case DMA_ADDR_ADJ_INCREMENT:
-		DMA_InitStruct.DestIncMode = LL_DMA_DEST_INCREMENT;
+		LL_DMA_SetDestIncMode(dma, dma_stm32_id_to_stream(id), LL_DMA_DEST_INCREMENT);
 		break;
 	case DMA_ADDR_ADJ_NO_CHANGE:
-		DMA_InitStruct.DestIncMode = LL_DMA_DEST_FIXED;
+		LL_DMA_SetDestIncMode(dma, dma_stm32_id_to_stream(id), LL_DMA_DEST_FIXED);
 		break;
 	case DMA_ADDR_ADJ_DECREMENT:
 		return -ENOTSUP;
@@ -482,36 +473,75 @@ static int dma_stm32_configure(const struct device *dev,
 			config->head_block->dest_addr_adj);
 		return -EINVAL;
 	}
-	LOG_DBG("Channel (%d) dest inc (%x).",
-				id, DMA_InitStruct.DestIncMode);
+	LOG_DBG("Channel (%d) dest inc (%x).", id,
+		LL_DMA_GetDestIncMode(dma, dma_stm32_id_to_stream(id)));
 
 	stream->source_periph = (stream->direction == PERIPHERAL_TO_MEMORY);
 
 	/* Set the data width, when source_data_size equals dest_data_size */
 	int index = find_lsb_set(config->source_data_size) - 1;
 
-	DMA_InitStruct.SrcDataWidth = table_src_size[index];
+	LL_DMA_SetSrcDataWidth(dma, dma_stm32_id_to_stream(id), table_src_size[index]);
 
 	index = find_lsb_set(config->dest_data_size) - 1;
-	DMA_InitStruct.DestDataWidth = table_dst_size[index];
+	LL_DMA_SetDestDataWidth(dma, dma_stm32_id_to_stream(id), table_dst_size[index]);
 
-	DMA_InitStruct.BlkDataLength = config->head_block->block_size;
+	LL_DMA_SetBlkDataLength(dma, dma_stm32_id_to_stream(id), config->head_block->block_size);
 
 	/* The request ID is stored in the dma_slot */
-	DMA_InitStruct.Request = config->dma_slot;
+	LL_DMA_SetPeriphRequest(dma, dma_stm32_id_to_stream(id), config->dma_slot);
+
+	if (config->head_block->source_reload_en == 0) {
+		LL_DMA_SetLinkStepMode(dma, dma_stm32_id_to_stream(id), LL_DMA_LSM_1LINK_EXECUTION);
+		/* Initialize the DMA structure in non-cyclic mode only */
+		LL_DMA_SetLinkedListAddrOffset(dma, dma_stm32_id_to_stream(id), 0);
+	} else {/* cyclic mode */
+		uint32_t linked_list_flags = 0;
+		volatile uint32_t *linked_list_node =
+			&dev_config->linked_list_buffer[id * STM32U5_DMA_LINKED_LIST_NODE_SIZE];
+		/* We use "linked list" to emulate circular mode.
+		 * The linked list can consists of just source and/or destination address.
+		 * Other registers can remain the same. Linked list itself doesn't contain
+		 * pointer to other item, since LLR register is not updated (ULL bit = 0).
+		 */
+		if (config->head_block->source_addr_adj == config->head_block->dest_addr_adj) {
+			/* We update both source and destination address */
+			linked_list_node[0] = config->head_block->source_address;
+			linked_list_node[1] = config->head_block->dest_address;
+			linked_list_flags = LL_DMA_UPDATE_CSAR | LL_DMA_UPDATE_CDAR;
+		} else if (config->head_block->source_addr_adj == DMA_ADDR_ADJ_INCREMENT) {
+			/* We update only source address */
+			linked_list_node[0] = config->head_block->source_address;
+			linked_list_flags = LL_DMA_UPDATE_CSAR;
+		} else if (config->head_block->dest_addr_adj == DMA_ADDR_ADJ_INCREMENT) {
+			/* We update only destination address */
+			linked_list_node[0] = config->head_block->dest_address;
+			linked_list_flags = LL_DMA_UPDATE_CDAR;
+		}
+		/* We update only destination address */
+		LL_DMA_SetLinkedListBaseAddr(dma, dma_stm32_id_to_stream(id),
+					     (uint32_t)&linked_list_node[0]);
+		LL_DMA_ConfigLinkUpdate(dma, dma_stm32_id_to_stream(id), linked_list_flags,
+					(uint32_t)&linked_list_node[0]);
 
-	LL_DMA_Init(dma, dma_stm32_id_to_stream(id), &DMA_InitStruct);
+		/* Continuous transfers with Linked List */
+		stream->cyclic = true;
+		LL_DMA_SetLinkStepMode(dma, dma_stm32_id_to_stream(id), LL_DMA_LSM_FULL_EXECUTION);
+
+		LL_DMA_EnableIT_HT(dma, dma_stm32_id_to_stream(id));
+	}
+
+#ifdef CONFIG_ARM_SECURE_FIRMWARE
+	LL_DMA_ConfigChannelSecure(dma, dma_stm32_id_to_stream(id),
+		LL_DMA_CHANNEL_SEC | LL_DMA_CHANNEL_SRC_SEC | LL_DMA_CHANNEL_DEST_SEC);
+	LL_DMA_EnableChannelPrivilege(dma, dma_stm32_id_to_stream(id));
+#endif
 
 	LL_DMA_EnableIT_TC(dma, dma_stm32_id_to_stream(id));
 	LL_DMA_EnableIT_USE(dma, dma_stm32_id_to_stream(id));
 	LL_DMA_EnableIT_ULE(dma, dma_stm32_id_to_stream(id));
 	LL_DMA_EnableIT_DTE(dma, dma_stm32_id_to_stream(id));
 
-	/* Enable Half-Transfer irq if circular mode is enabled */
-	if (config->head_block->source_reload_en) {
-		LL_DMA_EnableIT_HT(dma, dma_stm32_id_to_stream(id));
-	}
-
 	return ret;
 }
 
@@ -772,6 +802,11 @@ static struct dma_stm32_stream						\
 	dma_stm32_streams_##index[DT_INST_PROP_OR(index, dma_channels,	\
 		DT_NUM_IRQS(DT_DRV_INST(index)))];	\
 									\
+static volatile uint32_t dma_stm32_linked_list_buffer##index	\
+		[STM32U5_DMA_LINKED_LIST_NODE_SIZE * \
+		 DT_INST_PROP_OR(index, dma_channels,	\
+				 DT_NUM_IRQS(DT_DRV_INST(index)))] __nocache_noinit;	\
+									\
 const struct dma_stm32_config dma_stm32_config_##index = {		\
 	.pclken = { .bus = DT_INST_CLOCKS_CELL(index, bus),		\
 		    .enr = DT_INST_CLOCKS_CELL(index, bits) },		\
@@ -781,6 +816,7 @@ const struct dma_stm32_config dma_stm32_config_##index = {		\
 		DT_NUM_IRQS(DT_DRV_INST(index))				\
 	),		\
 	.streams = dma_stm32_streams_##index,				\
+	.linked_list_buffer = dma_stm32_linked_list_buffer##index	\
 };									\
 									\
 static struct dma_stm32_data dma_stm32_data_##index = {			\
diff --git a/drivers/dma/dma_ti_cc23x0.c b/drivers/dma/dma_ti_cc23x0.c
new file mode 100644
index 00000000000..5b1a6c72283
--- /dev/null
+++ b/drivers/dma/dma_ti_cc23x0.c
@@ -0,0 +1,382 @@
+/*
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ti_cc23x0_dma
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(dma_cc23x0, CONFIG_DMA_LOG_LEVEL);
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/dma.h>
+#include <zephyr/irq.h>
+#include <zephyr/sys/util.h>
+
+#include <driverlib/clkctl.h>
+#include <driverlib/udma.h>
+
+#include <inc/hw_evtsvt.h>
+#include <inc/hw_memmap.h>
+#include <inc/hw_types.h>
+
+/*
+ * Channels 0 to 5 are assigned to peripherals.
+ * Channels 6 and 7 are assigned to SW-initiated transfers.
+ */
+#define DMA_CC23_PERIPH_CH_MAX	5
+#define DMA_CC23_SW_CH_MIN	6
+#define DMA_CC23_SW_CH_MAX	7
+
+#define DMA_CC23_IS_SW_CH(ch)	((ch) >= DMA_CC23_SW_CH_MIN)
+
+/*
+ * In basic mode, the DMA controller performs transfers as long as there are more items
+ * to transfer, and a transfer request is present. This mode is used with peripherals that
+ * assert a DMA request signal whenever the peripheral is ready for a data transfer.
+ * Auto mode is similar to basic mode, except that when a transfer request is received,
+ * the transfer completes, even if the DMA request is removed. This mode is suitable for
+ * software-triggered transfers.
+ */
+#define DMA_CC23_MODE(ch)	(DMA_CC23_IS_SW_CH(ch) ? UDMA_MODE_AUTO : UDMA_MODE_BASIC)
+
+/* Each DMA channel is multiplexed between two peripherals which ID is in range 0 to 7 */
+#define DMA_CC23_IPID_MASK	GENMASK(2, 0)
+#define DMA_CC23_CHXSEL_REG(ch)	HWREG(EVTSVT_BASE + EVTSVT_O_DMACH0SEL + sizeof(uint32_t) * (ch))
+
+struct dma_cc23x0_channel {
+	uint8_t data_size;
+	dma_callback_t cb;
+	void *user_data;
+};
+
+struct dma_cc23x0_data {
+	__aligned(1024) uDMAControlTableEntry desc[UDMA_NUM_CHANNELS];
+	struct dma_cc23x0_channel channels[UDMA_NUM_CHANNELS];
+};
+
+/*
+ * If the channel is a software channel, then the completion will be signaled
+ * on this DMA dedicated interrupt.
+ * If a peripheral channel is used, then the completion will be signaled on the
+ * peripheral's interrupt.
+ */
+static void dma_cc23x0_isr(const struct device *dev)
+{
+	struct dma_cc23x0_data *data = dev->data;
+	struct dma_cc23x0_channel *ch_data;
+	uint32_t done_flags;
+	int i;
+
+	done_flags = uDMAIntStatus();
+
+	for (i = DMA_CC23_SW_CH_MIN; i <= DMA_CC23_SW_CH_MAX; i++) {
+		if (!(done_flags & BIT(i))) {
+			continue;
+		}
+
+		LOG_DBG("DMA transfer completed on channel %u", i);
+
+		ch_data = &data->channels[i];
+		if (ch_data->cb) {
+			ch_data->cb(dev, ch_data->user_data, i, DMA_STATUS_COMPLETE);
+		}
+
+		uDMAClearInt(done_flags & BIT(i));
+	}
+}
+
+static uint32_t dma_cc23x0_set_addr_adj(uint32_t *control, uint16_t addr_adj,
+					uint32_t inc_flags, uint32_t no_inc_flags)
+{
+	switch (addr_adj) {
+	case DMA_ADDR_ADJ_INCREMENT:
+		*control |= inc_flags;
+		break;
+	case DMA_ADDR_ADJ_NO_CHANGE:
+		*control |= no_inc_flags;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int dma_cc23x0_config(const struct device *dev, uint32_t channel,
+			     struct dma_config *config)
+{
+	struct dma_cc23x0_data *data = dev->data;
+	struct dma_cc23x0_channel *ch_data;
+	struct dma_block_config *block = config->head_block;
+	uint32_t control;
+	uint32_t data_size;
+	uint32_t src_inc_flags;
+	uint32_t dst_inc_flags;
+	uint32_t xfer_size;
+	uint32_t burst_len;
+	int ret;
+
+	if (channel >= UDMA_NUM_CHANNELS) {
+		LOG_ERR("Invalid channel (%u)", channel);
+		return -EINVAL;
+	}
+
+	if (config->dma_slot > DMA_CC23_IPID_MASK) {
+		LOG_ERR("Invalid trigger (%u)", config->dma_slot);
+		return -EINVAL;
+	}
+
+	if (config->block_count > 1) {
+		LOG_ERR("Chained transfers not supported");
+		return -ENOTSUP;
+	}
+
+	switch (config->source_data_size) {
+	case 1:
+		src_inc_flags = UDMA_SRC_INC_8;
+		break;
+	case 2:
+		src_inc_flags = UDMA_SRC_INC_16;
+		break;
+	case 4:
+		src_inc_flags = UDMA_SRC_INC_32;
+		break;
+	default:
+		LOG_ERR("Invalid source data size (%u)", config->source_data_size);
+		return -EINVAL;
+	}
+
+	switch (config->dest_data_size) {
+	case 1:
+		dst_inc_flags = UDMA_DST_INC_8;
+		break;
+	case 2:
+		dst_inc_flags = UDMA_DST_INC_16;
+		break;
+	case 4:
+		dst_inc_flags = UDMA_DST_INC_32;
+		break;
+	default:
+		LOG_ERR("Invalid destination data size (%u)", config->dest_data_size);
+		return -EINVAL;
+	}
+
+	data_size = MIN(config->source_data_size, config->dest_data_size);
+
+	switch (data_size) {
+	case 1:
+		control = UDMA_SIZE_8;
+		break;
+	case 2:
+		control = UDMA_SIZE_16;
+		break;
+	case 4:
+		control = UDMA_SIZE_32;
+		break;
+	default:
+		LOG_ERR("Invalid data size (%u)", data_size);
+		return -EINVAL;
+	}
+
+	ret = dma_cc23x0_set_addr_adj(&control, block->source_addr_adj,
+				      src_inc_flags, UDMA_SRC_INC_NONE);
+	if (ret) {
+		LOG_ERR("Invalid source address adjustment type (%u)", block->source_addr_adj);
+		return ret;
+	}
+
+	ret = dma_cc23x0_set_addr_adj(&control, block->dest_addr_adj,
+				      dst_inc_flags, UDMA_DST_INC_NONE);
+	if (ret) {
+		LOG_ERR("Invalid dest address adjustment type (%u)", block->dest_addr_adj);
+		return ret;
+	}
+
+	xfer_size = block->block_size / data_size;
+	if (!xfer_size || xfer_size > UDMA_XFER_SIZE_MAX) {
+		LOG_ERR("Invalid block size (%u - must be in range %u to %u)",
+			block->block_size, data_size, data_size * UDMA_XFER_SIZE_MAX);
+		return -EINVAL;
+	}
+
+	burst_len = config->source_burst_length / data_size;
+	if (burst_len <= UDMA_XFER_SIZE_MAX && IS_POWER_OF_TWO(burst_len)) {
+		control |= LOG2(burst_len) << UDMA_ARB_S;
+	} else {
+		LOG_ERR("Invalid burst length (%u - must be a power of 2 between %u and %u)",
+			config->source_burst_length, data_size, data_size * UDMA_XFER_SIZE_MAX);
+		return -EINVAL;
+	}
+
+	ch_data = &data->channels[channel];
+	ch_data->data_size = data_size;
+	ch_data->cb = config->dma_callback;
+	ch_data->user_data = config->user_data;
+
+	if (uDMAIsChannelEnabled(BIT(channel))) {
+		return -EBUSY;
+	}
+
+	if (DMA_CC23_IS_SW_CH(channel)) {
+		uDMAEnableSwEventInt(BIT(channel));
+	} else {
+		/* Select peripheral */
+		DMA_CC23_CHXSEL_REG(channel) = config->dma_slot;
+	}
+
+	uDMASetChannelControl(&data->desc[channel], control);
+
+	uDMASetChannelTransfer(&data->desc[channel], DMA_CC23_MODE(channel),
+			       (void *)block->source_address,
+			       (void *)block->dest_address,
+			       xfer_size);
+
+	LOG_DBG("Configured channel %u for %08x to %08x (%u bytes)",
+		channel,
+		block->source_address,
+		block->dest_address,
+		block->block_size);
+
+	return 0;
+}
+
+static int dma_cc23x0_start(const struct device *dev, uint32_t channel)
+{
+	if (uDMAIsChannelEnabled(BIT(channel))) {
+		return 0;
+	}
+
+	uDMAEnableChannel(BIT(channel));
+
+	if (DMA_CC23_IS_SW_CH(channel)) {
+		/* Request DMA channel to start a memory to memory transfer */
+		uDMARequestChannel(BIT(channel));
+	}
+
+	return 0;
+}
+
+static int dma_cc23x0_stop(const struct device *dev, uint32_t channel)
+{
+	uDMADisableChannel(BIT(channel));
+
+	return 0;
+}
+
+static int dma_cc23x0_reload(const struct device *dev, uint32_t channel,
+			     uint32_t src, uint32_t dst, size_t size)
+{
+	struct dma_cc23x0_data *data = dev->data;
+	struct dma_cc23x0_channel *ch_data = &data->channels[channel];
+	uint32_t xfer_size = size / ch_data->data_size;
+
+	if (uDMAIsChannelEnabled(BIT(channel))) {
+		return -EBUSY;
+	}
+
+	uDMASetChannelTransfer(&data->desc[channel], DMA_CC23_MODE(channel),
+			       (void *)src, (void *)dst, xfer_size);
+
+	LOG_DBG("Reloaded channel %u for %08x to %08x (%u bytes)",
+		channel, src, dst, size);
+
+	return 0;
+}
+
+static int dma_cc23x0_get_status(const struct device *dev, uint32_t channel,
+				 struct dma_status *stat)
+{
+	struct dma_cc23x0_data *data = dev->data;
+	uint8_t ch_sel;
+
+	if (channel >= UDMA_NUM_CHANNELS || !stat) {
+		return -EINVAL;
+	}
+
+	ch_sel = DMA_CC23_CHXSEL_REG(channel) & DMA_CC23_IPID_MASK;
+	switch (channel) {
+	case 0:
+		if (ch_sel == 0) {
+			/* spi0txtrg */
+			stat->dir = MEMORY_TO_PERIPHERAL;
+		} else {
+			/* uart0rxtrg */
+			stat->dir = PERIPHERAL_TO_MEMORY;
+		}
+		break;
+	case 1:
+		if (ch_sel == 1) {
+			/* spi0rxtrg */
+			stat->dir = PERIPHERAL_TO_MEMORY;
+		} else {
+			/* uart0txtrg */
+			stat->dir = MEMORY_TO_PERIPHERAL;
+		}
+		break;
+	case 2:
+	case 4:
+		/* ch2: uart0txtrg | ch4: laestrga */
+		stat->dir = MEMORY_TO_PERIPHERAL;
+		break;
+	case 3:
+	case 5:
+		/* ch3: adc0trg or uart0rxtrg | ch5: laestrgb or adc0trg */
+		stat->dir = PERIPHERAL_TO_MEMORY;
+		break;
+	default:
+		/* ch6, ch7: SW trg */
+		stat->dir = MEMORY_TO_MEMORY;
+		break;
+	}
+
+	stat->busy = uDMAIsChannelEnabled(BIT(channel));
+
+	stat->pending_length = uDMAGetChannelSize(&data->desc[channel]);
+	if (data->desc[channel].control & UDMA_SIZE_16) {
+		stat->pending_length <<= 1;
+	} else if (data->desc[channel].control & UDMA_SIZE_32) {
+		stat->pending_length <<= 2;
+	}
+
+	return 0;
+}
+
+static int dma_cc23x0_init(const struct device *dev)
+{
+	struct dma_cc23x0_data *data = dev->data;
+
+	IRQ_CONNECT(DT_INST_IRQN(0),
+		    DT_INST_IRQ(0, priority),
+		    dma_cc23x0_isr,
+		    DEVICE_DT_INST_GET(0),
+		    0);
+	irq_enable(DT_INST_IRQN(0));
+
+	/* Enable clock */
+	CLKCTLEnable(CLKCTL_BASE, CLKCTL_DMA);
+
+	/* Enable DMA */
+	uDMAEnable();
+
+	/* Set base address for channel control table (descriptors) */
+	uDMASetControlBase(data->desc);
+
+	return 0;
+}
+
+static struct dma_cc23x0_data cc23x0_data;
+
+static const struct dma_driver_api dma_cc23x0_api = {
+	.config = dma_cc23x0_config,
+	.start = dma_cc23x0_start,
+	.stop = dma_cc23x0_stop,
+	.reload = dma_cc23x0_reload,
+	.get_status = dma_cc23x0_get_status,
+};
+
+DEVICE_DT_INST_DEFINE(0, &dma_cc23x0_init, NULL,
+		      &cc23x0_data, NULL,
+		      PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY,
+		      &dma_cc23x0_api);
diff --git a/drivers/dma/dma_wch.c b/drivers/dma/dma_wch.c
new file mode 100644
index 00000000000..2174de15015
--- /dev/null
+++ b/drivers/dma/dma_wch.c
@@ -0,0 +1,499 @@
+/*
+ * Copyright (c) 2024 Paul Wedeck <paulwedeck@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#define DT_DRV_COMPAT wch_wch_dma
+
+#include <zephyr/drivers/dma.h>
+#include <zephyr/drivers/clock_control.h>
+
+#include <ch32fun.h>
+
+#define DMA_WCH_MAX_CHAN      11
+#define DMA_WCH_MAX_CHAN_BASE 8
+
+#define DMA_WCH_AIF        (DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)
+#define DMA_WCH_IF_OFF(ch) (4 * (ch))
+#define DMA_WCH_MAX_BLOCK  ((UINT32_C(2) << 16) - 1)
+
+struct dma_wch_chan_regs {
+	volatile uint32_t CFGR;
+	volatile uint32_t CNTR;
+	volatile uint32_t PADDR;
+	volatile uint32_t MADDR;
+	volatile uint32_t reserved1;
+};
+
+struct dma_wch_regs {
+	DMA_TypeDef base;
+	struct dma_wch_chan_regs channels[DMA_WCH_MAX_CHAN];
+	DMA_TypeDef ext;
+};
+
+struct dma_wch_config {
+	struct dma_wch_regs *regs;
+	uint32_t num_channels;
+	const struct device *clock_dev;
+	uint8_t clock_id;
+	void (*irq_config_func)(const struct device *dev);
+};
+
+struct dma_wch_channel {
+	void *user_data;
+	dma_callback_t dma_cb;
+};
+
+struct dma_wch_data {
+	struct dma_context ctx;
+	struct dma_wch_channel *channels;
+};
+
+static uint8_t dma_wch_get_ip(const struct device *dev, uint32_t chan)
+{
+	const struct dma_wch_config *config = dev->config;
+	struct dma_wch_regs *regs = config->regs;
+	uint32_t intfr;
+
+	if (chan > DMA_WCH_MAX_CHAN_BASE) {
+		chan -= DMA_WCH_MAX_CHAN_BASE;
+		intfr = regs->ext.INTFR;
+		return (intfr >> DMA_WCH_IF_OFF(chan)) & DMA_WCH_AIF;
+	}
+
+	intfr = regs->base.INTFR;
+	return (intfr >> DMA_WCH_IF_OFF(chan)) & DMA_WCH_AIF;
+}
+
+static bool dma_wch_busy(const struct device *dev, uint32_t ch)
+{
+	const struct dma_wch_config *config = dev->config;
+	struct dma_wch_regs *regs = config->regs;
+
+	return (regs->channels[ch].CFGR & DMA_CFGR1_EN) > 0 &&
+	       !(dma_wch_get_ip(dev, ch) & DMA_TCIF1);
+}
+
+static int dma_wch_init(const struct device *dev)
+{
+	const struct dma_wch_config *config = dev->config;
+	clock_control_subsys_t clock_sys = (clock_control_subsys_t *)(uintptr_t)config->clock_id;
+
+	if (config->num_channels > DMA_WCH_MAX_CHAN) {
+		return -ENOTSUP;
+	}
+
+	clock_control_on(config->clock_dev, clock_sys);
+
+	config->irq_config_func(dev);
+	return 0;
+}
+
+static int dma_wch_config(const struct device *dev, uint32_t ch, struct dma_config *dma_cfg)
+{
+	const struct dma_wch_config *config = dev->config;
+	struct dma_wch_data *data = dev->data;
+	struct dma_wch_regs *regs = config->regs;
+	unsigned int key;
+	int ret = 0;
+
+	uint32_t cfgr = 0;
+	uint32_t cntr = 0;
+	uint32_t paddr = 0;
+	uint32_t maddr = 0;
+
+	if (config->num_channels <= ch) {
+		return -EINVAL;
+	}
+
+	if (dma_cfg->block_count != 1) {
+		return -ENOTSUP;
+	}
+
+	if (dma_cfg->head_block->block_size > DMA_WCH_MAX_BLOCK ||
+	    dma_cfg->head_block->source_gather_en || dma_cfg->head_block->dest_scatter_en ||
+	    dma_cfg->head_block->source_reload_en || dma_cfg->channel_priority > 3 ||
+	    dma_cfg->head_block->source_addr_adj == DMA_ADDR_ADJ_DECREMENT ||
+	    dma_cfg->head_block->dest_addr_adj == DMA_ADDR_ADJ_DECREMENT ||
+	    dma_cfg->head_block->dest_reload_en) {
+		return -ENOTSUP;
+	}
+
+	cntr = dma_cfg->head_block->block_size;
+
+	switch (dma_cfg->channel_direction) {
+	case MEMORY_TO_MEMORY:
+		cfgr |= DMA_CFGR1_MEM2MEM;
+		paddr = dma_cfg->head_block->source_address;
+		maddr = dma_cfg->head_block->dest_address;
+
+		if (dma_cfg->cyclic) {
+			return -ENOTSUP;
+		}
+		break;
+	case MEMORY_TO_PERIPHERAL:
+		maddr = dma_cfg->head_block->source_address;
+		paddr = dma_cfg->head_block->dest_address;
+		cfgr |= DMA_CFGR1_DIR;
+		break;
+	case PERIPHERAL_TO_MEMORY:
+		paddr = dma_cfg->head_block->source_address;
+		maddr = dma_cfg->head_block->dest_address;
+		break;
+	default:
+		return -ENOTSUP;
+	}
+	cfgr |= dma_cfg->channel_priority * DMA_CFGR1_PL_0;
+
+	if (dma_cfg->channel_direction == MEMORY_TO_PERIPHERAL) {
+		cfgr |= dma_width_index(dma_cfg->source_data_size / BITS_PER_BYTE) *
+			DMA_CFGR1_MSIZE_0;
+		cfgr |= dma_width_index(dma_cfg->dest_data_size / BITS_PER_BYTE) *
+			DMA_CFGR1_PSIZE_0;
+
+		cfgr |= (dma_cfg->head_block->dest_addr_adj == DMA_ADDR_ADJ_INCREMENT)
+				? DMA_CFGR1_PINC
+				: 0;
+		cfgr |= (dma_cfg->head_block->source_addr_adj == DMA_ADDR_ADJ_INCREMENT)
+				? DMA_CFGR1_MINC
+				: 0;
+	} else {
+		cfgr |= dma_width_index(dma_cfg->source_data_size / BITS_PER_BYTE) *
+			DMA_CFGR1_PSIZE_0;
+		cfgr |= dma_width_index(dma_cfg->dest_data_size / BITS_PER_BYTE) *
+			DMA_CFGR1_MSIZE_0;
+
+		cfgr |= (dma_cfg->head_block->dest_addr_adj == DMA_ADDR_ADJ_INCREMENT)
+				? DMA_CFGR1_MINC
+				: 0;
+		cfgr |= (dma_cfg->head_block->source_addr_adj == DMA_ADDR_ADJ_INCREMENT)
+				? DMA_CFGR1_PINC
+				: 0;
+	}
+
+	if (dma_cfg->cyclic) {
+		cfgr |= DMA_CFGR1_CIRC;
+	}
+
+	if (dma_cfg->dma_callback) {
+		if (!dma_cfg->error_callback_dis) {
+			cfgr |= DMA_CFGR1_TEIE;
+		}
+
+		if (dma_cfg->complete_callback_en) {
+			cfgr |= DMA_CFGR1_HTIE;
+		}
+
+		cfgr |= DMA_CFGR1_TCIE;
+	}
+
+	key = irq_lock();
+
+	if (dma_wch_busy(dev, ch)) {
+		ret = -EBUSY;
+		goto end;
+	}
+
+	data->channels[ch].user_data = dma_cfg->user_data;
+	data->channels[ch].dma_cb = dma_cfg->dma_callback;
+
+	regs->channels[ch].CFGR = 0;
+
+	if (ch <= DMA_WCH_MAX_CHAN_BASE) {
+		regs->base.INTFCR = DMA_WCH_AIF << DMA_WCH_IF_OFF(ch);
+	} else {
+		regs->ext.INTFCR = DMA_WCH_AIF << DMA_WCH_IF_OFF(ch - DMA_WCH_MAX_CHAN_BASE);
+	}
+
+	regs->channels[ch].PADDR = paddr;
+	regs->channels[ch].MADDR = maddr;
+	regs->channels[ch].CNTR = cntr;
+	regs->channels[ch].CFGR = cfgr;
+end:
+	irq_unlock(key);
+	return ret;
+}
+
+#ifdef CONFIG_DMA_64BIT
+static int dma_wch_reload(const struct device *dev, uint32_t ch, uint64_t src, uint64_t dst,
+			  size_t size)
+#else
+static int dma_wch_reload(const struct device *dev, uint32_t ch, uint32_t src, uint32_t dst,
+			  size_t size)
+#endif
+{
+	const struct dma_wch_config *config = dev->config;
+	struct dma_wch_regs *regs = config->regs;
+	uint32_t maddr, paddr;
+	int ret = 0;
+	unsigned int key;
+
+	if (config->num_channels <= ch) {
+		return -EINVAL;
+	}
+
+	key = irq_lock();
+
+	if (dma_wch_busy(dev, ch)) {
+		ret = -EBUSY;
+		goto end;
+	}
+
+	if (regs->channels[ch].CFGR & DMA_CFGR1_DIR) {
+		maddr = src;
+		paddr = dst;
+	} else {
+		maddr = dst;
+		paddr = src;
+	}
+
+	regs->channels[ch].MADDR = maddr;
+	regs->channels[ch].PADDR = paddr;
+	regs->channels[ch].CNTR = size;
+end:
+	irq_unlock(key);
+	return ret;
+}
+
+static int dma_wch_start(const struct device *dev, uint32_t ch)
+{
+	const struct dma_wch_config *config = dev->config;
+	struct dma_wch_regs *regs = config->regs;
+	unsigned int key;
+
+	if (config->num_channels <= ch) {
+		return -EINVAL;
+	}
+
+	key = irq_lock();
+	regs->channels[ch].CFGR |= DMA_CFGR1_EN;
+	irq_unlock(key);
+
+	return 0;
+}
+
+static int dma_wch_stop(const struct device *dev, uint32_t ch)
+{
+	const struct dma_wch_config *config = dev->config;
+	struct dma_wch_regs *regs = config->regs;
+	unsigned int key;
+
+	if (config->num_channels <= ch) {
+		return -EINVAL;
+	}
+
+	key = irq_lock();
+	regs->channels[ch].CFGR &= ~DMA_CFGR1_EN;
+	irq_unlock(key);
+
+	return 0;
+}
+
+static int dma_wch_resume(const struct device *dev, uint32_t ch)
+{
+	const struct dma_wch_config *config = dev->config;
+	struct dma_wch_regs *regs = config->regs;
+	int ret = 0;
+	unsigned int key;
+
+	if (config->num_channels <= ch) {
+		return -EINVAL;
+	}
+
+	key = irq_lock();
+
+	if (regs->channels[ch].CFGR & DMA_CFGR1_EN) {
+		ret = -EINVAL;
+		goto end;
+	}
+
+	regs->channels[ch].CFGR |= DMA_CFGR1_EN;
+end:
+	irq_unlock(key);
+	return ret;
+}
+
+static int dma_wch_suspend(const struct device *dev, uint32_t ch)
+{
+	const struct dma_wch_config *config = dev->config;
+	struct dma_wch_regs *regs = config->regs;
+	int ret = 0;
+	unsigned int key;
+
+	if (config->num_channels <= ch) {
+		return -EINVAL;
+	}
+
+	key = irq_lock();
+
+	if (!(regs->channels[ch].CFGR & DMA_CFGR1_EN)) {
+		ret = -EINVAL;
+		goto end;
+	}
+
+	regs->channels[ch].CFGR &= ~DMA_CFGR1_EN;
+end:
+	irq_unlock(key);
+	return ret;
+}
+
+static int dma_wch_get_status(const struct device *dev, uint32_t ch, struct dma_status *status)
+{
+	const struct dma_wch_config *config = dev->config;
+	struct dma_wch_regs *regs = config->regs;
+	uint32_t cfgr;
+	unsigned int key;
+
+	if (config->num_channels <= ch) {
+		return -EINVAL;
+	}
+
+	key = irq_lock();
+	cfgr = regs->channels[ch].CFGR;
+
+	status->busy = dma_wch_busy(dev, ch);
+	if (cfgr & DMA_CFGR1_MEM2MEM) {
+		status->dir = MEMORY_TO_MEMORY;
+	} else if (cfgr & DMA_CFGR1_DIR) {
+		status->dir = MEMORY_TO_PERIPHERAL;
+	} else {
+		status->dir = PERIPHERAL_TO_MEMORY;
+	}
+
+	status->pending_length = regs->channels[ch].CNTR;
+	if (cfgr & DMA_CFGR1_DIR) {
+		status->read_position = regs->channels[ch].MADDR;
+		status->write_position = regs->channels[ch].PADDR;
+	} else {
+		status->read_position = regs->channels[ch].PADDR;
+		status->write_position = regs->channels[ch].MADDR;
+	}
+	irq_unlock(key);
+	return 0;
+}
+
+int dma_wch_get_attribute(const struct device *dev, uint32_t type, uint32_t *value)
+{
+	switch (type) {
+	case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
+	case DMA_ATTR_BUFFER_SIZE_ALIGNMENT:
+	case DMA_ATTR_COPY_ALIGNMENT:
+	case DMA_ATTR_MAX_BLOCK_COUNT:
+		*value = 1;
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
+static void dma_wch_handle_callback(const struct device *dev, uint32_t ch, uint8_t ip)
+{
+	const struct dma_wch_data *data = dev->data;
+	void *cb_data;
+	dma_callback_t cb_func;
+	unsigned int key = irq_lock();
+
+	cb_data = data->channels[ch].user_data;
+	cb_func = data->channels[ch].dma_cb;
+	irq_unlock(key);
+
+	if (!cb_func) {
+		return;
+	}
+
+	if (ip & DMA_TCIF1) {
+		cb_func(dev, cb_data, ch, DMA_STATUS_COMPLETE);
+	} else if (ip & DMA_TEIF1) {
+		cb_func(dev, cb_data, ch, -EIO);
+	} else if (ip & DMA_HTIF1) {
+		cb_func(dev, cb_data, ch, DMA_STATUS_BLOCK);
+	}
+}
+
+static void dma_wch_isr(const struct device *dev, uint32_t chan)
+{
+	const struct dma_wch_config *config = dev->config;
+	struct dma_wch_regs *regs = config->regs;
+	uint32_t intfr = regs->base.INTFR;
+
+	intfr &= (DMA_WCH_AIF << DMA_WCH_IF_OFF(chan));
+	if (intfr & DMA_TCIF1 << DMA_WCH_IF_OFF(chan)) {
+		regs->channels[chan].CFGR &= ~DMA_CFGR1_EN;
+	}
+	regs->base.INTFCR = intfr;
+
+	dma_wch_handle_callback(dev, chan, intfr >> DMA_WCH_IF_OFF(chan));
+}
+
+static void dma_wch_isr_ext(const struct device *dev, uint32_t chan)
+{
+	const struct dma_wch_config *config = dev->config;
+	struct dma_wch_regs *regs = config->regs;
+	uint32_t chan_idx = chan - DMA_WCH_MAX_CHAN_BASE;
+	uint32_t intfr = regs->ext.INTFR;
+
+	intfr &= (DMA_WCH_AIF << DMA_WCH_IF_OFF(chan_idx));
+	regs->ext.INTFCR = intfr;
+
+	dma_wch_handle_callback(dev, chan, intfr >> DMA_WCH_IF_OFF(chan_idx));
+}
+
+static DEVICE_API(dma, dma_wch_driver_api) = {
+	.config = dma_wch_config,
+	.reload = dma_wch_reload,
+	.start = dma_wch_start,
+	.stop = dma_wch_stop,
+	.resume = dma_wch_resume,
+	.suspend = dma_wch_suspend,
+	.get_status = dma_wch_get_status,
+	.get_attribute = dma_wch_get_attribute,
+};
+
+#define GENERATE_ISR(ch, _)                                                                        \
+	__used static void dma_wch_isr##ch(const struct device *dev)                               \
+	{                                                                                          \
+		if (ch <= DMA_WCH_MAX_CHAN_BASE) {                                                 \
+			dma_wch_isr(dev, ch);                                                      \
+		} else {                                                                           \
+			dma_wch_isr_ext(dev, ch);                                                  \
+		}                                                                                  \
+	}
+
+LISTIFY(DMA_WCH_MAX_CHAN, GENERATE_ISR, ())
+
+#define IRQ_CONFIGURE(n, idx)                                                                      \
+	IRQ_CONNECT(DT_INST_IRQ_BY_IDX(idx, n, irq), DT_INST_IRQ_BY_IDX(idx, n, priority),         \
+		    dma_wch_isr##n, DEVICE_DT_INST_GET(idx), 0);                                   \
+	irq_enable(DT_INST_IRQ_BY_IDX(idx, n, irq));
+
+#define CONFIGURE_ALL_IRQS(idx, n) LISTIFY(n, IRQ_CONFIGURE, (), idx)
+
+#define WCH_DMA_INIT(idx)                                                                          \
+	static void dma_wch##idx##_irq_config(const struct device *dev)                            \
+	{                                                                                          \
+		CONFIGURE_ALL_IRQS(idx, DT_NUM_IRQS(DT_DRV_INST(idx)));                            \
+	}                                                                                          \
+	static const struct dma_wch_config dma_wch##idx##_config = {                               \
+		.regs = (struct dma_wch_regs *)DT_INST_REG_ADDR(idx),                              \
+		.num_channels = DT_INST_PROP(idx, dma_channels),                                   \
+		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)),                              \
+		.clock_id = DT_INST_CLOCKS_CELL(idx, id),                                          \
+		.irq_config_func = dma_wch##idx##_irq_config,                                      \
+	};                                                                                         \
+	static struct dma_wch_channel dma_wch##idx##_channels[DT_INST_PROP(idx, dma_channels)];    \
+	ATOMIC_DEFINE(dma_wch_atomic##idx, DT_INST_PROP(idx, dma_channels));                       \
+	static struct dma_wch_data dma_wch##idx##_data = {                                         \
+		.ctx =                                                                             \
+			{                                                                          \
+				.magic = DMA_MAGIC,                                                \
+				.atomic = dma_wch_atomic##idx,                                     \
+				.dma_channels = DT_INST_PROP(idx, dma_channels),                   \
+			},                                                                         \
+		.channels = dma_wch##idx##_channels,                                               \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(idx, &dma_wch_init, NULL, &dma_wch##idx##_data,                      \
+			      &dma_wch##idx##_config, PRE_KERNEL_1, CONFIG_DMA_INIT_PRIORITY,      \
+			      &dma_wch_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(WCH_DMA_INIT)
diff --git a/drivers/dma/dma_xilinx_axi_dma.c b/drivers/dma/dma_xilinx_axi_dma.c
index 3b40f42f560..7503e64909d 100644
--- a/drivers/dma/dma_xilinx_axi_dma.c
+++ b/drivers/dma/dma_xilinx_axi_dma.c
@@ -359,8 +359,7 @@ uint32_t dma_xilinx_axi_dma_last_received_frame_length(const struct device *dev)
 	return data->channels[XILINX_AXI_DMA_RX_CHANNEL_NUM].last_rx_size;
 }
 
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Waddress-of-packed-member"
+TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER)
 static inline void
 dma_xilinx_axi_dma_acknowledge_interrupt(struct dma_xilinx_axi_dma_channel *channel_data)
 {
@@ -371,10 +370,9 @@ dma_xilinx_axi_dma_acknowledge_interrupt(struct dma_xilinx_axi_dma_channel *chan
 
 	dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->dmacr, dmacr);
 }
-#pragma GCC diagnostic pop
+TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER)
 
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Waddress-of-packed-member"
+TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER)
 static bool dma_xilinx_axi_dma_channel_has_error(
 	const struct dma_xilinx_axi_dma_channel *channel_data,
 	volatile const struct dma_xilinx_axi_dma_sg_descriptor *descriptor)
@@ -441,7 +439,7 @@ static bool dma_xilinx_axi_dma_channel_has_error(
 
 	return error;
 }
-#pragma GCC diagnostic pop
+TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER)
 
 static int
 dma_xilinx_axi_dma_clean_up_sg_descriptors(const struct device *dev,
@@ -522,12 +520,11 @@ dma_xilinx_axi_dma_clean_up_sg_descriptors(const struct device *dev,
 		processed_packets++;
 	}
 
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Waddress-of-packed-member"
+	TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER);
 	/* this clears the IRQ */
 	/* FIXME write the same value back... */
 	dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->dmasr, 0xffffffff);
-#pragma GCC diagnostic pop
+	TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER);
 
 	/* writes must commit before returning from ISR */
 	barrier_dmem_fence_full();
@@ -615,8 +612,7 @@ static int dma_xilinx_axi_dma_start(const struct device *dev, uint32_t channel)
 		channel == XILINX_AXI_DMA_TX_CHANNEL_NUM ? "TX" : "RX", tail_descriptor,
 		channel_data->current_transfer_end_index);
 
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Waddress-of-packed-member"
+	TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER);
 	if (dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &
 	    XILINX_AXI_DMA_REGS_DMASR_HALTED) {
 
@@ -636,7 +632,7 @@ static int dma_xilinx_axi_dma_start(const struct device *dev, uint32_t channel)
 					     (uint32_t)(uintptr_t)first_unprocessed_descriptor);
 #endif
 	}
-#pragma GCC diagnostic pop
+	TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER);
 
 	/* current descriptor MUST be set before tail descriptor */
 	barrier_dmem_fence_full();
@@ -669,8 +665,7 @@ static int dma_xilinx_axi_dma_start(const struct device *dev, uint32_t channel)
 
 		LOG_DBG("New DMACR value: %" PRIx32, new_control);
 
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Waddress-of-packed-member"
+		TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER);
 		dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->dmacr, new_control);
 		/* need to make sure start was committed before writing tail */
 		barrier_dmem_fence_full();
@@ -685,7 +680,7 @@ static int dma_xilinx_axi_dma_start(const struct device *dev, uint32_t channel)
 	dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->taildesc,
 				     (uint32_t)(uintptr_t)current_descriptor);
 #endif
-#pragma GCC diagnostic pop
+	TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER);
 
 	dma_xilinx_axi_dma_enable_cache();
 
@@ -717,10 +712,9 @@ static int dma_xilinx_axi_dma_stop(const struct device *dev, uint32_t channel)
 	/* RS = 0 --> DMA will complete ongoing transactions and then go into hold */
 	new_control = new_control & ~XILINX_AXI_DMA_REGS_DMACR_RS;
 
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Waddress-of-packed-member"
+	TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER);
 	dma_xilinx_axi_dma_write_reg(&channel_data->channel_regs->dmacr, new_control);
-#pragma GCC diagnostic pop
+	TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER);
 
 	/* commit before returning to caller */
 	barrier_dmem_fence_full();
@@ -743,13 +737,12 @@ static int dma_xilinx_axi_dma_get_status(const struct device *dev, uint32_t chan
 
 	memset(stat, 0, sizeof(*stat));
 
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Waddress-of-packed-member"
+	TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER);
 	stat->busy = !(dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &
 		       XILINX_AXI_DMA_REGS_DMASR_IDLE) &&
 		     !(dma_xilinx_axi_dma_read_reg(&channel_data->channel_regs->dmasr) &
 		       XILINX_AXI_DMA_REGS_DMASR_HALTED);
-#pragma GCC diagnostic pop
+	TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER);
 	stat->dir = channel_data->last_transfer_direction;
 
 	/* FIXME fill hardware-specific fields */
@@ -944,14 +937,13 @@ static int dma_xilinx_axi_dma_configure(const struct device *dev, uint32_t chann
 
 	if (!data->device_has_been_reset) {
 		LOG_INF("Soft-resetting the DMA core!");
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Waddress-of-packed-member"
+		TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER);
 		/* this resets BOTH RX and TX channels, although it is triggered in per-channel
 		 * DMACR
 		 */
 		dma_xilinx_axi_dma_write_reg(&data->channels[channel].channel_regs->dmacr,
 					     XILINX_AXI_DMA_REGS_DMACR_RESET);
-#pragma GCC diagnostic pop
+		TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER);
 		data->device_has_been_reset = true;
 	}
 
diff --git a/drivers/dma/dma_xmc4xxx.c b/drivers/dma/dma_xmc4xxx.c
index f5483280f6b..44217a46c37 100644
--- a/drivers/dma/dma_xmc4xxx.c
+++ b/drivers/dma/dma_xmc4xxx.c
@@ -24,6 +24,12 @@ LOG_MODULE_REGISTER(dma_xmc4xxx, CONFIG_DMA_LOG_LEVEL);
 #define DLR_SRSEL_RS_BITSIZE 4
 #define DLR_SRSEL_RS_MSK     0xf
 
+#define MULTI_BLOCK_NUM_CHANNELS 2
+
+#define XMC_DMA_CTLL_MEMORY_TO_MEMORY     0
+#define XMC_DMA_CTLL_MEMORY_TO_PERIPHERAL 1
+#define XMC_DMA_CTLL_PERIPHERAL_TO_MEMORY 2
+
 #define ALL_EVENTS                                                                                 \
 	(XMC_DMA_CH_EVENT_TRANSFER_COMPLETE | XMC_DMA_CH_EVENT_BLOCK_TRANSFER_COMPLETE |           \
 	 XMC_DMA_CH_EVENT_SRC_TRANSACTION_COMPLETE | XMC_DMA_CH_EVENT_DST_TRANSACTION_COMPLETE |   \
@@ -32,11 +38,33 @@ LOG_MODULE_REGISTER(dma_xmc4xxx, CONFIG_DMA_LOG_LEVEL);
 struct dma_xmc4xxx_channel {
 	dma_callback_t cb;
 	void *user_data;
-	uint16_t block_ts;
+	uint32_t dest_address;
+	uint32_t transfer_size;
 	uint8_t source_data_size;
 	uint8_t dlr_line;
+	uint8_t channel_direction;
+	uint8_t dest_addr_adj;
+	bool multi_block;
+};
+
+struct dma_xmc4xxx_descriptor {
+	uint32_t sar;   /* source address */
+	uint32_t dar;   /* destination address */
+	uint32_t llp;   /* linked-list pointer to the next descriptor or null if last descriptor */
+	uint32_t ctll;  /* control register low  */
+	uint32_t ctlh;  /* control register high */
+	uint32_t dstat; /* status register fetched from address DSTATAR after block completes*/
+} __packed;
+
+struct dma_xmc4xxx_scatter_gather {
+	bool enabled;
+	uint32_t interval;
+	uint16_t count;
 };
 
+static struct dma_xmc4xxx_descriptor descriptor_list[MULTI_BLOCK_NUM_CHANNELS]
+						    [CONFIG_DMA_XMC4XXX_NUM_DESCRIPTORS];
+
 struct dma_xmc4xxx_config {
 	XMC_DMA_t *dma;
 	void (*irq_configure)(void);
@@ -62,7 +90,7 @@ do {
 		if (dma_channel->cb) {                                                     \
 			dma_channel->cb(dev, dma_channel->user_data, channel, (ret));      \
 		}                                                                          \
-}                                                                                          \
+	}                                                                                  \
 } while (0)
 
 /* Isr is level triggered, so we don't have to loop over all the channels */
@@ -120,6 +148,54 @@ static void dma_xmc4xxx_isr(const struct device *dev)
 	}
 }
 
+static uint32_t dma_xmc4xxx_reg_ctll(struct dma_block_config *block, struct dma_config *config)
+{
+	uint32_t ctll;
+
+	ctll = config->dest_data_size / 2 << GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos |
+	       config->source_data_size / 2 << GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos |
+	       block->dest_addr_adj << GPDMA0_CH_CTLL_DINC_Pos |
+	       block->source_addr_adj << GPDMA0_CH_CTLL_SINC_Pos |
+	       config->dest_burst_length / 4 << GPDMA0_CH_CTLL_DEST_MSIZE_Pos |
+	       config->source_burst_length / 4 << GPDMA0_CH_CTLL_SRC_MSIZE_Pos |
+	       BIT(GPDMA0_CH_CTLL_INT_EN_Pos);
+
+	/* Only GPDMA flow controller supported */
+	if (config->channel_direction == MEMORY_TO_PERIPHERAL) {
+		ctll |= XMC_DMA_CTLL_MEMORY_TO_PERIPHERAL << GPDMA0_CH_CTLL_TT_FC_Pos;
+	}
+
+	if (config->channel_direction == PERIPHERAL_TO_MEMORY) {
+		ctll |= XMC_DMA_CTLL_PERIPHERAL_TO_MEMORY << GPDMA0_CH_CTLL_TT_FC_Pos;
+	}
+
+	if (block->source_gather_en && block->source_gather_count > 0) {
+		ctll |= BIT(GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos);
+	}
+
+	if (block->dest_scatter_en && block->dest_scatter_count > 0) {
+		ctll |= BIT(GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos);
+	}
+
+	return ctll;
+}
+
+#define SET_CHECK_SCATTER_GATHER(type)                                                             \
+	do {                                                                                       \
+		if (block->type##_en && block->type##_count > 0 && !type.enabled) {                \
+			type.enabled = true;                                                       \
+			type.interval = block->type##_interval;                                    \
+			type.count = block->type##_count;                                          \
+		} else if (block->type##_en && type.enabled) {                                     \
+			if (block->type##_interval != type.interval ||                             \
+			    block->type##_count != type.count) {                                   \
+				LOG_ERR(STRINGIFY(type) " parameters must be consistent "          \
+							"across enabled blocks");                  \
+				return -EINVAL;                                                    \
+			}                                                                          \
+		}                                                                                  \
+	} while (0)
+
 static int dma_xmc4xxx_config(const struct device *dev, uint32_t channel, struct dma_config *config)
 {
 	struct dma_xmc4xxx_data *dev_data = dev->data;
@@ -127,6 +203,8 @@ static int dma_xmc4xxx_config(const struct device *dev, uint32_t channel, struct
 	struct dma_block_config *block = config->head_block;
 	XMC_DMA_t *dma = dev_cfg->dma;
 	uint8_t dlr_line = DLR_LINE_UNSET;
+	struct dma_xmc4xxx_scatter_gather source_gather = { 0 };
+	struct dma_xmc4xxx_scatter_gather dest_scatter = { 0 };
 
 	if (channel >= dev_data->ctx.dma_channels) {
 		LOG_ERR("Invalid channel number");
@@ -150,14 +228,16 @@ static int dma_xmc4xxx_config(const struct device *dev, uint32_t channel, struct
 		return -EINVAL;
 	}
 
-	if (config->block_count != 1) {
-		LOG_ERR("Invalid block count");
+	if (config->block_count > CONFIG_DMA_XMC4XXX_NUM_DESCRIPTORS) {
+		LOG_ERR("Block count exceeds descriptor array size");
 		return -EINVAL;
 	}
 
-	if (block->source_gather_en || block->dest_scatter_en) {
-		if (dma != XMC_DMA0 || channel >= 2) {
-			LOG_ERR("Gather/scatter only supported on DMA0 on ch0 and ch1");
+	if (block->source_gather_en || block->dest_scatter_en || config->block_count != 1 ||
+	    config->cyclic) {
+		if ((uint32_t)dma != (uint32_t)XMC_DMA0 || channel >= 2) {
+			LOG_ERR("Multi-block, cyclic and gather/scatter only supported on DMA0 on "
+				"ch0 and ch1");
 			return -EINVAL;
 		}
 	}
@@ -199,24 +279,70 @@ static int dma_xmc4xxx_config(const struct device *dev, uint32_t channel, struct
 	XMC_DMA_CH_ClearEventStatus(dma, channel, ALL_EVENTS);
 
 	/* check dma slot number */
-	dma->CH[channel].SAR = block->source_address;
-	dma->CH[channel].DAR = block->dest_address;
-	dma->CH[channel].LLP = 0;
+	if (config->block_count == 1 && config->cyclic == 0) {
+		uint32_t ctll;
+
+		dma->CH[channel].SAR = block->source_address;
+		dma->CH[channel].DAR = block->dest_address;
+		dma->CH[channel].LLP = 0;
+
+		/* set number of transactions */
+		dma->CH[channel].CTLH = block->block_size / config->source_data_size;
+
+		ctll = dma_xmc4xxx_reg_ctll(block, config);
+
+		SET_CHECK_SCATTER_GATHER(source_gather);
+		SET_CHECK_SCATTER_GATHER(dest_scatter);
+
+		dma->CH[channel].CTLL = ctll;
+
+	} else {
+		struct dma_xmc4xxx_descriptor *desc;
+
+		dma->CH[channel].LLP = (uint32_t)&descriptor_list[channel][0];
+		dma->CH[channel].CTLL = BIT(GPDMA0_CH_CTLL_LLP_DST_EN_Pos) |
+					BIT(GPDMA0_CH_CTLL_LLP_SRC_EN_Pos);
+		for (int i = 0; i < config->block_count; i++) {
+			uint32_t ctll;
+
+			desc = &descriptor_list[channel][i];
+
+			desc->sar = block->source_address;
+			desc->dar = block->dest_address;
+			desc->ctlh = block->block_size / config->source_data_size;
+
+			ctll = dma_xmc4xxx_reg_ctll(block, config);
+
+			if (i < config->block_count - 1) {
+				desc->llp = (uint32_t)&descriptor_list[channel][i + 1];
+			} else if (config->cyclic) {
+				desc->llp = (uint32_t)&descriptor_list[channel][0];
+			} else {
+				desc->llp = 0;
+			}
+
+			if (i < config->block_count - 1 || config->cyclic) {
+				ctll |= BIT(GPDMA0_CH_CTLL_LLP_DST_EN_Pos) |
+					BIT(GPDMA0_CH_CTLL_LLP_SRC_EN_Pos);
+			}
+
+			desc->ctll = ctll;
+
+			SET_CHECK_SCATTER_GATHER(source_gather);
+			SET_CHECK_SCATTER_GATHER(dest_scatter);
+
+			block = block->next_block;
+		}
+	}
+
+	block = config->head_block;
 
-	/* set number of transactions */
-	dma->CH[channel].CTLH = block->block_size / config->source_data_size;
 	/* set priority and software handshaking for src/dst. if hardware hankshaking is used */
 	/* it will be enabled later in the code */
 	dma->CH[channel].CFGL = (config->channel_priority << GPDMA0_CH_CFGL_CH_PRIOR_Pos) |
 				GPDMA0_CH_CFGL_HS_SEL_SRC_Msk | GPDMA0_CH_CFGL_HS_SEL_DST_Msk;
 
-	dma->CH[channel].CTLL = config->dest_data_size / 2 << GPDMA0_CH_CTLL_DST_TR_WIDTH_Pos |
-				config->source_data_size / 2 << GPDMA0_CH_CTLL_SRC_TR_WIDTH_Pos |
-				block->dest_addr_adj << GPDMA0_CH_CTLL_DINC_Pos |
-				block->source_addr_adj << GPDMA0_CH_CTLL_SINC_Pos |
-				config->dest_burst_length / 4 << GPDMA0_CH_CTLL_DEST_MSIZE_Pos |
-				config->source_burst_length / 4 << GPDMA0_CH_CTLL_SRC_MSIZE_Pos |
-				BIT(GPDMA0_CH_CTLL_INT_EN_Pos);
+	dma->CH[channel].CFGH = 0;
 
 	if (config->channel_direction == MEMORY_TO_PERIPHERAL ||
 	    config->channel_direction == PERIPHERAL_TO_MEMORY) {
@@ -224,13 +350,13 @@ static int dma_xmc4xxx_config(const struct device *dev, uint32_t channel, struct
 		uint8_t dlr_line_reg = XMC4XXX_DMA_GET_LINE(config->dma_slot);
 
 		dlr_line = dlr_line_reg;
-		if (dma == XMC_DMA0 && dlr_line > 7) {
+		if ((uint32_t)dma == (uint32_t)XMC_DMA0 && dlr_line > 7) {
 			LOG_ERR("Unsupported request line %d for DMA0."
 					"Should be in range [0,7]", dlr_line);
 			return -EINVAL;
 		}
 
-		if (dma == XMC_DMA1 && (dlr_line < 8 || dlr_line > 11)) {
+		if ((uint32_t)dma == (uint32_t)XMC_DMA1 && (dlr_line < 8 || dlr_line > 11)) {
 			LOG_ERR("Unsupported request line %d for DMA1."
 					"Should be in range [8,11]", dlr_line);
 			return -EINVAL;
@@ -243,12 +369,12 @@ static int dma_xmc4xxx_config(const struct device *dev, uint32_t channel, struct
 		DLR->LNEN |= BIT(dlr_line);
 
 		/* connect DMA Line to SR */
-		if (dma == XMC_DMA0) {
+		if ((uint32_t)dma == (uint32_t)XMC_DMA0) {
 			DLR->SRSEL0 &= ~(DLR_SRSEL_RS_MSK << (dlr_line_reg * DLR_SRSEL_RS_BITSIZE));
 			DLR->SRSEL0 |= request_source << (dlr_line_reg * DLR_SRSEL_RS_BITSIZE);
 		}
 
-		if (dma == XMC_DMA1) {
+		if ((uint32_t)dma == (uint32_t)XMC_DMA1) {
 			dlr_line_reg -= 8;
 			DLR->SRSEL1 &= ~(DLR_SRSEL_RS_MSK << (dlr_line_reg * DLR_SRSEL_RS_BITSIZE));
 			DLR->SRSEL1 |= request_source << (dlr_line_reg * DLR_SRSEL_RS_BITSIZE);
@@ -258,35 +384,52 @@ static int dma_xmc4xxx_config(const struct device *dev, uint32_t channel, struct
 		if (config->channel_direction == MEMORY_TO_PERIPHERAL) {
 			dma->CH[channel].CFGH = (dlr_line_reg << GPDMA0_CH_CFGH_DEST_PER_Pos) | 4;
 			dma->CH[channel].CFGL &= ~BIT(GPDMA0_CH_CFGL_HS_SEL_DST_Pos);
-			dma->CH[channel].CTLL |= 1 << GPDMA0_CH_CTLL_TT_FC_Pos;
 		}
 
 		if (config->channel_direction == PERIPHERAL_TO_MEMORY) {
 			dma->CH[channel].CFGH = (dlr_line_reg << GPDMA0_CH_CFGH_SRC_PER_Pos) | 4;
 			dma->CH[channel].CFGL &= ~BIT(GPDMA0_CH_CFGL_HS_SEL_SRC_Pos);
-			dma->CH[channel].CTLL |= 2 << GPDMA0_CH_CTLL_TT_FC_Pos;
 		}
 	}
 
-	if (block->source_gather_en) {
-		dma->CH[channel].CTLL |= BIT(GPDMA0_CH_CTLL_SRC_GATHER_EN_Pos);
+	if (block->fifo_mode_control > 0) {
+		dma->CH[channel].CFGH |= GPDMA0_CH_CFGH_FIFO_MODE_Msk;
+	}
+
+	if ((uint32_t)dma == (uint32_t)XMC_DMA0) {
+		if (channel == 0 || channel == 1) {
+			/* reset scatter/gather registers */
+			dma->CH[channel].SGR = 0;
+			dma->CH[channel].DSR = 0;
+		}
+	}
+
+	if (source_gather.enabled) {
 		/* truncate if we are out of range */
-		dma->CH[channel].SGR = (block->source_gather_interval & GPDMA0_CH_SGR_SGI_Msk) |
-				       block->source_gather_count << GPDMA0_CH_SGR_SGC_Pos;
+		dma->CH[channel].SGR = (source_gather.interval & GPDMA0_CH_SGR_SGI_Msk) |
+				       source_gather.count << GPDMA0_CH_SGR_SGC_Pos;
 	}
 
-	if (block->dest_scatter_en) {
-		dma->CH[channel].CTLL |= BIT(GPDMA0_CH_CTLL_DST_SCATTER_EN_Pos);
+	if (dest_scatter.enabled) {
 		/* truncate if we are out of range */
-		dma->CH[channel].DSR = (block->dest_scatter_interval & GPDMA0_CH_DSR_DSI_Msk) |
-				       block->dest_scatter_count << GPDMA0_CH_DSR_DSC_Pos;
+		dma->CH[channel].DSR = (dest_scatter.interval & GPDMA0_CH_DSR_DSI_Msk) |
+				       dest_scatter.count << GPDMA0_CH_DSR_DSC_Pos;
 	}
 
 	dev_data->channels[channel].cb = config->dma_callback;
 	dev_data->channels[channel].user_data = config->user_data;
-	dev_data->channels[channel].block_ts = block->block_size / config->source_data_size;
+	dev_data->channels[channel].transfer_size = block->block_size;
 	dev_data->channels[channel].source_data_size = config->source_data_size;
 	dev_data->channels[channel].dlr_line = dlr_line;
+	dev_data->channels[channel].channel_direction = config->channel_direction;
+	dev_data->channels[channel].dest_addr_adj = block->dest_addr_adj;
+	dev_data->channels[channel].dest_address = block->dest_address;
+
+	if (config->block_count > 1) {
+		dev_data->channels[channel].multi_block = true;
+	} else {
+		dev_data->channels[channel].multi_block = false;
+	}
 
 	XMC_DMA_CH_DisableEvent(dma, channel, ALL_EVENTS);
 	XMC_DMA_CH_EnableEvent(dma, channel, XMC_DMA_CH_EVENT_TRANSFER_COMPLETE);
@@ -309,8 +452,14 @@ static int dma_xmc4xxx_config(const struct device *dev, uint32_t channel, struct
 static int dma_xmc4xxx_start(const struct device *dev, uint32_t channel)
 {
 	const struct dma_xmc4xxx_config *dev_cfg = dev->config;
+	struct dma_xmc4xxx_data *dev_data = dev->data;
+	uint8_t dlr_line = dev_data->channels[channel].dlr_line;
 
 	LOG_DBG("Starting channel %d", channel);
+	if (dlr_line != DLR_LINE_UNSET && (DLR->LNEN & BIT(dlr_line)) == 0) {
+		DLR->LNEN |= BIT(dlr_line);
+	}
+
 	XMC_DMA_CH_Enable(dev_cfg->dma, channel);
 	return 0;
 }
@@ -335,10 +484,8 @@ static int dma_xmc4xxx_stop(const struct device *dev, uint32_t channel)
 		DLR->LNEN &= ~BIT(dma_channel->dlr_line);
 	}
 
-	dma_channel->dlr_line = DLR_LINE_UNSET;
-	dma_channel->cb = NULL;
-
 	XMC_DMA_CH_Disable(dma, channel);
+	XMC_DMA_CH_Resume(dma, channel);
 	return 0;
 }
 
@@ -367,7 +514,8 @@ static int dma_xmc4xxx_reload(const struct device *dev, uint32_t channel, uint32
 		LOG_ERR("Block transactions must be <= 4095");
 		return -EINVAL;
 	}
-	dma_channel->block_ts = block_ts;
+	dma_channel->transfer_size = size;
+	dma_channel->dest_address = dst;
 
 	/* do we need to clear any errors */
 	dma->CH[channel].SAR = src;
@@ -384,6 +532,7 @@ static int dma_xmc4xxx_get_status(const struct device *dev, uint32_t channel,
 	const struct dma_xmc4xxx_config *dev_cfg = dev->config;
 	XMC_DMA_t *dma = dev_cfg->dma;
 	struct dma_xmc4xxx_channel *dma_channel;
+	uint32_t transferred_bytes;
 
 	if (channel >= dev_data->ctx.dma_channels) {
 		LOG_ERR("Invalid channel number");
@@ -393,8 +542,27 @@ static int dma_xmc4xxx_get_status(const struct device *dev, uint32_t channel,
 
 	stat->busy = XMC_DMA_CH_IsEnabled(dma, channel);
 
-	stat->pending_length  = dma_channel->block_ts - XMC_DMA_CH_GetTransferredData(dma, channel);
-	stat->pending_length *= dma_channel->source_data_size;
+	if (dma_channel->multi_block) {
+		/* not supported for multi-block transfers */
+		stat->pending_length = 0;
+		return 0;
+	}
+
+	/* Use DAR to check for transferred bytes when possible. Value CTL.BLOCK_TS does not */
+	/* appear to guarantee that the last value is fully transferred to dest. */
+	if (dma_channel->dest_addr_adj == DMA_ADDR_ADJ_INCREMENT) {
+		transferred_bytes = dma->CH[channel].DAR - dma_channel->dest_address;
+		stat->pending_length = dma_channel->transfer_size - transferred_bytes;
+	} else if (dma_channel->dest_addr_adj == DMA_ADDR_ADJ_DECREMENT) {
+		transferred_bytes =  dma_channel->dest_address - dma->CH[channel].DAR;
+		stat->pending_length = dma_channel->transfer_size - transferred_bytes;
+	} else {
+		uint32_t num_source_transfers = XMC_DMA_CH_GetTransferredData(dma, channel);
+
+		stat->pending_length = dma_channel->transfer_size -
+				       num_source_transfers * dma_channel->source_data_size;
+	}
+
 	/* stat->dir and other remaining fields are not set. They are not */
 	/* useful for xmc4xxx peripheral drivers. */
 
diff --git a/drivers/eeprom/CMakeLists.txt b/drivers/eeprom/CMakeLists.txt
index c7b5f65c21f..b22380fdde8 100644
--- a/drivers/eeprom/CMakeLists.txt
+++ b/drivers/eeprom/CMakeLists.txt
@@ -19,7 +19,7 @@ if(CONFIG_EEPROM_SIMULATOR)
   endif()
 endif()
 zephyr_library_sources_ifdef(CONFIG_EEPROM_EMULATOR eeprom_emulator.c)
-zephyr_library_sources_ifdef(CONFIG_EEPROM_TMP116 eeprom_tmp116.c)
+zephyr_library_sources_ifdef(CONFIG_EEPROM_TMP11X eeprom_tmp11x.c)
 zephyr_library_sources_ifdef(CONFIG_EEPROM_XEC eeprom_mchp_xec.c)
 zephyr_library_sources_ifdef(CONFIG_EEPROM_FAKE eeprom_fake.c)
 
diff --git a/drivers/eeprom/Kconfig b/drivers/eeprom/Kconfig
index cf1cefb5505..02e7fc9eba2 100644
--- a/drivers/eeprom/Kconfig
+++ b/drivers/eeprom/Kconfig
@@ -96,7 +96,7 @@ config EEPROM_AT2X_INIT_PRIORITY
 source "drivers/eeprom/Kconfig.lpc11u6x"
 source "drivers/eeprom/Kconfig.stm32"
 source "drivers/eeprom/Kconfig.eeprom_emu"
-source "drivers/eeprom/Kconfig.tmp116"
+source "drivers/eeprom/Kconfig.tmp11x"
 source "drivers/eeprom/Kconfig.xec"
 source "drivers/eeprom/Kconfig.mb85rcxx"
 source "drivers/eeprom/Kconfig.mb85rsxx"
diff --git a/drivers/eeprom/Kconfig.tmp116 b/drivers/eeprom/Kconfig.tmp116
deleted file mode 100644
index 86db689f265..00000000000
--- a/drivers/eeprom/Kconfig.tmp116
+++ /dev/null
@@ -1,11 +0,0 @@
-# Copyright (c) 2021 Innoseis B.V.
-# SPDX-License-Identifier: Apache-2.0
-
-config EEPROM_TMP116
-	bool "TMP116 EEPROM driver"
-	default y
-	depends on DT_HAS_TI_TMP116_EEPROM_ENABLED
-	depends on TMP116
-	help
-	  Enable support for the on-chip EEPROM found on
-	  Texas instrument TMP116 temperature sensor
diff --git a/drivers/eeprom/Kconfig.tmp11x b/drivers/eeprom/Kconfig.tmp11x
new file mode 100644
index 00000000000..6325523e492
--- /dev/null
+++ b/drivers/eeprom/Kconfig.tmp11x
@@ -0,0 +1,11 @@
+# Copyright (c) 2021 Innoseis B.V.
+# SPDX-License-Identifier: Apache-2.0
+
+config EEPROM_TMP11X
+	bool "TMP116, TMP117 and TMP119 EEPROM driver"
+	default y
+	depends on DT_HAS_TI_TMP11X_EEPROM_ENABLED
+	depends on TMP11X
+	help
+	  Enable support for the on-chip EEPROM found on
+	  Texas instrument TMP116, TMP117 and TMP119 temperature sensor
diff --git a/drivers/eeprom/eeprom_shell.c b/drivers/eeprom/eeprom_shell.c
index 6f32e98efe9..be0539780ba 100644
--- a/drivers/eeprom/eeprom_shell.c
+++ b/drivers/eeprom/eeprom_shell.c
@@ -213,10 +213,15 @@ static int cmd_fill(const struct shell *sh, size_t argc, char **argv)
 	return 0;
 }
 
+static bool device_is_eeprom(const struct device *dev)
+{
+	return DEVICE_API_IS(eeprom, dev);
+}
+
 /* Device name autocompletion support */
 static void device_name_get(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_lookup(idx, NULL);
+	const struct device *dev = shell_device_filter(idx, device_is_eeprom);
 
 	entry->syntax = (dev != NULL) ? dev->name : NULL;
 	entry->handler = NULL;
diff --git a/drivers/eeprom/eeprom_stm32.c b/drivers/eeprom/eeprom_stm32.c
index cc096247c16..a3288fe3dc6 100644
--- a/drivers/eeprom/eeprom_stm32.c
+++ b/drivers/eeprom/eeprom_stm32.c
@@ -91,8 +91,6 @@ static int eeprom_stm32_write(const struct device *dev, off_t offset,
 	ret = HAL_FLASHEx_DATAEEPROM_Lock();
 	if (ret) {
 		LOG_ERR("failed to lock EEPROM (err %d)", ret);
-		k_mutex_unlock(&lock);
-		return ret;
 	}
 
 	k_mutex_unlock(&lock);
diff --git a/drivers/eeprom/eeprom_tmp116.c b/drivers/eeprom/eeprom_tmp116.c
deleted file mode 100644
index 5a959aa9b32..00000000000
--- a/drivers/eeprom/eeprom_tmp116.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2020 Innoseis B.V
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <errno.h>
-
-#include <zephyr/devicetree.h>
-#include <zephyr/drivers/eeprom.h>
-#include <zephyr/drivers/sensor/tmp116.h>
-
-#define DT_DRV_COMPAT ti_tmp116_eeprom
-
-struct eeprom_tmp116_config {
-	const struct device *parent;
-};
-
-BUILD_ASSERT(CONFIG_EEPROM_INIT_PRIORITY >
-	     CONFIG_SENSOR_INIT_PRIORITY,
-	     "TMP116 eeprom driver must be initialized after TMP116 sensor "
-	     "driver");
-
-static size_t eeprom_tmp116_size(const struct device *dev)
-{
-	return EEPROM_TMP116_SIZE;
-}
-
-static int eeprom_tmp116_write(const struct device *dev, off_t offset,
-			       const void *data, size_t len)
-{
-	const struct eeprom_tmp116_config *config = dev->config;
-
-	return tmp116_eeprom_write(config->parent, offset, data, len);
-}
-
-static int eeprom_tmp116_read(const struct device *dev, off_t offset, void *data,
-			      size_t len)
-{
-	const struct eeprom_tmp116_config *config = dev->config;
-
-	return tmp116_eeprom_read(config->parent, offset, data, len);
-}
-
-static int eeprom_tmp116_init(const struct device *dev)
-{
-	const struct eeprom_tmp116_config *config = dev->config;
-
-	if (!device_is_ready(config->parent)) {
-		return -ENODEV;
-	}
-
-	return 0;
-}
-
-static DEVICE_API(eeprom, eeprom_tmp116_api) = {
-	.read = eeprom_tmp116_read,
-	.write = eeprom_tmp116_write,
-	.size = eeprom_tmp116_size,
-};
-
-#define DEFINE_TMP116(_num)						       \
-	static const struct eeprom_tmp116_config eeprom_tmp116_config##_num = { \
-		.parent =  DEVICE_DT_GET(DT_INST_BUS(_num))		       \
-	};								       \
-	DEVICE_DT_INST_DEFINE(_num, eeprom_tmp116_init, NULL,		       \
-			      NULL, &eeprom_tmp116_config##_num, POST_KERNEL,   \
-			      CONFIG_EEPROM_INIT_PRIORITY, &eeprom_tmp116_api);
-
-DT_INST_FOREACH_STATUS_OKAY(DEFINE_TMP116);
diff --git a/drivers/eeprom/eeprom_tmp11x.c b/drivers/eeprom/eeprom_tmp11x.c
new file mode 100644
index 00000000000..1966683ee6d
--- /dev/null
+++ b/drivers/eeprom/eeprom_tmp11x.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2020 Innoseis B.V
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/eeprom.h>
+#include <zephyr/drivers/sensor/tmp11x.h>
+
+#define DT_DRV_COMPAT ti_tmp11x_eeprom
+
+struct eeprom_tmp11x_config {
+	const struct device *parent;
+};
+
+BUILD_ASSERT(CONFIG_EEPROM_INIT_PRIORITY >
+	     CONFIG_SENSOR_INIT_PRIORITY,
+	     "TMP11X eeprom driver must be initialized after TMP11X sensor "
+	     "driver");
+
+static size_t eeprom_tmp11x_size(const struct device *dev)
+{
+	return EEPROM_TMP11X_SIZE;
+}
+
+static int eeprom_tmp11x_write(const struct device *dev, off_t offset,
+			       const void *data, size_t len)
+{
+	const struct eeprom_tmp11x_config *config = dev->config;
+
+	return tmp11x_eeprom_write(config->parent, offset, data, len);
+}
+
+static int eeprom_tmp11x_read(const struct device *dev, off_t offset, void *data,
+			      size_t len)
+{
+	const struct eeprom_tmp11x_config *config = dev->config;
+
+	return tmp11x_eeprom_read(config->parent, offset, data, len);
+}
+
+static int eeprom_tmp11x_init(const struct device *dev)
+{
+	const struct eeprom_tmp11x_config *config = dev->config;
+
+	if (!device_is_ready(config->parent)) {
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(eeprom, eeprom_tmp11x_api) = {
+	.read = eeprom_tmp11x_read,
+	.write = eeprom_tmp11x_write,
+	.size = eeprom_tmp11x_size,
+};
+
+#define DEFINE_TMP11X(_num)						       \
+	static const struct eeprom_tmp11x_config eeprom_tmp11x_config##_num = { \
+		.parent =  DEVICE_DT_GET(DT_INST_BUS(_num))		       \
+	};								       \
+	DEVICE_DT_INST_DEFINE(_num, eeprom_tmp11x_init, NULL,		       \
+			      NULL, &eeprom_tmp11x_config##_num, POST_KERNEL,   \
+			      CONFIG_EEPROM_INIT_PRIORITY, &eeprom_tmp11x_api);
+
+DT_INST_FOREACH_STATUS_OKAY(DEFINE_TMP11X);
diff --git a/drivers/entropy/CMakeLists.txt b/drivers/entropy/CMakeLists.txt
index e23b558a6a9..37a5999bd91 100644
--- a/drivers/entropy/CMakeLists.txt
+++ b/drivers/entropy/CMakeLists.txt
@@ -11,13 +11,15 @@ zephyr_library_sources_ifdef(CONFIG_ENTROPY_MCUX_RNG           entropy_mcux_rng.
 zephyr_library_sources_ifdef(CONFIG_ENTROPY_MCUX_RNGA          entropy_mcux_rnga.c)
 zephyr_library_sources_ifdef(CONFIG_ENTROPY_MCUX_TRNG          entropy_mcux_trng.c)
 zephyr_library_sources_ifdef(CONFIG_ENTROPY_MCUX_CAAM          entropy_mcux_caam.c)
+zephyr_library_sources_ifdef(CONFIG_ENTROPY_NXP_ELE_TRNG       entropy_nxp_ele.c)
 zephyr_library_sources_ifdef(CONFIG_ENTROPY_NRF5_RNG           entropy_nrf5.c)
+zephyr_library_sources_ifdef(CONFIG_ENTROPY_NRF_CRACEN_CTR_DRBG entropy_nrf_cracen.c)
 zephyr_library_sources_ifdef(CONFIG_ENTROPY_SAM_RNG            entropy_sam.c)
 zephyr_library_sources_ifdef(CONFIG_ENTROPY_SMARTBOND_TRNG     entropy_smartbond.c)
 zephyr_library_sources_ifdef(CONFIG_ENTROPY_STM32_RNG          entropy_stm32.c)
 zephyr_library_sources_ifdef(CONFIG_ENTROPY_LITEX_RNG          entropy_litex.c)
-if(CONFIG_FAKE_ENTROPY_NATIVE_POSIX)
-  zephyr_library_sources(fake_entropy_native_posix.c)
+if(CONFIG_FAKE_ENTROPY_NATIVE_SIM)
+  zephyr_library_sources(fake_entropy_native_sim.c)
   if(CONFIG_NATIVE_LIBRARY)
     target_sources(native_simulator INTERFACE fake_entropy_native_bottom.c)
   else()
@@ -31,10 +33,13 @@ zephyr_library_sources_ifdef(CONFIG_ENTROPY_GECKO_TRNG      entropy_gecko_trng.c
 zephyr_library_sources_ifdef(CONFIG_ENTROPY_NEORV32_TRNG    entropy_neorv32_trng.c)
 zephyr_library_sources_ifdef(CONFIG_ENTROPY_BT_HCI          entropy_bt_hci.c)
 zephyr_library_sources_ifdef(CONFIG_ENTROPY_GECKO_SE        entropy_gecko_se.c)
+zephyr_library_sources_ifdef(CONFIG_ENTROPY_SILABS_SIWX91X  entropy_silabs_siwx91x.c)
 zephyr_library_sources_ifdef(CONFIG_ENTROPY_PSA_CRYPTO_RNG  entropy_psa_crypto.c)
 zephyr_library_sources_ifdef(CONFIG_ENTROPY_NPCX_DRBG       entropy_npcx_drbg.c)
 zephyr_library_sources_ifdef(CONFIG_ENTROPY_MAX32_TRNG      entropy_max32.c)
+zephyr_library_sources_ifdef(CONFIG_ENTROPY_MAXQ10XX_RNG    entropy_maxq10xx.c)
 zephyr_library_sources_ifdef(CONFIG_ENTROPY_RENESAS_RA      entropy_renesas_ra.c)
+zephyr_library_sources_ifdef(CONFIG_ENTROPY_SY1XX_TRNG      entropy_sy1xx_trng.c)
 
 if (CONFIG_FAKE_ENTROPY_NRF_PRNG)
   zephyr_library_sources(fake_entropy_nrf_prng.c)
diff --git a/drivers/entropy/Kconfig b/drivers/entropy/Kconfig
index 40571df47f1..3d31282ad78 100644
--- a/drivers/entropy/Kconfig
+++ b/drivers/entropy/Kconfig
@@ -23,21 +23,26 @@ config ENTROPY_INIT_PRIORITY
 source "drivers/entropy/Kconfig.b91"
 source "drivers/entropy/Kconfig.cc13xx_cc26xx"
 source "drivers/entropy/Kconfig.mcux"
+source "drivers/entropy/Kconfig.nxp"
 source "drivers/entropy/Kconfig.stm32"
 source "drivers/entropy/Kconfig.esp32"
 source "drivers/entropy/Kconfig.nrf5"
+source "drivers/entropy/Kconfig.nrf_cracen"
 source "drivers/entropy/Kconfig.sam"
 source "drivers/entropy/Kconfig.smartbond"
-source "drivers/entropy/Kconfig.native_posix"
+source "drivers/entropy/Kconfig.native_sim"
 source "drivers/entropy/Kconfig.rv32m1"
 source "drivers/entropy/Kconfig.litex"
 source "drivers/entropy/Kconfig.gecko"
+source "drivers/entropy/Kconfig.siwx91x"
 source "drivers/entropy/Kconfig.neorv32"
 source "drivers/entropy/Kconfig.bt_hci"
 source "drivers/entropy/Kconfig.psa_crypto"
 source "drivers/entropy/Kconfig.npcx"
 source "drivers/entropy/Kconfig.max32"
+source "drivers/entropy/Kconfig.maxq10xx"
 source "drivers/entropy/Kconfig.renesas_ra"
+source "drivers/entropy/Kconfig.sy1xx"
 source "drivers/entropy/Kconfig.nrf_prng"
 
 config ENTROPY_HAS_DRIVER
diff --git a/drivers/entropy/Kconfig.maxq10xx b/drivers/entropy/Kconfig.maxq10xx
new file mode 100644
index 00000000000..3e18b761eac
--- /dev/null
+++ b/drivers/entropy/Kconfig.maxq10xx
@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Vogl Electronic GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+config ENTROPY_MAXQ10XX_RNG
+	bool "MAXQ10xx entropy number generator driver"
+	default y
+	depends on DT_HAS_ADI_MAXQ10XX_TRNG_ENABLED
+	select ENTROPY_HAS_DRIVER
+	select SPI
+	select MFD
+	select CRC
+	help
+	  This option enables the entropy number generator driver for the
+	  MAXQ10xx crypto chips.
+
+# Don't use use the MAXQ10XX RNG as a random source since it can be quite slow.
+# Instead, use the software-implemented xoshiro PRNG.
+choice RNG_GENERATOR_CHOICE
+	default XOSHIRO_RANDOM_GENERATOR if ENTROPY_MAXQ10XX_RNG
+endchoice
diff --git a/drivers/entropy/Kconfig.native_posix b/drivers/entropy/Kconfig.native_posix
deleted file mode 100644
index 39298c444df..00000000000
--- a/drivers/entropy/Kconfig.native_posix
+++ /dev/null
@@ -1,23 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-config FAKE_ENTROPY_NATIVE_POSIX
-	bool "Native posix entropy driver"
-	default y
-	depends on DT_HAS_ZEPHYR_NATIVE_POSIX_RNG_ENABLED
-	select ENTROPY_HAS_DRIVER
-	help
-	  This option enables the test random number generator for the
-	  native_posix board (ARCH_POSIX). This is based on the host random() API.
-	  Note that this entropy generator is only meant for test purposes and does
-	  not generate real entropy.
-	  It actually generates always the same sequence of random numbers if
-	  initialized with the same seed.
-
-config FAKE_ENTROPY_NATIVE_POSIX_SEED_BY_DEFAULT
-	bool "Seed the generator by default"
-	default y
-	depends on FAKE_ENTROPY_NATIVE_POSIX
-	help
-	  Apply a seed by default, even if the user does not request it through the command line.
-	  Disabling this feature allows some other component to seed the host standard library random
-	  generator without this component's default initialization interfering.
diff --git a/drivers/entropy/Kconfig.native_sim b/drivers/entropy/Kconfig.native_sim
new file mode 100644
index 00000000000..adcf3f407cd
--- /dev/null
+++ b/drivers/entropy/Kconfig.native_sim
@@ -0,0 +1,37 @@
+# SPDX-License-Identifier: Apache-2.0
+
+config FAKE_ENTROPY_NATIVE_SIM
+	bool "Native simulator entropy driver"
+	default y
+	depends on DT_HAS_ZEPHYR_NATIVE_POSIX_RNG_ENABLED || DT_HAS_ZEPHYR_NATIVE_SIM_RNG_ENABLED
+	select ENTROPY_HAS_DRIVER
+	help
+	  This option enables the test random number generator for the
+	  native_sim board (ARCH_POSIX). This is based on the host random() API.
+	  Note that this entropy generator is only meant for test purposes and does
+	  not generate real entropy.
+	  It actually generates always the same sequence of random numbers if
+	  initialized with the same seed.
+
+config FAKE_ENTROPY_NATIVE_SIM_SEED_BY_DEFAULT
+	bool "Seed the generator by default"
+	default y
+	depends on FAKE_ENTROPY_NATIVE_SIM
+	help
+	  Apply a seed by default, even if the user does not request it through the command line.
+	  Disabling this feature allows some other component to seed the host standard library random
+	  generator without this component's default initialization interfering.
+
+config FAKE_ENTROPY_NATIVE_POSIX
+	bool "Native posix entropy driver (deprecated)"
+	select FAKE_ENTROPY_NATIVE_SIM
+	select DEPRECATED
+	help
+	  Deprecated option in favour of FAKE_ENTROPY_NATIVE_SIM
+
+config FAKE_ENTROPY_NATIVE_POSIX_SEED_BY_DEFAULT
+	bool "Seed the generator by default (deprecated)"
+	depends on FAKE_ENTROPY_NATIVE_POSIX
+	select DEPRECATED
+	help
+	  Deprecated option. Replaced by FAKE_ENTROPY_NATIVE_SIM_SEED_BY_DEFAULT
diff --git a/drivers/entropy/Kconfig.nrf_cracen b/drivers/entropy/Kconfig.nrf_cracen
new file mode 100644
index 00000000000..8941096a126
--- /dev/null
+++ b/drivers/entropy/Kconfig.nrf_cracen
@@ -0,0 +1,17 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config ENTROPY_NRF_CRACEN_CTR_DRBG
+	bool "nRF entropy driver based on the CRACEN CTR_DRBG driver"
+	default y
+	depends on DT_HAS_NORDIC_NRF_CRACEN_CTRDRBG_ENABLED
+	depends on SOC_COMPATIBLE_NRF54LX
+	select ENTROPY_HAS_DRIVER
+	select NRFX_CRACEN
+	help
+	  This option enables the 54L CRACEN based entropy driver, based on the nrfx CRACEN CTR_DRBG
+	  random driver.
+	  Notes: This driver is only compatible with 54L devices, and may only be used from one processor
+	  core. This driver cannot be used in conjunction with the nRF security PSA solution, as both
+	  would attempt to use the CRACEN HW exclusively; When that is enabled, the PSA crypto entropy
+	  driver should be selected instead.
diff --git a/drivers/entropy/Kconfig.nxp b/drivers/entropy/Kconfig.nxp
new file mode 100644
index 00000000000..895ff59dd76
--- /dev/null
+++ b/drivers/entropy/Kconfig.nxp
@@ -0,0 +1,12 @@
+# NXP ELE entropy configuration options
+
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config ENTROPY_NXP_ELE_TRNG
+	bool "NXP ELE TRNG driver"
+	default y
+	depends on DT_HAS_NXP_ELE_TRNG_ENABLED
+	select ENTROPY_HAS_DRIVER
+	help
+	  This option enables the ELE true random number generator (TRNG)
diff --git a/drivers/entropy/Kconfig.renesas_ra b/drivers/entropy/Kconfig.renesas_ra
index c6220f6cb0f..fc5b14dc315 100644
--- a/drivers/entropy/Kconfig.renesas_ra
+++ b/drivers/entropy/Kconfig.renesas_ra
@@ -6,8 +6,9 @@
 config ENTROPY_RENESAS_RA
 	bool "Renesas RA TRNG driver"
 	default y
-	depends on DT_HAS_RENESAS_RA_RSIP_E51A_TRNG_ENABLED || DT_HAS_RENESAS_RA_SCE7_RNG_ENABLED \
-		|| DT_HAS_RENESAS_RA_SCE5_RNG_ENABLED || DT_HAS_RENESAS_RA_TRNG_ENABLED
+	depends on DT_HAS_RENESAS_RA_RSIP_E51A_TRNG_ENABLED || DT_HAS_RENESAS_RA_SCE9_RNG_ENABLED \
+		|| DT_HAS_RENESAS_RA_SCE7_RNG_ENABLED || DT_HAS_RENESAS_RA_SCE5_RNG_ENABLED       \
+		|| DT_HAS_RENESAS_RA_TRNG_ENABLED
 	select ENTROPY_HAS_DRIVER
 	select USE_RA_FSP_SCE
 	help
diff --git a/drivers/entropy/Kconfig.siwx91x b/drivers/entropy/Kconfig.siwx91x
new file mode 100644
index 00000000000..e8a45fea10c
--- /dev/null
+++ b/drivers/entropy/Kconfig.siwx91x
@@ -0,0 +1,11 @@
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config ENTROPY_SILABS_SIWX91X
+	bool "SiWx91x RNG driver"
+	default y
+	depends on DT_HAS_SILABS_SIWX91X_RNG_ENABLED
+	select ENTROPY_HAS_DRIVER
+	help
+	 Enable hardware Random Number Generator embedded on Silicon Labs
+	 SiWx91x chips.
diff --git a/drivers/entropy/Kconfig.stm32 b/drivers/entropy/Kconfig.stm32
index 1772b16c93f..7c9cfc441a7 100644
--- a/drivers/entropy/Kconfig.stm32
+++ b/drivers/entropy/Kconfig.stm32
@@ -6,9 +6,8 @@
 menuconfig ENTROPY_STM32_RNG
 	bool "STM32 RNG driver"
 	default y
-	depends on DT_HAS_ST_STM32_RNG_ENABLED
+	depends on DT_HAS_ST_STM32_RNG_ENABLED || DT_HAS_ST_STM32_RNG_NOIRQ_ENABLED
 	select ENTROPY_HAS_DRIVER
-	select USE_STM32_LL_RNG
 	help
 	  This option enables the RNG processor, which is a entropy number
 	  generator, based on a continuous analog noise, that provides
@@ -55,6 +54,7 @@ config ENTROPY_STM32_ISR_THRESHOLD
 
 config ENTROPY_STM32_CLK_CHECK
 	bool "Runtime clock configuration check"
+	depends on !SOC_SERIES_STM32WB0X
 	default y
 	help
 	  Enables a check on RNG clock configuration. Correct clock
diff --git a/drivers/entropy/Kconfig.sy1xx b/drivers/entropy/Kconfig.sy1xx
new file mode 100644
index 00000000000..bf40abe45b3
--- /dev/null
+++ b/drivers/entropy/Kconfig.sy1xx
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+config ENTROPY_SY1XX_TRNG
+	bool "Sensry sy1xx soc family true random number generator (TRNG) driver"
+	default y
+	depends on DT_HAS_SENSRY_SY1XX_TRNG_ENABLED
+	select ENTROPY_HAS_DRIVER
diff --git a/drivers/entropy/entropy_esp32.c b/drivers/entropy/entropy_esp32.c
index ddcf961fe4a..ab0c4e81c26 100644
--- a/drivers/entropy/entropy_esp32.c
+++ b/drivers/entropy/entropy_esp32.c
@@ -20,6 +20,26 @@
 
 LOG_MODULE_REGISTER(entropy, CONFIG_ENTROPY_LOG_LEVEL);
 
+#if SOC_LP_TIMER_SUPPORTED
+#include "hal/lp_timer_hal.h"
+#endif
+
+#if defined CONFIG_SOC_SERIES_ESP32S3
+/* If APB clock is 80 MHz, the maximum sampling frequency is around 45 KHz */
+/* 45 KHz reading frequency is the maximum we have tested so far on S3 */
+#define APB_CYCLE_WAIT_NUM (1778)
+#elif defined CONFIG_SOC_SERIES_ESP32C6
+/* On ESP32C6, we only read one byte at a time, then XOR the value with
+ * an asynchronous timer (see code below).
+ * The current value translates to a sampling frequency of around 62.5 KHz
+ * for reading 8 bit samples, which is the rate at which the RNG was tested,
+ * plus additional overhead for the calculation, making it slower.
+ */
+#define APB_CYCLE_WAIT_NUM (160 * 16)
+#else
+#define APB_CYCLE_WAIT_NUM (16)
+#endif
+
 static inline uint32_t entropy_esp32_get_u32(void)
 {
 	/* The PRNG which implements WDEV_RANDOM register gets 2 bits
@@ -30,18 +50,29 @@ static inline uint32_t entropy_esp32_get_u32(void)
 	 * wait a bit longer due to extra time spent in arithmetic and branch statements.
 	 */
 
-	uint32_t cpu_to_apb_freq_ratio =
-		esp_clk_cpu_freq() / esp_clk_apb_freq();
+	uint32_t cpu_to_apb_freq_ratio = esp_clk_cpu_freq() / esp_clk_apb_freq();
 
 	static uint32_t last_ccount;
 	uint32_t ccount;
-
+	uint32_t result = 0;
+#if SOC_LP_TIMER_SUPPORTED
+	for (size_t i = 0; i < sizeof(result); i++) {
+		do {
+			ccount = esp_cpu_get_cycle_count();
+			result ^= REG_READ(WDEV_RND_REG);
+		} while (ccount - last_ccount < cpu_to_apb_freq_ratio * APB_CYCLE_WAIT_NUM);
+		uint32_t current_rtc_timer_counter = (lp_timer_hal_get_cycle_count() & 0xFF);
+
+		result ^= ((result ^ current_rtc_timer_counter) & 0xFF) << (i * 8);
+	}
+#else
 	do {
 		ccount = esp_cpu_get_cycle_count();
-	} while (ccount - last_ccount < cpu_to_apb_freq_ratio * 16);
+		result ^= REG_READ(WDEV_RND_REG);
+	} while (ccount - last_ccount < cpu_to_apb_freq_ratio * APB_CYCLE_WAIT_NUM);
+#endif
 	last_ccount = ccount;
-
-	return REG_READ(WDEV_RND_REG);
+	return result ^ REG_READ(WDEV_RND_REG);
 }
 
 static int entropy_esp32_get_entropy(const struct device *dev, uint8_t *buf,
diff --git a/drivers/entropy/entropy_maxq10xx.c b/drivers/entropy/entropy_maxq10xx.c
new file mode 100644
index 00000000000..d20e798330a
--- /dev/null
+++ b/drivers/entropy/entropy_maxq10xx.c
@@ -0,0 +1,224 @@
+/*
+ * Copyright (c) 2025 Vogl Electronic GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT adi_maxq10xx_trng
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/drivers/entropy.h>
+#include <zephyr/drivers/mfd/mfd_maxq10xx.h>
+#include <zephyr/sys/crc.h>
+#include <zephyr/sys/byteorder.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(entropy_maxq10xx, CONFIG_ENTROPY_LOG_LEVEL);
+
+#define MAXQ10XX_CMD_HEADER                0xAA
+#define MAXQ10XX_CMD_GET_RANDOM            0xC9
+#define MAXQ10XX_CMD_GET_RANDOM_INPUT_DATA 0x02
+#define MAXQ10XX_CMD_READ_READY            0x55
+
+#define MAXQ10XX_CRC16_POLYNOMIAL    0xA001
+#define MAXQ10XX_CRC16_INITIAL_VALUE 0x0000
+
+#define MAXQ10XX_WAIT_TIME K_MSEC(1)
+
+struct entropy_maxq10xx_config {
+	struct spi_dt_spec spi;
+	const struct device *parent;
+};
+
+static int entropy_maxq10xx_send_cmd(const struct device *dev, uint16_t length)
+{
+	const struct entropy_maxq10xx_config *config = dev->config;
+
+	uint8_t buffer_tx[9];
+	uint16_t crc;
+	int ret;
+
+	buffer_tx[0] = MAXQ10XX_CMD_HEADER;
+	buffer_tx[1] = 0x00;
+	buffer_tx[2] = MAXQ10XX_CMD_GET_RANDOM;
+	buffer_tx[3] = 0x00;
+	buffer_tx[4] = MAXQ10XX_CMD_GET_RANDOM_INPUT_DATA;
+
+	sys_put_be16(length, &buffer_tx[5]);
+
+	crc = crc16_reflect(MAXQ10XX_CRC16_POLYNOMIAL, MAXQ10XX_CRC16_INITIAL_VALUE, buffer_tx, 7);
+
+	sys_put_le16(crc, &buffer_tx[7]);
+
+	const struct spi_buf tx_buf[] = {{
+		.buf = buffer_tx,
+		.len = ARRAY_SIZE(buffer_tx),
+	}};
+	const struct spi_buf_set tx = {
+		.buffers = tx_buf,
+		.count = ARRAY_SIZE(tx_buf),
+	};
+
+	LOG_HEXDUMP_DBG(buffer_tx, sizeof(buffer_tx), "TX buffer");
+
+	ret = spi_write_dt(&config->spi, &tx);
+
+	return ret;
+}
+
+static int entropy_maxq10xx_wait(const struct device *dev)
+{
+	const struct entropy_maxq10xx_config *config = dev->config;
+	uint8_t buffer_rx[1];
+	int ret;
+
+	const struct spi_buf rx_buf[] = {{
+		.buf = buffer_rx,
+		.len = ARRAY_SIZE(buffer_rx),
+	}};
+	const struct spi_buf_set rx = {
+		.buffers = rx_buf,
+		.count = ARRAY_SIZE(rx_buf),
+	};
+
+	while (1) {
+		ret = spi_read_dt(&config->spi, &rx);
+		if ((ret < 0) || (buffer_rx[0] == MAXQ10XX_CMD_READ_READY)) {
+			break;
+		}
+
+		k_sleep(MAXQ10XX_WAIT_TIME);
+	};
+
+	return ret;
+}
+
+static int entropy_maxq10xx_read(const struct device *dev, uint8_t *buffer, uint16_t length)
+{
+	const struct entropy_maxq10xx_config *config = dev->config;
+	uint8_t execution_status[2];
+	uint8_t length_data[2];
+	uint8_t crc[2];
+	uint16_t crc_calc;
+	int ret;
+
+	const struct spi_buf rx_buf[] = {
+		{
+			.buf = execution_status,
+			.len = ARRAY_SIZE(execution_status),
+		},
+		{
+			.buf = length_data,
+			.len = ARRAY_SIZE(length_data),
+		}
+	};
+	const struct spi_buf_set rx = {
+		.buffers = rx_buf,
+		.count = ARRAY_SIZE(rx_buf),
+	};
+
+	ret = spi_read_dt(&config->spi, &rx);
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (execution_status[0] != 0 || execution_status[1] != 0) {
+		LOG_ERR("Execution status: 0x%02X 0x%02X", execution_status[0],
+			execution_status[1]);
+		return -EIO;
+	}
+
+	if (length != sys_get_be16(length_data)) {
+		LOG_ERR("Length mismatch: %d != %d", length, sys_get_be16(length_data));
+		return -EIO;
+	}
+
+	const struct spi_buf rx_data_buf[] = {
+		{
+			.buf = buffer,
+			.len = length,
+		},
+		{
+			.buf = crc,
+			.len = sizeof(crc),
+		}
+	};
+
+	const struct spi_buf_set rx_data = {
+		.buffers = rx_data_buf,
+		.count = ARRAY_SIZE(rx_data_buf),
+	};
+
+	ret = spi_read_dt(&config->spi, &rx_data);
+	if (ret < 0) {
+		return ret;
+	}
+
+	uint8_t header_tx[1] = {MAXQ10XX_CMD_READ_READY};
+
+	crc_calc = crc16_reflect(MAXQ10XX_CRC16_POLYNOMIAL, MAXQ10XX_CRC16_INITIAL_VALUE, header_tx,
+				 sizeof(header_tx));
+	crc_calc = crc16_reflect(MAXQ10XX_CRC16_POLYNOMIAL, crc_calc, execution_status,
+				 sizeof(execution_status));
+	crc_calc = crc16_reflect(MAXQ10XX_CRC16_POLYNOMIAL, crc_calc, length_data,
+				 sizeof(length_data));
+	crc_calc = crc16_reflect(MAXQ10XX_CRC16_POLYNOMIAL, crc_calc, buffer, length);
+
+	if (crc_calc != sys_get_le16(crc)) {
+		LOG_ERR("CRC error: 0x%04X != 0x%04X", crc_calc, sys_get_le16(crc));
+		return -EIO;
+	}
+
+	return ret;
+}
+
+static int entropy_maxq10xx_get_entropy(const struct device *dev, uint8_t *buffer, uint16_t length)
+{
+	const struct entropy_maxq10xx_config *config = dev->config;
+	struct k_sem *sem_lock = mfd_maxq10xx_get_lock(config->parent);
+
+	int ret;
+
+	if (!spi_is_ready_dt(&config->spi)) {
+		return -EAGAIN;
+	}
+
+	k_sem_take(sem_lock, K_FOREVER);
+
+	ret = entropy_maxq10xx_send_cmd(dev, length);
+	if (ret < 0) {
+		LOG_ERR("Failed to send command: %d", ret);
+		goto exit;
+	}
+
+	ret = entropy_maxq10xx_wait(dev);
+	if (ret < 0) {
+		LOG_ERR("Failed to wait for ready: %d", ret);
+		goto exit;
+	}
+
+	ret = entropy_maxq10xx_read(dev, buffer, length);
+	if (ret < 0) {
+		LOG_ERR("Failed to read data: %d", ret);
+	}
+exit:
+	k_sem_give(sem_lock);
+	return ret;
+}
+
+static DEVICE_API(entropy, entropy_maxq10xx_api) = {
+	.get_entropy = entropy_maxq10xx_get_entropy
+};
+
+#define DEFINE_MAXQ10XX_ENTROPY(_num)                                                              \
+	static const struct entropy_maxq10xx_config entropy_maxq10xx_config##_num = {              \
+		.spi = SPI_DT_SPEC_GET(DT_INST_PARENT(_num), SPI_WORD_SET(8), 0),                  \
+		.parent = DEVICE_DT_GET(DT_INST_PARENT(_num)),                                     \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(_num, NULL, NULL, NULL,                                              \
+			      &entropy_maxq10xx_config##_num, POST_KERNEL,                         \
+			      CONFIG_MFD_MAXQ10XX_INIT_PRIORITY, &entropy_maxq10xx_api);
+
+DT_INST_FOREACH_STATUS_OKAY(DEFINE_MAXQ10XX_ENTROPY);
diff --git a/drivers/entropy/entropy_mcux_trng.c b/drivers/entropy/entropy_mcux_trng.c
index be542daddec..d541c5fbea4 100644
--- a/drivers/entropy/entropy_mcux_trng.c
+++ b/drivers/entropy/entropy_mcux_trng.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2017 Linaro Limited.
+ * Copyright 2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,6 +10,7 @@
 #include <zephyr/device.h>
 #include <zephyr/drivers/entropy.h>
 #include <zephyr/random/random.h>
+#include <zephyr/pm/device.h>
 #include <zephyr/init.h>
 
 #include "fsl_trng.h"
@@ -53,8 +55,29 @@ static int entropy_mcux_trng_init(const struct device *dev)
 	return 0;
 }
 
+#ifdef CONFIG_PM_DEVICE
+static int entropy_mcux_trng_pm_action(const struct device *dev, enum pm_device_action action)
+{
+	switch (action) {
+	case PM_DEVICE_ACTION_RESUME:
+		break;
+	case PM_DEVICE_ACTION_SUSPEND:
+		break;
+	case PM_DEVICE_ACTION_TURN_OFF:
+		break;
+	case PM_DEVICE_ACTION_TURN_ON:
+		entropy_mcux_trng_init(dev);
+		break;
+	default:
+		return -ENOTSUP;
+	}
+	return 0;
+}
+#endif /*CONFIG_PM_DEVICE*/
+
+PM_DEVICE_DT_INST_DEFINE(0, entropy_mcux_trng_pm_action);
 DEVICE_DT_INST_DEFINE(0,
-		    entropy_mcux_trng_init, NULL, NULL,
+		    entropy_mcux_trng_init, PM_DEVICE_DT_INST_GET(0), NULL,
 		    &entropy_mcux_config,
 		    PRE_KERNEL_1, CONFIG_ENTROPY_INIT_PRIORITY,
 		    &entropy_mcux_trng_api_funcs);
diff --git a/drivers/entropy/entropy_neorv32_trng.c b/drivers/entropy/entropy_neorv32_trng.c
index b33de87d7f1..8869b0e2a80 100644
--- a/drivers/entropy/entropy_neorv32_trng.c
+++ b/drivers/entropy/entropy_neorv32_trng.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
+ * Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,10 +17,19 @@
 
 LOG_MODULE_REGISTER(neorv32_trng, CONFIG_ENTROPY_LOG_LEVEL);
 
-/* TRNG CTRL register bits */
-#define NEORV32_TRNG_CTRL_DATA_MASK BIT_MASK(8)
-#define NEORV32_TRNG_CTRL_EN        BIT(30)
-#define NEORV32_TRNG_CTRL_VALID     BIT(31)
+/* Register offsets */
+#define NEORV32_TRNG_CTRL 0x00
+#define NEORV32_TRNG_DATA 0x04
+
+/* CTRL register bits */
+#define NEORV32_TRNG_CTRL_EN         BIT(0)
+#define NEORV32_TRNG_CTRL_FIFO_CLR   BIT(1)
+#define NEORV32_TRNG_CTRL_FIFO_DEPTH GENMASK(5, 2)
+#define NEORV32_TRNG_CTRL_SIM_MODE   BIT(6)
+#define NEORV32_TRNG_CTRL_AVAIL      BIT(7)
+
+/* DATA register bits */
+#define NEORV32_TRNG_DATA_MASK GENMASK(7, 0)
 
 struct neorv32_trng_config {
 	const struct device *syscon;
@@ -31,14 +40,21 @@ static inline uint32_t neorv32_trng_read_ctrl(const struct device *dev)
 {
 	const struct neorv32_trng_config *config = dev->config;
 
-	return sys_read32(config->base);
+	return sys_read32(config->base + NEORV32_TRNG_CTRL);
 }
 
 static inline void neorv32_trng_write_ctrl(const struct device *dev, uint32_t ctrl)
 {
 	const struct neorv32_trng_config *config = dev->config;
 
-	sys_write32(ctrl, config->base);
+	sys_write32(ctrl, config->base + NEORV32_TRNG_CTRL);
+}
+
+static inline uint8_t neorv32_trng_read_data(const struct device *dev)
+{
+	const struct neorv32_trng_config *config = dev->config;
+
+	return sys_read32(config->base + NEORV32_TRNG_DATA) & NEORV32_TRNG_DATA_MASK;
 }
 
 static int neorv32_trng_get_entropy(const struct device *dev, uint8_t *buffer, uint16_t len)
@@ -48,8 +64,8 @@ static int neorv32_trng_get_entropy(const struct device *dev, uint8_t *buffer, u
 	while (len > 0) {
 		ctrl = neorv32_trng_read_ctrl(dev);
 
-		if ((ctrl & NEORV32_TRNG_CTRL_VALID) != 0) {
-			*buffer++ = ctrl & NEORV32_TRNG_CTRL_DATA_MASK;
+		if ((ctrl & NEORV32_TRNG_CTRL_AVAIL) != 0) {
+			*buffer++ = neorv32_trng_read_data(dev);
 			len--;
 		}
 	}
@@ -65,8 +81,8 @@ static int neorv32_trng_get_entropy_isr(const struct device *dev, uint8_t *buffe
 
 	if ((flags & ENTROPY_BUSYWAIT) == 0) {
 		ctrl = neorv32_trng_read_ctrl(dev);
-		if ((ctrl & NEORV32_TRNG_CTRL_VALID) != 0) {
-			*buffer = ctrl & NEORV32_TRNG_CTRL_DATA_MASK;
+		if ((ctrl & NEORV32_TRNG_CTRL_AVAIL) != 0) {
+			*buffer = neorv32_trng_read_data(dev);
 			return 1;
 		}
 
@@ -93,13 +109,13 @@ static int neorv32_trng_init(const struct device *dev)
 		return -EINVAL;
 	}
 
-	err = syscon_read_reg(config->syscon, NEORV32_SYSINFO_FEATURES, &features);
+	err = syscon_read_reg(config->syscon, NEORV32_SYSINFO_SOC, &features);
 	if (err < 0) {
 		LOG_ERR("failed to determine implemented features (err %d)", err);
 		return err;
 	}
 
-	if ((features & NEORV32_SYSINFO_FEATURES_IO_TRNG) == 0) {
+	if ((features & NEORV32_SYSINFO_SOC_IO_TRNG) == 0) {
 		LOG_ERR("neorv32 trng not supported");
 		return -ENODEV;
 	}
diff --git a/drivers/entropy/entropy_nrf_cracen.c b/drivers/entropy/entropy_nrf_cracen.c
new file mode 100644
index 00000000000..8c34a06db61
--- /dev/null
+++ b/drivers/entropy/entropy_nrf_cracen.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nrfx_cracen.h>
+#include <zephyr/irq.h>
+#include <zephyr/drivers/entropy.h>
+
+#define DT_DRV_COMPAT nordic_nrf_cracen_ctrdrbg
+
+static int nrf_cracen_get_entropy_isr(const struct device *dev, uint8_t *buf, uint16_t len,
+				      uint32_t flags)
+{
+	(void)dev;
+	(void)flags;
+
+	unsigned int key = irq_lock();
+
+	/* This will take approximately 2 + (ceil(len/16) + 3)*3 us. i.e. 14us for 16 bytes */
+	int ret = nrfx_cracen_ctr_drbg_random_get(buf, len);
+
+	irq_unlock(key);
+
+	if (likely(ret == NRFX_SUCCESS)) {
+		return len;
+	} else if (ret == NRFX_ERROR_INVALID_PARAM) {
+		return -EINVAL;
+	} else {
+		return -EAGAIN;
+	}
+}
+
+static int nrf_cracen_get_entropy(const struct device *dev, uint8_t *buf, uint16_t len)
+{
+	int ret = nrf_cracen_get_entropy_isr(dev, buf, len, 0);
+
+	if (ret < 0) {
+		return ret;
+	} else {
+		return 0;
+	}
+}
+
+static int nrf_cracen_cracen_init(const struct device *dev)
+{
+	(void)dev;
+
+	int ret = nrfx_cracen_ctr_drbg_init();
+
+	if (ret == NRFX_SUCCESS) {
+		return 0;
+	} else {
+		return -EIO;
+	}
+}
+
+static DEVICE_API(entropy, nrf_cracen_api_funcs) = {
+	.get_entropy = nrf_cracen_get_entropy,
+	.get_entropy_isr = nrf_cracen_get_entropy_isr
+};
+
+DEVICE_DT_INST_DEFINE(0, nrf_cracen_cracen_init, NULL, NULL, NULL, PRE_KERNEL_1,
+		      CONFIG_ENTROPY_INIT_PRIORITY, &nrf_cracen_api_funcs);
diff --git a/drivers/entropy/entropy_nxp_ele.c b/drivers/entropy/entropy_nxp_ele.c
new file mode 100644
index 00000000000..8d8e037de7f
--- /dev/null
+++ b/drivers/entropy/entropy_nxp_ele.c
@@ -0,0 +1,71 @@
+/* entropy_nxp_ele.c - NXP ELE entropy driver */
+
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_ele_trng
+
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/entropy.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/util.h>
+#include <soc.h>
+
+#include "sss_crypto.h"
+
+struct entropy_ele_data_str {
+	struct k_sem sem_lock;
+};
+
+static struct entropy_ele_data_str entropy_ele_data;
+
+static int entropy_ele_get_entropy(const struct device *dev, uint8_t *buf, uint16_t len)
+{
+	sss_sscp_rng_t ctx;
+	int result = -EIO;
+
+	__ASSERT_NO_MSG(buf != NULL);
+	__ASSERT_NO_MSG(&entropy_ele_data == dev->data);
+
+	k_sem_take(&entropy_ele_data.sem_lock, K_FOREVER);
+
+	if (CRYPTO_InitHardware() != kStatus_Success) {
+		goto exit;
+	}
+
+	if (sss_sscp_rng_context_init(&g_sssSession, &ctx, 0u) != kStatus_SSS_Success) {
+		goto exit;
+	}
+
+	if (sss_sscp_rng_get_random(&ctx, buf, len) != kStatus_SSS_Success) {
+		goto exit;
+	}
+
+	if (sss_sscp_rng_free(&ctx) != kStatus_SSS_Success) {
+		goto exit;
+	}
+
+	result = 0;
+
+exit:
+	k_sem_give(&entropy_ele_data.sem_lock);
+	return result;
+}
+
+static int entropy_ele_init(const struct device *dev)
+{
+	__ASSERT_NO_MSG(&entropy_ele_data == dev->data);
+
+	k_sem_init(&entropy_ele_data.sem_lock, 1, 1);
+
+	return 0;
+}
+
+static DEVICE_API(entropy, entropy_ele_api_funcs) = {.get_entropy = entropy_ele_get_entropy};
+
+DEVICE_DT_INST_DEFINE(0, entropy_ele_init, NULL, &entropy_ele_data, NULL, PRE_KERNEL_1,
+		      CONFIG_ENTROPY_INIT_PRIORITY, &entropy_ele_api_funcs);
diff --git a/drivers/entropy/entropy_renesas_ra.c b/drivers/entropy/entropy_renesas_ra.c
index 7510679e376..4ac70c17142 100644
--- a/drivers/entropy/entropy_renesas_ra.c
+++ b/drivers/entropy/entropy_renesas_ra.c
@@ -50,4 +50,5 @@ static int entropy_renesas_ra_init(const struct device *dev)
 DT_FOREACH_STATUS_OKAY(renesas_ra_rsip_e51a_trng, RENESAS_RA_ENTROPY_INIT)
 DT_FOREACH_STATUS_OKAY(renesas_ra_sce5_rng, RENESAS_RA_ENTROPY_INIT)
 DT_FOREACH_STATUS_OKAY(renesas_ra_sce7_rng, RENESAS_RA_ENTROPY_INIT)
+DT_FOREACH_STATUS_OKAY(renesas_ra_sce9_rng, RENESAS_RA_ENTROPY_INIT)
 DT_FOREACH_STATUS_OKAY(renesas_ra_trng, RENESAS_RA_ENTROPY_INIT)
diff --git a/drivers/entropy/entropy_silabs_siwx91x.c b/drivers/entropy/entropy_silabs_siwx91x.c
new file mode 100644
index 00000000000..bb4a256daee
--- /dev/null
+++ b/drivers/entropy/entropy_silabs_siwx91x.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#define DT_DRV_COMPAT silabs_siwx91x_rng
+
+#include <zephyr/drivers/entropy.h>
+
+#include "rsi_rom_rng.h"
+#include "rsi_rom_clks.h"
+
+static int siwx91x_get_entropy_isr(const struct device *dev, uint8_t *buffer,
+				   uint16_t length, uint32_t flags)
+{
+	uint32_t u32_count = length / sizeof(uint32_t);
+	uint32_t u8_count = u32_count * sizeof(uint32_t);
+	uint32_t u8_remainder = length - u8_count;
+	uint32_t swap_space;
+
+	if (!(flags & ENTROPY_BUSYWAIT)) {
+		return -ENOTSUP;
+	}
+	RSI_RNG_GetBytes((void *)dev->config, (uint32_t *)buffer, u32_count);
+	if (length % sizeof(uint32_t)) {
+		RSI_RNG_GetBytes((void *)dev->config, &swap_space, 1);
+		memcpy(buffer + u8_count, &swap_space, u8_remainder);
+	}
+
+	return 0;
+}
+
+static int siwx91x_get_entropy(const struct device *dev, uint8_t *buffer, uint16_t length)
+{
+	return siwx91x_get_entropy_isr(dev, buffer, length, ENTROPY_BUSYWAIT);
+}
+
+static int siwx91x_init(const struct device *dev)
+{
+	int ret;
+
+	ret = RSI_CLK_PeripheralClkEnable1(M4CLK, HWRNG_PCLK_ENABLE);
+	if (ret) {
+		return -EIO;
+	}
+	ret = RSI_RNG_Start((void *)dev->config, RSI_RNG_TRUE_RANDOM);
+	if (ret) {
+		return -EIO;
+	}
+	return 0;
+}
+
+static DEVICE_API(entropy, siwx91x_api) = {
+	.get_entropy = siwx91x_get_entropy,
+	.get_entropy_isr = siwx91x_get_entropy_isr,
+};
+
+#define SIWX91X_RNG_INIT(idx)                                                               \
+	DEVICE_DT_INST_DEFINE(idx, siwx91x_init, NULL, NULL, (void *)DT_INST_REG_ADDR(idx), \
+			      PRE_KERNEL_1, CONFIG_ENTROPY_INIT_PRIORITY, &siwx91x_api);
+
+DT_INST_FOREACH_STATUS_OKAY(SIWX91X_RNG_INIT)
diff --git a/drivers/entropy/entropy_stm32.c b/drivers/entropy/entropy_stm32.c
index 2accb94f676..4aa0cf1d9e5 100644
--- a/drivers/entropy/entropy_stm32.c
+++ b/drivers/entropy/entropy_stm32.c
@@ -6,9 +6,6 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-
-#define DT_DRV_COMPAT st_stm32_rng
-
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/drivers/entropy.h>
@@ -32,8 +29,7 @@
 #include <zephyr/sys/barrier.h>
 #include "stm32_hsem.h"
 
-#define IRQN		DT_INST_IRQN(0)
-#define IRQ_PRIO	DT_INST_IRQ(0, priority)
+#include "entropy_stm32.h"
 
 #if defined(RNG_CR_CONDRST)
 #define STM32_CONDRST_SUPPORT
@@ -44,7 +40,7 @@
  *  - simple rng without hardware fifo and no DMA.
  *  - Variable delay between two consecutive random numbers
  *    (depending on family and clock settings)
- *
+ *  - IRQ-less TRNG instances
  *
  * Due to the first byte in a stream of bytes being more costly on
  * some platforms a "water system" inspired algorithm is used to
@@ -57,6 +53,9 @@
  * The entropy level is checked at the end of every consumption of
  * entropy.
  *
+ * For TRNG instances with no IRQ, a delayable work item is scheduled
+ * on the system work queue and used to "simulate" device-generated
+ * interrupts - this is done to reduce polling to a minimum.
  */
 
 struct rng_pool {
@@ -78,6 +77,15 @@ BUILD_ASSERT((CONFIG_ENTROPY_STM32_THR_POOL_SIZE &
 	      (CONFIG_ENTROPY_STM32_THR_POOL_SIZE - 1)) == 0,
 	     "The CONFIG_ENTROPY_STM32_THR_POOL_SIZE must be a power of 2!");
 
+/**
+ * RM0505 §14.4 "TRNG functional description":
+ *  To use the TRNG peripheral the system clock frequency must be
+ *  at least 32 MHz. See also: §6.2.2 "Peripheral clock details".
+ */
+BUILD_ASSERT(!IS_ENABLED(CONFIG_SOC_STM32WB09XX) ||
+		CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= (32 * 1000 * 1000),
+	"STM32WB09: TRNG requires system clock frequency >= 32MHz");
+
 struct entropy_stm32_rng_dev_cfg {
 	struct stm32_pclken *pclken;
 };
@@ -88,6 +96,10 @@ struct entropy_stm32_rng_dev_data {
 	struct k_sem sem_lock;
 	struct k_sem sem_sync;
 	struct k_work filling_work;
+#if IRQLESS_TRNG
+	/* work item that polls TRNG to refill pools */
+	struct k_work_delayable trng_poll_work;
+#endif /* IRQLESS_TRNG */
 	bool filling_pools;
 
 	RNG_POOL_DEFINE(isr, CONFIG_ENTROPY_STM32_ISR_POOL_SIZE);
@@ -117,6 +129,14 @@ static int entropy_stm32_suspend(void)
 	z_stm32_hsem_lock(CFG_HW_RNG_SEMID, HSEM_LOCK_WAIT_FOREVER);
 #endif /* CONFIG_SOC_SERIES_STM32WBX || CONFIG_STM32H7_DUAL_CORE */
 	LL_RNG_Disable(rng);
+#if defined(CONFIG_SOC_STM32WB09XX)
+	/* RM0505 Rev.2 §14.4:
+	 * "After the TRNG IP is disabled by setting CR.DISABLE, in order to
+	 * properly restart the TRNG IP, the AES_RESET bit must be set to 1
+	 * (that is, resetting the AES core and restarting all health tests)."
+	 */
+	LL_RNG_SetAesReset(rng, 1);
+#endif /* CONFIG_SOC_STM32WB09XX */
 
 #ifdef CONFIG_SOC_SERIES_STM32WBAX
 	uint32_t wait_cycles, rng_rate;
@@ -157,8 +177,16 @@ static int entropy_stm32_resume(void)
 
 	res = clock_control_on(dev_data->clock,
 			(clock_control_subsys_t)&dev_cfg->pclken[0]);
+#if defined(CONFIG_SOC_STM32WB09XX)
+	/**
+	 * STM32WB09 RNG clock domain runs at (16 MHz / CLKDIV).
+	 * CLKDIV is 256 after reset which makes the RNG runs VERY slow.
+	 * Configure CLKDIV=1 to ensure RNG runs at an acceptable speed.
+	 */
+	LL_RNG_SetSamplingClockEnableDivider(rng, 0);
+#endif
 	LL_RNG_Enable(rng);
-	LL_RNG_EnableIT(rng);
+	ll_rng_enable_it(rng);
 
 	return res;
 }
@@ -204,15 +232,22 @@ static void configure_rng(void)
 		LL_RNG_SetHealthConfig(rng, desired_htcr);
 #endif /* health_test_config */
 
+#if defined(CONFIG_SOC_SERIES_STM32L4X)
+		LL_RNG_ResetConditioningResetBit(rng);
+		/* Wait for conditioning reset process to be completed */
+		while (LL_RNG_IsResetConditioningBitSet(rng) == 1) {
+		}
+#else
 		LL_RNG_DisableCondReset(rng);
 		/* Wait for conditioning reset process to be completed */
 		while (LL_RNG_IsEnabledCondReset(rng) == 1) {
 		}
+#endif /* CONFIG_SOC_SERIES_STM32L4X */
 	}
 #endif /* STM32_CONDRST_SUPPORT */
 
 	LL_RNG_Enable(rng);
-	LL_RNG_EnableIT(rng);
+	ll_rng_enable_it(rng);
 }
 
 static void acquire_rng(void)
@@ -238,11 +273,13 @@ static int entropy_stm32_got_error(RNG_TypeDef *rng)
 {
 	__ASSERT_NO_MSG(rng != NULL);
 
+#if defined(STM32_CONDRST_SUPPORT)
 	if (LL_RNG_IsActiveFlag_CECS(rng)) {
 		return 1;
 	}
+#endif
 
-	if (LL_RNG_IsActiveFlag_SEIS(rng)) {
+	if (ll_rng_is_active_seis(rng)) {
 		return 1;
 	}
 
@@ -255,15 +292,25 @@ static int recover_seed_error(RNG_TypeDef *rng)
 {
 	uint32_t count_timeout = 0;
 
-	LL_RNG_EnableCondReset(rng);
-	LL_RNG_DisableCondReset(rng);
+#if defined(CONFIG_SOC_SERIES_STM32L4X)
+		LL_RNG_SetConditioningResetBit(rng);
+		LL_RNG_ResetConditioningResetBit(rng);
+#else
+		LL_RNG_EnableCondReset(rng);
+		LL_RNG_DisableCondReset(rng);
+#endif /* CONFIG_SOC_SERIES_STM32L4X */
+
 	/* When reset process is done cond reset bit is read 0
 	 * This typically takes: 2 AHB clock cycles + 2 RNG clock cycles.
 	 */
 
+#if defined(CONFIG_SOC_SERIES_STM32L4X)
+	while (LL_RNG_IsResetConditioningBitSet(rng) ||
+#else
 	while (LL_RNG_IsEnabledCondReset(rng) ||
-		LL_RNG_IsActiveFlag_SEIS(rng) ||
-		LL_RNG_IsActiveFlag_SECS(rng)) {
+#endif /* CONFIG_SOC_SERIES_STM32L4X */
+		ll_rng_is_active_seis(rng) ||
+		ll_rng_is_active_secs(rng)) {
 		count_timeout++;
 		if (count_timeout == 10) {
 			return -ETIMEDOUT;
@@ -277,13 +324,13 @@ static int recover_seed_error(RNG_TypeDef *rng)
 /* SOCS w/o soft-reset support: flush pipeline */
 static int recover_seed_error(RNG_TypeDef *rng)
 {
-	LL_RNG_ClearFlag_SEIS(rng);
+	ll_rng_clear_seis(rng);
 
 	for (int i = 0; i < 12; ++i) {
-		LL_RNG_ReadRandData32(rng);
+		(void)ll_rng_read_rand_data(rng);
 	}
 
-	if (LL_RNG_IsActiveFlag_SEIS(rng) != 0) {
+	if (ll_rng_is_active_seis(rng) != 0) {
 		return -EIO;
 	}
 
@@ -299,7 +346,8 @@ static int random_byte_get(void)
 
 	key = irq_lock();
 
-	if (IS_ENABLED(CONFIG_ENTROPY_STM32_CLK_CHECK) && !k_is_pre_kernel()) {
+#if defined(CONFIG_ENTROPY_STM32_CLK_CHECK)
+	if (!k_is_pre_kernel()) {
 		/* CECS bit signals that a clock configuration issue is detected,
 		 * which may lead to generation of non truly random data.
 		 */
@@ -307,19 +355,20 @@ static int random_byte_get(void)
 			 "CECS = 1: RNG domain clock is too slow.\n"
 			 "\tSee ref man and update target clock configuration.");
 	}
+#endif /* CONFIG_ENTROPY_STM32_CLK_CHECK */
 
-	if (LL_RNG_IsActiveFlag_SEIS(rng) && (recover_seed_error(rng) < 0)) {
+	if (ll_rng_is_active_seis(rng) && (recover_seed_error(rng) < 0)) {
 		retval = -EIO;
 		goto out;
 	}
 
-	if ((LL_RNG_IsActiveFlag_DRDY(rng) == 1)) {
+	if (ll_rng_is_active_drdy(rng) == 1) {
 		if (entropy_stm32_got_error(rng)) {
 			retval = -EIO;
 			goto out;
 		}
 
-		retval = LL_RNG_ReadRandData32(rng);
+		retval = ll_rng_read_rand_data(rng);
 		if (retval == 0) {
 			/* A seed error could have occurred between RNG_SR
 			 * polling and RND_DR output reading.
@@ -342,34 +391,42 @@ static uint16_t generate_from_isr(uint8_t *buf, uint16_t len)
 {
 	uint16_t remaining_len = len;
 
+#if !IRQLESS_TRNG
 	__ASSERT_NO_MSG(!irq_is_enabled(IRQN));
+#endif /* !IRQLESS_TRNG */
 
 #if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_STM32H7_DUAL_CORE)
 	__ASSERT_NO_MSG(z_stm32_hsem_is_owned(CFG_HW_RNG_SEMID));
 #endif /* CONFIG_SOC_SERIES_STM32WBX || CONFIG_STM32H7_DUAL_CORE */
 
 	/* do not proceed if a Seed error occurred */
-	if (LL_RNG_IsActiveFlag_SECS(entropy_stm32_rng_data.rng) ||
-		LL_RNG_IsActiveFlag_SEIS(entropy_stm32_rng_data.rng)) {
+	if (ll_rng_is_active_secs(entropy_stm32_rng_data.rng) ||
+		ll_rng_is_active_seis(entropy_stm32_rng_data.rng)) {
 
 		(void)random_byte_get(); /* this will recover the error */
 
 		return 0; /* return cnt is null : no random data available */
 	}
 
+#if !IRQLESS_TRNG
 	/* Clear NVIC pending bit. This ensures that a subsequent
 	 * RNG event will set the Cortex-M single-bit event register
 	 * to 1 (the bit is set when NVIC pending IRQ status is
 	 * changed from 0 to 1)
 	 */
 	NVIC_ClearPendingIRQ(IRQN);
+#endif /* !IRQLESS_TRNG */
 
 	do {
 		int byte;
 
-		while (LL_RNG_IsActiveFlag_DRDY(
+		while (ll_rng_is_active_drdy(
 				entropy_stm32_rng_data.rng) != 1) {
+#if !IRQLESS_TRNG
 			/*
+			 * Enter low-power mode while waiting for event
+			 * generated by TRNG interrupt becoming pending.
+			 *
 			 * To guarantee waking up from the event, the
 			 * SEV-On-Pend feature must be enabled (enabled
 			 * during ARCH initialization).
@@ -381,10 +438,13 @@ static uint16_t generate_from_isr(uint8_t *buf, uint16_t len)
 			__WFE();
 			__SEV();
 			__WFE();
+#endif /* !IRQLESS_TRNG */
 		}
 
 		byte = random_byte_get();
+#if !IRQLESS_TRNG
 		NVIC_ClearPendingIRQ(IRQN);
+#endif /* IRQLESS_TRNG */
 
 		if (byte < 0) {
 			continue;
@@ -430,8 +490,11 @@ static int start_pool_filling(bool wait)
 	}
 
 	acquire_rng();
+#if IRQLESS_TRNG
+	k_work_schedule(&entropy_stm32_rng_data.trng_poll_work, TRNG_GENERATION_DELAY);
+#else /* !IRQLESS_TRNG */
 	irq_enable(IRQN);
-
+#endif /* IRQLESS_TRNG */
 	return 0;
 }
 
@@ -498,8 +561,11 @@ static uint16_t rng_pool_get(struct rng_pool *rngp, uint8_t *buf,
 		 * Avoid starting pool filling from ISR as it might require
 		 * blocking if RNG is not available and a race condition could
 		 * also occur if this ISR has interrupted the RNG ISR.
+		 *
+		 * If the TRNG has no IRQ line, always schedule the work item,
+		 * as this is what fills the RNG pools instead of the ISR.
 		 */
-		if (k_is_in_isr()) {
+		if (k_is_in_isr() || IRQLESS_TRNG) {
 			k_work_submit(&entropy_stm32_rng_data.filling_work);
 		} else {
 			start_pool_filling(true);
@@ -536,15 +602,13 @@ static void rng_pool_init(struct rng_pool *rngp, uint16_t size,
 	rngp->threshold	  = threshold;
 }
 
-static void stm32_rng_isr(const void *arg)
+static int perform_pool_refill(void)
 {
 	int byte, ret;
 
-	ARG_UNUSED(arg);
-
 	byte = random_byte_get();
 	if (byte < 0) {
-		return;
+		return -EIO;
 	}
 
 	ret = rng_pool_put((struct rng_pool *)(entropy_stm32_rng_data.isr),
@@ -554,7 +618,9 @@ static void stm32_rng_isr(const void *arg)
 				(struct rng_pool *)(entropy_stm32_rng_data.thr),
 				byte);
 		if (ret < 0) {
+#if !IRQLESS_TRNG
 			irq_disable(IRQN);
+#endif /* !IRQLESS_TRNG */
 			release_rng();
 			pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
 			if (IS_ENABLED(CONFIG_PM_S2RAM)) {
@@ -565,8 +631,52 @@ static void stm32_rng_isr(const void *arg)
 
 		k_sem_give(&entropy_stm32_rng_data.sem_sync);
 	}
+
+	return ret;
 }
 
+#if IRQLESS_TRNG
+static void trng_poll_work_item(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	RNG_TypeDef *rng = entropy_stm32_rng_data.rng;
+
+	/* Seed error occurred: reset TRNG and try again */
+	if (ll_rng_is_active_secs(entropy_stm32_rng_data.rng) ||
+		ll_rng_is_active_seis(entropy_stm32_rng_data.rng)) {
+
+		(void)random_byte_get(); /* this will recover the error */
+	} else if (ll_rng_is_active_drdy(rng)) {
+		/* Entropy available: read it and fill pools */
+		int res = perform_pool_refill();
+
+		if (res == -ENOBUFS) {
+			/**
+			 * All RNG pools are full - no more work needed.
+			 * Exit early to stop the work item from re-scheduling
+			 * itself. The RNG peripheral has already been released
+			 * by perform_pool_refill().
+			 */
+			return;
+		}
+	} else {
+		/**
+		 * No entropy available - try again later
+		 */
+	}
+
+	/* Schedule ourselves for next cycle */
+	k_work_schedule(dwork, TRNG_GENERATION_DELAY);
+}
+#else /* !IRQLESS_TRNG */
+static void stm32_rng_isr(const void *arg)
+{
+	ARG_UNUSED(arg);
+
+	(void)perform_pool_refill();
+}
+#endif /* IRQLESS_TRNG */
+
 static int entropy_stm32_rng_get_entropy(const struct device *dev,
 					 uint8_t *buf,
 					 uint16_t len)
@@ -613,20 +723,29 @@ static int entropy_stm32_rng_get_entropy_isr(const struct device *dev,
 	}
 
 	if (len) {
-		unsigned int key;
-		int irq_enabled;
-		bool rng_already_acquired;
+		/**
+		 * On TRNG without interrupt line, we cannot allow reentrancy,
+		 * so we have to suspend all interrupts. Otherwise, only suspend
+		 * it until we have established ourselves as owner of the TRNG
+		 * to prevent race with a higher priority interrupt handler.
+		 */
+		unsigned int key = irq_lock();
+		bool rng_already_acquired = false;
+#if !IRQLESS_TRNG
+		int irq_enabled = irq_is_enabled(IRQN);
 
-		key = irq_lock();
-		irq_enabled = irq_is_enabled(IRQN);
+		rng_already_acquired = (irq_enabled != 0);
 		irq_disable(IRQN);
 		irq_unlock(key);
+#endif /* !IRQLESS_TRNG */
 
 		/* Do not release if IRQ is enabled. RNG will be released in ISR
-		 * when the pools are full.
+		 * when the pools are full. On TRNG without interrupt line, the
+		 * default value of false ensures TRNG is always released.
 		 */
-		rng_already_acquired = z_stm32_hsem_is_owned(CFG_HW_RNG_SEMID) ||
-				       irq_enabled;
+		if (z_stm32_hsem_is_owned(CFG_HW_RNG_SEMID)) {
+			rng_already_acquired = true;
+		}
 		acquire_rng();
 
 		cnt = generate_from_isr(buf, len);
@@ -636,9 +755,14 @@ static int entropy_stm32_rng_get_entropy_isr(const struct device *dev,
 			release_rng();
 		}
 
+#if IRQLESS_TRNG
+		/* Exit critical section */
+		irq_unlock(key);
+#else
 		if (irq_enabled) {
 			irq_enable(IRQN);
 		}
+#endif /* !IRQLESS_TRNG */
 	}
 
 	return cnt;
@@ -684,6 +808,10 @@ static int entropy_stm32_rng_init(const struct device *dev)
 
 	k_work_init(&dev_data->filling_work, pool_filling_work_handler);
 
+#if IRQLESS_TRNG
+	k_work_init_delayable(&dev_data->trng_poll_work, trng_poll_work_item);
+#endif /* IRQLESS_TRNG */
+
 	rng_pool_init((struct rng_pool *)(dev_data->thr),
 		      CONFIG_ENTROPY_STM32_THR_POOL_SIZE,
 		      CONFIG_ENTROPY_STM32_THR_THRESHOLD);
@@ -691,7 +819,9 @@ static int entropy_stm32_rng_init(const struct device *dev)
 		      CONFIG_ENTROPY_STM32_ISR_POOL_SIZE,
 		      CONFIG_ENTROPY_STM32_ISR_THRESHOLD);
 
+#if !IRQLESS_TRNG
 	IRQ_CONNECT(IRQN, IRQ_PRIO, stm32_rng_isr, &entropy_stm32_rng_data, 0);
+#endif /* !IRQLESS_TRNG */
 
 #if !defined(CONFIG_SOC_SERIES_STM32WBX) && !defined(CONFIG_STM32H7_DUAL_CORE)
 	/* For multi-core MCUs, RNG configuration is automatically performed
diff --git a/drivers/entropy/entropy_stm32.h b/drivers/entropy/entropy_stm32.h
new file mode 100644
index 00000000000..533cc031493
--- /dev/null
+++ b/drivers/entropy/entropy_stm32.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <stm32_ll_rng.h>
+
+/**
+ * This driver supports two compatibles:
+ *	- "st,stm32-rng" for TRNG with IRQ lines
+ *	- "st,stm32-rng-noirq" for TRNG without IRQ lines
+ */
+#define IRQLESS_TRNG DT_HAS_COMPAT_STATUS_OKAY(st_stm32_rng_noirq)
+
+#if IRQLESS_TRNG
+#define DT_DRV_COMPAT st_stm32_rng_noirq
+#define TRNG_GENERATION_DELAY	K_NSEC(DT_INST_PROP_OR(0, generation_delay_ns, 0))
+#else /* !IRQLESS_TRNG */
+#define DT_DRV_COMPAT st_stm32_rng
+#define IRQN		DT_INST_IRQN(0)
+#define IRQ_PRIO	DT_INST_IRQ(0, priority)
+#endif /* IRQLESS_TRNG */
+
+/* Cross-series LL compatibility wrappers */
+static inline void ll_rng_enable_it(RNG_TypeDef *RNGx)
+{
+	/* Silence "unused" warning on IRQ-less hardware*/
+	ARG_UNUSED(RNGx);
+#if !IRQLESS_TRNG
+#	if defined(CONFIG_SOC_STM32WB09XX)
+		LL_RNG_EnableEnErrorIrq(RNGx);
+		LL_RNG_EnableEnFfFullIrq(RNGx);
+#	else
+		LL_RNG_EnableIT(RNGx);
+#	endif
+#endif /* !IRQLESS_TRNG */
+}
+
+static inline uint32_t ll_rng_is_active_seis(RNG_TypeDef *RNGx)
+{
+#if defined(CONFIG_SOC_STM32WB09XX)
+	return LL_RNG_IsActiveFlag_ENTROPY_ERR(RNGx);
+#elif defined(CONFIG_SOC_SERIES_STM32WB0X)
+	/* STM32WB05 / STM32WB06 / STM32WB07 */
+	return LL_RNG_IsActiveFlag_FAULT(RNGx);
+#else
+	return LL_RNG_IsActiveFlag_SEIS(RNGx);
+#endif /* CONFIG_SOC_SERIES_STM32WB0X */
+}
+
+static inline void ll_rng_clear_seis(RNG_TypeDef *RNGx)
+{
+#if defined(CONFIG_SOC_STM32WB09XX)
+	LL_RNG_SetResetHealthErrorFlags(RNGx, 1);
+#elif defined(CONFIG_SOC_SERIES_STM32WB0X)
+	/* STM32WB05 / STM32WB06 / STM32WB07 */
+	LL_RNG_ClearFlag_FAULT(RNGx);
+#else
+	LL_RNG_ClearFlag_SEIS(RNGx);
+#endif /* CONFIG_SOC_SERIES_STM32WB0X */
+}
+
+static inline uint32_t ll_rng_is_active_secs(RNG_TypeDef *RNGx)
+{
+#if !defined(CONFIG_SOC_SERIES_STM32WB0X)
+	return LL_RNG_IsActiveFlag_SECS(RNGx);
+#else
+	/**
+	 * STM32WB0x RNG has no equivalent of SECS.
+	 * Since this flag is always checked in conjunction
+	 * with FAULT (the SEIS equivalent), returning 0 is OK.
+	 */
+	return 0;
+#endif /* !CONFIG_SOC_SERIES_STM32WB0X */
+}
+
+static inline uint32_t ll_rng_is_active_drdy(RNG_TypeDef *RNGx)
+{
+#if defined(CONFIG_SOC_STM32WB09XX)
+	return LL_RNG_IsActiveFlag_VAL_READY(RNGx);
+#elif defined(CONFIG_SOC_SERIES_STM32WB0X)
+	/* STM32WB05 / STM32WB06 / STM32WB07 */
+	return LL_RNG_IsActiveFlag_RNGRDY(RNGx);
+#else
+	return LL_RNG_IsActiveFlag_DRDY(RNGx);
+#endif /* CONFIG_SOC_SERIES_STM32WB0X */
+}
+
+static inline uint16_t ll_rng_read_rand_data(RNG_TypeDef *RNGx)
+{
+#if defined(CONFIG_SOC_STM32WB09XX)
+	uint16_t rnd = (uint16_t)LL_RNG_GetRndVal(RNGx);
+
+	/**
+	 * STM32WB09 TRNG does not clear IRQ flags in hardware.
+	 * We must clear the "FIFO full" flag now that we consumed data
+	 * from it to ensure the TRNG's IRQ line goes back to low state.
+	 *
+	 * Raw register access is performed because STM32CubeWB0 v1.0.0
+	 * package is lacking the LL function to clear IRQ flags.
+	 */
+	WRITE_REG(RNG->IRQ_SR, RNG_IRQ_SR_FF_FULL_IRQ);
+
+	return rnd;
+#elif defined(CONFIG_SOC_SERIES_STM32WB0X)
+	/* STM32WB05 / STM32WB06 / STM32WB07 */
+	return LL_RNG_ReadRandData16(RNGx);
+#else
+	return (uint16_t)LL_RNG_ReadRandData32(RNGx);
+#endif /* CONFIG_SOC_SERIES_STM32WB0X */
+}
diff --git a/drivers/entropy/entropy_sy1xx_trng.c b/drivers/entropy/entropy_sy1xx_trng.c
new file mode 100644
index 00000000000..636f2b27955
--- /dev/null
+++ b/drivers/entropy/entropy_sy1xx_trng.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2025 sensry.io
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT sensry_sy1xx_trng
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(sy1xx_entropy, CONFIG_ENTROPY_LOG_LEVEL);
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/entropy.h>
+#include <errno.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+
+#define SY1XX_TRNG_VAL_OFFS        0x00
+#define SY1XX_TRNG_FIFO_COUNT_OFFS 0x04
+#define SY1XX_TRNG_STATUS_OFFS     0x08
+#define SY1XX_TRNG_ERROR_OFFS      0x0c
+
+#define SY1XX_TRNG_FIFO_SIZE 64
+
+/* time needed to fill fifo when empty */
+#define SY1XX_TRNG_FIFO_REFILL_TIME_USEC   80
+#define SY1XX_TRNG_FIFO_REFILL_MAX_RETRIES 5
+
+struct sy1xx_trng_config {
+	uint32_t base_addr;
+};
+
+struct sy1xx_trng_data {
+	struct k_mutex mutex;
+};
+
+static int sy1xx_trng_driver_init(const struct device *dev)
+{
+	const struct sy1xx_trng_config *const cfg = dev->config;
+	struct sy1xx_trng_data *const data = dev->data;
+
+	k_mutex_init(&data->mutex);
+
+	/* trng comes up fully initialized, so only check if all is fine */
+	if (0 != sys_read32(cfg->base_addr + SY1XX_TRNG_ERROR_OFFS)) {
+		LOG_ERR("failure mode active, internal init failed");
+		return -EINVAL;
+	}
+
+	if (SY1XX_TRNG_FIFO_SIZE != sys_read32(cfg->base_addr + SY1XX_TRNG_FIFO_COUNT_OFFS)) {
+		LOG_ERR("fifo not fully loaded");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int sy1xx_trng_driver_get_entropy(const struct device *dev, uint8_t *buffer, uint16_t length)
+{
+	const struct sy1xx_trng_config *const cfg = dev->config;
+	struct sy1xx_trng_data *const data = dev->data;
+	uint32_t retries_left;
+	uint32_t random_word;
+
+	uint32_t word_count = DIV_ROUND_UP(length, 4);
+
+	for (uint32_t i = 0; i < word_count; i++) {
+		retries_left = SY1XX_TRNG_FIFO_REFILL_MAX_RETRIES;
+
+		k_mutex_lock(&data->mutex, K_FOREVER);
+		while (true) {
+			/* make sure fifo has at least one random word */
+			if (sys_read32(cfg->base_addr + SY1XX_TRNG_FIFO_COUNT_OFFS) > 0) {
+				/* get new random word */
+				random_word = sys_read32(cfg->base_addr + SY1XX_TRNG_VAL_OFFS);
+				break;
+			}
+
+			/* currently no random values available, thus wait */
+			retries_left--;
+			if (!retries_left) {
+				/* number of retries exhausted, give up */
+				k_mutex_unlock(&data->mutex);
+				return -ETIMEDOUT;
+			}
+			k_sleep(K_USEC(SY1XX_TRNG_FIFO_REFILL_TIME_USEC));
+		};
+		k_mutex_unlock(&data->mutex);
+
+		memcpy(&buffer[i * 4], &random_word, MIN(length, 4));
+		length -= 4;
+	}
+
+	/* always error check, to make sure that we received valid readings */
+	if (0 != sys_read32(cfg->base_addr + SY1XX_TRNG_ERROR_OFFS)) {
+		LOG_ERR("failure mode active, reading of values failed");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int sy1xx_trng_driver_get_entropy_isr(const struct device *dev, uint8_t *buffer,
+					     uint16_t length, uint32_t flags)
+{
+
+	const struct sy1xx_trng_config *const cfg = dev->config;
+	unsigned int key;
+	uint32_t random_word;
+	int ret;
+
+	uint32_t word_count = DIV_ROUND_UP(length, 4);
+
+	for (uint32_t i = 0; i < word_count; i++) {
+
+		do {
+			key = irq_lock();
+			/* make sure fifo has at least one random word */
+			if (sys_read32(cfg->base_addr + SY1XX_TRNG_FIFO_COUNT_OFFS) > 0) {
+				/* get new random word */
+				random_word = sys_read32(cfg->base_addr + SY1XX_TRNG_VAL_OFFS);
+				ret = 0;
+			} else {
+				ret = -EAGAIN;
+			}
+			irq_unlock(key);
+
+			if (ret && !(flags & ENTROPY_BUSYWAIT)) {
+				/* no waiting allowed */
+				return ret;
+			}
+
+		} while (ret);
+
+		memcpy(&buffer[i * 4], &random_word, MIN(length, 4));
+		length -= 4;
+	}
+
+	/* always error check, to make sure that we received valid readings */
+	if (0 != sys_read32(cfg->base_addr + SY1XX_TRNG_ERROR_OFFS)) {
+		LOG_ERR("failure mode active, reading of values failed");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(entropy,
+		  sy1xx_entropy_api) = {.get_entropy = sy1xx_trng_driver_get_entropy,
+					.get_entropy_isr = sy1xx_trng_driver_get_entropy_isr};
+
+#define SY1XX_TRNG_INIT(n)                                                                         \
+                                                                                                   \
+	static const struct sy1xx_trng_config sy1xx_trng##n##_cfg = {                              \
+		.base_addr = (uint32_t)DT_INST_REG_ADDR(n),                                        \
+	};                                                                                         \
+                                                                                                   \
+	static struct sy1xx_trng_data sy1xx_trng##n##_data = {};                                   \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, sy1xx_trng_driver_init, NULL, &sy1xx_trng##n##_data,              \
+			      &sy1xx_trng##n##_cfg, PRE_KERNEL_1, CONFIG_ENTROPY_INIT_PRIORITY,    \
+			      &sy1xx_entropy_api);
+
+DT_INST_FOREACH_STATUS_OKAY(SY1XX_TRNG_INIT)
diff --git a/drivers/entropy/fake_entropy_native_bottom.c b/drivers/entropy/fake_entropy_native_bottom.c
index f456b978d99..119e41c446f 100644
--- a/drivers/entropy/fake_entropy_native_bottom.c
+++ b/drivers/entropy/fake_entropy_native_bottom.c
@@ -3,8 +3,7 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  *
- * Bottom/Linux side of the pseudo-random entropy generator for
- * ARCH_POSIX architecture
+ * Bottom/Linux side of the pseudo-random entropy generator for the native simulator
  */
 
 #undef _XOPEN_SOURCE
diff --git a/drivers/entropy/fake_entropy_native_posix.c b/drivers/entropy/fake_entropy_native_posix.c
deleted file mode 100644
index 1b7e457fca6..00000000000
--- a/drivers/entropy/fake_entropy_native_posix.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Copyright (c) 2018 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Pseudo-random entropy generator for the ARCH_POSIX architecture:
- * Following the principle of reproducibility of the native_posix board
- * this entropy device will always generate the same random sequence when
- * initialized with the same seed
- *
- * This entropy source should only be used for testing.
- */
-
-#define DT_DRV_COMPAT zephyr_native_posix_rng
-
-#include <zephyr/device.h>
-#include <zephyr/drivers/entropy.h>
-#include <zephyr/init.h>
-#include <zephyr/sys/util.h>
-#include <stdlib.h>
-#include <string.h>
-#include <zephyr/arch/posix/posix_trace.h>
-#include "soc.h"
-#include "cmdline.h" /* native_posix command line options header */
-#include "nsi_host_trampolines.h"
-#include "fake_entropy_native_bottom.h"
-
-static unsigned int seed = 0x5678;
-static bool seed_random;
-static bool seed_set;
-
-static int entropy_native_posix_get_entropy(const struct device *dev,
-					    uint8_t *buffer,
-					    uint16_t length)
-{
-	ARG_UNUSED(dev);
-
-	while (length) {
-		/*
-		 * Note that only 1 thread (Zephyr thread or HW models), runs at
-		 * a time, therefore there is no need to use random_r()
-		 */
-		long value = nsi_host_random();
-
-		size_t to_copy = MIN(length, sizeof(long int));
-
-		memcpy(buffer, &value, to_copy);
-		buffer += to_copy;
-		length -= to_copy;
-	}
-
-	return 0;
-}
-
-static int entropy_native_posix_get_entropy_isr(const struct device *dev,
-						uint8_t *buf,
-						uint16_t len, uint32_t flags)
-{
-	ARG_UNUSED(flags);
-
-	/*
-	 * entropy_native_posix_get_entropy() is also safe for ISRs
-	 * and always produces data.
-	 */
-	entropy_native_posix_get_entropy(dev, buf, len);
-
-	return len;
-}
-
-static int entropy_native_posix_init(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-	if (seed_set || seed_random ||
-	    IS_ENABLED(CONFIG_FAKE_ENTROPY_NATIVE_POSIX_SEED_BY_DEFAULT)) {
-		entropy_native_seed(seed, seed_random);
-	}
-	posix_print_warning("WARNING: "
-			    "Using a test - not safe - entropy source\n");
-	return 0;
-}
-
-static DEVICE_API(entropy, entropy_native_posix_api_funcs) = {
-	.get_entropy     = entropy_native_posix_get_entropy,
-	.get_entropy_isr = entropy_native_posix_get_entropy_isr
-};
-
-DEVICE_DT_INST_DEFINE(0,
-		    entropy_native_posix_init, NULL,
-		    NULL, NULL,
-		    PRE_KERNEL_1, CONFIG_ENTROPY_INIT_PRIORITY,
-		    &entropy_native_posix_api_funcs);
-
-static void seed_was_set(char *argv, int offset)
-{
-	ARG_UNUSED(argv);
-	ARG_UNUSED(offset);
-	seed_set = true;
-}
-
-static void add_fake_entropy_option(void)
-{
-	static struct args_struct_t entropy_options[] = {
-		{
-			.option = "seed",
-			.name = "r_seed",
-			.type = 'u',
-			.dest = (void *)&seed,
-			.call_when_found = seed_was_set,
-			.descript = "A 32-bit integer seed value for the entropy device, such as "
-				    "97229 (decimal), 0x17BCD (hex), or 0275715 (octal)"
-		},
-		{
-			.is_switch = true,
-			.option = "seed-random",
-			.type = 'b',
-			.dest = (void *)&seed_random,
-			.descript = "Seed the random generator from /dev/urandom. "
-				    "Note your test may not be reproducible if you set this option"
-		},
-		ARG_TABLE_ENDMARKER
-	};
-
-	native_add_command_line_opts(entropy_options);
-}
-
-NATIVE_TASK(add_fake_entropy_option, PRE_BOOT_1, 10);
diff --git a/drivers/entropy/fake_entropy_native_sim.c b/drivers/entropy/fake_entropy_native_sim.c
new file mode 100644
index 00000000000..abc6acec537
--- /dev/null
+++ b/drivers/entropy/fake_entropy_native_sim.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2018 Oticon A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Pseudo-random entropy generator for native simulator based target boards:
+ * Following the principle of reproducibility of the native_sim board
+ * this entropy device will always generate the same random sequence when
+ * initialized with the same seed
+ *
+ * This entropy source should only be used for testing.
+ */
+
+#include <zephyr/devicetree.h>
+#if DT_HAS_COMPAT_STATUS_OKAY(zephyr_native_posix_rng)
+#define DT_DRV_COMPAT zephyr_native_posix_rng
+#warning "zephyr,native-posix-rng is deprecated in favor of zephyr,native-sim-rng"
+#else
+#define DT_DRV_COMPAT zephyr_native_sim_rng
+#endif
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/entropy.h>
+#include <zephyr/init.h>
+#include <zephyr/sys/util.h>
+#include <stdlib.h>
+#include <string.h>
+#include <zephyr/arch/posix/posix_trace.h>
+#include "soc.h"
+#include "cmdline.h" /* native_sim command line options header */
+#include "nsi_host_trampolines.h"
+#include "fake_entropy_native_bottom.h"
+
+static unsigned int seed = 0x5678;
+static bool seed_random;
+static bool seed_set;
+
+static int entropy_native_sim_get_entropy(const struct device *dev,
+					    uint8_t *buffer,
+					    uint16_t length)
+{
+	ARG_UNUSED(dev);
+
+	while (length) {
+		/*
+		 * Note that only 1 thread (Zephyr thread or HW models), runs at
+		 * a time, therefore there is no need to use random_r()
+		 */
+		long value = nsi_host_random();
+
+		/* The host random() provides a number between 0 and 2**31-1. Bit 32 is always 0.
+		 * So let's just use the lower 3 bytes discarding the upper 7 bits
+		 */
+		size_t to_copy = MIN(length, 3);
+
+		memcpy(buffer, &value, to_copy);
+		buffer += to_copy;
+		length -= to_copy;
+	}
+
+	return 0;
+}
+
+static int entropy_native_sim_get_entropy_isr(const struct device *dev,
+						uint8_t *buf,
+						uint16_t len, uint32_t flags)
+{
+	ARG_UNUSED(flags);
+
+	/*
+	 * entropy_native_sim_get_entropy() is also safe for ISRs
+	 * and always produces data.
+	 */
+	entropy_native_sim_get_entropy(dev, buf, len);
+
+	return len;
+}
+
+static int entropy_native_sim_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+	if (seed_set || seed_random ||
+	    IS_ENABLED(CONFIG_FAKE_ENTROPY_NATIVE_SIM_SEED_BY_DEFAULT)) {
+		entropy_native_seed(seed, seed_random);
+	}
+	posix_print_warning("WARNING: "
+			    "Using a test - not safe - entropy source\n");
+	return 0;
+}
+
+static DEVICE_API(entropy, entropy_native_sim_api_funcs) = {
+	.get_entropy     = entropy_native_sim_get_entropy,
+	.get_entropy_isr = entropy_native_sim_get_entropy_isr
+};
+
+DEVICE_DT_INST_DEFINE(0,
+		    entropy_native_sim_init, NULL,
+		    NULL, NULL,
+		    PRE_KERNEL_1, CONFIG_ENTROPY_INIT_PRIORITY,
+		    &entropy_native_sim_api_funcs);
+
+static void seed_was_set(char *argv, int offset)
+{
+	ARG_UNUSED(argv);
+	ARG_UNUSED(offset);
+	seed_set = true;
+}
+
+static void add_fake_entropy_option(void)
+{
+	static struct args_struct_t entropy_options[] = {
+		{
+			.option = "seed",
+			.name = "r_seed",
+			.type = 'u',
+			.dest = (void *)&seed,
+			.call_when_found = seed_was_set,
+			.descript = "A 32-bit integer seed value for the entropy device, such as "
+				    "97229 (decimal), 0x17BCD (hex), or 0275715 (octal)"
+		},
+		{
+			.is_switch = true,
+			.option = "seed-random",
+			.type = 'b',
+			.dest = (void *)&seed_random,
+			.descript = "Seed the random generator from /dev/urandom. "
+				    "Note your test may not be reproducible if you set this option"
+		},
+		ARG_TABLE_ENDMARKER
+	};
+
+	native_add_command_line_opts(entropy_options);
+}
+
+NATIVE_TASK(add_fake_entropy_option, PRE_BOOT_1, 10);
diff --git a/drivers/espi/Kconfig.npcx b/drivers/espi/Kconfig.npcx
index dbeadaddfa2..fbd6ee643ca 100644
--- a/drivers/espi/Kconfig.npcx
+++ b/drivers/espi/Kconfig.npcx
@@ -60,6 +60,19 @@ config ESPI_NPCX_PERIPHERAL_DEBUG_PORT_80_RING_BUF_SIZE
 	  The size of the ring buffer in byte used by the Port80 ISR to store
 	  Postcodes from Host.
 
+config ESPI_NPCX_VWIRE_ENABLE_SEND_CHECK
+	bool "Check the value was read by host after wire bits changed"
+	help
+	  This option enables the function to check whether the host has read the value
+	  after the wire data changes.
+
+config ESPI_NPCX_WIRE_SEND_TIMEOUT_US
+	int "eSPI virtual wire send timeout count"
+	default 1000
+	help
+	  The times to check status after sending the eSPI virtual wire signal. The unit
+	  is microseconds (µs).
+
 config ESPI_TAF_NPCX
 	bool "Nuvoton NPCX embedded controller (EC) ESPI TAF driver"
 	depends on SOC_SERIES_NPCX4
@@ -98,6 +111,14 @@ config ESPI_TAF_NPCX_RPMC_SUPPORT
 	help
 	  This option enable the handler for eSPI TAF RPMC request.
 
+config ESPI_TAF_NPCX_STS_AWAIT_TIMEOUT
+	int "A timeout value in microseconds to wait for automatic read status"
+	depends on ESPI_TAF_NPCX
+	default 20000
+	help
+	  This option specifies the timeout value in microseconds (us) for checking
+	  automatic read status.
+
 # The default value 'y' for the existing options if ESPI_NPCX is selected.
 if ESPI_NPCX
 
@@ -134,4 +155,12 @@ config ESPI_NPCX_CAF_GLOBAL_RESET_WORKAROUND
 	help
 	  Workaround the issue "Global Reset" in the npcx4 SoC errata.
 
+config ESPI_NPCX_RESET_SLP_SX_VW_ON_ESPI_RST
+	bool "Reset SLP_Sx virtual wires when eSPI_RST is asserted"
+	help
+	    The SLP_S3/SLP_S4/SLP_S5/ virtual wires are automatically reset when
+	    eSPI_Reset is asserted on the global reset.
+	    Don't enable this config if the platform implements the Deep-Sx
+	    entry as EC needs to maintain these pins' states per request.
+
 endif #ESPI_NPCX
diff --git a/drivers/espi/Kconfig.xec b/drivers/espi/Kconfig.xec
index 0b3e5644460..36ebba6aa9d 100644
--- a/drivers/espi/Kconfig.xec
+++ b/drivers/espi/Kconfig.xec
@@ -104,6 +104,13 @@ config ESPI_XEC_PERIPHERAL_HOST_CMD_PARAM_SIZE
 config ESPI_PERIPHERAL_8042_KBC
 	default y
 
+config ESPI_XEC_P80_MULTIBYTE
+	bool "Host can write 1/2/4 bytes of Port80 data in a eSPI transaction"
+	depends on ESPI_XEC_V2 && ESPI_PERIPHERAL_DEBUG_PORT_80
+	help
+	  EC can accept 1/2/4 bytes of Port 80 data written from the Host in an
+	  eSPI transaction.
+
 if ESPI_PERIPHERAL_CHANNEL
 
 config ESPI_PERIPHERAL_XEC_MAILBOX
diff --git a/drivers/espi/espi_mchp_xec.c b/drivers/espi/espi_mchp_xec.c
index a609c7a8921..01103e31bd4 100644
--- a/drivers/espi/espi_mchp_xec.c
+++ b/drivers/espi/espi_mchp_xec.c
@@ -19,9 +19,9 @@
 #define ESPI_XEC_VWIRE_ACK_DELAY    10ul
 
 /* Maximum timeout to transmit a virtual wire packet.
- * 10 ms expressed in multiples of 100us
+ * 1 ms expressed in multiples of 1us
  */
-#define ESPI_XEC_VWIRE_SEND_TIMEOUT 100ul
+#define ESPI_XEC_VWIRE_SEND_TIMEOUT 1000ul
 
 #define VW_MAX_GIRQS                2ul
 
@@ -461,10 +461,15 @@ static int espi_xec_send_vwire(const struct device *dev,
 		/* Ensure eSPI virtual wire packet is transmitted
 		 * There is no interrupt, so need to poll register
 		 */
-		uint8_t rd_cnt = ESPI_XEC_VWIRE_SEND_TIMEOUT;
+		uint16_t rd_cnt = ESPI_XEC_VWIRE_SEND_TIMEOUT;
 
 		while (reg->SRC_CHG && rd_cnt--) {
-			k_busy_wait(100);
+			k_busy_wait(1);
+		}
+
+		if (rd_cnt == 0) {
+			LOG_ERR("VW %d send timeout", signal);
+			return -ETIMEDOUT;
 		}
 	}
 
diff --git a/drivers/espi/espi_mchp_xec_host_v2.c b/drivers/espi/espi_mchp_xec_host_v2.c
index 5bcb78903cb..73e3858363c 100644
--- a/drivers/espi/espi_mchp_xec_host_v2.c
+++ b/drivers/espi/espi_mchp_xec_host_v2.c
@@ -70,6 +70,9 @@
 #define XEC_PCR_REG_BASE						\
 	((struct pcr_regs *)(DT_REG_ADDR(DT_NODELABEL(pcr))))
 
+#define MCHP_P80_MAX_BYTE_COUNT  4
+#define MCHP_P80_FIFO_READ_COUNT 8
+
 struct xec_espi_host_sram_config {
 	uint32_t host_sram1_base;
 	uint32_t host_sram2_base;
@@ -817,6 +820,7 @@ static const struct xec_p80bd_config xec_p80bd0_cfg = {
  * We must decode the byte lane information and produce one or more
  * notification packets.
  */
+#ifndef CONFIG_ESPI_XEC_P80_MULTIBYTE
 static void p80bd0_isr(const struct device *dev)
 {
 	struct espi_xec_data *const data =
@@ -825,7 +829,7 @@ static void p80bd0_isr(const struct device *dev)
 		(struct p80bd_regs *)xec_p80bd0_cfg.regbase;
 	struct espi_event evt = { ESPI_BUS_PERIPHERAL_NOTIFICATION, 0,
 				  ESPI_PERIPHERAL_NODATA };
-	int count = 8; /* limit ISR to 8 bytes */
+	int count = MCHP_P80_FIFO_READ_COUNT; /* limit ISR to 8 bytes */
 	uint32_t dattr = p80regs->EC_DA;
 
 	/* b[7:0]=8-bit value written, b[15:8]=attributes */
@@ -861,6 +865,47 @@ static void p80bd0_isr(const struct device *dev)
 	/* clear GIRQ status */
 	mchp_xec_ecia_info_girq_src_clr(xec_p80bd0_cfg.ecia_info);
 }
+#else
+static void p80bd0_isr(const struct device *dev)
+{
+	struct espi_xec_data *const data =
+		(struct espi_xec_data *const)dev->data;
+	struct p80bd_regs *p80regs =
+		(struct p80bd_regs *)xec_p80bd0_cfg.regbase;
+	struct espi_event evt = { ESPI_BUS_PERIPHERAL_NOTIFICATION, 0,
+				  ESPI_PERIPHERAL_NODATA };
+	int count = MCHP_P80_FIFO_READ_COUNT; /* limit ISR to 8 bytes */
+	uint32_t dattr = p80regs->EC_DA;
+	uint8_t byte_count;
+	uint8_t shift;
+
+	/* b[7:0]=8-bit value written, b[15:8]=attributes */
+	while ((dattr & MCHP_P80BD_ECDA_NE) && (count--)) { /* Not empty? */
+		byte_count = 0;
+		evt.evt_data = 0;
+
+		byte_count = BIT((dattr & MCHP_P80BD_ECDA_LEN_MSK) >> MCHP_P80BD_ECDA_LEN_POS);
+		if (byte_count <= MCHP_P80_MAX_BYTE_COUNT) {
+			shift = 0;
+			while (byte_count) {
+				evt.evt_data |= (dattr & 0xffu) << (shift * 8);
+				byte_count--;
+				shift++;
+				if (byte_count) {
+					dattr = p80regs->EC_DA;
+				}
+			}
+
+			evt.evt_details = ESPI_PERIPHERAL_DEBUG_PORT80;
+			espi_send_callbacks(&data->callbacks, dev, evt);
+		}
+		dattr = p80regs->EC_DA;
+	}
+
+	/* clear GIRQ status */
+	mchp_xec_ecia_info_girq_src_clr(xec_p80bd0_cfg.ecia_info);
+}
+#endif
 
 static int connect_irq_p80bd0(const struct device *dev)
 {
diff --git a/drivers/espi/espi_mchp_xec_v2.c b/drivers/espi/espi_mchp_xec_v2.c
index 22410a7f619..e4f315438be 100644
--- a/drivers/espi/espi_mchp_xec_v2.c
+++ b/drivers/espi/espi_mchp_xec_v2.c
@@ -25,9 +25,9 @@
 #define ESPI_XEC_VWIRE_ACK_DELAY	10ul
 
 /* Maximum timeout to transmit a virtual wire packet.
- * 10 ms expressed in multiples of 100us
+ * 1 ms expressed in multiples of 1us
  */
-#define ESPI_XEC_VWIRE_SEND_TIMEOUT	100ul
+#define ESPI_XEC_VWIRE_SEND_TIMEOUT	1000ul
 
 #define VW_MAX_GIRQS			2ul
 
@@ -325,10 +325,15 @@ static int espi_xec_send_vwire(const struct device *dev,
 		/* Ensure eSPI virtual wire packet is transmitted
 		 * There is no interrupt, so need to poll register
 		 */
-		uint8_t rd_cnt = ESPI_XEC_VWIRE_SEND_TIMEOUT;
+		uint16_t rd_cnt = ESPI_XEC_VWIRE_SEND_TIMEOUT;
 
 		while (sys_read8(regaddr + SMVW_BI_SRC_CHG) && rd_cnt--) {
-			k_busy_wait(100);
+			k_busy_wait(1);
+		}
+
+		if (rd_cnt == 0) {
+			LOG_ERR("VW %d send timeout", signal);
+			return -ETIMEDOUT;
 		}
 	}
 
diff --git a/drivers/espi/espi_npcx.c b/drivers/espi/espi_npcx.c
index 4a7f40b64c0..b42b270a2e8 100644
--- a/drivers/espi/espi_npcx.c
+++ b/drivers/espi/espi_npcx.c
@@ -91,6 +91,9 @@ static const struct espi_npcx_vw_ex espi_npcx_vw_ex_0[] = {
 #define NPCX_ESPI_MAXFREQ_50         3
 #define NPCX_ESPI_MAXFREQ_66         4
 
+/* SLP_S3/SLP_S4/SLP_S5 Virtual Wire belong to Virtual Wire Index 2 */
+#define ESPI_VW_SLP_SX_INDEX         0x02
+
 /* Minimum delay before acknowledging a virtual wire */
 #define NPCX_ESPI_VWIRE_ACK_DELAY    10ul /* 10 us */
 
@@ -498,6 +501,14 @@ static void espi_vw_config_input(const struct device *dev,
 	struct espi_reg *const inst = HAL_INSTANCE(dev);
 	int idx = config_in->reg_idx;
 
+	if (IS_ENABLED(CONFIG_ESPI_NPCX_RESET_SLP_SX_VW_ON_ESPI_RST)) {
+		uint8_t vwire_index = GET_FIELD(inst->VWEVMS[idx], NPCX_VWEVMS_INDEX);
+
+		if (vwire_index == ESPI_VW_SLP_SX_INDEX) {
+			inst->VWEVMS[idx] |= BIT(NPCX_VWEVMS_ENESPIRST);
+		}
+	}
+
 	/* IE & WE bits are already set? */
 	if (IS_BIT_SET(inst->VWEVMS[idx], NPCX_VWEVMS_IE) &&
 	    IS_BIT_SET(inst->VWEVMS[idx], NPCX_VWEVMS_WE)) {
@@ -848,9 +859,25 @@ static int espi_npcx_send_vwire(const struct device *dev,
 	if (signal >= ESPI_VWIRE_SIGNAL_TARGET_GPIO_0) {
 		SET_FIELD(inst->VWGPSM[reg_idx], NPCX_VWEVSM_WIRE, val);
 		reg_val = inst->VWGPSM[reg_idx];
+
+		if (IS_ENABLED(CONFIG_ESPI_NPCX_VWIRE_ENABLE_SEND_CHECK)) {
+			if (!WAIT_FOR(!IS_BIT_SET(inst->VWGPSM[reg_idx], NPCX_VWEVSM_DIRTY),
+				      CONFIG_ESPI_NPCX_WIRE_SEND_TIMEOUT_US, NULL)) {
+				LOG_ERR("%s signal %d timeout", __func__, signal);
+				return -ETIMEDOUT;
+			}
+		}
 	} else {
 		SET_FIELD(inst->VWEVSM[reg_idx], NPCX_VWEVSM_WIRE, val);
 		reg_val = inst->VWEVSM[reg_idx];
+
+		if (IS_ENABLED(CONFIG_ESPI_NPCX_VWIRE_ENABLE_SEND_CHECK)) {
+			if (!WAIT_FOR(!IS_BIT_SET(inst->VWEVSM[reg_idx], NPCX_VWEVSM_DIRTY),
+				      CONFIG_ESPI_NPCX_WIRE_SEND_TIMEOUT_US, NULL)) {
+				LOG_ERR("%s signal %d timeout", __func__, signal);
+				return -ETIMEDOUT;
+			}
+		}
 	}
 
 	LOG_DBG("Send VW: %s%d 0x%08X", reg_name, reg_idx, reg_val);
diff --git a/drivers/espi/espi_taf_npcx.c b/drivers/espi/espi_taf_npcx.c
index 04062f4363c..3d4450e1963 100644
--- a/drivers/espi/espi_taf_npcx.c
+++ b/drivers/espi/espi_taf_npcx.c
@@ -18,7 +18,15 @@
 
 LOG_MODULE_REGISTER(espi_taf, CONFIG_ESPI_LOG_LEVEL);
 
-static const struct device *const spi_dev = DEVICE_DT_GET(DT_ALIAS(taf_flash));
+#define NPCX_TAF_PRIME_FLASH_NODE DT_ALIAS(taf_flash)
+#define NPCX_TAF_SEC_FLASH_NODE   DT_ALIAS(taf_flash1)
+
+#define NPCX_TAF_ALLOC_SIZE(node) (MB(1) << DT_ENUM_IDX(node, spi_dev_size))
+
+static const struct device *const spi_dev = DEVICE_DT_GET(NPCX_TAF_PRIME_FLASH_NODE);
+#if DT_NODE_HAS_STATUS_OKAY(NPCX_TAF_SEC_FLASH_NODE)
+static const struct device *const spi_dev1 = DEVICE_DT_GET(NPCX_TAF_SEC_FLASH_NODE);
+#endif
 
 enum ESPI_TAF_ERASE_LEN {
 	NPCX_ESPI_TAF_ERASE_LEN_4KB,
@@ -52,6 +60,11 @@ struct espi_taf_npcx_data {
 	uint32_t src[16];
 	uint8_t read_buf[MAX_TX_PAYLOAD_SIZE];
 	struct k_work work;
+#if DT_NODE_HAS_STATUS_OKAY(NPCX_TAF_SEC_FLASH_NODE)
+	const struct device *low_dev_ptr;
+	const struct device *high_dev_ptr;
+	uint32_t low_dev_size;
+#endif
 };
 
 static struct espi_taf_npcx_data npcx_espi_taf_data;
@@ -236,6 +249,11 @@ static bool espi_taf_npcx_channel_ready(const struct device *dev)
 	if (!device_is_ready(spi_dev)) {
 		return false;
 	}
+#if DT_NODE_HAS_STATUS_OKAY(NPCX_TAF_SEC_FLASH_NODE)
+	if (!device_is_ready(spi_dev1)) {
+		return false;
+	}
+#endif
 
 	return true;
 }
@@ -362,7 +380,34 @@ static int espi_taf_npcx_flash_read(const struct device *dev, struct espi_saf_pa
 	}
 
 	do {
+#if DT_NODE_HAS_STATUS_OKAY(NPCX_TAF_SEC_FLASH_NODE)
+		if ((addr + len) <= npcx_espi_taf_data.low_dev_size) {
+			rc = flash_read(npcx_espi_taf_data.low_dev_ptr, addr,
+					npcx_espi_taf_data.read_buf, len);
+		} else if (addr >= npcx_espi_taf_data.low_dev_size) {
+			rc = flash_read(npcx_espi_taf_data.high_dev_ptr,
+					(addr - npcx_espi_taf_data.low_dev_size),
+					npcx_espi_taf_data.read_buf, len);
+		} else {
+			rc = flash_read(npcx_espi_taf_data.low_dev_ptr, addr,
+					npcx_espi_taf_data.read_buf,
+					(npcx_espi_taf_data.low_dev_size.low_dev_size - addr));
+
+			if (rc) {
+				LOG_ERR("flash read fail 0x%x", rc);
+				return -EIO;
+			}
+
+			uint32_t index = low_dev_size - addr;
+
+			rc = flash_read(
+				npcx_espi_taf_data.high_dev_ptr, 0x0,
+				&npcx_espi_taf_data.read_buf[index],
+				(addr + len - npcx_espi_taf_data.low_dev_size.low_dev_size));
+		}
+#else
 		rc = flash_read(spi_dev, addr, npcx_espi_taf_data.read_buf, len);
+#endif
 		if (rc) {
 			LOG_ERR("flash read fail 0x%x", rc);
 			return -EIO;
@@ -394,6 +439,8 @@ static int espi_taf_npcx_flash_write(const struct device *dev, struct espi_saf_p
 {
 	struct espi_taf_npcx_pckt *taf_data_ptr = (struct espi_taf_npcx_pckt *)pckt->buf;
 	uint8_t *data_ptr = (uint8_t *)(taf_data_ptr->data);
+	uint32_t addr = pckt->flash_addr;
+	uint32_t len = pckt->len;
 	int rc;
 
 	if (espi_taf_check_write_protect(dev, pckt->flash_addr,
@@ -402,7 +449,19 @@ static int espi_taf_npcx_flash_write(const struct device *dev, struct espi_saf_p
 		return -EINVAL;
 	}
 
-	rc = flash_write(spi_dev, pckt->flash_addr, data_ptr, pckt->len);
+#if DT_NODE_HAS_STATUS_OKAY(NPCX_TAF_SEC_FLASH_NODE)
+	if ((addr + len) <= npcx_espi_taf_data.low_dev_size) {
+		rc = flash_write(npcx_espi_taf_data.low_dev_ptr, addr, data_ptr, len);
+	} else if (addr >= npcx_espi_taf_data.low_dev_size) {
+		rc = flash_write(npcx_espi_taf_data.high_dev_ptr,
+				 (addr - npcx_espi_taf_data.low_dev_size), data_ptr, len);
+	} else {
+		LOG_ERR("Write across two flashes");
+		return -EINVAL;
+	}
+#else
+	rc = flash_write(spi_dev, addr, data_ptr, len);
+#endif
 	if (rc) {
 		LOG_ERR("flash write fail 0x%x", rc);
 		return -EIO;
@@ -438,7 +497,19 @@ static int espi_taf_npcx_flash_erase(const struct device *dev, struct espi_saf_p
 		return -EINVAL;
 	}
 
+#if DT_NODE_HAS_STATUS_OKAY(NPCX_TAF_SEC_FLASH_NODE)
+	if ((addr + len) <= npcx_espi_taf_data.low_dev_size) {
+		rc = flash_erase(npcx_espi_taf_data.low_dev_ptr, addr, len);
+	} else if (addr >= npcx_espi_taf_data.low_dev_size) {
+		rc = flash_erase(npcx_espi_taf_data.high_dev_ptr,
+				 (addr - npcx_espi_taf_data.low_dev_size), len);
+	} else {
+		LOG_ERR("Erase across two flashes");
+		return -EINVAL;
+	}
+#else
 	rc = flash_erase(spi_dev, addr, len);
+#endif
 	if (rc) {
 		LOG_ERR("flash erase fail");
 		return -EIO;
@@ -595,6 +666,38 @@ static void espi_taf_event_handler(const struct device *dev, struct espi_callbac
 	k_work_submit(&npcx_espi_taf_data.work);
 }
 
+int espi_taf_npcx_block(const struct device *dev, bool en_block)
+{
+	struct espi_reg *const inst = HAL_INSTANCE(dev);
+
+	if (!IS_BIT_SET(inst->FLASHCTL, NPCX_FLASHCTL_SAF_AUTO_READ)) {
+		return 0;
+	}
+
+	if (en_block) {
+		if (WAIT_FOR(!IS_BIT_SET(inst->ESPISTS, NPCX_ESPISTS_FLAUTORDREQ),
+			     CONFIG_ESPI_TAF_NPCX_STS_AWAIT_TIMEOUT, NULL) == false) {
+			LOG_ERR("Check Automatic Read Queue Empty Timeout");
+			return -ETIMEDOUT;
+		}
+
+		inst->FLASHCTL |= BIT(NPCX_FLASHCTL_AUTO_RD_DIS_CTL);
+
+		if (WAIT_FOR(IS_BIT_SET(inst->ESPISTS, NPCX_ESPISTS_AUTO_RD_DIS_STS),
+			     CONFIG_ESPI_TAF_NPCX_STS_AWAIT_TIMEOUT, NULL) == false) {
+			inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_AUTO_RD_DIS_CTL);
+			inst->ESPISTS |= BIT(NPCX_ESPISTS_AUTO_RD_DIS_STS);
+			LOG_ERR("Check Automatic Read Disable Timeout");
+			return -ETIMEDOUT;
+		}
+	} else {
+		inst->FLASHCTL &= ~BIT(NPCX_FLASHCTL_AUTO_RD_DIS_CTL);
+		inst->ESPISTS |= BIT(NPCX_ESPISTS_AUTO_RD_DIS_STS);
+	}
+
+	return 0;
+}
+
 int npcx_init_taf(const struct device *dev, sys_slist_t *callbacks)
 {
 	espi_init_callback(&espi_taf_cb, espi_taf_event_handler, ESPI_BUS_TAF_NOTIFICATION);
@@ -620,6 +723,18 @@ static int espi_taf_npcx_init(const struct device *dev)
 		  config->max_rd_sz);
 	inst->FLASHBASE = config->mapped_addr;
 
+#if DT_NODE_HAS_STATUS_OKAY(NPCX_TAF_SEC_FLASH_NODE)
+	if (IS_ENABLED(CONFIG_FLASH_NPCX_FIU_SUPP_LOW_DEV_SWAP)) {
+		npcx_espi_taf_data.low_dev_ptr = spi_dev1;
+		npcx_espi_taf_data.high_dev_ptr = spi_dev;
+		npcx_espi_taf_data.low_dev_size = NPCX_TAF_ALLOC_SIZE(NPCX_TAF_SEC_FLASH_NODE);
+	} else {
+		npcx_espi_taf_data.low_dev_ptr = spi_dev;
+		npcx_espi_taf_data.high_dev_ptr = spi_dev1;
+		npcx_espi_taf_data.low_dev_size = NPCX_TAF_ALLOC_SIZE(NPCX_TAF_PRIME_FLASH_NODE);
+	}
+#endif
+
 #ifdef CONFIG_ESPI_TAF_NPCX_RPMC_SUPPORT
 	uint8_t count_num = 0;
 
diff --git a/drivers/ethernet/CMakeLists.txt b/drivers/ethernet/CMakeLists.txt
index 65ce8a45332..f9cef24042b 100644
--- a/drivers/ethernet/CMakeLists.txt
+++ b/drivers/ethernet/CMakeLists.txt
@@ -26,7 +26,6 @@ zephyr_library_sources_ifdef(CONFIG_ETH_E1000		eth_e1000.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_ENC28J60	eth_enc28j60.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_ENC424J600	eth_enc424j600.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_ESP32		eth_esp32.c)
-zephyr_library_sources_ifdef(CONFIG_DSA_KSZ8XXX		dsa_ksz8xxx.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_LITEX_LITEETH	eth_litex_liteeth.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_SMSC911X	eth_smsc911x.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_STELLARIS	eth_stellaris.c)
@@ -41,8 +40,11 @@ zephyr_library_sources_ifdef(CONFIG_ETH_ADIN2111	eth_adin2111.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_LAN865X	        eth_lan865x.c oa_tc6.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_XMC4XXX		eth_xmc4xxx.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_TEST		eth_test.c)
-zephyr_library_sources_ifdef(CONFIG_ETH_RENESAS_RA     eth_renesas_ra.c)
-zephyr_library_sources_ifdef(CONFIG_ETH_LAN9250    eth_lan9250.c)
+zephyr_library_sources_ifdef(CONFIG_ETH_RENESAS_RA	eth_renesas_ra.c)
+zephyr_library_sources_ifdef(CONFIG_ETH_LAN9250		eth_lan9250.c)
+zephyr_library_sources_ifdef(CONFIG_ETH_SY1XX		eth_sensry_sy1xx_mac.c)
+zephyr_library_sources_ifdef(CONFIG_ETH_NXP_ENET	eth_nxp_enet.c)
+zephyr_library_sources_ifdef(CONFIG_ETH_XILINX_AXIENET	eth_xilinx_axienet.c)
 
 if(CONFIG_ETH_NXP_S32_NETC)
   zephyr_library_sources(eth_nxp_s32_netc.c)
@@ -50,29 +52,25 @@ if(CONFIG_ETH_NXP_S32_NETC)
   zephyr_library_sources_ifdef(CONFIG_DT_HAS_NXP_S32_NETC_VSI_ENABLED	eth_nxp_s32_netc_vsi.c)
 endif()
 
-if(CONFIG_ETH_NXP_IMX_NETC)
-  zephyr_library_sources(eth_nxp_imx_netc.c)
-  zephyr_library_sources(eth_nxp_imx_netc_psi.c)
-endif()
-
 zephyr_library_sources_ifdef(CONFIG_ETH_NXP_S32_GMAC	eth_nxp_s32_gmac.c)
 zephyr_library_sources_ifdef(CONFIG_ETH_NUMAKER		eth_numaker.c)
 
-if(CONFIG_ETH_NATIVE_POSIX)
+if(CONFIG_ETH_NATIVE_TAP)
   if (CONFIG_NATIVE_APPLICATION)
-    set(native_posix_source_files eth_native_posix.c eth_native_posix_adapt.c)
-    set_source_files_properties(${native_posix_source_files}
+    set(native_tap_source_files eth_native_tap.c eth_native_tap_adapt.c)
+    set_source_files_properties(${native_tap_source_files}
       PROPERTIES COMPILE_DEFINITIONS
       "NO_POSIX_CHEATS;_BSD_SOURCE;_DEFAULT_SOURCE"
     )
-    zephyr_library_sources(${native_posix_source_files})
+    zephyr_library_sources(${native_tap_source_files})
   else()
-    zephyr_library_sources(eth_native_posix.c)
-    target_sources(native_simulator INTERFACE eth_native_posix_adapt.c)
+    zephyr_library_sources(eth_native_tap.c)
+    target_sources(native_simulator INTERFACE eth_native_tap_adapt.c)
   endif()
 endif()
 
+add_subdirectory(dsa)
 add_subdirectory(phy)
 add_subdirectory(eth_nxp_enet_qos)
-add_subdirectory(nxp_enet)
+add_subdirectory(nxp_imx_netc)
 add_subdirectory(dwc_xgmac)
diff --git a/drivers/ethernet/Kconfig b/drivers/ethernet/Kconfig
index ba737519582..b771cd106f8 100644
--- a/drivers/ethernet/Kconfig
+++ b/drivers/ethernet/Kconfig
@@ -57,15 +57,14 @@ source "drivers/ethernet/Kconfig.sam_gmac"
 source "drivers/ethernet/Kconfig.stm32_hal"
 source "drivers/ethernet/Kconfig.dwmac"
 source "drivers/ethernet/Kconfig.smsc911x"
-source "drivers/ethernet/Kconfig.native_posix"
+source "drivers/ethernet/Kconfig.native_tap"
 source "drivers/ethernet/Kconfig.stellaris"
 source "drivers/ethernet/Kconfig.litex"
 source "drivers/ethernet/Kconfig.gecko"
 source "drivers/ethernet/Kconfig.w5500"
-source "drivers/ethernet/Kconfig.dsa"
 source "drivers/ethernet/Kconfig.xlnx_gem"
 source "drivers/ethernet/Kconfig.cyclonev"
-source "drivers/ethernet/Kconfig.nxp_imx_netc"
+source "drivers/ethernet/Kconfig.nxp_enet"
 source "drivers/ethernet/Kconfig.nxp_s32_netc"
 source "drivers/ethernet/Kconfig.nxp_s32_gmac"
 source "drivers/ethernet/Kconfig.smsc91x"
@@ -76,13 +75,16 @@ source "drivers/ethernet/Kconfig.lan865x"
 source "drivers/ethernet/Kconfig.xmc4xxx"
 source "drivers/ethernet/Kconfig.test"
 source "drivers/ethernet/Kconfig.lan9250"
+source "drivers/ethernet/Kconfig.sy1xx_mac"
+source "drivers/ethernet/Kconfig.xilinx_axienet"
 
 source "drivers/ethernet/eth_nxp_enet_qos/Kconfig"
 
+source "drivers/ethernet/dsa/Kconfig"
 source "drivers/ethernet/dwc_xgmac/Kconfig"
 source "drivers/ethernet/phy/Kconfig"
 
-source "drivers/ethernet/nxp_enet/Kconfig"
+source "drivers/ethernet/nxp_imx_netc/Kconfig"
 source "drivers/ethernet/Kconfig.renesas_ra"
 
 endif # "Ethernet Drivers"
diff --git a/drivers/ethernet/Kconfig.dsa b/drivers/ethernet/Kconfig.dsa
deleted file mode 100644
index 1974ce97f18..00000000000
--- a/drivers/ethernet/Kconfig.dsa
+++ /dev/null
@@ -1,60 +0,0 @@
-# Distributed Switch Architecture [DSA] configuration options
-
-# Copyright (c) 2020 DENX Software Engineering GmbH
-#               Lukasz Majewski <lukma@denx.de>
-# SPDX-License-Identifier: Apache-2.0
-
-config ETH_DSA_SUPPORT
-	bool
-	help
-	  Set by an ethernet driver that supports DSA.
-
-menuconfig NET_DSA
-	bool "Distributed Switch Architecture support"
-	depends on ETH_DSA_SUPPORT
-	help
-	  Enable Distributed Switch Architecture support. For now it
-	  only supports Kinetics and STM32 ENET drivers.
-
-if NET_DSA
-
-config DSA_KSZ8XXX
-	bool
-
-config DSA_KSZ8794
-	bool "Support for KSZ8794"
-	default y
-	depends on DT_HAS_MICROCHIP_KSZ8794_ENABLED
-	select DSA_KSZ8XXX
-	select SPI if $(dt_compat_on_bus,$(DT_COMPAT_MICROCHIP_KSZ8794),spi)
-	help
-	  Add support for KSZ8794 DSA device driver.
-
-config DSA_KSZ8863
-	bool "Support for KSZ8863"
-	default y
-	depends on DT_HAS_MICROCHIP_KSZ8863_ENABLED
-	select DSA_KSZ8XXX
-	select SPI if $(dt_compat_on_bus,$(DT_COMPAT_MICROCHIP_KSZ8863),spi)
-	help
-	  Add support for KSZ8863 DSA device driver.
-
-config DSA_KSZ_TAIL_TAGGING
-	bool "Support for tail tagging"
-	depends on DSA_KSZ8794 || DSA_KSZ8863
-	help
-	  Add support for tail tagging on DSA device.
-
-config DSA_SPI
-	bool "Support for PHY SPI interface"
-	depends on SPI && (DSA_KSZ8794 || DSA_KSZ8863)
-	help
-	  Use SPI bus to communicate with PHY
-
-module = NET_DSA
-module-dep = NET_LOG
-module-str = Log level for DSA
-module-help = Enables core DSA code to output debug messages.
-source "subsys/net/Kconfig.template.log_config.net"
-
-endif # NET_DSA
diff --git a/drivers/ethernet/Kconfig.lan865x b/drivers/ethernet/Kconfig.lan865x
index 42138aa1ed4..1a63331e079 100644
--- a/drivers/ethernet/Kconfig.lan865x
+++ b/drivers/ethernet/Kconfig.lan865x
@@ -6,6 +6,7 @@ menuconfig ETH_LAN865X
 	default y
 	depends on DT_HAS_MICROCHIP_LAN865X_ENABLED
 	select SPI
+	select MDIO
 	select NET_L2_ETHERNET_MGMT
 	help
 	  The LAN865X is a low power, 10BASE-T1S transceiver compliant with
diff --git a/drivers/ethernet/Kconfig.native_posix b/drivers/ethernet/Kconfig.native_posix
deleted file mode 100644
index d4c065fbdde..00000000000
--- a/drivers/ethernet/Kconfig.native_posix
+++ /dev/null
@@ -1,86 +0,0 @@
-# Native posix ethernet driver configuration options
-
-# Copyright (c) 2018 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-menuconfig ETH_NATIVE_POSIX
-	bool "Native Posix Ethernet driver"
-	depends on ARCH_POSIX
-	help
-	  Enable native posix ethernet driver. Note, this driver is run inside
-	  a process in your host system.
-
-if ETH_NATIVE_POSIX
-
-config ETH_NATIVE_POSIX_INTERFACE_COUNT
-	int "Number of network interfaces created"
-	default NET_GPTP_NUM_PORTS if NET_GPTP
-	default PTP_NUM_PORTS if PTP
-	default 1
-	range 1 32
-	help
-	  By default only one network interface is created. It is possible
-	  to create multiple interfaces in certain use cases. For example if
-	  multiple ports are defined in gPTP or PTP, then multiple network interfaces
-	  must be created here.
-
-config ETH_NATIVE_POSIX_DRV_NAME
-	string "Ethernet driver name"
-	default "zeth"
-	help
-	  This option sets the driver name and name of the network interface
-	  in your host system. If there are multiple network interfaces defined,
-	  then this value is used as a prefix and the interface names will be
-	  zeth0, zeth1, etc.
-
-config ETH_NATIVE_POSIX_DEV_NAME
-	string "Host ethernet TUN/TAP device name"
-	default "/dev/net/tun"
-	help
-	  This option sets the TUN/TAP device name in your host system.
-
-config ETH_NATIVE_POSIX_PTP_CLOCK
-	bool "PTP clock driver support"
-	default y if NET_GPTP || PTP
-	select PTP_CLOCK
-	depends on NET_GPTP || PTP
-	help
-	  Enable PTP clock support.
-
-config ETH_NATIVE_POSIX_RANDOM_MAC
-	bool "Random MAC address"
-	depends on ENTROPY_GENERATOR
-	default y
-	help
-	  Generate a random MAC address dynamically.
-
-config ETH_NATIVE_POSIX_VLAN_TAG_STRIP
-	bool "Strip VLAN tag from Rx frames"
-	depends on NET_VLAN
-	help
-	  Native posix ethernet driver will strip of VLAN tag from
-	  Rx Ethernet frames and sets tag information in net packet
-	  metadata.
-
-config ETH_NATIVE_POSIX_MAC_ADDR
-	string "MAC address for the interface"
-	default ""
-	depends on !ETH_NATIVE_POSIX_RANDOM_MAC
-	help
-	  Specify a MAC address for the ethernet interface in the form of
-	  six hex 8-bit chars separated by colons (e.g.:
-	  aa:33:cc:22:e2:c0).  The default is an empty string, which
-	  means the code will make 00:00:5E:00:53:XX, where XX will be
-	  random.
-
-config ETH_NATIVE_POSIX_RX_TIMEOUT
-	int "Ethernet RX timeout"
-	default 1 if NET_GPTP
-	default 50
-	range 1 100
-	help
-	  Native posix ethernet driver repeatedly checks for new data.
-	  Specify how long the thread sleeps between these checks if no new data
-	  available.
-
-endif # ETH_NATIVE_POSIX
diff --git a/drivers/ethernet/Kconfig.native_tap b/drivers/ethernet/Kconfig.native_tap
new file mode 100644
index 00000000000..f42b65fb198
--- /dev/null
+++ b/drivers/ethernet/Kconfig.native_tap
@@ -0,0 +1,159 @@
+# Native TAP ethernet driver configuration options
+
+# Copyright (c) 2018 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig ETH_NATIVE_TAP
+	bool "Native TAP Ethernet driver"
+	depends on ARCH_POSIX
+	select ETH_NATIVE_POSIX_BACKWARDS_COMPAT_MENU
+	help
+	  Enable native_sim TAP ethernet driver. Note, this driver is run inside
+	  a process in your host system.
+
+if ETH_NATIVE_TAP
+
+config ETH_NATIVE_TAP_INTERFACE_COUNT
+	int "Number of network interfaces created"
+	default ETH_NATIVE_POSIX_INTERFACE_COUNT
+	range 1 32
+	help
+	  By default only one network interface is created. It is possible
+	  to create multiple interfaces in certain use cases. For example if
+	  multiple ports are defined in gPTP or PTP, then multiple network interfaces
+	  must be created here.
+
+config ETH_NATIVE_TAP_DRV_NAME
+	string "Ethernet driver name"
+	default ETH_NATIVE_POSIX_DRV_NAME
+	help
+	  This option sets the driver name and name of the network interface
+	  in your host system. If there are multiple network interfaces defined,
+	  then this value is used as a prefix and the interface names will be
+	  zeth0, zeth1, etc.
+
+config ETH_NATIVE_TAP_DEV_NAME
+	string "Host ethernet TUN/TAP device name"
+	default ETH_NATIVE_POSIX_DEV_NAME
+	help
+	  This option sets the TUN/TAP device name in your host system.
+
+config ETH_NATIVE_TAP_PTP_CLOCK
+	bool "PTP clock driver support"
+	default ETH_NATIVE_POSIX_PTP_CLOCK
+	select PTP_CLOCK
+	depends on NET_GPTP || PTP
+	help
+	  Enable PTP clock support.
+
+config ETH_NATIVE_TAP_RANDOM_MAC
+	bool "Random MAC address"
+	depends on ENTROPY_GENERATOR
+	default ETH_NATIVE_POSIX_RANDOM_MAC
+	help
+	  Generate a random MAC address dynamically.
+
+config ETH_NATIVE_TAP_VLAN_TAG_STRIP
+	bool "Strip VLAN tag from Rx frames"
+	default ETH_NATIVE_POSIX_VLAN_TAG_STRIP
+	depends on NET_VLAN
+	help
+	  Native TAP ethernet driver will strip of VLAN tag from
+	  Rx Ethernet frames and sets tag information in net packet
+	  metadata.
+
+config ETH_NATIVE_TAP_MAC_ADDR
+	string "MAC address for the interface"
+	default ETH_NATIVE_POSIX_MAC_ADDR
+	depends on !ETH_NATIVE_TAP_RANDOM_MAC
+	help
+	  Specify a MAC address for the ethernet interface in the form of
+	  six hex 8-bit chars separated by colons (e.g.:
+	  aa:33:cc:22:e2:c0). The default is an empty string, which
+	  means the code will make 00:00:5E:00:53:XX, where XX will be
+	  random.
+
+config ETH_NATIVE_TAP_RX_TIMEOUT
+	int "Ethernet RX timeout"
+	default ETH_NATIVE_POSIX_RX_TIMEOUT
+	range 1 100
+	help
+	  Native TAP ethernet driver repeatedly checks for new data.
+	  Specify how long the thread sleeps between these checks if no new data
+	  available.
+
+endif # ETH_NATIVE_TAP
+
+
+config ETH_NATIVE_POSIX
+	bool "Native POSIX Ethernet driver (deprecated)"
+	depends on ARCH_POSIX
+	select DEPRECATED
+	select ETH_NATIVE_TAP
+	select ETH_NATIVE_POSIX_BACKWARDS_COMPAT_MENU
+	help
+	  Deprecated, use ETH_NATIVE_TAP instead
+
+menuconfig ETH_NATIVE_POSIX_BACKWARDS_COMPAT_MENU
+	bool "Native POSIX Ethernet driver options (deprecated)"
+	depends on ARCH_POSIX
+
+if ETH_NATIVE_POSIX_BACKWARDS_COMPAT_MENU
+
+config ETH_NATIVE_POSIX_INTERFACE_COUNT
+	int "Number of network interfaces created (deprecated)"
+	default NET_GPTP_NUM_PORTS if NET_GPTP
+	default PTP_NUM_PORTS if PTP
+	default 1
+	range 1 32
+	help
+	  Deprecated, use ETH_NATIVE_TAP_INTERFACE_COUNT instead
+
+config ETH_NATIVE_POSIX_DRV_NAME
+	string "Ethernet driver name (deprecated)"
+	default "zeth"
+	help
+	  Deprecated, use ETH_NATIVE_TAP_DRV_NAME instead
+
+config ETH_NATIVE_POSIX_DEV_NAME
+	string "Host ethernet TUN/TAP device name (deprecated)"
+	default "/dev/net/tun"
+	help
+	  Deprecated, use ETH_NATIVE_TAP_DEV_NAME instead
+
+config ETH_NATIVE_POSIX_PTP_CLOCK
+	bool "PTP clock driver support (deprecated)"
+	default y if NET_GPTP || PTP
+	depends on NET_GPTP || PTP
+	help
+	  Deprecated, use ETH_NATIVE_TAP_PTP_CLOCK instead
+
+config ETH_NATIVE_POSIX_RANDOM_MAC
+	bool "Random MAC address (deprecated)"
+	depends on ENTROPY_GENERATOR
+	default y
+	help
+	  Deprecated, use ETH_NATIVE_TAP_RANDOM_MAC instead
+
+config ETH_NATIVE_POSIX_VLAN_TAG_STRIP
+	bool "Strip VLAN tag from Rx frames (deprecated)"
+	depends on NET_VLAN
+	help
+	  Deprecated, use ETH_NATIVE_TAP_VLAN_TAG_STRIP instead
+
+config ETH_NATIVE_POSIX_MAC_ADDR
+	string "MAC address for the interface (deprecated)"
+	default ""
+	depends on !ETH_NATIVE_POSIX_RANDOM_MAC
+	help
+	  Deprecated, use ETH_NATIVE_TAP_MAC_ADDR instead
+
+config ETH_NATIVE_POSIX_RX_TIMEOUT
+	int "Ethernet RX timeout (deprecated)"
+	default 1 if NET_GPTP
+	default 50
+	range 1 100
+	help
+	  Deprecated, use ETH_NATIVE_TAP_DEV_NAME instead
+
+endif # ETH_NATIVE_POSIX_BACKWARDS_COMPAT
diff --git a/drivers/ethernet/Kconfig.numaker b/drivers/ethernet/Kconfig.numaker
index a21462bac74..3a40c1d81af 100644
--- a/drivers/ethernet/Kconfig.numaker
+++ b/drivers/ethernet/Kconfig.numaker
@@ -9,6 +9,7 @@ config ETH_NUMAKER
 	select HAS_NUMAKER_ETH
 	select PINCTRL
 	depends on DT_HAS_NUVOTON_NUMAKER_ETHERNET_ENABLED
+	select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
 	help
 	  This option enables the Ethernet driver for Nuvoton NuMaker family of
 	  processors.
diff --git a/drivers/ethernet/Kconfig.nxp_enet b/drivers/ethernet/Kconfig.nxp_enet
new file mode 100644
index 00000000000..3b94a159214
--- /dev/null
+++ b/drivers/ethernet/Kconfig.nxp_enet
@@ -0,0 +1,77 @@
+# NXP ENET ethernet drivers configuration options
+
+# Copyright (c) 2016-2017 ARM Ltd
+# Copyright 2024-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config ETH_NXP_ENET
+	bool "NXP ENET Ethernet driver"
+	default y
+	depends on DT_HAS_NXP_ENET_MAC_ENABLED
+	select NOCACHE_MEMORY if CPU_HAS_DCACHE
+	select ARM_MPU if CPU_CORTEX_M7
+	select MDIO if DT_HAS_NXP_ENET_MDIO_ENABLED
+	select NET_POWER_MANAGEMENT if (PM_DEVICE && SOC_FAMILY_KINETIS)
+	select ETH_DSA_SUPPORT_DEPRECATED
+	select PINCTRL
+	help
+	  Enable NXP ENET Ethernet driver.
+
+
+if ETH_NXP_ENET
+
+config ETH_NXP_ENET_1G
+	bool "1G mode for ENET1G instance"
+	default y
+	depends on DT_HAS_NXP_ENET1G_ENABLED
+	help
+	  Enable the use of the ENET1G ethernet instance in 1G mode.
+
+config ETH_NXP_ENET_USE_DTCM_FOR_DMA_BUFFER
+	bool "Use DTCM for hardware DMA buffers"
+	default y
+	help
+	  Place the hardware DMA buffers into DTCM for better
+	  networking performance.
+
+config ETH_NXP_ENET_HW_ACCELERATION
+	bool "Hardware acceleration"
+	default y
+	help
+	  Enable hardware acceleration for the following:
+	  - IPv4, UDP and TCP checksum (both Rx and Tx)
+
+config ETH_NXP_ENET_RX_BUFFERS
+	int "Number of RX buffers for ethernet driver"
+	default 6
+	range 6 16
+	help
+	  Set the number of RX buffers provided to the NXP ENET driver.
+
+config ETH_NXP_ENET_TX_BUFFERS
+	int "Number of TX buffers for ethernet driver"
+	default 1
+	range 1 16
+	help
+	  Set the number of TX buffers provided to the NXP ENET driver.
+
+config ETH_NXP_ENET_RX_THREAD_STACK_SIZE
+	int "NXP ENET RX thread stack size"
+	default 1600
+	help
+	  ENET RX thread stack size in bytes.
+
+config ETH_NXP_ENET_RX_THREAD_PRIORITY
+	int "NXP ENET driver RX cooperative thread priority"
+	default 2
+	help
+	  ENET MAC Driver handles RX in cooperative workqueue thread.
+	  This options sets the priority of that thread.
+
+config ETH_NXP_ENET_RMII_EXT_CLK
+	bool "RMII clock from external sources"
+	help
+	  Setting this option will configure ENET clock block to feed RMII
+	  reference clock from external source (ENET_1588_CLKIN)
+
+endif # ETH_NXP_ENET
diff --git a/drivers/ethernet/Kconfig.nxp_imx_netc b/drivers/ethernet/Kconfig.nxp_imx_netc
deleted file mode 100644
index e636f53da47..00000000000
--- a/drivers/ethernet/Kconfig.nxp_imx_netc
+++ /dev/null
@@ -1,87 +0,0 @@
-# Copyright 2024 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-menuconfig ETH_NXP_IMX_NETC
-	bool "NXP IMX Ethernet and Network Controller (NETC) driver"
-	default y
-	depends on DT_HAS_NXP_IMX_NETC_PSI_ENABLED
-	select MDIO
-	select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
-	help
-	  Enable Ethernet and Network Controller (NETC) driver for NXP IMX SoCs.
-
-if ETH_NXP_IMX_NETC
-
-config ETH_NXP_IMX_MSGINTR
-	int "Message Interrupt module select"
-	default 1
-	help
-	  Message Interrupt module select.
-
-config ETH_NXP_IMX_RX_THREAD_PRIO
-	int "RX thread priority"
-	default 2
-	help
-	  RX thread priority. RX thread is a cooperative thread.
-
-config ETH_NXP_IMX_RX_THREAD_STACK_SIZE
-	int "RX thread stack size"
-	default 1500
-	help
-	  RX thread stack size.
-
-config ETH_NXP_IMX_RX_BUDGET
-	int "RX thread budget"
-	default 128
-	range 1 1024
-	help
-	  The budget parameter places a limit on the amount of work the driver may
-	  do in the RX thread before yielding the processor, in case there is more
-	  work to do. This is to prevent the RX thread to starve other threads. Each
-	  received frame counts as one unit of work.
-
-config ETH_NXP_IMX_TX_RING_NUM
-	int "TX ring number"
-	default 1
-	range 1 1023
-	help
-	  TX ring number used. The actual maximum value may varies from platforms.
-
-config ETH_NXP_IMX_TX_RING_LEN
-	int "TX ring length"
-	default 8
-	range 8 256
-	help
-	  Length of the TX ring. The value must be a multiple of 8.
-
-config ETH_NXP_IMX_TX_RING_BUF_SIZE
-	int "TX ring data buffer size"
-	default 1000
-	range 64 1536
-	help
-	  Size, in bytes, of the TX data buffer. The size must be big enough to
-	  store one complete Ethernet frame, and be a multiple of 8.
-
-config ETH_NXP_IMX_RX_RING_NUM
-	int "RX ring number"
-	default 1
-	range 1 1023
-	help
-	  RX ring number used. The actual maximum value may varies from platforms.
-
-config ETH_NXP_IMX_RX_RING_LEN
-	int "RX ring length"
-	default 8
-	range 8 256
-	help
-	  Length of the RX ring. The value must be a multiple of 8.
-
-config ETH_NXP_IMX_RX_RING_BUF_SIZE
-	int "RX ring data buffer size"
-	default 1518
-	range 64 1536
-	help
-	  Size, in bytes, of the RX data buffer. The size must be big enough to
-	  store one complete Ethernet frame, and be a multiple of 8.
-
-endif # ETH_NXP_IMX_NETC
diff --git a/drivers/ethernet/Kconfig.sam_gmac b/drivers/ethernet/Kconfig.sam_gmac
index aecb9488f25..60403612bbb 100644
--- a/drivers/ethernet/Kconfig.sam_gmac
+++ b/drivers/ethernet/Kconfig.sam_gmac
@@ -11,7 +11,7 @@ menuconfig ETH_SAM_GMAC
 		   DT_HAS_ATMEL_SAM0_GMAC_ENABLED
 	select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
 	select MDIO
-	select ETH_DSA_SUPPORT
+	select ETH_DSA_SUPPORT_DEPRECATED
 	select PINCTRL
 	help
 	  Enable Atmel SAM MCU Family Ethernet driver.
@@ -27,8 +27,7 @@ DT_ETH_SAM_GMAC_NQ := $(dt_node_int_prop_int,$(DT_ETH_SAM_GMAC_PATH),num-queues)
 config ETH_SAM_GMAC_QUEUES
 	int "Number of active hardware TX and RX queues"
 	default 1
-	range 1 $(DT_ETH_SAM_GMAC_NQ) if SOC_SERIES_SAME70 || \
-						SOC_SERIES_SAMV71 || \
+	range 1 $(DT_ETH_SAM_GMAC_NQ) if SOC_SERIES_SAMX7X || \
 						SOC_SERIES_SAM4E || \
 						SOC_SERIES_SAME54
 	help
diff --git a/drivers/ethernet/Kconfig.stm32_hal b/drivers/ethernet/Kconfig.stm32_hal
index 1511498e96b..fc9beba2d90 100644
--- a/drivers/ethernet/Kconfig.stm32_hal
+++ b/drivers/ethernet/Kconfig.stm32_hal
@@ -9,11 +9,12 @@ menuconfig ETH_STM32_HAL
 	default y
 	depends on DT_HAS_ST_STM32_ETHERNET_ENABLED
 	select USE_STM32_HAL_ETH
-	select NOCACHE_MEMORY if SOC_SERIES_STM32H7X && CPU_CORTEX_M7
+	select USE_STM32_HAL_RIF if SOC_SERIES_STM32N6X
+	select NOCACHE_MEMORY if (SOC_SERIES_STM32H7X && CPU_CORTEX_M7) || SOC_SERIES_STM32N6X
 	select HWINFO
-	select ETH_DSA_SUPPORT
+	select ETH_DSA_SUPPORT_DEPRECATED
 	select PINCTRL
-	select MDIO if SOC_SERIES_STM32H5X || SOC_SERIES_STM32H7X
+	select MDIO if DT_HAS_ST_STM32_MDIO_ENABLED
 	imply CRC
 	help
 	  Enable STM32 HAL based Ethernet driver. It is available for
@@ -26,7 +27,8 @@ choice ETH_STM32_HAL_API_VERSION
 
 config ETH_STM32_HAL_API_V2
 	bool "Use official STM32Cube HAL driver"
-	depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32H5X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X
+	depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32H5X || SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32N6X
+	select USE_STM32_HAL_ETH_EX if SOC_SERIES_STM32N6X
 	help
 	  Use the official STM32Cube HAL driver instead of the legacy one.
 
@@ -45,6 +47,14 @@ config ETH_STM32_HAL_RX_THREAD_STACK_SIZE
 	help
 	  RX thread stack size
 
+config ETH_STM32_HAL_RX_THREAD_PREEMPTIVE
+	bool "STM32 Ethernet RX Thread pre-emptive [EXPERIMENTAL]"
+	default y if NET_TC_THREAD_PREEMPTIVE
+	depends on PREEMPT_ENABLED
+	select EXPERIMENTAL
+	help
+	  With pre-emptive threads, the thread can be pre-empted.
+
 config ETH_STM32_HAL_RX_THREAD_PRIO
 	int "STM32 Ethernet RX Thread Priority"
 	default 2
@@ -64,31 +74,6 @@ config ETH_STM32_HAL_USE_DTCM_FOR_DMA_BUFFER
 	  When this option is activated, the buffers for DMA transfer are
 	  moved from SRAM to the DTCM (Data Tightly Coupled Memory).
 
-config ETH_STM32_HAL_PHY_ADDRESS
-	int "Phy address"
-	default 0
-	help
-	  The phy address to use.
-
-config ETH_STM32_HAL_MII
-	bool "Use MII interface"
-	help
-	  Use the MII physical interface instead of RMII.
-
-config ETH_STM32_CARRIER_CHECK_RX_IDLE_TIMEOUT_MS
-	int "Carrier check timeout period (ms)"
-	default 500
-	range 100 30000
-	help
-	  Set the RX idle timeout period in milliseconds after which the
-	  PHY's carrier status is re-evaluated.
-
-config ETH_STM32_AUTO_NEGOTIATION_ENABLE
-	bool "Autonegotiation mode"
-	default y
-	help
-	  Enable this if using autonegotiation
-
 config ETH_STM32_HW_CHECKSUM
 	bool "Use TX and RX hardware checksum"
 	depends on !SOC_SERIES_STM32H5X
@@ -97,35 +82,20 @@ config ETH_STM32_HW_CHECKSUM
 	  performances.
 	  See reference manual for more information on this feature.
 
-if !ETH_STM32_AUTO_NEGOTIATION_ENABLE
-
-config ETH_STM32_SPEED_10M
-	bool "Set speed to 10 Mbps when autonegotiation is disabled"
-	help
-	  Set this if using 10 Mbps and when autonegotiation is disabled, otherwise speed
-	  is 100 Mbps
-
-config ETH_STM32_MODE_HALFDUPLEX
-	bool "Half duplex mode"
-	help
-	  Set this if using half duplex when autonegotiation is disabled otherwise
-	  duplex mode is full duplex
-
-endif # !ETH_STM32_AUTO_NEGOTIATION_ENABLE
-
-if SOC_SERIES_STM32F7X || SOC_SERIES_STM32H7X || SOC_SERIES_STM32H5X
-
-config PTP_CLOCK_STM32_HAL
+menuconfig PTP_CLOCK_STM32_HAL
 	bool "STM32 HAL PTP clock driver support"
 	default y
 	depends on PTP_CLOCK || NET_L2_PTP
+	depends on ETH_STM32_HAL_API_V2
+	depends on SOC_SERIES_STM32F7X || SOC_SERIES_STM32H7X || SOC_SERIES_STM32H5X
 	help
 	  Enable STM32 PTP clock support.
 
+if PTP_CLOCK_STM32_HAL
+
 config ETH_STM32_HAL_PTP_CLOCK_SRC_HZ
 	int "Frequency of the clock source for the PTP timer"
 	default 50000000
-	depends on PTP_CLOCK_STM32_HAL
 	help
 	  Set the frequency in Hz sourced to the PTP timer.
 	  If the value is set properly, the timer will be accurate.
@@ -133,27 +103,24 @@ config ETH_STM32_HAL_PTP_CLOCK_SRC_HZ
 config ETH_STM32_HAL_PTP_CLOCK_ADJ_MIN_PCT
 	int "Lower bound of clock frequency adjustment (in percent)"
 	default 90
-	depends on PTP_CLOCK_STM32_HAL
 	help
 	  Specifies lower bound of PTP clock rate adjustment.
 
 config ETH_STM32_HAL_PTP_CLOCK_ADJ_MAX_PCT
 	int "Upper bound of clock frequency adjustment (in percent)"
 	default 110
-	depends on PTP_CLOCK_STM32_HAL
 	help
 	  Specifies upper bound of PTP clock rate adjustment.
 
 config ETH_STM32_HAL_PTP_CLOCK_INIT_PRIO
 	int
 	default 85
-	depends on PTP_CLOCK_STM32_HAL
 	help
 	  STM32 PTP Clock initialization priority level. There is
 	  a dependency from the network stack that this device
 	  initializes before network stack (NET_INIT_PRIO).
 
-endif # SOC_SERIES_STM32F7X || SOC_SERIES_STM32H7X || SOC_SERIES_STM32H5X
+endif # PTP_CLOCK_STM32_HAL
 
 config ETH_STM32_MULTICAST_FILTER
 	bool "Multicast hash filter support"
diff --git a/drivers/ethernet/Kconfig.sy1xx_mac b/drivers/ethernet/Kconfig.sy1xx_mac
new file mode 100644
index 00000000000..8493aa5305f
--- /dev/null
+++ b/drivers/ethernet/Kconfig.sy1xx_mac
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+config ETH_SY1XX
+	bool "Sensry SY1XX Ethernet driver"
+	default y
+	depends on DT_HAS_SENSRY_SY1XX_MAC_ENABLED
+	select MDIO
+	select PINCTRL
+	help
+	  Enable Sensry SY1XX Ethernet MAC driver.
diff --git a/drivers/ethernet/Kconfig.xilinx_axienet b/drivers/ethernet/Kconfig.xilinx_axienet
new file mode 100644
index 00000000000..bec8ab31274
--- /dev/null
+++ b/drivers/ethernet/Kconfig.xilinx_axienet
@@ -0,0 +1,41 @@
+#
+#Xilinx AXI 1G / 2.5G Ethernet Subsystem
+#
+#Copyright(c) 2024, CISPA Helmholtz Center for Information Security
+#SPDX-License-Identifier: Apache-2.0
+#
+
+config ETH_XILINX_AXIENET
+	bool "Xilinx AXI Ethernet Driver"
+	default y
+	depends on DT_HAS_XLNX_AXI_ETHERNET_1_00_A_ENABLED
+	depends on DMA_XILINX_AXI_DMA
+	help
+		Enable Xilinx 1G / 2.5G AXI Ethernet driver,
+		commonly found on FPGAs.
+
+config ETH_XILINX_AXIENET_BUFFER_NUM_TX
+	int "Number of buffers for concurrent transmission (TX)."
+	depends on ETH_XILINX_AXIENET
+	default DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_TX
+	range 2 DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_TX
+	help
+		Number of buffers for transmission allocated in the Xilinx AXI Ethernet driver.
+		This limits how many transmissions can be in-flight at the same time.
+		This cannot exceed the number of available TX buffers in the AXI DMA. However,
+		in scenarios with multiple AXI DMAs for different purposes in the system, it
+		may be desirable to reduce the number of concurrent transmissions to conserve
+		resources.
+
+config ETH_XILINX_AXIENET_BUFFER_NUM_RX
+	int "Number of buffers for concurrent reception (RX)."
+	depends on ETH_XILINX_AXIENET
+	default DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_RX
+	range 2 DMA_XILINX_AXI_DMA_SG_DESCRIPTOR_NUM_RX
+	help
+		Number of buffers for reception allocated in the Xilinx AXI Ethernet driver.
+		This limits how many transmissions can be in-flight at the same time.
+		This cannot exceed the number of available RX buffers in the AXI DMA. However,
+		in scenarios with multiple AXI DMAs for different purposes in the system, it
+		may be desirable to reduce the number of concurrent transmissions to conserve
+		resources.
diff --git a/drivers/ethernet/dsa/CMakeLists.txt b/drivers/ethernet/dsa/CMakeLists.txt
new file mode 100644
index 00000000000..1ade5f741d9
--- /dev/null
+++ b/drivers/ethernet/dsa/CMakeLists.txt
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library_sources_ifdef(CONFIG_DSA_KSZ8XXX	dsa_ksz8xxx.c)
diff --git a/drivers/ethernet/dsa/Kconfig b/drivers/ethernet/dsa/Kconfig
new file mode 100644
index 00000000000..b7773e7476b
--- /dev/null
+++ b/drivers/ethernet/dsa/Kconfig
@@ -0,0 +1,95 @@
+# Distributed Switch Architecture [DSA] configuration options
+
+# Copyright (c) 2020 DENX Software Engineering GmbH
+#               Lukasz Majewski <lukma@denx.de>
+# SPDX-License-Identifier: Apache-2.0
+
+config ETH_DSA_SUPPORT_DEPRECATED
+	bool
+	help
+	  Set by an ethernet driver that supports DSA. This is obsolete,
+	  and only used for legacy dsa device.
+
+menuconfig NET_DSA
+	bool "Distributed Switch Architecture support"
+	help
+	  Enable Distributed Switch Architecture support.
+
+if NET_DSA
+
+config NET_DSA_DEPRECATED
+	bool "Distributed Switch Architecture support for legacy device"
+	select DEPRECATED
+	depends on ETH_DSA_SUPPORT_DEPRECATED
+	help
+	  This is obsolete, and only used for legacy dsa device.
+
+config DSA_PORT_MAX_COUNT
+	int "DSA port max count"
+	default 8
+	help
+	  Set DSA port max count.
+
+config DSA_KSZ8XXX
+	bool
+
+config DSA_KSZ8794
+	bool "Support for KSZ8794"
+	default y
+	depends on DT_HAS_MICROCHIP_KSZ8794_ENABLED
+	select DSA_KSZ8XXX
+	select SPI if $(dt_compat_on_bus,$(DT_COMPAT_MICROCHIP_KSZ8794),spi)
+	help
+	  Add support for KSZ8794 DSA device driver.
+
+config DSA_KSZ8863
+	bool "Support for KSZ8863"
+	default y
+	depends on DT_HAS_MICROCHIP_KSZ8863_ENABLED
+	select DSA_KSZ8XXX
+	select SPI if $(dt_compat_on_bus,$(DT_COMPAT_MICROCHIP_KSZ8863),spi)
+	help
+	  Add support for KSZ8863 DSA device driver.
+
+config DSA_KSZ8463
+	bool "Support for KSZ8463"
+	default y
+	depends on DT_HAS_MICROCHIP_KSZ8463_ENABLED
+	select DSA_KSZ8XXX
+	select SPI if $(dt_compat_on_bus,$(DT_COMPAT_MICROCHIP_KSZ8463),spi)
+	help
+	  Add support for KSZ8463 DSA device driver.
+
+config DSA_KSZ_TAIL_TAGGING
+	bool "Support for tail tagging"
+	depends on DSA_KSZ8794 || DSA_KSZ8863 || DSA_KSZ8463
+	help
+	  Add support for tail tagging on DSA device.
+
+config DSA_TAG_SIZE
+	int "DSA tag size in bytes"
+	default 1 if DSA_KSZ8794 || DSA_KSZ8863 || DSA_KSZ8463
+	default 0
+	depends on DSA_KSZ_TAIL_TAGGING
+	help
+	  Set the DSA tag length in bytes.
+
+config DSA_KSZ_PORT_ISOLATING
+	bool "Support for ports isolating"
+	depends on DSA_KSZ8794 || DSA_KSZ8863 || DSA_KSZ8463
+	help
+	  Add support for traffic isolation on DSA slave ports
+
+config DSA_SPI
+	bool "Support for PHY SPI interface"
+	depends on SPI && (DSA_KSZ8794 || DSA_KSZ8863 || DSA_KSZ8463)
+	help
+	  Use SPI bus to communicate with PHY
+
+module = NET_DSA
+module-dep = NET_LOG
+module-str = Log level for DSA
+module-help = Enables core DSA code to output debug messages.
+source "subsys/net/Kconfig.template.log_config.net"
+
+endif # NET_DSA
diff --git a/drivers/ethernet/dsa/dsa_ksz8463.h b/drivers/ethernet/dsa/dsa_ksz8463.h
new file mode 100644
index 00000000000..b57096cbac3
--- /dev/null
+++ b/drivers/ethernet/dsa/dsa_ksz8463.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2023 Meshium
+ *               Aleksandr Senin <al@meshium.net>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __DSA_KSZ8463_H__
+#define __DSA_KSZ8463_H__
+
+/* SPI commands */
+#define KSZ8463_SPI_CMD_WR (BIT(7))
+#define KSZ8463_SPI_CMD_RD (0)
+
+#define KSZ8463_REG_ADDR_HI_PART(x)	(((x) & 0x7FF) >> 4)
+#define KSZ8463_REG_ADDR_LO_PART(x)	(((x) & 0x00C) << 4)
+#define KSZ8463_SPI_BYTE_ENABLE(x)	(BIT(((x) & 0x3) + 2))
+
+/* PHY registers */
+#define KSZ8463_BMCR                                 0x00
+#define KSZ8463_BMSR                                 0x01
+#define KSZ8463_PHYID1                               0x02
+#define KSZ8463_PHYID2                               0x03
+#define KSZ8463_ANAR                                 0x04
+#define KSZ8463_ANLPAR                               0x05
+#define KSZ8463_LINKMD                               0x1D
+#define KSZ8463_PHYSCS                               0x1F
+
+/* SWITCH registers */
+#define KSZ8463_CHIP_ID0                             0x01
+#define KSZ8463_CHIP_ID1                             0x00
+#define KSZ8463_GLOBAL_CTRL_1L			     0x02
+#define KSZ8463_GLOBAL_CTRL_1H			     0x03
+#define KSZ8463_GLOBAL_CTRL_2L			     0x04
+#define KSZ8463_GLOBAL_CTRL_2H			     0x05
+#define KSZ8463_GLOBAL_CTRL_3L			     0x06
+#define KSZ8463_GLOBAL_CTRL_3H			     0x07
+#define KSZ8463_GLOBAL_CTRL_6L			     0x0C
+#define KSZ8463_GLOBAL_CTRL_6H			     0x0D
+#define KSZ8463_GLOBAL_CTRL_7L			     0x0E
+#define KSZ8463_GLOBAL_CTRL_7H			     0x0F
+#define KSZ8463_GLOBAL_CTRL_8L			     0xAC
+#define KSZ8463_GLOBAL_CTRL_8H			     0xAD
+#define KSZ8463_GLOBAL_CTRL_9L			     0xAE
+#define KSZ8463_GLOBAL_CTRL_9H			     0xAF
+
+#define KSZ8463_CFGR_L				     0xD8
+
+#define KSZ8463_DSP_CNTRL_6L			     0x734
+#define KSZ8463_DSP_CNTRL_6H			     0x735
+
+#define KSZ8463_GLOBAL_CTRL1_TAIL_TAG_EN             BIT(0)
+#define KSZ8463_GLOBAL_CTRL2_LEG_MAX_PKT_SIZ_CHK_ENA BIT(1)
+
+#define KSZ8463_CTRL2L_PORTn(n)                      (0x6E + ((n) * 0x18))
+#define KSZ8463_CTRL2L_VLAN_PORTS_MASK		     0xF8
+#define KSZ8463_CTRL2H_PORTn(n)                      (0x6F + ((n) * 0x18))
+#define KSZ8463_CTRL2_TRANSMIT_EN                    BIT(2)
+#define KSZ8463_CTRL2_RECEIVE_EN                     BIT(1)
+#define KSZ8463_CTRL2_LEARNING_DIS                   BIT(0)
+
+#define KSZ8463_STAT2_PORTn(n)                       (0x80 + ((n) * 0x18))
+#define KSZ8463_STAT2_LINK_GOOD                      BIT(5)
+
+#define KSZ8463_CHIP_ID0_ID_DEFAULT                  0x84
+#define KSZ8463_CHIP_ID1_ID_DEFAULT                  0x43
+#define KSZ8463F_CHIP_ID1_ID_DEFAULT                 0x53
+#define KSZ8463_RESET_REG	                     0x127
+#define KSZ8463_SOFTWARE_RESET_SET                   BIT(0)
+#define KSZ8463_SOFTWARE_RESET_CLEAR                 0
+
+#define KSZ8463_P2_COPPER_MODE			     BIT(7)
+#define KSZ8463_P1_COPPER_MODE			     BIT(6)
+#define KSZ8463_RECV_ADJ			     BIT(5)
+
+enum {
+	/* LAN ports for the ksz8463 switch */
+	KSZ8463_PORT1 = 0,
+	KSZ8463_PORT2,
+	/* SWITCH <-> CPU port */
+	KSZ8463_PORT3,
+};
+
+#define KSZ8463_REG_IND_CTRL_0                        0x31
+#define KSZ8463_REG_IND_CTRL_1                        0x30
+#define KSZ8463_REG_IND_DATA_8                        0x26
+#define KSZ8463_REG_IND_DATA_7                        0x2B
+#define KSZ8463_REG_IND_DATA_6                        0x2A
+#define KSZ8463_REG_IND_DATA_5                        0x29
+#define KSZ8463_REG_IND_DATA_4                        0x28
+#define KSZ8463_REG_IND_DATA_3                        0x2F
+#define KSZ8463_REG_IND_DATA_2                        0x2E
+#define KSZ8463_REG_IND_DATA_1                        0x2D
+#define KSZ8463_REG_IND_DATA_0                        0x2C
+
+#define KSZ8463_STATIC_MAC_TABLE_VALID                BIT(3)
+#define KSZ8463_STATIC_MAC_TABLE_OVRD                 BIT(4)
+#define KSZ8463_STATIC_MAC_TABLE_USE_FID              BIT(5)
+
+#define KSZ8XXX_CHIP_ID0                        KSZ8463_CHIP_ID0
+#define KSZ8XXX_CHIP_ID1                        KSZ8463_CHIP_ID1
+#define KSZ8XXX_CHIP_ID0_ID_DEFAULT             KSZ8463_CHIP_ID0_ID_DEFAULT
+#define KSZ8XXX_CHIP_ID1_ID_DEFAULT             KSZ8463F_CHIP_ID1_ID_DEFAULT
+#define KSZ8XXX_FIRST_PORT                      KSZ8463_PORT1
+#define KSZ8XXX_LAST_PORT                       KSZ8463_PORT3
+#define KSZ8XXX_CPU_PORT                        KSZ8463_PORT3
+#define KSZ8XXX_REG_IND_CTRL_0                  KSZ8463_REG_IND_CTRL_0
+#define KSZ8XXX_REG_IND_CTRL_1                  KSZ8463_REG_IND_CTRL_1
+#define KSZ8XXX_REG_IND_DATA_8                  KSZ8463_REG_IND_DATA_8
+#define KSZ8XXX_REG_IND_DATA_7                  KSZ8463_REG_IND_DATA_7
+#define KSZ8XXX_REG_IND_DATA_6                  KSZ8463_REG_IND_DATA_6
+#define KSZ8XXX_REG_IND_DATA_5                  KSZ8463_REG_IND_DATA_5
+#define KSZ8XXX_REG_IND_DATA_4                  KSZ8463_REG_IND_DATA_4
+#define KSZ8XXX_REG_IND_DATA_3                  KSZ8463_REG_IND_DATA_3
+#define KSZ8XXX_REG_IND_DATA_2                  KSZ8463_REG_IND_DATA_2
+#define KSZ8XXX_REG_IND_DATA_1                  KSZ8463_REG_IND_DATA_1
+#define KSZ8XXX_REG_IND_DATA_0                  KSZ8463_REG_IND_DATA_0
+#define KSZ8XXX_STATIC_MAC_TABLE_VALID          KSZ8463_STATIC_MAC_TABLE_VALID
+#define KSZ8XXX_STATIC_MAC_TABLE_OVRD           KSZ8463_STATIC_MAC_TABLE_OVRD
+#define KSZ8XXX_STAT2_LINK_GOOD                 KSZ8463_STAT2_LINK_GOOD
+#define KSZ8XXX_RESET_REG                       KSZ8463_RESET_REG
+#define KSZ8XXX_RESET_SET                       KSZ8463_SOFTWARE_RESET_SET
+#define KSZ8XXX_RESET_CLEAR                     KSZ8463_SOFTWARE_RESET_CLEAR
+#define KSZ8XXX_STAT2_PORTn                     KSZ8463_STAT2_PORTn
+#define KSZ8XXX_CTRL1_PORTn			KSZ8463_CTRL2L_PORTn
+#define KSZ8XXX_CTRL1_VLAN_PORTS_MASK		KSZ8463_CTRL2L_VLAN_PORTS_MASK
+#define KSZ8XXX_SPI_CMD_RD                      KSZ8463_SPI_CMD_RD
+#define KSZ8XXX_SPI_CMD_WR                      KSZ8463_SPI_CMD_WR
+#define KSZ8XXX_SOFT_RESET_DURATION             1000
+#define KSZ8XXX_HARD_RESET_WAIT                 10000
+
+#endif /* __DSA_KSZ8463_H__ */
diff --git a/drivers/ethernet/dsa_ksz8794.h b/drivers/ethernet/dsa/dsa_ksz8794.h
similarity index 98%
rename from drivers/ethernet/dsa_ksz8794.h
rename to drivers/ethernet/dsa/dsa_ksz8794.h
index 93ed81e5bac..d4a1c2f578b 100644
--- a/drivers/ethernet/dsa_ksz8794.h
+++ b/drivers/ethernet/dsa/dsa_ksz8794.h
@@ -234,6 +234,8 @@
 #define KSZ8794_GLOBAL_CTRL10_TAIL_TAG_EN            BIT(1)
 #define KSZ8794_GLOBAL_CTRL2_LEG_MAX_PKT_SIZ_CHK_DIS BIT(1)
 
+#define KSZ8794_CTRL1_PORTn(n)                       (0x11 + ((n) * 0x10))
+#define KSZ8794_CTRL1_VLAN_PORTS_MASK		     0xE0
 #define KSZ8794_CTRL2_PORTn(n)                       (0x12 + ((n) * 0x10))
 #define KSZ8794_CTRL2_TRANSMIT_EN                    BIT(2)
 #define KSZ8794_CTRL2_RECEIVE_EN                     BIT(1)
@@ -321,6 +323,8 @@ enum {
 #define KSZ8XXX_RESET_SET                       KSZ8794_PWR_MGNT_MODE_SOFT_DOWN
 #define KSZ8XXX_RESET_CLEAR                     0
 #define KSZ8XXX_STAT2_PORTn                     KSZ8794_STAT2_PORTn
+#define KSZ8XXX_CTRL1_PORTn			KSZ8794_CTRL1_PORTn
+#define KSZ8XXX_CTRL1_VLAN_PORTS_MASK		KSZ8794_CTRL1_VLAN_PORTS_MASK
 #define KSZ8XXX_SPI_CMD_RD                      KSZ8794_SPI_CMD_RD
 #define KSZ8XXX_SPI_CMD_WR                      KSZ8794_SPI_CMD_WR
 #define KSZ8XXX_SOFT_RESET_DURATION                     1000
diff --git a/drivers/ethernet/dsa_ksz8863.h b/drivers/ethernet/dsa/dsa_ksz8863.h
similarity index 97%
rename from drivers/ethernet/dsa_ksz8863.h
rename to drivers/ethernet/dsa/dsa_ksz8863.h
index 602662ee1eb..d523da92615 100644
--- a/drivers/ethernet/dsa_ksz8863.h
+++ b/drivers/ethernet/dsa/dsa_ksz8863.h
@@ -94,6 +94,8 @@
 #define KSZ8863_GLOBAL_CTRL1_TAIL_TAG_EN             BIT(6)
 #define KSZ8863_GLOBAL_CTRL2_LEG_MAX_PKT_SIZ_CHK_ENA BIT(1)
 
+#define KSZ8863_CTRL1_PORTn(n)                       (0x11 + ((n) * 0x10))
+#define KSZ8863_CTRL1_VLAN_PORTS_MASK                0xF8
 #define KSZ8863_CTRL2_PORTn(n)                       (0x12 + ((n) * 0x10))
 #define KSZ8863_CTRL2_TRANSMIT_EN                    BIT(2)
 #define KSZ8863_CTRL2_RECEIVE_EN                     BIT(1)
@@ -157,6 +159,8 @@ enum {
 #define KSZ8XXX_RESET_SET                       KSZ8863_SOFTWARE_RESET_SET
 #define KSZ8XXX_RESET_CLEAR                     KSZ8863_SOFTWARE_RESET_CLEAR
 #define KSZ8XXX_STAT2_PORTn                     KSZ8863_STAT2_PORTn
+#define KSZ8XXX_CTRL1_PORTn			KSZ8863_CTRL1_PORTn
+#define KSZ8XXX_CTRL1_VLAN_PORTS_MASK		KSZ8863_CTRL1_VLAN_PORTS_MASK
 #define KSZ8XXX_SPI_CMD_RD                      KSZ8863_SPI_CMD_RD
 #define KSZ8XXX_SPI_CMD_WR                      KSZ8863_SPI_CMD_WR
 #define KSZ8XXX_SOFT_RESET_DURATION             1000
diff --git a/drivers/ethernet/dsa_ksz8xxx.c b/drivers/ethernet/dsa/dsa_ksz8xxx.c
similarity index 91%
rename from drivers/ethernet/dsa_ksz8xxx.c
rename to drivers/ethernet/dsa/dsa_ksz8xxx.c
index 9cf136f7b01..41b3f45d355 100644
--- a/drivers/ethernet/dsa_ksz8xxx.c
+++ b/drivers/ethernet/dsa/dsa_ksz8xxx.c
@@ -30,6 +30,9 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_ETHERNET_LOG_LEVEL);
 #elif CONFIG_DSA_KSZ8794
 #define DT_DRV_COMPAT microchip_ksz8794
 #include "dsa_ksz8794.h"
+#elif CONFIG_DSA_KSZ8463
+#define DT_DRV_COMPAT microchip_ksz8463
+#include "dsa_ksz8463.h"
 #else
 #error "Unsupported KSZ chipset"
 #endif
@@ -59,9 +62,15 @@ static void dsa_ksz8xxx_write_reg(const struct ksz8xxx_data *pdev,
 		.count = 1
 	};
 
+#if CONFIG_DSA_KSZ8463
+	buf[0] = KSZ8XXX_SPI_CMD_WR | KSZ8463_REG_ADDR_HI_PART(reg_addr);
+	buf[1] = KSZ8463_REG_ADDR_LO_PART(reg_addr) | KSZ8463_SPI_BYTE_ENABLE(reg_addr);
+	buf[2] = value;
+#else
 	buf[0] = KSZ8XXX_SPI_CMD_WR | ((reg_addr >> 7) & 0x1F);
 	buf[1] = (reg_addr << 1) & 0xFE;
 	buf[2] = value;
+#endif
 
 	spi_write_dt(&pdev->spi, &tx);
 #endif
@@ -91,9 +100,15 @@ static void dsa_ksz8xxx_read_reg(const struct ksz8xxx_data *pdev,
 		.count = 1
 	};
 
+#if CONFIG_DSA_KSZ8463
+	buf[0] = KSZ8XXX_SPI_CMD_RD | KSZ8463_REG_ADDR_HI_PART(reg_addr);
+	buf[1] = KSZ8463_REG_ADDR_LO_PART(reg_addr) | KSZ8463_SPI_BYTE_ENABLE(reg_addr);
+	buf[2] = 0;
+#else
 	buf[0] = KSZ8XXX_SPI_CMD_RD | ((reg_addr >> 7) & 0x1F);
 	buf[1] = (reg_addr << 1) & 0xFE;
 	buf[2] = 0x0;
+#endif
 
 	if (!spi_transceive_dt(&pdev->spi, &tx, &rx)) {
 		*value = buf[2];
@@ -153,7 +168,12 @@ static int dsa_ksz8xxx_probe(struct ksz8xxx_data *pdev)
 	dsa_ksz8xxx_read_reg(pdev, KSZ8XXX_CHIP_ID1, &val[1]);
 
 	if (val[0] != KSZ8XXX_CHIP_ID0_ID_DEFAULT ||
+#if CONFIG_DSA_KSZ8463
+	    (val[1] != KSZ8463_CHIP_ID1_ID_DEFAULT &&
+	    val[1] != KSZ8463F_CHIP_ID1_ID_DEFAULT)) {
+#else
 	    val[1] != KSZ8XXX_CHIP_ID1_ID_DEFAULT) {
+#endif
 		LOG_ERR("Chip ID mismatch. "
 			"Expected %02x%02x but found %02x%02x",
 			KSZ8XXX_CHIP_ID0_ID_DEFAULT,
@@ -163,7 +183,7 @@ static int dsa_ksz8xxx_probe(struct ksz8xxx_data *pdev)
 		return -ENODEV;
 	}
 
-	LOG_DBG("KSZ8794: ID0: 0x%x ID1: 0x%x timeout: %d", val[1], val[0],
+	LOG_DBG("KSZ8794: ID0: 0x%x ID1: 0x%x timeout: %d", val[0], val[1],
 		timeout);
 
 	return 0;
@@ -260,6 +280,79 @@ static int dsa_ksz8xxx_read_static_mac_table(struct ksz8xxx_data *pdev,
 	return 0;
 }
 
+#if defined(CONFIG_DSA_KSZ_PORT_ISOLATING)
+static int dsa_ksz8xxx_port_isolate(const struct ksz8xxx_data *pdev)
+{
+	uint8_t tmp, i;
+
+	for (i = KSZ8XXX_FIRST_PORT; i < KSZ8XXX_LAST_PORT; i++) {
+		dsa_ksz8xxx_read_reg(pdev, KSZ8XXX_CTRL1_PORTn(i), &tmp);
+		tmp &= KSZ8XXX_CTRL1_VLAN_PORTS_MASK;
+		tmp |= 1 << KSZ8XXX_CPU_PORT | 1 << i;
+		dsa_ksz8xxx_write_reg(pdev, KSZ8XXX_CTRL1_PORTn(i), tmp);
+	}
+
+	dsa_ksz8xxx_read_reg(pdev, KSZ8XXX_CTRL1_PORTn(KSZ8XXX_CPU_PORT),
+			     &tmp);
+	tmp |= ~KSZ8XXX_CTRL1_VLAN_PORTS_MASK;
+	dsa_ksz8xxx_write_reg(pdev, KSZ8XXX_CTRL1_PORTn(KSZ8XXX_CPU_PORT),
+			      tmp);
+
+	return 0;
+}
+#endif
+
+#if CONFIG_DSA_KSZ8463
+static int dsa_ksz8xxx_switch_setup(struct ksz8xxx_data *pdev)
+{
+	uint8_t tmp, i;
+
+	dsa_ksz8xxx_read_reg(pdev, KSZ8XXX_CHIP_ID1, &tmp);
+
+	if (tmp == KSZ8463F_CHIP_ID1_ID_DEFAULT) {
+		dsa_ksz8xxx_read_reg(pdev, KSZ8463_CFGR_L, &tmp);
+		tmp &= ~KSZ8463_P1_COPPER_MODE;
+		tmp &= ~KSZ8463_P2_COPPER_MODE;
+		dsa_ksz8xxx_write_reg(pdev, KSZ8463_CFGR_L, tmp);
+		dsa_ksz8xxx_read_reg(pdev, KSZ8463_DSP_CNTRL_6H, &tmp);
+		tmp &= ~KSZ8463_RECV_ADJ;
+		dsa_ksz8xxx_write_reg(pdev, KSZ8463_DSP_CNTRL_6H, tmp);
+	}
+
+	/*
+	 * Loop through ports - The same setup when tail tagging is enabled or
+	 * disabled.
+	 */
+	for (i = KSZ8XXX_FIRST_PORT; i <= KSZ8XXX_LAST_PORT; i++) {
+
+		/* Enable transmission, reception and switch address learning */
+		dsa_ksz8xxx_read_reg(pdev, KSZ8463_CTRL2H_PORTn(i), &tmp);
+		tmp |= KSZ8463_CTRL2_TRANSMIT_EN;
+		tmp |= KSZ8463_CTRL2_RECEIVE_EN;
+		tmp &= ~KSZ8463_CTRL2_LEARNING_DIS;
+		dsa_ksz8xxx_write_reg(pdev, KSZ8463_CTRL2H_PORTn(i), tmp);
+	}
+
+#if defined(CONFIG_DSA_KSZ_TAIL_TAGGING)
+	/* Enable tail tag feature */
+	dsa_ksz8xxx_read_reg(pdev, KSZ8463_GLOBAL_CTRL_8H, &tmp);
+	tmp |= KSZ8463_GLOBAL_CTRL1_TAIL_TAG_EN;
+	dsa_ksz8xxx_write_reg(pdev, KSZ8463_GLOBAL_CTRL_8H, tmp);
+#else
+	/* Disable tail tag feature */
+	dsa_ksz8xxx_read_reg(pdev, KSZ8463_GLOBAL_CTRL_8H, &tmp);
+	tmp &= ~KSZ8463_GLOBAL_CTRL1_TAIL_TAG_EN;
+	dsa_ksz8xxx_write_reg(pdev, KSZ8463_GLOBAL_CTRL_8H, tmp);
+#endif
+
+	dsa_ksz8xxx_read_reg(pdev, KSZ8463_GLOBAL_CTRL_2L, &tmp);
+	tmp &= ~KSZ8463_GLOBAL_CTRL2_LEG_MAX_PKT_SIZ_CHK_ENA;
+	dsa_ksz8xxx_write_reg(pdev, KSZ8463_GLOBAL_CTRL_2L, tmp);
+
+	return 0;
+}
+#endif
+
 #if CONFIG_DSA_KSZ8863
 static int dsa_ksz8xxx_switch_setup(const struct ksz8xxx_data *pdev)
 {
@@ -697,6 +790,10 @@ int dsa_hw_init(struct ksz8xxx_data *pdev)
 	/* Setup KSZ8794 */
 	dsa_ksz8xxx_switch_setup(pdev);
 
+#if defined(CONFIG_DSA_KSZ_PORT_ISOLATING)
+	dsa_ksz8xxx_port_isolate(pdev);
+#endif
+
 #if DT_INST_NODE_HAS_PROP(0, mii_lowspeed_drivestrength)
 	dsa_ksz8794_set_lowspeed_drivestrength(pdev);
 #endif
@@ -841,8 +938,8 @@ struct net_pkt *dsa_ksz8xxx_xmit_pkt(struct net_if *iface, struct net_pkt *pkt)
 	struct net_buf *buf;
 	size_t len, pad = 0;
 
-	lladst.len = sizeof(hdr->dst.addr);
-	lladst.addr = &hdr->dst.addr[0];
+	(void)net_linkaddr_create(&lladst, hdr->dst.addr, sizeof(hdr->dst.addr),
+				  NET_LINK_ETHERNET);
 
 	len = net_pkt_get_len(pkt);
 	/*
@@ -885,7 +982,7 @@ struct net_pkt *dsa_ksz8xxx_xmit_pkt(struct net_if *iface, struct net_pkt *pkt)
 		port_idx = (1 << (ctx->dsa_port_idx));
 	}
 
-	NET_DBG("TT - port: 0x%x[%p] LEN: %d 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x",
+	LOG_DBG("TT - port: 0x%x[%p] LEN: %d 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x",
 		port_idx, iface, len, lladst.addr[0], lladst.addr[1],
 		lladst.addr[2], lladst.addr[3], lladst.addr[4], lladst.addr[5]);
 
@@ -922,7 +1019,7 @@ static struct net_if *dsa_ksz8xxx_get_iface(struct net_if *iface,
 	uint8_t pnum;
 
 	if (!(net_eth_get_hw_capabilities(iface) &
-	      (ETHERNET_DSA_SLAVE_PORT | ETHERNET_DSA_MASTER_PORT))) {
+	      (ETHERNET_DSA_USER_PORT | ETHERNET_DSA_CONDUIT_PORT))) {
 		return iface;
 	}
 
@@ -948,7 +1045,7 @@ static struct net_if *dsa_ksz8xxx_get_iface(struct net_if *iface,
 	iface_sw = net_if_get_by_index(pnum + 2);
 
 	ctx = net_if_l2_data(iface);
-	NET_DBG("TT - plen: %d pnum: %d pos: 0x%p dsa_port_idx: %d",
+	LOG_DBG("TT - plen: %d pnum: %d pos: 0x%p dsa_port_idx: %d",
 		plen - DSA_KSZ8794_EGRESS_TAG_LEN, pnum,
 		net_pkt_cursor_get_pos(pkt), ctx->dsa_port_idx);
 
@@ -1017,7 +1114,7 @@ static enum ethernet_hw_caps dsa_port_get_capabilities(const struct device *dev)
 {
 	ARG_UNUSED(dev);
 
-	return ETHERNET_DSA_SLAVE_PORT | ETHERNET_LINK_10BASE_T |
+	return ETHERNET_DSA_USER_PORT | ETHERNET_LINK_10BASE_T |
 		ETHERNET_LINK_100BASE_T;
 }
 
@@ -1112,5 +1209,4 @@ static struct dsa_api dsa_api_f = {
 	};								\
 	DT_INST_FOREACH_CHILD_VARGS(n, NET_SLAVE_DEVICE_INIT_INSTANCE, n);
 
-
 DT_INST_FOREACH_STATUS_OKAY(DSA_DEVICE);
diff --git a/drivers/ethernet/dwc_xgmac/eth_dwc_xgmac.c b/drivers/ethernet/dwc_xgmac/eth_dwc_xgmac.c
index 976e676a9a1..bc370eda205 100644
--- a/drivers/ethernet/dwc_xgmac/eth_dwc_xgmac.c
+++ b/drivers/ethernet/dwc_xgmac/eth_dwc_xgmac.c
@@ -1564,7 +1564,6 @@ static int eth_dwc_xgmac_set_config(const struct device *dev, enum ethernet_conf
 	const struct eth_dwc_xgmac_config *dev_conf = (struct eth_dwc_xgmac_config *)dev->config;
 	struct eth_dwc_xgmac_dev_data *dev_data = (struct eth_dwc_xgmac_dev_data *)dev->data;
 	const struct device *phy = dev_conf->phy_dev;
-	const struct ethphy_driver_api *phy_api = phy->api;
 	enum phy_link_speed adv_speeds;
 
 	int retval = 0;
@@ -1577,7 +1576,7 @@ static int eth_dwc_xgmac_set_config(const struct device *dev, enum ethernet_conf
 			adv_speeds =
 				get_phy_adv_speeds(dev_data->auto_neg, dev_data->enable_full_duplex,
 						   dev_data->link_speed);
-			retval = phy_api->cfg_link(phy, adv_speeds);
+			retval = phy_configure_link(phy, adv_speeds);
 		} else {
 			retval = -EALREADY;
 		}
@@ -1599,7 +1598,7 @@ static int eth_dwc_xgmac_set_config(const struct device *dev, enum ethernet_conf
 		}
 		adv_speeds = get_phy_adv_speeds(dev_data->auto_neg, dev_data->enable_full_duplex,
 						dev_data->link_speed);
-		retval = phy_api->cfg_link(phy, adv_speeds);
+		retval = phy_configure_link(phy, adv_speeds);
 		break;
 	case ETHERNET_CONFIG_TYPE_DUPLEX:
 		if (config->full_duplex == dev_data->enable_full_duplex) {
@@ -1610,7 +1609,7 @@ static int eth_dwc_xgmac_set_config(const struct device *dev, enum ethernet_conf
 
 		adv_speeds = get_phy_adv_speeds(dev_data->auto_neg, dev_data->enable_full_duplex,
 						dev_data->link_speed);
-		retval = phy_api->cfg_link(phy, adv_speeds);
+		retval = phy_configure_link(phy, adv_speeds);
 		break;
 	case ETHERNET_CONFIG_TYPE_MAC_ADDRESS:
 		memcpy(dev_data->mac_addr, config->mac_address.addr, ETH_MAC_ADDRESS_SIZE);
diff --git a/drivers/ethernet/eth_adin2111.c b/drivers/ethernet/eth_adin2111.c
index 536209a84ef..0f125fabc2d 100644
--- a/drivers/ethernet/eth_adin2111.c
+++ b/drivers/ethernet/eth_adin2111.c
@@ -317,7 +317,7 @@ int eth_adin2111_oa_data_read(const struct device *dev, const uint16_t port_idx)
 							   K_MSEC(CONFIG_ETH_ADIN2111_TIMEOUT));
 			if (!pkt) {
 				LOG_ERR("OA RX: cannot allcate packet space, skipping.");
-				return -EIO;
+				return -ENOMEM;
 			}
 			/* Skipping CRC32 */
 			ret = net_pkt_write(pkt, ctx->buf, ctx->scur - sizeof(uint32_t));
@@ -351,7 +351,7 @@ static int eth_adin2111_send_oa_frame(const struct device *dev, struct net_pkt *
 	uint16_t clen, len = net_pkt_get_len(pkt);
 	uint32_t hdr;
 	uint8_t chunks, i;
-	int ret, txc, cur;
+	int ret, txc, cur, ebo;
 
 	chunks = len / ctx->oa_cps;
 
@@ -359,6 +359,17 @@ static int eth_adin2111_send_oa_frame(const struct device *dev, struct net_pkt *
 		chunks++;
 	}
 
+	if (chunks > 1) {
+		/* we have to calculate EBO so we do not exceed maximum Ethernet frame length */
+		ebo = (len % ctx->oa_cps) - 1;
+		if (ebo < 0) {
+			ebo += ctx->oa_cps;
+		}
+	} else {
+		/* we have to pad to the minimum Ethernet frame length */
+		ebo = ctx->oa_cps - 1;
+	}
+
 	ret = eth_adin2111_reg_read(dev, ADIN2111_BUFSTS, &txc);
 	if (ret < 0) {
 		LOG_ERR("Cannot read txc");
@@ -380,7 +391,7 @@ static int eth_adin2111_send_oa_frame(const struct device *dev, struct net_pkt *
 		}
 		if (i == chunks) {
 			hdr |= ADIN2111_OA_DATA_HDR_EV;
-			hdr |= (ctx->oa_cps - 1) << ADIN2111_OA_DATA_HDR_EBO;
+			hdr |= ebo << ADIN2111_OA_DATA_HDR_EBO;
 		}
 
 		hdr |= eth_adin2111_oa_get_parity(hdr);
@@ -693,58 +704,47 @@ static void adin2111_offload_thread(void *p1, void *p2, void *p3)
 			adin2111_port_on_phyint(ctx->port[1]);
 		}
 
-		if (ctx->oa) {
-			if (status1 & ADIN2111_STATUS1_P1_RX_RDY) {
-				ret = eth_adin2111_oa_data_read(dev, 0);
-				if (ret < 0) {
-					goto continue_unlock;
-				}
-			}
-			if (is_adin2111 && (status1 & ADIN2111_STATUS1_P2_RX_RDY)) {
-				ret = eth_adin2111_oa_data_read(dev, 1);
-				if (ret < 0) {
-					goto continue_unlock;
-				}
-			}
-		} else {
+		if (!ctx->oa) {
 #if CONFIG_ETH_ADIN2111_SPI_CFG0
 			if (status0 & ADIN2111_STATUS1_SPI_ERR) {
 				LOG_WRN("Detected TX SPI CRC error");
 			}
-#endif /* CONFIG_ETH_ADIN2111_SPI_CFG0 */
+#endif
+		}
 
+		/* handle rx interrupt(s) */
+		do {
 			/* handle port 1 rx */
 			if (status1 & ADIN2111_STATUS1_P1_RX_RDY) {
-				do {
+				if (ctx->oa) {
+					ret = eth_adin2111_oa_data_read(dev, 0);
+				} else {
 					ret = adin2111_read_fifo(dev, 0U);
-					if (ret < 0) {
-						break;
-					}
-
-					ret = eth_adin2111_reg_read(dev, ADIN2111_STATUS1,
-								    &status1);
-					if (ret < 0) {
-						goto continue_unlock;
-					}
-				} while (!!(status1 & ADIN2111_STATUS1_P1_RX_RDY));
+				}
+
+				if (ret < 0) {
+					break;
+				}
 			}
 
 			/* handle port 2 rx */
 			if (is_adin2111 && (status1 & ADIN2111_STATUS1_P2_RX_RDY)) {
-				do {
+				if (ctx->oa) {
+					ret = eth_adin2111_oa_data_read(dev, 1);
+				} else {
 					ret = adin2111_read_fifo(dev, 1U);
-					if (ret < 0) {
-						break;
-					}
-
-					ret = eth_adin2111_reg_read(dev, ADIN2111_STATUS1,
-								    &status1);
-					if (ret < 0) {
-						goto continue_unlock;
-					}
-				} while (!!(status1 & ADIN2111_STATUS1_P2_RX_RDY));
+				}
+
+				if (ret < 0) {
+					break;
+				}
 			}
-		}
+
+			ret = eth_adin2111_reg_read(dev, ADIN2111_STATUS1, &status1);
+			if (ret < 0) {
+				break;
+			}
+		} while (status1 & (ADIN2111_STATUS1_P1_RX_RDY | ADIN2111_STATUS1_P2_RX_RDY));
 
 continue_unlock:
 		/* clear interrupts */
diff --git a/drivers/ethernet/eth_dwmac_stm32h7x.c b/drivers/ethernet/eth_dwmac_stm32h7x.c
index 846008c842d..bf96341207b 100644
--- a/drivers/ethernet/eth_dwmac_stm32h7x.c
+++ b/drivers/ethernet/eth_dwmac_stm32h7x.c
@@ -33,8 +33,8 @@ static const struct pinctrl_dev_config *eth0_pcfg =
 	PINCTRL_DT_INST_DEV_CONFIG_GET(0);
 
 static const struct stm32_pclken pclken = {
-	.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bus),
-	.enr = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bits),
+	.bus = DT_CLOCKS_CELL_BY_NAME(DT_INST_PARENT(0), stm_eth, bus),
+	.enr = DT_CLOCKS_CELL_BY_NAME(DT_INST_PARENT(0), stm_eth, bits),
 };
 static const struct stm32_pclken pclken_tx = {
 	.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_tx, bus),
@@ -81,7 +81,7 @@ int dwmac_bus_init(struct dwmac_priv *p)
 	reg_val = sys_read32(reg_addr);
 	sys_write32(reg_val | 0x03800000, reg_addr);
 
-	p->base_addr = DT_INST_REG_ADDR(0);
+	p->base_addr = DT_REG_ADDR(DT_INST_PARENT(0));
 	return 0;
 }
 
diff --git a/drivers/ethernet/eth_e1000.c b/drivers/ethernet/eth_e1000.c
index 178ceb5380d..322810698f6 100644
--- a/drivers/ethernet/eth_e1000.c
+++ b/drivers/ethernet/eth_e1000.c
@@ -270,10 +270,22 @@ static void e1000_iface_init(struct net_if *iface)
 	LOG_DBG("done");
 }
 
+#if defined(CONFIG_NET_STATISTICS_ETHERNET)
+static struct net_stats_eth *get_stats(const struct device *dev)
+{
+	struct e1000_dev *ctx = dev->data;
+
+	return &ctx->stats;
+}
+#endif
+
 static const struct ethernet_api e1000_api = {
 	.iface_api.init		= e1000_iface_init,
 #if defined(CONFIG_ETH_E1000_PTP_CLOCK)
 	.get_ptp_clock		= e1000_get_ptp_clock,
+#endif
+#if defined(CONFIG_NET_STATISTICS_ETHERNET)
+	.get_stats = get_stats,
 #endif
 	.get_capabilities	= e1000_caps,
 	.send			= e1000_send,
diff --git a/drivers/ethernet/eth_e1000_priv.h b/drivers/ethernet/eth_e1000_priv.h
index 64b7497b917..f8ecca6a0d7 100644
--- a/drivers/ethernet/eth_e1000_priv.h
+++ b/drivers/ethernet/eth_e1000_priv.h
@@ -94,6 +94,9 @@ struct e1000_dev {
 	const struct device *ptp_clock;
 	double clk_ratio;
 #endif
+#if defined(CONFIG_NET_STATISTICS_ETHERNET)
+	struct net_stats_eth stats;
+#endif
 };
 
 struct e1000_config {
diff --git a/drivers/ethernet/eth_esp32.c b/drivers/ethernet/eth_esp32.c
index 59977d357e1..c3fe85063d1 100644
--- a/drivers/ethernet/eth_esp32.c
+++ b/drivers/ethernet/eth_esp32.c
@@ -375,14 +375,14 @@ static void eth_esp32_iface_init(struct net_if *iface)
 	ethernet_init(iface);
 
 	if (device_is_ready(eth_esp32_phy_dev)) {
+		/* Do not start the interface until PHY link is up */
+		net_if_carrier_off(iface);
+
 		phy_link_callback_set(eth_esp32_phy_dev, phy_link_state_changed,
 				      (void *)dev);
 	} else {
 		LOG_ERR("PHY device not ready");
 	}
-
-	/* Do not start the interface until PHY link is up */
-	net_if_carrier_off(iface);
 }
 
 static const struct ethernet_api eth_esp32_api = {
diff --git a/drivers/ethernet/eth_lan865x.c b/drivers/ethernet/eth_lan865x.c
index 0ced9732928..3a3a0421e5d 100644
--- a/drivers/ethernet/eth_lan865x.c
+++ b/drivers/ethernet/eth_lan865x.c
@@ -18,9 +18,42 @@ LOG_MODULE_REGISTER(eth_lan865x, CONFIG_ETHERNET_LOG_LEVEL);
 #include <zephyr/net/net_if.h>
 #include <zephyr/net/ethernet.h>
 #include <zephyr/net/phy.h>
+#include <zephyr/drivers/ethernet/eth_lan865x.h>
 
 #include "eth_lan865x_priv.h"
 
+int eth_lan865x_mdio_c22_read(const struct device *dev, uint8_t prtad, uint8_t regad,
+			      uint16_t *data)
+{
+	struct lan865x_data *ctx = dev->data;
+
+	return oa_tc6_mdio_read(ctx->tc6, prtad, regad, data);
+}
+
+int eth_lan865x_mdio_c22_write(const struct device *dev, uint8_t prtad, uint8_t regad,
+			       uint16_t data)
+{
+	struct lan865x_data *ctx = dev->data;
+
+	return oa_tc6_mdio_write(ctx->tc6, prtad, regad, data);
+}
+
+int eth_lan865x_mdio_c45_read(const struct device *dev, uint8_t prtad, uint8_t devad,
+			      uint16_t regad, uint16_t *data)
+{
+	struct lan865x_data *ctx = dev->data;
+
+	return oa_tc6_mdio_read_c45(ctx->tc6, prtad, devad, regad, data);
+}
+
+int eth_lan865x_mdio_c45_write(const struct device *dev, uint8_t prtad, uint8_t devad,
+			       uint16_t regad, uint16_t data)
+{
+	struct lan865x_data *ctx = dev->data;
+
+	return oa_tc6_mdio_write_c45(ctx->tc6, prtad, devad, regad, data);
+}
+
 static int lan865x_mac_rxtx_control(const struct device *dev, bool en)
 {
 	struct lan865x_data *ctx = dev->data;
@@ -33,13 +66,38 @@ static int lan865x_mac_rxtx_control(const struct device *dev, bool en)
 	return oa_tc6_reg_write(ctx->tc6, LAN865x_MAC_NCR, ctl);
 }
 
+static int lan865x_enable_sync(const struct device *dev)
+{
+	struct lan865x_data *ctx = dev->data;
+	uint32_t val;
+	int ret;
+
+	ret = oa_tc6_reg_read(ctx->tc6, OA_CONFIG0, &val);
+	if (ret) {
+		return ret;
+	}
+	val |= OA_CONFIG0_SYNC | OA_CONFIG0_RFA_ZARFE;
+	ret = oa_tc6_reg_write(ctx->tc6, OA_CONFIG0, val);
+	if (ret) {
+		return ret;
+	}
+
+	return lan865x_mac_rxtx_control(dev, LAN865x_MAC_TXRX_ON);
+}
+
 static void lan865x_iface_init(struct net_if *iface)
 {
 	const struct device *dev = net_if_get_device(iface);
 	struct lan865x_data *ctx = dev->data;
+	int ret;
+
+	ret = lan865x_enable_sync(dev);
+	if (ret) {
+		LOG_ERR("LAN865x sync enable failed: %d\n", ret);
+		return;
+	}
 
-	net_if_set_link_addr(iface, ctx->mac_address, sizeof(ctx->mac_address),
-			     NET_LINK_ETHERNET);
+	net_if_set_link_addr(iface, ctx->mac_address, sizeof(ctx->mac_address), NET_LINK_ETHERNET);
 
 	if (ctx->iface == NULL) {
 		ctx->iface = iface;
@@ -64,44 +122,35 @@ static int lan865x_set_config(const struct device *dev, enum ethernet_config_typ
 {
 	const struct lan865x_config *cfg = dev->config;
 	struct lan865x_data *ctx = dev->data;
-	int ret = -ENOTSUP;
+	struct phy_plca_cfg plca_cfg;
 
 	if (type == ETHERNET_CONFIG_TYPE_PROMISC_MODE) {
-		return oa_tc6_reg_write(ctx->tc6, LAN865x_MAC_NCFGR,
-				       LAN865x_MAC_NCFGR_CAF);
+		return oa_tc6_reg_write(ctx->tc6, LAN865x_MAC_NCFGR, LAN865x_MAC_NCFGR_CAF);
 	}
 
 	if (type == ETHERNET_CONFIG_TYPE_MAC_ADDRESS) {
-		memcpy(ctx->mac_address, config->mac_address.addr,
-		       sizeof(ctx->mac_address));
+		memcpy(ctx->mac_address, config->mac_address.addr, sizeof(ctx->mac_address));
 
 		lan865x_write_macaddress(dev);
 
-		return net_if_set_link_addr(ctx->iface, ctx->mac_address,
-				     sizeof(ctx->mac_address),
-				     NET_LINK_ETHERNET);
+		return net_if_set_link_addr(ctx->iface, ctx->mac_address, sizeof(ctx->mac_address),
+					    NET_LINK_ETHERNET);
 	}
 
 	if (type == ETHERNET_CONFIG_TYPE_T1S_PARAM) {
-		ret = lan865x_mac_rxtx_control(dev, LAN865x_MAC_TXRX_OFF);
-		if (ret) {
-			return ret;
-		}
-
 		if (config->t1s_param.type == ETHERNET_T1S_PARAM_TYPE_PLCA_CONFIG) {
-			cfg->plca->enable = config->t1s_param.plca.enable;
-			cfg->plca->node_id = config->t1s_param.plca.node_id;
-			cfg->plca->node_count = config->t1s_param.plca.node_count;
-			cfg->plca->burst_count = config->t1s_param.plca.burst_count;
-			cfg->plca->burst_timer = config->t1s_param.plca.burst_timer;
-			cfg->plca->to_timer = config->t1s_param.plca.to_timer;
+			plca_cfg.enable = config->t1s_param.plca.enable;
+			plca_cfg.node_id = config->t1s_param.plca.node_id;
+			plca_cfg.node_count = config->t1s_param.plca.node_count;
+			plca_cfg.burst_count = config->t1s_param.plca.burst_count;
+			plca_cfg.burst_timer = config->t1s_param.plca.burst_timer;
+			plca_cfg.to_timer = config->t1s_param.plca.to_timer;
+
+			return phy_set_plca_cfg(cfg->phy, &plca_cfg);
 		}
-
-		/* Reset is required to re-program PLCA new configuration */
-		lan865x_gpio_reset(dev);
 	}
 
-	return ret;
+	return -ENOTSUP;
 }
 
 static int lan865x_wait_for_reset(const struct device *dev)
@@ -164,156 +213,6 @@ static int lan865x_check_spi(const struct device *dev)
 	return ret;
 }
 
-/* Implementation of pseudo code from AN1760 */
-static uint8_t lan865x_read_indirect_reg(const struct device *dev, uint8_t addr,
-					 uint8_t mask)
-{
-	struct lan865x_data *ctx = dev->data;
-	uint32_t val;
-
-	oa_tc6_reg_write(ctx->tc6, 0x000400D8, addr);
-	oa_tc6_reg_write(ctx->tc6, 0x000400DA, 0x02);
-
-	oa_tc6_reg_read(ctx->tc6, 0x000400D9, &val);
-
-	return (uint8_t) val & mask;
-}
-
-/*
- * Values in the below table for LAN865x rev. B0 and B1 (with place
- * holders for cfgparamX.
- */
-static oa_mem_map_t lan865x_conf[] = {
-	{ .mms = 0x1, .address = 0x00, .value = 0x0000 },
-	{ .mms = 0x4, .address = 0xD0, .value = 0x3F31 },
-	{ .mms = 0x4, .address = 0xE0, .value = 0xC000 },
-	{ .mms = 0x4, .address = 0x84, .value = 0x0000 }, /* cfgparam1 */
-	{ .mms = 0x4, .address = 0x8A, .value = 0x0000 }, /* cfgparam2 */
-	{ .mms = 0x4, .address = 0xE9, .value = 0x9E50 },
-	{ .mms = 0x4, .address = 0xF5, .value = 0x1CF8 },
-	{ .mms = 0x4, .address = 0xF4, .value = 0xC020 },
-	{ .mms = 0x4, .address = 0xF8, .value = 0xB900 },
-	{ .mms = 0x4, .address = 0xF9, .value = 0x4E53 },
-	{ .mms = 0x4, .address = 0x91, .value = 0x9660 },
-	{ .mms = 0x4, .address = 0x77, .value = 0x0028 },
-	{ .mms = 0x4, .address = 0x43, .value = 0x00FF },
-	{ .mms = 0x4, .address = 0x44, .value = 0xFFFF },
-	{ .mms = 0x4, .address = 0x45, .value = 0x0000 },
-	{ .mms = 0x4, .address = 0x53, .value = 0x00FF },
-	{ .mms = 0x4, .address = 0x54, .value = 0xFFFF },
-	{ .mms = 0x4, .address = 0x55, .value = 0x0000 },
-	{ .mms = 0x4, .address = 0x40, .value = 0x0002 },
-	{ .mms = 0x4, .address = 0x50, .value = 0x0002 },
-	{ .mms = 0x4, .address = 0xAD, .value = 0x0000 }, /* cfgparam3 */
-	{ .mms = 0x4, .address = 0xAE, .value = 0x0000 }, /* cfgparam4 */
-	{ .mms = 0x4, .address = 0xAF, .value = 0x0000 }, /* cfgparam5 */
-	{ .mms = 0x4, .address = 0xB0, .value = 0x0103 },
-	{ .mms = 0x4, .address = 0xB1, .value = 0x0910 },
-	{ .mms = 0x4, .address = 0xB2, .value = 0x1D26 },
-	{ .mms = 0x4, .address = 0xB3, .value = 0x002A },
-	{ .mms = 0x4, .address = 0xB4, .value = 0x0103 },
-	{ .mms = 0x4, .address = 0xB5, .value = 0x070D },
-	{ .mms = 0x4, .address = 0xB6, .value = 0x1720 },
-	{ .mms = 0x4, .address = 0xB7, .value = 0x0027 },
-	{ .mms = 0x4, .address = 0xB8, .value = 0x0509 },
-	{ .mms = 0x4, .address = 0xB9, .value = 0x0E13 },
-	{ .mms = 0x4, .address = 0xBA, .value = 0x1C25 },
-	{ .mms = 0x4, .address = 0xBB, .value = 0x002B },
-	{ .mms = 0x4, .address = 0x0C, .value = 0x0100 },
-	{ .mms = 0x4, .address = 0x81, .value = 0x00E0 },
-};
-
-/* Based on AN1760 DS60001760G pseudo code */
-static int lan865x_init_chip(const struct device *dev, uint8_t silicon_rev)
-{
-	uint16_t cfgparam1, cfgparam2, cfgparam3, cfgparam4, cfgparam5;
-	uint8_t i, size = ARRAY_SIZE(lan865x_conf);
-	struct lan865x_data *ctx = dev->data;
-	int8_t offset1 = 0, offset2 = 0;
-	uint8_t value1, value2;
-
-	/* Enable protected control RW */
-	oa_tc6_set_protected_ctrl(ctx->tc6, true);
-
-	value1 = lan865x_read_indirect_reg(dev, 0x04, 0x1F);
-	if ((value1 & 0x10) != 0) { /* Convert uint8_t to int8_t */
-		offset1 = (int8_t)((uint8_t)value1 - 0x20);
-	} else {
-		offset1 = (int8_t)value1;
-	}
-
-	value2 = lan865x_read_indirect_reg(dev, 0x08, 0x1F);
-	if ((value2 & 0x10) != 0) { /* Convert uint8_t to int8_t */
-		offset2 = (int8_t)((uint8_t)value2 - 0x20);
-	} else {
-		offset2 = (int8_t)value2;
-	}
-
-	cfgparam1 = (uint16_t) (((9 + offset1) & 0x3F) << 10) |
-		(uint16_t) (((14 + offset1) & 0x3F) << 4) | 0x03;
-	cfgparam2 = (uint16_t) (((40 + offset2) & 0x3F) << 10);
-	cfgparam3 = (uint16_t) (((5 + offset1) & 0x3F) << 8) |
-		(uint16_t) ((9 + offset1) & 0x3F);
-	cfgparam4 = (uint16_t) (((9 + offset1) & 0x3F) << 8) |
-		(uint16_t) ((14 + offset1) & 0x3F);
-	cfgparam5 = (uint16_t) (((17 + offset1) & 0x3F) << 8) |
-		(uint16_t) ((22 + offset1) & 0x3F);
-
-	lan865x_update_dev_cfg_array(lan865x_conf, size,
-				     MMS_REG(0x4, 0x84), cfgparam1);
-	lan865x_update_dev_cfg_array(lan865x_conf, size,
-				     MMS_REG(0x4, 0x8A), cfgparam2);
-	lan865x_update_dev_cfg_array(lan865x_conf, size,
-				     MMS_REG(0x4, 0xAD), cfgparam3);
-	lan865x_update_dev_cfg_array(lan865x_conf, size,
-				     MMS_REG(0x4, 0xAE), cfgparam4);
-	lan865x_update_dev_cfg_array(lan865x_conf, size,
-				     MMS_REG(0x4, 0xAF), cfgparam5);
-
-	if (silicon_rev == 1) {
-		/* For silicon rev 1 (B0): (bit [3..0] from 0x0A0084 */
-		lan865x_update_dev_cfg_array(lan865x_conf, size,
-					     MMS_REG(0x4, 0xD0), 0x5F21);
-	}
-
-	/* Write LAN865x config with correct order */
-	for (i = 0; i < size; i++) {
-		oa_tc6_reg_write(ctx->tc6, MMS_REG(lan865x_conf[i].mms,
-						   lan865x_conf[i].address),
-				 (uint32_t)lan865x_conf[i].value);
-	}
-
-	return 0;
-}
-/* Implementation of pseudo code from AN1760 - END */
-
-static int lan865x_config_plca(const struct device *dev, uint8_t node_id,
-			       uint8_t node_cnt, uint8_t burst_cnt, uint8_t burst_timer)
-{
-	struct lan865x_data *ctx = dev->data;
-	uint32_t val;
-
-	/* Collision Detection */
-	oa_tc6_reg_write(ctx->tc6, 0x00040087, 0x0083u); /* COL_DET_CTRL0 */
-
-	/* T1S Phy Node ID and Max Node Count */
-	if (node_id == 0) {
-		val = (uint32_t)node_cnt << 8;
-	} else {
-		val = (uint32_t)node_id;
-	}
-	oa_tc6_reg_write(ctx->tc6, 0x0004CA02, val); /* PLCA_CONTROL_1_REGISTER */
-
-	/* PLCA Burst Count and Burst Timer */
-	val = ((uint32_t)burst_cnt << 8) | burst_timer;
-	oa_tc6_reg_write(ctx->tc6, 0x0004CA05, val); /* PLCA_BURST_MODE_REGISTER */
-
-	/* Enable PLCA */
-	oa_tc6_reg_write(ctx->tc6, 0x0004CA01, BIT(15)); /* PLCA_CONTROL_0_REGISTER */
-
-	return 0;
-}
-
 static void lan865x_write_macaddress(const struct device *dev)
 {
 	struct lan865x_data *ctx = dev->data;
@@ -354,44 +253,34 @@ static int lan865x_set_specific_multicast_addr(const struct device *dev)
 		return ret;
 	}
 
-	return oa_tc6_reg_write(ctx->tc6, LAN865x_MAC_NCFGR,
-				LAN865x_MAC_NCFGR_MTIHEN);
+	return oa_tc6_reg_write(ctx->tc6, LAN865x_MAC_NCFGR, LAN865x_MAC_NCFGR_MTIHEN);
 }
 
-static int lan865x_default_config(const struct device *dev, uint8_t silicon_rev)
+static int lan865x_default_config(const struct device *dev)
 {
-	const struct lan865x_config *cfg = dev->config;
+	struct lan865x_data *ctx = dev->data;
 	int ret;
 
-	lan865x_write_macaddress(dev);
-	lan865x_set_specific_multicast_addr(dev);
+	/* Enable protected control RW */
+	oa_tc6_set_protected_ctrl(ctx->tc6, true);
 
-	ret = lan865x_init_chip(dev, silicon_rev);
-	if (ret < 0) {
+	ret = oa_tc6_reg_write(ctx->tc6, LAN865X_FIXUP_REG, LAN865X_FIXUP_VALUE);
+	if (ret) {
 		return ret;
 	}
 
-	if (cfg->plca->enable) {
-		ret = lan865x_config_plca(dev, cfg->plca->node_id,
-					  cfg->plca->node_count,
-					  cfg->plca->burst_count,
-					  cfg->plca->burst_timer);
-		if (ret < 0) {
-			return ret;
-		}
-	}
+	lan865x_write_macaddress(dev);
+	lan865x_set_specific_multicast_addr(dev);
+
 	return 0;
 }
 
-static void lan865x_int_callback(const struct device *dev,
-				  struct gpio_callback *cb,
-				  uint32_t pins)
+static void lan865x_int_callback(const struct device *dev, struct gpio_callback *cb, uint32_t pins)
 {
 	ARG_UNUSED(dev);
 	ARG_UNUSED(pins);
 
-	struct lan865x_data *ctx =
-		CONTAINER_OF(cb, struct lan865x_data, gpio_int_callback);
+	struct lan865x_data *ctx = CONTAINER_OF(cb, struct lan865x_data, gpio_int_callback);
 
 	k_sem_give(&ctx->int_sem);
 }
@@ -432,7 +321,7 @@ static void lan865x_int_thread(const struct device *dev)
 {
 	struct lan865x_data *ctx = dev->data;
 	struct oa_tc6 *tc6 = ctx->tc6;
-	uint32_t sts, val, ftr;
+	uint32_t sts, ftr;
 	int ret;
 
 	while (true) {
@@ -441,11 +330,8 @@ static void lan865x_int_thread(const struct device *dev)
 			oa_tc6_reg_read(tc6, OA_STATUS0, &sts);
 			if (sts & OA_STATUS0_RESETC) {
 				oa_tc6_reg_write(tc6, OA_STATUS0, sts);
-				lan865x_default_config(dev, ctx->silicon_rev);
-				oa_tc6_reg_read(tc6, OA_CONFIG0, &val);
-				val |= OA_CONFIG0_SYNC | OA_CONFIG0_RFA_ZARFE;
-				oa_tc6_reg_write(tc6, OA_CONFIG0, val);
-				lan865x_mac_rxtx_control(dev, LAN865x_MAC_TXRX_ON);
+
+				lan865x_default_config(dev);
 
 				ctx->reset = true;
 				/*
@@ -490,8 +376,7 @@ static int lan865x_init(const struct device *dev)
 	}
 
 	if (!gpio_is_ready_dt(&cfg->interrupt)) {
-		LOG_ERR("Interrupt GPIO device %s is not ready",
-			cfg->interrupt.port->name);
+		LOG_ERR("Interrupt GPIO device %s is not ready", cfg->interrupt.port->name);
 		return -ENODEV;
 	}
 
@@ -523,19 +408,15 @@ static int lan865x_init(const struct device *dev)
 	gpio_pin_interrupt_configure_dt(&cfg->interrupt, GPIO_INT_EDGE_TO_ACTIVE);
 
 	/* Start interruption-poll thread */
-	ctx->tid_int =
-		k_thread_create(&ctx->thread, ctx->thread_stack,
-				CONFIG_ETH_LAN865X_IRQ_THREAD_STACK_SIZE,
-				(k_thread_entry_t)lan865x_int_thread,
-				(void *)dev, NULL, NULL,
-				K_PRIO_COOP(CONFIG_ETH_LAN865X_IRQ_THREAD_PRIO),
-				0, K_NO_WAIT);
+	ctx->tid_int = k_thread_create(
+		&ctx->thread, ctx->thread_stack, CONFIG_ETH_LAN865X_IRQ_THREAD_STACK_SIZE,
+		(k_thread_entry_t)lan865x_int_thread, (void *)dev, NULL, NULL,
+		K_PRIO_COOP(CONFIG_ETH_LAN865X_IRQ_THREAD_PRIO), 0, K_NO_WAIT);
 	k_thread_name_set(ctx->tid_int, "lan865x_interrupt");
 
 	/* Perform HW reset - 'rst-gpios' required property set in DT */
 	if (!gpio_is_ready_dt(&cfg->reset)) {
-		LOG_ERR("Reset GPIO device %s is not ready",
-			cfg->reset.port->name);
+		LOG_ERR("Reset GPIO device %s is not ready", cfg->reset.port->name);
 		return -ENODEV;
 	}
 
@@ -580,36 +461,22 @@ static const struct ethernet_api lan865x_api_func = {
 };
 
 #define LAN865X_DEFINE(inst)                                                                       \
-	static struct lan865x_config_plca lan865x_config_plca_##inst = {                           \
-		.node_id = DT_INST_PROP(inst, plca_node_id),                                       \
-		.node_count = DT_INST_PROP(inst, plca_node_count),                                 \
-		.burst_count = DT_INST_PROP(inst, plca_burst_count),                               \
-		.burst_timer = DT_INST_PROP(inst, plca_burst_timer),                               \
-		.to_timer = DT_INST_PROP(inst, plca_to_timer),                                     \
-		.enable = DT_INST_PROP(inst, plca_enable),                                         \
-	};                                                                                         \
-												   \
 	static const struct lan865x_config lan865x_config_##inst = {                               \
 		.spi = SPI_DT_SPEC_INST_GET(inst, SPI_WORD_SET(8), 0),                             \
 		.interrupt = GPIO_DT_SPEC_INST_GET(inst, int_gpios),                               \
 		.reset = GPIO_DT_SPEC_INST_GET(inst, rst_gpios),                                   \
 		.timeout = CONFIG_ETH_LAN865X_TIMEOUT,                                             \
-		.plca = &lan865x_config_plca_##inst,                                               \
-	};                                                                                         \
-												   \
+		.phy = DEVICE_DT_GET(                                                              \
+			DT_CHILD(DT_INST_CHILD(inst, lan865x_mdio), ethernet_phy_##inst))};        \
+                                                                                                   \
 	struct oa_tc6 oa_tc6_##inst = {                                                            \
-		.cps = 64,                                                                         \
-		.protected = 0,                                                                    \
-		.spi = &lan865x_config_##inst.spi                                                  \
-	};                                                                                         \
+		.cps = 64, .protected = 0, .spi = &lan865x_config_##inst.spi};                     \
 	static struct lan865x_data lan865x_data_##inst = {                                         \
 		.mac_address = DT_INST_PROP(inst, local_mac_address),                              \
-		.tx_rx_sem =                                                                       \
-			Z_SEM_INITIALIZER((lan865x_data_##inst).tx_rx_sem, 1, 1),                  \
+		.tx_rx_sem = Z_SEM_INITIALIZER((lan865x_data_##inst).tx_rx_sem, 1, 1),             \
 		.int_sem = Z_SEM_INITIALIZER((lan865x_data_##inst).int_sem, 0, 1),                 \
-		.tc6 = &oa_tc6_##inst                                                              \
-	};                                                                                         \
-												   \
+		.tc6 = &oa_tc6_##inst};                                                            \
+                                                                                                   \
 	ETH_NET_DEVICE_DT_INST_DEFINE(inst, lan865x_init, NULL, &lan865x_data_##inst,              \
 				      &lan865x_config_##inst, CONFIG_ETH_INIT_PRIORITY,            \
 				      &lan865x_api_func, NET_ETH_MTU);
diff --git a/drivers/ethernet/eth_lan865x_priv.h b/drivers/ethernet/eth_lan865x_priv.h
index 1ba84bd9ff7..50110dee133 100644
--- a/drivers/ethernet/eth_lan865x_priv.h
+++ b/drivers/ethernet/eth_lan865x_priv.h
@@ -15,50 +15,42 @@
 #include <ethernet/eth_stats.h>
 #include "oa_tc6.h"
 
-#define LAN865X_SPI_MAX_FREQUENCY		25000000U
-#define LAN865X_HW_BOOT_DELAY_MS                7
-#define LAN8650_DEVID                           0x8650
-#define LAN8651_DEVID                           0x8651
-#define LAN865X_REV_MASK                        GENMASK(3, 0)
-#define LAN865X_RESET_TIMEOUT                   10
+#define LAN865X_SPI_MAX_FREQUENCY 25000000U
+#define LAN865X_HW_BOOT_DELAY_MS  7
+#define LAN8650_DEVID             0x8650
+#define LAN8651_DEVID             0x8651
+#define LAN865X_REV_MASK          GENMASK(3, 0)
+#define LAN865X_RESET_TIMEOUT     10
 
 /* Memory Map Sector (MMS) 1 (0x1) */
-#define LAN865x_MAC_NCR		        MMS_REG(0x1, 0x000)
-#define LAN865x_MAC_NCR_TXEN		BIT(3)
-#define LAN865x_MAC_NCR_RXEN		BIT(2)
-#define LAN865x_MAC_NCFGR		MMS_REG(0x1, 0x001)
-#define LAN865x_MAC_NCFGR_CAF		BIT(4)
-#define LAN865x_MAC_NCFGR_MTIHEN	BIT(6)
-#define LAN865x_MAC_HRB		MMS_REG(0x1, 0x020)
-#define LAN865x_MAC_HRT		MMS_REG(0x1, 0x021)
-#define LAN865x_MAC_SAB1		MMS_REG(0x1, 0x022)
-#define LAN865x_MAC_SAB2		MMS_REG(0x1, 0x024)
-#define LAN865x_MAC_SAT2		MMS_REG(0x1, 0x025)
+#define LAN865x_MAC_NCR          MMS_REG(0x1, 0x000)
+#define LAN865x_MAC_NCR_TXEN     BIT(3)
+#define LAN865x_MAC_NCR_RXEN     BIT(2)
+#define LAN865x_MAC_NCFGR        MMS_REG(0x1, 0x001)
+#define LAN865x_MAC_NCFGR_CAF    BIT(4)
+#define LAN865x_MAC_NCFGR_MTIHEN BIT(6)
+#define LAN865x_MAC_HRB          MMS_REG(0x1, 0x020)
+#define LAN865x_MAC_HRT          MMS_REG(0x1, 0x021)
+#define LAN865x_MAC_SAB1         MMS_REG(0x1, 0x022)
+#define LAN865x_MAC_SAB2         MMS_REG(0x1, 0x024)
+#define LAN865x_MAC_SAT2         MMS_REG(0x1, 0x025)
+/* LAN8650/1 configuration fixup from AN1760 */
+#define LAN865X_FIXUP_REG        MMS_REG(0x1, 0x077)
+#define LAN865X_FIXUP_VALUE      0x0028
 
-#define LAN865x_MAC_TXRX_ON             1
-#define LAN865x_MAC_TXRX_OFF            0
+#define LAN865x_MAC_TXRX_ON  1
+#define LAN865x_MAC_TXRX_OFF 0
 
 /* Memory Map Sector (MMS) 10 (0xA) */
 #define LAN865x_DEVID MMS_REG(0xA, 0x094)
 
-struct lan865x_config_plca {
-	bool enable : 1; /* 1 - PLCA enable, 0 - CSMA/CD enable */
-	uint8_t node_id  /* PLCA node id range: 0 to 254 */;
-	uint8_t node_count;  /* PLCA node count range: 1 to 255 */
-	uint8_t burst_count;  /* PLCA burst count range: 0x0 to 0xFF */
-	uint8_t burst_timer;  /* PLCA burst timer */
-	uint8_t to_timer;  /* PLCA TO value */
-};
-
 struct lan865x_config {
+	const struct device *phy;
 	struct spi_dt_spec spi;
 	struct gpio_dt_spec interrupt;
 	struct gpio_dt_spec reset;
 	int32_t timeout;
 
-	/* PLCA */
-	struct lan865x_config_plca *plca;
-
 	/* MAC */
 	bool tx_cut_through_mode; /* 1 - tx cut through, 0 - Store and forward */
 	bool rx_cut_through_mode; /* 1 - rx cut through, 0 - Store and forward */
@@ -81,14 +73,4 @@ struct lan865x_data {
 	k_tid_t tid_int;
 };
 
-static inline void lan865x_update_dev_cfg_array(oa_mem_map_t *cfg, uint8_t size,
-						uint32_t addr, uint16_t val)
-{
-	for (uint8_t i = 0; i < size; i++) {
-		if (cfg[i].address == addr) {
-			cfg[i].value = val;
-		}
-	}
-}
-
 #endif /* ETH_LAN865X_PRIV_H__ */
diff --git a/drivers/ethernet/eth_litex_liteeth.c b/drivers/ethernet/eth_litex_liteeth.c
index a8b1b38c739..1a2b6009832 100644
--- a/drivers/ethernet/eth_litex_liteeth.c
+++ b/drivers/ethernet/eth_litex_liteeth.c
@@ -27,12 +27,16 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
 
 #include "eth.h"
 
-#define MAX_TX_FAILURE 100
+#define MAX_TX_FAILURE K_MSEC(100)
+
+#define ETH_LITEX_SLOT_SIZE 0x0800
 
 struct eth_litex_dev_data {
 	struct net_if *iface;
 	uint8_t mac_addr[6];
 	uint8_t txslot;
+	struct k_mutex tx_mutex;
+	struct k_sem sem_tx_ready;
 };
 
 struct eth_litex_config {
@@ -49,8 +53,10 @@ struct eth_litex_config {
 	uint32_t tx_length_addr;
 	uint32_t tx_ev_pending_addr;
 	uint32_t tx_ev_enable_addr;
-	uint8_t *tx_buf[2];
-	uint8_t *rx_buf[2];
+	uint32_t tx_buf_addr;
+	uint32_t rx_buf_addr;
+	uint8_t tx_buf_n;
+	uint8_t rx_buf_n;
 };
 
 static int eth_initialize(const struct device *dev)
@@ -58,10 +64,10 @@ static int eth_initialize(const struct device *dev)
 	const struct eth_litex_config *config = dev->config;
 	struct eth_litex_dev_data *context = dev->data;
 
-	config->config_func(dev);
+	k_mutex_init(&context->tx_mutex);
+	k_sem_init(&context->sem_tx_ready, 1, 1);
 
-	/* TX event is disabled because it isn't used by this driver */
-	litex_write8(0, config->tx_ev_enable_addr);
+	config->config_func(dev);
 
 	if (config->random_mac_address) {
 		/* generate random MAC address */
@@ -73,42 +79,40 @@ static int eth_initialize(const struct device *dev)
 
 static int eth_tx(const struct device *dev, struct net_pkt *pkt)
 {
-	unsigned int key;
 	uint16_t len;
 	struct eth_litex_dev_data *context = dev->data;
 	const struct eth_litex_config *config = dev->config;
+	int ret;
 
-	key = irq_lock();
-	int attempts = 0;
+	k_mutex_lock(&context->tx_mutex, K_FOREVER);
 
 	/* get data from packet and send it */
 	len = net_pkt_get_len(pkt);
-	net_pkt_read(pkt, config->tx_buf[context->txslot], len);
+	net_pkt_read(pkt,
+		     UINT_TO_POINTER(config->tx_buf_addr + (context->txslot * ETH_LITEX_SLOT_SIZE)),
+		     len);
 
 	litex_write8(context->txslot, config->tx_slot_addr);
 	litex_write16(len, config->tx_length_addr);
 
 	/* wait for the device to be ready to transmit */
-	while (litex_read8(config->tx_ready_addr) == 0) {
-		if (attempts++ == MAX_TX_FAILURE) {
-			goto error;
-		}
-		k_sleep(K_MSEC(1));
-	}
-
+	ret = k_sem_take(&context->sem_tx_ready, MAX_TX_FAILURE);
+	if (ret < 0) {
+		goto error;
+	};
 	/* start transmitting */
 	litex_write8(1, config->tx_start_addr);
 
 	/* change slot */
-	context->txslot = (context->txslot + 1) % 2;
+	context->txslot = (context->txslot + 1) % config->tx_buf_n;
 
-	irq_unlock(key);
+	k_mutex_unlock(&context->tx_mutex);
 
 	return 0;
 error:
-	irq_unlock(key);
+	k_mutex_unlock(&context->tx_mutex);
 	LOG_ERR("TX fifo failed");
-	return -1;
+	return -EIO;
 }
 
 static void eth_rx(const struct device *port)
@@ -118,7 +122,6 @@ static void eth_rx(const struct device *port)
 	const struct eth_litex_config *config = port->config;
 
 	int r;
-	unsigned int key;
 	uint16_t len = 0;
 	uint8_t rxslot = 0;
 
@@ -126,8 +129,6 @@ static void eth_rx(const struct device *port)
 		return;
 	}
 
-	key = irq_lock();
-
 	/* get frame's length */
 	len = litex_read16(config->rx_length_addr);
 
@@ -139,14 +140,16 @@ static void eth_rx(const struct device *port)
 					   K_NO_WAIT);
 	if (pkt == NULL) {
 		LOG_ERR("Failed to obtain RX buffer");
-		goto out;
+		return;
 	}
 
 	/* copy data to buffer */
-	if (net_pkt_write(pkt, (void *)config->rx_buf[rxslot], len) != 0) {
+	if (net_pkt_write(pkt,
+			  UINT_TO_POINTER(config->rx_buf_addr + (rxslot * ETH_LITEX_SLOT_SIZE)),
+			  len) != 0) {
 		LOG_ERR("Failed to append RX buffer to context buffer");
 		net_pkt_unref(pkt);
-		goto out;
+		return;
 	}
 
 	/* receive data */
@@ -155,19 +158,17 @@ static void eth_rx(const struct device *port)
 		LOG_ERR("Failed to enqueue frame into RX queue: %d", r);
 		net_pkt_unref(pkt);
 	}
-
-out:
-	irq_unlock(key);
 }
 
 static void eth_irq_handler(const struct device *port)
 {
+	struct eth_litex_dev_data *context = port->data;
 	const struct eth_litex_config *config = port->config;
 	/* check sram reader events (tx) */
 	if (litex_read8(config->tx_ev_pending_addr) & BIT(0)) {
-		/* TX event is not enabled nor used by this driver; ack just
-		 * in case if some rogue TX event appeared
-		 */
+		k_sem_give(&context->sem_tx_ready);
+
+		/* ack reader irq */
 		litex_write8(BIT(0), config->tx_ev_pending_addr);
 	}
 
@@ -201,8 +202,14 @@ static int eth_set_config(const struct device *dev, enum ethernet_config_type ty
 
 static int eth_start(const struct device *dev)
 {
+	struct eth_litex_dev_data *context = dev->data;
 	const struct eth_litex_config *config = dev->config;
 
+	if (litex_read8(config->tx_ready_addr)) {
+		k_sem_give(&context->sem_tx_ready);
+	}
+
+	litex_write8(1, config->tx_ev_enable_addr);
 	litex_write8(1, config->rx_ev_enable_addr);
 
 	litex_write8(BIT(0), config->tx_ev_pending_addr);
@@ -215,6 +222,7 @@ static int eth_stop(const struct device *dev)
 {
 	const struct eth_litex_config *config = dev->config;
 
+	litex_write8(0, config->tx_ev_enable_addr);
 	litex_write8(0, config->rx_ev_enable_addr);
 
 	return 0;
@@ -299,16 +307,18 @@ static const struct ethernet_api eth_api = {
 	.send = eth_tx
 };
 
-#define ETH_LITEX_SLOT_SIZE 0x0800
-
-#define ETH_LITEX_SLOT_RX0_ADDR(n)                                                                 \
+#define ETH_LITEX_SLOT_RX_ADDR(n)                                                                  \
 	DT_INST_REG_ADDR_BY_NAME_OR(n, rx_buffers, (DT_INST_REG_ADDR_BY_NAME(n, buffers)))
-#define ETH_LITEX_SLOT_RX1_ADDR(n) (ETH_LITEX_SLOT_RX0_ADDR(n) + ETH_LITEX_SLOT_SIZE)
-#define ETH_LITEX_SLOT_TX0_ADDR(n)                                                                 \
+#define ETH_LITEX_SLOT_TX_ADDR(n)                                                                  \
 	DT_INST_REG_ADDR_BY_NAME_OR(n, tx_buffers,                                                 \
 				    (DT_INST_REG_ADDR_BY_NAME(n, buffers) +                        \
 				     (DT_INST_REG_SIZE_BY_NAME(n, buffers) / 2)))
-#define ETH_LITEX_SLOT_TX1_ADDR(n) (ETH_LITEX_SLOT_TX0_ADDR(n) + ETH_LITEX_SLOT_SIZE)
+#define ETH_LITEX_SLOT_RX_N(n)                                                                     \
+	(DT_INST_REG_SIZE_BY_NAME_OR(n, rx_buffers, (DT_INST_REG_SIZE_BY_NAME(n, buffers) / 2)) /  \
+	 ETH_LITEX_SLOT_SIZE)
+#define ETH_LITEX_SLOT_TX_N(n)                                                                     \
+	(DT_INST_REG_SIZE_BY_NAME_OR(n, tx_buffers, (DT_INST_REG_SIZE_BY_NAME(n, buffers) / 2)) /  \
+	 ETH_LITEX_SLOT_SIZE)
 
 #define ETH_LITEX_INIT(n)                                                                          \
                                                                                                    \
@@ -324,8 +334,7 @@ static const struct ethernet_api eth_api = {
 		.mac_addr = DT_INST_PROP(n, local_mac_address)};                                   \
                                                                                                    \
 	static const struct eth_litex_config eth_config##n = {                                     \
-		IF_ENABLED(DT_INST_NODE_HAS_PROP(n, phy_handle),                                   \
-			   (.phy_dev = DEVICE_DT_GET(DT_INST_PHANDLE(n, phy_handle)),))            \
+		.phy_dev = DEVICE_DT_GET_OR_NULL(DT_INST_PHANDLE(n, phy_handle)),                  \
 		.config_func = eth_irq_config##n,                                                  \
 		.random_mac_address = DT_INST_PROP(n, zephyr_random_mac_address),                  \
 		.rx_slot_addr = DT_INST_REG_ADDR_BY_NAME(n, rx_slot),                              \
@@ -338,15 +347,10 @@ static const struct ethernet_api eth_api = {
 		.tx_length_addr = DT_INST_REG_ADDR_BY_NAME(n, tx_length),                          \
 		.tx_ev_pending_addr = DT_INST_REG_ADDR_BY_NAME(n, tx_ev_pending),                  \
 		.tx_ev_enable_addr = DT_INST_REG_ADDR_BY_NAME(n, tx_ev_enable),                    \
-		.rx_buf = {                                                                        \
-			(uint8_t *)ETH_LITEX_SLOT_RX0_ADDR(n),                                     \
-			(uint8_t *)ETH_LITEX_SLOT_RX1_ADDR(n),                                     \
-												   \
-		},                                                                                 \
-		.tx_buf = {                                                                        \
-			(uint8_t *)ETH_LITEX_SLOT_TX0_ADDR(n),                                     \
-			(uint8_t *)ETH_LITEX_SLOT_TX1_ADDR(n),                                     \
-		},                                                                                 \
+		.rx_buf_addr = ETH_LITEX_SLOT_RX_ADDR(n),                                          \
+		.tx_buf_addr = ETH_LITEX_SLOT_TX_ADDR(n),                                          \
+		.rx_buf_n = ETH_LITEX_SLOT_RX_N(n),                                                \
+		.tx_buf_n = ETH_LITEX_SLOT_TX_N(n),                                                \
                                                                                                    \
 	};                                                                                         \
                                                                                                    \
diff --git a/drivers/ethernet/eth_native_posix.c b/drivers/ethernet/eth_native_posix.c
deleted file mode 100644
index 5a5be070c75..00000000000
--- a/drivers/ethernet/eth_native_posix.c
+++ /dev/null
@@ -1,617 +0,0 @@
-/*
- * Copyright (c) 2018 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- *
- * Ethernet driver for native posix board. This is meant for network
- * connectivity between host and Zephyr.
- */
-
-#define LOG_MODULE_NAME eth_posix
-#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
-
-#include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(LOG_MODULE_NAME);
-
-#include <stdio.h>
-
-#include <zephyr/kernel.h>
-#include <stdbool.h>
-#include <errno.h>
-#include <stddef.h>
-#include <cmdline.h>
-#include <posix_native_task.h>
-
-#include <zephyr/net/net_pkt.h>
-#include <zephyr/net/net_core.h>
-#include <zephyr/net/net_if.h>
-#include <zephyr/net/ethernet.h>
-#include <ethernet/eth_stats.h>
-
-#include <zephyr/drivers/ptp_clock.h>
-#include <zephyr/net/gptp.h>
-#include <zephyr/net/lldp.h>
-
-#include "eth_native_posix_priv.h"
-#include "nsi_host_trampolines.h"
-#include "eth.h"
-
-#define NET_BUF_TIMEOUT K_MSEC(100)
-
-#if defined(CONFIG_NET_VLAN)
-#define ETH_HDR_LEN sizeof(struct net_eth_vlan_hdr)
-#else
-#define ETH_HDR_LEN sizeof(struct net_eth_hdr)
-#endif
-
-struct eth_context {
-	uint8_t recv[NET_ETH_MTU + ETH_HDR_LEN];
-	uint8_t send[NET_ETH_MTU + ETH_HDR_LEN];
-	uint8_t mac_addr[6];
-	struct net_linkaddr ll_addr;
-	struct net_if *iface;
-	const char *if_name;
-	k_tid_t rx_thread;
-	struct z_thread_stack_element *rx_stack;
-	size_t rx_stack_size;
-	int dev_fd;
-	bool init_done;
-	bool status;
-	bool promisc_mode;
-
-#if defined(CONFIG_NET_STATISTICS_ETHERNET)
-	struct net_stats_eth stats;
-#endif
-#if defined(CONFIG_ETH_NATIVE_POSIX_PTP_CLOCK)
-	const struct device *ptp_clock;
-#endif
-};
-
-static const char *if_name_cmd_opt;
-
-#define DEFINE_RX_THREAD(x, _)						\
-	K_KERNEL_STACK_DEFINE(rx_thread_stack_##x,			\
-			      CONFIG_ARCH_POSIX_RECOMMENDED_STACK_SIZE);\
-	static struct k_thread rx_thread_data_##x
-
-LISTIFY(CONFIG_ETH_NATIVE_POSIX_INTERFACE_COUNT, DEFINE_RX_THREAD, (;), _);
-
-#if defined(CONFIG_NET_GPTP)
-static bool need_timestamping(struct gptp_hdr *hdr)
-{
-	switch (hdr->message_type) {
-	case GPTP_SYNC_MESSAGE:
-	case GPTP_PATH_DELAY_RESP_MESSAGE:
-		return true;
-	default:
-		return false;
-	}
-}
-
-static struct gptp_hdr *check_gptp_msg(struct net_if *iface,
-				       struct net_pkt *pkt,
-				       bool is_tx)
-{
-	uint8_t *msg_start = net_pkt_data(pkt);
-	struct gptp_hdr *gptp_hdr;
-	int eth_hlen;
-	struct net_eth_hdr *hdr;
-
-	hdr = (struct net_eth_hdr *)msg_start;
-	if (ntohs(hdr->type) != NET_ETH_PTYPE_PTP) {
-		return NULL;
-	}
-
-	eth_hlen = sizeof(struct net_eth_hdr);
-
-	/* In TX, the first net_buf contains the Ethernet header
-	 * and the actual gPTP header is in the second net_buf.
-	 * In RX, the Ethernet header + other headers are in the
-	 * first net_buf.
-	 */
-	if (is_tx) {
-		if (pkt->frags->frags == NULL) {
-			return false;
-		}
-
-		gptp_hdr = (struct gptp_hdr *)pkt->frags->frags->data;
-	} else {
-		gptp_hdr = (struct gptp_hdr *)(pkt->frags->data + eth_hlen);
-	}
-
-	return gptp_hdr;
-}
-
-static void update_pkt_priority(struct gptp_hdr *hdr, struct net_pkt *pkt)
-{
-	if (GPTP_IS_EVENT_MSG(hdr->message_type)) {
-		net_pkt_set_priority(pkt, NET_PRIORITY_CA);
-	} else {
-		net_pkt_set_priority(pkt, NET_PRIORITY_IC);
-	}
-}
-
-static void update_gptp(struct net_if *iface, struct net_pkt *pkt,
-			bool send)
-{
-	struct net_ptp_time timestamp;
-	struct gptp_hdr *hdr;
-	int ret;
-
-	ret = eth_clock_gettime(&timestamp.second, &timestamp.nanosecond);
-	if (ret < 0) {
-		return;
-	}
-
-	net_pkt_set_timestamp(pkt, &timestamp);
-
-	hdr = check_gptp_msg(iface, pkt, send);
-	if (!hdr) {
-		return;
-	}
-
-	if (send) {
-		ret = need_timestamping(hdr);
-		if (ret) {
-			net_if_add_tx_timestamp(pkt);
-		}
-	} else {
-		update_pkt_priority(hdr, pkt);
-	}
-}
-#else
-#define update_gptp(iface, pkt, send)
-#endif /* CONFIG_NET_GPTP */
-
-static int eth_send(const struct device *dev, struct net_pkt *pkt)
-{
-	struct eth_context *ctx = dev->data;
-	int count = net_pkt_get_len(pkt);
-	int ret;
-
-	ret = net_pkt_read(pkt, ctx->send, count);
-	if (ret) {
-		return ret;
-	}
-
-	update_gptp(net_pkt_iface(pkt), pkt, true);
-
-	LOG_DBG("Send pkt %p len %d", pkt, count);
-
-	ret = nsi_host_write(ctx->dev_fd, ctx->send, count);
-	if (ret < 0) {
-		LOG_DBG("Cannot send pkt %p (%d)", pkt, ret);
-	}
-
-	return ret < 0 ? ret : 0;
-}
-
-static struct net_linkaddr *eth_get_mac(struct eth_context *ctx)
-{
-	ctx->ll_addr.addr = ctx->mac_addr;
-	ctx->ll_addr.len = sizeof(ctx->mac_addr);
-
-	return &ctx->ll_addr;
-}
-
-static struct net_pkt *prepare_pkt(struct eth_context *ctx,
-				   int count, int *status)
-{
-	struct net_pkt *pkt;
-
-	pkt = net_pkt_rx_alloc_with_buffer(ctx->iface, count,
-					   AF_UNSPEC, 0, NET_BUF_TIMEOUT);
-	if (!pkt) {
-		*status = -ENOMEM;
-		return NULL;
-	}
-
-	if (net_pkt_write(pkt, ctx->recv, count)) {
-		net_pkt_unref(pkt);
-		*status = -ENOBUFS;
-		return NULL;
-	}
-
-	*status = 0;
-
-	LOG_DBG("Recv pkt %p len %d", pkt, count);
-
-	return pkt;
-}
-
-static int read_data(struct eth_context *ctx, int fd)
-{
-	struct net_if *iface = ctx->iface;
-	struct net_pkt *pkt = NULL;
-	int status;
-	int count;
-
-	count = nsi_host_read(fd, ctx->recv, sizeof(ctx->recv));
-	if (count <= 0) {
-		return 0;
-	}
-
-	pkt = prepare_pkt(ctx, count, &status);
-	if (!pkt) {
-		return status;
-	}
-
-	update_gptp(iface, pkt, false);
-
-	if (net_recv_data(iface, pkt) < 0) {
-		net_pkt_unref(pkt);
-	}
-
-	return 0;
-}
-
-static void eth_rx(void *p1, void *p2, void *p3)
-{
-	ARG_UNUSED(p2);
-	ARG_UNUSED(p3);
-
-	struct eth_context *ctx = p1;
-	LOG_DBG("Starting ZETH RX thread");
-
-	while (1) {
-		if (net_if_is_up(ctx->iface)) {
-			while (!eth_wait_data(ctx->dev_fd)) {
-				read_data(ctx, ctx->dev_fd);
-				k_yield();
-			}
-		}
-
-		k_sleep(K_MSEC(CONFIG_ETH_NATIVE_POSIX_RX_TIMEOUT));
-	}
-}
-
-#if defined(CONFIG_THREAD_MAX_NAME_LEN)
-#define THREAD_MAX_NAME_LEN CONFIG_THREAD_MAX_NAME_LEN
-#else
-#define THREAD_MAX_NAME_LEN 1
-#endif
-
-static void create_rx_handler(struct eth_context *ctx)
-{
-	k_thread_create(ctx->rx_thread,
-			ctx->rx_stack,
-			ctx->rx_stack_size,
-			eth_rx,
-			ctx, NULL, NULL, K_PRIO_COOP(14),
-			0, K_NO_WAIT);
-
-	if (IS_ENABLED(CONFIG_THREAD_NAME)) {
-		char name[THREAD_MAX_NAME_LEN];
-
-		snprintk(name, sizeof(name), "eth_native_posix_rx-%s",
-			 ctx->if_name);
-		k_thread_name_set(ctx->rx_thread, name);
-	}
-}
-
-static void eth_iface_init(struct net_if *iface)
-{
-	struct eth_context *ctx = net_if_get_device(iface)->data;
-	struct net_linkaddr *ll_addr = eth_get_mac(ctx);
-
-	ctx->iface = iface;
-
-	ethernet_init(iface);
-
-	if (ctx->init_done) {
-		return;
-	}
-
-	net_lldp_set_lldpdu(iface);
-
-	ctx->init_done = true;
-
-#if defined(CONFIG_ETH_NATIVE_POSIX_RANDOM_MAC)
-	/* 00-00-5E-00-53-xx Documentation RFC 7042 */
-	gen_random_mac(ctx->mac_addr, 0x00, 0x00, 0x5E);
-
-	ctx->mac_addr[3] = 0x00;
-	ctx->mac_addr[4] = 0x53;
-
-	/* The TUN/TAP setup script will by default set the MAC address of host
-	 * interface to 00:00:5E:00:53:FF so do not allow that.
-	 */
-	if (ctx->mac_addr[5] == 0xff) {
-		ctx->mac_addr[5] = 0x01;
-	}
-#else
-	/* Difficult to configure MAC addresses any sane way if we have more
-	 * than one network interface.
-	 */
-	BUILD_ASSERT(CONFIG_ETH_NATIVE_POSIX_INTERFACE_COUNT == 1,
-		     "Cannot have static MAC if interface count > 1");
-
-	if (CONFIG_ETH_NATIVE_POSIX_MAC_ADDR[0] != 0) {
-		if (net_bytes_from_str(ctx->mac_addr, sizeof(ctx->mac_addr),
-				       CONFIG_ETH_NATIVE_POSIX_MAC_ADDR) < 0) {
-			LOG_ERR("Invalid MAC address %s",
-				CONFIG_ETH_NATIVE_POSIX_MAC_ADDR);
-		}
-	}
-#endif
-
-	/* If we have only one network interface, then use the name
-	 * defined in the Kconfig directly. This way there is no need to
-	 * change the documentation etc. and break things.
-	 */
-	if (CONFIG_ETH_NATIVE_POSIX_INTERFACE_COUNT == 1) {
-		ctx->if_name = CONFIG_ETH_NATIVE_POSIX_DRV_NAME;
-	}
-
-	if (if_name_cmd_opt != NULL) {
-		ctx->if_name = if_name_cmd_opt;
-	}
-
-	LOG_DBG("Interface %p using \"%s\"", iface, ctx->if_name);
-
-	net_if_set_link_addr(iface, ll_addr->addr, ll_addr->len,
-			     NET_LINK_ETHERNET);
-
-	ctx->dev_fd = eth_iface_create(CONFIG_ETH_NATIVE_POSIX_DEV_NAME, ctx->if_name, false);
-	if (ctx->dev_fd < 0) {
-		LOG_ERR("Cannot create %s (%d/%s)", ctx->if_name, ctx->dev_fd,
-			strerror(-ctx->dev_fd));
-	} else {
-		/* Create a thread that will handle incoming data from host */
-		create_rx_handler(ctx);
-	}
-}
-
-static
-enum ethernet_hw_caps eth_posix_native_get_capabilities(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-	return ETHERNET_TXTIME
-#if defined(CONFIG_NET_VLAN)
-		| ETHERNET_HW_VLAN
-#endif
-#if defined(CONFIG_ETH_NATIVE_POSIX_VLAN_TAG_STRIP)
-		| ETHERNET_HW_VLAN_TAG_STRIP
-#endif
-#if defined(CONFIG_ETH_NATIVE_POSIX_PTP_CLOCK)
-		| ETHERNET_PTP
-#endif
-#if defined(CONFIG_NET_PROMISCUOUS_MODE)
-		| ETHERNET_PROMISC_MODE
-#endif
-#if defined(CONFIG_NET_LLDP)
-		| ETHERNET_LLDP
-#endif
-		;
-}
-
-#if defined(CONFIG_ETH_NATIVE_POSIX_PTP_CLOCK)
-static const struct device *eth_get_ptp_clock(const struct device *dev)
-{
-	struct eth_context *context = dev->data;
-
-	return context->ptp_clock;
-}
-#endif
-
-#if defined(CONFIG_NET_STATISTICS_ETHERNET)
-static struct net_stats_eth *get_stats(const struct device *dev)
-{
-	struct eth_context *context = dev->data;
-
-	return &(context->stats);
-}
-#endif
-
-static int set_config(const struct device *dev,
-		      enum ethernet_config_type type,
-		      const struct ethernet_config *config)
-{
-	int ret = 0;
-
-	if (IS_ENABLED(CONFIG_NET_PROMISCUOUS_MODE) &&
-	    type == ETHERNET_CONFIG_TYPE_PROMISC_MODE) {
-		struct eth_context *context = dev->data;
-
-		if (config->promisc_mode) {
-			if (context->promisc_mode) {
-				return -EALREADY;
-			}
-
-			context->promisc_mode = true;
-		} else {
-			if (!context->promisc_mode) {
-				return -EALREADY;
-			}
-
-			context->promisc_mode = false;
-		}
-
-		ret = eth_promisc_mode(context->if_name,
-				       context->promisc_mode);
-	} else if (type == ETHERNET_CONFIG_TYPE_MAC_ADDRESS) {
-		struct eth_context *context = dev->data;
-
-		memcpy(context->mac_addr, config->mac_address.addr,
-		       sizeof(context->mac_addr));
-	}
-
-	return ret;
-}
-
-#if defined(CONFIG_NET_VLAN)
-static int vlan_setup(const struct device *dev, struct net_if *iface,
-		      uint16_t tag, bool enable)
-{
-	if (enable) {
-		net_lldp_set_lldpdu(iface);
-	} else {
-		net_lldp_unset_lldpdu(iface);
-	}
-
-	return 0;
-}
-#endif /* CONFIG_NET_VLAN */
-
-static const struct ethernet_api eth_if_api = {
-	.iface_api.init = eth_iface_init,
-
-	.get_capabilities = eth_posix_native_get_capabilities,
-	.set_config = set_config,
-	.send = eth_send,
-
-#if defined(CONFIG_NET_VLAN)
-	.vlan_setup = vlan_setup,
-#endif
-#if defined(CONFIG_NET_STATISTICS_ETHERNET)
-	.get_stats = get_stats,
-#endif
-#if defined(CONFIG_ETH_NATIVE_POSIX_PTP_CLOCK)
-	.get_ptp_clock = eth_get_ptp_clock,
-#endif
-};
-
-#define DEFINE_ETH_DEV_DATA(x, _)					     \
-	static struct eth_context eth_context_data_##x = {		     \
-		.if_name = CONFIG_ETH_NATIVE_POSIX_DRV_NAME #x,		     \
-		.rx_thread = &rx_thread_data_##x,			     \
-		.rx_stack = rx_thread_stack_##x,			     \
-		.rx_stack_size = K_KERNEL_STACK_SIZEOF(rx_thread_stack_##x), \
-	}
-
-LISTIFY(CONFIG_ETH_NATIVE_POSIX_INTERFACE_COUNT, DEFINE_ETH_DEV_DATA, (;), _);
-
-#define DEFINE_ETH_DEVICE(x, _)						\
-	ETH_NET_DEVICE_INIT(eth_native_posix_##x,			\
-			    CONFIG_ETH_NATIVE_POSIX_DRV_NAME #x,	\
-			    NULL, NULL,	&eth_context_data_##x, NULL,	\
-			    CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,	\
-			    &eth_if_api,				\
-			    NET_ETH_MTU)
-
-LISTIFY(CONFIG_ETH_NATIVE_POSIX_INTERFACE_COUNT, DEFINE_ETH_DEVICE, (;), _);
-
-#if defined(CONFIG_ETH_NATIVE_POSIX_PTP_CLOCK)
-
-#if defined(CONFIG_NET_GPTP)
-BUILD_ASSERT(								\
-	CONFIG_ETH_NATIVE_POSIX_INTERFACE_COUNT == CONFIG_NET_GPTP_NUM_PORTS, \
-	"Number of network interfaces must match gPTP port count");
-#endif
-
-struct ptp_context {
-	struct eth_context *eth_context;
-};
-
-#define DEFINE_PTP_DEV_DATA(x, _) \
-	static struct ptp_context ptp_context_##x
-
-LISTIFY(CONFIG_ETH_NATIVE_POSIX_INTERFACE_COUNT, DEFINE_PTP_DEV_DATA, (;), _);
-
-static int ptp_clock_set_native_posix(const struct device *clk,
-				      struct net_ptp_time *tm)
-{
-	ARG_UNUSED(clk);
-	ARG_UNUSED(tm);
-
-	/* We cannot set the host device time so this function
-	 * does nothing.
-	 */
-
-	return 0;
-}
-
-static int ptp_clock_get_native_posix(const struct device *clk,
-				      struct net_ptp_time *tm)
-{
-	ARG_UNUSED(clk);
-
-	return eth_clock_gettime(&tm->second, &tm->nanosecond);
-}
-
-static int ptp_clock_adjust_native_posix(const struct device *clk,
-					 int increment)
-{
-	ARG_UNUSED(clk);
-	ARG_UNUSED(increment);
-
-	/* We cannot adjust the host device time so this function
-	 * does nothing.
-	 */
-
-	return 0;
-}
-
-static int ptp_clock_rate_adjust_native_posix(const struct device *clk,
-					      double ratio)
-{
-	ARG_UNUSED(clk);
-	ARG_UNUSED(ratio);
-
-	/* We cannot adjust the host device time so this function
-	 * does nothing.
-	 */
-
-	return 0;
-}
-
-static DEVICE_API(ptp_clock, api) = {
-	.set = ptp_clock_set_native_posix,
-	.get = ptp_clock_get_native_posix,
-	.adjust = ptp_clock_adjust_native_posix,
-	.rate_adjust = ptp_clock_rate_adjust_native_posix,
-};
-
-#define PTP_INIT_FUNC(x, _)						\
-	static int ptp_init_##x(const struct device *port)			\
-	{								\
-		const struct device *const eth_dev = DEVICE_GET(eth_native_posix_##x); \
-		struct eth_context *context = eth_dev->data;	\
-		struct ptp_context *ptp_context = port->data;	\
-									\
-		context->ptp_clock = port;				\
-		ptp_context->eth_context = context;			\
-									\
-		return 0;						\
-	}
-
-LISTIFY(CONFIG_ETH_NATIVE_POSIX_INTERFACE_COUNT, PTP_INIT_FUNC, (), _)
-
-#define DEFINE_PTP_DEVICE(x, _)						\
-	DEVICE_DEFINE(eth_native_posix_ptp_clock_##x,			\
-			    PTP_CLOCK_NAME "_" #x,			\
-			    ptp_init_##x,				\
-			    NULL,					\
-			    &ptp_context_##x,				\
-			    NULL,					\
-			    POST_KERNEL,				\
-			    CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,	\
-			    &api)
-
-LISTIFY(CONFIG_ETH_NATIVE_POSIX_INTERFACE_COUNT, DEFINE_PTP_DEVICE, (;), _);
-
-#endif /* CONFIG_ETH_NATIVE_POSIX_PTP_CLOCK */
-
-static void add_native_posix_options(void)
-{
-	static struct args_struct_t eth_native_posix_options[] = {
-		{
-			.is_mandatory = false,
-			.option = "eth-if",
-			.name = "name",
-			.type = 's',
-			.dest = (void *)&if_name_cmd_opt,
-			.descript = "Name of the eth interface to use",
-		},
-		ARG_TABLE_ENDMARKER,
-	};
-
-	native_add_command_line_opts(eth_native_posix_options);
-}
-
-NATIVE_TASK(add_native_posix_options, PRE_BOOT_1, 10);
diff --git a/drivers/ethernet/eth_native_posix_adapt.c b/drivers/ethernet/eth_native_posix_adapt.c
deleted file mode 100644
index 81ae9bdcf8f..00000000000
--- a/drivers/ethernet/eth_native_posix_adapt.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Copyright (c) 2018 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- *
- * Routines setting up the host system. Those are placed in separate file
- * because there is naming conflicts between host and zephyr network stacks.
- */
-
-/* Host include files */
-#include <stdio.h>
-#include <stdlib.h>
-#include <stdarg.h>
-#include <errno.h>
-#include <string.h>
-#include <stdbool.h>
-#include <unistd.h>
-#include <fcntl.h>
-#include <sys/ioctl.h>
-#include <sys/socket.h>
-#include <sys/select.h>
-#include <net/if.h>
-#include <time.h>
-#include <inttypes.h>
-#include <nsi_tracing.h>
-
-#ifdef __linux
-#include <linux/if.h>
-#include <linux/if_tun.h>
-#endif
-
-#include "eth_native_posix_priv.h"
-
-/* Note that we cannot create the TUN/TAP device from the setup script
- * as we need to get a file descriptor to communicate with the interface.
- */
-int eth_iface_create(const char *dev_name, const char *if_name, bool tun_only)
-{
-	struct ifreq ifr;
-	int fd, ret = -EINVAL;
-
-	fd = open(dev_name, O_RDWR);
-	if (fd < 0) {
-		return -errno;
-	}
-
-	(void)memset(&ifr, 0, sizeof(ifr));
-
-#ifdef __linux
-	ifr.ifr_flags = (tun_only ? IFF_TUN : IFF_TAP) | IFF_NO_PI;
-
-	strncpy(ifr.ifr_name, if_name, IFNAMSIZ - 1);
-
-	ret = ioctl(fd, TUNSETIFF, (void *)&ifr);
-	if (ret < 0) {
-		ret = -errno;
-		close(fd);
-		return ret;
-	}
-#endif
-
-	return fd;
-}
-
-int eth_iface_remove(int fd)
-{
-	return close(fd);
-}
-
-static int ssystem(const char *fmt, ...)
-	__attribute__((__format__(__printf__, 1, 2)));
-
-static int ssystem(const char *fmt, ...)
-{
-	char cmd[255];
-	va_list ap;
-	int ret;
-
-	va_start(ap, fmt);
-	vsnprintf(cmd, sizeof(cmd), fmt, ap);
-	va_end(ap);
-
-	nsi_print_trace("%s\n", cmd);
-
-	ret = system(cmd);
-
-	return -WEXITSTATUS(ret);
-}
-
-int eth_wait_data(int fd)
-{
-	struct timeval timeout;
-	fd_set rset;
-	int ret;
-
-	FD_ZERO(&rset);
-
-	FD_SET(fd, &rset);
-
-	timeout.tv_sec = 0;
-	timeout.tv_usec = 0;
-
-	ret = select(fd + 1, &rset, NULL, NULL, &timeout);
-	if (ret < 0 && errno != EINTR) {
-		return -errno;
-	} else if (ret > 0) {
-		if (FD_ISSET(fd, &rset)) {
-			return 0;
-		}
-	}
-
-	return -EAGAIN;
-}
-
-int eth_clock_gettime(uint64_t *second, uint32_t *nanosecond)
-{
-	struct timespec tp;
-	int ret;
-
-	ret = clock_gettime(CLOCK_MONOTONIC_RAW, &tp);
-	if (ret < 0) {
-		return -errno;
-	}
-
-	*second = (uint64_t)tp.tv_sec;
-	*nanosecond = (uint32_t)tp.tv_nsec;
-
-	return 0;
-}
-
-int eth_promisc_mode(const char *if_name, bool enable)
-{
-	return ssystem("ip link set dev %s promisc %s",
-		       if_name, enable ? "on" : "off");
-}
diff --git a/drivers/ethernet/eth_native_posix_priv.h b/drivers/ethernet/eth_native_posix_priv.h
deleted file mode 100644
index f1d56f8df17..00000000000
--- a/drivers/ethernet/eth_native_posix_priv.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (c) 2018 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/** @file
- * @brief Private functions for native posix ethernet driver.
- */
-
-#ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_NATIVE_POSIX_PRIV_H_
-#define ZEPHYR_DRIVERS_ETHERNET_ETH_NATIVE_POSIX_PRIV_H_
-
-int eth_iface_create(const char *dev_name, const char *if_name, bool tun_only);
-int eth_iface_remove(int fd);
-int eth_wait_data(int fd);
-int eth_clock_gettime(uint64_t *second, uint32_t *nanosecond);
-int eth_promisc_mode(const char *if_name, bool enable);
-
-#endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_NATIVE_POSIX_PRIV_H_ */
diff --git a/drivers/ethernet/eth_native_tap.c b/drivers/ethernet/eth_native_tap.c
new file mode 100644
index 00000000000..8e8f696e14e
--- /dev/null
+++ b/drivers/ethernet/eth_native_tap.c
@@ -0,0 +1,688 @@
+/*
+ * Copyright (c) 2018 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ *
+ * TAP Ethernet driver for the native_sim board. This is meant for network
+ * connectivity between the host and Zephyr.
+ *
+ * Note this driver is divided in two files. This one, built in the embedded code context,
+ * with whichever libC is used in that context, and eth_native_tap_adapt.c built with the host
+ * libC.
+ */
+
+#define LOG_MODULE_NAME eth_tap
+#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(LOG_MODULE_NAME);
+
+#include <stdio.h>
+
+#include <zephyr/kernel.h>
+#include <stdbool.h>
+#include <errno.h>
+#include <stddef.h>
+#include <cmdline.h>
+#include <posix_native_task.h>
+
+#include <zephyr/net/net_pkt.h>
+#include <zephyr/net/net_core.h>
+#include <zephyr/net/net_if.h>
+#include <zephyr/net/ethernet.h>
+#include <ethernet/eth_stats.h>
+
+#include <zephyr/drivers/ptp_clock.h>
+#include <zephyr/net/gptp.h>
+#include <zephyr/net/lldp.h>
+
+#include "eth_native_tap_priv.h"
+#include "nsi_host_trampolines.h"
+#include "eth.h"
+
+#define NET_BUF_TIMEOUT K_MSEC(100)
+
+#if defined(CONFIG_NET_VLAN)
+#define ETH_HDR_LEN sizeof(struct net_eth_vlan_hdr)
+#else
+#define ETH_HDR_LEN sizeof(struct net_eth_hdr)
+#endif
+
+struct eth_context {
+	uint8_t recv[NET_ETH_MTU + ETH_HDR_LEN];
+	uint8_t send[NET_ETH_MTU + ETH_HDR_LEN];
+	uint8_t mac_addr[6];
+	struct net_linkaddr ll_addr;
+	struct net_if *iface;
+	const char *if_name;
+	k_tid_t rx_thread;
+	struct z_thread_stack_element *rx_stack;
+	size_t rx_stack_size;
+	int dev_fd;
+	bool init_done;
+	bool status;
+	bool promisc_mode;
+
+#if defined(CONFIG_NET_STATISTICS_ETHERNET)
+	struct net_stats_eth stats;
+#endif
+#if defined(CONFIG_ETH_NATIVE_TAP_PTP_CLOCK)
+	const struct device *ptp_clock;
+#endif
+};
+
+static const char *if_name_cmd_opt;
+static const char *mac_addr_cmd_opt;
+#ifdef CONFIG_NET_IPV4
+static const char *ipv4_addr_cmd_opt;
+static const char *ipv4_nm_cmd_opt;
+static const char *ipv4_gw_cmd_opt;
+#endif
+
+
+#define DEFINE_RX_THREAD(x, _)						\
+	K_KERNEL_STACK_DEFINE(rx_thread_stack_##x,			\
+			      CONFIG_ARCH_POSIX_RECOMMENDED_STACK_SIZE);\
+	static struct k_thread rx_thread_data_##x
+
+LISTIFY(CONFIG_ETH_NATIVE_TAP_INTERFACE_COUNT, DEFINE_RX_THREAD, (;), _);
+
+#if defined(CONFIG_NET_GPTP)
+static bool need_timestamping(struct gptp_hdr *hdr)
+{
+	switch (hdr->message_type) {
+	case GPTP_SYNC_MESSAGE:
+	case GPTP_PATH_DELAY_RESP_MESSAGE:
+		return true;
+	default:
+		return false;
+	}
+}
+
+static struct gptp_hdr *check_gptp_msg(struct net_if *iface,
+				       struct net_pkt *pkt,
+				       bool is_tx)
+{
+	uint8_t *msg_start = net_pkt_data(pkt);
+	struct gptp_hdr *gptp_hdr;
+	int eth_hlen;
+	struct net_eth_hdr *hdr;
+
+	hdr = (struct net_eth_hdr *)msg_start;
+	if (ntohs(hdr->type) != NET_ETH_PTYPE_PTP) {
+		return NULL;
+	}
+
+	eth_hlen = sizeof(struct net_eth_hdr);
+
+	/* In TX, the first net_buf contains the Ethernet header
+	 * and the actual gPTP header is in the second net_buf.
+	 * In RX, the Ethernet header + other headers are in the
+	 * first net_buf.
+	 */
+	if (is_tx) {
+		if (pkt->frags->frags == NULL) {
+			return false;
+		}
+
+		gptp_hdr = (struct gptp_hdr *)pkt->frags->frags->data;
+	} else {
+		gptp_hdr = (struct gptp_hdr *)(pkt->frags->data + eth_hlen);
+	}
+
+	return gptp_hdr;
+}
+
+static void update_pkt_priority(struct gptp_hdr *hdr, struct net_pkt *pkt)
+{
+	if (GPTP_IS_EVENT_MSG(hdr->message_type)) {
+		net_pkt_set_priority(pkt, NET_PRIORITY_CA);
+	} else {
+		net_pkt_set_priority(pkt, NET_PRIORITY_IC);
+	}
+}
+
+static void update_gptp(struct net_if *iface, struct net_pkt *pkt,
+			bool send)
+{
+	struct net_ptp_time timestamp;
+	struct gptp_hdr *hdr;
+	int ret;
+
+	ret = eth_clock_gettime(&timestamp.second, &timestamp.nanosecond);
+	if (ret < 0) {
+		return;
+	}
+
+	net_pkt_set_timestamp(pkt, &timestamp);
+
+	hdr = check_gptp_msg(iface, pkt, send);
+	if (!hdr) {
+		return;
+	}
+
+	if (send) {
+		ret = need_timestamping(hdr);
+		if (ret) {
+			net_if_add_tx_timestamp(pkt);
+		}
+	} else {
+		update_pkt_priority(hdr, pkt);
+	}
+}
+#else
+#define update_gptp(iface, pkt, send)
+#endif /* CONFIG_NET_GPTP */
+
+static int eth_send(const struct device *dev, struct net_pkt *pkt)
+{
+	struct eth_context *ctx = dev->data;
+	int count = net_pkt_get_len(pkt);
+	int ret;
+
+	ret = net_pkt_read(pkt, ctx->send, count);
+	if (ret) {
+		return ret;
+	}
+
+	update_gptp(net_pkt_iface(pkt), pkt, true);
+
+	LOG_DBG("Send pkt %p len %d", pkt, count);
+
+	ret = nsi_host_write(ctx->dev_fd, ctx->send, count);
+	if (ret < 0) {
+		LOG_DBG("Cannot send pkt %p (%d)", pkt, ret);
+	}
+
+	return ret < 0 ? ret : 0;
+}
+
+static struct net_linkaddr *eth_get_mac(struct eth_context *ctx)
+{
+	(void)net_linkaddr_set(&ctx->ll_addr, ctx->mac_addr,
+			       sizeof(ctx->mac_addr));
+
+	return &ctx->ll_addr;
+}
+
+static struct net_pkt *prepare_pkt(struct eth_context *ctx,
+				   int count, int *status)
+{
+	struct net_pkt *pkt;
+
+	pkt = net_pkt_rx_alloc_with_buffer(ctx->iface, count,
+					   AF_UNSPEC, 0, NET_BUF_TIMEOUT);
+	if (!pkt) {
+		*status = -ENOMEM;
+		return NULL;
+	}
+
+	if (net_pkt_write(pkt, ctx->recv, count)) {
+		net_pkt_unref(pkt);
+		*status = -ENOBUFS;
+		return NULL;
+	}
+
+	*status = 0;
+
+	LOG_DBG("Recv pkt %p len %d", pkt, count);
+
+	return pkt;
+}
+
+static int read_data(struct eth_context *ctx, int fd)
+{
+	struct net_if *iface = ctx->iface;
+	struct net_pkt *pkt = NULL;
+	int status;
+	int count;
+
+	count = nsi_host_read(fd, ctx->recv, sizeof(ctx->recv));
+	if (count <= 0) {
+		return 0;
+	}
+
+	pkt = prepare_pkt(ctx, count, &status);
+	if (!pkt) {
+		return status;
+	}
+
+	update_gptp(iface, pkt, false);
+
+	if (net_recv_data(iface, pkt) < 0) {
+		net_pkt_unref(pkt);
+	}
+
+	return 0;
+}
+
+static void eth_rx(void *p1, void *p2, void *p3)
+{
+	ARG_UNUSED(p2);
+	ARG_UNUSED(p3);
+
+	struct eth_context *ctx = p1;
+	LOG_DBG("Starting ZETH RX thread");
+
+	while (1) {
+		if (net_if_is_up(ctx->iface)) {
+			while (!eth_wait_data(ctx->dev_fd)) {
+				read_data(ctx, ctx->dev_fd);
+				k_yield();
+			}
+		}
+
+		k_sleep(K_MSEC(CONFIG_ETH_NATIVE_TAP_RX_TIMEOUT));
+	}
+}
+
+#if defined(CONFIG_THREAD_MAX_NAME_LEN)
+#define THREAD_MAX_NAME_LEN CONFIG_THREAD_MAX_NAME_LEN
+#else
+#define THREAD_MAX_NAME_LEN 1
+#endif
+
+static void create_rx_handler(struct eth_context *ctx)
+{
+	k_thread_create(ctx->rx_thread,
+			ctx->rx_stack,
+			ctx->rx_stack_size,
+			eth_rx,
+			ctx, NULL, NULL, K_PRIO_COOP(14),
+			0, K_NO_WAIT);
+
+	if (IS_ENABLED(CONFIG_THREAD_NAME)) {
+		char name[THREAD_MAX_NAME_LEN];
+
+		snprintk(name, sizeof(name), "eth_native_tap_rx-%s",
+			 ctx->if_name);
+		k_thread_name_set(ctx->rx_thread, name);
+	}
+}
+
+static void eth_iface_init(struct net_if *iface)
+{
+	struct eth_context *ctx = net_if_get_device(iface)->data;
+	struct net_linkaddr *ll_addr = eth_get_mac(ctx);
+#if !defined(CONFIG_ETH_NATIVE_TAP_RANDOM_MAC)
+	const char *mac_addr =
+		mac_addr_cmd_opt ? mac_addr_cmd_opt : CONFIG_ETH_NATIVE_TAP_MAC_ADDR;
+#endif
+#ifdef CONFIG_NET_IPV4
+	struct in_addr addr, netmask;
+#endif
+
+	ctx->iface = iface;
+
+	ethernet_init(iface);
+
+	if (ctx->init_done) {
+		return;
+	}
+
+	net_lldp_set_lldpdu(iface);
+
+	ctx->init_done = true;
+
+#if defined(CONFIG_ETH_NATIVE_TAP_RANDOM_MAC)
+	/* 00-00-5E-00-53-xx Documentation RFC 7042 */
+	gen_random_mac(ctx->mac_addr, 0x00, 0x00, 0x5E);
+
+	ctx->mac_addr[3] = 0x00;
+	ctx->mac_addr[4] = 0x53;
+
+	/* The TUN/TAP setup script will by default set the MAC address of host
+	 * interface to 00:00:5E:00:53:FF so do not allow that.
+	 */
+	if (ctx->mac_addr[5] == 0xff) {
+		ctx->mac_addr[5] = 0x01;
+	}
+#else
+	/* Difficult to configure MAC addresses any sane way if we have more
+	 * than one network interface.
+	 */
+	BUILD_ASSERT(CONFIG_ETH_NATIVE_TAP_INTERFACE_COUNT == 1,
+		     "Cannot have static MAC if interface count > 1");
+
+	if (mac_addr[0] != 0) {
+		if (net_bytes_from_str(ctx->mac_addr, sizeof(ctx->mac_addr), mac_addr) < 0) {
+			LOG_ERR("Invalid MAC address %s", mac_addr);
+		}
+	}
+#endif
+
+	/* If we have only one network interface, then use the name
+	 * defined in the Kconfig directly. This way there is no need to
+	 * change the documentation etc. and break things.
+	 */
+	if (CONFIG_ETH_NATIVE_TAP_INTERFACE_COUNT == 1) {
+		ctx->if_name = CONFIG_ETH_NATIVE_TAP_DRV_NAME;
+	}
+
+	if (if_name_cmd_opt != NULL) {
+		ctx->if_name = if_name_cmd_opt;
+	}
+
+	LOG_DBG("Interface %p using \"%s\"", iface, ctx->if_name);
+
+	net_if_set_link_addr(iface, ll_addr->addr, ll_addr->len,
+			     NET_LINK_ETHERNET);
+
+#ifdef CONFIG_NET_IPV4
+	if (ipv4_addr_cmd_opt != NULL) {
+		if (net_addr_pton(AF_INET, ipv4_addr_cmd_opt, &addr) == 0) {
+			net_if_ipv4_addr_add(iface, &addr, NET_ADDR_MANUAL, 0);
+
+			if (ipv4_nm_cmd_opt != NULL) {
+				if (net_addr_pton(AF_INET, ipv4_nm_cmd_opt, &netmask) == 0) {
+					net_if_ipv4_set_netmask_by_addr(iface, &addr, &netmask);
+				} else {
+					NET_ERR("Invalid netmask: %s", ipv4_nm_cmd_opt);
+				}
+			}
+		} else {
+			NET_ERR("Invalid address: %s", ipv4_addr_cmd_opt);
+		}
+	}
+
+	if (ipv4_gw_cmd_opt != NULL) {
+		if (net_addr_pton(AF_INET, ipv4_gw_cmd_opt, &addr) == 0) {
+			net_if_ipv4_set_gw(iface, &addr);
+		} else {
+			NET_ERR("Invalid gateway: %s", ipv4_gw_cmd_opt);
+		}
+	}
+#endif
+
+	ctx->dev_fd = eth_iface_create(CONFIG_ETH_NATIVE_POSIX_DEV_NAME, ctx->if_name, false);
+	if (ctx->dev_fd < 0) {
+		LOG_ERR("Cannot create %s (%d/%s)", ctx->if_name, ctx->dev_fd,
+			strerror(-ctx->dev_fd));
+	} else {
+		/* Create a thread that will handle incoming data from host */
+		create_rx_handler(ctx);
+	}
+}
+
+static enum ethernet_hw_caps eth_native_tap_get_capabilities(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return ETHERNET_TXTIME
+#if defined(CONFIG_NET_VLAN)
+		| ETHERNET_HW_VLAN
+#endif
+#if defined(CONFIG_ETH_NATIVE_TAP_VLAN_TAG_STRIP)
+		| ETHERNET_HW_VLAN_TAG_STRIP
+#endif
+#if defined(CONFIG_ETH_NATIVE_TAP_PTP_CLOCK)
+		| ETHERNET_PTP
+#endif
+#if defined(CONFIG_NET_PROMISCUOUS_MODE)
+		| ETHERNET_PROMISC_MODE
+#endif
+#if defined(CONFIG_NET_LLDP)
+		| ETHERNET_LLDP
+#endif
+		;
+}
+
+#if defined(CONFIG_ETH_NATIVE_TAP_PTP_CLOCK)
+static const struct device *eth_get_ptp_clock(const struct device *dev)
+{
+	struct eth_context *context = dev->data;
+
+	return context->ptp_clock;
+}
+#endif
+
+#if defined(CONFIG_NET_STATISTICS_ETHERNET)
+static struct net_stats_eth *get_stats(const struct device *dev)
+{
+	struct eth_context *context = dev->data;
+
+	return &(context->stats);
+}
+#endif
+
+static int set_config(const struct device *dev,
+		      enum ethernet_config_type type,
+		      const struct ethernet_config *config)
+{
+	int ret = 0;
+
+	if (IS_ENABLED(CONFIG_NET_PROMISCUOUS_MODE) &&
+	    type == ETHERNET_CONFIG_TYPE_PROMISC_MODE) {
+		struct eth_context *context = dev->data;
+
+		if (config->promisc_mode) {
+			if (context->promisc_mode) {
+				return -EALREADY;
+			}
+
+			context->promisc_mode = true;
+		} else {
+			if (!context->promisc_mode) {
+				return -EALREADY;
+			}
+
+			context->promisc_mode = false;
+		}
+
+		ret = eth_promisc_mode(context->if_name,
+				       context->promisc_mode);
+	} else if (type == ETHERNET_CONFIG_TYPE_MAC_ADDRESS) {
+		struct eth_context *context = dev->data;
+
+		memcpy(context->mac_addr, config->mac_address.addr,
+		       sizeof(context->mac_addr));
+	}
+
+	return ret;
+}
+
+#if defined(CONFIG_NET_VLAN)
+static int vlan_setup(const struct device *dev, struct net_if *iface,
+		      uint16_t tag, bool enable)
+{
+	if (enable) {
+		net_lldp_set_lldpdu(iface);
+	} else {
+		net_lldp_unset_lldpdu(iface);
+	}
+
+	return 0;
+}
+#endif /* CONFIG_NET_VLAN */
+
+static const struct ethernet_api eth_if_api = {
+	.iface_api.init = eth_iface_init,
+
+	.get_capabilities = eth_native_tap_get_capabilities,
+	.set_config = set_config,
+	.send = eth_send,
+
+#if defined(CONFIG_NET_VLAN)
+	.vlan_setup = vlan_setup,
+#endif
+#if defined(CONFIG_NET_STATISTICS_ETHERNET)
+	.get_stats = get_stats,
+#endif
+#if defined(CONFIG_ETH_NATIVE_TAP_PTP_CLOCK)
+	.get_ptp_clock = eth_get_ptp_clock,
+#endif
+};
+
+#define DEFINE_ETH_DEV_DATA(x, _)					     \
+	static struct eth_context eth_context_data_##x = {		     \
+		.if_name = CONFIG_ETH_NATIVE_TAP_DRV_NAME #x,		     \
+		.rx_thread = &rx_thread_data_##x,			     \
+		.rx_stack = rx_thread_stack_##x,			     \
+		.rx_stack_size = K_KERNEL_STACK_SIZEOF(rx_thread_stack_##x), \
+	}
+
+LISTIFY(CONFIG_ETH_NATIVE_TAP_INTERFACE_COUNT, DEFINE_ETH_DEV_DATA, (;), _);
+
+#define DEFINE_ETH_DEVICE(x, _)						\
+	ETH_NET_DEVICE_INIT(eth_native_tap_##x,				\
+			    CONFIG_ETH_NATIVE_TAP_DRV_NAME #x,		\
+			    NULL, NULL,	&eth_context_data_##x, NULL,	\
+			    CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,	\
+			    &eth_if_api,				\
+			    NET_ETH_MTU)
+
+LISTIFY(CONFIG_ETH_NATIVE_TAP_INTERFACE_COUNT, DEFINE_ETH_DEVICE, (;), _);
+
+#if defined(CONFIG_ETH_NATIVE_TAP_PTP_CLOCK)
+
+#if defined(CONFIG_NET_GPTP)
+BUILD_ASSERT(								\
+	CONFIG_ETH_NATIVE_TAP_INTERFACE_COUNT == CONFIG_NET_GPTP_NUM_PORTS, \
+	"Number of network interfaces must match gPTP port count");
+#endif
+
+struct ptp_context {
+	struct eth_context *eth_context;
+};
+
+#define DEFINE_PTP_DEV_DATA(x, _) \
+	static struct ptp_context ptp_context_##x
+
+LISTIFY(CONFIG_ETH_NATIVE_TAP_INTERFACE_COUNT, DEFINE_PTP_DEV_DATA, (;), _);
+
+static int ptp_clock_set_native_tap(const struct device *clk, struct net_ptp_time *tm)
+{
+	ARG_UNUSED(clk);
+	ARG_UNUSED(tm);
+
+	/* We cannot set the host device time so this function
+	 * does nothing.
+	 */
+
+	return 0;
+}
+
+static int ptp_clock_get_native_tap(const struct device *clk, struct net_ptp_time *tm)
+{
+	ARG_UNUSED(clk);
+
+	return eth_clock_gettime(&tm->second, &tm->nanosecond);
+}
+
+static int ptp_clock_adjust_native_tap(const struct device *clk, int increment)
+{
+	ARG_UNUSED(clk);
+	ARG_UNUSED(increment);
+
+	/* We cannot adjust the host device time so this function
+	 * does nothing.
+	 */
+
+	return 0;
+}
+
+static int ptp_clock_rate_adjust_native_tap(const struct device *clk, double ratio)
+{
+	ARG_UNUSED(clk);
+	ARG_UNUSED(ratio);
+
+	/* We cannot adjust the host device time so this function
+	 * does nothing.
+	 */
+
+	return 0;
+}
+
+static DEVICE_API(ptp_clock, api) = {
+	.set = ptp_clock_set_native_tap,
+	.get = ptp_clock_get_native_tap,
+	.adjust = ptp_clock_adjust_native_tap,
+	.rate_adjust = ptp_clock_rate_adjust_native_tap,
+};
+
+#define PTP_INIT_FUNC(x, _)						\
+	static int ptp_init_##x(const struct device *port)			\
+	{								\
+		const struct device *const eth_dev = DEVICE_GET(eth_native_tap_##x); \
+		struct eth_context *context = eth_dev->data;	\
+		struct ptp_context *ptp_context = port->data;	\
+									\
+		context->ptp_clock = port;				\
+		ptp_context->eth_context = context;			\
+									\
+		return 0;						\
+	}
+
+LISTIFY(CONFIG_ETH_NATIVE_TAP_INTERFACE_COUNT, PTP_INIT_FUNC, (), _)
+
+#define DEFINE_PTP_DEVICE(x, _)						\
+	DEVICE_DEFINE(eth_native_tap_ptp_clock_##x,			\
+			    PTP_CLOCK_NAME "_" #x,			\
+			    ptp_init_##x,				\
+			    NULL,					\
+			    &ptp_context_##x,				\
+			    NULL,					\
+			    POST_KERNEL,				\
+			    CONFIG_KERNEL_INIT_PRIORITY_DEFAULT,	\
+			    &api)
+
+LISTIFY(CONFIG_ETH_NATIVE_TAP_INTERFACE_COUNT, DEFINE_PTP_DEVICE, (;), _);
+
+#endif /* CONFIG_ETH_NATIVE_TAP_PTP_CLOCK */
+
+static void add_native_tap_options(void)
+{
+	static struct args_struct_t eth_native_tap_options[] = {
+		{
+			.is_mandatory = false,
+			.option = "eth-if",
+			.name = "name",
+			.type = 's',
+			.dest = (void *)&if_name_cmd_opt,
+			.descript = "Name of the eth interface to use",
+		},
+		{
+			.is_mandatory = false,
+			.option = "mac-addr",
+			.name = "mac",
+			.type = 's',
+			.dest = (void *)&mac_addr_cmd_opt,
+			.descript = "MAC address",
+		},
+#ifdef CONFIG_NET_IPV4
+		{
+			.is_mandatory = false,
+			.option = "ipv4-addr",
+			.name = "ipv4",
+			.type = 's',
+			.dest = (void *)&ipv4_addr_cmd_opt,
+			.descript = "IPv4 address",
+		},
+		{
+			.is_mandatory = false,
+			.option = "ipv4-gw",
+			.name = "ipv4",
+			.type = 's',
+			.dest = (void *)&ipv4_gw_cmd_opt,
+			.descript = "IPv4 gateway",
+		},
+		{
+			.is_mandatory = false,
+			.option = "ipv4-nm",
+			.name = "ipv4",
+			.type = 's',
+			.dest = (void *)&ipv4_nm_cmd_opt,
+			.descript = "IPv4 netmask",
+		},
+#endif
+		ARG_TABLE_ENDMARKER,
+	};
+
+	native_add_command_line_opts(eth_native_tap_options);
+}
+
+NATIVE_TASK(add_native_tap_options, PRE_BOOT_1, 10);
diff --git a/drivers/ethernet/eth_native_tap_adapt.c b/drivers/ethernet/eth_native_tap_adapt.c
new file mode 100644
index 00000000000..3bdd6ac7548
--- /dev/null
+++ b/drivers/ethernet/eth_native_tap_adapt.c
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2018 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ *
+ * Routines setting up the host system. Those are placed in a separate file
+ * to avoid naming conflicts between host and zephyr network stacks.
+ * This file is built with the host libC in the native simulator runner context.
+ */
+
+/* Host include files */
+#include <stdio.h>
+#include <stdlib.h>
+#include <stdarg.h>
+#include <errno.h>
+#include <string.h>
+#include <stdbool.h>
+#include <unistd.h>
+#include <fcntl.h>
+#include <sys/ioctl.h>
+#include <sys/socket.h>
+#include <sys/select.h>
+#include <net/if.h>
+#include <time.h>
+#include <inttypes.h>
+#include <nsi_tracing.h>
+
+#ifdef __linux
+#include <linux/if.h>
+#include <linux/if_tun.h>
+#endif
+
+#include "eth_native_tap_priv.h"
+
+/* Note that we cannot create the TUN/TAP device from the setup script
+ * as we need to get a file descriptor to communicate with the interface.
+ */
+int eth_iface_create(const char *dev_name, const char *if_name, bool tun_only)
+{
+	struct ifreq ifr;
+	int fd, ret = -EINVAL;
+
+	fd = open(dev_name, O_RDWR);
+	if (fd < 0) {
+		return -errno;
+	}
+
+	(void)memset(&ifr, 0, sizeof(ifr));
+
+#ifdef __linux
+	ifr.ifr_flags = (tun_only ? IFF_TUN : IFF_TAP) | IFF_NO_PI;
+
+	strncpy(ifr.ifr_name, if_name, IFNAMSIZ - 1);
+
+	ret = ioctl(fd, TUNSETIFF, (void *)&ifr);
+	if (ret < 0) {
+		ret = -errno;
+		close(fd);
+		return ret;
+	}
+#endif
+
+	return fd;
+}
+
+int eth_iface_remove(int fd)
+{
+	return close(fd);
+}
+
+static int ssystem(const char *fmt, ...)
+	__attribute__((__format__(__printf__, 1, 2)));
+
+static int ssystem(const char *fmt, ...)
+{
+	char cmd[255];
+	va_list ap;
+	int ret;
+
+	va_start(ap, fmt);
+	vsnprintf(cmd, sizeof(cmd), fmt, ap);
+	va_end(ap);
+
+	nsi_print_trace("%s\n", cmd);
+
+	ret = system(cmd);
+
+	return -WEXITSTATUS(ret);
+}
+
+int eth_wait_data(int fd)
+{
+	struct timeval timeout;
+	fd_set rset;
+	int ret;
+
+	FD_ZERO(&rset);
+
+	FD_SET(fd, &rset);
+
+	timeout.tv_sec = 0;
+	timeout.tv_usec = 0;
+
+	ret = select(fd + 1, &rset, NULL, NULL, &timeout);
+	if (ret < 0 && errno != EINTR) {
+		return -errno;
+	} else if (ret > 0) {
+		if (FD_ISSET(fd, &rset)) {
+			return 0;
+		}
+	}
+
+	return -EAGAIN;
+}
+
+int eth_clock_gettime(uint64_t *second, uint32_t *nanosecond)
+{
+	struct timespec tp;
+	int ret;
+
+	ret = clock_gettime(CLOCK_MONOTONIC_RAW, &tp);
+	if (ret < 0) {
+		return -errno;
+	}
+
+	*second = (uint64_t)tp.tv_sec;
+	*nanosecond = (uint32_t)tp.tv_nsec;
+
+	return 0;
+}
+
+int eth_promisc_mode(const char *if_name, bool enable)
+{
+	return ssystem("ip link set dev %s promisc %s",
+		       if_name, enable ? "on" : "off");
+}
diff --git a/drivers/ethernet/eth_native_tap_priv.h b/drivers/ethernet/eth_native_tap_priv.h
new file mode 100644
index 00000000000..0769ee73add
--- /dev/null
+++ b/drivers/ethernet/eth_native_tap_priv.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2018 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/** @file
+ * @brief Private functions for native TAP ethernet driver.
+ */
+
+#ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_NATIVE_TAP_PRIV_H_
+#define ZEPHYR_DRIVERS_ETHERNET_ETH_NATIVE_TAP_PRIV_H_
+
+int eth_iface_create(const char *dev_name, const char *if_name, bool tun_only);
+int eth_iface_remove(int fd);
+int eth_wait_data(int fd);
+int eth_clock_gettime(uint64_t *second, uint32_t *nanosecond);
+int eth_promisc_mode(const char *if_name, bool enable);
+
+#endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_NATIVE_TAP_PRIV_H_ */
diff --git a/drivers/ethernet/eth_numaker.c b/drivers/ethernet/eth_numaker.c
index 77577943f23..80b807e8f8b 100644
--- a/drivers/ethernet/eth_numaker.c
+++ b/drivers/ethernet/eth_numaker.c
@@ -21,22 +21,31 @@
 
 #ifdef CONFIG_SOC_M467
 #include <m460_eth.h>
+#else
+#include <numaker_eth.h>
 #endif
 
 LOG_MODULE_REGISTER(eth_numaker, CONFIG_ETHERNET_LOG_LEVEL);
 
 /* Device EMAC Interface port */
 #define NUMAKER_GMAC_INTF  0
-/* 2KB Data Flash at 0xFF800 */
-#define NUMAKER_DATA_FLASH (0xFF800U)
+
 #define NUMAKER_MASK_32    (0xFFFFFFFFU)
 #define NUMAKER_MII_CONFIG (ADVERTISE_CSMA | ADVERTISE_10HALF | ADVERTISE_10FULL | \
 							ADVERTISE_100HALF | ADVERTISE_100FULL)
 #define NUMAKER_MII_LINKED (BMSR_ANEGCOMPLETE | BMSR_LSTATUS)
 
 extern synopGMACdevice GMACdev[GMAC_CNT];
+
+#ifdef CONFIG_NOCACHE_MEMORY
+DmaDesc tx_desc[GMAC_CNT][TRANSMIT_DESC_SIZE] __nocache __aligned(64);
+DmaDesc rx_desc[GMAC_CNT][RECEIVE_DESC_SIZE] __nocache __aligned(64);
+struct sk_buff tx_buf[GMAC_CNT][TRANSMIT_DESC_SIZE] __nocache __aligned(64);
+struct sk_buff rx_buf[GMAC_CNT][RECEIVE_DESC_SIZE] __nocache __aligned(64);
+#else
 extern struct sk_buff tx_buf[GMAC_CNT][TRANSMIT_DESC_SIZE];
 extern struct sk_buff rx_buf[GMAC_CNT][RECEIVE_DESC_SIZE];
+#endif
 
 static uint32_t eth_phy_addr;
 
@@ -167,33 +176,31 @@ static int reset_phy(synopGMACdevice *gmacdev)
 
 static void m_numaker_read_mac_addr(char *mac)
 {
+#if DT_INST_PROP(0, zephyr_random_mac_address)
+	gen_random_mac(mac, NUMAKER_OUI_B0, NUMAKER_OUI_B1, NUMAKER_OUI_B2);
+#else
 	uint32_t uid1;
-	/* Fetch word 0 of data flash */
-	uint32_t word0 = *(uint32_t *)(NUMAKER_DATA_FLASH + 0x04U);
+	uint32_t word0;
 	/*
-	 * Fetch word 1 of data flash
 	 * we only want bottom 16 bits of word1 (MAC bits 32-47)
 	 * and bit 9 forced to 1, bit 8 forced to 0
 	 * Locally administered MAC, reduced conflicts
 	 * http://en.wikipedia.org/wiki/MAC_address
 	 */
-	uint32_t word1 = *(uint32_t *)NUMAKER_DATA_FLASH;
-
-	/* Not burn any mac address at the beginning of data flash */
-	if (word0 == NUMAKER_MASK_32) {
-		/* Generate a semi-unique MAC address from the UUID */
-		SYS_UnlockReg();
-		/* Enable FMC ISP function */
-		FMC_Open();
-		uid1 = FMC_ReadUID(1);
-		word1 = (uid1 & 0x003FFFFF) | ((uid1 & 0x030000) << 6) >> 8;
-		word0 = ((FMC_ReadUID(0) >> 4) << 20) | ((uid1 & 0xFF) << 12) |
-			(FMC_ReadUID(2) & 0xFFF);
-		/* Disable FMC ISP function */
-		FMC_Close();
-		/* Lock protected registers */
-		SYS_LockReg();
-	}
+	uint32_t word1;
+
+	/* Generate a semi-unique MAC address from the UUID */
+	SYS_UnlockReg();
+	/* Enable FMC ISP function */
+	FMC_Open();
+	uid1 = FMC_ReadUID(1);
+	word1 = (uid1 & 0x003FFFFF) | ((uid1 & 0x030000) << 6) >> 8;
+	word0 = ((FMC_ReadUID(0) >> 4) << 20) | ((uid1 & 0xFF) << 12) |
+		(FMC_ReadUID(2) & 0xFFF);
+	/* Disable FMC ISP function */
+	FMC_Close();
+	/* Lock protected registers */
+	SYS_LockReg();
 
 	word1 |= 0x00000200;
 	word1 &= 0x0000FEFF;
@@ -204,7 +211,7 @@ static void m_numaker_read_mac_addr(char *mac)
 	mac[3] = (word0 & 0x00ff0000) >> 16;
 	mac[4] = (word0 & 0x0000ff00) >> 8;
 	mac[5] = (word0 & 0x000000ff);
-
+#endif
 	LOG_INF("mac address %02x:%02x:%02x:%02x:%02x:%02x", mac[0], mac[1], mac[2], mac[3],
 	       mac[4], mac[5]);
 }
diff --git a/drivers/ethernet/eth_numaker_priv.h b/drivers/ethernet/eth_numaker_priv.h
index e3bec804b98..283081dd47c 100644
--- a/drivers/ethernet/eth_numaker_priv.h
+++ b/drivers/ethernet/eth_numaker_priv.h
@@ -15,4 +15,9 @@
 
 #define NU_ETH_MTU_SIZE              1500
 
+/* NuMaker chip's OUI*/
+#define NUMAKER_OUI_B0 0xDA
+#define NUMAKER_OUI_B1 0x00
+#define NUMAKER_OUI_B2 0x53
+
 #endif /* ZEPHYR_DRIVERS_ETHERNET_ETH_NUMAKER_PRIV_H_ */
diff --git a/drivers/ethernet/nxp_enet/eth_nxp_enet.c b/drivers/ethernet/eth_nxp_enet.c
similarity index 97%
rename from drivers/ethernet/nxp_enet/eth_nxp_enet.c
rename to drivers/ethernet/eth_nxp_enet.c
index dd850370f39..df5588a4b05 100644
--- a/drivers/ethernet/nxp_enet/eth_nxp_enet.c
+++ b/drivers/ethernet/eth_nxp_enet.c
@@ -39,7 +39,7 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
 #include <zephyr/drivers/ptp_clock.h>
 #endif
 
-#ifdef CONFIG_NET_DSA
+#ifdef CONFIG_NET_DSA_DEPRECATED
 #include <zephyr/net/dsa.h>
 #endif
 
@@ -47,7 +47,7 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
 #include <zephyr/pm/device.h>
 #endif
 
-#include "../eth.h"
+#include "eth.h"
 #include <zephyr/drivers/ethernet/eth_nxp_enet.h>
 #include <zephyr/dt-bindings/ethernet/nxp_enet.h>
 #include <fsl_enet.h>
@@ -260,8 +260,8 @@ static enum ethernet_hw_caps eth_nxp_enet_get_capabilities(const struct device *
 #if defined(CONFIG_PTP_CLOCK_NXP_ENET)
 		ETHERNET_PTP |
 #endif
-#if defined(CONFIG_NET_DSA)
-		ETHERNET_DSA_MASTER_PORT |
+#if defined(CONFIG_NET_DSA_DEPRECATED)
+		ETHERNET_DSA_CONDUIT_PORT |
 #endif
 #if defined(CONFIG_ETH_NXP_ENET_HW_ACCELERATION)
 		ETHERNET_HW_TX_CHKSUM_OFFLOAD |
@@ -415,7 +415,7 @@ static int eth_nxp_enet_rx(const struct device *dev)
 #endif /* CONFIG_PTP_CLOCK_NXP_ENET */
 
 	iface = get_iface(data);
-#if defined(CONFIG_NET_DSA)
+#if defined(CONFIG_NET_DSA_DEPRECATED)
 	iface = dsa_net_recv(iface, &pkt);
 #endif
 	if (net_recv_data(iface, pkt) < 0) {
@@ -461,6 +461,8 @@ static int nxp_enet_phy_configure(const struct device *phy, uint8_t phy_mode)
 {
 	enum phy_link_speed speeds = LINK_HALF_10BASE_T | LINK_FULL_10BASE_T |
 				       LINK_HALF_100BASE_T | LINK_FULL_100BASE_T;
+	int ret;
+	struct phy_link_state state;
 
 	if (COND_CODE_1(IS_ENABLED(CONFIG_ETH_NXP_ENET_1G),
 	   (phy_mode == NXP_ENET_RGMII_MODE), (0))) {
@@ -468,7 +470,27 @@ static int nxp_enet_phy_configure(const struct device *phy, uint8_t phy_mode)
 	}
 
 	/* Configure the PHY */
-	return phy_configure_link(phy, speeds);
+	ret = phy_configure_link(phy, speeds);
+
+	if (ret == -ENOTSUP) {
+		phy_get_link_state(phy, &state);
+
+		if (state.is_up) {
+			LOG_WRN("phy_configure_link returned -ENOTSUP, but link is up. "
+				"Speed: %s, %s-duplex",
+				PHY_LINK_IS_SPEED_1000M(state.speed) ? "1 Gbits" :
+				PHY_LINK_IS_SPEED_100M(state.speed) ? "100 Mbits" : "10 Mbits",
+				PHY_LINK_IS_FULL_DUPLEX(state.speed) ? "full" : "half");
+		} else {
+			LOG_ERR("phy_configure_link returned -ENOTSUP and link is down.");
+			return -ENETDOWN;
+		}
+	} else if (ret) {
+		LOG_ERR("phy_configure_link failed with error: %d", ret);
+		return ret;
+	}
+
+	return 0;
 }
 
 static void nxp_enet_phy_cb(const struct device *phy,
@@ -533,7 +555,7 @@ static void eth_nxp_enet_iface_init(struct net_if *iface)
 		data->iface = iface;
 	}
 
-#if defined(CONFIG_NET_DSA)
+#if defined(CONFIG_NET_DSA_DEPRECATED)
 	dsa_register_master_tx(iface, &eth_nxp_enet_tx);
 #endif
 
@@ -854,11 +876,11 @@ static int eth_nxp_enet_device_pm_action(const struct device *dev, enum pm_devic
 #define ETH_NXP_ENET_PM_DEVICE_GET(n) NULL
 #endif /* CONFIG_NET_POWER_MANAGEMENT */
 
-#ifdef CONFIG_NET_DSA
+#ifdef CONFIG_NET_DSA_DEPRECATED
 #define NXP_ENET_SEND_FUNC dsa_tx
 #else
 #define NXP_ENET_SEND_FUNC eth_nxp_enet_tx
-#endif /* CONFIG_NET_DSA */
+#endif /* CONFIG_NET_DSA_DEPRECATED */
 
 static const struct ethernet_api api_funcs = {
 	.iface_api.init		= eth_nxp_enet_iface_init,
@@ -882,9 +904,6 @@ static const struct ethernet_api api_funcs = {
 		irq_enable(DT_IRQ_BY_IDX(node_id, idx, irq));			\
 	} while (false);
 
-#define NXP_ENET_DT_PHY_DEV(node_id, phy_phandle, idx)						\
-	DEVICE_DT_GET(DT_PHANDLE_BY_IDX(node_id, phy_phandle, idx))
-
 #if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_dtcm)) && \
 	CONFIG_ETH_NXP_ENET_USE_DTCM_FOR_DMA_BUFFER
 #define _nxp_enet_dma_desc_section __dtcm_bss_section
diff --git a/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c b/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c
index 30b95eeff96..bd2b4f59de2 100644
--- a/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c
+++ b/drivers/ethernet/eth_nxp_enet_qos/eth_nxp_enet_qos_mac.c
@@ -73,14 +73,15 @@ static int eth_nxp_enet_qos_tx(const struct device *dev, struct net_pkt *pkt)
 		frags_count++;
 		total_bytes += fragment->len;
 		fragment = fragment->frags;
-	}
 
-	if (total_bytes > config->hw_info.max_frame_len ||
-	    frags_count > NUM_TX_BUFDESC) {
-		LOG_ERR("TX packet too large");
-		return -E2BIG;
+		if (total_bytes > config->hw_info.max_frame_len ||
+			frags_count > NUM_TX_BUFDESC) {
+			LOG_ERR("TX packet too large");
+			return -E2BIG;
+		}
 	}
 
+
 	/* One TX at a time in the current implementation */
 	k_sem_take(&data->tx.tx_sem, K_FOREVER);
 
diff --git a/drivers/ethernet/eth_nxp_imx_netc.c b/drivers/ethernet/eth_nxp_imx_netc.c
deleted file mode 100644
index 0791f8fa488..00000000000
--- a/drivers/ethernet/eth_nxp_imx_netc.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * Copyright 2024 NXP
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
-#include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(nxp_imx_eth);
-
-#include <zephyr/kernel.h>
-#include <zephyr/device.h>
-#include <zephyr/drivers/mbox.h>
-#include <zephyr/drivers/pinctrl.h>
-#include <zephyr/net/ethernet.h>
-#include <zephyr/net/net_if.h>
-#include <zephyr/net/net_pkt.h>
-#include <zephyr/net/phy.h>
-#include <ethernet/eth_stats.h>
-
-#include "eth.h"
-#include "eth_nxp_imx_netc_priv.h"
-
-const struct device *netc_dev_list[NETC_DRV_MAX_INST_SUPPORT];
-
-static int netc_eth_rx(const struct device *dev)
-{
-	struct netc_eth_data *data = dev->data;
-	struct net_pkt *pkt;
-	int key;
-	int ret = 0;
-	status_t result;
-	uint32_t length;
-
-	key = irq_lock();
-
-	/* Check rx frame */
-	result = EP_GetRxFrameSize(&data->handle, 0, &length);
-	if (result == kStatus_NETC_RxFrameEmpty) {
-		ret = -ENOBUFS;
-		goto out;
-	}
-
-	if (result != kStatus_Success) {
-		LOG_ERR("Error on received frame");
-		ret = -EIO;
-		goto out;
-	}
-
-	/* Receive frame */
-	result = EP_ReceiveFrameCopy(&data->handle, 0, data->rx_frame, length, NULL);
-	if (result != kStatus_Success) {
-		LOG_ERR("Error on received frame");
-		ret = -EIO;
-		goto out;
-	}
-
-	/* Copy to pkt */
-	pkt = net_pkt_rx_alloc_with_buffer(data->iface, length, AF_UNSPEC, 0, NETC_TIMEOUT);
-	if (!pkt) {
-		eth_stats_update_errors_rx(data->iface);
-		ret = -ENOBUFS;
-		goto out;
-	}
-
-	ret = net_pkt_write(pkt, data->rx_frame, length);
-	if (ret) {
-		eth_stats_update_errors_rx(data->iface);
-		net_pkt_unref(pkt);
-		goto out;
-	}
-
-	/* Send to upper layer */
-	ret = net_recv_data(data->iface, pkt);
-	if (ret < 0) {
-		eth_stats_update_errors_rx(data->iface);
-		net_pkt_unref(pkt);
-		LOG_ERR("Failed to enqueue frame into rx queue: %d", ret);
-	}
-out:
-	irq_unlock(key);
-	return ret;
-}
-
-static void netc_eth_rx_thread(void *arg1, void *unused1, void *unused2)
-{
-	const struct device *dev = (const struct device *)arg1;
-	struct netc_eth_data *data = dev->data;
-	int ret;
-	int work;
-
-	ARG_UNUSED(unused1);
-	ARG_UNUSED(unused2);
-
-	while (1) {
-		ret = k_sem_take(&data->rx_sem, K_FOREVER);
-		if (ret != 0) {
-			LOG_ERR("Take rx_sem error: %d", ret);
-			continue;
-		}
-
-		work = 0;
-		while (netc_eth_rx(dev) != -ENOBUFS) {
-			if (++work == CONFIG_ETH_NXP_IMX_RX_BUDGET) {
-				/* more work to do, reschedule */
-				work = 0;
-				k_yield();
-			}
-		}
-	}
-}
-
-static void msgintr_isr(void)
-{
-	uint32_t irqs = NETC_MSGINTR->MSI[NETC_MSGINTR_CHANNEL].MSIR;
-
-	for (int i = 0; i < NETC_DRV_MAX_INST_SUPPORT; i++) {
-		const struct device *dev = netc_dev_list[i];
-		const struct netc_eth_config *config;
-		struct netc_eth_data *data;
-
-		if (!dev) {
-			return;
-		}
-
-		config = dev->config;
-		data = dev->data;
-		/* Transmit interrupt */
-		if (irqs & (1 << config->tx_intr_msg_data)) {
-			EP_CleanTxIntrFlags(&data->handle, 1, 0);
-			data->tx_done = true;
-		}
-		/* Receive interrupt */
-		if (irqs & (1 << config->rx_intr_msg_data)) {
-			EP_CleanRxIntrFlags(&data->handle, 1);
-			k_sem_give(&data->rx_sem);
-		}
-	}
-
-	SDK_ISR_EXIT_BARRIER;
-}
-
-static status_t netc_eth_reclaim_callback(ep_handle_t *handle, uint8_t ring,
-					  netc_tx_frame_info_t *frameInfo, void *userData)
-{
-	struct netc_eth_data *data = userData;
-
-	data->tx_info = *frameInfo;
-	return kStatus_Success;
-}
-
-int netc_eth_init_common(const struct device *dev)
-{
-	const struct netc_eth_config *config = dev->config;
-	struct netc_eth_data *data = dev->data;
-	netc_msix_entry_t msix_entry[NETC_MSIX_ENTRY_NUM];
-	netc_rx_bdr_config_t rx_bdr_config = {0};
-	netc_tx_bdr_config_t tx_bdr_config = {0};
-	netc_bdr_config_t bdr_config = {0};
-	ep_config_t ep_config;
-	uint32_t msg_addr;
-	status_t result;
-
-	config->bdr_init(&bdr_config, &rx_bdr_config, &tx_bdr_config);
-
-	/* MSIX entry configuration */
-	msg_addr = MSGINTR_GetIntrSelectAddr(NETC_MSGINTR, NETC_MSGINTR_CHANNEL);
-	msix_entry[NETC_TX_MSIX_ENTRY_IDX].control = kNETC_MsixIntrMaskBit;
-	msix_entry[NETC_TX_MSIX_ENTRY_IDX].msgAddr = msg_addr;
-	msix_entry[NETC_TX_MSIX_ENTRY_IDX].msgData = config->tx_intr_msg_data;
-
-	msix_entry[NETC_RX_MSIX_ENTRY_IDX].control = kNETC_MsixIntrMaskBit;
-	msix_entry[NETC_RX_MSIX_ENTRY_IDX].msgAddr = msg_addr;
-	msix_entry[NETC_RX_MSIX_ENTRY_IDX].msgData = config->rx_intr_msg_data;
-
-	if (!irq_is_enabled(NETC_MSGINTR_IRQ)) {
-		IRQ_CONNECT(NETC_MSGINTR_IRQ, 0, msgintr_isr, 0, 0);
-		irq_enable(NETC_MSGINTR_IRQ);
-	}
-
-	/* Endpoint configuration. */
-	EP_GetDefaultConfig(&ep_config);
-	ep_config.si = config->si_idx;
-	ep_config.siConfig.txRingUse = 1;
-	ep_config.siConfig.rxRingUse = 1;
-	ep_config.userData = data;
-	ep_config.reclaimCallback = netc_eth_reclaim_callback;
-	ep_config.msixEntry = &msix_entry[0];
-	ep_config.entryNum = NETC_MSIX_ENTRY_NUM;
-	ep_config.port.ethMac.miiMode = kNETC_RmiiMode;
-	ep_config.port.ethMac.miiSpeed = kNETC_MiiSpeed100M;
-	ep_config.port.ethMac.miiDuplex = kNETC_MiiFullDuplex;
-	ep_config.rxCacheMaintain = true;
-	ep_config.txCacheMaintain = true;
-
-	config->generate_mac(&data->mac_addr[0]);
-
-	result = EP_Init(&data->handle, &data->mac_addr[0], &ep_config, &bdr_config);
-	if (result != kStatus_Success) {
-		return -ENOBUFS;
-	}
-
-	for (int i = 0; i < NETC_DRV_MAX_INST_SUPPORT; i++) {
-		if (!netc_dev_list[i]) {
-			netc_dev_list[i] = dev;
-			break;
-		}
-	}
-
-	/* Unmask MSIX message interrupt. */
-	EP_MsixSetEntryMask(&data->handle, NETC_TX_MSIX_ENTRY_IDX, false);
-	EP_MsixSetEntryMask(&data->handle, NETC_RX_MSIX_ENTRY_IDX, false);
-
-	k_mutex_init(&data->tx_mutex);
-
-	k_sem_init(&data->rx_sem, 0, 1);
-	k_thread_create(&data->rx_thread, data->rx_thread_stack,
-			K_KERNEL_STACK_SIZEOF(data->rx_thread_stack), netc_eth_rx_thread,
-			(void *)dev, NULL, NULL, K_PRIO_COOP(CONFIG_ETH_NXP_IMX_RX_THREAD_PRIO), 0,
-			K_NO_WAIT);
-	k_thread_name_set(&data->rx_thread, "netc_eth_rx");
-
-	return 0;
-}
-
-int netc_eth_tx(const struct device *dev, struct net_pkt *pkt)
-{
-	struct netc_eth_data *data = dev->data;
-	netc_buffer_struct_t buff = {.buffer = data->tx_buff, .length = sizeof(data->tx_buff)};
-	netc_frame_struct_t frame = {.buffArray = &buff, .length = 1};
-	size_t pkt_len = net_pkt_get_len(pkt);
-	status_t result;
-	int ret;
-
-	__ASSERT(pkt, "Packet pointer is NULL");
-
-	k_mutex_lock(&data->tx_mutex, K_FOREVER);
-
-	/* Copy packet to tx buffer */
-	buff.length = (uint16_t)pkt_len;
-	ret = net_pkt_read(pkt, buff.buffer, pkt_len);
-	if (ret) {
-		LOG_ERR("Failed to copy packet to tx buffer: %d", ret);
-		ret = -ENOBUFS;
-		goto error;
-	}
-
-	/* Send */
-	data->tx_done = false;
-	result = EP_SendFrame(&data->handle, 0, &frame, NULL, NULL);
-	if (result != kStatus_Success) {
-		LOG_ERR("Failed to tx frame");
-		ret = -EIO;
-		goto error;
-	}
-
-	while (!data->tx_done) {
-	}
-
-	EP_ReclaimTxDescriptor(&data->handle, 0);
-	if (data->tx_info.status != kNETC_EPTxSuccess) {
-		LOG_ERR("Failed to tx frame");
-		ret = -EIO;
-		goto error;
-	}
-	ret = 0;
-error:
-	k_mutex_unlock(&data->tx_mutex);
-
-	if (ret != 0) {
-		eth_stats_update_errors_tx(data->iface);
-	}
-	return ret;
-}
-
-enum ethernet_hw_caps netc_eth_get_capabilities(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-	return (ETHERNET_LINK_10BASE_T | ETHERNET_LINK_100BASE_T | ETHERNET_LINK_1000BASE_T |
-		ETHERNET_HW_RX_CHKSUM_OFFLOAD | ETHERNET_HW_FILTERING
-#if defined(CONFIG_NET_VLAN)
-		| ETHERNET_HW_VLAN
-#endif
-#if defined(CONFIG_NET_PROMISCUOUS_MODE)
-		| ETHERNET_PROMISC_MODE
-#endif
-	);
-}
-
-int netc_eth_set_config(const struct device *dev, enum ethernet_config_type type,
-			const struct ethernet_config *config)
-{
-	struct netc_eth_data *data = dev->data;
-	const struct netc_eth_config *cfg = dev->config;
-	status_t result;
-	int ret = 0;
-
-	switch (type) {
-	case ETHERNET_CONFIG_TYPE_MAC_ADDRESS:
-		/* Set new Ethernet MAC address and register it with the upper layer */
-		memcpy(data->mac_addr, config->mac_address.addr, sizeof(data->mac_addr));
-		result = EP_SetPrimaryMacAddr(&data->handle, (uint8_t *)data->mac_addr);
-		if (result != kStatus_Success) {
-			LOG_ERR("PHY device (%p) is not ready, cannot init iface", cfg->phy_dev);
-			ret = -ENOTSUP;
-			break;
-		}
-		net_if_set_link_addr(data->iface, data->mac_addr, sizeof(data->mac_addr),
-				     NET_LINK_ETHERNET);
-		LOG_INF("SI%d MAC set to: %02x:%02x:%02x:%02x:%02x:%02x", getSiIdx(cfg->si_idx),
-			data->mac_addr[0], data->mac_addr[1], data->mac_addr[2], data->mac_addr[3],
-			data->mac_addr[4], data->mac_addr[5]);
-		break;
-	default:
-		ret = -ENOTSUP;
-		break;
-	}
-
-	return ret;
-}
diff --git a/drivers/ethernet/eth_renesas_ra.c b/drivers/ethernet/eth_renesas_ra.c
index 9ce7d41a7ab..809d0d189e6 100644
--- a/drivers/ethernet/eth_renesas_ra.c
+++ b/drivers/ethernet/eth_renesas_ra.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -35,6 +35,8 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
 #define ETHER_TOTAL_BUF_NUM         (CONFIG_ETH_RENESAS_TX_BUF_NUM + CONFIG_ETH_RENESAS_RX_BUF_NUM)
 #define ETHER_EE_RECEIVE_EVENT_MASK (0x01070000)
 
+BUILD_ASSERT(DT_INST_ENUM_IDX(0, phy_connection_type) <= 1, "Invalid PHY connection setting");
+
 void ether_eint_isr(void);
 void renesas_ra_eth_callback(ether_callback_args_t *p_args);
 static void renesas_ra_eth_buffer_init(const struct device *dev);
@@ -232,7 +234,6 @@ static void renesas_ra_eth_initialize(struct net_if *iface)
 	const struct device *dev = net_if_get_device(iface);
 	struct renesas_ra_eth_context *ctx = dev->data;
 	const struct renesas_ra_eth_config *cfg = dev->config;
-	const char *phy_connection_type = DT_INST_PROP_OR(0, phy_connection_type, "rmii");
 
 	LOG_DBG("eth_initialize");
 
@@ -244,15 +245,6 @@ static void renesas_ra_eth_initialize(struct net_if *iface)
 
 	ethernet_init(iface);
 
-	R_PMISC->PFENET = (uint8_t)(0x0 << R_PMISC_PFENET_PHYMODE0_Pos);
-
-	if (strstr(phy_connection_type, "mii") != NULL) {
-		/* Configure pins for MII or RMII. Set PHYMODE0 if MII is selected. */
-		R_PMISC->PFENET = (uint8_t)(0x1 << R_PMISC_PFENET_PHYMODE0_Pos);
-	} else {
-		LOG_ERR("Failed to init ether - phy-connection-type not support");
-	}
-
 	err = R_ETHER_Open(&ctx->ctrl, cfg->p_cfg);
 
 	if (err != FSP_SUCCESS) {
@@ -378,14 +370,28 @@ static void renesas_ra_eth_thread(void *p1, void *p2, void *p3)
 	}
 }
 
-#define ELC_EVENT_EDMAC_EINT(channel) ELC_EVENT_EDMAC##channel##_EINT
+#define EVENT_EDMAC_EINT(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_EDMAC, channel, _EINT))
 
 /* Bindings to the platform */
 int renesas_ra_eth_init(const struct device *dev)
 {
 	struct renesas_ra_eth_context *ctx = dev->data;
 
-	R_ICU->IELSR[DT_INST_IRQN(0)] = ELC_EVENT_EDMAC_EINT(0);
+	switch (DT_INST_ENUM_IDX(0, phy_connection_type)) {
+	case 0: /* mii */
+		R_PMISC->PFENET = (uint8_t)(0x1 << R_PMISC_PFENET_PHYMODE0_Pos);
+		break;
+	case 1: /* rmii */
+		R_PMISC->PFENET = (uint8_t)(0x0 << R_PMISC_PFENET_PHYMODE0_Pos);
+		break;
+	default:
+		/* Build assert at top of file should catch this case */
+		LOG_ERR("Failed to init Ethernet driver - phy-connection-type not support");
+
+		return -EINVAL;
+	}
+
+	R_ICU->IELSR[DT_INST_IRQN(0)] = EVENT_EDMAC_EINT(0);
 
 	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), renesas_ra_eth_isr,
 		    DEVICE_DT_INST_GET(0), 0);
diff --git a/drivers/ethernet/eth_sam_gmac.c b/drivers/ethernet/eth_sam_gmac.c
index e3748a86108..e81edb7daea 100644
--- a/drivers/ethernet/eth_sam_gmac.c
+++ b/drivers/ethernet/eth_sam_gmac.c
@@ -403,7 +403,7 @@ static inline void eth_sam_gmac_init_qav(Gmac *gmac)
 /*
  * Reset ring buffer
  */
-static void ring_buf_reset(struct ring_buf *rb)
+static void ring_buffer_reset(struct ring_buffer *rb)
 {
 	rb->head = 0U;
 	rb->tail = 0U;
@@ -412,7 +412,7 @@ static void ring_buf_reset(struct ring_buf *rb)
 /*
  * Get one 32 bit item from the ring buffer
  */
-static uint32_t ring_buf_get(struct ring_buf *rb)
+static uint32_t ring_buffer_get(struct ring_buffer *rb)
 {
 	uint32_t val;
 
@@ -428,7 +428,7 @@ static uint32_t ring_buf_get(struct ring_buf *rb)
 /*
  * Put one 32 bit item into the ring buffer
  */
-static void ring_buf_put(struct ring_buf *rb, uint32_t val)
+static void ring_buffer_put(struct ring_buffer *rb, uint32_t val)
 {
 	rb->buf[rb->head] = val;
 	MODULO_INC(rb->head, rb->len);
@@ -528,9 +528,9 @@ static void tx_descriptors_init(Gmac *gmac, struct gmac_queue *queue)
 
 #if GMAC_MULTIPLE_TX_PACKETS == 1
 	/* Reset TX frame list */
-	ring_buf_reset(&queue->tx_frag_list);
+	ring_buffer_reset(&queue->tx_frag_list);
 #if defined(CONFIG_PTP_CLOCK_SAM_GMAC)
-	ring_buf_reset(&queue->tx_frames);
+	ring_buffer_reset(&queue->tx_frames);
 #endif
 #endif
 }
@@ -721,14 +721,14 @@ static void tx_completed(Gmac *gmac, struct gmac_queue *queue)
 		k_sem_give(&queue->tx_desc_sem);
 
 		/* Release net buffer to the buffer pool */
-		frag = UINT_TO_POINTER(ring_buf_get(&queue->tx_frag_list));
+		frag = UINT_TO_POINTER(ring_buffer_get(&queue->tx_frag_list));
 		net_pkt_frag_unref(frag);
 		LOG_DBG("Dropping frag %p", frag);
 
 		if (tx_desc->w1 & GMAC_TXW1_LASTBUFFER) {
 #if defined(CONFIG_PTP_CLOCK_SAM_GMAC)
 			/* Release net packet to the packet pool */
-			pkt = UINT_TO_POINTER(ring_buf_get(&queue->tx_frames));
+			pkt = UINT_TO_POINTER(ring_buffer_get(&queue->tx_frames));
 
 #if defined(CONFIG_NET_GPTP)
 			hdr = check_gptp_msg(get_iface(dev_data),
@@ -756,10 +756,10 @@ static void tx_error_handler(Gmac *gmac, struct gmac_queue *queue)
 {
 #if GMAC_MULTIPLE_TX_PACKETS == 1
 	struct net_buf *frag;
-	struct ring_buf *tx_frag_list = &queue->tx_frag_list;
+	struct ring_buffer *tx_frag_list = &queue->tx_frag_list;
 #if defined(CONFIG_PTP_CLOCK_SAM_GMAC)
 	struct net_pkt *pkt;
-	struct ring_buf *tx_frames = &queue->tx_frames;
+	struct ring_buffer *tx_frames = &queue->tx_frames;
 #endif
 #endif
 
@@ -1495,7 +1495,7 @@ static int eth_tx(const struct device *dev, struct net_pkt *pkt)
 			 "tx_desc_list overflow");
 
 		/* Account for a sent frag */
-		ring_buf_put(&queue->tx_frag_list, POINTER_TO_UINT(frag));
+		ring_buffer_put(&queue->tx_frag_list, POINTER_TO_UINT(frag));
 
 		/* frag is internally queued, so it requires to hold a reference */
 		net_pkt_frag_ref(frag);
@@ -1533,7 +1533,7 @@ static int eth_tx(const struct device *dev, struct net_pkt *pkt)
 #if GMAC_MULTIPLE_TX_PACKETS == 1
 #if defined(CONFIG_PTP_CLOCK_SAM_GMAC)
 	/* Account for a sent frame */
-	ring_buf_put(&queue->tx_frames, POINTER_TO_UINT(pkt));
+	ring_buffer_put(&queue->tx_frames, POINTER_TO_UINT(pkt));
 
 	/* pkt is internally queued, so it requires to hold a reference */
 	net_pkt_ref(pkt);
@@ -1901,6 +1901,8 @@ static void eth0_iface_init(struct net_if *iface)
 #endif
 #endif
 	if (device_is_ready(cfg->phy_dev)) {
+		net_if_carrier_off(iface);
+
 		phy_link_callback_set(cfg->phy_dev, &phy_link_state_changed,
 				      (void *)dev);
 
@@ -1908,11 +1910,6 @@ static void eth0_iface_init(struct net_if *iface)
 		LOG_ERR("PHY device not ready");
 	}
 
-	/* Do not start the interface until PHY link is up */
-	if (!(dev_data->link_up)) {
-		net_if_carrier_off(iface);
-	}
-
 	init_done = true;
 }
 
diff --git a/drivers/ethernet/eth_sam_gmac_priv.h b/drivers/ethernet/eth_sam_gmac_priv.h
index 8fd5a2b257b..c2a94a1c3f1 100644
--- a/drivers/ethernet/eth_sam_gmac_priv.h
+++ b/drivers/ethernet/eth_sam_gmac_priv.h
@@ -208,7 +208,7 @@ enum queue_idx {
 #endif
 
 /** Minimal ring buffer implementation */
-struct ring_buf {
+struct ring_buffer {
 	uint32_t *buf;
 	uint16_t len;
 	uint16_t head;
@@ -242,9 +242,9 @@ struct gmac_queue {
 	struct net_buf **rx_frag_list;
 
 #if GMAC_MULTIPLE_TX_PACKETS == 1
-	struct ring_buf tx_frag_list;
+	struct ring_buffer tx_frag_list;
 #if defined(CONFIG_PTP_CLOCK_SAM_GMAC)
-	struct ring_buf tx_frames;
+	struct ring_buffer tx_frames;
 #endif
 #endif
 
diff --git a/drivers/ethernet/eth_sensry_sy1xx_mac.c b/drivers/ethernet/eth_sensry_sy1xx_mac.c
new file mode 100644
index 00000000000..6a885cbc913
--- /dev/null
+++ b/drivers/ethernet/eth_sensry_sy1xx_mac.c
@@ -0,0 +1,622 @@
+/*
+ * Copyright (c) 2025 sensry.io
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT sensry_sy1xx_mac
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(sy1xx_mac, CONFIG_ETHERNET_LOG_LEVEL);
+
+#include <sys/types.h>
+#include <zephyr/kernel.h>
+#include <zephyr/net/ethernet.h>
+#include <zephyr/sys/barrier.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/net/phy.h>
+#include <udma.h>
+#include "eth.h"
+
+/* MAC register offsets */
+#define SY1XX_MAC_VERSION_REG      0x0000
+#define SY1XX_MAC_ADDRESS_LOW_REG  0x0004
+#define SY1XX_MAC_ADDRESS_HIGH_REG 0x0008
+#define SY1XX_MAC_CTRL_REG         0x000c
+
+/* MAC control register bit offsets */
+#define SY1XX_MAC_CTRL_RESET_OFFS   (0)
+#define SY1XX_MAC_CTRL_RX_EN_OFFS   (1)
+#define SY1XX_MAC_CTRL_TX_EN_OFFS   (2)
+#define SY1XX_MAC_CTRL_GMII_OFFS    (3)
+#define SY1XX_MAC_CTRL_CLK_DIV_OFFS (8)
+#define SY1XX_MAC_CTRL_CLK_SEL_OFFS (10)
+
+/* MAC clock sources */
+#define SY1XX_MAC_CTRL_CLK_SEL_REF_CLK 0
+#define SY1XX_MAC_CTRL_CLK_SEL_MII_CLK 1
+
+/* Clock divider options */
+#define SY1XX_MAC_CTRL_CLK_DIV_1  0x0
+#define SY1XX_MAC_CTRL_CLK_DIV_5  0x1
+#define SY1XX_MAC_CTRL_CLK_DIV_10 0x2
+#define SY1XX_MAC_CTRL_CLK_DIV_50 0x3
+
+/* Clock divider mask */
+#define SY1XX_MAC_CTRL_CLK_DIV_MASK (0x3)
+
+#define MAX_MAC_PACKET_LEN      1600
+#define MAX_TX_RETRIES          5
+#define RECEIVE_GRACE_TIME_MSEC 1
+
+#define SY1XX_ETH_STACK_SIZE      4096
+#define SY1XX_ETH_THREAD_PRIORITY K_PRIO_PREEMPT(0)
+
+struct sy1xx_mac_dev_config {
+	/* address of controller configuration registers */
+	uint32_t ctrl_addr;
+	/* address of udma for data transfers */
+	uint32_t base_addr;
+	/* optional - enable promiscuous mode */
+	bool promiscuous_mode;
+	/* optional - device tree mac */
+	bool use_local_mac_address;
+	uint8_t local_mac_address[6];
+	/* optional - random mac */
+	bool use_zephyr_random_mac;
+
+	/* phy config */
+	const struct device *phy_dev;
+
+	/* pinctrl for rgmii pins */
+	const struct pinctrl_dev_config *pcfg;
+};
+
+struct sy1xx_mac_dma_buffers {
+	uint8_t tx[MAX_MAC_PACKET_LEN];
+	uint8_t rx[MAX_MAC_PACKET_LEN];
+};
+
+struct sy1xx_mac_dev_data {
+	struct k_mutex mutex;
+
+	/* current state of link and mac address */
+	bool link_is_up;
+	enum phy_link_speed link_speed;
+
+	uint8_t mac_addr[6];
+
+	/* intermediate, linear buffers that can hold a received or transmit msg */
+	struct {
+		uint8_t tx[MAX_MAC_PACKET_LEN];
+		uint16_t tx_len;
+
+		uint8_t rx[MAX_MAC_PACKET_LEN];
+		uint16_t rx_len;
+	} temp;
+
+	/* buffers used for dma transfer, cannot be accessed while transfer active */
+	struct sy1xx_mac_dma_buffers *dma_buffers;
+
+	struct k_thread rx_data_thread;
+
+	K_KERNEL_STACK_MEMBER(rx_data_thread_stack, SY1XX_ETH_STACK_SIZE);
+
+	struct net_if *iface;
+};
+
+/* prototypes */
+static int sy1xx_mac_set_mac_addr(const struct device *dev, uint8_t *mac_addr);
+static int sy1xx_mac_set_promiscuous_mode(const struct device *dev, bool promiscuous_mode);
+static int sy1xx_mac_set_config(const struct device *dev, enum ethernet_config_type type,
+				const struct ethernet_config *config);
+static void sy1xx_mac_rx_thread_entry(void *p1, void *p2, void *p3);
+
+static int sy1xx_mac_initialize(const struct device *dev)
+{
+	struct sy1xx_mac_dev_config *cfg = (struct sy1xx_mac_dev_config *)dev->config;
+	struct sy1xx_mac_dev_data *data = (struct sy1xx_mac_dev_data *)dev->data;
+	int ret;
+
+	data->link_is_up = false;
+	data->link_speed = -1;
+
+	k_mutex_init(&data->mutex);
+
+	/* PAD config */
+	ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret) {
+		LOG_ERR("failed to configure pins");
+		return ret;
+	}
+
+	/* create the receiver thread */
+	k_thread_create(&data->rx_data_thread, (k_thread_stack_t *)data->rx_data_thread_stack,
+			SY1XX_ETH_STACK_SIZE, sy1xx_mac_rx_thread_entry, (void *)dev, NULL, NULL,
+			SY1XX_ETH_THREAD_PRIORITY, 0, K_NO_WAIT);
+
+	/* start suspended and resume once we have link */
+	k_thread_suspend(&data->rx_data_thread);
+
+	k_thread_name_set(&data->rx_data_thread, "mac-rx-thread");
+
+	return 0;
+}
+
+static int sy1xx_mac_set_promiscuous_mode(const struct device *dev, bool promiscuous_mode)
+{
+	struct sy1xx_mac_dev_config *cfg = (struct sy1xx_mac_dev_config *)dev->config;
+	uint32_t prom;
+
+	/* set promiscuous mode */
+	prom = sys_read32(cfg->ctrl_addr + SY1XX_MAC_ADDRESS_HIGH_REG);
+	if (promiscuous_mode) {
+		prom &= ~BIT(16);
+	} else {
+		prom |= BIT(16);
+	}
+	sys_write32(prom, cfg->ctrl_addr + SY1XX_MAC_ADDRESS_HIGH_REG);
+
+	return 0;
+}
+
+static int sy1xx_mac_set_mac_addr(const struct device *dev, uint8_t *mac_addr)
+{
+	struct sy1xx_mac_dev_config *cfg = (struct sy1xx_mac_dev_config *)dev->config;
+	struct sy1xx_mac_dev_data *data = (struct sy1xx_mac_dev_data *)dev->data;
+	int ret;
+	uint32_t v_low, v_high;
+
+	LOG_INF("%s set link address %02x:%02x:%02x:%02x:%02x:%02x", dev->name, mac_addr[0],
+		mac_addr[1], mac_addr[2], mac_addr[3], mac_addr[4], mac_addr[5]);
+
+	/* update mac in controller */
+	v_low = sys_get_le32(&mac_addr[0]);
+	sys_write32(v_low, cfg->ctrl_addr + SY1XX_MAC_ADDRESS_LOW_REG);
+
+	v_high = sys_read32(cfg->ctrl_addr + SY1XX_MAC_ADDRESS_HIGH_REG);
+	v_high |= (v_high & 0xffff0000) | sys_get_le16(&mac_addr[4]);
+	sys_write32(v_high, cfg->ctrl_addr + SY1XX_MAC_ADDRESS_HIGH_REG);
+
+	memcpy(data->mac_addr, mac_addr, 6);
+
+	/* Register Ethernet MAC Address with the upper layer */
+	ret = net_if_set_link_addr(data->iface, data->mac_addr, sizeof(data->mac_addr),
+				   NET_LINK_ETHERNET);
+	if (ret) {
+		LOG_ERR("%s failed to set link address", dev->name);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int sy1xx_mac_start(const struct device *dev)
+{
+	struct sy1xx_mac_dev_config *cfg = (struct sy1xx_mac_dev_config *)dev->config;
+	struct sy1xx_mac_dev_data *data = (struct sy1xx_mac_dev_data *)dev->data;
+	uint8_t rand_mac_addr[6];
+
+	extern void sy1xx_udma_disable_clock(sy1xx_udma_module_t module, uint32_t instance);
+
+	/* UDMA clock reset and enable */
+	sy1xx_udma_enable_clock(SY1XX_UDMA_MODULE_MAC, 0);
+	sy1xx_udma_disable_clock(SY1XX_UDMA_MODULE_MAC, 0);
+	sy1xx_udma_enable_clock(SY1XX_UDMA_MODULE_MAC, 0);
+
+	/* reset mac controller */
+	sys_write32(0x0001, cfg->ctrl_addr + SY1XX_MAC_CTRL_REG);
+	sys_write32(0x0000, cfg->ctrl_addr + SY1XX_MAC_CTRL_REG);
+
+	/* preset mac addr */
+	if (cfg->use_local_mac_address) {
+		/* prio 0 -- from device tree */
+		sy1xx_mac_set_mac_addr(dev, cfg->local_mac_address);
+	} else if (cfg->use_zephyr_random_mac) {
+		/* prio 1 -- generate random, if set in device tree */
+		sys_rand_get(&rand_mac_addr, 6);
+		/* Set MAC address locally administered, unicast (LAA) */
+		rand_mac_addr[0] |= 0x02;
+		sy1xx_mac_set_mac_addr(dev, rand_mac_addr);
+	} else {
+		/* no preset mac address available */
+	}
+
+	sy1xx_mac_set_promiscuous_mode(dev, cfg->promiscuous_mode);
+
+	k_thread_resume(&data->rx_data_thread);
+
+	return 0;
+}
+
+static int sy1xx_mac_stop(const struct device *dev)
+{
+	struct sy1xx_mac_dev_data *data = (struct sy1xx_mac_dev_data *)dev->data;
+
+	k_thread_suspend(&data->rx_data_thread);
+	return 0;
+}
+
+static void phy_link_state_changed(const struct device *pdev, struct phy_link_state *state,
+				   void *user_data)
+{
+	const struct device *dev = (const struct device *)user_data;
+	struct sy1xx_mac_dev_data *const data = dev->data;
+	const struct sy1xx_mac_dev_config *const cfg = dev->config;
+	bool is_up;
+	enum phy_link_speed speed;
+	uint32_t v, en;
+
+	is_up = state->is_up;
+	speed = state->speed;
+
+	if (speed != data->link_speed) {
+		data->link_speed = speed;
+
+		/* configure mac, based on provided link information 1Gbs/100MBit/... */
+		v = sys_read32(cfg->ctrl_addr + SY1XX_MAC_CTRL_REG);
+
+		/* mask out relevant bits */
+		v &= ~(BIT(SY1XX_MAC_CTRL_GMII_OFFS) | BIT(SY1XX_MAC_CTRL_CLK_SEL_OFFS) |
+		       (SY1XX_MAC_CTRL_CLK_DIV_MASK << SY1XX_MAC_CTRL_CLK_DIV_OFFS));
+
+		switch (speed) {
+		case LINK_FULL_10BASE_T:
+			LOG_INF("link speed FULL_10BASE_T");
+			/* 2.5MHz, MAC is clock source */
+			v |= (SY1XX_MAC_CTRL_CLK_SEL_MII_CLK << SY1XX_MAC_CTRL_CLK_SEL_OFFS) |
+			     (SY1XX_MAC_CTRL_CLK_DIV_10 << SY1XX_MAC_CTRL_CLK_DIV_OFFS);
+			break;
+		case LINK_FULL_100BASE_T:
+			LOG_INF("link speed FULL_100BASE_T");
+			/* 25MHz, MAC is clock source */
+			v |= (SY1XX_MAC_CTRL_CLK_SEL_MII_CLK << SY1XX_MAC_CTRL_CLK_SEL_OFFS) |
+			     (SY1XX_MAC_CTRL_CLK_DIV_1 << SY1XX_MAC_CTRL_CLK_DIV_OFFS);
+			break;
+		case LINK_FULL_1000BASE_T:
+			LOG_INF("link speed FULL_1000BASE_T");
+			/* 125MHz, Phy is clock source */
+			v |= BIT(SY1XX_MAC_CTRL_GMII_OFFS) |
+			     (SY1XX_MAC_CTRL_CLK_SEL_REF_CLK << SY1XX_MAC_CTRL_CLK_SEL_OFFS) |
+			     (SY1XX_MAC_CTRL_CLK_DIV_1 << SY1XX_MAC_CTRL_CLK_DIV_OFFS);
+			break;
+		default:
+			LOG_ERR("invalid link speed");
+			return;
+		}
+		sys_write32(v, cfg->ctrl_addr + SY1XX_MAC_CTRL_REG);
+	}
+
+	if (is_up != data->link_is_up) {
+		data->link_is_up = is_up;
+
+		if (is_up) {
+			LOG_DBG("Link up");
+
+			/* enable mac controller */
+			en = sys_read32(cfg->ctrl_addr + SY1XX_MAC_CTRL_REG);
+			en |= BIT(SY1XX_MAC_CTRL_TX_EN_OFFS) | BIT(SY1XX_MAC_CTRL_RX_EN_OFFS);
+			sys_write32(en, cfg->ctrl_addr + SY1XX_MAC_CTRL_REG);
+
+			/* Announce link up status */
+			net_eth_carrier_on(data->iface);
+
+		} else {
+			LOG_DBG("Link down");
+
+			/* disable mac controller */
+			en = sys_read32(cfg->ctrl_addr + SY1XX_MAC_CTRL_REG);
+			en &= ~(BIT(SY1XX_MAC_CTRL_TX_EN_OFFS) | BIT(SY1XX_MAC_CTRL_RX_EN_OFFS));
+			sys_write32(en, cfg->ctrl_addr + SY1XX_MAC_CTRL_REG);
+
+			/* Announce link down status */
+			net_eth_carrier_off(data->iface);
+		}
+	}
+}
+
+static void sy1xx_mac_iface_init(struct net_if *iface)
+{
+	const struct device *dev = net_if_get_device(iface);
+	struct sy1xx_mac_dev_config *cfg = (struct sy1xx_mac_dev_config *)dev->config;
+	struct sy1xx_mac_dev_data *const data = dev->data;
+
+	LOG_INF("Interface init %s (%.8x)", net_if_get_device(iface)->name, iface);
+
+	data->iface = iface;
+
+	ethernet_init(iface);
+
+	if (device_is_ready(cfg->phy_dev)) {
+		phy_link_callback_set(cfg->phy_dev, &phy_link_state_changed, (void *)dev);
+	} else {
+		LOG_ERR("PHY device not ready");
+	}
+
+	/* Do not start the interface until PHY link is up */
+	if (!(data->link_is_up)) {
+		LOG_INF("found PHY link down");
+		net_if_carrier_off(iface);
+	}
+}
+
+static enum ethernet_hw_caps sy1xx_mac_get_caps(const struct device *dev)
+{
+	enum ethernet_hw_caps supported = 0;
+
+	/* basic implemented features */
+	supported |= ETHERNET_PROMISC_MODE;
+	supported |= ETHERNET_LINK_1000BASE_T;
+	supported |= ETHERNET_PROMISC_MODE;
+
+	return supported;
+}
+
+static int sy1xx_mac_get_config(const struct device *dev, enum ethernet_config_type type,
+				struct ethernet_config *config)
+{
+	struct sy1xx_mac_dev_data *data = (struct sy1xx_mac_dev_data *)dev->data;
+
+	/* we currently support only 1000mbit/s full duplex */
+	switch (type) {
+	case ETHERNET_CONFIG_TYPE_LINK:
+		config->l.link_1000bt = true;
+		break;
+
+	case ETHERNET_CONFIG_TYPE_DUPLEX:
+		config->full_duplex = true;
+		break;
+
+	case ETHERNET_CONFIG_TYPE_MAC_ADDRESS:
+		memcpy(config->mac_address.addr, data->mac_addr, 6);
+		break;
+	default:
+		return -ENOTSUP;
+	}
+	return 0;
+}
+
+static int sy1xx_mac_set_config(const struct device *dev, enum ethernet_config_type type,
+				const struct ethernet_config *config)
+{
+	int ret = 0;
+
+	switch (type) {
+
+	case ETHERNET_CONFIG_TYPE_PROMISC_MODE:
+		ret = sy1xx_mac_set_promiscuous_mode(dev, config->promisc_mode);
+		break;
+
+	case ETHERNET_CONFIG_TYPE_MAC_ADDRESS:
+		ret = sy1xx_mac_set_mac_addr(dev, (uint8_t *)&(config->mac_address.addr));
+		break;
+	default:
+		return -ENOTSUP;
+	}
+	return ret;
+}
+
+static const struct device *sy1xx_mac_get_phy(const struct device *dev)
+{
+	const struct sy1xx_mac_dev_config *const cfg = dev->config;
+
+	return cfg->phy_dev;
+}
+
+/*
+ * rx ready status of eth is different to any other rx udma,
+ * so we implement here
+ */
+static int32_t sy1xx_mac_udma_is_finished_rx(uint32_t base)
+{
+	uint32_t isBusy = SY1XX_UDMA_READ_REG(base, SY1XX_UDMA_CFG_REG + 0x00) & (BIT(17));
+
+	return isBusy ? 0 : 1;
+}
+
+static int sy1xx_mac_low_level_send(const struct device *dev, uint8_t *tx, uint16_t len)
+{
+	struct sy1xx_mac_dev_config *cfg = (struct sy1xx_mac_dev_config *)dev->config;
+	struct sy1xx_mac_dev_data *const data = dev->data;
+
+	if (len == 0) {
+		return -EINVAL;
+	}
+
+	if (len > MAX_MAC_PACKET_LEN) {
+		return -EINVAL;
+	}
+
+	if (!SY1XX_UDMA_IS_FINISHED_TX(cfg->base_addr)) {
+		return -EBUSY;
+	}
+
+	/* udma is ready, double check if last transmission was successful */
+	if (SY1XX_UDMA_GET_REMAINING_TX(cfg->base_addr)) {
+		SY1XX_UDMA_CANCEL_TX(cfg->base_addr);
+		LOG_ERR("tx - last transmission failed");
+		return -EINVAL;
+	}
+
+	/* copy data to dma buffer */
+	for (uint32_t i = 0; i < len; i++) {
+		data->dma_buffers->tx[i] = tx[i];
+	}
+
+	/* start dma transfer */
+	SY1XX_UDMA_START_TX(cfg->base_addr, (uint32_t)data->dma_buffers->tx, len, 0);
+
+	return 0;
+}
+
+static int sy1xx_mac_low_level_receive(const struct device *dev, uint8_t *rx, uint16_t *len)
+{
+	struct sy1xx_mac_dev_config *cfg = (struct sy1xx_mac_dev_config *)dev->config;
+	struct sy1xx_mac_dev_data *const data = dev->data;
+	int ret;
+	uint32_t bytes_transferred;
+
+	*len = 0;
+
+	/* rx udma still busy */
+	if (0 == sy1xx_mac_udma_is_finished_rx(cfg->base_addr)) {
+		return -EBUSY;
+	}
+
+	/* rx udma is ready */
+	bytes_transferred = SY1XX_UDMA_READ_REG(cfg->base_addr, SY1XX_UDMA_CFG_REG) & 0x0000ffff;
+	if (bytes_transferred) {
+		/* message received, copy data */
+		memcpy(rx, data->dma_buffers->rx, bytes_transferred);
+		*len = bytes_transferred;
+		ret = 0;
+	} else {
+		/* no data, should never happen */
+		SY1XX_UDMA_CANCEL_RX(cfg->base_addr);
+		ret = -EINVAL;
+	}
+
+	/* start new reception */
+	SY1XX_UDMA_START_RX(cfg->base_addr, (uint32_t)data->dma_buffers->rx, MAX_MAC_PACKET_LEN, 0);
+
+	return ret;
+}
+
+static int sy1xx_mac_send(const struct device *dev, struct net_pkt *pkt)
+{
+	struct sy1xx_mac_dev_data *const data = dev->data;
+	int ret;
+	uint32_t retries_left;
+	struct net_buf *frag;
+
+	k_mutex_lock(&data->mutex, K_FOREVER);
+
+	/* push all fragments of the packet into one linear buffer */
+	frag = pkt->buffer;
+	data->temp.tx_len = 0;
+	do {
+		/* copy fragment to buffer */
+		for (uint32_t i = 0; i < frag->len; i++) {
+			if (data->temp.tx_len < MAX_MAC_PACKET_LEN) {
+				data->temp.tx[data->temp.tx_len++] = frag->data[i];
+			} else {
+				LOG_ERR("tx buffer overflow");
+				k_mutex_unlock(&data->mutex);
+				return -ENOMEM;
+			}
+		}
+
+		frag = frag->frags;
+	} while (frag);
+
+	/* hand over linear tx frame to udma */
+	retries_left = MAX_TX_RETRIES;
+	while (retries_left) {
+		ret = sy1xx_mac_low_level_send(dev, data->temp.tx, data->temp.tx_len);
+		if (ret == 0) {
+			break;
+		}
+		if (ret != -EBUSY) {
+			LOG_ERR("tx error");
+			k_mutex_unlock(&data->mutex);
+			return ret;
+		}
+		k_sleep(K_MSEC(1));
+		retries_left--;
+	};
+
+	k_mutex_unlock(&data->mutex);
+	return ret;
+}
+
+static int sy1xx_mac_receive_data(const struct device *dev, uint8_t *rx, uint16_t len)
+{
+	struct sy1xx_mac_dev_data *const data = dev->data;
+	struct net_pkt *rx_pkt;
+	int ret;
+
+	rx_pkt = net_pkt_alloc_with_buffer(data->iface, len, AF_UNSPEC, 0, K_FOREVER);
+	if (rx_pkt == NULL) {
+		LOG_ERR("rx packet allocation failed");
+		return -EINVAL;
+	}
+
+	/* add data to the net_pkt */
+	if (net_pkt_write(rx_pkt, rx, len)) {
+		LOG_ERR("failed to write data to net_pkt");
+		net_pkt_unref(rx_pkt);
+		return -EINVAL;
+	}
+
+	/* register new packet in stack */
+	ret = net_recv_data(data->iface, rx_pkt);
+	if (ret) {
+		LOG_ERR("rx packet registration failed");
+		return ret;
+	}
+
+	return 0;
+}
+
+static void sy1xx_mac_rx_thread_entry(void *p1, void *p2, void *p3)
+{
+	const struct device *dev = p1;
+	struct sy1xx_mac_dev_data *const data = dev->data;
+	int ret;
+
+	while (true) {
+		ret = sy1xx_mac_low_level_receive(dev, data->temp.rx, &data->temp.rx_len);
+		if (ret == 0) {
+			/* register a new received frame */
+			if (data->temp.rx_len) {
+				sy1xx_mac_receive_data(dev, data->temp.rx, data->temp.rx_len);
+			}
+		} else {
+			/*
+			 * rx thread is running at higher prio, in case of error or busy,
+			 * we could lock up the system partially.
+			 */
+
+			/* we wait and try again */
+			k_sleep(K_MSEC(RECEIVE_GRACE_TIME_MSEC));
+		}
+	}
+}
+
+const struct ethernet_api sy1xx_mac_driver_api = {
+	.start = sy1xx_mac_start,
+	.stop = sy1xx_mac_stop,
+	.iface_api.init = sy1xx_mac_iface_init,
+	.get_capabilities = sy1xx_mac_get_caps,
+	.get_config = sy1xx_mac_get_config,
+	.set_config = sy1xx_mac_set_config,
+	.send = sy1xx_mac_send,
+	.get_phy = sy1xx_mac_get_phy,
+};
+
+#define SY1XX_MAC_INIT(n)                                                                          \
+                                                                                                   \
+	PINCTRL_DT_INST_DEFINE(n);                                                                 \
+                                                                                                   \
+	static const struct sy1xx_mac_dev_config sy1xx_mac_dev_config_##n = {                      \
+		.ctrl_addr = DT_INST_REG_ADDR_BY_NAME(n, ctrl),                                    \
+		.base_addr = DT_INST_REG_ADDR_BY_NAME(n, data),                                    \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                         \
+		.promiscuous_mode = DT_INST_PROP_OR(n, promiscuous_mode, false),                   \
+		.local_mac_address = DT_INST_PROP_OR(n, local_mac_address, {0}),                   \
+		.use_local_mac_address = DT_INST_NODE_HAS_PROP(n, local_mac_address),              \
+		.use_zephyr_random_mac = DT_INST_NODE_HAS_PROP(n, zephyr_random_mac_address),      \
+		.phy_dev = DEVICE_DT_GET(DT_INST_PHANDLE(0, phy_handle))};                         \
+                                                                                                   \
+	static struct sy1xx_mac_dma_buffers __attribute__((section(".udma_access")))               \
+	__aligned(4) sy1xx_mac_dma_buffers_##n;                                                    \
+                                                                                                   \
+	static struct sy1xx_mac_dev_data sy1xx_mac_dev_data##n = {                                 \
+		.dma_buffers = &sy1xx_mac_dma_buffers_##n,                                         \
+	};                                                                                         \
+                                                                                                   \
+	ETH_NET_DEVICE_DT_INST_DEFINE(n, &sy1xx_mac_initialize, NULL, &sy1xx_mac_dev_data##n,      \
+				      &sy1xx_mac_dev_config_##n, CONFIG_ETH_INIT_PRIORITY,         \
+				      &sy1xx_mac_driver_api, NET_ETH_MTU);
+
+DT_INST_FOREACH_STATUS_OKAY(SY1XX_MAC_INIT)
diff --git a/drivers/ethernet/eth_stm32_hal.c b/drivers/ethernet/eth_stm32_hal.c
index ec46339e8ef..0b7286b663e 100644
--- a/drivers/ethernet/eth_stm32_hal.c
+++ b/drivers/ethernet/eth_stm32_hal.c
@@ -34,7 +34,7 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
 #include <zephyr/net/lldp.h>
 #include <zephyr/drivers/hwinfo.h>
 
-#if defined(CONFIG_NET_DSA)
+#if defined(CONFIG_NET_DSA_DEPRECATED)
 #include <zephyr/net/dsa.h>
 #endif
 
@@ -54,31 +54,18 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
 #error DTCM for DMA buffer is activated but zephyr,dtcm is not present in dts
 #endif
 
-#define PHY_ADDR	CONFIG_ETH_STM32_HAL_PHY_ADDRESS
+static const struct device *eth_stm32_phy_dev = DEVICE_DT_GET(DT_INST_PHANDLE(0, phy_handle));
 
-#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_mdio)
-
-#define DEVICE_PHY_BY_NAME(n) \
-	    DEVICE_DT_GET(DT_CHILD(DT_INST_CHILD(n, mdio), _CONCAT(ethernet_phy_, PHY_ADDR)))
-
-static const struct device *eth_stm32_phy_dev = DEVICE_PHY_BY_NAME(0);
-
-#endif
+#define ETH_STM32_AUTO_NEGOTIATION_ENABLE                                                          \
+	UTIL_NOT(DT_NODE_HAS_PROP(DT_INST_PHANDLE(0, phy_handle), fixed_link))
 
 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
-
-#define PHY_BSR  ((uint16_t)0x0001U)  /*!< Transceiver Basic Status Register */
-#define PHY_LINKED_STATUS  ((uint16_t)0x0004U)  /*!< Valid link established */
-
 #define IS_ETH_DMATXDESC_OWN(dma_tx_desc)	(dma_tx_desc->DESC3 & \
 							ETH_DMATXNDESCRF_OWN)
 
 #define ETH_RXBUFNB	ETH_RX_DESC_CNT
 #define ETH_TXBUFNB	ETH_TX_DESC_CNT
 
-#define ETH_MEDIA_INTERFACE_MII		HAL_ETH_MII_MODE
-#define ETH_MEDIA_INTERFACE_RMII	HAL_ETH_RMII_MODE
-
 /* Only one tx_buffer is sufficient to pass only 1 dma_buffer */
 #define ETH_TXBUF_DEF_NB	1U
 #else
@@ -88,6 +75,33 @@ static const struct device *eth_stm32_phy_dev = DEVICE_PHY_BY_NAME(0);
 
 #endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
 
+#if defined(CONFIG_ETH_STM32_HAL_API_V2)
+#define ETH_MII_MODE	HAL_ETH_MII_MODE
+#define ETH_RMII_MODE	HAL_ETH_RMII_MODE
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
+#define ETH_GMII_MODE	HAL_ETH_GMII_MODE
+#define ETH_RGMII_MODE	HAL_ETH_RGMII_MODE
+#endif
+
+#else
+#define ETH_MII_MODE	ETH_MEDIA_INTERFACE_MII
+#define ETH_RMII_MODE	ETH_MEDIA_INTERFACE_RMII
+#endif
+
+#define MAC_NODE DT_NODELABEL(mac)
+
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
+#define STM32_ETH_PHY_MODE(node_id) \
+	((DT_ENUM_HAS_VALUE(node_id, phy_connection_type, rgmii) ? ETH_RGMII_MODE : \
+	 (DT_ENUM_HAS_VALUE(node_id, phy_connection_type, gmii) ? ETH_GMII_MODE : \
+	 (DT_ENUM_HAS_VALUE(node_id, phy_connection_type, mii) ? ETH_MII_MODE : \
+		 ETH_RMII_MODE))))
+#else
+#define STM32_ETH_PHY_MODE(node_id) \
+	(DT_ENUM_HAS_VALUE(node_id, phy_connection_type, mii) ? \
+		ETH_MII_MODE : ETH_RMII_MODE)
+#endif
+
 #define ETH_DMA_TX_TIMEOUT_MS	20U  /* transmit timeout in milliseconds */
 
 #if defined(CONFIG_ETH_STM32_HAL_USE_DTCM_FOR_DMA_BUFFER) && \
@@ -105,8 +119,16 @@ static const struct device *eth_stm32_phy_dev = DEVICE_PHY_BY_NAME(0);
 #define __eth_stm32_buf  __aligned(4)
 #endif
 
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
+static ETH_DMADescTypeDef
+	dma_rx_desc_tab[ETH_DMA_RX_CH_CNT][ETH_RXBUFNB] ALIGN_32BYTES(__eth_stm32_desc);
+static ETH_DMADescTypeDef
+	dma_tx_desc_tab[ETH_DMA_TX_CH_CNT][ETH_TXBUFNB] ALIGN_32BYTES(__eth_stm32_desc);
+#else
 static ETH_DMADescTypeDef dma_rx_desc_tab[ETH_RXBUFNB] __eth_stm32_desc;
 static ETH_DMADescTypeDef dma_tx_desc_tab[ETH_TXBUFNB] __eth_stm32_desc;
+#endif
+
 static uint8_t dma_rx_buffer[ETH_RXBUFNB][ETH_STM32_RX_BUF_SIZE] __eth_stm32_buf;
 static uint8_t dma_tx_buffer[ETH_TXBUFNB][ETH_STM32_TX_BUF_SIZE] __eth_stm32_buf;
 
@@ -234,21 +256,6 @@ static inline struct eth_stm32_tx_context *allocate_tx_context(struct net_pkt *p
 static ETH_TxPacketConfig tx_config;
 #endif
 
-static HAL_StatusTypeDef read_eth_phy_register(ETH_HandleTypeDef *heth,
-						uint32_t PHYAddr,
-						uint32_t PHYReg,
-						uint32_t *RegVal)
-{
-#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_mdio)
-	return phy_read(eth_stm32_phy_dev, PHYReg, RegVal);
-#elif defined(CONFIG_ETH_STM32_HAL_API_V2)
-	return HAL_ETH_ReadPHYRegister(heth, PHYAddr, PHYReg, RegVal);
-#else
-	ARG_UNUSED(PHYAddr);
-	return HAL_ETH_ReadPHYRegister(heth, PHYReg, RegVal);
-#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
-}
-
 static inline void setup_mac_filter(ETH_HandleTypeDef *heth)
 {
 	__ASSERT_NO_MSG(heth != NULL);
@@ -308,7 +315,7 @@ static bool eth_is_ptp_pkt(struct net_if *iface, struct net_pkt *pkt)
 
 	return true;
 }
-#if defined(CONFIG_ETH_STM32_HAL_API_V2)
+
 void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp)
 {
 	struct eth_stm32_tx_context *ctx = (struct eth_stm32_tx_context *)buff;
@@ -318,7 +325,6 @@ void HAL_ETH_TxPtpCallback(uint32_t *buff, ETH_TimeStampTypeDef *timestamp)
 
 	net_if_add_tx_timestamp(ctx->pkt);
 }
-#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
 #endif /* CONFIG_PTP_CLOCK_STM32_HAL */
 
 static int eth_tx(const struct device *dev, struct net_pkt *pkt)
@@ -370,11 +376,7 @@ static int eth_tx(const struct device *dev, struct net_pkt *pkt)
 			    net_pkt_is_tx_timestamping(pkt);
 	if (timestamped_frame) {
 		/* Enable transmit timestamp */
-#if defined(CONFIG_ETH_STM32_HAL_API_V2)
 		HAL_ETH_PTP_InsertTxTimestamp(heth);
-#else
-		dma_tx_desc->Status |= ETH_DMATXDESC_TTSE;
-#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
 	}
 #endif /* CONFIG_PTP_CLOCK_STM32_HAL */
 
@@ -495,35 +497,6 @@ static int eth_tx(const struct device *dev, struct net_pkt *pkt)
 	}
 #endif /* CONFIG_ETH_STM32_HAL_API_V2 */
 
-#if defined(CONFIG_PTP_CLOCK_STM32_HAL) && !defined(CONFIG_ETH_STM32_HAL_API_V2)
-	if (timestamped_frame) {
-		/* Retrieve transmission timestamp from last DMA TX descriptor */
-		__IO ETH_DMADescTypeDef *last_dma_tx_desc = dma_tx_desc;
-
-		while (!(last_dma_tx_desc->Status & ETH_DMATXDESC_LS) &&
-				last_dma_tx_desc->Buffer2NextDescAddr) {
-			last_dma_tx_desc =
-				(ETH_DMADescTypeDef *)last_dma_tx_desc->Buffer2NextDescAddr;
-		}
-
-		while (IS_ETH_DMATXDESC_OWN(last_dma_tx_desc) != (uint32_t)RESET) {
-			/* Wait for transmission */
-			k_yield();
-		}
-
-		if (last_dma_tx_desc->Status & ETH_DMATXDESC_LS &&
-				last_dma_tx_desc->Status & ETH_DMATXDESC_TTSS) {
-			pkt->timestamp.second = last_dma_tx_desc->TimeStampHigh;
-			pkt->timestamp.nanosecond = last_dma_tx_desc->TimeStampLow;
-		} else {
-			/* Invalid value */
-			pkt->timestamp.second = UINT64_MAX;
-			pkt->timestamp.nanosecond = UINT32_MAX;
-		}
-		net_if_add_tx_timestamp(pkt);
-	}
-#endif /* CONFIG_PTP_CLOCK_STM32_HAL && !CONFIG_ETH_STM32_HAL_API_V2 */
-
 	res = 0;
 error:
 
@@ -563,9 +536,7 @@ static struct net_pkt *eth_rx(const struct device *dev)
 #endif /* CONFIG_ETH_STM32_HAL_API_V2 */
 #if defined(CONFIG_PTP_CLOCK_STM32_HAL)
 	struct net_ptp_time timestamp;
-#if defined(CONFIG_ETH_STM32_HAL_API_V2)
 	ETH_TimeStampTypeDef ts_registers;
-#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
 	/* Default to invalid value. */
 	timestamp.second = UINT64_MAX;
 	timestamp.nanosecond = UINT32_MAX;
@@ -602,22 +573,10 @@ static struct net_pkt *eth_rx(const struct device *dev)
 #endif /* CONFIG_ETH_STM32_HAL_API_V2 */
 
 #if defined(CONFIG_PTP_CLOCK_STM32_HAL)
-#if defined(CONFIG_ETH_STM32_HAL_API_V2)
-
 	if (HAL_ETH_PTP_GetRxTimestamp(heth, &ts_registers) == HAL_OK) {
 		timestamp.second = ts_registers.TimeStampHigh;
 		timestamp.nanosecond = ts_registers.TimeStampLow;
 	}
-#else
-	__IO ETH_DMADescTypeDef *last_dma_rx_desc;
-
-	last_dma_rx_desc = heth->RxFrameInfos.LSRxDesc;
-	if (last_dma_rx_desc->TimeStampHigh != UINT32_MAX ||
-			last_dma_rx_desc->TimeStampLow != UINT32_MAX) {
-		timestamp.second = last_dma_rx_desc->TimeStampHigh;
-		timestamp.nanosecond = last_dma_rx_desc->TimeStampLow;
-	}
-#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
 #endif /* CONFIG_PTP_CLOCK_STM32_HAL */
 
 	pkt = net_pkt_rx_alloc_with_buffer(get_iface(dev_data),
@@ -707,8 +666,6 @@ static void rx_thread(void *arg1, void *unused1, void *unused2)
 	struct net_if *iface;
 	struct net_pkt *pkt;
 	int res;
-	uint32_t status;
-	HAL_StatusTypeDef hal_ret = HAL_OK;
 
 	__ASSERT_NO_MSG(arg1 != NULL);
 	ARG_UNUSED(unused1);
@@ -720,17 +677,12 @@ static void rx_thread(void *arg1, void *unused1, void *unused2)
 	__ASSERT_NO_MSG(dev_data != NULL);
 
 	while (1) {
-		res = k_sem_take(&dev_data->rx_int_sem,
-			K_MSEC(CONFIG_ETH_STM32_CARRIER_CHECK_RX_IDLE_TIMEOUT_MS));
+		res = k_sem_take(&dev_data->rx_int_sem, K_FOREVER);
 		if (res == 0) {
-			/* semaphore taken, update link status and receive packets */
-			if (dev_data->link_up != true) {
-				dev_data->link_up = true;
-				net_eth_carrier_on(get_iface(dev_data));
-			}
+			/* semaphore taken and receive packets */
 			while ((pkt = eth_rx(dev)) != NULL) {
 				iface = net_pkt_iface(pkt);
-#if defined(CONFIG_NET_DSA)
+#if defined(CONFIG_NET_DSA_DEPRECATED)
 				iface = dsa_net_recv(iface, &pkt);
 #endif
 				res = net_recv_data(iface, pkt);
@@ -742,25 +694,6 @@ static void rx_thread(void *arg1, void *unused1, void *unused2)
 					net_pkt_unref(pkt);
 				}
 			}
-		} else if (res == -EAGAIN) {
-			/* semaphore timeout period expired, check link status */
-			hal_ret = read_eth_phy_register(&dev_data->heth,
-				    PHY_ADDR, PHY_BSR, (uint32_t *) &status);
-			if (hal_ret == HAL_OK) {
-				if ((status & PHY_LINKED_STATUS) == PHY_LINKED_STATUS) {
-					if (dev_data->link_up != true) {
-						dev_data->link_up = true;
-						net_eth_carrier_on(
-							get_iface(dev_data));
-					}
-				} else {
-					if (dev_data->link_up != false) {
-						dev_data->link_up = false;
-						net_eth_carrier_off(
-							get_iface(dev_data));
-					}
-				}
-			}
 		}
 	}
 }
@@ -816,7 +749,12 @@ void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
 		CONTAINER_OF(heth, struct eth_stm32_hal_dev_data, heth);
 
 	switch (error_code) {
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
+	case HAL_ETH_ERROR_DMA_CH0:
+	case HAL_ETH_ERROR_DMA_CH1:
+#else
 	case HAL_ETH_ERROR_DMA:
+#endif
 		dma_error = HAL_ETH_GetDMAError(heth);
 
 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
@@ -913,12 +851,37 @@ static void generate_mac(uint8_t *mac_addr)
 #endif
 }
 
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
+/**
+ * Configures the RISAF (RIF Security Attribute Framework) for Ethernet on STM32N6.
+ * This function sets up the master and slave security attributes for the Ethernet peripheral.
+ */
+
+static void RISAF_Config(void)
+{
+	/* Define and initialize the master configuration structure */
+	RIMC_MasterConfig_t RIMC_master = {0};
+
+	/* Enable the clock for the RIFSC (RIF Security Controller) */
+	__HAL_RCC_RIFSC_CLK_ENABLE();
+
+	RIMC_master.MasterCID = RIF_CID_1;
+	RIMC_master.SecPriv = RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV;
+
+	/* Configure the master attributes for the Ethernet peripheral (ETH1) */
+	HAL_RIF_RIMC_ConfigMasterAttributes(RIF_MASTER_INDEX_ETH1, &RIMC_master);
+
+	/* Set the secure and privileged attributes for the Ethernet peripheral (ETH1) as a slave */
+	HAL_RIF_RISC_SetSlaveSecureAttributes(RIF_RISC_PERIPH_INDEX_ETH1,
+					      RIF_ATTRIBUTE_SEC | RIF_ATTRIBUTE_PRIV);
+}
+#endif
+
 static int eth_initialize(const struct device *dev)
 {
 	struct eth_stm32_hal_dev_data *dev_data;
 	const struct eth_stm32_hal_dev_cfg *cfg;
 	ETH_HandleTypeDef *heth;
-	HAL_StatusTypeDef hal_ret = HAL_OK;
 	int ret = 0;
 
 	__ASSERT_NO_MSG(dev != NULL);
@@ -936,6 +899,11 @@ static int eth_initialize(const struct device *dev)
 		return -ENODEV;
 	}
 
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
+	/* RISAF Configuration */
+	RISAF_Config();
+#endif
+
 	/* enable clock */
 	ret = clock_control_on(dev_data->clock,
 		(clock_control_subsys_t)&cfg->pclken);
@@ -966,95 +934,41 @@ static int eth_initialize(const struct device *dev)
 
 	heth->Init.MACAddr = dev_data->mac_addr;
 
-#if defined(CONFIG_ETH_STM32_HAL_API_V2)
-	heth->Init.TxDesc = dma_tx_desc_tab;
-	heth->Init.RxDesc = dma_rx_desc_tab;
-	heth->Init.RxBuffLen = ETH_STM32_RX_BUF_SIZE;
-#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
+#if defined(CONFIG_ETH_STM32_HAL_API_V1)
+	HAL_StatusTypeDef hal_ret = HAL_OK;
+
+	if (!ETH_STM32_AUTO_NEGOTIATION_ENABLE) {
+		struct phy_link_state state;
+
+		phy_get_link_state(eth_stm32_phy_dev, &state);
+
+		heth->Init.DuplexMode = PHY_LINK_IS_FULL_DUPLEX(state.speed) ? ETH_MODE_FULLDUPLEX
+									     : ETH_MODE_HALFDUPLEX;
+		heth->Init.Speed =
+			PHY_LINK_IS_SPEED_100M(state.speed) ? ETH_SPEED_100M : ETH_SPEED_10M;
+	}
 
 	hal_ret = HAL_ETH_Init(heth);
 	if (hal_ret == HAL_TIMEOUT) {
 		/* HAL Init time out. This could be linked to */
 		/* a recoverable error. Log the issue and continue */
 		/* driver initialisation */
-		LOG_ERR("HAL_ETH_Init Timed out");
+		LOG_WRN("HAL_ETH_Init timed out (cable not connected?)");
 	} else if (hal_ret != HAL_OK) {
 		LOG_ERR("HAL_ETH_Init failed: %d", hal_ret);
 		return -EINVAL;
 	}
 
-#if defined(CONFIG_PTP_CLOCK_STM32_HAL)
-	/* Enable timestamping of RX packets. We enable all packets to be
-	 * timestamped to cover both IEEE 1588 and gPTP.
-	 */
-#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
-	heth->Instance->MACTSCR |= ETH_MACTSCR_TSENALL;
-#else
-	heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSSARFE;
-#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
-#endif /* CONFIG_PTP_CLOCK_STM32_HAL */
-
-#if defined(CONFIG_ETH_STM32_HAL_API_V2)
-	/* Tx config init: */
-	memset(&tx_config, 0, sizeof(ETH_TxPacketConfig));
-	tx_config.Attributes = ETH_TX_PACKETS_FEATURES_CSUM |
-				ETH_TX_PACKETS_FEATURES_CRCPAD;
-	tx_config.ChecksumCtrl = IS_ENABLED(CONFIG_ETH_STM32_HW_CHECKSUM) ?
-			ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC : ETH_CHECKSUM_DISABLE;
-	tx_config.CRCPadCtrl = ETH_CRC_PAD_INSERT;
-#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
-
-	dev_data->link_up = false;
-
 	/* Initialize semaphores */
 	k_mutex_init(&dev_data->tx_mutex);
 	k_sem_init(&dev_data->rx_int_sem, 0, K_SEM_MAX_LIMIT);
-#if defined(CONFIG_ETH_STM32_HAL_API_V2)
-	k_sem_init(&dev_data->tx_int_sem, 0, K_SEM_MAX_LIMIT);
-#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
 
-#if defined(CONFIG_ETH_STM32_HAL_API_V2)
-	/* Adjust MDC clock range depending on HCLK frequency: */
-	HAL_ETH_SetMDIOClockRange(heth);
-
-	/* @TODO: read duplex mode and speed from PHY and set it to ETH */
-
-	ETH_MACConfigTypeDef mac_config;
-
-	HAL_ETH_GetMACConfig(heth, &mac_config);
-	mac_config.DuplexMode = IS_ENABLED(CONFIG_ETH_STM32_MODE_HALFDUPLEX) ?
-				      ETH_HALFDUPLEX_MODE : ETH_FULLDUPLEX_MODE;
-	mac_config.Speed = IS_ENABLED(CONFIG_ETH_STM32_SPEED_10M) ?
-				 ETH_SPEED_10M : ETH_SPEED_100M;
-	hal_ret = HAL_ETH_SetMACConfig(heth, &mac_config);
-	if (hal_ret != HAL_OK) {
-		LOG_ERR("HAL_ETH_SetMACConfig: failed: %d", hal_ret);
-	}
-#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
-
-#if defined(CONFIG_ETH_STM32_HAL_API_V2)
-
-	/* prepare tx buffer header */
-	for (uint16_t i = 0; i < ETH_TXBUFNB; ++i) {
-		dma_tx_buffer_header[i].tx_buff.buffer = dma_tx_buffer[i];
-	}
-
-	hal_ret = HAL_ETH_Start_IT(heth);
-#else
 	HAL_ETH_DMATxDescListInit(heth, dma_tx_desc_tab,
 		&dma_tx_buffer[0][0], ETH_TXBUFNB);
 	HAL_ETH_DMARxDescListInit(heth, dma_rx_desc_tab,
 		&dma_rx_buffer[0][0], ETH_RXBUFNB);
 
-	hal_ret = HAL_ETH_Start(heth);
-#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
-
-	if (hal_ret != HAL_OK) {
-		LOG_ERR("HAL_ETH_Start{_IT} failed");
-	}
-
-	setup_mac_filter(heth);
-
+#endif /* !CONFIG_ETH_STM32_HAL_API_V1 */
 
 	LOG_DBG("MAC %02x:%02x:%02x:%02x:%02x:%02x",
 		dev_data->mac_addr[0], dev_data->mac_addr[1],
@@ -1114,11 +1028,171 @@ static void eth_stm32_mcast_filter(const struct device *dev, const struct ethern
 
 #endif /* CONFIG_ETH_STM32_MULTICAST_FILTER */
 
+#if defined(CONFIG_ETH_STM32_HAL_API_V2)
+static int eth_init_api_v2(const struct device *dev)
+{
+	HAL_StatusTypeDef hal_ret = HAL_OK;
+	struct eth_stm32_hal_dev_data *dev_data;
+	ETH_HandleTypeDef *heth;
+
+	dev_data = dev->data;
+	heth = &dev_data->heth;
+
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet)
+	for (int ch = 0; ch < ETH_DMA_CH_CNT; ch++) {
+		heth->Init.TxDesc[ch] = dma_tx_desc_tab[ch];
+		heth->Init.RxDesc[ch] = dma_rx_desc_tab[ch];
+	}
+#else
+	heth->Init.TxDesc = dma_tx_desc_tab;
+	heth->Init.RxDesc = dma_rx_desc_tab;
+#endif
+	heth->Init.RxBuffLen = ETH_STM32_RX_BUF_SIZE;
+
+	hal_ret = HAL_ETH_Init(heth);
+	if (hal_ret == HAL_TIMEOUT) {
+		/* HAL Init time out. This could be linked to */
+		/* a recoverable error. Log the issue and continue */
+		/* driver initialisation */
+		LOG_ERR("HAL_ETH_Init Timed out");
+	} else if (hal_ret != HAL_OK) {
+		LOG_ERR("HAL_ETH_Init failed: %d", hal_ret);
+		return -EINVAL;
+	}
+
+#if defined(CONFIG_PTP_CLOCK_STM32_HAL)
+	/* Enable timestamping of RX packets. We enable all packets to be
+	 * timestamped to cover both IEEE 1588 and gPTP.
+	 */
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
+	heth->Instance->MACTSCR |= ETH_MACTSCR_TSENALL;
+#else
+	heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSSARFE;
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
+#endif /* CONFIG_PTP_CLOCK_STM32_HAL */
+
+	/* Initialize semaphores */
+	k_mutex_init(&dev_data->tx_mutex);
+	k_sem_init(&dev_data->rx_int_sem, 0, K_SEM_MAX_LIMIT);
+	k_sem_init(&dev_data->tx_int_sem, 0, K_SEM_MAX_LIMIT);
+
+	/* Tx config init: */
+	memset(&tx_config, 0, sizeof(ETH_TxPacketConfig));
+	tx_config.Attributes = ETH_TX_PACKETS_FEATURES_CSUM |
+				ETH_TX_PACKETS_FEATURES_CRCPAD;
+	tx_config.ChecksumCtrl = IS_ENABLED(CONFIG_ETH_STM32_HW_CHECKSUM) ?
+			ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC : ETH_CHECKSUM_DISABLE;
+	tx_config.CRCPadCtrl = ETH_CRC_PAD_INSERT;
+
+	/* prepare tx buffer header */
+	for (uint16_t i = 0; i < ETH_TXBUFNB; ++i) {
+		dma_tx_buffer_header[i].tx_buff.buffer = dma_tx_buffer[i];
+	}
+
+	return 0;
+}
+#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
+
+static void set_mac_config(const struct device *dev, struct phy_link_state *state)
+{
+	struct eth_stm32_hal_dev_data *dev_data = dev->data;
+	ETH_HandleTypeDef *heth = &dev_data->heth;
+	HAL_StatusTypeDef hal_ret = HAL_OK;
+#if defined(CONFIG_ETH_STM32_HAL_API_V2)
+	ETH_MACConfigTypeDef mac_config = {0};
+
+	HAL_ETH_GetMACConfig(heth, &mac_config);
+
+	mac_config.DuplexMode =
+		PHY_LINK_IS_FULL_DUPLEX(state->speed) ? ETH_FULLDUPLEX_MODE : ETH_HALFDUPLEX_MODE;
+
+	mac_config.Speed =
+		IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet),
+			PHY_LINK_IS_SPEED_1000M(state->speed) ? ETH_SPEED_1000M :)
+		PHY_LINK_IS_SPEED_100M(state->speed) ? ETH_SPEED_100M : ETH_SPEED_10M;
+
+	hal_ret = HAL_ETH_SetMACConfig(heth, &mac_config);
+	if (hal_ret != HAL_OK) {
+		LOG_ERR("HAL_ETH_SetMACConfig: failed: %d", hal_ret);
+	}
+#else  /* CONFIG_ETH_STM32_HAL_API_V2 */
+	heth->Init.DuplexMode =
+		PHY_LINK_IS_FULL_DUPLEX(state->speed) ? ETH_MODE_FULLDUPLEX : ETH_MODE_HALFDUPLEX;
+
+	heth->Init.Speed = PHY_LINK_IS_SPEED_100M(state->speed) ? ETH_SPEED_100M : ETH_SPEED_10M;
+
+	hal_ret = HAL_ETH_ConfigMAC(heth, NULL);
+	if (hal_ret != HAL_OK) {
+		LOG_ERR("HAL_ETH_ConfigMAC: failed: %d", hal_ret);
+	}
+#endif /* CONFIG_ETH_STM32_HAL_API_V2 */
+}
+
+static int eth_stm32_hal_start(const struct device *dev)
+{
+	struct eth_stm32_hal_dev_data *dev_data = dev->data;
+	ETH_HandleTypeDef *heth = &dev_data->heth;
+	HAL_StatusTypeDef hal_ret = HAL_OK;
+
+	LOG_DBG("Starting ETH HAL driver");
+
+#if defined(CONFIG_ETH_STM32_HAL_API_V2)
+	hal_ret = HAL_ETH_Start_IT(heth);
+#else
+	hal_ret = HAL_ETH_Start(heth);
+#endif
+	if (hal_ret != HAL_OK) {
+		LOG_ERR("HAL_ETH_Start{_IT} failed");
+	}
+
+	return 0;
+}
+
+static int eth_stm32_hal_stop(const struct device *dev)
+{
+	struct eth_stm32_hal_dev_data *dev_data = dev->data;
+	ETH_HandleTypeDef *heth = &dev_data->heth;
+	HAL_StatusTypeDef hal_ret = HAL_OK;
+
+	LOG_DBG("Stopping ETH HAL driver");
+
+#if defined(CONFIG_ETH_STM32_HAL_API_V2)
+	hal_ret = HAL_ETH_Stop_IT(heth);
+#else
+	hal_ret = HAL_ETH_Stop(heth);
+#endif
+	if (hal_ret != HAL_OK) {
+		/* HAL_ETH_Stop{_IT} returns HAL_ERROR only if ETH is already stopped */
+		LOG_DBG("HAL_ETH_Stop{_IT} returned error (Ethernet is already stopped)");
+	}
+
+	return 0;
+}
+
+static void phy_link_state_changed(const struct device *phy_dev, struct phy_link_state *state,
+				   void *user_data)
+{
+	const struct device *dev = (const struct device *)user_data;
+	struct eth_stm32_hal_dev_data *dev_data = dev->data;
+
+	ARG_UNUSED(phy_dev);
+
+	if (state->is_up) {
+		set_mac_config(dev, state);
+		eth_stm32_hal_start(dev);
+		net_eth_carrier_on(dev_data->iface);
+	} else {
+		eth_stm32_hal_stop(dev);
+		net_eth_carrier_off(dev_data->iface);
+	}
+}
+
 static void eth_iface_init(struct net_if *iface)
 {
 	const struct device *dev;
 	struct eth_stm32_hal_dev_data *dev_data;
 	bool is_first_init = false;
+	ETH_HandleTypeDef *heth;
 
 	__ASSERT_NO_MSG(iface != NULL);
 
@@ -1128,6 +1202,9 @@ static void eth_iface_init(struct net_if *iface)
 	dev_data = dev->data;
 	__ASSERT_NO_MSG(dev_data != NULL);
 
+	heth = &dev_data->heth;
+	__ASSERT_NO_MSG(heth != NULL);
+
 	if (dev_data->iface == NULL) {
 		dev_data->iface = iface;
 		is_first_init = true;
@@ -1138,16 +1215,32 @@ static void eth_iface_init(struct net_if *iface)
 			     sizeof(dev_data->mac_addr),
 			     NET_LINK_ETHERNET);
 
-#if defined(CONFIG_NET_DSA)
+#if defined(CONFIG_NET_DSA_DEPRECATED)
 	dsa_register_master_tx(iface, &eth_tx);
 #endif
 
 	ethernet_init(iface);
 
+#if defined(CONFIG_ETH_STM32_HAL_API_V2)
+	/* This function requires the Ethernet interface to be
+	 * properly initialized. In auto-negotiation mode, it reads the speed
+	 * and duplex settings to configure the driver accordingly.
+	 */
+	eth_init_api_v2(dev);
+#endif
+
+	setup_mac_filter(heth);
+
 	net_if_carrier_off(iface);
 
 	net_lldp_set_lldpdu(iface);
 
+	if (device_is_ready(eth_stm32_phy_dev)) {
+		phy_link_callback_set(eth_stm32_phy_dev, phy_link_state_changed, (void *)dev);
+	} else {
+		LOG_ERR("PHY device not ready");
+	}
+
 	if (is_first_init) {
 		const struct eth_stm32_hal_dev_cfg *cfg = dev->config;
 		/* Now that the iface is setup, we are safe to enable IRQs. */
@@ -1158,7 +1251,7 @@ static void eth_iface_init(struct net_if *iface)
 		k_thread_create(&dev_data->rx_thread, dev_data->rx_thread_stack,
 				K_KERNEL_STACK_SIZEOF(dev_data->rx_thread_stack),
 				rx_thread, (void *) dev, NULL, NULL,
-				IS_ENABLED(CONFIG_NET_TC_THREAD_PREEMPTIVE)
+				IS_ENABLED(CONFIG_ETH_STM32_HAL_RX_THREAD_PREEMPTIVE)
 					? K_PRIO_PREEMPT(CONFIG_ETH_STM32_HAL_RX_THREAD_PRIO)
 					: K_PRIO_COOP(CONFIG_ETH_STM32_HAL_RX_THREAD_PRIO),
 				0, K_NO_WAIT);
@@ -1188,8 +1281,8 @@ static enum ethernet_hw_caps eth_stm32_hal_get_capabilities(const struct device
 		| ETHERNET_HW_RX_CHKSUM_OFFLOAD
 		| ETHERNET_HW_TX_CHKSUM_OFFLOAD
 #endif
-#if defined(CONFIG_NET_DSA)
-		| ETHERNET_DSA_MASTER_PORT
+#if defined(CONFIG_NET_DSA_DEPRECATED)
+		| ETHERNET_DSA_CONDUIT_PORT
 #endif
 #if defined(CONFIG_ETH_STM32_MULTICAST_FILTER)
 		| ETHERNET_HW_FILTERING
@@ -1197,6 +1290,47 @@ static enum ethernet_hw_caps eth_stm32_hal_get_capabilities(const struct device
 		;
 }
 
+static int eth_stm32_hal_get_config(const struct device *dev, enum ethernet_config_type type,
+				    struct ethernet_config *config)
+{
+	int ret = -ENOTSUP;
+	struct eth_stm32_hal_dev_data *dev_data;
+	ETH_HandleTypeDef *heth;
+
+	dev_data = dev->data;
+	heth = &dev_data->heth;
+
+	switch (type) {
+	case ETHERNET_CONFIG_TYPE_MAC_ADDRESS:
+		memcpy(config->mac_address.addr, dev_data->mac_addr,
+		       sizeof(config->mac_address.addr));
+		ret = 0;
+		break;
+	case ETHERNET_CONFIG_TYPE_PROMISC_MODE:
+#if defined(CONFIG_NET_PROMISCUOUS_MODE)
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
+		if (heth->Instance->MACPFR & ETH_MACPFR_PR) {
+			config->promisc_mode = true;
+		} else {
+			config->promisc_mode = false;
+		}
+#else
+		if (heth->Instance->MACFFR & ETH_MACFFR_PM) {
+			config->promisc_mode = true;
+		} else {
+			config->promisc_mode = false;
+		}
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
+		ret = 0;
+#endif /* CONFIG_NET_PROMISCUOUS_MODE */
+		break;
+	default:
+		break;
+	}
+
+	return ret;
+}
+
 static int eth_stm32_hal_set_config(const struct device *dev,
 				    enum ethernet_config_type type,
 				    const struct ethernet_config *config)
@@ -1252,6 +1386,12 @@ static int eth_stm32_hal_set_config(const struct device *dev,
 	return ret;
 }
 
+static const struct device *eth_stm32_hal_get_phy(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+	return eth_stm32_phy_dev;
+}
+
 #if defined(CONFIG_PTP_CLOCK_STM32_HAL)
 static const struct device *eth_stm32_get_ptp_clock(const struct device *dev)
 {
@@ -1277,7 +1417,9 @@ static const struct ethernet_api eth_api = {
 #endif /* CONFIG_PTP_CLOCK_STM32_HAL */
 	.get_capabilities = eth_stm32_hal_get_capabilities,
 	.set_config = eth_stm32_hal_set_config,
-#if defined(CONFIG_NET_DSA)
+	.get_phy = eth_stm32_hal_get_phy,
+	.get_config = eth_stm32_hal_get_config,
+#if defined(CONFIG_NET_DSA_DEPRECATED)
 	.send = dsa_tx,
 #else
 	.send = eth_tx,
@@ -1298,8 +1440,8 @@ PINCTRL_DT_INST_DEFINE(0);
 
 static const struct eth_stm32_hal_dev_cfg eth0_config = {
 	.config_func = eth0_irq_config,
-	.pclken = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bus),
-		   .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bits)},
+	.pclken = {.bus = DT_CLOCKS_CELL_BY_NAME(DT_INST_PARENT(0), stm_eth, bus),
+		   .enr = DT_CLOCKS_CELL_BY_NAME(DT_INST_PARENT(0), stm_eth, bits)},
 	.pclken_tx = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_tx, bus),
 		      .enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_tx, bits)},
 	.pclken_rx = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_rx, bus),
@@ -1311,27 +1453,26 @@ static const struct eth_stm32_hal_dev_cfg eth0_config = {
 	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
 };
 
+BUILD_ASSERT(DT_ENUM_HAS_VALUE(MAC_NODE, phy_connection_type, mii)
+	|| DT_ENUM_HAS_VALUE(MAC_NODE, phy_connection_type, rmii)
+	IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_ethernet),
+	(|| DT_ENUM_HAS_VALUE(MAC_NODE, phy_connection_type, rgmii)
+	 || DT_ENUM_HAS_VALUE(MAC_NODE, phy_connection_type, gmii))),
+			"Unsupported PHY connection type");
+
 static struct eth_stm32_hal_dev_data eth0_data = {
 	.heth = {
-		.Instance = (ETH_TypeDef *)DT_INST_REG_ADDR(0),
+		.Instance = (ETH_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(0)),
 		.Init = {
-#if !defined(CONFIG_ETH_STM32_HAL_API_V2)
-#if defined(CONFIG_ETH_STM32_AUTO_NEGOTIATION_ENABLE)
-			.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE,
-#else
-			.AutoNegotiation = ETH_AUTONEGOTIATION_DISABLE,
-			.Speed = IS_ENABLED(CONFIG_ETH_STM32_SPEED_10M) ?
-				 ETH_SPEED_10M : ETH_SPEED_100M,
-			.DuplexMode = IS_ENABLED(CONFIG_ETH_STM32_MODE_HALFDUPLEX) ?
-				      ETH_MODE_HALFDUPLEX : ETH_MODE_FULLDUPLEX,
-#endif /* !CONFIG_ETH_STM32_AUTO_NEGOTIATION_ENABLE */
-			.PhyAddress = PHY_ADDR,
+#if defined(CONFIG_ETH_STM32_HAL_API_V1)
+			.AutoNegotiation = ETH_STM32_AUTO_NEGOTIATION_ENABLE ?
+					   ETH_AUTONEGOTIATION_ENABLE : ETH_AUTONEGOTIATION_DISABLE,
+			.PhyAddress = DT_REG_ADDR(DT_INST_PHANDLE(0, phy_handle)),
 			.RxMode = ETH_RXINTERRUPT_MODE,
 			.ChecksumMode = IS_ENABLED(CONFIG_ETH_STM32_HW_CHECKSUM) ?
 					ETH_CHECKSUM_BY_HARDWARE : ETH_CHECKSUM_BY_SOFTWARE,
-#endif /* !CONFIG_SOC_SERIES_STM32H7X */
-			.MediaInterface = IS_ENABLED(CONFIG_ETH_STM32_HAL_MII) ?
-					  ETH_MEDIA_INTERFACE_MII : ETH_MEDIA_INTERFACE_RMII,
+#endif /* CONFIG_ETH_STM32_HAL_API_V1 */
+			.MediaInterface = STM32_ETH_PHY_MODE(MAC_NODE),
 		},
 	},
 };
diff --git a/drivers/ethernet/eth_stm32_hal_priv.h b/drivers/ethernet/eth_stm32_hal_priv.h
index 4aef0389d40..53a01462c37 100644
--- a/drivers/ethernet/eth_stm32_hal_priv.h
+++ b/drivers/ethernet/eth_stm32_hal_priv.h
@@ -56,7 +56,6 @@ struct eth_stm32_hal_dev_data {
 	K_KERNEL_STACK_MEMBER(rx_thread_stack,
 		CONFIG_ETH_STM32_HAL_RX_THREAD_STACK_SIZE);
 	struct k_thread rx_thread;
-	bool link_up;
 #if defined(CONFIG_ETH_STM32_MULTICAST_FILTER)
 	uint8_t hash_index_cnt[64];
 #endif /* CONFIG_ETH_STM32_MULTICAST_FILTER */
diff --git a/drivers/ethernet/eth_xilinx_axienet.c b/drivers/ethernet/eth_xilinx_axienet.c
new file mode 100644
index 00000000000..0292fd95eb9
--- /dev/null
+++ b/drivers/ethernet/eth_xilinx_axienet.c
@@ -0,0 +1,607 @@
+/*
+ * Xilinx AXI 1G / 2.5G Ethernet Subsystem
+ *
+ * Copyright(c) 2024, CISPA Helmholtz Center for Information Security
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(eth_xilinx_axienet, CONFIG_ETHERNET_LOG_LEVEL);
+
+#include <sys/types.h>
+#include <zephyr/kernel.h>
+#include <zephyr/net/ethernet.h>
+#include <ethernet/eth_stats.h>
+#include <zephyr/drivers/dma.h>
+#include <zephyr/net/phy.h>
+#include <zephyr/irq.h>
+#include <zephyr/sys/barrier.h>
+
+#include "../dma/dma_xilinx_axi_dma.h"
+
+/* register offsets and masks */
+#define XILINX_AXIENET_INTERRUPT_STATUS_OFFSET         0x0000000C
+#define XILINX_AXIENET_INTERRUPT_STATUS_RXREJ_MASK     0x00000008
+#define XILINX_AXIENET_INTERRUPT_STATUS_RXFIFOOVR_MASK 0x00000010 /* Rx fifo overrun */
+#define XILINX_AXIENET_INTERRUPT_PENDING_OFFSET        0x00000010
+
+#define XILINX_AXIENET_INTERRUPT_PENDING_RXCMPIT_MASK     0x00000004 /* Rx complete */
+#define XILINX_AXIENET_INTERRUPT_PENDING_RXRJECT_MASK     0x00000008 /* Rx frame rejected */
+#define XILINX_AXIENET_INTERRUPT_PENDING_RXFIFOOVR_MASK   0x00000010 /* Rx fifo overrun */
+#define XILINX_AXIENET_INTERRUPT_PENDING_TXCMPIT_MASK     0x00000020 /* Tx complete */
+#define XILINX_AXIENET_INTERRUPT_PENDING_RXDCMLOCK_MASK   0x00000040 /* Rx Dcm Lock */
+#define XILINX_AXIENET_INTERRUPT_PENDING_MGTRDY_MASK      0x00000080 /* MGT clock Lock */
+#define XILINX_AXIENET_INTERRUPT_PENDING_PHYRSTCMPLT_MASK 0x00000100 /* Phy Reset complete */
+
+#define XILINX_AXIENET_INTERRUPT_ENABLE_OFFSET     0x00000014
+#define XILINX_AXIENET_INTERRUPT_ENABLE_RXREJ_MASK 0x00000008
+#define XILINX_AXIENET_INTERRUPT_ENABLE_OVR_MASK   0x00000010 /* FIFO overrun */
+
+#define XILINX_AXIENET_RECEIVER_CONFIGURATION_WORD_0_REG_OFFSET     0x00000400
+#define XILINX_AXIENET_RECEIVER_CONFIGURATION_WORD_1_REG_OFFSET     0x00000404
+#define XILINX_AXIENET_RECEIVER_CONFIGURATION_WORD_1_REG_RX_EN_MASK 0x10000000
+#define XILINX_AXIENET_RECEIVER_CONFIGURATION_FLOW_CONTROL_OFFSET   0x0000040C
+#define XILINX_AXIENET_RECEIVER_CONFIGURATION_FLOW_CONTROL_EN_MASK  0x20000000
+#define XILINX_AXIENET_TX_CONTROL_REG_OFFSET                        0x00000408
+#define XILINX_AXIENET_TX_CONTROL_TX_EN_MASK                        (1 << 11)
+
+#define XILINX_AXIENET_UNICAST_ADDRESS_WORD_0_OFFSET 0x00000700
+#define XILINX_AXIENET_UNICAST_ADDRESS_WORD_1_OFFSET 0x00000704
+
+#if (CONFIG_DCACHE_LINE_SIZE > 0)
+/* cache-line aligned to allow selective cache-line invalidation on the buffer */
+#define XILINX_AXIENET_ETH_ALIGN CONFIG_DCACHE_LINE_SIZE
+#else
+/* pointer-aligned to reduce padding in the struct */
+#define XILINX_AXIENET_ETH_ALIGN sizeof(void *)
+#endif
+
+#define XILINX_AXIENET_ETH_BUFFER_SIZE                                                             \
+	((NET_ETH_MAX_FRAME_SIZE + XILINX_AXIENET_ETH_ALIGN - 1) & ~(XILINX_AXIENET_ETH_ALIGN - 1))
+
+struct xilinx_axienet_buffer {
+	uint8_t buffer[XILINX_AXIENET_ETH_BUFFER_SIZE];
+} __aligned(XILINX_AXIENET_ETH_ALIGN);
+
+/* device state */
+struct xilinx_axienet_data {
+	struct xilinx_axienet_buffer tx_buffer[CONFIG_ETH_XILINX_AXIENET_BUFFER_NUM_TX];
+	struct xilinx_axienet_buffer rx_buffer[CONFIG_ETH_XILINX_AXIENET_BUFFER_NUM_RX];
+
+	size_t rx_populated_buffer_index;
+	size_t rx_completed_buffer_index;
+	size_t tx_populated_buffer_index;
+	size_t tx_completed_buffer_index;
+
+	struct net_if *interface;
+
+	/* device mac address */
+	uint8_t mac_addr[NET_ETH_ADDR_LEN];
+	bool dma_is_configured_rx;
+	bool dma_is_configured_tx;
+};
+
+/* global configuration per Ethernet device */
+struct xilinx_axienet_config {
+	void (*config_func)(const struct xilinx_axienet_data *dev);
+	const struct device *dma;
+
+	const struct device *phy;
+
+	mem_addr_t reg;
+
+	int irq_num;
+	bool have_irq;
+
+	bool have_rx_csum_offload;
+	bool have_tx_csum_offload;
+};
+
+static void xilinx_axienet_write_register(const struct xilinx_axienet_config *config,
+					  mem_addr_t reg_offset, uint32_t value)
+{
+	sys_write32(value, config->reg + reg_offset);
+}
+
+static uint32_t xilinx_axienet_read_register(const struct xilinx_axienet_config *config,
+					     mem_addr_t reg_offset)
+{
+	return sys_read32(config->reg + reg_offset);
+}
+static int setup_dma_rx_transfer(const struct device *dev,
+				 const struct xilinx_axienet_config *config,
+				 struct xilinx_axienet_data *data);
+
+/* called by DMA when a packet is available */
+static void xilinx_axienet_rx_callback(const struct device *dma, void *user_data, uint32_t channel,
+				       int status)
+{
+	struct device *ethdev = (struct device *)user_data;
+	struct xilinx_axienet_data *data = ethdev->data;
+	unsigned int packet_size;
+	struct net_pkt *pkt;
+
+	size_t next_descriptor =
+		(data->rx_completed_buffer_index + 1) % CONFIG_ETH_XILINX_AXIENET_BUFFER_NUM_RX;
+	size_t current_descriptor = data->rx_completed_buffer_index;
+
+	if (!net_if_is_up(data->interface)) {
+		/*
+		 * cannot receive data now, so discard silently
+		 * setup new transfer for when the interface is back up
+		 */
+		goto setup_new_transfer;
+	}
+
+	if (status < 0) {
+		LOG_ERR("DMA RX error: %d", status);
+		eth_stats_update_errors_rx(data->interface);
+		goto setup_new_transfer;
+	}
+
+	data->rx_completed_buffer_index = next_descriptor;
+
+	packet_size = dma_xilinx_axi_dma_last_received_frame_length(dma);
+	pkt = net_pkt_rx_alloc_with_buffer(data->interface, packet_size, AF_UNSPEC, 0, K_NO_WAIT);
+
+	if (!pkt) {
+		LOG_ERR("Could not allocate a packet!");
+		goto setup_new_transfer;
+	}
+	if (net_pkt_write(pkt, data->rx_buffer[current_descriptor].buffer, packet_size)) {
+		LOG_ERR("Could not write RX buffer into packet!");
+		net_pkt_unref(pkt);
+		goto setup_new_transfer;
+	}
+	if (net_recv_data(data->interface, pkt) < 0) {
+		LOG_ERR("Coult not receive packet data!");
+		net_pkt_unref(pkt);
+		goto setup_new_transfer;
+	}
+
+	LOG_DBG("Packet with %u bytes received!\n", packet_size);
+
+	/* we need to start a new DMA transfer irregardless of whether the DMA reported an error */
+	/* otherwise, the ethernet subsystem would just stop receiving */
+setup_new_transfer:
+	if (setup_dma_rx_transfer(ethdev, ethdev->config, ethdev->data)) {
+		LOG_ERR("Could not set up next RX DMA transfer!");
+	}
+}
+
+static void xilinx_axienet_tx_callback(const struct device *dev, void *user_data, uint32_t channel,
+				       int status)
+{
+	struct device *ethdev = (struct device *)user_data;
+	struct xilinx_axienet_data *data = ethdev->data;
+	size_t next_descriptor =
+		(data->tx_completed_buffer_index + 1) % CONFIG_ETH_XILINX_AXIENET_BUFFER_NUM_TX;
+
+	data->tx_completed_buffer_index = next_descriptor;
+
+	if (status < 0) {
+		LOG_ERR("DMA TX error: %d", status);
+		eth_stats_update_errors_tx(data->interface);
+	}
+}
+
+static int setup_dma_rx_transfer(const struct device *dev,
+				 const struct xilinx_axienet_config *config,
+				 struct xilinx_axienet_data *data)
+{
+	int err;
+	size_t next_descriptor =
+		(data->rx_populated_buffer_index + 1) % CONFIG_ETH_XILINX_AXIENET_BUFFER_NUM_RX;
+	size_t current_descriptor = data->rx_populated_buffer_index;
+
+	if (next_descriptor == data->rx_completed_buffer_index) {
+		LOG_ERR("Cannot start RX via DMA - populated buffer %zu will run into completed"
+			" buffer %zu!",
+			data->rx_populated_buffer_index, data->rx_completed_buffer_index);
+		return -ENOSPC;
+	}
+
+	if (!data->dma_is_configured_rx) {
+		struct dma_block_config head_block = {
+			.source_address = 0x0,
+			.dest_address = (uintptr_t)data->rx_buffer[current_descriptor].buffer,
+			.block_size = sizeof(data->rx_buffer[current_descriptor].buffer),
+			.next_block = NULL,
+			.source_addr_adj = DMA_ADDR_ADJ_INCREMENT,
+			.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT};
+		struct dma_config dma_conf = {.dma_slot = 0,
+					      .channel_direction = PERIPHERAL_TO_MEMORY,
+					      .complete_callback_en = 1,
+					      .error_callback_dis = 0,
+					      .block_count = 1,
+					      .head_block = &head_block,
+					      .user_data = (void *)dev,
+					      .dma_callback = xilinx_axienet_rx_callback};
+
+		if (config->have_rx_csum_offload) {
+			dma_conf.linked_channel = XILINX_AXI_DMA_LINKED_CHANNEL_FULL_CSUM_OFFLOAD;
+		} else {
+			dma_conf.linked_channel = XILINX_AXI_DMA_LINKED_CHANNEL_NO_CSUM_OFFLOAD;
+		}
+
+		err = dma_config(config->dma, XILINX_AXI_DMA_RX_CHANNEL_NUM, &dma_conf);
+		if (err) {
+			LOG_ERR("DMA config failed: %d", err);
+			return err;
+		}
+
+		data->dma_is_configured_rx = true;
+	} else {
+		/* can use faster "reload" API, as everything else stays the same */
+		err = dma_reload(config->dma, XILINX_AXI_DMA_RX_CHANNEL_NUM, 0x0,
+				 (uintptr_t)data->rx_buffer[current_descriptor].buffer,
+				 sizeof(data->rx_buffer[current_descriptor].buffer));
+		if (err) {
+			LOG_ERR("DMA reconfigure failed: %d", err);
+			return err;
+		}
+	}
+	LOG_DBG("Receiving one packet with DMA!");
+
+	/* prevent concurrent modification */
+	data->rx_populated_buffer_index = next_descriptor;
+
+	err = dma_start(config->dma, XILINX_AXI_DMA_RX_CHANNEL_NUM);
+
+	if (err) {
+		/* buffer has not been accepted by DMA */
+		data->rx_populated_buffer_index = current_descriptor;
+	}
+
+	return err;
+}
+
+/* assumes that the caller has set up data->tx_buffer */
+static int setup_dma_tx_transfer(const struct device *dev,
+				 const struct xilinx_axienet_config *config,
+				 struct xilinx_axienet_data *data, uint32_t buffer_len)
+{
+	int err;
+	size_t next_descriptor =
+		(data->tx_populated_buffer_index + 1) % CONFIG_ETH_XILINX_AXIENET_BUFFER_NUM_TX;
+	size_t current_descriptor = data->tx_populated_buffer_index;
+
+	if (next_descriptor == data->tx_completed_buffer_index) {
+		LOG_ERR("Cannot start TX via DMA - populated buffer %zu will run into completed"
+			" buffer %zu!",
+			data->tx_populated_buffer_index, data->tx_completed_buffer_index);
+		return -ENOSPC;
+	}
+
+	if (!data->dma_is_configured_tx) {
+		struct dma_block_config head_block = {
+			.source_address = (uintptr_t)data->tx_buffer[current_descriptor].buffer,
+			.dest_address = 0x0,
+			.block_size = buffer_len,
+			.next_block = NULL,
+			.source_addr_adj = DMA_ADDR_ADJ_INCREMENT,
+			.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT};
+		struct dma_config dma_conf = {.dma_slot = 0,
+					      .channel_direction = MEMORY_TO_PERIPHERAL,
+					      .complete_callback_en = 1,
+					      .error_callback_dis = 0,
+					      .block_count = 1,
+					      .head_block = &head_block,
+					      .user_data = (void *)dev,
+					      .dma_callback = xilinx_axienet_tx_callback};
+
+		if (config->have_tx_csum_offload) {
+			dma_conf.linked_channel = XILINX_AXI_DMA_LINKED_CHANNEL_FULL_CSUM_OFFLOAD;
+		} else {
+			dma_conf.linked_channel = XILINX_AXI_DMA_LINKED_CHANNEL_NO_CSUM_OFFLOAD;
+		}
+
+		err = dma_config(config->dma, XILINX_AXI_DMA_TX_CHANNEL_NUM, &dma_conf);
+		if (err) {
+			LOG_ERR("DMA config failed: %d", err);
+			return err;
+		}
+
+		data->dma_is_configured_tx = true;
+	} else {
+		/* can use faster "reload" API, as everything else stays the same */
+		err = dma_reload(config->dma, XILINX_AXI_DMA_TX_CHANNEL_NUM,
+				 (uintptr_t)data->tx_buffer[current_descriptor].buffer, 0x0,
+				 buffer_len);
+		if (err) {
+			LOG_ERR("DMA reconfigure failed: %d", err);
+			return err;
+		}
+	}
+
+	/* prevent concurrent modification */
+	data->tx_populated_buffer_index = next_descriptor;
+
+	err = dma_start(config->dma, XILINX_AXI_DMA_TX_CHANNEL_NUM);
+
+	if (err) {
+		/* buffer has not been accepted by DMA */
+		data->tx_populated_buffer_index = current_descriptor;
+	}
+
+	return err;
+}
+
+static void xilinx_axienet_isr(const struct device *dev)
+{
+	const struct xilinx_axienet_config *config = dev->config;
+	struct xilinx_axienet_data *data = dev->data;
+	uint32_t status =
+		xilinx_axienet_read_register(config, XILINX_AXIENET_INTERRUPT_PENDING_OFFSET);
+
+	(void)data;
+
+	if (status & XILINX_AXIENET_INTERRUPT_PENDING_RXFIFOOVR_MASK) {
+		LOG_WRN("FIFO was overrun - probably lost packets!");
+		eth_stats_update_errors_rx(data->interface);
+	} else if (status & XILINX_AXIENET_INTERRUPT_PENDING_RXRJECT_MASK) {
+		/* this is extremely rare on Ethernet */
+		/* most likely cause is mistake in FPGA configuration */
+		LOG_WRN("Erroneous frame received!");
+		eth_stats_update_errors_rx(data->interface);
+	}
+
+	if (status != 0) {
+		/* clear IRQ by writing the same value back */
+		xilinx_axienet_write_register(config, XILINX_AXIENET_INTERRUPT_STATUS_OFFSET,
+					      status);
+	}
+}
+
+static enum ethernet_hw_caps xilinx_axienet_caps(const struct device *dev)
+{
+	const struct xilinx_axienet_config *config = dev->config;
+	enum ethernet_hw_caps ret = ETHERNET_LINK_10BASE_T | ETHERNET_LINK_100BASE_T |
+				    ETHERNET_LINK_1000BASE_T;
+
+	if (config->have_rx_csum_offload) {
+		ret |= ETHERNET_HW_RX_CHKSUM_OFFLOAD;
+	}
+	if (config->have_tx_csum_offload) {
+		ret |= ETHERNET_HW_TX_CHKSUM_OFFLOAD;
+	}
+
+	return ret;
+}
+
+static const struct device *xilinx_axienet_get_phy(const struct device *dev)
+{
+	const struct xilinx_axienet_config *config = dev->config;
+
+	return config->phy;
+}
+
+static int xilinx_axienet_get_config(const struct device *dev, enum ethernet_config_type type,
+				     struct ethernet_config *config)
+{
+	const struct xilinx_axienet_config *dev_config = dev->config;
+	const struct xilinx_axienet_data *data = dev->data;
+	struct phy_link_state link_state;
+	int err;
+
+	switch (type) {
+	case ETHERNET_CONFIG_TYPE_RX_CHECKSUM_SUPPORT:
+		if (dev_config->have_rx_csum_offload) {
+			config->chksum_support =
+				ETHERNET_CHECKSUM_SUPPORT_IPV4_HEADER |
+				ETHERNET_CHECKSUM_SUPPORT_TCP | ETHERNET_CHECKSUM_SUPPORT_UDP |
+				ETHERNET_CHECKSUM_SUPPORT_IPV6_HEADER |
+				ETHERNET_CHECKSUM_SUPPORT_TCP | ETHERNET_CHECKSUM_SUPPORT_UDP;
+		} else {
+			config->chksum_support = ETHERNET_CHECKSUM_SUPPORT_NONE;
+		}
+		return 0;
+	case ETHERNET_CONFIG_TYPE_TX_CHECKSUM_SUPPORT:
+		if (dev_config->have_tx_csum_offload) {
+			config->chksum_support =
+				ETHERNET_CHECKSUM_SUPPORT_IPV4_HEADER |
+				ETHERNET_CHECKSUM_SUPPORT_TCP | ETHERNET_CHECKSUM_SUPPORT_UDP |
+				ETHERNET_CHECKSUM_SUPPORT_IPV6_HEADER |
+				ETHERNET_CHECKSUM_SUPPORT_TCP | ETHERNET_CHECKSUM_SUPPORT_UDP;
+		} else {
+			config->chksum_support = ETHERNET_CHECKSUM_SUPPORT_NONE;
+		}
+		return 0;
+	default:
+		LOG_ERR("Unsupported configuration queried: %u", type);
+		return -EINVAL;
+	}
+}
+
+static void xilinx_axienet_set_mac_address(const struct xilinx_axienet_config *config,
+					   const struct xilinx_axienet_data *data)
+{
+	xilinx_axienet_write_register(config, XILINX_AXIENET_UNICAST_ADDRESS_WORD_0_OFFSET,
+				      (data->mac_addr[0]) | (data->mac_addr[1] << 8) |
+					      (data->mac_addr[2] << 16) |
+					      (data->mac_addr[3] << 24));
+	xilinx_axienet_write_register(config, XILINX_AXIENET_UNICAST_ADDRESS_WORD_1_OFFSET,
+				      (data->mac_addr[4]) | (data->mac_addr[5] << 8));
+}
+
+static int xilinx_axienet_set_config(const struct device *dev, enum ethernet_config_type type,
+				     const struct ethernet_config *config)
+{
+	const struct xilinx_axienet_config *dev_config = dev->config;
+	struct xilinx_axienet_data *data = dev->data;
+
+	switch (type) {
+	case ETHERNET_CONFIG_TYPE_MAC_ADDRESS:
+		memcpy(data->mac_addr, config->mac_address.addr, sizeof(data->mac_addr));
+		xilinx_axienet_set_mac_address(dev_config, data);
+		return net_if_set_link_addr(data->interface, data->mac_addr,
+			sizeof(data->mac_addr), NET_LINK_ETHERNET);
+	default:
+		LOG_ERR("Unsupported configuration set: %u", type);
+		return -EINVAL;
+	}
+}
+
+static void phy_link_state_changed(const struct device *dev, struct phy_link_state *state,
+				   void *user_data)
+{
+	struct xilinx_axienet_data *data = user_data;
+
+	ARG_UNUSED(dev);
+
+	LOG_INF("Link state changed to: %s (speed %x)", state->is_up ? "up" : "down", state->speed);
+
+	/* inform the L2 driver about link event */
+	if (state->is_up) {
+		net_eth_carrier_on(data->interface);
+	} else {
+		net_eth_carrier_off(data->interface);
+	}
+}
+
+static void xilinx_axienet_iface_init(struct net_if *iface)
+{
+	struct xilinx_axienet_data *data = net_if_get_device(iface)->data;
+	const struct xilinx_axienet_config *config = net_if_get_device(iface)->config;
+	int err;
+
+	data->interface = iface;
+
+	ethernet_init(iface);
+
+	net_if_set_link_addr(iface, data->mac_addr, sizeof(data->mac_addr), NET_LINK_ETHERNET);
+
+	/* carrier is initially off */
+	net_eth_carrier_off(iface);
+
+	err = phy_link_callback_set(config->phy, phy_link_state_changed, data);
+
+	if (err) {
+		LOG_ERR("Could not set PHY link state changed handler : %d",
+			config->phy ? err : -1);
+	}
+
+	LOG_INF("Interface initialized!");
+}
+
+static int xilinx_axienet_send(const struct device *dev, struct net_pkt *pkt)
+{
+	struct xilinx_axienet_data *data = dev->data;
+	const struct xilinx_axienet_config *config = dev->config;
+	size_t pkt_len = net_pkt_get_len(pkt);
+	size_t current_descriptor = data->tx_populated_buffer_index;
+
+	if (net_pkt_read(pkt, data->tx_buffer[current_descriptor].buffer, pkt_len)) {
+		LOG_ERR("Failed to read packet into TX buffer!");
+		return -EIO;
+	}
+	return setup_dma_tx_transfer(dev, config, data, pkt_len);
+}
+
+static int xilinx_axienet_probe(const struct device *dev)
+{
+	const struct xilinx_axienet_config *config = dev->config;
+	struct xilinx_axienet_data *data = dev->data;
+	uint32_t status;
+	int err;
+
+	status = xilinx_axienet_read_register(
+		config, XILINX_AXIENET_RECEIVER_CONFIGURATION_WORD_1_REG_OFFSET);
+	status = status & ~XILINX_AXIENET_RECEIVER_CONFIGURATION_WORD_1_REG_RX_EN_MASK;
+	xilinx_axienet_write_register(
+		config, XILINX_AXIENET_RECEIVER_CONFIGURATION_WORD_1_REG_OFFSET, status);
+
+	/* RX disabled - it is safe to modify settings */
+
+	/* clear any RX rejected interrupts from when the core was not configured */
+	xilinx_axienet_write_register(config, XILINX_AXIENET_INTERRUPT_STATUS_OFFSET,
+				      XILINX_AXIENET_INTERRUPT_STATUS_RXREJ_MASK |
+					      XILINX_AXIENET_INTERRUPT_STATUS_RXFIFOOVR_MASK);
+
+	xilinx_axienet_write_register(config, XILINX_AXIENET_INTERRUPT_ENABLE_OFFSET,
+				      config->have_irq
+					      ? XILINX_AXIENET_INTERRUPT_ENABLE_RXREJ_MASK |
+							XILINX_AXIENET_INTERRUPT_ENABLE_OVR_MASK
+					      : 0);
+
+	xilinx_axienet_write_register(config,
+				      XILINX_AXIENET_RECEIVER_CONFIGURATION_FLOW_CONTROL_OFFSET,
+				      XILINX_AXIENET_RECEIVER_CONFIGURATION_FLOW_CONTROL_EN_MASK);
+
+	/* at time of writing, hardware does not support half duplex */
+	err = phy_configure_link(config->phy, LINK_FULL_10BASE_T | LINK_FULL_100BASE_T |
+						      LINK_FULL_1000BASE_T);
+	if (err) {
+		LOG_WRN("Could not configure PHY: %d", -err);
+	}
+
+	LOG_INF("RX Checksum offloading %s",
+		config->have_rx_csum_offload ? "requested" : "disabled");
+	LOG_INF("TX Checksum offloading %s",
+		config->have_tx_csum_offload ? "requested" : "disabled");
+
+	xilinx_axienet_set_mac_address(config, data);
+
+	for (int i = 0; i < CONFIG_ETH_XILINX_AXIENET_BUFFER_NUM_RX - 1; i++) {
+		setup_dma_rx_transfer(dev, config, data);
+	}
+
+	status = xilinx_axienet_read_register(
+		config, XILINX_AXIENET_RECEIVER_CONFIGURATION_WORD_1_REG_OFFSET);
+	status = status | XILINX_AXIENET_RECEIVER_CONFIGURATION_WORD_1_REG_RX_EN_MASK;
+	xilinx_axienet_write_register(
+		config, XILINX_AXIENET_RECEIVER_CONFIGURATION_WORD_1_REG_OFFSET, status);
+
+	status = xilinx_axienet_read_register(config, XILINX_AXIENET_TX_CONTROL_REG_OFFSET);
+	status = status | XILINX_AXIENET_TX_CONTROL_TX_EN_MASK;
+	xilinx_axienet_write_register(config, XILINX_AXIENET_TX_CONTROL_REG_OFFSET, status);
+
+	config->config_func(data);
+
+	return 0;
+}
+
+/* TODO PTP, VLAN not supported yet */
+static const struct ethernet_api xilinx_axienet_api = {
+	.iface_api.init = xilinx_axienet_iface_init,
+	.get_capabilities = xilinx_axienet_caps,
+	.get_config = xilinx_axienet_get_config,
+	.set_config = xilinx_axienet_set_config,
+	.get_phy = xilinx_axienet_get_phy,
+	.send = xilinx_axienet_send,
+};
+
+#define SETUP_IRQS(inst)                                                                           \
+	IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), xilinx_axienet_isr,           \
+		    DEVICE_DT_INST_GET(inst), 0);                                                  \
+                                                                                                   \
+	irq_enable(DT_INST_IRQN(inst))
+
+#define XILINX_AXIENET_INIT(inst)                                                                  \
+                                                                                                   \
+	static void xilinx_axienet_config_##inst(const struct xilinx_axienet_data *dev)            \
+	{                                                                                          \
+		COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, interrupts), (SETUP_IRQS(inst)),           \
+			    (LOG_INF("No IRQs defined!")));        \
+	}                                                                                          \
+                                                                                                   \
+	static struct xilinx_axienet_data data_##inst = {                                          \
+		.mac_addr = DT_INST_PROP(inst, local_mac_address),                                 \
+		.dma_is_configured_rx = false,                                                     \
+		.dma_is_configured_tx = false};                                                    \
+	static const struct xilinx_axienet_config config_##inst = {                                \
+		.config_func = xilinx_axienet_config_##inst,                                       \
+		.dma = DEVICE_DT_GET(DT_INST_PHANDLE(inst, axistream_connected)),                  \
+		.phy = DEVICE_DT_GET(DT_INST_PHANDLE(inst, phy_handle)),                           \
+		.reg = DT_REG_ADDR(DT_INST_PARENT(inst)),                                          \
+		.have_irq = DT_INST_NODE_HAS_PROP(inst, interrupts),                               \
+		.have_tx_csum_offload = DT_INST_PROP_OR(inst, xlnx_txcsum, 0x0) == 0x2,            \
+		.have_rx_csum_offload = DT_INST_PROP_OR(inst, xlnx_rxcsum, 0x0) == 0x2,            \
+	};                                                                                         \
+                                                                                                   \
+	ETH_NET_DEVICE_DT_INST_DEFINE(inst, xilinx_axienet_probe, NULL, &data_##inst,              \
+				      &config_##inst, CONFIG_ETH_INIT_PRIORITY,                    \
+				      &xilinx_axienet_api, NET_ETH_MTU);
+
+#define DT_DRV_COMPAT xlnx_axi_ethernet_1_00_a
+DT_INST_FOREACH_STATUS_OKAY(XILINX_AXIENET_INIT);
diff --git a/drivers/ethernet/nxp_enet/CMakeLists.txt b/drivers/ethernet/nxp_enet/CMakeLists.txt
deleted file mode 100644
index 777a1624ff1..00000000000
--- a/drivers/ethernet/nxp_enet/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright 2024 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library_sources_ifdef(CONFIG_ETH_NXP_ENET eth_nxp_enet.c)
-zephyr_library_sources_ifdef(CONFIG_ETH_MCUX eth_mcux.c)
diff --git a/drivers/ethernet/nxp_enet/Kconfig b/drivers/ethernet/nxp_enet/Kconfig
deleted file mode 100644
index 848d44b4856..00000000000
--- a/drivers/ethernet/nxp_enet/Kconfig
+++ /dev/null
@@ -1,195 +0,0 @@
-# NXP ENET ethernet drivers configuration options
-
-# Copyright (c) 2016-2017 ARM Ltd
-# Copyright 2024 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-menu "NXP ENET"
-
-choice NXP_ENET_DRIVER
-	prompt "NXP ENET Driver Version"
-	default ETH_NXP_ENET if DT_HAS_NXP_ENET_MAC_ENABLED
-	default ETH_MCUX if DT_HAS_NXP_KINETIS_ETHERNET_ENABLED
-	depends on DT_HAS_NXP_ENET_MAC_ENABLED || DT_HAS_NXP_KINETIS_ETHERNET_ENABLED
-
-config ETH_NXP_ENET
-	bool "NXP ENET Ethernet driver"
-	select NOCACHE_MEMORY if HAS_MCUX_CACHE && CPU_HAS_DCACHE
-	select ARM_MPU if CPU_CORTEX_M7
-	select MDIO if DT_HAS_NXP_ENET_MDIO_ENABLED
-	select NET_POWER_MANAGEMENT if (PM_DEVICE && SOC_FAMILY_KINETIS)
-	select ETH_DSA_SUPPORT
-	select PINCTRL
-	help
-	  Enable NXP ENET Ethernet driver.
-
-config ETH_MCUX
-	bool "MCUX Ethernet driver"
-	select NOCACHE_MEMORY if HAS_MCUX_CACHE && CPU_HAS_DCACHE
-	select ARM_MPU if CPU_CORTEX_M7
-	select NET_POWER_MANAGEMENT if PM_DEVICE
-	select ETH_DSA_SUPPORT
-	select DEPRECATED
-	select PINCTRL
-	help
-	  Enable deprecated legacy MCUX Ethernet driver.
-	  Note, this driver performs one shot PHY setup.
-	  There is no support for PHY disconnect, reconnect or configuration change.
-
-endchoice
-
-if ETH_NXP_ENET
-
-config ETH_NXP_ENET_1G
-	bool "1G mode for ENET1G instance"
-	default y
-	depends on DT_HAS_NXP_ENET1G_ENABLED
-	help
-	  Enable the use of the ENET1G ethernet instance in 1G mode.
-
-config ETH_NXP_ENET_USE_DTCM_FOR_DMA_BUFFER
-	bool "Use DTCM for hardware DMA buffers"
-	default y
-	help
-	  Place the hardware DMA buffers into DTCM for better
-	  networking performance.
-
-config ETH_NXP_ENET_HW_ACCELERATION
-	bool "Hardware acceleration"
-	default y
-	help
-	  Enable hardware acceleration for the following:
-	  - IPv4, UDP and TCP checksum (both Rx and Tx)
-
-config ETH_NXP_ENET_RX_BUFFERS
-	int "Number of RX buffers for ethernet driver"
-	default 6
-	range 6 16
-	help
-	  Set the number of RX buffers provided to the NXP ENET driver.
-
-config ETH_NXP_ENET_TX_BUFFERS
-	int "Number of TX buffers for ethernet driver"
-	default 1
-	range 1 16
-	help
-	  Set the number of TX buffers provided to the NXP ENET driver.
-
-config ETH_NXP_ENET_RX_THREAD_STACK_SIZE
-	int "NXP ENET RX thread stack size"
-	default 1600
-	help
-	  ENET RX thread stack size in bytes.
-
-config ETH_NXP_ENET_RX_THREAD_PRIORITY
-	int "NXP ENET driver RX cooperative thread priority"
-	default 2
-	help
-	  ENET MAC Driver handles RX in cooperative workqueue thread.
-	  This options sets the priority of that thread.
-
-endif # ETH_NXP_ENET
-
-if ETH_MCUX
-
-config ETH_MCUX_PROMISCUOUS_MODE
-	bool "Promiscuous mode"
-	help
-	  Place the Ethernet receiver in promiscuous mode. This may be useful
-	  for debugging and not needed for normal work.
-
-config ETH_MCUX_USE_DTCM_FOR_DMA_BUFFER
-	bool "Use DTCM for hardware DMA buffers"
-	default y
-	help
-	  Place the hardware DMA buffers into DTCM for better
-	  networking performance.
-
-config ETH_MCUX_HW_ACCELERATION
-	bool "Hardware acceleration"
-	default y
-	help
-	  Enable hardware acceleration for the following:
-	  - IPv4, UDP and TCP checksum (both Rx and Tx)
-
-config ETH_MCUX_RX_BUFFERS
-	int "Number of RX buffers for ethernet driver"
-	default 6
-	range 6 16
-	help
-	  Set the number of RX buffers provided to the NXP ENET driver.
-
-config ETH_MCUX_TX_BUFFERS
-	int "Number of TX buffers for ethernet driver"
-	default 1
-	range 1 16
-	help
-	  Set the number of TX buffers provided to the NXP ENET driver.
-
-menu "Legacy driver options"
-
-config ETH_MCUX_RMII_EXT_CLK
-	bool "RMII clock from external sources"
-	help
-	  Setting this option will configure MCUX clock block to feed RMII
-	  reference clock from external source (ENET_1588_CLKIN)
-
-config ETH_MCUX_NO_PHY_SMI
-	bool "Do not use SMI for PHY communication"
-	help
-	  Some PHY devices, with DSA capabilities do not use SMI for
-	  communication with MAC ENET controller. Other busses - like SPI
-	  or I2C are used instead.
-
-config ETH_MCUX_PHY_TICK_MS
-	int "PHY poll period (ms)"
-	default 1000
-	range 100 30000
-	help
-	  Set the PHY status polling period.
-
-config ETH_MCUX_PHY_EXTRA_DEBUG
-	bool "Additional detailed PHY debug"
-	help
-	  Enable additional PHY related debug information related to
-	  PHY status polling.
-
-config ETH_MCUX_PHY_RESET
-	bool "Reset the PHY at boot"
-	help
-	  Reset the ethernet PHY at boot. Requires dts properties int-gpios and
-	  reset-gpios to be present.
-
-config PTP_CLOCK_MCUX
-	bool "MCUX PTP clock driver support"
-	default y
-	depends on PTP_CLOCK || NET_L2_PTP
-	help
-	  Enable MCUX PTP clock support.
-
-if PTP_CLOCK_MCUX
-
-config ETH_MCUX_PTP_CLOCK_SRC_HZ
-	int "Frequency of the clock source for the PTP timer"
-	default 50000000 if SOC_SERIES_KINETIS_K6X
-	default 50000000 if SOC_SERIES_IMXRT10XX
-	default 24000000 if SOC_SERIES_IMXRT11XX
-	help
-	  Set the frequency in Hz sourced to the PTP timer.
-	  If the value is set properly, the timer will be accurate.
-
-config ETH_MCUX_PTP_CLOCK_INIT_PRIO
-	int
-	default 85
-	help
-	  MCUX PTP Clock initialization priority level. There is
-	  a dependency from the network stack that this device
-	  initializes before network stack (NET_INIT_PRIO).
-
-endif # PTP_CLOCK_MCUX
-
-endmenu # Legacy options
-
-endif # ETH_MCUX
-
-endmenu # NXP ENET
diff --git a/drivers/ethernet/nxp_enet/eth_mcux.c b/drivers/ethernet/nxp_enet/eth_mcux.c
deleted file mode 100644
index 8d8fac6ad4d..00000000000
--- a/drivers/ethernet/nxp_enet/eth_mcux.c
+++ /dev/null
@@ -1,1745 +0,0 @@
-/* MCUX Ethernet Driver
- *
- *  Copyright (c) 2016-2017 ARM Ltd
- *  Copyright (c) 2016 Linaro Ltd
- *  Copyright (c) 2018 Intel Corporation
- *  Copyright 2023 NXP
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DT_DRV_COMPAT nxp_kinetis_ethernet
-
-/* Driver Limitations:
- *
- * There is no statistics collection for either normal operation or
- * error behaviour.
- */
-
-#define LOG_MODULE_NAME eth_mcux
-#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
-#define RING_ID 0
-
-#include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(LOG_MODULE_NAME);
-
-#include <zephyr/device.h>
-#include <zephyr/sys/util.h>
-#include <zephyr/kernel.h>
-#include <zephyr/sys/__assert.h>
-#include <zephyr/net/net_pkt.h>
-#include <zephyr/net/net_if.h>
-#include <zephyr/net/ethernet.h>
-#include <ethernet/eth_stats.h>
-#include <zephyr/pm/device.h>
-#include <zephyr/irq.h>
-
-#if defined(CONFIG_PTP_CLOCK_MCUX)
-#include <zephyr/drivers/ptp_clock.h>
-#endif
-
-#if defined(CONFIG_NET_DSA)
-#include <zephyr/net/dsa.h>
-#endif
-
-#include "fsl_enet.h"
-#include "fsl_phy.h"
-#include "fsl_phyksz8081.h"
-#include "fsl_enet_mdio.h"
-#if defined(CONFIG_NET_POWER_MANAGEMENT)
-#include "fsl_clock.h"
-#include <zephyr/drivers/clock_control.h>
-#endif
-#include <zephyr/devicetree.h>
-#include <zephyr/drivers/gpio.h>
-#if defined(CONFIG_PINCTRL)
-#include <zephyr/drivers/pinctrl.h>
-#endif
-
-#include "../eth.h"
-
-#define PHY_OMS_OVERRIDE_REG 0x16U      /* The PHY Operation Mode Strap Override register. */
-#define PHY_OMS_STATUS_REG 0x17U        /* The PHY Operation Mode Strap Status register. */
-
-#define PHY_OMS_NANDTREE_MASK 0x0020U     /* The PHY NAND Tree Strap-In Override/Status mask. */
-#define PHY_OMS_FACTORY_MODE_MASK 0x8000U /* The factory mode Override/Status mask. */
-
-/* Defines the PHY KSZ8081 vendor defined registers. */
-#define PHY_CONTROL1_REG 0x1EU /* The PHY control one register. */
-#define PHY_CONTROL2_REG 0x1FU /* The PHY control two register. */
-
-/* Defines the PHY KSZ8081 ID number. */
-#define PHY_CONTROL_ID1 0x22U /* The PHY ID1 */
-
-/* Defines the mask flag of operation mode in control registers */
-#define PHY_CTL2_REMOTELOOP_MASK    0x0004U /* The PHY remote loopback mask. */
-#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /* The PHY RMII reference clock select. */
-#define PHY_CTL1_10HALFDUPLEX_MASK  0x0001U /* The PHY 10M half duplex mask. */
-#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /* The PHY 100M half duplex mask. */
-#define PHY_CTL1_10FULLDUPLEX_MASK  0x0005U /* The PHY 10M full duplex mask. */
-#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /* The PHY 100M full duplex mask. */
-#define PHY_CTL1_SPEEDUPLX_MASK     0x0007U /* The PHY speed and duplex mask. */
-#define PHY_CTL1_ENERGYDETECT_MASK  0x10U   /* The PHY signal present on rx differential pair. */
-#define PHY_CTL1_LINKUP_MASK        0x100U  /* The PHY link up. */
-#define PHY_LINK_READY_MASK         (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
-
-/* Defines the timeout macro. */
-#define PHY_READID_TIMEOUT_COUNT 1000U
-
-/* Define RX and TX thread stack sizes */
-#define ETH_MCUX_RX_THREAD_STACK_SIZE 1600
-#define ETH_MCUX_TX_THREAD_STACK_SIZE 1600
-
-#define FREESCALE_OUI_B0 0x00
-#define FREESCALE_OUI_B1 0x04
-#define FREESCALE_OUI_B2 0x9f
-
-#define ETH_MCUX_FIXED_LINK_NODE \
-	DT_CHILD(DT_NODELABEL(enet), fixed_link)
-#define ETH_MCUX_FIXED_LINK \
-	DT_NODE_EXISTS(ETH_MCUX_FIXED_LINK_NODE)
-#define ETH_MCUX_FIXED_LINK_SPEED \
-	DT_PROP(ETH_MCUX_FIXED_LINK_NODE, speed)
-#define ETH_MCUX_FIXED_LINK_FULL_DUPLEX \
-	DT_PROP(ETH_MCUX_FIXED_LINK_NODE, full_duplex)
-
-enum eth_mcux_phy_state {
-	eth_mcux_phy_state_initial,
-	eth_mcux_phy_state_reset,
-	eth_mcux_phy_state_autoneg,
-	eth_mcux_phy_state_restart,
-	eth_mcux_phy_state_read_status,
-	eth_mcux_phy_state_read_duplex,
-	eth_mcux_phy_state_wait,
-	eth_mcux_phy_state_closing
-};
-
-struct _phy_resource {
-	mdioWrite write;
-	mdioRead read;
-};
-
-#if defined(CONFIG_NET_POWER_MANAGEMENT)
-extern uint32_t ENET_GetInstance(ENET_Type * base);
-static const clock_ip_name_t enet_clocks[] = ENET_CLOCKS;
-#endif
-
-static void eth_mcux_init(const struct device *dev);
-
-#if defined(CONFIG_ETH_MCUX_PHY_EXTRA_DEBUG)
-static const char *phy_state_name(enum eth_mcux_phy_state state)
-{
-	static const char * const name[] = {
-		"initial",
-		"reset",
-		"autoneg",
-		"restart",
-		"read-status",
-		"read-duplex",
-		"wait",
-		"closing"
-	};
-
-	return name[state];
-}
-#endif
-
-static const char *eth_name(ENET_Type *base)
-{
-	switch ((int)base) {
-	case DT_INST_REG_ADDR(0):
-		return "ETH_0";
-#if DT_NODE_HAS_STATUS_OKAY(DT_DRV_INST(1))
-	case DT_INST_REG_ADDR(1):
-		return "ETH_1";
-#endif
-	default:
-		return "unknown";
-	}
-}
-
-struct eth_context {
-	ENET_Type *base;
-	void (*config_func)(void);
-	struct net_if *iface;
-#if defined(CONFIG_NET_POWER_MANAGEMENT)
-	clock_ip_name_t clock;
-	const struct device *clock_dev;
-#endif
-	enet_handle_t enet_handle;
-#if defined(CONFIG_PTP_CLOCK_MCUX)
-	const struct device *ptp_clock;
-	enet_ptp_config_t ptp_config;
-	double clk_ratio;
-	struct k_mutex ptp_mutex;
-	struct k_sem ptp_ts_sem;
-#endif
-	struct k_sem tx_buf_sem;
-	phy_handle_t *phy_handle;
-	struct _phy_resource *phy_config;
-	struct k_sem rx_thread_sem;
-	enum eth_mcux_phy_state phy_state;
-	bool enabled;
-	bool link_up;
-	uint32_t phy_addr;
-	uint32_t rx_irq_num;
-	uint32_t tx_irq_num;
-	phy_duplex_t phy_duplex;
-	phy_speed_t phy_speed;
-	uint8_t mac_addr[6];
-	void (*generate_mac)(uint8_t *);
-	struct k_work phy_work;
-	struct k_work_delayable delayed_phy_work;
-
-	K_KERNEL_STACK_MEMBER(rx_thread_stack, ETH_MCUX_RX_THREAD_STACK_SIZE);
-	struct k_thread rx_thread;
-
-	/* TODO: FIXME. This Ethernet frame sized buffer is used for
-	 * interfacing with MCUX. How it works is that hardware uses
-	 * DMA scatter buffers to receive a frame, and then public
-	 * MCUX call gathers them into this buffer (there's no other
-	 * public interface). All this happens only for this driver
-	 * to scatter this buffer again into Zephyr fragment buffers.
-	 * This is not efficient, but proper resolution of this issue
-	 * depends on introduction of zero-copy networking support
-	 * in Zephyr, and adding needed interface to MCUX (or
-	 * bypassing it and writing a more complex driver working
-	 * directly with hardware).
-	 *
-	 * Note that we do not copy FCS into this buffer thus the
-	 * size is 1514 bytes.
-	 */
-	struct k_mutex tx_frame_buf_mutex;
-	struct k_mutex rx_frame_buf_mutex;
-	uint8_t *tx_frame_buf; /* Max MTU + ethernet header */
-	uint8_t *rx_frame_buf; /* Max MTU + ethernet header */
-#if defined(CONFIG_PINCTRL)
-	const struct pinctrl_dev_config *pincfg;
-#endif
-#if defined(CONFIG_ETH_MCUX_PHY_RESET)
-	const struct gpio_dt_spec int_gpio;
-	const struct gpio_dt_spec reset_gpio;
-#endif
-};
-
-/* Use ENET_FRAME_MAX_VLANFRAMELEN for VLAN frame size
- * Use ENET_FRAME_MAX_FRAMELEN for Ethernet frame size
- */
-#if defined(CONFIG_NET_VLAN)
-#if !defined(ENET_FRAME_MAX_VLANFRAMELEN)
-#define ENET_FRAME_MAX_VLANFRAMELEN (ENET_FRAME_MAX_FRAMELEN + 4)
-#endif
-#define ETH_MCUX_BUFFER_SIZE \
-	ROUND_UP(ENET_FRAME_MAX_VLANFRAMELEN, ENET_BUFF_ALIGNMENT)
-#else
-#define ETH_MCUX_BUFFER_SIZE \
-	ROUND_UP(ENET_FRAME_MAX_FRAMELEN, ENET_BUFF_ALIGNMENT)
-#endif /* CONFIG_NET_VLAN */
-
-#ifdef CONFIG_SOC_FAMILY_KINETIS
-#if defined(CONFIG_NET_POWER_MANAGEMENT)
-static void eth_mcux_phy_enter_reset(struct eth_context *context);
-void eth_mcux_phy_stop(struct eth_context *context);
-
-static int eth_mcux_device_pm_action(const struct device *dev,
-				     enum pm_device_action action)
-{
-	struct eth_context *eth_ctx = dev->data;
-	int ret = 0;
-
-	if (!device_is_ready(eth_ctx->clock_dev)) {
-		LOG_ERR("No CLOCK dev");
-
-		ret = -EIO;
-		goto out;
-	}
-
-	switch (action) {
-	case PM_DEVICE_ACTION_SUSPEND:
-		LOG_DBG("Suspending");
-
-		ret = net_if_suspend(eth_ctx->iface);
-		if (ret == -EBUSY) {
-			goto out;
-		}
-
-		eth_mcux_phy_enter_reset(eth_ctx);
-		eth_mcux_phy_stop(eth_ctx);
-
-		ENET_Reset(eth_ctx->base);
-		ENET_Deinit(eth_ctx->base);
-		clock_control_off(eth_ctx->clock_dev,
-			(clock_control_subsys_t)eth_ctx->clock);
-		break;
-	case PM_DEVICE_ACTION_RESUME:
-		LOG_DBG("Resuming");
-
-		clock_control_on(eth_ctx->clock_dev,
-			(clock_control_subsys_t)eth_ctx->clock);
-		eth_mcux_init(dev);
-		net_if_resume(eth_ctx->iface);
-		break;
-	default:
-		ret = -ENOTSUP;
-		break;
-	}
-
-out:
-
-	return ret;
-}
-#endif /* CONFIG_NET_POWER_MANAGEMENT */
-#endif /* CONFIG_SOC_FAMILY_KINETIS */
-
-#if ETH_MCUX_FIXED_LINK
-static void eth_mcux_get_phy_params(phy_duplex_t *p_phy_duplex,
-				    phy_speed_t *p_phy_speed)
-{
-	*p_phy_duplex = kPHY_HalfDuplex;
-#if ETH_MCUX_FIXED_LINK_FULL_DUPLEX
-	*p_phy_duplex = kPHY_FullDuplex;
-#endif
-
-	*p_phy_speed = kPHY_Speed10M;
-#if ETH_MCUX_FIXED_LINK_SPEED == 100
-	*p_phy_speed = kPHY_Speed100M;
-#endif
-}
-#else
-
-static void eth_mcux_decode_duplex_and_speed(uint32_t status,
-					     phy_duplex_t *p_phy_duplex,
-					     phy_speed_t *p_phy_speed)
-{
-	switch (status & PHY_CTL1_SPEEDUPLX_MASK) {
-	case PHY_CTL1_10FULLDUPLEX_MASK:
-		*p_phy_duplex = kPHY_FullDuplex;
-		*p_phy_speed = kPHY_Speed10M;
-		break;
-	case PHY_CTL1_100FULLDUPLEX_MASK:
-		*p_phy_duplex = kPHY_FullDuplex;
-		*p_phy_speed = kPHY_Speed100M;
-		break;
-	case PHY_CTL1_100HALFDUPLEX_MASK:
-		*p_phy_duplex = kPHY_HalfDuplex;
-		*p_phy_speed = kPHY_Speed100M;
-		break;
-	case PHY_CTL1_10HALFDUPLEX_MASK:
-		*p_phy_duplex = kPHY_HalfDuplex;
-		*p_phy_speed = kPHY_Speed10M;
-		break;
-	}
-}
-#endif /* ETH_MCUX_FIXED_LINK */
-
-static inline struct net_if *get_iface(struct eth_context *ctx)
-{
-	return ctx->iface;
-}
-
-static void eth_mcux_phy_enter_reset(struct eth_context *context)
-{
-	/* Reset the PHY. */
-#if !defined(CONFIG_ETH_MCUX_NO_PHY_SMI)
-	ENET_StartSMIWrite(context->base, context->phy_addr,
-			   PHY_BASICCONTROL_REG,
-			   kENET_MiiWriteValidFrame,
-			   PHY_BCTL_RESET_MASK);
-#endif
-	context->phy_state = eth_mcux_phy_state_reset;
-#if defined(CONFIG_ETH_MCUX_NO_PHY_SMI)
-	k_work_submit(&context->phy_work);
-#endif
-}
-
-static void eth_mcux_phy_start(struct eth_context *context)
-{
-#if defined(CONFIG_ETH_MCUX_PHY_EXTRA_DEBUG)
-	LOG_DBG("%s phy_state=%s", eth_name(context->base),
-		phy_state_name(context->phy_state));
-#endif
-
-	context->enabled = true;
-
-	switch (context->phy_state) {
-	case eth_mcux_phy_state_initial:
-		context->phy_handle->phyAddr = context->phy_addr;
-		ENET_ActiveRead(context->base);
-		/* Reset the PHY. */
-#if !defined(CONFIG_ETH_MCUX_NO_PHY_SMI)
-		ENET_StartSMIWrite(context->base, context->phy_addr,
-				   PHY_BASICCONTROL_REG,
-				   kENET_MiiWriteValidFrame,
-				   PHY_BCTL_RESET_MASK);
-#else
-		/*
-		 * With no SMI communication one needs to wait for
-		 * iface being up by the network core.
-		 */
-		k_work_submit(&context->phy_work);
-		break;
-#endif
-#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX)
-		context->phy_state = eth_mcux_phy_state_initial;
-#else
-		context->phy_state = eth_mcux_phy_state_reset;
-#endif
-		break;
-	case eth_mcux_phy_state_reset:
-		eth_mcux_phy_enter_reset(context);
-		break;
-	case eth_mcux_phy_state_autoneg:
-	case eth_mcux_phy_state_restart:
-	case eth_mcux_phy_state_read_status:
-	case eth_mcux_phy_state_read_duplex:
-	case eth_mcux_phy_state_wait:
-	case eth_mcux_phy_state_closing:
-		break;
-	}
-}
-
-void eth_mcux_phy_stop(struct eth_context *context)
-{
-#if defined(CONFIG_ETH_MCUX_PHY_EXTRA_DEBUG)
-	LOG_DBG("%s phy_state=%s", eth_name(context->base),
-		phy_state_name(context->phy_state));
-#endif
-
-	context->enabled = false;
-
-	switch (context->phy_state) {
-	case eth_mcux_phy_state_initial:
-	case eth_mcux_phy_state_reset:
-	case eth_mcux_phy_state_autoneg:
-	case eth_mcux_phy_state_restart:
-	case eth_mcux_phy_state_read_status:
-	case eth_mcux_phy_state_read_duplex:
-		/* Do nothing, let the current communication complete
-		 * then deal with shutdown.
-		 */
-		context->phy_state = eth_mcux_phy_state_closing;
-		break;
-	case eth_mcux_phy_state_wait:
-		k_work_cancel_delayable(&context->delayed_phy_work);
-		/* @todo, actually power down the PHY ? */
-		context->phy_state = eth_mcux_phy_state_initial;
-		break;
-	case eth_mcux_phy_state_closing:
-		/* We are already going down. */
-		break;
-	}
-}
-
-static void eth_mcux_phy_event(struct eth_context *context)
-{
-#if !(defined(CONFIG_ETH_MCUX_NO_PHY_SMI) && ETH_MCUX_FIXED_LINK)
-	uint32_t status;
-#endif
-	bool link_up;
-#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX)
-	status_t res;
-	uint16_t ctrl2;
-#endif
-	phy_duplex_t phy_duplex = kPHY_FullDuplex;
-	phy_speed_t phy_speed = kPHY_Speed100M;
-
-#if defined(CONFIG_ETH_MCUX_PHY_EXTRA_DEBUG)
-	LOG_DBG("%s phy_state=%s", eth_name(context->base),
-		phy_state_name(context->phy_state));
-#endif
-	switch (context->phy_state) {
-	case eth_mcux_phy_state_initial:
-#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX)
-		ENET_DisableInterrupts(context->base, ENET_EIR_MII_MASK);
-		res = PHY_Read(context->phy_handle, PHY_CONTROL2_REG, &ctrl2);
-		ENET_EnableInterrupts(context->base, ENET_EIR_MII_MASK);
-		if (res != kStatus_Success) {
-			LOG_WRN("Reading PHY reg failed (status 0x%x)", res);
-			k_work_submit(&context->phy_work);
-		} else {
-			ctrl2 |= PHY_CTL2_REFCLK_SELECT_MASK;
-			ENET_StartSMIWrite(context->base, context->phy_addr,
-					   PHY_CONTROL2_REG,
-					   kENET_MiiWriteValidFrame,
-					   ctrl2);
-		}
-		context->phy_state = eth_mcux_phy_state_reset;
-#endif
-#if defined(CONFIG_ETH_MCUX_NO_PHY_SMI)
-		/*
-		 * When the iface is available proceed with the eth link setup,
-		 * otherwise reschedule the eth_mcux_phy_event and check after
-		 * 1ms
-		 */
-		if (context->iface) {
-		       context->phy_state = eth_mcux_phy_state_reset;
-		}
-
-		k_work_reschedule(&context->delayed_phy_work, K_MSEC(1));
-#endif
-		break;
-	case eth_mcux_phy_state_closing:
-		if (context->enabled) {
-			eth_mcux_phy_enter_reset(context);
-		} else {
-			/* @todo, actually power down the PHY ? */
-			context->phy_state = eth_mcux_phy_state_initial;
-		}
-		break;
-	case eth_mcux_phy_state_reset:
-		/* Setup PHY autonegotiation. */
-#if !defined(CONFIG_ETH_MCUX_NO_PHY_SMI)
-		ENET_StartSMIWrite(context->base, context->phy_addr,
-				   PHY_AUTONEG_ADVERTISE_REG,
-				   kENET_MiiWriteValidFrame,
-				   (PHY_100BASETX_FULLDUPLEX_MASK |
-				    PHY_100BASETX_HALFDUPLEX_MASK |
-				    PHY_10BASETX_FULLDUPLEX_MASK |
-				    PHY_10BASETX_HALFDUPLEX_MASK |
-					PHY_IEEE802_3_SELECTOR_MASK));
-#endif
-		context->phy_state = eth_mcux_phy_state_autoneg;
-#if defined(CONFIG_ETH_MCUX_NO_PHY_SMI)
-		k_work_submit(&context->phy_work);
-#endif
-		break;
-	case eth_mcux_phy_state_autoneg:
-#if !defined(CONFIG_ETH_MCUX_NO_PHY_SMI)
-		/* Setup PHY autonegotiation. */
-		ENET_StartSMIWrite(context->base, context->phy_addr,
-				   PHY_BASICCONTROL_REG,
-				   kENET_MiiWriteValidFrame,
-				   (PHY_BCTL_AUTONEG_MASK |
-				    PHY_BCTL_RESTART_AUTONEG_MASK));
-#endif
-		context->phy_state = eth_mcux_phy_state_restart;
-#if defined(CONFIG_ETH_MCUX_NO_PHY_SMI)
-		k_work_submit(&context->phy_work);
-#endif
-		break;
-	case eth_mcux_phy_state_wait:
-	case eth_mcux_phy_state_restart:
-		/* Start reading the PHY basic status. */
-#if !defined(CONFIG_ETH_MCUX_NO_PHY_SMI)
-		ENET_StartSMIRead(context->base, context->phy_addr,
-				  PHY_BASICSTATUS_REG,
-				  kENET_MiiReadValidFrame);
-#endif
-		context->phy_state = eth_mcux_phy_state_read_status;
-#if defined(CONFIG_ETH_MCUX_NO_PHY_SMI)
-		k_work_submit(&context->phy_work);
-#endif
-		break;
-	case eth_mcux_phy_state_read_status:
-		/* PHY Basic status is available. */
-#if defined(CONFIG_ETH_MCUX_NO_PHY_SMI) && ETH_MCUX_FIXED_LINK
-		link_up = true;
-#else
-		status = ENET_ReadSMIData(context->base);
-		link_up =  status & PHY_BSTATUS_LINKSTATUS_MASK;
-#endif
-		if (link_up && !context->link_up && context->iface != NULL) {
-			/* Start reading the PHY control register. */
-#if !defined(CONFIG_ETH_MCUX_NO_PHY_SMI)
-			ENET_StartSMIRead(context->base, context->phy_addr,
-					  PHY_CONTROL1_REG,
-					  kENET_MiiReadValidFrame);
-#endif
-			context->link_up = link_up;
-			context->phy_state = eth_mcux_phy_state_read_duplex;
-			net_eth_carrier_on(context->iface);
-			k_msleep(1);
-#if defined(CONFIG_ETH_MCUX_NO_PHY_SMI)
-			k_work_submit(&context->phy_work);
-#endif
-		} else if (!link_up && context->link_up && context->iface != NULL) {
-			LOG_INF("%s link down", eth_name(context->base));
-			context->link_up = link_up;
-			k_work_reschedule(&context->delayed_phy_work,
-					  K_MSEC(CONFIG_ETH_MCUX_PHY_TICK_MS));
-			context->phy_state = eth_mcux_phy_state_wait;
-			net_eth_carrier_off(context->iface);
-		} else {
-			k_work_reschedule(&context->delayed_phy_work,
-					  K_MSEC(CONFIG_ETH_MCUX_PHY_TICK_MS));
-			context->phy_state = eth_mcux_phy_state_wait;
-		}
-
-		break;
-	case eth_mcux_phy_state_read_duplex:
-		/* PHY control register is available. */
-#if defined(CONFIG_ETH_MCUX_NO_PHY_SMI) && ETH_MCUX_FIXED_LINK
-		eth_mcux_get_phy_params(&phy_duplex, &phy_speed);
-		LOG_INF("%s - Fixed Link", eth_name(context->base));
-#else
-		status = ENET_ReadSMIData(context->base);
-		eth_mcux_decode_duplex_and_speed(status,
-						 &phy_duplex,
-						 &phy_speed);
-#endif
-		if (phy_speed != context->phy_speed ||
-		    phy_duplex != context->phy_duplex) {
-			context->phy_speed = phy_speed;
-			context->phy_duplex = phy_duplex;
-			ENET_SetMII(context->base,
-				    (enet_mii_speed_t) phy_speed,
-				    (enet_mii_duplex_t) phy_duplex);
-		}
-
-		LOG_INF("%s enabled %sM %s-duplex mode.",
-			eth_name(context->base),
-			(phy_speed ? "100" : "10"),
-			(phy_duplex ? "full" : "half"));
-		k_work_reschedule(&context->delayed_phy_work,
-				  K_MSEC(CONFIG_ETH_MCUX_PHY_TICK_MS));
-		context->phy_state = eth_mcux_phy_state_wait;
-		break;
-	}
-}
-
-static void eth_mcux_phy_work(struct k_work *item)
-{
-	struct eth_context *context =
-		CONTAINER_OF(item, struct eth_context, phy_work);
-
-	eth_mcux_phy_event(context);
-}
-
-static void eth_mcux_delayed_phy_work(struct k_work *item)
-{
-	struct k_work_delayable *dwork = k_work_delayable_from_work(item);
-	struct eth_context *context =
-		CONTAINER_OF(dwork, struct eth_context, delayed_phy_work);
-
-	eth_mcux_phy_event(context);
-}
-
-static void eth_mcux_phy_setup(struct eth_context *context)
-{
-#if defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX)
-	status_t res;
-	uint16_t oms_override;
-
-	/* Disable MII interrupts to prevent triggering PHY events. */
-	ENET_DisableInterrupts(context->base, ENET_EIR_MII_MASK);
-
-	res = PHY_Read(context->phy_handle,
-		       PHY_OMS_OVERRIDE_REG, &oms_override);
-	if (res != kStatus_Success) {
-		LOG_WRN("Reading PHY reg failed (status 0x%x)", res);
-	} else {
-		/* Based on strap-in pins the PHY can be in factory test mode.
-		 * Force normal operation.
-		 */
-		oms_override &= ~PHY_OMS_FACTORY_MODE_MASK;
-
-		/* Prevent PHY entering NAND Tree mode override. */
-		if (oms_override & PHY_OMS_NANDTREE_MASK) {
-			oms_override &= ~PHY_OMS_NANDTREE_MASK;
-		}
-
-		res = PHY_Write(context->phy_handle,
-				PHY_OMS_OVERRIDE_REG, oms_override);
-		if (res != kStatus_Success) {
-			LOG_WRN("Writing PHY reg failed (status 0x%x)", res);
-		}
-	}
-
-	ENET_EnableInterrupts(context->base, ENET_EIR_MII_MASK);
-#endif
-}
-
-#if defined(CONFIG_PTP_CLOCK_MCUX)
-
-static bool eth_get_ptp_data(struct net_if *iface, struct net_pkt *pkt)
-{
-	int eth_hlen;
-
-	if (ntohs(NET_ETH_HDR(pkt)->type) != NET_ETH_PTYPE_PTP) {
-		return false;
-	}
-
-	eth_hlen = sizeof(struct net_eth_hdr);
-
-	net_pkt_set_priority(pkt, NET_PRIORITY_CA);
-
-	return true;
-}
-#endif /* CONFIG_PTP_CLOCK_MCUX */
-
-static int eth_tx(const struct device *dev, struct net_pkt *pkt)
-{
-	struct eth_context *context = dev->data;
-	uint16_t total_len = net_pkt_get_len(pkt);
-	status_t status;
-
-#if defined(CONFIG_PTP_CLOCK_MCUX)
-	bool timestamped_frame;
-#endif
-
-	/* Wait for a TX buffer descriptor to be available */
-	k_sem_take(&context->tx_buf_sem, K_FOREVER);
-
-	k_mutex_lock(&context->tx_frame_buf_mutex, K_FOREVER);
-
-	if (net_pkt_read(pkt, context->tx_frame_buf, total_len)) {
-		k_mutex_unlock(&context->tx_frame_buf_mutex);
-		return -EIO;
-	}
-
-
-#if defined(CONFIG_PTP_CLOCK_MCUX)
-	timestamped_frame = eth_get_ptp_data(net_pkt_iface(pkt), pkt);
-	if (timestamped_frame) {
-		status = ENET_SendFrame(context->base, &context->enet_handle,
-					  context->tx_frame_buf, total_len, RING_ID, true, pkt);
-		if (!status) {
-			net_pkt_ref(pkt);
-			/*
-			 * Network stack will modify the packet upon return,
-			 * so wait for the packet to be timestamped,
-			 * which will occur within the TX ISR, before
-			 * returning
-			 */
-			k_sem_take(&context->ptp_ts_sem, K_FOREVER);
-		}
-
-	} else
-#endif
-	{
-		status = ENET_SendFrame(context->base, &context->enet_handle,
-					context->tx_frame_buf, total_len, RING_ID, false, NULL);
-	}
-
-	if (status) {
-		LOG_ERR("ENET_SendFrame error: %d", (int)status);
-		k_mutex_unlock(&context->tx_frame_buf_mutex);
-		ENET_ReclaimTxDescriptor(context->base,
-					&context->enet_handle, RING_ID);
-		return -1;
-	}
-
-	k_mutex_unlock(&context->tx_frame_buf_mutex);
-
-	return 0;
-}
-
-static int eth_rx(struct eth_context *context)
-{
-	uint32_t frame_length = 0U;
-	struct net_if *iface;
-	struct net_pkt *pkt;
-	status_t status;
-	uint32_t ts;
-
-#if defined(CONFIG_PTP_CLOCK_MCUX)
-	enet_ptp_time_t ptpTimeData;
-#endif
-
-	status = ENET_GetRxFrameSize(&context->enet_handle,
-				     (uint32_t *)&frame_length, RING_ID);
-	if (status == kStatus_ENET_RxFrameEmpty) {
-		return 0;
-	} else if (status == kStatus_ENET_RxFrameError) {
-		enet_data_error_stats_t error_stats;
-
-		LOG_ERR("ENET_GetRxFrameSize return: %d", (int)status);
-
-		ENET_GetRxErrBeforeReadFrame(&context->enet_handle,
-					     &error_stats, RING_ID);
-		goto flush;
-	}
-
-	if (frame_length > NET_ETH_MAX_FRAME_SIZE) {
-		LOG_ERR("frame too large (%d)", frame_length);
-		goto flush;
-	}
-
-	/* Using root iface. It will be updated in net_recv_data() */
-	pkt = net_pkt_rx_alloc_with_buffer(context->iface, frame_length,
-					   AF_UNSPEC, 0, K_NO_WAIT);
-	if (!pkt) {
-		goto flush;
-	}
-
-	/* in case multiply thread access
-	 * we need to protect it with mutex.
-	 */
-	k_mutex_lock(&context->rx_frame_buf_mutex, K_FOREVER);
-
-	status = ENET_ReadFrame(context->base, &context->enet_handle,
-				context->rx_frame_buf, frame_length, RING_ID, &ts);
-	if (status) {
-		LOG_ERR("ENET_ReadFrame failed: %d", (int)status);
-		net_pkt_unref(pkt);
-
-		k_mutex_unlock(&context->rx_frame_buf_mutex);
-		goto error;
-	}
-
-	if (net_pkt_write(pkt, context->rx_frame_buf, frame_length)) {
-		LOG_ERR("Unable to write frame into the pkt");
-		net_pkt_unref(pkt);
-		k_mutex_unlock(&context->rx_frame_buf_mutex);
-		goto error;
-	}
-
-	k_mutex_unlock(&context->rx_frame_buf_mutex);
-
-	/*
-	 * Use MAC timestamp
-	 */
-#if defined(CONFIG_PTP_CLOCK_MCUX)
-	k_mutex_lock(&context->ptp_mutex, K_FOREVER);
-	if (eth_get_ptp_data(get_iface(context), pkt)) {
-		ENET_Ptp1588GetTimer(context->base, &context->enet_handle,
-					&ptpTimeData);
-		/* If latest timestamp reloads after getting from Rx BD,
-		 * then second - 1 to make sure the actual Rx timestamp is
-		 * accurate
-		 */
-		if (ptpTimeData.nanosecond < ts) {
-			ptpTimeData.second--;
-		}
-
-		pkt->timestamp.nanosecond = ts;
-		pkt->timestamp.second = ptpTimeData.second;
-	} else {
-		/* Invalid value. */
-		pkt->timestamp.nanosecond = UINT32_MAX;
-		pkt->timestamp.second = UINT64_MAX;
-	}
-	k_mutex_unlock(&context->ptp_mutex);
-#endif /* CONFIG_PTP_CLOCK_MCUX */
-
-	iface = get_iface(context);
-#if defined(CONFIG_NET_DSA)
-	iface = dsa_net_recv(iface, &pkt);
-#endif
-	if (net_recv_data(iface, pkt) < 0) {
-		net_pkt_unref(pkt);
-		goto error;
-	}
-
-	return 1;
-flush:
-	/* Flush the current read buffer.  This operation can
-	 * only report failure if there is no frame to flush,
-	 * which cannot happen in this context.
-	 */
-	status = ENET_ReadFrame(context->base, &context->enet_handle, NULL,
-					0, RING_ID, NULL);
-	__ASSERT_NO_MSG(status == kStatus_Success);
-error:
-	eth_stats_update_errors_rx(get_iface(context));
-	return -EIO;
-}
-
-#if defined(CONFIG_PTP_CLOCK_MCUX) && defined(CONFIG_NET_L2_PTP)
-static inline void ts_register_tx_event(struct eth_context *context,
-					 enet_frame_info_t *frameinfo)
-{
-	struct net_pkt *pkt;
-
-	pkt = frameinfo->context;
-	if (pkt && atomic_get(&pkt->atomic_ref) > 0) {
-		if (eth_get_ptp_data(net_pkt_iface(pkt), pkt)) {
-			if (frameinfo->isTsAvail) {
-				k_mutex_lock(&context->ptp_mutex, K_FOREVER);
-
-				pkt->timestamp.nanosecond =
-					frameinfo->timeStamp.nanosecond;
-				pkt->timestamp.second =
-					frameinfo->timeStamp.second;
-
-				net_if_add_tx_timestamp(pkt);
-				k_sem_give(&context->ptp_ts_sem);
-				k_mutex_unlock(&context->ptp_mutex);
-			}
-		}
-
-		net_pkt_unref(pkt);
-	} else {
-		if (IS_ENABLED(CONFIG_ETH_MCUX_PHY_EXTRA_DEBUG) && pkt) {
-			LOG_ERR("pkt %p already freed", pkt);
-		}
-	}
-
-}
-#endif /* CONFIG_PTP_CLOCK_MCUX && CONFIG_NET_L2_PTP */
-
-static void eth_callback(ENET_Type *base, enet_handle_t *handle,
-#if FSL_FEATURE_ENET_QUEUE > 1
-			 uint32_t ringId,
-#endif /* FSL_FEATURE_ENET_QUEUE > 1 */
-			 enet_event_t event, enet_frame_info_t *frameinfo, void *param)
-{
-	struct eth_context *context = param;
-
-	switch (event) {
-	case kENET_RxEvent:
-		k_sem_give(&context->rx_thread_sem);
-		break;
-	case kENET_TxEvent:
-#if defined(CONFIG_PTP_CLOCK_MCUX) && defined(CONFIG_NET_L2_PTP)
-		/* Register event */
-		ts_register_tx_event(context, frameinfo);
-#endif /* CONFIG_PTP_CLOCK_MCUX && CONFIG_NET_L2_PTP */
-		/* Free the TX buffer. */
-		k_sem_give(&context->tx_buf_sem);
-		break;
-	case kENET_ErrEvent:
-		/* Error event: BABR/BABT/EBERR/LC/RL/UN/PLR.  */
-		break;
-	case kENET_WakeUpEvent:
-		/* Wake up from sleep mode event. */
-		break;
-	case kENET_TimeStampEvent:
-		/* Time stamp event.  */
-		/* Reset periodic timer to default value. */
-		context->base->ATPER = NSEC_PER_SEC;
-		break;
-	case kENET_TimeStampAvailEvent:
-		/* Time stamp available event.  */
-		break;
-	}
-}
-
-static void eth_rx_thread(void *arg1, void *unused1, void *unused2)
-{
-	struct eth_context *context = (struct eth_context *)arg1;
-
-	while (1) {
-		if (k_sem_take(&context->rx_thread_sem, K_FOREVER) == 0) {
-			while (eth_rx(context) == 1) {
-				;
-			}
-			/* enable the IRQ for RX */
-			ENET_EnableInterrupts(context->base,
-			  kENET_RxFrameInterrupt | kENET_RxBufferInterrupt);
-		}
-	}
-}
-
-#if defined(CONFIG_ETH_MCUX_PHY_RESET)
-static int eth_phy_reset(const struct device *dev)
-{
-	int err;
-	struct eth_context *context = dev->data;
-
-	/* pull up the ENET_INT before RESET. */
-	err =  gpio_pin_configure_dt(&context->int_gpio, GPIO_OUTPUT_ACTIVE);
-	if (err) {
-		return err;
-	}
-	return gpio_pin_configure_dt(&context->reset_gpio, GPIO_OUTPUT_INACTIVE);
-}
-
-static int eth_phy_init(const struct device *dev)
-{
-	struct eth_context *context = dev->data;
-
-	/* RESET PHY chip. */
-	k_busy_wait(USEC_PER_MSEC * 500);
-	return gpio_pin_set_dt(&context->reset_gpio, 1);
-}
-#endif
-
-static void eth_mcux_init(const struct device *dev)
-{
-	struct eth_context *context = dev->data;
-	const enet_buffer_config_t *buffer_config = dev->config;
-	enet_config_t enet_config;
-	uint32_t sys_clock;
-#if defined(CONFIG_PTP_CLOCK_MCUX)
-	uint8_t ptp_multicast[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
-	uint8_t ptp_peer_multicast[6] = { 0x01, 0x80, 0xC2, 0x00, 0x00, 0x0E };
-#endif
-#if defined(CONFIG_MDNS_RESPONDER) || defined(CONFIG_MDNS_RESOLVER)
-	/* standard multicast MAC address */
-	uint8_t mdns_multicast[6] = { 0x01, 0x00, 0x5E, 0x00, 0x00, 0xFB };
-#endif
-
-	context->phy_state = eth_mcux_phy_state_initial;
-	context->phy_handle->ops = &phyksz8081_ops;
-
-#if defined(CONFIG_SOC_SERIES_IMXRT10XX)
-#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet))
-	sys_clock = CLOCK_GetFreq(kCLOCK_IpgClk);
-#endif
-#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet2))
-	sys_clock = CLOCK_GetFreq(kCLOCK_EnetPll1Clk);
-#endif
-#elif defined(CONFIG_SOC_SERIES_IMXRT11XX)
-	sys_clock = CLOCK_GetRootClockFreq(kCLOCK_Root_Bus);
-#else
-	sys_clock = CLOCK_GetFreq(kCLOCK_CoreSysClk);
-#endif
-
-	ENET_GetDefaultConfig(&enet_config);
-	enet_config.interrupt |= kENET_RxFrameInterrupt;
-	enet_config.interrupt |= kENET_TxFrameInterrupt;
-#if !defined(CONFIG_ETH_MCUX_NO_PHY_SMI)
-	enet_config.interrupt |= kENET_MiiInterrupt;
-#endif
-	enet_config.miiMode = kENET_RmiiMode;
-	enet_config.callback = eth_callback;
-	enet_config.userData = context;
-
-	if (IS_ENABLED(CONFIG_ETH_MCUX_PROMISCUOUS_MODE)) {
-		enet_config.macSpecialConfig |= kENET_ControlPromiscuousEnable;
-	}
-
-	if (IS_ENABLED(CONFIG_NET_VLAN)) {
-		enet_config.macSpecialConfig |= kENET_ControlVLANTagEnable;
-	}
-
-	if (IS_ENABLED(CONFIG_ETH_MCUX_HW_ACCELERATION)) {
-		enet_config.txAccelerConfig |=
-			kENET_TxAccelIpCheckEnabled |
-			kENET_TxAccelProtoCheckEnabled;
-		enet_config.rxAccelerConfig |=
-			kENET_RxAccelIpCheckEnabled |
-			kENET_RxAccelProtoCheckEnabled;
-	}
-
-	ENET_Init(context->base,
-		  &context->enet_handle,
-		  &enet_config,
-		  buffer_config,
-		  context->mac_addr,
-		  sys_clock);
-
-#if defined(CONFIG_PTP_CLOCK_MCUX)
-	ENET_AddMulticastGroup(context->base, ptp_multicast);
-	ENET_AddMulticastGroup(context->base, ptp_peer_multicast);
-
-	/* only for ERRATA_2579 */
-	context->ptp_config.channel = kENET_PtpTimerChannel3;
-	context->ptp_config.ptp1588ClockSrc_Hz =
-					CONFIG_ETH_MCUX_PTP_CLOCK_SRC_HZ;
-	context->clk_ratio = 1.0;
-
-	ENET_Ptp1588SetChannelMode(context->base, kENET_PtpTimerChannel3,
-			kENET_PtpChannelPulseHighonCompare, true);
-	ENET_Ptp1588Configure(context->base, &context->enet_handle,
-			      &context->ptp_config);
-#endif
-
-#if defined(CONFIG_MDNS_RESPONDER) || defined(CONFIG_MDNS_RESOLVER)
-	ENET_AddMulticastGroup(context->base, mdns_multicast);
-#endif
-
-#if !defined(CONFIG_ETH_MCUX_NO_PHY_SMI)
-	ENET_SetSMI(context->base, sys_clock, false);
-#endif
-
-	/* handle PHY setup after SMI initialization */
-	eth_mcux_phy_setup(context);
-
-#if defined(CONFIG_PTP_CLOCK_MCUX)
-	/* Enable reclaim of tx descriptors that will have the tx timestamp */
-	ENET_SetTxReclaim(&context->enet_handle, true, 0);
-#endif
-
-	eth_mcux_phy_start(context);
-}
-
-static int eth_init(const struct device *dev)
-{
-	struct eth_context *context = dev->data;
-#if defined(CONFIG_PINCTRL)
-	int err;
-
-	err = pinctrl_apply_state(context->pincfg, PINCTRL_STATE_DEFAULT);
-	if (err) {
-		return err;
-	}
-#endif /* CONFIG_PINCTRL */
-
-#if defined(CONFIG_NET_POWER_MANAGEMENT)
-	const uint32_t inst = ENET_GetInstance(context->base);
-
-	context->clock = enet_clocks[inst];
-#endif
-
-#if defined(CONFIG_ETH_MCUX_PHY_RESET)
-	eth_phy_reset(dev);
-	eth_phy_init(dev);
-#endif
-
-#if defined(CONFIG_PTP_CLOCK_MCUX)
-	k_mutex_init(&context->ptp_mutex);
-	k_sem_init(&context->ptp_ts_sem, 0, 1);
-#endif
-	k_mutex_init(&context->rx_frame_buf_mutex);
-	k_mutex_init(&context->tx_frame_buf_mutex);
-
-	k_sem_init(&context->rx_thread_sem, 0, CONFIG_ETH_MCUX_RX_BUFFERS);
-	k_sem_init(&context->tx_buf_sem,
-		   CONFIG_ETH_MCUX_TX_BUFFERS, CONFIG_ETH_MCUX_TX_BUFFERS);
-	k_work_init(&context->phy_work, eth_mcux_phy_work);
-	k_work_init_delayable(&context->delayed_phy_work,
-			      eth_mcux_delayed_phy_work);
-
-	/* Start interruption-poll thread */
-	k_thread_create(&context->rx_thread, context->rx_thread_stack,
-			K_KERNEL_STACK_SIZEOF(context->rx_thread_stack),
-			eth_rx_thread, (void *) context, NULL, NULL,
-			K_PRIO_COOP(2),
-			0, K_NO_WAIT);
-	k_thread_name_set(&context->rx_thread, "mcux_eth_rx");
-	if (context->generate_mac) {
-		context->generate_mac(context->mac_addr);
-	}
-
-	eth_mcux_init(dev);
-
-	LOG_DBG("%s MAC %02x:%02x:%02x:%02x:%02x:%02x",
-		dev->name,
-		context->mac_addr[0], context->mac_addr[1],
-		context->mac_addr[2], context->mac_addr[3],
-		context->mac_addr[4], context->mac_addr[5]);
-
-	return 0;
-}
-
-static void eth_iface_init(struct net_if *iface)
-{
-	const struct device *dev = net_if_get_device(iface);
-	struct eth_context *context = dev->data;
-
-	net_if_set_link_addr(iface, context->mac_addr,
-			     sizeof(context->mac_addr),
-			     NET_LINK_ETHERNET);
-
-	if (context->iface == NULL) {
-		context->iface = iface;
-	}
-
-#if defined(CONFIG_NET_DSA)
-	dsa_register_master_tx(iface, &eth_tx);
-#endif
-	ethernet_init(iface);
-	net_if_carrier_off(iface);
-
-	context->config_func();
-}
-
-static enum ethernet_hw_caps eth_mcux_get_capabilities(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-	return ETHERNET_LINK_10BASE_T |
-		ETHERNET_HW_FILTERING |
-#if defined(CONFIG_NET_VLAN)
-		ETHERNET_HW_VLAN |
-#endif
-#if defined(CONFIG_PTP_CLOCK_MCUX)
-		ETHERNET_PTP |
-#endif
-#if defined(CONFIG_NET_DSA)
-		ETHERNET_DSA_MASTER_PORT |
-#endif
-#if defined(CONFIG_ETH_MCUX_HW_ACCELERATION)
-		ETHERNET_HW_TX_CHKSUM_OFFLOAD |
-		ETHERNET_HW_RX_CHKSUM_OFFLOAD |
-#endif
-		ETHERNET_AUTO_NEGOTIATION_SET |
-		ETHERNET_LINK_100BASE_T;
-}
-
-static int eth_mcux_set_config(const struct device *dev,
-			       enum ethernet_config_type type,
-			       const struct ethernet_config *config)
-{
-	struct eth_context *context = dev->data;
-
-	switch (type) {
-	case ETHERNET_CONFIG_TYPE_MAC_ADDRESS:
-		memcpy(context->mac_addr,
-		       config->mac_address.addr,
-		       sizeof(context->mac_addr));
-		ENET_SetMacAddr(context->base, context->mac_addr);
-		net_if_set_link_addr(context->iface, context->mac_addr,
-				     sizeof(context->mac_addr),
-				     NET_LINK_ETHERNET);
-		LOG_DBG("%s MAC set to %02x:%02x:%02x:%02x:%02x:%02x",
-			dev->name,
-			context->mac_addr[0], context->mac_addr[1],
-			context->mac_addr[2], context->mac_addr[3],
-			context->mac_addr[4], context->mac_addr[5]);
-		return 0;
-	case ETHERNET_CONFIG_TYPE_FILTER:
-		/* The ENET driver does not modify the address buffer but the API is not const */
-		if (config->filter.set) {
-			ENET_AddMulticastGroup(context->base,
-					       (uint8_t *)config->filter.mac_address.addr);
-		} else {
-			ENET_LeaveMulticastGroup(context->base,
-						 (uint8_t *)config->filter.mac_address.addr);
-		}
-		return 0;
-	default:
-		break;
-	}
-
-	return -ENOTSUP;
-}
-
-#if defined(CONFIG_PTP_CLOCK_MCUX)
-static const struct device *eth_mcux_get_ptp_clock(const struct device *dev)
-{
-	struct eth_context *context = dev->data;
-
-	return context->ptp_clock;
-}
-#endif
-
-static const struct ethernet_api api_funcs = {
-	.iface_api.init		= eth_iface_init,
-#if defined(CONFIG_PTP_CLOCK_MCUX)
-	.get_ptp_clock		= eth_mcux_get_ptp_clock,
-#endif
-	.get_capabilities	= eth_mcux_get_capabilities,
-	.set_config		= eth_mcux_set_config,
-#if defined(CONFIG_NET_DSA)
-	.send                   = dsa_tx,
-#else
-	.send			= eth_tx,
-#endif
-};
-
-#if defined(CONFIG_PTP_CLOCK_MCUX)
-static void eth_mcux_ptp_isr(const struct device *dev)
-{
-	struct eth_context *context = dev->data;
-	unsigned int irq_lock_key = irq_lock();
-	enet_ptp_timer_channel_t channel;
-
-	/* clear channel */
-	for (channel = kENET_PtpTimerChannel1; channel <= kENET_PtpTimerChannel4; channel++) {
-		if (ENET_Ptp1588GetChannelStatus(context->base, channel)) {
-			ENET_Ptp1588ClearChannelStatus(context->base, channel);
-		}
-	}
-	ENET_TimeStampIRQHandler(context->base, &context->enet_handle);
-	irq_unlock(irq_lock_key);
-}
-#endif
-
-#if DT_INST_IRQ_HAS_NAME(0, common) || DT_INST_IRQ_HAS_NAME(1, common)
-static void eth_mcux_common_isr(const struct device *dev)
-{
-	struct eth_context *context = dev->data;
-	uint32_t EIR = ENET_GetInterruptStatus(context->base);
-	unsigned int irq_lock_key = irq_lock();
-
-	if (EIR & (kENET_RxBufferInterrupt | kENET_RxFrameInterrupt)) {
-		/* disable the IRQ for RX */
-		context->rx_irq_num++;
-#if FSL_FEATURE_ENET_QUEUE > 1
-		/* Only use ring 0 in this driver */
-		ENET_ReceiveIRQHandler(context->base, &context->enet_handle, 0);
-#else
-		ENET_ReceiveIRQHandler(context->base, &context->enet_handle);
-#endif
-		ENET_DisableInterrupts(context->base, kENET_RxFrameInterrupt |
-			kENET_RxBufferInterrupt);
-	}
-
-	if (EIR & kENET_TxFrameInterrupt) {
-#if FSL_FEATURE_ENET_QUEUE > 1
-		ENET_TransmitIRQHandler(context->base, &context->enet_handle, 0);
-#else
-		ENET_TransmitIRQHandler(context->base, &context->enet_handle);
-#endif
-	}
-
-	if (EIR | kENET_TxBufferInterrupt) {
-		ENET_ClearInterruptStatus(context->base, kENET_TxBufferInterrupt);
-		ENET_DisableInterrupts(context->base, kENET_TxBufferInterrupt);
-	}
-
-	if (EIR & ENET_EIR_MII_MASK) {
-		k_work_submit(&context->phy_work);
-		ENET_ClearInterruptStatus(context->base, kENET_MiiInterrupt);
-	}
-#if defined(CONFIG_PTP_CLOCK_MCUX)
-	if (EIR & ENET_TS_INTERRUPT) {
-		ENET_TimeStampIRQHandler(context->base, &context->enet_handle);
-	}
-#endif
-	irq_unlock(irq_lock_key);
-}
-#endif
-
-#if DT_INST_IRQ_HAS_NAME(0, rx) || DT_INST_IRQ_HAS_NAME(1, rx)
-static void eth_mcux_rx_isr(const struct device *dev)
-{
-	struct eth_context *context = dev->data;
-
-	ENET_DisableInterrupts(context->base, kENET_RxFrameInterrupt | kENET_RxBufferInterrupt);
-	ENET_ReceiveIRQHandler(context->base, &context->enet_handle);
-}
-#endif
-
-#if DT_INST_IRQ_HAS_NAME(0, tx) || DT_INST_IRQ_HAS_NAME(1, tx)
-static void eth_mcux_tx_isr(const struct device *dev)
-{
-	struct eth_context *context = dev->data;
-#if FSL_FEATURE_ENET_QUEUE > 1
-	ENET_TransmitIRQHandler(context->base, &context->enet_handle, 0);
-#else
-	ENET_TransmitIRQHandler(context->base, &context->enet_handle);
-#endif
-}
-#endif
-
-#if DT_INST_IRQ_HAS_NAME(0, err) || DT_INST_IRQ_HAS_NAME(1, err)
-static void eth_mcux_err_isr(const struct device *dev)
-{
-	struct eth_context *context = dev->data;
-	uint32_t pending = ENET_GetInterruptStatus(context->base);
-
-	if (pending & ENET_EIR_MII_MASK) {
-		k_work_submit(&context->phy_work);
-		ENET_ClearInterruptStatus(context->base, kENET_MiiInterrupt);
-	}
-}
-#endif
-
-#if defined(CONFIG_SOC_SERIES_IMXRT10XX)
-#define ETH_MCUX_UNIQUE_ID	(OCOTP->CFG1 ^ OCOTP->CFG2)
-#elif defined(CONFIG_SOC_SERIES_IMXRT11XX)
-#define ETH_MCUX_UNIQUE_ID	(OCOTP->FUSEN[40].FUSE)
-#elif defined(CONFIG_SOC_SERIES_KINETIS_K6X)
-#define ETH_MCUX_UNIQUE_ID	(SIM->UIDH ^ SIM->UIDMH ^ SIM->UIDML ^ SIM->UIDL)
-#else
-#error "Unsupported SOC"
-#endif
-
-#define ETH_MCUX_NONE
-
-#define ETH_MCUX_IRQ_INIT(n, name)					\
-	do {								\
-		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, name, irq),		\
-			    DT_INST_IRQ_BY_NAME(n, name, priority),	\
-			    eth_mcux_##name##_isr,			\
-			    DEVICE_DT_INST_GET(n),			\
-			    0);						\
-		irq_enable(DT_INST_IRQ_BY_NAME(n, name, irq));		\
-	} while (false)
-
-#define ETH_MCUX_IRQ(n, name)						\
-	COND_CODE_1(DT_INST_IRQ_HAS_NAME(n, name),			\
-		    (ETH_MCUX_IRQ_INIT(n, name)),			\
-		    (ETH_MCUX_NONE))
-
-#if defined(CONFIG_PTP_CLOCK_MCUX)
-#define PTP_INST_NODEID(n) DT_INST_CHILD(n, ptp)
-
-#define ETH_MCUX_IRQ_PTP_INIT(n)							\
-	do {										\
-		IRQ_CONNECT(DT_IRQ_BY_NAME(PTP_INST_NODEID(n), ieee1588_tmr, irq),	\
-			    DT_IRQ_BY_NAME(PTP_INST_NODEID(n), ieee1588_tmr, priority),	\
-			    eth_mcux_ptp_isr,						\
-			    DEVICE_DT_INST_GET(n),					\
-			    0);								\
-		irq_enable(DT_IRQ_BY_NAME(PTP_INST_NODEID(n), ieee1588_tmr, irq));	\
-	} while (false)
-
-#define ETH_MCUX_IRQ_PTP(n)						\
-	COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(PTP_INST_NODEID(n)),	\
-		    (ETH_MCUX_IRQ_PTP_INIT(n)),				\
-		    (ETH_MCUX_NONE))
-
-#define ETH_MCUX_PTP_FRAMEINFO_ARRAY(n)					\
-	static enet_frame_info_t					\
-		eth##n##_tx_frameinfo_array[CONFIG_ETH_MCUX_TX_BUFFERS];
-
-#define ETH_MCUX_PTP_FRAMEINFO(n)					\
-	.txFrameInfo = eth##n##_tx_frameinfo_array,
-#else
-#define ETH_MCUX_IRQ_PTP(n)
-
-#define ETH_MCUX_PTP_FRAMEINFO_ARRAY(n)
-
-#define ETH_MCUX_PTP_FRAMEINFO(n)					\
-	.txFrameInfo = NULL,
-#endif
-
-#define ETH_MCUX_GENERATE_MAC_RANDOM(n)					\
-	static void generate_eth##n##_mac(uint8_t *mac_addr)		\
-	{								\
-		gen_random_mac(mac_addr,				\
-			       FREESCALE_OUI_B0,			\
-			       FREESCALE_OUI_B1,			\
-			       FREESCALE_OUI_B2);			\
-	}
-
-#define ETH_MCUX_GENERATE_MAC_UNIQUE(n)					\
-	static void generate_eth##n##_mac(uint8_t *mac_addr)		\
-	{								\
-		uint32_t id = ETH_MCUX_UNIQUE_ID;			\
-									\
-		mac_addr[0] = FREESCALE_OUI_B0;				\
-		mac_addr[0] |= 0x02; /* force LAA bit */		\
-		mac_addr[1] = FREESCALE_OUI_B1;				\
-		mac_addr[2] = FREESCALE_OUI_B2;				\
-		mac_addr[3] = id >> 8;					\
-		mac_addr[4] = id >> 16;					\
-		mac_addr[5] = id >> 0;					\
-		mac_addr[5] += n;					\
-	}
-
-#define ETH_MCUX_GENERATE_MAC(n)					\
-	COND_CODE_1(DT_INST_PROP(n, zephyr_random_mac_address),		\
-		    (ETH_MCUX_GENERATE_MAC_RANDOM(n)),			\
-		    (ETH_MCUX_GENERATE_MAC_UNIQUE(n)))
-
-#define ETH_MCUX_MAC_ADDR_LOCAL(n)					\
-	.mac_addr = DT_INST_PROP(n, local_mac_address),			\
-	.generate_mac = NULL,
-
-#define ETH_MCUX_MAC_ADDR_GENERATE(n)					\
-	.mac_addr = {0},						\
-	.generate_mac = generate_eth##n##_mac,
-
-#define ETH_MCUX_MAC_ADDR(n)						\
-	COND_CODE_1(ETH_MCUX_MAC_ADDR_TO_BOOL(n),			\
-		    (ETH_MCUX_MAC_ADDR_LOCAL(n)),			\
-		    (ETH_MCUX_MAC_ADDR_GENERATE(n)))
-
-#ifdef CONFIG_SOC_FAMILY_KINETIS
-#define ETH_MCUX_POWER_INIT(n)						\
-	.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),		\
-
-#define ETH_MCUX_POWER(n)						\
-	COND_CODE_1(CONFIG_NET_POWER_MANAGEMENT,			\
-		    (ETH_MCUX_POWER_INIT(n)),				\
-		    (ETH_MCUX_NONE))
-#define ETH_MCUX_PM_DEVICE_INIT(n)					\
-	PM_DEVICE_DT_INST_DEFINE(n, eth_mcux_device_pm_action);
-#define ETH_MCUX_PM_DEVICE_GET(n) PM_DEVICE_DT_INST_GET(n)
-#else
-#define ETH_MCUX_POWER(n)
-#define ETH_MCUX_PM_DEVICE_INIT(n)
-#define ETH_MCUX_PM_DEVICE_GET(n) NULL
-#endif /* CONFIG_SOC_FAMILY_KINETIS */
-
-#define ETH_MCUX_GEN_MAC(n)                                             \
-	COND_CODE_0(ETH_MCUX_MAC_ADDR_TO_BOOL(n),                       \
-		    (ETH_MCUX_GENERATE_MAC(n)),                         \
-		    (ETH_MCUX_NONE))
-
-/*
- * In the below code we explicitly define
- * ETH_MCUX_MAC_ADDR_TO_BOOL_0 for the '0' instance of enet driver.
- *
- * For instance N one shall add definition for ETH_MCUX_MAC_ADDR_TO_BOOL_N
- */
-#if (NODE_HAS_VALID_MAC_ADDR(DT_DRV_INST(0))) == 0
-#define ETH_MCUX_MAC_ADDR_TO_BOOL_0 0
-#else
-#define ETH_MCUX_MAC_ADDR_TO_BOOL_0 1
-#endif
-#define ETH_MCUX_MAC_ADDR_TO_BOOL(n) ETH_MCUX_MAC_ADDR_TO_BOOL_##n
-
-#if defined(CONFIG_PINCTRL)
-#define ETH_MCUX_PINCTRL_DEFINE(n) PINCTRL_DT_INST_DEFINE(n);
-#define ETH_MCUX_PINCTRL_INIT(n) .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),
-#else
-#define ETH_MCUX_PINCTRL_DEFINE(n)
-#define ETH_MCUX_PINCTRL_INIT(n)
-#endif
-
-#if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_dtcm)) && \
-	CONFIG_ETH_MCUX_USE_DTCM_FOR_DMA_BUFFER
-/* Use DTCM for hardware DMA buffers */
-#define _mcux_dma_desc __dtcm_bss_section
-#define _mcux_dma_buffer __dtcm_noinit_section
-#define _mcux_driver_buffer __dtcm_noinit_section
-#elif defined(CONFIG_NOCACHE_MEMORY)
-#define _mcux_dma_desc __nocache
-#define _mcux_dma_buffer __nocache
-#define _mcux_driver_buffer
-#else
-#define _mcux_dma_desc
-#define _mcux_dma_buffer
-#define _mcux_driver_buffer
-#endif
-
-#if defined(CONFIG_ETH_MCUX_PHY_RESET)
-#define ETH_MCUX_PHY_GPIOS(n)						\
-	.int_gpio = GPIO_DT_SPEC_INST_GET(n, int_gpios),		\
-	.reset_gpio = GPIO_DT_SPEC_INST_GET(n, reset_gpios),
-#else
-#define ETH_MCUX_PHY_GPIOS(n)
-#endif
-
-#define ETH_MCUX_INIT(n)						\
-	ETH_MCUX_GEN_MAC(n)                                             \
-									\
-	ETH_MCUX_PINCTRL_DEFINE(n)					\
-									\
-	static void eth##n##_config_func(void);				\
-	static _mcux_driver_buffer uint8_t				\
-		tx_enet_frame_##n##_buf[NET_ETH_MAX_FRAME_SIZE];	\
-	static _mcux_driver_buffer uint8_t				\
-		rx_enet_frame_##n##_buf[NET_ETH_MAX_FRAME_SIZE];	\
-	static status_t _MDIO_Write(uint8_t phyAddr, uint8_t regAddr, uint16_t data) \
-	{								\
-		return ENET_MDIOWrite((ENET_Type *)DT_INST_REG_ADDR(n), phyAddr, regAddr, data);\
-	};								\
-									\
-	static status_t _MDIO_Read(uint8_t phyAddr, uint8_t regAddr, uint16_t *pData) \
-	{  \
-		return ENET_MDIORead((ENET_Type *)DT_INST_REG_ADDR(n), phyAddr, regAddr, pData); \
-	}; \
-									\
-	static struct _phy_resource eth##n##_phy_resource = {		\
-		.read = _MDIO_Read,					\
-		.write = _MDIO_Write					\
-	};								\
-	static phy_handle_t eth##n##_phy_handle = {			\
-		.resource = (void *)&eth##n##_phy_resource		\
-	};								\
-	static struct _phy_resource eth##n##_phy_config;		\
-									\
-	static struct eth_context eth##n##_context = {			\
-		.base = (ENET_Type *)DT_INST_REG_ADDR(n),		\
-		.config_func = eth##n##_config_func,			\
-		.phy_config = &eth##n##_phy_config,			\
-		.phy_addr = DT_INST_PROP(n, phy_addr),		        \
-		.phy_duplex = kPHY_FullDuplex,				\
-		.phy_speed = kPHY_Speed100M,				\
-		.phy_handle = &eth##n##_phy_handle,			\
-		.tx_frame_buf = tx_enet_frame_##n##_buf,		\
-		.rx_frame_buf = rx_enet_frame_##n##_buf,		\
-		ETH_MCUX_PINCTRL_INIT(n)				\
-		ETH_MCUX_PHY_GPIOS(n)					\
-		ETH_MCUX_MAC_ADDR(n)					\
-		ETH_MCUX_POWER(n)					\
-	};								\
-									\
-	static __aligned(ENET_BUFF_ALIGNMENT)				\
-		_mcux_dma_desc						\
-		enet_rx_bd_struct_t					\
-		eth##n##_rx_buffer_desc[CONFIG_ETH_MCUX_RX_BUFFERS];	\
-									\
-	static __aligned(ENET_BUFF_ALIGNMENT)				\
-		_mcux_dma_desc						\
-		enet_tx_bd_struct_t					\
-		eth##n##_tx_buffer_desc[CONFIG_ETH_MCUX_TX_BUFFERS];	\
-									\
-	static uint8_t __aligned(ENET_BUFF_ALIGNMENT)			\
-		_mcux_dma_buffer					\
-		eth##n##_rx_buffer[CONFIG_ETH_MCUX_RX_BUFFERS]		\
-				  [ETH_MCUX_BUFFER_SIZE];		\
-									\
-	static uint8_t __aligned(ENET_BUFF_ALIGNMENT)			\
-		_mcux_dma_buffer					\
-		eth##n##_tx_buffer[CONFIG_ETH_MCUX_TX_BUFFERS]		\
-				  [ETH_MCUX_BUFFER_SIZE];		\
-									\
-	ETH_MCUX_PTP_FRAMEINFO_ARRAY(n)					\
-									\
-	static const enet_buffer_config_t eth##n##_buffer_config = {	\
-		.rxBdNumber = CONFIG_ETH_MCUX_RX_BUFFERS,		\
-		.txBdNumber = CONFIG_ETH_MCUX_TX_BUFFERS,		\
-		.rxBuffSizeAlign = ETH_MCUX_BUFFER_SIZE,		\
-		.txBuffSizeAlign = ETH_MCUX_BUFFER_SIZE,		\
-		.rxBdStartAddrAlign = eth##n##_rx_buffer_desc,		\
-		.txBdStartAddrAlign = eth##n##_tx_buffer_desc,		\
-		.rxBufferAlign = eth##n##_rx_buffer[0],			\
-		.txBufferAlign = eth##n##_tx_buffer[0],			\
-		.rxMaintainEnable = true,				\
-		.txMaintainEnable = true,				\
-		ETH_MCUX_PTP_FRAMEINFO(n)				\
-	};								\
-									\
-	ETH_MCUX_PM_DEVICE_INIT(n)					\
-									\
-	ETH_NET_DEVICE_DT_INST_DEFINE(n,				\
-			    eth_init,					\
-			    ETH_MCUX_PM_DEVICE_GET(n),			\
-			    &eth##n##_context,				\
-			    &eth##n##_buffer_config,			\
-			    CONFIG_ETH_INIT_PRIORITY,			\
-			    &api_funcs,					\
-			    NET_ETH_MTU);				\
-									\
-	static void eth##n##_config_func(void)				\
-	{								\
-		ETH_MCUX_IRQ(n, rx);					\
-		ETH_MCUX_IRQ(n, tx);					\
-		ETH_MCUX_IRQ(n, err);					\
-		ETH_MCUX_IRQ(n, common);				\
-		ETH_MCUX_IRQ_PTP(n);					\
-	}								\
-
-DT_INST_FOREACH_STATUS_OKAY(ETH_MCUX_INIT)
-
-#if defined(CONFIG_PTP_CLOCK_MCUX)
-struct ptp_context {
-	struct eth_context *eth_context;
-#if defined(CONFIG_PINCTRL)
-	const struct pinctrl_dev_config *pincfg;
-#endif /* CONFIG_PINCTRL */
-};
-
-#if defined(CONFIG_PINCTRL)
-#define ETH_MCUX_PTP_PINCTRL_DEFINE(n) PINCTRL_DT_DEFINE(n);
-#define ETH_MCUX_PTP_PINCTRL_INIT(n) .pincfg = PINCTRL_DT_DEV_CONFIG_GET(n),
-#else
-#define ETH_MCUX_PTP_PINCTRL_DEFINE(n)
-#define ETH_MCUX_PTP_PINCTRL_INIT(n)
-#endif /* CONFIG_PINCTRL */
-
-ETH_MCUX_PTP_PINCTRL_DEFINE(DT_NODELABEL(ptp))
-
-static struct ptp_context ptp_mcux_0_context = {
-	ETH_MCUX_PTP_PINCTRL_INIT(DT_NODELABEL(ptp))
-};
-
-static int ptp_clock_mcux_set(const struct device *dev,
-			      struct net_ptp_time *tm)
-{
-	struct ptp_context *ptp_context = dev->data;
-	struct eth_context *context = ptp_context->eth_context;
-	enet_ptp_time_t enet_time;
-
-	enet_time.second = tm->second;
-	enet_time.nanosecond = tm->nanosecond;
-
-	ENET_Ptp1588SetTimer(context->base, &context->enet_handle, &enet_time);
-	return 0;
-}
-
-static int ptp_clock_mcux_get(const struct device *dev,
-			      struct net_ptp_time *tm)
-{
-	struct ptp_context *ptp_context = dev->data;
-	struct eth_context *context = ptp_context->eth_context;
-	enet_ptp_time_t enet_time;
-
-	ENET_Ptp1588GetTimer(context->base, &context->enet_handle, &enet_time);
-
-	tm->second = enet_time.second;
-	tm->nanosecond = enet_time.nanosecond;
-	return 0;
-}
-
-static int ptp_clock_mcux_adjust(const struct device *dev, int increment)
-{
-	struct ptp_context *ptp_context = dev->data;
-	struct eth_context *context = ptp_context->eth_context;
-	int key, ret;
-
-	ARG_UNUSED(dev);
-
-	if ((increment <= (int32_t)(-NSEC_PER_SEC)) ||
-			(increment >= (int32_t)NSEC_PER_SEC)) {
-		ret = -EINVAL;
-	} else {
-		key = irq_lock();
-		if (context->base->ATPER != NSEC_PER_SEC) {
-			ret = -EBUSY;
-		} else {
-			/* Seconds counter is handled by software. Change the
-			 * period of one software second to adjust the clock.
-			 */
-			context->base->ATPER = NSEC_PER_SEC - increment;
-			ret = 0;
-		}
-		irq_unlock(key);
-	}
-
-	return ret;
-}
-
-static int ptp_clock_mcux_rate_adjust(const struct device *dev, double ratio)
-{
-	const int hw_inc = NSEC_PER_SEC / CONFIG_ETH_MCUX_PTP_CLOCK_SRC_HZ;
-	struct ptp_context *ptp_context = dev->data;
-	struct eth_context *context = ptp_context->eth_context;
-	int corr;
-	int32_t mul;
-	double val;
-
-	/* No change needed. */
-	if ((ratio > 1.0 && ratio - 1.0 < 0.00000001) ||
-	   (ratio < 1.0 && 1.0 - ratio < 0.00000001)) {
-		return 0;
-	}
-
-	ratio *= context->clk_ratio;
-
-	/* Limit possible ratio. */
-	if ((ratio > 1.0 + 1.0/(2 * hw_inc)) ||
-			(ratio < 1.0 - 1.0/(2 * hw_inc))) {
-		return -EINVAL;
-	}
-
-	/* Save new ratio. */
-	context->clk_ratio = ratio;
-
-	if (ratio < 1.0) {
-		corr = hw_inc - 1;
-		val = 1.0 / (hw_inc * (1.0 - ratio));
-	} else if (ratio > 1.0) {
-		corr = hw_inc + 1;
-		val = 1.0 / (hw_inc * (ratio - 1.0));
-	} else {
-		val = 0;
-		corr = hw_inc;
-	}
-
-	if (val >= INT32_MAX) {
-		/* Value is too high.
-		 * It is not possible to adjust the rate of the clock.
-		 */
-		mul = 0;
-	} else {
-		mul = val;
-	}
-	k_mutex_lock(&context->ptp_mutex, K_FOREVER);
-	ENET_Ptp1588AdjustTimer(context->base, corr, mul);
-	k_mutex_unlock(&context->ptp_mutex);
-
-	return 0;
-}
-
-static DEVICE_API(ptp_clock, api) = {
-	.set = ptp_clock_mcux_set,
-	.get = ptp_clock_mcux_get,
-	.adjust = ptp_clock_mcux_adjust,
-	.rate_adjust = ptp_clock_mcux_rate_adjust,
-};
-
-static int ptp_mcux_init(const struct device *port)
-{
-	const struct device *const eth_dev = DEVICE_DT_GET(DT_NODELABEL(enet));
-	struct eth_context *context = eth_dev->data;
-	struct ptp_context *ptp_context = port->data;
-#if defined(CONFIG_PINCTRL)
-	int err;
-
-	err = pinctrl_apply_state(ptp_context->pincfg, PINCTRL_STATE_DEFAULT);
-	if (err) {
-		return err;
-	}
-#endif /* CONFIG_PINCTRL */
-
-	context->ptp_clock = port;
-	ptp_context->eth_context = context;
-
-	return 0;
-}
-
-DEVICE_DEFINE(mcux_ptp_clock_0, PTP_CLOCK_NAME, ptp_mcux_init,
-		NULL, &ptp_mcux_0_context, NULL, POST_KERNEL,
-		CONFIG_ETH_MCUX_PTP_CLOCK_INIT_PRIO, &api);
-
-#endif /* CONFIG_PTP_CLOCK_MCUX */
diff --git a/drivers/ethernet/nxp_imx_netc/CMakeLists.txt b/drivers/ethernet/nxp_imx_netc/CMakeLists.txt
new file mode 100644
index 00000000000..91fbf4d4f1e
--- /dev/null
+++ b/drivers/ethernet/nxp_imx_netc/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_ETH_NXP_IMX_NETC)
+  zephyr_library_sources(eth_nxp_imx_netc.c)
+  zephyr_library_sources(eth_nxp_imx_netc_psi.c)
+endif()
+
+zephyr_library_sources_ifdef(CONFIG_DSA_NXP_IMX_NETC	dsa_nxp_imx_netc.c)
diff --git a/drivers/ethernet/nxp_imx_netc/Kconfig b/drivers/ethernet/nxp_imx_netc/Kconfig
new file mode 100644
index 00000000000..5c6af4f5c0c
--- /dev/null
+++ b/drivers/ethernet/nxp_imx_netc/Kconfig
@@ -0,0 +1,98 @@
+# Copyright 2024-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig ETH_NXP_IMX_NETC
+	bool "NXP IMX Ethernet and Network Controller (NETC) driver"
+	default y
+	depends on DT_HAS_NXP_IMX_NETC_PSI_ENABLED
+	select MDIO
+	select NOCACHE_MEMORY if ARCH_HAS_NOCACHE_MEMORY_SUPPORT
+	help
+	  Enable Ethernet and Network Controller (NETC) driver for NXP IMX SoCs.
+
+if ETH_NXP_IMX_NETC
+
+config ETH_NXP_IMX_MSGINTR
+	int "Message Interrupt module select"
+	default 1
+	help
+	  Message Interrupt module select.
+
+config ETH_NXP_IMX_RX_THREAD_PRIO
+	int "RX thread priority"
+	default 2
+	help
+	  RX thread priority. RX thread is a cooperative thread.
+
+config ETH_NXP_IMX_RX_THREAD_STACK_SIZE
+	int "RX thread stack size"
+	default 1500
+	help
+	  RX thread stack size.
+
+config ETH_NXP_IMX_RX_BUDGET
+	int "RX thread budget"
+	default 128
+	range 1 1024
+	help
+	  The budget parameter places a limit on the amount of work the driver may
+	  do in the RX thread before yielding the processor, in case there is more
+	  work to do. This is to prevent the RX thread to starve other threads. Each
+	  received frame counts as one unit of work.
+
+config ETH_NXP_IMX_TX_RING_NUM
+	int "TX ring number"
+	default 1
+	range 1 1023
+	help
+	  TX ring number used. The actual maximum value may varies from platforms.
+
+config ETH_NXP_IMX_TX_RING_LEN
+	int "TX ring length"
+	default 8
+	range 8 256
+	help
+	  Length of the TX ring. The value must be a multiple of 8.
+
+config ETH_NXP_IMX_TX_RING_BUF_SIZE
+	int "TX ring data buffer size"
+	default 1000
+	range 64 1536
+	help
+	  Size, in bytes, of the TX data buffer. The size must be big enough to
+	  store one complete Ethernet frame, and be a multiple of 8.
+
+config ETH_NXP_IMX_RX_RING_NUM
+	int "RX ring number"
+	default 1
+	range 1 1023
+	help
+	  RX ring number used. The actual maximum value may varies from platforms.
+
+config ETH_NXP_IMX_RX_RING_LEN
+	int "RX ring length"
+	default 8
+	range 8 256
+	help
+	  Length of the RX ring. The value must be a multiple of 8.
+
+config ETH_NXP_IMX_RX_RING_BUF_SIZE
+	int "RX ring data buffer size"
+	default 1518
+	range 64 1536
+	help
+	  Size, in bytes, of the RX data buffer. The size must be big enough to
+	  store one complete Ethernet frame, and be a multiple of 8.
+
+endif # ETH_NXP_IMX_NETC
+
+if NET_DSA
+
+config DSA_NXP_IMX_NETC
+	bool "Support for NXP i.MX NETC"
+	default y
+	depends on DT_HAS_NXP_NETC_SWITCH_ENABLED
+	help
+	  Add support for NXP i.MX NETC DSA device driver.
+
+endif
diff --git a/drivers/ethernet/nxp_imx_netc/dsa_nxp_imx_netc.c b/drivers/ethernet/nxp_imx_netc/dsa_nxp_imx_netc.c
new file mode 100644
index 00000000000..9208a513347
--- /dev/null
+++ b/drivers/ethernet/nxp_imx_netc/dsa_nxp_imx_netc.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(dsa_netc, CONFIG_ETHERNET_LOG_LEVEL);
+
+#include <zephyr/net/ethernet.h>
+#include <zephyr/drivers/pinctrl.h>
+
+#include "../eth.h"
+#include "nxp_imx_netc.h"
+#include "fsl_netc_switch.h"
+
+#define DT_DRV_COMPAT nxp_netc_switch
+#define PRV_DATA(ctx) ((struct dsa_netc_data *const)(ctx)->prv_data)
+
+struct dsa_netc_port_config {
+	const struct pinctrl_dev_config *pincfg;
+	netc_hw_mii_mode_t phy_mode;
+};
+
+struct dsa_netc_data {
+	swt_config_t swt_config;
+	swt_handle_t swt_handle;
+	netc_cmd_bd_t *cmd_bd;
+};
+
+static int dsa_netc_port_init(const struct device *dev)
+{
+	const struct dsa_port_config *cfg = dev->config;
+	struct dsa_netc_port_config *prv_cfg = cfg->prv_config;
+	struct dsa_switch_context *dsa_switch_ctx = dev->data;
+	struct dsa_netc_data *prv = PRV_DATA(dsa_switch_ctx);
+	swt_config_t *swt_config = &prv->swt_config;
+	int ret;
+
+	if (prv_cfg->pincfg != NULL) {
+		ret = pinctrl_apply_state(prv_cfg->pincfg, PINCTRL_STATE_DEFAULT);
+		if (ret < 0) {
+			return ret;
+		}
+	}
+
+	/* Get default config when beginning to init the first port */
+	if (dsa_switch_ctx->init_ports == 1) {
+		SWT_GetDefaultConfig(swt_config);
+		swt_config->bridgeCfg.dVFCfg.portMembership = 0x0;
+	}
+
+	/* miiSpeed and miiDuplex will get set correctly when link is up */
+	swt_config->ports[cfg->port_idx].ethMac.miiMode = prv_cfg->phy_mode;
+
+	swt_config->bridgeCfg.dVFCfg.portMembership |= (1 << cfg->port_idx);
+	swt_config->ports[cfg->port_idx].bridgeCfg.enMacStationMove = true;
+
+	return 0;
+}
+
+static void dsa_netc_port_generate_random_mac(uint8_t *mac_addr)
+{
+	gen_random_mac(mac_addr, FREESCALE_OUI_B0, FREESCALE_OUI_B1, FREESCALE_OUI_B2);
+}
+
+static int dsa_netc_switch_setup(const struct dsa_switch_context *dsa_switch_ctx)
+{
+	struct dsa_netc_data *prv = PRV_DATA(dsa_switch_ctx);
+	swt_config_t *swt_config = &prv->swt_config;
+	status_t result;
+
+	swt_config->cmdRingUse = 1U;
+	swt_config->cmdBdrCfg[0].bdBase = prv->cmd_bd;
+	swt_config->cmdBdrCfg[0].bdLength = 8U;
+
+	result = SWT_Init(&prv->swt_handle, &prv->swt_config);
+	if (result != kStatus_Success) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static void dsa_netc_port_phylink_change(const struct device *phydev, struct phy_link_state *state,
+					 void *user_data)
+{
+	const struct device *dev = (struct device *)user_data;
+	struct net_if *iface = net_if_lookup_by_dev(dev);
+	const struct dsa_port_config *cfg = dev->config;
+	struct dsa_switch_context *dsa_switch_ctx = dev->data;
+	struct dsa_netc_data *prv = PRV_DATA(dsa_switch_ctx);
+	status_t result;
+
+	if (state->is_up) {
+		LOG_INF("DSA user port %d Link up", cfg->port_idx);
+		result = SWT_SetEthPortMII(&prv->swt_handle, cfg->port_idx,
+					   PHY_TO_NETC_SPEED(state->speed),
+					   PHY_TO_NETC_DUPLEX_MODE(state->speed));
+		if (result != kStatus_Success) {
+			LOG_ERR("DSA user port %d failed to set MAC up", cfg->port_idx);
+		}
+		net_eth_carrier_on(iface);
+	} else {
+		LOG_INF("DSA user port %d Link down", cfg->port_idx);
+		net_eth_carrier_off(iface);
+	}
+}
+
+static struct dsa_api dsa_netc_api = {
+	.port_init = dsa_netc_port_init,
+	.port_generate_random_mac = dsa_netc_port_generate_random_mac,
+	.switch_setup = dsa_netc_switch_setup,
+	.port_phylink_change = dsa_netc_port_phylink_change,
+};
+
+#define DSA_NETC_PORT_INST_INIT(port, n)                                                    \
+	COND_CODE_1(DT_NUM_PINCTRL_STATES(port),                                            \
+			(PINCTRL_DT_DEFINE(port);), (EMPTY))                                \
+	struct dsa_netc_port_config dsa_netc_##n##_##port##_config = {                      \
+		.pincfg = COND_CODE_1(DT_NUM_PINCTRL_STATES(port),                          \
+				(PINCTRL_DT_DEV_CONFIG_GET(port)), NULL),                   \
+		.phy_mode = NETC_PHY_MODE(port),                                            \
+	};                                                                                  \
+	struct dsa_port_config dsa_##n##_##port##_config = {                                \
+		.use_random_mac_addr = DT_NODE_HAS_PROP(port, zephyr_random_mac_address),   \
+		.mac_addr = DT_PROP_OR(port, local_mac_address, {0}),                       \
+		.port_idx = DT_REG_ADDR(port),                                              \
+		.phy_dev = DEVICE_DT_GET_OR_NULL(DT_PHANDLE(port, phy_handle)),             \
+		.phy_mode = DT_PROP_OR(port, phy_connection_type, ""),                      \
+		.ethernet_connection = DEVICE_DT_GET_OR_NULL(DT_PHANDLE(port, ethernet)),   \
+		.prv_config = &dsa_netc_##n##_##port##_config,                              \
+	};                                                                                  \
+	DSA_PORT_INST_INIT(port, n, &dsa_##n##_##port##_config)
+
+#define DSA_NETC_DEVICE(n)                                                                  \
+	AT_NONCACHEABLE_SECTION_ALIGN(static netc_cmd_bd_t dsa_netc_##n##_cmd_bd[8],        \
+				      NETC_BD_ALIGN);                                       \
+	static struct dsa_netc_data dsa_netc_data_##n = {                                   \
+		.cmd_bd = dsa_netc_##n##_cmd_bd,                                            \
+	};                                                                                  \
+	DSA_SWITCH_INST_INIT(n, &dsa_netc_api, &dsa_netc_data_##n, DSA_NETC_PORT_INST_INIT);
+
+DT_INST_FOREACH_STATUS_OKAY(DSA_NETC_DEVICE);
diff --git a/drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc.c b/drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc.c
new file mode 100644
index 00000000000..97c8463135c
--- /dev/null
+++ b/drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc.c
@@ -0,0 +1,386 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(nxp_imx_eth);
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/mbox.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/net/ethernet.h>
+#include <zephyr/net/net_if.h>
+#include <zephyr/net/net_pkt.h>
+#include <zephyr/net/phy.h>
+#include <ethernet/eth_stats.h>
+#include <zephyr/net/dsa_core.h>
+#include "../eth.h"
+#include "eth_nxp_imx_netc_priv.h"
+
+#if !(defined(FSL_FEATURE_NETC_HAS_SWITCH_TAG) && FSL_FEATURE_NETC_HAS_SWITCH_TAG) && \
+	defined(CONFIG_NET_DSA)
+#define NETC_HAS_NO_SWITCH_TAG_SUPPORT 1
+#endif
+
+const struct device *netc_dev_list[NETC_DRV_MAX_INST_SUPPORT];
+
+static int netc_eth_rx(const struct device *dev)
+{
+	struct netc_eth_data *data = dev->data;
+	struct net_if *iface_dst = data->iface;
+#if defined(NETC_HAS_NO_SWITCH_TAG_SUPPORT)
+	struct ethernet_context *ctx = net_if_l2_data(iface_dst);
+#endif
+	netc_frame_attr_t attr = {0};
+	struct net_pkt *pkt;
+	int key;
+	int ret = 0;
+	status_t result;
+	uint32_t length;
+
+	key = irq_lock();
+
+	/* Check rx frame */
+	result = EP_GetRxFrameSize(&data->handle, 0, &length);
+	if (result == kStatus_NETC_RxFrameEmpty) {
+		ret = -ENOBUFS;
+		goto out;
+	}
+
+	if (result != kStatus_Success) {
+		LOG_ERR("Error on received frame");
+		ret = -EIO;
+		goto out;
+	}
+
+	/* Receive frame */
+	result = EP_ReceiveFrameCopy(&data->handle, 0, data->rx_frame, length, &attr);
+	if (result != kStatus_Success) {
+		LOG_ERR("Error on received frame");
+		ret = -EIO;
+		goto out;
+	}
+
+#if defined(NETC_HAS_NO_SWITCH_TAG_SUPPORT)
+	if (ctx->dsa_port == DSA_CONDUIT_PORT) {
+		iface_dst = ctx->dsa_switch_ctx->iface_user[attr.srcPort];
+	}
+#endif
+	/* Copy to pkt */
+	pkt = net_pkt_rx_alloc_with_buffer(iface_dst, length, AF_UNSPEC, 0, NETC_TIMEOUT);
+	if (pkt == NULL) {
+		eth_stats_update_errors_rx(iface_dst);
+		ret = -ENOBUFS;
+		goto out;
+	}
+
+	ret = net_pkt_write(pkt, data->rx_frame, length);
+	if (ret != 0) {
+		eth_stats_update_errors_rx(iface_dst);
+		net_pkt_unref(pkt);
+		goto out;
+	}
+
+	/* Send to upper layer */
+	ret = net_recv_data(iface_dst, pkt);
+	if (ret < 0) {
+		eth_stats_update_errors_rx(iface_dst);
+		net_pkt_unref(pkt);
+		LOG_ERR("Failed to enqueue frame into rx queue: %d", ret);
+	}
+out:
+	irq_unlock(key);
+	return ret;
+}
+
+static void netc_eth_rx_thread(void *arg1, void *unused1, void *unused2)
+{
+	const struct device *dev = (const struct device *)arg1;
+	struct netc_eth_data *data = dev->data;
+	int ret;
+	int work;
+
+	ARG_UNUSED(unused1);
+	ARG_UNUSED(unused2);
+
+	while (1) {
+		ret = k_sem_take(&data->rx_sem, K_FOREVER);
+		if (ret != 0) {
+			LOG_ERR("Take rx_sem error: %d", ret);
+			continue;
+		}
+
+		work = 0;
+		while (netc_eth_rx(dev) != -ENOBUFS) {
+			if (++work == CONFIG_ETH_NXP_IMX_RX_BUDGET) {
+				/* more work to do, reschedule */
+				work = 0;
+				k_yield();
+			}
+		}
+	}
+}
+
+static void msgintr_isr(void)
+{
+	uint32_t irqs = NETC_MSGINTR->MSI[NETC_MSGINTR_CHANNEL].MSIR;
+
+	for (int i = 0; i < NETC_DRV_MAX_INST_SUPPORT; i++) {
+		const struct device *dev = netc_dev_list[i];
+		const struct netc_eth_config *config;
+		struct netc_eth_data *data;
+
+		if (!dev) {
+			return;
+		}
+
+		config = dev->config;
+		data = dev->data;
+		/* Transmit interrupt */
+		if (irqs & (1 << config->tx_intr_msg_data)) {
+			EP_CleanTxIntrFlags(&data->handle, 1, 0);
+			data->tx_done = true;
+		}
+		/* Receive interrupt */
+		if (irqs & (1 << config->rx_intr_msg_data)) {
+			EP_CleanRxIntrFlags(&data->handle, 1);
+			k_sem_give(&data->rx_sem);
+		}
+	}
+
+	SDK_ISR_EXIT_BARRIER;
+}
+
+int netc_eth_init_common(const struct device *dev)
+{
+	const struct netc_eth_config *config = dev->config;
+	struct netc_eth_data *data = dev->data;
+	netc_msix_entry_t msix_entry[NETC_MSIX_ENTRY_NUM];
+	netc_rx_bdr_config_t rx_bdr_config = {0};
+	netc_tx_bdr_config_t tx_bdr_config = {0};
+	netc_bdr_config_t bdr_config = {0};
+	ep_config_t ep_config;
+	uint32_t msg_addr;
+	status_t result;
+
+	config->bdr_init(&bdr_config, &rx_bdr_config, &tx_bdr_config);
+
+	/* MSIX entry configuration */
+	msg_addr = MSGINTR_GetIntrSelectAddr(NETC_MSGINTR, NETC_MSGINTR_CHANNEL);
+	msix_entry[NETC_TX_MSIX_ENTRY_IDX].control = kNETC_MsixIntrMaskBit;
+	msix_entry[NETC_TX_MSIX_ENTRY_IDX].msgAddr = msg_addr;
+	msix_entry[NETC_TX_MSIX_ENTRY_IDX].msgData = config->tx_intr_msg_data;
+
+	msix_entry[NETC_RX_MSIX_ENTRY_IDX].control = kNETC_MsixIntrMaskBit;
+	msix_entry[NETC_RX_MSIX_ENTRY_IDX].msgAddr = msg_addr;
+	msix_entry[NETC_RX_MSIX_ENTRY_IDX].msgData = config->rx_intr_msg_data;
+
+	if (!irq_is_enabled(NETC_MSGINTR_IRQ)) {
+		IRQ_CONNECT(NETC_MSGINTR_IRQ, 0, msgintr_isr, 0, 0);
+		irq_enable(NETC_MSGINTR_IRQ);
+	}
+
+	/* Endpoint configuration. */
+	EP_GetDefaultConfig(&ep_config);
+	ep_config.si = config->si_idx;
+	ep_config.siConfig.txRingUse = 1;
+	ep_config.siConfig.rxRingUse = 1;
+	ep_config.userData = data;
+	ep_config.reclaimCallback = NULL;
+	ep_config.msixEntry = &msix_entry[0];
+	ep_config.entryNum = NETC_MSIX_ENTRY_NUM;
+	ep_config.port.ethMac.miiMode = config->phy_mode;
+	ep_config.port.ethMac.miiSpeed = kNETC_MiiSpeed100M;
+	ep_config.port.ethMac.miiDuplex = kNETC_MiiFullDuplex;
+	ep_config.rxCacheMaintain = true;
+	ep_config.txCacheMaintain = true;
+
+	config->generate_mac(&data->mac_addr[0]);
+
+	result = EP_Init(&data->handle, &data->mac_addr[0], &ep_config, &bdr_config);
+	if (result != kStatus_Success) {
+		return -ENOBUFS;
+	}
+
+	/*
+	 * For management ENETC, the SI 0 hardware Tx ring index 0 should be used for
+	 * direct switch enqueue feature.
+	 * hal enetc driver reserved ring 0 for hal switch driver, so re-enable it here.
+	 */
+	if (config->pseudo_mac) {
+		if (NETC_SIConfigTxBDR(data->handle.hw.si, 0, &tx_bdr_config) != kStatus_Success) {
+			return -ENOBUFS;
+		}
+	}
+
+	for (int i = 0; i < NETC_DRV_MAX_INST_SUPPORT; i++) {
+		if (!netc_dev_list[i]) {
+			netc_dev_list[i] = dev;
+			break;
+		}
+	}
+
+	/* Unmask MSIX message interrupt. */
+	EP_MsixSetEntryMask(&data->handle, NETC_TX_MSIX_ENTRY_IDX, false);
+	EP_MsixSetEntryMask(&data->handle, NETC_RX_MSIX_ENTRY_IDX, false);
+
+	k_mutex_init(&data->tx_mutex);
+
+	k_sem_init(&data->rx_sem, 0, 1);
+	k_thread_create(&data->rx_thread, data->rx_thread_stack,
+			K_KERNEL_STACK_SIZEOF(data->rx_thread_stack), netc_eth_rx_thread,
+			(void *)dev, NULL, NULL, K_PRIO_COOP(CONFIG_ETH_NXP_IMX_RX_THREAD_PRIO), 0,
+			K_NO_WAIT);
+	k_thread_name_set(&data->rx_thread, "netc_eth_rx");
+
+	return 0;
+}
+
+int netc_eth_tx(const struct device *dev, struct net_pkt *pkt)
+{
+	const struct netc_eth_config *cfg = dev->config;
+	struct netc_eth_data *data = dev->data;
+	netc_buffer_struct_t buff = {.buffer = data->tx_buff, .length = sizeof(data->tx_buff)};
+	netc_frame_struct_t frame = {.buffArray = &buff, .length = 1};
+	netc_tx_frame_info_t *frame_info;
+	struct net_if *iface_dst;
+	size_t pkt_len = net_pkt_get_len(pkt);
+#if defined(NETC_HAS_NO_SWITCH_TAG_SUPPORT)
+	struct ethernet_context *eth_ctx = net_if_l2_data(data->iface);
+#endif
+	status_t result;
+	int ret;
+
+	__ASSERT(pkt, "Packet pointer is NULL");
+
+	iface_dst = data->iface;
+
+	if (cfg->pseudo_mac) {
+#if defined(NETC_HAS_NO_SWITCH_TAG_SUPPORT)
+		/* DSA conduit port not used */
+		if (eth_ctx->dsa_port != DSA_CONDUIT_PORT) {
+			return -ENOSYS;
+		}
+		/* DSA driver redirects the iface */
+		iface_dst = pkt->iface;
+#else
+		return -ENOSYS;
+#endif
+	}
+
+	k_mutex_lock(&data->tx_mutex, K_FOREVER);
+
+	/* Copy packet to tx buffer */
+	buff.length = (uint16_t)pkt_len;
+	ret = net_pkt_read(pkt, buff.buffer, pkt_len);
+	if (ret) {
+		LOG_ERR("Failed to copy packet to tx buffer: %d", ret);
+		ret = -ENOBUFS;
+		goto error;
+	}
+
+	/* Send */
+	data->tx_done = false;
+
+#if defined(NETC_HAS_NO_SWITCH_TAG_SUPPORT)
+	if (eth_ctx->dsa_port == DSA_CONDUIT_PORT) {
+		const struct dsa_port_config *port_cfg = net_if_get_device(iface_dst)->config;
+		const int dst_port = port_cfg->port_idx;
+		netc_tx_bd_t txDesc[2] = {0};
+
+		txDesc[0].standard.flags = NETC_SI_TXDESCRIP_RD_FLQ(2) |
+					   NETC_SI_TXDESCRIP_RD_SMSO_MASK |
+					   NETC_SI_TXDESCRIP_RD_PORT(dst_port);
+		result = EP_SendFrameCommon(&data->handle, &data->handle.txBdRing[0], 0, &frame,
+					    NULL, &txDesc[0], data->handle.cfg.txCacheMaintain);
+	} else {
+		result = EP_SendFrame(&data->handle, 0, &frame, NULL, NULL);
+	}
+#else
+	result = EP_SendFrame(&data->handle, 0, &frame, NULL, NULL);
+#endif
+	if (result != kStatus_Success) {
+		LOG_ERR("Failed to tx frame");
+		ret = -EIO;
+		goto error;
+	}
+
+	while (!data->tx_done) {
+	}
+
+	do {
+		frame_info = EP_ReclaimTxDescCommon(&data->handle, &data->handle.txBdRing[0],
+						    0, false);
+		if (frame_info != NULL) {
+			if (frame_info->status != kNETC_EPTxSuccess) {
+				memset(frame_info, 0, sizeof(netc_tx_frame_info_t));
+				LOG_ERR("Failed to tx frame");
+				ret = -EIO;
+				goto error;
+			}
+			memset(frame_info, 0, sizeof(netc_tx_frame_info_t));
+		}
+	} while (frame_info != NULL);
+
+	ret = 0;
+error:
+	k_mutex_unlock(&data->tx_mutex);
+
+	if (ret != 0) {
+		eth_stats_update_errors_tx(iface_dst);
+	}
+	return ret;
+}
+
+enum ethernet_hw_caps netc_eth_get_capabilities(const struct device *dev)
+{
+	uint32_t caps;
+
+	caps = (ETHERNET_LINK_10BASE_T | ETHERNET_LINK_100BASE_T | ETHERNET_LINK_1000BASE_T |
+		ETHERNET_HW_RX_CHKSUM_OFFLOAD | ETHERNET_HW_FILTERING
+#if defined(CONFIG_NET_VLAN)
+		| ETHERNET_HW_VLAN
+#endif
+#if defined(CONFIG_NET_PROMISCUOUS_MODE)
+		| ETHERNET_PROMISC_MODE
+#endif
+	);
+
+	return caps;
+}
+
+int netc_eth_set_config(const struct device *dev, enum ethernet_config_type type,
+			const struct ethernet_config *config)
+{
+	struct netc_eth_data *data = dev->data;
+	const struct netc_eth_config *cfg = dev->config;
+	status_t result;
+	int ret = 0;
+
+	switch (type) {
+	case ETHERNET_CONFIG_TYPE_MAC_ADDRESS:
+		/* Set new Ethernet MAC address and register it with the upper layer */
+		memcpy(data->mac_addr, config->mac_address.addr, sizeof(data->mac_addr));
+		result = EP_SetPrimaryMacAddr(&data->handle, (uint8_t *)data->mac_addr);
+		if (result != kStatus_Success) {
+			LOG_ERR("PHY device (%p) is not ready, cannot init iface", cfg->phy_dev);
+			ret = -ENOTSUP;
+			break;
+		}
+		net_if_set_link_addr(data->iface, data->mac_addr, sizeof(data->mac_addr),
+				     NET_LINK_ETHERNET);
+		LOG_INF("SI%d MAC set to: %02x:%02x:%02x:%02x:%02x:%02x", getSiIdx(cfg->si_idx),
+			data->mac_addr[0], data->mac_addr[1], data->mac_addr[2], data->mac_addr[3],
+			data->mac_addr[4], data->mac_addr[5]);
+		break;
+	default:
+		ret = -ENOTSUP;
+		break;
+	}
+
+	return ret;
+}
diff --git a/drivers/ethernet/eth_nxp_imx_netc_priv.h b/drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc_priv.h
similarity index 84%
rename from drivers/ethernet/eth_nxp_imx_netc_priv.h
rename to drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc_priv.h
index f09e718fdc2..f9f9c6419ea 100644
--- a/drivers/ethernet/eth_nxp_imx_netc_priv.h
+++ b/drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc_priv.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,11 +7,11 @@
 #ifndef ZEPHYR_DRIVERS_ETHERNET_ETH_NXP_IMX_NETC_PRIV_H_
 #define ZEPHYR_DRIVERS_ETHERNET_ETH_NXP_IMX_NETC_PRIV_H_
 
+#include "nxp_imx_netc.h"
 #include "fsl_netc_endpoint.h"
 #include "fsl_msgintr.h"
 
 /* Buffer and descriptor alignment */
-#define NETC_BD_ALIGN   128
 #define NETC_BUFF_ALIGN 64
 #define NETC_RX_RING_BUF_SIZE_ALIGN                                                                \
 	SDK_SIZEALIGN(CONFIG_ETH_NXP_IMX_RX_RING_BUF_SIZE, NETC_BUFF_ALIGN)
@@ -29,12 +29,20 @@
 /* MSGINTR */
 #define NETC_MSGINTR_CHANNEL 0
 
+#if DT_IRQ_HAS_IDX(DT_NODELABEL(netc), 0)
+#define NETC_MSGINTR_IRQ DT_IRQN_BY_IDX(DT_NODELABEL(netc), 0)
+#endif
+
 #if (CONFIG_ETH_NXP_IMX_MSGINTR == 1)
-#define NETC_MSGINTR     MSGINTR1
+#define NETC_MSGINTR MSGINTR1
+#ifndef NETC_MSGINTR_IRQ
 #define NETC_MSGINTR_IRQ MSGINTR1_IRQn
+#endif
 #elif (CONFIG_ETH_NXP_IMX_MSGINTR == 2)
-#define NETC_MSGINTR     MSGINTR2
+#define NETC_MSGINTR MSGINTR2
+#ifndef NETC_MSGINTR_IRQ
 #define NETC_MSGINTR_IRQ MSGINTR2_IRQn
+#endif
 #else
 #error "Current CONFIG_ETH_NXP_IMX_MSGINTR not support"
 #endif
@@ -42,15 +50,6 @@
 /* Timeout for various operations */
 #define NETC_TIMEOUT K_MSEC(20)
 
-/* Helper macros to convert from Zephyr PHY speed to NETC speed/duplex types */
-#define PHY_TO_NETC_SPEED(x)                                                                       \
-	(PHY_LINK_IS_SPEED_1000M(x)                                                                \
-		 ? kNETC_MiiSpeed1000M                                                             \
-		 : (PHY_LINK_IS_SPEED_100M(x) ? kNETC_MiiSpeed100M : kNETC_MiiSpeed10M))
-
-#define PHY_TO_NETC_DUPLEX_MODE(x)                                                                 \
-	(PHY_LINK_IS_FULL_DUPLEX(x) ? kNETC_MiiFullDuplex : kNETC_MiiHalfDuplex)
-
 /* Helper function to generate an Ethernet MAC address for a given ENETC instance */
 #define FREESCALE_OUI_B0 0x00
 #define FREESCALE_OUI_B1 0x04
@@ -85,6 +84,8 @@
 struct netc_eth_config {
 	uint16_t si_idx;
 	const struct device *phy_dev;
+	netc_hw_mii_mode_t phy_mode;
+	volatile bool pseudo_mac;
 	void (*generate_mac)(uint8_t *mac_addr);
 	void (*bdr_init)(netc_bdr_config_t *bdr_config, netc_rx_bdr_config_t *rx_bdr_config,
 			 netc_tx_bdr_config_t *tx_bdr_config);
@@ -101,7 +102,6 @@ struct netc_eth_data {
 	uint8_t mac_addr[6];
 	/* TX */
 	struct k_mutex tx_mutex;
-	netc_tx_frame_info_t tx_info;
 	uint8_t *tx_buff;
 	volatile bool tx_done;
 	/* RX */
diff --git a/drivers/ethernet/eth_nxp_imx_netc_psi.c b/drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc_psi.c
similarity index 91%
rename from drivers/ethernet/eth_nxp_imx_netc_psi.c
rename to drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc_psi.c
index d12b34e6308..30740d6cb1e 100644
--- a/drivers/ethernet/eth_nxp_imx_netc_psi.c
+++ b/drivers/ethernet/nxp_imx_netc/eth_nxp_imx_netc_psi.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,20 +19,21 @@ LOG_MODULE_REGISTER(nxp_imx_eth_psi);
 #include <zephyr/net/phy.h>
 #include <ethernet/eth_stats.h>
 
-#include "eth.h"
+#include "../eth.h"
 #include "eth_nxp_imx_netc_priv.h"
 
 static void netc_eth_phylink_callback(const struct device *pdev, struct phy_link_state *state,
 				      void *user_data)
 {
 	const struct device *dev = (struct device *)user_data;
+	const struct netc_eth_config *cfg = dev->config;
 	struct netc_eth_data *data = dev->data;
 	status_t result;
 
 	ARG_UNUSED(pdev);
 
 	if (state->is_up) {
-		LOG_DBG("Link up");
+		LOG_INF("ENETC%d Link up", getSiInstance(cfg->si_idx));
 		result = EP_Up(&data->handle, PHY_TO_NETC_SPEED(state->speed),
 			       PHY_TO_NETC_DUPLEX_MODE(state->speed));
 		if (result != kStatus_Success) {
@@ -40,7 +41,7 @@ static void netc_eth_phylink_callback(const struct device *pdev, struct phy_link
 		}
 		net_eth_carrier_on(data->iface);
 	} else {
-		LOG_DBG("Link down");
+		LOG_INF("ENETC%d Link down", getSiInstance(cfg->si_idx));
 		result = EP_Down(&data->handle);
 		if (result != kStatus_Success) {
 			LOG_ERR("Failed to set MAC down");
@@ -73,12 +74,16 @@ static void netc_eth_iface_init(struct net_if *iface)
 
 	net_if_set_link_addr(iface, data->mac_addr, sizeof(data->mac_addr), NET_LINK_ETHERNET);
 
-	LOG_INF("SI%d MAC: %02x:%02x:%02x:%02x:%02x:%02x", cfg->si_idx, data->mac_addr[0],
-		data->mac_addr[1], data->mac_addr[2], data->mac_addr[3], data->mac_addr[4],
-		data->mac_addr[5]);
+	LOG_INF("ENETC%d MAC: %02x:%02x:%02x:%02x:%02x:%02x", getSiInstance(cfg->si_idx),
+		data->mac_addr[0], data->mac_addr[1], data->mac_addr[2], data->mac_addr[3],
+		data->mac_addr[4], data->mac_addr[5]);
 
 	ethernet_init(iface);
 
+	if (cfg->pseudo_mac) {
+		return;
+	}
+
 	/*
 	 * PSI controls the PHY. If PHY is configured either as fixed
 	 * link or autoneg, the callback is executed at least once
@@ -88,10 +93,10 @@ static void netc_eth_iface_init(struct net_if *iface)
 		LOG_ERR("PHY device (%p) is not ready, cannot init iface", cfg->phy_dev);
 		return;
 	}
-	phy_link_callback_set(cfg->phy_dev, &netc_eth_phylink_callback, (void *)dev);
-
 	/* Do not start the interface until PHY link is up */
 	net_if_carrier_off(iface);
+
+	phy_link_callback_set(cfg->phy_dev, &netc_eth_phylink_callback, (void *)dev);
 }
 
 static int netc_eth_init(const struct device *dev)
@@ -99,11 +104,16 @@ static int netc_eth_init(const struct device *dev)
 	const struct netc_eth_config *cfg = dev->config;
 	int err;
 
+	if (cfg->pseudo_mac) {
+		goto init_common;
+	}
+
 	err = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);
 	if (err) {
 		return err;
 	}
 
+init_common:
 	return netc_eth_init_common(dev);
 }
 
@@ -181,7 +191,10 @@ static const struct ethernet_api netc_eth_api = {.iface_api.init = netc_eth_ifac
 	static const struct netc_eth_config netc_eth##n##_config = {                               \
 		.generate_mac = netc_eth##n##_generate_mac,                                        \
 		.bdr_init = netc_eth##n##_bdr_init,                                                \
-		.phy_dev = DEVICE_DT_GET(DT_INST_PHANDLE(n, phy_handle)),                          \
+		.phy_dev = (COND_CODE_1(DT_INST_NODE_HAS_PROP(n, phy_handle),                      \
+					(DEVICE_DT_GET(DT_INST_PHANDLE(n, phy_handle))), NULL)),   \
+		.phy_mode = NETC_PHY_MODE(DT_DRV_INST(n)),                                         \
+		.pseudo_mac = DT_ENUM_HAS_VALUE(DT_DRV_INST(n), phy_connection_type, internal),    \
 		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                       \
 		.si_idx = (DT_INST_PROP(n, mac_index) << 8) | DT_INST_PROP(n, si_index),           \
 		.tx_intr_msg_data = NETC_TX_INTR_MSG_DATA_START + n,                               \
diff --git a/drivers/ethernet/nxp_imx_netc/nxp_imx_netc.h b/drivers/ethernet/nxp_imx_netc/nxp_imx_netc.h
new file mode 100644
index 00000000000..67f043f06db
--- /dev/null
+++ b/drivers/ethernet/nxp_imx_netc/nxp_imx_netc.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __NXP_IMX_NETC_H__
+#define __NXP_IMX_NETC_H__
+
+#define NETC_BD_ALIGN 128
+
+#define FREESCALE_OUI_B0 0x00
+#define FREESCALE_OUI_B1 0x04
+#define FREESCALE_OUI_B2 0x9f
+
+/* Get phy mode from dts. Default RMII for i.MXRT1180 ENETC which hasn't added the property. */
+#define NETC_PHY_MODE(node_id)                                                                     \
+	(DT_ENUM_HAS_VALUE(node_id, phy_connection_type, mii)                                      \
+		 ? kNETC_MiiMode                                                                   \
+		 : (DT_ENUM_HAS_VALUE(node_id, phy_connection_type, rmii)                          \
+			    ? kNETC_RmiiMode                                                       \
+			    : (DT_ENUM_HAS_VALUE(node_id, phy_connection_type, rgmii)              \
+				       ? kNETC_RgmiiMode                                           \
+				       : (DT_ENUM_HAS_VALUE(node_id, phy_connection_type, gmii)    \
+						  ? kNETC_GmiiMode                                 \
+						  : kNETC_RmiiMode))))
+
+/* Helper macros to convert from Zephyr PHY speed to NETC speed/duplex types */
+#define PHY_TO_NETC_SPEED(x)                                                                       \
+	(PHY_LINK_IS_SPEED_1000M(x)                                                                \
+		 ? kNETC_MiiSpeed1000M                                                             \
+		 : (PHY_LINK_IS_SPEED_100M(x) ? kNETC_MiiSpeed100M : kNETC_MiiSpeed10M))
+
+#define PHY_TO_NETC_DUPLEX_MODE(x)                                                                 \
+	(PHY_LINK_IS_FULL_DUPLEX(x) ? kNETC_MiiFullDuplex : kNETC_MiiHalfDuplex)
+
+#endif
diff --git a/drivers/ethernet/oa_tc6.c b/drivers/ethernet/oa_tc6.c
index 1818ccf8c14..ccdfff4dbd2 100644
--- a/drivers/ethernet/oa_tc6.c
+++ b/drivers/ethernet/oa_tc6.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <zephyr/net/mdio.h>
 #include "oa_tc6.h"
 
 #include <zephyr/logging/log.h>
@@ -19,12 +20,12 @@ LOG_MODULE_REGISTER(oa_tc6, CONFIG_ETHERNET_LOG_LEVEL);
 
 int oa_tc6_reg_read(struct oa_tc6 *tc6, const uint32_t reg, uint32_t *val)
 {
-	uint8_t buf[OA_TC6_HDR_SIZE + 12] = { 0 };
-	struct spi_buf tx_buf = { .buf = buf, .len = sizeof(buf) };
-	const struct spi_buf_set tx = {	.buffers = &tx_buf, .count = 1 };
-	struct spi_buf rx_buf = { .buf = buf, .len = sizeof(buf) };
-	const struct spi_buf_set rx = {	.buffers = &rx_buf, .count = 1 };
-	uint32_t rv, rvn, hdr_bkp, *hdr = (uint32_t *) &buf[0];
+	uint8_t buf[OA_TC6_HDR_SIZE + 12] = {0};
+	struct spi_buf tx_buf = {.buf = buf, .len = sizeof(buf)};
+	const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1};
+	struct spi_buf rx_buf = {.buf = buf, .len = sizeof(buf)};
+	const struct spi_buf_set rx = {.buffers = &rx_buf, .count = 1};
+	uint32_t rv, rvn, hdr_bkp, *hdr = (uint32_t *)&buf[0];
 	int ret = 0;
 
 	/*
@@ -36,12 +37,10 @@ int oa_tc6_reg_read(struct oa_tc6 *tc6, const uint32_t reg, uint32_t *val)
 		rx_buf.len -= sizeof(rvn);
 	}
 
-	*hdr = FIELD_PREP(OA_CTRL_HDR_DNC, 0) |
-		FIELD_PREP(OA_CTRL_HDR_WNR, 0) |
-		FIELD_PREP(OA_CTRL_HDR_AID, 0) |
-		FIELD_PREP(OA_CTRL_HDR_MMS, reg >> 16) |
-		FIELD_PREP(OA_CTRL_HDR_ADDR, reg) |
-		FIELD_PREP(OA_CTRL_HDR_LEN, 0); /* To read single register len = 0 */
+	*hdr = FIELD_PREP(OA_CTRL_HDR_DNC, 0) | FIELD_PREP(OA_CTRL_HDR_WNR, 0) |
+	       FIELD_PREP(OA_CTRL_HDR_AID, 0) | FIELD_PREP(OA_CTRL_HDR_MMS, reg >> 16) |
+	       FIELD_PREP(OA_CTRL_HDR_ADDR, reg) |
+	       FIELD_PREP(OA_CTRL_HDR_LEN, 0); /* To read single register len = 0 */
 	*hdr |= FIELD_PREP(OA_CTRL_HDR_P, oa_tc6_get_parity(*hdr));
 	hdr_bkp = *hdr;
 	*hdr = sys_cpu_to_be32(*hdr);
@@ -76,13 +75,13 @@ int oa_tc6_reg_read(struct oa_tc6 *tc6, const uint32_t reg, uint32_t *val)
 
 int oa_tc6_reg_write(struct oa_tc6 *tc6, const uint32_t reg, uint32_t val)
 {
-	uint8_t buf_tx[OA_TC6_HDR_SIZE + 12] = { 0 };
-	uint8_t buf_rx[OA_TC6_HDR_SIZE + 12] = { 0 };
-	struct spi_buf tx_buf = { .buf = buf_tx, .len = sizeof(buf_tx) };
-	const struct spi_buf_set tx = {	.buffers = &tx_buf, .count = 1 };
-	struct spi_buf rx_buf = { .buf = buf_rx, .len = sizeof(buf_rx) };
-	const struct spi_buf_set rx = {	.buffers = &rx_buf, .count = 1	};
-	uint32_t rv, rvn, hdr_bkp, *hdr = (uint32_t *) &buf_tx[0];
+	uint8_t buf_tx[OA_TC6_HDR_SIZE + 12] = {0};
+	uint8_t buf_rx[OA_TC6_HDR_SIZE + 12] = {0};
+	struct spi_buf tx_buf = {.buf = buf_tx, .len = sizeof(buf_tx)};
+	const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1};
+	struct spi_buf rx_buf = {.buf = buf_rx, .len = sizeof(buf_rx)};
+	const struct spi_buf_set rx = {.buffers = &rx_buf, .count = 1};
+	uint32_t rv, rvn, hdr_bkp, *hdr = (uint32_t *)&buf_tx[0];
 	int ret;
 
 	/*
@@ -94,12 +93,10 @@ int oa_tc6_reg_write(struct oa_tc6 *tc6, const uint32_t reg, uint32_t val)
 		rx_buf.len -= sizeof(rvn);
 	}
 
-	*hdr = FIELD_PREP(OA_CTRL_HDR_DNC, 0) |
-		FIELD_PREP(OA_CTRL_HDR_WNR, 1) |
-		FIELD_PREP(OA_CTRL_HDR_AID, 0) |
-		FIELD_PREP(OA_CTRL_HDR_MMS, reg >> 16) |
-		FIELD_PREP(OA_CTRL_HDR_ADDR, reg) |
-		FIELD_PREP(OA_CTRL_HDR_LEN, 0); /* To read single register len = 0 */
+	*hdr = FIELD_PREP(OA_CTRL_HDR_DNC, 0) | FIELD_PREP(OA_CTRL_HDR_WNR, 1) |
+	       FIELD_PREP(OA_CTRL_HDR_AID, 0) | FIELD_PREP(OA_CTRL_HDR_MMS, reg >> 16) |
+	       FIELD_PREP(OA_CTRL_HDR_ADDR, reg) |
+	       FIELD_PREP(OA_CTRL_HDR_LEN, 0); /* To read single register len = 0 */
 	*hdr |= FIELD_PREP(OA_CTRL_HDR_P, oa_tc6_get_parity(*hdr));
 	hdr_bkp = *hdr;
 	*hdr = sys_cpu_to_be32(*hdr);
@@ -143,8 +140,7 @@ int oa_tc6_reg_write(struct oa_tc6 *tc6, const uint32_t reg, uint32_t val)
 	return ret;
 }
 
-int oa_tc6_reg_rmw(struct oa_tc6 *tc6, const uint32_t reg,
-		   uint32_t mask, uint32_t val)
+int oa_tc6_reg_rmw(struct oa_tc6 *tc6, const uint32_t reg, uint32_t mask, uint32_t val)
 {
 	uint32_t tmp;
 	int ret;
@@ -163,10 +159,74 @@ int oa_tc6_reg_rmw(struct oa_tc6 *tc6, const uint32_t reg,
 	return oa_tc6_reg_write(tc6, reg, tmp);
 }
 
+int oa_tc6_mdio_read(struct oa_tc6 *tc6, uint8_t prtad, uint8_t regad, uint16_t *data)
+{
+	return oa_tc6_reg_read(
+		tc6, OA_TC6_PHY_STD_REG_ADDR_BASE | (regad & OA_TC6_PHY_STD_REG_ADDR_MASK),
+		(uint32_t *)data);
+}
+
+int oa_tc6_mdio_write(struct oa_tc6 *tc6, uint8_t prtad, uint8_t regad, uint16_t data)
+{
+	return oa_tc6_reg_write(
+		tc6, OA_TC6_PHY_STD_REG_ADDR_BASE | (regad & OA_TC6_PHY_STD_REG_ADDR_MASK), data);
+}
+
+static int oa_tc6_get_phy_c45_mms(int devad)
+{
+	switch (devad) {
+	case MDIO_MMD_PCS:
+		return OA_TC6_PHY_C45_PCS_MMS2;
+	case MDIO_MMD_PMAPMD:
+		return OA_TC6_PHY_C45_PMA_PMD_MMS3;
+	case MDIO_MMD_VENDOR_SPECIFIC2:
+		return OA_TC6_PHY_C45_VS_PLCA_MMS4;
+	case MDIO_MMD_AN:
+		return OA_TC6_PHY_C45_AUTO_NEG_MMS5;
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+int oa_tc6_mdio_read_c45(struct oa_tc6 *tc6, uint8_t prtad, uint8_t devad, uint16_t regad,
+			 uint16_t *data)
+{
+	uint32_t tmp;
+	int ret;
+
+	ret = oa_tc6_get_phy_c45_mms(devad);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = oa_tc6_reg_read(tc6, (ret << 16) | regad, &tmp);
+	if (ret < 0) {
+		return ret;
+	}
+
+	*data = (uint16_t)tmp;
+
+	return 0;
+}
+
+int oa_tc6_mdio_write_c45(struct oa_tc6 *tc6, uint8_t prtad, uint8_t devad, uint16_t regad,
+			  uint16_t data)
+{
+	int ret;
+
+	ret = oa_tc6_get_phy_c45_mms(devad);
+	if (ret < 0) {
+		return ret;
+	}
+
+	return oa_tc6_reg_write(tc6, (ret << 16) | regad, (uint32_t)data);
+}
+
 int oa_tc6_set_protected_ctrl(struct oa_tc6 *tc6, bool prote)
 {
-	int ret = oa_tc6_reg_rmw(tc6, OA_CONFIG0, OA_CONFIG0_PROTE,
-				 prote ? OA_CONFIG0_PROTE : 0);
+	int ret;
+
+	ret = oa_tc6_reg_rmw(tc6, OA_CONFIG0, OA_CONFIG0_PROTE, prote ? OA_CONFIG0_PROTE : 0);
 	if (ret < 0) {
 		return ret;
 	}
@@ -199,18 +259,15 @@ int oa_tc6_send_chunks(struct oa_tc6 *tc6, struct net_pkt *pkt)
 
 	/* Transform struct net_pkt content into chunks */
 	for (i = 1; i <= chunks; i++) {
-		hdr = FIELD_PREP(OA_DATA_HDR_DNC, 1) |
-			FIELD_PREP(OA_DATA_HDR_DV, 1) |
-			FIELD_PREP(OA_DATA_HDR_NORX, 1) |
-			FIELD_PREP(OA_DATA_HDR_SWO, 0);
+		hdr = FIELD_PREP(OA_DATA_HDR_DNC, 1) | FIELD_PREP(OA_DATA_HDR_DV, 1) |
+		      FIELD_PREP(OA_DATA_HDR_NORX, 1) | FIELD_PREP(OA_DATA_HDR_SWO, 0);
 
 		if (i == 1) {
 			hdr |= FIELD_PREP(OA_DATA_HDR_SV, 1);
 		}
 
 		if (i == chunks) {
-			hdr |= FIELD_PREP(OA_DATA_HDR_EBO, len - 1) |
-				FIELD_PREP(OA_DATA_HDR_EV, 1);
+			hdr |= FIELD_PREP(OA_DATA_HDR_EBO, len - 1) | FIELD_PREP(OA_DATA_HDR_EV, 1);
 		}
 
 		hdr |= FIELD_PREP(OA_DATA_HDR_P, oa_tc6_get_parity(hdr));
@@ -277,8 +334,8 @@ static int oa_tc6_update_status(struct oa_tc6 *tc6, uint32_t ftr)
 	return 0;
 }
 
-int oa_tc6_chunk_spi_transfer(struct oa_tc6 *tc6, uint8_t *buf_rx, uint8_t *buf_tx,
-				     uint32_t hdr, uint32_t *ftr)
+int oa_tc6_chunk_spi_transfer(struct oa_tc6 *tc6, uint8_t *buf_rx, uint8_t *buf_tx, uint32_t hdr,
+			      uint32_t *ftr)
 {
 	struct spi_buf tx_buf[2];
 	struct spi_buf rx_buf[2];
@@ -318,9 +375,8 @@ int oa_tc6_read_status(struct oa_tc6 *tc6, uint32_t *ftr)
 {
 	uint32_t hdr;
 
-	hdr = FIELD_PREP(OA_DATA_HDR_DNC, 1) |
-		FIELD_PREP(OA_DATA_HDR_DV, 0) |
-		FIELD_PREP(OA_DATA_HDR_NORX, 1);
+	hdr = FIELD_PREP(OA_DATA_HDR_DNC, 1) | FIELD_PREP(OA_DATA_HDR_DV, 0) |
+	      FIELD_PREP(OA_DATA_HDR_NORX, 1);
 	hdr |= FIELD_PREP(OA_DATA_HDR_P, oa_tc6_get_parity(hdr));
 
 	return oa_tc6_chunk_spi_transfer(tc6, NULL, NULL, hdr, ftr);
@@ -445,7 +501,7 @@ int oa_tc6_read_chunks(struct oa_tc6 *tc6, struct net_pkt *pkt)
 
 	return 0;
 
- unref_buf:
+unref_buf:
 	net_buf_unref(buf_rx);
 	return ret;
 }
diff --git a/drivers/ethernet/oa_tc6.h b/drivers/ethernet/oa_tc6.h
index c61e0359d99..448e35e2794 100644
--- a/drivers/ethernet/oa_tc6.h
+++ b/drivers/ethernet/oa_tc6.h
@@ -13,72 +13,84 @@
 #include <zephyr/drivers/spi.h>
 #include <zephyr/net/net_pkt.h>
 
-#define MMS_REG(m, r) ((((m) & GENMASK(3, 0)) << 16) | ((r) & GENMASK(15, 0)))
+#define MMS_REG(m, r)        ((((m) & GENMASK(3, 0)) << 16) | ((r) & GENMASK(15, 0)))
 /* Memory Map Sector (MMS) 0 */
-#define OA_ID                         MMS_REG(0x0, 0x000) /* expect 0x11 */
-#define OA_PHYID                      MMS_REG(0x0, 0x001)
-#define OA_RESET                      MMS_REG(0x0, 0x003)
-#define OA_RESET_SWRESET              BIT(0)
-#define OA_CONFIG0                    MMS_REG(0x0, 0x004)
-#define OA_CONFIG0_SYNC               BIT(15)
-#define OA_CONFIG0_RFA_ZARFE          BIT(12)
-#define OA_CONFIG0_PROTE              BIT(5)
-#define OA_STATUS0                    MMS_REG(0x0, 0x008)
-#define OA_STATUS0_RESETC             BIT(6)
-#define OA_STATUS1                    MMS_REG(0x0, 0x009)
-#define OA_BUFSTS                     MMS_REG(0x0, 0x00B)
-#define OA_BUFSTS_TXC		      GENMASK(15, 8)
-#define OA_BUFSTS_RCA		      GENMASK(7, 0)
-#define OA_IMASK0                     MMS_REG(0x0, 0x00C)
-#define OA_IMASK0_TXPEM               BIT(0)
-#define OA_IMASK0_TXBOEM              BIT(1)
-#define OA_IMASK0_TXBUEM              BIT(2)
-#define OA_IMASK0_RXBOEM              BIT(3)
-#define OA_IMASK0_LOFEM               BIT(4)
-#define OA_IMASK0_HDREM               BIT(5)
-#define OA_IMASK1                     MMS_REG(0x0, 0x00D)
-#define OA_IMASK0_UV18M               BIT(19)
+#define OA_ID                MMS_REG(0x0, 0x000) /* expect 0x11 */
+#define OA_PHYID             MMS_REG(0x0, 0x001)
+#define OA_RESET             MMS_REG(0x0, 0x003)
+#define OA_RESET_SWRESET     BIT(0)
+#define OA_CONFIG0           MMS_REG(0x0, 0x004)
+#define OA_CONFIG0_SYNC      BIT(15)
+#define OA_CONFIG0_RFA_ZARFE BIT(12)
+#define OA_CONFIG0_PROTE     BIT(5)
+#define OA_STATUS0           MMS_REG(0x0, 0x008)
+#define OA_STATUS0_RESETC    BIT(6)
+#define OA_STATUS1           MMS_REG(0x0, 0x009)
+#define OA_BUFSTS            MMS_REG(0x0, 0x00B)
+#define OA_BUFSTS_TXC        GENMASK(15, 8)
+#define OA_BUFSTS_RCA        GENMASK(7, 0)
+#define OA_IMASK0            MMS_REG(0x0, 0x00C)
+#define OA_IMASK0_TXPEM      BIT(0)
+#define OA_IMASK0_TXBOEM     BIT(1)
+#define OA_IMASK0_TXBUEM     BIT(2)
+#define OA_IMASK0_RXBOEM     BIT(3)
+#define OA_IMASK0_LOFEM      BIT(4)
+#define OA_IMASK0_HDREM      BIT(5)
+#define OA_IMASK1            MMS_REG(0x0, 0x00D)
+#define OA_IMASK0_UV18M      BIT(19)
 
 /* OA Control header */
-#define OA_CTRL_HDR_DNC		      BIT(31)
-#define OA_CTRL_HDR_HDRB	      BIT(30)
-#define OA_CTRL_HDR_WNR		      BIT(29)
-#define OA_CTRL_HDR_AID		      BIT(28)
-#define OA_CTRL_HDR_MMS		      GENMASK(27, 24)
-#define OA_CTRL_HDR_ADDR	      GENMASK(23, 8)
-#define OA_CTRL_HDR_LEN		      GENMASK(7, 1)
-#define OA_CTRL_HDR_P		      BIT(0)
+#define OA_CTRL_HDR_DNC  BIT(31)
+#define OA_CTRL_HDR_HDRB BIT(30)
+#define OA_CTRL_HDR_WNR  BIT(29)
+#define OA_CTRL_HDR_AID  BIT(28)
+#define OA_CTRL_HDR_MMS  GENMASK(27, 24)
+#define OA_CTRL_HDR_ADDR GENMASK(23, 8)
+#define OA_CTRL_HDR_LEN  GENMASK(7, 1)
+#define OA_CTRL_HDR_P    BIT(0)
 
 /* OA Data header */
-#define OA_DATA_HDR_DNC		      BIT(31)
-#define OA_DATA_HDR_SEQ		      BIT(30)
-#define OA_DATA_HDR_NORX              BIT(29)
-#define OA_DATA_HDR_DV		      BIT(21)
-#define OA_DATA_HDR_SV		      BIT(20)
-#define OA_DATA_HDR_SWO		      GENMASK(19, 16)
-#define OA_DATA_HDR_EV		      BIT(14)
-#define OA_DATA_HDR_EBO		      GENMASK(13, 8)
-#define OA_DATA_HDR_P		      BIT(0)
+#define OA_DATA_HDR_DNC  BIT(31)
+#define OA_DATA_HDR_SEQ  BIT(30)
+#define OA_DATA_HDR_NORX BIT(29)
+#define OA_DATA_HDR_DV   BIT(21)
+#define OA_DATA_HDR_SV   BIT(20)
+#define OA_DATA_HDR_SWO  GENMASK(19, 16)
+#define OA_DATA_HDR_EV   BIT(14)
+#define OA_DATA_HDR_EBO  GENMASK(13, 8)
+#define OA_DATA_HDR_P    BIT(0)
 
 /* OA Data footer */
-#define OA_DATA_FTR_EXST	      BIT(31)
-#define OA_DATA_FTR_HDRB	      BIT(30)
-#define OA_DATA_FTR_SYNC	      BIT(29)
-#define OA_DATA_FTR_RCA		      GENMASK(28, 24)
-#define OA_DATA_FTR_DV		      BIT(21)
-#define OA_DATA_FTR_SV		      BIT(20)
-#define OA_DATA_FTR_SWO		      GENMASK(19, 16)
-#define OA_DATA_FTR_FD		      BIT(15)
-#define OA_DATA_FTR_EV		      BIT(14)
-#define OA_DATA_FTR_EBO		      GENMASK(13, 8)
-#define OA_DATA_FTR_TXC		      GENMASK(5, 1)
-#define OA_DATA_FTR_P		      BIT(0)
-
-#define OA_TC6_HDR_SIZE		      4
-#define OA_TC6_FTR_SIZE		      4
-#define OA_TC6_BUF_ALLOC_TIMEOUT      K_MSEC(10)
-#define OA_TC6_FTR_RCA_MAX	      GENMASK(4, 0)
-#define OA_TC6_FTR_TXC_MAX	      GENMASK(4, 0)
+#define OA_DATA_FTR_EXST BIT(31)
+#define OA_DATA_FTR_HDRB BIT(30)
+#define OA_DATA_FTR_SYNC BIT(29)
+#define OA_DATA_FTR_RCA  GENMASK(28, 24)
+#define OA_DATA_FTR_DV   BIT(21)
+#define OA_DATA_FTR_SV   BIT(20)
+#define OA_DATA_FTR_SWO  GENMASK(19, 16)
+#define OA_DATA_FTR_FD   BIT(15)
+#define OA_DATA_FTR_EV   BIT(14)
+#define OA_DATA_FTR_EBO  GENMASK(13, 8)
+#define OA_DATA_FTR_TXC  GENMASK(5, 1)
+#define OA_DATA_FTR_P    BIT(0)
+
+#define OA_TC6_HDR_SIZE          4
+#define OA_TC6_FTR_SIZE          4
+#define OA_TC6_BUF_ALLOC_TIMEOUT K_MSEC(10)
+#define OA_TC6_FTR_RCA_MAX       GENMASK(4, 0)
+#define OA_TC6_FTR_TXC_MAX       GENMASK(4, 0)
+
+/* PHY Clause 22 registers base address and mask */
+#define OA_TC6_PHY_STD_REG_ADDR_BASE 0xFF00
+#define OA_TC6_PHY_STD_REG_ADDR_MASK 0x1F
+
+/* PHY – Clause 45 registers memory map selector (MMS) as per table 6 in the
+ * OPEN Alliance specification.
+ */
+#define OA_TC6_PHY_C45_PCS_MMS2      2 /* MMD 3 */
+#define OA_TC6_PHY_C45_PMA_PMD_MMS3  3 /* MMD 1 */
+#define OA_TC6_PHY_C45_VS_PLCA_MMS4  4 /* MMD 31 */
+#define OA_TC6_PHY_C45_AUTO_NEG_MMS5 5 /* MMD 7 */
 
 /**
  * @brief OA TC6 data.
@@ -112,12 +124,6 @@ struct oa_tc6 {
 	struct net_buf *concat_buf;
 };
 
-typedef struct {
-	uint8_t mms;
-	uint8_t address;
-	uint16_t value;
-} oa_mem_map_t;
-
 /**
  * @brief Calculate parity bit from data
  *
@@ -212,8 +218,8 @@ int oa_tc6_read_chunks(struct oa_tc6 *tc6, struct net_pkt *pkt);
  *
  * @return 0 if transmission was successful, <0 otherwise.
  */
-int oa_tc6_chunk_spi_transfer(struct oa_tc6 *tc6, uint8_t *buf_rx, uint8_t *buf_tx,
-			      uint32_t hdr, uint32_t *ftr);
+int oa_tc6_chunk_spi_transfer(struct oa_tc6 *tc6, uint8_t *buf_rx, uint8_t *buf_tx, uint32_t hdr,
+			      uint32_t *ftr);
 
 /**
  * @brief Read status from OA TC6 device
@@ -239,8 +245,7 @@ int oa_tc6_read_status(struct oa_tc6 *tc6, uint32_t *ftr);
  *
  * @return 0 if successful, <0 otherwise.
  */
-int oa_tc6_reg_rmw(struct oa_tc6 *tc6, const uint32_t reg,
-		   uint32_t mask, uint32_t val);
+int oa_tc6_reg_rmw(struct oa_tc6 *tc6, const uint32_t reg, uint32_t mask, uint32_t val);
 
 /**
  * @brief Check the status of OA TC6 device
@@ -250,4 +255,68 @@ int oa_tc6_reg_rmw(struct oa_tc6 *tc6, const uint32_t reg,
  * @return 0 if successful, <0 otherwise.
  */
 int oa_tc6_check_status(struct oa_tc6 *tc6);
+
+/**
+ * @brief      Read C22 registers using MDIO Bus
+ *
+ * This routine provides an interface to perform a C22 register read on the
+ * MAC-PHY MDIO bus.
+ *
+ * @param[in]  tc6         Pointer to the tc6 structure for the MAC-PHY
+ * @param[in]  prtad       Port address
+ * @param[in]  regad       Register address
+ * @param      data        Pointer to receive read data
+ *
+ * @return 0 if successful, <0 otherwise.
+ */
+int oa_tc6_mdio_read(struct oa_tc6 *tc6, uint8_t prtad, uint8_t regad, uint16_t *data);
+
+/**
+ * @brief      Write C22 registers using MDIO Bus
+ *
+ * This routine provides an interface to perform a C22 register write on the
+ * MAC-PHY MDIO bus.
+ *
+ * @param[in]  tc6         Pointer to the tc6 structure for the MAC-PHY
+ * @param[in]  prtad       Port address
+ * @param[in]  regad       Register address
+ * @param[in]  data        Write data
+ *
+ * @return 0 if successful, <0 otherwise.
+ */
+int oa_tc6_mdio_write(struct oa_tc6 *tc6, uint8_t prtad, uint8_t regad, uint16_t data);
+
+/**
+ * @brief      Read C45 registers using MDIO Bus
+ *
+ * This routine provides an interface to perform a C45 register read on the
+ * MAC-PHY MDIO bus.
+ *
+ * @param[in]  tc6         Pointer to the tc6 structure for the MAC-PHY
+ * @param[in]  prtad       Port address
+ * @param[in]  devad       MMD device address
+ * @param[in]  regad       Register address
+ * @param      data        Pointer to receive read data
+ *
+ * @return 0 if successful, <0 otherwise.
+ */
+int oa_tc6_mdio_read_c45(struct oa_tc6 *tc6, uint8_t prtad, uint8_t devad, uint16_t regad,
+			 uint16_t *data);
+
+/**
+ * @brief      Write C45 registers using MDIO Bus
+ *
+ * This routine provides an interface to perform a C45 register write on the
+ * MAC-PHY MDIO bus.
+ *
+ * @param[in]  tc6         Pointer to the tc6 structure for the MAC-PHY
+ * @param[in]  prtad       Port address
+ * @param[in]  devad       MMD device address
+ * @param[in]  regad       Register address
+ * @param[in]  data        Write data
+ *
+ * @return 0 if successful, <0 otherwise.
+ */
+int oa_tc6_mdio_write_c45(struct oa_tc6 *tc6, uint8_t prtad, uint8_t devad, uint16_t regad,
+			  uint16_t data);
 #endif /* OA_TC6_CFG_H__ */
diff --git a/drivers/ethernet/phy/CMakeLists.txt b/drivers/ethernet/phy/CMakeLists.txt
index 32c218fdd5e..34d769eca6c 100644
--- a/drivers/ethernet/phy/CMakeLists.txt
+++ b/drivers/ethernet/phy/CMakeLists.txt
@@ -1,10 +1,17 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_library_sources_ifdef(CONFIG_PHY_GENERIC_MII	phy_mii.c)
+
+# zephyr-keep-sorted-start
 zephyr_library_sources_ifdef(CONFIG_PHY_ADIN2111	phy_adin2111.c)
 zephyr_library_sources_ifdef(CONFIG_PHY_DM8806	phy_dm8806.c)
-zephyr_library_sources_ifdef(CONFIG_PHY_TJA1103	        phy_tja1103.c)
 zephyr_library_sources_ifdef(CONFIG_PHY_MICROCHIP_KSZ8081	phy_microchip_ksz8081.c)
-zephyr_library_sources_ifdef(CONFIG_PHY_TI_DP83825  phy_ti_dp83825.c)
-zephyr_library_sources_ifdef(CONFIG_PHY_REALTEK_RTL8211F phy_realtek_rtl8211f.c)
+zephyr_library_sources_ifdef(CONFIG_PHY_MICROCHIP_T1S phy_microchip_t1s.c)
+zephyr_library_sources_ifdef(CONFIG_PHY_MICROCHIP_VSC8541 phy_microchip_vsc8541.c)
+zephyr_library_sources_ifdef(CONFIG_PHY_OA_TC14_PLCA_LIB phy_oa_tc14_plca.c)
 zephyr_library_sources_ifdef(CONFIG_PHY_QUALCOMM_AR8031 phy_qualcomm_ar8031.c)
+zephyr_library_sources_ifdef(CONFIG_PHY_REALTEK_RTL8211F phy_realtek_rtl8211f.c)
+zephyr_library_sources_ifdef(CONFIG_PHY_TI_DP83825  phy_ti_dp83825.c)
+zephyr_library_sources_ifdef(CONFIG_PHY_TI_DP83867  phy_ti_dp83867.c)
+zephyr_library_sources_ifdef(CONFIG_PHY_TJA1103	        phy_tja1103.c)
+# zephyr-keep-sorted-stop
diff --git a/drivers/ethernet/phy/Kconfig b/drivers/ethernet/phy/Kconfig
index dfb9862aca7..c9d0c61baa2 100644
--- a/drivers/ethernet/phy/Kconfig
+++ b/drivers/ethernet/phy/Kconfig
@@ -16,6 +16,7 @@ module-help = Sets log level for Ethernet PHY Device Drivers.
 source "subsys/net/Kconfig.template.log_config.net"
 source "drivers/ethernet/phy/Kconfig.tja1103"
 source "drivers/ethernet/phy/Kconfig.dm8806"
+source "drivers/ethernet/phy/Kconfig.microchip_t1s"
 
 config PHY_INIT_PRIORITY
 	int "Ethernet PHY driver init priority"
@@ -50,6 +51,15 @@ config PHY_MICROCHIP_KSZ8081
 	help
 	  Enable Microchip KSZ8081 Ethernet PHY Driver
 
+config PHY_MICROCHIP_VSC8541
+	bool "Microchip VSC8541 PHY Driver"
+	default y
+	depends on DT_HAS_MICROCHIP_VSC8541_ENABLED
+	depends on MDIO
+	depends on GPIO
+	help
+	  Enable Microchip VSC8541 Ethernet PHY Driver
+
 config PHY_TI_DP83825
 	bool "TI DP83825 PHY Driver"
 	default y
@@ -59,6 +69,15 @@ config PHY_TI_DP83825
 	help
 	  Enable TI DP83825 Ethernet PHY Driver
 
+config PHY_TI_DP83867
+	bool "TI DP83867 PHY Driver"
+	default y
+	depends on DT_HAS_TI_DP83867_ENABLED
+	depends on MDIO
+	depends on GPIO
+	help
+	  Enable TI DP83867 Ethernet PHY Driver
+
 config PHY_REALTEK_RTL8211F
 	bool "Realtek RTL8211F PHY Driver"
 	default y
@@ -92,4 +111,15 @@ config PHY_MONITOR_PERIOD
 	  periodically executed to detect and report any changes in the
 	  PHY link status to the operating system.
 
+config PHY_OA_TC14_PLCA_LIB
+	bool "Open Alliance TC14 PLCA generic lib"
+	help
+	  Enable Open Alliance TC14 PLCA generic lib.
+
+config PHY_VERIFY_DEVICE_IDENTIFICATION
+	bool "Verify selected phy to actual reported phy chip id"
+	help
+	  Verify the organizationally unique identifier that is reported
+	  by the phy chip.
+
 endif # "Ethernet PHY Drivers"
diff --git a/drivers/ethernet/phy/Kconfig.dm8806 b/drivers/ethernet/phy/Kconfig.dm8806
index bab9a5d0ad8..e952420f7f0 100644
--- a/drivers/ethernet/phy/Kconfig.dm8806
+++ b/drivers/ethernet/phy/Kconfig.dm8806
@@ -29,6 +29,13 @@ config PHY_DM8806_TRIGGER_GLOBAL_THREAD
 
 endchoice
 
+config PHY_DM8806_ENERGY_EFFICIENT_MODE
+	bool "Energy efficient mode"
+	help
+	  By default in DM8806, the energy efficient mode is enabled.
+	  It had been observed that the network randomly fails when
+	  this mode is on. Thus, this symbol is by default disabled.
+
 config PHY_DM8806_TRIGGER
 	bool
 
@@ -46,4 +53,25 @@ config PHY_DM8806_THREAD_STACK_SIZE
 	help
 	  Stack size of thread used by the driver to handle interrupts.
 
-endif # PHY_DM8806_TRIGGER
+config PHY_DM8806_SMI_BUS_CHECK
+	bool "Host SMI bus error check function"
+	default y
+	help
+	  This functionality prevents the host SMI bus to be interferered by the
+	  noise on board-level. During write procedure, the written value in
+	  register will be applied until the correct checksum is written. In read
+	  procedure, the hardware calculated checksum is compared with the software
+	  calculated one to detect correctness of received data.
+
+config PHY_DM8806_SMI_BUS_CHECK_REPETITION
+	int "SMI bus transmission repetitions"
+	depends on PHY_DM8806_SMI_BUS_CHECK
+	default 5
+	help
+	  The numbers of SMI bus transmission repetition in case if CRC checksum
+	  fails during read or write. After this numbers of repetition, the reading
+	  message is dropped and will not be passed to the system. In write
+	  procedure, the written value in register will be applied until the correct
+	  checksum is written to the PHY register.
+
+endif # PHY_DM8806
diff --git a/drivers/ethernet/phy/Kconfig.microchip_t1s b/drivers/ethernet/phy/Kconfig.microchip_t1s
new file mode 100644
index 00000000000..c339a7545b6
--- /dev/null
+++ b/drivers/ethernet/phy/Kconfig.microchip_t1s
@@ -0,0 +1,22 @@
+# Copyright 2025 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig PHY_MICROCHIP_T1S
+	bool "Microchip 10BASE-T1S Ethernet PHYs Driver"
+	default y
+	depends on DT_HAS_MICROCHIP_T1S_PHY_ENABLED
+	depends on MDIO
+	select PHY_OA_TC14_PLCA_LIB
+	help
+	  Enable Microchip's LAN8650/1 Rev.B0/B1 Internal PHYs and
+	  LAN8670/1/2 Rev.C1/C2 PHYs Driver.
+
+if PHY_MICROCHIP_T1S
+
+config PHY_MICROCHIP_T1S_INIT_PRIORITY
+	int "Microchip T1S PHY init priority"
+	default 82
+	help
+	  Microchip T1S phy device driver initialization priority.
+
+endif
diff --git a/drivers/ethernet/phy/phy_adin2111.c b/drivers/ethernet/phy/phy_adin2111.c
index 5f762ce6919..1b7a042d9d4 100644
--- a/drivers/ethernet/phy/phy_adin2111.c
+++ b/drivers/ethernet/phy/phy_adin2111.c
@@ -5,20 +5,20 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/logging/log.h>
-
-LOG_MODULE_REGISTER(DT_DRV_COMPAT, CONFIG_PHY_LOG_LEVEL);
-
 #include <errno.h>
 #include <stdint.h>
 #include <stdbool.h>
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
-#include <zephyr/sys/util.h>
-#include <zephyr/net/phy.h>
-#include <zephyr/net/mii.h>
-#include <zephyr/net/mdio.h>
 #include <zephyr/drivers/mdio.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net/mdio.h>
+#include <zephyr/net/mii.h>
+#include <zephyr/net/phy.h>
+#include <zephyr/sys/util.h>
+#include "phy_adin2111_priv.h"
+
+LOG_MODULE_REGISTER(phy_adin, CONFIG_PHY_LOG_LEVEL);
 
 /* PHYs out of reset check retry delay */
 #define ADIN2111_PHY_AWAIT_DELAY_POLL_US			15U
diff --git a/drivers/ethernet/phy/phy_dm8806.c b/drivers/ethernet/phy/phy_dm8806.c
index 76ae387316d..34f09bb975f 100644
--- a/drivers/ethernet/phy/phy_dm8806.c
+++ b/drivers/ethernet/phy/phy_dm8806.c
@@ -42,6 +42,204 @@ struct phy_dm8806_data {
 #endif
 };
 
+#ifdef CONFIG_PHY_DM8806_SMI_BUS_CHECK
+static uint16_t phy_calculate_checksum(uint16_t data, uint16_t reg_addr, uint8_t opcode)
+{
+	uint16_t csum[8];
+	uint16_t checksum = 0;
+
+	/* Checksum calculated formula proposed by Davicom on datasheet:
+	 * DM8806-DAVICOM - par. 7.2.1:
+	 * Host SMI Bus Error Check Function, page 141.
+	 */
+	csum[0] = (((data >> 0) & 1) ^ ((data >> 8) & 1) ^ ((reg_addr >> 0) & 1) ^
+		   ((reg_addr >> 8) & 1));
+	csum[1] = (((data >> 1) & 1) ^ ((data >> 9) & 1) ^ ((reg_addr >> 1) & 1) ^
+		   ((reg_addr >> 9) & 1));
+	csum[2] = (((data >> 2) & 1) ^ ((data >> 10) & 1) ^ ((reg_addr >> 2) & 1) ^
+		   ((opcode >> 0) & 1));
+	csum[3] = (((data >> 3) & 1) ^ ((data >> 11) & 1) ^ ((reg_addr >> 3) & 1) ^
+		   ((opcode >> 1) & 1));
+	csum[4] = (((data >> 4) & 1) ^ ((data >> 12) & 1) ^ ((reg_addr >> 4) & 1));
+	csum[5] = (((data >> 5) & 1) ^ ((data >> 13) & 1) ^ ((reg_addr >> 5) & 1));
+	csum[6] = (((data >> 6) & 1) ^ ((data >> 14) & 1) ^ ((reg_addr >> 6) & 1));
+	csum[7] = (((data >> 7) & 1) ^ ((data >> 15) & 1) ^ ((reg_addr >> 7) & 1));
+	for (int cnt = 0; cnt < 8; cnt++) {
+		checksum |= (csum[cnt] << cnt);
+	}
+	return checksum;
+}
+#endif
+
+static int phy_dm8806_write_reg(const struct device *dev, uint8_t phyad, uint8_t regad,
+				uint16_t data)
+{
+	int res = 0;
+	const struct phy_dm8806_config *cfg = dev->config;
+
+/* SMI bus check function should be activated each time, before writing
+ * procedure to the DM8806 registers. This is standard procedure described in
+ * the datasheet of the DM8806.
+ */
+#ifdef CONFIG_PHY_DM8806_SMI_BUS_CHECK
+	uint16_t checksum_status;
+	bool checksum_mismatch;
+	uint16_t sw_checksum = 0;
+	uint16_t abs_reg;
+	int repetition = 0;
+
+	do {
+		/* Set register 33AH.[0] = 1 to enable SMI Bus Error Check function. */
+		res = mdio_write(cfg->mdio, DM8806_SMI_BUS_CTRL_PHY_ADDRESS,
+				 DM8806_SMI_BUS_CTRL_REG_ADDRESS, DM8806_SMI_ECE);
+		if (res < 0) {
+			LOG_ERR("Failed to write data to PHY register: SMI_BUS_CTRL_REG_ADDRESS, "
+				"error code: %d",
+				res);
+			return res;
+		}
+#endif
+		res = mdio_write(cfg->mdio, phyad, regad, data);
+		if (res < 0) {
+			LOG_ERR("Failed to read data from PHY, error code: %d", res);
+			return res;
+		}
+#ifdef CONFIG_PHY_DM8806_SMI_BUS_CHECK
+		/* Calculate checksum */
+		abs_reg = (phyad << DM8806_REGAD_WIDTH);
+		abs_reg |= (regad & BIT_MASK(DM8806_REGAD_WIDTH));
+		sw_checksum = phy_calculate_checksum(data, abs_reg, DM8806_PHY_WRITE);
+		sw_checksum &= BIT_MASK(8);
+		/* Write calculated checksum to the PHY register 339H.[7:0] */
+		res = mdio_write(cfg->mdio, DM8806_SMI_BUS_ERR_CHK_PHY_ADDRESS,
+				 DM8806_SMI_BUS_ERR_CHK_REG_ADDRESS, sw_checksum);
+		if (res < 0) {
+			LOG_ERR("Failed to write calculated checksum to the PHY register, "
+				"error code: %d",
+				res);
+			return res;
+		}
+
+		/* Read status of the checksum from Serial Bus Error Check Register
+		 * 339H.[8].
+		 */
+		res = mdio_read(cfg->mdio, DM8806_SMI_BUS_ERR_CHK_PHY_ADDRESS,
+				DM8806_SMI_BUS_ERR_CHK_REG_ADDRESS, &checksum_status);
+		if (res < 0) {
+			LOG_ERR("Failed to read hardware calculated checksum from PHY, error code: "
+				"%d",
+				res);
+			return res;
+		}
+		/* Checksum status is present on the 8-th bit of the Serial Bus Error
+		 * Check Register (339h) [8].
+		 */
+		checksum_mismatch = (bool)(checksum_status & BIT(DM8806_SMI_ERR));
+
+		/* Repeat the writing procedure for the number of attempts defined in
+		 * KConfig after which the transfer will failed.
+		 */
+		if (CONFIG_PHY_DM8806_SMI_BUS_CHECK_REPETITION > 0) {
+			repetition++;
+			if (checksum_mismatch) {
+				LOG_WRN("%d repeat of PHY read procedure due to checksum error.",
+					repetition);
+				if (repetition >= CONFIG_PHY_DM8806_SMI_BUS_CHECK_REPETITION) {
+					LOG_ERR("Maximum number of PHY write repetition exceed.");
+					res = (-EIO);
+				}
+			} else {
+				break;
+			}
+			/* Do not repeat the transfer if repetition number is set to 0. Just check
+			 * the checksum in this case and report the error in case of wrong checksum
+			 * sum.
+			 */
+		} else {
+			if (checksum_mismatch) {
+				LOG_ERR("Wrong checksum, during PHY write procedure.");
+				res = (-EIO);
+				break;
+			}
+		}
+	} while (repetition < CONFIG_PHY_DM8806_SMI_BUS_CHECK_REPETITION);
+#endif
+
+	return res;
+}
+
+static int phy_dm8806_read_reg(const struct device *dev, uint8_t phyad, uint8_t regad,
+			       uint16_t *data)
+{
+	int res = 0;
+	const struct phy_dm8806_config *cfg = dev->config;
+
+/* SMI bus check function should be activated each time, before reading
+ * procedure to the DM8806 registers. This is standard procedure described in
+ * the datasheet of the DM8806.
+ */
+#ifdef CONFIG_PHY_DM8806_SMI_BUS_CHECK
+	uint16_t hw_checksum;
+	uint16_t sw_checksum = 0;
+	uint16_t abs_reg;
+	int repetition = 0;
+
+	do {
+		/* Set register 33AH.[0] = 1 to enable SMI Bus Error Check function. */
+		res = mdio_write(cfg->mdio, DM8806_SMI_BUS_CTRL_PHY_ADDRESS,
+				 DM8806_SMI_BUS_CTRL_REG_ADDRESS, DM8806_SMI_ECE);
+		if (res < 0) {
+			LOG_ERR("Failed to write data to PHY register: SMI_BUS_CTRL_REG_ADDRESS, "
+				"error code: %d",
+				res);
+			return res;
+		}
+#endif
+		res = mdio_read(cfg->mdio, phyad, regad, data);
+		if (res < 0) {
+			LOG_ERR("Failed to read data from PHY, error code: %d", res);
+			return res;
+		}
+#ifdef CONFIG_PHY_DM8806_SMI_BUS_CHECK
+		/* Read hardware calculated checksum from Serial Bus Error Check Register. */
+		res = mdio_read(cfg->mdio, DM8806_SMI_BUS_ERR_CHK_PHY_ADDRESS,
+				DM8806_SMI_BUS_ERR_CHK_REG_ADDRESS, &hw_checksum);
+		if (res < 0) {
+			LOG_ERR("Failed to read hardware calculated checksum from PHY, error code: "
+				"%d",
+				res);
+			return res;
+		}
+		/* Calculate checksum */
+		abs_reg = (phyad << DM8806_REGAD_WIDTH);
+		abs_reg |= (regad & BIT_MASK(DM8806_REGAD_WIDTH));
+		sw_checksum = phy_calculate_checksum(*data, abs_reg, DM8806_PHY_READ);
+
+		if (CONFIG_PHY_DM8806_SMI_BUS_CHECK_REPETITION > 0) {
+			repetition++;
+			if (hw_checksum != sw_checksum) {
+				LOG_WRN("%d repeat of PHY read procedure due to checksum error.",
+					repetition);
+				if (repetition >= CONFIG_PHY_DM8806_SMI_BUS_CHECK_REPETITION) {
+					LOG_ERR("Maximum number of PHY read repetition exceed.");
+					res = (-EIO);
+				}
+			} else {
+				break;
+			}
+		} else {
+			if (hw_checksum != sw_checksum) {
+				LOG_ERR("Wrong checksum, during PHY read procedure.");
+				res = (-EIO);
+				break;
+			}
+		}
+	} while (repetition < CONFIG_PHY_DM8806_SMI_BUS_CHECK_REPETITION);
+#endif
+
+	return res;
+}
+
 static void phy_dm8806_gpio_callback(const struct device *dev, struct gpio_callback *cb,
 				     uint32_t pins)
 {
@@ -66,9 +264,9 @@ static void phy_dm8806_thread_cb(const struct device *dev, struct phy_link_state
 	/* Clear the interrupt flag, by writing "1" to LNKCHG bit of Interrupt Status
 	 * Register (318h)
 	 */
-	mdio_read(cfg->mdio, INT_STAT_PHY_ADDR, INT_STAT_REG_ADDR, &data);
+	mdio_read(cfg->mdio, DM8806_INT_STAT_PHY_ADDR, DM8806_INT_STAT_REG_ADDR, &data);
 	data |= 0x1;
-	mdio_write(cfg->mdio, INT_STAT_PHY_ADDR, INT_STAT_REG_ADDR, data);
+	mdio_write(cfg->mdio, DM8806_INT_STAT_PHY_ADDR, DM8806_INT_STAT_REG_ADDR, data);
 	gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_EDGE_TO_ACTIVE);
 }
 
@@ -90,13 +288,13 @@ int phy_dm8806_port_init(const struct device *dev)
 	const struct phy_dm8806_config *cfg = dev->config;
 
 	res = gpio_pin_configure_dt(&cfg->gpio_rst, (GPIO_OUTPUT_INACTIVE | GPIO_PULL_UP));
-	if (res != 0) {
+	if (res < 0) {
 		LOG_ERR("Failed to configure gpio reset pin for PHY DM886 as an output");
 		return res;
 	}
 	/* Hardware reset of the PHY DM8806 */
 	gpio_pin_set_dt(&cfg->gpio_rst, true);
-	if (res != 0) {
+	if (res < 0) {
 		LOG_ERR("Failed to assert gpio reset pin of the PHY DM886 to physical 0");
 		return res;
 	}
@@ -105,7 +303,7 @@ int phy_dm8806_port_init(const struct device *dev)
 	 */
 	k_msleep(10);
 	res = gpio_pin_set_dt(&cfg->gpio_rst, false);
-	if (res != 0) {
+	if (res < 0) {
 		LOG_ERR("Failed to assert gpio reset pin of the PHY DM886 to physical 1");
 		return res;
 	}
@@ -125,13 +323,15 @@ int phy_dm8806_init_interrupt(const struct device *dev)
 	 * Activate global interrupt by writing "1" to LNKCHG of Interrupt Mask
 	 * And Control Register (319h)
 	 */
-	res = mdio_read(cfg->mdio, INT_MASK_CTRL_PHY_ADDR, INT_MASK_CTRL_REG_ADDR, &data);
+	res = mdio_read(cfg->mdio, DM8806_INT_MASK_CTRL_PHY_ADDR, DM8806_INT_MASK_CTRL_REG_ADDR,
+			&data);
 	if (res) {
 		LOG_ERR("Failed to read IRQ_LED_CONTROL, %i", res);
 		return res;
 	}
 	data |= 0x1;
-	res = mdio_write(cfg->mdio, INT_MASK_CTRL_PHY_ADDR, INT_MASK_CTRL_REG_ADDR, data);
+	res = mdio_write(cfg->mdio, DM8806_INT_MASK_CTRL_PHY_ADDR, DM8806_INT_MASK_CTRL_REG_ADDR,
+			 data);
 	if (res) {
 		LOG_ERR("Failed to read IRQ_LED_CONTROL, %i", res);
 		return res;
@@ -140,13 +340,15 @@ int phy_dm8806_init_interrupt(const struct device *dev)
 	/* Activate interrupt per Ethernet port by writing "1" to LNK_EN0~3
 	 * of WoL Control Register (2BBh)
 	 */
-	res = mdio_read(cfg->mdio, WOLL_CTRL_REG_PHY_ADDR, WOLL_CTRL_REG_REG_ADDR, &data);
+	res = mdio_read(cfg->mdio, DM8806_WOLL_CTRL_REG_PHY_ADDR, DM8806_WOLL_CTRL_REG_REG_ADDR,
+			&data);
 	if (res) {
 		LOG_ERR("Failed to read IRQ_LED_CONTROL, %i", res);
 		return res;
 	}
 	data |= 0xF;
-	res = mdio_write(cfg->mdio, WOLL_CTRL_REG_PHY_ADDR, WOLL_CTRL_REG_REG_ADDR, data);
+	res = mdio_write(cfg->mdio, DM8806_WOLL_CTRL_REG_PHY_ADDR, DM8806_WOLL_CTRL_REG_REG_ADDR,
+			 data);
 	if (res) {
 		LOG_ERR("Failed to read IRQ_LED_CONTROL, %i", res);
 		return res;
@@ -162,7 +364,7 @@ int phy_dm8806_init_interrupt(const struct device *dev)
 	}
 	drv_data->dev = dev;
 	res = gpio_pin_configure_dt(&cfg->gpio_int, GPIO_INPUT);
-	if (res != 0) {
+	if (res < 0) {
 		LOG_ERR("Failed to configure gpio interrupt pin for PHY DM886 as an input");
 		return res;
 	}
@@ -171,7 +373,7 @@ int phy_dm8806_init_interrupt(const struct device *dev)
 	 */
 	gpio_init_callback(&drv_data->gpio_cb, phy_dm8806_gpio_callback, BIT(cfg->gpio_int.pin));
 	res = gpio_add_callback(cfg->gpio_int.port, &drv_data->gpio_cb);
-	if (res != 0) {
+	if (res < 0) {
 		LOG_ERR("Failed to set PHY DM886 gpio callback");
 		return res;
 	}
@@ -183,7 +385,7 @@ int phy_dm8806_init_interrupt(const struct device *dev)
 	 * level 1 asserted by Davicom PHY DM8806 interrupt Pin
 	 */
 	gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_EDGE_TO_ACTIVE);
-	if (res != 0) {
+	if (res < 0) {
 		LOG_ERR("Failed to configure PHY DM886 gpio interrupt pin trigger for "
 			"active edge");
 		return res;
@@ -207,36 +409,58 @@ static int phy_dm8806_init(const struct device *dev)
 		return ret;
 	}
 
-	ret = mdio_read(cfg->mdio, PHY_ADDRESS_18H, PORT5_MAC_CONTROL, &val);
+	ret = mdio_read(cfg->mdio, DM8806_PHY_ADDRESS_18H, DM8806_PORT5_MAC_CONTROL, &val);
 	if (ret) {
 		LOG_ERR("Failed to read PORT5_MAC_CONTROL: %i", ret);
 		return ret;
 	}
 
 	/* Activate default working mode*/
-	val |= (P5_50M_INT_CLK_SOURCE | P5_50M_CLK_OUT_ENABLE | P5_EN_FORCE);
-	val &= (P5_SPEED_100M | P5_FULL_DUPLEX | P5_FORCE_LINK_ON);
+	val |= (DM8806_P5_50M_INT_CLK_SOURCE | DM8806_P5_50M_CLK_OUT_ENABLE | DM8806_P5_EN_FORCE);
+	val &= (DM8806_P5_SPEED_100M | DM8806_P5_FULL_DUPLEX | DM8806_P5_FORCE_LINK_ON);
 
-	ret = mdio_write(cfg->mdio, PHY_ADDRESS_18H, PORT5_MAC_CONTROL, val);
+	ret = mdio_write(cfg->mdio, DM8806_PHY_ADDRESS_18H, DM8806_PORT5_MAC_CONTROL, val);
 	if (ret) {
 		LOG_ERR("Failed to write PORT5_MAC_CONTROL, %i", ret);
 		return ret;
 	}
 
-	ret = mdio_read(cfg->mdio, PHY_ADDRESS_18H, IRQ_LED_CONTROL, &val);
+	ret = mdio_read(cfg->mdio, DM8806_PHY_ADDRESS_18H, DM8806_IRQ_LED_CONTROL, &val);
 	if (ret) {
 		LOG_ERR("Failed to read IRQ_LED_CONTROL, %i", ret);
 		return ret;
 	}
 
 	/* Activate LED blinking mode indicator mode 0. */
-	val &= LED_MODE_0;
-	ret = mdio_write(cfg->mdio, PHY_ADDRESS_18H, IRQ_LED_CONTROL, val);
+	val &= DM8806_LED_MODE_0;
+	ret = mdio_write(cfg->mdio, DM8806_PHY_ADDRESS_18H, DM8806_IRQ_LED_CONTROL, val);
 	if (ret) {
 		LOG_ERR("Failed to write IRQ_LED_CONTROL, %i", ret);
 		return ret;
 	}
 
+	if (!IS_ENABLED(CONFIG_PHY_DM8806_ENERGY_EFFICIENT_MODE)) {
+		/* Disable - 802.3az Energy Efficient Ethernet
+		 * The switch chip DM8806 only works reliably in this mode.
+		 */
+		for (uint32_t port_address = DM8806_SWITCH_REGISTER_OFFSET;
+		     port_address <= DM8806_SWITCH_REGISTER_OFFSET + 5; port_address++) {
+			ret = mdio_read(cfg->mdio, port_address,
+					DM8806_ENERGY_EFFICIENT_ETH_CTRL_REG_ADDR, &val);
+			if (ret) {
+				LOG_ERR("Failed to read ENERGY_EFFICIENT_ETH_CTRL_REG, %i", ret);
+				return ret;
+			}
+			val &= (~DM8806_EEE_EN);
+			ret = mdio_write(cfg->mdio, port_address,
+					 DM8806_ENERGY_EFFICIENT_ETH_CTRL_REG_ADDR, val);
+			if (ret) {
+				LOG_ERR("Failed to write ENERGY_EFFICIENT_ETH_CTRL_REG, %i", ret);
+				return ret;
+			}
+		}
+	} /* CONFIG_PHY_DM8806_ENERGY_EFFICIENT_MODE */
+
 #ifdef CONFIG_PHY_DM8806_TRIGGER
 	ret = phy_dm8806_init_interrupt(dev);
 	if (ret != 0) {
@@ -262,7 +486,7 @@ static int phy_dm8806_get_link_state(const struct device *dev, struct phy_link_s
 	}
 #endif
 	/* Read data from Switch Per-Port Register. */
-	ret = mdio_read(cfg->mdio, cfg->switch_addr, PORTX_SWITCH_STATUS, &data);
+	ret = phy_dm8806_read_reg(dev, cfg->switch_addr, DM8806_PORTX_SWITCH_STATUS, &data);
 	if (ret) {
 		LOG_ERR("Failes to read data drom DM8806 Switch Per-Port Registers area");
 		return ret;
@@ -271,18 +495,18 @@ static int phy_dm8806_get_link_state(const struct device *dev, struct phy_link_s
 	 * Status Data Register
 	 */
 	status = data;
-	status >>= SPEED_AND_DUPLEX_OFFSET;
-	switch (status & SPEED_AND_DUPLEX_MASK) {
-	case SPEED_10MBPS_HALF_DUPLEX:
+	status >>= DM8806_SPEED_AND_DUPLEX_OFFSET;
+	switch (status & DM8806_SPEED_AND_DUPLEX_MASK) {
+	case DM8806_SPEED_10MBPS_HALF_DUPLEX:
 		state->speed = LINK_HALF_10BASE_T;
 		break;
-	case SPEED_10MBPS_FULL_DUPLEX:
+	case DM8806_SPEED_10MBPS_FULL_DUPLEX:
 		state->speed = LINK_FULL_10BASE_T;
 		break;
-	case SPEED_100MBPS_HALF_DUPLEX:
+	case DM8806_SPEED_100MBPS_HALF_DUPLEX:
 		state->speed = LINK_HALF_100BASE_T;
 		break;
-	case SPEED_100MBPS_FULL_DUPLEX:
+	case DM8806_SPEED_100MBPS_FULL_DUPLEX:
 		state->speed = LINK_FULL_100BASE_T;
 		break;
 	}
@@ -290,7 +514,7 @@ static int phy_dm8806_get_link_state(const struct device *dev, struct phy_link_s
 	 * Register
 	 */
 	status = data;
-	if (status & LINK_STATUS_MASK) {
+	if (status & DM8806_LINK_STATUS_MASK) {
 		state->is_up = true;
 	} else {
 		state->is_up = false;
@@ -308,31 +532,31 @@ static int phy_dm8806_cfg_link(const struct device *dev, enum phy_link_speed adv
 	req_speed = adv_speeds;
 	switch (req_speed) {
 	case LINK_HALF_10BASE_T:
-		req_speed = MODE_10_BASET_HALF_DUPLEX;
+		req_speed = DM8806_MODE_10_BASET_HALF_DUPLEX;
 		break;
 
 	case LINK_FULL_10BASE_T:
-		req_speed = MODE_10_BASET_FULL_DUPLEX;
+		req_speed = DM8806_MODE_10_BASET_FULL_DUPLEX;
 		break;
 
 	case LINK_HALF_100BASE_T:
-		req_speed = MODE_100_BASET_HALF_DUPLEX;
+		req_speed = DM8806_MODE_100_BASET_HALF_DUPLEX;
 		break;
 
 	case LINK_FULL_100BASE_T:
-		req_speed = MODE_100_BASET_FULL_DUPLEX;
+		req_speed = DM8806_MODE_100_BASET_FULL_DUPLEX;
 		break;
 	}
 
 	/* Power down */
-	ret = mdio_read(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, &data);
+	ret = phy_dm8806_read_reg(dev, cfg->phy_addr, DM8806_PORTX_PHY_CONTROL_REGISTER, &data);
 	if (ret) {
 		LOG_ERR("Failes to read data drom DM8806");
 		return ret;
 	}
 	k_busy_wait(500);
-	data |= POWER_DOWN;
-	ret = mdio_write(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, data);
+	data |= DM8806_POWER_DOWN;
+	ret = phy_dm8806_write_reg(dev, cfg->phy_addr, DM8806_PORTX_PHY_CONTROL_REGISTER, data);
 	if (ret) {
 		LOG_ERR("Failed to write data to DM8806");
 		return ret;
@@ -340,14 +564,14 @@ static int phy_dm8806_cfg_link(const struct device *dev, enum phy_link_speed adv
 	k_busy_wait(500);
 
 	/* Turn off the auto-negotiation process. */
-	ret = mdio_read(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, &data);
+	ret = phy_dm8806_read_reg(dev, cfg->phy_addr, DM8806_PORTX_PHY_CONTROL_REGISTER, &data);
 	if (ret) {
 		LOG_ERR("Failed to write data to DM8806");
 		return ret;
 	}
 	k_busy_wait(500);
-	data &= ~(AUTO_NEGOTIATION);
-	ret = mdio_write(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, data);
+	data &= ~(DM8806_AUTO_NEGOTIATION);
+	ret = phy_dm8806_write_reg(dev, cfg->phy_addr, DM8806_PORTX_PHY_CONTROL_REGISTER, data);
 	if (ret) {
 		LOG_ERR("Failed to write data to DM8806");
 		return ret;
@@ -355,15 +579,15 @@ static int phy_dm8806_cfg_link(const struct device *dev, enum phy_link_speed adv
 	k_busy_wait(500);
 
 	/* Change the link speed. */
-	ret = mdio_read(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, &data);
+	ret = phy_dm8806_read_reg(dev, cfg->phy_addr, DM8806_PORTX_PHY_CONTROL_REGISTER, &data);
 	if (ret) {
 		LOG_ERR("Failed to read data from DM8806");
 		return ret;
 	}
 	k_busy_wait(500);
-	data &= ~(LINK_SPEED | DUPLEX_MODE);
+	data &= ~(DM8806_LINK_SPEED | DM8806_DUPLEX_MODE);
 	data |= req_speed;
-	ret = mdio_write(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, data);
+	ret = phy_dm8806_write_reg(dev, cfg->phy_addr, DM8806_PORTX_PHY_CONTROL_REGISTER, data);
 	if (ret) {
 		LOG_ERR("Failed to write data to DM8806");
 		return ret;
@@ -371,20 +595,20 @@ static int phy_dm8806_cfg_link(const struct device *dev, enum phy_link_speed adv
 	k_busy_wait(500);
 
 	/* Power up ethernet port*/
-	ret = mdio_read(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, &data);
+	ret = phy_dm8806_read_reg(dev, cfg->phy_addr, DM8806_PORTX_PHY_CONTROL_REGISTER, &data);
 	if (ret) {
 		LOG_ERR("Failes to read data drom DM8806");
 		return ret;
 	}
 	k_busy_wait(500);
-	data &= ~(POWER_DOWN);
-	ret = mdio_write(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, data);
+	data &= ~(DM8806_POWER_DOWN);
+	ret = phy_dm8806_write_reg(dev, cfg->phy_addr, DM8806_PORTX_PHY_CONTROL_REGISTER, data);
 	if (ret) {
 		LOG_ERR("Failed to write data to DM8806");
 		return ret;
 	}
 	k_busy_wait(500);
-	return -ENOTSUP;
+	return ret;
 }
 
 static int phy_dm8806_reg_read(const struct device *dev, uint16_t reg_addr, uint32_t *data)
@@ -420,14 +644,14 @@ static int phy_dm8806_link_cb_set(const struct device *dev, phy_callback_t cb, v
 	const struct phy_dm8806_config *cfg = dev->config;
 
 	res = gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_DISABLE);
-	if (res != 0) {
+	if (res < 0) {
 		LOG_WRN("Failed to disable DM8806 interrupt: %i", res);
 		return res;
 	}
 	data->link_speed_chenge_cb = cb;
 	data->cb_data = user_data;
 	gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_EDGE_TO_ACTIVE);
-	if (res != 0) {
+	if (res < 0) {
 		LOG_WRN("Failed to enable DM8806 interrupt: %i", res);
 		return res;
 	}
@@ -449,9 +673,9 @@ static DEVICE_API(ethphy, phy_dm8806_api) = {
 	static const struct phy_dm8806_config phy_dm8806_config_##n = {                            \
 		.mdio = DEVICE_DT_GET(DT_INST_BUS(n)),                                             \
 		.phy_addr = DT_INST_REG_ADDR(n),                                                   \
-		.switch_addr = DT_PROP(DT_NODELABEL(dm8806_phy##n), reg_switch),                   \
-		.gpio_int = GPIO_DT_SPEC_INST_GET(n, interrupt_gpio),                              \
-		.gpio_rst = GPIO_DT_SPEC_INST_GET(n, reset_gpio),                                  \
+		.switch_addr = DT_INST_PROP(n, reg_switch),                                        \
+		.gpio_int = GPIO_DT_SPEC_INST_GET(n, int_gpios),                                   \
+		.gpio_rst = GPIO_DT_SPEC_INST_GET(n, reset_gpios),                                 \
 	}
 
 #define DM8806_PHY_INITIALIZE(n)                                                                   \
diff --git a/drivers/ethernet/phy/phy_dm8806_priv.h b/drivers/ethernet/phy/phy_dm8806_priv.h
index 4c4a292cadf..9d8bc203edd 100644
--- a/drivers/ethernet/phy/phy_dm8806_priv.h
+++ b/drivers/ethernet/phy/phy_dm8806_priv.h
@@ -4,142 +4,178 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+/* The absolute PHY address is 10 bit length. Last 5 bits for oldest
+ * part of address - see Clause 22 of IEEE 802.3.
+ */
+#define DM8806_REGAD_WIDTH 0x5u
+
+/* Mask for checksum error. Checksum status is present on the 8-th bit of the
+ * Serial Bus Error Check Register (339h) [8]
+ */
+#define DM8806_SMI_ERR 8
+
+/* PHY read opcode as part of the MDIO frame in Clause 22 */
+#define DM8806_PHY_READ  0x2u
+/* PHY write opcode as part of the MDIO frame in Clause 22 */
+#define DM8806_PHY_WRITE 0x1u
+
 /* Port 0~4 PHY Control Register. */
-#define PORTX_PHY_CONTROL_REGISTER 0x0u
+#define DM8806_PORTX_PHY_CONTROL_REGISTER 0x0u
 /* 10 Mbit/s transfer with half duplex mask. */
-#define MODE_10_BASET_HALF_DUPLEX  0x0u
+#define DM8806_MODE_10_BASET_HALF_DUPLEX  0x0u
 /* 10 Mbit/s transfer with full duplex mask. */
-#define MODE_10_BASET_FULL_DUPLEX  0x100u
+#define DM8806_MODE_10_BASET_FULL_DUPLEX  0x100u
 /* 100 Mbit/s transfer with half duplex mask. */
-#define MODE_100_BASET_HALF_DUPLEX 0x2000u
+#define DM8806_MODE_100_BASET_HALF_DUPLEX 0x2000u
 /* 100 Mbit/s transfer with full duplex mask. */
-#define MODE_100_BASET_FULL_DUPLEX 0x2100u
+#define DM8806_MODE_100_BASET_FULL_DUPLEX 0x2100u
 /* Duplex mode ability offset. */
-#define DUPLEX_MODE                (1 << 8)
+#define DM8806_DUPLEX_MODE                (1 << 8)
 /* Power down mode offset. */
-#define POWER_DOWN                 (1 << 11)
+#define DM8806_POWER_DOWN                 (1 << 11)
 /* Auto negotiation mode offset. */
-#define AUTO_NEGOTIATION           (1 << 12)
+#define DM8806_AUTO_NEGOTIATION           (1 << 12)
 /* Link speed selection offset. */
-#define LINK_SPEED                 (1 << 13)
+#define DM8806_LINK_SPEED                 (1 << 13)
 
 /* Port 0~4 Status Data Register. */
-#define PORTX_SWITCH_STATUS       0x10u
+#define DM8806_PORTX_SWITCH_STATUS       0x10u
 /* 10 Mbit/s transfer speed with half duplex. */
-#define SPEED_10MBPS_HALF_DUPLEX  0x00u
+#define DM8806_SPEED_10MBPS_HALF_DUPLEX  0x00u
 /* 10 Mbit/s transfer speed with full duplex. */
-#define SPEED_10MBPS_FULL_DUPLEX  0x01u
+#define DM8806_SPEED_10MBPS_FULL_DUPLEX  0x01u
 /* 100 Mbit/s transfer speed with half duplex. */
-#define SPEED_100MBPS_HALF_DUPLEX 0x02u
+#define DM8806_SPEED_100MBPS_HALF_DUPLEX 0x02u
 /* 100 Mbit/s transfer speed with full duplex. */
-#define SPEED_100MBPS_FULL_DUPLEX 0x03u
+#define DM8806_SPEED_100MBPS_FULL_DUPLEX 0x03u
 /* Speed and duplex mode status offset. */
-#define SPEED_AND_DUPLEX_OFFSET   0x01u
+#define DM8806_SPEED_AND_DUPLEX_OFFSET   0x01u
 /* Speed and duplex mode staus mask. */
-#define SPEED_AND_DUPLEX_MASK     0x07u
+#define DM8806_SPEED_AND_DUPLEX_MASK     0x07u
 /* Link status mask. */
-#define LINK_STATUS_MASK          0x1u
+#define DM8806_LINK_STATUS_MASK          0x1u
 
 /* Switch Engine Registers */
 /* Address Table Control And Status Register PHY Address */
-#define ADDR_TAB_CTRL_STAT_PHY_ADDR 0x15u
+#define DM8806_ADDR_TAB_CTRL_STAT_PHY_ADDR 0x15u
 /* Address Table Control And Status Register Register SAddress */
-#define ADDR_TAB_CTRL_STAT_REG_ADDR 0x10u
+#define DM8806_ADDR_TAB_CTRL_STAT_REG_ADDR 0x10u
 
 /* Address Table Access bussy flag offset */
-#define ATB_S_OFFSET  0xf
+#define DM8806_ATB_S_OFFSET  0xf
 /* Address Table Command Result flag offset */
-#define ATB_CR_OFFSET 0xd
+#define DM8806_ATB_CR_OFFSET 0xd
 /* Address Table Command Result flag mask */
-#define ATB_CR_MASK   0x3
+#define DM8806_ATB_CR_MASK   0x3
 
 /* Unicast Address Table Index*/
-#define UNICAST_ADDR_TAB   (1 << 0 | 1 << 1)
+#define DM8806_UNICAST_ADDR_TAB   (1 << 0 | 1 << 1)
 /* Multicast Address Table Index*/
-#define MULTICAST_ADDR_TAB (1 << 0)
+#define DM8806_MULTICAST_ADDR_TAB (1 << 0)
 /* IGMP Table Index*/
-#define IGMP_ADDR_TAB      (1 << 1)
+#define DM8806_IGMP_ADDR_TAB      (1 << 1)
 
 /* Read a entry with sequence number of address table */
-#define ATB_CMD_READ   (1 << 2 | 1 << 3 | 1 << 4)
+#define DM8806_ATB_CMD_READ   (1 << 2 | 1 << 3 | 1 << 4)
 /* Write a entry with MAC address */
-#define ATB_CMD_WRITE  (1 << 2)
+#define DM8806_ATB_CMD_WRITE  (1 << 2)
 /* Delete a entry with MAC address */
-#define ATB_CMD_DELETE (1 << 3)
+#define DM8806_ATB_CMD_DELETE (1 << 3)
 /* Search a entry with MAC address */
-#define ATB_CMD_SEARCH (1 << 2 | 1 << 3)
+#define DM8806_ATB_CMD_SEARCH (1 << 2 | 1 << 3)
 /* Clear one or more than one entries with Port or FID */
-#define ATB_CMD_CLEAR  (1 << 4)
+#define DM8806_ATB_CMD_CLEAR  (1 << 4)
 
 /* Address Table Data 0 PHY Address */
-#define ADDR_TAB_DATA0_PHY_ADDR 0x15u
+#define DM8806_ADDR_TAB_DATA0_PHY_ADDR 0x15u
 /* Address Table Data 0 Register Address */
-#define ADDR_TAB_DATA0_REG_ADDR 0x11u
+#define DM8806_ADDR_TAB_DATA0_REG_ADDR 0x11u
 /* Port number or port map mask*/
-#define ATB_PORT_MASK           0x1f
+#define DM8806_ATB_PORT_MASK           0x1f
 
 /* Address Table Data 1 PHY Address */
-#define ADDR_TAB_DATA1_PHY_ADDR 0x15u
+#define DM8806_ADDR_TAB_DATA1_PHY_ADDR 0x15u
 /* Address Table Data 1 Register Address */
-#define ADDR_TAB_DATA1_REG_ADDR 0x12u
+#define DM8806_ADDR_TAB_DATA1_REG_ADDR 0x12u
 
 /* Address Table Data 2 PHY Address */
-#define ADDR_TAB_DATA2_PHY_ADDR 0x15u
+#define DM8806_ADDR_TAB_DATA2_PHY_ADDR 0x15u
 /* Address Table Data 2 Register Address */
-#define ADDR_TAB_DATA2_REG_ADDR 0x13u
+#define DM8806_ADDR_TAB_DATA2_REG_ADDR 0x13u
 
 /* Address Table Data 3 PHY Address */
-#define ADDR_TAB_DATA3_PHY_ADDR 0x15u
+#define DM8806_ADDR_TAB_DATA3_PHY_ADDR 0x15u
 /* Address Table Data 3 Register Address */
-#define ADDR_TAB_DATA3_REG_ADDR 0x14u
+#define DM8806_ADDR_TAB_DATA3_REG_ADDR 0x14u
 
 /* Address Table Data 4 PHY Address */
-#define ADDR_TAB_DATA4_PHY_ADDR 0x15u
+#define DM8806_ADDR_TAB_DATA4_PHY_ADDR 0x15u
 /* Address Table Data 4 Register Address */
-#define ADDR_TAB_DATA4_REG_ADDR 0x15u
+#define DM8806_ADDR_TAB_DATA4_REG_ADDR 0x15u
 
 /* WoL Control Register PHY Address */
-#define WOLL_CTRL_REG_PHY_ADDR 0x15u
+#define DM8806_WOLL_CTRL_REG_PHY_ADDR 0x15u
 /* WoL Control Register Register Address */
-#define WOLL_CTRL_REG_REG_ADDR 0x1bu
+#define DM8806_WOLL_CTRL_REG_REG_ADDR 0x1bu
+
+/* Serial Bus Error Check PHY Address. */
+#define DM8806_SMI_BUS_ERR_CHK_PHY_ADDRESS 0x19u
+/* Serial Bus Error Check Register Address. */
+#define DM8806_SMI_BUS_ERR_CHK_REG_ADDRESS 0x19u
+
+/* Serial Bus Control PHY Address. */
+#define DM8806_SMI_BUS_CTRL_PHY_ADDRESS 0x19u
+/* Serial Bus Control Register Address. */
+#define DM8806_SMI_BUS_CTRL_REG_ADDRESS 0x1au
+/* SMI Bus Error Check Enable. */
+#define DM8806_SMI_ECE                  BIT(0)
 
 /* PHY address 0x18h */
-#define PHY_ADDRESS_18H 0x18u
+#define DM8806_PHY_ADDRESS_18H 0x18u
 
 /* Interrupt Status Register PHY Address. */
-#define INT_STAT_PHY_ADDR 0x18u
+#define DM8806_INT_STAT_PHY_ADDR 0x18u
 /* Interrupt Status Register Register Address. */
-#define INT_STAT_REG_ADDR 0x18u
+#define DM8806_INT_STAT_REG_ADDR 0x18u
 
 /* Interrupt Mask & Control Register PHY Address. */
-#define INT_MASK_CTRL_PHY_ADDR 0x18u
+#define DM8806_INT_MASK_CTRL_PHY_ADDR 0x18u
 /* Interrupt Mask & Control Register Register Address. */
-#define INT_MASK_CTRL_REG_ADDR 0x19u
+#define DM8806_INT_MASK_CTRL_REG_ADDR 0x19u
+
+/* Switch Register offset  */
+#define DM8806_SWITCH_REGISTER_OFFSET 0x08
+
+/* Energy Efficient Ethernet Control Register Address. */
+#define DM8806_ENERGY_EFFICIENT_ETH_CTRL_REG_ADDR 0x1e
+
+/* Energy Efficient Ethernet enable bit */
+#define DM8806_EEE_EN BIT(15)
 
-#define PORT5_MAC_CONTROL     0x15u
+#define DM8806_PORT5_MAC_CONTROL     0x15u
 /* Port 5 Force Speed control bit */
-#define P5_SPEED_100M         ~BIT(0)
+#define DM8806_P5_SPEED_100M         ~BIT(0)
 /* Port 5 Force Duplex control bit */
-#define P5_FULL_DUPLEX        ~BIT(1)
+#define DM8806_P5_FULL_DUPLEX        ~BIT(1)
 /* Port 5 Force Link control bit. Only available in force mode. */
-#define P5_FORCE_LINK_ON      ~BIT(2)
+#define DM8806_P5_FORCE_LINK_ON      ~BIT(2)
 /* Port 5 Force Mode Enable control bit. Only available for
  * MII/RevMII/RMII
  */
-#define P5_EN_FORCE           BIT(3)
+#define DM8806_P5_EN_FORCE           BIT(3)
 /* Bit 4 is reserved and should not be use */
 /* Port 5 50MHz Clock Output Enable control bit. Only available when Port 5
  * be configured as RMII
  */
-#define P5_50M_CLK_OUT_ENABLE BIT(5)
+#define DM8806_P5_50M_CLK_OUT_ENABLE BIT(5)
 /* Port 5 Clock Source Selection control bit. Only available when Port 5
  * is configured as RMII
  */
-#define P5_50M_INT_CLK_SOURCE BIT(6)
+#define DM8806_P5_50M_INT_CLK_SOURCE BIT(6)
 /* Port 5 Output Pin Slew Rate. */
-#define P5_NORMAL_SLEW_RATE   ~BIT(7)
+#define DM8806_P5_NORMAL_SLEW_RATE   ~BIT(7)
 /* IRQ and LED Control Register. */
-#define IRQ_LED_CONTROL       0x17u
+#define DM8806_IRQ_LED_CONTROL       0x17u
 /* LED mode 0:
  * LNK_LED:
  * 100M link fail                       - LED off
@@ -153,4 +189,4 @@
  * 10M link ok and no TX/RX activity    - LED on
  * 10M link ok and TX/RX activity       - LED blinking
  */
-#define LED_MODE_0            ~(BIT(0) | BIT(1))
+#define DM8806_LED_MODE_0            ~(BIT(0) | BIT(1))
diff --git a/drivers/ethernet/phy/phy_microchip_ksz8081.c b/drivers/ethernet/phy/phy_microchip_ksz8081.c
index 5f80b659161..d580ffd42a0 100644
--- a/drivers/ethernet/phy/phy_microchip_ksz8081.c
+++ b/drivers/ethernet/phy/phy_microchip_ksz8081.c
@@ -161,13 +161,11 @@ static int phy_mc_ksz8081_get_link(const struct device *dev,
 	ret = phy_mc_ksz8081_read(dev, MII_BMSR, &bmsr);
 	if (ret) {
 		LOG_ERR("Error reading phy (%d) basic status register", config->addr);
-		k_mutex_unlock(&data->mutex);
-		return ret;
+		goto done;
 	}
 	state->is_up = bmsr & MII_BMSR_LINK_STATUS;
 
 	if (!state->is_up) {
-		k_mutex_unlock(&data->mutex);
 		goto result;
 	}
 
@@ -175,21 +173,16 @@ static int phy_mc_ksz8081_get_link(const struct device *dev,
 	ret = phy_mc_ksz8081_read(dev, MII_ANAR, &anar);
 	if (ret) {
 		LOG_ERR("Error reading phy (%d) advertising register", config->addr);
-		k_mutex_unlock(&data->mutex);
-		return ret;
+		goto done;
 	}
 
 	/* Read link partner capability */
 	ret = phy_mc_ksz8081_read(dev, MII_ANLPAR, &anlpar);
 	if (ret) {
 		LOG_ERR("Error reading phy (%d) link partner register", config->addr);
-		k_mutex_unlock(&data->mutex);
-		return ret;
+		goto done;
 	}
 
-	/* Unlock mutex */
-	k_mutex_unlock(&data->mutex);
-
 	uint32_t mutual_capabilities = anar & anlpar;
 
 	if (mutual_capabilities & MII_ADVERTISE_100_FULL) {
@@ -214,6 +207,9 @@ static int phy_mc_ksz8081_get_link(const struct device *dev,
 		}
 	}
 
+done:
+	k_mutex_unlock(&data->mutex);
+
 	return ret;
 }
 
@@ -267,30 +263,19 @@ static int phy_mc_ksz8081_static_cfg(const struct device *dev)
 	return 0;
 }
 
-static int phy_mc_ksz8081_reset(const struct device *dev)
-{
 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios)
-	const struct mc_ksz8081_config *config = dev->config;
-#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios) */
-	struct mc_ksz8081_data *data = dev->data;
+static int phy_ksz8081_reset_gpio(const struct mc_ksz8081_config *config)
+{
 	int ret;
 
-	/* Lock mutex */
-	ret = k_mutex_lock(&data->mutex, K_FOREVER);
-	if (ret) {
-		LOG_ERR("PHY mutex lock error");
-		return ret;
-	}
-
-#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios)
 	if (!config->reset_gpio.port) {
-		goto skip_reset_gpio;
+		return -ENODEV;
 	}
 
 	/* Start reset */
 	ret = gpio_pin_set_dt(&config->reset_gpio, 0);
 	if (ret) {
-		goto done;
+		return ret;
 	}
 
 	/* Wait for at least 500 us as specified by datasheet */
@@ -302,9 +287,35 @@ static int phy_mc_ksz8081_reset(const struct device *dev)
 	/* After deasserting reset, must wait at least 100 us to use programming interface */
 	k_busy_wait(200);
 
-	goto done;
-skip_reset_gpio:
+	return ret;
+}
+#else
+static int phy_ksz8081_reset_gpio(const struct mc_ksz8081_config *config)
+{
+	ARG_UNUSED(config);
+
+	return -ENODEV;
+}
 #endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios) */
+
+static int phy_mc_ksz8081_reset(const struct device *dev)
+{
+	const struct mc_ksz8081_config *config = dev->config;
+	struct mc_ksz8081_data *data = dev->data;
+	int ret;
+
+	/* Lock mutex */
+	ret = k_mutex_lock(&data->mutex, K_FOREVER);
+	if (ret) {
+		LOG_ERR("PHY mutex lock error");
+		return ret;
+	}
+
+	ret = phy_ksz8081_reset_gpio(config);
+	if (ret != -ENODEV) { /* On -ENODEV, attempt command-based reset */
+		goto done;
+	}
+
 	ret = phy_mc_ksz8081_write(dev, MII_BMCR, MII_BMCR_RESET);
 	if (ret) {
 		goto done;
diff --git a/drivers/ethernet/phy/phy_microchip_t1s.c b/drivers/ethernet/phy/phy_microchip_t1s.c
new file mode 100644
index 00000000000..98ab971545f
--- /dev/null
+++ b/drivers/ethernet/phy/phy_microchip_t1s.c
@@ -0,0 +1,568 @@
+/*
+ * Copyright (c) 2024 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT microchip_t1s_phy
+
+#include <zephyr/kernel.h>
+#include <zephyr/net/phy.h>
+#include <zephyr/net/mii.h>
+#include <zephyr/net/mdio.h>
+#include <zephyr/drivers/mdio.h>
+
+#define LOG_MODULE_NAME phy_mc_t1s
+#define LOG_LEVEL       CONFIG_PHY_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(LOG_MODULE_NAME);
+
+/* Support: Microchip Phys:
+ * lan8650/1 Rev.B0/B1 Internal PHYs
+ * lan8670/1/2 Rev.C1/C2 PHYs
+ */
+/* Both Rev.B0 and B1 clause 22 PHYID's are same due to B1 chip limitation */
+#define PHY_ID_LAN865X_REVB  0x0007C1B3
+#define PHY_ID_LAN867X_REVC1 0x0007C164
+#define PHY_ID_LAN867X_REVC2 0x0007C165
+
+/* Configuration param registers */
+#define LAN865X_REG_CFGPARAM_ADDR    0x00D8
+#define LAN865X_REG_CFGPARAM_DATA    0x00D9
+#define LAN865X_REG_CFGPARAM_CTRL    0x00DA
+#define LAN865X_REG_STS2             0x0019
+#define LAN865X_CFGPARAM_READ_ENABLE BIT(1)
+
+/* Collision detection enable/disable registers */
+#define LAN86XX_DISABLE_COL_DET   0x0000
+#define LAN86XX_ENABLE_COL_DET    0x8000
+#define LAN86XX_COL_DET_MASK      0x8000
+#define LAN86XX_REG_COL_DET_CTRL0 0x0087
+
+/* Structure holding configuration register address and value */
+typedef struct {
+	uint32_t address;
+	uint16_t value;
+} lan865x_config;
+
+/* LAN865x Rev.B0/B1 configuration parameters from AN1760
+ * As per the Configuration Application Note AN1760 published in the below link,
+ * https://www.microchip.com/en-us/application-notes/an1760
+ * Revision F (DS60001760G - June 2024)
+ * Addresses 0x0084, 0x008A, 0x00AD, 0x00AE and 0x00AF will be updated with cfgparam1, cfgparam2,
+ * cfgparam3, cfgparam4 and cfgparam5 respectively.
+ *
+ * LAN867x Rev.C1/C2 configuration settings described in AN1699 are equal to
+ * the first 11 configuration settings and all the sqi fixup settings from
+ * LAN865x Rev.B0/B1. So the same fixup registers and values from LAN865x
+ * Rev.B0/B1 are used for LAN867x Rev.C1/C2 to avoid duplication.
+ * Refer the below link for the AN1699,
+ * https://www.microchip.com/en-us/application-notes/an1699
+ * Revision E (DS60001699F - June 2024)
+ */
+static lan865x_config lan865x_revb_config[] = {
+	{.address = 0x00D0, .value = 0x3F31}, {.address = 0x00E0, .value = 0xC000},
+	{.address = 0x0084, .value = 0x0000}, {.address = 0x008A, .value = 0x0000},
+	{.address = 0x00E9, .value = 0x9E50}, {.address = 0x00F5, .value = 0x1CF8},
+	{.address = 0x00F4, .value = 0xC020}, {.address = 0x00F8, .value = 0xB900},
+	{.address = 0x00F9, .value = 0x4E53}, {.address = 0x0081, .value = 0x0080},
+	{.address = 0x0091, .value = 0x9660}, {.address = 0x0043, .value = 0x00FF},
+	{.address = 0x0044, .value = 0xFFFF}, {.address = 0x0045, .value = 0x0000},
+	{.address = 0x0053, .value = 0x00FF}, {.address = 0x0054, .value = 0xFFFF},
+	{.address = 0x0055, .value = 0x0000}, {.address = 0x0040, .value = 0x0002},
+	{.address = 0x0050, .value = 0x0002}, {.address = 0x00AD, .value = 0x0000},
+	{.address = 0x00AE, .value = 0x0000}, {.address = 0x00AF, .value = 0x0000},
+	{.address = 0x00B0, .value = 0x0103}, {.address = 0x00B1, .value = 0x0910},
+	{.address = 0x00B2, .value = 0x1D26}, {.address = 0x00B3, .value = 0x002A},
+	{.address = 0x00B4, .value = 0x0103}, {.address = 0x00B5, .value = 0x070D},
+	{.address = 0x00B6, .value = 0x1720}, {.address = 0x00B7, .value = 0x0027},
+	{.address = 0x00B8, .value = 0x0509}, {.address = 0x00B9, .value = 0x0E13},
+	{.address = 0x00BA, .value = 0x1C25}, {.address = 0x00BB, .value = 0x002B},
+};
+
+struct mc_t1s_plca_config {
+	bool enable;
+	uint8_t node_id;
+	uint8_t node_count;
+	uint8_t burst_count;
+	uint8_t burst_timer;
+	uint8_t to_timer;
+};
+
+struct mc_t1s_config {
+	uint8_t phy_addr;
+	const struct device *mdio;
+	struct mc_t1s_plca_config *plca;
+};
+
+struct mc_t1s_data {
+	const struct device *dev;
+	struct phy_link_state state;
+	phy_callback_t cb;
+	void *cb_data;
+	struct k_work_delayable phy_monitor_work;
+};
+
+static int phy_mc_t1s_read(const struct device *dev, uint16_t reg, uint32_t *data)
+{
+	const struct mc_t1s_config *cfg = dev->config;
+
+	/* Make sure excessive bits 16-31 are reset */
+	*data = 0U;
+
+	return mdio_read(cfg->mdio, cfg->phy_addr, reg, (uint16_t *)data);
+}
+
+static int phy_mc_t1s_write(const struct device *dev, uint16_t reg, uint32_t data)
+{
+	const struct mc_t1s_config *cfg = dev->config;
+
+	return mdio_write(cfg->mdio, cfg->phy_addr, reg, (uint16_t)data);
+}
+
+static int mdio_setup_c45_indirect_access(const struct device *dev, uint16_t devad, uint16_t reg)
+{
+	const struct mc_t1s_config *cfg = dev->config;
+	int ret;
+
+	ret = mdio_write(cfg->mdio, cfg->phy_addr, MII_MMD_ACR, devad);
+	if (ret) {
+		return ret;
+	}
+
+	ret = mdio_write(cfg->mdio, cfg->phy_addr, MII_MMD_AADR, reg);
+	if (ret < 0) {
+		return ret;
+	}
+
+	return mdio_write(cfg->mdio, cfg->phy_addr, MII_MMD_ACR, devad | BIT(14));
+}
+
+static int phy_mc_t1s_c45_read(const struct device *dev, uint8_t devad, uint16_t reg, uint16_t *val)
+{
+	const struct mc_t1s_config *cfg = dev->config;
+	int ret;
+
+	ret = mdio_read_c45(cfg->mdio, cfg->phy_addr, devad, reg, val);
+	/* @retval -ENOSYS if read using Clause 45 direct access is not supported */
+	if (ret == -ENOSYS) {
+		/* Read C45 registers using C22 indirect access registers */
+		ret = mdio_setup_c45_indirect_access(dev, devad, reg);
+		if (ret) {
+			return ret;
+		}
+
+		return mdio_read(cfg->mdio, cfg->phy_addr, MII_MMD_AADR, val);
+	}
+
+	return ret;
+}
+
+static int phy_mc_t1s_c45_write(const struct device *dev, uint8_t devad, uint16_t reg, uint16_t val)
+{
+	const struct mc_t1s_config *cfg = dev->config;
+	int ret;
+
+	ret = mdio_write_c45(cfg->mdio, cfg->phy_addr, devad, reg, val);
+	/* @retval -ENOSYS if write using Clause 45 direct access is not supported */
+	if (ret == -ENOSYS) {
+		/* Write C45 registers using C22 indirect access registers */
+		ret = mdio_setup_c45_indirect_access(dev, devad, reg);
+		if (ret) {
+			return ret;
+		}
+
+		return mdio_write(cfg->mdio, cfg->phy_addr, MII_MMD_AADR, val);
+	}
+
+	return ret;
+}
+
+static int phy_mc_t1s_get_link(const struct device *dev, struct phy_link_state *state)
+{
+	const struct mc_t1s_config *cfg = dev->config;
+	struct mc_t1s_data *data = dev->data;
+	struct phy_link_state old_state = data->state;
+	uint32_t value = 0;
+	int ret;
+
+	ret = phy_mc_t1s_read(dev, MII_BMSR, &value);
+	if (ret) {
+		LOG_ERR("Failed MII_BMSR register read: %d\n", ret);
+		return ret;
+	}
+
+	state->is_up = value & MII_BMSR_LINK_STATUS;
+	state->speed = LINK_HALF_10BASE_T;
+
+	if (memcmp(&old_state, state, sizeof(struct phy_link_state)) != 0) {
+		if (state->is_up) {
+			LOG_INF("PHY (%d) Link speed 10 Mbps, half duplex\n", cfg->phy_addr);
+		}
+	}
+
+	return 0;
+}
+
+static int phy_mc_t1s_link_cb_set(const struct device *dev, phy_callback_t cb, void *user_data)
+{
+	struct mc_t1s_data *data = dev->data;
+
+	data->cb = cb;
+	data->cb_data = user_data;
+
+	if (data->cb) {
+		data->cb(dev, &data->state, data->cb_data);
+	}
+
+	return 0;
+}
+
+static void phy_monitor_work_handler(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct mc_t1s_data *const data = CONTAINER_OF(dwork, struct mc_t1s_data, phy_monitor_work);
+	const struct device *dev = data->dev;
+
+	if (!data->cb) {
+		return;
+	}
+
+	phy_mc_t1s_get_link(dev, &data->state);
+
+	data->cb(dev, &data->state, data->cb_data);
+
+	/* Submit delayed work */
+	k_work_reschedule(&data->phy_monitor_work, K_MSEC(CONFIG_PHY_MONITOR_PERIOD));
+}
+
+/* Pulled from AN1760 describing 'indirect read'
+ *
+ * write_register(0x4, 0x00D8, addr)
+ * write_register(0x4, 0x00DA, 0x2)
+ * return (int8)(read_register(0x4, 0x00D9))
+ *
+ * 0x4 refers to memory map selector 4, which maps to MDIO_MMD_VENDOR_SPECIFIC2
+ */
+static int lan865x_indirect_read(const struct device *dev, uint16_t addr, uint16_t *value)
+{
+	int ret;
+
+	ret = phy_mc_t1s_c45_write(dev, MDIO_MMD_VENDOR_SPECIFIC2, LAN865X_REG_CFGPARAM_ADDR, addr);
+	if (ret) {
+		return ret;
+	}
+
+	ret = phy_mc_t1s_c45_write(dev, MDIO_MMD_VENDOR_SPECIFIC2, LAN865X_REG_CFGPARAM_CTRL,
+				   LAN865X_CFGPARAM_READ_ENABLE);
+	if (ret) {
+		return ret;
+	}
+
+	return phy_mc_t1s_c45_read(dev, MDIO_MMD_VENDOR_SPECIFIC2, LAN865X_REG_CFGPARAM_DATA,
+				   value);
+}
+
+static int lan865x_calculate_offset(const struct device *dev, uint16_t address, int8_t *offset)
+{
+	uint16_t value;
+	int ret;
+
+	ret = lan865x_indirect_read(dev, address, &value);
+	if (ret) {
+		return ret;
+	}
+
+	/* 5-bit signed value, sign extend */
+	value &= GENMASK(4, 0);
+	if (value & BIT(4)) {
+		*offset = (int8_t)((uint8_t)value - 0x20);
+	} else {
+		*offset = (int8_t)value;
+	}
+
+	return 0;
+}
+
+static void lan865x_update_cfgparam(uint32_t address, uint16_t cfgparam)
+{
+	for (uint8_t i = 0; i < ARRAY_SIZE(lan865x_revb_config); i++) {
+		if (lan865x_revb_config[i].address == address) {
+			lan865x_revb_config[i].value = cfgparam;
+		}
+	}
+}
+
+static int lan865x_calculate_update_cfgparams(const struct device *dev)
+{
+	uint16_t cfgparam;
+	int8_t offset1;
+	int8_t offset2;
+	int ret;
+
+	/* Calculate offset1 */
+	ret = lan865x_calculate_offset(dev, 0x04, &offset1);
+	if (ret) {
+		return ret;
+	}
+
+	/* Calculate offset2 */
+	ret = lan865x_calculate_offset(dev, 0x08, &offset2);
+	if (ret) {
+		return ret;
+	}
+
+	/* Calculate & update cfgparam1 for configuration */
+	cfgparam = (uint16_t)(((9 + offset1) & 0x3F) << 10) |
+		   (uint16_t)(((14 + offset1) & 0x3F) << 4) | 0x03;
+	lan865x_update_cfgparam(0x0084, cfgparam);
+
+	/* Calculate & update cfgparam2 for configuration */
+	cfgparam = (uint16_t)(((40 + offset2) & 0x3F) << 10);
+	lan865x_update_cfgparam(0x008A, cfgparam);
+
+	/* Calculate & update cfgparam3 for configuration */
+	cfgparam = (uint16_t)(((5 + offset1) & 0x3F) << 8) | (uint16_t)((9 + offset1) & 0x3F);
+	lan865x_update_cfgparam(0x00AD, cfgparam);
+
+	/* Calculate & update cfgparam4 for configuration */
+	cfgparam = (uint16_t)(((9 + offset1) & 0x3F) << 8) | (uint16_t)((14 + offset1) & 0x3F);
+	lan865x_update_cfgparam(0x00AE, cfgparam);
+
+	/* Calculate & update cfgparam5 for configuration */
+	cfgparam = (uint16_t)(((17 + offset1) & 0x3F) << 8) | (uint16_t)((22 + offset1) & 0x3F);
+	lan865x_update_cfgparam(0x00AF, cfgparam);
+
+	return 0;
+}
+
+static int phy_mc_lan865x_revb_config_init(const struct device *dev)
+{
+	int ret;
+
+	ret = lan865x_calculate_update_cfgparams(dev);
+	if (ret) {
+		return ret;
+	}
+
+	/* Configure lan865x initial settings */
+	for (int i = 0; i < ARRAY_SIZE(lan865x_revb_config); i++) {
+		ret = phy_mc_t1s_c45_write(dev, MDIO_MMD_VENDOR_SPECIFIC2,
+					   lan865x_revb_config[i].address,
+					   lan865x_revb_config[i].value);
+		if (ret) {
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+/* LAN867x Rev.C1/C2 configuration settings are equal to the first 11 configuration settings and all
+ * the sqi fixup settings from LAN865x Rev.B0/B1. So the same fixup registers and values from
+ * LAN865x Rev.B0/B1 are used for LAN867x Rev.C1/C2 to avoid duplication.
+ * Refer the below links for the comparison.
+ * https://www.microchip.com/en-us/application-notes/an1760
+ * Revision F (DS60001760G - June 2024)
+ * https://www.microchip.com/en-us/application-notes/an1699
+ * Revision E (DS60001699F - June 2024)
+ */
+static int phy_mc_lan867x_revc_config_init(const struct device *dev)
+{
+	int ret;
+
+	ret = lan865x_calculate_update_cfgparams(dev);
+	if (ret) {
+		return ret;
+	}
+
+	for (int i = 0; i < ARRAY_SIZE(lan865x_revb_config); i++) {
+		ret = phy_mc_t1s_c45_write(dev, MDIO_MMD_VENDOR_SPECIFIC2,
+					   lan865x_revb_config[i].address,
+					   lan865x_revb_config[i].value);
+		if (ret) {
+			return ret;
+		}
+
+		/* LAN867x Rev.C1/C2 configuration settings are equal to the first 11 configuration
+		 * settings and all the sqi fixup settings from LAN865x Rev.B0/B1. So the 8
+		 * inbetween configuration settings are skipped.
+		 */
+		if (i == 10) {
+			i += 8;
+		}
+	}
+
+	return 0;
+}
+
+static int lan86xx_config_collision_detection(const struct device *dev, bool plca_enable)
+{
+	uint16_t val;
+	uint16_t new;
+	int ret;
+
+	ret = phy_mc_t1s_c45_read(dev, MDIO_MMD_VENDOR_SPECIFIC2, LAN86XX_REG_COL_DET_CTRL0, &val);
+	if (ret) {
+		return ret;
+	}
+
+	if (plca_enable) {
+		new = (val & ~LAN86XX_COL_DET_MASK) | LAN86XX_DISABLE_COL_DET;
+	} else {
+		new = (val & ~LAN86XX_COL_DET_MASK) | LAN86XX_ENABLE_COL_DET;
+	}
+
+	if (new == val) {
+		return 0;
+	}
+
+	return phy_mc_t1s_c45_write(dev, MDIO_MMD_VENDOR_SPECIFIC2, LAN86XX_REG_COL_DET_CTRL0, new);
+}
+
+static int phy_mc_t1s_cfg_link(const struct device *dev, enum phy_link_speed speeds)
+{
+	ARG_UNUSED(dev);
+
+	if (speeds & LINK_HALF_10BASE_T) {
+		return 0;
+	}
+
+	return -ENOTSUP;
+}
+
+static int phy_mc_t1s_id(const struct device *dev, uint32_t *phy_id)
+{
+	uint32_t value;
+	int ret;
+
+	ret = phy_mc_t1s_read(dev, MII_PHYID1R, &value);
+	if (ret) {
+		LOG_ERR("Failed MII_PHYID1R register read: %d\n", ret);
+		return ret;
+	}
+
+	*phy_id = value << 16;
+
+	ret = phy_mc_t1s_read(dev, MII_PHYID2R, &value);
+	if (ret) {
+		LOG_ERR("Failed MII_PHYID2R register read: %d\n", ret);
+		return ret;
+	}
+
+	*phy_id |= value;
+
+	return 0;
+}
+
+static int phy_mc_t1s_set_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg)
+{
+	int ret;
+
+	ret = genphy_set_plca_cfg(dev, plca_cfg);
+	if (ret) {
+		return ret;
+	}
+
+	return lan86xx_config_collision_detection(dev, plca_cfg->enable);
+}
+
+static int phy_mc_t1s_set_dt_plca(const struct device *dev)
+{
+	const struct mc_t1s_config *cfg = dev->config;
+	struct phy_plca_cfg plca_cfg;
+
+	if (!cfg->plca->enable) {
+		return 0;
+	}
+
+	plca_cfg.enable = cfg->plca->enable;
+	plca_cfg.node_id = cfg->plca->node_id;
+	plca_cfg.node_count = cfg->plca->node_count;
+	plca_cfg.burst_count = cfg->plca->burst_count;
+	plca_cfg.burst_timer = cfg->plca->burst_timer;
+	plca_cfg.to_timer = cfg->plca->to_timer;
+
+	return phy_mc_t1s_set_plca_cfg(dev, &plca_cfg);
+}
+
+static int phy_mc_t1s_init(const struct device *dev)
+{
+	struct mc_t1s_data *data = dev->data;
+	uint32_t phy_id;
+	int ret;
+
+	data->dev = dev;
+
+	ret = phy_mc_t1s_id(dev, &phy_id);
+	if (ret) {
+		return ret;
+	}
+
+	switch (phy_id) {
+	case PHY_ID_LAN867X_REVC1:
+	case PHY_ID_LAN867X_REVC2:
+		ret = phy_mc_lan867x_revc_config_init(dev);
+		if (ret) {
+			LOG_ERR("PHY initial configuration error: %d\n", ret);
+			return ret;
+		}
+		break;
+	case PHY_ID_LAN865X_REVB:
+		ret = phy_mc_lan865x_revb_config_init(dev);
+		if (ret) {
+			LOG_ERR("PHY initial configuration error: %d\n", ret);
+			return ret;
+		}
+		break;
+	default:
+		LOG_ERR("Unsupported PHY ID: %x\n", phy_id);
+		return -ENODEV;
+	}
+
+	ret = phy_mc_t1s_set_dt_plca(dev);
+	if (ret) {
+		return ret;
+	}
+
+	k_work_init_delayable(&data->phy_monitor_work, phy_monitor_work_handler);
+	phy_monitor_work_handler(&data->phy_monitor_work.work);
+
+	return 0;
+}
+
+static DEVICE_API(ethphy, mc_t1s_phy_api) = {
+	.get_link = phy_mc_t1s_get_link,
+	.cfg_link = phy_mc_t1s_cfg_link,
+	.link_cb_set = phy_mc_t1s_link_cb_set,
+	.set_plca_cfg = phy_mc_t1s_set_plca_cfg,
+	.get_plca_cfg = genphy_get_plca_cfg,
+	.get_plca_sts = genphy_get_plca_sts,
+	.read = phy_mc_t1s_read,
+	.write = phy_mc_t1s_write,
+	.read_c45 = phy_mc_t1s_c45_read,
+	.write_c45 = phy_mc_t1s_c45_write,
+};
+
+#define MICROCHIP_T1S_PHY_INIT(n)                                                                  \
+	static struct mc_t1s_plca_config mc_t1s_plca_##n##_config = {                              \
+		.enable = DT_INST_PROP(n, plca_enable),                                            \
+		.node_id = DT_INST_PROP(n, plca_node_id),                                          \
+		.node_count = DT_INST_PROP(n, plca_node_count),                                    \
+		.burst_count = DT_INST_PROP(n, plca_burst_count),                                  \
+		.burst_timer = DT_INST_PROP(n, plca_burst_timer),                                  \
+		.to_timer = DT_INST_PROP(n, plca_to_timer),                                        \
+	};                                                                                         \
+                                                                                                   \
+	static const struct mc_t1s_config mc_t1s_##n##_config = {                                  \
+		.phy_addr = DT_INST_REG_ADDR(n),                                                   \
+		.mdio = DEVICE_DT_GET(DT_INST_PARENT(n)),                                          \
+		.plca = &mc_t1s_plca_##n##_config,                                                 \
+	};                                                                                         \
+                                                                                                   \
+	static struct mc_t1s_data mc_t1s_##n##_data;                                               \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, &phy_mc_t1s_init, NULL, &mc_t1s_##n##_data, &mc_t1s_##n##_config, \
+			      POST_KERNEL, CONFIG_PHY_MICROCHIP_T1S_INIT_PRIORITY, &mc_t1s_phy_api);
+
+DT_INST_FOREACH_STATUS_OKAY(MICROCHIP_T1S_PHY_INIT);
diff --git a/drivers/ethernet/phy/phy_microchip_vsc8541.c b/drivers/ethernet/phy/phy_microchip_vsc8541.c
new file mode 100644
index 00000000000..9a0c3267f6b
--- /dev/null
+++ b/drivers/ethernet/phy/phy_microchip_vsc8541.c
@@ -0,0 +1,576 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright (c) 2024 sensry.io
+ */
+
+#define DT_DRV_COMPAT microchip_vsc8541
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(microchip_vsc8541, CONFIG_PHY_LOG_LEVEL);
+
+#include <zephyr/kernel.h>
+#include <zephyr/net/phy.h>
+#include <zephyr/net/mii.h>
+#include <zephyr/drivers/mdio.h>
+#include <string.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/drivers/gpio.h>
+
+/* phy page selectors */
+#define PHY_PAGE_0 0x00 /* main registers space active */
+#define PHY_PAGE_1 0x01 /* reg 16 - 30 will be redirected to ext. register space 1 */
+#define PHY_PAGE_2 0x02 /* reg 16 - 30 will be redirected to ext. register space 2 */
+#define PHY_PAGE_3 0x03 /* reg 0 - 30 will be redirected to gpio register space */
+
+/* virtual register, treat higher byte as page selector and lower byte is register */
+#define PHY_REG(page, reg) ((page << 8) | (reg << 0))
+
+/* Generic Register */
+#define PHY_REG_PAGE0_BMCR            PHY_REG(PHY_PAGE_0, 0x00)
+#define PHY_REG_PAGE0_BMSR            PHY_REG(PHY_PAGE_0, 0x01)
+#define PHY_REG_PAGE0_ID1             PHY_REG(PHY_PAGE_0, 0x02)
+#define PHY_REG_PAGE0_ID2             PHY_REG(PHY_PAGE_0, 0x03)
+#define PHY_REG_PAGE0_ADV             PHY_REG(PHY_PAGE_0, 0x04)
+#define PHY_REG_LPA                   0x05
+#define PHY_REG_EXP                   0x06
+#define PHY_REG_PAGE0_CTRL1000        PHY_REG(PHY_PAGE_0, 0x09)
+#define PHY_REG_PAGE0_STAT1000        PHY_REG(0, 0x0A)
+#define PHY_REG_MMD_CTRL              0x0D
+#define PHY_REG_MMD_DATA              0x0E
+#define PHY_REG_STAT1000_EXT1         0x0F
+#define PHY_REG_PAGE0_STAT100         PHY_REG(PHY_PAGE_0, 0x10)
+#define PHY_REG_PAGE0_STAT1000_EXT2   PHY_REG(PHY_PAGE_0, 0x11)
+#define PHY_REG_AUX_CTRL              0x12
+#define PHY_REG_PAGE0_ERROR_COUNTER_1 PHY_REG(0, 0x13)
+#define PHY_REG_PAGE0_ERROR_COUNTER_2 PHY_REG(0, 0x14)
+#define PHY_REG_PAGE0_EXT_CTRL_STAT   PHY_REG(PHY_PAGE_0, 0x16)
+#define PHY_REG_PAGE0_EXT_CONTROL_1   PHY_REG(PHY_PAGE_0, 0x17)
+#define PHY_REG_LED_MODE              0x1d
+
+#define PHY_REG_PAGE_SELECTOR 0x1F
+
+/* Extended Register */
+#define PHY_REG_PAGE1_EXT_MODE_CTRL  PHY_REG(PHY_PAGE_1, 0x13)
+#define PHY_REG_PAGE2_RGMII_CONTROL  PHY_REG(PHY_PAGE_2, 0x14)
+#define PHY_REG_PAGE2_MAC_IF_CONTROL PHY_REG(PHY_PAGE_2, 0x1b)
+
+/* selected bits in registers */
+#define BMCR_RESET     (1 << 15)
+#define BMCR_LOOPBACK  (1 << 14)
+#define BMCR_ANENABLE  (1 << 12)
+#define BMCR_ANRESTART (1 << 9)
+#define BMCR_FULLDPLX  (1 << 8)
+#define BMCR_SPEED10   ((0 << 13) | (0 << 6))
+#define BMCR_SPEED100  ((1 << 13) | (0 << 6))
+#define BMCR_SPEED1000 ((0 << 13) | (1 << 6))
+
+#define BMCR_SPEEDMASK ((1 << 13) | (1 << 6))
+
+#define BMSR_LSTATUS (1 << 2)
+
+enum vsc8541_interface {
+	VSC8541_MII,
+	VSC8541_RMII,
+	VSC8541_GMII,
+	VSC8541_RGMII,
+};
+
+/* Thread stack size */
+#define STACK_SIZE 512
+
+/* Thread priority */
+#define THREAD_PRIORITY 7
+
+struct mc_vsc8541_config {
+	uint8_t addr;
+	const struct device *mdio_dev;
+	enum vsc8541_interface microchip_interface_type;
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios)
+	const struct gpio_dt_spec reset_gpio;
+#endif
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
+	const struct gpio_dt_spec interrupt_gpio;
+#endif
+};
+
+struct mc_vsc8541_data {
+	const struct device *dev;
+
+	struct phy_link_state state;
+	int active_page;
+
+	struct k_mutex mutex;
+
+	phy_callback_t cb;
+	void *cb_data;
+
+	struct k_thread link_monitor_thread;
+	uint8_t link_monitor_thread_stack[STACK_SIZE];
+};
+
+static int phy_mc_vsc8541_read(const struct device *dev, uint16_t reg_addr, uint32_t *data);
+static int phy_mc_vsc8541_write(const struct device *dev, uint16_t reg_addr, uint32_t data);
+static void phy_mc_vsc8541_link_monitor(void *arg1, void *arg2, void *arg3);
+
+#if CONFIG_PHY_VERIFY_DEVICE_IDENTIFICATION
+/**
+ * @brief Reads the phy manufacture id and compares to designed, known model version
+ */
+static int phy_mc_vsc8541_verify_phy_id(const struct device *dev)
+{
+	uint16_t phy_id_1;
+	uint16_t phy_id_2;
+
+	if (0 != phy_mc_vsc8541_read(dev, PHY_REG_PAGE0_ID1, (uint32_t *)&phy_id_1)) {
+		return -EINVAL;
+	}
+
+	if (0 != phy_mc_vsc8541_read(dev, PHY_REG_PAGE0_ID2, (uint32_t *)&phy_id_2)) {
+		return -EINVAL;
+	}
+
+	if (phy_id_1 == 0x0007) {
+		if (phy_id_2 == 0x0771) {
+			LOG_INF("model vsc8541-01 rev b");
+			return 0;
+		}
+		if (phy_id_2 == 0x0772) {
+			LOG_INF("model vsc8541-02/-05 rev c");
+			return 0;
+		}
+	}
+
+	LOG_INF("phy id is %#.4x - %#.4x", phy_id_1, phy_id_2);
+	return -EINVAL;
+}
+#endif
+
+/**
+ * @brief Low level reset procedure that toggles the reset gpio
+ */
+static int phy_mc_vsc8541_reset(const struct device *dev)
+{
+
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios)
+	const struct mc_vsc8541_config *cfg = dev->config;
+
+	if (!cfg->reset_gpio.port) {
+		LOG_WRN("missing reset port definition");
+		return -EINVAL;
+	}
+
+	/* configure the reset pin */
+	int ret = gpio_pin_configure_dt(&cfg->reset_gpio, GPIO_OUTPUT_ACTIVE);
+
+	if (ret) {
+		return ret;
+	}
+
+	for (uint32_t i = 0; i < 2; i++) {
+		/* Start reset */
+		ret = gpio_pin_set_dt(&cfg->reset_gpio, 0);
+		if (ret) {
+			LOG_WRN("failed to set reset gpio");
+			return -EINVAL;
+		}
+
+		/* Wait as specified by datasheet */
+		k_sleep(K_MSEC(200));
+
+		/* Reset over */
+		gpio_pin_set_dt(&cfg->reset_gpio, 1);
+
+		/* After de-asserting reset, must wait before using the config interface */
+		k_sleep(K_MSEC(200));
+	}
+#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios) */
+
+	/* According to IEEE 802.3, Section 2, Subsection 22.2.4.1.1,
+	 * a PHY reset may take up to 0.5 s.
+	 */
+	k_sleep(K_MSEC(500));
+
+#if CONFIG_PHY_VERIFY_DEVICE_IDENTIFICATION
+	/* confirm phy organizationally unique identifier, if enabled */
+	if (0 != phy_mc_vsc8541_verify_phy_id(dev)) {
+		LOG_ERR("failed to verify phy id");
+		return -EINVAL;
+	}
+#endif
+
+	/* set RGMII mode (must be executed BEFORE software reset -- see datasheet) */
+	if (cfg->microchip_interface_type == VSC8541_RGMII) {
+		ret = phy_mc_vsc8541_write(dev, PHY_REG_PAGE0_EXT_CONTROL_1,
+					   (0x0 << 13) | (0x2 << 11));
+		if (ret) {
+			return ret;
+		}
+	}
+
+	/* software reset */
+	ret = phy_mc_vsc8541_write(dev, PHY_REG_PAGE0_BMCR, MII_BMCR_RESET);
+	if (ret) {
+		return ret;
+	}
+
+	/* wait for phy finished software reset */
+	uint32_t reg = 0;
+
+	do {
+		phy_mc_vsc8541_read(dev, PHY_REG_PAGE0_BMCR, &reg);
+	} while (reg & BMCR_RESET);
+
+	/* forced MDI-X */
+	ret = phy_mc_vsc8541_write(dev, PHY_REG_PAGE1_EXT_MODE_CTRL, (3 << 2));
+	if (ret) {
+		return ret;
+	}
+
+	/* configure the RGMII clk delay */
+	/* this is highly hardware dependent and may vary between pcb designs */
+	reg = 0x0;
+	/* RX_CLK delay */
+	reg |= (0x5 << 4);
+	/* TX_CLK delay */
+	reg |= (0x5 << 0);
+	ret = phy_mc_vsc8541_write(dev, PHY_REG_PAGE2_RGMII_CONTROL, reg);
+	if (ret) {
+		return ret;
+	}
+
+	/* we use limited advertising, to force gigabit speed */
+	/* initial version of this driver supports only 1GB/s */
+
+	/* 1000MBit/s + AUTO */
+	ret = phy_mc_vsc8541_write(dev, PHY_REG_PAGE0_ADV, (1 << 8) | (1 << 6) | 0x01);
+	if (ret) {
+		return ret;
+	}
+
+	ret = phy_mc_vsc8541_write(dev, PHY_REG_PAGE0_CTRL1000, (1 << 12) | (1 << 11) | (1 << 9));
+	if (ret) {
+		return ret;
+	}
+
+	/* start auto negotiation */
+	ret = phy_mc_vsc8541_write(dev, PHY_REG_PAGE0_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
+	if (ret) {
+		return ret;
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Update the phy state with current speed given by readings of the phy
+ *
+ * @param dev device structure of the phy
+ * @param state being updated (we only update speed here)
+ */
+static int phy_mc_vsc8541_get_speed(const struct device *dev, struct phy_link_state *state)
+{
+	int ret;
+	uint32_t status;
+	uint32_t link10_status;
+	uint32_t link100_status;
+	uint32_t link1000_status;
+
+	ret = phy_mc_vsc8541_read(dev, PHY_REG_PAGE0_BMSR, &status);
+	if (ret) {
+		return ret;
+	}
+
+	ret = phy_mc_vsc8541_read(dev, PHY_REG_PAGE0_EXT_CTRL_STAT, &link10_status);
+	if (ret) {
+		return ret;
+	}
+
+	ret = phy_mc_vsc8541_read(dev, PHY_REG_PAGE0_STAT100, &link100_status);
+	if (ret) {
+		return ret;
+	}
+
+	ret = phy_mc_vsc8541_read(dev, PHY_REG_PAGE0_STAT1000_EXT2, &link1000_status);
+	if (ret) {
+		return ret;
+	}
+
+	if ((status & (1 << 2)) == 0) {
+		/* no link */
+		state->speed = LINK_HALF_10BASE_T;
+	}
+
+	if ((status & (1 << 5)) == 0) {
+		/* auto negotiation not yet complete */
+		state->speed = LINK_HALF_10BASE_T;
+	}
+
+	if ((link1000_status & (1 << 12))) {
+		state->speed = LINK_FULL_1000BASE_T;
+	}
+	if (link100_status & (1 << 12)) {
+		state->speed = LINK_FULL_100BASE_T;
+	}
+	if (link10_status & (1 << 6)) {
+		state->speed = LINK_FULL_10BASE_T;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Initializes the phy and starts the link monitor
+ *
+ */
+static int phy_mc_vsc8541_init(const struct device *dev)
+{
+	struct mc_vsc8541_data *data = dev->data;
+
+	data->cb = NULL;
+	data->cb_data = NULL;
+	data->state.is_up = false;
+	data->state.speed = LINK_HALF_10BASE_T;
+	data->active_page = -1;
+
+	/* Reset PHY */
+	int ret = phy_mc_vsc8541_reset(dev);
+
+	if (ret) {
+		LOG_ERR("initialize failed");
+		return ret;
+	}
+
+	/* setup thread to watch link state */
+	k_thread_create(&data->link_monitor_thread,
+			(k_thread_stack_t *)data->link_monitor_thread_stack, STACK_SIZE,
+			phy_mc_vsc8541_link_monitor, (void *)dev, NULL, NULL, THREAD_PRIORITY, 0,
+			K_NO_WAIT);
+
+	k_thread_name_set(&data->link_monitor_thread, "phy-link-mon");
+
+	return 0;
+}
+
+/**
+ * @brief Update the link status with readings from phy
+ *
+ * @param dev device structure to phy
+ * @param state which is being updated
+ */
+static int phy_mc_vsc8541_get_link(const struct device *dev, struct phy_link_state *state)
+{
+	int ret;
+	uint32_t reg_sr;
+	uint32_t reg_cr;
+
+	ret = phy_mc_vsc8541_read(dev, PHY_REG_PAGE0_BMSR, &reg_sr);
+	if (ret) {
+		return ret;
+	}
+
+	ret = phy_mc_vsc8541_read(dev, PHY_REG_PAGE0_BMCR, &reg_cr);
+	if (ret) {
+		return ret;
+	}
+
+	uint32_t hasLink = reg_sr & (1 << 2) ? 1 : 0;
+
+	uint32_t auto_negotiation_finished;
+
+	if (reg_cr & (BMCR_ANENABLE)) {
+		/* auto negotiation active; update status */
+		auto_negotiation_finished = reg_sr & (1 << 5) ? 1 : 0;
+	} else {
+		auto_negotiation_finished = 1;
+	}
+
+	if (hasLink & auto_negotiation_finished) {
+		state->is_up = 1;
+		ret = phy_mc_vsc8541_get_speed(dev, state);
+		if (ret) {
+			return ret;
+		}
+	} else {
+		state->is_up = 0;
+		state->speed = LINK_HALF_10BASE_T;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Reconfigure the link speed; currently unused
+ *
+ */
+static int phy_mc_vsc8541_cfg_link(const struct device *dev, enum phy_link_speed speeds)
+{
+	/* the initial version does not support reconfiguration */
+	return -ENOTSUP;
+}
+
+/**
+ * @brief Set callback which is used to announce link status changes
+ *
+ * @param dev device structure to phy device
+ * @param cb
+ * @param user_data
+ */
+static int phy_mc_vsc8541_link_cb_set(const struct device *dev, phy_callback_t cb, void *user_data)
+{
+	struct mc_vsc8541_data *data = dev->data;
+
+	data->cb = cb;
+	data->cb_data = user_data;
+
+	phy_mc_vsc8541_get_link(dev, &data->state);
+
+	data->cb(dev, &data->state, data->cb_data);
+
+	return 0;
+}
+
+/**
+ * @brief Monitor thread to check the link state and announce if changed
+ *
+ * @param arg1 provides a pointer to device structure
+ * @param arg2 not used
+ * @param arg3 not used
+ */
+void phy_mc_vsc8541_link_monitor(void *arg1, void *arg2, void *arg3)
+{
+	const struct device *dev = arg1;
+	struct mc_vsc8541_data *data = dev->data;
+	const struct mc_vsc8541_config *cfg = dev->config;
+
+	struct phy_link_state new_state;
+
+	while (1) {
+		k_sleep(K_MSEC(CONFIG_PHY_MONITOR_PERIOD));
+		phy_mc_vsc8541_get_link(dev, &new_state);
+
+		if ((new_state.is_up != data->state.is_up) ||
+		    (new_state.speed != data->state.speed)) {
+			/* state changed */
+			data->state.is_up = new_state.is_up;
+			data->state.speed = new_state.speed;
+
+			if (data->cb) {
+				/* announce new state */
+				data->cb(dev, &data->state, data->cb_data);
+			}
+		}
+	}
+}
+
+/**
+ * @brief Reading of phy register content at given address via mdio interface
+ *
+ * - high byte of register address defines page
+ * - low byte of register address defines the address within selected page
+ * - to speed up, we store the last used page and only swap page if needed
+ *
+ */
+static int phy_mc_vsc8541_read(const struct device *dev, uint16_t reg_addr, uint32_t *data)
+{
+	const struct mc_vsc8541_config *cfg = dev->config;
+	struct mc_vsc8541_data *dev_data = dev->data;
+	int ret;
+
+	*data = 0U;
+
+	/* decode page */
+	uint32_t page = reg_addr >> 8;
+
+	/* mask out lower byte */
+	reg_addr &= 0x00ff;
+
+	/* select page, given by register upper byte */
+	if (dev_data->active_page != page) {
+		ret = mdio_write(cfg->mdio_dev, cfg->addr, PHY_REG_PAGE_SELECTOR, (uint16_t)page);
+		if (ret) {
+			return ret;
+		}
+		dev_data->active_page = (int)page;
+	}
+
+	/* select register, given by register lower byte */
+	ret = mdio_read(cfg->mdio_dev, cfg->addr, reg_addr, (uint16_t *)data);
+	if (ret) {
+		return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Writing of new value to phy register at given address via mdio interface
+ *
+ * - high byte of register address defines page
+ * - low byte of register address defines the address within selected page
+ * - to speed up, we store the last used page and only swap page if needed
+ *
+ */
+static int phy_mc_vsc8541_write(const struct device *dev, uint16_t reg_addr, uint32_t data)
+{
+	const struct mc_vsc8541_config *cfg = dev->config;
+	struct mc_vsc8541_data *dev_data = dev->data;
+	int ret;
+
+	/* decode page */
+	uint32_t page = reg_addr >> 8;
+
+	/* mask out lower byte */
+	reg_addr &= 0x00ff;
+
+	/* select page, given by register upper byte */
+	if (dev_data->active_page != page) {
+		ret = mdio_write(cfg->mdio_dev, cfg->addr, PHY_REG_PAGE_SELECTOR, (uint16_t)page);
+		if (ret) {
+			return ret;
+		}
+		dev_data->active_page = (int)page;
+	}
+
+	/* write register, given by lower byte */
+	ret = mdio_write(cfg->mdio_dev, cfg->addr, reg_addr, (uint16_t)data);
+	if (ret) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(ethphy, mc_vsc8541_phy_api) = {
+	.get_link = phy_mc_vsc8541_get_link,
+	.cfg_link = phy_mc_vsc8541_cfg_link,
+	.link_cb_set = phy_mc_vsc8541_link_cb_set,
+	.read = phy_mc_vsc8541_read,
+	.write = phy_mc_vsc8541_write,
+};
+
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios)
+#define RESET_GPIO(n) .reset_gpio = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {0}),
+#else
+#define RESET_GPIO(n)
+#endif /* reset gpio */
+
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
+#define INTERRUPT_GPIO(n) .interrupt_gpio = GPIO_DT_SPEC_INST_GET_OR(n, int_gpios, {0}),
+#else
+#define INTERRUPT_GPIO(n)
+#endif /* interrupt gpio */
+
+#define MICROCHIP_VSC8541_INIT(n)                                                                  \
+	static const struct mc_vsc8541_config mc_vsc8541_##n##_config = {                          \
+		.addr = DT_INST_REG_ADDR(n),                                                       \
+		.mdio_dev = DEVICE_DT_GET(DT_INST_PARENT(n)),                                      \
+		.microchip_interface_type = DT_INST_ENUM_IDX(n, microchip_interface_type),         \
+		RESET_GPIO(n) INTERRUPT_GPIO(n)};                                                  \
+                                                                                                   \
+	static struct mc_vsc8541_data mc_vsc8541_##n##_data;                                       \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, &phy_mc_vsc8541_init, NULL, &mc_vsc8541_##n##_data,               \
+			      &mc_vsc8541_##n##_config, POST_KERNEL, CONFIG_PHY_INIT_PRIORITY,     \
+			      &mc_vsc8541_phy_api);
+
+DT_INST_FOREACH_STATUS_OKAY(MICROCHIP_VSC8541_INIT)
diff --git a/drivers/ethernet/phy/phy_mii.c b/drivers/ethernet/phy/phy_mii.c
index a19eb252bb1..b2abf474d9e 100644
--- a/drivers/ethernet/phy/phy_mii.c
+++ b/drivers/ethernet/phy/phy_mii.c
@@ -31,9 +31,11 @@ struct phy_mii_dev_data {
 	phy_callback_t cb;
 	void *cb_data;
 	struct k_work_delayable monitor_work;
+	struct k_work_delayable autoneg_work;
 	struct phy_link_state state;
 	struct k_sem sem;
 	bool gigabit_supported;
+	uint32_t autoneg_timeout;
 };
 
 /* Offset to align capabilities bits of 1000BASE-T Control and Status regs */
@@ -41,6 +43,9 @@ struct phy_mii_dev_data {
 
 #define MII_INVALID_PHY_ID UINT32_MAX
 
+/* How often to poll auto-negotiation status while waiting for it to complete */
+#define MII_AUTONEG_POLL_INTERVAL_MS 100
+
 static int phy_mii_get_link_state(const struct device *dev,
 				  struct phy_link_state *state);
 
@@ -50,9 +55,14 @@ static inline int phy_mii_reg_read(const struct device *dev, uint16_t reg_addr,
 	const struct phy_mii_dev_config *const cfg = dev->config;
 
 	/* if there is no mdio (fixed-link) it is not supported to read */
-	if (cfg->mdio == NULL) {
+	if (cfg->fixed) {
 		return -ENOTSUP;
 	}
+
+	if (cfg->mdio == NULL) {
+		return -ENODEV;
+	}
+
 	return mdio_read(cfg->mdio, cfg->phy_addr, reg_addr, value);
 }
 
@@ -62,9 +72,14 @@ static inline int phy_mii_reg_write(const struct device *dev, uint16_t reg_addr,
 	const struct phy_mii_dev_config *const cfg = dev->config;
 
 	/* if there is no mdio (fixed-link) it is not supported to write */
-	if (cfg->mdio == NULL) {
+	if (cfg->fixed) {
 		return -ENOTSUP;
 	}
+
+	if (cfg->mdio == NULL) {
+		return -ENODEV;
+	}
+
 	return mdio_write(cfg->mdio, cfg->phy_addr, reg_addr, value);
 }
 
@@ -145,13 +160,8 @@ static int update_link_state(const struct device *dev)
 	struct phy_mii_dev_data *const data = dev->data;
 	bool link_up;
 
-	uint16_t anar_reg = 0;
 	uint16_t bmcr_reg = 0;
 	uint16_t bmsr_reg = 0;
-	uint16_t anlpar_reg = 0;
-	uint16_t c1kt_reg = 0;
-	uint16_t s1kt_reg = 0;
-	uint32_t timeout = CONFIG_PHY_AUTONEG_TIMEOUT_MS / 100;
 
 	if (phy_mii_reg_read(dev, MII_BMSR, &bmsr_reg) < 0) {
 		return -EIO;
@@ -178,11 +188,6 @@ static int update_link_state(const struct device *dev)
 	LOG_DBG("PHY (%d) Starting MII PHY auto-negotiate sequence",
 		cfg->phy_addr);
 
-	/* Read PHY default advertising parameters */
-	if (phy_mii_reg_read(dev, MII_ANAR, &anar_reg) < 0) {
-		return -EIO;
-	}
-
 	/* Configure and start auto-negotiation process */
 	if (phy_mii_reg_read(dev, MII_BMCR, &bmcr_reg) < 0) {
 		return -EIO;
@@ -195,15 +200,21 @@ static int update_link_state(const struct device *dev)
 		return -EIO;
 	}
 
-	/* Wait for the auto-negotiation process to complete */
-	do {
-		if (timeout-- == 0U) {
-			LOG_DBG("PHY (%d) auto-negotiate timedout",
-				cfg->phy_addr);
-			return -ETIMEDOUT;
-		}
+	/* We have to wait for the auto-negotiation process to complete */
+	data->autoneg_timeout = CONFIG_PHY_AUTONEG_TIMEOUT_MS / MII_AUTONEG_POLL_INTERVAL_MS;
+	return -EINPROGRESS;
+}
+
+static int check_autonegotiation_completion(const struct device *dev)
+{
+	const struct phy_mii_dev_config *const cfg = dev->config;
+	struct phy_mii_dev_data *const data = dev->data;
 
-		k_sleep(K_MSEC(100));
+	uint16_t anar_reg = 0;
+	uint16_t bmsr_reg = 0;
+	uint16_t anlpar_reg = 0;
+	uint16_t c1kt_reg = 0;
+	uint16_t s1kt_reg = 0;
 
 		/* On some PHY chips, the BMSR bits are latched, so the first read may
 		 * show incorrect status. A second read ensures correct values.
@@ -216,11 +227,23 @@ static int update_link_state(const struct device *dev)
 		if (phy_mii_reg_read(dev, MII_BMSR, &bmsr_reg) < 0) {
 			return -EIO;
 		}
-	} while (!(bmsr_reg & MII_BMSR_AUTONEG_COMPLETE));
+
+	if (!(bmsr_reg & MII_BMSR_AUTONEG_COMPLETE)) {
+		if (data->autoneg_timeout-- == 0U) {
+			LOG_DBG("PHY (%d) auto-negotiate timedout", cfg->phy_addr);
+			return -ETIMEDOUT;
+		}
+		return -EINPROGRESS;
+	}
 
 	LOG_DBG("PHY (%d) auto-negotiate sequence completed",
 		cfg->phy_addr);
 
+	/* Read PHY default advertising parameters */
+	if (phy_mii_reg_read(dev, MII_ANAR, &anar_reg) < 0) {
+		return -EIO;
+	}
+
 	/** Read peer device capability */
 	if (phy_mii_reg_read(dev, MII_ANLPAR, &anlpar_reg) < 0) {
 		return -EIO;
@@ -283,7 +306,12 @@ static void monitor_work_handler(struct k_work *work)
 	const struct device *dev = data->dev;
 	int rc;
 
-	k_sem_take(&data->sem, K_FOREVER);
+	if (k_sem_take(&data->sem, K_NO_WAIT) != 0) {
+		/* Try again soon */
+		k_work_reschedule(&data->monitor_work,
+				  K_MSEC(MII_AUTONEG_POLL_INTERVAL_MS));
+		return;
+	}
 
 	rc = update_link_state(dev);
 
@@ -294,9 +322,49 @@ static void monitor_work_handler(struct k_work *work)
 		invoke_link_cb(dev);
 	}
 
-	/* Submit delayed work */
-	k_work_reschedule(&data->monitor_work,
-			  K_MSEC(CONFIG_PHY_MONITOR_PERIOD));
+	if (rc == -EINPROGRESS) {
+		/* Check for autonegotiation completion */
+		k_work_reschedule(&data->autoneg_work,
+				  K_MSEC(MII_AUTONEG_POLL_INTERVAL_MS));
+	} else {
+		/* Submit delayed work */
+		k_work_reschedule(&data->monitor_work, K_MSEC(CONFIG_PHY_MONITOR_PERIOD));
+	}
+}
+
+static void autoneg_work_handler(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct phy_mii_dev_data *const data =
+		CONTAINER_OF(dwork, struct phy_mii_dev_data, autoneg_work);
+	const struct device *dev = data->dev;
+	int rc;
+
+	if (k_sem_take(&data->sem, K_NO_WAIT) != 0) {
+		/* Try again soon */
+		k_work_reschedule(&data->autoneg_work,
+				  K_MSEC(MII_AUTONEG_POLL_INTERVAL_MS));
+		return;
+	}
+
+	rc = check_autonegotiation_completion(dev);
+
+	k_sem_give(&data->sem);
+
+	/* If link state has changed and a callback is set, invoke callback */
+	if (rc == 0) {
+		invoke_link_cb(dev);
+	}
+
+	if (rc == -EINPROGRESS) {
+		/* Check again soon */
+		k_work_reschedule(&data->autoneg_work,
+				  K_MSEC(MII_AUTONEG_POLL_INTERVAL_MS));
+	} else {
+		/* Schedule the next monitoring call */
+		k_work_reschedule(&data->monitor_work,
+				  K_MSEC(CONFIG_PHY_MONITOR_PERIOD));
+	}
 }
 
 static int phy_mii_read(const struct device *dev, uint16_t reg_addr,
@@ -315,10 +383,20 @@ static int phy_mii_cfg_link(const struct device *dev,
 			    enum phy_link_speed adv_speeds)
 {
 	struct phy_mii_dev_data *const data = dev->data;
+	const struct phy_mii_dev_config *const cfg = dev->config;
 	uint16_t anar_reg;
 	uint16_t bmcr_reg;
 	uint16_t c1kt_reg;
 
+	/* if there is no mdio (fixed-link) it is not supported to configure link */
+	if (cfg->fixed) {
+		return -ENOTSUP;
+	}
+
+	if (cfg->mdio == NULL) {
+		return -ENODEV;
+	}
+
 	if (phy_mii_reg_read(dev, MII_ANAR, &anar_reg) < 0) {
 		return -EIO;
 	}
@@ -479,6 +557,8 @@ static int phy_mii_initialize(const struct device *dev)
 
 		k_work_init_delayable(&data->monitor_work,
 					monitor_work_handler);
+		k_work_init_delayable(&data->autoneg_work,
+					autoneg_work_handler);
 
 		monitor_work_handler(&data->monitor_work.work);
 	}
diff --git a/drivers/ethernet/phy/phy_oa_tc14_plca.c b/drivers/ethernet/phy/phy_oa_tc14_plca.c
new file mode 100644
index 00000000000..1505bae8f78
--- /dev/null
+++ b/drivers/ethernet/phy/phy_oa_tc14_plca.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2024 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/net/mdio.h>
+#include <zephyr/net/phy.h>
+#include <errno.h>
+
+/* Open Alliance TC14 (10BASE-T1S) PLCA registers */
+#define MDIO_OATC14_PLCA_IDVER  0xca00 /* PLCA ID and version */
+#define MDIO_OATC14_PLCA_CTRL0  0xca01 /* PLCA Control register 0 */
+#define MDIO_OATC14_PLCA_CTRL1  0xca02 /* PLCA Control register 1 */
+#define MDIO_OATC14_PLCA_STATUS 0xca03 /* PLCA Status register */
+#define MDIO_OATC14_PLCA_TOTMR  0xca04 /* PLCA TO Timer register */
+#define MDIO_OATC14_PLCA_BURST  0xca05 /* PLCA BURST mode register */
+
+/* Open Alliance TC14 PLCA IDVER register */
+#define MDIO_OATC14_PLCA_IDM GENMASK(15, 8) /* PLCA MAP ID */
+#define MDIO_OATC14_PLCA_VER GENMASK(7, 0)  /* PLCA MAP version */
+
+/* Open Alliance TC14 PLCA CTRL0 register */
+#define MDIO_OATC14_PLCA_EN  BIT(15) /* PLCA enable */
+#define MDIO_OATC14_PLCA_RST BIT(14) /* PLCA reset */
+
+/* Open Alliance TC14 PLCA CTRL1 register */
+#define MDIO_OATC14_PLCA_NCNT GENMASK(15, 8) /* PLCA node count */
+#define MDIO_OATC14_PLCA_ID   GENMASK(7, 0)  /* PLCA local node ID */
+
+/* Open Alliance TC14 PLCA STATUS register */
+#define MDIO_OATC14_PLCA_PST BIT(15) /* PLCA status indication */
+
+/* Open Alliance TC14 PLCA TOTMR register */
+#define MDIO_OATC14_PLCA_TOT GENMASK(7, 0)
+
+/* Open Alliance TC14 PLCA BURST register */
+#define MDIO_OATC14_PLCA_MAXBC GENMASK(15, 8)
+#define MDIO_OATC14_PLCA_BTMR  GENMASK(7, 0)
+
+/* Version Identifiers */
+#define OATC14_IDM 0x0a00
+
+int genphy_set_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg)
+{
+	uint16_t val;
+	int ret;
+
+	/* Disable plca before doing the configuration */
+	ret = phy_write_c45(dev, MDIO_MMD_VENDOR_SPECIFIC2, MDIO_OATC14_PLCA_CTRL0, 0x0);
+	if (ret) {
+		return ret;
+	}
+
+	if (!plca_cfg->enable) {
+		/* As the PLCA is disabled above, just return */
+		return 0;
+	}
+
+	val = (plca_cfg->node_count << 8) | plca_cfg->node_id;
+	ret = phy_write_c45(dev, MDIO_MMD_VENDOR_SPECIFIC2, MDIO_OATC14_PLCA_CTRL1, val);
+	if (ret) {
+		return ret;
+	}
+
+	val = (plca_cfg->burst_count << 8) | plca_cfg->burst_timer;
+	ret = phy_write_c45(dev, MDIO_MMD_VENDOR_SPECIFIC2, MDIO_OATC14_PLCA_BURST, val);
+	if (ret) {
+		return ret;
+	}
+
+	ret = phy_write_c45(dev, MDIO_MMD_VENDOR_SPECIFIC2, MDIO_OATC14_PLCA_TOTMR,
+			    plca_cfg->to_timer);
+	if (ret) {
+		return ret;
+	}
+
+	/* Enable plca after doing all the configuration */
+	return phy_write_c45(dev, MDIO_MMD_VENDOR_SPECIFIC2, MDIO_OATC14_PLCA_CTRL0,
+			     MDIO_OATC14_PLCA_EN);
+}
+
+int genphy_get_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg)
+{
+	uint16_t val;
+	int ret;
+
+	ret = phy_read_c45(dev, MDIO_MMD_VENDOR_SPECIFIC2, MDIO_OATC14_PLCA_IDVER, &val);
+	if (ret) {
+		return ret;
+	}
+
+	if ((val & MDIO_OATC14_PLCA_IDM) != OATC14_IDM) {
+		return -ENODEV;
+	}
+
+	plca_cfg->version = ret & ~MDIO_OATC14_PLCA_IDM;
+
+	ret = phy_read_c45(dev, MDIO_MMD_VENDOR_SPECIFIC2, MDIO_OATC14_PLCA_CTRL0, &val);
+	if (ret) {
+		return ret;
+	}
+
+	plca_cfg->enable = !!(val & MDIO_OATC14_PLCA_EN);
+
+	ret = phy_read_c45(dev, MDIO_MMD_VENDOR_SPECIFIC2, MDIO_OATC14_PLCA_CTRL1, &val);
+	if (ret) {
+		return ret;
+	}
+
+	plca_cfg->node_id = val & MDIO_OATC14_PLCA_ID;
+	plca_cfg->node_count = (val & MDIO_OATC14_PLCA_NCNT) >> 8;
+
+	ret = phy_read_c45(dev, MDIO_MMD_VENDOR_SPECIFIC2, MDIO_OATC14_PLCA_BURST, &val);
+	if (ret) {
+		return ret;
+	}
+
+	plca_cfg->burst_timer = val & MDIO_OATC14_PLCA_BTMR;
+	plca_cfg->burst_count = (val & MDIO_OATC14_PLCA_MAXBC) >> 8;
+
+	ret = phy_read_c45(dev, MDIO_MMD_VENDOR_SPECIFIC2, MDIO_OATC14_PLCA_TOTMR, &val);
+	if (ret) {
+		return ret;
+	}
+
+	plca_cfg->to_timer = val & MDIO_OATC14_PLCA_TOT;
+
+	return 0;
+}
+
+int genphy_get_plca_sts(const struct device *dev, bool *plca_sts)
+{
+	uint16_t val;
+	int ret;
+
+	ret = phy_read_c45(dev, MDIO_MMD_VENDOR_SPECIFIC2, MDIO_OATC14_PLCA_STATUS, &val);
+	if (ret) {
+		return ret;
+	}
+
+	*plca_sts = !!(val & MDIO_OATC14_PLCA_PST);
+
+	return 0;
+}
diff --git a/drivers/ethernet/phy/phy_ti_dp83867.c b/drivers/ethernet/phy/phy_ti_dp83867.c
new file mode 100644
index 00000000000..84b3b4d14d9
--- /dev/null
+++ b/drivers/ethernet/phy/phy_ti_dp83867.c
@@ -0,0 +1,558 @@
+/*
+ * Copyright 2024, PHYTEC America, LLC
+ * Author: Florijan Plohl <florijan.plohl@norik.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ti_dp83867
+
+#include <zephyr/kernel.h>
+#include <zephyr/net/phy.h>
+#include <zephyr/net/mii.h>
+#include <zephyr/drivers/mdio.h>
+#include <string.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/drivers/gpio.h>
+
+#define LOG_MODULE_NAME phy_ti_dp83867
+#define LOG_LEVEL       CONFIG_PHY_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(LOG_MODULE_NAME, LOG_LEVEL);
+
+#define PHY_TI_DP83867_PHYSTS                 0x11
+#define PHY_TI_DP83867_PHYSTS_LINKSTATUS_MASK BIT(10)
+#define PHY_TI_DP83867_PHYSTS_LINKDUPLEX_MASK BIT(13)
+#define PHY_TI_DP83867_PHYSTS_LINKSPEED_MASK  (BIT(14) | BIT(15))
+#define PHY_TI_DP83867_PHYSTS_LINKSPEED_SHIFT (14U)
+
+#define PHY_TI_DP83867_PHYSTS_LINKSPEED_10M   (0U)
+#define PHY_TI_DP83867_PHYSTS_LINKSPEED_100M  (1U)
+#define PHY_TI_DP83867_PHYSTS_LINKSPEED_1000M (2U)
+
+#define PHY_TI_DP83867_RESET_PULSE_WIDTH 1
+#define PHY_TI_DP83867_POR_DELAY         200
+
+#define PHY_TI_DP83867_MICR                    0x0012
+#define PHY_TI_DP83867_ISR                     0x0013
+#define PHY_TI_DP83867_LINK_STATUS_CHNG_INT_EN BIT(10)
+#define PHY_TI_DP83867_CFG3                    0x001e
+#define PHY_TI_DP83867_INT_EN                  BIT(7)
+
+struct ti_dp83867_config {
+	uint8_t addr;
+	const struct device *mdio_dev;
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios)
+	const struct gpio_dt_spec reset_gpio;
+#endif
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
+	const struct gpio_dt_spec interrupt_gpio;
+#endif
+};
+
+struct ti_dp83867_data {
+	const struct device *dev;
+	struct phy_link_state state;
+	phy_callback_t cb;
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
+	struct gpio_callback gpio_callback;
+#endif
+	void *cb_data;
+	struct k_mutex mutex;
+	struct k_work_delayable phy_monitor_work;
+};
+
+static int phy_ti_dp83867_read(const struct device *dev, uint16_t reg_addr, uint32_t *data)
+{
+	const struct ti_dp83867_config *config = dev->config;
+	int ret;
+
+	/* Make sure excessive bits 16-31 are reset */
+	*data = 0U;
+
+	ret = mdio_read(config->mdio_dev, config->addr, reg_addr, (uint16_t *)data);
+	if (ret) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static int phy_ti_dp83867_write(const struct device *dev, uint16_t reg_addr, uint32_t data)
+{
+	const struct ti_dp83867_config *config = dev->config;
+	int ret;
+
+	ret = mdio_write(config->mdio_dev, config->addr, reg_addr, (uint16_t)data);
+	if (ret) {
+		return ret;
+	}
+
+	return 0;
+}
+
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
+static int phy_ti_dp83867_clear_interrupt(struct ti_dp83867_data *data)
+{
+	const struct device *dev = data->dev;
+	const struct ti_dp83867_config *config = dev->config;
+	uint32_t reg_val;
+	int ret;
+
+	/* Lock mutex */
+	ret = k_mutex_lock(&data->mutex, K_FOREVER);
+	if (ret) {
+		LOG_ERR("PHY mutex lock error");
+		return ret;
+	}
+
+	/* Read/clear PHY interrupt status register */
+	ret = phy_ti_dp83867_read(dev, PHY_TI_DP83867_ISR, &reg_val);
+	if (ret) {
+		LOG_ERR("Error reading phy (%d) interrupt status register", config->addr);
+	}
+
+	/* Unlock mutex */
+	(void)k_mutex_unlock(&data->mutex);
+
+	return ret;
+}
+
+static void phy_ti_dp83867_interrupt_handler(const struct device *port, struct gpio_callback *cb,
+					     gpio_port_pins_t pins)
+{
+	struct ti_dp83867_data *data = CONTAINER_OF(cb, struct ti_dp83867_data, gpio_callback);
+	int ret;
+
+	ret = k_work_reschedule(&data->phy_monitor_work, K_NO_WAIT);
+	if (ret < 0) {
+		LOG_ERR("Failed to schedule phy_monitor_work from ISR");
+	}
+}
+#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) */
+
+static int phy_ti_dp83867_autonegotiate(const struct device *dev)
+{
+	const struct ti_dp83867_config *config = dev->config;
+	int ret;
+	uint32_t bmcr = 0;
+
+	/* Read control register to write back with autonegotiation bit */
+	ret = phy_ti_dp83867_read(dev, MII_BMCR, &bmcr);
+	if (ret) {
+		LOG_ERR("Error reading phy (%d) basic control register", config->addr);
+		return ret;
+	}
+
+	/* (re)start autonegotiation */
+	LOG_DBG("PHY (%d) is entering autonegotiation sequence", config->addr);
+	bmcr |= MII_BMCR_AUTONEG_ENABLE | MII_BMCR_AUTONEG_RESTART;
+
+	ret = phy_ti_dp83867_write(dev, MII_BMCR, bmcr);
+	if (ret) {
+		LOG_ERR("Error writing phy (%d) basic control register", config->addr);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int phy_ti_dp83867_get_link(const struct device *dev, struct phy_link_state *state)
+{
+	const struct ti_dp83867_config *config = dev->config;
+	struct ti_dp83867_data *data = dev->data;
+	int ret;
+	uint32_t physr = 0;
+	uint32_t duplex = 0;
+	struct phy_link_state old_state = data->state;
+	struct phy_link_state new_state = {};
+
+	/* Lock mutex */
+	ret = k_mutex_lock(&data->mutex, K_FOREVER);
+	if (ret) {
+		LOG_ERR("PHY mutex lock error");
+		return ret;
+	}
+
+	/* Read PHY status register */
+	ret = phy_ti_dp83867_read(dev, PHY_TI_DP83867_PHYSTS, &physr);
+	if (ret) {
+		LOG_ERR("Error reading phy (%d) specific status register", config->addr);
+		(void)k_mutex_unlock(&data->mutex);
+		return ret;
+	}
+
+	/* Unlock mutex */
+	(void)k_mutex_unlock(&data->mutex);
+
+	new_state.is_up = physr & PHY_TI_DP83867_PHYSTS_LINKSTATUS_MASK;
+
+	if (new_state.is_up) {
+		duplex = (physr & PHY_TI_DP83867_PHYSTS_LINKDUPLEX_MASK);
+		switch ((physr & PHY_TI_DP83867_PHYSTS_LINKSPEED_MASK) >>
+			PHY_TI_DP83867_PHYSTS_LINKSPEED_SHIFT) {
+		case PHY_TI_DP83867_PHYSTS_LINKSPEED_1000M:
+			if (duplex) {
+				new_state.speed = LINK_FULL_1000BASE_T;
+			} else {
+				new_state.speed = LINK_HALF_1000BASE_T;
+			}
+			break;
+		case PHY_TI_DP83867_PHYSTS_LINKSPEED_100M:
+			if (duplex) {
+				new_state.speed = LINK_FULL_100BASE_T;
+			} else {
+				new_state.speed = LINK_HALF_100BASE_T;
+			}
+			break;
+		case PHY_TI_DP83867_PHYSTS_LINKSPEED_10M:
+		default:
+			if (duplex) {
+				new_state.speed = LINK_FULL_10BASE_T;
+			} else {
+				new_state.speed = LINK_HALF_10BASE_T;
+			}
+			break;
+		}
+	}
+
+	if (memcmp(&old_state, &new_state, sizeof(struct phy_link_state)) != 0) {
+		LOG_INF("PHY %d is %s", config->addr, new_state.is_up ? "up" : "down");
+		if (new_state.is_up) {
+			LOG_INF("PHY (%d) Link speed %s Mb, %s duplex", config->addr,
+				(PHY_LINK_IS_SPEED_1000M(new_state.speed)
+					 ? "1000"
+					 : (PHY_LINK_IS_SPEED_100M(new_state.speed) ? "100"
+										    : "10")),
+				PHY_LINK_IS_FULL_DUPLEX(new_state.speed) ? "full" : "half");
+		}
+	}
+
+	memcpy(state, &new_state, sizeof(struct phy_link_state));
+
+	return ret;
+}
+
+static int phy_ti_dp83867_reset(const struct device *dev)
+{
+	const struct ti_dp83867_config *config = dev->config;
+	struct ti_dp83867_data *data = dev->data;
+	int ret;
+
+	/* Lock mutex */
+	ret = k_mutex_lock(&data->mutex, K_FOREVER);
+	if (ret) {
+		LOG_ERR("PHY mutex lock error");
+		return ret;
+	}
+
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios)
+	if (config->reset_gpio.port) {
+		ret = gpio_pin_set_dt(&config->reset_gpio, 1);
+		if (ret >= 0) {
+			/* Reset pulse (minimum specified width is T1=1us) */
+			k_busy_wait(PHY_TI_DP83867_RESET_PULSE_WIDTH);
+
+			ret = gpio_pin_set_dt(&config->reset_gpio, 0);
+			if (ret >= 0) {
+				goto done;
+			}
+		}
+	}
+#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios) */
+
+	/* Reset PHY using register */
+	ret = phy_ti_dp83867_write(dev, MII_BMCR, MII_BMCR_RESET);
+	if (ret < 0) {
+		LOG_ERR("Error writing phy (%d) basic control register", config->addr);
+	}
+
+done:
+	/* POR release time (minimum specified is T4=195us) */
+	k_busy_wait(PHY_TI_DP83867_POR_DELAY);
+
+	/* Unlock mutex */
+	k_mutex_unlock(&data->mutex);
+	LOG_DBG("PHY (%d) reset completed", config->addr);
+
+	return ret;
+}
+
+static int phy_ti_dp83867_cfg_link(const struct device *dev, enum phy_link_speed speeds)
+{
+	const struct ti_dp83867_config *config = dev->config;
+	struct ti_dp83867_data *data = dev->data;
+	int ret;
+	uint32_t anar, cfg1, val;
+
+	/* Lock mutex */
+	ret = k_mutex_lock(&data->mutex, K_FOREVER);
+	if (ret) {
+		LOG_ERR("PHY mutex lock error");
+		goto done;
+	}
+
+	/* We are going to reconfigure the phy, don't need to monitor until done */
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
+	if (config->interrupt_gpio.port) {
+		/* Enable interrupt output register */
+		ret = phy_ti_dp83867_read(dev, PHY_TI_DP83867_CFG3, &val);
+		if (ret) {
+			LOG_ERR("Error reading phy (%d) CFG3 register", config->addr);
+			goto done;
+		}
+
+		val |= PHY_TI_DP83867_INT_EN;
+		ret = phy_ti_dp83867_write(dev, PHY_TI_DP83867_CFG3, val);
+		if (ret) {
+			LOG_ERR("Error writing phy (%d) CFG3 register", config->addr);
+			goto done;
+		}
+
+		/* Enable link status change interrupt */
+		ret = phy_ti_dp83867_read(dev, PHY_TI_DP83867_MICR, &val);
+		if (ret) {
+			LOG_ERR("Error reading phy (%d) MICR register", config->addr);
+			goto done;
+		}
+
+		val |= PHY_TI_DP83867_LINK_STATUS_CHNG_INT_EN;
+		ret = phy_ti_dp83867_write(dev, PHY_TI_DP83867_MICR, val);
+		if (ret) {
+			LOG_ERR("Error writing phy (%d) MICR register", config->addr);
+			goto done;
+		}
+
+	} else {
+		k_work_cancel_delayable(&data->phy_monitor_work);
+	}
+#else
+	k_work_cancel_delayable(&data->phy_monitor_work);
+#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) */
+
+	/* Read ANAR register to write back */
+	ret = phy_ti_dp83867_read(dev, MII_ANAR, &anar);
+	if (ret) {
+		LOG_ERR("Error reading phy (%d) advertising register", config->addr);
+		goto done;
+	}
+
+	/* Read CFG1 register to write back */
+	ret = phy_ti_dp83867_read(dev, MII_1KTCR, &cfg1);
+	if (ret) {
+		LOG_ERR("Error reading phy (%d) 1000Base-T control register", config->addr);
+		goto done;
+	}
+
+	/* Setup advertising register */
+	if (speeds & LINK_FULL_100BASE_T) {
+		anar |= MII_ADVERTISE_100_FULL;
+	} else {
+		anar &= ~MII_ADVERTISE_100_FULL;
+	}
+	if (speeds & LINK_HALF_100BASE_T) {
+		anar |= MII_ADVERTISE_100_HALF;
+	} else {
+		anar &= ~MII_ADVERTISE_100_HALF;
+	}
+	if (speeds & LINK_FULL_10BASE_T) {
+		anar |= MII_ADVERTISE_10_FULL;
+	} else {
+		anar &= ~MII_ADVERTISE_10_FULL;
+	}
+	if (speeds & LINK_HALF_10BASE_T) {
+		anar |= MII_ADVERTISE_10_HALF;
+	} else {
+		anar &= ~MII_ADVERTISE_10_HALF;
+	}
+
+	/* Setup 1000Base-T control register */
+	if (speeds & LINK_FULL_1000BASE_T) {
+		cfg1 |= MII_ADVERTISE_1000_FULL;
+	} else {
+		cfg1 &= ~MII_ADVERTISE_1000_FULL;
+	}
+
+	/* Write capabilities to advertising register */
+	ret = phy_ti_dp83867_write(dev, MII_ANAR, anar);
+	if (ret) {
+		LOG_ERR("Error writing phy (%d) advertising register", config->addr);
+		goto done;
+	}
+
+	/* Write capabilities to 1000Base-T control register */
+	ret = phy_ti_dp83867_write(dev, MII_1KTCR, cfg1);
+	if (ret) {
+		LOG_ERR("Error writing phy (%d) 1000Base-T control register", config->addr);
+		goto done;
+	}
+
+	/* (re)do autonegotiation */
+	ret = phy_ti_dp83867_autonegotiate(dev);
+	if (ret && (ret != -ENETDOWN)) {
+		LOG_ERR("Error in autonegotiation");
+		goto done;
+	}
+
+done:
+	/* Unlock mutex */
+	k_mutex_unlock(&data->mutex);
+
+	/* Start monitoring */
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
+	if (config->interrupt_gpio.port) {
+		return ret;
+	}
+#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) */
+	k_work_reschedule(&data->phy_monitor_work, K_MSEC(CONFIG_PHY_MONITOR_PERIOD));
+
+	return ret;
+}
+
+static int phy_ti_dp83867_link_cb_set(const struct device *dev, phy_callback_t cb, void *user_data)
+{
+	struct ti_dp83867_data *data = dev->data;
+
+	data->cb = cb;
+	data->cb_data = user_data;
+
+	phy_ti_dp83867_get_link(dev, &data->state);
+
+	data->cb(dev, &data->state, data->cb_data);
+
+	return 0;
+}
+
+static void phy_ti_dp83867_monitor_work_handler(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct ti_dp83867_data *data =
+		CONTAINER_OF(dwork, struct ti_dp83867_data, phy_monitor_work);
+	const struct device *dev = data->dev;
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
+	const struct ti_dp83867_config *config = dev->config;
+#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) */
+	struct phy_link_state state = {};
+	int ret;
+
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
+	if (config->interrupt_gpio.port) {
+		ret = phy_ti_dp83867_clear_interrupt(data);
+		if (ret) {
+			return;
+		}
+	}
+#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) */
+
+	ret = phy_ti_dp83867_get_link(dev, &state);
+
+	if (ret == 0 && memcmp(&state, &data->state, sizeof(struct phy_link_state)) != 0) {
+		memcpy(&data->state, &state, sizeof(struct phy_link_state));
+		if (data->cb) {
+			data->cb(dev, &data->state, data->cb_data);
+		}
+	}
+
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
+	if (config->interrupt_gpio.port) {
+		return;
+	}
+#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) */
+	k_work_reschedule(&data->phy_monitor_work, K_MSEC(CONFIG_PHY_MONITOR_PERIOD));
+}
+
+static int phy_ti_dp83867_init(const struct device *dev)
+{
+	const struct ti_dp83867_config *config = dev->config;
+	struct ti_dp83867_data *data = dev->data;
+	int ret;
+
+	data->dev = dev;
+
+	ret = k_mutex_init(&data->mutex);
+	if (ret) {
+		return ret;
+	}
+
+	mdio_bus_enable(config->mdio_dev);
+
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios)
+	if (config->reset_gpio.port) {
+		ret = gpio_pin_configure_dt(&config->reset_gpio, GPIO_OUTPUT_INACTIVE);
+		if (ret) {
+			return ret;
+		}
+	}
+#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios) */
+
+	/* Reset PHY */
+	ret = phy_ti_dp83867_reset(dev);
+	if (ret) {
+		LOG_ERR("Failed to reset phy (%d)", config->addr);
+		return ret;
+	}
+
+	k_work_init_delayable(&data->phy_monitor_work, phy_ti_dp83867_monitor_work_handler);
+
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
+	if (!config->interrupt_gpio.port) {
+		goto skip_int_gpio;
+	}
+
+	/* Configure interrupt pin */
+	ret = gpio_pin_configure_dt(&config->interrupt_gpio, GPIO_INPUT);
+	if (ret < 0) {
+		return ret;
+	}
+
+	gpio_init_callback(&data->gpio_callback, phy_ti_dp83867_interrupt_handler,
+			   BIT(config->interrupt_gpio.pin));
+	ret = gpio_add_callback_dt(&config->interrupt_gpio, &data->gpio_callback);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = gpio_pin_interrupt_configure_dt(&config->interrupt_gpio, GPIO_INT_EDGE_TO_ACTIVE);
+
+	return ret;
+
+skip_int_gpio:
+#endif /* DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) */
+	phy_ti_dp83867_monitor_work_handler(&data->phy_monitor_work.work);
+
+	return 0;
+}
+
+static DEVICE_API(ethphy, ti_dp83867_phy_api) = {
+	.get_link = phy_ti_dp83867_get_link,
+	.cfg_link = phy_ti_dp83867_cfg_link,
+	.link_cb_set = phy_ti_dp83867_link_cb_set,
+	.read = phy_ti_dp83867_read,
+	.write = phy_ti_dp83867_write,
+};
+
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios)
+#define RESET_GPIO(n) .reset_gpio = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {0}),
+#else
+#define RESET_GPIO(n)
+#endif /* reset gpio */
+
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios)
+#define INTERRUPT_GPIO(n) .interrupt_gpio = GPIO_DT_SPEC_INST_GET_OR(n, int_gpios, {0}),
+#else
+#define INTERRUPT_GPIO(n)
+#endif /* interrupt gpio */
+
+#define TI_DP83867_INIT(n)                                                                         \
+	static const struct ti_dp83867_config ti_dp83867_##n##_config = {                          \
+		.addr = DT_INST_REG_ADDR(n),                                                       \
+		.mdio_dev = DEVICE_DT_GET(DT_INST_PARENT(n)),                                      \
+		RESET_GPIO(n) INTERRUPT_GPIO(n)};                                                  \
+                                                                                                   \
+	static struct ti_dp83867_data ti_dp83867_##n##_data;                                       \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, &phy_ti_dp83867_init, NULL, &ti_dp83867_##n##_data,               \
+			      &ti_dp83867_##n##_config, POST_KERNEL, CONFIG_PHY_INIT_PRIORITY,     \
+			      &ti_dp83867_phy_api);
+
+DT_INST_FOREACH_STATUS_OKAY(TI_DP83867_INIT)
diff --git a/drivers/firmware/scmi/CMakeLists.txt b/drivers/firmware/scmi/CMakeLists.txt
index 68e4c7a787c..60ea86a5cb6 100644
--- a/drivers/firmware/scmi/CMakeLists.txt
+++ b/drivers/firmware/scmi/CMakeLists.txt
@@ -10,3 +10,6 @@ zephyr_library_sources_ifdef(CONFIG_ARM_SCMI_SHMEM shmem.c)
 # SCMI protocol helper files
 zephyr_library_sources_ifdef(CONFIG_ARM_SCMI_CLK_HELPERS clk.c)
 zephyr_library_sources_ifdef(CONFIG_ARM_SCMI_PINCTRL_HELPERS pinctrl.c)
+zephyr_library_sources_ifdef(CONFIG_ARM_SCMI_POWER_DOMAIN_HELPERS power.c)
+
+add_subdirectory_ifdef(CONFIG_ARM_SCMI nxp)
diff --git a/drivers/firmware/scmi/Kconfig b/drivers/firmware/scmi/Kconfig
index 1b4415452e6..c4beec1d2b4 100644
--- a/drivers/firmware/scmi/Kconfig
+++ b/drivers/firmware/scmi/Kconfig
@@ -28,6 +28,13 @@ config ARM_SCMI_PINCTRL_HELPERS
 	help
 	  Enable support for SCMI pinctrl protocol helper functions.
 
+config ARM_SCMI_POWER_DOMAIN_HELPERS
+	bool "Helper functions for SCMI power domain protocol"
+	default y
+	depends on DT_HAS_ARM_SCMI_POWER_ENABLED
+	help
+	  Enable support for SCMI power domain protocol helper functions.
+
 config ARM_SCMI_SHMEM
 	bool "SCMI shared memory (SHMEM) driver"
 	default y
@@ -57,4 +64,6 @@ config ARM_SCMI_TRANSPORT_INIT_PRIORITY
 	help
 	  SCMI transport driver device initialization priority.
 
+source "drivers/firmware/scmi/nxp/Kconfig"
+
 endif # ARM_SCMI
diff --git a/drivers/firmware/scmi/clk.c b/drivers/firmware/scmi/clk.c
index 415349586ee..1abd04f1c49 100644
--- a/drivers/firmware/scmi/clk.c
+++ b/drivers/firmware/scmi/clk.c
@@ -22,6 +22,16 @@ struct scmi_clock_rate_set_reply {
 	uint32_t rate[2];
 };
 
+struct scmi_clock_parent_get_reply {
+	int32_t status;
+	uint32_t parent_id;
+};
+
+struct scmi_clock_parent_config {
+	uint32_t clk_id;
+	uint32_t parent_id;
+};
+
 int scmi_clock_rate_get(struct scmi_protocol *proto,
 			uint32_t clk_id, uint32_t *rate)
 {
@@ -61,6 +71,119 @@ int scmi_clock_rate_get(struct scmi_protocol *proto,
 	return 0;
 }
 
+int scmi_clock_rate_set(struct scmi_protocol *proto, struct scmi_clock_rate_config *cfg)
+{
+	struct scmi_message msg, reply;
+	int status, ret;
+
+	/* sanity checks */
+	if (!proto || !cfg) {
+		return -EINVAL;
+	}
+
+	if (proto->id != SCMI_PROTOCOL_CLOCK) {
+		return -EINVAL;
+	}
+
+	/* Currently ASYNC flag is not supported. */
+	if (cfg->flags & SCMI_CLK_RATE_SET_FLAGS_ASYNC) {
+		return -ENOTSUP;
+	}
+
+	msg.hdr = SCMI_MESSAGE_HDR_MAKE(SCMI_CLK_MSG_CLOCK_RATE_SET, SCMI_COMMAND, proto->id, 0x0);
+	msg.len = sizeof(*cfg);
+	msg.content = cfg;
+
+	reply.hdr = msg.hdr;
+	reply.len = sizeof(status);
+	reply.content = &status;
+
+	ret = scmi_send_message(proto, &msg, &reply);
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (status != SCMI_SUCCESS) {
+		return scmi_status_to_errno(status);
+	}
+
+	return 0;
+}
+
+int scmi_clock_parent_get(struct scmi_protocol *proto, uint32_t clk_id, uint32_t *parent_id)
+{
+	struct scmi_message msg, reply;
+	int ret;
+	struct scmi_clock_parent_get_reply reply_buffer;
+
+	/* sanity checks */
+	if (!proto || !parent_id) {
+		return -EINVAL;
+	}
+
+	if (proto->id != SCMI_PROTOCOL_CLOCK) {
+		return -EINVAL;
+	}
+
+	msg.hdr =
+		SCMI_MESSAGE_HDR_MAKE(SCMI_CLK_MSG_CLOCK_PARENT_GET, SCMI_COMMAND, proto->id, 0x0);
+	msg.len = sizeof(clk_id);
+	msg.content = &clk_id;
+
+	reply.hdr = msg.hdr;
+	reply.len = sizeof(reply_buffer);
+	reply.content = &reply_buffer;
+
+	ret = scmi_send_message(proto, &msg, &reply);
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (reply_buffer.status != SCMI_SUCCESS) {
+		return scmi_status_to_errno(reply_buffer.status);
+	}
+
+	*parent_id = reply_buffer.parent_id;
+
+	return 0;
+}
+
+int scmi_clock_parent_set(struct scmi_protocol *proto, uint32_t clk_id, uint32_t parent_id)
+{
+	struct scmi_clock_parent_config cfg = {.clk_id = clk_id, .parent_id = parent_id};
+	struct scmi_message msg, reply;
+	int status, ret;
+
+	/* sanity checks */
+	if (!proto) {
+		return -EINVAL;
+	}
+
+	if (proto->id != SCMI_PROTOCOL_CLOCK) {
+		return -EINVAL;
+	}
+
+	msg.hdr =
+		SCMI_MESSAGE_HDR_MAKE(SCMI_CLK_MSG_CLOCK_PARENT_SET, SCMI_COMMAND, proto->id, 0x0);
+	msg.len = sizeof(cfg);
+	msg.content = &cfg;
+
+	reply.hdr = msg.hdr;
+	reply.len = sizeof(status);
+	reply.content = &status;
+
+	ret = scmi_send_message(proto, &msg, &reply);
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (status != SCMI_SUCCESS) {
+		return scmi_status_to_errno(status);
+	}
+
+	return 0;
+}
+
 int scmi_clock_config_set(struct scmi_protocol *proto,
 			  struct scmi_clock_config *cfg)
 {
diff --git a/drivers/firmware/scmi/nxp/CMakeLists.txt b/drivers/firmware/scmi/nxp/CMakeLists.txt
new file mode 100644
index 00000000000..3d8db1e5472
--- /dev/null
+++ b/drivers/firmware/scmi/nxp/CMakeLists.txt
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+zephyr_library_sources_ifdef(CONFIG_ARM_SCMI_NXP_VENDOR_EXTENSIONS shmem.c)
+zephyr_library_sources_ifdef(CONFIG_NXP_SCMI_CPU_DOMAIN_HELPERS cpu.c)
diff --git a/drivers/firmware/scmi/nxp/Kconfig b/drivers/firmware/scmi/nxp/Kconfig
new file mode 100644
index 00000000000..458db539352
--- /dev/null
+++ b/drivers/firmware/scmi/nxp/Kconfig
@@ -0,0 +1,19 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config ARM_SCMI_NXP_VENDOR_EXTENSIONS
+	bool "Allow NXP specific SCMI features"
+	select CRC
+	help
+	  When enabled, additional SCMI features specific to NXP will be available
+
+if ARM_SCMI_NXP_VENDOR_EXTENSIONS
+
+config NXP_SCMI_CPU_DOMAIN_HELPERS
+	bool "Helper functions for SCMI cpu domain protocol"
+	default y
+	depends on DT_HAS_NXP_SCMI_CPU_ENABLED
+	help
+	  Enable support for SCMI cpu domain protocol helper functions.
+
+endif # ARM_SCMI_NXP_VENDOR_EXTENSIONS
diff --git a/drivers/firmware/scmi/nxp/cpu.c b/drivers/firmware/scmi/nxp/cpu.c
new file mode 100644
index 00000000000..6c3aaa09822
--- /dev/null
+++ b/drivers/firmware/scmi/nxp/cpu.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include <zephyr/drivers/firmware/scmi/nxp/cpu.h>
+
+DT_SCMI_PROTOCOL_DEFINE_NODEV(DT_INST(0, nxp_scmi_cpu), NULL);
+
+int scmi_cpu_sleep_mode_set(struct scmi_cpu_sleep_mode_config *cfg)
+{
+	struct scmi_protocol *proto = &SCMI_PROTOCOL_NAME(SCMI_PROTOCOL_CPU_DOMAIN);
+	struct scmi_message msg, reply;
+	int status, ret;
+
+	/* sanity checks */
+	if (!proto || !cfg) {
+		return -EINVAL;
+	}
+
+	if (proto->id != SCMI_PROTOCOL_CPU_DOMAIN) {
+		return -EINVAL;
+	}
+
+	msg.hdr = SCMI_MESSAGE_HDR_MAKE(SCMI_CPU_DOMAIN_MSG_CPU_SLEEP_MODE_SET, SCMI_COMMAND,
+					proto->id, 0x0);
+	msg.len = sizeof(*cfg);
+	msg.content = cfg;
+
+	reply.hdr = msg.hdr;
+	reply.len = sizeof(status);
+	reply.content = &status;
+
+	ret = scmi_send_message(proto, &msg, &reply);
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (status != SCMI_SUCCESS) {
+		return scmi_status_to_errno(status);
+	}
+
+	return 0;
+}
diff --git a/drivers/firmware/scmi/nxp/shmem.c b/drivers/firmware/scmi/nxp/shmem.c
new file mode 100644
index 00000000000..629076a2e6d
--- /dev/null
+++ b/drivers/firmware/scmi/nxp/shmem.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/firmware/scmi/shmem.h>
+#include <zephyr/sys/crc.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(arm_scmi_shmem_nxp);
+
+#define SMT_CRC_NONE  0U
+#define SMT_CRC_XOR   1U /* Unsupported */
+#define SMT_CRC_J1850 2U /* Unsupported */
+#define SMT_CRC_CRC32 3U
+
+int scmi_shmem_vendor_read_message(const struct scmi_shmem_layout *layout)
+{
+	uint32_t validation_type = layout->res1[0];
+
+	if (validation_type == SMT_CRC_CRC32) {
+		if (layout->res1[1] != crc32_ieee((const uint8_t *)&layout->msg_hdr, layout->len)) {
+			LOG_ERR("bad message crc");
+			return -EBADMSG;
+		}
+	} else if (validation_type == SMT_CRC_NONE) {
+		/* do nothing */
+	} else {
+		LOG_ERR("unsupported validation type 0x%x", validation_type);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int scmi_shmem_vendor_write_message(struct scmi_shmem_layout *layout)
+{
+	uint32_t validation_type = layout->res1[0];
+
+	if (validation_type == SMT_CRC_CRC32) {
+		layout->res1[1] = crc32_ieee((const uint8_t *)&layout->msg_hdr, layout->len);
+	} else if (validation_type == SMT_CRC_NONE) {
+		/* do nothing */
+	} else {
+		LOG_ERR("unsupported validation type 0x%x", validation_type);
+		return -EINVAL;
+	}
+
+	return 0;
+}
diff --git a/drivers/firmware/scmi/power.c b/drivers/firmware/scmi/power.c
new file mode 100644
index 00000000000..e2c639a03fc
--- /dev/null
+++ b/drivers/firmware/scmi/power.c
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/firmware/scmi/power.h>
+#include <string.h>
+
+DT_SCMI_PROTOCOL_DEFINE_NODEV(DT_INST(0, arm_scmi_power), NULL);
+
+struct scmi_power_state_get_reply {
+	int32_t status;
+	uint32_t power_state;
+};
+
+int scmi_power_state_get(uint32_t domain_id, uint32_t *power_state)
+{
+	struct scmi_protocol *proto = &SCMI_PROTOCOL_NAME(SCMI_PROTOCOL_POWER_DOMAIN);
+	struct scmi_power_state_get_reply reply_buffer;
+	struct scmi_message msg, reply;
+	int ret;
+
+	/* sanity checks */
+	if (!proto || !power_state) {
+		return -EINVAL;
+	}
+
+	if (proto->id != SCMI_PROTOCOL_POWER_DOMAIN) {
+		return -EINVAL;
+	}
+
+	msg.hdr = SCMI_MESSAGE_HDR_MAKE(SCMI_POWER_DOMAIN_MSG_POWER_STATE_GET, SCMI_COMMAND,
+					proto->id, 0x0);
+	msg.len = sizeof(domain_id);
+	msg.content = &domain_id;
+
+	reply.hdr = msg.hdr;
+	reply.len = sizeof(reply_buffer);
+	reply.content = &reply_buffer;
+
+	ret = scmi_send_message(proto, &msg, &reply);
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (reply_buffer.status != SCMI_SUCCESS) {
+		return scmi_status_to_errno(reply_buffer.status);
+	}
+
+	*power_state = reply_buffer.power_state;
+
+	return 0;
+}
+
+int scmi_power_state_set(struct scmi_power_state_config *cfg)
+{
+	struct scmi_protocol *proto = &SCMI_PROTOCOL_NAME(SCMI_PROTOCOL_POWER_DOMAIN);
+	struct scmi_message msg, reply;
+	int status, ret;
+
+	/* sanity checks */
+	if (!proto || !cfg) {
+		return -EINVAL;
+	}
+
+	if (proto->id != SCMI_PROTOCOL_POWER_DOMAIN) {
+		return -EINVAL;
+	}
+
+	/* Currently ASYNC flag is not supported. */
+	if (cfg->flags & SCMI_POWER_STATE_SET_FLAGS_ASYNC) {
+		return -ENOTSUP;
+	}
+
+	msg.hdr = SCMI_MESSAGE_HDR_MAKE(SCMI_POWER_DOMAIN_MSG_POWER_STATE_SET, SCMI_COMMAND,
+					proto->id, 0x0);
+	msg.len = sizeof(*cfg);
+	msg.content = cfg;
+
+	reply.hdr = msg.hdr;
+	reply.len = sizeof(status);
+	reply.content = &status;
+
+	ret = scmi_send_message(proto, &msg, &reply);
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (status != SCMI_SUCCESS) {
+		return scmi_status_to_errno(status);
+	}
+
+	return 0;
+}
diff --git a/drivers/firmware/scmi/shmem.c b/drivers/firmware/scmi/shmem.c
index 6ec645cbc30..86b1a9659d4 100644
--- a/drivers/firmware/scmi/shmem.c
+++ b/drivers/firmware/scmi/shmem.c
@@ -26,15 +26,6 @@ struct scmi_shmem_data {
 	mm_reg_t regmap;
 };
 
-struct scmi_shmem_layout {
-	volatile uint32_t res0;
-	volatile uint32_t chan_status;
-	volatile uint32_t res1[2];
-	volatile uint32_t chan_flags;
-	volatile uint32_t len;
-	volatile uint32_t msg_hdr;
-};
-
 int scmi_shmem_get_channel_status(const struct device *dev, uint32_t *status)
 {
 	struct scmi_shmem_data *data;
@@ -57,6 +48,16 @@ static void scmi_shmem_memcpy(mm_reg_t dst, mm_reg_t src, uint32_t bytes)
 	}
 }
 
+__weak int scmi_shmem_vendor_read_message(const struct scmi_shmem_layout *layout)
+{
+	return 0;
+}
+
+__weak int scmi_shmem_vendor_write_message(struct scmi_shmem_layout *layout)
+{
+	return 0;
+}
+
 int scmi_shmem_read_message(const struct device *shmem, struct scmi_message *msg)
 {
 	struct scmi_shmem_layout *layout;
@@ -96,6 +97,11 @@ int scmi_shmem_read_message(const struct device *shmem, struct scmi_message *msg
 		return -EINVAL;
 	}
 
+	if (scmi_shmem_vendor_read_message(layout) < 0) {
+		LOG_ERR("vendor specific validation failed");
+		return -EINVAL;
+	}
+
 	if (msg->content) {
 		scmi_shmem_memcpy(POINTER_TO_UINT(msg->content),
 				  data->regmap + sizeof(*layout), msg->len);
@@ -139,6 +145,10 @@ int scmi_shmem_write_message(const struct device *shmem, struct scmi_message *ms
 				  POINTER_TO_UINT(msg->content), msg->len);
 	}
 
+	if (scmi_shmem_vendor_write_message(layout) < 0) {
+		return -EINVAL;
+	}
+
 	/* done, mark channel as busy and proceed */
 	layout->chan_status &= ~SCMI_SHMEM_CHAN_STATUS_BUSY_BIT;
 
diff --git a/drivers/flash/CMakeLists.txt b/drivers/flash/CMakeLists.txt
index d3bbf7ee2ff..089259a2572 100644
--- a/drivers/flash/CMakeLists.txt
+++ b/drivers/flash/CMakeLists.txt
@@ -44,6 +44,7 @@ zephyr_library_sources_ifdef(CONFIG_FLASH_STM32_XSPI flash_stm32_xspi.c)
 zephyr_library_sources_ifdef(CONFIG_INFINEON_CAT1_QSPI_FLASH flash_ifx_cat1_qspi.c)
 zephyr_library_sources_ifdef(CONFIG_NORDIC_QSPI_NOR nrf_qspi_nor.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_CC13XX_CC26XX soc_flash_cc13xx_cc26xx.c)
+zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_CC23X0 soc_flash_cc23x0.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_ESP32 flash_esp32.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_GECKO flash_gecko.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_ITE_IT8XXX2 flash_ite_it8xxx2.c)
@@ -60,6 +61,8 @@ zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_RV32M1 soc_flash_rv32m1.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_SAM flash_sam.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_SAM0 flash_sam0.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_SI32 flash_si32.c)
+zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_SILABS_S2 soc_flash_silabs_series2.c)
+zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_SILABS_SIWX91X soc_flash_silabs_siwx91x.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_SMARTBOND flash_smartbond.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_TELINK_B91 soc_flash_b91.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_FLASH_XMC4XXX soc_flash_xmc4xxx.c)
@@ -150,10 +153,11 @@ zephyr_library_include_directories_ifdef(
 )
 
 zephyr_library_sources_ifdef(CONFIG_FLASH_NXP_S32_QSPI_NOR flash_nxp_s32_qspi_nor.c)
-zephyr_library_include_directories_ifdef(
-  CONFIG_FLASH_NXP_S32_QSPI_NOR
-  ${ZEPHYR_BASE}/drivers/memc
-)
+zephyr_library_sources_ifdef(CONFIG_FLASH_NXP_S32_QSPI_HYPERFLASH flash_nxp_s32_qspi_hyperflash.c)
+if(CONFIG_FLASH_NXP_S32_QSPI_NOR OR CONFIG_FLASH_NXP_S32_QSPI_HYPERFLASH)
+  zephyr_library_sources(flash_nxp_s32_qspi.c)
+  zephyr_library_include_directories(${ZEPHYR_BASE}/drivers/memc)
+endif()
 
 if(CONFIG_RA_FLASH_HP)
   zephyr_library_sources(flash_hp_ra.c)
diff --git a/drivers/flash/Kconfig b/drivers/flash/Kconfig
index bc9f6e69d7e..bdd84f25814 100644
--- a/drivers/flash/Kconfig
+++ b/drivers/flash/Kconfig
@@ -171,6 +171,7 @@ source "drivers/flash/Kconfig.b91"
 source "drivers/flash/Kconfig.cadence_nand"
 source "drivers/flash/Kconfig.cadence_qspi_nor"
 source "drivers/flash/Kconfig.cc13xx_cc26xx"
+source "drivers/flash/Kconfig.cc23x0"
 source "drivers/flash/Kconfig.esp32"
 source "drivers/flash/Kconfig.gd32"
 source "drivers/flash/Kconfig.gecko"
@@ -196,7 +197,9 @@ source "drivers/flash/Kconfig.rv32m1"
 source "drivers/flash/Kconfig.sam"
 source "drivers/flash/Kconfig.sam0"
 source "drivers/flash/Kconfig.si32"
+source "drivers/flash/Kconfig.silabs"
 source "drivers/flash/Kconfig.simulator"
+source "drivers/flash/Kconfig.siwx91x"
 source "drivers/flash/Kconfig.smartbond"
 source "drivers/flash/Kconfig.stm32"
 source "drivers/flash/Kconfig.stm32_ospi"
diff --git a/drivers/flash/Kconfig.cc23x0 b/drivers/flash/Kconfig.cc23x0
new file mode 100644
index 00000000000..0a719009144
--- /dev/null
+++ b/drivers/flash/Kconfig.cc23x0
@@ -0,0 +1,14 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+# Copyright (c) 2024 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FLASH_CC23X0
+	bool "TI SimpleLink CC23x0 flash controller driver"
+	default y
+	depends on DT_HAS_TI_CC23X0_FLASH_CONTROLLER_ENABLED
+	select FLASH_HAS_PAGE_LAYOUT
+	select FLASH_HAS_DRIVER_ENABLED
+	select MPU_ALLOW_FLASH_WRITE if ARM_MPU
+	help
+	  Enables TI SimpleLink CC23x0 flash controller driver.
diff --git a/drivers/flash/Kconfig.it8xxx2 b/drivers/flash/Kconfig.it8xxx2
index ef0307f65a3..9c7252cac3a 100644
--- a/drivers/flash/Kconfig.it8xxx2
+++ b/drivers/flash/Kconfig.it8xxx2
@@ -7,7 +7,8 @@ config SOC_FLASH_ITE_IT8XXX2
 	bool "ITE IT8XXX2 flash driver"
 	default y
 	depends on DT_HAS_ITE_IT8XXX2_FLASH_CONTROLLER_ENABLED
-	select SOC_IT8XXX2_USE_ILM
+	select SOC_IT51XXX_USE_ILM if SOC_SERIES_IT51XXX
+	select SOC_IT8XXX2_USE_ILM if SOC_SERIES_IT8XXX2
 	select FLASH_HAS_PAGE_LAYOUT
 	select FLASH_HAS_DRIVER_ENABLED
 	select FLASH_HAS_EXPLICIT_ERASE
diff --git a/drivers/flash/Kconfig.nor b/drivers/flash/Kconfig.nor
index 8e395fa5a0c..ecf7a4e176a 100644
--- a/drivers/flash/Kconfig.nor
+++ b/drivers/flash/Kconfig.nor
@@ -68,6 +68,15 @@ config SPI_NOR_SLEEP_WHILE_WAITING_UNTIL_READY
 	  result in significant flash savings if this driver is the only user
 	  of "k_sleep". This can be the case when building as a bootloader.
 
+config SPI_NOR_SLEEP_ERASE_MS
+	int "Delay between polls while waiting for an erase operation in ms"
+	default 50
+	depends on SPI_NOR_SLEEP_WHILE_WAITING_UNTIL_READY
+	help
+	  The delay between polling while waiting for the flash to finish
+	  an erase operation.
+
+
 config SPI_NOR_FLASH_LAYOUT_PAGE_SIZE
 	int "Page size to use for FLASH_LAYOUT feature"
 	default 65536
diff --git a/drivers/flash/Kconfig.npcx_fiu b/drivers/flash/Kconfig.npcx_fiu
index 3ddf9a2b7e5..1137b1ad1ab 100644
--- a/drivers/flash/Kconfig.npcx_fiu
+++ b/drivers/flash/Kconfig.npcx_fiu
@@ -65,4 +65,12 @@ config FLASH_NPCX_FIU_SUPP_DRA_2_DEV
 	  Selected if NPCX series supports two external SPI devices in Direct
 	  Read Access (DRA) on QSPI bus.
 
+DT_NPCX_FIU_LOW_DEV_SWAP := $(dt_nodelabel_bool_prop,qspi_fiu1,flash-dev-inv)
+config FLASH_NPCX_FIU_SUPP_LOW_DEV_SWAP
+	bool "Inverse the access of the two external flashes"
+	default y if SOC_SERIES_NPCX4 && FLASH_NPCX_FIU_SUPP_DRA_2_DEV && \
+		     "$(DT_NPCX_FIU_LOW_DEV_SWAP)"
+	help
+	  Select if it needs to swap the access of the two external flashes.
+
 endif #FLASH_NPCX_FIU_QSPI
diff --git a/drivers/flash/Kconfig.nrf b/drivers/flash/Kconfig.nrf
index 6e29ef952ca..39800a0627e 100644
--- a/drivers/flash/Kconfig.nrf
+++ b/drivers/flash/Kconfig.nrf
@@ -7,6 +7,13 @@ config FLASH_NRF_FORCE_ALT
 	  This option can be enabled to force an alternative implementation
 	  of the flash driver.
 
+config SOC_FLASH_NRF_CUSTOM_CONTEXT
+	bool "Nordic nRFx flash driver operation custom context"
+	depends on SOC_COMPATIBLE_NRF
+	help
+	  Enable pointer to custom context, for drivers that need to store additional data,
+	  not covered by the structure.
+
 menuconfig SOC_FLASH_NRF
 	bool "Nordic Semiconductor nRF flash driver"
 	default y
diff --git a/drivers/flash/Kconfig.nxp_s32 b/drivers/flash/Kconfig.nxp_s32
index 47db1ab654e..08cc11a6a86 100644
--- a/drivers/flash/Kconfig.nxp_s32
+++ b/drivers/flash/Kconfig.nxp_s32
@@ -1,4 +1,4 @@
-# Copyright 2023 NXP
+# Copyright 2023-2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 config FLASH_NXP_S32_QSPI_NOR
@@ -14,10 +14,23 @@ config FLASH_NXP_S32_QSPI_NOR
 	  Enable the Flash driver for a NOR Serial Flash Memory device connected
 	  to an NXP S32 QSPI bus.
 
-if FLASH_NXP_S32_QSPI_NOR
+config FLASH_NXP_S32_QSPI_HYPERFLASH
+	bool "NXP S32 QSPI HYPERFLASH driver"
+	default y
+	depends on DT_HAS_NXP_S32_QSPI_HYPERFLASH_ENABLED
+	select MEMC
+	select FLASH_HAS_PAGE_LAYOUT
+	select FLASH_HAS_DRIVER_ENABLED
+	select FLASH_HAS_EXPLICIT_ERASE
+	help
+	  Enable the Flash driver for a HyperFlash Memory device connected
+	  to an NXP S32 QSPI bus.
+
+if FLASH_NXP_S32_QSPI_NOR || FLASH_NXP_S32_QSPI_HYPERFLASH
 
-config FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME
+config FLASH_NXP_S32_QSPI_SFDP_RUNTIME
 	bool "Read flash parameters at runtime"
+	depends on FLASH_NXP_S32_QSPI_NOR
 	help
 	  Read flash device characteristics from the device at runtime.
 	  This option should provide functionality for all supported
@@ -52,4 +65,4 @@ config FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE
 	  flash memory. Other options may include the 32K-byte erase size (32768),
 	  the block size (65536), or any non-zero multiple of the sector size.
 
-endif # FLASH_NXP_S32_QSPI_NOR
+endif # FLASH_NXP_S32_QSPI_NOR || FLASH_NXP_S32_QSPI_HYPERFLASH
diff --git a/drivers/flash/Kconfig.silabs b/drivers/flash/Kconfig.silabs
new file mode 100644
index 00000000000..5890f98ed34
--- /dev/null
+++ b/drivers/flash/Kconfig.silabs
@@ -0,0 +1,27 @@
+# Copyright (c) 2025 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FLASH_SILABS_S2
+	bool "Silicon Labs Series 2 flash driver"
+	default y
+	depends on DT_HAS_SILABS_SERIES2_FLASH_CONTROLLER_ENABLED
+	select FLASH_HAS_DRIVER_ENABLED
+	select FLASH_HAS_PAGE_LAYOUT
+	select SOC_GECKO_MSC
+	select FLASH_HAS_EXPLICIT_ERASE
+	select MPU_ALLOW_FLASH_WRITE if ARM_MPU
+	help
+	  Enable Silicon Labs Series 2 internal flash driver.
+
+if SOC_FLASH_SILABS_S2
+
+config SOC_FLASH_SILABS_S2_DMA_WRITE
+	bool "Use DMA for flash write operations"
+	depends on DMA
+	default y if $(dt_compat_any_has_prop,$(DT_COMPAT_SILABS_SERIES2_FLASH_CONTROLLER),dmas)
+
+config SOC_FLASH_SILABS_S2_DMA_READ
+	bool "Use DMA for flash read operations"
+	depends on DMA
+
+endif
diff --git a/drivers/flash/Kconfig.siwx91x b/drivers/flash/Kconfig.siwx91x
new file mode 100644
index 00000000000..ec7e7af209b
--- /dev/null
+++ b/drivers/flash/Kconfig.siwx91x
@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FLASH_SILABS_SIWX91X
+	bool "Silicon Labs SiWx91x flash driver"
+	default y
+	depends on DT_HAS_SILABS_SIWX91X_FLASH_CONTROLLER_ENABLED
+	select FLASH_HAS_DRIVER_ENABLED
+	select FLASH_HAS_EXPLICIT_ERASE
+	select FLASH_HAS_PAGE_LAYOUT
+	# Flash controller is handled by the network coprocessor
+	select WISECONNECT_NETWORK_STACK
+	help
+	  Enable flash controller for flash embedded on Silicon Labs SiWx91x
+	  chips.
diff --git a/drivers/flash/Kconfig.stm32 b/drivers/flash/Kconfig.stm32
index cfd3f5df17c..c7c9bb1e00c 100644
--- a/drivers/flash/Kconfig.stm32
+++ b/drivers/flash/Kconfig.stm32
@@ -33,7 +33,7 @@ if SOC_FLASH_STM32
 
 config FLASH_STM32_WRITE_PROTECT
 	bool "Extended operation for flash write protection control"
-	depends on SOC_SERIES_STM32F4X
+	depends on SOC_SERIES_STM32F4X || SOC_SERIES_STM32H7X
 	select FLASH_HAS_EX_OP
 	default n
 	help
diff --git a/drivers/flash/Kconfig.stm32_ospi b/drivers/flash/Kconfig.stm32_ospi
index 91a30c8cc0a..4b62bdcd23e 100644
--- a/drivers/flash/Kconfig.stm32_ospi
+++ b/drivers/flash/Kconfig.stm32_ospi
@@ -3,8 +3,7 @@
 # Copyright (c) 2022 STMicroelectronics
 # SPDX-License-Identifier: Apache-2.0
 
-DT_STM32_OCTOSPI_1_HAS_DMA := $(dt_nodelabel_has_prop,octospi1,dmas)
-DT_STM32_OCTOSPI_2_HAS_DMA := $(dt_nodelabel_has_prop,octospi2,dmas)
+DT_STM32_OCTOSPI_HAS_DMA := $(dt_compat_any_has_prop,$(DT_COMPAT_ST_STM32_OSPI),dmas)
 
 config FLASH_STM32_OSPI
 	bool "STM32 Octo SPI Flash driver"
@@ -19,11 +18,9 @@ config FLASH_STM32_OSPI
 	select FLASH_HAS_PAGE_LAYOUT
 	select FLASH_HAS_EXPLICIT_ERASE
 	select PINCTRL
-	select DMA if $(DT_STM32_OCTOSPI_1_HAS_DMA) || $(DT_STM32_OCTOSPI_2_HAS_DMA)
-	select USE_STM32_HAL_DMA if $(DT_STM32_OCTOSPI_1_HAS_DMA) || \
-					$(DT_STM32_OCTOSPI_2_HAS_DMA)
+	select DMA if $(DT_STM32_OCTOSPI_HAS_DMA)
+	select USE_STM32_HAL_DMA if $(DT_STM32_OCTOSPI_HAS_DMA)
 	select USE_STM32_HAL_DMA_EX if SOC_SERIES_STM32U5X && \
-					($(DT_STM32_OCTOSPI_1_HAS_DMA) || \
-					 $(DT_STM32_OCTOSPI_2_HAS_DMA))
+					$(DT_STM32_OCTOSPI_HAS_DMA)
 	help
 	  Enable OSPI-NOR support on the STM32 family of processors.
diff --git a/drivers/flash/Kconfig.stm32_qspi b/drivers/flash/Kconfig.stm32_qspi
index 976083238b1..aa174bfd21e 100644
--- a/drivers/flash/Kconfig.stm32_qspi
+++ b/drivers/flash/Kconfig.stm32_qspi
@@ -4,7 +4,7 @@
 # Copyright (c) 2020 Linaro Limited
 # SPDX-License-Identifier: Apache-2.0
 
-DT_STM32_QUADSPI_HAS_DMA := $(dt_nodelabel_has_prop,quadspi,dmas)
+DT_STM32_QUADSPI_HAS_DMA := $(dt_compat_any_has_prop,$(DT_COMPAT_ST_STM32_QSPI),dmas)
 
 config FLASH_STM32_QSPI
 	bool "STM32 Quad SPI Flash driver"
diff --git a/drivers/flash/Kconfig.stm32_xspi b/drivers/flash/Kconfig.stm32_xspi
index 39f62814b5c..53a3f381af5 100644
--- a/drivers/flash/Kconfig.stm32_xspi
+++ b/drivers/flash/Kconfig.stm32_xspi
@@ -3,8 +3,7 @@
 # Copyright (c) 2024 STMicroelectronics
 # SPDX-License-Identifier: Apache-2.0
 
-DT_STM32_XSPI_1_HAS_DMA := $(dt_nodelabel_has_prop,xspi1,dmas)
-DT_STM32_XSPI_2_HAS_DMA := $(dt_nodelabel_has_prop,xspi2,dmas)
+DT_STM32_XSPI_HAS_DMA := $(dt_compat_any_has_prop,$(DT_COMPAT_ST_STM32_XSPI),dmas)
 
 config FLASH_STM32_XSPI
 	bool "STM32 XSPI Flash driver"
@@ -17,11 +16,9 @@ config FLASH_STM32_XSPI
 	select FLASH_PAGE_LAYOUT
 	select FLASH_HAS_PAGE_LAYOUT
 	select PINCTRL
-	select DMA if $(DT_STM32_XSPI_1_HAS_DMA) || $(DT_STM32_XSPI_2_HAS_DMA)
-	select USE_STM32_HAL_DMA if $(DT_STM32_XSPI_1_HAS_DMA) || \
-					$(DT_STM32_XSPI_2_HAS_DMA)
+	select DMA if $(DT_STM32_XSPI_HAS_DMA)
+	select USE_STM32_HAL_DMA if $(DT_STM32_XSPI_HAS_DMA)
 	select USE_STM32_HAL_DMA_EX if SOC_SERIES_STM32H5X && \
-					($(DT_STM32_XSPI_1_HAS_DMA) || \
-					 $(DT_STM32_XSPI_2_HAS_DMA))
+					$(DT_STM32_XSPI_HAS_DMA)
 	help
 	  Enable XSPI-NOR support on the STM32 family of processors.
diff --git a/drivers/flash/flash_ambiq.c b/drivers/flash/flash_ambiq.c
index b7d805a65e8..d3998e3e200 100644
--- a/drivers/flash/flash_ambiq.c
+++ b/drivers/flash/flash_ambiq.c
@@ -11,7 +11,7 @@
 #include <zephyr/drivers/flash.h>
 #include <zephyr/logging/log.h>
 
-#include <am_mcu_apollo.h>
+#include <soc.h>
 
 LOG_MODULE_REGISTER(flash_ambiq, CONFIG_FLASH_LOG_LEVEL);
 
diff --git a/drivers/flash/flash_andes_qspi.c b/drivers/flash/flash_andes_qspi.c
index ff041e014f0..d7d58a73ad0 100644
--- a/drivers/flash/flash_andes_qspi.c
+++ b/drivers/flash/flash_andes_qspi.c
@@ -21,6 +21,9 @@
 
 LOG_MODULE_REGISTER(flash_andes, CONFIG_FLASH_LOG_LEVEL);
 
+/* ATCSPI200 transfer count is limited to 512 bytes. */
+#define MAX_TRANSFER_CNT (512)
+
 /* Indicates that an access command includes bytes for the address.
  * If not provided the opcode is not followed by address bytes.
  */
@@ -50,7 +53,7 @@ struct flash_andes_qspi_config {
 	uint32_t base;
 	uint32_t irq_num;
 	struct flash_parameters parameters;
-	bool xip;
+	bool qspi_cfg_rom;
 #if defined(CONFIG_FLASH_ANDES_QSPI_SFDP_DEVICETREE)
 	uint8_t jedec_id[SPI_NOR_MAX_ID_LEN];
 	uint32_t flash_size;
@@ -304,6 +307,8 @@ static int flash_andes_qspi_read(const struct device *dev,
 				 off_t addr, void *dest, size_t size)
 {
 	const size_t flash_size = dev_flash_size(dev);
+	size_t to_read = size;
+
 	int ret;
 
 	/* should be between 0 and flash size */
@@ -317,8 +322,23 @@ static int flash_andes_qspi_read(const struct device *dev,
 
 	acquire_device(dev);
 
-	ret = flash_andes_qspi_cmd_addr_read(dev,
-		FLASH_ANDES_CMD_4READ, addr, dest, size);
+	do {
+		/* Get the adequate size to receive */
+		to_read = MIN(MAX_TRANSFER_CNT, size);
+
+		ret = flash_andes_qspi_cmd_addr_read(dev,
+			FLASH_ANDES_CMD_4READ, addr, dest, to_read);
+
+		if (ret != 0) {
+			break;
+		}
+
+		size -= to_read;
+		dest = (uint8_t *)dest + to_read;
+		addr += to_read;
+
+		flash_andes_qspi_wait_until_ready(dev);
+	} while (size > 0);
 
 	release_device(dev);
 	return ret;
@@ -353,6 +373,8 @@ static int flash_andes_qspi_write(const struct device *dev, off_t addr,
 		/* Get the adequate size to send*/
 		to_write = MIN(page_size - (addr % page_size), size);
 
+		flash_andes_qspi_cmd_write(dev, FLASH_ANDES_CMD_WREN);
+
 		ret = flash_andes_qspi_cmd_addr_write(dev,
 			FLASH_ANDES_CMD_4PP, addr, src, to_write);
 
@@ -801,7 +823,7 @@ static int flash_andes_qspi_init(const struct device *dev)
 	uint8_t jedec_id[SPI_NOR_MAX_ID_LEN];
 
 	/* we should not configure the device we are running on */
-	if (config->xip) {
+	if (config->qspi_cfg_rom) {
 		return -EINVAL;
 	}
 
@@ -895,11 +917,21 @@ static DEVICE_API(flash, flash_andes_qspi_api) = {
 };
 
 #if (CONFIG_XIP)
-#define QSPI_ROM_CFG_XIP(node_id) DT_SAME_NODE(node_id, DT_CHOSEN(zephyr_flash))
+#define QSPI_FLASH_BASE DT_REG_ADDR_BY_IDX(DT_PARENT(DT_CHOSEN(zephyr_flash)), 1)
+#define QSPI_FLASH_SIZE DT_REG_SIZE_BY_IDX(DT_PARENT(DT_CHOSEN(zephyr_flash)), 1)
+#define QSPI_FLASH_END (QSPI_FLASH_BASE + QSPI_FLASH_SIZE)
+
+#if ((QSPI_FLASH_BASE <= CONFIG_FLASH_BASE_ADDRESS) && \
+	(CONFIG_FLASH_BASE_ADDRESS <= QSPI_FLASH_END))
+#define QSPI_CFG_ROM(node_id) DT_SAME_NODE(node_id, DT_CHOSEN(zephyr_flash))
 #else
-#define QSPI_ROM_CFG_XIP(node_id) false
+#define QSPI_CFG_ROM(node_id) false
 #endif
 
+#else /* CONFIG_XIP */
+#define QSPI_CFG_ROM(node_id) false
+#endif /* CONFIG_XIP */
+
 #define LAYOUT_PAGES_PROP(n)						\
 	IF_ENABLED(CONFIG_FLASH_PAGE_LAYOUT,				\
 		(.layout = {						\
@@ -940,7 +972,7 @@ static DEVICE_API(flash, flash_andes_qspi_api) = {
 				.write_block_size = 1,			\
 				.erase_value = 0xff			\
 			},						\
-			.xip = QSPI_ROM_CFG_XIP(DT_DRV_INST(n)),	\
+			.qspi_cfg_rom = QSPI_CFG_ROM(DT_DRV_INST(n)), \
 			ANDES_QSPI_SFDP_DEVICETREE_PROP(n)		\
 		};							\
 									\
diff --git a/drivers/flash/flash_esp32.c b/drivers/flash/flash_esp32.c
index 6d947064e9d..cb123a3349a 100644
--- a/drivers/flash/flash_esp32.c
+++ b/drivers/flash/flash_esp32.c
@@ -19,6 +19,7 @@
 #include <soc/spi_struct.h>
 #include <esp_flash_encrypt.h>
 #include <esp_flash_internal.h>
+#include <bootloader_flash_priv.h>
 
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
@@ -69,21 +70,89 @@ static inline void flash_esp32_sem_give(const struct device *dev)
 
 #endif /* CONFIG_MULTITHREADING */
 
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/util.h>
+#include <stdint.h>
+#include <string.h>
+
+#ifdef CONFIG_MCUBOOT
+#define READ_BUFFER_SIZE 32
+static bool flash_esp32_is_aligned(off_t address, void *buffer, size_t length)
+{
+	/* check if address, buffer pointer, and length are 4-byte aligned */
+	return ((address & 3) == 0) && (((uintptr_t)buffer & 3) == 0) && ((length & 3) == 0);
+}
+#endif
+
 static int flash_esp32_read(const struct device *dev, off_t address, void *buffer, size_t length)
 {
 	int ret = 0;
 
+#ifdef CONFIG_MCUBOOT
+	uint8_t *dest_ptr = (uint8_t *)buffer;
+	size_t remaining = length;
+	size_t copy_size = 0;
+	size_t aligned_size = 0;
+	bool allow_decrypt = esp_flash_encryption_enabled();
+
+	if (flash_esp32_is_aligned(address, buffer, length)) {
+		ret = esp_rom_flash_read(address, buffer, length, allow_decrypt);
+		return (ret == ESP_OK) ? 0 : -EIO;
+	}
+
+	/* handle unaligned reading */
+	uint8_t __aligned(4) temp_buf[READ_BUFFER_SIZE + 8];
+	while (remaining > 0) {
+		size_t addr_offset = address & 3;
+		size_t buf_offset = (uintptr_t)dest_ptr & 3;
+
+		copy_size = (remaining > READ_BUFFER_SIZE) ? READ_BUFFER_SIZE : remaining;
+
+		if (addr_offset == 0 && buf_offset == 0 && copy_size >= 4) {
+			aligned_size = copy_size & ~3;
+			ret = esp_rom_flash_read(address, dest_ptr, aligned_size, allow_decrypt);
+			if (ret != ESP_OK) {
+				return -EIO;
+			}
+
+			address += aligned_size;
+			dest_ptr += aligned_size;
+			remaining -= aligned_size;
+		} else {
+			size_t start_addr = address - addr_offset;
+
+			aligned_size = (copy_size + addr_offset + 3) & ~3;
+
+			ret = esp_rom_flash_read(start_addr, temp_buf, aligned_size, allow_decrypt);
+			if (ret != ESP_OK) {
+				return -EIO;
+			}
+
+			memcpy(dest_ptr, temp_buf + addr_offset, copy_size);
+
+			address += copy_size;
+			dest_ptr += copy_size;
+			remaining -= copy_size;
+		}
+	}
+#else
 	flash_esp32_sem_take(dev);
-	if (!esp_flash_encryption_enabled()) {
-		ret = esp_flash_read(NULL, buffer, address, length);
-	} else {
+
+	if (esp_flash_encryption_enabled()) {
 		ret = esp_flash_read_encrypted(NULL, address, buffer, length);
+	} else {
+		ret = esp_flash_read(NULL, buffer, address, length);
 	}
+
 	flash_esp32_sem_give(dev);
+#endif
+
 	if (ret != 0) {
-		LOG_ERR("esp_flash_read failed %d", ret);
+		LOG_ERR("Flash read error: %d", ret);
 		return -EIO;
 	}
+
 	return 0;
 }
 
@@ -94,28 +163,48 @@ static int flash_esp32_write(const struct device *dev,
 {
 	int ret = 0;
 
+#ifdef CONFIG_MCUBOOT
+	if (!flash_esp32_is_aligned(address, (void *)buffer, length)) {
+		LOG_ERR("Unaligned flash write is not supported");
+		return -EINVAL;
+	}
+
+	bool encrypt = esp_flash_encryption_enabled();
+
+	ret = esp_rom_flash_write(address, (void *)buffer, length, encrypt);
+#else
 	flash_esp32_sem_take(dev);
-	if (!esp_flash_encryption_enabled()) {
-		ret = esp_flash_write(NULL, buffer, address, length);
-	} else {
+
+	if (esp_flash_encryption_enabled()) {
 		ret = esp_flash_write_encrypted(NULL, address, buffer, length);
+	} else {
+		ret = esp_flash_write(NULL, buffer, address, length);
 	}
+
 	flash_esp32_sem_give(dev);
+#endif
 
 	if (ret != 0) {
-		LOG_ERR("esp_flash_write failed %d", ret);
+		LOG_ERR("Flash write error: %d", ret);
 		return -EIO;
 	}
+
 	return 0;
 }
 
 static int flash_esp32_erase(const struct device *dev, off_t start, size_t len)
 {
+	int ret = 0;
+
+#ifdef CONFIG_MCUBOOT
+	ret = esp_rom_flash_erase_range(start, len);
+#else
 	flash_esp32_sem_take(dev);
-	int ret = esp_flash_erase_region(NULL, start, len);
+	ret = esp_flash_erase_region(NULL, start, len);
 	flash_esp32_sem_give(dev);
+#endif
 	if (ret != 0) {
-		LOG_ERR("esp_flash_erase_region failed %d", ret);
+		LOG_ERR("Flash erase error: %d", ret);
 		return -EIO;
 	}
 	return 0;
@@ -146,18 +235,12 @@ flash_esp32_get_parameters(const struct device *dev)
 
 static int flash_esp32_init(const struct device *dev)
 {
-	uint32_t ret = 0;
-
 #ifdef CONFIG_MULTITHREADING
 	struct flash_esp32_dev_data *const dev_data = dev->data;
 
 	k_sem_init(&dev_data->sem, 1, 1);
 #endif /* CONFIG_MULTITHREADING */
-	ret = esp_flash_init_default_chip();
-	if (ret != 0) {
-		LOG_ERR("esp_flash_init_default_chip failed %d", ret);
-		return 0;
-	}
+
 	return 0;
 }
 
diff --git a/drivers/flash/flash_hp_ra.c b/drivers/flash/flash_hp_ra.c
index eb5ba3ec5bb..d58985c8ea3 100644
--- a/drivers/flash/flash_hp_ra.c
+++ b/drivers/flash/flash_hp_ra.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -378,8 +378,10 @@ static void flash_controller_ra_irq_config_func(const struct device *dev)
 {
 	ARG_UNUSED(dev);
 
-	R_ICU->IELSR[DT_IRQ_BY_NAME(DT_DRV_INST(0), frdyi, irq)] = ELC_EVENT_FCU_FRDYI;
-	R_ICU->IELSR[DT_IRQ_BY_NAME(DT_DRV_INST(0), fiferr, irq)] = ELC_EVENT_FCU_FIFERR;
+	R_ICU->IELSR[DT_IRQ_BY_NAME(DT_DRV_INST(0), frdyi, irq)] =
+		BSP_PRV_IELS_ENUM(EVENT_FCU_FRDYI);
+	R_ICU->IELSR[DT_IRQ_BY_NAME(DT_DRV_INST(0), fiferr, irq)] =
+		BSP_PRV_IELS_ENUM(EVENT_FCU_FIFERR);
 
 	IRQ_CONNECT(DT_IRQ_BY_NAME(DT_DRV_INST(0), frdyi, irq),
 		    DT_IRQ_BY_NAME(DT_DRV_INST(0), frdyi, priority), fcu_frdyi_isr,
diff --git a/drivers/flash/flash_hp_ra_ex_op.c b/drivers/flash/flash_hp_ra_ex_op.c
index 42cc4c81b1c..aa9c9f3c9fc 100644
--- a/drivers/flash/flash_hp_ra_ex_op.c
+++ b/drivers/flash/flash_hp_ra_ex_op.c
@@ -28,7 +28,8 @@ flash_hp_enter_pe_cf_mode(flash_hp_instance_ctrl_t *const p_ctrl) PLACE_IN_RAM_S
 extern fsp_err_t flash_hp_stop(void) PLACE_IN_RAM_SECTION;
 
 extern fsp_err_t flash_hp_configuration_area_write(flash_hp_instance_ctrl_t *p_ctrl,
-						   uint32_t fsaddr) PLACE_IN_RAM_SECTION;
+						   uint32_t fsaddr,
+						   uint16_t *src_address) PLACE_IN_RAM_SECTION;
 
 extern fsp_err_t flash_hp_check_errors(fsp_err_t previous_error, uint32_t error_bits,
 				       fsp_err_t return_error) PLACE_IN_RAM_SECTION;
@@ -63,7 +64,8 @@ static fsp_err_t flash_hp_set_block_protect_ns(flash_hp_instance_ctrl_t *p_ctrl,
 	if (bps_val_ns != NULL) {
 		memcpy(&g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_BPS_OFFSET], bps_val_ns,
 		       size);
-		err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_BPS);
+		err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_BPS,
+							&g_configuration_area_data);
 		err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED);
 	}
 
@@ -71,7 +73,8 @@ static fsp_err_t flash_hp_set_block_protect_ns(flash_hp_instance_ctrl_t *p_ctrl,
 	if (pbps_val_ns != NULL) {
 		memcpy(&g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_BPS_OFFSET], pbps_val_ns,
 		       size);
-		err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_PBPS);
+		err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_PBPS,
+							&g_configuration_area_data);
 		err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED);
 	}
 
@@ -103,7 +106,8 @@ static fsp_err_t flash_hp_set_block_protect_sec(flash_hp_instance_ctrl_t *p_ctrl
 	if (bps_val_sec != NULL) {
 		memcpy(&g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_BPS_OFFSET], bps_val_sec,
 		       size);
-		err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_BPS_SEC);
+		err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_BPS_SEC,
+							&g_configuration_area_data);
 		err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED);
 	}
 
@@ -111,7 +115,8 @@ static fsp_err_t flash_hp_set_block_protect_sec(flash_hp_instance_ctrl_t *p_ctrl
 	if (pbps_val_sec != NULL) {
 		memcpy(&g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_BPS_OFFSET], pbps_val_sec,
 		       size);
-		err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_PBPS_SEC);
+		err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_PBPS_SEC,
+							&g_configuration_area_data);
 		err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED);
 	}
 
@@ -141,7 +146,8 @@ static fsp_err_t flash_hp_set_block_protect_sel(flash_hp_instance_ctrl_t *p_ctrl
 
 	memset(g_configuration_area_data, UINT8_MAX, sizeof(g_configuration_area_data));
 	memcpy(&g_configuration_area_data[FLASH_HP_FCU_CONFIG_SET_BPS_OFFSET], bps_sel_val, size);
-	err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_BPS_SEL);
+	err = flash_hp_configuration_area_write(p_ctrl, FLASH_HP_FCU_CONFIG_SET_BPS_SEL,
+						&g_configuration_area_data);
 	err = flash_hp_check_errors(err, 0, FSP_ERR_WRITE_FAILED);
 
 	/* Return to read mode*/
diff --git a/drivers/flash/flash_ite_it8xxx2.c b/drivers/flash/flash_ite_it8xxx2.c
index 04b63c7a498..acf5bbd8664 100644
--- a/drivers/flash/flash_ite_it8xxx2.c
+++ b/drivers/flash/flash_ite_it8xxx2.c
@@ -25,8 +25,7 @@
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(flash_ite_it8xxx2);
 
-#define FLASH_IT8XXX2_REG_BASE \
-		((struct smfi_it8xxx2_regs *)DT_INST_REG_ADDR(0))
+#define FLASH_ITE_EC_REGS_BASE ((struct smfi_ite_ec_regs *)DT_INST_REG_ADDR(0))
 
 struct flash_it8xxx2_dev_data {
 	struct k_sem sem;
@@ -93,7 +92,8 @@ static const struct flash_parameters flash_it8xxx2_parameters = {
 
 void __soc_ram_code ramcode_reset_i_cache(void)
 {
-	struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE;
+#ifdef CONFIG_SOC_SERIES_IT8XXX2
+	struct gctrl_ite_ec_regs *const gctrl_regs = GCTRL_ITE_EC_REGS_BASE;
 
 	/* I-Cache tag sram reset */
 	gctrl_regs->GCTRL_MCCR |= IT8XXX2_GCTRL_ICACHE_RESET;
@@ -102,11 +102,14 @@ void __soc_ram_code ramcode_reset_i_cache(void)
 
 	gctrl_regs->GCTRL_MCCR &= ~IT8XXX2_GCTRL_ICACHE_RESET;
 	__asm__ volatile ("fence.i" ::: "memory");
+#else
+	custom_reset_instr_cache();
+#endif
 }
 
 void __soc_ram_code ramcode_flash_follow_mode(void)
 {
-	struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE;
+	struct smfi_ite_ec_regs *const flash_regs = FLASH_ITE_EC_REGS_BASE;
 	/*
 	 * ECINDAR3-0 are EC-indirect memory address registers.
 	 *
@@ -127,7 +130,7 @@ void __soc_ram_code ramcode_flash_follow_mode(void)
 
 void __soc_ram_code ramcode_flash_follow_mode_exit(void)
 {
-	struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE;
+	struct smfi_ite_ec_regs *const flash_regs = FLASH_ITE_EC_REGS_BASE;
 
 	/* Exit follow mode, and keep the setting of selecting internal flash */
 	flash_regs->SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLASH;
@@ -136,8 +139,8 @@ void __soc_ram_code ramcode_flash_follow_mode_exit(void)
 
 void __soc_ram_code ramcode_flash_fsce_high(void)
 {
-	struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE;
-	struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE;
+	struct smfi_ite_ec_regs *const flash_regs = FLASH_ITE_EC_REGS_BASE;
+	struct gctrl_ite_ec_regs *const gctrl_regs = GCTRL_ITE_EC_REGS_BASE;
 
 	/* FSCE# high level */
 	flash_regs->SMFI_ECINDAR1 = (FLASH_FSCE_HIGH_ADDRESS >> 8) & GENMASK(7, 0);
@@ -160,7 +163,7 @@ void __soc_ram_code ramcode_flash_fsce_high(void)
 
 void __soc_ram_code ramcode_flash_write_dat(uint8_t wdata)
 {
-	struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE;
+	struct smfi_ite_ec_regs *const flash_regs = FLASH_ITE_EC_REGS_BASE;
 
 	/* Write data to FMOSI */
 	flash_regs->SMFI_ECINDDR = wdata;
@@ -169,7 +172,7 @@ void __soc_ram_code ramcode_flash_write_dat(uint8_t wdata)
 void __soc_ram_code ramcode_flash_transaction(int wlen, uint8_t *wbuf, int rlen, uint8_t *rbuf,
 					      enum flash_transaction_cmd cmd_end)
 {
-	struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE;
+	struct smfi_ite_ec_regs *const flash_regs = FLASH_ITE_EC_REGS_BASE;
 	int i;
 
 	/*  FSCE# with low level */
@@ -191,7 +194,7 @@ void __soc_ram_code ramcode_flash_transaction(int wlen, uint8_t *wbuf, int rlen,
 void __soc_ram_code ramcode_flash_cmd_read_status(enum flash_status_mask mask,
 						  enum flash_status_mask target)
 {
-	struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE;
+	struct smfi_ite_ec_regs *const flash_regs = FLASH_ITE_EC_REGS_BASE;
 	uint8_t cmd_rs[] = {FLASH_CMD_RS};
 
 	/* Send read status command */
@@ -343,7 +346,7 @@ void __soc_ram_code ramcode_flash_erase(int addr, int cmd)
 static int __soc_ram_code flash_it8xxx2_read(const struct device *dev, off_t offset, void *data,
 					     size_t len)
 {
-	struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE;
+	struct smfi_ite_ec_regs *const flash_regs = FLASH_ITE_EC_REGS_BASE;
 	uint8_t *data_t = data;
 	int i;
 
@@ -464,7 +467,7 @@ flash_it8xxx2_get_parameters(const struct device *dev)
 
 static int flash_it8xxx2_init(const struct device *dev)
 {
-	struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE;
+	struct smfi_ite_ec_regs *const flash_regs = FLASH_ITE_EC_REGS_BASE;
 	struct flash_it8xxx2_dev_data *data = dev->data;
 
 	/* By default, select internal flash for indirect fast read. */
@@ -475,7 +478,7 @@ static int flash_it8xxx2_init(const struct device *dev)
 	 * than 256K-byte, enable the page program cycle constructed
 	 * by EC-Indirect Follow Mode.
 	 */
-	flash_regs->SMFI_FLHCTRL6R |= IT8XXX2_SMFI_MASK_ECINDPP;
+	flash_regs->SMFI_FLHCTRL6R |= ITE_EC_SMFI_MASK_ECINDPP;
 
 	/* Initialize mutex for flash controller */
 	k_sem_init(&data->sem, 1, 1);
diff --git a/drivers/flash/flash_mcux_flexspi_nor.c b/drivers/flash/flash_mcux_flexspi_nor.c
index 59b32b7588d..8487c870656 100644
--- a/drivers/flash/flash_mcux_flexspi_nor.c
+++ b/drivers/flash/flash_mcux_flexspi_nor.c
@@ -143,6 +143,14 @@ static const uint32_t flash_flexspi_nor_base_lut[][MEMC_FLEXSPI_CMD_PER_SEQ] = {
 	},
 };
 
+static ALWAYS_INLINE bool area_is_subregion(const struct device *dev, off_t offset, size_t size)
+{
+	struct flash_flexspi_nor_data *data = dev->data;
+
+	return ((offset >= 0) && (offset < data->size) &&
+		((data->size - offset) >= size));
+}
+
 /* Helper so we can read flash ID without flash access for XIP */
 static int flash_flexspi_nor_read_id_helper(struct flash_flexspi_nor_data *data,
 		uint8_t *vendor_id)
@@ -316,6 +324,15 @@ static int flash_flexspi_nor_read(const struct device *dev, off_t offset,
 		void *buffer, size_t len)
 {
 	struct flash_flexspi_nor_data *data = dev->data;
+
+	if (!buffer) {
+		return -EINVAL;
+	}
+
+	if (!area_is_subregion(dev, offset, len)) {
+		return -EINVAL;
+	}
+
 	uint8_t *src = memc_flexspi_get_ahb_address(&data->controller,
 						    data->port,
 						    offset);
@@ -329,6 +346,15 @@ static int flash_flexspi_nor_write(const struct device *dev, off_t offset,
 		const void *buffer, size_t len)
 {
 	struct flash_flexspi_nor_data *data = dev->data;
+
+	if (!buffer) {
+		return -EINVAL;
+	}
+
+	if (!area_is_subregion(dev, offset, len)) {
+		return -EINVAL;
+	}
+
 	size_t size = len;
 	uint8_t *src = (uint8_t *) buffer;
 	int i;
@@ -393,6 +419,11 @@ static int flash_flexspi_nor_erase(const struct device *dev, off_t offset,
 		size_t size)
 {
 	struct flash_flexspi_nor_data *data = dev->data;
+
+	if (!area_is_subregion(dev, offset, size)) {
+		return -EINVAL;
+	}
+
 	const size_t num_sectors = size / SPI_NOR_SECTOR_SIZE;
 	const size_t num_blocks = size / SPI_NOR_BLOCK_SIZE;
 
@@ -912,37 +943,72 @@ static int flash_flexspi_nor_sfdp_read(const struct device *dev,
 
 #endif
 
-/* Helper to configure IS25 flash, by clearing read param bits */
-static int flash_flexspi_nor_is25_clear_read_param(struct flash_flexspi_nor_data *data,
-			uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],
-			uint32_t *read_params)
+/* Helper to configure IS25 flash */
+static int
+flash_flexspi_nor_is25_clear_dummy_cycles(struct flash_flexspi_nor_data *data,
+					  uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ])
 {
 	int ret;
-	/* Install Set Read Parameters (Volatile) command */
+
+	const flexspi_device_config_t config = {
+		.flexspiRootClk = MHZ(50),
+		.flashSize = FLEXSPI_FLSHCR0_FLSHSZ_MASK, /* Max flash size */
+		.ARDSeqNumber = 1,
+		.ARDSeqIndex = READ,
+	};
+
 	flexspi_transfer_t transfer = {
 		.deviceAddress = 0,
 		.port = data->port,
 		.seqIndex = SCRATCH_CMD,
 		.SeqNumber = 1,
-		.data = read_params,
 		.dataSize = 1,
-		.cmdType = kFLEXSPI_Write,
-	};
-	flexspi_device_config_t config = {
-		.flexspiRootClk = MHZ(50),
-		.flashSize = FLEXSPI_FLSHCR0_FLSHSZ_MASK, /* Max flash size */
-		.ARDSeqNumber = 1,
-		.ARDSeqIndex = READ,
 	};
 
-	flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
-			kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC0,
-			kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
-	ret = memc_flexspi_set_device_config(&data->controller,
-				&config,
-				(uint32_t *)flexspi_lut,
-				FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
-				data->port);
+	/*
+	 * Get Extended Read Parameters (Non-Volatile) command (RDERP, 81h)
+	 *
+	 * This is done to distinguish between an IS25LPXXX and IS25LPXXXD since
+	 * the former uses the read parameters (SRPV) to set drive strength and
+	 * dummy cycles, while IS25LPXXXD uses extended read parameters (SERPV)
+	 * for drive strength and read parameters (SRPV) for dummy cycles.
+	 */
+	uint32_t resp_data;
+
+	transfer.data = &resp_data;
+	transfer.cmdType = kFLEXSPI_Read;
+
+	flexspi_lut[SCRATCH_CMD][0] =
+		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x81,
+				kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
+	ret = memc_flexspi_set_device_config(&data->controller, &config, (uint32_t *)flexspi_lut,
+					     FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
+					     data->port);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = memc_flexspi_transfer(&data->controller, &transfer);
+
+	/*
+	 * Check that EB[7:4] is not all zero and that EB[0] (WIP)
+	 * is not 1, which should catch a chip responding to an
+	 * unsupported 81h command with either 0x00 or 0xFF
+	 */
+	const int has_extended_read_reg = resp_data & 0xF0 && !(resp_data & 0x01);
+	uint32_t read_params = has_extended_read_reg ? 0 : 0xE0U;
+
+	/* Switch over to writing read_params (SRPV, C0h) */
+	transfer.cmdType = kFLEXSPI_Write;
+	transfer.data = &read_params;
+
+	flexspi_lut[SCRATCH_CMD][0] =
+		FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xC0,
+				kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
+	ret = memc_flexspi_set_device_config(&data->controller, &config, (uint32_t *)flexspi_lut,
+					     FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
+					     data->port);
 	if (ret < 0) {
 		return ret;
 	}
@@ -955,7 +1021,6 @@ static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data,
 {
 	int ret;
 	uint32_t vendor_id;
-	uint32_t read_params;
 
 	ret = flash_flexspi_nor_read_id_helper(data, (uint8_t *)&vendor_id);
 	if (ret < 0) {
@@ -964,31 +1029,17 @@ static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data,
 
 	/* Switch on manufacturer and vendor ID */
 	switch (vendor_id & 0xFFFFFF) {
-	case 0x16609d: /* IS25LP032 flash, needs P[4:3] cleared with same method as IS25WP */
+	case 0x16609d: /* IS25LP032 */
 	case 0x17609d: /* IS25LP064 */
 	case 0x18609d: /* IS25LP128 */
-		read_params = 0xE0U;
-		ret = flash_flexspi_nor_is25_clear_read_param(data, flexspi_lut, &read_params);
-		if (ret < 0) {
-			while (1) {
-				/*
-				 * Spin here, this flash won't configure correctly.
-				 * We can't print a warning, as we are unlikely to
-				 * be able to XIP at this point.
-				 */
-			}
-		}
-		/* Still return an error- we want the JEDEC configuration to run */
-		return -ENOTSUP;
 	case 0x16709d: /* IS25WP032 */
 	case 0x17709d: /* IS25WP064 */
 	case 0x18709d: /* IS25WP128 */
 		/*
-		 * IS25WP flash. We can support this flash with the JEDEC probe,
-		 * but we need to insure P[6:3] are at the default value
+		 * We can support this flash with the JEDEC probe, but we need to
+		 * ensure Dummy Cycles are at the default value
 		 */
-		read_params = 0;
-		ret = flash_flexspi_nor_is25_clear_read_param(data, flexspi_lut, &read_params);
+		ret = flash_flexspi_nor_is25_clear_dummy_cycles(data, flexspi_lut);
 		if (ret < 0) {
 			while (1) {
 				/*
diff --git a/drivers/flash/flash_npcx_fiu_nor.c b/drivers/flash/flash_npcx_fiu_nor.c
index ae3a31945fd..cbd3dcd70a5 100644
--- a/drivers/flash/flash_npcx_fiu_nor.c
+++ b/drivers/flash/flash_npcx_fiu_nor.c
@@ -23,9 +23,15 @@
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(flash_npcx_fiu_nor, CONFIG_FLASH_LOG_LEVEL);
 
+#if defined(CONFIG_ESPI_TAF)
+static const struct device *const espi_dev = DEVICE_DT_GET(DT_NODELABEL(espi0));
+#endif
+
 #define BLOCK_64K_SIZE KB(64)
 #define BLOCK_4K_SIZE  KB(4)
 
+#define POLLING_BUSY_SLEEP_TIME_US 100
+
 /* Device config */
 struct flash_npcx_nor_config {
 	/* QSPI bus device for mutex control and bus configuration */
@@ -45,6 +51,8 @@ struct flash_npcx_nor_config {
 
 /* Device data */
 struct flash_npcx_nor_data {
+	/* mutex for flash write and erase operation */
+	struct k_sem nor_flash_sem;
 	/* Specific control operation for Quad-SPI Nor Flash */
 	uint32_t operation;
 };
@@ -153,6 +161,7 @@ static int flash_npcx_nor_wait_until_ready(const struct device *dev)
 			return 0;
 		}
 
+		k_usleep(POLLING_BUSY_SLEEP_TIME_US);
 	} while ((k_uptime_get() - st) < config->max_timeout);
 
 	return -EBUSY;
@@ -189,16 +198,32 @@ static int flash_npcx_nor_write_status_regs(const struct device *dev, uint8_t *s
 #if defined(CONFIG_FLASH_JESD216_API)
 static int flash_npcx_nor_read_jedec_id(const struct device *dev, uint8_t *id)
 {
+	int ret;
+
 	if (id == NULL) {
 		return -EINVAL;
 	}
 
-	return flash_npcx_uma_read(dev, SPI_NOR_CMD_RDID, id, SPI_NOR_MAX_ID_LEN);
+#if defined(CONFIG_ESPI_TAF)
+	if (espi_taf_npcx_block(espi_dev, true) != 0) {
+		LOG_ERR("TAF LOCK TIMEOUT");
+		return -ETIMEDOUT;
+	}
+#endif
+
+	ret = flash_npcx_uma_read(dev, SPI_NOR_CMD_RDID, id, SPI_NOR_MAX_ID_LEN);
+
+#if defined(CONFIG_ESPI_TAF)
+	espi_taf_npcx_block(espi_dev, false);
+#endif
+
+	return ret;
 }
 
 static int flash_npcx_nor_read_sfdp(const struct device *dev, off_t addr,
 				    void *data, size_t size)
 {
+	int ret;
 	uint8_t sfdp_addr[4];
 	struct npcx_uma_cfg cfg = { .opcode = JESD216_CMD_READ_SFDP,
 					.tx_buf = sfdp_addr,
@@ -214,8 +239,22 @@ static int flash_npcx_nor_read_sfdp(const struct device *dev, off_t addr,
 	sfdp_addr[0] = (addr >> 16) & 0xff;
 	sfdp_addr[1] = (addr >> 8) & 0xff;
 	sfdp_addr[2] = addr & 0xff;
-	return flash_npcx_uma_transceive(dev, &cfg, NPCX_UMA_ACCESS_WRITE |
+
+#if defined(CONFIG_ESPI_TAF)
+	if (espi_taf_npcx_block(espi_dev, true) != 0) {
+		LOG_ERR("TAF LOCK TIMEOUT");
+		return -ETIMEDOUT;
+	}
+#endif
+
+	ret = flash_npcx_uma_transceive(dev, &cfg, NPCX_UMA_ACCESS_WRITE |
 					 NPCX_UMA_ACCESS_READ);
+
+#if defined(CONFIG_ESPI_TAF)
+	espi_taf_npcx_block(espi_dev, false);
+#endif
+
+	return ret;
 }
 #endif /* CONFIG_FLASH_JESD216_API */
 
@@ -257,32 +296,47 @@ static int flash_npcx_nor_read(const struct device *dev, off_t addr,
 static int flash_npcx_nor_erase(const struct device *dev, off_t addr, size_t size)
 {
 	const struct flash_npcx_nor_config *config = dev->config;
+	struct flash_npcx_nor_data *dev_data = dev->data;
 	int ret = 0;
 
+	k_sem_take(&dev_data->nor_flash_sem, K_FOREVER);
+
 	/* Out of the region of nor flash device? */
 	if (!is_within_region(addr, size, 0, config->flash_size)) {
 		LOG_ERR("Addr %ld, size %d are out of range", addr, size);
-		return -EINVAL;
+		ret = -EINVAL;
+		goto out_nor_erase;
 	}
 
 	/* address must be sector-aligned */
 	if (!SPI_NOR_IS_SECTOR_ALIGNED(addr)) {
 		LOG_ERR("Addr %ld is not sector-aligned", addr);
-		return -EINVAL;
+		ret = -EINVAL;
+		goto out_nor_erase;
 	}
 
 	/* size must be a multiple of sectors */
 	if ((size % BLOCK_4K_SIZE) != 0) {
 		LOG_ERR("Size %d is not a multiple of sectors", size);
-		return -EINVAL;
+		ret = -EINVAL;
+		goto out_nor_erase;
+	}
+
+#if defined(CONFIG_ESPI_TAF)
+	if (espi_taf_npcx_block(espi_dev, true) != 0) {
+		LOG_ERR("TAF LOCK TIMEOUT");
+		ret = -ETIMEDOUT;
+		goto out_nor_erase;
 	}
+#endif
 
 	/* Select erase opcode by size */
 	if (size == config->flash_size) {
 		flash_npcx_uma_cmd_only(dev, SPI_NOR_CMD_WREN);
 		/* Send chip erase command */
 		flash_npcx_uma_cmd_only(dev, SPI_NOR_CMD_CE);
-		return flash_npcx_nor_wait_until_ready(dev);
+		ret = flash_npcx_nor_wait_until_ready(dev);
+		goto out_nor_erase_unblock;
 	}
 
 	while (size > 0) {
@@ -302,6 +356,12 @@ static int flash_npcx_nor_erase(const struct device *dev, off_t addr, size_t siz
 			break;
 		}
 	}
+out_nor_erase_unblock:
+#if defined(CONFIG_ESPI_TAF)
+	espi_taf_npcx_block(espi_dev, false);
+#endif
+out_nor_erase:
+	k_sem_give(&dev_data->nor_flash_sem);
 
 	return ret;
 }
@@ -310,12 +370,16 @@ static int flash_npcx_nor_write(const struct device *dev, off_t addr,
 				  const void *data, size_t size)
 {
 	const struct flash_npcx_nor_config *config = dev->config;
+	struct flash_npcx_nor_data *dev_data = dev->data;
 	uint8_t *tx_buf = (uint8_t *)data;
 	int ret = 0;
 	size_t sz_write;
 
+	k_sem_take(&dev_data->nor_flash_sem, K_FOREVER);
+
 	/* Out of the region of nor flash device? */
 	if (!is_within_region(addr, size, 0, config->flash_size)) {
+		k_sem_give(&dev_data->nor_flash_sem);
 		return -EINVAL;
 	}
 
@@ -335,20 +399,38 @@ static int flash_npcx_nor_write(const struct device *dev, off_t addr,
 	}
 
 	while (size > 0) {
+#if defined(CONFIG_ESPI_TAF)
+		if (espi_taf_npcx_block(espi_dev, true) != 0) {
+			LOG_ERR("TAF LOCK TIMEOUT");
+			k_sem_give(&dev_data->nor_flash_sem);
+
+			return -ETIMEDOUT;
+		}
+#endif
 		/* Start to write */
 		flash_npcx_uma_cmd_only(dev, SPI_NOR_CMD_WREN);
 		ret = flash_npcx_uma_write_by_addr(dev, SPI_NOR_CMD_PP, tx_buf,
 						   sz_write, addr);
 		if (ret != 0) {
+#if defined(CONFIG_ESPI_TAF)
+			espi_taf_npcx_block(espi_dev, false);
+#endif
 			break;
 		}
 
 		/* Wait for writing completed */
 		ret = flash_npcx_nor_wait_until_ready(dev);
 		if (ret != 0) {
+#if defined(CONFIG_ESPI_TAF)
+			espi_taf_npcx_block(espi_dev, false);
+#endif
 			break;
 		}
 
+#if defined(CONFIG_ESPI_TAF)
+		espi_taf_npcx_block(espi_dev, false);
+#endif
+
 		size -= sz_write;
 		tx_buf += sz_write;
 		addr += sz_write;
@@ -360,6 +442,8 @@ static int flash_npcx_nor_write(const struct device *dev, off_t addr,
 		}
 	}
 
+	k_sem_give(&dev_data->nor_flash_sem);
+
 	return ret;
 }
 
@@ -459,7 +543,16 @@ static int flash_npcx_nor_ex_op(const struct device *dev, uint16_t code,
 		}
 #endif
 
+#if defined(CONFIG_ESPI_TAF)
+		if (espi_taf_npcx_block(espi_dev, true) != 0) {
+			LOG_ERR("TAF LOCK TIMEOUT");
+			return -ETIMEDOUT;
+		}
+#endif
 		ret = flash_npcx_nor_ex_exec_uma(dev, op_in, op_out);
+#if defined(CONFIG_ESPI_TAF)
+		espi_taf_npcx_block(espi_dev, false);
+#endif
 #ifdef CONFIG_USERSPACE
 		if (ret == 0 && syscall_trap) {
 			K_OOPS(k_usermode_to_copy(out, op_out, sizeof(out_copy)));
@@ -529,6 +622,7 @@ static DEVICE_API(flash, flash_npcx_nor_driver_api) = {
 static int flash_npcx_nor_init(const struct device *dev)
 {
 	const struct flash_npcx_nor_config *config = dev->config;
+	struct flash_npcx_nor_data *dev_data = dev->data;
 	int ret;
 
 	if (!IS_ENABLED(CONFIG_FLASH_NPCX_FIU_NOR_INIT)) {
@@ -587,9 +681,25 @@ static int flash_npcx_nor_init(const struct device *dev)
 		}
 	}
 
+	if (config->qspi_cfg.is_logical_low_dev && IS_ENABLED(CONFIG_FLASH_NPCX_FIU_DRA_V2)) {
+		qspi_npcx_fiu_set_spi_size(config->qspi_bus, &config->qspi_cfg);
+	}
+
+	k_sem_init(&dev_data->nor_flash_sem, 1, 1);
+
 	return 0;
 }
 
+#define NPCX_FLASH_IS_LOGICAL_LOW_DEV(n)					\
+	(DT_PROP(DT_PARENT(DT_DRV_INST(n)), en_direct_access_2dev) &&		\
+	 (DT_PROP(DT_PARENT(DT_DRV_INST(n)), flash_dev_inv) ==			\
+	  ((DT_INST_PROP(n, qspi_flags) & NPCX_QSPI_SEC_FLASH_SL) ==		\
+	   NPCX_QSPI_SEC_FLASH_SL)))
+
+#define NPCX_FLASH_SPI_ALLOCATE_SIZE(n)						\
+	COND_CODE_1(DT_INST_NODE_HAS_PROP(n, spi_dev_size),			\
+		    (DT_INST_STRING_TOKEN(n, spi_dev_size)), (0xFF))
+
 #define NPCX_FLASH_NOR_INIT(n)							\
 BUILD_ASSERT(DT_INST_QUAD_EN_PROP_OR(n) == JESD216_DW15_QER_NONE ||		\
 	     DT_INST_STRING_TOKEN(n, rd_mode) == NPCX_RD_MODE_FAST_DUAL,	\
@@ -606,6 +716,8 @@ static const struct flash_npcx_nor_config flash_npcx_nor_config_##n = {		\
 		.enter_4ba = DT_INST_PROP_OR(n, enter_4byte_addr, 0),		\
 		.qer_type = DT_INST_QUAD_EN_PROP_OR(n),				\
 		.rd_mode = DT_INST_STRING_TOKEN(n, rd_mode),			\
+		.is_logical_low_dev = NPCX_FLASH_IS_LOGICAL_LOW_DEV(n),		\
+		.spi_dev_sz = NPCX_FLASH_SPI_ALLOCATE_SIZE(n),			\
 	},									\
 	IF_ENABLED(CONFIG_FLASH_PAGE_LAYOUT, (					\
 		.layout = {							\
diff --git a/drivers/flash/flash_npcx_fiu_qspi.c b/drivers/flash/flash_npcx_fiu_qspi.c
index 4084a84fb21..5d78eed2f3c 100644
--- a/drivers/flash/flash_npcx_fiu_qspi.c
+++ b/drivers/flash/flash_npcx_fiu_qspi.c
@@ -30,6 +30,7 @@ struct npcx_qspi_fiu_config {
 	struct npcx_clk_cfg clk_cfg;
 	/* Enable 2 external SPI devices for direct read on QSPI bus */
 	bool en_direct_access_2dev;
+	bool base_flash_inv;
 };
 
 /* Device data */
@@ -244,6 +245,25 @@ void qspi_npcx_fiu_mutex_unlock(const struct device *dev)
 	k_sem_give(&data->lock_sem);
 }
 
+#if defined(CONFIG_FLASH_NPCX_FIU_DRA_V2)
+void qspi_npcx_fiu_set_spi_size(const struct device *dev, const struct npcx_qspi_cfg *cfg)
+{
+	struct fiu_reg *const inst = HAL_INSTANCE(dev);
+	uint8_t flags = cfg->flags;
+
+	if (cfg->spi_dev_sz <= NPCX_SPI_DEV_SIZE_128M) {
+		if ((flags & NPCX_QSPI_SEC_FLASH_SL) == 0) {
+			SET_FIELD(inst->BURST_CFG, NPCX_BURST_CFG_SPI_DEV_SEL, NPCX_SPI_F_CS0);
+		} else {
+			SET_FIELD(inst->BURST_CFG, NPCX_BURST_CFG_SPI_DEV_SEL, NPCX_SPI_F_CS1);
+		}
+		inst->SPI_DEV_SIZE = BIT(cfg->spi_dev_sz);
+	} else {
+		LOG_ERR("Invalid setting of low device size");
+	}
+}
+#endif
+
 static int qspi_npcx_fiu_init(const struct device *dev)
 {
 	const struct npcx_qspi_fiu_config *const config = dev->config;
@@ -273,6 +293,11 @@ static int qspi_npcx_fiu_init(const struct device *dev)
 		struct fiu_reg *const inst = HAL_INSTANCE(dev);
 
 		inst->FIU_EXT_CFG |= BIT(NPCX_FIU_EXT_CFG_SPI1_2DEV);
+#if defined(CONFIG_FLASH_NPCX_FIU_SUPP_LOW_DEV_SWAP)
+		if (config->base_flash_inv) {
+			inst->FIU_EXT_CFG |= BIT(NPCX_FIU_EXT_CFG_LOW_DEV_NUM);
+		}
+#endif
 #endif
 	}
 
@@ -284,6 +309,7 @@ static const struct npcx_qspi_fiu_config npcx_qspi_fiu_config_##n = {		\
 	.base = DT_INST_REG_ADDR(n),						\
 	.clk_cfg = NPCX_DT_CLK_CFG_ITEM(n),					\
 	.en_direct_access_2dev = DT_INST_PROP(n, en_direct_access_2dev),	\
+	.base_flash_inv = DT_INST_PROP(n, flash_dev_inv),			\
 };										\
 static struct npcx_qspi_fiu_data npcx_qspi_fiu_data_##n;			\
 DEVICE_DT_INST_DEFINE(n, qspi_npcx_fiu_init, NULL,				\
diff --git a/drivers/flash/flash_npcx_fiu_qspi.h b/drivers/flash/flash_npcx_fiu_qspi.h
index 1136684d453..6e63dd8b076 100644
--- a/drivers/flash/flash_npcx_fiu_qspi.h
+++ b/drivers/flash/flash_npcx_fiu_qspi.h
@@ -25,6 +25,20 @@ extern "C" {
 #define NPCX_DEV_NUM_ADDR_3BYTE 3
 #define NPCX_DEV_NUM_ADDR_4BYTE 4
 
+#define NPCX_SPI_F_CS0 0
+#define NPCX_SPI_F_CS1 1
+
+enum NPCX_SPI_DEV_SIZE {
+	NPCX_SPI_DEV_SIZE_1M,
+	NPCX_SPI_DEV_SIZE_2M,
+	NPCX_SPI_DEV_SIZE_4M,
+	NPCX_SPI_DEV_SIZE_8M,
+	NPCX_SPI_DEV_SIZE_16M,
+	NPCX_SPI_DEV_SIZE_32M,
+	NPCX_SPI_DEV_SIZE_64M,
+	NPCX_SPI_DEV_SIZE_128M,
+};
+
 /* UMA operation configuration for a SPI device */
 struct npcx_uma_cfg {
 	uint8_t opcode;
@@ -48,6 +62,8 @@ struct npcx_qspi_cfg {
 	uint8_t enter_4ba;
 	/* SPI read access type of Direct Read Access mode */
 	uint8_t rd_mode;
+	bool is_logical_low_dev;
+	uint8_t spi_dev_sz;
 	/* Configurations for the Quad-SPI peripherals */
 	int flags;
 };
@@ -81,6 +97,14 @@ void qspi_npcx_fiu_mutex_lock_configure(const struct device *dev,
  */
 void qspi_npcx_fiu_mutex_unlock(const struct device *dev);
 
+/**
+ * @brief Set the size of the address space allocated for SPI device.
+ *
+ * @param dev Pointer to the device structure for qspi bus controller instance.
+ * @param cfg Pointer to the configuration for the device on qspi bus.
+ */
+void qspi_npcx_fiu_set_spi_size(const struct device *dev, const struct npcx_qspi_cfg *cfg);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/drivers/flash/flash_nxp_s32_qspi.c b/drivers/flash/flash_nxp_s32_qspi.c
new file mode 100644
index 00000000000..424960935ba
--- /dev/null
+++ b/drivers/flash/flash_nxp_s32_qspi.c
@@ -0,0 +1,274 @@
+/*
+ * Copyright 2023-2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/flash.h>
+#include <zephyr/logging/log.h>
+
+#include <Qspi_Ip.h>
+
+#include "flash_nxp_s32_qspi.h"
+
+LOG_MODULE_REGISTER(flash_nxp_s32_qspi, CONFIG_FLASH_LOG_LEVEL);
+
+static ALWAYS_INLINE bool area_is_subregion(const struct device *dev, off_t offset, size_t size)
+{
+	Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev);
+
+	return ((offset >= 0) && (offset < memory_cfg->memSize) &&
+		((memory_cfg->memSize - offset) >= size));
+}
+
+uint8_t nxp_s32_qspi_register_device(void)
+{
+	static uint8_t instance_cnt;
+
+	return instance_cnt++;
+}
+
+/* Must be called with lock */
+int nxp_s32_qspi_wait_until_ready(const struct device *dev)
+{
+	struct nxp_s32_qspi_data *data = dev->data;
+	Qspi_Ip_StatusType status;
+	uint32_t timeout = 0xFFFFFF;
+	int ret = 0;
+
+	do {
+		status = Qspi_Ip_GetMemoryStatus(data->instance);
+		timeout--;
+	} while ((status == STATUS_QSPI_IP_BUSY) && (timeout > 0));
+
+	if (status != STATUS_QSPI_IP_SUCCESS) {
+		LOG_ERR("Failed to read memory status (%d)", status);
+		ret = -EIO;
+	} else if (timeout == 0) {
+		LOG_ERR("Timeout, memory is busy");
+		ret = -ETIMEDOUT;
+	}
+
+	return ret;
+}
+
+int nxp_s32_qspi_read(const struct device *dev, off_t offset, void *dest, size_t size)
+{
+	struct nxp_s32_qspi_data *data = dev->data;
+	Qspi_Ip_StatusType status;
+	int ret = 0;
+
+	if (!dest) {
+		return -EINVAL;
+	}
+
+	if (!area_is_subregion(dev, offset, size)) {
+		return -EINVAL;
+	}
+
+	if (size) {
+		nxp_s32_qspi_lock(dev);
+
+		status = Qspi_Ip_Read(data->instance, (uint32_t)offset, (uint8_t *)dest,
+				      (uint32_t)size);
+		if (status != STATUS_QSPI_IP_SUCCESS) {
+			LOG_ERR("Failed to read %zu bytes at 0x%lx (%d)", size, offset, status);
+			ret = -EIO;
+		}
+
+		nxp_s32_qspi_unlock(dev);
+	}
+
+	return ret;
+}
+
+int nxp_s32_qspi_write(const struct device *dev, off_t offset, const void *src, size_t size)
+{
+	const struct nxp_s32_qspi_config *config = dev->config;
+	struct nxp_s32_qspi_data *data = dev->data;
+	Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev);
+	Qspi_Ip_StatusType status;
+	size_t max_write = (size_t)MIN(QSPI_IP_MAX_WRITE_SIZE, memory_cfg->pageSize);
+	size_t len;
+	int ret = 0;
+
+	if (!src || !size) {
+		return -EINVAL;
+	}
+
+	if (!area_is_subregion(dev, offset, size) ||
+	    (offset % config->flash_parameters.write_block_size) ||
+	    (size % config->flash_parameters.write_block_size)) {
+		return -EINVAL;
+	}
+
+	nxp_s32_qspi_lock(dev);
+
+	while (size) {
+		len = MIN(max_write - (offset % max_write), size);
+		status = Qspi_Ip_Program(data->instance, (uint32_t)offset, (const uint8_t *)src,
+					 (uint32_t)len);
+		if (status != STATUS_QSPI_IP_SUCCESS) {
+			LOG_ERR("Failed to write %zu bytes at 0x%lx (%d)", len, offset, status);
+			ret = -EIO;
+			break;
+		}
+
+		ret = nxp_s32_qspi_wait_until_ready(dev);
+		if (ret != 0) {
+			break;
+		}
+
+		if (IS_ENABLED(CONFIG_FLASH_NXP_S32_QSPI_VERIFY_WRITE)) {
+			status = Qspi_Ip_ProgramVerify(data->instance, (uint32_t)offset,
+						       (const uint8_t *)src, (uint32_t)len);
+			if (status != STATUS_QSPI_IP_SUCCESS) {
+				LOG_ERR("Write verification failed at 0x%lx (%d)", offset, status);
+				ret = -EIO;
+				break;
+			}
+		}
+
+		size -= len;
+		src = (const uint8_t *)src + len;
+		offset += len;
+	}
+
+	nxp_s32_qspi_unlock(dev);
+
+	return ret;
+}
+
+static int nxp_s32_qspi_erase_block(const struct device *dev, off_t offset, size_t size,
+				    size_t *erase_size)
+{
+	struct nxp_s32_qspi_data *data = dev->data;
+	Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev);
+	Qspi_Ip_EraseVarConfigType *etp = NULL;
+	Qspi_Ip_EraseVarConfigType *etp_tmp;
+	Qspi_Ip_StatusType status;
+	int ret = 0;
+
+	/*
+	 * Find the erase type with bigger size that can erase all or part of the
+	 * requested memory size
+	 */
+	for (uint8_t i = 0; i < QSPI_IP_ERASE_TYPES; i++) {
+		etp_tmp = (Qspi_Ip_EraseVarConfigType *)&(memory_cfg->eraseSettings.eraseTypes[i]);
+		if ((etp_tmp->eraseLut != QSPI_IP_LUT_INVALID) &&
+		    QSPI_IS_ALIGNED(offset, etp_tmp->size) && (BIT(etp_tmp->size) <= size) &&
+		    ((etp == NULL) || (etp_tmp->size > etp->size))) {
+
+			etp = etp_tmp;
+		}
+	}
+	if (etp != NULL) {
+		*erase_size = BIT(etp->size);
+		status = Qspi_Ip_EraseBlock(data->instance, (uint32_t)offset, *erase_size);
+		if (status != STATUS_QSPI_IP_SUCCESS) {
+			LOG_ERR("Failed to erase %zu bytes at 0x%lx (%d)", *erase_size,
+				(long)offset, status);
+			ret = -EIO;
+		}
+	} else {
+		LOG_ERR("Can't find erase size to erase %zu bytes", size);
+		ret = -EINVAL;
+	}
+
+	return ret;
+}
+
+int nxp_s32_qspi_erase(const struct device *dev, off_t offset, size_t size)
+{
+	struct nxp_s32_qspi_data *data = dev->data;
+	Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev);
+	Qspi_Ip_StatusType status;
+	size_t erase_size;
+	int ret = 0;
+
+	if (!area_is_subregion(dev, offset, size) || !size) {
+		return -EINVAL;
+	}
+
+	nxp_s32_qspi_lock(dev);
+
+	if (size == memory_cfg->memSize) {
+		status = Qspi_Ip_EraseChip(data->instance);
+		if (status != STATUS_QSPI_IP_SUCCESS) {
+			LOG_ERR("Failed to erase chip (%d)", status);
+			ret = -EIO;
+		}
+	} else {
+		while (size > 0) {
+			erase_size = 0;
+
+			ret = nxp_s32_qspi_erase_block(dev, offset, size, &erase_size);
+			if (ret != 0) {
+				break;
+			}
+
+			ret = nxp_s32_qspi_wait_until_ready(dev);
+			if (ret != 0) {
+				break;
+			}
+
+			if (IS_ENABLED(CONFIG_FLASH_NXP_S32_QSPI_VERIFY_ERASE)) {
+				status = Qspi_Ip_EraseVerify(data->instance, (uint32_t)offset,
+							     erase_size);
+				if (status != STATUS_QSPI_IP_SUCCESS) {
+					LOG_ERR("Erase verification failed at 0x%lx (%d)", offset,
+						status);
+					ret = -EIO;
+					break;
+				}
+			}
+
+			offset += erase_size;
+			size -= erase_size;
+		}
+	}
+
+	nxp_s32_qspi_unlock(dev);
+
+	return ret;
+}
+
+const struct flash_parameters *nxp_s32_qspi_get_parameters(const struct device *dev)
+{
+	const struct nxp_s32_qspi_config *config = dev->config;
+
+	return &config->flash_parameters;
+}
+
+#if defined(CONFIG_FLASH_PAGE_LAYOUT)
+void nxp_s32_qspi_pages_layout(const struct device *dev, const struct flash_pages_layout **layout,
+			       size_t *layout_size)
+{
+	const struct nxp_s32_qspi_config *config = dev->config;
+
+	*layout = &config->layout;
+	*layout_size = 1;
+}
+#endif /* CONFIG_FLASH_PAGE_LAYOUT */
+
+#if defined(CONFIG_FLASH_JESD216_API) || !defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME)
+int nxp_s32_qspi_read_id(const struct device *dev, uint8_t *id)
+{
+	struct nxp_s32_qspi_data *data = dev->data;
+	Qspi_Ip_StatusType status;
+	int ret = 0;
+
+	nxp_s32_qspi_lock(dev);
+
+	status = Qspi_Ip_ReadId(data->instance, id);
+	if (status != STATUS_QSPI_IP_SUCCESS) {
+		LOG_ERR("Failed to read device ID (%d)", status);
+		ret = -EIO;
+	}
+
+	nxp_s32_qspi_unlock(dev);
+
+	return ret;
+}
+#endif /* CONFIG_FLASH_JESD216_API || !CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME */
diff --git a/drivers/flash/flash_nxp_s32_qspi.h b/drivers/flash/flash_nxp_s32_qspi.h
new file mode 100644
index 00000000000..5a296ca4d66
--- /dev/null
+++ b/drivers/flash/flash_nxp_s32_qspi.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright 2023-2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_FLASH_NXP_S32_QSPI_H_
+#define ZEPHYR_DRIVERS_FLASH_NXP_S32_QSPI_H_
+
+#include "jesd216.h"
+
+#define QSPI_ERASE_VALUE 0xff
+
+#define QSPI_IS_ALIGNED(addr, bits) (((addr) & BIT_MASK(bits)) == 0)
+
+#if defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME)
+/* Size of LUT */
+#define QSPI_SFDP_LUT_SIZE     130U
+/* Size of init operations */
+#define QSPI_SFDP_INIT_OP_SIZE 8U
+#if defined(CONFIG_FLASH_JESD216_API)
+/* Size of all LUT sequences for JESD216 operations */
+#define QSPI_JESD216_SEQ_SIZE 8U
+#endif /* CONFIG_FLASH_JESD216_API */
+#endif /* CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME */
+
+struct nxp_s32_qspi_config {
+	const struct device *controller;
+	struct flash_parameters flash_parameters;
+#if defined(CONFIG_FLASH_PAGE_LAYOUT)
+	struct flash_pages_layout layout;
+#endif
+#if !defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME)
+	const Qspi_Ip_MemoryConfigType memory_cfg;
+	enum jesd216_dw15_qer_type qer_type;
+	bool quad_mode;
+#endif
+};
+
+struct nxp_s32_qspi_data {
+	uint8_t instance;
+	Qspi_Ip_MemoryConnectionType memory_conn_cfg;
+	uint8_t read_sfdp_lut_idx;
+#if defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME)
+	Qspi_Ip_MemoryConfigType memory_cfg;
+	Qspi_Ip_InstrOpType lut_ops[QSPI_SFDP_LUT_SIZE];
+	Qspi_Ip_InitOperationType init_ops[QSPI_SFDP_INIT_OP_SIZE];
+#endif
+#if defined(CONFIG_MULTITHREADING)
+	struct k_sem sem;
+#endif
+};
+
+static ALWAYS_INLINE Qspi_Ip_MemoryConfigType *get_memory_config(const struct device *dev)
+{
+#if defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME)
+	return &((struct nxp_s32_qspi_data *)dev->data)->memory_cfg;
+#else
+	return ((Qspi_Ip_MemoryConfigType *)&((const struct nxp_s32_qspi_config *)dev->config)
+			->memory_cfg);
+#endif
+}
+
+static inline void nxp_s32_qspi_lock(const struct device *dev)
+{
+#ifdef CONFIG_MULTITHREADING
+	struct nxp_s32_qspi_data *data = dev->data;
+
+	k_sem_take(&data->sem, K_FOREVER);
+#else
+	ARG_UNUSED(dev);
+#endif
+}
+
+static inline void nxp_s32_qspi_unlock(const struct device *dev)
+{
+#ifdef CONFIG_MULTITHREADING
+	struct nxp_s32_qspi_data *data = dev->data;
+
+	k_sem_give(&data->sem);
+#else
+	ARG_UNUSED(dev);
+#endif
+}
+
+/*
+ * This function retrieves the device instance used by the HAL
+ * to access the internal driver state.
+ */
+uint8_t nxp_s32_qspi_register_device(void);
+
+int nxp_s32_qspi_wait_until_ready(const struct device *dev);
+
+int nxp_s32_qspi_read(const struct device *dev, off_t offset, void *dest, size_t size);
+
+int nxp_s32_qspi_write(const struct device *dev, off_t offset, const void *src, size_t size);
+
+int nxp_s32_qspi_erase(const struct device *dev, off_t offset, size_t size);
+
+const struct flash_parameters *nxp_s32_qspi_get_parameters(const struct device *dev);
+
+#if defined(CONFIG_FLASH_PAGE_LAYOUT)
+void nxp_s32_qspi_pages_layout(const struct device *dev, const struct flash_pages_layout **layout,
+			       size_t *layout_size);
+#endif /* CONFIG_FLASH_PAGE_LAYOUT */
+
+#if defined(CONFIG_FLASH_JESD216_API) || !defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME)
+int nxp_s32_qspi_read_id(const struct device *dev, uint8_t *id);
+#endif /* CONFIG_FLASH_JESD216_API || !CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME */
+
+#endif /* ZEPHYR_DRIVERS_FLASH_NXP_S32_QSPI_H_ */
diff --git a/drivers/flash/flash_nxp_s32_qspi_hyperflash.c b/drivers/flash/flash_nxp_s32_qspi_hyperflash.c
new file mode 100644
index 00000000000..4428aaded1f
--- /dev/null
+++ b/drivers/flash/flash_nxp_s32_qspi_hyperflash.c
@@ -0,0 +1,247 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_s32_qspi_hyperflash
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/flash.h>
+#include <zephyr/logging/log.h>
+
+#include <Qspi_Ip.h>
+
+#include "memc_nxp_s32_qspi.h"
+#include "flash_nxp_s32_qspi.h"
+
+LOG_MODULE_REGISTER(nxp_s32_qspi_hyperflash, CONFIG_FLASH_LOG_LEVEL);
+
+/* Use the fixed command sets from Qspi_Ip_Hyperflash.c */
+extern Qspi_Ip_InstrOpType QSPI_IP_HF_LUT_NAME[QSPI_IP_HF_LUT_SIZE];
+
+static int nxp_s32_qspi_init(const struct device *dev)
+{
+	struct nxp_s32_qspi_data *data = dev->data;
+	const struct nxp_s32_qspi_config *config = dev->config;
+	Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev);
+	uint8_t dev_id[memory_cfg->readIdSettings.readIdSize];
+	Qspi_Ip_StatusType status;
+	int ret = 0;
+
+	/* Used by the HAL to retrieve the internal driver state */
+	data->instance = nxp_s32_qspi_register_device();
+	__ASSERT_NO_MSG(data->instance < QSPI_IP_MEM_INSTANCE_COUNT);
+	data->memory_conn_cfg.qspiInstance = memc_nxp_s32_qspi_get_instance(config->controller);
+
+#if defined(CONFIG_MULTITHREADING)
+	k_sem_init(&data->sem, 1, 1);
+#endif
+
+	if (!device_is_ready(config->controller)) {
+		LOG_ERR("Memory control device not ready");
+		return -ENODEV;
+	}
+
+	status = Qspi_Ip_Init(data->instance, (const Qspi_Ip_MemoryConfigType *)memory_cfg,
+			      (const Qspi_Ip_MemoryConnectionType *)&data->memory_conn_cfg);
+	if (status != STATUS_QSPI_IP_SUCCESS) {
+		LOG_ERR("Fail to init memory device %d (%d)", data->instance, status);
+		return -EIO;
+	}
+
+	/* Verify connectivity by reading the device ID */
+	ret = nxp_s32_qspi_read_id(dev, dev_id);
+	if (ret != 0) {
+		LOG_ERR("Device ID read failed (%d)", ret);
+		return -ENODEV;
+	}
+
+	if (memcmp(dev_id, memory_cfg->readIdSettings.readIdExpected, sizeof(dev_id))) {
+		LOG_ERR("Device id does not match config");
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+static DEVICE_API(flash, nxp_s32_qspi_api) = {
+	.erase = nxp_s32_qspi_erase,
+	.write = nxp_s32_qspi_write,
+	.read = nxp_s32_qspi_read,
+	.get_parameters = nxp_s32_qspi_get_parameters,
+#if defined(CONFIG_FLASH_PAGE_LAYOUT)
+	.page_layout = nxp_s32_qspi_pages_layout,
+#endif /* CONFIG_FLASH_PAGE_LAYOUT */
+};
+
+#define QSPI_PAGE_LAYOUT(n)							\
+	.layout = {								\
+		.pages_count = (DT_INST_PROP(n, size) / 8)			\
+			/ CONFIG_FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE,		\
+		.pages_size = CONFIG_FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE,	\
+	}
+
+#define QSPI_READ_ID_CFG(n)							\
+	{									\
+		.readIdLut = QSPI_IP_HF_LUT_READ,				\
+		.readIdSize = DT_INST_PROP_LEN(n, jedec_id),			\
+		.readIdExpected = DT_INST_PROP(n, jedec_id),			\
+	}
+
+#define QSPI_MEMORY_CONN_CFG(n)							\
+	{									\
+		.connectionType = (Qspi_Ip_ConnectionType)DT_INST_REG_ADDR(n),	\
+		.memAlignment = DT_INST_PROP(n, write_block_size)		\
+	}
+
+#define QSPI_ERASE_CFG(n)							\
+	{									\
+		.eraseTypes = {							\
+			{							\
+				.eraseLut = QSPI_IP_HF_LUT_SE,			\
+				.size = 12, /* 4 KB */				\
+			},							\
+			{							\
+				.eraseLut = QSPI_IP_HF_LUT_SE,			\
+				.size = 18, /* 256 KB */			\
+			},							\
+			{							\
+				.eraseLut = QSPI_IP_LUT_INVALID,		\
+				.size = 0,					\
+			},							\
+			{							\
+				.eraseLut = QSPI_IP_LUT_INVALID,		\
+				.size = 0,					\
+			},							\
+		},								\
+		.chipEraseLut = QSPI_IP_HF_LUT_CE,				\
+	}
+
+#define QSPI_RESET_CFG(n)							\
+	{									\
+		.resetCmdLut = QSPI_IP_HF_LUT_RST,				\
+		.resetCmdCount = QSPI_IP_HF_RST_CNT,				\
+	}
+
+#define QSPI_STATUS_REG_CFG(n)							\
+	{									\
+		.statusRegInitReadLut = QSPI_IP_HF_LUT_RDSR,			\
+		.statusRegReadLut = QSPI_IP_HF_LUT_RDSR,			\
+		.statusRegWriteLut = QSPI_IP_LUT_INVALID,			\
+		.writeEnableSRLut = QSPI_IP_LUT_INVALID,			\
+		.writeEnableLut = QSPI_IP_LUT_INVALID,				\
+		.regSize = 1U,							\
+		.busyOffset = 0U,						\
+		.busyValue = 1U,						\
+		.writeEnableOffset = 1U,					\
+	}
+
+#define QSPI_INIT_CFG(n)							\
+	{									\
+		.opCount = 0U,							\
+		.operations = NULL,						\
+	}
+
+#define QSPI_LUT_CFG(n)								\
+	{									\
+		.opCount = QSPI_IP_HF_LUT_SIZE,					\
+		.lutOps = (Qspi_Ip_InstrOpType *)QSPI_IP_HF_LUT_NAME,		\
+	}
+
+#define QSPI_SUSPEND_CFG(n)							\
+	{									\
+		.eraseSuspendLut = QSPI_IP_HF_LUT_ES,				\
+		.eraseResumeLut = QSPI_IP_HF_LUT_ER,				\
+		.programSuspendLut = QSPI_IP_HF_LUT_PS,				\
+		.programResumeLut = QSPI_IP_HF_LUT_PR,				\
+	}
+
+#define QSPI_MEMORY_CFG(n)							\
+	{									\
+		.memType = QSPI_IP_HYPER_FLASH,					\
+		.hfConfig = &hyperflash_config_##n,				\
+		.memSize = DT_INST_PROP(n, size) / 8,				\
+		.pageSize = DT_INST_PROP(n, max_program_buffer_size),		\
+		.writeLut = QSPI_IP_HF_LUT_WRITE,				\
+		.readLut = QSPI_IP_HF_LUT_READ,					\
+		.read0xxLut = QSPI_IP_LUT_INVALID,				\
+		.read0xxLutAHB = QSPI_IP_LUT_INVALID,				\
+		.eraseSettings = QSPI_ERASE_CFG(n),				\
+		.statusConfig = QSPI_STATUS_REG_CFG(n),				\
+		.resetSettings = QSPI_RESET_CFG(n),				\
+		.initResetSettings = QSPI_RESET_CFG(n),				\
+		.initConfiguration = QSPI_INIT_CFG(n),				\
+		.lutSequences = QSPI_LUT_CFG(n),				\
+		.readIdSettings = QSPI_READ_ID_CFG(n),				\
+		.suspendSettings = QSPI_SUSPEND_CFG(n),				\
+		.initCallout = NULL,						\
+		.resetCallout = NULL,						\
+		.errorCheckCallout = NULL,					\
+		.eccCheckCallout = NULL,					\
+		.ctrlAutoCfgPtr = NULL,						\
+	}
+
+#define FLASH_NXP_S32_QSPI_DRV_STRENGTH(n)							\
+	COND_CODE_1(DT_INST_ENUM_IDX(n, vcc_mv),						\
+		(DT_INST_PROP(n, drive_strength_ohm) == 12 ? QSPI_IP_HF_DRV_STRENGTH_007 :	\
+		(DT_INST_PROP(n, drive_strength_ohm) == 14 ? QSPI_IP_HF_DRV_STRENGTH_006 :	\
+		(DT_INST_PROP(n, drive_strength_ohm) == 16 ? QSPI_IP_HF_DRV_STRENGTH_005 :	\
+		(DT_INST_PROP(n, drive_strength_ohm) == 20 ? QSPI_IP_HF_DRV_STRENGTH_000 :	\
+		(DT_INST_PROP(n, drive_strength_ohm) == 27 ? QSPI_IP_HF_DRV_STRENGTH_003 :	\
+		(DT_INST_PROP(n, drive_strength_ohm) == 40 ? QSPI_IP_HF_DRV_STRENGTH_002 :	\
+		(DT_INST_PROP(n, drive_strength_ohm) == 71 ? QSPI_IP_HF_DRV_STRENGTH_001 :	\
+		QSPI_IP_HF_DRV_STRENGTH_000))))))),						\
+		(DT_INST_PROP(n, drive_strength_ohm) == 20 ? QSPI_IP_HF_DRV_STRENGTH_007 :	\
+		(DT_INST_PROP(n, drive_strength_ohm) == 24 ? QSPI_IP_HF_DRV_STRENGTH_006 :	\
+		(DT_INST_PROP(n, drive_strength_ohm) == 27 ? QSPI_IP_HF_DRV_STRENGTH_000 :	\
+		(DT_INST_PROP(n, drive_strength_ohm) == 34 ? QSPI_IP_HF_DRV_STRENGTH_004 :	\
+		(DT_INST_PROP(n, drive_strength_ohm) == 45 ? QSPI_IP_HF_DRV_STRENGTH_003 :	\
+		(DT_INST_PROP(n, drive_strength_ohm) == 68 ? QSPI_IP_HF_DRV_STRENGTH_002 :	\
+		(DT_INST_PROP(n, drive_strength_ohm) == 117 ? QSPI_IP_HF_DRV_STRENGTH_001 :	\
+		QSPI_IP_HF_DRV_STRENGTH_000))))))))
+
+#define FLASH_NXP_S32_QSPI_SECTOR_MAP(n)							\
+	COND_CODE_1(DT_INST_PROP(n, support_only_uniform_sectors),				\
+		(DT_INST_ENUM_IDX(n, ppw_sectors_addr_mapping) ?				\
+			QSPI_IP_HF_UNIFORM_SECTORS_READ_PASSWORD_HIGH :				\
+			QSPI_IP_HF_UNIFORM_SECTORS_READ_PASSWORD_LOW),				\
+		(DT_INST_ENUM_IDX(n, ppw_sectors_addr_mapping) ?				\
+			QSPI_IP_HF_PARAM_AND_PASSWORD_MAP_HIGH :				\
+			QSPI_IP_HF_PARAM_AND_PASSWORD_MAP_LOW))
+
+#define FLASH_NXP_S32_QSPI_INIT_DEVICE(n)					\
+	static Qspi_Ip_HyperFlashConfigType hyperflash_config_##n =		\
+	{									\
+		.outputDriverStrength = FLASH_NXP_S32_QSPI_DRV_STRENGTH(n),	\
+		.RWDSLowOnDualError = DT_INST_PROP(n, rwds_low_dual_error),	\
+		.secureRegionUnlocked = !DT_INST_PROP(n, secure_region_locked),	\
+		.readLatency = DT_INST_ENUM_IDX(n, read_latency_cycles),	\
+		.paramSectorMap = FLASH_NXP_S32_QSPI_SECTOR_MAP(n),		\
+		.deviceIdWordAddress = DT_INST_PROP(n, device_id_word_addr),	\
+	};									\
+	static const struct nxp_s32_qspi_config nxp_s32_qspi_config_##n = {	\
+		.controller = DEVICE_DT_GET(DT_INST_BUS(n)),			\
+		.flash_parameters = {						\
+			.write_block_size = DT_INST_PROP(n, write_block_size),	\
+			.erase_value = QSPI_ERASE_VALUE,			\
+		},								\
+		IF_ENABLED(CONFIG_FLASH_PAGE_LAYOUT,				\
+			(QSPI_PAGE_LAYOUT(n),))					\
+		.memory_cfg = QSPI_MEMORY_CFG(n),				\
+	};									\
+										\
+	static struct nxp_s32_qspi_data nxp_s32_qspi_data_##n = {		\
+		.memory_conn_cfg = QSPI_MEMORY_CONN_CFG(n),			\
+	};									\
+										\
+	DEVICE_DT_INST_DEFINE(n,						\
+			      nxp_s32_qspi_init,				\
+			      NULL,						\
+			      &nxp_s32_qspi_data_##n,				\
+			      &nxp_s32_qspi_config_##n,				\
+			      POST_KERNEL,					\
+			      CONFIG_FLASH_INIT_PRIORITY,			\
+			      &nxp_s32_qspi_api);
+
+DT_INST_FOREACH_STATUS_OKAY(FLASH_NXP_S32_QSPI_INIT_DEVICE)
diff --git a/drivers/flash/flash_nxp_s32_qspi_nor.c b/drivers/flash/flash_nxp_s32_qspi_nor.c
index 9250b3ec0ea..b7c13290b3a 100644
--- a/drivers/flash/flash_nxp_s32_qspi_nor.c
+++ b/drivers/flash/flash_nxp_s32_qspi_nor.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2023 NXP
+ * Copyright 2023-2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,6 +19,7 @@ LOG_MODULE_REGISTER(nxp_s32_qspi_nor, CONFIG_FLASH_LOG_LEVEL);
 #include "jesd216.h"
 
 #include "memc_nxp_s32_qspi.h"
+#include "flash_nxp_s32_qspi.h"
 
 #define QSPI_INST_NODE_HAS_PROP_EQ_AND_OR(n, prop, val)				\
 	COND_CODE_1(DT_INST_NODE_HAS_PROP(n, prop),				\
@@ -55,52 +56,9 @@ LOG_MODULE_REGISTER(nxp_s32_qspi_nor, CONFIG_FLASH_LOG_LEVEL);
 		(_CONCAT(QSPI_SEQ_READ_, DT_INST_STRING_UPPER_TOKEN(n, readoc))),\
 		(QSPI_SEQ_READ_1_1_1))
 
-#define QSPI_ERASE_VALUE 0xff
-#define QSPI_WRITE_BLOCK_SIZE 1U
-
-#define QSPI_IS_ALIGNED(addr, bits) (((addr) & BIT_MASK(bits)) == 0)
-
 #define QSPI_LUT_ENTRY_SIZE (FEATURE_QSPI_LUT_SEQUENCE_SIZE * 2)
 #define QSPI_LUT_IDX(n)	(n * QSPI_LUT_ENTRY_SIZE)
 
-#if defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
-/* Size of LUT */
-#define QSPI_SFDP_LUT_SIZE 130U
-/* Size of init operations */
-#define QSPI_SFDP_INIT_OP_SIZE 8U
-#if defined(CONFIG_FLASH_JESD216_API)
-/* Size of all LUT sequences for JESD216 operations */
-#define QSPI_JESD216_SEQ_SIZE 8U
-#endif /* CONFIG_FLASH_JESD216_API */
-#endif /* CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME */
-
-struct nxp_s32_qspi_config {
-	const struct device *controller;
-	struct flash_parameters flash_parameters;
-#if defined(CONFIG_FLASH_PAGE_LAYOUT)
-	struct flash_pages_layout layout;
-#endif
-#if !defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
-	const Qspi_Ip_MemoryConfigType memory_cfg;
-	enum jesd216_dw15_qer_type qer_type;
-	bool quad_mode;
-#endif
-};
-
-struct nxp_s32_qspi_data {
-	uint8_t instance;
-	Qspi_Ip_MemoryConnectionType memory_conn_cfg;
-	uint8_t read_sfdp_lut_idx;
-#if defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
-	Qspi_Ip_MemoryConfigType memory_cfg;
-	Qspi_Ip_InstrOpType lut_ops[QSPI_SFDP_LUT_SIZE];
-	Qspi_Ip_InitOperationType init_ops[QSPI_SFDP_INIT_OP_SIZE];
-#endif
-#if defined(CONFIG_MULTITHREADING)
-	struct k_sem sem;
-#endif
-};
-
 enum {
 	QSPI_SEQ_RDSR,
 	QSPI_SEQ_RDSR2,
@@ -145,7 +103,7 @@ enum {
 #endif
 };
 
-#if !defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
+#if !defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME)
 static const Qspi_Ip_InstrOpType nxp_s32_qspi_lut[][QSPI_LUT_ENTRY_SIZE] = {
 	[QSPI_SEQ_RDSR] = {
 		QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_RDSR),
@@ -309,73 +267,9 @@ static const Qspi_Ip_InstrOpType nxp_s32_qspi_lut[][QSPI_LUT_ENTRY_SIZE] = {
 	},
 #endif
 };
-#endif /* !defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME) */
-
-static ALWAYS_INLINE Qspi_Ip_MemoryConfigType *get_memory_config(const struct device *dev)
-{
-#if defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
-	return &((struct nxp_s32_qspi_data *)dev->data)->memory_cfg;
-#else
-	return ((Qspi_Ip_MemoryConfigType *)
-		&((const struct nxp_s32_qspi_config *)dev->config)->memory_cfg);
-#endif
-}
-
-static ALWAYS_INLINE bool area_is_subregion(const struct device *dev, off_t offset, size_t size)
-{
-	Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev);
-
-	return ((offset >= 0) && (offset < memory_cfg->memSize)
-		&& ((size + offset) <= memory_cfg->memSize));
-}
-
-static inline void nxp_s32_qspi_lock(const struct device *dev)
-{
-#ifdef CONFIG_MULTITHREADING
-	struct nxp_s32_qspi_data *data = dev->data;
-
-	k_sem_take(&data->sem, K_FOREVER);
-#else
-	ARG_UNUSED(dev);
-#endif
-}
-
-static inline void nxp_s32_qspi_unlock(const struct device *dev)
-{
-#ifdef CONFIG_MULTITHREADING
-	struct nxp_s32_qspi_data *data = dev->data;
-
-	k_sem_give(&data->sem);
-#else
-	ARG_UNUSED(dev);
-#endif
-}
-
-/* Must be called with lock */
-static int nxp_s32_qspi_wait_until_ready(const struct device *dev)
-{
-	struct nxp_s32_qspi_data *data = dev->data;
-	Qspi_Ip_StatusType status;
-	uint32_t timeout = 0xFFFFFF;
-	int ret = 0;
-
-	do {
-		status = Qspi_Ip_GetMemoryStatus(data->instance);
-		timeout--;
-	} while ((status == STATUS_QSPI_IP_BUSY) && (timeout > 0));
-
-	if (status != STATUS_QSPI_IP_SUCCESS) {
-		LOG_ERR("Failed to read memory status (%d)", status);
-		ret = -EIO;
-	} else if (timeout <= 0) {
-		LOG_ERR("Timeout, memory is busy");
-		ret = -ETIMEDOUT;
-	}
-
-	return ret;
-}
+#endif /* !defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME) */
 
-#if !defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
+#if !defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME)
 static int nxp_s32_qspi_read_status_register(const struct device *dev,
 					     uint8_t reg_num,
 					     uint8_t *val)
@@ -565,210 +459,7 @@ static int nxp_s32_qspi_set_quad_mode(const struct device *dev, bool enabled)
 
 	return ret;
 }
-#endif /* !defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME) */
-
-static int nxp_s32_qspi_read(const struct device *dev, off_t offset, void *dest, size_t size)
-{
-	struct nxp_s32_qspi_data *data = dev->data;
-	Qspi_Ip_StatusType status;
-	int ret = 0;
-
-	if (!dest) {
-		return -EINVAL;
-	}
-
-	if (!area_is_subregion(dev, offset, size)) {
-		return -ENODEV;
-	}
-
-	if (size) {
-		nxp_s32_qspi_lock(dev);
-
-		status = Qspi_Ip_Read(data->instance, (uint32_t)offset, (uint8_t *)dest,
-				      (uint32_t)size);
-		if (status != STATUS_QSPI_IP_SUCCESS) {
-			LOG_ERR("Failed to read %zu bytes at 0x%lx (%d)",
-				size, offset, status);
-			ret = -EIO;
-		}
-
-		nxp_s32_qspi_unlock(dev);
-	}
-
-	return ret;
-}
-
-static int nxp_s32_qspi_write(const struct device *dev, off_t offset, const void *src, size_t size)
-{
-	struct nxp_s32_qspi_data *data = dev->data;
-	Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev);
-	Qspi_Ip_StatusType status;
-	size_t max_write = (size_t)MIN(QSPI_IP_MAX_WRITE_SIZE, memory_cfg->pageSize);
-	size_t len;
-	int ret = 0;
-
-	if (!src) {
-		return -EINVAL;
-	}
-
-	if (!area_is_subregion(dev, offset, size)) {
-		return -ENODEV;
-	}
-
-	nxp_s32_qspi_lock(dev);
-
-	while (size) {
-		len = MIN(max_write - (offset % max_write), size);
-		status = Qspi_Ip_Program(data->instance, (uint32_t)offset,
-					(const uint8_t *)src, (uint32_t)len);
-		if (status != STATUS_QSPI_IP_SUCCESS) {
-			LOG_ERR("Failed to write %zu bytes at 0x%lx (%d)",
-				len, offset, status);
-			ret = -EIO;
-			break;
-		}
-
-		ret = nxp_s32_qspi_wait_until_ready(dev);
-		if (ret != 0) {
-			break;
-		}
-
-		if (IS_ENABLED(CONFIG_FLASH_NXP_S32_QSPI_VERIFY_WRITE)) {
-			status = Qspi_Ip_ProgramVerify(data->instance, (uint32_t)offset,
-						       (const uint8_t *)src, (uint32_t)len);
-			if (status != STATUS_QSPI_IP_SUCCESS) {
-				LOG_ERR("Write verification failed at 0x%lx (%d)",
-					offset, status);
-				ret = -EIO;
-				break;
-			}
-		}
-
-		size -= len;
-		src = (const uint8_t *)src + len;
-		offset += len;
-	}
-
-	nxp_s32_qspi_unlock(dev);
-
-	return ret;
-}
-
-static int nxp_s32_qspi_erase_block(const struct device *dev, off_t offset,
-				    size_t size, size_t *erase_size)
-{
-	struct nxp_s32_qspi_data *data = dev->data;
-	Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev);
-	Qspi_Ip_EraseVarConfigType *etp = NULL;
-	Qspi_Ip_EraseVarConfigType *etp_tmp;
-	Qspi_Ip_StatusType status;
-	int ret = 0;
-
-	/*
-	 * Find the erase type with bigger size that can erase all or part of the
-	 * requested memory size
-	 */
-	for (uint8_t i = 0; i < QSPI_IP_ERASE_TYPES; i++) {
-		etp_tmp = (Qspi_Ip_EraseVarConfigType *)&(memory_cfg->eraseSettings.eraseTypes[i]);
-		if ((etp_tmp->eraseLut != QSPI_IP_LUT_INVALID)
-			&& QSPI_IS_ALIGNED(offset, etp_tmp->size)
-			&& (BIT(etp_tmp->size) <= size)
-			&& ((etp == NULL) || (etp_tmp->size > etp->size))) {
-
-			etp = etp_tmp;
-		}
-	}
-	if (etp != NULL) {
-		*erase_size = BIT(etp->size);
-		status = Qspi_Ip_EraseBlock(data->instance, (uint32_t)offset, *erase_size);
-		if (status != STATUS_QSPI_IP_SUCCESS) {
-			LOG_ERR("Failed to erase %zu bytes at 0x%lx (%d)",
-				*erase_size, (long)offset, status);
-			ret = -EIO;
-		}
-	} else {
-		LOG_ERR("Can't find erase size to erase %zu bytes", size);
-		ret = -EINVAL;
-	}
-
-	return ret;
-}
-
-static int nxp_s32_qspi_erase(const struct device *dev, off_t offset, size_t size)
-{
-	struct nxp_s32_qspi_data *data = dev->data;
-	Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev);
-	Qspi_Ip_StatusType status;
-	size_t erase_size;
-	int ret = 0;
-
-	if (!area_is_subregion(dev, offset, size)) {
-		return -ENODEV;
-	}
-
-	nxp_s32_qspi_lock(dev);
-
-	if (size == memory_cfg->memSize) {
-		status = Qspi_Ip_EraseChip(data->instance);
-		if (status != STATUS_QSPI_IP_SUCCESS) {
-			LOG_ERR("Failed to erase chip (%d)", status);
-			ret = -EIO;
-		}
-	} else {
-		while (size > 0) {
-			erase_size = 0;
-
-			ret = nxp_s32_qspi_erase_block(dev, offset, size, &erase_size);
-			if (ret != 0) {
-				break;
-			}
-
-			ret = nxp_s32_qspi_wait_until_ready(dev);
-			if (ret != 0) {
-				break;
-			}
-
-			if (IS_ENABLED(CONFIG_FLASH_NXP_S32_QSPI_VERIFY_ERASE)) {
-				status = Qspi_Ip_EraseVerify(data->instance, (uint32_t)offset,
-							erase_size);
-				if (status != STATUS_QSPI_IP_SUCCESS) {
-					LOG_ERR("Erase verification failed at 0x%lx (%d)",
-						offset, status);
-					ret = -EIO;
-					break;
-				}
-			}
-
-			offset += erase_size;
-			size -= erase_size;
-		}
-	}
-
-	nxp_s32_qspi_unlock(dev);
-
-	return ret;
-}
-
-#if defined(CONFIG_FLASH_JESD216_API) || !defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
-static int nxp_s32_qspi_read_id(const struct device *dev, uint8_t *id)
-{
-	struct nxp_s32_qspi_data *data = dev->data;
-	Qspi_Ip_StatusType status;
-	int ret = 0;
-
-	nxp_s32_qspi_lock(dev);
-
-	status = Qspi_Ip_ReadId(data->instance, id);
-	if (status != STATUS_QSPI_IP_SUCCESS) {
-		LOG_ERR("Failed to read device ID (%d)", status);
-		ret = -EIO;
-	}
-
-	nxp_s32_qspi_unlock(dev);
-
-	return ret;
-}
-#endif /* CONFIG_FLASH_JESD216_API || !CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME */
+#endif /* !defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME) */
 
 #if defined(CONFIG_FLASH_JESD216_API)
 static int nxp_s32_qspi_sfdp_read(const struct device *dev, off_t offset, void *buf, size_t len)
@@ -792,7 +483,7 @@ static int nxp_s32_qspi_sfdp_read(const struct device *dev, off_t offset, void *
 }
 #endif /* CONFIG_FLASH_JESD216_API */
 
-#if defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
+#if defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME)
 static int nxp_s32_qspi_sfdp_config(const struct device *dev)
 {
 	struct nxp_s32_qspi_data *data = dev->data;
@@ -852,36 +543,16 @@ static int nxp_s32_qspi_sfdp_config(const struct device *dev)
 }
 #endif
 
-static const struct flash_parameters *nxp_s32_qspi_get_parameters(const struct device *dev)
-{
-	const struct nxp_s32_qspi_config *config = dev->config;
-
-	return &config->flash_parameters;
-}
-
-#if defined(CONFIG_FLASH_PAGE_LAYOUT)
-static void nxp_s32_qspi_pages_layout(const struct device *dev,
-				const struct flash_pages_layout **layout,
-				size_t *layout_size)
-{
-	const struct nxp_s32_qspi_config *config = dev->config;
-
-	*layout = &config->layout;
-	*layout_size = 1;
-}
-#endif /* CONFIG_FLASH_PAGE_LAYOUT */
-
 static int nxp_s32_qspi_init(const struct device *dev)
 {
 	struct nxp_s32_qspi_data *data = dev->data;
 	const struct nxp_s32_qspi_config *config = dev->config;
 	Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev);
 	Qspi_Ip_StatusType status;
-	static uint8_t instance_cnt;
 	int ret = 0;
 
 	/* Used by the HAL to retrieve the internal driver state */
-	data->instance = instance_cnt++;
+	data->instance = nxp_s32_qspi_register_device();
 	__ASSERT_NO_MSG(data->instance < QSPI_IP_MEM_INSTANCE_COUNT);
 	data->memory_conn_cfg.qspiInstance = memc_nxp_s32_qspi_get_instance(config->controller);
 
@@ -889,7 +560,7 @@ static int nxp_s32_qspi_init(const struct device *dev)
 	k_sem_init(&data->sem, 1, 1);
 #endif
 
-#if defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
+#if defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME)
 	nxp_s32_qspi_sfdp_config(dev);
 #endif
 
@@ -903,7 +574,7 @@ static int nxp_s32_qspi_init(const struct device *dev)
 	}
 
 
-#if !defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
+#if !defined(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME)
 	uint8_t jedec_id[JESD216_READ_ID_LEN];
 
 	/* Verify connectivity by reading the device ID */
@@ -930,7 +601,7 @@ static int nxp_s32_qspi_init(const struct device *dev)
 	if (ret < 0) {
 		return ret;
 	}
-#endif /* !CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME */
+#endif /* !CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME */
 
 	return ret;
 }
@@ -966,7 +637,7 @@ static DEVICE_API(flash, nxp_s32_qspi_api) = {
 #define QSPI_MEMORY_CONN_CFG(n)							\
 	{									\
 		.connectionType = (Qspi_Ip_ConnectionType)DT_INST_REG_ADDR(n),	\
-		.memAlignment = DT_INST_PROP_OR(n, memory_alignment, 1)		\
+		.memAlignment = DT_INST_PROP(n, write_block_size)		\
 	}
 
 #define QSPI_ERASE_CFG(n)							\
@@ -1037,7 +708,7 @@ static DEVICE_API(flash, nxp_s32_qspi_api) = {
 		.memType = QSPI_IP_SERIAL_FLASH,				\
 		.hfConfig = NULL,						\
 		.memSize = DT_INST_PROP(n, size) / 8,				\
-		.pageSize = CONFIG_FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE,		\
+		.pageSize = DT_INST_PROP(n, max_program_buffer_size),		\
 		.writeLut = QSPI_LUT_IDX(QSPI_WRITE_SEQ(n)),			\
 		.readLut = QSPI_LUT_IDX(QSPI_READ_SEQ(n)),			\
 		.read0xxLut = QSPI_IP_LUT_INVALID,				\
@@ -1048,7 +719,7 @@ static DEVICE_API(flash, nxp_s32_qspi_api) = {
 		.initResetSettings = QSPI_RESET_CFG(n),				\
 		.initConfiguration = QSPI_INIT_CFG(n),				\
 		.lutSequences = QSPI_LUT_CFG(n),				\
-		COND_CODE_1(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME, (), (	\
+		COND_CODE_1(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME, (), (	\
 			.readIdSettings = QSPI_READ_ID_CFG(n),)			\
 		)								\
 		.suspendSettings = {						\
@@ -1065,7 +736,7 @@ static DEVICE_API(flash, nxp_s32_qspi_api) = {
 	}
 
 #define FLASH_NXP_S32_QSPI_INIT_DEVICE(n)					\
-	COND_CODE_1(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME, (), (		\
+	COND_CODE_1(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME, (), (		\
 		BUILD_ASSERT(DT_INST_NODE_HAS_PROP(n, jedec_id),		\
 			"jedec-id is required for non-runtime SFDP");		\
 		BUILD_ASSERT(DT_INST_PROP_LEN(n, jedec_id) == JESD216_READ_ID_LEN,\
@@ -1075,12 +746,12 @@ static DEVICE_API(flash, nxp_s32_qspi_api) = {
 	static const struct nxp_s32_qspi_config nxp_s32_qspi_config_##n = {	\
 		.controller = DEVICE_DT_GET(DT_INST_BUS(n)),			\
 		.flash_parameters = {						\
-			.write_block_size = QSPI_WRITE_BLOCK_SIZE,		\
+			.write_block_size = DT_INST_PROP(n, write_block_size),	\
 			.erase_value = QSPI_ERASE_VALUE,			\
 		},								\
 		IF_ENABLED(CONFIG_FLASH_PAGE_LAYOUT,				\
 			(QSPI_PAGE_LAYOUT(n),))					\
-		COND_CODE_1(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME, (), (	\
+		COND_CODE_1(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME, (), (	\
 			.memory_cfg = QSPI_MEMORY_CFG(n),			\
 			.qer_type = QSPI_QER_TYPE(n),				\
 			.quad_mode = QSPI_HAS_QUAD_MODE(n)			\
@@ -1089,7 +760,7 @@ static DEVICE_API(flash, nxp_s32_qspi_api) = {
 										\
 	static struct nxp_s32_qspi_data nxp_s32_qspi_data_##n = {		\
 		.memory_conn_cfg = QSPI_MEMORY_CONN_CFG(n),			\
-		COND_CODE_1(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME, (), (	\
+		COND_CODE_1(CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME, (), (	\
 			.read_sfdp_lut_idx = QSPI_LUT_IDX(QSPI_SEQ_READ_SFDP),	\
 		))								\
 	};									\
diff --git a/drivers/flash/flash_sam.c b/drivers/flash/flash_sam.c
index ba439bdec33..bb248fdf38e 100644
--- a/drivers/flash/flash_sam.c
+++ b/drivers/flash/flash_sam.c
@@ -396,17 +396,12 @@ static bool sam_flash_erase_foreach_page(const struct flash_pages_info *info, vo
 	/* Check if we've reached the end of pages to erase */
 	if (info->start_offset >= erase_data->section_end) {
 		/* Succeeded, stop iterating */
-		erase_data->succeeded = true;
 		return false;
 	}
 
-	if (sam_flash_unlock_page(dev, info) < 0) {
-		/* Failed to unlock page, stop iterating */
-		return false;
-	}
-
-	if (sam_flash_erase_page(dev, info) < 0) {
-		/* Failed to erase page, stop iterating */
+	if (sam_flash_unlock_page(dev, info) || sam_flash_erase_page(dev, info)) {
+		/* Failed to unlock page and erase page, stop iterating */
+		erase_data->succeeded = false;
 		return false;
 	}
 
@@ -436,7 +431,7 @@ static int sam_flash_erase(const struct device *dev, off_t offset, size_t size)
 	key = k_spin_lock(&sam_data->lock);
 	sam_data->erase_data.section_start = offset;
 	sam_data->erase_data.section_end = offset + size;
-	sam_data->erase_data.succeeded = false;
+	sam_data->erase_data.succeeded = true;
 	flash_page_foreach(dev, sam_flash_erase_foreach_page, sam_data);
 	if (!sam_data->erase_data.succeeded) {
 		k_spin_unlock(&sam_data->lock, key);
diff --git a/drivers/flash/flash_shell.c b/drivers/flash/flash_shell.c
index 061c4990142..068a108fc91 100644
--- a/drivers/flash/flash_shell.c
+++ b/drivers/flash/flash_shell.c
@@ -736,9 +736,14 @@ static void device_name_get(size_t idx, struct shell_static_entry *entry);
 
 SHELL_DYNAMIC_CMD_CREATE(dsub_device_name, device_name_get);
 
+static bool device_is_flash(const struct device *dev)
+{
+	return DEVICE_API_IS(flash, dev);
+}
+
 static void device_name_get(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_lookup(idx, NULL);
+	const struct device *dev = shell_device_filter(idx, device_is_flash);
 
 	entry->syntax = (dev != NULL) ? dev->name : NULL;
 	entry->handler = NULL;
diff --git a/drivers/flash/flash_stm32.c b/drivers/flash/flash_stm32.c
index c79b80bb0f5..c07ccd9d056 100644
--- a/drivers/flash/flash_stm32.c
+++ b/drivers/flash/flash_stm32.c
@@ -42,7 +42,7 @@ static const struct flash_parameters flash_stm32_parameters = {
 #endif
 };
 
-static int flash_stm32_write_protection(const struct device *dev, bool enable);
+static int flash_stm32_cr_lock(const struct device *dev, bool enable);
 
 bool __weak flash_stm32_valid_range(const struct device *dev, off_t offset,
 				    uint32_t len, bool write)
@@ -175,14 +175,14 @@ static int flash_stm32_erase(const struct device *dev, off_t offset,
 
 	LOG_DBG("Erase offset: %ld, len: %zu", (long int) offset, len);
 
-	rc = flash_stm32_write_protection(dev, false);
+	rc = flash_stm32_cr_lock(dev, false);
 	if (rc == 0) {
 		rc = flash_stm32_block_erase_loop(dev, offset, len);
 	}
 
 	flash_stm32_flush_caches(dev, offset, len);
 
-	int rc2 = flash_stm32_write_protection(dev, true);
+	int rc2 = flash_stm32_cr_lock(dev, true);
 
 	if (!rc) {
 		rc = rc2;
@@ -212,12 +212,12 @@ static int flash_stm32_write(const struct device *dev, off_t offset,
 
 	LOG_DBG("Write offset: %ld, len: %zu", (long int) offset, len);
 
-	rc = flash_stm32_write_protection(dev, false);
+	rc = flash_stm32_cr_lock(dev, false);
 	if (rc == 0) {
 		rc = flash_stm32_write_range(dev, offset, data, len);
 	}
 
-	int rc2 = flash_stm32_write_protection(dev, true);
+	int rc2 = flash_stm32_cr_lock(dev, true);
 
 	if (!rc) {
 		rc = rc2;
@@ -228,7 +228,7 @@ static int flash_stm32_write(const struct device *dev, off_t offset,
 	return rc;
 }
 
-static int flash_stm32_write_protection(const struct device *dev, bool enable)
+static int flash_stm32_cr_lock(const struct device *dev, bool enable)
 {
 	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
 
@@ -304,7 +304,7 @@ int flash_stm32_option_bytes_lock(const struct device *dev, bool enable)
 
 	/* Unlock CR/PECR/NSCR register if needed. */
 	if (!enable) {
-		rc = flash_stm32_write_protection(dev, false);
+		rc = flash_stm32_cr_lock(dev, false);
 		if (rc) {
 			return rc;
 		}
@@ -347,7 +347,7 @@ int flash_stm32_option_bytes_lock(const struct device *dev, bool enable)
 #endif
 	/* Lock CR/PECR/NSCR register if needed. */
 	if (enable) {
-		rc = flash_stm32_write_protection(dev, true);
+		rc = flash_stm32_cr_lock(dev, true);
 		if (rc) {
 			return rc;
 		}
diff --git a/drivers/flash/flash_stm32.h b/drivers/flash/flash_stm32.h
index 01d0c21d3f5..3480f152b4c 100644
--- a/drivers/flash/flash_stm32.h
+++ b/drivers/flash/flash_stm32.h
@@ -131,7 +131,12 @@ struct flash_stm32_priv {
 #define FLASH_STM32_NSPNB_POS FLASH_NSCR1_PNB_Pos
 #define FLASH_STM32_NSPNB FLASH_NSCR1_PNB
 #define FLASH_STM32_NSSTRT FLASH_NSCR1_STRT
+/* STM32WBA6x has DUAL bank flash */
+#if defined(FLASH_OPTR_DUAL_BANK)
+#define FLASH_STM32_DBANK FLASH_OPTR_DUAL_BANK
+#endif /* FLASH_OPTR_DUAL_BANK */
 #endif /* CONFIG_SOC_SERIES_STM32U5X */
+
 #if defined(FLASH_OPTR_DBANK)
 #define FLASH_STM32_DBANK FLASH_OPTR_DBANK
 #endif /* FLASH_OPTR_DBANK */
diff --git a/drivers/flash/flash_stm32_ospi.c b/drivers/flash/flash_stm32_ospi.c
index 1057ee56635..3c9fe5e542a 100644
--- a/drivers/flash/flash_stm32_ospi.c
+++ b/drivers/flash/flash_stm32_ospi.c
@@ -2103,6 +2103,21 @@ static int flash_stm32_ospi_init(const struct device *dev)
 	uint32_t prescaler = STM32_OSPI_CLOCK_PRESCALER_MIN;
 	int ret;
 
+	if (!device_is_ready(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE))) {
+		LOG_ERR("clock control device not ready");
+		return -ENODEV;
+	}
+
+#ifdef CONFIG_STM32_MEMMAP
+	/* If MemoryMapped then configure skip init */
+	if (stm32_ospi_is_memorymap(dev)) {
+		LOG_DBG("NOR init'd in MemMapped mode");
+		/* Force HAL instance in correct state */
+		dev_data->hospi.State = HAL_OSPI_STATE_BUSY_MEM_MAPPED;
+		return 0;
+	}
+#endif /* CONFIG_STM32_MEMMAP */
+
 	/* The SPI/DTR is not a valid config of data_mode/data_rate according to the DTS */
 	if ((dev_cfg->data_mode != OSPI_OPI_MODE)
 		&& (dev_cfg->data_rate == OSPI_DTR_TRANSFER)) {
@@ -2118,21 +2133,6 @@ static int flash_stm32_ospi_init(const struct device *dev)
 		return ret;
 	}
 
-	if (!device_is_ready(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE))) {
-		LOG_ERR("clock control device not ready");
-		return -ENODEV;
-	}
-
-#ifdef CONFIG_STM32_MEMMAP
-	/* If MemoryMapped then configure skip init */
-	if (stm32_ospi_is_memorymap(dev)) {
-		LOG_DBG("NOR init'd in MemMapped mode\n");
-		/* Force HAL instance in correct state */
-		dev_data->hospi.State = HAL_OSPI_STATE_BUSY_MEM_MAPPED;
-		return 0;
-	}
-#endif /* CONFIG_STM32_MEMMAP */
-
 #if STM32_OSPI_USE_DMA
 	/*
 	 * DMA configuration
@@ -2593,7 +2593,7 @@ static const struct flash_stm32_ospi_config flash_stm32_ospi_cfg = {
 		       .enr = DT_CLOCKS_CELL_BY_NAME(STM32_OSPI_NODE, ospi_mgr, bits)},
 #endif
 	.irq_config = flash_stm32_ospi_irq_config_func,
-	.flash_size = DT_INST_REG_ADDR_BY_IDX(0, 1),
+	.flash_size = DT_INST_REG_SIZE(0),
 	.max_frequency = DT_INST_PROP(0, ospi_max_frequency),
 	.data_mode = DT_INST_PROP(0, spi_bus_width), /* SPI or OPI */
 	.data_rate = DT_INST_PROP(0, data_rate), /* DTR or STR */
diff --git a/drivers/flash/flash_stm32_qspi.c b/drivers/flash/flash_stm32_qspi.c
index 83a98067bd7..d1d79854736 100644
--- a/drivers/flash/flash_stm32_qspi.c
+++ b/drivers/flash/flash_stm32_qspi.c
@@ -1617,7 +1617,7 @@ static const struct flash_stm32_qspi_config flash_stm32_qspi_cfg = {
 		.bus = DT_CLOCKS_CELL(STM32_QSPI_NODE, bus)
 	},
 	.irq_config = flash_stm32_qspi_irq_config_func,
-	.flash_size = DT_INST_REG_ADDR_BY_IDX(0, 1) << STM32_QSPI_DOUBLE_FLASH,
+	.flash_size = DT_INST_REG_SIZE(0) << STM32_QSPI_DOUBLE_FLASH,
 	.max_frequency = DT_INST_PROP(0, qspi_max_frequency),
 	.pcfg = PINCTRL_DT_DEV_CONFIG_GET(STM32_QSPI_NODE),
 #if STM32_QSPI_RESET_GPIO
diff --git a/drivers/flash/flash_stm32_xspi.c b/drivers/flash/flash_stm32_xspi.c
index 2eeef514393..29b352dee6b 100644
--- a/drivers/flash/flash_stm32_xspi.c
+++ b/drivers/flash/flash_stm32_xspi.c
@@ -190,7 +190,9 @@ static XSPI_RegularCmdTypeDef xspi_prepare_cmd(const uint8_t transfer_mode,
 		.DQSMode = (transfer_rate == XSPI_DTR_TRANSFER)
 				? HAL_XSPI_DQS_ENABLE
 				: HAL_XSPI_DQS_DISABLE,
+#ifdef XSPI_CCR_SIOO
 		.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD,
+#endif /* XSPI_CCR_SIOO */
 	};
 
 	switch (transfer_mode) {
@@ -773,7 +775,9 @@ static int stm32_xspi_mem_reset(const struct device *dev)
 		.DataLength = HAL_XSPI_DATA_NONE,
 		.DummyCycles = 0U,
 		.DQSMode = HAL_XSPI_DQS_DISABLE,
+#ifdef XSPI_CCR_SIOO
 		.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD,
+#endif /* XSPI_CCR_SIOO */
 	};
 
 	/* Reset enable in SPI mode and STR transfer mode */
@@ -1021,7 +1025,9 @@ static int flash_stm32_xspi_erase(const struct device *dev, off_t addr,
 		.DataMode = HAL_XSPI_DATA_NONE,
 		.DummyCycles = 0U,
 		.DQSMode = HAL_XSPI_DQS_DISABLE,
+#ifdef XSPI_CCR_SIOO
 		.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD,
+#endif /* XSPI_CCR_SIOO */
 	};
 
 	if (stm32_xspi_mem_ready(dev,
@@ -2019,6 +2025,21 @@ static int flash_stm32_xspi_init(const struct device *dev)
 	uint32_t prescaler = STM32_XSPI_CLOCK_PRESCALER_MIN;
 	int ret;
 
+	if (!device_is_ready(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE))) {
+		LOG_ERR("clock control device not ready");
+		return -ENODEV;
+	}
+
+#ifdef CONFIG_STM32_MEMMAP
+	/* If MemoryMapped then configure skip init */
+	if (stm32_xspi_is_memorymap(dev)) {
+		LOG_DBG("NOR init'd in MemMapped mode");
+		/* Force HAL instance in correct state */
+		dev_data->hxspi.State = HAL_XSPI_STATE_BUSY_MEM_MAPPED;
+		return 0;
+	}
+#endif /* CONFIG_STM32_MEMMAP */
+
 	/* The SPI/DTR is not a valid config of data_mode/data_rate according to the DTS */
 	if ((dev_cfg->data_mode != XSPI_OCTO_MODE)
 		&& (dev_cfg->data_rate == XSPI_DTR_TRANSFER)) {
@@ -2034,21 +2055,6 @@ static int flash_stm32_xspi_init(const struct device *dev)
 		return ret;
 	}
 
-	if (!device_is_ready(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE))) {
-		LOG_ERR("clock control device not ready");
-		return -ENODEV;
-	}
-
-#ifdef CONFIG_STM32_MEMMAP
-	/* If MemoryMapped then configure skip init */
-	if (stm32_xspi_is_memorymap(dev)) {
-		LOG_DBG("NOR init'd in MemMapped mode\n");
-		/* Force HAL instance in correct state */
-		dev_data->hxspi.State = HAL_XSPI_STATE_BUSY_MEM_MAPPED;
-		return 0;
-	}
-#endif /* CONFIG_STM32_MEMMAP */
-
 	if (dev_cfg->pclk_len > 3) {
 		/* Max 3 domain clock are expected */
 		LOG_ERR("Could not select %d XSPI domain clock", dev_cfg->pclk_len);
@@ -2121,11 +2127,13 @@ static int flash_stm32_xspi_init(const struct device *dev)
 	} else {
 
 	}
+#if defined(XSPI_DCR1_DLYBYP)
 #if STM32_XSPI_DLYB_BYPASSED
 	dev_data->hxspi.Init.DelayBlockBypass = HAL_XSPI_DELAY_BLOCK_BYPASS;
 #else
 	dev_data->hxspi.Init.DelayBlockBypass = HAL_XSPI_DELAY_BLOCK_ON;
 #endif /* STM32_XSPI_DLYB_BYPASSED */
+#endif /* XSPI_DCR1_DLYBYP */
 
 
 	if (HAL_XSPI_Init(&dev_data->hxspi) != HAL_OK) {
@@ -2405,7 +2413,7 @@ static const struct flash_stm32_xspi_config flash_stm32_xspi_cfg = {
 	.pclken = pclken,
 	.pclk_len = DT_NUM_CLOCKS(STM32_XSPI_NODE),
 	.irq_config = flash_stm32_xspi_irq_config_func,
-	.flash_size = DT_INST_REG_ADDR_BY_IDX(0, 1),
+	.flash_size = DT_INST_REG_SIZE(0),
 	.max_frequency = DT_INST_PROP(0, ospi_max_frequency),
 	.data_mode = DT_INST_PROP(0, spi_bus_width), /* SPI or OPI */
 	.data_rate = DT_INST_PROP(0, data_rate), /* DTR or STR */
diff --git a/drivers/flash/flash_stm32h7x.c b/drivers/flash/flash_stm32h7x.c
index 5999865fbc6..3873e9e1375 100644
--- a/drivers/flash/flash_stm32h7x.c
+++ b/drivers/flash/flash_stm32h7x.c
@@ -33,7 +33,9 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
 /* Let's wait for double the max erase time to be sure that the operation is
  * completed.
  */
-#define STM32H7_FLASH_TIMEOUT (2 * DT_PROP(DT_INST(0, st_stm32_nv_flash), max_erase_time))
+#define STM32H7_FLASH_TIMEOUT     (2 * DT_PROP(DT_INST(0, st_stm32_nv_flash), max_erase_time))
+/* No information in documentation about that. */
+#define STM32H7_FLASH_OPT_TIMEOUT_MS 800
 
 #define STM32H7_M4_FLASH_SIZE DT_PROP_OR(DT_INST(0, st_stm32_nv_flash), bank2_flash_size, 0)
 #ifdef CONFIG_CPU_CORTEX_M4
@@ -43,7 +45,7 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
 #define REAL_FLASH_SIZE_KB (KB(STM32H7_M4_FLASH_SIZE * 2))
 #endif
 #else
-#define REAL_FLASH_SIZE_KB KB(LL_GetFlashSize())
+#define REAL_FLASH_SIZE_KB DT_REG_SIZE(DT_INST(0, st_stm32_nv_flash))
 #endif
 #define SECTOR_PER_BANK ((REAL_FLASH_SIZE_KB / FLASH_SECTOR_SIZE) / 2)
 #if defined(DUAL_BANK)
@@ -53,6 +55,9 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
  * the serie, there is a discontinuty between bank1 and bank2.
  */
 #define DISCONTINUOUS_BANKS         (REAL_FLASH_SIZE_KB < STM32H7_SERIES_MAX_FLASH_KB)
+#define NUMBER_OF_BANKS             2
+#else
+#define NUMBER_OF_BANKS             1
 #endif
 
 struct flash_stm32_sector_t {
@@ -62,47 +67,76 @@ struct flash_stm32_sector_t {
 	volatile uint32_t *sr;
 };
 
-static __unused int write_optb(const struct device *dev, uint32_t mask,
-			       uint32_t value)
+#if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION) || defined(CONFIG_FLASH_STM32_WRITE_PROTECT)
+
+static int commit_optb(const struct device *dev)
 {
 	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
-	int rc;
+	int64_t timeout_time = k_uptime_get() + STM32H7_FLASH_OPT_TIMEOUT_MS;
+
+	/* Make sure previous write is completed before committing option bytes. */
+	barrier_dsync_fence_full();
+	regs->OPTCR |= FLASH_OPTCR_OPTSTART;
+	barrier_dsync_fence_full();
+	while (regs->OPTSR_CUR & FLASH_OPTSR_OPT_BUSY) {
+		if (k_uptime_get() > timeout_time) {
+			LOG_ERR("Timeout writing option bytes.");
+			return -ETIMEDOUT;
+		}
+	}
+
+	return 0;
+}
+
+/* Returns negative value on error, 0 if a change was not need, 1 if a change has been made. */
+static int write_opt(const struct device *dev, uint32_t mask, uint32_t value, uintptr_t cur,
+		     bool commit)
+{
+	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
+	/* PRG register always follows CUR register. */
+	uintptr_t prg = cur + 4;
+	int rc = 0;
 
 	if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) {
 		LOG_ERR("Option bytes locked");
 		return -EIO;
 	}
 
-	if ((regs->OPTCR & mask) == value) {
-		/* Done already */
-		return 0;
-	}
-
 	rc = flash_stm32_wait_flash_idle(dev);
 	if (rc < 0) {
 		LOG_ERR("Err flash no idle");
 		return rc;
 	}
 
-	regs->OPTCR = (regs->OPTCR & ~mask) | value;
-#ifdef CONFIG_SOC_SERIES_STM32H7RSX
-	regs->OPTCR |= FLASH_OPTCR_PG_OPT;
-#else
-	regs->OPTCR |= FLASH_OPTCR_OPTSTART;
-#endif /* CONFIG_SOC_SERIES_STM32H7RSX */
-	/* Make sure previous write is completed. */
-	barrier_dsync_fence_full();
+	if ((sys_read32(cur) & mask) == value) {
+		/* A change not needed, return 0. */
+		return 0;
+	}
 
-	rc = flash_stm32_wait_flash_idle(dev);
-	if (rc < 0) {
-		LOG_ERR("Err flash no idle");
-		return rc;
+	sys_write32((sys_read32(cur) & ~mask) | value, prg);
+
+	if (commit) {
+		rc = commit_optb(dev);
+		if (rc < 0) {
+			return rc;
+		}
 	}
 
-	return 0;
+	/* A change has been made, return 1. */
+	return 1;
 }
 
+#endif /* CONFIG_FLASH_STM32_WRITE_PROTECT || CONFIG_FLASH_STM32_READOUT_PROTECTION */
+
 #if defined(CONFIG_FLASH_STM32_READOUT_PROTECTION)
+static int write_optsr(const struct device *dev, uint32_t mask, uint32_t value)
+{
+	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
+	uintptr_t cur = (uintptr_t)regs + offsetof(FLASH_TypeDef, OPTSR_CUR);
+
+	return write_opt(dev, mask, value, cur, true);
+}
+
 uint8_t flash_stm32_get_rdp_level(const struct device *dev)
 {
 	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
@@ -112,11 +146,169 @@ uint8_t flash_stm32_get_rdp_level(const struct device *dev)
 
 void flash_stm32_set_rdp_level(const struct device *dev, uint8_t level)
 {
-	write_optb(dev, FLASH_OPTSR_RDP_Msk,
-		(uint32_t)level << FLASH_OPTSR_RDP_Pos);
+	write_optsr(dev, FLASH_OPTSR_RDP_Msk, (uint32_t)level << FLASH_OPTSR_RDP_Pos);
 }
 #endif /* CONFIG_FLASH_STM32_READOUT_PROTECTION */
 
+#if defined(CONFIG_FLASH_STM32_WRITE_PROTECT)
+
+#define WP_MSK FLASH_WPSN_WRPSN_Msk
+#define WP_POS FLASH_WPSN_WRPSN_Pos
+
+static int write_optwp(const struct device *dev, uint32_t mask, uint32_t value, uint32_t bank)
+{
+	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
+	uintptr_t cur = (uintptr_t)regs + offsetof(FLASH_TypeDef, WPSN_CUR1);
+
+	if (bank >= NUMBER_OF_BANKS) {
+		return -EINVAL;
+	}
+
+#ifdef DUAL_BANK
+	if (bank == 1) {
+		cur = (uintptr_t)regs + offsetof(FLASH_TypeDef, WPSN_CUR2);
+	}
+#endif /* DUAL_BANK */
+
+	return write_opt(dev, mask, value, cur, false);
+}
+
+int flash_stm32_update_wp_sectors(const struct device *dev, uint64_t changed_sectors,
+				  uint64_t protected_sectors)
+{
+	/* All banks share the same sector mask. */
+	const uint64_t bank_mask = WP_MSK >> WP_POS;
+	const uint32_t sectors_per_bank = __builtin_popcount(WP_MSK);
+	uint64_t sectors_mask = 0;
+	uint32_t protected_sectors_reg;
+	uint32_t changed_sectors_reg;
+	int ret, ret2 = 0;
+	bool commit = false;
+
+	for (int i = 0; i < NUMBER_OF_BANKS; i++) {
+		sectors_mask |= bank_mask << (sectors_per_bank * i);
+	}
+
+	if ((changed_sectors & sectors_mask) != changed_sectors) {
+		return -EINVAL;
+	}
+
+	for (int i = 0; i < NUMBER_OF_BANKS; i++) {
+		/* Prepare protected and changed masks per bank. */
+		protected_sectors_reg = (protected_sectors >> sectors_per_bank * i) & bank_mask;
+		changed_sectors_reg = (changed_sectors >> sectors_per_bank * i) & bank_mask;
+
+		if (changed_sectors_reg == 0) {
+			continue;
+		}
+		changed_sectors_reg <<= WP_POS;
+		protected_sectors_reg <<= WP_POS;
+		/* Sector is protected when bit == 0. Flip protected_sectors bits */
+		protected_sectors_reg = ~protected_sectors_reg;
+
+		ret = write_optwp(dev, changed_sectors_reg, protected_sectors_reg, i);
+		/* Option byte was successfully changed if the return value is greater than 0. */
+		if (ret > 0) {
+			commit = true;
+		} else if (ret < 0) {
+			/* Do not continue changing WP on error. */
+			ret2 = ret;
+			break;
+		}
+	}
+
+	if (commit) {
+		ret = commit_optb(dev);
+		/* Make sure to return the first error. */
+		if (ret < 0 && ret2 == 0) {
+			ret2 = ret;
+		}
+	}
+
+	return ret2;
+}
+
+int flash_stm32_get_wp_sectors(const struct device *dev, uint64_t *protected_sectors)
+{
+	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
+
+	*protected_sectors = (~regs->WPSN_CUR1 & WP_MSK) >> WP_POS;
+#ifdef DUAL_BANK
+	/* Available only for STM32H7x */
+	uint64_t proctected_sectors_2 =
+		(~regs->WPSN_CUR2 & WP_MSK) >> WP_POS;
+	const uint32_t sectors_per_bank = __builtin_popcount(WP_MSK);
+	*protected_sectors |= proctected_sectors_2 << sectors_per_bank;
+#endif /* DUAL_BANK */
+
+	return 0;
+}
+#endif /* CONFIG_FLASH_STM32_WRITE_PROTECT */
+
+#ifdef CONFIG_FLASH_STM32_BLOCK_REGISTERS
+int flash_stm32_control_register_disable(const struct device *dev)
+{
+	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
+
+	/*
+	 * Access to control register can be disabled by writing wrong key to
+	 * the key register. Option register will remain disabled until reset.
+	 * Writing wrong key causes a bus fault, so we need to set FAULTMASK to
+	 * disable faults, and clear bus fault pending bit before enabling them
+	 * again.
+	 */
+	regs->CR1 |= FLASH_CR_LOCK;
+#ifdef DUAL_BANK
+	regs->CR2 |= FLASH_CR_LOCK;
+#endif /* DUAL_BANK */
+
+	__set_FAULTMASK(1);
+	regs->KEYR1 = 0xffffffff;
+
+#ifdef DUAL_BANK
+	regs->KEYR2 = 0xffffffff;
+#endif /* DUAL_BANK */
+	/* Make sure that the fault occurs before we clear it. */
+	barrier_dsync_fence_full();
+
+	/* Clear Bus Fault pending bit */
+	SCB->SHCSR &= ~SCB_SHCSR_BUSFAULTPENDED_Msk;
+	/* Make sure to clear the fault before changing the fault mask. */
+	barrier_dsync_fence_full();
+
+	__set_FAULTMASK(0);
+
+	return 0;
+}
+
+int flash_stm32_option_bytes_disable(const struct device *dev)
+{
+	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
+
+	/*
+	 * Access to option register can be disabled by writing wrong key to
+	 * the key register. Option register will remain disabled until reset.
+	 * Writing wrong key causes a bus fault, so we need to set FAULTMASK to
+	 * disable faults, and clear bus fault pending bit before enabling them
+	 * again.
+	 */
+	regs->OPTCR |= FLASH_OPTCR_OPTLOCK;
+
+	__set_FAULTMASK(1);
+	regs->OPTKEYR = 0xffffffff;
+	/* Make sure that the fault occurs before we clear it. */
+	barrier_dsync_fence_full();
+
+	/* Clear Bus Fault pending bit */
+	SCB->SHCSR &= ~SCB_SHCSR_BUSFAULTPENDED_Msk;
+	/* Make sure to clear the fault before changing the fault mask. */
+	barrier_dsync_fence_full();
+	__set_FAULTMASK(0);
+
+	return 0;
+}
+#endif /* CONFIG_FLASH_STM32_BLOCK_REGISTERS */
+
 int flash_stm32_option_bytes_lock(const struct device *dev, bool enable)
 {
 	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
@@ -482,7 +674,7 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset, const
 	return rc;
 }
 
-static int flash_stm32h7_write_protection(const struct device *dev, bool enable)
+static int flash_stm32h7_cr_lock(const struct device *dev, bool enable)
 {
 	FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
 
@@ -561,7 +753,7 @@ static int flash_stm32h7_erase(const struct device *dev, off_t offset, size_t le
 
 	LOG_DBG("Erase offset: %ld, len: %zu", (long)offset, len);
 
-	rc = flash_stm32h7_write_protection(dev, false);
+	rc = flash_stm32h7_cr_lock(dev, false);
 	if (rc) {
 		goto done;
 	}
@@ -577,7 +769,7 @@ static int flash_stm32h7_erase(const struct device *dev, off_t offset, size_t le
 	}
 #endif /* CONFIG_CPU_CORTEX_M7 */
 done:
-	rc2 = flash_stm32h7_write_protection(dev, true);
+	rc2 = flash_stm32h7_cr_lock(dev, true);
 
 	if (!rc) {
 		rc = rc2;
@@ -605,12 +797,12 @@ static int flash_stm32h7_write(const struct device *dev, off_t offset, const voi
 
 	LOG_DBG("Write offset: %ld, len: %zu", (long)offset, len);
 
-	rc = flash_stm32h7_write_protection(dev, false);
+	rc = flash_stm32h7_cr_lock(dev, false);
 	if (!rc) {
 		rc = flash_stm32_write_range(dev, offset, data, len);
 	}
 
-	int rc2 = flash_stm32h7_write_protection(dev, true);
+	int rc2 = flash_stm32h7_cr_lock(dev, true);
 
 	if (!rc) {
 		rc = rc2;
diff --git a/drivers/flash/flash_stm32l5x.c b/drivers/flash/flash_stm32l5x.c
index 49e4259969f..1db7f0c4a91 100644
--- a/drivers/flash/flash_stm32l5x.c
+++ b/drivers/flash/flash_stm32l5x.c
@@ -11,6 +11,7 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
 
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
+#include <zephyr/cache.h>
 #include <string.h>
 #include <zephyr/drivers/flash.h>
 #include <zephyr/init.h>
@@ -20,105 +21,20 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
 
 #include "flash_stm32.h"
 
-#if defined(CONFIG_SOC_SERIES_STM32H5X)
-/* at this time stm32h5 mcus have 128KB (stm32h50x) or 2MB (stm32h56x/57x) */
-#define STM32_SERIES_MAX_FLASH	2048
-#elif defined(CONFIG_SOC_SERIES_STM32L5X)
-#define STM32_SERIES_MAX_FLASH	512
-#elif defined(CONFIG_SOC_SERIES_STM32U5X)
-/* It is used to handle the 2 banks discontinuity case, the discontinuity is not happen on STM32U5,
- *  so define it to flash size to avoid the unexptected check.
+#if defined(CONFIG_SOC_SERIES_STM32H5X) || defined(CONFIG_SOC_SERIES_STM32U5X)
+/*
+ * It is used to handle the 2 banks discontinuity case,
+ * so define it to flash size to avoid the unexpected check.
  */
 #define STM32_SERIES_MAX_FLASH	(CONFIG_FLASH_SIZE)
+#elif defined(CONFIG_SOC_SERIES_STM32L5X)
+#define STM32_SERIES_MAX_FLASH	512
 #endif
 
 #define PAGES_PER_BANK ((FLASH_SIZE / FLASH_PAGE_SIZE) / 2)
 
 #define BANK2_OFFSET	(KB(STM32_SERIES_MAX_FLASH) / 2)
 
-#define ICACHE_DISABLE_TIMEOUT_VALUE           1U   /* 1ms */
-#define ICACHE_INVALIDATE_TIMEOUT_VALUE        1U   /* 1ms */
-
-static int stm32_icache_disable(void)
-{
-	int status = 0;
-	uint32_t tickstart;
-
-	LOG_DBG("I-cache Disable");
-	/* Clear BSYENDF flag first and then disable the instruction cache
-	 * that starts a cache invalidation procedure
-	 */
-	CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
-
-	LL_ICACHE_Disable();
-
-	/* Get tick */
-	tickstart = k_uptime_get_32();
-
-	/* Wait for instruction cache to get disabled */
-	while (LL_ICACHE_IsEnabled()) {
-		if ((k_uptime_get_32() - tickstart) >
-						ICACHE_DISABLE_TIMEOUT_VALUE) {
-			/* New check to avoid false timeout detection in case
-			 * of preemption.
-			 */
-			if (LL_ICACHE_IsEnabled()) {
-				status = -ETIMEDOUT;
-				break;
-			}
-		}
-	}
-
-	return status;
-}
-
-static void stm32_icache_enable(void)
-{
-	LOG_DBG("I-cache Enable");
-	LL_ICACHE_Enable();
-}
-
-static int icache_wait_for_invalidate_complete(void)
-{
-	int status = -EIO;
-	uint32_t tickstart;
-
-	/* Check if ongoing invalidation operation */
-	if (LL_ICACHE_IsActiveFlag_BUSY()) {
-		/* Get tick */
-		tickstart = k_uptime_get_32();
-
-		/* Wait for end of cache invalidation */
-		while (!LL_ICACHE_IsActiveFlag_BSYEND()) {
-			if ((k_uptime_get_32() - tickstart) >
-					ICACHE_INVALIDATE_TIMEOUT_VALUE) {
-				break;
-			}
-		}
-	}
-
-	/* Clear any pending flags */
-	if (LL_ICACHE_IsActiveFlag_BSYEND()) {
-		LOG_DBG("I-cache Invalidation complete");
-
-		LL_ICACHE_ClearFlag_BSYEND();
-		status = 0;
-	} else {
-		LOG_ERR("I-cache Invalidation timeout");
-
-		status = -ETIMEDOUT;
-	}
-
-	if (LL_ICACHE_IsActiveFlag_ERR()) {
-		LOG_ERR("I-cache error");
-
-		LL_ICACHE_ClearFlag_ERR();
-		status = -EIO;
-	}
-
-	return status;
-}
-
 /* Macro to check if the flash is Dual bank or not */
 #if defined(CONFIG_SOC_SERIES_STM32H5X)
 #define stm32_flash_has_2_banks(flash_device) true
@@ -304,19 +220,16 @@ int flash_stm32_block_erase_loop(const struct device *dev,
 {
 	unsigned int address = offset;
 	int rc = 0;
-	bool icache_enabled = LL_ICACHE_IsEnabled();
 
-	if (icache_enabled) {
-		/* Disable icache, this will start the invalidation procedure.
-		 * All changes(erase/write) to flash memory should happen when
-		 * i-cache is disabled. A write to flash performed without
-		 * disabling i-cache will set ERRF error flag in SR register.
-		 */
-		rc = stm32_icache_disable();
-		if (rc != 0) {
-			return rc;
-		}
-	}
+	/* Disable icache, this will start the invalidation procedure.
+	 * All changes(erase/write) to flash memory should happen when
+	 * i-cache is disabled. A write to flash performed without
+	 * disabling i-cache will set ERRF error flag in SR register.
+	 */
+
+	bool cache_enabled = LL_ICACHE_IsEnabled();
+
+	sys_cache_instr_disable();
 
 	for (; address <= offset + len - 1 ; address += FLASH_PAGE_SIZE) {
 		rc = erase_page(dev, address);
@@ -325,16 +238,8 @@ int flash_stm32_block_erase_loop(const struct device *dev,
 		}
 	}
 
-	if (icache_enabled) {
-		/* Since i-cache was disabled, this would start the
-		 * invalidation procedure, so wait for completion.
-		 */
-		rc = icache_wait_for_invalidate_complete();
-
-		/* I-cache should be enabled only after the
-		 * invalidation is complete.
-		 */
-		stm32_icache_enable();
+	if (cache_enabled) {
+		sys_cache_instr_enable();
 	}
 
 	return rc;
@@ -344,19 +249,16 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
 			    const void *data, unsigned int len)
 {
 	int i, rc = 0;
-	bool icache_enabled = LL_ICACHE_IsEnabled();
 
-	if (icache_enabled) {
-		/* Disable icache, this will start the invalidation procedure.
-		 * All changes(erase/write) to flash memory should happen when
-		 * i-cache is disabled. A write to flash performed without
-		 * disabling i-cache will set ERRF error flag in SR register.
-		 */
-		rc = stm32_icache_disable();
-		if (rc != 0) {
-			return rc;
-		}
-	}
+	/* Disable icache, this will start the invalidation procedure.
+	 * All changes(erase/write) to flash memory should happen when
+	 * i-cache is disabled. A write to flash performed without
+	 * disabling i-cache will set ERRF error flag in SR register.
+	 */
+
+	bool cache_enabled = LL_ICACHE_IsEnabled();
+
+	sys_cache_instr_disable();
 
 	for (i = 0; i < len; i += FLASH_STM32_WRITE_BLOCK_SIZE) {
 		rc = write_nwords(dev, offset + i, ((const uint32_t *) data + (i>>2)),
@@ -366,22 +268,8 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
 		}
 	}
 
-	if (icache_enabled) {
-		int rc2;
-
-		/* Since i-cache was disabled, this would start the
-		 * invalidation procedure, so wait for completion.
-		 */
-		rc2 = icache_wait_for_invalidate_complete();
-
-		if (!rc) {
-			rc = rc2;
-		}
-
-		/* I-cache should be enabled only after the
-		 * invalidation is complete.
-		 */
-		stm32_icache_enable();
+	if (cache_enabled) {
+		sys_cache_instr_enable();
 	}
 
 	return rc;
diff --git a/drivers/flash/flash_stm32wba_fm.c b/drivers/flash/flash_stm32wba_fm.c
index 08838a147aa..8ebf1a35bd9 100644
--- a/drivers/flash/flash_stm32wba_fm.c
+++ b/drivers/flash/flash_stm32wba_fm.c
@@ -24,7 +24,7 @@ LOG_MODULE_REGISTER(flash_stm32wba, CONFIG_FLASH_LOG_LEVEL);
 #define STM32_FLASH_TIMEOUT	\
 	(2 * DT_PROP(DT_INST(0, st_stm32_nv_flash), max_erase_time))
 
-extern struct k_work_q ble_ctlr_work_q;
+extern struct k_work_q ble_ctrl_work_q;
 struct k_work fm_work;
 
 static const struct flash_parameters flash_stm32_parameters = {
@@ -47,7 +47,7 @@ struct FM_CallbackNode cb_ptr = {
 
 void FM_ProcessRequest(void)
 {
-	k_work_submit_to_queue(&ble_ctlr_work_q, &fm_work);
+	k_work_submit_to_queue(&ble_ctrl_work_q, &fm_work);
 }
 
 void FM_BackgroundProcess_Entry(struct k_work *work)
diff --git a/drivers/flash/flash_stm32wbax.c b/drivers/flash/flash_stm32wbax.c
index 8660d46c265..0065b36cee5 100644
--- a/drivers/flash/flash_stm32wbax.c
+++ b/drivers/flash/flash_stm32wbax.c
@@ -11,6 +11,7 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
 
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
+#include <zephyr/cache.h>
 #include <string.h>
 #include <zephyr/drivers/flash.h>
 #include <zephyr/init.h>
@@ -20,89 +21,47 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
 
 #include "flash_stm32.h"
 
+#if defined(FLASH_OPTR_DUAL_BANK)
+/* The stm32wba6x MCUs have 2MB dual-bank */
+#define STM32_SERIES_MAX_FLASH	2048
+#define STM32_FLASH_HAS_2_BANKS(flash_device) \
+	((FLASH_STM32_REGS(flash_device)->OPTR & FLASH_STM32_DBANK) \
+	== FLASH_STM32_DBANK)
+#else
 #define STM32_SERIES_MAX_FLASH	1024
+#define STM32_FLASH_HAS_2_BANKS(flash_device) (false)
+#endif /* FLASH_OPTR_DUAL_BANK */
 
-#define ICACHE_DISABLE_TIMEOUT_VALUE           1U   /* 1ms */
-#define ICACHE_INVALIDATE_TIMEOUT_VALUE        1U   /* 1ms */
+#define PAGES_PER_BANK ((FLASH_SIZE / FLASH_PAGE_SIZE) / 2)
 
-static int stm32_icache_disable(void)
-{
-	int status = 0;
-	uint32_t tickstart;
-
-	LOG_DBG("I-cache Disable");
-	/* Clear BSYENDF flag first and then disable the instruction cache
-	 * that starts a cache invalidation procedure
-	 */
-	CLEAR_BIT(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
-
-	LL_ICACHE_Disable();
-
-	/* Get tick */
-	tickstart = k_uptime_get_32();
-
-	/* Wait for instruction cache to get disabled */
-	while (LL_ICACHE_IsEnabled()) {
-		if ((k_uptime_get_32() - tickstart) >
-						ICACHE_DISABLE_TIMEOUT_VALUE) {
-			/* New check to avoid false timeout detection in case
-			 * of preemption.
-			 */
-			if (LL_ICACHE_IsEnabled()) {
-				status = -ETIMEDOUT;
-				break;
-			}
-		}
-	}
-
-	return status;
-}
+#define BANK2_OFFSET	(KB(STM32_SERIES_MAX_FLASH) / 2)
 
-static void stm32_icache_enable(void)
-{
-	LOG_DBG("I-cache Enable");
-	LL_ICACHE_Enable();
-}
-
-static int icache_wait_for_invalidate_complete(void)
+/*
+ * offset and len must be aligned on write-block-size for write,
+ * positive and not beyond end of flash
+ */
+bool flash_stm32_valid_range(const struct device *dev, off_t offset,
+			     uint32_t len, bool write)
 {
-	int status = -EIO;
-	uint32_t tickstart;
-
-	/* Check if ongoing invalidation operation */
-	if (LL_ICACHE_IsActiveFlag_BUSY()) {
-		/* Get tick */
-		tickstart = k_uptime_get_32();
-
-		/* Wait for end of cache invalidation */
-		while (!LL_ICACHE_IsActiveFlag_BSYEND()) {
-			if ((k_uptime_get_32() - tickstart) >
-					ICACHE_INVALIDATE_TIMEOUT_VALUE) {
-				break;
-			}
+	if (STM32_FLASH_HAS_2_BANKS(dev) &&
+			(CONFIG_FLASH_SIZE < STM32_SERIES_MAX_FLASH)) {
+		/*
+		 * In case of bank1/2 discontinuity, the range should not
+		 * start before bank2 and end beyond bank1 at the same time.
+		 * Locations beyond bank2 are caught by
+		 * flash_stm32_range_exists.
+		 */
+		if ((offset < BANK2_OFFSET) &&
+					(offset + len > FLASH_SIZE / 2)) {
+			return false;
 		}
 	}
 
-	/* Clear any pending flags */
-	if (LL_ICACHE_IsActiveFlag_BSYEND()) {
-		LOG_DBG("I-cache Invalidation complete");
-
-		LL_ICACHE_ClearFlag_BSYEND();
-		status = 0;
-	} else {
-		LOG_ERR("I-cache Invalidation timeout");
-
-		status = -ETIMEDOUT;
-	}
-
-	if (LL_ICACHE_IsActiveFlag_ERR()) {
-		LOG_ERR("I-cache error");
-
-		LL_ICACHE_ClearFlag_ERR();
-		status = -EIO;
+	if (write && !flash_stm32_valid_write(offset, len)) {
+		return false;
 	}
 
-	return status;
+	return flash_stm32_range_exists(dev, offset, len);
 }
 
 static int write_qword(const struct device *dev, off_t offset, const uint32_t *buff)
@@ -172,9 +131,40 @@ static int erase_page(const struct device *dev, unsigned int offset)
 		return rc;
 	}
 
+#if defined(FLASH_OPTR_DUAL_BANK)
+	bool bank_swap;
+	/* Check whether bank1/2 are swapped */
+	bank_swap =
+	((regs->OPTR & FLASH_OPTR_SWAP_BANK) == FLASH_OPTR_SWAP_BANK);
+
+	if ((offset < (FLASH_SIZE / 2)) && !bank_swap) {
+		/* The pages to be erased is in bank 1 */
+		regs->NSCR &= ~FLASH_STM32_NSBKER_MSK;
+		page = offset / FLASH_PAGE_SIZE;
+		LOG_DBG("Erase page %d on bank 1", page);
+	} else if ((offset >= BANK2_OFFSET) && bank_swap) {
+		/* The pages to be erased is in bank 1 */
+		regs->NSCR &= ~FLASH_STM32_NSBKER_MSK;
+		page = (offset - BANK2_OFFSET) / FLASH_PAGE_SIZE;
+		LOG_DBG("Erase page %d on bank 1", page);
+	} else if ((offset < (FLASH_SIZE / 2)) && bank_swap) {
+		/* The pages to be erased is in bank 2 */
+		regs->NSCR |= FLASH_STM32_NSBKER;
+		page = offset / FLASH_PAGE_SIZE;
+		LOG_DBG("Erase page %d on bank 2", page);
+	} else if ((offset >= BANK2_OFFSET) && !bank_swap) {
+		/* The pages to be erased is in bank 2 */
+		regs->NSCR |= FLASH_STM32_NSBKER;
+		page = (offset - BANK2_OFFSET) / FLASH_PAGE_SIZE;
+		LOG_DBG("Erase page %d on bank 2", page);
+	} else {
+		LOG_ERR("Offset %d does not exist", offset);
+		return -EINVAL;
+	}
+#else
 	page = offset / FLASH_PAGE_SIZE;
 	LOG_DBG("Erase page %d\n", page);
-
+#endif
 	/* Set the NSPER bit and select the page you wish to erase */
 	regs->NSCR |= FLASH_STM32_NSPER;
 	regs->NSCR &= ~FLASH_STM32_NSPNB_MSK;
@@ -200,19 +190,15 @@ int flash_stm32_block_erase_loop(const struct device *dev,
 {
 	unsigned int address = offset;
 	int rc = 0;
-	bool icache_enabled = LL_ICACHE_IsEnabled();
 
-	if (icache_enabled) {
-		/* Disable icache, this will start the invalidation procedure.
-		 * All changes(erase/write) to flash memory should happen when
-		 * i-cache is disabled. A write to flash performed without
-		 * disabling i-cache will set ERRF error flag in SR register.
-		 */
-		rc = stm32_icache_disable();
-		if (rc != 0) {
-			return rc;
-		}
-	}
+	/* Disable icache, this will start the invalidation procedure.
+	 * All changes(erase/write) to flash memory should happen when
+	 * i-cache is disabled. A write to flash performed without
+	 * disabling i-cache will set ERRF error flag in SR register.
+	 */
+	bool cache_enabled = LL_ICACHE_IsEnabled();
+
+	sys_cache_instr_disable();
 
 	for (; address <= offset + len - 1 ; address += FLASH_PAGE_SIZE) {
 		rc = erase_page(dev, address);
@@ -221,16 +207,8 @@ int flash_stm32_block_erase_loop(const struct device *dev,
 		}
 	}
 
-	if (icache_enabled) {
-		/* Since i-cache was disabled, this would start the
-		 * invalidation procedure, so wait for completion.
-		 */
-		rc = icache_wait_for_invalidate_complete();
-
-		/* I-cache should be enabled only after the
-		 * invalidation is complete.
-		 */
-		stm32_icache_enable();
+	if (cache_enabled) {
+		sys_cache_instr_enable();
 	}
 
 	return rc;
@@ -240,19 +218,15 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
 			    const void *data, unsigned int len)
 {
 	int i, rc = 0;
-	bool icache_enabled = LL_ICACHE_IsEnabled();
 
-	if (icache_enabled) {
-		/* Disable icache, this will start the invalidation procedure.
-		 * All changes(erase/write) to flash memory should happen when
-		 * i-cache is disabled. A write to flash performed without
-		 * disabling i-cache will set ERRF error flag in SR register.
-		 */
-		rc = stm32_icache_disable();
-		if (rc != 0) {
-			return rc;
-		}
-	}
+	/* Disable icache, this will start the invalidation procedure.
+	 * All changes(erase/write) to flash memory should happen when
+	 * i-cache is disabled. A write to flash performed without
+	 * disabling i-cache will set ERRF error flag in SR register.
+	 */
+	bool cache_enabled = LL_ICACHE_IsEnabled();
+
+	sys_cache_instr_disable();
 
 	for (i = 0; i < len; i += 16) {
 		rc = write_qword(dev, offset + i, ((const uint32_t *) data + (i>>2)));
@@ -261,27 +235,62 @@ int flash_stm32_write_range(const struct device *dev, unsigned int offset,
 		}
 	}
 
-	if (icache_enabled) {
-		int rc2;
+	if (cache_enabled) {
+		sys_cache_instr_enable();
+	}
 
-		/* Since i-cache was disabled, this would start the
-		 * invalidation procedure, so wait for completion.
-		 */
-		rc2 = icache_wait_for_invalidate_complete();
+	return rc;
+}
 
-		if (!rc) {
-			rc = rc2;
-		}
+#if defined(FLASH_OPTR_DUAL_BANK)
+/* The STM32WBA6x has a dual-bank flash */
+void flash_stm32_page_layout(const struct device *dev,
+			     const struct flash_pages_layout **layout,
+			     size_t *layout_size)
+{
+	static struct flash_pages_layout stm32_flash_layout[3];
+	static size_t stm32_flash_layout_size;
+
+	*layout = stm32_flash_layout;
+
+	if (stm32_flash_layout[0].pages_count != 0) {
+		/* Short circuit calculation logic if already performed (size is known) */
+		*layout_size = stm32_flash_layout_size;
+		return;
+	}
+
+	if (STM32_FLASH_HAS_2_BANKS(dev) &&
+			(CONFIG_FLASH_SIZE < STM32_SERIES_MAX_FLASH)) {
+		/* For device, which has space between banks 1 and 2 */
+
+		/* Bank1 */
+		stm32_flash_layout[0].pages_count = PAGES_PER_BANK;
+		stm32_flash_layout[0].pages_size = FLASH_PAGE_SIZE;
 
-		/* I-cache should be enabled only after the
-		 * invalidation is complete.
+		/* Dummy page corresponding to space between banks 1 and 2 */
+		stm32_flash_layout[1].pages_count = 1;
+		stm32_flash_layout[1].pages_size = BANK2_OFFSET
+				- (PAGES_PER_BANK * FLASH_PAGE_SIZE);
+
+		/* Bank2 */
+		stm32_flash_layout[2].pages_count = PAGES_PER_BANK;
+		stm32_flash_layout[2].pages_size = FLASH_PAGE_SIZE;
+
+		stm32_flash_layout_size = ARRAY_SIZE(stm32_flash_layout);
+	} else {
+		/*
+		 * For device, which has no space between banks 1 and 2
+		 * Considering one layout of full flash size, even with 2 banks
 		 */
-		stm32_icache_enable();
+		stm32_flash_layout[0].pages_count = FLASH_SIZE / FLASH_PAGE_SIZE;
+		stm32_flash_layout[0].pages_size = FLASH_PAGE_SIZE;
+
+		stm32_flash_layout_size = 1;
 	}
 
-	return rc;
+	*layout_size = stm32_flash_layout_size;
 }
-
+#else
 void flash_stm32_page_layout(const struct device *dev,
 			     const struct flash_pages_layout **layout,
 			     size_t *layout_size)
@@ -301,3 +310,4 @@ void flash_stm32_page_layout(const struct device *dev,
 	*layout = &stm32wba_flash_layout;
 	*layout_size = 1;
 }
+#endif /* FLASH_OPTR_DUAL_BANK */
diff --git a/drivers/flash/soc_flash_cc23x0.c b/drivers/flash/soc_flash_cc23x0.c
new file mode 100644
index 00000000000..dbcbad776ae
--- /dev/null
+++ b/drivers/flash/soc_flash_cc23x0.c
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/flash.h>
+#include <zephyr/irq.h>
+#include <zephyr/kernel.h>
+#include <string.h>
+
+#include <driverlib/flash.h>
+#include <driverlib/vims.h>
+
+#define DT_DRV_COMPAT     ti_cc23x0_flash_controller
+#define SOC_NV_FLASH_NODE DT_INST(0, soc_nv_flash)
+
+#define FLASH_ADDR       DT_REG_ADDR(SOC_NV_FLASH_NODE)
+#define FLASH_SIZE       DT_REG_SIZE(SOC_NV_FLASH_NODE)
+#define FLASH_ERASE_SIZE DT_PROP(SOC_NV_FLASH_NODE, erase_block_size)
+#define FLASH_WRITE_SIZE DT_PROP(SOC_NV_FLASH_NODE, write_block_size)
+
+struct flash_cc23x0_data {
+	struct k_sem mutex;
+};
+
+static const struct flash_parameters flash_cc23x0_parameters = {
+	.write_block_size = FLASH_WRITE_SIZE,
+	.erase_value = 0xff,
+};
+
+static int flash_cc23x0_init(const struct device *dev)
+{
+	struct flash_cc23x0_data *data = dev->data;
+
+	k_sem_init(&data->mutex, 1, 1);
+
+	return 0;
+}
+
+static void flash_cc23x0_cache_restore(uint32_t vims_mode)
+{
+	while (VIMSModeGet(VIMS_BASE) == VIMS_MODE_CHANGING) {
+		;
+	}
+
+	/* Restore VIMS mode and line buffers */
+	if (vims_mode != VIMS_MODE_DISABLED) {
+		VIMSModeSafeSet(VIMS_BASE, vims_mode, true);
+	}
+
+	VIMSLineBufEnable(VIMS_BASE);
+}
+
+static uint32_t flash_cc23x0_cache_disable(void)
+{
+	uint32_t vims_mode;
+
+	/* VIMS and both line buffers should be off during flash update */
+	VIMSLineBufDisable(VIMS_BASE);
+
+	while (VIMSModeGet(VIMS_BASE) == VIMS_MODE_CHANGING) {
+		;
+	}
+
+	/* Save current VIMS mode for restoring it later */
+	vims_mode = VIMSModeGet(VIMS_BASE);
+	if (vims_mode != VIMS_MODE_DISABLED) {
+		VIMSModeSafeSet(VIMS_BASE, VIMS_MODE_DISABLED, true);
+	}
+
+	return vims_mode;
+}
+
+static int flash_cc23x0_erase(const struct device *dev, off_t offs, size_t size)
+{
+	struct flash_cc23x0_data *data = dev->data;
+	uint32_t vims_mode;
+	unsigned int key;
+	int i;
+	int rc = 0;
+	size_t cnt;
+
+	if (!size) {
+		return 0;
+	}
+
+	/* Offset and length should be multiple of erase size */
+	if (((offs % FLASH_ERASE_SIZE) != 0) || ((size % FLASH_ERASE_SIZE) != 0)) {
+		return -EINVAL;
+	}
+
+	if (k_sem_take(&data->mutex, K_FOREVER)) {
+		return -EACCES;
+	}
+
+	vims_mode = flash_cc23x0_cache_disable();
+	/*
+	 * Disable all interrupts to prevent flash read, from TI's TRF:
+	 *
+	 * During a FLASH memory write or erase operation, the FLASH memory
+	 * must not be read.
+	 */
+	key = irq_lock();
+
+	/* Erase sector/page one by one, break out in case of an error */
+	cnt = size / FLASH_ERASE_SIZE;
+	for (i = 0; i < cnt; i++, offs += FLASH_ERASE_SIZE) {
+		while (FlashCheckFsmForReady() != FAPI_STATUS_FSM_READY) {
+			;
+		}
+
+		rc = FlashEraseSector(offs);
+		if (rc != FAPI_STATUS_SUCCESS) {
+			rc = -EIO;
+			break;
+		}
+	}
+
+	irq_unlock(key);
+
+	flash_cc23x0_cache_restore(vims_mode);
+
+	k_sem_give(&data->mutex);
+	return rc;
+}
+
+static int flash_cc23x0_write(const struct device *dev, off_t offs, const void *data, size_t size)
+{
+	struct flash_cc23x0_data *flash_data = dev->data;
+	uint32_t vims_mode;
+	unsigned int key;
+	int rc = 0;
+
+	if (!size) {
+		return 0;
+	}
+
+	if (offs < 0 || size < 1) {
+		return -EINVAL;
+	}
+
+	if (offs + size > FLASH_SIZE) {
+		return -EINVAL;
+	}
+
+	/*
+	 * From TI's HAL 'driverlib/flash.h':
+	 *
+	 * The pui8DataBuffer pointer can not point to flash.
+	 */
+	if ((data >= (void *)FLASH_ADDR) && (data <= (void *)(FLASH_ADDR + FLASH_SIZE))) {
+		return -EINVAL;
+	}
+
+	if (k_sem_take(&flash_data->mutex, K_FOREVER)) {
+		return -EACCES;
+	}
+
+	vims_mode = flash_cc23x0_cache_disable();
+
+	key = irq_lock();
+
+	while (FlashCheckFsmForReady() != FAPI_STATUS_FSM_READY) {
+		;
+	}
+
+	rc = FlashProgram((uint8_t *)data, offs, size);
+	if (rc != FAPI_STATUS_SUCCESS) {
+		rc = -EIO;
+	}
+
+	irq_unlock(key);
+
+	flash_cc23x0_cache_restore(vims_mode);
+
+	k_sem_give(&flash_data->mutex);
+
+	return rc;
+}
+
+static int flash_cc23x0_read(const struct device *dev, off_t offs, void *data, size_t size)
+{
+	ARG_UNUSED(dev);
+
+	if (!size) {
+		return 0;
+	}
+
+	if (offs < 0 || size < 1) {
+		return -EINVAL;
+	}
+
+	if (offs + size > FLASH_SIZE) {
+		return -EINVAL;
+	}
+
+	memcpy(data, (void *)offs, size);
+
+	return 0;
+}
+
+static const struct flash_parameters *flash_cc23x0_get_parameters(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return &flash_cc23x0_parameters;
+}
+
+#if defined(CONFIG_FLASH_PAGE_LAYOUT)
+static const struct flash_pages_layout dev_layout = {
+	.pages_count = FLASH_SIZE / FLASH_ERASE_SIZE,
+	.pages_size = FLASH_ERASE_SIZE,
+};
+
+static void flash_cc23x0_layout(const struct device *dev, const struct flash_pages_layout **layout,
+				size_t *layout_size)
+{
+	*layout = &dev_layout;
+	*layout_size = 1;
+}
+#endif /* CONFIG_FLASH_PAGE_LAYOUT */
+
+static DEVICE_API(flash, flash_cc23x0_api) = {
+	.erase = flash_cc23x0_erase,
+	.write = flash_cc23x0_write,
+	.read = flash_cc23x0_read,
+	.get_parameters = flash_cc23x0_get_parameters,
+#if defined(CONFIG_FLASH_PAGE_LAYOUT)
+	.page_layout = flash_cc23x0_layout,
+#endif
+};
+
+static struct flash_cc23x0_data cc23x0_flash_data;
+
+DEVICE_DT_INST_DEFINE(0, flash_cc23x0_init, NULL, &cc23x0_flash_data, NULL, POST_KERNEL,
+		      CONFIG_FLASH_INIT_PRIORITY, &flash_cc23x0_api);
diff --git a/drivers/flash/soc_flash_mcux.c b/drivers/flash/soc_flash_mcux.c
index 86a06cddff3..a09e79dfa6c 100644
--- a/drivers/flash/soc_flash_mcux.c
+++ b/drivers/flash/soc_flash_mcux.c
@@ -43,7 +43,7 @@ LOG_MODULE_REGISTER(flash_mcux);
 
 #if defined(SOC_HAS_IAP) && !defined(CONFIG_SOC_LPC55S36)
 #include "fsl_iap.h"
-#elif defined(CONFIG_SOC_MCXA156)
+#elif defined(CONFIG_SOC_SERIES_MCXA)
 #include "fsl_romapi.h"
 #define FLASH_Erase   FLASH_EraseSector
 #define FLASH_Program FLASH_ProgramPhrase
@@ -138,6 +138,11 @@ static void clear_flash_caches(void)
 	/* this bit clears the code cache */
 	*lpcac_ctrl |= BIT(1);
 }
+#elif CONFIG_SOC_SERIES_MCXA
+static void clear_flash_caches(void)
+{
+	SYSCON->LPCAC_CTRL |= SYSCON_LPCAC_CTRL_DIS_LPCAC(1U);
+}
 #else
 #undef SOC_FLASH_NEED_CLEAR_CACHES
 #define clear_flash_caches(...)
diff --git a/drivers/flash/soc_flash_nrf.h b/drivers/flash/soc_flash_nrf.h
index 6e6d9ad1089..24b899aaf29 100644
--- a/drivers/flash/soc_flash_nrf.h
+++ b/drivers/flash/soc_flash_nrf.h
@@ -25,6 +25,9 @@ struct flash_context {
 #if defined(CONFIG_SOC_FLASH_NRF_PARTIAL_ERASE)
 	uint32_t flash_addr_next;
 #endif /* CONFIG_SOC_FLASH_NRF_PARTIAL_ERASE */
+#if defined(CONFIG_SOC_FLASH_NRF_CUSTOM_CONTEXT)
+	void *custom_context;
+#endif
 }; /*< Context type for f. @ref write_op @ref erase_op */
 
 #ifndef CONFIG_SOC_FLASH_NRF_RADIO_SYNC_NONE
diff --git a/drivers/flash/soc_flash_silabs_series2.c b/drivers/flash/soc_flash_silabs_series2.c
new file mode 100644
index 00000000000..9b6e4968639
--- /dev/null
+++ b/drivers/flash/soc_flash_silabs_series2.c
@@ -0,0 +1,336 @@
+/*
+ * Copyright (c) 2018, Piotr Mienkowski
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT     silabs_series2_flash_controller
+#define SOC_NV_FLASH_NODE DT_INST(0, soc_nv_flash)
+
+#include <stddef.h>
+#include <string.h>
+#include <errno.h>
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/flash.h>
+#include <zephyr/drivers/dma.h>
+#include <soc.h>
+#include <em_msc.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(flash_silabs, CONFIG_FLASH_LOG_LEVEL);
+
+struct flash_silabs_data {
+	struct k_sem lock;
+#if defined(CONFIG_SOC_FLASH_SILABS_S2_DMA_WRITE) || defined(CONFIG_SOC_FLASH_SILABS_S2_DMA_READ)
+	const struct device *dma_dev;
+	uint32_t dma_channel;
+#endif
+#if defined(CONFIG_SOC_FLASH_SILABS_S2_DMA_READ)
+	struct k_sem sync;
+	int sync_status;
+	struct dma_config dma_cfg;
+	struct dma_block_config dma_block_cfg;
+#endif
+};
+
+struct flash_silabs_config {
+	struct flash_parameters flash_parameters;
+	struct flash_pages_layout page_layout;
+	bool lpwrite;
+};
+
+static bool flash_silabs_read_range_is_valid(off_t offset, uint32_t size)
+{
+	return (offset >= 0) && (offset < DT_REG_SIZE(SOC_NV_FLASH_NODE)) &&
+	       ((DT_REG_SIZE(SOC_NV_FLASH_NODE) - offset) >= size);
+}
+
+static bool flash_silabs_write_range_is_valid(off_t offset, uint32_t size)
+{
+	/* Note:
+	 * - A flash address to write to must be aligned to words.
+	 * - Number of bytes to write must be divisible by 4.
+	 */
+	return flash_silabs_read_range_is_valid(offset, size) &&
+	       IS_ALIGNED(offset, sizeof(uint32_t)) && IS_ALIGNED(size, 4);
+}
+
+static void flash_silabs_write_protection(bool enable)
+{
+	if (enable) {
+		/* Lock the MSC module. */
+		MSC->LOCK = 0;
+	} else {
+		/* Unlock the MSC module. */
+		MSC->LOCK = MSC_LOCK_LOCKKEY_UNLOCK;
+	}
+}
+
+#if defined(CONFIG_SOC_FLASH_SILABS_S2_DMA_READ)
+static void flash_silabs_read_callback(const struct device *dma_dev, void *user_data,
+				       uint32_t channel, int status)
+{
+	const struct device *dev = user_data;
+	struct flash_silabs_data *data = dev->data;
+
+	data->sync_status = status;
+	k_sem_give(&data->sync);
+}
+#endif
+
+static int flash_silabs_read_dma(const struct device *dev, off_t offset, void *data, size_t size)
+{
+#if defined(CONFIG_SOC_FLASH_SILABS_S2_DMA_READ)
+	struct flash_silabs_data *const dev_data = dev->data;
+	size_t data_size = 1;
+	int err;
+
+	if (IS_ALIGNED(offset, sizeof(uint32_t)) && IS_ALIGNED(data, sizeof(uint32_t)) &&
+	    IS_ALIGNED(size, 4)) {
+		data_size = 4;
+	}
+
+	k_sem_take(&dev_data->lock, K_FOREVER);
+
+	dev_data->dma_cfg.source_data_size = data_size;
+	dev_data->dma_cfg.dest_data_size = data_size;
+	dev_data->dma_cfg.source_burst_length = data_size;
+	dev_data->dma_cfg.dest_burst_length = data_size;
+
+	dev_data->dma_block_cfg = (struct dma_block_config){
+		.block_size = size,
+		.source_address = DT_REG_ADDR(SOC_NV_FLASH_NODE) + offset,
+		.dest_address = (uint32_t)data,
+	};
+
+	err = dma_config(dev_data->dma_dev, dev_data->dma_channel, &dev_data->dma_cfg);
+	if (err < 0) {
+		goto cleanup;
+	}
+
+	err = dma_start(dev_data->dma_dev, dev_data->dma_channel);
+	if (err < 0) {
+		goto cleanup;
+	}
+
+	k_sem_take(&dev_data->sync, K_FOREVER);
+	if (dev_data->sync_status != DMA_STATUS_COMPLETE) {
+		err = dev_data->sync_status;
+	}
+
+cleanup:
+	k_sem_give(&dev_data->lock);
+	return err;
+#else
+	return -ENOTSUP;
+#endif
+}
+
+static int flash_silabs_read(const struct device *dev, off_t offset, void *data, size_t size)
+{
+	if (!flash_silabs_read_range_is_valid(offset, size)) {
+		return -EINVAL;
+	}
+
+	if (!size) {
+		return 0;
+	}
+
+	if (IS_ENABLED(CONFIG_SOC_FLASH_SILABS_S2_DMA_READ)) {
+		return flash_silabs_read_dma(dev, offset, data, size);
+	}
+
+	memcpy(data, (uint8_t *)DT_REG_ADDR(SOC_NV_FLASH_NODE) + offset, size);
+
+	return 0;
+}
+
+static int flash_silabs_write(const struct device *dev, off_t offset, const void *data, size_t size)
+{
+	struct flash_silabs_data *const dev_data = dev->data;
+	void *address;
+	int ret = 0;
+
+	if (!flash_silabs_write_range_is_valid(offset, size)) {
+		return -EINVAL;
+	}
+
+	if (!size) {
+		return 0;
+	}
+
+	k_sem_take(&dev_data->lock, K_FOREVER);
+	flash_silabs_write_protection(false);
+
+	address = (uint8_t *)DT_REG_ADDR(SOC_NV_FLASH_NODE) + offset;
+#ifdef CONFIG_SOC_FLASH_SILABS_S2_DMA_WRITE
+	/* If the DMA channel has previously been used for a different purpose,
+	 * clear any lingering configuration that the MSC API doesn't tolerate.
+	 */
+	LDMA->IEN_CLR = BIT(dev_data->dma_channel);
+	LDMA->CHDONE_CLR = BIT(dev_data->dma_channel);
+	ret = MSC_WriteWordDma(dev_data->dma_channel, address, data, size);
+#else
+	ret = MSC_WriteWord(address, data, size);
+#endif
+	if (ret < 0) {
+		ret = -EIO;
+	}
+
+	flash_silabs_write_protection(true);
+	k_sem_give(&dev_data->lock);
+
+	return ret;
+}
+
+static int flash_silabs_erase_block(off_t offset, size_t size)
+{
+	void *address;
+	int ret = 0;
+
+	for (off_t tmp = offset; tmp < offset + size;
+	     tmp += DT_PROP(SOC_NV_FLASH_NODE, erase_block_size)) {
+		address = (uint8_t *)DT_REG_ADDR(SOC_NV_FLASH_NODE) + tmp;
+		ret = MSC_ErasePage(address);
+		if (ret < 0) {
+			ret = -EIO;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int flash_silabs_erase(const struct device *dev, off_t offset, size_t size)
+{
+	struct flash_silabs_data *const dev_data = dev->data;
+	int ret;
+
+	if (!flash_silabs_read_range_is_valid(offset, size)) {
+		return -EINVAL;
+	}
+
+	if (!IS_ALIGNED(offset, DT_PROP(SOC_NV_FLASH_NODE, erase_block_size))) {
+		LOG_ERR("offset 0x%lx: not on a page boundary", (long)offset);
+		return -EINVAL;
+	}
+
+	if (!IS_ALIGNED(size, DT_PROP(SOC_NV_FLASH_NODE, erase_block_size))) {
+		LOG_ERR("size %zu: not multiple of a page size", size);
+		return -EINVAL;
+	}
+
+	if (!size) {
+		return 0;
+	}
+
+	k_sem_take(&dev_data->lock, K_FOREVER);
+	flash_silabs_write_protection(false);
+
+	ret = flash_silabs_erase_block(offset, size);
+
+	flash_silabs_write_protection(true);
+	k_sem_give(&dev_data->lock);
+
+	return ret;
+}
+
+#if CONFIG_FLASH_PAGE_LAYOUT
+void flash_silabs_page_layout(const struct device *dev, const struct flash_pages_layout **layout,
+			      size_t *layout_size)
+{
+	const struct flash_silabs_config *const config = dev->config;
+
+	*layout = &config->page_layout;
+	*layout_size = 1;
+}
+#endif
+
+static const struct flash_parameters *flash_silabs_get_parameters(const struct device *dev)
+{
+	const struct flash_silabs_config *const config = dev->config;
+
+	return &config->flash_parameters;
+}
+
+static int flash_silabs_get_size(const struct device *dev, uint64_t *size)
+{
+	ARG_UNUSED(dev);
+
+	*size = (uint64_t)DT_REG_SIZE(SOC_NV_FLASH_NODE);
+
+	return 0;
+}
+
+static int flash_silabs_init(const struct device *dev)
+{
+	__maybe_unused struct flash_silabs_data *const dev_data = dev->data;
+	const struct flash_silabs_config *config = dev->config;
+
+	MSC_Init();
+
+	if (config->lpwrite) {
+		MSC->WRITECTRL_SET = MSC_WRITECTRL_LPWRITE;
+	}
+
+	/* Lock the MSC module. */
+	flash_silabs_write_protection(true);
+
+#if defined(CONFIG_SOC_FLASH_SILABS_S2_DMA_WRITE) || defined(CONFIG_SOC_FLASH_SILABS_S2_DMA_READ)
+	dev_data->dma_channel = dma_request_channel(dev_data->dma_dev, NULL);
+#endif
+
+	LOG_INF("Device %s initialized", dev->name);
+
+	return 0;
+}
+
+static DEVICE_API(flash, flash_silabs_driver_api) = {
+	.read = flash_silabs_read,
+	.write = flash_silabs_write,
+	.erase = flash_silabs_erase,
+	.get_parameters = flash_silabs_get_parameters,
+	.get_size = flash_silabs_get_size,
+#ifdef CONFIG_FLASH_PAGE_LAYOUT
+	.page_layout = flash_silabs_page_layout,
+#endif
+};
+
+/* clang-format off */
+static struct flash_silabs_data flash_silabs_data_0 = {
+	.lock = Z_SEM_INITIALIZER(flash_silabs_data_0.lock, 1, 1),
+#if defined(CONFIG_SOC_FLASH_SILABS_S2_DMA_WRITE) || defined(CONFIG_SOC_FLASH_SILABS_S2_DMA_READ)
+	.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR(0)),
+	.dma_channel = -1,
+#endif
+#if defined(CONFIG_SOC_FLASH_SILABS_S2_DMA_READ)
+	.sync = Z_SEM_INITIALIZER(flash_silabs_data_0.sync, 0, 1),
+	.sync_status = -EIO,
+	.dma_cfg = {
+		.channel_direction = MEMORY_TO_MEMORY,
+		.block_count = 1,
+		.head_block = &flash_silabs_data_0.dma_block_cfg,
+		.dma_callback = flash_silabs_read_callback,
+		.user_data = (void *)DEVICE_DT_INST_GET(0),
+	},
+#endif
+};
+
+static const struct flash_silabs_config flash_silabs_config_0 = {
+	.flash_parameters = {
+		.write_block_size = DT_PROP(SOC_NV_FLASH_NODE, write_block_size),
+		.erase_value = 0xff,
+	},
+	.page_layout = {
+		.pages_count = DT_REG_SIZE(SOC_NV_FLASH_NODE) /
+				DT_PROP(SOC_NV_FLASH_NODE, erase_block_size),
+		.pages_size = DT_PROP(SOC_NV_FLASH_NODE, erase_block_size),
+	},
+	.lpwrite = DT_INST_PROP(0, low_power_write),
+};
+/* clang-format on */
+
+DEVICE_DT_INST_DEFINE(0, flash_silabs_init, NULL, &flash_silabs_data_0, &flash_silabs_config_0,
+		      POST_KERNEL, CONFIG_FLASH_INIT_PRIORITY, &flash_silabs_driver_api);
diff --git a/drivers/flash/soc_flash_silabs_siwx91x.c b/drivers/flash/soc_flash_silabs_siwx91x.c
new file mode 100644
index 00000000000..9e714ce814d
--- /dev/null
+++ b/drivers/flash/soc_flash_silabs_siwx91x.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#define DT_DRV_COMPAT silabs_siwx91x_flash_controller
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/flash.h>
+#include <zephyr/logging/log.h>
+
+#include "sl_si91x_driver.h"
+
+LOG_MODULE_REGISTER(siwx91x_soc_flash);
+
+struct siwx91x_config {
+	uintptr_t base_address;
+	uint32_t size;
+	uint32_t write_block_size;
+	uint32_t erase_block_size;
+	struct flash_parameters flash_parameters;
+#ifdef CONFIG_FLASH_PAGE_LAYOUT
+	struct flash_pages_layout flash_pages_layout;
+#endif
+};
+
+struct siwx91x_data {
+	struct k_sem lock;
+};
+
+static bool flash_siwx91x_range_is_in_bounds(const struct device *dev, off_t offset, size_t len)
+{
+	const struct siwx91x_config *cfg = dev->config;
+
+	/* Note: If offset < __rom_region_end, the user to overwriting the current firmware. User
+	 * is probably doing a mistake, but not an error from this driver point of view.
+	 */
+	if (offset < 0) {
+		return false;
+	}
+	if (offset + len > cfg->size) {
+		return false;
+	}
+	return true;
+}
+
+static const struct flash_parameters *flash_siwx91x_get_parameters(const struct device *dev)
+{
+	const struct siwx91x_config *cfg = dev->config;
+
+	return &cfg->flash_parameters;
+}
+
+static int flash_siwx91x_read(const struct device *dev, off_t offset, void *buf, size_t len)
+{
+	const struct siwx91x_config *cfg = dev->config;
+	struct siwx91x_data *data = dev->data;
+	void *location = (void *)(cfg->base_address + offset);
+
+	if (!flash_siwx91x_range_is_in_bounds(dev, offset, len)) {
+		return -EINVAL;
+	}
+	k_sem_take(&data->lock, K_FOREVER);
+	memcpy(buf, location, len);
+	k_sem_give(&data->lock);
+	return 0;
+}
+
+static int flash_siwx91x_write(const struct device *dev, off_t offset, const void *buf, size_t len)
+{
+	const struct siwx91x_config *cfg = dev->config;
+	struct siwx91x_data *data = dev->data;
+	uint32_t ret;
+
+	if (!flash_siwx91x_range_is_in_bounds(dev, offset, len)) {
+		return -EINVAL;
+	}
+	if (offset % cfg->write_block_size) {
+		return -EINVAL;
+	}
+	if (len % cfg->write_block_size) {
+		return -EINVAL;
+	}
+	k_sem_take(&data->lock, K_FOREVER);
+	ret = sl_si91x_command_to_write_common_flash(cfg->base_address + offset, (void *)buf, len,
+						     false);
+	k_sem_give(&data->lock);
+	if (ret) {
+		return -EIO;
+	}
+	return 0;
+}
+
+static int flash_siwx91x_erase(const struct device *dev, off_t offset, size_t len)
+{
+	const struct siwx91x_config *cfg = dev->config;
+	struct siwx91x_data *data = dev->data;
+	uint32_t ret;
+
+	if (!flash_siwx91x_range_is_in_bounds(dev, offset, len)) {
+		return -EINVAL;
+	}
+	if (offset % cfg->erase_block_size) {
+		return -EINVAL;
+	}
+	if (len % cfg->erase_block_size) {
+		return -EINVAL;
+	}
+	k_sem_take(&data->lock, K_FOREVER);
+	ret = sl_si91x_command_to_write_common_flash(cfg->base_address + offset, NULL, len, true);
+	k_sem_give(&data->lock);
+	if (ret) {
+		return -EIO;
+	}
+	return 0;
+}
+
+#ifdef CONFIG_FLASH_PAGE_LAYOUT
+static void flash_siwx91x_page_layout(const struct device *dev,
+				      const struct flash_pages_layout **layout, size_t *layout_size)
+{
+	const struct siwx91x_config *cfg = dev->config;
+
+	*layout = &cfg->flash_pages_layout;
+	*layout_size = 1;
+}
+#endif
+
+static DEVICE_API(flash, siwx91x_api) = {
+	.read = flash_siwx91x_read,
+	.write = flash_siwx91x_write,
+	.erase = flash_siwx91x_erase,
+	.get_parameters = flash_siwx91x_get_parameters,
+#ifdef CONFIG_FLASH_PAGE_LAYOUT
+	.page_layout = flash_siwx91x_page_layout,
+#endif
+};
+
+static int flash_siwx91x_init(const struct device *dev)
+{
+	struct siwx91x_data *data = dev->data;
+
+	k_sem_init(&data->lock, 1, 1);
+	return 0;
+}
+
+#ifdef CONFIG_FLASH_PAGE_LAYOUT
+#define SIWX91X_PAGE_LAYOUT_FLASH_INIT(n)                                                          \
+	.flash_pages_layout.pages_count = DT_REG_SIZE(n) / DT_PROP(n, erase_block_size),           \
+	.flash_pages_layout.pages_size = DT_PROP(n, erase_block_size),
+#else
+#define SIWX91X_PAGE_LAYOUT_FLASH_INIT(n)
+#endif
+
+#define SIWX91X_FLASH_INIT_P(n, p)                                                                 \
+	static const struct siwx91x_config flash_siwx91x_config_##p = {                            \
+		.base_address = DT_REG_ADDR(n),                                                    \
+		.size = DT_REG_SIZE(n),                                                            \
+		.write_block_size = DT_PROP(n, write_block_size),                                  \
+		.erase_block_size = DT_PROP(n, erase_block_size),                                  \
+		.flash_parameters.write_block_size = DT_PROP(n, write_block_size),                 \
+		.flash_parameters.erase_value = 0xff,                                              \
+		SIWX91X_PAGE_LAYOUT_FLASH_INIT(n)                                                  \
+	};                                                \
+	static struct siwx91x_data flash_siwx91x_data_##p = {                                      \
+		.lock = Z_SEM_INITIALIZER(flash_siwx91x_data_##p.lock, 1, 1),                      \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(p, flash_siwx91x_init, NULL, &flash_siwx91x_data_##p,                \
+			      &flash_siwx91x_config_##p, POST_KERNEL, CONFIG_FLASH_INIT_PRIORITY,  \
+			      &siwx91x_api);
+
+#define SIWX91X_FLASH_INIT(p)                                                                      \
+	BUILD_ASSERT(DT_INST_CHILD_NUM_STATUS_OKAY(p) == 1);                                       \
+	DT_INST_FOREACH_CHILD_STATUS_OKAY_VARGS(p, SIWX91X_FLASH_INIT_P, p)
+
+DT_INST_FOREACH_STATUS_OKAY(SIWX91X_FLASH_INIT)
diff --git a/drivers/flash/spi_nor.c b/drivers/flash/spi_nor.c
index c9aa40c13c6..c02e77bf9a6 100644
--- a/drivers/flash/spi_nor.c
+++ b/drivers/flash/spi_nor.c
@@ -221,12 +221,17 @@ static const struct jesd216_erase_type minimal_erase_types_4b[JESD216_NUM_ERASE_
 };
 #endif /* CONFIG_SPI_NOR_SFDP_MINIMAL */
 
+
 /* Register writes should be ready extremely quickly */
 #define WAIT_READY_REGISTER K_NO_WAIT
 /* Page writes range from sub-ms to 10ms */
 #define WAIT_READY_WRITE K_TICKS(1)
-/* Erases can range from 45ms to 240sec */
-#define WAIT_READY_ERASE K_MSEC(50)
+
+#ifdef CONFIG_SPI_NOR_SLEEP_WHILE_WAITING_UNTIL_READY
+#define WAIT_READY_ERASE K_MSEC(CONFIG_SPI_NOR_SLEEP_ERASE_MS)
+#else
+#define WAIT_READY_ERASE K_NO_WAIT
+#endif
 
 static int spi_nor_write_protection_set(const struct device *dev,
 					bool write_protect);
@@ -300,12 +305,12 @@ static inline void record_entered_dpd(const struct device *const dev)
 #endif
 }
 
+#if ANY_INST_HAS_DPD
 /* Check the current time against the time DPD was entered and delay
  * until it's ok to initiate the DPD exit process.
  */
 static inline void delay_until_exit_dpd_ok(const struct device *const dev)
 {
-#if ANY_INST_HAS_DPD
 	const struct spi_nor_config *const driver_config = dev->config;
 
 	if (driver_config->dpd_exist) {
@@ -333,10 +338,8 @@ static inline void delay_until_exit_dpd_ok(const struct device *const dev)
 			}
 		}
 	}
-#else
-	ARG_UNUSED(dev);
-#endif /* ANY_INST_HAS_DPD */
 }
+#endif /* ANY_INST_HAS_DPD */
 
 /* Indicates that an access command includes bytes for the address.
  * If not provided the opcode is not followed by address bytes.
@@ -1136,13 +1139,26 @@ static int spi_nor_set_address_mode(const struct device *dev,
 
 	/* This currently only supports command 0xB7 (Enter 4-Byte
 	 * Address Mode), with or without preceding WREN.
+	 * Or when BIT(3) is set where the 4-byte address mode can be entered
+	 * by setting BIT(7) in a register via a 0x17 write
+	 * instruction. See JEDEC 216F 16th DWORD.
 	 */
-	if ((enter_4byte_addr & 0x03) == 0) {
+	if ((enter_4byte_addr & 0x0b) == 0) {
 		return -ENOTSUP;
 	}
 
 	acquire_device(dev);
 
+	if ((enter_4byte_addr & 0x08) != 0) {
+		/* Enter 4-byte address mode by setting BIT(7) in a register
+		 * via a 0x17 write instruction.
+		 */
+		uint8_t sr = BIT(7);
+
+		ret = spi_nor_access(dev, 0x17, NOR_ACCESS_WRITE, 0, &sr, sizeof(sr));
+		goto done;
+	}
+
 	if ((enter_4byte_addr & 0x02) != 0) {
 		/* Enter after WREN. */
 		ret = spi_nor_cmd_write(dev, SPI_NOR_CMD_WREN);
@@ -1150,12 +1166,13 @@ static int spi_nor_set_address_mode(const struct device *dev,
 
 	if (ret == 0) {
 		ret = spi_nor_cmd_write(dev, SPI_NOR_CMD_4BA);
+	}
 
-		if (ret == 0) {
-			struct spi_nor_data *data = dev->data;
+done:
+	if (ret == 0) {
+		struct spi_nor_data *data = dev->data;
 
-			data->flag_access_32bit = true;
-		}
+		data->flag_access_32bit = true;
 	}
 
 	release_device(dev);
@@ -1263,7 +1280,7 @@ static int spi_nor_process_sfdp(const struct device *dev)
 		uint16_t id = jesd216_param_id(php);
 
 		LOG_INF("PH%u: %04x rev %u.%u: %u DW @ %x",
-			(php - hp->phdr), id, php->rev_major, php->rev_minor,
+			(int)(php - hp->phdr), id, php->rev_major, php->rev_minor,
 			php->len_dw, jesd216_param_addr(php));
 
 		if (id == JESD216_SFDP_PARAM_ID_BFP) {
@@ -1388,7 +1405,7 @@ static int setup_pages_layout(const struct device *dev)
 
 	data->layout.pages_size = layout_page_size;
 	data->layout.pages_count = flash_size / layout_page_size;
-	LOG_DBG("layout %u x %u By pages", data->layout.pages_count, data->layout.pages_size);
+	LOG_DBG("layout %zu x %zu By pages", data->layout.pages_count, data->layout.pages_size);
 #elif defined(CONFIG_SPI_NOR_SFDP_DEVICETREE)
 	const struct spi_nor_config *cfg = dev->config;
 	const struct flash_pages_layout *layout = &cfg->layout;
diff --git a/drivers/fpga/fpga_ice40_bitbang.c b/drivers/fpga/fpga_ice40_bitbang.c
index 789f47009fa..37ca04d5808 100644
--- a/drivers/fpga/fpga_ice40_bitbang.c
+++ b/drivers/fpga/fpga_ice40_bitbang.c
@@ -8,9 +8,6 @@
 #include <zephyr/device.h>
 #include <zephyr/drivers/fpga.h>
 #include <zephyr/drivers/gpio.h>
-#ifdef CONFIG_PINCTRL
-#include <zephyr/drivers/pinctrl.h>
-#endif /* CONFIG_PINCTRL */
 #include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/sys/crc.h>
@@ -49,7 +46,6 @@ struct fpga_ice40_config_bitbang {
 	volatile gpio_port_pins_t *set;
 	volatile gpio_port_pins_t *clear;
 	uint16_t mhz_delay_count;
-	const struct pinctrl_dev_config *pincfg;
 };
 
 /*
@@ -161,6 +157,13 @@ static int fpga_ice40_load(const struct device *dev, uint32_t *image_ptr, uint32
 	data->loaded = false;
 	fpga_ice40_crc_to_str(0, data->info);
 
+	ret = device_deinit(config->bus.bus);
+
+	if (ret != 0) {
+		LOG_ERR("failed to deinitialize the SPI device: %i", ret);
+		goto unlock;
+	}
+
 	LOG_DBG("Initializing GPIO");
 	ret = gpio_pin_configure_dt(&config->cdone, GPIO_INPUT) ||
 	      gpio_pin_configure_dt(&config->creset, GPIO_OUTPUT_HIGH) ||
@@ -223,15 +226,14 @@ static int fpga_ice40_load(const struct device *dev, uint32_t *image_ptr, uint32
 	fpga_ice40_crc_to_str(crc, data->info);
 	LOG_INF("Loaded image with CRC32 0x%08x", crc);
 
-unlock:
-	(void)gpio_pin_configure_dt(&config->creset, GPIO_OUTPUT_HIGH);
-	(void)gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_HIGH);
-	(void)gpio_pin_configure_dt(&config_bitbang->clk, GPIO_DISCONNECTED);
-	(void)gpio_pin_configure_dt(&config_bitbang->pico, GPIO_DISCONNECTED);
-#ifdef CONFIG_PINCTRL
-	(void)pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
-#endif /* CONFIG_PINCTRL */
+	ret = device_init(config->bus.bus);
 
+	if (ret != 0) {
+		LOG_ERR("failed to reinitialize the SPI device: %i", ret);
+		goto unlock;
+	}
+
+unlock:
 	k_spin_unlock(&data->lock, key);
 
 	return ret;
@@ -246,27 +248,18 @@ static DEVICE_API(fpga, fpga_ice40_api) = {
 	.get_info = fpga_ice40_get_info,
 };
 
-#ifdef CONFIG_PINCTRL
-#define FPGA_ICE40_PINCTRL_DEFINE(inst) PINCTRL_DT_DEFINE(DT_INST_PARENT(inst))
-#define FPGA_ICE40_PINCTRL_GET(inst)    .pincfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST_PARENT(inst)),
-#else
-#define FPGA_ICE40_PINCTRL_DEFINE(inst)
-#define FPGA_ICE40_PINCTRL_GET(inst)
-#endif /* CONFIG_PINCTRL */
-
 #define FPGA_ICE40_DEFINE(inst)                                                                    \
 	BUILD_ASSERT(DT_INST_PROP(inst, mhz_delay_count) >= 0);                                    \
                                                                                                    \
-	FPGA_ICE40_PINCTRL_DEFINE(inst);                                                           \
 	static struct fpga_ice40_data fpga_ice40_data_##inst;                                      \
                                                                                                    \
 	static const struct fpga_ice40_config_bitbang fpga_ice40_config_bitbang_##inst = {         \
 		.clk = GPIO_DT_SPEC_INST_GET(inst, clk_gpios),                                     \
 		.pico = GPIO_DT_SPEC_INST_GET(inst, pico_gpios),                                   \
-		.set = DT_INST_PROP(inst, gpios_set_reg),                                          \
-		.clear = DT_INST_PROP(inst, gpios_clear_reg),                                      \
+		.set = (void *)DT_INST_PROP(inst, gpios_set_reg),                                  \
+		.clear = (void *)DT_INST_PROP(inst, gpios_clear_reg),                              \
 		.mhz_delay_count = DT_INST_PROP(inst, mhz_delay_count),                            \
-		FPGA_ICE40_PINCTRL_GET(inst)};                                                     \
+	};                                                                                         \
                                                                                                    \
 	FPGA_ICE40_CONFIG_DEFINE(inst, &fpga_ice40_config_bitbang_##inst);                         \
                                                                                                    \
diff --git a/drivers/gnss/Kconfig b/drivers/gnss/Kconfig
index d7f51c6de3a..87ddb7ffc4d 100644
--- a/drivers/gnss/Kconfig
+++ b/drivers/gnss/Kconfig
@@ -61,10 +61,10 @@ config GNSS_INIT_PRIORITY
 	  Driver initialization priority for GNSS drivers.
 
 config GNSS_U_BLOX_PROTOCOL
-	bool "GNSS U-BLOX protocol"
+	bool
 	select MODEM_UBX
 	help
-	  Enable gnss u-blox protocol.
+	  Hidden option that enables gnss u-blox protocol.
 
 choice GNSS_REFERENCE_FRAME
 	bool "GNSS reference frame datum"
diff --git a/drivers/gnss/gnss_nmea0183.c b/drivers/gnss/gnss_nmea0183.c
index 515606fbefe..bbeb50a5c7d 100644
--- a/drivers/gnss/gnss_nmea0183.c
+++ b/drivers/gnss/gnss_nmea0183.c
@@ -545,6 +545,16 @@ int gnss_nmea0183_parse_gga(const char **argv, uint16_t argc, struct gnss_data *
 	}
 
 	data->nav_data.altitude = (int32_t)tmp64;
+
+	/* Parse geoid separation */
+	if ((gnss_parse_dec_to_milli(argv[11], &tmp64) < 0) ||
+	    (tmp64 > INT32_MAX) ||
+	    (tmp64 < INT32_MIN)) {
+		return -EINVAL;
+	}
+
+	data->info.geoid_separation = (int32_t)tmp64;
+
 	return 0;
 }
 
diff --git a/drivers/gnss/gnss_u_blox_m8.c b/drivers/gnss/gnss_u_blox_m8.c
index bc550422c8a..0139443ded7 100644
--- a/drivers/gnss/gnss_u_blox_m8.c
+++ b/drivers/gnss/gnss_u_blox_m8.c
@@ -300,6 +300,7 @@ static int ubx_m8_ubx_cfg_prt_set(const struct device *dev, uint32_t target_baud
 
 	ubx_cfg_prt_set_payload_default(&payload);
 	payload.baudrate = target_baudrate;
+	payload.out_proto_mask = UBX_CFG_PRT_OUT_PROTO_NMEA;
 
 	ret = ubx_m8_modem_ubx_script_init(dev, &payload, UBX_CFG_PRT_SET_PAYLOAD_SZ,
 					    UBX_CLASS_CFG, UBX_CFG_PRT);
diff --git a/drivers/gpio/CMakeLists.txt b/drivers/gpio/CMakeLists.txt
index d88cb2b87a9..1eaae60d621 100644
--- a/drivers/gpio/CMakeLists.txt
+++ b/drivers/gpio/CMakeLists.txt
@@ -7,7 +7,7 @@ zephyr_library()
 # zephyr-keep-sorted-start
 zephyr_library_sources_ifdef(CONFIG_GPIO_AD559X     gpio_ad559x.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_ADP5585    gpio_adp5585.c)
-zephyr_library_sources_ifdef(CONFIG_GPIO_ADS114S0X  gpio_ads114s0x.c)
+zephyr_library_sources_ifdef(CONFIG_GPIO_ADS1X4S0X  gpio_ads1x4s0x.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_ALTERA_PIO gpio_altera_pio.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_AMBIQ      gpio_ambiq.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_ANDES_ATCGPIO100 gpio_andes_atcgpio100.c)
@@ -17,6 +17,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_BCM2711    gpio_bcm2711.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_BD8LB600FS gpio_bd8lb600fs.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_BRCMSTB    gpio_brcmstb.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_CC13XX_CC26XX gpio_cc13xx_cc26xx.c)
+zephyr_library_sources_ifdef(CONFIG_GPIO_CC23X0     gpio_cc23x0.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_CC32XX     gpio_cc32xx.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_CMSDK_AHB  gpio_cmsdk_ahb.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_CY8C95XX   gpio_cy8c95xx.c)
@@ -35,6 +36,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_IMX        gpio_imx.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_INFINEON_CAT1 gpio_ifx_cat1.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_INTEL      gpio_intel.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_IPROC      gpio_iproc.c)
+zephyr_library_sources_ifdef(CONFIG_GPIO_ITE_IT51XXX gpio_ite_it51xxx.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_ITE_IT8801 gpio_ite_it8801.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_ITE_IT8XXX2 gpio_ite_it8xxx2.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_ITE_IT8XXX2_V2 gpio_ite_it8xxx2_v2.c)
@@ -44,7 +46,9 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_LMP90XXX   gpio_lmp90xxx.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_LPC11U6X   gpio_lpc11u6x.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_MAX14906   gpio_max14906.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_MAX14916   gpio_max14916.c)
-zephyr_library_sources_ifdef(CONFIG_GPIO_MAX22190   gpio_max22190.c)
+zephyr_library_sources_ifdef(CONFIG_GPIO_MAX14917   gpio_max14917.c)
+zephyr_library_sources_ifdef(CONFIG_GPIO_MAX22017   gpio_max22017.c)
+zephyr_library_sources_ifdef(CONFIG_GPIO_MAX2219X   gpio_max2219x.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_MAX32      gpio_max32.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_MCHP_MEC5  gpio_mchp_mec5.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_MCHP_MSS       gpio_mchp_mss.c)
@@ -55,6 +59,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_MCUX       gpio_mcux.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_MCUX_IGPIO gpio_mcux_igpio.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_MCUX_LPC   gpio_mcux_lpc.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_MCUX_RGPIO gpio_mcux_rgpio.c)
+zephyr_library_sources_ifdef(CONFIG_GPIO_MFXSTM32L152 gpio_mfxstm32l152.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_MMIO32     gpio_mmio32.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_NCT38XX    gpio_nct38xx.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_NCT38XX    gpio_nct38xx_port.c)
@@ -68,6 +73,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_NRFX       gpio_nrfx.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_NUMAKER    gpio_numaker.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_NUMICRO    gpio_numicro.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_NXP_S32    gpio_nxp_s32.c)
+zephyr_library_sources_ifdef(CONFIG_GPIO_PCA6416    gpio_pca6416.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_PCA953X    gpio_pca953x.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_PCA95XX    gpio_pca95xx.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_PCAL64XXA  gpio_pcal64xxa.c)
@@ -76,8 +82,8 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_PCF857X    gpio_pcf857x.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_PSOC6      gpio_psoc6.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_RA_IOPORT  gpio_renesas_ra_ioport.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_RCAR       gpio_rcar.c)
-zephyr_library_sources_ifdef(CONFIG_GPIO_RENESAS_RA gpio_renesas_ra.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_RENESAS_RZ gpio_renesas_rz.c)
+zephyr_library_sources_ifdef(CONFIG_GPIO_RENESAS_RZA2M  gpio_renesas_rza2m.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_RP1        gpio_rp1.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_RPI_PICO   gpio_rpi_pico.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_RT1718S    gpio_rt1718s.c)
@@ -91,6 +97,8 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_SAM4L      gpio_sam4l.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_SEDI    gpio_sedi.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_SI32       gpio_si32.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_SIFIVE     gpio_sifive.c)
+zephyr_library_sources_ifdef(CONFIG_GPIO_SILABS_SIWX91X gpio_silabs_siwx91x.c)
+zephyr_library_sources_ifdef(CONFIG_GPIO_SILABS_SIWX91X_UULP gpio_silabs_siwx91x_uulp.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_SMARTBOND  gpio_smartbond.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_SN74HC595  gpio_sn74hc595.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_SNPS_CREG  gpio_creg_gpio.c)
@@ -98,6 +106,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_STELLARIS  gpio_stellaris.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_STM32      gpio_stm32.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_STMPE1600  gpio_stmpe1600.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_SX1509B    gpio_sx1509b.c)
+zephyr_library_sources_ifdef(CONFIG_GPIO_SY1XX      gpio_sy1xx.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_TCA6424A   gpio_tca6424a.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_TELINK_B91 gpio_b91.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_TEST       gpio_test.c)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 6ca6216a046..486f8146729 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -96,7 +96,7 @@ config GPIO_ENABLE_DISABLE_INTERRUPT
 # zephyr-keep-sorted-start
 source "drivers/gpio/Kconfig.ad559x"
 source "drivers/gpio/Kconfig.adp5585"
-source "drivers/gpio/Kconfig.ads114s0x"
+source "drivers/gpio/Kconfig.ads1x4s0x"
 source "drivers/gpio/Kconfig.altera"
 source "drivers/gpio/Kconfig.ambiq"
 source "drivers/gpio/Kconfig.andes_atcgpio100"
@@ -107,6 +107,7 @@ source "drivers/gpio/Kconfig.bcm2711"
 source "drivers/gpio/Kconfig.bd8lb600fs"
 source "drivers/gpio/Kconfig.brcmstb"
 source "drivers/gpio/Kconfig.cc13xx_cc26xx"
+source "drivers/gpio/Kconfig.cc23x0"
 source "drivers/gpio/Kconfig.cc32xx"
 source "drivers/gpio/Kconfig.cmsdk_ahb"
 source "drivers/gpio/Kconfig.creg_gpio"
@@ -127,6 +128,7 @@ source "drivers/gpio/Kconfig.ifx_cat1"
 source "drivers/gpio/Kconfig.imx"
 source "drivers/gpio/Kconfig.intel"
 source "drivers/gpio/Kconfig.iproc"
+source "drivers/gpio/Kconfig.it51xxx"
 source "drivers/gpio/Kconfig.it8801"
 source "drivers/gpio/Kconfig.it8xxx2"
 source "drivers/gpio/Kconfig.litex"
@@ -134,7 +136,9 @@ source "drivers/gpio/Kconfig.lmp90xxx"
 source "drivers/gpio/Kconfig.lpc11u6x"
 source "drivers/gpio/Kconfig.max14906"
 source "drivers/gpio/Kconfig.max14916"
-source "drivers/gpio/Kconfig.max22190"
+source "drivers/gpio/Kconfig.max14917"
+source "drivers/gpio/Kconfig.max22017"
+source "drivers/gpio/Kconfig.max2219x"
 source "drivers/gpio/Kconfig.max32"
 source "drivers/gpio/Kconfig.mchp_mss"
 source "drivers/gpio/Kconfig.mcp23xxx"
@@ -143,6 +147,7 @@ source "drivers/gpio/Kconfig.mcux_igpio"
 source "drivers/gpio/Kconfig.mcux_lpc"
 source "drivers/gpio/Kconfig.mcux_rgpio"
 source "drivers/gpio/Kconfig.mec5"
+source "drivers/gpio/Kconfig.mfxstm32l152"
 source "drivers/gpio/Kconfig.mmio32"
 source "drivers/gpio/Kconfig.nct38xx"
 source "drivers/gpio/Kconfig.neorv32"
@@ -154,6 +159,7 @@ source "drivers/gpio/Kconfig.nrfx"
 source "drivers/gpio/Kconfig.numaker"
 source "drivers/gpio/Kconfig.numicro"
 source "drivers/gpio/Kconfig.nxp_s32"
+source "drivers/gpio/Kconfig.pca6416"
 source "drivers/gpio/Kconfig.pca953x"
 source "drivers/gpio/Kconfig.pca95xx"
 source "drivers/gpio/Kconfig.pca_series"
@@ -161,9 +167,9 @@ source "drivers/gpio/Kconfig.pcal64xxa"
 source "drivers/gpio/Kconfig.pcf857x"
 source "drivers/gpio/Kconfig.psoc6"
 source "drivers/gpio/Kconfig.rcar"
-source "drivers/gpio/Kconfig.renesas_ra"
 source "drivers/gpio/Kconfig.renesas_ra_ioport"
 source "drivers/gpio/Kconfig.renesas_rz"
+source "drivers/gpio/Kconfig.renesas_rza2m"
 source "drivers/gpio/Kconfig.rp1"
 source "drivers/gpio/Kconfig.rpi_pico"
 source "drivers/gpio/Kconfig.rt1718s"
@@ -176,12 +182,14 @@ source "drivers/gpio/Kconfig.sc18im704"
 source "drivers/gpio/Kconfig.sedi"
 source "drivers/gpio/Kconfig.si32"
 source "drivers/gpio/Kconfig.sifive"
+source "drivers/gpio/Kconfig.siwx91x"
 source "drivers/gpio/Kconfig.smartbond"
 source "drivers/gpio/Kconfig.sn74hc595"
 source "drivers/gpio/Kconfig.stellaris"
 source "drivers/gpio/Kconfig.stm32"
 source "drivers/gpio/Kconfig.stmpe1600"
 source "drivers/gpio/Kconfig.sx1509b"
+source "drivers/gpio/Kconfig.sy1xx"
 source "drivers/gpio/Kconfig.tca6424a"
 source "drivers/gpio/Kconfig.test"
 source "drivers/gpio/Kconfig.tle9104"
diff --git a/drivers/gpio/Kconfig.ads114s0x b/drivers/gpio/Kconfig.ads114s0x
deleted file mode 100644
index 1dd642c6def..00000000000
--- a/drivers/gpio/Kconfig.ads114s0x
+++ /dev/null
@@ -1,25 +0,0 @@
-# ADS114S0x GPIO configuration options
-
-# Copyright (c) 2023 SILA Embedded Solutions GmbH
-# SPDX-License-Identifier: Apache-2.0
-
-menuconfig GPIO_ADS114S0X
-	bool "ADS114S0x GPIO driver"
-	default y
-	depends on DT_HAS_TI_ADS114S0X_GPIO_ENABLED
-	depends on ADC_ADS114S0X_GPIO
-	help
-	  Enable GPIO driver for ADS114S0x.
-
-	  The ADS114S0x is a multi-channel analog frontend (AFE).
-
-	  The GPIO port of the ADS114S0x (GPIO0 to GPIO3) is exposed as a
-	  GPIO controller driver with read/write support.
-
-config GPIO_ADS114S0X_INIT_PRIORITY
-	int "Driver init priority"
-	default 99
-	depends on GPIO_ADS114S0X
-	help
-	  Device driver initialization priority. This driver must be
-	  initialized after the ADS114S0x ADC driver.
diff --git a/drivers/gpio/Kconfig.ads1x4s0x b/drivers/gpio/Kconfig.ads1x4s0x
new file mode 100644
index 00000000000..39fca26923e
--- /dev/null
+++ b/drivers/gpio/Kconfig.ads1x4s0x
@@ -0,0 +1,25 @@
+# ADS1X4S0X GPIO configuration options
+
+# Copyright (c) 2023 SILA Embedded Solutions GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig GPIO_ADS1X4S0X
+	bool "ADS1X4S0X GPIO driver"
+	default y
+	depends on DT_HAS_TI_ADS1X4S0X_GPIO_ENABLED
+	depends on ADC_ADS1X4S0X_GPIO
+	help
+	  Enable GPIO driver for ADS1X4S0X.
+
+	  The ADS1X4S0X is a multi-channel analog frontend (AFE).
+
+	  The GPIO port of the ADS1X4S0X (GPIO0 to GPIO3) is exposed as a
+	  GPIO controller driver with read/write support.
+
+config GPIO_ADS1X4S0X_INIT_PRIORITY
+	int "Driver init priority"
+	default 99
+	depends on GPIO_ADS1X4S0X
+	help
+	  Device driver initialization priority. This driver must be
+	  initialized after the ADS1X4S0X ADC driver.
diff --git a/drivers/gpio/Kconfig.cc23x0 b/drivers/gpio/Kconfig.cc23x0
new file mode 100644
index 00000000000..147fd029cf2
--- /dev/null
+++ b/drivers/gpio/Kconfig.cc23x0
@@ -0,0 +1,11 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+# Copyright (c) 2024 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config GPIO_CC23X0
+	bool "TI SimpleLink CC23X0 GPIO driver"
+	default y
+	depends on DT_HAS_TI_CC23X0_GPIO_ENABLED
+	help
+	  Enable the TI SimpleLink CC23x0  GPIO driver.
diff --git a/drivers/gpio/Kconfig.davinci b/drivers/gpio/Kconfig.davinci
index 2bd94cade43..b7de108de71 100644
--- a/drivers/gpio/Kconfig.davinci
+++ b/drivers/gpio/Kconfig.davinci
@@ -7,5 +7,6 @@ config GPIO_DAVINCI
 	bool "Davinci GPIO Driver"
 	default y
 	depends on DT_HAS_TI_DAVINCI_GPIO_ENABLED
+	select PINCTRL
 	help
 		Enable the Davinci GPIO controller support.
diff --git a/drivers/gpio/Kconfig.it51xxx b/drivers/gpio/Kconfig.it51xxx
new file mode 100644
index 00000000000..cf4d0e7be6c
--- /dev/null
+++ b/drivers/gpio/Kconfig.it51xxx
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config GPIO_ITE_IT51XXX
+	bool "ITE IT51XXX GPIO driver"
+	default y
+	depends on DT_HAS_ITE_IT51XXX_GPIO_ENABLED
+	help
+	  Enable driver for the IT51XXX series GPIO controller.
diff --git a/drivers/gpio/Kconfig.max14916 b/drivers/gpio/Kconfig.max14916
index dfdc1c4f76c..f98c0bced3b 100644
--- a/drivers/gpio/Kconfig.max14916
+++ b/drivers/gpio/Kconfig.max14916
@@ -7,7 +7,7 @@
 menuconfig GPIO_MAX14916
 	bool "MAX14916 GPIO driver"
 	default y
-	depends on DT_HAS_ADI_MAX14916_GPIO_ENABLED && SPI
+	depends on (DT_HAS_ADI_MAX14916_GPIO_ENABLED || DT_HAS_ADI_MAX14915_GPIO_ENABLED) && SPI
 	help
 	  Enabe MAX1416 octal industrial digital
 	  output with diagnostics
diff --git a/drivers/gpio/Kconfig.max14917 b/drivers/gpio/Kconfig.max14917
new file mode 100644
index 00000000000..cd7f1af878d
--- /dev/null
+++ b/drivers/gpio/Kconfig.max14917
@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Analog Devices Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+# MAX14917 GPIO configuration options
+
+menuconfig GPIO_MAX14917
+	bool "MAX14917 GPIO driver"
+	default y
+	select CRC
+	depends on DT_HAS_ADI_MAX14917_GPIO_ENABLED && SPI
+	help
+	  Enable MAX14917 octal industrial digital
+	  output with diagnostics
+
+config GPIO_MAX14917_INIT_PRIORITY
+	int "Driver init priority"
+	default 99
+	depends on GPIO_MAX14917
+	help
+	  Device driver initialization priority.
diff --git a/drivers/gpio/Kconfig.max22017 b/drivers/gpio/Kconfig.max22017
new file mode 100644
index 00000000000..49c07edd92b
--- /dev/null
+++ b/drivers/gpio/Kconfig.max22017
@@ -0,0 +1,32 @@
+# Copyright (c) 2024 Analog Devices Inc.
+# Copyright (c) 2024 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+config GPIO_MAX22017
+	bool "Analog Devices MAX22017 GPIO support"
+	default y
+	depends on DT_HAS_ADI_MAX22017_GPIO_ENABLED
+	select MFD
+	help
+	  Enable GPIO support for the Analog Devices MAX22017
+
+if GPIO_MAX22017
+
+config GPIO_MAX22017_INIT_PRIORITY
+	int "Init priority"
+	default 81
+	help
+	  Analog Devices MAX22017 gpio device driver initialization priority.
+
+config GPIO_MAX22017_INT_QUIRK
+	bool "MAX22017 GPIO Interrupt quirk"
+	help
+	  The GPIO controller will not report any new GPI interrupt as long as its interrupt status
+	  register hasn't been read.
+	  Reading the interrupt status register happens on a falling edge of the INT pin.
+	  There seems to be a condition when the GPIO controller detects an interrupt but it's INT
+	  pin stays high which masks any subsequent interrupts.
+	  To avoid being stuck in that state, fire a timer to periodically check the interrupt status
+	  register.
+
+endif # GPIO_MAX22017
diff --git a/drivers/gpio/Kconfig.max22190 b/drivers/gpio/Kconfig.max22190
deleted file mode 100644
index c7e6dd4314b..00000000000
--- a/drivers/gpio/Kconfig.max22190
+++ /dev/null
@@ -1,21 +0,0 @@
-# Copyright (c) 2024 Analog Devices Inc.
-# Copyright (c) 2024 BayLibre SAS
-# SPDX-License-Identifier: Apache-2.0
-
-# MAX22190 GPIO configuration options
-
-menuconfig GPIO_MAX22190
-	bool "MAX22190 GPIO driver"
-	default y
-	depends on SPI
-	depends on DT_HAS_ADI_MAX22190_GPIO_ENABLED
-	help
-	  Enabe MAX22190 Octal industrial digital
-	  input with diagnostics
-
-config GPIO_MAX22190_INIT_PRIORITY
-	int "Driver init priority"
-	default 99
-	depends on GPIO_MAX22190
-	help
-	  Device driver initialization priority.
diff --git a/drivers/gpio/Kconfig.max2219x b/drivers/gpio/Kconfig.max2219x
new file mode 100644
index 00000000000..e1051dd02e7
--- /dev/null
+++ b/drivers/gpio/Kconfig.max2219x
@@ -0,0 +1,21 @@
+# Copyright (c) 2024 Analog Devices Inc.
+# Copyright (c) 2024 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+# MAX22190 GPIO configuration options
+
+menuconfig GPIO_MAX2219X
+	bool "MAX2219X GPIO driver"
+	default y
+	depends on SPI
+	depends on DT_HAS_ADI_MAX22190_GPIO_ENABLED || DT_HAS_ADI_MAX22199_GPIO_ENABLED
+	help
+	  Enabe MAX2219X Octal industrial digital
+	  input with diagnostics
+
+config GPIO_MAX22190_INIT_PRIORITY
+	int "Driver init priority"
+	default 99
+	depends on GPIO_MAX2219X
+	help
+	  Device driver initialization priority.
diff --git a/drivers/gpio/Kconfig.mfxstm32l152 b/drivers/gpio/Kconfig.mfxstm32l152
new file mode 100644
index 00000000000..ac9c649f0ca
--- /dev/null
+++ b/drivers/gpio/Kconfig.mfxstm32l152
@@ -0,0 +1,19 @@
+# MFXSTM32L152 GPIO configuration options
+
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig GPIO_MFXSTM32L152
+	bool "MFXSTM32L152 I2C-based GPIO chip"
+	default y
+	depends on DT_HAS_ST_MFXSTM32L152_ENABLED
+	select I2C
+	help
+	  Enable driver for MFXSTM32L152 I2C-based GPIO chip.
+
+config GPIO_MFXSTM32L152_INIT_PRIORITY
+	int "Init priority"
+	default 70
+	depends on GPIO_MFXSTM32L152
+	help
+	  Device driver initialization priority.
diff --git a/drivers/gpio/Kconfig.pca6416 b/drivers/gpio/Kconfig.pca6416
new file mode 100644
index 00000000000..bef9568c55f
--- /dev/null
+++ b/drivers/gpio/Kconfig.pca6416
@@ -0,0 +1,22 @@
+# PCA6416 GPIO configuration options
+
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig GPIO_PCA6416
+	bool "PCA6416 I2C GPIO chip"
+	default y
+	depends on DT_HAS_NXP_PCA6416_ENABLED
+	select I2C
+	help
+	  Enable driver for PCA6416 I2C GPIO chip.
+
+if GPIO_PCA6416
+
+config GPIO_PCA6416_INIT_PRIORITY
+	int "Init priority"
+	default 70
+	help
+	  PCA6416 Device driver initialization priority.
+
+endif # GPIO_PCA6416
diff --git a/drivers/gpio/Kconfig.renesas_ra b/drivers/gpio/Kconfig.renesas_ra
deleted file mode 100644
index 2f6fb3c38c4..00000000000
--- a/drivers/gpio/Kconfig.renesas_ra
+++ /dev/null
@@ -1,11 +0,0 @@
-# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
-# SPDX-License-Identifier: Apache-2.0
-
-config GPIO_RENESAS_RA
-	bool "Renesas RA Series GPIO driver"
-	default y
-	select GPIO_GET_CONFIG
-	select PINCTRL
-	depends on DT_HAS_RENESAS_RA_GPIO_ENABLED
-	help
-	  Enable Renesas RA series GPIO driver.
diff --git a/drivers/gpio/Kconfig.renesas_ra_ioport b/drivers/gpio/Kconfig.renesas_ra_ioport
index c09361cb1ca..257475b4f60 100644
--- a/drivers/gpio/Kconfig.renesas_ra_ioport
+++ b/drivers/gpio/Kconfig.renesas_ra_ioport
@@ -7,3 +7,8 @@ config GPIO_RA_IOPORT
 	depends on DT_HAS_RENESAS_RA_GPIO_IOPORT_ENABLED
 	help
 	  Enable the Renesas RA GPIO IO port driver.
+
+config GPIO_RA_HAS_VBTICTLR
+	bool "Support VBATT input control"
+	help
+	  Enable for Renesas RA which support VBATT input control.
diff --git a/drivers/gpio/Kconfig.renesas_rz b/drivers/gpio/Kconfig.renesas_rz
index ae2e08c85de..5c9306ec2c4 100644
--- a/drivers/gpio/Kconfig.renesas_rz
+++ b/drivers/gpio/Kconfig.renesas_rz
@@ -8,3 +8,10 @@ config GPIO_RENESAS_RZ
 	select USE_RZ_FSP_IOPORT
 	help
 	  Enable Renesas RZ series gpio driver.
+
+config GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT
+	bool
+	default y
+	depends on DT_HAS_RENESAS_RZ_GPIO_INT_ENABLED
+	help
+	  GPIO pins can generate interrupts at port mode.
diff --git a/drivers/gpio/Kconfig.renesas_rza2m b/drivers/gpio/Kconfig.renesas_rza2m
new file mode 100644
index 00000000000..124188f54f8
--- /dev/null
+++ b/drivers/gpio/Kconfig.renesas_rza2m
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config GPIO_RENESAS_RZA2M
+	bool "Renesas RZ/A2M GPIO"
+	default y
+	depends on DT_HAS_RENESAS_RZA2M_GPIO_ENABLED
+	select PINCTRL
+	help
+	  Enable Renesas RZ/A2M GPIO driver.
diff --git a/drivers/gpio/Kconfig.rpi_pico b/drivers/gpio/Kconfig.rpi_pico
index 64370be497c..8d75fea4472 100644
--- a/drivers/gpio/Kconfig.rpi_pico
+++ b/drivers/gpio/Kconfig.rpi_pico
@@ -3,7 +3,7 @@
 
 config GPIO_RPI_PICO
 	default y
-	depends on DT_HAS_RASPBERRYPI_PICO_GPIO_ENABLED
+	depends on DT_HAS_RASPBERRYPI_PICO_GPIO_PORT_ENABLED
 	select PICOSDK_USE_GPIO
 	select PINCTRL
 	bool "Raspberry Pi Pico GPIO driver"
diff --git a/drivers/gpio/Kconfig.rts5912 b/drivers/gpio/Kconfig.rts5912
index a0d845a8b3e..d1a1880c938 100644
--- a/drivers/gpio/Kconfig.rts5912
+++ b/drivers/gpio/Kconfig.rts5912
@@ -5,6 +5,7 @@
 
 config GPIO_RTS5912
 	bool "Realtek embedded controller (EC) gpio driver"
+	depends on SOC_SERIES_RTS5912
 	default y if DT_HAS_REALTEK_RTS5912_GPIO_ENABLED
 	help
 	  Enable support for Realtek GPIO controller.
diff --git a/drivers/gpio/Kconfig.siwx91x b/drivers/gpio/Kconfig.siwx91x
new file mode 100644
index 00000000000..1ea818fdbb8
--- /dev/null
+++ b/drivers/gpio/Kconfig.siwx91x
@@ -0,0 +1,21 @@
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig GPIO_SILABS_SIWX91X
+	bool "Silabs SiWx91x GPIO driver"
+	default y
+	depends on DT_HAS_SILABS_SIWX91X_GPIO_ENABLED
+	help
+	  Enable the HP/ULP GPIO driver for the Silabs SiWx91x SoC series.
+
+config GPIO_SILABS_SIWX91X_COMMON_INIT_PRIORITY
+	int "Common initialization priority"
+	depends on GPIO_SILABS_SIWX91X
+	default 39
+
+config GPIO_SILABS_SIWX91X_UULP
+	bool "Silabs SiWx91x UULP GPIO driver"
+	default y
+	depends on DT_HAS_SILABS_SIWX91X_GPIO_UULP_ENABLED
+	help
+	  Enable the UULP GPIO driver for the Silabs SiWx91x SoC series.
diff --git a/drivers/gpio/Kconfig.sy1xx b/drivers/gpio/Kconfig.sy1xx
new file mode 100644
index 00000000000..6fa452be854
--- /dev/null
+++ b/drivers/gpio/Kconfig.sy1xx
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+config GPIO_SY1XX
+	bool "SY1XX GPIO driver"
+	default y
+	depends on DT_HAS_SENSRY_SY1XX_GPIO_ENABLED
+	help
+	  Enable the SY1XX GPIO driver.
diff --git a/drivers/gpio/gpio_adp5585.c b/drivers/gpio/gpio_adp5585.c
index 99f074a130d..3011120726e 100644
--- a/drivers/gpio/gpio_adp5585.c
+++ b/drivers/gpio/gpio_adp5585.c
@@ -143,14 +143,14 @@ static int gpio_adp5585_config(const struct device *dev, gpio_pin_t pin, gpio_fl
 			data->output |= BIT(pin);
 		}
 		if (bank == 0) {
-			/* reg_value for ADP5585_GPO_OUT_MODE */
+			/* reg_value for ADP5585_GPO_DATA_OUT */
 			reg_value = (uint8_t)data->output;
 		} else {
-			/* reg_value for ADP5585_GPO_OUT_MODE */
+			/* reg_value for ADP5585_GPO_DATA_OUT */
 			reg_value = (uint8_t)(data->output >> 8);
 		}
 		ret = i2c_reg_write_byte_dt(&parent_cfg->i2c_bus,
-					ADP5585_GPO_OUT_MODE_A + bank,
+					ADP5585_GPO_DATA_OUT_A + bank,
 					reg_value);
 		if (ret != 0) {
 			goto out;
diff --git a/drivers/gpio/gpio_ads114s0x.c b/drivers/gpio/gpio_ads114s0x.c
deleted file mode 100644
index 5ccbc4b553e..00000000000
--- a/drivers/gpio/gpio_ads114s0x.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright (c) 2023 SILA Embedded Solutions GmbH
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief GPIO driver for the ADS114S0x AFE.
- */
-
-#define DT_DRV_COMPAT ti_ads114s0x_gpio
-
-#include <zephyr/drivers/gpio.h>
-#include <zephyr/kernel.h>
-
-#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
-#include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(gpio_ads114s0x);
-
-#include <zephyr/drivers/adc/ads114s0x.h>
-
-#include <zephyr/drivers/gpio/gpio_utils.h>
-
-struct gpio_ads114s0x_config {
-	/* gpio_driver_config needs to be first */
-	struct gpio_driver_config common;
-	const struct device *parent;
-};
-
-struct gpio_ads114s0x_data {
-	/* gpio_driver_data needs to be first */
-	struct gpio_driver_data common;
-};
-
-static int gpio_ads114s0x_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
-{
-	const struct gpio_ads114s0x_config *config = dev->config;
-	int err = 0;
-
-	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
-		return ads114s0x_gpio_deconfigure(config->parent, pin);
-	}
-
-	if ((flags & GPIO_SINGLE_ENDED) != 0) {
-		return -ENOTSUP;
-	}
-
-	if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
-		return -ENOTSUP;
-	}
-
-	if (flags & GPIO_INT_ENABLE) {
-		/* ads114s0x GPIOs do not support interrupts */
-		return -ENOTSUP;
-	}
-
-	switch (flags & GPIO_DIR_MASK) {
-	case GPIO_INPUT:
-		err = ads114s0x_gpio_set_input(config->parent, pin);
-		break;
-	case GPIO_OUTPUT:
-		err = ads114s0x_gpio_set_output(config->parent, pin,
-						(flags & GPIO_OUTPUT_INIT_HIGH) != 0);
-		break;
-	default:
-		return -ENOTSUP;
-	}
-
-	return err;
-}
-
-static int gpio_ads114s0x_port_get_raw(const struct device *dev, gpio_port_value_t *value)
-{
-	const struct gpio_ads114s0x_config *config = dev->config;
-
-	return ads114s0x_gpio_port_get_raw(config->parent, value);
-}
-
-static int gpio_ads114s0x_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
-					      gpio_port_value_t value)
-{
-	const struct gpio_ads114s0x_config *config = dev->config;
-
-	return ads114s0x_gpio_port_set_masked_raw(config->parent, mask, value);
-}
-
-static int gpio_ads114s0x_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
-{
-	const struct gpio_ads114s0x_config *config = dev->config;
-
-	return ads114s0x_gpio_port_set_masked_raw(config->parent, pins, pins);
-}
-
-static int gpio_ads114s0x_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
-{
-	const struct gpio_ads114s0x_config *config = dev->config;
-
-	return ads114s0x_gpio_port_set_masked_raw(config->parent, pins, 0);
-}
-
-static int gpio_ads114s0x_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
-{
-	const struct gpio_ads114s0x_config *config = dev->config;
-
-	return ads114s0x_gpio_port_toggle_bits(config->parent, pins);
-}
-
-static int gpio_ads114s0x_init(const struct device *dev)
-{
-	const struct gpio_ads114s0x_config *config = dev->config;
-
-	if (!device_is_ready(config->parent)) {
-		LOG_ERR("parent ads114s0x device '%s' not ready", config->parent->name);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static DEVICE_API(gpio, gpio_ads114s0x_api) = {
-	.pin_configure = gpio_ads114s0x_config,
-	.port_set_masked_raw = gpio_ads114s0x_port_set_masked_raw,
-	.port_set_bits_raw = gpio_ads114s0x_port_set_bits_raw,
-	.port_clear_bits_raw = gpio_ads114s0x_port_clear_bits_raw,
-	.port_toggle_bits = gpio_ads114s0x_port_toggle_bits,
-	.port_get_raw = gpio_ads114s0x_port_get_raw,
-};
-
-BUILD_ASSERT(CONFIG_GPIO_ADS114S0X_INIT_PRIORITY > CONFIG_ADC_INIT_PRIORITY,
-	     "ADS114S0X GPIO driver must be initialized after ADS114S0X ADC driver");
-
-#define GPIO_ADS114S0X_DEVICE(id)                                                                  \
-	static const struct gpio_ads114s0x_config gpio_ads114s0x_##id##_cfg = {                    \
-		.common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(id)},                  \
-		.parent = DEVICE_DT_GET(DT_INST_BUS(id)),                                          \
-	};                                                                                         \
-                                                                                                   \
-	static struct gpio_ads114s0x_data gpio_ads114s0x_##id##_data;                              \
-                                                                                                   \
-	DEVICE_DT_INST_DEFINE(id, gpio_ads114s0x_init, NULL, &gpio_ads114s0x_##id##_data,          \
-			      &gpio_ads114s0x_##id##_cfg, POST_KERNEL,                             \
-			      CONFIG_GPIO_ADS114S0X_INIT_PRIORITY, &gpio_ads114s0x_api);
-
-DT_INST_FOREACH_STATUS_OKAY(GPIO_ADS114S0X_DEVICE)
diff --git a/drivers/gpio/gpio_ads1x4s0x.c b/drivers/gpio/gpio_ads1x4s0x.c
new file mode 100644
index 00000000000..81ed760adcc
--- /dev/null
+++ b/drivers/gpio/gpio_ads1x4s0x.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2023 SILA Embedded Solutions GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief GPIO driver for the ADS1X4S0X AFE.
+ */
+
+#define DT_DRV_COMPAT ti_ads1x4s0x_gpio
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/kernel.h>
+
+#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(gpio_ads1x4s0x);
+
+#include <zephyr/drivers/adc/ads1x4s0x.h>
+
+#include <zephyr/drivers/gpio/gpio_utils.h>
+
+struct gpio_ads1x4s0x_config {
+	/* gpio_driver_config needs to be first */
+	struct gpio_driver_config common;
+	const struct device *parent;
+};
+
+struct gpio_ads1x4s0x_data {
+	/* gpio_driver_data needs to be first */
+	struct gpio_driver_data common;
+};
+
+static int gpio_ads1x4s0x_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
+{
+	const struct gpio_ads1x4s0x_config *config = dev->config;
+	int err = 0;
+
+	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
+		return ads1x4s0x_gpio_deconfigure(config->parent, pin);
+	}
+
+	if ((flags & GPIO_SINGLE_ENDED) != 0) {
+		return -ENOTSUP;
+	}
+
+	if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
+		return -ENOTSUP;
+	}
+
+	if (flags & GPIO_INT_ENABLE) {
+		/* ads1x4s0x GPIOs do not support interrupts */
+		return -ENOTSUP;
+	}
+
+	switch (flags & GPIO_DIR_MASK) {
+	case GPIO_INPUT:
+		err = ads1x4s0x_gpio_set_input(config->parent, pin);
+		break;
+	case GPIO_OUTPUT:
+		err = ads1x4s0x_gpio_set_output(config->parent, pin,
+						(flags & GPIO_OUTPUT_INIT_HIGH) != 0);
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	return err;
+}
+
+static int gpio_ads1x4s0x_port_get_raw(const struct device *dev, gpio_port_value_t *value)
+{
+	const struct gpio_ads1x4s0x_config *config = dev->config;
+
+	return ads1x4s0x_gpio_port_get_raw(config->parent, value);
+}
+
+static int gpio_ads1x4s0x_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
+					      gpio_port_value_t value)
+{
+	const struct gpio_ads1x4s0x_config *config = dev->config;
+
+	return ads1x4s0x_gpio_port_set_masked_raw(config->parent, mask, value);
+}
+
+static int gpio_ads1x4s0x_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
+{
+	const struct gpio_ads1x4s0x_config *config = dev->config;
+
+	return ads1x4s0x_gpio_port_set_masked_raw(config->parent, pins, pins);
+}
+
+static int gpio_ads1x4s0x_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
+{
+	const struct gpio_ads1x4s0x_config *config = dev->config;
+
+	return ads1x4s0x_gpio_port_set_masked_raw(config->parent, pins, 0);
+}
+
+static int gpio_ads1x4s0x_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
+{
+	const struct gpio_ads1x4s0x_config *config = dev->config;
+
+	return ads1x4s0x_gpio_port_toggle_bits(config->parent, pins);
+}
+
+static int gpio_ads1x4s0x_init(const struct device *dev)
+{
+	const struct gpio_ads1x4s0x_config *config = dev->config;
+
+	if (!device_is_ready(config->parent)) {
+		LOG_ERR("parent ads1x4s0x device '%s' not ready", config->parent->name);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(gpio, gpio_ads1x4s0x_api) = {
+	.pin_configure = gpio_ads1x4s0x_config,
+	.port_set_masked_raw = gpio_ads1x4s0x_port_set_masked_raw,
+	.port_set_bits_raw = gpio_ads1x4s0x_port_set_bits_raw,
+	.port_clear_bits_raw = gpio_ads1x4s0x_port_clear_bits_raw,
+	.port_toggle_bits = gpio_ads1x4s0x_port_toggle_bits,
+	.port_get_raw = gpio_ads1x4s0x_port_get_raw,
+};
+
+BUILD_ASSERT(CONFIG_GPIO_ADS1X4S0X_INIT_PRIORITY > CONFIG_ADC_INIT_PRIORITY,
+	     "ADS1X4S0X GPIO driver must be initialized after ADS1X4S0X ADC driver");
+
+#define GPIO_ADS1X4S0X_DEVICE(id)                                                                  \
+	static const struct gpio_ads1x4s0x_config gpio_ads1x4s0x_##id##_cfg = {                    \
+		.common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(id)},                  \
+		.parent = DEVICE_DT_GET(DT_INST_BUS(id)),                                          \
+	};                                                                                         \
+                                                                                                   \
+	static struct gpio_ads1x4s0x_data gpio_ads1x4s0x_##id##_data;                              \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(id, gpio_ads1x4s0x_init, NULL, &gpio_ads1x4s0x_##id##_data,          \
+			      &gpio_ads1x4s0x_##id##_cfg, POST_KERNEL,                             \
+			      CONFIG_GPIO_ADS1X4S0X_INIT_PRIORITY, &gpio_ads1x4s0x_api);
+
+DT_INST_FOREACH_STATUS_OKAY(GPIO_ADS1X4S0X_DEVICE)
diff --git a/drivers/gpio/gpio_ambiq.c b/drivers/gpio/gpio_ambiq.c
index 530b8326fed..c4effe03d15 100644
--- a/drivers/gpio/gpio_ambiq.c
+++ b/drivers/gpio/gpio_ambiq.c
@@ -13,8 +13,9 @@
 #include <zephyr/drivers/gpio/gpio_utils.h>
 #include <zephyr/irq.h>
 #include <zephyr/spinlock.h>
+#include <zephyr/drivers/gpio/gpio_ambiq.h>
 
-#include <am_mcu_apollo.h>
+#include <soc.h>
 
 typedef void (*ambiq_gpio_cfg_func_t)(void);
 
@@ -488,7 +489,12 @@ static int ambiq_gpio_pin_interrupt_configure(const struct device *dev, gpio_pin
 			 * GPIO_INT_TRIG_BOTH is not supported on Ambiq Apollo4 Plus Platform
 			 * ERR008: GPIO: Dual-edge interrupts are not vectoring
 			 */
+#if defined(CONFIG_SOC_SERIES_APOLLO4X)
 			return -ENOTSUP;
+#elif defined(CONFIG_SOC_SERIES_APOLLO5X)
+			pincfg.GP.cfg_b.eIntDir = AM_HAL_GPIO_PIN_INTDIR_BOTH;
+			break;
+#endif
 		default:
 			return -EINVAL;
 		}
@@ -567,6 +573,18 @@ static DEVICE_API(gpio, ambiq_gpio_drv_api) = {
 #endif
 };
 
+gpio_pin_t ambiq_gpio_get_pinnum(const struct device *dev, gpio_pin_t pin)
+{
+	const struct ambiq_gpio_config *const dev_cfg = dev->config;
+
+#if defined(CONFIG_SOC_SERIES_APOLLO3X)
+	pin += dev_cfg->offset;
+#else
+	pin += (dev_cfg->offset >> 2);
+#endif
+	return pin;
+}
+
 #if defined(CONFIG_SOC_SERIES_APOLLO3X)
 /* Apollo3 GPIO banks share the same irq number, connect irq here will cause build error, so we
  * leave this function blank here and do it in ambiq_gpio_cfg_func
diff --git a/drivers/gpio/gpio_cc23x0.c b/drivers/gpio/gpio_cc23x0.c
new file mode 100644
index 00000000000..b39c7b3ec9d
--- /dev/null
+++ b/drivers/gpio/gpio_cc23x0.c
@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ti_cc23x0_gpio
+
+#include <zephyr/types.h>
+#include <zephyr/device.h>
+#include <zephyr/irq.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_utils.h>
+
+#include <driverlib/clkctl.h>
+#include <driverlib/gpio.h>
+#include <inc/hw_ioc.h>
+
+#define IOC_ADDR(index)       (IOC_BASE + IOC_O_IOC0 + (sizeof(uint32_t) * (index)))
+
+struct gpio_cc23x0_config {
+	/* gpio_driver_config needs to be first */
+	struct gpio_driver_config common;
+};
+
+struct gpio_cc23x0_data {
+	/* gpio_driver_data needs to be first */
+	struct gpio_driver_data common;
+	sys_slist_t callbacks;
+};
+
+static void set_pin_mask_non_atomic(uint8_t index, uint32_t registerBaseAddress)
+{
+	GPIOSetConfigDio(GPIO_BASE + registerBaseAddress, BIT(index));
+}
+
+static int gpio_cc23x0_config(const struct device *port, gpio_pin_t pin, gpio_flags_t flags)
+{
+	uint32_t config = 0;
+	uint32_t iocfg_reg = IOC_ADDR(pin);
+	gpio_flags_t direction = flags & GPIO_DIR_MASK;
+
+	if (flags & GPIO_PULL_UP) {
+		config |= IOC_IOC0_PULLCTL_PULL_UP;
+	} else if (flags & GPIO_PULL_DOWN) {
+		config |= IOC_IOC0_PULLCTL_PULL_DOWN;
+	} else {
+		config |= IOC_IOC0_PULLCTL_PULL_DIS;
+	}
+
+	if (!(flags & GPIO_SINGLE_ENDED)) {
+		config |= IOC_IOC0_IOMODE_NORMAL;
+	} else {
+		if (flags & GPIO_LINE_OPEN_DRAIN) {
+			config |= IOC_IOC0_IOMODE_OPEND;
+		} else {
+			config |= IOC_IOC0_IOMODE_OPENS;
+		}
+	}
+	if (direction & GPIO_INPUT) {
+		config |= IOC_IOC0_INPEN_EN | IOC_IOC0_HYSTEN_EN;
+	}
+
+	GPIOSetConfigDio(iocfg_reg, config);
+
+	if (flags & GPIO_OUTPUT) {
+		if (flags & GPIO_OUTPUT_INIT_HIGH) {
+			GPIOSetDio(pin);
+		} else if (flags & GPIO_OUTPUT_INIT_LOW) {
+			GPIOClearDio(pin);
+		}
+		GPIOSetOutputEnableDio(pin, GPIO_OUTPUT_ENABLE);
+	} else {
+		GPIOSetOutputEnableDio(pin, GPIO_OUTPUT_DISABLE);
+	}
+	return 0;
+}
+
+#ifdef CONFIG_GPIO_GET_CONFIG
+static int gpio_cc23x0_get_config(const struct device *port, gpio_pin_t pin, gpio_flags_t *flags)
+{
+	uint32_t out_flag = 0;
+	uint32_t iocfg_reg = IOC_ADDR(pin);
+	uint32_t config = GPIOGetConfigDio(iocfg_reg);
+
+	/* GPIO input/output configuration flags */
+	if (config & IOC_IOC0_INPEN_EN) {
+		out_flag |= GPIO_INPUT;
+	}
+
+	if (GPIOGetOutputEnableDio(pin)) {
+		out_flag |= GPIO_OUTPUT;
+
+		if (GPIOReadDio(pin)) {
+			out_flag |= GPIO_OUTPUT_INIT_HIGH;
+		} else {
+			/* This is the default value. If not explicitly set,
+			 * the returned config will not be symmetric
+			 */
+			out_flag |= GPIO_OUTPUT_INIT_LOW;
+		}
+	}
+
+	/* GPIO interrupt configuration flags */
+	if ((config & IOC_IOC0_EDGEDET_M) != IOC_IOC0_EDGEDET_EDGE_DIS) {
+		if (config & IOC_IOC0_EDGEDET_EDGE_POS) {
+			out_flag |= GPIO_INT_EDGE_RISING;
+		}
+
+		if (config & IOC_IOC0_EDGEDET_EDGE_NEG) {
+			out_flag |= GPIO_INT_EDGE_FALLING;
+		}
+	} else {
+		/* This is the default value. If not explicitly set,
+		 * the returned config will not be symmetric
+		 */
+		out_flag |= GPIO_INT_DISABLE;
+	}
+
+	/* GPIO pin drive flags */
+	if (config & IOC_IOC0_IOMODE_OPENS) {
+		out_flag |= GPIO_OPEN_SOURCE;
+	}
+
+	if (config & IOC_IOC0_IOMODE_OPEND) {
+		out_flag |= IOC_IOC0_IOMODE_OPEND;
+	}
+
+	if (config & IOC_IOC0_PULLCTL_PULL_UP) {
+		out_flag |= GPIO_PULL_UP;
+	}
+
+	if (config & IOC_IOC0_PULLCTL_PULL_DOWN) {
+		out_flag |= GPIO_PULL_DOWN;
+	}
+
+	*flags = out_flag;
+
+	return 0;
+}
+#endif
+
+static int gpio_cc23x0_port_get_raw(const struct device *port, uint32_t *value)
+{
+	*value = GPIOReadMultiDio(GPIO_DIO_ALL_MASK);
+
+	return 0;
+}
+
+static int gpio_cc23x0_port_set_masked_raw(const struct device *port, uint32_t mask, uint32_t value)
+{
+	GPIOWriteMultiDio(mask, value);
+
+	return 0;
+}
+
+static int gpio_cc23x0_port_set_bits_raw(const struct device *port, uint32_t mask)
+{
+	GPIOSetMultiDio(mask);
+
+	return 0;
+}
+
+static int gpio_cc23x0_port_clear_bits_raw(const struct device *port, uint32_t mask)
+{
+	GPIOClearMultiDio(mask);
+
+	return 0;
+}
+
+static int gpio_cc23x0_port_toggle_bits(const struct device *port, uint32_t mask)
+{
+	GPIOToggleMultiDio(mask);
+
+	return 0;
+}
+
+static int gpio_cc23x0xx_pin_interrupt_configure(const struct device *port, gpio_pin_t pin,
+						 enum gpio_int_mode mode, enum gpio_int_trig trig)
+{
+	if (mode == GPIO_INT_MODE_LEVEL) {
+		return ENOTSUP;
+	}
+
+	uint32_t config = GPIOGetConfigDio(IOC_ADDR(pin)) & ~IOC_IOC0_EDGEDET_M;
+
+	if (mode == GPIO_INT_MODE_DISABLED) {
+		config |= IOC_IOC1_EDGEDET_EDGE_DIS;
+
+		GPIOSetConfigDio(IOC_ADDR(pin), config);
+
+		/* Disable interrupt mask */
+		set_pin_mask_non_atomic(pin, GPIO_O_IMCLR);
+
+	} else if (mode == GPIO_INT_MODE_EDGE) {
+		switch (trig) {
+		case GPIO_INT_TRIG_LOW:
+			config |= IOC_IOC1_EDGEDET_EDGE_NEG;
+			break;
+		case GPIO_INT_TRIG_HIGH:
+			config |= IOC_IOC1_EDGEDET_EDGE_POS;
+			break;
+		case GPIO_INT_TRIG_BOTH:
+			config |= IOC_IOC1_EDGEDET_EDGE_BOTH;
+			break;
+		default:
+			return ENOTSUP;
+		}
+
+		GPIOSetConfigDio(IOC_ADDR(pin), config);
+
+		/* Enable interrupt mask */
+		set_pin_mask_non_atomic(pin, GPIO_O_ICLR);
+		set_pin_mask_non_atomic(pin, GPIO_O_IMSET);
+	}
+
+	return 0;
+}
+
+static int gpio_cc23x0_manage_callback(const struct device *port, struct gpio_callback *callback,
+				       bool set)
+{
+	struct gpio_cc23x0_data *data = port->data;
+
+	return gpio_manage_callback(&data->callbacks, callback, set);
+}
+
+static uint32_t gpio_cc23x0_get_pending_int(const struct device *dev)
+{
+	return GPIOGetEventMultiDio(GPIO_DIO_ALL_MASK);
+}
+
+static void gpio_cc23x0_isr(const struct device *dev)
+{
+	struct gpio_cc23x0_data *data = dev->data;
+
+	uint32_t status = GPIOGetEventMultiDio(GPIO_DIO_ALL_MASK);
+
+	GPIOClearEventMultiDio(status);
+
+	gpio_fire_callbacks(&data->callbacks, dev, status);
+}
+
+static int gpio_cc23x0_init(const struct device *dev)
+{
+	/* Enable GPIO domain clock */
+	CLKCTLEnable(CLKCTL_BASE, CLKCTL_GPIO);
+
+	/* Enable IRQ */
+	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), gpio_cc23x0_isr,
+		    DEVICE_DT_INST_GET(0), 0);
+
+	irq_enable(DT_INST_IRQN(0));
+
+	return 0;
+}
+
+static DEVICE_API(gpio, gpio_cc23x0_driver_api) = {
+	.pin_configure = gpio_cc23x0_config,
+#ifdef CONFIG_GPIO_GET_CONFIG
+	.pin_get_config = gpio_cc23x0_get_config,
+#endif
+	.port_get_raw = gpio_cc23x0_port_get_raw,
+	.port_set_masked_raw = gpio_cc23x0_port_set_masked_raw,
+	.port_set_bits_raw = gpio_cc23x0_port_set_bits_raw,
+	.port_clear_bits_raw = gpio_cc23x0_port_clear_bits_raw,
+	.port_toggle_bits = gpio_cc23x0_port_toggle_bits,
+	.pin_interrupt_configure = gpio_cc23x0xx_pin_interrupt_configure,
+	.manage_callback = gpio_cc23x0_manage_callback,
+	.get_pending_int = gpio_cc23x0_get_pending_int,
+};
+
+static const struct gpio_cc23x0_config gpio_cc23x0_config_0 = {
+	.common = {/* Read ngpios from DT */
+		   .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(0)}};
+
+static struct gpio_cc23x0_data gpio_cc23x0_data_0;
+
+DEVICE_DT_INST_DEFINE(0, gpio_cc23x0_init, NULL, &gpio_cc23x0_data_0, &gpio_cc23x0_config_0,
+		      PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_cc23x0_driver_api);
diff --git a/drivers/gpio/gpio_cmsdk_ahb.c b/drivers/gpio/gpio_cmsdk_ahb.c
index fae16ac3159..476f905fc80 100644
--- a/drivers/gpio/gpio_cmsdk_ahb.c
+++ b/drivers/gpio/gpio_cmsdk_ahb.c
@@ -96,8 +96,7 @@ static int gpio_cmsdk_ahb_port_toggle_bits(const struct device *dev,
 	return 0;
 }
 
-static int cmsdk_ahb_gpio_config(const struct device *dev, uint32_t mask,
-				 gpio_flags_t flags)
+int cmsdk_ahb_gpio_config(const struct device *dev, uint32_t mask, gpio_flags_t flags)
 {
 	const struct gpio_cmsdk_ahb_cfg * const cfg = dev->config;
 
diff --git a/drivers/gpio/gpio_davinci.c b/drivers/gpio/gpio_davinci.c
index b0f30adf2d9..a1168311002 100644
--- a/drivers/gpio/gpio_davinci.c
+++ b/drivers/gpio/gpio_davinci.c
@@ -1,6 +1,7 @@
 /*
  * Copyright (C) 2023 BeagleBoard.org Foundation
  * Copyright (C) 2023 S Prashanth
+ * Copyright (C) 2025 Siemens Mobility GmbH
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -53,8 +54,8 @@ struct gpio_davinci_data {
 };
 
 struct gpio_davinci_config {
-	void (*bank_config)(const struct device *dev);
 	struct gpio_driver_config common;
+	void (*bank_config)(const struct device *dev);
 
 	DEVICE_MMIO_NAMED_ROM(port_base);
 
diff --git a/drivers/gpio/gpio_ene_kb1200.c b/drivers/gpio/gpio_ene_kb1200.c
index fb72fd564b0..cc607437419 100644
--- a/drivers/gpio/gpio_ene_kb1200.c
+++ b/drivers/gpio/gpio_ene_kb1200.c
@@ -10,6 +10,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/drivers/gpio/gpio_utils.h>
 #include <zephyr/sys/util_macro.h>
+#include <zephyr/dt-bindings/gpio/ene-kb1200-gpio.h>
 #include <reg/gpio.h>
 #include <reg/gptd.h>
 
@@ -42,35 +43,51 @@ static int kb1200_gpio_pin_configure(const struct device *dev, gpio_pin_t pin, g
 	const struct gpio_kb1200_config *config = dev->config;
 
 	WRITE_BIT(config->gpio_regs->GPIOFS, pin, 0);
-	if ((flags & GPIO_OUTPUT) != 0) {
-		WRITE_BIT(config->gpio_regs->GPIOIE, pin, 1);
-		if ((flags & GPIO_SINGLE_ENDED) != 0) {
+	/* ene specific flags. low voltage mode,input voltage threshold (ViH & ViL) support 1.8V */
+	if (flags & KB1200_GPIO_VOLTAGE_POS) {
+		WRITE_BIT(config->gpio_regs->GPIOLV, pin, 1);
+	} else {
+		WRITE_BIT(config->gpio_regs->GPIOLV, pin, 0);
+	}
+	/* ene specific flags. max current driving ability, max support 16 mA */
+	if (flags & KB1200_GPIO_DRIVING_16MA) {
+		WRITE_BIT(config->gpio_regs->GPIODC, pin, 1);
+	} else {
+		WRITE_BIT(config->gpio_regs->GPIODC, pin, 0);
+	}
+	/* pull-up function */
+	if (flags & GPIO_PULL_UP) {
+		WRITE_BIT(config->gpio_regs->GPIOPU, pin, 1);
+	} else {
+		WRITE_BIT(config->gpio_regs->GPIOPU, pin, 0);
+	}
+	/* output data high/low */
+	if (flags & GPIO_OUTPUT_INIT_HIGH) {
+		WRITE_BIT(config->gpio_regs->GPIOD, pin, 1);
+	} else if (flags & GPIO_OUTPUT_INIT_LOW) {
+		WRITE_BIT(config->gpio_regs->GPIOD, pin, 0);
+	}
+	/* output enable function */
+	if (flags & GPIO_OUTPUT) {
+		/* setting open-drain only when output is enabled */
+		/* output type push-pull/open-drain */
+		if (flags & GPIO_SINGLE_ENDED) {
 			if (flags & GPIO_LINE_OPEN_DRAIN) {
 				WRITE_BIT(config->gpio_regs->GPIOOD, pin, 1);
+			} else {
+				WRITE_BIT(config->gpio_regs->GPIOOD, pin, 0);
 			}
 		} else {
 			WRITE_BIT(config->gpio_regs->GPIOOD, pin, 0);
 		}
-		if (flags & GPIO_PULL_UP) {
-			WRITE_BIT(config->gpio_regs->GPIOPU, pin, 1);
-		} else {
-			WRITE_BIT(config->gpio_regs->GPIOPU, pin, 0);
-		}
-		if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
-			WRITE_BIT(config->gpio_regs->GPIOD, pin, 1);
-		} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
-			WRITE_BIT(config->gpio_regs->GPIOD, pin, 0);
-		}
 		WRITE_BIT(config->gpio_regs->GPIOOE, pin, 1);
 	} else {
 		WRITE_BIT(config->gpio_regs->GPIOOE, pin, 0);
-		if (flags & GPIO_PULL_UP) {
-			WRITE_BIT(config->gpio_regs->GPIOPU, pin, 1);
-		} else {
-			WRITE_BIT(config->gpio_regs->GPIOPU, pin, 0);
-		}
-		WRITE_BIT(config->gpio_regs->GPIOIE, pin, 1);
+		/* disable open-drain when output is disabled */
+		WRITE_BIT(config->gpio_regs->GPIOOD, pin, 0);
 	}
+	/* input function always enable */
+	WRITE_BIT(config->gpio_regs->GPIOIE, pin, 1);
 	return 0;
 }
 
@@ -203,8 +220,8 @@ static DEVICE_API(gpio, kb1200_gpio_api) = {
 		.gptd_regs = (struct gptd_regs *)DT_INST_REG_ADDR_BY_IDX(n, 1),                    \
 	};                                                                                         \
 	static struct gpio_kb1200_data gpio_kb1200_##n##_data;                                     \
-	DEVICE_DT_INST_DEFINE(n, &kb1200_gpio_##n##_init, NULL, &gpio_kb1200_##n##_data,           \
-			      &port_##n##_kb1200_config, POST_KERNEL,                              \
-			      CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &kb1200_gpio_api);
+	DEVICE_DT_INST_DEFINE(n, kb1200_gpio_##n##_init, NULL, &gpio_kb1200_##n##_data,            \
+			      &port_##n##_kb1200_config, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY,  \
+			      &kb1200_gpio_api);
 
 DT_INST_FOREACH_STATUS_OKAY(KB1200_GPIO_INIT)
diff --git a/drivers/gpio/gpio_esp32.c b/drivers/gpio/gpio_esp32.c
index 9460d3c75c8..be4348aba2d 100644
--- a/drivers/gpio/gpio_esp32.c
+++ b/drivers/gpio/gpio_esp32.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2017 Intel Corporation
- * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2021-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,13 +20,7 @@
 #include <zephyr/device.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/dt-bindings/gpio/espressif-esp32-gpio.h>
-#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
-	defined(CONFIG_SOC_SERIES_ESP32C3) || \
-	defined(CONFIG_SOC_SERIES_ESP32C6)
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-#else
 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
-#endif
 #include <zephyr/kernel.h>
 #include <zephyr/sys/util.h>
 
@@ -41,8 +35,7 @@ LOG_MODULE_REGISTER(gpio_esp32, CONFIG_LOG_DEFAULT_LEVEL);
 #define out_w1ts out_w1ts.val
 #define out_w1tc out_w1tc.val
 /* arch_curr_cpu() is not available for riscv based chips */
-#define CPU_ID()  0
-#define ISR_HANDLER isr_handler_t
+#define ESP32_CPU_ID()  0
 #elif CONFIG_SOC_SERIES_ESP32C3
 /* gpio structs in esp32c3 series are different from xtensa ones */
 #define out out.data
@@ -50,8 +43,7 @@ LOG_MODULE_REGISTER(gpio_esp32, CONFIG_LOG_DEFAULT_LEVEL);
 #define out_w1ts out_w1ts.val
 #define out_w1tc out_w1tc.val
 /* arch_curr_cpu() is not available for riscv based chips */
-#define CPU_ID()  0
-#define ISR_HANDLER isr_handler_t
+#define ESP32_CPU_ID()  0
 #elif defined(CONFIG_SOC_SERIES_ESP32C6)
 /* gpio structs in esp32c6 are also different */
 #define out out.out_data_orig
@@ -59,11 +51,9 @@ LOG_MODULE_REGISTER(gpio_esp32, CONFIG_LOG_DEFAULT_LEVEL);
 #define out_w1ts out_w1ts.val
 #define out_w1tc out_w1tc.val
 /* arch_curr_cpu() is not available for riscv based chips */
-#define CPU_ID()  0
-#define ISR_HANDLER isr_handler_t
+#define ESP32_CPU_ID()  0
 #else
-#define CPU_ID() arch_curr_cpu()->id
-#define ISR_HANDLER intr_handler_t
+#define ESP32_CPU_ID() arch_curr_cpu()->id
 #endif
 
 #ifndef SOC_GPIO_SUPPORT_RTC_INDEPENDENT
@@ -423,7 +413,7 @@ static int gpio_esp32_pin_interrupt_configure(const struct device *port,
 	}
 
 	gpio_ll_set_intr_type(cfg->gpio_base, io_pin, intr_trig_mode);
-	gpio_ll_intr_enable_on_core(cfg->gpio_base, CPU_ID(), io_pin);
+	gpio_ll_intr_enable_on_core(cfg->gpio_base, ESP32_CPU_ID(), io_pin);
 	irq_unlock(key);
 
 	return 0;
@@ -442,7 +432,7 @@ static uint32_t gpio_esp32_get_pending_int(const struct device *dev)
 {
 	const struct gpio_esp32_config *const cfg = dev->config;
 	uint32_t irq_status;
-	uint32_t const core_id = CPU_ID();
+	uint32_t const core_id = ESP32_CPU_ID();
 
 	if (cfg->gpio_port == 0) {
 		gpio_ll_get_intr_status(cfg->gpio_base, core_id, &irq_status);
@@ -458,7 +448,7 @@ static void IRAM_ATTR gpio_esp32_fire_callbacks(const struct device *dev)
 	const struct gpio_esp32_config *const cfg = dev->config;
 	struct gpio_esp32_data *data = dev->data;
 	uint32_t irq_status;
-	uint32_t const core_id = CPU_ID();
+	uint32_t const core_id = ESP32_CPU_ID();
 
 	if (cfg->gpio_port == 0) {
 		gpio_ll_get_intr_status(cfg->gpio_base, core_id, &irq_status);
@@ -482,8 +472,9 @@ static int gpio_esp32_init(const struct device *dev)
 	if (!isr_connected) {
 		int ret = esp_intr_alloc(DT_IRQ_BY_IDX(DT_NODELABEL(gpio0), 0, irq),
 			ESP_PRIO_TO_FLAGS(DT_IRQ_BY_IDX(DT_NODELABEL(gpio0), 0, priority)) |
-			ESP_INT_FLAGS_CHECK(DT_IRQ_BY_IDX(DT_NODELABEL(gpio0), 0, flags)),
-			(ISR_HANDLER)gpio_esp32_isr,
+			ESP_INT_FLAGS_CHECK(DT_IRQ_BY_IDX(DT_NODELABEL(gpio0), 0, flags)) |
+				ESP_INTR_FLAG_IRAM,
+			(intr_handler_t)gpio_esp32_isr,
 			(void *)dev,
 			NULL);
 
diff --git a/drivers/gpio/gpio_gecko.c b/drivers/gpio/gpio_gecko.c
index e9730f6dac8..3b5dca8903c 100644
--- a/drivers/gpio/gpio_gecko.c
+++ b/drivers/gpio/gpio_gecko.c
@@ -26,11 +26,7 @@
 #if DT_NODE_HAS_PROP(id, peripheral_id)
 #define GET_GECKO_GPIO_INDEX(id) DT_INST_PROP(id, peripheral_id)
 #else
-#if defined(CONFIG_SOC_SERIES_EFR32BG22) || \
-	defined(CONFIG_SOC_SERIES_EFR32BG27) || \
-	defined(CONFIG_SOC_SERIES_EFR32MG21) || \
-	defined(CONFIG_SOC_SERIES_EFR32MG24) || \
-	defined(CONFIG_SOC_SERIES_EFR32ZG23)
+#if defined(CONFIG_SOC_FAMILY_SILABS_S2)
 #define GECKO_GPIO_PORT_ADDR_SPACE_SIZE sizeof(GPIO_PORT_TypeDef)
 #else
 #define GECKO_GPIO_PORT_ADDR_SPACE_SIZE sizeof(GPIO_P_TypeDef)
@@ -296,10 +292,10 @@ static int gpio_gecko_pin_interrupt_configure(const struct device *dev,
 	} else {
 		/* Interrupt line is already in use */
 		if ((GPIO->IEN & BIT(pin)) != 0) {
-			/* TODO: Return an error only if request is done for
-			 * a pin from a different port.
-			 */
-			return -EBUSY;
+			/* Check if the interrupt is already configured for this port */
+			if (!(data->int_enabled_mask & BIT(pin))) {
+				return -EBUSY;
+			}
 		}
 
 		bool rising_edge = true;
diff --git a/drivers/gpio/gpio_ite_it51xxx.c b/drivers/gpio/gpio_ite_it51xxx.c
new file mode 100644
index 00000000000..daa49180c5f
--- /dev/null
+++ b/drivers/gpio/gpio_ite_it51xxx.c
@@ -0,0 +1,465 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#define DT_DRV_COMPAT ite_it51xxx_gpio
+
+#include <chip_chipregs.h>
+#include <soc.h>
+#include <soc_dt.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_utils.h>
+#include <zephyr/drivers/interrupt_controller/wuc_ite_it51xxx.h>
+#include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
+#include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(gpio_ite_it51xxx, LOG_LEVEL_ERR);
+
+#define IT515XX_GPIO_MAX_PINS 8
+
+struct it51xxx_gpio_wuc_map_cfg {
+	/* WUC control device structure */
+	const struct device *wucs;
+	/* WUC pin mask */
+	uint8_t mask;
+};
+
+/*
+ * Structure gpio_ite_cfg is about the setting of GPIO
+ * this config will be used at initial time
+ */
+struct gpio_ite_cfg {
+	/* gpio_driver_config needs to be first */
+	struct gpio_driver_config common;
+	/* gpio wake-up input source configuration list */
+	const struct it51xxx_gpio_wuc_map_cfg *wuc_map_list;
+	/* GPIO port data register (bit mapping to pin) */
+	uintptr_t reg_gpdr;
+	/* GPIO port data mirror register (bit mapping to pin) */
+	uintptr_t reg_gpdmr;
+	/* GPIO port output type register (bit mapping to pin) */
+	uintptr_t reg_gpotr;
+	/* GPIO port 1.8V select register (bit mapping to pin) */
+	uintptr_t reg_p18scr;
+	/* GPIO port control register (byte mapping to pin) */
+	uintptr_t reg_gpcr;
+	/* GPIO/KBS function selection register (bit mapping to pin) */
+	uintptr_t reg_ksfselr;
+	/* GPIO's irq */
+	uint8_t gpio_irq[8];
+	/* Support input voltage selection */
+	uint8_t has_volt_sel[8];
+	/* Number of pins per group of GPIO */
+	uint8_t num_pins;
+};
+
+/* Structure gpio_ite_data is about callback function */
+struct gpio_ite_data {
+	struct gpio_driver_data common;
+	struct k_spinlock lock;
+	sys_slist_t callbacks;
+	uint8_t volt_default_set;
+	uint8_t level_isr_high;
+	uint8_t level_isr_low;
+};
+
+/**
+ * Driver functions
+ */
+static int gpio_ite_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
+{
+	const struct gpio_ite_cfg *config = dev->config;
+	struct gpio_ite_data *data = dev->data;
+	uint8_t mask = BIT(pin);
+	int rc = 0;
+
+	/* Don't support "open source" mode */
+	if (((flags & GPIO_SINGLE_ENDED) != 0) && ((flags & GPIO_LINE_OPEN_DRAIN) == 0)) {
+		return -ENOTSUP;
+	}
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	if (flags == GPIO_DISCONNECTED) {
+		sys_write8(GPCR_PORT_PIN_MODE_TRISTATE, config->reg_gpcr + pin);
+		/*
+		 * Since not all GPIOs can be to configured as tri-state,
+		 * prompt error if pin doesn't support the flag.
+		 */
+		if (sys_read8(config->reg_gpcr + pin) != GPCR_PORT_PIN_MODE_TRISTATE) {
+			/* Go back to default setting (input) */
+			sys_write8(GPCR_PORT_PIN_MODE_INPUT, config->reg_gpcr + pin);
+			LOG_ERR("Cannot config the node-gpio@%x, pin=%d as tri-state",
+				(uint32_t)config->reg_gpdr, pin);
+			rc = -ENOTSUP;
+			goto unlock_and_return;
+		}
+		/*
+		 * The following configuration isn't necessary because the pin
+		 * was configured as disconnected.
+		 */
+		rc = 0;
+		goto unlock_and_return;
+	}
+
+	/*
+	 * Select open drain first, so that we don't glitch the signal
+	 * when changing the line to an output.
+	 */
+	if ((uint8_t *)config->reg_gpotr != NULL) {
+		if (flags & GPIO_OPEN_DRAIN) {
+			sys_write8(sys_read8(config->reg_gpotr) | mask, config->reg_gpotr);
+		} else {
+			sys_write8(sys_read8(config->reg_gpotr) & ~mask, config->reg_gpotr);
+		}
+	}
+
+	/* 1.8V or 3.3V */
+	if (config->has_volt_sel[pin]) {
+		gpio_flags_t volt = flags & IT8XXX2_GPIO_VOLTAGE_MASK;
+
+		if (volt == IT8XXX2_GPIO_VOLTAGE_1P8) {
+			__ASSERT(!(flags & GPIO_PULL_UP),
+				 "Don't enable internal pullup if 1.8V voltage is used");
+			sys_write8(sys_read8(config->reg_p18scr) | mask, config->reg_p18scr);
+			data->volt_default_set &= ~mask;
+		} else if (volt == IT8XXX2_GPIO_VOLTAGE_3P3) {
+			sys_write8(sys_read8(config->reg_p18scr) & ~mask, config->reg_p18scr);
+			/*
+			 * A variable is needed to store the difference between
+			 * 3.3V and default so that the flag can be distinguished
+			 * between the two in gpio_ite_get_config.
+			 */
+			data->volt_default_set &= ~mask;
+		} else if (volt == IT8XXX2_GPIO_VOLTAGE_DEFAULT) {
+			sys_write8(sys_read8(config->reg_p18scr) & ~mask, config->reg_p18scr);
+			data->volt_default_set |= mask;
+		} else {
+			rc = -EINVAL;
+			goto unlock_and_return;
+		}
+	}
+
+	/* GPIOK, L N group have to set this register */
+	if ((uint8_t *)config->reg_ksfselr) {
+		sys_write8(sys_read8(config->reg_ksfselr) | mask, config->reg_ksfselr);
+	}
+
+	/* If output, set level before changing type to an output. */
+	if (flags & GPIO_OUTPUT) {
+		if (flags & GPIO_OUTPUT_INIT_HIGH) {
+			sys_write8(sys_read8(config->reg_gpdr) | mask, config->reg_gpdr);
+		} else if (flags & GPIO_OUTPUT_INIT_LOW) {
+			sys_write8(sys_read8(config->reg_gpdr) & ~mask, config->reg_gpdr);
+		}
+	}
+
+	uint8_t reg_gpcr = sys_read8(config->reg_gpcr + pin);
+	/* Set input or output. */
+	/* Handle regular GPIO controller */
+	if (flags & GPIO_OUTPUT) {
+		reg_gpcr = (reg_gpcr | GPCR_PORT_PIN_MODE_OUTPUT) & ~GPCR_PORT_PIN_MODE_INPUT;
+	} else {
+		reg_gpcr = (reg_gpcr | GPCR_PORT_PIN_MODE_INPUT) & ~GPCR_PORT_PIN_MODE_OUTPUT;
+	}
+
+	/* Handle pullup / pulldown */
+	/* Handle regular GPIO controller */
+	if (flags & GPIO_PULL_UP) {
+		reg_gpcr = (reg_gpcr | GPCR_PORT_PIN_MODE_PULLUP) & ~GPCR_PORT_PIN_MODE_PULLDOWN;
+	} else if (flags & GPIO_PULL_DOWN) {
+		reg_gpcr = (reg_gpcr | GPCR_PORT_PIN_MODE_PULLDOWN) & ~GPCR_PORT_PIN_MODE_PULLUP;
+	} else {
+		/* No pull up/down */
+		reg_gpcr &= ~(GPCR_PORT_PIN_MODE_PULLDOWN | GPCR_PORT_PIN_MODE_PULLUP);
+	}
+	sys_write8(reg_gpcr, config->reg_gpcr + pin);
+
+unlock_and_return:
+	k_spin_unlock(&data->lock, key);
+	return rc;
+}
+
+#ifdef CONFIG_GPIO_GET_CONFIG
+static int gpio_ite_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *out_flags)
+{
+	const struct gpio_ite_cfg *config = dev->config;
+	struct gpio_ite_data *data = dev->data;
+	uint8_t mask = BIT(pin);
+	gpio_flags_t flags = 0;
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+	/* push-pull or open-drain */
+	if (sys_read8(config->reg_gpotr) & mask) {
+		flags |= GPIO_OPEN_DRAIN;
+	}
+
+	/* 1.8V or 3.3V */
+	if (config->has_volt_sel[pin]) {
+		if (data->volt_default_set & mask) {
+			flags |= IT8XXX2_GPIO_VOLTAGE_DEFAULT;
+		} else {
+			if (sys_read8(config->reg_p18scr) & mask) {
+				flags |= IT8XXX2_GPIO_VOLTAGE_1P8;
+			} else {
+				flags |= IT8XXX2_GPIO_VOLTAGE_3P3;
+			}
+		}
+	}
+
+	/* set input or output. */
+	if (sys_read8(config->reg_gpcr + pin) & GPCR_PORT_PIN_MODE_OUTPUT) {
+		flags |= GPIO_OUTPUT;
+
+		/* set level */
+		if (sys_read8(config->reg_gpdr) & mask) {
+			flags |= GPIO_OUTPUT_HIGH;
+		} else {
+			flags |= GPIO_OUTPUT_LOW;
+		}
+	}
+
+	if (sys_read8(config->reg_gpcr + pin) & GPCR_PORT_PIN_MODE_INPUT) {
+		flags |= GPIO_INPUT;
+
+		/* pullup / pulldown */
+		if (sys_read8(config->reg_gpcr + pin) & GPCR_PORT_PIN_MODE_PULLUP) {
+			flags |= GPIO_PULL_UP;
+		}
+
+		if (sys_read8(config->reg_gpcr + pin) & GPCR_PORT_PIN_MODE_PULLDOWN) {
+			flags |= GPIO_PULL_DOWN;
+		}
+	}
+
+	*out_flags = flags;
+	k_spin_unlock(&data->lock, key);
+
+	return 0;
+}
+#endif
+
+static int gpio_ite_port_get_raw(const struct device *dev, gpio_port_value_t *value)
+{
+	const struct gpio_ite_cfg *config = dev->config;
+
+	/* Get raw bits of GPIO mirror register */
+	*value = sys_read8(config->reg_gpdmr);
+
+	return 0;
+}
+
+static int gpio_ite_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
+					gpio_port_value_t value)
+{
+	const struct gpio_ite_cfg *config = dev->config;
+	struct gpio_ite_data *data = dev->data;
+	uint8_t masked_value = value & mask;
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+	uint8_t out = sys_read8(config->reg_gpdr);
+
+	sys_write8(((out & ~mask) | masked_value), config->reg_gpdr);
+	k_spin_unlock(&data->lock, key);
+
+	return 0;
+}
+
+static int gpio_ite_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
+{
+	const struct gpio_ite_cfg *config = dev->config;
+	struct gpio_ite_data *data = dev->data;
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+	/* Set raw bits of GPIO data register */
+	sys_write8(sys_read8(config->reg_gpdr) | pins, config->reg_gpdr);
+	k_spin_unlock(&data->lock, key);
+
+	return 0;
+}
+
+static int gpio_ite_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
+{
+	const struct gpio_ite_cfg *config = dev->config;
+	struct gpio_ite_data *data = dev->data;
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+	/* Clear raw bits of GPIO data register */
+	sys_write8(sys_read8(config->reg_gpdr) & ~pins, config->reg_gpdr);
+	k_spin_unlock(&data->lock, key);
+
+	return 0;
+}
+
+static int gpio_ite_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
+{
+	const struct gpio_ite_cfg *config = dev->config;
+	struct gpio_ite_data *data = dev->data;
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+	/* Toggle raw bits of GPIO data register */
+	sys_write8(sys_read8(config->reg_gpdr) ^ pins, config->reg_gpdr);
+	k_spin_unlock(&data->lock, key);
+
+	return 0;
+}
+
+static int gpio_ite_manage_callback(const struct device *dev, struct gpio_callback *callback,
+				    bool set)
+{
+	struct gpio_ite_data *data = dev->data;
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+	int rc = gpio_manage_callback(&data->callbacks, callback, set);
+
+	k_spin_unlock(&data->lock, key);
+
+	return rc;
+}
+
+static void gpio_ite_isr(const void *arg)
+{
+	const struct device *dev = arg;
+	const struct gpio_ite_cfg *config = dev->config;
+	struct gpio_ite_data *data = dev->data;
+	uint8_t irq = ite_intc_get_irq_num();
+	uint8_t num_pins = config->num_pins;
+	uint8_t pin;
+
+	for (pin = 0; pin < num_pins; pin++) {
+		if (irq == config->gpio_irq[pin]) {
+			/* Should be safe even without spinlock. */
+			/* Clear the WUC status register. */
+			it51xxx_wuc_clear_status(config->wuc_map_list[pin].wucs,
+						 config->wuc_map_list[pin].mask);
+			/* The callbacks are user code, and therefore should
+			 * not hold the lock.
+			 */
+			gpio_fire_callbacks(&data->callbacks, dev, BIT(pin));
+
+			break;
+		}
+	}
+}
+
+static int gpio_ite_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
+					    enum gpio_int_mode mode, enum gpio_int_trig trig)
+{
+	const struct gpio_ite_cfg *config = dev->config;
+	uint32_t flags;
+	uint8_t gpio_irq = config->gpio_irq[pin];
+	struct gpio_ite_data *data = dev->data;
+
+	if (!gpio_irq) {
+		LOG_ERR("Unsupport interrupt pin");
+		return -ENOTSUP;
+	}
+
+#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
+	if (mode == GPIO_INT_MODE_DISABLED || mode == GPIO_INT_MODE_DISABLE_ONLY) {
+#else
+	if (mode == GPIO_INT_MODE_DISABLED) {
+#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
+		/* Disable GPIO interrupt */
+		irq_disable(gpio_irq);
+		return 0;
+#ifdef CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT
+	} else if (mode == GPIO_INT_MODE_ENABLE_ONLY) {
+		/* Only enable GPIO interrupt */
+		irq_enable(gpio_irq);
+		return 0;
+#endif /* CONFIG_GPIO_ENABLE_DISABLE_INTERRUPT */
+	}
+
+	/* Disable irq before configuring it */
+	irq_disable(gpio_irq);
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	if (mode == GPIO_INT_MODE_LEVEL) {
+		flags = WUC_TYPE_LEVEL_TRIG;
+		if (trig & GPIO_INT_TRIG_HIGH) {
+			flags |= WUC_TYPE_LEVEL_HIGH;
+		} else {
+			flags |= WUC_TYPE_LEVEL_LOW;
+		}
+	} else {
+		switch (trig) {
+		case GPIO_INT_TRIG_LOW:
+			flags = WUC_TYPE_EDGE_FALLING;
+			break;
+		case GPIO_INT_TRIG_HIGH:
+			flags = WUC_TYPE_EDGE_RISING;
+			break;
+		case GPIO_INT_TRIG_BOTH:
+			flags = WUC_TYPE_EDGE_BOTH;
+			break;
+		default:
+			k_spin_unlock(&data->lock, key);
+			return -EINVAL;
+		}
+	}
+	/* Select wakeup interrupt edge triggered type of GPIO pins */
+	it51xxx_wuc_set_polarity(config->wuc_map_list[pin].wucs, config->wuc_map_list[pin].mask,
+				 flags);
+	/*
+	 * Always write 1 to clear the WUC status register after
+	 * modifying edge mode selection register (WUBEMR and WUEMR).
+	 */
+	it51xxx_wuc_clear_status(config->wuc_map_list[pin].wucs, config->wuc_map_list[pin].mask);
+	/* Enable wakeup interrupt of GPIO pins */
+	it51xxx_wuc_enable(config->wuc_map_list[pin].wucs, config->wuc_map_list[pin].mask);
+
+	k_spin_unlock(&data->lock, key);
+
+	/* Enable GPIO interrupt */
+	irq_connect_dynamic(gpio_irq, 0, gpio_ite_isr, dev, 0);
+	irq_enable(gpio_irq);
+
+	return 0;
+}
+
+static DEVICE_API(gpio, gpio_ite_driver_api) = {
+	.pin_configure = gpio_ite_configure,
+#ifdef CONFIG_GPIO_GET_CONFIG
+	.pin_get_config = gpio_ite_get_config,
+#endif
+	.port_get_raw = gpio_ite_port_get_raw,
+	.port_set_masked_raw = gpio_ite_port_set_masked_raw,
+	.port_set_bits_raw = gpio_ite_port_set_bits_raw,
+	.port_clear_bits_raw = gpio_ite_port_clear_bits_raw,
+	.port_toggle_bits = gpio_ite_port_toggle_bits,
+	.pin_interrupt_configure = gpio_ite_pin_interrupt_configure,
+	.manage_callback = gpio_ite_manage_callback,
+};
+
+#define GPIO_ITE_DEV_CFG_DATA(inst)                                                                \
+	BUILD_ASSERT(DT_INST_PROP(inst, ngpios) <= IT515XX_GPIO_MAX_PINS,                          \
+		     "The maximum number of pins per port is 8.");                                 \
+	static const struct it51xxx_gpio_wuc_map_cfg                                               \
+		it51xxx_gpio_wuc_##inst[IT8XXX2_DT_INST_WUCCTRL_LEN(inst)] =                       \
+			IT8XXX2_DT_WUC_ITEMS_LIST(inst);                                           \
+	static struct gpio_ite_data gpio_ite_data_##inst;                                          \
+	static const struct gpio_ite_cfg gpio_ite_cfg_##inst = {                                   \
+		.common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst)},                \
+		.wuc_map_list = it51xxx_gpio_wuc_##inst,                                           \
+		.reg_gpdr = DT_INST_REG_ADDR_BY_IDX(inst, 0),                                      \
+		.reg_gpdmr = DT_INST_REG_ADDR_BY_IDX(inst, 1),                                     \
+		.reg_gpotr = DT_INST_REG_ADDR_BY_IDX(inst, 2),                                     \
+		.reg_p18scr = DT_INST_REG_ADDR_BY_IDX(inst, 3),                                    \
+		.reg_gpcr = DT_INST_REG_ADDR_BY_IDX(inst, 4),                                      \
+		.reg_ksfselr = DT_INST_REG_ADDR_BY_IDX(inst, 5),                                   \
+		.gpio_irq = IT8XXX2_DT_GPIO_IRQ_LIST(inst),                                        \
+		.has_volt_sel = DT_INST_PROP_OR(inst, has_volt_sel, {0}),                          \
+		.num_pins = DT_INST_PROP(inst, ngpios),                                            \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(inst, NULL, NULL, &gpio_ite_data_##inst, &gpio_ite_cfg_##inst,       \
+			      PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_ite_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(GPIO_ITE_DEV_CFG_DATA)
diff --git a/drivers/gpio/gpio_ite_it8801.c b/drivers/gpio/gpio_ite_it8801.c
index ca2423f76f2..94cd36a0f1c 100644
--- a/drivers/gpio/gpio_ite_it8801.c
+++ b/drivers/gpio/gpio_ite_it8801.c
@@ -60,7 +60,7 @@ static int gpio_it8801_configure(const struct device *dev, gpio_pin_t pin, gpio_
 	int ret;
 	uint8_t reg_gpcr = config->reg_gpcr + pin;
 	uint8_t mask = BIT(pin);
-	uint8_t new_value, control;
+	uint8_t control;
 
 	/* Don't support "open source" mode */
 	if (((flags & GPIO_SINGLE_ENDED) != 0) && ((flags & GPIO_LINE_OPEN_DRAIN) == 0)) {
@@ -86,13 +86,11 @@ static int gpio_it8801_configure(const struct device *dev, gpio_pin_t pin, gpio_
 	/* If output, set level before changing type to an output. */
 	if (flags & GPIO_OUTPUT) {
 		if (flags & GPIO_OUTPUT_INIT_HIGH) {
-			new_value = mask;
+			ret = i2c_reg_update_byte_dt(&config->i2c_dev, config->reg_sovr, mask,
+						     mask);
 		} else if (flags & GPIO_OUTPUT_INIT_LOW) {
-			new_value = 0;
-		} else {
-			new_value = 0;
+			ret = i2c_reg_update_byte_dt(&config->i2c_dev, config->reg_sovr, mask, 0);
 		}
-		ret = i2c_reg_update_byte_dt(&config->i2c_dev, config->reg_sovr, mask, new_value);
 		if (ret) {
 			LOG_ERR("Failed to set output value (ret %d)", ret);
 			return ret;
diff --git a/drivers/gpio/gpio_ite_it8xxx2_v2.c b/drivers/gpio/gpio_ite_it8xxx2_v2.c
index e19345ca997..3a1b04c4873 100644
--- a/drivers/gpio/gpio_ite_it8xxx2_v2.c
+++ b/drivers/gpio/gpio_ite_it8xxx2_v2.c
@@ -27,6 +27,8 @@
 
 LOG_MODULE_REGISTER(gpio_it8xxx2, LOG_LEVEL_ERR);
 
+#define ITE_GPIO_MAX_PINS 8
+
 /*
  * Structure gpio_ite_cfg is about the setting of GPIO
  * this config will be used at initial time
@@ -529,33 +531,27 @@ static int gpio_ite_init(const struct device *dev)
 	return 0;
 }
 
-#define GPIO_ITE_DEV_CFG_DATA(inst)                                \
-static struct gpio_ite_data gpio_ite_data_##inst;                  \
-static const struct gpio_ite_cfg gpio_ite_cfg_##inst = {           \
-	.common = {                                                \
-		.port_pin_mask =                                   \
-			GPIO_PORT_PIN_MASK_FROM_DT_INST(inst)      \
-	},                                                         \
-	.reg_gpdr = DT_INST_REG_ADDR_BY_IDX(inst, 0),              \
-	.reg_gpdmr = DT_INST_REG_ADDR_BY_IDX(inst, 1),             \
-	.reg_gpotr = DT_INST_REG_ADDR_BY_IDX(inst, 2),             \
-	.reg_p18scr = DT_INST_REG_ADDR_BY_IDX(inst, 3),            \
-	.reg_gpcr = DT_INST_REG_ADDR_BY_IDX(inst, 4),              \
-	.wuc_base = DT_INST_PROP_OR(inst, wuc_base, {0}),          \
-	.wuc_mask = DT_INST_PROP_OR(inst, wuc_mask, {0}),          \
-	.gpio_irq = IT8XXX2_DT_GPIO_IRQ_LIST(inst),                \
-	.has_volt_sel = DT_INST_PROP_OR(inst, has_volt_sel, {0}),  \
-	.num_pins = DT_INST_PROP(inst, ngpios),                    \
-	.kbs_ctrl = DT_INST_PROP_OR(inst, keyboard_controller, 0), \
-	};                                                         \
-DEVICE_DT_INST_DEFINE(inst,                                        \
-		      gpio_ite_init,                               \
-		      NULL,                                        \
-		      &gpio_ite_data_##inst,                       \
-		      &gpio_ite_cfg_##inst,                        \
-		      PRE_KERNEL_1,                                \
-		      CONFIG_GPIO_INIT_PRIORITY,                   \
-		      &gpio_ite_driver_api);
+#define GPIO_ITE_DEV_CFG_DATA(inst)                                                                \
+	BUILD_ASSERT(DT_INST_PROP(inst, ngpios) <= ITE_GPIO_MAX_PINS,                              \
+		     "The maximum number of pins per port is 8.");                                 \
+	static struct gpio_ite_data gpio_ite_data_##inst;                                          \
+	static const struct gpio_ite_cfg gpio_ite_cfg_##inst = {                                   \
+		.common = {.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst)},                \
+		.reg_gpdr = DT_INST_REG_ADDR_BY_IDX(inst, 0),                                      \
+		.reg_gpdmr = DT_INST_REG_ADDR_BY_IDX(inst, 1),                                     \
+		.reg_gpotr = DT_INST_REG_ADDR_BY_IDX(inst, 2),                                     \
+		.reg_p18scr = DT_INST_REG_ADDR_BY_IDX(inst, 3),                                    \
+		.reg_gpcr = DT_INST_REG_ADDR_BY_IDX(inst, 4),                                      \
+		.wuc_base = DT_INST_PROP_OR(inst, wuc_base, {0}),                                  \
+		.wuc_mask = DT_INST_PROP_OR(inst, wuc_mask, {0}),                                  \
+		.gpio_irq = IT8XXX2_DT_GPIO_IRQ_LIST(inst),                                        \
+		.has_volt_sel = DT_INST_PROP_OR(inst, has_volt_sel, {0}),                          \
+		.num_pins = DT_INST_PROP(inst, ngpios),                                            \
+		.kbs_ctrl = DT_INST_PROP_OR(inst, keyboard_controller, 0),                         \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(inst, gpio_ite_init, NULL, &gpio_ite_data_##inst,                    \
+			      &gpio_ite_cfg_##inst, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY,       \
+			      &gpio_ite_driver_api);
 
 DT_INST_FOREACH_STATUS_OKAY(GPIO_ITE_DEV_CFG_DATA)
 
diff --git a/drivers/gpio/gpio_max14916.c b/drivers/gpio/gpio_max14916.c
index dd7f6a46bee..86dcb20372d 100644
--- a/drivers/gpio/gpio_max14916.c
+++ b/drivers/gpio/gpio_max14916.c
@@ -20,8 +20,6 @@ LOG_MODULE_REGISTER(gpio_max14916);
 #include "gpio_max14916.h"
 #include "gpio_max149x6.h"
 
-#define DT_DRV_COMPAT adi_max14916_gpio
-
 static int gpio_max14916_diag_chan_get(const struct device *dev);
 
 static int max14916_pars_spi_diag(const struct device *dev, uint8_t *rx_diag_buff, uint8_t rw)
@@ -367,8 +365,8 @@ static DEVICE_API(gpio, gpio_max14916_api) = {
 	.port_toggle_bits = gpio_max14916_port_toggle_bits,
 };
 
-#define GPIO_MAX14906_DEVICE(id)                                                                   \
-	static const struct max14916_config max14916_##id##_cfg = {                                \
+#define GPIO_MAX14906_DEVICE(id, model)                                                            \
+	static const struct max14916_config max##model##_##id##_cfg = {                            \
 		.spi = SPI_DT_SPEC_INST_GET(id, SPI_OP_MODE_MASTER | SPI_WORD_SET(8U), 0U),        \
 		.ready_gpio = GPIO_DT_SPEC_INST_GET(id, drdy_gpios),                               \
 		.fault_gpio = GPIO_DT_SPEC_INST_GET(id, fault_gpios),                              \
@@ -391,10 +389,16 @@ static DEVICE_API(gpio, gpio_max14916_api) = {
 		.spi_addr = DT_INST_PROP(id, spi_addr),                                            \
 	};                                                                                         \
                                                                                                    \
-	static struct max14916_data max14916_##id##_data;                                          \
+	static struct max14916_data max##model##_##id##_data;                                      \
                                                                                                    \
-	DEVICE_DT_INST_DEFINE(id, &gpio_max14916_init, NULL, &max14916_##id##_data,                \
-			      &max14916_##id##_cfg, POST_KERNEL,                                   \
+	DEVICE_DT_INST_DEFINE(id, &gpio_max14916_init, NULL, &max##model##_##id##_data,            \
+			      &max##model##_##id##_cfg, POST_KERNEL,                               \
 			      CONFIG_GPIO_MAX14916_INIT_PRIORITY, &gpio_max14916_api);
 
-DT_INST_FOREACH_STATUS_OKAY(GPIO_MAX14906_DEVICE)
+#undef DT_DRV_COMPAT
+#define DT_DRV_COMPAT adi_max14915_gpio
+DT_INST_FOREACH_STATUS_OKAY_VARGS(GPIO_MAX14906_DEVICE, 14915)
+
+#undef DT_DRV_COMPAT
+#define DT_DRV_COMPAT adi_max14916_gpio
+DT_INST_FOREACH_STATUS_OKAY_VARGS(GPIO_MAX14906_DEVICE, 14916)
diff --git a/drivers/gpio/gpio_max14917.c b/drivers/gpio/gpio_max14917.c
new file mode 100644
index 00000000000..74c87f45688
--- /dev/null
+++ b/drivers/gpio/gpio_max14917.c
@@ -0,0 +1,358 @@
+/*
+ * Copyright (c) 2025 Analog Devices Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/crc.h>
+
+#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(gpio_max14917);
+
+#include <zephyr/drivers/gpio/gpio_utils.h>
+
+#include "gpio_max14917.h"
+
+#define DT_DRV_COMPAT adi_max14917_gpio
+
+static int max14917_reg_trans_spi_diag(const struct device *dev)
+{
+	int ret = 0;
+	uint8_t crc;
+
+	uint8_t local_tx_buff[MAX14917_MAX_PKT_SIZE] = {0};
+	uint8_t local_rx_buff[MAX14917_MAX_PKT_SIZE] = {0};
+
+	struct max14917_data *data = dev->data;
+	const struct max14917_config *config = dev->config;
+
+	struct spi_buf tx_buf = {
+		.buf = &local_tx_buff,
+		.len = config->pkt_size,
+	};
+	const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1};
+
+	struct spi_buf rx_buf = {
+		.buf = &local_rx_buff,
+		.len = config->pkt_size,
+	};
+	const struct spi_buf_set rx = {.buffers = &rx_buf, .count = 1};
+
+	local_tx_buff[0] = data->gpios_ON;
+
+	/* If CRC enabled calculate it */
+	if (config->crc_en) {
+		crc = crc8(&local_tx_buff[0], 1, MAX14917_CRC_POLY, MAX14917_CRC_INI_VAL, false);
+		local_tx_buff[1] = (crc & MAX14917_CRC_MASK);
+	}
+
+	/* Perform SPI transaction */
+	ret = spi_transceive_dt(&config->spi, &tx, &rx);
+	if (ret) {
+		LOG_ERR("SPI transfer failed");
+		return ret;
+	}
+
+	/* If CRC enabled check it */
+	if (config->crc_en) {
+		crc = crc8(&local_tx_buff[0], 1, MAX14917_CRC_POLY, MAX14917_CRC_INI_VAL, false);
+		crc = (crc & MAX14917_CRC_MASK);
+		if (crc != (local_rx_buff[1] & 0x1F)) {
+			LOG_ERR("READ CRC ERR (%d)-(%d)\n", crc, (local_rx_buff[1] & 0x1F));
+			return -EINVAL;
+		}
+		/* Set error flags in device data */
+		data->comm_err = (local_rx_buff[1] & MAX14917_COMM_ERR);
+		data->verr = (local_rx_buff[1] & MAX14917_VERR);
+		data->therm_err = (local_rx_buff[1] & MAX14917_THERM_ERR);
+	}
+
+	data->gpios_fault = local_rx_buff[0];
+
+	return 0;
+}
+
+static int max14917_fault_check(const struct device *dev)
+{
+	int ret;
+	const struct max14917_data *data = dev->data;
+	const struct max14917_config *config = dev->config;
+
+	if (gpio_pin_get_dt(&config->fault_gpio)) {
+		LOG_DBG("FAULT GPIO is high");
+	}
+
+	/* Update error flags */
+	ret = max14917_reg_trans_spi_diag(dev);
+	if (ret) {
+		return ret;
+	}
+
+	if (data->comm_err) {
+		LOG_DBG("COMMERR flag is active");
+	}
+	if (data->verr) {
+		LOG_DBG("VERR flag is active");
+	}
+	if (data->therm_err) {
+		LOG_DBG("THERMERR flag is active");
+	}
+
+	for (int i = 0; i < MAX14917_CHANNELS; i++) {
+		if (data->gpios_fault & BIT(i)) {
+			LOG_DBG("Channel %d has a fault", i);
+		}
+	}
+
+	return 0;
+}
+
+static int gpio_max14917_init(const struct device *dev)
+{
+	struct max14917_data *data = dev->data;
+	const struct max14917_config *config = dev->config;
+	int err = 0;
+
+	LOG_DBG(" --- GPIO max14917 init IN ---");
+
+	if (!spi_is_ready_dt(&config->spi)) {
+		LOG_ERR("SPI bus is not ready\n");
+		return -ENODEV;
+	}
+
+	/* Output GPIOS */
+	/* setup EN gpio - normal low */
+	if (!gpio_is_ready_dt(&config->en_gpio)) {
+		LOG_ERR("EN GPIO device not ready");
+		return -ENODEV;
+	}
+
+	err = gpio_pin_configure_dt(&config->en_gpio, GPIO_OUTPUT);
+	if (err < 0) {
+		LOG_ERR("Failed to configure EN GPIO");
+		return err;
+	}
+
+	/* setup SYNC gpio - normal low */
+	if (!gpio_is_ready_dt(&config->sync_gpio)) {
+		LOG_ERR("SYNC GPIO device not ready");
+		return -ENODEV;
+	}
+
+	err = gpio_pin_configure_dt(&config->sync_gpio, GPIO_OUTPUT);
+	if (err < 0) {
+		LOG_ERR("Failed to configure SYNC GPIO");
+		return err;
+	}
+	/* setup CRCEN gpio - normal low */
+	if (!gpio_is_ready_dt(&config->crcen_gpio)) {
+		LOG_ERR("CRCEN GPIO device not ready");
+		return -ENODEV;
+	}
+
+	err = gpio_pin_configure_dt(&config->crcen_gpio, GPIO_OUTPUT);
+	if (err < 0) {
+		LOG_ERR("Failed to configure CRCEN GPIO");
+		return err;
+	}
+	/* Input GPIOS */
+	/* setup VDDOK gpio - normal low */
+	if (!gpio_is_ready_dt(&config->vddok_gpio)) {
+		LOG_ERR("VDDOK GPIO device not ready");
+		return -ENODEV;
+	}
+
+	err = gpio_pin_configure_dt(&config->vddok_gpio, GPIO_INPUT);
+	if (err < 0) {
+		LOG_ERR("Failed to configure VDDOK GPIO");
+		return err;
+	}
+	/* setup READY gpio - normal low */
+	if (!gpio_is_ready_dt(&config->ready_gpio)) {
+		LOG_ERR("VDDOK READY device not ready");
+		return -ENODEV;
+	}
+
+	err = gpio_pin_configure_dt(&config->ready_gpio, GPIO_INPUT);
+	if (err < 0) {
+		LOG_ERR("Failed to configure READY GPIO");
+		return err;
+	}
+	/* setup COMERR gpio - normal low */
+	if (!gpio_is_ready_dt(&config->comerr_gpio)) {
+		LOG_ERR("COMERR GPIO device not ready");
+		return -ENODEV;
+	}
+
+	err = gpio_pin_configure_dt(&config->comerr_gpio, GPIO_INPUT);
+	if (err < 0) {
+		LOG_ERR("Failed to configure COMERR GPIO");
+		return err;
+	}
+	/* setup FAULT gpio - normal low */
+	if (!gpio_is_ready_dt(&config->fault_gpio)) {
+		LOG_ERR("FAULT GPIO device not ready");
+		return -ENODEV;
+	}
+
+	err = gpio_pin_configure_dt(&config->fault_gpio, GPIO_INPUT);
+	if (err < 0) {
+		LOG_ERR("Failed to configure FAULT GPIO");
+		return err;
+	}
+
+	err = gpio_pin_set_dt(&config->en_gpio, 1);
+	if (err) {
+		return err;
+	}
+	err = gpio_pin_set_dt(&config->sync_gpio, 1);
+	if (err) {
+		return err;
+	}
+
+	if (config->crc_en) {
+		err = gpio_pin_set_dt(&config->crcen_gpio, 1);
+	} else {
+		err = gpio_pin_set_dt(&config->crcen_gpio, 0);
+	}
+
+	if (err) {
+		return err;
+	}
+
+	/* Initialize satus and fault flags to 0 */
+	data->gpios_ON = 0;
+	data->gpios_fault = 0;
+
+	err = max14917_fault_check(dev);
+
+	return err;
+}
+
+static int gpio_max14917_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
+{
+	int err = 0;
+
+	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
+		return -ENOTSUP;
+	}
+
+	if ((flags & GPIO_SINGLE_ENDED) != 0) {
+		return -ENOTSUP;
+	}
+
+	if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
+		return -ENOTSUP;
+	}
+
+	if (flags & GPIO_INT_ENABLE) {
+		return -ENOTSUP;
+	}
+
+	switch (flags & GPIO_DIR_MASK) {
+	case GPIO_OUTPUT:
+		break;
+	case GPIO_INPUT:
+	default:
+		LOG_ERR("NOT SUPPORTED OPTION!");
+		return -ENOTSUP;
+	}
+
+	return err;
+}
+
+static int gpio_max14917_port_get_raw(const struct device *dev, gpio_port_value_t *value)
+{
+	int ret;
+	const struct max14917_data *data = dev->data;
+
+	ret = max14917_fault_check(dev);
+	if (ret) {
+		return ret;
+	}
+
+	*value = data->gpios_ON;
+
+	return 0;
+}
+
+static int gpio_max14917_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
+{
+	int ret;
+	struct max14917_data *data = dev->data;
+
+	ret = max14917_fault_check(dev);
+	if (ret) {
+		return ret;
+	}
+
+	data->gpios_ON = data->gpios_ON | pins;
+
+	return max14917_reg_trans_spi_diag(dev);
+}
+
+static int gpio_max14917_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
+{
+	int ret;
+	struct max14917_data *data = dev->data;
+
+	ret = max14917_fault_check(dev);
+	if (ret) {
+		return ret;
+	}
+
+	data->gpios_ON = data->gpios_ON & ~pins;
+
+	return max14917_reg_trans_spi_diag(dev);
+}
+
+static int gpio_max14917_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
+{
+	int ret;
+	struct max14917_data *data = dev->data;
+
+	ret = max14917_fault_check(dev);
+	if (ret) {
+		return ret;
+	}
+
+	data->gpios_ON ^= pins;
+
+	return max14917_reg_trans_spi_diag(dev);
+}
+
+static DEVICE_API(gpio, gpio_max14917_api) = {
+	.pin_configure = gpio_max14917_config,
+	.port_get_raw = gpio_max14917_port_get_raw,
+	.port_set_bits_raw = gpio_max14917_port_set_bits_raw,
+	.port_clear_bits_raw = gpio_max14917_port_clear_bits_raw,
+	.port_toggle_bits = gpio_max14917_port_toggle_bits,
+};
+
+#define GPIO_MAX14917_DEVICE(id)                                                                   \
+	static const struct max14917_config max14917_##id##_cfg = {                                \
+		.spi = SPI_DT_SPEC_INST_GET(id, SPI_OP_MODE_MASTER | SPI_WORD_SET(8U), 0U),        \
+		.vddok_gpio = GPIO_DT_SPEC_INST_GET(id, vddok_gpios),                              \
+		.ready_gpio = GPIO_DT_SPEC_INST_GET(id, ready_gpios),                              \
+		.comerr_gpio = GPIO_DT_SPEC_INST_GET(id, comerr_gpios),                            \
+		.fault_gpio = GPIO_DT_SPEC_INST_GET(id, fault_gpios),                              \
+		.en_gpio = GPIO_DT_SPEC_INST_GET(id, en_gpios),                                    \
+		.sync_gpio = GPIO_DT_SPEC_INST_GET(id, sync_gpios),                                \
+		.crcen_gpio = GPIO_DT_SPEC_INST_GET(id, crcen_gpios),                              \
+		.crc_en = DT_INST_PROP(id, crc_en),                                                \
+		.pkt_size = (DT_INST_PROP(id, crc_en) & 0x1) ? 2 : 1,                              \
+	};                                                                                         \
+                                                                                                   \
+	static struct max14917_data max14917_##id##_data;                                          \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(id, &gpio_max14917_init, NULL, &max14917_##id##_data,                \
+			      &max14917_##id##_cfg, POST_KERNEL,                                   \
+			      CONFIG_GPIO_MAX14917_INIT_PRIORITY, &gpio_max14917_api);
+
+DT_INST_FOREACH_STATUS_OKAY(GPIO_MAX14917_DEVICE)
diff --git a/drivers/gpio/gpio_max14917.h b/drivers/gpio/gpio_max14917.h
new file mode 100644
index 00000000000..f23e1a14a9b
--- /dev/null
+++ b/drivers/gpio/gpio_max14917.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2025 Analog Devices Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_GPIO_GPIO_MAX14917_H_
+#define ZEPHYR_DRIVERS_GPIO_GPIO_MAX14917_H_
+
+#define MAX14917_CHANNELS 8
+
+#define MAX14917_MAX_PKT_SIZE 2
+
+#define MAX14917_COMM_ERR  BIT(7)
+#define MAX14917_VERR      BIT(6)
+#define MAX14917_THERM_ERR BIT(5)
+
+#define MAX14917_CRC_POLY       0x15
+#define MAX14917_CRC_INI_VAL    0x1F
+#define MAX14917_CRC_EXTRA_BYTE 0x00
+#define MAX14917_CRC_MASK       0x1F
+
+struct max14917_config {
+	struct spi_dt_spec spi;
+	/* Input gpios */
+	struct gpio_dt_spec vddok_gpio;
+	struct gpio_dt_spec ready_gpio;
+	struct gpio_dt_spec comerr_gpio;
+	struct gpio_dt_spec fault_gpio;
+	/* Output gpios */
+	struct gpio_dt_spec en_gpio;
+	struct gpio_dt_spec sync_gpio;
+	struct gpio_dt_spec crcen_gpio;
+	bool crc_en;
+	uint8_t pkt_size;
+};
+
+struct max14917_data {
+	uint8_t gpios_ON; /* GPIO states */
+	uint8_t gpios_fault;
+	bool comm_err;
+	bool verr;
+	bool therm_err;
+};
+
+#endif
diff --git a/drivers/gpio/gpio_max149x6.h b/drivers/gpio/gpio_max149x6.h
index 3266a219c65..6e2c0c51db5 100644
--- a/drivers/gpio/gpio_max149x6.h
+++ b/drivers/gpio/gpio_max149x6.h
@@ -107,10 +107,6 @@ static int max149x6_reg_transceive(const struct device *dev, uint8_t addr, uint8
 	};
 	const struct spi_buf_set rx = {.buffers = &rx_buf, .count = 1};
 
-	if (config->crc_en & 0) {
-		rx_buf.len++;
-	}
-
 	local_tx_buff[0] = FIELD_PREP(MAX149x6_ADDR_MASK, addr) |
 			   FIELD_PREP(MAX149x6_CHIP_ADDR_MASK, config->spi_addr) |
 			   FIELD_PREP(MAX149x6_RW_MASK, rw & 0x1);
diff --git a/drivers/gpio/gpio_max22017.c b/drivers/gpio/gpio_max22017.c
new file mode 100644
index 00000000000..29b2f08516b
--- /dev/null
+++ b/drivers/gpio/gpio_max22017.c
@@ -0,0 +1,410 @@
+/*
+ * Copyright (c) 2024 Analog Devices Inc.
+ * Copyright (c) 2024 Baylibre SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/kernel.h>
+
+#define DT_DRV_COMPAT adi_max22017_gpio
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(gpio_max22017, CONFIG_GPIO_LOG_LEVEL);
+
+#include <zephyr/drivers/mfd/max22017.h>
+
+#include <zephyr/drivers/gpio/gpio_utils.h>
+
+struct gpio_adi_max22017_config {
+	/* gpio_driver_config needs to be first */
+	struct gpio_driver_config common;
+	const struct device *parent;
+};
+
+struct gpio_adi_max22017_data {
+	/* gpio_driver_data needs to be first */
+	struct gpio_driver_data common;
+#ifdef CONFIG_GPIO_MAX22017_INT_QUIRK
+	struct k_timer int_quirk_timer;
+#endif
+};
+
+#ifdef CONFIG_GPIO_MAX22017_INT_QUIRK
+void isr_quirk_handler(struct k_timer *int_quirk_timer)
+{
+	int ret;
+	struct max22017_data *data = k_timer_user_data_get(int_quirk_timer);
+
+	k_mutex_lock(&data->lock, K_FOREVER);
+
+	ret = k_work_submit(&data->int_work);
+	if (ret < 0) {
+		LOG_WRN("Could not submit int work: %d", ret);
+	}
+
+	k_mutex_unlock(&data->lock);
+}
+#endif
+
+static int adi_max22017_gpio_set_output(const struct device *dev, uint8_t pin, bool initial_value)
+{
+	int ret;
+	uint16_t gpio_data, gpio_ctrl;
+	struct max22017_data *data = dev->data;
+
+	k_mutex_lock(&data->lock, K_FOREVER);
+
+	ret = max22017_reg_read(dev, MAX22017_GEN_GPIO_DATA_OFF, &gpio_data);
+	if (ret) {
+		goto fail;
+	}
+
+	ret = max22017_reg_read(dev, MAX22017_GEN_GPIO_CTRL_OFF, &gpio_ctrl);
+	if (ret) {
+		goto fail;
+	}
+
+	if (initial_value) {
+		gpio_data |= FIELD_PREP(MAX22017_GEN_GPIO_DATA_GPO_DATA, BIT(pin));
+	} else {
+		gpio_data &= ~FIELD_PREP(MAX22017_GEN_GPIO_DATA_GPO_DATA, BIT(pin));
+	}
+
+	gpio_ctrl |= FIELD_PREP(MAX22017_GEN_GPIO_CTRL_GPIO_EN, BIT(pin)) |
+		     FIELD_PREP(MAX22017_GEN_GPIO_CTRL_GPIO_DIR, BIT(pin));
+
+	ret = max22017_reg_write(dev, MAX22017_GEN_GPIO_DATA_OFF, gpio_data);
+	if (ret) {
+		goto fail;
+	}
+
+	ret = max22017_reg_write(dev, MAX22017_GEN_GPIO_CTRL_OFF, gpio_ctrl);
+
+fail:
+	k_mutex_unlock(&data->lock);
+	return ret;
+}
+
+static int adi_max22017_gpio_set_input(const struct device *dev, uint8_t pin)
+{
+	int ret;
+	uint16_t gpio_ctrl;
+	struct max22017_data *data = dev->data;
+
+	k_mutex_lock(&data->lock, K_FOREVER);
+
+	ret = max22017_reg_read(dev, MAX22017_GEN_GPIO_CTRL_OFF, &gpio_ctrl);
+	if (ret) {
+		goto fail;
+	}
+
+	gpio_ctrl |= FIELD_PREP(MAX22017_GEN_GPIO_CTRL_GPIO_EN, BIT(pin));
+	gpio_ctrl &= ~FIELD_PREP(MAX22017_GEN_GPIO_CTRL_GPIO_DIR, BIT(pin));
+
+	ret = max22017_reg_write(dev, MAX22017_GEN_GPIO_CTRL_OFF, gpio_ctrl);
+fail:
+	k_mutex_unlock(&data->lock);
+	return ret;
+}
+
+int adi_max22017_gpio_deconfigure(const struct device *dev, uint8_t pin)
+{
+	int ret;
+	uint16_t gpio_ctrl;
+	struct max22017_data *data = dev->data;
+
+	k_mutex_lock(&data->lock, K_FOREVER);
+
+	ret = max22017_reg_read(dev, MAX22017_GEN_GPIO_CTRL_OFF, &gpio_ctrl);
+	if (ret) {
+		goto fail;
+	}
+
+	gpio_ctrl &= ~FIELD_PREP(MAX22017_GEN_GPIO_CTRL_GPIO_EN, BIT(pin));
+
+	ret = max22017_reg_write(dev, MAX22017_GEN_GPIO_CTRL_OFF, gpio_ctrl);
+fail:
+	k_mutex_unlock(&data->lock);
+	return ret;
+}
+
+int adi_max22017_gpio_set_pin_value(const struct device *dev, uint8_t pin, bool value)
+{
+	int ret;
+	uint16_t gpio_data;
+	struct max22017_data *data = dev->data;
+
+	k_mutex_lock(&data->lock, K_FOREVER);
+
+	ret = max22017_reg_read(dev, MAX22017_GEN_GPIO_DATA_OFF, &gpio_data);
+	if (ret) {
+		goto fail;
+	}
+
+	if (value) {
+		gpio_data |= FIELD_PREP(MAX22017_GEN_GPIO_DATA_GPO_DATA, BIT(pin));
+	} else {
+		gpio_data &= ~FIELD_PREP(MAX22017_GEN_GPIO_DATA_GPO_DATA, BIT(pin));
+	}
+
+	ret = max22017_reg_write(dev, MAX22017_GEN_GPIO_DATA_OFF, gpio_data);
+fail:
+	k_mutex_unlock(&data->lock);
+	return ret;
+}
+
+int adi_max22017_gpio_get_pin_value(const struct device *dev, uint8_t pin, bool *value)
+{
+	int ret;
+	uint16_t gpio_data;
+	struct max22017_data *data = dev->data;
+
+	k_mutex_lock(&data->lock, K_FOREVER);
+
+	ret = max22017_reg_read(dev, MAX22017_GEN_GPIO_DATA_OFF, &gpio_data);
+	if (ret) {
+		goto fail;
+	}
+
+	*value = FIELD_GET(MAX22017_GEN_GPIO_DATA_GPI_DATA, gpio_data) & BIT(pin);
+
+fail:
+	k_mutex_unlock(&data->lock);
+	return ret;
+}
+
+static int adi_max22017_gpio_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
+						 gpio_port_value_t value)
+{
+	int ret;
+	uint16_t gpio_data, tmp_val;
+	struct max22017_data *data = dev->data;
+
+	k_mutex_lock(&data->lock, K_FOREVER);
+
+	ret = max22017_reg_read(dev, MAX22017_GEN_GPIO_DATA_OFF, &gpio_data);
+	if (ret) {
+		goto fail;
+	}
+
+	tmp_val = FIELD_GET(MAX22017_GEN_GPIO_DATA_GPO_DATA, gpio_data);
+	tmp_val = (tmp_val & ~mask) | (value & mask);
+	gpio_data = FIELD_PREP(MAX22017_GEN_GPIO_DATA_GPO_DATA, tmp_val) |
+		    FIELD_PREP(MAX22017_GEN_GPIO_DATA_GPI_DATA,
+			       FIELD_GET(MAX22017_GEN_GPIO_DATA_GPI_DATA, gpio_data));
+
+	ret = max22017_reg_write(dev, MAX22017_GEN_GPIO_DATA_OFF, gpio_data);
+fail:
+	k_mutex_unlock(&data->lock);
+	return ret;
+}
+
+static int gpio_adi_max22017_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
+{
+	const struct gpio_adi_max22017_config *config = dev->config;
+	int err = -EINVAL;
+
+	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
+		return adi_max22017_gpio_deconfigure(config->parent, pin);
+	}
+
+	if ((flags & GPIO_SINGLE_ENDED) != 0) {
+		return -ENOTSUP;
+	}
+
+	if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
+		return -ENOTSUP;
+	}
+
+	switch (flags & GPIO_DIR_MASK) {
+	case GPIO_INPUT:
+		err = adi_max22017_gpio_set_input(config->parent, pin);
+		break;
+	case GPIO_OUTPUT:
+		err = adi_max22017_gpio_set_output(config->parent, pin,
+						   (flags & GPIO_OUTPUT_INIT_HIGH) != 0);
+		break;
+	default:
+		return -ENOTSUP;
+	}
+	return err;
+}
+
+static int gpio_adi_max22017_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
+						     enum gpio_int_mode mode,
+						     enum gpio_int_trig trig)
+{
+	int ret;
+	uint16_t gpio_int, gen_int_en;
+	const struct gpio_adi_max22017_config *config = dev->config;
+	const struct device *parent = config->parent;
+	struct max22017_data *data = parent->data;
+
+	k_mutex_lock(&data->lock, K_FOREVER);
+
+	if (mode == GPIO_INT_MODE_DISABLED) {
+		ret = -ENOTSUP;
+		goto fail;
+	}
+
+	ret = max22017_reg_read(parent, MAX22017_GEN_GPI_INT_OFF, &gpio_int);
+	if (ret) {
+		goto fail;
+	}
+
+	if (mode & GPIO_INT_EDGE_RISING) {
+		gpio_int |= FIELD_PREP(MAX22017_GEN_GPI_INT_GPI_POS_EDGE_INT, BIT(pin));
+	}
+	if (mode & GPIO_INT_EDGE_FALLING) {
+		gpio_int |= FIELD_PREP(MAX22017_GEN_GPI_INT_GPI_NEG_EDGE_INT, BIT(pin));
+	}
+
+	ret = max22017_reg_write(parent, MAX22017_GEN_GPI_INT_OFF, gpio_int);
+	if (ret) {
+		goto fail;
+	}
+
+	ret = max22017_reg_read(parent, MAX22017_GEN_INTEN_OFF, &gen_int_en);
+	if (ret) {
+		goto fail;
+	}
+
+	ret = max22017_reg_write(parent, MAX22017_GEN_INTEN_OFF,
+				 gen_int_en | FIELD_PREP(MAX22017_GEN_INTEN_GPI_INTEN, 1));
+fail:
+	k_mutex_unlock(&data->lock);
+	return ret;
+}
+
+static int gpio_adi_max22017_port_get_raw(const struct device *dev, gpio_port_value_t *value)
+{
+	int ret;
+	const struct gpio_adi_max22017_config *config = dev->config;
+	const struct device *parent = config->parent;
+	struct max22017_data *data = parent->data;
+
+	k_mutex_lock(&data->lock, K_FOREVER);
+
+	ret = max22017_reg_read(parent, MAX22017_GEN_GPIO_DATA_OFF, (uint16_t *)value);
+	if (ret) {
+		goto fail;
+	}
+
+	*value = FIELD_GET(MAX22017_GEN_GPIO_DATA_GPI_DATA, *value);
+
+fail:
+	k_mutex_unlock(&data->lock);
+	return ret;
+}
+
+static int gpio_adi_max22017_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
+						 gpio_port_value_t value)
+{
+	const struct gpio_adi_max22017_config *config = dev->config;
+
+	return adi_max22017_gpio_port_set_masked_raw(config->parent, mask, value);
+}
+
+static int gpio_adi_max22017_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
+{
+	const struct gpio_adi_max22017_config *config = dev->config;
+
+	return adi_max22017_gpio_port_set_masked_raw(config->parent, pins, pins);
+}
+
+static int gpio_adi_max22017_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
+{
+	const struct gpio_adi_max22017_config *config = dev->config;
+
+	return adi_max22017_gpio_port_set_masked_raw(config->parent, pins, 0);
+}
+
+static int gpio_adi_max22017_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
+{
+	int ret;
+	uint16_t gpio_data, tmp_val;
+	const struct gpio_adi_max22017_config *config = dev->config;
+	const struct device *parent = config->parent;
+	struct max22017_data *data = parent->data;
+
+	k_mutex_lock(&data->lock, K_FOREVER);
+
+	ret = max22017_reg_read(parent, MAX22017_GEN_GPIO_DATA_OFF, &gpio_data);
+	if (ret) {
+		goto fail;
+	}
+
+	tmp_val = FIELD_GET(MAX22017_GEN_GPIO_DATA_GPO_DATA, gpio_data);
+	tmp_val = (tmp_val ^ pins);
+	gpio_data = FIELD_PREP(MAX22017_GEN_GPIO_DATA_GPO_DATA, tmp_val) |
+		    FIELD_PREP(MAX22017_GEN_GPIO_DATA_GPI_DATA,
+			       FIELD_GET(MAX22017_GEN_GPIO_DATA_GPI_DATA, gpio_data));
+
+	ret = max22017_reg_write(parent, MAX22017_GEN_GPIO_DATA_OFF, gpio_data);
+fail:
+	k_mutex_unlock(&data->lock);
+	return ret;
+}
+
+static int gpio_adi_max22017_manage_cb(const struct device *dev, struct gpio_callback *callback,
+				       bool set)
+{
+	int ret;
+	const struct gpio_adi_max22017_config *config = dev->config;
+	struct max22017_data *data = config->parent->data;
+
+	k_mutex_lock(&data->lock, K_FOREVER);
+	ret = gpio_manage_callback(&data->callbacks_gpi, callback, set);
+	k_mutex_unlock(&data->lock);
+
+	return ret;
+}
+
+static int gpio_adi_max22017_init(const struct device *dev)
+{
+	const struct gpio_adi_max22017_config *config = dev->config;
+	const struct device *parent = config->parent;
+
+	if (!device_is_ready(parent)) {
+		LOG_ERR("parent adi_max22017 MFD device '%s' not ready", config->parent->name);
+		return -EINVAL;
+	}
+
+#ifdef CONFIG_GPIO_MAX22017_INT_QUIRK
+	struct gpio_adi_max22017_data *data = dev->data;
+	struct k_timer *t = &data->int_quirk_timer;
+
+	k_timer_init(t, isr_quirk_handler, NULL);
+	k_timer_user_data_set(t, parent->data);
+	k_timer_start(t, K_MSEC(25), K_MSEC(25));
+#endif
+	return 0;
+}
+
+static DEVICE_API(gpio, gpio_adi_max22017_api) = {
+	.pin_configure = gpio_adi_max22017_configure,
+	.port_set_masked_raw = gpio_adi_max22017_port_set_masked_raw,
+	.port_set_bits_raw = gpio_adi_max22017_port_set_bits_raw,
+	.port_clear_bits_raw = gpio_adi_max22017_port_clear_bits_raw,
+	.port_toggle_bits = gpio_adi_max22017_port_toggle_bits,
+	.port_get_raw = gpio_adi_max22017_port_get_raw,
+	.pin_interrupt_configure = gpio_adi_max22017_pin_interrupt_configure,
+	.manage_callback = gpio_adi_max22017_manage_cb,
+};
+
+#define GPIO_MAX22017_DEVICE(id)                                                                   \
+	static const struct gpio_adi_max22017_config gpio_adi_max22017_##id##_cfg = {              \
+		.common =                                                                          \
+			{                                                                          \
+				.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(id),              \
+			},                                                                         \
+		.parent = DEVICE_DT_GET(DT_INST_PARENT(id)),                                       \
+	};                                                                                         \
+	static struct gpio_adi_max22017_data gpio_adi_max22017_##id##_data;                        \
+	DEVICE_DT_INST_DEFINE(id, gpio_adi_max22017_init, NULL, &gpio_adi_max22017_##id##_data,    \
+			      &gpio_adi_max22017_##id##_cfg, POST_KERNEL,                          \
+			      CONFIG_GPIO_MAX22017_INIT_PRIORITY, &gpio_adi_max22017_api);
+
+DT_INST_FOREACH_STATUS_OKAY(GPIO_MAX22017_DEVICE)
diff --git a/drivers/gpio/gpio_max22190.c b/drivers/gpio/gpio_max22190.c
deleted file mode 100644
index 8fa04821d08..00000000000
--- a/drivers/gpio/gpio_max22190.c
+++ /dev/null
@@ -1,666 +0,0 @@
-/*
- * Copyright (c) 2024 Analog Devices Inc.
- * Copyright (c) 2024 Baylibre SAS
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DT_DRV_COMPAT adi_max22190_gpio
-
-#include <zephyr/drivers/gpio.h>
-#include <zephyr/drivers/spi.h>
-#include <zephyr/kernel.h>
-#include <zephyr/sys/byteorder.h>
-
-#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
-#include <zephyr/logging/log.h>
-
-LOG_MODULE_REGISTER(gpio_max22190);
-
-#include <zephyr/drivers/gpio/gpio_utils.h>
-
-#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 0
-#warning "GPIO MAX22190 driver enabled without any devices"
-#endif
-
-#define MAX22190_ENABLE  1
-#define MAX22190_DISABLE 0
-
-#define MAX22190_READ  0
-#define MAX22190_WRITE 1
-
-#define MAX22190_MAX_PKT_SIZE   3
-#define MAX22190_CHANNELS       8
-#define MAX22190_FAULT2_ENABLES 5
-
-#define MAX22190_WB_REG           0x0
-#define MAX22190_DI_REG           0x2
-#define MAX22190_FAULT1_REG       0x4
-#define MAX22190_FILTER_IN_REG(x) (0x6 + (2 * (x)))
-#define MAX22190_CFG_REG          0x18
-#define MAX22190_IN_EN_REG        0x1A
-#define MAX22190_FAULT2_REG       0x1C
-#define MAX22190_FAULT2_EN_REG    0x1E
-#define MAX22190_GPO_REG          0x22
-#define MAX22190_FAULT1_EN_REG    0x24
-#define MAX22190_NOP_REG          0x26
-
-#define MAX22190_CH_STATE_MASK(x) BIT(x)
-#define MAX22190_DELAY_MASK       GENMASK(2, 0)
-#define MAX22190_FBP_MASK         BIT(3)
-#define MAX22190_WBE_MASK         BIT(4)
-#define MAX22190_RW_MASK          BIT(7)
-#define MAX22190_ADDR_MASK        GENMASK(6, 0)
-#define MAX22190_ALARM_MASK       GENMASK(4, 3)
-#define MAX22190_POR_MASK         BIT(6)
-
-#define MAX22190_FAULT_MASK(x)   BIT(x)
-#define MAX22190_FAULT2_WBE_MASK BIT(4)
-
-#define MAX22190_FAULT2_EN_MASK GENMASK(5, 0)
-
-#define MAX22190_CFG_REFDI_MASK BIT(0)
-#define MAX22190_CFG_CLRF_MASK  BIT(3)
-#define MAX22190_CFG_24VF_MASK  BIT(4)
-
-#define PRINT_ERR_BIT(bit1, bit2)                                                                  \
-	if (bit1 & bit2) {                                                                         \
-		LOG_ERR("[%s] %d", #bit1, bit1);                                                   \
-	}
-
-#define MAX22190_CLEAN_POR(dev)                                                                    \
-	max22190_reg_update(dev, MAX22190_FAULT1_REG, MAX22190_POR_MASK,                           \
-			    FIELD_PREP(MAX22190_POR_MASK, 0))
-
-enum max22190_ch_state {
-	MAX22190_CH_OFF,
-	MAX22190_CH_ON
-};
-
-enum max22190_ch_wb_state {
-	MAX22190_CH_NO_WB_BREAK,
-	MAX22190_CH_WB_COND_DET
-};
-
-enum max22190_mode {
-	MAX22190_MODE_0,
-	MAX22190_MODE_1,
-	MAX22190_MODE_2,
-	MAX22190_MODE_3,
-};
-
-union max22190_fault1 {
-	uint8_t reg_raw;
-	struct {
-		uint8_t max22190_WBG: 1; /* BIT 0 */
-		uint8_t max22190_24VM: 1;
-		uint8_t max22190_24VL: 1;
-		uint8_t max22190_ALRMT1: 1;
-		uint8_t max22190_ALRMT2: 1;
-		uint8_t max22190_FAULT2: 1;
-		uint8_t max22190_POR: 1;
-		uint8_t max22190_CRC: 1; /* BIT 7 */
-	} reg_bits;
-};
-
-union max22190_fault1_en {
-	uint8_t reg_raw;
-	struct {
-		uint8_t max22190_WBGE: 1; /* BIT 0 */
-		uint8_t max22190_24VME: 1;
-		uint8_t max22190_24VLE: 1;
-		uint8_t max22190_ALRMT1E: 1;
-		uint8_t max22190_ALRMT2E: 1;
-		uint8_t max22190_FAULT2E: 1;
-		uint8_t max22190_PORE: 1;
-		uint8_t max22190_CRCE: 1; /* BIT 7 */
-	} reg_bits;
-};
-
-union max22190_fault2 {
-	uint8_t reg_raw;
-	struct {
-		uint8_t max22190_RFWBS: 1; /* BIT 0 */
-		uint8_t max22190_RFWBO: 1;
-		uint8_t max22190_RFDIS: 1;
-		uint8_t max22190_RFDIO: 1;
-		uint8_t max22190_OTSHDN: 1;
-		uint8_t max22190_FAULT8CK: 1;
-		uint8_t max22190_DUMMY: 2; /* BIT 7 */
-	} reg_bits;
-};
-
-union max22190_fault2_en {
-	uint8_t reg_raw;
-	struct {
-		uint8_t max22190_RFWBSE: 1; /* BIT 0 */
-		uint8_t max22190_RFWBOE: 1;
-		uint8_t max22190_RFDISE: 1;
-		uint8_t max22190_RFDIOE: 1;
-		uint8_t max22190_OTSHDNE: 1;
-		uint8_t max22190_FAULT8CKE: 1;
-		uint8_t max22190_DUMMY: 2; /* BIT 7 */
-	} reg_bits;
-};
-
-union max22190_cfg {
-	uint8_t reg_raw;
-	struct {
-		uint8_t max22190_DUMMY1: 3; /* BIT 0 */
-		uint8_t max22190_24VF: 1;
-		uint8_t max22190_CLRF: 1;
-		uint8_t max22190_DUMMY2: 2;
-		uint8_t max22190_REFDI_SH_EN: 1; /* BIT 7 */
-	} reg_bits;
-};
-
-union max22190_filter {
-	uint8_t reg_raw;
-	struct {
-		uint8_t max22190_DELAY: 3; /* BIT 0 */
-		uint8_t max22190_FBP: 1;
-		uint8_t max22190_WBE: 1;
-		uint8_t max22190_DUMMY: 2; /* BIT 7 */
-	} reg_bits;
-};
-
-enum max22190_delay {
-	MAX22190_DELAY_50US,
-	MAX22190_DELAY_100US,
-	MAX22190_DELAY_400US,
-	MAX22190_DELAY_800US,
-	MAX22190_DELAY_1800US,
-	MAX22190_DELAY_3200US,
-	MAX22190_DELAY_12800US,
-	MAX22190_DELAY_20000US
-};
-
-struct max22190_config {
-	struct spi_dt_spec spi;
-	struct gpio_dt_spec fault_gpio;
-	struct gpio_dt_spec ready_gpio;
-	struct gpio_dt_spec latch_gpio;
-	union max22190_filter filter[8];
-	bool crc_en;
-	enum max22190_mode mode;
-	uint8_t pkt_size;
-};
-
-struct max22190_data {
-	struct gpio_driver_data common;
-	enum max22190_ch_state channels[MAX22190_CHANNELS];
-	enum max22190_ch_wb_state wb[MAX22190_CHANNELS];
-	union max22190_cfg cfg;
-	union max22190_fault1 fault1;
-	union max22190_fault1_en fault1_en;
-	union max22190_fault2 fault2;
-	union max22190_fault2_en fault2_en;
-};
-
-/*
- * @brief Compute the CRC5 value for MAX22190
- * @param data - Data array to calculate CRC for.
- * @return CRC result.
- */
-static uint8_t max22190_crc(uint8_t *data)
-{
-	int length = 19;
-	uint8_t crc_step, tmp;
-	uint8_t crc_init = 0x7;
-	uint8_t crc_poly = 0x35;
-	int i;
-
-	/*
-	 * This is the C custom implementation of CRC function for MAX22190, and
-	 * can be found here:
-	 * https://www.analog.com/en/design-notes/guidelines-to-implement-crc-algorithm.html
-	 */
-	uint32_t datainput = (uint32_t)((data[0] << 16) + (data[1] << 8) + data[2]);
-
-	datainput = (datainput & 0xFFFFE0) + crc_init;
-
-	tmp = (uint8_t)((datainput & 0xFC0000) >> 18);
-
-	if ((tmp & 0x20) == 0x20) {
-		crc_step = (uint8_t)(tmp ^ crc_poly);
-	} else {
-		crc_step = tmp;
-	}
-
-	for (i = 0; i < length - 1; i++) {
-		tmp = (uint8_t)(((crc_step & 0x1F) << 1) +
-				((datainput >> (length - 2 - i)) & 0x01));
-
-		if ((tmp & 0x20) == 0x20) {
-			crc_step = (uint8_t)(tmp ^ crc_poly);
-		} else {
-			crc_step = tmp;
-		}
-	}
-
-	return (uint8_t)(crc_step & 0x1F);
-}
-
-/*
- * @brief Update chan WB state in max22190_data
- *
- * @param dev - MAX22190 device.
- * @param val - value to be set.
- */
-static void max22190_update_wb_stat(const struct device *dev, uint8_t val)
-{
-	struct max22190_data *data = dev->data;
-
-	for (int ch_n = 0; ch_n < 8; ch_n++) {
-		data->wb[ch_n] = (val >> ch_n) & 0x1;
-	}
-}
-
-/*
- * @brief Update chan IN state in max22190_data
- *
- * @param dev - MAX22190 device.
- * @param val - value to be set.
- */
-static void max22190_update_in_stat(const struct device *dev, uint8_t val)
-{
-	struct max22190_data *data = dev->data;
-
-	for (int ch_n = 0; ch_n < 8; ch_n++) {
-		data->channels[ch_n] = (val >> ch_n) & 0x1;
-	}
-}
-
-/*
- * @brief Register write function for MAX22190
- *
- * @param dev - MAX22190 device config.
- * @param addr - Register value to which data is written.
- * @param val - Value which is to be written to requested register.
- * @return 0 in case of success, negative error code otherwise.
- */
-static int max22190_reg_transceive(const struct device *dev, uint8_t addr, uint8_t val, uint8_t rw)
-{
-	uint8_t crc;
-	int ret;
-
-	uint8_t local_rx_buff[MAX22190_MAX_PKT_SIZE] = {0};
-	uint8_t local_tx_buff[MAX22190_MAX_PKT_SIZE] = {0};
-
-	const struct max22190_config *config = dev->config;
-
-	struct spi_buf tx_buf = {
-		.buf = &local_tx_buff,
-		.len = config->pkt_size,
-	};
-	const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1};
-
-	struct spi_buf rx_buf = {
-		.buf = &local_rx_buff,
-		.len = config->pkt_size,
-	};
-	const struct spi_buf_set rx = {.buffers = &rx_buf, .count = 1};
-
-	local_tx_buff[0] =
-		FIELD_PREP(MAX22190_ADDR_MASK, addr) | FIELD_PREP(MAX22190_RW_MASK, rw & 0x1);
-	local_tx_buff[1] = val;
-
-	/* If CRC enabled calculate it */
-	if (config->crc_en) {
-		local_tx_buff[2] = max22190_crc(&local_tx_buff[0]);
-	}
-
-	/* write cmd & read resp at once */
-	ret = spi_transceive_dt(&config->spi, &tx, &rx);
-
-	if (ret) {
-		LOG_ERR("Err spi_transcieve_dt  [%d]\n", ret);
-		return ret;
-	}
-
-	/* if CRC enabled check readed */
-	if (config->crc_en) {
-		crc = max22190_crc(&local_rx_buff[0]);
-		if (crc != (local_rx_buff[2] & 0x1F)) {
-			LOG_ERR("READ CRC ERR (%d)-(%d)\n", crc, (local_rx_buff[2] & 0x1F));
-			return -EINVAL;
-		}
-	}
-
-	/* always (R/W) get DI reg in first byte */
-	max22190_update_in_stat(dev, local_rx_buff[0]);
-
-	/* in case of writing register we get as second byte WB reg */
-	if (rw == MAX22190_WRITE) {
-		max22190_update_wb_stat(dev, local_rx_buff[1]);
-	} else {
-		/* in case of READ second byte is value we are looking for */
-		ret = local_rx_buff[1];
-	}
-
-	return ret;
-}
-
-#define max22190_reg_read(dev, addr)       max22190_reg_transceive(dev, addr, 0, MAX22190_READ)
-#define max22190_reg_write(dev, addr, val) max22190_reg_transceive(dev, addr, val, MAX22190_WRITE)
-
-/*
- * @brief Register update function for MAX22190
- *
- * @param dev - MAX22190 device.
- * @param addr - Register valueto wich data is updated.
- * @param mask - Corresponding mask to the data that will be updated.
- * @param val - Updated value to be written in the register at update.
- * @return 0 in case of success, negative error code otherwise.
- */
-static int max22190_reg_update(const struct device *dev, uint8_t addr, uint8_t mask, uint8_t val)
-{
-	int ret;
-	uint32_t reg_val = 0;
-
-	ret = max22190_reg_read(dev, addr);
-
-	reg_val = ret;
-	reg_val &= ~mask;
-	reg_val |= mask & val;
-
-	return max22190_reg_write(dev, addr, reg_val);
-}
-
-/*
- * @brief Check FAULT1 and FAULT2
- *
- * @param dev - MAX22190 device
- */
-static void max22190_fault_check(const struct device *dev)
-{
-	struct max22190_data *data = dev->data;
-
-	/* FAULT1 */
-	data->fault1.reg_raw = max22190_reg_read(dev, MAX22190_FAULT1_REG);
-
-	if (data->fault1.reg_raw) {
-		/* FAULT1_EN */
-		data->fault1_en.reg_raw = max22190_reg_read(dev, MAX22190_FAULT1_EN_REG);
-
-		PRINT_ERR_BIT(data->fault1.reg_bits.max22190_CRC,
-			      data->fault1_en.reg_bits.max22190_CRCE);
-		PRINT_ERR_BIT(data->fault1.reg_bits.max22190_POR,
-			      data->fault1_en.reg_bits.max22190_PORE);
-		PRINT_ERR_BIT(data->fault1.reg_bits.max22190_FAULT2,
-			      data->fault1_en.reg_bits.max22190_FAULT2E);
-		PRINT_ERR_BIT(data->fault1.reg_bits.max22190_ALRMT2,
-			      data->fault1_en.reg_bits.max22190_ALRMT2E);
-		PRINT_ERR_BIT(data->fault1.reg_bits.max22190_ALRMT1,
-			      data->fault1_en.reg_bits.max22190_ALRMT1E);
-		PRINT_ERR_BIT(data->fault1.reg_bits.max22190_24VL,
-			      data->fault1_en.reg_bits.max22190_24VLE);
-		PRINT_ERR_BIT(data->fault1.reg_bits.max22190_24VM,
-			      data->fault1_en.reg_bits.max22190_24VME);
-		PRINT_ERR_BIT(data->fault1.reg_bits.max22190_WBG,
-			      data->fault1_en.reg_bits.max22190_WBGE);
-
-		if (data->fault1.reg_bits.max22190_WBG & data->fault1_en.reg_bits.max22190_WBGE) {
-			uint8_t wb_val = max22190_reg_read(dev, MAX22190_WB_REG);
-
-			max22190_update_wb_stat(dev, (uint8_t)wb_val);
-		}
-
-		if (data->fault1.reg_bits.max22190_FAULT2) {
-			/* FAULT2 */
-			data->fault2.reg_raw = max22190_reg_read(dev, MAX22190_FAULT2_REG);
-
-			/* FAULT2_EN */
-			data->fault2_en.reg_raw = max22190_reg_read(dev, MAX22190_FAULT2_EN_REG);
-
-			PRINT_ERR_BIT(data->fault2.reg_bits.max22190_RFWBS,
-				      data->fault2_en.reg_bits.max22190_RFWBSE);
-			PRINT_ERR_BIT(data->fault2.reg_bits.max22190_RFWBO,
-				      data->fault2_en.reg_bits.max22190_RFWBOE);
-			PRINT_ERR_BIT(data->fault2.reg_bits.max22190_RFDIS,
-				      data->fault2_en.reg_bits.max22190_RFDISE);
-			PRINT_ERR_BIT(data->fault2.reg_bits.max22190_RFDIO,
-				      data->fault2_en.reg_bits.max22190_RFDIOE);
-			PRINT_ERR_BIT(data->fault2.reg_bits.max22190_OTSHDN,
-				      data->fault2_en.reg_bits.max22190_OTSHDNE);
-			PRINT_ERR_BIT(data->fault2.reg_bits.max22190_FAULT8CK,
-				      data->fault2_en.reg_bits.max22190_FAULT8CKE);
-		}
-	}
-}
-
-static void max22190_state_get(const struct device *dev)
-{
-	const struct max22190_config *config = dev->config;
-
-	if (gpio_pin_get_dt(&config->fault_gpio)) {
-		max22190_fault_check(dev);
-	}
-
-	/* We are reading WB reg because on first byte will be clocked out DI reg
-	 * on second byte we will ge WB value.
-	 */
-	uint8_t wb_val = max22190_reg_read(dev, MAX22190_WB_REG);
-
-	max22190_update_wb_stat(dev, (uint8_t)wb_val);
-}
-
-static int gpio_max22190_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
-{
-	int err = 0;
-
-	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
-		return -ENOTSUP;
-	}
-
-	if ((flags & GPIO_SINGLE_ENDED) != 0) {
-		return -ENOTSUP;
-	}
-
-	if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
-		return -ENOTSUP;
-	}
-
-	if (flags & GPIO_INT_ENABLE) {
-		return -ENOTSUP;
-	}
-
-	switch (flags & GPIO_DIR_MASK) {
-	case GPIO_INPUT:
-		LOG_INF("Nothing to do, only INPUT supported");
-		break;
-	default:
-		LOG_ERR("On MAX22190 only input option is available!");
-		return -ENOTSUP;
-	}
-
-	return err;
-}
-
-static void max22190_filter_set(const struct device *dev)
-{
-	const struct max22190_config *config = dev->config;
-
-	for (int ch_n = 0; ch_n < 8; ch_n++) {
-		max22190_reg_write(dev, MAX22190_FILTER_IN_REG(ch_n), config->filter[ch_n].reg_raw);
-	}
-}
-
-static int max22190_fault_set(const struct device *dev)
-{
-	const struct max22190_data *data = dev->data;
-	int ret = 0;
-
-	ret = max22190_reg_write(dev, MAX22190_FAULT1_EN_REG, data->fault1_en.reg_raw);
-	if (ret) {
-		goto exit_fault_set;
-	}
-
-	ret = max22190_reg_write(dev, MAX22190_FAULT1_REG, data->fault1.reg_raw);
-	if (ret) {
-		goto exit_fault_set;
-	}
-
-	ret = max22190_reg_write(dev, MAX22190_FAULT2_EN_REG, data->fault2_en.reg_raw);
-	if (ret) {
-		goto exit_fault_set;
-	}
-
-	ret = max22190_reg_write(dev, MAX22190_FAULT2_REG, data->fault2.reg_raw);
-	if (ret) {
-		goto exit_fault_set;
-	}
-
-	return ret;
-
-exit_fault_set:
-	LOG_ERR("Err spi_transcieve_dt  [%d]\n", ret);
-	return ret;
-}
-
-static int gpio_max22190_port_get_raw(const struct device *dev, gpio_port_value_t *value)
-{
-	const struct max22190_data *data = dev->data;
-
-	max22190_state_get(dev);
-	*value = 0;
-	for (int ch_n = 0; ch_n < 8; ch_n++) {
-		/* IN ch state */
-		*value |= data->channels[ch_n] << ch_n;
-	}
-
-	return 0;
-}
-
-static int gpio_max22190_init(const struct device *dev)
-{
-	const struct max22190_config *config = dev->config;
-	struct max22190_data *data = dev->data;
-
-	LOG_DBG("GPIO MAX22190 init IN\n");
-
-	int err = 0;
-
-	if (!spi_is_ready_dt(&config->spi)) {
-		LOG_ERR("SPI bus is not ready\n");
-		return -ENODEV;
-	}
-
-	/* setup READY gpio - normal low */
-	if (!gpio_is_ready_dt(&config->ready_gpio)) {
-		LOG_ERR("READY GPIO device not ready");
-		return -ENODEV;
-	}
-
-	err = gpio_pin_configure_dt(&config->ready_gpio, GPIO_INPUT);
-	if (err < 0) {
-		LOG_ERR("Failed to configure reset GPIO");
-		return err;
-	}
-
-	/* setup FAULT gpio - normal high */
-	if (!gpio_is_ready_dt(&config->fault_gpio)) {
-		LOG_ERR("FAULT GPIO device not ready");
-		return -ENODEV;
-	}
-
-	err = gpio_pin_configure_dt(&config->fault_gpio, GPIO_INPUT | GPIO_PULL_UP);
-	if (err < 0) {
-		LOG_ERR("Failed to configure DC GPIO");
-		return err;
-	}
-
-	/* setup LATCH gpio - normal high */
-	if (!gpio_is_ready_dt(&config->latch_gpio)) {
-		LOG_ERR("LATCH GPIO device not ready");
-		return -ENODEV;
-	}
-
-	err = gpio_pin_configure_dt(&config->latch_gpio, GPIO_OUTPUT_INACTIVE);
-	if (err < 0) {
-		LOG_ERR("Failed to configure busy GPIO");
-		return err;
-	}
-
-	for (int i = 0; i < 8; i++) {
-		LOG_DBG("IN%d WBE [%d] FBP[%d] DELAY[%d]\n", i,
-			config->filter[i].reg_bits.max22190_WBE,
-			config->filter[i].reg_bits.max22190_FBP,
-			config->filter[i].reg_bits.max22190_DELAY);
-	}
-
-	LOG_DBG(" > MAX22190 MODE: %x", config->mode);
-	LOG_DBG(" > MAX22190 PKT SIZE: %dbits (%dbytes)", config->pkt_size * 8, config->pkt_size);
-	LOG_DBG(" > MAX22190 CRC: %s", config->crc_en ? "enable" : "disable");
-
-	data->fault1_en.reg_bits.max22190_WBGE = 1;
-	data->fault1_en.reg_bits.max22190_PORE = 1;
-
-	/* Set all FAULT and FAULT_EN regs */
-	max22190_fault_set(dev);
-
-	/* Set channels filters */
-	max22190_filter_set(dev);
-
-	/* POR bit need to be cleared after start */
-	MAX22190_CLEAN_POR(dev);
-
-	LOG_DBG("GPIO MAX22190 init OUT\n");
-	return 0;
-}
-
-static DEVICE_API(gpio, gpio_max22190_api) = {
-	.pin_configure = gpio_max22190_config,
-	.port_get_raw = gpio_max22190_port_get_raw,
-};
-
-/* Assign appropriate value for FILTER delay*/
-#define MAX22190_FILTER_SET_DELAY(delay)                                                           \
-	delay == 20000   ? MAX22190_DELAY_20000US                                                  \
-	: delay == 12800 ? MAX22190_DELAY_12800US                                                  \
-	: delay == 3200  ? MAX22190_DELAY_3200US                                                   \
-	: delay == 1600  ? MAX22190_DELAY_1800US                                                   \
-	: delay == 800   ? MAX22190_DELAY_800US                                                    \
-	: delay == 400   ? MAX22190_DELAY_400US                                                    \
-	: delay == 100   ? MAX22190_DELAY_100US                                                    \
-	: delay == 50    ? MAX22190_DELAY_50US                                                     \
-			 : MAX22190_DELAY_20000US
-
-/* Set FILTERx reg */
-#define MAX22190_FILTER_BY_IDX(id, idx)                                                            \
-	{                                                                                          \
-		.reg_bits.max22190_DELAY =                                                         \
-			MAX22190_FILTER_SET_DELAY(DT_INST_PROP_BY_IDX(id, filter_delays, idx)),    \
-		.reg_bits.max22190_FBP = DT_INST_PROP_BY_IDX(id, filter_fbps, idx),                \
-		.reg_bits.max22190_WBE = DT_INST_PROP_BY_IDX(id, filter_wbes, idx),                \
-	}
-
-#define GPIO_MAX22190_DEVICE(id)                                                                   \
-	static const struct max22190_config max22190_##id##_cfg = {                                \
-		.spi = SPI_DT_SPEC_INST_GET(id, SPI_OP_MODE_MASTER | SPI_WORD_SET(8U), 0U),        \
-		.ready_gpio = GPIO_DT_SPEC_INST_GET(id, drdy_gpios),                               \
-		.fault_gpio = GPIO_DT_SPEC_INST_GET(id, fault_gpios),                              \
-		.latch_gpio = GPIO_DT_SPEC_INST_GET(id, latch_gpios),                              \
-		.mode = DT_INST_PROP(id, max22190_mode),                                           \
-		.crc_en = !(DT_INST_PROP(id, max22190_mode) & 0x1),                                \
-		.pkt_size = !(DT_INST_PROP(id, max22190_mode) & 0x1) ? 3 : 2,                      \
-		.filter =                                                                          \
-			{                                                                          \
-				MAX22190_FILTER_BY_IDX(id, 0),                                     \
-				MAX22190_FILTER_BY_IDX(id, 1),                                     \
-				MAX22190_FILTER_BY_IDX(id, 2),                                     \
-				MAX22190_FILTER_BY_IDX(id, 3),                                     \
-				MAX22190_FILTER_BY_IDX(id, 4),                                     \
-				MAX22190_FILTER_BY_IDX(id, 5),                                     \
-				MAX22190_FILTER_BY_IDX(id, 6),                                     \
-				MAX22190_FILTER_BY_IDX(id, 7),                                     \
-			},                                                                         \
-	};                                                                                         \
-                                                                                                   \
-	static struct max22190_data max22190_##id##_data;                                          \
-                                                                                                   \
-	DEVICE_DT_INST_DEFINE(id, &gpio_max22190_init, NULL, &max22190_##id##_data,                \
-			      &max22190_##id##_cfg, POST_KERNEL,                                   \
-			      CONFIG_GPIO_MAX22190_INIT_PRIORITY, &gpio_max22190_api);
-
-DT_INST_FOREACH_STATUS_OKAY(GPIO_MAX22190_DEVICE)
diff --git a/drivers/gpio/gpio_max2219x.c b/drivers/gpio/gpio_max2219x.c
new file mode 100644
index 00000000000..e68f187df8b
--- /dev/null
+++ b/drivers/gpio/gpio_max2219x.c
@@ -0,0 +1,697 @@
+/*
+ * Copyright (c) 2024 Analog Devices Inc.
+ * Copyright (c) 2024 Baylibre SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/byteorder.h>
+
+#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(gpio_max22190);
+
+#include <zephyr/drivers/gpio/gpio_utils.h>
+
+#define MAX22190_ENABLE  1
+#define MAX22190_DISABLE 0
+
+#define MAX22190_READ  0
+#define MAX22190_WRITE 1
+
+#define MAX22190_MAX_PKT_SIZE   3
+#define MAX22190_CHANNELS       8
+#define MAX22190_FAULT2_ENABLES 5
+
+#define MAX22190_WB_REG           0x0
+#define MAX22190_DI_REG           0x2
+#define MAX22190_FAULT1_REG       0x4
+#define MAX22190_FILTER_IN_REG(x) (0x6 + (2 * (x)))
+#define MAX22190_CFG_REG          0x18
+#define MAX22190_IN_EN_REG        0x1A
+#define MAX22190_FAULT2_REG       0x1C
+#define MAX22190_FAULT2_EN_REG    0x1E
+#define MAX22190_GPO_REG          0x22
+#define MAX22190_FAULT1_EN_REG    0x24
+#define MAX22190_NOP_REG          0x26
+
+#define MAX22190_CH_STATE_MASK(x) BIT(x)
+#define MAX22190_DELAY_MASK       GENMASK(2, 0)
+#define MAX22190_FBP_MASK         BIT(3)
+#define MAX22190_WBE_MASK         BIT(4)
+#define MAX22190_RW_MASK          BIT(7)
+#define MAX22190_ADDR_MASK        GENMASK(6, 0)
+#define MAX22190_ALARM_MASK       GENMASK(4, 3)
+#define MAX22190_POR_MASK         BIT(6)
+
+#define MAX22190_FAULT_MASK(x)   BIT(x)
+#define MAX22190_FAULT2_WBE_MASK BIT(4)
+
+#define MAX22190_FAULT2_EN_MASK GENMASK(5, 0)
+
+#define MAX22190_CFG_REFDI_MASK BIT(0)
+#define MAX22190_CFG_CLRF_MASK  BIT(3)
+#define MAX22190_CFG_24VF_MASK  BIT(4)
+
+#define PRINT_ERR_BIT(bit1, bit2)                                                                  \
+	if (bit1 & bit2) {                                                                         \
+		LOG_ERR("[%s] %d", #bit1, bit1);                                                   \
+	}
+
+#define MAX22190_CLEAN_POR(dev)                                                                    \
+	max22190_reg_update(dev, MAX22190_FAULT1_REG, MAX22190_POR_MASK,                           \
+			    FIELD_PREP(MAX22190_POR_MASK, 0))
+
+enum max22190_variants {
+	MAX22190,
+	MAX22199,
+};
+
+enum max22190_ch_state {
+	MAX22190_CH_OFF,
+	MAX22190_CH_ON
+};
+
+enum max22190_ch_wb_state {
+	MAX22190_CH_NO_WB_BREAK,
+	MAX22190_CH_WB_COND_DET
+};
+
+enum max22190_mode {
+	MAX22190_MODE_0,
+	MAX22190_MODE_1,
+	MAX22190_MODE_2,
+	MAX22190_MODE_3,
+};
+
+union max22190_fault1 {
+	uint8_t reg_raw;
+	struct {
+		uint8_t max22190_WBG: 1; /* BIT 0 */
+		uint8_t max22190_24VM: 1;
+		uint8_t max22190_24VL: 1;
+		uint8_t max22190_ALRMT1: 1;
+		uint8_t max22190_ALRMT2: 1;
+		uint8_t max22190_FAULT2: 1;
+		uint8_t max22190_POR: 1;
+		uint8_t max22190_CRC: 1; /* BIT 7 */
+	} reg_bits;
+};
+
+union max22190_fault1_en {
+	uint8_t reg_raw;
+	struct {
+		uint8_t max22190_WBGE: 1; /* BIT 0 */
+		uint8_t max22190_24VME: 1;
+		uint8_t max22190_24VLE: 1;
+		uint8_t max22190_ALRMT1E: 1;
+		uint8_t max22190_ALRMT2E: 1;
+		uint8_t max22190_FAULT2E: 1;
+		uint8_t max22190_PORE: 1;
+		uint8_t max22190_CRCE: 1; /* BIT 7 */
+	} reg_bits;
+};
+
+union max22190_fault2 {
+	uint8_t reg_raw;
+	struct {
+		uint8_t max22190_RFWBS: 1; /* BIT 0 */
+		uint8_t max22190_RFWBO: 1;
+		uint8_t max22190_RFDIS: 1;
+		uint8_t max22190_RFDIO: 1;
+		uint8_t max22190_OTSHDN: 1;
+		uint8_t max22190_FAULT8CK: 1;
+		uint8_t max22190_DUMMY: 2; /* BIT 7 */
+	} reg_bits;
+};
+
+union max22190_fault2_en {
+	uint8_t reg_raw;
+	struct {
+		uint8_t max22190_RFWBSE: 1; /* BIT 0 */
+		uint8_t max22190_RFWBOE: 1;
+		uint8_t max22190_RFDISE: 1;
+		uint8_t max22190_RFDIOE: 1;
+		uint8_t max22190_OTSHDNE: 1;
+		uint8_t max22190_FAULT8CKE: 1;
+		uint8_t max22190_DUMMY: 2; /* BIT 7 */
+	} reg_bits;
+};
+
+union max22190_cfg {
+	uint8_t reg_raw;
+	struct {
+		uint8_t max22190_DUMMY1: 3; /* BIT 0 */
+		uint8_t max22190_24VF: 1;
+		uint8_t max22190_CLRF: 1;
+		uint8_t max22190_DUMMY2: 2;
+		uint8_t max22190_REFDI_SH_EN: 1; /* BIT 7 */
+	} reg_bits;
+};
+
+union max22190_filter {
+	uint8_t reg_raw;
+	struct {
+		uint8_t max22190_DELAY: 3; /* BIT 0 */
+		uint8_t max22190_FBP: 1;
+		uint8_t max22190_WBE: 1;
+		uint8_t max22190_DUMMY: 2; /* BIT 7 */
+	} reg_bits;
+};
+
+enum max22190_delay {
+	MAX22190_DELAY_50US,
+	MAX22190_DELAY_100US,
+	MAX22190_DELAY_400US,
+	MAX22190_DELAY_800US,
+	MAX22190_DELAY_1800US,
+	MAX22190_DELAY_3200US,
+	MAX22190_DELAY_12800US,
+	MAX22190_DELAY_20000US
+};
+
+struct max22190_config {
+	struct spi_dt_spec spi;
+	struct gpio_dt_spec fault_gpio;
+	struct gpio_dt_spec ready_gpio;
+	struct gpio_dt_spec latch_gpio;
+	union max22190_filter filter[8];
+	bool crc_en;
+	enum max22190_mode mode;
+	uint8_t pkt_size;
+	uint8_t variant;
+};
+
+struct max22190_data {
+	struct gpio_driver_data common;
+	enum max22190_ch_state channels[MAX22190_CHANNELS];
+	enum max22190_ch_wb_state wb[MAX22190_CHANNELS];
+	union max22190_cfg cfg;
+	union max22190_fault1 fault1;
+	union max22190_fault1_en fault1_en;
+	union max22190_fault2 fault2;
+	union max22190_fault2_en fault2_en;
+};
+
+/*
+ * @brief Compute the CRC5 value for MAX22190
+ * @param data - Data array to calculate CRC for.
+ * @return CRC result.
+ */
+static uint8_t max22190_crc(uint8_t *data)
+{
+	int length = 19;
+	uint8_t crc_step, tmp;
+	uint8_t crc_init = 0x7;
+	uint8_t crc_poly = 0x35;
+	int i;
+
+	/*
+	 * This is the C custom implementation of CRC function for MAX22190, and
+	 * can be found here:
+	 * https://www.analog.com/en/design-notes/guidelines-to-implement-crc-algorithm.html
+	 */
+	uint32_t datainput = (uint32_t)((data[0] << 16) + (data[1] << 8) + data[2]);
+
+	datainput = (datainput & 0xFFFFE0) + crc_init;
+
+	tmp = (uint8_t)((datainput & 0xFC0000) >> 18);
+
+	if ((tmp & 0x20) == 0x20) {
+		crc_step = (uint8_t)(tmp ^ crc_poly);
+	} else {
+		crc_step = tmp;
+	}
+
+	for (i = 0; i < length - 1; i++) {
+		tmp = (uint8_t)(((crc_step & 0x1F) << 1) +
+				((datainput >> (length - 2 - i)) & 0x01));
+
+		if ((tmp & 0x20) == 0x20) {
+			crc_step = (uint8_t)(tmp ^ crc_poly);
+		} else {
+			crc_step = tmp;
+		}
+	}
+
+	return (uint8_t)(crc_step & 0x1F);
+}
+
+/*
+ * @brief Update chan WB state in max22190_data
+ *
+ * @param dev - MAX22190 device.
+ * @param val - value to be set.
+ */
+static void max22190_update_wb_stat(const struct device *dev, uint8_t val)
+{
+	struct max22190_data *data = dev->data;
+
+	for (int ch_n = 0; ch_n < 8; ch_n++) {
+		data->wb[ch_n] = (val >> ch_n) & 0x1;
+	}
+}
+
+/*
+ * @brief Update chan IN state in max22190_data
+ *
+ * @param dev - MAX22190 device.
+ * @param val - value to be set.
+ */
+static void max22190_update_in_stat(const struct device *dev, uint8_t val)
+{
+	struct max22190_data *data = dev->data;
+
+	for (int ch_n = 0; ch_n < 8; ch_n++) {
+		data->channels[ch_n] = (val >> ch_n) & 0x1;
+	}
+}
+
+/*
+ * @brief Register write function for MAX22190
+ *
+ * @param dev - MAX22190 device config.
+ * @param addr - Register value to which data is written.
+ * @param val - Value which is to be written to requested register.
+ * @return 0 in case of success, negative error code otherwise.
+ */
+static int max22190_reg_transceive(const struct device *dev, uint8_t addr, uint8_t val, uint8_t rw)
+{
+	uint8_t crc;
+	int ret;
+
+	uint8_t local_rx_buff[MAX22190_MAX_PKT_SIZE] = {0};
+	uint8_t local_tx_buff[MAX22190_MAX_PKT_SIZE] = {0};
+
+	const struct max22190_config *config = dev->config;
+
+	struct spi_buf tx_buf = {
+		.buf = &local_tx_buff,
+		.len = config->pkt_size,
+	};
+	const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1};
+
+	struct spi_buf rx_buf = {
+		.buf = &local_rx_buff,
+		.len = config->pkt_size,
+	};
+	const struct spi_buf_set rx = {.buffers = &rx_buf, .count = 1};
+
+	local_tx_buff[0] =
+		FIELD_PREP(MAX22190_ADDR_MASK, addr) | FIELD_PREP(MAX22190_RW_MASK, rw & 0x1);
+	local_tx_buff[1] = val;
+
+	/* If CRC enabled calculate it */
+	if (config->crc_en) {
+		local_tx_buff[2] = max22190_crc(&local_tx_buff[0]);
+	}
+
+	/* write cmd & read resp at once */
+	ret = spi_transceive_dt(&config->spi, &tx, &rx);
+
+	if (ret) {
+		LOG_ERR("Err spi_transcieve_dt  [%d]\n", ret);
+		return ret;
+	}
+
+	/* if CRC enabled check readed */
+	if (config->crc_en) {
+		crc = max22190_crc(&local_rx_buff[0]);
+		if (crc != (local_rx_buff[2] & 0x1F)) {
+			LOG_ERR("READ CRC ERR (%d)-(%d)\n", crc, (local_rx_buff[2] & 0x1F));
+			return -EINVAL;
+		}
+	}
+
+	/* always (R/W) get DI reg in first byte */
+	max22190_update_in_stat(dev, local_rx_buff[0]);
+
+	/* in case of writing register we get as second byte WB reg */
+	if (rw == MAX22190_WRITE) {
+		max22190_update_wb_stat(dev, local_rx_buff[1]);
+	} else {
+		/* in case of READ second byte is value we are looking for */
+		ret = local_rx_buff[1];
+	}
+
+	return ret;
+}
+
+#define max22190_reg_read(dev, addr)       max22190_reg_transceive(dev, addr, 0, MAX22190_READ)
+#define max22190_reg_write(dev, addr, val) max22190_reg_transceive(dev, addr, val, MAX22190_WRITE)
+
+/*
+ * @brief Register update function for MAX22190
+ *
+ * @param dev - MAX22190 device.
+ * @param addr - Register valueto wich data is updated.
+ * @param mask - Corresponding mask to the data that will be updated.
+ * @param val - Updated value to be written in the register at update.
+ * @return 0 in case of success, negative error code otherwise.
+ */
+static int max22190_reg_update(const struct device *dev, uint8_t addr, uint8_t mask, uint8_t val)
+{
+	int ret;
+	uint32_t reg_val = 0;
+
+	ret = max22190_reg_read(dev, addr);
+
+	reg_val = ret;
+	reg_val &= ~mask;
+	reg_val |= mask & val;
+
+	return max22190_reg_write(dev, addr, reg_val);
+}
+
+/*
+ * @brief Check FAULT1 and FAULT2
+ *
+ * @param dev - MAX22190 device
+ */
+static void max22190_fault_check(const struct device *dev)
+{
+	struct max22190_data *data = dev->data;
+	const struct max22190_config *config = dev->config;
+
+	/* FAULT1 */
+	data->fault1.reg_raw = max22190_reg_read(dev, MAX22190_FAULT1_REG);
+
+	if (data->fault1.reg_raw) {
+		/* FAULT1_EN */
+		data->fault1_en.reg_raw = max22190_reg_read(dev, MAX22190_FAULT1_EN_REG);
+
+		PRINT_ERR_BIT(data->fault1.reg_bits.max22190_CRC,
+			      data->fault1_en.reg_bits.max22190_CRCE);
+		PRINT_ERR_BIT(data->fault1.reg_bits.max22190_POR,
+			      data->fault1_en.reg_bits.max22190_PORE);
+		PRINT_ERR_BIT(data->fault1.reg_bits.max22190_FAULT2,
+			      data->fault1_en.reg_bits.max22190_FAULT2E);
+		PRINT_ERR_BIT(data->fault1.reg_bits.max22190_24VL,
+			      data->fault1_en.reg_bits.max22190_24VLE);
+		PRINT_ERR_BIT(data->fault1.reg_bits.max22190_24VM,
+			      data->fault1_en.reg_bits.max22190_24VME);
+		if (config->variant == MAX22190) {
+			PRINT_ERR_BIT(data->fault1.reg_bits.max22190_ALRMT2,
+				      data->fault1_en.reg_bits.max22190_ALRMT2E);
+			PRINT_ERR_BIT(data->fault1.reg_bits.max22190_ALRMT1,
+				      data->fault1_en.reg_bits.max22190_ALRMT1E);
+			PRINT_ERR_BIT(data->fault1.reg_bits.max22190_WBG,
+				      data->fault1_en.reg_bits.max22190_WBGE);
+			if (data->fault1.reg_bits.max22190_WBG &
+			    data->fault1_en.reg_bits.max22190_WBGE) {
+				uint8_t wb_val = max22190_reg_read(dev, MAX22190_WB_REG);
+
+				max22190_update_wb_stat(dev, (uint8_t)wb_val);
+			}
+		}
+		if (data->fault1.reg_bits.max22190_FAULT2) {
+			/* FAULT2 */
+			data->fault2.reg_raw = max22190_reg_read(dev, MAX22190_FAULT2_REG);
+
+			/* FAULT2_EN */
+			data->fault2_en.reg_raw = max22190_reg_read(dev, MAX22190_FAULT2_EN_REG);
+
+			PRINT_ERR_BIT(data->fault2.reg_bits.max22190_OTSHDN,
+				      data->fault2_en.reg_bits.max22190_OTSHDNE);
+			PRINT_ERR_BIT(data->fault2.reg_bits.max22190_FAULT8CK,
+				      data->fault2_en.reg_bits.max22190_FAULT8CKE);
+			if (config->variant == MAX22190) {
+				PRINT_ERR_BIT(data->fault2.reg_bits.max22190_RFWBS,
+					      data->fault2_en.reg_bits.max22190_RFWBSE);
+				PRINT_ERR_BIT(data->fault2.reg_bits.max22190_RFWBO,
+					      data->fault2_en.reg_bits.max22190_RFWBOE);
+				PRINT_ERR_BIT(data->fault2.reg_bits.max22190_RFDIS,
+					      data->fault2_en.reg_bits.max22190_RFDISE);
+				PRINT_ERR_BIT(data->fault2.reg_bits.max22190_RFDIO,
+					      data->fault2_en.reg_bits.max22190_RFDIOE);
+			}
+		}
+	}
+}
+
+static void max22190_state_get(const struct device *dev)
+{
+	const struct max22190_config *config = dev->config;
+
+	if (gpio_pin_get_dt(&config->fault_gpio)) {
+		max22190_fault_check(dev);
+	}
+
+	/* We are reading WB reg because on first byte will be clocked out DI reg
+	 * on second byte we will ge WB value.
+	 */
+	uint8_t wb_val = max22190_reg_read(dev, MAX22190_WB_REG);
+
+	max22190_update_wb_stat(dev, (uint8_t)wb_val);
+}
+
+static int gpio_max22190_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
+{
+	int err = 0;
+
+	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED) {
+		return -ENOTSUP;
+	}
+
+	if ((flags & GPIO_SINGLE_ENDED) != 0) {
+		return -ENOTSUP;
+	}
+
+	if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
+		return -ENOTSUP;
+	}
+
+	if (flags & GPIO_INT_ENABLE) {
+		return -ENOTSUP;
+	}
+
+	switch (flags & GPIO_DIR_MASK) {
+	case GPIO_INPUT:
+		LOG_INF("Nothing to do, only INPUT supported");
+		break;
+	default:
+		LOG_ERR("On MAX22190 only input option is available!");
+		return -ENOTSUP;
+	}
+
+	return err;
+}
+
+static void max22190_filter_set(const struct device *dev)
+{
+	const struct max22190_config *config = dev->config;
+
+	for (int ch_n = 0; ch_n < 8; ch_n++) {
+		max22190_reg_write(dev, MAX22190_FILTER_IN_REG(ch_n), config->filter[ch_n].reg_raw);
+	}
+}
+
+static int max22190_fault_set(const struct device *dev)
+{
+	const struct max22190_data *data = dev->data;
+	int ret = 0;
+
+	ret = max22190_reg_write(dev, MAX22190_FAULT1_EN_REG, data->fault1_en.reg_raw);
+	if (ret) {
+		goto exit_fault_set;
+	}
+
+	ret = max22190_reg_write(dev, MAX22190_FAULT1_REG, data->fault1.reg_raw);
+	if (ret) {
+		goto exit_fault_set;
+	}
+
+	ret = max22190_reg_write(dev, MAX22190_FAULT2_EN_REG, data->fault2_en.reg_raw);
+	if (ret) {
+		goto exit_fault_set;
+	}
+
+	ret = max22190_reg_write(dev, MAX22190_FAULT2_REG, data->fault2.reg_raw);
+	if (ret) {
+		goto exit_fault_set;
+	}
+
+	return ret;
+
+exit_fault_set:
+	LOG_ERR("Err spi_transcieve_dt  [%d]\n", ret);
+
+	return ret;
+}
+
+static int gpio_max22190_port_get_raw(const struct device *dev, gpio_port_value_t *value)
+{
+	const struct max22190_data *data = dev->data;
+
+	max22190_state_get(dev);
+	*value = 0;
+	for (int ch_n = 0; ch_n < 8; ch_n++) {
+		/* IN ch state */
+		*value |= data->channels[ch_n] << ch_n;
+	}
+
+	return 0;
+}
+
+static int gpio_max22190_init(const struct device *dev)
+{
+	const struct max22190_config *config = dev->config;
+	struct max22190_data *data = dev->data;
+
+	LOG_DBG("GPIO MAX22190 init IN\n");
+
+	int err = 0;
+
+	if (!spi_is_ready_dt(&config->spi)) {
+		LOG_ERR("SPI bus is not ready\n");
+		return -ENODEV;
+	}
+
+	/* setup READY gpio - normal low */
+	if (!gpio_is_ready_dt(&config->ready_gpio)) {
+		LOG_ERR("READY GPIO device not ready");
+		return -ENODEV;
+	}
+
+	err = gpio_pin_configure_dt(&config->ready_gpio, GPIO_INPUT);
+	if (err < 0) {
+		LOG_ERR("Failed to configure reset GPIO");
+		return err;
+	}
+
+	/* setup FAULT gpio - normal high */
+	if (!gpio_is_ready_dt(&config->fault_gpio)) {
+		LOG_ERR("FAULT GPIO device not ready");
+		return -ENODEV;
+	}
+
+	err = gpio_pin_configure_dt(&config->fault_gpio, GPIO_INPUT | GPIO_PULL_UP);
+	if (err < 0) {
+		LOG_ERR("Failed to configure DC GPIO");
+		return err;
+	}
+
+	/* setup LATCH gpio - normal high */
+	if (!gpio_is_ready_dt(&config->latch_gpio)) {
+		LOG_ERR("LATCH GPIO device not ready");
+		return -ENODEV;
+	}
+
+	err = gpio_pin_configure_dt(&config->latch_gpio, GPIO_OUTPUT_INACTIVE);
+	if (err < 0) {
+		LOG_ERR("Failed to configure busy GPIO");
+		return err;
+	}
+
+	for (int i = 0; i < 8; i++) {
+		if (config->variant == MAX22190) {
+			LOG_DBG("IN%d WBE [%d] FBP[%d] DELAY[%d]\n", i,
+				config->filter[i].reg_bits.max22190_WBE,
+				config->filter[i].reg_bits.max22190_FBP,
+				config->filter[i].reg_bits.max22190_DELAY);
+		} else {
+			LOG_DBG("IN%d FBP[%d] DELAY[%d]\n", i,
+				config->filter[i].reg_bits.max22190_FBP,
+				config->filter[i].reg_bits.max22190_DELAY);
+		}
+	}
+
+	LOG_DBG(" > MAX22190 MODE: %x", config->mode);
+	LOG_DBG(" > MAX22190 PKT SIZE: %dbits (%dbytes)", config->pkt_size * 8, config->pkt_size);
+	LOG_DBG(" > MAX22190 CRC: %s", config->crc_en ? "enable" : "disable");
+
+	if (config->variant == MAX22190) {
+		data->fault1_en.reg_bits.max22190_WBGE = 1;
+	}
+	data->fault1_en.reg_bits.max22190_PORE = 1;
+
+	/* Set all FAULT and FAULT_EN regs */
+	max22190_fault_set(dev);
+
+	/* Set channels filters */
+	max22190_filter_set(dev);
+
+	/* POR bit need to be cleared after start */
+	MAX22190_CLEAN_POR(dev);
+
+	LOG_DBG("GPIO MAX22190 init OUT\n");
+	return 0;
+}
+
+static DEVICE_API(gpio, gpio_max22190_api) = {
+	.pin_configure = gpio_max22190_config,
+	.port_get_raw = gpio_max22190_port_get_raw,
+};
+
+/* Assign appropriate value for FILTER delay*/
+#define MAX22190_FILTER_SET_DELAY(delay)                                                           \
+	delay == 20000   ? MAX22190_DELAY_20000US                                                  \
+	: delay == 12800 ? MAX22190_DELAY_12800US                                                  \
+	: delay == 3200  ? MAX22190_DELAY_3200US                                                   \
+	: delay == 1600  ? MAX22190_DELAY_1800US                                                   \
+	: delay == 800   ? MAX22190_DELAY_800US                                                    \
+	: delay == 400   ? MAX22190_DELAY_400US                                                    \
+	: delay == 100   ? MAX22190_DELAY_100US                                                    \
+	: delay == 50    ? MAX22190_DELAY_50US                                                     \
+			 : MAX22190_DELAY_20000US
+
+/* Assigning proper variant for differentiating register map */
+#define MAX22190_CONFIG_SET_VARIANT(model)                                                         \
+	model == 22190   ? MAX22190 /* MAX22190 */                                                 \
+	: model == 22199 ? MAX22199 /* MAX22199 */                                                 \
+			 : MAX22190 /* Default fallback */
+
+/* Set FILTERx reg */
+#define MAX22190_FILTER_BY_IDX(id, model, idx)                                                     \
+	{                                                                                          \
+		.reg_bits.max22190_DELAY =                                                         \
+			MAX22190_FILTER_SET_DELAY(DT_INST_PROP_BY_IDX(id, filter_delays, idx)),    \
+		.reg_bits.max22190_FBP = DT_INST_PROP_BY_IDX(id, filter_fbps, idx),                \
+		.reg_bits.max22190_WBE =                                                           \
+			(model == 22190) ? DT_INST_PROP_BY_IDX(id, filter_wbes, idx) : 0,          \
+	}
+
+#define GPIO_MAX22190_DEVICE(id, model)                                                            \
+	static const struct max22190_config max##model##_##id##_cfg = {                            \
+		.spi = SPI_DT_SPEC_INST_GET(id, SPI_OP_MODE_MASTER | SPI_WORD_SET(8U), 0U),        \
+		.ready_gpio = GPIO_DT_SPEC_INST_GET(id, drdy_gpios),                               \
+		.fault_gpio = GPIO_DT_SPEC_INST_GET(id, fault_gpios),                              \
+		.latch_gpio = GPIO_DT_SPEC_INST_GET(id, latch_gpios),                              \
+		.mode = DT_INST_PROP(id, max22190_mode),                                           \
+		.crc_en = !(DT_INST_PROP(id, max22190_mode) & 0x1),                                \
+		.pkt_size = !(DT_INST_PROP(id, max22190_mode) & 0x1) ? 3 : 2,                      \
+		.variant = MAX22190_CONFIG_SET_VARIANT(model),                                     \
+		.filter =                                                                          \
+			{                                                                          \
+				MAX22190_FILTER_BY_IDX(id, model, 0),                              \
+				MAX22190_FILTER_BY_IDX(id, model, 1),                              \
+				MAX22190_FILTER_BY_IDX(id, model, 2),                              \
+				MAX22190_FILTER_BY_IDX(id, model, 3),                              \
+				MAX22190_FILTER_BY_IDX(id, model, 4),                              \
+				MAX22190_FILTER_BY_IDX(id, model, 5),                              \
+				MAX22190_FILTER_BY_IDX(id, model, 6),                              \
+				MAX22190_FILTER_BY_IDX(id, model, 7),                              \
+			},                                                                         \
+	};                                                                                         \
+                                                                                                   \
+	static struct max22190_data max##model##_##id##_data;                                      \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(id, &gpio_max22190_init, NULL, &max##model##_##id##_data,            \
+			      &max##model##_##id##_cfg, POST_KERNEL,                               \
+			      CONFIG_GPIO_MAX22190_INIT_PRIORITY, &gpio_max22190_api);
+
+#undef DT_DRV_COMPAT
+#define DT_DRV_COMPAT adi_max22190_gpio
+DT_INST_FOREACH_STATUS_OKAY_VARGS(GPIO_MAX22190_DEVICE, 22190)
+
+#undef DT_DRV_COMPAT
+#define DT_DRV_COMPAT adi_max22199_gpio
+DT_INST_FOREACH_STATUS_OKAY_VARGS(GPIO_MAX22190_DEVICE, 22199)
+
+#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 0
+#warning "GPIO MAX22190 driver enabled without any devices"
+#endif
diff --git a/drivers/gpio/gpio_mchp_mec5.c b/drivers/gpio/gpio_mchp_mec5.c
index ef339eae1ee..8b3fe7a598b 100644
--- a/drivers/gpio/gpio_mchp_mec5.c
+++ b/drivers/gpio/gpio_mchp_mec5.c
@@ -475,7 +475,7 @@ static void gpio_mec5_port_isr(const struct device *dev)
 }
 
 /* GPIO driver official API table */
-static const struct gpio_driver_api gpio_mec5_driver_api = {
+static DEVICE_API(gpio, gpio_mec5_driver_api) = {
 	.pin_configure = gpio_mec5_configure,
 	.port_get_raw = gpio_mec5_port_get_raw,
 	.port_set_masked_raw = gpio_mec5_port_set_masked_raw,
diff --git a/drivers/gpio/gpio_mcp23xxx.c b/drivers/gpio/gpio_mcp23xxx.c
index 48ed4bf06cd..a706f518ed7 100644
--- a/drivers/gpio/gpio_mcp23xxx.c
+++ b/drivers/gpio/gpio_mcp23xxx.c
@@ -23,7 +23,7 @@
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(gpio_mcp23xxx);
 
-#define MCP23XXX_RESET_TIME_US 1
+#define MCP23XXX_RESET_TIME_US 2
 
 /**
  * @brief Reads given register from mcp23xxx.
diff --git a/drivers/gpio/gpio_mcux.c b/drivers/gpio/gpio_mcux.c
index 9a360a72a55..44e6941ad7d 100644
--- a/drivers/gpio/gpio_mcux.c
+++ b/drivers/gpio/gpio_mcux.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017, 2023-2024 NXP
+ * Copyright 2017, 2023-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,12 +17,19 @@
 
 #include <zephyr/drivers/gpio/gpio_utils.h>
 
+#if defined(CONFIG_PINCTRL_NXP_IOCON)
+#include <fsl_iopctl.h>
+/* Use IOCON to configure electrical characteristic, set PORT_Type as void. */
+#define PORT_Type void
+#endif
+
 struct gpio_mcux_config {
 	/* gpio_driver_config needs to be first */
 	struct gpio_driver_config common;
 	GPIO_Type *gpio_base;
 	PORT_Type *port_base;
 	unsigned int flags;
+	uint32_t port_no;
 };
 
 struct gpio_mcux_data {
@@ -32,8 +39,80 @@ struct gpio_mcux_data {
 	sys_slist_t callbacks;
 };
 
-static int gpio_mcux_configure(const struct device *dev,
-			       gpio_pin_t pin, gpio_flags_t flags)
+#if defined(CONFIG_PINCTRL_NXP_IOCON)
+static int gpio_mcux_iopctl_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
+{
+	const struct gpio_mcux_config *config = dev->config;
+	GPIO_Type *gpio_base = config->gpio_base;
+	uint32_t port_no = config->port_no;
+	volatile uint32_t pinconfig = 0;
+
+	if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
+		return -ENOTSUP;
+	}
+
+	if ((flags & GPIO_SINGLE_ENDED) != 0) {
+		return -ENOTSUP;
+	}
+
+	/* The flags contain options that require touching registers in the
+	 * GPIO module and the corresponding PORT module.
+	 *
+	 * Start with the GPIO module and set up the pin direction register.
+	 * 0 - pin is input, 1 - pin is output
+	 */
+
+	switch (flags & GPIO_DIR_MASK) {
+	case GPIO_INPUT:
+		gpio_base->PDDR &= ~BIT(pin);
+		/* Enable input buffer for input pins */
+		pinconfig |= IOPCTL_INBUF_EN;
+		break;
+	case GPIO_OUTPUT:
+		if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
+			gpio_base->PSOR = BIT(pin);
+		} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
+			gpio_base->PCOR = BIT(pin);
+		}
+		gpio_base->PDDR |= BIT(pin);
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	/* Select GPIO mux for this pin (func 0 is always GPIO) */
+	pinconfig |= IOPCTL_FUNC0;
+
+	if ((flags & GPIO_PULL_UP) != 0) {
+		/* Enable and select pull up. */
+		pinconfig |= (IOPCTL_PUPD_EN | IOPCTL_PULLUP_EN);
+	} else if ((flags & GPIO_PULL_DOWN) != 0) {
+		/* Enable and select pull down. */
+		pinconfig |= (IOPCTL_PUPD_EN | IOPCTL_PULLDOWN_EN);
+	}
+
+#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH
+	/* Determine the drive strength */
+	switch (flags & KINETIS_GPIO_DS_MASK) {
+	case KINETIS_GPIO_DS_DFLT:
+		/* Default is low drive strength */
+		pinconfig |= IOPCTL_DRIVE_100OHM;
+		break;
+	case KINETIS_GPIO_DS_ALT:
+		/* Alternate is high drive strength */
+		pinconfig |= IOPCTL_DRIVE_33OHM;
+		break;
+	default:
+		return -ENOTSUP;
+	}
+#endif /* defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */
+
+	IOPCTL_PinMuxSet(port_no, pin, pinconfig);
+
+	return 0;
+}
+#else
+static int gpio_mcux_port_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
 {
 	const struct gpio_mcux_config *config = dev->config;
 	GPIO_Type *gpio_base = config->gpio_base;
@@ -123,6 +202,7 @@ static int gpio_mcux_configure(const struct device *dev,
 
 	return 0;
 }
+#endif /* defined(CONFIG_PINCTRL_NXP_IOCON) */
 
 static int gpio_mcux_port_get_raw(const struct device *dev, uint32_t *value)
 {
@@ -134,9 +214,7 @@ static int gpio_mcux_port_get_raw(const struct device *dev, uint32_t *value)
 	return 0;
 }
 
-static int gpio_mcux_port_set_masked_raw(const struct device *dev,
-					 uint32_t mask,
-					 uint32_t value)
+static int gpio_mcux_port_set_masked_raw(const struct device *dev, uint32_t mask, uint32_t value)
 {
 	const struct gpio_mcux_config *config = dev->config;
 	GPIO_Type *gpio_base = config->gpio_base;
@@ -146,8 +224,7 @@ static int gpio_mcux_port_set_masked_raw(const struct device *dev,
 	return 0;
 }
 
-static int gpio_mcux_port_set_bits_raw(const struct device *dev,
-				       uint32_t mask)
+static int gpio_mcux_port_set_bits_raw(const struct device *dev, uint32_t mask)
 {
 	const struct gpio_mcux_config *config = dev->config;
 	GPIO_Type *gpio_base = config->gpio_base;
@@ -157,8 +234,7 @@ static int gpio_mcux_port_set_bits_raw(const struct device *dev,
 	return 0;
 }
 
-static int gpio_mcux_port_clear_bits_raw(const struct device *dev,
-					 uint32_t mask)
+static int gpio_mcux_port_clear_bits_raw(const struct device *dev, uint32_t mask)
 {
 	const struct gpio_mcux_config *config = dev->config;
 	GPIO_Type *gpio_base = config->gpio_base;
@@ -178,11 +254,10 @@ static int gpio_mcux_port_toggle_bits(const struct device *dev, uint32_t mask)
 	return 0;
 }
 
+#if !(defined(CONFIG_PINCTRL_NXP_IOCON))
 #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
-static uint32_t get_port_pcr_irqc_value_from_flags(const struct device *dev,
-						   uint32_t pin,
-						   enum gpio_int_mode mode,
-						   enum gpio_int_trig trig)
+static uint32_t get_port_pcr_irqc_value_from_flags(const struct device *dev, uint32_t pin,
+						   enum gpio_int_mode mode, enum gpio_int_trig trig)
 {
 	port_interrupt_t port_interrupt = 0;
 
@@ -214,22 +289,21 @@ static uint32_t get_port_pcr_irqc_value_from_flags(const struct device *dev,
 
 	return PORT_PCR_IRQC(port_interrupt);
 }
-#endif  /* !defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT */
+#endif /* !defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT */
+#endif /* !(defined(CONFIG_PINCTRL_NXP_IOCON)) */
 
 #if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \
 		FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
 
-#define GPIO_MCUX_INTERRUPT_DISABLED		0
-#define GPIO_MCUX_INTERRUPT_LOGIC_0		0x8
-#define GPIO_MCUX_INTERRUPT_RISING_EDGE		0x9
-#define GPIO_MCUX_INTERRUPT_FALLING_EDGE	0xA
-#define GPIO_MCUX_INTERRUPT_BOTH_EDGE		0xB
-#define GPIO_MCUX_INTERRUPT_LOGIC_1		0xC
-
-static uint32_t get_gpio_icr_irqc_value_from_flags(const struct device *dev,
-						   uint32_t pin,
-						   enum gpio_int_mode mode,
-						   enum gpio_int_trig trig)
+#define GPIO_MCUX_INTERRUPT_DISABLED     0
+#define GPIO_MCUX_INTERRUPT_LOGIC_0      0x8
+#define GPIO_MCUX_INTERRUPT_RISING_EDGE  0x9
+#define GPIO_MCUX_INTERRUPT_FALLING_EDGE 0xA
+#define GPIO_MCUX_INTERRUPT_BOTH_EDGE    0xB
+#define GPIO_MCUX_INTERRUPT_LOGIC_1      0xC
+
+static uint32_t get_gpio_icr_irqc_value_from_flags(const struct device *dev, uint32_t pin,
+						   enum gpio_int_mode mode, enum gpio_int_trig trig)
 {
 	uint8_t gpio_interrupt = 0;
 
@@ -261,49 +335,48 @@ static uint32_t get_gpio_icr_irqc_value_from_flags(const struct device *dev,
 
 	return GPIO_ICR_IRQC(gpio_interrupt);
 }
-#endif  /* (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) */
+#endif /* (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) */
 
-static int gpio_mcux_pin_interrupt_configure(const struct device *dev,
-					     gpio_pin_t pin, enum gpio_int_mode mode,
-					     enum gpio_int_trig trig)
+static int gpio_mcux_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
+					     enum gpio_int_mode mode, enum gpio_int_trig trig)
 {
 	const struct gpio_mcux_config *config = dev->config;
 	GPIO_Type *gpio_base = config->gpio_base;
+#if !(defined(CONFIG_PINCTRL_NXP_IOCON))
 	PORT_Type *port_base = config->port_base;
 
 	/* Check for an invalid pin number */
 	if (pin >= ARRAY_SIZE(port_base->PCR)) {
 		return -EINVAL;
 	}
+#endif
 
 	/* Check for an invalid pin configuration */
-	if ((mode != GPIO_INT_MODE_DISABLED) &&
-	    ((gpio_base->PDDR & BIT(pin)) != 0)) {
+	if ((mode != GPIO_INT_MODE_DISABLED) && ((gpio_base->PDDR & BIT(pin)) != 0)) {
 		return -EINVAL;
 	}
 
 	/* Check if GPIO port supports interrupts */
-	if ((mode != GPIO_INT_MODE_DISABLED) &&
-	    ((config->flags & GPIO_INT_ENABLE) == 0U)) {
+	if ((mode != GPIO_INT_MODE_DISABLED) && ((config->flags & GPIO_INT_ENABLE) == 0U)) {
 		return -ENOTSUP;
 	}
 
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
-	uint32_t pcr = get_port_pcr_irqc_value_from_flags(dev, pin, mode, trig);
-
-	port_base->PCR[pin] = (port_base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | pcr;
-#elif (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \
+#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \
 		FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
 	uint32_t icr = get_gpio_icr_irqc_value_from_flags(dev, pin, mode, trig);
 
 	gpio_base->ICR[pin] = (gpio_base->ICR[pin] & ~GPIO_ICR_IRQC_MASK) | icr;
-#endif  /* !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) */
+#elif !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+	uint32_t pcr = get_port_pcr_irqc_value_from_flags(dev, pin, mode, trig);
+
+	port_base->PCR[pin] = (port_base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | pcr;
+#endif /* !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) */
 
 	return 0;
 }
 
-static int gpio_mcux_manage_callback(const struct device *dev,
-				     struct gpio_callback *callback, bool set)
+static int gpio_mcux_manage_callback(const struct device *dev, struct gpio_callback *callback,
+				     bool set)
 {
 	struct gpio_mcux_data *data = dev->data;
 
@@ -316,21 +389,21 @@ static void gpio_mcux_port_isr(const struct device *dev)
 	struct gpio_mcux_data *data = dev->data;
 	uint32_t int_status;
 
-#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
-	int_status = config->port_base->ISFR;
-
-	/* Clear the port interrupts */
-	config->port_base->ISFR = int_status;
-#elif (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \
+#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \
 		FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT)
 	int_status = config->gpio_base->ISFR[0];
 
 	/* Clear the gpio interrupts */
 	config->gpio_base->ISFR[0] = int_status;
+#elif !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT)
+	int_status = config->port_base->ISFR;
+
+	/* Clear the port interrupts */
+	config->port_base->ISFR = int_status;
 #else
 	int_status = 0U;
 	ARG_UNUSED(config);
-#endif  /* !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) */
+#endif /* !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) */
 
 	gpio_fire_callbacks(&data->callbacks, dev, int_status);
 }
@@ -350,20 +423,18 @@ static void gpio_mcux_shared_cluster_isr(const struct device *ports[])
 
 #define CLUSTER_ARRAY_ELEMENT(node_id) DEVICE_DT_GET(node_id),
 
-#define GPIO_MCUX_CLUSTER_INIT(node_id)								\
-	const struct device *shared_array##node_id[DT_CHILD_NUM_STATUS_OKAY(node_id) + 1] =	\
-		{DT_FOREACH_CHILD_STATUS_OKAY(node_id, CLUSTER_ARRAY_ELEMENT) NULL};	\
-												\
-	static int gpio_mcux_shared_interrupt_init##node_id(void)	\
-	{								\
-		IRQ_CONNECT(DT_IRQN(node_id),				\
-			    DT_IRQ(node_id, priority),			\
-			    gpio_mcux_shared_cluster_isr,		\
-			    shared_array##node_id, 0);			\
-		irq_enable(DT_IRQN(node_id));				\
-									\
-		return 0;						\
-	}								\
+#define GPIO_MCUX_CLUSTER_INIT(node_id)                                                            \
+	const struct device *shared_array##node_id[DT_CHILD_NUM_STATUS_OKAY(node_id) + 1] = {      \
+		DT_FOREACH_CHILD_STATUS_OKAY(node_id, CLUSTER_ARRAY_ELEMENT) NULL};                \
+                                                                                                   \
+	static int gpio_mcux_shared_interrupt_init##node_id(void)                                  \
+	{                                                                                          \
+		IRQ_CONNECT(DT_IRQN(node_id), DT_IRQ(node_id, priority),                           \
+			    gpio_mcux_shared_cluster_isr, shared_array##node_id, 0);               \
+		irq_enable(DT_IRQN(node_id));                                                      \
+                                                                                                   \
+		return 0;                                                                          \
+	}                                                                                          \
 	SYS_INIT(gpio_mcux_shared_interrupt_init##node_id, POST_KERNEL, 0);
 
 DT_FOREACH_STATUS_OKAY(nxp_gpio_cluster, GPIO_MCUX_CLUSTER_INIT)
@@ -391,7 +462,11 @@ static int gpio_mcux_port_get_direction(const struct device *dev, gpio_port_pins
 #endif /* CONFIG_GPIO_GET_DIRECTION */
 
 static DEVICE_API(gpio, gpio_mcux_driver_api) = {
-	.pin_configure = gpio_mcux_configure,
+#if defined(CONFIG_PINCTRL_NXP_IOCON)
+	.pin_configure = gpio_mcux_iopctl_configure,
+#else
+	.pin_configure = gpio_mcux_port_configure,
+#endif
 	.port_get_raw = gpio_mcux_port_get_raw,
 	.port_set_masked_raw = gpio_mcux_port_set_masked_raw,
 	.port_set_bits_raw = gpio_mcux_port_set_bits_raw,
@@ -404,47 +479,44 @@ static DEVICE_API(gpio, gpio_mcux_driver_api) = {
 #endif /* CONFIG_GPIO_GET_DIRECTION */
 };
 
-#define GPIO_MCUX_IRQ_INIT(n)						\
-	do {								\
-		IRQ_CONNECT(DT_INST_IRQN(n),				\
-			    DT_INST_IRQ(n, priority),			\
-			    gpio_mcux_port_isr,				\
-			    DEVICE_DT_INST_GET(n), 0);			\
-									\
-		irq_enable(DT_INST_IRQN(n));				\
+#define GPIO_MCUX_IRQ_INIT(n)                                                                      \
+	do {                                                                                       \
+		IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), gpio_mcux_port_isr,         \
+			    DEVICE_DT_INST_GET(n), 0);                                             \
+                                                                                                   \
+		irq_enable(DT_INST_IRQN(n));                                                       \
 	} while (false)
 
 #define GPIO_PORT_BASE_ADDR(n) DT_REG_ADDR(DT_INST_PHANDLE(n, nxp_kinetis_port))
-
-#define GPIO_DEVICE_INIT_MCUX(n)					\
-	static int gpio_mcux_port## n ## _init(const struct device *dev); \
-									\
-	static const struct gpio_mcux_config gpio_mcux_port## n ## _config = {\
-		.common = {						\
-			.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
-		},							\
-		.gpio_base = (GPIO_Type *) DT_INST_REG_ADDR(n),		\
-		.port_base = (PORT_Type *) GPIO_PORT_BASE_ADDR(n),	\
-		.flags = UTIL_AND(UTIL_OR(DT_INST_IRQ_HAS_IDX(n, 0),	\
-				GPIO_HAS_SHARED_IRQ), GPIO_INT_ENABLE), \
-	};								\
-									\
-	static struct gpio_mcux_data gpio_mcux_port## n ##_data;	\
-									\
-	DEVICE_DT_INST_DEFINE(n,					\
-			    gpio_mcux_port## n ##_init,			\
-			    NULL,					\
-			    &gpio_mcux_port## n ##_data,		\
-			    &gpio_mcux_port## n##_config,		\
-			    POST_KERNEL,				\
-			    CONFIG_GPIO_INIT_PRIORITY,			\
-			    &gpio_mcux_driver_api);			\
-									\
-	static int gpio_mcux_port## n ##_init(const struct device *dev)	\
-	{								\
+#define GPIO_PORT_NUMBER(n) COND_CODE_1(DT_INST_NODE_HAS_PROP(n, gpio_port_offest),	\
+						(DT_INST_PROP(n, gpio_port_offest) + n), (n))	\
+
+#define GPIO_DEVICE_INIT_MCUX(n)                                                                   \
+	static int gpio_mcux_port##n##_init(const struct device *dev);                             \
+                                                                                                   \
+	static const struct gpio_mcux_config gpio_mcux_port##n##_config = {                        \
+		.common =                                                                          \
+			{                                                                          \
+				.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),               \
+			},                                                                         \
+		.gpio_base = (GPIO_Type *)DT_INST_REG_ADDR(n),                                     \
+		.port_base = (PORT_Type *)GPIO_PORT_BASE_ADDR(n),                                  \
+		.flags = UTIL_AND(UTIL_OR(DT_INST_IRQ_HAS_IDX(n, 0), GPIO_HAS_SHARED_IRQ),         \
+				  GPIO_INT_ENABLE),                                                \
+		.port_no = GPIO_PORT_NUMBER(n),						\
+	};                                                                                         \
+                                                                                                   \
+	static struct gpio_mcux_data gpio_mcux_port##n##_data;                                     \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, gpio_mcux_port##n##_init, NULL, &gpio_mcux_port##n##_data,        \
+			      &gpio_mcux_port##n##_config, POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, \
+			      &gpio_mcux_driver_api);                                              \
+                                                                                                   \
+	static int gpio_mcux_port##n##_init(const struct device *dev)                              \
+	{                                                                                          \
 		IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0),			\
-			(GPIO_MCUX_IRQ_INIT(n);))			\
-		return 0;						\
+			(GPIO_MCUX_IRQ_INIT(n);))                                         \
+		return 0;                                                                          \
 	}
 
 DT_INST_FOREACH_STATUS_OKAY(GPIO_DEVICE_INIT_MCUX)
diff --git a/drivers/gpio/gpio_mcux_igpio.c b/drivers/gpio/gpio_mcux_igpio.c
index e1d1b82619b..df140eb55c3 100644
--- a/drivers/gpio/gpio_mcux_igpio.c
+++ b/drivers/gpio/gpio_mcux_igpio.c
@@ -17,6 +17,7 @@
 #include <fsl_gpio.h>
 
 #include <zephyr/drivers/pinctrl.h>
+#include <zephyr/dt-bindings/gpio/nxp-imx-igpio.h>
 
 #include <zephyr/drivers/gpio/gpio_utils.h>
 
@@ -90,8 +91,13 @@ static int mcux_igpio_configure(const struct device *dev,
 	if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
 		reg |= IOMUXC_SW_PAD_CTL_PAD_PUE_MASK;
 		if (((flags & GPIO_PULL_UP) != 0)) {
-			/* Use 100K pullup */
-			reg |= IOMUXC_SW_PAD_CTL_PAD_PUS(2);
+			if ((flags & NXP_IGPIO_PULL_STRONG) != 0) {
+				/* Use 22K pullup */
+				reg |= IOMUXC_SW_PAD_CTL_PAD_PUS(3);
+			} else {
+				/* Use 100K pullup */
+				reg |= IOMUXC_SW_PAD_CTL_PAD_PUS(2);
+			}
 		} else {
 			/* 100K pulldown */
 			reg &= ~IOMUXC_SW_PAD_CTL_PAD_PUS_MASK;
diff --git a/drivers/gpio/gpio_mcux_lpc.c b/drivers/gpio/gpio_mcux_lpc.c
index 6a103a77dc8..ab8d9981170 100644
--- a/drivers/gpio/gpio_mcux_lpc.c
+++ b/drivers/gpio/gpio_mcux_lpc.c
@@ -17,6 +17,7 @@
 #include <errno.h>
 #include <zephyr/device.h>
 #include <zephyr/drivers/gpio.h>
+#include <zephyr/pm/device.h>
 #include <zephyr/irq.h>
 #include <soc.h>
 #include <fsl_common.h>
@@ -398,6 +399,13 @@ static int gpio_mcux_lpc_pin_interrupt_configure(const struct device *dev,
 #endif
 }
 
+void gpio_mcux_lpc_trigger_cb(const struct device *dev, uint32_t pins)
+{
+	struct gpio_mcux_lpc_data *data = dev->data;
+
+	gpio_fire_callbacks(&data->callbacks, dev, pins);
+}
+
 static int gpio_mcux_lpc_manage_cb(const struct device *port,
 				   struct gpio_callback *callback, bool set)
 {
@@ -406,14 +414,34 @@ static int gpio_mcux_lpc_manage_cb(const struct device *port,
 	return gpio_manage_callback(&data->callbacks, callback, set);
 }
 
-static int gpio_mcux_lpc_init(const struct device *dev)
+static int gpio_mcux_lpc_pm_action(const struct device *dev, enum pm_device_action action)
 {
 	const struct gpio_mcux_lpc_config *config = dev->config;
-	GPIO_PortInit(config->gpio_base, config->port_no);
 
+	switch (action) {
+	case PM_DEVICE_ACTION_RESUME:
+		break;
+	case PM_DEVICE_ACTION_SUSPEND:
+		break;
+	case PM_DEVICE_ACTION_TURN_OFF:
+		break;
+	case PM_DEVICE_ACTION_TURN_ON:
+		GPIO_PortInit(config->gpio_base, config->port_no);
+		break;
+	default:
+		return -ENOTSUP;
+	}
 	return 0;
 }
 
+static int gpio_mcux_lpc_init(const struct device *dev)
+{
+	/* Rest of the init is done from the PM_DEVICE_TURN_ON action
+	 * which is invoked by pm_device_driver_init().
+	 */
+	return pm_device_driver_init(dev, gpio_mcux_lpc_pm_action);
+}
+
 static DEVICE_API(gpio, gpio_mcux_lpc_driver_api) = {
 	.pin_configure = gpio_mcux_lpc_configure,
 	.port_get_raw = gpio_mcux_lpc_port_get_raw,
@@ -465,7 +493,10 @@ static DEVICE_API(gpio, gpio_mcux_lpc_driver_api) = {
 											\
 	static struct gpio_mcux_lpc_data gpio_mcux_lpc_data_##n;			\
 											\
-	DEVICE_DT_INST_DEFINE(n, lpc_gpio_init_##n, NULL,				\
+	PM_DEVICE_DT_INST_DEFINE(n, gpio_mcux_lpc_pm_action);				\
+											\
+	DEVICE_DT_INST_DEFINE(n, lpc_gpio_init_##n,					\
+		    PM_DEVICE_DT_INST_GET(n),						\
 		    &gpio_mcux_lpc_data_##n,						\
 		    &gpio_mcux_lpc_config_##n, PRE_KERNEL_1,				\
 		    CONFIG_GPIO_INIT_PRIORITY,						\
diff --git a/drivers/gpio/gpio_mfxstm32l152.c b/drivers/gpio/gpio_mfxstm32l152.c
new file mode 100644
index 00000000000..bf2e57c138a
--- /dev/null
+++ b/drivers/gpio/gpio_mfxstm32l152.c
@@ -0,0 +1,639 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT st_mfxstm32l152
+
+/**
+ * @file Driver for ST MFXstm32l152 I2C-based GPIO driver.
+ */
+#include <errno.h>
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_utils.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util.h>
+
+#define LOG_LEVEL CONFIG_GPIO_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(mfxstm32l152);
+
+/* Register definitions */
+#define REG_ID                  0x00 /* const 0x7b */
+#define REG_GPIO_IRQ_PEND       0x0c /* GPIO irq pending */
+#define REG_GPIO_STATE          0x10 /* GPIO state */
+#define REG_SYS_CTRL            0x40 /* System control */
+#define REG_SYS_IRQ_MODE        0x41 /* System irq mode */
+#define SYS_IRQ_MODE_OPEN_DRAIN (0 << 0)
+#define SYS_IRQ_MODE_PUSH_PULL  (1 << 0)
+#define SYS_IRQ_MODE_POL_LOW    (0 << 1)
+#define SYS_IRQ_MODE_POL_HIGH   (1 << 1)
+#define REG_SYS_IRQ_EN          0x42 /* System irq enable */
+#define REG_GPIO_IRQ_EN         0x48 /* GPIO irq enable */
+#define REG_GPIO_IRQ_EVT        0x4c /* GPIO irq event */
+#define REG_GPIO_IRQ_TYPE       0x50 /* GPIO irq type */
+#define REG_GPIO_IRQ_ACK        0x54 /* GPIO irq ack */
+#define REG_GPIO_DIR            0x60 /* GPIO direction control */
+#define REG_GPIO_PUPD           0x68 /* GPIO pull-up/pull-down control */
+#define REG_GPIO_SET            0x6c /* GPIO set control */
+#define REG_GPIO_CLR            0x70 /* GPIO clear control */
+
+#define MFXSTM32L152_ID 0x7b
+
+/** Configuration data */
+struct mfxstm32l152_drv_cfg {
+	/* gpio_driver_config needs to be first */
+	struct gpio_driver_config common;
+
+	/** Master I2C DT specification */
+	struct i2c_dt_spec i2c_spec;
+	struct gpio_dt_spec int_gpio;
+};
+
+/** Cache of the pins configuration */
+struct mfxstm32l152_pins_state {
+	uint32_t direction;
+	uint32_t pupd;
+	uint32_t irq_enabled;
+};
+
+/** Runtime driver data */
+struct mfxstm32l152_drv_data {
+	/* gpio_driver_data needs to be first */
+	struct gpio_driver_data common;
+
+	/** Driver lock */
+	struct k_sem lock;
+
+	sys_slist_t callbacks;
+	struct k_work work;
+
+	const struct device *dev;
+	struct gpio_callback int_gpio_cb;
+	struct mfxstm32l152_pins_state pins_state;
+};
+
+/**
+ * @brief read a register value from the MFX
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @param reg Address of the register
+ * @param buf Pointer to the place to store the value
+ *
+ * @retval 0 if successful.
+ * @retval Negative value for error code.
+ */
+static int read_reg(const struct device *dev, uint8_t reg, uint8_t *buf)
+{
+	const struct mfxstm32l152_drv_cfg *const config = dev->config;
+	uint8_t value;
+	int ret;
+
+	ret = i2c_burst_read_dt(&config->i2c_spec, reg, (uint8_t *)&value, 1);
+	if (ret != 0) {
+		LOG_ERR("%s: error reading register 0x%X (%d)", dev->name, reg, ret);
+		return ret;
+	}
+
+	*buf = value;
+	LOG_DBG("%s: Read: REG[0x%X] = 0x%X", dev->name, reg, value);
+
+	return 0;
+}
+
+/**
+ * @brief write a register of the MFX
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @param reg Address of the register to be written
+ * @param value Value to be written into the register
+ *
+ * @retval 0 if successful.
+ * @retval Negative value for error code.
+ */
+static int write_reg(const struct device *dev, uint8_t reg, uint8_t value)
+{
+	const struct mfxstm32l152_drv_cfg *const config = dev->config;
+	uint8_t buf[2];
+	int ret;
+
+	LOG_DBG("%s: Write: REG[0x%X] = 0x%X", dev->name, reg, value);
+
+	buf[0] = reg;
+	buf[1] = value;
+	ret = i2c_write_dt(&config->i2c_spec, buf, sizeof(buf));
+	if (ret != 0) {
+		LOG_ERR("%s: error writing to register 0x%X (%d)", dev->name, reg, ret);
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Gets the state of a specified block of 3 registers from the MFX
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @param reg Address of the first of 3 registers to be read.
+ * @param buf Pointer to the buffer to output the register.
+ *
+ * @retval 0 if successful.
+ * @retval Negative value for error code.
+ */
+static int read_port_regs(const struct device *dev, uint8_t reg, uint32_t *buf)
+{
+	const struct mfxstm32l152_drv_cfg *const config = dev->config;
+	uint32_t port_data, value;
+	int ret;
+
+	ret = i2c_burst_read_dt(&config->i2c_spec, reg, (uint8_t *)&port_data, 3);
+	if (ret != 0) {
+		LOG_ERR("%s: error reading register 0x%X (%d)", dev->name, reg, ret);
+		return ret;
+	}
+
+	value = sys_le24_to_cpu(port_data);
+	*buf = value;
+	LOG_DBG("%s: Read: REG[0x%X] = 0x%X, REG[0x%X] = 0x%X, REG[0x%X] = 0x%X", dev->name, reg,
+		(*buf & 0xFF), (reg + 1), ((*buf >> 8) & 0xFF), (reg + 2), ((*buf >> 16) & 0xFF));
+
+	return 0;
+}
+
+/**
+ * @brief writes to a specified block of 3 registers into the MFX
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @param reg Address of the first of 3 registers to be written.
+ * @param value The pin value to be written into the registers.
+ *
+ * @retval 0 if successful.
+ * @retval Negative value for error code.
+ */
+static int write_port_regs(const struct device *dev, uint8_t reg, uint32_t value)
+{
+	const struct mfxstm32l152_drv_cfg *const config = dev->config;
+	uint8_t buf[4];
+	int ret;
+
+	LOG_DBG("%s: Write: REG[0x%X] = 0x%X, REG[0x%X] = 0x%X, REG[0x%X] = 0x%X", dev->name, reg,
+		(value & 0xFF), (reg + 1), ((value >> 8) & 0xFF), (reg + 2),
+		((value >> 16) & 0xFF));
+
+	buf[0] = reg;
+	sys_put_le24(value, &buf[1]);
+	ret = i2c_write_dt(&config->i2c_spec, buf, sizeof(buf));
+	if (ret != 0) {
+		LOG_ERR("%s: error writing to register 0x%X (%d)", dev->name, reg, ret);
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Handles interrupt triggered by the interrupt pin of MFXSTM32L152.
+ *
+ * If int_gpios is configured in device tree then this will be triggered each
+ * time a gpio configured as an input changes state. The gpio input states are
+ * read in this function which clears the interrupt.
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ */
+static void mfxstm32l152_handle_interrupt(const struct device *dev)
+{
+	struct mfxstm32l152_drv_data *drv_data = dev->data;
+	uint32_t irq_status;
+	int ret;
+
+	k_sem_take(&drv_data->lock, K_FOREVER);
+
+	/* Any interrupts enabled? */
+	if (!drv_data->pins_state.irq_enabled) {
+		k_sem_give(&drv_data->lock);
+		return;
+	}
+
+	/* Check pending irq status */
+	ret = read_port_regs(dev, REG_GPIO_IRQ_PEND, &irq_status);
+	if (ret != 0) {
+		k_sem_give(&drv_data->lock);
+		return;
+	}
+
+	if (irq_status == 0) {
+		k_sem_give(&drv_data->lock);
+		return;
+	}
+
+	/* Ack everything */
+	ret = write_port_regs(dev, REG_GPIO_IRQ_ACK, irq_status);
+	if (ret != 0) {
+		k_sem_give(&drv_data->lock);
+		return;
+	}
+
+	k_sem_give(&drv_data->lock);
+
+	gpio_fire_callbacks(&drv_data->callbacks, dev, irq_status);
+}
+
+/**
+ * @brief Work handler for MFXSTM32L152 interrupt
+ *
+ * @param work Work struct that contains pointer to interrupt handler function
+ */
+static void mfxstm32l152_work_handler(struct k_work *work)
+{
+	struct mfxstm32l152_drv_data *drv_data =
+		CONTAINER_OF(work, struct mfxstm32l152_drv_data, work);
+
+	mfxstm32l152_handle_interrupt(drv_data->dev);
+}
+
+/**
+ * @brief ISR for interrupt pin of MFXSTM32L152
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @param gpio_cb Pointer to callback function struct
+ * @param pins Bitmask of pins that triggered interrupt
+ */
+static void mfxstm32l152_int_gpio_handler(const struct device *dev, struct gpio_callback *gpio_cb,
+					  uint32_t pins)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(pins);
+
+	struct mfxstm32l152_drv_data *drv_data =
+		CONTAINER_OF(gpio_cb, struct mfxstm32l152_drv_data, int_gpio_cb);
+
+	k_work_submit(&drv_data->work);
+}
+
+static int set_pin_dir_mode(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
+{
+	struct mfxstm32l152_drv_data *const drvdata =
+		(struct mfxstm32l152_drv_data *const)dev->data;
+	uint32_t *dir_cache = &drvdata->pins_state.direction;
+	uint32_t *mode_cache = &drvdata->pins_state.pupd;
+	bool need_update = false;
+	uint32_t dir, mode;
+	int ret = 0;
+
+	/* In case of configure in output mode first set initial state */
+	if ((flags & GPIO_OUTPUT) != 0U) {
+		if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0U) {
+			ret = write_port_regs(dev, REG_GPIO_SET, BIT(pin));
+			if (ret != 0) {
+				goto out;
+			}
+		} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0U) {
+			ret = write_port_regs(dev, REG_GPIO_CLR, BIT(pin));
+			if (ret != 0) {
+				goto out;
+			}
+		}
+	}
+
+	/* Configure direction */
+	if ((flags & GPIO_OUTPUT) && ((*mode_cache & BIT(pin)) == 0)) {
+		dir = *dir_cache | BIT(pin);
+		need_update = true;
+	} else if ((flags & GPIO_INPUT) && ((*mode_cache & BIT(pin)) != 0)) {
+		dir = *dir_cache & ~BIT(pin);
+		need_update = true;
+	}
+	if (need_update) {
+		ret = write_port_regs(dev, REG_GPIO_DIR, dir);
+		if (ret != 0) {
+			goto out;
+		}
+		*dir_cache = dir;
+	}
+
+	/* In case of input mode, configure PullUp/ PullDown */
+	need_update = false;
+	if ((flags & GPIO_INPUT) != 0U) {
+		if ((flags & GPIO_PULL_UP) && ((*mode_cache & BIT(pin)) == 0)) {
+			mode = *mode_cache | BIT(pin);
+			need_update = true;
+		} else if ((flags & GPIO_PULL_DOWN) && ((*mode_cache & BIT(pin)) != 0)) {
+			mode = *mode_cache & ~BIT(pin);
+			need_update = true;
+		}
+	}
+	if (need_update) {
+		ret = write_port_regs(dev, REG_GPIO_PUPD, mode);
+		if (ret != 0) {
+			goto out;
+		}
+		*mode_cache = mode;
+	}
+
+out:
+	return ret;
+}
+
+static int mfxstm32l152_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
+{
+	struct mfxstm32l152_drv_data *const drvdata =
+		(struct mfxstm32l152_drv_data *const)dev->data;
+	int ret;
+
+	/* No support for disconnected pin, single ended and simultaneous input / output */
+	if ((flags & (GPIO_INPUT | GPIO_OUTPUT)) == GPIO_DISCONNECTED ||
+	    (flags & GPIO_SINGLE_ENDED) != 0 ||
+	    (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0))) {
+		return -ENOTSUP;
+	}
+
+	/* Can't do I2C bus operations from an ISR */
+	if (k_is_in_isr()) {
+		return -EWOULDBLOCK;
+	}
+
+	k_sem_take(&drvdata->lock, K_FOREVER);
+
+	ret = set_pin_dir_mode(dev, pin, flags);
+	if (ret != 0) {
+		LOG_ERR("%s: error setting pin direction and mode (%d)", dev->name, ret);
+	}
+
+	k_sem_give(&drvdata->lock);
+
+	return ret;
+}
+
+static int mfxstm32l152_port_get_raw(const struct device *dev, uint32_t *value)
+{
+	struct mfxstm32l152_drv_data *const drvdata =
+		(struct mfxstm32l152_drv_data *const)dev->data;
+	uint32_t reg_value;
+	int ret;
+
+	/* Can't do I2C bus operations from an ISR */
+	if (k_is_in_isr()) {
+		return -EWOULDBLOCK;
+	}
+
+	k_sem_take(&drvdata->lock, K_FOREVER);
+	ret = read_port_regs(dev, REG_GPIO_STATE, &reg_value);
+	k_sem_give(&drvdata->lock);
+
+	if (ret == 0) {
+		*value = reg_value;
+	}
+
+	return ret;
+}
+
+static int mfxstm32l152_port_set_bits_raw(const struct device *dev, uint32_t mask)
+{
+	struct mfxstm32l152_drv_data *const drvdata =
+		(struct mfxstm32l152_drv_data *const)dev->data;
+	int ret;
+
+	/* Can't do I2C bus operations from an ISR */
+	if (k_is_in_isr()) {
+		return -EWOULDBLOCK;
+	}
+
+	k_sem_take(&drvdata->lock, K_FOREVER);
+	ret = write_port_regs(dev, REG_GPIO_SET, mask);
+	k_sem_give(&drvdata->lock);
+
+	return ret;
+}
+
+static int mfxstm32l152_port_clear_bits_raw(const struct device *dev, uint32_t mask)
+{
+	struct mfxstm32l152_drv_data *const drvdata =
+		(struct mfxstm32l152_drv_data *const)dev->data;
+	int ret;
+
+	/* Can't do I2C bus operations from an ISR */
+	if (k_is_in_isr()) {
+		return -EWOULDBLOCK;
+	}
+
+	k_sem_take(&drvdata->lock, K_FOREVER);
+	ret = write_port_regs(dev, REG_GPIO_CLR, mask);
+	k_sem_give(&drvdata->lock);
+
+	return ret;
+}
+
+static int mfxstm32l152_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
+						enum gpio_int_mode mode, enum gpio_int_trig trig)
+{
+	struct mfxstm32l152_drv_data *drv_data = dev->data;
+	uint32_t irq_event, irq_type;
+	int ret;
+
+	k_sem_take(&drv_data->lock, K_FOREVER);
+
+	if (mode == GPIO_INT_MODE_DISABLED) {
+		drv_data->pins_state.irq_enabled &= ~BIT(pin);
+		ret = write_port_regs(dev, REG_GPIO_IRQ_EN, drv_data->pins_state.irq_enabled);
+		if (ret != 0) {
+			k_sem_give(&drv_data->lock);
+			return ret;
+		}
+
+		if (drv_data->pins_state.irq_enabled == 0) {
+			ret = write_reg(dev, REG_SYS_IRQ_EN, 0);
+			k_sem_give(&drv_data->lock);
+			return ret;
+		}
+
+		k_sem_give(&drv_data->lock);
+
+		return ret;
+	}
+
+	/* Set mode (EDGE / LEVEL */
+	ret = read_port_regs(dev, REG_GPIO_IRQ_EVT, &irq_event);
+	if (ret != 0) {
+		k_sem_give(&drv_data->lock);
+		return ret;
+	}
+
+	if (mode == GPIO_INT_MODE_EDGE) {
+		irq_event |= BIT(pin);
+	} else {
+		irq_event &= ~BIT(pin);
+	}
+
+	ret = write_port_regs(dev, REG_GPIO_IRQ_EVT, irq_event);
+	if (ret != 0) {
+		k_sem_give(&drv_data->lock);
+		return ret;
+	}
+
+	/* Set High / Rising or Low / Falling */
+	ret = read_port_regs(dev, REG_GPIO_IRQ_TYPE, &irq_type);
+	if (ret != 0) {
+		k_sem_give(&drv_data->lock);
+		return ret;
+	}
+
+	/* We cannot handle BOTH edge so if BOTH is asked, we set it as HIGH */
+	if (trig == GPIO_INT_TRIG_HIGH || trig == GPIO_INT_TRIG_BOTH) {
+		irq_type |= BIT(pin);
+	} else {
+		irq_type &= ~BIT(pin);
+	}
+
+	ret = write_port_regs(dev, REG_GPIO_IRQ_TYPE, irq_type);
+	if (ret != 0) {
+		k_sem_give(&drv_data->lock);
+		return ret;
+	}
+
+	/* Enable the interrupt */
+	drv_data->pins_state.irq_enabled |= BIT(pin);
+	ret = write_port_regs(dev, REG_GPIO_IRQ_EN, drv_data->pins_state.irq_enabled);
+	if (ret != 0) {
+		k_sem_give(&drv_data->lock);
+		return ret;
+	}
+
+	ret = write_reg(dev, REG_SYS_IRQ_EN, 1);
+
+	k_sem_give(&drv_data->lock);
+
+	return ret;
+}
+
+static int mfxstm32l152_manage_callback(const struct device *dev, struct gpio_callback *callback,
+					bool set)
+{
+	struct mfxstm32l152_drv_data *drv_data = dev->data;
+
+	return gpio_manage_callback(&drv_data->callbacks, callback, set);
+}
+
+static int mfxstm32l152_init(const struct device *dev)
+{
+	struct mfxstm32l152_drv_data *const drvdata =
+		(struct mfxstm32l152_drv_data *const)dev->data;
+	const struct mfxstm32l152_drv_cfg *drv_cfg = dev->config;
+	uint8_t chip_id, int_pin = 0;
+	int ret;
+
+	if (!device_is_ready(drv_cfg->i2c_spec.bus)) {
+		LOG_ERR("I2C device not found");
+		return -ENODEV;
+	}
+
+	k_sem_init(&drvdata->lock, 1, 1);
+
+	ret = read_reg(dev, REG_ID, &chip_id);
+	if (ret != 0) {
+		LOG_ERR("%s: Unable to read Chip ID", dev->name);
+		return ret;
+	}
+
+	if (chip_id != MFXSTM32L152_ID) {
+		LOG_ERR("%s: Invalid Chip ID", dev->name);
+		return -EINVAL;
+	}
+
+	ret = read_port_regs(dev, REG_GPIO_DIR, &drvdata->pins_state.direction);
+	if (ret != 0) {
+		LOG_ERR("%s: Unable to read initial directions", dev->name);
+		return ret;
+	}
+
+	ret = read_port_regs(dev, REG_GPIO_PUPD, &drvdata->pins_state.pupd);
+	if (ret != 0) {
+		LOG_ERR("%s: Unable to read initial directions", dev->name);
+		return ret;
+	}
+
+	ret = write_reg(dev, REG_SYS_CTRL, 0x01);
+	if (ret != 0) {
+		LOG_ERR("%s: Failed to enable GPIO", dev->name);
+		return ret;
+	}
+
+	/* If the INT line is available, configure the callback for it. */
+	if (drv_cfg->int_gpio.port) {
+		if (!gpio_is_ready_dt(&drv_cfg->int_gpio)) {
+			LOG_ERR("Cannot get pointer to gpio interrupt device %s init failed",
+				dev->name);
+			return -EINVAL;
+		}
+
+		drvdata->dev = dev;
+
+		k_work_init(&drvdata->work, mfxstm32l152_work_handler);
+
+		ret = gpio_pin_configure_dt(&drv_cfg->int_gpio, GPIO_INPUT);
+		if (ret != 0) {
+			LOG_ERR("%s init failed: %d", dev->name, ret);
+			return ret;
+		}
+
+		ret = gpio_pin_interrupt_configure_dt(&drv_cfg->int_gpio, GPIO_INT_EDGE_TO_ACTIVE);
+		if (ret != 0) {
+			LOG_ERR("%s init failed: %d", dev->name, ret);
+			return ret;
+		}
+
+		gpio_init_callback(&drvdata->int_gpio_cb, mfxstm32l152_int_gpio_handler,
+				   BIT(drv_cfg->int_gpio.pin));
+
+		ret = gpio_add_callback(drv_cfg->int_gpio.port, &drvdata->int_gpio_cb);
+		if (ret != 0) {
+			LOG_ERR("%s init failed: %d", dev->name, ret);
+			return ret;
+		}
+
+		/* Configure the INT_OUT pin based on int_gpio dt_flags */
+		if ((drv_cfg->int_gpio.dt_flags & GPIO_OPEN_DRAIN) != 0) {
+			int_pin |= SYS_IRQ_MODE_OPEN_DRAIN;
+		} else {
+			int_pin |= SYS_IRQ_MODE_PUSH_PULL;
+		}
+		if ((drv_cfg->int_gpio.dt_flags & GPIO_ACTIVE_LOW) != 0) {
+			int_pin |= SYS_IRQ_MODE_POL_LOW;
+		} else {
+			int_pin |= SYS_IRQ_MODE_POL_HIGH;
+		}
+
+		ret = write_reg(dev, REG_SYS_IRQ_MODE, int_pin);
+	}
+
+	return ret;
+}
+
+static DEVICE_API(gpio, mfxstm32l152_drv_api) = {
+	.pin_configure = mfxstm32l152_configure,
+	.port_get_raw = mfxstm32l152_port_get_raw,
+	.port_set_masked_raw = NULL,
+	.port_set_bits_raw = mfxstm32l152_port_set_bits_raw,
+	.port_clear_bits_raw = mfxstm32l152_port_clear_bits_raw,
+	.port_toggle_bits = NULL,
+	.pin_interrupt_configure = mfxstm32l152_pin_interrupt_configure,
+	.manage_callback = mfxstm32l152_manage_callback,
+};
+
+#define MFXSTM32L152_INIT(inst)                                                                    \
+	static struct mfxstm32l152_drv_cfg mfxstm32l152_##inst##_config = {                        \
+		.common = {.port_pin_mask = 0x0fff},                                               \
+		.i2c_spec = I2C_DT_SPEC_INST_GET(inst),                                            \
+		.int_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, {0}),                        \
+	};                                                                                         \
+                                                                                                   \
+	static struct mfxstm32l152_drv_data mfxstm32l152_##inst##_drv_data;                        \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(inst, mfxstm32l152_init, NULL, &mfxstm32l152_##inst##_drv_data,      \
+			      &mfxstm32l152_##inst##_config, POST_KERNEL,                          \
+			      CONFIG_GPIO_MFXSTM32L152_INIT_PRIORITY, &mfxstm32l152_drv_api);
+
+DT_INST_FOREACH_STATUS_OKAY(MFXSTM32L152_INIT)
diff --git a/drivers/gpio/gpio_mmio32.c b/drivers/gpio/gpio_mmio32.c
index b88fac97a8e..bcc6dd258f5 100644
--- a/drivers/gpio/gpio_mmio32.c
+++ b/drivers/gpio/gpio_mmio32.c
@@ -26,27 +26,50 @@
  * gpio_port_write.
  */
 
-#include <zephyr/drivers/gpio/gpio_mmio32.h>
+#define DT_DRV_COMPAT arm_mmio32_gpio
+
 #include <zephyr/irq.h>
 #include <errno.h>
 
-static int gpio_mmio32_config(const struct device *dev,
-			      gpio_pin_t pin, gpio_flags_t flags)
+#include <zephyr/drivers/gpio/gpio_utils.h>
+
+struct gpio_mmio32_config {
+	/* gpio_driver_config needs to be first */
+	struct gpio_driver_config common;
+	volatile uint32_t *reg;
+	bool is_input;
+};
+
+struct gpio_mmio32_context {
+	/* gpio_driver_data needs to be first */
+	struct gpio_driver_data common;
+	const struct gpio_mmio32_config *config;
+};
+
+int gpio_mmio32_init(const struct device *dev);
+
+static int gpio_mmio32_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
 {
 	struct gpio_mmio32_context *context = dev->data;
 	const struct gpio_mmio32_config *config = context->config;
 
-	if ((config->mask & (1 << pin)) == 0) {
+	if ((config->common.port_pin_mask & (1 << pin)) == 0) {
 		return -EINVAL; /* Pin not in our validity mask */
 	}
 
-	if (flags & ~(GPIO_INPUT | GPIO_OUTPUT |
-		      GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH |
+	if (flags & ~(GPIO_INPUT | GPIO_OUTPUT | GPIO_OUTPUT_INIT_LOW | GPIO_OUTPUT_INIT_HIGH |
 		      GPIO_ACTIVE_LOW)) {
 		/* We ignore direction and fake polarity, rest is unsupported */
 		return -ENOTSUP;
 	}
 
+	if (config->is_input && ((flags & GPIO_OUTPUT) != 0)) {
+		return -ENOTSUP;
+	}
+	if (!config->is_input && ((flags & GPIO_INPUT) != 0)) {
+		return -ENOTSUP;
+	}
+
 	if ((flags & GPIO_OUTPUT) != 0) {
 		unsigned int key;
 		volatile uint32_t *reg = config->reg;
@@ -55,7 +78,7 @@ static int gpio_mmio32_config(const struct device *dev,
 		if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
 			*reg = (*reg | (1 << pin));
 		} else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
-			*reg = (*reg & (config->mask & ~(1 << pin)));
+			*reg = (*reg & (config->common.port_pin_mask & ~(1 << pin)));
 		}
 		irq_unlock(key);
 	}
@@ -68,21 +91,19 @@ static int gpio_mmio32_port_get_raw(const struct device *dev, uint32_t *value)
 	struct gpio_mmio32_context *context = dev->data;
 	const struct gpio_mmio32_config *config = context->config;
 
-	*value = *config->reg & config->mask;
+	*value = *config->reg & config->common.port_pin_mask;
 
 	return 0;
 }
 
-static int gpio_mmio32_port_set_masked_raw(const struct device *dev,
-					   uint32_t mask,
-					   uint32_t value)
+static int gpio_mmio32_port_set_masked_raw(const struct device *dev, uint32_t mask, uint32_t value)
 {
 	struct gpio_mmio32_context *context = dev->data;
 	const struct gpio_mmio32_config *config = context->config;
 	volatile uint32_t *reg = config->reg;
 	unsigned int key;
 
-	mask &= config->mask;
+	mask &= config->common.port_pin_mask;
 	value &= mask;
 
 	/* Update pin state atomically */
@@ -93,15 +114,14 @@ static int gpio_mmio32_port_set_masked_raw(const struct device *dev,
 	return 0;
 }
 
-static int gpio_mmio32_port_set_bits_raw(const struct device *dev,
-					 uint32_t mask)
+static int gpio_mmio32_port_set_bits_raw(const struct device *dev, uint32_t mask)
 {
 	struct gpio_mmio32_context *context = dev->data;
 	const struct gpio_mmio32_config *config = context->config;
 	volatile uint32_t *reg = config->reg;
 	unsigned int key;
 
-	mask &= config->mask;
+	mask &= config->common.port_pin_mask;
 
 	/* Update pin state atomically */
 	key = irq_lock();
@@ -111,15 +131,14 @@ static int gpio_mmio32_port_set_bits_raw(const struct device *dev,
 	return 0;
 }
 
-static int gpio_mmio32_port_clear_bits_raw(const struct device *dev,
-					   uint32_t mask)
+static int gpio_mmio32_port_clear_bits_raw(const struct device *dev, uint32_t mask)
 {
 	struct gpio_mmio32_context *context = dev->data;
 	const struct gpio_mmio32_config *config = context->config;
 	volatile uint32_t *reg = config->reg;
 	unsigned int key;
 
-	mask &= config->mask;
+	mask &= config->common.port_pin_mask;
 
 	/* Update pin state atomically */
 	key = irq_lock();
@@ -129,15 +148,14 @@ static int gpio_mmio32_port_clear_bits_raw(const struct device *dev,
 	return 0;
 }
 
-static int gpio_mmio32_port_toggle_bits(const struct device *dev,
-					uint32_t mask)
+static int gpio_mmio32_port_toggle_bits(const struct device *dev, uint32_t mask)
 {
 	struct gpio_mmio32_context *context = dev->data;
 	const struct gpio_mmio32_config *config = context->config;
 	volatile uint32_t *reg = config->reg;
 	unsigned int key;
 
-	mask &= config->mask;
+	mask &= config->common.port_pin_mask;
 
 	/* Update pin state atomically */
 	key = irq_lock();
@@ -147,6 +165,14 @@ static int gpio_mmio32_port_toggle_bits(const struct device *dev,
 	return 0;
 }
 
+int gpio_mmio32_pin_interrupt_configure(const struct device *port,
+					gpio_pin_t pin,
+					enum gpio_int_mode mode,
+					enum gpio_int_trig trig)
+{
+	return -ENOTSUP;
+}
+
 DEVICE_API(gpio, gpio_mmio32_api) = {
 	.pin_configure = gpio_mmio32_config,
 	.port_get_raw = gpio_mmio32_port_get_raw,
@@ -154,6 +180,7 @@ DEVICE_API(gpio, gpio_mmio32_api) = {
 	.port_set_bits_raw = gpio_mmio32_port_set_bits_raw,
 	.port_clear_bits_raw = gpio_mmio32_port_clear_bits_raw,
 	.port_toggle_bits = gpio_mmio32_port_toggle_bits,
+	.pin_interrupt_configure = gpio_mmio32_pin_interrupt_configure,
 };
 
 int gpio_mmio32_init(const struct device *dev)
@@ -165,3 +192,21 @@ int gpio_mmio32_init(const struct device *dev)
 
 	return 0;
 }
+
+#define MMIO32_GPIO_DEVICE(n)                                                                      \
+	static struct gpio_mmio32_context gpio_mmio32_##n##_ctx;                                   \
+                                                                                                   \
+	static const struct gpio_mmio32_config gpio_mmio32_##n##_cfg = {                           \
+		.common =                                                                          \
+			{                                                                          \
+				.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),               \
+			},                                                                         \
+		.reg = (volatile uint32_t *)DT_INST_REG_ADDR(n),                                   \
+		.is_input = DT_INST_PROP(n, direction_input),                                      \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, gpio_mmio32_init, NULL, &gpio_mmio32_##n##_ctx,                   \
+			      &gpio_mmio32_##n##_cfg, PRE_KERNEL_1,                                \
+			      CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &gpio_mmio32_api);
+
+DT_INST_FOREACH_STATUS_OKAY(MMIO32_GPIO_DEVICE)
diff --git a/drivers/gpio/gpio_nct38xx_alert.c b/drivers/gpio/gpio_nct38xx_alert.c
index eb52339364a..d1f3cca0d85 100644
--- a/drivers/gpio/gpio_nct38xx_alert.c
+++ b/drivers/gpio/gpio_nct38xx_alert.c
@@ -157,12 +157,9 @@ static int nct38xx_alert_init(const struct device *dev)
 /* NCT38XX alert driver must be initialized after NCT38XX GPIO driver */
 BUILD_ASSERT(CONFIG_GPIO_NCT38XX_ALERT_INIT_PRIORITY > CONFIG_GPIO_NCT38XX_INIT_PRIORITY);
 
-#define NCT38XX_DEV_AND_COMMA(node_id, prop, idx)                                                  \
-	DEVICE_DT_GET(DT_PHANDLE_BY_IDX(node_id, prop, idx)),
-
 #define NCT38XX_ALERT_DEVICE_INSTANCE(inst)                                                        \
 	const struct device *nct38xx_dev_##inst[] = {                                              \
-		DT_INST_FOREACH_PROP_ELEM(inst, nct38xx_dev, NCT38XX_DEV_AND_COMMA)};              \
+		DT_INST_FOREACH_PROP_ELEM_SEP(inst, nct38xx_dev, DEVICE_DT_GET_BY_IDX, (,))};      \
 	static struct nct38xx_mfd nct38xx_mfd_##inst[DT_INST_PROP_LEN(inst, nct38xx_dev)];         \
 	static const struct nct38xx_alert_config nct38xx_alert_cfg_##inst = {                      \
 		.irq_gpio = GPIO_DT_SPEC_INST_GET(inst, irq_gpios),                                \
diff --git a/drivers/gpio/gpio_neorv32.c b/drivers/gpio/gpio_neorv32.c
index 51dc3ecd9ed..90546ef1abe 100644
--- a/drivers/gpio/gpio_neorv32.c
+++ b/drivers/gpio/gpio_neorv32.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
+ * Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,6 +20,10 @@ LOG_MODULE_REGISTER(gpio_neorv32, CONFIG_GPIO_LOG_LEVEL);
 
 #include <zephyr/drivers/gpio/gpio_utils.h>
 
+/* Register offsets */
+#define NEORV32_GPIO_PORT_IN  0x00
+#define NEORV32_GPIO_PORT_OUT 0x04
+
 /* Maximum number of GPIOs supported */
 #define MAX_GPIOS 32
 
@@ -27,8 +31,7 @@ struct neorv32_gpio_config {
 	/* gpio_driver_config needs to be first */
 	struct gpio_driver_config common;
 	const struct device *syscon;
-	mm_reg_t input;
-	mm_reg_t output;
+	mm_reg_t base;
 };
 
 struct neorv32_gpio_data {
@@ -42,14 +45,14 @@ static inline uint32_t neorv32_gpio_read(const struct device *dev)
 {
 	const struct neorv32_gpio_config *config = dev->config;
 
-	return sys_read32(config->input);
+	return sys_read32(config->base + NEORV32_GPIO_PORT_IN);
 }
 
 static inline void neorv32_gpio_write(const struct device *dev, uint32_t val)
 {
 	const struct neorv32_gpio_config *config = dev->config;
 
-	sys_write32(val, config->output);
+	sys_write32(val, config->base + NEORV32_GPIO_PORT_OUT);
 }
 
 static int neorv32_gpio_pin_configure(const struct device *dev, gpio_pin_t pin,
@@ -179,13 +182,13 @@ static int neorv32_gpio_init(const struct device *dev)
 		return -EINVAL;
 	}
 
-	err = syscon_read_reg(config->syscon, NEORV32_SYSINFO_FEATURES, &features);
+	err = syscon_read_reg(config->syscon, NEORV32_SYSINFO_SOC, &features);
 	if (err < 0) {
 		LOG_ERR("failed to determine implemented features (err %d)", err);
 		return -EIO;
 	}
 
-	if ((features & NEORV32_SYSINFO_FEATURES_IO_GPIO) == 0) {
+	if ((features & NEORV32_SYSINFO_SOC_IO_GPIO) == 0) {
 		LOG_ERR("neorv32 gpio not supported");
 		return -ENODEV;
 	}
@@ -216,8 +219,7 @@ static DEVICE_API(gpio, neorv32_gpio_driver_api) = {
 			.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n) \
 		},							\
 		.syscon = DEVICE_DT_GET(DT_INST_PHANDLE(n, syscon)),	\
-		.input = DT_INST_REG_ADDR_BY_NAME(n, input),		\
-		.output = DT_INST_REG_ADDR_BY_NAME(n, output),		\
+		.base = DT_INST_REG_ADDR(n),				\
 	};								\
 									\
 	DEVICE_DT_INST_DEFINE(n,					\
diff --git a/drivers/gpio/gpio_npm2100.c b/drivers/gpio/gpio_npm2100.c
index da7b649e29a..9fb15d19873 100644
--- a/drivers/gpio/gpio_npm2100.c
+++ b/drivers/gpio/gpio_npm2100.c
@@ -62,8 +62,8 @@ static int gpio_npm2100_port_set_masked_raw(const struct device *dev, gpio_port_
 
 	for (size_t idx = 0; idx < NPM2100_GPIO_PINS; idx++) {
 		if ((mask & BIT(idx)) != 0U) {
-			i2c_reg_write_byte_dt(&config->i2c, NPM2100_GPIO_OUTPUT + idx,
-					      !!(value & BIT(idx)));
+			ret = i2c_reg_write_byte_dt(&config->i2c, NPM2100_GPIO_OUTPUT + idx,
+						    !!(value & BIT(idx)));
 			if (ret != 0U) {
 				return ret;
 			}
diff --git a/drivers/gpio/gpio_nrfx.c b/drivers/gpio/gpio_nrfx.c
index e833017e7d5..3d2c1a12f46 100644
--- a/drivers/gpio/gpio_nrfx.c
+++ b/drivers/gpio/gpio_nrfx.c
@@ -241,6 +241,73 @@ static int gpio_nrfx_pin_configure(const struct device *port, gpio_pin_t pin,
 	return ret;
 }
 
+#ifdef CONFIG_GPIO_GET_CONFIG
+static int gpio_nrfx_pin_get_config(const struct device *port, gpio_pin_t pin,
+				    gpio_flags_t *flags)
+{
+	const struct gpio_nrfx_cfg *cfg = get_port_cfg(port);
+	nrfx_gpiote_pin_t abs_pin = NRF_GPIO_PIN_MAP(cfg->port_num, pin);
+
+	*flags = 0U;
+
+	nrf_gpio_pin_dir_t dir = nrf_gpio_pin_dir_get(abs_pin);
+
+	if (dir == NRF_GPIO_PIN_DIR_OUTPUT) {
+		*flags |= GPIO_OUTPUT;
+	}
+
+	nrf_gpio_pin_input_t input = nrf_gpio_pin_input_get(abs_pin);
+
+	if (input == NRF_GPIO_PIN_INPUT_CONNECT) {
+		*flags |= GPIO_INPUT;
+	}
+
+	nrf_gpio_pin_pull_t pull = nrf_gpio_pin_pull_get(abs_pin);
+
+	switch (pull) {
+	case NRF_GPIO_PIN_PULLUP:
+		*flags |= GPIO_PULL_UP;
+	case NRF_GPIO_PIN_PULLDOWN:
+		*flags |= GPIO_PULL_DOWN;
+	default:
+		break;
+	}
+
+	nrf_gpio_pin_drive_t drive = nrf_gpio_pin_drive_get(abs_pin);
+
+	switch (drive) {
+	case NRF_GPIO_PIN_S0S1:
+		*flags |= NRF_GPIO_DRIVE_S0S1;
+		break;
+	case NRF_GPIO_PIN_S0H1:
+		*flags |= NRF_GPIO_DRIVE_S0H1;
+		break;
+	case NRF_GPIO_PIN_H0S1:
+		*flags |= NRF_GPIO_DRIVE_H0S1;
+		break;
+	case NRF_GPIO_PIN_H0H1:
+		*flags |= NRF_GPIO_DRIVE_H0H1;
+		break;
+	case NRF_GPIO_PIN_S0D1:
+		*flags |= NRF_GPIO_DRIVE_S0 | GPIO_OPEN_DRAIN;
+		break;
+	case NRF_GPIO_PIN_H0D1:
+		*flags |= NRF_GPIO_DRIVE_H0 | GPIO_OPEN_DRAIN;
+		break;
+	case NRF_GPIO_PIN_D0S1:
+		*flags |= NRF_GPIO_DRIVE_S1 | GPIO_OPEN_SOURCE;
+		break;
+	case NRF_GPIO_PIN_D0H1:
+		*flags |= NRF_GPIO_DRIVE_H1 | GPIO_OPEN_SOURCE;
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+#endif
+
 static int gpio_nrfx_port_get_raw(const struct device *port,
 				  gpio_port_value_t *value)
 {
@@ -520,6 +587,9 @@ static DEVICE_API(gpio, gpio_nrfx_drv_api_funcs) = {
 #ifdef CONFIG_GPIO_GET_DIRECTION
 	.port_get_direction = gpio_nrfx_port_get_direction,
 #endif
+#ifdef CONFIG_GPIO_GET_CONFIG
+	.pin_get_config = gpio_nrfx_pin_get_config,
+#endif
 };
 
 #define GPIOTE_PHANDLE(id) DT_INST_PHANDLE(id, gpiote_instance)
diff --git a/drivers/gpio/gpio_pca6416.c b/drivers/gpio/gpio_pca6416.c
new file mode 100644
index 00000000000..a0d9b083fff
--- /dev/null
+++ b/drivers/gpio/gpio_pca6416.c
@@ -0,0 +1,492 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_pca6416
+
+#include <errno.h>
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(pca6416, CONFIG_GPIO_LOG_LEVEL);
+
+#include <zephyr/drivers/gpio/gpio_utils.h>
+
+/* PCA6416 Register addresses */
+#define PCA6416_INPUT_PORT0		0x00
+#define PCA6416_INPUT_PORT1		0x01
+#define PCA6416_OUTPUT_PORT0		0x02
+#define PCA6416_OUTPUT_PORT1		0x03
+#define PCA6416_POL_INV_PORT0		0x04
+#define PCA6416_POL_INV_PORT1		0x05
+#define PCA6416_CONFIG_PORT0		0x06
+#define PCA6416_CONFIG_PORT1		0x07
+
+/* Number of pins supported by the device */
+#define NUM_PINS 16
+
+/* Max to select all pins supported on the device. */
+#define ALL_PINS ((uint16_t)BIT_MASK(NUM_PINS))
+
+/** Cache of the output configuration and data of the pins. */
+struct pca6416_pin_state {
+	uint16_t dir;
+	uint16_t input;
+	uint16_t output;
+};
+
+struct pca6416_irq_state {
+	uint16_t rising;
+	uint16_t falling;
+};
+
+/** Runtime driver data */
+struct pca6416_drv_data {
+	/* gpio_driver_data needs to be first */
+	struct gpio_driver_data common;
+	struct pca6416_pin_state pin_state;
+	struct k_sem lock;
+	struct gpio_callback gpio_cb;
+	struct k_work work;
+	struct pca6416_irq_state irq_state;
+	const struct device *dev;
+	/* user ISR cb */
+	sys_slist_t cb;
+};
+
+/** Configuration data */
+struct pca6416_config {
+	/* gpio_driver_config needs to be first */
+	struct gpio_driver_config common;
+	struct i2c_dt_spec i2c;
+	const struct gpio_dt_spec gpio_int;
+	bool interrupt_enabled;
+};
+
+/**
+ * @brief Gets the state of input pins of the PCA6416 I/O Port and
+ * stores in driver data struct.
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ *
+ * @retval 0 If successful.
+ * @retval Negative value for error code.
+ */
+static int update_input(const struct device *dev)
+{
+	const struct pca6416_config *cfg = dev->config;
+	struct pca6416_drv_data *drv_data = dev->data;
+	uint16_t input_states;
+	int rc = 0;
+
+	rc = i2c_burst_read_dt(&cfg->i2c, PCA6416_INPUT_PORT0, (uint8_t *)&input_states, 2);
+	if (rc == 0) {
+		drv_data->pin_state.input = input_states;
+	}
+	return rc;
+}
+
+/**
+ * @brief Handles interrupt triggered by the interrupt pin of PCA6416 I/O Port.
+ *
+ * If interrupt-gpios is configured in device tree then this will be triggered each
+ * time a gpio configured as an input changes state. The gpio input states are
+ * read in this function which clears the interrupt.
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ */
+static void gpio_pca6416_handle_interrupt(const struct device *dev)
+{
+	struct pca6416_drv_data *drv_data = dev->data;
+	struct pca6416_irq_state *irq_state = &drv_data->irq_state;
+	int rc;
+	uint16_t previous_state;
+	uint16_t current_state;
+	uint16_t transitioned_pins;
+	uint16_t interrupt_status = 0;
+
+	k_sem_take(&drv_data->lock, K_FOREVER);
+
+	/* Any interrupts enabled? */
+	if (!irq_state->rising && !irq_state->falling) {
+		rc = -EINVAL;
+		goto out;
+	}
+
+	/* Store previous input state then read new value */
+	previous_state = drv_data->pin_state.input;
+	rc = update_input(dev);
+	if (rc != 0) {
+		goto out;
+	}
+
+	/* Find out which input pins have changed state */
+	current_state = drv_data->pin_state.input;
+	transitioned_pins = previous_state ^ current_state;
+
+	/* Mask gpio transactions with rising/falling edge interrupt config */
+	interrupt_status = (irq_state->rising & transitioned_pins &
+			  current_state);
+	interrupt_status |= (irq_state->falling & transitioned_pins &
+			   previous_state);
+
+out:
+	k_sem_give(&drv_data->lock);
+
+	if ((rc == 0) && (interrupt_status)) {
+		gpio_fire_callbacks(&drv_data->cb, dev, interrupt_status);
+	}
+}
+
+/**
+ * @brief Work handler for PCA6416 interrupt
+ *
+ * @param work Work struct that contains pointer to interrupt handler function
+ */
+static void gpio_pca6416_work_handler(struct k_work *work)
+{
+	struct pca6416_drv_data *drv_data =
+		CONTAINER_OF(work, struct pca6416_drv_data, work);
+
+	gpio_pca6416_handle_interrupt(drv_data->dev);
+}
+
+/**
+ * @brief ISR for interrupt pin of PCA6416
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @param gpio_cb Pointer to callback function struct
+ * @param pins Bitmask of pins that triggered interrupt
+ */
+static void gpio_pca6416_init_cb(const struct device *dev,
+				 struct gpio_callback *gpio_cb, uint32_t pins)
+{
+	struct pca6416_drv_data *drv_data =
+		CONTAINER_OF(gpio_cb, struct pca6416_drv_data, gpio_cb);
+	ARG_UNUSED(pins);
+
+	k_work_submit(&drv_data->work);
+}
+
+static int gpio_pca6416_config(const struct device *dev, gpio_pin_t pin,
+			       gpio_flags_t flags)
+{
+	const struct pca6416_config *cfg = dev->config;
+	struct pca6416_drv_data *drv_data = dev->data;
+	struct pca6416_pin_state *pins = &drv_data->pin_state;
+	int rc = 0;
+	bool data_first = false;
+
+	/* Can't do I2C bus operations from an ISR */
+	if (k_is_in_isr()) {
+		return -EWOULDBLOCK;
+	}
+
+	/* Single Ended lines (Open drain and open source) not supported */
+	if ((flags & GPIO_SINGLE_ENDED) != 0) {
+		return -ENOTSUP;
+	}
+
+	/* The PCA6416 has no internal pull up support */
+	if (((flags & GPIO_PULL_UP) != 0) || ((flags & GPIO_PULL_DOWN) != 0)) {
+		return -ENOTSUP;
+	}
+
+	/* Simultaneous input & output mode not supported */
+	if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) {
+		return -ENOTSUP;
+	}
+
+	k_sem_take(&drv_data->lock, K_FOREVER);
+
+	/* Ensure either Output or Input is specified */
+	if ((flags & GPIO_OUTPUT) != 0) {
+		pins->dir &= ~BIT(pin);
+		if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
+			pins->output &= ~BIT(pin);
+			data_first = true;
+		} else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
+			pins->output |= BIT(pin);
+			data_first = true;
+		}
+	} else if ((flags & GPIO_INPUT) != 0) {
+		pins->dir |= BIT(pin);
+	} else {
+		rc = -ENOTSUP;
+		goto out;
+	}
+
+	/* Set output values */
+	if (data_first) {
+		rc = i2c_burst_write_dt(&cfg->i2c, PCA6416_OUTPUT_PORT0,
+			(uint8_t *)&pins->output, 2);
+	}
+
+	if (rc == 0) {
+		/* Set pin directions */
+		rc = i2c_burst_write_dt(&cfg->i2c, PCA6416_CONFIG_PORT0,
+			(uint8_t *)&pins->dir, 2);
+	}
+
+	if (rc == 0) {
+		/* Refresh input status */
+		rc = update_input(dev);
+	}
+
+out:
+	k_sem_give(&drv_data->lock);
+	return rc;
+}
+
+static int gpio_pca6416_port_read(const struct device *dev,
+				 gpio_port_value_t *value)
+{
+	const struct pca6416_config *cfg = dev->config;
+	struct pca6416_drv_data *drv_data = dev->data;
+	uint16_t input_pin_data;
+	int rc = 0;
+
+	/* Can't do I2C bus operations from an ISR */
+	if (k_is_in_isr()) {
+		return -EWOULDBLOCK;
+	}
+
+	k_sem_take(&drv_data->lock, K_FOREVER);
+
+	/* Read Input Register */
+	rc = i2c_burst_read_dt(&cfg->i2c, PCA6416_INPUT_PORT0, (uint8_t *)&input_pin_data, 2);
+
+	LOG_DBG("read %x got %d", input_pin_data, rc);
+
+	if (rc == 0) {
+		drv_data->pin_state.input = input_pin_data;
+		*value = (gpio_port_value_t)(drv_data->pin_state.input);
+	}
+
+	k_sem_give(&drv_data->lock);
+	return rc;
+}
+
+static int gpio_pca6416_port_write(const struct device *dev,
+				   gpio_port_pins_t mask,
+				   gpio_port_value_t value,
+				   gpio_port_value_t toggle)
+{
+	const struct pca6416_config *cfg = dev->config;
+	struct pca6416_drv_data *drv_data = dev->data;
+	uint16_t *outp = &drv_data->pin_state.output;
+	int rc;
+	uint16_t orig_out;
+	uint16_t out;
+
+	/* Can't do I2C bus operations from an ISR */
+	if (k_is_in_isr()) {
+		return -EWOULDBLOCK;
+	}
+
+	k_sem_take(&drv_data->lock, K_FOREVER);
+
+	orig_out = *outp;
+	out = ((orig_out & ~mask) | (value & mask)) ^ toggle;
+
+	rc = i2c_burst_write_dt(&cfg->i2c, PCA6416_OUTPUT_PORT0, (uint8_t *)&out, 2);
+
+	if (rc == 0) {
+		*outp = out;
+	}
+
+	k_sem_give(&drv_data->lock);
+
+	LOG_DBG("write %x msk %08x val %08x => %x: %d", orig_out, mask,
+		value, out, rc);
+
+	return rc;
+}
+
+static int gpio_pca6416_port_set_masked(const struct device *dev,
+					gpio_port_pins_t mask,
+					gpio_port_value_t value)
+{
+	return gpio_pca6416_port_write(dev, mask, value, 0);
+}
+
+static int gpio_pca6416_port_set_bits(const struct device *dev,
+				      gpio_port_pins_t pins)
+{
+	return gpio_pca6416_port_write(dev, pins, pins, 0);
+}
+
+static int gpio_pca6416_port_clear_bits(const struct device *dev,
+					gpio_port_pins_t pins)
+{
+	return gpio_pca6416_port_write(dev, pins, 0, 0);
+}
+
+static int gpio_pca6416_port_toggle_bits(const struct device *dev,
+					 gpio_port_pins_t pins)
+{
+	return gpio_pca6416_port_write(dev, 0, 0, pins);
+}
+
+static int gpio_pca6416_pin_interrupt_configure(const struct device *dev,
+						gpio_pin_t pin,
+						enum gpio_int_mode mode,
+						enum gpio_int_trig trig)
+{
+	const struct pca6416_config *cfg = dev->config;
+	struct pca6416_drv_data *drv_data = dev->data;
+	struct pca6416_irq_state *irq = &drv_data->irq_state;
+
+	if (!cfg->interrupt_enabled) {
+		return -ENOTSUP;
+	}
+	/* Device does not support level-triggered interrupts. */
+	if (mode == GPIO_INT_MODE_LEVEL) {
+		return -ENOTSUP;
+	}
+
+	k_sem_take(&drv_data->lock, K_FOREVER);
+
+	if (mode == GPIO_INT_MODE_DISABLED) {
+		irq->falling &= ~BIT(pin);
+		irq->rising &= ~BIT(pin);
+	} else { /* GPIO_INT_MODE_EDGE */
+		if (trig == GPIO_INT_TRIG_BOTH) {
+			irq->falling |= BIT(pin);
+			irq->rising |= BIT(pin);
+		} else if (trig == GPIO_INT_TRIG_LOW) {
+			irq->falling |= BIT(pin);
+			irq->rising &= ~BIT(pin);
+		} else if (trig == GPIO_INT_TRIG_HIGH) {
+			irq->falling &= ~BIT(pin);
+			irq->rising |= BIT(pin);
+		}
+	}
+
+	k_sem_give(&drv_data->lock);
+
+	return 0;
+}
+
+static int gpio_pca6416_manage_callback(const struct device *dev,
+					struct gpio_callback *callback,
+					bool set)
+{
+	struct pca6416_drv_data *data = dev->data;
+
+	return gpio_manage_callback(&data->cb, callback, set);
+}
+
+/**
+ * @brief Initialization function of PCA6416
+ *
+ * This sets initial input/ output configuration and output states.
+ * The interrupt is configured if this is enabled.
+ *
+ * @param dev Device struct
+ * @return 0 if successful, failed otherwise.
+ */
+static int gpio_pca6416_init(const struct device *dev)
+{
+	const struct pca6416_config *cfg = dev->config;
+	struct pca6416_drv_data *drv_data = dev->data;
+	int rc = 0;
+
+	if (!device_is_ready(cfg->i2c.bus)) {
+		LOG_ERR("I2C bus device not found");
+		goto out;
+	}
+
+	/* Do an initial read, this clears the interrupt pin and sets
+	 * up the initial value of the pin state input data.
+	 */
+	rc = update_input(dev);
+	if (rc) {
+		goto out;
+	}
+	if (cfg->interrupt_enabled) {
+		if (!gpio_is_ready_dt(&cfg->gpio_int)) {
+			LOG_ERR("Cannot get pointer to gpio interrupt device");
+			rc = -EINVAL;
+			goto out;
+		}
+
+		drv_data->dev = dev;
+
+		k_work_init(&drv_data->work, gpio_pca6416_work_handler);
+
+		rc = gpio_pin_configure_dt(&cfg->gpio_int, GPIO_INPUT);
+		if (rc) {
+			goto out;
+		}
+
+		rc = gpio_pin_interrupt_configure_dt(&cfg->gpio_int,
+						GPIO_INT_EDGE_TO_ACTIVE);
+		if (rc) {
+			goto out;
+		}
+
+		gpio_init_callback(&drv_data->gpio_cb,
+					gpio_pca6416_init_cb,
+					BIT(cfg->gpio_int.pin));
+		rc = gpio_add_callback(cfg->gpio_int.port,
+					&drv_data->gpio_cb);
+
+		if (rc) {
+			goto out;
+		}
+
+	}
+out:
+	if (rc) {
+		LOG_ERR("%s init failed: %d", dev->name, rc);
+	} else {
+		LOG_INF("%s init ok", dev->name);
+	}
+	return rc;
+}
+
+static DEVICE_API(gpio, api_table) = {
+	.pin_configure = gpio_pca6416_config,
+	.port_get_raw = gpio_pca6416_port_read,
+	.port_set_masked_raw = gpio_pca6416_port_set_masked,
+	.port_set_bits_raw = gpio_pca6416_port_set_bits,
+	.port_clear_bits_raw = gpio_pca6416_port_clear_bits,
+	.port_toggle_bits = gpio_pca6416_port_toggle_bits,
+	.pin_interrupt_configure = gpio_pca6416_pin_interrupt_configure,
+	.manage_callback = gpio_pca6416_manage_callback,
+};
+
+#define GPIO_PCA6416_INIT(n)							\
+	static const struct pca6416_config pca6416_cfg_##n = {			\
+		.i2c = I2C_DT_SPEC_INST_GET(n),					\
+		.common = {							\
+			.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),	\
+		},								\
+		.interrupt_enabled = DT_INST_NODE_HAS_PROP(n, interrupt_gpios),	\
+		.gpio_int = GPIO_DT_SPEC_INST_GET(n, interrupt_gpios),	\
+	};									\
+										\
+	static struct pca6416_drv_data pca6416_drvdata_##n = {			\
+		.lock = Z_SEM_INITIALIZER(pca6416_drvdata_##n.lock, 1, 1),	\
+		.pin_state.dir = ALL_PINS,					\
+		.pin_state.output = ALL_PINS,					\
+	};									\
+	DEVICE_DT_INST_DEFINE(n,						\
+		gpio_pca6416_init,						\
+		NULL,								\
+		&pca6416_drvdata_##n,						\
+		&pca6416_cfg_##n,						\
+		POST_KERNEL,							\
+		CONFIG_GPIO_PCA6416_INIT_PRIORITY,				\
+		&api_table);
+
+DT_INST_FOREACH_STATUS_OKAY(GPIO_PCA6416_INIT)
diff --git a/drivers/gpio/gpio_pca95xx.c b/drivers/gpio/gpio_pca95xx.c
index 662a92465f3..c08094c8bb7 100644
--- a/drivers/gpio/gpio_pca95xx.c
+++ b/drivers/gpio/gpio_pca95xx.c
@@ -117,38 +117,6 @@ struct gpio_pca95xx_drv_data {
 #endif
 };
 
-static int read_port_reg(const struct device *dev, uint8_t reg, uint8_t pin,
-			 uint16_t *cache, uint16_t *buf)
-{
-	const struct gpio_pca95xx_config * const config = dev->config;
-	uint8_t b_buf;
-	int ret;
-
-	if (pin >= 8) {
-		reg++;
-	}
-
-	ret = i2c_reg_read_byte_dt(&config->bus, reg, &b_buf);
-	if (ret != 0) {
-		LOG_ERR("PCA95XX[0x%X]: error reading register 0x%X (%d)",
-			config->bus.addr, reg, ret);
-		return ret;
-	}
-
-	if (pin < 8) {
-		((uint8_t *)cache)[LOW_BYTE_LE16_IDX] = b_buf;
-	} else {
-		((uint8_t *)cache)[HIGH_BYTE_LE16_IDX] = b_buf;
-	}
-
-	*buf = *cache;
-
-	LOG_DBG("PCA95XX[0x%X]: Read: REG[0x%X] = 0x%X",
-		config->bus.addr, reg, b_buf);
-
-	return 0;
-}
-
 /**
  * @brief Read both port 0 and port 1 registers of certain register function.
  *
@@ -253,16 +221,6 @@ static int write_port_regs(const struct device *dev, uint8_t reg,
 	return ret;
 }
 
-static inline int update_input_reg(const struct device *dev, uint8_t pin,
-				   uint16_t *buf)
-{
-	struct gpio_pca95xx_drv_data * const drv_data =
-		(struct gpio_pca95xx_drv_data * const)dev->data;
-
-	return read_port_reg(dev, REG_INPUT_PORT0, pin,
-			     &drv_data->reg_cache.input, buf);
-}
-
 static inline int update_input_regs(const struct device *dev, uint16_t *buf)
 {
 	struct gpio_pca95xx_drv_data * const drv_data =
diff --git a/drivers/gpio/gpio_pca_series.c b/drivers/gpio/gpio_pca_series.c
index bdea2dc56b2..87e13a36244 100644
--- a/drivers/gpio/gpio_pca_series.c
+++ b/drivers/gpio/gpio_pca_series.c
@@ -898,7 +898,7 @@ static int gpio_pca_series_pin_configure(const struct device *dev,
 {
 	const struct gpio_pca_series_config *cfg = dev->config;
 	struct gpio_pca_series_data *data = dev->data;
-	uint32_t reg_value;
+	uint32_t reg_value = 0;
 	int ret = 0;
 
 	if ((flags & GPIO_INPUT) && (flags & GPIO_OUTPUT)) {
@@ -1474,9 +1474,9 @@ static void gpio_pca_series_interrupt_handler_standard(const struct device *dev,
 {
 	struct gpio_pca_series_data *data = dev->data;
 	int ret = 0;
-	uint32_t input_old, int_rise, int_fall;
-	uint32_t input;
-	uint32_t transitioned_pins;
+	uint32_t input_old = 0, int_rise = 0, int_fall = 0;
+	uint32_t input = 0;
+	uint32_t transitioned_pins = 0;
 	uint32_t int_status = 0;
 
 	k_sem_take(&data->lock, K_FOREVER);
@@ -2140,22 +2140,22 @@ const struct gpio_pca_series_part_config gpio_pca_series_part_cfg_pcal6524 = {
 
 static const uint8_t gpio_pca_series_reg_pcal6534[] = {
 	PCA_REG_INVALID, /** input_port if not PCA_HAS_OUT_CONFIG, non-cacheable */
-	0x04, /** output_port */
-/*	0x08,     polarity_inversion  (unused, omitted) */
-	0x0c, /** configuration */
-	0x40, /** 2b_output_drive_strength if PCA_HAS_LATCH*/
-	0x48, /** input_latch if PCA_HAS_LATCH*/
-	0x4c, /** pull_enable if PCA_HAS_PULL */
-	0x50, /** pull_select if PCA_HAS_PULL */
-	0x6c, /** input_status if PCA_HAS_OUT_CONFIG, non-cacheable */
-	0x70, /** output_config if PCA_HAS_OUT_CONFIG */
+	0x05, /** output_port */
+/*	0x0a,     polarity_inversion  (unused, omitted) */
+	0x0f, /** configuration */
+	0x30, /** 2b_output_drive_strength if PCA_HAS_LATCH*/
+	0x3a, /** input_latch if PCA_HAS_LATCH*/
+	0x3f, /** pull_enable if PCA_HAS_PULL */
+	0x44, /** pull_select if PCA_HAS_PULL */
+	0x63, /** input_status if PCA_HAS_OUT_CONFIG, non-cacheable */
+	0x68, /** output_config if PCA_HAS_OUT_CONFIG */
 #ifdef CONFIG_GPIO_PCA_SERIES_INTERRUPT
-	0x54, /** interrupt_mask if PCA_HAS_INT_MASK,
+	0x49, /** interrupt_mask if PCA_HAS_INT_MASK,
 		* non-cacheable if not PCA_HAS_INT_EXTEND
 		*/
-	0x58, /** int_status if PCA_HAS_INT_MASK */
-	0x60, /** 2b_interrupt_edge if PCA_HAS_INT_EXTEND */
-	0x68, /** interrupt_clear if PCA_HAS_INT_EXTEND, non-cacheable */
+	0x4e, /** int_status if PCA_HAS_INT_MASK */
+	0x54, /** 2b_interrupt_edge if PCA_HAS_INT_EXTEND */
+	0x5e, /** interrupt_clear if PCA_HAS_INT_EXTEND, non-cacheable */
 # ifdef CONFIG_GPIO_PCA_SERIES_CACHE_ALL
 	PCA_REG_INVALID, /** 1b_input_history if PCA_HAS_LATCH and not PCA_HAS_INT_EXTEND */
 	PCA_REG_INVALID, /** 1b_interrupt_rise if PCA_HAS_LATCH and not PCA_HAS_INT_EXTEND */
diff --git a/drivers/gpio/gpio_renesas_ra.c b/drivers/gpio/gpio_renesas_ra.c
deleted file mode 100644
index 69bb67c18d5..00000000000
--- a/drivers/gpio/gpio_renesas_ra.c
+++ /dev/null
@@ -1,435 +0,0 @@
-/*
- * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DT_DRV_COMPAT renesas_ra_gpio
-
-#include <errno.h>
-#include <string.h>
-
-#include <zephyr/kernel.h>
-#include <zephyr/device.h>
-#include <zephyr/init.h>
-#include <zephyr/irq.h>
-#include <zephyr/drivers/gpio.h>
-#include <zephyr/drivers/gpio/gpio_utils.h>
-#include <zephyr/drivers/interrupt_controller/intc_ra_icu.h>
-#include <zephyr/drivers/pinctrl.h>
-
-enum {
-	PCNTR1_OFFSET = 0x0,
-	PCNTR2_OFFSET = 0x4,
-	PCNTR3_OFFSET = 0x8,
-	PCNTR4_OFFSET = 0xc
-};
-
-enum {
-	PCNTR1_PDR0_OFFSET = 0,
-	PCNTR1_PODR0_OFFSET = 16,
-};
-
-enum {
-	PCNTR2_PIDR0_OFFSET = 0,
-	PCNTR2_EIDR0_OFFSET = 16,
-};
-
-enum {
-	PCNTR3_POSR0_OFFSET = 0,
-	PCNTR3_PORR0_OFFSET = 16,
-};
-
-enum {
-	PCNTR4_EOSR0_OFFSET = 0,
-	PCNTR4_EORR0_OFFSET = 16,
-};
-
-struct gpio_ra_irq_info {
-	const uint8_t *const pins;
-	size_t num;
-	int port_irq;
-	int irq;
-	uint32_t priority;
-	uint32_t flags;
-	ra_isr_handler isr;
-};
-
-struct gpio_ra_pin_irq_info {
-	const struct gpio_ra_irq_info *info;
-	uint8_t pin;
-};
-
-struct gpio_ra_config {
-	struct gpio_driver_config common;
-	mem_addr_t regs;
-	struct gpio_ra_irq_info *irq_info;
-	uint32_t irq_info_size;
-	uint16_t port;
-};
-
-struct gpio_ra_data {
-	struct gpio_driver_data common;
-	struct gpio_ra_pin_irq_info port_irq_info[16];
-	sys_slist_t callbacks;
-};
-
-static inline uint32_t gpio_ra_irq_info_event(const struct gpio_ra_irq_info *info)
-{
-	return ((info->flags & RA_ICU_FLAG_EVENT_MASK) >> RA_ICU_FLAG_EVENT_OFFSET);
-}
-
-static void gpio_ra_isr(const struct device *dev, uint32_t port_irq)
-{
-	struct gpio_ra_data *data = dev->data;
-	const struct gpio_ra_pin_irq_info *pin_irq = &data->port_irq_info[port_irq];
-	const int irq = ra_icu_query_exists_irq(gpio_ra_irq_info_event(pin_irq->info));
-
-	if (irq >= 0) {
-		gpio_fire_callbacks(&data->callbacks, dev, BIT(pin_irq->pin));
-		ra_icu_clear_int_flag(irq);
-	}
-}
-
-static const struct gpio_ra_irq_info *query_irq_info(const struct device *dev, uint32_t pin)
-{
-	const struct gpio_ra_config *config = dev->config;
-
-	for (int i = 0; i < config->irq_info_size; i++) {
-		const struct gpio_ra_irq_info *info = &config->irq_info[i];
-
-		for (int j = 0; j < info->num; j++) {
-			if (info->pins[j] == pin) {
-				return info;
-			}
-		}
-	}
-
-	return NULL;
-}
-
-static inline uint32_t reg_read(const struct device *dev, size_t offset)
-{
-	const struct gpio_ra_config *config = dev->config;
-
-	return sys_read32(config->regs + offset);
-}
-
-static inline void reg_write(const struct device *dev, size_t offset, uint32_t value)
-{
-	const struct gpio_ra_config *config = dev->config;
-
-	sys_write32(value, config->regs + offset);
-}
-
-static inline uint32_t port_read(const struct device *dev)
-{
-	return reg_read(dev, PCNTR2_OFFSET) & UINT16_MAX;
-}
-
-static int port_write(const struct device *dev, uint16_t value, uint16_t mask)
-{
-	const uint16_t set = value & mask;
-	const uint16_t clr = (~value) & mask;
-
-	reg_write(dev, PCNTR3_OFFSET, (clr << PCNTR3_PORR0_OFFSET) | set << PCNTR3_POSR0_OFFSET);
-
-	return 0;
-}
-
-static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
-{
-	const enum gpio_int_mode mode =
-		flags & (GPIO_INT_EDGE | GPIO_INT_DISABLE | GPIO_INT_ENABLE);
-	const enum gpio_int_trig trig = flags & (GPIO_INT_LOW_0 | GPIO_INT_HIGH_1);
-	const struct gpio_ra_config *config = dev->config;
-	struct gpio_ra_data *data = dev->data;
-	struct ra_pinctrl_soc_pin pincfg = {0};
-
-	if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) {
-		/* Pin cannot be configured as input and output */
-		return -ENOTSUP;
-	} else if (!(flags & (GPIO_INPUT | GPIO_OUTPUT))) {
-		/* Pin has to be configured as input or output */
-		return -ENOTSUP;
-	}
-
-	if (flags & GPIO_OUTPUT) {
-		pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_PDR_Pos);
-	}
-
-	if (flags & GPIO_PULL_UP) {
-		pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_PCR_Pos);
-	}
-
-	if ((flags & GPIO_SINGLE_ENDED) && (flags & GPIO_LINE_OPEN_DRAIN)) {
-		pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_NCODR_Pos);
-	}
-
-	if (flags & GPIO_INT_ENABLE) {
-		pincfg.cfg |= BIT(R_PFS_PORT_PIN_PmnPFS_ISEL_Pos);
-	}
-
-	pincfg.cfg &= ~BIT(R_PFS_PORT_PIN_PmnPFS_PMR_Pos);
-
-	pincfg.pin_num = pin;
-	pincfg.port_num = config->port;
-
-	if (flags & GPIO_INT_ENABLE) {
-		const struct gpio_ra_irq_info *irq_info;
-		uint32_t intcfg;
-		int irqn;
-
-		if (mode == GPIO_INT_MODE_LEVEL) {
-			if (trig != GPIO_INT_TRIG_LOW) {
-				return -ENOTSUP;
-			}
-
-			intcfg = ICU_LOW_LEVEL;
-		} else if (mode == GPIO_INT_MODE_EDGE) {
-			switch (trig) {
-			case GPIO_INT_TRIG_LOW:
-				intcfg = ICU_FALLING;
-				break;
-			case GPIO_INT_TRIG_HIGH:
-				intcfg = ICU_RISING;
-				break;
-			case GPIO_INT_TRIG_BOTH:
-				intcfg = ICU_BOTH_EDGE;
-				break;
-			default:
-				return -ENOTSUP;
-			}
-		} else {
-			return -ENOTSUP;
-		}
-
-		irq_info = query_irq_info(dev, pin);
-		if (irq_info == NULL) {
-			return -EINVAL;
-		}
-
-		irqn = ra_icu_irq_connect_dynamic(
-			irq_info->irq, irq_info->priority, irq_info->isr, dev,
-			(intcfg << RA_ICU_FLAG_INTCFG_OFFSET) | irq_info->flags);
-		if (irqn < 0) {
-			return irqn;
-		}
-
-		data->port_irq_info[irq_info->port_irq].pin = pin;
-		data->port_irq_info[irq_info->port_irq].info = irq_info;
-
-		irq_enable(irqn);
-	}
-
-	return pinctrl_configure_pins(&pincfg, 1, PINCTRL_REG_NONE);
-}
-
-#ifdef CONFIG_GPIO_GET_CONFIG
-static int gpio_ra_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *flags)
-{
-	const struct gpio_ra_config *config = dev->config;
-	const struct gpio_ra_irq_info *irq_info;
-	struct ra_pinctrl_soc_pin pincfg;
-	ra_isr_handler cb;
-	const void *cbarg;
-	uint32_t intcfg;
-	int irqn;
-	int err;
-
-	memset(flags, 0, sizeof(gpio_flags_t));
-
-	err = ra_pinctrl_query_config(config->port, pin, &pincfg);
-	if (err < 0) {
-		return err;
-	}
-
-	if (pincfg.cfg & BIT(R_PFS_PORT_PIN_PmnPFS_PDR_Pos)) {
-		*flags |= GPIO_OUTPUT;
-	} else {
-		*flags |= GPIO_INPUT;
-	}
-
-	if (pincfg.cfg & BIT(R_PFS_PORT_PIN_PmnPFS_ISEL_Pos)) {
-		*flags |= GPIO_INT_ENABLE;
-	}
-
-	if (pincfg.cfg & BIT(R_PFS_PORT_PIN_PmnPFS_PCR_Pos)) {
-		*flags |= GPIO_PULL_UP;
-	}
-
-	irq_info = query_irq_info(dev, pin);
-	if (irq_info == NULL) {
-		return 0;
-	}
-
-	irqn = ra_icu_query_exists_irq(gpio_ra_irq_info_event(irq_info));
-	if (irqn < 0) {
-		return 0;
-	}
-
-	ra_icu_query_irq_config(irqn, &intcfg, &cb, &cbarg);
-
-	if (cbarg != dev) {
-		return 0;
-	}
-
-	if (intcfg == ICU_FALLING) {
-		*flags |= GPIO_INT_TRIG_LOW;
-		*flags |= GPIO_INT_MODE_EDGE;
-	} else if (intcfg == ICU_RISING) {
-		*flags |= GPIO_INT_TRIG_HIGH;
-		*flags |= GPIO_INT_MODE_EDGE;
-	} else if (intcfg == ICU_BOTH_EDGE) {
-		*flags |= GPIO_INT_TRIG_BOTH;
-		*flags |= GPIO_INT_MODE_EDGE;
-	} else if (intcfg == ICU_LOW_LEVEL) {
-		*flags |= GPIO_INT_TRIG_LOW;
-		*flags |= GPIO_INT_MODE_LEVEL;
-	}
-
-	return 0;
-}
-#endif
-
-static int gpio_ra_port_get_raw(const struct device *dev, gpio_port_value_t *value)
-{
-	*value = port_read(dev);
-
-	return 0;
-}
-
-static int gpio_ra_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
-				       gpio_port_value_t value)
-{
-	uint16_t port_val;
-
-	port_val = port_read(dev);
-	port_val = (port_val & ~mask) | (value & mask);
-	return port_write(dev, port_val, UINT16_MAX);
-}
-
-static int gpio_ra_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
-{
-	uint16_t port_val;
-
-	port_val = port_read(dev);
-	port_val |= pins;
-	return port_write(dev, port_val, UINT16_MAX);
-}
-
-static int gpio_ra_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
-{
-	uint16_t port_val;
-
-	port_val = port_read(dev);
-	port_val &= ~pins;
-	return port_write(dev, port_val, UINT16_MAX);
-}
-
-static int gpio_ra_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
-{
-	uint16_t port_val;
-
-	port_val = port_read(dev);
-	port_val ^= pins;
-	return port_write(dev, port_val, UINT16_MAX);
-}
-
-static int gpio_ra_manage_callback(const struct device *dev, struct gpio_callback *callback,
-				   bool set)
-{
-	struct gpio_ra_data *data = dev->data;
-
-	return gpio_manage_callback(&data->callbacks, callback, set);
-}
-
-static int gpio_ra_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin,
-					   enum gpio_int_mode mode, enum gpio_int_trig trig)
-{
-	gpio_flags_t pincfg;
-	int err;
-
-	err = gpio_ra_pin_get_config(dev, pin, &pincfg);
-	if (err < 0) {
-		return err;
-	}
-
-	return gpio_ra_pin_configure(dev, pin, pincfg | mode | trig);
-}
-
-static DEVICE_API(gpio, gpio_ra_driver_api) = {
-	.pin_configure = gpio_ra_pin_configure,
-#ifdef CONFIG_GPIO_GET_CONFIG
-	.pin_get_config = gpio_ra_pin_get_config,
-#endif
-	.port_get_raw = gpio_ra_port_get_raw,
-	.port_set_masked_raw = gpio_ra_port_set_masked_raw,
-	.port_set_bits_raw = gpio_ra_port_set_bits_raw,
-	.port_clear_bits_raw = gpio_ra_port_clear_bits_raw,
-	.port_toggle_bits = gpio_ra_port_toggle_bits,
-	.pin_interrupt_configure = gpio_ra_pin_interrupt_configure,
-	.manage_callback = gpio_ra_manage_callback,
-};
-
-#define RA_NUM_PORT_IRQ0  0
-#define RA_NUM_PORT_IRQ1  1
-#define RA_NUM_PORT_IRQ2  2
-#define RA_NUM_PORT_IRQ3  3
-#define RA_NUM_PORT_IRQ4  4
-#define RA_NUM_PORT_IRQ5  5
-#define RA_NUM_PORT_IRQ6  6
-#define RA_NUM_PORT_IRQ7  7
-#define RA_NUM_PORT_IRQ8  8
-#define RA_NUM_PORT_IRQ9  9
-#define RA_NUM_PORT_IRQ10 10
-#define RA_NUM_PORT_IRQ11 11
-#define RA_NUM_PORT_IRQ12 12
-#define RA_NUM_PORT_IRQ13 13
-#define RA_NUM_PORT_IRQ14 14
-#define RA_NUM_PORT_IRQ15 15
-
-#define GPIO_RA_DECL_PINS(n, p, i)                                                                 \
-	const uint8_t _CONCAT(n, ___pins##i[]) = {DT_FOREACH_PROP_ELEM_SEP(                        \
-		n, _CONCAT(DT_STRING_TOKEN_BY_IDX(n, p, i), _pins), DT_PROP_BY_IDX, (,))};
-
-#define GPIO_RA_IRQ_INFO(n, p, i)                                                                  \
-	{                                                                                          \
-		.port_irq = _CONCAT(RA_NUM_, DT_STRING_UPPER_TOKEN_BY_IDX(n, p, i)),               \
-		.irq = DT_IRQ_BY_IDX(n, i, irq),                                                   \
-		.flags = DT_IRQ_BY_IDX(n, i, flags),                                               \
-		.priority = DT_IRQ_BY_IDX(n, i, priority),                                         \
-		.pins = _CONCAT(n, ___pins##i),                                                    \
-		.num = ARRAY_SIZE(_CONCAT(n, ___pins##i)),                                         \
-		.isr = _CONCAT(n, _CONCAT(gpio_ra_isr_, DT_STRING_TOKEN_BY_IDX(n, p, i))),         \
-	},
-
-#define GPIO_RA_ISR_DECL(n, p, i)                                                                  \
-	static void _CONCAT(n, _CONCAT(gpio_ra_isr_, DT_STRING_TOKEN_BY_IDX(n, p, i)))(            \
-		const void *arg)                                                                   \
-	{                                                                                          \
-		gpio_ra_isr((const struct device *)arg,                                            \
-			    _CONCAT(RA_NUM_, DT_STRING_UPPER_TOKEN_BY_IDX(n, p, i)));              \
-	}
-
-#define GPIO_RA_INIT(idx)                                                                          \
-	static struct gpio_ra_data gpio_ra_data_##idx = {};                                        \
-	DT_INST_FOREACH_PROP_ELEM(idx, interrupt_names, GPIO_RA_DECL_PINS);                        \
-	DT_INST_FOREACH_PROP_ELEM(idx, interrupt_names, GPIO_RA_ISR_DECL);                         \
-	struct gpio_ra_irq_info gpio_ra_irq_info_##idx[] = {                                       \
-		DT_INST_FOREACH_PROP_ELEM(idx, interrupt_names, GPIO_RA_IRQ_INFO)};                \
-	static struct gpio_ra_config gpio_ra_config_##idx = {                                      \
-		.common = {                                                                        \
-			.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx),                     \
-		},                                                                                 \
-		.regs = DT_INST_REG_ADDR(idx),                                                     \
-		.port = (DT_INST_REG_ADDR(idx) - DT_REG_ADDR(DT_NODELABEL(ioport0))) /             \
-			DT_INST_REG_SIZE(idx),                                                     \
-		.irq_info = gpio_ra_irq_info_##idx,                                                \
-		.irq_info_size = ARRAY_SIZE(gpio_ra_irq_info_##idx),                               \
-	};                                                                                         \
-                                                                                                   \
-	DEVICE_DT_INST_DEFINE(idx, NULL, NULL, &gpio_ra_data_##idx, &gpio_ra_config_##idx,         \
-			      PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_ra_driver_api);
-
-DT_INST_FOREACH_STATUS_OKAY(GPIO_RA_INIT)
diff --git a/drivers/gpio/gpio_renesas_ra_ioport.c b/drivers/gpio/gpio_renesas_ra_ioport.c
index 39e12321cb2..68d5334c675 100644
--- a/drivers/gpio/gpio_renesas_ra_ioport.c
+++ b/drivers/gpio/gpio_renesas_ra_ioport.c
@@ -78,6 +78,7 @@ static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_
 		return -ENOTSUP;
 	}
 
+#if CONFIG_GPIO_RA_HAS_VBTICTLR
 	if (config->vbatt_pins[0] != 0xFF) {
 		uint32_t clear = 0;
 
@@ -93,6 +94,7 @@ static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_
 
 		R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT);
 	}
+#endif
 
 	pincfg.port_num = config->port_num;
 	pincfg.pin_num = pin;
@@ -175,6 +177,37 @@ static int gpio_ra_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_
 	return pinctrl_configure_pins(&pincfg, 1, PINCTRL_REG_NONE);
 }
 
+__maybe_unused static int gpio_ra_pin_get_config(const struct device *dev, gpio_pin_t pin,
+						 gpio_flags_t *flags)
+{
+	const struct gpio_ra_config *config = dev->config;
+	uint32_t pincfg;
+
+	if (pin >= RA_PINCTRL_PIN_NUM) {
+		return -EINVAL;
+	}
+
+	memset(flags, 0, sizeof(gpio_flags_t));
+
+	pincfg = R_PFS->PORT[config->port_num].PIN[pin].PmnPFS;
+
+	if (pincfg & BIT(R_PFS_PORT_PIN_PmnPFS_PDR_Pos)) {
+		*flags |= GPIO_OUTPUT;
+	} else {
+		*flags |= GPIO_INPUT;
+	}
+
+	if (pincfg & BIT(R_PFS_PORT_PIN_PmnPFS_NCODR_Pos)) {
+		*flags |= GPIO_LINE_OPEN_DRAIN;
+	}
+
+	if (pincfg & BIT(R_PFS_PORT_PIN_PmnPFS_PCR_Pos)) {
+		*flags |= GPIO_PULL_UP;
+	}
+
+	return 0;
+}
+
 static int gpio_ra_port_get_raw(const struct device *dev, uint32_t *value)
 {
 	const struct gpio_ra_config *config = dev->config;
@@ -230,7 +263,15 @@ static int gpio_ra_port_toggle_bits(const struct device *dev, gpio_port_pins_t p
 static int gpio_ra_pin_interrupt_configure(const struct device *port, gpio_pin_t pin,
 					   enum gpio_int_mode mode, enum gpio_int_trig trig)
 {
-	return gpio_ra_pin_configure(port, pin, (mode | trig));
+	gpio_flags_t flags;
+	int err;
+
+	err = gpio_ra_pin_get_config(port, pin, &flags);
+	if (err) {
+		return err;
+	}
+
+	return gpio_ra_pin_configure(port, pin, (flags | mode | trig));
 }
 
 static int gpio_ra_manage_callback(const struct device *dev, struct gpio_callback *callback,
@@ -244,6 +285,9 @@ static int gpio_ra_manage_callback(const struct device *dev, struct gpio_callbac
 
 static DEVICE_API(gpio, gpio_ra_drv_api_funcs) = {
 	.pin_configure = gpio_ra_pin_configure,
+#ifdef CONFIG_GPIO_GET_CONFIG
+	.pin_get_config = gpio_ra_pin_get_config,
+#endif
 	.port_get_raw = gpio_ra_port_get_raw,
 	.port_set_masked_raw = gpio_ra_port_set_masked_raw,
 	.port_set_bits_raw = gpio_ra_port_set_bits_raw,
@@ -268,10 +312,16 @@ static DEVICE_API(gpio, gpio_ra_drv_api_funcs) = {
 		.num = ARRAY_SIZE(CONCAT(n, ___pins##i)),                                          \
 	},
 
+#define DECL_PINS_PARAMETER(node)                                                                  \
+	COND_CODE_1(DT_NODE_HAS_PROP(node, port_irq_names),                                        \
+	(DT_FOREACH_PROP_ELEM(node, port_irq_names, GPIO_RA_DECL_PINS)), ())
+#define IRQ_INFO_PARAMETER(node)                                                                   \
+	COND_CODE_1(DT_NODE_HAS_PROP(node, port_irq_names),                                        \
+	(DT_FOREACH_PROP_ELEM(node, port_irq_names, GPIO_RA_IRQ_INFO)), ())
+
 #define GPIO_DEVICE_INIT(node, port_number, suffix, addr)                                          \
-	DT_FOREACH_PROP_ELEM(node, port_irq_names, GPIO_RA_DECL_PINS);                             \
-	struct gpio_ra_irq_info gpio_ra_irq_info_##suffix[] = {                                    \
-		DT_FOREACH_PROP_ELEM(node, port_irq_names, GPIO_RA_IRQ_INFO)};                     \
+	DECL_PINS_PARAMETER(node);                                                                 \
+	struct gpio_ra_irq_info gpio_ra_irq_info_##suffix[] = {IRQ_INFO_PARAMETER(node)};          \
 	static const struct gpio_ra_config gpio_ra_config_##suffix = {                             \
 		.common =                                                                          \
 			{                                                                          \
diff --git a/drivers/gpio/gpio_renesas_rz.c b/drivers/gpio/gpio_renesas_rz.c
index 386bae12bfb..fa0b525ef20 100644
--- a/drivers/gpio/gpio_renesas_rz.c
+++ b/drivers/gpio/gpio_renesas_rz.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,6 +15,10 @@
 #include <zephyr/drivers/gpio/gpio_utils.h>
 #include "gpio_renesas_rz.h"
 #include <zephyr/logging/log.h>
+#if defined(CONFIG_RENESAS_RZ_EXT_IRQ)
+#include "r_icu.h"
+#include <zephyr/drivers/interrupt_controller/intc_rz_ext_irq.h>
+#endif
 LOG_MODULE_REGISTER(rz_gpio, CONFIG_GPIO_LOG_LEVEL);
 
 #define LOG_DEV_ERR(dev, format, ...) LOG_ERR("%s:" #format, (dev)->name, ##__VA_ARGS__)
@@ -28,7 +32,12 @@ struct gpio_rz_config {
 	const ioport_cfg_t *fsp_cfg;
 	const ioport_api_t *fsp_api;
 	const struct device *int_dev;
-	uint8_t tint_num[GPIO_RZ_MAX_TINT_NUM];
+	uint8_t int_num[GPIO_RZ_MAX_INT_NUM];
+#if defined(CONFIG_RENESAS_RZ_EXT_IRQ)
+	const struct device *eirq_dev[GPIO_RZ_MAX_INT_NUM];
+
+	void (*cb_list[GPIO_RZ_MAX_INT_NUM])(void *arg);
+#endif
 };
 
 struct gpio_rz_data {
@@ -36,62 +45,74 @@ struct gpio_rz_data {
 	sys_slist_t cb;
 	ioport_instance_ctrl_t *fsp_ctrl;
 	struct k_spinlock lock;
+#if defined(CONFIG_RENESAS_RZ_EXT_IRQ)
+	uint8_t pin[GPIO_RZ_MAX_INT_NUM];
+#endif
 };
 
-struct gpio_rz_tint_isr_data {
+struct gpio_rz_isr_data {
 	const struct device *gpio_dev;
 	gpio_pin_t pin;
 };
 
-struct gpio_rz_tint_data {
-	struct gpio_rz_tint_isr_data tint_data[GPIO_RZ_MAX_TINT_NUM];
+struct gpio_rz_int_data {
+	struct gpio_rz_isr_data gpio_mapping[GPIO_RZ_MAX_INT_NUM];
 	uint32_t irq_set_edge;
 };
 
+struct gpio_rz_hw_config {
+	gpio_flags_t p_pm;
+	uint8_t pfc;
+};
+
 struct gpio_rz_tint_config {
 	void (*gpio_int_init)(void);
 };
 
-static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, uint32_t *flags);
+static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, struct gpio_rz_hw_config *flags);
 
 #ifdef CONFIG_GPIO_GET_CONFIG
 static int gpio_rz_pin_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *flags)
 {
 	const struct gpio_rz_config *config = dev->config;
 	bsp_io_port_pin_t port_pin = config->fsp_port | pin;
+	struct gpio_rz_hw_config hw_flags;
+
+	gpio_rz_pin_config_get_raw(port_pin, &hw_flags);
+	*flags = hw_flags.p_pm;
 
-	gpio_rz_pin_config_get_raw(port_pin, flags);
 	return 0;
 }
 #endif
 
 /* Get previous pin's configuration, used by pin_configure/pin_interrupt_configure api */
-static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, uint32_t *flags)
+static int gpio_rz_pin_config_get_raw(bsp_io_port_pin_t port_pin, struct gpio_rz_hw_config *flags)
 {
 	bsp_io_port_t port = (port_pin >> 8U) & 0xFF;
 	gpio_pin_t pin = port_pin & 0xFF;
-	volatile uint8_t *p_p = GPIO_RZ_IOPORT_P_REG_BASE_GET;
-	volatile uint16_t *p_pm = GPIO_RZ_IOPORT_PM_REG_BASE_GET;
+	volatile uint8_t *p_p = GPIO_RZ_IOPORT_P_REG_GET(port, pin);
+	volatile uint16_t *p_pm = GPIO_RZ_IOPORT_PM_REG_GET(port, pin);
+	volatile uint32_t *p_pfc = GPIO_RZ_IOPORT_PFC_REG_GET(port, pin);
 
-	uint8_t adr_offset;
 	uint8_t p_value;
 	uint16_t pm_value;
-
-	adr_offset = (uint8_t)GPIO_RZ_REG_OFFSET(port, pin);
-
-	p_p = &p_p[adr_offset];
-	p_pm = &p_pm[adr_offset];
+	uint32_t pfc_value;
 
 	p_value = GPIO_RZ_P_VALUE_GET(*p_p, pin);
 	pm_value = GPIO_RZ_PM_VALUE_GET(*p_pm, pin);
+	pfc_value = GPIO_RZ_PFC_VALUE_GET(*p_pfc, pin);
+
+	flags->p_pm = 0;
+	flags->pfc = 0;
 
 	if (p_value) {
-		*flags |= GPIO_OUTPUT_INIT_HIGH;
+		flags->p_pm |= GPIO_OUTPUT_INIT_HIGH;
 	} else {
-		*flags |= GPIO_OUTPUT_INIT_LOW;
+		flags->p_pm |= GPIO_OUTPUT_INIT_LOW;
 	}
 
-	*flags |= ((pm_value << 16));
+	flags->p_pm |= (pm_value << 16);
+	flags->pfc |= pfc_value;
 	return 0;
 }
 
@@ -101,14 +122,14 @@ static int gpio_rz_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_
 	struct gpio_rz_data *data = dev->data;
 	bsp_io_port_pin_t port_pin = config->fsp_port | pin;
 	uint32_t ioport_config_data = 0;
-	gpio_flags_t pre_flags;
+	struct gpio_rz_hw_config pre_flags;
 	fsp_err_t err;
 
 	gpio_rz_pin_config_get_raw(port_pin, &pre_flags);
 
 	if (!flags) {
 		/* Disconnect mode */
-		ioport_config_data = 0;
+		GPIO_RZ_PIN_DISCONNECT(config->fsp_port, pin);
 	} else if (!(flags & GPIO_OPEN_DRAIN)) {
 		/* PM register */
 		ioport_config_data &= GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET;
@@ -124,7 +145,7 @@ static int gpio_rz_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_
 		}
 		/* P register */
 		if (!(flags & (GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOW))) {
-			flags |= pre_flags & (GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOW);
+			flags |= pre_flags.p_pm & (GPIO_OUTPUT_INIT_HIGH | GPIO_OUTPUT_INIT_LOW);
 		}
 
 		if (flags & GPIO_OUTPUT_INIT_HIGH) {
@@ -136,21 +157,36 @@ static int gpio_rz_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_
 		if (flags & GPIO_PULL_UP) {
 			ioport_config_data |= IOPORT_CFG_PULLUP_ENABLE;
 		} else if (flags & GPIO_PULL_DOWN) {
-			ioport_config_data |= IOPORT_CFG_PULLUP_ENABLE;
+			ioport_config_data |= IOPORT_CFG_PULLDOWN_ENABLE;
 		}
 
-		/* ISEL register */
+		/*
+		 * Interrupt register
+		 * RZG: ISEL
+		 * RZTN: PMC
+		 */
 		if (flags & GPIO_INT_ENABLE) {
 			ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_INT_ENABLE;
 		} else if (flags & GPIO_INT_DISABLE) {
 			ioport_config_data &= GPIO_RZ_PIN_CONFIGURE_INT_DISABLE;
 		}
 
-		/* Drive Ability register */
-		ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_GET_DRIVE_ABILITY(flags);
-
-		/* Filter register, see in renesas-rz-gpio-ioport.h */
-		ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flags);
+		/*
+		 * Drive ability register
+		 * RZG: IOLH
+		 * RZTN: DRCTL
+		 */
+		ioport_config_data |= GPIO_RZ_PIN_CONFIGURE_GET(flags);
+
+		/* PFC register */
+		ioport_config_data |= GPIO_RZ_IOPORT_PFC_SET(pre_flags.pfc);
+
+		/*
+		 * Specific register
+		 * RZG: FILONOFF, FILNUM, FILCLKSEL
+		 * RZTN: RSELP
+		 */
+		ioport_config_data |= GPIO_RZ_PIN_SPECIAL_FLAG_GET(flags);
 	} else {
 		return -ENOTSUP;
 	}
@@ -228,7 +264,7 @@ static int gpio_rz_port_toggle_bits(const struct device *dev, gpio_port_pins_t p
 	const struct gpio_rz_config *config = dev->config;
 	struct gpio_rz_data *data = dev->data;
 	bsp_io_port_pin_t port_pin;
-	gpio_flags_t pre_flags;
+	struct gpio_rz_hw_config pre_flags;
 	ioport_size_t value = 0;
 	fsp_err_t err;
 
@@ -236,9 +272,9 @@ static int gpio_rz_port_toggle_bits(const struct device *dev, gpio_port_pins_t p
 		if (pins & (1U << idx)) {
 			port_pin = config->fsp_port | idx;
 			gpio_rz_pin_config_get_raw(port_pin, &pre_flags);
-			if (pre_flags & GPIO_OUTPUT_INIT_HIGH) {
+			if (pre_flags.p_pm & GPIO_OUTPUT_INIT_HIGH) {
 				value &= (1U << idx);
-			} else if (pre_flags & GPIO_OUTPUT_INIT_LOW) {
+			} else if (pre_flags.p_pm & GPIO_OUTPUT_INIT_LOW) {
 				value |= (1U << idx);
 			}
 		}
@@ -251,60 +287,88 @@ static int gpio_rz_port_toggle_bits(const struct device *dev, gpio_port_pins_t p
 	return 0;
 }
 
-#define GPIO_RZ_HAS_INTERRUPT DT_HAS_COMPAT_STATUS_OKAY(renesas_rz_gpio_int)
-
-#if GPIO_RZ_HAS_INTERRUPT
-static int gpio_rz_int_disable(const struct device *dev, uint8_t tint_num)
+#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT) || defined(CONFIG_RENESAS_RZ_EXT_IRQ)
+static int gpio_rz_int_disable(const struct device *dev, const struct device *gpio_dev,
+			       uint8_t int_num, gpio_pin_t pin)
 {
-	struct gpio_rz_tint_data *data = dev->data;
-	volatile uint32_t *tssr = &R_INTC_IM33->TSSR0;
-	volatile uint32_t *titsr = &R_INTC_IM33->TITSR0;
-	volatile uint32_t *tscr = &R_INTC_IM33->TSCR;
+#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT)
+	volatile uint32_t *tssr = &R_INTC->TSSR0;
+	volatile uint32_t *titsr = &R_INTC->TITSR0;
+	volatile uint32_t *tscr = &R_INTC->TSCR;
+	struct gpio_rz_int_data *data = dev->data;
 
 	/* Get register offset base on interrupt number. */
-	tssr = &tssr[tint_num / 4];
-	titsr = &titsr[tint_num / 16];
+	tssr = &tssr[int_num / 4];
+	titsr = &titsr[int_num / 16];
 
-	irq_disable(GPIO_RZ_TINT_IRQ_GET(tint_num));
+	irq_disable(GPIO_RZ_TINT_IRQ_GET(int_num));
 	/* Disable interrupt and clear interrupt source. */
-	*tssr &= ~(0xFF << GPIO_RZ_TSSR_OFFSET(tint_num));
+	*tssr &= ~(0xFF << GPIO_RZ_TSSR_OFFSET(int_num));
 	/* Reset interrupt dectect type to default. */
-	*titsr &= ~(0x3 << GPIO_RZ_TITSR_OFFSET(tint_num));
+	*titsr &= ~(0x3 << GPIO_RZ_TITSR_OFFSET(int_num));
 
 	/* Clear interrupt detection status. */
-	if (data->irq_set_edge & BIT(tint_num)) {
-		*tscr &= ~BIT(tint_num);
-		data->irq_set_edge &= ~BIT(tint_num);
+	if (data->irq_set_edge & BIT(int_num)) {
+		*tscr &= ~BIT(int_num);
+		data->irq_set_edge &= ~BIT(int_num);
+	}
+
+	data->gpio_mapping[int_num].gpio_dev = NULL;
+	data->gpio_mapping[int_num].pin = UINT8_MAX;
+#elif defined(CONFIG_RENESAS_RZ_EXT_IRQ)
+	const struct gpio_rz_config *gpio_config = gpio_dev->config;
+	const struct device *eirq_dev = gpio_config->eirq_dev[pin];
+
+	if (device_is_ready(eirq_dev)) {
+		intc_rz_ext_irq_disable(eirq_dev);
 	}
-	data->tint_data[tint_num].gpio_dev = NULL;
-	data->tint_data[tint_num].pin = UINT8_MAX;
+#endif /* CONFIG_RENESAS_RZ_EXT_IRQ */
 
 	return 0;
 }
 
 static int gpio_rz_int_enable(const struct device *int_dev, const struct device *gpio_dev,
-			      uint8_t tint_num, uint8_t irq_type, gpio_pin_t pin)
+			      uint8_t int_num, uint8_t irq_type, gpio_pin_t pin)
 {
-	struct gpio_rz_tint_data *int_data = int_dev->data;
+	if (irq_type == GPIO_RZ_INT_UNSUPPORTED) {
+		return -ENOTSUP;
+	}
+
 	const struct gpio_rz_config *gpio_config = gpio_dev->config;
-	volatile uint32_t *tssr = &R_INTC_IM33->TSSR0;
-	volatile uint32_t *titsr = &R_INTC_IM33->TITSR0;
 
-	tssr = &tssr[tint_num / 4];
-	titsr = &titsr[tint_num / 16];
+#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT)
+	volatile uint32_t *tssr = &R_INTC->TSSR0;
+	volatile uint32_t *titsr = &R_INTC->TITSR0;
+	struct gpio_rz_int_data *int_data = int_dev->data;
+
+	tssr = &tssr[int_num / 4];
+	titsr = &titsr[int_num / 16];
 	/* Select interrupt detect type. */
-	*titsr |= (irq_type << GPIO_RZ_TITSR_OFFSET(tint_num));
-	/* Select interrupt source base on port and pin number.*/
-	*tssr |= (GPIO_RZ_TSSR_VAL(gpio_config->port_num, pin)) << GPIO_RZ_TSSR_OFFSET(tint_num);
+	*titsr &= ~(3U << GPIO_RZ_TITSR_OFFSET(int_num));
+	*titsr |= (irq_type << GPIO_RZ_TITSR_OFFSET(int_num));
+	/* Select interrupt source base on port and pin number. */
+	*tssr |= (GPIO_RZ_TSSR_VAL(gpio_config->port_num, pin)) << GPIO_RZ_TSSR_OFFSET(int_num);
 
-	if (irq_type == GPIO_RZ_TINT_EDGE_RISING || irq_type == GPIO_RZ_TINT_EDGE_FALLING) {
-		int_data->irq_set_edge |= BIT(tint_num);
+	if (irq_type == GPIO_RZ_INT_EDGE_RISING || irq_type == GPIO_RZ_INT_EDGE_FALLING) {
+		int_data->irq_set_edge |= BIT(int_num);
 		/* Clear interrupt status. */
-		R_INTC_IM33->TSCR &= ~BIT(tint_num);
+		R_INTC->TSCR &= ~BIT(int_num);
+	}
+	irq_enable(GPIO_RZ_TINT_IRQ_GET(int_num));
+	int_data->gpio_mapping[int_num].gpio_dev = gpio_dev;
+	int_data->gpio_mapping[int_num].pin = pin;
+#elif defined(CONFIG_RENESAS_RZ_EXT_IRQ)
+	const struct device *eirq_dev = gpio_config->eirq_dev[pin];
+	struct gpio_rz_data *gpio_data = gpio_dev->data;
+
+	gpio_data->pin[int_num] = pin;
+	if (device_is_ready(eirq_dev)) {
+		intc_rz_ext_irq_set_type(eirq_dev, irq_type);
+		intc_rz_ext_irq_enable(eirq_dev);
+		intc_rz_ext_irq_set_callback(eirq_dev, gpio_config->cb_list[int_num],
+					     (void *)gpio_dev);
 	}
-	int_data->tint_data[tint_num].gpio_dev = gpio_dev;
-	int_data->tint_data[tint_num].pin = pin;
-	irq_enable(GPIO_RZ_TINT_IRQ_GET(tint_num));
+#endif /* CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT */
 
 	return 0;
 }
@@ -315,54 +379,56 @@ static int gpio_rz_pin_interrupt_configure(const struct device *dev, gpio_pin_t
 	const struct gpio_rz_config *config = dev->config;
 	struct gpio_rz_data *data = dev->data;
 	bsp_io_port_pin_t port_pin = config->fsp_port | pin;
-	uint8_t tint_num = config->tint_num[pin];
+	uint8_t int_num = config->int_num[pin];
 	uint8_t irq_type = 0;
-	gpio_flags_t pre_flags = 0;
+	struct gpio_rz_hw_config pre_flags;
 	k_spinlock_key_t key;
+	int ret = 0;
 
-	if (tint_num >= GPIO_RZ_MAX_TINT_NUM) {
-		LOG_DEV_ERR(dev, "Invalid TINT interrupt:%d >= %d", tint_num, GPIO_RZ_MAX_TINT_NUM);
+	if (int_num >= GPIO_RZ_MAX_INT_NUM) {
+		LOG_DEV_ERR(dev, "Invalid interrupt:%d >= %d", int_num, GPIO_RZ_MAX_INT_NUM);
 	}
 
 	if (pin > config->ngpios) {
 		return -EINVAL;
 	}
 
-	if (trig == GPIO_INT_TRIG_BOTH) {
-		return -ENOTSUP;
-	}
-
 	key = k_spin_lock(&data->lock);
 
 	if (mode == GPIO_INT_MODE_DISABLED) {
 		gpio_rz_pin_config_get_raw(port_pin, &pre_flags);
-		pre_flags |= GPIO_INT_DISABLE;
-		gpio_rz_pin_configure(dev, pin, pre_flags);
-		gpio_rz_int_disable(config->int_dev, tint_num);
+		pre_flags.p_pm |= GPIO_INT_DISABLE;
+		gpio_rz_pin_configure(dev, pin, pre_flags.p_pm);
+		gpio_rz_int_disable(config->int_dev, dev, int_num, pin);
 		goto exit_unlock;
 	}
 
 	if (mode == GPIO_INT_MODE_EDGE) {
-		irq_type = GPIO_RZ_TINT_EDGE_RISING;
 		if (trig == GPIO_INT_TRIG_LOW) {
-			irq_type = GPIO_RZ_TINT_EDGE_FALLING;
+			irq_type = GPIO_RZ_INT_EDGE_FALLING;
+		} else if (trig == GPIO_INT_TRIG_HIGH) {
+			irq_type = GPIO_RZ_INT_EDGE_RISING;
+		} else if (trig == GPIO_INT_TRIG_BOTH) {
+			irq_type = GPIO_RZ_INT_BOTH_EDGE;
 		}
 	} else {
-		irq_type = GPIO_RZ_TINT_LEVEL_HIGH;
 		if (trig == GPIO_INT_TRIG_LOW) {
-			irq_type = GPIO_RZ_TINT_LEVEL_LOW;
+			irq_type = GPIO_RZ_INT_LEVEL_LOW;
+		} else if (trig == GPIO_INT_TRIG_HIGH) {
+			irq_type = GPIO_RZ_INT_LEVEL_HIGH;
 		}
 	}
 
-	/* Set register ISEL */
-	gpio_rz_pin_config_get_raw(port_pin, &pre_flags);
-	pre_flags |= GPIO_INT_ENABLE;
-	gpio_rz_pin_configure(dev, pin, pre_flags);
-	gpio_rz_int_enable(config->int_dev, dev, tint_num, irq_type, pin);
+	ret = gpio_rz_int_enable(config->int_dev, dev, int_num, irq_type, pin);
+	if (ret == 0) {
+		gpio_rz_pin_config_get_raw(port_pin, &pre_flags);
+		pre_flags.p_pm |= GPIO_INT_ENABLE;
+		gpio_rz_pin_configure(dev, pin, pre_flags.p_pm);
+	}
 
 exit_unlock:
 	k_spin_unlock(&data->lock, key);
-	return 0;
+	return ret;
 }
 
 static int gpio_rz_manage_callback(const struct device *dev, struct gpio_callback *callback,
@@ -373,41 +439,37 @@ static int gpio_rz_manage_callback(const struct device *dev, struct gpio_callbac
 	return gpio_manage_callback(&data->cb, callback, set);
 }
 
-static void gpio_rz_isr(const struct device *dev, uint8_t pin)
-{
-	struct gpio_rz_data *data = dev->data;
-
-	gpio_fire_callbacks(&data->cb, dev, BIT(pin));
-}
-
-static void gpio_rz_tint_isr(uint16_t irq, const struct device *dev)
+static void gpio_rz_isr(uint16_t irq, void *param)
 {
-	struct gpio_rz_tint_data *data = dev->data;
-	volatile uint32_t *tscr = &R_INTC_IM33->TSCR;
-	uint8_t tint_num;
+#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT)
+	const struct device *dev = param;
+	struct gpio_rz_int_data *int_data = dev->data;
+	volatile uint32_t *tscr = &R_INTC->TSCR;
 
-	tint_num = irq - GPIO_RZ_TINT_IRQ_OFFSET;
-
-	if (!(*tscr & BIT(tint_num))) {
-		LOG_DEV_DBG(dev, "tint:%u spurious irq, status 0", tint_num);
+	if (!(*tscr & BIT(irq))) {
+		LOG_DEV_DBG(dev, "tint:%u spurious irq, status 0", irq);
 		return;
 	}
 
-	if (data->irq_set_edge & BIT(tint_num)) {
-		*tscr &= ~BIT(tint_num);
+	if (int_data->irq_set_edge & BIT(irq)) {
+		*tscr &= ~BIT(irq);
 	}
 
-	gpio_rz_isr(data->tint_data[tint_num].gpio_dev, data->tint_data[tint_num].pin);
-}
+	uint8_t pin = int_data->gpio_mapping[irq].pin;
+	const struct device *gpio_dev = int_data->gpio_mapping[irq].gpio_dev;
+	struct gpio_rz_data *gpio_data = gpio_dev->data;
 
-static int gpio_rz_int_init(const struct device *dev)
-{
-	const struct gpio_rz_tint_config *config = dev->config;
+	gpio_fire_callbacks(&gpio_data->cb, gpio_dev, BIT(pin));
+#elif defined(CONFIG_RENESAS_RZ_EXT_IRQ)
+	const struct device *gpio_dev = (const struct device *)param;
+	struct gpio_rz_data *gpio_data = gpio_dev->data;
+	uint8_t pin = gpio_data->pin[irq];
 
-	config->gpio_int_init();
-	return 0;
+	gpio_fire_callbacks(&gpio_data->cb, gpio_dev, BIT(pin));
+#endif /* CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT */
 }
-#endif
+
+#endif /* CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT || CONFIG_RENESAS_RZ_EXT_IRQ */
 
 static DEVICE_API(gpio, gpio_rz_driver_api) = {
 	.pin_configure = gpio_rz_pin_configure,
@@ -419,25 +481,37 @@ static DEVICE_API(gpio, gpio_rz_driver_api) = {
 	.port_set_bits_raw = gpio_rz_port_set_bits_raw,
 	.port_clear_bits_raw = gpio_rz_port_clear_bits_raw,
 	.port_toggle_bits = gpio_rz_port_toggle_bits,
-#if GPIO_RZ_HAS_INTERRUPT
+#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT) || defined(CONFIG_RENESAS_RZ_EXT_IRQ)
 	.pin_interrupt_configure = gpio_rz_pin_interrupt_configure,
 	.manage_callback = gpio_rz_manage_callback,
 #endif
 };
 
-/*Initialize GPIO interrupt device*/
-#define GPIO_RZ_TINT_ISR_DECLARE(irq_num, node_id)                                                 \
-	static void rz_gpio_isr_##irq_num(void *param)                                             \
+/* Initialize GPIO interrupt device */
+#define GPIO_RZ_ISR_DEFINE(irq_num, _)                                                             \
+	static void rz_gpio_isr##irq_num(void *param)                                              \
 	{                                                                                          \
-		gpio_rz_tint_isr(DT_IRQ_BY_IDX(node_id, irq_num, irq), param);                     \
+		gpio_rz_isr(irq_num, param);                                                       \
 	}
 
-#define GPIO_RZ_TINT_ISR_INIT(node_id, irq_num) LISTIFY(irq_num,                                   \
-							GPIO_RZ_TINT_ISR_DECLARE, (), node_id)
+#define GPIO_RZ_ALL_ISR_DEFINE(irq_num) LISTIFY(irq_num, GPIO_RZ_ISR_DEFINE, ())
+
+#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT) || defined(CONFIG_RENESAS_RZ_EXT_IRQ)
+#if defined(CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT)
+
+#define GPIO_RZ_INT_DEFINE(inst) .int_dev = DEVICE_DT_GET_OR_NULL(DT_INST(0, renesas_rz_gpio_int))
+
+static int gpio_rz_int_init(const struct device *dev)
+{
+	const struct gpio_rz_tint_config *config = dev->config;
+
+	config->gpio_int_init();
+	return 0;
+}
 
 #define GPIO_RZ_TINT_CONNECT(irq_num, node_id)                                                     \
 	IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, irq_num, irq),                                          \
-		    DT_IRQ_BY_IDX(node_id, irq_num, priority), rz_gpio_isr_##irq_num,              \
+		    DT_IRQ_BY_IDX(node_id, irq_num, priority), rz_gpio_isr##irq_num,               \
 		    DEVICE_DT_GET(node_id), 0);
 
 #define GPIO_RZ_TINT_CONNECT_FUNC(node_id)                                                         \
@@ -447,20 +521,47 @@ static DEVICE_API(gpio, gpio_rz_driver_api) = {
 			GPIO_RZ_TINT_CONNECT, (;),               \
 			node_id)                                 \
 	}
-/* Initialize GPIO device*/
+/* Initialize GPIO device */
 #define GPIO_RZ_INT_INIT(node_id)                                                                  \
-	GPIO_RZ_TINT_ISR_INIT(node_id, DT_NUM_IRQS(node_id))                                       \
+	GPIO_RZ_ALL_ISR_DEFINE(DT_NUM_IRQS(node_id))                                               \
 	GPIO_RZ_TINT_CONNECT_FUNC(node_id)                                                         \
 	static const struct gpio_rz_tint_config rz_gpio_tint_cfg_##node_id = {                     \
 		.gpio_int_init = rz_gpio_tint_connect_func##node_id,                               \
 	};                                                                                         \
-	static struct gpio_rz_tint_data rz_gpio_tint_data_##node_id = {};                          \
+	static struct gpio_rz_int_data rz_gpio_tint_data_##node_id = {};                           \
 	DEVICE_DT_DEFINE(node_id, gpio_rz_int_init, NULL, &rz_gpio_tint_data_##node_id,            \
 			 &rz_gpio_tint_cfg_##node_id, POST_KERNEL,                                 \
 			 UTIL_DEC(CONFIG_GPIO_INIT_PRIORITY), NULL);
-
 DT_FOREACH_STATUS_OKAY(renesas_rz_gpio_int, GPIO_RZ_INT_INIT)
 
+#elif defined(CONFIG_RENESAS_RZ_EXT_IRQ)
+
+GPIO_RZ_ALL_ISR_DEFINE(GPIO_RZ_MAX_INT_NUM)
+
+#define EIRQ_CB_GET(eirq_line, _) [eirq_line] = rz_gpio_isr##eirq_line
+
+#define EIRQ_DEV_LABEL_GET(inst, idx) CONCAT(irq, DT_INST_PROP_BY_IDX(inst, irqs, UTIL_INC(idx)))
+
+#define EIRQ_DEV_GET(idx, inst)                                                                    \
+	COND_CODE_1(DT_INST_PROP_HAS_IDX(inst, irqs, idx),                                         \
+		    ([DT_INST_PROP_BY_IDX(inst, irqs, idx)] =                                      \
+			     DEVICE_DT_GET_OR_NULL(DT_NODELABEL(EIRQ_DEV_LABEL_GET(inst, idx))),), \
+		    ())
+
+#define ALL_EIRQ_DEV_GET(inst)                                                                     \
+	FOR_EACH_FIXED_ARG(EIRQ_DEV_GET, (), inst,                                                 \
+			   LISTIFY(DT_INST_PROP_LEN_OR(inst, irqs, 0), VALUE_2X, (,)))
+
+#define GPIO_RZ_INT_DEFINE(inst)                                                                   \
+	.eirq_dev = {ALL_EIRQ_DEV_GET(inst)},                                                      \
+	.cb_list = {LISTIFY(GPIO_RZ_MAX_INT_NUM, EIRQ_CB_GET, (,))}
+
+#endif /* CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT */
+
+#else
+#define GPIO_RZ_INT_DEFINE(inst)
+#endif /* CONFIG_GPIO_RENESAS_RZ_HAS_GPIO_INTERRUPT || CONFIG_RENESAS_RZ_EXT_IRQ */
+
 #define VALUE_2X(i, _) UTIL_X2(i)
 #define PIN_IRQ_GET(idx, inst)                                                                     \
 	COND_CODE_1(DT_INST_PROP_HAS_IDX(inst, irqs, idx),                                         \
@@ -472,7 +573,7 @@ DT_FOREACH_STATUS_OKAY(renesas_rz_gpio_int, GPIO_RZ_INT_INIT)
 	FOR_EACH_FIXED_ARG(PIN_IRQ_GET, (), inst,                                                  \
 			   LISTIFY(DT_INST_PROP_LEN_OR(inst, irqs, 0), VALUE_2X, (,)))
 
-#define RZG_GPIO_PORT_INIT(inst)                                                                   \
+#define RZ_GPIO_PORT_INIT(inst)                                                                    \
 	static ioport_cfg_t g_ioport_##inst##_cfg = {                                              \
 		.number_of_pins = 0,                                                               \
 		.p_pin_cfg_data = NULL,                                                            \
@@ -489,9 +590,8 @@ DT_FOREACH_STATUS_OKAY(renesas_rz_gpio_int, GPIO_RZ_INT_INIT)
 		.ngpios = (uint8_t)DT_INST_PROP(inst, ngpios),                                     \
 		.fsp_cfg = &g_ioport_##inst##_cfg,                                                 \
 		.fsp_api = &g_ioport_on_ioport,                                                    \
-		.int_dev = DEVICE_DT_GET_OR_NULL(DT_INST(0, renesas_rz_gpio_int)),                 \
-		.tint_num = {PIN_IRQS_GET(inst)},                                                  \
-	};                                                                                         \
+		.int_num = {PIN_IRQS_GET(inst)},                                                   \
+		GPIO_RZ_INT_DEFINE(inst)};                                                         \
 	static ioport_instance_ctrl_t g_ioport_##inst##_ctrl;                                      \
 	static struct gpio_rz_data gpio_rz_##inst##_data = {                                       \
 		.fsp_ctrl = &g_ioport_##inst##_ctrl,                                               \
@@ -499,4 +599,4 @@ DT_FOREACH_STATUS_OKAY(renesas_rz_gpio_int, GPIO_RZ_INT_INIT)
 	DEVICE_DT_INST_DEFINE(inst, NULL, NULL, &gpio_rz_##inst##_data, &gpio_rz_##inst##_config,  \
 			      POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, &gpio_rz_driver_api);
 
-DT_INST_FOREACH_STATUS_OKAY(RZG_GPIO_PORT_INIT)
+DT_INST_FOREACH_STATUS_OKAY(RZ_GPIO_PORT_INIT)
diff --git a/drivers/gpio/gpio_renesas_rz.h b/drivers/gpio/gpio_renesas_rz.h
index 6980450f40c..c9570ef9e84 100644
--- a/drivers/gpio/gpio_renesas_rz.h
+++ b/drivers/gpio/gpio_renesas_rz.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,40 +7,126 @@
 #ifndef ZEPHYR_DRIVERS_GPIO_RENESAS_RZ_H_
 #define ZEPHYR_DRIVERS_GPIO_RENESAS_RZ_H_
 
-#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
 #include "r_ioport.h"
 
-#define GPIO_RZ_IOPORT_P_REG_BASE_GET  (&R_GPIO->P_20)
-#define GPIO_RZ_IOPORT_PM_REG_BASE_GET (&R_GPIO->PM_20)
+#define GPIO_RZ_INT_UNSUPPORTED 0xF
+
+#if defined(CONFIG_SOC_SERIES_RZG3S) || defined(CONFIG_SOC_SERIES_RZA3UL) ||                       \
+	defined(CONFIG_SOC_SERIES_RZV2L) || defined(CONFIG_SOC_SERIES_RZG2L)
+#include <zephyr/dt-bindings/gpio/renesas-rz-gpio.h>
+
+#if defined(CONFIG_SOC_SERIES_RZG3S)
+#define GPIO_RZ_IOPORT_P_REG_BASE_GET   (&R_GPIO->P_20)
+#define GPIO_RZ_IOPORT_PM_REG_BASE_GET  (&R_GPIO->PM_20)
+#define GPIO_RZ_IOPORT_PFC_REG_BASE_GET (&R_GPIO->PFC_20)
+#define GPIO_RZ_MAX_PORT_NUM            19
+#define GPIO_RZ_TINT_IRQ_OFFSET         429
+#define R_INTC                          R_INTC_IM33
+static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0,  4,  9,  13, 17, 23, 28, 33, 38, 43,
+							  47, 52, 56, 58, 63, 66, 70, 72, 76};
+
+#elif defined(CONFIG_SOC_SERIES_RZA3UL)
+#define GPIO_RZ_IOPORT_P_REG_BASE_GET   (&R_GPIO->P10)
+#define GPIO_RZ_IOPORT_PM_REG_BASE_GET  (&R_GPIO->PM10)
+#define GPIO_RZ_IOPORT_PFC_REG_BASE_GET (&R_GPIO->PFC10)
+#define GPIO_RZ_MAX_PORT_NUM            19
+#define GPIO_RZ_TINT_IRQ_OFFSET         476
+#define R_INTC                          R_INTC_IA55
+static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0,  4,  9,  13, 17, 23, 28, 33, 38, 43,
+							  47, 52, 56, 58, 63, 66, 70, 72, 76};
+
+#elif defined(CONFIG_SOC_SERIES_RZV2L) || defined(CONFIG_SOC_SERIES_RZG2L)
+#define GPIO_RZ_IOPORT_P_REG_BASE_GET   (&R_GPIO->P10)
+#define GPIO_RZ_IOPORT_PM_REG_BASE_GET  (&R_GPIO->PM10)
+#define GPIO_RZ_IOPORT_PFC_REG_BASE_GET (&R_GPIO->PFC10)
+#define GPIO_RZ_MAX_PORT_NUM            49
+#define GPIO_RZ_TINT_IRQ_OFFSET         444
+#define R_INTC                          R_INTC_IM33
+static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {
+	0,  2,  4,  6,  8,  10, 13, 15, 18, 21, 24,  25,  27,  29,  32, 34, 36,
+	38, 41, 43, 45, 48, 50, 52, 54, 56, 58, 60,  62,  64,  66,  68, 70, 72,
+	74, 76, 78, 80, 83, 85, 88, 91, 93, 98, 102, 106, 110, 114, 118};
+#endif
+
+#define GPIO_RZ_IOPORT_P_REG_GET(port, pin)   (&GPIO_RZ_IOPORT_P_REG_BASE_GET[port])
+#define GPIO_RZ_IOPORT_PM_REG_GET(port, pin)  (&GPIO_RZ_IOPORT_PM_REG_BASE_GET[port])
+#define GPIO_RZ_IOPORT_PFC_REG_GET(port, pin) (&GPIO_RZ_IOPORT_PFC_REG_BASE_GET[port])
 
-#define GPIO_RZ_REG_OFFSET(port, pin) (port + (pin / 4))
+#define GPIO_RZ_P_VALUE_GET(value, pin)   ((value >> pin) & 1U)
+#define GPIO_RZ_PM_VALUE_GET(value, pin)  ((value >> (pin * 2)) & 3U)
+#define GPIO_RZ_PFC_VALUE_GET(value, pin) ((value >> (pin * 4)) & 0xF)
 
-#define GPIO_RZ_P_VALUE_GET(value, pin)  ((value >> pin) & 1U)
-#define GPIO_RZ_PM_VALUE_GET(value, pin) ((value >> (pin * 2)) & 3U)
+#define GPIO_RZ_IOPORT_PFC_SET(value) (value << 24)
 
-#define GPIO_RZ_MAX_PORT_NUM 19
-#define GPIO_RZ_MAX_TINT_NUM 32
+#define GPIO_RZ_PIN_DISCONNECT(port, pin) /* do nothing */
+
+#define GPIO_RZ_MAX_INT_NUM 32
 
-#define GPIO_RZ_TINT_IRQ_OFFSET        429
 #define GPIO_RZ_TINT_IRQ_GET(tint_num) (tint_num + GPIO_RZ_TINT_IRQ_OFFSET)
 
-#define GPIO_RZ_TINT_EDGE_RISING  0x0
-#define GPIO_RZ_TINT_EDGE_FALLING 0x1
-#define GPIO_RZ_TINT_LEVEL_HIGH   0x2
-#define GPIO_RZ_TINT_LEVEL_LOW    0x3
+#define GPIO_RZ_INT_EDGE_RISING  0x0
+#define GPIO_RZ_INT_EDGE_FALLING 0x1
+#define GPIO_RZ_INT_LEVEL_HIGH   0x2
+#define GPIO_RZ_INT_LEVEL_LOW    0x3
+#define GPIO_RZ_INT_BOTH_EDGE    GPIO_RZ_INT_UNSUPPORTED
 
 #define GPIO_RZ_TSSR_VAL(port, pin) (0x80 | (gpio_rz_int[port] + pin))
 #define GPIO_RZ_TSSR_OFFSET(irq)    ((irq % 4) * 8)
 #define GPIO_RZ_TITSR_OFFSET(irq)   ((irq % 16) * 2)
 
-#define GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flag) (((flags >> RZG3S_GPIO_FILTER_SHIFT) & 0x1F) << 19U)
-#define GPIO_RZ_PIN_CONFIGURE_GET_DRIVE_ABILITY(flag)                                              \
-	(((flag >> RZG3S_GPIO_IOLH_SHIFT) & 0x3) << 10U)
+#define GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flag) (((flags >> RZ_GPIO_FILTER_SHIFT) & 0x1F) << 19U)
+#define GPIO_RZ_PIN_CONFIGURE_GET(flag)        (((flag >> RZ_GPIO_IOLH_SHIFT) & 0x3) << 10U)
 
 #define GPIO_RZ_PIN_CONFIGURE_INT_ENABLE         IOPORT_CFG_TINT_ENABLE
 #define GPIO_RZ_PIN_CONFIGURE_INT_DISABLE        (~(IOPORT_CFG_TINT_ENABLE))
 #define GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET (~(0x3 << 2))
+#define GPIO_RZ_PIN_SPECIAL_FLAG_GET(flag)       GPIO_RZ_PIN_CONFIGURE_GET_FILTER(flag)
+
+#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) ||                      \
+	defined(CONFIG_SOC_SERIES_RZT2M)
+#include <zephyr/dt-bindings/gpio/renesas-rztn-gpio.h>
+#define GPIO_RZ_IOPORT_REG_REGION_GET(p) (R_BSP_IoRegionGet(p) == BSP_IO_REGION_NOT_SAFE ? 1 : 0)
+
+#define GPIO_RZ_IOPORT_P_REG_BASE_GET(port, pin)                                                   \
+	(GPIO_RZ_IOPORT_REG_REGION_GET((port << 8U) | pin) == 1 ? &R_PORT_NSR->P[port]             \
+								: &R_PORT_SR->P[port])
+
+#define GPIO_RZ_IOPORT_PM_REG_BASE_GET(port, pin)                                                  \
+	(GPIO_RZ_IOPORT_REG_REGION_GET((port << 8U) | pin) == 1 ? &R_PORT_NSR->PM[port]            \
+								: &R_PORT_SR->PM[port])
+
+#define GPIO_RZ_IOPORT_PFC_REG_BASE_GET(port, pin)                                                 \
+	(GPIO_RZ_IOPORT_REG_REGION_GET((port << 8U) | pin) == 1 ? &R_PORT_NSR->PFC[port]           \
+								: &R_PORT_SR->PFC[port])
+
+#define GPIO_RZ_IOPORT_P_REG_GET(port, pin)   (GPIO_RZ_IOPORT_P_REG_BASE_GET(port, pin))
+#define GPIO_RZ_IOPORT_PM_REG_GET(port, pin)  (GPIO_RZ_IOPORT_PM_REG_BASE_GET(port, pin))
+#define GPIO_RZ_IOPORT_PFC_REG_GET(port, pin) (GPIO_RZ_IOPORT_PFC_REG_BASE_GET(port, pin))
+
+#define GPIO_RZ_P_VALUE_GET(value, pin)   ((value >> pin) & 1U)
+#define GPIO_RZ_PM_VALUE_GET(value, pin)  ((value >> (pin * 2)) & 3U)
+#define GPIO_RZ_PFC_VALUE_GET(value, pin) ((value >> (pin * 4)) & 0xF)
+
+#define GPIO_RZ_IOPORT_PFC_SET(value) (value << 4)
+
+#define GPIO_RZ_PIN_DISCONNECT(port, pin)                                                          \
+	*GPIO_RZ_IOPORT_PM_REG_GET((port >> 8U), pin) &= ~(3U << (pin * 2))
+
+#define GPIO_RZ_MAX_INT_NUM 16
+
+#define GPIO_RZ_INT_EDGE_FALLING 0x0
+#define GPIO_RZ_INT_EDGE_RISING  0x1
+#define GPIO_RZ_INT_BOTH_EDGE    0x2
+#define GPIO_RZ_INT_LEVEL_LOW    0x3
+#define GPIO_RZ_INT_LEVEL_HIGH   GPIO_RZ_INT_UNSUPPORTED
+
+#define GPIO_RZ_PIN_CONFIGURE_GET(flag) (((flag >> RZTN_GPIO_DRCTL_SHIFT) & 0x33) << 8U)
+
+#define GPIO_RZ_PIN_CONFIGURE_INT_ENABLE         (1U << 3)
+#define GPIO_RZ_PIN_CONFIGURE_INT_DISABLE        (~(1U << 3))
+#define GPIO_RZ_PIN_CONFIGURE_INPUT_OUTPUT_RESET (~(0x3 << 2))
+#define GPIO_RZ_PIN_SPECIAL_FLAG_GET(flag)       IOPORT_CFG_REGION_NSAFETY
+
+#endif /* CONFIG_SOC_* */
 
-static const uint8_t gpio_rz_int[GPIO_RZ_MAX_PORT_NUM] = {0,  4,  9,  13, 17, 23, 28, 33, 38, 43,
-							  47, 52, 56, 58, 63, 66, 70, 72, 76};
 #endif /* ZEPHYR_DRIVERS_GPIO_RENESAS_RZ_H_ */
diff --git a/drivers/gpio/gpio_renesas_rza2m.c b/drivers/gpio/gpio_renesas_rza2m.c
new file mode 100644
index 00000000000..ceba683ecaf
--- /dev/null
+++ b/drivers/gpio/gpio_renesas_rza2m.c
@@ -0,0 +1,558 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_rza2m_gpio
+
+#include <zephyr/drivers/gpio/gpio_utils.h>
+#include <zephyr/drivers/interrupt_controller/gic.h>
+#include <zephyr/dt-bindings/gpio/renesas-rza2m-gpio.h>
+#include <zephyr/logging/log.h>
+#include "gpio_renesas_rza2m.h"
+
+LOG_MODULE_REGISTER(rza2m_gpio, CONFIG_GPIO_LOG_LEVEL);
+
+/* clang-format off */
+static const struct device *gpio_port_devs[] = {
+	DT_FOREACH_CHILD_STATUS_OKAY_SEP(DT_PARENT(DT_DRV_INST(0)), DEVICE_DT_GET, (,))};
+
+static const uint32_t gpio_port_regs[] = {
+	DT_FOREACH_CHILD_STATUS_OKAY_SEP(DT_PARENT(DT_DRV_INST(0)), DT_REG_ADDR, (,))};
+/* clang-format on */
+
+/* TINT pin map (According to the Table 51.37 of HW manual) */
+static const gpio_rza2m_port_tint_map_t gpio_rza2m_port_tint_map[] = {
+	{TINT31, {PORT0, UNUSED_PORT}, {0x7F, UNUSED_MASK}},
+	{TINT30, {PORT1, UNUSED_PORT}, {0x1F, UNUSED_MASK}},
+	{TINT29, {PORT2, PORT3}, {0x0F, 0x01}},
+	{TINT28, {PORT3, PORT4}, {0x3E, 0x01}},
+	{TINT27, {PORT4, UNUSED_PORT}, {0xFE, UNUSED_MASK}},
+	{TINT26, {PORT5, UNUSED_PORT}, {0x0F, UNUSED_MASK}},
+	{TINT25, {PORT5, UNUSED_PORT}, {0xF0, UNUSED_MASK}},
+	{TINT24, {PORT6, UNUSED_PORT}, {0x0F, UNUSED_MASK}},
+	{TINT23, {PORT6, UNUSED_PORT}, {0xF0, UNUSED_MASK}},
+	{TINT22, {PORT7, UNUSED_PORT}, {0x0F, UNUSED_MASK}},
+	{TINT21, {PORT7, UNUSED_PORT}, {0xF0, UNUSED_MASK}},
+	{TINT20, {PORT8, UNUSED_PORT}, {0x0F, UNUSED_MASK}},
+	{TINT19, {PORT8, UNUSED_PORT}, {0xF0, UNUSED_MASK}},
+	{TINT18, {PORT9, UNUSED_PORT}, {0x0F, UNUSED_MASK}},
+	{TINT17, {PORT9, UNUSED_PORT}, {0xF0, UNUSED_MASK}},
+	{TINT16, {PORTA, UNUSED_PORT}, {0x0F, UNUSED_MASK}},
+	{TINT15, {PORTA, UNUSED_PORT}, {0xF0, UNUSED_MASK}},
+	{TINT14, {PORTB, UNUSED_PORT}, {0x3F, UNUSED_MASK}},
+	{TINT13, {PORTC, UNUSED_PORT}, {0x0F, UNUSED_MASK}},
+	{TINT12, {PORTC, UNUSED_PORT}, {0xF0, UNUSED_MASK}},
+	{TINT11, {PORTD, UNUSED_PORT}, {0x0F, UNUSED_MASK}},
+	{TINT10, {PORTD, UNUSED_PORT}, {0xF0, UNUSED_MASK}},
+	{TINT9, {PORTE, UNUSED_PORT}, {0x7F, UNUSED_MASK}},
+	{TINT8, {PORTF, UNUSED_PORT}, {0x0F, UNUSED_MASK}},
+	{TINT7, {PORTF, UNUSED_PORT}, {0xF0, UNUSED_MASK}},
+	{TINT6, {PORTG, UNUSED_PORT}, {0x0F, UNUSED_MASK}},
+	{TINT5, {PORTG, UNUSED_PORT}, {0xF0, UNUSED_MASK}},
+	{TINT4, {PORTH, UNUSED_PORT}, {0x7F, UNUSED_MASK}},
+	{TINT3, {PORTJ, UNUSED_PORT}, {0x0F, UNUSED_MASK}},
+	{TINT2, {PORTJ, UNUSED_PORT}, {0xF0, UNUSED_MASK}},
+	{TINT1, {PORTK, UNUSED_PORT}, {0x3F, UNUSED_MASK}},
+	{TINT0, {PORTL, PORTM}, {0x1F, 0x01}}};
+
+static int gpio_rza2m_get_pin_interrupt_line(uint32_t port, uint8_t pin)
+{
+	int i, j;
+
+	for (i = 0; i < ARRAY_SIZE(gpio_rza2m_port_tint_map); i++) {
+		for (j = 0; j < RZA2M_MAX_PORTS_PER_TINT; j++) {
+			if (port == gpio_rza2m_port_tint_map[i].ports[j] &&
+			    (gpio_rza2m_port_tint_map[i].masks[j] & BIT(pin))) {
+				return gpio_rza2m_port_tint_map[i].tint;
+			}
+		}
+	}
+
+	return -ENOTSUP;
+}
+
+static uint8_t gpio_rza2m_port_get_output(const struct device *port_dev)
+{
+	const struct gpio_rza2m_port_config *config = port_dev->config;
+	const struct device *int_dev = config->int_dev;
+	uint8_t port = config->port;
+
+	return sys_read8(RZA2M_PODR(int_dev, port));
+}
+
+static void gpio_rza2m_port_write(const struct device *port_dev, uint8_t value)
+{
+	const struct gpio_rza2m_port_config *config = port_dev->config;
+	const struct device *int_dev = config->int_dev;
+	uint8_t port = config->port;
+
+	sys_write8(value, RZA2M_PODR(int_dev, port));
+}
+
+static int gpio_rza2m_port_set_bits_raw(const struct device *port_dev, gpio_port_pins_t pins)
+{
+	uint8_t base_value = gpio_rza2m_port_get_output(port_dev);
+
+	gpio_rza2m_port_write(port_dev, (base_value | pins));
+
+	return 0;
+}
+
+static int gpio_rza2m_port_clear_bits_raw(const struct device *port_dev, gpio_port_pins_t pins)
+{
+	uint8_t base_value = gpio_rza2m_port_get_output(port_dev);
+
+	gpio_rza2m_port_write(port_dev, (base_value & ~pins));
+
+	return 0;
+}
+
+static void gpio_rza2m_pin_configure_as_gpio(const struct device *port_dev, uint8_t pin,
+					     uint8_t dir)
+{
+	uint16_t mask16;
+	uint16_t reg16;
+	uint8_t reg8;
+	const struct gpio_rza2m_port_config *config = port_dev->config;
+	const struct device *int_dev = config->int_dev;
+	uint8_t port = config->port;
+
+	/* Set pin direction */
+	reg16 = sys_read16(RZA2M_PDR(int_dev, port));
+	mask16 = RZA2M_PDR_MASK << (pin * 2);
+	reg16 &= ~mask16;
+	reg16 |= dir << (pin * 2);
+	sys_write16(reg16, RZA2M_PDR(int_dev, port));
+
+	/* Select general I/O pin function */
+	reg8 = sys_read8(RZA2M_PMR(int_dev, port));
+	reg8 &= ~BIT(pin);
+	sys_write8(reg8, RZA2M_PMR(int_dev, port));
+}
+
+static void gpio_rza2m_set_pin_mux_protection(const struct device *port_dev, bool protect)
+{
+	const struct gpio_rza2m_port_config *config = port_dev->config;
+	const struct device *int_dev = config->int_dev;
+	uint8_t reg_value = sys_read8(RZA2M_PWPR(int_dev));
+
+	if (protect) {
+		reg_value &= ~RZA2M_PWPR_PFSWE_MASK;
+		sys_write8(reg_value, RZA2M_PWPR(int_dev));
+
+		reg_value |= RZA2M_PWPR_B0WI_MASK;
+		sys_write8(reg_value, RZA2M_PWPR(int_dev));
+	} else {
+		reg_value &= ~RZA2M_PWPR_B0WI_MASK;
+		sys_write8(reg_value, RZA2M_PWPR(int_dev));
+
+		reg_value |= RZA2M_PWPR_PFSWE_MASK;
+		sys_write8(reg_value, RZA2M_PWPR(int_dev));
+	}
+}
+
+static void gpio_rza2m_set_pin_int(const struct device *port_dev, uint8_t pin, bool int_en)
+{
+	uint8_t value;
+	const struct gpio_rza2m_port_config *config = port_dev->config;
+	const struct device *int_dev = config->int_dev;
+	uint8_t port = config->port;
+
+	/* PFS Register Write Protect : OFF */
+	gpio_rza2m_set_pin_mux_protection(port_dev, false);
+
+	value = sys_read8(RZA2M_PFS(int_dev, port, pin));
+	if (int_en) {
+		value |= RZA2M_PFS_ISEL_MASK;
+	} else {
+		value &= ~RZA2M_PFS_ISEL_MASK;
+	}
+	sys_write8(value, RZA2M_PFS(int_dev, port, pin));
+
+	/* PFS Register Write Protect : ON */
+	gpio_rza2m_set_pin_mux_protection(port_dev, true);
+}
+
+static void rza2m_configure_interrupt_line(int tint_num, enum gpio_rza2m_tint_sense sense)
+{
+	mm_reg_t reg;
+	uint32_t mask;
+	uint32_t reg_val;
+
+	if (tint_num >= TINT16) {
+		reg = RZA2M_GICD_ICFGR31;
+	} else {
+		reg = RZA2M_GICD_ICFGR30;
+	}
+
+	mask = (1u << (((tint_num % 16u) * 2u) + 1u));
+
+	reg_val = sys_read32(reg);
+	reg_val &= ~mask;
+	if (sense == RZA2M_GPIO_TINT_SENSE_RISING_EDGE) {
+		reg_val |= mask;
+	}
+	sys_write32(reg_val, reg);
+	sys_read32(reg);
+
+	irq_enable(tint_num);
+}
+
+/*
+ * GPIO HIGH is only possible for
+ * PG_2, PG_3, PG_4, PG_5, PG_6, PG_7, PJ_0, PJ_1, PJ_2, PJ_3, PJ_4, PJ_5, and PJ_6
+ * see 51.3.5 section of HW Manual
+ */
+static const gpio_rza2m_high_allowed_pin_t allowed_gpio_high_pins[] = {
+	{PORTG, 0xFC}, /* 0xFC = 0b11111100 for bits 2-7 */
+	{PORTJ, 0x7F}, /* 0x7F = 0b01111111 for bits 0-6 */
+};
+
+static bool is_gpio_high_allowed(uint8_t port, uint8_t pin)
+{
+	int num_allowed_pins = ARRAY_SIZE(allowed_gpio_high_pins);
+	int i;
+
+	for (i = 0; i < num_allowed_pins; i++) {
+		if (allowed_gpio_high_pins[i].port == port &&
+		    (allowed_gpio_high_pins[i].mask & BIT(pin))) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+static int gpio_rza2m_pin_drive_set(const struct device *port_dev, uint8_t pin, gpio_flags_t flags)
+{
+	uint16_t reg16;
+	uint16_t mask16;
+	const struct gpio_rza2m_port_config *config = port_dev->config;
+	const struct device *int_dev = config->int_dev;
+	uint8_t port = config->port;
+	uint8_t drive_strength;
+
+	if (flags & RZA2M_GPIO_DRIVE_HIGH) {
+		if (!is_gpio_high_allowed(port, pin)) {
+			return -ENOTSUP;
+		}
+		drive_strength = RZA2M_GPIO_DRIVE_STRENGTH_HIGH;
+	} else {
+		drive_strength = RZA2M_GPIO_DRIVE_STRENGTH_NORMAL;
+	}
+
+	reg16 = sys_read16(RZA2M_DSCR(int_dev, port));
+	mask16 = RZA2M_DSCR_MASK << (pin * 2);
+	reg16 &= ~mask16;
+	reg16 |= drive_strength << (pin * 2);
+
+	sys_write16(reg16, RZA2M_DSCR(int_dev, port));
+
+	return 0;
+}
+
+static int gpio_rza2m_pin_interrupt_configure(const struct device *port_dev, gpio_pin_t pin,
+					      enum gpio_int_mode mode, enum gpio_int_trig trig)
+{
+	const struct gpio_rza2m_port_config *config = port_dev->config;
+	struct gpio_rza2m_port_data *data = port_dev->data;
+	enum gpio_rza2m_tint_sense sense;
+	int tint_num;
+
+	/* Validate pin */
+	if (pin >= config->ngpios) {
+		return -EINVAL;
+	}
+
+	/* Map mode and trigger to sense */
+	switch (mode) {
+	case GPIO_INT_MODE_EDGE:
+		if (trig != GPIO_INT_TRIG_HIGH) {
+			return -ENOTSUP;
+		}
+		sense = RZA2M_GPIO_TINT_SENSE_RISING_EDGE;
+		break;
+
+	case GPIO_INT_MODE_LEVEL:
+		if (trig != GPIO_INT_TRIG_HIGH) {
+			return -ENOTSUP;
+		}
+		sense = RZA2M_GPIO_TINT_SENSE_HIGH_LEVEL;
+		break;
+
+	case GPIO_INT_MODE_DISABLED:
+		data->mask_irq_en &= ~BIT(pin);
+		gpio_rza2m_set_pin_int(port_dev, pin, false);
+		return 0;
+
+	default:
+		return -EINVAL;
+	}
+
+	/* Enable interrupt */
+	data->mask_irq_en |= BIT(pin);
+
+	tint_num = gpio_rza2m_get_pin_interrupt_line(config->port, pin);
+	if (tint_num < 0) {
+		return tint_num;
+	}
+
+	rza2m_configure_interrupt_line(tint_num, sense);
+	gpio_rza2m_set_pin_int(port_dev, pin, true);
+
+	return 0;
+}
+
+static int gpio_rza2m_pin_configure(const struct device *port_dev, gpio_pin_t pin,
+				    gpio_flags_t flags)
+{
+	int ret = 0;
+	const struct gpio_rza2m_port_config *config = port_dev->config;
+
+	if (pin >= config->ngpios) {
+		LOG_ERR("provided pin %d > %d (ngpios)", pin, config->ngpios);
+		return -EINVAL;
+	}
+
+	if ((flags & GPIO_PULL_UP) || (flags & GPIO_PULL_DOWN)) {
+		return -ENOTSUP;
+	}
+
+	/* Configure pin direction */
+	if (flags & GPIO_OUTPUT) {
+		gpio_rza2m_pin_configure_as_gpio(port_dev, pin, RZA2M_PDR_OUTPUT);
+	} else if (flags & GPIO_INPUT) {
+		gpio_rza2m_pin_configure_as_gpio(port_dev, pin, RZA2M_PDR_INPUT);
+	} else {
+		return -ENOTSUP;
+	}
+
+	/* Configure pin drive strength */
+	ret = gpio_rza2m_pin_drive_set(port_dev, pin, flags);
+	if (ret) {
+		LOG_ERR("unable to set gpio drive level");
+		return ret;
+	}
+
+	/* Configure pin initial value */
+	if (flags & GPIO_OUTPUT_INIT_HIGH) {
+		ret = gpio_rza2m_port_set_bits_raw(port_dev, BIT(pin));
+	} else if (flags & GPIO_OUTPUT_INIT_LOW) {
+		ret = gpio_rza2m_port_clear_bits_raw(port_dev, BIT(pin));
+	}
+
+	/* Configure pin interrupt */
+	if (flags & GPIO_INT_ENABLE) {
+		if (flags & GPIO_INT_LOW_0) {
+			return -ENOTSUP;
+		}
+
+		enum gpio_int_mode mode =
+			(flags & GPIO_INT_EDGE) ? GPIO_INT_MODE_EDGE : GPIO_INT_MODE_LEVEL;
+		enum gpio_int_trig trig = GPIO_INT_TRIG_HIGH;
+
+		ret = gpio_rza2m_pin_interrupt_configure(port_dev, pin, mode, trig);
+	} else if (flags & GPIO_INT_DISABLE) {
+		ret = gpio_rza2m_pin_interrupt_configure(port_dev, pin, GPIO_INT_MODE_DISABLED,
+							 GPIO_INT_TRIG_HIGH);
+	}
+
+	return ret;
+}
+
+#ifdef CONFIG_GPIO_GET_CONFIG
+static int gpio_rza2m_pin_get_config(const struct device *port_dev, gpio_pin_t pin,
+				     gpio_flags_t *flags)
+{
+	const struct gpio_rza2m_port_config *config = port_dev->config;
+	const struct device *int_dev = config->int_dev;
+	uint8_t port = config->port;
+	uint16_t mask16;
+	uint16_t reg16;
+	uint8_t reg8;
+
+	/* Get pin direction */
+	reg16 = sys_read16(RZA2M_PDR(int_dev, port));
+	mask16 = RZA2M_PDR_MASK << (pin * 2);
+	reg16 &= mask16;
+	if ((reg16 >> (pin * 2)) == RZA2M_PDR_INPUT) {
+		*flags |= GPIO_INPUT;
+	} else if ((reg16 >> (pin * 2)) == RZA2M_PDR_OUTPUT) {
+		*flags |= GPIO_OUTPUT;
+	}
+
+	/* Get pin initial value */
+	reg8 = sys_read8(RZA2M_PODR(int_dev, port));
+	if (reg8 & BIT(pin)) {
+		*flags |= GPIO_OUTPUT_INIT_HIGH;
+	} else {
+		*flags |= GPIO_OUTPUT_INIT_LOW;
+	}
+
+	/* Get pin drive strength */
+	reg16 = sys_read16(RZA2M_DSCR(int_dev, port));
+	mask16 = RZA2M_DSCR_MASK << (pin * 2);
+	reg16 &= mask16;
+	if ((reg16 >> (pin * 2)) == RZA2M_GPIO_DRIVE_STRENGTH_HIGH) {
+		*flags |= RZA2M_GPIO_DRIVE_HIGH;
+	}
+
+	return 0;
+}
+#endif
+
+static int gpio_rza2m_port_get_raw(const struct device *port_dev, gpio_port_value_t *value)
+{
+	const struct gpio_rza2m_port_config *config = port_dev->config;
+	const struct device *int_dev = config->int_dev;
+	uint8_t port = config->port;
+
+	*value = sys_read8(RZA2M_PIDR(int_dev, port));
+
+	return 0;
+}
+
+static int gpio_rza2m_port_set_masked_raw(const struct device *port_dev, gpio_port_pins_t mask,
+					  gpio_port_value_t value)
+{
+	uint8_t base_value = gpio_rza2m_port_get_output(port_dev);
+
+	gpio_rza2m_port_write(port_dev, (base_value & ~mask) | (value & mask));
+
+	return 0;
+}
+
+static int gpio_rza2m_port_toggle_bits(const struct device *port_dev, gpio_port_pins_t pins)
+{
+	uint8_t base_value = gpio_rza2m_port_get_output(port_dev);
+
+	gpio_rza2m_port_write(port_dev, (base_value ^ pins));
+
+	return 0;
+}
+
+static int gpio_rza2m_manage_callback(const struct device *port_dev, struct gpio_callback *callback,
+				      bool set)
+{
+	struct gpio_rza2m_port_data *data = port_dev->data;
+
+	gpio_manage_callback(&data->callbacks, callback, set);
+
+	return 0;
+}
+
+static DEVICE_API(gpio, gpio_rza2m_driver_api) = {
+	.pin_configure = gpio_rza2m_pin_configure,
+#ifdef CONFIG_GPIO_GET_CONFIG
+	.pin_get_config = gpio_rza2m_pin_get_config,
+#endif
+	.port_get_raw = gpio_rza2m_port_get_raw,
+	.port_set_masked_raw = gpio_rza2m_port_set_masked_raw,
+	.port_set_bits_raw = gpio_rza2m_port_set_bits_raw,
+	.port_clear_bits_raw = gpio_rza2m_port_clear_bits_raw,
+	.port_toggle_bits = gpio_rza2m_port_toggle_bits,
+	.pin_interrupt_configure = gpio_rza2m_pin_interrupt_configure,
+	.manage_callback = gpio_rza2m_manage_callback,
+};
+
+static void gpio_rza2m_isr_common(uint16_t idx)
+{
+	gpio_port_value_t value;
+
+	for (int j = 0; j < RZA2M_MAX_PORTS_PER_TINT; j++) {
+		uint32_t port = gpio_rza2m_port_tint_map[idx].ports[j];
+		uint16_t mask = gpio_rza2m_port_tint_map[idx].masks[j];
+
+		if (port == UNUSED_PORT) {
+			continue;
+		}
+
+		for (int i = 0; i < ARRAY_SIZE(gpio_port_regs); i++) {
+			if (gpio_port_regs[i] == port) {
+				const struct device *port_dev = gpio_port_devs[i];
+				struct gpio_rza2m_port_data *data = port_dev->data;
+				int pin;
+
+				gpio_rza2m_port_get_raw(port_dev, &value);
+				pin = find_lsb_set(data->mask_irq_en & (value & mask)) - 1;
+
+				if (pin >= 0) {
+					gpio_fire_callbacks(&data->callbacks, port_dev, BIT(pin));
+				}
+				break;
+			}
+		}
+	}
+}
+
+static int gpio_rza2m_int_init(const struct device *dev)
+{
+	const struct gpio_rza2m_tint_config *config = dev->config;
+
+	DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
+	config->gpio_int_init();
+
+	return 0;
+}
+
+static int gpio_rza2m_port_init(const struct device *port_dev)
+{
+	return 0;
+}
+
+#define GPIO_RZA2M_IRQ_DECLARE_ISR(irq_idx, node_id)                                               \
+	static void gpio_rza2m_##irq_idx##_isr(void *param)                                        \
+	{                                                                                          \
+		int idx = (ARRAY_SIZE(gpio_rza2m_port_tint_map) + TINT0) -                         \
+			  (DT_IRQ_BY_IDX(node_id, irq_idx, irq) - GIC_SPI_INT_BASE) - 1;           \
+                                                                                                   \
+		gpio_rza2m_isr_common(idx);                                                        \
+	}
+
+#define GPIO_RZA2M_DECLARE_ALL_IRQS(node_id)                                                       \
+	LISTIFY(DT_NUM_IRQS(node_id), GPIO_RZA2M_IRQ_DECLARE_ISR, (;), node_id)
+
+#define GPIO_RZA2M_TINT_CONNECT(irq_idx, node_id)                                                  \
+	IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, irq_idx, irq) - GIC_SPI_INT_BASE,                       \
+		    DT_IRQ_BY_IDX(node_id, irq_idx, priority), gpio_rza2m_##irq_idx##_isr, NULL,   \
+		    DT_IRQ_BY_IDX(node_id, irq_idx, flags));
+
+#define GPIO_RZA2M_TINT_CONNECT_FUNC(node_id)                                                      \
+	static void gpio_rza2m_tint_connect_func##node_id(void)                                    \
+	{                                                                                          \
+		LISTIFY(DT_NUM_IRQS(node_id),                                   \
+			GPIO_RZA2M_TINT_CONNECT, (;), node_id)                  \
+	}
+
+#define GPIO_RZA2M_INT_INIT(node_id)                                                               \
+	GPIO_RZA2M_DECLARE_ALL_IRQS(node_id)                                                       \
+	GPIO_RZA2M_TINT_CONNECT_FUNC(node_id)                                                      \
+	static const struct gpio_rza2m_tint_config gpio_rza2m_tint_cfg_##node_id = {               \
+		DEVICE_MMIO_ROM_INIT(DT_PARENT(DT_INST(0, renesas_rza2m_gpio_int))),               \
+		.gpio_int_init = gpio_rza2m_tint_connect_func##node_id,                            \
+	};                                                                                         \
+	static struct gpio_rza2m_tint_data gpio_rza2m_tint_data_##node_id;                         \
+	DEVICE_DT_DEFINE(node_id, gpio_rza2m_int_init, NULL, &gpio_rza2m_tint_data_##node_id,      \
+			 &gpio_rza2m_tint_cfg_##node_id, POST_KERNEL,                              \
+			 UTIL_DEC(CONFIG_GPIO_INIT_PRIORITY), NULL);
+
+#define GPIO_RZA2M_PORT_INIT(inst)                                                                 \
+	static const struct gpio_rza2m_port_config gpio_rza2m_cfg_##inst = {                       \
+		.common =                                                                          \
+			{                                                                          \
+				.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(inst),            \
+			},                                                                         \
+		.port = DT_INST_REG_ADDR(inst),                                                    \
+		.ngpios = DT_INST_PROP(inst, ngpios),                                              \
+		.int_dev = DEVICE_DT_GET_OR_NULL(DT_INST(0, renesas_rza2m_gpio_int)),              \
+	};                                                                                         \
+	static struct gpio_rza2m_port_data gpio_rza2m_data_##inst = {.mask_irq_en = 0};            \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(inst, gpio_rza2m_port_init, NULL, &gpio_rza2m_data_##inst,           \
+			      &gpio_rza2m_cfg_##inst, POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY,      \
+			      &gpio_rza2m_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(GPIO_RZA2M_PORT_INIT)
+DT_FOREACH_STATUS_OKAY(renesas_rza2m_gpio_int, GPIO_RZA2M_INT_INIT)
diff --git a/drivers/gpio/gpio_renesas_rza2m.h b/drivers/gpio/gpio_renesas_rza2m.h
new file mode 100644
index 00000000000..72fab0007a6
--- /dev/null
+++ b/drivers/gpio/gpio_renesas_rza2m.h
@@ -0,0 +1,140 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_GPIO_GPIO_RENESAS_RZA2M_H_
+#define ZEPHYR_DRIVERS_GPIO_GPIO_RENESAS_RZA2M_H_
+
+#include <zephyr/sys/device_mmio.h>
+
+#define RZA2M_PDR_OFFSET  0x0000
+#define RZA2M_PODR_OFFSET 0x0040
+#define RZA2M_PIDR_OFFSET 0x0060
+#define RZA2M_PMR_OFFSET  0x0080
+#define RZA2M_DSCR_OFFSET 0x0140
+#define RZA2M_PFS_OFFSET  0x0200
+#define RZA2M_PWPR_OFFSET 0x02FF
+
+#define RZA2M_PDR(dev, port)      (DEVICE_MMIO_GET(dev) + RZA2M_PDR_OFFSET + ((port) * 2))
+#define RZA2M_PODR(dev, port)     (DEVICE_MMIO_GET(dev) + RZA2M_PODR_OFFSET + (port))
+#define RZA2M_PIDR(dev, port)     (DEVICE_MMIO_GET(dev) + RZA2M_PIDR_OFFSET + (port))
+#define RZA2M_PMR(dev, port)      (DEVICE_MMIO_GET(dev) + RZA2M_PMR_OFFSET + (port))
+#define RZA2M_DSCR(dev, port)     (DEVICE_MMIO_GET(dev) + RZA2M_DSCR_OFFSET + ((port) * 2))
+#define RZA2M_PFS(dev, port, pin) (DEVICE_MMIO_GET(dev) + RZA2M_PFS_OFFSET + ((port) * 8) + (pin))
+#define RZA2M_PWPR(dev)           (DEVICE_MMIO_GET(dev) + RZA2M_PWPR_OFFSET)
+
+#define RZA2M_GICD_ICFGR31               0xE8221C7C
+#define RZA2M_GICD_ICFGR30               0xE8221C78
+#define RZA2M_GPIO_DRIVE_STRENGTH_HIGH   0b11
+#define RZA2M_GPIO_DRIVE_STRENGTH_NORMAL 0x01
+#define RZA2M_DSCR_MASK                  0x03
+#define RZA2M_PDR_MASK                   0x03
+#define RZA2M_PDR_INPUT                  0x02
+#define RZA2M_PDR_OUTPUT                 0x03
+#define RZA2M_PWPR_PFSWE_MASK            0x40
+#define RZA2M_PWPR_B0WI_MASK             0x80
+#define RZA2M_PFS_ISEL_MASK              0x40
+
+/* As per Table 51.37 of the hardware manual, each TINT group supports up to 2 ports. */
+#define RZA2M_MAX_PORTS_PER_TINT 2
+
+#define TINT0  480
+#define TINT1  481
+#define TINT2  482
+#define TINT3  483
+#define TINT4  484
+#define TINT5  485
+#define TINT6  486
+#define TINT7  487
+#define TINT8  488
+#define TINT9  489
+#define TINT10 490
+#define TINT11 491
+#define TINT12 492
+#define TINT13 493
+#define TINT14 494
+#define TINT15 495
+#define TINT16 496
+#define TINT17 497
+#define TINT18 498
+#define TINT19 499
+#define TINT20 500
+#define TINT21 501
+#define TINT22 502
+#define TINT23 503
+#define TINT24 504
+#define TINT25 505
+#define TINT26 506
+#define TINT27 507
+#define TINT28 508
+#define TINT29 509
+#define TINT30 510
+#define TINT31 511
+
+#define PORT0 0x00
+#define PORT1 0x01
+#define PORT2 0x02
+#define PORT3 0x03
+#define PORT4 0x04
+#define PORT5 0x05
+#define PORT6 0x06
+#define PORT7 0x07
+#define PORT8 0x08
+#define PORT9 0x09
+#define PORTA 0x0A
+#define PORTB 0x0B
+#define PORTC 0x0C
+#define PORTD 0x0D
+#define PORTE 0x0E
+#define PORTF 0x0F
+#define PORTG 0x10
+#define PORTH 0x11
+#define PORTJ 0x12
+#define PORTK 0x13
+#define PORTL 0x14
+#define PORTM 0x15
+
+#define UNUSED_PORT 0xFF
+#define UNUSED_MASK 0x00
+
+struct gpio_rza2m_tint_config {
+	DEVICE_MMIO_ROM;
+	void (*gpio_int_init)(void);
+};
+
+struct gpio_rza2m_tint_data {
+	DEVICE_MMIO_RAM;
+};
+
+typedef struct gpio_rza2m_high_allowed_pin {
+	uint8_t port;
+	uint8_t mask;
+} gpio_rza2m_high_allowed_pin_t;
+
+struct gpio_rza2m_port_config {
+	struct gpio_driver_config common;
+	uint8_t port;
+	uint8_t ngpios;
+	const struct device *int_dev;
+};
+
+struct gpio_rza2m_port_data {
+	struct gpio_driver_data common;
+	sys_slist_t callbacks;
+	uint8_t mask_irq_en;
+};
+
+typedef struct gpio_rza2m_port_tint_map {
+	uint32_t tint;
+	uint32_t ports[RZA2M_MAX_PORTS_PER_TINT];
+	uint16_t masks[RZA2M_MAX_PORTS_PER_TINT];
+} gpio_rza2m_port_tint_map_t;
+
+enum gpio_rza2m_tint_sense {
+	RZA2M_GPIO_TINT_SENSE_HIGH_LEVEL,
+	RZA2M_GPIO_TINT_SENSE_RISING_EDGE,
+};
+
+#endif /* ZEPHYR_DRIVERS_GPIO_GPIO_RENESAS_RZA2M_H_ */
diff --git a/drivers/gpio/gpio_rpi_pico.c b/drivers/gpio/gpio_rpi_pico.c
index 8b3d18e8717..198820f9244 100644
--- a/drivers/gpio/gpio_rpi_pico.c
+++ b/drivers/gpio/gpio_rpi_pico.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2021, Yonatan Schachter
+ * Copyright (c) 2025, Andrew Featherstone
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,36 +16,138 @@
 
 #include <zephyr/drivers/gpio/gpio_utils.h>
 
-#define DT_DRV_COMPAT raspberrypi_pico_gpio
+#define DT_DRV_COMPAT raspberrypi_pico_gpio_port
 
 #define ALL_EVENTS (GPIO_IRQ_EDGE_FALL | GPIO_IRQ_EDGE_RISE \
 		| GPIO_IRQ_LEVEL_LOW | GPIO_IRQ_LEVEL_HIGH)
 
+#define GPIO_RPI_PINS_PER_PORT 32
+
+#define ADDR_IS_ZERO(n, x)     (DT_INST_REG_ADDR(n) == 0) |
+#define ADDR_IS_NON_ZERO(n, x) (DT_INST_REG_ADDR(n) != 0) |
+#define GPIO_RPI_LO_AVAILABLE  (DT_INST_FOREACH_STATUS_OKAY_VARGS(ADDR_IS_ZERO) 0)
+#define GPIO_RPI_HI_AVAILABLE  (DT_INST_FOREACH_STATUS_OKAY_VARGS(ADDR_IS_NON_ZERO) 0)
+
+#if GPIO_RPI_HI_AVAILABLE
+#define PORT_NO(port) ((((struct gpio_rpi_config *)port->config)->high_dev != NULL) ? 0 : 1)
+#else
+#define PORT_NO(port) ((int)port & 0) /* generate zero and suppress unused warning */
+#endif
+
 struct gpio_rpi_config {
 	struct gpio_driver_config common;
 	void (*bank_config_func)(void);
+#if GPIO_RPI_HI_AVAILABLE
+	const struct device *high_dev;
+#endif
 };
 
 struct gpio_rpi_data {
 	struct gpio_driver_data common;
 	sys_slist_t callbacks;
-	uint32_t int_enabled_mask;
 	uint32_t single_ended_mask;
 	uint32_t open_drain_mask;
 };
 
+static inline void gpio_set_dir_out_masked_n(uint n, uint32_t mask)
+{
+	if (!n) {
+		gpio_set_dir_out_masked(mask);
+	} else if (n == 1) {
+#if PICO_USE_GPIO_COPROCESSOR
+		gpioc_hi_oe_set(mask);
+#else
+		sio_hw->gpio_hi_oe_set = mask;
+#endif
+	}
+}
+
+static inline void gpio_set_dir_in_masked_n(uint n, uint32_t mask)
+{
+	if (!n) {
+		gpio_set_dir_in_masked(mask);
+	} else if (n == 1) {
+#if PICO_USE_GPIO_COPROCESSOR
+		gpioc_hi_oe_clr(mask);
+#else
+		sio_hw->gpio_hi_oe_clr = mask;
+#endif
+	}
+}
+
+static inline void gpio_set_dir_masked_n(uint n, uint32_t mask, uint32_t value)
+{
+	if (!n) {
+		gpio_set_dir_masked(mask, value);
+	} else if (n == 1) {
+#if PICO_USE_GPIO_COPROCESSOR
+		gpioc_hi_oe_xor((gpioc_hi_oe_get() ^ value) & mask);
+#else
+		sio_hw->gpio_oe_togl = (sio_hw->gpio_hi_oe ^ value) & mask;
+#endif
+	}
+}
+
+static inline uint32_t gpio_get_all_n(uint n)
+{
+	if (!n) {
+		return gpio_get_all();
+	} else if (n == 1) {
+#if PICO_USE_GPIO_COPROCESSOR
+		return gpioc_hi_in_get();
+#else
+		return sio_hw->gpio_hi_in;
+#endif
+	}
+
+	return 0;
+}
+
+static inline void gpio_toggle_dir_masked_n(uint n, uint32_t mask)
+{
+	if (!n) {
+#if PICO_USE_GPIO_COPROCESSOR
+		gpioc_lo_oe_xor(mask);
+#else
+		sio_hw->gpio_oe_togl = mask;
+#endif
+	} else if (n == 1) {
+#if PICO_USE_GPIO_COPROCESSOR
+		gpioc_hi_oe_xor(mask);
+#else
+		sio_hw->gpio_hi_oe_togl = mask;
+#endif
+	}
+}
+
 static int gpio_rpi_configure(const struct device *dev,
 				gpio_pin_t pin,
 				gpio_flags_t flags)
 {
+	const int offset = GPIO_RPI_PINS_PER_PORT * PORT_NO(dev);
 	struct gpio_rpi_data *data = dev->data;
 
-	gpio_set_pulls(pin,
-		(flags & GPIO_PULL_UP) != 0U,
-		(flags & GPIO_PULL_DOWN) != 0U);
+	if (flags == GPIO_DISCONNECTED) {
+		gpio_disable_pulls(pin);
+		/* This is almost the opposite of the Pico SDK's gpio_set_function. */
+		hw_write_masked(&pads_bank0_hw->io[pin], PADS_BANK0_GPIO0_OD_BITS,
+				PADS_BANK0_GPIO0_IE_BITS | PADS_BANK0_GPIO0_OD_BITS);
+#ifdef SOC_SERIES_RP2350
+		hw_set_bits(&pads_bank0_hw->io[gpio], PADS_BANK0_GPIO0_ISO_BITS);
+#endif
+		return 0;
+	}
+
+	gpio_set_pulls(pin + offset, (flags & GPIO_PULL_UP) != 0U, (flags & GPIO_PULL_DOWN) != 0U);
 
 	/* Avoid gpio_init, since that also clears previously set direction/high/low */
-	gpio_set_function(pin, GPIO_FUNC_SIO);
+	gpio_set_function(pin + offset, GPIO_FUNC_SIO);
+
+	if (flags & GPIO_INPUT) {
+		gpio_set_dir(pin + offset, GPIO_IN);
+	} else {
+		gpio_set_input_enabled(pin + offset, false);
+	}
 
 	if (flags & GPIO_OUTPUT) {
 		if (flags & GPIO_SINGLE_ENDED) {
@@ -57,32 +160,63 @@ static int gpio_rpi_configure(const struct device *dev,
 			 */
 			if (flags & GPIO_LINE_OPEN_DRAIN) {
 				data->open_drain_mask |= BIT(pin);
-				gpio_put(pin, 0);
-				gpio_set_dir(pin, flags & GPIO_OUTPUT_INIT_LOW);
+				gpio_put(pin + offset, 0);
+				gpio_set_dir(pin + offset, flags & GPIO_OUTPUT_INIT_LOW);
 			} else {
 				data->open_drain_mask &= ~(BIT(pin));
-				gpio_put(pin, 1);
-				gpio_set_dir(pin, flags & GPIO_OUTPUT_INIT_HIGH);
+				gpio_put(pin + offset, 1);
+				gpio_set_dir(pin + offset, flags & GPIO_OUTPUT_INIT_HIGH);
 			}
 		} else {
 			data->single_ended_mask &= ~(BIT(pin));
 			if (flags & GPIO_OUTPUT_INIT_HIGH) {
-				gpio_put(pin, 1);
+				gpio_put(pin + offset, 1);
 			} else if (flags & GPIO_OUTPUT_INIT_LOW) {
-				gpio_put(pin, 0);
+				gpio_put(pin + offset, 0);
 			}
-			gpio_set_dir(pin, GPIO_OUT);
+			gpio_set_dir(pin + offset, GPIO_OUT);
+		}
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_GPIO_GET_CONFIG
+static int gpio_rpi_get_config(const struct device *dev, gpio_pin_t pin, gpio_flags_t *flags)
+{
+	const int offset = GPIO_RPI_PINS_PER_PORT * PORT_NO(dev);
+	struct gpio_rpi_data *data = dev->data;
+
+	*flags = 0;
+
+	/* RP2xxxx supports Bus Keeper mode where both pull-up and pull-down are enabled. */
+	if (gpio_is_pulled_up(pin + offset)) {
+		*flags |= GPIO_PULL_UP;
+	}
+	if (gpio_is_pulled_down(pin + offset)) {
+		*flags |= GPIO_PULL_DOWN;
+	}
+
+	if (gpio_get_dir(pin + offset)) {
+		*flags |= gpio_get_out_level(pin + offset) ? GPIO_OUTPUT_HIGH : GPIO_OUTPUT_LOW;
+		if (data->single_ended_mask & BIT(pin)) {
+			*flags |=
+				data->open_drain_mask & BIT(pin) ? GPIO_OPEN_DRAIN : GPIO_PUSH_PULL;
 		}
-	} else if (flags & GPIO_INPUT) {
-		gpio_set_dir(pin, GPIO_IN);
+	}
+
+	if (pads_bank0_hw->io[pin] & PADS_BANK0_GPIO0_IE_BITS) {
+		*flags |= GPIO_INPUT;
 	}
 
 	return 0;
 }
+#endif
 
-static int gpio_rpi_port_get_raw(const struct device *dev, uint32_t *value)
+static int gpio_rpi_port_get_raw(const struct device *port, uint32_t *value)
 {
-	*value = gpio_get_all();
+	*value = gpio_get_all_n(PORT_NO(port));
+
 	return 0;
 }
 
@@ -90,12 +224,16 @@ static int gpio_rpi_port_set_masked_raw(const struct device *port,
 					uint32_t mask, uint32_t value)
 {
 	struct gpio_rpi_data *data = port->data;
+
 	/* First handle push-pull pins: */
-	gpio_put_masked(mask & ~data->single_ended_mask, value);
+	gpio_put_masked_n(PORT_NO(port), mask & ~data->single_ended_mask, value);
 	/* Then handle open-drain pins: */
-	gpio_set_dir_masked(mask & data->single_ended_mask & data->open_drain_mask, ~value);
+	gpio_set_dir_masked_n(PORT_NO(port), mask & data->single_ended_mask & data->open_drain_mask,
+			      ~value);
 	/* Then handle open-source pins: */
-	gpio_set_dir_masked(mask & data->single_ended_mask & ~data->open_drain_mask, value);
+	gpio_set_dir_masked_n(PORT_NO(port),
+			      mask & data->single_ended_mask & ~data->open_drain_mask, value);
+
 	return 0;
 }
 
@@ -103,12 +241,16 @@ static int gpio_rpi_port_set_bits_raw(const struct device *port,
 					uint32_t pins)
 {
 	struct gpio_rpi_data *data = port->data;
+
 	/* First handle push-pull pins: */
-	gpio_set_mask(pins & ~data->single_ended_mask);
+	gpio_set_mask_n(PORT_NO(port), pins & ~data->single_ended_mask);
 	/* Then handle open-drain pins: */
-	gpio_set_dir_in_masked(pins & data->single_ended_mask & data->open_drain_mask);
+	gpio_set_dir_in_masked_n(PORT_NO(port),
+				 pins & data->single_ended_mask & data->open_drain_mask);
 	/* Then handle open-source pins: */
-	gpio_set_dir_out_masked(pins & data->single_ended_mask & ~data->open_drain_mask);
+	gpio_set_dir_out_masked_n(PORT_NO(port),
+				  pins & data->single_ended_mask & ~data->open_drain_mask);
+
 	return 0;
 }
 
@@ -116,12 +258,16 @@ static int gpio_rpi_port_clear_bits_raw(const struct device *port,
 					uint32_t pins)
 {
 	struct gpio_rpi_data *data = port->data;
+
 	/* First handle push-pull pins: */
-	gpio_clr_mask(pins & ~data->single_ended_mask);
+	gpio_clr_mask_n(PORT_NO(port), pins & ~data->single_ended_mask);
 	/* Then handle open-drain pins: */
-	gpio_set_dir_out_masked(pins & data->single_ended_mask & data->open_drain_mask);
+	gpio_set_dir_out_masked_n(PORT_NO(port),
+				  pins & data->single_ended_mask & data->open_drain_mask);
 	/* Then handle open-source pins: */
-	gpio_set_dir_in_masked(pins & data->single_ended_mask & ~data->open_drain_mask);
+	gpio_set_dir_in_masked_n(PORT_NO(port),
+				 pins & data->single_ended_mask & ~data->open_drain_mask);
+
 	return 0;
 }
 
@@ -129,13 +275,12 @@ static int gpio_rpi_port_toggle_bits(const struct device *port,
 					uint32_t pins)
 {
 	struct gpio_rpi_data *data = port->data;
+
 	/* First handle push-pull pins: */
-	gpio_xor_mask(pins & ~data->single_ended_mask);
+	gpio_xor_mask_n(PORT_NO(port), pins & ~data->single_ended_mask);
 	/* Then handle single-ended pins: */
-	/* (unfortunately there's no pico-sdk api call that can be used for this,
-	 * but it's possible by accessing the registers directly)
-	 */
-	sio_hw->gpio_oe_togl = (pins & data->single_ended_mask);
+	gpio_toggle_dir_masked_n(PORT_NO(port), pins & data->single_ended_mask);
+
 	return 0;
 }
 
@@ -144,10 +289,10 @@ static int gpio_rpi_pin_interrupt_configure(const struct device *dev,
 						enum gpio_int_mode mode,
 						enum gpio_int_trig trig)
 {
-	struct gpio_rpi_data *data = dev->data;
+	const int offset = GPIO_RPI_PINS_PER_PORT * PORT_NO(dev);
 	uint32_t events = 0;
 
-	gpio_set_irq_enabled(pin, ALL_EVENTS, false);
+	gpio_set_irq_enabled(pin + offset, ALL_EVENTS, false);
 	if (mode != GPIO_INT_DISABLE) {
 		if (mode & GPIO_INT_EDGE) {
 			if (trig & GPIO_INT_LOW_0) {
@@ -164,9 +309,9 @@ static int gpio_rpi_pin_interrupt_configure(const struct device *dev,
 				events |= GPIO_IRQ_LEVEL_HIGH;
 			}
 		}
-		gpio_set_irq_enabled(pin, events, true);
+		gpio_set_irq_enabled(pin + offset, events, true);
 	}
-	WRITE_BIT(data->int_enabled_mask, pin, mode != GPIO_INT_DISABLE);
+
 	return 0;
 }
 
@@ -178,8 +323,50 @@ static int gpio_rpi_manage_callback(const struct device *dev,
 	return gpio_manage_callback(&data->callbacks, callback, set);
 }
 
+static uint32_t gpio_rpi_get_pending_int(const struct device *dev)
+{
+	io_bank0_irq_ctrl_hw_t *irq_ctrl_base =
+		get_core_num() ? &io_bank0_hw->proc1_irq_ctrl : &io_bank0_hw->proc0_irq_ctrl;
+	ARRAY_FOR_EACH_PTR(irq_ctrl_base->ints, p) {
+		if (*p) {
+			return 1;
+		}
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_GPIO_GET_DIRECTION
+static int gpio_rpi_port_get_direction(const struct device *port, gpio_port_pins_t map,
+				  gpio_port_pins_t *inputs, gpio_port_pins_t *outputs)
+{
+	/* The Zephyr API considers a disconnected pin to be neither an input nor output.
+	 * Since we disable both OE and IE for disconnected pins clear the mask bits.
+	 */
+	for (int pin = 0; pin < NUM_BANK0_GPIOS; pin++) {
+		if (pads_bank0_hw->io[pin] & PADS_BANK0_GPIO0_OD_BITS) {
+			map &= ~BIT(pin);
+		}
+		if (inputs && (pads_bank0_hw->io[pin] & PADS_BANK0_GPIO0_IE_BITS)) {
+			*inputs |= BIT(pin);
+		}
+	}
+	if (inputs) {
+		*inputs &= map;
+	}
+	if (outputs) {
+		*outputs = sio_hw->gpio_oe & map;
+	}
+
+	return 0;
+}
+#endif
+
 static DEVICE_API(gpio, gpio_rpi_driver_api) = {
 	.pin_configure = gpio_rpi_configure,
+#ifdef CONFIG_GPIO_GET_CONFIG
+	.pin_get_config = gpio_rpi_get_config,
+#endif
 	.port_get_raw = gpio_rpi_port_get_raw,
 	.port_set_masked_raw = gpio_rpi_port_set_masked_raw,
 	.port_set_bits_raw = gpio_rpi_port_set_bits_raw,
@@ -187,6 +374,10 @@ static DEVICE_API(gpio, gpio_rpi_driver_api) = {
 	.port_toggle_bits = gpio_rpi_port_toggle_bits,
 	.pin_interrupt_configure = gpio_rpi_pin_interrupt_configure,
 	.manage_callback = gpio_rpi_manage_callback,
+	.get_pending_int = gpio_rpi_get_pending_int,
+#ifdef CONFIG_GPIO_GET_DIRECTION
+	.port_get_direction = gpio_rpi_port_get_direction,
+#endif
 };
 
 static void gpio_rpi_isr(const struct device *dev)
@@ -203,6 +394,18 @@ static void gpio_rpi_isr(const struct device *dev)
 		events = (*status_reg >> 4 * (pin % 8)) & ALL_EVENTS;
 		if (events) {
 			gpio_acknowledge_irq(pin, ALL_EVENTS);
+
+#if GPIO_RPI_HI_AVAILABLE
+			if (pin >= GPIO_RPI_PINS_PER_PORT) {
+				const struct gpio_rpi_config *config = dev->config;
+				struct gpio_rpi_data *high_data = config->high_dev->data;
+
+				gpio_fire_callbacks(&high_data->callbacks, config->high_dev,
+						    BIT(pin - GPIO_RPI_PINS_PER_PORT));
+				continue;
+			}
+#endif
+
 			gpio_fire_callbacks(&data->callbacks, dev, BIT(pin));
 		}
 	}
@@ -212,31 +415,56 @@ static int gpio_rpi_bank_init(const struct device *dev)
 {
 	const struct gpio_rpi_config *config = dev->config;
 
-	config->bank_config_func();
+	if (config->bank_config_func != NULL) {
+		config->bank_config_func();
+	}
+
 	return 0;
 }
 
-#define GPIO_RPI_INIT(idx)							\
-	static void bank_##idx##_config_func(void)				\
-	{									\
-		IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(idx, priority),	\
-			    gpio_rpi_isr, DEVICE_DT_INST_GET(idx), 0);		\
-		irq_enable(DT_INST_IRQN(idx));					\
-	}									\
-	static const struct gpio_rpi_config gpio_rpi_##idx##_config = {		\
-		.bank_config_func = bank_##idx##_config_func,			\
-		.common =							\
-		{								\
-			.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx),	\
-		}								\
-	};									\
-										\
-	static struct gpio_rpi_data gpio_rpi_##idx##_data;			\
-										\
-	DEVICE_DT_INST_DEFINE(idx, gpio_rpi_bank_init, NULL,			\
-				&gpio_rpi_##idx##_data,				\
-				&gpio_rpi_##idx##_config,			\
-				POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY,		\
-				&gpio_rpi_driver_api);
+#define GPIO_REG_0U            1
+#define IS_GPIO_RPI_LO_NODE(n) UTIL_CAT(GPIO_REG_, DT_REG_ADDR(n))
+
+#define DEVICE_IF_GPIO_RPI_HI_NODE(n) COND_CODE_1(IS_GPIO_RPI_LO_NODE(n), (), (DEVICE_DT_GET(n)))
+
+#define FIND_GPIO_RPI_HI_DEVICE(n)                                                                 \
+	COND_CODE_1(UTIL_CAT(GPIO_REG_, DT_REG_ADDR(n)),                                           \
+			(DT_FOREACH_CHILD(DT_PARENT(n), DEVICE_IF_GPIO_RPI_HI_NODE)), (NULL))
+
+#if GPIO_RPI_HI_AVAILABLE
+#define GPIO_RPI_INIT_HIGH_DEV(idx) .high_dev = FIND_GPIO_RPI_HI_DEVICE(DT_DRV_INST(idx)),
+#else
+#define GPIO_RPI_INIT_HIGH_DEV(idx)
+#endif
+
+#define GPIO_RPI_INIT(idx)                                                                         \
+	BUILD_ASSERT(DT_CHILD_NUM(DT_INST_PARENT(idx)) > 0 &&                                      \
+			     DT_CHILD_NUM(DT_INST_PARENT(idx)) <= 2,                               \
+		     "raspberrypi,pico-gpio node must have one or two child node.");               \
+	BUILD_ASSERT(GPIO_RPI_LO_AVAILABLE,                                                        \
+		     "raspberrypi,pico-gpio node must have reg=0 child node.");                    \
+	IF_ENABLED(IS_GPIO_RPI_LO_NODE(DT_DRV_INST(idx)), (                                        \
+		static void bank_##idx##_config_func(void)                                         \
+		{                                                                                  \
+			IRQ_CONNECT(DT_IRQN(DT_INST_PARENT(idx)),                                  \
+				    DT_IRQ(DT_INST_PARENT(idx), priority),                         \
+				    gpio_rpi_isr, DEVICE_DT_INST_GET(idx), 0);                     \
+			irq_enable(DT_IRQN(DT_INST_PARENT(idx)));                                  \
+		}                                                                                  \
+	))                                                                                         \
+	static const struct gpio_rpi_config gpio_rpi_##idx##_config = {                            \
+		.common = {                                                                        \
+			.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx),                     \
+		},                                                                                 \
+		IF_ENABLED(IS_GPIO_RPI_LO_NODE(DT_DRV_INST(idx)), (                                \
+			.bank_config_func = bank_##idx##_config_func,                              \
+		))                                                                                 \
+		GPIO_RPI_INIT_HIGH_DEV(idx)                                                        \
+	};                                                                                         \
+	static struct gpio_rpi_data gpio_rpi_##idx##_data;                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(idx, gpio_rpi_bank_init, NULL, &gpio_rpi_##idx##_data,               \
+			      &gpio_rpi_##idx##_config, POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY,    \
+			      &gpio_rpi_driver_api);
 
 DT_INST_FOREACH_STATUS_OKAY(GPIO_RPI_INIT)
diff --git a/drivers/gpio/gpio_sam.c b/drivers/gpio/gpio_sam.c
index ae8a954c6ae..9ceb9173b28 100644
--- a/drivers/gpio/gpio_sam.c
+++ b/drivers/gpio/gpio_sam.c
@@ -66,8 +66,7 @@ static int gpio_sam_port_configure(const struct device *dev, uint32_t mask,
 		pio->PIO_PUDR = mask;
 #if defined(CONFIG_SOC_SERIES_SAM4S) || \
 	defined(CONFIG_SOC_SERIES_SAM4E) || \
-	defined(CONFIG_SOC_SERIES_SAME70) || \
-	defined(CONFIG_SOC_SERIES_SAMV71)
+	defined(CONFIG_SOC_SERIES_SAMX7X)
 		/* Disable pull-down. */
 		pio->PIO_PPDDR = mask;
 #endif
@@ -108,8 +107,7 @@ static int gpio_sam_port_configure(const struct device *dev, uint32_t mask,
 	pio->PIO_PUDR = mask;
 #if defined(CONFIG_SOC_SERIES_SAM4S) || \
 	defined(CONFIG_SOC_SERIES_SAM4E) || \
-	defined(CONFIG_SOC_SERIES_SAME70) || \
-	defined(CONFIG_SOC_SERIES_SAMV71)
+	defined(CONFIG_SOC_SERIES_SAMX7X)
 	pio->PIO_PPDDR = mask;
 #endif
 	if (flags & GPIO_PULL_UP) {
@@ -117,8 +115,7 @@ static int gpio_sam_port_configure(const struct device *dev, uint32_t mask,
 		pio->PIO_PUER = mask;
 #if defined(CONFIG_SOC_SERIES_SAM4S) || \
 	defined(CONFIG_SOC_SERIES_SAM4E) || \
-	defined(CONFIG_SOC_SERIES_SAME70) || \
-	defined(CONFIG_SOC_SERIES_SAMV71)
+	defined(CONFIG_SOC_SERIES_SAMX7X)
 
 	/* Setup Pull-down resistor. */
 	} else if (flags & GPIO_PULL_DOWN) {
@@ -136,8 +133,7 @@ static int gpio_sam_port_configure(const struct device *dev, uint32_t mask,
 	}
 #elif defined(CONFIG_SOC_SERIES_SAM4S) || \
 	defined(CONFIG_SOC_SERIES_SAM4E) || \
-	defined(CONFIG_SOC_SERIES_SAME70) || \
-	defined(CONFIG_SOC_SERIES_SAMV71)
+	defined(CONFIG_SOC_SERIES_SAMX7X)
 
 	/* Setup debounce. */
 	if (flags & SAM_GPIO_DEBOUNCE) {
diff --git a/drivers/gpio/gpio_shell.c b/drivers/gpio/gpio_shell.c
index d85b72e2dca..514b6cc44b4 100644
--- a/drivers/gpio/gpio_shell.c
+++ b/drivers/gpio/gpio_shell.c
@@ -101,10 +101,6 @@ static void port_pin_get(gpio_port_pins_t reserved_mask, const char **line_names
 #define GPIO_CTRL_PIN_GET_FN(node_id)                                                              \
 	static const char *node_id##line_names[] = DT_PROP_OR(node_id, gpio_line_names, {NULL});   \
                                                                                                    \
-	static void node_id##cmd_gpio_pin_get(size_t idx, struct shell_static_entry *entry);       \
-                                                                                                   \
-	SHELL_DYNAMIC_CMD_CREATE(node_id##sub_gpio_pin, node_id##cmd_gpio_pin_get);                \
-                                                                                                   \
 	static void node_id##cmd_gpio_pin_get(size_t idx, struct shell_static_entry *entry)        \
 	{                                                                                          \
 		gpio_port_pins_t reserved_mask = GPIO_DT_RESERVED_RANGES_NGPIOS_SHELL(node_id);    \
@@ -112,7 +108,9 @@ static void port_pin_get(gpio_port_pins_t reserved_mask, const char **line_names
                                                                                                    \
 		port_pin_get(reserved_mask, node_id##line_names, line_names_len, idx, entry);      \
 		entry->subcmd = NULL;                                                              \
-	}
+	}                                                                                          \
+                                                                                                   \
+	SHELL_DYNAMIC_CMD_CREATE(node_id##sub_gpio_pin, node_id##cmd_gpio_pin_get);
 
 #define IS_GPIO_CTRL_PIN_GET(node_id)                                                              \
 	COND_CODE_1(DT_PROP(node_id, gpio_controller), (GPIO_CTRL_PIN_GET_FN(node_id)), ())
@@ -152,7 +150,7 @@ static const struct gpio_ctrl *get_gpio_ctrl(const char *name)
 	return NULL;
 }
 
-int line_cmp(const char *input, const char *line_name)
+static int line_cmp(const char *input, const char *line_name)
 {
 	int i = 0;
 
@@ -174,7 +172,7 @@ static int get_gpio_pin(const struct shell *sh, const struct gpio_ctrl *ctrl, ch
 	gpio_pin_t i;
 	int result;
 
-	for (i = 0; i < ctrl->ngpios; i++) {
+	for (i = 0; i < ctrl->ngpios && i < ctrl->line_names_len; i++) {
 		result = line_cmp(line_name, ctrl->line_names[i]);
 		if (result == 0) {
 			if ((BIT64(i) & ctrl->reserved_mask) != 0) {
@@ -224,12 +222,13 @@ static int get_sh_gpio(const struct shell *sh, char **argv, struct sh_gpio *gpio
 	return 0;
 }
 
-static int cmd_gpio_conf(const struct shell *sh, size_t argc, char **argv, void *data)
+static int cmd_gpio_conf(const struct shell *sh, size_t argc, char **argv)
 {
 	gpio_flags_t flags = 0;
 	gpio_flags_t vendor_specific;
 	struct sh_gpio gpio;
-	int ret = 0;
+	int ret;
+	size_t len;
 
 	ret = get_sh_gpio(sh, argv, &gpio);
 	if (ret != 0) {
@@ -237,7 +236,8 @@ static int cmd_gpio_conf(const struct shell *sh, size_t argc, char **argv, void
 		return SHELL_CMD_HELP_PRINTED;
 	}
 
-	for (int i = 0; i < strlen(argv[ARGV_CONF]); i++) {
+	len = strlen(argv[ARGV_CONF]);
+	for (int i = 0; i < len; i++) {
 		switch (argv[ARGV_CONF][i]) {
 		case 'i':
 			flags |= GPIO_INPUT;
@@ -363,7 +363,7 @@ static int cmd_gpio_set(const struct shell *sh, size_t argc, char **argv)
 {
 	struct sh_gpio gpio;
 	unsigned long value;
-	int ret = 0;
+	int ret;
 
 	ret = get_sh_gpio(sh, argv, &gpio);
 	if (ret != 0) {
@@ -389,7 +389,7 @@ static int cmd_gpio_set(const struct shell *sh, size_t argc, char **argv)
 static int cmd_gpio_toggle(const struct shell *sh, size_t argc, char **argv)
 {
 	struct sh_gpio gpio;
-	int ret = 0;
+	int ret;
 
 	ret = get_sh_gpio(sh, argv, &gpio);
 	if (ret != 0) {
@@ -474,14 +474,28 @@ static int cmd_gpio_blink(const struct shell *sh, size_t argc, char **argv)
 	return 0;
 }
 
+static const char *gpio_device_name(const struct device *dev)
+{
+#ifdef CONFIG_DEVICE_DT_METADATA
+	const struct device_dt_nodelabels *nl = device_get_dt_nodelabels(dev);
+
+	if (nl != NULL && nl->num_nodelabels > 0) {
+		return nl->nodelabels[0];
+	}
+#endif
+	return dev->name;
+}
+
 static void device_name_get(size_t idx, struct shell_static_entry *entry)
 {
+	const struct device *dev = gpio_list[idx].dev;
+
 	if (idx >= ARRAY_SIZE(gpio_list)) {
 		entry->syntax = NULL;
 		return;
 	}
 
-	entry->syntax = gpio_list[idx].dev->name;
+	entry->syntax = gpio_device_name(dev);
 	entry->handler = NULL;
 	entry->help = "Device";
 	entry->subcmd = gpio_list[idx].subcmd;
@@ -511,9 +525,7 @@ static void print_gpio_ctrl_info(const struct shell *sh, const struct gpio_ctrl
 	const char *line_name;
 
 	shell_print(sh, " ngpios: %u", ctrl->ngpios);
-	shell_print(sh, " Reserved pin mask: 0x%08X", ctrl->reserved_mask);
-
-	shell_print(sh, "");
+	shell_print(sh, " Reserved pin mask: 0x%08X\n", ctrl->reserved_mask);
 
 	shell_print(sh, " Reserved  Pin  Line Name");
 	for (pin = 0; pin < ctrl->ngpios; pin++) {
@@ -599,7 +611,7 @@ static void pin_ordered(const struct pin_info *info, void *user_data)
 	shell_print(data->sh, "   %-12s %-8c %-16s %2u",
 		    data->next.line_name,
 		    data->next.reserved ? '*' : ' ',
-		    data->next.dev->name,
+		    gpio_device_name(data->next.dev),
 		    data->next.pin);
 
 	data->prev = data->next;
diff --git a/drivers/gpio/gpio_silabs_siwx91x.c b/drivers/gpio/gpio_silabs_siwx91x.c
new file mode 100644
index 00000000000..d712a6909fd
--- /dev/null
+++ b/drivers/gpio/gpio_silabs_siwx91x.c
@@ -0,0 +1,403 @@
+/*
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT silabs_siwx91x_gpio
+
+#include "sl_si91x_driver_gpio.h"
+#include "sl_status.h"
+
+#include <errno.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/irq.h>
+
+/* Zephyr GPIO header must be included after driver, due to symbol conflicts
+ * for GPIO_INPUT and GPIO_OUTPUT between preprocessor macros in the Zephyr
+ * API and struct member register definitions for the SiWx91x device.
+ */
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_utils.h>
+
+#if CONFIG_GPIO_SILABS_SIWX91X_COMMON_INIT_PRIORITY >= CONFIG_GPIO_INIT_PRIORITY
+#error CONFIG_GPIO_SILABS_SIWX91X_COMMON_INIT_PRIORITY must be less than \
+	CONFIG_GPIO_INIT_PRIORITY.
+#endif
+
+#define MAX_PORT_COUNT  4
+#define MAX_PIN_COUNT   16
+#define INVALID_PORT    0xFF
+#define INTERRUPT_COUNT 8
+
+/* Types */
+struct gpio_siwx91x_common_config {
+	EGPIO_Type *reg;
+};
+
+struct gpio_siwx91x_port_config {
+	/* gpio_driver_config needs to be first */
+	struct gpio_driver_config common;
+	const struct device *parent;
+	uint8_t pads[MAX_PIN_COUNT];
+	int port;
+	int hal_port;
+	bool ulp;
+};
+
+struct gpio_siwx91x_common_data {
+	/* a list of all ports */
+	const struct device *ports[MAX_PORT_COUNT];
+	sl_gpio_t interrupts[INTERRUPT_COUNT];
+};
+
+struct gpio_siwx91x_port_data {
+	/* gpio_driver_data needs to be first */
+	struct gpio_driver_data common;
+	/* port ISR callback routine address */
+	sys_slist_t callbacks;
+};
+
+/* Functions */
+static int gpio_siwx91x_pin_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
+{
+	const struct gpio_siwx91x_port_config *cfg = dev->config;
+	const struct device *parent = cfg->parent;
+	const struct gpio_siwx91x_common_config *pcfg = parent->config;
+	sl_status_t status;
+	sl_si91x_gpio_driver_disable_state_t disable_state = GPIO_HZ;
+
+	if (flags & GPIO_SINGLE_ENDED) {
+		return -ENOTSUP;
+	}
+
+	uint8_t pad = cfg->pads[pin];
+
+	if (pad == 0) {
+		/* Enable MCU pad */
+		status = sl_si91x_gpio_driver_enable_host_pad_selection((cfg->hal_port << 4) | pin);
+		if (status != SL_STATUS_OK) {
+			return -ENODEV;
+		}
+	} else if (pad != 0xFF && pad != 9) {
+		/* Assign pad to MCU subsystem */
+		status = sl_si91x_gpio_driver_enable_pad_selection(pad);
+		if (status != SL_STATUS_OK) {
+			return -ENODEV;
+		}
+	}
+
+	if (flags & GPIO_PULL_UP) {
+		disable_state = GPIO_PULLUP;
+	} else if (flags & GPIO_PULL_DOWN) {
+		disable_state = GPIO_PULLDOWN;
+	}
+	if (cfg->ulp) {
+		sl_si91x_gpio_select_ulp_pad_driver_disable_state(pin, disable_state);
+	} else {
+		sl_si91x_gpio_select_pad_driver_disable_state((cfg->port << 4) | pin,
+							      disable_state);
+	}
+
+	if (flags & GPIO_INPUT) {
+		if (cfg->ulp) {
+			sl_si91x_gpio_driver_enable_ulp_pad_receiver(pin);
+		} else {
+			sl_si91x_gpio_driver_enable_pad_receiver((cfg->port << 4) | pin);
+		}
+	} else {
+		if (cfg->ulp) {
+			sl_si91x_gpio_driver_disable_ulp_pad_receiver(pin);
+		} else {
+			sl_si91x_gpio_driver_disable_pad_receiver((cfg->port << 4) | pin);
+		}
+	}
+
+	pcfg->reg->PIN_CONFIG[(cfg->port << 4) + pin].GPIO_CONFIG_REG_b.MODE = 0;
+
+	if (flags & GPIO_OUTPUT_INIT_HIGH) {
+		sl_gpio_set_pin_output(cfg->hal_port, pin);
+	} else if (flags & GPIO_OUTPUT_INIT_LOW) {
+		sl_gpio_clear_pin_output(cfg->hal_port, pin);
+	}
+
+	sl_si91x_gpio_set_pin_direction(cfg->hal_port, pin, (flags & GPIO_OUTPUT) ? 0 : 1);
+
+	return 0;
+}
+
+static int gpio_siwx91x_port_get(const struct device *port, gpio_port_value_t *value)
+{
+	const struct gpio_siwx91x_port_config *cfg = port->config;
+
+	*value = sl_gpio_get_port_input(cfg->hal_port);
+
+	return 0;
+}
+
+static int gpio_siwx91x_port_set_masked(const struct device *port, gpio_port_pins_t mask,
+					gpio_port_value_t value)
+{
+	const struct gpio_siwx91x_port_config *cfg = port->config;
+	const struct device *parent = cfg->parent;
+	const struct gpio_siwx91x_common_config *pcfg = parent->config;
+
+	/* Cannot use HAL function sl_gpio_set_port_output_value(), as it doesn't clear bits. */
+	pcfg->reg->PORT_CONFIG[cfg->port].PORT_LOAD_REG =
+		(pcfg->reg->PORT_CONFIG[cfg->port].PORT_LOAD_REG & ~mask) | (value & mask);
+
+	return 0;
+}
+
+static int gpio_siwx91x_port_set_bits(const struct device *port, gpio_port_pins_t pins)
+{
+	const struct gpio_siwx91x_port_config *cfg = port->config;
+
+	sl_gpio_set_port_output(cfg->hal_port, pins);
+
+	return 0;
+}
+
+static int gpio_siwx91x_port_clear_bits(const struct device *port, gpio_port_pins_t pins)
+{
+	const struct gpio_siwx91x_port_config *cfg = port->config;
+
+	sl_gpio_clear_port_output(cfg->hal_port, pins);
+
+	return 0;
+}
+
+static int gpio_siwx91x_port_toggle_bits(const struct device *port, gpio_port_pins_t pins)
+{
+	const struct gpio_siwx91x_port_config *cfg = port->config;
+
+	sl_gpio_toggle_port_output(cfg->hal_port, pins);
+
+	return 0;
+}
+
+static bool receiver_enabled(bool ulp, sl_gpio_port_t port, int pin)
+{
+	if (ulp) {
+		return ULP_PAD_CONFIG_REG & BIT(pin);
+	} else {
+		return PAD_REG(((port << 4) | pin))->GPIO_PAD_CONFIG_REG_b.PADCONFIG_REN;
+	}
+}
+
+int gpio_siwx91x_port_get_direction(const struct device *port, gpio_port_pins_t map,
+				    gpio_port_pins_t *inputs, gpio_port_pins_t *outputs)
+{
+	const struct gpio_siwx91x_port_config *cfg = port->config;
+
+	if (inputs != NULL) {
+		*inputs = 0;
+	}
+	if (outputs != NULL) {
+		*outputs = 0;
+	}
+	for (int i = 0; i < MAX_PIN_COUNT; i++) {
+		if ((map & BIT(i))) {
+			if (sl_si91x_gpio_get_pin_direction(cfg->hal_port, i) == 0) {
+				if (outputs != NULL) {
+					*outputs |= BIT(i);
+				}
+			}
+			if (receiver_enabled(cfg->ulp, cfg->port, i)) {
+				if (inputs != NULL) {
+					*inputs |= BIT(i);
+				}
+			}
+		}
+	}
+	return 0;
+}
+
+static int gpio_siwx91x_manage_callback(const struct device *port, struct gpio_callback *callback,
+					bool set)
+{
+	struct gpio_siwx91x_port_data *data = port->data;
+
+	return gpio_manage_callback(&data->callbacks, callback, set);
+}
+
+static int gpio_siwx91x_interrupt_configure(const struct device *port, gpio_pin_t pin,
+					    enum gpio_int_mode mode, enum gpio_int_trig trig)
+{
+	const struct gpio_siwx91x_port_config *cfg = port->config;
+	const struct device *parent = cfg->parent;
+	const struct gpio_siwx91x_common_config *pcfg = parent->config;
+	struct gpio_siwx91x_common_data *data = parent->data;
+	sl_si91x_gpio_interrupt_config_flag_t flags = 0;
+
+	if (mode & GPIO_INT_DISABLE) {
+		ARRAY_FOR_EACH(data->interrupts, i) {
+			if (data->interrupts[i].port == cfg->port &&
+			    data->interrupts[i].pin == pin) {
+				data->interrupts[i].port = INVALID_PORT;
+				if (cfg->ulp) {
+					sl_si91x_gpio_configure_ulp_pin_interrupt(i, flags, pin);
+				} else {
+					sl_gpio_configure_interrupt(cfg->port, pin, i, flags);
+				}
+				/* Configure function doesn't mask interrupts when disabling */
+				pcfg->reg->INTR[i].GPIO_INTR_CTRL_b.MASK = 1;
+				if (cfg->ulp) {
+					sl_si91x_gpio_clear_ulp_interrupt(i);
+				} else {
+					sl_gpio_clear_interrupts(i);
+				}
+				return 0;
+			}
+		}
+		/* No interrupt to disable, but this is not an error */
+		return 0;
+	}
+
+	if (trig == GPIO_INT_TRIG_LOW) {
+		flags = (mode == GPIO_INT_MODE_EDGE) ? SL_GPIO_INTERRUPT_FALL_EDGE
+						     : SL_GPIO_INTERRUPT_LEVEL_LOW;
+	} else if (trig == GPIO_INT_TRIG_HIGH) {
+		flags = (mode == GPIO_INT_MODE_EDGE) ? SL_GPIO_INTERRUPT_RISE_EDGE
+						     : SL_GPIO_INTERRUPT_LEVEL_HIGH;
+	} else if (trig == GPIO_INT_TRIG_BOTH) {
+		/* SL_GPIO_INTERRUPT_RISE_FALL_EDGE would make more sense, but HAL
+		 * implementation is buggy.
+		 */
+		flags = SL_GPIO_INTERRUPT_RISE_EDGE | SL_GPIO_INTERRUPT_FALL_EDGE;
+	}
+
+	ARRAY_FOR_EACH(data->interrupts, i) {
+		if (data->interrupts[i].port == INVALID_PORT ||
+		    (data->interrupts[i].port == cfg->port && data->interrupts[i].pin == pin)) {
+			data->interrupts[i].port = cfg->port;
+			data->interrupts[i].pin = pin;
+
+			if (cfg->ulp) {
+				sl_si91x_gpio_configure_ulp_pin_interrupt(i, flags, pin);
+			} else {
+				sl_gpio_configure_interrupt(cfg->port, pin, i, flags);
+			}
+			return 0;
+		}
+	}
+	/* No more available interrupts */
+	return -EBUSY;
+}
+
+static inline int gpio_siwx91x_init_port(const struct device *port)
+{
+	const struct gpio_siwx91x_port_config *cfg = port->config;
+	const struct device *parent = cfg->parent;
+	struct gpio_siwx91x_common_data *data = parent->data;
+
+	/* Register port as active */
+	__ASSERT(cfg->port < MAX_PORT_COUNT, "Too many ports");
+	data->ports[cfg->port] = port;
+
+	return 0;
+}
+
+static void gpio_siwx91x_isr(const struct device *parent)
+{
+	const struct gpio_siwx91x_common_config *pcfg = parent->config;
+	struct gpio_siwx91x_common_data *common = parent->data;
+	const struct device *port;
+	struct gpio_siwx91x_port_data *data;
+
+	ARRAY_FOR_EACH(common->interrupts, i) {
+		sl_gpio_port_t port_no = common->interrupts[i].port;
+		uint32_t pending = pcfg->reg->INTR[i].GPIO_INTR_STATUS_b.INTERRUPT_STATUS;
+
+		if (pending && port_no != INVALID_PORT) {
+			/* Clear interrupt */
+			pcfg->reg->INTR[i].GPIO_INTR_STATUS_b.INTERRUPT_STATUS = 1;
+			port = common->ports[port_no];
+			data = port->data;
+			gpio_fire_callbacks(&data->callbacks, port, BIT(common->interrupts[i].pin));
+		}
+	}
+}
+
+static uint32_t gpio_siwx91x_get_pending_int(const struct device *port)
+{
+	const struct gpio_siwx91x_port_config *cfg = port->config;
+	const struct device *parent = cfg->parent;
+	const struct gpio_siwx91x_common_config *pcfg = parent->config;
+	uint32_t status = 0;
+
+	ARRAY_FOR_EACH(pcfg->reg->INTR, i) {
+		if (pcfg->reg->INTR[i].GPIO_INTR_STATUS_b.INTERRUPT_STATUS) {
+			status |= BIT(i);
+		}
+	}
+	return status;
+}
+
+static DEVICE_API(gpio, gpio_siwx91x_api) = {
+	.pin_configure = gpio_siwx91x_pin_configure,
+	.port_get_raw = gpio_siwx91x_port_get,
+	.port_set_masked_raw = gpio_siwx91x_port_set_masked,
+	.port_set_bits_raw = gpio_siwx91x_port_set_bits,
+	.port_clear_bits_raw = gpio_siwx91x_port_clear_bits,
+	.port_toggle_bits = gpio_siwx91x_port_toggle_bits,
+	.pin_interrupt_configure = gpio_siwx91x_interrupt_configure,
+	.manage_callback = gpio_siwx91x_manage_callback,
+	.get_pending_int = gpio_siwx91x_get_pending_int,
+#ifdef CONFIG_GPIO_GET_DIRECTION
+	.port_get_direction = gpio_siwx91x_port_get_direction,
+#endif
+};
+
+#define GPIO_PORT_INIT(n)                                                                          \
+	static const struct gpio_siwx91x_port_config gpio_siwx91x_port_config##n = {               \
+		.common.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_NODE(n),                        \
+		.parent = DEVICE_DT_GET(DT_PARENT(n)),                                             \
+		.pads = DT_PROP(n, silabs_pads),                                                   \
+		.port = DT_REG_ADDR(n),                                                            \
+		.hal_port = (DT_PROP(DT_PARENT(n), silabs_ulp) ? SL_GPIO_ULP_PORT : 0) +           \
+			    DT_REG_ADDR(n),                                                        \
+		.ulp = DT_PROP(DT_PARENT(n), silabs_ulp),                                          \
+	};                                                                                         \
+	static struct gpio_siwx91x_port_data gpio_siwx91x_port_data##n;                            \
+                                                                                                   \
+	DEVICE_DT_DEFINE(n, gpio_siwx91x_init_port, NULL, &gpio_siwx91x_port_data##n,              \
+			 &gpio_siwx91x_port_config##n, PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY,    \
+			 &gpio_siwx91x_api);
+
+#define CONFIGURE_SHARED_INTERRUPT(node_id, prop, idx)                                             \
+	IRQ_CONNECT(DT_IRQ_BY_IDX(node_id, idx, irq), DT_IRQ_BY_IDX(node_id, idx, priority),       \
+		    gpio_siwx91x_isr, DEVICE_DT_GET(node_id), 0);                                  \
+	irq_enable(DT_IRQ_BY_IDX(node_id, idx, irq));
+
+static DEVICE_API(gpio, gpio_siwx91x_common_api) = { };
+
+#define GPIO_CONTROLLER_INIT(idx)                                                                  \
+	static const struct gpio_siwx91x_common_config gpio_siwx91x_config##idx = {                \
+		.reg = (EGPIO_Type *)DT_INST_REG_ADDR(idx),                                        \
+	};                                                                                         \
+	static struct gpio_siwx91x_common_data gpio_siwx91x_data##idx;                             \
+                                                                                                   \
+	static int gpio_siwx91x_init_controller_##idx(const struct device *dev)                    \
+	{                                                                                          \
+		struct gpio_siwx91x_common_data *data = dev->data;                                 \
+		int status;                                                                        \
+                                                                                                   \
+		status = sl_si91x_gpio_driver_enable_clock(                                        \
+			COND_CODE_1(DT_INST_PROP(idx, silabs_ulp), (ULPCLK_GPIO), (M4CLK_GPIO)));  \
+		if (status) {                                                                      \
+			return -ENODEV;                                                            \
+		}                                                                                  \
+		ARRAY_FOR_EACH(data->interrupts, i) {                                              \
+			data->interrupts[i].port = INVALID_PORT;                                   \
+		}                                                                                  \
+		DT_INST_FOREACH_PROP_ELEM(idx, interrupt_names, CONFIGURE_SHARED_INTERRUPT);       \
+		return 0;                                                                          \
+	}                                                                                          \
+	DEVICE_DT_INST_DEFINE(idx, gpio_siwx91x_init_controller_##idx, NULL,                       \
+			      &gpio_siwx91x_data##idx, &gpio_siwx91x_config##idx,                  \
+			      PRE_KERNEL_1, CONFIG_GPIO_SILABS_SIWX91X_COMMON_INIT_PRIORITY,       \
+			      &gpio_siwx91x_common_api);                                           \
+	DT_INST_FOREACH_CHILD_STATUS_OKAY(idx, GPIO_PORT_INIT);
+
+DT_INST_FOREACH_STATUS_OKAY(GPIO_CONTROLLER_INIT)
diff --git a/drivers/gpio/gpio_silabs_siwx91x_uulp.c b/drivers/gpio/gpio_silabs_siwx91x_uulp.c
new file mode 100644
index 00000000000..ff9389eacdb
--- /dev/null
+++ b/drivers/gpio/gpio_silabs_siwx91x_uulp.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT silabs_siwx91x_gpio_uulp
+
+#include "sl_si91x_driver_gpio.h"
+#include "sl_status.h"
+
+#include <errno.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/irq.h>
+
+/* Zephyr GPIO header must be included after driver, due to symbol conflicts
+ * for GPIO_INPUT and GPIO_OUTPUT between preprocessor macros in the Zephyr
+ * API and struct member register definitions for the SiWx91x device.
+ */
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_utils.h>
+
+#define UULP_GPIO_COUNT           5
+#define UULP_REG_INTERRUPT_CONFIG 0x10
+
+/* Types */
+struct gpio_siwx91x_uulp_config {
+	/* gpio_driver_config needs to be first */
+	struct gpio_driver_config common;
+};
+
+struct gpio_siwx91x_uulp_data {
+	/* gpio_driver_data needs to be first */
+	struct gpio_driver_data common;
+	/* port ISR callback routine address */
+	sys_slist_t callbacks;
+};
+
+/* Functions */
+static int gpio_siwx91x_uulp_pin_configure(const struct device *dev, gpio_pin_t pin,
+					   gpio_flags_t flags)
+{
+	if (flags & (GPIO_SINGLE_ENDED | GPIO_PULL_UP | GPIO_PULL_DOWN)) {
+		return -ENOTSUP;
+	}
+
+	/* Enable input */
+	sl_si91x_gpio_select_uulp_npss_receiver(pin, (flags & GPIO_INPUT) ? 1 : 0);
+
+	/* Select GPIO mode */
+	sl_si91x_gpio_set_uulp_npss_pin_mux(pin, 0);
+
+	if (flags & GPIO_OUTPUT_INIT_HIGH) {
+		sl_si91x_gpio_set_uulp_npss_pin_value(pin, 1);
+	} else if (flags & GPIO_OUTPUT_INIT_LOW) {
+		sl_si91x_gpio_set_uulp_npss_pin_value(pin, 0);
+	}
+
+	/* Enable output */
+	sl_si91x_gpio_set_uulp_npss_direction(pin, (flags & GPIO_OUTPUT) ? 0 : 1);
+
+	return 0;
+}
+
+static int gpio_siwx91x_uulp_port_get(const struct device *port, gpio_port_value_t *value)
+{
+	for (size_t i = 0; i < UULP_GPIO_COUNT; i++) {
+		WRITE_BIT(*value, i, sl_si91x_gpio_get_uulp_npss_pin(i));
+	}
+
+	return 0;
+}
+
+static int gpio_siwx91x_uulp_port_set_masked(const struct device *port, gpio_port_pins_t mask,
+					     gpio_port_value_t value)
+{
+	for (size_t i = 0; i < UULP_GPIO_COUNT; i++) {
+		if (mask & BIT(i)) {
+			sl_si91x_gpio_set_uulp_npss_pin_value(i, FIELD_GET(BIT(i), value));
+		}
+	}
+
+	return 0;
+}
+
+static int gpio_siwx91x_uulp_port_set_bits(const struct device *port, gpio_port_pins_t pins)
+{
+	for (size_t i = 0; i < UULP_GPIO_COUNT; i++) {
+		if (FIELD_GET(BIT(i), pins)) {
+			sl_si91x_gpio_set_uulp_npss_pin_value(i, 1);
+		}
+	}
+
+	return 0;
+}
+
+static int gpio_siwx91x_uulp_port_clear_bits(const struct device *port, gpio_port_pins_t pins)
+{
+	for (size_t i = 0; i < UULP_GPIO_COUNT; i++) {
+		if (FIELD_GET(BIT(i), pins)) {
+			sl_si91x_gpio_set_uulp_npss_pin_value(i, 0);
+		}
+	}
+
+	return 0;
+}
+
+static int gpio_siwx91x_uulp_port_toggle_bits(const struct device *port, gpio_port_pins_t pins)
+{
+	for (size_t i = 0; i < UULP_GPIO_COUNT; i++) {
+		if (FIELD_GET(BIT(i), pins)) {
+			sl_si91x_gpio_toggle_uulp_npss_pin(i);
+		}
+	}
+
+	return 0;
+}
+
+static int gpio_siwx91x_uulp_manage_callback(const struct device *port,
+					     struct gpio_callback *callback, bool set)
+{
+	struct gpio_siwx91x_uulp_data *data = port->data;
+
+	return gpio_manage_callback(&data->callbacks, callback, set);
+}
+
+static int gpio_siwx91x_uulp_interrupt_configure(const struct device *port, gpio_pin_t pin,
+						 enum gpio_int_mode mode, enum gpio_int_trig trig)
+{
+	uint32_t flags = 0;
+
+	if (mode == GPIO_INT_MODE_DISABLED) {
+		sl_si91x_gpio_configure_uulp_interrupt(flags, pin);
+		sl_si91x_gpio_clear_uulp_interrupt(BIT(pin));
+		sl_si91x_gpio_mask_uulp_npss_interrupt(BIT(pin));
+	} else {
+		if (trig == GPIO_INT_TRIG_LOW) {
+			flags = (mode == GPIO_INT_MODE_EDGE) ? SL_GPIO_INTERRUPT_FALL_EDGE
+							     : SL_GPIO_INTERRUPT_LEVEL_LOW;
+		} else if (trig == GPIO_INT_TRIG_HIGH) {
+			flags = (mode == GPIO_INT_MODE_EDGE) ? SL_GPIO_INTERRUPT_RISE_EDGE
+							     : SL_GPIO_INTERRUPT_LEVEL_HIGH;
+		} else if (trig == GPIO_INT_TRIG_BOTH) {
+			/* SL_GPIO_INTERRUPT_RISE_FALL_EDGE would make more sense, but HAL
+			 * implementation is buggy.
+			 */
+			flags = SL_GPIO_INTERRUPT_RISE_EDGE | SL_GPIO_INTERRUPT_FALL_EDGE;
+		}
+
+		sl_si91x_gpio_configure_uulp_interrupt(flags, pin);
+	}
+	return 0;
+}
+
+static void gpio_siwx91x_uulp_isr(const struct device *port)
+{
+	struct gpio_siwx91x_uulp_data *data = port->data;
+	uint8_t pins = sl_si91x_gpio_get_uulp_interrupt_status();
+
+	sl_si91x_gpio_clear_uulp_interrupt(pins);
+
+	gpio_fire_callbacks(&data->callbacks, port, pins);
+}
+
+static DEVICE_API(gpio, gpio_siwx91x_uulp_api) = {
+	.pin_configure = gpio_siwx91x_uulp_pin_configure,
+#ifdef CONFIG_GPIO_GET_CONFIG
+	.pin_get_config = NULL,
+#endif
+	.port_get_raw = gpio_siwx91x_uulp_port_get,
+	.port_set_masked_raw = gpio_siwx91x_uulp_port_set_masked,
+	.port_set_bits_raw = gpio_siwx91x_uulp_port_set_bits,
+	.port_clear_bits_raw = gpio_siwx91x_uulp_port_clear_bits,
+	.port_toggle_bits = gpio_siwx91x_uulp_port_toggle_bits,
+	.pin_interrupt_configure = gpio_siwx91x_uulp_interrupt_configure,
+	.manage_callback = gpio_siwx91x_uulp_manage_callback,
+	.get_pending_int = NULL,
+#ifdef CONFIG_GPIO_GET_DIRECTION
+	.port_get_direction = NULL,
+#endif
+};
+
+#define GPIO_PORT_INIT(idx)                                                                        \
+	static const struct gpio_siwx91x_uulp_config gpio_siwx91x_port_config##idx = {             \
+		.common.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx),                      \
+	};                                                                                         \
+	static struct gpio_siwx91x_uulp_data gpio_siwx91x_port_data##idx;                          \
+                                                                                                   \
+	static int gpio_siwx91x_init_uulp_##idx(const struct device *dev)                          \
+	{                                                                                          \
+		sys_write32(0, DT_INST_REG_ADDR_BY_NAME(idx, int) + UULP_REG_INTERRUPT_CONFIG);    \
+		IRQ_CONNECT(DT_INST_IRQ(idx, irq), DT_INST_IRQ(idx, priority),                     \
+			    gpio_siwx91x_uulp_isr, DEVICE_DT_GET(DT_DRV_INST(idx)), 0);            \
+		irq_enable(DT_INST_IRQ(idx, irq));                                                 \
+		return 0;                                                                          \
+	}                                                                                          \
+	DEVICE_DT_INST_DEFINE(idx, gpio_siwx91x_init_uulp_##idx, NULL,                             \
+			      &gpio_siwx91x_port_data##idx, &gpio_siwx91x_port_config##idx,        \
+			      PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &gpio_siwx91x_uulp_api);
+
+DT_INST_FOREACH_STATUS_OKAY(GPIO_PORT_INIT)
diff --git a/drivers/gpio/gpio_stm32.c b/drivers/gpio/gpio_stm32.c
index 29b243b3d06..09881a4dd01 100644
--- a/drivers/gpio/gpio_stm32.c
+++ b/drivers/gpio/gpio_stm32.c
@@ -91,6 +91,23 @@ static int gpio_stm32_flags_to_conf(gpio_flags_t flags, uint32_t *pincfg)
 		*pincfg = STM32_PINCFG_MODE_ANALOG;
 	}
 
+#if !defined(CONFIG_SOC_SERIES_STM32F1X)
+	switch (flags & (STM32_GPIO_SPEED_MASK << STM32_GPIO_SPEED_SHIFT)) {
+	case STM32_GPIO_VERY_HIGH_SPEED:
+		*pincfg |= STM32_OSPEEDR_VERY_HIGH_SPEED;
+		break;
+	case STM32_GPIO_HIGH_SPEED:
+		*pincfg |= STM32_OSPEEDR_HIGH_SPEED;
+		break;
+	case STM32_GPIO_MEDIUM_SPEED:
+		*pincfg |= STM32_OSPEEDR_MEDIUM_SPEED;
+		break;
+	default:
+		*pincfg |= STM32_OSPEEDR_LOW_SPEED;
+		break;
+	}
+#endif /* !CONFIG_SOC_SERIES_STM32F1X */
+
 	return 0;
 }
 
@@ -772,3 +789,4 @@ GPIO_DEVICE_INIT_STM32_IF_OKAY(m, M);
 GPIO_DEVICE_INIT_STM32_IF_OKAY(n, N);
 GPIO_DEVICE_INIT_STM32_IF_OKAY(o, O);
 GPIO_DEVICE_INIT_STM32_IF_OKAY(p, P);
+GPIO_DEVICE_INIT_STM32_IF_OKAY(q, Q);
diff --git a/drivers/gpio/gpio_stm32.h b/drivers/gpio/gpio_stm32.h
index 65b6bcc95da..57578dc4952 100644
--- a/drivers/gpio/gpio_stm32.h
+++ b/drivers/gpio/gpio_stm32.h
@@ -19,186 +19,6 @@
 #include <zephyr/dt-bindings/pinctrl/stm32-pinctrl.h>
 #endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32f1_pinctrl) */
 
-/* GPIO buses definitions */
-
-#define STM32_PORT_NOT_AVAILABLE 0xFFFFFFFF
-
-#ifdef CONFIG_SOC_SERIES_STM32F0X
-#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB1
-#define STM32_PERIPH_GPIOA LL_AHB1_GRP1_PERIPH_GPIOA
-#define STM32_PERIPH_GPIOB LL_AHB1_GRP1_PERIPH_GPIOB
-#define STM32_PERIPH_GPIOC LL_AHB1_GRP1_PERIPH_GPIOC
-#define STM32_PERIPH_GPIOD LL_AHB1_GRP1_PERIPH_GPIOD
-#define STM32_PERIPH_GPIOE LL_AHB1_GRP1_PERIPH_GPIOE
-#define STM32_PERIPH_GPIOF LL_AHB1_GRP1_PERIPH_GPIOF
-#elif CONFIG_SOC_SERIES_STM32F1X
-#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_APB2
-#define STM32_PERIPH_GPIOA LL_APB2_GRP1_PERIPH_GPIOA
-#define STM32_PERIPH_GPIOB LL_APB2_GRP1_PERIPH_GPIOB
-#define STM32_PERIPH_GPIOC LL_APB2_GRP1_PERIPH_GPIOC
-#define STM32_PERIPH_GPIOD LL_APB2_GRP1_PERIPH_GPIOD
-#define STM32_PERIPH_GPIOE LL_APB2_GRP1_PERIPH_GPIOE
-#define STM32_PERIPH_GPIOF LL_APB2_GRP1_PERIPH_GPIOF
-#define STM32_PERIPH_GPIOG LL_APB2_GRP1_PERIPH_GPIOG
-#elif CONFIG_SOC_SERIES_STM32F2X
-#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB1
-#define STM32_PERIPH_GPIOA LL_AHB1_GRP1_PERIPH_GPIOA
-#define STM32_PERIPH_GPIOB LL_AHB1_GRP1_PERIPH_GPIOB
-#define STM32_PERIPH_GPIOC LL_AHB1_GRP1_PERIPH_GPIOC
-#define STM32_PERIPH_GPIOD LL_AHB1_GRP1_PERIPH_GPIOD
-#define STM32_PERIPH_GPIOE LL_AHB1_GRP1_PERIPH_GPIOE
-#define STM32_PERIPH_GPIOF LL_AHB1_GRP1_PERIPH_GPIOF
-#define STM32_PERIPH_GPIOG LL_AHB1_GRP1_PERIPH_GPIOG
-#define STM32_PERIPH_GPIOH LL_AHB1_GRP1_PERIPH_GPIOH
-#define STM32_PERIPH_GPIOI LL_AHB1_GRP1_PERIPH_GPIOI
-#elif CONFIG_SOC_SERIES_STM32F3X
-#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB1
-#define STM32_PERIPH_GPIOA LL_AHB1_GRP1_PERIPH_GPIOA
-#define STM32_PERIPH_GPIOB LL_AHB1_GRP1_PERIPH_GPIOB
-#define STM32_PERIPH_GPIOC LL_AHB1_GRP1_PERIPH_GPIOC
-#define STM32_PERIPH_GPIOD LL_AHB1_GRP1_PERIPH_GPIOD
-#define STM32_PERIPH_GPIOE LL_AHB1_GRP1_PERIPH_GPIOE
-#define STM32_PERIPH_GPIOF LL_AHB1_GRP1_PERIPH_GPIOF
-#define STM32_PERIPH_GPIOG LL_AHB1_GRP1_PERIPH_GPIOG
-#define STM32_PERIPH_GPIOH LL_AHB1_GRP1_PERIPH_GPIOH
-#elif CONFIG_SOC_SERIES_STM32F4X
-#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB1
-#define STM32_PERIPH_GPIOA LL_AHB1_GRP1_PERIPH_GPIOA
-#define STM32_PERIPH_GPIOB LL_AHB1_GRP1_PERIPH_GPIOB
-#define STM32_PERIPH_GPIOC LL_AHB1_GRP1_PERIPH_GPIOC
-#define STM32_PERIPH_GPIOD LL_AHB1_GRP1_PERIPH_GPIOD
-#define STM32_PERIPH_GPIOE LL_AHB1_GRP1_PERIPH_GPIOE
-#define STM32_PERIPH_GPIOF LL_AHB1_GRP1_PERIPH_GPIOF
-#define STM32_PERIPH_GPIOG LL_AHB1_GRP1_PERIPH_GPIOG
-#define STM32_PERIPH_GPIOH LL_AHB1_GRP1_PERIPH_GPIOH
-#define STM32_PERIPH_GPIOI LL_AHB1_GRP1_PERIPH_GPIOI
-#define STM32_PERIPH_GPIOJ LL_AHB1_GRP1_PERIPH_GPIOJ
-#define STM32_PERIPH_GPIOK LL_AHB1_GRP1_PERIPH_GPIOK
-#elif CONFIG_SOC_SERIES_STM32F7X
-#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB1
-#define STM32_PERIPH_GPIOA LL_AHB1_GRP1_PERIPH_GPIOA
-#define STM32_PERIPH_GPIOB LL_AHB1_GRP1_PERIPH_GPIOB
-#define STM32_PERIPH_GPIOC LL_AHB1_GRP1_PERIPH_GPIOC
-#define STM32_PERIPH_GPIOD LL_AHB1_GRP1_PERIPH_GPIOD
-#define STM32_PERIPH_GPIOE LL_AHB1_GRP1_PERIPH_GPIOE
-#define STM32_PERIPH_GPIOF LL_AHB1_GRP1_PERIPH_GPIOF
-#define STM32_PERIPH_GPIOG LL_AHB1_GRP1_PERIPH_GPIOG
-#define STM32_PERIPH_GPIOH LL_AHB1_GRP1_PERIPH_GPIOH
-#define STM32_PERIPH_GPIOI LL_AHB1_GRP1_PERIPH_GPIOI
-#define STM32_PERIPH_GPIOJ LL_AHB1_GRP1_PERIPH_GPIOJ
-#define STM32_PERIPH_GPIOK LL_AHB1_GRP1_PERIPH_GPIOK
-#elif CONFIG_SOC_SERIES_STM32H7X
-#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB4
-#define STM32_PERIPH_GPIOA LL_AHB4_GRP1_PERIPH_GPIOA
-#define STM32_PERIPH_GPIOB LL_AHB4_GRP1_PERIPH_GPIOB
-#define STM32_PERIPH_GPIOC LL_AHB4_GRP1_PERIPH_GPIOC
-#define STM32_PERIPH_GPIOD LL_AHB4_GRP1_PERIPH_GPIOD
-#define STM32_PERIPH_GPIOE LL_AHB4_GRP1_PERIPH_GPIOE
-#define STM32_PERIPH_GPIOF LL_AHB4_GRP1_PERIPH_GPIOF
-#define STM32_PERIPH_GPIOG LL_AHB4_GRP1_PERIPH_GPIOG
-#define STM32_PERIPH_GPIOH LL_AHB4_GRP1_PERIPH_GPIOH
-#define STM32_PERIPH_GPIOI LL_AHB4_GRP1_PERIPH_GPIOI
-#define STM32_PERIPH_GPIOJ LL_AHB4_GRP1_PERIPH_GPIOJ
-#define STM32_PERIPH_GPIOK LL_AHB4_GRP1_PERIPH_GPIOK
-#elif CONFIG_SOC_SERIES_STM32H7RSX
-#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB4
-#define STM32_PERIPH_GPIOA LL_AHB4_GRP1_PERIPH_GPIOA
-#define STM32_PERIPH_GPIOB LL_AHB4_GRP1_PERIPH_GPIOB
-#define STM32_PERIPH_GPIOC LL_AHB4_GRP1_PERIPH_GPIOC
-#define STM32_PERIPH_GPIOD LL_AHB4_GRP1_PERIPH_GPIOD
-#define STM32_PERIPH_GPIOE LL_AHB4_GRP1_PERIPH_GPIOE
-#define STM32_PERIPH_GPIOF LL_AHB4_GRP1_PERIPH_GPIOF
-#define STM32_PERIPH_GPIOG LL_AHB4_GRP1_PERIPH_GPIOG
-#define STM32_PERIPH_GPIOH LL_AHB4_GRP1_PERIPH_GPIOH
-#define STM32_PERIPH_GPIOM LL_AHB4_GRP1_PERIPH_GPIOM
-#define STM32_PERIPH_GPION LL_AHB4_GRP1_PERIPH_GPION
-#define STM32_PERIPH_GPIOO LL_AHB4_GRP1_PERIPH_GPIOO
-#define STM32_PERIPH_GPIOP LL_AHB4_GRP1_PERIPH_GPIOP
-#elif CONFIG_SOC_SERIES_STM32G0X
-#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_IOP
-#define STM32_PERIPH_GPIOA LL_IOP_GRP1_PERIPH_GPIOA
-#define STM32_PERIPH_GPIOB LL_IOP_GRP1_PERIPH_GPIOB
-#define STM32_PERIPH_GPIOC LL_IOP_GRP1_PERIPH_GPIOC
-#define STM32_PERIPH_GPIOD LL_IOP_GRP1_PERIPH_GPIOD
-#define STM32_PERIPH_GPIOE LL_IOP_GRP1_PERIPH_GPIOE
-#define STM32_PERIPH_GPIOF LL_IOP_GRP1_PERIPH_GPIOF
-#elif CONFIG_SOC_SERIES_STM32L0X
-#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_IOP
-#define STM32_PERIPH_GPIOA LL_IOP_GRP1_PERIPH_GPIOA
-#define STM32_PERIPH_GPIOB LL_IOP_GRP1_PERIPH_GPIOB
-#define STM32_PERIPH_GPIOC LL_IOP_GRP1_PERIPH_GPIOC
-#define STM32_PERIPH_GPIOD LL_IOP_GRP1_PERIPH_GPIOD
-#define STM32_PERIPH_GPIOE LL_IOP_GRP1_PERIPH_GPIOE
-#define STM32_PERIPH_GPIOH LL_IOP_GRP1_PERIPH_GPIOH
-#elif CONFIG_SOC_SERIES_STM32L1X
-#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB1
-#define STM32_PERIPH_GPIOA LL_AHB1_GRP1_PERIPH_GPIOA
-#define STM32_PERIPH_GPIOB LL_AHB1_GRP1_PERIPH_GPIOB
-#define STM32_PERIPH_GPIOC LL_AHB1_GRP1_PERIPH_GPIOC
-#define STM32_PERIPH_GPIOD LL_AHB1_GRP1_PERIPH_GPIOD
-#define STM32_PERIPH_GPIOE LL_AHB1_GRP1_PERIPH_GPIOE
-#define STM32_PERIPH_GPIOF LL_AHB1_GRP1_PERIPH_GPIOF
-#define STM32_PERIPH_GPIOG LL_AHB1_GRP1_PERIPH_GPIOG
-#define STM32_PERIPH_GPIOH LL_AHB1_GRP1_PERIPH_GPIOH
-#elif CONFIG_SOC_SERIES_STM32L4X
-#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB2
-#define STM32_PERIPH_GPIOA LL_AHB2_GRP1_PERIPH_GPIOA
-#define STM32_PERIPH_GPIOB LL_AHB2_GRP1_PERIPH_GPIOB
-#define STM32_PERIPH_GPIOC LL_AHB2_GRP1_PERIPH_GPIOC
-#define STM32_PERIPH_GPIOD LL_AHB2_GRP1_PERIPH_GPIOD
-#define STM32_PERIPH_GPIOE LL_AHB2_GRP1_PERIPH_GPIOE
-#define STM32_PERIPH_GPIOF LL_AHB2_GRP1_PERIPH_GPIOF
-#define STM32_PERIPH_GPIOG LL_AHB2_GRP1_PERIPH_GPIOG
-#define STM32_PERIPH_GPIOH LL_AHB2_GRP1_PERIPH_GPIOH
-#define STM32_PERIPH_GPIOI LL_AHB2_GRP1_PERIPH_GPIOI
-#elif CONFIG_SOC_SERIES_STM32L5X
-#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB2
-#define STM32_PERIPH_GPIOA LL_AHB2_GRP1_PERIPH_GPIOA
-#define STM32_PERIPH_GPIOB LL_AHB2_GRP1_PERIPH_GPIOB
-#define STM32_PERIPH_GPIOC LL_AHB2_GRP1_PERIPH_GPIOC
-#define STM32_PERIPH_GPIOD LL_AHB2_GRP1_PERIPH_GPIOD
-#define STM32_PERIPH_GPIOE LL_AHB2_GRP1_PERIPH_GPIOE
-#define STM32_PERIPH_GPIOF LL_AHB2_GRP1_PERIPH_GPIOF
-#define STM32_PERIPH_GPIOG LL_AHB2_GRP1_PERIPH_GPIOG
-#define STM32_PERIPH_GPIOH LL_AHB2_GRP1_PERIPH_GPIOH
-#elif CONFIG_SOC_SERIES_STM32MP1X
-#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB4
-#define STM32_PERIPH_GPIOA LL_AHB4_GRP1_PERIPH_GPIOA
-#define STM32_PERIPH_GPIOB LL_AHB4_GRP1_PERIPH_GPIOB
-#define STM32_PERIPH_GPIOC LL_AHB4_GRP1_PERIPH_GPIOC
-#define STM32_PERIPH_GPIOD LL_AHB4_GRP1_PERIPH_GPIOD
-#define STM32_PERIPH_GPIOE LL_AHB4_GRP1_PERIPH_GPIOE
-#define STM32_PERIPH_GPIOF LL_AHB4_GRP1_PERIPH_GPIOF
-#define STM32_PERIPH_GPIOG LL_AHB4_GRP1_PERIPH_GPIOG
-#define STM32_PERIPH_GPIOH LL_AHB4_GRP1_PERIPH_GPIOH
-#define STM32_PERIPH_GPIOI LL_AHB4_GRP1_PERIPH_GPIOI
-#define STM32_PERIPH_GPIOJ LL_AHB4_GRP1_PERIPH_GPIOJ
-#define STM32_PERIPH_GPIOK LL_AHB4_GRP1_PERIPH_GPIOK
-#elif CONFIG_SOC_SERIES_STM32WBX
-#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB2
-#define STM32_PERIPH_GPIOA LL_AHB2_GRP1_PERIPH_GPIOA
-#define STM32_PERIPH_GPIOB LL_AHB2_GRP1_PERIPH_GPIOB
-#define STM32_PERIPH_GPIOC LL_AHB2_GRP1_PERIPH_GPIOC
-#define STM32_PERIPH_GPIOD LL_AHB2_GRP1_PERIPH_GPIOD
-#define STM32_PERIPH_GPIOE LL_AHB2_GRP1_PERIPH_GPIOE
-#define STM32_PERIPH_GPIOH LL_AHB2_GRP1_PERIPH_GPIOH
-#elif CONFIG_SOC_SERIES_STM32G4X
-#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB2
-#define STM32_PERIPH_GPIOA LL_AHB2_GRP1_PERIPH_GPIOA
-#define STM32_PERIPH_GPIOB LL_AHB2_GRP1_PERIPH_GPIOB
-#define STM32_PERIPH_GPIOC LL_AHB2_GRP1_PERIPH_GPIOC
-#define STM32_PERIPH_GPIOD LL_AHB2_GRP1_PERIPH_GPIOD
-#define STM32_PERIPH_GPIOE LL_AHB2_GRP1_PERIPH_GPIOE
-#define STM32_PERIPH_GPIOF LL_AHB2_GRP1_PERIPH_GPIOF
-#define STM32_PERIPH_GPIOG LL_AHB2_GRP1_PERIPH_GPIOG
-#elif CONFIG_SOC_SERIES_STM32WLX
-#define STM32_CLOCK_BUS_GPIO STM32_CLOCK_BUS_AHB2
-#define STM32_PERIPH_GPIOA LL_AHB2_GRP1_PERIPH_GPIOA
-#define STM32_PERIPH_GPIOB LL_AHB2_GRP1_PERIPH_GPIOB
-#define STM32_PERIPH_GPIOC LL_AHB2_GRP1_PERIPH_GPIOC
-#define STM32_PERIPH_GPIOH LL_AHB2_GRP1_PERIPH_GPIOH
-#endif /* CONFIG_SOC_SERIES_* */
-
 #ifdef CONFIG_SOC_SERIES_STM32F1X
 #define STM32_PINCFG_MODE_OUTPUT        (STM32_MODE_OUTPUT     \
 					 | STM32_CNF_GP_OUTPUT \
diff --git a/drivers/gpio/gpio_sy1xx.c b/drivers/gpio/gpio_sy1xx.c
new file mode 100644
index 00000000000..7bb57472838
--- /dev/null
+++ b/drivers/gpio/gpio_sy1xx.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2024 sensry.io
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT sensry_sy1xx_gpio
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(sy1xx_gpio, CONFIG_GPIO_LOG_LEVEL);
+
+#include <errno.h>
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/drivers/gpio/gpio_utils.h>
+#include <pinctrl_soc.h>
+#include <zephyr/drivers/pinctrl.h>
+
+#define SY1XX_GPIO_GET_IN_OFFS  0x00
+#define SY1XX_GPIO_GET_OUT_OFFS 0x04
+#define SY1XX_GPIO_SET_OFFS     0x1c
+#define SY1XX_GPIO_CLR_OFFS     0x20
+
+struct sy1xx_gpio_config {
+	/* Base address for GPIO port*/
+	uint32_t port_base_addr;
+	/* configuration base address for the pad config */
+	uint32_t pad_cfg_offs;
+	/* mask of pins which are allowed to modify by the gpio driver */
+	uint32_t pin_mask;
+};
+
+/* Function prototypes for the GPIO API */
+static int sy1xx_gpio_driver_configure(const struct device *dev, gpio_pin_t pin,
+				       gpio_flags_t flags);
+static int sy1xx_gpio_driver_port_get_raw(const struct device *dev, gpio_port_value_t *value);
+static int sy1xx_gpio_driver_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
+						 gpio_port_value_t value);
+static int sy1xx_gpio_driver_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins);
+static int sy1xx_gpio_driver_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins);
+static int sy1xx_gpio_driver_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins);
+
+static int sy1xx_gpio_driver_init(const struct device *dev)
+{
+	return 0;
+}
+
+int sy1xx_gpio_driver_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags)
+{
+	const struct sy1xx_gpio_config *const cfg = dev->config;
+
+	if (((BIT(pin)) & cfg->pin_mask) == 0) {
+		return -EINVAL;
+	}
+
+	/* initialize the pinctrl config for the given gpio pin */
+	pinctrl_soc_pin_t pcfg = {
+		.addr = cfg->pad_cfg_offs + ROUND_DOWN(pin, 4),
+		.iro = (pin % 4) * 8,
+		.cfg = 0,
+	};
+
+	/* translate gpio flags into pinctrl config */
+	if (flags & GPIO_INPUT) {
+
+		if (flags & GPIO_PULL_UP) {
+			pcfg.cfg |= BIT(SY1XX_PAD_PULL_UP_OFFS);
+		}
+		if (flags & GPIO_PULL_DOWN) {
+			pcfg.cfg |= BIT(SY1XX_PAD_PULL_DOWN_OFFS);
+		}
+
+	} else if (flags & GPIO_OUTPUT) {
+		pcfg.cfg |= BIT(SY1XX_PAD_DIR_OFFS);
+
+		if (flags & GPIO_OUTPUT_INIT_LOW) {
+			sy1xx_gpio_driver_port_set_masked_raw(dev, BIT(pin), 0);
+		}
+		if (flags & GPIO_OUTPUT_INIT_HIGH) {
+			sy1xx_gpio_driver_port_set_masked_raw(dev, BIT(pin), BIT(pin));
+		}
+
+	} else if (flags == GPIO_DISCONNECTED) {
+		pcfg.cfg |= BIT(SY1XX_PAD_TRISTATE_OFFS);
+
+	} else {
+		LOG_ERR("%s: unsupported pinctrl mode for pin: %u", dev->name, pin);
+		return -ENOTSUP;
+	}
+
+	/* PAD config */
+	int32_t ret = pinctrl_configure_pins(&pcfg, 1, PINCTRL_STATE_DEFAULT);
+
+	if (ret != 0) {
+		LOG_ERR("%s: failed to apply pinctrl for pin: %u", dev->name, pin);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int sy1xx_gpio_driver_port_get_raw(const struct device *dev, gpio_port_value_t *value)
+{
+	const struct sy1xx_gpio_config *const cfg = dev->config;
+
+	*value = sys_read32(cfg->port_base_addr | SY1XX_GPIO_GET_IN_OFFS);
+	return 0;
+}
+
+int sy1xx_gpio_driver_port_set_masked_raw(const struct device *dev, gpio_port_pins_t mask,
+					  gpio_port_value_t value)
+{
+	const struct sy1xx_gpio_config *const cfg = dev->config;
+
+	uint32_t set_mask = (mask & value) & (cfg->pin_mask);
+	uint32_t clr_mask = (mask & (~value)) & (cfg->pin_mask);
+
+	sy1xx_gpio_driver_port_set_bits_raw(dev, set_mask);
+	sy1xx_gpio_driver_port_clear_bits_raw(dev, clr_mask);
+	return 0;
+}
+
+int sy1xx_gpio_driver_port_set_bits_raw(const struct device *dev, gpio_port_pins_t pins)
+{
+	const struct sy1xx_gpio_config *const cfg = dev->config;
+
+	/* affects only pins that are set to logical '1' */
+	sys_write32((uint32_t)pins, cfg->port_base_addr | SY1XX_GPIO_SET_OFFS);
+	return 0;
+}
+
+int sy1xx_gpio_driver_port_clear_bits_raw(const struct device *dev, gpio_port_pins_t pins)
+{
+	const struct sy1xx_gpio_config *const cfg = dev->config;
+
+	/* affects only pins that are set to logical '1' */
+	sys_write32((uint32_t)pins, cfg->port_base_addr | SY1XX_GPIO_CLR_OFFS);
+	return 0;
+}
+
+int sy1xx_gpio_driver_port_toggle_bits(const struct device *dev, gpio_port_pins_t pins)
+{
+	const struct sy1xx_gpio_config *const cfg = dev->config;
+
+	uint32_t current = sys_read32(cfg->port_base_addr | SY1XX_GPIO_GET_OUT_OFFS);
+
+	sy1xx_gpio_driver_port_set_masked_raw(dev, pins, ~current);
+	return 0;
+}
+
+/* Define the GPIO API structure */
+static DEVICE_API(gpio, sy1xx_gpio_driver_api) = {
+	.pin_configure = sy1xx_gpio_driver_configure,
+	.port_get_raw = sy1xx_gpio_driver_port_get_raw,
+	.port_set_masked_raw = sy1xx_gpio_driver_port_set_masked_raw,
+	.port_set_bits_raw = sy1xx_gpio_driver_port_set_bits_raw,
+	.port_clear_bits_raw = sy1xx_gpio_driver_port_clear_bits_raw,
+	.port_toggle_bits = sy1xx_gpio_driver_port_toggle_bits,
+};
+
+#define SY1XX_GPIO_INIT(n)                                                                         \
+                                                                                                   \
+	static const struct sy1xx_gpio_config sy1xx_gpio_##n##_config = {                          \
+		.port_base_addr = (uint32_t)DT_INST_REG_ADDR_BY_IDX(n, 0),                         \
+		.pad_cfg_offs = (uint32_t)DT_INST_PROP(n, pad_cfg),                                \
+		.pin_mask = (uint32_t)GPIO_PORT_PIN_MASK_FROM_DT_INST(n)};                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, sy1xx_gpio_driver_init, NULL, NULL, &sy1xx_gpio_##n##_config,     \
+			      PRE_KERNEL_1, CONFIG_GPIO_INIT_PRIORITY, &sy1xx_gpio_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(SY1XX_GPIO_INIT)
diff --git a/drivers/gpio/gpio_xlnx_ps_bank.c b/drivers/gpio/gpio_xlnx_ps_bank.c
index c06479c8f53..8f62dc95da2 100644
--- a/drivers/gpio/gpio_xlnx_ps_bank.c
+++ b/drivers/gpio/gpio_xlnx_ps_bank.c
@@ -454,7 +454,7 @@ static const struct gpio_xlnx_ps_bank_dev_cfg gpio_xlnx_ps_bank##idx##_cfg = {\
 	.common = {\
 		.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(idx),\
 	},\
-	.bank_index = idx,\
+	.bank_index = DT_INST_REG_ADDR(idx),\
 };\
 static struct gpio_xlnx_ps_bank_dev_data gpio_xlnx_ps_bank##idx##_data = {\
 	.base = 0,\
diff --git a/drivers/gpio/wch_gpio_ch32v00x.c b/drivers/gpio/wch_gpio_ch32v00x.c
index bc8566e12c5..c8d3d4954a8 100644
--- a/drivers/gpio/wch_gpio_ch32v00x.c
+++ b/drivers/gpio/wch_gpio_ch32v00x.c
@@ -53,7 +53,12 @@ static int gpio_ch32v00x_configure(const struct device *dev, gpio_pin_t pin, gpi
 		cnf_mode = 0x00;
 	}
 
-	regs->CFGLR = (regs->CFGLR & ~(0x0F << (4 * pin))) | (cnf_mode << (4 * pin));
+	if (pin < 8) {
+		regs->CFGLR = (regs->CFGLR & ~(0x0F << (4 * pin))) | (cnf_mode << (4 * pin));
+	} else {
+		regs->CFGHR =
+			(regs->CFGHR & ~(0x0F << ((pin - 8) * 4))) | (cnf_mode << ((pin - 8) * 4));
+	}
 	regs->BSHR = bshr;
 
 	return 0;
diff --git a/drivers/hdlc_rcp_if/Kconfig.uart b/drivers/hdlc_rcp_if/Kconfig.uart
index 38b180d0225..a48c8f0a96a 100644
--- a/drivers/hdlc_rcp_if/Kconfig.uart
+++ b/drivers/hdlc_rcp_if/Kconfig.uart
@@ -12,6 +12,7 @@ config HDLC_RCP_IF_UART
 	bool "UART HDLC interface for Zephyr Openthread RCP host"
 	default y
 	depends on DT_HAS_UART_HDLC_RCP_IF_ENABLED
+	depends on UART_INTERRUPT_DRIVEN
 
 config OPENTHREAD_HDLC_RCP_IF_UART_RX_RING_BUFFER_SIZE
 	int "Set HDLC RCP IF UART RX ring buffer size"
diff --git a/drivers/hdlc_rcp_if/hdlc_rcp_if_nxp.c b/drivers/hdlc_rcp_if/hdlc_rcp_if_nxp.c
index d6942037737..f66af5b349a 100644
--- a/drivers/hdlc_rcp_if/hdlc_rcp_if_nxp.c
+++ b/drivers/hdlc_rcp_if/hdlc_rcp_if_nxp.c
@@ -34,10 +34,10 @@
 #define LOG_LEVEL       CONFIG_HDLC_RCP_IF_DRIVER_LOG_LEVEL
 LOG_MODULE_REGISTER(LOG_MODULE_NAME);
 
-struct ot_hdlc_rcp_context {
+static struct ot_hdlc_rcp_context {
 	struct net_if *iface;
 	struct openthread_context *ot_context;
-};
+} ot_hdlc_rcp_ctx;
 
 /* -------------------------------------------------------------------------- */
 /*                             Private prototypes                             */
@@ -111,7 +111,7 @@ static const struct hdlc_api nxp_hdlc_api = {
 
 NET_DEVICE_DT_INST_DEFINE(0, NULL,                             /* Initialization Function */
 			  NULL,                                /* No PM API support */
-			  NULL,                                /* No context data */
+			  &ot_hdlc_rcp_ctx,                    /* HDLC RCP context data */
 			  NULL,                                /* Configuration info */
 			  CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, /* Initial priority */
 			  &nxp_hdlc_api,                       /* API interface functions */
diff --git a/drivers/hdlc_rcp_if/hdlc_rcp_if_uart.c b/drivers/hdlc_rcp_if/hdlc_rcp_if_uart.c
index f14f1f792c6..0157f4f3693 100644
--- a/drivers/hdlc_rcp_if/hdlc_rcp_if_uart.c
+++ b/drivers/hdlc_rcp_if/hdlc_rcp_if_uart.c
@@ -54,10 +54,10 @@ struct openthread_uart {
 OT_UART_DEFINE(ot_uart, CONFIG_OPENTHREAD_HDLC_RCP_IF_UART_RX_RING_BUFFER_SIZE,
 	       CONFIG_OPENTHREAD_HDLC_RCP_IF_UART_TX_RING_BUFFER_SIZE);
 
-struct ot_hdlc_rcp_context {
+static struct ot_hdlc_rcp_context {
 	struct net_if *iface;
 	struct openthread_context *ot_context;
-};
+} ot_hdlc_rcp_ctx;
 
 /* -------------------------------------------------------------------------- */
 /*                             Private functions                              */
@@ -210,7 +210,7 @@ static const struct hdlc_api uart_hdlc_api = {
 
 NET_DEVICE_DT_INST_DEFINE(0, NULL,                             /* Initialization Function */
 			  NULL,                                /* No PM API support */
-			  NULL,                                /* No context data */
+			  &ot_hdlc_rcp_ctx,                    /* HDLC RCP context data */
 			  NULL,                                /* Configuration info */
 			  CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, /* Initial priority */
 			  &uart_hdlc_api,                       /* API interface functions */
diff --git a/drivers/hwinfo/CMakeLists.txt b/drivers/hwinfo/CMakeLists.txt
index e6db830d865..548577d05bf 100644
--- a/drivers/hwinfo/CMakeLists.txt
+++ b/drivers/hwinfo/CMakeLists.txt
@@ -16,6 +16,7 @@ zephyr_library_sources_ifdef(CONFIG_HWINFO_ESP32       hwinfo_esp32.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_GECKO       hwinfo_gecko.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_IMXRT       hwinfo_imxrt.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_LITEX       hwinfo_litex.c)
+zephyr_library_sources_ifdef(CONFIG_HWINFO_MAX32       hwinfo_max32.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_RCM    hwinfo_mcux_rcm.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SIM    hwinfo_mcux_sim.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_MCUX_SRC    hwinfo_mcux_src.c)
@@ -25,12 +26,14 @@ zephyr_library_sources_ifdef(CONFIG_HWINFO_NRF         hwinfo_nrf.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_NUMAKER     hwinfo_numaker.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_NUMAKER_RMC hwinfo_numaker_rmc.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_PSOC6       hwinfo_psoc6.c)
+zephyr_library_sources_ifdef(CONFIG_HWINFO_RENESAS_RA  hwinfo_renesas_ra.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_RPI_PICO    hwinfo_rpi_pico.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_RW61X       hwinfo_rw61x.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_SAM         hwinfo_sam.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_SAM0        hwinfo_sam0.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_SAM4L       hwinfo_sam4l.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_SAM_RSTC    hwinfo_sam_rstc.c)
+zephyr_library_sources_ifdef(CONFIG_HWINFO_SILABS_S2   hwinfo_silabs_series2.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_SMARTBOND   hwinfo_smartbond.c)
 zephyr_library_sources_ifdef(CONFIG_HWINFO_STM32       hwinfo_stm32.c)
 # zephyr-keep-sorted-stop
diff --git a/drivers/hwinfo/Kconfig b/drivers/hwinfo/Kconfig
index 1fa1418b83f..966f3d399b3 100644
--- a/drivers/hwinfo/Kconfig
+++ b/drivers/hwinfo/Kconfig
@@ -122,7 +122,7 @@ config HWINFO_MCUX_SYSCON
 config HWINFO_IMXRT
 	bool "NXP i.mx RT device ID"
 	default y
-	depends on SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX
+	depends on SOC_SERIES_IMXRT10XX || SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X
 	select HWINFO_HAS_DRIVER
 	help
 	  Enable NXP i.mx RT hwinfo driver.
@@ -204,14 +204,21 @@ config HWINFO_PSOC6
 config HWINFO_GECKO
 	bool "GECKO hwinfo"
 	default y
-	depends on SOC_FAMILY_SILABS_S0 || SOC_FAMILY_SILABS_S1 || SOC_FAMILY_SILABS_S2
-	depends on !SOC_SERIES_EFR32MG21
-	depends on !SOC_SERIES_EFR32BG22
+	depends on SOC_FAMILY_SILABS_S0 || SOC_FAMILY_SILABS_S1
 	select HWINFO_HAS_DRIVER
 	select SOC_GECKO_RMU
 	help
 	  Enable Silabs GECKO hwinfo driver.
 
+config HWINFO_SILABS_S2
+	bool "Silabs Series 2 hwinfo"
+	default y
+	depends on SOC_FAMILY_SILABS_S2
+	select HWINFO_HAS_DRIVER
+	select SOC_GECKO_RMU
+	help
+	  Enable Silabs Series 2 hwinfo driver.
+
 config HWINFO_ANDES
 	bool "Andes system ID"
 	default y
@@ -257,4 +264,21 @@ config HWINFO_NUMAKER_RMC
 	help
 	  Enable Nuvoton NuMaker hwinfo driver backed up by RMC
 
+config HWINFO_MAX32
+	bool "MAX32 hwinfo"
+	default y
+	depends on SOC_FAMILY_MAX32
+	depends on !TRUSTED_EXECUTION_NONSECURE
+	select HWINFO_HAS_DRIVER
+	help
+	  Enable MAX32 hwinfo driver.
+
+config HWINFO_RENESAS_RA
+	bool "Renesas RA device ID"
+	default y
+	depends on SOC_FAMILY_RENESAS_RA
+	select HWINFO_HAS_DRIVER
+	help
+	  Enable RENESAS RA hwinfo driver
+
 endif
diff --git a/drivers/hwinfo/hwinfo_ambiq.c b/drivers/hwinfo/hwinfo_ambiq.c
index 80bcf62763a..c8173e0f813 100644
--- a/drivers/hwinfo/hwinfo_ambiq.c
+++ b/drivers/hwinfo/hwinfo_ambiq.c
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <am_mcu_apollo.h>
+#include <soc.h>
 #include <zephyr/drivers/hwinfo.h>
 #include <string.h>
 #include <zephyr/sys/byteorder.h>
diff --git a/drivers/hwinfo/hwinfo_imxrt.c b/drivers/hwinfo/hwinfo_imxrt.c
index ea748482f76..ef6ae27fa15 100644
--- a/drivers/hwinfo/hwinfo_imxrt.c
+++ b/drivers/hwinfo/hwinfo_imxrt.c
@@ -10,7 +10,11 @@
 #include <zephyr/sys/byteorder.h>
 
 struct imxrt_uid {
+#if CONFIG_SOC_SERIES_IMXRT118X
+	uint32_t id[4];
+#else
 	uint32_t id[2];
+#endif
 };
 
 ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
@@ -20,6 +24,11 @@ ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
 #ifdef CONFIG_SOC_SERIES_IMXRT11XX
 	dev_id.id[0] = sys_cpu_to_be32(OCOTP->FUSEN[17].FUSE);
 	dev_id.id[1] = sys_cpu_to_be32(OCOTP->FUSEN[16].FUSE);
+#elif CONFIG_SOC_SERIES_IMXRT118X
+	dev_id.id[0] = sys_cpu_to_be32(OCOTP_FSB->OTP_SHADOW_PARTA[15]);
+	dev_id.id[1] = sys_cpu_to_be32(OCOTP_FSB->OTP_SHADOW_PARTA[14]);
+	dev_id.id[2] = sys_cpu_to_be32(OCOTP_FSB->OTP_SHADOW_PARTA[13]);
+	dev_id.id[3] = sys_cpu_to_be32(OCOTP_FSB->OTP_SHADOW_PARTA[12]);
 #else
 	dev_id.id[0] = sys_cpu_to_be32(OCOTP->CFG2);
 	dev_id.id[1] = sys_cpu_to_be32(OCOTP->CFG1);
diff --git a/drivers/hwinfo/hwinfo_max32.c b/drivers/hwinfo/hwinfo_max32.c
new file mode 100644
index 00000000000..e0ec75dd722
--- /dev/null
+++ b/drivers/hwinfo/hwinfo_max32.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/hwinfo.h>
+#include <soc.h>
+#include <wrap_max32_sys.h>
+#include <string.h>
+#include <zephyr/sys/byteorder.h>
+
+ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
+{
+	uint8_t usn[MXC_SYS_USN_LEN];
+	int error;
+
+	error = Wrap_MXC_SYS_GetUSN(usn);
+	if (error != E_NO_ERROR) {
+		/* Error reading USN */
+		return error;
+	}
+
+	if (length > sizeof(usn)) {
+		length = sizeof(usn);
+	}
+
+	/* Provide device ID in big endian */
+	sys_memcpy_swap(buffer, usn, length);
+
+	return length;
+}
diff --git a/drivers/hwinfo/hwinfo_renesas_ra.c b/drivers/hwinfo/hwinfo_renesas_ra.c
new file mode 100644
index 00000000000..0b326d855fe
--- /dev/null
+++ b/drivers/hwinfo/hwinfo_renesas_ra.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc.h>
+#include <zephyr/drivers/hwinfo.h>
+
+ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
+{
+	bsp_unique_id_t const *unique_id = R_BSP_UniqueIdGet();
+	size_t len = MIN(length, sizeof(unique_id->unique_id_bytes));
+
+	memcpy(buffer, &unique_id->unique_id_bytes[0], len);
+
+	return len;
+}
diff --git a/drivers/hwinfo/hwinfo_silabs_series2.c b/drivers/hwinfo/hwinfo_silabs_series2.c
new file mode 100644
index 00000000000..bb7b45d9fe9
--- /dev/null
+++ b/drivers/hwinfo/hwinfo_silabs_series2.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/hwinfo.h>
+#include <zephyr/sys/byteorder.h>
+
+#include <string.h>
+
+#include <em_system.h>
+#include <em_rmu.h>
+
+/* Ensure that all possible reset causes have a definition */
+#ifndef EMU_RSTCAUSE_BOOSTON
+#define EMU_RSTCAUSE_BOOSTON 0
+#endif
+#ifndef EMU_RSTCAUSE_WDOG1
+#define EMU_RSTCAUSE_WDOG1 0
+#endif
+#ifndef EMU_RSTCAUSE_IOVDD1BOD
+#define EMU_RSTCAUSE_IOVDD1BOD 0
+#endif
+#ifndef EMU_RSTCAUSE_IOVDD2BOD
+#define EMU_RSTCAUSE_IOVDD2BOD 0
+#endif
+#ifndef EMU_RSTCAUSE_SETAMPER
+#define EMU_RSTCAUSE_SETAMPER 0
+#endif
+#ifndef EMU_RSTCAUSE_SESYSREQ
+#define EMU_RSTCAUSE_SESYSREQ 0
+#endif
+#ifndef EMU_RSTCAUSE_SELOCKUP
+#define EMU_RSTCAUSE_SELOCKUP 0
+#endif
+#ifndef EMU_RSTCAUSE_DCI
+#define EMU_RSTCAUSE_DCI 0
+#endif
+
+/* The Zephyr API expects hwinfo_get_reset_cause() to return 0 after hwinfo_clear_reset_cause() has
+ * been called. This matches the hardware behavior on Series 2, but not the HAL API. The HAL stores
+ * the reset cause upon first read, and returns this cached value on subsequent calls to the API
+ * to allow multiple subsystems to read the reset cause despite it having been cleared in hardware
+ * already. Emulate the hardware behavior while staying compatible with other users of the HAL API
+ * by keeping track of whether the reset cause should be considered cleared or not ourselves.
+ */
+static bool reset_cleared;
+
+ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
+{
+	uint64_t unique_id = sys_cpu_to_be64(SYSTEM_GetUnique());
+
+	if (length > sizeof(unique_id)) {
+		length = sizeof(unique_id);
+	}
+
+	memcpy(buffer, &unique_id, length);
+
+	return length;
+}
+
+int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
+{
+	uint32_t flags = 0;
+	uint32_t rmu = RMU_ResetCauseGet();
+
+	if (reset_cleared) {
+		*cause = 0;
+		return 0;
+	}
+
+	if (rmu & EMU_RSTCAUSE_POR) {
+		flags |= RESET_POR;
+	}
+
+	if (rmu & EMU_RSTCAUSE_PIN) {
+		flags |= RESET_PIN;
+	}
+
+	if (rmu & (EMU_RSTCAUSE_EM4 | EMU_RSTCAUSE_BOOSTON)) {
+		flags |= RESET_LOW_POWER_WAKE;
+	}
+
+	if (rmu & (EMU_RSTCAUSE_WDOG0 | EMU_RSTCAUSE_WDOG1)) {
+		flags |= RESET_WATCHDOG;
+	}
+
+	if (rmu & EMU_RSTCAUSE_LOCKUP) {
+		flags |= RESET_CPU_LOCKUP;
+	}
+
+	if (rmu & EMU_RSTCAUSE_SYSREQ) {
+		flags |= RESET_SOFTWARE;
+	}
+
+	if (rmu & (EMU_RSTCAUSE_DVDDBOD | EMU_RSTCAUSE_DVDDLEBOD | EMU_RSTCAUSE_DECBOD |
+		   EMU_RSTCAUSE_AVDDBOD | EMU_RSTCAUSE_IOVDD0BOD |
+		   EMU_RSTCAUSE_IOVDD1BOD | EMU_RSTCAUSE_IOVDD2BOD)) {
+		flags |= RESET_BROWNOUT;
+	}
+
+	if (rmu & (EMU_RSTCAUSE_SETAMPER | EMU_RSTCAUSE_SESYSREQ |
+		   EMU_RSTCAUSE_SELOCKUP | EMU_RSTCAUSE_DCI)) {
+		flags |= RESET_SECURITY;
+	}
+
+	*cause = flags;
+	return 0;
+}
+
+int z_impl_hwinfo_clear_reset_cause(void)
+{
+	RMU_ResetCauseClear();
+	reset_cleared = true;
+	return 0;
+}
+
+int z_impl_hwinfo_get_supported_reset_cause(uint32_t *supported)
+{
+	*supported = RESET_PIN | RESET_SOFTWARE | RESET_BROWNOUT | RESET_POR | RESET_WATCHDOG |
+		     RESET_SECURITY | RESET_LOW_POWER_WAKE | RESET_CPU_LOCKUP;
+	return 0;
+}
diff --git a/drivers/hwinfo/hwinfo_stm32.c b/drivers/hwinfo/hwinfo_stm32.c
index 1cd9688acc1..264b7eb11db 100644
--- a/drivers/hwinfo/hwinfo_stm32.c
+++ b/drivers/hwinfo/hwinfo_stm32.c
@@ -8,13 +8,28 @@
 #include <stm32_ll_utils.h>
 #include <stm32_ll_rcc.h>
 #if defined(CONFIG_SOC_SERIES_STM32H5X)
-#include <stm32_ll_icache.h>
+#include <zephyr/cache.h>
 #endif /* CONFIG_SOC_SERIES_STM32H5X */
 #include <stm32_ll_pwr.h>
 #include <zephyr/drivers/hwinfo.h>
 #include <string.h>
 #include <zephyr/sys/byteorder.h>
 
+#if defined(CONFIG_SOC_SERIES_STM32MP13X)
+
+/* No ll_utils for the stm32mp13x series, instead use the HAL functions */
+#define STM32_UID_WORD_0 HAL_GetUIDw2()
+#define STM32_UID_WORD_1 HAL_GetUIDw1()
+#define STM32_UID_WORD_2 HAL_GetUIDw0()
+
+#else
+
+#define STM32_UID_WORD_0 LL_GetUID_Word2()
+#define STM32_UID_WORD_1 LL_GetUID_Word1()
+#define STM32_UID_WORD_2 LL_GetUID_Word0()
+
+#endif /* CONFIG_SOC_SERIES_STM32MP13X */
+
 struct stm32_uid {
 	uint32_t id[3];
 };
@@ -24,15 +39,15 @@ ssize_t z_impl_hwinfo_get_device_id(uint8_t *buffer, size_t length)
 	struct stm32_uid dev_id;
 
 #if defined(CONFIG_SOC_SERIES_STM32H5X)
-	LL_ICACHE_Disable();
+	sys_cache_instr_disable();
 #endif /* CONFIG_SOC_SERIES_STM32H5X */
 
-	dev_id.id[0] = sys_cpu_to_be32(LL_GetUID_Word2());
-	dev_id.id[1] = sys_cpu_to_be32(LL_GetUID_Word1());
-	dev_id.id[2] = sys_cpu_to_be32(LL_GetUID_Word0());
+	dev_id.id[0] = sys_cpu_to_be32(STM32_UID_WORD_2);
+	dev_id.id[1] = sys_cpu_to_be32(STM32_UID_WORD_1);
+	dev_id.id[2] = sys_cpu_to_be32(STM32_UID_WORD_0);
 
 #if defined(CONFIG_SOC_SERIES_STM32H5X)
-	LL_ICACHE_Enable();
+	sys_cache_instr_enable();
 #endif /* CONFIG_SOC_SERIES_STM32H5X */
 
 	if (length > sizeof(dev_id.id)) {
@@ -146,6 +161,10 @@ int z_impl_hwinfo_get_reset_cause(uint32_t *cause)
 	if (LL_PWR_MCU_IsActiveFlag_SB()) {
 		flags |= RESET_LOW_POWER_WAKE;
 	}
+#elif defined(CONFIG_SOC_SERIES_STM32MP13X)
+	if (LL_PWR_MPU_IsActiveFlag_SB()) {
+		flags |= RESET_LOW_POWER_WAKE;
+	}
 #elif defined(CONFIG_SOC_SERIES_STM32WLX) || defined(CONFIG_SOC_SERIES_STM32WBX)
 	if (LL_PWR_IsActiveFlag_C1SB()) {
 		flags |= RESET_LOW_POWER_WAKE;
@@ -173,6 +192,8 @@ int z_impl_hwinfo_clear_reset_cause(void)
 	LL_PWR_ClearFlag_STOP_SB();
 #elif defined(CONFIG_SOC_SERIES_STM32MP1X)
 	LL_PWR_ClearFlag_MCU();
+#elif defined(CONFIG_SOC_SERIES_STM32MP13X)
+	LL_PWR_ClearFlag_MPU();
 #elif defined(CONFIG_SOC_SERIES_STM32WLX) || defined(CONFIG_SOC_SERIES_STM32WBX)
 	LL_PWR_ClearFlag_C1STOP_C1STB();
 #elif defined(CONFIG_SOC_SERIES_STM32U0X) && defined(PWR_FLAG_SB)
diff --git a/drivers/i2c/CMakeLists.txt b/drivers/i2c/CMakeLists.txt
index bbef44180f2..7a4dbfc5389 100644
--- a/drivers/i2c/CMakeLists.txt
+++ b/drivers/i2c/CMakeLists.txt
@@ -25,6 +25,7 @@ add_subdirectory_ifdef(CONFIG_I2C_TARGET target)
 # zephyr-keep-sorted-start
 zephyr_library_sources_ifdef(CONFIG_I2C_AMBIQ		i2c_ambiq.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_ANDES_ATCIIC100	i2c_andes_atciic100.c)
+zephyr_library_sources_ifdef(CONFIG_I2C_CADENCE         i2c_cdns.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_CC13XX_CC26XX	i2c_cc13xx_cc26xx.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_CC32XX		i2c_cc32xx.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_DW		i2c_dw.c)
@@ -39,6 +40,7 @@ zephyr_library_sources_ifdef(CONFIG_I2C_IPROC		i2c_bcm_iproc.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_ITE_ENHANCE	i2c_ite_enhance.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_ITE_IT8XXX2	i2c_ite_it8xxx2.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_LITEX		i2c_litex.c)
+zephyr_library_sources_ifdef(CONFIG_I2C_LITEX_LITEI2C	i2c_litex_litei2c.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_LPC11U6X	i2c_lpc11u6x.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_MCHP_MSS	i2c_mchp_mss.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_MCUX		i2c_mcux.c)
@@ -48,8 +50,12 @@ zephyr_library_sources_ifdef(CONFIG_I2C_NPCX		i2c_npcx_controller.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_NPCX		i2c_npcx_port.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_NRFX_TWIS	i2c_nrfx_twis.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_NUMAKER		i2c_numaker.c)
+zephyr_library_sources_ifdef(CONFIG_I2C_NXP_II2C	i2c_nxp_ii2c.c)
+zephyr_library_sources_ifdef(CONFIG_I2C_OMAP		i2c_omap.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_RCAR		i2c_rcar.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_RENESAS_RA_IIC	i2c_renesas_ra_iic.c)
+zephyr_library_sources_ifdef(CONFIG_I2C_RENESAS_RA_SCI_B	i2c_renesas_ra_sci_b.c)
+zephyr_library_sources_ifdef(CONFIG_I2C_RENESAS_RZ_RIIC i2c_renesas_rz_riic.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_RV32M1_LPI2C	i2c_rv32m1_lpi2c.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_SAM0		i2c_sam0.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_SAM_TWI		i2c_sam_twi.c)
@@ -67,8 +73,10 @@ zephyr_library_sources_ifdef(CONFIG_I2C_STM32_V2
 	i2c_ll_stm32_v2.c
 	i2c_ll_stm32.c
  )
+zephyr_library_sources_ifdef(CONFIG_I2C_SY1XX		i2c_sy1xx.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_TCA954X		i2c_tca954x.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_TELINK_B91	i2c_b91.c)
+zephyr_library_sources_ifdef(CONFIG_I2C_WCH		i2c_wch.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_XEC		i2c_mchp_xec.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_XEC_V2		i2c_mchp_xec_v2.c)
 zephyr_library_sources_ifdef(CONFIG_I2C_XILINX_AXI	i2c_xilinx_axi.c)
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index a6d132ddc90..25bd2dfea78 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -123,6 +123,7 @@ source "drivers/i2c/Kconfig.andes_atciic100"
 source "drivers/i2c/Kconfig.b91"
 source "drivers/i2c/Kconfig.bcm_iproc"
 source "drivers/i2c/Kconfig.cc13xx_cc26xx"
+source "drivers/i2c/Kconfig.cdns"
 source "drivers/i2c/Kconfig.dw"
 source "drivers/i2c/Kconfig.ene"
 source "drivers/i2c/Kconfig.esp32"
@@ -140,8 +141,10 @@ source "drivers/i2c/Kconfig.mcux"
 source "drivers/i2c/Kconfig.npcx"
 source "drivers/i2c/Kconfig.nrfx"
 source "drivers/i2c/Kconfig.numaker"
+source "drivers/i2c/Kconfig.omap"
 source "drivers/i2c/Kconfig.rcar"
 source "drivers/i2c/Kconfig.renesas_ra"
+source "drivers/i2c/Kconfig.renesas_rz"
 source "drivers/i2c/Kconfig.sam0"
 source "drivers/i2c/Kconfig.sam_twihs"
 source "drivers/i2c/Kconfig.sbcon"
@@ -150,8 +153,10 @@ source "drivers/i2c/Kconfig.sedi"
 source "drivers/i2c/Kconfig.sifive"
 source "drivers/i2c/Kconfig.smartbond"
 source "drivers/i2c/Kconfig.stm32"
+source "drivers/i2c/Kconfig.sy1xx"
 source "drivers/i2c/Kconfig.tca954x"
 source "drivers/i2c/Kconfig.test"
+source "drivers/i2c/Kconfig.wch"
 source "drivers/i2c/Kconfig.xec"
 source "drivers/i2c/Kconfig.xilinx_axi"
 # zephyr-keep-sorted-stop
@@ -260,4 +265,11 @@ config GPIO_I2C_SWITCH
 	help
 	  Enable GPIO controlled I2C bus switch driver.
 
+config I2C_NXP_II2C
+	bool "NXP i.MX8M serial I2C driver"
+	default y
+	depends on DT_HAS_NXP_II2C_ENABLED
+	help
+	  Enable the NXP II2C driver.
+
 endif # I2C
diff --git a/drivers/i2c/Kconfig.cdns b/drivers/i2c/Kconfig.cdns
new file mode 100644
index 00000000000..f03dbaf462a
--- /dev/null
+++ b/drivers/i2c/Kconfig.cdns
@@ -0,0 +1,11 @@
+# Copyright 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config I2C_CADENCE
+	bool "Cadence I2C driver"
+	default y
+	depends on DT_HAS_CDNS_I2C_ENABLED
+	select EVENTS
+	help
+	  Enable Cadence I2C driver.
diff --git a/drivers/i2c/Kconfig.dw b/drivers/i2c/Kconfig.dw
index 75079814377..d666b2aceb2 100644
--- a/drivers/i2c/Kconfig.dw
+++ b/drivers/i2c/Kconfig.dw
@@ -5,7 +5,7 @@ menuconfig I2C_DW
 	bool "Design Ware I2C support"
 	default y
 	depends on DT_HAS_SNPS_DESIGNWARE_I2C_ENABLED
-	select PINCTRL if DT_HAS_RASPBERRYPI_PICO_I2C_ENABLED
+	select PINCTRL if $(dt_compat_any_has_prop,$(DT_COMPAT_SNPS_DESIGNWARE_I2C),pinctrl-0)
 	help
 	  Enable the Design Ware I2C driver
 
diff --git a/drivers/i2c/Kconfig.it8xxx2 b/drivers/i2c/Kconfig.it8xxx2
index 71e6b0ded52..def24ca2411 100644
--- a/drivers/i2c/Kconfig.it8xxx2
+++ b/drivers/i2c/Kconfig.it8xxx2
@@ -6,6 +6,7 @@ config I2C_ITE_IT8XXX2
 	default y
 	depends on DT_HAS_ITE_IT8XXX2_I2C_ENABLED
 	select PINCTRL
+	select I2C_BITBANG
 	help
 	  Enable I2C support on it8xxx2_evb.
 	  Supported Speeds: 100kHz, 400kHz and 1MHz.
@@ -32,6 +33,7 @@ config I2C_ITE_ENHANCE
 	default y
 	depends on DT_HAS_ITE_ENHANCE_I2C_ENABLED
 	select PINCTRL
+	select I2C_BITBANG
 	help
 	  This option can enable the enhance I2C
 	  of IT8XXX2 and support three channels.
diff --git a/drivers/i2c/Kconfig.litex b/drivers/i2c/Kconfig.litex
index d768c4ef8d5..9637f44f5a6 100644
--- a/drivers/i2c/Kconfig.litex
+++ b/drivers/i2c/Kconfig.litex
@@ -8,3 +8,10 @@ config I2C_LITEX
 	select I2C_BITBANG
 	help
 	  Enable support for Litex I2C driver
+
+config I2C_LITEX_LITEI2C
+	bool "LiteX LiteI2C I2C driver"
+	default y
+	depends on DT_HAS_LITEX_LITEI2C_ENABLED
+	help
+	  Enable support for Litex I2C driver
diff --git a/drivers/i2c/Kconfig.omap b/drivers/i2c/Kconfig.omap
new file mode 100644
index 00000000000..4b7951eb0e8
--- /dev/null
+++ b/drivers/i2c/Kconfig.omap
@@ -0,0 +1,19 @@
+# Copyright (C) 2024 BeagleBoard.org Foundation
+# Copyright (C) 2024 Dhruv Menon <dhruvmenon1104@gmail.com>
+
+# SPDX-License-Identifier: Apache-2.0
+
+config I2C_OMAP
+	bool "TI OMAP I2C Driver"
+	default y
+	depends on DT_HAS_TI_OMAP_I2C_ENABLED
+	select PINCTRL
+	help
+	  Enable the I2C driver for TI OMAP SoCs.
+
+config I2C_OMAP_BUS_RECOVERY
+	bool "Bus recovery support"
+	depends on I2C_OMAP
+	select I2C_BITBANG
+	help
+	  Enable OMAP I2C driver bus recovery support via bitbanging.
diff --git a/drivers/i2c/Kconfig.renesas_ra b/drivers/i2c/Kconfig.renesas_ra
index a0cd23a6b64..4a64daf5b42 100644
--- a/drivers/i2c/Kconfig.renesas_ra
+++ b/drivers/i2c/Kconfig.renesas_ra
@@ -1,6 +1,6 @@
 # Renesas RA Family
 
-# Copyright (c) 2024 Renesas Electronics Corporation
+# Copyright (c) 2024-2025 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 config I2C_RENESAS_RA_IIC
@@ -11,3 +11,23 @@ config I2C_RENESAS_RA_IIC
 	select PINCTRL
 	help
 	  Enable Renesas RA I2C IIC Driver.
+
+config I2C_RENESAS_RA_SCI_B
+	bool "Renesas RA SCI-B I2C"
+	default y
+	depends on DT_HAS_RENESAS_RA_I2C_SCI_B_ENABLED
+	select USE_RA_FSP_SCI_B_I2C
+	select PINCTRL
+	help
+	  Enable Renesas RA SCI-B I2C Driver.
+
+if I2C_RENESAS_RA_SCI_B
+
+config I2C_RENESAS_RA_SCI_B_DTC
+	bool "DTC on Transmission and Reception"
+	default y
+	select USE_RA_FSP_DTC
+	help
+	   Enable DTC on transmission and reception
+
+endif
diff --git a/drivers/i2c/Kconfig.renesas_rz b/drivers/i2c/Kconfig.renesas_rz
new file mode 100644
index 00000000000..16ebd19c54e
--- /dev/null
+++ b/drivers/i2c/Kconfig.renesas_rz
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config I2C_RENESAS_RZ_RIIC
+	bool "Renesas RZ I2C RIIC Master"
+	default y
+	depends on DT_HAS_RENESAS_RZ_RIIC_ENABLED
+	select USE_RZ_FSP_RIIC_MASTER
+	help
+	  Enable Renesas RZ I2C RIIC Driver.
diff --git a/drivers/i2c/Kconfig.sam0 b/drivers/i2c/Kconfig.sam0
index 2096dbf4627..6cc8b57d67f 100644
--- a/drivers/i2c/Kconfig.sam0
+++ b/drivers/i2c/Kconfig.sam0
@@ -21,6 +21,7 @@ config I2C_SAM0_DMA_DRIVEN
 
 config I2C_SAM0_TRANSFER_TIMEOUT
 	int "Transfer timeout [ms]"
+	depends on I2C_SAM0
 	default 500
 	help
 	  Timeout in milliseconds used for each I2C transfer.
diff --git a/drivers/i2c/Kconfig.sbcon b/drivers/i2c/Kconfig.sbcon
index 8a8a6a1ddf6..2f82720c5d2 100644
--- a/drivers/i2c/Kconfig.sbcon
+++ b/drivers/i2c/Kconfig.sbcon
@@ -6,3 +6,4 @@ config I2C_SBCON
 	default y
 	depends on DT_HAS_ARM_VERSATILE_I2C_ENABLED
 	select I2C_BITBANG
+	select PINCTRL
diff --git a/drivers/i2c/Kconfig.stm32 b/drivers/i2c/Kconfig.stm32
index b07dc5ca589..3b7bf71b551 100644
--- a/drivers/i2c/Kconfig.stm32
+++ b/drivers/i2c/Kconfig.stm32
@@ -55,4 +55,13 @@ config I2C_STM32_V2_TIMING
 	help
 	  Enable STM32 driver bus to calculate the Timing.
 
+config I2C_STM32_V2_DMA
+	bool "DMA support"
+	depends on I2C_STM32_V2
+	select DMA
+	select CACHE_MANAGEMENT if CPU_HAS_DCACHE
+	select EXPERIMENTAL
+	help
+	  Enable DMA support for the STM32 I2C driver.
+
 endif # I2C_STM32
diff --git a/drivers/i2c/Kconfig.sy1xx b/drivers/i2c/Kconfig.sy1xx
new file mode 100644
index 00000000000..b02b7a146b7
--- /dev/null
+++ b/drivers/i2c/Kconfig.sy1xx
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+config I2C_SY1XX
+	bool "Sensry SY1XX I2C driver"
+	default y
+	depends on DT_HAS_SENSRY_SY1XX_I2C_ENABLED
+	help
+	  Enable Sensry SY1xx SOC Family I2C driver.
diff --git a/drivers/i2c/Kconfig.wch b/drivers/i2c/Kconfig.wch
new file mode 100644
index 00000000000..f07114e8364
--- /dev/null
+++ b/drivers/i2c/Kconfig.wch
@@ -0,0 +1,15 @@
+# Copyright (c) 2025 Andrei-Edward Popa
+# SPDX-License-Identifier: Apache-2.0
+
+config I2C_WCH
+	bool "WCH I2C driver"
+	default y
+	depends on DT_HAS_WCH_I2C_ENABLED
+	select PINCTRL
+	help
+	  Enable I2C support on WCH platforms
+
+config I2C_WCH_XFER_TIMEOUT_MS
+	int "Set the transfer timeout in milliseconds"
+	depends on I2C_WCH
+	default 500
diff --git a/drivers/i2c/i2c_ambiq.c b/drivers/i2c/i2c_ambiq.c
index 50536a5dd53..8d2be5eccc2 100644
--- a/drivers/i2c/i2c_ambiq.c
+++ b/drivers/i2c/i2c_ambiq.c
@@ -13,7 +13,25 @@
 #include <zephyr/pm/policy.h>
 #include <zephyr/pm/device_runtime.h>
 
-#include <am_mcu_apollo.h>
+#include <soc.h>
+
+#include <zephyr/mem_mgmt/mem_attr.h>
+
+#ifdef CONFIG_DCACHE
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#endif /* CONFIG_DCACHE */
+
+#ifdef CONFIG_NOCACHE_MEMORY
+#include <zephyr/linker/linker-defs.h>
+#elif defined(CONFIG_CACHE_MANAGEMENT)
+#include <zephyr/arch/cache.h>
+#endif /* CONFIG_NOCACHE_MEMORY */
+
+#if defined(CONFIG_DCACHE) && !defined(CONFIG_NOCACHE_MEMORY)
+#define I2C_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED 1
+#else
+#define I2C_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED 0
+#endif /* defined(CONFIG_DCACHE) && !defined(CONFIG_NOCACHE_MEMORY) */
 
 #ifdef CONFIG_I2C_AMBIQ_BUS_RECOVERY
 #include <zephyr/drivers/gpio.h>
@@ -25,9 +43,6 @@
 
 LOG_MODULE_REGISTER(ambiq_i2c, CONFIG_I2C_LOG_LEVEL);
 
-typedef int (*ambiq_i2c_pwr_func_t)(void);
-
-#define PWRCTRL_MAX_WAIT_US       5
 #define I2C_TRANSFER_TIMEOUT_MSEC 500 /* Transfer timeout period */
 
 #include "i2c-priv.h"
@@ -39,9 +54,9 @@ struct i2c_ambiq_config {
 #endif /* CONFIG_I2C_AMBIQ_BUS_RECOVERY */
 	uint32_t base;
 	int size;
+	int inst_idx;
 	uint32_t bitrate;
 	const struct pinctrl_dev_config *pcfg;
-	ambiq_i2c_pwr_func_t pwr_func;
 	void (*irq_config_func)(void);
 };
 
@@ -54,7 +69,6 @@ struct i2c_ambiq_data {
 	struct k_sem transfer_sem;
 	i2c_ambiq_callback_t callback;
 	void *callback_data;
-	int inst_idx;
 	uint32_t transfer_status;
 	bool pm_policy_state_on;
 };
@@ -86,9 +100,15 @@ static void i2c_ambiq_pm_policy_state_lock_put(const struct device *dev)
 }
 
 #ifdef CONFIG_I2C_AMBIQ_DMA
+/*
+ * If Nocache Memory is supported, buffer will be placed in nocache region by
+ * the linker to avoid potential DMA cache-coherency problems.
+ * If Nocache Memory is not supported, cache coherency might need to be kept
+ * manually. See I2C_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED.
+ */
 static __aligned(32) struct {
 	__aligned(32) uint32_t buf[CONFIG_I2C_DMA_TCB_BUFFER_SIZE];
-} i2c_dma_tcb_buf[DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT)] __attribute__((__section__(".nocache")));
+} i2c_dma_tcb_buf[DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT)] __nocache;
 
 static void i2c_ambiq_callback(void *callback_ctxt, uint32_t status)
 {
@@ -100,6 +120,39 @@ static void i2c_ambiq_callback(void *callback_ctxt, uint32_t status)
 	}
 	data->transfer_status = status;
 }
+
+#ifdef CONFIG_DCACHE
+static bool buf_in_nocache(uintptr_t buf, size_t len_bytes)
+{
+	bool buf_within_nocache = false;
+
+#ifdef CONFIG_NOCACHE_MEMORY
+	/* Check if buffer is in nocache region defined by the linker */
+	buf_within_nocache = (buf >= ((uintptr_t)_nocache_ram_start)) &&
+			     ((buf + len_bytes - 1) <= ((uintptr_t)_nocache_ram_end));
+	if (buf_within_nocache) {
+		return true;
+	}
+#endif /* CONFIG_NOCACHE_MEMORY */
+
+	/* Check if buffer is in nocache memory region defined in DT */
+	buf_within_nocache =
+		mem_attr_check_buf((void *)buf, len_bytes, DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)) == 0;
+
+	return buf_within_nocache;
+}
+
+static bool i2c_buf_set_in_nocache(const struct i2c_msg *msgs, uint8_t num_msgs)
+{
+	for (int i = 0; i < num_msgs; i++) {
+		if (!buf_in_nocache((uintptr_t)msgs[i]->buf, msgs[i]->len)) {
+			return false;
+		}
+	}
+	return true;
+}
+#endif /* CONFIG_DCACHE */
+
 #endif
 
 static void i2c_ambiq_isr(const struct device *dev)
@@ -113,7 +166,8 @@ static void i2c_ambiq_isr(const struct device *dev)
 	k_sem_give(&data->transfer_sem);
 }
 
-static int i2c_ambiq_read(const struct device *dev, struct i2c_msg *msg, uint16_t addr)
+static int i2c_ambiq_read(const struct device *dev, struct i2c_msg *hdr_msg,
+			   struct i2c_msg *data_msg, uint16_t addr)
 {
 	struct i2c_ambiq_data *data = dev->data;
 
@@ -124,8 +178,19 @@ static int i2c_ambiq_read(const struct device *dev, struct i2c_msg *msg, uint16_
 	trans.ui8Priority = 1;
 	trans.eDirection = AM_HAL_IOM_RX;
 	trans.uPeerInfo.ui32I2CDevAddr = addr;
-	trans.ui32NumBytes = msg->len;
-	trans.pui32RxBuffer = (uint32_t *)msg->buf;
+	trans.ui32NumBytes = data_msg->len;
+	trans.pui32RxBuffer = (uint32_t *)data_msg->buf;
+	if (hdr_msg) {
+		if (hdr_msg->len > AM_HAL_IOM_MAX_OFFSETSIZE) {
+			return -E2BIG;
+		}
+#if defined(CONFIG_SOC_SERIES_APOLLO3X)
+		trans.ui32Instr = (*(uint32_t *)hdr_msg->buf) & (0xFFFFFFFF >> (32 - (hdr_msg->len * 8)));
+#else
+		trans.ui64Instr = (*(uint64_t *)hdr_msg->buf) & (0xFFFFFFFFFFFFFFFF >> (64 - (hdr_msg->len * 8)));
+#endif
+		trans.ui32InstrLen = hdr_msg->len;
+	}
 
 #ifdef CONFIG_I2C_AMBIQ_DMA
 	data->transfer_status = -EFAULT;
@@ -140,6 +205,10 @@ static int i2c_ambiq_read(const struct device *dev, struct i2c_msg *msg, uint16_
 		am_hal_iom_enable(data->iom_handler);
 		return -ETIMEDOUT;
 	}
+#if I2C_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED
+	/* Invalidate Dcache after DMA read */
+	sys_cache_data_invd_range((void *)trans.pui32RxBuffer, trans.ui32NumBytes);
+#endif /* I2C_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED */
 	ret = data->transfer_status;
 #else
 	ret = am_hal_iom_blocking_transfer(data->iom_handler, &trans);
@@ -147,7 +216,8 @@ static int i2c_ambiq_read(const struct device *dev, struct i2c_msg *msg, uint16_
 	return (ret != AM_HAL_STATUS_SUCCESS) ? -EIO : 0;
 }
 
-static int i2c_ambiq_write(const struct device *dev, struct i2c_msg *msg, uint16_t addr)
+static int i2c_ambiq_write(const struct device *dev, struct i2c_msg *hdr_msg,
+			   struct i2c_msg *data_msg, uint16_t addr)
 {
 	struct i2c_ambiq_data *data = dev->data;
 
@@ -158,11 +228,26 @@ static int i2c_ambiq_write(const struct device *dev, struct i2c_msg *msg, uint16
 	trans.ui8Priority = 1;
 	trans.eDirection = AM_HAL_IOM_TX;
 	trans.uPeerInfo.ui32I2CDevAddr = addr;
-	trans.ui32NumBytes = msg->len;
-	trans.pui32TxBuffer = (uint32_t *)msg->buf;
+	trans.ui32NumBytes = data_msg->len;
+	trans.pui32TxBuffer = (uint32_t *)data_msg->buf;
+	if (hdr_msg) {
+		if (hdr_msg->len > AM_HAL_IOM_MAX_OFFSETSIZE) {
+			return -E2BIG;
+		}
+#if defined(CONFIG_SOC_SERIES_APOLLO3X)
+		trans.ui32Instr = (*(uint32_t *)hdr_msg->buf) & (0xFFFFFFFF >> (32 - (hdr_msg->len * 8)));
+#else
+		trans.ui64Instr = (*(uint64_t *)hdr_msg->buf) & (0xFFFFFFFFFFFFFFFF >> (64 - (hdr_msg->len * 8)));
+#endif
+		trans.ui32InstrLen = hdr_msg->len;
+	}
 
 #ifdef CONFIG_I2C_AMBIQ_DMA
 	data->transfer_status = -EFAULT;
+#if I2C_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED
+	/* Clean Dcache before DMA write */
+	sys_cache_data_flush_range((void *)trans.pui32TxBuffer, trans.ui32NumBytes);
+#endif /* I2C_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED */
 	ret = am_hal_iom_nonblocking_transfer(data->iom_handler, &trans, i2c_ambiq_callback,
 					      (void *)dev);
 
@@ -206,7 +291,9 @@ static int i2c_ambiq_configure(const struct device *dev, uint32_t dev_config)
 	}
 
 #ifdef CONFIG_I2C_AMBIQ_DMA
-	data->iom_cfg.pNBTxnBuf = i2c_dma_tcb_buf[data->inst_idx].buf;
+	const struct i2c_ambiq_config *cfg = dev->config;
+
+	data->iom_cfg.pNBTxnBuf = i2c_dma_tcb_buf[cfg->inst_idx].buf;
 	data->iom_cfg.ui32NBTxnBufLength = CONFIG_I2C_DMA_TCB_BUFFER_SIZE;
 #endif
 
@@ -225,6 +312,12 @@ static int i2c_ambiq_transfer(const struct device *dev, struct i2c_msg *msgs, ui
 		return 0;
 	}
 
+#if defined(CONFIG_I2C_AMBIQ_DMA) && defined(CONFIG_DCACHE)
+	if (!i2c_buf_set_in_nocache(msgs, num_msgs)) {
+		return -EFAULT;
+	}
+#endif /* CONFIG_DCACHE */
+
 	i2c_ambiq_pm_policy_state_lock_get(dev);
 
 	/* Send out messages */
@@ -232,9 +325,16 @@ static int i2c_ambiq_transfer(const struct device *dev, struct i2c_msg *msgs, ui
 
 	for (int i = 0; i < num_msgs; i++) {
 		if (msgs[i].flags & I2C_MSG_READ) {
-			ret = i2c_ambiq_read(dev, &(msgs[i]), addr);
+			ret = i2c_ambiq_read(dev, NULL, &(msgs[i]), addr);
+		} else if ((i + 1) < num_msgs) {
+			if (msgs[i + 1].flags & I2C_MSG_READ) {
+				ret = i2c_ambiq_read(dev, &(msgs[i]), &(msgs[i + 1]), addr);
+			} else {
+				ret = i2c_ambiq_write(dev, &(msgs[i]), &(msgs[i + 1]), addr);
+			}
+			i++;
 		} else {
-			ret = i2c_ambiq_write(dev, &(msgs[i]), addr);
+			ret = i2c_ambiq_write(dev, NULL, &(msgs[i]), addr);
 		}
 
 		if (ret != 0) {
@@ -343,14 +443,12 @@ static int i2c_ambiq_init(const struct device *dev)
 
 	data->iom_cfg.eInterfaceMode = AM_HAL_IOM_I2C_MODE;
 
-	if (AM_HAL_STATUS_SUCCESS !=
-	    am_hal_iom_initialize((config->base - IOM0_BASE) / config->size,
-				  &data->iom_handler)) {
+	if (AM_HAL_STATUS_SUCCESS != am_hal_iom_initialize(config->inst_idx, &data->iom_handler)) {
 		LOG_ERR("Fail to initialize I2C\n");
 		return -ENXIO;
 	}
 
-	ret = config->pwr_func();
+	ret = am_hal_iom_power_ctrl(data->iom_handler, AM_HAL_SYSCTRL_WAKE, false);
 
 	ret |= i2c_ambiq_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
 	if (ret < 0) {
@@ -422,35 +520,26 @@ static int i2c_ambiq_pm_action(const struct device *dev, enum pm_device_action a
 
 #define AMBIQ_I2C_DEFINE(n)                                                                        \
 	PINCTRL_DT_INST_DEFINE(n);                                                                 \
-	static int pwr_on_ambiq_i2c_##n(void)                                                      \
-	{                                                                                          \
-		uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) +                    \
-				DT_INST_PHA(n, ambiq_pwrcfg, offset);                              \
-		sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr);        \
-		k_busy_wait(PWRCTRL_MAX_WAIT_US);                                                  \
-		return 0;                                                                          \
-	}                                                                                          \
 	static void i2c_irq_config_func_##n(void)                                                  \
 	{                                                                                          \
-		IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), i2c_ambiq_isr,              \
-			    DEVICE_DT_INST_GET(n), 0);                                             \
-		irq_enable(DT_INST_IRQN(n));                                                       \
+		IRQ_CONNECT(DT_IRQN(DT_INST_PARENT(n)), DT_IRQ(DT_INST_PARENT(n), priority),       \
+			    i2c_ambiq_isr, DEVICE_DT_INST_GET(n), 0);                              \
+		irq_enable(DT_IRQN(DT_INST_PARENT(n)));                                            \
 	};                                                                                         \
 	static struct i2c_ambiq_data i2c_ambiq_data##n = {                                         \
 		.bus_sem = Z_SEM_INITIALIZER(i2c_ambiq_data##n.bus_sem, 1, 1),                     \
-		.transfer_sem = Z_SEM_INITIALIZER(i2c_ambiq_data##n.transfer_sem, 0, 1),           \
-		.inst_idx = n,                                                                     \
-	};                                                                                         \
+		.transfer_sem = Z_SEM_INITIALIZER(i2c_ambiq_data##n.transfer_sem, 0, 1)};          \
 	static const struct i2c_ambiq_config i2c_ambiq_config##n = {                               \
-		.base = DT_INST_REG_ADDR(n),                                                       \
-		.size = DT_INST_REG_SIZE(n),                                                       \
+		.base = DT_REG_ADDR(DT_INST_PARENT(n)),                                            \
+		.size = DT_REG_SIZE(DT_INST_PARENT(n)),                                            \
+		.inst_idx =                                                                        \
+			(DT_REG_ADDR(DT_INST_PARENT(n)) - IOM0_BASE) / (IOM1_BASE - IOM0_BASE),    \
 		.bitrate = DT_INST_PROP(n, clock_frequency),                                       \
 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                         \
 		.irq_config_func = i2c_irq_config_func_##n,                                        \
-		.pwr_func = pwr_on_ambiq_i2c_##n,                                                  \
-		IF_ENABLED(CONFIG_I2C_AMBIQ_BUS_RECOVERY,			\
-		(.scl = GPIO_DT_SPEC_INST_GET_OR(n, scl_gpios, {0}),\
-		 .sda = GPIO_DT_SPEC_INST_GET_OR(n, sda_gpios, {0}),)) };      \
+		IF_ENABLED(CONFIG_I2C_AMBIQ_BUS_RECOVERY,                                          \
+		(.scl = GPIO_DT_SPEC_INST_GET_OR(n, scl_gpios, {0}),                               \
+		 .sda = GPIO_DT_SPEC_INST_GET_OR(n, sda_gpios, {0}),)) };                          \
 	PM_DEVICE_DT_INST_DEFINE(n, i2c_ambiq_pm_action);                                          \
 	I2C_DEVICE_DT_INST_DEFINE(n, i2c_ambiq_init, PM_DEVICE_DT_INST_GET(n), &i2c_ambiq_data##n, \
 				  &i2c_ambiq_config##n, POST_KERNEL, CONFIG_I2C_INIT_PRIORITY,     \
diff --git a/drivers/i2c/i2c_cc13xx_cc26xx.c b/drivers/i2c/i2c_cc13xx_cc26xx.c
index e475be674ca..fdcd8f543ab 100644
--- a/drivers/i2c/i2c_cc13xx_cc26xx.c
+++ b/drivers/i2c/i2c_cc13xx_cc26xx.c
@@ -40,153 +40,82 @@ struct i2c_cc13xx_cc26xx_config {
 	const struct pinctrl_dev_config *pcfg;
 };
 
-static int i2c_cc13xx_cc26xx_transmit(const struct device *dev,
-				      const uint8_t *buf,
-				      uint32_t len, uint16_t addr)
+static int i2c_cc13xx_cc26xx_transmit(const struct device *dev, const struct i2c_msg *msg,
+				      const uint8_t addr)
 {
 	const struct i2c_cc13xx_cc26xx_config *config = dev->config;
 	const uint32_t base = config->base;
 	struct i2c_cc13xx_cc26xx_data *data = dev->data;
 
-	/* Sending address without data is not supported */
-	if (len == 0) {
-		return -EIO;
-	}
-
 	I2CMasterSlaveAddrSet(base, addr, false);
 
-	/* The following assumes a single master. Use I2CMasterBusBusy() if
-	 * wanting to implement multiple master support.
-	 */
-
-	/* Single transmission */
-	if (len == 1) {
-		I2CMasterDataPut(base, *buf);
+	for (int i = 0; i < msg->len; i++) {
+		uint32_t command = I2C_MCTRL_RUN;
 
-		I2CMasterControl(base, I2C_MASTER_CMD_SINGLE_SEND);
-
-		k_sem_take(&data->complete, K_FOREVER);
-
-		return data->error == I2C_MASTER_ERR_NONE ? 0 : -EIO;
-	}
-
-	/* Burst transmission */
-	I2CMasterDataPut(base, buf[0]);
-
-	I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_START);
-
-	k_sem_take(&data->complete, K_FOREVER);
-
-	if (data->error != I2C_MASTER_ERR_NONE) {
-		goto send_error_stop;
-	}
-
-	for (int i = 1; i < len - 1; i++) {
-		I2CMasterDataPut(base, buf[i]);
+		if (i == 0 && msg->flags & I2C_MSG_RESTART) {
+			command |= I2C_MCTRL_START;
+		}
 
-		I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_CONT);
+		if (i == msg->len - 1 && msg->flags & I2C_MSG_STOP) {
+			command |= I2C_MCTRL_STOP;
+		}
 
+		I2CMasterDataPut(base, msg->buf[i]);
+		I2CMasterControl(base, command);
 		k_sem_take(&data->complete, K_FOREVER);
 
 		if (data->error != I2C_MASTER_ERR_NONE) {
-			goto send_error_stop;
+			if ((command & I2C_MCTRL_STOP) == 0) {
+				I2CMasterControl(base, I2C_MCTRL_STOP);
+			}
+			return -EIO;
 		}
 	}
 
-	I2CMasterDataPut(base, buf[len - 1]);
-
-	I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_FINISH);
-
-	k_sem_take(&data->complete, K_FOREVER);
-
-	if (data->error != I2C_MASTER_ERR_NONE) {
-		return -EIO;
-	}
-
 	return 0;
-
-send_error_stop:
-	I2CMasterControl(base, I2C_MASTER_CMD_BURST_SEND_ERROR_STOP);
-	return -EIO;
 }
 
-static int i2c_cc13xx_cc26xx_receive(const struct device *dev, uint8_t *buf,
-				     uint32_t len,
-				     uint16_t addr)
+static int i2c_cc13xx_cc26xx_receive(const struct device *dev, const struct i2c_msg *msg,
+				     const uint8_t addr)
 {
+	struct i2c_cc13xx_cc26xx_data *data = dev->data;
 	const struct i2c_cc13xx_cc26xx_config *config = dev->config;
 	const uint32_t base = config->base;
-	struct i2c_cc13xx_cc26xx_data *data = dev->data;
-
-	/* Sending address without data is not supported */
-	if (len == 0) {
-		return -EIO;
-	}
 
 	I2CMasterSlaveAddrSet(base, addr, true);
 
-	/* The following assumes a single master. Use I2CMasterBusBusy() if
-	 * wanting to implement multiple master support.
-	 */
-
-	/* Single receive */
-	if (len == 1) {
-		I2CMasterControl(base, I2C_MASTER_CMD_SINGLE_RECEIVE);
-
-		k_sem_take(&data->complete, K_FOREVER);
+	for (int i = 0; i < msg->len; i++) {
+		uint32_t command = I2C_MCTRL_RUN;
 
-		if (data->error != I2C_MASTER_ERR_NONE) {
-			return -EIO;
+		if (i == 0 && msg->flags & I2C_MSG_RESTART) {
+			command |= I2C_MCTRL_START;
 		}
 
-		*buf = I2CMasterDataGet(base);
-
-		return 0;
-	}
-
-	/* Burst receive */
-	I2CMasterControl(base, I2C_MASTER_CMD_BURST_RECEIVE_START);
-
-	k_sem_take(&data->complete, K_FOREVER);
-
-	if (data->error != I2C_MASTER_ERR_NONE) {
-		goto recv_error_stop;
-	}
-
-	buf[0] = I2CMasterDataGet(base);
+		if (i == msg->len - 1 && msg->flags & I2C_MSG_STOP) {
+			command |= I2C_MCTRL_STOP;
+		} else if (i < msg->len - 1) {
+			command |= I2C_MCTRL_ACK;
+		}
 
-	for (int i = 1; i < len - 1; i++) {
-		I2CMasterControl(base, I2C_MASTER_CMD_BURST_RECEIVE_CONT);
+		I2CMasterControl(base, command);
 
 		k_sem_take(&data->complete, K_FOREVER);
 
 		if (data->error != I2C_MASTER_ERR_NONE) {
-			goto recv_error_stop;
+			if ((command & I2C_MCTRL_STOP) == 0) {
+				I2CMasterControl(base, I2C_MCTRL_STOP);
+			}
+			return -EIO;
 		}
 
-		buf[i] = I2CMasterDataGet(base);
-	}
-
-	I2CMasterControl(base, I2C_MASTER_CMD_BURST_RECEIVE_FINISH);
-
-	k_sem_take(&data->complete, K_FOREVER);
-
-	if (data->error != I2C_MASTER_ERR_NONE) {
-		return -EIO;
+		msg->buf[i] = I2CMasterDataGet(base);
 	}
 
-	buf[len - 1] = I2CMasterDataGet(base);
-
 	return 0;
-
-recv_error_stop:
-	I2CMasterControl(base, I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP);
-	return -EIO;
 }
 
-static int i2c_cc13xx_cc26xx_transfer(const struct device *dev,
-				      struct i2c_msg *msgs,
-				      uint8_t num_msgs, uint16_t addr)
+static int i2c_cc13xx_cc26xx_transfer(const struct device *dev, struct i2c_msg *msgs,
+				      const uint8_t num_msgs, const uint16_t addr)
 {
 	struct i2c_cc13xx_cc26xx_data *data = dev->data;
 	int ret = 0;
@@ -195,6 +124,9 @@ static int i2c_cc13xx_cc26xx_transfer(const struct device *dev,
 		return 0;
 	}
 
+	/* Always a start condition in the first message */
+	msgs[0].flags |= I2C_MSG_RESTART;
+
 	k_sem_take(&data->lock, K_FOREVER);
 
 	pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
@@ -206,12 +138,16 @@ static int i2c_cc13xx_cc26xx_transfer(const struct device *dev,
 			break;
 		}
 
+		/* Sending address without data is not supported */
+		if (msgs[i].len == 0) {
+			ret = -EIO;
+			break;
+		}
+
 		if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
-			ret = i2c_cc13xx_cc26xx_transmit(dev, msgs[i].buf,
-							 msgs[i].len, addr);
+			ret = i2c_cc13xx_cc26xx_transmit(dev, &msgs[i], addr);
 		} else {
-			ret = i2c_cc13xx_cc26xx_receive(dev, msgs[i].buf,
-							msgs[i].len, addr);
+			ret = i2c_cc13xx_cc26xx_receive(dev, &msgs[i], addr);
 		}
 
 		if (ret) {
diff --git a/drivers/i2c/i2c_cdns.c b/drivers/i2c/i2c_cdns.c
new file mode 100644
index 00000000000..87380769979
--- /dev/null
+++ b/drivers/i2c/i2c_cdns.c
@@ -0,0 +1,1081 @@
+/*
+ * Copyright (c) 2025 Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/irq.h>
+
+LOG_MODULE_REGISTER(i2c_cadence, CONFIG_I2C_LOG_LEVEL);
+
+/* Register offsets for the I2C device. */
+#define CDNS_I2C_CR_OFFSET		0x00 /* Control Register, RW */
+#define CDNS_I2C_SR_OFFSET		0x04 /* Status Register, RO */
+#define CDNS_I2C_ADDR_OFFSET		0x08 /* I2C Address Register, RW */
+#define CDNS_I2C_DATA_OFFSET		0x0C /* I2C Data Register, RW */
+#define CDNS_I2C_ISR_OFFSET		0x10 /* IRQ Status Register, RW */
+#define CDNS_I2C_XFER_SIZE_OFFSET	0x14 /* Transfer Size Register, RW */
+#define CDNS_I2C_TIME_OUT_OFFSET	0x1C /* Time Out Register, RW */
+#define CDNS_I2C_IMR_OFFSET		0x20 /* IRQ Mask Register, RO */
+#define CDNS_I2C_IER_OFFSET		0x24 /* IRQ Enable Register, WO */
+#define CDNS_I2C_IDR_OFFSET		0x28 /* IRQ Disable Register, WO */
+#define CDNS_I2C_GFR_OFFSET		0x2C /* Glitch Filter Register, RW */
+
+/* Control Register Bit mask definitions */
+#define CDNS_I2C_CR_HOLD		BIT(4) /* Hold the I2C Bus */
+#define CDNS_I2C_CR_ACK_EN		BIT(3) /* Enables or disables acknowledgment */
+#define CDNS_I2C_CR_NEA			BIT(2) /* No Extended addressing */
+#define CDNS_I2C_CR_MS			BIT(1) /* 0 = Slave Mode, 1 = Master Mode */
+#define CDNS_I2C_CR_RW			BIT(0) /* Transfer Dir: 0 = Transmitter, 1 = Receiver */
+#define CDNS_I2C_CR_CLR_FIFO		BIT(6) /* Clears the FIFO on initialization */
+
+/* Master Enable Mask */
+#define CDNS_I2C_CR_MASTER_EN_MASK	(CDNS_I2C_CR_ACK_EN | \
+					 CDNS_I2C_CR_NEA | \
+					 CDNS_I2C_CR_MS)
+
+/* Dividers for clock generation */
+#define CDNS_I2C_CR_DIVA_SHIFT		14U
+#define CDNS_I2C_CR_DIVA_MASK		((uint32_t)3U << CDNS_I2C_CR_DIVA_SHIFT)
+#define CDNS_I2C_CR_DIVB_SHIFT		8U
+#define CDNS_I2C_CR_DIVB_MASK		((uint32_t)0x3f << CDNS_I2C_CR_DIVB_SHIFT)
+
+/* Status Register Bit mask definitions */
+#define CDNS_I2C_SR_BA			BIT(8) /* Bus is available */
+#define CDNS_I2C_SR_TXDV		BIT(6) /* Transmit data is valid */
+#define CDNS_I2C_SR_RXDV		BIT(5) /* Received data is valid */
+#define CDNS_I2C_SR_RXRW		BIT(3) /* Read or Write operation */
+
+/*
+ * I2C Address Register Bit mask definitions
+ * Normal addressing mode uses [6:0] bits.
+ * Extended addressing mode uses [9:0] bits.
+ * A write access to this register always initiates a transfer if the I2C is in master mode.
+ */
+#define CDNS_I2C_ADDR_MASK		0x000003FFU /* I2C Address Mask */
+
+/*
+ * I2C Interrupt Registers Bit mask definitions
+ * All the four interrupt registers (Status/Mask/Enable/Disable) have the same bit definitions.
+ */
+#define CDNS_I2C_IXR_ARB_LOST		BIT(9) /* Arbitration Lost Interrupt */
+#define CDNS_I2C_IXR_RX_UNF		BIT(7) /* RX FIFO Underflow Interrupt */
+#define CDNS_I2C_IXR_TX_OVF		BIT(6) /* TX FIFO Overflow Interrupt */
+#define CDNS_I2C_IXR_RX_OVF		BIT(5) /* RX FIFO Overflow Interrupt */
+#define CDNS_I2C_IXR_SLV_RDY		BIT(4) /* Slave Ready Interrupt */
+#define CDNS_I2C_IXR_TO			BIT(3) /* Timeout Interrupt */
+#define CDNS_I2C_IXR_NACK		BIT(2) /* NACK Interrupt */
+#define CDNS_I2C_IXR_DATA		BIT(1) /* Data Interrupt */
+#define CDNS_I2C_IXR_COMP		BIT(0) /* Transfer Complete Interrupt */
+
+/* All Interrupt Mask */
+#define CDNS_I2C_IXR_ALL_INTR_MASK	(CDNS_I2C_IXR_ARB_LOST | \
+					 CDNS_I2C_IXR_RX_UNF | \
+					 CDNS_I2C_IXR_TX_OVF | \
+					 CDNS_I2C_IXR_RX_OVF | \
+					 CDNS_I2C_IXR_SLV_RDY | \
+					 CDNS_I2C_IXR_TO | \
+					 CDNS_I2C_IXR_NACK | \
+					 CDNS_I2C_IXR_DATA | \
+					 CDNS_I2C_IXR_COMP)
+
+/* Error Interrupt Mask */
+#define CDNS_I2C_IXR_ERR_INTR_MASK	(CDNS_I2C_IXR_ARB_LOST | \
+					 CDNS_I2C_IXR_RX_UNF | \
+					 CDNS_I2C_IXR_TX_OVF | \
+					 CDNS_I2C_IXR_RX_OVF | \
+					 CDNS_I2C_IXR_NACK)
+
+/* Enabled Interrupt Mask */
+#define CDNS_I2C_ENABLED_INTR_MASK	(CDNS_I2C_IXR_ARB_LOST | \
+					 CDNS_I2C_IXR_RX_UNF | \
+					 CDNS_I2C_IXR_TX_OVF | \
+					 CDNS_I2C_IXR_RX_OVF | \
+					 CDNS_I2C_IXR_NACK | \
+					 CDNS_I2C_IXR_DATA | \
+					 CDNS_I2C_IXR_COMP)
+
+/* System clock frequency for I2C ticks */
+#define CDNS_I2C_TICKS_PER_SEC		CONFIG_SYS_CLOCK_TICKS_PER_SEC
+
+/* Default timeout ticks for I2C operations */
+#define CDNS_I2C_TIMEOUT_TICKS		CDNS_I2C_TICKS_PER_SEC
+
+#define CDNS_I2C_MAX_TRANSFER_SIZE	255U /* Maximum transfer size for I2C data */
+
+/* Default transfer size */
+#define CDNS_I2C_TRANSFER_SIZE_DEFAULT	(CDNS_I2C_MAX_TRANSFER_SIZE - 3U)
+
+/* Maximum dividers for I2C clock */
+#define CDNS_I2C_DIVA_MAX		4U
+#define CDNS_I2C_DIVB_MAX		64U
+#define CDNS_I2C_CLK_DIV_FACTOR		22U
+
+#define CDNS_I2C_TIMEOUT_MAX		  0xFFU /* Maximum value for Timeout Register */
+#define CDNS_I2C_POLL_US		100000U /* Polling interval in microseconds */
+#define CDNS_I2C_TIMEOUT_US		500000U /* Timeout value for I2C operations */
+
+/* Event flag for I2C transfer completion */
+#define I2C_XFER_COMPLETION_EVENT	BIT(0)
+
+/**
+ * struct cdns_i2c_config - Cadence I2C device private constant structure
+ * @irq_config_func: function pointer to configure I2C IRQ
+ */
+struct cdns_i2c_config {
+	void (*irq_config_func)(void);
+};
+
+/**
+ * struct cdns_i2c_data - Cadence I2C device private data structure
+ * @membase: Base address of the I2C device.
+ * @ctrl_reg: Cached value of the control register.
+ * @input_clk: Input clock to I2C controller.
+ * @i2c_clk: Actual I2C clock speed.
+ * @fifo_depth: The depth of the transfer FIFO.
+ * @transfer_size: The maximum number of bytes in one transfer.
+ * @bus_hold_flag: Flag used in repeated start for clearing HOLD bit.
+ * @xfer_done: Transfer complete event.
+ * @err_status: Error status in Interrupt Status Register.
+ * @p_msg: Message pointer for I2C communication.
+ * @p_send_buf:	Pointer to transmit buffer.
+ * @p_recv_buf:	Pointer to receive buffer.
+ * @send_count:	Number of bytes still expected to send.
+ * @recv_count:	Number of bytes still expected to receive.
+ * @curr_recv_count: Number of bytes to be received in current transfer.
+ * @bus_mutex: Mutex for bus access synchronization
+ */
+struct cdns_i2c_data {
+	mem_addr_t membase;
+	uint32_t ctrl_reg;
+	uint32_t input_clk;
+	uint32_t i2c_clk;
+	uint32_t fifo_depth;
+	uint32_t transfer_size;
+	uint32_t bus_hold_flag;
+
+	struct k_event xfer_done;
+	uint32_t err_status;
+	struct i2c_msg *p_msg;
+	uint8_t *p_send_buf;
+	uint8_t *p_recv_buf;
+	uint32_t send_count;
+	uint32_t recv_count;
+	uint32_t curr_recv_count;
+
+	struct k_mutex bus_mutex;
+};
+
+/**
+ * cdns_i2c_writereg - Write a 32-bit value to a specific offset in the I2C register space.
+ * @i2c_bus: Pointer to the I2C data structure.
+ * @value: The 32-bit value to write to the register.
+ * @offset: The offset in the I2C register space where the value will be written.
+ */
+static inline void cdns_i2c_writereg(const struct cdns_i2c_data *i2c_bus,
+				     uint32_t value, uintptr_t offset)
+{
+	uintptr_t reg_address = (uintptr_t)(i2c_bus->membase) + offset;
+
+	sys_write32(value, reg_address);
+}
+
+/**
+ * cdns_i2c_readreg - Read a 32-bit value from a specific offset in the I2C register space.
+ * @i2c_bus: Pointer to the I2C data structure.
+ * @offset: The offset in the I2C register space from which the value will be read.
+ *
+ * Return: The 32-bit value read from the register.
+ */
+static inline uint32_t cdns_i2c_readreg(const struct cdns_i2c_data *i2c_bus, uintptr_t offset)
+{
+	uintptr_t reg_address = (uintptr_t)(i2c_bus->membase) + offset;
+
+	return sys_read32(reg_address);
+}
+
+/**
+ * cdns_i2c_enable_peripheral - Enable the Cadence I2C controller
+ * @i2c_bus: Pointer to the device's private data structure for the I2C controller
+ */
+static void cdns_i2c_enable_peripheral(struct cdns_i2c_data *i2c_bus)
+{
+	cdns_i2c_writereg(i2c_bus, i2c_bus->ctrl_reg, CDNS_I2C_CR_OFFSET);
+
+	/*
+	 * Cadence I2C controller has a bug causing invalid reads after a timeout
+	 * in master receiver mode. While the timeout feature is disabled,
+	 * writing the max value to the timeout register reduces the issue.
+	 */
+	cdns_i2c_writereg(i2c_bus, CDNS_I2C_TIMEOUT_MAX, CDNS_I2C_TIME_OUT_OFFSET);
+}
+
+/**
+ * cdns_i2c_calc_divs - Calculate clock dividers for I2C frequency
+ * @f: Pointer to the I2C target frequency (input/output)
+ * @input_clk: Input clock frequency in Hz
+ * @a: Pointer to the first divider (output)
+ * @b: Pointer to the second divider (output)
+ *
+ * On entry, @f holds the target I2C frequency. On exit, @f will hold the
+ * actual I2C frequency generated by the calculated dividers.
+ *
+ * Return: 0 on success, negative errno otherwise.
+ */
+static int32_t cdns_i2c_calc_divs(uint32_t *f, uint32_t input_clk,
+				  uint32_t *a, uint32_t *b)
+{
+	uint32_t fscl = *f;
+	uint32_t best_fscl = *f;
+	uint32_t actual_fscl, temp;
+	uint32_t div_a, div_b;
+	uint32_t calc_div_a = 0, calc_div_b = 0;
+	uint32_t last_error, current_error;
+	int32_t ret = 0;
+
+	/* calculate initial estimate for divisor_a and divisor_b */
+	temp = input_clk / (CDNS_I2C_CLK_DIV_FACTOR * fscl);
+
+	/* Check if the calculated value is out of range */
+	if ((temp == 0U) || (temp > (CDNS_I2C_DIVA_MAX * CDNS_I2C_DIVB_MAX))) {
+		ret = -EINVAL;
+		goto out;
+	}
+
+	/* Initialize the last error to a large value (no error yet) */
+	last_error = UINT32_MAX;
+
+	/* Iterate over possible values for divisor_a */
+	for (div_a = 0; div_a < CDNS_I2C_DIVA_MAX; div_a++) {
+		/* Calculate the corresponding divisor_b for this div_a */
+		div_b = DIV_ROUND_UP(input_clk, CDNS_I2C_CLK_DIV_FACTOR * fscl * (div_a + 1U));
+
+		/* Skip invalid values of div_b */
+		if ((div_b < 1U) || (div_b > CDNS_I2C_DIVB_MAX)) {
+			continue;
+		}
+
+		/* Adjust div_b for zero-based indexing */
+		div_b--;
+
+		/* Calculate the actual fscl based on the current divisors */
+		actual_fscl = input_clk / (CDNS_I2C_CLK_DIV_FACTOR * (div_a + 1U) * (div_b + 1U));
+
+		/* Skip if the actual fscl exceeds the target fscl */
+		if (actual_fscl > fscl) {
+			continue;
+		}
+
+		/* Calculate the error between the target fscl and the actual fscl */
+		current_error = fscl - actual_fscl;
+
+		/* Update the best divisors if a smaller error is found */
+		if (last_error > current_error) {
+			calc_div_a = div_a;
+			calc_div_b = div_b;
+			best_fscl = actual_fscl;
+			last_error = current_error;
+		}
+	}
+
+	/* Set the output values */
+	*a = calc_div_a;
+	*b = calc_div_b;
+	*f = best_fscl;
+
+out:
+	return ret;
+}
+
+/**
+ * cdns_i2c_setclk - Set the serial clock rate for the I2C device
+ * @i2c_bus: Pointer to the I2C data structure
+ * @req_i2c_speed: requested I2C clock frequency in Hz
+ *
+ * This function sets the serial clock rate for the I2C device by configuring
+ * the clock divisors in the device's control register. The device must be idle
+ * (i.e., not actively transferring data) before calling this function.
+ *
+ * The clock rate is determined by the following formula:
+ *	Fscl = Fpclk / (22 * (divisor_a + 1) * (divisor_b + 1))
+ * Where:
+ *	- Fscl is the desired I2C clock rate
+ *	- Fpclk is the input clock frequency
+ *	- divisor_a and divisor_b are the calculated divisors to achieve the desired clock rate
+ *
+ * The serial clock rate cannot exceed the input clock divided by 22. Common I2C clock
+ * rates are 100 KHz and 400 KHz.
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+static int32_t cdns_i2c_setclk(struct cdns_i2c_data *i2c_bus, uint32_t req_i2c_speed)
+{
+	uint32_t div_a, div_b;
+	uint32_t ctrl_reg;
+	int32_t ret = 0;
+	uint32_t fscl = req_i2c_speed;
+
+	/* Calculate the divider values */
+	ret = cdns_i2c_calc_divs(&fscl, i2c_bus->input_clk, &div_a, &div_b);
+	if (ret != 0) {
+		goto out;
+	}
+	i2c_bus->i2c_clk = fscl; /* Update true SCL value */
+
+	/* Set new divider values in the control register */
+	ctrl_reg = i2c_bus->ctrl_reg;
+	ctrl_reg &= ~(CDNS_I2C_CR_DIVA_MASK | CDNS_I2C_CR_DIVB_MASK);
+	ctrl_reg |= ((div_a << CDNS_I2C_CR_DIVA_SHIFT) |
+		     (div_b << CDNS_I2C_CR_DIVB_SHIFT));
+	i2c_bus->ctrl_reg = ctrl_reg;
+	cdns_i2c_writereg(i2c_bus, ctrl_reg, CDNS_I2C_CR_OFFSET);
+
+out:
+	return ret;
+}
+
+/**
+ * cdns_i2c_configure - Configures the I2C bus speed and initializes the I2C peripheral
+ * @dev: Pointer to the device structure representing the I2C bus
+ * @dev_config: Configuration value containing the desired I2C bus speed
+ *
+ * This function configures the I2C bus speed based on the value provided in @dev_config
+ * It then sets the appropriate clock for the I2C bus, verifies the clock is valid, and
+ * initializes the I2C peripheral. The configuration is saved to the device's data structure.
+ *
+ * Return: 0 on success, negative error value on failure
+ */
+static int32_t cdns_i2c_configure(const struct device *dev, uint32_t dev_config)
+{
+	int32_t ret = 0;
+	struct cdns_i2c_data *i2c_bus = (struct cdns_i2c_data *)dev->data;
+	uint32_t i2c_speed = 0U;
+
+	(void)k_mutex_lock(&i2c_bus->bus_mutex, K_FOREVER);
+
+	/* Check requested I2C Speed */
+	switch (I2C_SPEED_GET(dev_config)) {
+	case I2C_SPEED_STANDARD:
+		i2c_speed = I2C_BITRATE_STANDARD; /* 100 KHz */
+		break;
+	case I2C_SPEED_FAST:
+		i2c_speed = I2C_BITRATE_FAST; /* 400 KHz */
+		break;
+	case I2C_SPEED_FAST_PLUS:
+		i2c_speed = I2C_BITRATE_FAST_PLUS; /* 1 MHz */
+		break;
+	default:
+		LOG_ERR("Unsupported I2C speed requested: %u", i2c_speed);
+		ret = -ERANGE;
+		goto out;
+	}
+
+	/* Set I2C Speed (SCL frequency) */
+	ret = cdns_i2c_setclk(i2c_bus, i2c_speed);
+	if (ret != 0) {
+		LOG_ERR("Invalid SCL clock: %u Hz", i2c_speed);
+		ret = -EIO;
+		goto out;
+	}
+
+	/* Enable the I2C peripheral */
+	i2c_bus->ctrl_reg |= CDNS_I2C_CR_MASTER_EN_MASK;
+	cdns_i2c_enable_peripheral(i2c_bus);
+
+out:
+	(void)k_mutex_unlock(&i2c_bus->bus_mutex);
+
+	return ret;
+}
+
+/**
+ * cdns_i2c_get_config - Retrieve the current I2C configuration.
+ * @dev: Pointer to the device structure.
+ * @dev_config: Pointer to a variable where the configuration will be stored.
+ *
+ * Return: 0 on success, or a negative error code on failure.
+ */
+static int32_t cdns_i2c_get_config(const struct device *dev, uint32_t *dev_config)
+{
+	int32_t ret = 0;
+	struct cdns_i2c_data *i2c_bus = (struct cdns_i2c_data *)dev->data;
+	uint32_t bus_speed = i2c_bus->i2c_clk;
+	uint32_t speed_cfg = 0U;
+
+	/* Retrieve Speed configuration from Actual Bus Speed */
+	if ((bus_speed > 0U) && (bus_speed <= I2C_BITRATE_STANDARD)) {
+		speed_cfg = I2C_SPEED_SET(I2C_SPEED_STANDARD);
+	} else if ((bus_speed > I2C_BITRATE_STANDARD) &&
+		   (bus_speed <= I2C_BITRATE_FAST)) {
+		speed_cfg = I2C_SPEED_SET(I2C_SPEED_FAST);
+	} else if ((bus_speed > I2C_BITRATE_FAST) &&
+		   (bus_speed <= I2C_BITRATE_FAST_PLUS)) {
+		speed_cfg = I2C_SPEED_SET(I2C_SPEED_FAST_PLUS);
+	} else {
+		ret = -ERANGE;
+		goto out;
+	}
+
+	/* Return current configuration */
+	*dev_config = (speed_cfg | I2C_MODE_CONTROLLER);
+
+out:
+	return ret;
+}
+
+/**
+ * cdns_i2c_clear_bus_hold - Clear bus hold bit in the controller's register
+ * @i2c_bus: Pointer to the I2C controller driver data structure
+ */
+static void cdns_i2c_clear_bus_hold(struct cdns_i2c_data *i2c_bus)
+{
+	uint32_t reg = cdns_i2c_readreg(i2c_bus, CDNS_I2C_CR_OFFSET);
+
+	if ((reg & CDNS_I2C_CR_HOLD) == CDNS_I2C_CR_HOLD) {
+		cdns_i2c_writereg(i2c_bus, reg & ~CDNS_I2C_CR_HOLD, CDNS_I2C_CR_OFFSET);
+	}
+}
+
+/**
+ * cdns_is_fifo_hold_quirk - Check if the FIFO hold quirk is triggered for I2C
+ * @i2c_bus: Pointer to the I2C controller driver data structure
+ * @hold_wrkaround: Boolean indicating if hold workarounds should be applied
+ *
+ * Return: True if the quirk condition is met, false otherwise.
+ */
+static inline bool cdns_is_fifo_hold_quirk(const struct cdns_i2c_data *i2c_bus,
+					   bool hold_wrkaround)
+{
+	return (hold_wrkaround && (i2c_bus->curr_recv_count == (i2c_bus->fifo_depth + 1U)));
+}
+
+/**
+ * cdns_i2c_master_handle_receive_interrupt - Handles I2C master receive interrupts
+ * @i2c_bus: Pointer to the I2C data structure
+ * @isr_status: Interrupt status, indicating the cause of the interrupt
+ */
+static void cdns_i2c_master_handle_receive_interrupt(struct cdns_i2c_data *i2c_bus,
+						     uint32_t isr_status)
+{
+	uint32_t transfer_size;
+	uint32_t xfer_size;
+
+	/* Handle reception interrupt (data available or transfer complete) */
+	if (((isr_status & CDNS_I2C_IXR_COMP) == 0U) && ((isr_status & CDNS_I2C_IXR_DATA) == 0U)) {
+		return;
+	}
+
+	/* Receiving Data: Keep reading as long as data is available */
+	while ((cdns_i2c_readreg(i2c_bus, CDNS_I2C_SR_OFFSET) & CDNS_I2C_SR_RXDV) != 0U) {
+		/* Ensure there's space to store received data */
+		if (i2c_bus->recv_count > 0U) {
+			*(i2c_bus->p_recv_buf) = (uint8_t)cdns_i2c_readreg(i2c_bus,
+									   CDNS_I2C_DATA_OFFSET);
+			i2c_bus->p_recv_buf++;
+			i2c_bus->recv_count--;
+			i2c_bus->curr_recv_count--;
+		} else {
+			/* Handle receive buffer overflow or unexpected condition */
+			LOG_ERR("I2C receive buffer overflow. Transfer aborted!");
+			i2c_bus->err_status |= CDNS_I2C_IXR_TO;
+			break;
+		}
+
+		/* Handle issues with receiving more data than expected */
+		if (cdns_is_fifo_hold_quirk(i2c_bus,
+					i2c_bus->recv_count > i2c_bus->curr_recv_count)) {
+			break;
+		}
+	}
+
+	/* Workaround for large data receive in case of FIFO space issues */
+	if (cdns_is_fifo_hold_quirk(i2c_bus, i2c_bus->recv_count > i2c_bus->curr_recv_count)) {
+		transfer_size = i2c_bus->recv_count - i2c_bus->fifo_depth;
+
+		if (transfer_size > i2c_bus->transfer_size) {
+			xfer_size = i2c_bus->transfer_size;
+		} else {
+			xfer_size = transfer_size;
+		}
+
+		/* Busy-wait until FIFO has space for more data */
+		while (cdns_i2c_readreg(i2c_bus, CDNS_I2C_XFER_SIZE_OFFSET) !=
+		       (i2c_bus->curr_recv_count - i2c_bus->fifo_depth)) {
+		}
+
+		/* Update the transfer size for the next batch of data */
+		cdns_i2c_writereg(i2c_bus, xfer_size, CDNS_I2C_XFER_SIZE_OFFSET);
+		i2c_bus->curr_recv_count = xfer_size + i2c_bus->fifo_depth;
+	}
+
+	/* Complete transfer if all data has been received and no more data is expected */
+	if (((isr_status & CDNS_I2C_IXR_COMP) == CDNS_I2C_IXR_COMP) &&
+	    (i2c_bus->recv_count == 0U)) {
+		/* Release bus hold if no longer needed */
+		if (i2c_bus->bus_hold_flag == 0U) {
+			cdns_i2c_clear_bus_hold(i2c_bus);
+		}
+		/* Notify completion of the transfer */
+		(void)k_event_post(&i2c_bus->xfer_done, I2C_XFER_COMPLETION_EVENT);
+	}
+}
+
+/**
+ * cdns_i2c_master_handle_transmit_interrupt - Handles I2C master transmit interrupts
+ * @i2c_bus: Pointer to the I2C data structure
+ * @isr_status: Interrupt status, indicating the cause of the interrupt
+ */
+static void cdns_i2c_master_handle_transmit_interrupt(struct cdns_i2c_data *i2c_bus,
+						      uint32_t isr_status)
+{
+	uint32_t avail_bytes;
+	uint32_t bytes_to_send;
+
+	/* Handle transmission interrupt (data sent or transfer complete) */
+	if ((isr_status & CDNS_I2C_IXR_COMP) == 0U) {
+		return;
+	}
+
+	/* Sending data: Check if there is any data left to send */
+	if (i2c_bus->send_count > 0U) {
+		/* Calculate how many bytes can be sent based on FIFO availability */
+		avail_bytes = i2c_bus->fifo_depth - cdns_i2c_readreg(i2c_bus,
+								     CDNS_I2C_XFER_SIZE_OFFSET);
+
+		if (i2c_bus->send_count > avail_bytes) {
+			bytes_to_send = avail_bytes;
+		} else {
+			bytes_to_send = i2c_bus->send_count;
+		}
+
+		/* Write data to the I2C data register */
+		while (bytes_to_send > 0U) {
+			cdns_i2c_writereg(i2c_bus, *(i2c_bus->p_send_buf), CDNS_I2C_DATA_OFFSET);
+			i2c_bus->p_send_buf++;
+			i2c_bus->send_count--;
+			bytes_to_send--;
+		}
+	} else {
+		/* If there is no data to send, signal transfer completion */
+		(void)k_event_post(&i2c_bus->xfer_done, I2C_XFER_COMPLETION_EVENT);
+	}
+
+	/* Clear bus hold if no more data is pending */
+	if ((i2c_bus->send_count == 0U) && (i2c_bus->bus_hold_flag == 0U)) {
+		cdns_i2c_clear_bus_hold(i2c_bus);
+	}
+}
+
+/**
+ * cdns_i2c_master_isr - Interrupt handler for the I2C device in master role
+ * @i2c_bus: Pointer to I2C device private data structure
+ *
+ * This function handles various interrupt events including data received,
+ * transfer complete, and error interrupts for the I2C master role.
+ */
+static void cdns_i2c_master_isr(struct cdns_i2c_data *i2c_bus)
+{
+	uint32_t isr_status;
+
+	/* Read the interrupt status register */
+	isr_status = cdns_i2c_readreg(i2c_bus, CDNS_I2C_ISR_OFFSET);
+
+	/* Clear interrupt status */
+	cdns_i2c_writereg(i2c_bus, isr_status, CDNS_I2C_ISR_OFFSET);
+
+	/* Update the error status based on interrupt flags */
+	i2c_bus->err_status = isr_status & CDNS_I2C_IXR_ERR_INTR_MASK;
+
+	/* Handling NACK or arbitration lost interrupts */
+	if ((isr_status & (CDNS_I2C_IXR_NACK | CDNS_I2C_IXR_ARB_LOST)) != 0U) {
+		(void)k_event_post(&i2c_bus->xfer_done, I2C_XFER_COMPLETION_EVENT);
+		return;
+	}
+
+	/* Handle reception interrupt */
+	if (i2c_bus->p_recv_buf != NULL) {
+		cdns_i2c_master_handle_receive_interrupt(i2c_bus, isr_status);
+	}
+
+	/* Handle transmission interrupt */
+	if (i2c_bus->p_recv_buf == NULL) {
+		cdns_i2c_master_handle_transmit_interrupt(i2c_bus, isr_status);
+	}
+}
+
+/**
+ * cdns_i2c_isr - Interrupt handler for the I2C controller
+ * @dev: Pointer to I2C device
+ */
+static void cdns_i2c_isr(const struct device *dev)
+{
+	struct cdns_i2c_data *i2c_bus = (struct cdns_i2c_data *)dev->data;
+
+	/* Handle the interrupt for master mode */
+	cdns_i2c_master_isr(i2c_bus);
+}
+
+/**
+ * cdns_i2c_mrecv - Prepare and start a master receive operation
+ * @i2c_bus: Pointer to the I2C data structure
+ * @msg_addr: The address of the slave device to receive data from
+ */
+static void cdns_i2c_mrecv(struct cdns_i2c_data *i2c_bus, uint16_t msg_addr)
+{
+	uint32_t ctrl_reg;
+	uint32_t isr_status;
+	bool hold_clear = false;
+	uint32_t addr;
+
+	/* Initialize the receive buffer and count */
+	i2c_bus->p_recv_buf = i2c_bus->p_msg->buf;
+	i2c_bus->recv_count = i2c_bus->p_msg->len;
+	i2c_bus->curr_recv_count = i2c_bus->recv_count;
+
+	/* Prepare controller for master receive mode and clear FIFO */
+	ctrl_reg = cdns_i2c_readreg(i2c_bus, CDNS_I2C_CR_OFFSET);
+	ctrl_reg |= CDNS_I2C_CR_RW | CDNS_I2C_CR_CLR_FIFO;
+
+	/* Check if the message size exceeds FIFO depth, hold the bus if true */
+	if (i2c_bus->recv_count > i2c_bus->fifo_depth) {
+		ctrl_reg |= CDNS_I2C_CR_HOLD;
+	}
+
+	cdns_i2c_writereg(i2c_bus, ctrl_reg, CDNS_I2C_CR_OFFSET);
+
+	/* Clear the interrupts in interrupt status register */
+	isr_status = cdns_i2c_readreg(i2c_bus, CDNS_I2C_ISR_OFFSET);
+	cdns_i2c_writereg(i2c_bus, isr_status, CDNS_I2C_ISR_OFFSET);
+
+	/* Set transfer size register and enable interrupts */
+	if ((i2c_bus->recv_count) > (i2c_bus->transfer_size)) {
+		cdns_i2c_writereg(i2c_bus, i2c_bus->transfer_size,
+				  CDNS_I2C_XFER_SIZE_OFFSET);
+		i2c_bus->curr_recv_count = i2c_bus->transfer_size;
+	} else {
+		cdns_i2c_writereg(i2c_bus, i2c_bus->recv_count, CDNS_I2C_XFER_SIZE_OFFSET);
+	}
+
+	/* Determine whether to clear the hold bit based on conditions */
+	if ((i2c_bus->bus_hold_flag == 0U) && (i2c_bus->recv_count <= i2c_bus->fifo_depth)) {
+		if ((ctrl_reg & CDNS_I2C_CR_HOLD) != 0U) {
+			hold_clear = true;
+		}
+	}
+
+	/* Mask address and prepare for I2C communication */
+	addr = msg_addr;
+	addr &= CDNS_I2C_ADDR_MASK;
+
+	/* Handle clearing of the hold bit */
+	if (hold_clear) {
+		ctrl_reg &= ~CDNS_I2C_CR_HOLD;
+		ctrl_reg &= ~CDNS_I2C_CR_CLR_FIFO;
+
+		/* Write the address and control register values */
+		cdns_i2c_writereg(i2c_bus, addr, CDNS_I2C_ADDR_OFFSET);
+		cdns_i2c_writereg(i2c_bus, ctrl_reg, CDNS_I2C_CR_OFFSET);
+		/* Read back to ensure write completion */
+		(void)cdns_i2c_readreg(i2c_bus, CDNS_I2C_CR_OFFSET);
+	} else {
+		/* Directly write the address if no need to clear the hold bit */
+		cdns_i2c_writereg(i2c_bus, addr, CDNS_I2C_ADDR_OFFSET);
+	}
+
+	/* Enable interrupts */
+	cdns_i2c_writereg(i2c_bus, CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
+}
+
+/**
+ * cdns_i2c_msend - Prepare and start a master send operation
+ * @i2c_bus: Pointer to the I2C data structure
+ * @msg_addr: I2C address of the slave to communicate with
+ */
+static void cdns_i2c_msend(struct cdns_i2c_data *i2c_bus, uint16_t msg_addr)
+{
+	uint32_t avail_bytes;
+	uint32_t bytes_to_send;
+	uint32_t ctrl_reg;
+	uint32_t isr_status;
+
+	/* Initialize send buffer and update send count */
+	i2c_bus->p_recv_buf = NULL;
+	i2c_bus->p_send_buf = i2c_bus->p_msg->buf;
+	i2c_bus->send_count = i2c_bus->p_msg->len;
+
+	/* Configure the controller in Master transmit mode and clear FIFO. */
+	ctrl_reg = cdns_i2c_readreg(i2c_bus, CDNS_I2C_CR_OFFSET);
+	ctrl_reg &= ~CDNS_I2C_CR_RW;
+	ctrl_reg |= CDNS_I2C_CR_CLR_FIFO;
+
+	/* Check if the message size exceeds FIFO depth, hold the bus if true */
+	if (i2c_bus->send_count > i2c_bus->fifo_depth) {
+		ctrl_reg |= CDNS_I2C_CR_HOLD;
+	}
+	cdns_i2c_writereg(i2c_bus, ctrl_reg, CDNS_I2C_CR_OFFSET);
+
+	/* Clear any previous interrupt flags */
+	isr_status = cdns_i2c_readreg(i2c_bus, CDNS_I2C_ISR_OFFSET);
+	cdns_i2c_writereg(i2c_bus, isr_status, CDNS_I2C_ISR_OFFSET);
+
+	/* Calculate available FIFO space and determine how many bytes to send */
+	avail_bytes = i2c_bus->fifo_depth - cdns_i2c_readreg(i2c_bus, CDNS_I2C_XFER_SIZE_OFFSET);
+	bytes_to_send = (i2c_bus->send_count > avail_bytes) ? avail_bytes : i2c_bus->send_count;
+
+	/* Send data to FIFO until all bytes are transmitted */
+	while (bytes_to_send > 0U) {
+		cdns_i2c_writereg(i2c_bus, (*(i2c_bus->p_send_buf)), CDNS_I2C_DATA_OFFSET);
+		(i2c_bus->p_send_buf)++;
+		i2c_bus->send_count--;
+		bytes_to_send--;
+	}
+
+	/* Clear the 'hold bus' flag if there's no more data and it's the last message */
+	if ((i2c_bus->bus_hold_flag == 0U) && (i2c_bus->send_count == 0U)) {
+		cdns_i2c_clear_bus_hold(i2c_bus);
+	}
+
+	/* Set the slave address to trigger operation. */
+	cdns_i2c_writereg(i2c_bus, ((uint32_t)msg_addr & CDNS_I2C_ADDR_MASK),
+				   CDNS_I2C_ADDR_OFFSET);
+
+	/* Enable interrupts after data transmission starts */
+	cdns_i2c_writereg(i2c_bus, CDNS_I2C_ENABLED_INTR_MASK, CDNS_I2C_IER_OFFSET);
+}
+
+/**
+ * cdns_i2c_master_reset - Reset the I2C master interface
+ * @i2c_bus: Pointer to the i2c driver instance
+ *
+ * This function performs a full reset of the I2C master interface
+ * The reset ensures that the interface is returned to a known idle state.
+ */
+static void cdns_i2c_master_reset(struct cdns_i2c_data *i2c_bus)
+{
+	uint32_t regval;
+
+	/* Disable the interrupts */
+	cdns_i2c_writereg(i2c_bus, CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
+
+	/* Clear the hold bit and flush FIFOs */
+	regval = cdns_i2c_readreg(i2c_bus, CDNS_I2C_CR_OFFSET);
+	regval &= ~CDNS_I2C_CR_HOLD;
+	regval |= CDNS_I2C_CR_CLR_FIFO;
+	cdns_i2c_writereg(i2c_bus, regval, CDNS_I2C_CR_OFFSET);
+
+	/* Reset transfer count register to zero */
+	cdns_i2c_writereg(i2c_bus, 0, CDNS_I2C_XFER_SIZE_OFFSET);
+
+	/* Clear the interrupt status register */
+	regval = cdns_i2c_readreg(i2c_bus, CDNS_I2C_ISR_OFFSET);
+	cdns_i2c_writereg(i2c_bus, regval, CDNS_I2C_ISR_OFFSET);
+
+	/* Clear the status register */
+	regval = cdns_i2c_readreg(i2c_bus, CDNS_I2C_SR_OFFSET);
+	cdns_i2c_writereg(i2c_bus, regval, CDNS_I2C_SR_OFFSET);
+}
+
+/**
+ * cdns_i2c_process_msg - Processes an I2C message on the specified I2C bus
+ * @i2c_bus: Pointer to the I2C data structure
+ * @msg: Pointer to the I2C message to be processed
+ * @addr: The 7-bit or 10-bit I2C address of the slave device
+ *
+ * Return: 0 on success, negative error code on failure.
+ */
+static int32_t cdns_i2c_process_msg(struct cdns_i2c_data *i2c_bus, struct i2c_msg *msg,
+				    uint16_t addr)
+{
+	int32_t ret = 0;
+	uint32_t reg;
+	k_timeout_t msg_timeout;
+	uint32_t events;
+
+	/* Initialize message processing state */
+	i2c_bus->p_msg = msg;
+	i2c_bus->err_status = 0U;
+	(void)k_event_clear(&i2c_bus->xfer_done, (uint32_t)I2C_XFER_COMPLETION_EVENT);
+
+	/* Handle 10-bit addressing mode */
+	reg = cdns_i2c_readreg(i2c_bus, CDNS_I2C_CR_OFFSET);
+	if ((msg->flags & I2C_MSG_ADDR_10_BITS) != 0U) {
+		/* Enable 10-bit address mode if not already enabled */
+		if ((reg & CDNS_I2C_CR_NEA) == CDNS_I2C_CR_NEA) {
+			cdns_i2c_writereg(i2c_bus,
+					reg & ~CDNS_I2C_CR_NEA,
+					CDNS_I2C_CR_OFFSET);
+		}
+	} else {
+		/* Disable 10-bit address mode if currently enabled */
+		if ((reg & CDNS_I2C_CR_NEA) == 0U) {
+			cdns_i2c_writereg(i2c_bus,
+					reg | CDNS_I2C_CR_NEA,
+					CDNS_I2C_CR_OFFSET);
+		}
+	}
+
+	/* Handle read/write flag and perform the appropriate action */
+	if ((msg->flags & I2C_MSG_READ) != 0U) {
+		cdns_i2c_mrecv(i2c_bus, addr); /* Receive data */
+	} else {
+		cdns_i2c_msend(i2c_bus, addr); /* Send data */
+	}
+
+	/* Calculate the minimal timeout based on message length */
+	msg_timeout.ticks = (((k_ticks_t)(msg->len) * 8)*(CDNS_I2C_TICKS_PER_SEC)) /
+			     ((k_ticks_t)(i2c_bus->i2c_clk));
+	msg_timeout.ticks += (CDNS_I2C_TICKS_PER_SEC / 2);
+	if (msg_timeout.ticks < CDNS_I2C_TIMEOUT_TICKS) {
+		msg_timeout.ticks = CDNS_I2C_TIMEOUT_TICKS;
+	}
+
+	/* Wait for the completion signal or timeout */
+	events = k_event_wait(&i2c_bus->xfer_done, (uint32_t)I2C_XFER_COMPLETION_EVENT,
+			      false, msg_timeout);
+	if ((events & I2C_XFER_COMPLETION_EVENT) == 0U) {
+		/* Timeout occurred, reset the master */
+		cdns_i2c_master_reset(i2c_bus);
+		ret = -ETIMEDOUT;
+		goto out;
+	}
+
+	/* Disable interrupt masking for the current transfer */
+	cdns_i2c_writereg(i2c_bus, CDNS_I2C_IXR_ALL_INTR_MASK, CDNS_I2C_IDR_OFFSET);
+
+	/* If it is bus arbitration error, try again */
+	if ((i2c_bus->err_status & CDNS_I2C_IXR_ARB_LOST) == CDNS_I2C_IXR_ARB_LOST) {
+		ret = -EAGAIN;
+	}
+
+out:
+	return ret;
+}
+
+/**
+ * cdns_i2c_wait_for_bus_free - Wait for the I2C bus to become free.
+ * @i2c_bus: Pointer to the I2C data structure that holds bus state information.
+ * @timeout_us: Maximum time (in microseconds) to wait for the bus to become free.
+ *
+ * This function waits for the I2C bus to become idle. It checks the bus state
+ * register periodically until the bus is free or the timeout occurs.
+ *
+ * Return: true if the bus is free within the timeout, false otherwise.
+ */
+static bool cdns_i2c_wait_for_bus_free(struct cdns_i2c_data *i2c_bus, uint32_t timeout_us)
+{
+	bool ret_flag = false;
+	uint32_t reg;
+
+	/* Poll until the bus is free or the timeout is reached */
+	while (timeout_us > 0U) {
+		reg = cdns_i2c_readreg(i2c_bus, CDNS_I2C_SR_OFFSET);
+		if ((reg & CDNS_I2C_SR_BA) == 0U) {
+			/* Bus Available (BA) bit is cleared, the bus is free */
+			ret_flag = true;
+			break;
+		}
+
+		/* Wait for a small period before checking again */
+		(void)k_usleep((int32_t)CDNS_I2C_POLL_US);
+		timeout_us -= CDNS_I2C_POLL_US;
+	}
+
+	if (timeout_us == 0U) {
+		/* Timeout reached, bus not available */
+		ret_flag = false;
+	}
+
+	return ret_flag;
+}
+
+/**
+ * cdns_i2c_master_handle_repeated_start - Handle repeated start during I2C master transfer
+ * @i2c_bus: Pointer to the I2C data structure that holds bus state information
+ * @msgs: Array of I2C messages to be processed
+ * @num_msgs: Number of messages in the @msgs array
+ *
+ * Return: 0 on success
+ */
+static int32_t cdns_i2c_master_handle_repeated_start(struct cdns_i2c_data *i2c_bus,
+						     struct i2c_msg *msgs, uint8_t num_msgs)
+{
+	uint32_t reg;
+	(void)msgs;
+	(void)num_msgs;
+
+	/* Set the hold flag and register */
+	i2c_bus->bus_hold_flag = 1;
+	reg = cdns_i2c_readreg(i2c_bus, CDNS_I2C_CR_OFFSET);
+	reg |= CDNS_I2C_CR_HOLD;
+	cdns_i2c_writereg(i2c_bus, reg, CDNS_I2C_CR_OFFSET);
+
+	return 0;
+}
+
+/**
+ * cdns_i2c_master_handle_transfer_error - Handle errors during I2C master transfer.
+ * @i2c_bus: Pointer to the I2C data structure
+ *
+ * Return: -EIO or -ENXIO.
+ */
+static int32_t cdns_i2c_master_handle_transfer_error(struct cdns_i2c_data *i2c_bus)
+{
+	int32_t ret;
+
+	/* Perform a reset of the I2C master to clear the error condition */
+	cdns_i2c_master_reset(i2c_bus);
+
+	if ((i2c_bus->err_status & CDNS_I2C_IXR_NACK) != 0U) {
+		ret = -ENXIO; /* No device found (NACK) */
+	} else {
+		ret = -EIO; /* General I/O error */
+	}
+
+	return ret;
+}
+
+/**
+ * cdns_i2c_master_transfer - Performs an I2C master transfer using the Cadence I2C controller.
+ * @dev: Pointer to the device structure representing the I2C controller.
+ * @msgs: Array of I2C message structures representing the messages to be sent/received.
+ * @num_msgs: Number of messages in the msgs array.
+ * @addr: The 7-bit or 10-bit I2C address of the slave device.
+ *
+ * Return: 0 on success, negative error code on failure.
+ */
+static int32_t cdns_i2c_master_transfer(const struct device *dev, struct i2c_msg *msgs,
+					uint8_t num_msgs, uint16_t addr)
+{
+	struct cdns_i2c_data *i2c_bus = (struct cdns_i2c_data *)dev->data;
+	int32_t ret = 0;
+	uint32_t count;
+	struct i2c_msg *msg_ptr = msgs;
+
+	(void)k_mutex_lock(&i2c_bus->bus_mutex, K_FOREVER);
+
+	/* Wait for the bus to be free */
+	if (cdns_i2c_wait_for_bus_free(i2c_bus, CDNS_I2C_TIMEOUT_US) == false) {
+		ret = -EAGAIN;
+		goto out;
+	}
+
+	/* Handle repeated start for multiple messages */
+	if (num_msgs > 1U) {
+		ret = cdns_i2c_master_handle_repeated_start(i2c_bus, msgs, num_msgs);
+		if (ret != 0) {
+			goto out;
+		}
+	}
+
+	/* Process each message individually */
+	for (count = 0; count < num_msgs; count++) {
+		/* Reset hold flag for the last message */
+		if (count == ((uint32_t)num_msgs - 1U)) {
+			i2c_bus->bus_hold_flag = 0;
+		}
+
+		/* Process the current message */
+		ret = cdns_i2c_process_msg(i2c_bus, msg_ptr, addr);
+		if (ret != 0) {
+			goto out;
+		}
+
+		/* Handle any errors during the transfer */
+		if ((i2c_bus->err_status) != 0U) {
+			ret = cdns_i2c_master_handle_transfer_error(i2c_bus);
+			if (ret != 0) {
+				goto out;
+			}
+		}
+
+		msg_ptr++;
+	}
+
+out:
+	(void)k_mutex_unlock(&i2c_bus->bus_mutex);
+
+	return ret;
+}
+
+/**
+ * cdns_i2c_init - Initialize the Cadence I2C controller
+ * @dev: Pointer to the device
+ *
+ * Return: 0 on success, negative error code on failure.
+ */
+static int32_t cdns_i2c_init(const struct device *dev)
+{
+	const struct cdns_i2c_config *config = (const struct cdns_i2c_config *)dev->config;
+	struct cdns_i2c_data *i2c_bus = (struct cdns_i2c_data *)dev->data;
+	int32_t ret;
+
+	(void)k_mutex_init(&i2c_bus->bus_mutex);
+	k_event_init(&i2c_bus->xfer_done);
+
+	/* Configure the control reg flags, transfer size */
+	i2c_bus->ctrl_reg = CDNS_I2C_CR_MASTER_EN_MASK;
+	i2c_bus->transfer_size = CDNS_I2C_TRANSFER_SIZE_DEFAULT;
+
+	/* Set the I2C clock frequency */
+	ret = cdns_i2c_setclk(i2c_bus, i2c_bus->i2c_clk);
+	if (ret != 0) {
+		LOG_ERR("Invalid SCL clock: %u Hz", i2c_bus->i2c_clk);
+		ret = -EINVAL;
+		goto out;
+	}
+
+	/* Configure IRQ */
+	config->irq_config_func();
+
+	/* Enable the I2C peripheral */
+	cdns_i2c_enable_peripheral(i2c_bus);
+
+	LOG_INF("%u KHz mmio %08lx", i2c_bus->i2c_clk/1000U, i2c_bus->membase);
+
+out:
+	return ret;
+}
+
+/* I2C driver API structure for the Cadence I2C controller */
+static DEVICE_API(i2c, cdns_i2c_driver_api) = {
+	.configure = cdns_i2c_configure,
+	.get_config = cdns_i2c_get_config,
+	.transfer = cdns_i2c_master_transfer,
+#ifdef CONFIG_I2C_RTIO
+	.iodev_submit = i2c_iodev_submit_fallback,
+#endif
+};
+
+#define CADENCE_I2C_INIT(n, compat)							\
+	static void cdns_i2c_config_func_##compat##_##n(void);				\
+											\
+	static const struct cdns_i2c_config cdns_i2c_config_##compat##_##n = {		\
+		.irq_config_func = cdns_i2c_config_func_##compat##_##n,			\
+	};										\
+											\
+	static struct cdns_i2c_data cdns_i2c_data_##compat##_##n = {			\
+		.membase = DT_INST_REG_ADDR(n),						\
+		.input_clk = DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency),	\
+		.i2c_clk = DT_INST_PROP(n, clock_frequency),				\
+		.fifo_depth = DT_INST_PROP(n, fifo_depth),				\
+	};										\
+											\
+	I2C_DEVICE_DT_INST_DEFINE(n, cdns_i2c_init, NULL,				\
+				&cdns_i2c_data_##compat##_##n,				\
+				&cdns_i2c_config_##compat##_##n, POST_KERNEL,		\
+				CONFIG_I2C_INIT_PRIORITY, &cdns_i2c_driver_api);	\
+											\
+	static void cdns_i2c_config_func_##compat##_##n(void)				\
+	{										\
+		IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), cdns_i2c_isr,	\
+			    DEVICE_DT_INST_GET(n), 0);					\
+											\
+		irq_enable(DT_INST_IRQN(n));						\
+	}
+
+#define DT_DRV_COMPAT cdns_i2c
+DT_INST_FOREACH_STATUS_OKAY_VARGS(CADENCE_I2C_INIT, DT_DRV_COMPAT)
diff --git a/drivers/i2c/i2c_dw.c b/drivers/i2c/i2c_dw.c
index 2915a79debc..1ee30a647dc 100644
--- a/drivers/i2c/i2c_dw.c
+++ b/drivers/i2c/i2c_dw.c
@@ -707,8 +707,15 @@ static int i2c_dw_transfer(const struct device *dev, struct i2c_msg *msgs, uint8
 		/* Wait for transfer to be done */
 		ret = k_sem_take(&dw->device_sync_sem, K_MSEC(CONFIG_I2C_DW_RW_TIMEOUT_MS));
 		if (ret != 0) {
+			if (test_bit_con_master_mode(reg_base)) {
+				/* Trigger abort and wait for it to complete. */
+				set_bit_enable_abort(reg_base);
+				(void)k_sem_take(&dw->device_sync_sem, K_MSEC(1));
+			}
 			write_intr_mask(DW_DISABLE_ALL_I2C_INT, reg_base);
 			value = read_clr_intr(reg_base);
+			ret = -ETIMEDOUT;
+			k_sem_reset(&dw->device_sync_sem);
 			break;
 		}
 
diff --git a/drivers/i2c/i2c_dw_registers.h b/drivers/i2c/i2c_dw_registers.h
index 117fcb196d0..12966b6ab7d 100644
--- a/drivers/i2c/i2c_dw_registers.h
+++ b/drivers/i2c/i2c_dw_registers.h
@@ -203,9 +203,11 @@ DEFINE_MM_REG_READ(clr_rx_done, DW_IC_REG_CLR_RX_DONE, 32)
 DEFINE_MM_REG_READ(clr_rd_req, DW_IC_REG_CLR_RD_REQ, 32)
 DEFINE_MM_REG_READ(clr_activity, DW_IC_REG_CLR_ACTIVITY, 32)
 
-#define DW_IC_ENABLE_EN_BIT (0)
+#define DW_IC_ENABLE_EN_BIT    (0)
+#define DW_IC_ENABLE_ABORT_BIT (1)
 DEFINE_CLEAR_BIT_OP(enable_en, DW_IC_REG_ENABLE, DW_IC_ENABLE_EN_BIT)
 DEFINE_SET_BIT_OP(enable_en, DW_IC_REG_ENABLE, DW_IC_ENABLE_EN_BIT)
+DEFINE_SET_BIT_OP(enable_abort, DW_IC_REG_ENABLE, DW_IC_ENABLE_ABORT_BIT)
 
 #define DW_IC_STATUS_ACTIVITY_BIT (0)
 #define DW_IC_STATUS_TFNT_BIT     (1)
diff --git a/drivers/i2c/i2c_emul.c b/drivers/i2c/i2c_emul.c
index ee2ae8d3975..7069b79af09 100644
--- a/drivers/i2c/i2c_emul.c
+++ b/drivers/i2c/i2c_emul.c
@@ -312,7 +312,7 @@ static DEVICE_API(i2c, i2c_emul_api) = {
 
 #define EMUL_FORWARD_ITEM(node_id, prop, idx)                                                      \
 	{                                                                                          \
-		.bus = DEVICE_DT_GET(DT_PHANDLE_BY_IDX(node_id, prop, idx)),                       \
+		.bus = DEVICE_DT_GET_BY_IDX(node_id, prop, idx),                                   \
 		.addr = DT_PHA_BY_IDX(node_id, prop, idx, addr),                                   \
 	},
 
diff --git a/drivers/i2c/i2c_ene_kb1200.c b/drivers/i2c/i2c_ene_kb1200.c
index 359f99793e4..e6853d38c7c 100644
--- a/drivers/i2c/i2c_ene_kb1200.c
+++ b/drivers/i2c/i2c_ene_kb1200.c
@@ -12,13 +12,20 @@
 #include <errno.h>
 #include <reg/fsmbm.h>
 
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(i2c_ene, CONFIG_I2C_LOG_LEVEL);
+
+#include "i2c-priv.h"
+
 struct i2c_kb1200_config {
 	struct fsmbm_regs *fsmbm;
+	uint32_t clock_freq;
 	const struct pinctrl_dev_config *pcfg;
 };
 
 struct i2c_kb1200_data {
-	struct k_sem mutex;
+	struct k_sem lock;
+	struct k_sem wait;
 	volatile uint8_t *msg_buf;
 	volatile uint32_t msg_len;
 	volatile uint8_t msg_flags;
@@ -39,6 +46,7 @@ static void i2c_kb1200_isr(const struct device *dev)
 			uint32_t remain = data->msg_len - data->index;
 			uint32_t send_bytes =
 				remain > FSMBM_BUFFER_SIZE ? FSMBM_BUFFER_SIZE : remain;
+
 			memcpy((void *)&config->fsmbm->FSMBMDAT[0],
 			       (void *)&data->msg_buf[data->index], send_bytes);
 			data->index += send_bytes;
@@ -52,7 +60,7 @@ static void i2c_kb1200_isr(const struct device *dev)
 		} else if (config->fsmbm->FSMBMPF & FSMBM_COMPLETE_EVENT) {
 			/* complete */
 			if (((config->fsmbm->FSMBMSTS & FSMBM_STS_MASK) == FSMBM_SMBUS_BUSY) &&
-			    ((config->fsmbm->FSMBMFRT & ___STOP) == ___NONE)) {
+			    ((config->fsmbm->FSMBMFRT & FRT_STOP) == FRT_NONE)) {
 				/* while packet finish without STOP, the error message is
 				 * FSMBM_SMBUS_BUSY
 				 */
@@ -61,10 +69,12 @@ static void i2c_kb1200_isr(const struct device *dev)
 				data->err_code = config->fsmbm->FSMBMSTS & FSMBM_STS_MASK;
 			}
 			data->state = STATE_COMPLETE;
+			k_sem_give(&data->wait);
 			config->fsmbm->FSMBMPF = FSMBM_COMPLETE_EVENT;
 		} else {
 			data->err_code = config->fsmbm->FSMBMSTS & FSMBM_STS_MASK;
 			data->state = STATE_COMPLETE;
+			k_sem_give(&data->wait);
 		}
 	} else if (data->state == STATE_RECEIVING) {
 		uint32_t remain = data->msg_len - data->index;
@@ -89,7 +99,7 @@ static void i2c_kb1200_isr(const struct device *dev)
 		} else if (config->fsmbm->FSMBMPF & FSMBM_COMPLETE_EVENT) {
 			/* complete */
 			if (((config->fsmbm->FSMBMSTS & FSMBM_STS_MASK) == FSMBM_SMBUS_BUSY) &&
-			    ((config->fsmbm->FSMBMFRT & ___STOP) == ___NONE)) {
+			    ((config->fsmbm->FSMBMFRT & FRT_STOP) == FRT_NONE)) {
 				/* while packet finish without STOP, the error message is
 				 * FSMBM_SMBUS_BUSY
 				 */
@@ -98,13 +108,16 @@ static void i2c_kb1200_isr(const struct device *dev)
 				data->err_code = config->fsmbm->FSMBMSTS & FSMBM_STS_MASK;
 			}
 			data->state = STATE_COMPLETE;
+			k_sem_give(&data->wait);
 			config->fsmbm->FSMBMPF = FSMBM_COMPLETE_EVENT;
 		} else {
 			data->err_code = config->fsmbm->FSMBMSTS & FSMBM_STS_MASK;
 			data->state = STATE_COMPLETE;
+			k_sem_give(&data->wait);
 		}
 	} else if (data->state == STATE_COMPLETE) {
 		config->fsmbm->FSMBMPF = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT);
+		k_sem_give(&data->wait);
 	}
 }
 
@@ -112,14 +125,16 @@ static int i2c_kb1200_poll_write(const struct device *dev, struct i2c_msg msg, u
 {
 	const struct i2c_kb1200_config *config = dev->config;
 	struct i2c_kb1200_data *data = dev->data;
-	uint8_t send_bytes;
+	uint32_t send_bytes;
+	int ret;
 
+	k_sem_reset(&data->wait);
 	if (msg.flags & I2C_MSG_STOP) {
 		/* No CMD, No CNT, No PEC, with STOP*/
-		config->fsmbm->FSMBMFRT = ___STOP;
+		config->fsmbm->FSMBMFRT = FRT_STOP;
 	} else {
 		/* No CMD, No CNT, No PEC, no STOP*/
-		config->fsmbm->FSMBMFRT = ___NONE;
+		config->fsmbm->FSMBMFRT = FRT_NONE;
 	}
 	data->msg_len = msg.len;
 	data->msg_buf = msg.buf;
@@ -135,7 +150,7 @@ static int i2c_kb1200_poll_write(const struct device *dev, struct i2c_msg msg, u
 	data->state = STATE_SENDING;
 
 	config->fsmbm->FSMBMCMD = 0;
-	config->fsmbm->FSMBMADR = (addr & ~BIT(0)) | FSMBM_WRITE;
+	config->fsmbm->FSMBMADR = (addr << 1) | FSMBM_WRITE;
 	config->fsmbm->FSMBMPF = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT);
 	/* If data over bufferSize increase 1 to force continue transmit */
 	if (msg.len >= (FSMBM_BUFFER_SIZE + 1)) {
@@ -145,15 +160,19 @@ static int i2c_kb1200_poll_write(const struct device *dev, struct i2c_msg msg, u
 	}
 	config->fsmbm->FSMBMIE = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT);
 	config->fsmbm->FSMBMPRTC_P = FLEXIBLE_PROTOCOL;
-	while (data->state != STATE_COMPLETE) {
-		;
+
+	/* Wait until ISR or timeout */
+	ret = k_sem_take(&data->wait, K_MSEC(FSMBM_MAX_TIMEOUT));
+	if (ret == -EAGAIN) {
+		data->err_code |= FSMBM_SDA_TIMEOUT;
 	}
 	data->state = STATE_IDLE;
-	if (data->err_code != 0) {
+	if (data->err_code) {
 		/* reset HW  */
 		config->fsmbm->FSMBMCFG |= FSMBM_HW_RESET;
 		return data->err_code;
 	}
+
 	return 0;
 }
 
@@ -161,13 +180,18 @@ static int i2c_kb1200_poll_read(const struct device *dev, struct i2c_msg msg, ui
 {
 	const struct i2c_kb1200_config *config = dev->config;
 	struct i2c_kb1200_data *data = dev->data;
+	int ret;
 
+	k_sem_reset(&data->wait);
+	if ((msg.flags & I2C_MSG_RESTART) && !(msg.flags & I2C_MSG_STOP)) {
+		LOG_ERR("ENE i2c format not support.");
+	}
 	if (msg.flags & I2C_MSG_STOP) {
 		/* No CMD, No CNT, No PEC, with STOP*/
-		config->fsmbm->FSMBMFRT = ___STOP;
+		config->fsmbm->FSMBMFRT = FRT_STOP;
 	} else {
 		/* No CMD, No CNT, No PEC, no STOP*/
-		config->fsmbm->FSMBMFRT = ___NONE;
+		config->fsmbm->FSMBMFRT = FRT_NONE;
 	}
 	data->msg_len = msg.len;
 	data->msg_buf = msg.buf;
@@ -178,7 +202,7 @@ static int i2c_kb1200_poll_read(const struct device *dev, struct i2c_msg msg, ui
 	data->state = STATE_RECEIVING;
 
 	config->fsmbm->FSMBMCMD = 0;
-	config->fsmbm->FSMBMADR = (addr & ~BIT(0)) | FSMBM_READ;
+	config->fsmbm->FSMBMADR = (addr << 1) | FSMBM_READ;
 	config->fsmbm->FSMBMPF = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT);
 	/* If data over bufferSize increase 1 to force continue receive */
 	if (msg.len >= (FSMBM_BUFFER_SIZE + 1)) {
@@ -188,15 +212,20 @@ static int i2c_kb1200_poll_read(const struct device *dev, struct i2c_msg msg, ui
 	}
 	config->fsmbm->FSMBMIE = (FSMBM_COMPLETE_EVENT | FSMBM_BLOCK_FINISH_EVENT);
 	config->fsmbm->FSMBMPRTC_P = FLEXIBLE_PROTOCOL;
-	while (data->state != STATE_COMPLETE) {
-		;
+
+	/* Wait until ISR or timeout */
+	ret = k_sem_take(&data->wait, K_MSEC(FSMBM_MAX_TIMEOUT));
+	if (ret == -EAGAIN) {
+		data->err_code |= FSMBM_SDA_TIMEOUT;
 	}
 	data->state = STATE_IDLE;
-	if (data->err_code != 0) {
+
+	if (data->err_code) {
 		/* reset HW  */
 		config->fsmbm->FSMBMCFG |= FSMBM_HW_RESET;
 		return data->err_code;
 	}
+
 	return 0;
 }
 
@@ -204,6 +233,7 @@ static int i2c_kb1200_poll_read(const struct device *dev, struct i2c_msg msg, ui
 static int i2c_kb1200_configure(const struct device *dev, uint32_t dev_config)
 {
 	const struct i2c_kb1200_config *config = dev->config;
+	uint32_t speed;
 
 	if (!(dev_config & I2C_MODE_CONTROLLER)) {
 		return -ENOTSUP;
@@ -213,7 +243,7 @@ static int i2c_kb1200_configure(const struct device *dev, uint32_t dev_config)
 		return -ENOTSUP;
 	}
 
-	uint32_t speed = I2C_SPEED_GET(dev_config);
+	speed = I2C_SPEED_GET(dev_config);
 
 	switch (speed) {
 	case I2C_SPEED_STANDARD:
@@ -242,7 +272,7 @@ static int i2c_kb1200_get_config(const struct device *dev, uint32_t *dev_config)
 	const struct i2c_kb1200_config *config = dev->config;
 
 	if ((config->fsmbm->FSMBMCFG & FSMBM_FUNCTION_ENABLE) == 0x00) {
-		printk("Cannot find i2c controller on 0x%p!\n", config->fsmbm);
+		LOG_ERR("Cannot find i2c controller on 0x%p!", config->fsmbm);
 		return -EIO;
 	}
 
@@ -251,6 +281,8 @@ static int i2c_kb1200_get_config(const struct device *dev, uint32_t *dev_config)
 		*dev_config = I2C_MODE_CONTROLLER | I2C_SPEED_SET(I2C_SPEED_STANDARD);
 		break;
 	case FSMBM_CLK_400K:
+	case FSMBM_CLK_500K:
+	case FSMBM_CLK_666K:
 		*dev_config = I2C_MODE_CONTROLLER | I2C_SPEED_SET(I2C_SPEED_FAST);
 		break;
 	case FSMBM_CLK_1M:
@@ -267,27 +299,27 @@ static int i2c_kb1200_transfer(const struct device *dev, struct i2c_msg *msgs, u
 			       uint16_t addr)
 {
 	struct i2c_kb1200_data *data = dev->data;
-	int ret;
+	int ret = 0;
 
-	/* get the mutex */
-	k_sem_take(&data->mutex, K_FOREVER);
+	/* lock */
+	k_sem_take(&data->lock, K_FOREVER);
 	for (int i = 0U; i < num_msgs; i++) {
 		if ((msgs[i].flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
 			ret = i2c_kb1200_poll_write(dev, msgs[i], addr);
 			if (ret) {
-				printk("%s Write error: 0x%X\n", dev->name, ret);
+				ret = -EIO;
 				break;
 			}
 		} else {
 			ret = i2c_kb1200_poll_read(dev, msgs[i], addr);
 			if (ret) {
-				printk("%s Read error: 0x%X\n", dev->name, ret);
+				ret = -EIO;
 				break;
 			}
 		}
 	}
-	/* release the mutex */
-	k_sem_give(&data->mutex);
+	/* release the lock */
+	k_sem_give(&data->lock);
 
 	return ret;
 }
@@ -332,14 +364,23 @@ static int i2c_kb1200_init(const struct device *dev)
 	int ret;
 	const struct i2c_kb1200_config *config = dev->config;
 	struct i2c_kb1200_data *data = dev->data;
+	uint32_t bitrate_cfg;
 
 	ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
 	if (ret != 0) {
 		return ret;
 	}
 
-	/* init mutex */
-	k_sem_init(&data->mutex, 1, 1);
+	bitrate_cfg = i2c_map_dt_bitrate(config->clock_freq);
+	if (!bitrate_cfg) {
+		return -EINVAL;
+	}
+
+	i2c_kb1200_configure(dev, bitrate_cfg | I2C_MODE_CONTROLLER);
+
+	k_sem_init(&data->wait, 0, 1);
+	/* init lock */
+	k_sem_init(&data->lock, 1, 1);
 	kb1200_fsmbm_irq_init();
 
 	return 0;
@@ -350,10 +391,11 @@ static int i2c_kb1200_init(const struct device *dev)
 	static struct i2c_kb1200_data i2c_kb1200_data_##inst;                                      \
 	static const struct i2c_kb1200_config i2c_kb1200_config_##inst = {                         \
 		.fsmbm = (struct fsmbm_regs *)DT_INST_REG_ADDR(inst),                              \
+		.clock_freq = DT_INST_PROP(inst, clock_frequency),                                 \
 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),                                      \
 	};                                                                                         \
 	I2C_DEVICE_DT_INST_DEFINE(inst, &i2c_kb1200_init, NULL, &i2c_kb1200_data_##inst,           \
-			      &i2c_kb1200_config_##inst, PRE_KERNEL_1,                             \
-			      CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &i2c_kb1200_api);
+				  &i2c_kb1200_config_##inst, PRE_KERNEL_1,                         \
+				  CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &i2c_kb1200_api);
 
 DT_INST_FOREACH_STATUS_OKAY(I2C_KB1200_DEVICE)
diff --git a/drivers/i2c/i2c_ifx_cat1.c b/drivers/i2c/i2c_ifx_cat1.c
index 3759be1d981..f272d87346e 100644
--- a/drivers/i2c/i2c_ifx_cat1.c
+++ b/drivers/i2c/i2c_ifx_cat1.c
@@ -81,11 +81,14 @@ static const cy_stc_scb_i2c_config_t _cyhal_i2c_default_config = {
 
 static int32_t _get_hw_block_num(CySCB_Type *reg_addr)
 {
+	extern const uint8_t _CYHAL_SCB_BASE_ADDRESS_INDEX[_SCB_ARRAY_SIZE];
+	extern CySCB_Type *const _CYHAL_SCB_BASE_ADDRESSES[_SCB_ARRAY_SIZE];
+
 	uint32_t i;
 
 	for (i = 0u; i < _SCB_ARRAY_SIZE; i++) {
 		if (_CYHAL_SCB_BASE_ADDRESSES[i] == reg_addr) {
-			return i;
+			return _CYHAL_SCB_BASE_ADDRESS_INDEX[i];
 		}
 	}
 
diff --git a/drivers/i2c/i2c_ite_enhance.c b/drivers/i2c/i2c_ite_enhance.c
index e67083218ff..1cfb68071d7 100644
--- a/drivers/i2c/i2c_ite_enhance.c
+++ b/drivers/i2c/i2c_ite_enhance.c
@@ -19,7 +19,7 @@
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(i2c_ite_enhance, CONFIG_I2C_LOG_LEVEL);
-
+#include "i2c_bitbang.h"
 #include "i2c-priv.h"
 
 /* Start smbus session from idle state */
@@ -121,6 +121,7 @@ struct i2c_enhance_data {
 	struct i2c_msg *active_msg;
 	struct k_mutex mutex;
 	struct k_sem device_sync_sem;
+	struct i2c_bitbang bitbang;
 	/* Index into output data */
 	size_t widx;
 	/* Index into input data */
@@ -1263,10 +1264,40 @@ static int i2c_enhance_init(const struct device *dev)
 	return 0;
 }
 
+static void i2c_enhance_set_scl(void *io_context, int state)
+{
+	const struct i2c_enhance_config *config = io_context;
+
+	gpio_pin_set_dt(&config->scl_gpios, state);
+}
+
+static void i2c_enhance_set_sda(void *io_context, int state)
+{
+	const struct i2c_enhance_config *config = io_context;
+
+	gpio_pin_set_dt(&config->sda_gpios, state);
+}
+
+static int i2c_enhance_get_sda(void *io_context)
+{
+	const struct i2c_enhance_config *config = io_context;
+	int ret = gpio_pin_get_dt(&config->sda_gpios);
+
+	/* Default high as that would be a NACK */
+	return ret != 0;
+}
+
+static const struct i2c_bitbang_io i2c_enhance_bitbang_io = {
+	.set_scl = i2c_enhance_set_scl,
+	.set_sda = i2c_enhance_set_sda,
+	.get_sda = i2c_enhance_get_sda,
+};
+
 static int i2c_enhance_recover_bus(const struct device *dev)
 {
 	const struct i2c_enhance_config *config = dev->config;
-	int i, status;
+	struct i2c_enhance_data *data = dev->data;
+	int status, ret;
 
 	/* Output type selection */
 	gpio_flags_t flags = GPIO_OUTPUT | (config->push_pull_recovery ? 0 : GPIO_OPEN_DRAIN);
@@ -1275,42 +1306,12 @@ static int i2c_enhance_recover_bus(const struct device *dev)
 	/* Set SDA of I2C as GPIO pin */
 	gpio_pin_configure_dt(&config->sda_gpios, flags);
 
-	/*
-	 * In I2C recovery bus, 1ms sleep interval for bitbanging i2c
-	 * is mainly to ensure that gpio has enough time to go from
-	 * low to high or high to low.
-	 */
-	/* Pull SCL and SDA pin to high */
-	gpio_pin_set_dt(&config->scl_gpios, 1);
-	gpio_pin_set_dt(&config->sda_gpios, 1);
-	k_msleep(1);
-
-	/* Start condition */
-	gpio_pin_set_dt(&config->sda_gpios, 0);
-	k_msleep(1);
-	gpio_pin_set_dt(&config->scl_gpios, 0);
-	k_msleep(1);
-
-	/* 9 cycles of SCL with SDA held high */
-	for (i = 0; i < 9; i++) {
-		/* SDA */
-		gpio_pin_set_dt(&config->sda_gpios, 1);
-		/* SCL */
-		gpio_pin_set_dt(&config->scl_gpios, 1);
-		k_msleep(1);
-		/* SCL */
-		gpio_pin_set_dt(&config->scl_gpios, 0);
-		k_msleep(1);
+	i2c_bitbang_init(&data->bitbang, &i2c_enhance_bitbang_io, (void *)config);
+
+	ret = i2c_bitbang_recover_bus(&data->bitbang);
+	if (ret != 0) {
+		LOG_ERR("%s: Failed to recover bus (err %d)", dev->name, ret);
 	}
-	/* SDA */
-	gpio_pin_set_dt(&config->sda_gpios, 0);
-	k_msleep(1);
-
-	/* Stop condition */
-	gpio_pin_set_dt(&config->scl_gpios, 1);
-	k_msleep(1);
-	gpio_pin_set_dt(&config->sda_gpios, 1);
-	k_msleep(1);
 
 	/* Set GPIO back to I2C alternate function */
 	status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
diff --git a/drivers/i2c/i2c_ite_it8xxx2.c b/drivers/i2c/i2c_ite_it8xxx2.c
index 203eaaa3d33..fd4311fb60f 100644
--- a/drivers/i2c/i2c_ite_it8xxx2.c
+++ b/drivers/i2c/i2c_ite_it8xxx2.c
@@ -21,7 +21,7 @@
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(i2c_ite_it8xxx2, CONFIG_I2C_LOG_LEVEL);
-
+#include "i2c_bitbang.h"
 #include "i2c-priv.h"
 
 /* Start smbus session from idle state */
@@ -74,6 +74,7 @@ struct i2c_it8xxx2_data {
 	struct i2c_msg *active_msg;
 	struct k_mutex mutex;
 	struct k_sem device_sync_sem;
+	struct i2c_bitbang bitbang;
 #ifdef CONFIG_I2C_IT8XXX2_FIFO_MODE
 	struct i2c_msg *msgs_list;
 	/* Read or write byte counts. */
@@ -1186,10 +1187,40 @@ static int i2c_it8xxx2_init(const struct device *dev)
 	return 0;
 }
 
+static void i2c_it8xxx2_set_scl(void *io_context, int state)
+{
+	const struct i2c_it8xxx2_config *config = io_context;
+
+	gpio_pin_set_dt(&config->scl_gpios, state);
+}
+
+static void i2c_it8xxx2_set_sda(void *io_context, int state)
+{
+	const struct i2c_it8xxx2_config *config = io_context;
+
+	gpio_pin_set_dt(&config->sda_gpios, state);
+}
+
+static int i2c_it8xxx2_get_sda(void *io_context)
+{
+	const struct i2c_it8xxx2_config *config = io_context;
+	int ret = gpio_pin_get_dt(&config->sda_gpios);
+
+	/* Default high as that would be a NACK */
+	return ret != 0;
+}
+
+static const struct i2c_bitbang_io i2c_it8xxx2_bitbang_io = {
+	.set_scl = i2c_it8xxx2_set_scl,
+	.set_sda = i2c_it8xxx2_set_sda,
+	.get_sda = i2c_it8xxx2_get_sda,
+};
+
 static int i2c_it8xxx2_recover_bus(const struct device *dev)
 {
 	const struct i2c_it8xxx2_config *config = dev->config;
-	int i, status;
+	struct i2c_it8xxx2_data *data = dev->data;
+	int status, ret;
 
 	/* Output type selection */
 	gpio_flags_t flags = GPIO_OUTPUT | (config->push_pull_recovery ? 0 : GPIO_OPEN_DRAIN);
@@ -1198,42 +1229,12 @@ static int i2c_it8xxx2_recover_bus(const struct device *dev)
 	/* Set SDA of I2C as GPIO pin */
 	gpio_pin_configure_dt(&config->sda_gpios, flags);
 
-	/*
-	 * In I2C recovery bus, 1ms sleep interval for bitbanging i2c
-	 * is mainly to ensure that gpio has enough time to go from
-	 * low to high or high to low.
-	 */
-	/* Pull SCL and SDA pin to high */
-	gpio_pin_set_dt(&config->scl_gpios, 1);
-	gpio_pin_set_dt(&config->sda_gpios, 1);
-	k_msleep(1);
-
-	/* Start condition */
-	gpio_pin_set_dt(&config->sda_gpios, 0);
-	k_msleep(1);
-	gpio_pin_set_dt(&config->scl_gpios, 0);
-	k_msleep(1);
-
-	/* 9 cycles of SCL with SDA held high */
-	for (i = 0; i < 9; i++) {
-		/* SDA */
-		gpio_pin_set_dt(&config->sda_gpios, 1);
-		/* SCL */
-		gpio_pin_set_dt(&config->scl_gpios, 1);
-		k_msleep(1);
-		/* SCL */
-		gpio_pin_set_dt(&config->scl_gpios, 0);
-		k_msleep(1);
+	i2c_bitbang_init(&data->bitbang, &i2c_it8xxx2_bitbang_io, (void *)config);
+
+	ret = i2c_bitbang_recover_bus(&data->bitbang);
+	if (ret != 0) {
+		LOG_ERR("%s: Failed to recover bus (err %d)", dev->name, ret);
 	}
-	/* SDA */
-	gpio_pin_set_dt(&config->sda_gpios, 0);
-	k_msleep(1);
-
-	/* Stop condition */
-	gpio_pin_set_dt(&config->scl_gpios, 1);
-	k_msleep(1);
-	gpio_pin_set_dt(&config->sda_gpios, 1);
-	k_msleep(1);
 
 	/* Set GPIO back to I2C alternate function of SCL */
 	status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
diff --git a/drivers/i2c/i2c_litex_litei2c.c b/drivers/i2c/i2c_litex_litei2c.c
new file mode 100644
index 00000000000..d73c8230854
--- /dev/null
+++ b/drivers/i2c/i2c_litex_litei2c.c
@@ -0,0 +1,352 @@
+/*
+ * Copyright (c) 2024 Vogl Electronic GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT litex_litei2c
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/i2c.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(i2c_litex_litei2c, CONFIG_I2C_LOG_LEVEL);
+
+#include "i2c-priv.h"
+
+#include <soc.h>
+
+#define MASTER_STATUS_TX_READY_OFFSET 0x0
+#define MASTER_STATUS_RX_READY_OFFSET 0x1
+#define MASTER_STATUS_NACK_OFFSET     0x8
+
+struct i2c_litex_litei2c_config {
+	uint32_t phy_speed_mode_addr;
+	uint32_t master_active_addr;
+	uint32_t master_settings_addr;
+	uint32_t master_addr_addr;
+	uint32_t master_rxtx_addr;
+	uint32_t master_status_addr;
+	uint32_t bitrate;
+};
+
+struct i2c_litex_litei2c_data {
+	struct k_mutex mutex;
+};
+
+static int i2c_litex_configure(const struct device *dev, uint32_t dev_config)
+{
+	const struct i2c_litex_litei2c_config *config = dev->config;
+	struct i2c_litex_litei2c_data *data = dev->data;
+
+	if (I2C_ADDR_10_BITS & dev_config) {
+		return -ENOTSUP;
+	}
+
+	if (!(I2C_MODE_CONTROLLER & dev_config)) {
+		return -ENOTSUP;
+	}
+
+	k_mutex_lock(&data->mutex, K_FOREVER);
+
+	/* Setup speed to use */
+	switch (I2C_SPEED_GET(dev_config)) {
+	case I2C_SPEED_STANDARD:
+		litex_write8(0, config->phy_speed_mode_addr);
+		break;
+	case I2C_SPEED_FAST:
+		litex_write8(1, config->phy_speed_mode_addr);
+		break;
+	case I2C_SPEED_FAST_PLUS:
+		litex_write8(2, config->phy_speed_mode_addr);
+		break;
+	default:
+		k_mutex_unlock(&data->mutex);
+		return -ENOTSUP;
+	}
+
+	k_mutex_unlock(&data->mutex);
+
+	return 0;
+}
+
+static int i2c_litex_get_config(const struct device *dev, uint32_t *config)
+{
+	const struct i2c_litex_litei2c_config *dev_config = dev->config;
+
+	*config = I2C_MODE_CONTROLLER;
+
+	switch (litex_read8(dev_config->phy_speed_mode_addr)) {
+	case 0:
+		*config |= I2C_SPEED_SET(I2C_SPEED_STANDARD);
+		break;
+	case 1:
+		*config |= I2C_SPEED_SET(I2C_SPEED_FAST);
+		break;
+	case 2:
+		*config |= I2C_SPEED_SET(I2C_SPEED_FAST_PLUS);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int i2c_litex_write_settings(const struct device *dev, uint8_t len_tx, uint8_t len_rx,
+				    bool recover)
+{
+	const struct i2c_litex_litei2c_config *config = dev->config;
+
+	uint32_t settings = len_tx | (len_rx << 8) | (recover << 16);
+
+	litex_write32(settings, config->master_settings_addr);
+
+	return 0;
+}
+
+static int i2c_litex_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
+			      uint16_t addr)
+{
+	const struct i2c_litex_litei2c_config *config = dev->config;
+	struct i2c_litex_litei2c_data *data = dev->data;
+	uint32_t len_tx_buf = 0;
+	uint32_t len_rx_buf = 0;
+	uint8_t len_tx = 0;
+	uint8_t len_rx = 0;
+
+	uint8_t *tx_buf_ptr;
+	uint8_t *rx_buf_ptr;
+
+	uint32_t tx_buf;
+	uint32_t rx_buf;
+
+	uint32_t tx_j = 0;
+	uint32_t rx_j = 0;
+
+	int ret = 0;
+
+	k_mutex_lock(&data->mutex, K_FOREVER);
+
+	litex_write8(1, config->master_active_addr);
+
+	LOG_DBG("addr: 0x%x", addr);
+	litex_write8((uint8_t)addr, config->master_addr_addr);
+
+	for (uint8_t i = 0; i < num_msgs; i++) {
+		if (msgs[i].flags & I2C_MSG_READ) {
+			len_tx_buf = 0;
+			len_rx_buf = msgs[i].len;
+			rx_buf_ptr = msgs[i].buf;
+			tx_buf_ptr = NULL;
+		} else {
+			len_tx_buf = msgs[i].len;
+			tx_buf_ptr = msgs[i].buf;
+			if (!(msgs[i].flags & I2C_MSG_STOP) && (i + 1 < num_msgs) &&
+			    (msgs[i + 1].flags & I2C_MSG_READ) &&
+			    (msgs[i + 1].flags & I2C_MSG_RESTART)) {
+				i++;
+				len_rx_buf = msgs[i].len;
+				rx_buf_ptr = msgs[i].buf;
+			} else {
+				len_rx_buf = 0;
+				rx_buf_ptr = NULL;
+			}
+		}
+
+		LOG_HEXDUMP_DBG(tx_buf_ptr, len_tx_buf, "tx_buf");
+
+		tx_j = 0;
+		rx_j = 0;
+		do {
+
+			if (len_tx_buf > (tx_j + 4)) {
+				len_tx = 5;
+				len_rx = 0;
+			} else {
+				len_tx = len_tx_buf - tx_j;
+
+				if (len_rx_buf > (rx_j + 4)) {
+					len_rx = 5;
+				} else {
+					len_rx = len_rx_buf - rx_j;
+				}
+			}
+
+			tx_buf = 0;
+
+			switch (len_tx) {
+			case 5:
+			case 4:
+				tx_buf |= tx_buf_ptr[0 + tx_j] << 24;
+				tx_buf |= tx_buf_ptr[1 + tx_j] << 16;
+				tx_buf |= tx_buf_ptr[2 + tx_j] << 8;
+				tx_buf |= tx_buf_ptr[3 + tx_j];
+				tx_j += 4;
+				break;
+			case 3:
+				tx_buf |= tx_buf_ptr[0 + tx_j] << 16;
+				tx_buf |= tx_buf_ptr[1 + tx_j] << 8;
+				tx_buf |= tx_buf_ptr[2 + tx_j];
+				tx_j += 3;
+				break;
+			case 2:
+				tx_buf |= tx_buf_ptr[0 + tx_j] << 8;
+				tx_buf |= tx_buf_ptr[1 + tx_j];
+				tx_j += 2;
+				break;
+			case 1:
+				tx_buf |= tx_buf_ptr[0 + tx_j];
+				tx_j += 1;
+				break;
+			default:
+				break;
+			}
+
+			LOG_DBG("len_tx: %d, len_rx: %d", len_tx, len_rx);
+			i2c_litex_write_settings(dev, len_tx, len_rx, false);
+
+			while (!(litex_read8(config->master_status_addr) &
+				 BIT(MASTER_STATUS_TX_READY_OFFSET))) {
+				;
+			}
+
+			LOG_DBG("tx_buf: 0x%x", tx_buf);
+			litex_write32(tx_buf, config->master_rxtx_addr);
+
+			while (!(litex_read8(config->master_status_addr) &
+				 BIT(MASTER_STATUS_RX_READY_OFFSET))) {
+				;
+			}
+
+			if (litex_read16(config->master_status_addr) &
+			    BIT(MASTER_STATUS_NACK_OFFSET)) {
+				LOG_DBG("NACK received (addr: 0x%x)", addr);
+				ret = -EIO;
+			}
+
+			rx_buf = litex_read32(config->master_rxtx_addr);
+			LOG_DBG("rx_buf: 0x%x", rx_buf);
+
+			switch (len_rx) {
+			case 5:
+			case 4:
+				rx_buf_ptr[0 + rx_j] = rx_buf >> 24;
+				rx_buf_ptr[1 + rx_j] = rx_buf >> 16;
+				rx_buf_ptr[2 + rx_j] = rx_buf >> 8;
+				rx_buf_ptr[3 + rx_j] = rx_buf;
+				rx_j += 4;
+				break;
+			case 3:
+				rx_buf_ptr[0 + rx_j] = rx_buf >> 16;
+				rx_buf_ptr[1 + rx_j] = rx_buf >> 8;
+				rx_buf_ptr[2 + rx_j] = rx_buf;
+				rx_j += 3;
+				break;
+			case 2:
+				rx_buf_ptr[0 + rx_j] = rx_buf >> 8;
+				rx_buf_ptr[1 + rx_j] = rx_buf;
+				rx_j += 2;
+				break;
+			case 1:
+				rx_buf_ptr[0 + rx_j] = rx_buf;
+				rx_j += 1;
+				break;
+			default:
+				break;
+			}
+
+			if (ret < 0) {
+				goto transfer_end;
+			}
+
+		} while ((tx_j < len_tx_buf) || (rx_j < len_rx_buf));
+
+		LOG_HEXDUMP_DBG(rx_buf_ptr, len_rx_buf, "rx_buf");
+	}
+
+transfer_end:
+
+	litex_write8(0, config->master_active_addr);
+
+	k_mutex_unlock(&data->mutex);
+
+	return ret;
+}
+
+static int i2c_litex_recover_bus(const struct device *dev)
+{
+	const struct i2c_litex_litei2c_config *config = dev->config;
+	struct i2c_litex_litei2c_data *data = dev->data;
+
+	k_mutex_lock(&data->mutex, K_FOREVER);
+
+	litex_write8(1, config->master_active_addr);
+
+	i2c_litex_write_settings(dev, 0, 0, true);
+
+	while (!(litex_read8(config->master_status_addr) & BIT(MASTER_STATUS_TX_READY_OFFSET))) {
+		;
+	}
+
+	litex_write32(0, config->master_rxtx_addr);
+
+	while (!(litex_read8(config->master_status_addr) & BIT(MASTER_STATUS_RX_READY_OFFSET))) {
+		;
+	}
+
+	(void)litex_read32(config->master_rxtx_addr);
+
+	litex_write8(0, config->master_active_addr);
+
+	k_mutex_unlock(&data->mutex);
+
+	return 0;
+}
+
+static int i2c_litex_init(const struct device *dev)
+{
+	const struct i2c_litex_litei2c_config *config = dev->config;
+	struct i2c_litex_litei2c_data *data = dev->data;
+	int ret;
+
+	k_mutex_init(&data->mutex);
+
+	ret = i2c_litex_configure(dev, I2C_MODE_CONTROLLER | i2c_map_dt_bitrate(config->bitrate));
+	if (ret != 0) {
+		LOG_ERR("failed to configure I2C: %d", ret);
+	}
+
+	return ret;
+}
+
+static DEVICE_API(i2c, i2c_litex_litei2c_driver_api) = {
+	.configure = i2c_litex_configure,
+	.get_config = i2c_litex_get_config,
+	.transfer = i2c_litex_transfer,
+	.recover_bus = i2c_litex_recover_bus,
+#ifdef CONFIG_I2C_RTIO
+	.iodev_submit = i2c_iodev_submit_fallback,
+#endif
+};
+
+/* Device Instantiation */
+
+#define I2C_LITEX_INIT(n)                                                                          \
+	static struct i2c_litex_litei2c_data i2c_litex_litei2c_data_##n;                           \
+												   \
+	static const struct i2c_litex_litei2c_config i2c_litex_litei2c_config_##n = {              \
+		.phy_speed_mode_addr = DT_INST_REG_ADDR_BY_NAME(n, phy_speed_mode),                \
+		.master_active_addr = DT_INST_REG_ADDR_BY_NAME(n, master_active),                  \
+		.master_settings_addr = DT_INST_REG_ADDR_BY_NAME(n, master_settings),              \
+		.master_addr_addr = DT_INST_REG_ADDR_BY_NAME(n, master_addr),                      \
+		.master_rxtx_addr = DT_INST_REG_ADDR_BY_NAME(n, master_rxtx),                      \
+		.master_status_addr = DT_INST_REG_ADDR_BY_NAME(n, master_status),                  \
+		.bitrate = DT_INST_PROP(n, clock_frequency),                                       \
+	};                                                                                         \
+                                                                                                   \
+	I2C_DEVICE_DT_INST_DEFINE(n, i2c_litex_init, NULL, &i2c_litex_litei2c_data_##n,            \
+				  &i2c_litex_litei2c_config_##n, POST_KERNEL,                      \
+				  CONFIG_I2C_INIT_PRIORITY, &i2c_litex_litei2c_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(I2C_LITEX_INIT)
diff --git a/drivers/i2c/i2c_ll_stm32.c b/drivers/i2c/i2c_ll_stm32.c
index 6e1d2c48f2c..15809dabc9f 100644
--- a/drivers/i2c/i2c_ll_stm32.c
+++ b/drivers/i2c/i2c_ll_stm32.c
@@ -5,6 +5,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <zephyr/drivers/dma.h>
+#include <zephyr/drivers/dma/dma_stm32.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/pm/device.h>
@@ -143,7 +145,8 @@ static int i2c_stm32_transfer(const struct device *dev, struct i2c_msg *msg,
 			      uint8_t num_msgs, uint16_t slave)
 {
 	struct i2c_stm32_data *data = dev->data;
-	struct i2c_msg *current, *next;
+	struct i2c_msg *current;
+	struct i2c_msg *next = NULL;
 	int ret = 0;
 
 	/* Check for validity of all messages, to prevent having to abort
@@ -582,6 +585,67 @@ static void i2c_stm32_irq_config_func_##index(const struct device *dev)	\
 
 #endif /* CONFIG_I2C_STM32_INTERRUPT */
 
+#ifdef CONFIG_I2C_STM32_V2_DMA
+
+#define I2C_DMA_INIT(index, dir)					\
+	.dir##_dma = {							\
+		.dev_dma = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir),\
+				(DEVICE_DT_GET(STM32_DMA_CTLR(index, dir))), (NULL)),\
+		.dma_channel = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir),\
+				(DT_INST_DMAS_CELL_BY_NAME(index, dir, channel)), (-1)),\
+		},
+
+void i2c_stm32_dma_tx_cb(const struct device *dma_dev, void *user_data,
+			uint32_t channel, int status)
+{
+	ARG_UNUSED(dma_dev);
+	ARG_UNUSED(user_data);
+	ARG_UNUSED(channel);
+
+	/* log DMA TX error */
+	if (status != 0) {
+		LOG_ERR("DMA error %d", status);
+	}
+}
+
+void i2c_stm32_dma_rx_cb(const struct device *dma_dev, void *user_data,
+			uint32_t channel, int status)
+{
+	ARG_UNUSED(dma_dev);
+	ARG_UNUSED(user_data);
+	ARG_UNUSED(channel);
+
+	/* log DMA RX error */
+	if (status != 0) {
+		LOG_ERR("DMA error %d", status);
+	}
+}
+
+#define I2C_DMA_DATA_INIT(index, dir, src, dest)			\
+	.dma_##dir##_cfg = {						\
+		.dma_slot = STM32_DMA_SLOT(index, dir, slot),		\
+		.channel_direction = STM32_DMA_CONFIG_DIRECTION(	\
+					STM32_DMA_CHANNEL_CONFIG(index, dir)),\
+		.cyclic =  STM32_DMA_CONFIG_CYCLIC(			\
+				STM32_DMA_CHANNEL_CONFIG(index, dir)),	\
+		.channel_priority = STM32_DMA_CONFIG_PRIORITY(		\
+				STM32_DMA_CHANNEL_CONFIG(index, dir)),	\
+		.source_data_size = STM32_DMA_CONFIG_##src##_DATA_SIZE(	\
+					STM32_DMA_CHANNEL_CONFIG(index, dir)),\
+		.dest_data_size = STM32_DMA_CONFIG_##dest##_DATA_SIZE(	\
+				STM32_DMA_CHANNEL_CONFIG(index, dir)),	\
+		.source_burst_length = 1,				\
+		.dest_burst_length = 1,					\
+		.dma_callback = i2c_stm32_dma_##dir##_cb,		\
+	},								\
+
+#else
+
+#define I2C_DMA_INIT(index, dir)
+#define I2C_DMA_DATA_INIT(index, dir, src, dest)
+
+#endif /* CONFIG_I2C_STM32_V2_DMA */
+
 #define STM32_I2C_INIT(index)						\
 STM32_I2C_IRQ_HANDLER_DECL(index);					\
 									\
@@ -607,9 +671,14 @@ static const struct i2c_stm32_config i2c_stm32_cfg_##index = {		\
 	IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2),		\
 		(.timings = (const struct i2c_config_timing *) i2c_timings_##index,\
 		 .n_timings = ARRAY_SIZE(i2c_timings_##index),))	\
+	I2C_DMA_INIT(index, tx)						\
+	I2C_DMA_INIT(index, rx)						\
 };									\
 									\
-static struct i2c_stm32_data i2c_stm32_dev_data_##index;		\
+static struct i2c_stm32_data i2c_stm32_dev_data_##index = {		\
+	I2C_DMA_DATA_INIT(index, tx, MEMORY, PERIPHERAL)		\
+	I2C_DMA_DATA_INIT(index, rx, PERIPHERAL, MEMORY)		\
+};									\
 									\
 PM_DEVICE_DT_INST_DEFINE(index, i2c_stm32_pm_action);			\
 									\
diff --git a/drivers/i2c/i2c_ll_stm32.h b/drivers/i2c/i2c_ll_stm32.h
index ec6db5b32a0..962492400e5 100644
--- a/drivers/i2c/i2c_ll_stm32.h
+++ b/drivers/i2c/i2c_ll_stm32.h
@@ -15,6 +15,8 @@
 #include <zephyr/drivers/gpio.h>
 #endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
 
+#include <zephyr/drivers/dma.h>
+
 typedef void (*irq_config_func_t)(const struct device *port);
 
 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2)
@@ -31,6 +33,13 @@ struct i2c_config_timing {
 };
 #endif
 
+#ifdef CONFIG_I2C_STM32_V2_DMA
+struct stream {
+	const struct device *dev_dma;
+	int32_t dma_channel;
+};
+#endif /* CONFIG_I2C_STM32_V2_DMA */
+
 struct i2c_stm32_config {
 #ifdef CONFIG_I2C_STM32_INTERRUPT
 	irq_config_func_t irq_config_func;
@@ -48,6 +57,10 @@ struct i2c_stm32_config {
 	const struct i2c_config_timing *timings;
 	size_t n_timings;
 #endif
+#ifdef CONFIG_I2C_STM32_V2_DMA
+	struct stream tx_dma;
+	struct stream rx_dma;
+#endif /* CONFIG_I2C_STM32_V2_DMA */
 };
 
 struct i2c_stm32_data {
@@ -91,12 +104,17 @@ struct i2c_stm32_data {
 	i2c_stm32_smbalert_cb_func_t smbalert_cb_func;
 	const struct device *smbalert_cb_dev;
 #endif
+#ifdef CONFIG_I2C_STM32_V2_DMA
+	struct dma_config dma_tx_cfg;
+	struct dma_config dma_rx_cfg;
+	struct dma_block_config dma_blk_cfg;
+#endif /* CONFIG_I2C_STM32_V2_DMA */
 };
 
-int32_t stm32_i2c_transaction(const struct device *dev,
+int stm32_i2c_transaction(const struct device *dev,
 			    struct i2c_msg msg, uint8_t *next_msg_flags,
 			    uint16_t periph);
-int32_t stm32_i2c_configure_timing(const struct device *dev, uint32_t clk);
+int stm32_i2c_configure_timing(const struct device *dev, uint32_t clk);
 int i2c_stm32_runtime_configure(const struct device *dev, uint32_t config);
 int i2c_stm32_get_config(const struct device *dev, uint32_t *config);
 
diff --git a/drivers/i2c/i2c_ll_stm32_v1.c b/drivers/i2c/i2c_ll_stm32_v1.c
index e4346726384..84624c53aa8 100644
--- a/drivers/i2c/i2c_ll_stm32_v1.c
+++ b/drivers/i2c/i2c_ll_stm32_v1.c
@@ -993,7 +993,7 @@ static int32_t stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg,
 }
 #endif /* CONFIG_I2C_STM32_INTERRUPT */
 
-int32_t stm32_i2c_configure_timing(const struct device *dev, uint32_t clock)
+int stm32_i2c_configure_timing(const struct device *dev, uint32_t clock)
 {
 	const struct i2c_stm32_config *cfg = dev->config;
 	struct i2c_stm32_data *data = dev->data;
diff --git a/drivers/i2c/i2c_ll_stm32_v2.c b/drivers/i2c/i2c_ll_stm32_v2.c
index 8e97fffbf09..367d15cef2a 100644
--- a/drivers/i2c/i2c_ll_stm32_v2.c
+++ b/drivers/i2c/i2c_ll_stm32_v2.c
@@ -21,6 +21,11 @@
 #include <zephyr/pm/device_runtime.h>
 #include "i2c_ll_stm32.h"
 
+#include <zephyr/cache.h>
+#include <zephyr/linker/linker-defs.h>
+#include <zephyr/mem_mgmt/mem_attr.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
 #define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(i2c_ll_stm32_v2);
@@ -117,6 +122,36 @@ static struct stm32_i2c_timings_t i2c_valid_timing[STM32_I2C_VALID_TIMING_NBR];
 static uint32_t i2c_valid_timing_nbr;
 #endif /* CONFIG_I2C_STM32_V2_TIMING */
 
+#ifdef CONFIG_I2C_STM32_V2_DMA
+static int configure_dma(struct stream const *dma, struct dma_config *dma_cfg,
+			 struct dma_block_config *blk_cfg)
+{
+	if (!device_is_ready(dma->dev_dma)) {
+		LOG_ERR("DMA device not ready");
+		return -ENODEV;
+	}
+
+	dma_cfg->head_block = blk_cfg;
+	dma_cfg->block_count = 1;
+
+	int ret = dma_config(dma->dev_dma, dma->dma_channel, dma_cfg);
+
+	if (ret != 0) {
+		LOG_ERR("Problem setting up DMA: %d", ret);
+		return ret;
+	}
+
+	ret = dma_start(dma->dev_dma, dma->dma_channel);
+
+	if (ret != 0) {
+		LOG_ERR("Problem starting DMA: %d", ret);
+		return ret;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_I2C_STM32_V2_DMA */
+
 static inline void msg_init(const struct device *dev, struct i2c_msg *msg,
 			    uint8_t *next_msg_flags, uint16_t slave,
 			    uint32_t transfer)
@@ -151,6 +186,50 @@ static inline void msg_init(const struct device *dev, struct i2c_msg *msg,
 #if defined(CONFIG_I2C_TARGET)
 		data->master_active = true;
 #endif
+
+#ifdef CONFIG_I2C_STM32_V2_DMA
+		if (msg->len) {
+			if (msg->flags & I2C_MSG_READ) {
+				/* Configure RX DMA */
+				data->dma_blk_cfg.source_address = LL_I2C_DMA_GetRegAddr(
+					cfg->i2c, LL_I2C_DMA_REG_DATA_RECEIVE);
+				data->dma_blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
+				data->dma_blk_cfg.dest_address = (uint32_t)msg->buf;
+				data->dma_blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;
+				data->dma_blk_cfg.block_size = msg->len;
+
+				if (configure_dma(&cfg->rx_dma, &data->dma_rx_cfg,
+						  &data->dma_blk_cfg) != 0) {
+					LOG_ERR("Problem setting up RX DMA");
+					return;
+				}
+				data->current.buf += msg->len;
+				data->current.len -= msg->len;
+				LL_I2C_EnableDMAReq_RX(i2c);
+			} else {
+				if (data->current.len) {
+					/* Configure TX DMA */
+					data->dma_blk_cfg.source_address =
+						(uint32_t)data->current.buf;
+					data->dma_blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
+					data->dma_blk_cfg.dest_address = LL_I2C_DMA_GetRegAddr(
+						cfg->i2c, LL_I2C_DMA_REG_DATA_TRANSMIT);
+					data->dma_blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
+					data->dma_blk_cfg.block_size = msg->len;
+
+					if (configure_dma(&cfg->tx_dma, &data->dma_tx_cfg,
+							  &data->dma_blk_cfg) != 0) {
+						LOG_ERR("Problem setting up TX DMA");
+						return;
+					}
+					data->current.buf += data->current.len;
+					data->current.len -= data->current.len;
+					LL_I2C_EnableDMAReq_TX(i2c);
+				}
+			}
+		}
+#endif /* CONFIG_I2C_STM32_V2_DMA */
+
 		LL_I2C_Enable(i2c);
 
 		LL_I2C_GenerateStartCondition(i2c);
@@ -209,6 +288,17 @@ static void stm32_i2c_master_mode_end(const struct device *dev)
 		LL_I2C_Disable(i2c);
 	}
 #endif
+
+#ifdef CONFIG_I2C_STM32_V2_DMA
+	if (data->current.msg->flags & I2C_MSG_READ) {
+		dma_stop(cfg->rx_dma.dev_dma, cfg->rx_dma.dma_channel);
+		LL_I2C_DisableDMAReq_RX(i2c);
+	} else {
+		dma_stop(cfg->tx_dma.dev_dma, cfg->tx_dma.dma_channel);
+		LL_I2C_DisableDMAReq_TX(i2c);
+	}
+#endif /* CONFIG_I2C_STM32_V2_DMA */
+
 	k_sem_give(&data->device_sync_sem);
 }
 
@@ -508,6 +598,17 @@ static void stm32_i2c_event(const struct device *dev)
 			LL_I2C_GenerateStopCondition(i2c);
 		} else {
 			stm32_i2c_disable_transfer_interrupts(dev);
+
+#ifdef CONFIG_I2C_STM32_V2_DMA
+			if (data->current.msg->flags & I2C_MSG_READ) {
+				dma_stop(cfg->rx_dma.dev_dma, cfg->rx_dma.dma_channel);
+				LL_I2C_DisableDMAReq_RX(i2c);
+			} else {
+				dma_stop(cfg->tx_dma.dev_dma, cfg->tx_dma.dma_channel);
+				LL_I2C_DisableDMAReq_TX(i2c);
+			}
+#endif /* CONFIG_I2C_STM32_V2_DMA */
+
 			k_sem_give(&data->device_sync_sem);
 		}
 	}
@@ -585,6 +686,37 @@ void stm32_i2c_error_isr(void *arg)
 }
 #endif
 
+#if defined(CONFIG_DCACHE) && defined(CONFIG_I2C_STM32_V2_DMA)
+static bool buf_in_nocache(uintptr_t buf, size_t len_bytes)
+{
+	bool buf_within_nocache = false;
+
+#ifdef CONFIG_NOCACHE_MEMORY
+	/* Check if buffer is in nocache region defined by the linker */
+	buf_within_nocache = (buf >= ((uintptr_t)_nocache_ram_start)) &&
+		((buf + len_bytes - 1) <= ((uintptr_t)_nocache_ram_end));
+	if (buf_within_nocache) {
+		return true;
+	}
+#endif /* CONFIG_NOCACHE_MEMORY */
+
+#ifdef CONFIG_MEM_ATTR
+	/* Check if buffer is in nocache memory region defined in DT */
+	buf_within_nocache = mem_attr_check_buf(
+		(void *)buf, len_bytes, DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)) == 0;
+	if (buf_within_nocache) {
+		return true;
+	}
+#endif /* CONFIG_MEM_ATTR */
+
+	/* Check if buffer is in RO region (Flash..) */
+	buf_within_nocache = (buf >= ((uintptr_t)__rodata_region_start)) &&
+		((buf + len_bytes - 1) <= ((uintptr_t)__rodata_region_end));
+
+	return buf_within_nocache;
+}
+#endif /* CONFIG_DCACHE && CONFIG_I2C_STM32_V2_DMA */
+
 static int stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg,
 			uint8_t *next_msg_flags, uint16_t slave)
 {
@@ -600,6 +732,14 @@ static int stm32_i2c_msg_write(const struct device *dev, struct i2c_msg *msg,
 	data->current.is_err = 0U;
 	data->current.msg = msg;
 
+#if defined(CONFIG_DCACHE) && defined(CONFIG_I2C_STM32_V2_DMA)
+	if (!buf_in_nocache((uintptr_t)msg->buf, msg->len)) {
+		LOG_DBG("Tx buffer at %p (len %zu) is in cached memory; cleaning cache", msg->buf,
+			msg->len);
+		sys_cache_data_flush_range((void *)msg->buf, msg->len);
+	}
+#endif /* CONFIG_DCACHE && CONFIG_I2C_STM32_V2_DMA*/
+
 	msg_init(dev, msg, next_msg_flags, slave, LL_I2C_REQUEST_WRITE);
 
 	stm32_i2c_enable_transfer_interrupts(dev);
@@ -671,6 +811,14 @@ static int stm32_i2c_msg_read(const struct device *dev, struct i2c_msg *msg,
 		is_timeout = true;
 	}
 
+#if defined(CONFIG_DCACHE) && defined(CONFIG_I2C_STM32_V2_DMA)
+	if (!buf_in_nocache((uintptr_t)msg->buf, msg->len)) {
+		LOG_DBG("Rx buffer at %p (len %zu) is in cached memory; invalidating cache",
+			msg->buf, msg->len);
+		sys_cache_data_invd_range((void *)msg->buf, msg->len);
+	}
+#endif /* CONFIG_DCACHE && CONFIG_I2C_STM32_V2_DMA */
+
 	if (data->current.is_nack || data->current.is_err ||
 	    data->current.is_arlo || is_timeout) {
 		goto error;
diff --git a/drivers/i2c/i2c_max32.c b/drivers/i2c/i2c_max32.c
index c42f837bf3e..d23910b416c 100644
--- a/drivers/i2c/i2c_max32.c
+++ b/drivers/i2c/i2c_max32.c
@@ -100,7 +100,7 @@ static int api_configure(const struct device *dev, uint32_t dev_cfg)
 		return -ENOTSUP;
 	}
 
-	return ret;
+	return ((ret > 0) ? 0 : -EIO);
 }
 
 #ifdef CONFIG_I2C_TARGET
@@ -292,11 +292,13 @@ static void i2c_max32_dma_callback(const struct device *dev, void *arg, uint32_t
 
 	if (status < 0) {
 		data->err = -EIO;
+		Wrap_MXC_I2C_SetIntEn(cfg->regs, 0, 0);
+		k_sem_give(&data->xfer);
 	} else {
-		if (data->req.restart) {
-			Wrap_MXC_I2C_Restart(cfg->regs);
-		} else {
+		if (data->flags & I2C_MSG_STOP) {
 			Wrap_MXC_I2C_Stop(cfg->regs);
+		} else if (!(data->flags & I2C_MSG_READ)) {
+			MXC_I2C_EnableInt(cfg->regs, ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
 		}
 	}
 }
@@ -366,48 +368,75 @@ static int i2c_max32_transfer_dma(const struct device *dev, struct i2c_msg *msgs
 	const struct max32_i2c_config *const cfg = dev->config;
 	struct max32_i2c_data *data = dev->data;
 	mxc_i2c_regs_t *i2c = cfg->regs;
+	mxc_i2c_req_t *req = &data->req;
 	uint8_t target_rw;
 	unsigned int i = 0;
 
 	k_sem_take(&data->lock, K_FOREVER);
 
+	req->addr = target_address;
+	req->i2c = i2c;
+
 	MXC_I2C_SetRXThreshold(i2c, 1);
 	MXC_I2C_SetTXThreshold(i2c, 2);
 	MXC_I2C_ClearTXFIFO(i2c);
 	MXC_I2C_ClearRXFIFO(i2c);
 
+	/* First message should always begin with a START condition */
+	msgs[0].flags |= I2C_MSG_RESTART;
+
 	for (i = 0; i < num_msgs; i++) {
-		data->req.restart = !(msgs[i].flags & I2C_MSG_STOP);
 		if (msgs[i].flags & I2C_MSG_READ) {
+			req->rx_len = msgs[i].len;
+			req->tx_len = 0;
 			target_rw = (target_address << 1) | 0x1;
-			MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1);
-			Wrap_MXC_I2C_SetRxCount(i2c, msgs[i].len);
 			ret = i2c_max32_rx_dma_load(dev, &msgs[i]);
 			if (ret < 0) {
 				break;
 			}
-
-			MXC_I2C_EnableInt(
-				i2c, ADI_MAX32_I2C_INT_EN0_DONE | ADI_MAX32_I2C_INT_EN0_ERR, 0);
-			i2c->dma |= ADI_MAX32_I2C_DMA_RX_EN;
 		} else {
+			req->tx_len = msgs[i].len;
+			req->rx_len = 0;
 			target_rw = (target_address << 1) & ~0x1;
-			MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1);
 			ret = i2c_max32_tx_dma_load(dev, &msgs[i]);
 			if (ret < 0) {
 				break;
 			}
+		}
 
-			MXC_I2C_EnableInt(
-				i2c, ADI_MAX32_I2C_INT_EN0_DONE | ADI_MAX32_I2C_INT_EN0_ERR, 0);
-			i2c->dma |= ADI_MAX32_I2C_DMA_TX_EN;
+		/*
+		 *  If previous message ends with a STOP condition, this message
+		 *  should begin with a START
+		 */
+		if (i > 0) {
+			if ((msgs[i - 1].flags & (I2C_MSG_STOP | I2C_MSG_READ))) {
+				msgs[i].flags |= I2C_MSG_RESTART;
+			}
 		}
+
+		data->flags = msgs[i].flags;
+		data->readb = 0;
+		data->written = 0;
 		data->err = 0;
 
-		Wrap_MXC_I2C_Start(i2c);
+		MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK);
+		MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ERR, 0);
+		Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len);
+
+		if ((data->flags & I2C_MSG_RESTART)) {
+			MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
+			MXC_I2C_Start(i2c);
+			Wrap_MXC_I2C_WaitForRestart(i2c);
+			MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1);
+		} else if (req->tx_len) {
+			MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
+			i2c->dma |= ADI_MAX32_I2C_DMA_TX_EN;
+		}
+
 		ret = k_sem_take(&data->xfer, K_FOREVER);
-		Wrap_MXC_I2C_SetIntEn(i2c, 0, 0);
-		i2c->dma &= ~(ADI_MAX32_I2C_DMA_TX_EN | ADI_MAX32_I2C_DMA_RX_EN);
+
+		i2c->dma &= ~(ADI_MAX32_I2C_DMA_TX_EN);
+		i2c->dma &= ~(ADI_MAX32_I2C_DMA_RX_EN);
 
 		if (data->err) {
 			ret = data->err;
@@ -416,6 +445,7 @@ static int i2c_max32_transfer_dma(const struct device *dev, struct i2c_msg *msgs
 			MXC_I2C_Stop(i2c);
 			dma_stop(cfg->tx_dma.dev, cfg->tx_dma.channel);
 			dma_stop(cfg->rx_dma.dev, cfg->rx_dma.channel);
+			break;
 		}
 	}
 
@@ -502,11 +532,19 @@ static int i2c_max32_transfer(const struct device *dev, struct i2c_msg *msgs, ui
 			ret = data->err;
 		} else {
 			if (data->flags & I2C_MSG_STOP) {
-				/* Wait for busy flag to be cleared */
-				while (i2c->status & ADI_MAX32_I2C_STATUS_MASTER_BUSY) {
+				/* 0 length transactions are needed for I2C SCANs */
+				if ((req->tx_len == req->rx_len) && (req->tx_len == 0)) {
+					MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK,
+							   ADI_MAX32_I2C_INT_FL1_MASK);
+				} else {
+					/* Wait for busy flag to be cleared for clock stetching
+					 * use-cases
+					 */
+					while (i2c->status & ADI_MAX32_I2C_STATUS_MASTER_BUSY) {
+					}
+					MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK,
+							   ADI_MAX32_I2C_INT_FL1_MASK);
 				}
-				MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK,
-						   ADI_MAX32_I2C_INT_FL1_MASK);
 			}
 		}
 		if (ret) {
@@ -725,6 +763,12 @@ static void i2c_max32_isr_controller(const struct device *dev, mxc_i2c_regs_t *i
 			MXC_I2C_EnableInt(
 				i2c, ADI_MAX32_I2C_INT_EN0_RX_THD | ADI_MAX32_I2C_INT_EN0_DONE, 0);
 		}
+		/* 0-length transactions are needed for I2C scans.
+		 * In these cases, just give up the semaphore.
+		 */
+		else if ((req->tx_len == req->rx_len) && (req->tx_len == 0)) {
+			k_sem_give(&data->xfer);
+		}
 	}
 
 	if (req->tx_len &&
@@ -785,6 +829,8 @@ static void i2c_max32_isr_controller(const struct device *dev, mxc_i2c_regs_t *i
 static void i2c_max32_isr_controller_dma(const struct device *dev, mxc_i2c_regs_t *i2c)
 {
 	struct max32_i2c_data *data = dev->data;
+	const struct max32_i2c_config *cfg = dev->config;
+	struct dma_status dma_stat;
 	uint32_t int_fl0, int_fl1;
 	uint32_t int_en0, int_en1;
 
@@ -797,7 +843,34 @@ static void i2c_max32_isr_controller_dma(const struct device *dev, mxc_i2c_regs_
 		Wrap_MXC_I2C_SetIntEn(i2c, 0, 0);
 		k_sem_give(&data->xfer);
 	} else {
-		if (!data->err && (int_en0 & ADI_MAX32_I2C_INT_EN0_DONE)) {
+		/* Run DMA once address is acknowledged */
+		if ((int_fl0 & ADI_MAX32_I2C_INT_FL0_ADDR_ACK)) {
+			MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
+			MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
+			if (data->flags & I2C_MSG_READ) {
+				i2c->dma |= ADI_MAX32_I2C_DMA_RX_EN;
+			} else {
+				i2c->dma |= ADI_MAX32_I2C_DMA_TX_EN;
+			}
+		} else if ((int_fl0 & ADI_MAX32_I2C_INT_FL0_DONE)) {
+			MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0);
+			if ((data->flags & I2C_MSG_READ)) {
+				dma_get_status(cfg->rx_dma.dev, cfg->rx_dma.channel, &dma_stat);
+				/* Send RESTART if more data is expected */
+				if (dma_stat.pending_length > 0) {
+					Wrap_MXC_I2C_SetRxCount(i2c, dma_stat.pending_length);
+					MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0);
+					i2c->fifo = (data->req.addr << 1) | 0x1;
+					Wrap_MXC_I2C_Restart(i2c);
+				} else {
+					k_sem_give(&data->xfer);
+				}
+			} else {
+				k_sem_give(&data->xfer);
+			}
+		} else if ((int_fl0 & ADI_MAX32_I2C_INT_FL0_TX_THD)) {
+			MXC_I2C_DisableInt(
+				i2c, ADI_MAX32_I2C_INT_EN0_DONE | ADI_MAX32_I2C_INT_EN0_TX_THD, 0);
 			k_sem_give(&data->xfer);
 		}
 	}
diff --git a/drivers/i2c/i2c_max32_rtio.c b/drivers/i2c/i2c_max32_rtio.c
index 40ceeffdd41..411044bef2f 100644
--- a/drivers/i2c/i2c_max32_rtio.c
+++ b/drivers/i2c/i2c_max32_rtio.c
@@ -97,7 +97,7 @@ static int max32_do_configure(const struct device *dev, uint32_t dev_cfg)
 		return -ENOTSUP;
 	}
 
-	return ret;
+	return ((ret > 0) ? 0 : -EIO);
 }
 
 static void max32_complete(const struct device *dev, int status);
@@ -199,6 +199,7 @@ static void i2c_max32_isr_controller(const struct device *dev, mxc_i2c_regs_t *i
 	if (int_fl0 & ADI_MAX32_I2C_INT_FL0_ERR) {
 		data->err = -EIO;
 		Wrap_MXC_I2C_SetIntEn(i2c, 0, 0);
+		max32_complete(dev, data->err);
 		return;
 	}
 
@@ -303,7 +304,6 @@ static void max32_complete(const struct device *dev, int status)
 	struct max32_i2c_data *data = dev->data;
 	struct i2c_rtio *const ctx = data->ctx;
 	const struct max32_i2c_config *const cfg = dev->config;
-	int ret = 0;
 
 	if (cfg->regs->clkhi == I2C_STANDAR_BITRATE_CLKHI) {
 		/* When I2C is configured in Standard Bitrate 100KHz
@@ -319,9 +319,12 @@ static void max32_complete(const struct device *dev, int status)
 		LOG_ERR("For Standard speed HW needs more time to run");
 		return;
 	}
-	if (i2c_rtio_complete(ctx, ret)) {
+
+	if (i2c_rtio_complete(ctx, status)) {
 		data->second_msg_flag = 1;
 		max32_start(dev);
+	} else {
+		data->second_msg_flag = 0;
 	}
 }
 
diff --git a/drivers/i2c/i2c_mcux_lpi2c.c b/drivers/i2c/i2c_mcux_lpi2c.c
index 86dc6303e25..3121b6902a4 100644
--- a/drivers/i2c/i2c_mcux_lpi2c.c
+++ b/drivers/i2c/i2c_mcux_lpi2c.c
@@ -42,9 +42,6 @@ LOG_MODULE_REGISTER(mcux_lpi2c);
 
 struct mcux_lpi2c_config {
 	DEVICE_MMIO_NAMED_ROM(reg_base);
-#ifdef CONFIG_NXP_LP_FLEXCOMM
-	const struct device *parent_dev;
-#endif
 	const struct device *clock_dev;
 	clock_control_subsys_t clock_subsys;
 	void (*irq_config_func)(const struct device *dev);
@@ -536,16 +533,8 @@ static int mcux_lpi2c_init(const struct device *dev)
 	if (error) {
 		return error;
 	}
-#if CONFIG_NXP_LP_FLEXCOMM
-	/* When using LP Flexcomm driver, register the interrupt handler
-	 * so we receive notification from the LP Flexcomm interrupt handler.
-	 */
-	nxp_lp_flexcomm_setirqhandler(config->parent_dev, dev,
-				      LP_FLEXCOMM_PERIPH_LPI2C, mcux_lpi2c_isr);
-#else
-	/* Interrupt is managed by this driver */
+
 	config->irq_config_func(dev);
-#endif
 
 	return 0;
 }
@@ -583,21 +572,31 @@ static DEVICE_API(i2c, mcux_lpi2c_driver_api) = {
 	IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0),				\
 		(I2C_MCUX_LPI2C_MODULE_IRQ_CONNECT(n)))
 
-#ifdef CONFIG_NXP_LP_FLEXCOMM
-#define PARENT_DEV(n)							\
-	.parent_dev = DEVICE_DT_GET(DT_INST_PARENT(n)),
-#else
-#define PARENT_DEV(n)
-#endif /* CONFIG_NXP_LP_FLEXCOMM */
+/* When using LP Flexcomm driver, register the interrupt handler
+ * so we receive notification from the LP Flexcomm interrupt handler.
+ */
+#define I2C_MCUX_LPI2C_LPFLEXCOMM_IRQ_FUNC(n)				\
+	nxp_lp_flexcomm_setirqhandler(DEVICE_DT_GET(DT_INST_PARENT(n)), \
+					DEVICE_DT_INST_GET(n),		\
+					LP_FLEXCOMM_PERIPH_LPI2C,	\
+					mcux_lpi2c_isr)
+
+#define I2C_MCUX_LPI2C_IRQ_SETUP_FUNC(n)				\
+	COND_CODE_1(DT_NODE_HAS_COMPAT(DT_INST_PARENT(n),		\
+					nxp_lp_flexcomm),		\
+		    (I2C_MCUX_LPI2C_LPFLEXCOMM_IRQ_FUNC(n)),		\
+		    (I2C_MCUX_LPI2C_MODULE_IRQ(n)))			\
 
 #define I2C_MCUX_LPI2C_INIT(n)						\
 	PINCTRL_DT_INST_DEFINE(n);					\
 									\
-	static void mcux_lpi2c_config_func_##n(const struct device *dev); \
+	static void mcux_lpi2c_config_func_##n(const struct device *dev)\
+	{								\
+		I2C_MCUX_LPI2C_IRQ_SETUP_FUNC(n);			\
+	}								\
 									\
 	static const struct mcux_lpi2c_config mcux_lpi2c_config_##n = {	\
 		DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)),	\
-		PARENT_DEV(n)						\
 		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),	\
 		.clock_subsys =						\
 			(clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\
@@ -616,12 +615,7 @@ static DEVICE_API(i2c, mcux_lpi2c_driver_api) = {
 	I2C_DEVICE_DT_INST_DEFINE(n, mcux_lpi2c_init, NULL,		\
 				&mcux_lpi2c_data_##n,			\
 				&mcux_lpi2c_config_##n, POST_KERNEL,	\
-				CONFIG_I2C_INIT_PRIORITY,			\
-				&mcux_lpi2c_driver_api);			\
-									\
-	static void mcux_lpi2c_config_func_##n(const struct device *dev) \
-	{								\
-		I2C_MCUX_LPI2C_MODULE_IRQ(n);				\
-	}
+				CONFIG_I2C_INIT_PRIORITY,		\
+				&mcux_lpi2c_driver_api);
 
 DT_INST_FOREACH_STATUS_OKAY(I2C_MCUX_LPI2C_INIT)
diff --git a/drivers/i2c/i2c_mcux_lpi2c_rtio.c b/drivers/i2c/i2c_mcux_lpi2c_rtio.c
index f267b7ada4c..a4ac9a2f20c 100644
--- a/drivers/i2c/i2c_mcux_lpi2c_rtio.c
+++ b/drivers/i2c/i2c_mcux_lpi2c_rtio.c
@@ -16,6 +16,9 @@
 #include <zephyr/kernel.h>
 #include <zephyr/irq.h>
 #include <fsl_lpi2c.h>
+#if CONFIG_NXP_LP_FLEXCOMM
+#include <zephyr/drivers/mfd/nxp_lp_flexcomm.h>
+#endif
 
 #include <zephyr/drivers/pinctrl.h>
 
@@ -280,7 +283,11 @@ static void mcux_lpi2c_isr(const struct device *dev)
 	struct mcux_lpi2c_data *data = dev->data;
 	LPI2C_Type *base = (LPI2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
 
+#if CONFIG_HAS_MCUX_FLEXCOMM
+	LPI2C_MasterTransferHandleIRQ(LPI2C_GetInstance(base), &data->handle);
+#else
 	LPI2C_MasterTransferHandleIRQ(base, &data->handle);
+#endif
 }
 
 static int mcux_lpi2c_init(const struct device *dev)
@@ -346,10 +353,41 @@ static DEVICE_API(i2c, mcux_lpi2c_driver_api) = {
 #define I2C_MCUX_LPI2C_SDA_INIT(n)
 #endif /* CONFIG_I2C_MCUX_LPI2C_BUS_RECOVERY */
 
+#define I2C_MCUX_LPI2C_MODULE_IRQ_CONNECT(n)				\
+	do {								\
+		IRQ_CONNECT(DT_INST_IRQN(n),				\
+			DT_INST_IRQ(n, priority),			\
+			mcux_lpi2c_isr,					\
+			DEVICE_DT_INST_GET(n), 0);			\
+		irq_enable(DT_INST_IRQN(n));				\
+	} while (false)
+
+#define I2C_MCUX_LPI2C_MODULE_IRQ(n)					\
+	IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0),				\
+		(I2C_MCUX_LPI2C_MODULE_IRQ_CONNECT(n)))
+
+/* When using LP Flexcomm driver, register the interrupt handler
+ * so we receive notification from the LP Flexcomm interrupt handler.
+ */
+#define I2C_MCUX_LPI2C_LPFLEXCOMM_IRQ_FUNC(n)				\
+	nxp_lp_flexcomm_setirqhandler(DEVICE_DT_GET(DT_INST_PARENT(n)), \
+					DEVICE_DT_INST_GET(n),		\
+					LP_FLEXCOMM_PERIPH_LPI2C,	\
+					mcux_lpi2c_isr)
+
+#define I2C_MCUX_LPI2C_IRQ_SETUP_FUNC(n)				\
+	COND_CODE_1(DT_NODE_HAS_COMPAT(DT_INST_PARENT(n),		\
+					nxp_lp_flexcomm),		\
+		    (I2C_MCUX_LPI2C_LPFLEXCOMM_IRQ_FUNC(n)),		\
+		    (I2C_MCUX_LPI2C_MODULE_IRQ(n)))
+
 #define I2C_MCUX_LPI2C_INIT(n)						\
 	PINCTRL_DT_INST_DEFINE(n);					\
 									\
-	static void mcux_lpi2c_config_func_##n(const struct device *dev); \
+	static void mcux_lpi2c_config_func_##n(const struct device *dev)\
+	{								\
+		I2C_MCUX_LPI2C_IRQ_SETUP_FUNC(n);			\
+	}								\
 									\
 	static const struct mcux_lpi2c_config mcux_lpi2c_config_##n = {	\
 		DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)),	\
@@ -378,16 +416,6 @@ static DEVICE_API(i2c, mcux_lpi2c_driver_api) = {
 				&mcux_lpi2c_data_##n,			\
 				&mcux_lpi2c_config_##n, POST_KERNEL,	\
 				CONFIG_I2C_INIT_PRIORITY,		\
-				&mcux_lpi2c_driver_api);		\
-									\
-	static void mcux_lpi2c_config_func_##n(const struct device *dev)\
-	{								\
-		IRQ_CONNECT(DT_INST_IRQN(n),				\
-				DT_INST_IRQ(n, priority),		\
-				mcux_lpi2c_isr,				\
-				DEVICE_DT_INST_GET(n), 0);		\
-									\
-		irq_enable(DT_INST_IRQN(n));				\
-	}
+				&mcux_lpi2c_driver_api);
 
 DT_INST_FOREACH_STATUS_OKAY(I2C_MCUX_LPI2C_INIT)
diff --git a/drivers/i2c/i2c_npcx_controller.c b/drivers/i2c/i2c_npcx_controller.c
index 8cffca7dfa5..ceded75ed16 100644
--- a/drivers/i2c/i2c_npcx_controller.c
+++ b/drivers/i2c/i2c_npcx_controller.c
@@ -73,6 +73,9 @@
 #include <zephyr/kernel.h>
 #include <zephyr/sys/atomic.h>
 #include <soc.h>
+#include "soc_miwu.h"
+#include "soc_pins.h"
+#include "soc_power.h"
 
 #include <zephyr/logging/log.h>
 #include <zephyr/irq.h>
@@ -105,6 +108,8 @@ LOG_MODULE_REGISTER(i2c_npcx, CONFIG_I2C_LOG_LEVEL);
 #define I2C_RECOVER_SCL_RETRY    10
 #define I2C_RECOVER_SDA_RETRY    3
 
+#define NPCX_SMBADDR_SAEN NPCX_SMBADDR1_SAEN /* All the SAEN in SMBADDR is bit_7 */
+
 /* Supported I2C bus frequency */
 enum npcx_i2c_freq {
 	NPCX_I2C_BUS_SPEED_100KHZ,
@@ -113,10 +118,22 @@ enum npcx_i2c_freq {
 };
 
 enum npcx_i2c_flag {
-	NPCX_I2C_FLAG_TARGET,
+	NPCX_I2C_FLAG_TARGET1,
+	NPCX_I2C_FLAG_TARGET2,
+	NPCX_I2C_FLAG_TARGET3,
+	NPCX_I2C_FLAG_TARGET4,
+	NPCX_I2C_FLAG_TARGET5,
+	NPCX_I2C_FLAG_TARGET6,
+	NPCX_I2C_FLAG_TARGET7,
+	NPCX_I2C_FLAG_TARGET8,
 	NPCX_I2C_FLAG_COUNT,
 };
 
+enum i2c_pm_policy_state_flag {
+	I2C_PM_POLICY_STATE_FLAG_TGT,
+	I2C_PM_POLICY_STATE_FLAG_COUNT,
+};
+
 /*
  * Internal SMBus Interface driver states values, which reflect events
  * which occurred on the bus
@@ -145,6 +162,11 @@ struct i2c_ctrl_config {
 	uintptr_t base; /* i2c controller base address */
 	struct npcx_clk_cfg clk_cfg; /* clock configuration */
 	uint8_t irq; /* i2c controller irq */
+#ifdef CONFIG_I2C_TARGET
+	/* i2c wake-up input source configuration */
+	const struct npcx_wui smb_wui;
+	bool wakeup_source;
+#endif /* CONFIG_I2C_TARGET */
 };
 
 /* Driver data */
@@ -155,16 +177,26 @@ struct i2c_ctrl_data {
 	enum npcx_i2c_oper_state oper_state; /* controller operation state */
 	int trans_err;  /* error code during transaction */
 	struct i2c_msg *msg; /* cache msg for transaction state machine */
+	struct i2c_msg *msg_head;
 	int is_write; /* direction of current msg */
 	uint8_t *ptr_msg; /* current msg pointer for FIFO read/write */
 	uint16_t addr; /* slave address of transaction */
+	uint8_t msg_max_num;
+	uint8_t msg_curr_idx;
 	uint8_t port; /* current port used the controller */
 	bool is_configured; /* is port configured? */
 	const struct npcx_i2c_timing_cfg *ptr_speed_confs;
 #ifdef CONFIG_I2C_TARGET
-	struct i2c_target_config *target_cfg;
-	atomic_t flags;
-#endif
+	struct i2c_target_config *target_cfg[NPCX_I2C_FLAG_COUNT];
+	uint8_t target_idx; /* current target_cfg index */
+	atomic_t registered_target_mask;
+	/* i2c wake-up callback configuration */
+	struct miwu_callback smb_wk_cb;
+#endif /* CONFIG_I2C_TARGET */
+
+#if defined(CONFIG_PM) && defined(CONFIG_I2C_TARGET)
+	ATOMIC_DEFINE(pm_policy_state_flag, I2C_PM_POLICY_STATE_FLAG_COUNT);
+#endif /* CONFIG_PM && CONFIG_I2C_TARGET */
 };
 
 /* Driver convenience defines */
@@ -184,6 +216,38 @@ static const struct npcx_i2c_timing_cfg npcx_20m_speed_confs[] = {
 	[NPCX_I2C_BUS_SPEED_1MHZ] = {.HLDT  = 7, .k1 = 16, .k2 = 10},
 };
 
+#if defined(CONFIG_PM) && defined(CONFIG_I2C_TARGET)
+static void i2c_npcx_pm_policy_state_lock_get(const struct device *dev,
+					      enum i2c_pm_policy_state_flag flag)
+{
+	const struct i2c_ctrl_config *const config = dev->config;
+	struct i2c_ctrl_data *const data = dev->data;
+
+	if (!config->wakeup_source) {
+		return;
+	}
+
+	if (atomic_test_and_set_bit(data->pm_policy_state_flag, flag) == 0) {
+		pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
+	}
+}
+
+static void i2c_npcx_pm_policy_state_lock_put(const struct device *dev,
+					      enum i2c_pm_policy_state_flag flag)
+{
+	const struct i2c_ctrl_config *const config = dev->config;
+	struct i2c_ctrl_data *const data = dev->data;
+
+	if (!config->wakeup_source) {
+		return;
+	}
+
+	if (atomic_test_and_clear_bit(data->pm_policy_state_flag, flag) == 1) {
+		pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
+	}
+}
+#endif /* CONFIG_PM && CONFIG_I2C_TARGET */
+
 /* I2C controller inline functions access shared registers */
 static inline void i2c_ctrl_start(const struct device *dev)
 {
@@ -588,6 +652,24 @@ static void i2c_ctrl_handle_write_int_event(const struct device *dev)
 			/* Wait for STOP completed */
 			data->oper_state = NPCX_I2C_WAIT_STOP;
 		} else {
+			uint8_t next_msg_idx = data->msg_curr_idx + 1;
+
+			if (next_msg_idx < data->msg_max_num) {
+				struct i2c_msg *msg;
+
+				data->msg_curr_idx = next_msg_idx;
+				msg = data->msg_head + next_msg_idx;
+				data->msg = msg;
+				data->ptr_msg = msg->buf;
+				if ((msg->flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
+					data->oper_state = NPCX_I2C_WRITE_FIFO;
+				} else {
+					data->is_write = 0;
+					data->oper_state = NPCX_I2C_WAIT_RESTART;
+					i2c_ctrl_start(dev);
+				}
+				return;
+			}
 			/* Disable interrupt and handle next message */
 			i2c_ctrl_irq_enable(dev, 0);
 		}
@@ -651,6 +733,27 @@ static void i2c_ctrl_handle_read_int_event(const struct device *dev)
 			/* Release bus */
 			i2c_ctrl_hold_bus(dev, 0);
 			return;
+		} else if ((data->msg->flags & I2C_MSG_STOP) == 0) {
+			uint8_t next_msg_idx = data->msg_curr_idx + 1;
+
+			if (next_msg_idx < data->msg_max_num) {
+				struct i2c_msg *msg;
+
+				msg = data->msg_head + next_msg_idx;
+				if ((msg->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
+
+					data->msg_curr_idx = next_msg_idx;
+					data->msg = msg;
+					data->ptr_msg = msg->buf;
+
+					/* Setup threshold of RX FIFO first */
+					i2c_ctrl_fifo_rx_setup_threshold_nack(
+						dev, msg->len, (msg->flags & I2C_MSG_STOP) != 0);
+					/* Release bus */
+					i2c_ctrl_hold_bus(dev, 0);
+					return;
+				}
+			}
 		}
 	}
 
@@ -754,7 +857,7 @@ static void i2c_ctrl_target_isr(const struct device *dev, uint8_t status)
 {
 	struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
 	struct i2c_ctrl_data *const data = dev->data;
-	const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks;
+	const struct i2c_target_callbacks *target_cb = NULL;
 	uint8_t val = 0;
 
 	/* A 'Bus Error' has been identified */
@@ -762,9 +865,11 @@ static void i2c_ctrl_target_isr(const struct device *dev, uint8_t status)
 		/* Clear BER Bit */
 		inst->SMBST = BIT(NPCX_SMBST_BER);
 
+		target_cb = data->target_cfg[data->target_idx]->callbacks;
+
 		/* Notify upper layer the end of transaction */
-		if (target_cb->stop) {
-			target_cb->stop(data->target_cfg);
+		if ((target_cb != NULL) && target_cb->stop) {
+			target_cb->stop(data->target_cfg[data->target_idx]);
 		}
 
 		/* Reset i2c module in target mode */
@@ -779,6 +884,10 @@ static void i2c_ctrl_target_isr(const struct device *dev, uint8_t status)
 		/* End of transaction */
 		data->oper_state = NPCX_I2C_IDLE;
 
+#ifdef CONFIG_PM
+		i2c_npcx_pm_policy_state_lock_put(dev, I2C_PM_POLICY_STATE_FLAG_TGT);
+#endif /* CONFIG_PM */
+
 		LOG_DBG("target: Bus error on port%02x!", data->port);
 		return;
 	}
@@ -790,9 +899,14 @@ static void i2c_ctrl_target_isr(const struct device *dev, uint8_t status)
 		/* End of transaction */
 		data->oper_state = NPCX_I2C_IDLE;
 		/* Notify upper layer a STOP condition received */
-		if (target_cb->stop) {
-			target_cb->stop(data->target_cfg);
+		target_cb = data->target_cfg[data->target_idx]->callbacks;
+		if ((target_cb != NULL) && target_cb->stop) {
+			target_cb->stop(data->target_cfg[data->target_idx]);
 		}
+
+#ifdef CONFIG_PM
+		i2c_npcx_pm_policy_state_lock_put(dev, I2C_PM_POLICY_STATE_FLAG_TGT);
+#endif /* CONFIG_PM */
 		return;
 	}
 
@@ -809,21 +923,36 @@ static void i2c_ctrl_target_isr(const struct device *dev, uint8_t status)
 		/* Clear NMATCH Bit */
 		inst->SMBST = BIT(NPCX_SMBST_NMATCH);
 
+		/* Check MATCH1F ~ MATCH7F */
+		if (inst->SMBCST2 & ~BIT(NPCX_SMBCST2_INTSTS)) {
+			for (uint8_t addr_idx = NPCX_I2C_FLAG_TARGET1;
+			     addr_idx <= NPCX_I2C_FLAG_TARGET7; addr_idx++) {
+				if (inst->SMBCST2 & BIT(addr_idx)) {
+					data->target_idx = addr_idx;
+					break;
+				}
+			}
+		} else if (inst->SMBCST3 & BIT(NPCX_SMBCST3_MATCHA8F)) {
+			data->target_idx = NPCX_I2C_FLAG_TARGET8;
+		}
+
+		target_cb = data->target_cfg[data->target_idx]->callbacks;
+
 		/* Distinguish the direction of i2c target mode by reading XMIT bit */
 		if (IS_BIT_SET(inst->SMBST, NPCX_SMBST_XMIT)) {
 			/* Start transmitting data in i2c target mode */
 			data->oper_state = NPCX_I2C_WRITE_FIFO;
 			/* Write first requested byte after repeated start */
-			if (target_cb->read_requested) {
-				target_cb->read_requested(data->target_cfg, &val);
+			if ((target_cb != NULL) && target_cb->read_requested) {
+				target_cb->read_requested(data->target_cfg[data->target_idx], &val);
 			}
 			inst->SMBSDA = val;
 		} else {
 			/* Start receiving data in i2c target mode */
 			data->oper_state = NPCX_I2C_READ_FIFO;
 
-			if (target_cb->write_requested) {
-				target_cb->write_requested(data->target_cfg);
+			if ((target_cb != NULL) && target_cb->write_requested) {
+				target_cb->write_requested(data->target_cfg[data->target_idx]);
 			}
 		}
 		return;
@@ -831,17 +960,19 @@ static void i2c_ctrl_target_isr(const struct device *dev, uint8_t status)
 
 	/* Tx byte empty or Rx byte full has occurred */
 	if (IS_BIT_SET(status, NPCX_SMBST_SDAST)) {
+		target_cb = data->target_cfg[data->target_idx]->callbacks;
+
 		if (data->oper_state == NPCX_I2C_WRITE_FIFO) {
 			/* Notify upper layer one byte will be transmitted */
-			if (target_cb->read_processed) {
-				target_cb->read_processed(data->target_cfg, &val);
+			if ((target_cb != NULL) && target_cb->read_processed) {
+				target_cb->read_processed(data->target_cfg[data->target_idx], &val);
 			}
 			inst->SMBSDA = val;
 		} else if (data->oper_state == NPCX_I2C_READ_FIFO) {
-			if (target_cb->write_received) {
+			if ((target_cb != NULL) && target_cb->write_received) {
 				val = inst->SMBSDA;
 				/* Notify upper layer one byte received */
-				target_cb->write_received(data->target_cfg, val);
+				target_cb->write_received(data->target_cfg[data->target_idx], val);
 			}
 		} else {
 			LOG_ERR("Unexpected oper state %d on i2c target port%02x!",
@@ -857,7 +988,7 @@ static void i2c_ctrl_target_isr(const struct device *dev, uint8_t status)
 			status, data->port);
 	}
 }
-#endif
+#endif /* CONFIG_I2C_TARGET */
 
 /* I2C controller isr function */
 static void i2c_ctrl_isr(const struct device *dev)
@@ -870,11 +1001,11 @@ static void i2c_ctrl_isr(const struct device *dev)
 	LOG_DBG("status: %02x, %d", status, data->oper_state);
 
 #ifdef CONFIG_I2C_TARGET
-	if (atomic_test_bit(&data->flags, NPCX_I2C_FLAG_TARGET)) {
+	if (atomic_get(&data->registered_target_mask) != (atomic_val_t) 0) {
 		i2c_ctrl_target_isr(dev, status);
 		return;
 	}
-#endif
+#endif /* CONFIG_I2C_TARGET */
 
 	/* A 'Bus Error' has been identified */
 	if (IS_BIT_SET(status, NPCX_SMBST_BER)) {
@@ -1069,29 +1200,86 @@ int npcx_i2c_ctrl_recover_bus(const struct device *dev)
 }
 
 #ifdef CONFIG_I2C_TARGET
+static volatile uint8_t *npcx_i2c_ctrl_target_get_reg_smbaddr(const struct device *i2c_dev,
+							      int index)
+{
+	struct smb_reg *const inst = HAL_I2C_INSTANCE(i2c_dev);
+
+	switch (index) {
+	case 0:
+		return &inst->SMBADDR1;
+	case 1:
+		return &inst->SMBADDR2;
+	case 2:
+		return &inst->SMBADDR3;
+	case 3:
+		return &inst->SMBADDR4;
+	case 4:
+		return &inst->SMBADDR5;
+	case 5:
+		return &inst->SMBADDR6;
+	case 6:
+		return &inst->SMBADDR7;
+	case 7:
+		return &inst->SMBADDR8;
+	default:
+		LOG_ERR("Invalid SMBADDR index: %d", index);
+		return NULL;
+	}
+}
+
 int npcx_i2c_ctrl_target_register(const struct device *i2c_dev,
 				 struct i2c_target_config *target_cfg, uint8_t port)
 {
 	struct smb_reg *const inst = HAL_I2C_INSTANCE(i2c_dev);
+	const struct i2c_ctrl_config *const config = i2c_dev->config;
 	struct i2c_ctrl_data *const data = i2c_dev->data;
 	int idx_ctrl = (port & 0xF0) >> 4;
 	int idx_port = (port & 0x0F);
-	uint8_t addr = BIT(NPCX_SMBADDR1_SAEN) | target_cfg->address;
-
-	/* I2c module has been configured to target mode */
-	if (atomic_test_and_set_bit(&data->flags, NPCX_I2C_FLAG_TARGET)) {
-		return -EBUSY;
-	}
+	int avail_addr_slot;
+	volatile uint8_t *reg_smbaddr;
+	uint8_t smbaddr_val = BIT(NPCX_SMBADDR_SAEN) | target_cfg->address;
+	uint32_t i2c_tgt_mask = (uint32_t)atomic_get(&data->registered_target_mask);
+	int addr_idx;
 
 	/* A transiaction is ongoing */
 	if (data->oper_state != NPCX_I2C_IDLE) {
-		atomic_clear_bit(&data->flags, NPCX_I2C_FLAG_TARGET);
 		return -EBUSY;
 	}
 
-	data->target_cfg = target_cfg;
+	/* Find valid smbaddr location */
+	avail_addr_slot = find_lsb_set(~i2c_tgt_mask) - 1;
+	if (avail_addr_slot == -1 || avail_addr_slot >= NPCX_I2C_FLAG_COUNT) {
+		LOG_ERR("No available smbaddr register, smbaddr_idx: %d", avail_addr_slot);
+		return -ENOSPC;
+	}
+
+	/* Check if the address is duplicated */
+	while (i2c_tgt_mask) {
+		addr_idx = find_lsb_set(i2c_tgt_mask) - 1;
+		reg_smbaddr = npcx_i2c_ctrl_target_get_reg_smbaddr(i2c_dev, addr_idx);
+
+		/* Check if the address is duplicated */
+		if (*reg_smbaddr == smbaddr_val) {
+			LOG_ERR("Address %#x is already set", target_cfg->address);
+			return -EINVAL;
+		}
+
+		i2c_tgt_mask &= ~BIT(addr_idx);
+	}
+
+	/* Mark the selected address slot */
+	atomic_set_bit(&data->registered_target_mask, avail_addr_slot);
 
 	i2c_ctrl_irq_enable(i2c_dev, 0);
+
+	data->port = port; /* Update the I2C port index */
+
+	/* Config new address */
+	reg_smbaddr = npcx_i2c_ctrl_target_get_reg_smbaddr(i2c_dev, avail_addr_slot);
+	*reg_smbaddr = smbaddr_val; /* Set address register */
+	data->target_cfg[avail_addr_slot] = target_cfg; /* Set target config */
+
 	/* Switch correct port for i2c controller first */
 	npcx_pinctrl_i2c_port_sel(idx_ctrl, idx_port);
 	/* Reset I2C module */
@@ -1101,23 +1289,41 @@ int npcx_i2c_ctrl_target_register(const struct device *i2c_dev,
 	/* Select normal bank and single byte mode for i2c target mode */
 	i2c_ctrl_bank_sel(i2c_dev, NPCX_I2C_BANK_NORMAL);
 	inst->SMBFIF_CTL &= ~BIT(NPCX_SMBFIF_CTL_FIFO_EN);
-	inst->SMBADDR1 = addr; /* Enable target mode and configure its address */
 
 	/* Reconfigure SMBCTL1 */
 	inst->SMBCTL1 |= BIT(NPCX_SMBCTL1_NMINTE) | BIT(NPCX_SMBCTL1_INTEN);
+
+	/* Enable irq of smb wake-up event */
+	if (IS_ENABLED(CONFIG_PM) && config->wakeup_source) {
+
+		/* Enable SMB wake up detection */
+		npcx_i2c_target_start_wk_enable(idx_ctrl, true);
+		/* Enable start detect in IDLE */
+		inst->SMBCTL3 |= BIT(NPCX_SMBCTL3_IDL_START);
+		/* Enable SMB's MIWU interrupts */
+		npcx_miwu_irq_enable(&config->smb_wui);
+	}
+
 	i2c_ctrl_irq_enable(i2c_dev, 1);
 
 	return 0;
 }
 
 int npcx_i2c_ctrl_target_unregister(const struct device *i2c_dev,
-				   struct i2c_target_config *target_cfg)
+				   struct i2c_target_config *target_cfg, uint8_t port)
 {
 	struct smb_reg *const inst = HAL_I2C_INSTANCE(i2c_dev);
+	const struct i2c_ctrl_config *const config = i2c_dev->config;
 	struct i2c_ctrl_data *const data = i2c_dev->data;
+	int idx_ctrl = (port & 0xF0) >> 4;
+	int cur_addr_slot;
+	volatile uint8_t *reg_smbaddr;
+	uint8_t smbaddr_val = BIT(NPCX_SMBADDR_SAEN) | target_cfg->address;
+	uint32_t i2c_tgt_mask = (uint32_t)atomic_get(&data->registered_target_mask);
 
 	/* No I2c module has been configured to target mode */
-	if (!atomic_test_bit(&data->flags, NPCX_I2C_FLAG_TARGET)) {
+	if (atomic_get(&data->registered_target_mask) == (atomic_val_t) 0) {
+		LOG_ERR("No available target to ungister");
 		return -EINVAL;
 	}
 
@@ -1125,42 +1331,103 @@ int npcx_i2c_ctrl_target_unregister(const struct device *i2c_dev,
 	if (data->oper_state != NPCX_I2C_IDLE) {
 		return -EBUSY;
 	}
-	data->target_cfg = NULL;
 
-	i2c_ctrl_irq_enable(i2c_dev, 0);
-	/* Reset I2C module */
-	inst->SMBCTL2 &= ~BIT(NPCX_SMBCTL2_ENABLE);
-	inst->SMBCTL2 |= BIT(NPCX_SMBCTL2_ENABLE);
+	/* Find target address in smbaddr */
+	while (i2c_tgt_mask) {
+		cur_addr_slot = find_lsb_set(i2c_tgt_mask) - 1;
+		reg_smbaddr = npcx_i2c_ctrl_target_get_reg_smbaddr(i2c_dev, cur_addr_slot);
+		if (reg_smbaddr == NULL) {
+			LOG_ERR("Invalid smbaddr register");
+			return -EINVAL;
+		}
 
-	inst->SMBADDR1 = 0; /* Disable target mode and clear address setting */
-	/* Enable FIFO mode and select to FIFO bank for i2c controller mode */
-	inst->SMBFIF_CTL |= BIT(NPCX_SMBFIF_CTL_FIFO_EN);
-	i2c_ctrl_bank_sel(i2c_dev, NPCX_I2C_BANK_FIFO);
+		/* Target address found */
+		if (*reg_smbaddr == smbaddr_val) {
+			break;
+		}
 
-	/* Reconfigure SMBCTL1 */
-	inst->SMBCTL1 |= BIT(NPCX_SMBCTL1_NMINTE) | BIT(NPCX_SMBCTL1_INTEN);
-	i2c_ctrl_irq_enable(i2c_dev, 1);
+		i2c_tgt_mask &= ~BIT(cur_addr_slot);
+	}
+
+	/* Input addrss is not in the smbaddr */
+	if (i2c_tgt_mask == 0 || reg_smbaddr == NULL) {
+		LOG_ERR("Address %#x is not found", target_cfg->address);
+		return -EINVAL;
+	}
+
+	i2c_ctrl_irq_enable(i2c_dev, 0);
+
+	*reg_smbaddr = 0; /* Disable target mode and clear address setting */
+	data->target_cfg[cur_addr_slot] = NULL; /* Clear target config */
 
 	/* Mark it as controller mode */
-	atomic_clear_bit(&data->flags, NPCX_I2C_FLAG_TARGET);
+	atomic_clear_bit(&data->registered_target_mask, cur_addr_slot);
+
+	/* Switch I2C to controller mode if no any other valid address in smbaddr */
+	if (atomic_get(&data->registered_target_mask) == (atomic_val_t) 0) {
+		/* Reset I2C module */
+		inst->SMBCTL2 &= ~BIT(NPCX_SMBCTL2_ENABLE);
+		inst->SMBCTL2 |= BIT(NPCX_SMBCTL2_ENABLE);
+
+		/* Enable FIFO mode and select to FIFO bank for i2c controller mode */
+		inst->SMBFIF_CTL |= BIT(NPCX_SMBFIF_CTL_FIFO_EN);
+		i2c_ctrl_bank_sel(i2c_dev, NPCX_I2C_BANK_FIFO);
+
+		/* Reconfigure SMBCTL1 */
+		inst->SMBCTL1 |= BIT(NPCX_SMBCTL1_NMINTE) | BIT(NPCX_SMBCTL1_INTEN);
+
+		/* Disable irq of smb wake-up event */
+		if (IS_ENABLED(CONFIG_PM)) {
+			/* Disable SMB wake up detection */
+			npcx_i2c_target_start_wk_enable(idx_ctrl, false);
+			/* Disable start detect in IDLE */
+			inst->SMBCTL3 &= ~BIT(NPCX_SMBCTL3_IDL_START);
+			/* Disable SMB's MIWU interrupts */
+			npcx_miwu_irq_disable(&config->smb_wui);
+		}
+	}
+
+	i2c_ctrl_irq_enable(i2c_dev, 1);
 
 	return 0;
 }
-#endif
+
+static void i2c_target_wk_isr(const struct device *dev, struct npcx_wui *wui)
+{
+	struct smb_reg *const inst = HAL_I2C_INSTANCE(dev);
+
+	/* Clear wake up detection event status */
+	npcx_i2c_target_clear_detection_event();
+
+	/* Reconfigure SMBCTL1 */
+	inst->SMBCTL1 |= BIT(NPCX_SMBCTL1_NMINTE) | BIT(NPCX_SMBCTL1_INTEN);
+
+	/*
+	 * Suspend-to-idle stops SMB module clocks (derived from APB2/APB3), which must remain
+	 * active during a transaction.
+	 *
+	 * This also prevent Sr set pm_policy_state_lock_get() twice.
+	 * Otherwise, it will cause I2C cannot switch to deep sleep state for the next time.
+	 */
+#ifdef CONFIG_PM
+	i2c_npcx_pm_policy_state_lock_get(dev, I2C_PM_POLICY_STATE_FLAG_TGT);
+#endif /* CONFIG_PM */
+}
+#endif /* CONFIG_I2C_TARGET */
 
 int npcx_i2c_ctrl_transfer(const struct device *i2c_dev, struct i2c_msg *msgs,
 			      uint8_t num_msgs, uint16_t addr, int port)
 {
 	struct i2c_ctrl_data *const data = i2c_dev->data;
 	int ret = 0;
-	uint8_t i;
+	struct i2c_msg *msg = msgs;
 
 #ifdef CONFIG_I2C_TARGET
 	/* I2c module has been configured to target mode */
-	if (atomic_test_bit(&data->flags, NPCX_I2C_FLAG_TARGET)) {
+	if (atomic_get(&data->registered_target_mask) != (atomic_val_t) 0) {
 		return -EBUSY;
 	}
-#endif
+#endif /* CONFIG_I2C_TARGET */
 
 	/*
 	 * suspend-to-idle stops SMB module clocks (derived from APB2/APB3), which must remain
@@ -1192,6 +1459,10 @@ int npcx_i2c_ctrl_transfer(const struct device *i2c_dev, struct i2c_msg *msgs,
 	data->trans_err = 0;
 	data->addr = addr;
 
+	data->msg_head = msgs;
+	data->msg_max_num = num_msgs;
+	data->msg_curr_idx = 0;
+
 	/*
 	 * Reset i2c event-completed semaphore before starting transactions.
 	 * Some interrupt events such as BUS_ERROR might change its counter
@@ -1199,18 +1470,10 @@ int npcx_i2c_ctrl_transfer(const struct device *i2c_dev, struct i2c_msg *msgs,
 	 */
 	k_sem_reset(&data->sync_sem);
 
-	for (i = 0U; i < num_msgs; i++) {
-		struct i2c_msg *msg = msgs + i;
-
-		/* Handle write transaction */
-		if ((msg->flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
-			ret = i2c_ctrl_proc_write_msg(i2c_dev, msg);
-		} else {/* Handle read transaction */
-			ret = i2c_ctrl_proc_read_msg(i2c_dev, msg);
-		}
-		if (ret < 0) {
-			break;
-		}
+	if ((msg->flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
+		ret = i2c_ctrl_proc_write_msg(i2c_dev, msg);
+	} else { /* Handle read transaction */
+		ret = i2c_ctrl_proc_read_msg(i2c_dev, msg);
 	}
 
 	/* Check STOP completed? */
@@ -1285,6 +1548,21 @@ static int i2c_ctrl_init(const struct device *dev)
 	/* Initialize i2c module */
 	i2c_ctrl_init_module(dev);
 
+#ifdef CONFIG_I2C_TARGET
+	if (IS_ENABLED(CONFIG_PM) && config->wakeup_source) {
+		/* Initialize a miwu device input and its callback function */
+		npcx_miwu_init_dev_callback(&data->smb_wk_cb, &config->smb_wui,
+					    i2c_target_wk_isr, dev);
+		npcx_miwu_manage_callback(&data->smb_wk_cb, true);
+		/*
+		 * Configure Start condition wake-up configuration of SMB
+		 * controller.
+		 */
+		npcx_miwu_interrupt_configure(&config->smb_wui, NPCX_MIWU_MODE_EDGE,
+					      NPCX_MIWU_TRIG_HIGH);
+	}
+#endif /* CONFIG_I2C_TARGET */
+
 	/* initialize mutex and semaphore for i2c/smb controller */
 	k_sem_init(&data->lock_sem, 1, 1);
 	k_sem_init(&data->sync_sem, 0, K_SEM_MAX_LIMIT);
@@ -1316,24 +1594,28 @@ static int i2c_ctrl_init(const struct device *dev)
 	}
 
 
-#define NPCX_I2C_CTRL_INIT(inst)                                               \
-	NPCX_I2C_CTRL_INIT_FUNC_DECL(inst);                                    \
-									       \
-	static const struct i2c_ctrl_config i2c_ctrl_cfg_##inst = {            \
-		.base = DT_INST_REG_ADDR(inst),                                \
-		.irq = DT_INST_IRQN(inst),                                     \
-		.clk_cfg = NPCX_DT_CLK_CFG_ITEM(inst),                         \
-	};                                                                     \
-									       \
-	static struct i2c_ctrl_data i2c_ctrl_data_##inst;                      \
-									       \
-	DEVICE_DT_INST_DEFINE(inst,                                            \
-			    NPCX_I2C_CTRL_INIT_FUNC(inst),                     \
-			    NULL,                                              \
-			    &i2c_ctrl_data_##inst, &i2c_ctrl_cfg_##inst,       \
-			    PRE_KERNEL_1, CONFIG_I2C_INIT_PRIORITY,            \
-			    NULL);                                             \
-									       \
+#define NPCX_I2C_CTRL_INIT(inst)                                                                   \
+	NPCX_I2C_CTRL_INIT_FUNC_DECL(inst);                                                        \
+									                           \
+	static const struct i2c_ctrl_config i2c_ctrl_cfg_##inst = {                                \
+		.base = DT_INST_REG_ADDR(inst),                                                    \
+		.irq = DT_INST_IRQN(inst),                                                         \
+		.clk_cfg = NPCX_DT_CLK_CFG_ITEM(inst),                                             \
+		IF_ENABLED(CONFIG_I2C_TARGET, (                                                    \
+			.smb_wui = NPCX_DT_WUI_ITEM_BY_NAME(inst, smb_wui),                        \
+			.wakeup_source = DT_INST_PROP_OR(inst, wakeup_source, 0)                   \
+		))                                                                                 \
+	};                                                                                         \
+									                           \
+	static struct i2c_ctrl_data i2c_ctrl_data_##inst;                                          \
+									                           \
+	DEVICE_DT_INST_DEFINE(inst,                                                                \
+			    NPCX_I2C_CTRL_INIT_FUNC(inst),                                         \
+			    NULL,                                                                  \
+			    &i2c_ctrl_data_##inst, &i2c_ctrl_cfg_##inst,                           \
+			    PRE_KERNEL_1, CONFIG_I2C_INIT_PRIORITY,                                \
+			    NULL);                                                                 \
+									                           \
 	NPCX_I2C_CTRL_INIT_FUNC_IMPL(inst)
 
 DT_INST_FOREACH_STATUS_OKAY(NPCX_I2C_CTRL_INIT)
diff --git a/drivers/i2c/i2c_npcx_controller.h b/drivers/i2c/i2c_npcx_controller.h
index 6155f1a1499..dc80aba386f 100644
--- a/drivers/i2c/i2c_npcx_controller.h
+++ b/drivers/i2c/i2c_npcx_controller.h
@@ -98,13 +98,14 @@ int npcx_i2c_ctrl_target_register(const struct device *i2c_dev,
  *
  * @param i2c_dev Pointer to the device structure for i2c controller instance.
  * @param target_cfg Config struct used by the i2c target driver
+ * @param port Port index of selected i2c port.
  *
  * @retval 0 Is successful
  * @retval -EBUSY If i2c transaction is proceeding.
  * @retval -EINVAL If parameters are invalid
  */
 int npcx_i2c_ctrl_target_unregister(const struct device *i2c_dev,
-				   struct i2c_target_config *target_cfg);
+				    struct i2c_target_config *target_cfg, uint8_t port);
 
 #ifdef __cplusplus
 }
diff --git a/drivers/i2c/i2c_npcx_port.c b/drivers/i2c/i2c_npcx_port.c
index 33f77e62d62..61f65cd6683 100644
--- a/drivers/i2c/i2c_npcx_port.c
+++ b/drivers/i2c/i2c_npcx_port.c
@@ -147,6 +147,7 @@ static int i2c_npcx_port_recover_bus(const struct device *dev)
 static int i2c_npcx_target_register(const struct device *dev,
 				  struct i2c_target_config *target_cfg)
 {
+	int ret;
 	const struct i2c_npcx_port_config *const config = dev->config;
 
 	if (!target_cfg) {
@@ -158,12 +159,21 @@ static int i2c_npcx_target_register(const struct device *dev,
 		return -EIO;
 	}
 
-	return npcx_i2c_ctrl_target_register(config->i2c_ctrl, target_cfg, config->port);
+	/* Lock mutex of i2c/smb controller */
+	npcx_i2c_ctrl_mutex_lock(config->i2c_ctrl);
+
+	ret = npcx_i2c_ctrl_target_register(config->i2c_ctrl, target_cfg, config->port);
+
+	/* Unlock mutex of i2c/smb controller */
+	npcx_i2c_ctrl_mutex_unlock(config->i2c_ctrl);
+
+	return ret;
 }
 
 static int i2c_npcx_target_unregister(const struct device *dev,
 				     struct i2c_target_config *target_cfg)
 {
+	int ret;
 	const struct i2c_npcx_port_config *const config = dev->config;
 
 	if (config->i2c_ctrl == NULL) {
@@ -171,7 +181,15 @@ static int i2c_npcx_target_unregister(const struct device *dev,
 		return -EIO;
 	}
 
-	return npcx_i2c_ctrl_target_unregister(config->i2c_ctrl, target_cfg);
+	/* Lock mutex of i2c/smb controller */
+	npcx_i2c_ctrl_mutex_lock(config->i2c_ctrl);
+
+	ret = npcx_i2c_ctrl_target_unregister(config->i2c_ctrl, target_cfg, config->port);
+
+	/* Unlock mutex of i2c/smb controller */
+	npcx_i2c_ctrl_mutex_unlock(config->i2c_ctrl);
+
+	return ret;
 }
 #endif
 
diff --git a/drivers/i2c/i2c_nrfx_twi_rtio.c b/drivers/i2c/i2c_nrfx_twi_rtio.c
index 9dc1b54914c..8775522b66a 100644
--- a/drivers/i2c/i2c_nrfx_twi_rtio.c
+++ b/drivers/i2c/i2c_nrfx_twi_rtio.c
@@ -41,6 +41,8 @@ static bool i2c_nrfx_twi_rtio_msg_start(const struct device *dev, uint8_t flags,
 	struct i2c_nrfx_twi_rtio_data *const dev_data = dev->data;
 	struct i2c_rtio *ctx = dev_data->ctx;
 	int ret = 0;
+	bool more_msgs = (rtio_txn_next(ctx->txn_curr) != NULL) &&
+			 ((ctx->txn_curr->next->sqe.iodev_flags & RTIO_IODEV_I2C_RESTART) == 0);
 
 	/** Enabling while already enabled ends up in a failed assertion: skip it. */
 	if (!dev_data->twi_enabled) {
@@ -48,7 +50,7 @@ static bool i2c_nrfx_twi_rtio_msg_start(const struct device *dev, uint8_t flags,
 		dev_data->twi_enabled = true;
 	}
 
-	ret = i2c_nrfx_twi_msg_transfer(dev, flags, buf, buf_len, i2c_addr, false);
+	ret = i2c_nrfx_twi_msg_transfer(dev, flags, buf, buf_len, i2c_addr, more_msgs);
 	if (ret != 0) {
 		nrfx_twi_disable(&config->twi);
 		dev_data->twi_enabled = false;
@@ -80,7 +82,11 @@ static bool i2c_nrfx_twi_rtio_start(const struct device *dev)
 						   sqe->tx.buf_len, dt_spec->addr);
 	case RTIO_OP_I2C_CONFIGURE:
 		(void)i2c_nrfx_twi_configure(dev, sqe->i2c_config);
-		return false;
+		/** This request will not generate an event therefore, this
+		 * code immediately submits a CQE in order to unblock
+		 * i2c_rtio_configure.
+		 */
+		return i2c_rtio_complete(ctx, 0);
 	case RTIO_OP_I2C_RECOVER:
 		(void)i2c_nrfx_twi_recover_bus(dev);
 		return false;
diff --git a/drivers/i2c/i2c_nrfx_twim_rtio.c b/drivers/i2c/i2c_nrfx_twim_rtio.c
index 8b5f2c625f8..d2cf14e1a05 100644
--- a/drivers/i2c/i2c_nrfx_twim_rtio.c
+++ b/drivers/i2c/i2c_nrfx_twim_rtio.c
@@ -100,7 +100,11 @@ static bool i2c_nrfx_twim_rtio_start(const struct device *dev)
 						    dt_spec->addr);
 	case RTIO_OP_I2C_CONFIGURE:
 		(void)i2c_nrfx_twim_configure(dev, sqe->i2c_config);
-		return false;
+		/** This request will not generate an event therefore, this
+		 * code immediately submits a CQE in order to unblock
+		 * i2c_rtio_configure.
+		 */
+		return i2c_rtio_complete(ctx, 0);
 	case RTIO_OP_I2C_RECOVER:
 		(void)i2c_nrfx_twim_recover_bus(dev);
 		return false;
diff --git a/drivers/i2c/i2c_nxp_ii2c.c b/drivers/i2c/i2c_nxp_ii2c.c
new file mode 100644
index 00000000000..bfe6cf1467e
--- /dev/null
+++ b/drivers/i2c/i2c_nxp_ii2c.c
@@ -0,0 +1,414 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_ii2c
+
+#include <errno.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/kernel.h>
+#include <fsl_i2c.h>
+#include <fsl_clock.h>
+#include <zephyr/sys/util.h>
+
+#include <zephyr/drivers/pinctrl.h>
+
+#include <zephyr/logging/log.h>
+#include <zephyr/irq.h>
+LOG_MODULE_REGISTER(i2c_nxp_ii2c);
+
+#include "i2c-priv.h"
+
+#define DEV_CFG(_dev) ((const struct nxp_ii2c_config *)(_dev)->config)
+#define DEV_DATA(_dev) ((struct nxp_ii2c_data *)(_dev)->data)
+
+struct nxp_ii2c_config {
+	DEVICE_MMIO_NAMED_ROM(reg_base);
+	const struct device *clock_dev;
+	clock_control_subsys_t clock_subsys;
+	void (*irq_config_func)(const struct device *dev);
+	uint32_t bitrate;
+	const struct pinctrl_dev_config *pincfg;
+};
+
+struct nxp_ii2c_data {
+	DEVICE_MMIO_NAMED_RAM(reg_base);
+	i2c_master_handle_t handle;
+	struct k_sem lock;
+	struct k_sem device_sync_sem;
+	status_t callback_status;
+#ifdef CONFIG_I2C_CALLBACK
+	uint16_t addr;
+	uint32_t msg;
+	struct i2c_msg *msgs;
+	uint32_t num_msgs;
+	i2c_callback_t cb;
+	void *userdata;
+#endif /* CONFIG_I2C_CALLBACK */
+};
+
+static I2C_Type *get_base(const struct device *dev)
+{
+	return (I2C_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
+}
+
+static int nxp_ii2c_configure(const struct device *dev,
+			      uint32_t dev_config_raw)
+{
+	I2C_Type *base = get_base(dev);
+	struct nxp_ii2c_data *data = dev->data;
+	const struct nxp_ii2c_config *config = dev->config;
+	uint32_t clock_freq;
+	uint32_t baudrate;
+
+	if (!(I2C_MODE_CONTROLLER & dev_config_raw)) {
+		return -EINVAL;
+	}
+
+	if (I2C_ADDR_10_BITS & dev_config_raw) {
+		return -EINVAL;
+	}
+
+	switch (I2C_SPEED_GET(dev_config_raw)) {
+	case I2C_SPEED_STANDARD:
+		baudrate = KHZ(100);
+		break;
+	case I2C_SPEED_FAST:
+		baudrate = KHZ(400);
+		break;
+	case I2C_SPEED_FAST_PLUS:
+		baudrate = MHZ(1);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
+				   &clock_freq)) {
+		return -EINVAL;
+	}
+
+	k_sem_take(&data->lock, K_FOREVER);
+	I2C_MasterSetBaudRate(base, baudrate, clock_freq);
+	k_sem_give(&data->lock);
+
+	return 0;
+}
+
+#ifdef CONFIG_I2C_CALLBACK
+
+static void nxp_ii2c_async_done(const struct device *dev, struct nxp_ii2c_data *data, int result);
+static void nxp_ii2c_async_iter(const struct device *dev);
+
+#endif
+
+static void nxp_ii2c_master_transfer_callback(I2C_Type *base,
+					      i2c_master_handle_t *handle,
+					      status_t status, void *userdata)
+{
+
+	ARG_UNUSED(handle);
+	ARG_UNUSED(base);
+
+	struct device *dev = userdata;
+	struct nxp_ii2c_data *data = dev->data;
+
+#ifdef CONFIG_I2C_CALLBACK
+	if (data->cb != NULL) {
+		/* Async transfer */
+		if (status != kStatus_Success) {
+			I2C_MasterTransferAbort(base, &data->handle);
+			nxp_ii2c_async_done(dev, data, -EIO);
+		} else if (data->msg == data->num_msgs - 1) {
+			nxp_ii2c_async_done(dev, data, 0);
+		} else {
+			data->msg++;
+			nxp_ii2c_async_iter(dev);
+		}
+		return;
+	}
+#endif /* CONFIG_I2C_CALLBACK */
+
+	data->callback_status = status;
+
+	k_sem_give(&data->device_sync_sem);
+}
+
+static uint32_t nxp_ii2c_convert_flags(int msg_flags)
+{
+	uint32_t flags = kI2C_TransferDefaultFlag;
+
+	if (!(msg_flags & I2C_MSG_STOP)) {
+		flags |= kI2C_TransferNoStopFlag;
+	}
+
+	if (msg_flags & I2C_MSG_RESTART) {
+		flags |= kI2C_TransferRepeatedStartFlag;
+	}
+
+	return flags;
+}
+
+static int nxp_ii2c_transfer(const struct device *dev, struct i2c_msg *msgs,
+			     uint8_t num_msgs, uint16_t addr)
+{
+	I2C_Type *base = get_base(dev);
+	struct nxp_ii2c_data *data = dev->data;
+	i2c_master_transfer_t transfer;
+	status_t status;
+	int ret = 0;
+
+	k_sem_take(&data->lock, K_FOREVER);
+
+	/* Iterate over all the messages */
+	for (int i = 0; i < num_msgs; i++) {
+		if (I2C_MSG_ADDR_10_BITS & msgs->flags) {
+			ret = -ENOTSUP;
+			break;
+		}
+
+		/* Initialize the transfer descriptor */
+		transfer.flags = nxp_ii2c_convert_flags(msgs->flags);
+		transfer.slaveAddress = addr;
+		transfer.direction = (msgs->flags & I2C_MSG_READ)
+			? kI2C_Read : kI2C_Write;
+		transfer.subaddress = 0;
+		transfer.subaddressSize = 0;
+		transfer.data = msgs->buf;
+		transfer.dataSize = msgs->len;
+
+		/* Prevent the controller to send a start condition between
+		 * messages, except if explicitly requested.
+		 */
+		if (i != 0 && !(msgs->flags & I2C_MSG_RESTART)) {
+			transfer.flags |= kI2C_TransferNoStartFlag;
+		}
+
+		/* Start the transfer */
+		status = I2C_MasterTransferNonBlocking(base,
+				&data->handle, &transfer);
+
+		/* Return an error if the transfer didn't start successfully
+		 * e.g., if the bus was busy
+		 */
+		if (status != kStatus_Success) {
+			I2C_MasterTransferAbort(base, &data->handle);
+			ret = -EIO;
+			break;
+		}
+
+		/* Wait for the transfer to complete */
+		k_sem_take(&data->device_sync_sem, K_FOREVER);
+
+		/* Return an error if the transfer didn't complete
+		 * successfully. e.g., nak, timeout, lost arbitration
+		 */
+		if (data->callback_status != kStatus_Success) {
+			I2C_MasterTransferAbort(base, &data->handle);
+			ret = -EIO;
+			break;
+		}
+
+		/* Move to the next message */
+		msgs++;
+	}
+
+	k_sem_give(&data->lock);
+
+	return ret;
+}
+
+#ifdef CONFIG_I2C_CALLBACK
+
+static void nxp_ii2c_async_done(const struct device *dev, struct nxp_ii2c_data *data, int result)
+{
+
+	i2c_callback_t cb = data->cb;
+	void *userdata = data->userdata;
+
+	data->msg = 0;
+	data->msgs = NULL;
+	data->num_msgs = 0;
+	data->cb = NULL;
+	data->userdata = NULL;
+	data->addr = 0;
+
+	k_sem_give(&data->lock);
+
+	/* Callback may wish to start another transfer */
+	cb(dev, result, userdata);
+}
+
+/* Start a transfer asynchronously */
+static void nxp_ii2c_async_iter(const struct device *dev)
+{
+	I2C_Type *base = get_base(dev);
+	struct nxp_ii2c_data *data = dev->data;
+	i2c_master_transfer_t transfer;
+	status_t status;
+	struct i2c_msg *msg = &data->msgs[data->msg];
+
+	if (I2C_MSG_ADDR_10_BITS & msg->flags) {
+		nxp_ii2c_async_done(dev, data, -ENOTSUP);
+		return;
+	}
+
+	/* Initialize the transfer descriptor */
+	transfer.flags = nxp_ii2c_convert_flags(msg->flags);
+	transfer.slaveAddress = data->addr;
+	transfer.direction = (msg->flags & I2C_MSG_READ) ? kI2C_Read : kI2C_Write;
+	transfer.subaddress = 0;
+	transfer.subaddressSize = 0;
+	transfer.data = msg->buf;
+	transfer.dataSize = msg->len;
+
+	/* Prevent the controller to send a start condition between
+	 * messages, except if explicitly requested.
+	 */
+	if (data->msg != 0 && !(msg->flags & I2C_MSG_RESTART)) {
+		transfer.flags |= kI2C_TransferNoStartFlag;
+	}
+
+	/* Start the transfer */
+	status = I2C_MasterTransferNonBlocking(base, &data->handle, &transfer);
+
+	/* Return an error if the transfer didn't start successfully
+	 * e.g., if the bus was busy
+	 */
+	if (status != kStatus_Success) {
+		I2C_MasterTransferAbort(base, &data->handle);
+		nxp_ii2c_async_done(dev, data, -EIO);
+	}
+}
+
+static int nxp_ii2c_transfer_cb(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
+				   uint16_t addr, i2c_callback_t cb, void *userdata)
+{
+	struct nxp_ii2c_data *data = dev->data;
+
+	int res = k_sem_take(&data->lock, K_NO_WAIT);
+
+	if (res != 0) {
+		return -EWOULDBLOCK;
+	}
+
+	data->msg = 0;
+	data->msgs = msgs;
+	data->num_msgs = num_msgs;
+	data->addr = addr;
+	data->cb = cb;
+	data->userdata = userdata;
+	data->addr = addr;
+
+	nxp_ii2c_async_iter(dev);
+
+	return 0;
+}
+
+#endif /* CONFIG_I2C_CALLBACK */
+
+static void nxp_ii2c_isr(const struct device *dev)
+{
+	I2C_Type *base = get_base(dev);
+	struct nxp_ii2c_data *data = dev->data;
+
+	I2C_MasterTransferHandleIRQ(base, &data->handle);
+}
+
+static int nxp_ii2c_init(const struct device *dev)
+{
+	I2C_Type *base;
+	const struct nxp_ii2c_config *config = dev->config;
+	struct nxp_ii2c_data *data = dev->data;
+	uint32_t clock_freq, bitrate_cfg;
+	i2c_master_config_t master_config;
+	int error;
+
+	DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP);
+
+	if (!device_is_ready(config->clock_dev)) {
+		LOG_ERR("clock control device not ready");
+		return -ENODEV;
+	}
+
+	if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
+				   &clock_freq)) {
+		return -EINVAL;
+	}
+
+	error = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
+	if (error) {
+		return error;
+	}
+
+	base = get_base(dev);
+
+	k_sem_init(&data->lock, 1, 1);
+	k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT);
+
+	I2C_MasterGetDefaultConfig(&master_config);
+	I2C_MasterInit(base, &master_config, clock_freq);
+	I2C_MasterTransferCreateHandle(base, &data->handle,
+				       nxp_ii2c_master_transfer_callback, (void *)dev);
+
+	bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
+
+	error = nxp_ii2c_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
+	if (error) {
+		return error;
+	}
+
+	config->irq_config_func(dev);
+
+	return 0;
+}
+
+static DEVICE_API(i2c, nxp_ii2c_driver_api) = {
+	.configure = nxp_ii2c_configure,
+	.transfer = nxp_ii2c_transfer,
+#ifdef CONFIG_I2C_CALLBACK
+	.transfer_cb = nxp_ii2c_transfer_cb,
+#endif
+#ifdef CONFIG_I2C_RTIO
+	.iodev_submit = i2c_iodev_submit_fallback,
+#endif
+};
+
+#define I2C_DEVICE_INIT_MCUX(n)			\
+	PINCTRL_DT_INST_DEFINE(n);					\
+									\
+	static void nxp_ii2c_config_func_ ## n(const struct device *dev); \
+									\
+	static const struct nxp_ii2c_config nxp_ii2c_config_ ## n = {	\
+		DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)),	\
+		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),	\
+		.clock_subsys =						\
+			(clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\
+		.irq_config_func = nxp_ii2c_config_func_ ## n,		\
+		.bitrate = DT_INST_PROP(n, clock_frequency),		\
+		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),		\
+	};								\
+									\
+	static struct nxp_ii2c_data nxp_ii2c_data_ ## n;		\
+									\
+	I2C_DEVICE_DT_INST_DEFINE(n,					\
+			nxp_ii2c_init, NULL,				\
+			&nxp_ii2c_data_ ## n,				\
+			&nxp_ii2c_config_ ## n, POST_KERNEL,		\
+			CONFIG_I2C_INIT_PRIORITY,			\
+			&nxp_ii2c_driver_api);				\
+									\
+	static void nxp_ii2c_config_func_ ## n(const struct device *dev) \
+	{								\
+		IRQ_CONNECT(DT_INST_IRQN(n),				\
+			DT_INST_IRQ(n, priority),			\
+			nxp_ii2c_isr,					\
+			DEVICE_DT_INST_GET(n), 0);			\
+									\
+		irq_enable(DT_INST_IRQN(n));				\
+	}
+
+DT_INST_FOREACH_STATUS_OKAY(I2C_DEVICE_INIT_MCUX)
diff --git a/drivers/i2c/i2c_omap.c b/drivers/i2c/i2c_omap.c
new file mode 100644
index 00000000000..222232d106e
--- /dev/null
+++ b/drivers/i2c/i2c_omap.c
@@ -0,0 +1,724 @@
+/* Copyright (C) 2024 BeagleBoard.org Foundation
+ * Copyright (C) 2024 Dhruv Menon <dhruvmenon1104@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ti_omap_i2c
+#include <errno.h>
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/irq.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/pinctrl.h>
+
+#ifdef CONFIG_I2C_OMAP_BUS_RECOVERY
+#include "i2c_bitbang.h"
+#endif /* CONFIG_I2C_OMAP_BUS_RECOVERY */
+
+LOG_MODULE_REGISTER(omap_i2c, CONFIG_I2C_LOG_LEVEL);
+
+#define I2C_OMAP_TIMEOUT     100U
+/* OCP_SYSSTATUS bit definitions */
+#define SYSS_RESETDONE_MASK  BIT(0)
+#define RETRY                -1
+#define I2C_BITRATE_FAST     400000
+#define I2C_BITRATE_STANDARD 100000
+
+/* I2C Registers */
+typedef struct {
+	uint8_t RESERVED_0[0x10]; /**< Reserved, offset: 0x0 */
+
+	__IO uint32_t SYSC;          /**< System Configuration, offset: 0x10 */
+	uint8_t RESERVED_1[0x18];    /**< Reserved, offset: 0x14 - 0x2C */
+	__IO uint32_t IRQENABLE_SET; /**< Interrupt Enable Set, offset: 0x2C */
+	uint8_t RESERVED_2[0x4];     /**< Reserved, offset: 0x30 - 0x34 */
+	__IO uint32_t WE;            /**< Wakeup Enable, offset: 0x34 */
+	uint8_t RESERVED_3[0x4C];    /**< Reserved, offset: 0x38 - 0x84 */
+	__IO uint32_t IE;            /**< Interrupt Enable (Legacy), offset: 0x84 */
+	__IO uint32_t STAT;          /**< Status, offset: 0x88 */
+	uint8_t RESERVED_4[0x4];     /**< Reserved, offset: 0x8C - 0x90 */
+	__IO uint32_t SYSS;          /**< System Status, offset: 0x90 */
+	__IO uint32_t BUF;           /**< Buffer, offset: 0x94 */
+	__IO uint32_t CNT;           /**< Data Count, offset: 0x98 */
+	__IO uint32_t DATA;          /**< Data Access, offset: 0x9C */
+	uint8_t RESERVED_5[0x4];     /**< Reserved, offset: 0xA0 - 0xA4 */
+	__IO uint32_t CON;           /**< Configuration, offset: 0xA4 */
+	__IO uint32_t OA;            /**< Own Address, offset: 0xA8 */
+	__IO uint32_t SA;            /**< Target Address, offset: 0xAC */
+	__IO uint32_t PSC;           /**< Clock Prescaler, offset: 0xB0 */
+	__IO uint32_t SCLL;          /**< SCL Low Time, offset: 0xB4 */
+	__IO uint32_t SCLH;          /**< SCL High Time, offset: 0xB8 */
+	__IO uint32_t SYSTEST;       /**< System Test, offset: 0xBC */
+	__IO uint32_t BUFSTAT;       /**< Buffer Status, offset: 0xC0 */
+} i2c_omap_regs_t;
+
+/* I2C Configuration Register (I2C_OMAP_CON) */
+#define I2C_OMAP_CON_EN        BIT(15) /* I2C module enable */
+#define I2C_OMAP_CON_OPMODE_HS BIT(12) /* High Speed support */
+#define I2C_OMAP_CON_MST       BIT(10) /* Controller/target mode */
+#define I2C_OMAP_CON_TRX       BIT(9)  /* TX/RX mode (controller only) */
+#define I2C_OMAP_CON_STP       BIT(1)  /* Stop condition (controller only) */
+#define I2C_OMAP_CON_STT       BIT(0)  /* Start condition (controller) */
+
+/* I2C Buffer Configuration Register (I2C_OMAP_BUF): */
+#define I2C_OMAP_BUF_RXFIF_CLR BIT(14) /* RX FIFO Clear */
+#define I2C_OMAP_BUF_TXFIF_CLR BIT(6)  /* TX FIFO Clear */
+
+/* I2C Status Register (I2C_OMAP_STAT): */
+#define I2C_OMAP_STAT_XDR  BIT(14) /* TX Buffer draining */
+#define I2C_OMAP_STAT_RDR  BIT(13) /* RX Buffer draining */
+#define I2C_OMAP_STAT_BB   BIT(12) /* Bus busy */
+#define I2C_OMAP_STAT_ROVR BIT(11) /* Receive overrun */
+#define I2C_OMAP_STAT_XUDF BIT(10) /* Transmit underflow */
+#define I2C_OMAP_STAT_AAS  BIT(9)  /* Address as target */
+#define I2C_OMAP_STAT_XRDY BIT(4)  /* Transmit data ready */
+#define I2C_OMAP_STAT_RRDY BIT(3)  /* Receive data ready */
+#define I2C_OMAP_STAT_ARDY BIT(2)  /* Register access ready */
+#define I2C_OMAP_STAT_NACK BIT(1)  /* No ack interrupt enable */
+#define I2C_OMAP_STAT_AL   BIT(0)  /* Arbitration lost */
+
+/* I2C System Test Register (I2C_OMAP_SYSTEST): */
+#define I2C_OMAP_SYSTEST_ST_EN       BIT(15)   /* System test enable */
+#define I2C_OMAP_SYSTEST_FREE        BIT(14)   /* Free running mode */
+#define I2C_OMAP_SYSTEST_TMODE_MASK  (3 << 12) /* Test mode select mask */
+#define I2C_OMAP_SYSTEST_TMODE_SHIFT (12)      /* Test mode select shift */
+
+/* Functional mode */
+#define I2C_OMAP_SYSTEST_SCL_I_FUNC BIT(8) /* SCL line input value */
+#define I2C_OMAP_SYSTEST_SDA_I_FUNC BIT(6) /* SDA line input value */
+
+/* SDA/SCL IO mode */
+#define I2C_OMAP_SYSTEST_SCL_I BIT(3) /* SCL line sense in */
+#define I2C_OMAP_SYSTEST_SCL_O BIT(2) /* SCL line drive out */
+#define I2C_OMAP_SYSTEST_SDA_I BIT(1) /* SDA line sense in */
+#define I2C_OMAP_SYSTEST_SDA_O BIT(0) /* SDA line drive out */
+
+typedef void (*init_func_t)(const struct device *dev);
+#define DEV_CFG(dev)      ((const struct i2c_omap_cfg *)(dev)->config)
+#define DEV_DATA(dev)     ((struct i2c_omap_data *)(dev)->data)
+#define DEV_I2C_BASE(dev) ((i2c_omap_regs_t *)DEVICE_MMIO_NAMED_GET(dev, base))
+
+struct i2c_omap_cfg {
+	DEVICE_MMIO_NAMED_ROM(base);
+	uint32_t irq;
+	uint32_t speed;
+	const struct pinctrl_dev_config *pcfg;
+};
+
+enum i2c_omap_speed {
+	I2C_OMAP_SPEED_STANDARD,
+	I2C_OMAP_SPEED_FAST,
+	I2C_OMAP_SPEED_FAST_PLUS,
+};
+
+struct i2c_omap_speed_config {
+	uint32_t pscstate;
+	uint32_t scllstate;
+	uint32_t sclhstate;
+};
+
+struct i2c_omap_data {
+	DEVICE_MMIO_NAMED_RAM(base);
+	enum i2c_omap_speed speed;
+	struct i2c_omap_speed_config speed_config;
+	struct i2c_msg current_msg;
+	struct k_sem lock;
+	bool receiver;
+	bool bb_valid;
+};
+
+/**
+ * @brief Initializes the OMAP I2C driver.
+ *
+ * This function is responsible for initializing the OMAP I2C driver.
+ *
+ * @param dev Pointer to the device structure for the I2C driver instance.
+ */
+static void i2c_omap_init_ll(const struct device *dev)
+{
+
+	struct i2c_omap_data *data = DEV_DATA(dev);
+	i2c_omap_regs_t *i2c_base_addr = DEV_I2C_BASE(dev);
+
+	i2c_base_addr->CON = 0;
+	i2c_base_addr->PSC = data->speed_config.pscstate;
+	i2c_base_addr->SCLL = data->speed_config.scllstate;
+	i2c_base_addr->SCLH = data->speed_config.sclhstate;
+	i2c_base_addr->CON = I2C_OMAP_CON_EN;
+}
+
+/**
+ * @brief Reset the OMAP I2C controller.
+ *
+ * This function resets the OMAP I2C controller specified by the device pointer.
+ *
+ * @param dev Pointer to the device structure for the I2C controller.
+ * @return 0 on success, negative errno code on failure.
+ */
+static int i2c_omap_reset(const struct device *dev)
+{
+	struct i2c_omap_data *data = DEV_DATA(dev);
+	i2c_omap_regs_t *i2c_base_addr = DEV_I2C_BASE(dev);
+	uint64_t timeout;
+	uint16_t sysc;
+
+	sysc = i2c_base_addr->SYSC;
+	i2c_base_addr->CON &= ~I2C_OMAP_CON_EN;
+	timeout = k_uptime_get() + I2C_OMAP_TIMEOUT;
+	i2c_base_addr->CON = I2C_OMAP_CON_EN;
+	while (!(i2c_base_addr->SYSS & SYSS_RESETDONE_MASK)) {
+		if (k_uptime_get() > timeout) {
+			LOG_WRN("timeout waiting for controller reset");
+			return -ETIMEDOUT;
+		}
+		k_busy_wait(100);
+	}
+	i2c_base_addr->SYSC = sysc;
+	data->bb_valid = 0;
+	return 0;
+}
+
+/**
+ * @brief Set the speed of the OMAP I2C controller.
+ *
+ * This function sets the speed of the OMAP I2C controller based on the
+ * specified speed parameter. The speed can be set to either Fast mode or
+ * Standard mode.
+ *
+ * @param dev The pointer to the device structure.
+ * @param speed The desired speed for the I2C controller.
+ *
+ * @return 0 on success, negative error code on failure.
+ */
+static int i2c_omap_set_speed(const struct device *dev, uint32_t speed)
+{
+	struct i2c_omap_data *data = DEV_DATA(dev);
+
+	/* If configured for High Speed */
+	switch (speed) {
+	case I2C_BITRATE_FAST:
+		/* Fast mode */
+		data->speed_config = (struct i2c_omap_speed_config){
+			.pscstate = 9,
+			.scllstate = 7,
+			.sclhstate = 5,
+		};
+		break;
+	case I2C_BITRATE_STANDARD:
+		/* Standard mode */
+		data->speed_config = (struct i2c_omap_speed_config){
+			.pscstate = 23,
+			.scllstate = 13,
+			.sclhstate = 15,
+		};
+		break;
+	default:
+		return -ERANGE;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Configure the OMAP I2C controller with the specified device configuration.
+ *
+ * This function configures the OMAP I2C controller with the specified device configuration.
+ *
+ * @param dev The pointer to the device structure.
+ * @param dev_config The device configuration to be applied.
+ *
+ * @return 0 on success, negative error code on failure.
+ */
+static int i2c_omap_configure(const struct device *dev, uint32_t dev_config)
+{
+	uint32_t speed_cfg = I2C_BITRATE_STANDARD;
+	struct i2c_omap_data *data = DEV_DATA(dev);
+
+	switch (I2C_SPEED_GET(dev_config)) {
+	case I2C_SPEED_STANDARD:
+		speed_cfg = I2C_BITRATE_STANDARD;
+		break;
+	case I2C_SPEED_FAST:
+		speed_cfg = I2C_BITRATE_FAST;
+		break;
+	default:
+		return -ENOTSUP;
+	}
+	if ((dev_config & I2C_MODE_CONTROLLER) != I2C_MODE_CONTROLLER) {
+		return -ENOTSUP;
+	}
+	k_sem_take(&data->lock, K_FOREVER);
+	i2c_omap_set_speed(dev, speed_cfg);
+	i2c_omap_init_ll(dev);
+	k_sem_give(&data->lock);
+	return 0;
+}
+
+/**
+ * @brief Transmit or receive data over I2C bus
+ *
+ * This function transmits or receives data over the I2C bus using the OMAP I2C controller.
+ *
+ * @param dev Pointer to the I2C device structure
+ * @param num_bytes Number of bytes to transmit or receive
+ */
+static void i2c_omap_transmit_receive_data(const struct device *dev, uint8_t num_bytes)
+{
+	struct i2c_omap_data *data = DEV_DATA(dev);
+	i2c_omap_regs_t *i2c_base_addr = DEV_I2C_BASE(dev);
+	uint8_t *buf_ptr = data->current_msg.buf;
+
+	while (num_bytes--) {
+		if (data->receiver) {
+			*buf_ptr++ = i2c_base_addr->DATA;
+		} else {
+			i2c_base_addr->DATA = *(buf_ptr++);
+		}
+	}
+}
+
+/**
+ * @brief Resize the FIFO buffer for the OMAP I2C controller.
+ *
+ * This function resizes the FIFO buffer for the OMAP I2C controller based on the specified size.
+ * It clears the RX threshold and sets the new size for the receiver, or clears the TX threshold
+ * and sets the new size for the transmitter.
+ *
+ * @param dev Pointer to the device structure.
+ * @param size The new size of the FIFO buffer.
+ */
+static void i2c_omap_resize_fifo(const struct device *dev, uint8_t size)
+{
+	struct i2c_omap_data *data = DEV_DATA(dev);
+	i2c_omap_regs_t *i2c_base_addr = DEV_I2C_BASE(dev);
+
+	if (data->receiver) {
+		i2c_base_addr->BUF &= I2C_OMAP_BUF_RXFIF_CLR;
+		i2c_base_addr->BUF |= ((size) << 8) | I2C_OMAP_BUF_RXFIF_CLR;
+	} else {
+		i2c_base_addr->BUF &= I2C_OMAP_BUF_TXFIF_CLR;
+		i2c_base_addr->BUF |= (size) | I2C_OMAP_BUF_TXFIF_CLR;
+	}
+}
+
+#ifdef CONFIG_I2C_OMAP_BUS_RECOVERY
+/**
+ * @brief Get the state of the SDA line.
+ *
+ * This function retrieves the state of the SDA (data) line for the OMAP I2C controller.
+ *
+ * @param io_context The I2C context.
+ * @return The state of the SDA line.
+ */
+static int i2c_omap_get_sda(void *io_context)
+{
+	const struct i2c_omap_cfg *cfg = (const struct i2c_omap_cfg *)io_context;
+	i2c_omap_regs_t *i2c_base_addr = (i2c_omap_regs_t *)cfg->base.addr;
+
+	return (i2c_base_addr->SYSTEST & I2C_OMAP_SYSTEST_SDA_I_FUNC) ? 1 : 0;
+}
+
+/**
+ * @brief Set the state of the SDA line.
+ *
+ * This function sets the state of the SDA (data) line for the OMAP I2C controller.
+ *
+ * @param io_context The I2C context.
+ * @param state The state to set (0 for low, 1 for high).
+ */
+static void i2c_omap_set_sda(void *io_context, int state)
+{
+	const struct i2c_omap_cfg *cfg = (const struct i2c_omap_cfg *)io_context;
+	i2c_omap_regs_t *i2c_base_addr = (i2c_omap_regs_t *)cfg->base.addr;
+
+	if (state) {
+		i2c_base_addr->SYSTEST |= I2C_OMAP_SYSTEST_SDA_O;
+	} else {
+		i2c_base_addr->SYSTEST &= ~I2C_OMAP_SYSTEST_SDA_O;
+	}
+}
+
+/**
+ * @brief Set the state of the SCL line.
+ *
+ * This function sets the state of the SCL (clock) line for the OMAP I2C controller.
+ *
+ * @param io_context The I2C context.
+ * @param state The state to set (0 for low, 1 for high).
+ */
+static void i2c_omap_set_scl(void *io_context, int state)
+{
+	const struct i2c_omap_cfg *cfg = (const struct i2c_omap_cfg *)io_context;
+	i2c_omap_regs_t *i2c_base_addr = (i2c_omap_regs_t *)cfg->base.addr;
+
+	if (state) {
+		i2c_base_addr->SYSTEST |= I2C_OMAP_SYSTEST_SCL_O;
+	} else {
+		i2c_base_addr->SYSTEST &= ~I2C_OMAP_SYSTEST_SCL_O;
+	}
+}
+/**
+ * @brief Recovers the I2C bus using the OMAP I2C controller.
+ *
+ * This function attempts to recover the I2C bus by performing a bus recovery
+ * sequence using the OMAP I2C controller. It uses the provided device
+ * configuration and bit-banging operations to recover the bus.
+ *
+ * @param dev Pointer to the device structure.
+ * @return 0 on success, negative error code on failure.
+ */
+
+static int i2c_omap_recover_bus(const struct device *dev)
+{
+	const struct i2c_omap_cfg *cfg = DEV_CFG(dev);
+	i2c_omap_regs_t *i2c_base_addr = DEV_I2C_BASE(dev);
+	struct i2c_omap_data *data = DEV_DATA(dev);
+
+	struct i2c_bitbang bitbang_omap;
+	struct i2c_bitbang_io bitbang_omap_io = {
+		.get_sda = i2c_omap_get_sda,
+		.set_scl = i2c_omap_set_scl,
+		.set_sda = i2c_omap_set_sda,
+	};
+	int error = 0;
+
+	k_sem_take(&data->lock, K_FOREVER);
+	i2c_base_addr->SYSTEST |= I2C_OMAP_SYSTEST_ST_EN | (3 << I2C_OMAP_SYSTEST_TMODE_SHIFT) |
+				  I2C_OMAP_SYSTEST_SCL_O | I2C_OMAP_SYSTEST_SDA_O;
+	i2c_bitbang_init(&bitbang_omap, &bitbang_omap_io, (void *)cfg);
+	error = i2c_bitbang_recover_bus(&bitbang_omap);
+	if (error != 0) {
+		LOG_ERR("failed to recover bus (err %d)", error);
+		goto restore;
+	}
+
+restore:
+	i2c_base_addr->SYSTEST &= ~(I2C_OMAP_SYSTEST_ST_EN | I2C_OMAP_SYSTEST_TMODE_MASK |
+				    I2C_OMAP_SYSTEST_SCL_O | I2C_OMAP_SYSTEST_SDA_O);
+	i2c_omap_reset(dev);
+	k_sem_give(&data->lock);
+	return error;
+}
+#endif /* CONFIG_I2C_OMAP_BUS_RECOVERY */
+
+/**
+ * @brief Wait for the bus to become free (no longer busy).
+ *
+ * This function waits for the bus to become free by continuously checking the
+ * status register of the OMAP I2C controller. If the bus remains busy for a
+ * certain timeout period, the function will return attempts to recover the bus by calling
+ * i2c_omap_recover_bus().
+ *
+ * @param dev The I2C device structure.
+ * @return 0 if the bus becomes free, or a negative error code if the bus cannot
+ * be recovered.
+ */
+static int i2c_omap_wait_for_bb(const struct device *dev)
+{
+	i2c_omap_regs_t *i2c_base_addr = DEV_I2C_BASE(dev);
+	uint32_t timeout = k_uptime_get_32() + I2C_OMAP_TIMEOUT;
+
+	while (i2c_base_addr->STAT & I2C_OMAP_STAT_BB) {
+		if (k_uptime_get_32() > timeout) {
+			LOG_ERR("Bus busy timeout");
+#ifdef CONFIG_I2C_OMAP_BUS_RECOVERY
+			return i2c_omap_recover_bus(dev);
+#else
+			return -ETIMEDOUT;
+#endif /* CONFIG_I2C_OMAP_BUS_RECOVERY */
+		}
+		k_busy_wait(100);
+	}
+	return 0;
+}
+
+/**
+ * @brief Performs data transfer for the OMAP I2C driver.
+ *
+ * This function is responsible for handling the data transfer logic for the OMAP I2C driver.
+ * It reads the status register and performs the necessary actions based on the status flags.
+ * It handles both receive and transmit logic, and also handles error conditions such as NACK,
+ * arbitration lost, receive overrun, and transmit underflow.
+ *
+ * @param dev Pointer to the device structure.
+ *
+ * @return Returns 0 on success, or a negative error code on failure.
+ */
+static int i2c_omap_transfer_message_ll(const struct device *dev)
+{
+	struct i2c_omap_data *data = DEV_DATA(dev);
+	i2c_omap_regs_t *i2c_base_addr = DEV_I2C_BASE(dev);
+	uint16_t stat = i2c_base_addr->STAT, result = 0;
+
+	if (data->receiver) {
+		stat &= ~(I2C_OMAP_STAT_XDR | I2C_OMAP_STAT_XRDY);
+	} else {
+		stat &= ~(I2C_OMAP_STAT_RDR | I2C_OMAP_STAT_RRDY);
+	}
+	if (stat & I2C_OMAP_STAT_NACK) {
+		result |= I2C_OMAP_STAT_NACK;
+		i2c_base_addr->STAT |= I2C_OMAP_STAT_NACK;
+	}
+	if (stat & I2C_OMAP_STAT_AL) {
+		result |= I2C_OMAP_STAT_AL;
+		i2c_base_addr->STAT |= I2C_OMAP_STAT_AL;
+	}
+	if (stat & I2C_OMAP_STAT_ARDY) {
+		i2c_base_addr->STAT |= I2C_OMAP_STAT_ARDY;
+	}
+	if (stat & (I2C_OMAP_STAT_ARDY | I2C_OMAP_STAT_NACK | I2C_OMAP_STAT_AL)) {
+
+		i2c_base_addr->STAT |=
+			(I2C_OMAP_STAT_RRDY | I2C_OMAP_STAT_RDR | I2C_OMAP_STAT_XRDY |
+			 I2C_OMAP_STAT_XDR | I2C_OMAP_STAT_ARDY);
+		return result;
+	}
+
+	/* Handle receive logic */
+	if (stat & (I2C_OMAP_STAT_RRDY | I2C_OMAP_STAT_RDR)) {
+		int buffer =
+			(stat & I2C_OMAP_STAT_RRDY) ? i2c_base_addr->BUF : i2c_base_addr->BUFSTAT;
+		i2c_omap_transmit_receive_data(dev, buffer);
+		i2c_base_addr->STAT |=
+			(stat & I2C_OMAP_STAT_RRDY) ? I2C_OMAP_STAT_RRDY : I2C_OMAP_STAT_RDR;
+		return RETRY;
+	}
+
+	/* Handle transmit logic */
+	if (stat & (I2C_OMAP_STAT_XRDY | I2C_OMAP_STAT_XDR)) {
+		int buffer =
+			(stat & I2C_OMAP_STAT_XRDY) ? i2c_base_addr->BUF : i2c_base_addr->BUFSTAT;
+		i2c_omap_transmit_receive_data(dev, buffer);
+		i2c_base_addr->STAT |=
+			(stat & I2C_OMAP_STAT_XRDY) ? I2C_OMAP_STAT_XRDY : I2C_OMAP_STAT_XDR;
+		return RETRY;
+	}
+
+	if (stat & I2C_OMAP_STAT_ROVR) {
+		i2c_base_addr->STAT |= I2C_OMAP_STAT_ROVR;
+		return I2C_OMAP_STAT_ROVR;
+	}
+	if (stat & I2C_OMAP_STAT_XUDF) {
+		i2c_base_addr->STAT |= I2C_OMAP_STAT_XUDF;
+		return I2C_OMAP_STAT_XUDF;
+	}
+	return RETRY;
+}
+
+/**
+ * @brief Performs an I2C transfer of a single message.
+ *
+ * This function is responsible for performing an I2C transfer of a single message.
+ * It sets up the necessary configurations, writes the target device address,
+ * sets the buffer and buffer length, and handles various error conditions.
+ *
+ * @param dev The I2C device structure.
+ * @param msg Pointer to the I2C message structure.
+ * @param polling Flag indicating whether to use polling mode or not.
+ * @param addr The target device address.
+ *
+ * @return 0 on success, negative error code on failure.
+ *         Possible error codes include:
+ *         - ETIMEDOUT: Timeout occurred during the transfer.
+ *         - EIO: I/O error due to receiver overrun or transmit underflow.
+ *         - EAGAIN: Arbitration lost error, try again.
+ *         - ENOMSG: Message error due to NACK.
+ */
+static int i2c_omap_transfer_message(const struct device *dev, struct i2c_msg *msg, bool polling,
+				     uint16_t addr)
+{
+	struct i2c_omap_data *data = DEV_DATA(dev);
+	i2c_omap_regs_t *i2c_base_addr = DEV_I2C_BASE(dev);
+	unsigned long time_left = 1000;
+	uint16_t control_reg;
+	int result = 0;
+	/* Determine message direction (read or write) and update the receiver flag */
+	data->receiver = msg->flags & I2C_MSG_READ;
+	/* Adjust the FIFO size according to the message length */
+	i2c_omap_resize_fifo(dev, msg->len);
+	/* Set the target I2C address for the transfer */
+	i2c_base_addr->SA = addr;
+	/* Store the message in the data structure */
+	data->current_msg = *msg;
+	/* Set the message length in the I2C controller */
+	i2c_base_addr->CNT = msg->len;
+	/* Clear FIFO buffers */
+	control_reg = i2c_base_addr->BUF;
+	control_reg |= I2C_OMAP_BUF_RXFIF_CLR | I2C_OMAP_BUF_TXFIF_CLR;
+	i2c_base_addr->BUF = control_reg;
+	/* If we're not polling, reset the command completion semaphore */
+	if (!polling) {
+		k_sem_reset(&data->lock);
+	}
+	/* Reset the command error status */
+	/* Prepare the control register for the I2C operation */
+	control_reg = I2C_OMAP_CON_EN | I2C_OMAP_CON_MST | I2C_OMAP_CON_STT;
+	/* Enable high-speed mode if required by the transfer speed */
+	if (data->speed > I2C_BITRATE_FAST) {
+		control_reg |= I2C_OMAP_CON_OPMODE_HS;
+	}
+	/* Set the STOP condition if it's specified in the message flags */
+	if (msg->flags & I2C_MSG_STOP) {
+		control_reg |= I2C_OMAP_CON_STP;
+	}
+	/* Set the transmission mode based on whether it's a read or write operation */
+	if (!(msg->flags & I2C_MSG_READ)) {
+		control_reg |= I2C_OMAP_CON_TRX;
+	}
+	/* Start the I2C transfer by writing the control register */
+	i2c_base_addr->CON = control_reg;
+	/* Poll for status until the transfer is complete */
+	/* Call a lower-level function to continue the transfer */
+	do {
+		result = i2c_omap_transfer_message_ll(dev);
+		time_left--;
+	} while (result == RETRY && time_left);
+
+	/* If no errors occurred, return success */
+	if (!result) {
+		return 0;
+	}
+
+	/* Handle timeout or specific error conditions */
+	if (result & (I2C_OMAP_STAT_ROVR | I2C_OMAP_STAT_XUDF)) {
+		i2c_omap_reset(dev);
+		i2c_omap_init_ll(dev);
+		/* Return an error code based on whether it was a timeout or buffer error */
+		return -EIO; /* Receiver overrun or transmitter underflow */
+	}
+	/* Handle arbitration loss and NACK errors */
+	if (result & (I2C_OMAP_STAT_AL | -EAGAIN)) {
+		return -EAGAIN;
+	}
+	if (result & I2C_OMAP_STAT_NACK) {
+		/* Issue a STOP condition after NACK */
+		i2c_base_addr->CON |= I2C_OMAP_CON_STP;
+		return -ENOMSG; /* Indicate a message error due to NACK */
+	}
+
+	/* Return a general I/O error if no specific error conditions matched */
+	return -EIO;
+}
+
+/**
+ * @brief Performs a common transfer operation for OMAP I2C devices.
+ *
+ * This function is responsible for transferring multiple I2C messages in a common way
+ * for OMAP I2C devices. It waits for the bus to be idle, then iterates through each
+ * message in the provided array and transfers them one by one using the i2c_omap_transfer_message()
+ * function. After all messages have been transferred, it waits for the bus to be idle again
+ * before returning.
+ *
+ * @param dev The pointer to the I2C device structure.
+ * @param msg An array of I2C messages to be transferred.
+ * @param num The number of messages in the array.
+ * @param polling Specifies whether to use polling or interrupt-based transfer.
+ * @param addr The I2C target address.
+ * @return 0 on success, or a negative error code on failure.
+ */
+static int i2c_omap_transfer_main(const struct device *dev, struct i2c_msg msg[], int num,
+				  bool polling, uint16_t addr)
+{
+	int ret;
+
+	ret = i2c_omap_wait_for_bb(dev);
+	struct i2c_omap_data *data = DEV_DATA(dev);
+
+	k_sem_take(&data->lock, K_FOREVER);
+	if (ret < 0) {
+		return ret;
+	}
+	for (int msg_idx = 0; msg_idx < num; msg_idx++) {
+		ret = i2c_omap_transfer_message(dev, &msg[msg_idx], polling, addr);
+		if (ret < 0) {
+			break;
+		}
+	}
+	k_sem_give(&data->lock);
+	i2c_omap_wait_for_bb(dev);
+	return ret;
+}
+
+/**
+ * @brief OMAP I2C transfer function using polling.
+ *
+ * This function performs the I2C transfer using the OMAP I2C controller
+ * in polling mode. It calls the common transfer function with the
+ * specified messages, number of messages, and target address.
+ *
+ * @param dev Pointer to the I2C device structure.
+ * @param msgs Array of I2C messages to be transferred.
+ * @param num_msgs Number of I2C messages in the array.
+ * @param addr Target address.
+ * @return 0 on success, negative error code on failure.
+ */
+static int i2c_omap_transfer_polling(const struct device *dev, struct i2c_msg msgs[],
+						    uint8_t num_msgs, uint16_t addr)
+{
+	return i2c_omap_transfer_main(dev, msgs, num_msgs, true, addr);
+}
+
+static DEVICE_API(i2c, i2c_omap_api) = {
+	.transfer = i2c_omap_transfer_polling,
+	.configure = i2c_omap_configure,
+#ifdef CONFIG_I2C_OMAP_BUS_RECOVERY
+	.recover_bus = i2c_omap_recover_bus,
+#endif /* CONFIG_I2C_OMAP_BUS_RECOVERY */
+};
+
+/**
+ * @brief Initialize the OMAP I2C controller.
+ *
+ * This function initializes the OMAP I2C controller by setting the speed and
+ * performing any necessary initialization steps.
+ *
+ * @param dev Pointer to the device structure for the I2C controller.
+ * @return 0 if successful, negative error code otherwise.
+ */
+static int i2c_omap_init(const struct device *dev)
+{
+	struct i2c_omap_data *data = DEV_DATA(dev);
+	const struct i2c_omap_cfg *cfg = DEV_CFG(dev);
+	int ret;
+
+	ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret < 0) {
+		LOG_ERR("failed to apply pinctrl");
+		return ret;
+	}
+
+	k_sem_init(&data->lock, 1, 1);
+	/* Set the speed for I2C */
+	if (i2c_omap_set_speed(dev, cfg->speed)) {
+		LOG_ERR("Failed to set speed");
+		return -ENOTSUP;
+	}
+	i2c_omap_init_ll(dev);
+	return 0;
+}
+
+#define I2C_OMAP_INIT(inst)                                                                        \
+	PINCTRL_DT_INST_DEFINE(inst);                                                              \
+	LOG_INSTANCE_REGISTER(omap_i2c, inst, CONFIG_I2C_LOG_LEVEL);                               \
+	static const struct i2c_omap_cfg i2c_omap_cfg_##inst = {                                   \
+		DEVICE_MMIO_NAMED_ROM_INIT(base, DT_DRV_INST(inst)),                               \
+		.irq = DT_INST_IRQN(inst),                                                         \
+		.speed = DT_INST_PROP(inst, clock_frequency),                                      \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),                                      \
+	};                                                                                         \
+                                                                                                   \
+	static struct i2c_omap_data i2c_omap_data_##inst;                                          \
+                                                                                                   \
+	I2C_DEVICE_DT_INST_DEFINE(inst,                                                            \
+		i2c_omap_init,                                                                     \
+		NULL,                                                                              \
+		&i2c_omap_data_##inst,                                                             \
+		&i2c_omap_cfg_##inst,                                                              \
+		POST_KERNEL,                                                                       \
+		CONFIG_I2C_INIT_PRIORITY,                                                          \
+		&i2c_omap_api);
+
+DT_INST_FOREACH_STATUS_OKAY(I2C_OMAP_INIT)
diff --git a/drivers/i2c/i2c_renesas_ra_iic.c b/drivers/i2c/i2c_renesas_ra_iic.c
index 8643b0c3d2e..a58fd3323b4 100644
--- a/drivers/i2c/i2c_renesas_ra_iic.c
+++ b/drivers/i2c/i2c_renesas_ra_iic.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -479,15 +479,10 @@ static DEVICE_API(i2c, i2c_ra_iic_driver_api) = {
 	.transfer = i2c_ra_iic_transfer,
 };
 
-#define _ELC_EVENT_IIC_RXI(channel) ELC_EVENT_IIC##channel##_RXI
-#define _ELC_EVENT_IIC_TXI(channel) ELC_EVENT_IIC##channel##_TXI
-#define _ELC_EVENT_IIC_TEI(channel) ELC_EVENT_IIC##channel##_TEI
-#define _ELC_EVENT_IIC_ERI(channel) ELC_EVENT_IIC##channel##_ERI
-
-#define ELC_EVENT_IIC_RXI(channel) _ELC_EVENT_IIC_RXI(channel)
-#define ELC_EVENT_IIC_TXI(channel) _ELC_EVENT_IIC_TXI(channel)
-#define ELC_EVENT_IIC_TEI(channel) _ELC_EVENT_IIC_TEI(channel)
-#define ELC_EVENT_IIC_ERI(channel) _ELC_EVENT_IIC_ERI(channel)
+#define EVENT_IIC_RXI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_IIC, channel, _RXI))
+#define EVENT_IIC_TXI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_IIC, channel, _TXI))
+#define EVENT_IIC_TEI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_IIC, channel, _TEI))
+#define EVENT_IIC_ERI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_IIC, channel, _ERI))
 
 #define I2C_RA_IIC_INIT(index)                                                                     \
                                                                                                    \
@@ -496,13 +491,13 @@ static DEVICE_API(i2c, i2c_ra_iic_driver_api) = {
 	static void i2c_ra_iic_irq_config_func##index(const struct device *dev)                    \
 	{                                                                                          \
 		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, rxi, irq)] =                               \
-			ELC_EVENT_IIC_RXI(DT_INST_PROP(index, channel));                           \
+			EVENT_IIC_RXI(DT_INST_PROP(index, channel));                               \
 		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, txi, irq)] =                               \
-			ELC_EVENT_IIC_TXI(DT_INST_PROP(index, channel));                           \
+			EVENT_IIC_TXI(DT_INST_PROP(index, channel));                               \
 		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, tei, irq)] =                               \
-			ELC_EVENT_IIC_TEI(DT_INST_PROP(index, channel));                           \
+			EVENT_IIC_TEI(DT_INST_PROP(index, channel));                               \
 		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, eri, irq)] =                               \
-			ELC_EVENT_IIC_ERI(DT_INST_PROP(index, channel));                           \
+			EVENT_IIC_ERI(DT_INST_PROP(index, channel));                               \
                                                                                                    \
 		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, rxi, irq),                                  \
 			    DT_INST_IRQ_BY_NAME(index, rxi, priority), iic_master_rxi_isr,         \
diff --git a/drivers/i2c/i2c_renesas_ra_sci_b.c b/drivers/i2c/i2c_renesas_ra_sci_b.c
new file mode 100644
index 00000000000..4c3f5f29dc9
--- /dev/null
+++ b/drivers/i2c/i2c_renesas_ra_sci_b.c
@@ -0,0 +1,728 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_ra_i2c_sci_b
+
+#define MDDR_DISABLE 256
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/irq.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/logging/log.h>
+
+#include "r_sci_b_i2c.h"
+#ifdef CONFIG_I2C_RENESAS_RA_SCI_B_DTC
+#include "r_dtc.h"
+#endif
+
+#include <soc.h>
+
+LOG_MODULE_REGISTER(renesas_ra_i2c_sci_b, CONFIG_I2C_LOG_LEVEL);
+
+#define I2C_MAX_MSG_LEN (1 << (sizeof(uint8_t) * 8))
+
+typedef void (*init_func_t)(const struct device *dev);
+struct sci_b_i2c_config {
+	void (*irq_config_func)(const struct device *dev);
+	const struct pinctrl_dev_config *pcfg;
+	uint16_t sda_output_delay;
+};
+
+struct sci_b_i2c_data {
+	sci_b_i2c_instance_ctrl_t ctrl;
+	i2c_master_cfg_t i2c_config;
+	sci_b_i2c_extended_cfg_t ext_cfg;
+	struct k_sem bus_lock;
+	struct k_sem complete_sem;
+	i2c_master_event_t event;
+	uint32_t dev_config;
+
+#ifdef CONFIG_I2C_CALLBACK
+	uint16_t addr;
+	uint32_t msg_idx;
+	struct i2c_msg *msgs;
+	uint32_t num_msgs;
+	i2c_callback_t cb;
+	void *p_context;
+#endif /* CONFIG_I2C_CALLBACK */
+
+#ifdef CONFIG_I2C_RENESAS_RA_SCI_B_DTC
+	/* RX */
+	transfer_instance_t rx_transfer;
+	transfer_info_t rx_transfer_info;
+	transfer_cfg_t rx_transfer_cfg;
+	dtc_instance_ctrl_t rx_transfer_ctrl;
+	dtc_extended_cfg_t rx_transfer_cfg_extend;
+
+	/* TX */
+	transfer_instance_t tx_transfer;
+	transfer_info_t tx_transfer_info;
+	transfer_cfg_t tx_transfer_cfg;
+	dtc_instance_ctrl_t tx_transfer_ctrl;
+	dtc_extended_cfg_t tx_transfer_cfg_extend;
+#endif /* CONFIG_I2C_RENESAS_RA_SCI_B_DTC */
+};
+
+static void calc_sci_b_iic_clock_setting(const struct device *dev, const uint32_t fsp_i2c_rate,
+					 sci_b_i2c_clock_settings_t *clk_cfg);
+
+/* FSP interruption handlers. */
+void sci_b_i2c_txi_isr(void);
+void sci_b_i2c_tei_isr(void);
+void sci_b_i2c_rxi_isr(void);
+
+static int renesas_ra_sci_b_i2c_configure(const struct device *dev, uint32_t dev_config)
+{
+	struct sci_b_i2c_data *data = (struct sci_b_i2c_data *const)dev->data;
+
+	if (!(dev_config & I2C_MODE_CONTROLLER)) {
+		LOG_ERR("Only I2C Master mode supported.");
+		return -EIO;
+	}
+
+	switch (I2C_SPEED_GET(dev_config)) {
+	case I2C_SPEED_STANDARD:
+		data->i2c_config.rate = I2C_MASTER_RATE_STANDARD;
+		break;
+	case I2C_SPEED_FAST:
+		data->i2c_config.rate = I2C_MASTER_RATE_FAST;
+		break;
+	default:
+		LOG_ERR("Invalid I2C speed rate flag: %d", I2C_SPEED_GET(dev_config));
+		return -EIO;
+	}
+
+	calc_sci_b_iic_clock_setting(dev, data->i2c_config.rate, &data->ext_cfg.clock_settings);
+
+	R_SCI_B_I2C_Close(&data->ctrl);
+	R_SCI_B_I2C_Open(&data->ctrl, &data->i2c_config);
+
+	/* save current devconfig. */
+	data->dev_config = dev_config;
+
+	return 0;
+}
+
+static int renesas_ra_sci_b_i2c_get_config(const struct device *dev, uint32_t *dev_config)
+{
+	struct sci_b_i2c_data *data = (struct sci_b_i2c_data *const)dev->data;
+	*dev_config = data->dev_config;
+	return 0;
+}
+
+#define OPERATION(msg) (((struct i2c_msg *)msg)->flags & I2C_MSG_RW_MASK)
+
+static int renesas_ra_sci_b_i2c_transfer(const struct device *dev, struct i2c_msg *msgs,
+					 uint8_t num_msgs, uint16_t addr)
+{
+	struct sci_b_i2c_data *data = (struct sci_b_i2c_data *const)dev->data;
+	struct i2c_msg *current, *next;
+	fsp_err_t fsp_err;
+	int ret;
+
+	if (!num_msgs) {
+		return 0;
+	}
+
+	/* Handle i2c burst write, restructure message to be compatible with HAL*/
+	if (num_msgs == 2) {
+		if (msgs[0].len == 1U && !(msgs[0].flags & I2C_MSG_READ) &&
+		    !(msgs[1].flags & I2C_MSG_READ)) {
+			uint16_t tmp_len = msgs[0].len + msgs[1].len;
+
+			if (tmp_len <= I2C_MAX_MSG_LEN) {
+				static uint8_t merge_buf[I2C_MAX_MSG_LEN];
+				struct i2c_msg tmp_msg;
+
+				memcpy(&merge_buf[0], msgs[0].buf, msgs[0].len);
+				memcpy(&merge_buf[msgs[0].len], msgs[1].buf, msgs[1].len);
+				tmp_msg.buf = &merge_buf[0];
+				tmp_msg.flags = I2C_MSG_WRITE | I2C_MSG_STOP;
+				tmp_msg.len = (uint8_t)tmp_len;
+				/* Merge 2 msgs into 1 msg */
+				msgs[0] = tmp_msg;
+				num_msgs = 1;
+			} else {
+				LOG_DBG("messages are too large to merge");
+			}
+		}
+	}
+
+	current = msgs;
+	ret = 0;
+
+	/* Check for validity of all messages before transfer */
+	for (int i = 1; i <= num_msgs; i++) {
+		if (i < num_msgs) {
+			next = current + 1;
+
+			/*
+			 * Restart condition between messages
+			 * of different directions is required
+			 */
+			if (OPERATION(current) != OPERATION(next)) {
+				if (!(next->flags & I2C_MSG_RESTART)) {
+					LOG_ERR("Restart condition between messages of "
+						"different directions is required."
+						"Current/Total: [%d/%d]",
+						i, num_msgs);
+					ret = -EIO;
+					break;
+				}
+			}
+
+			/* Stop condition is only allowed on last message */
+			if (current->flags & I2C_MSG_STOP) {
+				LOG_ERR("Invalid stop flag. Stop condition is only allowed on "
+					"last message. "
+					"Current/Total: [%d/%d]",
+					i, num_msgs);
+				ret = -EIO;
+				break;
+			}
+		} else {
+			current->flags |= I2C_MSG_STOP;
+		}
+
+		current++;
+	}
+
+	if (ret) {
+		return ret;
+	}
+
+	k_sem_take(&data->bus_lock, K_FOREVER);
+
+	/* Set destination address with configured address mode before sending msg. */
+
+	i2c_master_addr_mode_t addr_mode = 0;
+
+	if (I2C_MSG_ADDR_10_BITS & data->dev_config) {
+		addr_mode = I2C_MASTER_ADDR_MODE_10BIT;
+	} else {
+		addr_mode = I2C_MASTER_ADDR_MODE_7BIT;
+	}
+
+	R_SCI_B_I2C_SlaveAddressSet(&data->ctrl, addr, addr_mode);
+
+	/* Process input `msgs`. */
+
+	current = msgs;
+
+	while (num_msgs > 0) {
+		if (num_msgs > 1) {
+			next = current + 1;
+		} else {
+			next = NULL;
+		}
+
+		if (current->flags & I2C_MSG_READ) {
+			fsp_err = R_SCI_B_I2C_Read(&data->ctrl, current->buf, current->len,
+						   next != NULL && (next->flags & I2C_MSG_RESTART));
+		} else {
+			fsp_err =
+				R_SCI_B_I2C_Write(&data->ctrl, current->buf, current->len,
+						  next != NULL && (next->flags & I2C_MSG_RESTART));
+		}
+
+		if (fsp_err != FSP_SUCCESS) {
+			switch (fsp_err) {
+			case FSP_ERR_INVALID_SIZE:
+				LOG_ERR("Provided number of bytes more than uint16_t size "
+					"(65535) while DTC is used for data transfer.");
+				break;
+			case FSP_ERR_IN_USE:
+				LOG_ERR("Bus busy condition. Another transfer was in progress.");
+				break;
+			default:
+				LOG_ERR("Unknown error.");
+				break;
+			}
+
+			ret = -EIO;
+			goto RELEASE_BUS;
+		}
+
+		/* Wait for callback to return. */
+		k_sem_take(&data->complete_sem, K_FOREVER);
+
+		/* Handle event msg from callback. */
+		switch (data->event) {
+		case I2C_MASTER_EVENT_ABORTED:
+			LOG_ERR("%s failed.", (current->flags & I2C_MSG_READ) ? "Read" : "Write");
+			ret = -EIO;
+			goto RELEASE_BUS;
+		case I2C_MASTER_EVENT_RX_COMPLETE:
+			break;
+		case I2C_MASTER_EVENT_TX_COMPLETE:
+			break;
+		default:
+			break;
+		}
+
+		current++;
+		num_msgs--;
+	}
+
+RELEASE_BUS:
+	k_sem_give(&data->bus_lock);
+
+	return ret;
+}
+
+#ifdef CONFIG_I2C_CALLBACK
+
+static void renesas_ra_sci_b_i2c_async_done(const struct device *dev, struct sci_b_i2c_data *data,
+					    int result)
+{
+
+	i2c_callback_t cb = data->cb;
+	void *p_context = data->p_context;
+
+	data->msg_idx = 0;
+	data->msgs = NULL;
+	data->num_msgs = 0;
+	data->cb = NULL;
+	data->p_context = NULL;
+	data->addr = 0;
+
+	k_sem_give(&data->bus_lock);
+
+	/* Callback may wish to start another transfer */
+	cb(dev, result, p_context);
+}
+
+/* Start a transfer asynchronously */
+static void renesas_ra_sci_b_i2c_async_iter(const struct device *dev)
+{
+	struct sci_b_i2c_data *data = dev->data;
+	fsp_err_t fsp_err;
+	struct i2c_msg *current, *next;
+
+	struct i2c_msg *msg = &data->msgs[data->msg_idx];
+
+	/* Check for validity of all messages before transfer */
+	current = msg;
+	if (data->msg_idx < (data->num_msgs - 1)) {
+		next = current + 1;
+
+		/*
+		 * Restart condition between messages
+		 * of different directions is required
+		 */
+		if (OPERATION(current) != OPERATION(next)) {
+			if (!(next->flags & I2C_MSG_RESTART)) {
+				LOG_ERR("Restart condition between messages of "
+					"different directions is required."
+					"Current/Total: [%d/%d]",
+					data->msg_idx + 1, data->num_msgs);
+				renesas_ra_sci_b_i2c_async_done(dev, data, -EIO);
+				return;
+			}
+		}
+
+		if (current->flags & I2C_MSG_STOP) {
+			LOG_ERR("Invalid stop flag. Stop condition is only allowed on "
+				"last message. "
+				"Current/Total: [%d/%d]",
+				data->msg_idx + 1, data->num_msgs);
+			renesas_ra_sci_b_i2c_async_done(dev, data, -EIO);
+			return;
+		}
+	} else {
+		current->flags |= I2C_MSG_STOP;
+		next = NULL;
+	}
+
+	if (current->flags & I2C_MSG_READ) {
+		fsp_err = R_SCI_B_I2C_Read(&data->ctrl, current->buf, current->len,
+					   (next != NULL) && (next->flags & I2C_MSG_RESTART));
+	} else {
+		fsp_err = R_SCI_B_I2C_Write(&data->ctrl, current->buf, current->len,
+					    (next != NULL) && (next->flags & I2C_MSG_RESTART));
+	}
+
+	/* Return an error if the transfer didn't start successfully
+	 * e.g., if the bus was busy
+	 */
+	if (fsp_err != FSP_SUCCESS) {
+		switch (fsp_err) {
+		case FSP_ERR_INVALID_SIZE:
+			LOG_ERR("Provided number of bytes more than uint16_t size "
+				"(65535) while DTC is used for data transfer.");
+			break;
+		case FSP_ERR_IN_USE:
+			LOG_ERR("Bus busy condition. Another transfer was in progress.");
+			break;
+		default:
+			LOG_ERR("Unknown error.");
+			break;
+		}
+
+		R_SCI_B_I2C_Abort(&data->ctrl);
+		return;
+	}
+}
+
+static int renesas_ra_sci_b_i2c_transfer_cb(const struct device *dev, struct i2c_msg *msgs,
+					    uint8_t num_msgs, uint16_t addr, i2c_callback_t cb,
+					    void *p_context)
+{
+	struct sci_b_i2c_data *data = dev->data;
+
+	int res = k_sem_take(&data->bus_lock, K_NO_WAIT);
+
+	if (res != 0) {
+		return -EWOULDBLOCK;
+	}
+
+	data->msg_idx = 0;
+	data->msgs = msgs;
+	data->num_msgs = num_msgs;
+	data->addr = addr;
+	data->cb = cb;
+	data->p_context = p_context;
+
+	renesas_ra_sci_b_i2c_async_iter(dev);
+
+	return 0;
+}
+
+#endif /* CONFIG_I2C_CALLBACK */
+
+static void renesas_ra_sci_b_i2c_callback(i2c_master_callback_args_t *p_args)
+{
+	const struct device *dev = p_args->p_context;
+	struct sci_b_i2c_data *data = dev->data;
+
+#ifdef CONFIG_I2C_CALLBACK
+	if (data->cb != NULL) {
+		/* Async transfer */
+		if (p_args->event == I2C_MASTER_EVENT_ABORTED) {
+			R_SCI_B_I2C_Abort(&data->ctrl);
+			renesas_ra_sci_b_i2c_async_done(dev, data, -EIO);
+		} else if (data->msg_idx == data->num_msgs - 1) {
+			renesas_ra_sci_b_i2c_async_done(dev, data, 0);
+		} else {
+			data->msg_idx++;
+			renesas_ra_sci_b_i2c_async_iter(dev);
+		}
+		return;
+	}
+#endif /* CONFIG_I2C_CALLBACK */
+
+	data->event = p_args->event;
+
+	k_sem_give(&data->complete_sem);
+}
+
+static int renesas_ra_sci_b_i2c_init(const struct device *dev)
+{
+	const struct sci_b_i2c_config *config = dev->config;
+	struct sci_b_i2c_data *data = (struct sci_b_i2c_data *)dev->data;
+	fsp_err_t fsp_err;
+	int ret;
+
+	data->dev_config |= I2C_MODE_CONTROLLER;
+
+	/* Configure dt provided device signals when available */
+	ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+
+	if (ret < 0) {
+		LOG_ERR("Pinctrl config failed.");
+		return ret;
+	}
+
+	k_sem_init(&data->bus_lock, 1, 1);
+	k_sem_init(&data->complete_sem, 0, 1);
+
+	switch (data->i2c_config.rate) {
+	case I2C_MASTER_RATE_STANDARD:
+		calc_sci_b_iic_clock_setting(dev, data->i2c_config.rate,
+					     &data->ext_cfg.clock_settings);
+		data->i2c_config.p_extend = &data->ext_cfg;
+		data->dev_config |= I2C_SPEED_SET(I2C_SPEED_STANDARD);
+		break;
+	case I2C_MASTER_RATE_FAST:
+		calc_sci_b_iic_clock_setting(dev, data->i2c_config.rate,
+					     &data->ext_cfg.clock_settings);
+		data->i2c_config.p_extend = &data->ext_cfg;
+		data->dev_config |= I2C_SPEED_SET(I2C_SPEED_FAST);
+		break;
+	default:
+		LOG_ERR("Invalid I2C speed rate: %d", data->i2c_config.rate);
+		return -ENOTSUP;
+	}
+
+#ifdef CONFIG_I2C_RENESAS_RA_SCI_B_DTC
+	data->i2c_config.p_transfer_rx = &data->rx_transfer;
+	data->i2c_config.p_transfer_tx = &data->tx_transfer;
+#endif
+
+	fsp_err = R_SCI_B_I2C_Open(&data->ctrl, &data->i2c_config);
+
+	if (fsp_err != FSP_SUCCESS) {
+		LOG_ERR("I2C init failed.");
+	}
+
+	config->irq_config_func(dev);
+
+	return 0;
+};
+
+static void calc_sci_b_iic_clock_setting(const struct device *dev, const uint32_t fsp_i2c_rate,
+					 sci_b_i2c_clock_settings_t *clk_cfg)
+{
+	const struct sci_b_i2c_config *config = dev->config;
+
+	uint32_t bitrate = 0;
+	bool use_mddr = clk_cfg->bitrate_modulation;
+
+	uint32_t divisor = 0;
+	uint32_t divisor_bitrate_multiple = 0;
+	uint32_t brr = 0;
+	int32_t cks = 0;
+	uint32_t delta_error = 0;
+
+	uint32_t sda_delay_clock = 0;
+	uint32_t sda_delay_counts = 0;
+	uint32_t temp_mddr;
+	uint32_t calculated_bitrate = 0;
+
+	uint32_t mddr = MDDR_DISABLE;
+
+	uint32_t peripheral_clock = R_FSP_SciClockHzGet();
+
+	uint32_t sda_delay_ns = config->sda_output_delay;
+
+	if (I2C_MASTER_RATE_FAST == fsp_i2c_rate) {
+		bitrate = 400000;
+	} else {
+		bitrate = 100000;
+	}
+
+	for (uint32_t i = 0; i <= 3; i++) {
+
+		divisor_bitrate_multiple = (1 << (2 * (i + 1))) * 8;
+		divisor = divisor_bitrate_multiple * bitrate;
+
+		/* Calculate BRR so that the bit rate is the largest possible value less than or
+		 * equal to the desired bitrate.
+		 */
+		brr = (uint32_t)ceil(((double)peripheral_clock) / divisor - 1);
+		if (brr <= 255) {
+			break;
+		}
+		cks++;
+	}
+	calculated_bitrate = (uint32_t)((double)peripheral_clock) /
+			     (divisor_bitrate_multiple * (256 / mddr) * (brr + 1));
+	delta_error = bitrate - calculated_bitrate;
+
+	if (use_mddr) {
+		for (uint32_t temp_brr = brr; temp_brr > 0; temp_brr--) {
+
+			/** Calculate the MDDR (M) value if bit rate modulation is enabled,
+			 * The formula to calculate MBBR (from the M and N relationship given in the
+			 * hardware manual) is as follows and it must be between 128 and 256. MDDR =
+			 * ((divisor * 256) * (BRR + 1)) / PCLK
+			 */
+			temp_mddr = (uint32_t)floor(((double)divisor) * 256 * (temp_brr + 1) /
+						    peripheral_clock);
+
+			/* The maximum value that could result from the calculation above is 256,
+			 * which is a valid MDDR value, so only the lower bound is checked.
+			 */
+			if (temp_mddr < 128) {
+				break;
+			}
+
+			/* The maximum for MDDR is 256 (MDDR unused). */
+			if (temp_mddr > 256) {
+				continue;
+			}
+
+			calculated_bitrate =
+				(uint32_t)(peripheral_clock /
+					   (divisor_bitrate_multiple * (256 / ((double)temp_mddr)) *
+					    (temp_brr + 1)));
+
+			/** If the bit rate error is less than the previous lowest bit rate error,
+			 * then store these settings as the best value.
+			 */
+			if ((bitrate - calculated_bitrate) < delta_error) {
+				delta_error = bitrate - calculated_bitrate;
+				brr = temp_brr;
+				mddr = temp_mddr;
+			}
+		}
+	}
+
+	/* If MDDR == 256, disable bitrate modulation and set MDDR to a valid value. */
+	if (mddr == 256) {
+		mddr = 255;
+		use_mddr = false;
+	}
+
+	/* Calculate SDA delay. */
+	sda_delay_clock = peripheral_clock >> cks;
+	sda_delay_counts = (uint32_t)ceil(((double)sda_delay_ns) * sda_delay_clock / 1000000000);
+	if (sda_delay_counts > 31) {
+		sda_delay_counts = 31;
+	}
+
+	clk_cfg->clk_divisor_value = (uint8_t)cks;
+	clk_cfg->brr_value = (uint8_t)brr;
+	clk_cfg->mddr_value = (uint8_t)mddr;
+	clk_cfg->bitrate_modulation = use_mddr;
+	clk_cfg->cycles_value = (uint8_t)sda_delay_counts;
+}
+
+static const struct i2c_driver_api renesas_ra_sci_b_i2c_driver_api = {
+	.configure = renesas_ra_sci_b_i2c_configure,
+	.get_config = renesas_ra_sci_b_i2c_get_config,
+	.transfer = renesas_ra_sci_b_i2c_transfer,
+#ifdef CONFIG_I2C_CALLBACK
+	.transfer_cb = renesas_ra_sci_b_i2c_transfer_cb,
+#endif /* CONFIG_I2C_CALLBACK */
+};
+
+#define _ELC_EVENT_SCI_RXI(channel) ELC_EVENT_SCI##channel##_RXI
+#define _ELC_EVENT_SCI_TXI(channel) ELC_EVENT_SCI##channel##_TXI
+#define _ELC_EVENT_SCI_TEI(channel) ELC_EVENT_SCI##channel##_TEI
+
+#define ELC_EVENT_SCI_RXI(channel) _ELC_EVENT_SCI_RXI(channel)
+#define ELC_EVENT_SCI_TXI(channel) _ELC_EVENT_SCI_TXI(channel)
+#define ELC_EVENT_SCI_TEI(channel) _ELC_EVENT_SCI_TEI(channel)
+
+#ifndef CONFIG_I2C_RENESAS_RA_SCI_B_DTC
+#define SCI_B_I2C_DTC_INIT(index)
+#define RXI_TRANSFER(index)
+#else
+#define SCI_B_I2C_DTC_INIT(index)                                                                  \
+	.rx_transfer_info =                                                                        \
+		{                                                                                  \
+			.transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, \
+			.transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_DESTINATION,  \
+			.transfer_settings_word_b.irq = TRANSFER_IRQ_END,                          \
+			.transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,       \
+			.transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_FIXED,        \
+			.transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE,                     \
+			.transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL,                     \
+			.p_dest = (void *)NULL,                                                    \
+			.p_src = (void const *)NULL,                                               \
+			.num_blocks = 0,                                                           \
+			.length = 0,                                                               \
+	},                                                                                         \
+	.rx_transfer_cfg_extend = {.activation_source =                                            \
+					   DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq)},       \
+	.rx_transfer_cfg =                                                                         \
+		{                                                                                  \
+			.p_info = &sci_b_i2c_data_##index.rx_transfer_info,                        \
+			.p_extend = &sci_b_i2c_data_##index.rx_transfer_cfg_extend,                \
+	},                                                                                         \
+	.rx_transfer =                                                                             \
+		{                                                                                  \
+			.p_ctrl = &sci_b_i2c_data_##index.rx_transfer_ctrl,                        \
+			.p_cfg = &sci_b_i2c_data_##index.rx_transfer_cfg,                          \
+			.p_api = &g_transfer_on_dtc,                                               \
+	},                                                                                         \
+	.tx_transfer_info =                                                                        \
+		{                                                                                  \
+			.transfer_settings_word_b.dest_addr_mode = TRANSFER_ADDR_MODE_FIXED,       \
+			.transfer_settings_word_b.repeat_area = TRANSFER_REPEAT_AREA_SOURCE,       \
+			.transfer_settings_word_b.irq = TRANSFER_IRQ_END,                          \
+			.transfer_settings_word_b.chain_mode = TRANSFER_CHAIN_MODE_DISABLED,       \
+			.transfer_settings_word_b.src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED,  \
+			.transfer_settings_word_b.size = TRANSFER_SIZE_1_BYTE,                     \
+			.transfer_settings_word_b.mode = TRANSFER_MODE_NORMAL,                     \
+			.p_dest = (void *)NULL,                                                    \
+			.p_src = (void const *)NULL,                                               \
+			.num_blocks = 0,                                                           \
+			.length = 0,                                                               \
+	},                                                                                         \
+	.tx_transfer_cfg_extend = {.activation_source =                                            \
+					   DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq)},       \
+	.tx_transfer_cfg =                                                                         \
+		{                                                                                  \
+			.p_info = &sci_b_i2c_data_##index.tx_transfer_info,                        \
+			.p_extend = &sci_b_i2c_data_##index.tx_transfer_cfg_extend,                \
+	},                                                                                         \
+	.tx_transfer = {                                                                           \
+		.p_ctrl = &sci_b_i2c_data_##index.tx_transfer_ctrl,                                \
+		.p_cfg = &sci_b_i2c_data_##index.tx_transfer_cfg,                                  \
+		.p_api = &g_transfer_on_dtc,                                                       \
+	},
+
+#define RXI_TRANSFER(index)                                                                        \
+	/* rxi */                                                                                  \
+	R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq)] =                            \
+		ELC_EVENT_SCI_RXI(DT_INST_PROP(index, channel));                                   \
+	IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq),                               \
+		    DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, priority), sci_b_i2c_rxi_isr,       \
+		    DEVICE_DT_INST_GET(index), 0);                                                 \
+	irq_enable(DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq));
+#endif
+
+#define SCI_B_I2C_RA_INIT(index)                                                                   \
+	static void renesas_ra_sci_b_i2c_irq_config_func##index(const struct device *dev)          \
+	{                                                                                          \
+		RXI_TRANSFER(index)                                                                \
+                                                                                                   \
+		/* txi */                                                                          \
+		R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq)] =                    \
+			ELC_EVENT_SCI_TXI(DT_INST_PROP(index, channel));                           \
+		IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq),                       \
+			    DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, priority),                  \
+			    sci_b_i2c_txi_isr, DEVICE_DT_INST_GET(index), 0);                      \
+		irq_enable(DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq));                       \
+                                                                                                   \
+		/* tei */                                                                          \
+		R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq)] =                    \
+			ELC_EVENT_SCI_TEI(DT_INST_PROP(index, channel));                           \
+		IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq),                       \
+			    DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, priority),                  \
+			    sci_b_i2c_tei_isr, DEVICE_DT_INST_GET(index), 0);                      \
+		irq_enable(DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq));                       \
+	}                                                                                          \
+	PINCTRL_DT_DEFINE(DT_INST_PARENT(index));                                                  \
+                                                                                                   \
+	static const struct sci_b_i2c_config sci_b_i2c_config_##index = {                          \
+		.pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST_PARENT(index)),                          \
+		.irq_config_func = renesas_ra_sci_b_i2c_irq_config_func##index,                    \
+		.sda_output_delay = DT_INST_PROP(index, sda_output_delay),                         \
+	};                                                                                         \
+	static struct sci_b_i2c_data sci_b_i2c_data_##index = {                                    \
+		.i2c_config =                                                                      \
+			{                                                                          \
+				.channel = DT_INST_PROP(index, channel),                           \
+				.slave = 0,                                                        \
+				.rate = I2C_MASTER_RATE_STANDARD,                                  \
+				.addr_mode = I2C_MASTER_ADDR_MODE_7BIT,                            \
+				.ipl = DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, priority),       \
+				.rxi_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq),        \
+				.txi_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq),        \
+				.tei_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq),        \
+				.p_callback = renesas_ra_sci_b_i2c_callback,                       \
+				.p_context = DEVICE_DT_GET(DT_DRV_INST(index)),                    \
+			},                                                                         \
+		.ext_cfg =                                                                         \
+			{                                                                          \
+				.clock_settings.snfr_value =                                       \
+					DT_INST_PROP(index, noise_filter_clock_select),            \
+				.clock_settings.bitrate_modulation = DT_INST_NODE_HAS_PROP(        \
+					DT_DRV_INST(index), bit_rate_modulation),                  \
+				.clock_settings.clock_source = SCI_B_I2C_CLOCK_SOURCE_SCISPICLK,   \
+			},                                                                         \
+		SCI_B_I2C_DTC_INIT(index)};                                                        \
+	I2C_DEVICE_DT_INST_DEFINE(index, renesas_ra_sci_b_i2c_init, NULL, &sci_b_i2c_data_##index, \
+				  &sci_b_i2c_config_##index, POST_KERNEL,                          \
+				  CONFIG_I2C_INIT_PRIORITY, &renesas_ra_sci_b_i2c_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(SCI_B_I2C_RA_INIT)
diff --git a/drivers/i2c/i2c_renesas_rz_riic.c b/drivers/i2c/i2c_renesas_rz_riic.c
new file mode 100644
index 00000000000..8a43561ef59
--- /dev/null
+++ b/drivers/i2c/i2c_renesas_rz_riic.c
@@ -0,0 +1,539 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_rz_riic
+
+#include <math.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <instances/rzg/r_riic_master.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(renesas_rz_riic);
+
+typedef void (*init_func_t)(const struct device *dev);
+
+struct i2c_rz_riic_config {
+	const struct pinctrl_dev_config *pin_config;
+	i2c_master_cfg_t *fsp_cfg;
+	riic_master_extended_cfg_t *riic_master_ext_cfg;
+	const i2c_master_api_t *fsp_api;
+	double rise_time_s;
+	double fall_time_s;
+	double duty_cycle_percent;
+};
+
+struct i2c_rz_riic_data {
+	i2c_master_ctrl_t *fsp_ctrl;
+	struct k_mutex bus_mutex;
+	struct k_sem complete_sem;
+	i2c_master_event_t event;
+	uint32_t dev_config;
+};
+
+/* IIC master clock setting calculation function. */
+static void calc_riic_master_clock_setting(const struct device *dev, const uint32_t fsp_i2c_rate,
+					   iic_master_clock_settings_t *clk_cfg);
+
+/* FSP interruption handlers. */
+void riic_master_rxi_isr(void);
+void riic_master_txi_isr(void);
+void riic_master_tei_isr(void);
+void riic_master_naki_isr(void);
+void riic_master_sti_isr(void);
+void riic_master_spi_isr(void);
+void riic_master_ali_isr(void);
+void riic_master_tmoi_isr(void);
+
+struct rz_riic_master_bitrate {
+	uint32_t bitrate;
+	uint32_t duty;
+	uint32_t divider;
+	uint32_t brl;
+	uint32_t brh;
+	double duty_error_percent;
+};
+
+static int i2c_rz_riic_configure(const struct device *dev, uint32_t dev_config)
+{
+	const struct i2c_rz_riic_config *config = dev->config;
+	struct i2c_rz_riic_data *data = dev->data;
+
+	if (!(dev_config & I2C_MODE_CONTROLLER)) {
+		LOG_ERR("Only I2C Master mode supported.");
+		return -EIO;
+	}
+
+	switch (I2C_SPEED_GET(dev_config)) {
+	case I2C_SPEED_STANDARD:
+		config->fsp_cfg->rate = I2C_MASTER_RATE_STANDARD;
+		break;
+	case I2C_SPEED_FAST:
+		config->fsp_cfg->rate = I2C_MASTER_RATE_FAST;
+		break;
+	case I2C_SPEED_FAST_PLUS:
+		config->fsp_cfg->rate = I2C_MASTER_RATE_FASTPLUS;
+		break;
+	default:
+		LOG_ERR("%s: Invalid I2C speed rate flag: %d", __func__, I2C_SPEED_GET(dev_config));
+		return -EIO;
+	}
+
+	/* Recalc clock setting after updating config. */
+	calc_riic_master_clock_setting(dev, config->fsp_cfg->rate,
+				       &config->riic_master_ext_cfg->clock_settings);
+
+	config->fsp_api->close(data->fsp_ctrl);
+	config->fsp_api->open(data->fsp_ctrl, config->fsp_cfg);
+
+	/* save current devconfig. */
+	data->dev_config = dev_config;
+
+	return 0;
+}
+
+static int i2c_rz_riic_get_config(const struct device *dev, uint32_t *dev_config)
+{
+	struct i2c_rz_riic_data *data = (struct i2c_rz_riic_data *const)dev->data;
+	*dev_config = data->dev_config;
+
+	return 0;
+}
+
+#define OPERATION(msg) (((struct i2c_msg *)msg)->flags & I2C_MSG_RW_MASK)
+
+static int i2c_rz_riic_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
+				uint16_t addr)
+{
+	const struct i2c_rz_riic_config *config = dev->config;
+	struct i2c_rz_riic_data *data = (struct i2c_rz_riic_data *const)dev->data;
+	struct i2c_msg *current, *next;
+	fsp_err_t err = FSP_SUCCESS;
+	int ret = 0;
+
+	if (!num_msgs) {
+		return 0;
+	}
+
+	/* Check for validity of all messages before transfer */
+	current = msgs;
+
+	/*
+	 * Set I2C_MSG_RESTART flag on first message in order to send start
+	 * condition
+	 */
+	current->flags |= I2C_MSG_RESTART;
+
+	for (int i = 1; i <= num_msgs; i++) {
+		if (i < num_msgs) {
+			next = current + 1;
+
+			/*
+			 * Restart condition between messages
+			 * of different directions is required
+			 */
+			if (OPERATION(current) != OPERATION(next)) {
+				if (!(next->flags & I2C_MSG_RESTART)) {
+					LOG_ERR("%s: Restart condition between messages of "
+						"different directions is required."
+						"Current/Total: [%d/%d]",
+						__func__, i, num_msgs);
+					ret = -EIO;
+					break;
+				}
+			}
+
+			/* Stop condition is only allowed on last message */
+			if (current->flags & I2C_MSG_STOP) {
+				LOG_ERR("%s: Invalid stop flag. Stop condition is only allowed on "
+					"last message. "
+					"Current/Total: [%d/%d]",
+					__func__, i, num_msgs);
+				ret = -EIO;
+				break;
+			}
+		} else {
+			current->flags |= I2C_MSG_STOP;
+		}
+
+		current++;
+	}
+
+	if (ret) {
+		return ret;
+	}
+
+	k_mutex_lock(&data->bus_mutex, K_FOREVER);
+
+	/* Set destination address with configured address mode before sending msg. */
+
+	i2c_master_addr_mode_t addr_mode = 0;
+
+	if (I2C_MSG_ADDR_10_BITS & data->dev_config) {
+		addr_mode = I2C_MASTER_ADDR_MODE_10BIT;
+	} else {
+		addr_mode = I2C_MASTER_ADDR_MODE_7BIT;
+	}
+
+	config->fsp_api->slaveAddressSet(data->fsp_ctrl, addr, addr_mode);
+
+	/* Process input `msgs`. */
+
+	current = msgs;
+
+	while (num_msgs > 0) {
+		if (num_msgs > 1) {
+			next = current + 1;
+		} else {
+			next = NULL;
+		}
+
+		if (current->flags & I2C_MSG_READ) {
+			err = config->fsp_api->read(data->fsp_ctrl, current->buf, current->len,
+						    next != NULL &&
+							    (next->flags & I2C_MSG_RESTART));
+		} else {
+			err = config->fsp_api->write(data->fsp_ctrl, current->buf, current->len,
+						     next != NULL &&
+							     (next->flags & I2C_MSG_RESTART));
+		}
+
+		if (err != FSP_SUCCESS) {
+			switch (err) {
+			case FSP_ERR_IN_USE:
+				LOG_ERR("%s: Bus busy condition. Another transfer was in progress.",
+					__func__);
+				break;
+			default:
+				/* Should not reach here. */
+				LOG_ERR("%s: Unknown error. FSP_ERR=%d\n", __func__, err);
+				break;
+			}
+
+			ret = -EIO;
+			goto RELEASE_BUS;
+		}
+
+		/* Wait for callback to return. */
+		k_sem_take(&data->complete_sem, K_FOREVER);
+
+		/* Handle event msg from callback. */
+		switch (data->event) {
+		case I2C_MASTER_EVENT_ABORTED:
+			LOG_ERR("%s: %s failed.", __func__,
+				(current->flags & I2C_MSG_READ) ? "Read" : "Write");
+			ret = -EIO;
+			goto RELEASE_BUS;
+		case I2C_MASTER_EVENT_RX_COMPLETE:
+			break;
+		case I2C_MASTER_EVENT_TX_COMPLETE:
+			break;
+		default:
+			break;
+		}
+
+		current++;
+		num_msgs--;
+	}
+
+RELEASE_BUS:
+	k_mutex_unlock(&data->bus_mutex);
+
+	return ret;
+}
+
+static void i2c_rz_riic_callback(i2c_master_callback_args_t *p_args)
+{
+	const struct device *dev = p_args->p_context;
+	struct i2c_rz_riic_data *data = dev->data;
+
+	data->event = p_args->event;
+
+	k_sem_give(&data->complete_sem);
+}
+
+static int i2c_rz_riic_init(const struct device *dev)
+{
+	const struct i2c_rz_riic_config *config = dev->config;
+	struct i2c_rz_riic_data *data = dev->data;
+	fsp_err_t err = FSP_SUCCESS;
+	int ret = 0;
+
+	/* Configure dt provided device signals when available */
+	if (!config->pin_config) {
+		ret = pinctrl_apply_state(config->pin_config, PINCTRL_STATE_DEFAULT);
+
+		if (ret < 0) {
+			LOG_ERR("%s: pinctrl config failed.", __func__);
+			return ret;
+		}
+	}
+
+	k_mutex_init(&data->bus_mutex);
+	k_sem_init(&data->complete_sem, 0, 1);
+
+	switch (config->fsp_cfg->rate) {
+	case I2C_MASTER_RATE_STANDARD:
+	case I2C_MASTER_RATE_FAST:
+	case I2C_MASTER_RATE_FASTPLUS:
+		calc_riic_master_clock_setting(dev, config->fsp_cfg->rate,
+					       &config->riic_master_ext_cfg->clock_settings);
+		config->riic_master_ext_cfg->timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT;
+		config->riic_master_ext_cfg->timeout_scl_low = IIC_MASTER_TIMEOUT_SCL_LOW_ENABLED;
+		break;
+	default:
+		LOG_ERR("%s: Invalid I2C speed rate: %d", __func__, config->fsp_cfg->rate);
+		return -ENOTSUP;
+	}
+
+	err = config->fsp_api->open(data->fsp_ctrl, config->fsp_cfg);
+
+	if (err != FSP_SUCCESS) {
+		LOG_ERR("I2C initialization failed");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static void calc_riic_master_bitrate(const struct i2c_rz_riic_config *config,
+				     uint32_t total_brl_brh, uint32_t brh, uint32_t divider,
+				     struct rz_riic_master_bitrate *result)
+{
+	const uint32_t noise_filter_stages = config->riic_master_ext_cfg->noise_filter_stage;
+	const double rise_time_s = config->rise_time_s;
+	const double fall_time_s = config->fall_time_s;
+	const double requested_duty = config->duty_cycle_percent;
+	const uint32_t peripheral_clock = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_P0CLK);
+	uint32_t constant_add = 0;
+
+	/* A constant is added to BRL and BRH in all formulas. This constand is 3 + nf when CKS ==
+	 * 0, or 2 + nf when CKS != 0.
+	 */
+	if (divider == 0) {
+		constant_add = 3 + noise_filter_stages;
+	} else {
+		/* All dividers other than 0 use an addition of 2 + noise_filter_stages. */
+		constant_add = 2 + noise_filter_stages;
+	}
+
+	/* Converts all divided numbers to double to avoid data loss. */
+	double divided_p0 = (peripheral_clock >> divider);
+
+	result->bitrate =
+		1 / ((total_brl_brh + 2 * constant_add) / divided_p0 + rise_time_s + fall_time_s);
+	result->duty =
+		100 *
+		((rise_time_s + ((brh + constant_add) / divided_p0)) /
+		 (rise_time_s + fall_time_s + ((total_brl_brh + 2 * constant_add)) / divided_p0));
+	result->divider = divider;
+	result->brh = brh;
+	result->brl = total_brl_brh - brh;
+	result->duty_error_percent =
+		(result->duty > requested_duty ? (result->duty - requested_duty)
+					       : (requested_duty - result->duty)) /
+		requested_duty;
+}
+
+static void calc_riic_master_clock_setting(const struct device *dev, const uint32_t fsp_i2c_rate,
+					   iic_master_clock_settings_t *clk_cfg)
+{
+	const struct i2c_rz_riic_config *config = dev->config;
+	const uint32_t noise_filter_stages = config->riic_master_ext_cfg->noise_filter_stage;
+	const double rise_time_s = config->rise_time_s;
+	const double fall_time_s = config->fall_time_s;
+	const uint32_t requested_duty = config->duty_cycle_percent;
+	const uint32_t peripheral_clock = R_FSP_SystemClockHzGet(FSP_PRIV_CLOCK_P0CLK);
+
+	uint32_t requested_bitrate = 0;
+
+	switch (fsp_i2c_rate) {
+	case I2C_MASTER_RATE_STANDARD:
+	case I2C_MASTER_RATE_FAST:
+	case I2C_MASTER_RATE_FASTPLUS:
+		requested_bitrate = fsp_i2c_rate;
+		break;
+	default:
+		LOG_ERR("%s: Invalid I2C speed rate: %d", __func__, fsp_i2c_rate);
+		return;
+	}
+
+	/* Start with maximum possible bitrate. */
+	uint32_t min_brh = noise_filter_stages + 1;
+	uint32_t min_brl_brh = 2 * min_brh;
+	struct rz_riic_master_bitrate bitrate = {};
+
+	calc_riic_master_bitrate(config, min_brl_brh, min_brh, 0, &bitrate);
+
+	/* Start with the smallest divider because it gives the most resolution. */
+	uint32_t constant_add = 3 + noise_filter_stages;
+
+	for (int temp_divider = 0; temp_divider <= 7; ++temp_divider) {
+		if (1 == temp_divider) {
+			/* All dividers other than 0 use an addition of 2 + noise_filter_stages. */
+			constant_add = 2 + noise_filter_stages;
+		}
+
+		/* If the requested bitrate cannot be achieved with this divider, continue. */
+		double divided_p0 = (peripheral_clock >> temp_divider);
+		uint32_t total_brl_brh =
+			ceil(((1 / (double)requested_bitrate) - (rise_time_s + fall_time_s)) *
+				     divided_p0 -
+			     (2 * constant_add));
+
+		if ((total_brl_brh > 62) || (total_brl_brh < min_brl_brh)) {
+			continue;
+		}
+
+		uint32_t temp_brh = total_brl_brh * requested_duty / 100;
+
+		if (temp_brh < min_brh) {
+			temp_brh = min_brh;
+		}
+
+		/* Calculate the actual bitrate and duty cycle. */
+		struct rz_riic_master_bitrate temp_bitrate = {};
+
+		calc_riic_master_bitrate(config, total_brl_brh, temp_brh, temp_divider,
+					 &temp_bitrate);
+
+		/* Adjust duty cycle down if it helps. */
+		struct rz_riic_master_bitrate test_bitrate = temp_bitrate;
+
+		while (test_bitrate.duty > requested_duty) {
+			temp_brh -= 1;
+
+			if ((temp_brh < min_brh) || ((total_brl_brh - temp_brh) > 31)) {
+				break;
+			}
+
+			struct rz_riic_master_bitrate new_bitrate = {};
+
+			calc_riic_master_bitrate(config, total_brl_brh, temp_brh, temp_divider,
+						 &new_bitrate);
+
+			if (new_bitrate.duty_error_percent < temp_bitrate.duty_error_percent) {
+				temp_bitrate = new_bitrate;
+			} else {
+				break;
+			}
+		}
+
+		/* Adjust duty cycle up if it helps. */
+		while (test_bitrate.duty < requested_duty) {
+			++temp_brh;
+
+			if ((temp_brh > total_brl_brh) || (temp_brh > 31) ||
+			    ((total_brl_brh - temp_brh) < min_brh)) {
+				break;
+			}
+
+			struct rz_riic_master_bitrate new_bitrate = {};
+
+			calc_riic_master_bitrate(config, total_brl_brh, temp_brh, temp_divider,
+						 &new_bitrate);
+
+			if (new_bitrate.duty_error_percent < temp_bitrate.duty_error_percent) {
+				temp_bitrate = new_bitrate;
+			} else {
+				break;
+			}
+		}
+
+		if ((temp_bitrate.brh < 32) && (temp_bitrate.brl < 32)) {
+			/* Valid setting found. */
+			bitrate = temp_bitrate;
+			break;
+		}
+	}
+
+	clk_cfg->brl_value = bitrate.brl;
+	clk_cfg->brh_value = bitrate.brh;
+	clk_cfg->cks_value = bitrate.divider;
+}
+
+static DEVICE_API(i2c, i2c_rz_riic_driver_api) = {
+	.configure = i2c_rz_riic_configure,
+	.get_config = i2c_rz_riic_get_config,
+	.transfer = i2c_rz_riic_transfer,
+};
+
+#define I2C_RZG_IRQ_CONNECT(index, irq_name, isr)                                                  \
+	do {                                                                                       \
+		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, irq_name, irq),                             \
+			    DT_INST_IRQ_BY_NAME(index, irq_name, priority), isr,                   \
+			    DEVICE_DT_INST_GET(index), 0);                                         \
+		irq_enable(DT_INST_IRQ_BY_NAME(index, irq_name, irq));                             \
+	} while (0)
+
+#define I2C_RZG_CONFIG_FUNC(index)                                                                 \
+	I2C_RZG_IRQ_CONNECT(index, rxi, riic_master_rxi_isr);                                      \
+	I2C_RZG_IRQ_CONNECT(index, txi, riic_master_txi_isr);                                      \
+	I2C_RZG_IRQ_CONNECT(index, tei, riic_master_tei_isr);                                      \
+	I2C_RZG_IRQ_CONNECT(index, naki, riic_master_naki_isr);                                    \
+	I2C_RZG_IRQ_CONNECT(index, sti, riic_master_sti_isr);                                      \
+	I2C_RZG_IRQ_CONNECT(index, spi, riic_master_spi_isr);                                      \
+	I2C_RZG_IRQ_CONNECT(index, ali, riic_master_ali_isr);                                      \
+	I2C_RZG_IRQ_CONNECT(index, tmoi, riic_master_tmoi_isr);
+
+#define I2C_RZG_RIIC_INIT(index)                                                                   \
+	static const double RZG_RIIC_MASTER_DIV_TIME_NS = 1000000000;                              \
+                                                                                                   \
+	static riic_master_extended_cfg_t g_i2c_master##index##_extend = {                         \
+		.noise_filter_stage = DT_INST_PROP(index, noise_filter_stages),                    \
+		.naki_irq = DT_INST_IRQ_BY_NAME(index, naki, irq),                                 \
+		.sti_irq = DT_INST_IRQ_BY_NAME(index, sti, irq),                                   \
+		.spi_irq = DT_INST_IRQ_BY_NAME(index, spi, irq),                                   \
+		.ali_irq = DT_INST_IRQ_BY_NAME(index, ali, irq),                                   \
+		.tmoi_irq = DT_INST_IRQ_BY_NAME(index, tmoi, irq),                                 \
+	};                                                                                         \
+                                                                                                   \
+	static i2c_master_cfg_t g_i2c_master##index##_cfg = {                                      \
+		.channel = DT_INST_PROP(index, channel),                                           \
+		.rate = DT_INST_PROP(index, clock_frequency),                                      \
+		.slave = 0x00,                                                                     \
+		.addr_mode = I2C_MASTER_ADDR_MODE_7BIT,                                            \
+		.p_transfer_tx = NULL,                                                             \
+		.p_transfer_rx = NULL,                                                             \
+		.p_callback = i2c_rz_riic_callback,                                                \
+		.p_context = DEVICE_DT_GET(DT_DRV_INST(index)),                                    \
+		.rxi_irq = DT_INST_IRQ_BY_NAME(index, rxi, irq),                                   \
+		.txi_irq = DT_INST_IRQ_BY_NAME(index, txi, irq),                                   \
+		.tei_irq = DT_INST_IRQ_BY_NAME(index, tei, irq),                                   \
+		.ipl = DT_INST_IRQ_BY_NAME(index, rxi, priority),                                  \
+		.p_extend = &g_i2c_master##index##_extend,                                         \
+	};                                                                                         \
+                                                                                                   \
+	PINCTRL_DT_INST_DEFINE(index);                                                             \
+                                                                                                   \
+	static struct i2c_rz_riic_config i2c_rz_riic_config_##index = {                            \
+		.pin_config = PINCTRL_DT_INST_DEV_CONFIG_GET(index),                               \
+		.fsp_cfg = &g_i2c_master##index##_cfg,                                             \
+		.riic_master_ext_cfg = &g_i2c_master##index##_extend,                              \
+		.fsp_api = &g_i2c_master_on_iic,                                                   \
+		.rise_time_s = DT_INST_PROP(index, rise_time_ns) / RZG_RIIC_MASTER_DIV_TIME_NS,    \
+		.fall_time_s = DT_INST_PROP(index, fall_time_ns) / RZG_RIIC_MASTER_DIV_TIME_NS,    \
+		.duty_cycle_percent = DT_INST_PROP(index, duty_cycle_percent),                     \
+	};                                                                                         \
+                                                                                                   \
+	static iic_master_instance_ctrl_t g_i2c_master##index##_ctrl;                              \
+                                                                                                   \
+	static struct i2c_rz_riic_data i2c_rz_riic_data_##index = {                                \
+		.fsp_ctrl = (i2c_master_ctrl_t *)&g_i2c_master##index##_ctrl,                      \
+	};                                                                                         \
+                                                                                                   \
+	static int i2c_rz_riic_init_##index(const struct device *dev)                              \
+	{                                                                                          \
+		I2C_RZG_CONFIG_FUNC(index)                                                         \
+		return i2c_rz_riic_init(dev);                                                      \
+	};                                                                                         \
+                                                                                                   \
+	I2C_DEVICE_DT_INST_DEFINE(index, i2c_rz_riic_init_##index, NULL,                           \
+				  &i2c_rz_riic_data_##index, &i2c_rz_riic_config_##index,          \
+				  PRE_KERNEL_2, CONFIG_I2C_INIT_PRIORITY,                          \
+				  &i2c_rz_riic_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(I2C_RZG_RIIC_INIT)
diff --git a/drivers/i2c/i2c_rtio.c b/drivers/i2c/i2c_rtio.c
index d921f5604ef..a44e2e61fee 100644
--- a/drivers/i2c/i2c_rtio.c
+++ b/drivers/i2c/i2c_rtio.c
@@ -52,6 +52,47 @@ struct rtio_sqe *i2c_rtio_copy(struct rtio *r, struct rtio_iodev *iodev, const s
 	return sqe;
 }
 
+struct rtio_sqe *i2c_rtio_copy_reg_write_byte(struct rtio *r, struct rtio_iodev *iodev,
+					      uint8_t reg_addr, uint8_t data)
+{
+	uint8_t msg[2];
+
+	struct rtio_sqe *sqe = rtio_sqe_acquire(r);
+
+	if (sqe == NULL) {
+		rtio_sqe_drop_all(r);
+		return NULL;
+	}
+	msg[0] = reg_addr;
+	msg[1] = data;
+	rtio_sqe_prep_tiny_write(sqe, iodev, RTIO_PRIO_NORM, msg, sizeof(msg), NULL);
+	sqe->iodev_flags = RTIO_IODEV_I2C_STOP;
+	return sqe;
+}
+
+struct rtio_sqe *i2c_rtio_copy_reg_burst_read(struct rtio *r, struct rtio_iodev *iodev,
+					      uint8_t start_addr, void *buf, size_t num_bytes)
+{
+	struct rtio_sqe *sqe = rtio_sqe_acquire(r);
+
+	if (sqe == NULL) {
+		rtio_sqe_drop_all(r);
+		return NULL;
+	}
+	rtio_sqe_prep_tiny_write(sqe, iodev, RTIO_PRIO_NORM, &start_addr, 1, NULL);
+	sqe->flags |= RTIO_SQE_TRANSACTION;
+
+	sqe = rtio_sqe_acquire(r);
+	if (sqe == NULL) {
+		rtio_sqe_drop_all(r);
+		return NULL;
+	}
+	rtio_sqe_prep_read(sqe, iodev, RTIO_PRIO_NORM, buf, num_bytes, NULL);
+	sqe->iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART;
+
+	return sqe;
+}
+
 void i2c_rtio_init(struct i2c_rtio *ctx, const struct device *dev)
 {
 	k_sem_init(&ctx->lock, 1, 1);
diff --git a/drivers/i2c/i2c_sam0.c b/drivers/i2c/i2c_sam0.c
index 0f668448407..f28c65a359e 100644
--- a/drivers/i2c/i2c_sam0.c
+++ b/drivers/i2c/i2c_sam0.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
+ * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -18,6 +19,8 @@
 #include <zephyr/irq.h>
 LOG_MODULE_REGISTER(i2c_sam0, CONFIG_I2C_LOG_LEVEL);
 
+/* clang-format off */
+
 #include "i2c-priv.h"
 
 #ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
@@ -34,14 +37,10 @@ struct i2c_sam0_dev_config {
 	SercomI2cm *regs;
 	const struct pinctrl_dev_config *pcfg;
 	uint32_t bitrate;
-#ifdef MCLK
 	volatile uint32_t *mclk;
 	uint32_t mclk_mask;
-	uint16_t gclk_core_id;
-#else
-	uint32_t pm_apbcmask;
-	uint16_t gclk_clkctrl_id;
-#endif
+	uint32_t gclk_gen;
+	uint16_t gclk_id;
 	void (*irq_config_func)(const struct device *dev);
 
 #ifdef CONFIG_I2C_SAM0_DMA_DRIVEN
@@ -711,20 +710,17 @@ static int i2c_sam0_initialize(const struct device *dev)
 	SercomI2cm *i2c = cfg->regs;
 	int retval;
 
-#ifdef MCLK
-	/* Enable the GCLK */
-	GCLK->PCHCTRL[cfg->gclk_core_id].reg = GCLK_PCHCTRL_GEN_GCLK0 |
-					       GCLK_PCHCTRL_CHEN;
-	/* Enable SERCOM clock in MCLK */
 	*cfg->mclk |= cfg->mclk_mask;
-#else
-	/* Enable the GCLK */
-	GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 |
-			    GCLK_CLKCTRL_CLKEN;
 
-	/* Enable SERCOM clock in PM */
-	PM->APBCMASK.reg |= cfg->pm_apbcmask;
+#ifdef MCLK
+	GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_CHEN
+					| GCLK_PCHCTRL_GEN(cfg->gclk_gen);
+#else
+	GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
+			  | GCLK_CLKCTRL_GEN(cfg->gclk_gen)
+			  | GCLK_CLKCTRL_ID(cfg->gclk_id);
 #endif
+
 	/* Disable all I2C interrupts */
 	i2c->INTENCLR.reg = SERCOM_I2CM_INTENCLR_MASK;
 
@@ -801,7 +797,7 @@ static DEVICE_API(i2c, i2c_sam0_driver_api) = {
 
 #if DT_INST_IRQ_HAS_IDX(0, 3)
 #define I2C_SAM0_IRQ_HANDLER(n)						\
-static void i2c_sam0_irq_config_##n(const struct device *dev)			\
+static void i2c_sam0_irq_config_##n(const struct device *dev)		\
 {									\
 	SAM0_I2C_IRQ_CONNECT(n, 0);					\
 	SAM0_I2C_IRQ_CONNECT(n, 1);					\
@@ -810,21 +806,25 @@ static void i2c_sam0_irq_config_##n(const struct device *dev)			\
 }
 #else
 #define I2C_SAM0_IRQ_HANDLER(n)						\
-static void i2c_sam0_irq_config_##n(const struct device *dev)			\
+static void i2c_sam0_irq_config_##n(const struct device *dev)		\
 {									\
 	SAM0_I2C_IRQ_CONNECT(n, 0);					\
 }
 #endif
 
+#define ASSIGNED_CLOCKS_CELL_BY_NAME					\
+	ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_NAME
+
 #ifdef MCLK
 #define I2C_SAM0_CONFIG(n)						\
 static const struct i2c_sam0_dev_config i2c_sam0_dev_config_##n = {	\
 	.regs = (SercomI2cm *)DT_INST_REG_ADDR(n),			\
 	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
 	.bitrate = DT_INST_PROP(n, clock_frequency),			\
-	.mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(n),	\
-	.mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)),	\
-	.gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),\
+	.gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen),		\
+	.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id),		\
+	.mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n),		\
+	.mclk_mask = ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(n, bit),	\
 	.irq_config_func = &i2c_sam0_irq_config_##n,			\
 	I2C_SAM0_DMA_CHANNELS(n)					\
 }
@@ -834,8 +834,10 @@ static const struct i2c_sam0_dev_config i2c_sam0_dev_config_##n = {	\
 	.regs = (SercomI2cm *)DT_INST_REG_ADDR(n),			\
 	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
 	.bitrate = DT_INST_PROP(n, clock_frequency),			\
-	.pm_apbcmask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, pm, bit)),	\
-	.gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id),\
+	.gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen),		\
+	.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id),		\
+	.mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n),		\
+	.mclk_mask = ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(n, bit),	\
 	.irq_config_func = &i2c_sam0_irq_config_##n,			\
 	I2C_SAM0_DMA_CHANNELS(n)					\
 }
@@ -856,3 +858,5 @@ static const struct i2c_sam0_dev_config i2c_sam0_dev_config_##n = {	\
 	I2C_SAM0_IRQ_HANDLER(n)
 
 DT_INST_FOREACH_STATUS_OKAY(I2C_SAM0_DEVICE)
+
+/* clang-format on */
diff --git a/drivers/i2c/i2c_sbcon.c b/drivers/i2c/i2c_sbcon.c
index bf77fcdf352..2a28ae829d8 100644
--- a/drivers/i2c/i2c_sbcon.c
+++ b/drivers/i2c/i2c_sbcon.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2017 Linaro Ltd.
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,7 +18,7 @@
 #include <zephyr/device.h>
 #include <errno.h>
 #include <zephyr/drivers/i2c.h>
-
+#include <zephyr/drivers/pinctrl.h>
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(i2c_sbcon, CONFIG_I2C_LOG_LEVEL);
 
@@ -41,6 +42,7 @@ struct sbcon {
 struct i2c_sbcon_config {
 	struct sbcon *sbcon;		/* Address of hardware registers */
 	uint32_t bitrate;		/* I2C bus speed in Hz */
+	const struct pinctrl_dev_config *pctrl;
 };
 
 /* Driver instance data */
@@ -128,7 +130,14 @@ static int i2c_sbcon_init(const struct device *dev)
 	struct i2c_sbcon_context *context = dev->data;
 	const struct i2c_sbcon_config *config = dev->config;
 	int ret;
+	ret = pinctrl_apply_state(config->pctrl, PINCTRL_STATE_DEFAULT);
 
+	/* some pins are not available externally so,
+	 * ignore if there is no entry for them
+	 */
+	if (ret != -ENOENT) {
+		return ret;
+	}
 	i2c_bitbang_init(&context->bitbang, &io_fns, config->sbcon);
 
 	ret = i2c_bitbang_configure(&context->bitbang,
@@ -136,24 +145,24 @@ static int i2c_sbcon_init(const struct device *dev)
 	if (ret != 0) {
 		LOG_ERR("failed to configure I2C bitbang: %d", ret);
 	}
-
 	return ret;
 }
 
-#define	DEFINE_I2C_SBCON(_num)						\
-									\
-static struct i2c_sbcon_context i2c_sbcon_dev_data_##_num;		\
-									\
-static const struct i2c_sbcon_config i2c_sbcon_dev_cfg_##_num = {	\
-	.sbcon		= (void *)DT_INST_REG_ADDR(_num),		\
-	.bitrate	= DT_INST_PROP(_num, clock_frequency),		\
-};									\
-									\
-I2C_DEVICE_DT_INST_DEFINE(_num,						\
-	    i2c_sbcon_init,						\
-	    NULL,							\
-	    &i2c_sbcon_dev_data_##_num,					\
-	    &i2c_sbcon_dev_cfg_##_num,					\
-	    PRE_KERNEL_2, CONFIG_I2C_INIT_PRIORITY, &api);
+#define DEFINE_I2C_SBCON(_num)							\
+	PINCTRL_DT_INST_DEFINE(_num);						\
+	static struct i2c_sbcon_context i2c_sbcon_dev_data_##_num;		\
+										\
+	static const struct i2c_sbcon_config i2c_sbcon_dev_cfg_##_num = {	\
+		.sbcon		= (void *)DT_INST_REG_ADDR(_num),		\
+		.bitrate	= DT_INST_PROP(_num, clock_frequency),		\
+		.pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(_num),			\
+	};									\
+										\
+	I2C_DEVICE_DT_INST_DEFINE(_num,						\
+		    i2c_sbcon_init,						\
+		    NULL,							\
+		    &i2c_sbcon_dev_data_##_num,					\
+		    &i2c_sbcon_dev_cfg_##_num,					\
+		    PRE_KERNEL_2, CONFIG_I2C_INIT_PRIORITY, &api);
 
 DT_INST_FOREACH_STATUS_OKAY(DEFINE_I2C_SBCON)
diff --git a/drivers/i2c/i2c_sedi.c b/drivers/i2c/i2c_sedi.c
index e2646dc6b23..79744729a03 100644
--- a/drivers/i2c/i2c_sedi.c
+++ b/drivers/i2c/i2c_sedi.c
@@ -237,8 +237,8 @@ static void i2c_sedi_isr(const struct device *dev)
 		.cb_sedi = &i2c_sedi_callback_##n,                                                 \
 		.irq_config = &i2c_sedi_irq_config_##n,                                            \
 	};                                                                                         \
-	PM_DEVICE_DT_DEFINE(DT_NODELABEL(i2c##n), i2c_sedi_pm_action);                             \
-	I2C_DEVICE_DT_INST_DEFINE(n, i2c_sedi_init, PM_DEVICE_DT_GET(DT_NODELABEL(i2c##n)),        \
+	PM_DEVICE_DT_INST_DEFINE(n, i2c_sedi_pm_action);                                           \
+	I2C_DEVICE_DT_INST_DEFINE(n, i2c_sedi_init, PM_DEVICE_DT_INST_GET(n),                      \
 				  &i2c_sedi_data_##n, &i2c_sedi_config_##n, PRE_KERNEL_2,          \
 				  CONFIG_I2C_INIT_PRIORITY, &i2c_sedi_apis);
 
diff --git a/drivers/i2c/i2c_shell.c b/drivers/i2c/i2c_shell.c
index 10c1b912fc3..41f0518780c 100644
--- a/drivers/i2c/i2c_shell.c
+++ b/drivers/i2c/i2c_shell.c
@@ -5,6 +5,7 @@
  */
 
 #include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i3c.h>
 #include <zephyr/shell/shell.h>
 #include <stdlib.h>
 #include <string.h>
@@ -47,8 +48,7 @@ static int get_bytes_count_for_hex(char *arg)
  * https://manpages.debian.org/buster/i2c-tools/i2cdetect.8.en.html
  */
 /* i2c scan <device> */
-static int cmd_i2c_scan(const struct shell *shell_ctx,
-			size_t argc, char **argv)
+static int cmd_i2c_scan(const struct shell *sh, size_t argc, char **argv)
 {
 	const struct device *dev;
 	uint8_t cnt = 0, first = 0x04, last = 0x77;
@@ -56,18 +56,16 @@ static int cmd_i2c_scan(const struct shell *shell_ctx,
 	dev = shell_device_get_binding(argv[ARGV_DEV]);
 
 	if (!dev) {
-		shell_error(shell_ctx, "I2C: Device driver %s not found.",
-			    argv[ARGV_DEV]);
+		shell_error(sh, "I2C: Device driver %s not found.", argv[ARGV_DEV]);
 		return -ENODEV;
 	}
 
-	shell_print(shell_ctx,
-		    "     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f");
+	shell_print(sh, "     0  1  2  3  4  5  6  7  8  9  a  b  c  d  e  f");
 	for (uint8_t i = 0; i <= last; i += 16) {
-		shell_fprintf(shell_ctx, SHELL_NORMAL, "%02x: ", i);
+		shell_fprintf_normal(sh, "%02x: ", i);
 		for (uint8_t j = 0; j < 16; j++) {
 			if (i + j < first || i + j > last) {
-				shell_fprintf(shell_ctx, SHELL_NORMAL, "   ");
+				shell_fprintf_normal(sh, "   ");
 				continue;
 			}
 
@@ -79,47 +77,42 @@ static int cmd_i2c_scan(const struct shell *shell_ctx,
 			msgs[0].len = 0U;
 			msgs[0].flags = I2C_MSG_WRITE | I2C_MSG_STOP;
 			if (i2c_transfer(dev, &msgs[0], 1, i + j) == 0) {
-				shell_fprintf(shell_ctx, SHELL_NORMAL,
-					      "%02x ", i + j);
+				shell_fprintf_normal(sh, "%02x ", i + j);
 				++cnt;
 			} else {
-				shell_fprintf(shell_ctx, SHELL_NORMAL, "-- ");
+				shell_fprintf_normal(sh, "-- ");
 			}
 		}
-		shell_print(shell_ctx, "");
+		shell_print(sh, "");
 	}
 
-	shell_print(shell_ctx, "%u devices found on %s",
-		    cnt, argv[ARGV_DEV]);
+	shell_print(sh, "%u devices found on %s", cnt, argv[ARGV_DEV]);
 
 	return 0;
 }
 
 /* i2c recover <device> */
-static int cmd_i2c_recover(const struct shell *shell_ctx,
-			   size_t argc, char **argv)
+static int cmd_i2c_recover(const struct shell *sh, size_t argc, char **argv)
 {
 	const struct device *dev;
 	int err;
 
 	dev = shell_device_get_binding(argv[ARGV_DEV]);
 	if (!dev) {
-		shell_error(shell_ctx, "I2C: Device driver %s not found.",
-			    argv[1]);
+		shell_error(sh, "I2C: Device driver %s not found.", argv[1]);
 		return -ENODEV;
 	}
 
 	err = i2c_recover_bus(dev);
 	if (err) {
-		shell_error(shell_ctx, "I2C: Bus recovery failed (err %d)",
-			    err);
+		shell_error(sh, "I2C: Bus recovery failed (err %d)", err);
 		return err;
 	}
 
 	return 0;
 }
 
-static int i2c_write_from_buffer(const struct shell *shell_ctx,
+static int i2c_write_from_buffer(const struct shell *sh,
 		char *s_dev_name, char *s_dev_addr, char *s_reg_addr,
 		char **data, uint8_t data_length)
 {
@@ -137,8 +130,7 @@ static int i2c_write_from_buffer(const struct shell *shell_ctx,
 
 	dev = shell_device_get_binding(s_dev_name);
 	if (!dev) {
-		shell_error(shell_ctx, "I2C: Device driver %s not found.",
-			    s_dev_name);
+		shell_error(sh, "I2C: Device driver %s not found.", s_dev_name);
 		return -ENODEV;
 	}
 
@@ -150,7 +142,7 @@ static int i2c_write_from_buffer(const struct shell *shell_ctx,
 
 	if (data_length + reg_addr_bytes > MAX_I2C_BYTES) {
 		data_length = MAX_I2C_BYTES - reg_addr_bytes;
-		shell_info(shell_ctx, "Too many bytes provided, limit is %d",
+		shell_info(sh, "Too many bytes provided, limit is %d",
 			   MAX_I2C_BYTES - reg_addr_bytes);
 	}
 
@@ -163,8 +155,7 @@ static int i2c_write_from_buffer(const struct shell *shell_ctx,
 			buf + MAX_BYTES_FOR_REGISTER_INDEX - reg_addr_bytes,
 			reg_addr_bytes + data_length, dev_addr);
 	if (ret < 0) {
-		shell_error(shell_ctx, "Failed to write to device: %s",
-			    s_dev_addr);
+		shell_error(sh, "Failed to write to device: %s", s_dev_addr);
 		return -EIO;
 	}
 
@@ -172,24 +163,22 @@ static int i2c_write_from_buffer(const struct shell *shell_ctx,
 }
 
 /* i2c write <device> <dev_addr> <reg_addr> [<byte1>, ...] */
-static int cmd_i2c_write(const struct shell *shell_ctx,
-			 size_t argc, char **argv)
+static int cmd_i2c_write(const struct shell *sh, size_t argc, char **argv)
 {
-	return i2c_write_from_buffer(shell_ctx, argv[ARGV_DEV],
+	return i2c_write_from_buffer(sh, argv[ARGV_DEV],
 				     argv[ARGV_ADDR], argv[ARGV_REG],
 				     &argv[4], argc - 4);
 }
 
 /* i2c write_byte <device> <dev_addr> <reg_addr> <value> */
-static int cmd_i2c_write_byte(const struct shell *shell_ctx,
-			      size_t argc, char **argv)
+static int cmd_i2c_write_byte(const struct shell *sh, size_t argc, char **argv)
 {
-	return i2c_write_from_buffer(shell_ctx, argv[ARGV_DEV],
+	return i2c_write_from_buffer(sh, argv[ARGV_DEV],
 				     argv[ARGV_ADDR], argv[ARGV_REG],
 				     &argv[4], 1);
 }
 
-static int i2c_read_to_buffer(const struct shell *shell_ctx,
+static int i2c_read_to_buffer(const struct shell *sh,
 			      char *s_dev_name,
 			      char *s_dev_addr, char *s_reg_addr,
 			      uint8_t *buf, uint8_t buf_length)
@@ -200,8 +189,7 @@ static int i2c_read_to_buffer(const struct shell *shell_ctx,
 
 	dev = shell_device_get_binding(s_dev_name);
 	if (!dev) {
-		shell_error(shell_ctx, "I2C: Device driver %s not found.",
-			    s_dev_name);
+		shell_error(sh, "I2C: Device driver %s not found.", s_dev_name);
 		return -ENODEV;
 	}
 
@@ -224,8 +212,7 @@ static int i2c_read_to_buffer(const struct shell *shell_ctx,
 	}
 
 	if (ret < 0) {
-		shell_error(shell_ctx, "Failed to read from device: %s",
-			    s_dev_addr);
+		shell_error(sh, "Failed to read from device: %s", s_dev_addr);
 		return -EIO;
 	}
 
@@ -233,24 +220,22 @@ static int i2c_read_to_buffer(const struct shell *shell_ctx,
 }
 
 /* i2c read_byte <device> <dev_addr> <reg_addr> */
-static int cmd_i2c_read_byte(const struct shell *shell_ctx,
-			     size_t argc, char **argv)
+static int cmd_i2c_read_byte(const struct shell *sh, size_t argc, char **argv)
 {
 	uint8_t out;
 	int ret;
 
-
-	ret = i2c_read_to_buffer(shell_ctx, argv[ARGV_DEV],
+	ret = i2c_read_to_buffer(sh, argv[ARGV_DEV],
 				 argv[ARGV_ADDR], argv[ARGV_REG], &out, 1);
 	if (ret == 0) {
-		shell_print(shell_ctx, "Output: 0x%x", out);
+		shell_print(sh, "Output: 0x%x", out);
 	}
 
 	return ret;
 }
 
 /* i2c read <device> <dev_addr> <reg_addr> [<numbytes>] */
-static int cmd_i2c_read(const struct shell *shell_ctx, size_t argc, char **argv)
+static int cmd_i2c_read(const struct shell *sh, size_t argc, char **argv)
 {
 	uint8_t buf[MAX_I2C_BYTES];
 	int num_bytes;
@@ -265,18 +250,18 @@ static int cmd_i2c_read(const struct shell *shell_ctx, size_t argc, char **argv)
 		num_bytes = MAX_I2C_BYTES;
 	}
 
-	ret = i2c_read_to_buffer(shell_ctx, argv[ARGV_DEV],
+	ret = i2c_read_to_buffer(sh, argv[ARGV_DEV],
 				 argv[ARGV_ADDR], argv[ARGV_REG],
 				 buf, num_bytes);
 	if (ret == 0) {
-		shell_hexdump(shell_ctx, buf, num_bytes);
+		shell_hexdump(sh, buf, num_bytes);
 	}
 
 	return ret;
 }
 
 /* i2c direct_read <device> <dev_addr> [<numbytes>] */
-static int cmd_i2c_direct_read(const struct shell *shell_ctx, size_t argc, char **argv)
+static int cmd_i2c_direct_read(const struct shell *sh, size_t argc, char **argv)
 {
 	uint8_t buf[MAX_I2C_BYTES];
 	int num_bytes;
@@ -291,9 +276,9 @@ static int cmd_i2c_direct_read(const struct shell *shell_ctx, size_t argc, char
 		num_bytes = MAX_I2C_BYTES;
 	}
 
-	ret = i2c_read_to_buffer(shell_ctx, argv[ARGV_DEV], argv[ARGV_ADDR], NULL, buf, num_bytes);
+	ret = i2c_read_to_buffer(sh, argv[ARGV_DEV], argv[ARGV_ADDR], NULL, buf, num_bytes);
 	if (ret == 0) {
-		shell_hexdump(shell_ctx, buf, num_bytes);
+		shell_hexdump(sh, buf, num_bytes);
 	}
 
 	return ret;
@@ -302,7 +287,7 @@ static int cmd_i2c_direct_read(const struct shell *shell_ctx, size_t argc, char
 /* i2c speed <device> <speed>
  * For: speed see constants like I2C_SPEED_STANDARD
  */
-static int cmd_i2c_speed(const struct shell *shell_ctx, size_t argc, char **argv)
+static int cmd_i2c_speed(const struct shell *sh, size_t argc, char **argv)
 {
 	char *s_dev_name = argv[ARGV_DEV];
 	const struct device *dev;
@@ -312,8 +297,7 @@ static int cmd_i2c_speed(const struct shell *shell_ctx, size_t argc, char **argv
 
 	dev = shell_device_get_binding(s_dev_name);
 	if (!dev) {
-		shell_error(shell_ctx, "I2C: Device driver %s not found.",
-			    s_dev_name);
+		shell_error(sh, "I2C: Device driver %s not found.", s_dev_name);
 		return -ENODEV;
 	}
 
@@ -329,16 +313,24 @@ static int cmd_i2c_speed(const struct shell *shell_ctx, size_t argc, char **argv
 
 	ret = i2c_configure(dev, dev_config);
 	if (ret < 0) {
-		shell_error(shell_ctx, "I2C: Failed to configure device: %s",
-			    s_dev_name);
+		shell_error(sh, "I2C: Failed to configure device: %s", s_dev_name);
 		return -EIO;
 	}
 	return 0;
 }
 
+static bool device_is_i2c(const struct device *dev)
+{
+#ifdef CONFIG_I3C
+	return DEVICE_API_IS(i2c, dev) || DEVICE_API_IS(i3c, dev);
+#else
+	return DEVICE_API_IS(i2c, dev);
+#endif
+}
+
 static void device_name_get(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_lookup(idx, NULL);
+	const struct device *dev = shell_device_filter(idx, device_is_i2c);
 
 	entry->syntax = (dev != NULL) ? dev->name : NULL;
 	entry->handler = NULL;
diff --git a/drivers/i2c/i2c_sy1xx.c b/drivers/i2c/i2c_sy1xx.c
new file mode 100644
index 00000000000..300d800a8ba
--- /dev/null
+++ b/drivers/i2c/i2c_sy1xx.c
@@ -0,0 +1,406 @@
+/*
+ * Copyright (c) 2025 sensry.io
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT sensry_sy1xx_i2c
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(sy1xx_i2c, CONFIG_I2C_LOG_LEVEL);
+
+#include <soc.h>
+#include <udma.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/i2c.h>
+
+/** cmds for the udma of i2c */
+#define SY1XX_I2C_CMD_OFFSET  4
+#define SY1XX_I2C_CMD_START   (0x0 << SY1XX_I2C_CMD_OFFSET)
+#define SY1XX_I2C_CMD_STOP    (0x2 << SY1XX_I2C_CMD_OFFSET)
+#define SY1XX_I2C_CMD_RD_ACK  (0x4 << SY1XX_I2C_CMD_OFFSET)
+#define SY1XX_I2C_CMD_RD_NACK (0x6 << SY1XX_I2C_CMD_OFFSET)
+#define SY1XX_I2C_CMD_WR      (0x8 << SY1XX_I2C_CMD_OFFSET)
+#define SY1XX_I2C_CMD_WAIT    (0xA << SY1XX_I2C_CMD_OFFSET)
+#define SY1XX_I2C_CMD_RPT     (0xC << SY1XX_I2C_CMD_OFFSET)
+#define SY1XX_I2C_CMD_CFG     (0xE << SY1XX_I2C_CMD_OFFSET)
+#define SY1XX_I2C_CMD_WAIT_EV (0x1 << SY1XX_I2C_CMD_OFFSET)
+
+#define SY1XX_I2C_ADDR_WRITE (0x0)
+#define SY1XX_I2C_ADDR_READ  (0x1)
+
+enum sy1xx_i2c_speeds {
+	SY1XX_I2C_SPEED_STANDARD = 100000,
+	SY1XX_I2C_SPEED_FAST = 400000,
+	SY1XX_I2C_SPEED_FAST_PLUS = 1000000,
+	SY1XX_I2C_SPEED_HIGH = 3400000,
+	SY1XX_I2C_SPEED_ULTRA = 5000000,
+};
+
+#define DEVICE_MAX_BUFFER_SIZE (512)
+
+enum sy1xx_i2c_mode {
+	UNDEF,
+	READ,
+	WRITE,
+};
+
+struct sy1xx_i2c_dev_config {
+	uint32_t base;
+	uint32_t inst;
+	uint32_t clock_frequency;
+	const struct pinctrl_dev_config *pcfg;
+};
+
+struct sy1xx_i2c_dev_data {
+	struct k_sem lock;
+
+	bool error_active;
+	uint32_t bitrate;
+
+	uint8_t write[DEVICE_MAX_BUFFER_SIZE];
+	uint8_t read[DEVICE_MAX_BUFFER_SIZE];
+};
+
+static void sy1xx_i2c_ctrl_init(const struct device *dev)
+{
+	const struct sy1xx_i2c_dev_config *const cfg = dev->config;
+	struct sy1xx_i2c_dev_data *const data = dev->data;
+	uint16_t divider;
+	uint32_t idx;
+	uint8_t *buf;
+
+	k_sem_take(&data->lock, K_FOREVER);
+
+	/* reset the i2c controller */
+	SY1XX_UDMA_WRITE_REG(cfg->base, SY1XX_UDMA_SETUP_REG, 0x1);
+	k_sleep(K_MSEC(10));
+	SY1XX_UDMA_WRITE_REG(cfg->base, SY1XX_UDMA_SETUP_REG, 0x0);
+	k_sleep(K_MSEC(10));
+
+	/* prepare udma transfer buffer */
+	buf = data->write;
+	idx = 0;
+
+	/* fixed pre-scaler 1:5 */
+	divider = (sy1xx_soc_get_peripheral_clock() / 5) / data->bitrate;
+	buf[idx++] = SY1XX_I2C_CMD_CFG;
+	buf[idx++] = (divider & 0xff00) >> 8;
+	buf[idx++] = (divider & 0x00ff);
+
+	SY1XX_UDMA_START_RX(cfg->base, (uint32_t)data->read, 3, 0);
+	SY1XX_UDMA_START_TX(cfg->base, (uint32_t)buf, idx, 0);
+
+	/* wait for udma run empty */
+	k_sleep(K_MSEC(1));
+
+	/* reset udma channels */
+	SY1XX_UDMA_CANCEL_RX(cfg->base);
+	SY1XX_UDMA_CANCEL_TX(cfg->base);
+
+	data->error_active = false;
+
+	k_sem_give(&data->lock);
+}
+
+static int sy1xx_i2c_configure(const struct device *dev, uint32_t flags)
+{
+	const struct sy1xx_i2c_dev_config *const cfg = dev->config;
+	struct sy1xx_i2c_dev_data *const data = dev->data;
+
+	if (!(flags & I2C_MODE_CONTROLLER)) {
+		LOG_ERR("Master Mode is required");
+		return -EIO;
+	}
+
+	if (flags & I2C_ADDR_10_BITS) {
+		LOG_ERR("I2C 10-bit addressing is currently not supported");
+		LOG_ERR("Please submit a patch");
+		return -EIO;
+	}
+
+	/* Configure clock */
+	switch (I2C_SPEED_GET(flags)) {
+	case I2C_SPEED_STANDARD:
+		data->bitrate = SY1XX_I2C_SPEED_STANDARD;
+		break;
+	case I2C_SPEED_FAST:
+		data->bitrate = SY1XX_I2C_SPEED_FAST;
+		break;
+	case I2C_SPEED_FAST_PLUS:
+		data->bitrate = SY1XX_I2C_SPEED_FAST_PLUS;
+		break;
+	case I2C_SPEED_DT:
+		data->bitrate = cfg->clock_frequency;
+		break;
+
+	default:
+		LOG_ERR("Unsupported I2C speed value");
+		return -EIO;
+	}
+
+	sy1xx_i2c_ctrl_init(dev);
+
+	return 0;
+}
+
+static int sy1xx_i2c_initialize(const struct device *dev)
+{
+	const struct sy1xx_i2c_dev_config *const cfg = dev->config;
+	struct sy1xx_i2c_dev_data *const data = dev->data;
+	int ret;
+	uint32_t flags;
+
+	/* UDMA clock enable */
+	sy1xx_udma_enable_clock(SY1XX_UDMA_MODULE_I2C, cfg->inst);
+
+	/* PAD config */
+	ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret < 0) {
+		return ret;
+	}
+
+	k_sem_init(&data->lock, 1, 1);
+
+	/* check if DT has bitrate preset */
+	flags = I2C_MODE_CONTROLLER;
+	if (cfg->clock_frequency > 0) {
+		flags |= I2C_SPEED_SET(I2C_SPEED_DT);
+	} else {
+		flags |= I2C_SPEED_SET(I2C_SPEED_STANDARD);
+	}
+
+	return sy1xx_i2c_configure(dev, flags);
+}
+
+/**
+ *
+ * reading expects to receive all line data from i2c lines;
+ * so we have to wait until rx fifo fully empty, so
+ * we add wait states to the second queue and wait
+ * for the switch to second queue - which in that case indicates
+ * that reading (of first queue) is complete.
+ * then the first queue can immediately take the next transfer
+ * and so on.
+ *
+ */
+static int sy1xx_i2c_read(const struct device *dev, struct i2c_msg *msg, uint16_t addr, bool start,
+			  bool stop)
+{
+	const struct sy1xx_i2c_dev_config *const cfg = dev->config;
+	struct sy1xx_i2c_dev_data *const data = dev->data;
+	int ret;
+	uint32_t idx;
+	uint8_t *buf;
+	uint8_t *wait;
+	uint32_t wait_cnt;
+
+	/* prepare udma transfer buffer */
+	buf = data->write;
+	idx = 0;
+
+	if (start) {
+		buf[idx++] = SY1XX_I2C_CMD_START;
+		buf[idx++] = SY1XX_I2C_CMD_WR;
+		buf[idx++] = ((addr & 0x7F) << 1) | SY1XX_I2C_ADDR_READ;
+	}
+
+	if (msg->len > 1) {
+		/* repeat byte reads incl. ackn */
+		buf[idx++] = SY1XX_I2C_CMD_RPT;
+		buf[idx++] = msg->len - 1;
+		buf[idx++] = SY1XX_I2C_CMD_RD_ACK;
+	}
+
+	/* last read without ack */
+	buf[idx++] = SY1XX_I2C_CMD_RD_NACK;
+
+	if (stop) {
+		buf[idx++] = SY1XX_I2C_CMD_STOP;
+	} else {
+		/* add wait cycle for potentially restart condition */
+		buf[idx++] = SY1XX_I2C_CMD_WAIT;
+		buf[idx++] = 1;
+	}
+
+	/* fill 1st fifo queue with reading cmds */
+	SY1XX_UDMA_START_RX(cfg->base, (uint32_t)data->read, msg->len, 0);
+	SY1XX_UDMA_START_TX(cfg->base, (uint32_t)buf, idx, 0);
+
+	/* fill 2nd fifo queue with one waiting cycle */
+	wait = &buf[idx];
+	wait_cnt = 0;
+	wait[wait_cnt++] = SY1XX_I2C_CMD_WAIT;
+	wait[wait_cnt++] = 1;
+
+	SY1XX_UDMA_START_TX(cfg->base, (uint32_t)wait, wait_cnt, 0);
+
+	/* finally wait for the switch from 1st to 2nd queue */
+	SY1XX_UDMA_WAIT_FOR_FINISHED_TX(cfg->base);
+	SY1XX_UDMA_WAIT_FOR_FINISHED_RX(cfg->base);
+
+	/* make sure all is transferred to fifo */
+	if (SY1XX_UDMA_GET_REMAINING_TX(cfg->base)) {
+		LOG_ERR("filling fifo failed");
+		return -EINVAL;
+	}
+
+	if (SY1XX_UDMA_GET_REMAINING_RX(cfg->base)) {
+		LOG_ERR("missing read bytes, %d bytes left",
+			SY1XX_UDMA_GET_REMAINING_RX(cfg->base));
+		return -EINVAL;
+	}
+
+	/* copy data back to msg */
+	memcpy(msg->buf, data->read, msg->len);
+
+	return 0;
+}
+
+/**
+ *
+ * we just fill the outgoing tx fifo of i2c controller;
+ * after leaving this routine, not all bytes may have left the controller to the i2c lines
+ *
+ * filling the fifo is done by dma transfer to one of the two available queues
+ *
+ */
+static int sy1xx_i2c_write(const struct device *dev, struct i2c_msg *msg, uint16_t addr, bool start,
+			   bool stop)
+{
+	const struct sy1xx_i2c_dev_config *const cfg = dev->config;
+	struct sy1xx_i2c_dev_data *const data = dev->data;
+	int ret;
+	uint32_t idx;
+	uint8_t *buf;
+	uint8_t *wait;
+
+	/* prepare udma transfer buffer */
+	buf = data->write;
+	idx = 0;
+
+	if (start) {
+		buf[idx++] = SY1XX_I2C_CMD_START;
+		buf[idx++] = SY1XX_I2C_CMD_WR;
+		buf[idx++] = ((addr & 0x7F) << 1) | SY1XX_I2C_ADDR_WRITE;
+	}
+
+	if (msg->len) {
+		/* repeat byte write for all given data */
+		buf[idx++] = SY1XX_I2C_CMD_RPT;
+		buf[idx++] = msg->len;
+		buf[idx++] = SY1XX_I2C_CMD_WR;
+
+		/* add data */
+		for (uint32_t i = 0; i < msg->len; i++) {
+			buf[idx++] = msg->buf[i];
+		}
+	}
+
+	if (stop) {
+		buf[idx++] = SY1XX_I2C_CMD_STOP;
+	} else {
+		/* add wait cycle for potentially restart condition */
+		buf[idx++] = SY1XX_I2C_CMD_WAIT;
+		buf[idx++] = 1;
+	}
+
+	/* fill next tx fifo queue */
+	SY1XX_UDMA_START_TX(cfg->base, (uint32_t)buf, idx, 0);
+
+	/* wait for udma has filled i2c controller tx fifo */
+	SY1XX_UDMA_WAIT_FOR_FINISHED_TX(cfg->base);
+
+	/* make sure all is transferred to fifo */
+	if (SY1XX_UDMA_GET_REMAINING_TX(cfg->base)) {
+		LOG_ERR("filling fifo failed");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int sy1xx_i2c_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
+			      uint16_t addr)
+{
+	struct sy1xx_i2c_dev_data *const data = dev->data;
+	int ret;
+	bool start_cond, stop_cond;
+	enum sy1xx_i2c_mode prv_xfer, cur_xfer;
+
+	if (num_msgs < 0) {
+		return 0;
+	}
+
+	if (data->error_active) {
+		sy1xx_i2c_ctrl_init(dev);
+	}
+
+	k_sem_take(&data->lock, K_FOREVER);
+
+	prv_xfer = UNDEF;
+	for (uint32_t n = 0; n < num_msgs; n++) {
+
+		/* detect transfer type */
+		if ((msgs[n].flags & I2C_MSG_READ) == I2C_MSG_READ) {
+			/* read msg */
+			cur_xfer = READ;
+		} else {
+			/* write msg */
+			cur_xfer = WRITE;
+		}
+
+		/* transfer switched from read to write; or vice versa */
+		if (prv_xfer != cur_xfer) {
+			prv_xfer = cur_xfer;
+			start_cond = true;
+		} else {
+			start_cond = false;
+		}
+
+		/* stop on last msg */
+		if (n == (num_msgs - 1)) {
+			stop_cond = true;
+		} else {
+			stop_cond = false;
+		}
+
+		if (cur_xfer == READ) {
+			ret = sy1xx_i2c_read(dev, &msgs[n], addr, start_cond, stop_cond);
+		} else {
+			ret = sy1xx_i2c_write(dev, &msgs[n], addr, start_cond, stop_cond);
+		}
+
+		if (ret) {
+			data->error_active = true;
+			break;
+		}
+	}
+
+	k_sem_give(&data->lock);
+
+	return ret;
+}
+
+static DEVICE_API(i2c, sy1xx_i2c_driver_api) = {
+	.configure = sy1xx_i2c_configure,
+	.transfer = sy1xx_i2c_transfer,
+};
+
+#define SY1XX_I2C_INIT(n)                                                                          \
+                                                                                                   \
+	PINCTRL_DT_INST_DEFINE(n);                                                                 \
+                                                                                                   \
+	static const struct sy1xx_i2c_dev_config sy1xx_i2c_dev_config_##n = {                      \
+		.base = DT_INST_REG_ADDR(n),                                                       \
+		.inst = DT_INST_PROP(n, instance),                                                 \
+		.clock_frequency = DT_INST_PROP_OR(n, clock_frequency, 0),                         \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                         \
+	};                                                                                         \
+	static struct sy1xx_i2c_dev_data __attribute__((section(".udma_access")))                  \
+	__aligned(4) sy1xx_i2c_dev_data_##n = {};                                                  \
+	I2C_DEVICE_DT_INST_DEFINE(n, sy1xx_i2c_initialize, NULL, &sy1xx_i2c_dev_data_##n,          \
+				  &sy1xx_i2c_dev_config_##n, POST_KERNEL,                          \
+				  CONFIG_I2C_INIT_PRIORITY, &sy1xx_i2c_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(SY1XX_I2C_INIT)
diff --git a/drivers/i2c/i2c_tca954x.c b/drivers/i2c/i2c_tca954x.c
index ab8c3f01013..07e77852299 100644
--- a/drivers/i2c/i2c_tca954x.c
+++ b/drivers/i2c/i2c_tca954x.c
@@ -18,6 +18,7 @@ struct tca954x_root_config {
 	struct i2c_dt_spec i2c;
 	uint8_t nchans;
 	const struct gpio_dt_spec reset_gpios;
+	bool idle_disconnect;
 };
 
 struct tca954x_root_data {
@@ -82,7 +83,7 @@ static int tca954x_transfer(const struct device *dev,
 	const struct tca954x_root_config *config =
 			get_root_config_from_channel(dev);
 	const struct tca954x_channel_config *down_cfg = dev->config;
-	int res;
+	int res, disconnect_res;
 
 	res = k_mutex_lock(&data->lock, K_MSEC(5000));
 	if (res != 0) {
@@ -96,6 +97,14 @@ static int tca954x_transfer(const struct device *dev,
 
 	res = i2c_transfer(config->i2c.bus, msgs, num_msgs, addr);
 
+	if (config->idle_disconnect) {
+		/* Always attempt to disconnect, even if i2c_transfer fails */
+		disconnect_res = tca954x_set_channel(down_cfg->root, 0);
+		if (disconnect_res != 0 && res == 0) {
+			res = disconnect_res;
+		}
+	}
+
 end_trans:
 	k_mutex_unlock(&data->lock);
 	return res;
@@ -186,6 +195,7 @@ BUILD_ASSERT(CONFIG_I2C_TCA954X_CHANNEL_INIT_PRIO > CONFIG_I2C_TCA954X_ROOT_INIT
 		.nchans = ch,							  \
 		.reset_gpios = GPIO_DT_SPEC_GET_OR(			          \
 				DT_INST(inst, ti_tca##n##a), reset_gpios, {0}),	  \
+		.idle_disconnect = DT_INST_PROP(inst, i2c_mux_idle_disconnect),	  \
 	};								          \
 	static struct tca954x_root_data tca##n##a_data_##inst = {		  \
 		.lock = Z_MUTEX_INITIALIZER(tca##n##a_data_##inst.lock),	  \
diff --git a/drivers/i2c/i2c_wch.c b/drivers/i2c/i2c_wch.c
new file mode 100644
index 00000000000..e8176c257f0
--- /dev/null
+++ b/drivers/i2c/i2c_wch.c
@@ -0,0 +1,444 @@
+/*
+ * Copyright (c) 2025 Andrei-Edward Popa
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT wch_i2c
+
+#define LOG_LEVEL CONFIG_I2C_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(i2c_wch);
+
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/device.h>
+
+#include "i2c-priv.h"
+
+#include <ch32fun.h>
+
+typedef void (*irq_config_func_t)(const struct device *port);
+
+struct i2c_wch_config {
+	const struct pinctrl_dev_config *pcfg;
+	irq_config_func_t irq_config_func;
+	const struct device *clk_dev;
+	I2C_TypeDef *regs;
+	uint32_t bitrate;
+	uint8_t clk_id;
+};
+
+struct i2c_wch_data {
+	struct k_sem xfer_done;
+	struct {
+		struct i2c_msg *msg;
+		uint32_t idx;
+		union {
+			struct {
+				uint16_t addr : 10;
+				uint16_t err : 6;
+			};
+			uint16_t: 16;
+		};
+	} current;
+};
+
+static void wch_i2c_handle_start_bit(const struct device *dev)
+{
+	const struct i2c_wch_config *config = dev->config;
+	struct i2c_wch_data *data = dev->data;
+	I2C_TypeDef *regs = config->regs;
+
+	if ((data->current.msg->flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) {
+		regs->DATAR = ((data->current.addr << 1) & 0xFF);
+	} else {
+		regs->DATAR = ((data->current.addr << 1) & 0xFF) | 1;
+		if (data->current.msg->len == 2U) {
+			regs->CTLR1 |= I2C_CTLR1_POS;
+		}
+	}
+}
+
+static void wch_i2c_handle_addr(const struct device *dev)
+{
+	const struct i2c_wch_config *config = dev->config;
+	struct i2c_wch_data *data = dev->data;
+	I2C_TypeDef *regs = config->regs;
+
+	if ((data->current.msg->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
+		if (data->current.msg->len <= 2U) {
+			regs->CTLR1 &= ~I2C_CTLR1_ACK;
+			if (data->current.msg->len == 2U) {
+				regs->CTLR1 |= I2C_CTLR1_POS;
+			}
+		}
+	}
+
+	regs->STAR1;
+	regs->STAR2;
+}
+
+static void wch_i2c_handle_txe(const struct device *dev)
+{
+	const struct i2c_wch_config *config = dev->config;
+	struct i2c_wch_data *data = dev->data;
+	I2C_TypeDef *regs = config->regs;
+
+	if (data->current.idx < data->current.msg->len) {
+		regs->DATAR = data->current.msg->buf[data->current.idx++];
+		if (data->current.idx == data->current.msg->len) {
+			regs->CTLR2 &= ~I2C_CTLR2_ITBUFEN;
+		}
+	} else {
+		if (data->current.msg->flags & I2C_MSG_STOP) {
+			regs->CTLR1 |= I2C_CTLR1_STOP;
+		}
+
+		if (regs->STAR1 & I2C_STAR1_BTF) {
+			regs->DATAR;
+		}
+
+		k_sem_give(&data->xfer_done);
+	}
+}
+
+static void wch_i2c_handle_rxne(const struct device *dev)
+{
+	const struct i2c_wch_config *config = dev->config;
+	struct i2c_wch_data *data = dev->data;
+	I2C_TypeDef *regs = config->regs;
+
+	if (data->current.idx < data->current.msg->len) {
+		switch (data->current.msg->len - data->current.idx) {
+		case 1:
+			if (data->current.msg->flags & I2C_MSG_STOP) {
+				regs->CTLR1 |= I2C_CTLR1_STOP;
+			}
+			regs->CTLR2 &= ~I2C_CTLR2_ITBUFEN;
+			data->current.msg->buf[data->current.idx++] = regs->DATAR;
+			k_sem_give(&data->xfer_done);
+			break;
+		case 2:
+			regs->CTLR1 &= ~I2C_CTLR1_ACK;
+			regs->CTLR1 |= I2C_CTLR1_POS;
+			__fallthrough;
+		default:
+			data->current.msg->buf[data->current.idx++] = regs->DATAR;
+		}
+	} else {
+		if (data->current.msg->flags & I2C_MSG_STOP) {
+			regs->CTLR1 |= I2C_CTLR1_STOP;
+		}
+		k_sem_give(&data->xfer_done);
+	}
+}
+
+static void i2c_wch_event_isr(const struct device *dev)
+{
+	const struct i2c_wch_config *config = dev->config;
+	struct i2c_wch_data *data = dev->data;
+	I2C_TypeDef *regs = config->regs;
+	uint16_t status = regs->STAR1;
+	bool write;
+
+	write = ((data->current.msg->flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE);
+
+	if (status & I2C_STAR1_SB) {
+		wch_i2c_handle_start_bit(dev);
+	} else if (status & I2C_STAR1_ADDR) {
+		wch_i2c_handle_addr(dev);
+	} else if ((status & (I2C_STAR1_TXE | I2C_STAR1_BTF)) && write) {
+		wch_i2c_handle_txe(dev);
+	} else if ((status & (I2C_STAR1_RXNE | I2C_STAR1_BTF)) && (!write)) {
+		wch_i2c_handle_rxne(dev);
+	}
+}
+
+static void i2c_wch_error_isr(const struct device *dev)
+{
+	const struct i2c_wch_config *config = dev->config;
+	struct i2c_wch_data *data = dev->data;
+	I2C_TypeDef *regs = config->regs;
+	uint16_t status = regs->STAR1;
+
+	if (status & (I2C_STAR1_AF | I2C_STAR1_ARLO | I2C_STAR1_BERR)) {
+		if (status & I2C_STAR1_AF) {
+			regs->CTLR1 |= I2C_CTLR1_STOP;
+		}
+
+		data->current.err |= ((status >> 8) & 0x7);
+
+		regs->STAR1 &= ~(I2C_STAR1_AF | I2C_STAR1_ARLO | I2C_STAR1_BERR);
+
+		k_sem_give(&data->xfer_done);
+	}
+}
+
+static void wch_i2c_msg_init(const struct device *dev, struct i2c_msg *msg,
+			     uint16_t addr, bool first_msg)
+{
+	const struct i2c_wch_config *config = dev->config;
+	struct i2c_wch_data *data = dev->data;
+	I2C_TypeDef *regs = config->regs;
+
+	k_sem_reset(&data->xfer_done);
+
+	data->current.msg = msg;
+	data->current.idx = 0U;
+	data->current.err = 0U;
+	data->current.addr = addr;
+
+	regs->CTLR1 |= I2C_CTLR1_PE;
+	regs->CTLR1 |= I2C_CTLR1_ACK;
+
+	if (first_msg || (msg->flags & I2C_MSG_RESTART)) {
+		if (regs->CTLR1 & I2C_CTLR1_STOP) {
+			regs->CTLR1 &= ~I2C_CTLR1_STOP;
+		}
+		regs->CTLR1 |= I2C_CTLR1_START;
+	}
+}
+
+static int32_t wch_i2c_msg_end(const struct device *dev)
+{
+	struct i2c_wch_data *data = dev->data;
+
+	if (!data->current.err) {
+		return 0;
+	}
+
+	if (data->current.err & (I2C_STAR1_ARLO >> 8)) {
+		LOG_DBG("ARLO");
+	}
+
+	if (data->current.err & (I2C_STAR1_AF >> 8)) {
+		LOG_DBG("NACK");
+	}
+
+	if (data->current.err & (I2C_STAR1_BERR >> 8)) {
+		LOG_DBG("ERR");
+	}
+
+	data->current.err = 0;
+
+	return -EIO;
+}
+
+static void wch_i2c_config_interrupts(I2C_TypeDef *regs, bool enable)
+{
+	if (enable) {
+		regs->CTLR2 |= (I2C_CTLR2_ITERREN | I2C_CTLR2_ITEVTEN | I2C_CTLR2_ITBUFEN);
+	} else {
+		regs->CTLR2 &= ~(I2C_CTLR2_ITERREN | I2C_CTLR2_ITEVTEN | I2C_CTLR2_ITBUFEN);
+	}
+}
+
+static int32_t wch_i2c_begin_transfer(const struct device *dev, struct i2c_msg *msg,
+				      uint16_t addr, bool first_msg)
+{
+	const struct i2c_wch_config *config = dev->config;
+	struct i2c_wch_data *data = dev->data;
+	I2C_TypeDef *regs = config->regs;
+
+	wch_i2c_msg_init(dev, msg, addr, first_msg);
+
+	wch_i2c_config_interrupts(regs, true);
+
+	if (k_sem_take(&data->xfer_done, K_MSEC(CONFIG_I2C_WCH_XFER_TIMEOUT_MS)) < 0) {
+		return -ETIMEDOUT;
+	}
+
+	return wch_i2c_msg_end(dev);
+}
+
+static void wch_i2c_finish_transfer(const struct device *dev)
+{
+	const struct i2c_wch_config *config = dev->config;
+	I2C_TypeDef *regs = config->regs;
+
+	wch_i2c_config_interrupts(regs, false);
+
+	while (regs->STAR2 & I2C_STAR2_BUSY) {
+	}
+
+	regs->CTLR1 &= ~I2C_CTLR1_PE;
+}
+
+static int wch_i2c_configure_timing(I2C_TypeDef *regs, uint32_t clock_rate,
+				    uint32_t speed)
+{
+	uint16_t freq_range = (uint16_t)(clock_rate / 1000000);
+	uint16_t clock_config;
+
+#ifndef CONFIG_SOC_CH32V003
+	uint16_t trise;
+
+	switch (speed) {
+	case I2C_SPEED_STANDARD:
+		trise = freq_range + 1;
+		break;
+	case I2C_SPEED_FAST:
+		trise = (freq_range * 3 / 10) + 1;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	regs->RTR = trise;
+#endif
+
+	switch (speed) {
+	case I2C_SPEED_STANDARD:
+		clock_config = MAX((uint16_t)(clock_rate / (100000 * 2)), 4);
+		break;
+	case I2C_SPEED_FAST:
+		clock_config = MAX((uint16_t)(clock_rate / (400000 * 3)), 1) | I2C_CKCFGR_FS;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	regs->CKCFGR = clock_config;
+	regs->CTLR2 = (regs->CTLR2 & ~I2C_CTLR2_FREQ) | freq_range;
+
+	return 0;
+}
+
+static int i2c_wch_configure(const struct device *dev, uint32_t dev_config)
+{
+	const struct i2c_wch_config *config = dev->config;
+	I2C_TypeDef *regs = config->regs;
+	clock_control_subsys_t clk_sys;
+	uint32_t clock_rate;
+	int err;
+
+	if (!(dev_config & I2C_MODE_CONTROLLER)) {
+		return -ENOTSUP;
+	}
+
+	if (dev_config & I2C_ADDR_10_BITS) {
+		return -ENOTSUP;
+	}
+
+	clk_sys = (clock_control_subsys_t)(uintptr_t)config->clk_id;
+
+	err = clock_control_get_rate(config->clk_dev, clk_sys, &clock_rate);
+	if (err != 0) {
+		return err;
+	}
+
+	regs->CTLR1 &= ~I2C_CTLR1_PE;
+
+	err = wch_i2c_configure_timing(regs, clock_rate, I2C_SPEED_GET(dev_config));
+	if (err != 0) {
+		return err;
+	}
+
+	return 0;
+}
+
+static int i2c_wch_transfer(const struct device *dev, struct i2c_msg *msg,
+			    uint8_t num_msgs, uint16_t addr)
+{
+	int ret = 0;
+
+	for (uint8_t i = 1; i < num_msgs; i++) {
+		if ((msg[i - 1].flags & I2C_MSG_RW_MASK) != (msg[i].flags & I2C_MSG_RW_MASK)) {
+			if (!(msg[i].flags & I2C_MSG_RESTART)) {
+				return -EINVAL;
+			}
+		}
+
+		if (msg[i - 1].flags & I2C_MSG_STOP) {
+			return -EINVAL;
+		}
+	}
+
+	for (uint8_t i = 0; i < num_msgs && ret == 0; i++) {
+		ret = wch_i2c_begin_transfer(dev, &msg[i], addr, i == 0);
+	}
+
+	wch_i2c_finish_transfer(dev);
+
+	return ret;
+}
+
+static int i2c_wch_init(const struct device *dev)
+{
+	const struct i2c_wch_config *config = dev->config;
+	struct i2c_wch_data *data = dev->data;
+	clock_control_subsys_t clk_sys;
+	int err;
+
+	k_sem_init(&data->xfer_done, 0, 1);
+
+	clk_sys = (clock_control_subsys_t)(uintptr_t)config->clk_id;
+
+	err = clock_control_on(config->clk_dev, clk_sys);
+	if (err < 0) {
+		return err;
+	}
+
+	err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+	if (err < 0) {
+		return err;
+	}
+
+	err = i2c_wch_configure(dev, I2C_MODE_CONTROLLER | i2c_map_dt_bitrate(config->bitrate));
+	if (err < 0) {
+		return err;
+	}
+
+	config->irq_config_func(dev);
+
+	return 0;
+}
+
+static DEVICE_API(i2c, i2c_wch_api) = {
+	.configure = i2c_wch_configure,
+	.transfer = i2c_wch_transfer,
+#ifdef CONFIG_I2C_RTIO
+	.iodev_submit = i2c_iodev_submit_fallback,
+#endif
+};
+
+#define I2C_WCH_INIT(inst)								\
+	PINCTRL_DT_INST_DEFINE(inst);							\
+											\
+	static void i2c_wch_config_func_##inst(const struct device *dev);		\
+											\
+	static struct i2c_wch_config i2c_wch_cfg_##inst = {				\
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),				\
+		.irq_config_func = i2c_wch_config_func_##inst,				\
+		.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)),			\
+		.regs = (I2C_TypeDef *)DT_INST_REG_ADDR(inst),				\
+		.bitrate = DT_INST_PROP(inst, clock_frequency),				\
+		.clk_id = DT_INST_CLOCKS_CELL(inst, id)					\
+	};										\
+											\
+	static struct i2c_wch_data i2c_wch_data_##inst;					\
+											\
+	I2C_DEVICE_DT_INST_DEFINE(inst, i2c_wch_init, NULL, &i2c_wch_data_##inst,	\
+				 &i2c_wch_cfg_##inst, PRE_KERNEL_1,			\
+				 CONFIG_I2C_INIT_PRIORITY, &i2c_wch_api);		\
+											\
+	static void i2c_wch_config_func_##inst(const struct device *dev)		\
+	{										\
+		ARG_UNUSED(dev);							\
+											\
+		IRQ_CONNECT(DT_INST_IRQ_BY_IDX(inst, 0, irq),				\
+			    DT_INST_IRQ_BY_IDX(inst, 0, priority),			\
+			    i2c_wch_event_isr, DEVICE_DT_INST_GET(inst), 0);		\
+		irq_enable(DT_INST_IRQ_BY_IDX(inst, 0, irq));				\
+											\
+		IRQ_CONNECT(DT_INST_IRQ_BY_IDX(inst, 1, irq),				\
+			    DT_INST_IRQ_BY_IDX(inst, 1, priority),			\
+			    i2c_wch_error_isr, DEVICE_DT_INST_GET(inst), 0);		\
+		irq_enable(DT_INST_IRQ_BY_IDX(inst, 1, irq));				\
+	}
+
+DT_INST_FOREACH_STATUS_OKAY(I2C_WCH_INIT)
diff --git a/drivers/i2c/i2c_xilinx_axi.c b/drivers/i2c/i2c_xilinx_axi.c
index 61f9108b536..42a716f19ad 100644
--- a/drivers/i2c/i2c_xilinx_axi.c
+++ b/drivers/i2c/i2c_xilinx_axi.c
@@ -283,15 +283,24 @@ static uint32_t i2c_xilinx_axi_wait_interrupt(const struct i2c_xilinx_axi_config
 	return events;
 }
 
-static void i2c_xilinx_axi_clear_interrupt(const struct i2c_xilinx_axi_config *config,
-					   struct i2c_xilinx_axi_data *data, uint32_t int_mask)
+static void i2c_xilinx_axi_clear_interrupt_no_lock(const struct i2c_xilinx_axi_config *config,
+						   struct i2c_xilinx_axi_data *data,
+						   uint32_t int_mask)
 {
-	const k_spinlock_key_t key = k_spin_lock(&data->lock);
 	const uint32_t int_status = sys_read32(config->base + REG_ISR);
 
 	if (int_status & int_mask) {
 		sys_write32(int_status & int_mask, config->base + REG_ISR);
 	}
+}
+
+static void i2c_xilinx_axi_clear_interrupt(const struct i2c_xilinx_axi_config *config,
+					   struct i2c_xilinx_axi_data *data, uint32_t int_mask)
+{
+	const k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	i2c_xilinx_axi_clear_interrupt_no_lock(config, data, int_mask);
+
 	k_spin_unlock(&data->lock, key);
 }
 
@@ -521,7 +530,8 @@ static int i2c_xilinx_axi_write(const struct i2c_xilinx_axi_config *config,
 			bytes_to_send--;
 			bytes_left--;
 		}
-		i2c_xilinx_axi_clear_interrupt(config, data, ISR_TX_FIFO_EMPTY | ISR_BUS_NOT_BUSY);
+		i2c_xilinx_axi_clear_interrupt_no_lock(config, data,
+						       ISR_TX_FIFO_EMPTY | ISR_BUS_NOT_BUSY);
 		k_spin_unlock(&data->lock, key);
 
 		ret = i2c_xilinx_axi_wait_tx_done(config, data);
diff --git a/drivers/i2s/Kconfig.esp32 b/drivers/i2s/Kconfig.esp32
index b7044b14288..8cc13d01dc9 100644
--- a/drivers/i2s/Kconfig.esp32
+++ b/drivers/i2s/Kconfig.esp32
@@ -6,8 +6,7 @@ config I2S_ESP32
 	bool "ESP32 I2S driver"
 	default y
 	depends on DT_HAS_ESPRESSIF_ESP32_I2S_ENABLED
-	depends on DT_HAS_ESPRESSIF_ESP32_GDMA_ENABLED
-	select DMA
+	select DMA if DT_HAS_ESPRESSIF_ESP32_GDMA_ENABLED
 	help
 	  Enables the ESP32 I2S driver (GDMA SoCs only).
 
@@ -25,4 +24,11 @@ config I2S_ESP32_TX_BLOCK_COUNT
 	help
 	  Max number of blocks waiting to be transmitted by the I2S TX channel.
 
+config I2S_ESP32_DMA_DESC_NUM_MAX
+	int "ESP32 I2S number of link descriptors"
+	default 10
+	depends on !DT_HAS_ESPRESSIF_ESP32_GDMA_ENABLED
+	help
+	  Max number of link descriptor available for DMA transfers on each I2S channel
+
 endif
diff --git a/drivers/i2s/Kconfig.mcux b/drivers/i2s/Kconfig.mcux
index 4a7ef1b1eef..7a6889db617 100644
--- a/drivers/i2s/Kconfig.mcux
+++ b/drivers/i2s/Kconfig.mcux
@@ -1,6 +1,6 @@
 # MCUX I2S driver configuration options
 
-# Copyright (c) 2021, NXP
+# Copyright 2021,2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 menuconfig I2S_MCUX_SAI
@@ -28,4 +28,8 @@ config I2S_EDMA_BURST_SIZE
 	help
 	  I2S EDMA burst size in bytes.
 
+config I2S_HAS_PLL_SETTING
+	bool "I2S will setting pll in driver"
+	default y
+
 endif # I2S_MCUX_SAI
diff --git a/drivers/i2s/i2s_esp32.c b/drivers/i2s/i2s_esp32.c
index 1570c85efcf..ab29e02a902 100644
--- a/drivers/i2s/i2s_esp32.c
+++ b/drivers/i2s/i2s_esp32.c
@@ -1,70 +1,97 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) CO LTD
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #define DT_DRV_COMPAT espressif_esp32_i2s
 
-#include <zephyr/drivers/dma.h>
 #include <zephyr/drivers/i2s.h>
+#include <zephyr/drivers/dma.h>
 #include <zephyr/drivers/dma/dma_esp32.h>
-#include <soc.h>
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/drivers/pinctrl.h>
-
-#include <zephyr/logging/log.h>
 #include <zephyr/irq.h>
-
+#include <zephyr/devicetree.h>
+#include <zephyr/logging/log.h>
+#include <soc.h>
 #include <esp_clk_tree.h>
 #include <hal/i2s_hal.h>
 
+#if !SOC_GDMA_SUPPORTED
+#include <soc/lldesc.h>
+#include <esp_memory_utils.h>
+#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
+#endif /* !SOC_GDMA_SUPPORTED */
+
+#if SOC_GDMA_SUPPORTED && !DT_HAS_COMPAT_STATUS_OKAY(espressif_esp32_gdma)
+#error "DMA peripheral is not enabled!"
+#endif /* SOC_GDMA_SUPPORTED */
+
 LOG_MODULE_REGISTER(i2s_esp32, CONFIG_I2S_LOG_LEVEL);
 
-#if !SOC_GDMA_SUPPORTED
-#error "Only SoCs with GDMA peripheral are supported!"
-#endif
+#define I2S_ESP32_CLK_SRC             I2S_CLK_SRC_DEFAULT
+#define I2S_ESP32_DMA_BUFFER_MAX_SIZE 4092
 
-#define I2S_ESP32_CLK_SRC I2S_CLK_SRC_DEFAULT
+#define I2S_ESP32_NUM_INST_OK DT_NUM_INST_STATUS_OKAY(espressif_esp32_i2s)
+#define I2S_ESP32_IS_DIR_INST_EN(i, d) DT_INST_DMAS_HAS_NAME(i, d) || DT_INST_IRQ_HAS_NAME(i, d)
+#define I2S_ESP32_IS_DIR_EN(d)  LISTIFY(I2S_ESP32_NUM_INST_OK, I2S_ESP32_IS_DIR_INST_EN, (||), d)
 
 struct queue_item {
 	void *buffer;
 	size_t size;
 };
 
-struct i2s_esp32_stream {
+struct i2s_esp32_stream;
+
+struct i2s_esp32_stream_data {
 	int32_t state;
-	struct i2s_config i2s_cfg;
 	bool is_slave;
-
-	const struct device *dma_dev;
-	uint32_t dma_channel;
-
-	bool stop_without_draining;
-
+	struct i2s_config i2s_cfg;
 	void *mem_block;
 	size_t mem_block_len;
 	bool last_block;
-
+	bool stop_without_draining;
 	struct k_msgq queue;
-	void (*queue_drop)(struct i2s_esp32_stream *stream);
+	struct intr_handle_data_t *irq_handle;
+	bool dma_pending;
+	uint8_t chunks_rem;
+	uint8_t chunk_idx;
+};
 
+struct i2s_esp32_stream_conf {
+	void (*queue_drop)(const struct i2s_esp32_stream *stream);
 	int (*start_transfer)(const struct device *dev);
 	void (*stop_transfer)(const struct device *dev);
+	const struct device *dma_dev;
+	uint32_t dma_channel;
+#if SOC_GDMA_SUPPORTED
+	void *dma_desc;
+#else
+	lldesc_t *dma_desc;
+#endif
+	int irq_source;
+	int irq_priority;
+	int irq_flags;
+};
+
+struct i2s_esp32_stream {
+	struct i2s_esp32_stream_data *data;
+	const struct i2s_esp32_stream_conf *conf;
 };
 
 struct i2s_esp32_cfg {
 	const int unit;
-	i2s_hal_context_t hal_cxt;
+	i2s_hal_context_t hal;
 	const struct pinctrl_dev_config *pcfg;
 	const struct device *clock_dev;
 	clock_control_subsys_t clock_subsys;
+	struct i2s_esp32_stream rx;
+	struct i2s_esp32_stream tx;
 };
 
 struct i2s_esp32_data {
 	i2s_hal_clock_info_t clk_info;
-	struct i2s_esp32_stream rx;
-	struct i2s_esp32_stream tx;
 };
 
 uint32_t i2s_esp32_get_source_clk_freq(i2s_clock_src_t clk_src)
@@ -117,136 +144,163 @@ static esp_err_t i2s_esp32_calculate_clock(const struct i2s_config *i2s_cfg, uin
 	return ESP_OK;
 }
 
-static void i2s_esp32_queue_drop(struct i2s_esp32_stream *stream)
+static void i2s_esp32_queue_drop(const struct i2s_esp32_stream *stream)
 {
 	struct queue_item item;
 
-	while (k_msgq_get(&stream->queue, &item, K_NO_WAIT) == 0) {
-		k_mem_slab_free(stream->i2s_cfg.mem_slab, item.buffer);
+	while (k_msgq_get(&stream->data->queue, &item, K_NO_WAIT) == 0) {
+		k_mem_slab_free(stream->data->i2s_cfg.mem_slab, item.buffer);
 	}
 }
 
-static void i2s_esp32_rx_callback(const struct device *dma_dev, void *arg, uint32_t channel,
-				  int status);
-static void i2s_esp32_tx_callback(const struct device *dma_dev, void *arg, uint32_t channel,
-				  int status);
+static int i2s_esp32_restart_dma(const struct device *dev, enum i2s_dir dir);
+static int i2s_esp32_start_dma(const struct device *dev, enum i2s_dir dir);
 
-static int i2s_esp32_restart_dma(const struct device *dev, enum i2s_dir i2s_dir)
+#if I2S_ESP32_IS_DIR_EN(rx)
+
+#if SOC_GDMA_SUPPORTED
+static void i2s_esp32_rx_callback(const struct device *dma_dev, void *arg, uint32_t channel,
+				  int status)
+#else
+static void i2s_esp32_rx_callback(void *arg, int status)
+#endif /* SOC_GDMA_SUPPORTED */
 {
+	const struct device *dev = (const struct device *)arg;
 	const struct i2s_esp32_cfg *dev_cfg = dev->config;
-	struct i2s_esp32_data *const dev_data = dev->data;
-	struct i2s_esp32_stream *stream;
-	void *src = NULL, *dst = NULL;
+	const struct i2s_esp32_stream *stream = &dev_cfg->rx;
 	int err;
 
-	if (i2s_dir == I2S_DIR_RX) {
-		stream = &dev_data->rx;
-		dst = stream->mem_block;
-	} else if (i2s_dir == I2S_DIR_TX) {
-		stream = &dev_data->tx;
-		src = stream->mem_block;
-	} else {
-		LOG_ERR("Invalid DMA direction");
-		return -EINVAL;
+#if SOC_GDMA_SUPPORTED
+	if (status < 0) {
+#else
+	if (status & I2S_LL_EVENT_RX_DSCR_ERR) {
+#endif /* SOC_GDMA_SUPPORTED */
+		stream->data->state = I2S_STATE_ERROR;
+		LOG_ERR("RX status bad: %d", status);
+		goto rx_disable;
 	}
 
-	err = dma_reload(stream->dma_dev, stream->dma_channel, (uint32_t)src, (uint32_t)dst,
-			 stream->mem_block_len);
-	if (err < 0) {
-		LOG_ERR("Error reloading DMA channel[%d]: %d", (int)stream->dma_channel, err);
-		return -EIO;
+	if (stream->data->mem_block == NULL) {
+		if (stream->data->state != I2S_STATE_READY) {
+			stream->data->state = I2S_STATE_ERROR;
+			LOG_ERR("RX mem_block NULL");
+			goto rx_disable;
+		} else {
+			return;
+		}
 	}
 
-	if (i2s_dir == I2S_DIR_RX) {
-		i2s_ll_rx_set_eof_num(dev_cfg->hal_cxt.dev, stream->mem_block_len);
-	}
+#if SOC_GDMA_SUPPORTED
+	const i2s_hal_context_t *hal = &(dev_cfg->hal);
+	uint16_t chunk_len;
 
-	err = dma_start(stream->dma_dev, stream->dma_channel);
-	if (err < 0) {
-		LOG_ERR("Error starting DMA channel[%d]: %d", (int)stream->dma_channel, err);
-		return -EIO;
-	}
+	if (stream->data->chunks_rem) {
+		uint32_t dst;
 
-	return 0;
-}
+		stream->data->chunk_idx++;
+		stream->data->chunks_rem--;
+		if (stream->data->chunks_rem) {
+			chunk_len = I2S_ESP32_DMA_BUFFER_MAX_SIZE;
+		} else {
+			chunk_len = stream->data->mem_block_len % I2S_ESP32_DMA_BUFFER_MAX_SIZE;
+			if (chunk_len == 0) {
+				chunk_len = I2S_ESP32_DMA_BUFFER_MAX_SIZE;
+			}
+		}
 
-static int i2s_esp32_start_dma(const struct device *dev, enum i2s_dir i2s_dir)
-{
-	const struct i2s_esp32_cfg *dev_cfg = dev->config;
-	struct i2s_esp32_data *const dev_data = dev->data;
-	struct i2s_esp32_stream *stream = NULL;
-	struct dma_config dma_cfg = {0};
-	struct dma_block_config dma_blk = {0};
-	unsigned int key;
-	int err, ret = 0;
+		dst = (uint32_t)stream->data->mem_block + (stream->data->chunk_idx *
+							   I2S_ESP32_DMA_BUFFER_MAX_SIZE);
+		err = dma_reload(stream->conf->dma_dev, stream->conf->dma_channel, (uint32_t)NULL,
+				(uint32_t)dst, chunk_len);
+		if (err < 0) {
+			LOG_ERR("Failed to reload DMA channel: %"PRIu32, stream->conf->dma_channel);
+			goto rx_disable;
+		}
 
-	if (i2s_dir == I2S_DIR_RX) {
-		stream = &dev_data->rx;
-	} else if (i2s_dir == I2S_DIR_TX) {
-		stream = &dev_data->tx;
-	} else {
-		LOG_ERR("Invalid DMA direction");
-		return -EINVAL;
-	}
+		i2s_ll_rx_set_eof_num(hal->dev, chunk_len);
 
-	key = irq_lock();
+		err = dma_start(stream->conf->dma_dev, stream->conf->dma_channel);
+		if (err < 0) {
+			LOG_ERR("Failed to start DMA channel: %"PRIu32, stream->conf->dma_channel);
+			goto rx_disable;
+		}
 
-	dma_blk.block_size = stream->mem_block_len;
-	if (i2s_dir == I2S_DIR_RX) {
-		dma_blk.dest_address = (uint32_t)stream->mem_block;
-		dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
-		dma_cfg.dma_callback = i2s_esp32_rx_callback;
-	} else {
-		dma_blk.source_address = (uint32_t)stream->mem_block;
-		dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
-		dma_cfg.dma_callback = i2s_esp32_tx_callback;
+		stream->data->dma_pending = true;
+
+		return;
 	}
-	dma_cfg.user_data = (void *)dev;
-	dma_cfg.dma_slot =
-		dev_cfg->unit == 0 ? ESP_GDMA_TRIG_PERIPH_I2S0 : ESP_GDMA_TRIG_PERIPH_I2S1;
-	dma_cfg.block_count = 1;
-	dma_cfg.head_block = &dma_blk;
+#endif /* SOC_GDMA_SUPPORTED */
 
-	err = dma_config(stream->dma_dev, stream->dma_channel, &dma_cfg);
+	struct queue_item item = {
+		.buffer = stream->data->mem_block,
+		.size = stream->data->mem_block_len
+	};
+
+	err = k_msgq_put(&stream->data->queue, &item, K_NO_WAIT);
 	if (err < 0) {
-		LOG_ERR("Error configuring DMA channel[%d]: %d", (int)stream->dma_channel, err);
-		ret = -EINVAL;
-		goto unlock;
+		stream->data->state = I2S_STATE_ERROR;
+		goto rx_disable;
 	}
 
-	if (i2s_dir == I2S_DIR_RX) {
-		i2s_ll_rx_set_eof_num(dev_cfg->hal_cxt.dev, stream->mem_block_len);
+	if (stream->data->state == I2S_STATE_STOPPING) {
+		stream->data->state = I2S_STATE_READY;
+		goto rx_disable;
 	}
 
-	err = dma_start(stream->dma_dev, stream->dma_channel);
+	err = k_mem_slab_alloc(stream->data->i2s_cfg.mem_slab, &stream->data->mem_block, K_NO_WAIT);
 	if (err < 0) {
-		LOG_ERR("Error starting DMA channel[%d]: %d", (int)stream->dma_channel, err);
-		ret = -EIO;
-		goto unlock;
+		LOG_ERR("RX failed to allocate memory from slab: %i:", err);
+		stream->data->state = I2S_STATE_ERROR;
+		goto rx_disable;
 	}
+	stream->data->mem_block_len = stream->data->i2s_cfg.block_size;
 
-unlock:
-	irq_unlock(key);
-	return ret;
+	err = i2s_esp32_restart_dma(dev, I2S_DIR_RX);
+	if (err < 0) {
+		stream->data->state = I2S_STATE_ERROR;
+		LOG_ERR("Failed to restart RX transfer: %d", err);
+		goto rx_disable;
+	}
+
+	return;
+
+rx_disable:
+	stream->conf->stop_transfer(dev);
 }
 
+#if !SOC_GDMA_SUPPORTED
+
+static void IRAM_ATTR i2s_esp32_rx_handler(void *arg)
+{
+	if (arg == NULL) {
+		return;
+	}
+
+	struct device *dev = (struct device *)arg;
+	const struct i2s_esp32_cfg *const dev_cfg = dev->config;
+	const i2s_hal_context_t *hal = &(dev_cfg->hal);
+	uint32_t status = i2s_hal_get_intr_status(hal);
+
+	i2s_hal_clear_intr_status(hal, status);
+	if (status & I2S_LL_EVENT_RX_EOF) {
+		i2s_esp32_rx_callback((void *)arg, status);
+	}
+}
+
+#endif /* !SOC_GDMA_SUPPORTED */
+
 static int i2s_esp32_rx_start_transfer(const struct device *dev)
 {
-	struct i2s_esp32_data *const dev_data = dev->data;
 	const struct i2s_esp32_cfg *dev_cfg = dev->config;
-	struct i2s_esp32_stream *stream = &dev_data->rx;
-	const i2s_hal_context_t *hal_cxt = &dev_cfg->hal_cxt;
+	const struct i2s_esp32_stream *stream = &dev_cfg->rx;
+	const i2s_hal_context_t *hal = &dev_cfg->hal;
 	int err;
 
-	err = k_mem_slab_alloc(stream->i2s_cfg.mem_slab, &stream->mem_block, K_NO_WAIT);
+	err = k_mem_slab_alloc(stream->data->i2s_cfg.mem_slab, &stream->data->mem_block, K_NO_WAIT);
 	if (err < 0) {
 		return -ENOMEM;
 	}
-	stream->mem_block_len = stream->i2s_cfg.block_size;
-
-	i2s_hal_rx_stop(hal_cxt);
-	i2s_hal_rx_reset(hal_cxt);
-	i2s_hal_rx_reset_fifo(hal_cxt);
+	stream->data->mem_block_len = stream->data->i2s_cfg.block_size;
 
 	err = i2s_esp32_start_dma(dev, I2S_DIR_RX);
 	if (err < 0) {
@@ -254,213 +308,481 @@ static int i2s_esp32_rx_start_transfer(const struct device *dev)
 		return -EIO;
 	}
 
-	i2s_hal_rx_start(hal_cxt);
+	i2s_hal_rx_start(hal);
+
+#if !SOC_GDMA_SUPPORTED
+	esp_intr_enable(stream->data->irq_handle);
+#endif /* !SOC_GDMA_SUPPORTED */
 
 	return 0;
 }
 
-static int i2s_esp32_tx_start_transfer(const struct device *dev)
+static void i2s_esp32_rx_stop_transfer(const struct device *dev)
 {
 	const struct i2s_esp32_cfg *dev_cfg = dev->config;
-	struct i2s_esp32_data *const dev_data = dev->data;
-	struct i2s_esp32_stream *stream = &dev_data->tx;
-	const i2s_hal_context_t *hal_cxt = &dev_cfg->hal_cxt;
+	const struct i2s_esp32_stream *stream = &dev_cfg->rx;
+
+#if SOC_GDMA_SUPPORTED
+	dma_stop(stream->conf->dma_dev, stream->conf->dma_channel);
+#else
+	const i2s_hal_context_t *hal = &(dev_cfg->hal);
+
+	esp_intr_disable(stream->data->irq_handle);
+	i2s_hal_rx_stop_link(hal);
+	i2s_hal_rx_disable_intr(hal);
+	i2s_hal_rx_disable_dma(hal);
+	i2s_hal_clear_intr_status(hal, I2S_INTR_MAX);
+#endif /* SOC_GDMA_SUPPORTED */
+
+	if (stream->data->mem_block != NULL) {
+		k_mem_slab_free(stream->data->i2s_cfg.mem_slab, stream->data->mem_block);
+		stream->data->mem_block = NULL;
+		stream->data->mem_block_len = 0;
+	}
+}
+
+#endif /* I2S_ESP32_IS_DIR_EN(rx) */
+
+#if I2S_ESP32_IS_DIR_EN(tx)
+
+#if SOC_GDMA_SUPPORTED
+static void i2s_esp32_tx_callback(const struct device *dma_dev, void *arg, uint32_t channel,
+				  int status)
+#else
+static void i2s_esp32_tx_callback(void *arg, int status)
+#endif /* SOC_GDMA_SUPPORTED */
+{
+	const struct device *dev = (const struct device *)arg;
+	const struct i2s_esp32_cfg *const dev_cfg = dev->config;
+	const struct i2s_esp32_stream *stream = &dev_cfg->tx;
 	struct queue_item item;
+	void *mem_block_tmp;
 	int err;
 
-	err = k_msgq_get(&stream->queue, &item, K_NO_WAIT);
+	if (!stream->data->dma_pending) {
+		return;
+	}
+
+	stream->data->dma_pending = false;
+
+#if SOC_GDMA_SUPPORTED
+	if (status < 0) {
+#else
+	if (status & I2S_LL_EVENT_TX_DSCR_ERR) {
+#endif /* SOC_GDMA_SUPPORTED */
+		stream->data->state = I2S_STATE_ERROR;
+		LOG_ERR("TX bad status: %d", status);
+		goto tx_disable;
+	}
+
+	if (stream->data->mem_block == NULL) {
+		if (stream->data->state != I2S_STATE_READY) {
+			stream->data->state = I2S_STATE_ERROR;
+			LOG_ERR("TX mem_block NULL");
+			goto tx_disable;
+		} else {
+			return;
+		}
+	}
+
+	if (stream->data->state == I2S_STATE_STOPPING) {
+		if (k_msgq_num_used_get(&stream->data->queue) == 0) {
+			stream->data->state = I2S_STATE_READY;
+			goto tx_disable;
+		} else if (stream->data->stop_without_draining == true) {
+			stream->conf->queue_drop(stream);
+			stream->data->state = I2S_STATE_READY;
+			goto tx_disable;
+		}
+	}
+
+	if (stream->data->last_block) {
+		stream->data->state = I2S_STATE_READY;
+		goto tx_disable;
+	}
+
+	err = k_msgq_get(&stream->data->queue, &item, K_NO_WAIT);
 	if (err < 0) {
-		return -ENOMEM;
+		stream->data->state = I2S_STATE_ERROR;
+		LOG_ERR("TX queue empty: %d", err);
+		goto tx_disable;
 	}
 
-	stream->mem_block = item.buffer;
-	stream->mem_block_len = item.size;
+	mem_block_tmp = stream->data->mem_block;
 
-	i2s_hal_tx_stop(hal_cxt);
-	i2s_hal_tx_reset(hal_cxt);
-	i2s_hal_tx_reset_fifo(hal_cxt);
+	stream->data->mem_block = item.buffer;
+	stream->data->mem_block_len = item.size;
 
-	err = i2s_esp32_start_dma(dev, I2S_DIR_TX);
+	err = i2s_esp32_restart_dma(dev, I2S_DIR_TX);
 	if (err < 0) {
-		LOG_ERR("Failed to start TX DMA transfer: %d", err);
-		return -EIO;
+		stream->data->state = I2S_STATE_ERROR;
+		LOG_ERR("Failed to restart TX transfer: %d", err);
+		goto tx_disable;
 	}
 
-	i2s_hal_tx_start(hal_cxt);
+	k_mem_slab_free(stream->data->i2s_cfg.mem_slab, mem_block_tmp);
 
-	return 0;
+	return;
+
+tx_disable:
+	stream->conf->stop_transfer(dev);
 }
 
-static void i2s_esp32_rx_stop_transfer(const struct device *dev)
+#if !SOC_GDMA_SUPPORTED
+
+static void IRAM_ATTR i2s_esp32_tx_handler(void *arg)
 {
-	struct i2s_esp32_data *const dev_data = dev->data;
-	struct i2s_esp32_stream *stream = &dev_data->rx;
+	if (arg == NULL) {
+		return;
+	}
 
-	dma_stop(stream->dma_dev, stream->dma_channel);
+	struct device *dev = (struct device *)arg;
+	const struct i2s_esp32_cfg *const dev_cfg = dev->config;
+	const i2s_hal_context_t *hal = &(dev_cfg->hal);
+	uint32_t status = i2s_hal_get_intr_status(hal);
 
-	if (stream->mem_block != NULL) {
-		k_mem_slab_free(stream->i2s_cfg.mem_slab, stream->mem_block);
-		stream->mem_block = NULL;
-		stream->mem_block_len = 0;
+	i2s_hal_clear_intr_status(hal, status);
+	if (status & I2S_LL_EVENT_TX_EOF) {
+		i2s_esp32_tx_callback((void *)arg, status);
 	}
 }
 
-static void i2s_esp32_tx_stop_transfer(const struct device *dev)
+#endif /* !SOC_GDMA_SUPPORTED */
+
+static int i2s_esp32_tx_start_transfer(const struct device *dev)
 {
-	struct i2s_esp32_data *const dev_data = dev->data;
-	struct i2s_esp32_stream *stream = &dev_data->tx;
+	const struct i2s_esp32_cfg *dev_cfg = dev->config;
+	const struct i2s_esp32_stream *stream = &dev_cfg->tx;
+	const i2s_hal_context_t *hal = &dev_cfg->hal;
+	struct queue_item item;
+	int err;
+
+	err = k_msgq_get(&stream->data->queue, &item, K_NO_WAIT);
+	if (err < 0) {
+		return -ENOMEM;
+	}
 
-	dma_stop(stream->dma_dev, stream->dma_channel);
+	stream->data->mem_block = item.buffer;
+	stream->data->mem_block_len = item.size;
 
-	if (stream->mem_block != NULL) {
-		k_mem_slab_free(stream->i2s_cfg.mem_slab, stream->mem_block);
-		stream->mem_block = NULL;
-		stream->mem_block_len = 0;
+	err = i2s_esp32_start_dma(dev, I2S_DIR_TX);
+	if (err < 0) {
+		LOG_ERR("Failed to start TX DMA transfer: %d", err);
+		return -EIO;
 	}
+
+	i2s_hal_tx_start(hal);
+
+#if !SOC_GDMA_SUPPORTED
+	esp_intr_enable(stream->data->irq_handle);
+#endif /* !SOC_GDMA_SUPPORTED */
+
+	return 0;
 }
 
-static void i2s_esp32_rx_callback(const struct device *dma_dev, void *arg, uint32_t channel,
-				  int status)
+static void i2s_esp32_tx_stop_transfer(const struct device *dev)
 {
-	const struct device *dev = (const struct device *)arg;
-	struct i2s_esp32_data *const dev_data = dev->data;
-	struct i2s_esp32_stream *stream = &dev_data->rx;
+	const struct i2s_esp32_cfg *dev_cfg = dev->config;
+	const struct i2s_esp32_stream *stream = &dev_cfg->tx;
+
+#if SOC_GDMA_SUPPORTED
+	dma_stop(stream->conf->dma_dev, stream->conf->dma_channel);
+#else
+	const i2s_hal_context_t *hal = &(dev_cfg->hal);
+
+	esp_intr_disable(stream->data->irq_handle);
+	i2s_hal_tx_stop_link(hal);
+	i2s_hal_tx_disable_intr(hal);
+	i2s_hal_tx_disable_dma(hal);
+	i2s_hal_clear_intr_status(hal, I2S_INTR_MAX);
+#endif /* SOC_GDMA_SUPPORTED */
+
+	if (stream->data->mem_block != NULL) {
+		k_mem_slab_free(stream->data->i2s_cfg.mem_slab, stream->data->mem_block);
+		stream->data->mem_block = NULL;
+		stream->data->mem_block_len = 0;
+	}
+}
+
+#endif /* I2S_ESP32_IS_DIR_EN(tx) */
+
+int i2s_esp32_config_dma(const struct device *dev, enum i2s_dir dir,
+			 const struct i2s_esp32_stream *stream)
+{
+	uint32_t mem_block = (uint32_t)stream->data->mem_block;
+	uint32_t mem_block_size = stream->data->mem_block_len;
+
+#if SOC_GDMA_SUPPORTED
+	const struct i2s_esp32_cfg *dev_cfg = dev->config;
+	struct dma_config dma_cfg = {0};
+	struct dma_block_config dma_blk = {0};
 	int err;
 
-	if (status < 0) {
-		stream->state = I2S_STATE_ERROR;
-		LOG_ERR("RX status bad: %d", status);
-		goto rx_disable;
+	dma_blk.block_size = mem_block_size;
+	if (dir == I2S_DIR_RX) {
+#if I2S_ESP32_IS_DIR_EN(rx)
+		dma_blk.dest_address = mem_block;
+		dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
+		dma_cfg.dma_callback = i2s_esp32_rx_callback;
+#endif /* I2S_ESP32_IS_DIR_EN(rx) */
+	} else {
+#if I2S_ESP32_IS_DIR_EN(tx)
+		dma_blk.source_address = mem_block;
+		dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
+		dma_cfg.dma_callback = i2s_esp32_tx_callback;
+#endif /* I2S_ESP32_IS_DIR_EN(tx) */
 	}
+	dma_cfg.user_data = (void *)dev;
+	dma_cfg.dma_slot =
+		dev_cfg->unit == 0 ? ESP_GDMA_TRIG_PERIPH_I2S0 : ESP_GDMA_TRIG_PERIPH_I2S1;
+	dma_cfg.block_count = 1;
+	dma_cfg.head_block = &dma_blk;
 
-	if (stream->mem_block == NULL) {
-		if (stream->state != I2S_STATE_READY) {
-			stream->state = I2S_STATE_ERROR;
-			LOG_ERR("RX mem_block NULL");
-			goto rx_disable;
+	err = dma_config(stream->conf->dma_dev, stream->conf->dma_channel, &dma_cfg);
+	if (err < 0) {
+		LOG_ERR("Failed to configure DMA channel: %"PRIu32, stream->conf->dma_channel);
+		return -EINVAL;
+	}
+#else
+	lldesc_t *desc_iter = stream->conf->dma_desc;
+
+	if (!mem_block) {
+		LOG_ERR("At least one dma block is required");
+		return -EINVAL;
+	}
+
+	if (!esp_ptr_dma_capable((void *)mem_block)) {
+		LOG_ERR("Buffer is not in DMA capable memory: %p",
+			(uint32_t *)mem_block);
+
+		return -EINVAL;
+	}
+
+	for (int i = 0; i < CONFIG_I2S_ESP32_DMA_DESC_NUM_MAX; ++i) {
+		uint32_t buffer_size;
+
+		if (mem_block_size > I2S_ESP32_DMA_BUFFER_MAX_SIZE) {
+			buffer_size = I2S_ESP32_DMA_BUFFER_MAX_SIZE;
 		} else {
-			return;
+			buffer_size = mem_block_size;
 		}
-	}
 
-	struct queue_item item = {.buffer = stream->mem_block, .size = stream->mem_block_len};
+		memset(desc_iter, 0, sizeof(lldesc_t));
+		desc_iter->owner = 1;
+		desc_iter->sosf = 0;
+		desc_iter->buf = (uint8_t *)mem_block;
+		desc_iter->offset = 0;
+		desc_iter->length = buffer_size;
+		desc_iter->size = buffer_size;
+		desc_iter->eof = 0;
+
+		mem_block += buffer_size;
+		mem_block_size -= buffer_size;
+
+		if (mem_block_size > 0) {
+			desc_iter->empty = (uint32_t)(desc_iter + 1);
+			desc_iter += 1;
+		} else {
+			stream->data->dma_pending = true;
+			desc_iter->empty = 0;
+			if (dir == I2S_DIR_TX) {
+				desc_iter->eof = 1;
+			}
+			break;
+		}
+	}
 
-	err = k_msgq_put(&stream->queue, &item, K_NO_WAIT);
-	if (err < 0) {
-		stream->state = I2S_STATE_ERROR;
-		goto rx_disable;
+	if (desc_iter->empty)  {
+		stream->data->dma_pending = false;
+		LOG_ERR("Run out of descriptors. Increase CONFIG_I2S_ESP32_DMA_DESC_NUM_MAX");
+		return -EINVAL;
 	}
+#endif /* SOC_GDMA_SUPPORTED */
 
-	if (stream->state == I2S_STATE_STOPPING) {
-		stream->state = I2S_STATE_READY;
-		goto rx_disable;
+	return 0;
+}
+
+static int i2s_esp32_start_dma(const struct device *dev, enum i2s_dir dir)
+{
+	const struct i2s_esp32_cfg *dev_cfg = dev->config;
+	const struct i2s_esp32_stream *stream = NULL;
+	unsigned int key;
+	int err = 0;
+
+#if !SOC_GDMA_SUPPORTED || I2S_ESP32_IS_DIR_EN(rx)
+	const i2s_hal_context_t *hal = &(dev_cfg->hal);
+#endif /* SOC_GDMA_SUPPORTED || I2S_ESP32_IS_DIR_EN(rx) */
+
+	if (dir == I2S_DIR_RX) {
+		stream = &dev_cfg->rx;
+	} else if (dir == I2S_DIR_TX) {
+		stream = &dev_cfg->tx;
+	} else {
+		LOG_ERR("Invalid DMA direction");
+		return -EINVAL;
 	}
 
-	err = k_mem_slab_alloc(stream->i2s_cfg.mem_slab, &stream->mem_block, K_NO_WAIT);
+	key = irq_lock();
+
+	err = i2s_esp32_config_dma(dev, dir, stream);
 	if (err < 0) {
-		stream->state = I2S_STATE_ERROR;
-		goto rx_disable;
+		LOG_ERR("Dma configuration failed: %i", err);
+		goto unlock;
 	}
-	stream->mem_block_len = stream->i2s_cfg.block_size;
 
-	err = i2s_esp32_restart_dma(dev, I2S_DIR_RX);
+#if I2S_ESP32_IS_DIR_EN(rx)
+	if (dir == I2S_DIR_RX) {
+		uint16_t chunk_len;
+
+#if SOC_GDMA_SUPPORTED
+		if (stream->data->mem_block_len < I2S_ESP32_DMA_BUFFER_MAX_SIZE) {
+			chunk_len = stream->data->mem_block_len;
+			stream->data->chunks_rem = 0;
+		} else {
+			chunk_len = I2S_ESP32_DMA_BUFFER_MAX_SIZE;
+			stream->data->chunks_rem = ((stream->data->mem_block_len +
+						     (I2S_ESP32_DMA_BUFFER_MAX_SIZE - 1)) /
+						    I2S_ESP32_DMA_BUFFER_MAX_SIZE) - 1;
+		}
+		stream->data->chunk_idx = 0;
+#else
+		chunk_len = stream->data->mem_block_len;
+#endif
+		i2s_ll_rx_set_eof_num(hal->dev, chunk_len);
+	}
+#endif /* I2S_ESP32_IS_DIR_EN(rx) */
+
+#if SOC_GDMA_SUPPORTED
+	err = dma_start(stream->conf->dma_dev, stream->conf->dma_channel);
 	if (err < 0) {
-		stream->state = I2S_STATE_ERROR;
-		LOG_ERR("Failed to restart RX transfer: %d", err);
-		goto rx_disable;
+		LOG_ERR("Failed to start DMA channel: %"PRIu32, stream->conf->dma_channel);
+		goto unlock;
 	}
+	stream->data->dma_pending = true;
+#else
+#if I2S_ESP32_IS_DIR_EN(rx)
+	if (dir == I2S_DIR_RX) {
+		i2s_hal_rx_enable_dma(hal);
+		i2s_hal_rx_enable_intr(hal);
+		i2s_hal_rx_start_link(hal, (uint32_t)&(stream->conf->dma_desc[0]));
+	}
+#endif /* I2S_ESP32_IS_DIR_EN(rx) */
 
-	return;
+#if I2S_ESP32_IS_DIR_EN(tx)
+	if (dir == I2S_DIR_TX) {
+		i2s_hal_tx_enable_dma(hal);
+		i2s_hal_tx_enable_intr(hal);
+		i2s_hal_tx_start_link(hal, (uint32_t)&(stream->conf->dma_desc[0]));
+	}
+#endif /* I2S_ESP32_IS_DIR_EN(tx) */
+#endif /* SOC_GDMA_SUPPORTED */
 
-rx_disable:
-	stream->stop_transfer(dev);
+unlock:
+	irq_unlock(key);
+	return err;
 }
 
-static void i2s_esp32_tx_callback(const struct device *dma_dev, void *arg, uint32_t channel,
-				  int status)
+static int i2s_esp32_restart_dma(const struct device *dev, enum i2s_dir dir)
 {
-	const struct device *dev = (const struct device *)arg;
-	struct i2s_esp32_data *const dev_data = dev->data;
-	struct i2s_esp32_stream *stream = &dev_data->tx;
-	struct queue_item item;
-	void *mem_block_tmp;
-	int err;
+	const struct i2s_esp32_cfg *dev_cfg = dev->config;
+	const struct i2s_esp32_stream *stream;
+	int err = 0;
 
-	if (status < 0) {
-		stream->state = I2S_STATE_ERROR;
-		LOG_ERR("TX bad status: %d", status);
-		goto tx_disable;
-	}
+#if !SOC_GDMA_SUPPORTED || I2S_ESP32_IS_DIR_EN(rx)
+	const i2s_hal_context_t *hal = &(dev_cfg->hal);
+#endif /* SOC_GDMA_SUPPORTED || I2S_ESP32_IS_DIR_EN(rx) */
 
-	if (stream->mem_block == NULL) {
-		if (stream->state != I2S_STATE_READY) {
-			stream->state = I2S_STATE_ERROR;
-			LOG_ERR("TX mem_block NULL");
-			goto tx_disable;
-		} else {
-			return;
-		}
+	if (dir == I2S_DIR_RX) {
+		stream = &dev_cfg->rx;
+	} else if (dir == I2S_DIR_TX) {
+		stream = &dev_cfg->tx;
+	} else {
+		LOG_ERR("Invalid DMA direction");
+		return -EINVAL;
 	}
 
-	if (stream->state == I2S_STATE_STOPPING) {
-		if (k_msgq_num_used_get(&stream->queue) == 0) {
-			stream->state = I2S_STATE_READY;
-			goto tx_disable;
-		} else if (stream->stop_without_draining == true) {
-			stream->queue_drop(stream);
-			stream->state = I2S_STATE_READY;
-			goto tx_disable;
+#if SOC_GDMA_SUPPORTED
+	uint16_t chunk_len;
+	void *src = NULL, *dst = NULL;
+
+#if I2S_ESP32_IS_DIR_EN(rx)
+	if (dir == I2S_DIR_RX) {
+		dst = stream->data->mem_block;
+
+		if (stream->data->mem_block_len < I2S_ESP32_DMA_BUFFER_MAX_SIZE) {
+			chunk_len = stream->data->mem_block_len;
+			stream->data->chunks_rem = 0;
+		} else {
+			chunk_len = I2S_ESP32_DMA_BUFFER_MAX_SIZE;
+			stream->data->chunks_rem = ((stream->data->mem_block_len +
+						     (I2S_ESP32_DMA_BUFFER_MAX_SIZE - 1)) /
+						    I2S_ESP32_DMA_BUFFER_MAX_SIZE) - 1;
 		}
-		/*else: DRAIN trigger, so continue until queue is empty*/
+		stream->data->chunk_idx = 0;
 	}
+#endif /* I2S_ESP32_IS_DIR_EN(rx) */
 
-	if (stream->last_block) {
-		stream->state = I2S_STATE_READY;
-		goto tx_disable;
+#if I2S_ESP32_IS_DIR_EN(tx)
+	if (dir == I2S_DIR_TX) {
+		src = stream->data->mem_block;
+		chunk_len = stream->data->mem_block_len;
 	}
+#endif /* I2S_ESP32_IS_DIR_EN(tx) */
 
-	err = k_msgq_get(&stream->queue, &item, K_NO_WAIT);
+	err = dma_reload(stream->conf->dma_dev, stream->conf->dma_channel, (uint32_t)src,
+			(uint32_t)dst, chunk_len);
 	if (err < 0) {
-		stream->state = I2S_STATE_ERROR;
-		goto tx_disable;
+		LOG_ERR("Failed to reload DMA channel: %"PRIu32, stream->conf->dma_channel);
+		return -EIO;
 	}
 
-	mem_block_tmp = stream->mem_block;
-
-	stream->mem_block = item.buffer;
-	stream->mem_block_len = item.size;
+#if I2S_ESP32_IS_DIR_EN(rx)
+	if (dir == I2S_DIR_RX) {
+		i2s_ll_rx_set_eof_num(hal->dev, chunk_len);
+	}
+#endif /* I2S_ESP32_IS_DIR_EN(rx) */
 
-	err = i2s_esp32_restart_dma(dev, I2S_DIR_TX);
+	err = dma_start(stream->conf->dma_dev, stream->conf->dma_channel);
 	if (err < 0) {
-		stream->state = I2S_STATE_ERROR;
-		LOG_ERR("Failed to restart TX transfer: %d", err);
-		goto tx_disable;
+		LOG_ERR("Failed to start DMA channel: %"PRIu32, stream->conf->dma_channel);
+		return -EIO;
+	}
+#else
+	err = i2s_esp32_config_dma(dev, dir, stream);
+	if (err < 0) {
+		LOG_ERR("Failed to configure DMA");
+		return -EIO;
 	}
 
-	k_mem_slab_free(stream->i2s_cfg.mem_slab, mem_block_tmp);
+#if I2S_ESP32_IS_DIR_EN(rx)
+	if (dir == I2S_DIR_RX) {
+		i2s_ll_rx_set_eof_num(hal->dev, stream->data->mem_block_len);
+		i2s_hal_rx_start_link(hal, (uint32_t)stream->conf->dma_desc);
+	}
+#endif /* I2S_ESP32_IS_DIR_EN(rx) */
 
-	return;
+#if I2S_ESP32_IS_DIR_EN(tx)
+	if (dir == I2S_DIR_TX) {
+		i2s_hal_tx_start_link(hal, (uint32_t)stream->conf->dma_desc);
+	}
+#endif /* I2S_ESP32_IS_DIR_EN(tx) */
+#endif /* SOC_GDMA_SUPPORTED */
 
-tx_disable:
-	stream->stop_transfer(dev);
+	stream->data->dma_pending = true;
+
+	return 0;
 }
 
 static int i2s_esp32_initialize(const struct device *dev)
 {
 	const struct i2s_esp32_cfg *dev_cfg = dev->config;
-	struct i2s_esp32_data *const dev_data = dev->data;
 	const struct device *clk_dev = dev_cfg->clock_dev;
+	const struct i2s_esp32_stream *stream;
 	int err;
 
-	if (dev_data->tx.dma_dev && !device_is_ready(dev_data->tx.dma_dev)) {
-		LOG_ERR("%s device not ready", dev_data->tx.dma_dev->name);
-		return -ENODEV;
-	}
-
-	if (dev_data->rx.dma_dev && !device_is_ready(dev_data->rx.dma_dev)) {
-		LOG_ERR("%s device not ready", dev_data->rx.dma_dev->name);
-		return -ENODEV;
-	}
+#if !SOC_GDMA_SUPPORTED
+	const i2s_hal_context_t *hal = &(dev_cfg->hal);
+#endif /* !SOC_GDMA_SUPPORTED */
 
 	if (!device_is_ready(clk_dev)) {
 		LOG_ERR("clock control device not ready");
@@ -473,70 +795,133 @@ static int i2s_esp32_initialize(const struct device *dev)
 		return -EIO;
 	}
 
-	if (dev_data->tx.dma_dev) {
-		err = k_msgq_alloc_init(&dev_data->tx.queue, sizeof(struct queue_item),
-					CONFIG_I2S_ESP32_TX_BLOCK_COUNT);
+#if I2S_ESP32_IS_DIR_EN(rx)
+	if (dev_cfg->rx.data && dev_cfg->rx.conf) {
+		stream = &dev_cfg->rx;
+#if SOC_GDMA_SUPPORTED
+		if (stream->conf->dma_dev && !device_is_ready(stream->conf->dma_dev)) {
+			LOG_ERR("%s device not ready", stream->conf->dma_dev->name);
+			return -ENODEV;
+		}
+#else
+		int irq_flags = ESP_PRIO_TO_FLAGS(stream->conf->irq_priority) |
+				ESP_INT_FLAGS_CHECK(stream->conf->irq_flags) |
+				ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_INTRDISABLED |
+				ESP_INTR_FLAG_SHARED;
+
+		err = esp_intr_alloc_intrstatus(stream->conf->irq_source, irq_flags,
+						(uint32_t)i2s_ll_get_intr_status_reg(hal->dev),
+						I2S_LL_RX_EVENT_MASK, i2s_esp32_rx_handler,
+						(void *)dev, &(stream->data->irq_handle));
+		if (err != 0) {
+			LOG_ERR("Could not allocate rx interrupt (err %d)", err);
+			return err;
+		}
+#endif /* SOC_GDMA_SUPPORTED */
+
+		err = k_msgq_alloc_init(&stream->data->queue, sizeof(struct queue_item),
+					CONFIG_I2S_ESP32_RX_BLOCK_COUNT);
 		if (err < 0) {
 			return err;
 		}
 	}
+#endif /* I2S_ESP32_IS_DIR_EN(rx) */
+
+#if I2S_ESP32_IS_DIR_EN(tx)
+	if (dev_cfg->tx.data && dev_cfg->tx.conf) {
+		stream = &dev_cfg->tx;
+#if SOC_GDMA_SUPPORTED
+		if (stream->conf->dma_dev && !device_is_ready(stream->conf->dma_dev)) {
+			LOG_ERR("%s device not ready", stream->conf->dma_dev->name);
+			return -ENODEV;
+		}
+#else
+		int irq_flags = ESP_PRIO_TO_FLAGS(stream->conf->irq_priority) |
+				ESP_INT_FLAGS_CHECK(stream->conf->irq_flags) |
+				ESP_INTR_FLAG_IRAM | ESP_INTR_FLAG_INTRDISABLED |
+				ESP_INTR_FLAG_SHARED;
+
+		err = esp_intr_alloc_intrstatus(stream->conf->irq_source, irq_flags,
+						(uint32_t)i2s_ll_get_intr_status_reg(hal->dev),
+						I2S_LL_TX_EVENT_MASK, i2s_esp32_tx_handler,
+						(void *)dev, &(stream->data->irq_handle));
+		if (err != 0) {
+			LOG_ERR("Could not allocate tx interrupt (err %d)", err);
+			return err;
+		}
+#endif /* SOC_GDMA_SUPPORTED */
 
-	if (dev_data->rx.dma_dev) {
-		err = k_msgq_alloc_init(&dev_data->rx.queue, sizeof(struct queue_item),
-					CONFIG_I2S_ESP32_RX_BLOCK_COUNT);
+		err = k_msgq_alloc_init(&stream->data->queue, sizeof(struct queue_item),
+					CONFIG_I2S_ESP32_TX_BLOCK_COUNT);
 		if (err < 0) {
 			return err;
 		}
 	}
+#endif /* I2S_ESP32_IS_DIR_EN(tx) */
 
-	i2s_ll_enable_clock(dev_cfg->hal_cxt.dev);
+#if !SOC_GDMA_SUPPORTED
+	i2s_ll_clear_intr_status(hal->dev, I2S_INTR_MAX);
+#endif /* !SOC_GDMA_SUPPORTED */
 
-	LOG_INF("%s initialized", dev->name);
+	LOG_DBG("%s initialized", dev->name);
 
 	return 0;
 }
 
-static int i2s_esp32_configure(const struct device *dev, enum i2s_dir dir,
-			       const struct i2s_config *i2s_cfg)
+static int i2s_esp32_configure_dir(const struct device *dev, enum i2s_dir dir,
+				   const struct i2s_esp32_stream *stream,
+				   const struct i2s_config *i2s_cfg)
 {
-	const struct i2s_esp32_cfg *const dev_cfg = dev->config;
-	struct i2s_esp32_data *const dev_data = dev->data;
-	struct i2s_esp32_stream *stream;
+	const struct i2s_esp32_cfg *dev_cfg = dev->config;
 	uint8_t data_format;
+	int err;
 
 	switch (dir) {
+#if I2S_ESP32_IS_DIR_EN(rx)
 	case I2S_DIR_RX:
-		stream = &dev_data->rx;
-		if (stream->dma_dev == NULL) {
-			LOG_ERR("RX DMA controller not available");
-			return -EINVAL;
+		if (stream->conf) {
+#if SOC_GDMA_SUPPORTED
+			if (stream->conf->dma_dev == NULL) {
+				LOG_ERR("RX DMA controller not available");
+#else
+			if (stream->conf->irq_source == -1) {
+				LOG_ERR("RX IRQ source not available");
+#endif /* SOC_GDMA_SUPPORTED */
+				return -EINVAL;
+			}
 		}
 		break;
+#endif /* I2S_ESP32_IS_DIR_EN(rx) */
+#if I2S_ESP32_IS_DIR_EN(tx)
 	case I2S_DIR_TX:
-		stream = &dev_data->tx;
-		if (stream->dma_dev == NULL) {
-			LOG_ERR("TX DMA controller not available");
-			return -EINVAL;
+		if (stream->conf) {
+#if SOC_GDMA_SUPPORTED
+			if (stream->conf->dma_dev == NULL) {
+				LOG_ERR("TX DMA controller not available");
+#else
+			if (stream->conf->irq_source == -1) {
+				LOG_ERR("TX IRQ source not available");
+#endif /* SOC_GDMA_SUPPORTED */
+				return -EINVAL;
+			}
 		}
 		break;
-	case I2S_DIR_BOTH:
-		LOG_ERR("I2S_DIR_BOTH is not supported");
-		return -ENOSYS;
+#endif /* I2S_ESP32_IS_DIR_EN(tx) */
 	default:
 		LOG_ERR("Invalid direction");
 		return -EINVAL;
 	}
 
-	if (stream->state != I2S_STATE_NOT_READY && stream->state != I2S_STATE_READY) {
-		LOG_ERR("Invalid state: %d", (int)stream->state);
+	if (stream->data->state != I2S_STATE_NOT_READY && stream->data->state != I2S_STATE_READY) {
+		LOG_ERR("Invalid state: %d", (int)stream->data->state);
 		return -EINVAL;
 	}
 
 	if (i2s_cfg->frame_clk_freq == 0U) {
-		stream->queue_drop(stream);
-		memset(&stream->i2s_cfg, 0, sizeof(struct i2s_config));
-		stream->is_slave = false;
-		stream->state = I2S_STATE_NOT_READY;
+		stream->conf->queue_drop(stream);
+		memset(&stream->data->i2s_cfg, 0, sizeof(struct i2s_config));
+		stream->data->is_slave = false;
+		stream->data->state = I2S_STATE_NOT_READY;
 		return 0;
 	}
 
@@ -572,10 +957,10 @@ static int i2s_esp32_configure(const struct device *dev, enum i2s_dir dir,
 
 	if ((i2s_cfg->options & I2S_OPT_FRAME_CLK_SLAVE) != 0 &&
 	    (i2s_cfg->options & I2S_OPT_BIT_CLK_SLAVE) != 0) {
-		stream->is_slave = true;
+		stream->data->is_slave = true;
 	} else if ((i2s_cfg->options & I2S_OPT_FRAME_CLK_SLAVE) == 0 &&
 		   (i2s_cfg->options & I2S_OPT_BIT_CLK_SLAVE) == 0) {
-		stream->is_slave = false;
+		stream->data->is_slave = false;
 	} else {
 		LOG_ERR("I2S_OPT_FRAME_CLK and I2S_OPT_BIT_CLK options must both be"
 			" MASTER or SLAVE");
@@ -590,26 +975,33 @@ static int i2s_esp32_configure(const struct device *dev, enum i2s_dir dir,
 	if (data_format == I2S_FMT_DATA_FORMAT_I2S) {
 		slot_cfg.std.ws_pol = i2s_cfg->format & I2S_FMT_FRAME_CLK_INV ? true : false;
 		slot_cfg.std.bit_shift = true;
+#if SOC_I2S_HW_VERSION_2
 		slot_cfg.std.left_align = true;
+#endif /* SOC_I2S_HW_VERSION_2 */
 	} else {
 		slot_cfg.std.ws_pol = i2s_cfg->format & I2S_FMT_FRAME_CLK_INV ? false : true;
 		slot_cfg.std.bit_shift = false;
 		if (data_format == I2S_FMT_DATA_FORMAT_LEFT_JUSTIFIED) {
+#if SOC_I2S_HW_VERSION_2
 			slot_cfg.std.left_align = true;
 		} else if (data_format == I2S_FMT_DATA_FORMAT_RIGHT_JUSTIFIED) {
 			slot_cfg.std.left_align = false;
+#endif /* SOC_I2S_HW_VERSION_2 */
 		} else {
-			LOG_ERR("Invalid data format: %u", (unsigned int)data_format);
+			LOG_ERR("Unsupported data format: %u", (unsigned int)data_format);
 		}
 	}
 	slot_cfg.std.ws_width = slot_cfg.slot_bit_width;
 	slot_cfg.std.slot_mask = I2S_STD_SLOT_BOTH;
+#if SOC_I2S_HW_VERSION_1
+	slot_cfg.std.msb_right = true;
+#elif SOC_I2S_HW_VERSION_2
 	slot_cfg.std.big_endian = false;
 	slot_cfg.std.bit_order_lsb = i2s_cfg->format & I2S_FMT_DATA_ORDER_LSB ? true : false;
+#endif /* SOC_I2S_HW_VERSION_1 */
 
-	int err;
 	i2s_hal_clock_info_t i2s_hal_clock_info;
-	i2s_hal_context_t *hal_cxt = (i2s_hal_context_t *)&dev_cfg->hal_cxt;
+	i2s_hal_context_t *hal = (i2s_hal_context_t *)&(dev_cfg->hal);
 
 	err = i2s_esp32_calculate_clock(i2s_cfg, slot_cfg.slot_bit_width, &i2s_hal_clock_info);
 	if (err != ESP_OK) {
@@ -617,149 +1009,239 @@ static int i2s_esp32_configure(const struct device *dev, enum i2s_dir dir,
 	}
 
 	if (dir == I2S_DIR_TX) {
-		if (dev_data->rx.state != I2S_STATE_NOT_READY) {
-			if (stream->is_slave && !dev_data->rx.is_slave) { /*full duplex*/
-				i2s_ll_share_bck_ws(hal_cxt->dev, true);
+#if I2S_ESP32_IS_DIR_EN(tx)
+		i2s_hal_std_enable_tx_channel(hal);
+		if (dev_cfg->rx.data != NULL && dev_cfg->rx.data->state != I2S_STATE_NOT_READY) {
+			if (stream->data->is_slave && !dev_cfg->rx.data->is_slave) { /*full duplex*/
+				i2s_ll_share_bck_ws(hal->dev, true);
 			} else {
-				i2s_ll_share_bck_ws(hal_cxt->dev, false);
+				i2s_ll_share_bck_ws(hal->dev, false);
 			}
 		} else {
-			i2s_ll_share_bck_ws(hal_cxt->dev, false);
+			i2s_ll_share_bck_ws(hal->dev, false);
 		}
 
-		i2s_hal_std_set_tx_slot(hal_cxt, stream->is_slave, &slot_cfg);
+		i2s_hal_std_set_tx_slot(hal, stream->data->is_slave, &slot_cfg);
+		i2s_hal_set_tx_clock(hal, &i2s_hal_clock_info, I2S_ESP32_CLK_SRC);
 
-		i2s_hal_set_tx_clock(hal_cxt, &i2s_hal_clock_info, I2S_ESP32_CLK_SRC);
-
-		err = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
-		if (err < 0) {
-			LOG_ERR("Pins setup failed: %d", err);
-			return -EIO;
-		}
-
-		if (dev_data->tx.state != I2S_STATE_NOT_READY) {
-			if (stream->is_slave && dev_data->rx.is_slave) {
-				i2s_ll_mclk_bind_to_tx_clk(hal_cxt->dev);
+#if SOC_I2S_HW_VERSION_2
+		if (dev_cfg->rx.data != NULL && dev_cfg->rx.data->state != I2S_STATE_NOT_READY) {
+			if (stream->data->is_slave && !dev_cfg->rx.data->is_slave) { /*full duplex*/
+				i2s_ll_mclk_bind_to_rx_clk(hal->dev);
 			}
 		}
-
-		i2s_hal_std_enable_tx_channel(hal_cxt);
+#endif /* SOC_I2S_HW_VERSION_2 */
+#endif /* I2S_ESP32_IS_DIR_EN(tx) */
 	} else if (dir == I2S_DIR_RX) {
-		if (dev_data->tx.state != I2S_STATE_NOT_READY) {
-			if (stream->is_slave && !dev_data->tx.is_slave) { /*full duplex*/
-				i2s_ll_share_bck_ws(hal_cxt->dev, true);
+#if I2S_ESP32_IS_DIR_EN(rx)
+		i2s_hal_std_enable_rx_channel(hal);
+		if (dev_cfg->tx.data != NULL && dev_cfg->tx.data->state != I2S_STATE_NOT_READY) {
+			if (stream->data->is_slave && !dev_cfg->tx.data->is_slave) { /*full duplex*/
+				i2s_ll_share_bck_ws(hal->dev, true);
 			} else {
-				i2s_ll_share_bck_ws(hal_cxt->dev, false);
+				i2s_ll_share_bck_ws(hal->dev, false);
 			}
 		} else {
-			i2s_ll_share_bck_ws(hal_cxt->dev, false);
+			i2s_ll_share_bck_ws(hal->dev, false);
 		}
 
-		i2s_hal_std_set_rx_slot(hal_cxt, stream->is_slave, &slot_cfg);
+		i2s_hal_std_set_rx_slot(hal, stream->data->is_slave, &slot_cfg);
+		i2s_hal_set_rx_clock(hal, &i2s_hal_clock_info, I2S_ESP32_CLK_SRC);
 
-		i2s_hal_set_rx_clock(hal_cxt, &i2s_hal_clock_info, I2S_ESP32_CLK_SRC);
-
-		err = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
-		if (err < 0) {
-			LOG_ERR("Pins setup failed: %d", err);
-			return -EIO;
-		}
-
-		if (dev_data->tx.state != I2S_STATE_NOT_READY) {
-			if (!stream->is_slave && !dev_data->tx.is_slave) {
-				i2s_ll_mclk_bind_to_rx_clk(hal_cxt->dev);
+#if SOC_I2S_HW_VERSION_2
+		if (dev_cfg->tx.data != NULL && dev_cfg->tx.data->state != I2S_STATE_NOT_READY) {
+			if (stream->data->is_slave && !dev_cfg->tx.data->is_slave) { /*full duplex*/
+				i2s_ll_mclk_bind_to_tx_clk(hal->dev);
 			}
 		}
+#endif /* SOC_I2S_HW_VERSION_2 */
+#endif /* I2S_ESP32_IS_DIR_EN(rx) */
+	}
 
-		i2s_hal_std_enable_rx_channel(hal_cxt);
+	err = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
+	if (err < 0) {
+		LOG_ERR("Pins setup failed: %d", err);
+		return -EIO;
 	}
-	memcpy(&stream->i2s_cfg, i2s_cfg, sizeof(struct i2s_config));
 
-	stream->state = I2S_STATE_READY;
+	memcpy(&stream->data->i2s_cfg, i2s_cfg, sizeof(struct i2s_config));
+
+	stream->data->state = I2S_STATE_READY;
 
 	return 0;
 }
 
+static int i2s_esp32_configure(const struct device *dev, enum i2s_dir dir,
+			       const struct i2s_config *i2s_cfg)
+{
+	const struct i2s_esp32_cfg *dev_cfg = dev->config;
+	const struct i2s_esp32_stream *stream;
+	int err;
+
+	switch (dir) {
+	case I2S_DIR_RX:
+#if I2S_ESP32_IS_DIR_EN(rx)
+		stream = &dev_cfg->rx;
+		if (stream) {
+			err = i2s_esp32_configure_dir(dev, I2S_DIR_RX, stream, i2s_cfg);
+		} else {
+			LOG_ERR("I2S_DIR_RX not enabled");
+			err = -EINVAL;
+		}
+#else
+		LOG_ERR("I2S_DIR_RX not enabled");
+		err = -EINVAL;
+#endif /* I2S_ESP32_IS_DIR_EN(rx) */
+		break;
+	case I2S_DIR_TX:
+#if I2S_ESP32_IS_DIR_EN(tx)
+		stream = &dev_cfg->tx;
+		if (stream) {
+			err = i2s_esp32_configure_dir(dev, I2S_DIR_TX, stream, i2s_cfg);
+		} else {
+			LOG_ERR("I2S_DIR_TX not enabled");
+			err = -EINVAL;
+		}
+#else
+		LOG_ERR("I2S_DIR_TX not enabled");
+		err = -EINVAL;
+#endif /* I2S_ESP32_IS_DIR_EN(tx) */
+		break;
+	case I2S_DIR_BOTH:
+#if I2S_ESP32_IS_DIR_EN(tx)
+		stream = &dev_cfg->tx;
+		if (stream) {
+			err = i2s_esp32_configure_dir(dev, I2S_DIR_TX, stream, i2s_cfg);
+		} else {
+			LOG_ERR("I2S_DIR_TX not enabled");
+			err = -EINVAL;
+		}
+#else
+		LOG_ERR("I2S_DIR_TX not enabled");
+		err = -EINVAL;
+#endif /* I2S_ESP32_IS_DIR_EN(tx) */
+		if (err < 0) {
+			break;
+		}
+#if I2S_ESP32_IS_DIR_EN(rx)
+		stream = &dev_cfg->rx;
+		if (stream) {
+			err = i2s_esp32_configure_dir(dev, I2S_DIR_RX, stream, i2s_cfg);
+		} else {
+			LOG_ERR("I2S_DIR_RX not enabled");
+			err = -EINVAL;
+		}
+#else
+		LOG_ERR("I2S_DIR_RX not enabled");
+		err = -EINVAL;
+#endif /* I2S_ESP32_IS_DIR_EN(rx) */
+		break;
+	default:
+		LOG_ERR("Invalid direction: %d", (int)dir);
+		return -EINVAL;
+	}
+
+	return err;
+}
+
 static const struct i2s_config *i2s_esp32_config_get(const struct device *dev, enum i2s_dir dir)
 {
-	struct i2s_esp32_data *dev_data = dev->data;
-	struct i2s_esp32_stream *stream;
+	const struct i2s_esp32_cfg *dev_cfg = dev->config;
+	const struct i2s_esp32_stream *stream;
 
 	if (dir == I2S_DIR_RX) {
-		stream = &dev_data->rx;
+#if I2S_ESP32_IS_DIR_EN(rx)
+		stream = &dev_cfg->rx;
+		if (!stream) {
+			LOG_ERR("I2S_DIR_RX not enabled");
+			return NULL;
+		}
+#else
+		LOG_ERR("I2S_DIR_RX not enabled");
+		return NULL;
+#endif /* I2S_ESP32_IS_DIR_EN(rx) */
+	} else if (dir == I2S_DIR_TX) {
+#if I2S_ESP32_IS_DIR_EN(tx)
+		stream = &dev_cfg->tx;
+		if (!stream) {
+			LOG_ERR("I2S_DIR_TX not enabled");
+			return NULL;
+		}
+#else
+		LOG_ERR("I2S_DIR_TX not enabled");
+		return NULL;
+#endif /* I2S_ESP32_IS_DIR_EN(tx) */
 	} else {
-		stream = &dev_data->tx;
+		LOG_ERR("Invalid direction: %d", (int)dir);
+		return NULL;
 	}
 
-	if (stream->state == I2S_STATE_NOT_READY) {
+	if (stream->data->state == I2S_STATE_NOT_READY) {
 		return NULL;
 	}
 
-	return &stream->i2s_cfg;
+	return &stream->data->i2s_cfg;
 }
 
-static int i2s_esp32_trigger(const struct device *dev, enum i2s_dir dir, enum i2s_trigger_cmd cmd)
+static int i2s_esp32_trigger_stream(const struct device *dev, const struct i2s_esp32_stream *stream,
+				    enum i2s_dir dir, enum i2s_trigger_cmd cmd)
 {
-	struct i2s_esp32_data *const dev_data = dev->data;
-	struct i2s_esp32_stream *stream;
-	struct dma_status dma_channel_status;
+	const struct i2s_esp32_cfg *dev_cfg = dev->config;
+	const i2s_hal_context_t *hal = &dev_cfg->hal;
 	unsigned int key;
 	int err;
 
-	switch (dir) {
-	case I2S_DIR_RX:
-		stream = &dev_data->rx;
-		break;
-	case I2S_DIR_TX:
-		stream = &dev_data->tx;
-		break;
-	case I2S_DIR_BOTH:
-		LOG_ERR("Unsupported direction: %d", (int)dir);
-		return -ENOSYS;
-	default:
-		LOG_ERR("Invalid direction: %d", (int)dir);
-		return -EINVAL;
-	}
-
 	switch (cmd) {
 	case I2S_TRIGGER_START:
-		if (stream->state != I2S_STATE_READY) {
-			LOG_ERR("START - Invalid state: %d", (int)stream->state);
+		if (stream->data->state != I2S_STATE_READY) {
+			LOG_ERR("START - Invalid state: %d", (int)stream->data->state);
 			return -EIO;
 		}
 
-		err = stream->start_transfer(dev);
+		key = irq_lock();
+
+		if (dir == I2S_DIR_RX) {
+			i2s_hal_rx_stop(hal);
+			i2s_hal_rx_reset(hal);
+#if !SOC_GDMA_SUPPORTED
+			i2s_hal_rx_reset_dma(hal);
+#endif /* !SOC_GDMA_SUPPORTED */
+			i2s_hal_rx_reset_fifo(hal);
+		} else if (dir == I2S_DIR_TX) {
+			i2s_hal_tx_stop(hal);
+			i2s_hal_tx_reset(hal);
+#if !SOC_GDMA_SUPPORTED
+			i2s_hal_tx_reset_dma(hal);
+#endif /* !SOC_GDMA_SUPPORTED */
+			i2s_hal_tx_reset_fifo(hal);
+		}
+
+		err = stream->conf->start_transfer(dev);
 		if (err < 0) {
 			LOG_ERR("START - Transfer start failed: %d", err);
+			irq_unlock(key);
 			return -EIO;
 		}
-		stream->last_block = false;
-		stream->state = I2S_STATE_RUNNING;
+		stream->data->last_block = false;
+		stream->data->state = I2S_STATE_RUNNING;
+		irq_unlock(key);
 		break;
 
 	case I2S_TRIGGER_STOP:
 		key = irq_lock();
-		if (stream->state != I2S_STATE_RUNNING) {
-			irq_unlock(key);
-			LOG_ERR("STOP - Invalid state: %d", (int)stream->state);
-			return -EIO;
-		}
-
-		err = dma_get_status(stream->dma_dev, stream->dma_channel, &dma_channel_status);
-		if (err < 0) {
+		if (stream->data->state != I2S_STATE_RUNNING) {
 			irq_unlock(key);
-			LOG_ERR("Unable to get DMA channel[%d] status: %d",
-				(int)stream->dma_channel, err);
+			LOG_ERR("STOP - Invalid state: %d", (int)stream->data->state);
 			return -EIO;
 		}
 
-		if (dma_channel_status.busy) {
-			stream->stop_without_draining = true;
-			stream->state = I2S_STATE_STOPPING;
+		if (stream->data->dma_pending) {
+			stream->data->stop_without_draining = true;
+			stream->data->state = I2S_STATE_STOPPING;
 		} else {
-			stream->stop_transfer(dev);
-			stream->last_block = true;
-			stream->state = I2S_STATE_READY;
+			stream->conf->stop_transfer(dev);
+			stream->data->last_block = true;
+			stream->data->state = I2S_STATE_READY;
 		}
 
 		irq_unlock(key);
@@ -767,63 +1249,58 @@ static int i2s_esp32_trigger(const struct device *dev, enum i2s_dir dir, enum i2
 
 	case I2S_TRIGGER_DRAIN:
 		key = irq_lock();
-		if (stream->state != I2S_STATE_RUNNING) {
+		if (stream->data->state != I2S_STATE_RUNNING) {
 			irq_unlock(key);
-			LOG_ERR("DRAIN - Invalid state: %d", (int)stream->state);
-			return -EIO;
-		}
-
-		err = dma_get_status(stream->dma_dev, stream->dma_channel, &dma_channel_status);
-		if (err < 0) {
-			irq_unlock(key);
-			LOG_ERR("Unable to get DMA channel[%d] status: %d",
-				(int)stream->dma_channel, err);
+			LOG_ERR("DRAIN - Invalid state: %d", (int)stream->data->state);
 			return -EIO;
 		}
 
+#if I2S_ESP32_IS_DIR_EN(tx)
 		if (dir == I2S_DIR_TX) {
-			if (k_msgq_num_used_get(&stream->queue) > 0 || dma_channel_status.busy) {
-				stream->stop_without_draining = false;
-				stream->state = I2S_STATE_STOPPING;
+			if (k_msgq_num_used_get(&stream->data->queue) > 0 ||
+			    stream->data->dma_pending) {
+				stream->data->stop_without_draining = false;
+				stream->data->state = I2S_STATE_STOPPING;
 			} else {
-				stream->stop_transfer(dev);
-				stream->state = I2S_STATE_READY;
+				stream->conf->stop_transfer(dev);
+				stream->data->state = I2S_STATE_READY;
 			}
-		} else if (dir == I2S_DIR_RX) {
-			if (dma_channel_status.busy) {
-				stream->stop_without_draining = true;
-				stream->state = I2S_STATE_STOPPING;
+		}
+#endif /* I2S_ESP32_IS_DIR_EN(tx) */
+
+#if I2S_ESP32_IS_DIR_EN(rx)
+		if (dir == I2S_DIR_RX) {
+			if (stream->data->dma_pending) {
+				stream->data->stop_without_draining = true;
+				stream->data->state = I2S_STATE_STOPPING;
 			} else {
-				stream->stop_transfer(dev);
-				stream->last_block = true;
-				stream->state = I2S_STATE_READY;
+				stream->conf->stop_transfer(dev);
+				stream->data->last_block = true;
+				stream->data->state = I2S_STATE_READY;
 			}
-		} else {
-			irq_unlock(key);
-			LOG_ERR("Invalid direction: %d", (int)dir);
-			return -EINVAL;
 		}
+#endif /* I2S_ESP32_IS_DIR_EN(rx) */
 
 		irq_unlock(key);
 		break;
 
 	case I2S_TRIGGER_DROP:
-		if (stream->state == I2S_STATE_NOT_READY) {
-			LOG_ERR("DROP - invalid state: %d", (int)stream->state);
+		if (stream->data->state == I2S_STATE_NOT_READY) {
+			LOG_ERR("DROP - invalid state: %d", (int)stream->data->state);
 			return -EIO;
 		}
-		stream->stop_transfer(dev);
-		stream->queue_drop(stream);
-		stream->state = I2S_STATE_READY;
+		stream->conf->stop_transfer(dev);
+		stream->conf->queue_drop(stream);
+		stream->data->state = I2S_STATE_READY;
 		break;
 
 	case I2S_TRIGGER_PREPARE:
-		if (stream->state != I2S_STATE_ERROR) {
-			LOG_ERR("PREPARE - invalid state: %d", (int)stream->state);
+		if (stream->data->state != I2S_STATE_ERROR) {
+			LOG_ERR("PREPARE - invalid state: %d", (int)stream->data->state);
 			return -EIO;
 		}
-		stream->queue_drop(stream);
-		stream->state = I2S_STATE_READY;
+		stream->conf->queue_drop(stream);
+		stream->data->state = I2S_STATE_READY;
 		break;
 
 	default:
@@ -834,22 +1311,105 @@ static int i2s_esp32_trigger(const struct device *dev, enum i2s_dir dir, enum i2
 	return 0;
 }
 
+static int i2s_esp32_trigger(const struct device *dev, enum i2s_dir dir, enum i2s_trigger_cmd cmd)
+{
+	const struct i2s_esp32_cfg *dev_cfg = dev->config;
+	const struct i2s_esp32_stream *stream;
+	int err;
+
+	switch (dir) {
+	case I2S_DIR_RX:
+#if I2S_ESP32_IS_DIR_EN(rx)
+		stream = &dev_cfg->rx;
+		if (stream) {
+			err = i2s_esp32_trigger_stream(dev, stream, I2S_DIR_RX, cmd);
+		} else {
+			LOG_ERR("I2S_DIR_RX not enabled");
+			err = -EINVAL;
+		}
+#else
+		LOG_ERR("I2S_DIR_RX not enabled");
+		err = -EINVAL;
+#endif /* I2S_ESP32_IS_DIR_EN(rx) */
+		break;
+	case I2S_DIR_TX:
+#if I2S_ESP32_IS_DIR_EN(tx)
+		stream = &dev_cfg->tx;
+		if (stream) {
+			err = i2s_esp32_trigger_stream(dev, stream, I2S_DIR_TX, cmd);
+		} else {
+			LOG_ERR("I2S_DIR_TX not enabled");
+			err = -EINVAL;
+		}
+#else
+		LOG_ERR("I2S_DIR_TX not enabled");
+		err = -EINVAL;
+#endif /* I2S_ESP32_IS_DIR_EN(tx) */
+		break;
+	case I2S_DIR_BOTH:
+#if I2S_ESP32_IS_DIR_EN(tx)
+		stream = &dev_cfg->tx;
+		if (stream) {
+			err = i2s_esp32_trigger_stream(dev, stream, I2S_DIR_TX, cmd);
+		} else {
+			LOG_ERR("I2S_DIR_TX not enabled");
+			err = -EINVAL;
+		}
+#else
+		LOG_ERR("I2S_DIR_TX not enabled");
+		err = -EINVAL;
+#endif /* I2S_ESP32_IS_DIR_EN(tx) */
+		if (err < 0) {
+			break;
+		}
+#if I2S_ESP32_IS_DIR_EN(rx)
+		stream = &dev_cfg->rx;
+		if (stream) {
+			err = i2s_esp32_trigger_stream(dev, stream, I2S_DIR_RX, cmd);
+		} else {
+			LOG_ERR("I2S_DIR_RX not enabled");
+			err = -EINVAL;
+		}
+#else
+		LOG_ERR("I2S_DIR_RX not enabled");
+		err = -EINVAL;
+#endif /* I2S_ESP32_IS_DIR_EN(rx) */
+		break;
+	default:
+		LOG_ERR("Invalid direction: %d", (int)dir);
+		err = -EINVAL;
+	}
+
+	return err;
+}
+
 static int i2s_esp32_read(const struct device *dev, void **mem_block, size_t *size)
 {
-	struct i2s_esp32_data *const dev_data = dev->data;
+#if I2S_ESP32_IS_DIR_EN(rx)
+	const struct i2s_esp32_cfg *dev_cfg = dev->config;
+	const struct i2s_esp32_stream *stream = &dev_cfg->rx;
 	struct queue_item item;
 	int err;
 
-	if (dev_data->rx.state == I2S_STATE_NOT_READY) {
-		LOG_ERR("RX invalid state: %d", (int)dev_data->rx.state);
+	if (!stream) {
+		*mem_block = NULL;
+		*size = 0;
+
+		LOG_ERR("I2S_DIR_RX not enabled");
+		return -EINVAL;
+	}
+
+	if (stream->data->state == I2S_STATE_NOT_READY) {
+		LOG_ERR("RX invalid state: %d", (int)stream->data->state);
 		return -EIO;
-	} else if (dev_data->rx.state == I2S_STATE_ERROR &&
-		   k_msgq_num_used_get(&dev_data->rx.queue) == 0) {
+	} else if (stream->data->state == I2S_STATE_ERROR &&
+		   k_msgq_num_used_get(&stream->data->queue) == 0) {
 		LOG_ERR("RX queue empty");
 		return -EIO;
 	}
 
-	err = k_msgq_get(&dev_data->rx.queue, &item, K_MSEC(dev_data->rx.i2s_cfg.timeout));
+	err = k_msgq_get(&stream->data->queue, &item,
+			 K_MSEC(stream->data->i2s_cfg.timeout));
 	if (err < 0) {
 		LOG_ERR("RX queue empty");
 		return err;
@@ -859,32 +1419,52 @@ static int i2s_esp32_read(const struct device *dev, void **mem_block, size_t *si
 	*size = item.size;
 
 	return 0;
+#else
+	*mem_block = NULL;
+	*size = 0;
+
+	LOG_ERR("I2S_DIR_RX not enabled");
+	return -EINVAL;
+#endif /* I2S_ESP32_IS_DIR_EN(rx) */
 }
 
 static int i2s_esp32_write(const struct device *dev, void *mem_block, size_t size)
 {
-	struct i2s_esp32_data *const dev_data = dev->data;
+#if I2S_ESP32_IS_DIR_EN(tx)
+	const struct i2s_esp32_cfg *dev_cfg = dev->config;
+	const struct i2s_esp32_stream *stream = &dev_cfg->tx;
 	int err;
 
-	if (dev_data->tx.state != I2S_STATE_RUNNING && dev_data->tx.state != I2S_STATE_READY) {
-		LOG_ERR("TX Invalid state: %d", (int)dev_data->tx.state);
+	if (!stream) {
+		LOG_ERR("I2S_DIR_TX not enabled");
+		return -EINVAL;
+	}
+
+	if (stream->data->state != I2S_STATE_RUNNING &&
+	    stream->data->state != I2S_STATE_READY) {
+		LOG_ERR("TX Invalid state: %d", (int)stream->data->state);
 		return -EIO;
 	}
 
-	if (size > dev_data->tx.i2s_cfg.block_size) {
-		LOG_ERR("Max write size is: %u", (unsigned int)dev_data->tx.i2s_cfg.block_size);
+	if (size > stream->data->i2s_cfg.block_size) {
+		LOG_ERR("Max write size is: %zu", stream->data->i2s_cfg.block_size);
 		return -EINVAL;
 	}
 
 	struct queue_item item = {.buffer = mem_block, .size = size};
 
-	err = k_msgq_put(&dev_data->tx.queue, &item, K_MSEC(dev_data->tx.i2s_cfg.timeout));
+	err = k_msgq_put(&stream->data->queue, &item,
+			 K_MSEC(stream->data->i2s_cfg.timeout));
 	if (err < 0) {
 		LOG_ERR("TX queue full");
 		return err;
 	}
 
 	return 0;
+#else
+	LOG_ERR("I2S_DIR_TX not enabled");
+	return -EINVAL;
+#endif /* I2S_ESP32_IS_DIR_EN(tx) */
 }
 
 static DEVICE_API(i2s, i2s_esp32_driver_api) = {
@@ -892,36 +1472,79 @@ static DEVICE_API(i2s, i2s_esp32_driver_api) = {
 	.config_get = i2s_esp32_config_get,
 	.trigger = i2s_esp32_trigger,
 	.read = i2s_esp32_read,
-	.write = i2s_esp32_write,
+	.write = i2s_esp32_write
 };
 
-#define I2S_ESP32_DMA_CHANNEL_INIT(index, dir)                                                     \
-	.dir = {.state = I2S_STATE_NOT_READY,                                                      \
+#define I2S_ESP32_STREAM_DECLARE_DMA_DESC(index, dir)                                              \
+	lldesc_t i2s_esp32_stream_##index##_##dir##_dma_desc[CONFIG_I2S_ESP32_DMA_DESC_NUM_MAX]
+
+#define I2S_ESP32_STREAM_DECL_DMA_DESC(index, dir)                                                 \
+	COND_CODE_1(DT_INST_IRQ_HAS_NAME(index, dir),                                              \
+		    (I2S_ESP32_STREAM_DECLARE_DMA_DESC(index, dir)), ())
+
+#define I2S_ESP32_STREAM_DECLARE(index, dir)                                                       \
+	struct i2s_esp32_stream_data i2s_esp32_stream_##index##_##dir##_data = {                   \
+		.state = I2S_STATE_NOT_READY,                                                      \
 		.is_slave = false,                                                                 \
-		.dma_dev = UTIL_AND(DT_INST_DMAS_HAS_NAME(index, dir),                             \
-				    DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(index, dir))),         \
-		.dma_channel = UTIL_AND(DT_INST_DMAS_HAS_NAME(index, dir),                         \
-					DT_INST_DMAS_CELL_BY_NAME(index, dir, channel)),           \
+		.i2s_cfg = {0},                                                                    \
 		.mem_block = NULL,                                                                 \
 		.mem_block_len = 0,                                                                \
+		.last_block = false,                                                               \
+		.stop_without_draining = false,                                                    \
+		.queue = {},                                                                       \
+		.irq_handle = NULL,                                                                \
+		.dma_pending = false                                                               \
+	};                                                                                         \
+                                                                                                   \
+	const struct i2s_esp32_stream_conf i2s_esp32_stream_##index##_##dir##_conf = {             \
+		.queue_drop = i2s_esp32_queue_drop,                                                \
 		.start_transfer = i2s_esp32_##dir##_start_transfer,                                \
 		.stop_transfer = i2s_esp32_##dir##_stop_transfer,                                  \
-		.queue_drop = i2s_esp32_queue_drop,                                                \
-		.last_block = false,                                                               \
-		.stop_without_draining = false}
+		.dma_dev = UTIL_AND(DT_INST_DMAS_HAS_NAME(index, dir),                             \
+				    DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(index, dir))),         \
+		.dma_channel = UTIL_AND(DT_INST_DMAS_HAS_NAME(index, dir),                         \
+					DT_INST_DMAS_CELL_BY_NAME(index, dir, channel)),           \
+		.dma_desc = UTIL_AND(DT_INST_IRQ_HAS_NAME(index, dir),                             \
+					i2s_esp32_stream_##index##_##dir##_dma_desc),              \
+		.irq_source = COND_CODE_1(DT_INST_IRQ_HAS_NAME(index, dir),                        \
+					  (DT_INST_IRQ_BY_NAME(index, dir, irq)), (-1)),           \
+		.irq_priority = COND_CODE_1(DT_INST_IRQ_HAS_NAME(index, dir),                      \
+					    (DT_INST_IRQ_BY_NAME(index, dir, priority)), (-1)),    \
+		.irq_flags = COND_CODE_1(DT_INST_IRQ_HAS_NAME(index, dir),                         \
+					 (DT_INST_IRQ_BY_NAME(index, dir, flags)), (-1))           \
+	}
+
+#define I2S_ESP32_STREAM_DECL(index, dir) \
+	COND_CODE_1(UTIL_OR(DT_INST_DMAS_HAS_NAME(index, dir), DT_INST_IRQ_HAS_NAME(index, dir)),  \
+		    (I2S_ESP32_STREAM_DECLARE(index, dir)), ())
+
+#define I2S_ESP32_STREAM_INIT(index, dir)                                                          \
+	.dir = {.conf = UTIL_AND(UTIL_OR(DT_INST_DMAS_HAS_NAME(index, dir),                        \
+					 DT_INST_IRQ_HAS_NAME(index, dir)),                        \
+				 &i2s_esp32_stream_##index##_##dir##_conf),                        \
+		.data = UTIL_AND(UTIL_OR(DT_INST_DMAS_HAS_NAME(index, dir),                        \
+					 DT_INST_IRQ_HAS_NAME(index, dir)),                        \
+				 &i2s_esp32_stream_##index##_##dir##_data)}
 
 #define I2S_ESP32_INIT(index)                                                                      \
 	PINCTRL_DT_INST_DEFINE(index);                                                             \
                                                                                                    \
+	I2S_ESP32_STREAM_DECL_DMA_DESC(index, rx);                                                 \
+	I2S_ESP32_STREAM_DECL(index, rx);                                                          \
+                                                                                                   \
+	I2S_ESP32_STREAM_DECL_DMA_DESC(index, tx);                                                 \
+	I2S_ESP32_STREAM_DECL(index, tx);                                                          \
+                                                                                                   \
+	static struct i2s_esp32_data i2s_esp32_data_##index = {                                    \
+		.clk_info = {0}};                                                                  \
+                                                                                                   \
 	static const struct i2s_esp32_cfg i2s_esp32_config_##index = {                             \
 		.unit = DT_PROP(DT_DRV_INST(index), unit),                                         \
-		.hal_cxt = {.dev = (i2s_dev_t *)DT_INST_REG_ADDR(index)},                          \
+		.hal = {.dev = (i2s_dev_t *)DT_INST_REG_ADDR(index)},                              \
 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index),                                     \
 		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(index)),                            \
-		.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(index, offset)};       \
-                                                                                                   \
-	static struct i2s_esp32_data i2s_esp32_data_##index = {                                    \
-		I2S_ESP32_DMA_CHANNEL_INIT(index, rx), I2S_ESP32_DMA_CHANNEL_INIT(index, tx)};     \
+		.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(index, offset),        \
+		I2S_ESP32_STREAM_INIT(index, rx), I2S_ESP32_STREAM_INIT(index, tx)};               \
                                                                                                    \
 	DEVICE_DT_INST_DEFINE(index, &i2s_esp32_initialize, NULL, &i2s_esp32_data_##index,         \
 			      &i2s_esp32_config_##index, POST_KERNEL, CONFIG_I2S_INIT_PRIORITY,    \
diff --git a/drivers/i2s/i2s_litex.c b/drivers/i2s/i2s_litex.c
index 06bc4d5bc1d..4e759e6755f 100644
--- a/drivers/i2s/i2s_litex.c
+++ b/drivers/i2s/i2s_litex.c
@@ -260,7 +260,7 @@ static void i2s_copy_to_fifo(uint8_t *src, size_t size, int sample_width,
 /*
  * Get data from the queue
  */
-static int queue_get(struct ring_buf *rb, void **mem_block, size_t *size)
+static int queue_get(struct ring_buffer *rb, void **mem_block, size_t *size)
 {
 	unsigned int key;
 
@@ -282,7 +282,7 @@ static int queue_get(struct ring_buf *rb, void **mem_block, size_t *size)
 /*
  * Put data in the queue
  */
-static int queue_put(struct ring_buf *rb, void *mem_block, size_t size)
+static int queue_put(struct ring_buffer *rb, void *mem_block, size_t size)
 {
 	uint16_t head_next;
 	unsigned int key;
diff --git a/drivers/i2s/i2s_litex.h b/drivers/i2s/i2s_litex.h
index c373371cf9a..9fcae9f98c5 100644
--- a/drivers/i2s/i2s_litex.h
+++ b/drivers/i2s/i2s_litex.h
@@ -70,7 +70,7 @@ struct queue_item {
 };
 
 /* Minimal ring buffer implementation */
-struct ring_buf {
+struct ring_buffer {
 	struct queue_item *buf;
 	uint16_t len;
 	uint16_t head;
@@ -81,7 +81,7 @@ struct stream {
 	int32_t state;
 	struct k_sem sem;
 	struct i2s_config cfg;
-	struct ring_buf mem_block_queue;
+	struct ring_buffer mem_block_queue;
 	void *mem_block;
 };
 
diff --git a/drivers/i2s/i2s_ll_stm32.c b/drivers/i2s/i2s_ll_stm32.c
index 24df83639a4..bbf7e60de62 100644
--- a/drivers/i2s/i2s_ll_stm32.c
+++ b/drivers/i2s/i2s_ll_stm32.c
@@ -23,79 +23,49 @@
 #include <zephyr/irq.h>
 LOG_MODULE_REGISTER(i2s_ll_stm32);
 
-#define MODULO_INC(val, max) { val = (++val < max) ? val : 0; }
-
 static unsigned int div_round_closest(uint32_t dividend, uint32_t divisor)
 {
 	return (dividend + (divisor / 2U)) / divisor;
 }
 
-static bool queue_is_empty(struct ring_buf *rb)
+static bool queue_is_empty(struct k_msgq *q)
 {
-	unsigned int key;
-
-	key = irq_lock();
-
-	if (rb->tail != rb->head) {
-		/* Ring buffer is not empty */
-		irq_unlock(key);
-		return false;
-	}
-
-	irq_unlock(key);
-
-	return true;
+	return (k_msgq_num_used_get(q) == 0) ? true : false;
 }
 
 /*
  * Get data from the queue
  */
-static int queue_get(struct ring_buf *rb, void **mem_block, size_t *size)
+static int queue_get(struct k_msgq *q, void **mem_block, size_t *size, int32_t timeout)
 {
-	unsigned int key;
+	struct queue_item item;
+	int result = k_msgq_get(q, &item, SYS_TIMEOUT_MS(timeout));
 
-	key = irq_lock();
-
-	if (queue_is_empty(rb) == true) {
-		irq_unlock(key);
-		return -ENOMEM;
+	if (result == 0) {
+		*mem_block = item.mem_block;
+		*size = item.size;
 	}
-
-	*mem_block = rb->buf[rb->tail].mem_block;
-	*size = rb->buf[rb->tail].size;
-	MODULO_INC(rb->tail, rb->len);
-
-	irq_unlock(key);
-
-	return 0;
+	return result;
 }
 
 /*
  * Put data in the queue
  */
-static int queue_put(struct ring_buf *rb, void *mem_block, size_t size)
+static int queue_put(struct k_msgq *q, void *mem_block, size_t size, int32_t timeout)
 {
-	uint16_t head_next;
-	unsigned int key;
+	struct queue_item item = {.mem_block = mem_block, .size = size};
 
-	key = irq_lock();
+	return k_msgq_put(q, &item, SYS_TIMEOUT_MS(timeout));
+}
 
-	head_next = rb->head;
-	MODULO_INC(head_next, rb->len);
+static void stream_queue_drop(struct stream *s)
+{
+	size_t size;
+	void *mem_block;
 
-	if (head_next == rb->tail) {
-		/* Ring buffer is full */
-		irq_unlock(key);
-		return -ENOMEM;
+	while (queue_get(s->msgq, &mem_block, &size, 0) == 0) {
+		k_mem_slab_free(s->cfg.mem_slab, mem_block);
 	}
-
-	rb->buf[rb->head].mem_block = mem_block;
-	rb->buf[rb->head].size = size;
-	rb->head = head_next;
-
-	irq_unlock(key);
-
-	return 0;
 }
 
 static int i2s_stm32_enable_clock(const struct device *dev)
@@ -224,7 +194,7 @@ static int i2s_stm32_configure(const struct device *dev, enum i2s_dir dir,
 	}
 
 	if (i2s_cfg->frame_clk_freq == 0U) {
-		stream->queue_drop(stream);
+		stream_queue_drop(stream);
 		memset(&stream->cfg, 0, sizeof(struct i2s_config));
 		stream->state = I2S_STATE_NOT_READY;
 		return 0;
@@ -385,7 +355,7 @@ static int i2s_stm32_trigger(const struct device *dev, enum i2s_dir dir,
 		}
 
 		if (dir == I2S_DIR_TX) {
-			if ((queue_is_empty(&stream->mem_block_queue) == false) ||
+			if ((queue_is_empty(stream->msgq) == false) ||
 						(ll_func_i2s_dma_busy(cfg->i2s))) {
 				stream->state = I2S_STATE_STOPPING;
 				/*
@@ -412,7 +382,7 @@ static int i2s_stm32_trigger(const struct device *dev, enum i2s_dir dir,
 			return -EIO;
 		}
 		stream->stream_disable(stream, dev);
-		stream->queue_drop(stream);
+		stream_queue_drop(stream);
 		stream->state = I2S_STATE_READY;
 		break;
 
@@ -422,7 +392,7 @@ static int i2s_stm32_trigger(const struct device *dev, enum i2s_dir dir,
 			return -EIO;
 		}
 		stream->state = I2S_STATE_READY;
-		stream->queue_drop(stream);
+		stream_queue_drop(stream);
 		break;
 
 	default:
@@ -444,16 +414,8 @@ static int i2s_stm32_read(const struct device *dev, void **mem_block,
 		return -EIO;
 	}
 
-	if (dev_data->rx.state != I2S_STATE_ERROR) {
-		ret = k_sem_take(&dev_data->rx.sem,
-				 SYS_TIMEOUT_MS(dev_data->rx.cfg.timeout));
-		if (ret < 0) {
-			return ret;
-		}
-	}
-
 	/* Get data from the beginning of RX queue */
-	ret = queue_get(&dev_data->rx.mem_block_queue, mem_block, size);
+	ret = queue_get(dev_data->rx.msgq, mem_block, size, dev_data->rx.cfg.timeout);
 	if (ret < 0) {
 		return -EIO;
 	}
@@ -465,7 +427,6 @@ static int i2s_stm32_write(const struct device *dev, void *mem_block,
 			   size_t size)
 {
 	struct i2s_stm32_data *const dev_data = dev->data;
-	int ret;
 
 	if (dev_data->tx.state != I2S_STATE_RUNNING &&
 	    dev_data->tx.state != I2S_STATE_READY) {
@@ -473,14 +434,8 @@ static int i2s_stm32_write(const struct device *dev, void *mem_block,
 		return -EIO;
 	}
 
-	ret = k_sem_take(&dev_data->tx.sem,
-			 SYS_TIMEOUT_MS(dev_data->tx.cfg.timeout));
-	if (ret < 0) {
-		return ret;
-	}
-
 	/* Add data to the end of the TX queue */
-	return queue_put(&dev_data->tx.mem_block_queue, mem_block, size);
+	return queue_put(dev_data->tx.msgq, mem_block, size, dev_data->tx.cfg.timeout);
 }
 
 static DEVICE_API(i2s, i2s_stm32_driver_api) = {
@@ -604,13 +559,12 @@ static void dma_rx_callback(const struct device *dma_dev, void *arg,
 	sys_cache_data_invd_range(mblk_tmp, stream->cfg.block_size);
 
 	/* All block data received */
-	ret = queue_put(&stream->mem_block_queue, mblk_tmp,
-			stream->cfg.block_size);
+	ret = queue_put(stream->msgq, mblk_tmp,
+			stream->cfg.block_size, 0);
 	if (ret < 0) {
 		stream->state = I2S_STATE_ERROR;
 		goto rx_disable;
 	}
-	k_sem_give(&stream->sem);
 
 	/* Stop reception if we were requested */
 	if (stream->state == I2S_STATE_STOPPING) {
@@ -659,8 +613,8 @@ static void dma_tx_callback(const struct device *dma_dev, void *arg,
 		 * as stated in zephyr i2s specification, in case of DRAIN command
 		 * send all data in the transmit queue and stop the transmission.
 		 */
-		if (queue_is_empty(&stream->mem_block_queue) == true) {
-			stream->queue_drop(stream);
+		if (queue_is_empty(stream->msgq) == true) {
+			stream_queue_drop(stream);
 			stream->state = I2S_STATE_READY;
 			goto tx_disable;
 		} else if (stream->tx_stop_for_drain == false) {
@@ -681,8 +635,8 @@ static void dma_tx_callback(const struct device *dma_dev, void *arg,
 	}
 
 	/* Prepare to send the next data block */
-	ret = queue_get(&stream->mem_block_queue, &stream->mem_block,
-			&mem_block_size);
+	ret = queue_get(stream->msgq, &stream->mem_block,
+			&mem_block_size, 0);
 	if (ret < 0) {
 		if (stream->state == I2S_STATE_STOPPING) {
 			stream->state = I2S_STATE_READY;
@@ -691,7 +645,6 @@ static void dma_tx_callback(const struct device *dma_dev, void *arg,
 		}
 		goto tx_disable;
 	}
-	k_sem_give(&stream->sem);
 
 	/* Assure cache coherency before DMA read operation */
 	sys_cache_data_flush_range(stream->mem_block, mem_block_size);
@@ -765,10 +718,6 @@ static int i2s_stm32_initialize(const struct device *dev)
 
 	cfg->irq_config(dev);
 
-	k_sem_init(&dev_data->rx.sem, 0, CONFIG_I2S_STM32_RX_BLOCK_COUNT);
-	k_sem_init(&dev_data->tx.sem, CONFIG_I2S_STM32_TX_BLOCK_COUNT,
-		   CONFIG_I2S_STM32_TX_BLOCK_COUNT);
-
 	for (i = 0; i < STM32_DMA_NUM_CHANNELS; i++) {
 		active_dma_rx_channel[i] = NULL;
 		active_dma_tx_channel[i] = NULL;
@@ -847,12 +796,11 @@ static int tx_stream_start(struct stream *stream, const struct device *dev)
 	size_t mem_block_size;
 	int ret;
 
-	ret = queue_get(&stream->mem_block_queue, &stream->mem_block,
-			&mem_block_size);
+	ret = queue_get(stream->msgq, &stream->mem_block,
+			&mem_block_size, 0);
 	if (ret < 0) {
 		return ret;
 	}
-	k_sem_give(&stream->sem);
 
 	/* Assure cache coherency before DMA read operation */
 	sys_cache_data_flush_range(stream->mem_block, mem_block_size);
@@ -948,34 +896,6 @@ static void tx_stream_disable(struct stream *stream, const struct device *dev)
 	active_dma_tx_channel[stream->dma_channel] = NULL;
 }
 
-static void rx_queue_drop(struct stream *stream)
-{
-	size_t size;
-	void *mem_block;
-
-	while (queue_get(&stream->mem_block_queue, &mem_block, &size) == 0) {
-		k_mem_slab_free(stream->cfg.mem_slab, mem_block);
-	}
-
-	k_sem_reset(&stream->sem);
-}
-
-static void tx_queue_drop(struct stream *stream)
-{
-	size_t size;
-	void *mem_block;
-	unsigned int n = 0U;
-
-	while (queue_get(&stream->mem_block_queue, &mem_block, &size) == 0) {
-		k_mem_slab_free(stream->cfg.mem_slab, mem_block);
-		n++;
-	}
-
-	for (; n > 0; n--) {
-		k_sem_give(&stream->sem);
-	}
-}
-
 static const struct device *get_dev_from_rx_dma_channel(uint32_t dma_channel)
 {
 	return active_dma_rx_channel[dma_channel];
@@ -1011,9 +931,7 @@ static const struct device *get_dev_from_tx_dma_channel(uint32_t dma_channel)
 				STM32_DMA_FEATURES(index, dir)),	\
 	.stream_start = dir##_stream_start,				\
 	.stream_disable = dir##_stream_disable,				\
-	.queue_drop = dir##_queue_drop,					\
-	.mem_block_queue.buf = dir##_##index##_ring_buf,		\
-	.mem_block_queue.len = ARRAY_SIZE(dir##_##index##_ring_buf)	\
+	.msgq = &dir##_##index##_queue,		\
 }
 
 #define I2S_STM32_INIT(index)							\
@@ -1034,8 +952,8 @@ static const struct i2s_stm32_cfg i2s_stm32_config_##index = {		\
 	.master_clk_sel = DT_INST_PROP(index, mck_enabled)		\
 };									\
 									\
-struct queue_item rx_##index##_ring_buf[CONFIG_I2S_STM32_RX_BLOCK_COUNT + 1];\
-struct queue_item tx_##index##_ring_buf[CONFIG_I2S_STM32_TX_BLOCK_COUNT + 1];\
+K_MSGQ_DEFINE(rx_##index##_queue, sizeof(struct queue_item), CONFIG_I2S_STM32_RX_BLOCK_COUNT, 4);\
+K_MSGQ_DEFINE(tx_##index##_queue, sizeof(struct queue_item), CONFIG_I2S_STM32_TX_BLOCK_COUNT, 4);\
 									\
 static struct i2s_stm32_data i2s_stm32_data_##index = {			\
 	UTIL_AND(DT_INST_DMAS_HAS_NAME(index, rx),			\
diff --git a/drivers/i2s/i2s_ll_stm32.h b/drivers/i2s/i2s_ll_stm32.h
index 1f9d0eb0113..439fefafaf9 100644
--- a/drivers/i2s/i2s_ll_stm32.h
+++ b/drivers/i2s/i2s_ll_stm32.h
@@ -12,14 +12,6 @@ struct queue_item {
 	size_t size;
 };
 
-/* Minimal ring buffer implementation */
-struct ring_buf {
-	struct queue_item *buf;
-	uint16_t len;
-	uint16_t head;
-	uint16_t tail;
-};
-
 /* Device constant configuration parameters */
 struct i2s_stm32_cfg {
 	SPI_TypeDef *i2s;
@@ -32,7 +24,7 @@ struct i2s_stm32_cfg {
 
 struct stream {
 	int32_t state;
-	struct k_sem sem;
+	struct k_msgq *msgq;
 
 	const struct device *dev_dma;
 	uint32_t dma_channel;
@@ -44,13 +36,11 @@ struct stream {
 	bool tx_stop_for_drain;
 
 	struct i2s_config cfg;
-	struct ring_buf mem_block_queue;
 	void *mem_block;
 	bool last_block;
 	bool master;
 	int (*stream_start)(struct stream *, const struct device *dev);
 	void (*stream_disable)(struct stream *, const struct device *dev);
-	void (*queue_drop)(struct stream *);
 };
 
 /* Device run time data */
diff --git a/drivers/i2s/i2s_mcux_sai.c b/drivers/i2s/i2s_mcux_sai.c
index 8addd0a00d4..2cfd9da8fbb 100644
--- a/drivers/i2s/i2s_mcux_sai.c
+++ b/drivers/i2s/i2s_mcux_sai.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2021,2023-2024 NXP Semiconductor INC.
+ * Copyright 2021,2023-2025 NXP Semiconductor INC.
  * All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
@@ -9,6 +9,8 @@
  * @brief I2S bus (SAI) driver for NXP i.MX RT series.
  */
 
+#define DT_DRV_COMPAT nxp_mcux_i2s
+
 #include <errno.h>
 #include <string.h>
 #include <zephyr/sys/__assert.h>
@@ -21,26 +23,30 @@
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/dt-bindings/clock/imx_ccm.h>
 #include <zephyr/sys/barrier.h>
+#include <zephyr/device.h>
 #include <soc.h>
 
-#include "i2s_mcux_sai.h"
+#include <fsl_sai.h>
+#include <fsl_edma.h>
 
-#define LOG_DOMAIN dev_i2s_mcux
-#define LOG_LEVEL  CONFIG_I2S_LOG_LEVEL
 #include <zephyr/logging/log.h>
-#include <zephyr/irq.h>
+LOG_MODULE_REGISTER(dev_i2s_mcux, CONFIG_I2S_LOG_LEVEL);
 
-LOG_MODULE_REGISTER(LOG_DOMAIN);
-
-#define DT_DRV_COMPAT          nxp_mcux_i2s
 #define NUM_DMA_BLOCKS_RX_PREP 3
-#define MAX_TX_DMA_BLOCKS      CONFIG_DMA_TCD_QUEUE_SIZE
-#if (NUM_DMA_BLOCKS_RX_PREP >= CONFIG_DMA_TCD_QUEUE_SIZE)
-#error NUM_DMA_BLOCKS_RX_PREP must be < CONFIG_DMA_TCD_QUEUE_SIZE
-#endif
-#if defined(CONFIG_DMA_MCUX_EDMA) && (NUM_DMA_BLOCKS_RX_PREP < 3)
-#error eDMA avoids TCD coherency issue if NUM_DMA_BLOCKS_RX_PREP >= 3
-#endif
+#if defined(CONFIG_DMA_MCUX_EDMA)
+BUILD_ASSERT(NUM_DMA_BLOCKS_RX_PREP >= 3,
+	     "eDMA avoids TCD coherency issue if NUM_DMA_BLOCKS_RX_PREP >= 3");
+#endif /* CONFIG_DMA_MCUX_EDMA */
+
+#define MAX_TX_DMA_BLOCKS CONFIG_DMA_TCD_QUEUE_SIZE
+BUILD_ASSERT(MAX_TX_DMA_BLOCKS > NUM_DMA_BLOCKS_RX_PREP,
+	     "NUM_DMA_BLOCKS_RX_PREP must be < CONFIG_DMA_TCD_QUEUE_SIZE");
+
+#define SAI_WORD_SIZE_BITS_MIN 8
+#define SAI_WORD_SIZE_BITS_MAX 32
+
+#define SAI_WORD_PER_FRAME_MIN 0
+#define SAI_WORD_PER_FRAME_MAX 32
 
 /*
  * SAI driver uses source_gather_en/dest_scatter_en feature of DMA, and relies
@@ -65,7 +71,7 @@ LOG_MODULE_REGISTER(LOG_DOMAIN);
  *   (may optionally block) from out_queue and presented to application.
  */
 struct stream {
-	int32_t state;
+	enum i2s_state state;
 	uint32_t dma_channel;
 	uint32_t start_channel;
 	void (*irq_call_back)(void);
@@ -88,16 +94,17 @@ struct i2s_mcux_config {
 	uint32_t pll_pd;
 	uint32_t pll_num;
 	uint32_t pll_den;
-	uint32_t *mclk_control_base;
+	uint32_t mclk_control_base;
 	uint32_t mclk_pin_mask;
 	uint32_t mclk_pin_offset;
+	bool mclk_output;
 	uint32_t tx_channel;
 	clock_control_subsys_t clk_sub_sys;
 	const struct device *ccm_dev;
 	const struct pinctrl_dev_config *pinctrl;
 	void (*irq_connect)(const struct device *dev);
-	bool rx_sync_mode;
-	bool tx_sync_mode;
+	sai_sync_mode_t rx_sync_mode;
+	sai_sync_mode_t tx_sync_mode;
 };
 
 /* Device run time data */
@@ -111,12 +118,8 @@ struct i2s_dev_data {
 	void *rx_out_msgs[CONFIG_I2S_RX_BLOCK_COUNT];
 };
 
-static void i2s_dma_tx_callback(const struct device *, void *, uint32_t, int);
-static void i2s_tx_stream_disable(const struct device *, bool drop);
-static void i2s_rx_stream_disable(const struct device *, bool in_drop, bool out_drop);
-
-static inline void i2s_purge_stream_buffers(struct stream *strm, struct k_mem_slab *mem_slab,
-					    bool in_drop, bool out_drop)
+static void i2s_purge_stream_buffers(struct stream *strm, struct k_mem_slab *mem_slab, bool in_drop,
+				     bool out_drop)
 {
 	void *buffer;
 
@@ -165,9 +168,7 @@ static void i2s_tx_stream_disable(const struct device *dev, bool drop)
 	}
 
 	/* purge buffers queued in the stream */
-	if (drop) {
-		i2s_purge_stream_buffers(strm, dev_data->tx.cfg.mem_slab, true, true);
-	}
+	i2s_purge_stream_buffers(strm, dev_data->tx.cfg.mem_slab, drop, drop);
 }
 
 static void i2s_rx_stream_disable(const struct device *dev, bool in_drop, bool out_drop)
@@ -198,9 +199,7 @@ static void i2s_rx_stream_disable(const struct device *dev, bool in_drop, bool o
 	dev_cfg->base->RCSR &= ~I2S_RCSR_SR_MASK;
 
 	/* purge buffers queued in the stream */
-	if (in_drop || out_drop) {
-		i2s_purge_stream_buffers(strm, dev_data->rx.cfg.mem_slab, in_drop, out_drop);
-	}
+	i2s_purge_stream_buffers(strm, dev_data->rx.cfg.mem_slab, in_drop, out_drop);
 }
 
 static int i2s_tx_reload_multiple_dma_blocks(const struct device *dev, uint8_t *blocks_queued)
@@ -257,9 +256,9 @@ static void i2s_dma_tx_callback(const struct device *dma_dev, void *arg, uint32_
 	const struct device *dev = (struct device *)arg;
 	struct i2s_dev_data *dev_data = dev->data;
 	struct stream *strm = &dev_data->tx;
+	uint8_t blocks_queued;
 	void *buffer = NULL;
 	int ret;
-	uint8_t blocks_queued;
 
 	LOG_DBG("tx cb");
 
@@ -291,35 +290,42 @@ static void i2s_dma_tx_callback(const struct device *dma_dev, void *arg, uint32_
 		goto disabled_exit_no_drop;
 	}
 
-	switch (strm->state) {
-	case I2S_STATE_RUNNING:
-	case I2S_STATE_STOPPING:
-		ret = i2s_tx_reload_multiple_dma_blocks(dev, &blocks_queued);
+	if (strm->state != I2S_STATE_RUNNING && strm->state != I2S_STATE_STOPPING) {
+		goto disabled_exit_drop;
+	}
 
-		if (ret) {
-			strm->state = I2S_STATE_ERROR;
-			goto disabled_exit_no_drop;
-		}
+	ret = i2s_tx_reload_multiple_dma_blocks(dev, &blocks_queued);
+	if (ret) {
+		strm->state = I2S_STATE_ERROR;
+		goto disabled_exit_no_drop;
+	}
 
-		if (blocks_queued || (strm->free_tx_dma_blocks < MAX_TX_DMA_BLOCKS)) {
-			goto enabled_exit;
-		} else {
-			/* all DMA blocks are free but no blocks were queued */
-			if (strm->state == I2S_STATE_STOPPING) {
-				/* TX queue has drained */
-				strm->state = I2S_STATE_READY;
-				LOG_DBG("TX stream has stopped");
-			} else {
-				strm->state = I2S_STATE_ERROR;
-				LOG_ERR("TX Failed to reload DMA");
-			}
-			goto disabled_exit_no_drop;
-		}
+	if (blocks_queued || (strm->free_tx_dma_blocks < MAX_TX_DMA_BLOCKS)) {
+		goto enabled_exit;
+	}
 
-	case I2S_STATE_ERROR:
-	default:
-		goto disabled_exit_drop;
+	/* all DMA blocks are free but no blocks were queued */
+	if (strm->state == I2S_STATE_STOPPING) {
+		/* TX queue has drained */
+		strm->state = I2S_STATE_READY;
+		LOG_DBG("TX stream has stopped");
+		goto disabled_exit_no_drop;
+	}
+
+	LOG_WRN("TX input queue empty!");
+	if (strm->free_tx_dma_blocks >= MAX_TX_DMA_BLOCKS) {
+		/* In running state, no TX blocks for transferring, so stop
+		 * TX (This will disable bit clock to avoid dummy bits
+		 * received in RX side.
+		 */
+		const struct i2s_mcux_config *dev_cfg = dev->config;
+		I2S_Type *base = (I2S_Type *)dev_cfg->base;
+
+		SAI_TxEnable(base, false);
+		LOG_WRN("TX is paused.");
 	}
+	goto enabled_exit;
+
 
 disabled_exit_no_drop:
 	i2s_tx_stream_disable(dev, false);
@@ -346,68 +352,71 @@ static void i2s_dma_rx_callback(const struct device *dma_dev, void *arg, uint32_
 
 	LOG_DBG("RX cb");
 
-	switch (strm->state) {
-	case I2S_STATE_STOPPING:
-	case I2S_STATE_RUNNING:
-		/* retrieve buffer from input queue */
-		ret = k_msgq_get(&strm->in_queue, &buffer, K_NO_WAIT);
-		__ASSERT_NO_MSG(ret == 0);
-
-		/* put buffer to output queue */
-		ret = k_msgq_put(&strm->out_queue, &buffer, K_NO_WAIT);
-		if (ret != 0) {
-			LOG_ERR("buffer %p -> out_queue %p err %d", buffer, &strm->out_queue, ret);
-			i2s_rx_stream_disable(dev, false, false);
-			strm->state = I2S_STATE_ERROR;
-			return;
-		}
-		if (strm->state == I2S_STATE_RUNNING) {
-			/* allocate new buffer for next audio frame */
-			ret = k_mem_slab_alloc(strm->cfg.mem_slab, &buffer, K_NO_WAIT);
-			if (ret != 0) {
-				LOG_ERR("buffer alloc from slab %p err %d", strm->cfg.mem_slab,
-					ret);
-				i2s_rx_stream_disable(dev, false, false);
-				strm->state = I2S_STATE_ERROR;
-			} else {
-				uint32_t data_path = strm->start_channel;
-
-				ret = dma_reload(dev_data->dev_dma, strm->dma_channel,
-						 (uint32_t)&base->RDR[data_path], (uint32_t)buffer,
-						 strm->cfg.block_size);
-				if (ret != 0) {
-					LOG_ERR("dma_reload() failed with error 0x%x", ret);
-					i2s_rx_stream_disable(dev, false, false);
-					strm->state = I2S_STATE_ERROR;
-					return;
-				}
-
-				/* put buffer in input queue */
-				ret = k_msgq_put(&strm->in_queue, &buffer, K_NO_WAIT);
-				if (ret != 0) {
-					LOG_ERR("%p -> in_queue %p err %d", buffer, &strm->in_queue,
-						ret);
-				}
-
-			}
-		} else {
-			i2s_rx_stream_disable(dev, true, false);
-			/* Received a STOP/DRAIN trigger */
-			strm->state = I2S_STATE_READY;
-		}
-		break;
-	case I2S_STATE_ERROR:
+	if (strm->state == I2S_STATE_ERROR) {
 		i2s_rx_stream_disable(dev, true, true);
-		break;
 	}
+
+	if (strm->state != I2S_STATE_STOPPING && strm->state != I2S_STATE_RUNNING) {
+		return;
+	}
+
+	/* retrieve buffer from input queue */
+	ret = k_msgq_get(&strm->in_queue, &buffer, K_NO_WAIT);
+	__ASSERT_NO_MSG(ret == 0);
+
+	/* put buffer to output queue */
+	ret = k_msgq_put(&strm->out_queue, &buffer, K_NO_WAIT);
+	if (ret != 0) {
+		LOG_ERR("buffer %p -> out_queue %p err %d", buffer, &strm->out_queue, ret);
+		goto error;
+	}
+
+	if (strm->state == I2S_STATE_STOPPING) {
+		i2s_rx_stream_disable(dev, true, false);
+		/* Received a STOP/DRAIN trigger */
+		strm->state = I2S_STATE_READY;
+		return;
+	}
+
+	/* Now the only possible case is the running state */
+
+	/* allocate new buffer for next audio frame */
+	ret = k_mem_slab_alloc(strm->cfg.mem_slab, &buffer, K_NO_WAIT);
+	if (ret != 0) {
+		LOG_ERR("buffer alloc from slab %p err %d", strm->cfg.mem_slab, ret);
+		goto error;
+	}
+
+	uint32_t data_path = strm->start_channel;
+
+	ret = dma_reload(dev_data->dev_dma, strm->dma_channel,
+			 (uint32_t)&base->RDR[data_path], (uint32_t)buffer,
+			 strm->cfg.block_size);
+	if (ret != 0) {
+		LOG_ERR("dma_reload() failed with error 0x%x", ret);
+		goto error;
+	}
+
+	/* put buffer in input queue */
+	ret = k_msgq_put(&strm->in_queue, &buffer, K_NO_WAIT);
+	if (ret != 0) {
+		LOG_ERR("%p -> in_queue %p err %d", buffer, &strm->in_queue, ret);
+	}
+
+	return;
+
+error:
+	i2s_rx_stream_disable(dev, false, false);
+	strm->state = I2S_STATE_ERROR;
 }
 
 static void enable_mclk_direction(const struct device *dev, bool dir)
 {
 	const struct i2s_mcux_config *dev_cfg = dev->config;
+	uint32_t control_base = dev_cfg->mclk_control_base;
 	uint32_t offset = dev_cfg->mclk_pin_offset;
 	uint32_t mask = dev_cfg->mclk_pin_mask;
-	uint32_t *base = (uint32_t *)(dev_cfg->mclk_control_base + offset);
+	uint32_t *base = (uint32_t *)(control_base + offset);
 
 	if (dir) {
 		*base |= mask;
@@ -439,70 +448,47 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
 	const struct i2s_mcux_config *dev_cfg = dev->config;
 	I2S_Type *base = (I2S_Type *)dev_cfg->base;
 	struct i2s_dev_data *dev_data = dev->data;
+	enum i2s_state *tx_state = &(dev_data->tx.state);
+	enum i2s_state *rx_state = &(dev_data->rx.state);
+	uint8_t word_size_bits = i2s_cfg->word_size;
+	uint8_t word_size_bytes = word_size_bits / 8;
+	uint8_t num_words = i2s_cfg->channels;
 	sai_transceiver_t config;
+	int ret = -EINVAL;
 	uint32_t mclk;
-	/*num_words is frame size*/
-	uint8_t num_words = i2s_cfg->channels;
-	uint8_t word_size_bits = i2s_cfg->word_size;
 
 	if ((dev_data->tx.state != I2S_STATE_NOT_READY) &&
 	    (dev_data->tx.state != I2S_STATE_READY) &&
 	    (dev_data->rx.state != I2S_STATE_NOT_READY) &&
 	    (dev_data->rx.state != I2S_STATE_READY)) {
 		LOG_ERR("invalid state tx(%u) rx(%u)", dev_data->tx.state, dev_data->rx.state);
-		if (dir == I2S_DIR_TX) {
-			dev_data->tx.state = I2S_STATE_NOT_READY;
-		} else {
-			dev_data->rx.state = I2S_STATE_NOT_READY;
-		}
-		return -EINVAL;
+		goto invalid_config;
 	}
 
 	if (i2s_cfg->frame_clk_freq == 0U) {
 		LOG_ERR("Invalid frame_clk_freq %u", i2s_cfg->frame_clk_freq);
-		if (dir == I2S_DIR_TX) {
-			dev_data->tx.state = I2S_STATE_NOT_READY;
-		} else {
-			dev_data->rx.state = I2S_STATE_NOT_READY;
-		}
-		return 0;
+		goto invalid_config;
 	}
 
 	if (word_size_bits < SAI_WORD_SIZE_BITS_MIN || word_size_bits > SAI_WORD_SIZE_BITS_MAX) {
 		LOG_ERR("Unsupported I2S word size %u", word_size_bits);
-		if (dir == I2S_DIR_TX) {
-			dev_data->tx.state = I2S_STATE_NOT_READY;
-		} else {
-			dev_data->rx.state = I2S_STATE_NOT_READY;
-		}
-		return -EINVAL;
+		goto invalid_config;
 	}
 
 	if (num_words < SAI_WORD_PER_FRAME_MIN || num_words > SAI_WORD_PER_FRAME_MAX) {
 		LOG_ERR("Unsupported words length %u", num_words);
-		if (dir == I2S_DIR_TX) {
-			dev_data->tx.state = I2S_STATE_NOT_READY;
-		} else {
-			dev_data->rx.state = I2S_STATE_NOT_READY;
-		}
-		return -EINVAL;
+		goto invalid_config;
 	}
 
 	if ((i2s_cfg->options & I2S_OPT_PINGPONG) == I2S_OPT_PINGPONG) {
 		LOG_ERR("Ping-pong mode not supported");
-		if (dir == I2S_DIR_TX) {
-			dev_data->tx.state = I2S_STATE_NOT_READY;
-		} else {
-			dev_data->rx.state = I2S_STATE_NOT_READY;
-		}
-		return -ENOTSUP;
+		ret = -ENOTSUP;
+		goto invalid_config;
 	}
 
 	memset(&config, 0, sizeof(config));
 
-	const bool is_mclk_slave = i2s_cfg->options & I2S_OPT_BIT_CLK_SLAVE;
-
-	enable_mclk_direction(dev, !is_mclk_slave);
+	enable_mclk_direction(dev, dev_cfg->mclk_output);
 
 	get_mclk_rate(dev, &mclk);
 	LOG_DBG("mclk is %d", mclk);
@@ -553,43 +539,28 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
 		break;
 	default:
 		LOG_ERR("Unsupported I2S data format");
-		if (dir == I2S_DIR_TX) {
-			dev_data->tx.state = I2S_STATE_NOT_READY;
-		} else {
-			dev_data->rx.state = I2S_STATE_NOT_READY;
-		}
-		return -EINVAL;
+		ret = -EINVAL;
+		goto invalid_config;
 	}
 
 	/* sync mode configurations */
 	if (dir == I2S_DIR_TX) {
-		/* TX */
-		if (dev_cfg->tx_sync_mode) {
-			config.syncMode = kSAI_ModeSync;
-		} else {
-			config.syncMode = kSAI_ModeAsync;
-		}
-	} else {
-		/* RX */
-		if (dev_cfg->rx_sync_mode) {
-			config.syncMode = kSAI_ModeSync;
-		} else {
-			config.syncMode = kSAI_ModeAsync;
-		}
+		config.syncMode = dev_cfg->tx_sync_mode;
+	} else if (dir == I2S_DIR_RX) {
+		config.syncMode = dev_cfg->rx_sync_mode;
 	}
 
-	if (i2s_cfg->options & I2S_OPT_FRAME_CLK_SLAVE) {
-		if (i2s_cfg->options & I2S_OPT_BIT_CLK_SLAVE) {
-			config.masterSlave = kSAI_Slave;
-		} else {
-			config.masterSlave = kSAI_Bclk_Master_FrameSync_Slave;
-		}
+	bool frame_clk_slave = i2s_cfg->options & I2S_OPT_FRAME_CLK_SLAVE;
+	bool bit_clk_slave = i2s_cfg->options & I2S_OPT_BIT_CLK_SLAVE;
+
+	if (frame_clk_slave && bit_clk_slave) {
+		config.masterSlave = kSAI_Slave;
+	} else if (frame_clk_slave && !bit_clk_slave) {
+		config.masterSlave = kSAI_Bclk_Master_FrameSync_Slave;
+	} else if (!frame_clk_slave && bit_clk_slave) {
+		config.masterSlave = kSAI_Bclk_Slave_FrameSync_Master;
 	} else {
-		if (i2s_cfg->options & I2S_OPT_BIT_CLK_SLAVE) {
-			config.masterSlave = kSAI_Bclk_Slave_FrameSync_Master;
-		} else {
-			config.masterSlave = kSAI_Master;
-		}
+		config.masterSlave = kSAI_Master;
 	}
 
 	/* clock signal polarity */
@@ -605,7 +576,6 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
 				? kSAI_SampleOnRisingEdge
 				: kSAI_SampleOnFallingEdge;
 		break;
-
 	case I2S_FMT_CLK_IF_NB:
 		/* Swap frame sync polarity */
 		config.frameSync.frameSyncPolarity =
@@ -613,7 +583,6 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
 				? kSAI_PolarityActiveLow
 				: kSAI_PolarityActiveHigh;
 		break;
-
 	case I2S_FMT_CLK_IF_IB:
 		/* Swap frame sync and bclk polarity */
 		config.frameSync.frameSyncPolarity =
@@ -639,6 +608,7 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
 		LOG_DBG("tx slab block_size = %d", (uint32_t)i2s_cfg->mem_slab->info.block_size);
 		LOG_DBG("tx slab buffer = 0x%x", (uint32_t)i2s_cfg->mem_slab->buffer);
 
+		config.fifo.fifoWatermark = (uint32_t)FSL_FEATURE_SAI_FIFO_COUNTn(base) - 1;
 		/* set bit clock divider */
 		SAI_TxSetConfig(base, &config);
 		dev_data->tx.start_channel = config.startChannel;
@@ -648,10 +618,10 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
 				      i2s_cfg->channels);
 		LOG_DBG("tx start_channel = %d", dev_data->tx.start_channel);
 		/*set up dma settings*/
-		dev_data->tx.dma_cfg.source_data_size = word_size_bits / 8;
-		dev_data->tx.dma_cfg.dest_data_size = word_size_bits / 8;
-		dev_data->tx.dma_cfg.source_burst_length = i2s_cfg->word_size / 8;
-		dev_data->tx.dma_cfg.dest_burst_length = i2s_cfg->word_size / 8;
+		dev_data->tx.dma_cfg.source_data_size = word_size_bytes;
+		dev_data->tx.dma_cfg.dest_data_size = word_size_bytes;
+		dev_data->tx.dma_cfg.source_burst_length = word_size_bytes;
+		dev_data->tx.dma_cfg.dest_burst_length = word_size_bytes;
 		dev_data->tx.dma_cfg.user_data = (void *)dev;
 		dev_data->tx.state = I2S_STATE_READY;
 	} else {
@@ -671,15 +641,23 @@ static int i2s_mcux_config(const struct device *dev, enum i2s_dir dir,
 				      i2s_cfg->channels);
 		LOG_DBG("rx start_channel = %d", dev_data->rx.start_channel);
 		/*set up dma settings*/
-		dev_data->rx.dma_cfg.source_data_size = word_size_bits / 8;
-		dev_data->rx.dma_cfg.dest_data_size = word_size_bits / 8;
-		dev_data->rx.dma_cfg.source_burst_length = i2s_cfg->word_size / 8;
-		dev_data->rx.dma_cfg.dest_burst_length = i2s_cfg->word_size / 8;
+		dev_data->rx.dma_cfg.source_data_size = word_size_bytes;
+		dev_data->rx.dma_cfg.dest_data_size = word_size_bytes;
+		dev_data->rx.dma_cfg.source_burst_length = word_size_bytes;
+		dev_data->rx.dma_cfg.dest_burst_length = word_size_bytes;
 		dev_data->rx.dma_cfg.user_data = (void *)dev;
 		dev_data->rx.state = I2S_STATE_READY;
 	}
 
 	return 0;
+
+invalid_config:
+	if (dir == I2S_DIR_TX) {
+		*tx_state = I2S_STATE_NOT_READY;
+	} else if (dir == I2S_DIR_RX) {
+		*rx_state = I2S_STATE_NOT_READY;
+	}
+	return ret;
 }
 
 const struct i2s_config *i2s_mcux_config_get(const struct device *dev, enum i2s_dir dir)
@@ -1010,6 +988,23 @@ static int i2s_mcux_write(const struct device *dev, void *mem_block, size_t size
 		return ret;
 	}
 
+	if (strm->state == I2S_STATE_RUNNING && strm->free_tx_dma_blocks >= MAX_TX_DMA_BLOCKS) {
+		uint8_t blocks_queued = 0;
+		const struct i2s_mcux_config *dev_cfg = dev->config;
+		I2S_Type *base = (I2S_Type *)dev_cfg->base;
+		/* As DMA has been stopped because reloading failure in TX callback,
+		 * here is a good place to reload it and resume TX.
+		 */
+		ret = i2s_tx_reload_multiple_dma_blocks(dev, &blocks_queued);
+		if (ret == 0 && blocks_queued > 0) {
+			SAI_TxEnable(base, true);
+			LOG_WRN("TX is resumed");
+		} else {
+			LOG_ERR("TX block reload err, TX is not resumed");
+			return ret;
+		}
+	}
+
 	return ret;
 }
 
@@ -1065,6 +1060,7 @@ static void i2s_mcux_isr(void *arg)
 
 static void audio_clock_settings(const struct device *dev)
 {
+#ifdef CONFIG_I2S_HAS_PLL_SETTING
 	clock_audio_pll_config_t audioPllConfig;
 	const struct i2s_mcux_config *dev_cfg = dev->config;
 	uint32_t clock_name = (uint32_t)dev_cfg->clk_sub_sys;
@@ -1090,6 +1086,7 @@ static void audio_clock_settings(const struct device *dev)
 #endif /* CONFIG_SOC_SERIES */
 
 	CLOCK_InitAudioPll(&audioPllConfig);
+#endif
 }
 
 static int i2s_mcux_initialize(const struct device *dev)
@@ -1148,7 +1145,8 @@ static int i2s_mcux_initialize(const struct device *dev)
 /* master clock configurations */
 #if (defined(FSL_FEATURE_SAI_HAS_MCR) && (FSL_FEATURE_SAI_HAS_MCR)) ||                             \
 	(defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER))
-#if defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)
+#if ((defined(FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER) && (FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER)) || \
+	(defined(FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV) && (FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV)))
 	mclkConfig.mclkHz = mclk;
 	mclkConfig.mclkSourceClkHz = mclk;
 #endif
@@ -1175,25 +1173,27 @@ static DEVICE_API(i2s, i2s_mcux_driver_api) = {
                                                                                                    \
 	static const struct i2s_mcux_config i2s_##i2s_id##_config = {                              \
 		.base = (I2S_Type *)DT_INST_REG_ADDR(i2s_id),                                      \
-		.clk_src = DT_INST_PROP(i2s_id, clock_mux),                                        \
-		.clk_pre_div = DT_INST_PROP(i2s_id, pre_div),                                      \
-		.clk_src_div = DT_INST_PROP(i2s_id, podf),                                         \
-		.pll_src = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, src, value),            \
-		.pll_lp = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, lp, value),              \
-		.pll_pd = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, pd, value),              \
-		.pll_num = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, num, value),            \
-		.pll_den = DT_PHA_BY_NAME(DT_DRV_INST(i2s_id), pll_clocks, den, value),            \
-		.mclk_control_base =                                                               \
-			(uint32_t *)DT_REG_ADDR(DT_PHANDLE(DT_DRV_INST(i2s_id), pinmuxes)),    \
-		.mclk_pin_mask = DT_PHA_BY_IDX(DT_DRV_INST(i2s_id), pinmuxes, 0, function),        \
-		.mclk_pin_offset = DT_PHA_BY_IDX(DT_DRV_INST(i2s_id), pinmuxes, 0, pin),           \
+		.clk_src = DT_INST_PROP_OR(i2s_id, clock_mux, 0),                                  \
+		.clk_pre_div = DT_INST_PROP_OR(i2s_id, pre_div, 0),                                \
+		.clk_src_div = DT_INST_PROP_OR(i2s_id, podf, 0),                                   \
+		.pll_src = DT_PHA_BY_NAME_OR(DT_DRV_INST(i2s_id), pll_clocks, src, value, 0),      \
+		.pll_lp = DT_PHA_BY_NAME_OR(DT_DRV_INST(i2s_id), pll_clocks, lp, value, 0),        \
+		.pll_pd = DT_PHA_BY_NAME_OR(DT_DRV_INST(i2s_id), pll_clocks, pd, value, 0),        \
+		.pll_num = DT_PHA_BY_NAME_OR(DT_DRV_INST(i2s_id), pll_clocks, num, value, 0),      \
+		.pll_den = DT_PHA_BY_NAME_OR(DT_DRV_INST(i2s_id), pll_clocks, den, value, 0),      \
+		.mclk_control_base = DT_REG_ADDR(DT_PHANDLE(DT_DRV_INST(i2s_id), pinmuxes)),       \
+		.mclk_pin_mask = DT_PHA_BY_IDX(DT_DRV_INST(i2s_id), pinmuxes, 0, mask),            \
+		.mclk_pin_offset = DT_PHA_BY_IDX(DT_DRV_INST(i2s_id), pinmuxes, 0, offset),        \
+		.mclk_output = DT_INST_PROP_OR(i2s_id, mclk_output, 0),                            \
 		.clk_sub_sys =                                                                     \
 			(clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_IDX(i2s_id, 0, name),       \
 		.ccm_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(i2s_id)),                             \
 		.irq_connect = i2s_irq_connect_##i2s_id,                                           \
 		.pinctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(i2s_id),                                 \
-		.tx_sync_mode = DT_INST_PROP(i2s_id, nxp_tx_sync_mode),                            \
-		.rx_sync_mode = DT_INST_PROP(i2s_id, nxp_rx_sync_mode),                            \
+		.tx_sync_mode =                                                                    \
+			DT_INST_PROP(i2s_id, nxp_tx_sync_mode) ? kSAI_ModeSync : kSAI_ModeAsync,   \
+		.rx_sync_mode =                                                                    \
+			DT_INST_PROP(i2s_id, nxp_rx_sync_mode) ? kSAI_ModeSync : kSAI_ModeAsync,   \
 		.tx_channel = DT_INST_PROP(i2s_id, nxp_tx_channel),                                \
 	};                                                                                         \
                                                                                                    \
diff --git a/drivers/i2s/i2s_mcux_sai.h b/drivers/i2s/i2s_mcux_sai.h
deleted file mode 100644
index 3599320d113..00000000000
--- a/drivers/i2s/i2s_mcux_sai.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright (c) 2021 NXP
- * All rights reserved.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-
-#ifndef ZEPHYR_DRIVERS_I2S_MCUX_H_
-#define ZEPHYR_DRIVERS_I2S_MCUX_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <zephyr/device.h>
-#include <fsl_sai.h>
-#include <fsl_edma.h>
-
-#define SAI_WORD_SIZE_BITS_MIN 8
-#define SAI_WORD_SIZE_BITS_MAX 32
-
-#define SAI_WORD_PER_FRAME_MIN 0
-#define SAI_WORD_PER_FRAME_MAX 32
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ZEPHYR_DRIVERS_I2S_MCUX_H_ */
diff --git a/drivers/i2s/i2s_sam_ssc.c b/drivers/i2s/i2s_sam_ssc.c
index f96bb34d6d4..cabf8ec64c1 100644
--- a/drivers/i2s/i2s_sam_ssc.c
+++ b/drivers/i2s/i2s_sam_ssc.c
@@ -58,7 +58,7 @@ struct queue_item {
 };
 
 /* Minimal ring buffer implementation */
-struct ring_buf {
+struct ring_buffer {
 	struct queue_item *buf;
 	uint16_t len;
 	uint16_t head;
@@ -83,7 +83,7 @@ struct stream {
 	uint8_t word_size_bytes;
 	bool last_block;
 	struct i2s_config cfg;
-	struct ring_buf mem_block_queue;
+	struct ring_buffer mem_block_queue;
 	void *mem_block;
 	int (*stream_start)(struct stream *, Ssc *const,
 			    const struct device *);
@@ -113,7 +113,7 @@ static void tx_stream_disable(struct stream *, Ssc *const,
 /*
  * Get data from the queue
  */
-static int queue_get(struct ring_buf *rb, void **mem_block, size_t *size)
+static int queue_get(struct ring_buffer *rb, void **mem_block, size_t *size)
 {
 	unsigned int key;
 
@@ -137,7 +137,7 @@ static int queue_get(struct ring_buf *rb, void **mem_block, size_t *size)
 /*
  * Put data in the queue
  */
-static int queue_put(struct ring_buf *rb, void *mem_block, size_t size)
+static int queue_put(struct ring_buffer *rb, void *mem_block, size_t size)
 {
 	uint16_t head_next;
 	unsigned int key;
diff --git a/drivers/i3c/CMakeLists.txt b/drivers/i3c/CMakeLists.txt
index 9aeb3b926fe..39419267933 100644
--- a/drivers/i3c/CMakeLists.txt
+++ b/drivers/i3c/CMakeLists.txt
@@ -5,11 +5,16 @@
 zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/i3c.h)
 
 zephyr_library()
+zephyr_library_sources_ifdef(CONFIG_I3C_CONTROLLER i3c_ccc.c)
+zephyr_library_sources_ifdef(CONFIG_I3C_CONTROLLER i3c_common.c)
 
-zephyr_library_sources(
-  i3c_ccc.c
-  i3c_common.c
-)
+if(DEFINED CONFIG_I3C_NUM_OF_DESC_MEM_SLABS AND CONFIG_I3C_NUM_OF_DESC_MEM_SLABS GREATER 0)
+  zephyr_library_sources(i3c_mem_slab.c)
+endif()
+
+if(DEFINED CONFIG_I3C_I2C_NUM_OF_DESC_MEM_SLABS AND CONFIG_I3C_I2C_NUM_OF_DESC_MEM_SLABS GREATER 0)
+  zephyr_library_sources(i3c_i2c_mem_slab.c)
+endif()
 
 zephyr_library_sources_ifdef(
   CONFIG_USERSPACE
@@ -46,6 +51,11 @@ zephyr_library_sources_ifdef(
   i3c_stm32.c
 )
 
+zephyr_library_sources_ifdef(
+  CONFIG_I3C_DW
+  i3c_dw.c
+)
+
 zephyr_library_sources_ifdef(
   CONFIG_I3C_TEST
   i3c_test.c
diff --git a/drivers/i3c/Kconfig b/drivers/i3c/Kconfig
index d865b1a2d80..31f79b78f18 100644
--- a/drivers/i3c/Kconfig
+++ b/drivers/i3c/Kconfig
@@ -15,6 +15,34 @@ module = I3C
 module-str = i3c
 source "subsys/logging/Kconfig.template.log_config"
 
+choice I3C_MODE
+	prompt "I3C Mode Selection"
+	default I3C_DUAL_ROLE
+	help
+	  Select the role in which I3C is enabled.
+	  At least one of Controller or Target must be enabled.
+
+	  Selecting only one can reduce the code footprint size.
+
+config I3C_CONTROLLER_ROLE_ONLY
+	bool "I3C Controller only"
+
+config I3C_TARGET_ROLE_ONLY
+	bool "I3C Target only"
+
+config I3C_DUAL_ROLE
+	bool "Both I3C Controller and Target"
+
+endchoice
+
+config I3C_CONTROLLER
+	bool
+	default y if I3C_DUAL_ROLE || I3C_CONTROLLER_ROLE_ONLY
+
+config I3C_TARGET
+	bool
+	default y if I3C_DUAL_ROLE || I3C_TARGET_ROLE_ONLY
+
 config I3C_SHELL
 	bool "I3C Shell"
 	depends on SHELL
@@ -24,17 +52,9 @@ config I3C_SHELL
 	  The I3C shell supports info, bus recovery, CCC, I3C read and
 	  write operations.
 
-config I3C_USE_GROUP_ADDR
-	bool "Use Group Addresses"
-	default y
-	help
-	  Enable this to use group addresses if supported
-	  by the controllers and target devices.
-
-	  Says Y if unsure.
-
 config I3C_TARGET_BUFFER_MODE
 	bool "I3C target driver for buffer mode"
+	depends on I3C_TARGET
 	help
 	  This is an option to enable buffer mode.
 
@@ -117,6 +137,28 @@ config I3C_INIT_RSTACT
 	  This determines whether the bus initialization routine
 	  sends a reset action command to I3C targets.
 
+if I3C_CONTROLLER && I3C_TARGET
+
+config I3C_NUM_OF_DESC_MEM_SLABS
+	int "Number of I3C Device Descriptors Mem Slabs"
+	default 3
+	help
+	  This is the number of memory slabs allocated from when
+	  there is a device encounted through ENTDAA or DEFTGTS that
+	  is not within known I3C devices.
+
+config I3C_I2C_NUM_OF_DESC_MEM_SLABS
+	int "Number of I2C Device Descriptors Mem Slabs"
+	default 3
+	help
+	  This is the number of memory slabs allocated from when
+	  there is a device encounted through DEFTGTS that is not
+	  within known I2C devices.
+
+endif # I3C_CONTROLLER && I3C_TARGET
+
+if I3C_CONTROLLER
+
 config I3C_RTIO
 	bool "I3C RTIO API"
 	select EXPERIMENTAL
@@ -161,11 +203,14 @@ config I3C_RTIO_FALLBACK_MSGS
 
 endif # I3C_RTIO
 
+endif # I3C_CONTROLLER
+
 comment "Device Drivers"
 
 rsource "Kconfig.nxp"
 rsource "Kconfig.cdns"
 rsource "Kconfig.npcx"
+rsource "Kconfig.dw"
 rsource "Kconfig.test"
 rsource "Kconfig.stm32"
 
diff --git a/drivers/i3c/Kconfig.cdns b/drivers/i3c/Kconfig.cdns
index f401235c84b..9b13a1bb891 100644
--- a/drivers/i3c/Kconfig.cdns
+++ b/drivers/i3c/Kconfig.cdns
@@ -8,7 +8,7 @@ source "subsys/logging/Kconfig.template.log_config"
 
 config I3C_CADENCE
 	bool "Cadence I3C driver"
-	select I3C_IBI_WORKQUEUE if I3C_USE_IBI
+	select I3C_IBI_WORKQUEUE if I3C_USE_IBI && I3C_CONTROLLER
 	depends on DT_HAS_CDNS_I3C_ENABLED
 	default y
 	help
diff --git a/drivers/i3c/Kconfig.dw b/drivers/i3c/Kconfig.dw
new file mode 100644
index 00000000000..813a95ebaeb
--- /dev/null
+++ b/drivers/i3c/Kconfig.dw
@@ -0,0 +1,24 @@
+# Copyright (c) 2023 Meta Platforms, Inc. and its affiliates.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+module = I3C_DW
+module-str = i3c-dw
+source "subsys/logging/Kconfig.template.log_config"
+
+menuconfig I3C_DW
+	bool "DW I3C support"
+	select I3C_IBI_WORKQUEUE if I3C_USE_IBI && I3C_CONTROLLER
+	depends on DT_HAS_SNPS_DESIGNWARE_I3C_ENABLED
+	depends on CLOCK_CONTROL
+	default y
+	help
+	  Enable the Synopsys Designware I3C driver
+
+if I3C_DW
+
+config I3C_DW_RW_TIMEOUT_MS
+	int "Set the Read/Write timeout in milliseconds"
+	default 100
+
+endif # I3C_DW
diff --git a/drivers/i3c/i3c_ccc.c b/drivers/i3c/i3c_ccc.c
index ccf5d8efec0..c670476412a 100644
--- a/drivers/i3c/i3c_ccc.c
+++ b/drivers/i3c/i3c_ccc.c
@@ -137,6 +137,26 @@ int i3c_ccc_do_rstact(const struct i3c_device_desc *target,
 	return i3c_do_ccc(target->bus, &ccc_payload);
 }
 
+int i3c_ccc_do_rstdaa(struct i3c_device_desc *target)
+{
+	struct i3c_ccc_payload ccc_payload;
+	struct i3c_ccc_target_payload ccc_tgt_payload;
+
+	__ASSERT_NO_MSG(target != NULL);
+	__ASSERT_NO_MSG(target->bus != NULL);
+
+	ccc_tgt_payload.addr = target->dynamic_addr;
+	ccc_tgt_payload.rnw = 1;
+	ccc_tgt_payload.data_len = 0;
+
+	memset(&ccc_payload, 0, sizeof(ccc_payload));
+	ccc_payload.ccc.id = I3C_CCC_RSTDAA_DC;
+	ccc_payload.targets.payloads = &ccc_tgt_payload;
+	ccc_payload.targets.num_targets = 1;
+
+	return i3c_do_ccc(target->bus, &ccc_payload);
+}
+
 int i3c_ccc_do_rstdaa_all(const struct device *controller)
 {
 	struct i3c_ccc_payload ccc_payload;
@@ -255,6 +275,7 @@ int i3c_ccc_do_entas(const struct i3c_device_desc *target, uint8_t as)
 
 	ccc_tgt_payload.addr = target->dynamic_addr;
 	ccc_tgt_payload.rnw = 0;
+	ccc_tgt_payload.data_len = 0;
 
 	ccc_payload.ccc.id = I3C_CCC_ENTAS(as, false);
 	ccc_payload.targets.payloads = &ccc_tgt_payload;
@@ -910,3 +931,28 @@ int i3c_ccc_do_setbuscon(const struct device *controller,
 
 	return i3c_do_ccc(controller, &ccc_payload);
 }
+
+int i3c_ccc_do_getacccr(const struct i3c_device_desc *target,
+			 struct i3c_ccc_address *handoff_address)
+{
+	struct i3c_ccc_payload ccc_payload;
+	struct i3c_ccc_target_payload ccc_tgt_payload;
+	int ret;
+
+	__ASSERT_NO_MSG(target != NULL);
+	__ASSERT_NO_MSG(handoff_address != NULL);
+
+	ccc_tgt_payload.addr = target->dynamic_addr;
+	ccc_tgt_payload.rnw = 1;
+	ccc_tgt_payload.data = &handoff_address->addr;
+	ccc_tgt_payload.data_len = 1;
+
+	memset(&ccc_payload, 0, sizeof(ccc_payload));
+	ccc_payload.ccc.id = I3C_CCC_GETACCCR;
+	ccc_payload.targets.payloads = &ccc_tgt_payload;
+	ccc_payload.targets.num_targets = 1;
+
+	ret = i3c_do_ccc(target->bus, &ccc_payload);
+
+	return ret;
+}
diff --git a/drivers/i3c/i3c_cdns.c b/drivers/i3c/i3c_cdns.c
index e6d18ed058c..e4eafaa422f 100644
--- a/drivers/i3c/i3c_cdns.c
+++ b/drivers/i3c/i3c_cdns.c
@@ -14,6 +14,8 @@
 #include <zephyr/sys/sys_io.h>
 #include <zephyr/sys/util.h>
 
+#include <stdlib.h>
+
 #define DEV_ID            0x0
 #define DEV_ID_I3C_MASTER 0x5034
 
@@ -344,7 +346,8 @@
 #define SLV_ERR1          BIT(1)
 #define SLV_ERR0          BIT(0)
 
-#define SLV_STATUS2 0xA8
+#define SLV_STATUS2        0xA8
+#define SLV_STATUS2_MRL(s) (((s) & GENMASK(23, 8)) >> 8)
 
 #define SLV_STATUS3           0xAC
 #define SLV_STATUS3_BC_FSM(s) (((s) & GENMASK(26, 16)) >> 16)
@@ -455,9 +458,6 @@
  * Local Constants Definition
  ******************************************************************************/
 
-/* TODO: this needs to be configurable in the dts...somehow */
-#define I3C_CONTROLLER_ADDR 0x08
-
 /* Maximum i3c devices that the IP can be built with */
 #define I3C_MAX_DEVS                     11
 #define I3C_MAX_MSGS                     10
@@ -483,8 +483,6 @@
 #define I3C_CMDR_THR 1
 /* command tx fifo threshold - unused */
 #define I3C_CMDD_THR 1
-/* in-band-interrupt data fifo threshold - unused */
-#define I3C_IBID_THR 1
 /* in-band-interrupt response queue threshold */
 #define I3C_IBIR_THR 1
 /* tx data threshold - unused */
@@ -572,16 +570,31 @@ struct cdns_i3c_config {
 
 /* Driver instance data */
 struct cdns_i3c_data {
+	/* common must be first! */
 	struct i3c_driver_data common;
 	struct cdns_i3c_hw_config hw_cfg;
-#ifdef CONFIG_I3C_USE_IBI
-	struct cdns_i3c_ibi_buf ibi_buf;
-#endif
 	struct k_mutex bus_lock;
+#ifdef CONFIG_I3C_CONTROLLER
 	struct cdns_i3c_i2c_dev_data cdns_i3c_i2c_priv_data[I3C_MAX_DEVS];
+#endif /* CONFIG_I3C_CONTROLLER */
 	struct cdns_i3c_xfer xfer;
+#ifdef CONFIG_I3C_TARGET
 	struct i3c_target_config *target_config;
+#endif /* CONFIG_I3C_TARGET */
+#ifdef CONFIG_I3C_USE_IBI
+	struct cdns_i3c_ibi_buf ibi_buf;
+#ifdef CONFIG_I3C_TARGET
 	struct k_sem ibi_hj_complete;
+#ifdef CONFIG_I3C_CONTROLLER
+	struct k_sem ibi_cr_complete;
+#endif /* CONFIG_I3C_CONTROLLER */
+#endif /* CONFIG_I3C_TARGET */
+#endif /* CONFIG_I3C_USE_IBI*/
+#if defined(CONFIG_I3C_CONTROLLER) && defined(CONFIG_I3C_TARGET)
+	const struct device *dev;
+	struct k_work deftgts_work;
+	struct k_sem ch_complete;
+#endif /* CONFIG_I3C_CONTROLLER && CONFIG_I3C_TARGET */
 	uint32_t free_rr_slots;
 	uint16_t fifo_bytes_read;
 	uint8_t max_devs;
@@ -656,7 +669,7 @@ static uint16_t prepare_ddr_cmd_parity_adjustment_bit(uint16_t word)
 
 	return word;
 }
-
+#ifdef CONFIG_I3C_CONTROLLER
 /* Computes and sets parity */
 /* Returns [7:1] 7-bit addr, [0] even/xor parity */
 static uint8_t cdns_i3c_even_parity_byte(uint8_t byte)
@@ -672,6 +685,7 @@ static uint8_t cdns_i3c_even_parity_byte(uint8_t byte)
 
 	return b;
 }
+#endif /* CONFIG_I3C_CONTROLLER */
 
 /* Check if command response fifo is empty */
 static inline bool cdns_i3c_cmd_rsp_fifo_empty(const struct cdns_i3c_config *config)
@@ -767,6 +781,7 @@ static void cdns_i3c_write_tx_fifo(const struct cdns_i3c_config *config, const v
 	}
 }
 
+#ifdef CONFIG_I3C_TARGET
 static void cdns_i3c_write_ddr_tx_fifo(const struct cdns_i3c_config *config, const void *buf,
 				       uint32_t len)
 {
@@ -784,8 +799,10 @@ static void cdns_i3c_write_ddr_tx_fifo(const struct cdns_i3c_config *config, con
 		sys_write32(val, config->base + SLV_DDR_TX_FIFO);
 	}
 }
+#endif /* CONFIG_I3C_TARGET */
 
 #ifdef CONFIG_I3C_USE_IBI
+#ifdef CONFIG_I3C_TARGET
 static void cdns_i3c_write_ibi_fifo(const struct cdns_i3c_config *config, const void *buf,
 				    uint32_t len)
 {
@@ -803,8 +820,9 @@ static void cdns_i3c_write_ibi_fifo(const struct cdns_i3c_config *config, const
 		sys_write32(val, config->base + IBI_DATA_FIFO);
 	}
 }
+#endif /* CONFIG_I3C_TARGET */
 #endif /* CONFIG_I3C_USE_IBI */
-
+#ifdef CONFIG_I3C_TARGET
 static void cdns_i3c_target_read_rx_fifo(const struct device *dev)
 {
 	const struct cdns_i3c_config *config = dev->config;
@@ -839,7 +857,8 @@ static void cdns_i3c_target_read_rx_fifo(const struct device *dev)
 		target_cb->write_received_cb(data->target_config, rx_data);
 	}
 }
-
+#endif /* CONFIG_I3C_TARGET */
+#ifdef CONFIG_I3C_CONTROLLER
 static int cdns_i3c_read_rx_fifo(const struct cdns_i3c_config *config, void *buf, uint32_t len)
 {
 	uint32_t *ptr = buf;
@@ -973,7 +992,7 @@ static void cdns_i3c_set_prescalers(const struct device *dev)
 		sys_write32(CTRL_DEV_EN | ctrl, config->base + CTRL);
 	}
 }
-
+#ifdef CONFIG_I3C_CONTROLLER
 /**
  * @brief Compute RR0 Value from addr
  *
@@ -995,11 +1014,13 @@ static uint32_t prepare_rr0_dev_address(uint16_t addr)
 
 	return ret;
 }
+#endif /* CONFIG_I3C_CONTROLLER */
 
 /**
  * @brief Program Retaining Registers with device lists
  *
- * This will program the retaining register with the controller itself
+ * This will program the retaining register with the controller itself, this should
+ * only be called if it is a primary controller.
  *
  * @param dev Pointer to controller device driver instance.
  */
@@ -1007,20 +1028,32 @@ static void cdns_i3c_program_controller_retaining_reg(const struct device *dev)
 {
 	const struct cdns_i3c_config *config = dev->config;
 	struct cdns_i3c_data *data = dev->data;
-	/* Set controller retaining register */
-	uint8_t controller_da = I3C_CONTROLLER_ADDR;
+	uint8_t controller_da;
 
-	if (!i3c_addr_slots_is_free(&data->common.attached_dev.addr_slots, controller_da)) {
+	/* Set controller retaining register */
+	if (config->common.primary_controller_da) {
+		if (!i3c_addr_slots_is_free(&data->common.attached_dev.addr_slots,
+					    config->common.primary_controller_da)) {
+			controller_da = i3c_addr_slots_next_free_find(
+				&data->common.attached_dev.addr_slots, 0);
+			LOG_WRN("%s: 0x%02x DA selected for controller as 0x%02x is unavailable",
+				dev->name, controller_da, config->common.primary_controller_da);
+		} else {
+			controller_da = config->common.primary_controller_da;
+		}
+	} else {
 		controller_da =
 			i3c_addr_slots_next_free_find(&data->common.attached_dev.addr_slots, 0);
-		LOG_DBG("%s: 0x%02x DA selected for controller", dev->name, controller_da);
 	}
-	sys_write32(prepare_rr0_dev_address(controller_da), config->base + DEV_ID_RR0(0));
+	sys_write32(prepare_rr0_dev_address(controller_da) | DEV_ID_RR0_IS_I3C,
+		    config->base + DEV_ID_RR0(0));
 	/* Mark the address as I3C device */
 	i3c_addr_slots_mark_i3c(&data->common.attached_dev.addr_slots, controller_da);
 }
+#endif /* CONFIG_I3C_CONTROLLER */
 
 #ifdef CONFIG_I3C_USE_IBI
+#ifdef CONFIG_I3C_CONTROLLER
 static int cdns_i3c_ibi_hj_response(const struct device *dev, bool ack)
 {
 	const struct cdns_i3c_config *config = dev->config;
@@ -1043,7 +1076,8 @@ static int cdns_i3c_controller_ibi_enable(const struct device *dev, struct i3c_d
 	struct i3c_ccc_events i3c_events;
 	int ret = 0;
 
-	if (!i3c_device_is_ibi_capable(target)) {
+	/* Check if the device can issue IBI TIRs or CR */
+	if (!i3c_device_is_ibi_capable(target) && !i3c_device_is_controller_capable(target)) {
 		ret = -EINVAL;
 		return ret;
 	}
@@ -1053,7 +1087,8 @@ static int cdns_i3c_controller_ibi_enable(const struct device *dev, struct i3c_d
 	sir_cfg = SIR_MAP_DEV_ROLE(I3C_BCR_DEVICE_ROLE(target->bcr)) |
 		  SIR_MAP_DEV_DA(target->dynamic_addr) |
 		  SIR_MAP_DEV_PL(target->data_length.max_ibi);
-	if (target->ibi_cb != NULL) {
+	/* ACK if there is an ibi tir cb or if it is controller capable*/
+	if ((target->ibi_cb != NULL) || i3c_device_is_controller_capable(target)) {
 		sir_cfg |= SIR_MAP_DEV_ACK;
 	}
 	if (target->bcr & I3C_BCR_MAX_DATA_SPEED_LIMIT) {
@@ -1063,8 +1098,8 @@ static int cdns_i3c_controller_ibi_enable(const struct device *dev, struct i3c_d
 	LOG_DBG("%s: IBI enabling for 0x%02x (BCR 0x%02x)", dev->name, target->dynamic_addr,
 		target->bcr);
 
-	/* Tell target to enable IBI */
-	i3c_events.events = I3C_CCC_EVT_INTR;
+	/* Tell target to enable IBI TIRs and CRs */
+	i3c_events.events = I3C_CCC_EVT_INTR | I3C_CCC_EVT_CR;
 	ret = i3c_ccc_do_events_set(target, true, &i3c_events);
 	if (ret != 0) {
 		LOG_ERR("%s: Error sending IBI ENEC for 0x%02x (%d)", dev->name,
@@ -1111,7 +1146,8 @@ static int cdns_i3c_controller_ibi_disable(const struct device *dev, struct i3c_
 
 	return ret;
 }
-
+#endif /* CONFIG_I3C_CONTROLLER */
+#ifdef CONFIG_I3C_TARGET
 static int cdns_i3c_target_ibi_raise_hj(const struct device *dev)
 {
 	const struct cdns_i3c_config *config = dev->config;
@@ -1142,7 +1178,32 @@ static int cdns_i3c_target_ibi_raise_hj(const struct device *dev)
 	}
 	return 0;
 }
+#ifdef CONFIG_I3C_CONTROLLER
+static int cdns_i3c_target_ibi_raise_cr(const struct device *dev)
+{
+	const struct cdns_i3c_config *config = dev->config;
+	struct cdns_i3c_data *data = dev->data;
+
+	/* Check if target does not have a DA assigned to it */
+	if (!(sys_read32(config->base + SLV_STATUS1) & SLV_STATUS1_HAS_DA)) {
+		LOG_ERR("%s: CR not available, DA not assigned", dev->name);
+		return -EACCES;
+	}
+	/* Check if CR requests DISEC CCC with DISMR field set has been received */
+	if (sys_read32(config->base + SLV_STATUS1) & SLV_STATUS1_MR_DIS) {
+		LOG_ERR("%s: CR requests are currently disabled by DISEC", dev->name);
+		return -EAGAIN;
+	}
 
+	sys_write32(CTRL_MST_INIT | sys_read32(config->base + CTRL), config->base + CTRL);
+	k_sem_reset(&data->ibi_cr_complete);
+	if (k_sem_take(&data->ibi_cr_complete, K_MSEC(500)) != 0) {
+		LOG_ERR("%s: timeout waiting for GETACCCR after CR", dev->name);
+		return -ETIMEDOUT;
+	}
+	return 0;
+}
+#endif /* CONFIG_I3C_CONTROLLER */
 static int cdns_i3c_target_ibi_raise_intr(const struct device *dev, struct i3c_ibi *request)
 {
 	const struct cdns_i3c_config *config = dev->config;
@@ -1151,6 +1212,17 @@ static int cdns_i3c_target_ibi_raise_intr(const struct device *dev, struct i3c_i
 
 	LOG_DBG("%s: issuing IBI TIR", dev->name);
 
+	/* Check if target does not have a DA assigned to it */
+	if (!(sys_read32(config->base + SLV_STATUS1) & SLV_STATUS1_HAS_DA)) {
+		LOG_ERR("%s: TIR not available, DA not assigned", dev->name);
+		return -EACCES;
+	}
+	/* Check if TIR requests DISEC CCC with DISMR field set has been received */
+	if (sys_read32(config->base + SLV_STATUS1) & SLV_STATUS1_IBI_DIS) {
+		LOG_ERR("%s: TIR requests are currently disabled by DISEC", dev->name);
+		return -EAGAIN;
+	}
+
 	/*
 	 * Ensure data will fit within FIFO
 	 *
@@ -1175,10 +1247,14 @@ static int cdns_i3c_target_ibi_raise_intr(const struct device *dev, struct i3c_i
 
 static int cdns_i3c_target_ibi_raise(const struct device *dev, struct i3c_ibi *request)
 {
+	const struct cdns_i3c_config *config = dev->config;
 	struct cdns_i3c_data *data = dev->data;
 
-	if (request == NULL) {
-		return -EINVAL;
+	__ASSERT_NO_MSG(request != NULL);
+
+	/* make sure we are not currently the active controller */
+	if (sys_read32(config->base + MST_STATUS0) & MST_STATUS0_MASTER_MODE) {
+		return -EACCES;
 	}
 
 	switch (request->ibi_type) {
@@ -1190,16 +1266,21 @@ static int cdns_i3c_target_ibi_raise(const struct device *dev, struct i3c_ibi *r
 			return -ENOTSUP;
 		}
 	case I3C_IBI_CONTROLLER_ROLE_REQUEST:
-		/* TODO: Cadence I3C can support CR, but not implemented yet */
+#ifdef CONFIG_I3C_CONTROLLER
+		return cdns_i3c_target_ibi_raise_cr(dev);
+#else
 		return -ENOTSUP;
+#endif
 	case I3C_IBI_HOTJOIN:
 		return cdns_i3c_target_ibi_raise_hj(dev);
 	default:
 		return -EINVAL;
 	}
 }
-#endif
+#endif /* CONFIG_I3C_TARGET */
+#endif /* CONFIG_I3C_USE_IBI */
 
+#ifdef CONFIG_I3C_CONTROLLER
 static void cdns_i3c_cancel_transfer(const struct device *dev)
 {
 	struct cdns_i3c_data *data = dev->data;
@@ -1495,6 +1576,13 @@ static int cdns_i3c_do_ccc(const struct device *dev, struct i3c_ccc_payload *pay
 	}
 
 	ret = data->xfer.ret;
+#if defined(CONFIG_I3C_CONTROLLER) && defined(CONFIG_I3C_TARGET)
+	/* TODO: decide if this is the right approach or add a new separate API for CH */
+	/* Wait for Controller Handoff to finish */
+	if (payload->ccc.id == I3C_CCC_GETACCCR) {
+		ret = k_sem_take(&data->ch_complete, K_MSEC(1000));
+	}
+#endif /* CONFIG_I3C_CONTROLLER && CONFIG_I3C_TARGET */
 error:
 	k_mutex_unlock(&data->bus_lock);
 
@@ -1514,14 +1602,8 @@ static int cdns_i3c_do_daa(const struct device *dev)
 {
 	struct cdns_i3c_data *data = dev->data;
 	const struct cdns_i3c_config *config = dev->config;
-	struct i3c_config_controller *ctrl_config = &data->common.ctrl_config;
 	uint8_t last_addr = 0;
 
-	/* DAA should not be done by secondary controllers */
-	if (ctrl_config->is_secondary) {
-		return -EACCES;
-	}
-
 	/* read dev active reg */
 	uint32_t olddevs = sys_read32(config->base + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
 	/* ignore the controller register */
@@ -1580,20 +1662,46 @@ static int cdns_i3c_do_daa(const struct device *dev)
 				const struct i3c_device_id i3c_id = I3C_DEVICE_ID(pid);
 				struct i3c_device_desc *target = i3c_device_find(dev, &i3c_id);
 
-				if (target == NULL) {
+				if (!target) {
+					/* Target found that is not known, allocate a desc */
+					target = i3c_device_desc_alloc();
+					if (target) {
+						/*
+						 * able to allocate a descriptor
+						 * write all known values
+						 */
+						*(const struct device **)&target->bus = dev;
+						*(uint64_t *)&target->pid = pid;
+						target->dynamic_addr = dyn_addr;
+						target->bcr = bcr;
+						target->dcr = dcr;
+						/* attach it to the slist */
+						sys_slist_append(
+							&data->common.attached_dev.devices.i3c,
+							&target->node);
+
+						data->cdns_i3c_i2c_priv_data[rr_idx].id = rr_idx;
+						target->controller_priv =
+							&(data->cdns_i3c_i2c_priv_data[rr_idx]);
+					}
+
 					LOG_INF("%s: PID 0x%012llx is not in registered device "
 						"list, given DA 0x%02x",
 						dev->name, pid, dyn_addr);
-					i3c_addr_slots_mark_i3c(
-						&data->common.attached_dev.addr_slots, dyn_addr);
 				} else {
 					target->dynamic_addr = dyn_addr;
 					target->bcr = bcr;
 					target->dcr = dcr;
 
+					data->cdns_i3c_i2c_priv_data[rr_idx].id = rr_idx;
+					target->controller_priv =
+						&(data->cdns_i3c_i2c_priv_data[rr_idx]);
+
 					LOG_DBG("%s: PID 0x%012llx assigned dynamic address 0x%02x",
 						dev->name, pid, dyn_addr);
 				}
+				i3c_addr_slots_mark_i3c(&data->common.attached_dev.addr_slots,
+							dyn_addr);
 			}
 		}
 	} else {
@@ -1657,6 +1765,7 @@ static int cdns_i3c_i2c_api_configure(const struct device *dev, uint32_t config)
 
 	return 0;
 }
+#endif /* CONFIG_I3C_CONTROLLER */
 
 /**
  * @brief Configure I3C hardware.
@@ -1673,23 +1782,38 @@ static int cdns_i3c_i2c_api_configure(const struct device *dev, uint32_t config)
  */
 static int cdns_i3c_configure(const struct device *dev, enum i3c_config_type type, void *config)
 {
-	struct cdns_i3c_data *data = dev->data;
-	struct i3c_config_controller *ctrl_cfg = config;
+	if (type == I3C_CONFIG_CONTROLLER) {
+#ifdef CONFIG_I3C_CONTROLLER
+		struct cdns_i3c_data *data = dev->data;
+		struct i3c_config_controller *ctrl_cfg = config;
 
-	if ((ctrl_cfg->scl.i2c == 0U) || (ctrl_cfg->scl.i3c == 0U)) {
-		return -EINVAL;
-	}
+		if ((ctrl_cfg->scl.i2c == 0U) || (ctrl_cfg->scl.i3c == 0U)) {
+			return -EINVAL;
+		}
 
-	data->common.ctrl_config.scl.i3c = ctrl_cfg->scl.i3c;
-	data->common.ctrl_config.scl.i2c = ctrl_cfg->scl.i2c;
+		data->common.ctrl_config.scl.i3c = ctrl_cfg->scl.i3c;
+		data->common.ctrl_config.scl.i2c = ctrl_cfg->scl.i2c;
 
-	k_mutex_lock(&data->bus_lock, K_FOREVER);
-	cdns_i3c_set_prescalers(dev);
-	k_mutex_unlock(&data->bus_lock);
+		k_mutex_lock(&data->bus_lock, K_FOREVER);
+		cdns_i3c_set_prescalers(dev);
+		k_mutex_unlock(&data->bus_lock);
+#else
+		return -ENOTSUP;
+#endif
+	} else if (type == I3C_CONFIG_TARGET) {
+#ifdef CONFIG_I3C_TARGET
+		return 0;
+#else
+		return -ENOTSUP;
+#endif
+	} else {
+		return -EINVAL;
+	}
 
 	return 0;
 }
 
+#ifdef CONFIG_I3C_CONTROLLER
 /**
  * @brief Complete a I3C/I2C Transfer
  *
@@ -1871,7 +1995,8 @@ static void cdns_i3c_complete_transfer(const struct device *dev)
 
 	k_sem_give(&data->xfer.complete);
 }
-
+#endif /* CONFIG_I3C_CONTROLLER */
+#if CONFIG_I3C_CONTROLLER
 /**
  * @brief Transfer messages in I2C mode.
  *
@@ -2252,14 +2377,12 @@ static int cdns_i3c_transfer(const struct device *dev, struct i3c_device_desc *t
 			cmd->cmd0 |= CMD0_FIFO_DEV_ADDR(target->dynamic_addr);
 			if ((msgs[i].flags & I3C_MSG_RW_MASK) == I3C_MSG_READ) {
 				cmd->cmd0 |= CMD0_FIFO_RNW;
-				/*
-				 * For I3C_XMIT_MODE_NO_ADDR reads in SDN mode,
-				 * CMD0_FIFO_PL_LEN specifies the abort limit not bytes to read
-				 */
-				cmd->cmd0 |= CMD0_FIFO_PL_LEN(pl + 1);
-			} else {
-				cmd->cmd0 |= CMD0_FIFO_PL_LEN(pl);
 			}
+			/*
+			 * For I3C_XMIT_MODE_NO_ADDR reads in SDN mode,
+			 * CMD0_FIFO_PL_LEN specifies the abort limit not bytes to read
+			 */
+			cmd->cmd0 |= CMD0_FIFO_PL_LEN(pl);
 
 			/* Send broadcast header on first transfer or after a STOP. */
 			if (!(msgs[i].flags & I3C_MSG_NBCH) && (send_broadcast)) {
@@ -2360,8 +2483,10 @@ static int cdns_i3c_transfer(const struct device *dev, struct i3c_device_desc *t
 
 	return ret;
 }
+#endif /* CONFIG_I3C_CONTROLLER */
 
 #ifdef CONFIG_I3C_USE_IBI
+#ifdef CONFIG_I3C_CONTROLLER
 static int cdns_i3c_read_ibi_fifo(const struct cdns_i3c_config *config, void *buf, uint32_t len)
 {
 	uint32_t *ptr = buf;
@@ -2439,7 +2564,53 @@ static void cdns_i3c_handle_ibi(const struct device *dev, uint32_t ibir)
 		LOG_ERR("%s: Error enqueue IBI IRQ work", dev->name);
 	}
 }
+#ifdef CONFIG_I3C_TARGET
+static void cdns_i3c_handle_cr(const struct device *dev, uint32_t ibir)
+{
+	const struct cdns_i3c_config *config = dev->config;
 
+	/* The slave ID returned here is the device ID in the SIR map NOT the device ID
+	 * in the RR map.
+	 */
+	uint8_t slave_id = IBIR_SLVID(ibir);
+
+	if (slave_id == IBIR_SLVID_INV) {
+		/* DA does not match any value among SIR map */
+		return;
+	}
+
+	uint32_t dev_id_rr0 = sys_read32(config->base + DEV_ID_RR0(slave_id + 1));
+	uint8_t dyn_addr = DEV_ID_RR0_GET_DEV_ADDR(dev_id_rr0);
+	struct i3c_device_desc *desc = i3c_dev_list_i3c_addr_find(dev, dyn_addr);
+
+	/*
+	 * Check for NAK or error conditions.
+	 *
+	 * Note: The logging is for debugging only so will be compiled out in most cases.
+	 * However, if the log level for this module is DEBUG and log mode is IMMEDIATE or MINIMAL,
+	 * this option is also set this may cause problems due to being inside an ISR.
+	 */
+	if (!(IBIR_ACKED & ibir)) {
+		LOG_DBG("%s: NAK for slave ID %u", dev->name, (unsigned int)slave_id);
+		return;
+	}
+	if (ibir & IBIR_ERROR) {
+		LOG_ERR("%s: Data overflow", dev->name);
+		return;
+	}
+
+	if (i3c_ibi_work_enqueue_controller_request(desc) != 0) {
+		LOG_ERR("%s: Error enqueue IBI IRQ work", dev->name);
+	}
+}
+
+static void cdns_i3c_target_ibi_cr_complete(const struct device *dev)
+{
+	struct cdns_i3c_data *data = dev->data;
+
+	k_sem_give(&data->ibi_cr_complete);
+}
+#endif /* CONFIG_I3C_TARGET */
 static void cdns_i3c_handle_hj(const struct device *dev, uint32_t ibir)
 {
 	if (!(IBIR_ACKED & ibir)) {
@@ -2447,6 +2618,7 @@ static void cdns_i3c_handle_hj(const struct device *dev, uint32_t ibir)
 		return;
 	}
 
+	/* TODO: disable CTRL_HJ_DISEC and process auto-ENTDAA*/
 	if (i3c_ibi_work_enqueue_hotjoin(dev) != 0) {
 		LOG_ERR("%s: Error enqueue IBI HJ work", dev->name);
 	}
@@ -2468,22 +2640,27 @@ static void cnds_i3c_master_demux_ibis(const struct device *dev)
 			cdns_i3c_handle_hj(dev, ibir);
 			break;
 		case IBIR_TYPE_MR:
-			/* not implemented */
+#ifdef CONFIG_I3C_TARGET
+			cdns_i3c_handle_cr(dev, ibir);
+#endif /* CONFIG_I3C_TARGET */
 			break;
 		default:
 			break;
 		}
 	}
 }
-
+#endif /* CONFIG_I3C_CONTROLLER */
+#ifdef CONFIG_I3C_TARGET
 static void cdns_i3c_target_ibi_hj_complete(const struct device *dev)
 {
 	struct cdns_i3c_data *data = dev->data;
 
 	k_sem_give(&data->ibi_hj_complete);
 }
-#endif
+#endif /* CONFIG_I3C_TARGET */
+#endif /* CONFIG_I3C_USE_IBI */
 
+#ifdef CONFIG_I3C_TARGET
 static void cdns_i3c_target_sdr_tx_thr_int_handler(const struct device *dev,
 						   const struct i3c_target_callbacks *target_cb)
 {
@@ -2537,241 +2714,249 @@ static void cdns_i3c_target_sdr_tx_thr_int_handler(const struct device *dev,
 		}
 	}
 }
+#endif /* CONFIG_I3C_TARGET */
 
 static void cdns_i3c_irq_handler(const struct device *dev)
 {
 	const struct cdns_i3c_config *config = dev->config;
 	struct cdns_i3c_data *data = dev->data;
+#ifdef CONFIG_I3C_CONTROLLER
+	uint32_t int_st = sys_read32(config->base + MST_ISR);
 
-	if (sys_read32(config->base + MST_STATUS0) & MST_STATUS0_MASTER_MODE) {
-		uint32_t int_st = sys_read32(config->base + MST_ISR);
-		sys_write32(int_st, config->base + MST_ICR);
+	sys_write32(int_st, config->base + MST_ICR);
 
-		/* Command queue empty */
-		if (int_st & MST_INT_HALTED) {
-			LOG_WRN("Core Halted, 2 read aborts");
-		}
+	/* Command queue empty */
+	if (int_st & MST_INT_HALTED) {
+		LOG_WRN("Core Halted, 2 read aborts");
+	}
 
-		/* Command queue empty */
-		if (int_st & MST_INT_CMDD_EMP) {
-			cdns_i3c_complete_transfer(dev);
-		}
+	/* Command queue empty */
+	if (int_st & MST_INT_CMDD_EMP) {
+		cdns_i3c_complete_transfer(dev);
+	}
 
-		/* In-band interrupt */
-		if (int_st & MST_INT_IBIR_THR) {
+	/* In-band interrupt */
+	if (int_st & MST_INT_IBIR_THR) {
 #ifdef CONFIG_I3C_USE_IBI
-			cnds_i3c_master_demux_ibis(dev);
+		cnds_i3c_master_demux_ibis(dev);
 #else
-			LOG_ERR("%s: IBI received - Kconfig for using IBIs is not enabled",
-				dev->name);
+		LOG_ERR("%s: IBI received - Kconfig for using IBIs is not enabled", dev->name);
 #endif
-		}
+	}
 
-		/* In-band interrupt data threshold */
-		if (int_st & MST_INT_IBID_THR) {
+	/* In-band interrupt data threshold */
+	if (int_st & MST_INT_IBID_THR) {
 #ifdef CONFIG_I3C_USE_IBI
-			/* pop data out of the IBI FIFO */
-			while (!cdns_i3c_ibi_fifo_empty(config)) {
-				uint32_t *ptr = (uint32_t *)&data->ibi_buf
-							.ibi_data[data->ibi_buf.ibi_data_cnt];
-				*ptr = sys_le32_to_cpu(sys_read32(config->base + IBI_DATA_FIFO));
-				data->ibi_buf.ibi_data_cnt += 4;
-			}
+		/* pop data out of the IBI FIFO */
+		while (!cdns_i3c_ibi_fifo_empty(config)) {
+			uint32_t *ptr =
+				(uint32_t *)&data->ibi_buf.ibi_data[data->ibi_buf.ibi_data_cnt];
+			*ptr = sys_le32_to_cpu(sys_read32(config->base + IBI_DATA_FIFO));
+			data->ibi_buf.ibi_data_cnt += 4;
+		}
 #else
-			LOG_ERR("%s: IBI received - Kconfig for using IBIs is not enabled",
-				dev->name);
+		LOG_ERR("%s: IBI received - Kconfig for using IBIs is not enabled", dev->name);
 #endif
-		}
+	}
 
-		/* In-band interrupt response overflow */
-		if (int_st & MST_INT_IBIR_OVF) {
-			LOG_ERR("%s: controller ibir overflow,", dev->name);
-		}
+	/* In-band interrupt response overflow */
+	if (int_st & MST_INT_IBIR_OVF) {
+		LOG_ERR("%s: controller ibir overflow,", dev->name);
+	}
 
-		/* In-band interrupt data */
-		if (int_st & MST_INT_TX_OVF) {
-			LOG_ERR("%s: controller tx buffer overflow,", dev->name);
-		}
+	/* In-band interrupt data */
+	if (int_st & MST_INT_TX_OVF) {
+		LOG_ERR("%s: controller tx buffer overflow,", dev->name);
+	}
 
-		/* In-band interrupt data */
-		if (int_st & MST_INT_RX_UNF) {
-			LOG_ERR("%s: controller rx buffer underflow,", dev->name);
-		}
-	} else {
-		uint32_t int_sl = sys_read32(config->base + SLV_ISR);
-		const struct i3c_target_callbacks *target_cb =
-			data->target_config ? data->target_config->callbacks : NULL;
-		/* Clear interrupts */
-		sys_write32(int_sl, config->base + SLV_ICR);
-
-		/* SLV SDR rx fifo threshold */
-		if (int_sl & SLV_INT_SDR_RX_THR) {
-			/* while rx fifo is not empty */
-			while (!(sys_read32(config->base + SLV_STATUS1) &
-				 SLV_STATUS1_SDR_RX_EMPTY)) {
-				if (target_cb != NULL && target_cb->write_received_cb != NULL) {
-					cdns_i3c_target_read_rx_fifo(dev);
-				}
+	/* In-band interrupt data */
+	if (int_st & MST_INT_RX_UNF) {
+		LOG_ERR("%s: controller rx buffer underflow,", dev->name);
+	}
+#ifdef CONFIG_I3C_TARGET
+	if (int_st & MST_INT_MR_DONE) {
+		LOG_DBG("%s: controller CR Handoff done,", dev->name);
+		k_sem_give(&data->ch_complete);
+	}
+#endif /* CONFIG_I3C_TARGET */
+#endif /* CONFIG_I3C_CONTROLLER */
+#ifdef CONFIG_I3C_TARGET
+	uint32_t int_sl = sys_read32(config->base + SLV_ISR);
+	const struct i3c_target_callbacks *target_cb =
+		data->target_config ? data->target_config->callbacks : NULL;
+	/* Clear interrupts */
+	sys_write32(int_sl, config->base + SLV_ICR);
+
+	/* SLV SDR rx fifo threshold */
+	if (int_sl & SLV_INT_SDR_RX_THR) {
+		/* while rx fifo is not empty */
+		while (!(sys_read32(config->base + SLV_STATUS1) & SLV_STATUS1_SDR_RX_EMPTY)) {
+			if (target_cb != NULL && target_cb->write_received_cb != NULL) {
+				cdns_i3c_target_read_rx_fifo(dev);
 			}
 		}
+	}
 
-		/* SLV SDR tx fifo threshold */
-		if (int_sl & SLV_INT_SDR_TX_THR) {
-			cdns_i3c_target_sdr_tx_thr_int_handler(dev, target_cb);
-		}
+	/* SLV SDR tx fifo threshold */
+	if (int_sl & SLV_INT_SDR_TX_THR) {
+		cdns_i3c_target_sdr_tx_thr_int_handler(dev, target_cb);
+	}
 
-		/* SLV SDR rx complete */
-		if (int_sl & SLV_INT_SDR_RD_COMP) {
-			/* a read needs to be done on slv_status 0 else a NACK will happen */
-			(void)sys_read32(config->base + SLV_STATUS0);
-			/* call stop function pointer */
-			if (target_cb != NULL && target_cb->stop_cb) {
-				target_cb->stop_cb(data->target_config);
-			}
+	/* SLV SDR rx complete */
+	if (int_sl & SLV_INT_SDR_RD_COMP) {
+		/* a read needs to be done on slv_status 0 else a NACK will happen */
+		(void)sys_read32(config->base + SLV_STATUS0);
+		/* call stop function pointer */
+		if (target_cb != NULL && target_cb->stop_cb) {
+			target_cb->stop_cb(data->target_config);
 		}
+	}
 
-		/* SLV SDR tx complete */
-		if (int_sl & SLV_INT_SDR_WR_COMP) {
-			/* a read needs to be done on slv_status 0 else a NACK will happen */
-			(void)sys_read32(config->base + SLV_STATUS0);
-			/* clear bytes read parameter */
-			data->fifo_bytes_read = 0;
-			/* call stop function pointer */
-			if (target_cb != NULL && target_cb->stop_cb) {
-				target_cb->stop_cb(data->target_config);
-			}
+	/* SLV SDR tx complete */
+	if (int_sl & SLV_INT_SDR_WR_COMP) {
+		/* a read needs to be done on slv_status 0 else a NACK will happen */
+		(void)sys_read32(config->base + SLV_STATUS0);
+		/* clear bytes read parameter */
+		data->fifo_bytes_read = 0;
+		/* call stop function pointer */
+		if (target_cb != NULL && target_cb->stop_cb) {
+			target_cb->stop_cb(data->target_config);
 		}
+	}
 
-		/* DA has been updated */
-		if (int_sl & SLV_INT_DA_UPD) {
-			LOG_INF("%s: DA updated to 0x%02lx", dev->name,
-				SLV_STATUS1_DA(sys_read32(config->base + SLV_STATUS1)));
-			/* HJ could send a DISEC which would trigger the SLV_INT_EVENT_UP bit,
-			 * but it's still expected to eventually send a DAA
-			 */
+	/* DA has been updated */
+	if (int_sl & SLV_INT_DA_UPD) {
+		LOG_INF("%s: DA updated to 0x%02lx", dev->name,
+			SLV_STATUS1_DA(sys_read32(config->base + SLV_STATUS1)));
 #ifdef CONFIG_I3C_USE_IBI
-			cdns_i3c_target_ibi_hj_complete(dev);
+		cdns_i3c_target_ibi_hj_complete(dev);
 #endif
-		}
-
-		/* HJ complete and DA has been assigned */
-		if (int_sl & SLV_INT_HJ_DONE) {
-		}
+	}
 
-		/* Controllership has been been given */
-		if (int_sl & SLV_INT_MR_DONE) {
-			/* TODO: implement support for controllership handoff */
-		}
+	/* HJ complete and DA has been assigned or HJ NACK'ed or DISEC disabled HJ */
+	if (int_sl & SLV_INT_HJ_DONE) {
+	}
 
-		/* EISC or DISEC has been received */
-		if (int_sl & SLV_INT_EVENT_UP) {
-		}
+	/* EISC or DISEC has been received */
+	if (int_sl & SLV_INT_EVENT_UP) {
+	}
 
-		/* sdr transfer aborted by controller */
-		if (int_sl & SLV_INT_M_RD_ABORT) {
-			/* TODO: consider flushing tx buffer? */
-		}
+	/* sdr transfer aborted by controller */
+	if (int_sl & SLV_INT_M_RD_ABORT) {
+		/* TODO: consider flushing tx buffer? */
+	}
 
-		/* SLV SDR rx fifo underflow */
-		if (int_sl & SLV_INT_SDR_RX_UNF) {
-			LOG_ERR("%s: slave sdr rx buffer underflow", dev->name);
-		}
+	/* SLV SDR rx fifo underflow */
+	if (int_sl & SLV_INT_SDR_RX_UNF) {
+		LOG_ERR("%s: slave sdr rx buffer underflow", dev->name);
+	}
 
-		/* SLV SDR tx fifo overflow */
-		if (int_sl & SLV_INT_SDR_TX_OVF) {
-			LOG_ERR("%s: slave sdr tx buffer overflow,", dev->name);
-		}
+	/* SLV SDR tx fifo overflow */
+	if (int_sl & SLV_INT_SDR_TX_OVF) {
+		LOG_ERR("%s: slave sdr tx buffer overflow,", dev->name);
+	}
 
-		if (int_sl & SLV_INT_DDR_RX_THR) {
-		}
+	if (int_sl & SLV_INT_DDR_RX_THR) {
+	}
 
-		/* SLV DDR WR COMPLETE */
-		if (int_sl & SLV_INT_DDR_WR_COMP) {
-			/* initial value of CRC5 for HDR-DDR is 0x1F */
-			uint8_t crc5 = 0x1F;
+	/* SLV DDR WR COMPLETE */
+	if (int_sl & SLV_INT_DDR_WR_COMP) {
+		/* initial value of CRC5 for HDR-DDR is 0x1F */
+		uint8_t crc5 = 0x1F;
 
-			while (!(sys_read32(config->base + SLV_STATUS1) &
-				 SLV_STATUS1_DDR_RX_EMPTY)) {
-				uint32_t ddr_rx_data = sys_read32(config->base + SLV_DDR_RX_FIFO);
-				uint32_t preamble = (ddr_rx_data & DDR_PREAMBLE_MASK);
+		while (!(sys_read32(config->base + SLV_STATUS1) & SLV_STATUS1_DDR_RX_EMPTY)) {
+			uint32_t ddr_rx_data = sys_read32(config->base + SLV_DDR_RX_FIFO);
+			uint32_t preamble = (ddr_rx_data & DDR_PREAMBLE_MASK);
 
-				if (preamble == DDR_PREAMBLE_DATA_ABORT ||
-				    preamble == DDR_PREAMBLE_DATA_ABORT_ALT) {
-					uint16_t ddr_payload = DDR_DATA(ddr_rx_data);
+			if (preamble == DDR_PREAMBLE_DATA_ABORT ||
+			    preamble == DDR_PREAMBLE_DATA_ABORT_ALT) {
+				uint16_t ddr_payload = DDR_DATA(ddr_rx_data);
 
-					if (cdns_i3c_ddr_parity(ddr_payload) !=
-					    (ddr_rx_data & (DDR_ODD_PARITY | DDR_EVEN_PARITY))) {
-						LOG_ERR("%s: Received incorrect DDR Parity",
-							dev->name);
-					}
-					/* calculate a running a crc */
-					crc5 = i3c_cdns_crc5(crc5, ddr_payload);
-
-					if (target_cb != NULL &&
-					    target_cb->write_received_cb != NULL) {
-						/* DDR receives 2B for each payload */
-						target_cb->write_received_cb(
-							data->target_config,
-							(uint8_t)((ddr_payload >> 8) & 0xFF));
-						target_cb->write_received_cb(
-							data->target_config,
-							(uint8_t)(ddr_payload));
-					}
+				if (cdns_i3c_ddr_parity(ddr_payload) !=
+				    (ddr_rx_data & (DDR_ODD_PARITY | DDR_EVEN_PARITY))) {
+					LOG_ERR("%s: Received incorrect DDR Parity", dev->name);
+				}
+				/* calculate a running a crc */
+				crc5 = i3c_cdns_crc5(crc5, ddr_payload);
 
-				} else if ((preamble == DDR_PREAMBLE_CMD_CRC) &&
-					   ((ddr_rx_data & DDR_CRC_TOKEN_MASK) == DDR_CRC_TOKEN)) {
-					/* should come through here last */
-					if (crc5 != DDR_CRC(ddr_rx_data)) {
-						LOG_ERR("%s: Received incorrect DDR CRC5",
-							dev->name);
-					}
-				} else if (preamble == DDR_PREAMBLE_CMD_CRC) {
-					/* should come through here first */
-					uint16_t ddr_header_payload = DDR_DATA(ddr_rx_data);
+				if (target_cb != NULL && target_cb->write_received_cb != NULL) {
+					/* DDR receives 2B for each payload */
+					target_cb->write_received_cb(
+						data->target_config,
+						(uint8_t)((ddr_payload >> 8) & 0xFF));
+					target_cb->write_received_cb(data->target_config,
+								     (uint8_t)(ddr_payload));
+				}
 
-					crc5 = i3c_cdns_crc5(crc5, ddr_header_payload);
+			} else if ((preamble == DDR_PREAMBLE_CMD_CRC) &&
+				   ((ddr_rx_data & DDR_CRC_TOKEN_MASK) == DDR_CRC_TOKEN)) {
+				/* should come through here last */
+				if (crc5 != DDR_CRC(ddr_rx_data)) {
+					LOG_ERR("%s: Received incorrect DDR CRC5", dev->name);
 				}
-			}
+			} else if (preamble == DDR_PREAMBLE_CMD_CRC) {
+				/* should come through here first */
+				uint16_t ddr_header_payload = DDR_DATA(ddr_rx_data);
 
-			if (target_cb != NULL && target_cb->stop_cb != NULL) {
-				target_cb->stop_cb(data->target_config);
+				crc5 = i3c_cdns_crc5(crc5, ddr_header_payload);
 			}
 		}
 
-		/* SLV SDR rx complete */
-		if (int_sl & SLV_INT_DDR_RD_COMP) {
-			/* a read needs to be done on slv_status 0 else a NACK will happen */
-			(void)sys_read32(config->base + SLV_STATUS0);
-			/* call stop function pointer */
-			if (target_cb != NULL && target_cb->stop_cb) {
-				target_cb->stop_cb(data->target_config);
-			}
+		if (target_cb != NULL && target_cb->stop_cb != NULL) {
+			target_cb->stop_cb(data->target_config);
 		}
+	}
 
-		/*SLV DDR TX THR*/
-		if (int_sl & SLV_INT_DDR_TX_THR) {
-			int status = 0;
+	/* SLV SDR rx complete */
+	if (int_sl & SLV_INT_DDR_RD_COMP) {
+		/* a read needs to be done on slv_status 0 else a NACK will happen */
+		(void)sys_read32(config->base + SLV_STATUS0);
+		/* call stop function pointer */
+		if (target_cb != NULL && target_cb->stop_cb) {
+			target_cb->stop_cb(data->target_config);
+		}
+	}
 
-			if (target_cb != NULL && target_cb->read_processed_cb) {
+	/* SLV DDR TX THR */
+	if (int_sl & SLV_INT_DDR_TX_THR) {
+		int status = 0;
 
-				while ((!(sys_read32(config->base + SLV_STATUS1) &
-					  SLV_STATUS1_DDR_TX_FULL)) &&
-				       (status == 0)) {
-					/* call function pointer for read */
-					uint8_t byte;
-					/* will return negative if no data left to transmit
-					 * and 0 if data available
-					 */
-					status = target_cb->read_processed_cb(data->target_config,
-									      &byte);
-					if (status == 0) {
-						cdns_i3c_write_ddr_tx_fifo(config, &byte,
-									   sizeof(byte));
-					}
+		if (target_cb != NULL && target_cb->read_processed_cb) {
+
+			while ((!(sys_read32(config->base + SLV_STATUS1) &
+				  SLV_STATUS1_DDR_TX_FULL)) &&
+			       (status == 0)) {
+				/* call function pointer for read */
+				uint8_t byte;
+				/* will return negative if no data left to transmit
+				 * and 0 if data available
+				 */
+				status = target_cb->read_processed_cb(data->target_config, &byte);
+				if (status == 0) {
+					cdns_i3c_write_ddr_tx_fifo(config, &byte, sizeof(byte));
 				}
 			}
 		}
 	}
+#ifdef CONFIG_I3C_CONTROLLER
+	/* Controllership has been been given to us */
+	if (int_sl & SLV_INT_MR_DONE) {
+#ifdef CONFIG_I3C_USE_IBI
+		cdns_i3c_target_ibi_cr_complete(dev);
+		i3c_ibi_work_enqueue_cb(dev, i3c_sec_handoffed);
+		if (target_cb != NULL && target_cb->controller_handoff_cb) {
+			target_cb->controller_handoff_cb(data->target_config);
+		}
+#endif
+	}
+
+	/* DEFTGTS */
+	if (int_sl & SLV_INT_DEFSLVS) {
+		/* Execute outside of the ISR context */
+		k_work_submit(&data->deftgts_work);
+	}
+#endif /* CONFIG_I3C_CONTROLLER */
+#endif /* CONFIG_I3C_TARGET */
 }
 
 static void cdns_i3c_read_hw_cfg(const struct device *dev)
@@ -2846,19 +3031,58 @@ static void cdns_i3c_read_hw_cfg(const struct device *dev)
 static int cdns_i3c_config_get(const struct device *dev, enum i3c_config_type type, void *config)
 {
 	struct cdns_i3c_data *data = dev->data;
-	int ret = 0;
+	__ASSERT_NO_MSG(config != NULL);
 
-	if (config == NULL) {
-		ret = -EINVAL;
-		goto out_configure;
+	if (type == I3C_CONFIG_CONTROLLER) {
+#ifdef CONFIG_I3C_CONTROLLER
+		(void)memcpy(config, &data->common.ctrl_config, sizeof(data->common.ctrl_config));
+#else
+		return -EINVAL;
+#endif
+	} else if (type == I3C_CONFIG_TARGET) {
+#ifdef CONFIG_I3C_TARGET
+		const struct cdns_i3c_config *dev_config = dev->config;
+		struct i3c_config_target *target_config = (struct i3c_config_target *)config;
+		/* Read RR_0 registers for itself */
+		uint32_t dev_id_rr0 = sys_read32(dev_config->base + DEV_ID_RR0(0));
+		uint32_t dev_id_rr1 = sys_read32(dev_config->base + DEV_ID_RR1(0));
+		uint32_t dev_id_rr2 = sys_read32(dev_config->base + DEV_ID_RR2(0));
+		uint32_t slv_status1 = sys_read32(dev_config->base + SLV_STATUS1);
+
+		/* if we are currently a target */
+		target_config->enabled =
+			!!!(sys_read32(dev_config->base + MST_STATUS0) & MST_STATUS0_MASTER_MODE);
+		if (data->common.ctrl_config.is_secondary) {
+			target_config->dynamic_addr = SLV_STATUS1_DA(slv_status1);
+		} else {
+			target_config->dynamic_addr = (dev_id_rr0 & 0xFE) >> 1;
+		}
+		target_config->static_addr = 0;
+		target_config->pid = ((uint64_t)dev_id_rr1 << 16) + (dev_id_rr2 >> 16);
+		target_config->pid_random = !!(slv_status1 & SLV_STATUS1_VEN_TM);
+		target_config->bcr = dev_id_rr2 >> 8;
+		target_config->dcr = dev_id_rr2 & 0xFF;
+		/* Version 1p7 supports reading MRL/MWL */
+		if (REV_ID_REV(data->hw_cfg.rev_id) >= REV_ID_VERSION(1, 7)) {
+			target_config->max_read_len =
+				SLV_STATUS2_MRL(sys_read32(dev_config->base + SLV_STATUS2));
+			target_config->max_write_len =
+				SLV_STATUS3_MWL(sys_read32(dev_config->base + SLV_STATUS3));
+		} else {
+			target_config->max_read_len = 0;
+			target_config->max_write_len = 0;
+		}
+		target_config->supported_hdr = data->common.ctrl_config.supported_hdr;
+#else
+		return -EINVAL;
+#endif
+	} else {
+		return -EINVAL;
 	}
 
-	(void)memcpy(config, &data->common.ctrl_config, sizeof(data->common.ctrl_config));
-
-out_configure:
-	return ret;
+	return 0;
 }
-
+#ifdef CONFIG_I3C_TARGET
 static int cdns_i3c_target_tx_ddr_write(const struct device *dev, uint8_t *buf, uint16_t len)
 {
 	const struct cdns_i3c_config *config = dev->config;
@@ -3049,7 +3273,8 @@ static int cdns_i3c_target_unregister(const struct device *dev, struct i3c_targe
 	/* no way to disable? maybe write DA to 0? */
 	return 0;
 }
-
+#endif /* CONFIG_I3C_TARGET */
+#ifdef CONFIG_I3C_CONTROLLER
 /**
  * @brief Find a registered I3C target device.
  *
@@ -3086,7 +3311,8 @@ static struct i3c_i2c_device_desc *cdns_i3c_i2c_device_find(const struct device
 {
 	return i3c_dev_list_i2c_addr_find(dev, addr);
 }
-
+#endif
+#ifdef CONFIG_I3C_CONTROLLER
 /**
  * @brief Transfer messages in I2C mode.
  *
@@ -3113,7 +3339,34 @@ static int cdns_i3c_i2c_api_transfer(const struct device *dev, struct i2c_msg *m
 
 	return ret;
 }
+#endif /* CONFIG_I3C_CONTROLLER */
+#if defined(CONFIG_I3C_CONTROLLER) && defined(CONFIG_I3C_TARGET)
+/**
+ * ACK or NACK Controller Handoffs
+ *
+ * Reads the LVR of all I2C devices and returns the I3C bus
+ * Mode
+ *
+ * @param dev Pointer to device driver instance.
+ * @param accept True to accept controller handoffs, False to decline
+ *
+ * @return @see i3c_target_controller_handoff
+ */
+static int cdns_i3c_target_controller_handoff(const struct device *dev, bool accept)
+{
+	const struct cdns_i3c_config *config = dev->config;
+	uint32_t ctrl = sys_read32(config->base + CTRL);
 
+	if (accept) {
+		sys_write32(ctrl | CTRL_MST_ACK, config->base + CTRL);
+	} else {
+		sys_write32(ctrl & ~CTRL_MST_ACK, config->base + CTRL);
+	}
+
+	return 0;
+}
+#endif
+#ifdef CONFIG_I3C_CONTROLLER
 /**
  * Determine I3C bus mode from the i2c devices on the bus
  *
@@ -3175,7 +3428,91 @@ static uint8_t cdns_i3c_sda_data_hold(const struct device *dev)
 
 	return (THD_DELAY_MAX - thd_delay);
 }
+#endif /* CONFIG_I3C_CONTROLLER */
+#if defined(CONFIG_I3C_CONTROLLER) && defined(CONFIG_I3C_TARGET)
+static void i3c_cdns_deftgts_work_fn(struct k_work *work)
+{
+	const struct cdns_i3c_config *config;
+	struct cdns_i3c_data *data;
+	const struct device *dev;
+	uint32_t devs;
+	uint8_t count;
+	uint8_t n = 0;
+
+	data = CONTAINER_OF(work, struct cdns_i3c_data, deftgts_work);
+	dev = data->dev;
+	config = dev->config;
+	data = dev->data;
+
+	devs = sys_read32(config->base + DEVS_CTRL) & DEVS_CTRL_DEVS_ACTIVE_MASK;
+	data->free_rr_slots = GENMASK(data->max_devs, 1) & ~devs;
 
+	/*
+	 * count the number of ones in devs, The IP will 'skip' writing it self to the RR if
+	 * it was in DEFTGTS. Also, if the IP never had a DA, then the deftgts interrupt will
+	 * never fire. Subtract 1 as the active controller is not included in `count`.
+	 */
+	count = POPCOUNT(devs) - 1;
+
+	/* Free memory if it was previously allocated */
+	if (data->common.deftgts) {
+		free(data->common.deftgts);
+		data->common.deftgts = NULL;
+	}
+
+	/* Allocate memory for deftgts */
+	data->common.deftgts =
+		malloc(sizeof(uint8_t) + sizeof(struct i3c_ccc_deftgts_active_controller) +
+		       (count * sizeof(struct i3c_ccc_deftgts_target)));
+	if (!data->common.deftgts) {
+		LOG_ERR("%s: Failed to allocate memory for DEFTGTS", dev->name);
+		return;
+	}
+
+	data->common.deftgts->count = count;
+
+	for (uint8_t i = find_lsb_set(devs); i <= find_msb_set(devs); i++) {
+		uint8_t rr_idx = i - 1;
+
+		if (devs & BIT(rr_idx)) {
+			/* Read RRx registers */
+			uint32_t dev_id_rr0 = sys_read32(config->base + DEV_ID_RR0(rr_idx));
+			uint32_t dev_id_rr2 = sys_read32(config->base + DEV_ID_RR2(rr_idx));
+
+			uint8_t addr = (dev_id_rr0 & 0xFE) >> 1;
+			uint8_t bcr = dev_id_rr2 >> 8;
+			uint8_t dcr_lvr = dev_id_rr2 & 0xFF;
+			bool is_i3c = !!(dev_id_rr0 & DEV_ID_RR0_IS_I3C);
+
+			/* RR IDX 1 should always be expected to be the AC */
+			if (rr_idx == 1) {
+				data->common.deftgts->active_controller.addr = addr;
+				data->common.deftgts->active_controller.dcr = dcr_lvr;
+				data->common.deftgts->active_controller.bcr = bcr;
+				data->common.deftgts->active_controller.static_addr = 0;
+			} else if (is_i3c) {
+				data->common.deftgts->targets[n].addr = addr;
+				data->common.deftgts->targets[n].dcr = dcr_lvr;
+				data->common.deftgts->targets[n].bcr = bcr;
+				data->common.deftgts->targets[n].static_addr = 0;
+				n++;
+			} else {
+				data->common.deftgts->targets[n].addr = 0;
+				data->common.deftgts->targets[n].lvr = dcr_lvr;
+				data->common.deftgts->targets[n].bcr = 0;
+				data->common.deftgts->targets[n].static_addr = addr;
+				n++;
+			}
+		}
+	}
+	data->common.deftgts_refreshed = true;
+	LOG_HEXDUMP_DBG(
+		(uint8_t *)data->common.deftgts,
+		sizeof(uint8_t) + sizeof(struct i3c_ccc_deftgts_active_controller) +
+			(data->common.deftgts->count * sizeof(struct i3c_ccc_deftgts_target)),
+		"DEFTGTS Received");
+}
+#endif
 /**
  * @brief Initialize the hardware.
  *
@@ -3209,9 +3546,28 @@ static int cdns_i3c_bus_init(const struct device *dev)
 			(conf0 & CONF_STATUS0_SUPPORTS_DDR) ? I3C_MSG_HDR_DDR : 0;
 		ctrl_config->is_secondary = (conf0 & CONF_STATUS0_SEC_MASTER) ? true : false;
 	}
+	/*
+	 * Ensure that is_secondary is only set when CONFIG_I3C_TARGET is enabled,
+	 * or ensure that it is false when CONFIG_I3C_CONTROLLER is enabled.
+	 */
+	__ASSERT_NO_MSG((IS_ENABLED(CONFIG_I3C_TARGET) && ctrl_config->is_secondary) ||
+			(IS_ENABLED(CONFIG_I3C_CONTROLLER) && !ctrl_config->is_secondary));
+
 	k_mutex_init(&data->bus_lock);
 	k_sem_init(&data->xfer.complete, 0, 1);
+#if defined(CONFIG_I3C_CONTROLLER) && defined(CONFIG_I3C_TARGET)
+	data->dev = dev;
+	k_sem_init(&data->ch_complete, 0, 1);
+	k_work_init(&data->deftgts_work, i3c_cdns_deftgts_work_fn);
+#endif /* defined(CONFIG_I3C_CONTROLLER) && defined(CONFIG_I3C_TARGET) */
+#ifdef CONFIG_I3C_USE_IBI
+#ifdef CONFIG_I3C_TARGET
 	k_sem_init(&data->ibi_hj_complete, 0, 1);
+#ifdef CONFIG_I3C_CONTROLLER
+	k_sem_init(&data->ibi_cr_complete, 0, 1);
+#endif /* CONFIG_I3C_TARGET */
+#endif /* CONFIG_I3C_CONTROLLER */
+#endif
 
 	cdns_i3c_interrupts_disable(config);
 	cdns_i3c_interrupts_clear(config);
@@ -3220,7 +3576,7 @@ static int cdns_i3c_bus_init(const struct device *dev)
 
 	/* Ensure the bus is disabled. */
 	sys_write32(~CTRL_DEV_EN & sys_read32(config->base + CTRL), config->base + CTRL);
-
+#if defined(CONFIG_I3C_CONTROLLER)
 	/* determine prescaler timings for i3c and i2c scl */
 	cdns_i3c_set_prescalers(dev);
 
@@ -3243,7 +3599,7 @@ static int cdns_i3c_bus_init(const struct device *dev)
 	default:
 		return -EINVAL;
 	}
-
+#endif
 	/*
 	 * When a Hot-Join request happens, disable all events coming from this device.
 	 * We will issue ENTDAA afterwards from the threaded IRQ handler.
@@ -3251,16 +3607,20 @@ static int cdns_i3c_bus_init(const struct device *dev)
 	 *
 	 * Set the I3C Bus Mode based on the LVR of the I2C devices
 	 */
-	uint32_t ctrl = CTRL_HJ_DISEC | CTRL_MCS_EN | (CTRL_BUS_MODE_MASK & cdns_mode);
-	/* Disable Controllership requests as it is not supported yet by the driver */
-	ctrl &= ~CTRL_MST_ACK;
+	uint32_t ctrl = CTRL_HJ_DISEC | CTRL_MCS_EN;
+#if defined(CONFIG_I3C_CONTROLLER) && defined(CONFIG_I3C_TARGET)
+	ctrl |= CTRL_MST_ACK;
+#endif
 
+#ifdef CONFIG_I3C_CONTROLLER
+	ctrl |= (CTRL_BUS_MODE_MASK & cdns_mode);
 	/*
 	 * Cadence I3C release r104v1p0 and above support configuration of the sda data hold time
 	 */
 	if (REV_ID_REV(data->hw_cfg.rev_id) >= REV_ID_VERSION(1, 4)) {
 		ctrl |= CTRL_THD_DELAY(cdns_i3c_sda_data_hold(dev));
 	}
+#endif /* CONFIG_I3C_CONTROLLER */
 
 	/*
 	 * Cadence I3C release r105v1p0 and above support I3C v1.1 timing change
@@ -3278,8 +3638,8 @@ static int cdns_i3c_bus_init(const struct device *dev)
 	sys_write32(CTRL_DEV_EN | ctrl, config->base + CTRL);
 
 	/* Set fifo thresholds. */
-	sys_write32(CMD_THR(I3C_CMDD_THR) | IBI_THR(I3C_IBID_THR) | CMDR_THR(I3C_CMDR_THR) |
-			    IBIR_THR(config->ibid_thr),
+	sys_write32(CMD_THR(I3C_CMDD_THR) | IBI_THR(config->ibid_thr) | CMDR_THR(I3C_CMDR_THR) |
+			    IBIR_THR(I3C_IBIR_THR),
 		    config->base + CMD_IBI_THR_CTRL);
 
 	/* Set TX/RX interrupt thresholds. */
@@ -3291,17 +3651,19 @@ static int cdns_i3c_bus_init(const struct device *dev)
 		sys_write32(SLV_DDR_TX_THR(0) | SLV_DDR_RX_THR(1),
 			    config->base + SLV_DDR_TX_RX_THR_CTRL);
 	}
-
+#ifdef CONFIG_I3C_TARGET
 	/* enable target interrupts */
 	sys_write32(SLV_INT_DA_UPD | SLV_INT_SDR_RD_COMP | SLV_INT_SDR_WR_COMP |
 			    SLV_INT_SDR_RX_THR | SLV_INT_SDR_TX_THR | SLV_INT_SDR_RX_UNF |
-			    SLV_INT_SDR_TX_OVF | SLV_INT_HJ_DONE | SLV_INT_DDR_WR_COMP |
-			    SLV_INT_DDR_RD_COMP | SLV_INT_DDR_RX_THR | SLV_INT_DDR_TX_THR,
+			    SLV_INT_SDR_TX_OVF | SLV_INT_HJ_DONE | SLV_INT_MR_DONE |
+			    SLV_INT_DEFSLVS | SLV_INT_DDR_WR_COMP | SLV_INT_DDR_RD_COMP |
+			    SLV_INT_DDR_RX_THR | SLV_INT_DDR_TX_THR,
 		    config->base + SLV_IER);
-
-	/* Enable IBI interrupts. */
-	sys_write32(MST_INT_IBIR_THR | MST_INT_RX_UNF | MST_INT_HALTED | MST_INT_TX_OVF |
-			    MST_INT_IBIR_OVF | MST_INT_IBID_THR,
+#endif /* CONFIG_I3C_TARGET */
+#ifdef CONFIG_I3C_CONTROLLER
+	/* Enable controller interrupts. */
+	sys_write32(MST_INT_IBIR_THR | MST_INT_RX_UNF | MST_INT_HALTED | MST_INT_MR_DONE |
+			    MST_INT_TX_OVF | MST_INT_IBIR_OVF | MST_INT_IBID_THR,
 		    config->base + MST_IER);
 
 	int ret = i3c_addr_slots_init(dev);
@@ -3310,11 +3672,10 @@ static int cdns_i3c_bus_init(const struct device *dev)
 		return ret;
 	}
 
-	/* Program retaining regs. */
-	cdns_i3c_program_controller_retaining_reg(dev);
-
 	/* only primary controllers are responsible for initializing the bus */
 	if (!ctrl_config->is_secondary) {
+		/* Program retaining regs. */
+		cdns_i3c_program_controller_retaining_reg(dev);
 		/* Sleep to wait for bus idle. */
 		k_busy_wait(201);
 		/* Perform bus initialization */
@@ -3324,20 +3685,22 @@ static int cdns_i3c_bus_init(const struct device *dev)
 		sys_write32(CTRL_HJ_ACK | sys_read32(config->base + CTRL), config->base + CTRL);
 #endif
 	}
-
+#endif /* CONFIG_I3C_CONTROLLER */
 	return 0;
 }
 
 static DEVICE_API(i3c, api) = {
+#ifdef CONFIG_I3C_CONTROLLER
 	.i2c_api.configure = cdns_i3c_i2c_api_configure,
 	.i2c_api.transfer = cdns_i3c_i2c_api_transfer,
 #ifdef CONFIG_I2C_RTIO
 	.i2c_api.iodev_submit = i2c_iodev_submit_fallback,
 #endif
+#endif /* CONFIG_I3C_CONTROLLER */
 
 	.configure = cdns_i3c_configure,
 	.config_get = cdns_i3c_config_get,
-
+#ifdef CONFIG_I3C_CONTROLLER
 	.attach_i3c_device = cdns_i3c_attach_device,
 	.reattach_i3c_device = cdns_i3c_reattach_device,
 	.detach_i3c_device = cdns_i3c_detach_device,
@@ -3350,16 +3713,24 @@ static DEVICE_API(i3c, api) = {
 	.i3c_device_find = cdns_i3c_device_find,
 
 	.i3c_xfers = cdns_i3c_transfer,
-
+#endif /* CONFIG_I3C_CONTROLLER */
+#ifdef CONFIG_I3C_TARGET
 	.target_tx_write = cdns_i3c_target_tx_write,
 	.target_register = cdns_i3c_target_register,
 	.target_unregister = cdns_i3c_target_unregister,
-
+#ifdef CONFIG_I3C_CONTROLLER
+	.target_controller_handoff = cdns_i3c_target_controller_handoff,
+#endif /* CONFIG_I3C_CONTROLLER */
+#endif /* CONFIG_I3C_TARGET */
 #ifdef CONFIG_I3C_USE_IBI
+#ifdef CONFIG_I3C_CONTROLLER
 	.ibi_hj_response = cdns_i3c_ibi_hj_response,
 	.ibi_enable = cdns_i3c_controller_ibi_enable,
 	.ibi_disable = cdns_i3c_controller_ibi_disable,
+#endif /* CONFIG_I3C_CONTROLLER */
+#ifdef CONFIG_I3C_TARGET
 	.ibi_raise = cdns_i3c_target_ibi_raise,
+#endif /* CONFIG_I3C_TARGET */
 #endif
 
 #ifdef CONFIG_I3C_RTIO
@@ -3369,22 +3740,26 @@ static DEVICE_API(i3c, api) = {
 
 #define CADENCE_I3C_INSTANTIATE(n)                                                                 \
 	static void cdns_i3c_config_func_##n(const struct device *dev);                            \
-	static struct i3c_device_desc cdns_i3c_device_array_##n[] = I3C_DEVICE_ARRAY_DT_INST(n);   \
+	IF_ENABLED(CONFIG_I3C_CONTROLLER,                                                          \
+	(static struct i3c_device_desc cdns_i3c_device_array_##n[] = I3C_DEVICE_ARRAY_DT_INST(n);  \
 	static struct i3c_i2c_device_desc cdns_i3c_i2c_device_array_##n[] =                        \
-		I3C_I2C_DEVICE_ARRAY_DT_INST(n);                                                   \
+		I3C_I2C_DEVICE_ARRAY_DT_INST(n);))                                                 \
 	static const struct cdns_i3c_config i3c_config_##n = {                                     \
 		.base = DT_INST_REG_ADDR(n),                                                       \
 		.input_frequency = DT_INST_PROP(n, input_clock_frequency),                         \
 		.irq_config_func = cdns_i3c_config_func_##n,                                       \
 		.ibid_thr = DT_INST_PROP(n, ibid_thr),                                             \
-		.common.dev_list.i3c = cdns_i3c_device_array_##n,                                  \
-		.common.dev_list.num_i3c = ARRAY_SIZE(cdns_i3c_device_array_##n),                  \
-		.common.dev_list.i2c = cdns_i3c_i2c_device_array_##n,                              \
-		.common.dev_list.num_i2c = ARRAY_SIZE(cdns_i3c_i2c_device_array_##n),              \
+		IF_ENABLED(CONFIG_I3C_CONTROLLER,                                                  \
+			(.common.dev_list.i3c = cdns_i3c_device_array_##n,                         \
+			.common.dev_list.num_i3c = ARRAY_SIZE(cdns_i3c_device_array_##n),          \
+			.common.dev_list.i2c = cdns_i3c_i2c_device_array_##n,                      \
+			.common.dev_list.num_i2c = ARRAY_SIZE(cdns_i3c_i2c_device_array_##n),      \
+			.common.primary_controller_da = DT_INST_PROP_OR(n, primary_controller_da, 0x00),)) \
 	};                                                                                         \
 	static struct cdns_i3c_data i3c_data_##n = {                                               \
-		.common.ctrl_config.scl.i3c = DT_INST_PROP_OR(n, i3c_scl_hz, 0),                   \
-		.common.ctrl_config.scl.i2c = DT_INST_PROP_OR(n, i2c_scl_hz, 0),                   \
+		IF_ENABLED(CONFIG_I3C_CONTROLLER,                                                  \
+			(.common.ctrl_config.scl.i3c = DT_INST_PROP(n, i3c_scl_hz),                \
+			.common.ctrl_config.scl.i2c = DT_INST_PROP(n, i2c_scl_hz),))               \
 	};                                                                                         \
 	DEVICE_DT_INST_DEFINE(n, cdns_i3c_bus_init, NULL, &i3c_data_##n, &i3c_config_##n,          \
 			      POST_KERNEL, CONFIG_I3C_CONTROLLER_INIT_PRIORITY, &api);             \
diff --git a/drivers/i3c/i3c_common.c b/drivers/i3c/i3c_common.c
index 7f580f4059e..2f1b402a6ee 100644
--- a/drivers/i3c/i3c_common.c
+++ b/drivers/i3c/i3c_common.c
@@ -17,23 +17,21 @@
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(i3c, CONFIG_I3C_LOG_LEVEL);
 
-void i3c_dump_msgs(const char *name, const struct i3c_msg *msgs,
-		   uint8_t num_msgs, struct i3c_device_desc *target)
+void i3c_dump_msgs(const char *name, const struct i3c_msg *msgs, uint8_t num_msgs,
+		   struct i3c_device_desc *target)
 {
 	LOG_DBG("I3C msg: %s, addr=%x", name, target->dynamic_addr);
 	for (unsigned int i = 0; i < num_msgs; i++) {
 		const struct i3c_msg *msg = &msgs[i];
 
-		LOG_DBG("   %c len=%02x: ",
-			msg->flags & I3C_MSG_READ ? 'R' : 'W', msg->len);
+		LOG_DBG("   %c len=%02x: ", msg->flags & I3C_MSG_READ ? 'R' : 'W', msg->len);
 		if (!(msg->flags & I3C_MSG_READ)) {
 			LOG_HEXDUMP_DBG(msg->buf, msg->len, "contents:");
 		}
 	}
 }
 
-void i3c_addr_slots_set(struct i3c_addr_slots *slots,
-			uint8_t dev_addr,
+void i3c_addr_slots_set(struct i3c_addr_slots *slots, uint8_t dev_addr,
 			enum i3c_addr_slot_status status)
 {
 	int bitpos;
@@ -54,9 +52,7 @@ void i3c_addr_slots_set(struct i3c_addr_slots *slots,
 	slots->slots[idx] |= status << bitpos;
 }
 
-enum i3c_addr_slot_status
-i3c_addr_slots_status(struct i3c_addr_slots *slots,
-		      uint8_t dev_addr)
+enum i3c_addr_slot_status i3c_addr_slots_status(struct i3c_addr_slots *slots, uint8_t dev_addr)
 {
 	unsigned long status;
 	int bitpos;
@@ -82,13 +78,10 @@ i3c_addr_slots_status(struct i3c_addr_slots *slots,
 	return status;
 }
 
-
 int i3c_addr_slots_init(const struct device *dev)
 {
-	struct i3c_driver_data *data =
-		(struct i3c_driver_data *)dev->data;
-	const struct i3c_driver_config *config =
-		(const struct i3c_driver_config *)dev->config;
+	struct i3c_driver_data *data = (struct i3c_driver_data *)dev->data;
+	const struct i3c_driver_config *config = (const struct i3c_driver_config *)dev->config;
 	int i, ret = 0;
 	struct i3c_device_desc *i3c_dev;
 	struct i3c_i2c_device_desc *i2c_dev;
@@ -110,7 +103,6 @@ int i3c_addr_slots_init(const struct device *dev)
 		 */
 		i3c_addr_slots_set(&data->attached_dev.addr_slots, I3C_BROADCAST_ADDR ^ BIT(i),
 				   I3C_ADDR_SLOT_STATUS_RSVD);
-
 	}
 
 	/* The broadcast address is reserved */
@@ -149,8 +141,7 @@ int i3c_addr_slots_init(const struct device *dev)
 	return ret;
 }
 
-bool i3c_addr_slots_is_free(struct i3c_addr_slots *slots,
-			    uint8_t dev_addr)
+bool i3c_addr_slots_is_free(struct i3c_addr_slots *slots, uint8_t dev_addr)
 {
 	enum i3c_addr_slot_status status;
 
@@ -198,8 +189,7 @@ struct i3c_device_desc *i3c_dev_list_find(const struct i3c_dev_list *dev_list,
 	return ret;
 }
 
-struct i3c_device_desc *i3c_dev_list_i3c_addr_find(const struct device *dev,
-						   uint8_t addr)
+struct i3c_device_desc *i3c_dev_list_i3c_addr_find(const struct device *dev, uint8_t addr)
 {
 	struct i3c_device_desc *ret = NULL;
 	struct i3c_device_desc *desc;
@@ -216,8 +206,24 @@ struct i3c_device_desc *i3c_dev_list_i3c_addr_find(const struct device *dev,
 	return ret;
 }
 
-struct i3c_i2c_device_desc *i3c_dev_list_i2c_addr_find(const struct device *dev,
-							   uint16_t addr)
+struct i3c_device_desc *i3c_dev_list_i3c_static_addr_find(const struct device *dev, uint8_t addr)
+{
+	struct i3c_device_desc *ret = NULL;
+	struct i3c_device_desc *desc;
+
+	__ASSERT_NO_MSG(dev != NULL);
+
+	I3C_BUS_FOR_EACH_I3CDEV(dev, desc) {
+		if (desc->static_addr == addr) {
+			ret = desc;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+struct i3c_i2c_device_desc *i3c_dev_list_i2c_addr_find(const struct device *dev, uint16_t addr)
 {
 	struct i3c_i2c_device_desc *ret = NULL;
 	struct i3c_i2c_device_desc *desc;
@@ -318,6 +324,11 @@ int i3c_detach_i3c_device(struct i3c_device_desc *target)
 	i3c_addr_slots_mark_free(&data->attached_dev.addr_slots,
 				 target->dynamic_addr ? target->dynamic_addr : target->static_addr);
 
+	/* if it was from allocated memory, free it */
+	if (i3c_device_desc_in_pool(target)) {
+		i3c_device_desc_free(target);
+	}
+
 	return status;
 }
 
@@ -370,15 +381,175 @@ int i3c_detach_i2c_device(struct i3c_i2c_device_desc *target)
 
 	i3c_addr_slots_mark_free(&data->attached_dev.addr_slots, target->addr);
 
+	/* if it was from allocated memory, free it */
+	if (i3c_i2c_device_desc_in_pool(target)) {
+		i3c_i2c_device_desc_free(target);
+	}
+
 	return status;
 }
+#ifdef CONFIG_I3C_TARGET
+int i3c_sec_get_basic_info(const struct device *dev, uint8_t dynamic_addr, uint8_t static_addr,
+			   uint8_t bcr, uint8_t dcr)
+{
+	struct i3c_ccc_getpid getpid;
+	struct i3c_device_desc temp_desc;
+	struct i3c_device_desc *desc;
+	struct i3c_device_id id;
+	const struct i3c_driver_config *config = dev->config;
+	int ret;
+
+	temp_desc.bus = dev;
+	temp_desc.dynamic_addr = dynamic_addr;
+	temp_desc.bcr = bcr;
+	temp_desc.dcr = dcr;
+	/* attach it first with a temporary value so we can at least get the pid */
+	ret = i3c_attach_i3c_device(&temp_desc);
+	if (ret != 0) {
+		return ret;
+	}
+
+	/* First try to look up if this is a known device in the list by PID */
+	ret = i3c_ccc_do_getpid(&temp_desc, &getpid);
+	if (ret != 0) {
+		return ret;
+	}
+
+	id.pid = sys_get_be48(getpid.pid);
+
+	/* try to see if we already have a device statically allocated */
+	desc = i3c_dev_list_find(&config->dev_list, &id);
+	if (!desc) {
+		/* device was not found so allocate a descriptor */
+		desc = i3c_device_desc_alloc();
+		if (!desc) {
+			return -ENOMEM;
+		}
+		desc->pid = id.pid;
+		temp_desc.static_addr = (uint16_t)static_addr;
+	}
+	desc->dynamic_addr = dynamic_addr;
+	desc->bcr = bcr;
+	desc->dcr = dcr;
+
+	/* Detach that temporary device */
+	ret = i3c_detach_i3c_device(&temp_desc);
+	if (ret != 0) {
+		return ret;
+	}
+	ret = i3c_attach_i3c_device(desc);
+	if (ret != 0) {
+		return ret;
+	}
+
+	/* Skip reading BCR and DCR as they came from DEFTGTS */
+	ret = i3c_device_adv_info_get(desc);
+
+	return ret;
+}
+
+int i3c_sec_i2c_attach(const struct device *dev, uint8_t static_addr, uint8_t lvr)
+{
+	struct i3c_i2c_device_desc *i2c_desc;
+	int ret;
+
+	/* try to see if we already have a device statically allocated */
+	i2c_desc = i3c_dev_list_i2c_addr_find(dev, (uint16_t)static_addr);
+	if (!i2c_desc) {
+		/* device was not found so allocate a descriptor */
+		i2c_desc = i3c_i2c_device_desc_alloc();
+		if (!i2c_desc) {
+			return -ENOMEM;
+		}
+		*(const struct device **)&i2c_desc->bus = dev;
+		i2c_desc->addr = (uint16_t)static_addr;
+		i2c_desc->lvr = lvr;
+	}
+
+	ret = i3c_attach_i2c_device(i2c_desc);
+	return ret;
+}
+
+static void i3c_sec_bus_reset(const struct device *dev)
+{
+	struct i3c_device_desc *i3c_desc;
+	struct i3c_i2c_device_desc *i3c_i2c_desc;
+
+	I3C_BUS_FOR_EACH_I3CDEV(dev, i3c_desc) {
+		i3c_detach_i3c_device(i3c_desc);
+	}
+
+	I3C_BUS_FOR_EACH_I2CDEV(dev, i3c_i2c_desc) {
+		i3c_detach_i2c_device(i3c_i2c_desc);
+	}
+}
+#ifdef CONFIG_I3C_USE_IBI
+/* call this from a workq after the interrupt from a controller */
+void i3c_sec_handoffed(struct k_work *work)
+{
+	struct i3c_ibi_work *ibi_node = CONTAINER_OF(work, struct i3c_ibi_work, work);
+	const struct device *dev = ibi_node->controller;
+	struct i3c_driver_data *data = (struct i3c_driver_data *)dev->data;
+	struct i3c_ccc_deftgts *deftgts = data->deftgts;
+	struct i3c_config_target config_target;
+	uint8_t n, cur_dyn_addr;
+	int ret;
+
+	if (!deftgts) {
+		LOG_ERR("Did not receive DEFTGTS before Handoff");
+		return;
+	}
+
+	if (!data->deftgts_refreshed) {
+		LOG_DBG("Already processed DEFTGTS from previous handoff");
+		return;
+	}
+
+	/* Forget all devices as another controller made changes */
+	i3c_sec_bus_reset(dev);
+
+	/*
+	 * Retrieve the active controller information
+	 */
+	ret = i3c_config_get_target(dev, &config_target);
+	if (ret != 0) {
+		LOG_ERR("Failed to retrieve active controller info");
+		return;
+	}
+
+	cur_dyn_addr = config_target.dynamic_addr;
+
+	/* Attach the previous AC */
+	ret = i3c_sec_get_basic_info(
+		dev, deftgts->active_controller.addr, deftgts->active_controller.static_addr,
+		deftgts->active_controller.bcr, deftgts->active_controller.dcr);
+
+	/* Attach all Targets */
+	for (n = 0; n < deftgts->count; n++) {
+		if (deftgts->targets[n].addr != 0) {
+			/* Must be an I3C device and skip itself */
+			if (deftgts->targets[n].addr != cur_dyn_addr) {
+				ret = i3c_sec_get_basic_info(dev, deftgts->targets[n].addr,
+							     deftgts->targets[n].static_addr,
+							     deftgts->targets[n].bcr,
+							     deftgts->targets[n].dcr);
+			}
+		} else {
+			/* Must be an I2C device */
+			ret = i3c_sec_i2c_attach(dev, deftgts->targets[n].static_addr,
+						 deftgts->targets[n].lvr);
+		}
+	}
+
+	/* Set false, so the next handoff doesn't retrigger regathering info */
+	data->deftgts_refreshed = false;
+}
+#endif /* CONFIG_I3C_USE_IBI */
+#endif /* CONFIG_I3C_TARGET */
 
 int i3c_dev_list_daa_addr_helper(struct i3c_addr_slots *addr_slots,
-				 const struct i3c_dev_list *dev_list,
-				 uint64_t pid, bool must_match,
-				 bool assigned_okay,
-				 struct i3c_device_desc **target,
-				 uint8_t *addr)
+				 const struct i3c_dev_list *dev_list, uint64_t pid, bool must_match,
+				 bool assigned_okay, struct i3c_device_desc **target, uint8_t *addr)
 {
 	struct i3c_device_desc *desc;
 	const uint16_t vendor_id = (uint16_t)(pid >> 32);
@@ -388,6 +559,10 @@ int i3c_dev_list_daa_addr_helper(struct i3c_addr_slots *addr_slots,
 	const struct i3c_device_id i3c_id = I3C_DEVICE_ID(pid);
 
 	desc = i3c_dev_list_find(dev_list, &i3c_id);
+	/* If a device was not found, try to allocate a descriptor */
+	if (desc == NULL) {
+		desc = i3c_device_desc_alloc();
+	}
 	if (must_match && (desc == NULL)) {
 		/*
 		 * No device descriptor matching incoming PID and
@@ -395,8 +570,7 @@ int i3c_dev_list_daa_addr_helper(struct i3c_addr_slots *addr_slots,
 		 */
 		ret = -ENODEV;
 
-		LOG_DBG("PID 0x%04x%08x is not in registered device list",
-			vendor_id, part_no);
+		LOG_DBG("PID 0x%04x%08x is not in registered device list", vendor_id, part_no);
 
 		goto out;
 	}
@@ -449,7 +623,125 @@ int i3c_dev_list_daa_addr_helper(struct i3c_addr_slots *addr_slots,
 err:
 	return ret;
 }
+#ifdef CONFIG_I3C_TARGET
+uint8_t i3c_odd_parity(uint8_t p)
+{
+	p ^= p >> 4;
+	p &= 0xf;
+	return (0x9669 >> p) & 1;
+}
+
+int i3c_device_controller_handoff(const struct i3c_device_desc *target, bool requested)
+{
+	int ret;
+	union i3c_ccc_getstatus status = {0};
+	struct i3c_ccc_events i3c_events;
+	struct i3c_ccc_address handoff_address;
+
+	/*
+	 * If the Active Controller intends to pass the Controller Role to a selected Secondary
+	 * Controller that did not send a Controller Role Request, then the Active Controller should
+	 * verify that the selected Secondary Controller is active and ready to respond to
+	 * additional commands
+	 */
+	if (!requested) {
+		ret = i3c_ccc_do_getstatus_fmt1(target, &status);
+		if (ret != 0) {
+			return ret;
+		}
+
+		if (I3C_CCC_GETSTATUS_ACTIVITY_MODE(status.fmt1.status) ==
+		    I3C_CCC_GETSTATUS_ACTIVITY_MODE_NCH) {
+			return -EBUSY;
+		}
+	}
+
+	/*
+	 * The Active Controller needs to disable Hot-Joins, Target Interrupt Requests, and other
+	 * Bus events that could interfere with the Handoff, then it sends the appropriate
+	 * Broadcast to disable those events before the Handoff. Once the Handoff is complete, the
+	 * new Active Controller should re-enable events that are disabled in this step.
+	 */
+	i3c_events.events = I3C_CCC_EVT_ALL;
+	ret = i3c_ccc_do_events_all_set(target->bus, false, &i3c_events);
+	if (ret != 0) {
+		return ret;
+	}
+
+	/** TODO: reconfigure MLANE if needed */
+
+	/*
+	 * If the Active Controller knows that the selected Secondary Controller must be put into a
+	 * different Activity State before Handoff, then the Active Controller shall send the
+	 * appropriate Broadcast or Direct CCCs to put the Bus (or selected Devices) into a
+	 * different Activity State
+	 */
+	if (target->crhdly1 & I3C_CCC_GETMXDS_CRDHLY1_SET_BUS_ACT_STATE) {
+		ret = i3c_ccc_do_entas(
+			target, I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE(target->crhdly1));
+		if (ret != 0) {
+			return ret;
+		}
+	}
+
+	if ((target->getcaps.getcap3 & I3C_CCC_GETCAPS3_GETSTATUS_DEFINING_BYTE_SUPPORT) &&
+	    (target->crcaps.crcaps2 & I3C_CCC_GETCAPS_CRCAPS2_DEEP_SLEEP_CAPABLE)) {
+		ret = i3c_ccc_do_getstatus_fmt2(target, &status, GETSTATUS_FORMAT_2_PRECR);
+		if (ret != 0) {
+			return ret;
+		}
 
+		/*
+		 * If the Active Controller determines that the indicated Secondary Controller has
+		 * been in a “deep sleep” state and may need to be re-synchronized with the most
+		 * current list of I3C Targets and Group Addresses, then the Active Controller
+		 * should send CCC DEFTGTS and DEFGRPA
+		 */
+		if (status.fmt2.precr & I3C_CCC_GETSTATUS_PRECR_DEEP_SLEEP_DETECTED) {
+			ret = i3c_bus_deftgts(target->bus);
+			if (ret != 0) {
+				return ret;
+			}
+			/* TODO: broadcast DEFGRPA when group address support comes */
+
+			/* Check CRCAPS if the device needs additional time to process */
+			if (target->crcaps.crcaps2 &
+			    I3C_CCC_GETCAPS_CRCAPS2_DELAYED_CONTROLLER_HANDOFF) {
+				/*
+				 * Afterwards, the Active Controller should poll the Secondary
+				 * Controller to ensure that it has successfully processed this data
+				 * and indicates that it is ready to accept the Controller Role
+				 */
+				do {
+					ret = i3c_ccc_do_getstatus_fmt2(target, &status,
+									GETSTATUS_FORMAT_2_PRECR);
+					if (ret != 0) {
+						return ret;
+					}
+				} while (!(status.fmt2.precr &
+					   I3C_CCC_GETSTATUS_PRECR_HANDOFF_DELAY_NACK));
+			}
+		}
+	}
+
+	/*
+	 * After the Active Controller has prepared for Handoff, the Active Controller shall
+	 * then issue a GETACCCR CCC
+	 */
+	ret = i3c_ccc_do_getacccr(target, &handoff_address);
+	if (ret != 0) {
+		return ret;
+	}
+
+	/* Verify Odd Parity and Correct Dynamic Address Reply */
+	if ((i3c_odd_parity(handoff_address.addr >> 1) != (handoff_address.addr & BIT(0))) ||
+	    (handoff_address.addr >> 1 != target->dynamic_addr)) {
+		return -EIO;
+	}
+
+	return ret;
+}
+#endif /* CONFIG_I3C_TARGET */
 int i3c_device_basic_info_get(struct i3c_device_desc *target)
 {
 	int ret;
@@ -485,28 +777,37 @@ int i3c_device_adv_info_get(struct i3c_device_desc *target)
 	/* GETMRL */
 	if (i3c_ccc_do_getmrl(target, &mrl) != 0) {
 		/* GETMRL may be optionally supported if no settable limit */
-		LOG_DBG("No settable limit for GETMRL");
+		LOG_DBG("%s: No settable limit for GETMRL", target->dev->name);
 	}
 
 	/* GETMWL */
 	if (i3c_ccc_do_getmwl(target, &mwl) != 0) {
 		/* GETMWL may be optionally supported if no settable limit */
-		LOG_DBG("No settable limit for GETMWL");
+		LOG_DBG("%s: No settable limit for GETMWL", target->dev->name);
 	}
 
 	/* GETCAPS */
-	ret = i3c_ccc_do_getcaps_fmt1(target, &caps);
-	/*
-	 * GETCAPS (GETHDRCAP) is required to be supported for I3C v1.0 targets that support HDR
-	 * modes and required if the Target's I3C version is v1.1 or later, but which the version it
-	 * supports it can't be known ahead of time. So if the BCR bit for Advanced capabilities is
-	 * set, then it is expected for GETCAPS to always be supported. Otherwise, then it's a I3C
-	 * v1.0 device without any HDR modes so do not treat as an error if no valid response.
-	 */
-	if ((ret != 0) && (target->bcr & I3C_BCR_ADV_CAPABILITIES)) {
-		return ret;
-	} else {
-		ret = 0;
+	if (((target->flags & I3C_V1P0_SUPPORT) && (target->bcr & I3C_BCR_ADV_CAPABILITIES)) ||
+	    (!(target->flags & I3C_V1P0_SUPPORT))) {
+		/*
+		 * GETCAPS (GETHDRCAP) is required to be supported for I3C v1.0 targets that support
+		 * HDR modes and required if the Target's I3C version is v1.1 or later.
+		 * It is also possible for this function to be called on an 'unknown' device such as
+		 * from a secondary controller gathering info about a target it found about through
+		 * DEFTGTS, and it can't be known ahead of time if it is a v1.0 or v1.1 device.
+		 */
+		if (i3c_ccc_do_getcaps_fmt1(target, &caps) != 0) {
+			LOG_DBG("%s: GETCAPS not received", target->dev->name);
+		}
+	}
+
+	/* CRCAPS */
+	if ((target->getcaps.getcap3 & I3C_CCC_GETCAPS3_GETCAPS_DEFINING_BYTE_SUPPORT) &&
+	    (i3c_device_is_controller_capable(target))) {
+		ret = i3c_ccc_do_getcaps_fmt2(target, &caps, GETCAPS_FORMAT_2_CRCAPS);
+		if (ret != 0) {
+			return ret;
+		}
 	}
 
 	/* GETMXDS */
@@ -515,14 +816,18 @@ int i3c_device_adv_info_get(struct i3c_device_desc *target)
 		if (ret != 0) {
 			return ret;
 		}
-	}
 
-	/* Some values may not have been read, but set them back to 0 */
-	memcpy(&target->getcaps, &caps, sizeof(target->getcaps));
+		/* Get CRHDLY if supported */
+		if ((target->data_speed.maxwr & I3C_CCC_GETMXDS_MAXWR_DEFINING_BYTE_SUPPORT) &&
+		    (i3c_device_is_controller_capable(target))) {
+			ret = i3c_ccc_do_getmxds_fmt3(target, &mxds, GETMXDS_FORMAT_3_CRHDLY);
+			if (ret != 0) {
+				return ret;
+			}
 
-	target->data_speed.maxrd = mxds.fmt2.maxrd;
-	target->data_speed.maxwr = mxds.fmt2.maxwr;
-	target->data_speed.max_read_turnaround = sys_get_le24(mxds.fmt2.maxrdturn);
+			target->crhdly1 = mxds.fmt3.crhdly1;
+		}
+	}
 
 	target->data_length.mrl = mrl.len;
 	target->data_length.mwl = mwl.len;
@@ -540,8 +845,7 @@ int i3c_device_adv_info_get(struct i3c_device_desc *target)
  *
  * @retval 0 if successful.
  */
-static int i3c_bus_setdasa(const struct device *dev,
-			   const struct i3c_dev_list *dev_list,
+static int i3c_bus_setdasa(const struct device *dev, const struct i3c_dev_list *dev_list,
 			   bool *need_daa, bool *need_aasa)
 {
 	int i, ret;
@@ -569,8 +873,9 @@ static int i3c_bus_setdasa(const struct device *dev,
 		 * address as its static address if a different dynamic address
 		 * is not requested
 		 */
-		if ((desc->supports_setaasa) && ((desc->init_dynamic_addr == 0) ||
-					       desc->init_dynamic_addr == desc->static_addr)) {
+		if ((desc->flags & I3C_SUPPORTS_SETAASA) &&
+		    ((desc->init_dynamic_addr == 0) ||
+		     desc->init_dynamic_addr == desc->static_addr)) {
 			*need_aasa = true;
 			continue;
 		}
@@ -582,9 +887,9 @@ static int i3c_bus_setdasa(const struct device *dev,
 		 * if configured
 		 */
 		if ((desc->init_dynamic_addr != 0) &&
-			(desc->init_dynamic_addr != desc->static_addr)) {
+		    (desc->init_dynamic_addr != desc->static_addr)) {
 			if (!i3c_addr_slots_is_free(&bus_data->attached_dev.addr_slots,
-				desc->init_dynamic_addr)) {
+						    desc->init_dynamic_addr)) {
 				if (i3c_detach_i3c_device(desc) != 0) {
 					LOG_ERR("Failed to detach %s", desc->dev->name);
 				}
@@ -596,8 +901,9 @@ static int i3c_bus_setdasa(const struct device *dev,
 		 * Note that the 7-bit address needs to start at bit 1
 		 * (aka left-justified). So shift left by 1;
 		 */
-		dyn_addr.addr = (desc->init_dynamic_addr ?
-					desc->init_dynamic_addr : desc->static_addr) << 1;
+		dyn_addr.addr =
+			(desc->init_dynamic_addr ? desc->init_dynamic_addr : desc->static_addr)
+			<< 1;
 
 		ret = i3c_ccc_do_setdasa(desc, dyn_addr);
 		if (ret == 0) {
@@ -612,8 +918,7 @@ static int i3c_bus_setdasa(const struct device *dev,
 			if (i3c_detach_i3c_device(desc) != 0) {
 				LOG_ERR("Failed to detach %s (%d)", desc->dev->name, ret);
 			}
-			LOG_ERR("SETDASA error on address 0x%x (%d)",
-				desc->static_addr, ret);
+			LOG_ERR("SETDASA error on address 0x%x (%d)", desc->static_addr, ret);
 		}
 	}
 
@@ -632,7 +937,7 @@ bool i3c_bus_has_sec_controller(const struct device *dev)
 
 	return false;
 }
-
+#ifdef CONFIG_I3C_TARGET
 int i3c_bus_deftgts(const struct device *dev)
 {
 	struct i3c_driver_data *data = (struct i3c_driver_data *)dev->data;
@@ -644,9 +949,8 @@ int i3c_bus_deftgts(const struct device *dev)
 	uint8_t n = 0;
 	size_t num_of_targets = sys_slist_len(&data->attached_dev.devices.i3c) +
 				sys_slist_len(&data->attached_dev.devices.i2c);
-	size_t data_len = sizeof(uint8_t) +
-				   sizeof(struct i3c_ccc_deftgts_active_controller) +
-				   (num_of_targets * sizeof(struct i3c_ccc_deftgts_target));
+	size_t data_len = sizeof(uint8_t) + sizeof(struct i3c_ccc_deftgts_active_controller) +
+			  (num_of_targets * sizeof(struct i3c_ccc_deftgts_target));
 
 	/*
 	 * Retrieve the active controller information
@@ -706,7 +1010,7 @@ int i3c_bus_deftgts(const struct device *dev)
 
 	return ret;
 }
-
+#endif /* CONFIG_I3C_TARGET */
 int i3c_bus_init(const struct device *dev, const struct i3c_dev_list *dev_list)
 {
 	int i, ret = 0;
@@ -768,13 +1072,16 @@ int i3c_bus_init(const struct device *dev, const struct i3c_dev_list *dev_list)
 	if (need_aasa) {
 		ret = i3c_ccc_do_setaasa_all(dev);
 		if (ret != 0) {
+			LOG_ERR("failed to perform setaasa");
+		} else {
 			for (i = 0; i < dev_list->num_i3c; i++) {
 				struct i3c_device_desc *desc = &dev_list->i3c[i];
 				/*
 				 * Only set for devices that support SETAASA and do not
 				 * request a different dynamic address than its SA
 				 */
-				if ((desc->supports_setaasa) && (desc->static_addr != 0) &&
+				if ((desc->flags & I3C_SUPPORTS_SETAASA) &&
+				    (desc->static_addr != 0) &&
 				    ((desc->init_dynamic_addr == 0) ||
 				     desc->init_dynamic_addr == desc->static_addr)) {
 					desc->dynamic_addr = desc->static_addr;
@@ -824,28 +1131,24 @@ int i3c_bus_init(const struct device *dev, const struct i3c_dev_list *dev_list)
 		ret = (desc->static_addr == 0) ? i3c_device_adv_info_get(desc)
 					       : i3c_device_info_get(desc);
 		if (ret != 0) {
-			LOG_ERR("Error getting device info for 0x%02x",
-				desc->static_addr);
+			LOG_ERR("Error getting device info for 0x%02x", desc->static_addr);
 		} else {
 			LOG_DBG("Target 0x%02x, BCR 0x%02x, DCR 0x%02x, MRL %d, MWL %d, IBI %d",
-				desc->dynamic_addr, desc->bcr, desc->dcr,
-				desc->data_length.mrl, desc->data_length.mwl,
-				desc->data_length.max_ibi);
+				desc->dynamic_addr, desc->bcr, desc->dcr, desc->data_length.mrl,
+				desc->data_length.mwl, desc->data_length.max_ibi);
 		}
 	}
-
+#ifdef CONFIG_I3C_TARGET
 	if (i3c_bus_has_sec_controller(dev)) {
 		ret = i3c_bus_deftgts(dev);
 		if (ret != 0) {
 			LOG_ERR("Error sending DEFTGTS");
 		}
 	}
-
+#endif /* CONFIG_I3C_TARGET */
 	/*
 	 * Only re-enable Hot-Join from targets.
 	 * Target interrupts will be enabled when IBI is enabled.
-	 * And transferring controller role is not supported so not need to
-	 * enable the event.
 	 */
 	i3c_events.events = I3C_CCC_EVT_HJ;
 	ret = i3c_ccc_do_events_all_set(dev, true, &i3c_events);
diff --git a/drivers/i3c/i3c_dw.c b/drivers/i3c/i3c_dw.c
new file mode 100644
index 00000000000..4d13ec2e791
--- /dev/null
+++ b/drivers/i3c/i3c_dw.c
@@ -0,0 +1,2512 @@
+/*
+ * Copyright (C) 2020 Samsung Electronics Co., Ltd.
+ * Copyright (C) 2023 Meta Platforms
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/i3c.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/pm/device.h>
+#include <zephyr/sys/util.h>
+#include <assert.h>
+
+#if defined(CONFIG_PINCTRL)
+#include <zephyr/drivers/pinctrl.h>
+#endif
+
+#define NANO_SEC        1000000000ULL
+#define BYTES_PER_DWORD 4
+
+LOG_MODULE_REGISTER(i3c_dw, CONFIG_I3C_DW_LOG_LEVEL);
+
+#define DEVICE_CTRL                0x0
+#define DEV_CTRL_ENABLE            BIT(31)
+#define DEV_CTRL_RESUME            BIT(30)
+#define DEV_CTRL_HOT_JOIN_NACK     BIT(8)
+#define DEV_CTRL_I2C_SLAVE_PRESENT BIT(7)
+#define DEV_CTRL_IBA_INCLUDE       BIT(0)
+
+#define DEVICE_ADDR                    0x4
+#define DEVICE_ADDR_DYNAMIC_ADDR_VALID BIT(31)
+#define DEVICE_ADDR_DYNAMIC(x)         (((x) << 16) & GENMASK(22, 16))
+#define DEVICE_ADDR_STATIC_ADDR_VALID  BIT(15)
+#define DEVICE_ADDR_STATIC_MASK        GENMASK(6, 0)
+#define DEVICE_ADDR_STATIC(x)          ((x) & DEVICE_ADDR_STATIC_MASK)
+
+#define HW_CAPABILITY                         0x8
+#define HW_CAPABILITY_SLV_IBI_CAP             BIT(19)
+#define HW_CAPABILITY_SLV_HJ_CAP              BIT(18)
+#define HW_CAPABILITY_HDR_TS_EN               BIT(4)
+#define HW_CAPABILITY_HDR_DDR_EN              BIT(3)
+#define HW_CAPABILITY_DEVICE_ROLE_CONFIG_MASK GENMASK(2, 0)
+
+#define COMMAND_QUEUE_PORT         0xc
+#define COMMAND_PORT_TOC           BIT(30)
+#define COMMAND_PORT_READ_TRANSFER BIT(28)
+#define COMMAND_PORT_SDAP          BIT(27)
+#define COMMAND_PORT_ROC           BIT(26)
+#define COMMAND_PORT_DBP           BIT(25)
+#define COMMAND_PORT_SPEED(x)      (((x) << 21) & GENMASK(23, 21))
+#define COMMAND_PORT_SPEED_I2C_FM  0
+#define COMMAND_PORT_SPEED_I2C_FMP 1
+#define COMMAND_PORT_SPEED_I3C_DDR 6
+#define COMMAND_PORT_SPEED_I3C_TS  7
+#define COMMAND_PORT_DEV_INDEX(x)  (((x) << 16) & GENMASK(20, 16))
+#define COMMAND_PORT_CP            BIT(15)
+#define COMMAND_PORT_CMD(x)        (((x) << 7) & GENMASK(14, 7))
+#define COMMAND_PORT_TID(x)        (((x) << 3) & GENMASK(6, 3))
+
+#define COMMAND_PORT_ARG_DATA_LEN(x)  (((x) << 16) & GENMASK(31, 16))
+#define COMMAND_PORT_ARG_DB(x)        (((x) << 8) & GENMASK(15, 8))
+#define COMMAND_PORT_ARG_DATA_LEN_MAX 65536
+#define COMMAND_PORT_TRANSFER_ARG     0x01
+
+#define COMMAND_PORT_SDA_DATA_BYTE_3(x) (((x) << 24) & GENMASK(31, 24))
+#define COMMAND_PORT_SDA_DATA_BYTE_2(x) (((x) << 16) & GENMASK(23, 16))
+#define COMMAND_PORT_SDA_DATA_BYTE_1(x) (((x) << 8) & GENMASK(15, 8))
+#define COMMAND_PORT_SDA_BYTE_STRB_3    BIT(5)
+#define COMMAND_PORT_SDA_BYTE_STRB_2    BIT(4)
+#define COMMAND_PORT_SDA_BYTE_STRB_1    BIT(3)
+#define COMMAND_PORT_SHORT_DATA_ARG     0x02
+
+#define COMMAND_PORT_DEV_COUNT(x)   (((x) << 21) & GENMASK(25, 21))
+#define COMMAND_PORT_ADDR_ASSGN_CMD 0x03
+
+#define RESPONSE_QUEUE_PORT            0x10
+#define RESPONSE_PORT_ERR_STATUS(x)    (((x) & GENMASK(31, 28)) >> 28)
+#define RESPONSE_NO_ERROR              0
+#define RESPONSE_ERROR_CRC             1
+#define RESPONSE_ERROR_PARITY          2
+#define RESPONSE_ERROR_FRAME           3
+#define RESPONSE_ERROR_IBA_NACK        4
+#define RESPONSE_ERROR_ADDRESS_NACK    5
+#define RESPONSE_ERROR_OVER_UNDER_FLOW 6
+#define RESPONSE_ERROR_TRANSF_ABORT    8
+#define RESPONSE_ERROR_I2C_W_NACK_ERR  9
+#define RESPONSE_PORT_TID(x)           (((x) & GENMASK(27, 24)) >> 24)
+#define RESPONSE_PORT_DATA_LEN(x)      ((x) & GENMASK(15, 0))
+
+#define RX_TX_DATA_PORT              0x14
+#define IBI_QUEUE_STATUS             0x18
+#define IBI_QUEUE_STATUS_IBI_STS(x)  (((x) & GENMASK(31, 28)) >> 28)
+#define IBI_QUEUE_STATUS_IBI_ID(x)   (((x) & GENMASK(15, 8)) >> 8)
+#define IBI_QUEUE_STATUS_DATA_LEN(x) ((x) & GENMASK(7, 0))
+#define IBI_QUEUE_IBI_ADDR(x)        (IBI_QUEUE_STATUS_IBI_ID(x) >> 1)
+#define IBI_QUEUE_IBI_RNW(x)         (IBI_QUEUE_STATUS_IBI_ID(x) & BIT(0))
+#define IBI_TYPE_MR(x) \
+	((IBI_QUEUE_IBI_ADDR(x) != I3C_HOT_JOIN_ADDR) && !IBI_QUEUE_IBI_RNW(x))
+#define IBI_TYPE_HJ(x) \
+	((IBI_QUEUE_IBI_ADDR(x) == I3C_HOT_JOIN_ADDR) && !IBI_QUEUE_IBI_RNW(x))
+#define IBI_TYPE_SIRQ(x) \
+	((IBI_QUEUE_IBI_ADDR(x) != I3C_HOT_JOIN_ADDR) && IBI_QUEUE_IBI_RNW(x))
+
+#define QUEUE_THLD_CTRL               0x1c
+#define QUEUE_THLD_CTRL_IBI_STS_MASK  GENMASK(31, 24)
+#define QUEUE_THLD_CTRL_RESP_BUF_MASK GENMASK(15, 8)
+#define QUEUE_THLD_CTRL_RESP_BUF(x)   (((x) - 1) << 8)
+
+#define DATA_BUFFER_THLD_CTRL        0x20
+#define DATA_BUFFER_THLD_CTRL_RX_BUF GENMASK(11, 8)
+
+#define IBI_QUEUE_CTRL     0x24
+#define IBI_MR_REQ_REJECT  0x2C
+#define IBI_SIR_REQ_REJECT 0x30
+#define IBI_SIR_REQ_ID(x)  ((((x) & GENMASK(6, 5)) >> 5) + ((x) & GENMASK(4, 0)))
+#define IBI_REQ_REJECT_ALL GENMASK(31, 0)
+
+#define RESET_CTRL            0x34
+#define RESET_CTRL_IBI_QUEUE  BIT(5)
+#define RESET_CTRL_RX_FIFO    BIT(4)
+#define RESET_CTRL_TX_FIFO    BIT(3)
+#define RESET_CTRL_RESP_QUEUE BIT(2)
+#define RESET_CTRL_CMD_QUEUE  BIT(1)
+#define RESET_CTRL_SOFT       BIT(0)
+#define RESET_CTRL_ALL                                                                             \
+	(RESET_CTRL_IBI_QUEUE | RESET_CTRL_RX_FIFO | RESET_CTRL_TX_FIFO | RESET_CTRL_RESP_QUEUE |  \
+	 RESET_CTRL_CMD_QUEUE | RESET_CTRL_SOFT)
+
+#define SLV_EVENT_STATUS        0x38
+#define SLV_EVENT_STATUS_HJ_EN  BIT(3)
+#define SLV_EVENT_STATUS_MR_EN  BIT(1)
+#define SLV_EVENT_STATUS_SIR_EN BIT(0)
+
+#define INTR_STATUS               0x3c
+#define INTR_STATUS_EN            0x40
+#define INTR_SIGNAL_EN            0x44
+#define INTR_FORCE                0x48
+#define INTR_BUSOWNER_UPDATE_STAT BIT(13)
+#define INTR_IBI_UPDATED_STAT     BIT(12)
+#define INTR_READ_REQ_RECV_STAT   BIT(11)
+#define INTR_DEFSLV_STAT          BIT(10)
+#define INTR_TRANSFER_ERR_STAT    BIT(9)
+#define INTR_DYN_ADDR_ASSGN_STAT  BIT(8)
+#define INTR_CCC_UPDATED_STAT     BIT(6)
+#define INTR_TRANSFER_ABORT_STAT  BIT(5)
+#define INTR_RESP_READY_STAT      BIT(4)
+#define INTR_CMD_QUEUE_READY_STAT BIT(3)
+#define INTR_IBI_THLD_STAT        BIT(2)
+#define INTR_RX_THLD_STAT         BIT(1)
+#define INTR_TX_THLD_STAT         BIT(0)
+#define INTR_ALL                                                                                   \
+	(INTR_BUSOWNER_UPDATE_STAT | INTR_IBI_UPDATED_STAT | INTR_READ_REQ_RECV_STAT |             \
+	 INTR_DEFSLV_STAT | INTR_TRANSFER_ERR_STAT | INTR_DYN_ADDR_ASSGN_STAT |                    \
+	 INTR_CCC_UPDATED_STAT | INTR_TRANSFER_ABORT_STAT | INTR_RESP_READY_STAT |                 \
+	 INTR_CMD_QUEUE_READY_STAT | INTR_IBI_THLD_STAT | INTR_TX_THLD_STAT | INTR_RX_THLD_STAT)
+
+#ifdef CONFIG_I3C_USE_IBI
+#define INTR_MASTER_MASK (INTR_TRANSFER_ERR_STAT | INTR_RESP_READY_STAT | INTR_IBI_THLD_STAT)
+#else
+#define INTR_MASTER_MASK (INTR_TRANSFER_ERR_STAT | INTR_RESP_READY_STAT)
+#endif
+#define INTR_SLAVE_MASK                                                                            \
+	(INTR_TRANSFER_ERR_STAT | INTR_IBI_UPDATED_STAT | INTR_READ_REQ_RECV_STAT |                \
+	 INTR_DYN_ADDR_ASSGN_STAT | INTR_RESP_READY_STAT)
+
+#define QUEUE_STATUS_LEVEL             0x4c
+#define QUEUE_STATUS_IBI_STATUS_CNT(x) (((x) & GENMASK(28, 24)) >> 24)
+#define QUEUE_STATUS_IBI_BUF_BLR(x)    (((x) & GENMASK(23, 16)) >> 16)
+#define QUEUE_STATUS_LEVEL_RESP(x)     (((x) & GENMASK(15, 8)) >> 8)
+#define QUEUE_STATUS_LEVEL_CMD(x)      ((x) & GENMASK(7, 0))
+
+#define DATA_BUFFER_STATUS_LEVEL       0x50
+#define DATA_BUFFER_STATUS_LEVEL_RX(x) (((x) & GENMASK(23, 16)) >> 16)
+#define DATA_BUFFER_STATUS_LEVEL_TX(x) ((x) & GENMASK(7, 0))
+
+#define PRESENT_STATE                0x54
+#define PRESENT_STATE_CURRENT_MASTER BIT(2)
+
+#define CCC_DEVICE_STATUS          0x58
+#define DEVICE_ADDR_TABLE_POINTER  0x5c
+#define DEVICE_ADDR_TABLE_DEPTH(x) (((x) & GENMASK(31, 16)) >> 16)
+#define DEVICE_ADDR_TABLE_ADDR(x)  ((x) & GENMASK(15, 0))
+
+#define DEV_CHAR_TABLE_POINTER      0x60
+#define DEVICE_CHAR_TABLE_ADDR(x)   ((x) & GENMASK(11, 0))
+#define VENDOR_SPECIFIC_REG_POINTER 0x6c
+
+#define SLV_MIPI_ID_VALUE                      0x70
+#define SLV_MIPI_ID_VALUE_SLV_MIPI_MFG_ID_MASK GENMASK(15, 1)
+#define SLV_MIPI_ID_VALUE_SLV_MIPI_MFG_ID(x)   ((x) & SLV_MIPI_ID_VALUE_SLV_MIPI_MFG_ID_MASK)
+#define SLV_MIPI_ID_VALUE_SLV_PROV_ID_SEL      BIT(0)
+
+#define SLV_PID_VALUE 0x74
+
+#define SLV_CHAR_CTRL                      0x78
+#define SLV_CHAR_CTRL_MAX_DATA_SPEED_LIMIT BIT(0)
+#define SLV_CHAR_CTRL_IBI_REQUEST_CAPABLE  BIT(1)
+#define SLV_CHAR_CTRL_IBI_PAYLOAD          BIT(2)
+#define SLV_CHAR_CTRL_BCR_MASK             GENMASK(7, 0)
+#define SLV_CHAR_CTRL_BCR(x)               ((x) & SLV_CHAR_CTRL_BCR_MASK)
+#define SLV_CHAR_CTRL_DCR_MASK             GENMASK(15, 8)
+#define SLV_CHAR_CTRL_DCR(x)               (((x) & SLV_CHAR_CTRL_DCR_MASK) >> 8)
+#define SLV_CHAR_CTRL_HDR_CAP_MASK         GENMASK(23, 16)
+#define SLV_CHAR_CTRL_HDR_CAP(x)           (((x) & SLV_CHAR_CTRL_HDR_CAP_MASK) >> 16)
+
+#define SLV_MAX_LEN        0x7c
+#define SLV_MAX_LEN_MRL(x) (((x) & GENMASK(31, 16)) >> 16)
+#define SLV_MAX_LEN_MWL(x) ((x) & GENMASK(15, 0))
+
+#define MAX_READ_TURNAROUND                     0x80
+#define MAX_READ_TURNAROUND_MXDX_MAX_RD_TURN(x) ((x) & GENMASK(23, 0))
+
+#define MAX_DATA_SPEED   0x84
+#define SLV_DEBUG_STATUS 0x88
+
+#define SLV_INTR_REQ                        0x8c
+#define SLV_INTR_REQ_SIR_DATA_LENGTH(x)     (((x) << 16) & GENMASK(23, 16))
+#define SLV_INTR_REQ_MDB(x)                 (((x) << 8) & GENMASK(15, 8))
+#define SLV_INTR_REQ_IBI_STS(x)             (((x) & GENMASK(9, 8)) >> 8)
+#define SLV_INTR_REQ_IBI_STS_IBI_ACCEPT     0x01
+#define SLV_INTR_REQ_IBI_STS_IBI_NO_ATTEMPT 0x03
+#define SLV_INTR_REQ_TS                     BIT(4)
+#define SLV_INTR_REQ_MR                     BIT(3)
+#define SLV_INTR_REQ_SIR_CTRL(x)            (((x) & GENMASK(2, 1)) >> 1)
+#define SLV_INTR_REQ_SIR                    BIT(0)
+
+#define SLV_SIR_DATA          0x94
+#define SLV_SIR_DATA_BYTE3(x) (((x) << 24) & GENMASK(31, 24))
+#define SLV_SIR_DATA_BYTE2(x) (((x) << 16) & GENMASK(23, 16))
+#define SLV_SIR_DATA_BYTE1(x) (((x) << 8) & GENMASK(15, 8))
+#define SLV_SIR_DATA_BYTE0(x) ((x) & GENMASK(7, 0))
+
+#define SLV_IBI_RESP                         0x98
+#define SLV_IBI_RESP_DATA_LENGTH(x)          (((x) & GENMASK(23, 8)) >> 8)
+#define SLV_IBI_RESP_IBI_STS(x)              ((x) & GENMASK(1, 0))
+#define SLV_IBI_RESP_IBI_STS_ACK             0x01
+#define SLV_IBI_RESP_IBI_STS_EARLY_TERMINATE 0x02
+#define SLV_IBI_RESP_IBI_STS_NACK            0x03
+
+#define SLV_NACK_REQ               0x9c
+#define SLV_NACK_REQ_NACK_REQ(x)   ((x) & GENMASK(1, 0))
+#define SLV_NACK_REQ_NACK_REQ_ACK  0x00
+#define SLV_NACK_REQ_NACK_REQ_NACK 0x01
+
+#define DEVICE_CTRL_EXTENDED                           0xb0
+#define DEVICE_CTRL_EXTENDED_DEV_OPERATION_MODE(x)     ((x) & GENMASK(1, 0))
+#define DEVICE_CTRL_EXTENDED_DEV_OPERATION_MODE_MASTER 0
+#define DEVICE_CTRL_EXTENDED_DEV_OPERATION_MODE_SLAVE  1
+
+#define SCL_I3C_OD_TIMING      0xb4
+#define SCL_I3C_PP_TIMING      0xb8
+#define SCL_I3C_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16))
+#define SCL_I3C_TIMING_LCNT(x) ((x) & GENMASK(7, 0))
+#define SCL_I3C_TIMING_CNT_MIN 5
+#define SCL_I3C_TIMING_CNT_MAX 255
+
+#define SCL_I2C_FM_TIMING         0xbc
+#define SCL_I2C_FM_TIMING_HCNT(x) (((x) << 16) & GENMASK(31, 16))
+#define SCL_I2C_FM_TIMING_LCNT(x) ((x) & GENMASK(15, 0))
+
+#define SCL_I2C_FMP_TIMING         0xc0
+#define SCL_I2C_FMP_TIMING_HCNT(x) (((x) << 16) & GENMASK(23, 16))
+#define SCL_I2C_FMP_TIMING_LCNT(x) ((x) & GENMASK(15, 0))
+
+#define SCL_EXT_LCNT_TIMING 0xc8
+#define SCL_EXT_LCNT_4(x)   (((x) << 24) & GENMASK(31, 24))
+#define SCL_EXT_LCNT_3(x)   (((x) << 16) & GENMASK(23, 16))
+#define SCL_EXT_LCNT_2(x)   (((x) << 8) & GENMASK(15, 8))
+#define SCL_EXT_LCNT_1(x)   ((x) & GENMASK(7, 0))
+
+#define SCL_EXT_TERMN_LCNT_TIMING 0xcc
+
+#define SDA_HOLD_SWITCH_DLY_TIMING                         0xd0
+#define SDA_HOLD_SWITCH_DLY_TIMING_SDA_TX_HOLD(x)          (((x)&GENMASK(18, 16)) >> 16)
+#define SDA_HOLD_SWITCH_DLY_TIMING_SDA_PP_OD_SWITCH_DLY(x) (((x)&GENMASK(10, 8)) >> 8)
+#define SDA_HOLD_SWITCH_DLY_TIMING_SDA_OD_PP_SWITCH_DLY(x) ((x)&GENMASK(2, 0))
+
+#define BUS_FREE_TIMING           0xd4
+/* Bus available time of 1us in ns */
+#define I3C_BUS_AVAILABLE_TIME_NS 1000U
+#define BUS_I3C_MST_FREE(x)       ((x) & GENMASK(15, 0))
+#define BUS_I3C_AVAIL_TIME(x)     ((x << 16) & GENMASK(31, 16))
+
+#define BUS_IDLE_TIMING      0xd8
+/* Bus Idle time of 1ms in ns */
+#define I3C_BUS_IDLE_TIME_NS 1000000U
+#define BUS_I3C_IDLE_TIME(x) ((x) & GENMASK(19, 0))
+
+#define I3C_VER_ID          0xe0
+#define I3C_VER_TYPE        0xe4
+#define EXTENDED_CAPABILITY 0xe8
+#define SLAVE_CONFIG        0xec
+
+#define QUEUE_SIZE_CAPABILITY                        0xe8
+#define QUEUE_SIZE_CAPABILITY_IBI_BUF_DWORD_SIZE(x)  (2 << (((x) & GENMASK(19, 16)) >> 16))
+#define QUEUE_SIZE_CAPABILITY_RESP_BUF_DWORD_SIZE(x) (2 << (((x) & GENMASK(15, 12)) >> 12))
+#define QUEUE_SIZE_CAPABILITY_CMD_BUF_DWORD_SIZE(x)  (2 << (((x) & GENMASK(11, 8)) >> 8))
+#define QUEUE_SIZE_CAPABILITY_RX_BUF_DWORD_SIZE(x)   (2 << (((x) & GENMASK(7, 4)) >> 4))
+#define QUEUE_SIZE_CAPABILITY_TX_BUF_DWORD_SIZE(x)   (2 << ((x) & GENMASK(3, 0)))
+
+#define DEV_ADDR_TABLE_LEGACY_I2C_DEV    BIT(31)
+#define DEV_ADDR_TABLE_DYNAMIC_ADDR_MASK GENMASK(23, 16)
+#define DEV_ADDR_TABLE_DYNAMIC_ADDR(x)   (((x) << 16) & GENMASK(23, 16))
+#define DEV_ADDR_TABLE_SIR_REJECT        BIT(13)
+#define DEV_ADDR_TABLE_IBI_WITH_DATA     BIT(12)
+#define DEV_ADDR_TABLE_STATIC_ADDR(x)    ((x) & GENMASK(6, 0))
+#define DEV_ADDR_TABLE_LOC(start, idx)   ((start) + ((idx) << 2))
+
+#define DEV_CHAR_TABLE_LOC1(start, idx) ((start) + ((idx) << 4))
+#define DEV_CHAR_TABLE_MSB_PID(x)       ((x) & GENMASK(31, 16))
+#define DEV_CHAR_TABLE_LSB_PID(x)       ((x) & GENMASK(15, 0))
+#define DEV_CHAR_TABLE_LOC2(start, idx) ((DEV_CHAR_TABLE_LOC1(start, idx)) + 4)
+#define DEV_CHAR_TABLE_LOC3(start, idx) ((DEV_CHAR_TABLE_LOC1(start, idx)) + 8)
+#define DEV_CHAR_TABLE_DCR(x)           ((x) & GENMASK(7, 0))
+#define DEV_CHAR_TABLE_BCR(x)           (((x) & GENMASK(15, 8)) >> 8)
+
+#define I3C_BUS_SDR1_SCL_RATE       8000000
+#define I3C_BUS_SDR2_SCL_RATE       6000000
+#define I3C_BUS_SDR3_SCL_RATE       4000000
+#define I3C_BUS_SDR4_SCL_RATE       2000000
+#define I3C_BUS_I2C_FM_TLOW_MIN_NS  1300
+#define I3C_BUS_I2C_FMP_TLOW_MIN_NS 500
+#define I3C_BUS_THIGH_MAX_NS        41
+#define I3C_PERIOD_NS               1000000000ULL
+
+#define I3C_BUS_MAX_I3C_SCL_RATE     12900000
+#define I3C_BUS_TYP_I3C_SCL_RATE     12500000
+#define I3C_BUS_I2C_FM_PLUS_SCL_RATE 1000000
+#define I3C_BUS_I2C_FM_SCL_RATE      400000
+#define I3C_BUS_TLOW_OD_MIN_NS       200
+
+#define I3C_HOT_JOIN_ADDR 0x02
+
+#define DW_I3C_MAX_DEVS         32
+#define DW_I3C_MAX_CMD_BUF_SIZE 16
+
+/* Snps I3C/I2C Device Private Data */
+struct dw_i3c_i2c_dev_data {
+	/* Device id within the retaining registers. This is set after bus initialization by the
+	 * controller.
+	 */
+	uint8_t id;
+};
+
+struct dw_i3c_cmd {
+	uint32_t cmd_lo;
+	uint32_t cmd_hi;
+	void *buf;
+	uint16_t tx_len;
+	uint16_t rx_len;
+	uint8_t error;
+};
+
+struct dw_i3c_xfer {
+	int32_t ret;
+	uint32_t ncmds;
+	struct dw_i3c_cmd cmds[DW_I3C_MAX_CMD_BUF_SIZE];
+};
+
+struct dw_i3c_config {
+	struct i3c_driver_config common;
+	const struct device *clock;
+	uint32_t regs;
+
+	/* Initial clk configuration */
+	/* Maximum OD high clk pulse length */
+	uint32_t od_thigh_max_ns;
+	/* Minimum OD low clk pulse length */
+	uint32_t od_tlow_min_ns;
+
+	void (*irq_config_func)();
+
+#if defined(CONFIG_PINCTRL)
+	const struct pinctrl_dev_config *pcfg;
+#endif
+};
+
+struct dw_i3c_data {
+	struct i3c_driver_data common;
+	uint32_t free_pos;
+
+	uint16_t datstartaddr;
+	uint16_t dctstartaddr;
+	uint16_t maxdevs;
+
+	/* fifo depth is in words (32b) */
+	uint8_t ibififodepth;
+	uint8_t respfifodepth;
+	uint8_t cmdfifodepth;
+	uint8_t rxfifodepth;
+	uint8_t txfifodepth;
+
+#ifdef CONFIG_I3C_TARGET
+	struct i3c_target_config *target_config;
+#endif /* CONFIG_I3C_TARGET */
+	struct k_sem sem_xfer;
+	struct k_mutex mt;
+
+#ifdef CONFIG_I3C_USE_IBI
+	struct k_sem ibi_sts_sem;
+	struct k_sem sem_hj;
+#endif
+
+	struct dw_i3c_xfer xfer;
+#ifdef CONFIG_I3C_CONTROLLER
+	enum i3c_bus_mode mode;
+	struct dw_i3c_i2c_dev_data dw_i3c_i2c_priv_data[DW_I3C_MAX_DEVS];
+#endif /* CONFIG_I3C_CONTROLLER */
+};
+#ifdef CONFIG_I3C_CONTROLLER
+static uint8_t get_free_pos(uint32_t free_pos)
+{
+	return find_lsb_set(free_pos) - 1;
+}
+
+/**
+ * @brief Read data from the Receive FIFO of the I3C device.
+ *
+ * This function reads data from the Receive FIFO of the I3C device specified by
+ * the given device structure and stores it in the provided buffer.
+ *
+ * @param dev Pointer to the I3C device structure.
+ * @param buf Pointer to the buffer where the received data will be stored.
+ * @param nbytes Number of bytes to read from the Receive FIFO.
+ */
+static void read_rx_fifo(const struct device *dev, uint8_t *buf, int32_t nbytes)
+{
+	__ASSERT((buf != NULL), "Rx buffer should not be NULL");
+
+	const struct dw_i3c_config *config = dev->config;
+	int32_t i;
+	uint32_t tmp;
+
+	if (nbytes >= 4) {
+		for (i = 0; i <= nbytes - 4; i += 4) {
+			tmp = sys_read32(config->regs + RX_TX_DATA_PORT);
+			memcpy(buf + i, &tmp, 4);
+		}
+	}
+	if (nbytes & 3) {
+		tmp = sys_read32(config->regs + RX_TX_DATA_PORT);
+		memcpy(buf + (nbytes & ~3), &tmp, nbytes & 3);
+	}
+}
+#endif /* CONFIG_I3C_CONTROLLER */
+/**
+ * @brief Write data to the Transmit FIFO of the I3C device.
+ *
+ * This function writes data to the Transmit FIFO of the I3C device specified by
+ * the given device structure from the provided buffer.
+ *
+ * @param dev Pointer to the I3C device structure.
+ * @param buf Pointer to the buffer containing the data to be written.
+ * @param nbytes Number of bytes to write to the Transmit FIFO.
+ */
+static void write_tx_fifo(const struct device *dev, const uint8_t *buf, int32_t nbytes)
+{
+	__ASSERT((buf != NULL), "Tx buffer should not be NULL");
+
+	const struct dw_i3c_config *config = dev->config;
+	int32_t i;
+	uint32_t tmp;
+
+	if (nbytes >= 4) {
+		for (i = 0; i <= nbytes - 4; i += 4) {
+			memcpy(&tmp, buf + i, 4);
+			sys_write32(tmp, config->regs + RX_TX_DATA_PORT);
+		}
+	}
+
+	if (nbytes & 3) {
+		tmp = 0;
+		memcpy(&tmp, buf + (nbytes & ~3), nbytes & 3);
+		sys_write32(tmp, config->regs + RX_TX_DATA_PORT);
+	}
+}
+
+#ifdef CONFIG_I3C_USE_IBI
+#ifdef CONFIG_I3C_CONTROLLER
+/**
+ * @brief Read data from the In-Band Interrupt (IBI) FIFO of the I3C device.
+ *
+ * This function reads data from the In-Band Interrupt (IBI) FIFO of the I3C device
+ * specified by the given device structure and stores it in the provided buffer.
+ *
+ * @param dev Pointer to the I3C device structure.
+ * @param buf Pointer to the buffer where the received IBI data will be stored.
+ * @param nbytes Number of bytes to read from the IBI FIFO.
+ */
+static void read_ibi_fifo(const struct device *dev, uint8_t *buf, int32_t nbytes)
+{
+	__ASSERT((buf != NULL), "Rx IBI buffer should not be NULL");
+
+	const struct dw_i3c_config *config = dev->config;
+	int32_t i;
+	uint32_t tmp;
+
+	if (nbytes >= 4) {
+		for (i = 0; i <= nbytes - 4; i += 4) {
+			tmp = sys_read32(config->regs + IBI_QUEUE_STATUS);
+			memcpy(buf + i, &tmp, 4);
+		}
+	}
+	if (nbytes & 3) {
+		tmp = sys_read32(config->regs + IBI_QUEUE_STATUS);
+		memcpy(buf + (nbytes & ~3), &tmp, nbytes & 3);
+	}
+}
+#endif /* CONFIG_I3C_CONTROLLER */
+#endif /* CONFIG_I3C_USE_IBI */
+
+/**
+ * @brief End the I3C transfer and process responses.
+ *
+ * This function is responsible for ending the I3C transfer on the specified
+ * I3C device. It processes the responses received from the I3C bus, updating the
+ * status and error information in the transfer structure.
+ *
+ * @param dev Pointer to the I3C device structure.
+ */
+static void dw_i3c_end_xfer(const struct device *dev)
+{
+	const struct dw_i3c_config *config = dev->config;
+	struct dw_i3c_data *data = dev->data;
+	struct dw_i3c_xfer *xfer = &data->xfer;
+	struct dw_i3c_cmd *cmd;
+	uint32_t nresp, resp;
+	int i, ret = 0;
+#ifdef CONFIG_I3C_TARGET
+	uint32_t rx_data;
+	int j, k;
+#endif /* CONFIG_I3C_TARGET */
+
+	nresp = QUEUE_STATUS_LEVEL_RESP(sys_read32(config->regs + QUEUE_STATUS_LEVEL));
+	for (i = 0; i < nresp; i++) {
+		uint8_t tid;
+
+		resp = sys_read32(config->regs + RESPONSE_QUEUE_PORT);
+		tid = RESPONSE_PORT_TID(resp);
+		if (tid == 0xf) {
+			/* TODO: handle vendor extension ccc or hdr header in target mode */
+			continue;
+		}
+
+		cmd = &xfer->cmds[tid];
+		cmd->rx_len = RESPONSE_PORT_DATA_LEN(resp);
+		cmd->error = RESPONSE_PORT_ERR_STATUS(resp);
+#ifdef CONFIG_I3C_TARGET
+		/* if we are in target mode */
+		if (!(sys_read32(config->regs + PRESENT_STATE) & PRESENT_STATE_CURRENT_MASTER)) {
+			const struct i3c_target_callbacks *target_cb =
+				data->target_config->callbacks;
+
+			for (j = 0; j < cmd->rx_len; j += 4) {
+				rx_data = sys_read32(config->regs + RX_TX_DATA_PORT);
+				/* Call write received cb for each remaining byte  */
+				for (k = 0; k < MIN(4, cmd->rx_len - j); k++) {
+					target_cb->write_received_cb(data->target_config,
+								    (rx_data >> (8 * k)) & 0xff);
+				}
+			}
+
+			if (target_cb != NULL && target_cb->stop_cb != NULL) {
+				/*
+				 * TODO: modify API to include status, such as success or aborted
+				 * transfer
+				 */
+				target_cb->stop_cb(data->target_config);
+			}
+		}
+#endif /* CONFIG_I3C_TARGET */
+	}
+
+	for (i = 0; i < nresp; i++) {
+		switch (xfer->cmds[i].error) {
+		case RESPONSE_NO_ERROR:
+			break;
+		case RESPONSE_ERROR_PARITY:
+		case RESPONSE_ERROR_IBA_NACK:
+		case RESPONSE_ERROR_TRANSF_ABORT:
+		case RESPONSE_ERROR_CRC:
+		case RESPONSE_ERROR_FRAME:
+			ret = -EIO;
+			break;
+		case RESPONSE_ERROR_OVER_UNDER_FLOW:
+			ret = -ENOSPC;
+			break;
+		case RESPONSE_ERROR_I2C_W_NACK_ERR:
+		case RESPONSE_ERROR_ADDRESS_NACK:
+			ret = -ENXIO;
+			break;
+		default:
+			ret = -EINVAL;
+			break;
+		}
+	}
+	xfer->ret = ret;
+
+	if (ret < 0) {
+		sys_write32(RESET_CTRL_RX_FIFO | RESET_CTRL_TX_FIFO | RESET_CTRL_RESP_QUEUE |
+			    RESET_CTRL_CMD_QUEUE,
+			    config->regs + RESET_CTRL);
+		sys_write32(sys_read32(config->regs + DEVICE_CTRL) | DEV_CTRL_RESUME,
+			    config->regs + DEVICE_CTRL);
+	}
+	k_sem_give(&data->sem_xfer);
+}
+
+/**
+ * @brief Start an I3C transfer on the specified device.
+ *
+ * This function initiates an I3C transfer on the specified I3C device by pushing
+ * data to the Transmit FIFO (TXFIFO) and enqueuing commands to the command queue.
+ *
+ * @param dev Pointer to the I3C device structure.
+ */
+static void start_xfer(const struct device *dev)
+{
+	const struct dw_i3c_config *config = dev->config;
+	struct dw_i3c_data *data = dev->data;
+	struct dw_i3c_xfer *xfer = &data->xfer;
+	struct dw_i3c_cmd *cmd;
+	uint32_t thld_ctrl, present_state;
+	int32_t i;
+
+	present_state = sys_read32(config->regs + PRESENT_STATE);
+
+	/* Push data to TXFIFO */
+	for (i = 0; i < xfer->ncmds; i++) {
+		cmd = &xfer->cmds[i];
+		/* Not all the commands use write_tx_fifo function */
+		if (cmd->buf != NULL) {
+			write_tx_fifo(dev, cmd->buf, cmd->tx_len);
+		}
+	}
+
+	thld_ctrl = sys_read32(config->regs + QUEUE_THLD_CTRL);
+	thld_ctrl &= ~QUEUE_THLD_CTRL_RESP_BUF_MASK;
+	thld_ctrl |= QUEUE_THLD_CTRL_RESP_BUF(xfer->ncmds);
+	sys_write32(thld_ctrl, config->regs + QUEUE_THLD_CTRL);
+
+	/* Enqueue CMD */
+	for (i = 0; i < xfer->ncmds; i++) {
+		cmd = &xfer->cmds[i];
+		/* Only cmd_lo is used when it is a target */
+		if (present_state & PRESENT_STATE_CURRENT_MASTER) {
+			sys_write32(cmd->cmd_hi, config->regs + COMMAND_QUEUE_PORT);
+		}
+		sys_write32(cmd->cmd_lo, config->regs + COMMAND_QUEUE_PORT);
+	}
+}
+#ifdef CONFIG_I3C_CONTROLLER
+/**
+ * @brief Get the position of an I3C device with the specified address.
+ *
+ * This function retrieves the position (ID) of an I3C device with the specified
+ * address on the I3C bus associated with the provided I3C device structure. This
+ * utilizes the controller private data for where the id reg is stored.
+ *
+ * @param dev Pointer to the I3C device structure.
+ * @param addr I3C address of the device whose position is to be retrieved.
+ * @param sa True if looking up by Static Address, False if by Dynamic Address
+ *
+ * @return The position (ID) of the device on success, or a negative error code
+ *         if the device with the given address is not found.
+ */
+static int get_i3c_addr_pos(const struct device *dev, uint8_t addr, bool sa)
+{
+	struct dw_i3c_i2c_dev_data *dw_i3c_device_data;
+	struct i3c_device_desc *desc = sa ? i3c_dev_list_i3c_static_addr_find(dev, addr)
+					  : i3c_dev_list_i3c_addr_find(dev, addr);
+
+	if (desc == NULL) {
+		return -ENODEV;
+	}
+
+	dw_i3c_device_data = desc->controller_priv;
+
+	return dw_i3c_device_data->id;
+}
+
+/**
+ * @brief Transfer messages in I3C mode.
+ *
+ * @param dev Pointer to device driver instance.
+ * @param target Pointer to target device descriptor.
+ * @param msgs Pointer to I3C messages.
+ * @param num_msgs Number of messages to transfers.
+ *
+ * @retval 0 If successful.
+ * @retval -EIO General input / output error.
+ * @retval -EINVAL Address not registered
+ */
+static int dw_i3c_xfers(const struct device *dev, struct i3c_device_desc *target,
+			struct i3c_msg *msgs, uint8_t num_msgs)
+{
+	const struct dw_i3c_config *config = dev->config;
+	struct dw_i3c_data *data = dev->data;
+	struct dw_i3c_xfer *xfer = &data->xfer;
+	int32_t ret, i, pos, nrxwords = 0, ntxwords = 0;
+	uint32_t present_state;
+
+	present_state = sys_read32(config->regs + PRESENT_STATE);
+	if (!(present_state & PRESENT_STATE_CURRENT_MASTER)) {
+		return -EACCES;
+	}
+
+	if (num_msgs > data->cmdfifodepth) {
+		return -ENOTSUP;
+	}
+
+	pos = get_i3c_addr_pos(dev, target->dynamic_addr, false);
+	if (pos < 0) {
+		LOG_ERR("%s: Invalid slave device", dev->name);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < num_msgs; i++) {
+		if (msgs[i].flags & I2C_MSG_READ) {
+			nrxwords += DIV_ROUND_UP(msgs[i].len, 4);
+		} else {
+			ntxwords += DIV_ROUND_UP(msgs[i].len, 4);
+		}
+	}
+
+	if (ntxwords > data->txfifodepth || nrxwords > data->rxfifodepth) {
+		return -ENOTSUP;
+	}
+
+	ret = k_mutex_lock(&data->mt, K_MSEC(1000));
+	if (ret) {
+		LOG_ERR("%s: Mutex err (%d)", dev->name, ret);
+		return ret;
+	}
+
+	pm_device_busy_set(dev);
+
+	memset(xfer, 0, sizeof(struct dw_i3c_xfer));
+
+	xfer->ncmds = num_msgs;
+	xfer->ret = -1;
+
+	for (i = 0; i < num_msgs; i++) {
+		struct dw_i3c_cmd *cmd = &xfer->cmds[i];
+
+		cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(msgs[i].len) | COMMAND_PORT_TRANSFER_ARG;
+		cmd->cmd_lo = COMMAND_PORT_TID(i) | COMMAND_PORT_DEV_INDEX(pos) | COMMAND_PORT_ROC;
+
+		cmd->buf = msgs[i].buf;
+
+		if (msgs[i].flags & I3C_MSG_NBCH) {
+			sys_write32(sys_read32(config->regs + DEVICE_CTRL) & ~DEV_CTRL_IBA_INCLUDE,
+				    config->regs + DEVICE_CTRL);
+		} else {
+			sys_write32(sys_read32(config->regs + DEVICE_CTRL) | DEV_CTRL_IBA_INCLUDE,
+				    config->regs + DEVICE_CTRL);
+		}
+
+		if (msgs[i].flags & I3C_MSG_READ) {
+			uint8_t rd_speed;
+
+			if (msgs[i].flags & I3C_MSG_HDR) {
+				/* Set read command bit for DDR and TS */
+				cmd->cmd_lo |= COMMAND_PORT_CP |
+					       COMMAND_PORT_CMD(BIT(7) | (msgs[i].hdr_cmd_code &
+									  GENMASK(6, 0)));
+				if (msgs[i].hdr_mode & I3C_MSG_HDR_DDR) {
+					if (data->common.ctrl_config.supported_hdr &
+					    I3C_MSG_HDR_DDR) {
+						rd_speed = COMMAND_PORT_SPEED_I3C_DDR;
+					} else {
+						/* DDR support not configured with this */
+						LOG_ERR("%s: HDR-DDR not supported", dev->name);
+						ret = -ENOTSUP;
+						goto error;
+					}
+				} else if (msgs[i].hdr_mode & I3C_MSG_HDR_TSP ||
+					   msgs[i].hdr_mode & I3C_MSG_HDR_TSL) {
+					if (data->common.ctrl_config.supported_hdr &
+					    (I3C_MSG_HDR_TSP | I3C_MSG_HDR_TSL)) {
+						rd_speed = COMMAND_PORT_SPEED_I3C_TS;
+					} else {
+						/* TS support not configured with this */
+						LOG_ERR("%s: HDR-TS not supported", dev->name);
+						ret = -ENOTSUP;
+						goto error;
+					}
+				} else {
+					LOG_ERR("%s: HDR %d not supported", dev->name,
+						msgs[i].hdr_mode);
+					ret = -ENOTSUP;
+					goto error;
+				}
+			} else {
+				rd_speed = I3C_CCC_GETMXDS_MAXRD_MAX_SDR_FSCL(
+					target->data_speed.maxrd);
+			}
+
+			cmd->cmd_lo |= (COMMAND_PORT_READ_TRANSFER | COMMAND_PORT_SPEED(rd_speed));
+			cmd->rx_len = msgs[i].len;
+		} else {
+			uint8_t wr_speed;
+
+			if (msgs[i].flags & I3C_MSG_HDR) {
+				cmd->cmd_lo |=
+					COMMAND_PORT_CP |
+					COMMAND_PORT_CMD(msgs[i].hdr_cmd_code & GENMASK(6, 0));
+				if (msgs[i].hdr_mode & I3C_MSG_HDR_DDR) {
+					if (data->common.ctrl_config.supported_hdr &
+					    I3C_MSG_HDR_DDR) {
+						wr_speed = COMMAND_PORT_SPEED_I3C_DDR;
+					} else {
+						/* DDR support not configured with this */
+						LOG_ERR("%s: HDR-DDR not supported", dev->name);
+						ret = -ENOTSUP;
+						goto error;
+					}
+				} else if (msgs[i].hdr_mode & I3C_MSG_HDR_TSP ||
+					   msgs[i].hdr_mode & I3C_MSG_HDR_TSL) {
+					if (data->common.ctrl_config.supported_hdr &
+					    (I3C_MSG_HDR_TSP | I3C_MSG_HDR_TSL)) {
+						wr_speed = COMMAND_PORT_SPEED_I3C_TS;
+					} else {
+						/* TS support not configured with this */
+						LOG_ERR("%s: HDR-TS not supported", dev->name);
+						ret = -ENOTSUP;
+						goto error;
+					}
+				} else {
+					LOG_ERR("%s: HDR %d not supported", dev->name,
+						msgs[i].hdr_mode);
+					ret = -ENOTSUP;
+					goto error;
+				}
+			} else {
+				wr_speed = I3C_CCC_GETMXDS_MAXWR_MAX_SDR_FSCL(
+					target->data_speed.maxwr);
+			}
+
+			cmd->cmd_lo |= COMMAND_PORT_SPEED(wr_speed);
+			cmd->tx_len = msgs[i].len;
+		}
+
+		if (i == (num_msgs - 1)) {
+			cmd->cmd_lo |= COMMAND_PORT_TOC;
+		}
+	}
+
+	start_xfer(dev);
+
+	ret = k_sem_take(&data->sem_xfer, K_MSEC(CONFIG_I3C_DW_RW_TIMEOUT_MS));
+	if (ret) {
+		LOG_ERR("%s: Semaphore err (%d)", dev->name, ret);
+		goto error;
+	}
+
+	for (i = 0; i < xfer->ncmds; i++) {
+		msgs[i].num_xfer = (msgs[i].flags & I3C_MSG_READ) ? xfer->cmds[i].rx_len
+								  : xfer->cmds[i].tx_len;
+		if (xfer->cmds[i].rx_len && !xfer->cmds[i].error) {
+			read_rx_fifo(dev, xfer->cmds[i].buf, xfer->cmds[i].rx_len);
+		}
+	}
+
+	ret = xfer->ret;
+
+error:
+	pm_device_busy_clear(dev);
+	k_mutex_unlock(&data->mt);
+
+	return ret;
+}
+
+static int dw_i3c_i2c_attach_device(const struct device *dev, struct i3c_i2c_device_desc *desc)
+{
+	const struct dw_i3c_config *config = dev->config;
+	struct dw_i3c_data *data = dev->data;
+	uint8_t pos;
+
+	pos = get_free_pos(data->free_pos);
+	if (pos < 0) {
+		return -ENOSPC;
+	}
+
+	data->dw_i3c_i2c_priv_data[pos].id = pos;
+	desc->controller_priv = &(data->dw_i3c_i2c_priv_data[pos]);
+	data->free_pos &= ~BIT(pos);
+
+	sys_write32(DEV_ADDR_TABLE_LEGACY_I2C_DEV | DEV_ADDR_TABLE_STATIC_ADDR(desc->addr),
+		    config->regs + DEV_ADDR_TABLE_LOC(data->datstartaddr, pos));
+
+	return 0;
+}
+
+static void dw_i3c_i2c_detach_device(const struct device *dev, struct i3c_i2c_device_desc *desc)
+{
+	const struct dw_i3c_config *config = dev->config;
+	struct dw_i3c_data *data = dev->data;
+	struct dw_i3c_i2c_dev_data *dw_i2c_device_data = desc->controller_priv;
+
+	__ASSERT_NO_MSG(dw_i2c_device_data != NULL);
+
+	sys_write32(0,
+		    config->regs + DEV_ADDR_TABLE_LOC(data->datstartaddr, dw_i2c_device_data->id));
+	data->free_pos |= BIT(dw_i2c_device_data->id);
+	desc->controller_priv = NULL;
+}
+
+/**
+ * @brief Transfer messages in I2C mode.
+ *
+ * @param dev Pointer to device driver instance.
+ * @param target Pointer to target device descriptor.
+ * @param msgs Pointer to I2C messages.
+ * @param num_msgs Number of messages to transfers.
+ *
+ * @retval 0 If successful.
+ * @retval -EIO General input / output error.
+ * @retval -EINVAL Address not registered
+ */
+static int dw_i3c_i2c_transfer(const struct device *dev, struct i3c_i2c_device_desc *target,
+			       struct i2c_msg *msgs, uint8_t num_msgs)
+{
+	const struct dw_i3c_config *config = dev->config;
+	struct dw_i3c_data *data = dev->data;
+	struct dw_i3c_xfer *xfer = &data->xfer;
+	int32_t ret, i, pos, nrxwords = 0, ntxwords = 0;
+	uint32_t present_state;
+
+	present_state = sys_read32(config->regs + PRESENT_STATE);
+	if (!(present_state & PRESENT_STATE_CURRENT_MASTER)) {
+		return -EACCES;
+	}
+
+	if (num_msgs > data->cmdfifodepth) {
+		return -ENOTSUP;
+	}
+
+	for (i = 0; i < num_msgs; i++) {
+		if (msgs[i].flags & I2C_MSG_READ) {
+			nrxwords += DIV_ROUND_UP(msgs[i].len, 4);
+		} else {
+			ntxwords += DIV_ROUND_UP(msgs[i].len, 4);
+		}
+	}
+
+	if (ntxwords > data->txfifodepth || nrxwords > data->rxfifodepth) {
+		return -ENOTSUP;
+	}
+
+	ret = k_mutex_lock(&data->mt, K_MSEC(1000));
+	if (ret) {
+		LOG_ERR("%s: Mutex err (%d)", dev->name, ret);
+		return ret;
+	}
+
+	pm_device_busy_set(dev);
+
+	/* In order limit the number of retaining registers occupied by connected devices,
+	 * I2C devices are only configured during transfers. This allows the number of devices
+	 * to be larger than the number of retaining registers on mixed buses.
+	 */
+	ret = dw_i3c_i2c_attach_device(dev, target);
+	if (ret != 0) {
+		LOG_ERR("%s: Failed to attach I2C device (%d)", dev->name, ret);
+		goto error_attach;
+	}
+	pos = ((struct dw_i3c_i2c_dev_data *)target->controller_priv)->id;
+
+	memset(xfer, 0, sizeof(struct dw_i3c_xfer));
+
+	xfer->ncmds = num_msgs;
+	xfer->ret = -1;
+
+	for (i = 0; i < num_msgs; i++) {
+		struct dw_i3c_cmd *cmd = &xfer->cmds[i];
+
+		cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(msgs[i].len) | COMMAND_PORT_TRANSFER_ARG;
+		cmd->cmd_lo = COMMAND_PORT_TID(i) | COMMAND_PORT_DEV_INDEX(pos) | COMMAND_PORT_ROC;
+
+		cmd->buf = msgs[i].buf;
+
+		if (msgs[i].flags & I2C_MSG_READ) {
+			uint8_t rd_speed = I3C_LVR_I2C_MODE(target->lvr) == I3C_LVR_I2C_FM_MODE
+						   ? COMMAND_PORT_SPEED_I2C_FM
+						   : COMMAND_PORT_SPEED_I2C_FMP;
+
+			cmd->cmd_lo |= (COMMAND_PORT_READ_TRANSFER | COMMAND_PORT_SPEED(rd_speed));
+			cmd->rx_len = msgs[i].len;
+		} else {
+			uint8_t wr_speed = I3C_LVR_I2C_MODE(target->lvr) == I3C_LVR_I2C_FM_MODE
+						   ? COMMAND_PORT_SPEED_I2C_FM
+						   : COMMAND_PORT_SPEED_I2C_FMP;
+
+			cmd->cmd_lo |= COMMAND_PORT_SPEED(wr_speed);
+			cmd->tx_len = msgs[i].len;
+		}
+
+		if (i == (num_msgs - 1)) {
+			cmd->cmd_lo |= COMMAND_PORT_TOC;
+		}
+	}
+
+	/* Do not send broadcast address (0x7E) with I2C transfers */
+	sys_write32(sys_read32(config->regs + DEVICE_CTRL) & ~DEV_CTRL_IBA_INCLUDE,
+		    config->regs + DEVICE_CTRL);
+
+	start_xfer(dev);
+
+	ret = k_sem_take(&data->sem_xfer, K_MSEC(CONFIG_I3C_DW_RW_TIMEOUT_MS));
+	if (ret) {
+		LOG_ERR("%s: Semaphore err (%d)", dev->name, ret);
+		goto error;
+	}
+
+	for (i = 0; i < xfer->ncmds; i++) {
+		if (xfer->cmds[i].rx_len && !xfer->cmds[i].error) {
+			read_rx_fifo(dev, xfer->cmds[i].buf, xfer->cmds[i].rx_len);
+		}
+	}
+
+	ret = xfer->ret;
+
+error:
+	dw_i3c_i2c_detach_device(dev, target);
+error_attach:
+	pm_device_busy_clear(dev);
+	k_mutex_unlock(&data->mt);
+
+	return ret;
+}
+
+/**
+ * Find a registered I2C target device.
+ *
+ * Controller only API.
+ *
+ * This returns the I2C device descriptor of the I2C device
+ * matching the device address @p addr.
+ *
+ * @param dev Pointer to controller device driver instance.
+ * @param id I2C target device address.
+ *
+ * @return @see i3c_i2c_device_find.
+ */
+static struct i3c_i2c_device_desc *dw_i3c_i2c_device_find(const struct device *dev, uint16_t addr)
+{
+	return i3c_dev_list_i2c_addr_find(dev, addr);
+}
+
+/**
+ * @brief Transfer messages in I2C mode.
+ *
+ * @see i2c_transfer
+ *
+ * @param dev Pointer to device driver instance.
+ * @param msgs Pointer to I2C messages.
+ * @param num_msgs Number of messages to transfers.
+ * @param addr Address of the I2C target device.
+ *
+ * @return @see i2c_transfer
+ */
+static int dw_i3c_i2c_api_transfer(const struct device *dev, struct i2c_msg *msgs, uint8_t num_msgs,
+				   uint16_t addr)
+{
+	struct i3c_i2c_device_desc *i2c_dev = dw_i3c_i2c_device_find(dev, addr);
+
+	if (i2c_dev == NULL) {
+		return -ENODEV;
+	}
+
+	return dw_i3c_i2c_transfer(dev, i2c_dev, msgs, num_msgs);
+}
+#endif /* CONFIG_I3C_CONTROLLER */
+#ifdef CONFIG_I3C_USE_IBI
+#ifdef CONFIG_I3C_CONTROLLER
+static int dw_i3c_controller_ibi_hj_response(const struct device *dev, bool ack)
+{
+	const struct dw_i3c_config *config = dev->config;
+	uint32_t ctrl = sys_read32(config->regs + DEVICE_CTRL);
+
+	if (ack) {
+		ctrl &= ~DEV_CTRL_HOT_JOIN_NACK;
+	} else {
+		ctrl |= DEV_CTRL_HOT_JOIN_NACK;
+	}
+
+	sys_write32(ctrl, config->regs + DEVICE_CTRL);
+
+	return 0;
+}
+
+static int i3c_dw_endis_ibi(const struct device *dev, struct i3c_device_desc *target, bool en)
+{
+	struct dw_i3c_data *data = dev->data;
+	const struct dw_i3c_config *config = dev->config;
+	uint32_t bitpos, sir_con;
+	struct i3c_ccc_events i3c_events;
+	int ret;
+	int pos;
+
+	pos = get_i3c_addr_pos(dev, target->dynamic_addr, false);
+	if (pos < 0) {
+		LOG_ERR("%s: Invalid Slave address", dev->name);
+		return pos;
+	}
+
+	uint32_t reg = sys_read32(config->regs + DEV_ADDR_TABLE_LOC(data->datstartaddr, pos));
+
+	if (i3c_ibi_has_payload(target)) {
+		reg |= DEV_ADDR_TABLE_IBI_WITH_DATA;
+	} else {
+		reg &= ~DEV_ADDR_TABLE_IBI_WITH_DATA;
+	}
+	if (en) {
+		reg &= ~DEV_ADDR_TABLE_SIR_REJECT;
+	} else {
+		reg |= DEV_ADDR_TABLE_SIR_REJECT;
+	}
+	sys_write32(reg, config->regs + DEV_ADDR_TABLE_LOC(data->datstartaddr, pos));
+
+	sir_con = sys_read32(config->regs + IBI_SIR_REQ_REJECT);
+	/* TODO: what is this macro doing?? */
+	bitpos = IBI_SIR_REQ_ID(target->dynamic_addr);
+
+	if (en) {
+		sir_con &= ~BIT(bitpos);
+	} else {
+		sir_con |= BIT(bitpos);
+	}
+	sys_write32(sir_con, config->regs + IBI_SIR_REQ_REJECT);
+
+	/* Tell target to enable IBI */
+	i3c_events.events = I3C_CCC_EVT_INTR;
+	ret = i3c_ccc_do_events_set(target, en, &i3c_events);
+	if (ret != 0) {
+		LOG_ERR("%s: Error sending IBI ENEC for 0x%02x (%d)", dev->name,
+			target->dynamic_addr, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int dw_i3c_controller_enable_ibi(const struct device *dev, struct i3c_device_desc *target)
+{
+	return i3c_dw_endis_ibi(dev, target, true);
+}
+
+static int dw_i3c_controller_disable_ibi(const struct device *dev, struct i3c_device_desc *target)
+{
+	return i3c_dw_endis_ibi(dev, target, false);
+}
+
+static void dw_i3c_handle_tir(const struct device *dev, uint32_t ibi_status)
+{
+	uint8_t ibi_data[CONFIG_I3C_IBI_MAX_PAYLOAD_SIZE];
+	uint8_t addr, len;
+	int pos;
+
+	addr = IBI_QUEUE_IBI_ADDR(ibi_status);
+	len = IBI_QUEUE_STATUS_DATA_LEN(ibi_status);
+
+	pos = get_i3c_addr_pos(dev, addr, false);
+	if (pos < 0) {
+		LOG_ERR("%s: Invalid Slave address", dev->name);
+		return;
+	}
+
+	struct i3c_device_desc *desc = i3c_dev_list_i3c_addr_find(dev, addr);
+
+	if (desc == NULL) {
+		return;
+	}
+
+	if (len > 0) {
+		read_ibi_fifo(dev, ibi_data, len);
+	}
+
+	if (i3c_ibi_work_enqueue_target_irq(desc, ibi_data, len) != 0) {
+		LOG_ERR("%s: Error enqueue IBI IRQ work", dev->name);
+	}
+}
+
+static void dw_i3c_handle_hj(const struct device *dev, uint32_t ibi_status)
+{
+	if (IBI_QUEUE_STATUS_IBI_STS(ibi_status) & BIT(3)) {
+		LOG_DBG("%s: NAK for HJ", dev->name);
+		return;
+	}
+
+	if (i3c_ibi_work_enqueue_hotjoin(dev) != 0) {
+		LOG_ERR("%s: Error enqueue IBI HJ work", dev->name);
+	}
+}
+
+static void ibis_handle(const struct device *dev)
+{
+	const struct dw_i3c_config *config = dev->config;
+	uint32_t nibis, ibi_stat;
+	int32_t i;
+
+	nibis = sys_read32(config->regs + QUEUE_STATUS_LEVEL);
+	nibis = QUEUE_STATUS_IBI_BUF_BLR(nibis);
+	for (i = 0; i < nibis; i++) {
+		ibi_stat = sys_read32(config->regs + IBI_QUEUE_STATUS);
+		if (IBI_TYPE_SIRQ(ibi_stat)) {
+			dw_i3c_handle_tir(dev, ibi_stat);
+		} else if (IBI_TYPE_HJ(ibi_stat)) {
+			dw_i3c_handle_hj(dev, ibi_stat);
+		} else {
+			LOG_WRN("%s: Controller Role Request Not implemented", dev->name);
+		}
+	}
+}
+#endif /* CONFIG_I3C_CONTROLLER */
+#ifdef CONFIG_I3C_TARGET
+static int dw_i3c_target_ibi_raise_hj(const struct device *dev)
+{
+	const struct dw_i3c_config *config = dev->config;
+	struct dw_i3c_data *data = dev->data;
+	int ret;
+
+	if (!(sys_read32(config->regs + HW_CAPABILITY) & HW_CAPABILITY_SLV_HJ_CAP)) {
+		LOG_ERR("%s: HJ not supported", dev->name);
+		return -ENOTSUP;
+	}
+	if (sys_read32(config->regs + DEVICE_ADDR) & DEVICE_ADDR_DYNAMIC_ADDR_VALID) {
+		LOG_ERR("%s: HJ not available, DA already assigned", dev->name);
+		return -EACCES;
+	}
+	/* if this is set, then it is assumed it is already trying */
+	if ((sys_read32(config->regs + SLV_EVENT_STATUS) & SLV_EVENT_STATUS_HJ_EN)) {
+		LOG_ERR("%s: HJ requests are currently disabled by DISEC", dev->name);
+		return -EAGAIN;
+	}
+
+	/*
+	 * This is issued auto-magically by the IP when certain conditions are meet.
+	 * These include:
+	 * 1. SLV_EVENT_STATUS[HJ_EN] = 1 (or a controller issues Enables HJ events with
+	 * the CCC ENEC, This can be set to 0 with CCC DISEC from a controller)
+	 * 2. The Dynamic address is invalid. (not assigned yet)
+	 * 3. Bus Idle condition is met (1ms) as programmed in the Bus Timing Register
+	 */
+
+	/* enable HJ */
+	sys_write32(sys_read32(config->regs + SLV_EVENT_STATUS) | SLV_EVENT_STATUS_HJ_EN,
+		    config->regs + SLV_EVENT_STATUS);
+
+	ret = k_sem_take(&data->sem_hj, K_MSEC(CONFIG_I3C_DW_RW_TIMEOUT_MS));
+	if (ret) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static int dw_i3c_target_ibi_raise_tir(const struct device *dev, struct i3c_ibi *request)
+{
+	const struct dw_i3c_config *config = dev->config;
+	struct dw_i3c_data *data = dev->data;
+	int status;
+	uint32_t slv_intr_req, slv_ibi_resp;
+
+	if (!(sys_read32(config->regs + HW_CAPABILITY) & HW_CAPABILITY_SLV_IBI_CAP)) {
+		LOG_ERR("%s: IBI TIR not supported", dev->name);
+		return -ENOTSUP;
+	}
+
+	if (!(sys_read32(config->regs + DEVICE_ADDR) & DEVICE_ADDR_DYNAMIC_ADDR_VALID)) {
+		LOG_ERR("%s: IBI TIR not available, DA not assigned", dev->name);
+		return -EACCES;
+	}
+
+	if (!(sys_read32(config->regs + SLV_EVENT_STATUS) & SLV_EVENT_STATUS_SIR_EN)) {
+		LOG_ERR("%s: IBI TIR requests are currently disabled by DISEC", dev->name);
+		return -EAGAIN;
+	}
+
+	slv_intr_req = sys_read32(config->regs + SLV_INTR_REQ);
+	if (sys_read32(config->regs + SLV_CHAR_CTRL) & SLV_CHAR_CTRL_IBI_PAYLOAD) {
+		uint32_t tir_data = 0;
+
+		/* max support length is DA + MDB (1 byte) + 4 data bytes, MDB must be at least
+		 * included
+		 */
+		if ((request->payload_len > 5) || (request->payload_len == 0)) {
+			return -EINVAL;
+		}
+
+		/* MDB should be the first byte of the payload */
+		slv_intr_req |= SLV_INTR_REQ_MDB(request->payload[0]) |
+				SLV_INTR_REQ_SIR_DATA_LENGTH(request->payload_len - 1);
+
+		/* program the tir data packet */
+		tir_data |=
+			SLV_SIR_DATA_BYTE0((request->payload_len > 1) ? request->payload[1] : 0);
+		tir_data |=
+			SLV_SIR_DATA_BYTE1((request->payload_len > 2) ? request->payload[2] : 0);
+		tir_data |=
+			SLV_SIR_DATA_BYTE2((request->payload_len > 3) ? request->payload[3] : 0);
+		tir_data |=
+			SLV_SIR_DATA_BYTE3((request->payload_len > 4) ? request->payload[4] : 0);
+		sys_write32(tir_data, config->regs + SLV_SIR_DATA);
+	}
+
+	/* kick off the ibi tir request */
+	slv_intr_req |= SLV_INTR_REQ_SIR;
+	sys_write32(slv_intr_req, config->regs + SLV_INTR_REQ);
+
+	/* wait for SLV_IBI_RESP update */
+	status = k_sem_take(&data->ibi_sts_sem, K_MSEC(100));
+	if (status != 0) {
+		return -ETIMEDOUT;
+	}
+
+	slv_ibi_resp = sys_read32(config->regs + SLV_INTR_REQ);
+	switch (SLV_IBI_RESP_IBI_STS(slv_ibi_resp)) {
+	case SLV_IBI_RESP_IBI_STS_ACK:
+		LOG_DBG("%s: Controller ACKed IBI TIR", dev->name);
+		return 0;
+	case SLV_IBI_RESP_IBI_STS_NACK:
+		LOG_ERR("%s: Controller NACKed IBI TIR", dev->name);
+		return -EAGAIN;
+	case SLV_IBI_RESP_IBI_STS_EARLY_TERMINATE:
+		LOG_ERR("%s: Controller aborted IBI TIR with %lu remaining", dev->name,
+			SLV_IBI_RESP_DATA_LENGTH(slv_ibi_resp));
+		return -EIO;
+	default:
+		return -EIO;
+	}
+}
+
+static int dw_i3c_target_ibi_raise(const struct device *dev, struct i3c_ibi *request)
+{
+	if (request == NULL) {
+		return -EINVAL;
+	}
+
+	switch (request->ibi_type) {
+	case I3C_IBI_TARGET_INTR:
+		return dw_i3c_target_ibi_raise_tir(dev, request);
+	case I3C_IBI_CONTROLLER_ROLE_REQUEST:
+		/* TODO: Synopsys I3C can support CR, but not implemented yet */
+		return -ENOTSUP;
+	case I3C_IBI_HOTJOIN:
+		return dw_i3c_target_ibi_raise_hj(dev);
+	default:
+		return -EINVAL;
+	}
+}
+#endif /* CONFIG_I3C_TARGET */
+#endif /* CONFIG_I3C_USE_IBI */
+
+static int i3c_dw_irq(const struct device *dev)
+{
+	const struct dw_i3c_config *config = dev->config;
+	uint32_t status;
+#ifdef CONFIG_I3C_TARGET
+	struct dw_i3c_data *data = dev->data;
+	uint32_t present_state;
+#endif /* CONFIG_I3C_TARGET */
+
+	status = sys_read32(config->regs + INTR_STATUS);
+	if (status & (INTR_TRANSFER_ERR_STAT | INTR_RESP_READY_STAT)) {
+		dw_i3c_end_xfer(dev);
+
+		if (status & INTR_TRANSFER_ERR_STAT) {
+			sys_write32(INTR_TRANSFER_ERR_STAT, config->regs + INTR_STATUS);
+		}
+	}
+#ifdef CONFIG_I3C_CONTROLLER
+	if (status & INTR_IBI_THLD_STAT) {
+#ifdef CONFIG_I3C_USE_IBI
+		ibis_handle(dev);
+#endif /* CONFIG_I3C_USE_IBI */
+	}
+#endif /* CONFIG_I3C_CONTROLLER */
+#ifdef CONFIG_I3C_TARGET
+	/* target mode related interrupts */
+	present_state = sys_read32(config->regs + PRESENT_STATE);
+	if (!(present_state & PRESENT_STATE_CURRENT_MASTER)) {
+		const struct i3c_target_callbacks *target_cb =
+			data->target_config ? data->target_config->callbacks : NULL;
+
+		/* Read Requested when the CMDQ is empty*/
+		if (status & INTR_READ_REQ_RECV_STAT) {
+			if (target_cb != NULL && target_cb->read_requested_cb != NULL) {
+				/* Inform app so that it can send data. */
+				target_cb->read_requested_cb(data->target_config, NULL);
+			}
+			sys_write32(INTR_READ_REQ_RECV_STAT, config->regs + INTR_STATUS);
+		}
+#ifdef CONFIG_I3C_USE_IBI
+		/* IBI TIR request register is addressed and status is updated*/
+		if (status & INTR_IBI_UPDATED_STAT) {
+			k_sem_give(&data->ibi_sts_sem);
+			sys_write32(INTR_IBI_UPDATED_STAT, config->regs + INTR_STATUS);
+		}
+		/* DA has been assigned, could happen after a IBI HJ request */
+		if (status & INTR_DYN_ADDR_ASSGN_STAT) {
+			/* TODO: handle IBI HJ with semaphore */
+			sys_write32(INTR_DYN_ADDR_ASSGN_STAT, config->regs + INTR_STATUS);
+		}
+#endif /* CONFIG_I3C_USE_IBI */
+	}
+#endif /* CONFIG_I3C_TARGET */
+	return 0;
+}
+
+static int init_scl_timing(const struct device *dev)
+{
+	const struct dw_i3c_config *config = dev->config;
+	uint32_t core_rate, scl_timing;
+#ifdef CONFIG_I3C_CONTROLLER
+	struct dw_i3c_data *data = dev->data;
+	uint32_t hcnt, lcnt;
+#endif /* CONFIG_I3C_CONTROLLER */
+
+	if (clock_control_get_rate(config->clock, NULL, &core_rate) != 0) {
+		LOG_ERR("%s: get clock rate failed", dev->name);
+		return -EINVAL;
+	}
+#ifdef CONFIG_I3C_CONTROLLER
+	/* I3C_OD */
+	hcnt = DIV_ROUND_UP(config->od_thigh_max_ns * (uint64_t)core_rate, I3C_PERIOD_NS) - 1;
+	hcnt = CLAMP(hcnt, SCL_I3C_TIMING_CNT_MIN, SCL_I3C_TIMING_CNT_MAX);
+
+	lcnt = DIV_ROUND_UP(config->od_tlow_min_ns * (uint64_t)core_rate, I3C_PERIOD_NS);
+	lcnt = CLAMP(lcnt, SCL_I3C_TIMING_CNT_MIN, SCL_I3C_TIMING_CNT_MAX);
+
+	scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
+	sys_write32(scl_timing, config->regs + SCL_I3C_OD_TIMING);
+
+	/* Set bus free timing to match tlow setting for OD clk config. */
+	sys_write32(BUS_I3C_MST_FREE(lcnt), config->regs + BUS_FREE_TIMING);
+
+	/* I3C_PP */
+	hcnt = DIV_ROUND_UP(I3C_BUS_THIGH_MAX_NS * (uint64_t)core_rate, I3C_PERIOD_NS) - 1;
+	hcnt = CLAMP(hcnt, SCL_I3C_TIMING_CNT_MIN, SCL_I3C_TIMING_CNT_MAX);
+
+	lcnt = DIV_ROUND_UP(core_rate, data->common.ctrl_config.scl.i3c) - hcnt;
+	lcnt = CLAMP(lcnt, SCL_I3C_TIMING_CNT_MIN, SCL_I3C_TIMING_CNT_MAX);
+
+	scl_timing = SCL_I3C_TIMING_HCNT(hcnt) | SCL_I3C_TIMING_LCNT(lcnt);
+	sys_write32(scl_timing, config->regs + SCL_I3C_PP_TIMING);
+
+	/* I3C */
+	lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR1_SCL_RATE) - hcnt;
+	scl_timing = SCL_EXT_LCNT_1(lcnt);
+	lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR2_SCL_RATE) - hcnt;
+	scl_timing |= SCL_EXT_LCNT_2(lcnt);
+	lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR3_SCL_RATE) - hcnt;
+	scl_timing |= SCL_EXT_LCNT_3(lcnt);
+	lcnt = DIV_ROUND_UP(core_rate, I3C_BUS_SDR4_SCL_RATE) - hcnt;
+	scl_timing |= SCL_EXT_LCNT_4(lcnt);
+	sys_write32(scl_timing, config->regs + SCL_EXT_LCNT_TIMING);
+
+	/* I2C FM+ */
+	lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FMP_TLOW_MIN_NS * (uint64_t)core_rate, I3C_PERIOD_NS);
+	hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_PLUS_SCL_RATE) - lcnt;
+	scl_timing = SCL_I2C_FMP_TIMING_HCNT(hcnt) | SCL_I2C_FMP_TIMING_LCNT(lcnt);
+	sys_write32(scl_timing, config->regs + SCL_I2C_FMP_TIMING);
+
+	/* I2C FM */
+	lcnt = DIV_ROUND_UP(I3C_BUS_I2C_FM_TLOW_MIN_NS * (uint64_t)core_rate, I3C_PERIOD_NS);
+	hcnt = DIV_ROUND_UP(core_rate, I3C_BUS_I2C_FM_SCL_RATE) - lcnt;
+	scl_timing = SCL_I2C_FM_TIMING_HCNT(hcnt) | SCL_I2C_FM_TIMING_LCNT(lcnt);
+	sys_write32(scl_timing, config->regs + SCL_I2C_FM_TIMING);
+
+	if (data->mode != I3C_BUS_MODE_PURE) {
+		sys_write32(BUS_I3C_MST_FREE(lcnt), config->regs + BUS_FREE_TIMING);
+		sys_write32(sys_read32(config->regs + DEVICE_CTRL) | DEV_CTRL_I2C_SLAVE_PRESENT,
+			    config->regs + DEVICE_CTRL);
+	}
+#endif /* CONFIG_I3C_CONTROLLER */
+#ifdef CONFIG_I3C_TARGET
+	/* I3C Bus Available Time */
+	scl_timing = DIV_ROUND_UP(I3C_BUS_AVAILABLE_TIME_NS * (uint64_t)core_rate,
+					I3C_PERIOD_NS);
+	sys_write32(BUS_I3C_AVAIL_TIME(scl_timing), config->regs + BUS_FREE_TIMING);
+
+	/* I3C Bus Idle Time */
+	scl_timing =
+		DIV_ROUND_UP(I3C_BUS_IDLE_TIME_NS * (uint64_t)core_rate, I3C_PERIOD_NS);
+	sys_write32(BUS_I3C_IDLE_TIME(scl_timing), config->regs + BUS_IDLE_TIMING);
+#endif /* CONFIG_I3C_TARGET */
+	return 0;
+}
+#ifdef CONFIG_I3C_CONTROLLER
+/**
+ * Determine I3C bus mode from the i2c devices on the bus
+ *
+ * Reads the LVR of all I2C devices and returns the I3C bus
+ * Mode
+ *
+ * @param dev_list Pointer to device list
+ *
+ * @return @see enum i3c_bus_mode.
+ */
+static enum i3c_bus_mode i3c_bus_mode(const struct i3c_dev_list *dev_list)
+{
+	enum i3c_bus_mode mode = I3C_BUS_MODE_PURE;
+
+	for (int i = 0; i < dev_list->num_i2c; i++) {
+		switch (I3C_LVR_I2C_DEV_IDX(dev_list->i2c[i].lvr)) {
+		case I3C_LVR_I2C_DEV_IDX_0:
+			if (mode < I3C_BUS_MODE_MIXED_FAST) {
+				mode = I3C_BUS_MODE_MIXED_FAST;
+			}
+			break;
+		case I3C_LVR_I2C_DEV_IDX_1:
+			if (mode < I3C_BUS_MODE_MIXED_LIMITED) {
+				mode = I3C_BUS_MODE_MIXED_LIMITED;
+			}
+			break;
+		case I3C_LVR_I2C_DEV_IDX_2:
+			if (mode < I3C_BUS_MODE_MIXED_SLOW) {
+				mode = I3C_BUS_MODE_MIXED_SLOW;
+			}
+			break;
+		default:
+			mode = I3C_BUS_MODE_INVALID;
+			break;
+		}
+	}
+	return mode;
+}
+
+static int dw_i3c_attach_device(const struct device *dev, struct i3c_device_desc *desc)
+{
+	const struct dw_i3c_config *config = dev->config;
+	struct dw_i3c_data *data = dev->data;
+	uint8_t pos = get_free_pos(data->free_pos);
+	uint8_t addr = desc->dynamic_addr ? desc->dynamic_addr : desc->static_addr;
+
+	if (pos < 0) {
+		LOG_ERR("%s: no space for i3c device: %s", dev->name, desc->dev->name);
+		return -ENOSPC;
+	}
+
+	data->dw_i3c_i2c_priv_data[pos].id = pos;
+	desc->controller_priv = &(data->dw_i3c_i2c_priv_data[pos]);
+	data->free_pos &= ~BIT(pos);
+
+	LOG_DBG("%s: Attaching %s", dev->name, desc->dev->name);
+
+	sys_write32(DEV_ADDR_TABLE_DYNAMIC_ADDR(addr),
+		    config->regs + DEV_ADDR_TABLE_LOC(data->datstartaddr, pos));
+
+	return 0;
+}
+
+static int dw_i3c_reattach_device(const struct device *dev, struct i3c_device_desc *desc,
+				  uint8_t old_dyn_addr)
+{
+	ARG_UNUSED(old_dyn_addr);
+
+	const struct dw_i3c_config *config = dev->config;
+	struct dw_i3c_data *data = dev->data;
+	struct dw_i3c_i2c_dev_data *dw_i3c_device_data = desc->controller_priv;
+	uint32_t dat;
+
+	if (dw_i3c_device_data == NULL) {
+		LOG_ERR("%s: %s: device not attached", dev->name, desc->dev->name);
+		return -EINVAL;
+	}
+	/* TODO: investigate clearing table beforehand */
+
+	LOG_DBG("Reattaching %s", desc->dev->name);
+
+	dat = sys_read32(config->regs +
+			 DEV_ADDR_TABLE_LOC(data->datstartaddr, dw_i3c_device_data->id));
+	dat &= ~DEV_ADDR_TABLE_DYNAMIC_ADDR_MASK;
+	sys_write32(DEV_ADDR_TABLE_DYNAMIC_ADDR(desc->dynamic_addr) | dat,
+		    config->regs + DEV_ADDR_TABLE_LOC(data->datstartaddr, dw_i3c_device_data->id));
+
+	return 0;
+}
+
+static int dw_i3c_detach_device(const struct device *dev, struct i3c_device_desc *desc)
+{
+	const struct dw_i3c_config *config = dev->config;
+	struct dw_i3c_data *data = dev->data;
+	struct dw_i3c_i2c_dev_data *dw_i3c_device_data = desc->controller_priv;
+
+	if (dw_i3c_device_data == NULL) {
+		LOG_ERR("%s: %s: device not attached", dev->name, desc->dev->name);
+		return -EINVAL;
+	}
+
+	LOG_DBG("%s: Detaching %s", dev->name, desc->dev->name);
+
+	sys_write32(0,
+		    config->regs + DEV_ADDR_TABLE_LOC(data->datstartaddr, dw_i3c_device_data->id));
+	data->free_pos |= BIT(dw_i3c_device_data->id);
+	desc->controller_priv = NULL;
+
+	return 0;
+}
+
+static int set_controller_info(const struct device *dev)
+{
+	const struct dw_i3c_config *config = dev->config;
+	struct dw_i3c_data *data = dev->data;
+	uint8_t controller_da;
+
+	if (config->common.primary_controller_da) {
+		if (!i3c_addr_slots_is_free(&data->common.attached_dev.addr_slots,
+					    config->common.primary_controller_da)) {
+			controller_da = i3c_addr_slots_next_free_find(
+				&data->common.attached_dev.addr_slots, 0);
+			LOG_WRN("%s: 0x%02x DA selected for controller as 0x%02x is unavailable",
+				dev->name, controller_da, config->common.primary_controller_da);
+		} else {
+			controller_da = config->common.primary_controller_da;
+		}
+	} else {
+		controller_da =
+			i3c_addr_slots_next_free_find(&data->common.attached_dev.addr_slots, 0);
+	}
+
+	sys_write32(DEVICE_ADDR_DYNAMIC_ADDR_VALID | DEVICE_ADDR_DYNAMIC(controller_da),
+		    config->regs + DEVICE_ADDR);
+	/* Mark the address as I3C device */
+	i3c_addr_slots_mark_i3c(&data->common.attached_dev.addr_slots, controller_da);
+
+	return 0;
+}
+#endif /* CONFIG_I3C_CONTROLLER */
+static void enable_interrupts(const struct device *dev)
+{
+	const struct dw_i3c_config *config = dev->config;
+	uint32_t thld_ctrl, intr_mask;
+
+	config->irq_config_func();
+
+	thld_ctrl = sys_read32(config->regs + QUEUE_THLD_CTRL);
+	thld_ctrl &= (~QUEUE_THLD_CTRL_RESP_BUF_MASK & ~QUEUE_THLD_CTRL_IBI_STS_MASK);
+	sys_write32(thld_ctrl, config->regs + QUEUE_THLD_CTRL);
+
+	thld_ctrl = sys_read32(config->regs + DATA_BUFFER_THLD_CTRL);
+	thld_ctrl &= ~DATA_BUFFER_THLD_CTRL_RX_BUF;
+	sys_write32(thld_ctrl, config->regs + DATA_BUFFER_THLD_CTRL);
+
+	sys_write32(INTR_ALL, config->regs + INTR_STATUS);
+
+	/* Enable interrupts */
+#if defined(CONFIG_I3C_CONTROLLER) && defined(CONFIG_I3C_TARGET)
+	intr_mask = INTR_MASTER_MASK | INTR_SLAVE_MASK;
+#elif defined(CONFIG_I3C_CONTROLLER)
+	intr_mask = INTR_MASTER_MASK;
+#elif defined(CONFIG_I3C_TARGET)
+	intr_mask = INTR_SLAVE_MASK;
+#endif
+	sys_write32(intr_mask, config->regs + INTR_STATUS_EN);
+	sys_write32(intr_mask, config->regs + INTR_SIGNAL_EN);
+}
+#ifdef CONFIG_I3C_CONTROLLER
+/**
+ * @brief Calculate the odd parity of a byte.
+ *
+ * This function calculates the odd parity of the input byte, returning 1 if the
+ * number of set bits is odd and 0 otherwise.
+ *
+ * @param p The byte for which odd parity is to be calculated.
+ *
+ * @return The odd parity result (1 if odd, 0 if even).
+ */
+static uint8_t odd_parity(uint8_t p)
+{
+	p ^= p >> 4;
+	p &= 0xf;
+	return (0x9669 >> p) & 1;
+}
+
+/**
+ * @brief Send Common Command Code (CCC).
+ *
+ * @see i3c_do_ccc
+ *
+ * @param dev Pointer to controller device driver instance.
+ * @param payload Pointer to CCC payload.
+ *
+ * @return @see i3c_do_ccc
+ */
+static int dw_i3c_do_ccc(const struct device *dev, struct i3c_ccc_payload *payload)
+{
+	const struct dw_i3c_config *config = dev->config;
+	struct dw_i3c_data *data = dev->data;
+	struct dw_i3c_xfer *xfer = &data->xfer;
+	struct dw_i3c_cmd *cmd;
+	int ret, i, pos;
+	uint32_t present_state;
+
+	present_state = sys_read32(config->regs + PRESENT_STATE);
+	if (!(present_state & PRESENT_STATE_CURRENT_MASTER)) {
+		return -EACCES;
+	}
+
+	ret = k_mutex_lock(&data->mt, K_MSEC(1000));
+	if (ret) {
+		LOG_DBG("%s: Mutex err (%d)", dev->name, ret);
+		return ret;
+	}
+
+	pm_device_busy_set(dev);
+
+	memset(xfer, 0, sizeof(struct dw_i3c_xfer));
+	xfer->ret = -1;
+
+	/* in the case of multiple targets in a CCC, each command queue must have the same CCC ID
+	 * loaded along with different dev index fields pointing to the targets
+	 */
+	if (i3c_ccc_is_payload_broadcast(payload)) {
+		xfer->ncmds = 1;
+		cmd = &xfer->cmds[0];
+		cmd->buf = payload->ccc.data;
+
+		cmd->cmd_hi = COMMAND_PORT_ARG_DATA_LEN(payload->ccc.data_len) |
+			      COMMAND_PORT_TRANSFER_ARG;
+		cmd->cmd_lo = COMMAND_PORT_CP | COMMAND_PORT_TOC | COMMAND_PORT_ROC |
+			      COMMAND_PORT_CMD(payload->ccc.id);
+
+		if ((payload->targets.payloads) && (payload->targets.payloads[0].rnw)) {
+			cmd->cmd_lo |= COMMAND_PORT_READ_TRANSFER;
+			cmd->rx_len = payload->ccc.data_len;
+		} else {
+			cmd->tx_len = payload->ccc.data_len;
+		}
+	} else {
+		if (!(payload->targets.payloads)) {
+			LOG_ERR("%s: Direct CCC Payload structure Empty", dev->name);
+			ret = -EINVAL;
+			goto error;
+		}
+		xfer->ncmds = payload->targets.num_targets;
+		for (i = 0; i < payload->targets.num_targets; i++) {
+			cmd = &xfer->cmds[i];
+			/* Look up position, SETDASA will perform the look up by static addr */
+			pos = get_i3c_addr_pos(dev, payload->targets.payloads[i].addr,
+					       payload->ccc.id == I3C_CCC_SETDASA);
+			if (pos < 0) {
+				LOG_ERR("%s: Invalid Slave address with pos %d", dev->name, pos);
+				ret = -ENOSPC;
+				goto error;
+			}
+			cmd->buf = payload->targets.payloads[i].data;
+
+			cmd->cmd_hi =
+				COMMAND_PORT_ARG_DATA_LEN(payload->targets.payloads[i].data_len) |
+				COMMAND_PORT_TRANSFER_ARG;
+			cmd->cmd_lo = COMMAND_PORT_CP | COMMAND_PORT_DEV_INDEX(pos) |
+				      COMMAND_PORT_ROC | COMMAND_PORT_CMD(payload->ccc.id);
+			/* last command queue with multiple targets must have TOC set */
+			if (i == (payload->targets.num_targets - 1)) {
+				cmd->cmd_lo |= COMMAND_PORT_TOC;
+			}
+			/* If there is a defining byte for direct CCC */
+			if (payload->ccc.data_len == 1) {
+				cmd->cmd_lo |= COMMAND_PORT_DBP;
+				cmd->cmd_hi |= COMMAND_PORT_ARG_DB(payload->ccc.data[0]);
+			} else if (payload->ccc.data_len > 1) {
+				LOG_ERR("%s: direct CCCs defining byte >1", dev->name);
+				ret = -EINVAL;
+				goto error;
+			}
+
+			if (payload->targets.payloads[i].rnw) {
+				cmd->cmd_lo |= COMMAND_PORT_READ_TRANSFER;
+				cmd->rx_len = payload->targets.payloads[i].data_len;
+			} else {
+				cmd->tx_len = payload->targets.payloads[i].data_len;
+			}
+		}
+	}
+
+	start_xfer(dev);
+
+	ret = k_sem_take(&data->sem_xfer, K_MSEC(CONFIG_I3C_DW_RW_TIMEOUT_MS));
+	if (ret) {
+		LOG_ERR("%s: Semaphore err (%d)", dev->name, ret);
+		goto error;
+	}
+
+	/* the only way data_len would not equal num_xfer would be if an abort happened */
+	payload->ccc.num_xfer = payload->ccc.data_len;
+	for (i = 0; i < xfer->ncmds; i++) {
+		/* if this is a direct ccc, then write back the number of bytes tx or rx */
+		if (!i3c_ccc_is_payload_broadcast(payload)) {
+			payload->targets.payloads[i].num_xfer = payload->targets.payloads[i].rnw
+									? xfer->cmds[i].rx_len
+									: xfer->cmds[i].tx_len;
+		}
+		if (xfer->cmds[i].rx_len && !xfer->cmds[i].error) {
+			read_rx_fifo(dev, xfer->cmds[i].buf, xfer->cmds[i].rx_len);
+		}
+	}
+
+	ret = xfer->ret;
+error:
+	pm_device_busy_clear(dev);
+	k_mutex_unlock(&data->mt);
+
+	return ret;
+}
+
+/**
+ * @brief Add a slave device from Dynamic Address Assignment (DAA) information.
+ *
+ * This function adds a slave device to the I3C controller based on the Dynamic
+ * Address Assignment (DAA) information at the specified position. It retrieves
+ * the dynamic address, PID (Provisional ID), and additional device characteristics
+ * from the corresponding tables and associates the device with a registered device
+ * descriptor if the PID is known.
+ *
+ * @param dev Pointer to the I3C device structure.
+ * @param pos Position of the device in the DAA and DCT tables.
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
+static int add_slave_from_daa(const struct device *dev, int32_t pos)
+{
+	const struct dw_i3c_config *config = dev->config;
+	struct dw_i3c_data *data = dev->data;
+	uint32_t tmp;
+	uint64_t pid;
+	uint8_t dyn_addr;
+
+	/* retrieve dynamic address assigned */
+	tmp = sys_read32(config->regs + DEV_ADDR_TABLE_LOC(data->datstartaddr, pos));
+	dyn_addr = (((tmp) & GENMASK(22, 16)) >> 16);
+
+	/* retrieve pid */
+	tmp = sys_read32(config->regs + DEV_CHAR_TABLE_LOC1(data->dctstartaddr, pos));
+	pid = ((uint64_t)DEV_CHAR_TABLE_MSB_PID(tmp) << 16) + (DEV_CHAR_TABLE_LSB_PID(tmp) << 16);
+	tmp = sys_read32(config->regs + DEV_CHAR_TABLE_LOC2(data->dctstartaddr, pos));
+	pid |= DEV_CHAR_TABLE_LSB_PID(tmp);
+
+	/* lookup known pids */
+	const struct i3c_device_id i3c_id = I3C_DEVICE_ID(pid);
+	struct i3c_device_desc *target = i3c_device_find(dev, &i3c_id);
+
+	if (target == NULL) {
+		LOG_INF("%s: PID 0x%012llx is not in registered device "
+			"list, given DA 0x%02x",
+			dev->name, pid, dyn_addr);
+	} else {
+		target->dynamic_addr = dyn_addr;
+		tmp = sys_read32(config->regs + DEV_CHAR_TABLE_LOC3(data->dctstartaddr, pos));
+		target->bcr = DEV_CHAR_TABLE_BCR(tmp);
+		target->dcr = DEV_CHAR_TABLE_DCR(tmp);
+
+		LOG_DBG("%s: PID 0x%012llx assigned dynamic address 0x%02x", dev->name, pid,
+			dyn_addr);
+	}
+	i3c_addr_slots_mark_i3c(&data->common.attached_dev.addr_slots, dyn_addr);
+
+	return 0;
+}
+
+/**
+ * @brief Perform Dynamic Address Assignment.
+ *
+ * @see i3c_do_daa
+ *
+ * @param dev Pointer to controller device driver instance.
+ *
+ * @return @see i3c_do_daa
+ */
+static int dw_i3c_do_daa(const struct device *dev)
+{
+	const struct dw_i3c_config *config = dev->config;
+	struct dw_i3c_data *data = dev->data;
+	struct dw_i3c_xfer *xfer = &data->xfer;
+	struct dw_i3c_cmd *cmd;
+	uint32_t olddevs, newdevs;
+	uint8_t p, idx, last_addr = 0;
+	int32_t pos, addr, ret;
+	uint32_t present_state;
+
+	present_state = sys_read32(config->regs + PRESENT_STATE);
+	if (!(present_state & PRESENT_STATE_CURRENT_MASTER)) {
+		return -EACCES;
+	}
+
+	olddevs = ~(data->free_pos);
+
+	/* Prepare DAT before launching DAA. */
+	for (pos = 0; pos < data->maxdevs; pos++) {
+		if (olddevs & BIT(pos)) {
+			continue;
+		}
+
+		addr = i3c_addr_slots_next_free_find(&data->common.attached_dev.addr_slots,
+						     last_addr + 1);
+		if (addr == 0) {
+			return -ENOSPC;
+		}
+
+		p = odd_parity(addr);
+		last_addr = addr;
+		addr |= (p << 7);
+		sys_write32(DEV_ADDR_TABLE_DYNAMIC_ADDR(addr),
+			    config->regs + DEV_ADDR_TABLE_LOC(data->datstartaddr, pos));
+	}
+
+	pos = get_free_pos(data->free_pos);
+	if (pos < 0) {
+		LOG_ERR("%s: find free pos failed", dev->name);
+		return -ENOSPC;
+	}
+
+	ret = k_mutex_lock(&data->mt, K_MSEC(1000));
+	if (ret) {
+		LOG_ERR("%s: Mutex err (%d)", dev->name, ret);
+		return ret;
+	}
+
+	pm_device_busy_set(dev);
+
+	memset(xfer, 0, sizeof(struct dw_i3c_xfer));
+
+	xfer->ncmds = 1;
+	xfer->ret = -1;
+
+	cmd = &xfer->cmds[0];
+	cmd->cmd_hi = COMMAND_PORT_TRANSFER_ARG;
+	cmd->cmd_lo = COMMAND_PORT_TOC | COMMAND_PORT_ROC |
+		      COMMAND_PORT_DEV_COUNT(data->maxdevs - pos) | COMMAND_PORT_DEV_INDEX(pos) |
+		      COMMAND_PORT_CMD(I3C_CCC_ENTDAA) | COMMAND_PORT_ADDR_ASSGN_CMD;
+
+	start_xfer(dev);
+	ret = k_sem_take(&data->sem_xfer, K_MSEC(CONFIG_I3C_DW_RW_TIMEOUT_MS));
+
+	pm_device_busy_clear(dev);
+	k_mutex_unlock(&data->mt);
+
+	if (ret) {
+		LOG_ERR("%s: Semaphore err (%d)", dev->name, ret);
+		return ret;
+	}
+
+	if (data->maxdevs == cmd->rx_len) {
+		newdevs = 0;
+	} else {
+		newdevs = GENMASK(data->maxdevs - cmd->rx_len - 1, 0);
+	}
+	newdevs &= ~olddevs;
+
+	for (pos = find_lsb_set(newdevs); pos <= find_msb_set(newdevs); pos++) {
+		idx = pos - 1;
+		if (newdevs & BIT(idx)) {
+			add_slave_from_daa(dev, idx);
+		}
+	}
+
+	return 0;
+}
+#endif /* CONFIG_I3C_CONTROLLER */
+
+static void dw_i3c_enable_controller(const struct dw_i3c_config *config, bool enable)
+{
+	uint32_t reg = sys_read32(config->regs + DEVICE_CTRL);
+
+	if (enable) {
+		reg |= DEV_CTRL_ENABLE;
+	} else {
+		reg &= ~DEV_CTRL_ENABLE;
+	}
+
+	sys_write32(reg, config->regs + DEVICE_CTRL);
+}
+
+/**
+ * @brief Get configuration of the I3C hardware.
+ *
+ * This provides a way to get the current configuration of the I3C hardware.
+ *
+ * This can return cached config or probed hardware parameters, but it has to
+ * be up to date with current configuration.
+ *
+ * @param[in] dev Pointer to controller device driver instance.
+ * @param[in] type Type of configuration parameters being passed
+ *                 in @p config.
+ * @param[in,out] config Pointer to the configuration parameters.
+ *
+ * Note that if @p type is @c I3C_CONFIG_CUSTOM, @p config must contain
+ * the ID of the parameter to be retrieved.
+ *
+ * @retval 0 If successful.
+ * @retval -EIO General Input/Output errors.
+ * @retval -ENOSYS If not implemented.
+ */
+static int dw_i3c_config_get(const struct device *dev, enum i3c_config_type type, void *config)
+{
+#ifdef CONFIG_I3C_TARGET
+	const struct dw_i3c_config *dev_config = dev->config;
+#endif /* CONFIG_I3C_TARGET */
+#ifdef CONFIG_I3C_CONTROLLER
+	struct dw_i3c_data *data = dev->data;
+#endif /* CONFIG_I3C_CONTROLLER */
+	int ret = 0;
+
+	if (type == I3C_CONFIG_CONTROLLER) {
+#ifdef CONFIG_I3C_CONTROLLER
+		(void)memcpy(config, &data->common.ctrl_config, sizeof(data->common.ctrl_config));
+#else
+		return -ENOTSUP;
+#endif /* CONFIG_I3C_CONTROLLER */
+	} else if (type == I3C_CONFIG_TARGET) {
+#ifdef CONFIG_I3C_TARGET
+		struct i3c_config_target *target_config = config;
+		uint32_t reg;
+
+		reg = sys_read32(dev_config->regs + SLV_MAX_LEN);
+		target_config->max_read_len = SLV_MAX_LEN_MRL(reg);
+		target_config->max_write_len = SLV_MAX_LEN_MWL(reg);
+
+		reg = sys_read32(dev_config->regs + DEVICE_ADDR);
+		if (reg & DEVICE_ADDR_STATIC_ADDR_VALID) {
+			target_config->static_addr = DEVICE_ADDR_STATIC(reg);
+		} else {
+			target_config->static_addr = 0x00;
+		}
+
+		reg = sys_read32(dev_config->regs + SLV_CHAR_CTRL);
+		target_config->bcr = SLV_CHAR_CTRL_BCR(reg);
+		target_config->dcr = SLV_CHAR_CTRL_DCR(reg);
+		target_config->supported_hdr = SLV_CHAR_CTRL_HDR_CAP(reg);
+
+		reg = sys_read32(dev_config->regs + SLV_MIPI_ID_VALUE);
+		target_config->pid = ((uint64_t)reg) << 32;
+		target_config->pid_random = (bool)!!(reg & SLV_MIPI_ID_VALUE_SLV_PROV_ID_SEL);
+		reg = sys_read32(dev_config->regs + SLV_PID_VALUE);
+		target_config->pid |= reg;
+
+		if (!(sys_read32(dev_config->regs + PRESENT_STATE) &
+		      PRESENT_STATE_CURRENT_MASTER)) {
+			target_config->enabled = true;
+		} else {
+			target_config->enabled = false;
+		}
+#else
+		return -ENOTSUP;
+#endif /* CONFIG_I3C_TARGET */
+	} else {
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Configure I3C hardware.
+ *
+ * @param dev Pointer to controller device driver instance.
+ * @param type Type of configuration parameters being passed
+ *             in @p config.
+ * @param config Pointer to the configuration parameters.
+ *
+ * @retval 0 If successful.
+ * @retval -EINVAL If invalid configure parameters.
+ * @retval -EIO General Input/Output errors.
+ * @retval -ENOSYS If not implemented.
+ */
+static int dw_i3c_configure(const struct device *dev, enum i3c_config_type type, void *config)
+{
+#ifdef CONFIG_I3C_TARGET
+	const struct dw_i3c_config *dev_config = dev->config;
+#endif /* CONFIG_I3C_TARGET */
+
+	if (type == I3C_CONFIG_CONTROLLER) {
+		/* struct i3c_config_controller *ctrl_cfg = config; */
+		/* TODO: somehow determine i3c rate? snps is complicated */
+		return -ENOTSUP;
+	} else if (type == I3C_CONFIG_TARGET) {
+#ifdef CONFIG_I3C_TARGET
+		struct i3c_config_target *target_cfg = config;
+		uint32_t val;
+
+		/* TODO: some how randomly generate pid */
+		if (target_cfg->pid_random) {
+			return -EINVAL;
+		}
+
+		val = SLV_MAX_LEN_MWL(target_cfg->max_write_len) |
+		      (SLV_MAX_LEN_MRL(target_cfg->max_read_len) << 16);
+		sys_write32(val, dev_config->regs + SLV_MAX_LEN);
+
+		/* set static address */
+		val = sys_read32(dev_config->regs + DEVICE_ADDR);
+		/* if static address is set to 0x00, then disable static_addr_en */
+		if (target_cfg->static_addr != 0x00) {
+			val |= DEVICE_ADDR_STATIC_ADDR_VALID;
+		} else {
+			val &= ~DEVICE_ADDR_STATIC_ADDR_VALID;
+		}
+		val &= ~DEVICE_ADDR_STATIC_MASK;
+		val |= DEVICE_ADDR_STATIC(target_cfg->static_addr);
+		sys_write32(val, dev_config->regs + DEVICE_ADDR);
+
+		val = sys_read32(dev_config->regs + SLV_CHAR_CTRL);
+		val &= ~(SLV_CHAR_CTRL_BCR_MASK | SLV_CHAR_CTRL_DCR_MASK);
+		/* Bridge identifier, offline capable, ibi_payload, ibi_request_capable can not be
+		 * written to in bcr
+		 */
+		val |= SLV_CHAR_CTRL_BCR(target_cfg->bcr);
+		val |= SLV_CHAR_CTRL_DCR(target_cfg->dcr) << 8;
+		/* HDR CAPs is not settable */
+		sys_write32(val, dev_config->regs + SLV_CHAR_CTRL);
+
+		val = sys_read32(dev_config->regs + SLV_MIPI_ID_VALUE);
+		val &= ~(SLV_MIPI_ID_VALUE_SLV_MIPI_MFG_ID_MASK |
+			 SLV_MIPI_ID_VALUE_SLV_PROV_ID_SEL);
+		val |= (uint32_t)(target_cfg->pid >> 16);
+		sys_write32(val, dev_config->regs + SLV_MIPI_ID_VALUE);
+
+		val = (uint32_t)(target_cfg->pid & 0xFFFFFFFF);
+		sys_write32(val, dev_config->regs + SLV_PID_VALUE);
+#else
+		return -ENOTSUP;
+#endif /* CONFIG_I3C_TARGET */
+	} else {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+#ifdef CONFIG_I3C_CONTROLLER
+/**
+ * @brief Find a registered I3C target device.
+ *
+ * This returns the I3C device descriptor of the I3C device
+ * matching the incoming @p id.
+ *
+ * @param dev Pointer to controller device driver instance.
+ * @param id Pointer to I3C device ID.
+ *
+ * @return @see i3c_device_find.
+ */
+static struct i3c_device_desc *dw_i3c_device_find(const struct device *dev,
+						  const struct i3c_device_id *id)
+{
+	const struct dw_i3c_config *config = dev->config;
+
+	return i3c_dev_list_find(&config->common.dev_list, id);
+}
+#endif /* CONFIG_I3C_CONTROLLER */
+#ifdef CONFIG_I3C_TARGET
+/**
+ * @brief Writes to the Target's TX FIFO
+ *
+ * The Synopsys I3C will then ACK read requests to it's TX FIFO from a
+ * Controller, if there is no tx cmd in cmd Q. Then it will NACK.
+ *
+ * @param dev Pointer to the device structure for an I3C controller
+ *            driver configured in target mode.
+ * @param buf Pointer to the buffer
+ * @param len Length of the buffer
+ *
+ * @retval Total number of bytes written
+ * @retval -EACCES Not in Target Mode
+ * @retval -ENOSPC No space in Tx FIFO
+ */
+static int dw_i3c_target_tx_write(const struct device *dev, uint8_t *buf, uint16_t len,
+				  uint8_t hdr_mode)
+{
+	const struct dw_i3c_config *config = dev->config;
+	struct dw_i3c_data *data = dev->data;
+	struct dw_i3c_xfer *xfer = &data->xfer;
+	uint32_t present_state;
+
+	/* check if we are in target mode */
+	present_state = sys_read32(config->regs + PRESENT_STATE);
+	if (present_state & PRESENT_STATE_CURRENT_MASTER) {
+		return -EACCES;
+	}
+
+	/*
+	 * TODO: if len is greater than fifo size, then it will need to be written to based
+	 * on the threshold interrupt
+	 */
+	if (len > (data->txfifodepth * BYTES_PER_DWORD)) {
+		return -ENOSPC;
+	}
+
+	k_mutex_lock(&data->mt, K_FOREVER);
+
+	if ((hdr_mode == 0) || (hdr_mode & data->common.ctrl_config.supported_hdr)) {
+		/* Write to CMD */
+		memset(xfer, 0, sizeof(struct dw_i3c_xfer));
+		xfer->ncmds = 1;
+
+		/* TODO: write_tx_fifo needs to check that the fifo doesn't fill up */
+		struct dw_i3c_cmd *cmd = &xfer->cmds[0];
+
+		cmd->cmd_hi = 0;
+		cmd->cmd_lo = COMMAND_PORT_TID(0) | COMMAND_PORT_ARG_DATA_LEN(len);
+		cmd->buf = buf;
+		cmd->tx_len = len;
+
+		start_xfer(dev);
+	} else {
+		k_mutex_unlock(&data->mt);
+		LOG_ERR("%s: Unsupported HDR Mode %d", dev->name, hdr_mode);
+		return -ENOTSUP;
+	}
+
+	k_mutex_unlock(&data->mt);
+
+	/* return total bytes written */
+	return (int)len;
+}
+
+/**
+ * @brief Instructs the I3C Target device to register itself to the I3C Controller
+ *
+ * This routine instructs the I3C Target device to register itself to the I3C
+ * Controller via its parent controller's i3c_target_register() API.
+ *
+ * @param dev Pointer to target device driver instance.
+ * @param cfg Config struct with functions and parameters used by the I3C driver
+ * to send bus events
+ *
+ * @return @see i3c_device_find.
+ */
+static int dw_i3c_target_register(const struct device *dev, struct i3c_target_config *cfg)
+{
+	struct dw_i3c_data *data = dev->data;
+
+	data->target_config = cfg;
+	return 0;
+}
+
+/**
+ * @brief Unregisters the provided config as Target device
+ *
+ * This routine disables I3C target mode for the 'dev' I3C bus driver using
+ * the provided 'config' struct containing the functions and parameters
+ * to send bus events.
+ *
+ * @param dev Pointer to target device driver instance.
+ * @param cfg Config struct with functions and parameters used by the I3C driver
+ * to send bus events
+ *
+ * @return @see i3c_device_find.
+ */
+static int dw_i3c_target_unregister(const struct device *dev, struct i3c_target_config *cfg)
+{
+	/* no way to disable? maybe write DA to 0? */
+	return 0;
+}
+#endif /* CONFIG_I3C_TARGET */
+
+static int dw_i3c_pinctrl_enable(const struct device *dev, bool enable)
+{
+#ifdef CONFIG_PINCTRL
+	const struct dw_i3c_config *config = dev->config;
+	uint8_t state = enable ? PINCTRL_STATE_DEFAULT : PINCTRL_STATE_SLEEP;
+	int ret;
+
+	ret = pinctrl_apply_state(config->pcfg, state);
+	if (ret == -ENOENT) {
+		/* State not defined; ignore and return success. */
+		ret = 0;
+	}
+
+	return ret;
+#else
+	ARG_UNUSED(dev);
+	ARG_UNUSED(enable);
+	return 0;
+#endif
+}
+
+static int dw_i3c_init(const struct device *dev)
+{
+	const struct dw_i3c_config *config = dev->config;
+	struct dw_i3c_data *data = dev->data;
+	struct i3c_config_controller *ctrl_config = &data->common.ctrl_config;
+	int ret;
+	uint32_t hw_capabilities;
+	uint32_t queue_capability;
+	uint32_t device_ctrl_ext;
+
+	if (!device_is_ready(config->clock)) {
+		return -ENODEV;
+	}
+
+	ret = clock_control_on(config->clock, NULL);
+	if (ret < 0) {
+		return ret;
+	}
+
+#ifdef CONFIG_I3C_USE_IBI
+	k_sem_init(&data->ibi_sts_sem, 0, 1);
+#endif /* CONFIG_I3C_USE_IBI */
+	k_sem_init(&data->sem_xfer, 0, 1);
+	k_mutex_init(&data->mt);
+
+	dw_i3c_pinctrl_enable(dev, true);
+#ifdef CONFIG_I3C_CONTROLLER
+	data->mode = i3c_bus_mode(&config->common.dev_list);
+#endif /* CONFIG_I3C_CONTROLLER */
+	/* reset all */
+	sys_write32(RESET_CTRL_ALL, config->regs + RESET_CTRL);
+
+	/* get DAT, DCT pointer */
+	data->datstartaddr =
+		DEVICE_ADDR_TABLE_ADDR(sys_read32(config->regs + DEVICE_ADDR_TABLE_POINTER));
+	data->dctstartaddr =
+		DEVICE_CHAR_TABLE_ADDR(sys_read32(config->regs + DEV_CHAR_TABLE_POINTER));
+
+	/* get max devices based on table depth */
+	data->maxdevs =
+		DEVICE_ADDR_TABLE_DEPTH(sys_read32(config->regs + DEVICE_ADDR_TABLE_POINTER));
+	data->free_pos = GENMASK(data->maxdevs - 1, 0);
+
+	/* get fifo sizes */
+	queue_capability = sys_read32(config->regs + QUEUE_SIZE_CAPABILITY);
+	data->txfifodepth = QUEUE_SIZE_CAPABILITY_TX_BUF_DWORD_SIZE(queue_capability);
+	data->rxfifodepth = QUEUE_SIZE_CAPABILITY_RX_BUF_DWORD_SIZE(queue_capability);
+	data->cmdfifodepth = QUEUE_SIZE_CAPABILITY_CMD_BUF_DWORD_SIZE(queue_capability);
+	data->respfifodepth = QUEUE_SIZE_CAPABILITY_RESP_BUF_DWORD_SIZE(queue_capability);
+	data->ibififodepth = QUEUE_SIZE_CAPABILITY_IBI_BUF_DWORD_SIZE(queue_capability);
+
+	/* get HDR capabilities */
+	ctrl_config->supported_hdr = 0;
+	hw_capabilities = sys_read32(config->regs + HW_CAPABILITY);
+	if (hw_capabilities & HW_CAPABILITY_HDR_TS_EN) {
+		ctrl_config->supported_hdr |= I3C_MSG_HDR_TSP | I3C_MSG_HDR_TSL;
+	}
+	if (hw_capabilities & HW_CAPABILITY_HDR_DDR_EN) {
+		ctrl_config->supported_hdr |= I3C_MSG_HDR_DDR;
+	}
+
+	/* if the boot condition starts as a target, then it's a secondary controller */
+	device_ctrl_ext = sys_read32(config->regs + DEVICE_CTRL_EXTENDED);
+	if (DEVICE_CTRL_EXTENDED_DEV_OPERATION_MODE(device_ctrl_ext) &
+	    DEVICE_CTRL_EXTENDED_DEV_OPERATION_MODE_SLAVE) {
+		ctrl_config->is_secondary = true;
+	} else {
+		ctrl_config->is_secondary = false;
+	}
+	/*
+	 * Ensure that is_secondary is only set when CONFIG_I3C_TARGET is enabled,
+	 * or ensure that it is false when CONFIG_I3C_CONTROLLER is enabled.
+	 */
+	__ASSERT_NO_MSG((IS_ENABLED(CONFIG_I3C_TARGET) && ctrl_config->is_secondary) ||
+			(IS_ENABLED(CONFIG_I3C_CONTROLLER) && !ctrl_config->is_secondary));
+
+	ret = init_scl_timing(dev);
+	if (ret != 0) {
+		return ret;
+	}
+
+	enable_interrupts(dev);
+
+	/* disable ibi */
+	sys_write32(IBI_REQ_REJECT_ALL, config->regs + IBI_SIR_REQ_REJECT);
+	sys_write32(IBI_REQ_REJECT_ALL, config->regs + IBI_MR_REQ_REJECT);
+
+	/* disable hot-join */
+	sys_write32(sys_read32(config->regs + DEVICE_CTRL) | (DEV_CTRL_HOT_JOIN_NACK),
+		    config->regs + DEVICE_CTRL);
+#ifdef CONFIG_I3C_CONTROLLER
+	ret = i3c_addr_slots_init(dev);
+	if (ret != 0) {
+		return ret;
+	}
+#endif /* CONFIG_I3C_CONTROLLER */
+	dw_i3c_enable_controller(config, true);
+#ifdef CONFIG_I3C_CONTROLLER
+	if (!(ctrl_config->is_secondary)) {
+		ret = set_controller_info(dev);
+		if (ret) {
+			return ret;
+		}
+		/* Perform bus initialization - skip if no I3C devices are known. */
+		if (config->common.dev_list.num_i3c > 0) {
+			ret = i3c_bus_init(dev, &config->common.dev_list);
+		}
+		/* Bus Initialization Complete, allow HJ ACKs */
+		sys_write32(sys_read32(config->regs + DEVICE_CTRL) & ~(DEV_CTRL_HOT_JOIN_NACK),
+			    config->regs + DEVICE_CTRL);
+	}
+#endif /* CONFIG_I3C_CONTROLLER */
+
+	return 0;
+}
+
+#if defined(CONFIG_PM_DEVICE)
+static int dw_i3c_pm_ctrl(const struct device *dev, enum pm_device_action action)
+{
+	const struct dw_i3c_config *config = dev->config;
+
+	LOG_DBG("PM action: %d", (int)action);
+
+	switch (action) {
+	case PM_DEVICE_ACTION_SUSPEND:
+		dw_i3c_enable_controller(config, false);
+		dw_i3c_pinctrl_enable(dev, false);
+		break;
+
+	case PM_DEVICE_ACTION_RESUME:
+		dw_i3c_pinctrl_enable(dev, true);
+		dw_i3c_enable_controller(config, true);
+		break;
+
+	default:
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+#endif
+
+static DEVICE_API(i3c, dw_i3c_api) = {
+#ifdef CONFIG_I3C_CONTROLLER
+	.i2c_api.transfer = dw_i3c_i2c_api_transfer,
+#ifdef CONFIG_I2C_RTIO
+	.i2c_api.iodev_submit = i2c_iodev_submit_fallback,
+#endif
+#endif /* CONFIG_I3C_CONTROLLER */
+
+	.configure = dw_i3c_configure,
+	.config_get = dw_i3c_config_get,
+#ifdef CONFIG_I3C_CONTROLLER
+	.attach_i3c_device = dw_i3c_attach_device,
+	.reattach_i3c_device = dw_i3c_reattach_device,
+	.detach_i3c_device = dw_i3c_detach_device,
+
+	.do_daa = dw_i3c_do_daa,
+	.do_ccc = dw_i3c_do_ccc,
+
+	.i3c_device_find = dw_i3c_device_find,
+
+	.i3c_xfers = dw_i3c_xfers,
+#endif /* CONFIG_I3C_CONTROLLER */
+#ifdef CONFIG_I3C_TARGET
+	.target_tx_write = dw_i3c_target_tx_write,
+	.target_register = dw_i3c_target_register,
+	.target_unregister = dw_i3c_target_unregister,
+#endif /* CONFIG_I3C_TARGET */
+#ifdef CONFIG_I3C_USE_IBI
+#ifdef CONFIG_I3C_CONTROLLER
+	.ibi_hj_response = dw_i3c_controller_ibi_hj_response,
+	.ibi_enable = dw_i3c_controller_enable_ibi,
+	.ibi_disable = dw_i3c_controller_disable_ibi,
+#endif /* CONFIG_I3C_CONTROLLER */
+#ifdef CONFIG_I3C_TARGET
+	.ibi_raise = dw_i3c_target_ibi_raise,
+#endif /* CONFIG_I3C_TARGET */
+#endif /* CONFIG_I3C_USE_IBI */
+
+#ifdef CONFIG_I3C_RTIO
+	.iodev_submit = i3c_iodev_submit_fallback,
+#endif
+};
+
+#define I3C_DW_IRQ_HANDLER(n)                                                                      \
+	static void i3c_dw_irq_config_##n(void)                                                    \
+	{                                                                                          \
+		IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), i3c_dw_irq,                 \
+			    DEVICE_DT_INST_GET(n), 0);                                             \
+		irq_enable(DT_INST_IRQN(n));                                                       \
+	}
+
+#if defined(CONFIG_PINCTRL)
+#define I3C_DW_PINCTRL_DEFINE(n) PINCTRL_DT_INST_DEFINE(n)
+#define I3C_DW_PINCTRL_INIT(n)   .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),
+#else
+#define I3C_DW_PINCTRL_DEFINE(n)
+#define I3C_DW_PINCTRL_INIT(n)
+#endif
+
+#define DEFINE_DEVICE_FN(n)                                                                        \
+	I3C_DW_IRQ_HANDLER(n)                                                                      \
+	I3C_DW_PINCTRL_DEFINE(n);                                                                  \
+	IF_ENABLED(CONFIG_I3C_CONTROLLER,                                                          \
+		   (static struct i3c_device_desc dw_i3c_device_array_##n[] =                      \
+			    I3C_DEVICE_ARRAY_DT_INST(n);                                           \
+		    static struct i3c_i2c_device_desc dw_i3c_i2c_device_array_##n[] =              \
+			    I3C_I2C_DEVICE_ARRAY_DT_INST(n);))                                     \
+	static struct dw_i3c_data dw_i3c_data_##n = {                                              \
+		.common.ctrl_config.scl.i3c =                                                      \
+			DT_INST_PROP_OR(n, i3c_scl_hz, I3C_BUS_TYP_I3C_SCL_RATE),                  \
+		.common.ctrl_config.scl.i2c = DT_INST_PROP_OR(n, i2c_scl_hz, 0),                   \
+	};                                                                                         \
+	static const struct dw_i3c_config dw_i3c_cfg_##n = {                                       \
+		.regs = DT_INST_REG_ADDR(n),                                                       \
+		.clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),                                    \
+		.od_thigh_max_ns = DT_INST_PROP(n, od_thigh_max_ns),                               \
+		.od_tlow_min_ns = DT_INST_PROP(n, od_tlow_min_ns),                                 \
+		.irq_config_func = &i3c_dw_irq_config_##n,                                         \
+		IF_ENABLED(CONFIG_I3C_CONTROLLER,                                                  \
+			(.common.dev_list.i3c = dw_i3c_device_array_##n,                           \
+			.common.dev_list.num_i3c = ARRAY_SIZE(dw_i3c_device_array_##n),            \
+			.common.dev_list.i2c = dw_i3c_i2c_device_array_##n,                        \
+			.common.dev_list.num_i2c = ARRAY_SIZE(dw_i3c_i2c_device_array_##n),        \
+			.common.primary_controller_da = DT_INST_PROP_OR(n, primary_controller_da, 0x00),)) \
+		I3C_DW_PINCTRL_INIT(n)};                                                           \
+	PM_DEVICE_DT_INST_DEFINE(n, dw_i3c_pm_action);                                             \
+	DEVICE_DT_INST_DEFINE(n, dw_i3c_init, PM_DEVICE_DT_INST_GET(n), &dw_i3c_data_##n,          \
+			      &dw_i3c_cfg_##n, POST_KERNEL, CONFIG_I3C_CONTROLLER_INIT_PRIORITY,   \
+			      &dw_i3c_api);
+
+#define DT_DRV_COMPAT snps_designware_i3c
+DT_INST_FOREACH_STATUS_OKAY(DEFINE_DEVICE_FN);
diff --git a/drivers/i3c/i3c_i2c_mem_slab.c b/drivers/i3c/i3c_i2c_mem_slab.c
new file mode 100644
index 00000000000..472d39df76f
--- /dev/null
+++ b/drivers/i3c/i3c_i2c_mem_slab.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2024 Meta Platforms
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include <stdlib.h>
+
+#include <zephyr/drivers/i3c.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(i3c, CONFIG_I3C_LOG_LEVEL);
+
+K_MEM_SLAB_DEFINE(i3c_i2c_device_desc_pool, sizeof(struct i3c_i2c_device_desc),
+	CONFIG_I3C_I2C_NUM_OF_DESC_MEM_SLABS, 4);
+
+struct i3c_i2c_device_desc *i3c_i2c_device_desc_alloc(void)
+{
+	struct i3c_i2c_device_desc *desc;
+
+	if (k_mem_slab_alloc(&i3c_i2c_device_desc_pool, (void **)&desc, K_NO_WAIT) == 0) {
+		memset(desc, 0, sizeof(struct i3c_i2c_device_desc));
+		LOG_INF("I2C Device Desc allocated - %d free",
+			k_mem_slab_num_free_get(&i3c_i2c_device_desc_pool));
+	} else {
+		LOG_WRN("No memory left for I2C descriptors");
+	}
+
+	return desc;
+}
+
+void i3c_i2c_device_desc_free(struct i3c_i2c_device_desc *desc)
+{
+	k_mem_slab_free(&i3c_i2c_device_desc_pool, (void *)desc);
+	LOG_DBG("I2C Device Desc freed");
+}
+
+bool i3c_i2c_device_desc_in_pool(struct i3c_i2c_device_desc *desc)
+{
+	const char *p =  (const char *)desc;
+	ptrdiff_t offset = p - i3c_i2c_device_desc_pool.buffer;
+
+	return (offset >= 0) &&
+	       (offset < (i3c_i2c_device_desc_pool.info.block_size *
+		   i3c_i2c_device_desc_pool.info.num_blocks)) &&
+	       ((offset % i3c_i2c_device_desc_pool.info.block_size) == 0);
+}
diff --git a/drivers/i3c/i3c_ibi_workq.c b/drivers/i3c/i3c_ibi_workq.c
index 108f20f44e5..b0b2088626b 100644
--- a/drivers/i3c/i3c_ibi_workq.c
+++ b/drivers/i3c/i3c_ibi_workq.c
@@ -86,6 +86,32 @@ int i3c_ibi_work_enqueue_target_irq(struct i3c_device_desc *target,
 	return ret;
 }
 
+int i3c_ibi_work_enqueue_controller_request(struct i3c_device_desc *target)
+{
+	sys_snode_t *node;
+	struct i3c_ibi_work *ibi_node;
+	int ret;
+
+	node = sys_slist_get(&i3c_ibi_work_nodes_free);
+	if (node == NULL) {
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	ibi_node = (struct i3c_ibi_work *)node;
+
+	ibi_node->type = I3C_IBI_CONTROLLER_ROLE_REQUEST;
+	ibi_node->target = target;
+
+	ret = ibi_work_submit(ibi_node);
+	if (ret >= 0) {
+		ret = 0;
+	}
+
+out:
+	return ret;
+}
+
 int i3c_ibi_work_enqueue_hotjoin(const struct device *dev)
 {
 	sys_snode_t *node;
@@ -167,9 +193,13 @@ static void i3c_ibi_work_handler(struct k_work *work)
 			payload = NULL;
 		}
 
-		ret = ibi_node->target->ibi_cb(ibi_node->target, payload);
-		if ((ret != 0) && (ret != -EBUSY)) {
-			LOG_ERR("IBI work %p cb returns %d", ibi_node, ret);
+		if (ibi_node->target->ibi_cb) {
+			ret = ibi_node->target->ibi_cb(ibi_node->target, payload);
+			if ((ret != 0) && (ret != -EBUSY)) {
+				LOG_ERR("IBI work %p cb returns %d", ibi_node, ret);
+			}
+		} else {
+			LOG_ERR("No IBI callback for target %s", ibi_node->target->dev->name);
 		}
 		break;
 
@@ -178,13 +208,14 @@ static void i3c_ibi_work_handler(struct k_work *work)
 		if ((ret != 0) && (ret != -EBUSY)) {
 			LOG_ERR("i3c_do_daa returns %d", ret);
 		}
-
+#ifdef CONFIG_I3C_TARGET
 		if (i3c_bus_has_sec_controller(ibi_node->controller)) {
 			ret = i3c_bus_deftgts(ibi_node->controller);
 			if (ret != 0) {
 				LOG_ERR("Error sending DEFTGTS");
 			}
 		}
+#endif /* CONFIG_I3C_TARGET */
 		break;
 
 	case I3C_IBI_WORKQUEUE_CB:
@@ -194,8 +225,13 @@ static void i3c_ibi_work_handler(struct k_work *work)
 		break;
 
 	case I3C_IBI_CONTROLLER_ROLE_REQUEST:
-		/* TODO: Add support for controller role request */
-		__fallthrough;
+#ifdef CONFIG_I3C_TARGET
+		ret = i3c_device_controller_handoff(ibi_node->target, true);
+		if (ret != 0) {
+			LOG_ERR("i3c_device_controller_handoff returns %d", ret);
+		}
+#endif /* CONFIG_I3C_TARGET */
+		break;
 
 	default:
 		/* Unknown IBI type: do nothing */
diff --git a/drivers/i3c/i3c_mem_slab.c b/drivers/i3c/i3c_mem_slab.c
new file mode 100644
index 00000000000..2c80aa58418
--- /dev/null
+++ b/drivers/i3c/i3c_mem_slab.c
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2024 Meta Platforms
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include <stdlib.h>
+
+#include <zephyr/drivers/i3c.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(i3c, CONFIG_I3C_LOG_LEVEL);
+
+/* Generate Names */
+#define UNKNOWN_NAME_STR(i, _)                                                                     \
+	{                                                                                          \
+		.name = "unknown-" STRINGIFY(i)                                                    \
+	}
+const struct device dummy_devs[] = {
+	LISTIFY(CONFIG_I3C_NUM_OF_DESC_MEM_SLABS, UNKNOWN_NAME_STR, (,)) };
+
+K_MEM_SLAB_DEFINE(i3c_device_desc_pool, sizeof(struct i3c_device_desc),
+		  CONFIG_I3C_NUM_OF_DESC_MEM_SLABS, 4);
+
+struct i3c_device_desc *i3c_device_desc_alloc(void)
+{
+	struct i3c_device_desc *desc;
+
+	if (k_mem_slab_alloc(&i3c_device_desc_pool, (void **)&desc, K_NO_WAIT) == 0) {
+		memset(desc, 0, sizeof(struct i3c_device_desc));
+		*(const struct device **)&desc->dev =
+			&dummy_devs[k_mem_slab_num_free_get(&i3c_device_desc_pool)];
+		LOG_DBG("I3C Device Desc allocated - %d free",
+			k_mem_slab_num_free_get(&i3c_device_desc_pool));
+	} else {
+		LOG_WRN("No memory left for I3C descriptors");
+	}
+
+	return desc;
+}
+
+void i3c_device_desc_free(struct i3c_device_desc *desc)
+{
+	k_mem_slab_free(&i3c_device_desc_pool, (void *)desc);
+	LOG_DBG("I3C Device Desc freed");
+}
+
+bool i3c_device_desc_in_pool(struct i3c_device_desc *desc)
+{
+	const char *p = (const char *)desc;
+	ptrdiff_t offset = p - i3c_device_desc_pool.buffer;
+
+	return (offset >= 0) &&
+	       (offset < (i3c_device_desc_pool.info.block_size *
+		   i3c_device_desc_pool.info.num_blocks)) &&
+	       ((offset % i3c_device_desc_pool.info.block_size) == 0);
+}
diff --git a/drivers/i3c/i3c_shell.c b/drivers/i3c/i3c_shell.c
index cd651a81d3d..7a37919016c 100644
--- a/drivers/i3c/i3c_shell.c
+++ b/drivers/i3c/i3c_shell.c
@@ -24,10 +24,12 @@ LOG_MODULE_REGISTER(i3c_shell, CONFIG_LOG_DEFAULT_LEVEL);
 
 struct i3c_ctrl {
 	const struct device *dev;
+#ifdef CONFIG_I3C_CONTROLLER
 	const union shell_cmd_entry *i3c_attached_dev_subcmd;
 	const union shell_cmd_entry *i3c_list_dev_subcmd;
+#endif
 };
-
+#ifdef CONFIG_I3C_CONTROLLER
 #define I3C_ATTACHED_DEV_GET_FN(node_id)                                                           \
 	static void node_id##cmd_i3c_attached_get(size_t idx, struct shell_static_entry *entry);   \
                                                                                                    \
@@ -82,14 +84,16 @@ struct i3c_ctrl {
 DT_FOREACH_STATUS_OKAY(cdns_i3c, I3C_CTRL_FN)
 DT_FOREACH_STATUS_OKAY(nuvoton_npcx_i3c, I3C_CTRL_FN)
 DT_FOREACH_STATUS_OKAY(nxp_mcux_i3c, I3C_CTRL_FN)
+DT_FOREACH_STATUS_OKAY(snps_designware_i3c, I3C_CTRL_FN)
 DT_FOREACH_STATUS_OKAY(st_stm32_i3c, I3C_CTRL_FN)
 /* zephyr-keep-sorted-stop */
-
+#endif /* CONFIG_I3C_CONTROLLER */
 #define I3C_CTRL_LIST_ENTRY(node_id)                                                               \
 	{                                                                                          \
 		.dev = DEVICE_DT_GET(node_id),                                                     \
-		.i3c_attached_dev_subcmd = &node_id##sub_i3c_attached,                             \
-		.i3c_list_dev_subcmd = &node_id##sub_i3c_list,                                     \
+		IF_ENABLED(CONFIG_I3C_CONTROLLER,                                                  \
+			   (.i3c_attached_dev_subcmd = &node_id##sub_i3c_attached,                 \
+			    .i3c_list_dev_subcmd = &node_id##sub_i3c_list,))                       \
 	},
 
 const struct i3c_ctrl i3c_list[] = {
@@ -97,10 +101,11 @@ const struct i3c_ctrl i3c_list[] = {
 	DT_FOREACH_STATUS_OKAY(cdns_i3c, I3C_CTRL_LIST_ENTRY)
 	DT_FOREACH_STATUS_OKAY(nuvoton_npcx_i3c, I3C_CTRL_LIST_ENTRY)
 	DT_FOREACH_STATUS_OKAY(nxp_mcux_i3c, I3C_CTRL_LIST_ENTRY)
+	DT_FOREACH_STATUS_OKAY(snps_designware_i3c, I3C_CTRL_LIST_ENTRY)
 	DT_FOREACH_STATUS_OKAY(st_stm32_i3c, I3C_CTRL_LIST_ENTRY)
 	/* zephyr-keep-sorted-stop */
 };
-
+#ifdef CONFIG_I3C_CONTROLLER
 static int get_bytes_count_for_hex(char *arg)
 {
 	int length = (strlen(arg) + 1) / 2;
@@ -198,9 +203,6 @@ static int cmd_i3c_info(const struct shell *sh, size_t argc, char **argv)
 						    "\tpid: 0x%012llx\n"
 						    "\tstatic_addr: 0x%02x\n"
 						    "\tdynamic_addr: 0x%02x\n"
-#if defined(CONFIG_I3C_USE_GROUP_ADDR)
-						    "\tgroup_addr: 0x%02x\n"
-#endif
 						    "\tbcr: 0x%02x\n"
 						    "\tdcr: 0x%02x\n"
 						    "\tmaxrd: 0x%02x\n"
@@ -209,19 +211,19 @@ static int cmd_i3c_info(const struct shell *sh, size_t argc, char **argv)
 						    "\tmrl: 0x%04x\n"
 						    "\tmwl: 0x%04x\n"
 						    "\tmax_ibi: 0x%02x\n"
-						    "\tgetcaps: 0x%02x; 0x%02x; 0x%02x; 0x%02x",
+						    "\tcrhdly1: 0x%02x\n"
+						    "\tgetcaps: 0x%02x; 0x%02x; 0x%02x; 0x%02x\n"
+						    "\tcrcaps: 0x%02x; 0x%02x",
 						    desc->dev->name, (uint64_t)desc->pid,
 						    desc->static_addr, desc->dynamic_addr,
-#if defined(CONFIG_I3C_USE_GROUP_ADDR)
-						    desc->group_addr,
-#endif
 						    desc->bcr, desc->dcr, desc->data_speed.maxrd,
 						    desc->data_speed.maxwr,
 						    desc->data_speed.max_read_turnaround,
 						    desc->data_length.mrl, desc->data_length.mwl,
-						    desc->data_length.max_ibi,
+						    desc->data_length.max_ibi, desc->crhdly1,
 						    desc->getcaps.getcap1, desc->getcaps.getcap2,
-						    desc->getcaps.getcap3, desc->getcaps.getcap4);
+						    desc->getcaps.getcap3, desc->getcaps.getcap4,
+						    desc->crcaps.crcaps1, desc->crcaps.crcaps2);
 					found = true;
 					break;
 				}
@@ -244,9 +246,6 @@ static int cmd_i3c_info(const struct shell *sh, size_t argc, char **argv)
 					    "\tpid: 0x%012llx\n"
 					    "\tstatic_addr: 0x%02x\n"
 					    "\tdynamic_addr: 0x%02x\n"
-#if defined(CONFIG_I3C_USE_GROUP_ADDR)
-					    "\tgroup_addr: 0x%02x\n"
-#endif
 					    "\tbcr: 0x%02x\n"
 					    "\tdcr: 0x%02x\n"
 					    "\tmaxrd: 0x%02x\n"
@@ -255,19 +254,19 @@ static int cmd_i3c_info(const struct shell *sh, size_t argc, char **argv)
 					    "\tmrl: 0x%04x\n"
 					    "\tmwl: 0x%04x\n"
 					    "\tmax_ibi: 0x%02x\n"
-					    "\tgetcaps: 0x%02x; 0x%02x; 0x%02x; 0x%02x",
+					    "\tcrhdly1: 0x%02x\n"
+					    "\tgetcaps: 0x%02x; 0x%02x; 0x%02x; 0x%02x\n"
+					    "\tcrcaps: 0x%02x; 0x%02x",
 					    desc->dev->name, (uint64_t)desc->pid, desc->static_addr,
 					    desc->dynamic_addr,
-#if defined(CONFIG_I3C_USE_GROUP_ADDR)
-					    desc->group_addr,
-#endif
 					    desc->bcr, desc->dcr, desc->data_speed.maxrd,
 					    desc->data_speed.maxwr,
 					    desc->data_speed.max_read_turnaround,
 					    desc->data_length.mrl, desc->data_length.mwl,
-					    desc->data_length.max_ibi, desc->getcaps.getcap1,
-					    desc->getcaps.getcap2, desc->getcaps.getcap3,
-					    desc->getcaps.getcap4);
+					    desc->data_length.max_ibi, desc->crhdly1,
+					    desc->getcaps.getcap1, desc->getcaps.getcap2,
+					    desc->getcaps.getcap3, desc->getcaps.getcap4,
+					    desc->crcaps.crcaps1, desc->crcaps.crcaps2);
 			}
 		} else {
 			shell_print(sh, "I3C: No devices found.");
@@ -567,6 +566,36 @@ static int cmd_i3c_hdr_ddr_read(const struct shell *sh, size_t argc, char **argv
 	return ret;
 }
 
+/* i3c ccc rstdaa_dc <device> <target> */
+static int cmd_i3c_ccc_rstdaa_dc(const struct shell *sh, size_t argc, char **argv)
+{
+	const struct device *dev, *tdev;
+	struct i3c_device_desc *desc;
+	int ret;
+
+	ret = i3c_parse_args(sh, argv, &dev, &tdev, &desc);
+	if (ret != 0) {
+		return ret;
+	}
+
+	if (!(desc->flags & I3C_V1P0_SUPPORT)) {
+		shell_error(sh, "I3C: %s does not support RSTDAA_DC.", tdev->name);
+		return -ENOTSUP;
+	}
+
+	ret = i3c_ccc_do_rstdaa(desc);
+	if (ret < 0) {
+		shell_error(sh, "I3C: unable to send CCC RSTDAA.");
+		return ret;
+	}
+
+	/* reset device DA */
+	desc->dynamic_addr = 0;
+	shell_print(sh, "Reset dynamic address for device %s", desc->dev->name);
+
+	return ret;
+}
+
 /* i3c ccc rstdaa <device> */
 static int cmd_i3c_ccc_rstdaa(const struct shell *sh, size_t argc, char **argv)
 {
@@ -630,7 +659,7 @@ static int cmd_i3c_ccc_setaasa(const struct shell *sh, size_t argc, char **argv)
 
 	/* set all devices DA to SA */
 	I3C_BUS_FOR_EACH_I3CDEV(dev, desc) {
-		if ((desc->supports_setaasa) && (desc->dynamic_addr == 0) &&
+		if (((desc->flags) & I3C_SUPPORTS_SETAASA) && (desc->dynamic_addr == 0) &&
 		    (desc->static_addr != 0)) {
 			desc->dynamic_addr = desc->static_addr;
 		}
@@ -967,7 +996,7 @@ static int cmd_i3c_ccc_setmwl_bc(const struct shell *sh, size_t argc, char **arg
 		return -ENODEV;
 	}
 
-	mwl.len = strtol(argv[3], NULL, 16);
+	mwl.len = strtol(argv[2], NULL, 16);
 
 	ret = i3c_ccc_do_setmwl_all(dev, &mwl);
 	if (ret < 0) {
@@ -981,7 +1010,7 @@ static int cmd_i3c_ccc_setmwl_bc(const struct shell *sh, size_t argc, char **arg
 
 	return ret;
 }
-
+#ifdef CONFIG_I3C_TARGET
 /* i3c ccc deftgts <device> */
 static int cmd_i3c_ccc_deftgts(const struct shell *sh, size_t argc, char **argv)
 {
@@ -1007,7 +1036,7 @@ static int cmd_i3c_ccc_deftgts(const struct shell *sh, size_t argc, char **argv)
 
 	return ret;
 }
-
+#endif /* CONFIG_I3C_TARGET */
 /* i3c ccc enttm <device> <defining byte> */
 static int cmd_i3c_ccc_enttm(const struct shell *sh, size_t argc, char **argv)
 {
@@ -1031,7 +1060,44 @@ static int cmd_i3c_ccc_enttm(const struct shell *sh, size_t argc, char **argv)
 
 	return ret;
 }
+#ifdef CONFIG_I3C_TARGET
+/* i3c ccc getacccr <device> <target> */
+static int cmd_i3c_ccc_getacccr(const struct shell *sh, size_t argc, char **argv)
+{
+	const struct device *dev, *tdev;
+	struct i3c_device_desc *desc;
+	struct i3c_ccc_address handoff_address;
+	int ret;
 
+	ret = i3c_parse_args(sh, argv, &dev, &tdev, &desc);
+	if (ret != 0) {
+		return ret;
+	}
+
+	if (!i3c_device_is_controller_capable(desc)) {
+		shell_error(sh, "I3C: Not a Controller Capable Device");
+		return -EINVAL;
+	}
+
+	ret = i3c_ccc_do_getacccr(desc, &handoff_address);
+	if (ret < 0) {
+		shell_error(sh, "I3C: unable to send CCC GETACCCR.");
+		return ret;
+	}
+
+	/* Verify Odd Parity and Correct Dynamic Address Reply */
+	if ((i3c_odd_parity(handoff_address.addr >> 1) != (handoff_address.addr & BIT(0))) ||
+	    (handoff_address.addr >> 1 != desc->dynamic_addr)) {
+		shell_error(sh, "I3C: invalid returned address 0x%02x; expected 0x%02x",
+			    handoff_address.addr, desc->dynamic_addr);
+		return -EIO;
+	}
+
+	shell_print(sh, "I3C: Controller Handoff successful");
+
+	return ret;
+}
+#endif /* CONFIG_I3C_TARGET */
 /* i3c ccc rstact_bc <device> <defining byte> */
 static int cmd_i3c_ccc_rstact_bc(const struct shell *sh, size_t argc, char **argv)
 {
@@ -1385,7 +1451,7 @@ static int cmd_i3c_ccc_getstatus(const struct shell *sh, size_t argc, char **arg
 	if (argc > 3) {
 		fmt = GETSTATUS_FORMAT_2;
 		defbyte = strtol(argv[3], NULL, 16);
-		if (defbyte != GETSTATUS_FORMAT_2_TGTSTAT || defbyte != GETSTATUS_FORMAT_2_PRECR) {
+		if (defbyte != GETSTATUS_FORMAT_2_TGTSTAT && defbyte != GETSTATUS_FORMAT_2_PRECR) {
 			shell_error(sh, "Invalid defining byte.");
 			return -EINVAL;
 		}
@@ -1431,8 +1497,8 @@ static int cmd_i3c_ccc_getcaps(const struct shell *sh, size_t argc, char **argv)
 	if (argc > 3) {
 		fmt = GETCAPS_FORMAT_2;
 		defbyte = strtol(argv[3], NULL, 16);
-		if (defbyte != GETCAPS_FORMAT_2_TGTCAPS || defbyte != GETCAPS_FORMAT_2_TESTPAT ||
-		    defbyte != GETCAPS_FORMAT_2_CRCAPS || defbyte != GETCAPS_FORMAT_2_VTCAPS ||
+		if (defbyte != GETCAPS_FORMAT_2_TGTCAPS && defbyte != GETCAPS_FORMAT_2_TESTPAT &&
+		    defbyte != GETCAPS_FORMAT_2_CRCAPS && defbyte != GETCAPS_FORMAT_2_VTCAPS &&
 		    defbyte != GETCAPS_FORMAT_2_DBGCAPS) {
 			shell_error(sh, "Invalid defining byte.");
 			return -EINVAL;
@@ -1457,6 +1523,7 @@ static int cmd_i3c_ccc_getcaps(const struct shell *sh, size_t argc, char **argv)
 		} else if (defbyte == GETCAPS_FORMAT_2_CRCAPS) {
 			shell_print(sh, "CRCAPS: 0x%02x; 0x%02x", caps.fmt2.crcaps[0],
 				    caps.fmt2.crcaps[1]);
+			memcpy(&desc->crcaps, &caps, sizeof(desc->crcaps));
 		} else if (defbyte == GETCAPS_FORMAT_2_VTCAPS) {
 			shell_print(sh, "VTCAPS: 0x%02x; 0x%02x", caps.fmt2.vtcaps[0],
 				    caps.fmt2.vtcaps[1]);
@@ -1665,7 +1732,7 @@ static int cmd_i3c_ccc_getmxds(const struct shell *sh, size_t argc, char **argv)
 	if (argc > 3) {
 		fmt = GETMXDS_FORMAT_3;
 		defbyte = strtol(argv[3], NULL, 16);
-		if (defbyte != GETMXDS_FORMAT_3_CRHDLY || defbyte != GETMXDS_FORMAT_3_WRRDTURN) {
+		if (defbyte != GETMXDS_FORMAT_3_CRHDLY && defbyte != GETMXDS_FORMAT_3_WRRDTURN) {
 			shell_error(sh, "Invalid defining byte.");
 			return -EINVAL;
 		}
@@ -1690,6 +1757,7 @@ static int cmd_i3c_ccc_getmxds(const struct shell *sh, size_t argc, char **argv)
 			desc->data_speed.max_read_turnaround = sys_get_le24(&mxds.fmt3.wrrdturn[2]);
 		} else if (defbyte == GETMXDS_FORMAT_3_CRHDLY) {
 			shell_print(sh, "CRHDLY1: 0x%02x", mxds.fmt3.crhdly1);
+			desc->crhdly1 = mxds.fmt3.crhdly1;
 		}
 	} else {
 		shell_print(sh, "GETMXDS: maxwr 0x%02x; maxrd 0x%02x; maxrdturn 0x%06x",
@@ -1927,8 +1995,9 @@ static int cmd_i3c_i2c_scan(const struct shell *sh, size_t argc, char **argv)
 
 	return 0;
 }
-
+#endif /* CONFIG_I3C_CONTROLLER */
 #ifdef CONFIG_I3C_USE_IBI
+#ifdef CONFIG_I3C_CONTROLLER
 /* i3c ibi hj_response <device> <"ack"/"nack"> */
 static int cmd_i3c_ibi_hj_response(const struct shell *sh, size_t argc, char **argv)
 {
@@ -1961,7 +2030,8 @@ static int cmd_i3c_ibi_hj_response(const struct shell *sh, size_t argc, char **a
 
 	return 0;
 }
-
+#endif /* CONFIG_I3C_CONTROLLER */
+#ifdef CONFIG_I3C_TARGET
 /* i3c ibi hj <device> */
 static int cmd_i3c_ibi_hj(const struct shell *sh, size_t argc, char **argv)
 {
@@ -1986,7 +2056,7 @@ static int cmd_i3c_ibi_hj(const struct shell *sh, size_t argc, char **argv)
 
 	return 0;
 }
-
+#ifdef CONFIG_I3C_CONTROLLER
 /* i3c ibi cr <device> */
 static int cmd_i3c_ibi_cr(const struct shell *sh, size_t argc, char **argv)
 {
@@ -2011,7 +2081,7 @@ static int cmd_i3c_ibi_cr(const struct shell *sh, size_t argc, char **argv)
 
 	return 0;
 }
-
+#endif /* CONFIG_I3C_CONTROLLER */
 /* i3c ibi tir <device> [<bytes>]*/
 static int cmd_i3c_ibi_tir(const struct shell *sh, size_t argc, char **argv)
 {
@@ -2028,9 +2098,9 @@ static int cmd_i3c_ibi_tir(const struct shell *sh, size_t argc, char **argv)
 		return -ENODEV;
 	}
 
-	data_length = argc - 3;
+	data_length = argc - 2;
 	for (i = 0; i < data_length; i++) {
-		buf[i] = (uint8_t)strtol(argv[3 + i], NULL, 16);
+		buf[i] = (uint8_t)strtol(argv[2 + i], NULL, 16);
 	}
 
 	request.ibi_type = I3C_IBI_TARGET_INTR;
@@ -2047,7 +2117,8 @@ static int cmd_i3c_ibi_tir(const struct shell *sh, size_t argc, char **argv)
 
 	return 0;
 }
-
+#endif /* CONFIG_I3C_TARGET */
+#ifdef CONFIG_I3C_CONTROLLER
 /* i3c ibi enable <device> <target> */
 static int cmd_i3c_ibi_enable(const struct shell *sh, size_t argc, char **argv)
 {
@@ -2093,8 +2164,9 @@ static int cmd_i3c_ibi_disable(const struct shell *sh, size_t argc, char **argv)
 
 	return 0;
 }
-#endif
-
+#endif /* CONFIG_I3C_CONTROLLER */
+#endif /* CONFIG_I3C_USE_IBI */
+#ifdef CONFIG_I3C_CONTROLLER
 static void i3c_device_list_target_name_get(size_t idx, struct shell_static_entry *entry)
 {
 	if (idx < ARRAY_SIZE(i3c_list)) {
@@ -2122,6 +2194,7 @@ static void i3c_device_attached_target_name_get(size_t idx, struct shell_static_
 }
 
 SHELL_DYNAMIC_CMD_CREATE(dsub_i3c_device_attached_name, i3c_device_attached_target_name_get);
+#endif /* CONFIG_I3C_CONTROLLER */
 
 static void i3c_device_name_get(size_t idx, struct shell_static_entry *entry)
 {
@@ -2141,10 +2214,7 @@ SHELL_DYNAMIC_CMD_CREATE(dsub_i3c_device_name, i3c_device_name_get);
 /* L2 I3C IBI Shell Commands*/
 SHELL_STATIC_SUBCMD_SET_CREATE(
 	sub_i3c_ibi_cmds,
-	SHELL_CMD_ARG(hj_response, &dsub_i3c_device_name,
-		      "Set IBI HJ Response\n"
-		      "Usage: ibi hj_response <device> <\"ack\"/\"nack\">",
-		      cmd_i3c_ibi_hj_response, 3, 0),
+#ifdef CONFIG_I3C_TARGET
 	SHELL_CMD_ARG(hj, &dsub_i3c_device_name,
 		      "Send IBI HJ\n"
 		      "Usage: ibi hj <device>",
@@ -2153,10 +2223,18 @@ SHELL_STATIC_SUBCMD_SET_CREATE(
 		      "Send IBI TIR\n"
 		      "Usage: ibi tir <device> [<byte1>, ...]",
 		      cmd_i3c_ibi_tir, 2, MAX_I3C_BYTES),
+#ifdef CONFIG_I3C_CONTROLLER
 	SHELL_CMD_ARG(cr, &dsub_i3c_device_name,
 		      "Send IBI CR\n"
 		      "Usage: ibi cr <device>",
 		      cmd_i3c_ibi_cr, 2, 0),
+#endif /* CONFIG_I3C_CONTROLLER */
+#endif /* CONFIG_I3C_TARGET */
+#ifdef CONFIG_I3C_CONTROLLER
+	SHELL_CMD_ARG(hj_response, &dsub_i3c_device_name,
+		      "Set IBI HJ Response\n"
+		      "Usage: ibi hj_response <device> <\"ack\"/\"nack\">",
+		      cmd_i3c_ibi_hj_response, 3, 0),
 	SHELL_CMD_ARG(enable, &dsub_i3c_device_attached_name,
 		      "Enable receiving IBI from target\n"
 		      "Usage: ibi enable <device> <target>",
@@ -2165,10 +2243,12 @@ SHELL_STATIC_SUBCMD_SET_CREATE(
 		      "Disable receiving IBI from target\n"
 		      "Usage: ibi disable <device> <target>",
 		      cmd_i3c_ibi_disable, 3, 0),
+#endif /* CONFIG_I3C_CONTROLLER */
 	SHELL_SUBCMD_SET_END /* Array terminated. */
 );
 #endif
 
+#ifdef CONFIG_I3C_CONTROLLER
 /* L3 I3C HDR DDR Shell Commands*/
 SHELL_STATIC_SUBCMD_SET_CREATE(
 	sub_i3c_hdr_ddr_cmds,
@@ -2196,6 +2276,10 @@ SHELL_STATIC_SUBCMD_SET_CREATE(
 /* L2 I3C CCC Shell Commands*/
 SHELL_STATIC_SUBCMD_SET_CREATE(
 	sub_i3c_ccc_cmds,
+	SHELL_CMD_ARG(rstdaa_dc, &dsub_i3c_device_attached_name,
+		      "Send CCC RSTDAA\n"
+		      "Usage: ccc rstdaa_dc <device> <target>",
+		      cmd_i3c_ccc_rstdaa_dc, 3, 0),
 	SHELL_CMD_ARG(rstdaa, &dsub_i3c_device_name,
 		      "Send CCC RSTDAA\n"
 		      "Usage: ccc rstdaa <device>",
@@ -2252,10 +2336,12 @@ SHELL_STATIC_SUBCMD_SET_CREATE(
 		      "Send CCC SETMWL BC\n"
 		      "Usage: ccc setmwl_bc <device> <max write length>",
 		      cmd_i3c_ccc_setmwl_bc, 3, 0),
+#ifdef CONFIG_I3C_TARGET
 	SHELL_CMD_ARG(deftgts, &dsub_i3c_device_name,
 		      "Send CCC DEFTGTS\n"
 		      "Usage: ccc deftgts <device>",
 		      cmd_i3c_ccc_deftgts, 2, 0),
+#endif
 	SHELL_CMD_ARG(enttm, &dsub_i3c_device_name,
 		      "Send CCC ENTTM\n"
 		      "Usage: ccc enttm <device> <defining byte>",
@@ -2264,6 +2350,12 @@ SHELL_STATIC_SUBCMD_SET_CREATE(
 		      "Send CCC RSTACT\n"
 		      "Usage: ccc rstact <device> <target> <\"set\"/\"get\"> <defining byte>",
 		      cmd_i3c_ccc_rstact, 5, 0),
+#ifdef CONFIG_I3C_TARGET
+	SHELL_CMD_ARG(getacccr, &dsub_i3c_device_attached_name,
+		      "Send CCC GETACCCR\n"
+		      "Usage: ccc getacccr <device> <target>",
+		      cmd_i3c_ccc_getacccr, 3, 0),
+#endif /* CONFIG_I3C_TARGET */
 	SHELL_CMD_ARG(rstact_bc, &dsub_i3c_device_name,
 		      "Send CCC RSTACT BC\n"
 		      "Usage: ccc rstact_bc <device> <defining byte>",
@@ -2346,10 +2438,12 @@ SHELL_STATIC_SUBCMD_SET_CREATE(
 		      cmd_i3c_ccc_setvendor_bc, 3, MAX_I3C_BYTES),
 	SHELL_SUBCMD_SET_END /* Array terminated. */
 );
+#endif /* CONFIG_I3C_CONTROLLER */
 
 /* L1 I3C Shell Commands*/
 SHELL_STATIC_SUBCMD_SET_CREATE(
 	sub_i3c_cmds,
+#ifdef CONFIG_I3C_CONTROLLER
 	SHELL_CMD_ARG(info, &dsub_i3c_device_attached_name,
 		      "Get I3C device info\n"
 		      "Usage: info <device> [<target>]",
@@ -2410,12 +2504,13 @@ SHELL_STATIC_SUBCMD_SET_CREATE(
 		      "Send I3C HDR\n"
 		      "Usage: hdr <sub cmd>",
 		      NULL, 3, 0),
+#endif /* CONFIG_I3C_CONTROLLER */
 #ifdef CONFIG_I3C_USE_IBI
 	SHELL_CMD_ARG(ibi, &sub_i3c_ibi_cmds,
 		      "Send I3C IBI\n"
 		      "Usage: ibi <sub cmd>",
 		      NULL, 3, 0),
-#endif
+#endif /* CONFIG_I3C_USE_IBI */
 	SHELL_SUBCMD_SET_END /* Array terminated. */
 );
 
diff --git a/drivers/i3c/i3c_stm32.c b/drivers/i3c/i3c_stm32.c
index 9616db1fbd4..8c9f747273f 100644
--- a/drivers/i3c/i3c_stm32.c
+++ b/drivers/i3c/i3c_stm32.c
@@ -103,7 +103,7 @@ struct i3c_stm32_msg {
 	size_t num_msgs;                  /* Number of messages */
 	size_t ctrl_msg_idx;              /* Current control message index */
 	size_t status_msg_idx;            /* Current status message index */
-	size_t xfer_msg_idx;              /* Current trasnfer message index */
+	size_t xfer_msg_idx;              /* Current transfer message index */
 	size_t xfer_offset;               /* Current message transfer offset */
 	uint32_t msg_type;                /* Either LL_I3C_CONTROLLER_MTYPE_PRIVATE or
 					   * LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C
@@ -157,6 +157,7 @@ struct i3c_stm32_data {
 		uint8_t num_addr; /* Number of valid addresses */
 	} ibi;
 	struct k_sem ibi_lock_sem; /* Semaphore used for ibi requests */
+	bool hj_pm_lock;           /* Used as flag for setting pm */
 #endif
 };
 /**
@@ -472,15 +473,16 @@ static int i3c_stm32_calc_scll_od_sclh_i2c(const struct device *dev, uint32_t i2
 						1000000000ull) -
 				   1;
 			*sclh_i2c = DIV_ROUND_UP(i3c_clock, i2c_bus_freq) - *scll_od - 2;
+			if (*sclh_i2c <
+				  (DIV_ROUND_UP(STM32_I3C_SCLH_I2C_MIN_FM_NS * i3c_clock,
+							    1000000000ull) - 1)
+			   ) {
+				LOG_ERR("Cannot find a combination of SCLL_OD and SCLH_I2C at "
+					"current I3C clock frequency for FM I2C bus");
+				return -EINVAL;
+			}
 		}
 
-		if (*sclh_i2c <
-		    DIV_ROUND_UP(STM32_I3C_SCLH_I2C_MIN_FM_NS * i3c_clock, 1000000000ull) - 1) {
-			LOG_ERR("Cannot find a combination of SCLL_OD and SCLH_I2C at current I3C "
-				"clock "
-				"frequency for FM I2C bus");
-			return -EINVAL;
-		}
 	} else {
 		if (config->drv_cfg.dev_list.num_i2c > 0) {
 			enum i3c_bus_mode mode = i3c_bus_mode(&config->drv_cfg.dev_list);
@@ -1562,6 +1564,9 @@ static int i3c_stm32_init(const struct device *dev)
 
 #ifdef CONFIG_I3C_USE_IBI
 	LL_I3C_EnableHJAck(i3c);
+	data->hj_pm_lock = true;
+	(void)pm_device_runtime_get(dev);
+	pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
 #endif
 
 	return 0;
@@ -1895,6 +1900,35 @@ static void i3c_stm32_error_isr(void *arg)
 
 #ifdef CONFIG_I3C_USE_IBI
 
+int i3c_stm32_ibi_hj_response(const struct device *dev, bool ack)
+{
+	const struct i3c_stm32_config *config = dev->config;
+	struct i3c_stm32_data *data = dev->data;
+	I3C_TypeDef *i3c = config->i3c;
+
+	if (ack) {
+		/*
+		 * This prevents pm_device_runtime from being called multiple times
+		 * with redunant calls
+		 */
+		if (!data->hj_pm_lock) {
+			data->hj_pm_lock = true;
+			(void)pm_device_runtime_get(dev);
+			pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
+		}
+		LL_I3C_EnableHJAck(i3c);
+	} else {
+		LL_I3C_DisableHJAck(i3c);
+		if (data->hj_pm_lock) {
+			data->hj_pm_lock = false;
+			(void)pm_device_runtime_put(dev);
+			pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
+		}
+	}
+
+	return 0;
+}
+
 int i3c_stm32_ibi_enable(const struct device *dev, struct i3c_device_desc *target)
 {
 	int ret = 0;
@@ -2068,6 +2102,7 @@ static DEVICE_API(i3c, i3c_stm32_driver_api) = {
 	.do_daa = i3c_stm32_do_daa,
 	.do_ccc = i3c_stm32_do_ccc,
 #ifdef CONFIG_I3C_USE_IBI
+	.ibi_hj_response = i3c_stm32_ibi_hj_response,
 	.ibi_enable = i3c_stm32_ibi_enable,
 	.ibi_disable = i3c_stm32_ibi_disable,
 #endif
diff --git a/drivers/ieee802154/CMakeLists.txt b/drivers/ieee802154/CMakeLists.txt
index 3fdb65790af..f731bdb9f55 100644
--- a/drivers/ieee802154/CMakeLists.txt
+++ b/drivers/ieee802154/CMakeLists.txt
@@ -15,6 +15,7 @@ zephyr_library_sources_ifdef(CONFIG_IEEE802154_CC2520		ieee802154_cc2520.c)
 zephyr_library_sources_ifdef(CONFIG_IEEE802154_DW1000		ieee802154_dw1000.c)
 zephyr_library_sources_ifdef(CONFIG_IEEE802154_KW41Z		ieee802154_kw41z.c)
 zephyr_library_sources_ifdef(CONFIG_IEEE802154_MCR20A		ieee802154_mcr20a.c)
+zephyr_library_sources_ifdef(CONFIG_IEEE802154_MCXW		ieee802154_mcxw.c		ieee802154_mcxw_utils.c)
 zephyr_library_sources_ifdef(CONFIG_IEEE802154_NRF5		ieee802154_nrf5.c)
 zephyr_library_sources_ifdef(CONFIG_IEEE802154_RF2XX		ieee802154_rf2xx.c)
 zephyr_library_sources_ifdef(CONFIG_IEEE802154_RF2XX		ieee802154_rf2xx_iface.c)
diff --git a/drivers/ieee802154/Kconfig b/drivers/ieee802154/Kconfig
index 447b32ccbe0..a3f89c72665 100644
--- a/drivers/ieee802154/Kconfig
+++ b/drivers/ieee802154/Kconfig
@@ -76,6 +76,8 @@ source "drivers/ieee802154/Kconfig.kw41z"
 
 source "drivers/ieee802154/Kconfig.mcr20a"
 
+source "drivers/ieee802154/Kconfig.mcxw"
+
 source "drivers/ieee802154/Kconfig.nrf5"
 
 source "drivers/ieee802154/Kconfig.cc1200"
diff --git a/drivers/ieee802154/Kconfig.mcxw b/drivers/ieee802154/Kconfig.mcxw
new file mode 100644
index 00000000000..5829a8f9736
--- /dev/null
+++ b/drivers/ieee802154/Kconfig.mcxw
@@ -0,0 +1,28 @@
+# NXP MCXW 802.15.4 configuration options
+
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig IEEE802154_MCXW
+	bool "NXP MCXW series IEEE 802.15.4 Driver"
+	default y
+	depends on DT_HAS_NXP_MCXW_IEEE802154_ENABLED
+	depends on COUNTER
+
+if IEEE802154_MCXW
+
+config IEEE802154_MCXW_INIT_PRIO
+	int "Initial priority for the IEEE802154 driver"
+	default 80
+
+config IEEE802154_MCXW_RX_STACK_SIZE
+	int "Driver's internal RX thread stack size"
+	default 800
+
+
+config IEEE802154_MCXW_CSL_ACCURACY
+	int "Csl accuracy for delayed operations"
+	default 100
+
+
+endif
diff --git a/drivers/ieee802154/ieee802154_dw1000.c b/drivers/ieee802154/ieee802154_dw1000.c
index de8dd68e562..f8acaa928d4 100644
--- a/drivers/ieee802154/ieee802154_dw1000.c
+++ b/drivers/ieee802154/ieee802154_dw1000.c
@@ -274,16 +274,6 @@ static inline uint32_t dwt_reg_read_u32(const struct device *dev,
 	return sys_get_le32(buf);
 }
 
-static inline uint16_t dwt_reg_read_u16(const struct device *dev,
-				     uint8_t reg, uint16_t offset)
-{
-	uint8_t buf[sizeof(uint16_t)];
-
-	dwt_spi_transfer(dev, reg, offset, sizeof(buf), buf, false);
-
-	return sys_get_le16(buf);
-}
-
 static inline uint8_t dwt_reg_read_u8(const struct device *dev,
 				   uint8_t reg, uint16_t offset)
 {
diff --git a/drivers/ieee802154/ieee802154_dw1000_regs.h b/drivers/ieee802154/ieee802154_dw1000_regs.h
index ae0433ad927..886765f79dc 100644
--- a/drivers/ieee802154/ieee802154_dw1000_regs.h
+++ b/drivers/ieee802154/ieee802154_dw1000_regs.h
@@ -151,7 +151,7 @@
 #define DWT_TX_FCTRL_PE_MASK        0x00300000UL
 /* Bit mask to access Transmit Preamble Symbol Repetitions (PSR). */
 #define DWT_TX_FCTRL_TXPSR_PE_MASK  0x003C0000UL
-/* FSCTRL has fields which should always be writen zero */
+/* FSCTRL has fields which should always be written zero */
 #define DWT_TX_FCTRL_SAFE_MASK_32   0xFFFFE3FFUL
 /* Transmit Bit Rate = 110k */
 #define DWT_TX_FCTRL_TXBR_110k      0x00000000UL
@@ -227,7 +227,7 @@
 #define DWT_SYS_CTRL_LEN            4
 /*
  * System Control Register access mask
- * (all unused fields should always be writen as zero)
+ * (all unused fields should always be written as zero)
  */
 #define DWT_SYS_CTRL_MASK_32        0x010003CFUL
 /* Suppress Auto-FCS Transmission (on this frame) */
@@ -262,7 +262,7 @@
 #define DWT_SYS_MASK_LEN            4
 /*
  * System Event Mask Register access mask
- * (all unused fields should always be writen as zero)
+ * (all unused fields should always be written as zero)
  */
 #define DWT_SYS_MASK_MASK_32        0x3FF7FFFEUL
 /* Mask clock PLL lock event */
@@ -329,7 +329,7 @@
 #define DWT_SYS_STATUS_LEN          5
 /*
  * System event Status Register access mask
- * (all unused fields should always be writen as zero)
+ * (all unused fields should always be written as zero)
  */
 #define DWT_SYS_STATUS_MASK_32      0xFFF7FFFFUL
 /* Interrupt Request Status READ ONLY */
@@ -453,7 +453,7 @@
 #define DWT_RX_FINFO_LEN            4
 /*
  * System event Status Register access mask
- * (all unused fields should always be writen as zero)
+ * (all unused fields should always be written as zero)
  */
 #define DWT_RX_FINFO_MASK_32        0xFFFFFBFFUL
 /* Receive Frame Length (0 to 127) */
@@ -558,7 +558,7 @@
 #define DWT_RX_TTCKO_LEN            5
 /*
  * Receiver Time Tracking Offset access mask
- * (all unused fields should always be writen as zero)
+ * (all unused fields should always be written as zero)
  */
 #define DWT_RX_TTCKO_MASK_32        0xFF07FFFFUL
 /* RX time tracking offset. This RXTOFS value is a 19-bit signed quantity */
diff --git a/drivers/ieee802154/ieee802154_mcxw.c b/drivers/ieee802154/ieee802154_mcxw.c
new file mode 100644
index 00000000000..247342e66a1
--- /dev/null
+++ b/drivers/ieee802154/ieee802154_mcxw.c
@@ -0,0 +1,1360 @@
+/* ieee802154_mcxw.c - NXP MCXW 802.15.4 driver */
+
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_mcxw_ieee802154
+
+#define LOG_MODULE_NAME ieee802154_mcxw
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(LOG_MODULE_NAME);
+
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <zephyr/debug/stack.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/counter.h>
+#include <zephyr/init.h>
+#include <zephyr/net/net_if.h>
+#include <zephyr/net/net_pkt.h>
+
+#if defined(CONFIG_NET_L2_OPENTHREAD)
+#include <zephyr/net/openthread.h>
+#include <zephyr/net/ieee802154_radio_openthread.h>
+#endif
+
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/random/random.h>
+
+#include <zephyr/net/ieee802154_radio.h>
+
+#include <soc.h>
+#include <errno.h>
+#include <string.h>
+
+#include "EmbeddedTypes.h"
+#include "Phy.h"
+
+#include "fwk_platform_ot.h"
+
+#include "ieee802154_mcxw.h"
+#include "ieee802154_mcxw_utils.h"
+
+void PLATFORM_RemoteActiveReq(void);
+void PLATFORM_RemoteActiveRel(void);
+
+#if CONFIG_IEEE802154_CSL_ENDPOINT
+
+#define CMP_OVHD (4 * IEEE802154_SYMBOL_TIME_US) /* 2 LPTRM (32 kHz) ticks */
+
+static bool_t csl_rx = FALSE;
+
+static void set_csl_sample_time(void);
+static void start_csl_receiver(void);
+static void stop_csl_receiver(void);
+static uint16_t rf_compute_csl_phase(uint32_t aTimeUs);
+
+#else /* CONFIG_IEEE802154_CSL_ENDPOINT */
+#define start_csl_receiver()
+#define stop_csl_receiver()
+#endif /* CONFIG_IEEE802154_CSL_ENDPOINT */
+
+static volatile uint32_t sun_rx_mode = RX_ON_IDLE_START;
+
+/* Private functions */
+static void rf_abort(void);
+static void rf_set_channel(uint8_t channel);
+static void rf_set_tx_power(int8_t tx_power);
+static uint64_t rf_adjust_tstamp_from_phy(uint64_t ts);
+
+#if CONFIG_IEEE802154_CSL_ENDPOINT || CONFIG_NET_PKT_TXTIME
+static uint32_t rf_adjust_tstamp_from_app(uint32_t time);
+#endif /* CONFIG_IEEE802154_CSL_ENDPOINT || CONFIG_NET_PKT_TXTIME */
+
+static void rf_rx_on_idle(uint32_t newValue);
+
+static uint8_t ot_phy_ctx = (uint8_t)(-1);
+
+static struct mcxw_context mcxw_ctx;
+
+/**
+ * Stub function used for controlling low power mode
+ */
+WEAK void app_allow_device_to_slepp(void)
+{
+}
+
+/**
+ * Stub function used for controlling low power mode
+ */
+WEAK void app_disallow_device_to_slepp(void)
+{
+}
+
+void mcxw_get_eui64(uint8_t *eui64)
+{
+	__ASSERT_NO_MSG(eui64);
+
+	/* PLATFORM_GetIeee802_15_4Addr(); */
+	sys_rand_get(eui64, sizeof(mcxw_ctx.mac));
+
+	eui64[0] = (eui64[0] & ~0x01) | 0x02;
+}
+
+static int mcxw_set_pan_id(const struct device *dev, uint16_t aPanId)
+{
+	struct mcxw_context *mcxw_radio = dev->data;
+
+	macToPlmeMessage_t msg;
+
+	msg.msgType = gPlmeSetReq_c;
+	msg.msgData.setReq.PibAttribute = gPhyPibPanId_c;
+	msg.msgData.setReq.PibAttributeValue = (uint64_t)aPanId;
+
+	(void)MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+
+	mcxw_radio->pan_id = aPanId;
+
+	return 0;
+}
+
+static int mcxw_set_extended_address(const struct device *dev, const uint8_t *ieee_addr)
+{
+	struct mcxw_context *mcxw_radio = dev->data;
+
+	macToPlmeMessage_t msg;
+
+	msg.msgType = gPlmeSetReq_c;
+	msg.msgData.setReq.PibAttribute = gPhyPibLongAddress_c;
+	msg.msgData.setReq.PibAttributeValue = *(uint64_t *)ieee_addr;
+
+	memcpy(mcxw_radio->mac, ieee_addr, 8);
+
+	(void)MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+
+	return 0;
+}
+
+static int mcxw_set_short_address(const struct device *dev, uint16_t aShortAddress)
+{
+	ARG_UNUSED(dev);
+
+	macToPlmeMessage_t msg;
+
+	msg.msgType = gPlmeSetReq_c;
+	msg.msgData.setReq.PibAttribute = gPhyPibShortAddress_c;
+	msg.msgData.setReq.PibAttributeValue = (uint64_t)aShortAddress;
+
+	(void)MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+
+	return 0;
+}
+
+static int mcxw_filter(const struct device *dev, bool set, enum ieee802154_filter_type type,
+		       const struct ieee802154_filter *filter)
+{
+	LOG_DBG("Applying filter %u", type);
+
+	if (!set) {
+		return -ENOTSUP;
+	}
+
+	if (type == IEEE802154_FILTER_TYPE_IEEE_ADDR) {
+		return mcxw_set_extended_address(dev, filter->ieee_addr);
+	} else if (type == IEEE802154_FILTER_TYPE_SHORT_ADDR) {
+		return mcxw_set_short_address(dev, filter->short_addr);
+	} else if (type == IEEE802154_FILTER_TYPE_PAN_ID) {
+		return mcxw_set_pan_id(dev, filter->pan_id);
+	}
+
+	return -ENOTSUP;
+}
+
+void mcxw_radio_receive(void)
+{
+	macToPlmeMessage_t msg;
+	phyStatus_t phy_status;
+
+	app_disallow_device_to_slepp();
+
+	__ASSERT(mcxw_ctx.state != RADIO_STATE_DISABLED, "Radio RX invalid state");
+
+	mcxw_ctx.state = RADIO_STATE_RECEIVE;
+
+	rf_abort();
+	rf_set_channel(mcxw_ctx.channel);
+
+	if (sun_rx_mode) {
+		start_csl_receiver();
+
+		/* restart Rx on idle only if it was enabled */
+		msg.msgType = gPlmeSetReq_c;
+		msg.msgData.setReq.PibAttribute = gPhyPibRxOnWhenIdle;
+		msg.msgData.setReq.PibAttributeValue = (uint64_t)1;
+
+		phy_status = MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+		__ASSERT_NO_MSG(phy_status == gPhySuccess_c);
+	}
+}
+
+static uint8_t mcxw_get_acc(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return CONFIG_IEEE802154_MCXW_CSL_ACCURACY;
+}
+
+static int mcxw_start(const struct device *dev)
+{
+	struct mcxw_context *mcxw_radio = dev->data;
+
+	__ASSERT(mcxw_radio->state == RADIO_STATE_DISABLED, "%s", __func__);
+
+	mcxw_radio->state = RADIO_STATE_SLEEP;
+
+	rf_rx_on_idle(RX_ON_IDLE_START);
+
+	mcxw_radio_receive();
+
+	return 0;
+}
+
+static int mcxw_stop(const struct device *dev)
+{
+	struct mcxw_context *mcxw_radio = dev->data;
+
+	__ASSERT(mcxw_radio->state != RADIO_STATE_DISABLED, "%s", __func__);
+
+	stop_csl_receiver();
+
+	mcxw_radio->state = RADIO_STATE_DISABLED;
+
+	return 0;
+}
+
+void mcxw_radio_sleep(void)
+{
+	__ASSERT_NO_MSG(((mcxw_ctx.state != RADIO_STATE_TRANSMIT) &&
+			 (mcxw_ctx.state != RADIO_STATE_DISABLED)));
+
+	rf_abort();
+
+	stop_csl_receiver();
+
+	app_allow_device_to_slepp();
+
+	mcxw_ctx.state = RADIO_STATE_SLEEP;
+}
+
+static void mcxw_enable_src_match(bool enable)
+{
+	macToPlmeMessage_t msg;
+
+	msg.msgType = gPlmeSetSAMState_c;
+	msg.msgData.SAMState = enable;
+
+	(void)MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+}
+
+static int mcxw_src_match_entry(bool extended, uint8_t *address)
+{
+	macToPlmeMessage_t msg;
+
+	msg.msgType = gPlmeAddToSapTable_c;
+	msg.msgData.deviceAddr.panId = mcxw_ctx.pan_id;
+
+	if (extended) {
+		msg.msgData.deviceAddr.mode = 3;
+		memcpy(msg.msgData.deviceAddr.addr, address, 8);
+	} else {
+		msg.msgData.deviceAddr.mode = 2;
+		memcpy(msg.msgData.deviceAddr.addr, address, 2);
+	}
+
+	if (gPhySuccess_c != MAC_PLME_SapHandler(&msg, ot_phy_ctx)) {
+		/* the status is not returned from PHY over RPMSG */
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+static int mcxw_src_clear_entry(bool extended, uint8_t *address)
+{
+	macToPlmeMessage_t msg;
+
+	msg.msgType = gPlmeRemoveFromSAMTable_c;
+	msg.msgData.deviceAddr.panId = mcxw_ctx.pan_id;
+
+	if (extended) {
+		msg.msgData.deviceAddr.mode = 3;
+		memcpy(msg.msgData.deviceAddr.addr, address, 8);
+	} else {
+		msg.msgData.deviceAddr.mode = 2;
+		memcpy(msg.msgData.deviceAddr.addr, address, 2);
+	}
+
+	if (gPhySuccess_c != MAC_PLME_SapHandler(&msg, ot_phy_ctx)) {
+		/* the status is not returned from PHY over RPMSG */
+		return -ENOENT;
+	}
+
+	return 0;
+}
+
+static int handle_ack(struct mcxw_context *mcxw_radio)
+{
+	uint8_t len;
+	struct net_pkt *pkt;
+	int err = 0;
+
+	len = mcxw_radio->rx_ack_frame.length;
+	pkt = net_pkt_rx_alloc_with_buffer(mcxw_radio->iface, len, AF_UNSPEC, 0, K_NO_WAIT);
+	if (!pkt) {
+		LOG_ERR("No free packet available.");
+		err = -ENOMEM;
+		goto exit;
+	}
+
+	if (net_pkt_write(pkt, mcxw_radio->rx_ack_frame.psdu, len) < 0) {
+		LOG_ERR("Failed to write to a packet.");
+		err = -ENOMEM;
+		goto free_ack;
+	}
+
+	/* Use some fake values for LQI and RSSI. */
+	net_pkt_set_ieee802154_lqi(pkt, 80);
+	net_pkt_set_ieee802154_rssi_dbm(pkt, -40);
+
+	net_pkt_set_timestamp_ns(pkt, mcxw_radio->rx_ack_frame.timestamp);
+
+	net_pkt_cursor_init(pkt);
+
+	if (ieee802154_handle_ack(mcxw_radio->iface, pkt) != NET_OK) {
+		LOG_ERR("ACK packet not handled - releasing.");
+	}
+
+free_ack:
+	net_pkt_unref(pkt);
+
+exit:
+	mcxw_radio->rx_ack_frame.length = 0;
+	return err;
+}
+
+static int mcxw_tx(const struct device *dev, enum ieee802154_tx_mode mode, struct net_pkt *pkt,
+		   struct net_buf *frag)
+{
+	struct mcxw_context *mcxw_radio = dev->data;
+	/* tx_data buffer has reserved memory for both macToPdDataMessage_t and actual data frame
+	 * after
+	 */
+	macToPdDataMessage_t *msg = (macToPdDataMessage_t *)mcxw_radio->tx_data;
+	phyStatus_t phy_status;
+
+	uint8_t payload_len = frag->len;
+	uint8_t *payload = frag->data;
+
+	app_disallow_device_to_slepp();
+
+	__ASSERT(mcxw_radio->state != RADIO_STATE_DISABLED, "%s: radio disabled", __func__);
+
+	if (payload_len > IEEE802154_MTU) {
+		LOG_ERR("Payload too large: %d", payload_len);
+		return -EMSGSIZE;
+	}
+
+	mcxw_radio->tx_frame.length = payload_len + IEEE802154_FCS_LENGTH;
+	memcpy(mcxw_radio->tx_frame.psdu, payload, payload_len);
+
+	mcxw_radio->tx_frame.sec_processed = net_pkt_ieee802154_frame_secured(pkt);
+	mcxw_radio->tx_frame.hdr_updated = net_pkt_ieee802154_mac_hdr_rdy(pkt);
+
+	rf_set_channel(mcxw_radio->channel);
+
+	msg->msgType = gPdDataReq_c;
+	msg->msgData.dataReq.slottedTx = gPhyUnslottedMode_c;
+	msg->msgData.dataReq.psduLength = mcxw_radio->tx_frame.length;
+	msg->msgData.dataReq.CCABeforeTx = gPhyNoCCABeforeTx_c;
+	msg->msgData.dataReq.startTime = gPhySeqStartAsap_c;
+
+	/* tx_frame.psdu will point to tx_frame.tx_data data buffer after macToPdDataMessage_t
+	 * structure
+	 */
+	msg->msgData.dataReq.pPsdu = mcxw_radio->tx_frame.psdu;
+
+	if (ieee802154_is_ar_flag_set(frag)) {
+		msg->msgData.dataReq.ackRequired = gPhyRxAckRqd_c;
+		/* The 3 bytes are 1 byte frame length and 2 bytes FCS */
+		msg->msgData.dataReq.txDuration =
+			IEEE802154_CCA_LEN_SYM + IEEE802154_PHY_SHR_LEN_SYM +
+			(3 + mcxw_radio->tx_frame.length) * RADIO_SYMBOLS_PER_OCTET +
+			IEEE802154_TURNAROUND_LEN_SYM;
+
+		if (is_frame_version_2015(frag->data, frag->len)) {
+			/* Because enhanced ack can be of variable length we need to set the timeout
+			 * value to account for the FCF and addressing fields only, and stop the
+			 * timeout timer after they are received and validated as a valid ACK
+			 */
+			msg->msgData.dataReq.txDuration += IEEE802154_ENH_ACK_WAIT_SYM;
+		} else {
+			msg->msgData.dataReq.txDuration += IEEE802154_IMM_ACK_WAIT_SYM;
+		}
+	} else {
+		msg->msgData.dataReq.ackRequired = gPhyNoAckRqd_c;
+		msg->msgData.dataReq.txDuration = 0xFFFFFFFFU;
+	}
+
+	switch (mode) {
+	case IEEE802154_TX_MODE_DIRECT:
+		msg->msgData.dataReq.CCABeforeTx = gPhyNoCCABeforeTx_c;
+		break;
+	case IEEE802154_TX_MODE_CCA:
+		msg->msgData.dataReq.CCABeforeTx = gPhyCCAMode1_c;
+		break;
+
+#if defined(CONFIG_NET_PKT_TXTIME)
+	case IEEE802154_TX_MODE_TXTIME:
+	case IEEE802154_TX_MODE_TXTIME_CCA:
+		mcxw_radio->tx_frame.tx_delay = net_pkt_timestamp_ns(pkt);
+		msg->msgData.dataReq.startTime =
+			rf_adjust_tstamp_from_app(mcxw_radio->tx_frame.tx_delay);
+		msg->msgData.dataReq.startTime /= IEEE802154_SYMBOL_TIME_US;
+		break;
+#endif
+	default:
+		break;
+	}
+
+	msg->msgData.dataReq.flags = 0;
+
+#if OPENTHREAD_CONFIG_THREAD_VERSION >= OT_THREAD_VERSION_1_2
+	if (is_keyid_mode_1(mcxw_radio->tx_frame.psdu, mcxw_radio->tx_frame.length)) {
+		if (!net_pkt_ieee802154_frame_secured(pkt)) {
+			msg->msgData.dataReq.flags |= gPhyEncFrame;
+
+			if (!net_pkt_ieee802154_mac_hdr_rdy(pkt)) {
+				msg->msgData.dataReq.flags |= gPhyUpdHDr;
+
+#if CONFIG_IEEE802154_CSL_ENDPOINT
+				/* Previously aFrame->mInfo.mTxInfo.mCslPresent was used to
+				 * determine if the radio code should update the IE header. This
+				 * field is no longer set by the OT stack. Until the issue is fixed
+				 * in OT stack check if CSL period is > 0 and always update CSL IE
+				 * in that case.
+				 */
+				if (mcxw_radio->csl_period) {
+					uint32_t hdr_time_us;
+
+					start_csl_receiver();
+
+					/* Add TX_ENCRYPT_DELAY_SYM symbols delay to allow
+					 * encryption to finish
+					 */
+					msg->msgData.dataReq.startTime =
+						PhyTime_ReadClock() + TX_ENCRYPT_DELAY_SYM;
+
+					hdr_time_us = mcxw_get_time(NULL) +
+						    (TX_ENCRYPT_DELAY_SYM +
+						     IEEE802154_PHY_SHR_LEN_SYM) *
+							    IEEE802154_SYMBOL_TIME_US;
+					set_csl_ie(mcxw_radio->tx_frame.psdu,
+						 mcxw_radio->tx_frame.length,
+						 mcxw_radio->csl_period,
+						 rf_compute_csl_phase(hdr_time_us));
+				}
+#endif /* CONFIG_IEEE802154_CSL_ENDPOINT */
+			}
+		}
+	}
+
+#endif
+
+	k_sem_reset(&mcxw_radio->tx_wait);
+
+	phy_status = MAC_PD_SapHandler(msg, ot_phy_ctx);
+	if (phy_status == gPhySuccess_c) {
+		mcxw_radio->tx_status = 0;
+		mcxw_radio->state = RADIO_STATE_TRANSMIT;
+	} else {
+		return -EIO;
+	}
+
+	k_sem_take(&mcxw_radio->tx_wait, K_FOREVER);
+
+	/* PWR_AllowDeviceToSleep(); */
+
+	mcxw_radio_receive();
+
+	switch (mcxw_radio->tx_status) {
+	case 0:
+		if (mcxw_radio->rx_ack_frame.length) {
+			return handle_ack(mcxw_radio);
+		}
+		return 0;
+
+	default:
+		return -(mcxw_radio->tx_status);
+	}
+}
+
+void mcxw_rx_thread(void *arg1, void *arg2, void *arg3)
+{
+	struct mcxw_context *mcxw_radio = (struct mcxw_context *)arg1;
+	struct net_pkt *pkt;
+	struct mcxw_rx_frame rx_frame;
+
+	ARG_UNUSED(arg2);
+	ARG_UNUSED(arg3);
+
+	while (true) {
+		pkt = NULL;
+
+		LOG_DBG("Waiting for frame");
+
+		if (k_msgq_get(&mcxw_radio->rx_msgq, &rx_frame, K_FOREVER) < 0) {
+			LOG_ERR("Failed to get RX data from message queue");
+			continue;
+		}
+
+		pkt = net_pkt_rx_alloc_with_buffer(mcxw_radio->iface, rx_frame.length, AF_UNSPEC, 0,
+						   K_FOREVER);
+
+		if (net_pkt_write(pkt, rx_frame.psdu, rx_frame.length)) {
+			goto drop;
+		}
+
+		net_pkt_set_ieee802154_lqi(pkt, rx_frame.lqi);
+		net_pkt_set_ieee802154_rssi_dbm(pkt, rx_frame.rssi);
+		net_pkt_set_ieee802154_ack_fpb(pkt, rx_frame.ack_fpb);
+
+#if defined(CONFIG_NET_PKT_TIMESTAMP)
+		net_pkt_set_timestamp_ns(pkt, rx_frame.timestamp);
+#endif
+
+#if defined(CONFIG_NET_L2_OPENTHREAD)
+		net_pkt_set_ieee802154_ack_seb(pkt, rx_frame.ack_seb);
+#endif
+		if (net_recv_data(mcxw_radio->iface, pkt) < 0) {
+			LOG_ERR("Packet dropped by NET stack");
+			goto drop;
+		}
+
+		k_free(rx_frame.phy_buffer);
+		rx_frame.phy_buffer = NULL;
+
+		/* restart rx on idle if enough space in message queue */
+		if (k_msgq_num_free_get(&mcxw_radio->rx_msgq) >= 2) {
+			rf_rx_on_idle(RX_ON_IDLE_START);
+		}
+
+		continue;
+
+drop:
+		/* PWR_AllowDeviceToSleep(); */
+		net_pkt_unref(pkt);
+	}
+}
+
+int8_t mcxw_get_rssi(void)
+{
+	macToPlmeMessage_t msg;
+
+	msg.msgType = gPlmeGetReq_c;
+	msg.msgData.getReq.PibAttribute = gPhyGetRSSILevel_c;
+	msg.msgData.getReq.PibAttributeValue = 127; /* RSSI is invalid*/
+
+	(void)MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+
+	return (int8_t)msg.msgData.getReq.PibAttributeValue;
+}
+
+void mcxw_set_promiscuous(bool aEnable)
+{
+	macToPlmeMessage_t msg;
+
+	msg.msgType = gPlmeSetReq_c;
+	msg.msgData.setReq.PibAttribute = gPhyPibPromiscuousMode_c;
+	msg.msgData.setReq.PibAttributeValue = (uint64_t)aEnable;
+
+	(void)MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+}
+
+void mcxw_set_pan_coord(bool aEnable)
+{
+	macToPlmeMessage_t msg;
+
+	msg.msgType = gPlmeSetReq_c;
+	msg.msgData.setReq.PibAttribute = gPhyPibPanCoordinator_c;
+	msg.msgData.setReq.PibAttributeValue = (uint64_t)aEnable;
+
+	(void)MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+}
+
+static int mcxw_energy_scan(const struct device *dev, uint16_t duration,
+			    energy_scan_done_cb_t done_cb)
+{
+
+	int status = 0;
+	phyStatus_t phy_status;
+	macToPlmeMessage_t msg;
+
+	app_disallow_device_to_slepp();
+
+	struct mcxw_context *mcxw_radio = dev->data;
+
+	__ASSERT_NO_MSG(((mcxw_radio->state != RADIO_STATE_TRANSMIT) &&
+			 (mcxw_radio->state != RADIO_STATE_DISABLED)));
+
+	rf_abort();
+
+	rf_set_channel(mcxw_radio->channel);
+
+	mcxw_radio->energy_scan_done = done_cb;
+
+	msg.msgType = gPlmeEdReq_c;
+	msg.msgData.edReq.startTime = gPhySeqStartAsap_c;
+	msg.msgData.edReq.measureDurationSym = duration * 1000;
+
+	phy_status = MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+	if (phy_status != gPhySuccess_c) {
+		mcxw_radio->energy_scan_done = NULL;
+		status = -EIO;
+	}
+
+	return status;
+}
+
+static int mcxw_set_txpower(const struct device *dev, int16_t dbm)
+{
+	struct mcxw_context *mcxw_radio = dev->data;
+
+	LOG_DBG("%d", dbm);
+
+	if (dbm != mcxw_radio->tx_pwr_lvl) {
+		/* Set Power level for TX */
+		rf_set_tx_power(dbm);
+		mcxw_radio->tx_pwr_lvl = dbm;
+	}
+
+	return 0;
+}
+
+static void mcxw_configure_enh_ack_probing(const struct ieee802154_config *config)
+{
+	uint32_t ie_param = 0;
+	macToPlmeMessage_t msg;
+
+	uint8_t *header_ie_buf = (uint8_t *)(config->ack_ie.header_ie);
+
+	ie_param = (header_ie_buf[6] == 0x03 ? IeData_Lqi_c : 0) |
+		   (header_ie_buf[7] == 0x02 ? IeData_LinkMargin_c : 0) |
+		   (header_ie_buf[8] == 0x01 ? IeData_Rssi_c : 0);
+
+	msg.msgType = gPlmeConfigureAckIeData_c;
+	msg.msgData.AckIeData.param = (ie_param > 0 ? IeData_MSB_VALID_DATA : 0);
+	msg.msgData.AckIeData.param |= ie_param;
+	msg.msgData.AckIeData.shortAddr = config->ack_ie.short_addr;
+	memcpy(msg.msgData.AckIeData.extAddr, config->ack_ie.ext_addr, 8);
+	memcpy(msg.msgData.AckIeData.data, config->ack_ie.header_ie,
+	       config->ack_ie.header_ie->length);
+
+	(void)MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+}
+
+static void mcxw_set_mac_key(struct ieee802154_key *mac_keys)
+{
+	macToPlmeMessage_t msg;
+
+	__ASSERT_NO_MSG(mac_keys);
+	__ASSERT_NO_MSG(mac_keys[0].key_id && mac_keys[0].key_value);
+	__ASSERT_NO_MSG(mac_keys[1].key_id && mac_keys[1].key_value);
+	__ASSERT_NO_MSG(mac_keys[2].key_id && mac_keys[2].key_value);
+
+	msg.msgType = gPlmeSetMacKey_c;
+	msg.msgData.MacKeyData.keyId = *(mac_keys[1].key_id);
+
+	memcpy(msg.msgData.MacKeyData.prevKey, mac_keys[0].key_value, 16);
+	memcpy(msg.msgData.MacKeyData.currKey, mac_keys[1].key_value, 16);
+	memcpy(msg.msgData.MacKeyData.nextKey, mac_keys[2].key_value, 16);
+
+	(void)MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+}
+
+void mcxw_set_mac_frame_counter(uint32_t frame_counter)
+{
+	macToPlmeMessage_t msg;
+
+	msg.msgType = gPlmeSetMacFrameCounter_c;
+	msg.msgData.MacFrameCounter = frame_counter;
+
+	(void)MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+}
+
+void mcxw_set_mac_frame_counter_if_larger(uint32_t frame_counter)
+{
+	macToPlmeMessage_t msg;
+
+	msg.msgType = gPlmeSetMacFrameCounterIfLarger_c;
+	msg.msgData.MacFrameCounter = frame_counter;
+
+	(void)MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+}
+
+#if CONFIG_IEEE802154_CSL_ENDPOINT
+
+static void mcxw_receive_at(uint8_t channel, uint32_t start, uint32_t duration)
+{
+	macToPlmeMessage_t msg;
+
+	__ASSERT_NO_MSG(mcxw_ctx.state == RADIO_STATE_SLEEP);
+	mcxw_ctx.state = RADIO_STATE_RECEIVE;
+
+	/* checks internally if the channel needs to be changed */
+	rf_set_channel(mcxw_ctx.channel);
+
+	start = rf_adjust_tstamp_from_app(start);
+
+	msg.msgType = gPlmeSetTRxStateReq_c;
+	msg.msgData.setTRxStateReq.slottedMode = gPhyUnslottedMode_c;
+	msg.msgData.setTRxStateReq.state = gPhySetRxOn_c;
+	msg.msgData.setTRxStateReq.rxDuration = duration / IEEE802154_SYMBOL_TIME_US;
+	msg.msgData.setTRxStateReq.startTime = start / IEEE802154_SYMBOL_TIME_US;
+
+	(void)MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+}
+
+static void mcxw_enable_csl(uint16_t period)
+{
+	mcxw_ctx.csl_period = period;
+
+	macToPlmeMessage_t msg;
+
+	msg.msgType = gPlmeCslEnable_c;
+	msg.msgData.cslPeriod = period;
+
+	(void)MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+}
+
+static void set_csl_sample_time(void)
+{
+	if (!mcxw_ctx.csl_period) {
+		return;
+	}
+
+	macToPlmeMessage_t msg;
+	uint32_t csl_period = mcxw_ctx.csl_period * 10 * IEEE802154_SYMBOL_TIME_US;
+	uint32_t dt = mcxw_ctx.csl_sample_time - (uint32_t)mcxw_get_time(NULL);
+
+	/* next channel sample should be in the future */
+	while ((dt <= CMP_OVHD) || (dt > (CMP_OVHD + 2 * csl_period))) {
+		mcxw_ctx.csl_sample_time += csl_period;
+		dt = mcxw_ctx.csl_sample_time - (uint32_t)mcxw_get_time(NULL);
+	}
+
+	/* The CSL sample time is in microseconds and PHY function expects also microseconds */
+	msg.msgType = gPlmeCslSetSampleTime_c;
+	msg.msgData.cslSampleTime = rf_adjust_tstamp_from_app(mcxw_ctx.csl_sample_time);
+
+	(void)MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+}
+
+static void start_csl_receiver(void)
+{
+	if (!mcxw_ctx.csl_period) {
+		return;
+	}
+
+	/* NBU has to be awake during CSL receiver trx  so that conversion from
+	 * PHY timebase (NBU) to TMR timebase (host) is valid
+	 */
+	if (!csl_rx) {
+		PLATFORM_RemoteActiveReq();
+
+		csl_rx = TRUE;
+	}
+
+	/* sample time is converted to PHY time */
+	set_csl_sample_time();
+}
+
+static void stop_csl_receiver(void)
+{
+	if (csl_rx) {
+		PLATFORM_RemoteActiveRel();
+
+		csl_rx = FALSE;
+	}
+}
+
+/*
+ * Compute the CSL Phase for the time_us - i.e. the time from the time_us to
+ * mcxw_ctx.csl_sample_time. The assumption is that mcxw_ctx.csl_sample_time > time_us. Since the
+ * time is kept with a limited timer in reality it means that sometimes mcxw_ctx.csl_sample_time <
+ * time_us, when the timer overflows. Therefore the formula should be:
+ *
+ * if (time_us <= mcxw_ctx.csl_sample_time)
+ *         csl_phase_us = mcxw_ctx.csl_sample_time - time_us;
+ * else
+ *         csl_phase_us = MAX_TIMER_VALUE - time_us + mcxw_ctx.csl_sample_time;
+ *
+ * For simplicity the formula below has been used.
+ */
+static uint16_t rf_compute_csl_phase(uint32_t time_us)
+{
+	/* convert CSL Period in microseconds - it was given in 10 symbols */
+	uint32_t csl_period_us = mcxw_ctx.csl_period * 10 * IEEE802154_SYMBOL_TIME_US;
+	uint32_t csl_phase_us =
+		(csl_period_us - (time_us % csl_period_us) +
+		(mcxw_ctx.csl_sample_time % csl_period_us)) % csl_period_us;
+
+	return (uint16_t)(csl_phase_us / (10 * IEEE802154_SYMBOL_TIME_US) + 1);
+}
+#endif /* CONFIG_IEEE802154_CSL_ENDPOINT */
+
+/*************************************************************************************************/
+static void rf_abort(void)
+{
+	macToPlmeMessage_t msg;
+
+	sun_rx_mode = RX_ON_IDLE_START;
+	msg.msgType = gPlmeSetReq_c;
+	msg.msgData.setReq.PibAttribute = gPhyPibRxOnWhenIdle;
+	msg.msgData.setReq.PibAttributeValue = (uint64_t)0;
+
+	(void)MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+
+	msg.msgType = gPlmeSetTRxStateReq_c;
+	msg.msgData.setTRxStateReq.state = gPhyForceTRxOff_c;
+
+	(void)MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+}
+
+static void rf_set_channel(uint8_t channel)
+{
+	macToPlmeMessage_t msg;
+
+	msg.msgType = gPlmeSetReq_c;
+	msg.msgData.setReq.PibAttribute = gPhyPibCurrentChannel_c;
+	msg.msgData.setReq.PibAttributeValue = (uint64_t)channel;
+
+	(void)MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+}
+
+static int mcxw_cca(const struct device *dev)
+{
+	macToPlmeMessage_t msg;
+	phyStatus_t phy_status;
+
+	struct mcxw_context *mcxw_radio = dev->data;
+
+	msg.msgType = gPlmeCcaReq_c;
+	msg.msgData.ccaReq.ccaType = gPhyCCAMode1_c;
+	msg.msgData.ccaReq.contCcaMode = gPhyContCcaDisabled;
+
+	phy_status = MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+
+	__ASSERT_NO_MSG(phy_status == gPhySuccess_c);
+
+	k_sem_take(&mcxw_radio->cca_wait, K_FOREVER);
+
+	return (mcxw_radio->tx_status == OT_ERROR_CHANNEL_ACCESS_FAILURE) ? -EBUSY : 0;
+}
+
+static int mcxw_set_channel(const struct device *dev, uint16_t channel)
+{
+	struct mcxw_context *mcxw_radio = dev->data;
+
+	LOG_DBG("%u", channel);
+
+	if (channel != mcxw_radio->channel) {
+
+		if (channel < 11 || channel > 26) {
+			return channel < 11 ? -ENOTSUP : -EINVAL;
+		}
+
+		mcxw_radio->channel = channel;
+	}
+
+	return 0;
+}
+
+static net_time_t mcxw_get_time(const struct device *dev)
+{
+	static uint64_t sw_timestamp;
+	static uint64_t hw_timestamp;
+
+	ARG_UNUSED(dev);
+
+	/* Get new 32bit HW timestamp */
+	uint32_t ticks;
+	uint64_t hw_timestamp_new;
+	uint64_t wrapped_val = 0;
+	uint64_t increment;
+	unsigned int key;
+
+	key = irq_lock();
+
+	if (counter_get_value(mcxw_ctx.counter, &ticks)) {
+		irq_unlock(key);
+		return -1;
+	}
+
+	hw_timestamp_new = counter_ticks_to_us(mcxw_ctx.counter, ticks);
+
+	/* Check if the timestamp has wrapped around */
+	if (hw_timestamp > hw_timestamp_new) {
+		wrapped_val =
+			COUNT_TO_USEC(((uint64_t)1 << 32), counter_get_frequency(mcxw_ctx.counter));
+	}
+
+	increment = (hw_timestamp_new + wrapped_val) - hw_timestamp;
+	sw_timestamp += increment;
+
+	/* Store new HW timestamp for next iteration */
+	hw_timestamp = hw_timestamp_new;
+
+	irq_unlock(key);
+
+	return (net_time_t)sw_timestamp;
+}
+
+static void rf_set_tx_power(int8_t tx_power)
+{
+	macToPlmeMessage_t msg;
+
+	msg.msgType = gPlmeSetReq_c;
+	msg.msgData.setReq.PibAttribute = gPhyPibTransmitPower_c;
+	msg.msgData.setReq.PibAttributeValue = (uint64_t)tx_power;
+
+	MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+}
+
+/* Used to convert from phy clock timestamp (in symbols) to platform time (in us)
+ * the reception timestamp which must use a true 64bit timestamp source
+ */
+static uint64_t rf_adjust_tstamp_from_phy(uint64_t ts)
+{
+	uint64_t now = PhyTime_ReadClock();
+	uint64_t delta;
+
+	delta = (now >= ts) ? (now - ts) : ((PHY_TMR_MAX_VALUE + now) - ts);
+	delta *= IEEE802154_SYMBOL_TIME_US;
+
+	return mcxw_get_time(NULL) - delta;
+}
+
+#if CONFIG_IEEE802154_CSL_ENDPOINT || CONFIG_NET_PKT_TXTIME
+static uint32_t rf_adjust_tstamp_from_app(uint32_t time)
+{
+	/* The phy timestamp is in symbols so we need to convert it to microseconds */
+	uint64_t ts = PhyTime_ReadClock() * IEEE802154_SYMBOL_TIME_US;
+	uint32_t delta = time - (uint32_t)mcxw_get_time(NULL);
+
+	return (uint32_t)(ts + delta);
+}
+#endif /* CONFIG_IEEE802154_CSL_ENDPOINT || CONFIG_NET_PKT_TXTIME */
+
+/* Phy Data Service Access Point handler
+ * Called by Phy to notify when Tx has been done or Rx data is available
+ */
+phyStatus_t pd_mac_sap_handler(void *msg, instanceId_t instance)
+{
+	pdDataToMacMessage_t *data_msg = (pdDataToMacMessage_t *)msg;
+
+	__ASSERT_NO_MSG(msg != NULL);
+
+	/* PWR_DisallowDeviceToSleep(); */
+
+	switch (data_msg->msgType) {
+	case gPdDataCnf_c:
+		/* TX is done */
+#if OPENTHREAD_CONFIG_THREAD_VERSION >= OT_THREAD_VERSION_1_2
+		if (is_keyid_mode_1(mcxw_ctx.tx_frame.psdu, mcxw_ctx.tx_frame.length) &&
+		    !mcxw_ctx.tx_frame.sec_processed && !mcxw_ctx.tx_frame.hdr_updated) {
+			set_frame_counter(mcxw_ctx.tx_frame.psdu, mcxw_ctx.tx_frame.length,
+					data_msg->fc);
+			mcxw_ctx.tx_frame.hdr_updated = true;
+		}
+#endif
+
+		mcxw_ctx.tx_frame.length = 0;
+		mcxw_ctx.tx_status = 0;
+		mcxw_ctx.state = RADIO_STATE_RECEIVE;
+
+		mcxw_ctx.rx_ack_frame.channel = mcxw_ctx.channel;
+		mcxw_ctx.rx_ack_frame.length = data_msg->msgData.dataCnf.ackLength;
+		mcxw_ctx.rx_ack_frame.timestamp = data_msg->msgData.dataCnf.timeStamp;
+		memcpy(mcxw_ctx.rx_ack_frame.psdu, data_msg->msgData.dataCnf.ackData,
+		       mcxw_ctx.rx_ack_frame.length);
+
+		k_sem_give(&mcxw_ctx.tx_wait);
+
+		k_free(msg);
+		break;
+
+	case gPdDataInd_c:
+		/* RX is done */
+		struct mcxw_rx_frame rx_frame;
+
+		/* retrieve frame information and data */
+		rx_frame.lqi = data_msg->msgData.dataInd.ppduLinkQuality;
+		rx_frame.rssi = data_msg->msgData.dataInd.ppduRssi;
+		rx_frame.timestamp = rf_adjust_tstamp_from_phy(data_msg->msgData.dataInd.timeStamp);
+		rx_frame.ack_fpb = data_msg->msgData.dataInd.rxAckFp;
+		rx_frame.length = data_msg->msgData.dataInd.psduLength;
+		rx_frame.psdu = data_msg->msgData.dataInd.pPsdu;
+		rx_frame.ack_seb = data_msg->msgData.dataInd.ackedWithSecEnhAck;
+
+		rx_frame.phy_buffer = (void *)msg;
+
+		/* stop rx on idle if message queue is almost full */
+		if (k_msgq_num_free_get(&mcxw_ctx.rx_msgq) == 1) {
+			rf_rx_on_idle(RX_ON_IDLE_STOP);
+		}
+
+		/* add the rx message in queue */
+		if (k_msgq_put(&mcxw_ctx.rx_msgq, &rx_frame, K_NO_WAIT) < 0) {
+			LOG_ERR("Failed to push RX data to message queue");
+		}
+		break;
+
+	default:
+		/* PWR_AllowDeviceToSleep(); */
+		break;
+	}
+
+	stop_csl_receiver();
+
+	return gPhySuccess_c;
+}
+
+/* Phy Layer Management Entities Service Access Point handler
+ * Called by Phy to notify PLME event
+ */
+phyStatus_t plme_mac_sap_handler(void *msg, instanceId_t instance)
+{
+	plmeToMacMessage_t *plme_msg = (plmeToMacMessage_t *)msg;
+
+	__ASSERT_NO_MSG(msg != NULL);
+
+	/* PWR_DisallowDeviceToSleep(); */
+
+	switch (plme_msg->msgType) {
+	case gPlmeCcaCnf_c:
+		if (plme_msg->msgData.ccaCnf.status == gPhyChannelBusy_c) {
+			/* Channel is busy */
+			mcxw_ctx.tx_status = EBUSY;
+		} else {
+			mcxw_ctx.tx_status = 0;
+		}
+		mcxw_ctx.state = RADIO_STATE_RECEIVE;
+
+		k_sem_give(&mcxw_ctx.cca_wait);
+		break;
+	case gPlmeEdCnf_c:
+		/* Scan done */
+		if (mcxw_ctx.energy_scan_done != NULL) {
+			energy_scan_done_cb_t callback = mcxw_ctx.energy_scan_done;
+
+			mcxw_ctx.max_ed = plme_msg->msgData.edCnf.maxEnergyLeveldB;
+
+			mcxw_ctx.energy_scan_done = NULL;
+			callback(net_if_get_device(mcxw_ctx.iface), mcxw_ctx.max_ed);
+		}
+		break;
+	case gPlmeTimeoutInd_c:
+		if (RADIO_STATE_TRANSMIT == mcxw_ctx.state) {
+			/* Ack timeout */
+#if OPENTHREAD_CONFIG_THREAD_VERSION >= OT_THREAD_VERSION_1_2
+			if (is_keyid_mode_1(mcxw_ctx.tx_frame.psdu, mcxw_ctx.tx_frame.length) &&
+			    !mcxw_ctx.tx_frame.sec_processed && !mcxw_ctx.tx_frame.hdr_updated) {
+				set_frame_counter(mcxw_ctx.tx_frame.psdu, mcxw_ctx.tx_frame.length,
+						plme_msg->fc);
+				mcxw_ctx.tx_frame.hdr_updated = true;
+			}
+#endif
+
+			mcxw_ctx.state = RADIO_STATE_RECEIVE;
+			/* No ack */
+			mcxw_ctx.tx_status = ENOMSG;
+
+			k_sem_give(&mcxw_ctx.tx_wait);
+		} else if (RADIO_STATE_RECEIVE == mcxw_ctx.state) {
+			/* CSL Receive AT state has ended with timeout and we are returning to SLEEP
+			 * state
+			 */
+			mcxw_ctx.state = RADIO_STATE_SLEEP;
+			/* PWR_AllowDeviceToSleep(); */
+		}
+		break;
+	case gPlmeAbortInd_c:
+		/* TX Packet was loaded into TX Packet RAM but the TX/TR seq did not ended ok */
+#if OPENTHREAD_CONFIG_THREAD_VERSION >= OT_THREAD_VERSION_1_2
+		if (is_keyid_mode_1(mcxw_ctx.tx_frame.psdu, mcxw_ctx.tx_frame.length) &&
+		    !mcxw_ctx.tx_frame.sec_processed && !mcxw_ctx.tx_frame.hdr_updated) {
+			set_frame_counter(mcxw_ctx.tx_frame.psdu, mcxw_ctx.tx_frame.length,
+					plme_msg->fc);
+			mcxw_ctx.tx_frame.hdr_updated = true;
+		}
+#endif
+
+		mcxw_ctx.state = RADIO_STATE_RECEIVE;
+		mcxw_ctx.tx_status = EIO;
+
+		k_sem_give(&mcxw_ctx.tx_wait);
+		break;
+	default:
+		/* PWR_AllowDeviceToSleep(); */
+		break;
+	}
+	/* The message has been allocated by the Phy, we have to free it */
+	k_free(msg);
+
+	stop_csl_receiver();
+
+	return gPhySuccess_c;
+}
+
+static int mcxw_configure(const struct device *dev, enum ieee802154_config_type type,
+			  const struct ieee802154_config *config)
+{
+	ARG_UNUSED(dev);
+
+	switch (type) {
+
+	case IEEE802154_CONFIG_AUTO_ACK_FPB:
+		if (config->auto_ack_fpb.mode == IEEE802154_FPB_ADDR_MATCH_THREAD) {
+			mcxw_enable_src_match(config->auto_ack_fpb.enabled);
+		}
+		/* TODO IEEE802154_FPB_ADDR_MATCH_ZIGBEE */
+		break;
+
+	case IEEE802154_CONFIG_ACK_FPB:
+		if (config->ack_fpb.enabled) {
+			return mcxw_src_match_entry(config->ack_fpb.extended, config->ack_fpb.addr);
+		} else {
+			return mcxw_src_clear_entry(config->ack_fpb.extended, config->ack_fpb.addr);
+		}
+
+		/* TODO otPlatRadioClearSrcMatchShortEntries */
+		/* TODO otPlatRadioClearSrcMatchExtEntries */
+		break;
+
+	case IEEE802154_CONFIG_PAN_COORDINATOR:
+		mcxw_set_pan_coord(config->pan_coordinator);
+		break;
+
+	case IEEE802154_CONFIG_PROMISCUOUS:
+		mcxw_set_promiscuous(config->promiscuous);
+		break;
+
+	case IEEE802154_CONFIG_MAC_KEYS:
+		mcxw_set_mac_key(config->mac_keys);
+		break;
+
+	case IEEE802154_CONFIG_FRAME_COUNTER:
+		mcxw_set_mac_frame_counter(config->frame_counter);
+		break;
+
+	case IEEE802154_CONFIG_FRAME_COUNTER_IF_LARGER:
+		mcxw_set_mac_frame_counter_if_larger(config->frame_counter);
+		break;
+
+	case IEEE802154_CONFIG_ENH_ACK_HEADER_IE:
+		mcxw_configure_enh_ack_probing(config);
+		break;
+
+#if defined(CONFIG_IEEE802154_CSL_ENDPOINT)
+	case IEEE802154_CONFIG_EXPECTED_RX_TIME:
+		mcxw_ctx.csl_sample_time = config->expected_rx_time;
+		break;
+
+	case IEEE802154_CONFIG_RX_SLOT:
+		mcxw_receive_at(config->rx_slot.channel, config->rx_slot.start / NSEC_PER_USEC,
+				config->rx_slot.duration / NSEC_PER_USEC);
+		break;
+
+	case IEEE802154_CONFIG_CSL_PERIOD:
+		mcxw_enable_csl(config->csl_period);
+		break;
+#endif /* CONFIG_IEEE802154_CSL_ENDPOINT */
+
+	case IEEE802154_CONFIG_RX_ON_WHEN_IDLE:
+		if (config->rx_on_when_idle) {
+			rf_rx_on_idle(RX_ON_IDLE_START);
+		} else {
+			rf_rx_on_idle(RX_ON_IDLE_STOP);
+		}
+		break;
+
+	case IEEE802154_CONFIG_EVENT_HANDLER:
+		break;
+
+	case IEEE802154_OPENTHREAD_CONFIG_MAX_EXTRA_CCA_ATTEMPTS:
+		break;
+
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+IEEE802154_DEFINE_PHY_SUPPORTED_CHANNELS(drv_attr, 11, 26);
+
+static int mcxw_attr_get(const struct device *dev, enum ieee802154_attr attr,
+			 struct ieee802154_attr_value *value)
+{
+	ARG_UNUSED(dev);
+
+	if (ieee802154_attr_get_channel_page_and_range(
+		    attr, IEEE802154_ATTR_PHY_CHANNEL_PAGE_ZERO_OQPSK_2450_BPSK_868_915,
+		    &drv_attr.phy_supported_channels, value) == 0) {
+		return 0;
+	}
+
+	return -EIO;
+}
+
+static enum ieee802154_hw_caps mcxw_get_capabilities(const struct device *dev)
+{
+	enum ieee802154_hw_caps caps;
+
+	caps = IEEE802154_HW_FCS | IEEE802154_HW_PROMISC | IEEE802154_HW_FILTER |
+	       IEEE802154_HW_TX_RX_ACK | IEEE802154_HW_RX_TX_ACK | IEEE802154_HW_ENERGY_SCAN |
+	       IEEE802154_HW_TXTIME | IEEE802154_HW_RXTIME | IEEE802154_HW_SLEEP_TO_TX |
+	       IEEE802154_RX_ON_WHEN_IDLE | IEEE802154_HW_TX_SEC |
+	       IEEE802154_OPENTHREAD_HW_MULTIPLE_CCA | IEEE802154_HW_SELECTIVE_TXCHANNEL |
+	       IEEE802154_OPENTHREAD_HW_CST;
+	return caps;
+}
+
+static int mcxw_init(const struct device *dev)
+{
+	struct mcxw_context *mcxw_radio = dev->data;
+
+	macToPlmeMessage_t msg;
+
+	if (PLATFORM_InitOT() < 0) {
+		return -EIO;
+	}
+
+	Phy_Init();
+
+	ot_phy_ctx = PHY_get_ctx();
+
+	/* Register Phy Data Service Access Point and Phy Layer Management Entities Service Access
+	 * Point handlers
+	 */
+	Phy_RegisterSapHandlers((PD_MAC_SapHandler_t)pd_mac_sap_handler,
+				(PLME_MAC_SapHandler_t)plme_mac_sap_handler, ot_phy_ctx);
+
+	msg.msgType = gPlmeEnableEncryption_c;
+	(void)MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+
+	mcxw_radio->state = RADIO_STATE_DISABLED;
+	mcxw_radio->energy_scan_done = NULL;
+
+	mcxw_radio->channel = DEFAULT_CHANNEL;
+	rf_set_channel(mcxw_radio->channel);
+
+	mcxw_radio->tx_frame.length = 0;
+	/* Make the psdu point to the space after macToPdDataMessage_t in the data buffer */
+	mcxw_radio->tx_frame.psdu = mcxw_radio->tx_data + sizeof(macToPdDataMessage_t);
+
+	/* Get and start LPTRM counter */
+	mcxw_radio->counter = DEVICE_DT_GET(DT_NODELABEL(lptmr0));
+	if (counter_start(mcxw_radio->counter)) {
+		return -EIO;
+	}
+
+	/* Init TX semaphore */
+	k_sem_init(&mcxw_radio->tx_wait, 0, 1);
+	/* Init CCA semaphore */
+	k_sem_init(&mcxw_radio->cca_wait, 0, 1);
+
+	/* Init RX message queue */
+	k_msgq_init(&mcxw_radio->rx_msgq, mcxw_radio->rx_msgq_buffer, sizeof(mcxw_rx_frame),
+		    NMAX_RXRING_BUFFERS);
+
+	memset(&(mcxw_radio->rx_ack_frame), 0, sizeof(mcxw_radio->rx_ack_frame));
+	mcxw_radio->rx_ack_frame.psdu = mcxw_radio->rx_ack_data;
+
+	k_thread_create(&mcxw_radio->rx_thread, mcxw_radio->rx_stack,
+			CONFIG_IEEE802154_MCXW_RX_STACK_SIZE, mcxw_rx_thread, mcxw_radio, NULL,
+			NULL, K_PRIO_COOP(2), 0, K_NO_WAIT);
+
+	k_thread_name_set(&mcxw_radio->rx_thread, "mcxw_rx");
+
+	return 0;
+}
+
+static void mcxw_iface_init(struct net_if *iface)
+{
+	const struct device *dev = net_if_get_device(iface);
+	struct mcxw_context *mcxw_radio = dev->data;
+
+	mcxw_get_eui64(mcxw_radio->mac);
+
+	net_if_set_link_addr(iface, mcxw_radio->mac, sizeof(mcxw_radio->mac), NET_LINK_IEEE802154);
+	mcxw_radio->iface = iface;
+	ieee802154_init(iface);
+}
+
+static void rf_rx_on_idle(uint32_t new_val)
+{
+	macToPlmeMessage_t msg;
+	phyStatus_t phy_status;
+
+	new_val %= 2;
+	if (sun_rx_mode != new_val) {
+		sun_rx_mode = new_val;
+		msg.msgType = gPlmeSetReq_c;
+		msg.msgData.setReq.PibAttribute = gPhyPibRxOnWhenIdle;
+		msg.msgData.setReq.PibAttributeValue = (uint64_t)sun_rx_mode;
+
+		phy_status = MAC_PLME_SapHandler(&msg, ot_phy_ctx);
+
+		__ASSERT_NO_MSG(phy_status == gPhySuccess_c);
+	}
+}
+
+static const struct ieee802154_radio_api mcxw71_radio_api = {
+	.iface_api.init = mcxw_iface_init,
+
+	.get_capabilities = mcxw_get_capabilities,
+	.cca = mcxw_cca,
+	.set_channel = mcxw_set_channel,
+	.filter = mcxw_filter,
+	.set_txpower = mcxw_set_txpower,
+	.start = mcxw_start,
+	.stop = mcxw_stop,
+	.configure = mcxw_configure,
+	.tx = mcxw_tx,
+	.ed_scan = mcxw_energy_scan,
+	.get_time = mcxw_get_time,
+	.get_sch_acc = mcxw_get_acc,
+	.attr_get = mcxw_attr_get,
+};
+
+#if defined(CONFIG_NET_L2_IEEE802154)
+#define L2          IEEE802154_L2
+#define L2_CTX_TYPE NET_L2_GET_CTX_TYPE(IEEE802154_L2)
+#define MTU         IEEE802154_MTU
+#elif defined(CONFIG_NET_L2_OPENTHREAD)
+#define L2          OPENTHREAD_L2
+#define L2_CTX_TYPE NET_L2_GET_CTX_TYPE(OPENTHREAD_L2)
+#define MTU         1280
+#elif defined(CONFIG_NET_L2_CUSTOM_IEEE802154)
+#define L2          CUSTOM_IEEE802154_L2
+#define L2_CTX_TYPE NET_L2_GET_CTX_TYPE(CUSTOM_IEEE802154_L2)
+#define MTU         CONFIG_NET_L2_CUSTOM_IEEE802154_MTU
+#endif
+
+NET_DEVICE_DT_INST_DEFINE(0, mcxw_init, NULL, &mcxw_ctx, NULL, CONFIG_IEEE802154_MCXW_INIT_PRIO,
+			  &mcxw71_radio_api, L2, L2_CTX_TYPE, MTU);
diff --git a/drivers/ieee802154/ieee802154_mcxw.h b/drivers/ieee802154/ieee802154_mcxw.h
new file mode 100644
index 00000000000..eb3fb284dc6
--- /dev/null
+++ b/drivers/ieee802154/ieee802154_mcxw.h
@@ -0,0 +1,125 @@
+/* ieee802154_mcxw.h - NXP MCXW 802.15.4 driver */
+
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCXW_H_
+#define ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCXW_H_
+
+#include <zephyr/net/ieee802154_radio.h>
+
+#include "PhyInterface.h"
+
+#define TX_ENCRYPT_DELAY_SYM 200
+
+#define DEFAULT_CHANNEL                  (11)
+#define DEFAULT_CCA_MODE                 (gPhyCCAMode1_c)
+#define IEEE802154_ACK_REQUEST           (1 << 5)
+#define IEEE802154_MIN_LENGTH            (5)
+#define IEEE802154_FRM_CTL_LO_OFFSET     (0)
+#define IEEE802154_DSN_OFFSET            (2)
+#define IEEE802154_FRM_TYPE_MASK         (0x7)
+#define IEEE802154_FRM_TYPE_ACK          (0x2)
+#define IEEE802154_SYMBOL_TIME_US        (16)
+#define IEEE802154_TURNAROUND_LEN_SYM    (12)
+#define IEEE802154_CCA_LEN_SYM           (8)
+#define IEEE802154_PHY_SHR_LEN_SYM       (10)
+#define IEEE802154_IMM_ACK_WAIT_SYM      (54)
+#define IEEE802154_ENH_ACK_WAIT_SYM      (90)
+
+#define NMAX_RXRING_BUFFERS              (8)
+#define RX_ON_IDLE_START                 (1)
+#define RX_ON_IDLE_STOP                  (0)
+
+#define PHY_TMR_MAX_VALUE                (0x00FFFFFF)
+
+/* The Uncertainty of the scheduling CSL of transmission by the parent, in ±10 us units. */
+#define CSL_UNCERT 32
+
+#define RADIO_SYMBOLS_PER_OCTET			(2)
+
+typedef enum mcxw_radio_state {
+	RADIO_STATE_DISABLED = 0,
+	RADIO_STATE_SLEEP    = 1,
+	RADIO_STATE_RECEIVE  = 2,
+	RADIO_STATE_TRANSMIT = 3,
+	RADIO_STATE_INVALID  = 255,
+} mcxw_radio_state;
+
+typedef struct mcxw_rx_frame {
+	uint8_t *psdu;
+	uint8_t length;
+	int8_t rssi;
+	uint8_t lqi;
+	uint32_t timestamp;
+	bool ack_fpb;
+	bool ack_seb;
+	uint64_t time;
+	void *phy_buffer;
+	uint8_t channel;
+} mcxw_rx_frame;
+
+typedef struct mcxw_tx_frame {
+	uint8_t *psdu;
+	uint8_t length;
+	uint32_t tx_delay;
+	uint32_t tx_delay_base;
+	bool sec_processed;
+	bool hdr_updated;
+} mcxw_tx_frame;
+
+struct mcxw_context {
+	/* Pointer to the network interface. */
+	struct net_if *iface;
+	/* Pointer to the LPTMR counter device structure*/
+	const struct device *counter;
+	/* 802.15.4 HW address. */
+	uint8_t mac[8];
+	/* RX thread stack. */
+	K_KERNEL_STACK_MEMBER(rx_stack, CONFIG_IEEE802154_MCXW_RX_STACK_SIZE);
+	/* RX thread control block. */
+	struct k_thread rx_thread;
+	/* RX message queue */
+	struct k_msgq rx_msgq;
+	/* RX message queue buffer */
+	char rx_msgq_buffer[NMAX_RXRING_BUFFERS * sizeof(mcxw_rx_frame)];
+	/* TX synchronization semaphore */
+	struct k_sem tx_wait;
+	/* TX synchronization semaphore */
+	struct k_sem cca_wait;
+	/* Radio state */
+	mcxw_radio_state state;
+	/* Pan ID */
+	uint16_t pan_id;
+	/* Channel */
+	uint8_t channel;
+	/* Maximum energy detected during ED scan */
+	int8_t max_ed;
+	/* TX power level */
+	int8_t tx_pwr_lvl;
+	/* Enery detect */
+	energy_scan_done_cb_t energy_scan_done;
+	/* TX Status */
+	int tx_status;
+	/* TX frame */
+	mcxw_tx_frame tx_frame;
+	/* TX data */
+	uint8_t tx_data[sizeof(macToPdDataMessage_t) + IEEE802154_MAX_PHY_PACKET_SIZE];
+	/* RX mode */
+	uint32_t rx_mode;
+	/* RX ACK buffers */
+	mcxw_rx_frame rx_ack_frame;
+	/* RX ACK data */
+	uint8_t rx_ack_data[IEEE802154_MAX_PHY_PACKET_SIZE];
+	/* CSL period */
+	uint32_t csl_period;
+	/* CSL sample time in microseconds */
+	uint32_t csl_sample_time;
+	/* PHY context */
+	uint8_t ot_phy_ctx;
+};
+
+#endif /* ZEPHYR_DRIVERS_IEEE802154_IEEE802154_MCXW_H_ */
diff --git a/drivers/ieee802154/ieee802154_mcxw_utils.c b/drivers/ieee802154/ieee802154_mcxw_utils.c
new file mode 100644
index 00000000000..0367f8a26b6
--- /dev/null
+++ b/drivers/ieee802154/ieee802154_mcxw_utils.c
@@ -0,0 +1,356 @@
+/* ieee802154_mcxw_utils.c - NXP MCXW 802.15.4 driver utils*/
+
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/byteorder.h>
+
+#include <errno.h>
+
+#include "ieee802154_mcxw_utils.h"
+
+/* TODO IEEE 802.15.4 MAC Multipurpose frame format */
+/* TODO add function checks */
+
+enum offset_fcf_fields {
+	OffsetFrameType = 0x00,
+	OffsetSecurityEnabled = 0x03,
+	OffsetFramePending = 0x04,
+	OffsetAR = 0x05,
+	OffsetPanIdCompression = 0x06,
+	OffsetSeqNumberSuppression = 0x08,
+	OffsetIEPresent = 0x09,
+	OffsetDstAddrMode = 0x0A,
+	OffsetFrameVersion = 0x0C,
+	OffsetSrcAddrMode = 0x0E,
+};
+
+enum mask_fcf_fields {
+	MaskFrameType = (0x7 << OffsetFrameType),
+	MaskSecurityEnabled = (0x01 << OffsetSecurityEnabled),
+	MaskFramePending = (0x01 << OffsetFramePending),
+	MaskAR = (0x01 << OffsetAR),
+	MaskPanIdCompression = (0x01 << OffsetPanIdCompression),
+	MaskSeqNumberSuppression = (0x01 << OffsetSeqNumberSuppression),
+	MaskIEPresent = (0x01 << OffsetIEPresent),
+	MaskDstAddrMode = (0x03 << OffsetDstAddrMode),
+	MaskFrameVersion = (0x03 << OffsetFrameVersion),
+	MaskSrcAddrMode = (0x03 << OffsetSrcAddrMode),
+};
+
+enum modes_dst_addr {
+	ModeDstAddrNone = 0x00,
+	ModeDstAddrShort = (0x02 << OffsetDstAddrMode),
+	ModeDstAddrExt = (0x03 << OffsetDstAddrMode),
+};
+
+enum version_frame {
+	VersionIeee2003 = 0x00,
+	VersionIeee2006 = 0x01,
+	VersionIeee2015 = 0x02,
+};
+
+enum modes_src_addr {
+	ModeSrcAddrNone = 0x00,
+	ModeSrcAddrShort = (0x02 << OffsetSrcAddrMode),
+	ModeSrcAddrExt = (0x03 << OffsetSrcAddrMode),
+};
+
+enum offset_scf_fields {
+	OffsetSecurityLevel = 0x00,
+	OffsetKeyIdMode = 0x03,
+	OffsetFrameCntSuppression = 0x05,
+	OffsetASNinNonce = 0x06,
+};
+
+enum mask_scf_fields {
+	MaskSecurityLevel = (0x07 << OffsetSecurityLevel),
+	MaskKeyIdMode = (0x03 << OffsetKeyIdMode),
+	MaskFrameCntSuppression = (0x1 << OffsetFrameCntSuppression),
+	MaskASNinNonce = (0x01 << OffsetASNinNonce),
+};
+
+static uint16_t get_frame_control_field(uint8_t *pdu, uint16_t length)
+{
+	if ((pdu == NULL) || (length < 3)) {
+		return 0x00;
+	}
+
+	return (uint16_t)(pdu[0] | (pdu[1] << 8));
+}
+
+static bool is_security_enabled(uint16_t fcf)
+{
+	if (fcf) {
+		return (bool)(fcf & MaskSecurityEnabled);
+	}
+
+	return false;
+}
+
+static bool is_ie_present(uint16_t fcf)
+{
+	if (fcf) {
+		return (bool)(fcf & MaskIEPresent);
+	}
+
+	return false;
+}
+
+static uint8_t get_frame_version(uint16_t fcf)
+{
+	if (fcf) {
+		return (uint8_t)((fcf & MaskFrameVersion) >> OffsetFrameVersion);
+	}
+
+	return 0xFF;
+}
+
+static bool is_frame_version_2015_fcf(uint16_t fcf)
+{
+	if (fcf) {
+		return get_frame_version(fcf) == VersionIeee2015;
+	}
+
+	return false;
+}
+
+bool is_frame_version_2015(uint8_t *pdu, uint16_t length)
+{
+	uint16_t fcf = get_frame_control_field(pdu, length);
+
+	if (fcf) {
+		return get_frame_version(fcf) == VersionIeee2015;
+	}
+
+	return false;
+}
+
+static bool is_sequence_number_suppression(uint16_t fcf)
+{
+	if (fcf) {
+		return (bool)(fcf & MaskSeqNumberSuppression);
+	}
+
+	return false;
+}
+
+static bool is_dst_panid_present(uint16_t fcf)
+{
+	bool present;
+
+	if (!fcf) {
+		return false;
+	}
+
+	if (is_frame_version_2015_fcf(fcf)) {
+		switch (fcf & (MaskDstAddrMode | MaskSrcAddrMode | MaskPanIdCompression)) {
+		case (ModeDstAddrNone | ModeSrcAddrNone):
+		case (ModeDstAddrShort | ModeSrcAddrNone | MaskPanIdCompression):
+		case (ModeDstAddrExt | ModeSrcAddrNone | MaskPanIdCompression):
+		case (ModeDstAddrNone | ModeSrcAddrShort):
+		case (ModeDstAddrNone | ModeSrcAddrExt):
+		case (ModeDstAddrNone | ModeSrcAddrShort | MaskPanIdCompression):
+		case (ModeDstAddrNone | ModeSrcAddrExt | MaskPanIdCompression):
+		case (ModeDstAddrExt | ModeSrcAddrExt | MaskPanIdCompression):
+			present = false;
+			break;
+		default:
+			present = true;
+		}
+	} else {
+		present = (bool)(fcf & MaskDstAddrMode);
+	}
+
+	return present;
+}
+
+static bool is_src_panid_present(uint16_t fcf)
+{
+	bool present;
+
+	if (!fcf) {
+		return false;
+	}
+
+	if (is_frame_version_2015_fcf(fcf)) {
+		switch (fcf & (MaskDstAddrMode | MaskSrcAddrMode | MaskPanIdCompression)) {
+		case (ModeDstAddrNone | ModeSrcAddrShort):
+		case (ModeDstAddrNone | ModeSrcAddrExt):
+		case (ModeDstAddrShort | ModeSrcAddrShort):
+		case (ModeDstAddrShort | ModeSrcAddrExt):
+		case (ModeDstAddrExt | ModeSrcAddrShort):
+			present = true;
+			break;
+		default:
+			present = false;
+		}
+
+	} else {
+		present = ((fcf & MaskSrcAddrMode) != 0) && ((fcf & MaskPanIdCompression) == 0);
+	}
+
+	return present;
+}
+
+static uint8_t calculate_addr_field_size(uint16_t fcf)
+{
+	uint8_t size = 2;
+
+	if (!fcf) {
+		return 0;
+	}
+
+	if (!is_sequence_number_suppression(fcf)) {
+		size += 1;
+	}
+
+	if (is_dst_panid_present(fcf)) {
+		size += 2;
+	}
+
+	/* destination addressing mode */
+	switch (fcf & MaskDstAddrMode) {
+	case ModeDstAddrShort:
+		size += 2;
+		break;
+	case ModeDstAddrExt:
+		size += 8;
+		break;
+	default:
+		break;
+	}
+
+	if (is_src_panid_present(fcf)) {
+		size += 2;
+	}
+
+	/* source addressing mode */
+	switch (fcf & MaskSrcAddrMode) {
+	case ModeSrcAddrShort:
+		size += 2;
+		break;
+	case ModeSrcAddrExt:
+		size += 8;
+		break;
+	default:
+		break;
+	}
+
+	return size;
+}
+
+static uint8_t get_keyid_mode(uint8_t *pdu, uint16_t length)
+{
+	uint16_t fcf = get_frame_control_field(pdu, length);
+	uint8_t ash_start;
+
+	if (is_security_enabled(fcf)) {
+		ash_start = calculate_addr_field_size(fcf);
+		return (uint8_t)((pdu[ash_start] & MaskKeyIdMode) >> OffsetKeyIdMode);
+	}
+
+	return 0xFF;
+}
+
+bool is_keyid_mode_1(uint8_t *pdu, uint16_t length)
+{
+	uint8_t key_mode = get_keyid_mode(pdu, length);
+
+	if (key_mode == 0x01) {
+		return true;
+	}
+
+	return false;
+}
+
+void set_frame_counter(uint8_t *pdu, uint16_t length, uint32_t fc)
+{
+	uint16_t fcf = get_frame_control_field(pdu, length);
+
+	if (is_security_enabled(fcf)) {
+		uint8_t ash_start = calculate_addr_field_size(fcf);
+		uint8_t scf = pdu[ash_start];
+
+		/* check that Frame Counter Suppression is not set */
+		if (!(scf & MaskFrameCntSuppression)) {
+			sys_put_le32(fc, &pdu[ash_start + 1]);
+		}
+	}
+}
+
+static uint8_t get_asn_size(uint8_t *pdu, uint16_t length)
+{
+	uint16_t fcf = get_frame_control_field(pdu, length);
+
+	if (is_security_enabled(fcf)) {
+		uint8_t ash_start = calculate_addr_field_size(fcf);
+		uint8_t scf = pdu[ash_start];
+		uint8_t size = 1;
+
+		/* Frame Counter Suppression is not set */
+		if (!(scf & MaskFrameCntSuppression)) {
+			size += 4;
+		}
+
+		uint8_t key_mode = get_keyid_mode(pdu, length);
+
+		switch (key_mode) {
+		case 0x01:
+			size += 1;
+			break;
+		case 0x02:
+			size += 5;
+		case 0x03:
+			size += 9;
+		default:
+			break;
+		}
+
+		return size;
+	}
+	return 0;
+}
+
+static uint8_t *get_csl_ie_content_start(uint8_t *pdu, uint16_t length)
+{
+	uint16_t fcf = get_frame_control_field(pdu, length);
+
+	if (is_ie_present(fcf)) {
+		uint8_t ie_start_idx = calculate_addr_field_size(fcf) + get_asn_size(pdu, length);
+		uint8_t *cur_ie = &pdu[ie_start_idx];
+
+		uint8_t ie_header = (uint16_t)(cur_ie[0] | (cur_ie[1] << 8));
+		uint8_t ie_length = ie_header & 0x7F;
+		uint8_t ie_el_id = ie_header & 0x7F80;
+
+		while ((ie_el_id != 0x7e) && (ie_el_id != 0x7f)) {
+			if (ie_el_id == 0x1a) {
+				return (cur_ie + 2);
+			}
+			cur_ie += (2 + ie_length);
+			ie_header = (uint16_t)(cur_ie[0] | (cur_ie[1] << 8));
+			ie_length = ie_header & 0x7F;
+			ie_el_id = ie_header & 0x7F80;
+		}
+	}
+
+	return NULL;
+}
+
+void set_csl_ie(uint8_t *pdu, uint16_t length, uint16_t period, uint16_t phase)
+{
+	uint8_t *csl_ie_content = get_csl_ie_content_start(pdu, length);
+
+	if (csl_ie_content) {
+		sys_put_le16(phase, csl_ie_content);
+		sys_put_le16(period, csl_ie_content + 2);
+	}
+}
diff --git a/drivers/ieee802154/ieee802154_mcxw_utils.h b/drivers/ieee802154/ieee802154_mcxw_utils.h
new file mode 100644
index 00000000000..2b37538eeeb
--- /dev/null
+++ b/drivers/ieee802154/ieee802154_mcxw_utils.h
@@ -0,0 +1,16 @@
+/* ieee802154_mcxw_utils.h - NXP MCXW 802.15.4 driver utils*/
+
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+bool is_frame_version_2015(uint8_t *pdu, uint16_t length);
+
+bool is_keyid_mode_1(uint8_t *pdu, uint16_t length);
+
+void set_frame_counter(uint8_t *pdu, uint16_t length, uint32_t fc);
+
+void set_csl_ie(uint8_t *pdu, uint16_t length, uint16_t period, uint16_t phase);
diff --git a/drivers/ieee802154/ieee802154_nrf5.c b/drivers/ieee802154/ieee802154_nrf5.c
index 618ee449b11..ef6208ecc27 100644
--- a/drivers/ieee802154/ieee802154_nrf5.c
+++ b/drivers/ieee802154/ieee802154_nrf5.c
@@ -585,7 +585,7 @@ static int nrf5_tx(const struct device *dev,
 		return -EMSGSIZE;
 	}
 
-	LOG_DBG("%p (%u)", payload, payload_len);
+	LOG_DBG("%p (%u)", (void *)payload, payload_len);
 
 	nrf5_radio->tx_psdu[0] = payload_len + IEEE802154_FCS_LENGTH;
 	memcpy(nrf5_radio->tx_psdu + 1, payload, payload_len);
diff --git a/drivers/input/CMakeLists.txt b/drivers/input/CMakeLists.txt
index 9215060d8ad..f8d04e4094f 100644
--- a/drivers/input/CMakeLists.txt
+++ b/drivers/input/CMakeLists.txt
@@ -11,6 +11,7 @@ zephyr_library_sources_ifdef(CONFIG_INPUT_CAP12XX input_cap12xx.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_CF1133 input_cf1133.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_CHSC6X input_chsc6x.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_CST816S input_cst816s.c)
+zephyr_library_sources_ifdef(CONFIG_INPUT_CY8CMBR3XXX input_cy8cmbr3xxx.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_ESP32_TOUCH_SENSOR input_esp32_touch_sensor.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_FT5336 input_ft5336.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_GPIO_KBD_MATRIX input_gpio_kbd_matrix.c)
@@ -18,6 +19,7 @@ zephyr_library_sources_ifdef(CONFIG_INPUT_GPIO_KEYS input_gpio_keys.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_GPIO_QDEC input_gpio_qdec.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_GT911 input_gt911.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_ILI2132A input_ili2132a.c)
+zephyr_library_sources_ifdef(CONFIG_INPUT_ITE_IT51XXX_KBD input_ite_it51xxx_kbd.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_ITE_IT8801_KBD input_ite_it8801_kbd.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_ITE_IT8XXX2_KBD input_ite_it8xxx2_kbd.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_KBD_MATRIX input_kbd_matrix.c)
@@ -27,7 +29,9 @@ zephyr_library_sources_ifdef(CONFIG_INPUT_PAT912X input_pat912x.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_PAW32XX input_paw32xx.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_PINNACLE input_pinnacle.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_PMW3610 input_pmw3610.c)
+zephyr_library_sources_ifdef(CONFIG_INPUT_REALTEK_RTS5912_KBD input_realtek_rts5912_kbd.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_SBUS input_sbus.c)
+zephyr_library_sources_ifdef(CONFIG_INPUT_STM32_TSC_KEYS input_tsc_keys.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_STMPE811 input_stmpe811.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_TOUCH input_touch.c)
 zephyr_library_sources_ifdef(CONFIG_INPUT_XEC_KBD input_xec_kbd.c)
diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig
index 85a316ac12e..889702e48db 100644
--- a/drivers/input/Kconfig
+++ b/drivers/input/Kconfig
@@ -12,6 +12,7 @@ source "drivers/input/Kconfig.cap12xx"
 source "drivers/input/Kconfig.cf1133"
 source "drivers/input/Kconfig.chsc6x"
 source "drivers/input/Kconfig.cst816s"
+source "drivers/input/Kconfig.cy8cmbr3xxx"
 source "drivers/input/Kconfig.esp32"
 source "drivers/input/Kconfig.evdev"
 source "drivers/input/Kconfig.ft5336"
@@ -20,6 +21,7 @@ source "drivers/input/Kconfig.gpio_keys"
 source "drivers/input/Kconfig.gpio_qdec"
 source "drivers/input/Kconfig.gt911"
 source "drivers/input/Kconfig.ili2132a"
+source "drivers/input/Kconfig.it51xxx"
 source "drivers/input/Kconfig.it8801"
 source "drivers/input/Kconfig.it8xxx2"
 source "drivers/input/Kconfig.kbd_matrix"
@@ -29,10 +31,12 @@ source "drivers/input/Kconfig.pat912x"
 source "drivers/input/Kconfig.paw32xx"
 source "drivers/input/Kconfig.pinnacle"
 source "drivers/input/Kconfig.pmw3610"
+source "drivers/input/Kconfig.rts5912"
 source "drivers/input/Kconfig.sbus"
 source "drivers/input/Kconfig.sdl"
 source "drivers/input/Kconfig.stmpe811"
 source "drivers/input/Kconfig.touch"
+source "drivers/input/Kconfig.tsc_keys"
 source "drivers/input/Kconfig.xec"
 source "drivers/input/Kconfig.xpt2046"
 # zephyr-keep-sorted-stop
diff --git a/drivers/input/Kconfig.cy8cmbr3xxx b/drivers/input/Kconfig.cy8cmbr3xxx
new file mode 100644
index 00000000000..d09702109d7
--- /dev/null
+++ b/drivers/input/Kconfig.cy8cmbr3xxx
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Basalte bv
+# SPDX-License-Identifier: Apache-2.0
+
+config INPUT_CY8CMBR3XXX
+	bool "CY8CMBR3XXX capacitive touch sensor driver"
+	default y
+	depends on DT_HAS_CYPRESS_CY8CMBR3XXX_ENABLED
+	select I2C
+	help
+	  Enable driver for cypress CY8CMBR3XXX capacitive
+	  touch sensor.
diff --git a/drivers/input/Kconfig.ft5336 b/drivers/input/Kconfig.ft5336
index 1f09483cc32..782bdb2fdba 100644
--- a/drivers/input/Kconfig.ft5336
+++ b/drivers/input/Kconfig.ft5336
@@ -25,6 +25,7 @@ config INPUT_FT5336_PERIOD
 
 config INPUT_FT5336_INTERRUPT
 	bool "Interrupt"
+	default y if $(dt_compat_any_has_prop,$(DT_COMPAT_FOCALTECH_FT5336),int-gpios)
 	help
 	  Enable interrupt support (requires GPIO).
 
diff --git a/drivers/input/Kconfig.it51xxx b/drivers/input/Kconfig.it51xxx
new file mode 100644
index 00000000000..5bcd9bc103a
--- /dev/null
+++ b/drivers/input/Kconfig.it51xxx
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config INPUT_ITE_IT51XXX_KBD
+	bool "ITE keyboard scanning driver"
+	default y
+	depends on DT_HAS_ITE_IT51XXX_KBD_ENABLED
+	select INPUT_KBD_MATRIX
+	select PINCTRL
+	help
+	  This option enables the ITE keyboard scan driver.
diff --git a/drivers/input/Kconfig.rts5912 b/drivers/input/Kconfig.rts5912
new file mode 100644
index 00000000000..7bd631a2ecd
--- /dev/null
+++ b/drivers/input/Kconfig.rts5912
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Realtek Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+config INPUT_REALTEK_RTS5912_KBD
+	bool "Realtek RTS5912 keyboard scanning driver"
+	default y
+	depends on DT_HAS_REALTEK_RTS5912_KBD_ENABLED
+	select INPUT_KBD_MATRIX
+	help
+	  This option enables the Realtek keyboard scan driver.
diff --git a/drivers/input/Kconfig.tsc_keys b/drivers/input/Kconfig.tsc_keys
new file mode 100644
index 00000000000..57b05321a67
--- /dev/null
+++ b/drivers/input/Kconfig.tsc_keys
@@ -0,0 +1,21 @@
+# Copyright (c) 2024 Arif Balik <arifbalik@outlook.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config INPUT_STM32_TSC_KEYS
+	bool "STM32 TSC touch library"
+	default y
+	depends on DT_HAS_ST_STM32_TSC_ENABLED
+	select RING_BUFFER
+	help
+	  Enable support for STM32 TSC touch library.
+
+config INPUT_STM32_TSC_KEYS_BUFFER_WORD_SIZE
+	int "STM32 TSC touch buffer size in words"
+	default 10
+	depends on INPUT_STM32_TSC_KEYS
+	help
+	  Size of the ring buffer for the STM32 TSC touch library. The size of this
+	  buffer together with the sampling-interval property in the tsc-keys
+	  device tree node determines the time window of interest. A slope value is
+	  calculated between the oldest and the newest value in the buffer to
+	  generate a press or release input event.
diff --git a/drivers/input/input_cy8cmbr3xxx.c b/drivers/input/input_cy8cmbr3xxx.c
new file mode 100644
index 00000000000..a724f0652e5
--- /dev/null
+++ b/drivers/input/input_cy8cmbr3xxx.c
@@ -0,0 +1,445 @@
+/*
+ * Copyright (c) 2025 Basalte bv
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT cypress_cy8cmbr3xxx
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/input/cy8cmbr3xxx.h>
+#include <zephyr/input/input.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(cy8cmbr3xxx, CONFIG_INPUT_LOG_LEVEL);
+
+#define CY8CMBR3XXX_SENSOR_EN                 0x00
+#define CY8CMBR3XXX_FSS_EN                    0x02
+#define CY8CMBR3XXX_TOGGLE_EN                 0x04
+#define CY8CMBR3XXX_LED_ON_EN                 0x06
+#define CY8CMBR3XXX_SENSITIVITY0              0x08
+#define CY8CMBR3XXX_SENSITIVITY1              0x09
+#define CY8CMBR3XXX_SENSITIVITY2              0x0A
+#define CY8CMBR3XXX_SENSITIVITY3              0x0B
+#define CY8CMBR3XXX_BASE_THRESHOLD0           0x0C
+#define CY8CMBR3XXX_BASE_THRESHOLD1           0x0D
+#define CY8CMBR3XXX_FINGER_THRESHOLD2         0x0E
+#define CY8CMBR3XXX_FINGER_THRESHOLD3         0x0F
+#define CY8CMBR3XXX_FINGER_THRESHOLD4         0x10
+#define CY8CMBR3XXX_FINGER_THRESHOLD5         0x11
+#define CY8CMBR3XXX_FINGER_THRESHOLD6         0x12
+#define CY8CMBR3XXX_FINGER_THRESHOLD7         0x13
+#define CY8CMBR3XXX_FINGER_THRESHOLD8         0x14
+#define CY8CMBR3XXX_FINGER_THRESHOLD9         0x15
+#define CY8CMBR3XXX_FINGER_THRESHOLD10        0x16
+#define CY8CMBR3XXX_FINGER_THRESHOLD11        0x17
+#define CY8CMBR3XXX_FINGER_THRESHOLD12        0x18
+#define CY8CMBR3XXX_FINGER_THRESHOLD13        0x19
+#define CY8CMBR3XXX_FINGER_THRESHOLD14        0x1A
+#define CY8CMBR3XXX_FINGER_THRESHOLD15        0x1B
+#define CY8CMBR3XXX_SENSOR_DEBOUNCE           0x1C
+#define CY8CMBR3XXX_BUTTON_HYS                0x1D
+#define CY8CMBR3XXX_BUTTON_LBR                0x1F
+#define CY8CMBR3XXX_BUTTON_NNT                0x20
+#define CY8CMBR3XXX_BUTTON_NT                 0x21
+#define CY8CMBR3XXX_PROX_EN                   0x26
+#define CY8CMBR3XXX_PROX_CFG                  0x27
+#define CY8CMBR3XXX_PROX_CFG2                 0x28
+#define CY8CMBR3XXX_PROX_TOUCH_TH0            0x2A
+#define CY8CMBR3XXX_PROX_TOUCH_TH1            0x2C
+#define CY8CMBR3XXX_PROX_RESOLUTION0          0x2E
+#define CY8CMBR3XXX_PROX_RESOLUTION1          0x2F
+#define CY8CMBR3XXX_PROX_HYS                  0x30
+#define CY8CMBR3XXX_PROX_LBR                  0x32
+#define CY8CMBR3XXX_PROX_NNT                  0x33
+#define CY8CMBR3XXX_PROX_NT                   0x34
+#define CY8CMBR3XXX_PROX_POSITIVE_TH0         0x35
+#define CY8CMBR3XXX_PROX_POSITIVE_TH1         0x36
+#define CY8CMBR3XXX_PROX_NEGATIVE_TH0         0x39
+#define CY8CMBR3XXX_PROX_NEGATIVE_TH1         0x3A
+#define CY8CMBR3XXX_LED_ON_TIME               0x3D
+#define CY8CMBR3XXX_BUZZER_CFG                0x3E
+#define CY8CMBR3XXX_BUZZER_ON_TIME            0x3F
+#define CY8CMBR3XXX_GPO_CFG                   0x40
+#define CY8CMBR3XXX_PWM_DUTYCYCLE_CFG0        0x41
+#define CY8CMBR3XXX_PWM_DUTYCYCLE_CFG1        0x42
+#define CY8CMBR3XXX_PWM_DUTYCYCLE_CFG2        0x43
+#define CY8CMBR3XXX_PWM_DUTYCYCLE_CFG3        0x44
+#define CY8CMBR3XXX_PWM_DUTYCYCLE_CFG4        0x45
+#define CY8CMBR3XXX_PWM_DUTYCYCLE_CFG5        0x46
+#define CY8CMBR3XXX_PWM_DUTYCYCLE_CFG6        0x47
+#define CY8CMBR3XXX_PWM_DUTYCYCLE_CFG7        0x48
+#define CY8CMBR3XXX_SPO_CFG                   0x4C
+#define CY8CMBR3XXX_DEVICE_CFG0               0x4D
+#define CY8CMBR3XXX_DEVICE_CFG1               0x4E
+#define CY8CMBR3XXX_DEVICE_CFG2               0x4F
+#define CY8CMBR3XXX_DEVICE_CFG3               0x50
+#define CY8CMBR3XXX_I2C_ADDR                  0x51
+#define CY8CMBR3XXX_REFRESH_CTRL              0x52
+#define CY8CMBR3XXX_STATE_TIMEOUT             0x55
+#define CY8CMBR3XXX_SLIDER_CFG                0x5D
+#define CY8CMBR3XXX_SLIDER1_CFG               0x61
+#define CY8CMBR3XXX_SLIDER1_RESOLUTION        0x62
+#define CY8CMBR3XXX_SLIDER1_THRESHOLD         0x63
+#define CY8CMBR3XXX_SLIDER2_CFG               0x67
+#define CY8CMBR3XXX_SLIDER2_RESOLUTION        0x68
+#define CY8CMBR3XXX_SLIDER2_THRESHOLD         0x69
+#define CY8CMBR3XXX_SLIDER_LBR                0x71
+#define CY8CMBR3XXX_SLIDER_NNT                0x72
+#define CY8CMBR3XXX_SLIDER_NT                 0x73
+#define CY8CMBR3XXX_SCRATCHPAD0               0x7A
+#define CY8CMBR3XXX_SCRATCHPAD1               0x7B
+#define CY8CMBR3XXX_CONFIG_CRC                0x7E
+#define CY8CMBR3XXX_GPO_OUTPUT_STATE          0x80
+#define CY8CMBR3XXX_SENSOR_ID                 0x82
+#define CY8CMBR3XXX_CTRL_CMD                  0x86
+#define CY8CMBR3XXX_CTRL_CMD_STATUS           0x88
+#define CY8CMBR3XXX_CTRL_CMD_ERR              0x89
+#define CY8CMBR3XXX_SYSTEM_STATUS             0x8A
+#define CY8CMBR3XXX_PREV_CTRL_CMD_CODE        0x8C
+#define CY8CMBR3XXX_FAMILY_ID                 0x8F
+#define CY8CMBR3XXX_DEVICE_ID                 0x90
+#define CY8CMBR3XXX_DEVICE_REV                0x92
+#define CY8CMBR3XXX_CALC_CRC                  0x94
+#define CY8CMBR3XXX_TOTAL_WORKING_SNS         0x97
+#define CY8CMBR3XXX_SNS_CP_HIGH               0x98
+#define CY8CMBR3XXX_SNS_VDD_SHORT             0x9A
+#define CY8CMBR3XXX_SNS_GND_SHORT             0x9C
+#define CY8CMBR3XXX_SNS_SNS_SHORT             0x9E
+#define CY8CMBR3XXX_CMOD_SHIELD_TEST          0xA0
+#define CY8CMBR3XXX_BUTTON_STAT               0xAA
+#define CY8CMBR3XXX_LATCHED_BUTTON_STAT       0xAC
+#define CY8CMBR3XXX_PROX_STAT                 0xAE
+#define CY8CMBR3XXX_LATCHED_PROX_STAT         0xAF
+#define CY8CMBR3XXX_SLIDER1_POSITION          0xB0
+#define CY8CMBR3XXX_LIFTOFF_SLIDER1_POSITION  0xB1
+#define CY8CMBR3XXX_SLIDER2_POSITION          0xB2
+#define CY8CMBR3XXX_LIFTOFF_SLIDER2_POSITION  0xB3
+#define CY8CMBR3XXX_SYNC_COUNTER0             0xB9
+#define CY8CMBR3XXX_DIFFERENCE_COUNT_SENSOR0  0xBA
+#define CY8CMBR3XXX_DIFFERENCE_COUNT_SENSOR1  0xBC
+#define CY8CMBR3XXX_DIFFERENCE_COUNT_SENSOR2  0xBE
+#define CY8CMBR3XXX_DIFFERENCE_COUNT_SENSOR3  0xC0
+#define CY8CMBR3XXX_DIFFERENCE_COUNT_SENSOR4  0xC2
+#define CY8CMBR3XXX_DIFFERENCE_COUNT_SENSOR5  0xC4
+#define CY8CMBR3XXX_DIFFERENCE_COUNT_SENSOR6  0xC6
+#define CY8CMBR3XXX_DIFFERENCE_COUNT_SENSOR7  0xC8
+#define CY8CMBR3XXX_DIFFERENCE_COUNT_SENSOR8  0xCA
+#define CY8CMBR3XXX_DIFFERENCE_COUNT_SENSOR9  0xCC
+#define CY8CMBR3XXX_DIFFERENCE_COUNT_SENSOR10 0xCE
+#define CY8CMBR3XXX_DIFFERENCE_COUNT_SENSOR11 0xD0
+#define CY8CMBR3XXX_DIFFERENCE_COUNT_SENSOR12 0xD2
+#define CY8CMBR3XXX_DIFFERENCE_COUNT_SENSOR13 0xD4
+#define CY8CMBR3XXX_DIFFERENCE_COUNT_SENSOR14 0xD6
+#define CY8CMBR3XXX_DIFFERENCE_COUNT_SENSOR15 0xD8
+#define CY8CMBR3XXX_GPO_DATA                  0xDA
+#define CY8CMBR3XXX_SYNC_COUNTER1             0xDB
+#define CY8CMBR3XXX_DEBUG_SENSOR_ID           0xDC
+#define CY8CMBR3XXX_DEBUG_CP                  0xDD
+#define CY8CMBR3XXX_DEBUG_DIFFERENCE_COUNT0   0xDE
+#define CY8CMBR3XXX_DEBUG_BASELINE0           0xE0
+#define CY8CMBR3XXX_DEBUG_RAW_COUNT0          0xE2
+#define CY8CMBR3XXX_DEBUG_AVG_RAW_COUNT0      0xE4
+#define CY8CMBR3XXX_SYNC_COUNTER2             0xE7
+
+#define CY8CMBR3XXX_CTRL_CMD_CALC_CRC 0x02
+#define CY8CMBR3XXX_CTRL_CMD_RESET    0xFF
+
+/* The controller wakes up from the low-power state on an address match but sends NACK
+ * until it transitions into the Active state. When the device NACKs a transaction, the host is
+ * expected to retry the transaction until it receives an ACK. Typically, no more than 3 retries are
+ * necessary, depending on time between the interrupt and the first i2c transfer or if
+ * no interrupt has caused the initiation of the communication.
+ */
+#define CY8CMBR3XXX_I2C_RETRIES 5
+
+struct cy8cmbr3xxx_config {
+	struct i2c_dt_spec i2c;
+	struct gpio_dt_spec int_gpio;
+	struct gpio_dt_spec rst_gpio;
+	const uint16_t *input_codes;
+	uint8_t input_codes_count;
+	const uint16_t *proximity_codes;
+	uint8_t proximity_codes_count;
+};
+
+struct cy8cmbr3xxx_data {
+	const struct device *dev;
+	struct k_work work;
+	struct gpio_callback int_gpio_cb;
+	uint16_t prev_button_state;
+	uint8_t prev_proximity_state;
+};
+
+static int cy8cmbr3xxx_i2c_read(const struct device *dev, uint8_t address, void *buf, size_t len)
+{
+	const struct cy8cmbr3xxx_config *config = dev->config;
+	int ret;
+
+	for (int i = 0; i < CY8CMBR3XXX_I2C_RETRIES; i++) {
+		ret = i2c_write_read_dt(&config->i2c, &address, sizeof(address), buf, len);
+		if (ret == 0) {
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int cy8cmbr3xxx_i2c_write(const struct device *dev, uint8_t address, const void *buf,
+				 size_t len)
+{
+	const struct cy8cmbr3xxx_config *config = dev->config;
+	int ret;
+
+	for (int i = 0; i < CY8CMBR3XXX_I2C_RETRIES; i++) {
+		ret = i2c_burst_write_dt(&config->i2c, address, buf, len);
+		if (ret == 0) {
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int cy8cmbr3xxx_wait_for_command_completion(const struct device *dev, k_timeout_t timeout)
+{
+	uint8_t current_command;
+	int ret;
+	k_timepoint_t end = sys_timepoint_calc(timeout);
+
+	do {
+		/* Wait for the completion of the command. After a reset command, it can
+		 * happen that the device NACKs for some time.
+		 */
+		ret = cy8cmbr3xxx_i2c_read(dev, CY8CMBR3XXX_CTRL_CMD, &current_command,
+					   sizeof(uint8_t));
+
+		/* As soon as current_command is 0x00, the command is completed */
+		if (ret == 0 && current_command == 0x00) {
+			return 0;
+		}
+
+		k_msleep(1);
+	} while (!sys_timepoint_expired(end));
+
+	LOG_ERR("Wait for command completion timed out");
+
+	return -ETIMEDOUT;
+}
+
+int cy8cmbr3xxx_configure(const struct device *dev, const struct cy8cmbr3xxx_config_data *config)
+{
+	int ret;
+	uint8_t read_config[CY8CMBR3XXX_EZ_CLICK_CONFIG_SIZE];
+	uint8_t command;
+
+	if (config == NULL) {
+		return -EINVAL;
+	}
+
+	/* Read the complete configuration */
+	ret = cy8cmbr3xxx_i2c_read(dev, CY8CMBR3XXX_SENSOR_EN, read_config, sizeof(read_config));
+	if (ret < 0) {
+		LOG_ERR("Failed to read i2c (%d)", ret);
+		return ret;
+	}
+
+	if (memcmp(read_config, config->data, sizeof(config->data)) == 0) {
+		return 0;
+	}
+
+	/* Write the complete configuration of 128 bytes to the CY8CMBR3XXX controller */
+	ret = cy8cmbr3xxx_i2c_write(dev, CY8CMBR3XXX_SENSOR_EN, config->data, sizeof(config->data));
+	if (ret < 0) {
+		LOG_ERR("Failed to write i2c (%d)", ret);
+		return ret;
+	}
+
+	/* The device calculates a CRC checksum over the configuration data in this
+	 * register map and compares the result with the content of CONFIG_CRC. If the
+	 * two values match, the device saves the configuration and the CRC checksum to
+	 * nonvolatile memory.
+	 */
+	command = CY8CMBR3XXX_CTRL_CMD_CALC_CRC;
+	ret = cy8cmbr3xxx_i2c_write(dev, CY8CMBR3XXX_CTRL_CMD, &command, 1);
+	if (ret < 0) {
+		LOG_ERR("Failed to write i2c (%d)", ret);
+		return ret;
+	}
+
+	/* 600ms seems to be sufficient */
+	ret = cy8cmbr3xxx_wait_for_command_completion(dev, K_MSEC(600));
+	if (ret < 0) {
+		LOG_ERR("Failed to wait for command completion (%d)", ret);
+		return ret;
+	}
+
+	/* The device resets itself */
+	command = CY8CMBR3XXX_CTRL_CMD_RESET;
+	ret = cy8cmbr3xxx_i2c_write(dev, CY8CMBR3XXX_CTRL_CMD, &command, 1);
+	if (ret < 0) {
+		LOG_ERR("Failed to write i2c (%d)", ret);
+		return ret;
+	}
+
+	ret = cy8cmbr3xxx_wait_for_command_completion(dev, K_MSEC(50));
+	if (ret < 0) {
+		LOG_ERR("Failed to wait for command completion (%d)", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int cy8cmbr3xxx_process(const struct device *dev)
+{
+	const struct cy8cmbr3xxx_config *config = dev->config;
+	struct cy8cmbr3xxx_data *data = dev->data;
+	int ret;
+	uint16_t button_state, single_button_state;
+	uint8_t proximity_state, single_proximity_state;
+
+	/* Request button status */
+	ret = cy8cmbr3xxx_i2c_read(dev, CY8CMBR3XXX_BUTTON_STAT, &button_state, sizeof(uint16_t));
+	if (ret < 0) {
+		LOG_ERR("Failed to read button status (%d)", ret);
+		return ret;
+	}
+
+	for (uint8_t i = 0; i < config->input_codes_count; i++) {
+		single_button_state = button_state & BIT(i);
+		if (single_button_state != (data->prev_button_state & BIT(i))) {
+			input_report_key(dev, config->input_codes[i], single_button_state, true,
+					 K_FOREVER);
+		}
+	}
+	data->prev_button_state = button_state;
+
+	/* Request proximity status */
+	if (config->proximity_codes_count > 0) {
+		ret = cy8cmbr3xxx_i2c_read(dev, CY8CMBR3XXX_PROX_STAT, &proximity_state,
+					   sizeof(uint8_t));
+		if (ret < 0) {
+			LOG_ERR("Failed to read proximity status (%d)", ret);
+			return ret;
+		}
+
+		for (uint8_t i = 0; i < config->proximity_codes_count; i++) {
+			single_proximity_state = proximity_state & BIT(i);
+			if (single_proximity_state != (data->prev_proximity_state & BIT(i))) {
+				input_report_key(dev, config->proximity_codes[i],
+						 single_proximity_state, true, K_FOREVER);
+			}
+		}
+		data->prev_proximity_state = proximity_state;
+	}
+
+	return 0;
+}
+
+static void cy8cmbr3xxx_work_handler(struct k_work *work)
+{
+	struct cy8cmbr3xxx_data *data = CONTAINER_OF(work, struct cy8cmbr3xxx_data, work);
+
+	cy8cmbr3xxx_process(data->dev);
+}
+
+static void cy8cmbr3xxx_isr_handler(const struct device *dev, struct gpio_callback *cb,
+				    uint32_t pins)
+{
+	struct cy8cmbr3xxx_data *data = CONTAINER_OF(cb, struct cy8cmbr3xxx_data, int_gpio_cb);
+
+	k_work_submit(&data->work);
+}
+
+static void cy8cmbr3xxx_reset(const struct device *dev)
+{
+	const struct cy8cmbr3xxx_config *config = dev->config;
+	int ret;
+
+	if (!gpio_is_ready_dt(&config->rst_gpio)) {
+		LOG_ERR("GPIO controller device not ready");
+		return;
+	}
+
+	ret = gpio_pin_configure_dt(&config->rst_gpio, GPIO_OUTPUT_ACTIVE);
+	if (ret < 0) {
+		LOG_ERR("Could not configure reset GPIO pin (%d)", ret);
+		return;
+	}
+
+	k_usleep(5);
+
+	ret = gpio_pin_set_dt(&config->rst_gpio, 0);
+	if (ret < 0) {
+		LOG_ERR("Could not set reset GPIO pin (%d)", ret);
+		return;
+	}
+}
+
+static int cy8cmbr3xxx_init(const struct device *dev)
+{
+	const struct cy8cmbr3xxx_config *config = dev->config;
+	struct cy8cmbr3xxx_data *data = dev->data;
+	int ret;
+
+	data->dev = dev;
+
+	k_work_init(&data->work, cy8cmbr3xxx_work_handler);
+
+	if (!i2c_is_ready_dt(&config->i2c)) {
+		LOG_ERR("I2C controller device not ready");
+		return -ENODEV;
+	}
+
+	cy8cmbr3xxx_reset(dev);
+
+	if (!gpio_is_ready_dt(&config->int_gpio)) {
+		LOG_ERR("GPIO controller device not ready");
+		return -ENODEV;
+	}
+
+	ret = gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT);
+	if (ret < 0) {
+		LOG_ERR("Could not configure interrupt GPIO pin (%d)", ret);
+		return ret;
+	}
+
+	ret = gpio_pin_interrupt_configure_dt(&config->int_gpio, GPIO_INT_EDGE_TO_ACTIVE);
+	if (ret < 0) {
+		LOG_ERR("Could not configure GPIO interrupt (%d)", ret);
+		return ret;
+	}
+
+	gpio_init_callback(&data->int_gpio_cb, cy8cmbr3xxx_isr_handler, BIT(config->int_gpio.pin));
+
+	ret = gpio_add_callback(config->int_gpio.port, &data->int_gpio_cb);
+	if (ret < 0) {
+		LOG_ERR("Could not set gpio callback (%d)", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+#define CY8CMBR3XXX_INIT(inst)                                                                     \
+	static const uint16_t cy8cmbr3xxx_input_codes_##inst[] = DT_INST_PROP(inst, input_codes);  \
+	static const uint16_t cy8cmbr3xxx_proximity_codes_##inst[] =                               \
+		DT_INST_PROP_OR(inst, proximity_codes, {});                                        \
+	static const struct cy8cmbr3xxx_config cy8cmbr3xxx_config_##inst = {                       \
+		.i2c = I2C_DT_SPEC_INST_GET(inst),                                                 \
+		.int_gpio = GPIO_DT_SPEC_INST_GET(inst, int_gpios),                                \
+		.rst_gpio = GPIO_DT_SPEC_INST_GET(inst, rst_gpios),                                \
+		.input_codes = cy8cmbr3xxx_input_codes_##inst,                                     \
+		.input_codes_count = DT_INST_PROP_LEN(inst, input_codes),                          \
+		.proximity_codes = cy8cmbr3xxx_proximity_codes_##inst,                             \
+		.proximity_codes_count = DT_INST_PROP_LEN_OR(inst, proximity_codes, 0),            \
+	};                                                                                         \
+	static struct cy8cmbr3xxx_data cy8cmbr3xxx_data_##inst;                                    \
+	DEVICE_DT_INST_DEFINE(inst, cy8cmbr3xxx_init, NULL, &cy8cmbr3xxx_data_##inst,              \
+			      &cy8cmbr3xxx_config_##inst, POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, \
+			      NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(CY8CMBR3XXX_INIT)
diff --git a/drivers/input/input_ite_it51xxx_kbd.c b/drivers/input/input_ite_it51xxx_kbd.c
new file mode 100644
index 00000000000..388fdc6f292
--- /dev/null
+++ b/drivers/input/input_ite_it51xxx_kbd.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ite_it51xxx_kbd
+
+#include <errno.h>
+#include <soc.h>
+#include <soc_dt.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/interrupt_controller/wuc_ite_it51xxx.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/dt-bindings/interrupt-controller/ite-it51xxx-wuc.h>
+#include <zephyr/input/input.h>
+#include <zephyr/input/input_kbd_matrix.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/util_macro.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(input_ite_it51xxx_kbd);
+
+#define KEYBOARD_KSI_PIN_COUNT IT8XXX2_DT_INST_WUCCTRL_LEN(0)
+
+/* 0x04: Keyboard Scan In Data */
+#define REG_KBS_KSI 0x04
+/* 0x80: Keyboard Scan Out Data (3 bytes value and 4 bytes aligned) */
+#define REG_KBS_KSO 0x80
+
+struct it51xxx_kbd_wuc_map_cfg {
+	/* WUC control device structure */
+	const struct device *wucs;
+	/* WUC pin mask */
+	uint8_t mask;
+};
+
+struct it51xxx_kbd_config {
+	struct input_kbd_matrix_common_config common;
+	/* Keyboard scan controller base address */
+	uintptr_t base;
+	/* Keyboard scan input (KSI) wake-up irq */
+	int irq;
+	/* KSI[7:0] wake-up input source configuration list */
+	const struct it51xxx_kbd_wuc_map_cfg *wuc_map_list;
+	/* keyboard scan alternate configuration */
+	const struct pinctrl_dev_config *pcfg;
+	/* KSO16 GPIO cells */
+	struct gpio_dt_spec kso16_gpios;
+	/* KSO17 GPIO cells */
+	struct gpio_dt_spec kso17_gpios;
+	/* Mask of signals to ignore */
+	uint32_t kso_ignore_mask;
+};
+
+struct it51xxx_kbd_data {
+	struct input_kbd_matrix_common_data common;
+	/* KSI[7:0] wake-up interrupt status mask */
+	uint8_t ksi_pin_mask;
+};
+
+INPUT_KBD_STRUCT_CHECK(struct it51xxx_kbd_config, struct it51xxx_kbd_data);
+
+static void it51xxx_kbd_drive_column(const struct device *dev, int col)
+{
+	const struct it51xxx_kbd_config *const config = dev->config;
+	const struct input_kbd_matrix_common_config *common = &config->common;
+	const uintptr_t base = config->base;
+	const uint32_t kso_mask = BIT_MASK(common->col_size) & ~config->kso_ignore_mask;
+	uint32_t kso_val, reg_val;
+	unsigned int key;
+
+	if (col == INPUT_KBD_MATRIX_COLUMN_DRIVE_NONE) {
+		/* Tri-state all outputs */
+		kso_val = kso_mask;
+	} else if (col == INPUT_KBD_MATRIX_COLUMN_DRIVE_ALL) {
+		/* Assert all outputs */
+		kso_val = 0;
+	} else {
+		/* Assert a single output */
+		kso_val = kso_mask ^ BIT(col);
+	}
+
+	/*
+	 * Set keyboard scan output data, disable global interrupts for critical section.
+	 * The KBS_KSO registers contains both keyboard and GPIO output settings.
+	 * Not all bits are for the keyboard will be driven, so a critical section
+	 * is needed to avoid race conditions.
+	 */
+	key = irq_lock();
+	reg_val = sys_read32(base + REG_KBS_KSO) & ~kso_mask;
+	sys_write32((reg_val | (kso_val & kso_mask)), base + REG_KBS_KSO);
+	irq_unlock(key);
+}
+
+static kbd_row_t it51xxx_kbd_read_row(const struct device *dev)
+{
+	const struct it51xxx_kbd_config *const config = dev->config;
+	const uintptr_t base = config->base;
+	uint8_t reg_val;
+
+	/* Bits are active-low, so toggle it (return 1 means key pressed) */
+	reg_val = sys_read8(base + REG_KBS_KSI);
+
+	return reg_val ^ 0xff;
+}
+
+static void it51xxx_kbd_clear_status(const struct device *dev)
+{
+	const struct it51xxx_kbd_config *const config = dev->config;
+	struct it51xxx_kbd_data *data = dev->data;
+
+	/*
+	 * W/C wakeup interrupt status of KSI[7:0] pins
+	 *
+	 * NOTE: We want to clear the status as soon as possible,
+	 *       so clear KSI[7:0] pins at a time.
+	 */
+	it51xxx_wuc_clear_status(config->wuc_map_list[0].wucs, data->ksi_pin_mask);
+
+	/* W/C interrupt status of KSI[7:0] pins */
+	ite_intc_isr_clear(config->irq);
+}
+
+static void it51xxx_kbd_isr(const struct device *dev)
+{
+	it51xxx_kbd_clear_status(dev);
+
+	input_kbd_matrix_poll_start(dev);
+}
+
+static void it51xxx_kbd_set_detect_mode(const struct device *dev, bool enable)
+{
+	const struct it51xxx_kbd_config *const config = dev->config;
+
+	if (enable) {
+		it51xxx_kbd_clear_status(dev);
+
+		irq_enable(config->irq);
+	} else {
+		irq_disable(config->irq);
+	}
+}
+
+static int it51xxx_kbd_init(const struct device *dev)
+{
+	const struct it51xxx_kbd_config *const config = dev->config;
+	const struct input_kbd_matrix_common_config *common = &config->common;
+	struct it51xxx_kbd_data *data = dev->data;
+	const uintptr_t base = config->base;
+	const uint32_t kso_mask = BIT_MASK(common->col_size) & ~config->kso_ignore_mask;
+	int status;
+	uint32_t reg_val;
+
+	/* Disable wakeup and interrupt of KSI pins before configuring */
+	it51xxx_kbd_set_detect_mode(dev, false);
+
+	if (common->col_size > 16) {
+		/*
+		 * For KSO[16] and KSO[17]:
+		 * Set pull up and open-drain by their GPIO ports corresponding
+		 * GPCRx and GPOTx registers.
+		 */
+		gpio_pin_configure_dt(&config->kso16_gpios, (GPIO_OPEN_DRAIN | GPIO_PULL_UP));
+		gpio_pin_configure_dt(&config->kso17_gpios, (GPIO_OPEN_DRAIN | GPIO_PULL_UP));
+	}
+	/* Enable keyboard scan alternate function */
+	status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+	if (status < 0) {
+		LOG_ERR("Failed to enable keyboard scan alternate function");
+		return status;
+	}
+
+	/* KSO[col_size:0] pins output low */
+	reg_val = sys_read32(base + REG_KBS_KSO) & ~kso_mask;
+	sys_write32(reg_val, base + REG_KBS_KSO);
+
+	for (int i = 0; i < KEYBOARD_KSI_PIN_COUNT; i++) {
+		/* Select wakeup interrupt falling-edge triggered of KSI[7:0] pins */
+		it51xxx_wuc_set_polarity(config->wuc_map_list[i].wucs, config->wuc_map_list[i].mask,
+					 WUC_TYPE_EDGE_FALLING);
+		/* W/C wakeup interrupt status of KSI[7:0] pins */
+		it51xxx_wuc_clear_status(config->wuc_map_list[i].wucs,
+					 config->wuc_map_list[i].mask);
+		/* Enable wakeup interrupt of KSI[7:0] pins */
+		it51xxx_wuc_enable(config->wuc_map_list[i].wucs, config->wuc_map_list[i].mask);
+
+		/*
+		 * We want to clear KSI[7:0] pins status at a time when wakeup
+		 * interrupt fire, so gather the KSI[7:0] pin mask value here.
+		 */
+		if (config->wuc_map_list[i].wucs != config->wuc_map_list[0].wucs) {
+			LOG_ERR("KSI%d pin isn't in the same wuc node!", i);
+		}
+		data->ksi_pin_mask |= config->wuc_map_list[i].mask;
+	}
+
+	/* W/C interrupt status of KSI[7:0] pins */
+	ite_intc_isr_clear(config->irq);
+
+	irq_connect_dynamic(DT_INST_IRQN(0), 0, (void (*)(const void *))it51xxx_kbd_isr,
+			    (const void *)dev, 0);
+
+	return input_kbd_matrix_common_init(dev);
+}
+
+static const struct it51xxx_kbd_wuc_map_cfg it51xxx_kbd_wuc[IT8XXX2_DT_INST_WUCCTRL_LEN(0)] =
+	IT8XXX2_DT_WUC_ITEMS_LIST(0);
+
+PINCTRL_DT_INST_DEFINE(0);
+
+INPUT_KBD_MATRIX_DT_INST_DEFINE(0);
+
+static const struct input_kbd_matrix_api it51xxx_kbd_api = {
+	.drive_column = it51xxx_kbd_drive_column,
+	.read_row = it51xxx_kbd_read_row,
+	.set_detect_mode = it51xxx_kbd_set_detect_mode,
+};
+
+static const struct it51xxx_kbd_config it51xxx_kbd_cfg_0 = {
+	.common = INPUT_KBD_MATRIX_DT_INST_COMMON_CONFIG_INIT(0, &it51xxx_kbd_api),
+	.base = DT_INST_REG_ADDR(0),
+	.irq = DT_INST_IRQN(0),
+	.wuc_map_list = it51xxx_kbd_wuc,
+	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
+	.kso16_gpios = GPIO_DT_SPEC_INST_GET(0, kso16_gpios),
+	.kso17_gpios = GPIO_DT_SPEC_INST_GET(0, kso17_gpios),
+	.kso_ignore_mask = DT_INST_PROP(0, kso_ignore_mask),
+};
+
+static struct it51xxx_kbd_data it51xxx_kbd_data_0;
+
+PM_DEVICE_DT_INST_DEFINE(0, input_kbd_matrix_pm_action);
+
+DEVICE_DT_INST_DEFINE(0, &it51xxx_kbd_init, PM_DEVICE_DT_INST_GET(0), &it51xxx_kbd_data_0,
+		      &it51xxx_kbd_cfg_0, POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, NULL);
+
+BUILD_ASSERT(!IS_ENABLED(CONFIG_PM_DEVICE_SYSTEM_MANAGED) || IS_ENABLED(CONFIG_PM_DEVICE_RUNTIME),
+	     "CONFIG_PM_DEVICE_RUNTIME must be enabled when using CONFIG_PM_DEVICE_SYSTEM_MANAGED");
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
+	     "only one ite,it51xxx-kbd compatible node can be supported");
+BUILD_ASSERT(IN_RANGE(DT_INST_PROP(0, row_size), 1, 8), "invalid row-size");
+BUILD_ASSERT(IN_RANGE(DT_INST_PROP(0, col_size), 1, 18), "invalid col-size");
diff --git a/drivers/input/input_realtek_rts5912_kbd.c b/drivers/input/input_realtek_rts5912_kbd.c
new file mode 100644
index 00000000000..ba8314a2932
--- /dev/null
+++ b/drivers/input/input_realtek_rts5912_kbd.c
@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2025 Realtek Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT realtek_rts5912_kbd
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/clock_control_rts5912.h>
+#include <zephyr/irq.h>
+#include <zephyr/input/input.h>
+#include <zephyr/input/input_kbd_matrix.h>
+#include <zephyr/sys/util_macro.h>
+#include "reg/reg_kbm.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(input_realtek_rts5912_kbd, CONFIG_INPUT_LOG_LEVEL);
+
+struct rts5912_kbd_config {
+	struct input_kbd_matrix_common_config common;
+	/* Keyboard scan controller base address */
+	volatile struct kbm_regs *base;
+	/* Keyboard scan input (KSI) wake-up irq */
+	uint32_t irq;
+	/* KSI/KSO keyboard scan alternate configuration */
+	const struct pinctrl_dev_config *pcfg;
+	const struct device *clk_dev;
+	struct rts5912_sccon_subsys sccon_cfg;
+	/* For user ignore specific pin of kso*/
+	uint32_t kso_ignore_mask;
+};
+
+struct rts5912_kbd_data {
+	struct input_kbd_matrix_common_data common;
+};
+
+INPUT_KBD_STRUCT_CHECK(struct rts5912_kbd_config, struct rts5912_kbd_data);
+
+static void rts5912_kbd_drive_column(const struct device *dev, int col)
+{
+	const struct rts5912_kbd_config *config = dev->config;
+	const struct input_kbd_matrix_common_config *common = &config->common;
+	volatile struct kbm_regs *inst = config->base;
+	const uint32_t kso_mask = BIT_MASK(common->col_size) & ~config->kso_ignore_mask;
+	uint32_t kso_val;
+	uint32_t key;
+
+	/* Tri-state all outputs */
+	if (col == INPUT_KBD_MATRIX_COLUMN_DRIVE_NONE) {
+		kso_val = kso_mask;
+		/* Assert all outputs */
+	} else if (col == INPUT_KBD_MATRIX_COLUMN_DRIVE_ALL) {
+		kso_val = 0;
+		/* Assert a single output */
+	} else {
+		kso_val = kso_mask ^ BIT(col);
+	}
+
+	/* Set KSO output data */
+	key = irq_lock();
+	inst->scan_out = kso_val;
+	irq_unlock(key);
+}
+
+static kbd_row_t rts5912_kbd_read_row(const struct device *dev)
+{
+	const struct rts5912_kbd_config *config = dev->config;
+	volatile struct kbm_regs *inst = config->base;
+	const struct input_kbd_matrix_common_config *common = &config->common;
+	const uint32_t ksi_mask = BIT_MASK(common->row_size);
+
+	/* Bits are active-low, so toggle it (return 1 means key pressed) */
+	return (inst->scan_in ^ ksi_mask);
+}
+
+static void rts5912_intc_isr_clear(const struct device *dev)
+{
+	const struct rts5912_kbd_config *config = dev->config;
+	volatile struct kbm_regs *inst = config->base;
+
+	inst->ctrl |= KBM_CTRL_KSIINTSTS_Msk;
+}
+
+static void rts5912_kbd_isr(const struct device *dev)
+{
+	/* W/C interrupt status of KSI pins */
+	rts5912_intc_isr_clear(dev);
+	input_kbd_matrix_poll_start(dev);
+}
+
+static void rts5912_kbd_set_detect_mode(const struct device *dev, bool enable)
+{
+	const struct rts5912_kbd_config *config = dev->config;
+
+	if (enable) {
+		/* W/C interrupt status of KSI pins */
+		rts5912_intc_isr_clear(dev);
+
+		irq_enable(config->irq);
+	} else {
+		irq_disable(config->irq);
+	}
+}
+
+static int rts5912_kbd_init(const struct device *dev)
+{
+	const struct rts5912_kbd_config *config = dev->config;
+	const struct input_kbd_matrix_common_config *common = &config->common;
+
+	volatile struct kbm_regs *inst = config->base;
+
+	const uint32_t kso_mask = BIT_MASK(common->col_size) & ~config->kso_ignore_mask;
+	const uint32_t ksi_mask = BIT_MASK(common->row_size);
+
+	uint32_t status;
+
+	/* Disable wakeup and interrupt of KSI pins before configuring */
+	rts5912_kbd_set_detect_mode(dev, false);
+
+	/*
+	 * Enable the internal pull-up and kbs mode of the KSI pins.
+	 * Enable the internal pull-up and kbs mode of the KSO pins.
+	 * Enable the open-drain mode of the KSO pins.
+	 */
+	status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+	if (status < 0) {
+		LOG_ERR("Failed to configure KSI and KSO pins");
+		return status;
+	}
+
+	if (!device_is_ready(config->clk_dev)) {
+		LOG_ERR("clock kbd device not ready");
+		return -ENODEV;
+	}
+
+	status = clock_control_on(config->clk_dev, (clock_control_subsys_t)&config->sccon_cfg);
+	if (status != 0) {
+		LOG_ERR("kbd clock power on fail");
+		return status;
+	}
+
+	/* KSO pins output low */
+	inst->scan_out = 0x00;
+
+	/* Enable KSI 8 if RAW Size more than 8*/
+	if (ksi_mask & BIT(8)) {
+		inst->ctrl |= KBM_CTRL_KSI8EN_Msk;
+	}
+
+	/* Enable KSI 9 if RAW Size more than 9*/
+	if (ksi_mask & BIT(9)) {
+		inst->ctrl |= KBM_CTRL_KSI9EN_Msk;
+	}
+
+	/* Enable KSO 18 if COL Size more than 18*/
+	if (kso_mask & BIT(18)) {
+		inst->ctrl |= KBM_CTRL_KSO18EN_Msk;
+	}
+
+	/* Enable KSO 19 if COL Size more than 19*/
+	if (kso_mask & BIT(19)) {
+		inst->ctrl |= KBM_CTRL_KSO19EN_Msk;
+	}
+
+	/* Enable KSO OpenDrain Output Type */
+	inst->ctrl |= KBM_CTRL_KSOTYPE_Msk;
+
+	/* Enable Scan Interrupt*/
+	inst->int_en |= ksi_mask;
+
+	/* W/C interrupt status of KSI pins */
+	rts5912_intc_isr_clear(dev);
+
+	/* Interrupts are enabled in the thread function */
+	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
+		    rts5912_kbd_isr, DEVICE_DT_INST_GET(0), 0);
+
+	return input_kbd_matrix_common_init(dev);
+}
+
+PINCTRL_DT_INST_DEFINE(0);
+
+INPUT_KBD_MATRIX_DT_INST_DEFINE(0);
+
+static const struct input_kbd_matrix_api rts5912_kbd_api = {
+	.drive_column = rts5912_kbd_drive_column,
+	.read_row = rts5912_kbd_read_row,
+	.set_detect_mode = rts5912_kbd_set_detect_mode,
+};
+
+static const struct rts5912_kbd_config rts5912_kbd_cfg_0 = {
+	.common = INPUT_KBD_MATRIX_DT_INST_COMMON_CONFIG_INIT(0, &rts5912_kbd_api),
+	.base = (volatile struct kbm_regs *)DT_INST_REG_ADDR_BY_IDX(0, 0),
+	.irq = DT_INST_IRQN(0),
+	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
+	.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
+	.sccon_cfg = {
+		.clk_grp = DT_CLOCKS_CELL(DT_NODELABEL(kbd), clk_grp),
+		.clk_idx = DT_CLOCKS_CELL(DT_NODELABEL(kbd), clk_idx),
+	},
+	.kso_ignore_mask = DT_INST_PROP_OR(0, kso_ignore_mask, 0x00),
+};
+
+static struct rts5912_kbd_data rts5912_kbd_data_0;
+
+PM_DEVICE_DT_INST_DEFINE(0, input_kbd_matrix_pm_action);
+
+DEVICE_DT_INST_DEFINE(0, &rts5912_kbd_init, PM_DEVICE_DT_INST_GET(0), &rts5912_kbd_data_0,
+		      &rts5912_kbd_cfg_0, POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, NULL);
+
+BUILD_ASSERT(!IS_ENABLED(CONFIG_PM_DEVICE_SYSTEM_MANAGED) || IS_ENABLED(CONFIG_PM_DEVICE_RUNTIME),
+	     "CONFIG_PM_DEVICE_RUNTIME must be enabled when using CONFIG_PM_DEVICE_SYSTEM_MANAGED");
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
+	     "only one realtek,rts5912-kbd compatible node can be supported");
+BUILD_ASSERT(IN_RANGE(DT_INST_PROP(0, row_size), 1, 9), "invalid row-size");
+BUILD_ASSERT(IN_RANGE(DT_INST_PROP(0, col_size), 1, 19), "invalid col-size");
diff --git a/drivers/input/input_sbus.c b/drivers/input/input_sbus.c
index b9eb44e03e6..80f365e0be7 100644
--- a/drivers/input/input_sbus.c
+++ b/drivers/input/input_sbus.c
@@ -123,7 +123,7 @@ static void input_sbus_input_report_thread(const struct device *dev, void *dummy
 
 	uint8_t i, channel;
 	uint8_t *sbus_channel_data = &data->sbus_frame[1]; /* Omit header */
-	uint16_t value;
+	uint32_t value;
 	int bits_read;
 	unsigned int key;
 	int ret;
@@ -247,7 +247,7 @@ static void sbus_uart_isr(const struct device *uart_dev, void *user_data)
 		return;
 	}
 
-	while (uart_irq_rx_ready(uart_dev) && data->xfer_bytes <= SBUS_FRAME_LEN) {
+	while (uart_irq_rx_ready(uart_dev) && data->xfer_bytes < SBUS_FRAME_LEN) {
 		if (data->in_sync) {
 			if (data->xfer_bytes == 0) {
 				data->last_rx_time = k_uptime_get_32();
@@ -324,10 +324,10 @@ static int input_sbus_init(const struct device *dev)
 		return ret;
 	}
 
-	uart_irq_rx_enable(config->uart_dev);
-
 	k_sem_init(&data->report_lock, 0, 1);
 
+	uart_irq_rx_enable(config->uart_dev);
+
 	k_thread_create(&data->thread, data->thread_stack,
 			K_KERNEL_STACK_SIZEOF(data->thread_stack),
 			(k_thread_entry_t)input_sbus_input_report_thread, (void *)dev, NULL, NULL,
diff --git a/drivers/input/input_sdl_touch.c b/drivers/input/input_sdl_touch.c
index 14ed5469e17..1034919d439 100644
--- a/drivers/input/input_sdl_touch.c
+++ b/drivers/input/input_sdl_touch.c
@@ -41,7 +41,11 @@ static int sdl_init(const struct device *dev)
 	return 0;
 }
 
-static struct sdl_input_data sdl_data_0;
-
-DEVICE_DT_INST_DEFINE(0, sdl_init, NULL, &sdl_data_0, NULL,
-		    POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, NULL);
+#define INPUT_SDL_TOUCH_DEFINE(inst)                                                               \
+	static struct sdl_input_data sdl_data_##inst = {                                           \
+		.display_dev = DEVICE_DT_GET_OR_NULL(DT_INST_PHANDLE(inst, display)),              \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(inst, sdl_init, NULL, &sdl_data_##inst, NULL, POST_KERNEL,           \
+			      CONFIG_INPUT_INIT_PRIORITY, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(INPUT_SDL_TOUCH_DEFINE)
diff --git a/drivers/input/input_sdl_touch_bottom.c b/drivers/input/input_sdl_touch_bottom.c
index eb03f89ca11..266dcccd8db 100644
--- a/drivers/input/input_sdl_touch_bottom.c
+++ b/drivers/input/input_sdl_touch_bottom.c
@@ -8,10 +8,41 @@
 #include <SDL.h>
 #include "input_sdl_touch_bottom.h"
 
+static bool event_targets_display(SDL_Event *event, struct sdl_input_data *data)
+{
+	SDL_Window *window = NULL;
+	const void *display_dev;
+
+	if (!data->display_dev) {
+		return true;
+	}
+
+	if (event->type == SDL_MOUSEBUTTONDOWN || event->type == SDL_MOUSEBUTTONUP) {
+		window = SDL_GetWindowFromID(event->button.windowID);
+	} else if (event->type == SDL_MOUSEMOTION) {
+		window = SDL_GetWindowFromID(event->motion.windowID);
+	} else {
+		return false;
+	}
+
+	if (!window) {
+		return false;
+	}
+
+	/* Get the zephyr display associated with the window */
+	display_dev = SDL_GetWindowData(window, "zephyr_display");
+
+	return !display_dev || display_dev == data->display_dev;
+}
+
 static int sdl_filter(void *arg, SDL_Event *event)
 {
 	struct sdl_input_data *data = arg;
 
+	if (!event_targets_display(event, data)) {
+		return 1;
+	}
+
 	switch (event->type) {
 	case SDL_MOUSEBUTTONUP:
 		data->pressed = false;
diff --git a/drivers/input/input_sdl_touch_bottom.h b/drivers/input/input_sdl_touch_bottom.h
index 397715686ca..8472517b62c 100644
--- a/drivers/input/input_sdl_touch_bottom.h
+++ b/drivers/input/input_sdl_touch_bottom.h
@@ -22,6 +22,7 @@ extern "C" {
 
 struct sdl_input_data {
 	const void *dev; /* device structure pointer */
+	const void *display_dev;
 	void (*callback)(struct sdl_input_data *data);
 	int x;
 	int y;
diff --git a/drivers/input/input_tsc_keys.c b/drivers/input/input_tsc_keys.c
new file mode 100644
index 00000000000..a09afc53782
--- /dev/null
+++ b/drivers/input/input_tsc_keys.c
@@ -0,0 +1,446 @@
+/*
+ * Copyright (c) 2024 Arif Balik <arifbalik@outlook.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc.h>
+#include <stdlib.h>
+#include <stdbool.h>
+#include <autoconf.h>
+#include <zephyr/irq.h>
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/input/input.h>
+#include <zephyr/drivers/reset.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/ring_buffer.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/clock_control/stm32_clock_control.h>
+
+LOG_MODULE_REGISTER(tsc_keys, CONFIG_INPUT_LOG_LEVEL);
+
+#define DT_DRV_COMPAT st_stm32_tsc
+
+/* each group only has 4 configurable I/O */
+#define GET_GROUP_BITS(val, group) (uint32_t)(((val) & 0x0f) << ((group - 1) * 4))
+
+struct stm32_tsc_group_config {
+	uint8_t group;
+	uint8_t channel_ios;
+	uint8_t sampling_io;
+	bool use_as_shield;
+};
+
+typedef void (*stm32_tsc_group_ready_cb)(uint32_t count_value, void *user_data);
+
+struct stm32_tsc_group_data {
+	stm32_tsc_group_ready_cb cb;
+	void *user_data;
+};
+
+struct stm32_tsc_config {
+	const TSC_TypeDef *tsc;
+	const struct stm32_pclken *pclken;
+	struct reset_dt_spec reset;
+	const struct pinctrl_dev_config *pcfg;
+	const struct stm32_tsc_group_config *group_config;
+	struct stm32_tsc_group_data *group_data;
+	uint8_t group_cnt;
+
+	uint32_t pgpsc;
+	uint8_t ctph;
+	uint8_t ctpl;
+	bool spread_spectrum;
+	uint8_t sscpsc;
+	uint8_t ssd;
+	uint16_t max_count;
+	bool iodef;
+	bool sync_acq;
+	bool sync_pol;
+	void (*irq_func)(void);
+};
+
+int stm32_tsc_group_register_callback(const struct device *dev, uint8_t group_idx,
+				      stm32_tsc_group_ready_cb cb, void *user_data)
+{
+	const struct stm32_tsc_config *config = dev->config;
+
+	if (group_idx >= config->group_cnt) {
+		LOG_ERR("%s: group index %d is out of range", dev->name, group_idx);
+		return -EINVAL;
+	}
+
+	struct stm32_tsc_group_data *group_data = &config->group_data[group_idx];
+
+	group_data->cb = cb;
+	group_data->user_data = user_data;
+
+	return 0;
+}
+
+void stm32_tsc_start(const struct device *dev)
+{
+	const struct stm32_tsc_config *config = dev->config;
+
+	/* clear interrupts */
+	sys_set_bits((mem_addr_t)&config->tsc->ICR, TSC_ICR_EOAIC | TSC_ICR_MCEIC);
+
+	/* enable end of acquisition and max count error interrupts */
+	sys_set_bits((mem_addr_t)&config->tsc->IER, TSC_IER_EOAIE | TSC_IER_MCEIE);
+
+	/* TODO: When sync acqusition mode is enabled, both this bit and an external input signal
+	 * should be set. When the acqusition stops this bit is cleared, so even if a sync signal is
+	 * present, the next acqusition will not start until this bit is set again.
+	 */
+	/* start acquisition */
+	sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_START_Pos);
+}
+
+static int get_group_index(const struct device *dev, uint8_t group, uint8_t *group_idx)
+{
+	const struct stm32_tsc_config *config = dev->config;
+	const struct stm32_tsc_group_config *groups = config->group_config;
+
+	for (int i = 0; i < config->group_cnt; i++) {
+		if (groups[i].group == group) {
+			*group_idx = i;
+			return 0;
+		}
+	}
+
+	return -ENODEV;
+}
+
+static int stm32_tsc_handle_incoming_data(const struct device *dev)
+{
+	const struct stm32_tsc_config *config = dev->config;
+
+	if (sys_test_bit((mem_addr_t)&config->tsc->ISR, TSC_ISR_MCEF_Pos)) {
+		/* clear max count error flag */
+		sys_set_bit((mem_addr_t)&config->tsc->ICR, TSC_ICR_MCEIC_Pos);
+		LOG_ERR("%s: max count error", dev->name);
+		LOG_HEXDUMP_DBG(config->tsc, sizeof(TSC_TypeDef), "TSC Registers");
+		return -EIO;
+	}
+
+	if (sys_test_bit((mem_addr_t)&config->tsc->ISR, TSC_ISR_EOAF_Pos)) {
+		/* clear end of acquisition flag */
+		sys_set_bit((mem_addr_t)&config->tsc->ICR, TSC_ICR_EOAIC_Pos);
+
+		/* read values */
+		for (uint8_t i = 0; i < config->group_cnt; i++) {
+			const struct stm32_tsc_group_config *group = &config->group_config[i];
+			uint32_t group_bit = BIT(group->group - 1) << 16;
+
+			if (config->tsc->IOGCSR & group_bit) {
+				uint32_t count_value = sys_read32(
+					(mem_addr_t)&config->tsc->IOGXCR[group->group - 1]);
+
+				uint8_t group_idx = 0;
+
+				int ret = get_group_index(dev, group->group, &group_idx);
+
+				if (ret < 0) {
+					LOG_ERR("%s: group %d not found", dev->name, group->group);
+					return ret;
+				}
+
+				struct stm32_tsc_group_data *data = &config->group_data[group_idx];
+
+				if (data->cb) {
+					data->cb(count_value, data->user_data);
+				}
+			}
+		}
+	}
+
+	return 0;
+}
+
+static void stm32_tsc_isr(const struct device *dev)
+{
+	const struct stm32_tsc_config *config = dev->config;
+
+	/* disable interrupts */
+	sys_clear_bits((mem_addr_t)&config->tsc->IER, TSC_IER_EOAIE | TSC_IER_MCEIE);
+
+	stm32_tsc_handle_incoming_data(dev);
+}
+
+static int stm32_tsc_init(const struct device *dev)
+{
+	const struct stm32_tsc_config *config = dev->config;
+	const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
+
+	int ret;
+
+	if (!device_is_ready(clk)) {
+		LOG_ERR("%s: clock controller device not ready", dev->name);
+		return -ENODEV;
+	}
+
+	/* reset TSC values to default */
+	ret = reset_line_toggle_dt(&config->reset);
+	if (ret < 0) {
+		LOG_ERR("Failed to reset %s (%d)", dev->name, ret);
+		return ret;
+	}
+
+	ret = clock_control_on(clk, (clock_control_subsys_t)&config->pclken[0]);
+	if (ret < 0) {
+		LOG_ERR("Failed to enable clock for %s (%d)", dev->name, ret);
+		return ret;
+	}
+
+	ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret < 0) {
+		LOG_ERR("Failed to configure %s pins (%d)", dev->name, ret);
+		return ret;
+	}
+
+	/* set ctph (bits 31:28) and ctpl (bits 27:24) */
+	sys_set_bits((mem_addr_t)&config->tsc->CR, (((config->ctph - 1) << 4) | (config->ctpl - 1))
+							   << TSC_CR_CTPL_Pos);
+
+	/* set spread spectrum deviation (bits 23:17) */
+	sys_set_bits((mem_addr_t)&config->tsc->CR, config->ssd << TSC_CR_SSD_Pos);
+
+	/* set pulse generator prescaler (bits 14:12) */
+	sys_set_bits((mem_addr_t)&config->tsc->CR, config->pgpsc << TSC_CR_PGPSC_Pos);
+
+	/* set max count value (bits 7:5) */
+	sys_set_bits((mem_addr_t)&config->tsc->CR, config->max_count << TSC_CR_MCV_Pos);
+
+	/* set spread spectrum prescaler (bit 15) */
+	if (config->sscpsc == 2) {
+		sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_SSPSC_Pos);
+	}
+
+	/* set sync bit polarity */
+	if (config->sync_pol) {
+		sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_SYNCPOL_Pos);
+	}
+
+	/* set sync acquisition */
+	if (config->sync_acq) {
+		sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_AM_Pos);
+	}
+
+	/* set I/O default mode */
+	if (config->iodef) {
+		sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_IODEF_Pos);
+	}
+
+	/* set spread spectrum */
+	if (config->spread_spectrum) {
+		sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_SSE_Pos);
+	}
+
+	/* group configuration */
+	for (int i = 0; i < config->group_cnt; i++) {
+		const struct stm32_tsc_group_config *group = &config->group_config[i];
+
+		if (group->channel_ios & group->sampling_io) {
+			LOG_ERR("%s: group %d has the same channel and sampling I/O", dev->name,
+				group->group);
+			return -EINVAL;
+		}
+
+		/* if use_as_shield is true, the channel I/Os are used as shield, and can only have
+		 * values 1,2,4,8
+		 */
+		if (group->use_as_shield && group->channel_ios != 1 && group->channel_ios != 2 &&
+		    group->channel_ios != 4 && group->channel_ios != 8) {
+			LOG_ERR("%s: group %d is used as shield, but has invalid channel I/Os. "
+				"Can only have one",
+				dev->name, group->group);
+			return -EINVAL;
+		}
+
+		/* clear schmitt trigger hysteresis for enabled I/Os */
+		sys_clear_bits(
+			(mem_addr_t)&config->tsc->IOHCR,
+			GET_GROUP_BITS(group->channel_ios | group->sampling_io, group->group));
+
+		/* set channel I/Os */
+		sys_set_bits((mem_addr_t)&config->tsc->IOCCR,
+			     GET_GROUP_BITS(group->channel_ios, group->group));
+
+		/* set sampling I/O */
+		sys_set_bits((mem_addr_t)&config->tsc->IOSCR,
+			     GET_GROUP_BITS(group->sampling_io, group->group));
+
+		/* enable group */
+		if (!group->use_as_shield) {
+			sys_set_bit((mem_addr_t)&config->tsc->IOGCSR, group->group - 1);
+		}
+	}
+
+	/* disable interrupts */
+	sys_clear_bits((mem_addr_t)&config->tsc->IER, TSC_IER_EOAIE | TSC_IER_MCEIE);
+
+	/* clear interrupts */
+	sys_set_bits((mem_addr_t)&config->tsc->ICR, TSC_ICR_EOAIC | TSC_ICR_MCEIC);
+
+	/* enable peripheral */
+	sys_set_bit((mem_addr_t)&config->tsc->CR, TSC_CR_TSCE_Pos);
+
+	config->irq_func();
+
+	return 0;
+}
+
+#define STM32_TSC_GROUP_DEFINE(node_id)                                                            \
+	{                                                                                          \
+		.group = DT_PROP(node_id, group),                                                  \
+		.channel_ios = DT_PROP(node_id, channel_ios),                                      \
+		.sampling_io = DT_PROP(node_id, sampling_io),                                      \
+		.use_as_shield = DT_PROP(node_id, st_use_as_shield),                               \
+	}
+
+#define STM32_TSC_INIT(index)                                                                      \
+	static const struct stm32_pclken pclken_##index[] = STM32_DT_INST_CLOCKS(index);           \
+                                                                                                   \
+	PINCTRL_DT_INST_DEFINE(index);                                                             \
+                                                                                                   \
+	static void stm32_tsc_irq_init_##index(void)                                               \
+	{                                                                                          \
+		IRQ_CONNECT(DT_INST_IRQN(index), DT_INST_IRQ(index, priority), stm32_tsc_isr,      \
+			    DEVICE_DT_INST_GET(index), 0);                                         \
+		irq_enable(DT_INST_IRQN(index));                                                   \
+	};                                                                                         \
+                                                                                                   \
+	static const struct stm32_tsc_group_config group_config_cfg_##index[] = {                  \
+		DT_INST_FOREACH_CHILD_STATUS_OKAY_SEP(index, STM32_TSC_GROUP_DEFINE, (,))};        \
+                                                                                                   \
+	static struct stm32_tsc_group_data                                                         \
+		group_data_cfg_##index[DT_INST_CHILD_NUM_STATUS_OKAY(index)];                      \
+                                                                                                   \
+	static const struct stm32_tsc_config stm32_tsc_cfg_##index = {                             \
+		.tsc = (TSC_TypeDef *)DT_INST_REG_ADDR(index),                                     \
+		.pclken = pclken_##index,                                                          \
+		.reset = RESET_DT_SPEC_INST_GET(index),                                            \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index),                                     \
+		.group_config = group_config_cfg_##index,                                          \
+		.group_data = group_data_cfg_##index,                                              \
+		.group_cnt = DT_INST_CHILD_NUM_STATUS_OKAY(index),                                 \
+		.pgpsc = LOG2CEIL(DT_INST_PROP(index, st_pulse_generator_prescaler)),              \
+		.ctph = DT_INST_PROP(index, st_charge_transfer_pulse_high),                        \
+		.ctpl = DT_INST_PROP(index, st_charge_transfer_pulse_low),                         \
+		.spread_spectrum = DT_INST_PROP(index, st_spread_spectrum),                        \
+		.sscpsc = DT_INST_PROP(index, st_spread_spectrum_prescaler),                       \
+		.ssd = DT_INST_PROP(index, st_spread_spectrum_deviation),                          \
+		.max_count = LOG2CEIL(DT_INST_PROP(index, st_max_count_value) + 1) - 8,            \
+		.iodef = DT_INST_PROP(index, st_iodef_float),                                      \
+		.sync_acq = DT_INST_PROP(index, st_synced_acquisition),                            \
+		.sync_pol = DT_INST_PROP(index, st_syncpol_rising),                                \
+		.irq_func = stm32_tsc_irq_init_##index,                                            \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(index, stm32_tsc_init, NULL, NULL, &stm32_tsc_cfg_##index,           \
+			      POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(STM32_TSC_INIT)
+
+struct input_tsc_keys_data {
+	uint32_t buffer[CONFIG_INPUT_STM32_TSC_KEYS_BUFFER_WORD_SIZE];
+	struct ring_buf rb;
+	bool expect_release;
+	struct k_timer sampling_timer;
+};
+
+struct input_tsc_keys_config {
+	const struct device *tsc_dev;
+	uint32_t sampling_interval_ms;
+	int32_t noise_threshold;
+	int zephyr_code;
+	uint8_t group;
+};
+
+static void input_tsc_sampling_timer_callback(struct k_timer *timer)
+{
+	const struct device *dev = k_timer_user_data_get(timer);
+
+	stm32_tsc_start(dev);
+}
+
+static void input_tsc_callback_handler(uint32_t count_value, void *user_data)
+{
+	const struct device *dev = (const struct device *)user_data;
+	const struct input_tsc_keys_config *config =
+		(const struct input_tsc_keys_config *)dev->config;
+	struct input_tsc_keys_data *data = (struct input_tsc_keys_data *)dev->data;
+
+	if (ring_buf_item_space_get(&data->rb) == 0) {
+		uint32_t oldest_point;
+		int32_t slope;
+
+		(void)ring_buf_get(&data->rb, (uint8_t *)&oldest_point, sizeof(oldest_point));
+
+		slope = count_value - oldest_point;
+		if (slope < -config->noise_threshold && !data->expect_release) {
+			data->expect_release = true;
+			input_report_key(dev, config->zephyr_code, 1, false, K_NO_WAIT);
+		} else if (slope > config->noise_threshold && data->expect_release) {
+			data->expect_release = false;
+			input_report_key(dev, config->zephyr_code, 0, false, K_NO_WAIT);
+		}
+	}
+
+	(void)ring_buf_put(&data->rb, (uint8_t *)&count_value, sizeof(count_value));
+}
+
+static int input_tsc_keys_init(const struct device *dev)
+{
+	const struct input_tsc_keys_config *config = dev->config;
+	struct input_tsc_keys_data *data = dev->data;
+
+	if (!device_is_ready(config->tsc_dev)) {
+		LOG_ERR("%s: TSC device not ready", config->tsc_dev->name);
+		return -ENODEV;
+	}
+
+	ring_buf_item_init(&data->rb, CONFIG_INPUT_STM32_TSC_KEYS_BUFFER_WORD_SIZE, data->buffer);
+
+	uint8_t group_index = 0;
+
+	int ret = get_group_index(config->tsc_dev, config->group, &group_index);
+
+	if (ret) {
+		LOG_ERR("%s: group %d not found", config->tsc_dev->name, config->group);
+		return ret;
+	}
+
+	ret = stm32_tsc_group_register_callback(config->tsc_dev, group_index,
+						input_tsc_callback_handler, (void *)dev);
+
+	if (ret) {
+		LOG_ERR("%s: failed to register callback for group %d", config->tsc_dev->name,
+			config->group);
+		return ret;
+	}
+
+	k_timer_init(&data->sampling_timer, input_tsc_sampling_timer_callback, NULL);
+	k_timer_user_data_set(&data->sampling_timer, (void *)config->tsc_dev);
+	k_timer_start(&data->sampling_timer, K_NO_WAIT, K_MSEC(config->sampling_interval_ms));
+
+	return 0;
+}
+
+#define TSC_KEYS_INIT(inst)                                                                        \
+                                                                                                   \
+	static struct input_tsc_keys_data tsc_keys_data_##inst;                                    \
+                                                                                                   \
+	static const struct input_tsc_keys_config tsc_keys_config_##inst = {                       \
+		.tsc_dev = DEVICE_DT_GET(DT_GPARENT(inst)),                                        \
+		.sampling_interval_ms = DT_PROP(inst, sampling_interval_ms),                       \
+		.zephyr_code = DT_PROP(inst, zephyr_code),                                         \
+		.noise_threshold = DT_PROP(inst, noise_threshold),                                 \
+		.group = DT_PROP(DT_PARENT(inst), group),                                          \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_DEFINE(inst, input_tsc_keys_init, NULL, &tsc_keys_data_##inst,                   \
+			 &tsc_keys_config_##inst, POST_KERNEL, CONFIG_INPUT_INIT_PRIORITY, NULL);
+
+DT_FOREACH_STATUS_OKAY(tsc_keys, TSC_KEYS_INIT);
diff --git a/drivers/interrupt_controller/CMakeLists.txt b/drivers/interrupt_controller/CMakeLists.txt
index 0e458d033f2..2bb2dbe1633 100644
--- a/drivers/interrupt_controller/CMakeLists.txt
+++ b/drivers/interrupt_controller/CMakeLists.txt
@@ -15,8 +15,10 @@ zephyr_library_sources_ifdef(CONFIG_GIC_V3_ITS              intc_gicv3_its.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_INTC_STM32WB0      intc_gpio_stm32wb0.c)
 zephyr_library_sources_ifdef(CONFIG_INTEL_VTD_ICTL          intc_intel_vtd.c)
 zephyr_library_sources_ifdef(CONFIG_IOAPIC                  intc_ioapic.c)
+zephyr_library_sources_ifdef(CONFIG_ITE_IT51XXX_INTC        intc_ite_it51xxx.c)
 zephyr_library_sources_ifdef(CONFIG_ITE_IT8XXX2_INTC        intc_ite_it8xxx2.c)
 zephyr_library_sources_ifdef(CONFIG_ITE_IT8XXX2_INTC_V2     intc_ite_it8xxx2_v2.c)
+zephyr_library_sources_ifdef(CONFIG_ITE_IT51XXX_WUC         wuc_ite_it51xxx.c)
 zephyr_library_sources_ifdef(CONFIG_ITE_IT8XXX2_WUC         wuc_ite_it8xxx2.c)
 zephyr_library_sources_ifdef(CONFIG_LEON_IRQMP              intc_irqmp.c)
 zephyr_library_sources_ifdef(CONFIG_LOAPIC                  intc_loapic.c intc_system_apic.c)
@@ -28,19 +30,18 @@ zephyr_library_sources_ifdef(CONFIG_RV32M1_INTMUX           intc_rv32m1_intmux.c
 zephyr_library_sources_ifdef(CONFIG_SAM0_EIC                intc_sam0_eic.c)
 zephyr_library_sources_ifdef(CONFIG_SHARED_IRQ              intc_shared_irq.c)
 zephyr_library_sources_ifdef(CONFIG_INTC_ESP32              intc_esp32.c)
-zephyr_library_sources_ifdef(CONFIG_INTC_ESP32C3            intc_esp32c3.c)
 zephyr_library_sources_ifdef(CONFIG_SWERV_PIC               intc_swerv_pic.c)
 zephyr_library_sources_ifdef(CONFIG_VEXRISCV_LITEX_IRQ      intc_vexriscv_litex.c)
 zephyr_library_sources_ifdef(CONFIG_VIM                     intc_vim.c)
-zephyr_library_sources_ifdef(CONFIG_NUCLEI_ECLIC            intc_nuclei_eclic.c)
-zephyr_library_sources_ifdef(CONFIG_NUCLEI_ECLIC            intc_nuclei_eclic.S)
+zephyr_library_sources_ifdef(CONFIG_CLIC                    intc_clic.c)
+zephyr_library_sources_ifdef(CONFIG_CLIC                    intc_clic.S)
 zephyr_library_sources_ifdef(CONFIG_NRFX_CLIC               intc_nrfx_clic.c)
 zephyr_library_sources_ifdef(CONFIG_NRFX_CLIC               intc_nrfx_clic.S)
 zephyr_library_sources_ifdef(CONFIG_NXP_S32_EIRQ            intc_eirq_nxp_s32.c)
 zephyr_library_sources_ifdef(CONFIG_NXP_S32_WKPU            intc_wkpu_nxp_s32.c)
 zephyr_library_sources_ifdef(CONFIG_XMC4XXX_INTC            intc_xmc4xxx.c)
 zephyr_library_sources_ifdef(CONFIG_NXP_PINT                intc_nxp_pint.c)
-zephyr_library_sources_ifdef(CONFIG_RENESAS_RA_ICU          intc_renesas_ra_icu.c)
+zephyr_library_sources_ifdef(CONFIG_RENESAS_RZ_EXT_IRQ      intc_renesas_rz_ext_irq.c)
 zephyr_library_sources_ifdef(CONFIG_NXP_IRQSTEER            intc_nxp_irqsteer.c)
 zephyr_library_sources_ifdef(CONFIG_INTC_MTK_ADSP           intc_mtk_adsp.c)
 zephyr_library_sources_ifdef(CONFIG_WCH_PFIC                intc_wch_pfic.c)
diff --git a/drivers/interrupt_controller/Kconfig b/drivers/interrupt_controller/Kconfig
index caabfc57690..3468cf4f3f2 100644
--- a/drivers/interrupt_controller/Kconfig
+++ b/drivers/interrupt_controller/Kconfig
@@ -66,6 +66,8 @@ source "drivers/interrupt_controller/Kconfig.loapic"
 
 source "drivers/interrupt_controller/Kconfig.dw"
 
+source "drivers/interrupt_controller/Kconfig.it51xxx"
+
 source "drivers/interrupt_controller/Kconfig.it8xxx2"
 
 source "drivers/interrupt_controller/Kconfig.stm32"
@@ -84,8 +86,6 @@ source "drivers/interrupt_controller/Kconfig.intel_vtd"
 
 source "drivers/interrupt_controller/Kconfig.esp32"
 
-source "drivers/interrupt_controller/Kconfig.esp32c3"
-
 source "drivers/interrupt_controller/Kconfig.xec"
 
 source "drivers/interrupt_controller/Kconfig.clic"
@@ -102,7 +102,7 @@ source "drivers/interrupt_controller/Kconfig.nxp_pint"
 
 source "drivers/interrupt_controller/Kconfig.vim"
 
-source "drivers/interrupt_controller/Kconfig.renesas_ra"
+source "drivers/interrupt_controller/Kconfig.renesas_rz"
 
 source "drivers/interrupt_controller/Kconfig.nxp_irqsteer"
 
diff --git a/drivers/interrupt_controller/Kconfig.clic b/drivers/interrupt_controller/Kconfig.clic
index f27301323ee..aba90ff0086 100644
--- a/drivers/interrupt_controller/Kconfig.clic
+++ b/drivers/interrupt_controller/Kconfig.clic
@@ -1,12 +1,23 @@
 # Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
+config CLIC
+	bool "RISC-V Core Local Interrupt Controller (CLIC)"
+	default y
+	depends on DT_HAS_NUCLEI_ECLIC_ENABLED || DT_HAS_RISCV_CLIC_ENABLED
+	select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING
+	help
+	  Core Local Interrupt Controller provide low-latency, vectored,
+	  preemptive interrupts for RISC-V systems.
+
 config NUCLEI_ECLIC
 	bool "Enhanced Core Local Interrupt Controller (ECLIC)"
 	default y
 	depends on DT_HAS_NUCLEI_ECLIC_ENABLED
-	select RISCV_SOC_HAS_CUSTOM_IRQ_HANDLING
+	select CLIC
 	select CLIC_SMCLICSHV_EXT if RISCV_VECTORED_MODE
+	select CLIC_SMCLICCONFIG_EXT
+	select LEGACY_CLIC_MEMORYMAP_ACCESS
 	help
 	  Interrupt controller for Nuclei SoC core.
 
@@ -18,6 +29,8 @@ config NRFX_CLIC
 	help
 	  Interrupt controller for Nordic VPR cores.
 
+if CLIC
+
 config CLIC_SMCLICSHV_EXT
 	bool
 	help
@@ -25,7 +38,33 @@ config CLIC_SMCLICSHV_EXT
 	  to select the behavior for each interrupt. The CLIC driver needs to
 	  implement the riscv_clic_irq_vector_set() function.
 
-if NUCLEI_ECLIC
+config CLIC_SMCLICCONFIG_EXT
+	bool
+	help
+	  Enables the SMCLICCONFIG extension, allowing configuration of CLIC
+	  parameters such as the number of interrupt level bits.
+
+config CLIC_PARAMETER_INTCTLBITS
+	int "The number of modifiable bits in the clicintctl registers"
+	range 0 8
+	default 8
+	help
+	  This option specifies the number of modifiable bits in the clicintctl
+	  registers.
+
+config CLIC_PARAMETER_MNLBITS
+	int "The number of bits in CLICINTCTLBITS to encode the interrupt level"
+	range 0 CLIC_PARAMETER_INTCTLBITS
+	default 0
+	help
+	  This option specifies the number of bits in CLICINTCTLBITS assigned to
+	  encode the interrupt level at machine mode.
+
+config LEGACY_CLIC_MEMORYMAP_ACCESS
+	bool
+	help
+	  Enables legacy CLIC, allowing access to CLIC registers through
+	  memory-mapped access instead of indirect CSR access.
 
 config LEGACY_CLIC
 	bool "Use the legacy clic specification"
@@ -34,4 +73,4 @@ config LEGACY_CLIC
 	  Enables legacy clic, where smclicshv extension is not supported and
 	  hardware vectoring is set via mode bits of mtvec.
 
-endif # NUCLEI_ECLIC
+endif # CLIC
diff --git a/drivers/interrupt_controller/Kconfig.esp32 b/drivers/interrupt_controller/Kconfig.esp32
index 507161fb613..35699cce56f 100644
--- a/drivers/interrupt_controller/Kconfig.esp32
+++ b/drivers/interrupt_controller/Kconfig.esp32
@@ -4,10 +4,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config INTC_ESP32
-	bool "Interrupt allocator for Xtensa-based Espressif SoCs"
+	bool "Interrupt allocator for Espressif SoCs"
 	default y
 	depends on SOC_FAMILY_ESPRESSIF_ESP32
-	depends on !SOC_SERIES_ESP32C2 && !SOC_SERIES_ESP32C3 && !SOC_SERIES_ESP32C6
 	help
 	  Enable custom interrupt allocator for Espressif SoCs based on Xtensa
 	  architecture.
diff --git a/drivers/interrupt_controller/Kconfig.esp32c3 b/drivers/interrupt_controller/Kconfig.esp32c3
deleted file mode 100644
index c1a72395648..00000000000
--- a/drivers/interrupt_controller/Kconfig.esp32c3
+++ /dev/null
@@ -1,21 +0,0 @@
-# Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
-# SPDX-License-Identifier: Apache-2.0
-
-config INTC_ESP32C3
-	bool "ESP32C3 interrupt controller driver"
-	depends on SOC_FAMILY_ESPRESSIF_ESP32
-	depends on SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
-	default y
-	help
-	  Enables the esp32c3 interrupt controller driver to handle ISR
-	  management at SoC level.
-
-config INTC_ESP32C3_DECISIONS_LOG
-	bool "Espressif's interrupt allocator logging"
-	depends on INTC_ESP32C3
-	select LOG
-	help
-	  Enable this option to visualize information on decisions made by the
-	  interrupt allocator. This has no impact on the interrupt allocator usage
-	  but may be valuable for debugging purposes. When enabled, messages are
-	  print to the serial console.
diff --git a/drivers/interrupt_controller/Kconfig.it51xxx b/drivers/interrupt_controller/Kconfig.it51xxx
new file mode 100644
index 00000000000..a3237c96906
--- /dev/null
+++ b/drivers/interrupt_controller/Kconfig.it51xxx
@@ -0,0 +1,26 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config HAS_ITE_INTC
+	bool
+	help
+	  This option is selected when ITE_IT51XXX_INTC is enabled.
+
+config ITE_IT51XXX_INTC
+	def_bool DT_HAS_ITE_IT51XXX_INTC_ENABLED
+	depends on DT_HAS_ITE_IT51XXX_INTC_ENABLED
+	select HAS_ITE_INTC
+	help
+	  This option mainly collects several interrupts from modules.
+	  Configurable level-triggered and dege-triggered mode.
+	  Configurable interrupt polarity of triggered mode.
+	  Each interrupt source able to enabled/masked individually.
+
+config ITE_IT51XXX_WUC
+	bool "ITE it51xxx Wakeup controller (WUC) interface"
+	default y
+	depends on DT_HAS_ITE_IT51XXX_WUC_ENABLED
+	help
+	  This option enables the wakeup controller interface for IT51XXX
+	  family.
+	  This is required for KSCAN, UART, eSPI, GPIO etc., interrupt support.
diff --git a/drivers/interrupt_controller/Kconfig.mtk_adsp b/drivers/interrupt_controller/Kconfig.mtk_adsp
index 0c8875973e8..112358986bb 100644
--- a/drivers/interrupt_controller/Kconfig.mtk_adsp
+++ b/drivers/interrupt_controller/Kconfig.mtk_adsp
@@ -3,6 +3,7 @@
 
 config INTC_MTK_ADSP
 	bool "MediaTek Audio DSP Interrupt Controller"
+	depends on SOC_FAMILY_MTK
 	help
 	  Very simple cascaded interrupt controller consisting of two
 	  bitfield registers (status and enable) and one mask value
diff --git a/drivers/interrupt_controller/Kconfig.nxp_irqsteer b/drivers/interrupt_controller/Kconfig.nxp_irqsteer
index b2dbc9b2afa..e3c5c9d68e4 100644
--- a/drivers/interrupt_controller/Kconfig.nxp_irqsteer
+++ b/drivers/interrupt_controller/Kconfig.nxp_irqsteer
@@ -6,7 +6,6 @@ config NXP_IRQSTEER
 	default y
 	depends on DT_HAS_NXP_IRQSTEER_INTC_ENABLED
 	depends on MULTI_LEVEL_INTERRUPTS
-	depends on XTENSA
 	help
 		The IRQSTEER INTC provides support for MUX-ing
 		multiple interrupts from peripheral to one or
diff --git a/drivers/interrupt_controller/Kconfig.renesas_ra b/drivers/interrupt_controller/Kconfig.renesas_ra
deleted file mode 100644
index 45cb171d26d..00000000000
--- a/drivers/interrupt_controller/Kconfig.renesas_ra
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
-# SPDX-License-Identifier: Apache-2.0
-
-config RENESAS_RA_ICU
-	bool "Renesas RA series interrupt controller unit"
-	default y
-	depends on DT_HAS_RENESAS_RA_INTERRUPT_CONTROLLER_UNIT_ENABLED
-	select GEN_ISR_TABLES
-	help
-	  Renesas RA series interrupt controller unit
diff --git a/drivers/interrupt_controller/Kconfig.renesas_rz b/drivers/interrupt_controller/Kconfig.renesas_rz
new file mode 100644
index 00000000000..6fe45f73788
--- /dev/null
+++ b/drivers/interrupt_controller/Kconfig.renesas_rz
@@ -0,0 +1,11 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config RENESAS_RZ_EXT_IRQ
+	bool "Renesas RZ external interrupt controller driver"
+	default y
+	depends on DT_HAS_RENESAS_RZ_EXT_IRQ_ENABLED
+	select USE_RZ_FSP_EXT_IRQ
+	select PINCTRL
+	help
+	  Renesas RZ external interrupt controller driver
diff --git a/drivers/interrupt_controller/intc_clic.S b/drivers/interrupt_controller/intc_clic.S
new file mode 100644
index 00000000000..3a03b8d417c
--- /dev/null
+++ b/drivers/interrupt_controller/intc_clic.S
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2024 Baumer Electric AG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Assembler-hooks specific to RISC-V Core Local Interrupt Controller
+ */
+
+#include <zephyr/arch/cpu.h>
+#include "intc_clic.h"
+
+#ifdef CONFIG_64BIT
+	/* register-wide load/store based on ld/sd (XLEN = 64) */
+
+	.macro lr, rd, mem
+	ld \rd, \mem
+	.endm
+
+	.macro sr, rs, mem
+	sd \rs, \mem
+	.endm
+
+#else
+	/* register-wide load/store based on lw/sw (XLEN = 32) */
+
+	.macro lr, rd, mem
+	lw \rd, \mem
+	.endm
+
+	.macro sr, rs, mem
+	sw \rs, \mem
+	.endm
+
+#endif
+
+GTEXT(__soc_handle_irq)
+/*
+ * In an CLIC, pending interrupts don't have to be cleared by hand.
+ * In vectored mode, interrupts are cleared automatically.
+ * In non-vectored mode, interrupts are cleared when writing the mnxti register (done in
+ * __soc_handle_all_irqs).
+ * Thus this function can directly return.
+ */
+SECTION_FUNC(exception.other, __soc_handle_irq)
+	ret
+
+GTEXT(__soc_handle_all_irqs)
+
+#ifdef CONFIG_TRACING
+/* imports */
+GTEXT(sys_trace_isr_enter)
+GTEXT(sys_trace_isr_exit)
+#endif
+
+/*
+ * This function services and clears all pending interrupts for an CLIC in non-vectored mode.
+ */
+SECTION_FUNC(exception.other, __soc_handle_all_irqs)
+	addi sp, sp, -16
+	sr ra, 0(sp)
+
+	/* Read and clear mnxti to get highest current interrupt and enable interrupts. Will return
+	 * original interrupt if no others appear. */
+	csrrci a0, CSR_MNXTI, MSTATUS_IEN
+	beqz a0, irq_done /* Check if original interrupt vanished. */
+
+irq_loop:
+
+#ifdef CONFIG_TRACING_ISR
+	call sys_trace_isr_enter
+#endif
+
+	/* Call corresponding registered function in _sw_isr_table. a0 is offset in pointer with
+	 * the mtvt, sw irq table is 2-pointer wide -> shift by one. */
+	csrr t0, CSR_MTVT
+	sub a0, a0, t0
+	la t0, _sw_isr_table
+	slli a0, a0, (1)
+	add t0, t0, a0
+
+	/* Load argument in a0 register */
+	lr a0, 0(t0)
+
+	/* Load ISR function address in register t1 */
+	lr t1, RV_REGSIZE(t0)
+
+	/* Call ISR function */
+	jalr ra, t1, 0
+
+#ifdef CONFIG_TRACING_ISR
+	call sys_trace_isr_exit
+#endif
+
+	/* Read and clear mnxti to get highest current interrupt and enable interrupts. */
+	csrrci a0, CSR_MNXTI, MSTATUS_IEN
+	bnez a0, irq_loop
+
+irq_done:
+	lr ra, 0(sp)
+	addi sp, sp, 16
+	ret
diff --git a/drivers/interrupt_controller/intc_clic.c b/drivers/interrupt_controller/intc_clic.c
new file mode 100644
index 00000000000..4cbf2de6f2a
--- /dev/null
+++ b/drivers/interrupt_controller/intc_clic.c
@@ -0,0 +1,340 @@
+/*
+ * Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
+ * Copyright (c) 2025 Andes Technology Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Driver for Core Local Interrupt Controller
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/arch/riscv/csr.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/interrupt_controller/riscv_clic.h>
+#include "intc_clic.h"
+
+#if DT_HAS_COMPAT_STATUS_OKAY(riscv_clic)
+#define DT_DRV_COMPAT riscv_clic
+#elif DT_HAS_COMPAT_STATUS_OKAY(nuclei_eclic)
+#define DT_DRV_COMPAT nuclei_eclic
+#else
+#error "Unknown CLIC controller compatible for this configuration"
+#endif
+
+struct clic_data {
+	uint8_t nlbits;
+	uint8_t intctlbits;
+};
+
+struct clic_config {
+	mem_addr_t base;
+};
+
+struct pmp_stack_guard_key_t {
+	unsigned long mstatus;
+	unsigned int irq_key;
+};
+
+/*
+ * M-mode CLIC memory-mapped registers are accessible only in M-mode.
+ * Temporarily disable the PMP stack guard (set mstatus.MPRV = 0) to configure
+ * CLIC registers, then restore the PMP stack guard using these functions.
+ */
+static ALWAYS_INLINE void disable_pmp_stack_guard(struct pmp_stack_guard_key_t *key)
+{
+	if (IS_ENABLED(CONFIG_PMP_STACK_GUARD)) {
+		key->irq_key = irq_lock();
+		key->mstatus = csr_read_clear(mstatus, MSTATUS_MPRV);
+	} else {
+		ARG_UNUSED(key);
+	}
+}
+
+static ALWAYS_INLINE void restore_pmp_stack_guard(struct pmp_stack_guard_key_t key)
+{
+	if (IS_ENABLED(CONFIG_PMP_STACK_GUARD)) {
+		csr_write(mstatus, key.mstatus);
+		irq_unlock(key.irq_key);
+	} else {
+		ARG_UNUSED(key);
+	}
+}
+
+static ALWAYS_INLINE void write_clic32(const struct device *dev, uint32_t offset, uint32_t value)
+{
+	const struct clic_config *config = dev->config;
+	mem_addr_t reg_addr = config->base + offset;
+	struct pmp_stack_guard_key_t key;
+
+	disable_pmp_stack_guard(&key);
+	sys_write32(value, reg_addr);
+	restore_pmp_stack_guard(key);
+}
+
+static ALWAYS_INLINE uint32_t read_clic32(const struct device *dev, uint32_t offset)
+{
+	const struct clic_config *config = dev->config;
+	mem_addr_t reg_addr = config->base + offset;
+	struct pmp_stack_guard_key_t key;
+	uint32_t reg;
+
+	disable_pmp_stack_guard(&key);
+	reg = sys_read32(reg_addr);
+	restore_pmp_stack_guard(key);
+
+	return reg;
+}
+
+static ALWAYS_INLINE void write_clic8(const struct device *dev, uint32_t offset, uint8_t value)
+{
+	const struct clic_config *config = dev->config;
+	mem_addr_t reg_addr = config->base + offset;
+	struct pmp_stack_guard_key_t key;
+
+	disable_pmp_stack_guard(&key);
+	sys_write8(value, reg_addr);
+	restore_pmp_stack_guard(key);
+}
+
+static ALWAYS_INLINE uint8_t read_clic8(const struct device *dev, uint32_t offset)
+{
+	const struct clic_config *config = dev->config;
+	mem_addr_t reg_addr = config->base + offset;
+	struct pmp_stack_guard_key_t key;
+	uint32_t reg;
+
+	disable_pmp_stack_guard(&key);
+	reg = sys_read8(reg_addr);
+	restore_pmp_stack_guard(key);
+
+	return reg;
+}
+
+/**
+ * @brief Enable interrupt
+ */
+void riscv_clic_irq_enable(uint32_t irq)
+{
+	if (IS_ENABLED(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS)) {
+		const struct device *dev = DEVICE_DT_INST_GET(0);
+		union CLICINTIE clicintie = {.b = {.IE = 0x1}};
+
+		write_clic8(dev, CLIC_INTIE(irq), clicintie.w);
+	} else {
+		csr_write(CSR_MISELECT, CLIC_INTIE(irq));
+		csr_set(CSR_MIREG2, BIT(irq % 32));
+	}
+}
+
+/**
+ * @brief Disable interrupt
+ */
+void riscv_clic_irq_disable(uint32_t irq)
+{
+	if (IS_ENABLED(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS)) {
+		const struct device *dev = DEVICE_DT_INST_GET(0);
+		union CLICINTIE clicintie = {.b = {.IE = 0x0}};
+
+		write_clic8(dev, CLIC_INTIE(irq), clicintie.w);
+	} else {
+		csr_write(CSR_MISELECT, CLIC_INTIE(irq));
+		csr_clear(CSR_MIREG2, BIT(irq % 32));
+	}
+}
+
+/**
+ * @brief Get enable status of interrupt
+ */
+int riscv_clic_irq_is_enabled(uint32_t irq)
+{
+	int is_enabled = 0;
+
+	if (IS_ENABLED(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS)) {
+		const struct device *dev = DEVICE_DT_INST_GET(0);
+		union CLICINTIE clicintie = {.w = read_clic8(dev, CLIC_INTIE(irq))};
+
+		is_enabled = clicintie.b.IE;
+	} else {
+		csr_write(CSR_MISELECT, CLIC_INTIE(irq));
+		is_enabled = csr_read(CSR_MIREG2) & BIT(irq % 32);
+	}
+
+	return !!is_enabled;
+}
+
+/**
+ * @brief Set priority and level of interrupt
+ */
+void riscv_clic_irq_priority_set(uint32_t irq, uint32_t pri, uint32_t flags)
+{
+	const struct device *dev = DEVICE_DT_INST_GET(0);
+	const struct clic_data *data = dev->data;
+
+	/*
+	 * Set the interrupt level and the interrupt priority.
+	 * Examples of mcliccfg settings:
+	 * CLICINTCTLBITS mnlbits clicintctl[i] interrupt levels
+	 *       0         2      ........      255
+	 *       1         2      l.......      127,255
+	 *       2         2      ll......      63,127,191,255
+	 *       3         3      lll.....      31,63,95,127,159,191,223,255
+	 *       4         1      lppp....      127,255
+	 * "." bits are non-existent bits for level encoding, assumed to be 1
+	 * "l" bits are available variable bits in level specification
+	 * "p" bits are available variable bits in priority specification
+	 */
+	const uint8_t max_level = BIT_MASK(data->nlbits);
+	const uint8_t max_prio = BIT_MASK(data->intctlbits - data->nlbits);
+	uint8_t intctrl = (MIN(pri, max_prio) << (8U - data->intctlbits)) |
+			  (MIN(pri, max_level) << (8U - data->nlbits)) |
+			  BIT_MASK(8U - data->intctlbits);
+
+	if (IS_ENABLED(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS)) {
+		write_clic8(dev, CLIC_INTCTRL(irq), intctrl);
+	} else {
+		uint32_t clicintctl, bit_offset = 8 * (irq % 4);
+
+		csr_write(CSR_MISELECT, CLIC_INTCTRL(irq));
+		clicintctl = csr_read(CSR_MIREG);
+		clicintctl &= ~GENMASK(bit_offset + 7, bit_offset);
+		clicintctl |= intctrl << bit_offset;
+		csr_write(CSR_MIREG, clicintctl);
+	}
+
+	/* Set the IRQ operates in machine mode, non-vectoring and the trigger type. */
+	union CLICINTATTR clicattr = {.b = {.mode = 0x3, .shv = 0x0, .trg = flags & BIT_MASK(3)}};
+
+	if (IS_ENABLED(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS)) {
+		write_clic8(dev, CLIC_INTATTR(irq), clicattr.w);
+	} else {
+		uint32_t clicintattr, bit_offset = 8 * (irq % 4);
+
+		csr_write(CSR_MISELECT, CLIC_INTATTR(irq));
+		clicintattr = csr_read(CSR_MIREG2);
+		clicintattr &= ~GENMASK(bit_offset + 7, bit_offset);
+		clicintattr |= clicattr.w << bit_offset;
+		csr_write(CSR_MIREG2, clicintattr);
+	}
+}
+
+/**
+ * @brief Set vector mode of interrupt
+ */
+void riscv_clic_irq_vector_set(uint32_t irq)
+{
+	if (IS_ENABLED(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS)) {
+		const struct device *dev = DEVICE_DT_INST_GET(0);
+		union CLICINTATTR clicattr = {.w = read_clic8(dev, CLIC_INTATTR(irq))};
+
+		/* Set Selective Hardware Vectoring. */
+		clicattr.b.shv = 1;
+		write_clic8(dev, CLIC_INTATTR(irq), clicattr.w);
+	} else {
+		uint32_t clicintattr, bit_offset = 8 * (irq % 4);
+		union CLICINTATTR clicattr = {.b = {.shv = 1}};
+
+		csr_write(CSR_MISELECT, CLIC_INTATTR(irq));
+		clicintattr = csr_read(CSR_MIREG2);
+		clicintattr |= clicattr.w << bit_offset;
+		csr_write(CSR_MIREG2, clicintattr);
+	}
+}
+
+/**
+ * @brief Set pending bit of an interrupt
+ */
+void riscv_clic_irq_set_pending(uint32_t irq)
+{
+	if (IS_ENABLED(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS)) {
+		const struct device *dev = DEVICE_DT_INST_GET(0);
+		union CLICINTIP clicintip = {.b = {.IP = 0x1}};
+
+		write_clic8(dev, CLIC_INTIP(irq), clicintip.w);
+	} else {
+		csr_write(CSR_MISELECT, CLIC_INTIP(irq));
+		csr_set(CSR_MIREG, BIT(irq % 32));
+	}
+}
+
+static int clic_init(const struct device *dev)
+{
+	struct clic_data *data = dev->data;
+
+	if (IS_ENABLED(CONFIG_NUCLEI_ECLIC)) {
+		/* Configure the interrupt level threshold. */
+		union CLICMTH clicmth = {.b = {.mth = 0x0}};
+
+		write_clic32(dev, CLIC_MTH, clicmth.qw);
+
+		/* Detect the number of bits for the clicintctl register. */
+		union CLICINFO clicinfo = {.qw = read_clic32(dev, CLIC_INFO)};
+
+		data->intctlbits = clicinfo.b.intctlbits;
+
+		if (data->nlbits > data->intctlbits) {
+			data->nlbits = data->intctlbits;
+		}
+	} else {
+		/* Configure the interrupt level threshold by CSR mintthresh. */
+		csr_write(CSR_MINTTHRESH, 0x0);
+	}
+
+	if (IS_ENABLED(CONFIG_CLIC_SMCLICCONFIG_EXT)) {
+		if (IS_ENABLED(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS)) {
+			/* Configure the number of bits assigned to interrupt levels. */
+			union CLICCFG cliccfg = {.qw = read_clic32(dev, CLIC_CFG)};
+
+			cliccfg.w.nlbits = data->nlbits;
+			write_clic32(dev, CLIC_CFG, cliccfg.qw);
+		} else {
+			csr_write(CSR_MISELECT, CLIC_CFG);
+			union CLICCFG cliccfg = {.qw = csr_read(CSR_MIREG)};
+
+			cliccfg.w.nlbits = data->nlbits;
+			csr_write(CSR_MIREG, cliccfg.qw);
+		}
+	}
+
+	if (IS_ENABLED(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS)) {
+		/* Reset all interrupt control register. */
+		for (int i = 0; i < CONFIG_NUM_IRQS; i++) {
+			write_clic32(dev, CLIC_CTRL(i), 0);
+		}
+	} else {
+		/* Reset all clicintip, clicintie register. */
+		for (int i = 0; i < CONFIG_NUM_IRQS; i += 32) {
+			csr_write(CSR_MISELECT, CLIC_INTIP(i));
+			csr_write(CSR_MIREG, 0);
+			csr_write(CSR_MIREG2, 0);
+		}
+
+		/* Reset all clicintctl, clicintattr register. */
+		for (int i = 0; i < CONFIG_NUM_IRQS; i += 4) {
+			csr_write(CSR_MISELECT, CLIC_INTCTRL(i));
+			csr_write(CSR_MIREG, 0);
+			csr_write(CSR_MIREG2, 0);
+		}
+	}
+
+	return 0;
+}
+
+#define CLIC_INTC_DATA_INIT(n)                                                                     \
+	static struct clic_data clic_data_##n = {                                                  \
+		.nlbits = CONFIG_CLIC_PARAMETER_MNLBITS,                                           \
+		.intctlbits = CONFIG_CLIC_PARAMETER_INTCTLBITS,                                    \
+	};
+#define CLIC_INTC_CONFIG_INIT(n)                                                                   \
+	const static struct clic_config clic_config_##n = {                                        \
+		.base = COND_CODE_1(CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS,                           \
+				   (DT_REG_ADDR(DT_DRV_INST(n))), (0)),                            \
+	};
+#define CLIC_INTC_DEVICE_INIT(n)                                                                   \
+	CLIC_INTC_DATA_INIT(n)                                                                     \
+	CLIC_INTC_CONFIG_INIT(n)                                                                   \
+	DEVICE_DT_INST_DEFINE(n, &clic_init, NULL, &clic_data_##n, &clic_config_##n, PRE_KERNEL_1, \
+			      CONFIG_INTC_INIT_PRIORITY, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(CLIC_INTC_DEVICE_INIT)
diff --git a/drivers/interrupt_controller/intc_clic.h b/drivers/interrupt_controller/intc_clic.h
new file mode 100644
index 00000000000..b63e40b31cd
--- /dev/null
+++ b/drivers/interrupt_controller/intc_clic.h
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
+ * Copyright (c) 2025 Andes Technology Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_CLIC_H_
+#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_CLIC_H_
+
+/* CLIC relative CSR number */
+#define CSR_MTVT       (0x307)
+#define CSR_MNXTI      (0x345)
+#define CSR_MINTTHRESH (0x347)
+#define CSR_MISELECT   (0x350)
+#define CSR_MIREG      (0x351)
+#define CSR_MIREG2     (0x352)
+
+#ifndef __ASSEMBLER__
+
+#include <stddef.h>
+
+#ifdef CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS
+/* CLIC Memory mapped register offset */
+#define CLIC_CFG          (0x0)
+#define CLIC_CTRL(irq)    (0x1000 + 4 * (irq))
+#define CLIC_INTIP(irq)   (CLIC_CTRL(irq) + offsetof(union CLICCTRL, w.INTIP))
+#define CLIC_INTIE(irq)   (CLIC_CTRL(irq) + offsetof(union CLICCTRL, w.INTIE))
+#define CLIC_INTATTR(irq) (CLIC_CTRL(irq) + offsetof(union CLICCTRL, w.INTATTR))
+#define CLIC_INTCTRL(irq) (CLIC_CTRL(irq) + offsetof(union CLICCTRL, w.INTCTRL))
+#else
+/* Indirect CSR Access miselect offset */
+#define CLIC_CFG          (0x14A0)
+#define CLIC_CTRL(irq)    (0x0) /* Dummy value for driver compatibility */
+#define CLIC_INTIP(irq)   (0x1400 + (irq) / 32)
+#define CLIC_INTIE(irq)   (0x1400 + (irq) / 32)
+#define CLIC_INTATTR(irq) (0x1000 + (irq) / 4)
+#define CLIC_INTCTRL(irq) (0x1000 + (irq) / 4)
+#endif /* !CONFIG_LEGACY_CLIC_MEMORYMAP_ACCESS */
+
+/* Nuclei ECLIC memory mapped register offset */
+#define CLIC_INFO (0x4)
+#define CLIC_MTH  (0x8)
+
+/* CLIC register structure */
+union CLICCFG {
+	struct {
+#ifdef CONFIG_NUCLEI_ECLIC
+		uint32_t _reserved0: 1;
+#endif /* CONFIG_NUCLEI_ECLIC */
+		/** number of interrupt level bits */
+		uint32_t nlbits: 4;
+		/** number of clicintattr[i].MODE bits */
+		uint32_t nmbits: 2;
+		uint32_t _reserved1: 25;
+	} w;
+	uint32_t qw;
+};
+
+union CLICINTIP {
+	struct {
+		/** Interrupt Pending */
+		uint8_t IP: 1;
+		uint8_t reserved0: 7;
+	} b;
+	uint8_t w;
+};
+
+union CLICINTIE {
+	struct {
+		/** Interrupt Enabled */
+		uint8_t IE: 1;
+		uint8_t reserved0: 7;
+	} b;
+	uint8_t w;
+};
+
+union CLICINTATTR {
+	struct {
+		/** 0: non-vectored 1:vectored */
+		uint8_t shv: 1;
+		/** 0: level 1: rising edge 2: falling edge */
+		uint8_t trg: 2;
+		uint8_t reserved0: 3;
+		uint8_t mode: 2;
+	} b;
+	uint8_t w;
+};
+
+union CLICCTRL {
+	struct {
+		volatile union CLICINTIP INTIP;
+		volatile union CLICINTIE INTIE;
+		volatile union CLICINTATTR INTATTR;
+		volatile uint8_t INTCTRL;
+	} w;
+	uint32_t qw;
+};
+
+/* Nuclei ECLIC register structure */
+union CLICINFO {
+	struct {
+		/** number of max supported interrupts */
+		uint32_t numint: 13;
+		/** architecture version */
+		uint32_t version: 8;
+		/** supported bits in the clicintctl */
+		uint32_t intctlbits: 4;
+		uint32_t _reserved0: 7;
+	} b;
+	uint32_t qw;
+};
+
+union CLICMTH {
+	struct {
+		uint32_t reserved0: 24;
+		/**  machine mode interrupt level threshold */
+		uint32_t mth: 8;
+	} b;
+	uint32_t qw;
+};
+
+#endif /*__ASSEMBLER__*/
+
+#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_CLIC_H_ */
diff --git a/drivers/interrupt_controller/intc_esp32.c b/drivers/interrupt_controller/intc_esp32.c
index 23073d80edc..d6980b3e615 100644
--- a/drivers/interrupt_controller/intc_esp32.c
+++ b/drivers/interrupt_controller/intc_esp32.c
@@ -1,10 +1,11 @@
 /*
- * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2021-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <zephyr/kernel.h>
+#include <zephyr/irq.h>
 #include <stdint.h>
 #include <stdio.h>
 #include <stdlib.h>
@@ -15,13 +16,14 @@
 #include <esp_memory_utils.h>
 #include <esp_attr.h>
 #include <esp_cpu.h>
+#include <esp_rom_sys.h>
 #include <esp_private/rtc_ctrl.h>
 #include <limits.h>
 #include <assert.h>
 #include <soc/soc.h>
 
 #include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(esp32_intc, CONFIG_LOG_DEFAULT_LEVEL);
+LOG_MODULE_REGISTER(intc_esp32, CONFIG_LOG_DEFAULT_LEVEL);
 
 #define ETS_INTERNAL_TIMER0_INTR_NO 6
 #define ETS_INTERNAL_TIMER1_INTR_NO 15
@@ -47,7 +49,6 @@ LOG_MODULE_REGISTER(esp32_intc, CONFIG_LOG_DEFAULT_LEVEL);
 #endif
 
 /* Typedef for C-callable interrupt handler function */
-typedef void (*intc_handler_t)(void *);
 typedef void (*intc_dyn_handler_t)(const void *);
 
 /* shared critical section context */
@@ -63,32 +64,6 @@ static inline void esp_intr_unlock(void)
 	irq_unlock(esp_intc_csec);
 }
 
-/*
- * Interrupt handler table and unhandled interrupt routine. Duplicated
- * from xtensa_intr.c... it's supposed to be private, but we need to look
- * into it in order to see if someone allocated an int using
- * set_interrupt_handler.
- */
-struct intr_alloc_table_entry {
-	void (*handler)(void *arg);
-	void *arg;
-};
-
-/* Default handler for unhandled interrupts. */
-void IRAM_ATTR default_intr_handler(void *arg)
-{
-	esp_rom_printf("Unhandled interrupt %d on cpu %d!\n", (int)arg, esp_cpu_get_core_id());
-}
-
-static struct intr_alloc_table_entry intr_alloc_table[ESP_INTC_INTS_NUM * CONFIG_MP_MAX_NUM_CPUS];
-
-static void set_interrupt_handler(int n, intc_handler_t f, void *arg)
-{
-	irq_disable(n);
-	intr_alloc_table[n * CONFIG_MP_MAX_NUM_CPUS].handler = f;
-	irq_connect_dynamic(n, 0, (intc_dyn_handler_t)f, arg, 0);
-}
-
 /* Linked list of vector descriptions, sorted by cpu.intno value */
 static struct vector_desc_t *vector_desc_head; /* implicitly initialized to NULL */
 
@@ -201,19 +176,9 @@ static struct vector_desc_t *find_desc_for_source(int source, int cpu)
 	return vd;
 }
 
-void esp_intr_initialize(void)
-{
-	unsigned int num_cpus = arch_num_cpus();
-
-	for (size_t i = 0; i < (ESP_INTC_INTS_NUM * num_cpus); ++i) {
-		intr_alloc_table[i].handler = default_intr_handler;
-		intr_alloc_table[i].arg = (void *)i;
-	}
-}
-
 int esp_intr_mark_shared(int intno, int cpu, bool is_int_ram)
 {
-	if (intno >= ESP_INTC_INTS_NUM) {
+	if (intno >= SOC_CPU_INTR_NUM) {
 		return -EINVAL;
 	}
 	if (cpu >= arch_num_cpus()) {
@@ -238,7 +203,7 @@ int esp_intr_mark_shared(int intno, int cpu, bool is_int_ram)
 
 int esp_intr_reserve(int intno, int cpu)
 {
-	if (intno >= ESP_INTC_INTS_NUM) {
+	if (intno >= SOC_CPU_INTR_NUM) {
 		return -EINVAL;
 	}
 	if (cpu >= arch_num_cpus()) {
@@ -263,7 +228,7 @@ static bool intr_has_handler(int intr, int cpu)
 {
 	bool r;
 
-	r = intr_alloc_table[intr * CONFIG_MP_MAX_NUM_CPUS + cpu].handler != default_intr_handler;
+	r = _sw_isr_table[intr * CONFIG_MP_MAX_NUM_CPUS + cpu].isr != z_irq_spurious;
 
 	return r;
 }
@@ -273,7 +238,6 @@ static bool is_vect_desc_usable(struct vector_desc_t *vd, int flags, int cpu, in
 	/* Check if interrupt is not reserved by design */
 	int x = vd->intno;
 	esp_cpu_intr_desc_t intr_desc;
-
 	esp_cpu_intr_get_desc(cpu, x, &intr_desc);
 
 	if (intr_desc.flags & ESP_CPU_INTR_DESC_FLAG_RESVD) {
@@ -286,14 +250,14 @@ static bool is_vect_desc_usable(struct vector_desc_t *vd, int flags, int cpu, in
 	}
 
 #ifndef SOC_CPU_HAS_FLEXIBLE_INTC
-	/* Check if the interrupt priority is acceptable */
+	/* Check if the interrupt level is acceptable */
 	if (!(flags & (1 << intr_desc.priority))) {
-		INTC_LOG("....Unusable: incompatible priority");
+		INTC_LOG("....Unusable: incompatible level");
 		return false;
 	}
 	/* check if edge/level type matches what we want */
 	if (((flags & ESP_INTR_FLAG_EDGE) && (intr_desc.type == ESP_CPU_INTR_TYPE_LEVEL)) ||
-		(((!(flags & ESP_INTR_FLAG_EDGE)) && (intr_desc.type == ESP_CPU_INTR_TYPE_EDGE)))) {
+	    (((!(flags & ESP_INTR_FLAG_EDGE)) && (intr_desc.type == ESP_CPU_INTR_TYPE_EDGE)))) {
 		INTC_LOG("....Unusable: incompatible trigger type");
 		return false;
 	}
@@ -335,7 +299,6 @@ static bool is_vect_desc_usable(struct vector_desc_t *vd, int flags, int cpu, in
 			return false;
 		}
 	} else if (intr_has_handler(x, cpu)) {
-		/* Check if interrupt already is allocated by set_interrupt_handler */
 		INTC_LOG("....Unusable: already allocated");
 		return false;
 	}
@@ -400,7 +363,7 @@ static int get_available_int(int flags, int cpu, int force, int source)
 
 	INTC_LOG("%s: start looking. Current cpu: %d", __func__, cpu);
 	/* No allocated handlers as well as forced intr, iterate over the 32 possible interrupts */
-	for (x = 0; x < ESP_INTC_INTS_NUM; x++) {
+	for (x = 0; x < SOC_CPU_INTR_NUM; x++) {
 		/* Grab the vector_desc for this vector. */
 		vd = find_desc_for_int(x, cpu);
 		if (vd == NULL) {
@@ -409,12 +372,10 @@ static int get_available_int(int flags, int cpu, int force, int source)
 		}
 
 		esp_cpu_intr_desc_t intr_desc;
-
 		esp_cpu_intr_get_desc(cpu, x, &intr_desc);
 
 		INTC_LOG("Int %d reserved %d level %d %s hasIsr %d",
-			 x, intr_desc.flags & ESP_CPU_INTR_DESC_FLAG_RESVD,
-			 intr_desc.priority,
+			 x, intr_desc.flags & ESP_CPU_INTR_DESC_FLAG_RESVD, intr_desc.priority,
 			 intr_desc.type == ESP_CPU_INTR_TYPE_LEVEL ? "LEVEL" : "EDGE",
 			 intr_has_handler(x, cpu));
 
@@ -438,7 +399,8 @@ static int get_available_int(int flags, int cpu, int force, int source)
 					no++;
 					svdesc = svdesc->next;
 				}
-				if (no < best_shared_ct || best_level > intr_desc.priority) {
+				if (no < best_shared_ct ||
+					best_level > intr_desc.priority) {
 					/*
 					 * Seems like this shared vector is both okay and has
 					 * the least amount of ISRs already attached to it.
@@ -500,8 +462,7 @@ static void IRAM_ATTR shared_intr_isr(void *arg)
 	esp_intr_lock();
 	while (sh_vec) {
 		if (!sh_vec->disabled) {
-			if ((sh_vec->statusreg == NULL) ||
-				(*sh_vec->statusreg & sh_vec->statusmask)) {
+			if (!(sh_vec->statusreg) || (*sh_vec->statusreg & sh_vec->statusmask)) {
 				sh_vec->isr(sh_vec->arg);
 			}
 		}
@@ -516,9 +477,9 @@ int esp_intr_alloc_intrstatus(int source,
 			      uint32_t intrstatusmask,
 			      intr_handler_t handler,
 			      void *arg,
-			      struct intr_handle_data_t **ret_handle)
+			     intr_handle_t *ret_handle)
 {
-	struct intr_handle_data_t *ret = NULL;
+	intr_handle_data_t *ret = NULL;
 	int force = -1;
 
 	INTC_LOG("%s (cpu %d): checking args", __func__, esp_cpu_get_core_id());
@@ -544,8 +505,8 @@ int esp_intr_alloc_intrstatus(int source,
 	 * we need to make sure the interrupt is connected to the CPU0.
 	 * CPU1 does not have access to the RTC fast memory through this region.
 	 */
-	if ((flags & ESP_INTR_FLAG_IRAM) && handler && !esp_ptr_in_iram(handler) &&
-		!esp_ptr_in_rtc_iram_fast(handler)) {
+	if ((flags & ESP_INTR_FLAG_IRAM) && handler &&
+	    !esp_ptr_in_iram(handler) && !esp_ptr_in_rtc_iram_fast(handler)) {
 		return -EINVAL;
 	}
 
@@ -636,16 +597,20 @@ int esp_intr_alloc_intrstatus(int source,
 		sv->disabled = 0;
 		vd->shared_vec_info = sv;
 		vd->flags |= VECDESC_FL_SHARED;
+
+		/* Disable interrupt to avoid assert at IRQ install */
+		irq_disable(intr);
+
 		/* (Re-)set shared isr handler to new value. */
-		set_interrupt_handler(intr, shared_intr_isr, vd);
+		irq_connect_dynamic(intr, 0, (intc_dyn_handler_t)shared_intr_isr, vd, 0);
 	} else {
 		/* Mark as unusable for other interrupt sources. This is ours now! */
 		vd->flags = VECDESC_FL_NONSHARED;
 		if (handler) {
-			set_interrupt_handler(intr, handler, arg);
+			irq_connect_dynamic(intr, 0, (intc_dyn_handler_t)handler, arg, 0);
 		}
 		if (flags & ESP_INTR_FLAG_EDGE) {
-			xthal_set_intclear(1 << intr);
+			esp_cpu_intr_edge_ack(intr);
 		}
 		vd->source = source;
 	}
@@ -675,10 +640,9 @@ int esp_intr_alloc_intrstatus(int source,
 		esp_intr_disable(ret);
 	}
 
-#ifdef SOC_CPU_HAS_FLEXIBLE_INTC
+#if SOC_CPU_HAS_FLEXIBLE_INTC
 	/* Extract the level from the interrupt passed flags */
 	int level = esp_intr_flags_to_level(flags);
-
 	esp_cpu_intr_set_priority(intr, level);
 
 	if (flags & ESP_INTR_FLAG_EDGE) {
@@ -688,6 +652,11 @@ int esp_intr_alloc_intrstatus(int source,
 	}
 #endif
 
+#if SOC_INT_PLIC_SUPPORTED
+	/* Make sure the interrupt is not delegated to user mode (IDF uses machine mode only) */
+	RV_CLEAR_CSR(mideleg, BIT(intr));
+#endif
+
 	esp_intr_unlock();
 
 	/* Fill return handle if needed, otherwise free handle. */
@@ -698,6 +667,7 @@ int esp_intr_alloc_intrstatus(int source,
 	}
 
 	LOG_DBG("Connected src %d to int %d (cpu %d)", source, intr, cpu);
+
 	return 0;
 }
 
@@ -705,7 +675,7 @@ int esp_intr_alloc(int source,
 		int flags,
 		intr_handler_t handler,
 		void *arg,
-		struct intr_handle_data_t **ret_handle)
+		intr_handle_t *ret_handle)
 {
 	/*
 	 * As an optimization, we can create a table with the possible interrupt status
@@ -715,7 +685,7 @@ int esp_intr_alloc(int source,
 	return esp_intr_alloc_intrstatus(source, flags, 0, 0, handler, arg, ret_handle);
 }
 
-int IRAM_ATTR esp_intr_set_in_iram(struct intr_handle_data_t *handle, bool is_in_iram)
+int IRAM_ATTR esp_intr_set_in_iram(intr_handle_t handle, bool is_in_iram)
 {
 	if (!handle) {
 		return -EINVAL;
@@ -739,7 +709,7 @@ int IRAM_ATTR esp_intr_set_in_iram(struct intr_handle_data_t *handle, bool is_in
 	return 0;
 }
 
-int esp_intr_free(struct intr_handle_data_t *handle)
+int esp_intr_free(intr_handle_t handle)
 {
 	bool free_shared_vector = false;
 
@@ -780,18 +750,20 @@ int esp_intr_free(struct intr_handle_data_t *handle)
 
 	if ((handle->vector_desc->flags & VECDESC_FL_NONSHARED) || free_shared_vector) {
 		INTC_LOG("%s: Disabling int, killing handler", __func__);
-		/* Reset to normal handler */
-		set_interrupt_handler(handle->vector_desc->intno,
-				      default_intr_handler,
-				      (void *)((int)handle->vector_desc->intno));
+
+		/* Disable interrupt to avoid assert at IRQ install */
+		irq_disable(handle->vector_desc->intno);
+
+		/* Reset IRQ handler */
+		irq_connect_dynamic(handle->vector_desc->intno, 0,
+				      (intc_dyn_handler_t)z_irq_spurious,
+				      (void *)((int)handle->vector_desc->intno), 0);
 		/*
 		 * Theoretically, we could free the vector_desc... not sure if that's worth the
 		 * few bytes of memory we save.(We can also not use the same exit path for empty
 		 * shared ints anymore if we delete the desc.) For now, just mark it as free.
 		 */
-		handle->vector_desc->flags &= ~(VECDESC_FL_NONSHARED |
-			VECDESC_FL_RESERVED | VECDESC_FL_SHARED);
-
+		handle->vector_desc->flags &= !(VECDESC_FL_NONSHARED | VECDESC_FL_RESERVED);
 		/* Also kill non_iram mask bit. */
 		non_iram_int_mask[handle->vector_desc->cpu] &= ~(1 << (handle->vector_desc->intno));
 	}
@@ -800,12 +772,12 @@ int esp_intr_free(struct intr_handle_data_t *handle)
 	return 0;
 }
 
-int esp_intr_get_intno(struct intr_handle_data_t *handle)
+int esp_intr_get_intno(intr_handle_t handle)
 {
 	return handle->vector_desc->intno;
 }
 
-int esp_intr_get_cpu(struct intr_handle_data_t *handle)
+int esp_intr_get_cpu(intr_handle_t handle)
 {
 	return handle->vector_desc->cpu;
 }
@@ -824,7 +796,7 @@ int esp_intr_get_cpu(struct intr_handle_data_t *handle)
  */
 #define INT_MUX_DISABLED_INTNO 6
 
-int IRAM_ATTR esp_intr_enable(struct intr_handle_data_t *handle)
+int IRAM_ATTR esp_intr_enable(intr_handle_t handle)
 {
 	if (!handle) {
 		return -EINVAL;
@@ -840,8 +812,8 @@ int IRAM_ATTR esp_intr_enable(struct intr_handle_data_t *handle)
 	}
 	if (source >= 0) {
 		/* Disabled using int matrix; re-connect to enable */
-		esp_rom_route_intr_matrix(handle->vector_desc->cpu,
-			source, handle->vector_desc->intno);
+		esp_rom_route_intr_matrix(handle->vector_desc->cpu, source,
+			handle->vector_desc->intno);
 	} else {
 		/* Re-enable using cpu int ena reg */
 		if (handle->vector_desc->cpu != esp_cpu_get_core_id()) {
@@ -854,7 +826,7 @@ int IRAM_ATTR esp_intr_enable(struct intr_handle_data_t *handle)
 	return 0;
 }
 
-int IRAM_ATTR esp_intr_disable(struct intr_handle_data_t *handle)
+int IRAM_ATTR esp_intr_disable(intr_handle_t handle)
 {
 	if (!handle) {
 		return -EINVAL;
@@ -884,8 +856,8 @@ int IRAM_ATTR esp_intr_disable(struct intr_handle_data_t *handle)
 	if (source >= 0) {
 		if (disabled) {
 			/* Disable using int matrix */
-			esp_rom_route_intr_matrix(handle->vector_desc->cpu,
-				source, INT_MUX_DISABLED_INTNO);
+			esp_rom_route_intr_matrix(handle->vector_desc->cpu, source,
+				INT_MUX_DISABLED_INTNO);
 		}
 	} else {
 		/* Disable using per-cpu regs */
@@ -899,7 +871,6 @@ int IRAM_ATTR esp_intr_disable(struct intr_handle_data_t *handle)
 	return 0;
 }
 
-
 void IRAM_ATTR esp_intr_noniram_disable(void)
 {
 	esp_intr_lock();
@@ -914,6 +885,7 @@ void IRAM_ATTR esp_intr_noniram_disable(void)
 	oldint = esp_cpu_intr_get_enabled_mask();
 	esp_cpu_intr_disable(non_iram_ints);
 	rtc_isr_noniram_disable(cpu);
+	/* Save which ints we did disable */
 	non_iram_int_disabled[cpu] = oldint & non_iram_ints;
 	esp_intr_unlock();
 }
@@ -932,3 +904,29 @@ void IRAM_ATTR esp_intr_noniram_enable(void)
 	rtc_isr_noniram_enable(cpu);
 	esp_intr_unlock();
 }
+
+#if defined(CONFIG_RISCV)
+/*
+ * Functions below are implemented to keep consistency with current
+ * Xtensa chips API behavior. When accessing Zephyr's API
+ * directly, the CPU IRQs can be enabled or disabled directly. This
+ * is mostly used to control lines that are not muxed, thus bypass the
+ * interrupt matrix. For RISCV, these functions are not expected to
+ * be used via user API, as peripherals are all routed through INTMUX
+ * and shared interrupts require managing sources state.
+ */
+void arch_irq_enable(unsigned int irq)
+{
+	esp_cpu_intr_enable(1 << irq);
+}
+
+void arch_irq_disable(unsigned int irq)
+{
+	esp_cpu_intr_disable(1 << irq);
+}
+
+int arch_irq_is_enabled(unsigned int irq)
+{
+	return !!(esp_cpu_intr_get_enabled_mask() & (1 << irq));
+}
+#endif
diff --git a/drivers/interrupt_controller/intc_esp32c3.c b/drivers/interrupt_controller/intc_esp32c3.c
deleted file mode 100644
index da889a8f0af..00000000000
--- a/drivers/interrupt_controller/intc_esp32c3.c
+++ /dev/null
@@ -1,296 +0,0 @@
-/*
- * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <stdbool.h>
-#include <string.h>
-#include <soc/periph_defs.h>
-#include <limits.h>
-#include <assert.h>
-#include "soc/soc.h"
-#include <soc.h>
-#include <zephyr/kernel.h>
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-#include <zephyr/sw_isr_table.h>
-#include <riscv/interrupt.h>
-
-#define ESP32C3_INTC_DEFAULT_PRIO			15
-
-#include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(intc_esp32c3, CONFIG_LOG_DEFAULT_LEVEL);
-
-/*
- * Define this to debug the choices made when allocating the interrupt. This leads to much debugging
- * output within a critical region, which can lead to weird effects like e.g. the interrupt watchdog
- * being triggered, that is why it is separate from the normal LOG* scheme.
- */
-#ifdef CONFIG_INTC_ESP32C3_DECISIONS_LOG
-# define INTC_LOG(...) LOG_INF(__VA_ARGS__)
-#else
-# define INTC_LOG(...) do {} while (0)
-#endif
-
-#define ESP32C3_INTC_DEFAULT_PRIORITY   15
-#define ESP32C3_INTC_DEFAULT_THRESHOLD  1
-#define ESP32C3_INTC_DISABLED_SLOT      31
-#define ESP32C3_INTC_SRCS_PER_IRQ       2
-#define ESP32C3_INTC_AVAILABLE_IRQS     30
-
-#if defined(CONFIG_SOC_SERIES_ESP32C6)
-
-#define IRQ_NA		0xFF	/* IRQ not available */
-#define IRQ_FREE	0xFE
-
-#define ESP32C6_INTC_SRCS_PER_IRQ       2
-#define ESP32C6_INTC_AVAILABLE_IRQS     31
-
-/* Interrupt overview for ESP32C6:
- * - 0, 3, 4, and 7 are used by the CPU for core-local interrupts (CLINT)
- * - 1 is used for Wi-Fi in Espressif HAL
- * - 2, 5, 6, 8 .. 31 are available for Zephyr
- * - 31 is reserved for disabled interrupts
- */
-static uint8_t esp_intr_irq_alloc[ESP32C6_INTC_AVAILABLE_IRQS][ESP32C6_INTC_SRCS_PER_IRQ] = {
-	[0] = {IRQ_NA, IRQ_NA},
-	[1] = {IRQ_NA, IRQ_NA},
-	[2] = {IRQ_FREE, IRQ_FREE},
-	[3] = {IRQ_NA, IRQ_NA},
-	[4] = {IRQ_NA, IRQ_NA},
-	[5 ... 6] = {IRQ_FREE, IRQ_FREE},
-	[7] = {IRQ_NA, IRQ_NA},
-	[8 ... 30] = {IRQ_FREE, IRQ_FREE}
-};
-#endif
-
-#define STATUS_MASK_NUM		3
-
-static uint32_t esp_intr_enabled_mask[STATUS_MASK_NUM] = {0, 0, 0};
-
-#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3)
-
-static uint32_t esp_intr_find_irq_for_source(uint32_t source)
-{
-	/* in general case, each 2 sources goes routed to
-	 * 1 IRQ line.
-	 */
-	uint32_t irq = (source / ESP32C3_INTC_SRCS_PER_IRQ);
-
-	if (irq > ESP32C3_INTC_AVAILABLE_IRQS) {
-		INTC_LOG("Clamping the source: %d no more IRQs available", source);
-		irq = ESP32C3_INTC_AVAILABLE_IRQS;
-	} else if (irq == 0) {
-		irq = 1;
-	}
-
-	INTC_LOG("Found IRQ: %d for source: %d", irq, source);
-
-	return irq;
-}
-
-#elif defined(CONFIG_SOC_SERIES_ESP32C6)
-
-static uint32_t esp_intr_find_irq_for_source(uint32_t source)
-{
-	uint32_t irq = IRQ_NA;
-	uint32_t irq_free = IRQ_NA;
-	uint8_t *irq_ptr = NULL;
-
-	/* First allocate one source per IRQ, then two
-	 * if there are more sources than free IRQs
-	 */
-	for (int j = 0; j < ESP32C6_INTC_SRCS_PER_IRQ; j++) {
-		for (int i = 0; i < ESP32C6_INTC_AVAILABLE_IRQS; i++) {
-			/* Find first free slot but keep searching to see
-			 * if source is already associated to an IRQ
-			 */
-			if (esp_intr_irq_alloc[i][j] == source) {
-				/* Source is already associated to an IRQ */
-				irq = i;
-				goto found;
-			} else if ((irq_free == IRQ_NA) && (esp_intr_irq_alloc[i][j] == IRQ_FREE)) {
-				irq_free = i;
-				irq_ptr = &esp_intr_irq_alloc[i][j];
-			}
-		}
-	}
-
-	if (irq_ptr != NULL) {
-		*irq_ptr = (uint8_t)source;
-		irq = irq_free;
-	} else {
-		return IRQ_NA;
-	}
-
-found:
-	INTC_LOG("Found IRQ: %d for source: %d", irq, source);
-
-	return irq;
-}
-
-#endif
-
-void esp_intr_initialize(void)
-{
-	/* IRQ 31 is reserved for disabled interrupts,
-	 * so route all sources to it
-	 */
-	for (int i = 0 ; i < ESP32C3_INTC_AVAILABLE_IRQS + 2; i++) {
-		irq_disable(i);
-	}
-
-	for (int i = 0; i < ETS_MAX_INTR_SOURCE; i++) {
-		esp_rom_intr_matrix_set(0, i, ESP32C3_INTC_DISABLED_SLOT);
-	}
-
-#if defined(CONFIG_SOC_SERIES_ESP32C6)
-	/* Clear up IRQ allocation */
-	for (int j = 0; j < ESP32C6_INTC_SRCS_PER_IRQ; j++) {
-		for (int i = 0; i < ESP32C6_INTC_AVAILABLE_IRQS; i++) {
-			/* screen out reserved IRQs */
-			if (esp_intr_irq_alloc[i][j] != IRQ_NA) {
-				esp_intr_irq_alloc[i][j] = IRQ_FREE;
-			}
-		}
-	}
-#endif
-
-	/* set global esp32c3's INTC masking level */
-	esprv_intc_int_set_threshold(ESP32C3_INTC_DEFAULT_THRESHOLD);
-}
-
-int esp_intr_alloc(int source,
-		int flags,
-		isr_handler_t handler,
-		void *arg,
-		void **ret_handle)
-{
-	ARG_UNUSED(flags);
-	ARG_UNUSED(ret_handle);
-
-	if (handler == NULL) {
-		return -EINVAL;
-	}
-
-	if (source < 0 || source >= ETS_MAX_INTR_SOURCE) {
-		return -EINVAL;
-	}
-
-	uint32_t key = irq_lock();
-
-	irq_connect_dynamic(source,
-		ESP32C3_INTC_DEFAULT_PRIORITY,
-		handler,
-		arg,
-		0);
-
-	if (source < 32) {
-		esp_intr_enabled_mask[0] |= (1 << source);
-	} else if (source < 64) {
-		esp_intr_enabled_mask[1] |= (1 << (source - 32));
-	} else if (source < 96) {
-		esp_intr_enabled_mask[2] |= (1 << (source - 64));
-	}
-
-	INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X",
-		esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]);
-
-	irq_unlock(key);
-	int ret = esp_intr_enable(source);
-
-	return ret;
-}
-
-int esp_intr_disable(int source)
-{
-	if (source < 0 || source >= ETS_MAX_INTR_SOURCE) {
-		return -EINVAL;
-	}
-
-	uint32_t key = irq_lock();
-
-	esp_rom_intr_matrix_set(0,
-		source,
-		ESP32C3_INTC_DISABLED_SLOT);
-
-#if defined(CONFIG_SOC_SERIES_ESP32C6)
-	for (int j = 0; j < ESP32C6_INTC_SRCS_PER_IRQ; j++) {
-		for (int i = 0; i < ESP32C6_INTC_AVAILABLE_IRQS; i++) {
-			if (esp_intr_irq_alloc[i][j] == source) {
-				esp_intr_irq_alloc[i][j] = IRQ_FREE;
-				goto freed;
-			}
-		}
-	}
-freed:
-#endif
-
-	if (source < 32) {
-		esp_intr_enabled_mask[0] &= ~(1 << source);
-	} else if (source < 64) {
-		esp_intr_enabled_mask[1] &= ~(1 << (source - 32));
-	} else if (source < 96) {
-		esp_intr_enabled_mask[2] &= ~(1 << (source - 64));
-	}
-
-	INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X",
-		esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]);
-
-	irq_unlock(key);
-
-	return 0;
-}
-
-int esp_intr_enable(int source)
-{
-	if (source < 0 || source >= ETS_MAX_INTR_SOURCE) {
-		return -EINVAL;
-	}
-
-	uint32_t key = irq_lock();
-	uint32_t irq = esp_intr_find_irq_for_source(source);
-
-#if defined(CONFIG_SOC_SERIES_ESP32C6)
-	if (irq == IRQ_NA) {
-		irq_unlock(key);
-		return -ENOMEM;
-	}
-#endif
-
-	esp_rom_intr_matrix_set(0, source, irq);
-
-	if (source < 32) {
-		esp_intr_enabled_mask[0] |= (1 << source);
-	} else if (source < 64) {
-		esp_intr_enabled_mask[1] |= (1 << (source - 32));
-	} else if (source < 96) {
-		esp_intr_enabled_mask[2] |= (1 << (source - 64));
-	}
-
-	INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X",
-		esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]);
-
-	esprv_intc_int_set_priority(irq, ESP32C3_INTC_DEFAULT_PRIO);
-	esprv_intc_int_set_type(irq, INTR_TYPE_LEVEL);
-	esprv_intc_int_enable(1 << irq);
-
-	irq_unlock(key);
-
-	return 0;
-}
-
-uint32_t esp_intr_get_enabled_intmask(int status_mask_number)
-{
-	INTC_LOG("Enabled ISRs -- 0: 0x%X -- 1: 0x%X -- 2: 0x%X",
-		esp_intr_enabled_mask[0], esp_intr_enabled_mask[1], esp_intr_enabled_mask[2]);
-
-	if (status_mask_number < STATUS_MASK_NUM) {
-		return esp_intr_enabled_mask[status_mask_number];
-	} else {
-		return 0;	/* error */
-	}
-}
diff --git a/drivers/interrupt_controller/intc_gic_common_priv.h b/drivers/interrupt_controller/intc_gic_common_priv.h
index f07d66a7cf5..4223196182f 100644
--- a/drivers/interrupt_controller/intc_gic_common_priv.h
+++ b/drivers/interrupt_controller/intc_gic_common_priv.h
@@ -8,29 +8,53 @@
 #define ZEPHYR_INCLUDE_DRIVERS_INTC_GIC_COMMON_PRIV_H_
 
 /* Offsets from GICD base or GICR(n) SGI_base */
-#define GIC_DIST_IGROUPR		0x0080
-#define GIC_DIST_ISENABLER		0x0100
-#define GIC_DIST_ICENABLER		0x0180
-#define GIC_DIST_ISPENDR		0x0200
-#define GIC_DIST_ICPENDR		0x0280
-#define GIC_DIST_ISACTIVER		0x0300
-#define GIC_DIST_ICACTIVER		0x0380
-#define GIC_DIST_IPRIORITYR		0x0400
-#define GIC_DIST_ITARGETSR		0x0800
-#define GIC_DIST_ICFGR			0x0c00
-#define GIC_DIST_IGROUPMODR		0x0d00
-#define GIC_DIST_SGIR			0x0f00
+#define GIC_DIST_IGROUPR    0x0080
+#define GIC_DIST_ISENABLER  0x0100
+#define GIC_DIST_ICENABLER  0x0180
+#define GIC_DIST_ISPENDR    0x0200
+#define GIC_DIST_ICPENDR    0x0280
+#define GIC_DIST_ISACTIVER  0x0300
+#define GIC_DIST_ICACTIVER  0x0380
+#define GIC_DIST_IPRIORITYR 0x0400
+#define GIC_DIST_ITARGETSR  0x0800
+#define GIC_DIST_ICFGR      0x0c00
+#define GIC_DIST_IGROUPMODR 0x0d00
+#define GIC_DIST_SGIR       0x0f00
+
+/* GICv3.1 Support for Extended SPI Range */
+#define GIC_ESPI_START        4096
+#define GIC_ESPI_END          5119
+#define GIC_DIST_IGROUPRnE    0x1000
+#define GIC_DIST_ISENABLERnE  0x1200
+#define GIC_DIST_ICENABLERnE  0x1400
+#define GIC_DIST_ISPENDRnE    0x1600
+#define GIC_DIST_ICPENDRnE    0x1800
+#define GIC_DIST_ISACTIVERnE  0x1a00
+#define GIC_DIST_ICACTIVERnE  0x1c00
+#define GIC_DIST_IPRIORITYRnE 0x2000
+#define GIC_DIST_ICFGRnE      0x3000
+#define GIC_DIST_IGROUPMODRnE 0x3400
 
 /* GICD GICR common access macros */
-#define IGROUPR(base, n)		(base + GIC_DIST_IGROUPR + (n) * 4)
-#define ISENABLER(base, n)		(base + GIC_DIST_ISENABLER + (n) * 4)
-#define ICENABLER(base, n)		(base + GIC_DIST_ICENABLER + (n) * 4)
-#define ISPENDR(base, n)		(base + GIC_DIST_ISPENDR + (n) * 4)
-#define ICPENDR(base, n)		(base + GIC_DIST_ICPENDR + (n) * 4)
-#define IPRIORITYR(base, n)		(base + GIC_DIST_IPRIORITYR + n)
-#define ITARGETSR(base, n)		(base + GIC_DIST_ITARGETSR + (n) * 4)
-#define ICFGR(base, n)			(base + GIC_DIST_ICFGR + (n) * 4)
-#define IGROUPMODR(base, n)		(base + GIC_DIST_IGROUPMODR + (n) * 4)
+#define IGROUPR(base, n)    (base + GIC_DIST_IGROUPR + (n) * 4)
+#define ISENABLER(base, n)  (base + GIC_DIST_ISENABLER + (n) * 4)
+#define ICENABLER(base, n)  (base + GIC_DIST_ICENABLER + (n) * 4)
+#define ISPENDR(base, n)    (base + GIC_DIST_ISPENDR + (n) * 4)
+#define ICPENDR(base, n)    (base + GIC_DIST_ICPENDR + (n) * 4)
+#define IPRIORITYR(base, n) (base + GIC_DIST_IPRIORITYR + n)
+#define ITARGETSR(base, n)  (base + GIC_DIST_ITARGETSR + (n) * 4)
+#define ICFGR(base, n)      (base + GIC_DIST_ICFGR + (n) * 4)
+#define IGROUPMODR(base, n) (base + GIC_DIST_IGROUPMODR + (n) * 4)
+
+/* GICD Extended SPI (GICv3.1) common access macros */
+#define IGROUPRnE(base, n)    (base + GIC_DIST_IGROUPRnE + (n) * 4)
+#define ISENABLERnE(base, n)  (base + GIC_DIST_ISENABLERnE + (n) * 4)
+#define ICENABLERnE(base, n)  (base + GIC_DIST_ICENABLERnE + (n) * 4)
+#define ISPENDRnE(base, n)    (base + GIC_DIST_ISPENDRnE + (n) * 4)
+#define ICPENDRnE(base, n)    (base + GIC_DIST_ICPENDRnE + (n) * 4)
+#define IPRIORITYRnE(base, n) (base + GIC_DIST_IPRIORITYRnE + n)
+#define ICFGRnE(base, n)      (base + GIC_DIST_ICFGRnE + (n) * 4)
+#define IGROUPMODRnE(base, n) (base + GIC_DIST_IGROUPMODRnE + (n) * 4)
 
 /*
  * selects redistributor SGI_base for current core for PPI and SGI
@@ -39,10 +63,11 @@
  */
 
 #if CONFIG_GIC_VER <= 2
-#define GET_DIST_BASE(intid)	GIC_DIST_BASE
+#define GET_DIST_BASE(intid) GIC_DIST_BASE
+#define GIC_IS_ESPI(intid)   0
 #else
-#define GET_DIST_BASE(intid)	((intid < GIC_SPI_INT_BASE) ? \
-				(gic_get_rdist() + GICR_SGI_BASE_OFF) \
-				: GIC_DIST_BASE)
+#define GET_DIST_BASE(intid)                                                                       \
+	((intid < GIC_SPI_INT_BASE) ? (gic_get_rdist() + GICR_SGI_BASE_OFF) : GIC_DIST_BASE)
+#define GIC_IS_ESPI(intid) ((intid >= GIC_ESPI_START) && (intid <= GIC_ESPI_END))
 #endif
 #endif /* ZEPHYR_INCLUDE_DRIVERS_INTC_GIC_COMMON_PRIV_H */
diff --git a/drivers/interrupt_controller/intc_gicv3.c b/drivers/interrupt_controller/intc_gicv3.c
index c84a42c7e36..cc22eaedb17 100644
--- a/drivers/interrupt_controller/intc_gicv3.c
+++ b/drivers/interrupt_controller/intc_gicv3.c
@@ -1,6 +1,7 @@
 /*
  * Copyright 2020 Broadcom
  * Copyright 2024 NXP
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,13 +21,38 @@
 
 #define DT_DRV_COMPAT arm_gic_v3
 
+#define GIC_V3_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(DT_DRV_COMPAT)
+
+#define GIC_REDISTRIBUTOR_STRIDE      DT_PROP_OR(GIC_V3_NODE, redistributor_stride, 0)
+#define GIC_NUM_REDISTRIBUTOR_REGIONS DT_PROP_OR(GIC_V3_NODE, redistributor_regions, 1)
+
+#define GIC_REG_REGION(idx, node_id)                                                               \
+	{                                                                                          \
+		.base = DT_REG_ADDR_BY_IDX(node_id, idx),                                          \
+		.size = DT_REG_SIZE_BY_IDX(node_id, idx),                                          \
+	}
+
+/*
+ * Structure to save GIC register region info
+ */
+struct gic_reg_region {
+	mem_addr_t base;
+	mem_addr_t size;
+};
+
+/*
+ * GIC register regions info table
+ */
+static struct gic_reg_region gic_reg_regions[] = {
+	LISTIFY(DT_NUM_REGS(GIC_V3_NODE), GIC_REG_REGION, (,), GIC_V3_NODE) };
+
 /* Redistributor base addresses for each core */
 mem_addr_t gic_rdists[CONFIG_MP_MAX_NUM_CPUS];
 
 #if defined(CONFIG_ARMV8_A_NS) || defined(CONFIG_GIC_SINGLE_SECURITY_STATE)
-#define IGROUPR_VAL	0xFFFFFFFFU
+#define IGROUPR_VAL 0xFFFFFFFFU
 #else
-#define IGROUPR_VAL	0x0U
+#define IGROUPR_VAL 0x0U
 #endif
 
 /*
@@ -34,10 +60,10 @@ mem_addr_t gic_rdists[CONFIG_MP_MAX_NUM_CPUS];
  * deal with (one configuration byte per interrupt). PENDBASE has to
  * be 64kB aligned (one bit per LPI, plus 8192 bits for SPI/PPI/SGI).
  */
-#define ITS_MAX_LPI_NRBITS	16 /* 64K LPIs */
+#define ITS_MAX_LPI_NRBITS 16 /* 64K LPIs */
 
-#define LPI_PROPBASE_SZ(nrbits)	ROUND_UP(BIT(nrbits), KB(64))
-#define LPI_PENDBASE_SZ(nrbits)	ROUND_UP(BIT(nrbits) / 8, KB(64))
+#define LPI_PROPBASE_SZ(nrbits) ROUND_UP(BIT(nrbits), KB(64))
+#define LPI_PENDBASE_SZ(nrbits) ROUND_UP(BIT(nrbits) / 8, KB(64))
 
 #ifdef CONFIG_GIC_V3_ITS
 static uintptr_t lpi_prop_table;
@@ -113,7 +139,13 @@ static bool arm_gic_lpi_is_enabled(unsigned int intid)
 #if defined(CONFIG_ARMV8_A_NS) || defined(CONFIG_GIC_SINGLE_SECURITY_STATE)
 static inline void arm_gic_write_irouter(uint64_t val, unsigned int intid)
 {
-	mem_addr_t addr = IROUTER(GET_DIST_BASE(intid), intid);
+	mem_addr_t addr;
+
+	if (GIC_IS_ESPI(intid)) {
+		addr = IROUTERnE(GET_DIST_BASE(intid), intid - GIC_ESPI_START);
+	} else {
+		addr = IROUTER(GET_DIST_BASE(intid), intid);
+	}
 
 #ifdef CONFIG_ARM
 	sys_write32((uint32_t)val, addr);
@@ -124,8 +156,7 @@ static inline void arm_gic_write_irouter(uint64_t val, unsigned int intid)
 }
 #endif
 
-void arm_gic_irq_set_priority(unsigned int intid,
-			      unsigned int prio, uint32_t flags)
+void arm_gic_irq_set_priority(unsigned int intid, unsigned int prio, uint32_t flags)
 {
 #ifdef CONFIG_GIC_V3_ITS
 	if (intid >= 8192) {
@@ -134,29 +165,45 @@ void arm_gic_irq_set_priority(unsigned int intid,
 	}
 #endif
 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
-	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+	uint32_t idx = GIC_IS_ESPI(intid) ? ((intid - GIC_ESPI_START) / GIC_NUM_INTR_PER_REG)
+					  : (intid / GIC_NUM_INTR_PER_REG);
 	uint32_t shift;
 	uint32_t val;
 	mem_addr_t base = GET_DIST_BASE(intid);
 
 	/* Disable the interrupt */
-	sys_write32(mask, ICENABLER(base, idx));
+	if (GIC_IS_ESPI(intid)) {
+		sys_write32(mask, ICENABLERnE(base, idx));
+	} else {
+		sys_write32(mask, ICENABLER(base, idx));
+	}
+
 	gic_wait_rwp(intid);
 
 	/* PRIORITYR registers provide byte access */
-	sys_write8(prio & GIC_PRI_MASK, IPRIORITYR(base, intid));
+	if (GIC_IS_ESPI(intid)) {
+		sys_write8(prio & GIC_PRI_MASK, IPRIORITYRnE(base, intid - GIC_ESPI_START));
+	} else {
+		sys_write8(prio & GIC_PRI_MASK, IPRIORITYR(base, intid));
+	}
 
 	/* Interrupt type config */
 	if (!GIC_IS_SGI(intid)) {
-		idx = intid / GIC_NUM_CFG_PER_REG;
+		idx = GIC_IS_ESPI(intid) ? ((intid - GIC_ESPI_START) / GIC_NUM_CFG_PER_REG)
+					 : (intid / GIC_NUM_CFG_PER_REG);
 		shift = (intid & (GIC_NUM_CFG_PER_REG - 1)) * 2;
 
-		val = sys_read32(ICFGR(base, idx));
+		val = GIC_IS_ESPI(intid) ? sys_read32(ICFGRnE(base, idx))
+					 : sys_read32(ICFGR(base, idx));
 		val &= ~(GICD_ICFGR_MASK << shift);
 		if (flags & IRQ_TYPE_EDGE) {
 			val |= (GICD_ICFGR_TYPE << shift);
 		}
-		sys_write32(val, ICFGR(base, idx));
+		if (GIC_IS_ESPI(intid)) {
+			sys_write32(val, ICFGRnE(base, idx));
+		} else {
+			sys_write32(val, ICFGR(base, idx));
+		}
 	}
 }
 
@@ -169,7 +216,8 @@ void arm_gic_irq_enable(unsigned int intid)
 	}
 #endif
 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
-	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+	uint32_t idx = GIC_IS_ESPI(intid) ? ((intid - GIC_ESPI_START) / GIC_NUM_INTR_PER_REG)
+					  : (intid / GIC_NUM_INTR_PER_REG);
 
 #if defined(CONFIG_ARMV8_A_NS) || defined(CONFIG_GIC_SINGLE_SECURITY_STATE)
 	/*
@@ -177,12 +225,16 @@ void arm_gic_irq_enable(unsigned int intid)
 	 * is set to '1') and for GIC single security state (GICD_CTRL.ARE is set to '1'),
 	 * so need to set SPI's affinity, now set it to be the PE on which it is enabled.
 	 */
-	if (GIC_IS_SPI(intid)) {
+	if (GIC_IS_SPI(intid) || GIC_IS_ESPI(intid)) {
 		arm_gic_write_irouter(MPIDR_TO_CORE(GET_MPIDR()), intid);
 	}
 #endif
 
-	sys_write32(mask, ISENABLER(GET_DIST_BASE(intid), idx));
+	if (GIC_IS_ESPI(intid)) {
+		sys_write32(mask, ISENABLERnE(GET_DIST_BASE(intid), idx));
+	} else {
+		sys_write32(mask, ISENABLER(GET_DIST_BASE(intid), idx));
+	}
 }
 
 void arm_gic_irq_disable(unsigned int intid)
@@ -194,9 +246,15 @@ void arm_gic_irq_disable(unsigned int intid)
 	}
 #endif
 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
-	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+	uint32_t idx = GIC_IS_ESPI(intid) ? ((intid - GIC_ESPI_START) / GIC_NUM_INTR_PER_REG)
+					  : (intid / GIC_NUM_INTR_PER_REG);
+
+	if (GIC_IS_ESPI(intid)) {
+		sys_write32(mask, ICENABLERnE(GET_DIST_BASE(intid), idx));
+	} else {
+		sys_write32(mask, ICENABLER(GET_DIST_BASE(intid), idx));
+	}
 
-	sys_write32(mask, ICENABLER(GET_DIST_BASE(intid), idx));
 	/* poll to ensure write is complete */
 	gic_wait_rwp(intid);
 }
@@ -209,10 +267,12 @@ bool arm_gic_irq_is_enabled(unsigned int intid)
 	}
 #endif
 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
-	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+	uint32_t idx = GIC_IS_ESPI(intid) ? ((intid - GIC_ESPI_START) / GIC_NUM_INTR_PER_REG)
+					  : (intid / GIC_NUM_INTR_PER_REG);
 	uint32_t val;
 
-	val = sys_read32(ISENABLER(GET_DIST_BASE(intid), idx));
+	val = GIC_IS_ESPI(intid) ? sys_read32(ISENABLERnE(GET_DIST_BASE(intid), idx))
+				 : sys_read32(ISENABLER(GET_DIST_BASE(intid), idx));
 
 	return (val & mask) != 0;
 }
@@ -220,10 +280,12 @@ bool arm_gic_irq_is_enabled(unsigned int intid)
 bool arm_gic_irq_is_pending(unsigned int intid)
 {
 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
-	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+	uint32_t idx = GIC_IS_ESPI(intid) ? ((intid - GIC_ESPI_START) / GIC_NUM_INTR_PER_REG)
+					  : (intid / GIC_NUM_INTR_PER_REG);
 	uint32_t val;
 
-	val = sys_read32(ISPENDR(GET_DIST_BASE(intid), idx));
+	val = GIC_IS_ESPI(intid) ? sys_read32(ISPENDRnE(GET_DIST_BASE(intid), idx))
+				 : sys_read32(ISPENDR(GET_DIST_BASE(intid), idx));
 
 	return (val & mask) != 0;
 }
@@ -231,17 +293,27 @@ bool arm_gic_irq_is_pending(unsigned int intid)
 void arm_gic_irq_set_pending(unsigned int intid)
 {
 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
-	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+	uint32_t idx = GIC_IS_ESPI(intid) ? ((intid - GIC_ESPI_START) / GIC_NUM_INTR_PER_REG)
+					  : (intid / GIC_NUM_INTR_PER_REG);
 
-	sys_write32(mask, ISPENDR(GET_DIST_BASE(intid), idx));
+	if (GIC_IS_ESPI(intid)) {
+		sys_write32(mask, ISPENDRnE(GET_DIST_BASE(intid), idx));
+	} else {
+		sys_write32(mask, ISPENDR(GET_DIST_BASE(intid), idx));
+	}
 }
 
 void arm_gic_irq_clear_pending(unsigned int intid)
 {
 	uint32_t mask = BIT(intid & (GIC_NUM_INTR_PER_REG - 1));
-	uint32_t idx = intid / GIC_NUM_INTR_PER_REG;
+	uint32_t idx = GIC_IS_ESPI(intid) ? ((intid - GIC_ESPI_START) / GIC_NUM_INTR_PER_REG)
+					  : (intid / GIC_NUM_INTR_PER_REG);
 
-	sys_write32(mask, ICPENDR(GET_DIST_BASE(intid), idx));
+	if (GIC_IS_ESPI(intid)) {
+		sys_write32(mask, ICPENDRnE(GET_DIST_BASE(intid), idx));
+	} else {
+		sys_write32(mask, ICPENDR(GET_DIST_BASE(intid), idx));
+	}
 }
 
 unsigned int arm_gic_get_active(void)
@@ -273,8 +345,7 @@ void arm_gic_eoi(unsigned int intid)
 	write_sysreg(intid, ICC_EOIR1_EL1);
 }
 
-void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
-		   uint16_t target_list)
+void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff, uint16_t target_list)
 {
 	uint32_t aff3, aff2, aff1;
 	uint64_t sgi_val;
@@ -290,8 +361,7 @@ void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
 #else
 	aff3 = MPIDR_AFFLVL(target_aff, 3);
 #endif
-	sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_id,
-				   SGIR_IRM_TO_AFF, target_list);
+	sgi_val = GICV3_SGIR_VALUE(aff3, aff2, aff1, sgi_id, SGIR_IRM_TO_AFF, target_list);
 
 	barrier_dsync_fence_full();
 	write_sysreg(sgi_val, ICC_SGI1R);
@@ -333,8 +403,8 @@ static void gicv3_rdist_enable(mem_addr_t rdist)
  */
 static void gicv3_rdist_setup_lpis(mem_addr_t rdist)
 {
-	unsigned int lpi_id_bits = MIN(GICD_TYPER_IDBITS(sys_read32(GICD_TYPER)),
-				       ITS_MAX_LPI_NRBITS);
+	unsigned int lpi_id_bits =
+		MIN(GICD_TYPER_IDBITS(sys_read32(GICD_TYPER)), ITS_MAX_LPI_NRBITS);
 	uintptr_t lpi_pend_table;
 	uint64_t reg;
 	uint32_t ctlr;
@@ -365,8 +435,7 @@ static void gicv3_rdist_setup_lpis(mem_addr_t rdist)
 	reg = (GIC_BASER_SHARE_INNER << GITR_PENDBASER_SHAREABILITY_SHIFT) |
 	      (GIC_BASER_CACHE_RAWAWB << GITR_PENDBASER_INNER_CACHE_SHIFT) |
 	      (lpi_pend_table & (GITR_PENDBASER_ADDR_MASK << GITR_PENDBASER_ADDR_SHIFT)) |
-	      (GIC_BASER_CACHE_INNERLIKE << GITR_PENDBASER_OUTER_CACHE_SHIFT) |
-	      GITR_PENDBASER_PTZ;
+	      (GIC_BASER_CACHE_INNERLIKE << GITR_PENDBASER_OUTER_CACHE_SHIFT) | GITR_PENDBASER_PTZ;
 	sys_write64(reg, rdist + GICR_PENDBASER);
 	/* TOFIX: check SHAREABILITY validity */
 
@@ -406,8 +475,7 @@ static void gicv3_cpuif_init(void)
 	/*
 	 * Configure default priorities for SGI 0:15 and PPI 0:15.
 	 */
-	for (intid = 0; intid < GIC_SPI_INT_BASE;
-	     intid += GIC_NUM_PRI_PER_REG) {
+	for (intid = 0; intid < GIC_SPI_INT_BASE; intid += GIC_NUM_PRI_PER_REG) {
 		sys_write32(GIC_INT_DEF_PRI_X4, IPRIORITYR(base, intid));
 	}
 
@@ -423,8 +491,8 @@ static void gicv3_cpuif_init(void)
 	icc_sre = read_sysreg(ICC_SRE_EL1);
 
 	if (!(icc_sre & ICC_SRE_ELx_SRE_BIT)) {
-		icc_sre = (icc_sre | ICC_SRE_ELx_SRE_BIT |
-			   ICC_SRE_ELx_DIB_BIT | ICC_SRE_ELx_DFB_BIT);
+		icc_sre =
+			(icc_sre | ICC_SRE_ELx_SRE_BIT | ICC_SRE_ELx_DIB_BIT | ICC_SRE_ELx_DFB_BIT);
 		write_sysreg(icc_sre, ICC_SRE_EL1);
 		icc_sre = read_sysreg(ICC_SRE_EL1);
 
@@ -442,7 +510,7 @@ static void gicv3_cpuif_init(void)
  */
 static void gicv3_dist_init(void)
 {
-	unsigned int num_ints;
+	unsigned int num_ints, num_espi;
 	unsigned int intid;
 	unsigned int idx;
 	mem_addr_t base = GIC_DIST_BASE;
@@ -459,6 +527,7 @@ static void gicv3_dist_init(void)
 #endif
 
 	num_ints = sys_read32(GICD_TYPER);
+	num_espi = (num_ints & GICD_TYPER_ESPI_MASK) ? ((num_ints >> 27) + 1) * 32 : 0;
 	num_ints &= GICD_TYPER_ITLINESNUM_MASK;
 	num_ints = (num_ints + 1) << 5;
 
@@ -473,46 +542,63 @@ static void gicv3_dist_init(void)
 	 */
 	sys_set_bit(GICD_CTLR, GICD_CTRL_NS);
 	__ASSERT(sys_test_bit(GICD_CTLR, GICD_CTRL_NS),
-		"Current GIC does not support single security state");
+		 "Current GIC does not support single security state");
 #endif
 
 	/*
 	 * Default configuration of all SPIs
 	 */
-	for (intid = GIC_SPI_INT_BASE; intid < num_ints;
-	     intid += GIC_NUM_INTR_PER_REG) {
+	for (intid = GIC_SPI_INT_BASE; intid < num_ints; intid += GIC_NUM_INTR_PER_REG) {
 		idx = intid / GIC_NUM_INTR_PER_REG;
 		/* Disable interrupt */
-		sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
-			    ICENABLER(base, idx));
+		sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICENABLER(base, idx));
 		/* Clear pending */
-		sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
-			    ICPENDR(base, idx));
+		sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICPENDR(base, idx));
 		sys_write32(IGROUPR_VAL, IGROUPR(base, idx));
-		sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
-			    IGROUPMODR(base, idx));
+		sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), IGROUPMODR(base, idx));
+	}
 
+	/*
+	 * Default configuration of all ESPIs
+	 */
+	for (intid = 0; intid < num_espi; intid += GIC_NUM_INTR_PER_REG) {
+		idx = intid / GIC_NUM_INTR_PER_REG;
+		/* Disable interrupt */
+		sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICENABLERnE(base, idx));
+		/* Clear pending */
+		sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICPENDRnE(base, idx));
+		sys_write32(IGROUPR_VAL, IGROUPRnE(base, idx));
+		sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), IGROUPMODRnE(base, idx));
 	}
+
 	/* wait for rwp on GICD */
 	gic_wait_rwp(GIC_SPI_INT_BASE);
 
 	/* Configure default priorities for all SPIs. */
-	for (intid = GIC_SPI_INT_BASE; intid < num_ints;
-	     intid += GIC_NUM_PRI_PER_REG) {
+	for (intid = GIC_SPI_INT_BASE; intid < num_ints; intid += GIC_NUM_PRI_PER_REG) {
 		sys_write32(GIC_INT_DEF_PRI_X4, IPRIORITYR(base, intid));
 	}
 
+	/* Configure default priorities for all ESPIs. */
+	for (intid = 0; intid < num_espi; intid += GIC_NUM_PRI_PER_REG) {
+		sys_write32(GIC_INT_DEF_PRI_X4, IPRIORITYRnE(base, intid));
+	}
+
 	/* Configure all SPIs as active low, level triggered by default */
-	for (intid = GIC_SPI_INT_BASE; intid < num_ints;
-	     intid += GIC_NUM_CFG_PER_REG) {
+	for (intid = GIC_SPI_INT_BASE; intid < num_ints; intid += GIC_NUM_CFG_PER_REG) {
 		idx = intid / GIC_NUM_CFG_PER_REG;
 		sys_write32(0, ICFGR(base, idx));
 	}
 
+	/* Configure all ESPIs as active low, level triggered by default */
+	for (intid = 0; intid < num_espi; intid += GIC_NUM_CFG_PER_REG) {
+		idx = intid / GIC_NUM_CFG_PER_REG;
+		sys_write32(0, ICFGRnE(base, idx));
+	}
+
 #ifdef CONFIG_ARMV8_A_NS
 	/* Enable distributor with ARE */
-	sys_write32(BIT(GICD_CTRL_ARE_NS) | BIT(GICD_CTLR_ENABLE_G1NS),
-		    GICD_CTLR);
+	sys_write32(BIT(GICD_CTRL_ARE_NS) | BIT(GICD_CTLR_ENABLE_G1NS), GICD_CTLR);
 #elif defined(CONFIG_GIC_SINGLE_SECURITY_STATE)
 	/*
 	 * For GIC single security state, the config GIC_SINGLE_SECURITY_STATE
@@ -524,8 +610,7 @@ static void gicv3_dist_init(void)
 	 * similarly the GICD_CTLR_ENABLE_G1 and GICD_CTLR_ENABLE_G1NS share
 	 * BIT(1), we can reuse them.
 	 */
-	sys_write32(BIT(GICD_CTRL_ARE_S) | BIT(GICD_CTLR_ENABLE_G1NS),
-		    GICD_CTLR);
+	sys_write32(BIT(GICD_CTRL_ARE_S) | BIT(GICD_CTLR_ENABLE_G1NS), GICD_CTLR);
 #else
 	/* enable Group 1 secure interrupts */
 	sys_set_bit(GICD_CTLR, GICD_CTLR_ENABLE_G1S);
@@ -578,20 +663,34 @@ static inline uint64_t arm_gic_get_typer(mem_addr_t addr)
 static mem_addr_t arm_gic_iterate_rdists(void)
 {
 	uint64_t aff = arm_gic_mpidr_to_affinity(GET_MPIDR());
+	uint32_t idx;
 
-	for (mem_addr_t rdist_addr = GIC_RDIST_BASE;
-		rdist_addr < GIC_RDIST_BASE + GIC_RDIST_SIZE;
-		rdist_addr += 0x20000) {
-		uint64_t val = arm_gic_get_typer(rdist_addr + GICR_TYPER);
-		uint64_t gicr_aff = GICR_TYPER_AFFINITY_VALUE_GET(val);
+	/* Skip the first array entry as it refers to the GIC distributor */
+	for (idx = 1; idx < GIC_NUM_REDISTRIBUTOR_REGIONS + 1; idx++) {
+		uint64_t val;
+		mem_addr_t rdist_addr = gic_reg_regions[idx].base;
+		mem_addr_t rdist_end = rdist_addr + gic_reg_regions[idx].size;
 
-		if (arm_gic_aff_matching(gicr_aff, aff)) {
-			return rdist_addr;
-		}
+		do {
+			val = arm_gic_get_typer(rdist_addr + GICR_TYPER);
+			uint64_t gicr_aff = GICR_TYPER_AFFINITY_VALUE_GET(val);
 
-		if (GICR_TYPER_LAST_GET(val) == 1) {
-			return (mem_addr_t)NULL;
-		}
+			if (arm_gic_aff_matching(gicr_aff, aff)) {
+				return rdist_addr;
+			}
+
+			if (GIC_REDISTRIBUTOR_STRIDE > 0) {
+				rdist_addr += GIC_REDISTRIBUTOR_STRIDE;
+			} else {
+				/*
+				 * Skip RD_base and SGI_base
+				 * In GICv3, GICR_TYPER.VLPIS bit is RES0 and can can be ignored
+				 * as there are no VLPI and reserved pages.
+				 */
+				rdist_addr += KB(64) * 2;
+			}
+
+		} while ((!GICR_TYPER_LAST_GET(val)) && (rdist_addr < rdist_end));
 	}
 
 	return (mem_addr_t)NULL;
@@ -626,8 +725,8 @@ int arm_gic_init(const struct device *dev)
 
 	return 0;
 }
-DEVICE_DT_INST_DEFINE(0, arm_gic_init, NULL, NULL, NULL,
-		      PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);
+DEVICE_DT_INST_DEFINE(0, arm_gic_init, NULL, NULL, NULL, PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY,
+		      NULL);
 
 #ifdef CONFIG_SMP
 void arm_gic_secondary_init(void)
diff --git a/drivers/interrupt_controller/intc_gicv3_priv.h b/drivers/interrupt_controller/intc_gicv3_priv.h
index 64fabe21537..4beda8c0496 100644
--- a/drivers/interrupt_controller/intc_gicv3_priv.h
+++ b/drivers/interrupt_controller/intc_gicv3_priv.h
@@ -1,5 +1,6 @@
 /*
  * Copyright 2020 Broadcom
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,270 +13,267 @@
 #include <zephyr/sys/atomic.h>
 
 /* Cache and Share ability for ITS & Redistributor LPI state tables */
-#define GIC_BASER_CACHE_NGNRNE		0x0UL /* Device-nGnRnE */
-#define GIC_BASER_CACHE_INNERLIKE	0x0UL /* Same as Inner Cacheability. */
-#define GIC_BASER_CACHE_NCACHEABLE	0x1UL /* Non-cacheable */
-#define GIC_BASER_CACHE_RAWT		0x2UL /* Cacheable R-allocate, W-through */
-#define GIC_BASER_CACHE_RAWB		0x3UL /* Cacheable R-allocate, W-back */
-#define GIC_BASER_CACHE_WAWT		0x4UL /* Cacheable W-allocate, W-through */
-#define GIC_BASER_CACHE_WAWB		0x5UL /* Cacheable W-allocate, W-back */
-#define GIC_BASER_CACHE_RAWAWT		0x6UL /* Cacheable R-allocate, W-allocate, W-through */
-#define GIC_BASER_CACHE_RAWAWB		0x7UL /* Cacheable R-allocate, W-allocate, W-back */
-#define GIC_BASER_SHARE_NO		0x0UL /* Non-shareable */
-#define GIC_BASER_SHARE_INNER		0x1UL /* Inner Shareable */
-#define GIC_BASER_SHARE_OUTER		0x2UL /* Outer Shareable */
-
-/*
- * GIC Register Interface Base Addresses
- */
-
-#define GIC_RDIST_BASE	DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1)
-#define GIC_RDIST_SIZE	DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1)
+#define GIC_BASER_CACHE_NGNRNE     0x0UL /* Device-nGnRnE */
+#define GIC_BASER_CACHE_INNERLIKE  0x0UL /* Same as Inner Cacheability. */
+#define GIC_BASER_CACHE_NCACHEABLE 0x1UL /* Non-cacheable */
+#define GIC_BASER_CACHE_RAWT       0x2UL /* Cacheable R-allocate, W-through */
+#define GIC_BASER_CACHE_RAWB       0x3UL /* Cacheable R-allocate, W-back */
+#define GIC_BASER_CACHE_WAWT       0x4UL /* Cacheable W-allocate, W-through */
+#define GIC_BASER_CACHE_WAWB       0x5UL /* Cacheable W-allocate, W-back */
+#define GIC_BASER_CACHE_RAWAWT     0x6UL /* Cacheable R-allocate, W-allocate, W-through */
+#define GIC_BASER_CACHE_RAWAWB     0x7UL /* Cacheable R-allocate, W-allocate, W-back */
+#define GIC_BASER_SHARE_NO         0x0UL /* Non-shareable */
+#define GIC_BASER_SHARE_INNER      0x1UL /* Inner Shareable */
+#define GIC_BASER_SHARE_OUTER      0x2UL /* Outer Shareable */
 
 /* SGI base is at 64K offset from Redistributor */
-#define GICR_SGI_BASE_OFF		0x10000
+#define GICR_SGI_BASE_OFF 0x10000
 
 /* GICR registers offset from RD_base(n) */
-#define GICR_CTLR			0x0000
-#define GICR_IIDR			0x0004
-#define GICR_TYPER			0x0008
-#define GICR_STATUSR			0x0010
-#define GICR_WAKER			0x0014
-#define GICR_PWRR			0x0024
-#define GICR_PROPBASER			0x0070
-#define GICR_PENDBASER			0x0078
+#define GICR_CTLR      0x0000
+#define GICR_IIDR      0x0004
+#define GICR_TYPER     0x0008
+#define GICR_STATUSR   0x0010
+#define GICR_WAKER     0x0014
+#define GICR_PWRR      0x0024
+#define GICR_PROPBASER 0x0070
+#define GICR_PENDBASER 0x0078
 
 /* Register bit definitions */
 
 /* GICD_CTLR Interrupt group definitions */
-#define GICD_CTLR_ENABLE_G0		0
-#define GICD_CTLR_ENABLE_G1NS		1
-#define GICD_CTLR_ENABLE_G1S		2
-#define GICD_CTRL_ARE_S			4
-#define GICD_CTRL_ARE_NS		5
-#define GICD_CTRL_NS			6
-#define GICD_CGRL_E1NWF			7
+#define GICD_CTLR_ENABLE_G0   0
+#define GICD_CTLR_ENABLE_G1NS 1
+#define GICD_CTLR_ENABLE_G1S  2
+#define GICD_CTRL_ARE_S       4
+#define GICD_CTRL_ARE_NS      5
+#define GICD_CTRL_NS          6
+#define GICD_CGRL_E1NWF       7
 
 /* GICD_CTLR Register write progress bit */
-#define GICD_CTLR_RWP			31
+#define GICD_CTLR_RWP 31
 
 /* GICR_CTLR */
-#define GICR_CTLR_ENABLE_LPIS		BIT(0)
-#define GICR_CTLR_RWP			3
+#define GICR_CTLR_ENABLE_LPIS BIT(0)
+#define GICR_CTLR_RWP         3
 
 /* GICR_IIDR */
-#define GICR_IIDR_PRODUCT_ID_SHIFT		24
-#define GICR_IIDR_PRODUCT_ID_MASK		0xFFUL
-#define GICR_IIDR_PRODUCT_ID_GET(_val)		MASK_GET(_val, GICR_IIDR_PRODUCT_ID)
+#define GICR_IIDR_PRODUCT_ID_SHIFT     24
+#define GICR_IIDR_PRODUCT_ID_MASK      0xFFUL
+#define GICR_IIDR_PRODUCT_ID_GET(_val) MASK_GET(_val, GICR_IIDR_PRODUCT_ID)
 
 /* GICR_TYPER */
-#define GICR_TYPER_AFFINITY_VALUE_SHIFT		32
-#define GICR_TYPER_AFFINITY_VALUE_MASK		0xFFFFFFFFUL
-#define GICR_TYPER_AFFINITY_VALUE_GET(_val)	MASK_GET(_val, GICR_TYPER_AFFINITY_VALUE)
-#define GICR_TYPER_LAST_SHIFT			4
-#define GICR_TYPER_LAST_MASK			0x1UL
-#define GICR_TYPER_LAST_GET(_val)		MASK_GET(_val, GICR_TYPER_LAST)
-#define GICR_TYPER_PROCESSOR_NUMBER_SHIFT	8
-#define GICR_TYPER_PROCESSOR_NUMBER_MASK	0xFFFFUL
-#define GICR_TYPER_PROCESSOR_NUMBER_GET(_val)	MASK_GET(_val, GICR_TYPER_PROCESSOR_NUMBER)
+#define GICR_TYPER_AFFINITY_VALUE_SHIFT       32
+#define GICR_TYPER_AFFINITY_VALUE_MASK        0xFFFFFFFFUL
+#define GICR_TYPER_AFFINITY_VALUE_GET(_val)   MASK_GET(_val, GICR_TYPER_AFFINITY_VALUE)
+#define GICR_TYPER_LAST_SHIFT                 4
+#define GICR_TYPER_LAST_MASK                  0x1UL
+#define GICR_TYPER_LAST_GET(_val)             MASK_GET(_val, GICR_TYPER_LAST)
+#define GICR_TYPER_PROCESSOR_NUMBER_SHIFT     8
+#define GICR_TYPER_PROCESSOR_NUMBER_MASK      0xFFFFUL
+#define GICR_TYPER_PROCESSOR_NUMBER_GET(_val) MASK_GET(_val, GICR_TYPER_PROCESSOR_NUMBER)
 
 /* GICR_WAKER */
-#define GICR_WAKER_PS			1
-#define GICR_WAKER_CA			2
+#define GICR_WAKER_PS 1
+#define GICR_WAKER_CA 2
 
 /* GICR_PWRR */
-#define GICR_PWRR_RDPD			0
-#define GICR_PWRR_RDAG			1
-#define GICR_PWRR_RDGPO			3
+#define GICR_PWRR_RDPD  0
+#define GICR_PWRR_RDAG  1
+#define GICR_PWRR_RDGPO 3
 
 /* GICR_PROPBASER */
-#define GITR_PROPBASER_ID_BITS_MASK		0x1fUL
-#define GITR_PROPBASER_INNER_CACHE_SHIFT	7
-#define GITR_PROPBASER_INNER_CACHE_MASK		0x7UL
-#define GITR_PROPBASER_SHAREABILITY_SHIFT	10
-#define GITR_PROPBASER_SHAREABILITY_MASK	0x3UL
-#define GITR_PROPBASER_ADDR_SHIFT		12
-#define GITR_PROPBASER_ADDR_MASK		0xFFFFFFFFFFUL
-#define GITR_PROPBASER_OUTER_CACHE_SHIFT	56
-#define GITR_PROPBASER_OUTER_CACHE_MASK		0x7UL
+#define GITR_PROPBASER_ID_BITS_MASK       0x1fUL
+#define GITR_PROPBASER_INNER_CACHE_SHIFT  7
+#define GITR_PROPBASER_INNER_CACHE_MASK   0x7UL
+#define GITR_PROPBASER_SHAREABILITY_SHIFT 10
+#define GITR_PROPBASER_SHAREABILITY_MASK  0x3UL
+#define GITR_PROPBASER_ADDR_SHIFT         12
+#define GITR_PROPBASER_ADDR_MASK          0xFFFFFFFFFFUL
+#define GITR_PROPBASER_OUTER_CACHE_SHIFT  56
+#define GITR_PROPBASER_OUTER_CACHE_MASK   0x7UL
 
 /* GICR_PENDBASER */
-#define GITR_PENDBASER_INNER_CACHE_SHIFT	7
-#define GITR_PENDBASER_INNER_CACHE_MASK		0x7UL
-#define GITR_PENDBASER_SHAREABILITY_SHIFT	10
-#define GITR_PENDBASER_SHAREABILITY_MASK	0x3UL
-#define GITR_PENDBASER_ADDR_SHIFT		16
-#define GITR_PENDBASER_ADDR_MASK		0xFFFFFFFFFUL
-#define GITR_PENDBASER_OUTER_CACHE_SHIFT	56
-#define GITR_PENDBASER_OUTER_CACHE_MASK		0x7UL
-#define GITR_PENDBASER_PTZ			BIT64(62)
-
-/* GITCD_IROUTER */
-#define GIC_DIST_IROUTER		0x6000
-#define IROUTER(base, n)		(base + GIC_DIST_IROUTER + (n) * 8)
+#define GITR_PENDBASER_INNER_CACHE_SHIFT  7
+#define GITR_PENDBASER_INNER_CACHE_MASK   0x7UL
+#define GITR_PENDBASER_SHAREABILITY_SHIFT 10
+#define GITR_PENDBASER_SHAREABILITY_MASK  0x3UL
+#define GITR_PENDBASER_ADDR_SHIFT         16
+#define GITR_PENDBASER_ADDR_MASK          0xFFFFFFFFFUL
+#define GITR_PENDBASER_OUTER_CACHE_SHIFT  56
+#define GITR_PENDBASER_OUTER_CACHE_MASK   0x7UL
+#define GITR_PENDBASER_PTZ                BIT64(62)
+
+/* GICD_IROUTER */
+#define GIC_DIST_IROUTER 0x6000
+#define IROUTER(base, n) (base + GIC_DIST_IROUTER + (n) * 8)
+
+/* GICD_IROUTERnE for GICv3.1 Extended SPI Range */
+#define GIC_DIST_IROUTERnE 0x8000
+#define IROUTERnE(base, n) (base + GIC_DIST_IROUTERnE + (n) * 8)
 
 /*
  * ITS registers, offsets from ITS_base
  */
-#define GITS_CTLR				0x0000
-#define GITS_IIDR				0x0004
-#define GITS_TYPER				0x0008
-#define GITS_STATUSR				0x0040
-#define GITS_UMSIR				0x0048
-#define GITS_CBASER				0x0080
-#define GITS_CWRITER				0x0088
-#define GITS_CREADR				0x0090
-#define GITS_BASER(n)				(0x0100 + ((n) * 8))
-
-#define GITS_TRANSLATER				0x10040
+#define GITS_CTLR     0x0000
+#define GITS_IIDR     0x0004
+#define GITS_TYPER    0x0008
+#define GITS_STATUSR  0x0040
+#define GITS_UMSIR    0x0048
+#define GITS_CBASER   0x0080
+#define GITS_CWRITER  0x0088
+#define GITS_CREADR   0x0090
+#define GITS_BASER(n) (0x0100 + ((n) * 8))
+
+#define GITS_TRANSLATER 0x10040
 
 /* ITS CTLR register */
-#define GITS_CTLR_ENABLED_SHIFT			0
-#define GITS_CTLR_ENABLED_MASK			0x1UL
-#define GITS_CTLR_ITS_NUMBER_SHIFT		4
-#define GITS_CTLR_ITS_NUMBER_MASK		0xfUL
-#define GITS_CTLR_QUIESCENT_SHIFT		31
-#define GITS_CTLR_QUIESCENT_MASK		0x1UL
+#define GITS_CTLR_ENABLED_SHIFT    0
+#define GITS_CTLR_ENABLED_MASK     0x1UL
+#define GITS_CTLR_ITS_NUMBER_SHIFT 4
+#define GITS_CTLR_ITS_NUMBER_MASK  0xfUL
+#define GITS_CTLR_QUIESCENT_SHIFT  31
+#define GITS_CTLR_QUIESCENT_MASK   0x1UL
 
-#define GITS_CTLR_ENABLED_GET(_val)		MASK_GET(_val, GITS_CTLR_ENABLED)
-#define GITS_CTLR_QUIESCENT_GET(_val)		MASK_GET(_val, GITS_CTLR_QUIESCENT)
+#define GITS_CTLR_ENABLED_GET(_val)   MASK_GET(_val, GITS_CTLR_ENABLED)
+#define GITS_CTLR_QUIESCENT_GET(_val) MASK_GET(_val, GITS_CTLR_QUIESCENT)
 
 /* ITS TYPER register */
-#define GITS_TYPER_PHY_SHIFT			0
-#define GITS_TYPER_PHY_MASK			0x1UL
-#define GITS_TYPER_VIRT_SHIFT			1
-#define GITS_TYPER_VIRT_MASK			0x1UL
-#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT		4
-#define GITS_TYPER_ITT_ENTRY_SIZE_MASK		0xfUL
-#define GITS_TYPER_IDBITS_SHIFT			8
-#define GITS_TYPER_IDBITS_MASK			0x1fUL
-#define GITS_TYPER_DEVBITS_SHIFT		13
-#define GITS_TYPER_DEVBITS_MASK			0x1fUL
-#define GITS_TYPER_SEIS_SHIFT			18
-#define GITS_TYPER_SEIS_MASK			0x1UL
-#define GITS_TYPER_PTA_SHIFT			19
-#define GITS_TYPER_PTA_MASK			0x1UL
-#define GITS_TYPER_HCC_SHIFT			24
-#define GITS_TYPER_HCC_MASK			0xffUL
-#define GITS_TYPER_CIDBITS_SHIFT		32
-#define GITS_TYPER_CIDBITS_MASK			0xfUL
-#define GITS_TYPER_CIL_SHIFT			36
-#define GITS_TYPER_CIL_MASK			0x1UL
-
-#define GITS_TYPER_ITT_ENTRY_SIZE_GET(_val)	MASK_GET(_val, GITS_TYPER_ITT_ENTRY_SIZE)
-#define GITS_TYPER_PTA_GET(_val)		MASK_GET(_val, GITS_TYPER_PTA)
-#define GITS_TYPER_HCC_GET(_val)		MASK_GET(_val, GITS_TYPER_HCC)
-#define GITS_TYPER_DEVBITS_GET(_val)		MASK_GET(_val, GITS_TYPER_DEVBITS)
+#define GITS_TYPER_PHY_SHIFT            0
+#define GITS_TYPER_PHY_MASK             0x1UL
+#define GITS_TYPER_VIRT_SHIFT           1
+#define GITS_TYPER_VIRT_MASK            0x1UL
+#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4
+#define GITS_TYPER_ITT_ENTRY_SIZE_MASK  0xfUL
+#define GITS_TYPER_IDBITS_SHIFT         8
+#define GITS_TYPER_IDBITS_MASK          0x1fUL
+#define GITS_TYPER_DEVBITS_SHIFT        13
+#define GITS_TYPER_DEVBITS_MASK         0x1fUL
+#define GITS_TYPER_SEIS_SHIFT           18
+#define GITS_TYPER_SEIS_MASK            0x1UL
+#define GITS_TYPER_PTA_SHIFT            19
+#define GITS_TYPER_PTA_MASK             0x1UL
+#define GITS_TYPER_HCC_SHIFT            24
+#define GITS_TYPER_HCC_MASK             0xffUL
+#define GITS_TYPER_CIDBITS_SHIFT        32
+#define GITS_TYPER_CIDBITS_MASK         0xfUL
+#define GITS_TYPER_CIL_SHIFT            36
+#define GITS_TYPER_CIL_MASK             0x1UL
+
+#define GITS_TYPER_ITT_ENTRY_SIZE_GET(_val) MASK_GET(_val, GITS_TYPER_ITT_ENTRY_SIZE)
+#define GITS_TYPER_PTA_GET(_val)            MASK_GET(_val, GITS_TYPER_PTA)
+#define GITS_TYPER_HCC_GET(_val)            MASK_GET(_val, GITS_TYPER_HCC)
+#define GITS_TYPER_DEVBITS_GET(_val)        MASK_GET(_val, GITS_TYPER_DEVBITS)
 
 /* ITS COMMON BASER / CBASER register */
 
 /* ITS CBASER register */
-#define GITS_CBASER_SIZE_SHIFT			0
-#define GITS_CBASER_SIZE_MASK			0xffUL
-#define GITS_CBASER_SHAREABILITY_SHIFT		10
-#define GITS_CBASER_SHAREABILITY_MASK		0x3UL
-#define GITS_CBASER_ADDR_SHIFT			12
-#define GITS_CBASER_ADDR_MASK			0xfffffffffUL
-#define GITS_CBASER_OUTER_CACHE_SHIFT		53
-#define GITS_CBASER_OUTER_CACHE_MASK		0x7UL
-#define GITS_CBASER_INNER_CACHE_SHIFT		59
-#define GITS_CBASER_INNER_CACHE_MASK		0x7UL
-#define GITS_CBASER_VALID_SHIFT			63
-#define GITS_CBASER_VALID_MASK			0x1UL
+#define GITS_CBASER_SIZE_SHIFT         0
+#define GITS_CBASER_SIZE_MASK          0xffUL
+#define GITS_CBASER_SHAREABILITY_SHIFT 10
+#define GITS_CBASER_SHAREABILITY_MASK  0x3UL
+#define GITS_CBASER_ADDR_SHIFT         12
+#define GITS_CBASER_ADDR_MASK          0xfffffffffUL
+#define GITS_CBASER_OUTER_CACHE_SHIFT  53
+#define GITS_CBASER_OUTER_CACHE_MASK   0x7UL
+#define GITS_CBASER_INNER_CACHE_SHIFT  59
+#define GITS_CBASER_INNER_CACHE_MASK   0x7UL
+#define GITS_CBASER_VALID_SHIFT        63
+#define GITS_CBASER_VALID_MASK         0x1UL
 
 /* ITS BASER<n> register */
-#define GITS_BASER_SIZE_SHIFT			0
-#define GITS_BASER_SIZE_MASK			0xffUL
-#define GITS_BASER_PAGE_SIZE_SHIFT		8
-#define GITS_BASER_PAGE_SIZE_MASK		0x3UL
-#define GITS_BASER_PAGE_SIZE_4K			0
-#define GITS_BASER_PAGE_SIZE_16K		1
-#define GITS_BASER_PAGE_SIZE_64K		2
-#define GITS_BASER_SHAREABILITY_SHIFT		10
-#define GITS_BASER_SHAREABILITY_MASK		0x3UL
-#define GITS_BASER_ADDR_SHIFT			12
-#define GITS_BASER_ADDR_MASK			0xfffffffff
-#define GITS_BASER_ENTRY_SIZE_SHIFT		48
-#define GITS_BASER_ENTRY_SIZE_MASK		0x1fUL
-#define GITS_BASER_OUTER_CACHE_SHIFT		53
-#define GITS_BASER_OUTER_CACHE_MASK		0x7UL
-#define GITS_BASER_TYPE_SHIFT			56
-#define GITS_BASER_TYPE_MASK			0x7UL
-#define GITS_BASER_INNER_CACHE_SHIFT		59
-#define GITS_BASER_INNER_CACHE_MASK		0x7UL
-#define GITS_BASER_INDIRECT_SHIFT		62
-#define GITS_BASER_INDIRECT_MASK		0x1UL
-#define GITS_BASER_VALID_SHIFT			63
-#define GITS_BASER_VALID_MASK			0x1UL
-
-#define GITS_BASER_TYPE_NONE			0
-#define GITS_BASER_TYPE_DEVICE			1
-#define GITS_BASER_TYPE_COLLECTION		4
-
-#define GITS_BASER_TYPE_GET(_val)		MASK_GET(_val, GITS_BASER_TYPE)
-#define GITS_BASER_PAGE_SIZE_GET(_val)		MASK_GET(_val, GITS_BASER_PAGE_SIZE)
-#define GITS_BASER_ENTRY_SIZE_GET(_val)		MASK_GET(_val, GITS_BASER_ENTRY_SIZE)
-#define GITS_BASER_INDIRECT_GET(_val)		MASK_GET(_val, GITS_BASER_INDIRECT)
-
-#define GITS_BASER_NR_REGS		8
+#define GITS_BASER_SIZE_SHIFT         0
+#define GITS_BASER_SIZE_MASK          0xffUL
+#define GITS_BASER_PAGE_SIZE_SHIFT    8
+#define GITS_BASER_PAGE_SIZE_MASK     0x3UL
+#define GITS_BASER_PAGE_SIZE_4K       0
+#define GITS_BASER_PAGE_SIZE_16K      1
+#define GITS_BASER_PAGE_SIZE_64K      2
+#define GITS_BASER_SHAREABILITY_SHIFT 10
+#define GITS_BASER_SHAREABILITY_MASK  0x3UL
+#define GITS_BASER_ADDR_SHIFT         12
+#define GITS_BASER_ADDR_MASK          0xfffffffff
+#define GITS_BASER_ENTRY_SIZE_SHIFT   48
+#define GITS_BASER_ENTRY_SIZE_MASK    0x1fUL
+#define GITS_BASER_OUTER_CACHE_SHIFT  53
+#define GITS_BASER_OUTER_CACHE_MASK   0x7UL
+#define GITS_BASER_TYPE_SHIFT         56
+#define GITS_BASER_TYPE_MASK          0x7UL
+#define GITS_BASER_INNER_CACHE_SHIFT  59
+#define GITS_BASER_INNER_CACHE_MASK   0x7UL
+#define GITS_BASER_INDIRECT_SHIFT     62
+#define GITS_BASER_INDIRECT_MASK      0x1UL
+#define GITS_BASER_VALID_SHIFT        63
+#define GITS_BASER_VALID_MASK         0x1UL
+
+#define GITS_BASER_TYPE_NONE       0
+#define GITS_BASER_TYPE_DEVICE     1
+#define GITS_BASER_TYPE_COLLECTION 4
+
+#define GITS_BASER_TYPE_GET(_val)       MASK_GET(_val, GITS_BASER_TYPE)
+#define GITS_BASER_PAGE_SIZE_GET(_val)  MASK_GET(_val, GITS_BASER_PAGE_SIZE)
+#define GITS_BASER_ENTRY_SIZE_GET(_val) MASK_GET(_val, GITS_BASER_ENTRY_SIZE)
+#define GITS_BASER_INDIRECT_GET(_val)   MASK_GET(_val, GITS_BASER_INDIRECT)
+
+#define GITS_BASER_NR_REGS 8
 
 /* ITS Commands */
 
-#define GITS_CMD_ID_MOVI			0x01
-#define GITS_CMD_ID_INT				0x03
-#define GITS_CMD_ID_CLEAR			0x04
-#define GITS_CMD_ID_SYNC			0x05
-#define GITS_CMD_ID_MAPD			0x08
-#define GITS_CMD_ID_MAPC			0x09
-#define GITS_CMD_ID_MAPTI			0x0a
-#define GITS_CMD_ID_MAPI			0x0b
-#define GITS_CMD_ID_INV				0x0c
-#define GITS_CMD_ID_INVALL			0x0d
-#define GITS_CMD_ID_MOVALL			0x0e
-#define GITS_CMD_ID_DISCARD			0x0f
-
-#define GITS_CMD_ID_OFFSET			0
-#define GITS_CMD_ID_SHIFT			0
-#define GITS_CMD_ID_MASK			0xffUL
-
-#define GITS_CMD_DEVICEID_OFFSET		0
-#define GITS_CMD_DEVICEID_SHIFT			32
-#define GITS_CMD_DEVICEID_MASK			0xffffffffUL
-
-#define GITS_CMD_SIZE_OFFSET			1
-#define GITS_CMD_SIZE_SHIFT			0
-#define GITS_CMD_SIZE_MASK			0x1fUL
-
-#define GITS_CMD_EVENTID_OFFSET			1
-#define GITS_CMD_EVENTID_SHIFT			0
-#define GITS_CMD_EVENTID_MASK			0xffffffffUL
-
-#define GITS_CMD_PINTID_OFFSET			1
-#define GITS_CMD_PINTID_SHIFT			32
-#define GITS_CMD_PINTID_MASK			0xffffffffUL
-
-#define GITS_CMD_ICID_OFFSET			2
-#define GITS_CMD_ICID_SHIFT			0
-#define GITS_CMD_ICID_MASK			0xffffUL
-
-#define GITS_CMD_ITTADDR_OFFSET			2
-#define GITS_CMD_ITTADDR_SHIFT			8
-#define GITS_CMD_ITTADDR_MASK			0xffffffffffUL
-#define GITS_CMD_ITTADDR_ALIGN			GITS_CMD_ITTADDR_SHIFT
-#define GITS_CMD_ITTADDR_ALIGN_SZ		(BIT(0) << GITS_CMD_ITTADDR_ALIGN)
-
-#define GITS_CMD_RDBASE_OFFSET			2
-#define GITS_CMD_RDBASE_SHIFT			16
-#define GITS_CMD_RDBASE_MASK			0xffffffffUL
-#define GITS_CMD_RDBASE_ALIGN			GITS_CMD_RDBASE_SHIFT
-
-#define GITS_CMD_VALID_OFFSET			2
-#define GITS_CMD_VALID_SHIFT			63
-#define GITS_CMD_VALID_MASK			0x1UL
-
-#define MASK(__basename)		(__basename##_MASK << __basename##_SHIFT)
-#define MASK_SET(__val, __basename)	(((__val) & __basename##_MASK) << __basename##_SHIFT)
-#define MASK_GET(__reg, __basename)	(((__reg) >> __basename##_SHIFT) & __basename##_MASK)
+#define GITS_CMD_ID_MOVI    0x01
+#define GITS_CMD_ID_INT     0x03
+#define GITS_CMD_ID_CLEAR   0x04
+#define GITS_CMD_ID_SYNC    0x05
+#define GITS_CMD_ID_MAPD    0x08
+#define GITS_CMD_ID_MAPC    0x09
+#define GITS_CMD_ID_MAPTI   0x0a
+#define GITS_CMD_ID_MAPI    0x0b
+#define GITS_CMD_ID_INV     0x0c
+#define GITS_CMD_ID_INVALL  0x0d
+#define GITS_CMD_ID_MOVALL  0x0e
+#define GITS_CMD_ID_DISCARD 0x0f
+
+#define GITS_CMD_ID_OFFSET 0
+#define GITS_CMD_ID_SHIFT  0
+#define GITS_CMD_ID_MASK   0xffUL
+
+#define GITS_CMD_DEVICEID_OFFSET 0
+#define GITS_CMD_DEVICEID_SHIFT  32
+#define GITS_CMD_DEVICEID_MASK   0xffffffffUL
+
+#define GITS_CMD_SIZE_OFFSET 1
+#define GITS_CMD_SIZE_SHIFT  0
+#define GITS_CMD_SIZE_MASK   0x1fUL
+
+#define GITS_CMD_EVENTID_OFFSET 1
+#define GITS_CMD_EVENTID_SHIFT  0
+#define GITS_CMD_EVENTID_MASK   0xffffffffUL
+
+#define GITS_CMD_PINTID_OFFSET 1
+#define GITS_CMD_PINTID_SHIFT  32
+#define GITS_CMD_PINTID_MASK   0xffffffffUL
+
+#define GITS_CMD_ICID_OFFSET 2
+#define GITS_CMD_ICID_SHIFT  0
+#define GITS_CMD_ICID_MASK   0xffffUL
+
+#define GITS_CMD_ITTADDR_OFFSET   2
+#define GITS_CMD_ITTADDR_SHIFT    8
+#define GITS_CMD_ITTADDR_MASK     0xffffffffffUL
+#define GITS_CMD_ITTADDR_ALIGN    GITS_CMD_ITTADDR_SHIFT
+#define GITS_CMD_ITTADDR_ALIGN_SZ (BIT(0) << GITS_CMD_ITTADDR_ALIGN)
+
+#define GITS_CMD_RDBASE_OFFSET 2
+#define GITS_CMD_RDBASE_SHIFT  16
+#define GITS_CMD_RDBASE_MASK   0xffffffffUL
+#define GITS_CMD_RDBASE_ALIGN  GITS_CMD_RDBASE_SHIFT
+
+#define GITS_CMD_VALID_OFFSET 2
+#define GITS_CMD_VALID_SHIFT  63
+#define GITS_CMD_VALID_MASK   0x1UL
+
+#define MASK(__basename)            (__basename##_MASK << __basename##_SHIFT)
+#define MASK_SET(__val, __basename) (((__val) & __basename##_MASK) << __basename##_SHIFT)
+#define MASK_GET(__reg, __basename) (((__reg) >> __basename##_SHIFT) & __basename##_MASK)
 
 #ifdef CONFIG_GIC_V3_ITS
 void its_rdist_map(void);
diff --git a/drivers/interrupt_controller/intc_ioapic.c b/drivers/interrupt_controller/intc_ioapic.c
index 0748ddccf76..6671da982ca 100644
--- a/drivers/interrupt_controller/intc_ioapic.c
+++ b/drivers/interrupt_controller/intc_ioapic.c
@@ -84,7 +84,7 @@ DEVICE_MMIO_TOPLEVEL_STATIC(ioapic_regs, DT_DRV_INST(0));
  * In either case, regardless how many CPUs in the system, 0xff implies that
  * it's intended to deliver to all possible 8 local APICs.
  */
-#define DEFAULT_RTE_DEST	(0xFF << 24)
+#define DEFAULT_RTE_DEST (0xFFU << 24)
 
 static __pinned_bss uint32_t ioapic_rtes;
 
diff --git a/drivers/interrupt_controller/intc_ite_it51xxx.c b/drivers/interrupt_controller/intc_ite_it51xxx.c
new file mode 100644
index 00000000000..3e70f8449df
--- /dev/null
+++ b/drivers/interrupt_controller/intc_ite_it51xxx.c
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc.h>
+#include <zephyr/dt-bindings/interrupt-controller/ite-it51xxx-intc.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(intc_ite_it51xxx, LOG_LEVEL_DBG);
+
+/* it51xxx INTC registers definition */
+#define INTC_REG_OFFSET(n) ((n) < 3 ? 1 : 2)
+#define INTC_GRPNISR(n)    (4 * ((n) + INTC_REG_OFFSET(n)))
+#define INTC_GRPNIER(n)    (4 * ((n) + INTC_REG_OFFSET(n)) + 1)
+#define INTC_GRPNIELMR(n)  (4 * ((n) + INTC_REG_OFFSET(n)) + 2)
+#define INTC_GRPNIPOLR(n)  (4 * ((n) + INTC_REG_OFFSET(n)) + 3)
+#define INTC_IVECT         0x10
+
+#define II51XXX_INTC_GROUP_COUNT 29
+#define MAX_REGISR_IRQ_NUM       8
+#define IVECT_OFFSET_WITH_IRQ    0x10
+
+static mm_reg_t intc_base = DT_REG_ADDR(DT_NODELABEL(intc));
+/* Interrupt number of INTC module */
+static uint8_t intc_irq;
+static uint8_t ier_setting[II51XXX_INTC_GROUP_COUNT];
+
+void ite_intc_save_and_disable_interrupts(void)
+{
+	volatile uint8_t _ier __unused;
+	/* Disable global interrupt for critical section */
+	unsigned int key = irq_lock();
+
+	/* Save and disable interrupts */
+	for (int i = 0; i < II51XXX_INTC_GROUP_COUNT; i++) {
+		ier_setting[i] = sys_read8(intc_base + INTC_GRPNIER(i));
+		sys_write8(0, intc_base + INTC_GRPNIER(i));
+	}
+	/*
+	 * This load operation will guarantee the above modification of
+	 * SOC's register can be seen by any following instructions.
+	 * Note: Barrier instruction can not synchronize chip register,
+	 * so we introduce workaround here.
+	 */
+	_ier = sys_read8(intc_base + INTC_GRPNIER(II51XXX_INTC_GROUP_COUNT - 1));
+
+	irq_unlock(key);
+}
+
+void ite_intc_restore_interrupts(void)
+{
+	/*
+	 * Ensure the highest priority interrupt will be the first fired
+	 * interrupt when soc is ready to go.
+	 */
+	unsigned int key = irq_lock();
+
+	/* Restore interrupt state */
+	for (int i = 0; i < II51XXX_INTC_GROUP_COUNT; i++) {
+		sys_write8(ier_setting[i], intc_base + INTC_GRPNIER(i));
+	}
+
+	irq_unlock(key);
+}
+
+void ite_intc_isr_clear(unsigned int irq)
+{
+	uint32_t g, i;
+
+	if (irq > CONFIG_NUM_IRQS) {
+		return;
+	}
+	g = irq / MAX_REGISR_IRQ_NUM;
+	i = irq % MAX_REGISR_IRQ_NUM;
+
+	sys_write8(BIT(i), intc_base + INTC_GRPNISR(g));
+}
+
+void ite_intc_irq_enable(unsigned int irq)
+{
+	uint32_t g, i;
+	uint8_t en;
+
+	if (irq > CONFIG_NUM_IRQS) {
+		return;
+	}
+	g = irq / MAX_REGISR_IRQ_NUM;
+	i = irq % MAX_REGISR_IRQ_NUM;
+
+	/* critical section due to run a bit-wise OR operation */
+	unsigned int key = irq_lock();
+
+	en = sys_read8(intc_base + INTC_GRPNIER(g));
+	sys_write8(en | BIT(i), intc_base + INTC_GRPNIER(g));
+
+	irq_unlock(key);
+}
+
+void ite_intc_irq_disable(unsigned int irq)
+{
+	uint32_t g, i;
+	uint8_t en;
+
+	volatile uint8_t _ier __unused;
+
+	if (irq > CONFIG_NUM_IRQS) {
+		return;
+	}
+	g = irq / MAX_REGISR_IRQ_NUM;
+	i = irq % MAX_REGISR_IRQ_NUM;
+
+	/* critical section due to run a bit-wise OR operation */
+	unsigned int key = irq_lock();
+
+	en = sys_read8(intc_base + INTC_GRPNIER(g));
+	sys_write8(en & ~BIT(i), intc_base + INTC_GRPNIER(g));
+	/*
+	 * This load operation will guarantee the above modification of
+	 * SOC's register can be seen by any following instructions.
+	 */
+	_ier = sys_read8(intc_base + INTC_GRPNIER(g));
+
+	irq_unlock(key);
+}
+
+void ite_intc_irq_polarity_set(unsigned int irq, unsigned int flags)
+{
+	uint32_t g, i;
+	uint8_t tri;
+
+	if ((irq > CONFIG_NUM_IRQS) || ((flags & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)) {
+		return;
+	}
+	g = irq / MAX_REGISR_IRQ_NUM;
+	i = irq % MAX_REGISR_IRQ_NUM;
+
+	tri = sys_read8(intc_base + INTC_GRPNIPOLR(g));
+	if ((flags & IRQ_TYPE_LEVEL_HIGH) || (flags & IRQ_TYPE_EDGE_RISING)) {
+		sys_write8(tri & ~BIT(i), intc_base + INTC_GRPNIPOLR(g));
+	} else {
+		sys_write8(tri | BIT(i), intc_base + INTC_GRPNIPOLR(g));
+	}
+
+	tri = sys_read8(intc_base + INTC_GRPNIELMR(g));
+	if ((flags & IRQ_TYPE_LEVEL_LOW) || (flags & IRQ_TYPE_LEVEL_HIGH)) {
+		sys_write8(tri & ~BIT(i), intc_base + INTC_GRPNIELMR(g));
+	} else {
+		sys_write8(tri | BIT(i), intc_base + INTC_GRPNIELMR(g));
+	}
+
+	/* W/C interrupt status of the pin */
+	sys_write8(BIT(i), intc_base + INTC_GRPNISR(g));
+}
+
+int ite_intc_irq_is_enable(unsigned int irq)
+{
+	uint32_t g, i;
+	uint8_t en;
+
+	if (irq > CONFIG_NUM_IRQS) {
+		return 0;
+	}
+	g = irq / MAX_REGISR_IRQ_NUM;
+	i = irq % MAX_REGISR_IRQ_NUM;
+
+	en = sys_read8(intc_base + INTC_GRPNIER(g));
+
+	return (en & BIT(i));
+}
+
+uint8_t ite_intc_get_irq_num(void)
+{
+	return intc_irq;
+}
+
+uint8_t get_irq(void *arg)
+{
+	ARG_UNUSED(arg);
+	/* wait until two equal interrupt values are read */
+	do {
+		/* Read interrupt number from interrupt vector register */
+		intc_irq = sys_read8(intc_base + INTC_IVECT);
+		/*
+		 * WORKAROUND: when the interrupt vector register (INTC_VECT)
+		 * isn't latched in a load operation, we read it again to make
+		 * sure the value we got is the correct value.
+		 */
+	} while (intc_irq != sys_read8(intc_base + INTC_IVECT));
+	/* determine interrupt number */
+	intc_irq -= IVECT_OFFSET_WITH_IRQ;
+	/* clear interrupt status */
+	ite_intc_isr_clear(intc_irq);
+	/* return interrupt number */
+	return intc_irq;
+}
+
+void soc_interrupt_init(void)
+{
+	/* Ensure interrupts of soc are disabled at default */
+	for (int i = 0; i < II51XXX_INTC_GROUP_COUNT; i++) {
+		sys_write8(0, intc_base + INTC_GRPNIER(i));
+	}
+
+	/* Enable M-mode external interrupt */
+	csr_set(mie, MIP_MEIP);
+}
diff --git a/drivers/interrupt_controller/intc_nuclei_eclic.S b/drivers/interrupt_controller/intc_nuclei_eclic.S
deleted file mode 100644
index 60577413395..00000000000
--- a/drivers/interrupt_controller/intc_nuclei_eclic.S
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright (c) 2024 Baumer Electric AG
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @brief Assembler-hooks specific to Nuclei's Extended Core Interrupt Controller
- */
-
-#include <zephyr/arch/cpu.h>
-
-
-GTEXT(__soc_handle_irq)
-/*
- * In an ECLIC, pending interrupts don't have to be cleared by hand.
- * In vectored mode, interrupts are cleared automatically.
- * In non-vectored mode, interrupts are cleared when writing the mnxti register (done in
- * __soc_handle_all_irqs).
- * Thus this function can directly return.
- */
-SECTION_FUNC(exception.other, __soc_handle_irq)
-	ret
-
-GTEXT(__soc_handle_all_irqs)
-
-#ifdef CONFIG_TRACING
-/* imports */
-GTEXT(sys_trace_isr_enter)
-GTEXT(sys_trace_isr_exit)
-#endif
-
-/*
- * This function services and clears all pending interrupts for an ECLIC in non-vectored mode.
- */
-SECTION_FUNC(exception.other, __soc_handle_all_irqs)
-	addi sp, sp, -16
-	sw ra, 0(sp)
-
-	/* Read and clear mnxti to get highest current interrupt and enable interrupts. Will return
-	 * original interrupt if no others appear. */
-	csrrci a0, 0x345, MSTATUS_IEN
-	beqz a0, irq_done /* Check if original interrupt vanished. */
-
-irq_loop:
-
-#ifdef CONFIG_TRACING_ISR
-	call sys_trace_isr_enter
-#endif
-
-	/* Call corresponding registered function in _sw_isr_table. a0 is offset in pointer with
-	 * the mtvt, sw irq table is 2-pointer wide -> shift by one. */
-	csrr t0, 0x307 /* mtvt */
-	sub a0, a0, t0
-	la t0, _sw_isr_table
-	slli a0, a0, (1)
-	add t0, t0, a0
-
-	/* Load argument in a0 register */
-	lw a0, 0(t0)
-
-	/* Load ISR function address in register t1 */
-	lw t1, RV_REGSIZE(t0)
-
-	/* Call ISR function */
-	jalr ra, t1, 0
-
-#ifdef CONFIG_TRACING_ISR
-	call sys_trace_isr_exit
-#endif
-
-	/* Read and clear mnxti to get highest current interrupt and enable interrupts. */
-	csrrci a0, 0x345, MSTATUS_IEN
-	bnez a0, irq_loop
-
-irq_done:
-	lw ra, 0(sp)
-	addi sp, sp, 16
-	ret
diff --git a/drivers/interrupt_controller/intc_nuclei_eclic.c b/drivers/interrupt_controller/intc_nuclei_eclic.c
deleted file mode 100644
index f141864bbf0..00000000000
--- a/drivers/interrupt_controller/intc_nuclei_eclic.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @brief Driver for Nuclie's Extended Core Interrupt Controller
- */
-
-#include <zephyr/kernel.h>
-#include <zephyr/arch/cpu.h>
-#include <zephyr/sys/util.h>
-#include <zephyr/device.h>
-
-#include <zephyr/sw_isr_table.h>
-#include <zephyr/drivers/interrupt_controller/riscv_clic.h>
-
-#define DT_DRV_COMPAT nuclei_eclic
-
-union CLICCFG {
-	struct {
-		uint8_t _reserved0 : 1;
-		/** number of interrupt level bits */
-		uint8_t nlbits : 4;
-		uint8_t _reserved1 : 2;
-		uint8_t _reserved2 : 1;
-	} b;
-	uint8_t w;
-};
-
-union CLICINFO {
-	struct {
-		/** number of max supported interrupts */
-		uint32_t numint : 13;
-		/** architecture version */
-		uint32_t version : 8;
-		/** supported bits in the clicintctl */
-		uint32_t intctlbits : 4;
-		uint32_t _reserved0 : 7;
-	} b;
-	uint32_t qw;
-};
-
-union CLICMTH {
-	uint8_t w;
-};
-
-union CLICINTIP {
-	struct {
-		/** Interrupt Pending */
-		uint8_t IP : 1;
-		uint8_t reserved0 : 7;
-	} b;
-	uint8_t w;
-};
-
-union CLICINTIE {
-	struct {
-		/** Interrupt Enabled */
-		uint8_t IE : 1;
-		uint8_t reserved0 : 7;
-	} b;
-	uint8_t w;
-};
-
-union CLICINTATTR {
-	struct {
-		/** 0: non-vectored 1:vectored */
-		uint8_t shv : 1;
-		/** 0: level 1: rising edge 2: falling edge */
-		uint8_t trg : 2;
-		uint8_t reserved0 : 3;
-		uint8_t reserved1 : 2;
-	} b;
-	uint8_t w;
-};
-
-struct CLICCTRL {
-	volatile union CLICINTIP INTIP;
-	volatile union CLICINTIE INTIE;
-	volatile union CLICINTATTR INTATTR;
-	volatile uint8_t INTCTRL;
-};
-
-/** CLIC INTATTR: TRIG Mask */
-#define CLIC_INTATTR_TRIG_Msk  0x3U
-
-#define ECLIC_CFG       (*((volatile union CLICCFG  *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 0))))
-#define ECLIC_INFO      (*((volatile union CLICINFO *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 1))))
-#define ECLIC_MTH       (*((volatile union CLICMTH  *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 2))))
-#define ECLIC_CTRL      ((volatile  struct CLICCTRL *)(DT_REG_ADDR_BY_IDX(DT_NODELABEL(eclic), 3)))
-#define ECLIC_CTRL_SIZE (DT_REG_SIZE_BY_IDX(DT_NODELABEL(eclic), 3))
-
-static uint8_t nlbits;
-static uint8_t intctlbits;
-static uint8_t max_prio;
-static uint8_t max_level;
-static uint8_t intctrl_mask;
-
-static inline uint8_t leftalign8(uint8_t val, uint8_t shift)
-{
-	return (val << (8U - shift));
-}
-
-static inline uint8_t mask8(uint8_t len)
-{
-	return ((1 << len) - 1) & 0xFFFFU;
-}
-
-/**
- * @brief Enable interrupt
- */
-void riscv_clic_irq_enable(uint32_t irq)
-{
-	ECLIC_CTRL[irq].INTIE.b.IE = 1;
-}
-
-/**
- * @brief Disable interrupt
- */
-void riscv_clic_irq_disable(uint32_t irq)
-{
-	ECLIC_CTRL[irq].INTIE.b.IE = 0;
-}
-
-/**
- * @brief Get enable status of interrupt
- */
-int riscv_clic_irq_is_enabled(uint32_t irq)
-{
-	return ECLIC_CTRL[irq].INTIE.b.IE;
-}
-
-/**
- * @brief Set priority and level of interrupt
- */
-void riscv_clic_irq_priority_set(uint32_t irq, uint32_t pri, uint32_t flags)
-{
-	const uint8_t prio = leftalign8(MIN(pri, max_prio), intctlbits);
-	const uint8_t level =  leftalign8(max_level, nlbits);
-	const uint8_t intctrl = (prio | level) | (~intctrl_mask);
-
-	ECLIC_CTRL[irq].INTCTRL = intctrl;
-
-	union CLICINTATTR intattr = {.w = 0};
-
-	/* Set non-vectoring as default. */
-	intattr.b.shv = 0;
-	intattr.b.trg = (uint8_t)(flags & CLIC_INTATTR_TRIG_Msk);
-	ECLIC_CTRL[irq].INTATTR = intattr;
-}
-
-/**
- * @brief Set vector mode of interrupt
- */
-void riscv_clic_irq_vector_set(uint32_t irq)
-{
-	/* Set Selective Hardware Vectoring. */
-	union CLICINTATTR intattr = ECLIC_CTRL[irq].INTATTR;
-
-	intattr.b.shv = 1;
-	ECLIC_CTRL[irq].INTATTR = intattr;
-}
-
-/**
- * @brief Set pending bit of an interrupt
- */
-void riscv_clic_irq_set_pending(uint32_t irq)
-{
-	ECLIC_CTRL[irq].INTIP.b.IP = 1;
-}
-
-static int nuclei_eclic_init(const struct device *dev)
-{
-	ECLIC_MTH.w = 0;
-	ECLIC_CFG.w = 0;
-	ECLIC_CFG.b.nlbits = 0;
-	for (int i = 0; i < ECLIC_CTRL_SIZE; i++) {
-		ECLIC_CTRL[i] = (struct CLICCTRL) { 0 };
-	}
-
-	nlbits = ECLIC_CFG.b.nlbits;
-	intctlbits = ECLIC_INFO.b.intctlbits;
-	max_prio = mask8(intctlbits - nlbits);
-	max_level = mask8(nlbits);
-	intctrl_mask = leftalign8(mask8(intctlbits), intctlbits);
-
-	return 0;
-}
-
-DEVICE_DT_INST_DEFINE(0, nuclei_eclic_init, NULL, NULL, NULL,
-		      PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);
diff --git a/drivers/interrupt_controller/intc_nxp_irqsteer.c b/drivers/interrupt_controller/intc_nxp_irqsteer.c
index 02c310dfbe6..95c03267eb1 100644
--- a/drivers/interrupt_controller/intc_nxp_irqsteer.c
+++ b/drivers/interrupt_controller/intc_nxp_irqsteer.c
@@ -265,6 +265,18 @@ LOG_MODULE_REGISTER(nxp_irqstr);
 #define DISPATCHER_REGMAP(disp) \
 	(((const struct irqsteer_config *)disp->dev->config)->regmap_phys)
 
+#if defined(CONFIG_XTENSA)
+#define irqstr_l1_irq_enable_raw(irq)     xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq))
+#define irqstr_l1_irq_disable_raw(irq)    xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq))
+#define irqsteer_level1_irq_is_enabled(irq) xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq))
+#elif defined(CONFIG_ARM)
+#define irqstr_l1_irq_enable_raw(irq)     arm_irq_enable(irq)
+#define irqstr_l1_irq_disable_raw(irq)    arm_irq_disable(irq)
+#define irqsteer_level1_irq_is_enabled(irq) arm_irq_is_enabled(irq)
+#else
+#error ARCH not supported
+#endif
+
 struct irqsteer_config {
 	uint32_t regmap_phys;
 	uint32_t regmap_size;
@@ -279,12 +291,12 @@ struct irqsteer_dispatcher {
 	uint32_t irq;
 	/* reference count for all IRQs aggregated by dispatcher */
 	uint8_t irq_refcnt[CONFIG_MAX_IRQ_PER_AGGREGATOR];
-	/* dispatcher lock */
-	struct k_spinlock lock;
-	/* reference count for dispatcher */
-	uint8_t refcnt;
 };
 
+static struct k_spinlock irqstr_lock;
+
+static uint8_t l1_irq_refcnt[CONFIG_2ND_LVL_ISR_TBL_OFFSET];
+
 static struct irqsteer_dispatcher dispatchers[] = {
 	IRQSTEER_DECLARE_DISPATCHERS(DT_NODELABEL(irqsteer))
 };
@@ -295,7 +307,7 @@ static int to_zephyr_irq(uint32_t regmap, uint32_t irq,
 {
 	int i, idx;
 
-	idx = irq;
+	idx = irq - FSL_FEATURE_IRQSTEER_IRQ_START_INDEX;
 
 	for (i = dispatcher->master_index - 1; i >= 0; i--) {
 		idx -= IRQSTEER_GetMasterIrqCount(UINT_TO_IRQSTEER(regmap), i);
@@ -313,10 +325,10 @@ static int to_system_irq(uint32_t regmap, int irq, int master_index)
 		irq += IRQSTEER_GetMasterIrqCount(UINT_TO_IRQSTEER(regmap), i);
 	}
 
-	return irq;
+	return irq + FSL_FEATURE_IRQSTEER_IRQ_START_INDEX;
 }
 
-/* used to convert zephyr INTID to system INTID */
+/* used to convert zephyr INTID (level 2) to system INTID */
 static int from_zephyr_irq(uint32_t regmap, uint32_t irq, uint32_t master_index)
 {
 	int i, idx;
@@ -327,73 +339,98 @@ static int from_zephyr_irq(uint32_t regmap, uint32_t irq, uint32_t master_index)
 		idx += IRQSTEER_GetMasterIrqCount(UINT_TO_IRQSTEER(regmap), i);
 	}
 
-	return idx;
+	return idx + FSL_FEATURE_IRQSTEER_IRQ_START_INDEX;
 }
 
-static void _irqstr_disp_enable_disable(struct irqsteer_dispatcher *disp,
-					bool enable)
+/* note: if disp != NULL that means there's several level2 interrupts
+ * multiplexed into this single level 1 line via irqsteer. In such cases,
+ * the interrupt needs to also be enable/disabled at the irqsteer level.
+ *
+ * brief: disp == NULL => IRQ is not managed by IRQSTEER
+ *        disp != NULL => IRQ is managed by IRQSTEER
+ */
+static void irqstr_l1_irq_enable_disable(uint32_t irq,
+					 struct irqsteer_dispatcher *disp,
+					 bool enable)
 {
-	uint32_t regmap = DISPATCHER_REGMAP(disp);
-
 	if (enable) {
-		xtensa_irq_enable(XTENSA_IRQ_NUMBER(disp->irq));
+		irqstr_l1_irq_enable_raw(irq);
 
-		IRQSTEER_EnableMasterInterrupt(UINT_TO_IRQSTEER(regmap), disp->irq);
+		if (disp) {
+			IRQSTEER_EnableMasterInterrupt(UINT_TO_IRQSTEER(DISPATCHER_REGMAP(disp)),
+						       irq);
+		}
 	} else {
-		IRQSTEER_DisableMasterInterrupt(UINT_TO_IRQSTEER(regmap), disp->irq);
+		if (disp) {
+			IRQSTEER_DisableMasterInterrupt(UINT_TO_IRQSTEER(DISPATCHER_REGMAP(disp)),
+							irq);
+		}
 
-		xtensa_irq_disable(XTENSA_IRQ_NUMBER(disp->irq));
+		irqstr_l1_irq_disable_raw(irq);
 	}
 }
 
-static void _irqstr_disp_get_unlocked(struct irqsteer_dispatcher *disp)
+static void irqstr_request_l1_irq_unlocked(uint32_t irq,
+					   struct irqsteer_dispatcher *disp)
 {
 	int ret;
 
-	if (disp->refcnt == UINT8_MAX) {
-		LOG_WRN("disp for irq %d reference count reached limit", disp->irq);
+#ifndef CONFIG_SHARED_INTERRUPTS
+	if (l1_irq_refcnt[irq]) {
+		LOG_WRN("L1 IRQ %d already requested", irq);
+		return;
+	}
+#endif /* CONFIG_SHARED_INTERRUPTS */
+
+	if (l1_irq_refcnt[irq] == UINT8_MAX) {
+		LOG_WRN("L1 IRQ %d reference count reached limit", irq);
 		return;
 	}
 
-	if (!disp->refcnt) {
-		ret = pm_device_runtime_get(disp->dev);
-		if (ret < 0) {
-			LOG_ERR("failed to enable PM resources: %d", ret);
-			return;
+	if (!l1_irq_refcnt[irq]) {
+		if (disp) {
+			ret = pm_device_runtime_get(disp->dev);
+			if (ret < 0) {
+				LOG_ERR("failed to enable PM resources: %d", ret);
+				return;
+			}
 		}
 
-		_irqstr_disp_enable_disable(disp, true);
+		irqstr_l1_irq_enable_disable(irq, disp, true);
 	}
 
-	disp->refcnt++;
+	l1_irq_refcnt[irq]++;
 
-	LOG_DBG("get on disp for irq %d results in refcnt: %d",
-		disp->irq, disp->refcnt);
+	LOG_DBG("request for L1 IRQ %d results in refcnt: %d",
+		irq, l1_irq_refcnt[irq]);
 }
 
-static void _irqstr_disp_put_unlocked(struct irqsteer_dispatcher *disp)
+static void irqstr_release_l1_irq_unlocked(uint32_t irq,
+					   struct irqsteer_dispatcher *disp)
 {
 	int ret;
 
-	if (!disp->refcnt) {
-		LOG_WRN("disp for irq %d already put", disp->irq);
+	if (!l1_irq_refcnt[irq]) {
+		LOG_WRN("L1 IRQ %d already released", irq);
 		return;
 	}
 
-	disp->refcnt--;
+	l1_irq_refcnt[irq]--;
 
-	if (!disp->refcnt) {
-		_irqstr_disp_enable_disable(disp, false);
+	if (!l1_irq_refcnt[irq]) {
+		irqstr_l1_irq_enable_disable(irq, disp, false);
 
-		ret = pm_device_runtime_put(disp->dev);
-		if (ret < 0) {
-			LOG_ERR("failed to disable PM resources: %d", ret);
-			return;
+		if (disp) {
+			ret = pm_device_runtime_put(disp->dev);
+			if (ret < 0) {
+				LOG_ERR("failed to disable PM resources: %d", ret);
+				return;
+			}
 		}
 	}
 
-	LOG_DBG("put on disp for irq %d results in refcnt: %d",
-		disp->irq, disp->refcnt);
+	LOG_DBG("release on L1 IRQ %d results in refcnt: %d",
+		irq, l1_irq_refcnt[irq]);
 }
 
 static void _irqstr_enable_disable_irq(struct irqsteer_dispatcher *disp,
@@ -427,7 +464,7 @@ static void irqstr_request_irq_unlocked(struct irqsteer_dispatcher *disp,
 	}
 
 	if (!disp->irq_refcnt[zephyr_irq]) {
-		_irqstr_disp_get_unlocked(disp);
+		irqstr_request_l1_irq_unlocked(disp->irq, disp);
 		_irqstr_enable_disable_irq(disp, system_irq, true);
 	}
 
@@ -452,7 +489,7 @@ static void irqstr_release_irq_unlocked(struct irqsteer_dispatcher *disp,
 
 	if (!disp->irq_refcnt[zephyr_irq]) {
 		_irqstr_enable_disable_irq(disp, system_irq, false);
-		_irqstr_disp_put_unlocked(disp);
+		irqstr_release_l1_irq_unlocked(disp->irq, disp);
 	}
 
 	LOG_DBG("released irq %d has refcount %d",
@@ -466,10 +503,12 @@ void z_soc_irq_enable_disable(uint32_t irq, bool enable)
 
 	if (irq_get_level(irq) == 1) {
 		/* LEVEL 1 interrupts are DSP direct */
-		if (enable) {
-			xtensa_irq_enable(XTENSA_IRQ_NUMBER(irq));
-		} else {
-			xtensa_irq_disable(XTENSA_IRQ_NUMBER(irq));
+		K_SPINLOCK(&irqstr_lock) {
+			if (enable) {
+				irqstr_request_l1_irq_unlocked(irq, NULL);
+			} else {
+				irqstr_release_l1_irq_unlocked(irq, NULL);
+			}
 		}
 		return;
 	}
@@ -483,7 +522,7 @@ void z_soc_irq_enable_disable(uint32_t irq, bool enable)
 			continue;
 		}
 
-		K_SPINLOCK(&dispatchers[i].lock) {
+		K_SPINLOCK(&irqstr_lock) {
 			if (enable) {
 				irqstr_request_irq_unlocked(&dispatchers[i], level2_irq);
 			} else {
@@ -510,15 +549,16 @@ int z_soc_irq_is_enabled(unsigned int irq)
 	uint32_t parent_irq;
 	int i;
 	const struct irqsteer_config *cfg;
-	bool enabled;
+	bool enabled = false;
 
 	if (irq_get_level(irq) == 1) {
-		/* LEVEL 1 interrupts are DSP direct */
-		return xtensa_irq_is_enabled(XTENSA_IRQ_NUMBER(irq));
+		K_SPINLOCK(&irqstr_lock) {
+			enabled = l1_irq_refcnt[irq];
+		}
+		return enabled;
 	}
 
 	parent_irq = irq_parent_level_2(irq);
-	enabled = false;
 
 	/* find dispatcher responsible for this interrupt */
 	for (i = 0; i < ARRAY_SIZE(dispatchers); i++) {
@@ -528,7 +568,7 @@ int z_soc_irq_is_enabled(unsigned int irq)
 
 		cfg = dispatchers[i].dev->config;
 
-		K_SPINLOCK(&dispatchers[i].lock) {
+		K_SPINLOCK(&irqstr_lock) {
 			enabled = dispatchers[i].irq_refcnt[irq_from_level_2(irq)];
 		}
 
@@ -538,6 +578,18 @@ int z_soc_irq_is_enabled(unsigned int irq)
 	return false;
 }
 
+#if defined(CONFIG_ARM)
+void z_soc_irq_priority_set(unsigned int irq, unsigned int prio, unsigned int flags)
+{
+	uint32_t level1_irq = irq;
+
+	if (irq_get_level(irq) != 1) {
+		level1_irq = irq_parent_level_2(irq);
+	}
+
+	arm_irq_priority_set(level1_irq, prio, flags);
+}
+#endif
 
 static void irqsteer_isr_dispatcher(const void *data)
 {
diff --git a/drivers/interrupt_controller/intc_renesas_ra_icu.c b/drivers/interrupt_controller/intc_renesas_ra_icu.c
deleted file mode 100644
index 57b9ac731ab..00000000000
--- a/drivers/interrupt_controller/intc_renesas_ra_icu.c
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * Copyright (c) 2023 TOKITTA Hiroshi <tokita.hiroshi@fujitsu.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DT_DRV_COMPAT renesas_ra_interrupt_controller_unit
-
-#include <zephyr/device.h>
-#include <zephyr/irq.h>
-#include <soc.h>
-#include <zephyr/drivers/interrupt_controller/intc_ra_icu.h>
-#include <zephyr/sw_isr_table.h>
-#include <errno.h>
-
-#define IELSRn_REG(n) (DT_INST_REG_ADDR(0) + IELSRn_OFFSET + (n * 4))
-#define IRQCRi_REG(i) (DT_INST_REG_ADDR(0) + IRQCRi_OFFSET + (i))
-
-#define IRQCRi_IRQMD_POS  0
-#define IRQCRi_IRQMD_MASK BIT_MASK(2)
-#define IELSRn_IR_POS     16
-#define IELSRn_IR_MASK    BIT_MASK(1)
-
-enum {
-	IRQCRi_OFFSET = 0x0,
-	IELSRn_OFFSET = 0x300,
-};
-
-int ra_icu_query_exists_irq(uint32_t event)
-{
-	for (uint32_t i = 0; i < CONFIG_NUM_IRQS; i++) {
-		uint32_t els = sys_read32(IELSRn_REG(i)) & UINT8_MAX;
-
-		if (event == els) {
-			return i;
-		}
-	}
-
-	return -EINVAL;
-}
-
-int ra_icu_query_available_irq(uint32_t event)
-{
-	int irq = -EINVAL;
-
-	if (ra_icu_query_exists_irq(event) > 0) {
-		return -EINVAL;
-	}
-
-	for (uint32_t i = 0; i < CONFIG_NUM_IRQS; i++) {
-		if (_sw_isr_table[i].isr == z_irq_spurious) {
-			irq = i;
-			break;
-		}
-	}
-
-	return irq;
-}
-
-void ra_icu_clear_int_flag(unsigned int irqn)
-{
-	uint32_t cfg = sys_read32(IELSRn_REG(irqn));
-
-	sys_write32(cfg & ~BIT(IELSRn_IR_POS), IELSRn_REG(irqn));
-}
-
-void ra_icu_query_irq_config(unsigned int irq, uint32_t *intcfg, ra_isr_handler *cb,
-			     const void **cbarg)
-{
-	*intcfg = sys_read32(IELSRn_REG(irq));
-	*cb = _sw_isr_table[irq].isr;
-	*cbarg = (void *)_sw_isr_table[irq].arg;
-}
-
-static void ra_icu_irq_configure(unsigned int irqn, uint32_t intcfg)
-{
-	uint8_t reg = sys_read8(IRQCRi_REG(irqn)) & ~(IRQCRi_IRQMD_MASK);
-
-	sys_write8(reg | (intcfg & IRQCRi_IRQMD_MASK), IRQCRi_REG(irqn));
-}
-
-int ra_icu_irq_connect_dynamic(unsigned int irq, unsigned int priority,
-			       void (*routine)(const void *parameter), const void *parameter,
-			       uint32_t flags)
-{
-	uint32_t event = ((flags & RA_ICU_FLAG_EVENT_MASK) >> RA_ICU_FLAG_EVENT_OFFSET);
-	uint32_t intcfg = ((flags & RA_ICU_FLAG_INTCFG_MASK) >> RA_ICU_FLAG_INTCFG_OFFSET);
-	int irqn = irq;
-
-	if (irq == RA_ICU_IRQ_UNSPECIFIED) {
-		irqn = ra_icu_query_available_irq(event);
-		if (irqn < 0) {
-			return irqn;
-		}
-	}
-
-	irq_disable(irqn);
-	sys_write32(event, IELSRn_REG(irqn));
-	z_isr_install(irqn, routine, parameter);
-	z_arm_irq_priority_set(irqn, priority, flags);
-	ra_icu_irq_configure(event, intcfg);
-
-	return irqn;
-}
-
-int ra_icu_irq_disconnect_dynamic(unsigned int irq, unsigned int priority,
-				  void (*routine)(const void *parameter), const void *parameter,
-				  uint32_t flags)
-{
-	int irqn = irq;
-
-	if (irq == RA_ICU_IRQ_UNSPECIFIED) {
-		return -EINVAL;
-	}
-
-	irq_disable(irqn);
-	sys_write32(0, IELSRn_REG(irqn));
-	z_isr_install(irqn, z_irq_spurious, NULL);
-	z_arm_irq_priority_set(irqn, 0, 0);
-
-	return 0;
-}
-
-DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, NULL, PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);
diff --git a/drivers/interrupt_controller/intc_renesas_rz_ext_irq.c b/drivers/interrupt_controller/intc_renesas_rz_ext_irq.c
new file mode 100644
index 00000000000..a6358e07345
--- /dev/null
+++ b/drivers/interrupt_controller/intc_renesas_rz_ext_irq.c
@@ -0,0 +1,242 @@
+/*
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_rz_ext_irq
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+#if defined(CONFIG_SOC_SERIES_RZG3S)
+#include <instances/rzg/r_intc_irq.h>
+#include <instances/rzg/r_intc_nmi.h>
+#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) ||                      \
+	defined(CONFIG_SOC_SERIES_RZT2M)
+#include <instances/rzn/r_icu.h>
+#endif /* CONFIG_SOC_SERIES_* */
+#include <zephyr/drivers/interrupt_controller/intc_rz_ext_irq.h>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+
+LOG_MODULE_REGISTER(rz_ext_irq, CONFIG_INTC_LOG_LEVEL);
+
+struct intc_rz_ext_irq_config {
+	const struct pinctrl_dev_config *pin_config;
+	const external_irq_cfg_t *fsp_cfg;
+	const external_irq_api_t *fsp_api;
+};
+
+struct intc_rz_ext_irq_data {
+	external_irq_ctrl_t *fsp_ctrl;
+	intc_rz_ext_irq_callback_t callback;
+	void *callback_data;
+};
+
+/* FSP interruption handlers. */
+#if defined(CONFIG_SOC_SERIES_RZG3S)
+void r_intc_irq_isr(void);
+void r_intc_nmi_isr(void);
+#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) ||                      \
+	defined(CONFIG_SOC_SERIES_RZT2M)
+void r_icu_isr(void);
+#endif /* CONFIG_SOC_SERIES_* */
+
+int intc_rz_ext_irq_enable(const struct device *dev)
+{
+	const struct intc_rz_ext_irq_config *config = dev->config;
+	struct intc_rz_ext_irq_data *data = dev->data;
+	fsp_err_t err = FSP_SUCCESS;
+
+	err = config->fsp_api->enable(data->fsp_ctrl);
+
+	if (err != FSP_SUCCESS) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+int intc_rz_ext_irq_disable(const struct device *dev)
+{
+	const struct intc_rz_ext_irq_config *config = dev->config;
+	struct intc_rz_ext_irq_data *data = dev->data;
+	fsp_err_t err = FSP_SUCCESS;
+
+	err = config->fsp_api->disable(data->fsp_ctrl);
+
+	if (err != FSP_SUCCESS) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+int intc_rz_ext_irq_set_callback(const struct device *dev, intc_rz_ext_irq_callback_t cb, void *arg)
+{
+	struct intc_rz_ext_irq_data *data = dev->data;
+
+	data->callback = cb;
+	data->callback_data = arg;
+
+	return 0;
+}
+
+int intc_rz_ext_irq_set_type(const struct device *dev, uint8_t trig)
+{
+	const struct intc_rz_ext_irq_config *config = dev->config;
+	struct intc_rz_ext_irq_data *data = dev->data;
+	fsp_err_t err = FSP_SUCCESS;
+	external_irq_cfg_t *p_cfg = (external_irq_cfg_t *)config->fsp_cfg;
+
+	p_cfg->trigger = (external_irq_trigger_t)trig;
+	err = config->fsp_api->close(data->fsp_ctrl);
+
+	if (err != FSP_SUCCESS) {
+		return -EIO;
+	}
+
+	err = config->fsp_api->open(data->fsp_ctrl, config->fsp_cfg);
+
+	if (err != FSP_SUCCESS) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int intc_rz_ext_irq_init(const struct device *dev)
+{
+	const struct intc_rz_ext_irq_config *config = dev->config;
+	struct intc_rz_ext_irq_data *data = dev->data;
+	fsp_err_t err = FSP_SUCCESS;
+	int ret = 0;
+
+	if (config->pin_config) {
+		ret = pinctrl_apply_state(config->pin_config, PINCTRL_STATE_DEFAULT);
+
+		if (ret < 0) {
+			LOG_ERR("%s: pinctrl config failed.", __func__);
+			return ret;
+		}
+	}
+
+	err = config->fsp_api->open(data->fsp_ctrl, config->fsp_cfg);
+
+	if (err != FSP_SUCCESS) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static void intc_rz_ext_irq_callback(external_irq_callback_args_t *args)
+{
+	const struct device *dev = (const struct device *)args->p_context;
+	struct intc_rz_ext_irq_data *data = dev->data;
+
+	if (data->callback) {
+		data->callback(data->callback_data);
+	}
+}
+
+#ifdef CONFIG_CPU_CORTEX_M
+#define GET_IRQ_FLAGS(index) 0
+#else /* Cortex-A/R */
+#define GET_IRQ_FLAGS(index) DT_INST_IRQ_BY_IDX(index, 0, flags)
+#endif
+
+#define EXT_IRQ_RZ_IRQ_CONNECT(index, isr, isr_nmi)                                                \
+	IRQ_CONNECT(DT_INST_IRQ_BY_IDX(index, 0, irq), DT_INST_IRQ_BY_IDX(index, 0, priority),     \
+		    COND_CODE_0(DT_INST_IRQ_BY_IDX(index, 0, irq),                                 \
+		    (isr_nmi), (isr)), NULL, GET_IRQ_FLAGS(index));
+
+#define INTC_RZG_EXT_IRQ_INIT(index)                                                               \
+	static const external_irq_cfg_t g_external_irq##index##_cfg = {                            \
+		.trigger = DT_INST_ENUM_IDX_OR(index, trigger_type, 0),                            \
+		.filter_enable = true,                                                             \
+		.clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_1,                               \
+		.p_callback = intc_rz_ext_irq_callback,                                            \
+		.p_context = DEVICE_DT_INST_GET(index),                                            \
+		.p_extend = NULL,                                                                  \
+		.ipl = DT_INST_IRQ_BY_IDX(index, 0, priority),                                     \
+		.irq = DT_INST_IRQ_BY_IDX(index, 0, irq),                                          \
+		COND_CODE_0(DT_INST_IRQ_BY_IDX(index, 0, irq),                   \
+			(.channel = DT_INST_IRQ_BY_IDX(index, 0, irq)),          \
+			(.channel = DT_INST_IRQ_BY_IDX(index, 0, irq) - 1)),     \
+	};                                                                                         \
+                                                                                                   \
+	PINCTRL_DT_INST_DEFINE(index);                                                             \
+                                                                                                   \
+	struct intc_rz_ext_irq_config intc_rz_ext_irq_config##index = {                            \
+		.pin_config = PINCTRL_DT_INST_DEV_CONFIG_GET(index),                               \
+		.fsp_cfg = (external_irq_cfg_t *)&g_external_irq##index##_cfg,                     \
+		COND_CODE_0(DT_INST_IRQ_BY_IDX(index, 0, irq), (            \
+			.fsp_api = &g_external_irq_on_intc_nmi), (          \
+			.fsp_api = &g_external_irq_on_intc_irq)),           \
+	};                                                                                         \
+                                                                                                   \
+	COND_CODE_0(DT_INST_IRQ_BY_IDX(index, 0, irq),                                     \
+		    (static intc_nmi_instance_ctrl_t g_external_irq##index##_ctrl;),       \
+		    (static intc_irq_instance_ctrl_t g_external_irq##index##_ctrl;))       \
+                                                                                                   \
+	static struct intc_rz_ext_irq_data intc_rz_ext_irq_data##index = {                         \
+		.fsp_ctrl = (external_irq_ctrl_t *)&g_external_irq##index##_ctrl,                  \
+	};                                                                                         \
+                                                                                                   \
+	static int intc_rz_ext_irq_init_##index(const struct device *dev)                          \
+	{                                                                                          \
+		EXT_IRQ_RZ_IRQ_CONNECT(index, r_intc_irq_isr, r_intc_nmi_isr)                      \
+		return intc_rz_ext_irq_init(dev);                                                  \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(index, intc_rz_ext_irq_init_##index, NULL,                           \
+			      &intc_rz_ext_irq_data##index, &intc_rz_ext_irq_config##index,        \
+			      PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);
+
+#define INTC_RZTN_EXT_IRQ_INIT(index)                                                              \
+	static const external_irq_cfg_t g_external_irq##index##_cfg = {                            \
+		.trigger = DT_INST_ENUM_IDX_OR(index, trigger_type, 0),                            \
+		.filter_enable = true,                                                             \
+		.clock_source_div = EXTERNAL_IRQ_CLOCK_SOURCE_DIV_1,                               \
+		.p_callback = intc_rz_ext_irq_callback,                                            \
+		.p_context = DEVICE_DT_INST_GET(index),                                            \
+		.p_extend = NULL,                                                                  \
+		.ipl = DT_INST_IRQ_BY_IDX(index, 0, priority),                                     \
+		.irq = DT_INST_IRQ_BY_IDX(index, 0, irq),                                          \
+		.channel = DT_INST_REG_ADDR(index),                                                \
+	};                                                                                         \
+                                                                                                   \
+	PINCTRL_DT_INST_DEFINE(index);                                                             \
+                                                                                                   \
+	struct intc_rz_ext_irq_config intc_rz_ext_irq_config##index = {                            \
+		.pin_config = PINCTRL_DT_INST_DEV_CONFIG_GET(index),                               \
+		.fsp_cfg = (external_irq_cfg_t *)&g_external_irq##index##_cfg,                     \
+		.fsp_api = &g_external_irq_on_icu,                                                 \
+	};                                                                                         \
+                                                                                                   \
+	icu_instance_ctrl_t g_external_irq##index##_ctrl;                                          \
+                                                                                                   \
+	static struct intc_rz_ext_irq_data intc_rz_ext_irq_data##index = {                         \
+		.fsp_ctrl = (icu_instance_ctrl_t *)&g_external_irq##index##_ctrl,                  \
+	};                                                                                         \
+                                                                                                   \
+	static int intc_rz_ext_irq_init_##index(const struct device *dev)                          \
+	{                                                                                          \
+		EXT_IRQ_RZ_IRQ_CONNECT(index, r_icu_isr, NULL);                                    \
+		return intc_rz_ext_irq_init(dev);                                                  \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(index, intc_rz_ext_irq_init_##index, NULL,                           \
+			      &intc_rz_ext_irq_data##index, &intc_rz_ext_irq_config##index,        \
+			      PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);
+
+#if defined(CONFIG_SOC_SERIES_RZG3S)
+DT_INST_FOREACH_STATUS_OKAY(INTC_RZG_EXT_IRQ_INIT)
+#elif defined(CONFIG_SOC_SERIES_RZN2L) || defined(CONFIG_SOC_SERIES_RZT2L) ||                      \
+	defined(CONFIG_SOC_SERIES_RZT2M)
+DT_INST_FOREACH_STATUS_OKAY(INTC_RZTN_EXT_IRQ_INIT)
+#endif
diff --git a/drivers/interrupt_controller/intc_vim.c b/drivers/interrupt_controller/intc_vim.c
index 01d2633413d..d37aac051d1 100644
--- a/drivers/interrupt_controller/intc_vim.c
+++ b/drivers/interrupt_controller/intc_vim.c
@@ -1,5 +1,6 @@
 /* Copyright (C) 2023 BeagleBoard.org Foundation
  * Copyright (C) 2023 S Prashanth
+ * Copyright (C) 2025 Siemens Mobility GmbH
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -14,6 +15,7 @@
 #include <zephyr/drivers/interrupt_controller/intc_vim.h>
 #include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
+#include "zephyr/sys/__assert.h"
 #include <zephyr/sys/util_macro.h>
 
 LOG_MODULE_REGISTER(vim);
@@ -56,8 +58,12 @@ void z_vim_irq_eoi(unsigned int irq)
 
 void z_vim_irq_init(void)
 {
-	uint32_t num_of_irqs = sys_read32(VIM_INFO_INTERRUPTS_MASK);
+	uint32_t num_of_irqs = sys_read32(VIM_INFO) & VIM_INFO_INTERRUPTS_MASK;
 
+	__ASSERT(CONFIG_NUM_IRQS == num_of_irqs,
+		 "Number of configured interrupts (%d) doesn't match reported "
+		 "(%" PRIu32 ") interrupts",
+		 CONFIG_NUM_IRQS, num_of_irqs);
 	LOG_DBG("VIM: Number of IRQs = %u\n", num_of_irqs);
 }
 
diff --git a/drivers/interrupt_controller/wuc_ite_it51xxx.c b/drivers/interrupt_controller/wuc_ite_it51xxx.c
new file mode 100644
index 00000000000..41f3627e177
--- /dev/null
+++ b/drivers/interrupt_controller/wuc_ite_it51xxx.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ite_it51xxx_wuc
+
+#include <soc.h>
+#include <zephyr/drivers/interrupt_controller/wuc_ite_it51xxx.h>
+#include <zephyr/dt-bindings/interrupt-controller/ite-it51xxx-wuc.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/kernel.h>
+
+LOG_MODULE_REGISTER(wuc_ite_it51xxx, CONFIG_INTC_LOG_LEVEL);
+
+/* Driver config */
+struct it51xxx_wuc_cfg {
+	/* WUC wakeup edge mode register */
+	uint8_t *reg_wuemr;
+	/* WUC wakeup edge sense register */
+	uint8_t *reg_wuesr;
+	/* WUC wakeup enable register */
+	uint8_t *reg_wuenr;
+	/* WUC level or edge mode register */
+	uint8_t *reg_wuler;
+	bool wakeup_ctrl;
+	bool both_edge_trigger;
+};
+
+void it51xxx_wuc_enable(const struct device *dev, uint8_t mask)
+{
+	const struct it51xxx_wuc_cfg *config = dev->config;
+	volatile uint8_t *reg_wuenr = config->reg_wuenr;
+
+	if (!config->wakeup_ctrl) {
+		LOG_ERR("Wakeup control(enable) is not supported.");
+		return;
+	}
+	/*
+	 * WUC group only 1, 3, and 4 have enable/disable register,
+	 * others are always enabled.
+	 */
+	if (reg_wuenr == IT51XXX_WUC_UNUSED_REG) {
+		return;
+	}
+
+	/* Enable wakeup interrupt of the pin */
+	*reg_wuenr |= mask;
+}
+
+void it51xxx_wuc_disable(const struct device *dev, uint8_t mask)
+{
+	const struct it51xxx_wuc_cfg *config = dev->config;
+	volatile uint8_t *reg_wuenr = config->reg_wuenr;
+
+	if (!config->wakeup_ctrl) {
+		LOG_ERR("Wakeup control(disable) is not supported.");
+		return;
+	}
+	/*
+	 * WUC group only 1, 3, and 4 have enable/disable register,
+	 * others are always enabled.
+	 */
+	if (reg_wuenr == IT51XXX_WUC_UNUSED_REG) {
+		return;
+	}
+
+	/* Disable wakeup interrupt of the pin */
+	*reg_wuenr &= ~mask;
+}
+
+void it51xxx_wuc_clear_status(const struct device *dev, uint8_t mask)
+{
+	const struct it51xxx_wuc_cfg *config = dev->config;
+	volatile uint8_t *reg_wuesr = config->reg_wuesr;
+
+	if (!config->wakeup_ctrl) {
+		LOG_ERR("Wakeup control of clear status is not supported.");
+		return;
+	}
+
+	if (reg_wuesr == IT51XXX_WUC_UNUSED_REG) {
+		return;
+	}
+
+	/* W/C wakeup interrupt status of the pin */
+	*reg_wuesr = mask;
+}
+
+void it51xxx_wuc_set_polarity(const struct device *dev, uint8_t mask, uint32_t flags)
+{
+	const struct it51xxx_wuc_cfg *config = dev->config;
+	volatile uint8_t *reg_wuemr = config->reg_wuemr;
+	volatile uint8_t *reg_wuler = config->reg_wuler;
+	volatile uint8_t *reg_wuesr = config->reg_wuesr;
+
+	if (!config->wakeup_ctrl) {
+		LOG_ERR("Wakeup control of set polarity is not supported.");
+		return;
+	}
+
+	if (reg_wuemr == IT51XXX_WUC_UNUSED_REG) {
+		return;
+	}
+
+	if (flags & WUC_TYPE_LEVEL_TRIG) {
+		*reg_wuler |= mask;
+		if (flags & WUC_TYPE_LEVEL_HIGH) {
+			*reg_wuemr &= ~mask;
+		} else {
+			*reg_wuemr |= mask;
+		}
+	} else {
+		*reg_wuler &= ~mask;
+		if ((flags & WUC_TYPE_EDGE_BOTH) == WUC_TYPE_EDGE_RISING) {
+			/* Rising-edge trigger mode */
+			*reg_wuemr &= ~mask;
+		} else {
+			if (((flags & WUC_TYPE_EDGE_BOTH) == WUC_TYPE_EDGE_FALLING) &&
+			    config->both_edge_trigger) {
+				LOG_WRN("Group 7, 10, 12 do not support falling edge mode.");
+			}
+			if (((flags & WUC_TYPE_EDGE_BOTH) == WUC_TYPE_EDGE_BOTH) &&
+			    !config->both_edge_trigger) {
+				LOG_WRN("Both edge trigger mode only support group 7, 10, 12.\n"
+					"Not support dev = %s",
+					dev->name);
+			}
+			/* Falling-edge or both edge trigger mode */
+			*reg_wuemr |= mask;
+		}
+	}
+	/* W/C wakeup interrupt status of the pin */
+	*reg_wuesr = mask;
+}
+
+#define IT51XXX_WUC_INIT(inst)                                                                     \
+	static const struct it51xxx_wuc_cfg it51xxx_wuc_cfg_##inst = {                             \
+		.reg_wuemr = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 0),                          \
+		.reg_wuesr = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 1),                          \
+		.reg_wuenr = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 2),                          \
+		.reg_wuler = (uint8_t *)DT_INST_REG_ADDR_BY_IDX(inst, 3),                          \
+		.wakeup_ctrl = DT_INST_PROP(inst, wakeup_controller),                              \
+		.both_edge_trigger = DT_INST_PROP(inst, both_edge_trigger),                        \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(inst, NULL, NULL, NULL, &it51xxx_wuc_cfg_##inst, PRE_KERNEL_1,       \
+			      CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(IT51XXX_WUC_INIT)
diff --git a/drivers/ipm/Kconfig b/drivers/ipm/Kconfig
index 0648cdd32c8..8d7a3f3288e 100644
--- a/drivers/ipm/Kconfig
+++ b/drivers/ipm/Kconfig
@@ -59,7 +59,7 @@ config IPM_MBOX
 	bool "IPM over MBOX driver"
 	default y
 	depends on DT_HAS_ZEPHYR_MBOX_IPM_ENABLED
-	depends on MBOX
+	select MBOX
 	help
 	  IPM driver using a MBOX driver as the backend mechanism.
 
diff --git a/drivers/ipm/Kconfig.stm32 b/drivers/ipm/Kconfig.stm32
index 9fd3f60263e..456168783dd 100644
--- a/drivers/ipm/Kconfig.stm32
+++ b/drivers/ipm/Kconfig.stm32
@@ -5,7 +5,6 @@ config IPM_STM32_IPCC
 	bool "STM32 IPCC controller"
 	default y
 	depends on DT_HAS_ST_STM32_IPCC_MAILBOX_ENABLED
-	select USE_STM32_LL_IPCC
 	help
 	  Driver for stm32 IPCC mailboxes
 
diff --git a/drivers/ipm/ipm_mcux.c b/drivers/ipm/ipm_mcux.c
index ac0ad8c3b3c..8d860710c88 100644
--- a/drivers/ipm/ipm_mcux.c
+++ b/drivers/ipm/ipm_mcux.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, NXP
+ * Copyright (c) 2017-2018, 2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,8 +20,11 @@
 #define MCUX_IPM_DATA_REGS 1
 #define MCUX_IPM_MAX_ID_VAL 0
 
-#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES))
-#ifdef LPC55S69_cm33_core0_SERIES
+#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) || \
+defined(CONFIG_SOC_SERIES_MCXN))
+#if (defined(LPC55S69_cm33_core0_SERIES) || defined(MCXN947_cm33_core0_SERIES) || \
+defined(MCXN946_cm33_core0_SERIES) || defined(MCXN547_cm33_core0_SERIES) || \
+defined(MCXN546_cm33_core0_SERIES))
 #define MAILBOX_ID_THIS_CPU kMAILBOX_CM33_Core0
 #define MAILBOX_ID_OTHER_CPU kMAILBOX_CM33_Core1
 #else
diff --git a/drivers/ipm/ipm_sedi.c b/drivers/ipm/ipm_sedi.c
index a5f689556b6..7fa93ea1986 100644
--- a/drivers/ipm/ipm_sedi.c
+++ b/drivers/ipm/ipm_sedi.c
@@ -284,10 +284,10 @@ static DEVICE_API(ipm, ipm_funcs) = {
 			    DT_INST_PROP(n, peripheral_id),		\
 			    DT_INST_IRQ(n, sense));			\
 	}								\
-	PM_DEVICE_DT_DEFINE(DT_NODELABEL(ipm##n), ipm_power_ctrl);	\
+	PM_DEVICE_DT_INST_DEFINE(n, ipm_power_ctrl);			\
 	DEVICE_DT_INST_DEFINE(n,					\
 			      &ipm_init,				\
-			      PM_DEVICE_DT_GET(DT_NODELABEL(ipm##n)),   \
+			      PM_DEVICE_DT_INST_GET(n),			\
 			      &ipm_data_##n,				\
 			      &ipm_config_##n,				\
 			      POST_KERNEL,				\
diff --git a/drivers/kscan/CMakeLists.txt b/drivers/kscan/CMakeLists.txt
deleted file mode 100644
index 1108cd61629..00000000000
--- a/drivers/kscan/CMakeLists.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/kscan.h)
-
-zephyr_library()
-
-zephyr_library_sources_ifdef(CONFIG_KSCAN_INPUT		kscan_input.c)
-
-zephyr_library_sources_ifdef(CONFIG_USERSPACE	    kscan_handlers.c)
diff --git a/drivers/kscan/Kconfig b/drivers/kscan/Kconfig
deleted file mode 100644
index 0ed9acc7e06..00000000000
--- a/drivers/kscan/Kconfig
+++ /dev/null
@@ -1,26 +0,0 @@
-# Keyboard scan configuration options
-
-# Copyright (c) 2019 Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-menuconfig KSCAN
-	bool "Keyboard scan drivers [DEPRECATED]"
-	select DEPRECATED
-	help
-	  Include Keyboard scan drivers in system config.
-
-if KSCAN
-
-source "drivers/kscan/Kconfig.input"
-
-module = KSCAN
-module-str = kscan
-source "subsys/logging/Kconfig.template.log_config"
-
-config KSCAN_INIT_PRIORITY
-	int "Keyboard scan driver init priority"
-	default 90
-	help
-	  Keyboard scan device driver initialization priority.
-
-endif # KSCAN
diff --git a/drivers/kscan/Kconfig.input b/drivers/kscan/Kconfig.input
deleted file mode 100644
index 85168a9a129..00000000000
--- a/drivers/kscan/Kconfig.input
+++ /dev/null
@@ -1,8 +0,0 @@
-# Copyright 2023 Google LLC
-# SPDX-License-Identifier: Apache-2.0
-
-config KSCAN_INPUT
-	bool "Input subsystem to kscan adapter driver"
-	default y
-	depends on INPUT
-	depends on DT_HAS_ZEPHYR_KSCAN_INPUT_ENABLED
diff --git a/drivers/kscan/kscan_handlers.c b/drivers/kscan/kscan_handlers.c
deleted file mode 100644
index 81c97c19d04..00000000000
--- a/drivers/kscan/kscan_handlers.c
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2019 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/drivers/kscan.h>
-#include <zephyr/internal/syscall_handler.h>
-
-static inline int z_vrfy_kscan_config(const struct device *dev,
-				      kscan_callback_t callback_isr)
-{
-	K_OOPS(K_SYSCALL_DRIVER_KSCAN(dev, config));
-	K_OOPS(K_SYSCALL_VERIFY_MSG(callback_isr == 0,
-				    "callback cannot be set from user mode"));
-	return z_impl_kscan_config((const struct device *)dev, callback_isr);
-}
-#include <zephyr/syscalls/kscan_config_mrsh.c>
-
-static inline int z_vrfy_kscan_disable_callback(const struct device *dev)
-{
-	K_OOPS(K_SYSCALL_DRIVER_KSCAN(dev, disable_callback));
-
-	return z_impl_kscan_disable_callback((const struct device *)dev);
-}
-#include <zephyr/syscalls/kscan_disable_callback_mrsh.c>
-
-static int z_vrfy_kscan_enable_callback(const struct device *dev)
-{
-	K_OOPS(K_SYSCALL_DRIVER_KSCAN(dev, enable_callback));
-
-	return z_impl_kscan_enable_callback((const struct device *)dev);
-}
-#include <zephyr/syscalls/kscan_enable_callback_mrsh.c>
diff --git a/drivers/kscan/kscan_input.c b/drivers/kscan/kscan_input.c
deleted file mode 100644
index 52c23f21ca3..00000000000
--- a/drivers/kscan/kscan_input.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright 2023 Google LLC
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#define DT_DRV_COMPAT zephyr_kscan_input
-
-#include <zephyr/drivers/kscan.h>
-#include <zephyr/input/input.h>
-
-#include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(kscan_input, CONFIG_KSCAN_LOG_LEVEL);
-
-struct kscan_input_config {
-	const struct device *input_dev;
-};
-
-struct kscan_input_data {
-	bool enabled;
-	kscan_callback_t callback;
-	int row;
-	int col;
-	bool pressed;
-};
-
-static void kscan_input_cb(struct input_event *evt, void *user_data)
-{
-	const struct device *dev = user_data;
-	struct kscan_input_data *data = dev->data;
-
-	switch (evt->code) {
-	case INPUT_ABS_X:
-		data->col = evt->value;
-		break;
-	case INPUT_ABS_Y:
-		data->row = evt->value;
-		break;
-	case INPUT_BTN_TOUCH:
-		data->pressed = evt->value;
-		break;
-	}
-
-	if (evt->sync) {
-		LOG_DBG("input event: %3d %3d %d",
-			data->row, data->col, data->pressed);
-		if (data->callback) {
-			data->callback(dev, data->row, data->col, data->pressed);
-		}
-	}
-}
-
-static int kscan_input_configure(const struct device *dev,
-				      kscan_callback_t callback)
-{
-	struct kscan_input_data *data = dev->data;
-
-	if (!callback) {
-		LOG_ERR("Invalid callback (NULL)");
-		return -EINVAL;
-	}
-
-	data->callback = callback;
-
-	return 0;
-}
-
-static int kscan_input_enable_callback(const struct device *dev)
-{
-	struct kscan_input_data *data = dev->data;
-
-	data->enabled = true;
-
-	return 0;
-}
-
-static int kscan_input_disable_callback(const struct device *dev)
-{
-	struct kscan_input_data *data = dev->data;
-
-	data->enabled = false;
-
-	return 0;
-}
-
-static int kscan_input_init(const struct device *dev)
-{
-	const struct kscan_input_config *cfg = dev->config;
-
-	if (!device_is_ready(cfg->input_dev)) {
-		LOG_ERR("Input device not ready");
-		return -ENODEV;
-	}
-
-	return 0;
-}
-
-static DEVICE_API(kscan, kscan_input_driver_api) = {
-	.config = kscan_input_configure,
-	.enable_callback = kscan_input_enable_callback,
-	.disable_callback = kscan_input_disable_callback,
-};
-
-#define KSCAN_INPUT_INIT(index) \
-	INPUT_CALLBACK_DEFINE_NAMED(DEVICE_DT_GET(DT_INST_PARENT(index)),      \
-				    kscan_input_cb,                            \
-				    (void *)DEVICE_DT_INST_GET(index),         \
-				    kscan_input_cb_##index);                   \
-	static const struct kscan_input_config kscan_input_config_##index = {  \
-		.input_dev = DEVICE_DT_GET(DT_INST_PARENT(index)),             \
-	};                                                                     \
-	static struct kscan_input_data kscan_input_data_##index;               \
-	DEVICE_DT_INST_DEFINE(index, kscan_input_init, NULL,                   \
-			      &kscan_input_data_##index,                       \
-			      &kscan_input_config_##index,                     \
-			      POST_KERNEL, CONFIG_KSCAN_INIT_PRIORITY,         \
-			      &kscan_input_driver_api);
-
-DT_INST_FOREACH_STATUS_OKAY(KSCAN_INPUT_INIT)
diff --git a/drivers/led/CMakeLists.txt b/drivers/led/CMakeLists.txt
index 09ea5e202fd..1ba04d22cea 100644
--- a/drivers/led/CMakeLists.txt
+++ b/drivers/led/CMakeLists.txt
@@ -4,8 +4,12 @@ zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/led.h)
 
 zephyr_library()
 
+# zephyr-keep-sorted-start
 zephyr_library_sources_ifdef(CONFIG_HT16K33 ht16k33.c)
+zephyr_library_sources_ifdef(CONFIG_IS31FL3194 is31fl3194.c)
 zephyr_library_sources_ifdef(CONFIG_IS31FL3216A is31fl3216a.c)
+zephyr_library_sources_ifdef(CONFIG_IS31FL3733 is31fl3733.c)
+zephyr_library_sources_ifdef(CONFIG_LED_AXP192_AXP2101 led_axp192.c)
 zephyr_library_sources_ifdef(CONFIG_LED_GPIO led_gpio.c)
 zephyr_library_sources_ifdef(CONFIG_LED_NPM1300 led_npm1300.c)
 zephyr_library_sources_ifdef(CONFIG_LED_PWM led_pwm.c)
@@ -17,8 +21,7 @@ zephyr_library_sources_ifdef(CONFIG_LP5569 lp5569.c)
 zephyr_library_sources_ifdef(CONFIG_NCP5623 ncp5623.c)
 zephyr_library_sources_ifdef(CONFIG_PCA9633 pca9633.c)
 zephyr_library_sources_ifdef(CONFIG_TLC59108 tlc59108.c)
-zephyr_library_sources_ifdef(CONFIG_IS31FL3733 is31fl3733.c)
-zephyr_library_sources_ifdef(CONFIG_IS31FL3194 is31fl3194.c)
+# zephyr-keep-sorted-stop
 
 zephyr_library_sources_ifdef(CONFIG_LED_SHELL   led_shell.c)
 
diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig
index 26bf49cd5e2..fa0628f112c 100644
--- a/drivers/led/Kconfig
+++ b/drivers/led/Kconfig
@@ -26,9 +26,13 @@ config LED_SHELL
 	help
 	  Enable LED shell for testing.
 
+# zephyr-keep-sorted-start
+source "drivers/led/Kconfig.axp192"
 source "drivers/led/Kconfig.gpio"
 source "drivers/led/Kconfig.ht16k33"
+source "drivers/led/Kconfig.is31fl3194"
 source "drivers/led/Kconfig.is31fl3216a"
+source "drivers/led/Kconfig.is31fl3733"
 source "drivers/led/Kconfig.lp3943"
 source "drivers/led/Kconfig.lp50xx"
 source "drivers/led/Kconfig.lp5562"
@@ -39,7 +43,6 @@ source "drivers/led/Kconfig.pca9633"
 source "drivers/led/Kconfig.pwm"
 source "drivers/led/Kconfig.tlc59108"
 source "drivers/led/Kconfig.xec"
-source "drivers/led/Kconfig.is31fl3733"
-source "drivers/led/Kconfig.is31fl3194"
+# zephyr-keep-sorted-stop
 
 endif # LED
diff --git a/drivers/led/Kconfig.axp192 b/drivers/led/Kconfig.axp192
new file mode 100644
index 00000000000..d747a773840
--- /dev/null
+++ b/drivers/led/Kconfig.axp192
@@ -0,0 +1,17 @@
+# Copyright (c) 2024 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+config LED_AXP192_AXP2101
+	bool "X-Powers AXP192/AXP2101 LED driver"
+	default y
+	depends on DT_HAS_X_POWERS_AXP192_LED_ENABLED || DT_HAS_X_POWERS_AXP2101_LED_ENABLED
+	depends on DT_HAS_X_POWERS_AXP192_ENABLED || DT_HAS_X_POWERS_AXP2101_ENABLED
+	select I2C
+	select MFD
+	help
+	  Enable the AXP192/AXP2101 LED driver.
+
+	  AXP192 and AXP2101 are multi-functional integrated Power Management IC (PMIC).
+	  This driver is for its LED controller feature.
+	  This LED controller can control the lighting using a register,
+	  and can also light up in response to the charging status.
diff --git a/drivers/led/Kconfig.gpio b/drivers/led/Kconfig.gpio
index 7288daae29e..ce4bfffe0d3 100644
--- a/drivers/led/Kconfig.gpio
+++ b/drivers/led/Kconfig.gpio
@@ -4,6 +4,7 @@
 config LED_GPIO
 	bool "GPIO LED driver"
 	default y
-	depends on GPIO && DT_HAS_GPIO_LEDS_ENABLED
+	depends on DT_HAS_GPIO_LEDS_ENABLED
+	select GPIO
 	help
 	  Enable driver for GPIO LEDs.
diff --git a/drivers/led/led_axp192.c b/drivers/led/led_axp192.c
new file mode 100644
index 00000000000..3e312d6a1cc
--- /dev/null
+++ b/drivers/led/led_axp192.c
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2024 TOKITA Hiroshi
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/led.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(led_axp192, CONFIG_LED_LOG_LEVEL);
+
+#define CHGLED_OUTPUT_HIZ        0x0
+#define CHGLED_OUTPUT_SLOW_BLINK 0x1
+#define CHGLED_OUTPUT_FAST_BLINK 0x2
+#define CHGLED_OUTPUT_DRIVE_LOW  0x3
+
+#define CHGLED_OUTPUT_OFFSET 4
+
+#define CHGLED_ON          (CHGLED_OUTPUT_DRIVE_LOW << CHGLED_OUTPUT_OFFSET)
+#define CHGLED_OFF         (CHGLED_OUTPUT_HIZ << CHGLED_OUTPUT_OFFSET)
+#define CHGLED_BLINK_SLOW  (CHGLED_OUTPUT_SLOW_BLINK << CHGLED_OUTPUT_OFFSET)
+#define CHGLED_BLINK_FAST  (CHGLED_OUTPUT_FAST_BLINK << CHGLED_OUTPUT_OFFSET)
+#define CHGLED_OUTPUT_MASK (BIT_MASK(2) << CHGLED_OUTPUT_OFFSET)
+
+#define SLOW_BLINK_DELAY_ON  (((1000 / 4) / 1) * 1)
+#define SLOW_BLINK_DELAY_OFF (((1000 / 4) / 1) * 3)
+#define FAST_BLINK_DELAY_ON  (((1000 / 4) / 4) * 1)
+#define FAST_BLINK_DELAY_OFF (((1000 / 4) / 4) * 3)
+
+#define CHGLED_CTRL_TYPE_A    0x0
+#define CHGLED_CTRL_TYPE_B    0x1
+#define CHGLED_CTRL_BY_REG    0x2
+#define CHGLED_CTRL_BY_CHARGE 0x3
+
+#define AXP192_REG_PWROFF_BATTCHK_CHGLED 0x32
+#define AXP192_REG_CHGLED                AXP192_REG_PWROFF_BATTCHK_CHGLED
+#define AXP192_CHGLED_CTRL_MASK          0x2
+#define AXP192_CHGLED_CTRL_OFFSET        2
+
+#define AXP2101_REG_CHGLED         0x69
+#define AXP2101_CHGLED_CTRL_MASK   0x3
+#define AXP2101_CHGLED_CTRL_OFFSET 1
+
+struct led_axp192_config {
+	struct i2c_dt_spec i2c;
+	uint8_t addr;
+	uint8_t mode;
+	uint8_t mode_mask;
+	uint8_t mode_offset;
+};
+
+static int led_axp192_on(const struct device *dev, uint32_t led)
+{
+	const struct led_axp192_config *config = dev->config;
+
+	ARG_UNUSED(led);
+
+	if (config->mode != CHGLED_CTRL_BY_REG) {
+		return -EINVAL;
+	}
+
+	return i2c_reg_update_byte_dt(&config->i2c, config->addr, CHGLED_OUTPUT_MASK, CHGLED_ON);
+}
+
+static int led_axp192_off(const struct device *dev, uint32_t led)
+{
+	const struct led_axp192_config *config = dev->config;
+
+	ARG_UNUSED(led);
+
+	if (config->mode != CHGLED_CTRL_BY_REG) {
+		return -EINVAL;
+	}
+
+	return i2c_reg_update_byte_dt(&config->i2c, config->addr, CHGLED_OUTPUT_MASK, CHGLED_OFF);
+}
+
+static int led_axp192_blink(const struct device *dev, uint32_t led, uint32_t delay_on,
+			    uint32_t delay_off)
+{
+	const struct led_axp192_config *config = dev->config;
+
+	ARG_UNUSED(led);
+
+	if (config->mode != CHGLED_CTRL_BY_REG) {
+		return -EINVAL;
+	}
+
+	if ((delay_on == SLOW_BLINK_DELAY_ON) && (delay_off == SLOW_BLINK_DELAY_OFF)) {
+		return i2c_reg_update_byte_dt(&config->i2c, config->addr, CHGLED_OUTPUT_MASK,
+					      CHGLED_BLINK_SLOW);
+	} else if ((delay_on == FAST_BLINK_DELAY_ON) && (delay_off == FAST_BLINK_DELAY_OFF)) {
+		return i2c_reg_update_byte_dt(&config->i2c, config->addr, CHGLED_OUTPUT_MASK,
+					      CHGLED_BLINK_FAST);
+	} else {
+		LOG_ERR("The AXP192 blink setting can only %d/%d or %d/%d. (%d/%d)",
+			SLOW_BLINK_DELAY_ON, SLOW_BLINK_DELAY_OFF, FAST_BLINK_DELAY_ON,
+			FAST_BLINK_DELAY_OFF, delay_on, delay_off);
+	}
+
+	return -ENOTSUP;
+}
+
+static DEVICE_API(led, led_axp192_api) = {
+	.on = led_axp192_on,
+	.off = led_axp192_off,
+	.blink = led_axp192_blink,
+};
+
+static int led_axp192_init(const struct device *dev)
+{
+	const struct led_axp192_config *config = dev->config;
+
+	switch (config->mode) {
+	case CHGLED_CTRL_TYPE_A:
+	case CHGLED_CTRL_TYPE_B:
+	case CHGLED_CTRL_BY_REG:
+	case CHGLED_CTRL_BY_CHARGE:
+		return i2c_reg_update_byte_dt(&config->i2c, config->addr,
+					      config->mode_mask << config->mode_offset,
+					      config->mode << config->mode_offset);
+	}
+
+	return -EINVAL;
+}
+
+#define LED_AXPXXXX_DEFINE(n, model, compat)                                                       \
+	static const struct led_axp192_config led_axp_config_##model##_##n = {                     \
+		.i2c = I2C_DT_SPEC_GET(DT_PARENT(n)),                                              \
+		.addr = AXP##model##_REG_CHGLED,                                                   \
+		.mode = UTIL_CAT(CHGLED_CTRL_, DT_STRING_UPPER_TOKEN(n, x_powers_mode)),           \
+		.mode_mask = AXP##model##_CHGLED_CTRL_MASK,                                        \
+		.mode_offset = AXP##model##_CHGLED_CTRL_OFFSET,                                    \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_DEFINE(n, led_axp192_init, NULL, NULL, &led_axp_config_##model##_##n,            \
+			 POST_KERNEL, CONFIG_LED_INIT_PRIORITY, &led_axp192_api);
+
+#define LED_AXP192_DEFINE(n)  LED_AXPXXXX_DEFINE(n, 192, x_powers_axp192_led)
+#define LED_AXP2101_DEFINE(n) LED_AXPXXXX_DEFINE(n, 2101, x_powers_axp2101_led)
+
+DT_FOREACH_STATUS_OKAY(x_powers_axp192_led, LED_AXP192_DEFINE)
+DT_FOREACH_STATUS_OKAY(x_powers_axp2101_led, LED_AXP2101_DEFINE)
diff --git a/drivers/led/led_shell.c b/drivers/led/led_shell.c
index eda7fd27eae..65db93c6756 100644
--- a/drivers/led/led_shell.c
+++ b/drivers/led/led_shell.c
@@ -330,14 +330,14 @@ cmd_write_channels(const struct shell *sh, size_t argc, char **argv)
 	return err;
 }
 
-static bool device_is_led_and_ready(const struct device *dev)
+static bool device_is_led(const struct device *dev)
 {
-	return device_is_ready(dev) && DEVICE_API_IS(led, dev);
+	return DEVICE_API_IS(led, dev);
 }
 
 static void device_name_get(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_filter(idx, device_is_led_and_ready);
+	const struct device *dev = shell_device_filter(idx, device_is_led);
 
 	entry->syntax = (dev != NULL) ? dev->name : NULL;
 	entry->handler = NULL;
diff --git a/drivers/led/lp50xx.c b/drivers/led/lp50xx.c
index 57ffb1db3b0..bd1fd11b529 100644
--- a/drivers/led/lp50xx.c
+++ b/drivers/led/lp50xx.c
@@ -153,7 +153,8 @@ static int lp50xx_set_color(const struct device *dev, uint32_t led,
 {
 	const struct lp50xx_config *config = dev->config;
 	const struct led_info *led_info = lp50xx_led_to_info(config, led);
-	uint8_t buf[4];
+	uint8_t buf[LP50XX_COLORS_PER_LED + 1];
+	uint8_t i;
 
 	if (!led_info) {
 		return -ENODEV;
@@ -170,11 +171,11 @@ static int lp50xx_set_color(const struct device *dev, uint32_t led,
 	buf[0] = LP50XX_OUT0_COLOR(config->num_modules);
 	buf[0] += LP50XX_COLORS_PER_LED * led_info->index;
 
-	buf[1] = color[0];
-	buf[2] = color[1];
-	buf[3] = color[2];
+	for (i = 0; i < led_info->num_colors; i++) {
+		buf[1 + i] = color[i];
+	}
 
-	return i2c_write_dt(&config->bus, buf, sizeof(buf));
+	return i2c_write_dt(&config->bus, buf, led_info->num_colors + 1);
 }
 
 static int lp50xx_write_channels(const struct device *dev,
@@ -266,6 +267,7 @@ static int lp50xx_enable(const struct device *dev, bool enable)
 static int lp50xx_init(const struct device *dev)
 {
 	const struct lp50xx_config *config = dev->config;
+	uint8_t led;
 	int err;
 
 	if (!i2c_is_ready_dt(&config->bus)) {
@@ -273,6 +275,7 @@ static int lp50xx_init(const struct device *dev)
 		return -ENODEV;
 	}
 
+	/* Check LED configuration found in DT */
 	if (config->num_leds > config->max_leds) {
 		LOG_ERR("%s: invalid number of LEDs %d (max %d)",
 			dev->name,
@@ -280,6 +283,16 @@ static int lp50xx_init(const struct device *dev)
 			config->max_leds);
 		return -EINVAL;
 	}
+	for (led = 0; led < config->num_leds; led++) {
+		const struct led_info *led_info =
+			lp50xx_led_to_info(config, led);
+
+		if (led_info->num_colors > LP50XX_COLORS_PER_LED) {
+			LOG_ERR("%s: LED %d: invalid number of colors (max %d)",
+				dev->name, led, LP50XX_COLORS_PER_LED);
+			return -EINVAL;
+		}
+	}
 
 	/* Configure GPIO if present */
 	if (config->gpio_enable.port != NULL) {
diff --git a/drivers/led_strip/Kconfig.ws2812 b/drivers/led_strip/Kconfig.ws2812
index c9125b06d3e..eb6cec6732a 100644
--- a/drivers/led_strip/Kconfig.ws2812
+++ b/drivers/led_strip/Kconfig.ws2812
@@ -99,4 +99,4 @@ config WS2812_STRIP_RPI_PICO_PIO
 	select PICOSDK_USE_PIO
 	help
 	  Enable driver for WS2812 (and compatibles) LED strip using
-	  the RaspberryPi Pico's PIO.
+	  the Raspberry Pi Pico's PIO.
diff --git a/drivers/led_strip/apa102.c b/drivers/led_strip/apa102.c
index 1ba14af8b51..f0df75241d6 100644
--- a/drivers/led_strip/apa102.c
+++ b/drivers/led_strip/apa102.c
@@ -15,13 +15,15 @@
 struct apa102_config {
 	struct spi_dt_spec bus;
 	size_t length;
+	uint8_t *const end_frame;
+	const size_t end_frame_size;
 };
 
 static int apa102_update(const struct device *dev, void *buf, size_t size)
 {
 	const struct apa102_config *config = dev->config;
 	static const uint8_t zeros[] = { 0, 0, 0, 0 };
-	static const uint8_t ones[] = { 0xFF, 0xFF, 0xFF, 0xFF };
+
 	const struct spi_buf tx_bufs[] = {
 		{
 			/* Start frame: at least 32 zeros */
@@ -38,8 +40,8 @@ static int apa102_update(const struct device *dev, void *buf, size_t size)
 			 * remaining bits to the LEDs at the end of
 			 * the strip.
 			 */
-			.buf = (uint8_t *)ones,
-			.len = sizeof(ones),
+			.buf = (uint8_t *)config->end_frame,
+			.len = config->end_frame_size,
 		},
 	};
 	const struct spi_buf_set tx = {
@@ -89,6 +91,8 @@ static int apa102_init(const struct device *dev)
 		return -ENODEV;
 	}
 
+	memset(config->end_frame, 0xFF, config->end_frame_size);
+
 	return 0;
 }
 
@@ -97,13 +101,26 @@ static DEVICE_API(led_strip, apa102_api) = {
 	.length = apa102_length,
 };
 
+/*
+ * The "End frame" is statically allocated, as a sequence of 0xFF bytes
+ * The only function of the “End frame” is to supply more clock pulses
+ * to the string until the data has permeated to the last LED. The
+ * number of clock pulses required is exactly half the total number
+ * of LEDs in the string. See below `end_frame`.
+ */
 #define APA102_DEVICE(idx)						 \
+	static uint8_t apa102_end_frame_##idx				 \
+		[(DT_INST_PROP(idx, chain_length) /			 \
+			sizeof(struct led_rgb) / 2) + 1];		 \
 	static const struct apa102_config apa102_##idx##_config = {	 \
 		.bus = SPI_DT_SPEC_INST_GET(				 \
 			idx,						 \
 			SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8), \
 			0),						 \
 		.length = DT_INST_PROP(idx, chain_length),		 \
+		.end_frame = apa102_end_frame_##idx,			 \
+		.end_frame_size = (DT_INST_PROP(idx, chain_length) /	 \
+				sizeof(struct led_rgb) / 2) + 1,	 \
 	};								 \
 									 \
 	DEVICE_DT_INST_DEFINE(idx,					 \
diff --git a/drivers/lora/rylrxxx.c b/drivers/lora/rylrxxx.c
index 6ed47d4c90e..7dd4d21a8c1 100644
--- a/drivers/lora/rylrxxx.c
+++ b/drivers/lora/rylrxxx.c
@@ -335,7 +335,7 @@ static int rylr_config(const struct device *dev, struct lora_modem_config *confi
 	}
 
 	if (RYLR_IS_ASYNC_OP_PENDING(data->pending_async_flags)) {
-		LOG_ERR("pending async opperation");
+		LOG_ERR("pending async operation");
 		err = -EBUSY;
 		goto exit;
 	}
@@ -379,7 +379,7 @@ int rylr_send(const struct device *dev, uint8_t *payload, uint32_t payload_len)
 	}
 
 	if (RYLR_IS_ASYNC_OP_PENDING(data->pending_async_flags)) {
-		LOG_ERR("pending async opperation");
+		LOG_ERR("pending async operation");
 		err = -EBUSY;
 		goto exit;
 	}
@@ -423,7 +423,7 @@ int rylr_send_async(const struct device *dev, uint8_t *payload, uint32_t payload
 	}
 
 	if (RYLR_IS_ASYNC_OP_PENDING(data->pending_async_flags)) {
-		LOG_ERR("pending async opperation");
+		LOG_ERR("pending async operation");
 		err = -EBUSY;
 		goto bail;
 	}
@@ -484,7 +484,7 @@ int rylr_recv(const struct device *dev, uint8_t *ret_msg, uint8_t size, k_timeou
 	}
 
 	if (RYLR_IS_ASYNC_OP_PENDING(data->pending_async_flags)) {
-		LOG_ERR("pending async opperation");
+		LOG_ERR("pending async operation");
 		ret = -EBUSY;
 		goto exit;
 	}
@@ -542,7 +542,7 @@ int rylr_recv_async(const struct device *dev, lora_recv_cb cb, void *user_data)
 	data->async_rx_cb = cb;
 	data->async_user_data = user_data;
 	if (RYLR_IS_ASYNC_OP_PENDING(data->pending_async_flags)) {
-		LOG_ERR("pending async opperation");
+		LOG_ERR("pending async operation");
 		err = -EBUSY;
 		goto bail;
 	}
diff --git a/drivers/mbox/CMakeLists.txt b/drivers/mbox/CMakeLists.txt
index 1a862e6375a..5e4f61b9d03 100644
--- a/drivers/mbox/CMakeLists.txt
+++ b/drivers/mbox/CMakeLists.txt
@@ -19,3 +19,6 @@ zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_BELLBOARD_RX mbox_nrf_bellboard_rx.
 zephyr_library_sources_ifdef(CONFIG_MBOX_NRF_BELLBOARD_TX mbox_nrf_bellboard_tx.c)
 zephyr_library_sources_ifdef(CONFIG_MBOX_STM32_HSEM   mbox_stm32_hsem.c)
 zephyr_library_sources_ifdef(CONFIG_MBOX_IVSHMEM mbox_ivshmem.c)
+zephyr_library_sources_ifdef(CONFIG_MBOX_TI_OMAP_MAILBOX   mbox_ti_omap.c)
+zephyr_library_sources_ifdef(CONFIG_MBOX_RENESAS_RZ_MHU mbox_renesas_rz_mhu.c)
+zephyr_library_sources_ifdef(CONFIG_MBOX_MHUV3   mbox_mhuv3.c)
diff --git a/drivers/mbox/Kconfig b/drivers/mbox/Kconfig
index 66029780128..fe456b0b89e 100644
--- a/drivers/mbox/Kconfig
+++ b/drivers/mbox/Kconfig
@@ -23,6 +23,10 @@ source "drivers/mbox/Kconfig.nrf_bellboard"
 source "drivers/mbox/Kconfig.stm32_hsem"
 source "drivers/mbox/Kconfig.esp32"
 source "drivers/mbox/Kconfig.ivshmem"
+source "drivers/mbox/Kconfig.ti_omap"
+source "drivers/mbox/Kconfig.renesas_rz"
+source "drivers/mbox/Kconfig.mhuv3"
+
 
 config MBOX_INIT_PRIORITY
 	int "MBOX init priority"
diff --git a/drivers/mbox/Kconfig.mhuv3 b/drivers/mbox/Kconfig.mhuv3
new file mode 100644
index 00000000000..6e28dae1f2f
--- /dev/null
+++ b/drivers/mbox/Kconfig.mhuv3
@@ -0,0 +1,27 @@
+#
+# SPDX-FileCopyrightText: <text>Copyright 2024-2025 Arm Limited and/or its
+# affiliates <open-source-office@arm.com></text>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config MBOX_MHUV3
+	bool "ARM MHUv3 mailbox driver"
+	depends on DT_HAS_ARM_MHUV3_ENABLED
+	default y
+	help
+	  Driver for Arm MHUv3 (Message Handling Unit v3)
+
+if MBOX_MHUV3
+
+config MBOX_MHUV3_NUM_DBCH
+	int "ARM MHUv3 mailbox doorbell number of channels"
+	default 0
+	help
+	  Maximum number of doorbell channels allowed in the Postbox/Mailbox.
+	  This number has to be less than or equal to (NUM_DBCH + 1) in PBX_DBCH_CFG0/MBX_DBCH_CFG0 registers.
+	  If the doorbell extension is supported then this number has to be bigger than zero.
+	  MHUv3 allows up to 128 doorbell channels.
+	  This configuration parameter is needed to avoid the dynamic memory allocation of doorbell channels
+	  data structures.
+
+endif
diff --git a/drivers/mbox/Kconfig.nrf_vevif_event b/drivers/mbox/Kconfig.nrf_vevif_event
index 94a9658d9a9..655cc82f385 100644
--- a/drivers/mbox/Kconfig.nrf_vevif_event
+++ b/drivers/mbox/Kconfig.nrf_vevif_event
@@ -17,4 +17,5 @@ config MBOX_NRF_VEVIF_EVENT_TX
 
 config MBOX_NRF_VEVIF_EVENT_USE_54L_ERRATA_16
 	bool "Apply errata 16 for nRF54L series"
-	default y if SOC_SERIES_NRF54LX
+	depends on SOC_SERIES_NRF54LX
+	default y
diff --git a/drivers/mbox/Kconfig.renesas_rz b/drivers/mbox/Kconfig.renesas_rz
new file mode 100644
index 00000000000..0f58505945c
--- /dev/null
+++ b/drivers/mbox/Kconfig.renesas_rz
@@ -0,0 +1,24 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config MBOX_RENESAS_RZ_MHU
+	bool "Renesas RZ MHU Driver"
+	default y
+	depends on DT_HAS_RENESAS_RZ_MHU_MBOX_ENABLED
+	select USE_RZ_FSP_MHU
+	help
+	  Enable the RZ MHU driver.
+
+if MBOX_RENESAS_RZ_MHU
+
+config MBOX_BUSY_WAIT_TIMEOUT_US
+	int "MBOX send api timeout in microseconds"
+	default 10
+	help
+	  This option specifies the timeout duration for the `mbox_send` API to busy-wait for the
+	  remote processor to consume the previous message before sending a new one. If the
+	  message is not consumed within this time, `mbox_send` will return an error.
+	  Setting this value to 0 or a negative number will cause `mbox_send` to wait indefinitely
+	  until the previous message is consumed before sending a new one.
+
+endif
diff --git a/drivers/mbox/Kconfig.ti_omap b/drivers/mbox/Kconfig.ti_omap
new file mode 100644
index 00000000000..8cc040ea521
--- /dev/null
+++ b/drivers/mbox/Kconfig.ti_omap
@@ -0,0 +1,9 @@
+# Copyright 2024 Texas Instruments Incorporated.
+# SPDX-License-Identifier: Apache-2.0
+
+config MBOX_TI_OMAP_MAILBOX
+	bool "TI OMAP Mailbox driver"
+	default y
+	depends on DT_HAS_TI_OMAP_MAILBOX_ENABLED
+	help
+	  Driver for TI OMAP Mailbox.
diff --git a/drivers/mbox/mbox_mhuv3.c b/drivers/mbox/mbox_mhuv3.c
new file mode 100644
index 00000000000..b32a4129398
--- /dev/null
+++ b/drivers/mbox/mbox_mhuv3.c
@@ -0,0 +1,1563 @@
+/*
+ * SPDX-FileCopyrightText: <text>Copyright 2024-2025 Arm Limited and/or its
+ * affiliates <open-source-office@arm.com></text>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT	arm_mhuv3
+
+#include <zephyr/drivers/mbox.h>
+
+#include <zephyr/irq.h>
+#include <zephyr/kernel.h>
+
+#define LOG_LEVEL	CONFIG_MBOX_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(mbox_mhuv3);
+
+/* ====== MHUv3 Registers ====== */
+
+/* Maximum number of Doorbell channel windows */
+#define MHUV3_DBCW_MAX		      128
+/* Number of DBCH combined interrupt status registers */
+#define MHUV3_DBCH_CMB_INT_ST_REG_CNT 4
+
+/* Number of FFCH combined interrupt status registers */
+#define MHUV3_FFCH_CMB_INT_ST_REG_CNT 2
+
+#define MHUV3_FLAG_BITS		      32
+
+#define MHUV3_MAJOR_VERSION	      2
+
+/* Postbox/Mailbox Block Identifier */
+#define BLK_ID_BLK_ID		   GENMASK(3, 0)
+/* Postbox/Mailbox Feature Support 0 */
+#define FEAT_SPT0_DBE_SPT	   GENMASK(3, 0)
+#define FEAT_SPT0_FE_SPT	   GENMASK(7, 4)
+#define FEAT_SPT0_FCE_SPT	   GENMASK(11, 8)
+/* Postbox/Mailbox Feature Support 1 */
+#define FEAT_SPT1_AUTO_OP_SPT      GENMASK(3, 0)
+/* Postbox/Mailbox Doorbell Channel Configuration 0 */
+#define DBCH_CFG0_NUM_DBCH	   GENMASK(7, 0)
+/* Postbox/Mailbox FIFO Channel Configuration 0 */
+#define FFCH_CFG0_NUM_FFCH	   GENMASK(7, 0)
+#define FFCH_CFG0_P8BA_SPT	   BIT(8)
+#define FFCH_CFG0_P16BA_SPT	   BIT(9)
+#define FFCH_CFG0_P32BA_SPT	   BIT(10)
+#define FFCH_CFG0_P64BA_SPT	   BIT(11)
+#define FFCH_CFG0_FFCH_DEPTH	   GENMASK(25, 16)
+/* Postbox/Mailbox Fast Channel Configuration 0 */
+#define FCH_CFG0_NUM_FCH	   GENMASK(9, 0)
+#define FCH_CFG0_FCGI_SPT	   BIT(10)	/* MBX-only */
+#define FCH_CFG0_NUM_FCG	   GENMASK(15, 11)
+#define FCH_CFG0_NUM_FCH_PER_FCG   GENMASK(20, 16)
+#define FCH_CFG0_FCH_WS		   GENMASK(28, 21)
+/* Postbox/Mailbox Control */
+#define CTRL_OP_REQ		   BIT(0)
+#define	CTRL_CH_OP_MSK		   BIT(1)
+/* Mailbox Fast Channel Control */
+#define FCH_CTRL_INT_EN		   BIT(2)
+/* Postbox/Mailbox Implementer Identification Register */
+#define IIDR_IMPLEMENTER	   GENMASK(11, 0)
+#define IIDR_REVISION		   GENMASK(15, 12)
+#define IIDR_VARIANT		   GENMASK(19, 16)
+#define IIDR_PRODUCT_ID		   GENMASK(31, 20)
+/* Postbox/Mailbox Architecture Identification Register */
+#define AIDR_ARCH_MINOR_REV	   GENMASK(3, 0)
+#define AIDR_ARCH_MAJOR_REV	   GENMASK(7, 4)
+/* Postbox/Mailbox Doorbell/FIFO/Fast Channel Control */
+#define XBCW_CTRL_COMB_EN	   BIT(0)
+/* Postbox Doorbell Interrupt Status/Clear/Enable */
+#define PDBCW_INT_TFR_ACK	   BIT(0)
+
+/* Padding bitfields/fields represents hole in the regs MMIO */
+
+/* CTRL_Page */
+struct ctrl_page {
+	uint32_t blk_id;
+	uint8_t reserved0[12];
+	uint32_t feat_spt0;
+	uint32_t feat_spt1;
+	uint8_t reserved1[8];
+	uint32_t dbch_cfg0;
+	uint8_t reserved2[12];
+	uint32_t ffch_cfg0;
+	uint8_t reserved3[12];
+	uint32_t fch_cfg0;
+	uint8_t reserved4[188];
+	uint32_t x_ctrl;
+	/*-- MBX-only registers --*/
+	uint8_t reserved5[60];
+	uint32_t fch_ctrl;
+	uint32_t fcg_int_en;
+	uint8_t reserved6[696];
+	/*-- End of MBX-only ---- */
+	uint32_t dbch_int_st[MHUV3_DBCH_CMB_INT_ST_REG_CNT];
+	uint32_t ffch_int_st[MHUV3_FFCH_CMB_INT_ST_REG_CNT];
+	/*-- MBX-only registers --*/
+	uint8_t reserved7[88];
+	uint32_t fcg_int_st;
+	uint8_t reserved8[12];
+	uint32_t fcg_grp_int_st[32];
+	uint8_t reserved9[2760];
+	/*-- End of MBX-only ---- */
+	uint32_t iidr;
+	uint32_t aidr;
+	uint32_t imp_def_id[12];
+} __packed;
+
+/* DBCW_Page */
+struct pdbcw_page {
+	uint32_t st;
+	uint8_t reserved0[8];
+	uint32_t set;
+	uint32_t int_st;
+	uint32_t int_clr;
+	uint32_t int_en;
+	uint32_t ctrl;
+} __packed;
+
+struct mdbcw_page {
+	uint32_t st;
+	uint32_t st_msk;
+	uint32_t clr;
+	uint8_t reserved0[4];
+	uint32_t msk_st;
+	uint32_t msk_set;
+	uint32_t msk_clr;
+	uint32_t ctrl;
+} __packed;
+
+struct dummy_page {
+	uint8_t reserved0[KB(4)];
+} __packed;
+
+struct mhuv3_pbx_frame_reg {
+	struct ctrl_page ctrl;
+	struct pdbcw_page dbcw[MHUV3_DBCW_MAX];
+	struct dummy_page ffcw;
+	struct dummy_page fcw;
+	uint8_t reserved0[KB(4) * 11];
+	struct dummy_page impdef;
+} __packed;
+
+struct mhuv3_mbx_frame_reg {
+	struct ctrl_page ctrl;
+	struct mdbcw_page dbcw[MHUV3_DBCW_MAX];
+	struct dummy_page ffcw;
+	struct dummy_page fcw;
+	uint8_t reserved0[KB(4) * 11];
+	struct dummy_page impdef;
+} __packed;
+
+/* ====== MHUv3 data structures ====== */
+
+enum mbox_mhuv3_frame {
+	PBX_FRAME,
+	MBX_FRAME,
+};
+
+static char *mbox_mhuv3_str[] = {
+	"PBX",
+	"MBX"
+};
+
+enum mbox_mhuv3_extension_type {
+	DBE_EXT,
+	FCE_EXT,
+	FE_EXT,
+	NUM_EXT
+};
+
+static char *mbox_mhuv3_ext_str[] = {
+	"DBE",
+	"FCE",
+	"FE"
+};
+
+/** @brief MHUv3 channel information. */
+struct mbox_mhuv3_channel {
+	/** Channel window index associated to this mailbox channel. */
+	uint32_t ch_idx;
+	/**
+	 * Doorbell bit number within the @ch_idx window.
+	 * Only relevant to Doorbell transport.
+	 */
+	uint32_t doorbell;
+	/** Transport protocol specific operations for this channel. */
+	const struct mbox_mhuv3_protocol_ops *ops;
+	/** Callback function to execute on incoming message interrupts. */
+	mbox_callback_t cb;
+	/** Pointer to some private data provided at registration time */
+	void *user_data;
+};
+
+/** @brief MHUv3 operations */
+struct mbox_mhuv3_protocol_ops {
+	/** Receiver enable callback. */
+	int (*rx_enable)(const struct device *dev, struct mbox_mhuv3_channel *chan);
+	/** Receiver disable callback. */
+	int (*rx_disable)(const struct device *dev, struct mbox_mhuv3_channel *chan);
+	/** Read available Sender in-band LE data (if any). */
+	int *(*read_data)(const struct device *dev, struct mbox_mhuv3_channel *chan);
+	/**
+	 * Acknowledge data reception to the Sender. Any out-of-band data
+	 * has to have been already retrieved before calling this.
+	 */
+	int (*rx_complete)(const struct device *dev, struct mbox_mhuv3_channel *chan);
+	/** Sender enable callback. */
+	int (*tx_enable)(const struct device *dev, struct mbox_mhuv3_channel *chan);
+	/** Sender disable callback. */
+	int (*tx_disable)(const struct device *dev, struct mbox_mhuv3_channel *chan);
+	/** Report back to the Sender if the last transfer has completed. */
+	int (*last_tx_done)(const struct device *dev, struct mbox_mhuv3_channel *chan);
+	/** Send data to the receiver. */
+	int (*send_data)(const struct device *dev, struct mbox_mhuv3_channel *chan,
+			 const struct mbox_msg *msg);
+};
+
+/**
+ * @brief MHUv3 extension descriptor
+ */
+struct mbox_mhuv3_extension {
+	/** Type of extension. */
+	enum mbox_mhuv3_extension_type type;
+	/** Max number of channels found for this extension. */
+	uint32_t num_chans;
+	/**
+	 * First channel number assigned to this extension, picked from
+	 * the set of all mailbox channels descriptors created.
+	 */
+	uint32_t base_ch_idx;
+	/** Extension specific helper to parse DT and lookup associated
+	 *  channel from the related 'mboxes' property.
+	 */
+	struct mbox_mhuv3_channel *(*get_channel)(const struct device *dev,
+						  uint32_t channel,
+						  uint32_t param);
+	/** Extension specific helper to setup the combined irq. */
+	void (*combined_irq_setup)(const struct device *dev);
+	/** Extension specific helper to initialize channels. */
+	int (*channels_init)(const struct device *dev, uint32_t *base_ch_idx);
+	/**
+	 * Extension specific helper to lookup which channel
+	 * triggered the combined irq.
+	 */
+	struct mbox_mhuv3_channel *(*chan_from_comb_irq_get)(const struct device *dev);
+	/** Extension specifier helper to get maximum data size. */
+	int (*mtu_get)(void);
+	/** Array of per-channel pending doorbells. */
+	uint32_t pending_db[MHUV3_DBCW_MAX];
+	/** Protect access to pending_db */
+	struct k_spinlock pending_lock;
+};
+
+/**
+ * @brief MHUv3 mailbox configuration data
+ */
+struct mbox_mhuv3_config {
+	/** A reference to the MHUv3 control page for this block. */
+	struct ctrl_page *ctrl;
+	union {
+		/** Base address of the PBX register mapping region. */
+		struct mhuv3_pbx_frame_reg *pbx;
+		/** Base address of the MBX register mapping region. */
+		struct mhuv3_mbx_frame_reg *mbx;
+	};
+	/** Interrupt configuration function pointer. */
+	void (*cmb_irq_config)(const struct device *dev);
+};
+
+/**
+ * @brief MHUv3 mailbox controller data
+ */
+struct mbox_mhuv3_data {
+	/** Frame type: MBX_FRAME or PBX_FRAME. */
+	enum mbox_mhuv3_frame frame;
+	/** Flag to indicate if the MHU supports AutoOp full mode. */
+	bool auto_op_full;
+	/** MHUv3 controller architectural major version. */
+	uint32_t major;
+	/** MHUv3 controller architectural minor version. */
+	uint32_t minor;
+	/** MHUv3 controller IIDR implementer. */
+	uint32_t implem;
+	/** MHUv3 controller IIDR revision. */
+	uint32_t rev;
+	/** MHUv3 controller IIDR variant. */
+	uint32_t var;
+	/** MHUv3 controller IIDR product_id. */
+	uint32_t prod_id;
+	/** The total number of channels discovered across all extensions. */
+	uint32_t num_chans;
+	/** Array holding descriptors for any found implemented extension. */
+	struct mbox_mhuv3_extension ext[NUM_EXT];
+	/** Array of channels */
+	/**
+	 * TODO: The total number of channels should be increased when the rest of the
+	 * extensions get supported.
+	 */
+	struct mbox_mhuv3_channel channels[CONFIG_MBOX_MHUV3_NUM_DBCH][MHUV3_FLAG_BITS];
+};
+
+typedef int (*mhuv3_extension_initializer)(const struct device *dev);
+
+/* =========================== Utility Functions =========================== */
+
+/**
+ * @brief Reads a bitmask from a 32-bit memory-mapped register.
+ *
+ * Extracts and returns the value of bits specified by a bitmask
+ * from the register at the given memory address.
+ *
+ * @param addr Address of the 32-bit register.
+ * @param bitmask Bitmask specifying the bits to extract.
+ *
+ * @return Extracted bitmask value.
+ */
+static ALWAYS_INLINE uint32_t read_bitmask32(mem_addr_t addr, uint32_t bitmask)
+{
+	uint32_t reg = sys_read32(addr);
+
+	return FIELD_GET(bitmask, reg);
+}
+
+/**
+ * @brief Writes a bitmask to a 32-bit memory-mapped register.
+ *
+ * Updates bits specified by a bitmask in the register at the given
+ * memory address with the provided data value.
+ *
+ * @param data Value to write to the specified bits.
+ * @param addr Address of the 32-bit register.
+ * @param bitmask Bitmask specifying the bits to update.
+ */
+static ALWAYS_INLINE void write_bitmask32(uint32_t data, mem_addr_t addr, uint32_t bitmask)
+{
+	uint32_t reg = sys_read32(addr);
+
+	reg &= ~bitmask;
+	reg |= FIELD_PREP(bitmask, data);
+	sys_write32(reg, addr);
+}
+
+/* =================== Doorbell transport protocol operations =============== */
+
+/**
+ * @brief Enables transfer acknowledgment events for a channel.
+ *
+ * @param dev Pointer to the device structure.
+ * @param chan Pointer to the MHUv3 channel structure.
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
+static int mbox_mhuv3_doorbell_tx_enable(const struct device *dev, struct mbox_mhuv3_channel *chan)
+{
+	const struct mbox_mhuv3_config *cfg = dev->config;
+
+	if (chan->ch_idx >= MHUV3_DBCW_MAX) {
+		return -EINVAL;
+	}
+
+	/* Enable Transfer Acknowledgment events */
+	write_bitmask32(0x1,
+			(mem_addr_t)&cfg->pbx->dbcw[chan->ch_idx].int_en,
+			PDBCW_INT_TFR_ACK);
+
+	return 0;
+}
+
+/**
+ * @brief Disables transfer acknowledgment events for a channel.
+ *
+ * Disables Transfer Acknowledgment events and clears the corresponding
+ * interrupt and pending doorbell for the specified channel.
+ *
+ * @param dev Pointer to the device structure.
+ * @param chan Pointer to the MHUv3 channel structure.
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
+static int mbox_mhuv3_doorbell_tx_disable(const struct device *dev, struct mbox_mhuv3_channel *chan)
+{
+	const struct mbox_mhuv3_config *cfg = dev->config;
+	struct mbox_mhuv3_data *data = dev->data;
+	struct mbox_mhuv3_extension *ext = &data->ext[DBE_EXT];
+	struct pdbcw_page *dbcw = cfg->pbx->dbcw;
+
+	if (chan->ch_idx >= MHUV3_DBCW_MAX) {
+		return -EINVAL;
+	}
+
+	/* Disable Channel Transfer Acknowledgment events */
+	write_bitmask32(0x0, (mem_addr_t)&dbcw[chan->ch_idx].int_en, PDBCW_INT_TFR_ACK);
+
+	/* Clear Channel Transfer Acknowledgment and pending doorbell */
+	write_bitmask32(0x1, (mem_addr_t)&dbcw[chan->ch_idx].int_clr, PDBCW_INT_TFR_ACK);
+	K_SPINLOCK(&ext->pending_lock) {
+		ext->pending_db[chan->ch_idx] = 0;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Enables transfer events for a channel.
+ *
+ * @param dev Pointer to the device structure.
+ * @param chan Pointer to the MHUv3 channel structure.
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
+static int mbox_mhuv3_doorbell_rx_enable(const struct device *dev, struct mbox_mhuv3_channel *chan)
+{
+	const struct mbox_mhuv3_config *cfg = dev->config;
+
+	if (chan->ch_idx >= MHUV3_DBCW_MAX) {
+		return -EINVAL;
+	}
+
+	/* Unmask Channel Transfer events */
+	sys_set_bit((mem_addr_t)&cfg->mbx->dbcw[chan->ch_idx].msk_clr, chan->doorbell);
+
+	return 0;
+}
+
+/**
+ * @brief Disables transfer events for a channel.
+ *
+ * @param dev Pointer to the device structure.
+ * @param chan Pointer to the MHUv3 channel structure.
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
+static int mbox_mhuv3_doorbell_rx_disable(const struct device *dev, struct mbox_mhuv3_channel *chan)
+{
+	const struct mbox_mhuv3_config *cfg = dev->config;
+
+	if (chan->ch_idx >= MHUV3_DBCW_MAX) {
+		return -EINVAL;
+	}
+
+	/* Mask Channel Transfer events */
+	sys_set_bit((mem_addr_t)&cfg->mbx->dbcw[chan->ch_idx].msk_set, chan->doorbell);
+
+	return 0;
+}
+
+/**
+ * @brief Completes a transfer event for a channel.
+ *
+ * @param dev Pointer to the device structure.
+ * @param chan Pointer to the MHUv3 channel structure.
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
+static int mbox_mhuv3_doorbell_rx_complete(const struct device *dev,
+					   struct mbox_mhuv3_channel *chan)
+{
+	const struct mbox_mhuv3_config *cfg = dev->config;
+
+	if (chan->ch_idx >= MHUV3_DBCW_MAX) {
+		return -EINVAL;
+	}
+
+	/* Clearing the pending transfer generates the Channel Transfer Acknowledge */
+	sys_set_bit((mem_addr_t)&cfg->mbx->dbcw[chan->ch_idx].clr, chan->doorbell);
+
+	return 0;
+}
+
+/**
+ * @brief Checks if the last transfer for a channel is complete.
+ *
+ * Determines whether the last transfer for the specified channel in the
+ * Doorbell Channel Window (DBCW) register is complete. If the transfer is
+ * complete, it also clears the pending doorbell for the channel.
+ *
+ * @param dev Pointer to the device structure.
+ * @param chan Pointer to the MHUv3 channel structure.
+ *
+ * @return 0 if the last transfer is complete, or a negative error code otherwise.
+ */
+static int mbox_mhuv3_doorbell_last_tx_done(const struct device *dev,
+					    struct mbox_mhuv3_channel *chan)
+{
+	const struct mbox_mhuv3_config *cfg = dev->config;
+
+	if (chan->ch_idx >= MHUV3_DBCW_MAX) {
+		return -EINVAL;
+	}
+
+	bool done = !(sys_test_bit((mem_addr_t)&cfg->pbx->dbcw[chan->ch_idx].st, chan->doorbell));
+
+	if (done) {
+		struct mbox_mhuv3_data *data = dev->data;
+		struct mbox_mhuv3_extension *ext = &data->ext[DBE_EXT];
+
+		/* Take care to clear the pending doorbell also when polling */
+		K_SPINLOCK(&ext->pending_lock) {
+			sys_clear_bit((mem_addr_t)&ext->pending_db[chan->ch_idx], chan->doorbell);
+		}
+
+		return 0;
+	}
+
+	return -EBUSY;
+}
+
+/**
+ * @brief Sends data via the specified channel.
+ *
+ * Attempts to send data using the specified channel. If the channel is
+ * busy (i.e., a transfer is already in progress), it returns an error.
+ * It also sets the appropriate flags to indicate pending data.
+ *
+ * @param dev Pointer to the device structure.
+ * @param chan Pointer to the MHUv3 channel structure.
+ * @param msg Pointer to the message structure containing data to be sent.
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
+static int mbox_mhuv3_doorbell_send_data(const struct device *dev,
+					 struct mbox_mhuv3_channel *chan,
+					 const struct mbox_msg *msg)
+{
+	const struct mbox_mhuv3_config *cfg = dev->config;
+	struct mbox_mhuv3_data *data = dev->data;
+	struct mbox_mhuv3_extension *ext = &data->ext[DBE_EXT];
+	int ret = 0;
+
+	if (chan->ch_idx >= MHUV3_DBCW_MAX) {
+		return -EINVAL;
+	}
+
+	if (msg) {
+		LOG_WRN("Doorbell extension does not support sending data");
+	}
+
+	K_SPINLOCK(&ext->pending_lock) {
+		if (sys_test_bit((mem_addr_t)&ext->pending_db[chan->ch_idx], chan->doorbell)) {
+			ret = -EBUSY;
+		} else {
+			sys_set_bit((mem_addr_t)&ext->pending_db[chan->ch_idx], chan->doorbell);
+		}
+	}
+
+	if (ret == 0) {
+		sys_set_bit((mem_addr_t)&cfg->pbx->dbcw[chan->ch_idx].set, chan->doorbell);
+	}
+
+	return ret;
+}
+
+static const struct mbox_mhuv3_protocol_ops mhuv3_doorbell_ops = {
+	.tx_enable = mbox_mhuv3_doorbell_tx_enable,
+	.tx_disable = mbox_mhuv3_doorbell_tx_disable,
+	.rx_enable = mbox_mhuv3_doorbell_rx_enable,
+	.rx_disable = mbox_mhuv3_doorbell_rx_disable,
+	.rx_complete = mbox_mhuv3_doorbell_rx_complete,
+	.last_tx_done = mbox_mhuv3_doorbell_last_tx_done,
+	.send_data = mbox_mhuv3_doorbell_send_data,
+};
+
+/**
+ * @brief Retrieves the MHUv3 channel based on the provided channel ID.
+ *
+ * This function extracts the channel and doorbell numbers from the
+ * given Flattened Channel ID, and retrieves the corresponding channel
+ * from the Doorbell extension. The Flattened Channel ID is calculated
+ * using the formula: Channel ID * MHUV3_FLAG_BITS + Doorbell.
+ *
+ * @param dev Pointer to the device structure.
+ * @param channel_id The Flattened Channel ID that contains both the
+ *		     channel and doorbell information.
+ *
+ * @return Pointer to the corresponding MHUv3 channel structure.
+ */
+static struct mbox_mhuv3_channel *mbox_mhuv3_get_channel(const struct device *dev,
+							 mbox_channel_id_t channel_id)
+{
+	struct mbox_mhuv3_data *data = dev->data;
+	uint32_t channel, doorbell;
+
+	/**
+	 * TODO: The type of extension, channel and doorbell should be
+	 * extracted from a struct passed to this function from device tree,
+	 * but mbox_channel_id_t is only a Flattened Channel ID,
+	 * where Flattened Channel ID = Channel ID * MHUV3_FLAG_BITS + Doorbell
+	 * Until this is changed, Pin the type to Doorbell extension and use
+	 * the next formula to get the actual channel and doorbell numbers.
+	 */
+	enum mbox_mhuv3_extension_type type = DBE_EXT;
+
+	channel = channel_id / MHUV3_FLAG_BITS;
+	doorbell = channel_id % MHUV3_FLAG_BITS;
+
+	return data->ext[type].get_channel(dev, channel, doorbell);
+}
+
+/**
+ * @brief Sends data using the specified MHUv3 sender channel.
+ *
+ * This function checks if the last transmission is complete for the
+ * specified channel. If not, it returns an error. If the channel is
+ * available, it proceeds to send the data using the channel's send_data
+ * operation.
+ *
+ * @param dev Pointer to the device structure.
+ * @param channel_id The ID of the channel to use for sending data.
+ * @param msg Pointer to the message structure containing the data to be sent.
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
+static int mbox_mhuv3_sender_send_data(const struct device *dev,
+				       mbox_channel_id_t channel_id,
+				       const struct mbox_msg *msg)
+{
+	struct mbox_mhuv3_channel *chan = mbox_mhuv3_get_channel(dev, channel_id);
+	int ret;
+
+	ret = chan->ops->last_tx_done(dev, chan);
+	if (ret) {
+		return ret;
+	}
+
+	return chan->ops->send_data(dev, chan, msg);
+}
+
+/**
+ * @brief Attempts to send data using the MHUv3 receiver channel (not supported).
+ *
+ * This function logs an error as transmitting data on an MHUv3 receiver channel
+ * is not supported and returns an I/O error.
+ *
+ * @param dev Pointer to the device structure.
+ * @param channel_id The ID of the channel (unused).
+ * @param msg Pointer to the message structure (unused).
+ *
+ * @return -ENOTSUP to indicate an I/O error as transmission is not supported.
+ */
+static int mbox_mhuv3_receiver_send_data(const struct device *dev,
+					 mbox_channel_id_t channel_id,
+					 const struct mbox_msg *msg)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(channel_id);
+	ARG_UNUSED(msg);
+
+	LOG_ERR("Trying to transmit on a MBX MHUv3 frame");
+
+	return -ENOTSUP;
+}
+
+/**
+ * @brief Sends data based on the frame type.
+ *
+ * This function determines whether to send data using the sender or receiver
+ * functions based on the current frame type.
+ *
+ * @param dev Pointer to the device structure.
+ * @param channel_id The ID of the channel to use for sending data.
+ * @param msg Pointer to the message structure containing the data to be sent.
+ *
+ * @return 0 on success, an error code on failure.
+ */
+static int mbox_mhuv3_send_data(const struct device *dev,
+				mbox_channel_id_t channel_id,
+				const struct mbox_msg *msg)
+{
+	struct mbox_mhuv3_data *data = dev->data;
+
+	if (data->frame == PBX_FRAME) {
+		return mbox_mhuv3_sender_send_data(dev, channel_id, msg);
+	}
+
+	return mbox_mhuv3_receiver_send_data(dev, channel_id, msg);
+}
+
+/**
+ * @brief Retrieves the MHUv3 channel based on the specified channel and doorbell.
+ *
+ * This function returns the channel structure for the given channel and doorbell
+ * numbers.
+ *
+ * @param dev Pointer to the device structure.
+ * @param channel The channel number to retrieve.
+ * @param doorbell The doorbell number to retrieve.
+ *
+ * @return Pointer to the corresponding MHUv3 channel structure, or NULL if invalid.
+ */
+static struct mbox_mhuv3_channel *mbox_mhuv3_dbe_get_channel(const struct device *dev,
+							     uint32_t channel,
+							     uint32_t doorbell)
+{
+	struct mbox_mhuv3_data *data = dev->data;
+	struct mbox_mhuv3_extension *ext = &data->ext[DBE_EXT];
+
+	if (channel >= ext->num_chans || doorbell >= MHUV3_FLAG_BITS) {
+		LOG_ERR("Couldn't find a valid channel (%d: %d)", channel, doorbell);
+		return NULL;
+	}
+
+	return &data->channels[ext->base_ch_idx + channel][doorbell];
+}
+
+/**
+ * @brief Configures the combined IRQ for the MHUv3 device.
+ *
+ * This function sets up the combined interrupt handling for the specified device,
+ * configuring the interrupt enable, clear, and control registers for each channel.
+ * It handles both PBX and non-PBX frame types differently.
+ *
+ * @param dev Pointer to the device structure.
+ */
+static void mbox_mhuv3_dbe_combined_irq_setup(const struct device *dev)
+{
+	const struct mbox_mhuv3_config *cfg = dev->config;
+	struct mbox_mhuv3_data *data = dev->data;
+	struct mbox_mhuv3_extension *ext = &data->ext[DBE_EXT];
+	uint32_t i;
+
+	if (data->frame == PBX_FRAME) {
+		struct pdbcw_page *dbcw = cfg->pbx->dbcw;
+
+		for (i = 0; i < ext->num_chans; i++) {
+			write_bitmask32(0x1, (mem_addr_t)&dbcw[i].int_clr, PDBCW_INT_TFR_ACK);
+			write_bitmask32(0x0, (mem_addr_t)&dbcw[i].int_en, PDBCW_INT_TFR_ACK);
+			write_bitmask32(0x1, (mem_addr_t)&dbcw[i].ctrl, XBCW_CTRL_COMB_EN);
+		}
+	} else {
+		struct mdbcw_page *dbcw = cfg->mbx->dbcw;
+
+		for (i = 0; i < ext->num_chans; i++) {
+			sys_write32(0xFFFFFFFFU, (mem_addr_t)&dbcw[i].clr);
+			sys_write32(0xFFFFFFFFU, (mem_addr_t)&dbcw[i].msk_set);
+			write_bitmask32(0x1, (mem_addr_t)&dbcw[i].ctrl, XBCW_CTRL_COMB_EN);
+		}
+	}
+}
+
+/**
+ * @brief Initializes the MHUv3 DBE channels.
+ *
+ * This function initializes the MHUv3 DBE channels by assigning the base index,
+ * configuring each channel with its corresponding index and doorbell, and
+ * setting the appropriate channel operations. It updates the base channel index
+ * after initialization.
+ *
+ * @param dev Pointer to the device structure.
+ * @param base_ch_idx Pointer to the base channel index.
+ *
+ * @return 0 on success.
+ */
+static int mbox_mhuv3_dbe_channels_init(const struct device *dev, uint32_t *base_ch_idx)
+{
+	struct mbox_mhuv3_data *data = dev->data;
+	struct mbox_mhuv3_extension *ext = &data->ext[DBE_EXT];
+	struct mbox_mhuv3_channel *chan;
+
+	__ASSERT(((*base_ch_idx + ext->num_chans) * MHUV3_FLAG_BITS) < data->num_chans,
+		 "The number of allocated channels is less than required by the MHUv3 extension");
+
+	ext->base_ch_idx = *base_ch_idx;
+	chan = &data->channels[*base_ch_idx];
+
+	for (uint32_t i = 0; i < ext->num_chans; i++) {
+		for (uint32_t k = 0; k < MHUV3_FLAG_BITS; k++) {
+			chan->ch_idx = i;
+			chan->doorbell = k;
+			chan->ops = &mhuv3_doorbell_ops;
+			chan++;
+		}
+	}
+
+	*base_ch_idx += ext->num_chans;
+
+	return 0;
+}
+
+/**
+ * @brief Searches for the active doorbell for the given MHUv3 DBE channel.
+ *
+ * This function checks the interrupt status and identifies which doorbell has been
+ * triggered for the specified channel. It returns the doorbell index if found or
+ * logs a warning if an unexpected interrupt occurs.
+ *
+ * @param dev Pointer to the device structure.
+ * @param channel The channel to check for the doorbell.
+ * @param doorbell Pointer to store the found doorbell index.
+ *
+ * @return true if a doorbell is found, false if an unexpected IRQ is encountered.
+ */
+static bool mbox_mhuv3_dbe_doorbell_search(const struct device *dev,
+					   uint32_t channel,
+					   uint32_t *doorbell)
+{
+	const struct mbox_mhuv3_config *cfg = dev->config;
+	struct mbox_mhuv3_data *data = dev->data;
+	struct mbox_mhuv3_extension *ext = &data->ext[DBE_EXT];
+	uint32_t st;
+
+	__ASSERT(channel < MHUV3_DBCW_MAX,
+		 "Number of channels exceeds the maximum number of doorbell channel windows.");
+
+	if (data->frame == PBX_FRAME) {
+		uint32_t active_doorbells, fired_doorbells;
+
+		st = read_bitmask32((mem_addr_t)&cfg->pbx->dbcw[channel].int_st, PDBCW_INT_TFR_ACK);
+		if (!st) {
+			goto unexpected_irq;
+		}
+		active_doorbells = sys_read32((mem_addr_t)&cfg->pbx->dbcw[channel].st);
+		K_SPINLOCK(&ext->pending_lock) {
+			fired_doorbells = ext->pending_db[channel] & ~active_doorbells;
+			if (!fired_doorbells) {
+				K_SPINLOCK_BREAK;
+			}
+
+			*doorbell = find_lsb_set(fired_doorbells) - 1;
+			ext->pending_db[channel] &= ~BIT(*doorbell);
+		}
+		if (!fired_doorbells) {
+			goto unexpected_irq;
+		}
+		/* If no other pending doorbells, clear the transfer acknowledge */
+		if (!(fired_doorbells & ~BIT(*doorbell))) {
+			write_bitmask32(0x1, (mem_addr_t)&cfg->pbx->dbcw[channel].int_clr,
+					PDBCW_INT_TFR_ACK);
+		}
+	} else {
+		st = sys_read32((mem_addr_t)&cfg->mbx->dbcw[channel].st_msk);
+		if (!st) {
+			goto unexpected_irq;
+		}
+
+		*doorbell = find_lsb_set(st) - 1;
+	}
+
+	return true;
+
+unexpected_irq:
+	LOG_WRN("Unexpected IRQ on %s channel:%d", mbox_mhuv3_str[data->frame], channel);
+
+	return false;
+}
+
+/**
+ * @brief Retrieves the channel corresponding to a combined interrupt.
+ *
+ * This function checks the combined interrupt status for the MHUv3 DBE device and
+ * identifies the channel and doorbell associated with the interrupt. It returns the
+ * matching channel if found, or NULL if no valid channel is identified.
+ *
+ * @param dev Pointer to the device structure.
+ *
+ * @return Pointer to the mbox_mhuv3_channel if a valid channel is found, NULL otherwise.
+ */
+static struct mbox_mhuv3_channel *mbox_mhuv3_dbe_chan_from_comb_irq_get(const struct device *dev)
+{
+	const struct mbox_mhuv3_config *cfg = dev->config;
+	struct mbox_mhuv3_data *data = dev->data;
+	struct mbox_mhuv3_extension *ext = &data->ext[DBE_EXT];
+
+	for (uint32_t i = 0; i < MHUV3_DBCH_CMB_INT_ST_REG_CNT; i++) {
+		uint32_t channel, doorbell, int_st;
+
+		int_st = sys_read32((mem_addr_t)&cfg->ctrl->dbch_int_st[i]);
+		if (!int_st) {
+			continue;
+		}
+
+		channel = i * MHUV3_FLAG_BITS + (find_lsb_set(int_st) - 1);
+		if (channel >= ext->num_chans) {
+			LOG_ERR("Invalid %s channel: %d", mbox_mhuv3_str[data->frame], channel);
+			return NULL;
+		}
+
+		if (!mbox_mhuv3_dbe_doorbell_search(dev, channel, &doorbell)) {
+			continue;
+		}
+
+		LOG_DBG("Found %s channel [%d], doorbell[%d]",
+			mbox_mhuv3_str[data->frame], channel, doorbell);
+		return &data->channels[channel][doorbell];
+	}
+
+	return NULL;
+}
+
+/**
+ * @brief Retrieves the maximum transmit units for doorbell extension.
+ *
+ * @return 0 as doorbell extension does not support transmitting data.
+ */
+static int mbox_mhuv3_dbe_mtu_get(void)
+{
+	return 0;
+}
+
+/**
+ * @brief Initializes the Doorbell Extension (DBE) for the MHUv3 device.
+ *
+ * This function initializes the Doorbell Extension (DBE) by reading the number
+ * of channels from the device's control registers, and setting up necessary handlers.
+ * If the feature is not supported, it returns early. It also updates the device's
+ * data with the number of channels available and the extension's function pointers.
+ *
+ * @param dev Pointer to the device structure.
+ *
+ * @return 0 if initialization is successful, negative error code if there is a failure.
+ */
+static int mbox_mhuv3_dbe_init(const struct device *dev)
+{
+	const struct mbox_mhuv3_config *cfg = dev->config;
+	struct mbox_mhuv3_data *data = dev->data;
+	struct mbox_mhuv3_extension *ext = &data->ext[DBE_EXT];
+	uint32_t num_chans;
+
+	if (!read_bitmask32((mem_addr_t)&cfg->ctrl->feat_spt0, FEAT_SPT0_DBE_SPT)) {
+		return 0;
+	}
+
+	LOG_DBG("%s: Initializing Doorbell Extension.", mbox_mhuv3_str[data->frame]);
+
+	ext->type = DBE_EXT;
+	/* Note that, by the spec, the number of channels is (num_dbch + 1) */
+	num_chans = read_bitmask32((mem_addr_t)&cfg->ctrl->dbch_cfg0, DBCH_CFG0_NUM_DBCH) + 1;
+	__ASSERT(CONFIG_MBOX_MHUV3_NUM_DBCH >= num_chans,
+		"The number of configured doorbell channels is less than required by the MHUv3 extension");
+	ext->num_chans = num_chans;
+	ext->get_channel = mbox_mhuv3_dbe_get_channel;
+	ext->combined_irq_setup = mbox_mhuv3_dbe_combined_irq_setup;
+	ext->channels_init = mbox_mhuv3_dbe_channels_init;
+	ext->chan_from_comb_irq_get = mbox_mhuv3_dbe_chan_from_comb_irq_get;
+	ext->mtu_get = mbox_mhuv3_dbe_mtu_get;
+
+	data->num_chans += ext->num_chans * MHUV3_FLAG_BITS;
+
+	LOG_DBG("%s: found %d DBE channels.", mbox_mhuv3_str[data->frame], ext->num_chans);
+
+	return 0;
+}
+
+/**
+ * @brief Initializes the Fast Channel Extension (FCE) for the MHUv3 device.
+ *
+ * This function initializes the Fast Channel Extension (FCE). Currently,
+ * FCE is not supported.
+ *
+ * @param dev Pointer to the device structure.
+ *
+ * @return 0, indicating that the function completes successfully.
+ */
+static int mbox_mhuv3_fce_init(const struct device *dev)
+{
+	const struct mbox_mhuv3_config *cfg = dev->config;
+	struct mbox_mhuv3_data *data = dev->data;
+
+	if (!read_bitmask32((mem_addr_t)&cfg->ctrl->feat_spt0, FEAT_SPT0_FCE_SPT)) {
+		return 0;
+	}
+
+	LOG_DBG("%s: Fast Channel Extension is not supported by driver.",
+		mbox_mhuv3_str[data->frame]);
+
+	return 0;
+}
+
+/**
+ * @brief Initializes the FIFO Extension (FE) for the MHUv3 device.
+ *
+ * This function initializes the FIFO Extension (FE). Currently,
+ * FE is not supported.
+ *
+ * @param dev Pointer to the device structure.
+ *
+ * @return 0, indicating that the function completes successfully.
+ */
+static int mbox_mhuv3_fe_init(const struct device *dev)
+{
+	const struct mbox_mhuv3_config *cfg = dev->config;
+	struct mbox_mhuv3_data *data = dev->data;
+
+	if (!read_bitmask32((mem_addr_t)&cfg->ctrl->feat_spt0, FEAT_SPT0_FE_SPT)) {
+		return 0;
+	}
+
+	LOG_DBG("%s: FIFO Extension is not supported by driver.", mbox_mhuv3_str[data->frame]);
+
+	return 0;
+}
+
+static mhuv3_extension_initializer mhuv3_extension_init[NUM_EXT] = {
+	mbox_mhuv3_dbe_init,
+	mbox_mhuv3_fce_init,
+	mbox_mhuv3_fe_init,
+};
+
+/**
+ * @brief Initializes the channels for the MHUv3 device.
+ *
+ * This function allocates memory for the channels array and initializes
+ * each channel based on the device's extensions. It calls the `channels_init`
+ * function for each extension and updates the base channel index accordingly.
+ *
+ * @param dev Pointer to the device structure.
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
+static int mbox_mhuv3_initialize_channels(const struct device *dev)
+{
+	struct mbox_mhuv3_data *data = dev->data;
+	uint32_t base_ch_idx = 0;
+	int ret = 0;
+
+	for (uint32_t i = 0; i < NUM_EXT && !ret; i++) {
+		struct mbox_mhuv3_extension *ext = &data->ext[i];
+
+		if (ext->num_chans > 0) {
+			ret = ext->channels_init(dev, &base_ch_idx);
+		}
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Initializes the MHUv3 frame for the device.
+ *
+ * This function reads the block ID to determine the frame type (PBX or MBX),
+ * retrieves the version and implementer information, and checks if the frame
+ * is supported. It also handles the initialization of extensions for the MHUv3 device.
+ *
+ * @param dev Pointer to the device structure.
+ *
+ * @return 0 on success, or a negative error code on failure (e.g., -EIO, -ENOMEM).
+ */
+static int mbox_mhuv3_frame_init(const struct device *dev)
+{
+	const struct mbox_mhuv3_config *cfg = dev->config;
+	struct mbox_mhuv3_data *data = dev->data;
+
+	data->frame = read_bitmask32((mem_addr_t)&cfg->ctrl->blk_id, BLK_ID_BLK_ID);
+	if (data->frame > MBX_FRAME) {
+		LOG_ERR("Invalid Frame type- %d", data->frame);
+		return -EIO;
+	}
+
+	data->major = read_bitmask32((mem_addr_t)&cfg->ctrl->aidr, AIDR_ARCH_MAJOR_REV);
+	data->minor = read_bitmask32((mem_addr_t)&cfg->ctrl->aidr, AIDR_ARCH_MINOR_REV);
+	data->implem = read_bitmask32((mem_addr_t)&cfg->ctrl->iidr, IIDR_IMPLEMENTER);
+	data->rev = read_bitmask32((mem_addr_t)&cfg->ctrl->iidr, IIDR_REVISION);
+	data->var = read_bitmask32((mem_addr_t)&cfg->ctrl->iidr, IIDR_VARIANT);
+	data->prod_id = read_bitmask32((mem_addr_t)&cfg->ctrl->iidr, IIDR_PRODUCT_ID);
+	if (data->major != MHUV3_MAJOR_VERSION) {
+		LOG_ERR("Unsupported MHU %s block - major:%d  minor:%d",
+			mbox_mhuv3_str[data->frame], data->major, data->minor);
+		return -EIO;
+	}
+
+	data->auto_op_full = !!read_bitmask32((mem_addr_t)&cfg->ctrl->feat_spt1,
+					      FEAT_SPT1_AUTO_OP_SPT);
+	/* Request the PBX/MBX to remain operational */
+	if (data->auto_op_full) {
+		write_bitmask32(0x1, (mem_addr_t)&cfg->ctrl->x_ctrl, CTRL_OP_REQ);
+	}
+
+	LOG_DBG("Found MHU %s block - major:%d  minor:%d\n"
+		"  implem:0x%X  rev:0x%X  var:0x%X  prod_id:0x%X",
+		mbox_mhuv3_str[data->frame], data->major, data->minor,
+		data->implem, data->rev, data->var, data->prod_id);
+
+	for (uint32_t i = 0; i < NUM_EXT; i++) {
+		uint32_t ret;
+		/*
+		 * Note that extensions initialization fails only when such
+		 * extension initialization routine fails and the extensions
+		 * was found to be supported in hardware and in software.
+		 */
+		ret = mhuv3_extension_init[i](dev);
+		if (ret) {
+			LOG_ERR("Failed to initialize %s %s: %d",
+				mbox_mhuv3_str[data->frame],
+				mbox_mhuv3_ext_str[i],
+				ret);
+			return -EIO;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Handles the PBX combined interrupt for the MHUv3 device.
+ *
+ * This function iterates through all available extensions and checks for channels
+ * that are part of the combined interrupt mechanism.
+ *
+ * @param dev Pointer to the device structure.
+ */
+static void mbox_mhuv3_pbx_comb_interrupt(const struct device *dev)
+{
+	uint32_t found = 0;
+
+	for (uint32_t i = 0; i < NUM_EXT; i++) {
+		struct mbox_mhuv3_data *data = dev->data;
+		struct mbox_mhuv3_extension *ext = &data->ext[i];
+		struct mbox_mhuv3_channel *chan;
+
+		/* FCE does not participate to the PBX combined */
+		if (i == FCE_EXT || ext->num_chans == 0) {
+			continue;
+		}
+
+		chan = ext->chan_from_comb_irq_get(dev);
+		if (!chan) {
+			continue;
+		}
+
+		found++;
+
+		if (!chan->ops) {
+			LOG_WRN("TX Ack on UNBOUND channel (%u)", chan->ch_idx);
+			continue;
+		}
+	}
+
+	if (found == 0) {
+		LOG_WRN("Failed to find channel for the TX interrupt");
+	}
+}
+
+/**
+ * @brief Handles the MBX combined interrupt for the MHUv3 device.
+ *
+ * This function iterates through all available extensions and checks for channels
+ * that are part of the combined interrupt mechanism. It reads data from the channel
+ * if available and invokes the appropriate callback for the channel.
+ *
+ * @param dev Pointer to the device structure.
+ */
+static void mbox_mhuv3_mbx_comb_interrupt(const struct device *dev)
+{
+	uint32_t found = 0;
+
+	for (uint32_t i = 0; i < NUM_EXT; i++) {
+		struct mbox_mhuv3_data *data = dev->data;
+		struct mbox_mhuv3_extension *ext = &data->ext[i];
+		struct mbox_mhuv3_channel *chan;
+		uint32_t flattened_ch_idx;
+
+		if (ext->num_chans == 0) {
+			continue;
+		}
+
+		chan = ext->chan_from_comb_irq_get(dev);
+		if (!chan) {
+			continue;
+		}
+
+		found++;
+
+		if (!chan->ops) {
+			LOG_WRN("RX Data on UNBOUND channel (%u)", chan->ch_idx);
+		}
+
+		if (chan->ops->read_data) {
+			void *data = chan->ops->read_data(dev, chan);
+
+			if (!data) {
+				LOG_ERR("Failed to read in-band data.");
+				goto rx_ack;
+			}
+		}
+
+		/* Call channel call back */
+		flattened_ch_idx = chan->ch_idx * MHUV3_FLAG_BITS + chan->doorbell;
+		chan->cb(dev, flattened_ch_idx, chan->user_data, NULL);
+
+rx_ack:
+		if (chan->ops->rx_complete) {
+			chan->ops->rx_complete(dev, chan);
+		}
+	}
+
+	if (found == 0) {
+		LOG_ERR("Failed to find channel for the RX interrupt");
+	}
+}
+
+/**
+ * @brief Handles the combined interrupt for the MHUv3 device, based on the frame type.
+ *
+ * This function checks the current frame type of the MHUv3 device (PBX or MBX) and
+ * delegates the interrupt handling to the appropriate function.
+ *
+ * @param dev Pointer to the device structure.
+ */
+static void mbox_mhuv3_comb_interrupt(const struct device *dev)
+{
+	struct mbox_mhuv3_data *data = dev->data;
+
+	if (data->frame == PBX_FRAME) {
+		mbox_mhuv3_pbx_comb_interrupt(dev);
+	} else {
+		mbox_mhuv3_mbx_comb_interrupt(dev);
+	}
+}
+
+/**
+ * @brief Sets up the PBX for the MHUv3 device.
+ *
+ * This function initializes the PBX-related IRQs (interrupts) for the MHUv3 device.
+ * If no combined IRQ configuration is provided, it defaults to using PBX in Tx polling mode.
+ *
+ * @param dev Pointer to the device structure.
+ * @return 0 on success.
+ */
+static int mbox_mhuv3_setup_pbx(const struct device *dev)
+{
+	const struct mbox_mhuv3_config *cfg = dev->config;
+
+	if (cfg->cmb_irq_config != NULL) {
+		cfg->cmb_irq_config(dev);
+
+		for (uint32_t i = 0; i < NUM_EXT; i++) {
+			struct mbox_mhuv3_data *data = dev->data;
+
+			if (data->ext[i].num_chans > 0) {
+				data->ext[i].combined_irq_setup(dev);
+			}
+		}
+
+		LOG_DBG("MHUv3 PBX IRQs initialized.");
+
+		return 0;
+	}
+
+	LOG_INF("Using PBX in Tx polling mode.");
+
+	return 0;
+}
+
+/**
+ * @brief Sets up the MBX for the MHUv3 device.
+ *
+ * This function initializes the MBX-related IRQs (interrupts) for the MHUv3 device.
+ *
+ * @param dev Pointer to the device structure.
+ * @return 0 on success, -EINVAL if combined IRQ configuration is missing.
+ */
+static int mbox_mhuv3_setup_mbx(const struct device *dev)
+{
+	const struct mbox_mhuv3_config *cfg = dev->config;
+
+	if (cfg->cmb_irq_config == NULL) {
+		LOG_ERR("MBX combined IRQ is missing!");
+		return -EINVAL;
+	}
+
+	cfg->cmb_irq_config(dev);
+
+	for (uint32_t i = 0; i < NUM_EXT; i++) {
+		struct mbox_mhuv3_data *data = dev->data;
+
+		if (data->ext[i].num_chans > 0) {
+			data->ext[i].combined_irq_setup(dev);
+		}
+	}
+
+	LOG_DBG("MHUv3 MBX IRQs initialized.");
+
+	return 0;
+}
+
+/**
+ * @brief Initializes the IRQs for the MHUv3 device.
+ *
+ * This function initializes the IRQs (interrupts) based on the frame type
+ * of the MHUv3 device.
+ *
+ * @param dev Pointer to the device structure.
+ * @return 0 on success, or the error code returned by the setup functions.
+ */
+static int mbox_mhuv3_irqs_init(const struct device *dev)
+{
+	struct mbox_mhuv3_data *data = dev->data;
+
+	LOG_DBG("Initializing %s block.", mbox_mhuv3_str[data->frame]);
+
+	if (data->frame == PBX_FRAME) {
+		return mbox_mhuv3_setup_pbx(dev);
+	}
+
+	return mbox_mhuv3_setup_mbx(dev);
+}
+
+/**
+ * @brief Initializes the MHUv3 device.
+ *
+ * This function initializes the MHUv3 device by performing the following steps:
+ * 1. Initializes the frame type.
+ * 2. Initializes the IRQs.
+ * 3. Initializes the channels.
+ *
+ * If any of the initialization steps fail, the error code is returned immediately.
+ *
+ * @param dev Pointer to the device structure.
+ * @return 0 on success, or the error code from any of the initialization functions.
+ */
+static int mbox_mhuv3_init(const struct device *dev)
+{
+	int ret;
+
+	ret = mbox_mhuv3_frame_init(dev);
+	if (ret) {
+		return ret;
+	}
+
+	ret = mbox_mhuv3_irqs_init(dev);
+	if (ret) {
+		return ret;
+	}
+
+	ret = mbox_mhuv3_initialize_channels(dev);
+	if (ret) {
+		return ret;
+	}
+
+	return ret;
+}
+
+/**
+ * @brief Attempts to register a callback for a specified channel on the sender.
+ *
+ * @param dev Pointer to the device structure.
+ * @param channel_id The ID of the channel for the callback.
+ * @param cb The callback function to be registered.
+ * @param user_data User data to be passed to the callback.
+ *
+ * @return Always returns -ENOTSUP as callback registration for a sender device is not supported.
+ */
+static int mbox_mhuv3_sender_register_callback(const struct device *dev,
+					       mbox_channel_id_t channel_id,
+					       mbox_callback_t cb, void *user_data)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(channel_id);
+	ARG_UNUSED(cb);
+	ARG_UNUSED(user_data);
+
+	LOG_ERR("Trying to register a callback on a PBX MHUv3 frame");
+
+	return -ENOTSUP;
+}
+
+/**
+ * @brief Registers a callback function for a specified channel on the receiver.
+ *
+ * This function associates a callback with the specified channel. The callback
+ * will be invoked when the receiver processes data for that channel. The user
+ * data will be passed to the callback when it is called.
+ *
+ * @param dev Pointer to the device structure.
+ * @param channel_id The channel ID for which the callback is being registered.
+ * @param cb The callback function to register for the receiver.
+ * @param user_data User-specific data that will be passed to the callback.
+ *
+ * @return 0 on success, or -EINVAL if the specified channel is invalid.
+ */
+static int mbox_mhuv3_receiver_register_callback(const struct device *dev,
+						 mbox_channel_id_t channel_id,
+						 mbox_callback_t cb, void *user_data)
+{
+	struct mbox_mhuv3_channel *chan = mbox_mhuv3_get_channel(dev, channel_id);
+
+	if (!chan) {
+		return -EINVAL;
+	}
+
+	chan->cb = cb;
+	chan->user_data = user_data;
+
+	return 0;
+}
+
+/**
+ * @brief Registers a callback function for a specified channel, based on the frame type.
+ *
+ * @param dev Pointer to the device structure.
+ * @param channel_id The channel ID for which the callback is being registered.
+ * @param cb The callback function to register.
+ * @param user_data User-specific data that will be passed to the callback.
+ *
+ * @return 0 on success, or an error code from the sender or receiver callback registration.
+ */
+static int mbox_mhuv3_register_callback(const struct device *dev,
+					mbox_channel_id_t channel_id,
+					mbox_callback_t cb, void *user_data)
+{
+	struct mbox_mhuv3_data *data = dev->data;
+
+	if (data->frame == PBX_FRAME) {
+		return mbox_mhuv3_sender_register_callback(dev, channel_id, cb, user_data);
+	}
+
+	return mbox_mhuv3_receiver_register_callback(dev, channel_id, cb, user_data);
+}
+
+/**
+ * @brief Retrieves the maximum transmission unit (MTU) for the sender device.
+ *
+ * @param dev Pointer to the device structure.
+ *
+ * @return The MTU size for the sender channel.
+ */
+static int mbox_mhuv3_sender_mtu_get(const struct device *dev)
+{
+	struct mbox_mhuv3_data *data = dev->data;
+
+	/**
+	 * TODO: The maximum transmit units depends on the channel extension.
+	 * The type of extension, channel and doorbell should be
+	 * extracted from a struct passed to this function from device tree.
+	 * Until this is changed, Pin the type to Doorbell extension which
+	 * is the only supported extension.
+	 */
+
+	enum mbox_mhuv3_extension_type type = DBE_EXT;
+
+	return data->ext[type].mtu_get();
+}
+
+/**
+ * @brief Attempts to retrieve the maximum transmission unit (MTU) for the receiver device.
+ *
+ * @param dev Pointer to the device structure.
+ *
+ * @return Always returns 0.
+ */
+static int mbox_mhuv3_receiver_mtu_get(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	LOG_ERR("Trying to get maximum transmit units on a MBX MHUv3 frame");
+
+	return 0;
+}
+
+/**
+ * @brief Retrieves the Maximum Transmission Unit (MTU) for the MHUv3 device.
+ *
+ * This function determines the MTU based on the frame type (PBX or MBX) and calls
+ * the appropriate function to retrieve the MTU for the sender or receiver.
+ *
+ * @param dev Pointer to the device structure.
+ *
+ * @return The MTU value for the sender or receiver, depending on the frame type.
+ */
+static int mbox_mhuv3_mtu_get(const struct device *dev)
+{
+	struct mbox_mhuv3_data *data = dev->data;
+
+	if (data->frame == PBX_FRAME) {
+		return mbox_mhuv3_sender_mtu_get(dev);
+	}
+
+	return mbox_mhuv3_receiver_mtu_get(dev);
+}
+
+/**
+ * @brief Retrieves the maximum number of channels available in the MHUv3 device.
+ *
+ * @param dev Pointer to the device structure.
+ *
+ * @return The number of available channels for the MHUv3 device.
+ */
+static uint32_t mbox_mhuv3_max_channels_get(const struct device *dev)
+{
+	struct mbox_mhuv3_data *data = dev->data;
+
+	return data->num_chans;
+}
+
+/**
+ * @brief Enables or disables a channel based on the MHUv3 frame type.
+ *
+ * This function handles enabling or disabling the transmission (TX) or reception (RX)
+ * functionality of a channel.
+ *
+ * @param dev The device handle representing the MHUv3 system.
+ * @param channel_id The ID of the channel to enable or disable.
+ * @param enabled Boolean flag to enable (true) or disable (false) the channel.
+ *
+ * @return 0 on success, or a negative error code on failure.
+ */
+static int mbox_mhuv3_set_enabled(const struct device *dev,
+				  mbox_channel_id_t channel_id, bool enabled)
+{
+	struct mbox_mhuv3_data *data = dev->data;
+	struct mbox_mhuv3_channel *chan = mbox_mhuv3_get_channel(dev, channel_id);
+	int ret;
+
+	if (!chan) {
+		return -EINVAL;
+	}
+
+	if (data->frame == PBX_FRAME) {
+		if (enabled) {
+			ret = chan->ops->tx_enable(dev, chan);
+		} else {
+			ret = chan->ops->tx_disable(dev, chan);
+		}
+	} else {
+		if (enabled) {
+			ret = chan->ops->rx_enable(dev, chan);
+		} else {
+			ret = chan->ops->rx_disable(dev, chan);
+		}
+	}
+
+	return ret;
+}
+
+static DEVICE_API(mbox, mhuv3_driver_api) = {
+	.send = mbox_mhuv3_send_data,
+	.register_callback = mbox_mhuv3_register_callback,
+	.mtu_get = mbox_mhuv3_mtu_get,
+	.max_channels_get = mbox_mhuv3_max_channels_get,
+	.set_enabled = mbox_mhuv3_set_enabled,
+};
+
+#define MHUV3_INIT(n)							\
+									\
+static void mbox_mhuv3_cmb_irq_config_##n(const struct device *dev)	\
+{									\
+	IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, combined, irq),		\
+		    DT_INST_IRQ_BY_NAME(n, combined, priority),		\
+		    mbox_mhuv3_comb_interrupt,				\
+		    DEVICE_DT_INST_GET(n),				\
+		    0);							\
+	irq_enable(DT_INST_IRQ_BY_NAME(n, combined, irq));		\
+}									\
+									\
+static const struct mbox_mhuv3_config mhuv3_cfg_##n = {			\
+	(struct ctrl_page *)DT_INST_REG_ADDR(n),			\
+	DT_INST_REG_ADDR(n),						\
+	mbox_mhuv3_cmb_irq_config_##n,					\
+};									\
+									\
+struct mbox_mhuv3_data mhuv3_data_##n;					\
+									\
+DEVICE_DT_INST_DEFINE(n,						\
+		      &mbox_mhuv3_init,					\
+		      NULL,						\
+		      &mhuv3_data_##n,					\
+		      &mhuv3_cfg_##n,					\
+		      POST_KERNEL,					\
+		      CONFIG_MBOX_INIT_PRIORITY,			\
+		      &mhuv3_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(MHUV3_INIT);
diff --git a/drivers/mbox/mbox_nxp_imx_mu.c b/drivers/mbox/mbox_nxp_imx_mu.c
index 830c3ec6648..8b5dfd3b738 100644
--- a/drivers/mbox/mbox_nxp_imx_mu.c
+++ b/drivers/mbox/mbox_nxp_imx_mu.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -21,6 +21,25 @@ LOG_MODULE_REGISTER(nxp_mbox_imx_mu);
 #define MU_MAX_CHANNELS 4
 #define MU_MBOX_SIZE    sizeof(uint32_t)
 
+/*
+ * Arrays to translate the channel number to Generic Interrupt Mask for mu driver.
+ * The kMU_GenInt[0..3]Flag comes from MU driver header mu.h.
+ * There are more MU drivers implementations. For the `mu` driver
+ * the kMU_GenInt0Flag goes from 3 to 0 relative bit for the
+ * `mu1` driver kMU_GenInt0Flag goes from 0 to 3.
+ * Same for kMU_GenInt0InterruptTrigger and kMU_Rx0FullFlag.
+ * Therefore use this mapping table to select correct mask based on channel index.
+ */
+const static uint32_t g_gen_int_pend_mask[MU_MAX_CHANNELS] = {kMU_GenInt0Flag, kMU_GenInt1Flag,
+							      kMU_GenInt2Flag, kMU_GenInt3Flag};
+
+const static uint32_t g_gen_int_trig_mask[MU_MAX_CHANNELS] = {
+	kMU_GenInt0InterruptTrigger, kMU_GenInt1InterruptTrigger, kMU_GenInt2InterruptTrigger,
+	kMU_GenInt3InterruptTrigger};
+
+const static uint32_t g_rx_flag_mask[MU_MAX_CHANNELS] = {kMU_Rx0FullFlag, kMU_Rx1FullFlag,
+							 kMU_Rx2FullFlag, kMU_Rx3FullFlag};
+
 struct nxp_imx_mu_data {
 	mbox_callback_t cb[MU_MAX_CHANNELS];
 	void *user_data[MU_MAX_CHANNELS];
@@ -42,11 +61,11 @@ static int nxp_imx_mu_send(const struct device *dev, uint32_t channel, const str
 
 	/* Signalling mode. */
 	if (msg == NULL) {
-		return MU_TriggerInterrupts(cfg->base, kMU_GenInt0InterruptTrigger >> channel);
+		return MU_TriggerInterrupts(cfg->base, g_gen_int_trig_mask[channel]);
 	}
 
 	/* Data transfer mode. */
-	if (msg->size != MU_MBOX_SIZE) {
+	if (msg->size > MU_MBOX_SIZE) {
 		/* We can only send this many bytes at a time. */
 		return -EMSGSIZE;
 	}
@@ -159,10 +178,13 @@ static void handle_irq(const struct device *dev)
 {
 	struct nxp_imx_mu_data *data = dev->data;
 	const struct nxp_imx_mu_config *config = dev->config;
-	const uint32_t flag = MU_GetStatusFlags(config->base);
+	const uint32_t flags = MU_GetStatusFlags(config->base);
 
 	for (int i_channel = 0; i_channel < MU_MAX_CHANNELS; i_channel++) {
-		if ((flag & (kMU_Rx0FullFlag >> i_channel)) == (kMU_Rx0FullFlag >> i_channel)) {
+		const uint32_t rx_int_mask = g_rx_flag_mask[i_channel];
+		const uint32_t gen_int_mask = g_gen_int_pend_mask[i_channel];
+
+		if ((flags & rx_int_mask) == rx_int_mask) {
 			data->received_data = MU_ReceiveMsgNonBlocking(config->base, i_channel);
 			struct mbox_msg msg = {(const void *)&data->received_data, MU_MBOX_SIZE};
 
@@ -170,9 +192,8 @@ static void handle_irq(const struct device *dev)
 				data->cb[i_channel](dev, i_channel, data->user_data[i_channel],
 						    &msg);
 			}
-		} else if ((flag & (kMU_GenInt0Flag >> i_channel)) ==
-			   (kMU_GenInt0Flag >> i_channel)) {
-			MU_ClearStatusFlags(config->base, (kMU_GenInt0Flag >> i_channel));
+		} else if ((flags & gen_int_mask) == gen_int_mask) {
+			MU_ClearStatusFlags(config->base, gen_int_mask);
 			if (data->cb[i_channel]) {
 				data->cb[i_channel](dev, i_channel, data->user_data[i_channel],
 						    NULL);
diff --git a/drivers/mbox/mbox_nxp_mailbox.c b/drivers/mbox/mbox_nxp_mailbox.c
index 5f0e2f38a28..807d78efdf9 100644
--- a/drivers/mbox/mbox_nxp_mailbox.c
+++ b/drivers/mbox/mbox_nxp_mailbox.c
@@ -21,8 +21,11 @@ LOG_MODULE_REGISTER(nxp_mbox_mailbox);
 #define MAILBOX_MAX_CHANNELS 4
 #define MAILBOX_MBOX_SIZE    3
 
-#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES))
-#ifdef LPC55S69_cm33_core0_SERIES
+#if (defined(LPC55S69_cm33_core0_SERIES) || defined(LPC55S69_cm33_core1_SERIES) ||                 \
+defined(CONFIG_SOC_SERIES_MCXN))
+#if (defined(LPC55S69_cm33_core0_SERIES) || defined(MCXN947_cm33_core0_SERIES) ||                  \
+defined(MCXN946_cm33_core0_SERIES) || defined(MCXN547_cm33_core0_SERIES) ||                   \
+defined(MCXN546_cm33_core0_SERIES))
 #define MAILBOX_ID_THIS_CPU  kMAILBOX_CM33_Core0
 #define MAILBOX_ID_OTHER_CPU kMAILBOX_CM33_Core1
 #else
diff --git a/drivers/mbox/mbox_renesas_rz_mhu.c b/drivers/mbox/mbox_renesas_rz_mhu.c
new file mode 100644
index 00000000000..67753474170
--- /dev/null
+++ b/drivers/mbox/mbox_renesas_rz_mhu.c
@@ -0,0 +1,329 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_rz_mhu_mbox
+
+#include <stdint.h>
+#include <string.h>
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/mbox.h>
+#include <zephyr/logging/log.h>
+
+#include "r_mhu_ns.h"
+
+LOG_MODULE_REGISTER(mbox_renesas_rz_mhu, CONFIG_MBOX_LOG_LEVEL);
+
+/* Global dummy value required for FSP driver implementation */
+#define MHU_SHM_START_ADDR 0
+const uint32_t *const __mhu_shmem_start = (uint32_t *)MHU_SHM_START_ADDR;
+
+/* FSP interrupt handlers. */
+void mhu_ns_int_isr(void);
+
+static volatile uint32_t callback_msg;
+static void mhu_ns_callback(mhu_callback_args_t *p_args)
+{
+	callback_msg = p_args->msg;
+}
+
+struct mbox_rz_mhu_config {
+	const mhu_api_t *fsp_api;
+	uint16_t mhu_ch_size;
+	/* Number of supported channels */
+	uint32_t num_channels;
+	/* TX channels mask */
+	uint32_t tx_mask;
+	/* RX channels mask */
+	uint32_t rx_mask;
+};
+
+struct mbox_rz_mhu_data {
+	const struct device *dev;
+	mhu_ns_instance_ctrl_t *fsp_ctrl;
+	mhu_cfg_t *fsp_cfg;
+	mbox_callback_t cb;
+	void *user_data;
+	uint32_t channel_id;
+};
+
+/**
+ * @brief Return true if the channel of the MBOX device is an inbound channel.
+ */
+static inline bool is_rx_channel_valid(const struct device *dev, uint32_t ch)
+{
+	const struct mbox_rz_mhu_config *config = dev->config;
+
+	return ((ch < config->num_channels) && (config->rx_mask & BIT(ch)));
+}
+
+/**
+ * @brief Return true if the channel of the MBOX device is an outbound channel.
+ */
+static inline bool is_tx_channel_valid(const struct device *dev, uint32_t ch)
+{
+	const struct mbox_rz_mhu_config *config = dev->config;
+
+	return ((ch < config->num_channels) && (config->tx_mask & BIT(ch)));
+}
+
+/**
+ * Interrupt handler
+ */
+static void mbox_rz_mhu_isr(const struct device *dev)
+{
+	struct mbox_rz_mhu_data *data = dev->data;
+	struct mbox_msg msg;
+
+	mhu_ns_int_isr();
+	if (data->cb && data->fsp_cfg->p_shared_memory) {
+		uint32_t local_msg = callback_msg;
+
+		msg.data = &local_msg;
+
+		/* On the receiving end, the size of the message is always 4 bytes since the FSP MHU
+		 * driver requires the message to be of type uint32_t
+		 */
+		msg.size = sizeof(local_msg);
+
+		data->cb(dev, data->channel_id, data->user_data, &msg);
+	}
+}
+
+/**
+ * @brief Try to send a message over the MBOX device.
+ */
+static int mbox_rz_mhu_send(const struct device *dev, mbox_channel_id_t channel_id,
+			    const struct mbox_msg *msg)
+{
+	const struct mbox_rz_mhu_config *config = dev->config;
+	struct mbox_rz_mhu_data *data = dev->data;
+	fsp_err_t fsp_err = FSP_SUCCESS;
+
+	/* FSP driver implementation requires the message to be of type uint32_t */
+	uint32_t message = 0;
+
+	if (!is_tx_channel_valid(dev, channel_id)) {
+		if (!is_rx_channel_valid(dev, channel_id)) {
+			/* Channel is neither RX nor TX */
+			LOG_ERR("Invalid MBOX channel number: %d", channel_id);
+			return -EINVAL;
+		}
+
+		/* Channel is a RX channel, but this function only accepts TX */
+		LOG_ERR("Channel ID %d is a RX channel, but only TX channels are allowed",
+			channel_id);
+		return -ENOSYS;
+	}
+
+	if (msg != NULL) {
+		/* Maximum size allowed is 4 bytes */
+		if (msg->size > config->mhu_ch_size) {
+			LOG_ERR("Size %d is not valid. Maximum size is 4 bytes", msg->size);
+			return -EMSGSIZE;
+		}
+
+		if (msg->data && msg->size) {
+			/* Copy message */
+			memcpy(&message, msg->data, msg->size);
+		} else {
+			/* Clear Message */
+			message = 0;
+		}
+	} else {
+		message = 0;
+	}
+
+	if (data->fsp_cfg->p_shared_memory) {
+
+#if CONFIG_MBOX_BUSY_WAIT_TIMEOUT_US > 0
+		/* The FSP MHU "msgSend" API continuously polls until the
+		 * previous message is consumed before sending a new one. To avoid
+		 * blocking indefinitely, we need to check if the remote clears the message
+		 * within the allowed time before sending a new one
+		 */
+		if (MHU_SEND_TYPE_MSG == data->fsp_ctrl->send_type) {
+			if (data->fsp_ctrl->p_regs->MSG_INT_STSn != 0) {
+				k_busy_wait(CONFIG_MBOX_BUSY_WAIT_TIMEOUT_US);
+				if (data->fsp_ctrl->p_regs->MSG_INT_STSn != 0) {
+					LOG_ERR("Remote is busy");
+					return -EBUSY;
+				}
+			}
+		} else {
+			if (data->fsp_ctrl->p_regs->RSP_INT_STSn != 0) {
+				k_busy_wait(CONFIG_MBOX_BUSY_WAIT_TIMEOUT_US);
+				if (data->fsp_ctrl->p_regs->RSP_INT_STSn != 0) {
+					LOG_ERR("Remote is busy");
+					return -EBUSY;
+				}
+			}
+		}
+#endif
+
+		/* Send message to shared memory, this will also invoke interrupt on the receiving
+		 * core
+		 */
+		fsp_err = config->fsp_api->msgSend(data->fsp_ctrl, message);
+	}
+
+	if (fsp_err) {
+		LOG_ERR("Message send failed");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Register a callback function on a channel for incoming messages.
+ */
+static int mbox_rz_mhu_reg_callback(const struct device *dev, mbox_channel_id_t channel_id,
+				    mbox_callback_t cb, void *user_data)
+{
+	struct mbox_rz_mhu_data *data = dev->data;
+
+	if (!is_rx_channel_valid(dev, channel_id)) {
+		if (!is_tx_channel_valid(dev, channel_id)) {
+			/* Channel is neither RX nor TX */
+			LOG_ERR("Invalid MBOX channel number: %d", channel_id);
+			return -EINVAL;
+		}
+
+		/* Channel is a TX channel, but this function only accepts RX */
+		LOG_ERR("Channel ID %d is a TX channel, but only RX channels are allowed",
+			channel_id);
+		return -ENOSYS;
+	}
+
+	if (!cb) {
+		LOG_ERR("Must provide callback");
+		return -EINVAL;
+	}
+
+	data->cb = cb;
+	data->user_data = user_data;
+	data->channel_id = channel_id;
+
+	return 0;
+}
+
+/**
+ * @brief Initialize the module.
+ */
+static int mbox_rz_mhu_init(const struct device *dev)
+{
+	const struct mbox_rz_mhu_config *config = dev->config;
+	struct mbox_rz_mhu_data *data = dev->data;
+	fsp_err_t fsp_err = FSP_SUCCESS;
+
+	fsp_err = config->fsp_api->open(data->fsp_ctrl, data->fsp_cfg);
+
+	if (fsp_err) {
+		LOG_ERR("MBOX initialization failed");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Enable (disable) interrupts and callbacks for inbound channels.
+ */
+static int mbox_rz_mhu_set_enabled(const struct device *dev, mbox_channel_id_t channel_id,
+				   bool enabled)
+{
+	if (!is_rx_channel_valid(dev, channel_id)) {
+		if (!is_tx_channel_valid(dev, channel_id)) {
+			/* Channel is neither RX nor TX */
+			LOG_ERR("Invalid MBOX channel number: %d", channel_id);
+			return -EINVAL;
+		}
+
+		/* Channel is a TX channel, but this function only accepts RX */
+		LOG_ERR("Channel ID %d is a TX channel, but only RX channels are allowed",
+			channel_id);
+		return -ENOSYS;
+	}
+
+	ARG_UNUSED(enabled);
+	return 0;
+}
+
+/**
+ * @brief Return the maximum number of bytes possible in an outbound message.
+ */
+static int mbox_rz_mhu_mtu_get(const struct device *dev)
+{
+	const struct mbox_rz_mhu_config *config = dev->config;
+
+	return config->mhu_ch_size;
+}
+
+/**
+ * @brief Return the maximum number of channels.
+ */
+static uint32_t mbox_rz_mhu_max_channels_get(const struct device *dev)
+{
+	const struct mbox_rz_mhu_config *config = dev->config;
+
+	return config->num_channels;
+}
+
+static DEVICE_API(mbox, mbox_rz_mhu_driver_api) = {
+	.send = mbox_rz_mhu_send,
+	.register_callback = mbox_rz_mhu_reg_callback,
+	.mtu_get = mbox_rz_mhu_mtu_get,
+	.max_channels_get = mbox_rz_mhu_max_channels_get,
+	.set_enabled = mbox_rz_mhu_set_enabled,
+};
+
+/*
+ * ************************* DRIVER REGISTER SECTION ***************************
+ */
+
+#define MHU_RZG_IRQ_CONNECT(idx, irq_name, isr)                                                    \
+	do {                                                                                       \
+		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, irq_name, irq),                               \
+			    DT_INST_IRQ_BY_NAME(idx, irq_name, priority), isr,                     \
+			    DEVICE_DT_INST_GET(idx), 0);                                           \
+		irq_enable(DT_INST_IRQ_BY_NAME(idx, irq_name, irq));                               \
+	} while (0)
+
+#define MHU_RZG_CONFIG_FUNC(idx) MHU_RZG_IRQ_CONNECT(idx, mhuns, mbox_rz_mhu_isr);
+
+#define MHU_RZG_INIT(idx)                                                                          \
+	static mhu_ns_instance_ctrl_t g_mhu_ns##idx##_ctrl;                                        \
+	static mhu_cfg_t g_mhu_ns##idx##_cfg = {                                                   \
+		.channel = DT_INST_PROP(idx, channel),                                             \
+		.rx_ipl = DT_INST_IRQ_BY_NAME(idx, mhuns, priority),                               \
+		.rx_irq = DT_INST_IRQ_BY_NAME(idx, mhuns, irq),                                    \
+		.p_callback = mhu_ns_callback,                                                     \
+		.p_context = NULL,                                                                 \
+		.p_shared_memory = (void *)COND_CODE_1(DT_INST_NODE_HAS_PROP(idx, shared_memory),  \
+		      (DT_REG_ADDR(DT_INST_PHANDLE(idx, shared_memory))), (NULL)),                 \
+	};                                                                                         \
+	static const struct mbox_rz_mhu_config mbox_rz_mhu_config_##idx = {                        \
+		.fsp_api = &g_mhu_ns_on_mhu_ns,                                                    \
+		.mhu_ch_size = 4,                                                                  \
+		.num_channels = DT_INST_PROP(idx, channels_count),                                 \
+		.tx_mask = DT_INST_PROP(idx, tx_mask),                                             \
+		.rx_mask = DT_INST_PROP(idx, rx_mask),                                             \
+	};                                                                                         \
+	static struct mbox_rz_mhu_data mbox_rz_mhu_data_##idx = {                                  \
+		.dev = DEVICE_DT_INST_GET(idx),                                                    \
+		.fsp_ctrl = &g_mhu_ns##idx##_ctrl,                                                 \
+		.fsp_cfg = &g_mhu_ns##idx##_cfg,                                                   \
+	};                                                                                         \
+	static int mbox_rz_mhu_init_##idx(const struct device *dev)                                \
+	{                                                                                          \
+		MHU_RZG_CONFIG_FUNC(idx)                                                           \
+		return mbox_rz_mhu_init(dev);                                                      \
+	}                                                                                          \
+	DEVICE_DT_INST_DEFINE(idx, mbox_rz_mhu_init_##idx, NULL, &mbox_rz_mhu_data_##idx,          \
+			      &mbox_rz_mhu_config_##idx, PRE_KERNEL_1,                             \
+			      CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &mbox_rz_mhu_driver_api)
+
+DT_INST_FOREACH_STATUS_OKAY(MHU_RZG_INIT);
diff --git a/drivers/mbox/mbox_ti_omap.c b/drivers/mbox/mbox_ti_omap.c
new file mode 100644
index 00000000000..847d9106282
--- /dev/null
+++ b/drivers/mbox/mbox_ti_omap.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated.
+ *
+ * TI OMAP Mailbox driver for Zephyr's MBOX model.
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/mbox.h>
+#include <zephyr/irq.h>
+#include <zephyr/spinlock.h>
+#define LOG_LEVEL CONFIG_MBOX_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(ti_omap_mailbox);
+
+#define DT_DRV_COMPAT ti_omap_mailbox
+
+#define MAILBOX_IRQ_NEWMSG(m)  (1 << (2 * (m)))
+#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))
+#define OMAP_MAILBOX_NUM_MSGS  16
+#define MAILBOX_MAX_CHANNELS   16
+#define OMAP_MAILBOX_NUM_USERS 4
+#define MAILBOX_MBOX_SIZE      sizeof(uint32_t)
+
+#define DEV_CFG(_dev)     ((const struct omap_mailbox_config *)(_dev)->config)
+#define DEV_DATA(_dev)    ((struct omap_mailbox_data *)(_dev)->data)
+#define DEV_REG_BASE(dev) ((struct omap_mailbox_regs *)DEVICE_MMIO_NAMED_GET(dev, reg_base))
+
+struct omap_mailbox_data {
+	DEVICE_MMIO_NAMED_RAM(reg_base);
+	mbox_callback_t cb[MAILBOX_MAX_CHANNELS];
+	void *user_data[MAILBOX_MAX_CHANNELS];
+	bool channel_enable[MAILBOX_MAX_CHANNELS];
+	uint32_t received_data;
+	struct k_spinlock lock;
+};
+
+struct omap_mailbox_config {
+	DEVICE_MMIO_NAMED_ROM(reg_base);
+	uint32_t irq;
+	uint32_t usr_id;
+};
+
+struct omap_mailbox_irq_regs {
+	uint32_t status_raw;
+	uint32_t status_clear;
+	uint32_t enable_set;
+	uint32_t enable_clear;
+};
+
+struct omap_mailbox_regs {
+	uint32_t revision;
+	uint32_t __pad0[3];
+	uint32_t sysconfig;
+	uint32_t __pad1[11];
+	uint32_t message[OMAP_MAILBOX_NUM_MSGS];
+	uint32_t fifo_status[OMAP_MAILBOX_NUM_MSGS];
+	uint32_t msg_status[OMAP_MAILBOX_NUM_MSGS];
+	struct omap_mailbox_irq_regs irq_regs[OMAP_MAILBOX_NUM_USERS];
+};
+
+static void omap_mailbox_isr(const struct device *dev)
+{
+	volatile struct omap_mailbox_regs *regs = DEV_REG_BASE(dev);
+	const struct omap_mailbox_config *cfg = DEV_CFG(dev);
+	struct omap_mailbox_data *data = DEV_DATA(dev);
+
+	uint32_t irq_enabled = regs->irq_regs[cfg->usr_id].enable_set;
+	uint32_t flags = regs->irq_regs[cfg->usr_id].status_clear;
+
+	regs->irq_regs[cfg->usr_id].enable_set = 0;
+
+	for (int i_channel = 0; i_channel < MAILBOX_MAX_CHANNELS; i_channel++) {
+		if (!data->channel_enable[i_channel]) {
+			continue;
+		}
+
+		if ((flags & MAILBOX_IRQ_NEWMSG(i_channel))) {
+			data->received_data = regs->message[i_channel];
+			struct mbox_msg msg = {
+				.data = (const void *)&data->received_data,
+				.size = MAILBOX_MBOX_SIZE,
+			};
+
+			if (data->cb[i_channel]) {
+				data->cb[i_channel](dev, i_channel, data->user_data[i_channel],
+						    &msg);
+			}
+		}
+	}
+
+	regs->irq_regs[cfg->usr_id].status_clear = flags;
+	regs->irq_regs[cfg->usr_id].enable_set = irq_enabled;
+}
+
+static int omap_mailbox_send(const struct device *dev, uint32_t channel, const struct mbox_msg *msg)
+{
+	uint32_t __aligned(4) data32;
+
+	volatile struct omap_mailbox_regs *regs = DEV_REG_BASE(dev);
+	struct omap_mailbox_data *data = DEV_DATA(dev);
+	k_spinlock_key_t key;
+
+	if (channel >= MAILBOX_MAX_CHANNELS) {
+		return -EINVAL;
+	}
+
+	if (regs->fifo_status[channel]) {
+		return -EBUSY;
+	}
+
+	key = k_spin_lock(&data->lock);
+	if (!msg) {
+		regs->message[channel] = 0;
+		k_spin_unlock(&data->lock, key);
+		return 0;
+	}
+
+	if (msg->size > MAILBOX_MBOX_SIZE) {
+		k_spin_unlock(&data->lock, key);
+		return -EMSGSIZE;
+	}
+
+	memcpy(&data32, msg->data, msg->size);
+	regs->message[channel] = data32;
+	k_spin_unlock(&data->lock, key);
+
+	return 0;
+}
+
+static int omap_mailbox_register_callback(const struct device *dev, uint32_t channel,
+					  mbox_callback_t cb, void *user_data)
+{
+	struct omap_mailbox_data *data = DEV_DATA(dev);
+	k_spinlock_key_t key;
+
+	if (channel >= MAILBOX_MAX_CHANNELS) {
+		return -EINVAL;
+	}
+
+	key = k_spin_lock(&data->lock);
+	data->cb[channel] = cb;
+	data->user_data[channel] = user_data;
+	k_spin_unlock(&data->lock, key);
+
+	return 0;
+}
+
+static int omap_mailbox_mtu_get(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return MAILBOX_MBOX_SIZE;
+}
+
+static uint32_t omap_mailbox_max_channels_get(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return MAILBOX_MAX_CHANNELS;
+}
+
+static int omap_mailbox_set_enabled(const struct device *dev, uint32_t channel, bool enable)
+{
+	const struct omap_mailbox_config *cfg = DEV_CFG(dev);
+	struct omap_mailbox_data *data = DEV_DATA(dev);
+	volatile struct omap_mailbox_regs *regs;
+	k_spinlock_key_t key;
+	uint32_t irqstatus;
+
+	if (channel >= MAILBOX_MAX_CHANNELS) {
+		return -EINVAL;
+	}
+
+	if (enable && data->channel_enable[channel]) {
+		return -EALREADY;
+	}
+
+	key = k_spin_lock(&data->lock);
+	regs = DEV_REG_BASE(dev);
+	irqstatus = regs->irq_regs[cfg->usr_id].enable_set;
+
+	if (enable) {
+		irqstatus |= MAILBOX_IRQ_NEWMSG(channel);
+	} else {
+		irqstatus &= ~MAILBOX_IRQ_NEWMSG(channel);
+	}
+
+	regs->irq_regs[cfg->usr_id].enable_set = irqstatus;
+	data->channel_enable[channel] = enable;
+
+	if (enable) {
+		irq_enable(cfg->irq);
+	} else {
+		irq_disable(cfg->irq);
+	}
+
+	k_spin_unlock(&data->lock, key);
+
+	return 0;
+}
+
+static DEVICE_API(mbox, omap_mailbox_driver_api) = {
+	.send = omap_mailbox_send,
+	.register_callback = omap_mailbox_register_callback,
+	.mtu_get = omap_mailbox_mtu_get,
+	.max_channels_get = omap_mailbox_max_channels_get,
+	.set_enabled = omap_mailbox_set_enabled,
+};
+
+#define MAILBOX_INSTANCE_DEFINE(idx)								\
+	static struct omap_mailbox_data omap_mailbox_##idx##_data;				\
+	const static struct omap_mailbox_config omap_mailbox_##idx##_config = {			\
+		DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(idx)),				\
+		.irq = DT_INST_IRQN(idx),							\
+		.usr_id = DT_INST_PROP(idx, usr_id),						\
+	};											\
+	static int omap_mailbox_##idx##_init(const struct device *dev)				\
+	{											\
+		DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE);				\
+		IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(idx, priority), omap_mailbox_isr,	\
+			    DEVICE_DT_INST_GET(idx),						\
+			    COND_CODE_1(DT_INST_IRQ_HAS_CELL(idx, flags),			\
+					(DT_INST_IRQ(idx, flags)), (0)));			\
+		return 0;									\
+	}											\
+	DEVICE_DT_INST_DEFINE(idx, omap_mailbox_##idx##_init, NULL, &omap_mailbox_##idx##_data,	\
+			      &omap_mailbox_##idx##_config, POST_KERNEL,	\
+			      CONFIG_MBOX_INIT_PRIORITY, &omap_mailbox_driver_api)
+
+DT_INST_FOREACH_STATUS_OKAY(MAILBOX_INSTANCE_DEFINE)
diff --git a/drivers/mdio/CMakeLists.txt b/drivers/mdio/CMakeLists.txt
index 779ba7ed5ef..fc3ce620c20 100644
--- a/drivers/mdio/CMakeLists.txt
+++ b/drivers/mdio/CMakeLists.txt
@@ -17,3 +17,6 @@ zephyr_library_sources_ifdef(CONFIG_MDIO_INFINEON_XMC4XXX mdio_xmc4xxx.c)
 zephyr_library_sources_ifdef(CONFIG_MDIO_NXP_ENET_QOS	mdio_nxp_enet_qos.c)
 zephyr_library_sources_ifdef(CONFIG_MDIO_DWCXGMAC	mdio_dwcxgmac.c)
 zephyr_library_sources_ifdef(CONFIG_MDIO_RENESAS_RA	mdio_renesas_ra.c)
+zephyr_library_sources_ifdef(CONFIG_MDIO_LAN865X	mdio_lan865x.c)
+zephyr_library_sources_ifdef(CONFIG_MDIO_SENSRY_SY1XX   mdio_sy1xx.c)
+zephyr_library_sources_ifdef(CONFIG_MDIO_XILINX_AXI_ENET        mdio_xilinx_axienet.c)
diff --git a/drivers/mdio/Kconfig b/drivers/mdio/Kconfig
index 77dc4d34111..658bbe78b7b 100644
--- a/drivers/mdio/Kconfig
+++ b/drivers/mdio/Kconfig
@@ -38,6 +38,9 @@ source "drivers/mdio/Kconfig.xmc4xxx"
 source "drivers/mdio/Kconfig.nxp_enet_qos"
 source "drivers/mdio/Kconfig.dwcxgmac"
 source "drivers/mdio/Kconfig.renesas_ra"
+source "drivers/mdio/Kconfig.lan865x"
+source "drivers/mdio/Kconfig.sy1xx"
+source "drivers/mdio/Kconfig.xilinx_axienet"
 
 config MDIO_INIT_PRIORITY
 	int "Init priority"
diff --git a/drivers/mdio/Kconfig.lan865x b/drivers/mdio/Kconfig.lan865x
new file mode 100644
index 00000000000..8cf7f0c0e83
--- /dev/null
+++ b/drivers/mdio/Kconfig.lan865x
@@ -0,0 +1,20 @@
+# Copyright 2024 Microchip Technology Inc
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig MDIO_LAN865X
+	bool "LAN865X MDIO driver"
+	default y
+	depends on DT_HAS_MICROCHIP_LAN865X_MDIO_ENABLED
+	depends on ETH_LAN865X
+	help
+	  Enable LAN865X MDIO driver.
+
+if MDIO_LAN865X
+
+config MDIO_LAN865X_INIT_PRIORITY
+	int "LAN865X MDIO init priority"
+	default 81
+	help
+	  LAN865X MDIO device driver initialization priority.
+
+endif
diff --git a/drivers/mdio/Kconfig.stm32_hal b/drivers/mdio/Kconfig.stm32_hal
index e92573e3234..e54844a4f70 100644
--- a/drivers/mdio/Kconfig.stm32_hal
+++ b/drivers/mdio/Kconfig.stm32_hal
@@ -5,8 +5,8 @@
 config MDIO_ST_STM32_HAL
 	bool "STM32 MDIO controller driver"
 	default y
-	depends on ETH_STM32_HAL_API_V2
 	depends on DT_HAS_ST_STM32_MDIO_ENABLED
+	depends on ETH_STM32_HAL
 	select PINCTRL
 	help
 	  Enable STM32 MDIO support.
diff --git a/drivers/mdio/Kconfig.sy1xx b/drivers/mdio/Kconfig.sy1xx
new file mode 100644
index 00000000000..be2b4105c25
--- /dev/null
+++ b/drivers/mdio/Kconfig.sy1xx
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+config MDIO_SENSRY_SY1XX
+	bool "Sensry SY1XX MDIO driver"
+	select PINCTRL
+	depends on DT_HAS_SENSRY_SY1XX_MDIO_ENABLED
+	default y
+	help
+	  Enable Sensry SY1xx SOC Family MDIO driver.
diff --git a/drivers/mdio/Kconfig.xilinx_axienet b/drivers/mdio/Kconfig.xilinx_axienet
new file mode 100644
index 00000000000..96bf7dd3945
--- /dev/null
+++ b/drivers/mdio/Kconfig.xilinx_axienet
@@ -0,0 +1,9 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+config MDIO_XILINX_AXI_ENET
+	bool "Xilinx AXI Ethernet MDIO driver"
+	default y
+	depends on DT_HAS_XLNX_AXI_ETHERNET_1_00_A_MDIO_ENABLED
+	help
+	  Enable Xilinx AXI Ethernet MDIO bus driver.
diff --git a/drivers/mdio/mdio_esp32.c b/drivers/mdio/mdio_esp32.c
index 46de13f3fe7..9079d49e741 100644
--- a/drivers/mdio/mdio_esp32.c
+++ b/drivers/mdio/mdio_esp32.c
@@ -16,6 +16,8 @@
 #include <esp_mac.h>
 #include <hal/emac_hal.h>
 #include <hal/emac_ll.h>
+#include <soc/rtc.h>
+#include <clk_ctrl_os.h>
 
 LOG_MODULE_REGISTER(mdio_esp32, CONFIG_MDIO_LOG_LEVEL);
 
@@ -86,6 +88,35 @@ static int mdio_esp32_write(const struct device *dev, uint8_t prtad,
 	return mdio_transfer(dev, prtad, regad, true, data, NULL);
 }
 
+#if DT_INST_NODE_HAS_PROP(0, ref_clk_output_gpios)
+static int emac_config_apll_clock(void)
+{
+	uint32_t expt_freq = MHZ(50);
+	uint32_t real_freq = 0;
+	esp_err_t ret = periph_rtc_apll_freq_set(expt_freq, &real_freq);
+
+	if (ret == ESP_ERR_INVALID_ARG) {
+		LOG_ERR("Set APLL clock coefficients failed");
+		return -EIO;
+	}
+
+	if (ret == ESP_ERR_INVALID_STATE) {
+		LOG_INF("APLL is occupied already, it is working at %d Hz", real_freq);
+	}
+
+	/* If the difference of real APLL frequency
+	 * is not within 50 ppm, i.e. 2500 Hz,
+	 * the APLL is unavailable
+	 */
+	if (abs((int)real_freq - (int)expt_freq) > 2500) {
+		LOG_ERR("The APLL is working at an unusable frequency");
+		return -EIO;
+	}
+
+	return 0;
+}
+#endif
+
 static int mdio_esp32_initialize(const struct device *dev)
 {
 	const struct mdio_esp32_dev_config *const cfg = dev->config;
@@ -113,6 +144,24 @@ static int mdio_esp32_initialize(const struct device *dev)
 	/* Only the mac registers are required for MDIO */
 	dev_data->hal.mac_regs = &EMAC_MAC;
 
+#if DT_INST_NODE_HAS_PROP(0, ref_clk_output_gpios)
+	emac_hal_init(&dev_data->hal, NULL, NULL, NULL);
+	emac_hal_iomux_init_rmii();
+	BUILD_ASSERT(DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 16 ||
+		DT_INST_GPIO_PIN(0, ref_clk_output_gpios) == 17,
+		"Only GPIO16/17 are allowed as a GPIO REF_CLK source!");
+	int ref_clk_gpio = DT_INST_GPIO_PIN(0, ref_clk_output_gpios);
+
+	emac_hal_iomux_rmii_clk_output(ref_clk_gpio);
+	emac_ll_clock_enable_rmii_output(dev_data->hal.ext_regs);
+	periph_rtc_apll_acquire();
+	res = emac_config_apll_clock();
+	if (res != 0) {
+		goto err;
+	}
+	rtc_clk_apll_enable(true);
+#endif
+
 	/* Init MDIO clock */
 	emac_hal_set_csr_clock_range(&dev_data->hal, esp_clk_apb_freq());
 
diff --git a/drivers/mdio/mdio_lan865x.c b/drivers/mdio/mdio_lan865x.c
new file mode 100644
index 00000000000..dc46100ce89
--- /dev/null
+++ b/drivers/mdio/mdio_lan865x.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2024 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(mdio_lan865x, CONFIG_MDIO_LOG_LEVEL);
+
+#define DT_DRV_COMPAT microchip_lan865x_mdio
+
+#include <stdint.h>
+#include <errno.h>
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/mdio.h>
+#include <zephyr/drivers/ethernet/eth_lan865x.h>
+
+struct mdio_lan865x_config {
+	const struct device *dev;
+};
+
+static void lan865x_mdio_bus_enable(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+}
+
+static void lan865x_mdio_bus_disable(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+}
+
+static int lan865x_mdio_c22_read(const struct device *dev, uint8_t prtad, uint8_t regad,
+				 uint16_t *data)
+{
+	const struct mdio_lan865x_config *const cfg = dev->config;
+
+	return eth_lan865x_mdio_c22_read(cfg->dev, prtad, regad, data);
+}
+
+static int lan865x_mdio_c22_write(const struct device *dev, uint8_t prtad, uint8_t regad,
+				  uint16_t data)
+{
+	const struct mdio_lan865x_config *const cfg = dev->config;
+
+	return eth_lan865x_mdio_c22_write(cfg->dev, prtad, regad, data);
+}
+
+static int lan865x_mdio_c45_read(const struct device *dev, uint8_t prtad, uint8_t devad,
+				 uint16_t regad, uint16_t *data)
+{
+	const struct mdio_lan865x_config *const cfg = dev->config;
+
+	return eth_lan865x_mdio_c45_read(cfg->dev, prtad, devad, regad, data);
+}
+
+static int lan865x_mdio_c45_write(const struct device *dev, uint8_t prtad, uint8_t devad,
+				  uint16_t regad, uint16_t data)
+{
+	const struct mdio_lan865x_config *const cfg = dev->config;
+
+	return eth_lan865x_mdio_c45_write(cfg->dev, prtad, devad, regad, data);
+}
+
+static DEVICE_API(mdio, mdio_lan865x_api) = {
+	.read = lan865x_mdio_c22_read,
+	.write = lan865x_mdio_c22_write,
+	.read_c45 = lan865x_mdio_c45_read,
+	.write_c45 = lan865x_mdio_c45_write,
+	.bus_enable = lan865x_mdio_bus_enable,
+	.bus_disable = lan865x_mdio_bus_disable,
+};
+
+#define MICROCHIP_LAN865X_MDIO_INIT(n)                                                             \
+	static const struct mdio_lan865x_config mdio_lan865x_config_##n = {                        \
+		.dev = DEVICE_DT_GET(DT_INST_PARENT(n)),                                           \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(n, NULL, NULL, NULL, &mdio_lan865x_config_##n, POST_KERNEL,          \
+			      CONFIG_MDIO_LAN865X_INIT_PRIORITY, &mdio_lan865x_api);
+
+DT_INST_FOREACH_STATUS_OKAY(MICROCHIP_LAN865X_MDIO_INIT)
diff --git a/drivers/mdio/mdio_nxp_enet.c b/drivers/mdio/mdio_nxp_enet.c
index 93b9eae216b..d71e3640cd4 100644
--- a/drivers/mdio/mdio_nxp_enet.c
+++ b/drivers/mdio/mdio_nxp_enet.c
@@ -59,9 +59,8 @@ static int nxp_enet_mdio_wait_xfer(const struct device *dev)
 	return 0;
 }
 
-/* MDIO Read API implementation */
-static int nxp_enet_mdio_read(const struct device *dev,
-			uint8_t prtad, uint8_t regad, uint16_t *read_data)
+static int mdio_transfer(const struct device *dev, uint8_t prtad, uint8_t regad,
+			 enum mdio_opcode op, bool c45, uint16_t data_in, uint16_t *data_out)
 {
 	struct nxp_enet_mdio_data *data = dev->data;
 	int ret;
@@ -71,25 +70,27 @@ static int nxp_enet_mdio_read(const struct device *dev,
 
 	/*
 	 * Clear the bit (W1C) that indicates MDIO transfer is ready to
-	 * prepare to wait for it to be set once this read is done
+	 * prepare to wait for it to be set once this transfer is done
 	 */
 	data->base->EIR = ENET_EIR_MII_MASK;
 
 	/*
 	 * Write MDIO frame to MII management register which will
-	 * send the read command and data out to the MDIO bus as this frame:
-	 * ST = start, 1 means start
-	 * OP = operation, 2 means read
+	 * send the command and data out to the MDIO bus as this frame:
+	 * ST = start, C22: 1 means start
+	 *             C45: 0 means start
+	 * OP = operation, see mdio_opcode for specifics on what the values are
 	 * PA = PHY/Port address
 	 * RA = Register/Device Address
 	 * TA = Turnaround, must be 2 to be valid
 	 * data = data to be written to the PHY register
 	 */
-	data->base->MMFR = ENET_MMFR_ST(0x1U) |
-				ENET_MMFR_OP(MDIO_OP_C22_READ) |
-				ENET_MMFR_PA(prtad) |
-				ENET_MMFR_RA(regad) |
-				ENET_MMFR_TA(0x2U);
+	data->base->MMFR = ENET_MMFR_ST(c45 ? 0x0U : 0x1U)
+					 | ENET_MMFR_OP(op)
+					 | ENET_MMFR_PA(prtad)
+					 | ENET_MMFR_RA(regad)
+					 | ENET_MMFR_TA(0x2U)
+					 | data_in;
 
 	ret = nxp_enet_mdio_wait_xfer(dev);
 	if (ret) {
@@ -98,7 +99,9 @@ static int nxp_enet_mdio_read(const struct device *dev,
 	}
 
 	/* The data is received in the same register that we wrote the command to */
-	*read_data = (data->base->MMFR & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT;
+	if (data_out != NULL) {
+		*data_out = (data->base->MMFR & ENET_MMFR_DATA_MASK) >> ENET_MMFR_DATA_SHIFT;
+	}
 
 	/* Clear the same bit as before because the event has been handled */
 	data->base->EIR = ENET_EIR_MII_MASK;
@@ -109,57 +112,49 @@ static int nxp_enet_mdio_read(const struct device *dev,
 	return ret;
 }
 
-/* MDIO Write API implementation */
-static int nxp_enet_mdio_write(const struct device *dev,
-			uint8_t prtad, uint8_t regad, uint16_t write_data)
+static int nxp_enet_mdio_read(const struct device *dev, uint8_t prtad, uint8_t regad,
+			      uint16_t *read_data)
 {
-	struct nxp_enet_mdio_data *data = dev->data;
-	int ret;
-
-	/* Only one MDIO bus operation attempt at a time */
-	(void)k_mutex_lock(&data->mdio_mutex, K_FOREVER);
+	return mdio_transfer(dev, prtad, regad, MDIO_OP_C22_READ, false, 0, read_data);
+}
 
-	/*
-	 * Clear the bit (W1C) that indicates MDIO transfer is ready to
-	 * prepare to wait for it to be set once this write is done
-	 */
-	data->base->EIR = ENET_EIR_MII_MASK;
+static int nxp_enet_mdio_write(const struct device *dev, uint8_t prtad, uint8_t regad,
+			       uint16_t write_data)
+{
+	return mdio_transfer(dev, prtad, regad, MDIO_OP_C22_WRITE, false, write_data, NULL);
+}
 
-	/*
-	 * Write MDIO frame to MII management register which will
-	 * send the write command and data out to the MDIO bus as this frame:
-	 * ST = start, 1 means start
-	 * OP = operation, 1 means write
-	 * PA = PHY/Port address
-	 * RA = Register/Device Address
-	 * TA = Turnaround, must be 2 to be valid
-	 * data = data to be written to the PHY register
-	 */
-	data->base->MMFR = ENET_MMFR_ST(0x1U) |
-				ENET_MMFR_OP(MDIO_OP_C22_WRITE) |
-				ENET_MMFR_PA(prtad) |
-				ENET_MMFR_RA(regad) |
-				ENET_MMFR_TA(0x2U) |
-				write_data;
+static int nxp_enet_mdio_read_c45(const struct device *dev, uint8_t prtad, uint8_t devad,
+				  uint16_t regad, uint16_t *data)
+{
+	int err;
 
-	ret = nxp_enet_mdio_wait_xfer(dev);
-	if (ret) {
-		(void)k_mutex_unlock(&data->mdio_mutex);
-		return ret;
+	err = mdio_transfer(dev, prtad, devad, MDIO_OP_C45_ADDRESS, true, regad, NULL);
+	if (!err) {
+		err = mdio_transfer(dev, prtad, devad, MDIO_OP_C45_READ, true, 0, data);
 	}
 
-	/* Clear the same bit as before because the event has been handled */
-	data->base->EIR = ENET_EIR_MII_MASK;
+	return err;
+}
 
-	/* This MDIO interaction is finished */
-	(void)k_mutex_unlock(&data->mdio_mutex);
+int nxp_enet_mdio_write_c45(const struct device *dev, uint8_t prtad, uint8_t devad, uint16_t regad,
+			    uint16_t data)
+{
+	int err;
 
-	return ret;
+	err = mdio_transfer(dev, prtad, devad, MDIO_OP_C45_ADDRESS, true, regad, NULL);
+	if (!err) {
+		err = mdio_transfer(dev, prtad, devad, MDIO_OP_C45_WRITE, true, data, NULL);
+	}
+
+	return err;
 }
 
 static DEVICE_API(mdio, nxp_enet_mdio_api) = {
 	.read = nxp_enet_mdio_read,
 	.write = nxp_enet_mdio_write,
+	.read_c45 = nxp_enet_mdio_read_c45,
+	.write_c45 = nxp_enet_mdio_write_c45
 };
 
 static void nxp_enet_mdio_isr_cb(const struct device *dev)
diff --git a/drivers/mdio/mdio_shell.c b/drivers/mdio/mdio_shell.c
index 856005bc4e1..e29d96e60a5 100644
--- a/drivers/mdio/mdio_shell.c
+++ b/drivers/mdio/mdio_shell.c
@@ -15,44 +15,37 @@
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(mdio_shell, CONFIG_LOG_DEFAULT_LEVEL);
 
-#if DT_HAS_COMPAT_STATUS_OKAY(atmel_sam_mdio)
-#define DT_DRV_COMPAT atmel_sam_mdio
-#elif DT_HAS_COMPAT_STATUS_OKAY(espressif_esp32_mdio)
-#define DT_DRV_COMPAT espressif_esp32_mdio
-#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_imx_netc_emdio)
-#define DT_DRV_COMPAT nxp_imx_netc_emdio
-#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_s32_netc_emdio)
-#define DT_DRV_COMPAT nxp_s32_netc_emdio
-#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_s32_gmac_mdio)
-#define DT_DRV_COMPAT nxp_s32_gmac_mdio
-#elif DT_HAS_COMPAT_STATUS_OKAY(adi_adin2111_mdio)
-#define DT_DRV_COMPAT adi_adin2111_mdio
-#elif DT_HAS_COMPAT_STATUS_OKAY(smsc_lan91c111_mdio)
-#define DT_DRV_COMPAT smsc_lan91c111_mdio
-#elif DT_HAS_COMPAT_STATUS_OKAY(zephyr_mdio_gpio)
-#define DT_DRV_COMPAT zephyr_mdio_gpio
-#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_enet_mdio)
-#define DT_DRV_COMPAT nxp_enet_mdio
-#elif DT_HAS_COMPAT_STATUS_OKAY(infineon_xmc4xxx_mdio)
-#define DT_DRV_COMPAT infineon_xmc4xxx_mdio
-#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_enet_qos_mdio)
-#define DT_DRV_COMPAT nxp_enet_qos_mdio
-#elif DT_HAS_COMPAT_STATUS_OKAY(litex_liteeth_mdio)
-#define DT_DRV_COMPAT litex_liteeth_mdio
-#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_mdio)
-#define DT_DRV_COMPAT st_stm32_mdio
-#elif DT_HAS_COMPAT_STATUS_OKAY(snps_dwcxgmac_mdio)
-#define DT_DRV_COMPAT snps_dwcxgmac_mdio
-#else
-#error "No known devicetree compatible match for MDIO shell"
-#endif
-
-#define MDIO_NODE_ID DT_COMPAT_GET_ANY_STATUS_OKAY(DT_DRV_COMPAT)
+static bool device_is_mdio(const struct device *dev)
+{
+	return DEVICE_API_IS(mdio, dev);
+}
+
+static void device_name_get(size_t idx, struct shell_static_entry *entry)
+{
+	const struct device *dev = shell_device_filter(idx, device_is_mdio);
+
+	entry->syntax = (dev != NULL) ? dev->name : NULL;
+	entry->handler = NULL;
+	entry->help = NULL;
+	entry->subcmd = NULL;
+}
+
+SHELL_DYNAMIC_CMD_CREATE(dsub_device_name, device_name_get);
+
+static int parse_device_arg(const struct shell *sh, char **argv, const struct device **dev)
+{
+	*dev = shell_device_get_binding(argv[1]);
+	if (!*dev) {
+		shell_error(sh, "device %s not found", argv[1]);
+		return -ENODEV;
+	}
+	return 0;
+}
 
 /*
  * Scan the entire 5-bit address space of the MDIO bus
  *
- * scan [<reg_addr>]
+ * scan <device> [<reg_addr>]
  */
 static int cmd_mdio_scan(const struct shell *sh, size_t argc, char **argv)
 {
@@ -60,16 +53,15 @@ static int cmd_mdio_scan(const struct shell *sh, size_t argc, char **argv)
 	int cnt;
 	uint16_t data;
 	uint16_t reg_addr;
+	int ret;
 
-	dev = DEVICE_DT_GET(MDIO_NODE_ID);
-	if (!device_is_ready(dev)) {
-		shell_error(sh, "MDIO: Device driver %s is not ready.", dev->name);
-
-		return -ENODEV;
+	ret = parse_device_arg(sh, argv, &dev);
+	if (ret < 0) {
+		return ret;
 	}
 
 	if (argc >= 2) {
-		reg_addr = strtol(argv[1], NULL, 16);
+		reg_addr = strtol(argv[2], NULL, 16);
 	} else {
 		reg_addr = 0;
 	}
@@ -97,24 +89,23 @@ static int cmd_mdio_scan(const struct shell *sh, size_t argc, char **argv)
 	return 0;
 }
 
-/* mdio write <port_addr> <reg_addr> <data> */
+/* mdio write <device> <port_addr> <reg_addr> <data> */
 static int cmd_mdio_write(const struct shell *sh, size_t argc, char **argv)
 {
 	const struct device *dev;
 	uint16_t data;
 	uint16_t reg_addr;
 	uint16_t port_addr;
+	int ret;
 
-	dev = DEVICE_DT_GET(MDIO_NODE_ID);
-	if (!device_is_ready(dev)) {
-		shell_error(sh, "MDIO: Device driver %s is not ready.", dev->name);
-
-		return -ENODEV;
+	ret = parse_device_arg(sh, argv, &dev);
+	if (ret < 0) {
+		return ret;
 	}
 
-	port_addr = strtol(argv[1], NULL, 16);
-	reg_addr = strtol(argv[2], NULL, 16);
-	data = strtol(argv[3], NULL, 16);
+	port_addr = strtol(argv[2], NULL, 16);
+	reg_addr = strtol(argv[3], NULL, 16);
+	data = strtol(argv[4], NULL, 16);
 
 	mdio_bus_enable(dev);
 
@@ -130,23 +121,22 @@ static int cmd_mdio_write(const struct shell *sh, size_t argc, char **argv)
 	return 0;
 }
 
-/* mdio read <port_addr> <reg_addr> */
+/* mdio read <device> <port_addr> <reg_addr> */
 static int cmd_mdio_read(const struct shell *sh, size_t argc, char **argv)
 {
 	const struct device *dev;
 	uint16_t data;
 	uint16_t reg_addr;
 	uint16_t port_addr;
+	int ret;
 
-	dev = DEVICE_DT_GET(MDIO_NODE_ID);
-	if (!device_is_ready(dev)) {
-		shell_error(sh, "MDIO: Device driver %s is not ready.", dev->name);
-
-		return -ENODEV;
+	ret = parse_device_arg(sh, argv, &dev);
+	if (ret < 0) {
+		return ret;
 	}
 
-	port_addr = strtol(argv[1], NULL, 16);
-	reg_addr = strtol(argv[2], NULL, 16);
+	port_addr = strtol(argv[2], NULL, 16);
+	reg_addr = strtol(argv[3], NULL, 16);
 
 	mdio_bus_enable(dev);
 
@@ -164,7 +154,7 @@ static int cmd_mdio_read(const struct shell *sh, size_t argc, char **argv)
 	return 0;
 }
 
-/* mdio write_c45 <port_addr> <dev_addr> <reg_addr> <value> */
+/* mdio write_c45 <device> <port_addr> <dev_addr> <reg_addr> <value> */
 static int cmd_mdio_write_45(const struct shell *sh, size_t argc, char **argv)
 {
 	const struct device *dev;
@@ -172,18 +162,17 @@ static int cmd_mdio_write_45(const struct shell *sh, size_t argc, char **argv)
 	uint16_t reg_addr;
 	uint8_t dev_addr;
 	uint8_t port_addr;
+	int ret;
 
-	dev = DEVICE_DT_GET(MDIO_NODE_ID);
-	if (!device_is_ready(dev)) {
-		shell_error(sh, "MDIO: Device driver %s is not ready.", dev->name);
-
-		return -ENODEV;
+	ret = parse_device_arg(sh, argv, &dev);
+	if (ret < 0) {
+		return ret;
 	}
 
-	port_addr = strtol(argv[1], NULL, 16);
-	dev_addr = strtol(argv[2], NULL, 16);
-	reg_addr = strtol(argv[3], NULL, 16);
-	data = strtol(argv[4], NULL, 16);
+	port_addr = strtol(argv[2], NULL, 16);
+	dev_addr = strtol(argv[3], NULL, 16);
+	reg_addr = strtol(argv[4], NULL, 16);
+	data = strtol(argv[5], NULL, 16);
 
 	mdio_bus_enable(dev);
 
@@ -199,7 +188,7 @@ static int cmd_mdio_write_45(const struct shell *sh, size_t argc, char **argv)
 	return 0;
 }
 
-/* mdio read_c45 <port_addr> <dev_addr> <reg_addr> */
+/* mdio read_c45 <device> <port_addr> <dev_addr> <reg_addr> */
 static int cmd_mdio_read_c45(const struct shell *sh, size_t argc, char **argv)
 {
 	const struct device *dev;
@@ -207,17 +196,16 @@ static int cmd_mdio_read_c45(const struct shell *sh, size_t argc, char **argv)
 	uint16_t reg_addr;
 	uint8_t dev_addr;
 	uint8_t port_addr;
+	int ret;
 
-	dev = DEVICE_DT_GET(MDIO_NODE_ID);
-	if (!device_is_ready(dev)) {
-		shell_error(sh, "MDIO: Device driver %s is not ready.", dev->name);
-
-		return -ENODEV;
+	ret = parse_device_arg(sh, argv, &dev);
+	if (ret < 0) {
+		return ret;
 	}
 
-	port_addr = strtol(argv[1], NULL, 16);
-	dev_addr = strtol(argv[2], NULL, 16);
-	reg_addr = strtol(argv[3], NULL, 16);
+	port_addr = strtol(argv[2], NULL, 16);
+	dev_addr = strtol(argv[3], NULL, 16);
+	reg_addr = strtol(argv[4], NULL, 16);
 
 	mdio_bus_enable(dev);
 
@@ -236,23 +224,23 @@ static int cmd_mdio_read_c45(const struct shell *sh, size_t argc, char **argv)
 }
 
 SHELL_STATIC_SUBCMD_SET_CREATE(sub_mdio_cmds,
-	SHELL_CMD_ARG(scan, NULL,
-		"Scan MDIO bus for devices: scan [<reg_addr>]",
-		cmd_mdio_scan, 0, 1),
-	SHELL_CMD_ARG(read, NULL,
-		"Read from MDIO device: read <phy_addr> <reg_addr>",
-		cmd_mdio_read, 3, 0),
-	SHELL_CMD_ARG(write, NULL,
-		"Write to MDIO device: write <phy_addr> <reg_addr> <value>",
-		cmd_mdio_write, 4, 0),
-	SHELL_CMD_ARG(read_c45, NULL,
+	SHELL_CMD_ARG(scan, &dsub_device_name,
+		"Scan MDIO bus for devices: scan <device> [<reg_addr>]",
+		cmd_mdio_scan, 1, 1),
+	SHELL_CMD_ARG(read, &dsub_device_name,
+		"Read from MDIO device: read <device> <phy_addr> <reg_addr>",
+		cmd_mdio_read, 4, 0),
+	SHELL_CMD_ARG(write, &dsub_device_name,
+		"Write to MDIO device: write <device> <phy_addr> <reg_addr> <value>",
+		cmd_mdio_write, 5, 0),
+	SHELL_CMD_ARG(read_c45, &dsub_device_name,
 		"Read from MDIO Clause 45 device: "
-		"read_c45 <port_addr> <dev_addr> <reg_addr>",
-		cmd_mdio_read_c45, 4, 0),
-	SHELL_CMD_ARG(write_c45, NULL,
+		"read_c45 <device> <port_addr> <dev_addr> <reg_addr>",
+		cmd_mdio_read_c45, 5, 0),
+	SHELL_CMD_ARG(write_c45, &dsub_device_name,
 		"Write to MDIO Clause 45 device: "
-		"write_c45 <port_addr> <dev_addr> <reg_addr> <value>",
-		cmd_mdio_write_45, 5, 0),
+		"write_c45 <device> <port_addr> <dev_addr> <reg_addr> <value>",
+		cmd_mdio_write_45, 6, 0),
 	SHELL_SUBCMD_SET_END     /* Array terminated. */
 );
 
diff --git a/drivers/mdio/mdio_stm32_hal.c b/drivers/mdio/mdio_stm32_hal.c
index aba789d705a..de9672fda94 100644
--- a/drivers/mdio/mdio_stm32_hal.c
+++ b/drivers/mdio/mdio_stm32_hal.c
@@ -9,6 +9,8 @@
 #include <errno.h>
 #include <zephyr/device.h>
 #include <zephyr/kernel.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <zephyr/drivers/pinctrl.h>
 #include <zephyr/drivers/mdio.h>
 #include <zephyr/net/ethernet.h>
@@ -28,6 +30,7 @@ struct mdio_stm32_data {
 
 struct mdio_stm32_config {
 	const struct pinctrl_dev_config *pincfg;
+	struct stm32_pclken pclken;
 };
 
 static int mdio_stm32_read(const struct device *dev, uint8_t prtad,
@@ -40,7 +43,13 @@ static int mdio_stm32_read(const struct device *dev, uint8_t prtad,
 
 	k_sem_take(&dev_data->sem, K_FOREVER);
 
+#ifdef CONFIG_ETH_STM32_HAL_API_V2
 	ret = HAL_ETH_ReadPHYRegister(heth, prtad, regad, &read);
+#else
+	heth->Init.PhyAddress = prtad;
+
+	ret = HAL_ETH_ReadPHYRegister(heth, regad, &read);
+#endif
 
 	k_sem_give(&dev_data->sem);
 
@@ -62,7 +71,13 @@ static int mdio_stm32_write(const struct device *dev, uint8_t prtad,
 
 	k_sem_take(&dev_data->sem, K_FOREVER);
 
+#ifdef CONFIG_ETH_STM32_HAL_API_V2
 	ret = HAL_ETH_WritePHYRegister(heth, prtad, regad, data);
+#else
+	heth->Init.PhyAddress = prtad;
+
+	ret = HAL_ETH_WritePHYRegister(heth, regad, data);
+#endif
 
 	k_sem_give(&dev_data->sem);
 
@@ -73,27 +88,84 @@ static int mdio_stm32_write(const struct device *dev, uint8_t prtad,
 	return ret;
 }
 
-static void mdio_stm32_bus_enable(const struct device *dev)
+#ifdef CONFIG_ETH_STM32_HAL_API_V1
+static void eth_set_mdio_clock_range_for_hal_v1(ETH_HandleTypeDef *heth)
 {
-	ARG_UNUSED(dev);
-}
+	uint32_t tmpreg1 = 0U;
+
+	/* Get the ETHERNET MACMIIAR value */
+	tmpreg1 = (heth->Instance)->MACMIIAR;
+	/* Clear CSR Clock Range CR[2:0] bits */
+	tmpreg1 &= ETH_MACMIIAR_CR_MASK;
+
+	/* Set CR bits depending on CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC value */
+#ifdef SOC_SERIES_STM32F1X
+	if ((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= 20000000U) &&
+	    (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC < 35000000U)) {
+		/* CSR Clock Range between 20-35 MHz */
+		tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV16;
+	} else if ((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= 35000000U) &&
+		   (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC < 60000000U)) {
+		/* CSR Clock Range between 35-60 MHz */
+		tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV26;
+	} else {
+		/* CSR Clock Range between 60-72 MHz */
+		tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_DIV42;
+	}
+#else  /* SOC_SERIES_STM32F2X */
+	if ((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= 20000000U) &&
+	    (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC < 35000000U)) {
+		/* CSR Clock Range between 20-35 MHz */
+		tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div16;
+	} else if ((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= 35000000U) &&
+		   (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC < 60000000U)) {
+		/* CSR Clock Range between 35-60 MHz */
+		tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div26;
+	} else if ((CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC >= 60000000U) &&
+		   (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC < 100000000U)) {
+		/* CSR Clock Range between 60-100 MHz */
+		tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div42;
+	} else {
+		/* CSR Clock Range between 100-120 MHz */
+		tmpreg1 |= (uint32_t)ETH_MACMIIAR_CR_Div62;
+	}
+#endif /* SOC_SERIES_STM32F2X */
 
-static void mdio_stm32_bus_disable(const struct device *dev)
-{
-	ARG_UNUSED(dev);
+	/* Write to ETHERNET MAC MIIAR: Configure the ETHERNET CSR Clock Range */
+	(heth->Instance)->MACMIIAR = (uint32_t)tmpreg1;
 }
+#endif /* CONFIG_ETH_STM32_HAL_API_V1 */
 
 static int mdio_stm32_init(const struct device *dev)
 {
 	struct mdio_stm32_data *const dev_data = dev->data;
 	const struct mdio_stm32_config *const config = dev->config;
+	ETH_HandleTypeDef *heth = &dev_data->heth;
 	int ret;
 
+	/* enable clock */
+	ret = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+			       (clock_control_subsys_t)&config->pclken);
+	if (ret < 0) {
+		LOG_ERR("Failed to enable ethernet clock needed for MDIO (%d)", ret);
+		return ret;
+	}
+
 	ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
 	if (ret < 0) {
 		return ret;
 	}
 
+#ifdef CONFIG_ETH_STM32_HAL_API_V2
+	HAL_ETH_SetMDIOClockRange(heth);
+#else
+	/* The legacy V1 HAL API does not provide a way to set the MDC clock range
+	 * via a separated function call. Implement an equivalent function ourselves
+	 * based on what the V1 HAL performs in HAL_ETH_Init().
+	 */
+	eth_set_mdio_clock_range_for_hal_v1(heth);
+#endif
+
 	k_sem_init(&dev_data->sem, 1, 1);
 
 	return 0;
@@ -102,22 +174,21 @@ static int mdio_stm32_init(const struct device *dev)
 static DEVICE_API(mdio, mdio_stm32_api) = {
 	.read = mdio_stm32_read,
 	.write = mdio_stm32_write,
-	.bus_enable = mdio_stm32_bus_enable,
-	.bus_disable = mdio_stm32_bus_disable,
 };
 
-#define MDIO_STM32_HAL_DEVICE(inst)								\
-	PINCTRL_DT_INST_DEFINE(inst);								\
-												\
-	static struct mdio_stm32_data mdio_stm32_data_##inst = {				\
-		.heth = {.Instance = (ETH_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(inst))},		\
-	};											\
-	static struct mdio_stm32_config mdio_stm32_config_##inst = {				\
-		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),					\
-	};											\
-	DEVICE_DT_INST_DEFINE(inst, &mdio_stm32_init, NULL,					\
-				&mdio_stm32_data_##inst, &mdio_stm32_config_##inst,		\
-				POST_KERNEL, CONFIG_ETH_INIT_PRIORITY,				\
-				&mdio_stm32_api);
+#define MDIO_STM32_HAL_DEVICE(inst)                                                                \
+	PINCTRL_DT_INST_DEFINE(inst);                                                              \
+                                                                                                   \
+	static struct mdio_stm32_data mdio_stm32_data_##inst = {                                   \
+		.heth = {.Instance = (ETH_TypeDef *)DT_REG_ADDR(DT_INST_PARENT(inst))},            \
+	};                                                                                         \
+	static struct mdio_stm32_config mdio_stm32_config_##inst = {                               \
+		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),                                    \
+		.pclken = {.bus = DT_CLOCKS_CELL_BY_NAME(DT_INST_PARENT(inst), stm_eth, bus),      \
+			   .enr = DT_CLOCKS_CELL_BY_NAME(DT_INST_PARENT(inst), stm_eth, bits)},    \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(inst, &mdio_stm32_init, NULL, &mdio_stm32_data_##inst,               \
+			      &mdio_stm32_config_##inst, POST_KERNEL, CONFIG_MDIO_INIT_PRIORITY,   \
+			      &mdio_stm32_api);
 
 DT_INST_FOREACH_STATUS_OKAY(MDIO_STM32_HAL_DEVICE)
diff --git a/drivers/mdio/mdio_sy1xx.c b/drivers/mdio/mdio_sy1xx.c
new file mode 100644
index 00000000000..21be9c148db
--- /dev/null
+++ b/drivers/mdio/mdio_sy1xx.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2024 sensry.io
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT sensry_sy1xx_mdio
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(sy1xx_mdio, CONFIG_MDIO_LOG_LEVEL);
+
+#include <zephyr/drivers/mdio.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <udma.h>
+
+struct sy1xx_mdio_dev_config {
+	const struct pinctrl_dev_config *pcfg;
+	uint32_t base_addr;
+	uint32_t mdc_freq;
+};
+
+struct sy1xx_mdio_dev_data {
+	struct k_sem sem;
+};
+
+/* mdio register offsets */
+#define SY1XX_MDIO_CFG_REG        0x0000
+#define SY1XX_MDIO_CTRL_REG       0x0004
+#define SY1XX_MDIO_READ_DATA_REG  0x0008
+#define SY1XX_MDIO_WRITE_DATA_REG 0x000c
+#define SY1XX_MDIO_IRQ_REG        0x0010
+
+/* mdio config register bit offsets */
+#define SY1XX_MDIO_CFG_DIV_OFFS (0)
+#define SY1XX_MDIO_CFG_EN_OFFS  (8)
+
+/* mdio ctrl register bit offsets */
+#define SY1XX_MDIO_CTRL_READY_OFFS    (0)
+#define SY1XX_MDIO_CTRL_INIT_OFFS     (8)
+#define SY1XX_MDIO_CTRL_REG_ADDR_OFFS (16)
+#define SY1XX_MDIO_CTRL_PHY_ADDR_OFFS (24)
+#define SY1XX_MDIO_CTRL_OP_OFFS       (30)
+
+/* mdio ctrl operations */
+#define SY1XX_MDIO_CTRL_OP_WRITE (0x1)
+#define SY1XX_MDIO_CTRL_OP_READ  (0x2)
+
+#define SY1XX_MDIO_READ_WRITE_WAIT_TIME_US (15)
+#define SY1XX_MDIO_READ_WRITE_RETRY_COUNT  (5)
+
+static int sy1xx_mdio_wait_for_ready(const struct device *dev);
+
+static int sy1xx_mdio_initialize(const struct device *dev)
+{
+
+	struct sy1xx_mdio_dev_config *cfg = (struct sy1xx_mdio_dev_config *)dev->config;
+	int ret;
+	uint32_t divider;
+	uint32_t reg;
+
+	/* zero mdio controller regs */
+	sys_write32(0x0, cfg->base_addr + SY1XX_MDIO_CFG_REG);
+	sys_write32(0x0, cfg->base_addr + SY1XX_MDIO_CTRL_REG);
+	sys_write32(0x0, cfg->base_addr + SY1XX_MDIO_READ_DATA_REG);
+	sys_write32(0x0, cfg->base_addr + SY1XX_MDIO_WRITE_DATA_REG);
+	sys_write32(0x0, cfg->base_addr + SY1XX_MDIO_IRQ_REG);
+
+	/* prepare mdio clock and enable mdio controller */
+	divider = (((sy1xx_soc_get_peripheral_clock() / cfg->mdc_freq) / 2) - 1) & 0xff;
+	reg = (divider << SY1XX_MDIO_CFG_DIV_OFFS) | BIT(SY1XX_MDIO_CFG_EN_OFFS);
+
+	LOG_DBG("config, div: %d, freq: %d", divider, cfg->mdc_freq);
+
+	sys_write32(reg, cfg->base_addr + SY1XX_MDIO_CFG_REG);
+
+	/* PAD config */
+	ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret < 0) {
+		LOG_ERR("failed to configure pins");
+		return ret;
+	}
+
+	ret = sy1xx_mdio_wait_for_ready(dev);
+	if (ret < 0) {
+		LOG_ERR("not ready");
+		return ret;
+	}
+
+	return 0;
+}
+
+static uint32_t sy1xx_mdio_is_ready(const struct device *dev)
+{
+	struct sy1xx_mdio_dev_config *cfg = (struct sy1xx_mdio_dev_config *)dev->config;
+	uint32_t status = sys_read32(cfg->base_addr + SY1XX_MDIO_CTRL_REG);
+
+	return (status & BIT(SY1XX_MDIO_CTRL_READY_OFFS));
+}
+
+static int sy1xx_mdio_wait_for_ready(const struct device *dev)
+{
+	uint32_t retries_left = SY1XX_MDIO_READ_WRITE_RETRY_COUNT;
+
+	while (!sy1xx_mdio_is_ready(dev)) {
+		k_sleep(K_USEC(SY1XX_MDIO_READ_WRITE_WAIT_TIME_US));
+		retries_left--;
+		if (!retries_left) {
+			return -EINVAL;
+		}
+	}
+	return 0;
+}
+
+static int sy1xx_mdio_read(const struct device *dev, uint8_t prtad, uint8_t regad, uint16_t *data)
+{
+	struct sy1xx_mdio_dev_config *cfg = (struct sy1xx_mdio_dev_config *)dev->config;
+	int ret;
+	uint32_t v;
+
+	prtad &= 0x1f;
+	regad &= 0x1f;
+
+	v = (SY1XX_MDIO_CTRL_OP_READ << SY1XX_MDIO_CTRL_OP_OFFS) |
+	    (prtad << SY1XX_MDIO_CTRL_PHY_ADDR_OFFS) | (regad << SY1XX_MDIO_CTRL_REG_ADDR_OFFS) |
+	    BIT(SY1XX_MDIO_CTRL_INIT_OFFS);
+
+	/* start the reading procedure */
+	sys_write32(v, cfg->base_addr + SY1XX_MDIO_CTRL_REG);
+
+	/* wait for the reading operation to finish */
+	ret = sy1xx_mdio_wait_for_ready(dev);
+	if (ret < 0) {
+		*data = sys_read32(cfg->base_addr + SY1XX_MDIO_READ_DATA_REG);
+
+		LOG_WRN("timeout while reading from phy: %d, reg: %d, val: %d", prtad, regad,
+			*data);
+		return ret;
+	}
+
+	/* get the data from the read result register */
+	*data = sys_read32(cfg->base_addr + SY1XX_MDIO_READ_DATA_REG);
+
+	return 0;
+}
+
+static int sy1xx_mdio_write(const struct device *dev, uint8_t prtad, uint8_t regad, uint16_t data)
+{
+	struct sy1xx_mdio_dev_config *cfg = (struct sy1xx_mdio_dev_config *)dev->config;
+	int ret;
+	uint32_t v;
+
+	prtad &= 0x1f;
+	regad &= 0x1f;
+
+	/* put the data to the write register */
+	sys_write32(data, cfg->base_addr + SY1XX_MDIO_WRITE_DATA_REG);
+
+	v = (SY1XX_MDIO_CTRL_OP_WRITE << SY1XX_MDIO_CTRL_OP_OFFS) |
+	    (prtad << SY1XX_MDIO_CTRL_PHY_ADDR_OFFS) | (regad << SY1XX_MDIO_CTRL_REG_ADDR_OFFS) |
+	    BIT(SY1XX_MDIO_CTRL_INIT_OFFS);
+
+	/* start the writing procedure */
+	sys_write32(v, cfg->base_addr + SY1XX_MDIO_CTRL_REG);
+
+	/* wait for the writing operation to finish */
+	ret = sy1xx_mdio_wait_for_ready(dev);
+	if (ret < 0) {
+		LOG_WRN("timeout while writing to phy: %d, reg: %d, val: %d", prtad, regad, data);
+		return ret;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(mdio, sy1xx_mdio_driver_api) = {
+	.read = sy1xx_mdio_read,
+	.write = sy1xx_mdio_write,
+};
+
+#define SY1XX_MDIO_INIT(n)                                                                         \
+                                                                                                   \
+	PINCTRL_DT_INST_DEFINE(n);                                                                 \
+                                                                                                   \
+	static const struct sy1xx_mdio_dev_config sy1xx_mdio_dev_config_##n = {                    \
+		.base_addr = DT_INST_REG_ADDR(n),                                                  \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                         \
+		.mdc_freq = DT_INST_PROP(n, clock_frequency),                                      \
+	};                                                                                         \
+                                                                                                   \
+	static struct sy1xx_mdio_dev_data sy1xx_mdio_dev_data##n;                                  \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, &sy1xx_mdio_initialize, NULL, &sy1xx_mdio_dev_data##n,            \
+			      &sy1xx_mdio_dev_config_##n, POST_KERNEL, CONFIG_MDIO_INIT_PRIORITY,  \
+			      &sy1xx_mdio_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(SY1XX_MDIO_INIT)
diff --git a/drivers/mdio/mdio_xilinx_axienet.c b/drivers/mdio/mdio_xilinx_axienet.c
new file mode 100644
index 00000000000..f06434a81d4
--- /dev/null
+++ b/drivers/mdio/mdio_xilinx_axienet.c
@@ -0,0 +1,338 @@
+/*
+ * Xilinx AXI 1G / 2.5G Ethernet Subsystem
+ *
+ * Copyright(c) 2024, CISPA Helmholtz Center for Information Security
+ * SPDX - License - Identifier : Apache-2.0
+ */
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(eth_xilinx_axienet_mdio, CONFIG_ETHERNET_LOG_LEVEL);
+
+#include <sys/types.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/mdio.h>
+#include <zephyr/sys/barrier.h>
+
+#define XILINX_AXIENET_MDIO_SETUP_REG_OFFSET                  0x00000500
+#define XILINX_AXIENET_MDIO_SETUP_REG_MDIO_DISABLE_MASK       BIT_MASK(0)
+#define XILINX_AXIENET_MDIO_SETUP_REG_MDIO_ENABLE_MASK        BIT(6)
+#define XILINX_AXIENET_MDIO_SETUP_REG_MDIO_CLOCK_DIVIDER_MASK BIT_MASK(6)
+#define XILINX_AXIENET_MDIO_CONTROL_REG_OFFSET                0x00000504
+#define XILINX_AXIENET_MDIO_CONTROL_REG_MASK_READY            BIT(7)
+#define XILINX_AXIENET_MDIO_CONTROL_REG_SHIFT_PHYADDR         24
+#define XILINX_AXIENET_MDIO_CONTROL_REG_SHIFT_REGADDR         16
+#define XILINX_AXIENET_MDIO_CONTROL_REG_SHIFT_TXOP            14
+#define XILINX_AXIENET_MDIO_CONTROL_REG_MASK_READ             BIT(15)
+#define XILINX_AXIENET_MDIO_CONTROL_REG_MASK_WRITE            BIT(14)
+#define XILINX_AXIENET_MDIO_CONTROL_REG_MASK_INITIATE         BIT(11)
+#define XILINX_AXIENET_MDIO_WRITE_DATA_REG_OFFSET             0x00000508
+#define XILINX_AXIENET_MDIO_READ_DATA_REG_OFFSET              0x0000050C
+#define XILINX_AXIENET_MDIO_READ_DATA_REG_DATA_MASK           BIT_MASK(16)
+/* same mask for all interrupt-related registers */
+#define XILINX_AXIENET_MDIO_INTERRUPT_MASK                    BIT(0)
+#define XILINX_AXIENET_MDIO_INTERRUPT_STATUS_REG_OFFSET       0x00000600
+#define XILINX_AXIENET_MDIO_INTERRUPT_PENDING_REG_OFFSET      0x00000610
+#define XILINX_AXIENET_MDIO_INTERRUPT_ENABLE_REG_OFFSET       0x00000620
+#define XILINX_AXIENET_MDIO_INTERRUPT_DISABLE_ALL_MASK        BIT_MASK(0)
+#define XILINX_AXIENET_MDIO_INTERRUPT_CLEAR_REG_OFFSET        0x00000630
+#define XILINX_AXIENET_MDIO_INTERRUPT_CLEAR_ALL_MASK          BIT_MASK(8)
+
+/* 2.5 MHz, i.e., max MDIO clock according to IEEE spec */
+#define XILINX_AXIENET_MDIO_MDIO_TARGET_FREQUENCY_HZ 2500000
+#define XILINX_AXIENET_MDIO_INTERRUPT_TIMEOUT_MS     100
+
+struct mdio_xilinx_axienet_data {
+	struct k_sem irq_sema;
+	uint16_t clock_divider;
+	bool bus_enabled;
+};
+
+struct mdio_xilinx_axienet_config {
+	void *reg;
+	unsigned int clock_frequency_hz;
+	void (*config_func)(const struct mdio_xilinx_axienet_data *data);
+	bool have_irq;
+};
+
+static void xilinx_axienet_mdio_write_register(const struct mdio_xilinx_axienet_config *config,
+					       uintptr_t reg_offset, uint32_t value)
+{
+	volatile uint32_t *reg_addr = (uint32_t *)((uint8_t *)(config->reg) + reg_offset);
+	*reg_addr = value;
+	barrier_dmem_fence_full(); /* make sure that write commits */
+}
+
+static uint32_t xilinx_axienet_read_mdio_register(const struct mdio_xilinx_axienet_config *config,
+						  uintptr_t reg_offset)
+{
+	const volatile uint32_t *reg_addr = (uint32_t *)((uint8_t *)(config->reg) + reg_offset);
+	const uint32_t ret = *reg_addr;
+
+	barrier_dmem_fence_full(); /* make sure that read commits */
+	return ret;
+}
+
+static void mdio_xilinx_axienet_bus_disable(const struct device *dev)
+{
+	const struct mdio_xilinx_axienet_config *config = dev->config;
+	struct mdio_xilinx_axienet_data *data = dev->data;
+
+	LOG_INF("Disable MDIO Bus!");
+
+	xilinx_axienet_mdio_write_register(config, XILINX_AXIENET_MDIO_INTERRUPT_ENABLE_REG_OFFSET,
+					   XILINX_AXIENET_MDIO_INTERRUPT_DISABLE_ALL_MASK);
+
+	xilinx_axienet_mdio_write_register(config, XILINX_AXIENET_MDIO_SETUP_REG_OFFSET,
+					   XILINX_AXIENET_MDIO_SETUP_REG_MDIO_DISABLE_MASK);
+	data->bus_enabled = false;
+}
+
+static void enable_mdio_bus(const struct mdio_xilinx_axienet_config *config,
+			    struct mdio_xilinx_axienet_data *data)
+{
+
+	if ((xilinx_axienet_read_mdio_register(config, XILINX_AXIENET_MDIO_SETUP_REG_OFFSET) &
+	     XILINX_AXIENET_MDIO_SETUP_REG_MDIO_ENABLE_MASK) == 0) {
+		int err;
+
+		xilinx_axienet_mdio_write_register(config, XILINX_AXIENET_MDIO_SETUP_REG_OFFSET,
+						   XILINX_AXIENET_MDIO_SETUP_REG_MDIO_ENABLE_MASK |
+							   data->clock_divider);
+
+		xilinx_axienet_mdio_write_register(config,
+						   XILINX_AXIENET_MDIO_INTERRUPT_ENABLE_REG_OFFSET,
+						   XILINX_AXIENET_MDIO_INTERRUPT_MASK);
+
+		if (config->have_irq) {
+			LOG_DBG("Waiting for bus enable!");
+			err = k_sem_take(&data->irq_sema,
+					 K_MSEC(XILINX_AXIENET_MDIO_INTERRUPT_TIMEOUT_MS));
+
+			if (err != 0) {
+				LOG_ERR("Could not enable MDIO bus: %d (%s)", err, strerror(-err));
+			}
+		}
+
+		while ((xilinx_axienet_read_mdio_register(config,
+							  XILINX_AXIENET_MDIO_SETUP_REG_OFFSET) &
+			XILINX_AXIENET_MDIO_SETUP_REG_MDIO_ENABLE_MASK) == 0) {
+			LOG_DBG("Waiting for bus enable!");
+		}
+
+	} else {
+		data->bus_enabled = true;
+	}
+}
+
+static void mdio_xilinx_axienet_bus_enable(const struct device *dev)
+{
+	const struct mdio_xilinx_axienet_config *config = dev->config;
+	struct mdio_xilinx_axienet_data *data = dev->data;
+	uint16_t clock_divider, clock_divider_full;
+
+	if (!config->clock_frequency_hz) {
+		LOG_ERR("No clock frequency specified for ethernet device!");
+		return;
+	}
+
+	/* this might result in a MDIO frequency that is a bit lower than the max frequency */
+	clock_divider_full = DIV_ROUND_UP(config->clock_frequency_hz,
+					  XILINX_AXIENET_MDIO_MDIO_TARGET_FREQUENCY_HZ * 2);
+	clock_divider = clock_divider_full & XILINX_AXIENET_MDIO_SETUP_REG_MDIO_CLOCK_DIVIDER_MASK;
+
+	if (clock_divider != clock_divider_full) {
+		LOG_ERR("Clock divider overflow!");
+		/* maximum divider value - lowest MDIO frequency we can achieve */
+		clock_divider = XILINX_AXIENET_MDIO_SETUP_REG_MDIO_CLOCK_DIVIDER_MASK;
+	}
+
+	data->clock_divider = clock_divider;
+
+	LOG_INF("Enable MDIO Bus assuming ethernet clock frequency %u divider %u!",
+		config->clock_frequency_hz, clock_divider);
+
+	xilinx_axienet_mdio_write_register(config, XILINX_AXIENET_MDIO_SETUP_REG_OFFSET,
+					   clock_divider);
+
+	enable_mdio_bus(config, data);
+
+	LOG_INF("MDIO ready!");
+}
+
+static int mdio_xilinx_axienet_read(const struct device *dev, uint8_t prtad, uint8_t devad,
+				    uint16_t *data)
+{
+	const struct mdio_xilinx_axienet_config *config = dev->config;
+	struct mdio_xilinx_axienet_data *dev_data = dev->data;
+	int err;
+
+	if (k_is_in_isr()) {
+		LOG_ERR("Called MDIO read in ISR!");
+		return -EWOULDBLOCK;
+	}
+
+	enable_mdio_bus(config, dev_data);
+
+	if (!dev_data->bus_enabled) {
+		LOG_ERR("Bus needs to be enabled!");
+		return -EIO;
+	}
+
+	LOG_DBG("Waiting for IRQ from MDIO!");
+
+	xilinx_axienet_mdio_write_register(
+		config, XILINX_AXIENET_MDIO_CONTROL_REG_OFFSET,
+		XILINX_AXIENET_MDIO_CONTROL_REG_MASK_INITIATE |
+			(prtad << XILINX_AXIENET_MDIO_CONTROL_REG_SHIFT_PHYADDR) |
+			(devad << XILINX_AXIENET_MDIO_CONTROL_REG_SHIFT_REGADDR) |
+			XILINX_AXIENET_MDIO_CONTROL_REG_MASK_READ);
+
+	xilinx_axienet_mdio_write_register(config, XILINX_AXIENET_MDIO_INTERRUPT_ENABLE_REG_OFFSET,
+					   XILINX_AXIENET_MDIO_INTERRUPT_MASK);
+
+	if (config->have_irq) {
+		err = k_sem_take(&dev_data->irq_sema,
+				 K_MSEC(XILINX_AXIENET_MDIO_INTERRUPT_TIMEOUT_MS));
+
+		if (err != 0) {
+			LOG_DBG("Error %d (%s) from IRQ semaphore - polling!", err, strerror(-err));
+		}
+	}
+
+	while ((xilinx_axienet_read_mdio_register(config, XILINX_AXIENET_MDIO_CONTROL_REG_OFFSET) &
+		XILINX_AXIENET_MDIO_CONTROL_REG_MASK_READY) == 0x0) {
+		LOG_DBG("Transfer is not yet ready!");
+	}
+
+	LOG_DBG("IRQ from MDIO received - read complete!");
+
+	*data = (uint16_t)(xilinx_axienet_read_mdio_register(
+				   config, XILINX_AXIENET_MDIO_READ_DATA_REG_OFFSET) &
+			   XILINX_AXIENET_MDIO_READ_DATA_REG_DATA_MASK);
+
+	LOG_DBG("Read %" PRIu16 " from MDIO!", *data);
+
+	return 0;
+}
+
+static int mdio_xilinx_axienet_write(const struct device *dev, uint8_t prtad, uint8_t devad,
+				     uint16_t data)
+{
+	const struct mdio_xilinx_axienet_config *config = dev->config;
+	struct mdio_xilinx_axienet_data *dev_data = dev->data;
+	int err;
+
+	if (k_is_in_isr()) {
+		LOG_ERR("Called MDIO write in ISR!");
+		return -EWOULDBLOCK;
+	}
+
+	enable_mdio_bus(config, dev_data);
+
+	if (!dev_data->bus_enabled) {
+		LOG_ERR("Bus needs to be enabled!");
+		return -EIO;
+	}
+
+	LOG_DBG("Waiting for IRQ from MDIO!");
+
+	xilinx_axienet_mdio_write_register(config, XILINX_AXIENET_MDIO_WRITE_DATA_REG_OFFSET, data);
+
+	xilinx_axienet_mdio_write_register(config, XILINX_AXIENET_MDIO_INTERRUPT_ENABLE_REG_OFFSET,
+					   XILINX_AXIENET_MDIO_INTERRUPT_MASK);
+
+	xilinx_axienet_mdio_write_register(
+		config, XILINX_AXIENET_MDIO_CONTROL_REG_OFFSET,
+		XILINX_AXIENET_MDIO_CONTROL_REG_MASK_INITIATE |
+			(prtad << XILINX_AXIENET_MDIO_CONTROL_REG_SHIFT_PHYADDR) |
+			(devad << XILINX_AXIENET_MDIO_CONTROL_REG_SHIFT_REGADDR) |
+			XILINX_AXIENET_MDIO_CONTROL_REG_MASK_WRITE);
+
+	if (config->have_irq) {
+		err = k_sem_take(&dev_data->irq_sema,
+				 K_MSEC(XILINX_AXIENET_MDIO_INTERRUPT_TIMEOUT_MS));
+		if (err != 0) {
+			LOG_DBG("Error %d (%s) from IRQ semaphore - polling!", err, strerror(-err));
+		}
+	}
+	while ((xilinx_axienet_read_mdio_register(config, XILINX_AXIENET_MDIO_CONTROL_REG_OFFSET) &
+		XILINX_AXIENET_MDIO_CONTROL_REG_MASK_READY) == 0x0) {
+		LOG_DBG("IRQ from MDIO received but transfer is not yet ready!");
+	}
+
+	LOG_DBG("IRQ from MDIO received - write complete!");
+
+	return 0;
+}
+
+static inline void xilinx_axienet_mdio_isr(const struct device *dev)
+{
+	const struct mdio_xilinx_axienet_config *config = dev->config;
+	struct mdio_xilinx_axienet_data *data = dev->data;
+	uint32_t interrupt_status;
+
+	interrupt_status = xilinx_axienet_read_mdio_register(
+		config, XILINX_AXIENET_MDIO_INTERRUPT_STATUS_REG_OFFSET);
+
+	if (interrupt_status & XILINX_AXIENET_MDIO_INTERRUPT_MASK) {
+		k_sem_give(&data->irq_sema);
+		LOG_DBG("MDIO interrupt received!");
+	} else {
+		LOG_DBG("Unknown interrupt received: %x!", interrupt_status);
+	}
+	xilinx_axienet_mdio_write_register(config, XILINX_AXIENET_MDIO_INTERRUPT_CLEAR_REG_OFFSET,
+					   XILINX_AXIENET_MDIO_INTERRUPT_MASK);
+}
+
+static int xilinx_axienet_mdio_probe(const struct device *dev)
+{
+	const struct mdio_xilinx_axienet_config *config = dev->config;
+	struct mdio_xilinx_axienet_data *data = dev->data;
+	int err;
+
+	if (config->have_irq) {
+		err = k_sem_init(&data->irq_sema, 0, K_SEM_MAX_LIMIT);
+
+		if (err != 0) {
+			LOG_ERR("Could not init semaphore: error %d (%s)", err, strerror(-err));
+			return err;
+		}
+	}
+
+	LOG_INF("Enabling IRQ!");
+	config->config_func(data);
+
+	return 0;
+}
+
+static const struct mdio_driver_api mdio_xilinx_axienet_api = {
+	.bus_disable = mdio_xilinx_axienet_bus_disable,
+	.bus_enable = mdio_xilinx_axienet_bus_enable,
+	.read = mdio_xilinx_axienet_read,
+	.write = mdio_xilinx_axienet_write};
+
+#define SETUP_IRQS(inst)                                                                           \
+	IRQ_CONNECT(DT_INST_IRQN(inst), DT_INST_IRQ(inst, priority), xilinx_axienet_mdio_isr,      \
+		    DEVICE_DT_INST_GET(inst), 0);                                                  \
+                                                                                                   \
+	irq_enable(DT_INST_IRQN(inst))
+
+#define XILINX_AXIENET_MDIO_INIT(inst)                                                             \
+                                                                                                   \
+	static void xilinx_axienet_mdio_config_##inst(const struct mdio_xilinx_axienet_data *data) \
+	{                                                                                          \
+                                                                                                   \
+		COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, interrupts), (SETUP_IRQS(inst)),           \
+			    (LOG_INF("No IRQs defined!")));        \
+	}                                                                                          \
+	static const struct mdio_xilinx_axienet_config mdio_xilinx_axienet_config##inst = {        \
+		.config_func = xilinx_axienet_mdio_config_##inst,                                  \
+		.reg = (void *)(uintptr_t)DT_REG_ADDR(DT_INST_PARENT(inst)),                       \
+		.clock_frequency_hz = DT_INST_PROP(inst, clock_frequency),                         \
+		.have_irq = DT_INST_NODE_HAS_PROP(inst, interrupts)};                              \
+	static struct mdio_xilinx_axienet_data mdio_xilinx_axienet_data##inst = {0};               \
+	DEVICE_DT_INST_DEFINE(inst, xilinx_axienet_mdio_probe, NULL,                               \
+			      &mdio_xilinx_axienet_data##inst, &mdio_xilinx_axienet_config##inst,  \
+			      POST_KERNEL, CONFIG_MDIO_INIT_PRIORITY, &mdio_xilinx_axienet_api);
+
+#define DT_DRV_COMPAT xlnx_axi_ethernet_1_00_a_mdio
+DT_INST_FOREACH_STATUS_OKAY(XILINX_AXIENET_MDIO_INIT)
diff --git a/drivers/memc/CMakeLists.txt b/drivers/memc/CMakeLists.txt
index fcdc5f06e45..afd05f4ecf1 100644
--- a/drivers/memc/CMakeLists.txt
+++ b/drivers/memc/CMakeLists.txt
@@ -6,6 +6,8 @@ zephyr_library_sources_ifdef(CONFIG_MEMC_STM32 memc_stm32.c)
 zephyr_library_sources_ifdef(CONFIG_MEMC_STM32_SDRAM memc_stm32_sdram.c)
 zephyr_linker_sources_ifdef(CONFIG_MEMC_STM32_SDRAM SECTIONS memc_stm32_sdram.ld)
 zephyr_library_sources_ifdef(CONFIG_MEMC_STM32_NOR_PSRAM memc_stm32_nor_psram.c)
+zephyr_library_sources_ifdef(CONFIG_MEMC_STM32_XSPI_PSRAM memc_stm32_xspi_psram.c)
+zephyr_linker_sources_ifdef(CONFIG_MEMC_STM32_XSPI_PSRAM SECTIONS memc_stm32_xspi_psram.ld)
 
 zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI memc_mcux_flexspi.c)
 zephyr_library_sources_ifdef(CONFIG_MEMC_MCUX_FLEXSPI_W956A8MBYA memc_mcux_flexspi_w956a8mbya.c)
diff --git a/drivers/memc/Kconfig.stm32 b/drivers/memc/Kconfig.stm32
index a4b3b96e816..b9e5fb02158 100644
--- a/drivers/memc/Kconfig.stm32
+++ b/drivers/memc/Kconfig.stm32
@@ -31,3 +31,12 @@ config MEMC_STM32_NOR_PSRAM
 	  Enable STM32 FMC NOR/PSRAM controller.
 
 endif
+
+config MEMC_STM32_XSPI_PSRAM
+	bool "STM32 XSPI PSRAM"
+	default y
+	depends on DT_HAS_ST_STM32_XSPI_PSRAM_ENABLED
+	select USE_STM32_HAL_XSPI
+	select PINCTRL
+	help
+	  Enable STM32 XSPI Memory Controller.
diff --git a/drivers/memc/memc_nxp_s32_qspi.c b/drivers/memc/memc_nxp_s32_qspi.c
index e1d5c60bd67..0eeef1e0572 100644
--- a/drivers/memc/memc_nxp_s32_qspi.c
+++ b/drivers/memc/memc_nxp_s32_qspi.c
@@ -11,6 +11,7 @@ LOG_MODULE_REGISTER(nxp_s32_qspi_memc, CONFIG_MEMC_LOG_LEVEL);
 
 #include <zephyr/drivers/pinctrl.h>
 #include <zephyr/sys/util.h>
+#include <zephyr/dt-bindings/qspi/nxp-s32-qspi.h>
 
 #include <soc.h>
 #include "memc_nxp_s32_qspi.h"
@@ -138,7 +139,7 @@ uint8_t memc_nxp_s32_qspi_get_instance(const struct device *dev)
 	))
 
 #define QSPI_PORT_SIZE_FN(node_id, side_upper, port)					\
-	COND_CODE_1(IS_EQ(DT_REG_ADDR(node_id), QSPI_PCSF##side_upper##port),		\
+	COND_CODE_1(IS_EQ(DT_REG_ADDR_RAW(node_id), QSPI_PCSF##side_upper##port),	\
 		(COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(node_id),				\
 			(.memSize##side_upper##port = DT_PROP(node_id, size) / 8,),	\
 			(.memSize##side_upper##port = 0,))),				\
@@ -154,6 +155,81 @@ uint8_t memc_nxp_s32_qspi_get_instance(const struct device *dev)
 	QSPI_PORT_SIZE(n, side_upper)							\
 	.readMode##side_upper = QSPI_READ_MODE(n, side, side_upper),
 
+#if FEATURE_QSPI_HAS_SFP
+
+#if QSPI_IP_SFP_ENABLE_MDAD
+#define SFP_MDAD_NODE(n) DT_INST_CHILD(n, sfp_mdad)
+
+#define QSPI_SECURE_ATTRIBUTE(node_id)								\
+	(DT_PROP(node_id, secure_attribute) == NXP_S32_QSPI_NON_SECURE ? QSPI_IP_SFP_UNSECURE :	\
+	(DT_PROP(node_id, secure_attribute) == NXP_S32_QSPI_SECURE ? QSPI_IP_SFP_SECURE :	\
+	(DT_PROP(node_id, secure_attribute) == (NXP_S32_QSPI_NON_SECURE | NXP_S32_QSPI_SECURE) ?\
+									QSPI_IP_SFP_BOTH :	\
+	QSPI_IP_SFP_RESERVED)))
+
+#define _QSPI_SFP_MDAD_CFG(node_id, n)							\
+	{										\
+		.SecureAttribute = QSPI_SECURE_ATTRIBUTE(node_id),			\
+		.MaskType = DT_ENUM_IDX(node_id, mask_type),				\
+		.Valid = true,								\
+		.Mask = DT_PROP(node_id, mask),						\
+		.DomainId = DT_PROP(node_id, domain_id),				\
+	},
+
+#define QSPI_SFP_MDAD_CFG(n)								\
+	.Tg = {										\
+		DT_FOREACH_CHILD_STATUS_OKAY_VARGS(SFP_MDAD_NODE(n), _QSPI_SFP_MDAD_CFG, n)\
+	},
+#endif /* QSPI_IP_SFP_ENABLE_MDAD */
+
+#if QSPI_IP_SFP_ENABLE_FRAD
+#define SFP_FRAD_NODE(n) DT_INST_CHILD(n, sfp_frad)
+
+#define QSPI_ACP_POLICY(node_id)							\
+	(DT_PROP(node_id, master_domain_acp_policy) == NXP_S32_QSPI_SECURE ?		\
+								QSPI_IP_SFP_ACP_SECURE :\
+	(DT_PROP(node_id, master_domain_acp_policy) == (NXP_S32_QSPI_NON_SECURE |	\
+				NXP_S32_QSPI_PRIVILEGE) ? QSPI_IP_SFP_ACP_PRIVILEGED :	\
+	(DT_PROP(node_id, master_domain_acp_policy) == (NXP_S32_QSPI_SECURE |		\
+				NXP_S32_QSPI_PRIVILEGE) ? QSPI_IP_SFP_ACP_SECURE_PRIVILEGED :\
+	(DT_PROP(node_id, master_domain_acp_policy) == (NXP_S32_QSPI_NON_SECURE |	\
+		NXP_S32_QSPI_SECURE | NXP_S32_QSPI_PRIVILEGE) ? QSPI_IP_SFP_ACP_ALL :	\
+	QSPI_IP_SFP_ACP_NONE))))
+
+#define QSPI_EXCLUSIVE_ACCESS_LOCK(node_id)						\
+	(DT_ENUM_IDX(node_id, exclusive_access_lock) == 0 ? QSPI_IP_SFP_EAL_DISABLED :	\
+	(DT_ENUM_IDX(node_id, exclusive_access_lock) == 1 ? QSPI_IP_SFP_EAL_OWNER :	\
+	QSPI_IP_SFP_EAL_NONE))
+
+#define _QSPI_SFP_FRAD_CFG(node_id, n)							\
+	{										\
+		.StartAddress = DT_REG_ADDR(node_id),					\
+		.EndAddress = DT_REG_ADDR(node_id) + DT_REG_SIZE(node_id) - 1,		\
+		.Valid = true,								\
+		.Md0Acp = QSPI_ACP_POLICY(node_id),					\
+		.Md1Acp = QSPI_ACP_POLICY(node_id),					\
+		.ExclusiveAccessLock = QSPI_EXCLUSIVE_ACCESS_LOCK(node_id),		\
+		.ExclusiveAccessOwner = DT_PROP(node_id, exclusive_access_owner),	\
+	},
+
+#define QSPI_SFP_FRAD_CFG(n)								\
+	.Frad = {									\
+		DT_FOREACH_CHILD_STATUS_OKAY_VARGS(SFP_FRAD_NODE(n), _QSPI_SFP_FRAD_CFG, n)\
+	},
+#endif /* QSPI_IP_SFP_ENABLE_FRAD */
+
+#define QSPI_SFP_MASTER_TIMEOUT_CYCLES 0xffff
+
+#define QSPI_SFP_CFG(n)									\
+	IF_ENABLED(QSPI_IP_SFP_ENABLE_GLOBAL,						\
+		(.SfpCfg = {								\
+			.MasterTimeout = QSPI_SFP_MASTER_TIMEOUT_CYCLES,		\
+			IF_ENABLED(QSPI_IP_SFP_ENABLE_MDAD, (QSPI_SFP_MDAD_CFG(n)))	\
+			IF_ENABLED(QSPI_IP_SFP_ENABLE_FRAD, (QSPI_SFP_FRAD_CFG(n)))	\
+		},))
+
+#endif /* FEATURE_QSPI_HAS_SFP */
+
 #define MEMC_NXP_S32_QSPI_CONTROLLER_CONFIG(n)						\
 	BUILD_ASSERT(DT_INST_PROP_LEN(n, ahb_buffers_masters) == QSPI_IP_AHB_BUFFERS,	\
 		"ahb-buffers-masters must be of size QSPI_IP_AHB_BUFFERS");		\
@@ -174,6 +250,7 @@ uint8_t memc_nxp_s32_qspi_get_instance(const struct device *dev)
 		QSPI_DATA_CFG(n)							\
 		QSPI_ADDR_CFG(n)							\
 		QSPI_BYTES_SWAP_ADDR(n)							\
+		IF_ENABLED(FEATURE_QSPI_HAS_SFP, (QSPI_SFP_CFG(n)))			\
 	}
 
 #define MEMC_NXP_S32_QSPI_INIT_DEVICE(n)						\
diff --git a/drivers/memc/memc_stm32_xspi_psram.c b/drivers/memc/memc_stm32_xspi_psram.c
new file mode 100644
index 00000000000..676ec8c7f27
--- /dev/null
+++ b/drivers/memc/memc_stm32_xspi_psram.c
@@ -0,0 +1,371 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT st_stm32_xspi_psram
+
+#include <errno.h>
+#include <soc.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/stm32_clock_control.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(memc_stm32_xspi_psram, CONFIG_MEMC_LOG_LEVEL);
+
+#define STM32_XSPI_NODE DT_INST_PARENT(0)
+
+/* Memory registers definition */
+#define MR0		0x00000000U
+#define MR1		0x00000001U
+#define MR2		0x00000002U
+#define MR3		0x00000003U
+#define MR4		0x00000004U
+#define MR8		0x00000008U
+
+/* Memory commands */
+#define SYNC_READ_CMD	0x00U
+#define SYNC_WRITE_CMD	0x80U
+#define BURST_READ_CMD	0x20U
+#define BURST_WRITE_CMD	0xA0U
+#define READ_REG_CMD	0x40U
+#define WRITE_REG_CMD	0xC0U
+#define RESET_CMD	0xFFU
+
+/* Memory default dummy clocks cycles */
+#define DUMMY_CLK_CYCLES_READ	6U
+#define DUMMY_CLK_CYCLES_WRITE	6U
+
+struct memc_stm32_xspi_psram_config {
+	const struct pinctrl_dev_config *pcfg;
+	const struct stm32_pclken pclken;
+	const struct stm32_pclken pclken_ker;
+	const struct stm32_pclken pclken_mgr;
+	size_t memory_size;
+};
+
+struct memc_stm32_xspi_psram_data {
+	XSPI_HandleTypeDef hxspi;
+};
+
+static int ap_memory_write_reg(XSPI_HandleTypeDef *hxspi, uint32_t address, uint8_t *value)
+{
+	XSPI_RegularCmdTypeDef cmd = {0};
+
+	/* Initialize the write register command.
+	 * The following fields are already set to 0 thanks to cmd = {0}.
+	 * They are kept in comment for better understanding of the command.
+	 * cmd.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
+	 * cmd.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
+	 * cmd.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
+	 * cmd.DQSMode = HAL_XSPI_DQS_DISABLE;
+	 */
+	cmd.Instruction = WRITE_REG_CMD;
+	cmd.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
+	cmd.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
+	cmd.Address = address;
+	cmd.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
+	cmd.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
+	cmd.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE;
+	cmd.DataMode = HAL_XSPI_DATA_8_LINES;
+	cmd.DataLength = 2U;
+	cmd.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE;
+
+	/* Configure the command */
+	if (HAL_XSPI_Command(hxspi, &cmd, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
+		LOG_ERR("XSPI write command failed");
+		return -EIO;
+	}
+
+	/* Transmission of the data */
+	if (HAL_XSPI_Transmit(hxspi, value, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
+		LOG_ERR("XSPI transmit failed");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int ap_memory_read_reg(XSPI_HandleTypeDef *hxspi, uint32_t address, uint8_t *value,
+			      uint32_t latency_cycles)
+{
+	XSPI_RegularCmdTypeDef cmd = {0};
+
+	/* Initialize the read register command
+	 * The following fields are already set to 0 thanks to cmd = {0}.
+	 * They are kept in comment for better understanding of the command.
+	 * cmd.OperationType = HAL_XSPI_OPTYPE_COMMON_CFG;
+	 * cmd.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
+	 * cmd.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
+	 * cmd.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
+	 */
+	cmd.Instruction = READ_REG_CMD;
+	cmd.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
+	cmd.Address = address;
+	cmd.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
+	cmd.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
+	cmd.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE;
+	cmd.DataMode = HAL_XSPI_DATA_8_LINES;
+	cmd.DataLength = 2U;
+	cmd.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE;
+	cmd.DummyCycles = latency_cycles;
+	cmd.DQSMode = HAL_XSPI_DQS_ENABLE;
+
+	/* Configure the command */
+	if (HAL_XSPI_Command(hxspi, &cmd, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
+		LOG_ERR("XSPI read command failed");
+		return -EIO;
+	}
+
+	/* Reception of the data */
+	if (HAL_XSPI_Receive(hxspi, value, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
+		LOG_ERR("XSPI receive failed");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int ap_memory_configure(XSPI_HandleTypeDef *hxspi)
+{
+	uint8_t read_latency_code = DT_INST_PROP(0, read_latency);
+	uint8_t read_latency_cycles = read_latency_code + 3U; /* Code 0 <=> 3 cycles... */
+
+	/* MR0 register for read and write */
+	uint8_t regW_MR0[2] = {(DT_INST_PROP(0, fixed_latency) ? 0x20U : 0x00U) |
+			       (read_latency_code << 2) |
+			       (DT_INST_PROP(0, drive_strength)), 0x8DU};
+	uint8_t regR_MR0[2] = {0};
+
+	/* MR4 register for read and write */
+	uint8_t regW_MR4[2] = {(DT_INST_PROP(0, write_latency) << 5) |
+			      (DT_INST_PROP(0, refresh_rate) << 3) |
+			      (DT_INST_PROP(0, pasr)), 0x05U};
+	uint8_t regR_MR4[2] = {0};
+
+	/* MR8 register for read and write */
+	uint8_t regW_MR8[2] = {(DT_INST_PROP(0, io_x16_mode) ? 0x40U : 0x00U) |
+			       (DT_INST_PROP(0, rbx) ? 0x08U : 0x00U) |
+			       (DT_INST_PROP(0, burst_type_hybrid_wrap) ? 0x04U : 0x00U) |
+			       (DT_INST_PROP(0, burst_length)), 0x08U};
+	uint8_t regR_MR8[2] = {0};
+
+	/* Configure Read Latency and drive Strength */
+	if (ap_memory_write_reg(hxspi, MR0, regW_MR0) != 0) {
+		return -EIO;
+	}
+
+	/* Check MR0 configuration */
+	if (ap_memory_read_reg(hxspi, MR0, regR_MR0, read_latency_cycles) != 0) {
+		return -EIO;
+	}
+	if (regR_MR0[0] != regW_MR0[0]) {
+		return -EIO;
+	}
+
+	/* Configure Write Latency and refresh rate */
+	if (ap_memory_write_reg(hxspi, MR4, regW_MR4) != 0) {
+		return -EIO;
+	}
+
+	/* Check MR4 configuration */
+	if (ap_memory_read_reg(hxspi, MR4, regR_MR4, read_latency_cycles) != 0) {
+		return -EIO;
+	}
+	if (regR_MR4[0] != regW_MR4[0]) {
+		return -EIO;
+	}
+
+	/* Configure Burst Length */
+	if (ap_memory_write_reg(hxspi, MR8, regW_MR8) != 0) {
+		return -EIO;
+	}
+
+	/* Check MR8 configuration */
+	if (ap_memory_read_reg(hxspi, MR8, regR_MR8, read_latency_cycles) != 0) {
+		return -EIO;
+	}
+	if (regR_MR8[0] != regW_MR8[0]) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int memc_stm32_xspi_psram_init(const struct device *dev)
+{
+	const struct memc_stm32_xspi_psram_config *dev_cfg = dev->config;
+	struct memc_stm32_xspi_psram_data *dev_data = dev->data;
+	XSPI_HandleTypeDef hxspi = dev_data->hxspi;
+	XSPI_TypeDef *xspi = hxspi.Instance;
+	uint32_t ahb_clock_freq;
+	XSPIM_CfgTypeDef cfg = {0};
+	XSPI_RegularCmdTypeDef cmd = {0};
+	XSPI_MemoryMappedTypeDef mem_mapped_cfg = {0};
+	int ret;
+
+	/* Signals configuration */
+	ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret < 0) {
+		LOG_ERR("XSPI pinctrl setup failed (%d)", ret);
+		return ret;
+	}
+
+	if (!device_is_ready(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE))) {
+		LOG_ERR("clock control device not ready");
+		return -ENODEV;
+	}
+
+	/* Clock configuration */
+	if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+			     (clock_control_subsys_t) &dev_cfg->pclken) != 0) {
+		LOG_ERR("Could not enable XSPI clock");
+		return -EIO;
+	}
+	if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+				   (clock_control_subsys_t) &dev_cfg->pclken,
+				   &ahb_clock_freq) < 0) {
+		LOG_ERR("Failed call clock_control_get_rate(pclken)");
+		return -EIO;
+	}
+
+#if DT_CLOCKS_HAS_NAME(STM32_XSPI_NODE, xspi_ker)
+	/* Kernel clock config for peripheral if any */
+	if (clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+					(clock_control_subsys_t) &dev_cfg->pclken_ker,
+					NULL) != 0) {
+		LOG_ERR("Could not select XSPI domain clock");
+		return -EIO;
+	}
+
+	if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+					(clock_control_subsys_t) &dev_cfg->pclken_ker,
+					&ahb_clock_freq) < 0) {
+		LOG_ERR("Failed call clock_control_get_rate(pclken_ker)");
+		return -EIO;
+	}
+#endif
+
+#if DT_CLOCKS_HAS_NAME(STM32_XSPI_NODE, xspi_mgr)
+	/* Clock domain corresponding to the IO-Mgr (XSPIM) */
+	if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+				(clock_control_subsys_t) &dev_cfg->pclken_mgr) != 0) {
+		LOG_ERR("Could not enable XSPI Manager clock");
+		return -EIO;
+	}
+#endif
+
+	hxspi.Init.MemorySize = find_msb_set(dev_cfg->memory_size) - 2;
+
+	if (HAL_XSPI_Init(&hxspi) != HAL_OK) {
+		LOG_ERR("XSPI Init failed");
+		return -EIO;
+	}
+
+	cfg.nCSOverride = HAL_XSPI_CSSEL_OVR_NCS1;
+	cfg.IOPort = HAL_XSPIM_IOPORT_1;
+
+	if (HAL_XSPIM_Config(&hxspi, &cfg, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
+		LOG_ERR("XSPIMgr Init failed");
+		return -EIO;
+	}
+
+	/* Configure AP memory registers */
+	ret = ap_memory_configure(&hxspi);
+	if (ret != 0) {
+		LOG_ERR("AP memory configuration failed");
+		return -EIO;
+	}
+
+	/* The following fields are already set to 0 thanks to cmd = {0}.
+	 * They are kept in comment for better understanding of the command.
+	 * cmd.InstructionWidth = HAL_XSPI_INSTRUCTION_8_BITS;
+	 * cmd.InstructionDTRMode = HAL_XSPI_INSTRUCTION_DTR_DISABLE;
+	 * cmd.Address = 0x0U;
+	 * cmd.AlternateBytesMode = HAL_XSPI_ALT_BYTES_NONE;
+	 */
+	cmd.OperationType = HAL_XSPI_OPTYPE_WRITE_CFG;
+	cmd.InstructionMode = HAL_XSPI_INSTRUCTION_8_LINES;
+	cmd.Instruction = BURST_WRITE_CMD;
+	cmd.AddressMode = HAL_XSPI_ADDRESS_8_LINES;
+	cmd.AddressWidth = HAL_XSPI_ADDRESS_32_BITS;
+	cmd.AddressDTRMode = HAL_XSPI_ADDRESS_DTR_ENABLE;
+	cmd.DataMode = HAL_XSPI_DATA_16_LINES;
+	cmd.DataDTRMode = HAL_XSPI_DATA_DTR_ENABLE;
+	cmd.DummyCycles = DUMMY_CLK_CYCLES_WRITE;
+	cmd.DQSMode = HAL_XSPI_DQS_ENABLE;
+
+	if (HAL_XSPI_Command(&hxspi, &cmd, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
+		return -EIO;
+	}
+
+	cmd.OperationType = HAL_XSPI_OPTYPE_READ_CFG;
+	cmd.Instruction = BURST_READ_CMD;
+	cmd.DummyCycles = DUMMY_CLK_CYCLES_READ;
+
+	if (HAL_XSPI_Command(&hxspi, &cmd, HAL_XSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
+		return -EIO;
+	}
+
+	mem_mapped_cfg.TimeOutActivation = HAL_XSPI_TIMEOUT_COUNTER_DISABLE;
+	mem_mapped_cfg.NoPrefetchData = HAL_XSPI_AUTOMATIC_PREFETCH_ENABLE;
+	mem_mapped_cfg.NoPrefetchAXI = HAL_XSPI_AXI_PREFETCH_DISABLE;
+
+	if (HAL_XSPI_MemoryMapped(&hxspi, &mem_mapped_cfg) != HAL_OK) {
+		return -EIO;
+	}
+
+	MODIFY_REG(xspi->CR, XSPI_CR_NOPREF, HAL_XSPI_AUTOMATIC_PREFETCH_DISABLE);
+
+	return 0;
+}
+
+PINCTRL_DT_DEFINE(STM32_XSPI_NODE);
+
+static const struct memc_stm32_xspi_psram_config memc_stm32_xspi_cfg = {
+	.pcfg = PINCTRL_DT_DEV_CONFIG_GET(STM32_XSPI_NODE),
+	.pclken = {.bus = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspix, bus),
+		   .enr = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspix, bits)},
+#if DT_CLOCKS_HAS_NAME(STM32_XSPI_NODE, xspi_ker)
+	.pclken_ker = {.bus = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_ker, bus),
+		       .enr = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_ker, bits)},
+#endif
+#if DT_CLOCKS_HAS_NAME(STM32_XSPI_NODE, xspi_mgr)
+	.pclken_mgr = {.bus = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_mgr, bus),
+		       .enr = DT_CLOCKS_CELL_BY_NAME(STM32_XSPI_NODE, xspi_mgr, bits)},
+#endif
+	.memory_size = DT_INST_REG_ADDR_BY_IDX(0, 1),
+};
+
+static struct memc_stm32_xspi_psram_data memc_stm32_xspi_data = {
+	.hxspi = {
+		.Instance = (XSPI_TypeDef *)DT_REG_ADDR(STM32_XSPI_NODE),
+		.Init = {
+			.FifoThresholdByte = 8U,
+			.MemoryMode = HAL_XSPI_SINGLE_MEM,
+			.MemoryType = (DT_INST_PROP(0, io_x16_mode) ?
+					HAL_XSPI_MEMTYPE_APMEM_16BITS :
+					HAL_XSPI_MEMTYPE_APMEM),
+			.ChipSelectHighTimeCycle = 1U,
+			.FreeRunningClock = HAL_XSPI_FREERUNCLK_DISABLE,
+			.ClockMode = HAL_XSPI_CLOCK_MODE_0,
+			.WrapSize = HAL_XSPI_WRAP_NOT_SUPPORTED,
+			.ClockPrescaler = 3U,
+			.SampleShifting = HAL_XSPI_SAMPLE_SHIFT_NONE,
+			.DelayHoldQuarterCycle = HAL_XSPI_DHQC_ENABLE,
+			.ChipSelectBoundary = HAL_XSPI_BONDARYOF_16KB,
+			.MaxTran = 0U,
+			.Refresh = 0x81U,
+			.MemorySelect = HAL_XSPI_CSSEL_NCS1,
+		},
+	},
+};
+
+DEVICE_DT_INST_DEFINE(0, &memc_stm32_xspi_psram_init, NULL,
+		      &memc_stm32_xspi_data, &memc_stm32_xspi_cfg,
+		      POST_KERNEL, CONFIG_MEMC_INIT_PRIORITY,
+		      NULL);
diff --git a/drivers/memc/memc_stm32_xspi_psram.ld b/drivers/memc/memc_stm32_xspi_psram.ld
new file mode 100644
index 00000000000..6ef15da2841
--- /dev/null
+++ b/drivers/memc/memc_stm32_xspi_psram.ld
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(psram), okay)
+GROUP_START(PSRAM)
+
+	SECTION_PROLOGUE(_STM32_PSRAM_SECTION_NAME, (NOLOAD),)
+	{
+		*(.stm32_psram)
+		*(".stm32_psram.*")
+	} GROUP_LINK_IN(PSRAM)
+
+GROUP_END(PSRAM)
+#endif
diff --git a/drivers/mfd/CMakeLists.txt b/drivers/mfd/CMakeLists.txt
index 8fe7ac34cae..7a479bdc9dc 100644
--- a/drivers/mfd/CMakeLists.txt
+++ b/drivers/mfd/CMakeLists.txt
@@ -9,11 +9,12 @@ zephyr_library_sources_ifdef(CONFIG_MFD_NCT38XX mfd_nct38xx.c)
 zephyr_library_sources_ifdef(CONFIG_MFD_NPM1300 mfd_npm1300.c)
 zephyr_library_sources_ifdef(CONFIG_MFD_NPM2100 mfd_npm2100.c)
 zephyr_library_sources_ifdef(CONFIG_MFD_NPM6001 mfd_npm6001.c)
-zephyr_library_sources_ifdef(CONFIG_MFD_AXP192 mfd_axp192.c)
+zephyr_library_sources_ifdef(CONFIG_MFD_AXP192_AXP2101 mfd_axp192.c)
 zephyr_library_sources_ifdef(CONFIG_MFD_AD559X mfd_ad559x.c)
 zephyr_library_sources_ifdef(CONFIG_MFD_AD559X_BUS_I2C mfd_ad559x_i2c.c)
 zephyr_library_sources_ifdef(CONFIG_MFD_AD559X_BUS_SPI mfd_ad559x_spi.c)
 zephyr_library_sources_ifdef(CONFIG_MFD_MAX31790 mfd_max31790.c)
+zephyr_library_sources_ifdef(CONFIG_MFD_MAXQ10XX mfd_maxq10xx.c)
 zephyr_library_sources_ifdef(CONFIG_NXP_LP_FLEXCOMM mfd_nxp_lp_flexcomm.c)
 zephyr_library_sources_ifdef(CONFIG_MFD_BD8LB600FS mfd_bd8lb600fs.c)
 zephyr_library_sources_ifdef(CONFIG_MFD_TLE9104 mfd_tle9104.c)
@@ -21,3 +22,5 @@ zephyr_library_sources_ifdef(CONFIG_MFD_ITE_IT8801 mfd_ite_it8801.c)
 zephyr_library_sources_ifdef(CONFIG_MFD_ITE_IT8801_ALTCTRL mfd_it8801_altctrl.c)
 zephyr_library_sources_ifdef(CONFIG_MFD_AW9523B mfd_aw9523b.c)
 zephyr_library_sources_ifdef(CONFIG_MFD_DS3231 mfd_ds3231.c)
+zephyr_library_sources_ifdef(CONFIG_MFD_MAX22017 mfd_max22017.c)
+zephyr_library_sources_ifdef(CONFIG_MFD_PF1550 mfd_pf1550.c)
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index b11e3dfd4b2..74184f231f4 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -25,11 +25,14 @@ source "drivers/mfd/Kconfig.aw9523b"
 source "drivers/mfd/Kconfig.bd8lb600fs"
 source "drivers/mfd/Kconfig.ds3231"
 source "drivers/mfd/Kconfig.max20335"
+source "drivers/mfd/Kconfig.max22017"
 source "drivers/mfd/Kconfig.max31790"
+source "drivers/mfd/Kconfig.maxq10xx"
 source "drivers/mfd/Kconfig.nct38xx"
 source "drivers/mfd/Kconfig.npm1300"
 source "drivers/mfd/Kconfig.npm2100"
 source "drivers/mfd/Kconfig.npm6001"
+source "drivers/mfd/Kconfig.pf1550"
 source "drivers/mfd/Kconfig.lpflexcomm"
 source "drivers/mfd/Kconfig.tle9104"
 source "drivers/mfd/Kconfig.it8801"
diff --git a/drivers/mfd/Kconfig.axp192 b/drivers/mfd/Kconfig.axp192
index da76c4cc615..93bef1b72ff 100644
--- a/drivers/mfd/Kconfig.axp192
+++ b/drivers/mfd/Kconfig.axp192
@@ -1,10 +1,10 @@
 # Copyright (c) 2023 Martin Kiepfer <mrmarteng@teleschirm.org>
 # SPDX-License-Identifier: Apache-2.0
 
-config MFD_AXP192
-	bool "AXP192 PMIC multi-function device driver"
+config MFD_AXP192_AXP2101
+	bool "AXP192/AXP2101 PMIC multi-function device driver"
 	default y
-	depends on DT_HAS_X_POWERS_AXP192_ENABLED
+	depends on DT_HAS_X_POWERS_AXP192_ENABLED || DT_HAS_X_POWERS_AXP2101_ENABLED
 	select I2C
 	help
-	  Enable the X-Powers AXP192 PMIC multi-function device driver
+	  Enable the X-Powers AXP192/AXP2101 PMIC multi-function device driver
diff --git a/drivers/mfd/Kconfig.max22017 b/drivers/mfd/Kconfig.max22017
new file mode 100644
index 00000000000..8a28f19614e
--- /dev/null
+++ b/drivers/mfd/Kconfig.max22017
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Analog Devices Inc.
+# Copyright (c) 2024 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+config MFD_MAX22017
+	bool "Analog Devices MAX22017 DAC/GPIO chip"
+	default y
+	depends on SPI
+	select CRC
+	depends on DT_HAS_ADI_MAX22017_ENABLED
+	help
+	  Enable the driver for the Analog Devices MAX22017 DAC/GPIO chip
diff --git a/drivers/mfd/Kconfig.maxq10xx b/drivers/mfd/Kconfig.maxq10xx
new file mode 100644
index 00000000000..e6fdc680c27
--- /dev/null
+++ b/drivers/mfd/Kconfig.maxq10xx
@@ -0,0 +1,24 @@
+# Copyright (c) 2025 Vogl Electronic GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+config MFD_MAXQ10XX
+	bool "MAXQ10xx mfd driver"
+	default y
+	depends on DT_HAS_ADI_MAXQ10XX_ENABLED
+	# using select SPI at this point introduces a cyclic dependency
+	depends on SPI
+	help
+	  This option enables the mfd driver for the
+	  MAXQ10xx crypto chips.
+
+if MFD_MAXQ10XX
+
+config MFD_MAXQ10XX_INIT_PRIORITY
+	int "MAXQ10xx init priority"
+	default 51
+	help
+	  Device driver initialization priority.
+	  Device is connected to SPI bus, it has to
+	  be initialized after SPI driver.
+
+endif # MFD_MAXQ10XX
diff --git a/drivers/mfd/Kconfig.pf1550 b/drivers/mfd/Kconfig.pf1550
new file mode 100644
index 00000000000..127bcbabe0b
--- /dev/null
+++ b/drivers/mfd/Kconfig.pf1550
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Arduino SA
+# SPDX-License-Identifier: Apache-2.0
+
+config MFD_PF1550
+	bool "PF1550 PMIC multi-function device driver"
+	default y
+	depends on DT_HAS_NXP_PF1550_ENABLED
+	select I2C
+	help
+	  Enable the NXP PF1550 PMIC multi-function device driver
diff --git a/drivers/mfd/mfd_adp5585.c b/drivers/mfd/mfd_adp5585.c
index d57b82035dc..61d0e386e4c 100644
--- a/drivers/mfd/mfd_adp5585.c
+++ b/drivers/mfd/mfd_adp5585.c
@@ -56,9 +56,8 @@ static void mfd_adp5585_work_handler(struct k_work *work)
 
 	k_sem_take(&data->lock, K_FOREVER);
 	/* Read Interrput Flag */
-	if (ret == 0) {
-		ret = i2c_reg_read_byte_dt(&config->i2c_bus, ADP5585_INT_STATUS, &reg_int_status);
-	}
+	ret = i2c_reg_read_byte_dt(&config->i2c_bus, ADP5585_INT_STATUS, &reg_int_status);
+
 	/* Clear Interrput Flag */
 	if (ret == 0) {
 		ret = i2c_reg_write_byte_dt(&config->i2c_bus, ADP5585_INT_STATUS, reg_int_status);
diff --git a/drivers/mfd/mfd_axp192.c b/drivers/mfd/mfd_axp192.c
index 421f5d19a37..b15fdeac75d 100644
--- a/drivers/mfd/mfd_axp192.c
+++ b/drivers/mfd/mfd_axp192.c
@@ -3,8 +3,6 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#define DT_DRV_COMPAT x_powers_axp192
-
 #include <errno.h>
 #include <stdbool.h>
 
@@ -15,6 +13,19 @@
 
 LOG_MODULE_REGISTER(mfd_axp192, CONFIG_MFD_LOG_LEVEL);
 
+struct mfd_axp192_config {
+	struct i2c_dt_spec i2c;
+#ifdef CONFIG_DT_HAS_X_POWERS_AXP192_ENABLED
+	bool vbusen_disable;
+#endif
+	uint8_t reg_chip_id;
+	uint8_t vbus_config_reg;
+	uint8_t chip_id;
+	uint8_t val_vbusen_disable;
+};
+
+#ifdef CONFIG_DT_HAS_X_POWERS_AXP192_ENABLED
+
 /* Chip ID value */
 #define AXP192_CHIP_ID 0x03U
 
@@ -97,11 +108,6 @@ LOG_MODULE_REGISTER(mfd_axp192, CONFIG_MFD_LOG_LEVEL);
 #define AXP192_GPIO5_OUTPUT_VAL   0x04U
 #define AXP192_GPIO5_OUTPUT_SHIFT 3U
 
-struct mfd_axp192_config {
-	struct i2c_dt_spec i2c;
-	bool vbusen_disable;
-};
-
 struct mfd_axp192_data {
 	const struct device *gpio_mask_used[AXP192_GPIO_MAX_NUM];
 	uint8_t gpio_mask_output;
@@ -139,12 +145,27 @@ const struct mfd_axp192_func_reg_desc gpio_reg_desc[AXP192_GPIO_MAX_NUM] = {
 		.mask = AXP192_GPIO4_FUNC_MASK,
 	},
 };
+#endif /* CONFIG_DT_HAS_X_POWERS_AXP192_ENABLED */
+
+#ifdef CONFIG_DT_HAS_X_POWERS_AXP2101_ENABLED
+
+/* Chip ID value */
+#define AXP2101_CHIP_ID		0x4AU
+
+/* Registers definitions */
+#define AXP2101_REG_CHIP_ID	0x03U
+
+/* AXP210 GPIO register addresses */
+#define AXP2101_VBUS_CFG_REG	0x00U
+
+/* VBUS control reg values */
+#define AXP2101_VBUS_CFG_VAL_VBUSEN_DISABLE	0x00U
+#endif /* CONFIG_DT_HAS_X_POWERS_AXP2101_ENABLED */
 
 static int mfd_axp192_init(const struct device *dev)
 {
 	const struct mfd_axp192_config *config = dev->config;
 	uint8_t chip_id;
-	uint8_t vbus_val;
 	int ret;
 
 	LOG_DBG("Initializing instance");
@@ -155,29 +176,29 @@ static int mfd_axp192_init(const struct device *dev)
 	}
 
 	/* Check if axp192 chip is available */
-	ret = i2c_reg_read_byte_dt(&config->i2c, AXP192_REG_CHIP_ID, &chip_id);
+	ret = i2c_reg_read_byte_dt(&config->i2c, config->reg_chip_id, &chip_id);
 	if (ret < 0) {
 		return ret;
 	}
-	if (chip_id != AXP192_CHIP_ID) {
+	if (chip_id != config->chip_id) {
 		LOG_ERR("Invalid Chip detected (%d)", chip_id);
 		return -EINVAL;
 	}
 
+#ifdef CONFIG_DT_HAS_X_POWERS_AXP192_ENABLED
 	/* Disable N_VBUSEN */
-	vbus_val = 0;
-	if (config->vbusen_disable) {
-		vbus_val = AXP192_VBUS_CFG_VAL_VBUSEN_DISABLE;
-	}
-	ret = i2c_reg_update_byte_dt(&config->i2c, AXP192_VBUS_CFG_REG,
-				     AXP192_VBUS_CFG_VAL_VBUSEN_DISABLE, vbus_val);
+	ret = i2c_reg_update_byte_dt(
+		&config->i2c, config->vbus_config_reg, config->val_vbusen_disable,
+		config->vbusen_disable ? config->val_vbusen_disable : 0);
 	if (ret < 0) {
 		return ret;
 	}
+#endif
 
 	return 0;
 }
 
+#ifdef CONFIG_DT_HAS_X_POWERS_AXP192_ENABLED
 int mfd_axp192_gpio_func_get(const struct device *dev, uint8_t gpio, enum axp192_gpio_func *func)
 {
 	const struct mfd_axp192_config *config = dev->config;
@@ -605,16 +626,29 @@ int mfd_axp192_gpio_write_port(const struct device *dev, uint8_t value, uint8_t
 
 	return 0;
 }
-
-#define MFD_AXP192_DEFINE(inst)                                                                    \
-	static const struct mfd_axp192_config config##inst = {                                     \
-		.i2c = I2C_DT_SPEC_INST_GET(inst),                                                 \
-		.vbusen_disable = DT_INST_PROP_OR(inst, vbusen_disable, false),                    \
+#endif
+
+#define MFD_AXP192_CONST_CONFIG(model)                                                             \
+	.reg_chip_id = AXP##model##_REG_CHIP_ID,                                                   \
+	.vbus_config_reg = AXP##model##_VBUS_CFG_REG,                                              \
+	.chip_id = AXP##model##_CHIP_ID,                                                           \
+	.val_vbusen_disable = AXP##model##_CHIP_ID,
+
+#define MFD_AXP192_AXP2101_DEFINE(node, model)                                                     \
+	static const struct mfd_axp192_config config##node = {                                     \
+		.i2c = I2C_DT_SPEC_GET(node),                                                      \
+		IF_ENABLED(CONFIG_DT_HAS_X_POWERS_AXP192_ENABLED,                                  \
+		(.vbusen_disable = DT_PROP_OR(node, vbusen_disable, false),))                      \
+		MFD_AXP192_CONST_CONFIG(model)                                                     \
 	};                                                                                         \
                                                                                                    \
-	static struct mfd_axp192_data data##inst;                                                  \
+	IF_ENABLED(CONFIG_DT_HAS_X_POWERS_AXP192_ENABLED,                                          \
+		   (static struct mfd_axp192_data data##node;))                                    \
                                                                                                    \
-	DEVICE_DT_INST_DEFINE(inst, mfd_axp192_init, NULL, &data##inst, &config##inst,             \
-			      POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, NULL);
+	DEVICE_DT_DEFINE(node, mfd_axp192_init, NULL,                                              \
+			 COND_CODE_1(CONFIG_DT_HAS_X_POWERS_AXP192_ENABLED,                        \
+				     (&data##node), (NULL)),                                       \
+			 &config##node, POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, NULL);
 
-DT_INST_FOREACH_STATUS_OKAY(MFD_AXP192_DEFINE);
+DT_FOREACH_STATUS_OKAY_VARGS(x_powers_axp192, MFD_AXP192_AXP2101_DEFINE, 192);
+DT_FOREACH_STATUS_OKAY_VARGS(x_powers_axp2101, MFD_AXP192_AXP2101_DEFINE, 2101);
diff --git a/drivers/mfd/mfd_max22017.c b/drivers/mfd/mfd_max22017.c
new file mode 100644
index 00000000000..a4b7d6fa155
--- /dev/null
+++ b/drivers/mfd/mfd_max22017.c
@@ -0,0 +1,390 @@
+/*
+ * Copyright (c) 2024 Analog Devices Inc.
+ * Copyright (c) 2024 Baylibre SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT adi_max22017
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_utils.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/irq.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/crc.h>
+
+LOG_MODULE_REGISTER(mfd_max22017, CONFIG_MFD_LOG_LEVEL);
+
+#include <zephyr/drivers/mfd/max22017.h>
+
+struct max22017_config {
+	struct spi_dt_spec spi;
+	const struct gpio_dt_spec gpio_reset;
+	const struct gpio_dt_spec gpio_int;
+	bool crc_mode;
+};
+
+int max22017_reg_read(const struct device *dev, uint8_t addr, uint16_t *value)
+{
+	int ret;
+	const struct max22017_config *config = dev->config;
+	const struct max22017_data *data = dev->data;
+	uint8_t rxbuffer[4] = {0};
+	size_t recv_len = 3;
+
+	*value = 0;
+	addr = FIELD_PREP(MAX22017_SPI_TRANS_ADDR, addr) | FIELD_PREP(MAX22017_SPI_TRANS_DIR, 1);
+
+	if (data->crc_enabled) {
+		recv_len += 1;
+	}
+
+	const struct spi_buf txb[] = {
+		{
+			.buf = &addr,
+			.len = 1,
+		},
+	};
+	const struct spi_buf rxb[] = {
+		{
+			.buf = rxbuffer,
+			.len = recv_len,
+		},
+	};
+
+	struct spi_buf_set tx = {
+		.buffers = txb,
+		.count = ARRAY_SIZE(txb),
+	};
+
+	struct spi_buf_set rx = {
+		.buffers = rxb,
+		.count = ARRAY_SIZE(rxb),
+	};
+
+	ret = spi_transceive_dt(&config->spi, &tx, &rx);
+
+	if (ret) {
+		return ret;
+	}
+
+	if (!data->crc_enabled) {
+		goto out_skip_crc;
+	}
+
+	uint8_t crc_in[] = {addr, rxbuffer[1], rxbuffer[2]};
+
+	ret = crc8(crc_in, 3, MAX22017_CRC_POLY, 0, true);
+
+	if (ret != rxbuffer[3]) {
+		LOG_ERR("Reg read: CRC Mismatch calculated / read: %x / %x", ret, rxbuffer[3]);
+		return -EINVAL;
+	}
+
+out_skip_crc:
+	*value = rxbuffer[1] | rxbuffer[2] << 8;
+	*value = sys_be16_to_cpu(*value);
+
+	return 0;
+}
+
+int max22017_reg_write(const struct device *dev, uint8_t addr, uint16_t value)
+{
+	uint8_t crc;
+	size_t crc_len = 0;
+	const struct max22017_config *config = dev->config;
+	const struct max22017_data *data = dev->data;
+
+	addr = FIELD_PREP(MAX22017_SPI_TRANS_ADDR, addr) | FIELD_PREP(MAX22017_SPI_TRANS_DIR, 0);
+	value = sys_cpu_to_be16(value);
+
+	if (data->crc_enabled) {
+		uint8_t crc_in[] = {addr, ((uint8_t *)&value)[0], ((uint8_t *)&value)[1]};
+
+		crc_len = 1;
+		crc = crc8(crc_in, 3, MAX22017_CRC_POLY, 0, true);
+	}
+
+	const struct spi_buf buf[] = {
+		{
+			.buf = &addr,
+			.len = 1,
+		},
+		{
+			.buf = &value,
+			.len = 2,
+		},
+		{
+			.buf = &crc,
+			.len = crc_len,
+		},
+	};
+
+	struct spi_buf_set tx = {
+		.buffers = buf,
+		.count = ARRAY_SIZE(buf),
+	};
+
+	return spi_write_dt(&config->spi, &tx);
+}
+
+static int max22017_reset(const struct device *dev)
+{
+	int ret = 0;
+	uint16_t ao_sta;
+	const struct max22017_config *config = dev->config;
+
+	if (config->gpio_reset.port != NULL) {
+		ret = gpio_pin_set_dt(&config->gpio_reset, 0);
+		if (ret) {
+			return ret;
+		}
+		k_sleep(K_MSEC(100));
+		ret = gpio_pin_set_dt(&config->gpio_reset, 1);
+		k_sleep(K_MSEC(500));
+	} else {
+		ret = max22017_reg_write(dev, MAX22017_GEN_RST_CTRL_OFF,
+					 FIELD_PREP(MAX22017_GEN_RST_CTRL_GEN_RST, 1));
+		if (ret) {
+			return ret;
+		}
+		k_sleep(K_MSEC(100));
+		ret = max22017_reg_write(dev, MAX22017_GEN_RST_CTRL_OFF,
+					 FIELD_PREP(MAX22017_GEN_RST_CTRL_GEN_RST, 0));
+		if (ret) {
+			return ret;
+		}
+		k_sleep(K_MSEC(500));
+		ret = max22017_reg_read(dev, MAX22017_AO_STA_OFF, &ao_sta);
+		if (ret) {
+			return ret;
+		}
+		if (FIELD_GET(MAX22017_AO_STA_BUSY_STA, ao_sta)) {
+			ret = -EBUSY;
+		}
+	}
+	return ret;
+}
+
+static void max22017_isr(const struct device *dev, struct gpio_callback *gpio_cb, uint32_t pins)
+{
+	struct max22017_data *data = CONTAINER_OF(gpio_cb, struct max22017_data, callback_int);
+	int ret;
+
+	k_mutex_lock(&data->lock, K_FOREVER);
+
+	ret = k_work_submit(&data->int_work);
+	if (ret < 0) {
+		LOG_WRN("Could not submit int work: %d", ret);
+	}
+
+	k_mutex_unlock(&data->lock);
+}
+
+static void max22017_int_worker(struct k_work *work)
+{
+	struct max22017_data *data = CONTAINER_OF(work, struct max22017_data, int_work);
+	const struct device *dev = data->dev;
+	int ret;
+	uint16_t gen_int;
+
+	k_mutex_lock(&data->lock, K_FOREVER);
+
+	ret = max22017_reg_read(dev, MAX22017_GEN_INT_OFF, &gen_int);
+	if (ret) {
+		LOG_ERR("Unable to read GEN_INT register");
+		goto fail;
+	}
+
+	if (FIELD_GET(MAX22017_GEN_INT_FAIL_INT, gen_int)) {
+		LOG_ERR("Boot failure");
+	}
+
+	ret = FIELD_GET(MAX22017_GEN_INT_CONV_OVF_INT, gen_int);
+	if (ret) {
+		LOG_ERR("Conversion failure on channels: %s %s", (ret & BIT(0)) ? "0" : "",
+			(ret & BIT(1)) ? "1" : "");
+	}
+
+	ret = FIELD_GET(MAX22017_GEN_INT_OPENWIRE_DTCT_INT, gen_int);
+	if (ret) {
+		LOG_ERR("Openwire detected on channels: %s %s", (ret & BIT(0)) ? "0" : "",
+			(ret & BIT(1)) ? "1" : "");
+	}
+
+	if (FIELD_GET(MAX22017_GEN_INT_HVDD_INT, gen_int)) {
+		LOG_ERR("HVDD/HVSS voltage difference below 1.5V");
+	}
+
+	if (FIELD_GET(MAX22017_GEN_INT_TMOUT_INT, gen_int)) {
+		LOG_ERR("SPI transaction timeout");
+	}
+
+	ret = FIELD_GET(MAX22017_GEN_INT_THSHDN_INT, gen_int);
+	if (ret) {
+		LOG_ERR("Thermal shutdown AO channels: %s %s", (ret & BIT(0)) ? "0" : "",
+			(ret & BIT(1)) ? "1" : "");
+	}
+
+	ret = FIELD_GET(MAX22017_GEN_INT_THWRNG_INT, gen_int);
+	if (ret) {
+		LOG_ERR("Thermal warning AO channels: %s %s", (ret & BIT(0)) ? "0" : "",
+			(ret & BIT(1)) ? "1" : "");
+	}
+
+	ret = FIELD_GET(MAX22017_GEN_INT_OVC_INT, gen_int);
+	if (ret) {
+		LOG_ERR("Over current on channels: %s %s", (ret & BIT(0)) ? "0" : "",
+			(ret & BIT(1)) ? "1" : "");
+	}
+
+	if (FIELD_GET(MAX22017_GEN_INT_CRC_INT, gen_int)) {
+		LOG_ERR("CRC Error");
+	}
+
+	ret = FIELD_GET(MAX22017_GEN_INT_GPI_INT, gen_int);
+	if (ret) {
+		LOG_INF("GPI Interrupt: %d", ret);
+#ifdef CONFIG_GPIO_MAX22017
+		uint16_t gpi_sta, lsb;
+
+		ret = max22017_reg_read(dev, MAX22017_GEN_GPI_INT_STA_OFF, &gpi_sta);
+		if (ret) {
+			goto fail;
+		}
+
+		/* Aggregate both positive and negative edge together */
+		gpi_sta = FIELD_GET(MAX22017_GEN_GPI_INT_GPI_NEG_EDGE_INT, gpi_sta) |
+			  FIELD_GET(MAX22017_GEN_GPI_INT_GPI_POS_EDGE_INT, gpi_sta);
+		while (gpi_sta) {
+			lsb = LSB_GET(gpi_sta);
+			gpio_fire_callbacks(&data->callbacks_gpi, dev, lsb);
+			gpi_sta &= ~lsb;
+		}
+#endif
+	}
+fail:
+	k_mutex_unlock(&data->lock);
+}
+
+static int max22017_init(const struct device *dev)
+{
+	const struct max22017_config *config = dev->config;
+	struct max22017_data *data = dev->data;
+	uint16_t version;
+	int ret;
+	uint16_t gen_cnfg = 0, gen_int_en = 0;
+
+	if (!spi_is_ready_dt(&config->spi)) {
+		LOG_ERR("SPI spi %s not ready", config->spi.bus->name);
+		return -ENODEV;
+	}
+
+	if (config->gpio_reset.port != NULL) {
+		ret = gpio_pin_configure_dt(&config->gpio_reset, GPIO_OUTPUT_ACTIVE);
+		if (ret) {
+			LOG_ERR("failed to initialize GPIO reset pin");
+			return ret;
+		}
+	}
+
+	ret = max22017_reset(dev);
+	if (ret) {
+		LOG_ERR("failed to reset MAX22017");
+		return ret;
+	}
+
+	data->dev = dev;
+	k_work_init(&data->int_work, max22017_int_worker);
+	k_mutex_init(&data->lock);
+
+	if (config->gpio_int.port) {
+		ret = gpio_pin_configure_dt(&config->gpio_int, GPIO_INPUT);
+		if (ret) {
+			LOG_ERR("failed to initialize GPIO interrupt pin");
+			goto fail;
+		}
+
+		ret = gpio_pin_interrupt_configure_dt(&config->gpio_int, GPIO_INT_EDGE_TO_ACTIVE);
+		if (ret) {
+			LOG_ERR("failed to configure interrupt pin");
+			goto fail;
+		}
+
+		gpio_init_callback(&data->callback_int, max22017_isr, BIT(config->gpio_int.pin));
+		ret = gpio_add_callback(config->gpio_int.port, &data->callback_int);
+		if (ret) {
+			LOG_ERR("failed to add data ready callback");
+			goto fail;
+		}
+	}
+
+	k_mutex_lock(&data->lock, K_FOREVER);
+
+	ret = max22017_reg_write(dev, MAX22017_AO_CNFG_OFF, 0);
+	if (ret) {
+		return ret;
+	}
+
+	ret = max22017_reg_write(dev, MAX22017_AO_DATA_CHn_OFF(0), 0);
+	if (ret) {
+		goto fail;
+	}
+
+	ret = max22017_reg_write(dev, MAX22017_AO_DATA_CHn_OFF(1), 0);
+	if (ret) {
+		goto fail;
+	}
+
+	if (config->crc_mode) {
+		gen_cnfg |= FIELD_PREP(MAX22017_GEN_CNFG_CRC_EN, 1);
+		gen_int_en |= FIELD_PREP(MAX22017_GEN_INTEN_CRC_INTEN, 1);
+	}
+
+	ret = max22017_reg_write(dev, MAX22017_GEN_INTEN_OFF, gen_int_en);
+	if (ret) {
+		goto fail;
+	}
+
+	ret = max22017_reg_write(dev, MAX22017_GEN_CNFG_OFF, gen_cnfg);
+	if (ret) {
+		goto fail;
+	}
+
+	if (config->crc_mode) {
+		data->crc_enabled = true;
+	}
+
+	ret = max22017_reg_read(dev, MAX22017_GEN_ID_OFF, &version);
+	if (ret) {
+		LOG_ERR("Unable to read MAX22017 version over SPI: %d", ret);
+		goto fail;
+	}
+
+	LOG_INF("MAX22017 version: 0x%lx 0x%lx", FIELD_GET(MAX22017_GEN_ID_PROD_ID, version),
+		FIELD_GET(MAX22017_GEN_ID_REV_ID, version));
+
+fail:
+	k_mutex_unlock(&data->lock);
+	return ret;
+}
+
+#define INST_DT_MAX22017(index)                                                                    \
+	static const struct max22017_config max22017_config_##index = {                            \
+		.spi = SPI_DT_SPEC_INST_GET(index, SPI_OP_MODE_MASTER | SPI_WORD_SET(8U), 0U),     \
+		.gpio_int = GPIO_DT_SPEC_INST_GET_OR(index, int_gpios, {0}),                       \
+		.gpio_reset = GPIO_DT_SPEC_INST_GET_OR(index, rst_gpios, {0}),                     \
+		.crc_mode = DT_INST_PROP_OR(index, crc_mode, 0),                                   \
+	};                                                                                         \
+                                                                                                   \
+	static struct max22017_data max22017_data_##index;                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(index, max22017_init, NULL, &max22017_data_##index,                  \
+			      &max22017_config_##index, POST_KERNEL, CONFIG_MFD_INIT_PRIORITY,     \
+			      NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(INST_DT_MAX22017);
diff --git a/drivers/mfd/mfd_maxq10xx.c b/drivers/mfd/mfd_maxq10xx.c
new file mode 100644
index 00000000000..d5c5642783f
--- /dev/null
+++ b/drivers/mfd/mfd_maxq10xx.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2025 Vogl Electronic GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT adi_maxq10xx
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/drivers/mfd/mfd_maxq10xx.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(mfd_maxq10xx, CONFIG_MFD_LOG_LEVEL);
+
+struct mfd_maxq10xx_config {
+	struct spi_dt_spec spi;
+};
+
+struct mfd_maxq10xx_data {
+	struct k_sem sem_lock;
+};
+
+struct k_sem *mfd_maxq10xx_get_lock(const struct device *dev)
+{
+	struct mfd_maxq10xx_data *data = dev->data;
+
+	return &data->sem_lock;
+}
+
+static int mfd_maxq10xx_init(const struct device *dev)
+{
+	const struct mfd_maxq10xx_config *config = dev->config;
+
+	if (!spi_is_ready_dt(&config->spi)) {
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+BUILD_ASSERT(CONFIG_SPI_INIT_PRIORITY < CONFIG_MFD_MAXQ10XX_INIT_PRIORITY,
+	     "SPI driver must be initialized before maxq10xx mfd driver");
+
+#define DEFINE_MAXQ10XX_MFD(_num)                                                                  \
+	static const struct mfd_maxq10xx_config mfd_maxq10xx_config##_num = {                      \
+		.spi = SPI_DT_SPEC_INST_GET(_num, SPI_WORD_SET(8), 0),                             \
+	};                                                                                         \
+	static struct mfd_maxq10xx_data mfd_maxq10xx_data##_num = {                                \
+		.sem_lock = Z_SEM_INITIALIZER(mfd_maxq10xx_data##_num.sem_lock, 1, 1),             \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(_num, mfd_maxq10xx_init, NULL, &mfd_maxq10xx_data##_num,             \
+			      &mfd_maxq10xx_config##_num, POST_KERNEL,                             \
+			      CONFIG_MFD_MAXQ10XX_INIT_PRIORITY, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(DEFINE_MAXQ10XX_MFD);
diff --git a/drivers/mfd/mfd_pf1550.c b/drivers/mfd/mfd_pf1550.c
new file mode 100644
index 00000000000..492f516e253
--- /dev/null
+++ b/drivers/mfd/mfd_pf1550.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2024 Arduino SA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_pf1550
+
+#include <errno.h>
+
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/sys/util.h>
+
+#define PF1550_REG_CHIP_ID 0x00
+#define PF1550_CHIP_ID_VAL ((15 << 3) | 4)
+
+struct mfd_pf1550_config {
+	struct i2c_dt_spec bus;
+};
+
+static int mfd_pf1550_init(const struct device *dev)
+{
+	const struct mfd_pf1550_config *config = dev->config;
+	uint8_t val;
+	int ret;
+
+	if (!i2c_is_ready_dt(&config->bus)) {
+		return -ENODEV;
+	}
+
+	ret = i2c_reg_read_byte_dt(&config->bus, PF1550_REG_CHIP_ID, &val);
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (val != PF1550_CHIP_ID_VAL) {
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+#define MFD_PF1550_DEFINE(inst)                                                                    \
+	static const struct mfd_pf1550_config mfd_pf1550_config##inst = {                          \
+		.bus = I2C_DT_SPEC_INST_GET(inst),                                                 \
+	};                                                                                         \
+												   \
+	DEVICE_DT_INST_DEFINE(inst, mfd_pf1550_init, NULL, NULL, &mfd_pf1550_config##inst,         \
+			      POST_KERNEL, CONFIG_MFD_INIT_PRIORITY, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(MFD_PF1550_DEFINE)
diff --git a/drivers/mipi_dbi/CMakeLists.txt b/drivers/mipi_dbi/CMakeLists.txt
index 3bd1ee28473..f01bf36598c 100644
--- a/drivers/mipi_dbi/CMakeLists.txt
+++ b/drivers/mipi_dbi/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2023 NXP
+# Copyright 2023,2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 
@@ -7,6 +7,7 @@ zephyr_sources_ifdef(CONFIG_MIPI_DBI_BITBANG mipi_dbi_bitbang.c)
 zephyr_sources_ifdef(CONFIG_MIPI_DBI_SMARTBOND mipi_dbi_smartbond.c)
 zephyr_sources_ifdef(CONFIG_MIPI_DBI_NXP_LCDIC mipi_dbi_nxp_lcdic.c)
 zephyr_sources_ifdef(CONFIG_MIPI_DBI_NXP_FLEXIO_LCDIF mipi_dbi_nxp_flexio_lcdif.c)
+zephyr_sources_ifdef(CONFIG_MIPI_DBI_NXP_DCNANO_LCDIF mipi_dbi_nxp_dcnano_lcdif.c)
 zephyr_sources_ifdef(CONFIG_MIPI_DBI_STM32_FMC mipi_dbi_stm32_fmc.c)
 # Data bus width is used by the SDK driver and processes it as a compile time option
 if(CONFIG_MIPI_DBI_NXP_FLEXIO_LCDIF)
diff --git a/drivers/mipi_dbi/Kconfig b/drivers/mipi_dbi/Kconfig
index ab3ac43c76e..71be0772dc9 100644
--- a/drivers/mipi_dbi/Kconfig
+++ b/drivers/mipi_dbi/Kconfig
@@ -1,6 +1,6 @@
 # MIPI DBI controller options
 
-# Copyright 2023 NXP
+# Copyright 2023,2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 menuconfig MIPI_DBI
@@ -27,5 +27,6 @@ source "drivers/mipi_dbi/Kconfig.smartbond"
 source "drivers/mipi_dbi/Kconfig.nxp_lcdic"
 source "drivers/mipi_dbi/Kconfig.nxp_flexio_lcdif"
 source "drivers/mipi_dbi/Kconfig.stm32_fmc"
+source "drivers/mipi_dbi/Kconfig.nxp_dcnano_lcdif"
 
 endif
diff --git a/drivers/mipi_dbi/Kconfig.nxp_dcnano_lcdif b/drivers/mipi_dbi/Kconfig.nxp_dcnano_lcdif
new file mode 100644
index 00000000000..d88b3e26f45
--- /dev/null
+++ b/drivers/mipi_dbi/Kconfig.nxp_dcnano_lcdif
@@ -0,0 +1,10 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config MIPI_DBI_NXP_DCNANO_LCDIF
+	bool "MIPI DBI driver for NXP DCnano LCDIF"
+	default y
+	depends on DT_HAS_NXP_MIPI_DBI_DCNANO_LCDIF_ENABLED
+	select PINCTRL
+	help
+	  Enable support for MIPI DBI driver for NXP FlexIO based LCDIF controller.
diff --git a/drivers/mipi_dbi/mipi_dbi_nxp_dcnano_lcdif.c b/drivers/mipi_dbi/mipi_dbi_nxp_dcnano_lcdif.c
new file mode 100644
index 00000000000..7c45e10b5eb
--- /dev/null
+++ b/drivers/mipi_dbi/mipi_dbi_nxp_dcnano_lcdif.c
@@ -0,0 +1,382 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_mipi_dbi_dcnano_lcdif
+
+#include <zephyr/drivers/display.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/mipi_dbi.h>
+#include <zephyr/dt-bindings/mipi_dbi/mipi_dbi.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <fsl_lcdif.h>
+
+LOG_MODULE_REGISTER(mipi_dbi_nxp_dcnano_lcdif, CONFIG_DISPLAY_LOG_LEVEL);
+
+struct mcux_dcnano_lcdif_dbi_data {
+	struct k_sem transfer_done;
+	const struct mipi_dbi_config *active_cfg;
+};
+
+struct mcux_dcnano_lcdif_dbi_config {
+	LCDIF_Type *base;
+	void (*irq_config_func)(const struct device *dev);
+	lcdif_dbi_config_t dbi_config;
+	lcdif_panel_config_t panel_config;
+	const struct pinctrl_dev_config *pincfg;
+	const struct gpio_dt_spec reset;
+};
+
+struct mcux_dcnano_lcdif_dbi_foramt_map_t {
+	uint8_t bus_type;
+	uint8_t color_coding;
+	lcdif_dbi_out_format_t format;
+};
+
+const struct mcux_dcnano_lcdif_dbi_foramt_map_t format_map[] = {
+	{MIPI_DBI_MODE_6800_BUS_8_BIT, MIPI_DBI_MODE_RGB332, kLCDIF_DbiOutD8RGB332},
+	{MIPI_DBI_MODE_6800_BUS_8_BIT, MIPI_DBI_MODE_RGB444, kLCDIF_DbiOutD8RGB444},
+	{MIPI_DBI_MODE_6800_BUS_8_BIT, MIPI_DBI_MODE_RGB565, kLCDIF_DbiOutD8RGB565},
+	{MIPI_DBI_MODE_6800_BUS_8_BIT, MIPI_DBI_MODE_RGB666_1, kLCDIF_DbiOutD8RGB666},
+	{MIPI_DBI_MODE_6800_BUS_8_BIT, MIPI_DBI_MODE_RGB888_1, kLCDIF_DbiOutD8RGB888},
+	{MIPI_DBI_MODE_6800_BUS_9_BIT, MIPI_DBI_MODE_RGB666_1, kLCDIF_DbiOutD9RGB666},
+	{MIPI_DBI_MODE_6800_BUS_8_BIT, MIPI_DBI_MODE_RGB666_2, kLCDIF_DbiOutD8RGB666},
+	{MIPI_DBI_MODE_6800_BUS_8_BIT, MIPI_DBI_MODE_RGB888_2, kLCDIF_DbiOutD8RGB888},
+	{MIPI_DBI_MODE_6800_BUS_9_BIT, MIPI_DBI_MODE_RGB666_2, kLCDIF_DbiOutD9RGB666},
+	{MIPI_DBI_MODE_6800_BUS_16_BIT, MIPI_DBI_MODE_RGB332, kLCDIF_DbiOutD16RGB332},
+	{MIPI_DBI_MODE_6800_BUS_16_BIT, MIPI_DBI_MODE_RGB444, kLCDIF_DbiOutD16RGB444},
+	{MIPI_DBI_MODE_6800_BUS_16_BIT, MIPI_DBI_MODE_RGB565, kLCDIF_DbiOutD16RGB565},
+	{MIPI_DBI_MODE_6800_BUS_16_BIT, MIPI_DBI_MODE_RGB666_1,
+		kLCDIF_DbiOutD16RGB666Option1},
+	{MIPI_DBI_MODE_6800_BUS_16_BIT, MIPI_DBI_MODE_RGB666_2,
+		kLCDIF_DbiOutD16RGB666Option2},
+	{MIPI_DBI_MODE_6800_BUS_16_BIT, MIPI_DBI_MODE_RGB888_1,
+		kLCDIF_DbiOutD16RGB888Option1},
+	{MIPI_DBI_MODE_6800_BUS_16_BIT, MIPI_DBI_MODE_RGB888_2,
+		kLCDIF_DbiOutD16RGB888Option2},
+};
+
+static int mcux_dcnano_lcdif_dbi_get_format(uint8_t bus_type, uint8_t color_coding,
+	lcdif_dbi_out_format_t *format)
+{
+	for (uint8_t i = 0; i < ARRAY_SIZE(format_map); i++) {
+		if ((format_map[i].bus_type == (bus_type - MIPI_DBI_MODE_6800_BUS_16_BIT)) &&
+			(format_map[i].color_coding == color_coding)) {
+			*format = format_map[i].format;
+			return 0;
+		}
+	}
+
+	return -EINVAL;
+}
+
+static void mcux_dcnano_lcdif_dbi_isr(const struct device *dev)
+{
+	const struct mcux_dcnano_lcdif_dbi_config *config = dev->config;
+	struct mcux_dcnano_lcdif_dbi_data *lcdif_data = dev->data;
+	uint32_t status;
+
+	status = LCDIF_GetAndClearInterruptPendingFlags(config->base);
+
+	if (0 != (status & kLCDIF_Display0FrameDoneInterrupt)) {
+		k_sem_give(&lcdif_data->transfer_done);
+	}
+}
+
+static int mcux_dcnano_lcdif_dbi_configure(const struct device *dev,
+					   const struct mipi_dbi_config *dbi_config)
+{
+	const struct mcux_dcnano_lcdif_dbi_config *config = dev->config;
+	struct mcux_dcnano_lcdif_dbi_data *lcdif_data = dev->data;
+	uint8_t bus_type = dbi_config->mode & 0xFU;
+	uint8_t color_coding = dbi_config->mode & 0xF0U;
+	lcdif_dbi_config_t lcdif_dbi_config = config->dbi_config;
+	status_t status;
+
+	/* No need to update if configuration is the same. */
+	if (dbi_config == lcdif_data->active_cfg) {
+		return 0;
+	}
+
+	/* SPI mode is not supported by the SDK LCDIF driver */
+	if ((bus_type == MIPI_DBI_MODE_SPI_3WIRE) ||
+		(bus_type == MIPI_DBI_MODE_SPI_4WIRE)) {
+		LOG_ERR("Bus type not supported.");
+		return -EINVAL;
+	}
+
+	/* 9-bit bus only has RGB666 color coding. */
+	if (((bus_type == MIPI_DBI_MODE_6800_BUS_9_BIT) ||
+		(bus_type == MIPI_DBI_MODE_8080_BUS_9_BIT)) &&
+		((color_coding != MIPI_DBI_MODE_RGB666_1) &&
+		(color_coding != MIPI_DBI_MODE_RGB666_2))) {
+		return -EINVAL;
+	}
+
+	/* Get the bus type */
+	switch (bus_type) {
+	case MIPI_DBI_MODE_6800_BUS_16_BIT:
+	case MIPI_DBI_MODE_6800_BUS_9_BIT:
+	case MIPI_DBI_MODE_6800_BUS_8_BIT:
+		lcdif_dbi_config.type = kLCDIF_DbiTypeA_FixedE;
+		break;
+	case MIPI_DBI_MODE_8080_BUS_16_BIT:
+	case MIPI_DBI_MODE_8080_BUS_9_BIT:
+	case MIPI_DBI_MODE_8080_BUS_8_BIT:
+		lcdif_dbi_config.type = kLCDIF_DbiTypeB;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* Get the color cosing */
+	status = mcux_dcnano_lcdif_dbi_get_format(bus_type, color_coding,
+		&lcdif_dbi_config.format);
+
+	if (kStatus_Success != status) {
+		return -EINVAL;
+	}
+
+	/* Update DBI configuration. */
+	status = LCDIF_DbiModeSetConfig(config->base, 0, &lcdif_dbi_config);
+
+	if (kStatus_Success != status) {
+		return -EINVAL;
+	}
+
+	lcdif_data->active_cfg = dbi_config;
+
+	return 0;
+}
+
+static int mcux_dcnano_lcdif_dbi_init(const struct device *dev)
+{
+	const struct mcux_dcnano_lcdif_dbi_config *config = dev->config;
+	struct mcux_dcnano_lcdif_dbi_data *lcdif_data = dev->data;
+
+#ifndef CONFIG_MIPI_DSI_MCUX_NXP_DCNANO_LCDIF
+	int ret;
+
+	/* Pin control is not applied when DCNano is used in MCUX DSI driver. */
+	ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
+	if (ret) {
+		return ret;
+	}
+#endif
+
+	LCDIF_Init(config->base);
+
+	LCDIF_DbiModeSetConfig(config->base, 0, &config->dbi_config);
+
+	LCDIF_SetPanelConfig(config->base, 0, &config->panel_config);
+
+	LCDIF_EnableInterrupts(config->base, kLCDIF_Display0FrameDoneInterrupt);
+
+	config->irq_config_func(dev);
+
+	k_sem_init(&lcdif_data->transfer_done, 0, 1);
+
+	LOG_DBG("%s device init complete", dev->name);
+
+	return 0;
+}
+
+static int mipi_dbi_dcnano_lcdif_write_display(const struct device *dev,
+						   const struct mipi_dbi_config *dbi_config,
+						   const uint8_t *framebuf,
+						   struct display_buffer_descriptor *desc,
+						   enum display_pixel_format pixfmt)
+{
+	const struct mcux_dcnano_lcdif_dbi_config *config = dev->config;
+	struct mcux_dcnano_lcdif_dbi_data *lcdif_data = dev->data;
+	int ret = 0;
+	uint8_t bytes_per_pixel = 0U;
+
+	/* The DBI bus type and color coding. */
+	ret = mcux_dcnano_lcdif_dbi_configure(dev, dbi_config);
+
+	if (ret) {
+		return ret;
+	}
+
+	lcdif_fb_config_t fbConfig;
+
+	LCDIF_FrameBufferGetDefaultConfig(&fbConfig);
+
+	fbConfig.enable		= true;
+	fbConfig.inOrder	= kLCDIF_PixelInputOrderARGB;
+	fbConfig.rotateFlipMode	= kLCDIF_Rotate0;
+	switch (pixfmt) {
+	case PIXEL_FORMAT_RGB_888:
+		fbConfig.format = kLCDIF_PixelFormatRGB888;
+		bytes_per_pixel = 3U;
+		break;
+	case PIXEL_FORMAT_ARGB_8888:
+		fbConfig.format = kLCDIF_PixelFormatARGB8888;
+		bytes_per_pixel = 4U;
+		break;
+	case PIXEL_FORMAT_BGR_565:
+		fbConfig.inOrder = kLCDIF_PixelInputOrderABGR;
+	case PIXEL_FORMAT_RGB_565:
+		fbConfig.format = kLCDIF_PixelFormatRGB565;
+		bytes_per_pixel = 2U;
+		break;
+	default:
+		LOG_ERR("Bus tyoe not supported.");
+		ret = -ENODEV;
+		break;
+	}
+
+	if (ret) {
+		return ret;
+	}
+
+	fbConfig.alpha.enable	 = false;
+	fbConfig.colorkey.enable = false;
+	fbConfig.topLeftX	 = 0U;
+	fbConfig.topLeftY	 = 0U;
+	fbConfig.width		 = desc->width;
+	fbConfig.height = desc->height;
+
+	LCDIF_SetFrameBufferConfig(config->base, 0, &fbConfig);
+
+	if (bytes_per_pixel == 3U) {
+		/* For RGB888 the stride shall be calculated as
+		 * 4 bytes per pixel instead of 3.
+		 */
+		LCDIF_SetFrameBufferStride(config->base, 0, 4U * desc->pitch);
+	} else {
+		LCDIF_SetFrameBufferStride(config->base, 0, bytes_per_pixel * desc->pitch);
+	}
+
+	/* Set the updated area's size according to desc. */
+	LCDIF_SetFrameBufferPosition(config->base, 0U, 0U, 0U, desc->width,
+								desc->height);
+
+	LCDIF_DbiSelectArea(config->base, 0, 0, 0, desc->width - 1U,
+						desc->height - 1U, false);
+
+	LCDIF_SetFrameBufferAddr(config->base, 0, (uint32_t)framebuf);
+
+	/* Enable DMA and send out data. */
+	LCDIF_DbiWriteMem(config->base, 0);
+
+	/* Wait for transfer done. */
+	k_sem_take(&lcdif_data->transfer_done, K_FOREVER);
+
+	return 0;
+}
+
+static int mipi_dbi_dcnano_lcdif_command_write(const struct device *dev,
+						   const struct mipi_dbi_config *dbi_config,
+						   uint8_t cmd, const uint8_t *data_buf,
+						   size_t len)
+{
+	const struct mcux_dcnano_lcdif_dbi_config *config = dev->config;
+	int ret = 0;
+
+	/* The DBI bus type and color coding. */
+	ret = mcux_dcnano_lcdif_dbi_configure(dev, dbi_config);
+
+	if (ret) {
+		return ret;
+	}
+
+	LCDIF_DbiSendCommand(config->base, 0U, cmd);
+
+	if (len != 0U) {
+		LCDIF_DbiSendData(config->base, 0U, data_buf, len);
+	}
+
+	return kStatus_Success;
+}
+
+static int mipi_dbi_dcnano_lcdif_reset(const struct device *dev, k_timeout_t delay)
+{
+	int ret;
+
+	const struct mcux_dcnano_lcdif_dbi_config *config = dev->config;
+
+	/* Check if a reset port is provided to reset the LCD controller */
+	if (config->reset.port == NULL) {
+		return 0;
+	}
+
+	/* Reset the LCD controller. */
+	ret = gpio_pin_configure_dt(&config->reset, GPIO_OUTPUT_HIGH);
+	if (ret) {
+		return ret;
+	}
+
+	ret = gpio_pin_set_dt(&config->reset, 0);
+	if (ret < 0) {
+		return ret;
+	}
+
+	k_sleep(delay);
+
+	ret = gpio_pin_set_dt(&config->reset, 1);
+	if (ret < 0) {
+		return ret;
+	}
+
+	LOG_DBG("%s device reset complete", dev->name);
+
+	return 0;
+}
+
+static struct mipi_dbi_driver_api mcux_dcnano_lcdif_dbi_api = {
+	.reset = mipi_dbi_dcnano_lcdif_reset,
+	.command_write = mipi_dbi_dcnano_lcdif_command_write,
+	.write_display = mipi_dbi_dcnano_lcdif_write_display,
+};
+
+#define MCUX_DCNANO_LCDIF_DEVICE_INIT(n)						\
+	static void mcux_dcnano_lcdif_dbi_config_func_##n(const struct device *dev)	\
+	{										\
+		IRQ_CONNECT(DT_INST_IRQN(n),						\
+				DT_INST_IRQ(n, priority),				\
+				mcux_dcnano_lcdif_dbi_isr,				\
+				DEVICE_DT_INST_GET(n),					\
+				0);							\
+		irq_enable(DT_INST_IRQN(n));						\
+	}										\
+	PINCTRL_DT_INST_DEFINE(n);							\
+	struct mcux_dcnano_lcdif_dbi_data mcux_dcnano_lcdif_dbi_data_##n;		\
+	struct mcux_dcnano_lcdif_dbi_config mcux_dcnano_lcdif_dbi_config_##n = {	\
+		.base = (LCDIF_Type *) DT_INST_REG_ADDR(n),				\
+		.irq_config_func = mcux_dcnano_lcdif_dbi_config_func_##n,		\
+		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),				\
+		.reset = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {0}),			\
+		.dbi_config = {								\
+			.type = kLCDIF_DbiTypeA_FixedE,					\
+			.swizzle = DT_INST_ENUM_IDX_OR(n, swizzle, 0),			\
+			.format = kLCDIF_DbiOutD8RGB332,				\
+			.acTimeUnit = DT_INST_PROP_OR(n, divider, 1) - 1,		\
+			.writeWRPeriod = DT_INST_PROP(n, wr_period),			\
+			.writeWRAssert = DT_INST_PROP(n, wr_assert),			\
+			.writeWRDeassert = DT_INST_PROP(n, wr_deassert),		\
+			.writeCSAssert = DT_INST_PROP(n, cs_assert),			\
+			.writeCSDeassert = DT_INST_PROP(n, cs_deassert),		\
+		},									\
+		.panel_config = {							\
+			.enable = true,							\
+			.enableGamma = false,						\
+			.order = kLCDIF_VideoOverlay0Overlay1,				\
+			.endian = DT_INST_ENUM_IDX_OR(n, endian, 0),			\
+		},									\
+	};										\
+	DEVICE_DT_INST_DEFINE(n,							\
+		&mcux_dcnano_lcdif_dbi_init,						\
+		NULL,									\
+		&mcux_dcnano_lcdif_dbi_data_##n,					\
+		&mcux_dcnano_lcdif_dbi_config_##n,					\
+		POST_KERNEL,								\
+		CONFIG_MIPI_DBI_INIT_PRIORITY,						\
+		&mcux_dcnano_lcdif_dbi_api);
+
+DT_INST_FOREACH_STATUS_OKAY(MCUX_DCNANO_LCDIF_DEVICE_INIT)
diff --git a/drivers/mipi_dbi/mipi_dbi_spi.c b/drivers/mipi_dbi/mipi_dbi_spi.c
index b6a6857c381..85cba935dff 100644
--- a/drivers/mipi_dbi/mipi_dbi_spi.c
+++ b/drivers/mipi_dbi/mipi_dbi_spi.c
@@ -1,6 +1,6 @@
 /*
  * Copyright 2023 NXP
- * Copyright 2024 TiaC Systems
+ * Copyright 2024-2025 TiaC Systems
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -33,26 +33,28 @@ struct mipi_dbi_spi_data {
 };
 
 /* Expands to 1 if the node does not have the `write-only` property */
-#define _WRITE_ONLY_ABSENT(n) (!DT_INST_PROP(n, write_only)) |
+#define MIPI_DBI_SPI_WRITE_ONLY_ABSENT(n) (!DT_INST_PROP(n, write_only)) |
 
 /* This macro will evaluate to 1 if any of the nodes with zephyr,mipi-dbi-spi
  * lack a `write-only` property. The intention here is to allow the entire
  * command_read function to be optimized out when it is not needed.
  */
-#define MIPI_DBI_SPI_READ_REQUIRED DT_INST_FOREACH_STATUS_OKAY(_WRITE_ONLY_ABSENT) 0
+#define MIPI_DBI_SPI_READ_REQUIRED DT_INST_FOREACH_STATUS_OKAY(MIPI_DBI_SPI_WRITE_ONLY_ABSENT) 0
 uint32_t var = MIPI_DBI_SPI_READ_REQUIRED;
 
 /* Expands to 1 if the node does reflect the enum in `xfr-min-bits` property */
-#define _XFR_8BITS(n) (DT_INST_PROP(n, xfr_min_bits) == MIPI_DBI_SPI_XFR_8BIT) |
-#define _XFR_16BITS(n) (DT_INST_PROP(n, xfr_min_bits) == MIPI_DBI_SPI_XFR_16BIT) |
+#define MIPI_DBI_SPI_XFR_8BITS(n) (DT_INST_STRING_UPPER_TOKEN(n, xfr_min_bits) \
+						== MIPI_DBI_SPI_XFR_8BIT) |
+#define MIPI_DBI_SPI_XFR_16BITS(n) (DT_INST_STRING_UPPER_TOKEN(n, xfr_min_bits) \
+						== MIPI_DBI_SPI_XFR_16BIT) |
 
 /* This macros will evaluate to 1 if any of the nodes with zephyr,mipi-dbi-spi
  * have the `xfr-min-bits` property to corresponding enum value. The intention
  * here is to allow the write helper functions to be optimized out when not all
  * minimum transfer bits will be needed.
  */
-#define MIPI_DBI_SPI_WRITE_8BIT_REQUIRED DT_INST_FOREACH_STATUS_OKAY(_XFR_8BITS) 0
-#define MIPI_DBI_SPI_WRITE_16BIT_REQUIRED DT_INST_FOREACH_STATUS_OKAY(_XFR_16BITS) 0
+#define MIPI_DBI_SPI_WRITE_8BIT_REQUIRED DT_INST_FOREACH_STATUS_OKAY(MIPI_DBI_SPI_XFR_8BITS) 0
+#define MIPI_DBI_SPI_WRITE_16BIT_REQUIRED DT_INST_FOREACH_STATUS_OKAY(MIPI_DBI_SPI_XFR_16BITS) 0
 
 /* In Type C mode 1 MIPI BIT communication, the 9th bit of the word
  * (first bit sent in each word) indicates if the word is a command or
@@ -560,7 +562,7 @@ static DEVICE_API(mipi_dbi, mipi_dbi_spi_driver_api) = {
 				    DT_INST_PHANDLE(n, spi_dev)),		\
 		    .cmd_data = GPIO_DT_SPEC_INST_GET_OR(n, dc_gpios, {}),	\
 		    .reset = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {}),	\
-		    .xfr_min_bits = DT_INST_PROP(n, xfr_min_bits)               \
+		    .xfr_min_bits = DT_INST_STRING_UPPER_TOKEN(n, xfr_min_bits) \
 	};									\
 	static struct mipi_dbi_spi_data mipi_dbi_spi_data_##n;			\
 										\
diff --git a/drivers/mipi_dsi/Kconfig.mcux b/drivers/mipi_dsi/Kconfig.mcux
index 17d8d437dfe..af624e6ac10 100644
--- a/drivers/mipi_dsi/Kconfig.mcux
+++ b/drivers/mipi_dsi/Kconfig.mcux
@@ -26,6 +26,14 @@ config MIPI_DSI_MCUX_2L_SMARTDMA
 	  convert RGB565 input data to BGR565 (little endian to big endian),
 	  and write it to the MIPI DSI.
 
+config MIPI_DSI_MCUX_NXP_DCNANO_LCDIF
+	bool "Use NXP DCNano DBI controller with MIPI DSI"
+	default y
+	depends on DT_HAS_NXP_MIPI_DBI_DCNANO_LCDIF_ENABLED
+	select MIPI_DBI
+	help
+	  Use DCNano DBI controller for the data transfer.
+
 config MIPI_DSI_MCUX_2L_SWAP16
 	bool "Swap 16 byte color"
 	help
diff --git a/drivers/mipi_dsi/dsi_mcux_2l.c b/drivers/mipi_dsi/dsi_mcux_2l.c
index 9adfc19b838..f664974620b 100644
--- a/drivers/mipi_dsi/dsi_mcux_2l.c
+++ b/drivers/mipi_dsi/dsi_mcux_2l.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2023, NXP
+ * Copyright 2023,2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,17 +16,24 @@
 #include <zephyr/drivers/dma/dma_mcux_smartdma.h>
 #include <zephyr/logging/log.h>
 
-#include <fsl_inputmux.h>
 #include <fsl_mipi_dsi.h>
 #include <fsl_clock.h>
 #ifdef CONFIG_MIPI_DSI_MCUX_2L_SMARTDMA
+#include <fsl_inputmux.h>
 #include <fsl_smartdma.h>
 #endif
+#ifdef CONFIG_MIPI_DSI_MCUX_NXP_DCNANO_LCDIF
+#include <zephyr/drivers/mipi_dbi.h>
+#endif
 
 #include <soc.h>
 
 LOG_MODULE_REGISTER(dsi_mcux_host, CONFIG_MIPI_DSI_LOG_LEVEL);
 
+#if CONFIG_MIPI_DSI_MCUX_NXP_DCNANO_LCDIF
+#define MIPI_DSI_MAX_PAYLOAD_SIZE 0xFFFF
+#endif
+
 struct mcux_mipi_dsi_config {
 	MIPI_DSI_HOST_Type *base;
 	dsi_dpi_config_t dpi_config;
@@ -44,22 +51,70 @@ struct mcux_mipi_dsi_config {
 #else
 	void (*irq_config_func)(const struct device *dev);
 #endif
+#ifdef CONFIG_MIPI_DSI_MCUX_NXP_DCNANO_LCDIF
+	const struct device *mipi_dbi;
+#endif
 };
 
 struct mcux_mipi_dsi_data {
 	dsi_handle_t mipi_handle;
 	struct k_sem transfer_sem;
+	uint16_t flags;
+	uint8_t lane_mask;
+#if DT_PROP(DT_NODELABEL(mipi_dsi), ulps_control)
+	uint32_t delay_hs_to_ulps_ns;
+	uint32_t delay_lp_to_ulps_ns;
+#endif
 #ifdef CONFIG_MIPI_DSI_MCUX_2L_SMARTDMA
 	smartdma_dsi_param_t smartdma_params __aligned(4);
 	uint32_t smartdma_stack[32];
 	uint8_t dma_slot;
 #endif
+#ifdef CONFIG_MIPI_DSI_MCUX_NXP_DCNANO_LCDIF
+	uint32_t width;
+	uint32_t height;
+	uint8_t src_bytes_per_pixel;
+#endif
 };
 
 
 /* MAX DSI TX payload */
 #define DSI_TX_MAX_PAYLOAD_BYTE (64U * 4U)
 
+static void dsi_mcux_transfer_prepare(const struct device *dev)
+{
+#if DT_PROP(DT_NODELABEL(mipi_dsi), ulps_control)
+	const struct mcux_mipi_dsi_config *config = dev->config;
+
+	/* If in ULPS state, exit before transfer. */
+	if (DSI_GetUlpsStatus(config->base) != 0U) {
+		DSI_SetUlpsStatus(config->base, 0U);
+		while (DSI_GetUlpsStatus(config->base) != 0U) {
+		}
+	}
+#endif
+}
+
+static void dsi_mcux_transfer_complete(const struct device *dev)
+{
+#if DT_PROP(DT_NODELABEL(mipi_dsi), ulps_control)
+	const struct mcux_mipi_dsi_config *config = dev->config;
+	struct mcux_mipi_dsi_data *data = dev->data;
+
+	/* Enter ulps state after transfer completes. */
+	if ((data->flags & MCUX_DSI_2L_ULPS) != 0U) {
+		/* It is necessary to delay a period. */
+		if (data->flags & MIPI_DSI_MSG_USE_LPM) {
+			k_busy_wait(data->delay_lp_to_ulps_ns / 1000U);
+		} else {
+			k_busy_wait(data->delay_hs_to_ulps_ns / 1000U);
+		}
+		DSI_SetUlpsStatus(config->base, data->lane_mask);
+		while (DSI_GetUlpsStatus(config->base) != data->lane_mask) {
+		}
+	}
+#endif
+}
 
 #ifdef CONFIG_MIPI_DSI_MCUX_2L_SMARTDMA
 
@@ -81,6 +136,8 @@ static void dsi_mcux_dma_cb(const struct device *dma_dev,
 		DSI_GetAndClearInterruptStatus(config->base, &int_flags1, &int_flags2);
 		k_sem_give(&data->transfer_sem);
 	}
+
+	dsi_mcux_transfer_complete(dev);
 }
 
 /* Helper function to transfer DSI color (DMA based implementation) */
@@ -146,12 +203,119 @@ static int dsi_mcux_tx_color(const struct device *dev, uint8_t channel,
 static void dsi_transfer_complete(MIPI_DSI_HOST_Type *base,
 	dsi_handle_t *handle, status_t status, void *userData)
 {
-	struct mcux_mipi_dsi_data *data = userData;
+	struct device *dev = userData;
+	struct mcux_mipi_dsi_data *data = dev->data;
+
+	dsi_mcux_transfer_complete(dev);
 
 	k_sem_give(&data->transfer_sem);
 }
 
+#ifdef CONFIG_MIPI_DSI_MCUX_NXP_DCNANO_LCDIF
+static status_t dsi_mcux_dcnano_transfer(const struct device *dev, uint8_t channel,
+				 struct mipi_dsi_msg *msg, dsi_transfer_t *dsi_xfer)
+{
+	const struct mcux_mipi_dsi_config *config = dev->config;
+	struct mcux_mipi_dsi_data *data = dev->data;
+	uint8_t *tx_buf = (uint8_t *)msg->tx_buf;
+
+	/* Record the bpp, width, height of the buffer according to command. They are
+	 * necessary to configure the DCNano DBI in the following memory write.
+	 */
+	if (channel == 0U) {
+		if (msg->cmd == MIPI_DCS_SET_PIXEL_FORMAT) {
+			if (tx_buf[0] == MIPI_DCS_PIXEL_FORMAT_16BIT) {
+				data->src_bytes_per_pixel = 2U;
+			} else {
+				data->src_bytes_per_pixel = 3U;
+			}
+		} else if (msg->cmd == MIPI_DCS_SET_COLUMN_ADDRESS) {
+			data->width = ((tx_buf[2] << 8U) | tx_buf[3]) -
+				((tx_buf[0] << 8U) | tx_buf[1]) + 1U;
+		} else if (msg->cmd == MIPI_DCS_SET_PAGE_ADDRESS) {
+			data->height = ((tx_buf[2] << 8U) | tx_buf[3]) -
+				((tx_buf[0] << 8U) | tx_buf[1]) + 1U;
+		}
+	}
+
+	/* When the DSI channel is 0, for and only for DCS long write like
+	 * MIPI_DCS_WRITE_MEMORY_START or MIPI_DCS_WRITE_MEMORY_CONTINUE, we can
+	 * use DCNano DBI to speed up the frame buffer write. The DCS command and the
+	 * following data are all handled by DCNano DBI, while on MIPI-DSI side special
+	 * handling shall be done so that it can be properly used with DCNano DBI,
+	 * like MIPI DBI FIFO configuration of send level and payload size, etc.
+	 */
+	if (((msg->cmd == MIPI_DCS_WRITE_MEMORY_START) ||
+		(msg->cmd == MIPI_DCS_WRITE_MEMORY_CONTINUE)) && (channel == 0U)) {
+		enum display_pixel_format pixfmt;
+		struct mipi_dbi_config dbi_config = {
+			.mode = MIPI_DBI_MODE_8080_BUS_16_BIT,
+		};
+		struct display_buffer_descriptor desc = {
+			.width = data->width,
+			.height = data->height,
+			.pitch = data->width,
+		};
+
+		/* Every time buffer 64 pixels first before the transfer. */
+		DSI_SetDbiPixelFifoSendLevel(config->base, 64U);
+
+		/* Set payload size. */
+		if ((desc.height * desc.width * data->src_bytes_per_pixel) >
+			MIPI_DSI_MAX_PAYLOAD_SIZE) {
+			desc.height = MIPI_DSI_MAX_PAYLOAD_SIZE /
+				(desc.width * data->src_bytes_per_pixel);
+		}
+
+		DSI_SetDbiPixelPayloadSize(config->base,
+			(desc.height * desc.width * data->src_bytes_per_pixel) >> 1U);
+
+		/* Get the source buffer pixel format and DBI output format
+		 * Currently only support RGB565 and RGB888 when using DCNano DBI.
+		 */
+		switch (data->src_bytes_per_pixel) {
+		case 2:
+			pixfmt = PIXEL_FORMAT_RGB_565;
+			dbi_config.mode |= MIPI_DBI_MODE_RGB565;
+			DSI_SetDbiPixelFormat(config->base, kDSI_DbiRGB565);
+			break;
+		case 3:
+			pixfmt = PIXEL_FORMAT_RGB_888;
+			/* If using the DBI, only RGB888 option 1 is supported. */
+			dbi_config.mode |= MIPI_DBI_MODE_RGB888_1;
+			DSI_SetDbiPixelFormat(config->base, kDSI_DbiRGB888);
+			break;
+		default:
+			/* MIPI-DSI do not support other format of DBI pixel. */
+			LOG_ERR("Pixel type not supported yet.");
+			return -EIO;
+		}
+
+		/* Send the command first. */
+		if (msg->cmd == MIPI_DCS_WRITE_MEMORY_START) {
+			mipi_dbi_command_write(config->mipi_dbi, &dbi_config,
+				MIPI_DCS_WRITE_MEMORY_START, NULL, 0);
+		} else {
+			mipi_dbi_command_write(config->mipi_dbi, &dbi_config,
+				MIPI_DCS_WRITE_MEMORY_CONTINUE, NULL, 0);
+		}
+
+		/* Send the frame buffer data. */
+		mipi_dbi_write_display(config->mipi_dbi, &dbi_config, msg->tx_buf,
+			&desc, pixfmt);
+
+		msg->tx_len = desc.height * desc.width * data->src_bytes_per_pixel;
+	} else {
+		/* For other DCS commands, the DCNano DBI cannot be used. */
+		if (DSI_TransferBlocking(config->base, dsi_xfer) != kStatus_Success) {
+			LOG_ERR("Transmission failed");
+			return -EIO;
+		}
+	}
 
+	return 0;
+}
+#else
 /* Helper function to transfer DSI color (Interrupt based implementation) */
 static int dsi_mcux_tx_color(const struct device *dev, uint8_t channel,
 			     struct mipi_dsi_msg *msg)
@@ -201,6 +365,7 @@ static int dsi_mcux_tx_color(const struct device *dev, uint8_t channel,
 	}
 	return xfer.txDataSize;
 }
+#endif
 
 /* ISR is used for DSI interrupt based implementation, unnecessary if DMA is used */
 static int mipi_dsi_isr(const struct device *dev)
@@ -219,6 +384,7 @@ static int dsi_mcux_attach(const struct device *dev,
 			   const struct mipi_dsi_device *mdev)
 {
 	const struct mcux_mipi_dsi_config *config = dev->config;
+	struct mcux_mipi_dsi_data *data = dev->data;
 	dsi_dphy_config_t dphy_config;
 	dsi_config_t dsi_config;
 	uint32_t dphy_bit_clk_freq;
@@ -250,8 +416,6 @@ static int dsi_mcux_attach(const struct device *dev,
 		return -ENODEV;
 	}
 
-	struct mcux_mipi_dsi_data *data = dev->data;
-
 	switch (mdev->pixfmt) {
 	case MIPI_DSI_PIXFMT_RGB888:
 		data->dma_slot = kSMARTDMA_MIPI_RGB888_DMA;
@@ -277,15 +441,30 @@ static int dsi_mcux_attach(const struct device *dev,
 				(uint8_t *)s_smartdmaDisplayFirmware,
 				s_smartdmaDisplayFirmwareSize);
 #else
-	struct mcux_mipi_dsi_data *data = dev->data;
-
 	/* Create transfer handle */
 	if (DSI_TransferCreateHandle(config->base, &data->mipi_handle,
-				dsi_transfer_complete, data) != kStatus_Success) {
+				dsi_transfer_complete, (void *)dev) != kStatus_Success) {
 		return -ENODEV;
 	}
 #endif
 
+#if DT_PROP(DT_NODELABEL(mipi_dsi), ulps_control)
+	/* Get how many lanes are enabled. */
+	uint8_t data_lanes = mdev->data_lanes;
+
+	/* Calculate the lane mask. */
+	data->lane_mask = 2U;
+	while (data_lanes--) {
+		data->lane_mask <<= 1U;
+	}
+	data->lane_mask--;
+
+	/* Clock lane cannot go into ULPS if not in non-continuous mode. */
+	if (!dsi_config.enableNonContinuousHsClk) {
+		data->lane_mask &= ~0x1U;
+	}
+#endif
+
 	/* Get the DPHY bit clock frequency */
 	if (clock_control_get_rate(config->bit_clk_dev,
 				config->bit_clk_subsys,
@@ -353,6 +532,47 @@ static int dsi_mcux_attach(const struct device *dev,
 						dsi_pixel_clk_freq, dphy_bit_clk_freq);
 	}
 
+#if DT_PROP(DT_NODELABEL(mipi_dsi), ulps_control)
+	/* Calculate the delay before entering ULPS. After the last cycle of data has
+	 * been accepted from the controller to the PHY, the data still needs to be
+	 * serialized, transmitted, then the appropriate timing must be met before
+	 * entering the ULPS. The data lane rate can impact this, so calcuate the time
+	 * it takes for one data lane to send 1 bit in HS and LP mode first.
+	 */
+	uint32_t hs_bit_ns = 1000000000UL / dphy_bit_clk_freq;
+	uint32_t lp_bit_ns = 1000000000UL / dphy_esc_clk_freq;
+
+	/* When the clock is in non-continuous mode, the formula for the delay after
+	 * HS transmit would be:
+	 * delay = 4*(UI*8) + m_prg_hs_trail*(UI*8) + 2*TxClkEsc_period +
+	 * (cfg_t_post+2)*(UI*8) + mc_prg_hs_trail*(UI*8) + 2*TxClkEsc_period.
+	 * Similarly, the delay after LP transmit would be:
+	 * 4*(UI*8) + 2*TxClkEsc_period + TxClkEsc_period + 2*TxClkEsc_period.
+	 */
+	if (dsi_config.enableNonContinuousHsClk) {
+		data->delay_hs_to_ulps_ns = 4U * 8U * hs_bit_ns / dsi_config.numLanes +
+			dphy_config.tHsTrail_ByteClk * 8U * hs_bit_ns +
+			2U * lp_bit_ns +
+			(dphy_config.tClkPost_ByteClk + 2U) * hs_bit_ns +
+			dphy_config.tClkTrail_ByteClk * 8U * hs_bit_ns +
+			2U * lp_bit_ns;
+		data->delay_lp_to_ulps_ns = (2U + 1U + 2U) * lp_bit_ns +
+			4U * 8U * lp_bit_ns / dsi_config.numLanes;
+	/* When the clock is in continuous mode, the formula for the delay after
+	 * HS transmit would be:
+	 * delay = 4*(UI*8) + m_prg_hs_trail*(UI*8) + 2*TxClkEsc_period.
+	 * Similarly, the delay after LP transmit would be:
+	 * delay = 4*(UI*8) + 2*TxClkEsc_period + TxClkEsc_period.
+	 */
+	} else {
+		data->delay_hs_to_ulps_ns = 2U * lp_bit_ns +
+			4U * 8U * hs_bit_ns / dsi_config.numLanes +
+			dphy_config.tHsTrail_ByteClk * 8U * hs_bit_ns;
+		data->delay_lp_to_ulps_ns = (2U + 1U) * lp_bit_ns +
+			4U * 8U * lp_bit_ns / dsi_config.numLanes;
+	}
+#endif
+
 	imxrt_post_init_display_interface();
 
 	return 0;
@@ -379,10 +599,16 @@ static int dsi_mcux_detach(const struct device *dev, uint8_t channel,
 static ssize_t dsi_mcux_transfer(const struct device *dev, uint8_t channel,
 				 struct mipi_dsi_msg *msg)
 {
+#if DT_PROP(DT_NODELABEL(mipi_dsi), ulps_control)
+	struct mcux_mipi_dsi_data *data = dev->data;
+#endif
+
+#ifndef CONFIG_MIPI_DSI_MCUX_NXP_DCNANO_LCDIF
 	const struct mcux_mipi_dsi_config *config = dev->config;
+#endif
+
 	dsi_transfer_t dsi_xfer = {0};
 	status_t status;
-	int ret;
 
 	dsi_xfer.virtualChannel = channel;
 	dsi_xfer.txDataSize = msg->tx_len;
@@ -392,6 +618,15 @@ static ssize_t dsi_mcux_transfer(const struct device *dev, uint8_t channel,
 	/* default to high speed unless told to use low power */
 	dsi_xfer.flags = (msg->flags & MIPI_DSI_MSG_USE_LPM) ? 0 : kDSI_TransferUseHighSpeed;
 
+#if DT_PROP(DT_NODELABEL(mipi_dsi), ulps_control)
+	data->flags = (msg->flags & MIPI_DSI_MSG_USE_LPM) ? MIPI_DSI_MSG_USE_LPM : 0U;
+	if (msg->flags & MCUX_DSI_2L_ULPS) {
+		data->flags |= MCUX_DSI_2L_ULPS;
+	}
+#endif
+
+	dsi_mcux_transfer_prepare(dev);
+
 	switch (msg->type) {
 	case MIPI_DSI_DCS_READ:
 		LOG_ERR("DCS Read not yet implemented or used");
@@ -410,6 +645,9 @@ static ssize_t dsi_mcux_transfer(const struct device *dev, uint8_t channel,
 		dsi_xfer.sendDscCmd = true;
 		dsi_xfer.dscCmd = msg->cmd;
 		dsi_xfer.txDataType = kDSI_TxDataDcsLongWr;
+#ifndef CONFIG_MIPI_DSI_MCUX_NXP_DCNANO_LCDIF
+		int ret;
+
 		if (msg->flags & MCUX_DSI_2L_FB_DATA) {
 			/*
 			 * Special case- transfer framebuffer data using
@@ -423,6 +661,7 @@ static ssize_t dsi_mcux_transfer(const struct device *dev, uint8_t channel,
 			}
 			return ret;
 		}
+#endif
 		break;
 	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
 		dsi_xfer.txDataType = kDSI_TxDataGenShortWrNoParam;
@@ -448,12 +687,19 @@ static ssize_t dsi_mcux_transfer(const struct device *dev, uint8_t channel,
 		return -ENOTSUP;
 	}
 
+#ifdef CONFIG_MIPI_DSI_MCUX_NXP_DCNANO_LCDIF
+	status = dsi_mcux_dcnano_transfer(dev, channel, msg, &dsi_xfer);
+#else
 	status = DSI_TransferBlocking(config->base, &dsi_xfer);
+#endif
+
 	if (status != kStatus_Success) {
 		LOG_ERR("Transmission failed");
 		return -EIO;
 	}
 
+	dsi_mcux_transfer_complete(dev);
+
 	if (msg->rx_len != 0) {
 		/* Return rx_len on a read */
 		return msg->rx_len;
@@ -533,6 +779,8 @@ static int mcux_mipi_dsi_init(const struct device *dev)
 		COND_CODE_1(CONFIG_MIPI_DSI_MCUX_2L_SMARTDMA,					\
 		(.smart_dma = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(id, smartdma)),),		\
 		(.irq_config_func = mipi_dsi_##n##_irq_config_func,))				\
+		COND_CODE_1(CONFIG_MIPI_DSI_MCUX_NXP_DCNANO_LCDIF,				\
+		(.mipi_dbi = DEVICE_DT_GET(DT_NODELABEL(zephyr_lcdif)),), ())			\
 		.base = (MIPI_DSI_HOST_Type *)DT_INST_REG_ADDR(id),				\
 		.auto_insert_eotp = DT_INST_PROP(id, autoinsert_eotp),				\
 		.noncontinuous_hs_clk = DT_INST_PROP(id, noncontinuous_hs_clk),			\
diff --git a/drivers/mipi_dsi/dsi_renesas_ra.c b/drivers/mipi_dsi/dsi_renesas_ra.c
index 608bbb6867f..8087284b8f2 100644
--- a/drivers/mipi_dsi/dsi_renesas_ra.c
+++ b/drivers/mipi_dsi/dsi_renesas_ra.c
@@ -1,46 +1,20 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #define DT_DRV_COMPAT renesas_ra_mipi_dsi
 
-#include <zephyr/device.h>
-#include <zephyr/devicetree.h>
-#include <zephyr/drivers/clock_control.h>
+#include <soc.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
 #include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
-#include <zephyr/drivers/gpio.h>
 #include <zephyr/drivers/mipi_dsi.h>
-#include <zephyr/drivers/reset.h>
-#include <zephyr/irq.h>
-#include <zephyr/logging/log.h>
 #include "r_mipi_dsi.h"
-#include "r_mipi_phy.h"
 
 LOG_MODULE_REGISTER(dsi_renesas_ra, CONFIG_MIPI_DSI_LOG_LEVEL);
 
-/* MIPI PHY Macros */
-#define MIPI_PHY_CLKSTPT (1183)
-#define MIPI_PHY_CLKBFHT (11)
-#define MIPI_PHY_CLKKPT  (26)
-#define MIPI_PHY_GOLPBKT (40)
-
-#define MIPI_PHY_TINIT     (71999)
-#define MIPI_PHY_TCLKPREP  (8)
-#define MIPI_PHY_THSPREP   (5)
-#define MIPI_PHY_TCLKTRAIL (7)
-#define MIPI_PHY_TCLKPOST  (19)
-#define MIPI_PHY_TCLKPRE   (1)
-#define MIPI_PHY_TCLKZERO  (27)
-#define MIPI_PHY_THSEXIT   (11)
-#define MIPI_PHY_THSTRAIL  (8)
-#define MIPI_PHY_THSZERO   (19)
-#define MIPI_PHY_TLPEXIT   (7)
-#define LP_DIVISOR         (4)
-#define PLL_MUL_SETTING    (49)
-#define VIDEO_MODE_DELAY   (186)
-#define ULPS_WAKEUP_PERIOD (97)
 struct mipi_dsi_renesas_ra_config {
 	const struct device *clock_dev;
 	struct clock_control_ra_subsys_cfg clock_dsi_subsys;
@@ -50,40 +24,20 @@ struct mipi_dsi_renesas_ra_config {
 struct mipi_dsi_renesas_ra_data {
 	mipi_dsi_instance_ctrl_t mipi_dsi_ctrl;
 	mipi_dsi_cfg_t mipi_dsi_cfg;
-	volatile bool message_sent;
-	volatile bool fatal_error;
+	struct k_sem in_transmission;
+	atomic_t status;
 };
 
-void mipi_dsi_seq0(void);
-void mipi_dsi_ferr(void);
-void mipi_dsi_callback(mipi_dsi_callback_args_t *p_args);
-
-typedef struct {
-	unsigned char size;
-	unsigned char buffer[256];
-	mipi_dsi_cmd_id_t cmd_id;
-	mipi_dsi_cmd_flag_t flags;
-} lcd_table_setting_t;
+void mipi_dsi_seq0_isr(void);
 
 void mipi_dsi_callback(mipi_dsi_callback_args_t *p_args)
 {
 	const struct device *dev = (struct device *)p_args->p_context;
 	struct mipi_dsi_renesas_ra_data *data = dev->data;
 
-	switch (p_args->event) {
-	case MIPI_DSI_EVENT_SEQUENCE_0: {
-		if (MIPI_DSI_SEQUENCE_STATUS_DESCRIPTORS_FINISHED == p_args->tx_status) {
-			data->message_sent = true;
-		}
-		break;
-	}
-	case MIPI_DSI_EVENT_FATAL: {
-		data->fatal_error = true;
-		break;
-	}
-	default: {
-		break;
-	}
+	if (p_args->event == MIPI_DSI_EVENT_SEQUENCE_0) {
+		atomic_set(&data->status, p_args->tx_status);
+		k_sem_give(&data->in_transmission);
 	}
 }
 
@@ -92,19 +46,29 @@ static int mipi_dsi_renesas_ra_attach(const struct device *dev, uint8_t channel,
 {
 	struct mipi_dsi_renesas_ra_data *data = dev->data;
 	mipi_dsi_cfg_t cfg = data->mipi_dsi_cfg;
-	int ret;
+	fsp_err_t err;
 
 	if (!(mdev->mode_flags & MIPI_DSI_MODE_VIDEO)) {
 		LOG_ERR("DSI host supports video mode only!");
 		return -ENOTSUP;
 	}
+
+	if (channel == 0 && (mdev->mode_flags & MIPI_DSI_MODE_LPM) == 0) {
+		LOG_ERR("This channel support LP mode transfer only");
+		return -ENOTSUP;
+	}
+
 	cfg.virtual_channel_id = channel;
 	cfg.num_lanes = mdev->data_lanes;
+
 	if (mdev->pixfmt == MIPI_DSI_PIXFMT_RGB888) {
 		cfg.data_type = MIPI_DSI_VIDEO_DATA_24RGB_PIXEL_STREAM;
 	} else if (mdev->pixfmt == MIPI_DSI_PIXFMT_RGB565) {
 		cfg.data_type = MIPI_DSI_VIDEO_DATA_16RGB_PIXEL_STREAM;
+	} else {
+		return -ENOTSUP;
 	}
+
 	cfg.horizontal_active_lines = mdev->timings.hactive;
 	cfg.horizontal_front_porch = mdev->timings.hfp;
 	cfg.horizontal_back_porch = mdev->timings.hbp;
@@ -115,68 +79,119 @@ static int mipi_dsi_renesas_ra_attach(const struct device *dev, uint8_t channel,
 	cfg.vertical_back_porch = mdev->timings.vbp;
 	cfg.vertical_sync_lines = mdev->timings.vsync;
 
-	ret = R_MIPI_DSI_Open(&data->mipi_dsi_ctrl, &cfg);
-	if (ret) {
-		LOG_ERR("Open DSI failed (%d)", ret);
+	err = R_MIPI_DSI_Open(&data->mipi_dsi_ctrl, &cfg);
+	if (err != FSP_SUCCESS) {
+		LOG_ERR("Open DSI failed (%d)", err);
 		return -EIO;
 	}
 
-	ret = R_MIPI_DSI_Start(&data->mipi_dsi_ctrl);
-	if (ret) {
-		LOG_ERR("Start DSI host failed! (%d)", ret);
+	err = R_MIPI_DSI_Start(&data->mipi_dsi_ctrl);
+	if (err != FSP_SUCCESS) {
+		LOG_ERR("Start DSI host failed! (%d)", err);
 		return -EIO;
 	}
 
 	return 0;
 }
 
-static ssize_t mipi_dsi_renesas_ra_transfer(const struct device *dev, uint8_t channel,
-					    struct mipi_dsi_msg *msg)
+#define MIPI_DSI_SEQUENCE_STATUS_ERROR                                                             \
+	(MIPI_DSI_SEQUENCE_STATUS_DESCRIPTOR_ABORT | MIPI_DSI_SEQUENCE_STATUS_SIZE_ERROR |         \
+	 MIPI_DSI_SEQUENCE_STATUS_TX_INTERNAL_BUS_ERROR |                                          \
+	 MIPI_DSI_SEQUENCE_STATUS_RX_FATAL_ERROR | MIPI_DSI_SEQUENCE_STATUS_RX_FAIL |              \
+	 MIPI_DSI_SEQUENCE_STATUS_RX_PACKET_DATA_FAIL |                                            \
+	 MIPI_DSI_SEQUENCE_STATUS_RX_CORRECTABLE_ERROR |                                           \
+	 MIPI_DSI_SEQUENCE_STATUS_RX_ACK_AND_ERROR)
+
+static ssize_t mipi_dsi_renesas_ra_dcs_write(const struct device *dev, uint8_t channel,
+					     struct mipi_dsi_msg *msg)
 {
 	struct mipi_dsi_renesas_ra_data *data = dev->data;
-	ssize_t len;
-	int ret;
-	uint8_t combined_tx_buffer[msg->tx_len + 1];
+	uint8_t payload[msg->tx_len + 1];
+	mipi_dsi_cmd_t fsp_msg = {.channel = channel,
+				  .cmd_id = msg->type,
+				  .p_tx_buffer = payload,
+				  .tx_len = msg->tx_len + 1,
+				  .flags = (msg->flags & MIPI_DSI_MSG_USE_LPM) != 0
+						   ? MIPI_DSI_CMD_FLAG_LOW_POWER
+						   : 0};
 
-	combined_tx_buffer[0] = msg->cmd;
-	memcpy(&combined_tx_buffer[1], msg->tx_buf, msg->tx_len);
+	payload[0] = msg->cmd;
+	memcpy(&payload[1], msg->tx_buf, msg->tx_len);
 
-	mipi_dsi_cmd_t fsp_msg = {
-		.channel = channel,
-		.cmd_id = msg->type,
-		.flags = MIPI_DSI_CMD_FLAG_LOW_POWER,
-		.tx_len = msg->tx_len + 1,
-		.p_tx_buffer = combined_tx_buffer,
-	};
-	data->message_sent = false;
-	data->fatal_error = false;
+	atomic_clear(&data->status);
+	k_sem_reset(&data->in_transmission);
 
-	switch (msg->type) {
-	case MIPI_DSI_DCS_READ:
-		LOG_ERR("DCS Read not yet implemented or used");
+	if (R_MIPI_DSI_Command(&data->mipi_dsi_ctrl, &fsp_msg) != FSP_SUCCESS) {
+		LOG_ERR("DSI write fail");
+		return -EIO;
+	}
+
+	k_sem_take(&data->in_transmission, K_FOREVER);
+
+	if ((data->status & MIPI_DSI_SEQUENCE_STATUS_ERROR) != MIPI_DSI_SEQUENCE_STATUS_NONE) {
+		return -EIO;
+	}
+
+	return (ssize_t)msg->tx_len;
+}
+
+static ssize_t mipi_dsi_renesas_ra_generic_write(const struct device *dev, uint8_t channel,
+						 struct mipi_dsi_msg *msg)
+{
+	struct mipi_dsi_renesas_ra_data *data = dev->data;
+	mipi_dsi_cmd_t fsp_msg = {.channel = channel,
+				  .cmd_id = msg->type,
+				  .p_tx_buffer = msg->tx_buf,
+				  .tx_len = msg->tx_len,
+				  .flags = (msg->flags & MIPI_DSI_MSG_USE_LPM) != 0
+						   ? MIPI_DSI_CMD_FLAG_LOW_POWER
+						   : 0};
+
+	atomic_clear(&data->status);
+	k_sem_reset(&data->in_transmission);
+
+	if (R_MIPI_DSI_Command(&data->mipi_dsi_ctrl, &fsp_msg) != FSP_SUCCESS) {
+		LOG_ERR("DSI write fail");
+		return -EIO;
+	}
+
+	k_sem_take(&data->in_transmission, K_FOREVER);
+
+	if ((data->status & MIPI_DSI_SEQUENCE_STATUS_ERROR) != MIPI_DSI_SEQUENCE_STATUS_NONE) {
+		return -EIO;
+	}
+
+	return (ssize_t)msg->tx_len;
+}
+
+static ssize_t mipi_dsi_renesas_ra_transfer(const struct device *dev, uint8_t channel,
+					    struct mipi_dsi_msg *msg)
+{
+	if (channel == 0 && (msg->flags & MIPI_DSI_MSG_USE_LPM) == 0) {
+		LOG_ERR("This channel support LP mode transfer only");
 		return -ENOTSUP;
+	}
+
+	switch (msg->type) {
 	case MIPI_DSI_DCS_SHORT_WRITE:
+		__fallthrough;
 	case MIPI_DSI_DCS_SHORT_WRITE_PARAM:
+		__fallthrough;
 	case MIPI_DSI_DCS_LONG_WRITE:
-		ret = R_MIPI_DSI_Command(&data->mipi_dsi_ctrl, &fsp_msg);
-		if (ret) {
-			LOG_ERR("DSI write fail: err: (%d)", ret);
-			return -EIO;
-		}
-		while (!(data->message_sent)) {
-			if (data->fatal_error) {
-				LOG_ERR("fatal error");
-				return -EIO;
-			}
-		}
-		len = msg->tx_len;
-		break;
+		return mipi_dsi_renesas_ra_dcs_write(dev, channel, msg);
+	case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM:
+		__fallthrough;
+	case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM:
+		__fallthrough;
+	case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM:
+		__fallthrough;
+	case MIPI_DSI_GENERIC_LONG_WRITE:
+		return mipi_dsi_renesas_ra_generic_write(dev, channel, msg);
 	default:
-		LOG_ERR("Unsupported message type (%d)", msg->type);
 		return -ENOTSUP;
 	}
 
-	return len;
+	return 0;
 }
 
 static DEVICE_API(mipi_dsi, mipi_dsi_api) = {
@@ -197,60 +212,90 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev)
 
 	ret = clock_control_on(config->clock_dev,
 			       (clock_control_subsys_t)&config->clock_dsi_subsys);
-	if (ret) {
+	if (ret != 0) {
 		LOG_ERR("Enable DSI peripheral clock failed! (%d)", ret);
 		return ret;
 	}
 
+	k_sem_init(&data->in_transmission, 0, 1);
+
 	config->irq_configure();
-	data->mipi_dsi_cfg.p_context = dev;
 
 	return 0;
 }
 
-#define IRQ_CONFIGURE_FUNC(id)                                                                     \
+#define RENESAS_RA_MIPI_PHYS_SETTING_DEFINE(n)                                                     \
+	static const mipi_phy_timing_t mipi_phy_##n##_timing = {                                   \
+		.t_init = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_init), 0, 0x7FFF),        \
+		.t_clk_prep = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_clk_prep), 0, 0xFF),  \
+		.t_hs_prep = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_hs_prep), 0, 0xFF),    \
+		.t_lp_exit = CLAMP(DT_PROP(DT_INST_CHILD(n, phys_timing), t_lp_exit), 0, 0xFF),    \
+		.dphytim4_b =                                                                      \
+			{                                                                          \
+				.t_clk_zero = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing),        \
+							     dphytim4, 0),                         \
+				.t_clk_pre = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing),         \
+							    dphytim4, 1),                          \
+				.t_clk_post = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing),        \
+							     dphytim4, 2),                         \
+				.t_clk_trail = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing),       \
+							      dphytim4, 3),                        \
+			},                                                                         \
+		.dphytim5_b =                                                                      \
+			{                                                                          \
+				.t_hs_zero = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing),         \
+							    dphytim5, 0),                          \
+				.t_hs_trail = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing),        \
+							     dphytim5, 1),                         \
+				.t_hs_exit = DT_PROP_BY_IDX(DT_INST_CHILD(n, phys_timing),         \
+							    dphytim5, 2),                          \
+			},                                                                         \
+	};                                                                                         \
+                                                                                                   \
+	static const mipi_phy_cfg_t mipi_phy_##n##_cfg = {                                         \
+		.pll_settings =                                                                    \
+			{                                                                          \
+				.div = DT_INST_PROP(n, pll_div) - 1,                               \
+				.mul_frac = DT_INST_ENUM_IDX(n, pll_mul_frac),                     \
+				.mul_int = CLAMP(DT_INST_PROP(n, pll_mul_int), 20, 180) - 1,       \
+			},                                                                         \
+		.lp_divisor = CLAMP(DT_INST_PROP(n, lp_divisor), 1, 32) - 1,                       \
+		.p_timing = &mipi_phy_##n##_timing,                                                \
+	};                                                                                         \
+                                                                                                   \
+	mipi_phy_ctrl_t mipi_phy_##n##_ctrl;                                                       \
+                                                                                                   \
+	static const mipi_phy_instance_t mipi_phy##n = {                                           \
+		.p_ctrl = &mipi_phy_##n##_ctrl,                                                    \
+		.p_cfg = &mipi_phy_##n##_cfg,                                                      \
+		.p_api = &g_mipi_phy,                                                              \
+	};
+
+#define RENESAS_RA_MIPI_DSI_PHYS_GET(n) &mipi_phy##n
+
+#define RENESAS_RA_MIPI_DSI_TIMING_DEFINE(n)                                                       \
+	static const mipi_dsi_timing_t mipi_dsi_##n##_timing = {                                   \
+		.clock_stop_time = DT_INST_PROP_BY_IDX(n, timing, 0),                              \
+		.clock_beforehand_time = DT_INST_PROP_BY_IDX(n, timing, 1),                        \
+		.clock_keep_time = DT_INST_PROP_BY_IDX(n, timing, 2),                              \
+		.go_lp_and_back = DT_INST_PROP_BY_IDX(n, timing, 3),                               \
+	};
+
+#define RENESAS_RA_MIPI_DSI_TIMING_GET(n) &mipi_dsi_##n##_timing
+
+#define RENESAS_MIPI_DSI_DEVICE(id)                                                                \
 	static void mipi_dsi_ra_configure_func_##id(void)                                          \
 	{                                                                                          \
-		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(id, sq0, irq)] = ELC_EVENT_MIPIDSI_SEQ0;          \
+		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(id, sq0, irq)] =                                  \
+			BSP_PRV_IELS_ENUM(EVENT_MIPIDSI_SEQ0);                                     \
 		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(id, sq0, irq),                                     \
-			    DT_INST_IRQ_BY_NAME(id, sq0, priority), mipi_dsi_seq0,                 \
-			    DEVICE_DT_INST_GET(id), 0);                                            \
+			    DT_INST_IRQ_BY_NAME(id, sq0, priority), mipi_dsi_seq0_isr, NULL, 0);   \
 		irq_enable(DT_INST_IRQ_BY_NAME(id, sq0, irq));                                     \
-		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(id, ferr, irq)] = ELC_EVENT_MIPIDSI_FERR;         \
-		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(id, ferr, irq),                                    \
-			    DT_INST_IRQ_BY_NAME(id, ferr, priority), mipi_dsi_ferr,                \
-			    DEVICE_DT_INST_GET(id), 0);                                            \
-		irq_enable(DT_INST_IRQ_BY_NAME(id, ferr, irq));                                    \
-	}
-
-#define IRQ_CONFIGURE_DEFINE(id) .irq_configure = mipi_dsi_ra_configure_func_##id
-
-#define RENESAS_MIPI_DSI_DEVICE(id)                                                                \
-	IRQ_CONFIGURE_FUNC(id)                                                                     \
-	mipi_phy_ctrl_t mipi_phy_##id##_ctrl;                                                      \
-	static const mipi_phy_timing_t mipi_phy_##id##_timing = {                                  \
-		.t_init = 0x3FFFF & (uint32_t)MIPI_PHY_TINIT,                                      \
-		.t_clk_prep = (uint8_t)MIPI_PHY_TCLKPREP,                                          \
-		.t_hs_prep = (uint8_t)MIPI_PHY_THSPREP,                                            \
-		.dphytim4_b.t_clk_trail = (uint32_t)MIPI_PHY_TCLKTRAIL,                            \
-		.dphytim4_b.t_clk_post = (uint32_t)MIPI_PHY_TCLKPOST,                              \
-		.dphytim4_b.t_clk_pre = (uint32_t)MIPI_PHY_TCLKPRE,                                \
-		.dphytim4_b.t_clk_zero = (uint32_t)MIPI_PHY_TCLKZERO,                              \
-		.dphytim5_b.t_hs_exit = (uint32_t)MIPI_PHY_THSEXIT,                                \
-		.dphytim5_b.t_hs_trail = (uint32_t)MIPI_PHY_THSTRAIL,                              \
-		.dphytim5_b.t_hs_zero = (uint32_t)MIPI_PHY_THSZERO,                                \
-		.t_lp_exit = (uint32_t)MIPI_PHY_TLPEXIT,                                           \
-	};                                                                                         \
-	static const mipi_phy_cfg_t mipi_phy_##id##_cfg = {                                        \
-		.pll_settings = {.div = 0, .mul_int = PLL_MUL_SETTING, .mul_frac = 0},             \
-		.lp_divisor = LP_DIVISOR,                                                          \
-		.p_timing = &mipi_phy_##id##_timing,                                               \
-	};                                                                                         \
-	static const mipi_phy_instance_t mipi_phy##id = {                                          \
-		.p_ctrl = &mipi_phy_##id##_ctrl,                                                   \
-		.p_cfg = &mipi_phy_##id##_cfg,                                                     \
-		.p_api = &g_mipi_phy,                                                              \
-	};                                                                                         \
+	}                                                                                          \
+                                                                                                   \
+	RENESAS_RA_MIPI_DSI_TIMING_DEFINE(id)                                                      \
+	RENESAS_RA_MIPI_PHYS_SETTING_DEFINE(id)                                                    \
+                                                                                                   \
 	static const mipi_dsi_extended_cfg_t mipi_dsi_##id##_extended_cfg = {                      \
 		.dsi_seq0.ipl = DT_INST_IRQ_BY_NAME(id, sq0, priority),                            \
 		.dsi_seq0.irq = DT_INST_IRQ_BY_NAME(id, sq0, irq),                                 \
@@ -273,58 +318,54 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev)
 			    R_DSILINK_RXIER_CRCERR_Msk | R_DSILINK_RXIER_IBERR_Msk |               \
 			    R_DSILINK_RXIER_RXOVFERR_Msk | R_DSILINK_RXIER_PRTOERR_Msk |           \
 			    R_DSILINK_RXIER_NORESERR_Msk | R_DSILINK_RXIER_RSIZEERR_Msk |          \
-			    R_DSILINK_RXIER_ECCERRS_Msk | R_DSILINK_RXIER_RXAKE_Msk | 0x0,         \
+			    R_DSILINK_RXIER_ECCERRS_Msk | R_DSILINK_RXIER_RXAKE_Msk,               \
 		.dsi_ferrie = R_DSILINK_FERRIER_HTXTO_Msk | R_DSILINK_FERRIER_LRXHTO_Msk |         \
 			      R_DSILINK_FERRIER_TATO_Msk | R_DSILINK_FERRIER_ESCENT_Msk |          \
 			      R_DSILINK_FERRIER_SYNCESC_Msk | R_DSILINK_FERRIER_CTRL_Msk |         \
-			      R_DSILINK_FERRIER_CLP0_Msk | R_DSILINK_FERRIER_CLP1_Msk | 0x0,       \
-		.dsi_plie = R_DSILINK_PLIER_DLULPENT_Msk | R_DSILINK_PLIER_DLULPEXT_Msk | 0x0,     \
-		.dsi_vmie = R_DSILINK_VMIER_VBUFUDF_Msk | R_DSILINK_VMIER_VBUFOVF_Msk | 0x0,       \
+			      R_DSILINK_FERRIER_CLP0_Msk | R_DSILINK_FERRIER_CLP1_Msk,             \
+		.dsi_plie = R_DSILINK_PLIER_DLULPENT_Msk | R_DSILINK_PLIER_DLULPEXT_Msk,           \
+		.dsi_vmie = R_DSILINK_VMIER_VBUFUDF_Msk | R_DSILINK_VMIER_VBUFOVF_Msk,             \
 		.dsi_sqch0ie = R_DSILINK_SQCH0IER_AACTFIN_Msk | R_DSILINK_SQCH0IER_ADESFIN_Msk |   \
 			       R_DSILINK_SQCH0IER_TXIBERR_Msk | R_DSILINK_SQCH0IER_RXFERR_Msk |    \
 			       R_DSILINK_SQCH0IER_RXFAIL_Msk | R_DSILINK_SQCH0IER_RXPFAIL_Msk |    \
-			       R_DSILINK_SQCH0IER_RXCORERR_Msk | R_DSILINK_SQCH0IER_RXAKE_Msk |    \
-			       0x0,                                                                \
+			       R_DSILINK_SQCH0IER_RXCORERR_Msk | R_DSILINK_SQCH0IER_RXAKE_Msk,     \
 		.dsi_sqch1ie = R_DSILINK_SQCH1IER_AACTFIN_Msk | R_DSILINK_SQCH1IER_ADESFIN_Msk |   \
 			       R_DSILINK_SQCH1IER_SIZEERR_Msk | R_DSILINK_SQCH1IER_TXIBERR_Msk |   \
 			       R_DSILINK_SQCH1IER_RXFERR_Msk | R_DSILINK_SQCH1IER_RXFAIL_Msk |     \
 			       R_DSILINK_SQCH1IER_RXPFAIL_Msk | R_DSILINK_SQCH1IER_RXCORERR_Msk |  \
-			       R_DSILINK_SQCH1IER_RXAKE_Msk | 0x0,                                 \
-	};                                                                                         \
-	static const mipi_dsi_timing_t mipi_dsi_##id##_timing = {                                  \
-		.clock_stop_time = MIPI_PHY_CLKSTPT,                                               \
-		.clock_beforehand_time = MIPI_PHY_CLKBFHT,                                         \
-		.clock_keep_time = MIPI_PHY_CLKKPT,                                                \
-		.go_lp_and_back = MIPI_PHY_GOLPBKT,                                                \
+			       R_DSILINK_SQCH1IER_RXAKE_Msk,                                       \
 	};                                                                                         \
+                                                                                                   \
 	static const struct mipi_dsi_renesas_ra_config ra_config_##id = {                          \
 		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(id)),                               \
-		IRQ_CONFIGURE_DEFINE(id),                                                          \
-		.clock_dsi_subsys = {.mstp = (uint32_t)DT_INST_CLOCKS_CELL_BY_IDX(id, 0, mstp),    \
-				     .stop_bit = DT_INST_CLOCKS_CELL_BY_IDX(id, 0, stop_bit)}};    \
+		.clock_dsi_subsys =                                                                \
+			{                                                                          \
+				.mstp = DT_INST_CLOCKS_CELL(id, mstp),                             \
+				.stop_bit = DT_INST_CLOCKS_CELL(id, stop_bit),                     \
+			},                                                                         \
+		.irq_configure = mipi_dsi_ra_configure_func_##id,                                  \
+	};                                                                                         \
+                                                                                                   \
 	static struct mipi_dsi_renesas_ra_data ra_data_##id = {                                    \
 		.mipi_dsi_cfg =                                                                    \
 			{                                                                          \
-				.p_mipi_phy_instance = &mipi_phy##id,                              \
-				.p_timing = &mipi_dsi_##id##_timing,                               \
+				.p_mipi_phy_instance = RENESAS_RA_MIPI_DSI_PHYS_GET(id),           \
+				.p_timing = RENESAS_RA_MIPI_DSI_TIMING_GET(id),                    \
 				.sync_pulse = (0),                                                 \
-				.data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24,                      \
 				.vertical_sync_polarity = 1,                                       \
 				.horizontal_sync_polarity = 1,                                     \
-				.video_mode_delay = VIDEO_MODE_DELAY,                              \
-				.hsa_no_lp = ((0x0) & R_DSILINK_VMSET0R_HSANOLP_Msk),              \
-				.hbp_no_lp = ((0x0) & R_DSILINK_VMSET0R_HBPNOLP_Msk),              \
-				.hfp_no_lp = ((0x0) & R_DSILINK_VMSET0R_HFPNOLP_Msk),              \
-				.num_lanes =                                                       \
-					DT_PROP_BY_IDX(DT_NODELABEL(ili9806e), data_lanes, 0),     \
-				.ulps_wakeup_period = ULPS_WAKEUP_PERIOD,                          \
+				.video_mode_delay = DT_INST_PROP(id, video_mode_delay),            \
+				.hsa_no_lp = R_DSILINK_VMSET0R_HSANOLP_Msk,                        \
+				.hbp_no_lp = R_DSILINK_VMSET0R_HBPNOLP_Msk,                        \
+				.hfp_no_lp = R_DSILINK_VMSET0R_HFPNOLP_Msk,                        \
+				.ulps_wakeup_period = DT_INST_PROP(id, ulps_wakeup_period),        \
 				.continuous_clock = (1),                                           \
 				.hs_tx_timeout = 0,                                                \
 				.lp_rx_timeout = 0,                                                \
 				.turnaround_timeout = 0,                                           \
 				.bta_timeout = 0,                                                  \
-				.lprw_timeout = (0 << R_DSILINK_PRESPTOLPSETR_LPRTO_Pos) | 0,      \
-				.hsrw_timeout = (0 << R_DSILINK_PRESPTOHSSETR_HSRTO_Pos) | 0,      \
+				.lprw_timeout = 0,                                                 \
+				.hsrw_timeout = 0,                                                 \
 				.max_return_packet_size = 1,                                       \
 				.ecc_enable = (1),                                                 \
 				.crc_check_mask = (mipi_dsi_vc_t)(0x0),                            \
@@ -333,9 +374,10 @@ static int mipi_dsi_renesas_ra_init(const struct device *dev)
 				.eotp_enable = (1),                                                \
 				.p_extend = &mipi_dsi_##id##_extended_cfg,                         \
 				.p_callback = mipi_dsi_callback,                                   \
-				.p_context = NULL,                                                 \
+				.p_context = DEVICE_DT_INST_GET(id),                               \
 			},                                                                         \
 	};                                                                                         \
+                                                                                                   \
 	DEVICE_DT_INST_DEFINE(id, &mipi_dsi_renesas_ra_init, NULL, &ra_data_##id, &ra_config_##id, \
 			      POST_KERNEL, CONFIG_MIPI_DSI_INIT_PRIORITY, &mipi_dsi_api);
 
diff --git a/drivers/misc/devmux/devmux.c b/drivers/misc/devmux/devmux.c
index d8c1a9b90c7..f4e64fdb385 100644
--- a/drivers/misc/devmux/devmux.c
+++ b/drivers/misc/devmux/devmux.c
@@ -129,7 +129,7 @@ int z_vrfy_devmux_select_set(struct device *dev, size_t index)
 #include <zephyr/syscalls/devmux_select_set_mrsh.c>
 #endif
 
-static int devmux_init(struct device *const dev)
+static int devmux_init(const struct device *dev)
 {
 	size_t inst = devmux_inst_get(dev);
 	struct devmux_data *const data = dev->data;
@@ -143,16 +143,13 @@ static int devmux_init(struct device *const dev)
 		return -ENODEV;
 	}
 
-	*dev = *config->devs[sel];
+	*(struct device *)dev = *config->devs[sel];
 
 	return 0;
 }
 
-#define DEVMUX_PHANDLE_TO_DEVICE(node_id, prop, idx)                                               \
-	DEVICE_DT_GET(DT_PHANDLE_BY_IDX(node_id, prop, idx))
-
 #define DEVMUX_PHANDLE_DEVICES(_n)                                                                 \
-	DT_INST_FOREACH_PROP_ELEM_SEP(_n, devices, DEVMUX_PHANDLE_TO_DEVICE, (,))
+	DT_INST_FOREACH_PROP_ELEM_SEP(_n, devices, DEVICE_DT_GET_BY_IDX, (,))
 
 #define DEVMUX_SELECTED(_n) DT_INST_PROP(_n, selected)
 
diff --git a/drivers/misc/ft8xx/ft8xx.c b/drivers/misc/ft8xx/ft8xx.c
index 1dcbe581b13..a77eb0016ed 100644
--- a/drivers/misc/ft8xx/ft8xx.c
+++ b/drivers/misc/ft8xx/ft8xx.c
@@ -20,6 +20,7 @@
 #include <zephyr/drivers/misc/ft8xx/ft8xx_dl.h>
 #include <zephyr/drivers/misc/ft8xx/ft8xx_memory.h>
 
+#include "ft8xx_dev_data.h"
 #include "ft8xx_drv.h"
 #include "ft8xx_host_commands.h"
 
@@ -46,38 +47,11 @@ struct ft8xx_config {
 	uint8_t swizzle  :4;
 };
 
-struct ft8xx_data {
-	const struct ft8xx_config *config;
-	ft8xx_int_callback irq_callback;
-};
-
-const static struct ft8xx_config ft8xx_config = {
-	.pclk     = DT_INST_PROP(0, pclk),
-	.pclk_pol = DT_INST_PROP(0, pclk_pol),
-	.cspread  = DT_INST_PROP(0, cspread),
-	.swizzle  = DT_INST_PROP(0, swizzle),
-	.vsize    = DT_INST_PROP(0, vsize),
-	.voffset  = DT_INST_PROP(0, voffset),
-	.vcycle   = DT_INST_PROP(0, vcycle),
-	.vsync0   = DT_INST_PROP(0, vsync0),
-	.vsync1   = DT_INST_PROP(0, vsync1),
-	.hsize    = DT_INST_PROP(0, hsize),
-	.hoffset  = DT_INST_PROP(0, hoffset),
-	.hcycle   = DT_INST_PROP(0, hcycle),
-	.hsync0   = DT_INST_PROP(0, hsync0),
-	.hsync1   = DT_INST_PROP(0, hsync1),
-};
-
-static struct ft8xx_data ft8xx_data = {
-	.config = &ft8xx_config,
-	.irq_callback = NULL,
-};
-
-static void host_command(uint8_t cmd)
+static void host_command(const struct device *dev, uint8_t cmd)
 {
 	int err;
 
-	err = ft8xx_drv_command(cmd);
+	err = ft8xx_drv_command(dev, cmd);
 	__ASSERT(err == 0, "Writing FT8xx command failed");
 }
 
@@ -86,9 +60,9 @@ static void wait(void)
 	k_sleep(K_MSEC(20));
 }
 
-static bool verify_chip(void)
+static bool verify_chip(const struct device *dev)
 {
-	uint32_t id = ft8xx_rd32(FT800_REG_ID);
+	uint32_t id = ft8xx_rd32(dev, FT800_REG_ID);
 
 	return (id & 0xff) == FT8XX_EXPECTED_ID;
 }
@@ -97,131 +71,167 @@ static int ft8xx_init(const struct device *dev)
 {
 	int ret;
 	const struct ft8xx_config *config = dev->config;
+	struct ft8xx_data *data = dev->data;
+
+	data->ft8xx_dev = dev;
 
-	ret = ft8xx_drv_init();
+	ret = ft8xx_drv_init(dev);
 	if (ret < 0) {
 		LOG_ERR("FT8xx driver initialization failed with %d", ret);
 		return ret;
 	}
 
 	/* Reset display controller */
-	host_command(CORERST);
-	host_command(ACTIVE);
+	host_command(dev, CORERST);
+	host_command(dev, ACTIVE);
 	wait();
-	host_command(CLKEXT);
-	host_command(CLK48M);
+	host_command(dev, CLKEXT);
+	host_command(dev, CLK48M);
 	wait();
 
-	host_command(CORERST);
-	host_command(ACTIVE);
+	host_command(dev, CORERST);
+	host_command(dev, ACTIVE);
 	wait();
-	host_command(CLKEXT);
-	host_command(CLK48M);
+	host_command(dev, CLKEXT);
+	host_command(dev, CLK48M);
 	wait();
 
-	if (!verify_chip()) {
+	if (!verify_chip(dev)) {
 		LOG_ERR("FT8xx chip not recognized");
 		return -ENODEV;
 	}
 
 	/* Disable LCD */
-	ft8xx_wr8(FT800_REG_GPIO, 0);
-	ft8xx_wr8(FT800_REG_PCLK, 0);
+	ft8xx_wr8(dev, FT800_REG_GPIO, 0);
+	ft8xx_wr8(dev, FT800_REG_PCLK, 0);
 
 	/* Configure LCD */
-	ft8xx_wr16(FT800_REG_HSIZE, config->hsize);
-	ft8xx_wr16(FT800_REG_HCYCLE, config->hcycle);
-	ft8xx_wr16(FT800_REG_HOFFSET, config->hoffset);
-	ft8xx_wr16(FT800_REG_HSYNC0, config->hsync0);
-	ft8xx_wr16(FT800_REG_HSYNC1, config->hsync1);
-	ft8xx_wr16(FT800_REG_VSIZE, config->vsize);
-	ft8xx_wr16(FT800_REG_VCYCLE, config->vcycle);
-	ft8xx_wr16(FT800_REG_VOFFSET, config->voffset);
-	ft8xx_wr16(FT800_REG_VSYNC0, config->vsync0);
-	ft8xx_wr16(FT800_REG_VSYNC1, config->vsync1);
-	ft8xx_wr8(FT800_REG_SWIZZLE, config->swizzle);
-	ft8xx_wr8(FT800_REG_PCLK_POL, config->pclk_pol);
-	ft8xx_wr8(FT800_REG_CSPREAD, config->cspread);
+	ft8xx_wr16(dev, FT800_REG_HSIZE, config->hsize);
+	ft8xx_wr16(dev, FT800_REG_HCYCLE, config->hcycle);
+	ft8xx_wr16(dev, FT800_REG_HOFFSET, config->hoffset);
+	ft8xx_wr16(dev, FT800_REG_HSYNC0, config->hsync0);
+	ft8xx_wr16(dev, FT800_REG_HSYNC1, config->hsync1);
+	ft8xx_wr16(dev, FT800_REG_VSIZE, config->vsize);
+	ft8xx_wr16(dev, FT800_REG_VCYCLE, config->vcycle);
+	ft8xx_wr16(dev, FT800_REG_VOFFSET, config->voffset);
+	ft8xx_wr16(dev, FT800_REG_VSYNC0, config->vsync0);
+	ft8xx_wr16(dev, FT800_REG_VSYNC1, config->vsync1);
+	ft8xx_wr8(dev, FT800_REG_SWIZZLE, config->swizzle);
+	ft8xx_wr8(dev, FT800_REG_PCLK_POL, config->pclk_pol);
+	ft8xx_wr8(dev, FT800_REG_CSPREAD, config->cspread);
 
 	/* Display initial screen */
 
 	/* Set the initial color */
-	ft8xx_wr32(FT800_RAM_DL + 0, FT8XX_CLEAR_COLOR_RGB(0, 0x80, 0));
+	ft8xx_wr32(dev, FT800_RAM_DL + 0, FT8XX_CLEAR_COLOR_RGB(0, 0x80, 0));
 	/* Clear to the initial color */
-	ft8xx_wr32(FT800_RAM_DL + 4, FT8XX_CLEAR(1, 1, 1));
+	ft8xx_wr32(dev, FT800_RAM_DL + 4, FT8XX_CLEAR(1, 1, 1));
 	/* End the display list */
-	ft8xx_wr32(FT800_RAM_DL + 8, FT8XX_DISPLAY());
-	ft8xx_wr8(FT800_REG_DLSWAP, FT8XX_DLSWAP_FRAME);
+	ft8xx_wr32(dev, FT800_RAM_DL + 8, FT8XX_DISPLAY());
+	ft8xx_wr8(dev, FT800_REG_DLSWAP, FT8XX_DLSWAP_FRAME);
 
 	/* Enable LCD */
 
 	/* Enable display bit */
-	ft8xx_wr8(FT800_REG_GPIO_DIR, 0x80);
-	ft8xx_wr8(FT800_REG_GPIO, 0x80);
+	ft8xx_wr8(dev, FT800_REG_GPIO_DIR, 0x80);
+	ft8xx_wr8(dev, FT800_REG_GPIO, 0x80);
 	/* Enable backlight */
-	ft8xx_wr16(FT800_REG_PWM_HZ, 0x00FA);
-	ft8xx_wr8(FT800_REG_PWM_DUTY, 0x10);
+	ft8xx_wr16(dev, FT800_REG_PWM_HZ, 0x00FA);
+	ft8xx_wr8(dev, FT800_REG_PWM_DUTY, 0x10);
 	/* Enable LCD signals */
-	ft8xx_wr8(FT800_REG_PCLK, config->pclk);
+	ft8xx_wr8(dev, FT800_REG_PCLK, config->pclk);
 
 	return 0;
 }
 
-DEVICE_DT_INST_DEFINE(0, ft8xx_init, NULL, &ft8xx_data, &ft8xx_config,
-		      POST_KERNEL, CONFIG_FT800_INIT_PRIORITY, NULL);
-
-int ft8xx_get_touch_tag(void)
+int ft8xx_get_touch_tag(const struct device *dev)
 {
 	/* Read FT800_REG_INT_FLAGS to clear IRQ */
-	(void)ft8xx_rd8(FT800_REG_INT_FLAGS);
+	(void)ft8xx_rd8(dev, FT800_REG_INT_FLAGS);
 
-	return (int)ft8xx_rd8(FT800_REG_TOUCH_TAG);
+	return (int)ft8xx_rd8(dev, FT800_REG_TOUCH_TAG);
 }
 
-void ft8xx_drv_irq_triggered(const struct device *dev, struct gpio_callback *cb,
-			      uint32_t pins)
+void ft8xx_drv_irq_triggered(const struct device *gpio_port, struct gpio_callback *cb,
+			     uint32_t pins)
 {
-	if (ft8xx_data.irq_callback != NULL) {
-		ft8xx_data.irq_callback();
+	struct ft8xx_data *ft8xx_data = CONTAINER_OF(cb, struct ft8xx_data, irq_cb_data);
+	const struct device *ft8xx_dev = ft8xx_data->ft8xx_dev;
+
+	if (ft8xx_data->irq_callback != NULL) {
+		ft8xx_data->irq_callback(ft8xx_dev, ft8xx_data->irq_callback_ud);
 	}
 }
 
-void ft8xx_register_int(ft8xx_int_callback callback)
+void ft8xx_register_int(const struct device *dev, ft8xx_int_callback callback, void *user_data)
 {
-	if (ft8xx_data.irq_callback != NULL) {
+	struct ft8xx_data *ft8xx_data = dev->data;
+
+	if (ft8xx_data->irq_callback != NULL) {
 		return;
 	}
 
-	ft8xx_data.irq_callback = callback;
-	ft8xx_wr8(FT800_REG_INT_MASK, 0x04);
-	ft8xx_wr8(FT800_REG_INT_EN, 0x01);
+	ft8xx_data->irq_callback = callback;
+	ft8xx_data->irq_callback_ud = user_data;
+	ft8xx_wr8(dev, FT800_REG_INT_MASK, 0x04);
+	ft8xx_wr8(dev, FT800_REG_INT_EN, 0x01);
 }
 
-void ft8xx_calibrate(struct ft8xx_touch_transform *data)
+void ft8xx_calibrate(const struct device *dev, struct ft8xx_touch_transform *data)
 {
 	uint32_t result = 0;
 
 	do {
-		ft8xx_copro_cmd_dlstart();
-		ft8xx_copro_cmd(FT8XX_CLEAR_COLOR_RGB(0x00, 0x00, 0x00));
-		ft8xx_copro_cmd(FT8XX_CLEAR(1, 1, 1));
-		ft8xx_copro_cmd_calibrate(&result);
+		ft8xx_copro_cmd_dlstart(dev);
+		ft8xx_copro_cmd(dev, FT8XX_CLEAR_COLOR_RGB(0x00, 0x00, 0x00));
+		ft8xx_copro_cmd(dev, FT8XX_CLEAR(1, 1, 1));
+		ft8xx_copro_cmd_calibrate(dev, &result);
 	} while (result == 0);
 
-	data->a = ft8xx_rd32(FT800_REG_TOUCH_TRANSFORM_A);
-	data->b = ft8xx_rd32(FT800_REG_TOUCH_TRANSFORM_B);
-	data->c = ft8xx_rd32(FT800_REG_TOUCH_TRANSFORM_C);
-	data->d = ft8xx_rd32(FT800_REG_TOUCH_TRANSFORM_D);
-	data->e = ft8xx_rd32(FT800_REG_TOUCH_TRANSFORM_E);
-	data->f = ft8xx_rd32(FT800_REG_TOUCH_TRANSFORM_F);
+	data->a = ft8xx_rd32(dev, FT800_REG_TOUCH_TRANSFORM_A);
+	data->b = ft8xx_rd32(dev, FT800_REG_TOUCH_TRANSFORM_B);
+	data->c = ft8xx_rd32(dev, FT800_REG_TOUCH_TRANSFORM_C);
+	data->d = ft8xx_rd32(dev, FT800_REG_TOUCH_TRANSFORM_D);
+	data->e = ft8xx_rd32(dev, FT800_REG_TOUCH_TRANSFORM_E);
+	data->f = ft8xx_rd32(dev, FT800_REG_TOUCH_TRANSFORM_F);
 }
 
-void ft8xx_touch_transform_set(const struct ft8xx_touch_transform *data)
+void ft8xx_touch_transform_set(const struct device *dev, const struct ft8xx_touch_transform *data)
 {
-	ft8xx_wr32(FT800_REG_TOUCH_TRANSFORM_A, data->a);
-	ft8xx_wr32(FT800_REG_TOUCH_TRANSFORM_B, data->b);
-	ft8xx_wr32(FT800_REG_TOUCH_TRANSFORM_C, data->c);
-	ft8xx_wr32(FT800_REG_TOUCH_TRANSFORM_D, data->d);
-	ft8xx_wr32(FT800_REG_TOUCH_TRANSFORM_E, data->e);
-	ft8xx_wr32(FT800_REG_TOUCH_TRANSFORM_F, data->f);
+	ft8xx_wr32(dev, FT800_REG_TOUCH_TRANSFORM_A, data->a);
+	ft8xx_wr32(dev, FT800_REG_TOUCH_TRANSFORM_B, data->b);
+	ft8xx_wr32(dev, FT800_REG_TOUCH_TRANSFORM_C, data->c);
+	ft8xx_wr32(dev, FT800_REG_TOUCH_TRANSFORM_D, data->d);
+	ft8xx_wr32(dev, FT800_REG_TOUCH_TRANSFORM_E, data->e);
+	ft8xx_wr32(dev, FT800_REG_TOUCH_TRANSFORM_F, data->f);
 }
+
+#define FT8XX_DEVICE(idx)                                                                          \
+const static struct ft8xx_config ft8xx_##idx##_config = {                                          \
+	.pclk     = DT_INST_PROP(idx, pclk),                                                       \
+	.pclk_pol = DT_INST_PROP(idx, pclk_pol),                                                   \
+	.cspread  = DT_INST_PROP(idx, cspread),                                                    \
+	.swizzle  = DT_INST_PROP(idx, swizzle),                                                    \
+	.vsize    = DT_INST_PROP(idx, vsize),                                                      \
+	.voffset  = DT_INST_PROP(idx, voffset),                                                    \
+	.vcycle   = DT_INST_PROP(idx, vcycle),                                                     \
+	.vsync0   = DT_INST_PROP(idx, vsync0),                                                     \
+	.vsync1   = DT_INST_PROP(idx, vsync1),                                                     \
+	.hsize    = DT_INST_PROP(idx, hsize),                                                      \
+	.hoffset  = DT_INST_PROP(idx, hoffset),                                                    \
+	.hcycle   = DT_INST_PROP(idx, hcycle),                                                     \
+	.hsync0   = DT_INST_PROP(idx, hsync0),                                                     \
+	.hsync1   = DT_INST_PROP(idx, hsync1),                                                     \
+};                                                                                                 \
+static struct ft8xx_data ft8xx_##idx##_data = {                                                    \
+	.ft8xx_dev = NULL,                                                                         \
+	.irq_callback = NULL,                                                                      \
+	.irq_callback_ud = NULL,                                                                   \
+												   \
+	.spi = SPI_DT_SPEC_INST_GET(idx, SPI_WORD_SET(8) | SPI_OP_MODE_MASTER, 0),                 \
+	.irq_gpio = GPIO_DT_SPEC_INST_GET(idx, irq_gpios),                                         \
+};                                                                                                 \
+DEVICE_DT_INST_DEFINE(idx, ft8xx_init, NULL, &ft8xx_##idx##_data, &ft8xx_##idx##_config,           \
+		      POST_KERNEL, CONFIG_FT800_INIT_PRIORITY, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(FT8XX_DEVICE)
diff --git a/drivers/misc/ft8xx/ft8xx_common.c b/drivers/misc/ft8xx/ft8xx_common.c
index ebf2d11cd99..f35fbd72fe3 100644
--- a/drivers/misc/ft8xx/ft8xx_common.c
+++ b/drivers/misc/ft8xx/ft8xx_common.c
@@ -9,62 +9,62 @@
 #include <zephyr/sys/byteorder.h>
 #include "ft8xx_drv.h"
 
-void ft8xx_wr8(uint32_t address, uint8_t data)
+void ft8xx_wr8(const struct device *dev, uint32_t address, uint8_t data)
 {
 	int err;
 
-	err = ft8xx_drv_write(address, &data, sizeof(data));
+	err = ft8xx_drv_write(dev, address, &data, sizeof(data));
 	__ASSERT(err == 0, "Writing FT8xx data at 0x%x failed", address);
 }
 
-void ft8xx_wr16(uint32_t address, uint16_t data)
+void ft8xx_wr16(const struct device *dev, uint32_t address, uint16_t data)
 {
 	int err;
 	uint8_t buffer[2];
 
 	*(uint16_t *)buffer = sys_cpu_to_le16(data);
-	err = ft8xx_drv_write(address, buffer, sizeof(buffer));
+	err = ft8xx_drv_write(dev, address, buffer, sizeof(buffer));
 	__ASSERT(err == 0, "Writing FT8xx data at 0x%x failed", address);
 }
 
-void ft8xx_wr32(uint32_t address, uint32_t data)
+void ft8xx_wr32(const struct device *dev, uint32_t address, uint32_t data)
 {
 	int err;
 	uint8_t buffer[4];
 
 	*(uint32_t *)buffer = sys_cpu_to_le32(data);
-	err = ft8xx_drv_write(address, buffer, sizeof(buffer));
+	err = ft8xx_drv_write(dev, address, buffer, sizeof(buffer));
 	__ASSERT(err == 0, "Writing FT8xx data at 0x%x failed", address);
 }
 
-uint8_t ft8xx_rd8(uint32_t address)
+uint8_t ft8xx_rd8(const struct device *dev, uint32_t address)
 {
 	int err;
 	uint8_t data = 0;
 
-	err = ft8xx_drv_read(address, &data, sizeof(data));
+	err = ft8xx_drv_read(dev, address, &data, sizeof(data));
 	__ASSERT(err == 0, "Reading FT8xx data from 0x%x failed", address);
 
 	return data;
 }
 
-uint16_t ft8xx_rd16(uint32_t address)
+uint16_t ft8xx_rd16(const struct device *dev, uint32_t address)
 {
 	int err;
 	uint8_t buffer[2] = {0};
 
-	err = ft8xx_drv_read(address, buffer, sizeof(buffer));
+	err = ft8xx_drv_read(dev, address, buffer, sizeof(buffer));
 	__ASSERT(err == 0, "Reading FT8xx data from 0x%x failed", address);
 
 	return sys_le16_to_cpu(*(const uint16_t *)buffer);
 }
 
-uint32_t ft8xx_rd32(uint32_t address)
+uint32_t ft8xx_rd32(const struct device *dev, uint32_t address)
 {
 	int err;
 	uint8_t buffer[4] = {0};
 
-	err = ft8xx_drv_read(address, buffer, sizeof(buffer));
+	err = ft8xx_drv_read(dev, address, buffer, sizeof(buffer));
 	__ASSERT(err == 0, "Reading FT8xx data from 0x%x failed", address);
 
 	return sys_le32_to_cpu(*(const uint32_t *)buffer);
diff --git a/drivers/misc/ft8xx/ft8xx_copro.c b/drivers/misc/ft8xx/ft8xx_copro.c
index d1f1f82c663..9e8e969228f 100644
--- a/drivers/misc/ft8xx/ft8xx_copro.c
+++ b/drivers/misc/ft8xx/ft8xx_copro.c
@@ -11,6 +11,7 @@
 
 #include <zephyr/drivers/misc/ft8xx/ft8xx_common.h>
 #include <zephyr/drivers/misc/ft8xx/ft8xx_memory.h>
+#include "ft8xx_dev_data.h"
 #include "ft8xx_drv.h"
 
 #define FT800_RAM_CMD_SIZE 4096UL
@@ -23,63 +24,73 @@ enum {
 	CMD_CALIBRATE = 0xffffff15,
 } ft8xx_cmd;
 
-static uint16_t reg_cmd_read;
-static uint16_t reg_cmd_write;
-
-static uint16_t ram_cmd_fullness(void)
+static uint16_t ram_cmd_fullness(const struct device *dev)
 {
-	return (reg_cmd_write - reg_cmd_read) % 4096UL;
+	const struct ft8xx_data *data = dev->data;
+
+	return (data->reg_cmd_write - data->reg_cmd_read) % 4096UL;
 }
 
-static uint16_t ram_cmd_freespace(void)
+static uint16_t ram_cmd_freespace(const struct device *dev)
 {
-	return (FT800_RAM_CMD_SIZE - 4UL) - ram_cmd_fullness();
+	return (FT800_RAM_CMD_SIZE - 4UL) - ram_cmd_fullness(dev);
 }
 
-static void refresh_reg_cmd_read(void)
+static void refresh_reg_cmd_read(const struct device *dev)
 {
-	reg_cmd_read = ft8xx_rd32(FT800_REG_CMD_READ);
+	struct ft8xx_data *data = dev->data;
+
+	data->reg_cmd_read = ft8xx_rd32(dev, FT800_REG_CMD_READ);
 }
 
-static void flush_reg_cmd_write(void)
+static void flush_reg_cmd_write(const struct device *dev)
 {
-	ft8xx_wr32(FT800_REG_CMD_WRITE, reg_cmd_write);
+	struct ft8xx_data *data = dev->data;
+
+	ft8xx_wr32(dev, FT800_REG_CMD_WRITE, data->reg_cmd_write);
 }
 
-static void increase_reg_cmd_write(uint16_t value)
+static void increase_reg_cmd_write(const struct device *dev, uint16_t value)
 {
-	reg_cmd_write = (reg_cmd_write + value) % FT800_RAM_CMD_SIZE;
+	struct ft8xx_data *data = dev->data;
+
+	data->reg_cmd_write = (data->reg_cmd_write + value) % FT800_RAM_CMD_SIZE;
 }
 
-void ft8xx_copro_cmd(uint32_t cmd)
+void ft8xx_copro_cmd(const struct device *dev, uint32_t cmd)
 {
-	while (ram_cmd_freespace() < sizeof(cmd)) {
-		refresh_reg_cmd_read();
+	struct ft8xx_data *data = dev->data;
+
+	while (ram_cmd_freespace(dev) < sizeof(cmd)) {
+		refresh_reg_cmd_read(dev);
 	}
 
-	ft8xx_wr32(FT800_RAM_CMD + reg_cmd_write, cmd);
-	increase_reg_cmd_write(sizeof(cmd));
+	ft8xx_wr32(dev, FT800_RAM_CMD + data->reg_cmd_write, cmd);
+	increase_reg_cmd_write(dev, sizeof(cmd));
 
-	flush_reg_cmd_write();
+	flush_reg_cmd_write(dev);
 }
 
-void ft8xx_copro_cmd_dlstart(void)
+void ft8xx_copro_cmd_dlstart(const struct device *dev)
 {
-	ft8xx_copro_cmd(CMD_DLSTART);
+	ft8xx_copro_cmd(dev, CMD_DLSTART);
 }
 
-void ft8xx_copro_cmd_swap(void)
+void ft8xx_copro_cmd_swap(const struct device *dev)
 {
-	ft8xx_copro_cmd(CMD_SWAP);
+	ft8xx_copro_cmd(dev, CMD_SWAP);
 }
 
-void ft8xx_copro_cmd_text(int16_t x,
+void ft8xx_copro_cmd_text(const struct device *dev,
+			   int16_t x,
 			   int16_t y,
 			   int16_t font,
 			   uint16_t options,
-			   const char *s)
+			   const char *string)
 {
-	const uint16_t str_bytes = strlen(s) + 1;
+	struct ft8xx_data *data = dev->data;
+
+	const uint16_t str_bytes = strlen(string) + 1;
 	const uint16_t padding_bytes = (4 - (str_bytes % 4)) % 4;
 	const uint16_t cmd_size = sizeof(CMD_TEXT) +
 				   sizeof(x) +
@@ -89,91 +100,97 @@ void ft8xx_copro_cmd_text(int16_t x,
 				   str_bytes +
 				   padding_bytes;
 
-	while (ram_cmd_freespace() < cmd_size) {
-		refresh_reg_cmd_read();
+	while (ram_cmd_freespace(dev) < cmd_size) {
+		refresh_reg_cmd_read(dev);
 	}
 
-	ft8xx_wr32(FT800_RAM_CMD + reg_cmd_write, CMD_TEXT);
-	increase_reg_cmd_write(sizeof(CMD_TEXT));
+	ft8xx_wr32(dev, FT800_RAM_CMD + data->reg_cmd_write, CMD_TEXT);
+	increase_reg_cmd_write(dev, sizeof(CMD_TEXT));
 
-	ft8xx_wr16(FT800_RAM_CMD + reg_cmd_write, x);
-	increase_reg_cmd_write(sizeof(x));
+	ft8xx_wr16(dev, FT800_RAM_CMD + data->reg_cmd_write, x);
+	increase_reg_cmd_write(dev, sizeof(x));
 
-	ft8xx_wr16(FT800_RAM_CMD + reg_cmd_write, y);
-	increase_reg_cmd_write(sizeof(y));
+	ft8xx_wr16(dev, FT800_RAM_CMD + data->reg_cmd_write, y);
+	increase_reg_cmd_write(dev, sizeof(y));
 
-	ft8xx_wr16(FT800_RAM_CMD + reg_cmd_write, font);
-	increase_reg_cmd_write(sizeof(font));
+	ft8xx_wr16(dev, FT800_RAM_CMD + data->reg_cmd_write, font);
+	increase_reg_cmd_write(dev, sizeof(font));
 
-	ft8xx_wr16(FT800_RAM_CMD + reg_cmd_write, options);
-	increase_reg_cmd_write(sizeof(options));
+	ft8xx_wr16(dev, FT800_RAM_CMD + data->reg_cmd_write, options);
+	increase_reg_cmd_write(dev, sizeof(options));
 
-	(void)ft8xx_drv_write(FT800_RAM_CMD + reg_cmd_write, s, str_bytes);
-	increase_reg_cmd_write(str_bytes + padding_bytes);
+	(void)ft8xx_drv_write(dev, FT800_RAM_CMD + data->reg_cmd_write, (uint8_t *)string,
+			      str_bytes);
+	increase_reg_cmd_write(dev, str_bytes + padding_bytes);
 
-	flush_reg_cmd_write();
+	flush_reg_cmd_write(dev);
 }
 
-void ft8xx_copro_cmd_number(int16_t x,
+void ft8xx_copro_cmd_number(const struct device *dev,
+			     int16_t x,
 			     int16_t y,
 			     int16_t font,
 			     uint16_t options,
-			     int32_t n)
+			     int32_t number)
 {
+	struct ft8xx_data *data = dev->data;
+
 	const uint16_t cmd_size = sizeof(CMD_NUMBER) +
 				   sizeof(x) +
 				   sizeof(y) +
 				   sizeof(font) +
 				   sizeof(options) +
-				   sizeof(n);
+				   sizeof(number);
 
-	while (ram_cmd_freespace() < cmd_size) {
-		refresh_reg_cmd_read();
+	while (ram_cmd_freespace(dev) < cmd_size) {
+		refresh_reg_cmd_read(dev);
 	}
 
-	ft8xx_wr32(FT800_RAM_CMD + reg_cmd_write, CMD_NUMBER);
-	increase_reg_cmd_write(sizeof(CMD_NUMBER));
+	ft8xx_wr32(dev, FT800_RAM_CMD + data->reg_cmd_write, CMD_NUMBER);
+	increase_reg_cmd_write(dev, sizeof(CMD_NUMBER));
 
-	ft8xx_wr16(FT800_RAM_CMD + reg_cmd_write, x);
-	increase_reg_cmd_write(sizeof(x));
+	ft8xx_wr16(dev, FT800_RAM_CMD + data->reg_cmd_write, x);
+	increase_reg_cmd_write(dev, sizeof(x));
 
-	ft8xx_wr16(FT800_RAM_CMD + reg_cmd_write, y);
-	increase_reg_cmd_write(sizeof(y));
+	ft8xx_wr16(dev, FT800_RAM_CMD + data->reg_cmd_write, y);
+	increase_reg_cmd_write(dev, sizeof(y));
 
-	ft8xx_wr16(FT800_RAM_CMD + reg_cmd_write, font);
-	increase_reg_cmd_write(sizeof(font));
+	ft8xx_wr16(dev, FT800_RAM_CMD + data->reg_cmd_write, font);
+	increase_reg_cmd_write(dev, sizeof(font));
 
-	ft8xx_wr16(FT800_RAM_CMD + reg_cmd_write, options);
-	increase_reg_cmd_write(sizeof(options));
+	ft8xx_wr16(dev, FT800_RAM_CMD + data->reg_cmd_write, options);
+	increase_reg_cmd_write(dev, sizeof(options));
 
-	ft8xx_wr32(FT800_RAM_CMD + reg_cmd_write, n);
-	increase_reg_cmd_write(sizeof(n));
+	ft8xx_wr32(dev, FT800_RAM_CMD + data->reg_cmd_write, number);
+	increase_reg_cmd_write(dev, sizeof(number));
 
-	flush_reg_cmd_write();
+	flush_reg_cmd_write(dev);
 }
 
-void ft8xx_copro_cmd_calibrate(uint32_t *result)
+void ft8xx_copro_cmd_calibrate(const struct device *dev, uint32_t *result)
 {
+	struct ft8xx_data *data = dev->data;
+
 	const uint16_t cmd_size = sizeof(CMD_CALIBRATE) + sizeof(uint32_t);
 	uint32_t result_address;
 
-	while (ram_cmd_freespace() < cmd_size) {
-		refresh_reg_cmd_read();
+	while (ram_cmd_freespace(dev) < cmd_size) {
+		refresh_reg_cmd_read(dev);
 	}
 
-	ft8xx_wr32(FT800_RAM_CMD + reg_cmd_write, CMD_CALIBRATE);
-	increase_reg_cmd_write(sizeof(CMD_CALIBRATE));
+	ft8xx_wr32(dev, FT800_RAM_CMD + data->reg_cmd_write, CMD_CALIBRATE);
+	increase_reg_cmd_write(dev, sizeof(CMD_CALIBRATE));
 
-	result_address = FT800_RAM_CMD + reg_cmd_write;
-	ft8xx_wr32(result_address, 1UL);
-	increase_reg_cmd_write(sizeof(uint32_t));
+	result_address = FT800_RAM_CMD + data->reg_cmd_write;
+	ft8xx_wr32(dev, result_address, 1UL);
+	increase_reg_cmd_write(dev, sizeof(uint32_t));
 
-	flush_reg_cmd_write();
+	flush_reg_cmd_write(dev);
 
 	/* Wait until calibration is finished. */
-	while (ram_cmd_fullness() > 0) {
-		refresh_reg_cmd_read();
+	while (ram_cmd_fullness(dev) > 0) {
+		refresh_reg_cmd_read(dev);
 	}
 
-	*result = ft8xx_rd32(result_address);
+	*result = ft8xx_rd32(dev, result_address);
 }
diff --git a/drivers/misc/ft8xx/ft8xx_dev_data.h b/drivers/misc/ft8xx/ft8xx_dev_data.h
new file mode 100644
index 00000000000..e459d37c4d5
--- /dev/null
+++ b/drivers/misc/ft8xx/ft8xx_dev_data.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2024 Hubert Miś
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief FT8XX device driver data structure
+ */
+
+#ifndef ZEPHYR_DRIVERS_MISC_FT8XX_FT8XX_DEV_DATA_H_
+#define ZEPHYR_DRIVERS_MISC_FT8XX_FT8XX_DEV_DATA_H_
+
+#include <stdint.h>
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/drivers/misc/ft8xx/ft8xx.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct ft8xx_data {
+	const struct device *ft8xx_dev; /* Required for GPIO IRQ handling */
+	ft8xx_int_callback irq_callback;
+	void *irq_callback_ud;
+
+	const struct spi_dt_spec spi;
+	const struct gpio_dt_spec irq_gpio;
+	struct gpio_callback irq_cb_data;
+
+	uint16_t reg_cmd_read;
+	uint16_t reg_cmd_write;
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_DRIVERS_MISC_FT8XX_FT8XX_DEV_DATA_H_ */
diff --git a/drivers/misc/ft8xx/ft8xx_drv.c b/drivers/misc/ft8xx/ft8xx_drv.c
index 93b2522937d..f392a79cd13 100644
--- a/drivers/misc/ft8xx/ft8xx_drv.c
+++ b/drivers/misc/ft8xx/ft8xx_drv.c
@@ -6,6 +6,9 @@
 
 #include "ft8xx_drv.h"
 
+#include "ft8xx_dev_data.h"
+
+#include <zephyr/device.h>
 #include <zephyr/kernel.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/drivers/spi.h>
@@ -17,17 +20,7 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
 #define DT_DRV_COMPAT ftdi_ft800
 #define NODE_ID DT_INST(0, DT_DRV_COMPAT)
 
-/* SPI device */
-static const struct spi_dt_spec spi = SPI_DT_SPEC_INST_GET(0,
-					 SPI_WORD_SET(8) | SPI_OP_MODE_MASTER,
-					 0);
-
-/* GPIO int line */
-static const struct gpio_dt_spec irq_gpio = GPIO_DT_SPEC_INST_GET(0, irq_gpios);
-
-static struct gpio_callback irq_cb_data;
-
-__weak void ft8xx_drv_irq_triggered(const struct device *dev,
+__weak void ft8xx_drv_irq_triggered(const struct device *gpio_port,
 				     struct gpio_callback *cb, uint32_t pins)
 {
 	/* Intentionally empty */
@@ -51,43 +44,46 @@ static void insert_addr(uint32_t addr, uint8_t *buff)
 	buff[2] = (addr) & 0xff;
 }
 
-int ft8xx_drv_init(void)
+int ft8xx_drv_init(const struct device *dev)
 {
 	int ret;
+	struct ft8xx_data *data = dev->data;
 
-	if (!spi_is_ready_dt(&spi)) {
-		LOG_ERR("SPI bus %s not ready", spi.bus->name);
+	if (!spi_is_ready_dt(&data->spi)) {
+		LOG_ERR("SPI bus %s not ready", data->spi.bus->name);
 		return -ENODEV;
 	}
 
 	/* TODO: Verify if such entry in DTS is present.
 	 * If not, use polling mode.
 	 */
-	if (!gpio_is_ready_dt(&irq_gpio)) {
-		LOG_ERR("GPIO device %s is not ready", irq_gpio.port->name);
+	if (!gpio_is_ready_dt(&data->irq_gpio)) {
+		LOG_ERR("GPIO device %s is not ready", data->irq_gpio.port->name);
 		return -ENODEV;
 	}
 
-	ret = gpio_pin_configure_dt(&irq_gpio, GPIO_INPUT);
+	ret = gpio_pin_configure_dt(&data->irq_gpio, GPIO_INPUT);
 	if (ret != 0) {
 		return ret;
 	}
 
-	ret = gpio_pin_interrupt_configure_dt(&irq_gpio, GPIO_INT_EDGE_TO_ACTIVE);
+	ret = gpio_pin_interrupt_configure_dt(&data->irq_gpio, GPIO_INT_EDGE_TO_ACTIVE);
 	if (ret != 0) {
 		return ret;
 	}
 
-	gpio_init_callback(&irq_cb_data, ft8xx_drv_irq_triggered, BIT(irq_gpio.pin));
-	gpio_add_callback(irq_gpio.port, &irq_cb_data);
+	gpio_init_callback(&data->irq_cb_data, ft8xx_drv_irq_triggered, BIT(data->irq_gpio.pin));
+	gpio_add_callback(data->irq_gpio.port, &data->irq_cb_data);
 
 	return 0;
 }
 
-int ft8xx_drv_write(uint32_t address, const uint8_t *data, unsigned int length)
+int ft8xx_drv_write(const struct device *dev, uint32_t address, const uint8_t *data,
+		    unsigned int length)
 {
 	int ret;
 	uint8_t addr_buf[ADDR_SIZE];
+	const struct ft8xx_data *dev_data = dev->data;
 
 	insert_addr(address, addr_buf);
 	addr_buf[0] |= WRITE_OP;
@@ -109,7 +105,7 @@ int ft8xx_drv_write(uint32_t address, const uint8_t *data, unsigned int length)
 		.count = 2,
 	};
 
-	ret = spi_write_dt(&spi, &tx_bufs);
+	ret = spi_write_dt(&dev_data->spi, &tx_bufs);
 	if (ret < 0) {
 		LOG_ERR("SPI write error: %d", ret);
 	}
@@ -117,11 +113,12 @@ int ft8xx_drv_write(uint32_t address, const uint8_t *data, unsigned int length)
 	return ret;
 }
 
-int ft8xx_drv_read(uint32_t address, uint8_t *data, unsigned int length)
+int ft8xx_drv_read(const struct device *dev, uint32_t address, uint8_t *data, unsigned int length)
 {
 	int ret;
 	uint8_t dummy_read_buf[ADDR_SIZE + DUMMY_READ_SIZE];
 	uint8_t addr_buf[ADDR_SIZE];
+	const struct ft8xx_data *dev_data = dev->data;
 
 	insert_addr(address, addr_buf);
 	addr_buf[0] |= READ_OP;
@@ -152,7 +149,7 @@ int ft8xx_drv_read(uint32_t address, uint8_t *data, unsigned int length)
 		.count = 2,
 	};
 
-	ret = spi_transceive_dt(&spi, &tx_bufs, &rx_bufs);
+	ret = spi_transceive_dt(&dev_data->spi, &tx_bufs, &rx_bufs);
 	if (ret < 0) {
 		LOG_ERR("SPI transceive error: %d", ret);
 	}
@@ -160,9 +157,10 @@ int ft8xx_drv_read(uint32_t address, uint8_t *data, unsigned int length)
 	return ret;
 }
 
-int ft8xx_drv_command(uint8_t command)
+int ft8xx_drv_command(const struct device *dev, uint8_t command)
 {
 	int ret;
+	const struct ft8xx_data *dev_data = dev->data;
 	/* Most commands include COMMAND_OP bit. ACTIVE power mode command is
 	 * an exception with value 0x00.
 	 */
@@ -178,7 +176,7 @@ int ft8xx_drv_command(uint8_t command)
 		.count = 1,
 	};
 
-	ret = spi_write_dt(&spi, &tx_bufs);
+	ret = spi_write_dt(&dev_data->spi, &tx_bufs);
 	if (ret < 0) {
 		LOG_ERR("SPI command error: %d", ret);
 	}
diff --git a/drivers/misc/ft8xx/ft8xx_drv.h b/drivers/misc/ft8xx/ft8xx_drv.h
index 46632f69642..37461d40f32 100644
--- a/drivers/misc/ft8xx/ft8xx_drv.h
+++ b/drivers/misc/ft8xx/ft8xx_drv.h
@@ -21,10 +21,11 @@
 extern "C" {
 #endif
 
-int ft8xx_drv_init(void);
-int ft8xx_drv_read(uint32_t address, uint8_t *data, unsigned int length);
-int ft8xx_drv_write(uint32_t address, const uint8_t *data, unsigned int length);
-int ft8xx_drv_command(uint8_t command);
+int ft8xx_drv_init(const struct device *dev);
+int ft8xx_drv_read(const struct device *dev, uint32_t address, uint8_t *data, unsigned int length);
+int ft8xx_drv_write(const struct device *dev, uint32_t address, const uint8_t *data,
+		    unsigned int length);
+int ft8xx_drv_command(const struct device *dev, uint8_t command);
 
 extern void ft8xx_drv_irq_triggered(const struct device *dev,
 		struct gpio_callback *cb, uint32_t pins);
diff --git a/drivers/misc/nxp_s32_emios/nxp_s32_emios.c b/drivers/misc/nxp_s32_emios/nxp_s32_emios.c
index d22d94b3015..371dca15389 100644
--- a/drivers/misc/nxp_s32_emios/nxp_s32_emios.c
+++ b/drivers/misc/nxp_s32_emios/nxp_s32_emios.c
@@ -59,15 +59,10 @@ static int nxp_s32_emios_init(const struct device *dev)
 		.enableGlobalTimeBase = true							\
 	};
 
-#define NXP_S32_EMIOS_MASTER_BUS_VERIFY(node_id)						\
-	BUILD_ASSERT(IN_RANGE(DT_PROP(node_id, period),						\
-			      MIN_MASTER_BUS_PERIOD, MAX_MASTER_BUS_PERIOD),			\
-		     "Node "DT_NODE_PATH(node_id)": period is out of range");
-
 #define NXP_S32_EMIOS_MASTER_BUS_CONFIG(node_id)						\
 	{											\
 		.hwChannel = DT_PROP(node_id, channel),						\
-		.defaultPeriod = DT_PROP(node_id, period),					\
+		.defaultPeriod = MAX_MASTER_BUS_PERIOD,						\
 		.masterBusPrescaler = DT_PROP(node_id, prescaler) - 1,				\
 		.allowDebugMode = DT_PROP(node_id, freeze),					\
 		.masterMode = NXP_S32_EMIOS_MASTER_BUS_MODE(DT_STRING_TOKEN(node_id, mode)),	\
@@ -75,8 +70,6 @@ static int nxp_s32_emios_init(const struct device *dev)
 	},
 
 #define NXP_S32_EMIOS_GENERATE_MASTER_BUS_CONFIG(n)						\
-	DT_FOREACH_CHILD_STATUS_OKAY(DT_INST_CHILD(n, master_bus),				\
-				     NXP_S32_EMIOS_MASTER_BUS_VERIFY)				\
 	const Emios_Ip_MasterBusConfigType nxp_s32_emios_##n##_master_bus_config[] = {		\
 		DT_FOREACH_CHILD_STATUS_OKAY(DT_INST_CHILD(n, master_bus),			\
 					     NXP_S32_EMIOS_MASTER_BUS_CONFIG)			\
diff --git a/drivers/misc/pio_rpi_pico/Kconfig b/drivers/misc/pio_rpi_pico/Kconfig
index 718acc6bd1c..5e78a53bb39 100644
--- a/drivers/misc/pio_rpi_pico/Kconfig
+++ b/drivers/misc/pio_rpi_pico/Kconfig
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config PIO_RPI_PICO
-	bool "RaspberryPi Pico PIO"
+	bool "Raspberry Pi Pico PIO"
 	default y
 	depends on DT_HAS_RASPBERRYPI_PICO_PIO_ENABLED
 	depends on RESET
diff --git a/drivers/misc/renesas_ra_external_interrupt/renesas_ra_external_interrupt.c b/drivers/misc/renesas_ra_external_interrupt/renesas_ra_external_interrupt.c
index a8da3c622e3..f669446a3f0 100644
--- a/drivers/misc/renesas_ra_external_interrupt/renesas_ra_external_interrupt.c
+++ b/drivers/misc/renesas_ra_external_interrupt/renesas_ra_external_interrupt.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -152,7 +152,7 @@ static int gpio_ra_interrupt_init(const struct device *dev)
 	static int gpio_ra_irq_init##index(const struct device *dev)                               \
 	{                                                                                          \
 		R_ICU->IELSR[DT_INST_IRQ(index, irq)] =                                            \
-			UTIL_CAT(ELC_EVENT_ICU_IRQ, DT_INST_PROP(index, channel));                 \
+			BSP_PRV_IELS_ENUM(UTIL_CAT(EVENT_ICU_IRQ, DT_INST_PROP(index, channel)));  \
 		IRQ_CONNECT(DT_INST_IRQ(index, irq), DT_INST_IRQ(index, priority), gpio_ra_isr,    \
 			    DEVICE_DT_INST_GET(index), 0);                                         \
 		return gpio_ra_interrupt_init(dev);                                                \
diff --git a/drivers/mm/mm_drv_intel_adsp.h b/drivers/mm/mm_drv_intel_adsp.h
index 861621a510f..133e5a2f9d1 100644
--- a/drivers/mm/mm_drv_intel_adsp.h
+++ b/drivers/mm/mm_drv_intel_adsp.h
@@ -55,7 +55,6 @@
 #define MAX_EBB_BANKS_IN_SEGMENT	32
 #define SRAM_BANK_SIZE				(128 * 1024)
 #define L2_SRAM_BANK_NUM			(L2_SRAM_SIZE / SRAM_BANK_SIZE)
-#define IS_BIT_SET(value, idx)		((value) & (1 << (idx)))
 
 /**
  * Calculate TLB entry based on physical address.
diff --git a/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c b/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c
index b7b046f3b95..e2c369cb904 100644
--- a/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c
+++ b/drivers/mm/mm_drv_intel_adsp_mtl_tlb.c
@@ -462,7 +462,7 @@ int sys_mm_drv_update_page_flags(void *virt, uint32_t flags)
 	tlb_entries[entry_idx] = entry;
 
 #ifdef CONFIG_MMU
-	arch_mem_map(virt, tlb_entry_to_pa(entry), CONFIG_MM_DRV_PAGE_SIZE, flags);
+	arch_mem_map(virt, va, CONFIG_MM_DRV_PAGE_SIZE, flags);
 #endif
 
 out:
@@ -850,7 +850,7 @@ static void adsp_mm_save_context(void *storage_buffer)
 
 #ifdef CONFIG_MMU
 			arch_mem_map(UINT_TO_POINTER(phys_addr), phys_addr, CONFIG_MM_DRV_PAGE_SIZE,
-				     K_MEM_CACHE_WB);
+				     K_MEM_CACHE_WB | K_MEM_PERM_RW);
 #endif
 
 			/* Invalidate cache to avoid stalled data
diff --git a/drivers/mm/mm_drv_ti_rat.c b/drivers/mm/mm_drv_ti_rat.c
index b82bbc162ac..44a9cd30627 100644
--- a/drivers/mm/mm_drv_ti_rat.c
+++ b/drivers/mm/mm_drv_ti_rat.c
@@ -24,7 +24,21 @@
 #include <zephyr/drivers/mm/system_mm.h>
 #include <zephyr/sys/__assert.h>
 
-static struct address_trans_params translate_config;
+#define ADDR_TRANSLATE_MAX_REGIONS (16u)
+#define RAT_CTRL(base_addr, i)     (base_addr + 0x20 + 0x10 * (i))
+#define RAT_BASE(base_addr, i)     (base_addr + 0x24 + 0x10 * (i))
+#define RAT_TRANS_L(base_addr, i)  (base_addr + 0x28 + 0x10 * (i))
+#define RAT_TRANS_H(base_addr, i)  (base_addr + 0x2C + 0x10 * (i))
+#define RAT_CTRL_W(enable, size)   (((enable & 0x1) << 31u) | (size & 0x3F))
+
+/**
+ * @brief Parameters for address_trans_init
+ */
+static struct address_trans_params {
+	uint32_t num_regions;
+	uint32_t rat_base_addr;
+	struct address_trans_region_config *region_config;
+} translate_config;
 
 /**
  * @brief Set registers for the address regions being used
@@ -34,13 +48,13 @@ static struct address_trans_params translate_config;
  * @param enable Region status
  */
 
-static void address_trans_set_region(struct address_trans_params *addr_translate_config,
+static void address_trans_set_region(struct address_trans_region_config *region_config,
 			uint16_t region_num, uint32_t enable)
 {
-	uint32_t rat_base_addr = addr_translate_config->rat_base_addr;
-	uint64_t system_addr = addr_translate_config->region_config[region_num].system_addr;
-	uint32_t local_addr = addr_translate_config->region_config[region_num].local_addr;
-	uint32_t size = addr_translate_config->region_config[region_num].size;
+	uint32_t rat_base_addr = translate_config.rat_base_addr;
+	uint64_t system_addr = region_config->system_addr;
+	uint32_t local_addr = region_config->local_addr;
+	uint32_t size = region_config->size;
 	uint32_t system_addrL, system_addrH;
 
 	if (size > address_trans_region_size_4G) {
@@ -57,27 +71,6 @@ static void address_trans_set_region(struct address_trans_params *addr_translate
 	sys_write32(RAT_CTRL_W(enable, size), RAT_CTRL(rat_base_addr, region_num));
 }
 
-static void address_trans_init(struct address_trans_params *params)
-{
-	uint32_t i;
-
-	if (params != NULL) {
-		translate_config = *params;
-	}
-
-	__ASSERT(translate_config.num_regions < ADDR_TRANSLATE_MAX_REGIONS,
-		 "Exceeding maximum number of regions");
-
-	for (i = 0; i < translate_config.num_regions; i++) {
-		__ASSERT(translate_config.rat_base_addr != 0, "RAT base address cannot be 0");
-		__ASSERT(translate_config.region_config != NULL,
-			 "RAT region config cannot be NULL");
-
-		/* enable regions setup by user */
-		address_trans_set_region(&translate_config, i, 1);
-	}
-}
-
 /**
  * @brief Initialise RAT module
  *
@@ -86,59 +79,60 @@ static void address_trans_init(struct address_trans_params *params)
  * @param translate_regions Number of regions being initialised
  */
 
-void sys_mm_drv_ti_rat_init(void *region_config, uint64_t rat_base_addr, uint8_t translate_regions)
+void sys_mm_drv_ti_rat_init(struct address_trans_region_config *region_config,
+			    uint64_t rat_base_addr, uint8_t translate_regions)
 {
+	uint32_t i;
+
+	__ASSERT(translate_regions < ADDR_TRANSLATE_MAX_REGIONS, "Maximum regions exceeded");
+	__ASSERT(rat_base_addr != 0, "RAT base address cannot be 0");
+	__ASSERT(region_config != NULL, "RAT region config cannot be NULL");
+
 	translate_config.num_regions = translate_regions;
 	translate_config.rat_base_addr = rat_base_addr;
-	translate_config.region_config = (struct address_trans_region_config *)region_config;
+	translate_config.region_config = region_config;
 
-	address_trans_init(&translate_config);
+	/* enable regions setup by user */
+	for (i = 0; i < translate_regions; i++) {
+		address_trans_set_region(&region_config[i], i, 1);
+	}
 }
 
 int sys_mm_drv_page_phys_get(void *virt, uintptr_t *phys)
 {
-	if (virt == NULL) {
-		return -EINVAL;
+	if (phys == NULL) {
+		/*
+		 * NULL phys means the caller wants to check if a virtual address is
+		 * valid. For RAT, even addresses without a mapping are still valid and
+		 * are mapped as pass-through in HW, so we always return 0(valid) here.
+		 */
+		return 0;
 	}
 	uintptr_t pa = (uintptr_t) virt;
 	uintptr_t *va = phys;
 
-	uint32_t found, regionId;
-
-	__ASSERT(translate_config.num_regions < ADDR_TRANSLATE_MAX_REGIONS,
-		 "Exceeding maximum number of regions");
-
-	found = 0;
+	uint32_t regionId;
 
 	for (regionId = 0; regionId < translate_config.num_regions; regionId++) {
-		uint64_t start_addr, end_addr;
-		uint32_t size_mask;
+		struct address_trans_region_config *region_config =
+			&translate_config.region_config[regionId];
 
-		size_mask =
-			((uint32_t)((BIT64_MASK(translate_config.region_config[regionId].size))));
+		uint64_t start_addr = region_config->system_addr;
+		uint64_t end_addr = start_addr + BIT64_MASK(region_config->size);
 
-		start_addr = translate_config.region_config[regionId].system_addr;
-
-		end_addr = start_addr + size_mask;
-
-		if (pa >= start_addr && pa <= end_addr) {
-			found = 1;
-			break;
+		if (pa < start_addr || pa > end_addr) {
+			continue;
 		}
-	}
-	if (found) {
+
 		/* translate input address to output address */
-		uint32_t offset =
-			pa - translate_config.region_config[regionId].system_addr;
+		uint32_t offset = pa - start_addr;
+		*va = region_config->local_addr + offset;
 
-		*va = (translate_config.region_config[regionId].local_addr + offset);
-	} else {
-		/* no mapping found, set output = input with 32b truncation */
-		*va = pa;
+		return 0;
 	}
 
-	if (va == NULL) {
-		return -EFAULT;
-	}
+	/* no mapping found, set output = input with 32b truncation */
+	*va = pa;
+
 	return 0;
 }
diff --git a/drivers/modem/Kconfig b/drivers/modem/Kconfig
index 7219312e18f..b8e66ef4274 100644
--- a/drivers/modem/Kconfig
+++ b/drivers/modem/Kconfig
@@ -146,6 +146,7 @@ endif # MODEM_CONTEXT
 
 config MODEM_SOCKET
 	bool "Generic modem socket support layer"
+	depends on NET_SOCKETS
 	help
 	  This layer provides much of the groundwork for keeping track of
 	  modem "sockets" throughout their lifecycle (from the initial offload
diff --git a/drivers/modem/hl7800.c b/drivers/modem/hl7800.c
index a30d3cbd8c6..58e4f663838 100644
--- a/drivers/modem/hl7800.c
+++ b/drivers/modem/hl7800.c
@@ -252,6 +252,7 @@ struct xmodem_packet {
 #define DNS_WORK_DELAY_SECS 1
 #define IFACE_WORK_DELAY K_MSEC(500)
 #define SOCKET_CLEANUP_WORK_DELAY K_MSEC(100)
+#define STORED_SOCKETS_DELAY K_SECONDS(1)
 #define WAIT_FOR_KSUP_RETRIES 5
 
 #define CGCONTRDP_RESPONSE_NUM_DELIMS 7
@@ -427,6 +428,7 @@ struct hl7800_iface_ctx {
 	bool wait_for_KSUP;
 	uint32_t wait_for_KSUP_tries;
 	bool reconfig_IP_connection;
+	bool reset_sockets;
 	char dns_v4_string[NET_IPV4_ADDR_LEN];
 	char no_id_resp_cmd[NO_ID_RESP_CMD_MAX_LENGTH];
 	bool search_no_id_resp;
@@ -456,6 +458,7 @@ struct hl7800_iface_ctx {
 	/* semaphores */
 	struct k_sem response_sem;
 	struct k_sem mdm_awake;
+	struct k_sem wait_urc;
 
 	/* work */
 	struct k_work_delayable rssi_query_work;
@@ -476,6 +479,7 @@ struct hl7800_iface_ctx {
 	int file_pos;
 	struct k_work finish_fw_update_work;
 	bool fw_updated;
+	bool fw_updating;
 #endif
 
 	/* modem info */
@@ -520,11 +524,14 @@ struct hl7800_iface_ctx {
 	struct tm local_time;
 	int32_t local_time_offset;
 	bool local_time_valid;
-	bool configured;
+	enum mdm_hl7800_state state;
 	bool off;
 	void (*wake_up_callback)(int state);
 	void (*gpio6_callback)(int state);
 	void (*cts_callback)(int state);
+	bool user_at_cmd;
+	char *user_at_cmd_resp_buf;
+	uint16_t user_at_cmd_resp_buf_len;
 
 #ifdef CONFIG_MODEM_HL7800_GPS
 	struct k_work_delayable gps_work;
@@ -562,6 +569,9 @@ static char *get_sleep_state_string(enum mdm_hl7800_sleep state);
 static void set_network_state(enum mdm_hl7800_network_state state);
 static void set_startup_state(enum mdm_hl7800_startup_state state);
 static void set_sleep_state(enum mdm_hl7800_sleep state);
+static void set_state(enum mdm_hl7800_state state);
+static void generate_state_event(void);
+static char *get_state_string(enum mdm_hl7800_state state);
 static void generate_network_state_event(void);
 static void generate_startup_state_event(void);
 static void generate_sleep_state_event(void);
@@ -812,6 +822,11 @@ static struct hl7800_socket *socket_from_id(int socket_id)
 
 static inline void set_busy(bool busy)
 {
+#ifdef CONFIG_MODEM_HL7800_FW_UPDATE
+	if (iface_ctx.fw_updating && !busy) {
+		return;
+	}
+#endif
 	iface_ctx.busy = busy;
 }
 
@@ -1073,7 +1088,8 @@ static int wakeup_hl7800(void)
 	return 0;
 }
 
-int32_t mdm_hl7800_send_at_cmd(const uint8_t *data)
+int32_t mdm_hl7800_send_at_cmd(const uint8_t *data, uint8_t resp_timeout, char *resp,
+			       uint16_t *resp_len)
 {
 	int ret;
 
@@ -1084,7 +1100,21 @@ int32_t mdm_hl7800_send_at_cmd(const uint8_t *data)
 	hl7800_lock();
 	wakeup_hl7800();
 	iface_ctx.last_socket_id = 0;
-	ret = send_at_cmd(NULL, data, MDM_CMD_SEND_TIMEOUT, 0, false);
+	iface_ctx.user_at_cmd = true;
+	iface_ctx.user_at_cmd_resp_buf = resp;
+	if (resp_len) {
+		iface_ctx.user_at_cmd_resp_buf_len = *resp_len;
+	} else {
+		iface_ctx.user_at_cmd_resp_buf_len = 0;
+	}
+	if (iface_ctx.user_at_cmd_resp_buf) {
+		iface_ctx.user_at_cmd_resp_buf[0] = '\0';
+	}
+	ret = send_at_cmd(NULL, data, K_SECONDS(resp_timeout), 0, false);
+	iface_ctx.user_at_cmd = false;
+	if (resp_len && iface_ctx.user_at_cmd_resp_buf) {
+		*resp_len = strlen(iface_ctx.user_at_cmd_resp_buf);
+	}
 	set_busy(false);
 	allow_sleep(true);
 	hl7800_unlock();
@@ -1391,6 +1421,7 @@ void mdm_hl7800_generate_status_events(void)
 	event_handler(HL7800_EVENT_BANDS, iface_ctx.mdm_bands_string);
 	event_handler(HL7800_EVENT_ACTIVE_BANDS, iface_ctx.mdm_active_bands_string);
 	event_handler(HL7800_EVENT_REVISION, iface_ctx.mdm_revision);
+	generate_state_event();
 	hl7800_unlock();
 }
 
@@ -1440,7 +1471,7 @@ static int send_data(struct hl7800_socket *sock, struct net_pkt *pkt)
 		}
 		snprintk(buf, sizeof(buf), "AT+KUDPSND=%d,\"%s\",%u,%zu",
 			 sock->socket_id, dst_addr,
-			 net_sin(&sock->dst)->sin_port, send_len);
+			 ntohs(net_sin(&sock->dst)->sin_port), send_len);
 	}
 	send_at_cmd(sock, buf, K_NO_WAIT, 0, false);
 
@@ -1590,8 +1621,8 @@ static int pkt_setup_ip_data(struct net_pkt *pkt, struct hl7800_socket *sock)
 		}
 		net_pkt_set_remote_address(pkt, &sock->dst, sizeof(struct sockaddr_in6));
 		pkt->remote.sa_family = AF_INET6;
-		src_port = ntohs(net_sin6(&sock->src)->sin6_port);
-		dst_port = ntohs(net_sin6(&sock->dst)->sin6_port);
+		src_port = net_sin6(&sock->src)->sin6_port;
+		dst_port = net_sin6(&sock->dst)->sin6_port;
 
 		hdr_len = sizeof(struct net_ipv6_hdr);
 	}
@@ -1605,8 +1636,8 @@ static int pkt_setup_ip_data(struct net_pkt *pkt, struct hl7800_socket *sock)
 		}
 		net_pkt_set_remote_address(pkt, &sock->dst, sizeof(struct sockaddr_in));
 		pkt->remote.sa_family = AF_INET;
-		src_port = ntohs(net_sin(&sock->src)->sin_port);
-		dst_port = ntohs(net_sin(&sock->dst)->sin_port);
+		src_port = net_sin(&sock->src)->sin_port;
+		dst_port = net_sin(&sock->dst)->sin_port;
 
 		hdr_len = sizeof(struct net_ipv4_hdr);
 	}
@@ -1945,7 +1976,7 @@ static void dns_work_cb(struct k_work *work)
 			LOG_DBG("DNS ready");
 			iface_ctx.dns_ready = true;
 		} else {
-			LOG_DBG("DNS not ready, schedule a retry");
+			LOG_WRN("DNS not ready, schedule a retry");
 			k_work_reschedule_for_queue(&hl7800_workq, &iface_ctx.dns_work,
 						    K_SECONDS(DNS_WORK_DELAY_SECS * 2));
 		}
@@ -2531,6 +2562,34 @@ static void set_sleep_state(enum mdm_hl7800_sleep state)
 	generate_sleep_state_event();
 }
 
+static char *get_state_string(enum mdm_hl7800_state state)
+{
+	/* clang-format off */
+	switch (state) {
+		PREFIXED_SWITCH_CASE_RETURN_STRING(HL7800_STATE, NOT_READY);
+		PREFIXED_SWITCH_CASE_RETURN_STRING(HL7800_STATE, INITIALIZED);
+	default:
+		return "UNKNOWN";
+	}
+	/* clang-format on */
+}
+
+static void generate_state_event(void)
+{
+	struct mdm_hl7800_compound_event event;
+
+	event.code = iface_ctx.state;
+	event.string = get_state_string(iface_ctx.state);
+	LOG_INF("State: %s", event.string);
+	event_handler(HL7800_EVENT_STATE, &event);
+}
+
+static void set_state(enum mdm_hl7800_state state)
+{
+	iface_ctx.state = state;
+	generate_state_event();
+}
+
 static void generate_sleep_state_event(void)
 {
 	struct mdm_hl7800_compound_event event;
@@ -2604,6 +2663,7 @@ static bool on_cmd_startup_report(struct net_buf **buf, uint16_t len)
 #ifdef CONFIG_MODEM_HL7800_FW_UPDATE
 	if (iface_ctx.fw_updated) {
 		iface_ctx.fw_updated = false;
+		iface_ctx.fw_updating = false;
 		set_fota_state(HL7800_FOTA_REBOOT_AND_RECONFIGURE);
 		/* issue reset after a firmware update to reconfigure modem state */
 		k_work_reschedule_for_queue(&hl7800_workq, &iface_ctx.mdm_reset_work,
@@ -3823,9 +3883,9 @@ static bool on_cmd_sockerror(struct net_buf **buf, uint16_t len)
 		LOG_ERR("'%s'", string);
 	}
 
+	iface_ctx.last_error = -EIO;
 	sock = socket_from_id(iface_ctx.last_socket_id);
 	if (!sock) {
-		iface_ctx.last_error = -EIO;
 		k_sem_give(&iface_ctx.response_sem);
 	} else {
 		sock->error = -EIO;
@@ -3844,12 +3904,11 @@ static bool on_cmd_sock_error_code(struct net_buf **buf, uint16_t len)
 
 	out_len = net_buf_linearize(value, sizeof(value), *buf, 0, len);
 	value[out_len] = 0;
-
+	iface_ctx.last_error = strtol(value, NULL, 10);
 	LOG_ERR("Error code: %s", value);
 
 	sock = socket_from_id(iface_ctx.last_socket_id);
 	if (!sock) {
-		iface_ctx.last_error = -EIO;
 		k_sem_give(&iface_ctx.response_sem);
 	} else {
 		sock->error = -EIO;
@@ -4009,7 +4068,8 @@ static bool on_cmd_sockcreate(enum net_sock_type type, struct net_buf **buf, uin
 	if (!sock) {
 		LOG_DBG("look up new socket by creation id");
 		sock = socket_from_id(MDM_CREATE_SOCKET_ID);
-		if (!sock || sock->type != type) {
+		if (iface_ctx.reset_sockets || !sock || sock->type != type) {
+			iface_ctx.reset_sockets = false;
 			if (queue_stale_socket(type, iface_ctx.last_socket_id) == 0) {
 				/* delay some time before socket cleanup in case there
 				 * are multiple sockets to cleanup
@@ -4027,6 +4087,9 @@ static bool on_cmd_sockcreate(enum net_sock_type type, struct net_buf **buf, uin
 	sock->reconfig = false;
 	/* don't give back semaphore -- OK to follow */
 done:
+	if (iface_ctx.reconfig_IP_connection) {
+		k_sem_give(&iface_ctx.wait_urc);
+	}
 	return true;
 }
 
@@ -4581,7 +4644,8 @@ static void hl7800_rx(void *p1, void *p2, void *p3)
 	struct net_buf *rx_buf = NULL;
 	struct net_buf *frag = NULL;
 	int i, cmp_res;
-	uint16_t len;
+	uint16_t len, resp_offset;
+	int16_t resp_max_len;
 	size_t out_len;
 	bool cmd_handled = false;
 	static char rx_msg[MDM_HANDLER_MATCH_MAX_LEN];
@@ -4770,6 +4834,30 @@ static void hl7800_rx(void *p1, void *p2, void *p3)
 				}
 			}
 
+			if (iface_ctx.user_at_cmd && iface_ctx.user_at_cmd_resp_buf &&
+			    iface_ctx.user_at_cmd_resp_buf_len > 0 && frag && len > 1) {
+				/* Get the current length of the response. Multi-line responses will
+				 * be appended.
+				 */
+				resp_offset = strlen(iface_ctx.user_at_cmd_resp_buf);
+				/* Make sure we have room for the new data and '\n\0' */
+				resp_max_len = iface_ctx.user_at_cmd_resp_buf_len - resp_offset - 2;
+				if (resp_max_len < 0) {
+					resp_max_len = 0;
+				}
+				if (resp_max_len > 0) {
+					out_len = net_buf_linearize(iface_ctx.user_at_cmd_resp_buf +
+									    resp_offset,
+								    resp_max_len, rx_buf, 0, len);
+					/* Add '\n\0' to terminate the response */
+					memcpy(iface_ctx.user_at_cmd_resp_buf + resp_offset +
+						       out_len,
+					       "\n\0", 2);
+				} else {
+					LOG_WRN("User AT cmd resp buf full");
+				}
+			}
+
 			/* Handle unhandled commands */
 			if (IS_ENABLED(HL7800_LOG_UNHANDLED_RX_MSGS) &&
 			    !cmd_handled && frag && len > 1) {
@@ -5313,11 +5401,11 @@ static int modem_reset_and_configure(void)
 
 	/* If CONFIG_MODEM_HL7800_RAT_M1 or CONFIG_MODEM_HL7800_RAT_NB1, then
 	 * set the radio mode. This is only done here if the driver has not been
-	 * initialized (!iface_ctx.configured) yet because the public API also
+	 * initialized yet because the public API also
 	 * allows the RAT to be changed (and will reset the modem).
 	 */
 #ifndef CONFIG_MODEM_HL7800_RAT_NO_CHANGE
-	if (!iface_ctx.configured) {
+	if (iface_ctx.state == HL7800_STATE_NOT_READY) {
 #if CONFIG_MODEM_HL7800_RAT_M1
 		if (iface_ctx.mdm_rat != MDM_RAT_CAT_M1) {
 			if (iface_ctx.new_rat_cmd_support) {
@@ -5517,14 +5605,11 @@ static int modem_reset_and_configure(void)
 		config_apn = true;
 	}
 
-	/* Query PDP authentication context to get APN username/password.
-	 * Temporary Workaround - Ignore error
-	 * On some modules this is returning an error and the response data.
-	 */
-	SEND_AT_CMD_IGNORE_ERROR("AT+WPPP?");
+	/* Disable PDP authentication, the driver does not support it */
+	SEND_AT_CMD_EXPECT_OK("AT+WPPP=0");
 
 #if CONFIG_MODEM_HL7800_SET_APN_NAME_ON_STARTUP
-	if (!iface_ctx.configured) {
+	if (iface_ctx.state == HL7800_STATE_NOT_READY) {
 		if (strncmp(iface_ctx.mdm_apn.value, CONFIG_MODEM_HL7800_APN_NAME,
 			    MDM_HL7800_APN_MAX_STRLEN) != 0) {
 			apn = CONFIG_MODEM_HL7800_APN_NAME;
@@ -5553,12 +5638,6 @@ static int modem_reset_and_configure(void)
 	/* Turn on EPS network registration status reporting */
 	SEND_AT_CMD_EXPECT_OK("AT+CEREG=5");
 
-	/* query all socket configs to cleanup any sockets that are not
-	 * tracked by the driver
-	 */
-	SEND_AT_CMD_EXPECT_OK("AT+KTCPCFG?");
-	SEND_AT_CMD_EXPECT_OK("AT+KUDPCFG?");
-
 	/* Enabled the LTE radio */
 #if !defined(CONFIG_MODEM_HL7800_BOOT_IN_AIRPLANE_MODE)
 	SEND_AT_CMD_EXPECT_OK("AT+CFUN=1,0");
@@ -5569,7 +5648,7 @@ static int modem_reset_and_configure(void)
 	 */
 	LOG_INF("Modem ready!");
 	iface_ctx.restarting = false;
-	iface_ctx.configured = true;
+	set_state(HL7800_STATE_INITIALIZED);
 	set_busy(false);
 	allow_sleep(sleep);
 	/* trigger APN update event */
@@ -5591,7 +5670,7 @@ static int modem_reset_and_configure(void)
 
 error:
 	LOG_ERR("Unable to configure modem");
-	iface_ctx.configured = false;
+	set_state(HL7800_STATE_NOT_READY);
 	set_network_state(HL7800_UNABLE_TO_CONFIGURE);
 	/* Kernel will fault with non-zero return value.
 	 * Allow other parts of application to run when modem cannot be configured.
@@ -5621,20 +5700,16 @@ static void mdm_reset_work_callback(struct k_work *item)
 {
 	ARG_UNUSED(item);
 
-	mdm_hl7800_reset();
-}
-
-int32_t mdm_hl7800_reset(void)
-{
-	int ret;
-
 	hl7800_lock();
 
-	ret = modem_reset_and_configure();
+	(void)modem_reset_and_configure();
 
 	hl7800_unlock();
+}
 
-	return ret;
+int32_t mdm_hl7800_reset(void)
+{
+	return k_work_reschedule_for_queue(&hl7800_workq, &iface_ctx.mdm_reset_work, K_NO_WAIT);
 }
 
 static void mdm_power_off_work_callback(struct k_work *item)
@@ -5660,7 +5735,7 @@ static void mdm_power_off_work_callback(struct k_work *item)
 	}
 	prepare_io_for_reset();
 	iface_ctx.dns_ready = false;
-	iface_ctx.configured = false;
+	set_state(HL7800_STATE_NOT_READY);
 	iface_ctx.off = true;
 	set_busy(false);
 	/* bring the iface down */
@@ -5668,6 +5743,9 @@ static void mdm_power_off_work_callback(struct k_work *item)
 		net_if_carrier_off(iface_ctx.iface);
 	}
 	LOG_INF("Modem powered off");
+	set_sleep_state(HL7800_SLEEP_UNINITIALIZED);
+	set_network_state(HL7800_NOT_REGISTERED);
+	set_startup_state(HL7800_STARTUP_STATE_UNKNOWN);
 
 	hl7800_unlock();
 }
@@ -5782,10 +5860,10 @@ static int configure_TCP_socket(struct hl7800_socket *sock)
 
 	if (sock->dst.sa_family == AF_INET6) {
 		af = MDM_HL7800_SOCKET_AF_IPV6;
-		dst_port = net_sin6(&sock->dst)->sin6_port;
+		dst_port = ntohs(net_sin6(&sock->dst)->sin6_port);
 	} else if (sock->dst.sa_family == AF_INET) {
 		af = MDM_HL7800_SOCKET_AF_IPV4;
-		dst_port = net_sin(&sock->dst)->sin_port;
+		dst_port = ntohs(net_sin(&sock->dst)->sin_port);
 	} else {
 		return -EINVAL;
 	}
@@ -5855,8 +5933,6 @@ static int reconfigure_IP_connection(void)
 	int ret = 0;
 
 	if (iface_ctx.reconfig_IP_connection) {
-		iface_ctx.reconfig_IP_connection = false;
-
 		/* reconfigure GPRS connection so sockets can be used */
 		ret = setup_gprs_connection(iface_ctx.mdm_apn.value);
 		if (ret < 0) {
@@ -5864,6 +5940,8 @@ static int reconfigure_IP_connection(void)
 			goto done;
 		}
 
+		k_sem_reset(&iface_ctx.wait_urc);
+
 		/* query all TCP socket configs */
 		ret = send_at_cmd(NULL, "AT+KTCPCFG?", MDM_CMD_SEND_TIMEOUT, 0,
 				  false);
@@ -5872,8 +5950,13 @@ static int reconfigure_IP_connection(void)
 		ret = send_at_cmd(NULL, "AT+KUDPCFG?", MDM_CMD_SEND_TIMEOUT, 0,
 				  false);
 
-		/* TODO: to make this better, wait for +KUDP_IND or timeout */
-		k_sleep(K_SECONDS(1));
+		ret = k_sem_take(&iface_ctx.wait_urc, STORED_SOCKETS_DELAY);
+		if (ret == -EAGAIN) {
+			/* There are no sockets to reset */
+			iface_ctx.reset_sockets = false;
+		}
+
+		iface_ctx.reconfig_IP_connection = false;
 	}
 
 done:
@@ -6006,7 +6089,7 @@ static int offload_connect(struct net_context *context,
 	if (addr->sa_family == AF_INET6) {
 		net_ipaddr_copy(&net_sin6(&sock->dst)->sin6_addr,
 				&net_sin6(addr)->sin6_addr);
-		dst_port = ntohs(net_sin6(addr)->sin6_port);
+		dst_port = net_sin6(addr)->sin6_port;
 		net_sin6(&sock->dst)->sin6_port = dst_port;
 	} else
 #endif
@@ -6014,7 +6097,7 @@ static int offload_connect(struct net_context *context,
 		if (addr->sa_family == AF_INET) {
 		net_ipaddr_copy(&net_sin(&sock->dst)->sin_addr,
 				&net_sin(addr)->sin_addr);
-		dst_port = ntohs(net_sin(addr)->sin_port);
+		dst_port = net_sin(addr)->sin_port;
 		net_sin(&sock->dst)->sin_port = dst_port;
 	} else
 #endif
@@ -6023,7 +6106,7 @@ static int offload_connect(struct net_context *context,
 	}
 
 	if (dst_port < 0) {
-		LOG_ERR("Invalid port: %d", dst_port);
+		LOG_ERR("Invalid port: %d", ntohs(dst_port));
 		return -EINVAL;
 	}
 
@@ -6074,7 +6157,7 @@ static int offload_sendto(struct net_pkt *pkt, const struct sockaddr *dst_addr,
 {
 	struct net_context *context = net_pkt_context(pkt);
 	struct hl7800_socket *sock;
-	int ret, dst_port = 0;
+	int ret;
 
 	if (!context) {
 		return -EINVAL;
@@ -6090,16 +6173,14 @@ static int offload_sendto(struct net_pkt *pkt, const struct sockaddr *dst_addr,
 	if (dst_addr->sa_family == AF_INET6) {
 		net_ipaddr_copy(&net_sin6(&sock->dst)->sin6_addr,
 				&net_sin6(dst_addr)->sin6_addr);
-		dst_port = ntohs(net_sin6(dst_addr)->sin6_port);
-		net_sin6(&sock->dst)->sin6_port = dst_port;
+		net_sin6(&sock->dst)->sin6_port = net_sin6(dst_addr)->sin6_port;
 	} else
 #endif
 #if defined(CONFIG_NET_IPV4)
 		if (dst_addr->sa_family == AF_INET) {
 		net_ipaddr_copy(&net_sin(&sock->dst)->sin_addr,
 				&net_sin(dst_addr)->sin_addr);
-		dst_port = ntohs(net_sin(dst_addr)->sin_port);
-		net_sin(&sock->dst)->sin_port = dst_port;
+		net_sin(&sock->dst)->sin_port = net_sin(dst_addr)->sin_port;
 	} else
 #endif
 	{
@@ -6278,11 +6359,14 @@ int32_t mdm_hl7800_update_fw(char *file_path)
 		goto err;
 	}
 
+	wakeup_hl7800();
+
 	/* turn on device service indications */
 	ret = send_at_cmd(NULL, "AT+WDSI=2", MDM_CMD_SEND_TIMEOUT, 0, false);
 	if (ret < 0) {
 		goto err;
 	}
+	iface_ctx.fw_updating = true;
 
 	notify_all_tcp_sockets_closed();
 	hl7800_stop_rssi_work();
@@ -6321,6 +6405,7 @@ static int hl7800_init(const struct device *dev)
 	ARG_UNUSED(dev);
 
 	LOG_DBG("HL7800 Init");
+	iface_ctx.reset_sockets = true;
 
 	/* The UART starts in the on state and CTS is set low by the HL7800 */
 	iface_ctx.cts_state = iface_ctx.last_cts_state = 0;
@@ -6350,6 +6435,7 @@ static int hl7800_init(const struct device *dev)
 	iface_ctx.last_socket_id = 0;
 	k_sem_init(&iface_ctx.response_sem, 0, 1);
 	k_sem_init(&iface_ctx.mdm_awake, 0, 1);
+	k_sem_init(&iface_ctx.wait_urc, 0, 1);
 
 	/* initialize the work queue */
 	k_work_queue_start(&hl7800_workq, hl7800_workq_stack,
@@ -6376,6 +6462,7 @@ static int hl7800_init(const struct device *dev)
 	k_work_init(&iface_ctx.finish_fw_update_work,
 		    finish_fw_update_work_callback);
 	iface_ctx.fw_updated = false;
+	iface_ctx.fw_updating = false;
 #endif
 
 	/* setup port devices and pin directions */
diff --git a/drivers/modem/modem_cellular.c b/drivers/modem/modem_cellular.c
index 826240beab9..2af67a01c7a 100644
--- a/drivers/modem/modem_cellular.c
+++ b/drivers/modem/modem_cellular.c
@@ -154,6 +154,7 @@ struct modem_cellular_config {
 	const struct device *uart;
 	struct gpio_dt_spec power_gpio;
 	struct gpio_dt_spec reset_gpio;
+	struct gpio_dt_spec wake_gpio;
 	uint16_t power_pulse_duration_ms;
 	uint16_t reset_pulse_duration_ms;
 	uint16_t startup_time_ms;
@@ -599,6 +600,10 @@ static int modem_cellular_on_idle_state_enter(struct modem_cellular_data *data)
 	const struct modem_cellular_config *config =
 		(const struct modem_cellular_config *)data->dev->config;
 
+	if (modem_cellular_gpio_is_enabled(&config->wake_gpio)) {
+		gpio_pin_set_dt(&config->wake_gpio, 0);
+	}
+
 	if (modem_cellular_gpio_is_enabled(&config->reset_gpio)) {
 		gpio_pin_set_dt(&config->reset_gpio, 1);
 	}
@@ -662,6 +667,10 @@ static int modem_cellular_on_idle_state_leave(struct modem_cellular_data *data)
 		gpio_pin_set_dt(&config->reset_gpio, 0);
 	}
 
+	if (modem_cellular_gpio_is_enabled(&config->wake_gpio)) {
+		gpio_pin_set_dt(&config->wake_gpio, 1);
+	}
+
 	return 0;
 }
 
@@ -670,6 +679,10 @@ static int modem_cellular_on_reset_pulse_state_enter(struct modem_cellular_data
 	const struct modem_cellular_config *config =
 		(const struct modem_cellular_config *)data->dev->config;
 
+	if (modem_cellular_gpio_is_enabled(&config->wake_gpio)) {
+		gpio_pin_set_dt(&config->wake_gpio, 0);
+	}
+
 	gpio_pin_set_dt(&config->reset_gpio, 1);
 	modem_cellular_start_timer(data, K_MSEC(config->reset_pulse_duration_ms));
 	return 0;
@@ -698,6 +711,11 @@ static int modem_cellular_on_reset_pulse_state_leave(struct modem_cellular_data
 		(const struct modem_cellular_config *)data->dev->config;
 
 	gpio_pin_set_dt(&config->reset_gpio, 0);
+
+	if (modem_cellular_gpio_is_enabled(&config->wake_gpio)) {
+		gpio_pin_set_dt(&config->wake_gpio, 1);
+	}
+
 	modem_cellular_stop_timer(data);
 	return 0;
 }
@@ -1715,6 +1733,10 @@ static int modem_cellular_init(const struct device *dev)
 
 	k_sem_init(&data->suspended_sem, 0, 1);
 
+	if (modem_cellular_gpio_is_enabled(&config->wake_gpio)) {
+		gpio_pin_configure_dt(&config->wake_gpio, GPIO_OUTPUT_INACTIVE);
+	}
+
 	if (modem_cellular_gpio_is_enabled(&config->power_gpio)) {
 		gpio_pin_configure_dt(&config->power_gpio, GPIO_OUTPUT_INACTIVE);
 	}
@@ -2127,10 +2149,16 @@ MODEM_CHAT_SCRIPT_DEFINE(u_blox_lara_r6_periodic_chat_script,
 
 #if DT_HAS_COMPAT_STATUS_OKAY(swir_hl7800)
 MODEM_CHAT_SCRIPT_CMDS_DEFINE(swir_hl7800_init_chat_script_cmds,
-			      MODEM_CHAT_SCRIPT_CMD_RESP_NONE("AT", 100),
-			      MODEM_CHAT_SCRIPT_CMD_RESP_NONE("AT", 100),
-			      MODEM_CHAT_SCRIPT_CMD_RESP_NONE("AT", 100),
-			      MODEM_CHAT_SCRIPT_CMD_RESP_NONE("AT", 100),
+			      MODEM_CHAT_SCRIPT_CMD_RESP_NONE("AT", 1000),
+			      MODEM_CHAT_SCRIPT_CMD_RESP_NONE("AT", 1000),
+			      MODEM_CHAT_SCRIPT_CMD_RESP_NONE("AT", 1000),
+			      MODEM_CHAT_SCRIPT_CMD_RESP_NONE("AT", 1000),
+			      /* Turn off sleep mode */
+			      MODEM_CHAT_SCRIPT_CMD_RESP("AT+KSLEEP=2", ok_match),
+			      /* Turn off PSM */
+			      MODEM_CHAT_SCRIPT_CMD_RESP("AT+CPSMS=0", ok_match),
+			      /* Turn off eDRX */
+			      MODEM_CHAT_SCRIPT_CMD_RESP("AT+CEDRXS=0", ok_match),
 			      MODEM_CHAT_SCRIPT_CMD_RESP("ATE0", ok_match),
 			      MODEM_CHAT_SCRIPT_CMD_RESP("AT+CFUN=1", ok_match),
 			      MODEM_CHAT_SCRIPT_CMD_RESP_MULT("AT+CGACT=0", allow_match),
@@ -2388,6 +2416,7 @@ MODEM_CHAT_SCRIPT_DEFINE(sqn_gm02s_periodic_chat_script,
 		.uart = DEVICE_DT_GET(DT_INST_BUS(inst)),                                          \
 		.power_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_power_gpios, {}),                 \
 		.reset_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_reset_gpios, {}),                 \
+		.wake_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, mdm_wake_gpios, {}),                   \
 		.power_pulse_duration_ms = (power_ms),                                             \
 		.reset_pulse_duration_ms = (reset_ms),                                             \
 		.startup_time_ms  = (startup_ms),                                                  \
diff --git a/drivers/modem/modem_cmd_handler.c b/drivers/modem/modem_cmd_handler.c
index 8bc84f5c5f2..99b15480515 100644
--- a/drivers/modem/modem_cmd_handler.c
+++ b/drivers/modem/modem_cmd_handler.c
@@ -99,12 +99,6 @@ static bool starts_with(struct net_buf *buf, const char *str)
  * Cmd Handler Functions
  */
 
-static inline struct net_buf *read_rx_allocator(k_timeout_t timeout,
-						void *user_data)
-{
-	return net_buf_alloc((struct net_buf_pool *)user_data, timeout);
-}
-
 /* return scanned length for params */
 static int parse_params(struct modem_cmd_handler_data *data,  size_t match_len,
 			const struct modem_cmd *cmd,
diff --git a/drivers/modem/modem_socket.c b/drivers/modem/modem_socket.c
index a30528ba899..81c5a5cd31d 100644
--- a/drivers/modem/modem_socket.c
+++ b/drivers/modem/modem_socket.c
@@ -437,6 +437,7 @@ int modem_socket_init(struct modem_socket_config *cfg, struct modem_socket *sock
 		k_sem_init(&cfg->sockets[i].sem_data_ready, 0, 1);
 		k_poll_signal_init(&cfg->sockets[i].sig_data_ready);
 		cfg->sockets[i].id = -1;
+		cfg->sockets[i].sock_fd = -1;
 	}
 	return 0;
 }
diff --git a/drivers/mspi/mspi_ambiq.h b/drivers/mspi/mspi_ambiq.h
index b289f190f7d..f8ca6789ae4 100644
--- a/drivers/mspi/mspi_ambiq.h
+++ b/drivers/mspi/mspi_ambiq.h
@@ -7,7 +7,7 @@
 #ifndef MSPI_AMBIQ_H_
 #define MSPI_AMBIQ_H_
 
-#include <am_mcu_apollo.h>
+#include <soc.h>
 
 /* Hand-calculated minimum heap sizes needed to return a successful
  * 1-byte allocation.  See details in lib/os/heap.[ch]
diff --git a/drivers/mspi/mspi_ambiq_ap3.c b/drivers/mspi/mspi_ambiq_ap3.c
index 12bdae882ae..0e2148c1e59 100644
--- a/drivers/mspi/mspi_ambiq_ap3.c
+++ b/drivers/mspi/mspi_ambiq_ap3.c
@@ -26,6 +26,14 @@ LOG_MODULE_REGISTER(mspi_ambiq_ap3);
 #define PWRCTRL_MAX_WAIT_US  5
 #define MSPI_BUSY            BIT(2)
 
+#if defined(CONFIG_SOC_APOLLO3_BLUE)
+#define MSPI_BASE_ADDR       MSPI_BASE
+#define MSPI_ADDR_INTERVAL   1
+#else
+#define MSPI_BASE_ADDR       MSPI0_BASE
+#define MSPI_ADDR_INTERVAL   (MSPI1_BASE - MSPI0_BASE)
+#endif
+
 typedef int (*mspi_ambiq_pwr_func_t)(void);
 typedef void (*irq_config_func_t)(void);
 
@@ -1356,8 +1364,8 @@ static DEVICE_API(mspi, mspi_ambiq_driver_api) = {
 
 #define MSPI_CONFIG(n)                                                                           \
 	{                                                                                        \
-		.channel_num           = (DT_INST_REG_ADDR(n) - MSPI0_BASE) /                    \
-					 (DT_INST_REG_SIZE(n) * 4),                              \
+		.channel_num           = (DT_INST_REG_ADDR(n) - MSPI_BASE_ADDR) /                \
+									 MSPI_ADDR_INTERVAL,     \
 		.op_mode               = MSPI_OP_MODE_CONTROLLER,                                \
 		.duplex                = MSPI_HALF_DUPLEX,                                       \
 		.max_freq              = MSPI_MAX_FREQ,                                          \
diff --git a/drivers/net/CMakeLists.txt b/drivers/net/CMakeLists.txt
index 456d27c02e9..ba3e44fd1f4 100644
--- a/drivers/net/CMakeLists.txt
+++ b/drivers/net/CMakeLists.txt
@@ -14,7 +14,6 @@ if(CONFIG_NET_NATIVE_OFFLOADED_SOCKETS)
   zephyr_library_include_directories(
     ${ZEPHYR_BASE}/subsys/net/lib/sockets
   )
-  zephyr_library_sources(nsos_errno.c)
   zephyr_library_sources(nsos_fcntl.c)
   zephyr_library_sources(nsos_netdb.c)
   zephyr_library_sources(nsos_sockets.c)
@@ -23,7 +22,6 @@ if(CONFIG_NET_NATIVE_OFFLOADED_SOCKETS)
     -DNSOS_EPOLL_WAIT_INTERVAL=${CONFIG_NET_NATIVE_OFFLOADED_SOCKETS_EPOLL_WAIT_INTERVAL}
   )
   target_sources(native_simulator INTERFACE nsos_adapt.c)
-  target_sources(native_simulator INTERFACE nsos_errno.c)
   target_sources(native_simulator INTERFACE nsos_fcntl.c)
   target_sources(native_simulator INTERFACE nsos_netdb.c)
 endif()
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index fc316d0f029..7b176606cfb 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -249,6 +249,7 @@ menuconfig NET_NATIVE_OFFLOADED_SOCKETS
 	depends on ARCH_POSIX
 	depends on NATIVE_LIBRARY
 	depends on NET_SOCKETS_OFFLOAD
+	select NATIVE_USE_NSI_ERRNO
 	help
 	  Offloaded sockets for Native Simulator utilize host BSD sockets API (like socket(),
 	  connect(), send(), recvfrom(), etc.) in order to provide networking capability.
diff --git a/drivers/net/nsos_adapt.c b/drivers/net/nsos_adapt.c
index 09da353f731..d1631efc651 100644
--- a/drivers/net/nsos_adapt.c
+++ b/drivers/net/nsos_adapt.c
@@ -29,7 +29,7 @@
 #include <unistd.h>
 
 #include "nsos.h"
-#include "nsos_errno.h"
+#include "nsi_errno.h"
 #include "nsos_fcntl.h"
 #include "nsos_netdb.h"
 #include "nsos_socket.h"
@@ -56,7 +56,7 @@ static int nsos_adapt_nfds;
 
 int nsos_adapt_get_errno(void)
 {
-	return errno_to_nsos_mid(errno);
+	return nsi_errno_to_mid(errno);
 }
 
 static int socket_family_from_nsos_mid(int family_mid, int *family)
@@ -79,7 +79,7 @@ static int socket_family_from_nsos_mid(int family_mid, int *family)
 		break;
 	default:
 		nsi_print_warning("%s: socket family %d not supported\n", __func__, family_mid);
-		return -NSOS_MID_EAFNOSUPPORT;
+		return -NSI_ERRNO_MID_EAFNOSUPPORT;
 	}
 
 	return 0;
@@ -105,7 +105,7 @@ static int socket_family_to_nsos_mid(int family, int *family_mid)
 		break;
 	default:
 		nsi_print_warning("%s: socket family %d not supported\n", __func__, family);
-		return -NSOS_MID_EAFNOSUPPORT;
+		return -NSI_ERRNO_MID_EAFNOSUPPORT;
 	}
 
 	return 0;
@@ -143,7 +143,7 @@ static int socket_proto_from_nsos_mid(int proto_mid, int *proto)
 		break;
 	default:
 		nsi_print_warning("%s: socket protocol %d not supported\n", __func__, proto_mid);
-		return -NSOS_MID_EPROTONOSUPPORT;
+		return -NSI_ERRNO_MID_EPROTONOSUPPORT;
 	}
 
 	return 0;
@@ -181,7 +181,7 @@ static int socket_proto_to_nsos_mid(int proto, int *proto_mid)
 		break;
 	default:
 		nsi_print_warning("%s: socket protocol %d not supported\n", __func__, proto);
-		return -NSOS_MID_EPROTONOSUPPORT;
+		return -NSI_ERRNO_MID_EPROTONOSUPPORT;
 	}
 
 	return 0;
@@ -201,7 +201,7 @@ static int socket_type_from_nsos_mid(int type_mid, int *type)
 		break;
 	default:
 		nsi_print_warning("%s: socket type %d not supported\n", __func__, type_mid);
-		return -NSOS_MID_ESOCKTNOSUPPORT;
+		return -NSI_ERRNO_MID_ESOCKTNOSUPPORT;
 	}
 
 	return 0;
@@ -221,7 +221,7 @@ static int socket_type_to_nsos_mid(int type, int *type_mid)
 		break;
 	default:
 		nsi_print_warning("%s: socket type %d not supported\n", __func__, type);
-		return -NSOS_MID_ESOCKTNOSUPPORT;
+		return -NSI_ERRNO_MID_ESOCKTNOSUPPORT;
 	}
 
 	return 0;
@@ -241,7 +241,7 @@ static int socket_flags_from_nsos_mid(int flags_mid)
 				 &flags, MSG_WAITALL);
 
 	if (flags_mid != 0) {
-		return -NSOS_MID_EINVAL;
+		return -NSI_ERRNO_MID_EINVAL;
 	}
 
 	return flags;
@@ -271,7 +271,7 @@ int nsos_adapt_socket(int family_mid, int type_mid, int proto_mid)
 
 	ret = socket(family, type, proto);
 	if (ret < 0) {
-		return -errno_to_nsos_mid(errno);
+		return -nsi_errno_to_mid(errno);
 	}
 
 	return ret;
@@ -350,7 +350,7 @@ static int sockaddr_from_nsos_mid(struct sockaddr **addr, socklen_t *addrlen,
 	}
 	}
 
-	return -NSOS_MID_EINVAL;
+	return -NSI_ERRNO_MID_EINVAL;
 }
 
 static int sockaddr_to_nsos_mid(const struct sockaddr *addr, socklen_t addrlen,
@@ -437,7 +437,7 @@ static int sockaddr_to_nsos_mid(const struct sockaddr *addr, socklen_t addrlen,
 
 	nsi_print_warning("%s: socket family %d not supported\n", __func__, addr->sa_family);
 
-	return -NSOS_MID_EINVAL;
+	return -NSI_ERRNO_MID_EINVAL;
 }
 
 int nsos_adapt_bind(int fd, const struct nsos_mid_sockaddr *addr_mid, size_t addrlen_mid)
@@ -454,7 +454,7 @@ int nsos_adapt_bind(int fd, const struct nsos_mid_sockaddr *addr_mid, size_t add
 
 	ret = bind(fd, addr, addrlen);
 	if (ret < 0) {
-		return -errno_to_nsos_mid(errno);
+		return -nsi_errno_to_mid(errno);
 	}
 
 	return ret;
@@ -474,7 +474,7 @@ int nsos_adapt_connect(int fd, const struct nsos_mid_sockaddr *addr_mid, size_t
 
 	ret = connect(fd, addr, addrlen);
 	if (ret < 0) {
-		return -errno_to_nsos_mid(errno);
+		return -nsi_errno_to_mid(errno);
 	}
 
 	return ret;
@@ -486,7 +486,7 @@ int nsos_adapt_listen(int fd, int backlog)
 
 	ret = listen(fd, backlog);
 	if (ret < 0) {
-		return -errno_to_nsos_mid(errno);
+		return -nsi_errno_to_mid(errno);
 	}
 
 	return ret;
@@ -502,7 +502,7 @@ int nsos_adapt_accept(int fd, struct nsos_mid_sockaddr *addr_mid, size_t *addrle
 
 	ret = accept(fd, addr, &addrlen);
 	if (ret < 0) {
-		return -errno_to_nsos_mid(errno);
+		return -nsi_errno_to_mid(errno);
 	}
 
 	err = sockaddr_to_nsos_mid(addr, addrlen, addr_mid, addrlen_mid);
@@ -531,7 +531,7 @@ int nsos_adapt_sendto(int fd, const void *buf, size_t len, int flags,
 		     socket_flags_from_nsos_mid(flags) | MSG_NOSIGNAL,
 		     addr, addrlen);
 	if (ret < 0) {
-		return -errno_to_nsos_mid(errno);
+		return -nsi_errno_to_mid(errno);
 	}
 
 	return ret;
@@ -572,7 +572,7 @@ int nsos_adapt_sendmsg(int fd, const struct nsos_mid_msghdr *msg_mid, int flags)
 
 	ret = sendmsg(fd, &msg, socket_flags_from_nsos_mid(flags) | MSG_NOSIGNAL);
 	if (ret < 0) {
-		ret = -errno_to_nsos_mid(errno);
+		ret = -nsi_errno_to_mid(errno);
 	}
 
 	free(msg_iov);
@@ -592,7 +592,7 @@ int nsos_adapt_recvfrom(int fd, void *buf, size_t len, int flags,
 	ret = recvfrom(fd, buf, len, socket_flags_from_nsos_mid(flags),
 		       addr, &addrlen);
 	if (ret < 0) {
-		return -errno_to_nsos_mid(errno);
+		return -nsi_errno_to_mid(errno);
 	}
 
 	err = sockaddr_to_nsos_mid(addr, addrlen, addr_mid, addrlen_mid);
@@ -611,7 +611,7 @@ static int nsos_adapt_getsockopt_int(int fd, int level, int optname,
 
 	ret = getsockopt(fd, level, optname, optval, &optlen);
 	if (ret < 0) {
-		return -errno_to_nsos_mid(errno);
+		return -nsi_errno_to_mid(errno);
 	}
 
 	*nsos_mid_optlen = optlen;
@@ -632,10 +632,10 @@ int nsos_adapt_getsockopt(int fd, int nsos_mid_level, int nsos_mid_optname,
 
 			ret = getsockopt(fd, SOL_SOCKET, SO_ERROR, &err, &optlen);
 			if (ret < 0) {
-				return -errno_to_nsos_mid(errno);
+				return -nsi_errno_to_mid(errno);
 			}
 
-			*(int *)nsos_mid_optval = errno_to_nsos_mid(err);
+			*(int *)nsos_mid_optval = nsi_errno_to_mid(err);
 
 			return 0;
 		}
@@ -647,7 +647,7 @@ int nsos_adapt_getsockopt(int fd, int nsos_mid_level, int nsos_mid_optname,
 
 			ret = getsockopt(fd, SOL_SOCKET, SO_TYPE, &type, &optlen);
 			if (ret < 0) {
-				return -errno_to_nsos_mid(errno);
+				return -nsi_errno_to_mid(errno);
 			}
 
 			err = socket_type_to_nsos_mid(type, nsos_mid_optval);
@@ -665,7 +665,7 @@ int nsos_adapt_getsockopt(int fd, int nsos_mid_level, int nsos_mid_optname,
 
 			ret = getsockopt(fd, SOL_SOCKET, SO_PROTOCOL, &proto, &optlen);
 			if (ret < 0) {
-				return -errno_to_nsos_mid(errno);
+				return -nsi_errno_to_mid(errno);
 			}
 
 			err = socket_proto_to_nsos_mid(proto, nsos_mid_optval);
@@ -683,7 +683,7 @@ int nsos_adapt_getsockopt(int fd, int nsos_mid_level, int nsos_mid_optname,
 
 			ret = getsockopt(fd, SOL_SOCKET, SO_DOMAIN, &family, &optlen);
 			if (ret < 0) {
-				return -errno_to_nsos_mid(errno);
+				return -nsi_errno_to_mid(errno);
 			}
 
 			err = socket_family_to_nsos_mid(family, nsos_mid_optval);
@@ -740,7 +740,7 @@ int nsos_adapt_getsockopt(int fd, int nsos_mid_level, int nsos_mid_optname,
 		break;
 	}
 
-	return -NSOS_MID_EOPNOTSUPP;
+	return -NSI_ERRNO_MID_EOPNOTSUPP;
 }
 
 static int nsos_adapt_setsockopt_int(int fd, int level, int optname,
@@ -750,7 +750,7 @@ static int nsos_adapt_setsockopt_int(int fd, int level, int optname,
 
 	ret = setsockopt(fd, level, optname, optval, optlen);
 	if (ret < 0) {
-		return -errno_to_nsos_mid(errno);
+		return -nsi_errno_to_mid(errno);
 	}
 
 	return 0;
@@ -777,7 +777,7 @@ int nsos_adapt_setsockopt(int fd, int nsos_mid_level, int nsos_mid_optname,
 			ret = setsockopt(fd, SOL_SOCKET, SO_RCVTIMEO,
 					 &tv, sizeof(tv));
 			if (ret < 0) {
-				return -errno_to_nsos_mid(errno);
+				return -nsi_errno_to_mid(errno);
 			}
 
 			return 0;
@@ -793,7 +793,7 @@ int nsos_adapt_setsockopt(int fd, int nsos_mid_level, int nsos_mid_optname,
 			ret = setsockopt(fd, SOL_SOCKET, SO_SNDTIMEO,
 					 &tv, sizeof(tv));
 			if (ret < 0) {
-				return -errno_to_nsos_mid(errno);
+				return -nsi_errno_to_mid(errno);
 			}
 
 			return 0;
@@ -845,7 +845,7 @@ int nsos_adapt_setsockopt(int fd, int nsos_mid_level, int nsos_mid_optname,
 		break;
 	}
 
-	return -NSOS_MID_EOPNOTSUPP;
+	return -NSI_ERRNO_MID_EOPNOTSUPP;
 }
 
 #define MAP_POLL_EPOLL(_event_from, _event_to)	\
@@ -958,7 +958,7 @@ static int addrinfo_to_nsos_mid(struct addrinfo *res,
 
 	nsos_res_wraps = calloc(n_res, sizeof(*nsos_res_wraps));
 	if (!nsos_res_wraps) {
-		return -NSOS_MID_ENOMEM;
+		return -NSI_ERRNO_MID_ENOMEM;
 	}
 
 	for (struct addrinfo *res_p = res; res_p; res_p = res_p->ai_next, idx_res++) {
@@ -1092,7 +1092,7 @@ int nsos_adapt_fcntl_setfl(int fd, int flags)
 
 	ret = fcntl(fd, F_SETFL, fl_from_nsos_mid(flags));
 	if (ret < 0) {
-		return -errno_to_nsos_mid(errno);
+		return -nsi_errno_to_mid(errno);
 	}
 
 	return 0;
@@ -1104,7 +1104,7 @@ int nsos_adapt_fionread(int fd, int *avail)
 
 	ret = ioctl(fd, FIONREAD, avail);
 	if (ret < 0) {
-		return -errno_to_nsos_mid(errno);
+		return -nsi_errno_to_mid(errno);
 	}
 
 	return 0;
@@ -1116,7 +1116,7 @@ int nsos_adapt_dup(int oldfd)
 
 	ret = dup(oldfd);
 	if (ret < 0) {
-		return -errno_to_nsos_mid(errno);
+		return -nsi_errno_to_mid(errno);
 	}
 
 	return ret;
diff --git a/drivers/net/nsos_errno.c b/drivers/net/nsos_errno.c
deleted file mode 100644
index 417c1af4f06..00000000000
--- a/drivers/net/nsos_errno.c
+++ /dev/null
@@ -1,125 +0,0 @@
-/**
- * Copyright (c) 2023-2024 Marcin Niestroj
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "nsos_errno.h"
-
-#ifndef ARRAY_SIZE
-#define ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0]))
-#endif
-
-struct nsos_mid_errno_map {
-	/** Zephyr/host error code */
-	int err;
-	/** NSOS middleground error code */
-	int mid_err;
-};
-
-#define ERR(_name)				\
-	{ _name, NSOS_MID_ ## _name }
-
-static const struct nsos_mid_errno_map map[] = {
-	ERR(EPERM),
-	ERR(ENOENT),
-	ERR(ESRCH),
-	ERR(EINTR),
-	ERR(EIO),
-	ERR(ENXIO),
-	ERR(E2BIG),
-	ERR(ENOEXEC),
-	ERR(EBADF),
-	ERR(ECHILD),
-	ERR(EAGAIN),
-	ERR(ENOMEM),
-	ERR(EACCES),
-	ERR(EFAULT),
-	ERR(ENOTBLK),
-	ERR(EBUSY),
-	ERR(EEXIST),
-	ERR(EXDEV),
-	ERR(ENODEV),
-	ERR(ENOTDIR),
-	ERR(EISDIR),
-	ERR(EINVAL),
-	ERR(ENFILE),
-	ERR(EMFILE),
-	ERR(ENOTTY),
-	ERR(ETXTBSY),
-	ERR(EFBIG),
-	ERR(ENOSPC),
-	ERR(ESPIPE),
-	ERR(EROFS),
-	ERR(EMLINK),
-	ERR(EPIPE),
-	ERR(EDOM),
-	ERR(ERANGE),
-	ERR(ENOMSG),
-	ERR(EDEADLK),
-	ERR(ENOLCK),
-	ERR(ENOSTR),
-	ERR(ENODATA),
-	ERR(ETIME),
-	ERR(ENOSR),
-	ERR(EPROTO),
-	ERR(EBADMSG),
-	ERR(ENOSYS),
-	ERR(ENOTEMPTY),
-	ERR(ENAMETOOLONG),
-	ERR(ELOOP),
-	ERR(EOPNOTSUPP),
-	ERR(EPFNOSUPPORT),
-	ERR(ECONNRESET),
-	ERR(ENOBUFS),
-	ERR(EAFNOSUPPORT),
-	ERR(EPROTOTYPE),
-	ERR(ENOTSOCK),
-	ERR(ENOPROTOOPT),
-	ERR(ESHUTDOWN),
-	ERR(ECONNREFUSED),
-	ERR(EADDRINUSE),
-	ERR(ECONNABORTED),
-	ERR(ENETUNREACH),
-	ERR(ENETDOWN),
-	ERR(ETIMEDOUT),
-	ERR(EHOSTDOWN),
-	ERR(EHOSTUNREACH),
-	ERR(EINPROGRESS),
-	ERR(EALREADY),
-	ERR(EDESTADDRREQ),
-	ERR(EMSGSIZE),
-	ERR(EPROTONOSUPPORT),
-	ERR(ESOCKTNOSUPPORT),
-	ERR(EADDRNOTAVAIL),
-	ERR(ENETRESET),
-	ERR(EISCONN),
-	ERR(ENOTCONN),
-	ERR(ETOOMANYREFS),
-	ERR(ENOTSUP),
-	ERR(EILSEQ),
-	ERR(EOVERFLOW),
-	ERR(ECANCELED),
-};
-
-int errno_to_nsos_mid(int err)
-{
-	for (int i = 0; i < ARRAY_SIZE(map); i++) {
-		if (map[i].err == err) {
-			return map[i].mid_err;
-		}
-	}
-
-	return err;
-}
-
-int errno_from_nsos_mid(int err)
-{
-	for (int i = 0; i < ARRAY_SIZE(map); i++) {
-		if (map[i].mid_err == err) {
-			return map[i].err;
-		}
-	}
-
-	return err;
-}
diff --git a/drivers/net/nsos_errno.h b/drivers/net/nsos_errno.h
deleted file mode 100644
index 8e9b6214671..00000000000
--- a/drivers/net/nsos_errno.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/**
- * Copyright (c) 2023-2024 Marcin Niestroj
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef __DRIVERS_NET_NSOS_ERRNO_H__
-#define __DRIVERS_NET_NSOS_ERRNO_H__
-
-#include <errno.h>
-
-#define NSOS_MID_EPERM 1         /**< Not owner */
-#define NSOS_MID_ENOENT 2        /**< No such file or directory */
-#define NSOS_MID_ESRCH 3         /**< No such context */
-#define NSOS_MID_EINTR 4         /**< Interrupted system call */
-#define NSOS_MID_EIO 5           /**< I/O error */
-#define NSOS_MID_ENXIO 6         /**< No such device or address */
-#define NSOS_MID_E2BIG 7         /**< Arg list too long */
-#define NSOS_MID_ENOEXEC 8       /**< Exec format error */
-#define NSOS_MID_EBADF 9         /**< Bad file number */
-#define NSOS_MID_ECHILD 10       /**< No children */
-#define NSOS_MID_EAGAIN 11       /**< No more contexts */
-#define NSOS_MID_ENOMEM 12       /**< Not enough core */
-#define NSOS_MID_EACCES 13       /**< Permission denied */
-#define NSOS_MID_EFAULT 14       /**< Bad address */
-#define NSOS_MID_ENOTBLK 15      /**< Block device required */
-#define NSOS_MID_EBUSY 16        /**< Mount device busy */
-#define NSOS_MID_EEXIST 17       /**< File exists */
-#define NSOS_MID_EXDEV 18        /**< Cross-device link */
-#define NSOS_MID_ENODEV 19       /**< No such device */
-#define NSOS_MID_ENOTDIR 20      /**< Not a directory */
-#define NSOS_MID_EISDIR 21       /**< Is a directory */
-#define NSOS_MID_EINVAL 22       /**< Invalid argument */
-#define NSOS_MID_ENFILE 23       /**< File table overflow */
-#define NSOS_MID_EMFILE 24       /**< Too many open files */
-#define NSOS_MID_ENOTTY 25       /**< Not a typewriter */
-#define NSOS_MID_ETXTBSY 26      /**< Text file busy */
-#define NSOS_MID_EFBIG 27        /**< File too large */
-#define NSOS_MID_ENOSPC 28       /**< No space left on device */
-#define NSOS_MID_ESPIPE 29       /**< Illegal seek */
-#define NSOS_MID_EROFS 30        /**< Read-only file system */
-#define NSOS_MID_EMLINK 31       /**< Too many links */
-#define NSOS_MID_EPIPE 32        /**< Broken pipe */
-#define NSOS_MID_EDOM 33         /**< Argument too large */
-#define NSOS_MID_ERANGE 34       /**< Result too large */
-#define NSOS_MID_ENOMSG 35       /**< Unexpected message type */
-#define NSOS_MID_EDEADLK 45      /**< Resource deadlock avoided */
-#define NSOS_MID_ENOLCK 46       /**< No locks available */
-#define NSOS_MID_ENOSTR 60       /**< STREAMS device required */
-#define NSOS_MID_ENODATA 61      /**< Missing expected message data */
-#define NSOS_MID_ETIME 62        /**< STREAMS timeout occurred */
-#define NSOS_MID_ENOSR 63        /**< Insufficient memory */
-#define NSOS_MID_EPROTO 71       /**< Generic STREAMS error */
-#define NSOS_MID_EBADMSG 77      /**< Invalid STREAMS message */
-#define NSOS_MID_ENOSYS 88       /**< Function not implemented */
-#define NSOS_MID_ENOTEMPTY 90    /**< Directory not empty */
-#define NSOS_MID_ENAMETOOLONG 91 /**< File name too long */
-#define NSOS_MID_ELOOP 92        /**< Too many levels of symbolic links */
-#define NSOS_MID_EOPNOTSUPP 95   /**< Operation not supported on socket */
-#define NSOS_MID_EPFNOSUPPORT 96 /**< Protocol family not supported */
-#define NSOS_MID_ECONNRESET 104   /**< Connection reset by peer */
-#define NSOS_MID_ENOBUFS 105      /**< No buffer space available */
-#define NSOS_MID_EAFNOSUPPORT 106 /**< Addr family not supported */
-#define NSOS_MID_EPROTOTYPE 107   /**< Protocol wrong type for socket */
-#define NSOS_MID_ENOTSOCK 108     /**< Socket operation on non-socket */
-#define NSOS_MID_ENOPROTOOPT 109  /**< Protocol not available */
-#define NSOS_MID_ESHUTDOWN 110    /**< Can't send after socket shutdown */
-#define NSOS_MID_ECONNREFUSED 111 /**< Connection refused */
-#define NSOS_MID_EADDRINUSE 112   /**< Address already in use */
-#define NSOS_MID_ECONNABORTED 113 /**< Software caused connection abort */
-#define NSOS_MID_ENETUNREACH 114  /**< Network is unreachable */
-#define NSOS_MID_ENETDOWN 115     /**< Network is down */
-#define NSOS_MID_ETIMEDOUT 116    /**< Connection timed out */
-#define NSOS_MID_EHOSTDOWN 117    /**< Host is down */
-#define NSOS_MID_EHOSTUNREACH 118 /**< No route to host */
-#define NSOS_MID_EINPROGRESS 119  /**< Operation now in progress */
-#define NSOS_MID_EALREADY 120     /**< Operation already in progress */
-#define NSOS_MID_EDESTADDRREQ 121 /**< Destination address required */
-#define NSOS_MID_EMSGSIZE 122        /**< Message size */
-#define NSOS_MID_EPROTONOSUPPORT 123 /**< Protocol not supported */
-#define NSOS_MID_ESOCKTNOSUPPORT 124 /**< Socket type not supported */
-#define NSOS_MID_EADDRNOTAVAIL 125   /**< Can't assign requested address */
-#define NSOS_MID_ENETRESET 126       /**< Network dropped connection on reset */
-#define NSOS_MID_EISCONN 127         /**< Socket is already connected */
-#define NSOS_MID_ENOTCONN 128        /**< Socket is not connected */
-#define NSOS_MID_ETOOMANYREFS 129    /**< Too many references: can't splice */
-#define NSOS_MID_ENOTSUP 134         /**< Unsupported value */
-#define NSOS_MID_EILSEQ 138          /**< Illegal byte sequence */
-#define NSOS_MID_EOVERFLOW 139       /**< Value overflow */
-#define NSOS_MID_ECANCELED 140       /**< Operation canceled */
-
-int errno_to_nsos_mid(int err);
-int errno_from_nsos_mid(int err);
-
-#endif /* __DRIVERS_NET_NSOS_ERRNO_H__ */
diff --git a/drivers/net/nsos_fcntl.c b/drivers/net/nsos_fcntl.c
index ab4d22ce51a..ad6a61285c9 100644
--- a/drivers/net/nsos_fcntl.c
+++ b/drivers/net/nsos_fcntl.c
@@ -25,7 +25,7 @@
 #include <fcntl.h>
 #endif
 
-#include "nsos_errno.h"
+#include "nsi_errno.h"
 #include "nsos_fcntl.h"
 
 #include <stdbool.h>
@@ -51,7 +51,7 @@ static int fl_to_nsos_mid_(int flags, bool strict)
 #undef TO_NSOS_MID
 
 	if (strict && flags != 0) {
-		return -NSOS_MID_EINVAL;
+		return -NSI_ERRNO_MID_EINVAL;
 	}
 
 	return flags_mid;
diff --git a/drivers/net/nsos_sockets.c b/drivers/net/nsos_sockets.c
index 7aa4e3cb924..a4a29605ef0 100644
--- a/drivers/net/nsos_sockets.c
+++ b/drivers/net/nsos_sockets.c
@@ -28,7 +28,7 @@ LOG_MODULE_REGISTER(nsos_sockets);
 
 #include "sockets_internal.h"
 #include "nsos.h"
-#include "nsos_errno.h"
+#include "nsi_errno.h"
 #include "nsos_fcntl.h"
 #include "nsos_netdb.h"
 #include "nsos_socket.h"
@@ -79,7 +79,7 @@ static int socket_family_to_nsos_mid(int family, int *family_mid)
 		*family_mid = NSOS_MID_AF_PACKET;
 		break;
 	default:
-		return -NSOS_MID_EAFNOSUPPORT;
+		return -NSI_ERRNO_MID_EAFNOSUPPORT;
 	}
 
 	return 0;
@@ -116,7 +116,7 @@ static int socket_proto_to_nsos_mid(int proto, int *proto_mid)
 		*proto_mid = NSOS_MID_IPPROTO_ETH_P_ALL;
 		break;
 	default:
-		return -NSOS_MID_EPROTONOSUPPORT;
+		return -NSI_ERRNO_MID_EPROTONOSUPPORT;
 	}
 
 	return 0;
@@ -135,7 +135,7 @@ static int socket_type_to_nsos_mid(int type, int *type_mid)
 		*type_mid = NSOS_MID_SOCK_RAW;
 		break;
 	default:
-		return -NSOS_MID_ESOCKTNOSUPPORT;
+		return -NSI_ERRNO_MID_ESOCKTNOSUPPORT;
 	}
 
 	return 0;
@@ -155,7 +155,7 @@ static int socket_flags_to_nsos_mid(int flags)
 				 &flags_mid, NSOS_MID_MSG_WAITALL);
 
 	if (flags != 0) {
-		return -NSOS_MID_EINVAL;
+		return -NSI_ERRNO_MID_EINVAL;
 	}
 
 	return flags_mid;
@@ -174,19 +174,19 @@ static int nsos_socket_create(int family, int type, int proto)
 
 	err = socket_family_to_nsos_mid(family, &family_mid);
 	if (err) {
-		errno = errno_from_nsos_mid(-err);
+		errno = nsi_errno_from_mid(-err);
 		return -1;
 	}
 
 	err = socket_type_to_nsos_mid(type, &type_mid);
 	if (err) {
-		errno = errno_from_nsos_mid(-err);
+		errno = nsi_errno_from_mid(-err);
 		return -1;
 	}
 
 	err = socket_proto_to_nsos_mid(proto, &proto_mid);
 	if (err) {
-		errno = errno_from_nsos_mid(-err);
+		errno = nsi_errno_from_mid(-err);
 		return -1;
 	}
 
@@ -207,7 +207,7 @@ static int nsos_socket_create(int family, int type, int proto)
 
 	sock->poll.mid.fd = nsos_adapt_socket(family_mid, type_mid, proto_mid);
 	if (sock->poll.mid.fd < 0) {
-		errno = errno_from_nsos_mid(-sock->poll.mid.fd);
+		errno = nsi_errno_from_mid(-sock->poll.mid.fd);
 		goto free_sock;
 	}
 
@@ -226,7 +226,7 @@ static int nsos_socket_create(int family, int type, int proto)
 
 static int nsos_adapt_get_zephyr_errno(void)
 {
-	return errno_from_nsos_mid(nsos_adapt_get_errno());
+	return nsi_errno_from_mid(nsos_adapt_get_errno());
 }
 
 static ssize_t nsos_read(void *obj, void *buf, size_t sz)
@@ -395,12 +395,12 @@ static int nsos_ioctl(void *obj, unsigned int request, va_list args)
 
 		ret = fl_to_nsos_mid_strict(flags);
 		if (ret < 0) {
-			return -errno_from_nsos_mid(-ret);
+			return -nsi_errno_from_mid(-ret);
 		}
 
 		ret = nsos_adapt_fcntl_setfl(sock->poll.mid.fd, flags);
 
-		return -errno_from_nsos_mid(-ret);
+		return -nsi_errno_from_mid(-ret);
 	}
 
 	case ZFD_IOCTL_FIONREAD: {
@@ -409,7 +409,7 @@ static int nsos_ioctl(void *obj, unsigned int request, va_list args)
 
 		ret = nsos_adapt_fionread(sock->poll.mid.fd, avail);
 
-		return -errno_from_nsos_mid(-ret);
+		return -nsi_errno_from_mid(-ret);
 	}
 	}
 
@@ -434,7 +434,7 @@ static int sockaddr_to_nsos_mid(const struct sockaddr *addr, socklen_t addrlen,
 			(struct nsos_mid_sockaddr_in *)*addr_mid;
 
 		if (addrlen < sizeof(*addr_in)) {
-			return -NSOS_MID_EINVAL;
+			return -NSI_ERRNO_MID_EINVAL;
 		}
 
 		addr_in_mid->sin_family = NSOS_MID_AF_INET;
@@ -452,7 +452,7 @@ static int sockaddr_to_nsos_mid(const struct sockaddr *addr, socklen_t addrlen,
 			(struct nsos_mid_sockaddr_in6 *)*addr_mid;
 
 		if (addrlen < sizeof(*addr_in)) {
-			return -NSOS_MID_EINVAL;
+			return -NSI_ERRNO_MID_EINVAL;
 		}
 
 		addr_in_mid->sin6_family = NSOS_MID_AF_INET6;
@@ -472,7 +472,7 @@ static int sockaddr_to_nsos_mid(const struct sockaddr *addr, socklen_t addrlen,
 			(struct nsos_mid_sockaddr_un *)*addr_mid;
 
 		if (addrlen < sizeof(*addr_un)) {
-			return -NSOS_MID_EINVAL;
+			return -NSI_ERRNO_MID_EINVAL;
 		}
 
 		addr_un_mid->sun_family = NSOS_MID_AF_UNIX;
@@ -490,7 +490,7 @@ static int sockaddr_to_nsos_mid(const struct sockaddr *addr, socklen_t addrlen,
 			(struct nsos_mid_sockaddr_ll *)*addr_mid;
 
 		if (addrlen < sizeof(*addr_ll)) {
-			return -NSOS_MID_EINVAL;
+			return -NSI_ERRNO_MID_EINVAL;
 		}
 
 		addr_ll_mid->sll_family = NSOS_MID_AF_UNIX;
@@ -508,7 +508,7 @@ static int sockaddr_to_nsos_mid(const struct sockaddr *addr, socklen_t addrlen,
 	}
 	}
 
-	return -NSOS_MID_EINVAL;
+	return -NSI_ERRNO_MID_EINVAL;
 }
 
 static int sockaddr_from_nsos_mid(struct sockaddr *addr, socklen_t *addrlen,
@@ -551,7 +551,7 @@ static int sockaddr_from_nsos_mid(struct sockaddr *addr, socklen_t *addrlen,
 	}
 	}
 
-	return -NSOS_MID_EINVAL;
+	return -NSI_ERRNO_MID_EINVAL;
 }
 
 static int nsos_wait_for_poll(struct nsos_socket *sock, int events,
@@ -598,7 +598,7 @@ static int nsos_wait_for_poll(struct nsos_socket *sock, int events,
 
 return_ret:
 	if (ret < 0) {
-		return -errno_to_nsos_mid(-ret);
+		return -nsi_errno_to_mid(-ret);
 	}
 
 	return 0;
@@ -641,7 +641,7 @@ static int nsos_bind(void *obj, const struct sockaddr *addr, socklen_t addrlen)
 
 return_ret:
 	if (ret < 0) {
-		errno = errno_from_nsos_mid(-ret);
+		errno = nsi_errno_from_mid(-ret);
 		return -1;
 	}
 
@@ -662,7 +662,7 @@ static int nsos_connect_blocking(struct nsos_socket *sock,
 	}
 
 	ret = nsos_adapt_connect(sock->poll.mid.fd, addr_mid, addrlen_mid);
-	if (ret == -NSOS_MID_EINPROGRESS) {
+	if (ret == -NSI_ERRNO_MID_EINPROGRESS) {
 		int so_err;
 		size_t so_err_len = sizeof(so_err);
 
@@ -677,7 +677,7 @@ static int nsos_connect_blocking(struct nsos_socket *sock,
 			goto clear_nonblock;
 		}
 
-		ret = so_err;
+		ret = -nsi_errno_to_mid(so_err);
 	}
 
 clear_nonblock:
@@ -713,7 +713,7 @@ static int nsos_connect(void *obj, const struct sockaddr *addr, socklen_t addrle
 
 return_ret:
 	if (ret < 0) {
-		errno = errno_from_nsos_mid(-ret);
+		errno = nsi_errno_from_mid(-ret);
 		return -1;
 	}
 
@@ -727,7 +727,7 @@ static int nsos_listen(void *obj, int backlog)
 
 	ret = nsos_adapt_listen(sock->poll.mid.fd, backlog);
 	if (ret < 0) {
-		errno = errno_from_nsos_mid(-ret);
+		errno = nsi_errno_from_mid(-ret);
 		return -1;
 	}
 
@@ -765,13 +765,13 @@ static int nsos_accept(void *obj, struct sockaddr *addr, socklen_t *addrlen)
 
 	zephyr_fd = zvfs_reserve_fd();
 	if (zephyr_fd < 0) {
-		ret = -errno_to_nsos_mid(-zephyr_fd);
+		ret = -nsi_errno_to_mid(-zephyr_fd);
 		goto close_adapt_fd;
 	}
 
 	conn_sock = k_malloc(sizeof(*conn_sock));
 	if (!conn_sock) {
-		ret = -NSOS_MID_ENOMEM;
+		ret = -NSI_ERRNO_MID_ENOMEM;
 		goto free_zephyr_fd;
 	}
 
@@ -790,7 +790,7 @@ static int nsos_accept(void *obj, struct sockaddr *addr, socklen_t *addrlen)
 	nsi_host_close(adapt_fd);
 
 return_ret:
-	errno = errno_from_nsos_mid(-ret);
+	errno = nsi_errno_from_mid(-ret);
 	return -1;
 }
 
@@ -826,7 +826,7 @@ static ssize_t nsos_sendto(void *obj, const void *buf, size_t len, int flags,
 
 return_ret:
 	if (ret < 0) {
-		errno = errno_from_nsos_mid(-ret);
+		errno = nsi_errno_from_mid(-ret);
 		return -1;
 	}
 
@@ -858,7 +858,7 @@ static ssize_t nsos_sendmsg(void *obj, const struct msghdr *msg, int flags)
 
 	msg_iov = k_calloc(msg->msg_iovlen, sizeof(*msg_iov));
 	if (!msg_iov) {
-		ret = -NSOS_MID_ENOMEM;
+		ret = -NSI_ERRNO_MID_ENOMEM;
 		goto return_ret;
 	}
 
@@ -887,7 +887,7 @@ static ssize_t nsos_sendmsg(void *obj, const struct msghdr *msg, int flags)
 
 return_ret:
 	if (ret < 0) {
-		errno = errno_from_nsos_mid(-ret);
+		errno = nsi_errno_from_mid(-ret);
 		return -1;
 	}
 
@@ -926,7 +926,7 @@ static ssize_t nsos_recvfrom(void *obj, void *buf, size_t len, int flags,
 
 return_ret:
 	if (ret < 0) {
-		errno = errno_from_nsos_mid(-ret);
+		errno = nsi_errno_from_mid(-ret);
 		return -1;
 	}
 
@@ -952,7 +952,7 @@ static int socket_type_from_nsos_mid(int type_mid, int *type)
 		*type = SOCK_RAW;
 		break;
 	default:
-		return -NSOS_MID_ESOCKTNOSUPPORT;
+		return -NSI_ERRNO_MID_ESOCKTNOSUPPORT;
 	}
 
 	return 0;
@@ -989,7 +989,7 @@ static int socket_proto_from_nsos_mid(int proto_mid, int *proto)
 		*proto = htons(IPPROTO_ETH_P_ALL);
 		break;
 	default:
-		return -NSOS_MID_EPROTONOSUPPORT;
+		return -NSI_ERRNO_MID_EPROTONOSUPPORT;
 	}
 
 	return 0;
@@ -1014,7 +1014,7 @@ static int socket_family_from_nsos_mid(int family_mid, int *family)
 		*family = AF_PACKET;
 		break;
 	default:
-		return -NSOS_MID_EAFNOSUPPORT;
+		return -NSI_ERRNO_MID_EAFNOSUPPORT;
 	}
 
 	return 0;
@@ -1034,7 +1034,7 @@ static int nsos_getsockopt_int(struct nsos_socket *sock, int nsos_mid_level, int
 	err = nsos_adapt_getsockopt(sock->poll.mid.fd, NSOS_MID_SOL_SOCKET,
 				    NSOS_MID_SO_KEEPALIVE, optval, &nsos_mid_optlen);
 	if (err) {
-		errno = errno_from_nsos_mid(-err);
+		errno = nsi_errno_from_mid(-err);
 		return -1;
 	}
 
@@ -1063,11 +1063,11 @@ static int nsos_getsockopt(void *obj, int level, int optname,
 			err = nsos_adapt_getsockopt(sock->poll.mid.fd, NSOS_MID_SOL_SOCKET,
 						    NSOS_MID_SO_ERROR, &nsos_mid_err, NULL);
 			if (err) {
-				errno = errno_from_nsos_mid(-err);
+				errno = nsi_errno_from_mid(-err);
 				return -1;
 			}
 
-			*(int *)optval = errno_from_nsos_mid(nsos_mid_err);
+			*(int *)optval = nsi_errno_from_mid(nsos_mid_err);
 
 			return 0;
 		}
@@ -1083,13 +1083,13 @@ static int nsos_getsockopt(void *obj, int level, int optname,
 			err = nsos_adapt_getsockopt(sock->poll.mid.fd, NSOS_MID_SOL_SOCKET,
 						    NSOS_MID_SO_TYPE, &nsos_mid_type, NULL);
 			if (err) {
-				errno = errno_from_nsos_mid(-err);
+				errno = nsi_errno_from_mid(-err);
 				return -1;
 			}
 
 			err = socket_type_from_nsos_mid(nsos_mid_type, optval);
 			if (err) {
-				errno = errno_from_nsos_mid(-err);
+				errno = nsi_errno_from_mid(-err);
 				return -1;
 			}
 
@@ -1107,13 +1107,13 @@ static int nsos_getsockopt(void *obj, int level, int optname,
 			err = nsos_adapt_getsockopt(sock->poll.mid.fd, NSOS_MID_SOL_SOCKET,
 						    NSOS_MID_SO_PROTOCOL, &nsos_mid_proto, NULL);
 			if (err) {
-				errno = errno_from_nsos_mid(-err);
+				errno = nsi_errno_from_mid(-err);
 				return -1;
 			}
 
 			err = socket_proto_from_nsos_mid(nsos_mid_proto, optval);
 			if (err) {
-				errno = errno_from_nsos_mid(-err);
+				errno = nsi_errno_from_mid(-err);
 				return -1;
 			}
 
@@ -1131,13 +1131,13 @@ static int nsos_getsockopt(void *obj, int level, int optname,
 			err = nsos_adapt_getsockopt(sock->poll.mid.fd, NSOS_MID_SOL_SOCKET,
 						    NSOS_MID_SO_DOMAIN, &nsos_mid_family, NULL);
 			if (err) {
-				errno = errno_from_nsos_mid(-err);
+				errno = nsi_errno_from_mid(-err);
 				return -1;
 			}
 
 			err = socket_family_from_nsos_mid(nsos_mid_family, optval);
 			if (err) {
-				errno = errno_from_nsos_mid(-err);
+				errno = nsi_errno_from_mid(-err);
 				return -1;
 			}
 
@@ -1214,7 +1214,7 @@ static int nsos_setsockopt_int(struct nsos_socket *sock, int nsos_mid_level, int
 	err = nsos_adapt_setsockopt(sock->poll.mid.fd, nsos_mid_level, nsos_mid_optname,
 				    optval, optlen);
 	if (err) {
-		errno = errno_from_nsos_mid(-err);
+		errno = nsi_errno_from_mid(-err);
 		return -1;
 	}
 
@@ -1244,7 +1244,7 @@ static int nsos_setsockopt(void *obj, int level, int optname,
 						    NSOS_MID_SO_PRIORITY, &nsos_mid_priority,
 						    sizeof(nsos_mid_priority));
 			if (err) {
-				errno = errno_from_nsos_mid(-err);
+				errno = nsi_errno_from_mid(-err);
 				return -1;
 			}
 
@@ -1267,7 +1267,7 @@ static int nsos_setsockopt(void *obj, int level, int optname,
 						    NSOS_MID_SO_RCVTIMEO, &nsos_mid_tv,
 						    sizeof(nsos_mid_tv));
 			if (err) {
-				errno = errno_from_nsos_mid(-err);
+				errno = nsi_errno_from_mid(-err);
 				return -1;
 			}
 
@@ -1296,7 +1296,7 @@ static int nsos_setsockopt(void *obj, int level, int optname,
 						    NSOS_MID_SO_SNDTIMEO, &nsos_mid_tv,
 						    sizeof(nsos_mid_tv));
 			if (err) {
-				errno = errno_from_nsos_mid(-err);
+				errno = nsi_errno_from_mid(-err);
 				return -1;
 			}
 
@@ -1512,7 +1512,7 @@ static int nsos_getaddrinfo(const char *node, const char *service,
 				     &system_errno);
 	if (ret < 0) {
 		if (ret == NSOS_MID_EAI_SYSTEM) {
-			errno = errno_from_nsos_mid(system_errno);
+			errno = nsi_errno_from_mid(system_errno);
 		}
 
 		return eai_from_nsos_mid(ret);
diff --git a/drivers/net/ppp.c b/drivers/net/ppp.c
index 99d3eef881f..022e728e755 100644
--- a/drivers/net/ppp.c
+++ b/drivers/net/ppp.c
@@ -976,8 +976,7 @@ static int ppp_driver_init(const struct device *dev)
 
 static inline struct net_linkaddr *ppp_get_mac(struct ppp_driver_context *ppp)
 {
-	ppp->ll_addr.addr = ppp->mac_addr;
-	ppp->ll_addr.len = sizeof(ppp->mac_addr);
+	(void)net_linkaddr_set(&ppp->ll_addr, ppp->mac_addr, sizeof(ppp->mac_addr));
 
 	return &ppp->ll_addr;
 }
diff --git a/drivers/net/slip.c b/drivers/net/slip.c
index c9f9fd7bb62..cea09b9f570 100644
--- a/drivers/net/slip.c
+++ b/drivers/net/slip.c
@@ -366,8 +366,8 @@ int slip_init(const struct device *dev)
 
 static inline struct net_linkaddr *slip_get_mac(struct slip_context *slip)
 {
-	slip->ll_addr.addr = slip->mac_addr;
-	slip->ll_addr.len = sizeof(slip->mac_addr);
+	(void)net_linkaddr_set(&slip->ll_addr, slip->mac_addr,
+			       sizeof(slip->mac_addr));
 
 	return &slip->ll_addr;
 }
diff --git a/drivers/pcie/CMakeLists.txt b/drivers/pcie/CMakeLists.txt
index 351f355ffec..7840524a768 100644
--- a/drivers/pcie/CMakeLists.txt
+++ b/drivers/pcie/CMakeLists.txt
@@ -1,2 +1,3 @@
 add_subdirectory_ifdef(CONFIG_PCIE host)
 add_subdirectory_ifdef(CONFIG_PCIE_ENDPOINT endpoint)
+add_subdirectory_ifdef(CONFIG_PCIE_CONTROLLER controller)
diff --git a/drivers/pcie/Kconfig b/drivers/pcie/Kconfig
index 2651a84f6a6..23158897875 100644
--- a/drivers/pcie/Kconfig
+++ b/drivers/pcie/Kconfig
@@ -2,3 +2,4 @@
 
 source "drivers/pcie/host/Kconfig"
 source "drivers/pcie/endpoint/Kconfig"
+source "drivers/pcie/controller/Kconfig"
diff --git a/drivers/pcie/controller/CMakeLists.txt b/drivers/pcie/controller/CMakeLists.txt
new file mode 100644
index 00000000000..3a2ca4fddc8
--- /dev/null
+++ b/drivers/pcie/controller/CMakeLists.txt
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources_ifdef(CONFIG_PCIE_BRCMSTB pcie_brcmstb.c)
diff --git a/drivers/pcie/controller/Kconfig b/drivers/pcie/controller/Kconfig
new file mode 100644
index 00000000000..29804ce1cb4
--- /dev/null
+++ b/drivers/pcie/controller/Kconfig
@@ -0,0 +1,10 @@
+# PCIe controller configuration options
+
+# Copyright 2024 TSN Lab, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if PCIE_CONTROLLER
+
+source "drivers/pcie/controller/Kconfig.brcmstb"
+
+endif # PCIE_CONTROLLER
diff --git a/drivers/pcie/controller/Kconfig.brcmstb b/drivers/pcie/controller/Kconfig.brcmstb
new file mode 100644
index 00000000000..439e57e1ecd
--- /dev/null
+++ b/drivers/pcie/controller/Kconfig.brcmstb
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Junho Lee <junho@tsnlab.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config PCIE_BRCMSTB
+	bool "Broadcom Set-top box SoC PCIe Driver"
+	default y
+	depends on DT_HAS_BRCM_BRCMSTB_PCIE_ENABLED
+	help
+	  Enable Driver for Broadcom Set-top box SoC PCIe controllers.
diff --git a/drivers/pcie/controller/pcie_brcmstb.c b/drivers/pcie/controller/pcie_brcmstb.c
new file mode 100644
index 00000000000..68e66bc424f
--- /dev/null
+++ b/drivers/pcie/controller/pcie_brcmstb.c
@@ -0,0 +1,635 @@
+/*
+ * Copyright (c) 2024 Junho Lee <junho@tsnlab.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(pcie_brcmstb, LOG_LEVEL_ERR);
+
+#include <zephyr/arch/common/sys_bitops.h>
+#include <zephyr/arch/cpu.h>
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+#include <zephyr/math/ilog2.h>
+#include <zephyr/sys/device_mmio.h>
+
+#include <zephyr/drivers/pcie/pcie.h>
+#include <zephyr/drivers/pcie/controller.h>
+
+#define DT_DRV_COMPAT brcm_brcmstb_pcie
+
+#define PCIE_RC_PL_PHY_CTL_15                    0x184c
+#define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK 0xff
+
+#define PCIE_MISC_MISC_CTRL                       0x4008
+#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK    0x1000
+#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
+#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK   0x300000
+#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_LSB    20
+#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK        0xf8000000
+#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_LSB         27
+
+#define PCIE_MISC_RC_BAR_CONFIG_LO_SIZE_MASK 0x1f
+
+#define PCIE_MISC_RC_BAR1_CONFIG_LO           0x402c
+#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
+
+#define PCIE_MISC_RC_BAR2_CONFIG_LO           0x4034
+#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
+#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_LSB  0
+#define PCIE_MISC_RC_BAR2_CONFIG_HI           0x4038
+
+#define PCIE_MISC_RC_BAR3_CONFIG_LO           0x403c
+#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
+
+#define PCIE_MISC_RC_BAR4_CONFIG_LO 0x40d4
+#define PCIE_MISC_RC_BAR4_CONFIG_HI 0x40d8
+
+#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_ENABLE  0x1
+#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_LO_MASK 0xfffff000
+#define PCIE_MISC_UBUS_BAR_CONFIG_REMAP_HI_MASK 0xff
+
+#define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP                    0x40b4
+#define PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_ENABLE_MASK 0x1
+
+#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_LO 0x410c
+#define PCIE_MISC_UBUS_BAR4_CONFIG_REMAP_HI 0x4110
+
+#define PCIE_MISC_UBUS_CTRL                                 0x40a4
+#define PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK    0x2000
+#define PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK 0x80000
+
+#define PCIE_MISC_AXI_READ_ERROR_DATA     0x4170
+#define PCIE_MISC_UBUS_TIMEOUT            0x40a8
+#define PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT 0x405c
+
+#define PCIE_MISC_PCIE_CTRL                  0x4064
+#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
+
+#define PCIE_RC_CFG_PRIV1_ID_VAL3                 0x043c
+#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
+
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1                       0x0188
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_LSB  2
+#define PCIE_RC_CFG_VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN                0x0
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
+#define PCIE_MEM_WIN0_LO(win)            (PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win) * 8)
+#define PCIE_MEM_WIN0_HI(win)            (PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win) * 8)
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT            0x4070
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_LSB  20
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK  0xfff0
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_LSB   4
+
+#define PCIE_MEM_WIN0_BASE_LIMIT(win) (PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT + (win) * 4)
+
+/* Hamming weight of PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK */
+#define HIGH_ADDR_SHIFT 12
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI           0x4080
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_LSB  0
+
+#define PCIE_MEM_WIN0_BASE_HI(win) (PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI + (win) * 8)
+
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI            0x4084
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_LSB  0
+
+#define PCIE_MEM_WIN0_LIMIT_HI(win) (PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI + (win) * 8)
+
+#define PCIE_EXT_CFG_DATA  0x8000
+#define PCIE_EXT_CFG_INDEX 0x9000
+
+#define PCI_BASE_ADDRESS_0 0x10
+
+#define PCI_COMMAND        0x0004
+#define PCI_COMMAND_MEMORY 0x2
+#define PCI_COMMAND_MASTER 0x4
+
+#define PCI_EXP_LNKCAP     0x0c
+#define PCI_EXP_LNKCAP_SLS 0xf
+#define PCI_EXP_LNKCTL2    0x30
+
+#define BRCM_PCIE_CAP_REGS 0x00ac
+
+#define BCM2712_RC_BAR2_SIZE   0x400000
+#define BCM2712_RC_BAR2_OFFSET 0x0
+#define BCM2712_RC_BAR4_CPU    0x0
+#define BCM2712_RC_BAR4_SIZE   0x0
+#define BCM2712_RC_BAR4_PCI    0x0
+#define BCM2712_SCB0_SIZE      0x400000
+
+#define BCM2712_BURST_SIZE 0x1
+
+#define BCM2712_CLOCK_RATE 750000000ULL /* 750Mhz */
+
+#define BCM2712_UBUS_TIMEOUT_NS    250000000ULL /* 250ms */
+#define BCM2712_UBUS_TIMEOUT_TICKS (BCM2712_UBUS_TIMEOUT_NS * BCM2712_CLOCK_RATE / 1000000000ULL)
+
+#define BCM2712_RC_CONFIG_RETRY_TIMEOUT_NS 240000000ULL /* 240ms */
+#define BCM2712_RC_CONFIG_RETRY_TIMEOUT_TICKS                                                      \
+	(BCM2712_RC_CONFIG_RETRY_TIMEOUT_NS * BCM2712_CLOCK_RATE / 1000000000ULL)
+
+#define BCM2712_PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE 0x060400
+
+#define MDIO_DATA_DONE_MASK 0x80000000
+#define MDIO_CMD_WRITE      0x0
+#define MDIO_PORT0          0x0
+
+#define PCIE_RC_DL_MDIO_ADDR                0x1100
+#define PCIE_RC_DL_MDIO_WR_DATA             0x1104
+#define PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD 0x12 /* 18.52ns as ticks */
+
+#define SET_ADDR_OFFSET 0x1f
+
+#define DMA_RANGES_IDX 2
+
+#define PCIE_ECAM_BDF_SHIFT 12
+
+#define BAR_MAX 8
+
+#define SZ_1M 0x100000
+
+struct pcie_brcmstb_config {
+	const struct pcie_ctrl_config *common;
+	size_t regs_count;
+	struct {
+		uintptr_t addr;
+		size_t size;
+	} regs[BAR_MAX];
+};
+
+enum pcie_region_type {
+	PCIE_REGION_IO = 0,
+	PCIE_REGION_MEM,
+	PCIE_REGION_MEM64,
+	PCIE_REGION_MAX,
+};
+
+struct pcie_brcmstb_data {
+	uintptr_t cfg_phys_addr;
+	mm_reg_t cfg_addr;
+	size_t cfg_size;
+	struct {
+		uintptr_t phys_start;
+		uintptr_t bus_start;
+		size_t size;
+		size_t allocation_offset;
+	} regions[PCIE_REGION_MAX];
+	size_t bar_cnt;
+};
+
+static inline uint32_t lower_32_bits(uint64_t val)
+{
+	return val & 0xffffffff;
+}
+
+static inline uint32_t upper_32_bits(uint64_t val)
+{
+	return (val >> 32) & 0xffffffff;
+}
+
+static uint32_t encode_ibar_size(uint64_t size)
+{
+	uint32_t tmp;
+	uint32_t size_upper = (uint32_t)(size >> 32);
+
+	if (size_upper > 0) {
+		tmp = ilog2(size_upper) + 32;
+	} else {
+		tmp = ilog2(size);
+	}
+
+	if (tmp >= 12 && tmp <= 15) {
+		return (tmp - 12) + 0x1c;
+	} else if (tmp >= 16 && tmp <= 36) {
+		return tmp - 15;
+	}
+
+	return 0;
+}
+
+static mm_reg_t pcie_brcmstb_map_bus(const struct device *dev, pcie_bdf_t bdf, unsigned int reg)
+{
+	struct pcie_brcmstb_data *data = dev->data;
+
+	sys_write32(bdf << PCIE_ECAM_BDF_SHIFT, data->cfg_addr + PCIE_EXT_CFG_INDEX);
+	return data->cfg_addr + PCIE_EXT_CFG_DATA + reg * sizeof(uint32_t);
+}
+
+static uint32_t pcie_brcmstb_conf_read(const struct device *dev, pcie_bdf_t bdf, unsigned int reg)
+{
+	mm_reg_t conf_addr = pcie_brcmstb_map_bus(dev, bdf, reg);
+
+	if (!conf_addr) {
+		return 0xffffffff;
+	}
+
+	return sys_read32(conf_addr);
+}
+
+void pcie_brcmstb_conf_write(const struct device *dev, pcie_bdf_t bdf, unsigned int reg,
+			     uint32_t data)
+{
+	mm_reg_t conf_addr = pcie_brcmstb_map_bus(dev, bdf, reg);
+
+	if (!conf_addr) {
+		return;
+	}
+
+	sys_write32(data, conf_addr);
+}
+
+static inline enum pcie_region_type pcie_brcmstb_determine_region_type(const struct device *dev,
+								       bool mem, bool mem64)
+{
+	struct pcie_brcmstb_data *data = dev->data;
+
+	if (!mem) {
+		return PCIE_REGION_IO;
+	}
+
+	if ((data->regions[PCIE_REGION_MEM64].size > 0) &&
+	    (mem64 || data->regions[PCIE_REGION_MEM].size == 0)) {
+		return PCIE_REGION_MEM64;
+	}
+
+	return PCIE_REGION_MEM;
+}
+
+static bool pcie_brcmstb_region_allocate_type(const struct device *dev, pcie_bdf_t bdf,
+					      size_t bar_size, uintptr_t *bar_bus_addr,
+					      enum pcie_region_type type)
+{
+	const struct pcie_brcmstb_config *config = dev->config;
+	struct pcie_brcmstb_data *data = dev->data;
+	uintptr_t addr;
+
+	addr = (((data->regions[type].bus_start + config->regs[PCIE_BDF_TO_BUS(bdf) + 1].addr +
+		  data->regions[type].allocation_offset) -
+		 1) |
+		((bar_size)-1)) +
+	       1;
+
+	if (addr + bar_size > data->regions[type].bus_start + data->regions[type].size) {
+		return false;
+	}
+
+	*bar_bus_addr = addr;
+
+	return true;
+}
+
+static bool pcie_brcmstb_region_allocate(const struct device *dev, pcie_bdf_t bdf, bool mem,
+					 bool mem64, size_t bar_size, uintptr_t *bar_bus_addr)
+{
+	struct pcie_brcmstb_data *data = dev->data;
+	enum pcie_region_type type;
+
+	if (!mem && mem64) {
+		return false;
+	}
+
+	if (mem && data->regions[PCIE_REGION_MEM64].size == 0 &&
+	    data->regions[PCIE_REGION_MEM].size == 0) {
+		return false;
+	}
+
+	if (!mem && data->regions[PCIE_REGION_IO].size == 0) {
+		return false;
+	}
+
+	type = pcie_brcmstb_determine_region_type(dev, mem, mem64);
+
+	return pcie_brcmstb_region_allocate_type(dev, bdf, bar_size, bar_bus_addr, type);
+}
+
+static bool pcie_brcmstb_region_get_allocate_base(const struct device *dev, pcie_bdf_t bdf,
+						  bool mem, bool mem64, size_t align,
+						  uintptr_t *bar_base_addr)
+{
+	struct pcie_brcmstb_data *data = dev->data;
+	enum pcie_region_type type;
+
+	if (!mem && mem64) {
+		return false;
+	}
+
+	if (mem && data->regions[PCIE_REGION_MEM64].size == 0 &&
+	    data->regions[PCIE_REGION_MEM].size == 0) {
+		return false;
+	}
+
+	if (!mem && data->regions[PCIE_REGION_IO].size == 0) {
+		return false;
+	}
+
+	type = pcie_brcmstb_determine_region_type(dev, mem, mem64);
+
+	*bar_base_addr =
+		(((data->regions[type].bus_start + data->regions[type].allocation_offset) - 1) |
+		 ((align)-1)) +
+		1;
+
+	return true;
+}
+
+static bool pcie_brcmstb_region_translate(const struct device *dev, pcie_bdf_t bdf, bool mem,
+					  bool mem64, uintptr_t bar_bus_addr, uintptr_t *bar_addr)
+{
+	struct pcie_brcmstb_data *data = dev->data;
+	enum pcie_region_type type;
+
+	type = pcie_brcmstb_determine_region_type(dev, mem, mem64);
+
+	*bar_addr = data->regions[type].phys_start + (bar_bus_addr - data->regions[type].bus_start);
+
+	return true;
+}
+
+static DEVICE_API(pcie_ctrl, pcie_brcmstb_api) = {
+	.conf_read = pcie_brcmstb_conf_read,
+	.conf_write = pcie_brcmstb_conf_write,
+	.region_allocate = pcie_brcmstb_region_allocate,
+	.region_get_allocate_base = pcie_brcmstb_region_get_allocate_base,
+	.region_translate = pcie_brcmstb_region_translate,
+};
+
+static int pcie_brcmstb_parse_regions(const struct device *dev)
+{
+	const struct pcie_brcmstb_config *config = dev->config;
+	struct pcie_brcmstb_data *data = dev->data;
+	enum pcie_region_type type;
+	int i;
+
+	for (i = 0; i < DMA_RANGES_IDX; i++) {
+		switch ((config->common->ranges[i].flags >> 24) & 0x03) {
+		case 0x01:
+			type = PCIE_REGION_IO;
+			break;
+		case 0x02:
+			type = PCIE_REGION_MEM;
+			break;
+		case 0x03:
+			type = PCIE_REGION_MEM64;
+			break;
+		default:
+			continue;
+		}
+		data->regions[type].bus_start = config->common->ranges[i].pcie_bus_addr;
+		data->regions[type].phys_start = config->common->ranges[i].host_map_addr;
+		data->regions[type].size = config->common->ranges[i].map_length;
+	}
+
+	if (!data->regions[PCIE_REGION_IO].size && !data->regions[PCIE_REGION_MEM].size &&
+	    !data->regions[PCIE_REGION_MEM64].size) {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static mm_reg_t pcie_brcmstb_mdio_from_pkt(int port, int regad, int cmd)
+{
+	return (mm_reg_t)cmd << 20 | port << 16 | regad;
+}
+
+static void pcie_brcmstb_mdio_write(mm_reg_t base, uint8_t port, uint8_t regad, uint16_t wrdata)
+{
+	sys_write32(pcie_brcmstb_mdio_from_pkt(port, regad, MDIO_CMD_WRITE),
+		    base + PCIE_RC_DL_MDIO_ADDR);
+	sys_write32(MDIO_DATA_DONE_MASK | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
+}
+
+static void pcie_brcmstb_munge_pll(const struct device *dev)
+{
+	struct pcie_brcmstb_data *data = dev->data;
+	int i;
+
+	uint8_t regs[] = {0x16, 0x17, 0x18, 0x19, 0x1b, 0x1c, 0x1e};
+	uint16_t vals[] = {0x50b9, 0xbda1, 0x0094, 0x97b4, 0x5030, 0x5030, 0x0007};
+
+	pcie_brcmstb_mdio_write(data->cfg_addr, MDIO_PORT0, SET_ADDR_OFFSET, 0x1600);
+	for (i = 0; i < 7; i++) {
+		k_busy_wait(300);
+		pcie_brcmstb_mdio_write(data->cfg_addr, MDIO_PORT0, regs[i], vals[i]);
+	}
+}
+
+static void pcie_brcmstb_set_outbound_win(const struct device *dev, uint8_t win, uintptr_t cpu_addr,
+					  uintptr_t pcie_addr, size_t size)
+{
+	struct pcie_brcmstb_data *data = dev->data;
+	uint32_t cpu_addr_mb_high, limit_addr_mb_high;
+	uintptr_t cpu_addr_mb, limit_addr_mb;
+	uint32_t tmp, tmp2;
+
+	sys_write32(lower_32_bits(pcie_addr), data->cfg_addr + PCIE_MEM_WIN0_LO(win));
+	sys_write32(upper_32_bits(pcie_addr), data->cfg_addr + PCIE_MEM_WIN0_HI(win));
+
+	cpu_addr_mb = cpu_addr / SZ_1M;
+	limit_addr_mb = (cpu_addr + size - 1) / SZ_1M;
+
+	tmp = sys_read32(data->cfg_addr + PCIE_MEM_WIN0_BASE_LIMIT(win));
+	tmp &= ~PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK;
+	tmp &= ~PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK;
+	tmp2 = (cpu_addr_mb << PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_LSB);
+	tmp2 &= PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK;
+	tmp |= tmp2;
+	tmp2 = (limit_addr_mb << PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_LSB);
+	tmp2 &= PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK;
+	tmp |= tmp2;
+	sys_write32(tmp, data->cfg_addr + PCIE_MEM_WIN0_BASE_LIMIT(win));
+
+	cpu_addr_mb_high = cpu_addr_mb >> HIGH_ADDR_SHIFT;
+	tmp = sys_read32(data->cfg_addr + PCIE_MEM_WIN0_BASE_HI(win));
+	tmp &= ~PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK;
+	tmp |= (cpu_addr_mb_high << PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_LSB);
+	sys_write32(tmp, data->cfg_addr + PCIE_MEM_WIN0_BASE_HI(win));
+
+	limit_addr_mb_high = limit_addr_mb >> HIGH_ADDR_SHIFT;
+	tmp = sys_read32(data->cfg_addr + PCIE_MEM_WIN0_LIMIT_HI(win));
+	tmp &= ~PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK;
+	tmp |= (cpu_addr_mb_high << PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_LSB);
+	sys_write32(tmp, data->cfg_addr + PCIE_MEM_WIN0_LIMIT_HI(win));
+}
+
+static int pcie_brcmstb_setup(const struct device *dev)
+{
+	const struct pcie_brcmstb_config *config = dev->config;
+	struct pcie_brcmstb_data *data = dev->data;
+	uint32_t tmp;
+	uint16_t tmp16;
+
+	/* This block is for BCM2712 only */
+	pcie_brcmstb_munge_pll(dev);
+	tmp = sys_read32(data->cfg_addr + PCIE_RC_PL_PHY_CTL_15);
+	tmp &= ~PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD_MASK;
+	tmp |= PCIE_RC_PL_PHY_CTL_15_PM_CLK_PERIOD;
+	sys_write32(tmp, data->cfg_addr + PCIE_RC_PL_PHY_CTL_15);
+
+	tmp = sys_read32(data->cfg_addr + PCIE_MISC_MISC_CTRL);
+	tmp |= PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK;
+	tmp |= PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK;
+	tmp &= ~PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK;
+	tmp |= (BCM2712_BURST_SIZE << PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_LSB);
+	sys_write32(tmp, data->cfg_addr + PCIE_MISC_MISC_CTRL);
+
+	uint64_t rc_bar2_offset = config->common->ranges[DMA_RANGES_IDX].host_map_addr -
+				  config->common->ranges[DMA_RANGES_IDX].pcie_bus_addr;
+	uint64_t rc_bar2_size = config->common->ranges[DMA_RANGES_IDX].map_length;
+
+	tmp = lower_32_bits(rc_bar2_offset);
+	tmp &= ~PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK;
+	tmp |= encode_ibar_size(rc_bar2_size) << PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_LSB;
+	sys_write32(tmp, data->cfg_addr + PCIE_MISC_RC_BAR2_CONFIG_LO);
+	sys_write32(upper_32_bits(rc_bar2_offset), data->cfg_addr + PCIE_MISC_RC_BAR2_CONFIG_HI);
+
+	tmp = sys_read32(data->cfg_addr + PCIE_MISC_UBUS_BAR2_CONFIG_REMAP);
+	tmp |= PCIE_MISC_UBUS_BAR2_CONFIG_REMAP_ACCESS_ENABLE_MASK;
+	sys_write32(tmp, data->cfg_addr + PCIE_MISC_UBUS_BAR2_CONFIG_REMAP);
+
+	/* Set SCB Size */
+	tmp = sys_read32(data->cfg_addr + PCIE_MISC_MISC_CTRL);
+	tmp &= ~PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK;
+	tmp |= (ilog2(config->common->ranges[DMA_RANGES_IDX].map_length) - 15)
+	       << PCIE_MISC_MISC_CTRL_SCB0_SIZE_LSB;
+	sys_write32(tmp, data->cfg_addr + PCIE_MISC_MISC_CTRL);
+
+	tmp = sys_read32(data->cfg_addr + PCIE_MISC_UBUS_CTRL);
+	tmp |= PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_ERR_DIS_MASK;
+	tmp |= PCIE_MISC_UBUS_CTRL_UBUS_PCIE_REPLY_DECERR_DIS_MASK;
+	sys_write32(tmp, data->cfg_addr + PCIE_MISC_UBUS_CTRL);
+	sys_write32(0xffffffff, data->cfg_addr + PCIE_MISC_AXI_READ_ERROR_DATA);
+
+	/* Set timeouts */
+	sys_write32(BCM2712_UBUS_TIMEOUT_TICKS, data->cfg_addr + PCIE_MISC_UBUS_TIMEOUT);
+	sys_write32(BCM2712_RC_CONFIG_RETRY_TIMEOUT_TICKS,
+		    data->cfg_addr + PCIE_MISC_RC_CONFIG_RETRY_TIMEOUT);
+
+	tmp = sys_read32(data->cfg_addr + PCIE_MISC_RC_BAR1_CONFIG_LO);
+	tmp &= ~PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK;
+	sys_write32(tmp, data->cfg_addr + PCIE_MISC_RC_BAR1_CONFIG_LO);
+
+	tmp = sys_read32(data->cfg_addr + PCIE_MISC_RC_BAR3_CONFIG_LO);
+	tmp &= ~PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK;
+	sys_write32(tmp, data->cfg_addr + PCIE_MISC_RC_BAR3_CONFIG_LO);
+
+	/* Set gen to 2 */
+	tmp16 = sys_read16(data->cfg_addr + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
+	tmp = sys_read32(data->cfg_addr + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
+	tmp &= ~PCI_EXP_LNKCAP_SLS;
+	tmp |= 0x2;
+	sys_write32(tmp, data->cfg_addr + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
+	tmp16 &= ~0xf;
+	tmp16 |= 0x2;
+	sys_write16(tmp16, data->cfg_addr + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
+
+	tmp = sys_read32(data->cfg_addr + PCIE_RC_CFG_PRIV1_ID_VAL3);
+	tmp &= ~PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK;
+	tmp |= BCM2712_PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE;
+	sys_write32(tmp, data->cfg_addr + PCIE_RC_CFG_PRIV1_ID_VAL3);
+
+	tmp = sys_read32(data->cfg_addr + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
+	tmp &= ~PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK;
+	tmp |= PCIE_RC_CFG_VENDOR_SPECIFIC_REG1_LITTLE_ENDIAN
+	       << PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_LSB;
+	sys_write32(tmp, data->cfg_addr + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
+
+	return 0;
+}
+
+static int pcie_brcmstb_init(const struct device *dev)
+{
+	const struct pcie_brcmstb_config *config = dev->config;
+	struct pcie_brcmstb_data *data = dev->data;
+	uint32_t tmp;
+	int ret;
+
+	if (config->common->ranges_count < DMA_RANGES_IDX) {
+		/* Workaround since macros for `dma-ranges` property is not available */
+		return -EINVAL;
+	}
+
+	ret = pcie_brcmstb_parse_regions(dev);
+	if (ret != 0) {
+		return ret;
+	}
+
+	data->cfg_phys_addr = config->common->cfg_addr;
+	data->cfg_size = config->common->cfg_size;
+
+	device_map(&data->cfg_addr, data->cfg_phys_addr, data->cfg_size, K_MEM_CACHE_NONE);
+
+	/* PCIe Setup */
+	pcie_brcmstb_setup(dev);
+
+	/* Assert PERST# */
+	tmp = sys_read32(data->cfg_addr + PCIE_MISC_PCIE_CTRL);
+	tmp |= PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK;
+	sys_write32(tmp, data->cfg_addr + PCIE_MISC_PCIE_CTRL);
+
+	k_busy_wait(500000);
+
+	/* Enable resources and bus-mastering */
+	tmp = sys_read32(data->cfg_addr + PCI_COMMAND);
+	tmp |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
+	sys_write32(tmp, data->cfg_addr + PCI_COMMAND);
+
+	for (int i = 0; i < DMA_RANGES_IDX; i++) {
+		pcie_brcmstb_set_outbound_win(dev, i, config->common->ranges[i].host_map_addr,
+					      config->common->ranges[i].pcie_bus_addr,
+					      config->common->ranges[i].map_length);
+	}
+
+	/* Assign BARs */
+	/* TODO: It might be possible to do this without extra <regs> property */
+	for (int i = 1; i < config->regs_count; i++) {
+		sys_write32(config->regs[i].addr, data->cfg_addr + PCIE_EXT_CFG_DATA +
+							  PCI_BASE_ADDRESS_0 + 0x4 * (i - 1));
+	}
+
+	/* Enable resources */
+	tmp = sys_read32(data->cfg_addr + PCIE_EXT_CFG_DATA + PCI_COMMAND);
+	tmp |= PCI_COMMAND_MEMORY;
+	sys_write32(tmp, data->cfg_addr + PCIE_EXT_CFG_DATA + PCI_COMMAND);
+	k_busy_wait(500000);
+
+	return 0;
+}
+
+#define PCIE_BRCMSTB_INIT(n)                                                                       \
+	static struct pcie_brcmstb_data pcie_brcmstb_data_##n = {};                                \
+                                                                                                   \
+	static const struct pcie_ctrl_config pcie_ctrl_cfg_##n = {                                 \
+		.cfg_addr = DT_INST_REG_ADDR(n),                                                   \
+		.cfg_size = DT_INST_REG_SIZE(n),                                                   \
+		.ranges_count = DT_NUM_RANGES(DT_DRV_INST(n)),                                     \
+		.ranges = {DT_FOREACH_RANGE(DT_DRV_INST(n), PCIE_RANGE_FORMAT)},                   \
+	};                                                                                         \
+                                                                                                   \
+	static const struct pcie_brcmstb_config pcie_brcmstb_cfg_##n = {                           \
+		.common = &pcie_ctrl_cfg_##n,                                                      \
+		.regs_count = DT_NUM_REGS(DT_DRV_INST(n)),                                         \
+		.regs =                                                                            \
+			{                                                                          \
+				{DT_REG_ADDR_BY_IDX(DT_DRV_INST(n), 0),                            \
+				 DT_REG_SIZE_BY_IDX(DT_DRV_INST(n), 0)},                           \
+				{DT_REG_ADDR_BY_IDX(DT_DRV_INST(n), 1),                            \
+				 DT_REG_SIZE_BY_IDX(DT_DRV_INST(n), 1)},                           \
+				{DT_REG_ADDR_BY_IDX(DT_DRV_INST(n), 2),                            \
+				 DT_REG_SIZE_BY_IDX(DT_DRV_INST(n), 2)},                           \
+			},                                                                         \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, pcie_brcmstb_init, NULL, &pcie_brcmstb_data_##n,                  \
+			      &pcie_brcmstb_cfg_##n, PRE_KERNEL_1, CONFIG_PCIE_INIT_PRIORITY,      \
+			      &pcie_brcmstb_api);
+
+DT_INST_FOREACH_STATUS_OKAY(PCIE_BRCMSTB_INIT)
diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt
index e56922d083e..60e1741f2b7 100644
--- a/drivers/pinctrl/CMakeLists.txt
+++ b/drivers/pinctrl/CMakeLists.txt
@@ -1,10 +1,15 @@
 # Copyright (c) 2021 Nordic Semiconductor ASA
+# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_library()
 zephyr_library_sources(common.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_TELINK_B91 pinctrl_b91.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_AMBIQ pinctrl_ambiq.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_ARM_MPS2 pinctrl_arm_mps2.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_ARM_MPS3 pinctrl_arm_mps3.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_ARM_V2M_BEETLE pinctrl_arm_v2m_beetle.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_BFLB pinctrl_bflb.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AF pinctrl_gd32_af.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_GD32_AFIO pinctrl_gd32_afio.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_ITE_IT8XXX2 pinctrl_ite_it8xxx2.c)
@@ -21,6 +26,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX pinctrl_imx.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_SIFIVE pinctrl_sifive.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_IOCON pinctrl_lpc_iocon.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_CC13XX_CC26XX pinctrl_cc13xx_cc26xx.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_CC23X0 pinctrl_cc23x0.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_ESP32 pinctrl_esp32.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_RV32M1 pinctrl_rv32m1.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_INFINEON_CAT1 pinctrl_ifx_cat1.c)
@@ -29,6 +35,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_XLNX_ZYNQMP pinctrl_xlnx_zynqmp.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_XMC4XXX pinctrl_xmc4xxx.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_S32 pinctrl_nxp_s32.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_GECKO pinctrl_gecko.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_SILABS_SIWX91X pinctrl_silabs_siwx91x.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_SILABS_DBUS pinctrl_silabs_dbus.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_TI_K3 pinctrl_ti_k3.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_EMSDP pinctrl_emsdp.c)
@@ -44,5 +51,6 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_MEC5 pinctrl_mchp_mec5.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_AFIO pinctrl_wch_afio.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_SY1XX pinctrl_sy1xx.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_REALTEK_RTS5912 pinctrl_realtek_rts5912.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_20X_30X_AFIO pinctrl_wch_20x_30x_afio.c)
 
 add_subdirectory(renesas)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 299372eea7f..9cdbfd42444 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -1,4 +1,5 @@
 # Copyright (c) 2021 Nordic Semiconductor ASA
+# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 menuconfig PINCTRL
@@ -34,7 +35,11 @@ config PINCTRL_DYNAMIC
 	  peripheral at early boot stages depending on a certain input.
 
 source "drivers/pinctrl/Kconfig.b91"
+source "drivers/pinctrl/Kconfig.bflb"
 source "drivers/pinctrl/Kconfig.ambiq"
+source "drivers/pinctrl/Kconfig.arm_mps2"
+source "drivers/pinctrl/Kconfig.arm_mps3"
+source "drivers/pinctrl/Kconfig.arm_v2m_beetle"
 source "drivers/pinctrl/Kconfig.gd32"
 source "drivers/pinctrl/Kconfig.it8xxx2"
 source "drivers/pinctrl/Kconfig.npcx"
@@ -50,6 +55,7 @@ source "drivers/pinctrl/Kconfig.imx"
 source "drivers/pinctrl/Kconfig.sifive"
 source "drivers/pinctrl/Kconfig.lpc_iocon"
 source "drivers/pinctrl/Kconfig.cc13xx_cc26xx"
+source "drivers/pinctrl/Kconfig.cc23x0"
 source "drivers/pinctrl/Kconfig.esp32"
 source "drivers/pinctrl/Kconfig.rv32m1"
 source "drivers/pinctrl/Kconfig.ifx_cat1"
@@ -58,6 +64,7 @@ source "drivers/pinctrl/Kconfig.xmc4xxx"
 source "drivers/pinctrl/Kconfig.nxp_s32"
 source "drivers/pinctrl/Kconfig.gecko"
 source "drivers/pinctrl/Kconfig.silabs_dbus"
+source "drivers/pinctrl/Kconfig.siwx91x"
 source "drivers/pinctrl/Kconfig.ti_k3"
 source "drivers/pinctrl/Kconfig.emsdp"
 source "drivers/pinctrl/Kconfig.ti_cc32xx"
@@ -71,6 +78,7 @@ source "drivers/pinctrl/Kconfig.mec5"
 source "drivers/pinctrl/Kconfig.wch_afio"
 source "drivers/pinctrl/Kconfig.sy1xx"
 source "drivers/pinctrl/Kconfig.realtek_rts5912"
+source "drivers/pinctrl/Kconfig.wch_20x_30x_afio"
 
 rsource "renesas/Kconfig"
 
diff --git a/drivers/pinctrl/Kconfig.ambiq b/drivers/pinctrl/Kconfig.ambiq
index 336dce05dec..70d476793c8 100644
--- a/drivers/pinctrl/Kconfig.ambiq
+++ b/drivers/pinctrl/Kconfig.ambiq
@@ -5,7 +5,7 @@
 config PINCTRL_AMBIQ
 	bool "Ambiq Apollo pin controller driver"
 	default y
-	depends on DT_HAS_AMBIQ_APOLLO4_PINCTRL_ENABLED || DT_HAS_AMBIQ_APOLLO3_PINCTRL_ENABLED
+	depends on DT_HAS_AMBIQ_APOLLO5_PINCTRL_ENABLED || DT_HAS_AMBIQ_APOLLO4_PINCTRL_ENABLED || DT_HAS_AMBIQ_APOLLO3_PINCTRL_ENABLED
 	select AMBIQ_HAL
 	select AMBIQ_HAL_USE_GPIO
 	help
diff --git a/drivers/pinctrl/Kconfig.arm_mps2 b/drivers/pinctrl/Kconfig.arm_mps2
new file mode 100644
index 00000000000..0820a671087
--- /dev/null
+++ b/drivers/pinctrl/Kconfig.arm_mps2
@@ -0,0 +1,10 @@
+# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# SPDX-License-Identifier: Apache-2.0
+
+
+config PINCTRL_ARM_MPS2
+	bool "Arm MPS2 pin controller driver"
+	default y
+	depends on DT_HAS_ARM_MPS2_PINCTRL_ENABLED
+	help
+	  Arm MPS2 pinctrl driver
diff --git a/drivers/pinctrl/Kconfig.arm_mps3 b/drivers/pinctrl/Kconfig.arm_mps3
new file mode 100644
index 00000000000..335b4f055c5
--- /dev/null
+++ b/drivers/pinctrl/Kconfig.arm_mps3
@@ -0,0 +1,9 @@
+# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config PINCTRL_ARM_MPS3
+	bool "Arm MPS3 pin controller driver"
+	default y
+	depends on DT_HAS_ARM_MPS3_PINCTRL_ENABLED
+	help
+	  Arm MPS2 pinctrl driver
diff --git a/drivers/pinctrl/Kconfig.arm_v2m_beetle b/drivers/pinctrl/Kconfig.arm_v2m_beetle
new file mode 100644
index 00000000000..218ea123011
--- /dev/null
+++ b/drivers/pinctrl/Kconfig.arm_v2m_beetle
@@ -0,0 +1,9 @@
+# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config PINCTRL_ARM_V2M_BEETLE
+	bool "Arm V2M Beetle pin controller driver"
+	default y
+	depends on DT_HAS_ARM_V2M_BEETLE_PINCTRL_ENABLED
+	help
+	  Arm MPS2 V2M Beetle driver
diff --git a/drivers/pinctrl/Kconfig.bflb b/drivers/pinctrl/Kconfig.bflb
new file mode 100644
index 00000000000..c49d600f247
--- /dev/null
+++ b/drivers/pinctrl/Kconfig.bflb
@@ -0,0 +1,10 @@
+# Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config PINCTRL_BFLB
+	bool "Bouffalo Lab pin control driver"
+	depends on DT_HAS_BFLB_PINCTRL_ENABLED
+	default y
+	help
+	  Bouffalo Lab pin control driver
diff --git a/drivers/pinctrl/Kconfig.cc23x0 b/drivers/pinctrl/Kconfig.cc23x0
new file mode 100644
index 00000000000..f10e2215aa0
--- /dev/null
+++ b/drivers/pinctrl/Kconfig.cc23x0
@@ -0,0 +1,11 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+# Copyright (c) 2024 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config PINCTRL_CC23X0
+	bool "TI SimpleLink CC23X0 pinctrl driver"
+	default y
+	depends on DT_HAS_TI_CC23X0_PINCTRL_ENABLED
+	help
+	  Enable the TI SimpleLink CC23X0 pinctrl driver
diff --git a/drivers/pinctrl/Kconfig.imx b/drivers/pinctrl/Kconfig.imx
index ceb61d74513..a79d91e28b9 100644
--- a/drivers/pinctrl/Kconfig.imx
+++ b/drivers/pinctrl/Kconfig.imx
@@ -26,6 +26,12 @@ config PINCTRL_IMX_SCMI
 # TODO: Find better place for this option
 config MCUX_XBARA
 	bool "MCUX XBARA driver"
-	depends on HAS_MCUX_XBARA
+	depends on DT_HAS_NXP_MCUX_XBAR_ENABLED
 	help
 	  Enable the MCUX XBARA driver.
+
+config MCUX_XBARB
+	bool "MCUX XBARB driver"
+	depends on DT_HAS_NXP_MCUX_XBAR_ENABLED
+	help
+	  Enable the MCUX XBARB driver.
diff --git a/drivers/pinctrl/Kconfig.realtek_rts5912 b/drivers/pinctrl/Kconfig.realtek_rts5912
index 12b926b3f52..925729389ab 100644
--- a/drivers/pinctrl/Kconfig.realtek_rts5912
+++ b/drivers/pinctrl/Kconfig.realtek_rts5912
@@ -5,6 +5,7 @@
 
 config PINCTRL_REALTEK_RTS5912
 	bool "Pin controller driver for REALTEK RTS MCUs"
+	depends on SOC_SERIES_RTS5912
 	default y if DT_HAS_REALTEK_RTS5912_PINCTRL_ENABLED
 	help
 	  Enable pin controller driver for REALTEK RTS MCUs
diff --git a/drivers/pinctrl/Kconfig.rpi_pico b/drivers/pinctrl/Kconfig.rpi_pico
index 7ce46bdafa0..9fc8d19085b 100644
--- a/drivers/pinctrl/Kconfig.rpi_pico
+++ b/drivers/pinctrl/Kconfig.rpi_pico
@@ -2,9 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config PINCTRL_RPI_PICO
-	bool "RaspberryPi Pico pin controller driver"
+	bool "Raspberry Pi Pico pin controller driver"
 	default y
 	depends on DT_HAS_RASPBERRYPI_PICO_PINCTRL_ENABLED
 	select PICOSDK_USE_GPIO
 	help
-	  RaspberryPi Pico pinctrl driver
+	  Raspberry Pi Pico pinctrl driver
diff --git a/drivers/pinctrl/Kconfig.siwx91x b/drivers/pinctrl/Kconfig.siwx91x
new file mode 100644
index 00000000000..7c803364dde
--- /dev/null
+++ b/drivers/pinctrl/Kconfig.siwx91x
@@ -0,0 +1,9 @@
+# Copyright (c) 2023 Antmicro
+# SPDX-License-Identifier: Apache-2.0
+
+config PINCTRL_SILABS_SIWX91X
+	bool "Silabs SiWx91x SoC series pinctrl driver"
+	default y
+	depends on DT_HAS_SILABS_SIWX91X_PINCTRL_ENABLED
+	help
+	  Enable the pinctrl driver for the Silabs SiWx91x SoC series.
diff --git a/drivers/pinctrl/Kconfig.wch_20x_30x_afio b/drivers/pinctrl/Kconfig.wch_20x_30x_afio
new file mode 100644
index 00000000000..a13e7ac09d4
--- /dev/null
+++ b/drivers/pinctrl/Kconfig.wch_20x_30x_afio
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 MASSDRIVER EI (massdriver.sapce)
+# SPDX-License-Identifier: Apache-2.0
+
+config PINCTRL_WCH_20X_30X_AFIO
+	bool "WCH AFIO pin controller driver for CH32V20x/30x"
+	default y
+	depends on DT_HAS_WCH_20X_30X_AFIO_ENABLED
+	help
+	  WCH CH32V20x/30x AFIO pin controller driver.
diff --git a/drivers/pinctrl/pinctrl_ambiq.c b/drivers/pinctrl/pinctrl_ambiq.c
index 0be5a24052a..b6c3e9ff676 100644
--- a/drivers/pinctrl/pinctrl_ambiq.c
+++ b/drivers/pinctrl/pinctrl_ambiq.c
@@ -7,7 +7,7 @@
 #include <zephyr/drivers/pinctrl.h>
 
 /* ambiq-sdk includes */
-#include <am_mcu_apollo.h>
+#include <soc.h>
 
 static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
 {
@@ -22,7 +22,8 @@ static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
 			       : pin->tristate   ? AM_HAL_GPIO_PIN_OUTCFG_TRISTATE
 						 : AM_HAL_GPIO_PIN_OUTCFG_DISABLE;
 	pin_config.eDriveStrength = pin->drive_strength;
-	pin_config.uNCE = pin->iom_nce;
+	pin_config.uNCE = pin->nce;
+	pin_config.eCEpol = pin->nce_pol;
 #if defined(CONFIG_SOC_APOLLO3P_BLUE)
 	pin_config.bIomMSPIn = pin->iom_mspi;
 #endif
@@ -42,9 +43,40 @@ static void pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
 					: pin->tristate   ? AM_HAL_GPIO_PIN_OUTCFG_TRISTATE
 							  : AM_HAL_GPIO_PIN_OUTCFG_DISABLE;
 	pin_config.GP.cfg_b.eDriveStrength = pin->drive_strength;
+#if defined(CONFIG_SOC_SERIES_APOLLO4X)
 	pin_config.GP.cfg_b.uSlewRate = pin->slew_rate;
-	pin_config.GP.cfg_b.uNCE = pin->iom_nce;
-	pin_config.GP.cfg_b.eIntDir = pin->interrupt_direction;
+	switch (pin->sdif_cdwp) {
+	case 1:
+		am_hal_gpio_cd_pin_config(pin->pin_num);
+		break;
+	case 2:
+		am_hal_gpio_wp_pin_config(pin->pin_num);
+		break;
+	default:
+		/* not a sdif pin */
+		break;
+	}
+#else
+	switch (pin->sdif_cdwp) {
+	case 1:
+		am_hal_gpio_cd0_pin_config(pin->pin_num);
+		break;
+	case 2:
+		am_hal_gpio_wp0_pin_config(pin->pin_num);
+		break;
+	case 3:
+		am_hal_gpio_cd1_pin_config(pin->pin_num);
+		break;
+	case 4:
+		am_hal_gpio_wp1_pin_config(pin->pin_num);
+		break;
+	default:
+		/* not a sdif pin */
+		break;
+	}
+#endif
+	pin_config.GP.cfg_b.uNCE = pin->nce;
+	pin_config.GP.cfg_b.eCEpol = pin->nce_pol;
 
 	if (pin->bias_pull_up) {
 		pin_config.GP.cfg_b.ePullup = pin->ambiq_pull_up_ohms + AM_HAL_GPIO_PIN_PULLUP_1_5K;
diff --git a/drivers/pinctrl/pinctrl_arm_mps2.c b/drivers/pinctrl/pinctrl_arm_mps2.c
new file mode 100644
index 00000000000..c78a007fdf3
--- /dev/null
+++ b/drivers/pinctrl/pinctrl_arm_mps2.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "zephyr/device.h"
+#include "zephyr/drivers/gpio.h"
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/devicetree/gpio.h>
+#include <zephyr/drivers/gpio/gpio_cmsdk_ahb.h>
+
+/**
+ * The ARM MPS2 Board has 4 GPIO controllers. These controllers
+ * are responsible for pin muxing, input/output, pull-up, etc.
+ *
+ * All GPIO controller pins are exposed via the following sequence of pin
+ * numbers:
+ *   Pins  0 -  15 are for GPIO0
+ *   Pins 16 -  31 are for GPIO1
+ *   Pins 32 -  47 are for GPIO2
+ *   Pins 48 -  51 are for GPIO3
+ *
+ * For the GPIO controllers configuration ARM MPS2 Board follows the
+ * Arduino compliant pin out.
+ */
+
+static const struct device *const gpio_ports[] = {
+	DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpio0)),
+	DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpio1)),
+	DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpio2)),
+	DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpio3)),
+};
+
+static int pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
+{
+	uint32_t flags = pin->input_enable ? GPIO_INPUT : GPIO_OUTPUT;
+
+	/* Each gpio has 16 pins, so divide by 16 to get specific gpio*/
+	const struct device *gpio_dev = gpio_ports[pin->pin_num >> 4];
+
+	return cmsdk_ahb_gpio_config(gpio_dev, pin->pin_num % 16, flags);
+}
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
+{
+	ARG_UNUSED(reg);
+	for (uint8_t i = 0U; i < pin_cnt; i++) {
+		if (pinctrl_configure_pin(pins++) == -ENOTSUP) {
+			return -ENOTSUP;
+		}
+	}
+
+	return 0;
+}
diff --git a/drivers/pinctrl/pinctrl_arm_mps3.c b/drivers/pinctrl/pinctrl_arm_mps3.c
new file mode 100644
index 00000000000..c3b1eb2402f
--- /dev/null
+++ b/drivers/pinctrl/pinctrl_arm_mps3.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "zephyr/device.h"
+#include "zephyr/drivers/gpio.h"
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/devicetree/gpio.h>
+#include <zephyr/drivers/gpio/gpio_cmsdk_ahb.h>
+
+static const struct device *const gpio_ports[] = {DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpio0)),
+						  DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpio1)),
+						  DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpio2))};
+
+static int pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
+{
+	uint32_t flags = pin->input_enable ? GPIO_INPUT : GPIO_OUTPUT;
+
+	/* Each gpio has 16 pins, so divide by 16 to get specific gpio*/
+	const struct device *gpio_dev = gpio_ports[pin->pin_num >> 4];
+
+	return cmsdk_ahb_gpio_config(gpio_dev, pin->pin_num % 16, flags);
+}
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
+{
+	ARG_UNUSED(reg);
+	for (uint8_t i = 0U; i < pin_cnt; i++) {
+		if (pinctrl_configure_pin(pins++) == -ENOTSUP) {
+			return -ENOTSUP;
+		}
+	}
+
+	return 0;
+}
diff --git a/drivers/pinctrl/pinctrl_arm_v2m_beetle.c b/drivers/pinctrl/pinctrl_arm_v2m_beetle.c
new file mode 100644
index 00000000000..47fba5a6a2b
--- /dev/null
+++ b/drivers/pinctrl/pinctrl_arm_v2m_beetle.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "zephyr/device.h"
+#include "zephyr/drivers/gpio.h"
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/devicetree/gpio.h>
+#include <zephyr/drivers/gpio/gpio_cmsdk_ahb.h>
+
+#define EXPANSION_SHIELD_POWER_ENABLE_MASK	BIT(15)
+
+static const struct device *const gpio_ports[] = {DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpio0)),
+						  DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpio1))};
+
+static int pinctrl_configure_pin(const pinctrl_soc_pin_t *pin)
+{
+	uint32_t flags = pin->input_enable ? GPIO_INPUT : GPIO_OUTPUT;
+
+	/* Each gpio has 16 pins, so divide by 16 to get specific gpio*/
+	const struct device *gpio_dev = gpio_ports[pin->pin_num >> 4];
+
+	return cmsdk_ahb_gpio_config(gpio_dev, pin->pin_num % 16, flags);
+}
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
+{
+	ARG_UNUSED(reg);
+	for (uint8_t i = 0U; i < pin_cnt; i++) {
+		if (pinctrl_configure_pin(pins++) == -ENOTSUP) {
+			return -ENOTSUP;
+		}
+	}
+
+	const struct gpio_cmsdk_ahb_cfg *const cfg = gpio_ports[1]->config;
+	/* Set the ARD_PWR_EN GPIO1[15] as an output */
+	cfg->port->outenableset |= EXPANSION_SHIELD_POWER_ENABLE_MASK;
+	/* Set on 3v3 (for ARDUINO HDR compliance) */
+	cfg->port->data |= EXPANSION_SHIELD_POWER_ENABLE_MASK;
+
+	return 0;
+}
diff --git a/drivers/pinctrl/pinctrl_bflb.c b/drivers/pinctrl/pinctrl_bflb.c
new file mode 100644
index 00000000000..b40a555e444
--- /dev/null
+++ b/drivers/pinctrl/pinctrl_bflb.c
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <bflb_pinctrl.h>
+#include <bflb_glb.h>
+#include <bflb_gpio.h>
+
+/* clang-format off */
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
+			   uintptr_t reg)
+{
+	GLB_GPIO_Cfg_Type pincfg;
+	uint8_t i;
+
+	ARG_UNUSED(reg);
+
+	for (i = 0U; i < pin_cnt; i++) {
+		pincfg.gpioFun  = BFLB_PINMUX_GET_FUN(pins[i]);
+		pincfg.gpioMode = BFLB_PINMUX_GET_MODE(pins[i]);
+		pincfg.gpioPin  = BFLB_PINMUX_GET_PIN(pins[i]);
+		pincfg.pullType = BFLB_PINMUX_GET_PULL_MODES(pins[i]);
+		pincfg.smtCtrl  = BFLB_PINMUX_GET_SMT(pins[i]);
+		pincfg.drive    = BFLB_PINMUX_GET_DRIVER_STRENGTH(pins[i]);
+
+		if (pincfg.gpioFun == BFLB_PINMUX_FUN_INST_uart0) {
+			GLB_UART_Fun_Sel(pincfg.gpioPin % 8,
+					 (BFLB_PINMUX_GET_INST(pins[i]))
+					  * 0x4U /* rts, cts, rx, tx */
+					  + BFLB_PINMUX_GET_SIGNAL(pins[i])
+					 );
+		}
+
+		GLB_GPIO_Init(&pincfg);
+	}
+
+	return 0;
+}
+
+/* clang-format on */
diff --git a/drivers/pinctrl/pinctrl_cc23x0.c b/drivers/pinctrl/pinctrl_cc23x0.c
new file mode 100644
index 00000000000..41ce0be662e
--- /dev/null
+++ b/drivers/pinctrl/pinctrl_cc23x0.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ti_cc23x0_pinctrl
+
+#include <zephyr/drivers/pinctrl.h>
+
+#include <inc/hw_types.h>
+
+#define IOC_BASE_REG     DT_REG_ADDR(DT_NODELABEL(pinctrl))
+#define IOC_BASE_PIN_REG 0x00000100
+#define IOC_ADDR(index)  (IOC_BASE_REG + IOC_BASE_PIN_REG + (sizeof(uint32_t) * (index)))
+
+static int pinctrl_cc23x0_set(uint32_t pin, uint32_t func, uint32_t mode)
+{
+	uint32_t iocfg_reg = IOC_ADDR(pin);
+
+	HWREG(iocfg_reg) = mode | func;
+
+	return 0;
+}
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
+{
+	ARG_UNUSED(reg);
+
+	for (uint8_t i = 0U; i < pin_cnt; i++) {
+		pinctrl_cc23x0_set(pins[i].pin, pins[i].iofunc, pins[i].iomode);
+	}
+
+	return 0;
+}
diff --git a/drivers/pinctrl/pinctrl_gecko.c b/drivers/pinctrl/pinctrl_gecko.c
index db8f5523c01..ffca6c45e2b 100644
--- a/drivers/pinctrl/pinctrl_gecko.c
+++ b/drivers/pinctrl/pinctrl_gecko.c
@@ -142,7 +142,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp
 #endif /* CONFIG_SOC_FAMILY_SILABS_S1 */
 #endif /* CONFIG_UART_GECKO */
 
-#ifdef CONFIG_SPI_GECKO_USART
+#ifdef CONFIG_SPI_SILABS_USART
 #ifdef CONFIG_SOC_FAMILY_SILABS_S1
 		case GECKO_FUN_SPIM_SCK:
 			pin_config.mode = gpioModePushPull;
@@ -224,7 +224,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp
 			base->ROUTELOC0 |= (loc << _USART_ROUTELOC0_CSLOC_SHIFT);
 			break;
 #endif /* CONFIG_SOC_FAMILY_SILABS_S1 */
-#endif /* CONFIG_SPI_GECKO_USART */
+#endif /* CONFIG_SPI_SILABS_USART */
 
 #ifdef CONFIG_I2C_GECKO
 		case GECKO_FUN_I2C_SDA:
diff --git a/drivers/pinctrl/pinctrl_imx.c b/drivers/pinctrl/pinctrl_imx.c
index 8d60cea5817..51a81f134ea 100644
--- a/drivers/pinctrl/pinctrl_imx.c
+++ b/drivers/pinctrl/pinctrl_imx.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022, 2024 NXP
+ * Copyright 2022, 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -33,7 +33,7 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 		}
 #endif
 
-#ifdef CONFIG_SOC_MIMX9352
+#if defined(CONFIG_SOC_MIMX9352) || defined(CONFIG_SOC_MIMX9131)
 		sys_write32(IOMUXC1_SW_MUX_CTL_PAD_MUX_MODE(mux_mode) |
 			IOMUXC1_SW_MUX_CTL_PAD_SION(MCUX_IMX_INPUT_ENABLE(pin_ctrl_flags)),
 			(mem_addr_t)mux_register);
diff --git a/drivers/pinctrl/pinctrl_ite_it8xxx2.c b/drivers/pinctrl/pinctrl_ite_it8xxx2.c
index 422f8c6c67f..1416af04809 100644
--- a/drivers/pinctrl/pinctrl_ite_it8xxx2.c
+++ b/drivers/pinctrl/pinctrl_ite_it8xxx2.c
@@ -14,8 +14,6 @@
 
 LOG_MODULE_REGISTER(pinctrl_ite_it8xxx2, LOG_LEVEL_ERR);
 
-#define GPIO_IT8XXX2_REG_BASE \
-	((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr)))
 #define GPIO_GROUP_MEMBERS  8
 
 struct pinctrl_it8xxx2_gpio {
@@ -291,7 +289,7 @@ static int pinctrl_kscan_it8xxx2_configure_pins(const pinctrl_soc_pin_t *pins)
 		return -EINVAL;
 	}
 
-#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
+#if defined(CONFIG_SOC_IT8XXX2_REG_SET_V1) || defined(CONFIG_SOC_SERIES_IT51XXX)
 	uint8_t pin_mask = BIT(pins->pin);
 	volatile uint8_t *reg_gctrl = ksi_kso->reg_gctrl;
 
@@ -356,14 +354,14 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 
 static int pinctrl_it8xxx2_init(const struct device *dev)
 {
-	struct gpio_it8xxx2_regs *const gpio_base = GPIO_IT8XXX2_REG_BASE;
+	struct gpio_ite_ec_regs *const gpio_base = GPIO_ITE_EC_REGS_BASE;
 
 	/*
 	 * The default value of LPCRSTEN is bit2:1 = 10b(GPD2) in GCR.
 	 * If LPC reset is enabled on GPB7, we have to clear bit2:1
 	 * to 00b.
 	 */
-	gpio_base->GPIO_GCR &= ~IT8XXX2_GPIO_LPCRSTEN;
+	gpio_base->GPIO_GCR &= ~ITE_EC_GPIO_LPCRSTEN;
 
 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
 #if defined(CONFIG_I2C_ITE_ENHANCE) && DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c5))
diff --git a/drivers/pinctrl/pinctrl_lpc_iocon.c b/drivers/pinctrl/pinctrl_lpc_iocon.c
index 805cd46849b..ff85bb0cbba 100644
--- a/drivers/pinctrl/pinctrl_lpc_iocon.c
+++ b/drivers/pinctrl/pinctrl_lpc_iocon.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022, NXP
+ * Copyright 2022,2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,22 +11,40 @@
 #include <fsl_clock.h>
 #endif
 
+/* IOCON register addresses. */
+static uint32_t volatile *iocon[] = {
+#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(iocon)))
+	(uint32_t *)DT_REG_ADDR(DT_NODELABEL(iocon)),
+#else
+	NULL,
+#endif
+#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(iocon1)))
+	(uint32_t *)DT_REG_ADDR(DT_NODELABEL(iocon1)),
+#else
+	NULL,
+#endif
+#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(iocon2)))
+	(uint32_t *)DT_REG_ADDR(DT_NODELABEL(iocon2)),
+#else
+	NULL,
+#endif
+};
+
 #define OFFSET(mux) (((mux) & 0xFFF00000) >> 20)
 #define TYPE(mux) (((mux) & 0xC0000) >> 18)
+#define INDEX(mux)  (((mux) & 0x38000) >> 15)
 
 #define IOCON_TYPE_D 0x0
 #define IOCON_TYPE_I 0x1
 #define IOCON_TYPE_A 0x2
 
-static volatile uint32_t *iocon =
-	(volatile uint32_t *)DT_REG_ADDR(DT_NODELABEL(iocon));
 
-int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
-			   uintptr_t reg)
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
 {
 	for (uint8_t i = 0; i < pin_cnt; i++) {
 		uint32_t pin_mux = pins[i];
 		uint32_t offset = OFFSET(pin_mux);
+		uint8_t index = INDEX(pin_mux);
 
 		/* Check if this is an analog or i2c type pin */
 		switch (TYPE(pin_mux)) {
@@ -44,7 +62,8 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			__ASSERT_NO_MSG(TYPE(pin_mux) <= IOCON_TYPE_A);
 		}
 		/* Set pinmux */
-		*(iocon + offset) = pin_mux;
+		*(iocon[index] + offset) = pin_mux;
+
 	}
 	return 0;
 }
diff --git a/drivers/pinctrl/pinctrl_nrf.c b/drivers/pinctrl/pinctrl_nrf.c
index 70a2983482d..05c0ed9ac0b 100644
--- a/drivers/pinctrl/pinctrl_nrf.c
+++ b/drivers/pinctrl/pinctrl_nrf.c
@@ -100,10 +100,10 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = {
 #endif
 
 #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_grtc) || defined(CONFIG_NRFX_GRTC)
-#if DT_NODE_HAS_PROP(DT_NODELABEL(grtc), clkout_fast_frequency)
+#if DT_NODE_HAS_PROP(DT_NODELABEL(grtc), clkout_fast_frequency_hz)
 #define NRF_GRTC_CLKOUT_FAST 1
 #endif
-#if DT_NODE_HAS_PROP(DT_NODELABEL(grtc), clkout_32k_frequency)
+#if DT_NODE_HAS_PROP(DT_NODELABEL(grtc), clkout_32k)
 #define NRF_GRTC_CLKOUT_SLOW 1
 #endif
 #endif
diff --git a/drivers/pinctrl/pinctrl_silabs_dbus.c b/drivers/pinctrl/pinctrl_silabs_dbus.c
index be918847b16..edca73d6db4 100644
--- a/drivers/pinctrl/pinctrl_silabs_dbus.c
+++ b/drivers/pinctrl/pinctrl_silabs_dbus.c
@@ -11,6 +11,7 @@
 
 #define DT_DRV_COMPAT silabs_dbus_pinctrl
 #define PIN_MASK      0xF0000UL
+#define ABUS_MASK(i)  GENMASK(((i) * 8) + 3, (i) * 8)
 
 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
 {
@@ -19,17 +20,33 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp
 	for (uint8_t i = 0U; i < pin_cnt; i++) {
 		mem_addr_t enable_reg, route_reg;
 
+		/* Configure ABUS */
+		if (pins[i].en_bit == SILABS_PINCTRL_ANALOG) {
+			enable_reg = DT_INST_REG_ADDR_BY_NAME(0, abus) +
+				     (pins[i].base_offset * sizeof(mem_addr_t));
+			sys_write32(FIELD_PREP(ABUS_MASK(pins[i].mode), pins[i].route_offset),
+				    enable_reg);
+			continue;
+		}
+
 		/* Configure GPIO */
 		GPIO_PinModeSet(pins[i].port, pins[i].pin, pins[i].mode, pins[i].dout);
 
 		/* Configure DBUS */
-		enable_reg = DT_INST_REG_ADDR(0) + (pins[i].base_offset * sizeof(mem_addr_t));
+		enable_reg = DT_INST_REG_ADDR_BY_NAME(0, dbus) +
+			     (pins[i].base_offset * sizeof(mem_addr_t));
 		route_reg = enable_reg + (pins[i].route_offset * sizeof(mem_addr_t));
 
-		sys_write32(pins[i].port | FIELD_PREP(PIN_MASK, pins[i].pin), route_reg);
+		if (pins[i].route_offset != SILABS_PINCTRL_UNUSED) {
+			sys_write32(pins[i].port | FIELD_PREP(PIN_MASK, pins[i].pin), route_reg);
+		}
 
-		if (pins[i].en_bit != 0xFFU) {
-			sys_set_bit(enable_reg, pins[i].en_bit);
+		if (pins[i].en_bit != SILABS_PINCTRL_UNUSED) {
+			if (pins[i].mode == gpioModeDisabled) {
+				sys_clear_bit(enable_reg, pins[i].en_bit);
+			} else {
+				sys_set_bit(enable_reg, pins[i].en_bit);
+			}
 		}
 	}
 
diff --git a/drivers/pinctrl/pinctrl_silabs_siwx91x.c b/drivers/pinctrl/pinctrl_silabs_siwx91x.c
new file mode 100644
index 00000000000..2e3a9f62488
--- /dev/null
+++ b/drivers/pinctrl/pinctrl_silabs_siwx91x.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2023 Antmicro
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT silabs_siwx91x_pinctrl
+
+#include <zephyr/drivers/pinctrl.h>
+#include "sl_si91x_peripheral_gpio.h"
+
+#define MODE_COUNT               16
+#define HP_PERIPHERAL_ON_ULP_PIN 6
+
+static bool pinctrl_siwx91x_valid_mode(uint8_t mode)
+{
+	return mode < MODE_COUNT;
+}
+
+static void pinctrl_siwx91x_set(uint8_t port, uint8_t pin, uint8_t ulppin, uint8_t mode,
+				uint8_t ulpmode, uint8_t pad)
+{
+	if (pad == 0) {
+		sl_si91x_gpio_enable_host_pad_selection((port << 4) | pin);
+	} else if (pad != 0xFF && pad != 9) {
+		sl_si91x_gpio_enable_pad_selection(pad);
+	}
+
+	if (port == SL_GPIO_ULP_PORT) {
+		sl_si91x_gpio_enable_ulp_pad_receiver(ulppin);
+	} else {
+		sl_si91x_gpio_enable_pad_receiver((port << 4) | pin);
+	}
+
+	if (pinctrl_siwx91x_valid_mode(mode)) {
+		GPIO->PIN_CONFIG[(port << 4) | pin].GPIO_CONFIG_REG_b.MODE = mode;
+	}
+
+	if (pinctrl_siwx91x_valid_mode(ulpmode)) {
+		if (pinctrl_siwx91x_valid_mode(mode) && ulpmode != HP_PERIPHERAL_ON_ULP_PIN) {
+			sl_si91x_gpio_ulp_soc_mode(ulppin, ulpmode);
+			ulpmode = 0;
+		}
+		ULP_GPIO->PIN_CONFIG[ulppin].GPIO_CONFIG_REG_b.MODE = ulpmode;
+	}
+}
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
+{
+	ARG_UNUSED(reg);
+	int i;
+
+	for (i = 0; i < pin_cnt; i++) {
+		pinctrl_siwx91x_set(pins[i].port, pins[i].pin, pins[i].ulppin, pins[i].mode,
+				    pins[i].ulpmode, pins[i].pad);
+	}
+
+	return 0;
+}
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c
index 9dc3e26f37c..dd7905e59be 100644
--- a/drivers/pinctrl/pinctrl_stm32.c
+++ b/drivers/pinctrl/pinctrl_stm32.c
@@ -63,6 +63,7 @@ static const struct device *const gpio_ports[] = {
 	DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpion)),
 	DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioo)),
 	DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpiop)),
+	DEVICE_DT_GET_OR_NULL(DT_NODELABEL(gpioq)),
 };
 
 /** Number of GPIO ports. */
@@ -168,19 +169,23 @@ static int stm32_pins_remap(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt)
 	uint32_t reg_val;
 	uint16_t remap;
 
-	remap = (uint16_t)STM32_DT_PINMUX_REMAP(pins[0].pinmux);
+	remap = NO_REMAP;
+
+	for (size_t i = 0U; i < pin_cnt; i++) {
+		if (remap == NO_REMAP) {
+			remap = STM32_DT_PINMUX_REMAP(pins[i].pinmux);
+		} else if (STM32_DT_PINMUX_REMAP(pins[i].pinmux) == NO_REMAP) {
+			continue;
+		} else if (STM32_DT_PINMUX_REMAP(pins[i].pinmux) != remap) {
+			return -EINVAL;
+		}
+	}
 
 	/* not remappable */
 	if (remap == NO_REMAP) {
 		return 0;
 	}
 
-	for (size_t i = 1U; i < pin_cnt; i++) {
-		if (STM32_DT_PINMUX_REMAP(pins[i].pinmux) != remap) {
-			return -EINVAL;
-		}
-	}
-
 	/* A valid remapping configuration is available */
 	/* Apply remapping before proceeding with pin configuration */
 	LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_AFIO);
diff --git a/drivers/pinctrl/pinctrl_wch_20x_30x_afio.c b/drivers/pinctrl/pinctrl_wch_20x_30x_afio.c
new file mode 100644
index 00000000000..ae22af8b648
--- /dev/null
+++ b/drivers/pinctrl/pinctrl_wch_20x_30x_afio.c
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/ch32v20x_30x-pinctrl.h>
+
+#include <ch32fun.h>
+
+static GPIO_TypeDef *const wch_afio_pinctrl_regs[] = {
+	(GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpioa)),
+	(GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpiob)),
+	(GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpioc)),
+	(GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpiod)),
+#if DT_NODE_EXISTS(DT_NODELABEL(gpioe))
+	(GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpioe)),
+#endif
+};
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
+{
+	int i;
+
+	for (i = 0; i < pin_cnt; i++, pins++) {
+		uint8_t port = FIELD_GET(CH32V20X_V30X_PINCTRL_PORT_MASK, pins->config);
+		uint8_t pin = FIELD_GET(CH32V20X_V30X_PINCTRL_PIN_MASK, pins->config);
+		uint8_t bit0 = FIELD_GET(CH32V20X_V30X_PINCTRL_RM_BASE_MASK, pins->config);
+		uint8_t pcfr_id = FIELD_GET(CH32V20X_V30X_PINCTRL_PCFR_ID_MASK, pins->config);
+		uint8_t remap = FIELD_GET(CH32V20X_V30X_PINCTRL_RM_MASK, pins->config);
+		GPIO_TypeDef *regs = wch_afio_pinctrl_regs[port];
+		uint32_t pcfr = pcfr_id == 0 ? AFIO->PCFR1 : AFIO->PCFR2;
+		uint8_t cfg = 0;
+
+		if (pins->output_high || pins->output_low) {
+			cfg |= (pins->slew_rate + 1);
+			if (pins->drive_open_drain) {
+				cfg |= BIT(2);
+			}
+			/* Select the alternate function */
+			cfg |= BIT(3);
+		} else {
+			if (pins->bias_pull_up || pins->bias_pull_down) {
+				cfg |= BIT(3);
+			}
+		}
+
+		if (pin < 8) {
+			regs->CFGLR = (regs->CFGLR & ~(0x0F << (pin * 4))) | (cfg << (pin * 4));
+		} else {
+			regs->CFGHR = (regs->CFGHR & ~(0x0F << ((pin - 8) * 4))) |
+				      (cfg << ((pin - 8) * 4));
+		}
+		if (pins->output_high) {
+			regs->OUTDR |= BIT(pin);
+			regs->BSHR |= BIT(pin);
+		} else if (pins->output_low) {
+			regs->OUTDR |= BIT(pin);
+			/* Reset the pin. */
+			regs->BSHR |= BIT(pin + 16);
+		} else {
+			regs->OUTDR &= ~BIT(pin);
+			if (pins->bias_pull_up) {
+				regs->BSHR = BIT(pin);
+			}
+			if (pins->bias_pull_down) {
+				regs->BCR = BIT(pin);
+			}
+		}
+
+		pcfr |= remap << bit0;
+
+		if (pcfr_id == 0) {
+			AFIO->PCFR1 = pcfr;
+		} else {
+			AFIO->PCFR2 = pcfr;
+		}
+
+		if (bit0 == CH32V20X_V30X_PINMUX_USART1_RM) {
+			pcfr = AFIO->PCFR2;
+			pcfr |= ((uint32_t)((remap >> 1) & 1)
+				 << (CH32V20X_V30X_PINMUX_USART1_RM1 & 0x1F));
+			AFIO->PCFR2 = pcfr;
+		}
+	}
+
+	return 0;
+}
diff --git a/drivers/pinctrl/renesas/CMakeLists.txt b/drivers/pinctrl/renesas/CMakeLists.txt
index 4d420529178..0382b0be253 100644
--- a/drivers/pinctrl/renesas/CMakeLists.txt
+++ b/drivers/pinctrl/renesas/CMakeLists.txt
@@ -1,10 +1,11 @@
 # Copyright (c) 2024 EPAM Systems
-# Copyright (c) 2024 Renesas Electronics Corporation
+# Copyright (c) 2024-2025 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RA_PFS ra/pinctrl_ra.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_RZT2M rz/pinctrl_rzt2m.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_SMARTBOND smartbond/pinctrl_smartbond.c)
 zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RZ rz/pinctrl_renesas_rz.c)
+zephyr_library_sources_ifdef(CONFIG_PINCTRL_RENESAS_RZA2M rz/pinctrl_renesas_rza2m.c)
 
 add_subdirectory_ifdef(CONFIG_PINCTRL_RCAR_PFC rcar)
diff --git a/drivers/pinctrl/renesas/ra/pinctrl_ra.c b/drivers/pinctrl/renesas/ra/pinctrl_ra.c
index 0f2bc85bd60..efaac2f34f7 100644
--- a/drivers/pinctrl/renesas/ra/pinctrl_ra.c
+++ b/drivers/pinctrl/renesas/ra/pinctrl_ra.c
@@ -26,16 +26,3 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintp
 
 	return 0;
 }
-
-int ra_pinctrl_query_config(uint32_t port, uint32_t pin, pinctrl_soc_pin_t *pincfg)
-{
-	if (port >= RA_PINCTRL_PORT_NUM || pin >= RA_PINCTRL_PIN_NUM) {
-		return -EINVAL;
-	}
-
-	pincfg->port_num = port;
-	pincfg->pin_num = pin;
-
-	pincfg->cfg = R_PFS->PORT[port].PIN[pin].PmnPFS;
-	return 0;
-}
diff --git a/drivers/pinctrl/renesas/rz/Kconfig b/drivers/pinctrl/renesas/rz/Kconfig
index 745496b8f17..0d18fc64e73 100644
--- a/drivers/pinctrl/renesas/rz/Kconfig
+++ b/drivers/pinctrl/renesas/rz/Kconfig
@@ -1,5 +1,5 @@
 # Copyright (c) 2023 Antmicro <www.antmicro.com>
-# Copyright (c) 2024 Renesas Electronics Corporation
+# Copyright (c) 2024-2025 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 config PINCTRL_RZT2M
@@ -12,7 +12,18 @@ config PINCTRL_RZT2M
 config PINCTRL_RENESAS_RZ
 	bool "Renesas RZ pin controller driver"
 	default y
-	depends on DT_HAS_RENESAS_RZG_PINCTRL_ENABLED
+	depends on DT_HAS_RENESAS_RZG_PINCTRL_ENABLED \
+		|| DT_HAS_RENESAS_RZN_PINCTRL_ENABLED \
+		|| DT_HAS_RENESAS_RZT_PINCTRL_ENABLED \
+		|| DT_HAS_RENESAS_RZA_PINCTRL_ENABLED \
+		|| DT_HAS_RENESAS_RZV_PINCTRL_ENABLED
 	select USE_RZ_FSP_IOPORT
 	help
 	  Enable Renesas RZ pinctrl driver.
+
+config PINCTRL_RENESAS_RZA2M
+	bool "Renesas RZA2M pin controller driver"
+	default y
+	depends on DT_HAS_RENESAS_RZA2M_PINCTRL_ENABLED
+	help
+	  Enable Renesas RZ pinctrl driver.
diff --git a/drivers/pinctrl/renesas/rz/pinctrl_renesas_rza2m.c b/drivers/pinctrl/renesas/rz/pinctrl_renesas_rza2m.c
new file mode 100644
index 00000000000..0f54a6242bc
--- /dev/null
+++ b/drivers/pinctrl/renesas/rz/pinctrl_renesas_rza2m.c
@@ -0,0 +1,520 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_rza2m_pinctrl
+
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza2m.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/device_mmio.h>
+
+#define RZA2M_PINCTRL_REG  DT_REG_ADDR(DT_NODELABEL(pinctrl))
+#define RZA2M_PINCTRL_SIZE DT_REG_SIZE(DT_NODELABEL(pinctrl))
+
+static struct rza2m_pinctrl_data {
+	mm_reg_t base_addr;
+	struct k_mutex lock;
+} rza2m_pinctrl_data;
+
+#define RZA2M_PDR(port)      (rza2m_pinctrl_data.base_addr + 0x0000 + (port) * 2)
+#define RZA2M_PMR(port)      (rza2m_pinctrl_data.base_addr + 0x0080 + (port))
+#define RZA2M_DSCR(port)     (rza2m_pinctrl_data.base_addr + 0x0140 + (port * 2))
+#define RZA2M_PFS(port, pin) (rza2m_pinctrl_data.base_addr + 0x0200 + ((port) * 8) + (pin))
+#define RZA2M_PPOC           (rza2m_pinctrl_data.base_addr + 0x0900)
+#define RZA2M_PSDMMC0        (rza2m_pinctrl_data.base_addr + 0x0920)
+#define RZA2M_PSDMMC1        (rza2m_pinctrl_data.base_addr + 0x0930)
+#define RZA2M_PSDMMC2        (rza2m_pinctrl_data.base_addr + 0x0940)
+#define RZA2M_PSPIBSC        (rza2m_pinctrl_data.base_addr + 0x0960)
+#define RZA2M_PCKIO          (rza2m_pinctrl_data.base_addr + 0x09D0)
+#define RZA2M_PWPR           (rza2m_pinctrl_data.base_addr + 0x02FF)
+
+#define RZA2M_PWPR_PFSWE BIT(6) /* PFSWE Bit Enable */
+#define RZA2M_PWPR_B0WI  BIT(7) /* PFSWE Bit Disable */
+
+#define RZA2M_PDR_INPUT  (0x02)
+#define RZA2M_PDR_OUTPUT (0x03)
+#define RZA2M_PDR_MASK   (0x03)
+
+#define RZA2M_DSCR_PIN_DRV_MASK (0x03)
+
+#define RZA2M_PSDMMC0_MASK (0x3FFF)
+#define RZA2M_PSDMMC1_MASK (0x7FF)
+#define RZA2M_PSDMMC2_MASK (0x3FFF)
+
+#define RZA2M_PIN_CURRENT_2mA  (0u)
+#define RZA2M_PIN_CURRENT_8mA  (1u)
+#define RZA2M_PIN_CURRENT_12mA (2u)
+
+#define RZA2M_PPOC_POC0          (0x00000001u)
+#define RZA2M_PPOC_POC0_SHIFT    (0u)
+#define RZA2M_PPOC_POC2          (0x00000004u)
+#define RZA2M_PPOC_POC2_SHIFT    (2u)
+#define RZA2M_PPOC_POC3          (0x00000008u)
+#define RZA2M_PPOC_POC3_SHIFT    (3u)
+#define RZA2M_PPOC_POCSEL0       (0x00000100u)
+#define RZA2M_PPOC_POCSEL0_SHIFT (8u)
+
+/* Implemented pins */
+static const uint8_t valid_gpio_support[] = {0x7F, 0x1F, 0x0F, 0x3F, 0xFF, 0xFF, 0xFF, 0xFF,
+					     0xFF, 0xFF, 0xFF, 0x3F, 0xFF, 0xFF, 0x7F, 0xFF,
+					     0xFF, 0x7F, 0xFF, 0x3F, 0x1F, 0x03};
+
+/* DSCR supported pins for 8mA */
+static const uint8_t valid_gpio_dscr_8ma_support[] = {
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x7F, 0x00, 0x00, 0x00};
+
+/* DSCR supported pins for 2mA */
+static const uint8_t valid_gpio_dscr_2ma_support[] = {
+	0x7F, 0x1F, 0x0F, 0x3F, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+	0x3F, 0xFF, 0xFF, 0x7F, 0xFF, 0xFF, 0x7F, 0xFF, 0x3F, 0x1F, 0x00};
+
+static bool rza2m_pin_function_check(const uint8_t *check_array, uint8_t port, uint8_t pin)
+{
+	bool ret;
+
+	ret = true;
+	if ((check_array[port] & (1u << pin)) == 0) {
+		ret = false;
+	}
+
+	return (ret);
+}
+
+static int rza2m_set_output_current_pin(const pinctrl_soc_pin_t pin)
+{
+	uint16_t reg_16;
+	uint16_t dscr;
+
+	dscr = 0;
+
+	if (!rza2m_pin_function_check(valid_gpio_support, pin.port, pin.pin)) {
+		return -EINVAL;
+	}
+
+	if (pin.drive_strength == RZA2M_PIN_CURRENT_2mA) {
+		if (!rza2m_pin_function_check(valid_gpio_dscr_2ma_support, pin.port, pin.pin)) {
+			return -EINVAL;
+		}
+		dscr = 1;
+	} else if (pin.drive_strength == RZA2M_PIN_CURRENT_8mA) {
+		if (!rza2m_pin_function_check(valid_gpio_dscr_8ma_support, pin.port, pin.pin)) {
+			return -EINVAL;
+		}
+		dscr = 3;
+	} else {
+		return -EINVAL;
+	}
+
+	/* Write to DCSR */
+	reg_16 = sys_read16(RZA2M_DSCR(pin.port));
+	reg_16 &= ~(RZA2M_DSCR_PIN_DRV_MASK << (pin.pin * 2));
+	reg_16 |= (dscr << pin.pin * 2);
+	sys_write16(reg_16, RZA2M_DSCR(pin.port));
+
+	return 0;
+}
+
+static int rza2m_set_output_current_ckio(uint8_t drive_strength)
+{
+	uint8_t ckio_drv;
+
+	if (drive_strength == RZA2M_PIN_CURRENT_8mA) {
+		ckio_drv = 1;
+	} else if (drive_strength == RZA2M_PIN_CURRENT_12mA) {
+		ckio_drv = 2;
+	} else {
+		return -EINVAL;
+	}
+
+	sys_write8(ckio_drv, RZA2M_PCKIO);
+
+	return 0;
+}
+
+static void rza2m_update_pspibsc(void)
+{
+	uint32_t pocsel0_poc0;
+	uint32_t reg_32;
+
+	pocsel0_poc0 = sys_read32(RZA2M_PPOC);
+	pocsel0_poc0 &= (RZA2M_PPOC_POCSEL0 | RZA2M_PPOC_POC0);
+
+	if (pocsel0_poc0 == (RZA2M_PPOC_POCSEL0 | RZA2M_PPOC_POC0)) {
+		/* 3.3v */
+		reg_32 = 0x5555555;
+	} else {
+		/* 1.8v */
+		reg_32 = 0xFFFFFFF;
+	}
+
+	sys_write32(reg_32, RZA2M_PSPIBSC);
+}
+
+static void rza2m_update_drv_sdmmc0(void)
+{
+	uint32_t reg_32;
+	uint32_t poc2;
+	uint32_t psdmmc0_val;
+	uint32_t psdmmc1_val;
+
+	poc2 = sys_read32(RZA2M_PPOC);
+	poc2 &= RZA2M_PPOC_POC2;
+
+	if (poc2 == RZA2M_PPOC_POC2) {
+		/* 3.3 V */
+		/* TDSEL = 0b11, other fields = 0b10 */
+		psdmmc0_val = 0x3AAA;
+		psdmmc1_val = 0x2AA;
+	} else {
+		/* 1.8 V */
+		/* TDSEL = 0b01, other fields = 0b11 */
+		psdmmc0_val = 0x1FFF;
+		psdmmc1_val = 0x3FF;
+	}
+
+	/* Read and write PSDMMC0 */
+	reg_32 = sys_read32(RZA2M_PSDMMC0);
+	reg_32 &= ~(RZA2M_PSDMMC0_MASK);
+	reg_32 |= psdmmc0_val;
+	sys_write32(reg_32, RZA2M_PSDMMC0);
+
+	/* Read and write PSDMMC1 */
+	reg_32 = sys_read32(RZA2M_PSDMMC1);
+	reg_32 &= ~(RZA2M_PSDMMC1_MASK);
+	reg_32 |= psdmmc1_val;
+	sys_write32(reg_32, RZA2M_PSDMMC1);
+}
+
+static void rza2m_update_drv_sdmmc1(void)
+{
+	uint32_t reg_32;
+	uint32_t poc3;
+	uint32_t psdmmc2_val;
+
+	poc3 = sys_read32(RZA2M_PPOC);
+	poc3 &= RZA2M_PPOC_POC3;
+
+	if (poc3 == RZA2M_PPOC_POC3) {
+		/* 3.3 V */
+		/* TDSEL = 0b11, other fields = 0b10 */
+		psdmmc2_val = 0x3AAA;
+	} else {
+		/* 1.8 V */
+		/* TDSEL = 0b01, other fields = 0b11 */
+		psdmmc2_val = 0x1FFF;
+	}
+
+	/* Read and write PSDMMC2 */
+	reg_32 = sys_read32(RZA2M_PSDMMC2);
+	reg_32 &= ~(RZA2M_PSDMMC2_MASK);
+	reg_32 |= psdmmc2_val;
+	sys_write32(reg_32, RZA2M_PSDMMC2);
+}
+
+static int rza2m_set_ppoc(const pinctrl_soc_pin_t pin)
+{
+	uint32_t reg_32;
+	uint32_t ppoc_val;
+	int ret;
+
+	ret = 0;
+	k_mutex_lock(&rza2m_pinctrl_data.lock, K_FOREVER);
+
+	switch (pin.pin) {
+	case PIN_POSEL:
+		ppoc_val = ((pin.func & 0x1) << RZA2M_PPOC_POC0_SHIFT) |
+			   (((pin.func & 0x2) >> 1) << RZA2M_PPOC_POCSEL0_SHIFT);
+
+		/* Set POC0 and POCSEL0 */
+		reg_32 = sys_read32(RZA2M_PPOC);
+		reg_32 &= ~(RZA2M_PPOC_POC0 & RZA2M_PPOC_POCSEL0);
+		reg_32 |= ppoc_val;
+		sys_write32(reg_32, RZA2M_PPOC);
+
+		rza2m_update_pspibsc();
+		break;
+
+	case PIN_POC2:
+		ppoc_val = ((pin.func & 0x1) << RZA2M_PPOC_POC2_SHIFT);
+
+		/* Set POC2 */
+		reg_32 = sys_read32(RZA2M_PPOC);
+		reg_32 &= ~(RZA2M_PPOC_POC2);
+		reg_32 |= ppoc_val;
+		sys_write32(reg_32, RZA2M_PPOC);
+
+		rza2m_update_drv_sdmmc0();
+		break;
+
+	case PIN_POC3:
+		ppoc_val = ((pin.func & 0x1) << RZA2M_PPOC_POC3_SHIFT);
+
+		/* Set POC3 */
+		reg_32 = sys_read32(RZA2M_PPOC);
+		reg_32 &= ~(RZA2M_PPOC_POC3);
+		reg_32 |= ppoc_val;
+		sys_write32(reg_32, RZA2M_PPOC);
+
+		rza2m_update_drv_sdmmc1();
+		break;
+
+	default:
+		ret = -EINVAL;
+	}
+
+	k_mutex_unlock(&rza2m_pinctrl_data.lock);
+
+	return ret;
+}
+
+/* PFS Register Write Protect : OFF */
+static void rza2m_unprotect_pin_mux(void)
+{
+	uint8_t reg_8;
+
+	/* Set B0WI to 0 */
+	reg_8 = sys_read8(RZA2M_PWPR);
+	reg_8 &= ~RZA2M_PWPR_B0WI;
+	sys_write8(reg_8, RZA2M_PWPR);
+
+	/* Set PFSWE to 1 */
+	reg_8 = sys_read8(RZA2M_PWPR);
+	reg_8 |= RZA2M_PWPR_PFSWE;
+	sys_write8(reg_8, RZA2M_PWPR);
+}
+
+/* PFS Register Write Protect : ON */
+static void rza2m_protect_pin_mux(void)
+{
+	uint8_t reg_8;
+
+	/* Set PFSWE to 0 */
+	reg_8 = sys_read8(RZA2M_PWPR);
+	reg_8 &= ~RZA2M_PWPR_PFSWE;
+	sys_write8(reg_8, RZA2M_PWPR);
+
+	/* Set B0WI to 1 */
+	reg_8 = sys_read8(RZA2M_PWPR);
+	reg_8 |= RZA2M_PWPR_B0WI;
+	sys_write8(reg_8, RZA2M_PWPR);
+}
+
+static int rza2m_set_pin_hiz(uint8_t port, uint8_t pin)
+{
+	uint16_t mask_16;
+	uint16_t reg_16;
+	uint8_t reg_8;
+
+	if (!rza2m_pin_function_check(valid_gpio_support, port, pin)) {
+		return -EINVAL;
+	}
+
+	k_mutex_lock(&rza2m_pinctrl_data.lock, K_FOREVER);
+
+	/* Set pin to Hi-z input protection */
+	reg_16 = sys_read16(RZA2M_PDR(port));
+	mask_16 = RZA2M_PDR_MASK << (pin * 2);
+	reg_16 &= ~mask_16;
+	sys_write16(reg_16, RZA2M_PDR(port));
+
+	rza2m_unprotect_pin_mux();
+
+	/* Set Pin function to 0 */
+	reg_8 = sys_read8(RZA2M_PFS(port, pin));
+	reg_8 &= ~(RZA2M_MUX_FUNC_MAX);
+	sys_write8(reg_8, RZA2M_PFS(port, pin));
+
+	rza2m_protect_pin_mux();
+
+	/* Switch to GPIO */
+	reg_8 = sys_read8(RZA2M_PMR(port));
+	reg_8 &= ~BIT(pin);
+	sys_write8(reg_8, RZA2M_PMR(port));
+
+	k_mutex_unlock(&rza2m_pinctrl_data.lock);
+
+	return 0;
+}
+
+static int rza2m_pin_to_gpio(uint8_t port, uint8_t pin, uint8_t dir)
+{
+	uint16_t mask_16;
+	uint16_t reg_16;
+	uint8_t reg_8;
+
+	if (!rza2m_pin_function_check(valid_gpio_support, port, pin)) {
+		return -EINVAL;
+	}
+
+	k_mutex_lock(&rza2m_pinctrl_data.lock, K_FOREVER);
+
+	/* Set pin to Hi-z input protection */
+	reg_16 = sys_read16(RZA2M_PDR(port));
+	mask_16 = RZA2M_PDR_MASK << (pin * 2);
+	reg_16 &= ~mask_16;
+	sys_write16(reg_16, RZA2M_PDR(port));
+
+	/* Use the pin as a general I/O pin */
+	reg_8 = sys_read8(RZA2M_PMR(port));
+	reg_8 &= ~BIT(pin);
+	sys_write8(reg_8, RZA2M_PMR(port));
+
+	/* Set pin direction */
+	reg_16 = sys_read16(RZA2M_PDR(port));
+	mask_16 = RZA2M_PDR_MASK << (pin * 2);
+	reg_16 &= ~mask_16;
+	reg_16 |= dir << (pin * 2);
+	sys_write16(reg_16, RZA2M_PDR(port));
+
+	k_mutex_unlock(&rza2m_pinctrl_data.lock);
+
+	return 0;
+}
+
+static int rza2m_set_pin_function(uint8_t port, uint8_t pin, uint8_t func)
+{
+	uint16_t mask_16;
+	uint16_t reg_16;
+	uint8_t reg_8;
+
+	if (!rza2m_pin_function_check(valid_gpio_support, port, pin)) {
+		return -EINVAL;
+	}
+
+	k_mutex_lock(&rza2m_pinctrl_data.lock, K_FOREVER);
+
+	/* Set pin to Hi-z input protection */
+	reg_16 = sys_read16(RZA2M_PDR(port));
+	mask_16 = RZA2M_PDR_MASK << (pin * 2);
+	reg_16 &= ~mask_16;
+	sys_write16(reg_16, RZA2M_PDR(port));
+
+	/* Temporarily switch to GPIO */
+	reg_8 = sys_read8(RZA2M_PMR(port));
+	reg_8 &= ~BIT(pin);
+	sys_write8(reg_8, RZA2M_PMR(port));
+
+	rza2m_unprotect_pin_mux();
+
+	/* Set Pin function */
+	reg_8 = sys_read8(RZA2M_PFS(port, pin));
+	reg_8 |= (func & RZA2M_MUX_FUNC_MAX);
+	sys_write8(reg_8, RZA2M_PFS(port, pin));
+
+	rza2m_protect_pin_mux();
+
+	/* Port Mode  : Peripheral module pin functions */
+	reg_8 = sys_read8(RZA2M_PMR(port));
+	reg_8 |= BIT(pin);
+	sys_write8(reg_8, RZA2M_PMR(port));
+
+	k_mutex_unlock(&rza2m_pinctrl_data.lock);
+
+	return 0;
+}
+
+static int rza2m_set_gpio_int(uint8_t port, uint8_t pin, bool int_en)
+{
+	uint8_t reg_8;
+
+	if (!rza2m_pin_function_check(valid_gpio_support, port, pin)) {
+		return -EINVAL;
+	}
+
+	rza2m_unprotect_pin_mux();
+
+	reg_8 = sys_read8(RZA2M_PFS(port, pin));
+	if (int_en) {
+		/* Enable interrupt, ISEL = 1 */
+		reg_8 |= BIT(6);
+	} else {
+		/* Disable interrupt, ISEL = 0 */
+		reg_8 &= ~BIT(6);
+	}
+	sys_write8(reg_8, RZA2M_PFS(port, pin));
+
+	rza2m_protect_pin_mux();
+
+	return 0;
+}
+
+static int pinctrl_configure_pin(const pinctrl_soc_pin_t pin)
+{
+	int ret;
+
+	ret = 0;
+
+	/* Some pins of PORT_G and PORT_J can be set to 8mA */
+	/* Use PORT_CKIO to configure current for the CKIO pin */
+	/* Use PORT_PPOC to configure voltage for SPI or SD/MMC interface, after that:
+	 *	- If configure voltage for SPI, PSPIBSC need to be updated
+	 *	- If configure voltage for SD/MMC, PSDMMC0, PSDMMC1 or PSDMMC2 need to be updated
+	 */
+	if (pin.port == PORT_G || pin.port == PORT_J) {
+		ret = rza2m_set_output_current_pin(pin);
+	} else if (pin.port == PORT_CKIO) {
+		ret = rza2m_set_output_current_ckio(pin.drive_strength);
+	} else if (pin.port == PORT_PPOC) {
+		ret = rza2m_set_ppoc(pin);
+	}
+
+	if (ret) {
+		return ret;
+	}
+
+	/* Configure pin to HiZ, input, output and peripheral */
+	if (pin.func & RZA2M_FUNC_GPIO_HIZ) {
+		ret = rza2m_set_pin_hiz(pin.port, pin.pin);
+	} else if (pin.func & RZA2M_FUNC_GPIO_INPUT) {
+		ret = rza2m_pin_to_gpio(pin.port, pin.pin, RZA2M_PDR_INPUT);
+	} else if (pin.func & RZA2M_FUNC_GPIO_OUTPUT) {
+		ret = rza2m_pin_to_gpio(pin.port, pin.pin, RZA2M_PDR_OUTPUT);
+	} else {
+		ret = rza2m_set_pin_function(pin.port, pin.pin, (pin.func & RZA2M_MUX_FUNC_MAX));
+	}
+
+	if (ret) {
+		return ret;
+	}
+
+	/* Set TINT */
+	if (pin.func & RZA2M_FUNC_GPIO_INT_EN) {
+		ret = rza2m_set_gpio_int(pin.port, pin.pin, true);
+	} else if (pin.func & RZA2M_FUNC_GPIO_INT_DIS) {
+		ret = rza2m_set_gpio_int(pin.port, pin.pin, false);
+	}
+
+	return ret;
+}
+
+int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
+{
+	int ret;
+
+	ret = 0;
+	ARG_UNUSED(reg);
+	while (pin_cnt-- > 0U) {
+		ret = pinctrl_configure_pin(*pins++);
+		if (ret < 0) {
+			break;
+		}
+	}
+
+	return ret;
+}
+
+__boot_func static int pinctrl_rza2m_driver_init(void)
+{
+	device_map(&rza2m_pinctrl_data.base_addr, RZA2M_PINCTRL_REG, RZA2M_PINCTRL_SIZE,
+		   K_MEM_CACHE_NONE);
+
+	k_mutex_init(&rza2m_pinctrl_data.lock);
+
+	return 0;
+}
+
+SYS_INIT(pinctrl_rza2m_driver_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/drivers/power_domain/CMakeLists.txt b/drivers/power_domain/CMakeLists.txt
index dedd7a50dff..d459e0d88c3 100644
--- a/drivers/power_domain/CMakeLists.txt
+++ b/drivers/power_domain/CMakeLists.txt
@@ -7,3 +7,4 @@ zephyr_library_sources_ifdef(CONFIG_POWER_DOMAIN_GPIO power_domain_gpio.c)
 zephyr_library_sources_ifdef(CONFIG_POWER_DOMAIN_GPIO_MONITOR power_domain_gpio_monitor.c)
 zephyr_library_sources_ifdef(CONFIG_POWER_DOMAIN_INTEL_ADSP power_domain_intel_adsp.c)
 zephyr_library_sources_ifdef(CONFIG_POWER_DOMAIN_NXP_SCU power_domain_nxp_scu.c)
+zephyr_library_sources_ifdef(CONFIG_POWER_DOMAIN_SOC_PM_STATE power_domain_soc_state_change.c)
diff --git a/drivers/power_domain/Kconfig b/drivers/power_domain/Kconfig
index f29057acf5c..7bf5fe42470 100644
--- a/drivers/power_domain/Kconfig
+++ b/drivers/power_domain/Kconfig
@@ -90,4 +90,13 @@ config POWER_DOMAIN_NXP_SCU_INIT_PRIORITY
 
 endif #POWER_DOMAIN_NXP_SCU
 
+config POWER_DOMAIN_SOC_PM_STATE
+	bool "SoC PM state power domain"
+	default y
+	depends on DT_HAS_POWER_DOMAIN_SOC_STATE_CHANGE_ENABLED
+	select DEVICE_DEPS
+	help
+	  Generic power domain control to turn on/off devices when the
+	  PM subsystem transitions in and out certain power states.
+
 endif
diff --git a/drivers/power_domain/power_domain_soc_state_change.c b/drivers/power_domain/power_domain_soc_state_change.c
new file mode 100644
index 00000000000..e177c60b4e4
--- /dev/null
+++ b/drivers/power_domain/power_domain_soc_state_change.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright 2024-25 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/kernel.h>
+#include <zephyr/kernel_structs.h>
+#include <zephyr/pm/device.h>
+#include <zephyr/pm/device_runtime.h>
+#include <zephyr/pm/pm.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(power_domain_soc_state_change, CONFIG_POWER_DOMAIN_LOG_LEVEL);
+
+/* Indicates the end of the onoff_power_states array */
+#define POWER_DOMAIN_DEVICE_ONOFF_STATE_MARKER 0xFF
+
+struct pd_deviceonoff_config {
+	uint8_t *onoff_power_states;
+};
+
+struct pd_visitor_context {
+	const struct device *domain;
+	enum pm_device_action action;
+};
+
+static int pd_domain_visitor(const struct device *dev, void *context)
+{
+	struct pd_visitor_context *visitor_context = context;
+
+	/* Only run action if the device is on the specified domain */
+	if (!dev->pm || (dev->pm_base->domain != visitor_context->domain)) {
+		return 0;
+	}
+
+	/* In case device is active, first suspend it before turning it off */
+	if ((visitor_context->action == PM_DEVICE_ACTION_TURN_OFF) &&
+	    (dev->pm_base->state == PM_DEVICE_STATE_ACTIVE)) {
+		(void)pm_device_action_run(dev, PM_DEVICE_ACTION_SUSPEND);
+	}
+	(void)pm_device_action_run(dev, visitor_context->action);
+	return 0;
+}
+
+static int pd_pm_action(const struct device *dev, enum pm_device_action action)
+{
+	const struct pd_deviceonoff_config *config = dev->config;
+	uint8_t i = 0;
+	/* Get the next power state that will be used */
+	enum pm_state state = pm_state_next_get(_current_cpu->id)->state;
+	struct pd_visitor_context context = {.domain = dev};
+
+	switch (action) {
+	case PM_DEVICE_ACTION_RESUME:
+		LOG_DBG("%s: resuming", dev->name);
+		while (config->onoff_power_states[i] != POWER_DOMAIN_DEVICE_ONOFF_STATE_MARKER) {
+			/* Check if we need do the turn on action for this state */
+			if (state == config->onoff_power_states[i]) {
+				/* Notify devices on the domain they are now powered */
+				context.action = PM_DEVICE_ACTION_TURN_ON;
+				(void)device_supported_foreach(dev, pd_domain_visitor, &context);
+				/* No need to go through the rest of the array of states */
+				break;
+			}
+			i++;
+		}
+		break;
+	case PM_DEVICE_ACTION_SUSPEND:
+		LOG_DBG("%s: suspending", dev->name);
+		while (config->onoff_power_states[i] != POWER_DOMAIN_DEVICE_ONOFF_STATE_MARKER) {
+			/* Check if need to do the turn off action for this state */
+			if (state == config->onoff_power_states[i]) {
+				/* Notify devices on the domain that power is going down */
+				context.action = PM_DEVICE_ACTION_TURN_OFF;
+				(void)device_supported_foreach(dev, pd_domain_visitor, &context);
+				/* No need to go through the rest of the array of states */
+				break;
+			}
+			i++;
+		}
+		break;
+	case PM_DEVICE_ACTION_TURN_ON:
+		break;
+	case PM_DEVICE_ACTION_TURN_OFF:
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+#define DT_DRV_COMPAT power_domain_soc_state_change
+
+#define PM_STATE_FROM_DT(i, node_id, prop_name)						\
+	COND_CODE_1(DT_NODE_HAS_STATUS(DT_PHANDLE_BY_IDX(node_id, prop_name, i), okay),	\
+		(PM_STATE_DT_INIT(DT_PHANDLE_BY_IDX(node_id, prop_name, i)),), ())
+
+#define POWER_DOMAIN_DEVICE_ONOFF_STATES(id, node_id)					\
+	uint8_t onoff_states_##id[] = {							\
+		LISTIFY(DT_PROP_LEN_OR(node_id, onoff_power_states, 0),			\
+			PM_STATE_FROM_DT, (), node_id, onoff_power_states)		\
+		POWER_DOMAIN_DEVICE_ONOFF_STATE_MARKER					\
+	};
+
+#define POWER_DOMAIN_DEVICE(id)								\
+	POWER_DOMAIN_DEVICE_ONOFF_STATES(id, DT_DRV_INST(id))				\
+											\
+	static const struct pd_deviceonoff_config pd_deviceonoff_##id##_cfg = {		\
+		.onoff_power_states = onoff_states_##id,				\
+	};										\
+	PM_DEVICE_DT_INST_DEFINE(id, pd_pm_action);					\
+	DEVICE_DT_INST_DEFINE(id, NULL, PM_DEVICE_DT_INST_GET(id),			\
+			      NULL, &pd_deviceonoff_##id##_cfg, PRE_KERNEL_1,		\
+			      CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(POWER_DOMAIN_DEVICE)
diff --git a/drivers/ptp_clock/Kconfig b/drivers/ptp_clock/Kconfig
index 74ab3e14eb8..f6479b65aab 100644
--- a/drivers/ptp_clock/Kconfig
+++ b/drivers/ptp_clock/Kconfig
@@ -1,7 +1,7 @@
 # Copyright (c) 2018 Intel Corporation.
 # SPDX-License-Identifier: Apache-2.0
 
-config PTP_CLOCK
+menuconfig PTP_CLOCK
 	bool "Precision Time Protocol (PTP) Clock drivers"
 	help
 	  Enable options for Precision Time Protocol Clock drivers.
diff --git a/drivers/pwm/CMakeLists.txt b/drivers/pwm/CMakeLists.txt
index e7596ed6d95..4c1b22e9c63 100644
--- a/drivers/pwm/CMakeLists.txt
+++ b/drivers/pwm/CMakeLists.txt
@@ -31,6 +31,7 @@ zephyr_library_sources_ifdef(CONFIG_PWM_NPCX		pwm_npcx.c)
 zephyr_library_sources_ifdef(CONFIG_PWM_XLNX_AXI_TIMER	pwm_xlnx_axi_timer.c)
 zephyr_library_sources_ifdef(CONFIG_PWM_MCUX_PWT 	pwm_mcux_pwt.c)
 zephyr_library_sources_ifdef(CONFIG_PWM_GECKO		pwm_gecko.c)
+zephyr_library_sources_ifdef(CONFIG_PWM_SILABS_SIWX91X	pwm_silabs_siwx91x.c)
 zephyr_library_sources_ifdef(CONFIG_PWM_GD32		pwm_gd32.c)
 zephyr_library_sources_ifdef(CONFIG_PWM_RCAR		pwm_rcar.c)
 zephyr_library_sources_ifdef(CONFIG_PWM_PCA9685 	pwm_pca9685.c)
@@ -49,6 +50,7 @@ zephyr_library_sources_ifdef(CONFIG_PWM_ENE_KB1200	pwm_ene_kb1200.c)
 zephyr_library_sources_ifdef(CONFIG_PWM_RENESAS_RA	pwm_renesas_ra.c)
 zephyr_library_sources_ifdef(CONFIG_PWM_INFINEON_CAT1	pwm_ifx_cat1.c)
 zephyr_library_sources_ifdef(CONFIG_PWM_FAKE	pwm_fake.c)
+zephyr_library_sources_ifdef(CONFIG_PWM_RENESAS_RZ_GPT	pwm_renesas_rz_gpt.c)
 zephyr_library_sources_ifdef(CONFIG_USERSPACE   pwm_handlers.c)
 zephyr_library_sources_ifdef(CONFIG_PWM_CAPTURE pwm_capture.c)
 zephyr_library_sources_ifdef(CONFIG_PWM_SHELL   pwm_shell.c)
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig
index f4ccd04b383..57a684ca2d1 100644
--- a/drivers/pwm/Kconfig
+++ b/drivers/pwm/Kconfig
@@ -84,6 +84,8 @@ source "drivers/pwm/Kconfig.mcux_pwt"
 
 source "drivers/pwm/Kconfig.gecko"
 
+source "drivers/pwm/Kconfig.siwx91x"
+
 source "drivers/pwm/Kconfig.gd32"
 
 source "drivers/pwm/Kconfig.rcar"
@@ -118,4 +120,6 @@ source "drivers/pwm/Kconfig.ifx_cat1"
 
 source "drivers/pwm/Kconfig.fake"
 
+source "drivers/pwm/Kconfig.renesas_rz"
+
 endif # PWM
diff --git a/drivers/pwm/Kconfig.renesas_rz b/drivers/pwm/Kconfig.renesas_rz
new file mode 100644
index 00000000000..2d9a9a831cc
--- /dev/null
+++ b/drivers/pwm/Kconfig.renesas_rz
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config PWM_RENESAS_RZ_GPT
+	bool "Renesas RZ General PWM Timer (GPT) PWM driver"
+	default y
+	depends on DT_HAS_RENESAS_RZ_GPT_PWM_ENABLED
+	select USE_RZ_FSP_GPT
+	help
+	  Enable the PWM driver for the Renesas RZ General PWM Timer (GPT).
diff --git a/drivers/pwm/Kconfig.siwx91x b/drivers/pwm/Kconfig.siwx91x
new file mode 100644
index 00000000000..6cf16ade50d
--- /dev/null
+++ b/drivers/pwm/Kconfig.siwx91x
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config PWM_SILABS_SIWX91X
+	bool "Silabs SiWx91x PWM driver"
+	default y
+	depends on DT_HAS_SILABS_SIWX91X_PWM_ENABLED
+	help
+	  Enable the PWM driver for the Silabs SiWx91x SoC series.
diff --git a/drivers/pwm/pwm_cc13xx_cc26xx_timer.c b/drivers/pwm/pwm_cc13xx_cc26xx_timer.c
index 19837ad08b8..ea07f706d25 100644
--- a/drivers/pwm/pwm_cc13xx_cc26xx_timer.c
+++ b/drivers/pwm/pwm_cc13xx_cc26xx_timer.c
@@ -34,6 +34,7 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_PWM_LOG_LEVEL);
 #define PWM_INITIAL_DUTY   0U /* initially off */
 
 struct pwm_cc13xx_cc26xx_data {
+	bool standby_disabled;
 };
 
 struct pwm_cc13xx_cc26xx_config {
@@ -56,14 +57,17 @@ static void write_value(const struct pwm_cc13xx_cc26xx_config *config, uint32_t
 }
 
 static int set_period_and_pulse(const struct pwm_cc13xx_cc26xx_config *config, uint32_t period,
-				uint32_t pulse)
+				uint32_t pulse, struct pwm_cc13xx_cc26xx_data *data)
 {
 	uint32_t match_value = pulse;
 
 	if (pulse == 0U) {
 		TimerDisable(config->gpt_base, TIMER_B);
 #ifdef CONFIG_PM
-		Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY);
+		if (data->standby_disabled) {
+			Power_releaseConstraint(PowerCC26XX_DISALLOW_STANDBY);
+			data->standby_disabled = false;
+		}
 #endif
 		match_value = period + 1;
 	}
@@ -86,7 +90,10 @@ static int set_period_and_pulse(const struct pwm_cc13xx_cc26xx_config *config, u
 
 	if (pulse > 0U) {
 #ifdef CONFIG_PM
-		Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY);
+		if (!data->standby_disabled) {
+			Power_setConstraint(PowerCC26XX_DISALLOW_STANDBY);
+			data->standby_disabled = true;
+		}
 #endif
 		TimerEnable(config->gpt_base, TIMER_B);
 	}
@@ -110,7 +117,7 @@ static int set_cycles(const struct device *dev, uint32_t channel, uint32_t perio
 		HWREG(config->gpt_base + GPT_O_CTL) |= GPT_CTL_TBPWML_NORMAL;
 	}
 
-	set_period_and_pulse(config, period, pulse);
+	set_period_and_pulse(config, period, pulse, dev->data);
 
 	return 0;
 }
@@ -223,7 +230,7 @@ static int init_pwm(const struct device *dev)
 	HWREG(config->gpt_base + GPT_O_TBMR) = GPT_TBMR_TBAMS_PWM | GPT_TBMR_TBMRSU_TOUPDATE |
 					       GPT_TBMR_TBPWMIE_EN | GPT_TBMR_TBMR_PERIODIC;
 
-	set_period_and_pulse(config, PWM_INITIAL_PERIOD, PWM_INITIAL_DUTY);
+	set_period_and_pulse(config, PWM_INITIAL_PERIOD, PWM_INITIAL_DUTY, dev->data);
 
 	return 0;
 }
diff --git a/drivers/pwm/pwm_led_esp32.c b/drivers/pwm/pwm_led_esp32.c
index d532423ad80..f2a46abd886 100644
--- a/drivers/pwm/pwm_led_esp32.c
+++ b/drivers/pwm/pwm_led_esp32.c
@@ -1,15 +1,15 @@
 /*
  * Copyright (c) 2017 Vitor Massaru Iha <vitor@massaru.org>
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #define DT_DRV_COMPAT espressif_esp32_ledc
 
-/* Include esp-idf headers first to avoid redefining BIT() macro */
 #include <hal/ledc_hal.h>
 #include <hal/ledc_types.h>
+#include <esp_clk_tree.h>
 
 #include <soc.h>
 #include <errno.h>
@@ -22,15 +22,13 @@
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(pwm_ledc_esp32, CONFIG_PWM_LOG_LEVEL);
 
-#if SOC_LEDC_SUPPORT_APB_CLOCK
-#define CLOCK_SOURCE LEDC_APB_CLK
-#elif SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
-#define CLOCK_SOURCE LEDC_SCLK
-#if defined(CONFIG_SOC_SERIES_ESP32C2)
-#define SCLK_CLK_FREQ MHZ(60)
-#elif defined(CONFIG_SOC_SERIES_ESP32C6)
-#define SCLK_CLK_FREQ MHZ(80)
+static const int global_clks[] = LEDC_LL_GLOBAL_CLOCKS;
+#if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
+static const int timer_specific_clks[] = LEDC_LL_TIMER_SPECIFIC_CLOCKS;
+static int lowspd_clks[ARRAY_SIZE(global_clks) + ARRAY_SIZE(timer_specific_clks)];
 #endif
+#if SOC_LEDC_SUPPORT_HS_MODE
+static const int highspd_clks[] = {LEDC_APB_CLK, LEDC_REF_TICK};
 #endif
 
 struct pwm_ledc_esp32_data {
@@ -46,7 +44,9 @@ struct pwm_ledc_esp32_channel_config {
 	const ledc_mode_t speed_mode;
 	uint8_t resolution;
 	ledc_clk_src_t clock_src;
+	uint32_t clock_src_hz;
 	uint32_t duty_val;
+	bool inverted;
 };
 
 struct pwm_ledc_esp32_config {
@@ -58,10 +58,9 @@ struct pwm_ledc_esp32_config {
 };
 
 static struct pwm_ledc_esp32_channel_config *get_channel_config(const struct device *dev,
-	int channel_id)
+								int channel_id)
 {
-	struct pwm_ledc_esp32_config *config =
-		(struct pwm_ledc_esp32_config *) dev->config;
+	struct pwm_ledc_esp32_config *config = (struct pwm_ledc_esp32_config *)dev->config;
 
 	for (uint8_t i = 0; i < config->channel_len; i++) {
 		if (config->channel_config[i].idx == channel_id) {
@@ -71,27 +70,31 @@ static struct pwm_ledc_esp32_channel_config *get_channel_config(const struct dev
 	return NULL;
 }
 
-static void pwm_led_esp32_low_speed_update(const struct device *dev, int speed_mode, int channel)
+static void pwm_led_esp32_start(struct pwm_ledc_esp32_data *data,
+				struct pwm_ledc_esp32_channel_config *channel)
 {
-	struct pwm_ledc_esp32_data *data = (struct pwm_ledc_esp32_data *const)(dev)->data;
+	ledc_hal_set_sig_out_en(&data->hal, channel->channel_num, true);
+	ledc_hal_set_duty_start(&data->hal, channel->channel_num, true);
 
-	if (speed_mode == LEDC_LOW_SPEED_MODE) {
-		ledc_hal_ls_channel_update(&data->hal, channel);
+	if (channel->speed_mode == LEDC_LOW_SPEED_MODE) {
+		ledc_hal_ls_channel_update(&data->hal, channel->channel_num);
 	}
 }
 
-static void pwm_led_esp32_update_duty(const struct device *dev, int speed_mode, int channel)
+static void pwm_led_esp32_stop(struct pwm_ledc_esp32_data *data,
+			       struct pwm_ledc_esp32_channel_config *channel, bool idle_level)
 {
-	struct pwm_ledc_esp32_data *data = (struct pwm_ledc_esp32_data *const)(dev)->data;
-
-	ledc_hal_set_sig_out_en(&data->hal, channel, true);
-	ledc_hal_set_duty_start(&data->hal, channel, true);
+	ledc_hal_set_idle_level(&data->hal, channel->channel_num, idle_level);
+	ledc_hal_set_sig_out_en(&data->hal, channel->channel_num, false);
+	ledc_hal_set_duty_start(&data->hal, channel->channel_num, false);
 
-	pwm_led_esp32_low_speed_update(dev, speed_mode, channel);
+	if (channel->speed_mode == LEDC_LOW_SPEED_MODE) {
+		ledc_hal_ls_channel_update(&data->hal, channel->channel_num);
+	}
 }
 
 static void pwm_led_esp32_duty_set(const struct device *dev,
-	struct pwm_ledc_esp32_channel_config *channel)
+				   struct pwm_ledc_esp32_channel_config *channel)
 {
 	struct pwm_ledc_esp32_data *data = (struct pwm_ledc_esp32_data *const)(dev)->data;
 
@@ -101,31 +104,6 @@ static void pwm_led_esp32_duty_set(const struct device *dev,
 	ledc_hal_set_duty_num(&data->hal, channel->channel_num, 1);
 	ledc_hal_set_duty_cycle(&data->hal, channel->channel_num, 1);
 	ledc_hal_set_duty_scale(&data->hal, channel->channel_num, 0);
-	pwm_led_esp32_low_speed_update(dev, channel->speed_mode, channel->channel_num);
-	pwm_led_esp32_update_duty(dev, channel->speed_mode, channel->channel_num);
-}
-
-static int pwm_led_esp32_configure_pinctrl(const struct device *dev)
-{
-	int ret;
-	struct pwm_ledc_esp32_config *config = (struct pwm_ledc_esp32_config *) dev->config;
-
-	ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
-	if (ret < 0) {
-		LOG_ERR("PWM pinctrl setup failed (%d)", ret);
-		return ret;
-	}
-	return 0;
-}
-
-static void pwm_led_esp32_bind_channel_timer(const struct device *dev,
-	struct pwm_ledc_esp32_channel_config *channel)
-{
-	struct pwm_ledc_esp32_data *data = (struct pwm_ledc_esp32_data *const)(dev)->data;
-
-	ledc_hal_bind_channel_timer(&data->hal, channel->channel_num, channel->timer_num);
-
-	pwm_led_esp32_low_speed_update(dev, channel->speed_mode, channel->channel_num);
 }
 
 static int pwm_led_esp32_calculate_max_resolution(struct pwm_ledc_esp32_channel_config *channel)
@@ -134,74 +112,65 @@ static int pwm_led_esp32_calculate_max_resolution(struct pwm_ledc_esp32_channel_
 	 * Max duty resolution can be obtained with
 	 * max_res = log2(CLK_FREQ/FREQ)
 	 */
-#if SOC_LEDC_SUPPORT_APB_CLOCK
-	uint64_t clock_freq = channel->clock_src == LEDC_APB_CLK ? APB_CLK_FREQ : REF_CLK_FREQ;
-#elif SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
-	uint64_t clock_freq = SCLK_CLK_FREQ;
-#endif
-	uint32_t max_precision_n = clock_freq/channel->freq;
+	uint32_t max_precision_n = channel->clock_src_hz / channel->freq;
 
 	for (uint8_t i = 0; i <= SOC_LEDC_TIMER_BIT_WIDTH; i++) {
 		max_precision_n /= 2;
 		if (!max_precision_n) {
-			channel->resolution =  i;
+			channel->resolution = i;
 			return 0;
 		}
 	}
 	return -EINVAL;
-
 }
 
 static int pwm_led_esp32_timer_config(struct pwm_ledc_esp32_channel_config *channel)
 {
-	/**
-	 * Calculate max resolution based on the given frequency and the pwm clock.
-	 *
-	 * There are 2 clock resources for PWM:
-	 *
-	 * 1. APB_CLK (80MHz)
-	 * 2. REF_TICK (1MHz)
-	 *
-	 * The low speed timers can be sourced from:
-	 *
-	 * 1. APB_CLK (80MHz)
-	 * 2. RTC_CLK (8Mhz)
-	 *
-	 * The APB_CLK is mostly used
-	 *
-	 * First we try to find the largest resolution using the APB_CLK source.
-	 * If the given frequency doesn't support it, we move to the next clock source.
-	 */
+	const int *clock_src;
+	int clock_src_num;
 
-#if SOC_LEDC_SUPPORT_APB_CLOCK
-	channel->clock_src = LEDC_APB_CLK;
+	if (channel->speed_mode == LEDC_LOW_SPEED_MODE) {
+#ifdef SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
+		clock_src = lowspd_clks;
+		clock_src_num = ARRAY_SIZE(lowspd_clks);
+#else
+		clock_src = global_clks;
+		clock_src_num = ARRAY_SIZE(global_clks);
 #endif
-	if (!pwm_led_esp32_calculate_max_resolution(channel)) {
-		return 0;
 	}
-
-#if SOC_LEDC_SUPPORT_REF_TICK
-	channel->clock_src = LEDC_REF_TICK;
-	if (!pwm_led_esp32_calculate_max_resolution(channel)) {
-		return 0;
+#ifdef SOC_LEDC_SUPPORT_HS_MODE
+	else {
+		clock_src = highspd_clks;
+		clock_src_num = ARRAY_SIZE(highspd_clks);
 	}
 #endif
 
 	/**
-	 * ESP32 - S2,S3 and C3 variants have only 14 bits counter.
-	 * where as the plain ESP32 variant has 20 bits counter.
-	 * application failed to set low frequency(1Hz) in S2, S3 and C3 variants.
-	 * to get very low frequencies on these variants,
-	 * frequency needs to be tuned with 18 bits clock divider.
-	 * so select the slow clock source (1MHz) with highest counter resolution.
-	 * this can be handled on the func 'pwm_led_esp32_timer_set' with 'prescaler'.
+	 * Calculate max resolution based on the given frequency and the pwm clock.
+	 * Try each clock source available depending on the device and channel type.
+	 */
+	for (int i = 0; i < clock_src_num; i++) {
+		channel->clock_src = clock_src[i];
+		esp_clk_tree_src_get_freq_hz(channel->clock_src,
+					     ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
+					     &channel->clock_src_hz);
+		if (!pwm_led_esp32_calculate_max_resolution(channel)) {
+			return 0;
+		}
+	}
+
+	/* Frequency is too low for this device, so even though best precision can't
+	 * be achieved we can set max resolution and consider that the previous
+	 * loop selects clock from fastest to slowest, so this is the best
+	 * configuration achievable.
 	 */
 	channel->resolution = SOC_LEDC_TIMER_BIT_WIDTH;
+
 	return 0;
 }
 
 static int pwm_led_esp32_timer_set(const struct device *dev,
-	struct pwm_ledc_esp32_channel_config *channel)
+				   struct pwm_ledc_esp32_channel_config *channel)
 {
 	int prescaler = 0;
 	uint32_t precision = (0x1 << channel->resolution);
@@ -209,30 +178,7 @@ static int pwm_led_esp32_timer_set(const struct device *dev,
 
 	__ASSERT_NO_MSG(channel->freq > 0);
 
-	switch (channel->clock_src) {
-#if SOC_LEDC_SUPPORT_APB_CLOCK
-	case LEDC_APB_CLK:
-		/** This expression comes from ESP32 Espressif's Technical Reference
-		 * Manual chapter 13.2.2 Timers.
-		 * div_num is a fixed point value (Q10.8).
-		 */
-		prescaler = ((uint64_t) APB_CLK_FREQ << 8) / channel->freq / precision;
-	break;
-#endif
-#if SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
-	case LEDC_SCLK:
-		prescaler = ((uint64_t) SCLK_CLK_FREQ << 8) / channel->freq / precision;
-	break;
-#endif
-#if SOC_LEDC_SUPPORT_REF_TICK
-	case LEDC_REF_TICK:
-		prescaler = ((uint64_t) REF_CLK_FREQ << 8) / channel->freq / precision;
-	break;
-#endif
-	default:
-		LOG_ERR("Invalid clock source (%d)", channel->clock_src);
-		return -EINVAL;
-	}
+	prescaler = ((uint64_t)channel->clock_src_hz << 8) / channel->freq / precision;
 
 	if (prescaler < 0x100 || prescaler > 0x3FFFF) {
 		LOG_ERR("Prescaler out of range: %#X", prescaler);
@@ -251,14 +197,16 @@ static int pwm_led_esp32_timer_set(const struct device *dev,
 		ledc_hal_ls_timer_update(&data->hal, channel->timer_num);
 	}
 
-	/* reset low speed timer */
-	ledc_hal_timer_rst(&data->hal, channel->timer_num);
+	LOG_DBG("channel_num=%d, speed_mode=%d, timer_num=%d, clock_src=%d, prescaler=%d, "
+		"resolution=%d\n",
+		channel->channel_num, channel->speed_mode, channel->timer_num, channel->clock_src,
+		prescaler, channel->resolution);
 
 	return 0;
 }
 
-static int pwm_led_esp32_get_cycles_per_sec(const struct device *dev,
-					    uint32_t channel_idx, uint64_t *cycles)
+static int pwm_led_esp32_get_cycles_per_sec(const struct device *dev, uint32_t channel_idx,
+					    uint64_t *cycles)
 {
 	struct pwm_ledc_esp32_channel_config *channel = get_channel_config(dev, channel_idx);
 
@@ -267,81 +215,126 @@ static int pwm_led_esp32_get_cycles_per_sec(const struct device *dev,
 		return -EINVAL;
 	}
 
-#if SOC_LEDC_SUPPORT_APB_CLOCK
-	*cycles = channel->clock_src == LEDC_APB_CLK ? APB_CLK_FREQ : REF_CLK_FREQ;
-#elif SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
-	*cycles = SCLK_CLK_FREQ;
-#endif
+	*cycles = (uint64_t)channel->clock_src_hz;
 
 	return 0;
 }
 
-static int pwm_led_esp32_set_cycles(const struct device *dev, uint32_t channel_idx,
-				    uint32_t period_cycles,
-				    uint32_t pulse_cycles, pwm_flags_t flags)
+static int pwm_led_esp32_channel_update_frequency(const struct device *dev,
+						  struct pwm_ledc_esp32_channel_config *channel,
+						  uint32_t period_cycles)
 {
-	int ret;
+	const struct pwm_ledc_esp32_config *config = dev->config;
+	uint32_t current_freq = channel->freq;
 	uint64_t clk_freq;
-	struct pwm_ledc_esp32_data *data = (struct pwm_ledc_esp32_data *const)(dev)->data;
-	struct pwm_ledc_esp32_channel_config *channel = get_channel_config(dev, channel_idx);
+	int ret;
 
-	if (!channel) {
-		LOG_ERR("Error getting channel %d", channel_idx);
-		return -EINVAL;
-	}
+	ret = pwm_led_esp32_get_cycles_per_sec(dev, channel->idx, &clk_freq);
 
-	/* Update PWM frequency according to period_cycles */
-	ret = pwm_led_esp32_get_cycles_per_sec(dev, channel_idx, &clk_freq);
 	if (ret < 0) {
 		return ret;
 	}
 
-	channel->freq = (uint32_t) (clk_freq/period_cycles);
+	channel->freq = (uint32_t)(clk_freq / period_cycles);
+
 	if (!channel->freq) {
 		channel->freq = 1;
 	}
 
-	k_sem_take(&data->cmd_sem, K_FOREVER);
-
-	ledc_hal_init(&data->hal, channel->speed_mode);
+	if (channel->freq == current_freq) {
+		/* No need to reconfigure timer */
+		return 0;
+	}
 
-	ret = pwm_led_esp32_timer_config(channel);
-	if (ret < 0) {
-		k_sem_give(&data->cmd_sem);
-		return ret;
+	/* Check whether another channel is using the same timer.
+	 * Timers can only be shared if the same frequency is used, so
+	 * first set operation will take precedence.
+	 */
+	for (int i = 0; i < config->channel_len; ++i) {
+		struct pwm_ledc_esp32_channel_config *ch = &config->channel_config[i];
+
+		if (ch->freq && (channel->channel_num != ch->channel_num) &&
+			(channel->timer_num == ch->timer_num) &&
+			(channel->speed_mode == ch->speed_mode) &&
+			(channel->freq != ch->freq)) {
+			LOG_ERR("Timer can't be shared and different frequency be "
+				"requested");
+			channel->freq = 0;
+			return -EINVAL;
+		}
 	}
 
+	pwm_led_esp32_timer_config(channel);
+
 	ret = pwm_led_esp32_timer_set(dev, channel);
+
 	if (ret < 0) {
-		k_sem_give(&data->cmd_sem);
+		LOG_ERR("Error setting timer for channel %d", channel->idx);
 		return ret;
 	}
 
-	pwm_led_esp32_bind_channel_timer(dev, channel);
+	return 0;
+}
 
-	/* Update PWM duty  */
+static int pwm_led_esp32_set_cycles(const struct device *dev, uint32_t channel_idx,
+				    uint32_t period_cycles, uint32_t pulse_cycles,
+				    pwm_flags_t flags)
+{
+	struct pwm_ledc_esp32_data *data = (struct pwm_ledc_esp32_data *const)(dev)->data;
+	struct pwm_ledc_esp32_channel_config *channel = get_channel_config(dev, channel_idx);
+	int ret = 0;
+
+	if (!channel) {
+		LOG_ERR("Error getting channel %d", channel_idx);
+		return -EINVAL;
+	}
 
-	double duty_cycle = (double) pulse_cycles / (double) period_cycles;
+	k_sem_take(&data->cmd_sem, K_FOREVER);
 
-	channel->duty_val = (uint32_t)((double) (1 << channel->resolution) * duty_cycle);
+	if (flags & PWM_POLARITY_INVERTED) {
+		pulse_cycles = period_cycles - pulse_cycles;
+		channel->inverted = true;
+	} else {
+		channel->inverted = false;
+	}
 
-	pwm_led_esp32_duty_set(dev, channel);
+	ledc_hal_init(&data->hal, channel->speed_mode);
+
+	if ((pulse_cycles == period_cycles) || (pulse_cycles == 0)) {
+		/* For duty 0% and 100% stop PWM, set output level and return */
+		pwm_led_esp32_stop(data, channel, (pulse_cycles == period_cycles));
+		goto sem_give;
+	}
+
+	ret = pwm_led_esp32_channel_update_frequency(dev, channel, period_cycles);
 
-	ret = pwm_led_esp32_configure_pinctrl(dev);
 	if (ret < 0) {
-		k_sem_give(&data->cmd_sem);
-		return ret;
+		LOG_ERR("Error updating frequency of channel %d", channel_idx);
+		goto sem_give;
 	}
 
+	/* Update PWM duty  */
+
+	double duty_cycle = (double)pulse_cycles / (double)period_cycles;
+
+	channel->duty_val = (uint32_t)((double)(1 << channel->resolution) * duty_cycle);
+
+	pwm_led_esp32_duty_set(dev, channel);
+
+	pwm_led_esp32_start(data, channel);
+
+sem_give:
 	k_sem_give(&data->cmd_sem);
 
 	return ret;
 }
 
-
 int pwm_led_esp32_init(const struct device *dev)
 {
 	const struct pwm_ledc_esp32_config *config = dev->config;
+	struct pwm_ledc_esp32_data *data = dev->data;
+	struct pwm_ledc_esp32_channel_config *channel;
+	int ret = 0;
 
 	if (!device_is_ready(config->clock_dev)) {
 		LOG_ERR("clock control device not ready");
@@ -351,6 +344,45 @@ int pwm_led_esp32_init(const struct device *dev)
 	/* Enable peripheral */
 	clock_control_on(config->clock_dev, config->clock_subsys);
 
+#if SOC_LEDC_HAS_TIMER_SPECIFIC_MUX
+	/* Combine clock sources to include timer specific sources */
+	memcpy(lowspd_clks, global_clks, sizeof(global_clks));
+	memcpy(&lowspd_clks[ARRAY_SIZE(global_clks)], timer_specific_clks,
+	       sizeof(timer_specific_clks));
+#endif
+
+	for (int i = 0; i < config->channel_len; ++i) {
+		channel = &config->channel_config[i];
+
+		ledc_hal_init(&data->hal, channel->speed_mode);
+
+		if (channel->speed_mode == LEDC_LOW_SPEED_MODE) {
+			channel->clock_src = global_clks[0];
+			ledc_hal_set_slow_clk_sel(&data->hal, channel->clock_src);
+		}
+#ifdef SOC_LEDC_SUPPORT_HS_MODE
+		else {
+			channel->clock_src = highspd_clks[0];
+		}
+#endif
+		ledc_hal_set_clock_source(&data->hal, channel->timer_num, channel->clock_src);
+
+		esp_clk_tree_src_get_freq_hz(channel->clock_src,
+					     ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED,
+					     &channel->clock_src_hz);
+
+		ledc_hal_bind_channel_timer(&data->hal, channel->channel_num, channel->timer_num);
+		pwm_led_esp32_stop(data, channel, channel->inverted);
+		ledc_hal_timer_rst(&data->hal, channel->timer_num);
+	}
+
+	ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
+
+	if (ret < 0) {
+		LOG_ERR("PWM pinctrl setup failed (%d)", ret);
+		return ret;
+	}
+
 	return 0;
 }
 
@@ -361,20 +393,18 @@ static DEVICE_API(pwm, pwm_led_esp32_api) = {
 
 PINCTRL_DT_INST_DEFINE(0);
 
-#define CHANNEL_CONFIG(node_id)                                                \
-	{                                                                      \
-		.idx = DT_REG_ADDR(node_id),                                   \
-		.channel_num = DT_REG_ADDR(node_id) % 8,                       \
-		.timer_num = DT_PROP(node_id, timer),                          \
-		.speed_mode = DT_REG_ADDR(node_id) < SOC_LEDC_CHANNEL_NUM      \
-				      ? LEDC_LOW_SPEED_MODE                    \
-				      : !LEDC_LOW_SPEED_MODE,                  \
-		.clock_src = CLOCK_SOURCE,                                     \
+#define CHANNEL_CONFIG(node_id)                                                                    \
+	{                                                                                          \
+		.idx = DT_REG_ADDR(node_id),                                                       \
+		.channel_num = DT_REG_ADDR(node_id) % 8,                                           \
+		.timer_num = DT_PROP(node_id, timer),                                              \
+		.speed_mode = DT_REG_ADDR(node_id) < SOC_LEDC_CHANNEL_NUM ? LEDC_LOW_SPEED_MODE    \
+									  : !LEDC_LOW_SPEED_MODE,  \
+		.inverted = DT_PROP(node_id, inverted),                                            \
 	},
 
 static struct pwm_ledc_esp32_channel_config channel_config[] = {
-	DT_INST_FOREACH_CHILD(0, CHANNEL_CONFIG)
-};
+	DT_INST_FOREACH_CHILD(0, CHANNEL_CONFIG)};
 
 static struct pwm_ledc_esp32_config pwm_ledc_esp32_config = {
 	.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
@@ -391,9 +421,5 @@ static struct pwm_ledc_esp32_data pwm_ledc_esp32_data = {
 	.cmd_sem = Z_SEM_INITIALIZER(pwm_ledc_esp32_data.cmd_sem, 1, 1),
 };
 
-DEVICE_DT_INST_DEFINE(0, &pwm_led_esp32_init, NULL,
-			&pwm_ledc_esp32_data,
-			&pwm_ledc_esp32_config,
-			POST_KERNEL,
-			CONFIG_PWM_INIT_PRIORITY,
-			&pwm_led_esp32_api);
+DEVICE_DT_INST_DEFINE(0, &pwm_led_esp32_init, NULL, &pwm_ledc_esp32_data, &pwm_ledc_esp32_config,
+		      POST_KERNEL, CONFIG_PWM_INIT_PRIORITY, &pwm_led_esp32_api);
diff --git a/drivers/pwm/pwm_mc_esp32.c b/drivers/pwm/pwm_mc_esp32.c
index b7bb59f1cd5..2e15355a642 100644
--- a/drivers/pwm/pwm_mc_esp32.c
+++ b/drivers/pwm/pwm_mc_esp32.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,21 +19,11 @@
 #include <zephyr/drivers/clock_control.h>
 #include <esp_clk_tree.h>
 #ifdef CONFIG_PWM_CAPTURE
-#if defined(CONFIG_RISCV)
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-#else
 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
-#endif
 #endif /* CONFIG_PWM_CAPTURE */
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(mcpwm_esp32, CONFIG_PWM_LOG_LEVEL);
 
-#if defined(CONFIG_RISCV)
-#define ISR_HANDLER isr_handler_t
-#else
-#define ISR_HANDLER intr_handler_t
-#endif
-
 #ifdef CONFIG_PWM_CAPTURE
 #define SKIP_IRQ_NUM        4U
 #define CAP_INT_MASK        7U
@@ -554,7 +544,7 @@ static DEVICE_API(pwm, mcpwm_esp32_api) = {
 				ESP_PRIO_TO_FLAGS(DT_INST_IRQ_BY_IDX(idx, 0, priority)) |          \
 				ESP_INT_FLAGS_CHECK(DT_INST_IRQ_BY_IDX(idx, 0, flags)) |          \
 					ESP_INTR_FLAG_IRAM,                                        \
-				(ISR_HANDLER)mcpwm_esp32_isr, (void *)dev, NULL);                  \
+				(intr_handler_t)mcpwm_esp32_isr, (void *)dev, NULL);               \
 		return ret;                                                                \
 	}
 #define CAPTURE_INIT(idx) .irq_config_func = mcpwm_esp32_irq_config_func_##idx
diff --git a/drivers/pwm/pwm_mcux_tpm.c b/drivers/pwm/pwm_mcux_tpm.c
index ae869c51815..c647d673858 100644
--- a/drivers/pwm/pwm_mcux_tpm.c
+++ b/drivers/pwm/pwm_mcux_tpm.c
@@ -1,6 +1,6 @@
 /*
  * Copyright 2019 Henrik Brix Andersen <henrik@brixandersen.dk>
- * Copyright 2020, 2024 NXP
+ * Copyright 2020, 2024-2025 NXP
  *
  * Heavily based on pwm_mcux_ftm.c, which is:
  * Copyright (c) 2017, NXP
@@ -20,6 +20,10 @@
 
 #include <zephyr/logging/log.h>
 
+#if defined(CONFIG_SOC_MIMX9596)
+#include <zephyr/dt-bindings/clock/imx95_clock.h>
+#endif
+
 LOG_MODULE_REGISTER(pwm_mcux_tpm, CONFIG_PWM_LOG_LEVEL);
 
 #if defined(TPM0)
@@ -51,29 +55,22 @@ static int mcux_tpm_set_cycles(const struct device *dev, uint32_t channel,
 {
 	const struct mcux_tpm_config *config = dev->config;
 	struct mcux_tpm_data *data = dev->data;
-	uint8_t duty_cycle;
-
-	if (period_cycles == 0U) {
-		LOG_ERR("Channel can not be set to inactive level");
-		return -ENOTSUP;
-	}
 
 	if (channel >= config->channel_count) {
 		LOG_ERR("Invalid channel");
 		return -ENOTSUP;
 	}
 
-	duty_cycle = pulse_cycles * 100U / period_cycles;
-	data->channel[channel].dutyCyclePercent = duty_cycle;
+	if (period_cycles == 0 || period_cycles == TPM_MAX_COUNTER_VALUE(base)) {
+		return -ENOTSUP;
+	}
 
-	if ((flags & PWM_POLARITY_INVERTED) == 0) {
-		data->channel[channel].level = kTPM_HighTrue;
-	} else {
-		data->channel[channel].level = kTPM_LowTrue;
+	if ((TPM_MAX_COUNTER_VALUE(base) == 0xFFFFU) &&
+	    (pulse_cycles > TPM_MAX_COUNTER_VALUE(base))) {
+		return -ENOTSUP;
 	}
 
-	LOG_DBG("pulse_cycles=%d, period_cycles=%d, duty_cycle=%d, flags=%d",
-		pulse_cycles, period_cycles, duty_cycle, flags);
+	LOG_DBG("pulse_cycles=%d, period_cycles=%d, flags=%d", pulse_cycles, period_cycles, flags);
 
 	if (period_cycles != data->period_cycles) {
 		uint32_t pwm_freq;
@@ -102,6 +99,9 @@ static int mcux_tpm_set_cycles(const struct device *dev, uint32_t channel,
 
 		TPM_StopTimer(config->base);
 
+		/* Set counter back to zero */
+		config->base->CNT = 0;
+
 		status = TPM_SetupPwm(config->base, data->channel,
 				      config->channel_count, config->mode,
 				      pwm_freq, data->clock_freq);
@@ -111,13 +111,24 @@ static int mcux_tpm_set_cycles(const struct device *dev, uint32_t channel,
 			return -ENOTSUP;
 		}
 		TPM_StartTimer(config->base, config->tpm_clock_source);
-	} else {
-		TPM_UpdateChnlEdgeLevelSelect(config->base, channel,
-					      data->channel[channel].level);
-		TPM_UpdatePwmDutycycle(config->base, channel, config->mode,
-				       duty_cycle);
 	}
 
+	if ((flags & PWM_POLARITY_INVERTED) == 0 &&
+		   data->channel[channel].level != kTPM_HighTrue) {
+		data->channel[channel].level = kTPM_HighTrue;
+		TPM_UpdateChnlEdgeLevelSelect(config->base, channel, kTPM_HighTrue);
+	} else if ((flags & PWM_POLARITY_INVERTED) != 0 &&
+		   data->channel[channel].level != kTPM_LowTrue) {
+		data->channel[channel].level = kTPM_LowTrue;
+		TPM_UpdateChnlEdgeLevelSelect(config->base, channel, kTPM_LowTrue);
+	}
+
+	if (pulse_cycles == period_cycles) {
+		pulse_cycles = period_cycles + 1U;
+	}
+
+	config->base->CONTROLS[channel].CnV = pulse_cycles;
+
 	return 0;
 }
 
@@ -151,10 +162,18 @@ static int mcux_tpm_init(const struct device *dev)
 		return -ENODEV;
 	}
 
-	if (clock_control_on(config->clock_dev, config->clock_subsys)) {
-		LOG_ERR("Could not turn on clock");
-		return -EINVAL;
+#if defined(CONFIG_SOC_MIMX9596)
+	/* IMX9596 AON and WAKEUP clocks aren't controllable */
+	if (config->clock_subsys != (clock_control_subsys_t)IMX95_CLK_BUSWAKEUP &&
+	    config->clock_subsys != (clock_control_subsys_t)IMX95_CLK_BUSAON) {
+#endif
+		if (clock_control_on(config->clock_dev, config->clock_subsys)) {
+			LOG_ERR("Could not turn on clock");
+			return -EINVAL;
+		}
+#if defined(CONFIG_SOC_MIMX9596)
 	}
+#endif
 
 	if (clock_control_get_rate(config->clock_dev, config->clock_subsys,
 				   &data->clock_freq)) {
diff --git a/drivers/pwm/pwm_nxp_s32_emios.c b/drivers/pwm/pwm_nxp_s32_emios.c
index 34cd5c3b0a5..2547892d56c 100644
--- a/drivers/pwm/pwm_nxp_s32_emios.c
+++ b/drivers/pwm/pwm_nxp_s32_emios.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2023 NXP
+ * Copyright 2023-2024 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,6 +8,7 @@
 #include <zephyr/drivers/pwm.h>
 #include <zephyr/drivers/pinctrl.h>
 #include <zephyr/drivers/clock_control.h>
+#include <zephyr/irq.h>
 
 #include <Emios_Mcl_Ip.h>
 #include <Emios_Pwm_Ip.h>
@@ -22,40 +23,58 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_PWM_LOG_LEVEL);
 
 #define DT_DRV_COMPAT	nxp_s32_emios_pwm
 
+#if !defined(EMIOS_PWM_IP_NUM_OF_CHANNELS_USED)
+#define EMIOS_PWM_IP_NUM_OF_CHANNELS_USED EMIOS_PWM_IP_NUM_OF_CHANNELS_USED_U8
+#endif
+
 /*
  * Need to fill to this array at runtime, cannot do at build time like
  * the HAL over configuration tool due to limitation of the integration
  */
 #if EMIOS_PWM_IP_USED
 extern uint8 eMios_Pwm_Ip_IndexInChState[EMIOS_PWM_IP_INSTANCE_COUNT][EMIOS_PWM_IP_CHANNEL_COUNT];
+#define EMIOS_PWM_MASTER_CHANNEL(channel, bus)					\
+	((bus == EMIOS_PWM_IP_BUS_A) ? 23 :					\
+	((bus == EMIOS_PWM_IP_BUS_F) ? 22 :					\
+	((bus == EMIOS_PWM_IP_BUS_BCDE) ? ((channel >> 3) * 8) : channel)))
 #endif
 
 #ifdef CONFIG_PWM_CAPTURE
 extern uint8 eMios_Icu_Ip_IndexInChState[EMIOS_ICU_IP_INSTANCE_COUNT][EMIOS_ICU_IP_NUM_OF_CHANNELS];
 
+#define EMIOS_ICU_MASTER_CHANNEL(channel, bus)					\
+	((bus == EMIOS_ICU_BUS_A) ? 23 :					\
+	((bus == EMIOS_ICU_BUS_F) ? 22 :					\
+	((bus == EMIOS_ICU_BUS_DIVERSE) ? ((channel >> 3) * 8) : channel)))
+
 /* We need maximum three edges for measure both period and cycle */
 #define MAX_NUM_EDGE 3
+#endif
 
-struct pwm_nxp_s32_capture_data {
-	bool continuous;
+struct pwm_nxp_s32_channel_data {
 	bool inverted;
+	uint8_t master_channel;
+
+#if EMIOS_PWM_IP_USED
+	uint32_t curr_period;
+#endif
+
+#ifdef CONFIG_PWM_CAPTURE
+	bool continuous;
 	bool pulse_capture;
 	bool period_capture;
 	void *user_data;
 	pwm_capture_callback_handler_t callback;
 	eMios_Icu_ValueType edge_buff[MAX_NUM_EDGE];
-};
 #endif
+};
 
 struct pwm_nxp_s32_data {
 	uint32_t emios_clk;
 #if EMIOS_PWM_IP_USED
 	uint8_t start_pwm_ch;
 #endif
-
-#ifdef CONFIG_PWM_CAPTURE
-	struct pwm_nxp_s32_capture_data capture[EMIOS_ICU_IP_NUM_OF_CHANNELS];
-#endif
+	struct pwm_nxp_s32_channel_data ch_data[eMIOS_CH_UC_UC_COUNT];
 };
 
 #if EMIOS_PWM_IP_USED
@@ -83,69 +102,237 @@ struct pwm_nxp_s32_config {
 
 #if EMIOS_PWM_IP_USED
 #ifdef EMIOS_PWM_IP_MODE_OPWFMB_USED
-static int pwm_nxp_s32_set_cycles_internal_timebase(uint8_t instance, uint32_t channel,
-						    uint32_t period_cycles, uint32_t pulse_cycles)
+static int pwm_nxp_s32_set_cycles_opwfmb(const struct device *dev, uint32_t channel,
+					uint32_t period_cycles, uint32_t pulse_cycles,
+					pwm_flags_t flags)
 {
-	bool need_update = false;
+	const struct pwm_nxp_s32_config *config = dev->config;
+	struct pwm_nxp_s32_data *data = dev->data;
+	struct pwm_nxp_s32_channel_data *ch_data = &data->ch_data[channel];
 
-	if ((period_cycles > EMIOS_PWM_IP_MAX_CNT_VAL) ||
-		(period_cycles <= EMIOS_PWM_IP_MIN_CNT_VAL)) {
-		LOG_ERR("period_cycles is out of range");
-		return -EINVAL;
-	}
+	Emios_Pwm_Ip_PolarityType polarity;
 
-	if (Emios_Pwm_Ip_GetPeriod(instance, channel) != period_cycles) {
-		Emios_Pwm_Ip_SetPeriod(instance, channel, period_cycles);
-		need_update = true;
-	}
+	unsigned int key;
+
+	if ((ch_data->inverted != flags) || (!ch_data->curr_period)) {
+		/* If PWM flag is changed or this is the first time PWM channel is configured */
+		polarity = (flags & PWM_POLARITY_MASK) ? EMIOS_PWM_IP_ACTIVE_LOW :
+							 EMIOS_PWM_IP_ACTIVE_HIGH;
 
-	if (Emios_Pwm_Ip_GetDutyCycle(instance, channel) != pulse_cycles) {
-		need_update = true;
-		if (Emios_Pwm_Ip_SetDutyCycle(instance, channel, pulse_cycles)) {
-			LOG_ERR("Cannot set pulse cycles");
-			return -EIO;
+		config->base->CH.UC[channel].C &= ~(eMIOS_C_MODE_MASK |
+						    eMIOS_C_EDPOL_MASK);
+		config->base->CH.UC[channel].A = pulse_cycles;
+		config->base->CH.UC[channel].B = period_cycles;
+
+		/*
+		 * When entering OPWFMB mode, Output = Cn[EDPOL]. Unless 100% pulse cycle is
+		 * expected, Cn[EDPOL] is set to complement value (i.e 0 if active high and
+		 * 1 if active low).
+		 */
+		if (pulse_cycles) {
+			config->base->CH.UC[channel].C |= eMIOS_C_EDPOL(polarity);
+		} else {
+			config->base->CH.UC[channel].C |= eMIOS_C_EDPOL(!polarity);
 		}
-	}
 
-	if (need_update) {
-		/* Force match so that the new period, duty cycle takes effect immediately */
-		Emios_Pwm_Ip_ForceMatchTrailingEdge(instance, channel, true);
+		key = irq_lock();
+		config->base->CH.UC[channel].C |= eMIOS_C_MODE(EMIOS_PWM_IP_MODE_OPWFMB_FLAG);
+
+		if (pulse_cycles) {
+			/* Restore expected value for Cn[EDPOL] */
+			config->base->CH.UC[channel].C = (config->base->CH.UC[channel].C &
+							~(eMIOS_C_EDPOL_MASK)) |
+							eMIOS_C_EDPOL(!polarity);
+		}
+		irq_unlock(key);
+
+		ch_data->curr_period = period_cycles;
+		ch_data->inverted = flags;
+	} else {
+		key = irq_lock();
+		config->base->CH.UC[channel].A = pulse_cycles;
+		config->base->CH.UC[channel].B = period_cycles;
+		irq_unlock(key);
 	}
 
 	return 0;
 }
 #endif
 
-#if defined(EMIOS_PWM_IP_MODE_OPWMCB_USED) || defined(EMIOS_PWM_IP_MODE_OPWMB_USED)
-static int pwm_nxp_s32_set_cycles_external_timebase(uint8_t instance, uint32_t channel,
-						    uint32_t period_cycles, uint32_t pulse_cycles)
+#if defined(EMIOS_PWM_IP_MODE_OPWMCB_USED)
+static int pwm_nxp_s32_set_cycles_opwmcb(const struct device *dev, uint32_t channel,
+					uint32_t period_cycles, uint32_t pulse_cycles,
+					Emios_Pwm_Ip_ChannelConfigType *pwm_info,
+					pwm_flags_t flags)
 {
-	uint8_t master_channel;
+	const struct pwm_nxp_s32_config *config = dev->config;
+	struct pwm_nxp_s32_data *data = dev->data;
+	struct pwm_nxp_s32_channel_data *ch_data = &data->ch_data[channel];
+	struct pwm_nxp_s32_channel_data *master_ch_data = &data->ch_data[ch_data->master_channel];
 
-	if ((period_cycles > EMIOS_PWM_IP_MAX_CNT_VAL) ||
-		(period_cycles <= EMIOS_PWM_IP_MIN_CNT_VAL)) {
-		LOG_ERR("period_cycles is out of range");
-		return -EINVAL;
-	}
+	unsigned int key;
+	Emios_Pwm_Ip_PolarityType polarity;
+
+	/* Convert to written value into eMIOS register */
+	if (pulse_cycles == 0) {
+		pulse_cycles = EMIOS_PWM_IP_MAX_CNT_VAL;
+	} else if (pulse_cycles == period_cycles) {
+		pulse_cycles = 1;
+	} else {
+		pulse_cycles = period_cycles - (pulse_cycles >> 1);
+	}
+
+	if ((ch_data->inverted != flags) || (!ch_data->curr_period)) {
+		/* If PWM flag is changed or this is the first time PWM channel is configured */
+		polarity = (flags & PWM_POLARITY_MASK) ? EMIOS_PWM_IP_ACTIVE_LOW :
+							 EMIOS_PWM_IP_ACTIVE_HIGH;
+
+		if (master_ch_data->curr_period != period_cycles) {
+			/*
+			 * Move timebase channel to GPIO mode --> configure period --> MCB mode
+			 * Period can be shared between multiple PWM channels, only configure
+			 * when needed.
+			 */
+			config->base->CH.UC[ch_data->master_channel].C &= ~eMIOS_C_MODE_MASK;
+			config->base->CH.UC[ch_data->master_channel].A = period_cycles;
+		}
+
+		config->base->CH.UC[channel].C &= ~(eMIOS_C_MODE_MASK  |
+						    eMIOS_C_EDPOL_MASK |
+						    eMIOS_C_BSL_MASK);
 
-	if (Emios_Pwm_Ip_GetPeriod(instance, channel) != period_cycles) {
 		/*
-		 * This mode uses internal counter, so change period and cycle
-		 * don't effect to the others
+		 * When entering OPWMCB mode, Output = !Cn[EDPOL]. If 100% pulse cycle is expected
+		 * Cn[EDPOL] is set to complement value (i.e 0 if active high and 1 if active low).
 		 */
-		master_channel = Emios_Pwm_Ip_GetMasterBusChannel(instance, channel);
+		if (pulse_cycles == 1) {
+			/* 100% pulse cycle */
+			config->base->CH.UC[channel].C |= eMIOS_C_EDPOL(!polarity);
+		} else {
+			config->base->CH.UC[channel].C |= eMIOS_C_EDPOL(polarity);
+		}
+
+		config->base->CH.UC[channel].A = pulse_cycles;
+		config->base->CH.UC[channel].B = pwm_info->DeadTime;
+
+		key = irq_lock();
+		config->base->CH.UC[channel].C |= (eMIOS_C_MODE(pwm_info->Mode) |
+						   eMIOS_C_BSL(pwm_info->Timebase));
+
+		if (pulse_cycles == 1) {
+			config->base->CH.UC[channel].C = (config->base->CH.UC[channel].C &
+							 ~eMIOS_C_EDPOL_MASK) |
+							 eMIOS_C_EDPOL(polarity);
+		}
+		irq_unlock(key);
 
-		if (Emios_Mcl_Ip_SetCounterBusPeriod(instance, master_channel, period_cycles)) {
-			LOG_ERR("Cannot set counter period");
-			return -EIO;
+		if (master_ch_data->curr_period != period_cycles) {
+			config->base->CH.UC[ch_data->master_channel].C |=
+							eMIOS_C_MODE(EMIOS_IP_MCB_UP_DOWN_COUNTER);
+			master_ch_data->curr_period = period_cycles;
 		}
+
+		ch_data->inverted = flags;
+		ch_data->curr_period = period_cycles;
+	} else if (master_ch_data->curr_period != period_cycles) {
+		key = irq_lock();
+		config->base->CH.UC[ch_data->master_channel].A = period_cycles;
+		config->base->CH.UC[channel].A = pulse_cycles;
+		irq_unlock(key);
+
+		master_ch_data->curr_period = period_cycles;
+	} else {
+		config->base->CH.UC[channel].A = pulse_cycles;
 	}
 
-	if (Emios_Pwm_Ip_GetDutyCycle(instance, channel) != pulse_cycles) {
-		if (Emios_Pwm_Ip_SetDutyCycle(instance, channel, pulse_cycles)) {
-			LOG_ERR("Cannot set pulse cycles");
-			return -EIO;
+	return 0;
+}
+#endif
+
+#if defined(EMIOS_PWM_IP_MODE_OPWMB_USED)
+static int pwm_nxp_s32_set_cycles_opwmb(const struct device *dev, uint32_t channel,
+					uint32_t period_cycles, uint32_t pulse_cycles,
+					Emios_Pwm_Ip_ChannelConfigType *pwm_info,
+					pwm_flags_t flags)
+{
+	const struct pwm_nxp_s32_config *config = dev->config;
+	struct pwm_nxp_s32_data *data = dev->data;
+	struct pwm_nxp_s32_channel_data *ch_data = &data->ch_data[channel];
+	struct pwm_nxp_s32_channel_data *master_ch_data = &data->ch_data[ch_data->master_channel];
+
+	Emios_Pwm_Ip_PolarityType polarity;
+
+	unsigned int key;
+
+	if ((ch_data->inverted != flags) || (!ch_data->curr_period)) {
+		/* If PWM flag is changed or this is the first time PWM channel is configured */
+		polarity = (flags & PWM_POLARITY_MASK) ? EMIOS_PWM_IP_ACTIVE_LOW :
+							 EMIOS_PWM_IP_ACTIVE_HIGH;
+
+		if (master_ch_data->curr_period != period_cycles) {
+			/*
+			 * Move timebase channel to GPIO mode --> configure period --> MCB mode
+			 * Period can be shared between multiple PWM channels, only configure
+			 * when needed.
+			 */
+			config->base->CH.UC[ch_data->master_channel].C &= ~eMIOS_C_MODE_MASK;
+			config->base->CH.UC[ch_data->master_channel].A = period_cycles;
+		}
+
+		config->base->CH.UC[channel].C &= ~(eMIOS_C_MODE_MASK |
+						    eMIOS_C_EDPOL_MASK | eMIOS_C_BSL_MASK);
+
+		config->base->CH.UC[channel].A = pwm_info->PhaseShift;
+		config->base->CH.UC[channel].B = pulse_cycles;
+
+		/*
+		 * When entering OPWMB mode, Output = Cn[EDPOL]. Unless 100% pulse cycle is
+		 * expected, Cn[EDPOL] is set to complement value (i.e 0 if active high and
+		 * 1 if active low).
+		 */
+		if (pulse_cycles == period_cycles) {
+			config->base->CH.UC[channel].C |= eMIOS_C_EDPOL(polarity);
+		} else {
+			config->base->CH.UC[channel].C |= eMIOS_C_EDPOL(!polarity);
+		}
+
+		key = irq_lock();
+		config->base->CH.UC[channel].C |= eMIOS_C_MODE(pwm_info->Mode) |
+						  eMIOS_C_BSL(pwm_info->Timebase);
+
+		if (pulse_cycles != period_cycles) {
+			config->base->CH.UC[channel].C = (config->base->CH.UC[channel].C &
+							~(eMIOS_C_EDPOL_MASK)) |
+							eMIOS_C_EDPOL(polarity);
+		}
+
+		if (!pwm_info->PhaseShift) {
+			/*
+			 * If Phase Shift == 0, Force Match A to ensure PWM pulse can be
+			 * generated immediately. Otherwise, it will need to wait until
+			 * next period boundary.
+			 */
+			config->base->CH.UC[channel].C |= eMIOS_C_FORCMA(1);
 		}
+		irq_unlock(key);
+
+		if (master_ch_data->curr_period != period_cycles) {
+			config->base->CH.UC[ch_data->master_channel].C |=
+							eMIOS_C_MODE(EMIOS_IP_MCB_UP_COUNTER);
+			master_ch_data->curr_period = period_cycles;
+		}
+
+		ch_data->inverted = flags;
+		ch_data->curr_period = period_cycles;
+	} else if (master_ch_data->curr_period != period_cycles) {
+		key = irq_lock();
+		config->base->CH.UC[ch_data->master_channel].A = period_cycles;
+		config->base->CH.UC[channel].B = pulse_cycles;
+		irq_unlock(key);
+
+		master_ch_data->curr_period = period_cycles;
+	} else {
+		config->base->CH.UC[channel].B = pulse_cycles;
 	}
 
 	return 0;
@@ -176,49 +363,60 @@ static int pwm_nxp_s32_set_cycles(const struct device *dev, uint32_t channel,
 	logic_ch = eMios_Pwm_Ip_IndexInChState[config->instance][channel] - data->start_pwm_ch;
 	pwm_info = &config->pulse_info->pwm_info[logic_ch];
 
-	if ((flags & PWM_POLARITY_MASK) == pwm_info->OutputPolarity) {
-		LOG_ERR("Only support configuring output polarity at boot time");
-		return -ENOTSUP;
-	}
-
 	switch (pwm_info->Mode) {
 #ifdef EMIOS_PWM_IP_MODE_OPWFMB_USED
 	case EMIOS_PWM_IP_MODE_OPWFMB_FLAG:
-		return pwm_nxp_s32_set_cycles_internal_timebase(config->instance, channel,
-								period_cycles, pulse_cycles);
+
+		if ((period_cycles > EMIOS_PWM_IP_MAX_CNT_VAL) ||
+			(period_cycles <= EMIOS_PWM_IP_MIN_CNT_VAL)) {
+			LOG_ERR("Period cycles is out of range");
+			return -EINVAL;
+		}
+
+		return pwm_nxp_s32_set_cycles_opwfmb(dev, channel, period_cycles,
+						     pulse_cycles, flags);
 #endif
 
 #ifdef EMIOS_PWM_IP_MODE_OPWMCB_USED
 	case EMIOS_PWM_IP_MODE_OPWMCB_TRAIL_EDGE_FLAG:
 	case EMIOS_PWM_IP_MODE_OPWMCB_LEAD_EDGE_FLAG:
-		if ((period_cycles % 2)) {
-			LOG_ERR("OPWMCB mode: period must be an even number");
+
+		period_cycles = (period_cycles + 2) / 2;
+
+		if ((period_cycles > EMIOS_PWM_IP_MAX_CNT_VAL) ||
+			(period_cycles <= EMIOS_PWM_IP_MIN_CNT_VAL)) {
+			LOG_ERR("Period cycles is out of range");
 			return -EINVAL;
 		}
 
-		return pwm_nxp_s32_set_cycles_external_timebase(config->instance, channel,
-								(period_cycles + 2) / 2,
-								pulse_cycles);
+		return pwm_nxp_s32_set_cycles_opwmcb(dev, channel, period_cycles,
+						     pulse_cycles, pwm_info, flags);
 #endif
 
 #if defined(EMIOS_PWM_IP_MODE_OPWMB_USED)
 	case EMIOS_PWM_IP_MODE_OPWMB_FLAG:
-		if ((Emios_Pwm_Ip_GetPhaseShift(config->instance, channel) +
-						pulse_cycles) > period_cycles) {
-			LOG_ERR("OPWMB mode: new duty cycle + phase shift must <= new period");
+
+		if ((period_cycles > EMIOS_PWM_IP_MAX_CNT_VAL) ||
+			(period_cycles <= EMIOS_PWM_IP_MIN_CNT_VAL)) {
+			LOG_ERR("Period cycles is out of range");
 			return -EINVAL;
 		}
 
-		return pwm_nxp_s32_set_cycles_external_timebase(config->instance, channel,
-								period_cycles, pulse_cycles);
+		pulse_cycles += pwm_info->PhaseShift;
+
+		if (pulse_cycles > period_cycles) {
+			LOG_ERR("Pulse cycles is out of range");
+			return -EINVAL;
+		}
+
+		return pwm_nxp_s32_set_cycles_opwmb(dev, channel, period_cycles,
+						    pulse_cycles, pwm_info, flags);
 #endif
 
 	default:
 		/* Never reach here */
-		break;
+		return 0;
 	}
-
-	return 0;
 }
 #endif
 
@@ -284,12 +482,12 @@ static int pwm_nxp_s32_capture_configure(const struct device *dev,
 		return -EBUSY;
 	}
 
-	data->capture[channel].continuous = (flags & PWM_CAPTURE_MODE_MASK);
-	data->capture[channel].inverted = (flags & PWM_POLARITY_MASK);
-	data->capture[channel].pulse_capture = (flags & PWM_CAPTURE_TYPE_PULSE);
-	data->capture[channel].period_capture = (flags & PWM_CAPTURE_TYPE_PERIOD);
-	data->capture[channel].callback = cb;
-	data->capture[channel].user_data = user_data;
+	data->ch_data[channel].continuous = (flags & PWM_CAPTURE_MODE_MASK);
+	data->ch_data[channel].inverted = (flags & PWM_POLARITY_MASK);
+	data->ch_data[channel].pulse_capture = (flags & PWM_CAPTURE_TYPE_PULSE);
+	data->ch_data[channel].period_capture = (flags & PWM_CAPTURE_TYPE_PERIOD);
+	data->ch_data[channel].callback = cb;
+	data->ch_data[channel].user_data = user_data;
 
 	return 0;
 }
@@ -313,7 +511,7 @@ static int pwm_nxp_s32_capture_enable(const struct device *dev, uint32_t channel
 		return -EINVAL;
 	}
 
-	if (!data->capture[channel].callback) {
+	if (!data->ch_data[channel].callback) {
 		LOG_ERR("Callback is not configured");
 		return -EINVAL;
 	}
@@ -325,7 +523,7 @@ static int pwm_nxp_s32_capture_enable(const struct device *dev, uint32_t channel
 	}
 
 	/* If just measure period, we just need 2 edges */
-	if (data->capture[channel].period_capture && !data->capture[channel].pulse_capture) {
+	if (data->ch_data[channel].period_capture && !data->ch_data[channel].pulse_capture) {
 		num_edge = 2U;
 		edge = EMIOS_ICU_RISING_EDGE;
 	} else {
@@ -338,7 +536,7 @@ static int pwm_nxp_s32_capture_enable(const struct device *dev, uint32_t channel
 	Emios_Icu_Ip_EnableNotification(config->instance, channel);
 
 	Emios_Icu_Ip_StartTimestamp(config->instance, channel,
-				    data->capture[channel].edge_buff,
+				    data->ch_data[channel].edge_buff,
 				    MAX_NUM_EDGE, num_edge);
 
 	return 0;
@@ -363,68 +561,22 @@ static int pwm_nxp_s32_capture_disable(const struct device *dev, uint32_t channe
 
 	return 0;
 }
-
-static int pwm_nxp_s32_get_master_bus(const struct device *dev, uint32_t channel)
-{
-	const struct pwm_nxp_s32_config *config = dev->config;
-	uint8_t bus_select, master_bus;
-
-	bus_select = (config->base->CH.UC[channel].C & eMIOS_C_BSL_MASK) >> eMIOS_C_BSL_SHIFT;
-
-	switch (bus_select) {
-	case 0:
-		master_bus = 23U;
-		break;
-	case 1:
-		master_bus = (channel < 8U) ? 0U : ((channel < 16U) ? 8U : 16U);
-		break;
-	case 2:
-		master_bus = 22U;
-		break;
-	default:
-		/* Default is internal counter */
-		master_bus = channel;
-		break;
-	}
-
-	return master_bus;
-}
 #endif
 
 static int pwm_nxp_s32_get_cycles_per_sec(const struct device *dev,
-					  uint32_t channel,
-					  uint64_t *cycles)
+					  uint32_t channel, uint64_t *cycles)
 {
 	const struct pwm_nxp_s32_config *config = dev->config;
 	struct pwm_nxp_s32_data *data = dev->data;
 
-	uint8_t master_bus = 0xFFU;
-	uint8_t internal_prescaler, global_prescaler;
+	uint8_t internal_prescaler, global_prescaler, master_channel;
 
-#if EMIOS_PWM_IP_USED
-	if (eMios_Pwm_Ip_IndexInChState[config->instance][channel] <
-	    EMIOS_PWM_IP_NUM_OF_CHANNELS_USED) {
-		master_bus = Emios_Pwm_Ip_GetMasterBusChannel(config->instance, channel);
-	}
-#endif
-
-#ifdef CONFIG_PWM_CAPTURE
-	if (eMios_Icu_Ip_IndexInChState[config->instance][channel] <
-	    EMIOS_ICU_IP_NUM_OF_CHANNELS_USED) {
-		master_bus = pwm_nxp_s32_get_master_bus(dev, channel);
-	}
-#endif
-
-	if (master_bus == 0xFF) {
-		LOG_ERR("Channel %d is not configured for PWM", channel);
-		return -EINVAL;
-	}
-
-	internal_prescaler = (config->base->CH.UC[master_bus].C2 & eMIOS_C2_UCEXTPRE_MASK) >>
+	master_channel = data->ch_data[channel].master_channel;
+	internal_prescaler = (config->base->CH.UC[master_channel].C2 & eMIOS_C2_UCEXTPRE_MASK) >>
 			      eMIOS_C2_UCEXTPRE_SHIFT;
 
 	/* Clock source for internal prescaler is from either eMIOS or eMIOS / global prescaler */
-	if (config->base->CH.UC[master_bus].C2 & eMIOS_C2_UCPRECLK_MASK) {
+	if (config->base->CH.UC[master_channel].C2 & eMIOS_C2_UCPRECLK_MASK) {
 		*cycles = data->emios_clk / (internal_prescaler + 1);
 	} else {
 		global_prescaler = (config->base->MCR & eMIOS_MCR_GPRE_MASK) >>
@@ -441,7 +593,8 @@ static int pwm_nxp_s32_pulse_gen_init(const struct device *dev)
 	const struct pwm_nxp_s32_config *config = dev->config;
 	struct pwm_nxp_s32_data *data = dev->data;
 
-	const Emios_Pwm_Ip_ChannelConfigType *pwm_info;
+	struct pwm_nxp_s32_channel_data *ch_data;
+	Emios_Pwm_Ip_ChannelConfigType pwm_info;
 
 	uint8_t ch_id;
 	static uint8_t logic_ch;
@@ -449,9 +602,20 @@ static int pwm_nxp_s32_pulse_gen_init(const struct device *dev)
 	data->start_pwm_ch = logic_ch;
 
 	for (ch_id = 0; ch_id < config->pulse_info->pwm_pulse_channels; ch_id++) {
-		pwm_info = &config->pulse_info->pwm_info[ch_id];
-		eMios_Pwm_Ip_IndexInChState[config->instance][pwm_info->ChannelId] = logic_ch++;
-		Emios_Pwm_Ip_InitChannel(config->instance, pwm_info);
+		memcpy(&pwm_info, &config->pulse_info->pwm_info[ch_id],
+			sizeof(Emios_Pwm_Ip_ChannelConfigType));
+
+		/*
+		 * Let eMIOS channel is in GPIO mode, the actual PWM mode will be
+		 * configured at the first time pwm_set* is called.
+		 */
+		pwm_info.Mode = EMIOS_PWM_IP_MODE_GPO;
+		eMios_Pwm_Ip_IndexInChState[config->instance][pwm_info.ChannelId] = logic_ch++;
+		Emios_Pwm_Ip_InitChannel(config->instance, &pwm_info);
+
+		ch_data = &data->ch_data[pwm_info.ChannelId];
+		ch_data->master_channel = EMIOS_PWM_MASTER_CHANNEL(pwm_info.ChannelId,
+								   pwm_info.Timebase);
 	}
 
 	return 0;
@@ -462,7 +626,9 @@ static int pwm_nxp_s32_pulse_gen_init(const struct device *dev)
 static int pwm_nxp_s32_pulse_capture_init(const struct device *dev)
 {
 	const struct pwm_nxp_s32_config *config = dev->config;
+	struct pwm_nxp_s32_data *data = dev->data;
 
+	struct pwm_nxp_s32_channel_data *ch_data;
 	const eMios_Icu_Ip_ChannelConfigType *icu_info;
 
 	uint8_t ch_id;
@@ -470,7 +636,11 @@ static int pwm_nxp_s32_pulse_capture_init(const struct device *dev)
 
 	for (ch_id = 0; ch_id < config->icu_cfg->nNumChannels; ch_id++) {
 		icu_info = &(*config->icu_cfg->pChannelsConfig)[ch_id];
+		ch_data = &data->ch_data[icu_info->hwChannel];
+
 		eMios_Icu_Ip_IndexInChState[config->instance][icu_info->hwChannel] = logic_ch++;
+		ch_data->master_channel = EMIOS_ICU_MASTER_CHANNEL(icu_info->hwChannel,
+								   icu_info->CntBus);
 	}
 
 	if (Emios_Icu_Ip_Init(config->instance, config->icu_cfg)) {
@@ -487,29 +657,29 @@ static void pwm_nxp_s32_capture_callback(const struct device *dev, uint32_t chan
 
 	uint32_t period = 0, pulse = 0;
 
-	if (data->capture[channel].period_capture && !data->capture[channel].pulse_capture) {
-		period = pwm_nxp_s32_capture_calc(data->capture[channel].edge_buff[0],
-						 data->capture[channel].edge_buff[1]);
+	if (data->ch_data[channel].period_capture && !data->ch_data[channel].pulse_capture) {
+		period = pwm_nxp_s32_capture_calc(data->ch_data[channel].edge_buff[0],
+						 data->ch_data[channel].edge_buff[1]);
 	} else {
-		if (data->capture[channel].pulse_capture) {
-			pulse = pwm_nxp_s32_pulse_calc(data->capture[channel].inverted,
-						       data->capture[channel].edge_buff,
+		if (data->ch_data[channel].pulse_capture) {
+			pulse = pwm_nxp_s32_pulse_calc(data->ch_data[channel].inverted,
+						       data->ch_data[channel].edge_buff,
 						       Emios_Icu_Ip_GetInputLevel(config->instance,
 										  channel));
 		}
 
-		if (data->capture[channel].period_capture) {
-			period = pwm_nxp_s32_capture_calc(data->capture[channel].edge_buff[0],
-							  data->capture[channel].edge_buff[2]);
+		if (data->ch_data[channel].period_capture) {
+			period = pwm_nxp_s32_capture_calc(data->ch_data[channel].edge_buff[0],
+							  data->ch_data[channel].edge_buff[2]);
 		}
 	}
 
-	if (!data->capture[channel].continuous) {
+	if (!data->ch_data[channel].continuous) {
 		Emios_Icu_Ip_StopTimestamp(config->instance, channel);
 	}
 
-	data->capture[channel].callback(dev, channel, period, pulse, 0,
-					data->capture[channel].user_data);
+	data->ch_data[channel].callback(dev, channel, period, pulse, 0,
+					data->ch_data[channel].user_data);
 }
 #endif
 
@@ -561,14 +731,6 @@ static DEVICE_API(pwm, pwm_nxp_s32_driver_api) = {
 #endif
 };
 
-/*
- * If timebase is configured in MCB up/down count mode: pwm period = (2 * master bus's period - 2)
- */
-#define EMIOS_PWM_PERIOD_TIME_BASE(node_id)							\
-	COND_CODE_1(DT_ENUM_HAS_VALUE(node_id, mode, MCB_UP_DOWN_COUNTER),			\
-		   (2 * DT_PROP_BY_PHANDLE(node_id, master_bus, period) - 2),			\
-		   (DT_PROP_BY_PHANDLE(node_id, master_bus, period)))
-
 #define EMIOS_PWM_IS_MODE_OPWFMB(node_id)							\
 	DT_ENUM_HAS_VALUE(node_id, pwm_mode, OPWFMB)
 
@@ -594,22 +756,11 @@ static DEVICE_API(pwm, pwm_nxp_s32_driver_api) = {
 		     EMIOS_PWM_LOG(node_id, "invalid master bus"));
 
 #define EMIOS_PWM_PULSE_GEN_COMMON_VERIFY(node_id)						\
-	BUILD_ASSERT(DT_NODE_HAS_PROP(node_id, duty_cycle),					\
-		     EMIOS_PWM_LOG(node_id, "duty-cycle must be configured"));			\
-	BUILD_ASSERT(DT_NODE_HAS_PROP(node_id, polarity),					\
-		     EMIOS_PWM_LOG(node_id, "polarity must be configured"));			\
 	BUILD_ASSERT(DT_NODE_HAS_PROP(node_id, input_filter),					\
 		     EMIOS_PWM_LOG(node_id, "input-filter is not used"));
 
 #define EMIOS_PWM_VERIFY_MODE_OPWFMB(node_id)							\
 	EMIOS_PWM_PULSE_GEN_COMMON_VERIFY(node_id)						\
-	BUILD_ASSERT(DT_NODE_HAS_PROP(node_id, period),						\
-		     EMIOS_PWM_LOG(node_id, "period must be configured"));			\
-	BUILD_ASSERT(IN_RANGE(DT_PROP(node_id, period), EMIOS_PWM_IP_MIN_CNT_VAL + 1,		\
-			      EMIOS_PWM_IP_MAX_CNT_VAL),					\
-		     EMIOS_PWM_LOG(node_id, "period is out of range"));				\
-	BUILD_ASSERT(DT_PROP(node_id, duty_cycle) <= DT_PROP(node_id, period),			\
-		     EMIOS_PWM_LOG(node_id, "duty-cycle must <= period"));			\
 	BUILD_ASSERT(!DT_NODE_HAS_PROP(node_id, master_bus),					\
 		     EMIOS_PWM_LOG(node_id, "master-bus must not be configured"));		\
 	BUILD_ASSERT(DT_PROP(node_id, dead_time) == 0,						\
@@ -622,16 +773,8 @@ static DEVICE_API(pwm, pwm_nxp_s32_driver_api) = {
 	BUILD_ASSERT(DT_ENUM_HAS_VALUE(DT_PHANDLE(node_id, master_bus),	mode,			\
 		     MCB_UP_DOWN_COUNTER),							\
 		     EMIOS_PWM_LOG(node_id, "master-bus must be configured in MCB up-down"));	\
-	BUILD_ASSERT((DT_PROP(node_id, duty_cycle) + DT_PROP(node_id, dead_time)) <=		\
-		     EMIOS_PWM_PERIOD_TIME_BASE(node_id),					\
-		     EMIOS_PWM_LOG(node_id, "duty-cycle + dead-time must <= period"));		\
-	BUILD_ASSERT(DT_PROP(node_id, dead_time) <= DT_PROP(node_id, duty_cycle),		\
-		     EMIOS_PWM_LOG(node_id, "dead-time must <= duty-cycle"));			\
 	BUILD_ASSERT(DT_PROP(node_id, phase_shift) == 0,					\
 		     EMIOS_PWM_LOG(node_id, "phase-shift is not used"));			\
-	BUILD_ASSERT(!DT_NODE_HAS_PROP(node_id, period),					\
-		     EMIOS_PWM_LOG(node_id, "period is not used,"				\
-		     " driver takes the value from master bus"));				\
 	BUILD_ASSERT(!DT_NODE_HAS_PROP(node_id, prescaler),					\
 		     EMIOS_PWM_LOG(node_id, "prescaler is not used,"				\
 		     " driver takes the value from master bus"));				\
@@ -643,12 +786,6 @@ static DEVICE_API(pwm, pwm_nxp_s32_driver_api) = {
 	EMIOS_PWM_PULSE_GEN_COMMON_VERIFY(node_id)						\
 	BUILD_ASSERT(DT_ENUM_HAS_VALUE(DT_PHANDLE(node_id, master_bus),	mode, MCB_UP_COUNTER),	\
 		     EMIOS_PWM_LOG(node_id, "master-bus must be configured in MCB up"));	\
-	BUILD_ASSERT(!DT_NODE_HAS_PROP(node_id, period),					\
-		     EMIOS_PWM_LOG(node_id, "period is not used,"				\
-		     " driver takes the value from master bus"));				\
-	BUILD_ASSERT((DT_PROP(node_id, duty_cycle) + DT_PROP(node_id, phase_shift)) <=		\
-		     EMIOS_PWM_PERIOD_TIME_BASE(node_id),					\
-		     EMIOS_PWM_LOG(node_id, "duty-cycle + phase-shift must <= period"));	\
 	BUILD_ASSERT(DT_PROP(node_id, dead_time) == 0,						\
 		     EMIOS_PWM_LOG(node_id, "dead-time is not used"));				\
 	BUILD_ASSERT(!DT_NODE_HAS_PROP(node_id, prescaler),					\
@@ -662,9 +799,6 @@ static DEVICE_API(pwm, pwm_nxp_s32_driver_api) = {
 		  (BUILD_ASSERT(								\
 		   DT_ENUM_HAS_VALUE(DT_PHANDLE(node_id, master_bus), mode, MCB_UP_COUNTER),	\
 		   EMIOS_PWM_LOG(node_id, "master-bus must be configured in MCB up"));))	\
-	IF_ENABLED(DT_NODE_HAS_PROP(node_id, master_bus),					\
-		  (BUILD_ASSERT(DT_PROP_BY_PHANDLE(node_id, master_bus, period) == 0xFFFF,	\
-		   EMIOS_PWM_LOG(node_id, "master-bus period must be 0xFFFF"));))		\
 	IF_ENABLED(UTIL_NOT(DT_NODE_HAS_PROP(node_id, master_bus)),				\
 		   (BUILD_ASSERT(								\
 		    BIT(DT_PROP(node_id, channel)) & DT_PROP(DT_GPARENT(node_id), internal_cnt),\
@@ -674,12 +808,6 @@ static DEVICE_API(pwm, pwm_nxp_s32_driver_api) = {
 		   (BUILD_ASSERT(DT_NODE_HAS_PROP(node_id, prescaler),				\
 		    EMIOS_PWM_LOG(node_id, "if use internal counter, prescaler must"		\
 		    " be configured"))));							\
-	BUILD_ASSERT(!DT_NODE_HAS_PROP(node_id, duty_cycle),					\
-		     EMIOS_PWM_LOG(node_id, "duty-cycle is not used"));				\
-	BUILD_ASSERT(!DT_NODE_HAS_PROP(node_id, polarity),					\
-		     EMIOS_PWM_LOG(node_id, "polarity is not used"));				\
-	BUILD_ASSERT(!DT_NODE_HAS_PROP(node_id, period),					\
-		     EMIOS_PWM_LOG(node_id, "period is not used"));				\
 	BUILD_ASSERT(DT_ENUM_HAS_VALUE(node_id, prescaler_src, PRESCALED_CLOCK),		\
 		     EMIOS_PWM_LOG(node_id, "prescaler-src is not used,"			\
 		     " always use prescalered source"));
@@ -707,9 +835,9 @@ static DEVICE_API(pwm, pwm_nxp_s32_driver_api) = {
 
 #define EMIOS_PWM_BUS(mode)		DT_CAT(EMIOS_PWM_, mode)
 #define EMIOS_PWM_MODE(mode)		DT_CAT3(EMIOS_PWM_IP_MODE_, mode, _FLAG)
-#define EMIOS_PWM_POLARITY(mode)	DT_CAT(EMIOS_PWM_IP_, mode)
 #define EMIOS_PWM_PS_SRC(mode)		DT_CAT(EMIOS_PWM_IP_PS_SRC_, mode)
 
+/* Keep minimal configuration used at driver initialization, no PWM signal is produced */
 #define _EMIOS_PWM_PULSE_GEN_CONFIG(node_id)							\
 	IF_ENABLED(UTIL_NOT(EMIOS_PWM_IS_CAPTURE_MODE(node_id)),				\
 	({											\
@@ -725,10 +853,10 @@ static DEVICE_API(pwm, pwm_nxp_s32_driver_api) = {
 		.PhaseShift = DT_PROP(node_id, phase_shift),					\
 		.DeadTime   = DT_PROP(node_id, dead_time),					\
 		.OutputDisableSource = EMIOS_PWM_IP_OUTPUT_DISABLE_NONE,			\
-		.OutputPolarity = EMIOS_PWM_POLARITY(DT_STRING_TOKEN(node_id, polarity)),	\
+		.OutputPolarity = EMIOS_PWM_IP_ACTIVE_LOW,					\
 		.DebugMode   = DT_PROP(node_id, freeze),					\
-		.PeriodCount = DT_PROP_OR(node_id, period, EMIOS_PWM_PERIOD_TIME_BASE(node_id)),\
-		.DutyCycle   = DT_PROP(node_id, duty_cycle),					\
+		.PeriodCount = 0,								\
+		.DutyCycle   = 0,								\
 	},))
 
 #define EMIOS_PWM_PULSE_GEN_CONFIG(n)								\
diff --git a/drivers/pwm/pwm_renesas_ra.c b/drivers/pwm/pwm_renesas_ra.c
index 432ef568ebe..fa745a0aa37 100644
--- a/drivers/pwm/pwm_renesas_ra.c
+++ b/drivers/pwm/pwm_renesas_ra.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -437,7 +437,7 @@ static void fsp_callback(timer_callback_args_t *p_args)
 
 #endif /* CONFIG_PWM_CAPTURE */
 
-static const struct pwm_driver_api pwm_renesas_ra_driver_api = {
+static DEVICE_API(pwm, pwm_renesas_ra_driver_api) = {
 	.get_cycles_per_sec = pwm_renesas_ra_get_cycles_per_sec,
 	.set_cycles = pwm_renesas_ra_set_cycles,
 #ifdef CONFIG_PWM_CAPTURE
@@ -485,11 +485,10 @@ static int pwm_renesas_ra_init(const struct device *dev)
 	return 0;
 }
 
-#define _ELC_EVENT_GPT_CAPTURE_COMPARE_A(channel) ELC_EVENT_GPT##channel##_CAPTURE_COMPARE_A
-#define _ELC_EVENT_GPT_COUNTER_OVERFLOW(channel)  ELC_EVENT_GPT##channel##_COUNTER_OVERFLOW
-
-#define ELC_EVENT_GPT_CAPTURE_COMPARE_A(channel) _ELC_EVENT_GPT_CAPTURE_COMPARE_A(channel)
-#define ELC_EVENT_GPT_COUNTER_OVERFLOW(channel)  _ELC_EVENT_GPT_COUNTER_OVERFLOW(channel)
+#define EVENT_GPT_CAPTURE_COMPARE_A(channel)                                                       \
+	BSP_PRV_IELS_ENUM(CONCAT(EVENT_GPT, channel, _CAPTURE_COMPARE_A))
+#define EVENT_GPT_COUNTER_OVERFLOW(channel)                                                        \
+	BSP_PRV_IELS_ENUM(CONCAT(EVENT_GPT, channel, _COUNTER_OVERFLOW))
 
 #ifdef CONFIG_PWM_CAPTURE
 #define PWM_RA_IRQ_CONFIG_INIT(index)                                                              \
@@ -546,8 +545,8 @@ static int pwm_renesas_ra_init(const struct device *dev)
 				.cycle_end_irq = DT_INST_IRQ_BY_NAME(index, overflow, irq),        \
 			},                                                                         \
 		.extend_cfg = g_timer1_extend_##index,                                             \
-		.capture_a_event = ELC_EVENT_GPT_CAPTURE_COMPARE_A(DT_INST_PROP(index, channel)),  \
-		.overflow_event = ELC_EVENT_GPT_COUNTER_OVERFLOW(DT_INST_PROP(index, channel)),    \
+		.capture_a_event = EVENT_GPT_CAPTURE_COMPARE_A(DT_INST_PROP(index, channel)),      \
+		.overflow_event = EVENT_GPT_COUNTER_OVERFLOW(DT_INST_PROP(index, channel)),        \
 	};                                                                                         \
 	static const struct pwm_renesas_ra_config pwm_renesas_ra_config_##index = {                \
 		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index),                                   \
diff --git a/drivers/pwm/pwm_renesas_rz_gpt.c b/drivers/pwm/pwm_renesas_rz_gpt.c
new file mode 100644
index 00000000000..faae50c23a0
--- /dev/null
+++ b/drivers/pwm/pwm_renesas_rz_gpt.c
@@ -0,0 +1,664 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/irq.h>
+#include <zephyr/drivers/pwm.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/dt-bindings/pwm/renesas_rz_pwm.h>
+#include "r_gpt.h"
+#include "r_gpt_cfg.h"
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(pwm_renesas_rz_gpt, CONFIG_PWM_LOG_LEVEL);
+
+#define DT_DRV_COMPAT renesas_rz_gpt_pwm
+
+#define GPT_PRV_GTIO_HIGH_COMPARE_MATCH_LOW_CYCLE_END 0x6U
+#define GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END 0x9U
+#define GPT_PRV_GTIOR_INITIAL_LEVEL_BIT               4
+
+#define CAPTURE_BOTH_MODE_FIRST_EVENT_IS_CAPTURE_PULSE   1
+#define CAPTURE_BOTH_MODE_SECOND_EVENT_IS_CAPTURE_PERIOD 2
+
+struct pwm_rz_gpt_capture_data {
+	pwm_capture_callback_handler_t callback;
+	void *user_data;
+	uint64_t period;
+	uint64_t pulse;
+	uint16_t capture_type_flag;
+	uint32_t capture_both_event_count;
+	bool is_busy;
+	uint32_t overflows;
+	bool continuous;
+	uint32_t capture_channel;
+};
+
+struct pwm_rz_gpt_data {
+	timer_cfg_t *fsp_cfg;
+	gpt_instance_ctrl_t *fsp_ctrl;
+#ifdef CONFIG_PWM_CAPTURE
+	struct pwm_rz_gpt_capture_data capture;
+#endif /* CONFIG_PWM_CAPTURE */
+};
+
+struct pwm_rz_gpt_config {
+	const struct pinctrl_dev_config *pincfg;
+	const timer_api_t *fsp_api;
+};
+
+static uint32_t pwm_rz_gpt_gtior_calculate(gpt_pin_level_t const stop_level)
+{
+	/* The stop level is used as both the initial level and the stop level. */
+	uint32_t gtior = R_GPT0_GTIOR_OAE_Msk | ((uint32_t)stop_level << R_GPT0_GTIOR_OADFLT_Pos) |
+			 ((uint32_t)stop_level << GPT_PRV_GTIOR_INITIAL_LEVEL_BIT);
+
+	uint32_t gtion = GPT_PRV_GTIO_LOW_COMPARE_MATCH_HIGH_CYCLE_END;
+
+	/* Calculate the gtior value for PWM mode only */
+	gtior |= gtion;
+
+	return gtior;
+}
+
+static int pwm_rz_gpt_apply_gtior_config(gpt_instance_ctrl_t *const p_ctrl,
+					 timer_cfg_t const *const p_cfg)
+{
+	gpt_extended_cfg_t *p_extend = (gpt_extended_cfg_t *)p_cfg->p_extend;
+	uint32_t gtior = p_extend->gtior_setting.gtior;
+
+#if GPT_CFG_OUTPUT_SUPPORT_ENABLE
+	/* Check if custom GTIOR settings are provided. */
+	if (p_extend->gtior_setting.gtior == 0) {
+		/* If custom GTIOR settings are not provided, calculate GTIOR. */
+		if (p_extend->gtioca.output_enabled) {
+			uint32_t gtioca_gtior =
+				pwm_rz_gpt_gtior_calculate(p_extend->gtioca.stop_level);
+			gtior |= gtioca_gtior << R_GPT0_GTIOR_GTIOA_Pos;
+		}
+
+		if (p_extend->gtiocb.output_enabled) {
+			uint32_t gtiocb_gtior =
+				pwm_rz_gpt_gtior_calculate(p_extend->gtiocb.stop_level);
+			gtior |= gtiocb_gtior << R_GPT0_GTIOR_GTIOB_Pos;
+		}
+	}
+#endif
+
+	/* Check if custom GTIOR settings are provided. */
+	if (p_extend->gtior_setting.gtior == 0) {
+		/*
+		 * If custom GTIOR settings are not provided, configure the noise filter for
+		 * the GTIOC pins.
+		 */
+		gtior |= (uint32_t)(p_extend->capture_filter_gtioca << R_GPT0_GTIOR_NFAEN_Pos);
+		gtior |= (uint32_t)(p_extend->capture_filter_gtiocb << R_GPT0_GTIOR_NFBEN_Pos);
+	}
+
+	/* Set the I/O control register. */
+	p_ctrl->p_reg->GTIOR = gtior;
+
+	return 0;
+}
+
+static int pwm_rz_gpt_set_cycles(const struct device *dev, uint32_t channel, uint32_t period_cycles,
+				 uint32_t pulse_cycles, pwm_flags_t flags)
+{
+	const struct pwm_rz_gpt_config *cfg = dev->config;
+	struct pwm_rz_gpt_data *data = dev->data;
+	gpt_extended_cfg_t *fsp_cfg_extend = (gpt_extended_cfg_t *)data->fsp_cfg->p_extend;
+	uint32_t pulse;
+	fsp_err_t err;
+	uint32_t pin;
+
+	/* gtioca and gtiocb setting */
+	if (channel == RZ_PWM_GPT_IO_A) {
+		pin = GPT_IO_PIN_GTIOCA;
+		fsp_cfg_extend->gtioca.output_enabled = true;
+	} else if (channel == RZ_PWM_GPT_IO_B) {
+		pin = GPT_IO_PIN_GTIOCB;
+		fsp_cfg_extend->gtiocb.output_enabled = true;
+	} else {
+		LOG_ERR("Valid only for RZ_PWM_GPT_IO_A and RZ_PWM_GPT_IO_B pins");
+		return -EINVAL;
+	}
+
+	if ((data->fsp_ctrl->variant == TIMER_VARIANT_16_BIT && period_cycles > UINT16_MAX) ||
+	    (data->fsp_ctrl->variant == TIMER_VARIANT_32_BIT && period_cycles > UINT32_MAX)) {
+		LOG_ERR("Out of range period cycles are not valid");
+		return -EINVAL;
+	}
+
+	pulse = (flags & PWM_POLARITY_INVERTED) ? period_cycles - pulse_cycles : pulse_cycles;
+
+	/* Apply gtio output setting */
+	pwm_rz_gpt_apply_gtior_config(data->fsp_ctrl, data->fsp_cfg);
+
+	/* Stop timer */
+	err = cfg->fsp_api->stop(data->fsp_ctrl);
+	if (err != FSP_SUCCESS) {
+		return -EIO;
+	}
+
+	/* Update period cycles, reflected at an overflow */
+	err = cfg->fsp_api->periodSet(data->fsp_ctrl, period_cycles);
+	if (err != FSP_SUCCESS) {
+		return -EIO;
+	}
+
+	/* Update pulse cycles, reflected at an overflow */
+	err = cfg->fsp_api->dutyCycleSet(data->fsp_ctrl, pulse, pin);
+	if (err != FSP_SUCCESS) {
+		return -EIO;
+	}
+
+	/* Start timer */
+	err = cfg->fsp_api->start(data->fsp_ctrl);
+	if (err != FSP_SUCCESS) {
+		return -EIO;
+	}
+
+	return 0;
+};
+
+static int pwm_rz_gpt_get_cycles_per_sec(const struct device *dev, uint32_t channel,
+					 uint64_t *cycles)
+{
+	const struct pwm_rz_gpt_config *cfg = dev->config;
+	struct pwm_rz_gpt_data *data = dev->data;
+	timer_info_t info;
+	fsp_err_t err;
+
+	if (!(channel == RZ_PWM_GPT_IO_A || channel == RZ_PWM_GPT_IO_B)) {
+		LOG_ERR("Valid only for RZ_PWM_GPT_IO_A and RZ_PWM_GPT_IO_B pins");
+		return -EINVAL;
+	}
+
+	err = cfg->fsp_api->infoGet(data->fsp_ctrl, &info);
+	if (err != FSP_SUCCESS) {
+		return -EIO;
+	}
+	*cycles = (uint64_t)info.clock_frequency;
+
+	return 0;
+};
+
+extern void gpt_capture_a_isr(void);
+extern void gpt_capture_b_isr(void);
+extern void gpt_counter_overflow_isr(void);
+
+#ifdef CONFIG_PWM_CAPTURE
+
+static int pwm_rz_gpt_configure_capture(const struct device *dev, uint32_t channel,
+					pwm_flags_t flags, pwm_capture_callback_handler_t cb,
+					void *user_data)
+{
+	struct pwm_rz_gpt_data *data = dev->data;
+	gpt_extended_cfg_t *fsp_cfg_extend = (gpt_extended_cfg_t *)data->fsp_cfg->p_extend;
+
+	if (!(flags & PWM_CAPTURE_TYPE_MASK)) {
+		LOG_ERR("No PWWM capture type specified");
+		return -EINVAL;
+	}
+	data->capture.capture_type_flag = flags & PWM_CAPTURE_TYPE_MASK;
+	data->capture.capture_channel = channel;
+	if (data->capture.is_busy) {
+		LOG_ERR("Capture already active on this pin");
+		return -EBUSY;
+	}
+	if (channel == RZ_PWM_GPT_IO_A) {
+		if (data->capture.capture_type_flag == PWM_CAPTURE_TYPE_BOTH) {
+			data->capture.capture_both_event_count = 0;
+			if (flags & PWM_POLARITY_INVERTED) {
+				fsp_cfg_extend->start_source =
+					(gpt_source_t)(GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW |
+						       GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH |
+						       GPT_SOURCE_NONE);
+			} else {
+				fsp_cfg_extend->start_source =
+					(gpt_source_t)(GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW |
+						       GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH |
+						       GPT_SOURCE_NONE);
+			}
+			fsp_cfg_extend->capture_a_source =
+				(gpt_source_t)(GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW |
+					       GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH |
+					       GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW |
+					       GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH |
+					       GPT_SOURCE_NONE);
+		} else if (data->capture.capture_type_flag == PWM_CAPTURE_TYPE_PERIOD) {
+			if (flags & PWM_POLARITY_INVERTED) {
+				fsp_cfg_extend->start_source =
+					(gpt_source_t)(GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW |
+						       GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH |
+						       GPT_SOURCE_NONE);
+				fsp_cfg_extend->capture_a_source = fsp_cfg_extend->start_source;
+			} else {
+				fsp_cfg_extend->start_source =
+					(gpt_source_t)(GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW |
+						       GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH |
+						       GPT_SOURCE_NONE);
+				fsp_cfg_extend->capture_a_source = fsp_cfg_extend->start_source;
+			}
+		} else {
+			if (flags & PWM_POLARITY_INVERTED) {
+				fsp_cfg_extend->start_source =
+					(gpt_source_t)(GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW |
+						       GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH |
+						       GPT_SOURCE_NONE);
+				fsp_cfg_extend->capture_a_source =
+					(gpt_source_t)(GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW |
+						       GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH |
+						       GPT_SOURCE_NONE);
+			} else {
+				fsp_cfg_extend->start_source =
+					(gpt_source_t)(GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_LOW |
+						       GPT_SOURCE_GTIOCA_RISING_WHILE_GTIOCB_HIGH |
+						       GPT_SOURCE_NONE);
+				fsp_cfg_extend->capture_a_source =
+					(gpt_source_t)(GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_LOW |
+						       GPT_SOURCE_GTIOCA_FALLING_WHILE_GTIOCB_HIGH |
+						       GPT_SOURCE_NONE);
+			}
+		}
+	} else if (channel == RZ_PWM_GPT_IO_B) {
+		if (data->capture.capture_type_flag == PWM_CAPTURE_TYPE_BOTH) {
+			data->capture.capture_both_event_count = 0;
+			if (flags & PWM_POLARITY_INVERTED) {
+				fsp_cfg_extend->start_source =
+					(gpt_source_t)(GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_LOW |
+						       GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_HIGH |
+						       GPT_SOURCE_NONE);
+			} else {
+				fsp_cfg_extend->start_source =
+					(gpt_source_t)(GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_LOW |
+						       GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_HIGH |
+						       GPT_SOURCE_NONE);
+			}
+			fsp_cfg_extend->capture_b_source =
+				(gpt_source_t)(GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_LOW |
+					       GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_HIGH |
+					       GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_LOW |
+					       GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_HIGH |
+					       GPT_SOURCE_NONE);
+		} else if (data->capture.capture_type_flag == PWM_CAPTURE_TYPE_PERIOD) {
+			if (flags & PWM_POLARITY_INVERTED) {
+				fsp_cfg_extend->start_source =
+					(gpt_source_t)(GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_LOW |
+						       GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_HIGH |
+						       GPT_SOURCE_NONE);
+				fsp_cfg_extend->capture_b_source = fsp_cfg_extend->start_source;
+			} else {
+				fsp_cfg_extend->start_source =
+					(gpt_source_t)(GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_LOW |
+						       GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_HIGH |
+						       GPT_SOURCE_NONE);
+				fsp_cfg_extend->capture_b_source = fsp_cfg_extend->start_source;
+			}
+		} else {
+			if (flags & PWM_POLARITY_INVERTED) {
+				fsp_cfg_extend->start_source =
+					(gpt_source_t)(GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_LOW |
+						       GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_HIGH |
+						       GPT_SOURCE_NONE);
+				fsp_cfg_extend->capture_b_source =
+					(gpt_source_t)(GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_LOW |
+						       GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_HIGH |
+						       GPT_SOURCE_NONE);
+			} else {
+				fsp_cfg_extend->start_source =
+					(gpt_source_t)(GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_LOW |
+						       GPT_SOURCE_GTIOCB_RISING_WHILE_GTIOCA_HIGH |
+						       GPT_SOURCE_NONE);
+				fsp_cfg_extend->capture_b_source =
+					(gpt_source_t)(GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_LOW |
+						       GPT_SOURCE_GTIOCB_FALLING_WHILE_GTIOCA_HIGH |
+						       GPT_SOURCE_NONE);
+			}
+		}
+	}
+
+	data->capture.callback = cb;
+	data->capture.user_data = user_data;
+	data->capture.continuous = flags & PWM_CAPTURE_MODE_CONTINUOUS;
+	if (data->capture.continuous) {
+		if (channel == RZ_PWM_GPT_IO_A) {
+			fsp_cfg_extend->stop_source = fsp_cfg_extend->capture_a_source;
+		} else if (channel == RZ_PWM_GPT_IO_B) {
+			fsp_cfg_extend->stop_source = fsp_cfg_extend->capture_b_source;
+		}
+		fsp_cfg_extend->clear_source = fsp_cfg_extend->start_source;
+	}
+
+	else {
+		fsp_cfg_extend->stop_source = (gpt_source_t)(GPT_SOURCE_NONE);
+		fsp_cfg_extend->clear_source = (gpt_source_t)(GPT_SOURCE_NONE);
+	}
+
+	return 0;
+}
+
+static int pwm_rz_gpt_enable_capture(const struct device *dev, uint32_t channel)
+{
+	const struct pwm_rz_gpt_config *cfg = dev->config;
+	struct pwm_rz_gpt_data *data = dev->data;
+	gpt_extended_cfg_t *fsp_cfg_extend = (gpt_extended_cfg_t *)data->fsp_cfg->p_extend;
+	fsp_err_t err;
+
+	data->capture.capture_channel = channel;
+
+	if (data->capture.is_busy) {
+		LOG_ERR("Capture already active on this pin");
+		return -EBUSY;
+	}
+
+	if (!data->capture.callback) {
+		LOG_ERR("PWM capture not configured");
+		return -EINVAL;
+	}
+
+	data->capture.is_busy = true;
+
+	/* Enable capture source */
+	err = cfg->fsp_api->enable(data->fsp_ctrl);
+	if (err != FSP_SUCCESS) {
+		return -EIO;
+	}
+
+	/* Enable interruption */
+	irq_enable(data->fsp_cfg->cycle_end_irq);
+	if (channel == RZ_PWM_GPT_IO_A) {
+		irq_enable(fsp_cfg_extend->capture_a_irq);
+	} else if (channel == RZ_PWM_GPT_IO_B) {
+		irq_enable(fsp_cfg_extend->capture_b_irq);
+	}
+
+	return 0;
+}
+
+static int pwm_rz_gpt_disable_capture(const struct device *dev, uint32_t channel)
+{
+	const struct pwm_rz_gpt_config *cfg = dev->config;
+	struct pwm_rz_gpt_data *data = dev->data;
+	fsp_err_t err;
+	gpt_extended_cfg_t *fsp_cfg_extend = (gpt_extended_cfg_t *)data->fsp_cfg->p_extend;
+
+	data->capture.capture_channel = channel;
+	data->capture.is_busy = false;
+
+	/* Disable interruption */
+	irq_disable(data->fsp_cfg->cycle_end_irq);
+	if (channel == RZ_PWM_GPT_IO_A) {
+		irq_disable(fsp_cfg_extend->capture_a_irq);
+	} else if (channel == RZ_PWM_GPT_IO_B) {
+		irq_disable(fsp_cfg_extend->capture_b_irq);
+	}
+
+	/* Disable capture source */
+	err = cfg->fsp_api->disable(data->fsp_ctrl);
+	if (err != FSP_SUCCESS) {
+		return -EIO;
+	}
+
+	/* Stop timer */
+	err = cfg->fsp_api->stop(data->fsp_ctrl);
+	if (err != FSP_SUCCESS) {
+		return -EIO;
+	}
+
+	/* Clear timer */
+	err = cfg->fsp_api->reset(data->fsp_ctrl);
+	if (err != FSP_SUCCESS) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static void fsp_callback(timer_callback_args_t *p_args)
+{
+	const struct device *dev = p_args->p_context;
+	const struct pwm_rz_gpt_config *cfg = dev->config;
+	struct pwm_rz_gpt_data *data = dev->data;
+	timer_info_t info;
+
+	(void)cfg->fsp_api->infoGet(data->fsp_ctrl, &info);
+
+	uint64_t period = info.period_counts;
+
+	/* The maximum period is one more than the maximum 16,32-bit number, but will be reflected
+	 * as 0
+	 */
+	if (period == 0U) {
+		if (data->fsp_ctrl->variant == TIMER_VARIANT_16_BIT) {
+			period = UINT16_MAX + 1U;
+		} else {
+			period = UINT32_MAX + 1U;
+		}
+	}
+
+	/* Capture event */
+	if (p_args->event == TIMER_EVENT_CAPTURE_A) {
+		if (p_args->capture != 0U) {
+			bool check_disable_capture = false;
+
+			if (data->capture.capture_type_flag == PWM_CAPTURE_TYPE_BOTH) {
+				data->capture.capture_both_event_count++;
+				if (data->capture.capture_both_event_count ==
+				    CAPTURE_BOTH_MODE_FIRST_EVENT_IS_CAPTURE_PULSE) {
+					data->capture.pulse = (data->capture.overflows * period) +
+							      p_args->capture;
+				}
+				if (data->capture.capture_both_event_count ==
+				    CAPTURE_BOTH_MODE_SECOND_EVENT_IS_CAPTURE_PERIOD) {
+					data->capture.capture_both_event_count = 0;
+					data->capture.period = (data->capture.overflows * period) +
+							       p_args->capture;
+					data->capture.callback(
+						dev, GPT_IO_PIN_GTIOCA, data->capture.period,
+						data->capture.pulse, 0, data->capture.user_data);
+
+					check_disable_capture = true;
+				}
+			} else if (data->capture.capture_type_flag == PWM_CAPTURE_TYPE_PULSE) {
+				data->capture.pulse =
+					(data->capture.overflows * period) + p_args->capture;
+				data->capture.callback(dev, GPT_IO_PIN_GTIOCA, 0,
+						       data->capture.pulse, 0,
+						       data->capture.user_data);
+
+				check_disable_capture = true;
+			} else {
+				data->capture.period =
+					(data->capture.overflows * period) + p_args->capture;
+				data->capture.callback(dev, GPT_IO_PIN_GTIOCA, data->capture.period,
+						       0, 0, data->capture.user_data);
+
+				check_disable_capture = true;
+			}
+			if (check_disable_capture) {
+				data->capture.overflows = 0U;
+				/* Disable capture in single mode */
+				if (data->capture.continuous == false) {
+					pwm_rz_gpt_disable_capture(dev, GPT_IO_PIN_GTIOCA);
+				}
+			}
+		}
+	} else if (p_args->event == TIMER_EVENT_CAPTURE_B) {
+		if (p_args->capture != 0U) {
+			bool check_disable_capture = false;
+
+			if (data->capture.capture_type_flag == PWM_CAPTURE_TYPE_BOTH) {
+				data->capture.capture_both_event_count++;
+				if (data->capture.capture_both_event_count ==
+				    CAPTURE_BOTH_MODE_FIRST_EVENT_IS_CAPTURE_PULSE) {
+					data->capture.pulse = (data->capture.overflows * period) +
+							      p_args->capture;
+				}
+				if (data->capture.capture_both_event_count ==
+				    CAPTURE_BOTH_MODE_SECOND_EVENT_IS_CAPTURE_PERIOD) {
+					data->capture.capture_both_event_count = 0;
+					data->capture.period = (data->capture.overflows * period) +
+							       p_args->capture;
+					data->capture.callback(
+						dev, GPT_IO_PIN_GTIOCB, data->capture.period,
+						data->capture.pulse, 0, data->capture.user_data);
+
+					check_disable_capture = true;
+				}
+			} else if (data->capture.capture_type_flag == PWM_CAPTURE_TYPE_PULSE) {
+				data->capture.pulse =
+					(data->capture.overflows * period) + p_args->capture;
+				data->capture.callback(dev, GPT_IO_PIN_GTIOCB, 0,
+						       data->capture.pulse, 0,
+						       data->capture.user_data);
+
+				check_disable_capture = true;
+			} else {
+				data->capture.period =
+					(data->capture.overflows * period) + p_args->capture;
+				data->capture.callback(dev, GPT_IO_PIN_GTIOCB, data->capture.period,
+						       0, 0, data->capture.user_data);
+
+				check_disable_capture = true;
+			}
+			if (check_disable_capture) {
+				data->capture.overflows = 0U;
+				/* Disable capture in single mode */
+				if (data->capture.continuous == false) {
+					pwm_rz_gpt_disable_capture(dev, GPT_IO_PIN_GTIOCB);
+				}
+			}
+		}
+	} else if (p_args->event == TIMER_EVENT_CYCLE_END) {
+		data->capture.overflows++;
+	} else {
+		if (data->capture.capture_channel == RZ_PWM_GPT_IO_A) {
+			data->capture.callback(dev, GPT_IO_PIN_GTIOCA, 0, 0, -ECANCELED,
+					       data->capture.user_data);
+		} else if (data->capture.capture_channel == RZ_PWM_GPT_IO_B) {
+			data->capture.callback(dev, GPT_IO_PIN_GTIOCB, 0, 0, -ECANCELED,
+					       data->capture.user_data);
+		}
+	}
+}
+
+#endif /* CONFIG_PWM_CAPTURE */
+
+static DEVICE_API(pwm, pwm_rz_gpt_driver_api) = {
+	.get_cycles_per_sec = pwm_rz_gpt_get_cycles_per_sec,
+	.set_cycles = pwm_rz_gpt_set_cycles,
+#ifdef CONFIG_PWM_CAPTURE
+	.configure_capture = pwm_rz_gpt_configure_capture,
+	.enable_capture = pwm_rz_gpt_enable_capture,
+	.disable_capture = pwm_rz_gpt_disable_capture,
+#endif /* CONFIG_PWM_CAPTURE */
+};
+
+static int pwm_rz_gpt_init(const struct device *dev)
+{
+	const struct pwm_rz_gpt_config *cfg = dev->config;
+	struct pwm_rz_gpt_data *data = dev->data;
+	gpt_extended_cfg_t *fsp_cfg_extend = (gpt_extended_cfg_t *)data->fsp_cfg->p_extend;
+	int err;
+
+	err = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);
+	if (err) {
+		LOG_ERR("Failed to configure pins for PWM (%d)", err);
+		return err;
+	}
+
+#if defined(CONFIG_PWM_CAPTURE)
+	data->fsp_cfg->p_callback = fsp_callback;
+	data->fsp_cfg->p_context = dev;
+#endif /* defined(CONFIG_PWM_CAPTURE) */
+
+	err = cfg->fsp_api->open(data->fsp_ctrl, data->fsp_cfg);
+	if (err != FSP_SUCCESS) {
+		return -EIO;
+	}
+
+	irq_disable(data->fsp_cfg->cycle_end_irq);
+	irq_disable(fsp_cfg_extend->capture_a_irq);
+	irq_disable(fsp_cfg_extend->capture_b_irq);
+
+	return 0;
+}
+
+#define GPT(idx) DT_INST_PARENT(idx)
+
+#define PWM_RZ_IRQ_CONFIG_INIT(inst)                                                               \
+	do {                                                                                       \
+		IRQ_CONNECT(DT_IRQ_BY_NAME(GPT(inst), ccmpa, irq),                                 \
+			    DT_IRQ_BY_NAME(GPT(inst), ccmpa, priority), gpt_capture_a_isr, NULL,   \
+			    0);                                                                    \
+		IRQ_CONNECT(DT_IRQ_BY_NAME(GPT(inst), ccmpb, irq),                                 \
+			    DT_IRQ_BY_NAME(GPT(inst), ccmpb, priority), gpt_capture_b_isr, NULL,   \
+			    0);                                                                    \
+		IRQ_CONNECT(DT_IRQ_BY_NAME(GPT(inst), ovf, irq),                                   \
+			    DT_IRQ_BY_NAME(GPT(inst), ovf, priority), gpt_counter_overflow_isr,    \
+			    NULL, 0);                                                              \
+	} while (0)
+
+#define PWM_RZG_INIT(inst)                                                                         \
+	PINCTRL_DT_INST_DEFINE(inst);                                                              \
+	static gpt_instance_ctrl_t g_timer##inst##_ctrl;                                           \
+	static gpt_extended_cfg_t g_timer##inst##_extend = {                                       \
+		.gtioca =                                                                          \
+			{                                                                          \
+				.output_enabled = false,                                           \
+				.stop_level = GPT_PIN_LEVEL_LOW,                                   \
+			},                                                                         \
+		.gtiocb =                                                                          \
+			{                                                                          \
+				.output_enabled = false,                                           \
+				.stop_level = GPT_PIN_LEVEL_LOW,                                   \
+			},                                                                         \
+		.start_source = (gpt_source_t)(GPT_SOURCE_NONE),                                   \
+		.stop_source = (gpt_source_t)(GPT_SOURCE_NONE),                                    \
+		.clear_source = (gpt_source_t)(GPT_SOURCE_NONE),                                   \
+		.count_up_source = (gpt_source_t)(GPT_SOURCE_NONE),                                \
+		.count_down_source = (gpt_source_t)(GPT_SOURCE_NONE),                              \
+		.capture_a_source = (gpt_source_t)(GPT_SOURCE_NONE),                               \
+		.capture_b_source = (gpt_source_t)(GPT_SOURCE_NONE),                               \
+		.capture_a_ipl = DT_IRQ_BY_NAME(GPT(inst), ccmpa, priority),                       \
+		.capture_b_ipl = DT_IRQ_BY_NAME(GPT(inst), ccmpb, priority),                       \
+		.capture_a_irq = DT_IRQ_BY_NAME(GPT(inst), ccmpa, irq),                            \
+		.capture_b_irq = DT_IRQ_BY_NAME(GPT(inst), ccmpb, irq),                            \
+		.capture_filter_gtioca = GPT_CAPTURE_FILTER_NONE,                                  \
+		.capture_filter_gtiocb = GPT_CAPTURE_FILTER_NONE,                                  \
+		.p_pwm_cfg = NULL,                                                                 \
+		.gtior_setting.gtior = (0x0U),                                                     \
+	};                                                                                         \
+	static timer_cfg_t g_timer##inst##_cfg = {                                                 \
+		.mode = TIMER_MODE_PWM,                                                            \
+		.channel = DT_PROP(GPT(inst), channel),                                            \
+		.source_div = DT_ENUM_IDX(GPT(inst), prescaler),                                   \
+		.cycle_end_ipl = DT_IRQ_BY_NAME(GPT(inst), ovf, priority),                         \
+		.cycle_end_irq = DT_IRQ_BY_NAME(GPT(inst), ovf, irq),                              \
+		.p_extend = &g_timer##inst##_extend,                                               \
+	};                                                                                         \
+	static const struct pwm_rz_gpt_config pwm_rz_gpt_config_##inst = {                         \
+		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),                                    \
+		.fsp_api = &g_timer_on_gpt,                                                        \
+	};                                                                                         \
+	static struct pwm_rz_gpt_data pwm_rz_gpt_data_##inst = {                                   \
+		.fsp_cfg = &g_timer##inst##_cfg, .fsp_ctrl = &g_timer##inst##_ctrl};               \
+	static int pwm_rz_gpt_init_##inst(const struct device *dev)                                \
+	{                                                                                          \
+		PWM_RZ_IRQ_CONFIG_INIT(inst);                                                      \
+		int err = pwm_rz_gpt_init(dev);                                                    \
+		if (err != 0) {                                                                    \
+			return err;                                                                \
+		}                                                                                  \
+		return 0;                                                                          \
+	}                                                                                          \
+	DEVICE_DT_INST_DEFINE(inst, pwm_rz_gpt_init_##inst, NULL, &pwm_rz_gpt_data_##inst,         \
+			      &pwm_rz_gpt_config_##inst, POST_KERNEL, CONFIG_PWM_INIT_PRIORITY,    \
+			      &pwm_rz_gpt_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(PWM_RZG_INIT);
diff --git a/drivers/pwm/pwm_sam.c b/drivers/pwm/pwm_sam.c
index 8a5f52dd061..ed7b96ba9d4 100644
--- a/drivers/pwm/pwm_sam.c
+++ b/drivers/pwm/pwm_sam.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2019 Aurelien Jarno
+ * Copyright (c) 2021 Linaro Limited
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,7 +12,6 @@
 #include <zephyr/drivers/pwm.h>
 #include <zephyr/drivers/pinctrl.h>
 #include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
-#include <soc.h>
 
 #include <zephyr/logging/log.h>
 
@@ -22,6 +22,13 @@ LOG_MODULE_REGISTER(pwm_sam, CONFIG_PWM_LOG_LEVEL);
 #define PWMCHNUM_NUMBER PWMCH_NUM_NUMBER
 #endif
 
+/* The SAMV71 HALs change the name of the field, so we need to
+ * define it this way to match how the other SoC variants name it
+ */
+#if defined(CONFIG_SOC_ATMEL_SAMV71) || defined(CONFIG_SOC_ATMEL_SAMV71_REVB)
+#define PWM_CH_NUM PwmChNum
+#endif
+
 struct sam_pwm_config {
 	Pwm *regs;
 	const struct atmel_sam_pmc_config clock_cfg;
diff --git a/drivers/pwm/pwm_sam0_tc.c b/drivers/pwm/pwm_sam0_tc.c
index 655c0cb0491..871a14ab8ec 100644
--- a/drivers/pwm/pwm_sam0_tc.c
+++ b/drivers/pwm/pwm_sam0_tc.c
@@ -28,6 +28,8 @@
 #include <zephyr/drivers/pinctrl.h>
 #include <soc.h>
 
+/* clang-format off */
+
 /* Static configuration */
 struct pwm_sam0_config {
 	Tc *regs;
@@ -36,15 +38,10 @@ struct pwm_sam0_config {
 	uint8_t counter_size;
 	uint16_t prescaler;
 	uint32_t freq;
-
-#ifdef MCLK
 	volatile uint32_t *mclk;
 	uint32_t mclk_mask;
+	uint32_t gclk_gen;
 	uint16_t gclk_id;
-#else
-	uint32_t pm_apbcmask;
-	uint16_t gclk_clkctrl_id;
-#endif
 };
 
 #define COUNTER_8BITS 8U
@@ -133,19 +130,19 @@ static int pwm_sam0_set_cycles(const struct device *dev, uint32_t channel, uint3
 static int pwm_sam0_init(const struct device *dev)
 {
 	const struct pwm_sam0_config *const cfg = dev->config;
-	int retval;
-	Tc *regs = cfg->regs;
 	uint8_t counter_size = cfg->counter_size;
+	Tc *regs = cfg->regs;
+	int retval;
 
-	/* Enable the clocks */
-#ifdef MCLK
-	GCLK->PCHCTRL[cfg->gclk_id].reg =
-		GCLK_PCHCTRL_GEN_GCLK0 | GCLK_PCHCTRL_CHEN;
 	*cfg->mclk |= cfg->mclk_mask;
+
+#ifdef MCLK
+	GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_CHEN
+					| GCLK_PCHCTRL_GEN(cfg->gclk_gen);
 #else
-	GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 |
-			    GCLK_CLKCTRL_CLKEN;
-	PM->APBCMASK.reg |= cfg->pm_apbcmask;
+	GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
+			  | GCLK_CLKCTRL_GEN(cfg->gclk_gen)
+			  | GCLK_CLKCTRL_ID(cfg->gclk_id);
 #endif
 
 	retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
@@ -185,30 +182,32 @@ static DEVICE_API(pwm, pwm_sam0_driver_api) = {
 	.get_cycles_per_sec = pwm_sam0_get_cycles_per_sec,
 };
 
-#ifdef MCLK
-#define PWM_SAM0_INIT_CLOCKS(inst)                                                                 \
-	.mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(inst),                              \
-	.mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(inst, mclk, bit)),                            \
-	.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, periph_ch)
-#else
-#define PWM_SAM0_INIT_CLOCKS(inst)                                                                 \
-	.pm_apbcmask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(inst, pm, bit)),                            \
-	.gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, clkctrl_id)
-#endif
-
-#define PWM_SAM0_INIT(inst)                                                                        \
-	PINCTRL_DT_INST_DEFINE(inst);                                                              \
-	static const struct pwm_sam0_config pwm_sam0_config_##inst = {                             \
-		.regs = (Tc *)DT_INST_REG_ADDR(inst),                                              \
-		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),                                      \
-		.channels = DT_INST_PROP(inst, channels),                                          \
-		.counter_size = DT_INST_PROP(inst, counter_size),                                  \
-		.prescaler = UTIL_CAT(TC_CTRLA_PRESCALER_DIV, DT_INST_PROP(inst, prescaler)),      \
-		.freq = SOC_ATMEL_SAM0_GCLK0_FREQ_HZ / DT_INST_PROP(inst, prescaler),              \
-		PWM_SAM0_INIT_CLOCKS(inst),                                                        \
-	};                                                                                         \
-                                                                                                   \
-	DEVICE_DT_INST_DEFINE(inst, &pwm_sam0_init, NULL, NULL, &pwm_sam0_config_##inst,           \
-			      POST_KERNEL, CONFIG_PWM_TC_INIT_PRIORITY, &pwm_sam0_driver_api);
+#define ASSIGNED_CLOCKS_CELL_BY_NAME						\
+	ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_NAME
+
+#define PWM_SAM0_INIT(inst)							\
+	PINCTRL_DT_INST_DEFINE(inst);						\
+										\
+	static const struct pwm_sam0_config pwm_sam0_config_##inst = {		\
+		.regs = (Tc *)DT_INST_REG_ADDR(inst),				\
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),			\
+		.channels = DT_INST_PROP(inst, channels),			\
+		.counter_size = DT_INST_PROP(inst, counter_size),		\
+		.prescaler = UTIL_CAT(TC_CTRLA_PRESCALER_DIV,			\
+				      DT_INST_PROP(inst, prescaler)),		\
+		.freq = SOC_ATMEL_SAM0_GCLK0_FREQ_HZ /				\
+			DT_INST_PROP(inst, prescaler),		\
+		.gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(inst, gclk, gen),	\
+		.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, id),		\
+		.mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(inst),	\
+		.mclk_mask = ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(inst, bit),	\
+	};									\
+										\
+	DEVICE_DT_INST_DEFINE(inst, &pwm_sam0_init, NULL,			\
+			      NULL, &pwm_sam0_config_##inst,			\
+			      POST_KERNEL, CONFIG_PWM_TC_INIT_PRIORITY,		\
+			      &pwm_sam0_driver_api);
 
 DT_INST_FOREACH_STATUS_OKAY(PWM_SAM0_INIT)
+
+/* clang-format on */
diff --git a/drivers/pwm/pwm_sam0_tcc.c b/drivers/pwm/pwm_sam0_tcc.c
index 20b40c917da..1d5578c5a77 100644
--- a/drivers/pwm/pwm_sam0_tcc.c
+++ b/drivers/pwm/pwm_sam0_tcc.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2020 Google LLC.
+ * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,6 +18,8 @@
 #include <zephyr/drivers/pinctrl.h>
 #include <soc.h>
 
+/* clang-format off */
+
 /* Static configuration */
 struct pwm_sam0_config {
 	Tcc *regs;
@@ -25,15 +28,10 @@ struct pwm_sam0_config {
 	uint8_t counter_size;
 	uint16_t prescaler;
 	uint32_t freq;
-
-#ifdef MCLK
 	volatile uint32_t *mclk;
 	uint32_t mclk_mask;
+	uint32_t gclk_gen;
 	uint16_t gclk_id;
-#else
-	uint32_t pm_apbcmask;
-	uint16_t gclk_clkctrl_id;
-#endif
 };
 
 /* Wait for the peripheral to finish all commands */
@@ -106,15 +104,15 @@ static int pwm_sam0_init(const struct device *dev)
 	Tcc *regs = cfg->regs;
 	int retval;
 
-	/* Enable the clocks */
-#ifdef MCLK
-	GCLK->PCHCTRL[cfg->gclk_id].reg =
-		GCLK_PCHCTRL_GEN_GCLK0 | GCLK_PCHCTRL_CHEN;
 	*cfg->mclk |= cfg->mclk_mask;
+
+#ifdef MCLK
+	GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_CHEN
+					| GCLK_PCHCTRL_GEN(cfg->gclk_gen);
 #else
-	GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 |
-			    GCLK_CLKCTRL_CLKEN;
-	PM->APBCMASK.reg |= cfg->pm_apbcmask;
+	GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
+			  | GCLK_CLKCTRL_GEN(cfg->gclk_gen)
+			  | GCLK_CLKCTRL_ID(cfg->gclk_id);
 #endif
 
 	retval = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
@@ -140,34 +138,31 @@ static DEVICE_API(pwm, pwm_sam0_driver_api) = {
 	.get_cycles_per_sec = pwm_sam0_get_cycles_per_sec,
 };
 
-#ifdef MCLK
-#define PWM_SAM0_INIT_CLOCKS(inst)					       \
-	.mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(inst),	       \
-	.mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(inst, mclk, bit)),	       \
-	.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, periph_ch)
-#else
-#define PWM_SAM0_INIT_CLOCKS(inst)					       \
-	.pm_apbcmask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(inst, pm, bit)),	       \
-	.gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, clkctrl_id)
-#endif
-
-#define PWM_SAM0_INIT(inst)						       \
-	PINCTRL_DT_INST_DEFINE(inst);					       \
-	static const struct pwm_sam0_config pwm_sam0_config_##inst = {	       \
-		.regs = (Tcc *)DT_INST_REG_ADDR(inst),			       \
-		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),		       \
-		.channels = DT_INST_PROP(inst, channels),		       \
-		.counter_size = DT_INST_PROP(inst, counter_size),	       \
-		.prescaler = UTIL_CAT(TCC_CTRLA_PRESCALER_DIV,		       \
-				      DT_INST_PROP(inst, prescaler)),	       \
-		.freq = SOC_ATMEL_SAM0_GCLK0_FREQ_HZ /			       \
-			DT_INST_PROP(inst, prescaler),			       \
-		PWM_SAM0_INIT_CLOCKS(inst),				       \
-	};								       \
-									       \
-	DEVICE_DT_INST_DEFINE(inst, &pwm_sam0_init, NULL,		       \
-			    NULL, &pwm_sam0_config_##inst,		       \
-			    POST_KERNEL, CONFIG_PWM_INIT_PRIORITY,	       \
-			    &pwm_sam0_driver_api);
+#define ASSIGNED_CLOCKS_CELL_BY_NAME						\
+	ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_NAME
+
+#define PWM_SAM0_INIT(inst)							\
+	PINCTRL_DT_INST_DEFINE(inst);						\
+	static const struct pwm_sam0_config pwm_sam0_config_##inst = {		\
+		.regs = (Tcc *)DT_INST_REG_ADDR(inst),				\
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),			\
+		.channels = DT_INST_PROP(inst, channels),			\
+		.counter_size = DT_INST_PROP(inst, counter_size),		\
+		.prescaler = UTIL_CAT(TCC_CTRLA_PRESCALER_DIV,			\
+				      DT_INST_PROP(inst, prescaler)),		\
+		.freq = SOC_ATMEL_SAM0_GCLK0_FREQ_HZ /				\
+			DT_INST_PROP(inst, prescaler),				\
+		.gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(inst, gclk, gen),	\
+		.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, id),		\
+		.mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(inst),	\
+		.mclk_mask = ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(inst, bit),	\
+	};									\
+										\
+	DEVICE_DT_INST_DEFINE(inst, &pwm_sam0_init, NULL,			\
+			      NULL, &pwm_sam0_config_##inst,			\
+			      POST_KERNEL, CONFIG_PWM_INIT_PRIORITY,		\
+			      &pwm_sam0_driver_api);
 
 DT_INST_FOREACH_STATUS_OKAY(PWM_SAM0_INIT)
+
+/* clang-format on */
diff --git a/drivers/pwm/pwm_shell.c b/drivers/pwm/pwm_shell.c
index e7cbcc0391d..e827710286e 100644
--- a/drivers/pwm/pwm_shell.c
+++ b/drivers/pwm/pwm_shell.c
@@ -126,14 +126,14 @@ static int cmd_nsec(const struct shell *sh, size_t argc, char **argv)
 	return 0;
 }
 
-static bool device_is_pwm_and_ready(const struct device *dev)
+static bool device_is_pwm(const struct device *dev)
 {
-	return device_is_ready(dev) && DEVICE_API_IS(pwm, dev);
+	return DEVICE_API_IS(pwm, dev);
 }
 
 static void device_name_get(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_filter(idx, device_is_pwm_and_ready);
+	const struct device *dev = shell_device_filter(idx, device_is_pwm);
 
 	entry->syntax = (dev != NULL) ? dev->name : NULL;
 	entry->handler = NULL;
diff --git a/drivers/pwm/pwm_silabs_siwx91x.c b/drivers/pwm/pwm_silabs_siwx91x.c
new file mode 100644
index 00000000000..520776a3717
--- /dev/null
+++ b/drivers/pwm/pwm_silabs_siwx91x.c
@@ -0,0 +1,236 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <zephyr/irq.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/pwm.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/types.h>
+#include "sl_si91x_pwm.h"
+
+#define DT_DRV_COMPAT silabs_siwx91x_pwm
+
+#define PWM_CHANNELS  4
+#define DEFAULT_VALUE 0xFF
+
+struct pwm_siwx91x_channel_config {
+	uint8_t duty_cycle;
+	uint32_t frequency;
+	bool is_chan_active;
+};
+
+struct pwm_siwx91x_config {
+	/* Pointer to the clock device structure */
+	const struct device *clock_dev;
+	/* Clock control subsystem */
+	clock_control_subsys_t clock_subsys;
+	/* Pointer to the pin control device configuration */
+	const struct pinctrl_dev_config *pcfg;
+	/* Prescaler information of the channels */
+	uint8_t ch_prescaler[PWM_CHANNELS];
+	/* Common PWM polarity for all the channels */
+	uint8_t pwm_polarity;
+};
+
+struct pwm_siwx91x_data {
+	struct pwm_siwx91x_channel_config pwm_channel_cfg[PWM_CHANNELS];
+};
+
+/* Function to convert prescaler value to a programmable reg value */
+static int siwx91x_prescale_convert(uint8_t prescale)
+{
+	switch (prescale) {
+	case 1:
+		return SL_TIME_PERIOD_PRESCALE_1;
+	case 2:
+		return SL_TIME_PERIOD_PRESCALE_2;
+	case 4:
+		return SL_TIME_PERIOD_PRESCALE_4;
+	case 8:
+		return SL_TIME_PERIOD_PRESCALE_8;
+	case 16:
+		return SL_TIME_PERIOD_PRESCALE_16;
+	case 32:
+		return SL_TIME_PERIOD_PRESCALE_32;
+	case 64:
+		return SL_TIME_PERIOD_PRESCALE_64;
+	default:
+		return -EINVAL;
+	}
+}
+
+/* Program PWM channel with the default configurations */
+static int siwx91x_default_channel_config(const struct device *dev, uint32_t channel)
+{
+	const struct pwm_siwx91x_config *config = dev->config;
+	int prescale_reg_value = siwx91x_prescale_convert(config->ch_prescaler[channel]);
+	int ret;
+
+	if (prescale_reg_value < 0) {
+		return -EINVAL;
+	}
+
+	ret = sl_si91x_pwm_set_output_mode(SL_MODE_INDEPENDENT, channel);
+	if (ret) {
+		return -EINVAL;
+	}
+
+	ret = sl_si91x_pwm_set_base_timer_mode(SL_FREE_RUN_MODE, channel);
+	if (ret) {
+		return -EINVAL;
+	}
+
+	ret = sl_si91x_pwm_control_base_timer(SL_BASE_TIMER_EACH_CHANNEL);
+	if (ret) {
+		return -EINVAL;
+	}
+
+	ret = sl_si91x_pwm_control_period(SL_TIME_PERIOD_POSTSCALE_1_1, prescale_reg_value,
+					  channel);
+	if (ret) {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int pwm_siwx91x_set_cycles(const struct device *dev, uint32_t channel,
+				  uint32_t period_cycles, uint32_t pulse_cycles, pwm_flags_t flags)
+{
+	const struct pwm_siwx91x_config *config = dev->config;
+	struct pwm_siwx91x_data *data = dev->data;
+	uint32_t prev_period;
+	uint32_t duty_cycle;
+	int ret;
+
+	if (channel >= ARRAY_SIZE(data->pwm_channel_cfg)) {
+		return -EINVAL;
+	}
+
+	if (config->pwm_polarity != flags) {
+		/* Polarity mismatch */
+		return -ENOTSUP;
+	}
+
+	if (data->pwm_channel_cfg[channel].is_chan_active == false) {
+		/* Configure the channel with default parameters */
+		ret = siwx91x_default_channel_config(dev, channel);
+		if (ret) {
+			return -EINVAL;
+		}
+	}
+
+	ret = sl_si91x_pwm_get_time_period(channel, (uint16_t *)&prev_period);
+	if (ret) {
+		return -EINVAL;
+	}
+
+	if (period_cycles != prev_period) {
+		ret = sl_si91x_pwm_set_time_period(channel, period_cycles, 0);
+		if (ret) {
+			/* Programmed value must be out of range (>65535) */
+			return -EINVAL;
+		}
+	}
+
+	/* Calculate the duty cycle */
+	duty_cycle = pulse_cycles * 100;
+	duty_cycle /= period_cycles;
+
+	if (duty_cycle != data->pwm_channel_cfg[channel].duty_cycle) {
+		ret = sl_si91x_pwm_set_duty_cycle(pulse_cycles, channel);
+		if (ret) {
+			return -EINVAL;
+		}
+		data->pwm_channel_cfg[channel].duty_cycle = duty_cycle;
+	}
+
+	if (data->pwm_channel_cfg[channel].is_chan_active == false) {
+		/* Start PWM after configuring the channel for first time */
+		ret = sl_si91x_pwm_start(channel);
+		if (ret) {
+			return -EINVAL;
+		}
+		data->pwm_channel_cfg[channel].is_chan_active = true;
+	}
+
+	return 0;
+}
+
+static int pwm_siwx91x_get_cycles_per_sec(const struct device *dev, uint32_t channel,
+					  uint64_t *cycles)
+{
+	struct pwm_siwx91x_data *data = dev->data;
+
+	if (channel >= ARRAY_SIZE(data->pwm_channel_cfg)) {
+		return -EINVAL;
+	}
+
+	*cycles = (uint64_t)data->pwm_channel_cfg[channel].frequency;
+
+	return 0;
+}
+
+static int pwm_siwx91x_init(const struct device *dev)
+{
+	const struct pwm_siwx91x_config *config = dev->config;
+	struct pwm_siwx91x_data *data = dev->data;
+	bool polarity_inverted = (config->pwm_polarity == PWM_POLARITY_INVERTED);
+	uint32_t pwm_frequency;
+	int ret;
+
+	ret = clock_control_on(config->clock_dev, config->clock_subsys);
+	if (ret) {
+		return ret;
+	}
+
+	ret = clock_control_get_rate(config->clock_dev, config->clock_subsys, &pwm_frequency);
+	if (ret) {
+		return ret;
+	}
+
+	ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret) {
+		return ret;
+	}
+
+	ARRAY_FOR_EACH(data->pwm_channel_cfg, i) {
+		data->pwm_channel_cfg[i].frequency = pwm_frequency / config->ch_prescaler[i];
+	}
+
+	ret = sl_si91x_pwm_set_output_polarity(polarity_inverted, !polarity_inverted);
+	if (ret) {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(pwm, pwm_siwx91x_driver_api) = {
+	.set_cycles = pwm_siwx91x_set_cycles,
+	.get_cycles_per_sec = pwm_siwx91x_get_cycles_per_sec,
+};
+
+#define SIWX91X_PWM_INIT(inst)                                                                     \
+	PINCTRL_DT_INST_DEFINE(inst);                                                              \
+	static struct pwm_siwx91x_data pwm_siwx91x_data_##inst;                                    \
+	static const struct pwm_siwx91x_config pwm_config_##inst = {                               \
+		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)),                             \
+		.clock_subsys = (clock_control_subsys_t)DT_INST_PHA(inst, clocks, clkid),          \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),                                      \
+		.ch_prescaler = DT_INST_PROP(inst, silabs_ch_prescaler),                           \
+		.pwm_polarity = DT_INST_PROP(inst, silabs_pwm_polarity),                           \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(inst, &pwm_siwx91x_init, NULL, &pwm_siwx91x_data_##inst,             \
+			      &pwm_config_##inst, PRE_KERNEL_1, CONFIG_PWM_INIT_PRIORITY,          \
+			      &pwm_siwx91x_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(SIWX91X_PWM_INIT)
diff --git a/drivers/pwm/pwm_stm32.c b/drivers/pwm/pwm_stm32.c
index 3102d73149f..708709bf2ef 100644
--- a/drivers/pwm/pwm_stm32.c
+++ b/drivers/pwm/pwm_stm32.c
@@ -116,16 +116,19 @@ static const uint32_t ch2ll[TIMER_MAX_CH] = {
 #endif
 };
 
-/** Some stm32 mcus have complementary channels : 3 or 4 */
+/** STM32 MCUs have between 1 and 4 complementary channels */
 static const uint32_t ch2ll_n[] = {
 #if defined(LL_TIM_CHANNEL_CH1N)
 	LL_TIM_CHANNEL_CH1N,
+#if defined(LL_TIM_CHANNEL_CH2N)
 	LL_TIM_CHANNEL_CH2N,
+#if defined(LL_TIM_CHANNEL_CH3N)
 	LL_TIM_CHANNEL_CH3N,
 #if defined(LL_TIM_CHANNEL_CH4N)
-/** stm32g4x and stm32u5x have 4 complementary channels */
 	LL_TIM_CHANNEL_CH4N,
 #endif /* LL_TIM_CHANNEL_CH4N */
+#endif /* LL_TIM_CHANNEL_CH3N */
+#endif /* LL_TIM_CHANNEL_CH2N */
 #endif /* LL_TIM_CHANNEL_CH1N */
 };
 /** Maximum number of complemented timer channels is ARRAY_SIZE(ch2ll_n)*/
@@ -231,7 +234,10 @@ static int get_tim_clk(const struct stm32_pclken *pclken, uint32_t *tim_clk)
 		return r;
 	}
 
-#if defined(CONFIG_SOC_SERIES_STM32H7X)
+#if defined(CONFIG_SOC_SERIES_STM32WB0X)
+	/* Timers are clocked by SYSCLK on STM32WB0 */
+	apb_psc = 1;
+#elif defined(CONFIG_SOC_SERIES_STM32H7X)
 	if (pclken->bus == STM32_CLOCK_BUS_APB1) {
 		apb_psc = STM32_D2PPRE1;
 	} else {
diff --git a/drivers/regulator/CMakeLists.txt b/drivers/regulator/CMakeLists.txt
index 7ed90137c3f..ed5a1996da9 100644
--- a/drivers/regulator/CMakeLists.txt
+++ b/drivers/regulator/CMakeLists.txt
@@ -4,7 +4,7 @@
 zephyr_library()
 
 zephyr_library_sources(regulator_common.c)
-zephyr_library_sources_ifdef(CONFIG_REGULATOR_AXP192 regulator_axp192.c)
+zephyr_library_sources_ifdef(CONFIG_REGULATOR_AXP192_AXP2101 regulator_axp192.c)
 zephyr_library_sources_ifdef(CONFIG_REGULATOR_ADP5360 regulator_adp5360.c)
 zephyr_library_sources_ifdef(CONFIG_REGULATOR_CP9314 regulator_cp9314.c)
 zephyr_library_sources_ifdef(CONFIG_REGULATOR_DA1469X regulator_da1469x.c)
@@ -17,6 +17,7 @@ zephyr_library_sources_ifdef(CONFIG_REGULATOR_NPM1300 regulator_npm1300.c)
 zephyr_library_sources_ifdef(CONFIG_REGULATOR_NPM2100 regulator_npm2100.c)
 zephyr_library_sources_ifdef(CONFIG_REGULATOR_NPM6001 regulator_npm6001.c)
 zephyr_library_sources_ifdef(CONFIG_REGULATOR_PCA9420 regulator_pca9420.c)
+zephyr_library_sources_ifdef(CONFIG_REGULATOR_PF1550 regulator_pf1550.c)
 zephyr_library_sources_ifdef(CONFIG_REGULATOR_SHELL regulator_shell.c)
 zephyr_library_sources_ifdef(CONFIG_REGULATOR_RPI_PICO regulator_rpi_pico.c)
 zephyr_library_sources_ifdef(CONFIG_REGULATOR_NXP_VREF regulator_nxp_vref.c)
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index d4b70e6b76a..dc331b2139d 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -39,6 +39,7 @@ source "drivers/regulator/Kconfig.npm1300"
 source "drivers/regulator/Kconfig.npm2100"
 source "drivers/regulator/Kconfig.npm6001"
 source "drivers/regulator/Kconfig.pca9420"
+source "drivers/regulator/Kconfig.pf1550"
 source "drivers/regulator/Kconfig.rpi_pico"
 source "drivers/regulator/Kconfig.nxp_vref"
 source "drivers/regulator/Kconfig.mpm54304"
diff --git a/drivers/regulator/Kconfig.axp192 b/drivers/regulator/Kconfig.axp192
index b56868ccdb7..42a28044bfc 100644
--- a/drivers/regulator/Kconfig.axp192
+++ b/drivers/regulator/Kconfig.axp192
@@ -1,23 +1,23 @@
 # Copyright (c) 2023 Martin Kiepfer
 # SPDX-License-Identifier: Apache-2.0
 
-config REGULATOR_AXP192
-	bool "X-Power AXP192 PMIC regulator driver"
+config REGULATOR_AXP192_AXP2101
+	bool "X-Powers AXP192/AXP2101 PMIC regulator driver"
 	default y
-	depends on DT_HAS_X_POWERS_AXP192_REGULATOR_ENABLED
-	depends on DT_HAS_X_POWERS_AXP192_ENABLED
+	depends on DT_HAS_X_POWERS_AXP192_REGULATOR_ENABLED || DT_HAS_X_POWERS_AXP2101_REGULATOR_ENABLED
+	depends on DT_HAS_X_POWERS_AXP192_ENABLED || DT_HAS_X_POWERS_AXP2101_ENABLED
 	select I2C
 	select MFD
 	help
 	  Enable the AXP PMIC regulator driver
 
-if REGULATOR_AXP192
+if REGULATOR_AXP192_AXP2101
 
-config REGULATOR_AXP192_INIT_PRIORITY
-	int "AXP192 regulator driver init priority"
+config REGULATOR_AXP192_AXP2101_INIT_PRIORITY
+	int "AXP192/AXP2101 regulator driver init priority"
 	default 86
 	help
-	  Init priority for the axp192 regulator driver. It must be
+	  Init priority for the axp192/axp2101 regulator driver. It must be
 	  greater than MFD_INIT_PRIORITY.
 
 endif
diff --git a/drivers/regulator/Kconfig.pf1550 b/drivers/regulator/Kconfig.pf1550
new file mode 100644
index 00000000000..667a4b411ee
--- /dev/null
+++ b/drivers/regulator/Kconfig.pf1550
@@ -0,0 +1,11 @@
+# Copyright (c) 2024 Arduino SA
+# SPDX-License-Identifier: Apache-2.0
+
+config REGULATOR_PF1550
+	bool "NXP PF1550 PMIC regulator driver"
+	default y
+	depends on DT_HAS_NXP_PF1550_REGULATOR_ENABLED
+	select I2C
+	select MFD
+	help
+	  Enable the NXP PF1550 PMIC regulator driver
diff --git a/drivers/regulator/Kconfig.rpi_pico b/drivers/regulator/Kconfig.rpi_pico
index fe97a524464..1900cf53381 100644
--- a/drivers/regulator/Kconfig.rpi_pico
+++ b/drivers/regulator/Kconfig.rpi_pico
@@ -2,18 +2,18 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config REGULATOR_RPI_PICO
-	bool "RaspberryPi Pico regulator driver"
+	bool "Raspberry Pi Pico regulator driver"
 	default y
 	depends on DT_HAS_RASPBERRYPI_CORE_SUPPLY_REGULATOR_ENABLED
 	help
-	  Enable support for the RaspberryPi Pico regulator.
+	  Enable support for the Raspberry Pi Pico regulator.
 
 if REGULATOR_RPI_PICO
 
 config REGULATOR_RPI_PICO_INIT_PRIORITY
-	int "RaspberryPi Pico regulator driver init priority"
+	int "Raspberry Pi Pico regulator driver init priority"
 	default KERNEL_INIT_PRIORITY_DEVICE
 	help
-	  Init priority for the RaspberryPi Pico regulator driver.
+	  Init priority for the Raspberry Pi Pico regulator driver.
 
 endif
diff --git a/drivers/regulator/regulator_axp192.c b/drivers/regulator/regulator_axp192.c
index c6e09682384..8d37287a7ef 100644
--- a/drivers/regulator/regulator_axp192.c
+++ b/drivers/regulator/regulator_axp192.c
@@ -1,11 +1,10 @@
 /*
  * Copyright (c) 2021 NXP
  * Copyright (c) 2023 Martin Kiepfer <mrmarteng@teleschirm.org>
+ * Copyright (c) 2024 Lothar Felten <lothar.felten@gmail.com>
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#define DT_DRV_COMPAT x_powers_axp192_regulator
-
 #include <errno.h>
 
 #include <zephyr/kernel.h>
@@ -20,7 +19,7 @@
 
 LOG_MODULE_REGISTER(regulator_axp192, CONFIG_REGULATOR_LOG_LEVEL);
 
-/* Output control registers */
+/* AXP192 register defines */
 #define AXP192_REG_EXTEN_DCDC2_CONTROL   0x10U
 #define AXP192_REG_DCDC123_LDO23_CONTROL 0x12U
 #define AXP192_REG_DCDC2_VOLTAGE         0x23U
@@ -32,6 +31,39 @@ LOG_MODULE_REGISTER(regulator_axp192, CONFIG_REGULATOR_LOG_LEVEL);
 #define AXP192_REG_GPIO0_CONTROL         0x90U
 #define AXP192_REG_LDOIO0_VOLTAGE        0x91U
 
+/* AXP2101 register defines */
+#define AXP2101_REG_CHGLED            0x69U
+#define AXP2101_REG_DCDC12345_CONTROL 0x80U
+#define AXP2101_REG_DCDCS_PWM_CONTROL 0x81U
+#define AXP2101_REG_DCDC1_VOLTAGE     0x82U
+#define AXP2101_REG_DCDC2_VOLTAGE     0x83U
+#define AXP2101_REG_DCDC3_VOLTAGE     0x84U
+#define AXP2101_REG_DCDC4_VOLTAGE     0x85U
+#define AXP2101_REG_DCDC5_VOLTAGE     0x86U
+#define AXP2101_REG_LDOGRP1_CONTROL   0x90U
+#define AXP2101_REG_LDOGRP2_CONTROL   0x91U
+#define AXP2101_REG_ALDO1_VOLTAGE     0x92U
+#define AXP2101_REG_ALDO2_VOLTAGE     0x93U
+#define AXP2101_REG_ALDO3_VOLTAGE     0x94U
+#define AXP2101_REG_ALDO4_VOLTAGE     0x95U
+#define AXP2101_REG_BLDO1_VOLTAGE     0x96U
+#define AXP2101_REG_BLDO2_VOLTAGE     0x97U
+#define AXP2101_REG_CPUSLDO_VOLTAGE   0x98U
+#define AXP2101_REG_DLDO1_VOLTAGE     0x99U
+#define AXP2101_REG_DLDO2_VOLTAGE     0x9AU
+
+#define AXP2101_CHGLED_CTRL_MASK   0x3
+#define AXP2101_CHGLED_CTRL_OFFSET 1
+
+#define AXP2101_VBUS_CFG_REG                0
+#define AXP2101_VBUS_CFG_VAL_VBUSEN_DISABLE 0
+
+#define AXP_NODE_HAS_CHILD(node, child) DT_NODE_HAS_STATUS_OKAY(DT_CHILD(node, child)) |
+#define AXP192_ANY_HAS_CHILD(child)                                                                \
+	(DT_FOREACH_STATUS_OKAY_VARGS(x_powers_axp192_regulator, AXP_NODE_HAS_CHILD, child) 0)
+#define AXP2101_ANY_HAS_CHILD(child)                                                               \
+	(DT_FOREACH_STATUS_OKAY_VARGS(x_powers_axp2101_regulator, AXP_NODE_HAS_CHILD, child) 0)
+
 struct regulator_axp192_desc {
 	const uint8_t enable_reg;
 	const uint8_t enable_mask;
@@ -56,15 +88,13 @@ struct regulator_axp192_config {
 	const struct regulator_axp192_desc *desc;
 	const struct device *mfd;
 	const struct i2c_dt_spec i2c;
-
-	LOG_INSTANCE_PTR_DECLARE(log);
 };
 
-static const struct linear_range dcdc1_ranges[] = {
+static const struct linear_range axp192_dcdc1_ranges[] = {
 	LINEAR_RANGE_INIT(700000U, 25000U, 0x00U, 0x7FU),
 };
 
-__maybe_unused static const struct regulator_axp192_desc dcdc1_desc = {
+__maybe_unused static const struct regulator_axp192_desc axp192_dcdc1_desc = {
 	.enable_reg = AXP192_REG_DCDC123_LDO23_CONTROL,
 	.enable_mask = 0x01U,
 	.enable_val = 0x01U,
@@ -75,15 +105,15 @@ __maybe_unused static const struct regulator_axp192_desc dcdc1_desc = {
 	.workmode_reg = AXP192_REG_DCDC123_WORKMODE,
 	.workmode_mask = 0x08U,
 	.workmode_pwm_val = 0x08U,
-	.ranges = dcdc1_ranges,
-	.num_ranges = ARRAY_SIZE(dcdc1_ranges),
+	.ranges = axp192_dcdc1_ranges,
+	.num_ranges = ARRAY_SIZE(axp192_dcdc1_ranges),
 };
 
-static const struct linear_range dcdc2_ranges[] = {
+static const struct linear_range axp192_dcdc2_ranges[] = {
 	LINEAR_RANGE_INIT(700000U, 25000U, 0x00U, 0x3FU),
 };
 
-__maybe_unused static const struct regulator_axp192_desc dcdc2_desc = {
+__maybe_unused static const struct regulator_axp192_desc axp192_dcdc2_desc = {
 	.enable_reg = AXP192_REG_EXTEN_DCDC2_CONTROL,
 	.enable_mask = 0x01U,
 	.enable_val = 0x01U,
@@ -94,15 +124,15 @@ __maybe_unused static const struct regulator_axp192_desc dcdc2_desc = {
 	.workmode_reg = AXP192_REG_DCDC123_WORKMODE,
 	.workmode_mask = 0x04U,
 	.workmode_pwm_val = 0x04U,
-	.ranges = dcdc2_ranges,
-	.num_ranges = ARRAY_SIZE(dcdc2_ranges),
+	.ranges = axp192_dcdc2_ranges,
+	.num_ranges = ARRAY_SIZE(axp192_dcdc2_ranges),
 };
 
-static const struct linear_range dcdc3_ranges[] = {
+static const struct linear_range axp192_dcdc3_ranges[] = {
 	LINEAR_RANGE_INIT(700000U, 25000U, 0x00U, 0x7FU),
 };
 
-__maybe_unused static const struct regulator_axp192_desc dcdc3_desc = {
+__maybe_unused static const struct regulator_axp192_desc axp192_dcdc3_desc = {
 	.enable_reg = AXP192_REG_DCDC123_LDO23_CONTROL,
 	.enable_mask = 0x02U,
 	.enable_val = 0x02U,
@@ -113,15 +143,15 @@ __maybe_unused static const struct regulator_axp192_desc dcdc3_desc = {
 	.workmode_reg = AXP192_REG_DCDC123_WORKMODE,
 	.workmode_mask = 0x02U,
 	.workmode_pwm_val = 0x02U,
-	.ranges = dcdc3_ranges,
-	.num_ranges = ARRAY_SIZE(dcdc3_ranges),
+	.ranges = axp192_dcdc3_ranges,
+	.num_ranges = ARRAY_SIZE(axp192_dcdc3_ranges),
 };
 
-static const struct linear_range ldoio0_ranges[] = {
+static const struct linear_range axp192_ldoio0_ranges[] = {
 	LINEAR_RANGE_INIT(1800000u, 100000u, 0x00u, 0x0Fu),
 };
 
-__maybe_unused static const struct regulator_axp192_desc ldoio0_desc = {
+__maybe_unused static const struct regulator_axp192_desc axp192_ldoio0_desc = {
 	.enable_reg = AXP192_REG_GPIO0_CONTROL,
 	.enable_mask = 0x07u,
 	.enable_val = 0x03u,
@@ -131,15 +161,15 @@ __maybe_unused static const struct regulator_axp192_desc ldoio0_desc = {
 	.max_ua = 50000u,
 	.workmode_reg = 0u,
 	.workmode_mask = 0u,
-	.ranges = ldoio0_ranges,
-	.num_ranges = ARRAY_SIZE(ldoio0_ranges),
+	.ranges = axp192_ldoio0_ranges,
+	.num_ranges = ARRAY_SIZE(axp192_ldoio0_ranges),
 };
 
-static const struct linear_range ldo2_ranges[] = {
+static const struct linear_range axp192_ldo2_ranges[] = {
 	LINEAR_RANGE_INIT(1800000U, 100000U, 0x00U, 0x0FU),
 };
 
-__maybe_unused static const struct regulator_axp192_desc ldo2_desc = {
+__maybe_unused static const struct regulator_axp192_desc axp192_ldo2_desc = {
 	.enable_reg = AXP192_REG_DCDC123_LDO23_CONTROL,
 	.enable_mask = 0x04U,
 	.enable_val = 0x04U,
@@ -149,15 +179,15 @@ __maybe_unused static const struct regulator_axp192_desc ldo2_desc = {
 	.max_ua = 200000U,
 	.workmode_reg = 0U,
 	.workmode_mask = 0U,
-	.ranges = ldo2_ranges,
-	.num_ranges = ARRAY_SIZE(ldo2_ranges),
+	.ranges = axp192_ldo2_ranges,
+	.num_ranges = ARRAY_SIZE(axp192_ldo2_ranges),
 };
 
-static const struct linear_range ldo3_ranges[] = {
+static const struct linear_range axp192_ldo3_ranges[] = {
 	LINEAR_RANGE_INIT(1800000U, 100000U, 0x00U, 0x0FU),
 };
 
-__maybe_unused static const struct regulator_axp192_desc ldo3_desc = {
+__maybe_unused static const struct regulator_axp192_desc axp192_ldo3_desc = {
 	.enable_reg = AXP192_REG_DCDC123_LDO23_CONTROL,
 	.enable_mask = 0x08U,
 	.enable_val = 0x08U,
@@ -167,8 +197,238 @@ __maybe_unused static const struct regulator_axp192_desc ldo3_desc = {
 	.max_ua = 200000U,
 	.workmode_reg = 0U,
 	.workmode_mask = 0U,
-	.ranges = ldo3_ranges,
-	.num_ranges = ARRAY_SIZE(ldo3_ranges),
+	.ranges = axp192_ldo3_ranges,
+	.num_ranges = ARRAY_SIZE(axp192_ldo3_ranges),
+};
+
+static const struct linear_range axp2101_dcdc1_ranges[] = {
+	LINEAR_RANGE_INIT(1500000U, 100000U, 0U, 19U),
+};
+
+__maybe_unused static const struct regulator_axp192_desc axp2101_dcdc1_desc = {
+	.enable_reg = AXP2101_REG_DCDC12345_CONTROL,
+	.enable_mask = 0x01U,
+	.enable_val = 0x01U,
+	.vsel_reg = AXP2101_REG_DCDC1_VOLTAGE,
+	.vsel_mask = 0x1FU,
+	.vsel_bitpos = 0U,
+	.max_ua = 2000000U,
+	.ranges = axp2101_dcdc1_ranges,
+	.num_ranges = ARRAY_SIZE(axp2101_dcdc1_ranges),
+	.workmode_reg = AXP2101_REG_DCDCS_PWM_CONTROL,
+	.workmode_mask = BIT(2),
+	.workmode_pwm_val = BIT(2),
+};
+
+static const struct linear_range axp2101_dcdc2_ranges[] = {
+	LINEAR_RANGE_INIT(500000U, 10000U, 0U, 70U),
+	LINEAR_RANGE_INIT(1220000U, 20000U, 71U, 87U),
+};
+
+__maybe_unused static const struct regulator_axp192_desc axp2101_dcdc2_desc = {
+	.enable_reg = AXP2101_REG_DCDC12345_CONTROL,
+	.enable_mask = 0x02U,
+	.enable_val = 0x02U,
+	.vsel_reg = AXP2101_REG_DCDC2_VOLTAGE,
+	.vsel_mask = 0x7FU,
+	.vsel_bitpos = 0U,
+	.max_ua = 2000000U,
+	.ranges = axp2101_dcdc2_ranges,
+	.num_ranges = ARRAY_SIZE(axp2101_dcdc2_ranges),
+	.workmode_reg = AXP2101_REG_DCDCS_PWM_CONTROL,
+	.workmode_mask = BIT(3),
+	.workmode_pwm_val = BIT(3),
+};
+
+static const struct linear_range axp2101_dcdc3_ranges[] = {
+	LINEAR_RANGE_INIT(500000U, 10000U, 0U, 70U),
+	LINEAR_RANGE_INIT(1220000U, 20000U, 71U, 87U),
+	LINEAR_RANGE_INIT(1600000U, 100000U, 88U, 106U),
+};
+
+__maybe_unused static const struct regulator_axp192_desc axp2101_dcdc3_desc = {
+	.enable_reg = AXP2101_REG_DCDC12345_CONTROL,
+	.enable_mask = 0x04U,
+	.enable_val = 0x04U,
+	.vsel_reg = AXP2101_REG_DCDC3_VOLTAGE,
+	.vsel_mask = 0x7FU,
+	.vsel_bitpos = 0U,
+	.max_ua = 2000000U,
+	.ranges = axp2101_dcdc3_ranges,
+	.num_ranges = ARRAY_SIZE(axp2101_dcdc3_ranges),
+	.workmode_reg = AXP2101_REG_DCDCS_PWM_CONTROL,
+	.workmode_mask = BIT(4),
+	.workmode_pwm_val = BIT(4),
+};
+
+static const struct linear_range axp2101_dcdc4_ranges[] = {
+	LINEAR_RANGE_INIT(500000U, 10000U, 0U, 70U),
+	LINEAR_RANGE_INIT(1220000U, 20000U, 71U, 102U),
+};
+
+__maybe_unused static const struct regulator_axp192_desc axp2101_dcdc4_desc = {
+	.enable_reg = AXP2101_REG_DCDC12345_CONTROL,
+	.enable_mask = 0x08U,
+	.enable_val = 0x08U,
+	.vsel_reg = AXP2101_REG_DCDC4_VOLTAGE,
+	.vsel_mask = 0x7FU,
+	.vsel_bitpos = 0U,
+	.max_ua = 1500000U,
+	.ranges = axp2101_dcdc4_ranges,
+	.num_ranges = ARRAY_SIZE(axp2101_dcdc4_ranges),
+	.workmode_reg = AXP2101_REG_DCDCS_PWM_CONTROL,
+	.workmode_mask = BIT(5),
+	.workmode_pwm_val = BIT(5),
+};
+
+static const struct linear_range axp2101_dcdc5_ranges[] = {
+	LINEAR_RANGE_INIT(1400000U, 100000U, 0U, 23U),
+};
+
+__maybe_unused static const struct regulator_axp192_desc axp2101_dcdc5_desc = {
+	.enable_reg = AXP2101_REG_DCDC12345_CONTROL,
+	.enable_mask = 0x10U,
+	.enable_val = 0x10U,
+	.vsel_reg = AXP2101_REG_DCDC5_VOLTAGE,
+	.vsel_mask = 0x1FU,
+	.vsel_bitpos = 0U,
+	.max_ua = 1000000U,
+	.ranges = axp2101_dcdc5_ranges,
+	.num_ranges = ARRAY_SIZE(axp2101_dcdc5_ranges),
+};
+
+static const struct linear_range axp2101_abldox_ranges[] = {
+	LINEAR_RANGE_INIT(500000U, 100000U, 0U, 30U),
+};
+
+__maybe_unused static const struct regulator_axp192_desc axp2101_aldo1_desc = {
+	.enable_reg = AXP2101_REG_LDOGRP1_CONTROL,
+	.enable_mask = 0x01U,
+	.enable_val = 0x01U,
+	.vsel_reg = AXP2101_REG_ALDO1_VOLTAGE,
+	.vsel_mask = 0x1FU,
+	.vsel_bitpos = 0U,
+	.max_ua = 300000U,
+	.ranges = axp2101_abldox_ranges,
+	.num_ranges = ARRAY_SIZE(axp2101_abldox_ranges),
+};
+
+__maybe_unused static const struct regulator_axp192_desc axp2101_aldo2_desc = {
+	.enable_reg = AXP2101_REG_LDOGRP1_CONTROL,
+	.enable_mask = 0x02U,
+	.enable_val = 0x02U,
+	.vsel_reg = AXP2101_REG_ALDO2_VOLTAGE,
+	.vsel_mask = 0x1FU,
+	.vsel_bitpos = 0U,
+	.max_ua = 300000U,
+	.ranges = axp2101_abldox_ranges,
+	.num_ranges = ARRAY_SIZE(axp2101_abldox_ranges),
+};
+
+__maybe_unused static const struct regulator_axp192_desc axp2101_aldo3_desc = {
+	.enable_reg = AXP2101_REG_LDOGRP1_CONTROL,
+	.enable_mask = 0x04U,
+	.enable_val = 0x04U,
+	.vsel_reg = AXP2101_REG_ALDO3_VOLTAGE,
+	.vsel_mask = 0x1FU,
+	.vsel_bitpos = 0U,
+	.max_ua = 300000U,
+	.ranges = axp2101_abldox_ranges,
+	.num_ranges = ARRAY_SIZE(axp2101_abldox_ranges),
+};
+
+__maybe_unused static const struct regulator_axp192_desc axp2101_aldo4_desc = {
+	.enable_reg = AXP2101_REG_LDOGRP1_CONTROL,
+	.enable_mask = 0x08U,
+	.enable_val = 0x08U,
+	.vsel_reg = AXP2101_REG_ALDO4_VOLTAGE,
+	.vsel_mask = 0x1FU,
+	.vsel_bitpos = 0U,
+	.max_ua = 300000U,
+	.ranges = axp2101_abldox_ranges,
+	.num_ranges = ARRAY_SIZE(axp2101_abldox_ranges),
+};
+
+__maybe_unused static const struct regulator_axp192_desc axp2101_bldo1_desc = {
+	.enable_reg = AXP2101_REG_LDOGRP1_CONTROL,
+	.enable_mask = 0x10U,
+	.enable_val = 0x10U,
+	.vsel_reg = AXP2101_REG_BLDO1_VOLTAGE,
+	.vsel_mask = 0x1FU,
+	.vsel_bitpos = 0U,
+	.max_ua = 300000U,
+	.ranges = axp2101_abldox_ranges,
+	.num_ranges = ARRAY_SIZE(axp2101_abldox_ranges),
+	.workmode_reg = 0U,
+	.workmode_mask = 0U,
+};
+
+__maybe_unused static const struct regulator_axp192_desc axp2101_bldo2_desc = {
+	.enable_reg = AXP2101_REG_LDOGRP1_CONTROL,
+	.enable_mask = 0x20U,
+	.enable_val = 0x20U,
+	.vsel_reg = AXP2101_REG_BLDO2_VOLTAGE,
+	.vsel_mask = 0x1FU,
+	.vsel_bitpos = 0U,
+	.max_ua = 300000U,
+	.ranges = axp2101_abldox_ranges,
+	.num_ranges = ARRAY_SIZE(axp2101_abldox_ranges),
+	.workmode_reg = 0U,
+	.workmode_mask = 0U,
+};
+
+static const struct linear_range axp2101_cpusldo_ranges[] = {
+	LINEAR_RANGE_INIT(500000U, 50000U, 0U, 19U),
+};
+
+__maybe_unused static const struct regulator_axp192_desc axp2101_cpusldo_desc = {
+	.enable_reg = AXP2101_REG_LDOGRP1_CONTROL,
+	.enable_mask = 0x40U,
+	.enable_val = 0x40U,
+	.vsel_reg = AXP2101_REG_CPUSLDO_VOLTAGE,
+	.vsel_mask = 0x1FU,
+	.vsel_bitpos = 0U,
+	.max_ua = 30000U,
+	.ranges = axp2101_cpusldo_ranges,
+	.num_ranges = ARRAY_SIZE(axp2101_cpusldo_ranges),
+	.workmode_reg = 0U,
+	.workmode_mask = 0U,
+};
+
+static const struct linear_range axp2101_dldo1_ranges[] = {
+	LINEAR_RANGE_INIT(500000U, 100000U, 0U, 28U),
+};
+
+__maybe_unused static const struct regulator_axp192_desc axp2101_dldo1_desc = {
+	.enable_reg = AXP2101_REG_LDOGRP1_CONTROL,
+	.enable_mask = 0x80U,
+	.enable_val = 0x80U,
+	.vsel_reg = AXP2101_REG_DLDO1_VOLTAGE,
+	.vsel_mask = 0x1FU,
+	.vsel_bitpos = 0U,
+	.max_ua = 300000U,
+	.ranges = axp2101_dldo1_ranges,
+	.num_ranges = ARRAY_SIZE(axp2101_dldo1_ranges),
+	.workmode_reg = 0U,
+	.workmode_mask = 0U,
+};
+
+static const struct linear_range axp2101_dldo2_ranges[] = {
+	LINEAR_RANGE_INIT(500000U, 50000U, 0U, 19U),
+};
+
+__maybe_unused static const struct regulator_axp192_desc axp2101_dldo2_desc = {
+	.enable_reg = AXP2101_REG_LDOGRP2_CONTROL,
+	.enable_mask = 0x01U,
+	.enable_val = 0x01U,
+	.vsel_reg = AXP2101_REG_DLDO2_VOLTAGE,
+	.vsel_mask = 0x1FU,
+	.vsel_bitpos = 0U,
+	.max_ua = 300000U,
+	.ranges = axp2101_dldo2_ranges,
+	.num_ranges = ARRAY_SIZE(axp2101_dldo2_ranges),
+	.workmode_reg = 0U,
+	.workmode_mask = 0U,
 };
 
 static int axp192_enable(const struct device *dev)
@@ -176,20 +436,24 @@ static int axp192_enable(const struct device *dev)
 	const struct regulator_axp192_config *config = dev->config;
 	int ret;
 
-	LOG_INST_DBG(config->log, "Enabling regulator");
-	LOG_INST_DBG(config->log, "[0x%02x]=0x%02x mask=0x%02x", config->desc->enable_reg,
+	LOG_DBG("Enabling regulator");
+	LOG_DBG("[0x%02x]=0x%02x mask=0x%02x", config->desc->enable_reg,
 		     config->desc->enable_val, config->desc->enable_mask);
 
+#if AXP192_ANY_HAS_CHILD(ldoio0)
 	/* special case for LDOIO0, which is multiplexed with GPIO0 */
 	if (config->desc->enable_reg == AXP192_REG_GPIO0_CONTROL) {
 		ret = mfd_axp192_gpio_func_ctrl(config->mfd, dev, 0, AXP192_GPIO_FUNC_LDO);
 	} else {
+#endif
 		ret = i2c_reg_update_byte_dt(&config->i2c, config->desc->enable_reg,
 					     config->desc->enable_mask, config->desc->enable_val);
+#if AXP192_ANY_HAS_CHILD(ldoio0)
 	}
+#endif
 
 	if (ret != 0) {
-		LOG_INST_ERR(config->log, "Failed to enable regulator");
+		LOG_ERR("Failed to enable regulator");
 	}
 
 	return ret;
@@ -200,19 +464,24 @@ static int axp192_disable(const struct device *dev)
 	const struct regulator_axp192_config *config = dev->config;
 	int ret;
 
-	LOG_INST_DBG(config->log, "Disabling regulator");
-	LOG_INST_DBG(config->log, "[0x%02x]=0 mask=0x%x", config->desc->enable_reg,
+	LOG_DBG("Disabling regulator");
+	LOG_DBG("[0x%02x]=0 mask=0x%x", config->desc->enable_reg,
 		     config->desc->enable_mask);
 
+#if AXP192_ANY_HAS_CHILD(ldoio0)
 	/* special case for LDOIO0, which is multiplexed with GPIO0 */
 	if (config->desc->enable_reg == AXP192_REG_GPIO0_CONTROL) {
 		ret = mfd_axp192_gpio_func_ctrl(config->mfd, dev, 0, AXP192_GPIO_FUNC_OUTPUT_LOW);
 	} else {
+#endif
 		ret = i2c_reg_update_byte_dt(&config->i2c, config->desc->enable_reg,
 					     config->desc->enable_mask, 0u);
+#if AXP192_ANY_HAS_CHILD(ldoio0)
 	}
+#endif
+
 	if (ret != 0) {
-		LOG_INST_ERR(config->log, "Failed to disable regulator");
+		LOG_ERR("Failed to disable regulator");
 	}
 
 	return ret;
@@ -239,24 +508,24 @@ static int axp192_set_voltage(const struct device *dev, int32_t min_uv, int32_t
 	uint16_t idx;
 	int ret;
 
-	LOG_INST_DBG(config->log, "voltage = [min=%d, max=%d]", min_uv, max_uv);
+	LOG_DBG("voltage = [min=%d, max=%d]", min_uv, max_uv);
 
 	/* set voltage */
 	ret = linear_range_group_get_win_index(config->desc->ranges, config->desc->num_ranges,
 					       min_uv, max_uv, &idx);
 	if (ret != 0) {
-		LOG_INST_ERR(config->log, "No voltage range window could be detected");
+		LOG_ERR("No voltage range window could be detected");
 		return ret;
 	}
 
 	idx <<= config->desc->vsel_bitpos;
 
-	LOG_INST_DBG(config->log, "[0x%x]=0x%x mask=0x%x", config->desc->vsel_reg, idx,
+	LOG_DBG("[0x%x]=0x%x mask=0x%x", config->desc->vsel_reg, idx,
 		     config->desc->vsel_mask);
 	ret = i2c_reg_update_byte_dt(&config->i2c, config->desc->vsel_reg, config->desc->vsel_mask,
 				     (uint8_t)idx);
 	if (ret != 0) {
-		LOG_INST_ERR(config->log, "Failed to set regulator voltage");
+		LOG_ERR("Failed to set regulator voltage");
 	}
 
 	return ret;
@@ -291,7 +560,7 @@ static int axp192_set_mode(const struct device *dev, regulator_mode_t mode)
 	if ((mode == AXP192_DCDC_MODE_PWM) && (config->desc->workmode_reg != 0)) {
 
 		/* configure PWM mode */
-		LOG_INST_DBG(config->log, "PWM mode enabled");
+		LOG_DBG("PWM mode enabled");
 		ret = i2c_reg_update_byte_dt(&config->i2c, config->desc->workmode_reg,
 					     config->desc->workmode_mask,
 					     config->desc->workmode_pwm_val);
@@ -313,7 +582,7 @@ static int axp192_set_mode(const struct device *dev, regulator_mode_t mode)
 			return 0;
 		}
 	} else {
-		LOG_INST_ERR(config->log, "Setting DCDC workmode failed");
+		LOG_ERR("Setting DCDC workmode failed");
 		return -ENOTSUP;
 	}
 
@@ -350,44 +619,63 @@ static int regulator_axp192_init(const struct device *dev)
 	regulator_common_data_init(dev);
 
 	if (!device_is_ready(config->mfd)) {
-		LOG_INST_ERR(config->log, "Parent instance not ready!");
+		LOG_ERR("Parent instance not ready!");
 		return -ENODEV;
 	}
 
 	/* read regulator state */
 	ret = i2c_reg_read_byte_dt(&config->i2c, config->desc->enable_reg, &enabled_val);
 	if (ret != 0) {
-		LOG_INST_ERR(config->log, "Reading enable status failed!");
+		LOG_ERR("Reading enable status failed!");
 		return ret;
 	}
 	is_enabled = ((enabled_val & config->desc->enable_mask) == config->desc->enable_val);
-	LOG_INST_DBG(config->log, "is_enabled: %d", is_enabled);
+	LOG_DBG("is_enabled: %d", is_enabled);
 
 	return regulator_common_init(dev, is_enabled);
 }
 
 #define REGULATOR_AXP192_DEFINE(node_id, id, name)                                                 \
 	static struct regulator_axp192_data data_##id;                                             \
-	LOG_INSTANCE_REGISTER(name, node_id, CONFIG_REGULATOR_LOG_LEVEL);                          \
 	static const struct regulator_axp192_config config_##id = {                                \
 		.common = REGULATOR_DT_COMMON_CONFIG_INIT(node_id),                                \
-		.desc = &name##_desc,                                                              \
+		.desc = &id##_desc,                                                                \
 		.mfd = DEVICE_DT_GET(DT_GPARENT(node_id)),                                         \
-		.i2c = I2C_DT_SPEC_GET(DT_GPARENT(node_id)),                                       \
-		LOG_INSTANCE_PTR_INIT(log, name, node_id)};                                        \
+		.i2c = I2C_DT_SPEC_GET(DT_GPARENT(node_id))};                                      \
 	DEVICE_DT_DEFINE(node_id, regulator_axp192_init, NULL, &data_##id, &config_##id,           \
-			 POST_KERNEL, CONFIG_REGULATOR_AXP192_INIT_PRIORITY, &api);
-
-#define REGULATOR_AXP192_DEFINE_COND(inst, child)                                                  \
-	COND_CODE_1(DT_NODE_EXISTS(DT_INST_CHILD(inst, child)),                                    \
-		    (REGULATOR_AXP192_DEFINE(DT_INST_CHILD(inst, child), child##inst, child)), ())
-
-#define REGULATOR_AXP192_DEFINE_ALL(inst)                                                          \
-	REGULATOR_AXP192_DEFINE_COND(inst, dcdc1)                                                  \
-	REGULATOR_AXP192_DEFINE_COND(inst, dcdc2)                                                  \
-	REGULATOR_AXP192_DEFINE_COND(inst, dcdc3)                                                  \
-	REGULATOR_AXP192_DEFINE_COND(inst, ldoio0)                                                 \
-	REGULATOR_AXP192_DEFINE_COND(inst, ldo2)                                                   \
-	REGULATOR_AXP192_DEFINE_COND(inst, ldo3)
-
-DT_INST_FOREACH_STATUS_OKAY(REGULATOR_AXP192_DEFINE_ALL)
+			 POST_KERNEL, CONFIG_REGULATOR_AXP192_AXP2101_INIT_PRIORITY, &api);
+
+#define REGULATOR_AXP192_DEFINE_COND(node, child)                                                  \
+	COND_CODE_1(DT_NODE_EXISTS(DT_CHILD(node, child)),                                         \
+		    (REGULATOR_AXP192_DEFINE(DT_CHILD(node, child), axp192_##child, child)), ())
+
+#define REGULATOR_AXP2101_DEFINE_COND(node, child)                                                 \
+	COND_CODE_1(DT_NODE_EXISTS(DT_CHILD(node, child)),                                         \
+		    (REGULATOR_AXP192_DEFINE(DT_CHILD(node, child), axp2101_##child, child)), ())
+
+#define REGULATOR_AXP192_DEFINE_ALL(node)                                                          \
+	REGULATOR_AXP192_DEFINE_COND(node, dcdc1)                                                  \
+	REGULATOR_AXP192_DEFINE_COND(node, dcdc2)                                                  \
+	REGULATOR_AXP192_DEFINE_COND(node, dcdc3)                                                  \
+	REGULATOR_AXP192_DEFINE_COND(node, ldoio0)                                                 \
+	REGULATOR_AXP192_DEFINE_COND(node, ldo2)                                                   \
+	REGULATOR_AXP192_DEFINE_COND(node, ldo3)
+
+#define REGULATOR_AXP2101_DEFINE_ALL(node)                                                         \
+	REGULATOR_AXP2101_DEFINE_COND(node, dcdc1)                                                 \
+	REGULATOR_AXP2101_DEFINE_COND(node, dcdc2)                                                 \
+	REGULATOR_AXP2101_DEFINE_COND(node, dcdc3)                                                 \
+	REGULATOR_AXP2101_DEFINE_COND(node, dcdc4)                                                 \
+	REGULATOR_AXP2101_DEFINE_COND(node, dcdc5)                                                 \
+	REGULATOR_AXP2101_DEFINE_COND(node, aldo1)                                                 \
+	REGULATOR_AXP2101_DEFINE_COND(node, aldo2)                                                 \
+	REGULATOR_AXP2101_DEFINE_COND(node, aldo3)                                                 \
+	REGULATOR_AXP2101_DEFINE_COND(node, aldo4)                                                 \
+	REGULATOR_AXP2101_DEFINE_COND(node, bldo1)                                                 \
+	REGULATOR_AXP2101_DEFINE_COND(node, bldo2)                                                 \
+	REGULATOR_AXP2101_DEFINE_COND(node, cpusldo)                                               \
+	REGULATOR_AXP2101_DEFINE_COND(node, dldo1)                                                 \
+	REGULATOR_AXP2101_DEFINE_COND(node, dldo2)
+
+DT_FOREACH_STATUS_OKAY(x_powers_axp192_regulator, REGULATOR_AXP192_DEFINE_ALL)
+DT_FOREACH_STATUS_OKAY(x_powers_axp2101_regulator, REGULATOR_AXP2101_DEFINE_ALL)
diff --git a/drivers/regulator/regulator_fake.c b/drivers/regulator/regulator_fake.c
index e48bd8cdb39..9e483ae7d3b 100644
--- a/drivers/regulator/regulator_fake.c
+++ b/drivers/regulator/regulator_fake.c
@@ -32,6 +32,9 @@ DEFINE_FAKE_VALUE_FUNC(int, regulator_fake_set_voltage, const struct device *,
 		       int32_t, int32_t);
 DEFINE_FAKE_VALUE_FUNC(int, regulator_fake_get_voltage, const struct device *,
 		       int32_t *);
+DEFINE_FAKE_VALUE_FUNC(unsigned int, regulator_fake_count_current_limits, const struct device *);
+DEFINE_FAKE_VALUE_FUNC(int, regulator_fake_list_current_limit, const struct device *, unsigned int,
+		       int32_t *);
 DEFINE_FAKE_VALUE_FUNC(int, regulator_fake_set_current_limit,
 		       const struct device *, int32_t, int32_t);
 DEFINE_FAKE_VALUE_FUNC(int, regulator_fake_get_current_limit,
@@ -54,6 +57,8 @@ static DEVICE_API(regulator, api) = {
 	.list_voltage = regulator_fake_list_voltage,
 	.set_voltage = regulator_fake_set_voltage,
 	.get_voltage = regulator_fake_get_voltage,
+	.count_current_limits = regulator_fake_count_current_limits,
+	.list_current_limit = regulator_fake_list_current_limit,
 	.set_current_limit = regulator_fake_set_current_limit,
 	.get_current_limit = regulator_fake_get_current_limit,
 	.set_mode = regulator_fake_set_mode,
diff --git a/drivers/regulator/regulator_pf1550.c b/drivers/regulator/regulator_pf1550.c
new file mode 100644
index 00000000000..7cbfd0cd771
--- /dev/null
+++ b/drivers/regulator/regulator_pf1550.c
@@ -0,0 +1,432 @@
+/*
+ * Copyright (c) 2024 Arduino SA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_pf1550_regulator
+
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/regulator.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/linear_range.h>
+
+#define PMIC_DEVICE_ID         0x00
+#define PMIC_OTP_FLAVOR        0x01
+#define PMIC_SILICON_REV       0x02
+#define PMIC_INT_CATEGORY      0x06
+#define PMIC_SW_INT_STAT0      0x08
+#define PMIC_SW_INT_MASK0      0x09
+#define PMIC_SW_INT_SENSE0     0x0A
+#define PMIC_SW_INT_STAT1      0x0B
+#define PMIC_SW_INT_MASK1      0x0C
+#define PMIC_SW_INT_SENSE1     0x0D
+#define PMIC_SW_INT_STAT2      0x0E
+#define PMIC_SW_INT_MASK2      0x0F
+#define PMIC_SW_INT_SENSE2     0x10
+#define PMIC_LDO_INT_STAT0     0x18
+#define PMIC_LDO_INT_MASK0     0x19
+#define PMIC_LDO_INT_SENSE0    0x1A
+#define PMIC_TEMP_INT_STAT0    0x20
+#define PMIC_TEMP_INT_MASK0    0x21
+#define PMIC_TEMP_INT_SENSE0   0x22
+#define PMIC_ONKEY_INT_STAT0   0x24
+#define PMIC_ONKEY_INT_MASK0   0x25
+#define PMIC_ONKEY_INT_SENSE0  0x26
+#define PMIC_MISC_INT_STAT0    0x28
+#define PMIC_MISC_INT_MASK0    0x29
+#define PMIC_MISC_INT_SENSE0   0x2A
+#define PMIC_COINCELL_CONTROL  0x30
+#define PMIC_SW1_VOLT          0x32
+#define PMIC_SW1_STBY_VOLT     0x33
+#define PMIC_SW1_SLP_VOLT      0x34
+#define PMIC_SW1_CTRL          0x35
+#define PMIC_SW1_CTRL1         0x36
+#define PMIC_SW2_VOLT          0x38
+#define PMIC_SW2_STBY_VOLT     0x39
+#define PMIC_SW2_SLP_VOLT      0x3A
+#define PMIC_SW2_CTRL          0x3B
+#define PMIC_SW2_CTRL1         0x3C
+#define PMIC_SW3_VOLT          0x3E
+#define PMIC_SW3_STBY_VOLT     0x3F
+#define PMIC_SW3_SLP_VOLT      0x40
+#define PMIC_SW3_CTRL          0x41
+#define PMIC_SW3_CTRL1         0x42
+#define PMIC_VSNVS_CTRL        0x48
+#define PMIC_VREFDDR_CTRL      0x4A
+#define PMIC_LDO1_VOLT         0x4C
+#define PMIC_LDO1_CTRL         0x4D
+#define PMIC_LDO2_VOLT         0x4F
+#define PMIC_LDO2_CTRL         0x50
+#define PMIC_LDO3_VOLT         0x52
+#define PMIC_LDO3_CTRL         0x53
+#define PMIC_PWRCTRL0          0x58
+#define PMIC_PWRCTRL1          0x59
+#define PMIC_PWRCTRL2          0x5A
+#define PMIC_PWRCTRL3          0x5B
+#define PMIC_SW1_PWRDN_SEQ     0x5F
+#define PMIC_SW2_PWRDN_SEQ     0x60
+#define PMIC_SW3_PWRDN_SEQ     0x61
+#define PMIC_LDO1_PWRDN_SEQ    0x62
+#define PMIC_LDO2_PWRDN_SEQ    0x63
+#define PMIC_LDO3_PWRDN_SEQ    0x64
+#define PMIC_VREFDDR_PWRDN_SEQ 0x65
+#define PMIC_STATE_INFO        0x67
+#define PMIC_I2C_ADDR          0x68
+#define PMIC_RC_16MHZ          0x6B
+#define PMIC_KEY1              0x6B
+
+enum pf1550_pmic_sources {
+	PF1550_PMIC_SOURCE_BUCK1,
+	PF1550_PMIC_SOURCE_BUCK2,
+	PF1550_PMIC_SOURCE_BUCK3,
+	PF1550_PMIC_SOURCE_LDO1,
+	PF1550_PMIC_SOURCE_LDO2,
+	PF1550_PMIC_SOURCE_LDO3,
+};
+
+struct regulator_pf1550_desc {
+	uint8_t vsel_reg;
+	uint8_t enable_mask;
+	uint8_t enable_val;
+	uint8_t cfg_reg;
+	const struct linear_range *uv_range;
+	uint8_t uv_nranges;
+	const struct linear_range *ua_range;
+	uint8_t ua_nranges;
+};
+
+struct regulator_pf1550_common_config {
+	struct i2c_dt_spec bus;
+};
+
+struct regulator_pf1550_config {
+	struct regulator_common_config common;
+	struct i2c_dt_spec bus;
+	const struct regulator_pf1550_desc *desc;
+	uint8_t source;
+};
+
+struct regulator_pf1550_data {
+	struct regulator_common_data common;
+};
+
+/*
+ * Output voltage for BUCK1/2 with DVS disabled (OTP_SWx_DVS_SEL =  1).
+ * This is needed to reach the 3V3 maximum range
+ */
+static const struct linear_range buck12_range[] = {
+	LINEAR_RANGE_INIT(1100000, 0, 0, 0), LINEAR_RANGE_INIT(1200000, 0, 1, 1),
+	LINEAR_RANGE_INIT(1350000, 0, 2, 2), LINEAR_RANGE_INIT(1500000, 0, 3, 3),
+	LINEAR_RANGE_INIT(1800000, 0, 4, 4), LINEAR_RANGE_INIT(2500000, 0, 5, 5),
+	LINEAR_RANGE_INIT(3000000, 0, 6, 6), LINEAR_RANGE_INIT(3300000, 0, 7, 7),
+};
+static const struct linear_range buck3_range[] = {
+	LINEAR_RANGE_INIT(1800000, 100000, 0, 15),
+};
+static const struct linear_range buck123_current_limit_range[] = {
+	LINEAR_RANGE_INIT(1000000, 0, 0, 0),
+	LINEAR_RANGE_INIT(1200000, 0, 0, 0),
+	LINEAR_RANGE_INIT(1500000, 0, 0, 0),
+	LINEAR_RANGE_INIT(2000000, 0, 0, 0),
+};
+static const struct linear_range ldo13_range[] = {
+	LINEAR_RANGE_INIT(750000, 50000, 0, 15),
+	LINEAR_RANGE_INIT(1800000, 100000, 16, 31),
+};
+static const struct linear_range ldo2_range[] = {
+	LINEAR_RANGE_INIT(1800000, 100000, 0, 15),
+};
+
+#define PF1550_RAIL_EN        BIT(0)
+#define PF1550_RAIL_EN_MASK   GENMASK(1, 0)
+#define PF1550_GOTO_SHIP      BIT(0)
+#define PF1550_GOTO_SHIP_MASK GENMASK(1, 0)
+
+static const struct regulator_pf1550_desc __maybe_unused buck1_desc = {
+	.vsel_reg = PMIC_SW1_VOLT,
+	.enable_mask = PF1550_RAIL_EN,
+	.enable_val = PF1550_RAIL_EN_MASK,
+	.cfg_reg = PMIC_SW1_CTRL,
+	.uv_range = buck12_range,
+	.uv_nranges = ARRAY_SIZE(buck12_range),
+	.ua_range = buck123_current_limit_range,
+	.ua_nranges = ARRAY_SIZE(buck123_current_limit_range),
+};
+
+static const struct regulator_pf1550_desc __maybe_unused buck2_desc = {
+	.vsel_reg = PMIC_SW2_VOLT,
+	.enable_mask = PF1550_RAIL_EN,
+	.enable_val = PF1550_RAIL_EN_MASK,
+	.cfg_reg = PMIC_SW2_CTRL,
+	.uv_range = buck12_range,
+	.uv_nranges = ARRAY_SIZE(buck12_range),
+	.ua_range = buck123_current_limit_range,
+	.ua_nranges = ARRAY_SIZE(buck123_current_limit_range),
+};
+
+static const struct regulator_pf1550_desc __maybe_unused buck3_desc = {
+	.vsel_reg = PMIC_SW3_VOLT,
+	.enable_mask = PF1550_RAIL_EN,
+	.enable_val = PF1550_RAIL_EN_MASK,
+	.cfg_reg = PMIC_SW3_CTRL,
+	.uv_range = buck3_range,
+	.uv_nranges = ARRAY_SIZE(buck3_range),
+	.ua_range = buck123_current_limit_range,
+	.ua_nranges = ARRAY_SIZE(buck123_current_limit_range),
+};
+
+static const struct regulator_pf1550_desc __maybe_unused ldo1_desc = {
+	.vsel_reg = PMIC_LDO1_VOLT,
+	.enable_mask = PF1550_RAIL_EN,
+	.enable_val = PF1550_RAIL_EN_MASK,
+	.cfg_reg = PMIC_LDO1_CTRL,
+	.uv_range = ldo13_range,
+	.uv_nranges = ARRAY_SIZE(ldo13_range),
+};
+
+static const struct regulator_pf1550_desc __maybe_unused ldo2_desc = {
+	.vsel_reg = PMIC_LDO2_VOLT,
+	.enable_mask = PF1550_RAIL_EN,
+	.enable_val = PF1550_RAIL_EN_MASK,
+	.cfg_reg = PMIC_LDO2_CTRL,
+	.uv_range = ldo2_range,
+	.uv_nranges = ARRAY_SIZE(ldo2_range),
+};
+
+static const struct regulator_pf1550_desc __maybe_unused ldo3_desc = {
+	.vsel_reg = PMIC_LDO3_VOLT,
+	.enable_mask = PF1550_RAIL_EN,
+	.enable_val = PF1550_RAIL_EN_MASK,
+	.cfg_reg = PMIC_LDO3_CTRL,
+	.uv_range = ldo13_range,
+	.uv_nranges = ARRAY_SIZE(ldo13_range),
+};
+
+static int regulator_pf1550_set_enable(const struct device *dev, bool enable)
+{
+	const struct regulator_pf1550_config *config = dev->config;
+
+	return i2c_reg_update_byte_dt(&config->bus, config->desc->cfg_reg,
+				      config->desc->enable_mask,
+				      enable ? config->desc->enable_val : 0);
+}
+
+static int regulator_pf1550_enable(const struct device *dev)
+{
+	return regulator_pf1550_set_enable(dev, true);
+}
+
+static int regulator_pf1550_disable(const struct device *dev)
+{
+	return regulator_pf1550_set_enable(dev, false);
+}
+
+static unsigned int regulator_pf1550_count_voltages(const struct device *dev)
+{
+	const struct regulator_pf1550_config *config = dev->config;
+
+	return linear_range_group_values_count(config->desc->uv_range, config->desc->uv_nranges);
+}
+
+static int regulator_pf1550_list_voltage(const struct device *dev, unsigned int idx,
+					 int32_t *volt_uv)
+{
+	const struct regulator_pf1550_config *config = dev->config;
+
+	return linear_range_group_get_value(config->desc->uv_range, config->desc->uv_nranges, idx,
+					    volt_uv);
+}
+
+static int regulator_pf1550_set_buck_ldo_voltage(const struct device *dev, int32_t min_uv,
+						 int32_t max_uv, const struct linear_range *range,
+						 const uint8_t nranges, uint8_t vout_reg)
+{
+	const struct regulator_pf1550_config *config = dev->config;
+	uint16_t idx;
+	int ret;
+
+	ret = linear_range_group_get_win_index(range, nranges, min_uv, max_uv, &idx);
+	if (ret < 0) {
+		return ret;
+	}
+
+	return i2c_reg_write_byte_dt(&config->bus, vout_reg, (uint8_t)idx);
+}
+
+static int regulator_pf1550_buck12_ldo123_get_voltage(const struct device *dev,
+						      const struct linear_range *range,
+						      const uint8_t nranges, uint8_t vout_reg,
+						      int32_t *volt_uv)
+{
+	const struct regulator_pf1550_config *config = dev->config;
+	uint8_t idx;
+	int ret;
+
+	ret = i2c_reg_read_byte_dt(&config->bus, vout_reg, &idx);
+	if (ret < 0) {
+		return ret;
+	}
+
+	return linear_range_group_get_value(range, nranges, idx, volt_uv);
+}
+
+static int regulator_pf1550_get_voltage(const struct device *dev, int32_t *volt_uv)
+{
+	const struct regulator_pf1550_config *config = dev->config;
+
+	return regulator_pf1550_buck12_ldo123_get_voltage(dev, config->desc->uv_range,
+							  config->desc->uv_nranges,
+							  config->desc->vsel_reg, volt_uv);
+}
+
+static int regulator_pf1550_set_voltage(const struct device *dev, int32_t min_uv, int32_t max_uv)
+{
+	const struct regulator_pf1550_config *config = dev->config;
+
+	return regulator_pf1550_set_buck_ldo_voltage(dev, min_uv, max_uv, config->desc->uv_range,
+						     config->desc->uv_nranges,
+						     config->desc->vsel_reg);
+}
+
+static unsigned int regulator_pf1550_count_current_limits(const struct device *dev)
+{
+	const struct regulator_pf1550_config *config = dev->config;
+
+	if (config->source != PF1550_PMIC_SOURCE_BUCK1 &&
+	    config->source != PF1550_PMIC_SOURCE_BUCK2 &&
+	    config->source != PF1550_PMIC_SOURCE_BUCK3) {
+		return -ENOTSUP;
+	}
+
+	return linear_range_group_values_count(config->desc->ua_range, config->desc->ua_nranges);
+}
+
+static int regulator_pf1550_list_current_limit(const struct device *dev, unsigned int idx,
+					       int32_t *current_ua)
+{
+	const struct regulator_pf1550_config *config = dev->config;
+
+	if (config->source != PF1550_PMIC_SOURCE_BUCK1 &&
+	    config->source != PF1550_PMIC_SOURCE_BUCK2 &&
+	    config->source != PF1550_PMIC_SOURCE_BUCK3) {
+		return -ENOTSUP;
+	}
+
+	return linear_range_group_get_value(config->desc->ua_range, config->desc->ua_nranges, idx,
+					    current_ua);
+}
+
+static int regulator_pf1550_set_current_limit(const struct device *dev, int32_t min_ua,
+					      int32_t max_ua)
+{
+	const struct regulator_pf1550_config *config = dev->config;
+	uint8_t val;
+	uint16_t idx;
+	int ret;
+
+	if (config->source != PF1550_PMIC_SOURCE_BUCK1 &&
+	    config->source != PF1550_PMIC_SOURCE_BUCK2 &&
+	    config->source != PF1550_PMIC_SOURCE_BUCK3) {
+		return -ENOTSUP;
+	}
+
+	/* Current is stored in SW*_CTRL1 register */
+	ret = i2c_reg_read_byte_dt(&config->bus, config->desc->cfg_reg + 1, &val);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = linear_range_group_get_win_index(config->desc->ua_range, config->desc->ua_nranges,
+					       min_ua, max_ua, &idx);
+	if (ret < 0) {
+		return ret;
+	}
+
+	val |= idx;
+	return i2c_reg_write_byte_dt(&config->bus, config->desc->cfg_reg + 1, val);
+}
+
+static int regulator_pf1550_power_off(const struct device *dev)
+{
+	const struct regulator_pf1550_common_config *common_config = dev->config;
+
+	return i2c_reg_update_byte_dt(&common_config->bus, PMIC_PWRCTRL3, PF1550_GOTO_SHIP_MASK,
+				      PF1550_GOTO_SHIP);
+}
+
+static int regulator_pf1550_init(const struct device *dev)
+{
+	const struct regulator_pf1550_config *config = dev->config;
+
+	if (!i2c_is_ready_dt(&config->bus)) {
+		return -ENODEV;
+	}
+
+	regulator_common_data_init(dev);
+
+	return regulator_common_init(dev, false);
+}
+
+static int regulator_pf1550_common_init(const struct device *dev)
+{
+	const struct regulator_pf1550_common_config *common_config = dev->config;
+
+	if (!i2c_is_ready_dt(&common_config->bus)) {
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(regulator_parent, parent_api) = {
+	.ship_mode = regulator_pf1550_power_off,
+};
+
+static DEVICE_API(regulator, api) = {
+	.enable = regulator_pf1550_enable,
+	.disable = regulator_pf1550_disable,
+	.count_voltages = regulator_pf1550_count_voltages,
+	.list_voltage = regulator_pf1550_list_voltage,
+	.set_voltage = regulator_pf1550_set_voltage,
+	.get_voltage = regulator_pf1550_get_voltage,
+	.count_current_limits = regulator_pf1550_count_current_limits,
+	.list_current_limit = regulator_pf1550_list_current_limit,
+	.set_current_limit = regulator_pf1550_set_current_limit,
+};
+
+#define REGULATOR_PF1550_DEFINE(node_id, id, child_name, _source)                                  \
+	static const struct regulator_pf1550_config regulator_pf1550_config_##id = {               \
+		.common = REGULATOR_DT_COMMON_CONFIG_INIT(node_id),                                \
+		.bus = I2C_DT_SPEC_GET(DT_GPARENT(node_id)),                                       \
+		.desc = &child_name##_desc,                                                        \
+		.source = _source,                                                                 \
+	};                                                                                         \
+												   \
+	static struct regulator_pf1550_data regulator_pf1550_data_##id;                            \
+	DEVICE_DT_DEFINE(node_id, regulator_pf1550_init, NULL, &regulator_pf1550_data_##id,        \
+			 &regulator_pf1550_config_##id, POST_KERNEL,                               \
+			 CONFIG_MFD_INIT_PRIORITY, &api);
+
+#define REGULATOR_PF1550_DEFINE_COND(inst, child, source)                                          \
+	COND_CODE_1(                                                                               \
+		DT_NODE_EXISTS(DT_INST_CHILD(inst, child)),                                        \
+		(REGULATOR_PF1550_DEFINE(DT_INST_CHILD(inst, child), child##inst, child, source)), \
+		())
+
+#define REGULATOR_PF1550_DEFINE_ALL(inst)                                                          \
+	static const struct regulator_pf1550_common_config common_config_##inst = {                \
+		.bus = I2C_DT_SPEC_GET(DT_INST_PARENT(inst)),                                      \
+	};                                                                                         \
+												   \
+	DEVICE_DT_INST_DEFINE(inst, regulator_pf1550_common_init, NULL, NULL,                      \
+			      &common_config_##inst, POST_KERNEL,                                  \
+			      CONFIG_MFD_INIT_PRIORITY, &parent_api);                              \
+												   \
+	REGULATOR_PF1550_DEFINE_COND(inst, buck1, PF1550_PMIC_SOURCE_BUCK1)                        \
+	REGULATOR_PF1550_DEFINE_COND(inst, buck2, PF1550_PMIC_SOURCE_BUCK2)                        \
+	REGULATOR_PF1550_DEFINE_COND(inst, buck3, PF1550_PMIC_SOURCE_BUCK3)                        \
+	REGULATOR_PF1550_DEFINE_COND(inst, ldo1, PF1550_PMIC_SOURCE_LDO1)                          \
+	REGULATOR_PF1550_DEFINE_COND(inst, ldo2, PF1550_PMIC_SOURCE_LDO2)                          \
+	REGULATOR_PF1550_DEFINE_COND(inst, ldo3, PF1550_PMIC_SOURCE_LDO3)
+
+DT_INST_FOREACH_STATUS_OKAY(REGULATOR_PF1550_DEFINE_ALL)
diff --git a/drivers/regulator/regulator_shell.c b/drivers/regulator/regulator_shell.c
index 7524e71c946..259b4f8e89c 100644
--- a/drivers/regulator/regulator_shell.c
+++ b/drivers/regulator/regulator_shell.c
@@ -522,9 +522,14 @@ static int cmd_shipmode(const struct shell *sh, size_t argc, char **argv)
 	return 0;
 }
 
+static bool device_is_regulator(const struct device *dev)
+{
+	return DEVICE_API_IS(regulator, dev);
+}
+
 static void device_name_get(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_lookup(idx, NULL);
+	const struct device *dev = shell_device_filter(idx, device_is_regulator);
 
 	entry->syntax = (dev != NULL) ? dev->name : NULL;
 	entry->handler = NULL;
diff --git a/drivers/reset/CMakeLists.txt b/drivers/reset/CMakeLists.txt
index 84f0443cabb..e94d51e2d2a 100644
--- a/drivers/reset/CMakeLists.txt
+++ b/drivers/reset/CMakeLists.txt
@@ -12,3 +12,4 @@ zephyr_library_sources_ifdef(CONFIG_RESET_INTEL_SOCFPGA reset_intel_socfpga.c)
 zephyr_library_sources_ifdef(CONFIG_RESET_NPCX reset_npcx.c)
 zephyr_library_sources_ifdef(CONFIG_RESET_NXP_SYSCON reset_lpc_syscon.c)
 zephyr_library_sources_ifdef(CONFIG_RESET_NXP_RSTCTL reset_nxp_rstctl.c)
+zephyr_library_sources_ifdef(CONFIG_RESET_MMIO reset_mmio.c)
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 87ba9c7576c..10e34c47f0b 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -36,5 +36,6 @@ rsource "Kconfig.intel_socfpga"
 rsource "Kconfig.npcx"
 rsource "Kconfig.lpc_syscon"
 rsource "Kconfig.nxp_rstctl"
+rsource "Kconfig.mmio"
 
 endif # RESET
diff --git a/drivers/reset/Kconfig.mmio b/drivers/reset/Kconfig.mmio
new file mode 100644
index 00000000000..dc1c88a233d
--- /dev/null
+++ b/drivers/reset/Kconfig.mmio
@@ -0,0 +1,11 @@
+# MMIO reset driver configuration options
+
+# Copyright (c) 2025 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+config RESET_MMIO
+	bool "Generic MMIO reset driver"
+	default y
+	depends on DT_HAS_RESET_MMIO_ENABLED
+	help
+	  This option enables the generic MMIO reset driver. This is meant for IPs with a single memory mapped reset bit required to take them out of reset.
diff --git a/drivers/reset/reset_mmio.c b/drivers/reset/reset_mmio.c
new file mode 100644
index 00000000000..033e8e00c66
--- /dev/null
+++ b/drivers/reset/reset_mmio.c
@@ -0,0 +1,111 @@
+/* Copyright (c) 2025 Google LLC.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/reset.h>
+#include <zephyr/kernel.h>
+
+struct reset_mmio_dev_config {
+	uint32_t base;
+	uint8_t num_resets;
+	bool active_low;
+};
+
+struct reset_mmio_dev_data {
+	struct k_spinlock lock;
+};
+
+static inline int reset_mmio_status(const struct device *dev, uint32_t id, uint8_t *status)
+{
+	const struct reset_mmio_dev_config *config = dev->config;
+	uint32_t value;
+
+	if (id >= config->num_resets) {
+		return -EINVAL;
+	}
+
+	value = sys_read32(config->base);
+	*status = FIELD_GET(BIT(id), value);
+
+	/* If active low, invert the logic */
+	if (config->active_low) {
+		*status = !(*status);
+	}
+
+	return 0;
+}
+
+static inline int reset_mmio_update(const struct device *dev, uint32_t id, uint8_t assert)
+{
+	const struct reset_mmio_dev_config *config = dev->config;
+	struct reset_mmio_dev_data *data = dev->data;
+	uint32_t value;
+	bool set;
+
+	if (id >= config->num_resets) {
+		return -EINVAL;
+	}
+
+	/* If active low, invert the logic */
+	set = config->active_low ? !assert : assert;
+
+	K_SPINLOCK(&data->lock) {
+		value = sys_read32(config->base);
+
+		if (set) {
+			value |= BIT(id);
+		} else {
+			value &= ~BIT(id);
+		}
+
+		sys_write32(value, config->base);
+	}
+
+	return 0;
+}
+
+static int reset_mmio_line_assert(const struct device *dev, uint32_t id)
+{
+	return reset_mmio_update(dev, id, 1);
+}
+
+static int reset_mmio_line_deassert(const struct device *dev, uint32_t id)
+{
+	return reset_mmio_update(dev, id, 0);
+}
+
+static int reset_mmio_line_toggle(const struct device *dev, uint32_t id)
+{
+	uint8_t reset_status = 0;
+	int status;
+
+	status = reset_mmio_status(dev, id, &reset_status);
+	if (status) {
+		return status;
+	}
+
+	return reset_mmio_update(dev, id, !reset_status);
+}
+
+static DEVICE_API(reset, reset_mmio_driver_api) = {
+	.status = reset_mmio_status,
+	.line_assert = reset_mmio_line_assert,
+	.line_deassert = reset_mmio_line_deassert,
+	.line_toggle = reset_mmio_line_toggle,
+};
+
+#define DT_DRV_COMPAT reset_mmio
+#define RESET_MMIO_INIT(n)                                                                         \
+	BUILD_ASSERT(DT_INST_PROP(n, num_resets) > 0 && DT_INST_PROP(n, num_resets) < 32,          \
+		     "num-resets needs to be in [1, 31].");                                        \
+	static const struct reset_mmio_dev_config reset_mmio_dev_config_##n = {                    \
+		.base = DT_INST_REG_ADDR(n),                                                       \
+		.num_resets = DT_INST_PROP(n, num_resets),                                         \
+		.active_low = DT_INST_PROP(n, active_low)};                                        \
+	static struct reset_mmio_dev_data reset_mmio_dev_data_##n;                                 \
+	DEVICE_DT_INST_DEFINE(n, NULL, NULL, &reset_mmio_dev_data_##n, &reset_mmio_dev_config_##n, \
+			      POST_KERNEL, CONFIG_RESET_INIT_PRIORITY, &reset_mmio_driver_api);
+DT_INST_FOREACH_STATUS_OKAY(RESET_MMIO_INIT)
diff --git a/drivers/reset/reset_numaker.c b/drivers/reset/reset_numaker.c
index 2054d661fff..52144fd2741 100644
--- a/drivers/reset/reset_numaker.c
+++ b/drivers/reset/reset_numaker.c
@@ -11,11 +11,16 @@
 #include <zephyr/devicetree.h>
 #include <zephyr/drivers/reset.h>
 
+#if defined(CONFIG_SOC_SERIES_M55M1X)
+#define NUMAKER_RESET_IP_OFFSET(id) (((id) >> 20UL) & 0xfffUL)
+#define NUMAKER_RESET_IP_BIT(id)    (id & 0x000fffffUL)
+#else
 /* Reset controller module IPRST offset */
 #define NUMAKER_RESET_IPRST0_OFFSET (8UL)
 #define NUMAKER_RESET_IP_OFFSET(id) (NUMAKER_RESET_IPRST0_OFFSET + (((id) >> 24UL) & 0xffUL))
 /* Reset controller module configuration bit */
 #define NUMAKER_RESET_IP_BIT(id)    (id & 0x00ffffffUL)
+#endif
 
 struct reset_numaker_config {
 	uint32_t base;
@@ -59,7 +64,7 @@ static int reset_numaker_line_toggle(const struct device *dev, uint32_t id)
 	return 0;
 }
 
-static DEVICE_API(reset, reset_numaker_driver_api) = {
+static const struct reset_driver_api reset_numaker_driver_api = {
 	.status = reset_numaker_status,
 	.line_assert = reset_numaker_line_assert,
 	.line_deassert = reset_numaker_line_deassert,
diff --git a/drivers/retained_mem/retained_mem_nrf_ram_ctrl.c b/drivers/retained_mem/retained_mem_nrf_ram_ctrl.c
index 08e777aa6fa..380c288fd1e 100644
--- a/drivers/retained_mem/retained_mem_nrf_ram_ctrl.c
+++ b/drivers/retained_mem/retained_mem_nrf_ram_ctrl.c
@@ -12,7 +12,7 @@
 
 #define _BUILD_MEM_REGION(node_id)		    \
 	{.dt_addr = DT_REG_ADDR(DT_PARENT(node_id)),\
-	 .dt_size = DT_REG_SIZE(DT_PARENT(node_id))}
+	 .dt_size = DT_REG_SIZE(DT_PARENT(node_id))},
 
 struct ret_mem_region {
 	uintptr_t dt_addr;
diff --git a/drivers/rtc/CMakeLists.txt b/drivers/rtc/CMakeLists.txt
index a18ff22568b..703ada100a7 100644
--- a/drivers/rtc/CMakeLists.txt
+++ b/drivers/rtc/CMakeLists.txt
@@ -15,6 +15,7 @@ zephyr_library_sources_ifdef(CONFIG_RTC_DS3231 rtc_ds3231.c)
 zephyr_library_sources_ifdef(CONFIG_USERSPACE rtc_handlers.c)
 zephyr_library_sources_ifdef(CONFIG_RTC_EMUL rtc_emul.c)
 zephyr_library_sources_ifdef(CONFIG_RTC_INFINEON_CAT1 rtc_ifx_cat1.c)
+zephyr_library_sources_ifdef(CONFIG_RTC_PCF2123 rtc_pcf2123.c)
 zephyr_library_sources_ifdef(CONFIG_RTC_PCF8523 rtc_pcf8523.c)
 zephyr_library_sources_ifdef(CONFIG_RTC_PCF8563 rtc_pcf8563.c)
 zephyr_library_sources_ifdef(CONFIG_RTC_MOTOROLA_MC146818 rtc_mc146818.c)
@@ -23,8 +24,14 @@ zephyr_library_sources_ifdef(CONFIG_RTC_SHELL rtc_shell.c)
 zephyr_library_sources_ifdef(CONFIG_RTC_FAKE rtc_fake.c)
 zephyr_library_sources_ifdef(CONFIG_RTC_SMARTBOND rtc_smartbond.c)
 zephyr_library_sources_ifdef(CONFIG_RTC_ATMEL_SAM rtc_sam.c)
+zephyr_library_sources_ifdef(CONFIG_RTC_ATMEL_SAM0 rtc_sam0.c)
 zephyr_library_sources_ifdef(CONFIG_RTC_RPI_PICO rtc_rpi_pico.c)
+zephyr_library_sources_ifdef(CONFIG_RTC_RTS5912 rtc_rts5912.c)
 zephyr_library_sources_ifdef(CONFIG_RTC_RV3028 rtc_rv3028.c)
 zephyr_library_sources_ifdef(CONFIG_RTC_NUMAKER rtc_numaker.c)
 zephyr_library_sources_ifdef(CONFIG_RTC_XMC4XXX rtc_xmc4xxx.c)
 zephyr_library_sources_ifdef(CONFIG_RTC_NXP_IRTC rtc_nxp_irtc.c)
+zephyr_library_sources_ifdef(CONFIG_RTC_RV8803 rtc_rv8803.c)
+zephyr_library_sources_ifdef(CONFIG_RTC_BQ32002 rtc_bq32002.c)
+zephyr_library_sources_ifdef(CONFIG_RTC_RX8130CE rtc_rx8130ce.c)
+zephyr_library_sources_ifdef(CONFIG_RTC_DS1337 rtc_ds1337.c)
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index e883414bfca..d84003ec3a1 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -49,16 +49,23 @@ source "drivers/rtc/Kconfig.emul"
 source "drivers/rtc/Kconfig.fake"
 source "drivers/rtc/Kconfig.ifx_cat1"
 source "drivers/rtc/Kconfig.mc146818"
+source "drivers/rtc/Kconfig.pcf2123"
 source "drivers/rtc/Kconfig.pcf8523"
 source "drivers/rtc/Kconfig.pcf8563"
 source "drivers/rtc/Kconfig.rpi_pico"
+source "drivers/rtc/Kconfig.rts5912"
 source "drivers/rtc/Kconfig.rv3028"
 source "drivers/rtc/Kconfig.sam"
+source "drivers/rtc/Kconfig.sam0"
 source "drivers/rtc/Kconfig.smartbond"
 source "drivers/rtc/Kconfig.stm32"
 source "drivers/rtc/Kconfig.numaker"
 source "drivers/rtc/Kconfig.rv8263"
 source "drivers/rtc/Kconfig.xmc4xxx"
 source "drivers/rtc/Kconfig.nxp_irtc"
+source "drivers/rtc/Kconfig.rv8803"
+source "drivers/rtc/Kconfig.bq32002"
+source "drivers/rtc/Kconfig.rx8130ce"
+source "drivers/rtc/Kconfig.ds1337"
 
 endif # RTC
diff --git a/drivers/rtc/Kconfig.bq32002 b/drivers/rtc/Kconfig.bq32002
new file mode 100644
index 00000000000..1f413d4f58e
--- /dev/null
+++ b/drivers/rtc/Kconfig.bq32002
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Marcin Lyda <elektromarcin@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config RTC_BQ32002
+	bool "Texas Instruments BQ32002 Real-Time Clock driver"
+	default y
+	depends on DT_HAS_TI_BQ32002_ENABLED
+	select I2C
+	help
+	    Enable Texas Instruments BQ32002 I2C RTC driver.
diff --git a/drivers/rtc/Kconfig.ds1337 b/drivers/rtc/Kconfig.ds1337
new file mode 100644
index 00000000000..9d2079f4655
--- /dev/null
+++ b/drivers/rtc/Kconfig.ds1337
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Marcin Lyda <elektromarcin@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config RTC_DS1337
+	bool "Maxim DS1337 RTC driver"
+	default y
+	depends on DT_HAS_MAXIM_DS1337_ENABLED
+	select I2C
+	help
+	    Enable Maxim DS1337 RTC driver.
diff --git a/drivers/rtc/Kconfig.pcf2123 b/drivers/rtc/Kconfig.pcf2123
new file mode 100644
index 00000000000..85c781ae2d3
--- /dev/null
+++ b/drivers/rtc/Kconfig.pcf2123
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Lukas Gunnarsson <lukasgunnarsson@protonmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config RTC_PCF2123
+	bool "NXP PCF2123 Real-Time Clock driver"
+	default y
+	depends on DT_HAS_NXP_PCF2123_ENABLED
+	select SPI
+	help
+	  Enable NXP PCF2123 SPI RTC driver.
diff --git a/drivers/rtc/Kconfig.rts5912 b/drivers/rtc/Kconfig.rts5912
new file mode 100644
index 00000000000..d064bf39fb0
--- /dev/null
+++ b/drivers/rtc/Kconfig.rts5912
@@ -0,0 +1,10 @@
+# Copyright (c) 2025, Realtek, SIBG-SD7
+# SPDX-License-Identifier: Apache-2.0
+
+config RTC_RTS5912
+	bool "Realtek RTS5912 rtc driver"
+	default y
+	depends on CLOCK_CONTROL
+	depends on DT_HAS_REALTEK_RTS5912_RTC_ENABLED
+	help
+	  Enable support for Realtek RTC driver.
diff --git a/drivers/rtc/Kconfig.rv8803 b/drivers/rtc/Kconfig.rv8803
new file mode 100644
index 00000000000..3e3982f7789
--- /dev/null
+++ b/drivers/rtc/Kconfig.rv8803
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Marcin Lyda <elektromarcin@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config RTC_RV8803
+	bool "Micro Crystal RV8803 Extreme Low Power Real-Time Clock Module driver"
+	default y
+	depends on DT_HAS_MICROCRYSTAL_RV8803_ENABLED
+	select I2C
+	help
+	    Enable Micro Crystal RV8803 I2C RTC driver.
diff --git a/drivers/rtc/Kconfig.rx8130ce b/drivers/rtc/Kconfig.rx8130ce
new file mode 100644
index 00000000000..ccd909b428a
--- /dev/null
+++ b/drivers/rtc/Kconfig.rx8130ce
@@ -0,0 +1,11 @@
+#Copyright (c) 2025 Måns Ansgariusson <mansgariusson@gmail.com>
+#
+#SPDX-License-Identifier: Apache-2.0
+
+config RTC_RX8130CE
+	bool "EPSON rx8130ce rtc driver"
+	default y
+	depends on DT_HAS_EPSON_RX8130CE_RTC_ENABLED
+	select I2C
+	help
+	  Enable RTC driver for the Epson rx8130ce rtc
diff --git a/drivers/rtc/Kconfig.sam0 b/drivers/rtc/Kconfig.sam0
new file mode 100644
index 00000000000..5dccc7b357c
--- /dev/null
+++ b/drivers/rtc/Kconfig.sam0
@@ -0,0 +1,10 @@
+# Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config RTC_ATMEL_SAM0
+	bool "Atmel SAM RTC driver"
+	default y
+	depends on DT_HAS_ATMEL_SAM0_RTC_ENABLED \
+		&& !$(dt_nodelabel_bool_prop,rtc,systimer)
+	help
+	  Atmel Real-Time Clock (RTC) driver used on SAM0 SoC series.
diff --git a/drivers/rtc/Kconfig.stm32 b/drivers/rtc/Kconfig.stm32
index 1cdbe99ca0b..777343c5286 100644
--- a/drivers/rtc/Kconfig.stm32
+++ b/drivers/rtc/Kconfig.stm32
@@ -6,7 +6,5 @@ config RTC_STM32
 	default y if !COUNTER
 	depends on DT_HAS_ST_STM32_RTC_ENABLED && !SOC_SERIES_STM32F1X
 	select USE_STM32_LL_RTC
-	select USE_STM32_LL_PWR
-	select USE_STM32_LL_RCC
 	help
 	  Build RTC driver for STM32 SoCs, excluding STM32F1 series.
diff --git a/drivers/rtc/rtc_ambiq.c b/drivers/rtc/rtc_ambiq.c
index 39459e3b38a..83ce35f0ea3 100644
--- a/drivers/rtc/rtc_ambiq.c
+++ b/drivers/rtc/rtc_ambiq.c
@@ -15,7 +15,7 @@
 
 LOG_MODULE_REGISTER(ambiq_rtc, CONFIG_RTC_LOG_LEVEL);
 
-#include <am_mcu_apollo.h>
+#include <soc.h>
 
 #define AMBIQ_RTC_ALARM_TIME_MASK                                                              \
 	(RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR |      \
diff --git a/drivers/rtc/rtc_bq32002.c b/drivers/rtc/rtc_bq32002.c
new file mode 100644
index 00000000000..38eb7783573
--- /dev/null
+++ b/drivers/rtc/rtc_bq32002.c
@@ -0,0 +1,372 @@
+/*
+ * Copyright (c) 2025 Marcin Lyda <elektromarcin@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/rtc.h>
+#include "rtc_utils.h"
+
+LOG_MODULE_REGISTER(bq32002, CONFIG_RTC_LOG_LEVEL);
+
+#define DT_DRV_COMPAT ti_bq32002
+
+#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 0
+#warning "Texas Instruments BQ32002 RTC driver enabled without any devices"
+#endif
+
+/* Registers */
+#define BQ32002_SECONDS_REG    0x00
+#define BQ32002_MINUTES_REG    0x01
+#define BQ32002_CENT_HOURS_REG 0x02
+#define BQ32002_DAY_REG        0x03
+#define BQ32002_DATE_REG       0x04
+#define BQ32002_MONTH_REG      0x05
+#define BQ32002_YEARS_REG      0x06
+#define BQ32002_CAL_CFG1_REG   0x07
+#define BQ32002_CFG2_REG       0x09
+#define BQ32002_SF_KEY_1_REG   0x20
+#define BQ32002_SF_KEY_2_REG   0x21
+#define BQ32002_SFR_REG        0x22
+
+/* Bitmasks */
+#define BQ32002_SECONDS_MASK GENMASK(6, 0)
+#define BQ32002_MINUTES_MASK GENMASK(6, 0)
+#define BQ32002_HOURS_MASK   GENMASK(5, 0)
+#define BQ32002_DAY_MASK     GENMASK(2, 0)
+#define BQ32002_DATE_MASK    GENMASK(5, 0)
+#define BQ32002_MONTH_MASK   GENMASK(4, 0)
+#define BQ32002_YEAR_MASK    GENMASK(7, 0)
+#define BQ32002_CAL_MASK     GENMASK(4, 0)
+
+#define BQ32002_OSC_STOP_MASK  BIT(7)
+#define BQ32002_OSC_FAIL_MASK  BIT(7)
+#define BQ32002_CENT_EN_MASK   BIT(7)
+#define BQ32002_CENT_MASK      BIT(6)
+#define BQ32002_OUT_MASK       BIT(7)
+#define BQ32002_FREQ_TEST_MASK BIT(6)
+#define BQ32002_CAL_SIGN_MASK  BIT(5)
+#define BQ32002_FTF_MASK       BIT(0)
+
+/* Keys to unlock special function register */
+#define BQ32002_SF_KEY_1 0x5E
+#define BQ32002_SF_KEY_2 0xC7
+
+/* BQ32002 counts weekdays from 1 to 7 */
+#define BQ32002_DAY_OFFSET -1
+
+/* BQ32002 counts months from 1 to 12 */
+#define BQ32002_MONTH_OFFSET -1
+
+/* Year 2000 value represented as tm_year value */
+#define BQ32002_TM_YEAR_2000 (2000 - 1900)
+
+/* Calibration constants, see BQ32002 datasheet, Table 12, p.16 */
+#define BQ32002_CAL_PPB_PER_LSB_POS 2034 /* 1e9 / 491520 */
+#define BQ32002_CAL_PPB_PER_LSB_NEG 4069 /* 1e9 / 245760 */
+#define BQ32002_CAL_PPB_MIN         (-31 * BQ32002_CAL_PPB_PER_LSB_POS)
+#define BQ32002_CAL_PPB_MAX         (31 * BQ32002_CAL_PPB_PER_LSB_NEG)
+
+/* IRQ frequency property enum values */
+#define BQ32002_IRQ_FREQ_ENUM_1HZ      0
+#define BQ32002_IRQ_FREQ_ENUM_512HZ    1
+#define BQ32002_IRQ_FREQ_ENUM_DISABLED 2
+
+/* RTC time fields supported by BQ32002 */
+#define BQ32002_RTC_TIME_MASK                                                                      \
+	(RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR |      \
+	 RTC_ALARM_TIME_MASK_MONTH | RTC_ALARM_TIME_MASK_MONTHDAY | RTC_ALARM_TIME_MASK_YEAR |     \
+	 RTC_ALARM_TIME_MASK_WEEKDAY)
+
+struct bq32002_config {
+	struct i2c_dt_spec i2c;
+	uint8_t irq_freq;
+};
+
+struct bq32002_data {
+	struct k_sem lock;
+};
+
+static void bq32002_lock_sem(const struct device *dev)
+{
+	struct bq32002_data *data = dev->data;
+
+	(void)k_sem_take(&data->lock, K_FOREVER);
+}
+
+static void bq32002_unlock_sem(const struct device *dev)
+{
+	struct bq32002_data *data = dev->data;
+
+	k_sem_give(&data->lock);
+}
+
+static int bq32002_set_irq_frequency(const struct device *dev)
+{
+	const struct bq32002_config *config = dev->config;
+	uint8_t sf_regs[3];
+	uint8_t cfg1_val;
+	uint8_t cfg2_val;
+	int err;
+
+	switch (config->irq_freq) {
+	case BQ32002_IRQ_FREQ_ENUM_1HZ:
+		cfg1_val = BQ32002_FREQ_TEST_MASK;
+		cfg2_val = BQ32002_FTF_MASK;
+		break;
+	case BQ32002_IRQ_FREQ_ENUM_512HZ:
+		cfg1_val = BQ32002_FREQ_TEST_MASK;
+		cfg2_val = 0;
+		break;
+	default:
+		cfg1_val = BQ32002_OUT_MASK;
+		cfg2_val = 0;
+		break;
+	}
+
+	err = i2c_reg_update_byte_dt(&config->i2c, BQ32002_CAL_CFG1_REG, BQ32002_FREQ_TEST_MASK,
+				     cfg1_val);
+	if (err) {
+		return err;
+	}
+
+	/* Update FTF value if frequency output enabled */
+	if (cfg1_val & BQ32002_FREQ_TEST_MASK) {
+		sf_regs[0] = BQ32002_SF_KEY_1;
+		sf_regs[1] = BQ32002_SF_KEY_2;
+		sf_regs[2] = cfg2_val;
+		err = i2c_burst_write_dt(&config->i2c, BQ32002_SF_KEY_1_REG, sf_regs,
+					 sizeof(sf_regs));
+		if (err) {
+			return err;
+		}
+	}
+
+	return 0;
+}
+
+static int bq32002_set_time(const struct device *dev, const struct rtc_time *timeptr)
+{
+	const struct bq32002_config *config = dev->config;
+	int err;
+	uint8_t regs[7];
+
+	if ((timeptr == NULL) || !rtc_utils_validate_rtc_time(timeptr, BQ32002_RTC_TIME_MASK)) {
+		return -EINVAL;
+	}
+
+	bq32002_lock_sem(dev);
+
+	/* Update the registers */
+	regs[0] = bin2bcd(timeptr->tm_sec) & BQ32002_SECONDS_MASK;
+	regs[1] = bin2bcd(timeptr->tm_min) & BQ32002_MINUTES_MASK; /* Clear oscillator fail flag */
+	regs[2] = (bin2bcd(timeptr->tm_hour) & BQ32002_HOURS_MASK) | BQ32002_CENT_EN_MASK;
+	regs[3] = bin2bcd(timeptr->tm_wday - BQ32002_DAY_OFFSET) & BQ32002_DAY_MASK;
+	regs[4] = bin2bcd(timeptr->tm_mday) & BQ32002_DATE_MASK;
+	regs[5] = bin2bcd(timeptr->tm_mon - BQ32002_MONTH_OFFSET) & BQ32002_MONTH_MASK;
+
+	/* Determine which century we're in */
+	if (timeptr->tm_year >= BQ32002_TM_YEAR_2000) {
+		regs[2] |= BQ32002_CENT_MASK;
+		regs[6] = bin2bcd(timeptr->tm_year - BQ32002_TM_YEAR_2000) & BQ32002_YEAR_MASK;
+	} else {
+		regs[6] = bin2bcd(timeptr->tm_year) & BQ32002_YEAR_MASK;
+	}
+
+	/* Write new time to the chip */
+	err = i2c_burst_write_dt(&config->i2c, BQ32002_SECONDS_REG, regs, sizeof(regs));
+
+	bq32002_unlock_sem(dev);
+
+	if (!err) {
+		LOG_DBG("Set time: year: %d, month: %d, month day: %d, week day: %d, hour: %d, "
+			"minute: %d, second: %d",
+			timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday,
+			timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
+	}
+
+	return err;
+}
+
+static int bq32002_get_time(const struct device *dev, struct rtc_time *timeptr)
+{
+	const struct bq32002_config *config = dev->config;
+	int err;
+	uint8_t reg_val;
+	uint8_t regs[7];
+
+	if (timeptr == NULL) {
+		return -EINVAL;
+	}
+
+	bq32002_lock_sem(dev);
+
+	err = i2c_reg_read_byte_dt(&config->i2c, BQ32002_MINUTES_REG, &reg_val);
+	if (err) {
+		goto out_unlock;
+	}
+
+	/* Oscillator failure detected, data might be invalid */
+	if (reg_val & BQ32002_OSC_FAIL_MASK) {
+		err = -ENODATA;
+		goto out_unlock;
+	}
+
+	err = i2c_burst_read_dt(&config->i2c, BQ32002_SECONDS_REG, regs, sizeof(regs));
+	if (err) {
+		goto out_unlock;
+	}
+
+	timeptr->tm_sec = bcd2bin(regs[0] & BQ32002_SECONDS_MASK);
+	timeptr->tm_min = bcd2bin(regs[1] & BQ32002_MINUTES_MASK);
+	timeptr->tm_hour = bcd2bin(regs[2] & BQ32002_HOURS_MASK);
+	timeptr->tm_wday = bcd2bin(regs[3] & BQ32002_DAY_MASK) + BQ32002_DAY_OFFSET;
+	timeptr->tm_mday = bcd2bin(regs[4] & BQ32002_DATE_MASK);
+	timeptr->tm_mon = bcd2bin(regs[5] & BQ32002_MONTH_MASK) + BQ32002_MONTH_OFFSET;
+	timeptr->tm_year = bcd2bin(regs[6] & BQ32002_YEAR_MASK);
+	timeptr->tm_yday = -1;  /* Unsupported */
+	timeptr->tm_isdst = -1; /* Unsupported */
+	timeptr->tm_nsec = 0;   /* Unsupported */
+
+	/* Apply century offset */
+	if (regs[2] & BQ32002_CENT_MASK) {
+		timeptr->tm_year += BQ32002_TM_YEAR_2000;
+	}
+
+out_unlock:
+	bq32002_unlock_sem(dev);
+
+	if (!err) {
+		LOG_DBG("Read time: year: %d, month: %d, month day: %d, week day: %d, hour: %d, "
+			"minute: "
+			"%d, second: %d",
+			timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday,
+			timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
+	}
+
+	return err;
+}
+
+#ifdef CONFIG_RTC_CALIBRATION
+
+static int bq32002_set_calibration(const struct device *dev, int32_t freq_ppb)
+{
+	const struct bq32002_config *config = dev->config;
+	int err;
+	uint8_t offset;
+	uint8_t reg_val;
+
+	if ((freq_ppb < BQ32002_CAL_PPB_MIN) || (freq_ppb > BQ32002_CAL_PPB_MAX)) {
+		LOG_ERR("Calibration value %d ppb out of range", freq_ppb);
+		return -EINVAL;
+	}
+
+	err = i2c_reg_read_byte_dt(&config->i2c, BQ32002_CAL_CFG1_REG, &reg_val);
+	if (err) {
+		return err;
+	}
+
+	reg_val &= ~(BQ32002_CAL_SIGN_MASK | BQ32002_CAL_MASK);
+
+	if (freq_ppb > 0) {
+		reg_val |= BQ32002_CAL_SIGN_MASK; /* Negative sign speeds the oscillator up */
+		offset =
+			DIV_ROUND_CLOSEST(freq_ppb, BQ32002_CAL_PPB_PER_LSB_NEG) & BQ32002_CAL_MASK;
+	} else {
+		offset = DIV_ROUND_CLOSEST(-freq_ppb, BQ32002_CAL_PPB_PER_LSB_POS) &
+			 BQ32002_CAL_MASK;
+	}
+	reg_val |= offset;
+
+	err = i2c_reg_write_byte_dt(&config->i2c, BQ32002_CAL_CFG1_REG, reg_val);
+	if (err) {
+		return err;
+	}
+
+	LOG_DBG("Set calibration: frequency ppb: %d, offset value: %d, sign: %d", freq_ppb, offset,
+		freq_ppb > 0);
+
+	return 0;
+}
+
+static int bq32002_get_calibration(const struct device *dev, int32_t *freq_ppb)
+{
+	const struct bq32002_config *config = dev->config;
+	uint8_t reg_val;
+	uint8_t offset;
+	int err;
+
+	err = i2c_reg_read_byte_dt(&config->i2c, BQ32002_CAL_CFG1_REG, &reg_val);
+	if (err) {
+		return err;
+	}
+
+	offset = reg_val & BQ32002_CAL_MASK;
+
+	if (reg_val & BQ32002_CAL_SIGN_MASK) {
+		*freq_ppb = offset * BQ32002_CAL_PPB_PER_LSB_NEG;
+	} else {
+		*freq_ppb = -offset * BQ32002_CAL_PPB_PER_LSB_POS;
+	}
+
+	LOG_DBG("Get calibration: frequency ppb: %d, offset value: %d, sign: %d", *freq_ppb, offset,
+		*freq_ppb > 0);
+
+	return 0;
+}
+
+#endif
+
+static DEVICE_API(rtc, bq32002_driver_api) = {
+	.set_time = bq32002_set_time,
+	.get_time = bq32002_get_time,
+#ifdef CONFIG_RTC_CALIBRATION
+	.set_calibration = bq32002_set_calibration,
+	.get_calibration = bq32002_get_calibration
+#endif
+};
+
+static int bq32002_init(const struct device *dev)
+{
+	const struct bq32002_config *config = dev->config;
+	struct bq32002_data *data = dev->data;
+	int err;
+
+	(void)k_sem_init(&data->lock, 1, 1);
+
+	if (!i2c_is_ready_dt(&config->i2c)) {
+		LOG_ERR("I2C bus not ready");
+		return -ENODEV;
+	}
+
+	/* Start the oscillator */
+	err = i2c_reg_update_byte_dt(&config->i2c, BQ32002_SECONDS_REG, BQ32002_OSC_STOP_MASK, 0);
+	if (err) {
+		return err;
+	}
+
+	/* Configure IRQ output frequency */
+	err = bq32002_set_irq_frequency(dev);
+	if (err) {
+		return err;
+	}
+
+	return 0;
+}
+
+#define BQ32002_INIT(inst)                                                                         \
+	static struct bq32002_data bq32002_data_##inst;                                            \
+	static const struct bq32002_config bq32002_config_##inst = {                               \
+		.i2c = I2C_DT_SPEC_INST_GET(inst),                                                 \
+		.irq_freq =                                                                        \
+			DT_INST_ENUM_IDX_OR(inst, irq_frequency, BQ32002_IRQ_FREQ_ENUM_DISABLED)   \
+		};										   \
+	DEVICE_DT_INST_DEFINE(inst, &bq32002_init, NULL, &bq32002_data_##inst,                     \
+			      &bq32002_config_##inst, POST_KERNEL, CONFIG_RTC_INIT_PRIORITY,       \
+			      &bq32002_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(BQ32002_INIT)
diff --git a/drivers/rtc/rtc_ds1307.c b/drivers/rtc/rtc_ds1307.c
index 48b934102cd..b5685cddd13 100644
--- a/drivers/rtc/rtc_ds1307.c
+++ b/drivers/rtc/rtc_ds1307.c
@@ -3,6 +3,8 @@
  *
  * Copyright (c) 2023 Arunmani Alagarsamy
  * Author: Arunmani Alagarsamy  <arunmani27100@gmail.com>
+ *
+ * Copyright (c) 2025 Marcin Lyda <elektromarcin@gmail.com>
  */
 
 #include <zephyr/drivers/i2c.h>
@@ -25,6 +27,7 @@ LOG_MODULE_REGISTER(ds1307, CONFIG_RTC_LOG_LEVEL);
 #define DS1307_REG_YEAR    0x06
 #define DS1307_REG_CTRL    0x07
 
+/* DS1307 bitmasks */
 #define SECONDS_BITS  GENMASK(6, 0)
 #define MINUTES_BITS  GENMASK(7, 0)
 #define HOURS_BITS    GENMASK(5, 0)
@@ -34,8 +37,24 @@ LOG_MODULE_REGISTER(ds1307, CONFIG_RTC_LOG_LEVEL);
 #define YEAR_BITS     GENMASK(7, 0)
 #define VALIDATE_24HR BIT(6)
 
+#define CTRL_RS_BITS  GENMASK(1, 0)
+#define CTRL_SQWE_BIT BIT(4)
+
+#define SQW_FREQ_1Hz     FIELD_PREP(CTRL_RS_BITS, 0x00)
+#define SQW_FREQ_4096Hz  FIELD_PREP(CTRL_RS_BITS, 0x01)
+#define SQW_FREQ_8192Hz  FIELD_PREP(CTRL_RS_BITS, 0x02)
+#define SQW_FREQ_32768Hz FIELD_PREP(CTRL_RS_BITS, 0x03)
+
+/* SQW frequency property enum values */
+#define SQW_PROP_ENUM_1HZ      0
+#define SQW_PROP_ENUM_4096HZ   1
+#define SQW_PROP_ENUM_8192HZ   2
+#define SQW_PROP_ENUM_32768HZ  3
+#define SQW_PROP_ENUM_DISABLED 4
+
 struct ds1307_config {
 	struct i2c_dt_spec i2c_bus;
+	uint8_t sqw_freq;
 };
 
 struct ds1307_data {
@@ -126,6 +145,7 @@ static DEVICE_API(rtc, ds1307_driver_api) = {
 static int ds1307_init(const struct device *dev)
 {
 	int err;
+	uint8_t reg_val;
 	const struct ds1307_config *config = dev->config;
 
 	if (!i2c_is_ready_dt(&config->i2c_bus)) {
@@ -133,25 +153,42 @@ static int ds1307_init(const struct device *dev)
 		return -ENODEV;
 	}
 
-	/* Disable squarewave output */
-	err = i2c_reg_write_byte_dt(&config->i2c_bus, DS1307_REG_CTRL, 0x00);
+	/* Configure SQW output frequency */
+	reg_val = CTRL_SQWE_BIT;
+	switch (config->sqw_freq) {
+	case SQW_PROP_ENUM_1HZ:
+		reg_val |= SQW_FREQ_1Hz;
+		break;
+	case SQW_PROP_ENUM_4096HZ:
+		reg_val |= SQW_FREQ_4096Hz;
+		break;
+	case SQW_PROP_ENUM_8192HZ:
+		reg_val |= SQW_FREQ_8192Hz;
+		break;
+	case SQW_PROP_ENUM_32768HZ:
+		reg_val |= SQW_FREQ_32768Hz;
+		break;
+	case SQW_PROP_ENUM_DISABLED:
+	default:
+		reg_val &= ~CTRL_SQWE_BIT;
+		break;
+	}
+	err = i2c_reg_write_byte_dt(&config->i2c_bus, DS1307_REG_CTRL, reg_val);
 	if (err < 0) {
-		LOG_ERR("Error: SQW: %d\n", err);
+		LOG_ERR("Error: Configure SQW: %d", err);
 	}
 
 	/* Ensure Clock Halt = 0 */
-	uint8_t reg = 0;
-
-	err = i2c_reg_read_byte_dt(&config->i2c_bus, DS1307_REG_SECONDS, &reg);
+	err = i2c_reg_read_byte_dt(&config->i2c_bus, DS1307_REG_SECONDS, &reg_val);
 	if (err < 0) {
-		LOG_ERR("Error: Read SECONDS/Clock Halt register: %d\n", err);
+		LOG_ERR("Error: Read SECONDS/Clock Halt register: %d", err);
 	}
-	if (reg & ~SECONDS_BITS) {
+	if (reg_val & ~SECONDS_BITS) {
 		/* Clock Halt bit is set */
 		err = i2c_reg_write_byte_dt(&config->i2c_bus, DS1307_REG_SECONDS,
-					    reg & SECONDS_BITS);
+					    reg_val & SECONDS_BITS);
 		if (err < 0) {
-			LOG_ERR("Error: Clear Clock Halt bit: %d\n", err);
+			LOG_ERR("Error: Clear Clock Halt bit: %d", err);
 		}
 	}
 
@@ -162,7 +199,8 @@ static int ds1307_init(const struct device *dev)
 	static struct ds1307_data ds1307_data_##inst;                                              \
 	static const struct ds1307_config ds1307_config_##inst = {                                 \
 		.i2c_bus = I2C_DT_SPEC_INST_GET(inst),                                             \
-	};                                                                                         \
+		.sqw_freq = DT_INST_ENUM_IDX_OR(inst, sqw_frequency, SQW_PROP_ENUM_DISABLED)	   \
+	};											   \
 	DEVICE_DT_INST_DEFINE(inst, &ds1307_init, NULL, &ds1307_data_##inst,                       \
 			      &ds1307_config_##inst, POST_KERNEL, CONFIG_RTC_INIT_PRIORITY,        \
 			      &ds1307_driver_api);
diff --git a/drivers/rtc/rtc_ds1337.c b/drivers/rtc/rtc_ds1337.c
new file mode 100644
index 00000000000..209f5086d1c
--- /dev/null
+++ b/drivers/rtc/rtc_ds1337.c
@@ -0,0 +1,737 @@
+/*
+ * Copyright (c) 2025 Marcin Lyda <elektromarcin@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/rtc.h>
+#include <zephyr/drivers/gpio.h>
+#include "rtc_utils.h"
+
+LOG_MODULE_REGISTER(ds1337, CONFIG_RTC_LOG_LEVEL);
+
+#define DT_DRV_COMPAT maxim_ds1337
+
+#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 0
+#warning "Maxim DS1337 RTC driver enabled without any devices"
+#endif
+
+/* Registers */
+#define DS1337_SECONDS_REG          0x00
+#define DS1337_ALARM_1_SECONDS_REG  0x07
+#define DS1337_ALARM_2_MINUTES_REG  0x0B
+#define DS1337_CONTROL_REG          0x0E
+#define DS1337_STATUS_REG           0x0F
+
+/* Bitmasks */
+#define DS1337_SECONDS_MASK       GENMASK(6, 0)
+#define DS1337_MINUTES_MASK       GENMASK(6, 0)
+#define DS1337_HOURS_MASK         GENMASK(5, 0)
+#define DS1337_DAY_MASK           GENMASK(2, 0)
+#define DS1337_DATE_MASK          GENMASK(5, 0)
+#define DS1337_MONTH_MASK         GENMASK(4, 0)
+#define DS1337_YEAR_MASK          GENMASK(7, 0)
+#define DS1337_ALARM_SECONDS_MASK GENMASK(6, 0)
+#define DS1337_ALARM_MINUTES_MASK GENMASK(6, 0)
+#define DS1337_ALARM_HOURS_MASK   GENMASK(5, 0)
+#define DS1337_ALARM_DAY_MASK     GENMASK(3, 0)
+#define DS1337_ALARM_DATE_MASK    GENMASK(5, 0)
+
+#define DS1337_12_24_MODE_MASK BIT(6)
+#define DS1337_CENTURY_MASK    BIT(7)
+#define DS1337_DY_DT_MASK      BIT(6)
+
+#define DS1337_ALARM_DISABLE_MASK BIT(7)
+
+#define DS1337_EOSC_MASK  BIT(7)
+#define DS1337_RS_MASK    GENMASK(4, 3)
+#define DS1337_INTCN_MASK BIT(2)
+#define DS1337_A2IE_MASK  BIT(1)
+#define DS1337_A1IE_MASK  BIT(0)
+
+#define DS1337_OSF_MASK BIT(7)
+#define DS1337_A2F_MASK BIT(1)
+#define DS1337_A1F_MASK BIT(0)
+
+#define DS1337_SQW_FREQ_1Hz     FIELD_PREP(DS1337_RS_MASK, 0x00)
+#define DS1337_SQW_FREQ_4096Hz  FIELD_PREP(DS1337_RS_MASK, 0x01)
+#define DS1337_SQW_FREQ_8192Hz  FIELD_PREP(DS1337_RS_MASK, 0x02)
+#define DS1337_SQW_FREQ_32768Hz FIELD_PREP(DS1337_RS_MASK, 0x03)
+
+/* DS1337 features two independent alarms */
+#define DS1337_ALARM_1_ID   0
+#define DS1337_ALARM_2_ID   1
+#define DS1337_ALARMS_COUNT 2
+
+/* SQW frequency property enum values */
+#define DS1337_SQW_PROP_ENUM_1HZ     0
+#define DS1337_SQW_PROP_ENUM_4096HZ  1
+#define DS1337_SQW_PROP_ENUM_8192HZ  2
+#define DS1337_SQW_PROP_ENUM_32768HZ 3
+
+/* DS1337 counts weekdays from 1 to 7 */
+#define DS1337_DAY_OFFSET -1
+
+/* DS1337 counts months 1 to 12 */
+#define DS1337_MONTH_OFFSET -1
+
+/* Year 2000 value represented as tm_year value */
+#define DS1337_TM_YEAR_2000 (2000 - 1900)
+
+/* RTC time fields supported by DS1337 */
+#define DS1337_RTC_TIME_MASK                                                                       \
+	(RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR |      \
+	 RTC_ALARM_TIME_MASK_MONTH | RTC_ALARM_TIME_MASK_MONTHDAY | RTC_ALARM_TIME_MASK_YEAR |     \
+	 RTC_ALARM_TIME_MASK_WEEKDAY)
+
+/* RTC alarm 1 fields supported by DS1337 */
+#define DS1337_RTC_ALARM_TIME_1_MASK                                                               \
+	(RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR |      \
+	 RTC_ALARM_TIME_MASK_MONTHDAY | RTC_ALARM_TIME_MASK_WEEKDAY)
+
+/* RTC alarm 2 fields supported by DS1337 */
+#define DS1337_RTC_ALARM_TIME_2_MASK                                                               \
+	(RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR | RTC_ALARM_TIME_MASK_MONTHDAY |    \
+	 RTC_ALARM_TIME_MASK_WEEKDAY)
+
+/* Helper macro to guard GPIO interrupt related stuff */
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) && defined(CONFIG_RTC_ALARM)
+#define DS1337_INT_GPIOS_IN_USE 1
+#endif
+
+struct ds1337_config {
+	const struct i2c_dt_spec i2c;
+#ifdef DS1337_INT_GPIOS_IN_USE
+	struct gpio_dt_spec gpio_int;
+#endif
+	uint8_t sqw_freq;
+};
+
+struct ds1337_data {
+	struct k_sem lock;
+#ifdef DS1337_INT_GPIOS_IN_USE
+	const struct device *dev;
+	struct gpio_callback irq_callback;
+	struct k_work work;
+#ifdef CONFIG_RTC_ALARM
+	rtc_alarm_callback alarm_callbacks[DS1337_ALARMS_COUNT];
+	void *alarm_user_data[DS1337_ALARMS_COUNT];
+#endif
+#endif
+};
+
+static void ds1337_lock_sem(const struct device *dev)
+{
+	struct ds1337_data *data = dev->data;
+
+	(void)k_sem_take(&data->lock, K_FOREVER);
+}
+
+static void ds1337_unlock_sem(const struct device *dev)
+{
+	struct ds1337_data *data = dev->data;
+
+	k_sem_give(&data->lock);
+}
+
+static bool ds1337_validate_alarm_mask(uint16_t alarm_mask, uint16_t alarm_id)
+{
+	const uint16_t allowed_configs[6] = {
+		0,
+		RTC_ALARM_TIME_MASK_SECOND,
+		RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE,
+		RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR,
+		RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR |
+			RTC_ALARM_TIME_MASK_WEEKDAY,
+		RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR |
+			RTC_ALARM_TIME_MASK_MONTHDAY
+	};
+
+	const uint16_t available_fields =
+		(alarm_id == 0) ? DS1337_RTC_ALARM_TIME_1_MASK : DS1337_RTC_ALARM_TIME_2_MASK;
+	if (alarm_mask & ~available_fields) {
+		return false;
+	}
+
+	ARRAY_FOR_EACH_PTR(allowed_configs, config) {
+		if (alarm_mask == (*config & available_fields)) {
+			return true;
+		}
+	}
+	return false;
+}
+
+#ifdef DS1337_INT_GPIOS_IN_USE
+
+static void ds1337_work_callback(struct k_work *work)
+{
+	struct ds1337_data *data = CONTAINER_OF(work, struct ds1337_data, work);
+	const struct device *dev = data->dev;
+	const struct ds1337_config *config = dev->config;
+	rtc_alarm_callback alarm_callbacks[DS1337_ALARMS_COUNT] = {NULL};
+	void *alarm_user_data[DS1337_ALARMS_COUNT] = {NULL};
+	uint8_t status_reg;
+	int err;
+
+	ds1337_lock_sem(dev);
+
+	/* Read status register */
+	err = i2c_reg_read_byte_dt(&config->i2c, DS1337_STATUS_REG, &status_reg);
+	if (err) {
+		goto out_unlock;
+	}
+
+#ifdef CONFIG_RTC_ALARM
+	/* Handle alarm 1 event */
+	if ((status_reg & DS1337_A1F_MASK) && (data->alarm_callbacks[DS1337_ALARM_1_ID] != NULL)) {
+		status_reg &= ~DS1337_A1F_MASK;
+		alarm_callbacks[DS1337_ALARM_1_ID] = data->alarm_callbacks[DS1337_ALARM_1_ID];
+		alarm_user_data[DS1337_ALARM_1_ID] = data->alarm_user_data[DS1337_ALARM_1_ID];
+	}
+
+	/* Handle alarm 2 event */
+	if ((status_reg & DS1337_A2F_MASK) && (data->alarm_callbacks[DS1337_ALARM_2_ID] != NULL)) {
+		status_reg &= ~DS1337_A2F_MASK;
+		alarm_callbacks[DS1337_ALARM_2_ID] = data->alarm_callbacks[DS1337_ALARM_2_ID];
+		alarm_user_data[DS1337_ALARM_2_ID] = data->alarm_user_data[DS1337_ALARM_2_ID];
+	}
+#endif
+
+	/* Clear alarm flag(s) */
+	err = i2c_reg_write_byte_dt(&config->i2c, DS1337_STATUS_REG, status_reg);
+	if (err) {
+		goto out_unlock;
+	}
+
+	/* Check if any interrupt occurred between flags register read/write */
+	err = i2c_reg_read_byte_dt(&config->i2c, DS1337_STATUS_REG, &status_reg);
+	if (err) {
+		goto out_unlock;
+	}
+
+	if (((status_reg & DS1337_A1F_MASK) && (alarm_callbacks[0] != NULL)) ||
+	    ((status_reg & DS1337_A2F_MASK) && (alarm_callbacks[1] != NULL))) {
+		/* Another interrupt occurred while servicing this one */
+		(void)k_work_submit(&data->work);
+	}
+
+out_unlock:
+	ds1337_unlock_sem(dev);
+
+	/* Execute alarm callback(s) */
+	for (uint8_t alarm_id = DS1337_ALARM_1_ID; alarm_id < DS1337_ALARMS_COUNT; ++alarm_id) {
+		if (alarm_callbacks[alarm_id] != NULL) {
+			alarm_callbacks[alarm_id](dev, alarm_id, alarm_user_data[alarm_id]);
+			alarm_callbacks[alarm_id] = NULL;
+		}
+	}
+}
+
+static void ds1337_irq_handler(const struct device *port, struct gpio_callback *callback,
+			       gpio_port_pins_t pins)
+{
+	ARG_UNUSED(port);
+	ARG_UNUSED(pins);
+
+	struct ds1337_data *data = CONTAINER_OF(callback, struct ds1337_data, irq_callback);
+
+	(void)k_work_submit(&data->work);
+}
+
+#endif
+
+static int ds1337_set_time(const struct device *dev, const struct rtc_time *timeptr)
+{
+	const struct ds1337_config *config = dev->config;
+	uint8_t regs[7];
+	int err;
+
+	if ((timeptr == NULL) || !rtc_utils_validate_rtc_time(timeptr, DS1337_RTC_TIME_MASK)) {
+		return -EINVAL;
+	}
+
+	ds1337_lock_sem(dev);
+
+	regs[0] = bin2bcd(timeptr->tm_sec) & DS1337_SECONDS_MASK;
+	regs[1] = bin2bcd(timeptr->tm_min) & DS1337_MINUTES_MASK;
+	regs[2] = bin2bcd(timeptr->tm_hour) & DS1337_HOURS_MASK;
+	regs[3] = bin2bcd(timeptr->tm_wday - DS1337_DAY_OFFSET) & DS1337_DAY_MASK;
+	regs[4] = bin2bcd(timeptr->tm_mday) & DS1337_DATE_MASK;
+	regs[5] = bin2bcd(timeptr->tm_mon - DS1337_MONTH_OFFSET) & DS1337_MONTH_MASK;
+
+	/* Determine which century we're in */
+	if (timeptr->tm_year >= DS1337_TM_YEAR_2000) {
+		regs[5] |= DS1337_CENTURY_MASK;
+		regs[6] = bin2bcd(timeptr->tm_year - DS1337_TM_YEAR_2000) & DS1337_YEAR_MASK;
+	} else {
+		regs[6] = bin2bcd(timeptr->tm_year) & DS1337_YEAR_MASK;
+	}
+
+	/* Set new time */
+	err = i2c_burst_write_dt(&config->i2c, DS1337_SECONDS_REG, regs, sizeof(regs));
+	if (err) {
+		goto out_unlock;
+	}
+
+	/* Clear Oscillator Stop Flag, indicating data validity */
+	err = i2c_reg_update_byte_dt(&config->i2c, DS1337_STATUS_REG, DS1337_OSF_MASK, 0);
+
+out_unlock:
+	ds1337_unlock_sem(dev);
+
+	if (!err) {
+		LOG_DBG("Set time: year: %d, month: %d, month day: %d, week day: %d, hour: %d, "
+			"minute: %d, second: %d",
+			timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday,
+			timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
+	}
+
+	return err;
+}
+
+static int ds1337_get_time(const struct device *dev, struct rtc_time *timeptr)
+{
+	const struct ds1337_config *config = dev->config;
+	uint8_t regs[7];
+	uint8_t status_reg;
+	int err;
+
+	if (timeptr == NULL) {
+		return -EINVAL;
+	}
+
+	ds1337_lock_sem(dev);
+
+	/* Check data validity */
+	err = i2c_reg_read_byte_dt(&config->i2c, DS1337_STATUS_REG, &status_reg);
+	if (err) {
+		goto out_unlock;
+	}
+	if (status_reg & DS1337_OSF_MASK) {
+		err = -ENODATA;
+		goto out_unlock;
+	}
+
+	/* Read time data */
+	err = i2c_burst_read_dt(&config->i2c, DS1337_SECONDS_REG, regs, sizeof(regs));
+	if (err) {
+		goto out_unlock;
+	}
+
+	timeptr->tm_sec = bcd2bin(regs[0] & DS1337_SECONDS_MASK);
+	timeptr->tm_min = bcd2bin(regs[1] & DS1337_MINUTES_MASK);
+	timeptr->tm_hour = bcd2bin(regs[2] & DS1337_HOURS_MASK);
+	timeptr->tm_wday = bcd2bin(regs[3] & DS1337_DAY_MASK) + DS1337_DAY_OFFSET;
+	timeptr->tm_mday = bcd2bin(regs[4] & DS1337_DATE_MASK);
+	timeptr->tm_mon = bcd2bin(regs[5] & DS1337_MONTH_MASK) + DS1337_MONTH_OFFSET;
+	timeptr->tm_year = bcd2bin(regs[6] & DS1337_YEAR_MASK);
+	timeptr->tm_yday = -1;  /* Unsupported */
+	timeptr->tm_isdst = -1; /* Unsupported */
+	timeptr->tm_nsec = 0;   /* Unsupported */
+
+	/* Apply century offset */
+	if (regs[5] & DS1337_CENTURY_MASK) {
+		timeptr->tm_year += DS1337_TM_YEAR_2000;
+	}
+
+out_unlock:
+	ds1337_unlock_sem(dev);
+
+	if (!err) {
+		LOG_DBG("Read time: year: %d, month: %d, month day: %d, week day: %d, hour: %d, "
+			"minute: %d, second: %d",
+			timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday,
+			timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
+	}
+
+	return err;
+}
+
+#ifdef CONFIG_RTC_ALARM
+
+static int ds1337_alarm_get_supported_fields(const struct device *dev, uint16_t id, uint16_t *mask)
+{
+	ARG_UNUSED(dev);
+
+	if (id == DS1337_ALARM_1_ID) {
+		*mask = DS1337_RTC_ALARM_TIME_1_MASK;
+		return 0;
+	} else if (id == DS1337_ALARM_2_ID) {
+		*mask = DS1337_RTC_ALARM_TIME_2_MASK;
+		return 0;
+	}
+
+	LOG_ERR("Invalid alarm ID: %d", id);
+	return -EINVAL;
+}
+
+static int ds1337_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
+				 const struct rtc_time *timeptr)
+{
+	const struct ds1337_config *config = dev->config;
+	uint8_t regs[4];
+	uint8_t reg_addr;
+	uint8_t reg_offset;
+	int err;
+
+	if (id >= DS1337_ALARMS_COUNT) {
+		LOG_ERR("Invalid alarm ID: %d", id);
+		return -EINVAL;
+	}
+
+	if ((mask & RTC_ALARM_TIME_MASK_MONTHDAY) && (mask & RTC_ALARM_TIME_MASK_WEEKDAY)) {
+		LOG_ERR("Month day and week day alarms cannot be set simultaneously");
+		return -EINVAL;
+	}
+
+	if (!ds1337_validate_alarm_mask(mask, id)) {
+		LOG_ERR("Unsupported mask 0x%04X for alarm %d", mask, id);
+		return -EINVAL;
+	}
+
+	if (!rtc_utils_validate_rtc_time(timeptr, mask)) {
+		LOG_ERR("Invalid alarm time");
+		return -EINVAL;
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_SECOND) {
+		regs[0] = bin2bcd(timeptr->tm_sec) & DS1337_ALARM_SECONDS_MASK;
+	} else {
+		regs[0] = DS1337_ALARM_DISABLE_MASK;
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
+		regs[1] = bin2bcd(timeptr->tm_min) & DS1337_ALARM_MINUTES_MASK;
+	} else {
+		regs[1] = DS1337_ALARM_DISABLE_MASK;
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_HOUR) {
+		regs[2] = bin2bcd(timeptr->tm_hour) & DS1337_ALARM_HOURS_MASK;
+	} else {
+		regs[2] = DS1337_ALARM_DISABLE_MASK;
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
+		regs[3] = bin2bcd(timeptr->tm_mday) & DS1337_ALARM_DATE_MASK;
+	} else if (mask & RTC_ALARM_TIME_MASK_WEEKDAY) {
+		regs[3] = bin2bcd(timeptr->tm_wday - DS1337_DAY_OFFSET) & DS1337_ALARM_DAY_MASK;
+		regs[3] |= DS1337_DY_DT_MASK;
+	} else {
+		regs[3] = DS1337_ALARM_DISABLE_MASK;
+	}
+
+	/* Update alarm registers */
+	if (id == DS1337_ALARM_1_ID) {
+		reg_addr = DS1337_ALARM_1_SECONDS_REG;
+		reg_offset = 0;
+	} else {
+		reg_addr = DS1337_ALARM_2_MINUTES_REG;
+		reg_offset = 1;
+	}
+
+	err = i2c_burst_write_dt(&config->i2c, reg_addr, &regs[reg_offset],
+				 sizeof(regs) - reg_offset);
+	if (err) {
+		return err;
+	}
+
+	LOG_DBG("Set alarm: month day: %d, week day: %d, hour: %d, minute: %d, second: %d mask: "
+		"0x%04X",
+		timeptr->tm_mday, timeptr->tm_wday, timeptr->tm_hour, timeptr->tm_min,
+		timeptr->tm_sec, mask);
+
+	return 0;
+}
+
+static int ds1337_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
+				 struct rtc_time *timeptr)
+{
+	const struct ds1337_config *config = dev->config;
+	uint8_t regs[4];
+	uint8_t reg_addr;
+	uint8_t reg_offset;
+	int err;
+
+	if (id >= DS1337_ALARMS_COUNT) {
+		LOG_ERR("Invalid alarm ID: %d", id);
+		return -EINVAL;
+	}
+
+	/* Read alarm registers */
+	if (id == DS1337_ALARM_1_ID) {
+		reg_addr = DS1337_ALARM_1_SECONDS_REG;
+		reg_offset = 0;
+	} else {
+		reg_addr = DS1337_ALARM_2_MINUTES_REG;
+		reg_offset = 1;
+	}
+	err = i2c_burst_read_dt(&config->i2c, reg_addr, &regs[reg_offset],
+				sizeof(regs) - reg_offset);
+	if (err) {
+		return err;
+	}
+
+	(void)memset(timeptr, 0, sizeof(*timeptr));
+	*mask = 0;
+
+	if ((regs[0] & DS1337_ALARM_DISABLE_MASK) == 0) {
+		timeptr->tm_sec = bcd2bin(regs[0] & DS1337_ALARM_SECONDS_MASK);
+		*mask |= RTC_ALARM_TIME_MASK_SECOND;
+	}
+
+	if ((regs[1] & DS1337_ALARM_DISABLE_MASK) == 0) {
+		timeptr->tm_min = bcd2bin(regs[1] & DS1337_ALARM_MINUTES_MASK);
+		*mask |= RTC_ALARM_TIME_MASK_MINUTE;
+	}
+
+	if ((regs[2] & DS1337_ALARM_DISABLE_MASK) == 0) {
+		timeptr->tm_hour = bcd2bin(regs[2] & DS1337_ALARM_HOURS_MASK);
+		*mask |= RTC_ALARM_TIME_MASK_HOUR;
+	}
+
+	if ((regs[3] & DS1337_ALARM_DISABLE_MASK) == 0) {
+		if ((regs[3] & DS1337_DY_DT_MASK) == 0) {
+			timeptr->tm_mday = bcd2bin(regs[3] & DS1337_ALARM_DATE_MASK);
+			*mask |= RTC_ALARM_TIME_MASK_MONTHDAY;
+		} else {
+			timeptr->tm_wday =
+				bcd2bin(regs[3] & DS1337_ALARM_DAY_MASK) + DS1337_DAY_OFFSET;
+			*mask |= RTC_ALARM_TIME_MASK_WEEKDAY;
+		}
+	}
+
+	LOG_DBG("Get alarm: month day: %d, week day: %d, hour: %d, minute: %d, second: %d mask: "
+		"0x%04X",
+		timeptr->tm_mday, timeptr->tm_wday, timeptr->tm_hour, timeptr->tm_min,
+		timeptr->tm_sec, *mask);
+
+	return 0;
+}
+
+static int ds1337_alarm_is_pending(const struct device *dev, uint16_t id)
+{
+	const struct ds1337_config *config = dev->config;
+	uint8_t pending = 0;
+	uint8_t status_reg;
+	int err;
+
+	if (id >= DS1337_ALARMS_COUNT) {
+		LOG_ERR("Invalid alarm ID: %d", id);
+		return -EINVAL;
+	}
+
+	ds1337_lock_sem(dev);
+
+	err = i2c_reg_read_byte_dt(&config->i2c, DS1337_STATUS_REG, &status_reg);
+	if (err) {
+		goto out_unlock;
+	}
+
+	if (id == DS1337_ALARM_1_ID) {
+		if (status_reg & DS1337_A1F_MASK) {
+			status_reg &= ~DS1337_A1F_MASK;
+			pending = 1;
+		}
+	} else {
+		if (status_reg & DS1337_A2F_MASK) {
+			status_reg &= ~DS1337_A2F_MASK;
+			pending = 1;
+		}
+	}
+
+	err = i2c_reg_write_byte_dt(&config->i2c, DS1337_STATUS_REG, status_reg);
+	if (err) {
+		goto out_unlock;
+	}
+
+out_unlock:
+	ds1337_unlock_sem(dev);
+
+	if (err) {
+		return err;
+	}
+	return pending;
+}
+
+#ifdef DS1337_INT_GPIOS_IN_USE
+
+static int ds1337_alarm_set_callback(const struct device *dev, uint16_t id,
+				     rtc_alarm_callback callback, void *user_data)
+{
+	const struct ds1337_config *config = dev->config;
+	struct ds1337_data *data = dev->data;
+	uint8_t reg_val = 0;
+	uint8_t mask = 0;
+	int err;
+
+	if (config->gpio_int.port == NULL) {
+		return -ENOTSUP;
+	}
+
+	if (id >= DS1337_ALARMS_COUNT) {
+		LOG_ERR("Invalid alarm ID: %d", id);
+		return -EINVAL;
+	}
+
+	ds1337_lock_sem(dev);
+
+	data->alarm_callbacks[id] = callback;
+	data->alarm_user_data[id] = user_data;
+
+	/* Enable alarm interrupt if callback provided */
+	if (id == DS1337_ALARM_1_ID) {
+		mask = DS1337_A1IE_MASK;
+		reg_val = (callback != NULL) ? DS1337_A1IE_MASK : 0;
+	} else {
+		mask = DS1337_A2IE_MASK;
+		reg_val = (callback != NULL) ? DS1337_A2IE_MASK : 0;
+	}
+	err = i2c_reg_update_byte_dt(&config->i2c, DS1337_CONTROL_REG, mask, reg_val);
+
+	ds1337_unlock_sem(dev);
+
+	/* Alarm IRQ might have already been triggered */
+	(void)k_work_submit(&data->work);
+
+	return err;
+}
+
+#endif
+
+#endif
+
+static int ds1337_init(const struct device *dev)
+{
+	const struct ds1337_config *config = dev->config;
+	struct ds1337_data *data = dev->data;
+	uint8_t reg_val;
+	int err;
+
+	(void)k_sem_init(&data->lock, 1, 1);
+
+	if (!i2c_is_ready_dt(&config->i2c)) {
+		LOG_ERR("I2C bus not ready");
+		return -ENODEV;
+	}
+
+#ifdef DS1337_INT_GPIOS_IN_USE
+	if (config->gpio_int.port != NULL) {
+		if (!gpio_is_ready_dt(&config->gpio_int)) {
+			LOG_ERR("GPIO not ready");
+			return -ENODEV;
+		}
+
+		err = gpio_pin_configure_dt(&config->gpio_int, GPIO_INPUT);
+		if (err) {
+			LOG_ERR("Failed to configure interrupt GPIO, error: %d", err);
+			return err;
+		}
+
+		err = gpio_pin_interrupt_configure_dt(&config->gpio_int, GPIO_INT_EDGE_TO_ACTIVE);
+		if (err) {
+			LOG_ERR("Failed to enable GPIO interrupt, error: %d", err);
+			return err;
+		}
+
+		gpio_init_callback(&data->irq_callback, ds1337_irq_handler,
+				   BIT(config->gpio_int.pin));
+
+		err = gpio_add_callback_dt(&config->gpio_int, &data->irq_callback);
+		if (err) {
+			LOG_ERR("Failed to add GPIO callback, error: %d", err);
+			return err;
+		}
+
+		data->dev = dev;
+		data->work.handler = ds1337_work_callback;
+	}
+#endif
+
+	/* Display warning if alarm flags are set */
+	err = i2c_reg_read_byte_dt(&config->i2c, DS1337_STATUS_REG, &reg_val);
+	if (err) {
+		return err;
+	}
+	if (reg_val & DS1337_A1F_MASK) {
+		LOG_WRN("Alarm 1 might have been missed!");
+	}
+	if (reg_val & DS1337_A2F_MASK) {
+		LOG_WRN("Alarm 2 might have been missed!");
+	}
+
+	/* Enable oscillator */
+	err = i2c_reg_update_byte_dt(&config->i2c, DS1337_CONTROL_REG, DS1337_EOSC_MASK, 0);
+	if (err) {
+		return err;
+	}
+
+	/* Configure SQW output frequency */
+	switch (config->sqw_freq) {
+	case DS1337_SQW_PROP_ENUM_1HZ:
+		reg_val = DS1337_SQW_FREQ_1Hz;
+		break;
+	case DS1337_SQW_PROP_ENUM_4096HZ:
+		reg_val = DS1337_SQW_FREQ_4096Hz;
+		break;
+	case DS1337_SQW_PROP_ENUM_8192HZ:
+		reg_val = DS1337_SQW_FREQ_8192Hz;
+		break;
+	case DS1337_SQW_PROP_ENUM_32768HZ:
+	default:
+		reg_val = DS1337_SQW_FREQ_32768Hz;
+		break;
+	}
+
+	/*
+	 * Set SQW frequency, enable oscillator, clear INTCN (both alarms will trigger INTA),
+	 * disable IRQs
+	 */
+	err = i2c_reg_write_byte_dt(&config->i2c, DS1337_CONTROL_REG, reg_val);
+	if (err) {
+		return err;
+	}
+
+	/* Clear alarm flags */
+	err = i2c_reg_update_byte_dt(&config->i2c, DS1337_STATUS_REG,
+				     DS1337_A1F_MASK | DS1337_A2F_MASK, 0);
+	if (err) {
+		return err;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(rtc, ds1337_driver_api) = {
+	.get_time = ds1337_get_time,
+	.set_time = ds1337_set_time,
+#ifdef CONFIG_RTC_ALARM
+	.alarm_get_supported_fields = ds1337_alarm_get_supported_fields,
+	.alarm_set_time = ds1337_alarm_set_time,
+	.alarm_get_time = ds1337_alarm_get_time,
+	.alarm_is_pending = ds1337_alarm_is_pending,
+#ifdef DS1337_INT_GPIOS_IN_USE
+	.alarm_set_callback = ds1337_alarm_set_callback,
+#endif
+#endif
+};
+
+#define DS1337_INIT(inst)                                                                          \
+	static struct ds1337_data ds1337_data_##inst;                                              \
+	static const struct ds1337_config ds1337_config_##inst = {                                 \
+		.i2c = I2C_DT_SPEC_INST_GET(inst),                                                 \
+		.sqw_freq = DT_INST_ENUM_IDX_OR(inst, sqw_frequency, DS1337_SQW_PROP_ENUM_1HZ),    \
+		IF_ENABLED(                                                                        \
+			DS1337_INT_GPIOS_IN_USE,                                                   \
+			(.gpio_int = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, {0}))               \
+		)										   \
+		};										   \
+	DEVICE_DT_INST_DEFINE(inst, &ds1337_init, NULL, &ds1337_data_##inst,                       \
+			      &ds1337_config_##inst, POST_KERNEL, CONFIG_RTC_INIT_PRIORITY,        \
+			      &ds1337_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(DS1337_INIT)
diff --git a/drivers/rtc/rtc_ds3231.c b/drivers/rtc/rtc_ds3231.c
index 0a64e31bb42..3d149fec007 100644
--- a/drivers/rtc/rtc_ds3231.c
+++ b/drivers/rtc/rtc_ds3231.c
@@ -192,12 +192,15 @@ static int rtc_ds3231_modify_ctrl_sts(const struct device *dev,
 
 	return rtc_ds3231_modify_register(dev, reg, &buf, bitmask);
 }
+
+#ifdef CONFIG_RTC_ALARM
 static int rtc_ds3231_get_ctrl_sts(const struct device *dev, uint8_t *buf)
 {
 	const struct rtc_ds3231_conf *config = dev->config;
 
 	return mfd_ds3231_i2c_get_registers(config->mfd, DS3231_REG_CTRL_STS, buf, 1);
 }
+#endif /* CONFIG_RTC_ALARM */
 
 struct rtc_ds3231_settings {
 	bool osc;                      /* bit 0 */
@@ -355,7 +358,7 @@ struct rtc_ds3231_alarm_details {
 };
 static struct rtc_ds3231_alarm_details alarms[] = {{DS3231_REG_ALARM_1_SECONDS, 4},
 						   {DS3231_REG_ALARM_2_MINUTES, 3}};
-static int rtc_ds3231_alarm_get_supported_fields(const struct device *dev, u int16_t id,
+static int rtc_ds3231_alarm_get_supported_fields(const struct device *dev, uint16_t id,
 						 uint16_t *mask)
 {
 	*mask = RTC_ALARM_TIME_MASK_MONTHDAY | RTC_ALARM_TIME_MASK_WEEKDAY |
@@ -641,7 +644,7 @@ static int rtc_ds3231_init_alarms(struct rtc_ds3231_data *data)
 	data->alarms[1] = (struct rtc_ds3231_alarm){NULL, NULL};
 	return 0;
 }
-#endif
+#endif /* CONFIG_RTC_ALARM */
 
 #ifdef CONFIG_RTC_UPDATE
 static int rtc_ds3231_init_update(struct rtc_ds3231_data *data)
@@ -805,7 +808,7 @@ static int rtc_ds3231_init(const struct device *dev)
 	int err = 0;
 
 	const struct rtc_ds3231_conf *config = dev->config;
-	struct rtc_ds3231_data *data = dev->data;
+	struct rtc_ds3231_data __maybe_unused *data = dev->data;
 
 	if (!device_is_ready(config->mfd)) {
 		return -ENODEV;
diff --git a/drivers/rtc/rtc_ll_stm32.c b/drivers/rtc/rtc_ll_stm32.c
index 4b284f2e133..84c6f10272c 100644
--- a/drivers/rtc/rtc_ll_stm32.c
+++ b/drivers/rtc/rtc_ll_stm32.c
@@ -14,6 +14,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/init.h>
 #include <zephyr/devicetree.h>
+#include <zephyr/spinlock.h>
 #include <zephyr/drivers/rtc.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <zephyr/drivers/clock_control.h>
@@ -78,7 +79,7 @@ LOG_MODULE_REGISTER(rtc_stm32, CONFIG_RTC_LOG_LEVEL);
 /* Timeout in microseconds used to wait for flags */
 #define RTC_TIMEOUT 1000000
 
-#ifdef CONFIG_RTC_ALARM
+#ifdef STM32_RTC_ALARM_ENABLED
 #define RTC_STM32_ALARMS_COUNT	DT_INST_PROP(0, alarms_count)
 
 #define RTC_STM32_ALRM_A	0U
@@ -95,7 +96,7 @@ LOG_MODULE_REGISTER(rtc_stm32, CONFIG_RTC_LOG_LEVEL);
 #else
 #define RTC_STM32_EXTI_LINE	0
 #endif /* DT_INST_NODE_HAS_PROP(0, alrm_exti_line) */
-#endif /* CONFIG_RTC_ALARM */
+#endif /* STM32_RTC_ALARM_ENABLED */
 
 #if defined(PWR_CR_DBP) || defined(PWR_CR1_DBP) || defined(PWR_DBPCR_DBP) || defined(PWR_DBPR_DBP)
 /*
@@ -120,7 +121,7 @@ struct rtc_stm32_config {
 #endif
 };
 
-#ifdef CONFIG_RTC_ALARM
+#ifdef STM32_RTC_ALARM_ENABLED
 struct rtc_stm32_alrm {
 	LL_RTC_AlarmTypeDef ll_rtc_alrm;
 	/* user-defined alarm mask, values from RTC_ALARM_TIME_MASK */
@@ -129,14 +130,14 @@ struct rtc_stm32_alrm {
 	void *user_data;
 	bool is_pending;
 };
-#endif /* CONFIG_RTC_ALARM */
+#endif /* STM32_RTC_ALARM_ENABLED */
 
 struct rtc_stm32_data {
-	struct k_mutex lock;
-#ifdef CONFIG_RTC_ALARM
+	struct k_spinlock lock;
+#ifdef STM32_RTC_ALARM_ENABLED
 	struct rtc_stm32_alrm rtc_alrm_a;
 	struct rtc_stm32_alrm rtc_alrm_b;
-#endif /* CONFIG_RTC_ALARM */
+#endif /* STM32_RTC_ALARM_ENABLED */
 };
 
 static int rtc_stm32_configure(const struct device *dev)
@@ -185,7 +186,7 @@ static int rtc_stm32_configure(const struct device *dev)
 	return err;
 }
 
-#ifdef CONFIG_RTC_ALARM
+#ifdef STM32_RTC_ALARM_ENABLED
 static inline ErrorStatus rtc_stm32_init_alarm(RTC_TypeDef *rtc, uint32_t format,
 					LL_RTC_AlarmTypeDef *ll_alarm_struct, uint16_t id)
 {
@@ -329,13 +330,13 @@ static void rtc_stm32_irq_config(const struct device *dev)
 		    rtc_stm32_isr, DEVICE_DT_INST_GET(0), 0);
 	irq_enable(DT_INST_IRQN(0));
 }
-#endif /* CONFIG_RTC_ALARM */
+#endif /* STM32_RTC_ALARM_ENABLED */
 
 static int rtc_stm32_init(const struct device *dev)
 {
 	const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
 	const struct rtc_stm32_config *cfg = dev->config;
-	struct rtc_stm32_data *data = dev->data;
+	__maybe_unused struct rtc_stm32_data *data = dev->data;
 
 	int err = 0;
 
@@ -350,7 +351,35 @@ static int rtc_stm32_init(const struct device *dev)
 		return -EIO;
 	}
 
-	k_mutex_init(&data->lock);
+#if defined(CONFIG_SOC_SERIES_STM32WB0X)
+	/**
+	 * The STM32WB0 series has no bit for clock gating of RTC's APB
+	 * interface. On the other hand, the RTCEN bit that would control
+	 * whether the RTC IP is clock gated or not exists, and has been
+	 * placed in APB0ENR. The call to clock_control_on() that just
+	 * completed should have set this bit to 1.
+	 *
+	 * However, according to RefMan, the software must wait two slow
+	 * clock cycles before the IP is actually usable, due to clock
+	 * resynchronization delays. Sadly, there is no hardware register
+	 * we can poll to wait until RTC is ready...
+	 *
+	 * In worst case scenario of 24 kHz LSI, we have to wait for:
+	 *		tREADY = (2 cycles / 24'000 Hz) ≅ 84µs
+	 *
+	 * Spin until that much time has elapsed, and RTC should be up.
+	 *
+	 * N.B.: we can't use k_busy_wait because it uses the SysTick
+	 * as time base, but SysTick is initialized after the RTC...
+	 */
+	const uint32_t cycles_to_waste =
+		84 * (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / USEC_PER_SEC);
+	volatile uint32_t i = cycles_to_waste;
+
+	while (--i > 0) {
+		/* Do nothing - loop itself burns enough cycles */
+	}
+#endif /* CONFIG_SOC_SERIES_STM32WB0X */
 
 	/* Enable Backup access */
 #if RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION
@@ -362,16 +391,22 @@ static int rtc_stm32_init(const struct device *dev)
 	LL_RCC_SetRTC_HSEPrescaler(cfg->hse_prescaler);
 #endif
 	/* Enable RTC clock source */
-	if (clock_control_configure(clk, (clock_control_subsys_t)&cfg->pclken[1], NULL) != 0) {
-		LOG_ERR("clock configure failed\n");
-		return -EIO;
+	if (cfg->pclken[1].enr != NO_SEL) {
+		err = clock_control_configure(clk, (clock_control_subsys_t)&cfg->pclken[1], NULL);
+
+		if (err < 0) {
+			LOG_ERR("clock configure failed\n");
+			return -EIO;
+		}
 	}
 
 /*
  * On STM32WBAX series, there is no bit in BCDR register to enable RTC.
  * Enabling RTC is done directly via the RCC APB register bit.
+ * On STM32WB0 series, LL_RCC_EnableRTC is not provided by STM32CubeWB0,
+ * but RTC IP clock has already been turned on - skip the call as well.
  */
-#ifndef CONFIG_SOC_SERIES_STM32WBAX
+#if !defined(CONFIG_SOC_SERIES_STM32WBAX) && !defined(CONFIG_SOC_SERIES_STM32WB0X)
 	z_stm32_hsem_lock(CFG_HW_RCC_SEMID, HSEM_LOCK_DEFAULT_RETRY);
 
 	LL_RCC_EnableRTC();
@@ -385,15 +420,15 @@ static int rtc_stm32_init(const struct device *dev)
 	LL_PWR_DisableBkUpAccess();
 #endif /* RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION */
 
-#ifdef CONFIG_RTC_ALARM
+#ifdef STM32_RTC_ALARM_ENABLED
 	rtc_stm32_irq_config(dev);
 
 	ll_func_exti_enable_rtc_alarm_it(RTC_STM32_EXTI_LINE);
 
-	k_mutex_lock(&data->lock, K_FOREVER);
-	memset(&(data->rtc_alrm_a), 0, sizeof(struct rtc_stm32_alrm));
-	memset(&(data->rtc_alrm_b), 0, sizeof(struct rtc_stm32_alrm));
-	k_mutex_unlock(&data->lock);
+	K_SPINLOCK(&data->lock) {
+		memset(&(data->rtc_alrm_a), 0, sizeof(struct rtc_stm32_alrm));
+		memset(&(data->rtc_alrm_b), 0, sizeof(struct rtc_stm32_alrm));
+	}
 #endif /* CONFIG_RTC_ALARM */
 
 	return err;
@@ -405,7 +440,6 @@ static int rtc_stm32_set_time(const struct device *dev, const struct rtc_time *t
 	LL_RTC_TimeTypeDef rtc_time;
 	LL_RTC_DateTypeDef rtc_date;
 	uint32_t real_year = timeptr->tm_year + TM_YEAR_REF;
-	int err = 0;
 
 	if (real_year < RTC_YEAR_REF) {
 		/* RTC does not support years before 2000 */
@@ -417,22 +451,10 @@ static int rtc_stm32_set_time(const struct device *dev, const struct rtc_time *t
 		return -EINVAL;
 	}
 
-	err = k_mutex_lock(&data->lock, K_NO_WAIT);
-	if (err) {
-		return err;
-	}
-
-	LOG_DBG("Setting clock");
-
-#if RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION
-	LL_PWR_EnableBkUpAccess();
-#endif /* RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION */
-
 	/* Enter Init mode inside the LL_RTC_Time and Date Init functions */
 	rtc_time.Hours = bin2bcd(timeptr->tm_hour);
 	rtc_time.Minutes = bin2bcd(timeptr->tm_min);
 	rtc_time.Seconds = bin2bcd(timeptr->tm_sec);
-	LL_RTC_TIME_Init(RTC, LL_RTC_FORMAT_BCD, &rtc_time);
 
 	/* Set Date after Time to be sure the DR is correctly updated on stm32F2 serie. */
 	rtc_date.Year = bin2bcd((real_year - RTC_YEAR_REF));
@@ -442,6 +464,16 @@ static int rtc_stm32_set_time(const struct device *dev, const struct rtc_time *t
 	/* WeekDay sunday (tm_wday = 0) is not represented by the same value in hardware,
 	 * all the other values are consistent with what is expected by hardware.
 	 */
+
+	LOG_DBG("Setting clock");
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+#if RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION
+	LL_PWR_EnableBkUpAccess();
+#endif /* RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION */
+
+	LL_RTC_TIME_Init(RTC, LL_RTC_FORMAT_BCD, &rtc_time);
 	LL_RTC_DATE_Init(RTC, LL_RTC_FORMAT_BCD, &rtc_date);
 
 #if RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION
@@ -458,8 +490,6 @@ static int rtc_stm32_set_time(const struct device *dev, const struct rtc_time *t
 	}
 #endif /* CONFIG_SOC_SERIES_STM32F2X */
 
-	k_mutex_unlock(&data->lock);
-
 	LOG_DBG("Calendar set : %d/%d/%d - %dh%dm%ds",
 			LL_RTC_DATE_GetDay(RTC),
 			LL_RTC_DATE_GetMonth(RTC),
@@ -469,7 +499,9 @@ static int rtc_stm32_set_time(const struct device *dev, const struct rtc_time *t
 			LL_RTC_TIME_GetSecond(RTC)
 	);
 
-	return err;
+	k_spin_unlock(&data->lock, key);
+
+	return 0;
 }
 
 static int rtc_stm32_get_time(const struct device *dev, struct rtc_time *timeptr)
@@ -488,18 +520,14 @@ static int rtc_stm32_get_time(const struct device *dev, struct rtc_time *timeptr
 		return -EINVAL;
 	}
 
-	int err = k_mutex_lock(&data->lock, K_NO_WAIT);
-
-	if (err) {
-		return err;
-	}
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
 
 	if (!LL_RTC_IsActiveFlag_INITS(RTC)) {
 		/* INITS flag is set when the calendar has been initialiazed. This flag is
 		 * reset only on backup domain reset, so it can be read after a system
 		 * reset to check if the calendar has been initialized.
 		 */
-		k_mutex_unlock(&data->lock);
+		k_spin_unlock(&data->lock, key);
 		return -ENODATA;
 	}
 
@@ -519,7 +547,7 @@ static int rtc_stm32_get_time(const struct device *dev, struct rtc_time *timeptr
 		} while (rtc_time != LL_RTC_TIME_Get(RTC));
 	} while (rtc_date != LL_RTC_DATE_Get(RTC));
 
-	k_mutex_unlock(&data->lock);
+	k_spin_unlock(&data->lock, key);
 
 	/* tm_year is the value since 1900 and Rtc year is from 2000 */
 	timeptr->tm_year = bcd2bin(__LL_RTC_GET_YEAR(rtc_date)) + (RTC_YEAR_REF - TM_YEAR_REF);
@@ -564,7 +592,7 @@ static int rtc_stm32_get_time(const struct device *dev, struct rtc_time *timeptr
 	return 0;
 }
 
-#ifdef CONFIG_RTC_ALARM
+#ifdef STM32_RTC_ALARM_ENABLED
 static void rtc_stm32_init_ll_alrm_struct(LL_RTC_AlarmTypeDef *p_rtc_alarm,
 					const struct rtc_time *timeptr, uint16_t mask)
 {
@@ -721,7 +749,7 @@ static int rtc_stm32_alarm_get_time(const struct device *dev, uint16_t id, uint1
 		return -EINVAL;
 	}
 
-	k_mutex_lock(&data->lock, K_FOREVER);
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
 
 	if (id == RTC_STM32_ALRM_A) {
 		p_rtc_alrm = &(data->rtc_alrm_a);
@@ -749,7 +777,7 @@ static int rtc_stm32_alarm_get_time(const struct device *dev, uint16_t id, uint1
 		timeptr->tm_min, timeptr->tm_sec, *mask);
 
 unlock:
-	k_mutex_unlock(&data->lock);
+	k_spin_unlock(&data->lock, key);
 
 	return err;
 }
@@ -763,7 +791,7 @@ static int rtc_stm32_alarm_set_time(const struct device *dev, uint16_t id, uint1
 	LL_RTC_TimeTypeDef *p_ll_rtc_alrm_time;
 	int err = 0;
 
-	k_mutex_lock(&data->lock, K_FOREVER);
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
 
 	if (id == RTC_STM32_ALRM_A) {
 		p_rtc_alrm = &(data->rtc_alrm_a);
@@ -882,7 +910,7 @@ static int rtc_stm32_alarm_set_time(const struct device *dev, uint16_t id, uint1
 #endif /* RTC_STM32_BACKUP_DOMAIN_WRITE_PROTECTION */
 
 unlock:
-	k_mutex_unlock(&data->lock);
+	k_spin_unlock(&data->lock, key);
 
 	if (id == RTC_STM32_ALRM_A) {
 		LOG_DBG("Alarm A : %dh%dm%ds   mask = 0x%x",
@@ -910,7 +938,7 @@ static int rtc_stm32_alarm_set_callback(const struct device *dev, uint16_t id,
 	struct rtc_stm32_alrm *p_rtc_alrm;
 	int err = 0;
 
-	k_mutex_lock(&data->lock, K_FOREVER);
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
 
 	if (id == RTC_STM32_ALRM_A) {
 		p_rtc_alrm = &(data->rtc_alrm_a);
@@ -927,7 +955,7 @@ static int rtc_stm32_alarm_set_callback(const struct device *dev, uint16_t id,
 	p_rtc_alrm->user_data = user_data;
 
 unlock:
-	k_mutex_unlock(&data->lock);
+	k_spin_unlock(&data->lock, key);
 
 	return err;
 }
@@ -938,7 +966,7 @@ static int rtc_stm32_alarm_is_pending(const struct device *dev, uint16_t id)
 	struct rtc_stm32_alrm *p_rtc_alrm;
 	int ret = 0;
 
-	k_mutex_lock(&data->lock, K_FOREVER);
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
 
 	if (id == RTC_STM32_ALRM_A) {
 		p_rtc_alrm = &(data->rtc_alrm_a);
@@ -956,10 +984,10 @@ static int rtc_stm32_alarm_is_pending(const struct device *dev, uint16_t id)
 	__enable_irq();
 
 unlock:
-	k_mutex_unlock(&data->lock);
+	k_spin_unlock(&data->lock, key);
 	return ret;
 }
-#endif /* CONFIG_RTC_ALARM */
+#endif /* STM32_RTC_ALARM_ENABLED */
 
 #ifdef CONFIG_RTC_CALIBRATION
 #if !defined(CONFIG_SOC_SERIES_STM32F2X) && \
@@ -1042,13 +1070,13 @@ static int rtc_stm32_get_calibration(const struct device *dev, int32_t *calibrat
 static DEVICE_API(rtc, rtc_stm32_driver_api) = {
 	.set_time = rtc_stm32_set_time,
 	.get_time = rtc_stm32_get_time,
-#ifdef CONFIG_RTC_ALARM
+#ifdef STM32_RTC_ALARM_ENABLED
 	.alarm_get_supported_fields = rtc_stm32_alarm_get_supported_fields,
 	.alarm_set_time = rtc_stm32_alarm_set_time,
 	.alarm_get_time = rtc_stm32_alarm_get_time,
 	.alarm_set_callback = rtc_stm32_alarm_set_callback,
 	.alarm_is_pending = rtc_stm32_alarm_is_pending,
-#endif /* CONFIG_RTC_ALARM */
+#endif /* STM32_RTC_ALARM_ENABLED */
 #ifdef CONFIG_RTC_CALIBRATION
 #if !defined(CONFIG_SOC_SERIES_STM32F2X) && \
 	!(defined(CONFIG_SOC_SERIES_STM32L1X) && !defined(RTC_SMOOTHCALIB_SUPPORT))
diff --git a/drivers/rtc/rtc_ll_stm32.h b/drivers/rtc/rtc_ll_stm32.h
index 16f381081c1..5199724edd8 100644
--- a/drivers/rtc/rtc_ll_stm32.h
+++ b/drivers/rtc/rtc_ll_stm32.h
@@ -7,7 +7,23 @@
 #ifndef ZEPHYR_DRIVERS_RTC_RTC_LL_STM32_H_
 #define ZEPHYR_DRIVERS_RTC_RTC_LL_STM32_H_
 
-#ifdef CONFIG_RTC_ALARM
+/**
+ * ES0584 / ES0631 §2.5.2; ES0632 §2.6.2 (both Rev. 2)
+ * """
+ * RTC interrupts cannot be reliably used for real-time
+ * control functions, since some occurences of RTC
+ * interrupts may be missed.
+ * """
+ * Since alarm IRQs are unreliable, don't allow RTC alarm
+ * to be used on STM32WB0 series. For this, we have to
+ * create a #define only valid when both the Kconfig is
+ * enabled, and we're on a supported series. This must
+ * be done because the RTC driver has to build properly
+ * on all targets regardless of which Kconfig options have
+ * been enabled.
+ */
+#if defined(CONFIG_RTC_ALARM) && !defined(CONFIG_SOC_SERIES_STM32WB0X)
+#define STM32_RTC_ALARM_ENABLED	1
 
 /* STM32 RTC alarms, A & B, LL masks are equal */
 #define RTC_STM32_ALRM_MASK_ALL		LL_RTC_ALMA_MASK_ALL
@@ -44,6 +60,6 @@ static inline void ll_func_exti_clear_rtc_alarm_flag(uint32_t exti_line)
 	LL_EXTI_ClearFlag_0_31(exti_line);
 #endif /* CONFIG_SOC_SERIES_STM32H7X and CONFIG_CPU_CORTEX_M4 */
 }
-#endif /* CONFIG_RTC_ALARM */
+#endif /* CONFIG_RTC_ALARM && !CONFIG_SOC_SERIES_STM32WB0X */
 
 #endif	/* ZEPHYR_DRIVERS_RTC_RTC_LL_STM32_H_ */
diff --git a/drivers/rtc/rtc_pcf2123.c b/drivers/rtc/rtc_pcf2123.c
new file mode 100644
index 00000000000..7d69d674485
--- /dev/null
+++ b/drivers/rtc/rtc_pcf2123.c
@@ -0,0 +1,669 @@
+/**
+ * Copyright (c) 2025 Lukas Gunnarsson <lukasgunnarsson@protonmail.com>
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Supported features:
+ * - Base RTC functionality (set/get time)
+ * - Alarm interrupts
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/drivers/rtc.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/util.h>
+
+#include "rtc_utils.h"
+
+#define DT_DRV_COMPAT nxp_pcf2123
+
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int1_gpios) &&                                                \
+	(defined(CONFIG_RTC_ALARM) || defined(CONFIG_RTC_UPDATE))
+#define PCF2123_INT1_GPIOS_IN_USE 1
+#endif
+
+LOG_MODULE_REGISTER(pcf2123, CONFIG_RTC_LOG_LEVEL);
+
+/**
+ * Datasheet: https://www.nxp.com/docs/en/data-sheet/PCF2123.pdf
+ */
+
+/* Control registers. */
+#define PCF2123_REG_CTRL_1        0x00
+#define PCF2123_REG_CTRL_2        0x01
+/* Time and date registers. */
+#define PCF2123_REG_SECONDS       0x02
+#define PCF2123_REG_MINUTES       0x03
+#define PCF2123_REG_HOURS         0x04
+#define PCF2123_REG_DAYS          0x05
+#define PCF2123_REG_WEEKDAYS      0x06
+#define PCF2123_REG_MONTHS        0x07
+#define PCF2123_REG_YEARS         0x08
+/* Alarm registers. */
+#define PCF2123_REG_ALARM_MINUTE  0x09
+#define PCF2123_REG_ALARM_HOUR    0x0A
+#define PCF2123_REG_ALARM_DAY     0x0B
+#define PCF2123_REG_ALARM_WEEKDAY 0x0C
+/* Offset register. */
+#define PCF2123_REG_OFFSET        0x0D
+/* Timer registers. */
+#define PCF2123_TIMER_CLKOUT      0x0E
+#define PCF2123_TIMER_COUNTDOWN   0x0F
+
+/**
+ * Control register 1 bits (page 9 in the datasheet).
+ * Bits 6, 3 and 0 are unused.
+ */
+#define PCF2123_CTRL_1_EXT_TEST BIT(7)
+#define PCF2123_CTRL_1_STOP     BIT(5)
+#define PCF2123_CTRL_1_SR       BIT(4)
+#define PCF2123_CTRL_1_12_24    BIT(2)
+#define PCF2123_CTRL_1_CIE      BIT(1)
+
+/**
+ * Control register 2 bits (page 11 in the datasheet).
+ */
+#define PCF2123_CTRL_2_MI    BIT(7)
+#define PCF2123_CTRL_2_SI    BIT(6)
+#define PCF2123_CTRL_2_MSF   BIT(5)
+#define PCF2123_CTRL_2_TI_TP BIT(4)
+#define PCF2123_CTRL_2_AF    BIT(3)
+#define PCF2123_CTRL_2_TF    BIT(2)
+#define PCF2123_CTRL_2_AIE   BIT(1)
+#define PCF2123_CTRL_2_TIE   BIT(0)
+
+/**
+ * Alarm register bits (page 17 in the datasheet).
+ */
+#define PCF2123_ALARM_MINUTE_AE_M  (0UL << 7)
+#define PCF2123_ALARM_HOUR_AE_H    (0UL << 7)
+#define PCF2123_ALARM_DAY_AE_D     (0UL << 7)
+#define PCF2123_ALARM_WEEKDAY_AE_W (0UL << 7)
+
+/**
+ * The masks have been gathered from the register overview (page 8 in the datasheet).
+ */
+#define PCF2123_SECONDS_MASK  GENMASK(6, 0)
+#define PCF2123_MINUTES_MASK  GENMASK(6, 0)
+#define PCF2123_HOURS_MASK    GENMASK(5, 0)
+#define PCF2123_DAYS_MASK     GENMASK(5, 0)
+#define PCF2123_WEEKDAYS_MASK GENMASK(2, 0)
+#define PCF2123_MONTHS_MASK   GENMASK(4, 0)
+#define PCF2123_YEARS_MASK    GENMASK(7, 0)
+
+#define PCF2123_RTC_TIME_MASK                                                                      \
+	(RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR |      \
+	 RTC_ALARM_TIME_MASK_MONTHDAY | RTC_ALARM_TIME_MASK_WEEKDAY | RTC_ALARM_TIME_MASK_MONTH |  \
+	 RTC_ALARM_TIME_MASK_YEAR)
+
+#define PCF2123_RTC_ALARM_TIME_MASK                                                                \
+	(RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR | RTC_ALARM_TIME_MASK_MONTHDAY |    \
+	 RTC_ALARM_TIME_MASK_WEEKDAY)
+
+/* The PCF2123 supports two-digit years (0-99). */
+#define PCF2123_YEARS_OFFSET  (2000 - 1900)
+#define PCF2123_MONTHS_OFFSET 1
+
+/**
+ * Command byte definition (page 36 in the datasheet).
+ *  Bit 7:   R/W (0 write, 1 read)
+ *  Bit 6-4: SA  (Subaddress, required to be 0b001)
+ *  Bit 3-0: RA  (Register address range)
+ *
+ * The PCF2123 starts from the address RA and auto-increments for every byte.
+ */
+#define PCF2123_CMD_READ  ((1U << 7) | (0b001 << 4))
+#define PCF2123_CMD_WRITE ((0U << 7) | (0b001 << 4))
+
+#ifdef PCF2123_INT1_GPIOS_IN_USE
+void callback_work_handler(struct k_work *work);
+K_WORK_DEFINE(callback_work, callback_work_handler);
+
+static void gpio_int1_callback(const struct device *dev, struct gpio_callback *cb, uint32_t pins);
+#endif
+
+struct pcf2123_config {
+	const struct spi_dt_spec spi;
+#ifdef PCF2123_INT1_GPIOS_IN_USE
+	struct gpio_dt_spec int1;
+#endif
+};
+
+struct pcf2123_data {
+#ifdef PCF2123_INT1_GPIOS_IN_USE
+	const struct device *dev;
+	rtc_alarm_callback alarm_callback;
+	void *alarm_user_data;
+	struct gpio_callback int1_callback;
+	struct k_work callback_work;
+#endif
+};
+
+/**
+ * @brief Read from a single or multiple PCF2123 registers.
+ *
+ * @param dev The RTC device.
+ * @param start_addr The first memory address to start reading from.
+ * @param buf Buffer to store read data.
+ * @param len Number of bytes to read.
+ * @retval 0 on success, else -ERRNO.
+ *
+ * @note The PCF2123 auto-increments the selected memory address for every byte sent.
+ */
+static int pcf2123_reg_read(const struct device *dev, const uint8_t start_addr, uint8_t *buf,
+			    const size_t len)
+{
+	if (!buf) {
+		return -EINVAL;
+	}
+	if (len <= 0) {
+		return -EINVAL;
+	}
+
+	const struct pcf2123_config *config = dev->config;
+	int ret;
+
+	uint8_t cmd_byte = PCF2123_CMD_READ | start_addr;
+	struct spi_buf tx_buf = {.buf = &cmd_byte, .len = sizeof(cmd_byte)};
+	const struct spi_buf_set tx_bufs = {.buffers = &tx_buf, .count = 1};
+
+	uint8_t rx_dummy; /* Dummy byte. */
+	struct spi_buf rx_buf[2] = {{.buf = &rx_dummy, .len = 1}, {.buf = buf, .len = len}};
+	const struct spi_buf_set rx_bufs = {.buffers = rx_buf, .count = 2};
+
+	ret = spi_transceive_dt(&config->spi, &tx_bufs, &rx_bufs);
+	if (ret < 0) {
+		LOG_ERR("Failed to read from register with start address %d (err %d)", start_addr,
+			ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Write to a single or multiple PCF2123 registers.
+ *
+ * @param dev The RTC device.
+ * @param start_addr The first memory address to start writing towards.
+ * @param buf Data to write.
+ * @param len Data size in bytes.
+ * @retval 0 on success, else -ERRNO.
+ *
+ * @note The PCF2123 auto-increments the selected memory address for every byte sent.
+ */
+static int pcf2123_reg_write(const struct device *dev, const uint8_t start_addr, uint8_t *buf,
+			     const size_t len)
+{
+	if (!buf) {
+		return -EINVAL;
+	}
+	if (len <= 0) {
+		return -EINVAL;
+	}
+
+	const struct pcf2123_config *config = dev->config;
+	int ret;
+
+	uint8_t cmd_byte = PCF2123_CMD_WRITE | start_addr;
+	struct spi_buf cmd_buf = {.buf = &cmd_byte, .len = sizeof(cmd_byte)};
+	struct spi_buf data_buf = {.buf = buf, .len = len};
+	struct spi_buf tx_buf[] = {cmd_buf, data_buf};
+	const struct spi_buf_set tx_bufs = {.buffers = tx_buf, .count = 2};
+
+	ret = spi_write_dt(&config->spi, &tx_bufs);
+	if (ret < 0) {
+		LOG_ERR("Failed to set RTC time (err %d)", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int pcf2123_set_time(const struct device *dev, const struct rtc_time *timeptr)
+{
+	LOG_DBG("Set time: year=%d mon=%d mday=%d wday=%d hour=%d min=%d sec=%d", timeptr->tm_year,
+		timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday, timeptr->tm_hour,
+		timeptr->tm_min, timeptr->tm_sec);
+
+	if (!rtc_utils_validate_rtc_time(timeptr, PCF2123_RTC_TIME_MASK)) {
+		LOG_ERR("RTC time validation failed");
+		return -EINVAL;
+	}
+
+	if ((timeptr->tm_year < PCF2123_YEARS_OFFSET) ||
+	    (timeptr->tm_year > PCF2123_YEARS_OFFSET + 99)) {
+		LOG_ERR("Invalid tm_year value: %d", timeptr->tm_year);
+		return -EINVAL;
+	}
+
+	/* There are 7 time registers ranging from 02h-08h. */
+	uint8_t regs[7];
+
+	/* Set seconds. */
+	regs[0] = bin2bcd(timeptr->tm_sec) & PCF2123_SECONDS_MASK;
+
+	/* Set minutes. */
+	regs[1] = bin2bcd(timeptr->tm_min) & PCF2123_MINUTES_MASK;
+
+	/* Set hours. */
+	regs[2] = bin2bcd(timeptr->tm_hour) & PCF2123_HOURS_MASK;
+
+	/* Set days. */
+	regs[3] = bin2bcd(timeptr->tm_mday) & PCF2123_DAYS_MASK;
+
+	/* Set weekdays. The values are not BCD encoded. */
+	regs[4] = timeptr->tm_wday;
+
+	/* Set month. */
+	regs[5] = bin2bcd(timeptr->tm_mon + PCF2123_MONTHS_OFFSET) & PCF2123_MONTHS_MASK;
+
+	/* Set year. */
+	regs[6] = bin2bcd(timeptr->tm_year - PCF2123_YEARS_OFFSET) & PCF2123_YEARS_MASK;
+
+	pcf2123_reg_write(dev, PCF2123_REG_SECONDS, regs, sizeof(regs));
+
+	return 0;
+}
+
+static int pcf2123_get_time(const struct device *dev, struct rtc_time *timeptr)
+{
+	uint8_t regs[7];
+	int ret;
+
+	ret = pcf2123_reg_read(dev, PCF2123_REG_SECONDS, regs, sizeof(regs));
+	if (ret < 0) {
+		return -ENODATA;
+	}
+
+	/**
+	 * Validate clock integrity.
+	 * The seconds register use bit 7 for checking integrity (page 12 in the datasheet).
+	 */
+	if (bcd2bin(regs[0]) & BIT(7)) {
+		LOG_WRN("Clock integrity failed");
+		LOG_HEXDUMP_DBG(regs, sizeof(regs), "Read data");
+		return -ENODATA;
+	}
+
+	/* Nanoseconds, unused. */
+	timeptr->tm_nsec = 0;
+
+	/* Seconds. */
+	timeptr->tm_sec = bcd2bin(regs[0] & PCF2123_SECONDS_MASK);
+
+	/* Minutes. */
+	timeptr->tm_min = bcd2bin(regs[1] & PCF2123_MINUTES_MASK);
+
+	/* Hours. */
+	timeptr->tm_hour = bcd2bin(regs[2] & PCF2123_HOURS_MASK);
+
+	/* Days. */
+	timeptr->tm_mday = bcd2bin(regs[3] & PCF2123_DAYS_MASK);
+
+	/* Weekdays. */
+	timeptr->tm_wday = bcd2bin(regs[4] & PCF2123_WEEKDAYS_MASK);
+
+	/* Year days, unused. */
+	timeptr->tm_yday = -1;
+
+	/**
+	 * Months range from 1-12 (table 5, page 8 in the datasheet).
+	 * The struct rtc_time expects months in the 0-11 range therefore
+	 * we need to offset the month by 1.
+	 */
+	timeptr->tm_mon = bcd2bin(regs[5] & PCF2123_MONTHS_MASK) - PCF2123_MONTHS_OFFSET;
+
+	/* Years range from 0-99 (table 5, page 8 in the datasheet). */
+	timeptr->tm_year = bcd2bin(regs[6] & PCF2123_YEARS_MASK) + PCF2123_YEARS_OFFSET;
+
+	timeptr->tm_isdst = -1; /* Unused. */
+
+	LOG_DBG("Get time: year=%d mon=%d mday=%d wday=%d hour=%d min=%d sec=%d", timeptr->tm_year,
+		timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday, timeptr->tm_hour,
+		timeptr->tm_min, timeptr->tm_sec);
+
+	return 0;
+}
+
+#ifdef CONFIG_RTC_ALARM
+static int pcf2123_clear_alarm_flag(const struct device *dev)
+{
+	/* Clearing of the alarm flag can be found in page 19 in the datasheet. */
+	uint8_t ctrl2;
+	int ret;
+
+	ret = pcf2123_reg_read(dev, PCF2123_REG_CTRL_2, &ctrl2, 1);
+	if (ret < 0) {
+		LOG_ERR("Failed to read from control register 2 to clear AF bit (err %d)", ret);
+		return ret;
+	}
+
+	/* Clear the AF bit. */
+	ctrl2 &= ~PCF2123_CTRL_2_AF;
+	ret = pcf2123_reg_write(dev, PCF2123_REG_CTRL_2, &ctrl2, 1);
+	if (ret < 0) {
+		LOG_ERR("Failed write to control register 2 to clear the AF bit (err %d)", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int pcf2123_alarm_get_supported_fields(const struct device *dev, uint16_t id, uint16_t *mask)
+{
+	ARG_UNUSED(dev);
+
+	if (id != 0U) {
+		LOG_ERR("Invalid ID: %d", id);
+		return -EINVAL;
+	}
+
+	*mask = PCF2123_RTC_ALARM_TIME_MASK;
+
+	return 0;
+}
+
+static int pcf2123_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
+				  const struct rtc_time *timeptr)
+{
+	if (id != 0) {
+		LOG_ERR("Invalid ID: %d", id);
+		return -EINVAL;
+	}
+
+	if ((mask & ~(PCF2123_RTC_ALARM_TIME_MASK)) != 0) {
+		LOG_ERR("Invalid alarm mask: 0x%04X", mask);
+		return -EINVAL;
+	}
+
+	if (!rtc_utils_validate_rtc_time(timeptr, mask)) {
+		LOG_ERR("Failed to validate the RTC time");
+		return -EINVAL;
+	}
+
+	uint8_t regs[4];
+	int ret;
+
+	/* The alarms are disabled if bit 7 is 1 (page 17 in the datasheet). */
+
+	/* Alarm register: MINUTE */
+	if ((mask & RTC_ALARM_TIME_MASK_MINUTE) != 0) {
+		regs[0] = bin2bcd(timeptr->tm_min) & PCF2123_MINUTES_MASK;
+	} else {
+		regs[0] = BIT(7);
+	}
+
+	/* Alarm register: HOUR */
+	if ((mask & RTC_ALARM_TIME_MASK_HOUR) != 0) {
+		regs[1] = bin2bcd(timeptr->tm_hour) & PCF2123_HOURS_MASK;
+	} else {
+		regs[1] = BIT(7);
+	}
+
+	/* Alarm register: DAY */
+	if ((mask & RTC_ALARM_TIME_MASK_MONTHDAY) != 0) {
+		regs[2] = bin2bcd(timeptr->tm_mday) & PCF2123_DAYS_MASK;
+	} else {
+		regs[2] = BIT(7);
+	}
+
+	/* Alarm register: WEEKDAY */
+	if ((mask & RTC_ALARM_TIME_MASK_WEEKDAY) != 0) {
+		regs[3] = bin2bcd(timeptr->tm_wday) & PCF2123_WEEKDAYS_MASK;
+	} else {
+		regs[3] = BIT(7);
+	}
+
+	/* Clear the alarm flag. */
+	ret = pcf2123_clear_alarm_flag(dev);
+	if (ret < 0) {
+		LOG_ERR("Failed to clear alarm flag (err %d)", ret);
+		return -ENOMSG;
+	}
+
+	ret = pcf2123_reg_write(dev, PCF2123_REG_ALARM_MINUTE, regs, sizeof(regs));
+	if (ret) {
+		LOG_ERR("Failed to write to alarm registers (err %d)", ret);
+		return -ENOMSG;
+	}
+
+	/* Make sure interrupts are enabled. */
+	uint8_t ctrl2;
+
+	ret = pcf2123_reg_read(dev, PCF2123_REG_CTRL_2, &ctrl2, 1);
+	if (ret < 0) {
+		LOG_ERR("Failed to read from control register 2 (err %d)", ret);
+		return ret;
+	}
+
+	if ((ctrl2 & PCF2123_CTRL_2_AIE) == 0) {
+		ctrl2 |= PCF2123_CTRL_2_AIE;
+		ret = pcf2123_reg_write(dev, PCF2123_REG_CTRL_2, &ctrl2, 1);
+		if (ret < 0) {
+			LOG_ERR("Failed to enable interrupts in control register 2 (err %d)", ret);
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int pcf2123_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
+				  struct rtc_time *timeptr)
+{
+	uint8_t regs[4];
+	int ret;
+
+	ret = pcf2123_reg_read(dev, PCF2123_REG_ALARM_MINUTE, regs, sizeof(regs));
+	if (ret < 0) {
+		LOG_ERR("Failed to read alarm registers (err %d)", ret);
+		return ret;
+	}
+
+	*mask = 0;
+
+	/* Alarm register: MINUTE */
+	if ((regs[0] & BIT(7)) == 0) {
+		*mask |= RTC_ALARM_TIME_MASK_MINUTE;
+		timeptr->tm_min = bcd2bin(regs[0] & PCF2123_MINUTES_MASK);
+	} else {
+		timeptr->tm_min = 0;
+	}
+
+	/* Alarm register: HOUR */
+	if ((regs[1] & BIT(7)) == 0) {
+		*mask |= RTC_ALARM_TIME_MASK_HOUR;
+		timeptr->tm_hour = bcd2bin(regs[1] & PCF2123_HOURS_MASK);
+	} else {
+		timeptr->tm_hour = 0;
+	}
+
+	/* Alarm register: DAY */
+	if ((regs[2] & BIT(7)) == 0) {
+		*mask |= RTC_ALARM_TIME_MASK_MONTHDAY;
+		timeptr->tm_mday = bcd2bin(regs[2] & PCF2123_DAYS_MASK);
+	} else {
+		timeptr->tm_mday = 1;
+	}
+
+	/* Alarm register: WEEKDAY */
+	if ((regs[3] & BIT(7)) == 0) {
+		*mask |= RTC_ALARM_TIME_MASK_WEEKDAY;
+		timeptr->tm_wday = bcd2bin(regs[3] & PCF2123_WEEKDAYS_MASK);
+	} else {
+		timeptr->tm_wday = -1;
+	}
+
+	return 0;
+}
+
+static int pcf2123_alarm_is_pending(const struct device *dev, uint16_t id)
+{
+	int ret;
+	uint8_t ctrl2;
+
+	if (id != 0) {
+		LOG_ERR("Invalid ID: %d", id);
+		return -EINVAL;
+	}
+
+	ret = pcf2123_reg_read(dev, PCF2123_REG_CTRL_2, &ctrl2, 1);
+	if (ret < 0) {
+		LOG_ERR("Failed to read from control register 2 (err %d)", ret);
+		return ret;
+	}
+
+	/* Clear the alarm flag. */
+	if (ctrl2 & PCF2123_CTRL_2_AF) {
+		ret = pcf2123_clear_alarm_flag(dev);
+		if (ret < 0) {
+			LOG_ERR("Failed to clear alarm flag (err %d)", ret);
+			return -ENOMSG;
+		}
+
+		return 1;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_RTC_ALARM */
+
+static int pcf2123_alarm_set_callback(const struct device *dev, uint16_t id,
+				      rtc_alarm_callback callback, void *user_data)
+{
+#ifndef PCF2123_INT1_GPIOS_IN_USE
+	ARG_UNUSED(dev);
+	ARG_UNUSED(id);
+	ARG_UNUSED(callback);
+	ARG_UNUSED(user_data);
+
+	return -ENOTSUP;
+#else
+	const struct pcf2123_config *config = dev->config;
+	struct pcf2123_data *data = dev->data;
+	int ret;
+
+	if (config->int1.port == NULL) {
+		LOG_ERR("The int1 port is NULL");
+		return -ENOTSUP;
+	}
+
+	if (id != 0U) {
+		LOG_ERR("Invalid ID %d", id);
+		return -EINVAL;
+	}
+
+	data->dev = dev;
+	data->alarm_callback = callback;
+	data->alarm_user_data = user_data;
+
+	ret = gpio_pin_configure_dt(&config->int1, GPIO_INPUT | GPIO_PULL_UP);
+	if (ret < 0) {
+		LOG_ERR("Failed to configure int1 (err %d)", ret);
+		return ret;
+	}
+
+	ret = gpio_pin_interrupt_configure_dt(&config->int1, GPIO_INT_EDGE_FALLING);
+	if (ret < 0) {
+		LOG_ERR("Failed to configure edge on int1 (err %d)", ret);
+		return ret;
+	}
+
+	gpio_init_callback(&data->int1_callback, gpio_int1_callback, BIT(config->int1.pin));
+	ret = gpio_add_callback(config->int1.port, &data->int1_callback);
+	if (ret < 0) {
+		LOG_ERR("Failed to add callback to int1 (err %d)", ret);
+		return ret;
+	}
+
+	return 0;
+#endif
+}
+
+#ifdef PCF2123_INT1_GPIOS_IN_USE
+static void gpio_int1_callback(const struct device *dev, struct gpio_callback *cb, uint32_t pins)
+{
+	struct pcf2123_data *data = CONTAINER_OF(cb, struct pcf2123_data, int1_callback);
+
+	LOG_DBG("PCF2123 interrupt detected");
+	k_work_submit(&(data->callback_work));
+}
+
+void callback_work_handler(struct k_work *work)
+{
+	struct pcf2123_data *data = CONTAINER_OF(work, struct pcf2123_data, callback_work);
+
+	if (data->alarm_callback) {
+		data->alarm_callback(data->dev, 0, data->alarm_user_data);
+	} else {
+		LOG_WRN("Missing PCF2123 alarm callback");
+	}
+}
+#endif /* PCF2123_INT1_GPIOS_IN_USE */
+
+static DEVICE_API(rtc, pcf2123_driver_api) = {
+	.set_time = pcf2123_set_time,
+	.get_time = pcf2123_get_time,
+#ifdef CONFIG_RTC_ALARM
+	.alarm_get_supported_fields = pcf2123_alarm_get_supported_fields,
+	.alarm_set_time = pcf2123_alarm_set_time,
+	.alarm_get_time = pcf2123_alarm_get_time,
+	.alarm_is_pending = pcf2123_alarm_is_pending,
+	.alarm_set_callback = pcf2123_alarm_set_callback,
+#endif
+};
+
+int pcf2123_init(const struct device *dev)
+{
+	const struct pcf2123_config *config = dev->config;
+	int ret;
+	uint8_t dummy_check;
+
+#ifdef PCF2123_INT1_GPIOS_IN_USE
+	struct pcf2123_data *data = dev->data;
+
+	data->callback_work = callback_work;
+#endif
+
+	if (!device_is_ready(config->spi.bus)) {
+		LOG_ERR("SPI device not ready: %s", config->spi.bus->name);
+		return -ENODEV;
+	}
+
+	/* Determine if the SPI device is alive by attempting to read from control register 1. */
+	ret = pcf2123_reg_read(dev, PCF2123_REG_CTRL_1, &dummy_check, 1);
+	if (ret < 0) {
+		LOG_ERR("Failed to communicate with PCF2123 (err %d)", ret);
+		return -ENODEV;
+	}
+
+#ifdef PCF2123_INT1_GPIOS_IN_USE
+	uint8_t ctrl2 = PCF2123_CTRL_2_AIE; /* Enable alarm interrupts (AIE). */
+
+	ret = pcf2123_reg_write(dev, PCF2123_REG_CTRL_2, &ctrl2, 1);
+	if (ret < 0) {
+		LOG_ERR("Failed to write to control register 2 during initialization");
+		return -ENODEV;
+	}
+#endif
+
+	LOG_DBG("%s initialized", dev->name);
+
+	return 0;
+}
+
+#define PCF2123_INIT(inst)                                                                         \
+	static const struct pcf2123_config pcf2123_config_##inst = {                               \
+		.spi = SPI_DT_SPEC_INST_GET(inst, SPI_WORD_SET(8) | SPI_TRANSFER_MSB, 0U),         \
+		IF_ENABLED(PCF2123_INT1_GPIOS_IN_USE,\
+			(.int1 = GPIO_DT_SPEC_INST_GET_OR(inst, int1_gpios, {0})) \
+		)};                \
+                                                                                                   \
+	static struct pcf2123_data pcf2123_data_##inst;                                            \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(inst, &pcf2123_init, NULL, &pcf2123_data_##inst,                     \
+			      &pcf2123_config_##inst, POST_KERNEL, CONFIG_RTC_INIT_PRIORITY,       \
+			      &pcf2123_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(PCF2123_INIT)
diff --git a/drivers/rtc/rtc_pcf8563.c b/drivers/rtc/rtc_pcf8563.c
index a994f133361..acf2822da4c 100644
--- a/drivers/rtc/rtc_pcf8563.c
+++ b/drivers/rtc/rtc_pcf8563.c
@@ -103,7 +103,7 @@ struct pcf8563_data {
  * the datasheet because they may contain unexpected values. Applying a mask will help us
  * to sanitize the read values
  */
-int pcf8563_set_time(const struct device *dev, const struct rtc_time *timeptr)
+static int pcf8563_set_time(const struct device *dev, const struct rtc_time *timeptr)
 {
 	const struct pcf8563_config *config = dev->config;
 	int ret;
@@ -146,7 +146,7 @@ int pcf8563_set_time(const struct device *dev, const struct rtc_time *timeptr)
 	return 0;
 }
 
-int pcf8563_get_time(const struct device *dev, struct rtc_time *timeptr)
+static int pcf8563_get_time(const struct device *dev, struct rtc_time *timeptr)
 {
 	const struct pcf8563_config *config = dev->config;
 	int ret;
@@ -198,7 +198,34 @@ int pcf8563_get_time(const struct device *dev, struct rtc_time *timeptr)
 	return 0;
 }
 
+#ifdef PCF8563_INT1_GPIOS_IN_USE
+
+/* The logic related to the pin interrupt logic */
+static void callback_work_handler(struct k_work *work)
+{
+	/* This function is run as a work so the user can spend here all the necessary time */
+	struct pcf8563_data *data = CONTAINER_OF(work, struct pcf8563_data, callback_work);
+
+	if (data->alarm_callback == NULL) {
+		LOG_WRN("No PCF8563 alarm callback function provided");
+	} else {
+		data->alarm_callback(data->dev, 0, data->alarm_user_data);
+	}
+}
+
+/* The function called when the clock alarm activates the interrupt*/
+static void gpio_callback_function(const struct device *dev, struct gpio_callback *cb,
+		    uint32_t pins)
+{
+	struct pcf8563_data *data = CONTAINER_OF(cb, struct pcf8563_data, int1_callback);
+
+	LOG_DBG("PCF8563 interrupt detected");
+	/* By using a work we are able to run "heavier" code */
+	k_work_submit(&(data->callback_work));
+
+}
 
+#endif /* PCF8563_INT1_GPIOS_IN_USE */
 
 #ifdef CONFIG_RTC_ALARM
 
@@ -366,37 +393,6 @@ static int pcf8563_alarm_is_pending(const struct device *dev, uint16_t id)
 	/* No alarms */
 	return 0;
 }
-#endif
-
-#ifdef PCF8563_INT1_GPIOS_IN_USE
-/* The logic related to the pin interrupt logic */
-
-void callback_work_handler(struct k_work *work)
-{
-	/* This function is run as a work so the user can spend here all the necessary time */
-	struct pcf8563_data *data = CONTAINER_OF(work, struct pcf8563_data, callback_work);
-
-	if (data->alarm_callback == NULL) {
-		LOG_WRN("No PCF8563 alarm callback function provided");
-	} else {
-		data->alarm_callback(data->dev, 0, data->alarm_user_data);
-	}
-}
-
-
-/* The function called when the clock alarm activates the interrupt*/
-void gpio_callback_function(const struct device *dev, struct gpio_callback *cb,
-		    uint32_t pins)
-{
-	struct pcf8563_data *data = CONTAINER_OF(cb, struct pcf8563_data, int1_callback);
-
-	LOG_DBG("PCF8563 interrupt detected");
-	/* By using a work we are able to run "heavier" code */
-	k_work_submit(&(data->callback_work));
-
-}
-
-#endif
 
 static int pcf8563_alarm_set_callback(const struct device *dev, uint16_t id,
 				      rtc_alarm_callback callback, void *user_data)
@@ -408,7 +404,7 @@ static int pcf8563_alarm_set_callback(const struct device *dev, uint16_t id,
 	ARG_UNUSED(user_data);
 
 	return -ENOTSUP;
-#else
+#else /* PCF8563_INT1_GPIOS_IN_USE */
 	const struct pcf8563_config *config = dev->config;
 	struct pcf8563_data *data = dev->data;
 	int ret;
@@ -446,9 +442,11 @@ static int pcf8563_alarm_set_callback(const struct device *dev, uint16_t id,
 	gpio_add_callback(config->int1.port, &data->int1_callback);
 	LOG_DBG("Alarm set");
 	return 0;
-#endif
+#endif /* PCF8563_INT1_GPIOS_IN_USE */
 }
 
+#endif /* CONFIG_RTC_ALARM */
+
 static DEVICE_API(rtc, pcf8563_driver_api) = {
 	.set_time = pcf8563_set_time,
 	.get_time = pcf8563_get_time,
@@ -462,7 +460,7 @@ static DEVICE_API(rtc, pcf8563_driver_api) = {
 };
 
 
-int pcf8563_init(const struct device *dev)
+static int pcf8563_init(const struct device *dev)
 {
 	const struct pcf8563_config *config = dev->config;
 	int ret;
diff --git a/drivers/rtc/rtc_rts5912.c b/drivers/rtc/rtc_rts5912.c
new file mode 100644
index 00000000000..6dba0a2ab2c
--- /dev/null
+++ b/drivers/rtc/rtc_rts5912.c
@@ -0,0 +1,158 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 Realtek Semiconductor Corporation, SIBG-SD7
+ * Author: Chia-Yang Lin <cylin0708@realtek.com>
+ */
+
+#define DT_DRV_COMPAT realtek_rts5912_rtc
+
+#include <soc.h>
+#include <errno.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/rtc.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/clock_control_rts5912.h>
+#include "rtc_utils.h"
+
+#include "reg/reg_system.h"
+#include "reg/reg_rtc.h"
+
+LOG_MODULE_REGISTER(rtc_rts5912, CONFIG_RTC_LOG_LEVEL);
+
+#define RTS5912_RTC_TIME_MASK                                                                      \
+	(RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR |      \
+	 RTC_ALARM_TIME_MASK_WEEKDAY | RTC_ALARM_TIME_MASK_MONTHDAY | RTC_ALARM_TIME_MASK_MONTH |  \
+	 RTC_ALARM_TIME_MASK_YEAR)
+
+#define RTS5912_RTC_DIVCTL_NORMAL_OPERATION BIT(1)
+
+#define RTS5912_RTC_DAYWEEK_OFFSET 1
+#define RTS5912_RTC_MONTH_OFFSET   1
+#define RTS5912_RTC_YEAR_OFFSET    100
+
+struct rtc_rts5912_config {
+	RTC_Type *regs;
+	uint32_t rtc_base;
+	uint32_t rtc_clk_grp;
+	uint32_t rtc_clk_idx;
+	const struct device *clk_dev;
+};
+
+struct rtc_rts5912_data {
+	struct k_spinlock lock;
+};
+
+static void rtc_rts5912_reset_rtc_time(const struct device *dev)
+{
+	const struct rtc_rts5912_config *const dev_cfg = dev->config;
+	RTC_Type *rtc_regs = dev_cfg->regs;
+
+	rtc_regs->CTRL1 |= RTC_CTRL1_SETMODE_Msk;
+	rtc_regs->CTRL0 &= ~RTC_CTRL0_DIVCTL_Msk;
+	rtc_regs->CTRL0 |= (RTS5912_RTC_DIVCTL_NORMAL_OPERATION << RTC_CTRL0_DIVCTL_Pos);
+	rtc_regs->CTRL1 |= RTC_CTRL1_DATEMODE_Msk;
+	rtc_regs->CTRL1 |= RTC_CTRL1_HRMODE_Msk;
+	rtc_regs->SEC = 0;
+	rtc_regs->MIN = 0;
+	rtc_regs->HR &= ~(RTC_HR_AMPM_Msk | RTC_HR_VAL_Msk);
+	rtc_regs->DAYWEEK = BIT(0);
+	rtc_regs->DAYMONTH = BIT(0);
+	rtc_regs->MONTH = BIT(0);
+	rtc_regs->YEAR = 0;
+	rtc_regs->WEEK &= ~RTC_WEEK_NUM_Msk;
+}
+
+static int rtc_rts5912_set_time(const struct device *dev, const struct rtc_time *timeptr)
+{
+	const struct rtc_rts5912_config *const dev_cfg = dev->config;
+	RTC_Type *rtc_regs = dev_cfg->regs;
+
+	if (!rtc_utils_validate_rtc_time(timeptr, RTS5912_RTC_TIME_MASK)) {
+		rtc_rts5912_reset_rtc_time(dev);
+		k_msleep(1);
+		return -EINVAL;
+	}
+
+	rtc_regs->CTRL1 |= RTC_CTRL1_SETMODE_Msk;
+	rtc_regs->SEC = timeptr->tm_sec;
+	rtc_regs->MIN = timeptr->tm_min;
+	rtc_regs->HR = timeptr->tm_hour;
+	rtc_regs->DAYWEEK = timeptr->tm_wday + RTS5912_RTC_DAYWEEK_OFFSET;
+	rtc_regs->DAYMONTH = timeptr->tm_mday;
+	rtc_regs->MONTH = timeptr->tm_mon + RTS5912_RTC_MONTH_OFFSET;
+	rtc_regs->YEAR = timeptr->tm_year % RTS5912_RTC_YEAR_OFFSET;
+	/* Need to delay in order to update register after setting RTC time */
+	k_msleep(1);
+	rtc_regs->CTRL1 &= ~RTC_CTRL1_SETMODE_Msk;
+
+	return 0;
+}
+
+static int rtc_rts5912_get_time(const struct device *dev, struct rtc_time *timeptr)
+{
+	const struct rtc_rts5912_config *const dev_cfg = dev->config;
+	RTC_Type *rtc_regs = dev_cfg->regs;
+
+	timeptr->tm_sec = rtc_regs->SEC;
+	timeptr->tm_min = rtc_regs->MIN;
+	timeptr->tm_hour = rtc_regs->HR;
+	timeptr->tm_wday = rtc_regs->DAYWEEK - RTS5912_RTC_DAYWEEK_OFFSET;
+	timeptr->tm_mday = rtc_regs->DAYMONTH;
+	timeptr->tm_mon = rtc_regs->MONTH - RTS5912_RTC_MONTH_OFFSET;
+	timeptr->tm_year = rtc_regs->YEAR + RTS5912_RTC_YEAR_OFFSET;
+
+	/* No support for daylight saving time flag and nanoseconds in rts5912 RTC */
+	timeptr->tm_isdst = -1;
+	timeptr->tm_nsec = 0;
+
+	return 0;
+}
+
+static DEVICE_API(rtc, rtc_rts5912_driver_api) = {
+	.set_time = rtc_rts5912_set_time,
+	.get_time = rtc_rts5912_get_time,
+};
+
+static int rtc_rts5912_init(const struct device *dev)
+{
+	const struct rtc_rts5912_config *const rtc_config = dev->config;
+	struct rts5912_sccon_subsys sccon;
+
+	int rc;
+
+	if (!device_is_ready(rtc_config->clk_dev)) {
+		LOG_ERR("RTC device not ready");
+		return -ENODEV;
+	}
+
+	sccon.clk_grp = rtc_config->rtc_clk_grp;
+	sccon.clk_idx = rtc_config->rtc_clk_idx;
+	rc = clock_control_on(rtc_config->clk_dev, (clock_control_subsys_t)&sccon);
+	if (rc < 0) {
+		LOG_ERR("Failed to turn on RTC clock (%d)", rc);
+		return rc;
+	}
+
+	rtc_rts5912_reset_rtc_time(dev);
+
+	return rc;
+}
+
+#define RTC_RTS5912_CONFIG(inst)                                                                   \
+	static struct rtc_rts5912_config rtc_rts5912_config_##inst = {                             \
+		.regs = (RTC_Type *)(DT_INST_REG_ADDR(inst)),                                      \
+		.rtc_base = DT_INST_REG_ADDR(inst),                                                \
+		.rtc_clk_grp = DT_INST_CLOCKS_CELL_BY_NAME(inst, rtc, clk_grp),                    \
+		.rtc_clk_idx = DT_INST_CLOCKS_CELL_BY_NAME(inst, rtc, clk_idx),                    \
+		.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)),                               \
+	};
+
+#define RTC_RTS5912_DEVICE_INIT(index)                                                             \
+	RTC_RTS5912_CONFIG(index)                                                                  \
+	DEVICE_DT_INST_DEFINE(index, &rtc_rts5912_init, NULL, NULL, &rtc_rts5912_config_##index,   \
+			      POST_KERNEL, CONFIG_RTC_INIT_PRIORITY, &rtc_rts5912_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(RTC_RTS5912_DEVICE_INIT)
diff --git a/drivers/rtc/rtc_rv8803.c b/drivers/rtc/rtc_rv8803.c
new file mode 100644
index 00000000000..568938269e7
--- /dev/null
+++ b/drivers/rtc/rtc_rv8803.c
@@ -0,0 +1,865 @@
+/*
+ * Copyright (c) 2024 Marcin Lyda <elektromarcin@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/rtc.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/arch/common/ffs.h>
+#include "rtc_utils.h"
+
+/* Registers */
+#define RV8803_SECONDS_REG               0x00
+#define RV8803_MINUTES_REG               0x01
+#define RV8803_HOURS_REG                 0x02
+#define RV8803_WEEKDAY_REG               0x03
+#define RV8803_DATE_REG                  0x04
+#define RV8803_MONTH_REG                 0x05
+#define RV8803_YEAR_REG                  0x06
+#define RV8803_RAM_REG                   0x07
+#define RV8803_MINUTES_ALARM_REG         0x08
+#define RV8803_HOURS_ALARM_REG           0x09
+#define RV8803_WEEKDAY_OR_DATE_ALARM_REG 0x0A
+#define RV8803_EXTENSION_REG             0x0D
+#define RV8803_FLAG_REG                  0x0E
+#define RV8803_CONTROL_REG               0x0F
+#define RV8803_OFFSET_REG                0x2C
+
+/* Bitmasks */
+#define RV8803_SECONDS_MASK GENMASK(6, 0)
+#define RV8803_MINUTES_MASK GENMASK(6, 0)
+#define RV8803_HOURS_MASK   GENMASK(5, 0)
+#define RV8803_WEEKDAY_MASK GENMASK(6, 0)
+#define RV8803_DATE_MASK    GENMASK(5, 0)
+#define RV8803_MONTH_MASK   GENMASK(4, 0)
+#define RV8803_YEAR_MASK    GENMASK(7, 0)
+
+#define RV8803_MINUTES_ALARM_AE_M_BIT          BIT(7)
+#define RV8803_MINUTES_ALARM_MASK              GENMASK(6, 0)
+#define RV8803_HOURS_ALARM_AE_H_BIT            BIT(7)
+#define RV8803_HOURS_ALARM_MASK                GENMASK(5, 0)
+#define RV8803_WEEKDAY_OR_DATE_ALARM_AE_WD_BIT BIT(7)
+#define RV8803_WEEKDAY_ALARM_MASK              GENMASK(6, 0)
+#define RV8803_DATE_ALARM_MASK                 GENMASK(5, 0)
+
+#define RV8803_EXTENSION_TEST_BIT BIT(7)
+#define RV8803_EXTENSION_WADA_BIT BIT(6)
+#define RV8803_EXTENSION_USEL_BIT BIT(5)
+#define RV8803_EXTENSION_TE_BIT   BIT(4)
+#define RV8803_EXTENSION_FD_MASK  GENMASK(3, 2)
+#define RV8803_EXTENSION_TD_MASK  GENMASK(1, 0)
+
+#define RV8803_EXTENSION_FD_32768Hz FIELD_PREP(RV8803_EXTENSION_FD_MASK, 0x00)
+#define RV8803_EXTENSION_FD_1024Hz  FIELD_PREP(RV8803_EXTENSION_FD_MASK, 0x01)
+#define RV8803_EXTENSION_FD_1Hz     FIELD_PREP(RV8803_EXTENSION_FD_MASK, 0x02)
+
+#define RV8803_FLAG_UF_BIT  BIT(5)
+#define RV8803_FLAG_TF_BIT  BIT(4)
+#define RV8803_FLAG_AF_BIT  BIT(3)
+#define RV8803_FLAG_EVF_BIT BIT(2)
+#define RV8803_FLAG_V2F_BIT BIT(1)
+#define RV8803_FLAG_V1F_BIT BIT(0)
+
+#define RV8803_CONTROL_UIE_BIT   BIT(5)
+#define RV8803_CONTROL_TIE_BIT   BIT(4)
+#define RV8803_CONTROL_AIE_BIT   BIT(3)
+#define RV8803_CONTROL_EIE_BIT   BIT(2)
+#define RV8803_CONTROL_RESET_BIT BIT(0)
+
+#define RV8803_MONDAY_MASK    BIT(0)
+#define RV8803_TUESDAY_MASK   BIT(1)
+#define RV8803_WEDNESDAY_MASK BIT(2)
+#define RV8803_THURSDAY_MASK  BIT(3)
+#define RV8803_FRIDAY_MASK    BIT(4)
+#define RV8803_SATURDAY_MASK  BIT(5)
+#define RV8803_SUNDAY_MASK    BIT(6)
+
+#define RV8803_OFFSET_MASK GENMASK(5, 0)
+
+/* Offset between first tm_year and first RV8803 year */
+#define RV8803_YEAR_OFFSET (2000 - 1900)
+
+/* RV8803 enumerates months 1 to 12 */
+#define RV8803_MONTH_OFFSET -1
+
+/* Max value of seconds, needed for readout procedure workaround */
+#define RV8803_SECONDS_MAX_VALUE 59
+
+/* See RV-8803-C7 Application Manual p. 22, 3.9. */
+#define RV8803_OFFSET_PPB_PER_LSB    238
+#define RV8803_OFFSET_PPB_MIN        (-32 * RV8803_OFFSET_PPB_PER_LSB)
+#define RV8803_OFFSET_PPB_MAX        (31 * RV8803_OFFSET_PPB_PER_LSB)
+#define RV8803_OFFSET_SIGN_BIT_INDEX 5 /* Required for aging offset sign extension */
+
+/* CLKOUT property enum values */
+#define RV8803_PROP_ENUM_1HZ     0
+#define RV8803_PROP_ENUM_1024HZ  1
+#define RV8803_PROP_ENUM_32768HZ 2
+
+#define DT_DRV_COMPAT microcrystal_rv8803
+
+#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 0
+#warning "Micro Crystal RV8803 driver enabled without any devices"
+#endif
+
+/* RTC time fields supported by RV8803 */
+#define RV8803_RTC_TIME_MASK                                                                       \
+	(RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR |      \
+	 RTC_ALARM_TIME_MASK_MONTH | RTC_ALARM_TIME_MASK_MONTHDAY | RTC_ALARM_TIME_MASK_YEAR |     \
+	 RTC_ALARM_TIME_MASK_WEEKDAY)
+
+/* RTC alarm time fields supported by RV8803 */
+#define RV8803_RTC_ALARM_TIME_MASK                                                                 \
+	(RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR | RTC_ALARM_TIME_MASK_MONTHDAY |    \
+	 RTC_ALARM_TIME_MASK_WEEKDAY)
+
+/* Helper macro to guard GPIO interrupt related stuff */
+#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(int_gpios) &&                                                 \
+	(defined(CONFIG_RTC_ALARM) || defined(CONFIG_RTC_UPDATE))
+#define RV8803_INT_GPIOS_IN_USE 1
+#endif
+
+LOG_MODULE_REGISTER(rv8803, CONFIG_RTC_LOG_LEVEL);
+
+struct rv8803_config {
+	const struct i2c_dt_spec i2c;
+#ifdef RV8803_INT_GPIOS_IN_USE
+	struct gpio_dt_spec gpio_int;
+#endif
+	uint16_t clkout_freq;
+};
+
+struct rv8803_data {
+	struct k_sem lock;
+#ifdef RV8803_INT_GPIOS_IN_USE
+	const struct device *dev;
+	struct gpio_callback irq_callback;
+	struct k_work work;
+
+#ifdef CONFIG_RTC_ALARM
+	rtc_alarm_callback alarm_callback;
+	void *alarm_user_data;
+#endif
+
+#ifdef CONFIG_RTC_UPDATE
+	rtc_update_callback update_callback;
+	void *update_user_data;
+#endif
+#endif
+};
+
+static void rv8803_lock_sem(const struct device *dev)
+{
+	struct rv8803_data *data = dev->data;
+
+	k_sem_take(&data->lock, K_FOREVER);
+}
+
+static void rv8803_unlock_sem(const struct device *dev)
+{
+	struct rv8803_data *data = dev->data;
+
+	k_sem_give(&data->lock);
+}
+
+static int rv8803_read_regs(const struct device *dev, uint8_t addr, void *buffer, size_t size)
+{
+	const struct rv8803_config *config = dev->config;
+	int err;
+
+	err = i2c_write_read_dt(&config->i2c, &addr, sizeof(addr), buffer, size);
+	if (err) {
+		LOG_ERR("Failed to read %zuB from register 0x%02X, error: %d", size, addr, err);
+	}
+	return err;
+}
+
+static int rv8803_read_reg8(const struct device *dev, uint8_t addr, uint8_t *val)
+{
+	return rv8803_read_regs(dev, addr, val, sizeof(*val));
+}
+
+static int rv8803_write_regs(const struct device *dev, uint8_t addr, const void *buffer,
+			     size_t size)
+{
+	const struct rv8803_config *config = dev->config;
+	const size_t i2c_data_size = sizeof(addr) + size;
+	uint8_t i2c_data[i2c_data_size];
+	int err;
+
+	/* Prepend data with I2C device address */
+	i2c_data[0] = addr;
+	memcpy(&i2c_data[1], buffer, size);
+
+	err = i2c_write_dt(&config->i2c, i2c_data, i2c_data_size);
+	if (err) {
+		LOG_ERR("Failed to write %zuB to register 0x%02X, error: %d", i2c_data_size, addr,
+			err);
+	}
+
+	return err;
+}
+
+#if defined(RV8803_INT_GPIOS_IN_USE) || defined(CONFIG_RTC_ALARM) || defined(CONFIG_RTC_CALIBRATION)
+static int rv8803_write_reg8(const struct device *dev, uint8_t addr, uint8_t val)
+{
+	return rv8803_write_regs(dev, addr, &val, sizeof(val));
+}
+#endif
+
+static int rv8803_update_reg8(const struct device *dev, uint8_t addr, uint8_t mask, uint8_t val)
+{
+	const struct rv8803_config *config = dev->config;
+	int err;
+
+	err = i2c_reg_update_byte_dt(&config->i2c, addr, mask, val);
+	if (err) {
+		LOG_ERR("Failed to update register 0x%02X with value 0x%02X and mask 0x%02X, "
+			"error: %d",
+			addr, val, mask, err);
+	}
+	return err;
+}
+
+static uint8_t rv8803_weekday2mask(int weekday)
+{
+	return (1 << weekday);
+}
+
+static int rv8803_mask2weekday(uint8_t mask)
+{
+	return find_lsb_set(mask) - 1;
+}
+
+#ifdef RV8803_INT_GPIOS_IN_USE
+
+static void rv8803_work_callback(struct k_work *work)
+{
+	struct rv8803_data *data = CONTAINER_OF(work, struct rv8803_data, work);
+	const struct device *dev = data->dev;
+	rtc_alarm_callback alarm_callback = NULL;
+	void *alarm_user_data = NULL;
+	rtc_update_callback update_callback = NULL;
+	void *update_user_data = NULL;
+	int err;
+	uint8_t flags;
+
+	rv8803_lock_sem(dev);
+
+	do {
+		/* Read flags register */
+		err = rv8803_read_reg8(dev, RV8803_FLAG_REG, &flags);
+		if (err) {
+			break;
+		}
+
+#ifdef CONFIG_RTC_ALARM
+		/* Handle alarm event */
+		if ((flags & RV8803_FLAG_AF_BIT) && (data->alarm_callback != NULL)) {
+			flags &= ~RV8803_FLAG_AF_BIT;
+			alarm_callback = data->alarm_callback;
+			alarm_user_data = data->alarm_user_data;
+		}
+#endif
+
+#ifdef CONFIG_RTC_UPDATE
+		/* Handle update event */
+		if ((flags & RV8803_FLAG_UF_BIT) && (data->update_callback != NULL)) {
+			flags &= ~RV8803_FLAG_UF_BIT;
+			update_callback = data->update_callback;
+			update_user_data = data->update_user_data;
+		}
+#endif
+
+		/* Clear flags */
+		err = rv8803_write_reg8(dev, RV8803_FLAG_REG, flags);
+		if (err) {
+			break;
+		}
+
+		/* Check if any interrupt occurred between flags register read/write */
+		err = rv8803_read_reg8(dev, RV8803_FLAG_REG, &flags);
+		if (err) {
+			break;
+		}
+
+		if (((flags & RV8803_FLAG_AF_BIT) && (alarm_callback != NULL)) ||
+		    ((flags & RV8803_FLAG_UF_BIT) && (update_callback != NULL))) {
+			/* Another interrupt occurred while servicing this one */
+			k_work_submit(&data->work);
+		}
+	} while (0);
+
+	rv8803_unlock_sem(dev);
+
+	if (alarm_callback != NULL) {
+		/* ID is always zero, there's only one set of alarm regs on chip */
+		alarm_callback(dev, 0, alarm_user_data);
+		alarm_callback = NULL;
+	}
+
+	if (update_callback != NULL) {
+		update_callback(dev, update_user_data);
+		update_callback = NULL;
+	}
+}
+
+static void rv8803_irq_handler(const struct device *port, struct gpio_callback *callback,
+			       gpio_port_pins_t pins)
+{
+	ARG_UNUSED(port);
+	ARG_UNUSED(pins);
+
+	struct rv8803_data *data = CONTAINER_OF(callback, struct rv8803_data, irq_callback);
+
+	k_work_submit(&data->work);
+}
+
+#endif
+
+static int rv8803_set_time(const struct device *dev, const struct rtc_time *timeptr)
+{
+	uint8_t date[7];
+	int err;
+
+	if ((timeptr == NULL) || !rtc_utils_validate_rtc_time(timeptr, RV8803_RTC_TIME_MASK) ||
+	    (timeptr->tm_year < RV8803_YEAR_OFFSET)) {
+		return -EINVAL;
+	}
+
+	rv8803_lock_sem(dev);
+
+	date[0] = bin2bcd(timeptr->tm_sec) & RV8803_SECONDS_MASK;
+	date[1] = bin2bcd(timeptr->tm_min) & RV8803_MINUTES_MASK;
+	date[2] = bin2bcd(timeptr->tm_hour) & RV8803_HOURS_MASK;
+	date[3] = rv8803_weekday2mask(timeptr->tm_wday);
+	date[4] = bin2bcd(timeptr->tm_mday) & RV8803_DATE_MASK;
+	date[5] = bin2bcd(timeptr->tm_mon - RV8803_MONTH_OFFSET) & RV8803_MONTH_MASK;
+	date[6] = bin2bcd(timeptr->tm_year - RV8803_YEAR_OFFSET) & RV8803_YEAR_MASK;
+
+	do {
+		/* Reset and freeze countdown chain */
+		err = rv8803_update_reg8(dev, RV8803_CONTROL_REG, RV8803_CONTROL_RESET_BIT,
+					 RV8803_CONTROL_RESET_BIT);
+		if (err) {
+			break;
+		}
+
+		/* Write new time value */
+		err = rv8803_write_regs(dev, RV8803_SECONDS_REG, date, sizeof(date));
+		if (err) {
+			break;
+		}
+
+		/* Clear Voltage Low flags */
+		err = rv8803_update_reg8(dev, RV8803_FLAG_REG,
+					 RV8803_FLAG_V1F_BIT | RV8803_FLAG_V2F_BIT, 0);
+		if (err) {
+			break;
+		}
+
+		/* Release countdown chain lock */
+		err = rv8803_update_reg8(dev, RV8803_CONTROL_REG, RV8803_CONTROL_RESET_BIT, 0);
+		if (err) {
+			break;
+		}
+	} while (0);
+
+	rv8803_unlock_sem(dev);
+
+	if (!err) {
+		LOG_DBG("Set time: year: %d, month: %d, month day: %d, week day: %d, hour: %d, "
+			"minute: %d, second: %d",
+			timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday,
+			timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
+	}
+
+	return err;
+}
+
+static int rv8803_get_time(const struct device *dev, struct rtc_time *timeptr)
+{
+	uint8_t flags;
+	uint8_t date_1[7];
+	uint8_t date_2[7];
+	uint8_t *date = date_1;
+	uint8_t seconds_1;
+	uint8_t seconds_2;
+	int err;
+
+	if (timeptr == NULL) {
+		return -EINVAL;
+	}
+
+	err = rv8803_read_reg8(dev, RV8803_FLAG_REG, &flags);
+	if (err) {
+		return err;
+	}
+
+	/* Voltage Flag 2 indicates data loss */
+	if (flags & RV8803_FLAG_V2F_BIT) {
+		return -ENODATA;
+	}
+
+	/* Time readout procedure to bypass the inability to freeze registers. */
+	/* See RV-8803-C7 Application Manual p. 42, 4.12.2. */
+	err = rv8803_read_regs(dev, RV8803_SECONDS_REG, date_1, sizeof(date_1));
+	if (err) {
+		return err;
+	}
+	seconds_1 = bcd2bin(date_1[0] & RV8803_SECONDS_MASK);
+	if (seconds_1 == RV8803_SECONDS_MAX_VALUE) {
+		err = rv8803_read_regs(dev, RV8803_SECONDS_REG, date_2, sizeof(date_2));
+		if (err) {
+			return err;
+		}
+
+		seconds_2 = bcd2bin(date_2[0] & RV8803_SECONDS_MASK);
+		if (seconds_2 != RV8803_SECONDS_MAX_VALUE) {
+			date = date_2;
+		}
+	}
+
+	memset(timeptr, 0, sizeof(*timeptr));
+	timeptr->tm_sec = bcd2bin(date[0] & RV8803_SECONDS_MASK);
+	timeptr->tm_min = bcd2bin(date[1] & RV8803_MINUTES_MASK);
+	timeptr->tm_hour = bcd2bin(date[2] & RV8803_HOURS_MASK);
+	timeptr->tm_wday = rv8803_mask2weekday(date[3] & RV8803_WEEKDAY_MASK);
+	timeptr->tm_mday = bcd2bin(date[4] & RV8803_DATE_MASK);
+	timeptr->tm_mon = bcd2bin(date[5] & RV8803_MONTH_MASK) + RV8803_MONTH_OFFSET;
+	timeptr->tm_year = bcd2bin(date[6] & RV8803_YEAR_MASK) + RV8803_YEAR_OFFSET;
+	timeptr->tm_yday = -1;  /* Unsupported */
+	timeptr->tm_isdst = -1; /* Unsupported */
+	timeptr->tm_nsec = 0;   /* Unsupported */
+
+	LOG_DBG("Read time: year: %d, month: %d, month day: %d, week day: %d, hour: %d, minute: "
+		"%d, second: %d",
+		timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday, timeptr->tm_wday,
+		timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
+
+	return 0;
+}
+
+#ifdef CONFIG_RTC_ALARM
+
+static int rv8803_alarm_get_supported_fields(const struct device *dev, uint16_t id, uint16_t *mask)
+{
+	ARG_UNUSED(dev);
+
+	if (id != 0) {
+		LOG_ERR("Invalid alarm ID: %d", id);
+		return -EINVAL;
+	}
+
+	*mask = RV8803_RTC_ALARM_TIME_MASK;
+
+	return 0;
+}
+
+static int rv8803_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
+				 const struct rtc_time *timeptr)
+{
+	uint8_t regs[3];
+	uint8_t reg_val;
+	int err;
+
+	if (id != 0) {
+		LOG_ERR("Invalid alarm ID: %d", id);
+		return -EINVAL;
+	}
+
+	if (mask & ~RV8803_RTC_ALARM_TIME_MASK) {
+		LOG_ERR("Unsupported alarm mask 0x%04X, excess field(s): 0x%04X", mask,
+			mask & ~(int16_t)RV8803_RTC_ALARM_TIME_MASK);
+		return -EINVAL;
+	}
+
+	if ((mask & RTC_ALARM_TIME_MASK_MONTHDAY) && (mask & RTC_ALARM_TIME_MASK_WEEKDAY)) {
+		LOG_ERR("Month day and week day alarms cannot be set simultaneously");
+		return -EINVAL;
+	}
+
+	if (!rtc_utils_validate_rtc_time(timeptr, mask)) {
+		LOG_ERR("Invalid alarm time");
+		return -EINVAL;
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
+		regs[0] = bin2bcd(timeptr->tm_min) & RV8803_MINUTES_ALARM_MASK;
+	} else {
+		regs[0] = RV8803_MINUTES_ALARM_AE_M_BIT;
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_HOUR) {
+		regs[1] = bin2bcd(timeptr->tm_hour) & RV8803_HOURS_ALARM_MASK;
+	} else {
+		regs[1] = RV8803_HOURS_ALARM_AE_H_BIT;
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
+		regs[2] = bin2bcd(timeptr->tm_mday) & RV8803_DATE_ALARM_MASK;
+	} else if (mask & RTC_ALARM_TIME_MASK_WEEKDAY) {
+		regs[2] = rv8803_weekday2mask(timeptr->tm_wday) & RV8803_WEEKDAY_ALARM_MASK;
+	} else {
+		regs[2] = RV8803_WEEKDAY_OR_DATE_ALARM_AE_WD_BIT;
+	}
+
+	/* Update WADA bit */
+	if ((mask & RTC_ALARM_TIME_MASK_MONTHDAY) || (mask & RTC_ALARM_TIME_MASK_WEEKDAY)) {
+		reg_val = (mask & RTC_ALARM_TIME_MASK_MONTHDAY) ? RV8803_EXTENSION_WADA_BIT : 0;
+		err = rv8803_update_reg8(dev, RV8803_EXTENSION_REG, RV8803_EXTENSION_WADA_BIT,
+					 reg_val);
+		if (err) {
+			return err;
+		}
+	}
+
+	/* Update alarm registers */
+	err = rv8803_write_regs(dev, RV8803_MINUTES_ALARM_REG, regs, sizeof(regs));
+	if (err) {
+		return err;
+	}
+
+	LOG_DBG("Set alarm: month day: %d, week day: %d, hour: %d, minute: %d, mask: 0x%04X",
+		timeptr->tm_mday, timeptr->tm_wday, timeptr->tm_hour, timeptr->tm_min, mask);
+
+	return 0;
+}
+
+static int rv8803_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
+				 struct rtc_time *timeptr)
+{
+	uint8_t regs[3];
+	uint8_t reg_val;
+	int err;
+
+	if (id != 0) {
+		LOG_ERR("Invalid alarm ID: %d", id);
+		return -EINVAL;
+	}
+
+	err = rv8803_read_regs(dev, RV8803_MINUTES_ALARM_REG, regs, sizeof(regs));
+	if (err) {
+		return err;
+	}
+
+	/* Read extension register to get WADA bit */
+	err = rv8803_read_reg8(dev, RV8803_EXTENSION_REG, &reg_val);
+	if (err) {
+		return err;
+	}
+
+	memset(timeptr, 0, sizeof(*timeptr));
+	*mask = 0;
+
+	if ((regs[0] & RV8803_MINUTES_ALARM_AE_M_BIT) == 0) {
+		timeptr->tm_min = bcd2bin(regs[0] & RV8803_MINUTES_ALARM_MASK);
+		*mask |= RTC_ALARM_TIME_MASK_MINUTE;
+	}
+
+	if ((regs[1] & RV8803_HOURS_ALARM_AE_H_BIT) == 0) {
+		timeptr->tm_hour = bcd2bin(regs[1] & RV8803_HOURS_ALARM_MASK);
+		*mask |= RTC_ALARM_TIME_MASK_HOUR;
+	}
+
+	if ((regs[2] & RV8803_WEEKDAY_OR_DATE_ALARM_AE_WD_BIT) == 0) {
+		if (reg_val & RV8803_EXTENSION_WADA_BIT) {
+			timeptr->tm_mday = bcd2bin(regs[2] & RV8803_DATE_ALARM_MASK);
+			*mask |= RTC_ALARM_TIME_MASK_MONTHDAY;
+		} else {
+			timeptr->tm_wday = find_lsb_set(regs[2] & RV8803_WEEKDAY_ALARM_MASK);
+			*mask |= RTC_ALARM_TIME_MASK_WEEKDAY;
+		}
+	}
+
+	LOG_DBG("Get alarm: month day: %d, week day: %d, hour: %d, minute: %d, mask: 0x%04X",
+		timeptr->tm_mday, timeptr->tm_wday, timeptr->tm_hour, timeptr->tm_min, *mask);
+
+	return 0;
+}
+
+static int rv8803_alarm_is_pending(const struct device *dev, uint16_t id)
+{
+	uint8_t flags;
+	int err;
+
+	if (id != 0) {
+		LOG_ERR("Invalid alarm ID: %d", id);
+		return -EINVAL;
+	}
+
+	rv8803_lock_sem(dev);
+
+	do {
+		err = rv8803_read_reg8(dev, RV8803_FLAG_REG, &flags);
+		if (err) {
+			break;
+		}
+
+		if (flags & RV8803_FLAG_AF_BIT) {
+			flags &= ~RV8803_FLAG_AF_BIT;
+
+			err = rv8803_write_reg8(dev, RV8803_FLAG_REG, flags);
+			if (err) {
+				break;
+			}
+
+			/* Indicate that alarm is pending */
+			err = 1;
+		}
+	} while (0);
+
+	rv8803_unlock_sem(dev);
+
+	return err;
+}
+
+#ifdef RV8803_INT_GPIOS_IN_USE
+
+static int rv8803_alarm_set_callback(const struct device *dev, uint16_t id,
+				     rtc_alarm_callback callback, void *user_data)
+{
+	const struct rv8803_config *config = dev->config;
+	struct rv8803_data *data = dev->data;
+	uint8_t reg_val;
+	int err;
+
+	if (config->gpio_int.port == NULL) {
+		return -ENOTSUP;
+	}
+
+	if (id != 0) {
+		LOG_ERR("Invalid alarm ID: %d", id);
+		return -EINVAL;
+	}
+
+	rv8803_lock_sem(dev);
+
+	data->alarm_callback = callback;
+	data->alarm_user_data = user_data;
+
+	/* Enable alarm interrupt if callback provided */
+	reg_val = (callback != NULL) ? RV8803_CONTROL_AIE_BIT : 0;
+	err = rv8803_update_reg8(dev, RV8803_CONTROL_REG, RV8803_CONTROL_AIE_BIT, reg_val);
+
+	rv8803_unlock_sem(dev);
+
+	/* Alarm IRQ might have already been triggered */
+	k_work_submit(&data->work);
+
+	return err;
+}
+
+#endif
+
+#endif
+
+#if defined(RV8803_INT_GPIOS_IN_USE) && defined(CONFIG_RTC_UPDATE)
+
+static int rv8803_update_set_callback(const struct device *dev, rtc_update_callback callback,
+				      void *user_data)
+{
+	const struct rv8803_config *config = dev->config;
+	struct rv8803_data *data = dev->data;
+	uint8_t reg_val;
+	int err;
+
+	if (config->gpio_int.port == NULL) {
+		return -ENOTSUP;
+	}
+
+	rv8803_lock_sem(dev);
+
+	data->update_callback = callback;
+	data->update_user_data = user_data;
+
+	/* Enable update interrupt if callback provided */
+	reg_val = (callback != NULL) ? RV8803_CONTROL_UIE_BIT : 0;
+	err = rv8803_update_reg8(dev, RV8803_CONTROL_REG, RV8803_CONTROL_UIE_BIT, reg_val);
+
+	rv8803_unlock_sem(dev);
+
+	/* Update IRQ might have already been triggered */
+	k_work_submit(&data->work);
+
+	return err;
+}
+
+#endif
+
+#ifdef CONFIG_RTC_CALIBRATION
+
+static int rv8803_set_calibration(const struct device *dev, int32_t freq_ppb)
+{
+	int8_t offset;
+
+	if ((freq_ppb < RV8803_OFFSET_PPB_MIN) || (freq_ppb > RV8803_OFFSET_PPB_MAX)) {
+		LOG_ERR("Calibration value %d ppb out of range", freq_ppb);
+		return -EINVAL;
+	}
+
+	offset = (freq_ppb / RV8803_OFFSET_PPB_PER_LSB) & RV8803_OFFSET_MASK;
+
+	LOG_DBG("Set calibration: frequency ppb: %d, offset value: %d", freq_ppb, offset);
+
+	return rv8803_write_reg8(dev, RV8803_OFFSET_REG, offset);
+}
+
+static int rv8803_get_calibration(const struct device *dev, int32_t *freq_ppb)
+{
+	int8_t offset;
+	int err;
+
+	err = rv8803_read_reg8(dev, RV8803_OFFSET_REG, &offset);
+	if (err) {
+		return err;
+	}
+
+	*freq_ppb = sign_extend(offset, RV8803_OFFSET_SIGN_BIT_INDEX) * RV8803_OFFSET_PPB_PER_LSB;
+
+	LOG_DBG("Get calibration: frequency ppb: %d, offset value: %d", *freq_ppb, offset);
+
+	return 0;
+}
+#endif
+
+static int rv8803_init(const struct device *dev)
+{
+	const struct rv8803_config *config = dev->config;
+	struct rv8803_data *data = dev->data;
+	uint8_t freq;
+	uint8_t regs[3];
+	int err;
+
+	k_sem_init(&data->lock, 1, 1);
+
+	if (!i2c_is_ready_dt(&config->i2c)) {
+		LOG_ERR("I2C bus not ready");
+		return -ENODEV;
+	}
+
+#ifdef RV8803_INT_GPIOS_IN_USE
+	if (config->gpio_int.port != NULL) {
+		if (!gpio_is_ready_dt(&config->gpio_int)) {
+			LOG_ERR("GPIO not ready");
+			return -ENODEV;
+		}
+
+		err = gpio_pin_configure_dt(&config->gpio_int, GPIO_INPUT);
+		if (err) {
+			LOG_ERR("Failed to configure interrupt GPIO, error: %d", err);
+			return err;
+		}
+
+		err = gpio_pin_interrupt_configure_dt(&config->gpio_int, GPIO_INT_EDGE_TO_ACTIVE);
+		if (err) {
+			LOG_ERR("Failed to enable GPIO interrupt, error: %d", err);
+			return err;
+		}
+
+		gpio_init_callback(&data->irq_callback, rv8803_irq_handler,
+				   BIT(config->gpio_int.pin));
+
+		err = gpio_add_callback_dt(&config->gpio_int, &data->irq_callback);
+		if (err) {
+			LOG_ERR("Failed to add GPIO callback, error: %d", err);
+			return err;
+		}
+
+		data->dev = dev;
+		data->work.handler = rv8803_work_callback;
+	}
+#endif
+
+	/* Configure CLKOUT frequency */
+	switch (config->clkout_freq) {
+	case RV8803_PROP_ENUM_1HZ:
+		freq = RV8803_EXTENSION_FD_1Hz;
+		break;
+	case RV8803_PROP_ENUM_1024HZ:
+		freq = RV8803_EXTENSION_FD_1024Hz;
+		break;
+	case RV8803_PROP_ENUM_32768HZ:
+	default:
+		freq = RV8803_EXTENSION_FD_32768Hz;
+		break;
+	}
+	err = rv8803_update_reg8(dev, RV8803_EXTENSION_REG, RV8803_EXTENSION_FD_MASK, freq);
+	if (err) {
+		return -ENODEV;
+	}
+
+	/* Clear alarm and update flag */
+	err = rv8803_update_reg8(dev, RV8803_CONTROL_REG, RV8803_FLAG_AF_BIT | RV8803_FLAG_UF_BIT,
+				 RV8803_FLAG_AF_BIT | RV8803_FLAG_UF_BIT);
+	if (err) {
+		return -ENODEV;
+	}
+
+	/* Disable IRQs */
+	err = rv8803_update_reg8(dev, RV8803_CONTROL_REG,
+				 RV8803_CONTROL_AIE_BIT | RV8803_CONTROL_UIE_BIT, 0);
+	if (err) {
+		return -ENODEV;
+	}
+
+	/* Disable alarms */
+	err = rv8803_read_regs(dev, RV8803_MINUTES_ALARM_REG, regs, sizeof(regs));
+	if (err) {
+		return -ENODEV;
+	}
+
+	regs[0] |= RV8803_MINUTES_ALARM_AE_M_BIT;
+	regs[1] |= RV8803_HOURS_ALARM_AE_H_BIT;
+	regs[2] |= RV8803_WEEKDAY_OR_DATE_ALARM_AE_WD_BIT;
+
+	err = rv8803_write_regs(dev, RV8803_MINUTES_ALARM_REG, regs, sizeof(regs));
+	if (err) {
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(rtc, rv8803_driver_api) = {
+	.set_time = rv8803_set_time,
+	.get_time = rv8803_get_time,
+#ifdef CONFIG_RTC_ALARM
+	.alarm_get_supported_fields = rv8803_alarm_get_supported_fields,
+	.alarm_set_time = rv8803_alarm_set_time,
+	.alarm_get_time = rv8803_alarm_get_time,
+	.alarm_is_pending = rv8803_alarm_is_pending,
+#ifdef RV8803_INT_GPIOS_IN_USE
+	.alarm_set_callback = rv8803_alarm_set_callback,
+#endif
+#endif
+#if defined(RV8803_INT_GPIOS_IN_USE) && defined(CONFIG_RTC_UPDATE)
+	.update_set_callback = rv8803_update_set_callback,
+#endif
+#ifdef CONFIG_RTC_CALIBRATION
+	.set_calibration = rv8803_set_calibration,
+	.get_calibration = rv8803_get_calibration
+#endif
+};
+
+#define RV8803_INIT(inst)                                                                          \
+	static const struct rv8803_config rv8803_config_##inst = {                                 \
+		.i2c = I2C_DT_SPEC_INST_GET(inst),                                                 \
+		.clkout_freq = DT_INST_ENUM_IDX_OR(inst, clkout_frequency, 0),                     \
+		IF_ENABLED(                                                                        \
+			RV8803_INT_GPIOS_IN_USE,                                                   \
+			(.gpio_int = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, {0}))               \
+		)                                                                                  \
+	};                                                                                         \
+                                                                                                   \
+	static struct rv8803_data rv8803_data_##inst;                                              \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(inst, rv8803_init, NULL, &rv8803_data_##inst, &rv8803_config_##inst, \
+			      POST_KERNEL, CONFIG_RTC_INIT_PRIORITY, &rv8803_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(RV8803_INIT);
diff --git a/drivers/rtc/rtc_rx8130ce.c b/drivers/rtc/rtc_rx8130ce.c
new file mode 100644
index 00000000000..89a5430d51c
--- /dev/null
+++ b/drivers/rtc/rtc_rx8130ce.c
@@ -0,0 +1,776 @@
+/*
+ * Copyright (c) 2025 Måns Ansgariusson <mansgariusson@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/rtc.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(rx8130ce, CONFIG_RTC_LOG_LEVEL);
+
+#define DT_DRV_COMPAT epson_rx8130ce_rtc
+
+enum registers {
+	TIME		= 0x10,
+	ALARM		= 0x17,
+	/* control registers */
+	EXTENSION	= 0x1C,
+	FLAG		= 0x1D,
+	CTRL0		= 0x1E,
+	CTRL1		= 0x1F,
+	OFFSET		= 0x30,
+};
+
+#define RX8130CE_SECONDS_MASK	GENMASK(6, 0)
+#define RX8130CE_MINUTES_MASK	GENMASK(6, 0)
+#define RX8130CE_HOURS_MASK	GENMASK(5, 0)
+#define RX8130CE_DAYS_MASK	GENMASK(5, 0)
+#define RX8130CE_WEEKDAYS_MASK	GENMASK(6, 0)
+#define RX8130CE_MONTHS_MASK	GENMASK(4, 0)
+#define RX8130CE_YEARS_MASK	GENMASK(7, 0)
+
+#define RX8130CE_MONTHS_OFFSET (1)
+#define RX8130CE_YEARS_OFFSET (100)
+
+/* Alarm AE bit */
+#define ALARM_DISABLE	BIT(7)
+
+/* Extension reg(0x1C) bit field */
+#define EXT_TSEL0	BIT(0)
+#define EXT_TSEL1	BIT(1)
+#define EXT_TSEL2	BIT(2)
+#define EXT_WADA	BIT(3)
+#define EXT_TE		BIT(4)
+#define EXT_USEL	BIT(5)
+#define EXT_FSEL0	BIT(6)
+#define EXT_FSEL1	BIT(7)
+
+/* Flag reg(0x1D) bit field */
+#define FLAG_VBFF	BIT(0)
+#define FLAG_VLF	BIT(1)
+#define FLAG_RSF	BIT(2)
+#define FLAG_AF		BIT(3)
+#define FLAG_TF		BIT(4)
+#define FLAG_UF		BIT(5)
+#define FLAG_VBLF	BIT(7)
+
+/* Control0 reg(0x1E) bit field */
+#define CTRL0_TBKE	BIT(0)
+#define CTRL0_TBKON	BIT(1)
+#define CTRL0_TSTP	BIT(2)
+#define CTRL0_AIE	BIT(3)
+#define CTRL0_TIE	BIT(4)
+#define CTRL0_UIE	BIT(5)
+#define CTRL0_STOP	BIT(6)
+#define CTRL0_TEST	BIT(7)
+
+/* ctrl1 reg(0x1F) bit field */
+#define CTRL1_BFVSEL0	BIT(0)
+#define CTRL1_BFVSEL1	BIT(1)
+#define CTRL1_RSVSEL	BIT(2)
+#define CTRL1_INIEN	BIT(4)
+#define CTRL1_CHGEN	BIT(5)
+#define CTRL1_SMPTSEL0	BIT(6)
+#define CTRL1_SMPTSEL1	BIT(7)
+
+
+/* Digital Offest reg(0x30) bit field */
+#define DIGITAL_OFFSET_NEG	BIT(6)
+#define DIGITAL_OFFSET_DTE	BIT(7)
+
+/* Digital Offset register values */
+#define DIGITAL_OFFSET_MAX	192260
+#define DIGITAL_OFFSET_MIN	-195310
+#define DIGITAL_OFFSET_STEP_PPB	3050
+
+/**
+ * @brief rx8130ce control registers
+ * 0x1C extension register
+ * 0x1D Flag register
+ * 0x1E control0
+ * 0x1F ctrl1
+ */
+struct __packed rx8130ce_registers {
+	uint8_t extension;
+	uint8_t flag;
+	uint8_t ctrl0;
+	uint8_t ctrl1;
+};
+
+struct __packed rx8130ce_time {
+	uint8_t second;
+	uint8_t minute;
+	uint8_t hour;
+	uint8_t weekday;
+	uint8_t day;
+	uint8_t month;
+	uint8_t year;
+};
+
+struct __packed rx8130ce_alarm {
+	uint8_t minute;
+	uint8_t hour;
+	union {
+		uint8_t wday;
+		uint8_t day;
+	};
+};
+
+struct rx8130ce_config {
+	const struct i2c_dt_spec i2c;
+	struct gpio_dt_spec irq;
+	uint16_t clockout_frequency;
+	uint8_t battery_switchover;
+};
+
+struct rx8130ce_data {
+	struct k_sem lock;
+	const struct device *dev;
+	struct rx8130ce_registers reg;
+
+#if defined(CONFIG_RTC_ALARM) || defined(CONFIG_RTC_UPDATE)
+	struct gpio_callback irq_cb;
+	struct k_work irq_work;
+#endif
+#ifdef CONFIG_RTC_ALARM
+	void *alarm_user_data;
+	rtc_alarm_callback alarm_callback;
+#endif /* CONFIG_RTC_ALARM */
+#ifdef CONFIG_RTC_UPDATE
+	void *update_user_data;
+	rtc_update_callback update_callback;
+#endif /* CONFIG_RTC_UPDATE */
+};
+
+static inline uint8_t wday2rtc(uint8_t wday)
+{
+	return 1 << wday;
+}
+
+static inline uint8_t rtc2wday(uint8_t rtc_wday)
+{
+	for (size_t bit = 0 ; bit < 7; bit++) {
+		if (rtc_wday & (1 << bit)) {
+			return bit;
+		}
+	}
+	return 0;
+}
+
+static int rx8130ce_get_time(const struct device *dev, struct rtc_time *timeptr)
+{
+	int rc = 0;
+	struct rx8130ce_time rtc_time;
+	const struct rx8130ce_config *cfg = dev->config;
+	struct rx8130ce_data *data = dev->data;
+
+	memset(timeptr, 0U, sizeof(*timeptr));
+
+	k_sem_take(&data->lock, K_FOREVER);
+	rc = i2c_burst_read_dt(&cfg->i2c, TIME, (uint8_t *)&rtc_time, sizeof(rtc_time));
+	if (rc != 0) {
+		LOG_ERR("Failed to read time");
+		goto error;
+	}
+	timeptr->tm_sec = bcd2bin(rtc_time.second & RX8130CE_SECONDS_MASK);
+	timeptr->tm_min = bcd2bin(rtc_time.minute & RX8130CE_MINUTES_MASK);
+	timeptr->tm_hour = bcd2bin(rtc_time.hour & RX8130CE_HOURS_MASK);
+	timeptr->tm_mday = bcd2bin(rtc_time.day & RX8130CE_DAYS_MASK);
+	timeptr->tm_wday = rtc2wday(rtc_time.weekday & RX8130CE_WEEKDAYS_MASK);
+	timeptr->tm_mon = bcd2bin(rtc_time.month & RX8130CE_MONTHS_MASK) - RX8130CE_MONTHS_OFFSET;
+	timeptr->tm_year = bcd2bin(rtc_time.year & RX8130CE_YEARS_MASK) + RX8130CE_YEARS_OFFSET;
+	timeptr->tm_yday = -1;
+	timeptr->tm_isdst = -1;
+
+error:
+	k_sem_give(&data->lock);
+	return rc;
+}
+
+static int rx8130ce_set_time(const struct device *dev, const struct rtc_time *timeptr)
+{
+	int rc = 0;
+	struct rx8130ce_time rtc_time;
+	const struct rx8130ce_config *cfg = dev->config;
+	struct rx8130ce_data *data = dev->data;
+
+	rtc_time.second = bin2bcd(timeptr->tm_sec);
+	rtc_time.minute  = bin2bcd(timeptr->tm_min);
+	rtc_time.hour   = bin2bcd(timeptr->tm_hour);
+	rtc_time.weekday = wday2rtc(timeptr->tm_wday);
+	rtc_time.day =   bin2bcd(timeptr->tm_mday);
+	rtc_time.month = bin2bcd(timeptr->tm_mon + RX8130CE_MONTHS_OFFSET);
+	rtc_time.year  = bin2bcd(timeptr->tm_year -
+			  (timeptr->tm_year >= RX8130CE_YEARS_OFFSET ? RX8130CE_YEARS_OFFSET : 0));
+
+	k_sem_take(&data->lock, K_FOREVER);
+
+	rc = i2c_burst_write_dt(&cfg->i2c, TIME, (uint8_t *)&rtc_time, sizeof(rtc_time));
+	if (rc != 0) {
+		LOG_ERR("Failed to write time");
+		goto error;
+	}
+	LOG_DBG("set time: year = %d, mon = %d, mday = %d, hour = %d, min = %d, sec = %d",
+		timeptr->tm_year, timeptr->tm_mon, timeptr->tm_mday,
+		timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
+error:
+	k_sem_give(&data->lock);
+	return rc;
+}
+
+#if defined(CONFIG_RTC_ALARM) || defined(CONFIG_RTC_UPDATE)
+static void rx8130ce_irq_work_handler(struct k_work *work)
+{
+	int rc;
+	const struct device *dev = CONTAINER_OF(work, struct rx8130ce_data, irq_work)->dev;
+	struct rx8130ce_data *data = CONTAINER_OF(work, struct rx8130ce_data, irq_work);
+	const struct rx8130ce_config *cfg = data->dev->config;
+	#ifdef CONFIG_RTC_ALARM
+	rtc_alarm_callback alarm_callback = NULL;
+	void *alarm_user_data = NULL;
+	#endif /* CONFIG_RTC_ALARM */
+	#ifdef CONFIG_RTC_UPDATE
+	rtc_update_callback update_callback = NULL;
+	void *update_user_data = NULL;
+	#endif /* CONFIG_RTC_UPDATE */
+
+	k_sem_take(&data->lock, K_FOREVER);
+	rc = i2c_burst_read_dt(&cfg->i2c, EXTENSION, (uint8_t *)&data->reg, sizeof(data->reg));
+	if (rc != 0) {
+		LOG_ERR("Failed to read flag register");
+		goto exit;
+	}
+#ifdef CONFIG_RTC_ALARM
+	if ((data->reg.flag & FLAG_AF) != 0) {
+		LOG_INF("Alarm triggered");
+		alarm_callback = data->alarm_callback;
+		alarm_user_data = data->alarm_user_data;
+	}
+#endif /* CONFIG_RTC_ALARM */
+#ifdef CONFIG_RTC_UPDATE
+	if ((data->reg.flag & FLAG_UF) != 0) {
+		LOG_INF("Update triggered");
+		update_callback = data->update_callback;
+		update_user_data = data->update_user_data;
+	}
+#endif /* CONFIG_RTC_UPDATE */
+	/* Clear alarm flags */
+	data->reg.flag &= ~(FLAG_AF | FLAG_UF);
+	rc = i2c_burst_write_dt(&cfg->i2c, EXTENSION, (uint8_t *)&data->reg, sizeof(data->reg));
+	if (rc != 0) {
+		LOG_ERR("Failed to clear alarm flag");
+		goto exit;
+	}
+exit:
+	k_sem_give(&data->lock);
+
+#ifdef CONFIG_RTC_ALARM
+	if (alarm_callback) {
+		alarm_callback(dev, 0, alarm_user_data);
+	}
+#endif /* CONFIG_RTC_ALARM */
+#ifdef CONFIG_RTC_UPDATE
+	if (update_callback) {
+		update_callback(dev, update_user_data);
+	}
+#endif /* CONFIG_RTC_UPDATE */
+}
+
+static void rx8130ce_irq(const struct device *dev, struct gpio_callback *cb, uint32_t pins)
+{
+	struct rx8130ce_data *data = CONTAINER_OF(cb, struct rx8130ce_data, irq_cb);
+
+	LOG_DBG("IRQ-recv");
+	k_work_submit(&data->irq_work);
+}
+#endif /* CONFIG_RTC_ALARM || CONFIG_RTC_UPDATE */
+
+#ifdef CONFIG_RTC_ALARM
+#define RX8130CE_ALARM_MASK (RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR | \
+				RTC_ALARM_TIME_MASK_MONTHDAY)
+static int rx8130ce_alarm_get_supported_fields(const struct device *dev, uint16_t id,
+						uint16_t *mask)
+{
+	const struct rx8130ce_config *cfg = dev->config;
+
+	if (cfg->irq.port == NULL) {
+		LOG_ERR("IRQ not configured");
+		return -ENOTSUP;
+	}
+
+	if (id != 0U) {
+		LOG_ERR("invalid ID %d", id);
+		return -EINVAL;
+	}
+
+	*mask = RX8130CE_ALARM_MASK;
+	return 0;
+}
+
+static int rx8130ce_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
+					const struct rtc_time *timeptr)
+{
+	int rc = 0;
+	bool alarm_enabled = false;
+	struct rx8130ce_alarm alarm_time;
+	struct rx8130ce_data *data = dev->data;
+	const struct rx8130ce_config *cfg = dev->config;
+
+	if (id != 0U) {
+		LOG_ERR("invalid ID %d", id);
+		return -EINVAL;
+	}
+
+	if ((mask & ~(RX8130CE_ALARM_MASK)) != 0U) {
+		LOG_ERR("unsupported alarm field mask 0x%04x", mask);
+		return -EINVAL;
+	}
+
+	k_sem_take(&data->lock, K_FOREVER);
+
+	rc = i2c_burst_read_dt(&cfg->i2c, EXTENSION, (uint8_t *)&data->reg, sizeof(data->reg));
+	if (rc != 0) {
+		LOG_ERR("Failed to read control registers");
+		goto error;
+	}
+	/* Prevent alarm interrupts inadvertently while entering settings/time */
+	if ((data->reg.ctrl0 & CTRL0_AIE) != 0) {
+		alarm_enabled = true;
+		data->reg.ctrl0 &= ~CTRL0_AIE;
+		rc = i2c_burst_write_dt(&cfg->i2c, EXTENSION, (uint8_t *)&data->reg,
+			  sizeof(data->reg));
+		if (rc != 0) {
+			LOG_ERR("Failed to write time");
+			goto error;
+		}
+	}
+
+	/* Set alarm */
+	if (alarm_enabled) {
+		data->reg.ctrl0 |= CTRL0_AIE;
+	}
+
+	alarm_time.minute = bin2bcd(timeptr->tm_min);
+	alarm_time.hour = bin2bcd(timeptr->tm_hour);
+	alarm_time.day = bin2bcd(timeptr->tm_mday);
+	data->reg.extension |= EXT_WADA;
+
+	if ((mask & RTC_ALARM_TIME_MASK_MINUTE) == 0U) {
+		alarm_time.minute |= ALARM_DISABLE;
+	}
+	if ((mask & RTC_ALARM_TIME_MASK_HOUR) == 0U) {
+		alarm_time.hour |= ALARM_DISABLE;
+	}
+	if ((mask & RTC_ALARM_TIME_MASK_MONTHDAY) == 0U) {
+		alarm_time.day |= ALARM_DISABLE;
+	}
+
+	/* Write alarm time */
+	rc = i2c_burst_write_dt(&cfg->i2c, ALARM, (uint8_t *)&alarm_time, sizeof(alarm_time));
+	if (rc != 0) {
+		LOG_ERR("Failed to write alarm time");
+		goto error;
+	}
+
+	/* Enable alarm */
+	rc = i2c_burst_write_dt(&cfg->i2c, EXTENSION, (uint8_t *)&data->reg, sizeof(data->reg));
+	if (rc != 0) {
+		LOG_ERR("Failed to write control registers");
+		goto error;
+	}
+error:
+	k_sem_give(&data->lock);
+	return rc;
+
+}
+
+static int rx8130ce_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
+					struct rtc_time *timeptr)
+{
+	int rc = 0;
+	struct rx8130ce_alarm alarm_time;
+	struct rx8130ce_data *data = dev->data;
+	const struct rx8130ce_config *cfg = dev->config;
+
+	if (id != 0U) {
+		LOG_ERR("invalid ID %d", id);
+		return -EINVAL;
+	}
+
+	k_sem_take(&data->lock, K_FOREVER);
+	*mask = 0U;
+	memset(timeptr, 0x00, sizeof(*timeptr));
+	rc = i2c_burst_read_dt(&cfg->i2c, EXTENSION, (uint8_t *)&data->reg, sizeof(data->reg));
+	if (rc != 0) {
+		LOG_ERR("Failed to read control registers");
+		goto error;
+	}
+
+	rc = i2c_burst_read_dt(&cfg->i2c, ALARM, (uint8_t *)&alarm_time, sizeof(alarm_time));
+	if (rc != 0) {
+		LOG_ERR("Failed to read alarm time");
+		goto error;
+	}
+
+	timeptr->tm_min = bcd2bin(alarm_time.minute & RX8130CE_MINUTES_MASK);
+	timeptr->tm_hour = bcd2bin(alarm_time.hour & RX8130CE_HOURS_MASK);
+	if (!(alarm_time.minute & ALARM_DISABLE)) {
+		*mask |= RTC_ALARM_TIME_MASK_MINUTE;
+	}
+	if (!(alarm_time.hour & ALARM_DISABLE)) {
+		*mask |= RTC_ALARM_TIME_MASK_HOUR;
+	}
+	if (data->reg.extension & EXT_WADA) {
+		timeptr->tm_mday = bcd2bin(alarm_time.day);
+		if (!(alarm_time.day & ALARM_DISABLE)) {
+			*mask |= RTC_ALARM_TIME_MASK_MONTHDAY;
+		}
+	} else {
+		timeptr->tm_wday = rtc2wday(alarm_time.wday);
+		if (!(alarm_time.wday & ALARM_DISABLE)) {
+			*mask |= RTC_ALARM_TIME_MASK_WEEKDAY;
+		}
+	}
+error:
+	k_sem_give(&data->lock);
+	return rc;
+}
+
+static int rx8130ce_alarm_is_pending(const struct device *dev, uint16_t id)
+{
+	int rc = 0;
+	struct rx8130ce_data *data = dev->data;
+	const struct rx8130ce_config *cfg = dev->config;
+
+	if (id != 0U) {
+		LOG_ERR("invalid ID %d", id);
+		return -EINVAL;
+	}
+
+	k_sem_take(&data->lock, K_FOREVER);
+	rc = i2c_burst_read_dt(&cfg->i2c, EXTENSION, (uint8_t *)&data->reg, sizeof(data->reg));
+	if (rc != 0) {
+		LOG_ERR("Failed to read control registers");
+		goto error;
+	}
+
+	rc = (data->reg.ctrl0 & CTRL0_AIE) != 0;
+error:
+	k_sem_give(&data->lock);
+	return rc;
+}
+
+static int rx8130ce_alarm_set_callback(const struct device *dev, uint16_t id,
+				       rtc_alarm_callback callback, void *user_data)
+{
+	int rc = 0;
+	struct rx8130ce_data *data = dev->data;
+	const struct rx8130ce_config *cfg = dev->config;
+
+	if (id != 0U) {
+		LOG_ERR("invalid ID %d", id);
+		return -EINVAL;
+	}
+	if (cfg->irq.port == NULL) {
+		LOG_ERR("IRQ not configured");
+		return -ENOTSUP;
+	}
+
+	k_sem_take(&data->lock, K_FOREVER);
+	rc = i2c_burst_read_dt(&cfg->i2c, EXTENSION, (uint8_t *)&data->reg, sizeof(data->reg));
+	if (rc != 0) {
+		LOG_ERR("Failed to read control registers");
+		goto exit;
+	}
+	if (callback == NULL) {
+		data->alarm_user_data = NULL;
+		data->alarm_callback = NULL;
+		data->reg.ctrl0 &= ~CTRL0_AIE;
+#ifdef CONFIG_RTC_UPDATE
+		if (data->update_callback == NULL) {
+#endif
+			rc = gpio_pin_interrupt_configure_dt(&cfg->irq, GPIO_INT_DISABLE);
+			if (rc != 0) {
+				LOG_ERR("Failed to disable interrupt");
+				goto exit;
+			}
+#ifdef CONFIG_RTC_UPDATE
+		}
+#endif
+	} else {
+		/* Enable alarm interrupt  & clear Alarm flag */
+		data->reg.ctrl0 |= CTRL0_AIE;
+		data->reg.flag &= ~FLAG_AF;
+		data->alarm_callback = callback;
+		data->alarm_user_data = user_data;
+		rc = gpio_pin_interrupt_configure_dt(&cfg->irq, GPIO_INT_EDGE_TO_ACTIVE);
+		if (rc != 0) {
+			LOG_ERR("Failed to configure interrupt");
+			goto exit;
+		}
+	}
+	rc = i2c_burst_write_dt(&cfg->i2c, EXTENSION, (uint8_t *)&data->reg, sizeof(data->reg));
+	if (rc != 0) {
+		LOG_ERR("Failed to write control registers");
+		goto exit;
+	}
+exit:
+	k_sem_give(&data->lock);
+	return rc;
+}
+#endif /* CONFIG_RTC_ALARM */
+
+#ifdef CONFIG_RTC_UPDATE
+static int rx8130ce_update_set_callback(const struct device *dev, rtc_update_callback callback,
+					void *user_data)
+{
+	int rc = 0;
+	const struct rx8130ce_config *cfg = dev->config;
+	struct rx8130ce_data *data = dev->data;
+
+	if (cfg->irq.port == NULL) {
+		LOG_ERR("IRQ not configured");
+		return -ENOTSUP;
+	}
+
+	k_sem_take(&data->lock, K_FOREVER);
+	rc = i2c_burst_read_dt(&cfg->i2c, EXTENSION, (uint8_t *)&data->reg, sizeof(data->reg));
+	if (rc != 0) {
+		LOG_ERR("Failed to read control registers");
+		goto exit;
+	}
+	if (callback == NULL) {
+		data->reg.ctrl0 &= ~CTRL0_UIE;
+		data->update_user_data = NULL;
+		data->update_callback = NULL;
+
+		#ifdef CONFIG_RTC_ALARM
+		if (data->alarm_callback == NULL) {
+		#endif
+			rc = gpio_pin_interrupt_configure_dt(&cfg->irq, GPIO_INT_DISABLE);
+			if (rc != 0) {
+				LOG_ERR("Failed to disable interrupt");
+				goto exit;
+			}
+		#ifdef CONFIG_RTC_ALARM
+		}
+		#endif
+	} else {
+		data->reg.ctrl0 |= CTRL0_UIE;
+		data->update_callback = callback;
+		data->update_user_data = user_data;
+		rc = gpio_pin_interrupt_configure_dt(&cfg->irq, GPIO_INT_EDGE_TO_ACTIVE);
+		if (rc != 0) {
+			LOG_ERR("Failed to configure interrupt");
+			goto exit;
+		}
+	}
+	rc = i2c_burst_write_dt(&cfg->i2c, EXTENSION, (uint8_t *)&data->reg, sizeof(data->reg));
+	if (rc != 0) {
+		LOG_ERR("Failed to write control registers");
+		goto exit;
+	}
+exit:
+	k_sem_give(&data->lock);
+	return rc;
+
+}
+#endif /* CONFIG_RTC_UPDATE */
+
+#ifdef CONFIG_RTC_CALIBRATION
+static int rx8130ce_set_calibration(const struct device *dev, int32_t freq_ppb)
+{
+	int rc;
+	const struct rx8130ce_config *cfg = dev->config;
+	struct rx8130ce_data *data = dev->data;
+	uint8_t offset = 0;
+
+	if (freq_ppb < DIGITAL_OFFSET_MIN || freq_ppb > DIGITAL_OFFSET_MAX) {
+		LOG_ERR("Invalid calibration value: %d", freq_ppb);
+		return -EINVAL;
+	}
+
+	k_sem_take(&data->lock, K_FOREVER);
+	/* Explanation see section 17 of the datasheet */
+	if (freq_ppb < 0) {
+		offset |= DIGITAL_OFFSET_DTE;
+		offset |= DIGITAL_OFFSET_NEG;
+		offset |= 128 - (-freq_ppb / DIGITAL_OFFSET_STEP_PPB);
+	} else if (freq_ppb > 0) {
+		offset |= DIGITAL_OFFSET_DTE;
+		offset |= freq_ppb / DIGITAL_OFFSET_STEP_PPB;
+	}
+	LOG_DBG("set calibration: offset = 0x%02x, from %d", offset, freq_ppb);
+
+	rc = i2c_burst_write_dt(&cfg->i2c, OFFSET, &offset, sizeof(offset));
+	if (rc != 0) {
+		LOG_ERR("Failed to write calibration value");
+		goto exit;
+	}
+exit:
+	k_sem_give(&data->lock);
+	return rc;
+}
+
+static int rx8130ce_get_calibration(const struct device *dev, int32_t *freq_ppb)
+{
+	int rc;
+	const struct rx8130ce_config *cfg = dev->config;
+	struct rx8130ce_data *data = dev->data;
+	uint8_t offset;
+	*freq_ppb = 0;
+
+	k_sem_take(&data->lock, K_FOREVER);
+	rc = i2c_burst_read_dt(&cfg->i2c, OFFSET, &offset, sizeof(offset));
+	if (rc != 0) {
+		LOG_ERR("Failed to read calibration value");
+		goto exit;
+	}
+	/* Explanation see section 17 of the datasheet */
+	if (offset & DIGITAL_OFFSET_DTE) {
+		offset &= ~DIGITAL_OFFSET_DTE;
+		if (offset & DIGITAL_OFFSET_NEG) {
+			*freq_ppb = -((128 - offset) * DIGITAL_OFFSET_STEP_PPB);
+		} else {
+			*freq_ppb = offset * DIGITAL_OFFSET_STEP_PPB;
+		}
+	}
+	LOG_DBG("get calibration: offset = 0x%02x, freq_ppb = %d", offset, *freq_ppb);
+
+exit:
+	k_sem_give(&data->lock);
+	return rc;
+}
+#endif /* CONFIG_RTC_CALIBRATION */
+
+
+static int rx8130ce_init(const struct device *dev)
+{
+	int rc;
+	const struct rx8130ce_config *cfg = dev->config;
+	struct rx8130ce_data *data = dev->data;
+
+	data->dev = dev;
+	k_sem_init(&data->lock, 1, 1);
+	if (!i2c_is_ready_dt(&cfg->i2c)) {
+		LOG_ERR("I2C bus not ready");
+		return -ENODEV;
+	}
+
+	/* read all control registers */
+	rc = i2c_burst_read_dt(&cfg->i2c, EXTENSION, (uint8_t *)&data->reg, sizeof(data->reg));
+	if (rc != 0) {
+		LOG_ERR("Failed to read control registers");
+		return rc;
+	}
+	data->reg.flag = 0x00;
+	data->reg.extension &= ~EXT_TE;
+
+
+	switch (cfg->clockout_frequency) {
+	case 0: /* OFF */
+		data->reg.extension |= EXT_FSEL1 | EXT_FSEL0;
+		break;
+	case 1: /* 1 Hz */
+		data->reg.extension &= ~EXT_FSEL0;
+		data->reg.extension |= EXT_FSEL1;
+		break;
+	case 1024: /* 1.024 kHz */
+		data->reg.extension |= EXT_FSEL0;
+		data->reg.extension &= ~EXT_FSEL1;
+		break;
+	case 32768: /* 32.768 kHz */
+		data->reg.extension &= ~(EXT_FSEL1 | EXT_FSEL0);
+		break;
+	default:
+		LOG_ERR("Invalid clockout frequency option: %d", cfg->clockout_frequency);
+		return -EINVAL;
+	}
+
+	if (cfg->battery_switchover != 0) {
+		/* Enable initial voltage detection, following settings depend
+		 * on if the CTRL1_INIEN has been set prior (lifetime)
+		 */
+		data->reg.ctrl1 |= CTRL1_INIEN;
+		rc = i2c_burst_write_dt(&cfg->i2c, CTRL1,
+			  (uint8_t *)&data->reg.ctrl1, sizeof(data->reg.ctrl1));
+		if (rc != 0) {
+			LOG_ERR("Failed to write ctrl1 register");
+			return rc;
+		}
+	}
+
+	switch (cfg->battery_switchover) {
+	case 1: /* Power switch on, non rechargeable battery */
+		data->reg.ctrl1 |= CTRL1_INIEN;
+		break;
+	case 2: /* Power switch on, rechargeable battery */
+		data->reg.ctrl1 &= ~(CTRL1_INIEN | CTRL1_CHGEN);
+		break;
+	case 3: /* Power switch on, rechargeable battery, i2c & Fout disabled if VDD < Vdet1 */
+		data->reg.ctrl1 |= CTRL1_CHGEN | CTRL1_INIEN;
+		break;
+	case 4: /* Power switch on, rechargeable battery, i2c & Fout always enabled */
+		data->reg.ctrl1 |= CTRL1_CHGEN;
+		data->reg.ctrl1 &= ~CTRL1_INIEN;
+		break;
+	}
+
+#if defined(CONFIG_RTC_ALARM) || defined(CONFIG_RTC_UPDATE)
+	k_work_init(&data->irq_work, rx8130ce_irq_work_handler);
+	if (cfg->irq.port != NULL) {
+		gpio_pin_configure_dt(&cfg->irq, GPIO_INPUT);
+		gpio_init_callback(&data->irq_cb, rx8130ce_irq, BIT(cfg->irq.pin));
+		rc = gpio_add_callback_dt(&cfg->irq, &data->irq_cb);
+		if (rc != 0) {
+			LOG_ERR("Failed to add callback");
+			return rc;
+		}
+	}
+#endif /* CONFIG_RTC_ALARM || CONFIG_RTC_UPDATE */
+	rc = i2c_burst_write_dt(&cfg->i2c, EXTENSION, (uint8_t *)&data->reg, sizeof(data->reg));
+	if (rc != 0) {
+		LOG_ERR("Failed to write control registers");
+		return rc;
+	}
+	return 0;
+}
+static DEVICE_API(rtc, rx8130ce_driver_api) = {
+	.set_time = rx8130ce_set_time,
+	.get_time = rx8130ce_get_time,
+#ifdef CONFIG_RTC_ALARM
+	.alarm_get_supported_fields = rx8130ce_alarm_get_supported_fields,
+	.alarm_set_time = rx8130ce_alarm_set_time,
+	.alarm_get_time = rx8130ce_alarm_get_time,
+	.alarm_is_pending = rx8130ce_alarm_is_pending,
+	.alarm_set_callback = rx8130ce_alarm_set_callback,
+#endif /* CONFIG_RTC_ALARM */
+#ifdef CONFIG_RTC_UPDATE
+	.update_set_callback = rx8130ce_update_set_callback,
+#endif /* CONFIG_RTC_UPDATE */
+#ifdef CONFIG_RTC_CALIBRATION
+	.set_calibration = rx8130ce_set_calibration,
+	.get_calibration = rx8130ce_get_calibration,
+#endif /* CONFIG_RTC_CALIBRATION */
+};
+
+#define RX8130CE_INIT(inst)									\
+	static const struct rx8130ce_config rx8130ce_config_##inst = {				\
+		.i2c = I2C_DT_SPEC_INST_GET(inst),						\
+		.clockout_frequency = DT_INST_PROP_OR(inst, clockout_frequency, 0),		\
+		.battery_switchover = DT_INST_PROP_OR(inst, battery_switchover, 0),		\
+		.irq = GPIO_DT_SPEC_INST_GET_OR(inst, irq_gpios, {0}),				\
+	};											\
+												\
+	static struct rx8130ce_data rx8130ce_data_##inst;					\
+												\
+	DEVICE_DT_INST_DEFINE(inst, &rx8130ce_init, NULL,					\
+			      &rx8130ce_data_##inst, &rx8130ce_config_##inst, POST_KERNEL,	\
+			      CONFIG_RTC_INIT_PRIORITY, &rx8130ce_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(RX8130CE_INIT)
diff --git a/drivers/rtc/rtc_sam0.c b/drivers/rtc/rtc_sam0.c
new file mode 100644
index 00000000000..a6dc578a01d
--- /dev/null
+++ b/drivers/rtc/rtc_sam0.c
@@ -0,0 +1,641 @@
+/*
+ * Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT atmel_sam0_rtc
+
+/** @file
+ * @brief RTC driver for Atmel SAM0 MCU family.
+ */
+
+#include <stdlib.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/rtc.h>
+#include "rtc_utils.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(rtc_sam0, CONFIG_RTC_LOG_LEVEL);
+
+/* clang-format off */
+
+#define RTC_SAM0_TIME_MASK		\
+	(RTC_ALARM_TIME_MASK_SECOND	\
+	| RTC_ALARM_TIME_MASK_MINUTE	\
+	| RTC_ALARM_TIME_MASK_HOUR	\
+	| RTC_ALARM_TIME_MASK_MONTHDAY	\
+	| RTC_ALARM_TIME_MASK_MONTH	\
+	| RTC_ALARM_TIME_MASK_YEAR	\
+	)
+
+#define RTC_SAM0_CALIBRATE_PPB_MAX	(127)
+#define RTC_SAM0_CALIBRATE_PPB_QUANTA	(1000)
+
+enum rtc_sam0_counter_mode {
+	COUNTER_MODE_0,
+	COUNTER_MODE_1,
+	COUNTER_MODE_2,
+};
+
+struct rtc_sam0_config {
+	Rtc *regs;
+	enum rtc_sam0_counter_mode mode;
+	uint16_t prescaler;
+
+	volatile uint32_t *mclk;
+	uint32_t mclk_mask;
+	uint32_t gclk_gen;
+	uint16_t gclk_id;
+	bool has_gclk;
+	bool has_osc32kctrl;
+	uint8_t osc32_src;
+	uint32_t evt_ctrl_msk;
+
+#ifdef CONFIG_RTC_ALARM
+	uint8_t alarms_count;
+#endif /* CONFIG_RTC_ALARM */
+#ifdef CONFIG_RTC_CALIBRATION
+	int32_t cal_constant;
+#endif
+};
+
+struct rtc_sam0_data_cb {
+	rtc_alarm_callback cb;
+	void *cb_data;
+};
+
+struct rtc_sam0_data {
+	struct k_spinlock lock;
+#ifdef CONFIG_RTC_ALARM
+	struct rtc_sam0_data_cb *const alarms;
+#endif /* CONFIG_RTC_ALARM */
+};
+
+static inline void rtc_sam0_sync(Rtc *rtc)
+{
+	/* Wait for synchronization */
+#ifdef MCLK
+	while (rtc->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_MASK) {
+	}
+#else
+	while (rtc->MODE0.STATUS.reg & RTC_STATUS_SYNCBUSY) {
+	}
+#endif
+}
+
+static int rtc_sam0_set_time(const struct device *dev, const struct rtc_time *timeptr)
+{
+	const struct rtc_sam0_config *cfg = dev->config;
+	struct rtc_sam0_data *data = dev->data;
+	RtcMode2 *regs = &cfg->regs->MODE2;
+	uint32_t datetime = 0;
+
+	if (rtc_utils_validate_rtc_time(timeptr, RTC_SAM0_TIME_MASK) == false) {
+		return -EINVAL;
+	}
+
+	datetime |= RTC_MODE2_CLOCK_SECOND(timeptr->tm_sec);
+	datetime |= RTC_MODE2_CLOCK_MINUTE(timeptr->tm_min);
+	datetime |= RTC_MODE2_CLOCK_HOUR(timeptr->tm_hour);
+	datetime |= RTC_MODE2_CLOCK_DAY(timeptr->tm_mday);
+	datetime |= RTC_MODE2_CLOCK_MONTH(timeptr->tm_mon + 1);
+	datetime |= RTC_MODE2_CLOCK_YEAR(timeptr->tm_year - 99);
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+#ifdef MCLK
+	regs->CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE;
+	rtc_sam0_sync(cfg->regs);
+	regs->CLOCK.reg = datetime;
+	regs->CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE;
+#else
+	regs->CTRL.reg &= ~RTC_MODE0_CTRL_ENABLE;
+	rtc_sam0_sync(cfg->regs);
+	regs->CLOCK.reg = datetime;
+	regs->CTRL.reg |= RTC_MODE0_CTRL_ENABLE;
+#endif
+
+	k_spin_unlock(&data->lock, key);
+
+	return 0;
+}
+
+static int rtc_sam0_get_time(const struct device *dev, struct rtc_time *timeptr)
+{
+	const struct rtc_sam0_config *cfg = dev->config;
+	RTC_MODE2_CLOCK_Type calendar = cfg->regs->MODE2.CLOCK;
+
+	timeptr->tm_sec = calendar.bit.SECOND;
+	timeptr->tm_min = calendar.bit.MINUTE;
+	timeptr->tm_hour = calendar.bit.HOUR;
+	timeptr->tm_mday = calendar.bit.DAY;
+	timeptr->tm_mon = calendar.bit.MONTH - 1;
+	timeptr->tm_year = calendar.bit.YEAR + 99;
+	timeptr->tm_wday = -1;
+	timeptr->tm_yday = -1;
+	timeptr->tm_isdst = -1;
+	timeptr->tm_nsec = 0;
+
+	LOG_DBG("D/M/Y H:M:S %02d/%02d/%02d %02d:%02d:%02d",
+		timeptr->tm_mday, timeptr->tm_mon + 1, timeptr->tm_year - 99,
+		timeptr->tm_hour, timeptr->tm_min, timeptr->tm_sec);
+
+	return 0;
+}
+
+#ifdef CONFIG_RTC_ALARM
+static inline uint32_t rtc_sam0_datetime_from_tm(const struct rtc_time *timeptr,
+						 uint32_t mask)
+{
+	uint32_t datetime = 0;
+
+	if (mask & RTC_ALARM_TIME_MASK_SECOND) {
+		datetime |= RTC_MODE2_CLOCK_SECOND(timeptr->tm_sec);
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
+		datetime |= RTC_MODE2_CLOCK_MINUTE(timeptr->tm_min);
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_HOUR) {
+		datetime |= RTC_MODE2_CLOCK_HOUR(timeptr->tm_hour);
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
+		datetime |= RTC_MODE2_CLOCK_DAY(timeptr->tm_mday);
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_MONTH) {
+		datetime |= RTC_MODE2_CLOCK_MONTH(timeptr->tm_mon + 1);
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_YEAR) {
+		datetime |= RTC_MODE2_CLOCK_YEAR(timeptr->tm_year - 99);
+	}
+
+	return datetime;
+}
+
+static inline void rtc_sam0_tm_from_datetime(struct rtc_time *timeptr, uint32_t mask,
+					     RTC_MODE2_ALARM_Type calendar)
+{
+	memset(timeptr, 0x00, sizeof(struct rtc_time));
+
+	if (mask & RTC_ALARM_TIME_MASK_SECOND) {
+		timeptr->tm_sec = calendar.bit.SECOND;
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
+		timeptr->tm_min = calendar.bit.MINUTE;
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_HOUR) {
+		timeptr->tm_hour = calendar.bit.HOUR;
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
+		timeptr->tm_mday = calendar.bit.DAY;
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_MONTH) {
+		timeptr->tm_mon = calendar.bit.MONTH - 1;
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_YEAR) {
+		timeptr->tm_year = calendar.bit.YEAR + 99;
+	}
+
+	timeptr->tm_wday = -1;
+	timeptr->tm_yday = -1;
+	timeptr->tm_isdst = -1;
+	timeptr->tm_nsec = 0;
+}
+
+static inline uint32_t rtc_sam0_alarm_msk_from_mask(uint32_t mask)
+{
+	uint32_t alarm_mask = 0;
+
+	if (mask & RTC_ALARM_TIME_MASK_SECOND) {
+		alarm_mask = RTC_MODE2_MASK_SEL_SS_Val;
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_MINUTE) {
+		alarm_mask = RTC_MODE2_MASK_SEL_MMSS_Val;
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_HOUR) {
+		alarm_mask = RTC_MODE2_MASK_SEL_HHMMSS_Val;
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_MONTHDAY) {
+		alarm_mask = RTC_MODE2_MASK_SEL_DDHHMMSS_Val;
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_MONTH) {
+		alarm_mask = RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val;
+	}
+
+	if (mask & RTC_ALARM_TIME_MASK_YEAR) {
+		alarm_mask = RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val;
+	}
+
+	return alarm_mask;
+}
+
+static inline uint32_t rtc_sam0_mask_from_alarm_msk(uint32_t alarm_mask)
+{
+	uint32_t mask = 0;
+
+	switch (alarm_mask) {
+	case RTC_MODE2_MASK_SEL_YYMMDDHHMMSS_Val:
+		mask |= RTC_ALARM_TIME_MASK_YEAR;
+		__fallthrough;
+	case RTC_MODE2_MASK_SEL_MMDDHHMMSS_Val:
+		mask |= RTC_ALARM_TIME_MASK_MONTH;
+		__fallthrough;
+	case RTC_MODE2_MASK_SEL_DDHHMMSS_Val:
+		mask |= RTC_ALARM_TIME_MASK_MONTHDAY;
+		__fallthrough;
+	case RTC_MODE2_MASK_SEL_HHMMSS_Val:
+		mask |= RTC_ALARM_TIME_MASK_HOUR;
+		__fallthrough;
+	case RTC_MODE2_MASK_SEL_MMSS_Val:
+		mask |= RTC_ALARM_TIME_MASK_MINUTE;
+		__fallthrough;
+	case RTC_MODE2_MASK_SEL_SS_Val:
+		mask |= RTC_ALARM_TIME_MASK_SECOND;
+		break;
+	default:
+		break;
+	}
+
+	return mask;
+}
+
+static int rtc_sam0_alarm_get_supported_fields(const struct device *dev, uint16_t id,
+					       uint16_t *mask)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(id);
+
+	*mask = RTC_SAM0_TIME_MASK;
+
+	return 0;
+}
+
+static int rtc_sam0_alarm_set_time(const struct device *dev, uint16_t id, uint16_t mask,
+				   const struct rtc_time *timeptr)
+{
+	const struct rtc_sam0_config *cfg = dev->config;
+	struct rtc_sam0_data *data = dev->data;
+	RtcMode2 *regs = &cfg->regs->MODE2;
+	uint32_t mask_supported = RTC_SAM0_TIME_MASK;
+	uint32_t datetime;
+	uint32_t alarm_msk;
+
+	if (BIT(id) > RTC_MODE2_INTFLAG_ALARM_Msk) {
+		return -EINVAL;
+	}
+
+	if ((mask > 0) && (timeptr == NULL)) {
+		return -EINVAL;
+	}
+
+	if (mask & ~mask_supported) {
+		return -EINVAL;
+	}
+
+	if (rtc_utils_validate_rtc_time(timeptr, mask) == false) {
+		return -EINVAL;
+	}
+
+	datetime = rtc_sam0_datetime_from_tm(timeptr, mask);
+	alarm_msk = rtc_sam0_alarm_msk_from_mask(mask);
+
+	LOG_DBG("S: datetime: %d, mask: %d", datetime, alarm_msk);
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	irq_disable(DT_INST_IRQN(0));
+
+	rtc_sam0_sync(cfg->regs);
+	regs->Mode2Alarm[id].ALARM.reg = datetime;
+	regs->Mode2Alarm[id].MASK.reg = RTC_MODE2_MASK_SEL(alarm_msk);
+	regs->INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(BIT(id));
+
+	irq_enable(DT_INST_IRQN(0));
+
+	k_spin_unlock(&data->lock, key);
+
+	return 0;
+}
+
+static int rtc_sam0_alarm_get_time(const struct device *dev, uint16_t id, uint16_t *mask,
+				   struct rtc_time *timeptr)
+{
+	const struct rtc_sam0_config *cfg = dev->config;
+	struct rtc_sam0_data *data = dev->data;
+	RtcMode2 *regs = &cfg->regs->MODE2;
+	RTC_MODE2_ALARM_Type datetime;
+	uint32_t alarm_msk;
+
+	if (BIT(id) > RTC_MODE2_INTFLAG_ALARM_Msk) {
+		return -EINVAL;
+	}
+
+	if ((mask == NULL) || (timeptr == NULL)) {
+		return -EINVAL;
+	}
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	rtc_sam0_sync(cfg->regs);
+
+	datetime = regs->Mode2Alarm[id].ALARM;
+	alarm_msk = regs->Mode2Alarm[id].MASK.reg;
+
+	LOG_DBG("G: datetime: %d, mask: %d", datetime.reg, alarm_msk);
+
+	k_spin_unlock(&data->lock, key);
+
+	*mask = rtc_sam0_mask_from_alarm_msk(alarm_msk);
+
+	rtc_sam0_tm_from_datetime(timeptr, *mask, datetime);
+
+	return 0;
+}
+
+static int rtc_sam0_alarm_is_pending(const struct device *dev, uint16_t id)
+{
+	const struct rtc_sam0_config *cfg = dev->config;
+	struct rtc_sam0_data *data = dev->data;
+	RtcMode2 *regs = &cfg->regs->MODE2;
+
+	if (BIT(id) > RTC_MODE2_INTFLAG_ALARM_Msk) {
+		return -EINVAL;
+	}
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	if ((regs->INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM(BIT(id))) == 0) {
+		k_spin_unlock(&data->lock, key);
+
+		return 0;
+	}
+
+	regs->INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM(BIT(id));
+
+	k_spin_unlock(&data->lock, key);
+
+	return 1;
+}
+
+static int rtc_sam0_alarm_set_callback(const struct device *dev, uint16_t id,
+				       rtc_alarm_callback callback, void *user_data)
+{
+	const struct rtc_sam0_config *cfg = dev->config;
+	struct rtc_sam0_data *data = dev->data;
+	RtcMode2 *regs = &cfg->regs->MODE2;
+
+	if (BIT(id) > RTC_MODE2_INTFLAG_ALARM_Msk) {
+		return -EINVAL;
+	}
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	data->alarms[id].cb = callback;
+	data->alarms[id].cb_data = user_data;
+
+	if (callback) {
+		regs->INTENSET.reg = RTC_MODE2_INTENSET_ALARM(BIT(id));
+	} else {
+		regs->INTENCLR.reg = RTC_MODE2_INTENCLR_ALARM(BIT(id));
+	}
+
+	k_spin_unlock(&data->lock, key);
+
+	return 0;
+}
+
+static void rtc_sam0_isr(const struct device *dev)
+{
+	const struct rtc_sam0_config *cfg = dev->config;
+	struct rtc_sam0_data *data = dev->data;
+	RtcMode2 *regs = &cfg->regs->MODE2;
+	uint32_t int_flags = regs->INTFLAG.reg;
+
+	for (int i = 0; i < cfg->alarms_count; ++i) {
+		if (int_flags & RTC_MODE2_INTFLAG_ALARM(BIT(i))) {
+			if (data->alarms[i].cb != NULL) {
+				data->alarms[i].cb(dev, i, data->alarms[i].cb_data);
+			}
+		}
+	}
+
+	regs->INTFLAG.reg |= int_flags;
+}
+
+#endif /* CONFIG_RTC_ALARM */
+
+#ifdef CONFIG_RTC_CALIBRATION
+static int rtc_sam0_set_calibration(const struct device *dev, int32_t calibration)
+{
+	const struct rtc_sam0_config *cfg = dev->config;
+	RtcMode2 *regs = &cfg->regs->MODE2;
+	int32_t correction = calibration / (1000000000 / cfg->cal_constant);
+	uint32_t abs_correction = abs(correction);
+
+	LOG_DBG("Correction: %d, Absolute: %d, Calibration: %d",
+		correction, abs_correction, calibration);
+
+	if (abs_correction == 0) {
+		regs->FREQCORR.reg = 0;
+		return 0;
+	}
+
+	if (abs_correction > RTC_SAM0_CALIBRATE_PPB_MAX) {
+		LOG_ERR("The calibration %d result in an out of range value %d",
+			calibration, abs_correction);
+		return -EINVAL;
+	}
+
+	rtc_sam0_sync(cfg->regs);
+	regs->FREQCORR.reg = RTC_FREQCORR_VALUE(abs_correction)
+			   | (correction < 0 ? RTC_FREQCORR_SIGN : 0);
+
+	LOG_DBG("W REG: 0x%02x", regs->FREQCORR.reg);
+
+	return 0;
+}
+
+static int rtc_sam0_get_calibration(const struct device *dev, int32_t *calibration)
+{
+	const struct rtc_sam0_config *cfg = dev->config;
+	RtcMode2 *regs = &cfg->regs->MODE2;
+	int32_t correction;
+
+	if (calibration == NULL) {
+		return -EINVAL;
+	}
+
+	correction = regs->FREQCORR.bit.VALUE;
+
+	if (correction == 0) {
+		*calibration = 0;
+	} else {
+		*calibration = (correction * 1000000000) / cfg->cal_constant;
+	}
+
+	if (regs->FREQCORR.bit.SIGN) {
+		*calibration *= -1;
+	}
+
+	LOG_DBG("R REG: 0x%02x", regs->FREQCORR.reg);
+
+	return 0;
+}
+#endif /* CONFIG_RTC_CALIBRATION */
+
+static int rtc_sam0_init(const struct device *dev)
+{
+	const struct rtc_sam0_config *cfg = dev->config;
+	RtcMode0 *regs = &cfg->regs->MODE0;
+
+	LOG_DBG("Counter Mode %d selected", cfg->mode);
+	LOG_DBG("gclk_id: %d, gclk_gen: %d, prescaler: %d, osc32k: %d",
+		cfg->gclk_id, cfg->gclk_gen, cfg->prescaler, cfg->osc32_src);
+
+	*cfg->mclk |= cfg->mclk_mask;
+
+#ifdef MCLK
+	if (cfg->has_gclk) {
+		GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_CHEN
+						| GCLK_PCHCTRL_GEN(cfg->gclk_gen);
+	}
+#else
+	GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
+			  | GCLK_CLKCTRL_GEN(cfg->gclk_gen)
+			  | GCLK_CLKCTRL_ID(cfg->gclk_id);
+#endif
+	rtc_sam0_sync(cfg->regs);
+
+#ifdef MCLK
+	if (cfg->has_osc32kctrl) {
+		OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL(cfg->osc32_src);
+	}
+#endif
+
+	rtc_sam0_sync(cfg->regs);
+	regs->EVCTRL.reg = (cfg->evt_ctrl_msk & RTC_MODE0_EVCTRL_MASK);
+
+#ifdef MCLK
+	regs->CTRLA.reg = RTC_MODE0_CTRLA_ENABLE
+			| RTC_MODE0_CTRLA_COUNTSYNC
+			| RTC_MODE0_CTRLA_MODE(cfg->mode)
+			| RTC_MODE0_CTRLA_PRESCALER(cfg->prescaler + 1);
+#else
+	regs->CTRL.reg = RTC_MODE0_CTRL_ENABLE
+		       | RTC_MODE0_CTRL_MODE(cfg->mode)
+		       | RTC_MODE0_CTRL_PRESCALER(cfg->prescaler);
+#endif
+
+	regs->INTFLAG.reg = 0;
+#ifdef CONFIG_RTC_ALARM
+	IRQ_CONNECT(DT_INST_IRQN(0),
+		    DT_INST_IRQ(0, priority),
+		    rtc_sam0_isr,
+		    DEVICE_DT_INST_GET(0), 0);
+	irq_enable(DT_INST_IRQN(0));
+#endif
+	return 0;
+}
+
+static DEVICE_API(rtc, rtc_sam0_driver_api) = {
+	.set_time = rtc_sam0_set_time,
+	.get_time = rtc_sam0_get_time,
+#ifdef CONFIG_RTC_ALARM
+	.alarm_get_supported_fields = rtc_sam0_alarm_get_supported_fields,
+	.alarm_set_time = rtc_sam0_alarm_set_time,
+	.alarm_get_time = rtc_sam0_alarm_get_time,
+	.alarm_is_pending = rtc_sam0_alarm_is_pending,
+	.alarm_set_callback = rtc_sam0_alarm_set_callback,
+#endif /* CONFIG_RTC_ALARM */
+#ifdef CONFIG_RTC_CALIBRATION
+	.set_calibration = rtc_sam0_set_calibration,
+	.get_calibration = rtc_sam0_get_calibration,
+#endif /* CONFIG_RTC_CALIBRATION */
+};
+
+#define ASSIGNED_CLOCKS_CELL_BY_NAME							\
+	ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_NAME
+
+#define RTC_SAM0_GCLK(n)								\
+	COND_CODE_1(DT_INST_CLOCKS_HAS_NAME(n, gclk),					\
+	(										\
+		.has_gclk = true,							\
+		.gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen),			\
+		.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id)			\
+	),										\
+	(										\
+		.has_gclk = false,							\
+		.gclk_gen = 0,								\
+		.gclk_id = 0								\
+	))
+
+#define RTC_SAM0_OSC32KCTRL(n)								\
+	COND_CODE_1(DT_INST_CLOCKS_HAS_NAME(n, osc32kctrl),				\
+	(										\
+		.has_osc32kctrl = true,							\
+		.osc32_src = ASSIGNED_CLOCKS_CELL_BY_NAME(n, osc32kctrl, src)		\
+	),										\
+	(										\
+		.has_osc32kctrl = false,						\
+		.osc32_src = 0								\
+	))
+
+#define RTC_SAM0_DEVICE(n)								\
+	BUILD_ASSERT(DT_INST_NODE_HAS_PROP(n, counter_mode),				\
+	"sam0:rtc: Missing counter-mode devicetree property");				\
+	BUILD_ASSERT(DT_INST_NODE_HAS_PROP(n, prescaler),				\
+	"sam0:rtc: Missing prescaler devicetree property");				\
+											\
+	static const struct rtc_sam0_config rtc_sam0_config_##n = {			\
+		.regs = (Rtc *)DT_INST_REG_ADDR(n),					\
+		.mode = DT_INST_ENUM_IDX(n, counter_mode),				\
+		.prescaler = DT_INST_ENUM_IDX(n, prescaler),				\
+		.evt_ctrl_msk = DT_INST_PROP(n, event_control_msk),			\
+		RTC_SAM0_GCLK(n),							\
+		RTC_SAM0_OSC32KCTRL(n),							\
+		.mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n),			\
+		.mclk_mask = ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(n, bit),		\
+		IF_ENABLED(CONFIG_RTC_ALARM, (						\
+			.alarms_count = DT_INST_PROP(n, alarms_count),			\
+		))									\
+		IF_ENABLED(CONFIG_RTC_CALIBRATION, (					\
+			.cal_constant = DT_INST_PROP(n, cal_constant),			\
+		))									\
+	};										\
+											\
+	IF_ENABLED(CONFIG_RTC_ALARM, (							\
+		static struct rtc_sam0_data_cb						\
+			rtc_sam0_data_cb_##n[DT_INST_PROP(n, alarms_count)] = {};	\
+	))										\
+											\
+	static struct rtc_sam0_data rtc_sam0_data_##n = {				\
+		IF_ENABLED(CONFIG_RTC_ALARM, (						\
+			.alarms = rtc_sam0_data_cb_##n,					\
+		))									\
+	};										\
+											\
+	DEVICE_DT_INST_DEFINE(n, rtc_sam0_init,						\
+			      NULL,							\
+			      &rtc_sam0_data_##n,					\
+			      &rtc_sam0_config_##n, POST_KERNEL,			\
+			      CONFIG_RTC_INIT_PRIORITY,					\
+			      &rtc_sam0_driver_api);					\
+
+DT_INST_FOREACH_STATUS_OKAY(RTC_SAM0_DEVICE);
+
+/* clang-format on */
diff --git a/drivers/rtc/rtc_shell.c b/drivers/rtc/rtc_shell.c
index 93e53099890..2ea8ba3047d 100644
--- a/drivers/rtc/rtc_shell.c
+++ b/drivers/rtc/rtc_shell.c
@@ -217,9 +217,14 @@ static int cmd_get(const struct shell *sh, size_t argc, char **argv)
 	return 0;
 }
 
+static bool device_is_rtc(const struct device *dev)
+{
+	return DEVICE_API_IS(rtc, dev);
+}
+
 static void device_name_get(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_lookup(idx, NULL);
+	const struct device *dev = shell_device_filter(idx, device_is_rtc);
 
 	entry->syntax = (dev != NULL) ? dev->name : NULL;
 	entry->handler = NULL;
diff --git a/drivers/sdhc/CMakeLists.txt b/drivers/sdhc/CMakeLists.txt
index 269f1a419c0..589ba209eb3 100644
--- a/drivers/sdhc/CMakeLists.txt
+++ b/drivers/sdhc/CMakeLists.txt
@@ -13,4 +13,6 @@ zephyr_library_sources_ifdef(CONFIG_SDHC_INFINEON_CAT1 ifx_cat1_sdio.c)
 zephyr_library_sources_ifdef(CONFIG_CDNS_SDHC sdhc_cdns_ll.c sdhc_cdns.c)
 zephyr_library_sources_ifdef(CONFIG_SDHC_ESP32 sdhc_esp32.c)
 zephyr_library_sources_ifdef(CONFIG_SDHC_RENESAS_RA sdhc_renesas_ra.c)
+zephyr_library_sources_ifdef(CONFIG_SDHC_MAX32 sdhc_max32.c)
+zephyr_library_sources_ifdef(CONFIG_SDHC_AMBIQ sdhc_ambiq.c)
 endif()
diff --git a/drivers/sdhc/Kconfig b/drivers/sdhc/Kconfig
index 89fa669a5e5..3c8a7bd869c 100644
--- a/drivers/sdhc/Kconfig
+++ b/drivers/sdhc/Kconfig
@@ -2,9 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 menuconfig SDHC
-	bool "Secure Digital High Capacity (SDHC) drivers"
+	bool "Secure Digital (SD card) host controller drivers"
 	help
-	  Include drivers for SD host controller
+	  Include drivers for interacting with SD cards
 
 if SDHC
 
@@ -18,6 +18,8 @@ source "drivers/sdhc/Kconfig.intel"
 source "drivers/sdhc/Kconfig.sdhc_cdns"
 source "drivers/sdhc/Kconfig.esp32"
 source "drivers/sdhc/Kconfig.renesas_ra"
+source "drivers/sdhc/Kconfig.max32"
+source "drivers/sdhc/Kconfig.ambiq"
 
 config SDHC_INIT_PRIORITY
 	int "SDHC driver init priority"
diff --git a/drivers/sdhc/Kconfig.ambiq b/drivers/sdhc/Kconfig.ambiq
new file mode 100644
index 00000000000..44e465aca94
--- /dev/null
+++ b/drivers/sdhc/Kconfig.ambiq
@@ -0,0 +1,31 @@
+# Copyright (c) 2025 Ambiq Micro Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SDHC_AMBIQ
+	bool "Ambiq SDHC driver"
+	default y
+	depends on DT_HAS_AMBIQ_SDIO_ENABLED
+	select AMBIQ_HAL
+	select AMBIQ_HAL_USE_SDIO
+	select PINCTRL
+	select GPIO
+	select SDHC_SUPPORTS_NATIVE_MODE
+	help
+	  This option enables the SDHC driver for Ambiq Apollo family.
+
+if SDHC_AMBIQ
+
+config AMBIQ_SDIO_ASYNC
+	bool "Ambiq SDIO Async Mode"
+	default y
+	depends on DT_HAS_AMBIQ_SDIO_ENABLED
+	help
+	  This option enables Ambiq SDIO Async Mode.
+
+config SDHC_BUFFER_ALIGNMENT
+	default 32 if DCACHE
+	default 16
+	help
+	  SDHC buffer should be 32bytes aligned when placed in cachable region.
+
+endif
diff --git a/drivers/sdhc/Kconfig.max32 b/drivers/sdhc/Kconfig.max32
new file mode 100644
index 00000000000..71212042ae1
--- /dev/null
+++ b/drivers/sdhc/Kconfig.max32
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SDHC_MAX32
+	bool "Analog Devices MAX32 SDHC driver"
+	default y
+	depends on DT_HAS_ADI_MAX32_SDHC_ENABLED
+	select SDHC_SUPPORTS_NATIVE_MODE
+	help
+	  sdhc driver for max32 family.
diff --git a/drivers/sdhc/ifx_cat1_sdio.c b/drivers/sdhc/ifx_cat1_sdio.c
index 537b68e3395..4449b532f0b 100644
--- a/drivers/sdhc/ifx_cat1_sdio.c
+++ b/drivers/sdhc/ifx_cat1_sdio.c
@@ -47,6 +47,7 @@
 #include <soc.h>
 #include <zephyr/drivers/pinctrl.h>
 
+#include <cyhal_hw_resources.h>
 #include <cyhal_sdhc.h>
 #include <cyhal_sdio.h>
 #include <cyhal_gpio.h>
@@ -283,13 +284,21 @@ static int ifx_cat1_sdio_init(const struct device *dev)
 	}
 
 	/* Dedicate SDIO HW resource */
-	data->hw_resource.type = CYHAL_RSC_SDIODEV;
+	data->hw_resource.type = CYHAL_RSC_SDHC;
 	data->hw_resource.block_num = _get_hw_block_num(config->reg_addr);
+	data->hw_resource.channel_num = 0;
 
 	/* Initialize the SDIO peripheral */
 	data->cyhal_sdio_config.resource = &data->hw_resource;
 	data->cyhal_sdio_config.host_config = &host_config,
 	data->cyhal_sdio_config.card_config = &sd_host_sd_card_config,
+	data->cyhal_sdio_config.gpios.cmd = NC;
+	data->cyhal_sdio_config.gpios.clk = NC;
+	data->cyhal_sdio_config.gpios.data[0] = NC;
+	data->cyhal_sdio_config.gpios.data[1] = NC;
+	data->cyhal_sdio_config.gpios.data[2] = NC;
+	data->cyhal_sdio_config.gpios.data[3] = NC;
+	data->cyhal_sdio_config.clock = NULL;
 
 	ret = cyhal_sdio_init_cfg(&data->sdio_obj, &data->cyhal_sdio_config);
 	if (ret != CY_RSLT_SUCCESS) {
diff --git a/drivers/sdhc/intel_emmc_host.c b/drivers/sdhc/intel_emmc_host.c
index 0b0695ffecb..2ac32d82898 100644
--- a/drivers/sdhc/intel_emmc_host.c
+++ b/drivers/sdhc/intel_emmc_host.c
@@ -417,7 +417,7 @@ static int emmc_dma_init(const struct device *dev, struct sdhc_data *data, bool
 	if (IS_ENABLED(CONFIG_INTEL_EMMC_HOST_ADMA)) {
 		uint8_t *buff = data->data;
 
-		/* Setup DMA trasnfer using ADMA2 */
+		/* Setup DMA transfer using ADMA2 */
 		memset(emmc->desc_table, 0, sizeof(emmc->desc_table));
 
 #if defined(CONFIG_INTEL_EMMC_HOST_ADMA_DESC_SIZE)
@@ -446,7 +446,7 @@ static int emmc_dma_init(const struct device *dev, struct sdhc_data *data, bool
 		LOG_DBG("adma: %llx %x %p", emmc->desc_table[0], regs->adma_sys_addr1,
 			emmc->desc_table);
 	} else {
-		/* Setup DMA trasnfer using SDMA */
+		/* Setup DMA transfer using SDMA */
 		regs->sdma_sysaddr = (uint32_t)((uintptr_t)data->data);
 		LOG_DBG("sdma_sysaddr: %x", regs->sdma_sysaddr);
 	}
diff --git a/drivers/sdhc/sdhc_ambiq.c b/drivers/sdhc/sdhc_ambiq.c
new file mode 100644
index 00000000000..b58949a8557
--- /dev/null
+++ b/drivers/sdhc/sdhc_ambiq.c
@@ -0,0 +1,828 @@
+/*
+ * Copyright (c) 2025 Ambiq Micro Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ambiq_sdio
+
+#include <zephyr/devicetree.h>
+#include <zephyr/kernel.h>
+#include <zephyr/cache.h>
+#include <zephyr/irq.h>
+#include <zephyr/drivers/sdhc.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/pm/device.h>
+#include <zephyr/pm/policy.h>
+#include <zephyr/pm/device_runtime.h>
+
+#include <soc.h>
+
+LOG_MODULE_REGISTER(ambiq_sdio, CONFIG_SDHC_LOG_LEVEL);
+
+#define CACHABLE_START_ADDR SSRAM_BASEADDR
+
+struct ambiq_sdio_config {
+	SDIO_Type *pSDHC;
+	const struct pinctrl_dev_config *pincfg;
+	void (*irq_config_func)(const struct device *dev);
+	uint32_t inst;
+	uint8_t tx_delay;
+	uint8_t rx_delay;
+	uint32_t max_bus_freq;
+	uint32_t min_bus_freq;
+	uint32_t power_delay_ms;
+};
+
+struct ambiq_sdio_data {
+	am_hal_card_t card;
+	am_hal_card_host_t *host;
+	sdhc_interrupt_cb_t sdio_cb;
+	void *sdio_cb_user_data;
+	struct k_mutex access_mutex;
+#ifdef CONFIG_AMBIQ_SDIO_ASYNC
+	struct k_sem *async_sem;
+#endif /* CONFIG_AMBIQ_SDIO_ASYNC */
+};
+
+#ifdef CONFIG_AMBIQ_SDIO_ASYNC
+/* Semaphore for SDIO0 Async Data Transfer */
+static K_SEM_DEFINE(sdio_async_sem_0, 0, 1);
+
+/*
+ * SDIO0 Async Data Transfer Callback Function
+ */
+static void ambiq_sdio_event_cb_0(am_hal_host_evt_t *pEvt)
+{
+	am_hal_card_host_t *pHost = (am_hal_card_host_t *)pEvt->pCtx;
+
+	if (AM_HAL_EVT_XFER_COMPLETE == pEvt->eType &&
+	    pHost->AsyncCmdData.dir == AM_HAL_DATA_DIR_READ) {
+		LOG_DBG("Last Read Xfered block %d\n", pEvt->ui32BlkCnt);
+		k_sem_give(&sdio_async_sem_0);
+	} else if (AM_HAL_EVT_XFER_COMPLETE == pEvt->eType &&
+		   pHost->AsyncCmdData.dir == AM_HAL_DATA_DIR_WRITE) {
+		LOG_DBG("Last Write Xfered block %d\n", pEvt->ui32BlkCnt);
+		k_sem_give(&sdio_async_sem_0);
+	} else if (AM_HAL_EVT_CARD_INT == pEvt->eType) {
+		LOG_DBG("SDIO Card Interrupt\n");
+	}
+}
+
+/* Semaphore for SDIO1 Async Data Transfer */
+static K_SEM_DEFINE(sdio_async_sem_1, 0, 1);
+
+/*
+ * SDIO1 Async Data Transfer Callback Function
+ */
+static void ambiq_sdio_event_cb_1(am_hal_host_evt_t *pEvt)
+{
+	am_hal_card_host_t *pHost = (am_hal_card_host_t *)pEvt->pCtx;
+
+	if (AM_HAL_EVT_XFER_COMPLETE == pEvt->eType &&
+	    pHost->AsyncCmdData.dir == AM_HAL_DATA_DIR_READ) {
+		LOG_DBG("Last Read Xfered block %d\n", pEvt->ui32BlkCnt);
+		k_sem_give(&sdio_async_sem_1);
+	} else if (AM_HAL_EVT_XFER_COMPLETE == pEvt->eType &&
+		   pHost->AsyncCmdData.dir == AM_HAL_DATA_DIR_WRITE) {
+		LOG_DBG("Last Write Xfered block %d\n", pEvt->ui32BlkCnt);
+		k_sem_give(&sdio_async_sem_1);
+	} else if (AM_HAL_EVT_CARD_INT == pEvt->eType) {
+		LOG_DBG("SDIO Card Interrupt\n");
+	}
+}
+#endif /* CONFIG_AMBIQ_SDIO_ASYNC */
+
+/*
+ * Ambiq SDIO interrupt service routine
+ */
+static void ambiq_sdio_isr(const struct device *dev)
+{
+	uint32_t ui32IntStatus;
+	struct ambiq_sdio_data *data = dev->data;
+
+	am_hal_sdhc_intr_status_get(data->host->pHandle, &ui32IntStatus, true);
+	am_hal_sdhc_intr_status_clear(data->host->pHandle, ui32IntStatus);
+	am_hal_sdhc_interrupt_service(data->host->pHandle, ui32IntStatus);
+	if (data->sdio_cb != NULL && data->host->Evt.eType == AM_HAL_EVT_CARD_INT) {
+		data->sdio_cb(dev, SDHC_INT_SDIO, data->sdio_cb_user_data);
+	}
+}
+
+/*
+ * Ambiq SDIO host controller software reset
+ */
+static int ambiq_sdio_reset(const struct device *dev)
+{
+	const struct ambiq_sdio_config *config = dev->config;
+	uint32_t ui32Status = 0;
+	int ret = 0;
+
+#if defined(CONFIG_PM_DEVICE_RUNTIME)
+	ret = pm_device_runtime_get(dev);
+
+	if (ret < 0) {
+		LOG_ERR("pm_device_runtime_get failed: %d", ret);
+	}
+#endif /* CONFIG_PM_DEVICE_RUNTIME */
+
+	LOG_DBG("SDHC Software Reset");
+	ui32Status = am_hal_sdhc_software_reset(config->pSDHC, AM_HAL_SDHC_SW_RESET_ALL);
+	if (ui32Status) {
+		LOG_ERR("SDHC software reset failed, ui32Status = %u", ui32Status);
+		ret = -EIO;
+	}
+
+#if defined(CONFIG_PM_DEVICE_RUNTIME)
+	/* Use async put to avoid useless device suspension/resumption
+	 * when doing consecutive transmission.
+	 */
+	ret = pm_device_runtime_put_async(dev, K_MSEC(2));
+
+	if (ret < 0) {
+		LOG_ERR("pm_device_runtime_put failed: %d", ret);
+	}
+#endif /* CONFIG_PM_DEVICE_RUNTIME */
+
+	return ret;
+}
+
+/*
+ * Get Ambiq SDIO Host controller properties
+ */
+static int ambiq_sdio_get_host_props(const struct device *dev, struct sdhc_host_props *props)
+{
+	const struct ambiq_sdio_config *config = dev->config;
+
+	LOG_DBG("SDHC get host props");
+	memset(props, 0, sizeof(*props));
+	props->f_max = config->max_bus_freq;
+	props->f_min = config->min_bus_freq;
+	props->power_delay = config->power_delay_ms;
+	props->host_caps.suspend_res_support = true;
+	props->host_caps.adma_2_support = true;
+	props->host_caps.sdio_async_interrupt_support = true;
+	props->host_caps.vol_180_support = true;
+	props->host_caps.bus_4_bit_support = true;
+	props->host_caps.bus_8_bit_support = true;
+	props->host_caps.high_spd_support = true;
+	props->host_caps.sdr50_support = true;
+	props->host_caps.sdr104_support = true;
+	props->host_caps.ddr50_support = true;
+	props->host_caps.hs200_support = true;
+	props->max_current_330 = 1020;
+	props->max_current_300 = 1020;
+	props->max_current_180 = 1020;
+	props->is_spi = false;
+	return 0;
+}
+
+/*
+ * Set I/O properties of SDIO host controller
+ */
+static int ambiq_sdio_set_io(const struct device *dev, struct sdhc_io *ios)
+{
+	const struct ambiq_sdio_config *config = dev->config;
+	struct ambiq_sdio_data *data = dev->data;
+	am_hal_host_bus_voltage_e eBusVoltage;
+	am_hal_host_bus_width_e eBusWidth;
+	am_hal_host_uhs_mode_e eUHSMode = AM_HAL_HOST_UHS_SDR50;
+	uint32_t ui32Status = 0;
+	int ret = 0;
+
+	LOG_DBG("(SDIO clock_freq=%d, bus_width=%d, timing_mode=%d, bus_mode=%d)", ios->clock,
+		ios->bus_width, ios->timing, ios->bus_mode);
+
+	if (ios->clock != 0 && (ios->clock <= config->max_bus_freq) &&
+	    (ios->clock >= config->min_bus_freq)) {
+		data->card.cfg.ui32Clock = ios->clock;
+	} else if (ios->clock != 0 && (ios->clock > config->max_bus_freq) &&
+		   (ios->clock <= MMC_CLOCK_HS200)) {
+		/*Limit HS200 frequency to config->max_bus_freq*/
+		data->card.cfg.ui32Clock = config->max_bus_freq;
+		eUHSMode = AM_HAL_HOST_UHS_SDR104;
+	} else if (ios->clock != 0) {
+		return -ENOTSUP;
+	}
+
+	if (ios->bus_mode != SDHC_BUSMODE_PUSHPULL) {
+		return -ENOTSUP;
+	}
+
+	switch (ios->bus_width) {
+	case SDHC_BUS_WIDTH1BIT:
+		eBusWidth = AM_HAL_HOST_BUS_WIDTH_1;
+		break;
+	case SDHC_BUS_WIDTH4BIT:
+		eBusWidth = AM_HAL_HOST_BUS_WIDTH_4;
+		break;
+	case SDHC_BUS_WIDTH8BIT:
+		eBusWidth = AM_HAL_HOST_BUS_WIDTH_8;
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	switch (ios->signal_voltage) {
+	case SD_VOL_3_3_V:
+		eBusVoltage = AM_HAL_HOST_BUS_VOLTAGE_3_3;
+		break;
+	case SD_VOL_3_0_V:
+		eBusVoltage = AM_HAL_HOST_BUS_VOLTAGE_3_0;
+		break;
+	case SD_VOL_1_8_V:
+		eBusVoltage = AM_HAL_HOST_BUS_VOLTAGE_1_8;
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+#if defined(CONFIG_PM_DEVICE_RUNTIME)
+	ret = pm_device_runtime_get(dev);
+
+	if (ret < 0) {
+		LOG_ERR("pm_device_runtime_get failed: %d", ret);
+	}
+#endif /* CONFIG_PM_DEVICE_RUNTIME */
+
+	/* Change SDIO Host Bus Voltage */
+	if (eBusVoltage != data->card.cfg.eIoVoltage) {
+		data->card.cfg.eIoVoltage = eBusVoltage;
+		ui32Status = data->host->ops->set_bus_voltage(data->host->pHandle, eBusVoltage);
+		if (ui32Status != AM_HAL_STATUS_SUCCESS) {
+#ifdef CONFIG_PM_DEVICE_RUNTIME
+			pm_device_runtime_put(dev);
+#endif
+			return -ENOTSUP;
+		}
+	}
+
+	/* Change SDIO Host Bus Width */
+	if (eBusWidth != data->card.cfg.eBusWidth) {
+		data->card.cfg.eBusWidth = eBusWidth;
+		ui32Status = data->host->ops->set_bus_width(data->host->pHandle, eBusWidth);
+		if (ui32Status != AM_HAL_STATUS_SUCCESS) {
+#ifdef CONFIG_PM_DEVICE_RUNTIME
+			pm_device_runtime_put(dev);
+#endif
+			return -ENOTSUP;
+		}
+	}
+
+	/* Change SDIO Host Clock Speed */
+	ui32Status = data->host->ops->set_bus_clock(data->host->pHandle, data->card.cfg.ui32Clock);
+	if (ui32Status != AM_HAL_STATUS_SUCCESS) {
+#ifdef CONFIG_PM_DEVICE_RUNTIME
+		pm_device_runtime_put(dev);
+#endif
+		return -ENOTSUP;
+	}
+
+	if (ios->timing == SDHC_TIMING_DDR52) {
+		LOG_DBG("MMC Card DDR50 Mode");
+		/* DDR50 mode must be 4bit or 8bit width according to EMMC Spec */
+		if (eBusWidth == AM_HAL_HOST_BUS_WIDTH_1) {
+#ifdef CONFIG_PM_DEVICE_RUNTIME
+			pm_device_runtime_put(dev);
+#endif
+			return -ENOTSUP;
+		}
+		eUHSMode = AM_HAL_HOST_UHS_DDR50;
+	}
+
+	/* Change SDIO Host UHS mode */
+	if (eUHSMode != data->card.cfg.eUHSMode) {
+		data->card.cfg.eUHSMode = eUHSMode;
+		ui32Status = data->host->ops->set_uhs_mode(data->host->pHandle, eUHSMode);
+		if (ui32Status != AM_HAL_STATUS_SUCCESS) {
+#ifdef CONFIG_PM_DEVICE_RUNTIME
+			pm_device_runtime_put(dev);
+#endif
+			return -ENOTSUP;
+		}
+	}
+
+#if defined(CONFIG_PM_DEVICE_RUNTIME)
+	/* Use async put to avoid useless device suspension/resumption
+	 * when doing consecutive transmission.
+	 */
+	ret = pm_device_runtime_put_async(dev, K_MSEC(2));
+
+	if (ret < 0) {
+		LOG_ERR("pm_device_runtime_put failed: %d", ret);
+	}
+#endif /* CONFIG_PM_DEVICE_RUNTIME */
+
+	return ret;
+}
+
+/*
+ * Ambiq SDIO Host Initialization Function
+ */
+static int ambiq_sdio_init(const struct device *dev)
+{
+	const struct ambiq_sdio_config *config = dev->config;
+	struct ambiq_sdio_data *data = dev->data;
+	int ret;
+
+	LOG_DBG("Ambiq SDIO Initialize Host #%d", config->inst);
+
+	ret = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
+	if (ret) {
+		return ret;
+	}
+
+	/* Get the uderlying SDHC host instance */
+	data->host = am_hal_get_card_host(AM_HAL_SDHC_CARD_HOST + config->inst, true);
+
+	if (data->host == NULL) {
+		LOG_ERR("No such card host and stop");
+		return -ENODEV;
+	}
+
+	config->irq_config_func(dev);
+
+	/* Fill the Card default setting with the host's default value  */
+	data->card.pHost = data->host;
+	data->card.cfg.eBusWidth = data->host->eBusWidth;
+	data->card.cfg.eIoVoltage = data->host->eBusVoltage;
+	data->card.cfg.ui32Clock = data->host->ui32MinClock;
+	data->card.cfg.eUHSMode = data->host->eUHSMode;
+
+	/* Set AM_HAL_CARD_PWR_CTRL_SDHC_OFF as default SDIO power control policy  */
+	data->card.eCardPwrCtrlPolicy = AM_HAL_CARD_PWR_CTRL_SDHC_OFF;
+	data->card.eState = AM_HAL_CARD_STATE_PWRON;
+	data->card.pCardPwrCtrlFunc = NULL;
+
+#ifdef CONFIG_AMBIQ_SDIO_ASYNC
+	/* Register callback function for Async data transfer  */
+	if (config->inst == 0) {
+		data->async_sem = &sdio_async_sem_0;
+		am_hal_card_register_evt_callback(&data->card, ambiq_sdio_event_cb_0);
+	} else if (config->inst == 1) {
+		data->async_sem = &sdio_async_sem_1;
+		am_hal_card_register_evt_callback(&data->card, ambiq_sdio_event_cb_1);
+	} else {
+		return -ENODEV;
+	}
+#endif /* CONFIG_AMBIQ_SDIO_ASYNC */
+
+	k_mutex_init(&data->access_mutex);
+
+	return 0;
+}
+
+/*
+ * Set TX & RX delay for Ambiq SDIO Timing Tuning
+ */
+static int ambiq_sdio_execute_tuning(const struct device *dev)
+{
+	const struct ambiq_sdio_config *config = dev->config;
+	struct ambiq_sdio_data *data = dev->data;
+	uint8_t ui8TxRxDelays[2] = {0};
+	int ret = 0;
+
+	/* SDIO TX delay setting range is 0 ~ 15 */
+	if (config->tx_delay < 16) {
+		ui8TxRxDelays[0] = config->tx_delay;
+	} else {
+		return -EINVAL;
+	}
+
+	/* SDIO RX delay setting range is 0 ~ 31 */
+	if (config->rx_delay < 32) {
+		ui8TxRxDelays[1] = config->rx_delay;
+	} else {
+		return -EINVAL;
+	}
+
+	/* Timing delay is disabled if both TX and RX delay are set into 0 */
+	if (ui8TxRxDelays[0] != 0 || ui8TxRxDelays[1] != 0) {
+#if defined(CONFIG_PM_DEVICE_RUNTIME)
+		ret = pm_device_runtime_get(dev);
+
+		if (ret < 0) {
+			LOG_ERR("pm_device_runtime_get failed: %d", ret);
+		}
+#endif /* CONFIG_PM_DEVICE_RUNTIME */
+
+		am_hal_card_host_set_txrx_delay(data->host, ui8TxRxDelays);
+
+#if defined(CONFIG_PM_DEVICE_RUNTIME)
+		/* Use async put to avoid useless device suspension/resumption
+		 * when doing consecutive transmission.
+		 */
+		ret = pm_device_runtime_put_async(dev, K_MSEC(2));
+
+		if (ret < 0) {
+			LOG_ERR("pm_device_runtime_put failed: %d", ret);
+		}
+#endif /* CONFIG_PM_DEVICE_RUNTIME */
+	}
+
+	return ret;
+}
+
+/*
+ * Check for Card Presence
+ */
+static int ambiq_sdio_get_card_present(const struct device *dev)
+{
+	struct ambiq_sdio_data *data = dev->data;
+	int status = 0;
+#if defined(CONFIG_PM_DEVICE_RUNTIME)
+	int ret = 0;
+
+	ret = pm_device_runtime_get(dev);
+
+	if (ret < 0) {
+		LOG_ERR("pm_device_runtime_get failed: %d", ret);
+	}
+#endif /* CONFIG_PM_DEVICE_RUNTIME */
+	LOG_DBG("Get card present status");
+	status = data->host->ops->get_cd(data->host->pHandle);
+#if defined(CONFIG_PM_DEVICE_RUNTIME)
+	/* Use async put to avoid useless device suspension/resumption
+	 * when doing consecutive transmission.
+	 */
+	ret = pm_device_runtime_put_async(dev, K_MSEC(2));
+
+	if (ret < 0) {
+		LOG_ERR("pm_device_runtime_put failed: %d", ret);
+	}
+#endif /* CONFIG_PM_DEVICE_RUNTIME */
+	return status;
+}
+
+/*
+ * Check for Card Busy Status
+ */
+static int ambiq_sdio_card_busy(const struct device *dev)
+{
+	struct ambiq_sdio_data *data = dev->data;
+	uint32_t ui32Status;
+#if defined(CONFIG_PM_DEVICE_RUNTIME)
+	int ret = 0;
+
+	ret = pm_device_runtime_get(dev);
+
+	if (ret < 0) {
+		LOG_ERR("pm_device_runtime_get failed: %d", ret);
+	}
+#endif /* CONFIG_PM_DEVICE_RUNTIME */
+	ui32Status = data->host->ops->card_busy(data->host->pHandle, DEFAULT_GET_STATUS_TIMEOUT_MS);
+	LOG_DBG("Check card busy status");
+#if defined(CONFIG_PM_DEVICE_RUNTIME)
+	/* Use async put to avoid useless device suspension/resumption
+	 * when doing consecutive transmission.
+	 */
+	ret = pm_device_runtime_put_async(dev, K_MSEC(2));
+
+	if (ret < 0) {
+		LOG_ERR("pm_device_runtime_put failed: %d", ret);
+	}
+#endif /* CONFIG_PM_DEVICE_RUNTIME */
+
+	return (ui32Status != AM_HAL_STATUS_SUCCESS) ? 1 : 0;
+}
+
+/*
+ * Ambiq SDIO Command and Data Request Function
+ */
+static int ambiq_sdio_request(const struct device *dev, struct sdhc_command *cmd,
+			      struct sdhc_data *data)
+{
+	struct ambiq_sdio_data *dev_data = dev->data;
+	uint32_t ui32Status = 0;
+	int ret = 0;
+
+	am_hal_card_cmd_t sdio_cmd = {0};
+	am_hal_card_cmd_data_t cmd_data = {0};
+
+	if (cmd) {
+		sdio_cmd.ui8Idx = cmd->opcode;
+		sdio_cmd.ui32Arg = cmd->arg;
+		sdio_cmd.ui32RespType = cmd->response_type;
+		sdio_cmd.bASync = false;
+	} else {
+		LOG_ERR("Invalid CMD");
+		return -EINVAL;
+	}
+
+	if (data) {
+		cmd_data.ui32BlkCnt = data->blocks;
+		cmd_data.ui32BlkSize = data->block_size;
+		cmd_data.pui8Buf = data->data;
+
+		if (sdio_cmd.ui8Idx == MMC_CMD_READ_MULTIPLE_BLOCK ||
+		    sdio_cmd.ui8Idx == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
+			sdio_cmd.bAutoCMD23 = true;
+		}
+
+		if (sdio_cmd.ui8Idx == MMC_CMD_WRITE_SINGLE_BLOCK ||
+		    sdio_cmd.ui8Idx == MMC_CMD_WRITE_MULTIPLE_BLOCK) {
+			cmd_data.dir = AM_HAL_DATA_DIR_WRITE;
+		} else if ((sdio_cmd.ui8Idx == SDIO_CMD_IO_RW_EXTENDED) &&
+			   (sdio_cmd.ui32Arg & BIT(SDIO_CMD_ARG_RW_SHIFT))) {
+			cmd_data.dir = AM_HAL_DATA_DIR_WRITE;
+		} else {
+			cmd_data.dir = AM_HAL_DATA_DIR_READ;
+		}
+	}
+
+	LOG_DBG("Send SDIO CMD%d", sdio_cmd.ui8Idx);
+	LOG_DBG("CMD->Arg = 0x%x CMD->RespType = 0x%x", sdio_cmd.ui32Arg, sdio_cmd.ui32RespType);
+
+	if (sdio_cmd.ui8Idx == 1) {
+		LOG_DBG("Config CMD1 RespType");
+		sdio_cmd.ui32RespType = MMC_RSP_R3;
+	} else if (sdio_cmd.ui8Idx == 3) {
+		LOG_DBG("Config CMD3 RespType");
+		sdio_cmd.ui32RespType = MMC_RSP_R6;
+	} else if ((sdio_cmd.ui8Idx == 52) || (sdio_cmd.ui8Idx == 53)) {
+		LOG_DBG("Config CMD%d RespType", sdio_cmd.ui8Idx);
+		sdio_cmd.ui32RespType = MMC_RSP_R5;
+	} else if (sdio_cmd.ui8Idx == 6 || sdio_cmd.ui8Idx == 38) {
+		LOG_DBG("Set CheckBusyCmd");
+		sdio_cmd.bCheckBusyCmd = true;
+		sdio_cmd.ui32RespType = MMC_RSP_R1b;
+	} else if (sdio_cmd.ui8Idx == 17 || sdio_cmd.ui8Idx == 18 || sdio_cmd.ui8Idx == 24 ||
+		   sdio_cmd.ui8Idx == 25) {
+		sdio_cmd.ui32RespType = MMC_RSP_R1;
+	}
+
+#ifdef CONFIG_AMBIQ_SDIO_ASYNC
+	if (data) {
+		sdio_cmd.bASync = true;
+		dev_data->host->AsyncCmd = sdio_cmd;
+		dev_data->host->AsyncCmdData = cmd_data;
+	}
+#endif /* CONFIG_AMBIQ_SDIO_ASYNC */
+
+	ret = k_mutex_lock(&dev_data->access_mutex, K_MSEC(cmd->timeout_ms));
+	if (ret) {
+		LOG_ERR("Could not access card");
+		return -EBUSY;
+	}
+
+#if defined(CONFIG_PM_DEVICE_RUNTIME)
+	ret = pm_device_runtime_get(dev);
+
+	if (ret < 0) {
+		LOG_ERR("pm_device_runtime_get failed: %d", ret);
+	}
+#endif /* CONFIG_PM_DEVICE_RUNTIME */
+
+	if (data) {
+#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
+		/* Clean Dcache before DMA write */
+		if (cmd_data.dir == AM_HAL_DATA_DIR_WRITE &&
+		    (uint32_t)(data->data) >= CACHABLE_START_ADDR) {
+			sys_cache_data_flush_range(data->data, data->blocks * data->block_size);
+		}
+#endif
+
+#ifdef CONFIG_AMBIQ_SDIO_ASYNC
+		k_sem_reset(dev_data->async_sem);
+#endif /* CONFIG_AMBIQ_SDIO_ASYNC */
+		ui32Status = dev_data->host->ops->execute_cmd(dev_data->host->pHandle, &sdio_cmd,
+							      &cmd_data);
+#ifdef CONFIG_AMBIQ_SDIO_ASYNC
+		if ((ui32Status & 0xFFFF) == AM_HAL_STATUS_SUCCESS) {
+			if (k_sem_take(dev_data->async_sem, K_MSEC(data->timeout_ms))) {
+				return -ETIMEDOUT;
+			}
+		}
+#endif /* CONFIG_AMBIQ_SDIO_ASYNC */
+
+#if defined(CONFIG_CACHE_MANAGEMENT) && defined(CONFIG_DCACHE)
+		/* Invalidate Dcache after DMA read */
+		if (cmd_data.dir == AM_HAL_DATA_DIR_READ &&
+		    (uint32_t)(data->data) >= CACHABLE_START_ADDR) {
+			sys_cache_data_invd_range(data->data, data->blocks * data->block_size);
+		}
+#endif
+
+	} else {
+		ui32Status =
+			dev_data->host->ops->execute_cmd(dev_data->host->pHandle, &sdio_cmd, NULL);
+	}
+	if ((ui32Status & 0xFFFF) != AM_HAL_STATUS_SUCCESS) {
+		if ((ui32Status & 0xFFFF) == AM_HAL_STATUS_TIMEOUT) {
+			LOG_DBG("CMD%d Timeout!", sdio_cmd.ui8Idx);
+			ret = -ETIMEDOUT;
+		} else {
+			LOG_DBG("Failed to send CMD%d, ui32Status = 0x%x", sdio_cmd.ui8Idx,
+				ui32Status);
+			ret = -EIO;
+		}
+	}
+
+	k_mutex_unlock(&dev_data->access_mutex);
+
+	memcpy(cmd->response, sdio_cmd.ui32Resp, sizeof(cmd->response));
+
+	LOG_DBG("Resp0 = 0x%x, Resp1 = 0x%x, Resp2 = 0x%x, Resp3 = 0x%x", cmd->response[0],
+		cmd->response[1], cmd->response[2], cmd->response[3]);
+
+	if (data) {
+		data->bytes_xfered = (ui32Status >> 16) & 0xFFFF;
+	}
+
+#if defined(CONFIG_PM_DEVICE_RUNTIME)
+	/* Use async put to avoid useless device suspension/resumption
+	 * when doing consecutive transmission.
+	 */
+	ret = pm_device_runtime_put_async(dev, K_MSEC(2));
+
+	if (ret < 0) {
+		LOG_ERR("pm_device_runtime_put failed: %d", ret);
+	}
+#endif /* CONFIG_PM_DEVICE_RUNTIME */
+
+	return ret;
+}
+
+/*
+ * Enable Card Interrupts
+ */
+static int ambiq_sdio_card_interrupt_enable(const struct device *dev, sdhc_interrupt_cb_t callback,
+					    int sources, void *user_data)
+{
+	struct ambiq_sdio_data *data = dev->data;
+	uint32_t ui32Status = 0;
+
+	data->sdio_cb = callback;
+	data->sdio_cb_user_data = user_data;
+
+	if (sources & SDHC_INT_SDIO) {
+		/* Enable SDIO Card Interrupt */
+		ui32Status = am_hal_sdhc_intr_signal_enable(data->host->pHandle,
+							    SDIO_INTSIG_CARDINTEN_Msk);
+		if (ui32Status != AM_HAL_STATUS_SUCCESS) {
+			return -EIO;
+		}
+		ui32Status = am_hal_sdhc_intr_status_enable(
+			data->host->pHandle, SDIO_INTENABLE_CARDINTERRUPTSTATUSENABLE_Msk);
+		if (ui32Status != AM_HAL_STATUS_SUCCESS) {
+			return -EIO;
+		}
+	}
+
+	if (sources & SDHC_INT_INSERTED) {
+		/* Enable Card Insert Interrupt */
+		ui32Status = am_hal_sdhc_intr_signal_enable(data->host->pHandle,
+							    SDIO_INTSIG_CARDINSERTEN_Msk);
+		if (ui32Status != AM_HAL_STATUS_SUCCESS) {
+			return -EIO;
+		}
+		ui32Status = am_hal_sdhc_intr_status_enable(
+			data->host->pHandle, SDIO_INTENABLE_CARDINSERTIONSTATUSENABLE_Msk);
+		if (ui32Status != AM_HAL_STATUS_SUCCESS) {
+			return -EIO;
+		}
+	}
+
+	if (sources & SDHC_INT_REMOVED) {
+		/* Enable Card Removal Interrupt */
+		ui32Status = am_hal_sdhc_intr_signal_enable(data->host->pHandle,
+							    SDIO_INTSIG_CARDREMOVALEN_Msk);
+		if (ui32Status != AM_HAL_STATUS_SUCCESS) {
+			return -EIO;
+		}
+		ui32Status = am_hal_sdhc_intr_status_enable(
+			data->host->pHandle, SDIO_INTENABLE_CARDREMOVALSTATUSENABLE_Msk);
+		if (ui32Status != AM_HAL_STATUS_SUCCESS) {
+			return -EIO;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * Disable Card Interrupts
+ */
+static int ambiq_sdio_card_interrupt_disable(const struct device *dev, int sources)
+{
+	struct ambiq_sdio_data *data = dev->data;
+	uint32_t ui32Status = 0;
+
+	data->sdio_cb = NULL;
+	data->sdio_cb_user_data = NULL;
+
+	if (sources & SDHC_INT_SDIO) {
+		/* Disable SDIO Card Interrupt */
+		ui32Status = am_hal_sdhc_intr_signal_disable(data->host->pHandle,
+							     SDIO_INTSIG_CARDINTEN_Msk);
+		if (ui32Status != AM_HAL_STATUS_SUCCESS) {
+			return -EIO;
+		}
+		ui32Status = am_hal_sdhc_intr_status_disable(
+			data->host->pHandle, SDIO_INTENABLE_CARDINTERRUPTSTATUSENABLE_Msk);
+		if (ui32Status != AM_HAL_STATUS_SUCCESS) {
+			return -EIO;
+		}
+	}
+
+	if (sources & SDHC_INT_INSERTED) {
+		/* Disable Card Insert Interrupt */
+		ui32Status = am_hal_sdhc_intr_signal_disable(data->host->pHandle,
+							     SDIO_INTSIG_CARDINSERTEN_Msk);
+		if (ui32Status != AM_HAL_STATUS_SUCCESS) {
+			return -EIO;
+		}
+		ui32Status = am_hal_sdhc_intr_status_disable(
+			data->host->pHandle, SDIO_INTENABLE_CARDINSERTIONSTATUSENABLE_Msk);
+		if (ui32Status != AM_HAL_STATUS_SUCCESS) {
+			return -EIO;
+		}
+	}
+
+	if (sources & SDHC_INT_REMOVED) {
+		/* Disable Card Removal Interrupt */
+		ui32Status = am_hal_sdhc_intr_signal_disable(data->host->pHandle,
+							     SDIO_INTSIG_CARDREMOVALEN_Msk);
+		if (ui32Status != AM_HAL_STATUS_SUCCESS) {
+			return -EIO;
+		}
+		ui32Status = am_hal_sdhc_intr_status_disable(
+			data->host->pHandle, SDIO_INTENABLE_CARDREMOVALSTATUSENABLE_Msk);
+		if (ui32Status != AM_HAL_STATUS_SUCCESS) {
+			return -EIO;
+		}
+	}
+
+	return 0;
+}
+
+static const struct sdhc_driver_api ambiq_sdio_api = {
+	.reset = ambiq_sdio_reset,
+	.request = ambiq_sdio_request,
+	.set_io = ambiq_sdio_set_io,
+	.get_card_present = ambiq_sdio_get_card_present,
+	.execute_tuning = ambiq_sdio_execute_tuning,
+	.card_busy = ambiq_sdio_card_busy,
+	.get_host_props = ambiq_sdio_get_host_props,
+	.enable_interrupt = ambiq_sdio_card_interrupt_enable,
+	.disable_interrupt = ambiq_sdio_card_interrupt_disable,
+};
+
+#ifdef CONFIG_PM_DEVICE
+/*
+ * Ambiq SDIO peripheral power management function
+ */
+static int ambiq_sdio_pm_action(const struct device *dev, enum pm_device_action action)
+{
+	struct ambiq_sdio_data *data = dev->data;
+	int ret;
+
+	switch (action) {
+	case PM_DEVICE_ACTION_RESUME:
+		ret = am_hal_card_pwrctrl_wakeup(&data->card);
+		break;
+	case PM_DEVICE_ACTION_SUSPEND:
+		ret = am_hal_card_pwrctrl_sleep(&data->card);
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	if (ret != AM_HAL_STATUS_SUCCESS) {
+		return -EPERM;
+	} else {
+		return 0;
+	}
+}
+#endif /* CONFIG_PM_DEVICE */
+
+#define AMBIQ_SDIO_INIT(n)                                                                         \
+	static void sdio_##n##_irq_config_func(const struct device *dev)                           \
+	{                                                                                          \
+		IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), ambiq_sdio_isr,             \
+			    DEVICE_DT_INST_GET(n), 0);                                             \
+		irq_enable(DT_INST_IRQN(n));                                                       \
+	}                                                                                          \
+                                                                                                   \
+	PINCTRL_DT_INST_DEFINE(n);                                                                 \
+                                                                                                   \
+	static const struct ambiq_sdio_config ambiq_sdio_config_##n = {                            \
+		.pSDHC = (SDIO_Type *)DT_INST_REG_ADDR(n),                                         \
+		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                       \
+		.irq_config_func = sdio_##n##_irq_config_func,                                     \
+		.inst = n,                                                                         \
+		.tx_delay = DT_INST_PROP(n, txdelay),                                              \
+		.rx_delay = DT_INST_PROP(n, rxdelay),                                              \
+		.max_bus_freq = DT_INST_PROP(n, max_bus_freq),                                     \
+		.min_bus_freq = DT_INST_PROP(n, min_bus_freq),                                     \
+		.power_delay_ms = DT_INST_PROP(n, power_delay_ms),                                 \
+	};                                                                                         \
+                                                                                                   \
+	static struct ambiq_sdio_data ambiq_sdio_data_##n;                                         \
+	PM_DEVICE_DT_INST_DEFINE(n, ambiq_sdio_pm_action);                                         \
+	DEVICE_DT_INST_DEFINE(n, &ambiq_sdio_init, PM_DEVICE_DT_INST_GET(n), &ambiq_sdio_data_##n, \
+			      &ambiq_sdio_config_##n, POST_KERNEL, CONFIG_SDHC_INIT_PRIORITY,      \
+			      &ambiq_sdio_api);
+
+DT_INST_FOREACH_STATUS_OKAY(AMBIQ_SDIO_INIT)
diff --git a/drivers/sdhc/sdhc_cdns_ll.c b/drivers/sdhc/sdhc_cdns_ll.c
index 773b92b0e05..485f6c008ec 100644
--- a/drivers/sdhc/sdhc_cdns_ll.c
+++ b/drivers/sdhc/sdhc_cdns_ll.c
@@ -165,7 +165,7 @@ void cdns_sdhc_set_sdmmc_params(struct sdhc_cdns_combo_phy *sdhc_cdns_combo_phy_
 	sdhc_cdns_sdmmc_reg->sdhc_wrdata1_sdclk_dly = 0;
 }
 
-/* Phy register programing for phy init */
+/* Phy register programming for phy init */
 static int sdhc_cdns_program_phy_reg(struct sdhc_cdns_combo_phy *sdhc_cdns_combo_phy_reg,
 	struct sdhc_cdns_sdmmc *sdhc_cdns_sdmmc_reg)
 {
diff --git a/drivers/sdhc/sdhc_max32.c b/drivers/sdhc/sdhc_max32.c
new file mode 100644
index 00000000000..0bc8caa3233
--- /dev/null
+++ b/drivers/sdhc/sdhc_max32.c
@@ -0,0 +1,412 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT adi_max32_sdhc
+
+#include <errno.h>
+#include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
+#include <zephyr/drivers/sdhc.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/sys/util_macro.h>
+#include <wrap_max32_sdhc.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/kernel.h>
+
+LOG_MODULE_REGISTER(sdhc_max32, CONFIG_SDHC_LOG_LEVEL);
+
+static int cmd_opcode_converter(int opcode, unsigned int *cmd);
+static int convert_freq_to_divider(int freq);
+
+/* **** Definitions ****
+ * todo: added from sdhc_resp_regs.h cmd51 is mandatory and is missing in msdk.
+ * SDHC commands and associated cmd register bits which inform hardware to wait for response, etc.
+ */
+#define MXC_SDHC_LIB_CMD0  0x0000
+#define MXC_SDHC_LIB_CMD1  0x0102
+#define MXC_SDHC_LIB_CMD2  0x0209
+#define MXC_SDHC_LIB_CMD3  0x031A
+#define MXC_SDHC_LIB_CMD4  0x0400
+#define MXC_SDHC_LIB_CMD5  0x051A
+#define MXC_SDHC_LIB_CMD6  0x060A
+#define MXC_SDHC_LIB_CMD7  0x071B
+#define MXC_SDHC_LIB_CMD8  0x081A
+#define MXC_SDHC_LIB_CMD9  0x0901
+#define MXC_SDHC_LIB_CMD10 0x0A01
+#define MXC_SDHC_LIB_CMD11 0x0B1A
+#define MXC_SDHC_LIB_CMD12 0x0C1B
+#define MXC_SDHC_LIB_CMD13 0x0D1A
+#define MXC_SDHC_LIB_CMD16 0x101A
+#define MXC_SDHC_LIB_CMD17 0x113A
+#define MXC_SDHC_LIB_CMD18 0x123A
+#define MXC_SDHC_LIB_CMD23 0x171A
+#define MXC_SDHC_LIB_CMD24 0x183E
+#define MXC_SDHC_LIB_CMD25 0x193E
+#define MXC_SDHC_LIB_CMD55 0x371A
+
+/* Application commands (SD Card) which are prefixed by CMD55 */
+#define MXC_SDHC_LIB_ACMD6  0x061B
+#define MXC_SDHC_LIB_ACMD41 0x2902
+#define MXC_SDHC_LIB_ACMD51 0x331B
+
+/* todo: GCR dependent division might be 4 as well. if set to = 1 sdhcfrq. add support in msdk */
+#define SDHC_CLOCK (ADI_MAX32_CLK_IPO_FREQ / 2)
+
+#define SDHC_SDHC_MAX_DIV_VAL 0x3FF
+#define SDHC_SDHC_PCLK_DIV 2
+
+/* todo: cmd.arg = SD_IF_COND_VHS_3V3 | check_pattern;
+ * todo: zephyr always configures response types. msdk needs to support this as well.
+ * todo: add host io support
+ */
+
+struct sdhc_max32_data {
+	struct sdhc_host_props props;
+};
+
+/* SDHC configuration. */
+struct sdhc_max32_config {
+	void (*irq_func)(void);
+	const struct pinctrl_dev_config *pcfg;
+	unsigned int power_delay_ms;
+	unsigned int bus_volt;
+	const struct device *clock;
+	struct max32_perclk perclk;
+};
+
+static void sdhc_max32_init_props(const struct device *dev)
+{
+	struct sdhc_max32_data *sdhc_data = dev->data;
+	const struct sdhc_max32_config *sdhc_config = dev->config;
+
+	memset(sdhc_data, 0, sizeof(struct sdhc_max32_data));
+
+	sdhc_data->props.f_min = SDHC_CLOCK / (SDHC_SDHC_PCLK_DIV * SDHC_SDHC_MAX_DIV_VAL);
+	sdhc_data->props.f_max = SDHC_CLOCK;
+	sdhc_data->props.is_spi = 0;
+	sdhc_data->props.max_current_180 = 0;
+	sdhc_data->props.max_current_300 = 0;
+	sdhc_data->props.max_current_330 = 0;
+	sdhc_data->props.host_caps.timeout_clk_freq = 0x01;
+	sdhc_data->props.host_caps.timeout_clk_unit = 1;
+	sdhc_data->props.host_caps.sd_base_clk = 0x00;
+	sdhc_data->props.host_caps.max_blk_len = 0b10;
+	sdhc_data->props.host_caps.bus_8_bit_support = false;
+	sdhc_data->props.host_caps.bus_4_bit_support = false;
+	sdhc_data->props.host_caps.adma_2_support = true;
+	sdhc_data->props.host_caps.high_spd_support = true;
+	sdhc_data->props.host_caps.sdma_support = true;
+	sdhc_data->props.host_caps.suspend_res_support = true;
+	sdhc_data->props.host_caps.vol_330_support = true;
+	sdhc_data->props.host_caps.vol_300_support = false;
+	sdhc_data->props.host_caps.vol_180_support = false;
+	sdhc_data->props.host_caps.address_64_bit_support_v4 = false;
+	sdhc_data->props.host_caps.address_64_bit_support_v3 = false;
+	sdhc_data->props.host_caps.sdio_async_interrupt_support = true;
+	sdhc_data->props.host_caps.slot_type = 00;
+	sdhc_data->props.host_caps.sdr50_support = true;
+	sdhc_data->props.host_caps.sdr104_support = true;
+	sdhc_data->props.host_caps.ddr50_support = true;
+	sdhc_data->props.host_caps.uhs_2_support = false;
+	sdhc_data->props.host_caps.drv_type_a_support = true;
+	sdhc_data->props.host_caps.drv_type_c_support = true;
+	sdhc_data->props.host_caps.drv_type_d_support = true;
+	sdhc_data->props.host_caps.retune_timer_count = 0;
+	sdhc_data->props.host_caps.sdr50_needs_tuning = 0;
+	sdhc_data->props.host_caps.retuning_mode = 0;
+	sdhc_data->props.host_caps.clk_multiplier = 0;
+	sdhc_data->props.host_caps.adma3_support = false;
+	sdhc_data->props.host_caps.vdd2_180_support = false;
+	sdhc_data->props.host_caps.hs200_support = false;
+	sdhc_data->props.host_caps.hs400_support = false;
+	sdhc_data->props.power_delay = sdhc_config->power_delay_ms;
+}
+
+static int sdhc_max32_init(const struct device *dev)
+{
+	const struct sdhc_max32_config *sdhc_config = dev->config;
+	int ret = 0;
+	mxc_sdhc_cfg_t cfg;
+
+	ret = pinctrl_apply_state(sdhc_config->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret < 0) {
+		LOG_ERR("Pinctrl apply error:%d", ret);
+		return ret;
+	}
+
+	ret = clock_control_on(sdhc_config->clock, (clock_control_subsys_t)&sdhc_config->perclk);
+	if (ret) {
+		LOG_ERR("Clock control on error:%d", ret);
+		return ret;
+	}
+
+	cfg.bus_voltage = MXC_SDHC_Bus_Voltage_3_3;
+	cfg.block_gap = 0;
+	/* Maximum divide ratio, frequency must be 100 - 400 kHz during Card Identification"*/
+	cfg.clk_div = SDHC_SDHC_MAX_DIV_VAL;
+
+	ret = MXC_SDHC_Init(&cfg);
+	if (ret != E_NO_ERROR) {
+		LOG_ERR("MXC_SDHC_Init error:%d", ret);
+		return ret;
+	}
+
+/* note: init delay, without it applications fail. 5ms found empirically.
+ * todo: investigate why fails, see if it can be removed via polling a register bit etc.
+ */
+	k_sleep(K_MSEC(5));
+
+	sdhc_max32_init_props(dev);
+
+	return 0;
+}
+
+static int sdhc_max32_card_busy(const struct device *dev)
+{
+	int ret = 0;
+
+	ret = MXC_SDHC_Card_Busy();
+
+	return ret;
+}
+
+static int sdhc_max32_reset(const struct device *dev)
+{
+	MXC_SDHC_Reset();
+
+	return 0;
+}
+
+static int sdhc_max32_request(const struct device *dev, struct sdhc_command *cmd,
+			      struct sdhc_data *data)
+{
+	int ret = 0;
+	unsigned int mxc_cmd = 0;
+	mxc_sdhc_cmd_cfg_t sd_cmd_cfg;
+	bool card_size_workaround = false;
+
+	if (data) {
+		sd_cmd_cfg.sdma = (unsigned int)data->data;
+		sd_cmd_cfg.block_size = data->block_size;
+		sd_cmd_cfg.block_count = data->blocks;
+	}
+
+	sd_cmd_cfg.arg_1 = cmd->arg;
+	sd_cmd_cfg.dma = true; /* todo: add config depending on config_dma etc. */
+
+	switch (cmd->opcode) {
+	case SD_READ_SINGLE_BLOCK:
+	case SD_READ_MULTIPLE_BLOCK:
+		sd_cmd_cfg.direction = MXC_SDHC_DIRECTION_READ;
+		sd_cmd_cfg.arg_1 = data->block_addr;
+		break;
+	case SD_WRITE_SINGLE_BLOCK:
+	case SD_WRITE_MULTIPLE_BLOCK:
+		sd_cmd_cfg.direction = MXC_SDHC_DIRECTION_WRITE;
+		sd_cmd_cfg.arg_1 = data->block_addr;
+		break;
+	case SD_SEND_CSD:
+		card_size_workaround = true;
+	default:
+		sd_cmd_cfg.direction = MXC_SDHC_DIRECTION_CFG;
+		break;
+	}
+
+	ret = cmd_opcode_converter(cmd->opcode, &mxc_cmd);
+	if (ret) {
+		return ret;
+	}
+	sd_cmd_cfg.command = mxc_cmd;
+	sd_cmd_cfg.host_control_1 = MXC_SDHC_Get_Host_Cn_1();
+	sd_cmd_cfg.callback = NULL;
+
+	/*
+	 * todo: this was also needed, otherwise applications failed randomly. it would be good to
+	 * remove this with a better solution in future.
+	 */
+	k_sleep(K_MSEC(1));
+	ret = MXC_SDHC_SendCommand(&sd_cmd_cfg);
+	if (ret) {
+		LOG_ERR("MXC_SDHC_SendCommand error:%d, SD opcode: %d", ret, cmd->opcode);
+		return ret;
+	}
+
+	MXC_SDHC_Get_Response128((char *)(cmd->response));
+
+	if (card_size_workaround) {
+		/*
+		 * this workaround is required for only CMD9. This fixes size problem. Otherwise
+		 * it doesn't give the correct device size information.
+		 */
+		cmd->response[1] <<= 8;
+		cmd->response[3] <<= 8;
+	}
+
+	return 0;
+}
+
+static int sdhc_max32_get_card_present(const struct device *dev)
+{
+	return MXC_SDHC_Card_Inserted();
+}
+
+static int sdhc_max32_get_host_props(const struct device *dev, struct sdhc_host_props *props)
+{
+	struct sdhc_max32_data *sdhc_data = dev->data;
+
+	memcpy(props, &sdhc_data->props, sizeof(struct sdhc_host_props));
+
+	return 0;
+}
+
+static int sdhc_max32_set_io(const struct device *dev, struct sdhc_io *ios)
+{
+	struct sdhc_max32_data *data = dev->data;
+	struct sdhc_host_props *props = &data->props;
+	enum sdhc_clock_speed speed = ios->clock;
+	unsigned int clk_div = 0;
+
+	if (speed) {
+		if (speed < props->f_min || speed > props->f_max) {
+			LOG_ERR("Speed range error %d", speed);
+			return -ENOTSUP;
+		}
+		clk_div = convert_freq_to_divider(speed);
+		MXC_SDHC_Set_Clock_Config(clk_div);
+	}
+
+	if (ios->power_mode == SDHC_POWER_OFF) {
+		MXC_SDHC_PowerDown();
+	} else {
+		MXC_SDHC_PowerUp();
+	}
+
+	return 0;
+}
+
+static DEVICE_API(sdhc, sdhc_max32_driver_api) = {
+	.reset = sdhc_max32_reset,
+	.request = sdhc_max32_request,
+	.set_io = sdhc_max32_set_io,
+	.get_card_present = sdhc_max32_get_card_present,
+	.card_busy = sdhc_max32_card_busy,
+	.get_host_props = sdhc_max32_get_host_props,
+	.enable_interrupt = NULL,
+	.disable_interrupt = NULL,
+	.execute_tuning = NULL,
+};
+
+static int cmd_opcode_converter(int opcode, unsigned int *cmd)
+{
+	switch (opcode) {
+	case SD_GO_IDLE_STATE:
+		*cmd = MXC_SDHC_LIB_CMD0;
+		break;
+	case MMC_SEND_OP_COND:
+		*cmd = MXC_SDHC_LIB_CMD1;
+		break;
+	case SD_ALL_SEND_CID:
+		*cmd = MXC_SDHC_LIB_CMD2;
+		break;
+	case SD_SEND_RELATIVE_ADDR:
+		*cmd = MXC_SDHC_LIB_CMD3;
+		break;
+	case SDIO_SEND_OP_COND:
+		*cmd = MXC_SDHC_LIB_CMD5;
+		break;
+	case SD_SWITCH:
+		*cmd = MXC_SDHC_LIB_CMD6;
+		break;
+	case SD_SELECT_CARD:
+		*cmd = MXC_SDHC_LIB_CMD7;
+		break;
+	case SD_SEND_IF_COND:
+		*cmd = MXC_SDHC_LIB_CMD8;
+		break;
+	case SD_SEND_CSD:
+		*cmd = MXC_SDHC_LIB_CMD9;
+		break;
+	case SD_SEND_CID:
+		*cmd = MXC_SDHC_LIB_CMD10;
+		break;
+	case SD_VOL_SWITCH:
+		*cmd = MXC_SDHC_LIB_CMD11;
+		break;
+	case SD_STOP_TRANSMISSION:
+		*cmd = MXC_SDHC_LIB_CMD12;
+		break;
+	case SD_SEND_STATUS:
+		*cmd = MXC_SDHC_LIB_CMD13;
+		break;
+	case SD_SET_BLOCK_SIZE:
+		*cmd = MXC_SDHC_LIB_CMD16;
+		break;
+	case SD_READ_SINGLE_BLOCK:
+		*cmd = MXC_SDHC_LIB_CMD17;
+		break;
+	case SD_READ_MULTIPLE_BLOCK:
+		*cmd = MXC_SDHC_LIB_CMD18;
+		break;
+	case SD_SET_BLOCK_COUNT:
+		*cmd = MXC_SDHC_LIB_CMD23;
+		break;
+	case SD_WRITE_SINGLE_BLOCK:
+		*cmd = MXC_SDHC_LIB_CMD24;
+		break;
+	case SD_WRITE_MULTIPLE_BLOCK:
+		*cmd = MXC_SDHC_LIB_CMD25;
+		break;
+	case SD_APP_CMD:
+		*cmd = MXC_SDHC_LIB_CMD55;
+		break;
+	case SD_APP_SEND_OP_COND:
+		*cmd = MXC_SDHC_LIB_ACMD41;
+		break;
+	case SD_APP_SEND_SCR:
+		*cmd = MXC_SDHC_LIB_ACMD51;
+		break;
+		/* todo: below are not defined in msdk, support might be added later */
+	case SD_ERASE_BLOCK_START:
+	case SD_ERASE_BLOCK_END:
+	case SD_ERASE_BLOCK_OPERATION:
+	case SDIO_RW_DIRECT:
+	case SD_SEND_TUNING_BLOCK:
+	case SD_GO_INACTIVE_STATE:
+	case SDIO_RW_EXTENDED:
+	default:
+		LOG_ERR("Opcode convert error %d", opcode);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int convert_freq_to_divider(int freq)
+{
+	if (!freq) {
+		return 0;
+	}
+
+	int divider = 0;
+	/* note: this causes a bit different speed than exact number. */
+	divider = SDHC_CLOCK / (2 * freq);
+
+	return divider;
+}
+
+#define DEFINE_SDHC_MAX32(_num)                                                                    \
+	PINCTRL_DT_INST_DEFINE(_num);                                                              \
+	static struct sdhc_max32_data sdhc_max32_data_##_num;                                      \
+	static const struct sdhc_max32_config sdhc_max32_config_##_num = {                         \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(_num),                                      \
+		.power_delay_ms = DT_INST_PROP(_num, power_delay_ms),                              \
+		.clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(_num)),                                 \
+		.perclk.bus = DT_INST_CLOCKS_CELL(_num, offset),                                   \
+		.perclk.bit = DT_INST_CLOCKS_CELL(_num, bit),                                      \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(_num, sdhc_max32_init, NULL, &sdhc_max32_data_##_num,                \
+			      &sdhc_max32_config_##_num, POST_KERNEL, 2, &sdhc_max32_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(DEFINE_SDHC_MAX32)
diff --git a/drivers/sdhc/sdhc_renesas_ra.c b/drivers/sdhc/sdhc_renesas_ra.c
index 9993d5be3bf..7dda458b0dc 100644
--- a/drivers/sdhc/sdhc_renesas_ra.c
+++ b/drivers/sdhc/sdhc_renesas_ra.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -591,24 +591,20 @@ static DEVICE_API(sdhc, sdhc_api) = {
 	.get_host_props = sdhc_ra_get_host_props,
 };
 
-#define _ELC_EVENT_SDMMC_ACCS(channel)    ELC_EVENT_SDHIMMC##channel##_ACCS
-#define _ELC_EVENT_SDMMC_CARD(channel)    ELC_EVENT_SDHIMMC##channel##_CARD
-#define _ELC_EVENT_SDMMC_DMA_REQ(channel) ELC_EVENT_SDHIMMC##channel##_DMA_REQ
-
-#define ELC_EVENT_SDMMC_ACCS(channel)    _ELC_EVENT_SDMMC_ACCS(channel)
-#define ELC_EVENT_SDMMC_CARD(channel)    _ELC_EVENT_SDMMC_CARD(channel)
-#define ELC_EVENT_SDMMC_DMA_REQ(channel) _ELC_EVENT_SDMMC_DMA_REQ(channel)
+#define EVENT_SDMMC_ACCS(channel)    BSP_PRV_IELS_ENUM(CONCAT(EVENT_SDHIMMC, channel, _ACCS))
+#define EVENT_SDMMC_CARD(channel)    BSP_PRV_IELS_ENUM(CONCAT(EVENT_SDHIMMC, channel, _CARD))
+#define EVENT_SDMMC_DMA_REQ(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_SDHIMMC, channel, _DMA_REQ))
 
 #define RA_SDMMC_IRQ_CONFIG_INIT(index)                                                            \
 	do {                                                                                       \
 		ARG_UNUSED(dev);                                                                   \
                                                                                                    \
 		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, accs, irq)] =                              \
-			ELC_EVENT_SDMMC_ACCS(DT_INST_PROP(index, channel));                        \
+			EVENT_SDMMC_ACCS(DT_INST_PROP(index, channel));                            \
 		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, card, irq)] =                              \
-			ELC_EVENT_SDMMC_CARD(DT_INST_PROP(index, channel));                        \
+			EVENT_SDMMC_CARD(DT_INST_PROP(index, channel));                            \
 		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, dma_req, irq)] =                           \
-			ELC_EVENT_SDMMC_DMA_REQ(DT_INST_PROP(index, channel));                     \
+			EVENT_SDMMC_DMA_REQ(DT_INST_PROP(index, channel));                         \
                                                                                                    \
 		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, accs, irq),                                 \
 			    DT_INST_IRQ_BY_NAME(index, accs, priority), ra_sdmmc_accs_isr,         \
diff --git a/drivers/sdhc/sdhc_spi.c b/drivers/sdhc/sdhc_spi.c
index d6ec2429ace..aaf75ebf100 100644
--- a/drivers/sdhc/sdhc_spi.c
+++ b/drivers/sdhc/sdhc_spi.c
@@ -183,8 +183,13 @@ static int sdhc_spi_card_busy(const struct device *dev)
 	int ret;
 	uint8_t response;
 
+	/* Request SPI bus to be active */
+	if (pm_device_runtime_get(config->spi_dev) < 0) {
+		return -EIO;
+	}
 
 	ret = sdhc_spi_rx(config->spi_dev, data->spi_cfg, &response, 1);
+	(void)pm_device_runtime_put(config->spi_dev);
 	if (ret) {
 		return -EIO;
 	}
diff --git a/drivers/sensor/CMakeLists.txt b/drivers/sensor/CMakeLists.txt
index 679d9c3c6e4..7b26ff5d2fa 100644
--- a/drivers/sensor/CMakeLists.txt
+++ b/drivers/sensor/CMakeLists.txt
@@ -7,17 +7,22 @@ add_subdirectory(aosong)
 add_subdirectory(asahi_kasei)
 add_subdirectory(bosch)
 add_subdirectory(espressif)
+add_subdirectory(everlight)
 add_subdirectory(honeywell)
 add_subdirectory(infineon)
 add_subdirectory(ite)
 add_subdirectory(jedec)
+add_subdirectory(liteon)
 add_subdirectory(maxim)
 add_subdirectory(meas)
+add_subdirectory(melexis)
 add_subdirectory(memsic)
 add_subdirectory(microchip)
 add_subdirectory(nordic)
 add_subdirectory(nuvoton)
 add_subdirectory(nxp)
+add_subdirectory(pixart)
+add_subdirectory(realtek)
 add_subdirectory(renesas)
 add_subdirectory(rohm)
 add_subdirectory(seeed)
@@ -48,7 +53,6 @@ add_subdirectory_ifdef(CONFIG_IST8310 ist8310)
 add_subdirectory_ifdef(CONFIG_LM35 lm35)
 add_subdirectory_ifdef(CONFIG_LM75 lm75)
 add_subdirectory_ifdef(CONFIG_LM77 lm77)
-add_subdirectory_ifdef(CONFIG_LTR_F216A ltrf216a)
 add_subdirectory_ifdef(CONFIG_MHZ19B mhz19b)
 add_subdirectory_ifdef(CONFIG_NCT75 nct75)
 add_subdirectory_ifdef(CONFIG_NTC_THERMISTOR ntc_thermistor)
@@ -75,3 +79,15 @@ zephyr_library_sources_ifdef(CONFIG_SENSOR_SHELL sensor_shell.c)
 zephyr_library_sources_ifdef(CONFIG_SENSOR_SHELL_STREAM sensor_shell_stream.c)
 zephyr_library_sources_ifdef(CONFIG_SENSOR_SHELL_BATTERY shell_battery.c)
 zephyr_library_sources_ifdef(CONFIG_SENSOR_ASYNC_API sensor_decoders_init.c default_rtio_sensor.c)
+
+dt_has_chosen(has_zephyr_sensor_clock PROPERTY "zephyr,sensor-clock")
+
+if(CONFIG_SENSOR_CLOCK_RTC OR CONFIG_SENSOR_CLOCK_COUNTER)
+  if(has_zephyr_sensor_clock)
+    zephyr_library_sources(sensor_clock_external.c)
+  else()
+    message(FATAL_ERROR "Sensor clock type (RTC or Counter) is selected, but no zephyr,sensor-clock is defined in the device tree.")
+  endif()
+elseif(CONFIG_SENSOR_CLOCK_SYSTEM)
+  zephyr_library_sources(sensor_clock_sys.c)
+endif()
diff --git a/drivers/sensor/Kconfig b/drivers/sensor/Kconfig
index 4c6bfc3c413..8cda03acc08 100644
--- a/drivers/sensor/Kconfig
+++ b/drivers/sensor/Kconfig
@@ -82,6 +82,8 @@ config SENSOR_SHELL_MAX_TRIGGER_DEVICES
 config SENSOR_INFO
 	bool "Sensor Info iterable section"
 
+source "drivers/sensor/Kconfig.sensor_clock"
+
 comment "Device Drivers"
 
 # zephyr-keep-sorted-start
@@ -91,17 +93,22 @@ source "drivers/sensor/aosong/Kconfig"
 source "drivers/sensor/asahi_kasei/Kconfig"
 source "drivers/sensor/bosch/Kconfig"
 source "drivers/sensor/espressif/Kconfig"
+source "drivers/sensor/everlight/Kconfig"
 source "drivers/sensor/honeywell/Kconfig"
 source "drivers/sensor/infineon/Kconfig"
 source "drivers/sensor/ite/Kconfig"
 source "drivers/sensor/jedec/Kconfig"
+source "drivers/sensor/liteon/Kconfig"
 source "drivers/sensor/maxim/Kconfig"
 source "drivers/sensor/meas/Kconfig"
+source "drivers/sensor/melexis/Kconfig"
 source "drivers/sensor/memsic/Kconfig"
 source "drivers/sensor/microchip/Kconfig"
 source "drivers/sensor/nordic/Kconfig"
 source "drivers/sensor/nuvoton/Kconfig"
 source "drivers/sensor/nxp/Kconfig"
+source "drivers/sensor/pixart/Kconfig"
+source "drivers/sensor/realtek/Kconfig"
 source "drivers/sensor/renesas/Kconfig"
 source "drivers/sensor/rohm/Kconfig"
 source "drivers/sensor/seeed/Kconfig"
@@ -114,13 +121,15 @@ source "drivers/sensor/vishay/Kconfig"
 source "drivers/sensor/wsen/Kconfig"
 # zephyr-keep-sorted-stop
 
+# zephyr-keep-sorted-start
 source "drivers/sensor/a01nyub/Kconfig"
 source "drivers/sensor/amd_sb_tsi/Kconfig"
 source "drivers/sensor/amg88xx/Kconfig"
 source "drivers/sensor/apds9253/Kconfig"
-source "drivers/sensor/apds9960/Kconfig"
 source "drivers/sensor/apds9306/Kconfig"
+source "drivers/sensor/apds9960/Kconfig"
 source "drivers/sensor/current_amp/Kconfig"
+source "drivers/sensor/ene_tach_kb1200/Kconfig"
 source "drivers/sensor/ens160/Kconfig"
 source "drivers/sensor/explorir_m/Kconfig"
 source "drivers/sensor/f75303/Kconfig"
@@ -132,7 +141,6 @@ source "drivers/sensor/ist8310/Kconfig"
 source "drivers/sensor/lm35/Kconfig"
 source "drivers/sensor/lm75/Kconfig"
 source "drivers/sensor/lm77/Kconfig"
-source "drivers/sensor/ltrf216a/Kconfig"
 source "drivers/sensor/mhz19b/Kconfig"
 source "drivers/sensor/nct75/Kconfig"
 source "drivers/sensor/ntc_thermistor/Kconfig"
@@ -147,6 +155,6 @@ source "drivers/sensor/tsic_xx6/Kconfig"
 source "drivers/sensor/veaa_x_3/Kconfig"
 source "drivers/sensor/voltage_divider/Kconfig"
 source "drivers/sensor/xbr818/Kconfig"
-source "drivers/sensor/ene_tach_kb1200/Kconfig"
+# zephyr-keep-sorted-stop
 
 endif # SENSOR
diff --git a/drivers/sensor/Kconfig.sensor_clock b/drivers/sensor/Kconfig.sensor_clock
new file mode 100644
index 00000000000..be985746197
--- /dev/null
+++ b/drivers/sensor/Kconfig.sensor_clock
@@ -0,0 +1,30 @@
+# Sensor clock configuration options
+# Copyright(c) 2024 Cienet
+# SPDX-License-Identifier: Apache-2.0
+
+config SENSOR_CLOCK
+	bool
+	default y if SENSOR_ASYNC_API
+	help
+	  Configure the sensor clock source for the system.
+
+if SENSOR_CLOCK
+
+choice
+	prompt "Sensor clock type"
+	default SENSOR_CLOCK_SYSTEM
+	help
+	  Select the clock source to be used for sensor timing.
+
+config SENSOR_CLOCK_SYSTEM
+	bool "Use the system counter for sensor time"
+
+config SENSOR_CLOCK_COUNTER
+	bool "Use a counter device/API for sensor time"
+
+config SENSOR_CLOCK_RTC
+	bool "Use an RTC device/API for sensor time"
+
+endchoice
+
+endif # SENSOR_CLOCK
diff --git a/drivers/sensor/Kconfig.trigger_template b/drivers/sensor/Kconfig.trigger_template
index 7cb98e10e9e..37f7121f003 100644
--- a/drivers/sensor/Kconfig.trigger_template
+++ b/drivers/sensor/Kconfig.trigger_template
@@ -4,6 +4,7 @@
 
 choice "$(module)_TRIGGER_MODE"
 	prompt "Trigger mode"
+	default $(module)_TRIGGER_NONE
 	help
 	  Specify the type of triggering to be used by the sensor module.
 
diff --git a/drivers/sensor/adi/adltc2990/adltc2990.c b/drivers/sensor/adi/adltc2990/adltc2990.c
index f1d5e540842..912b0acf5f7 100644
--- a/drivers/sensor/adi/adltc2990/adltc2990.c
+++ b/drivers/sensor/adi/adltc2990/adltc2990.c
@@ -1,15 +1,19 @@
 /*
  * SPDX-FileCopyrightText: Copyright (c) 2023 Carl Zeiss Meditec AG
+ * SPDX-FileCopyrightText: Copyright (c) 2024 Jilay Sandeep Pandya
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #define DT_DRV_COMPAT adi_adltc2990
 
+#include <stdbool.h>
+
 #include <zephyr/sys/util.h>
 #include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/sensor/adltc2990.h>
 
 #include "adltc2990_reg.h"
-#include "adltc2990.h"
+#include "adltc2990_internal.h"
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(adltc2990, CONFIG_SENSOR_LOG_LEVEL);
@@ -30,26 +34,25 @@ static enum adltc2990_monitoring_type adltc2990_get_v1_v2_measurement_modes(uint
 
 	switch (mode_2_0) {
 	case ADLTC2990_MODE_V1_V2_TR2:
-	case ADLTC2990_MODE_V1_V2_V3_V4: {
+	case ADLTC2990_MODE_V1_V2_V3_V4:
 		type = VOLTAGE_SINGLEENDED;
 		break;
-	}
+
 	case ADLTC2990_MODE_V1_MINUS_V2_TR2:
 	case ADLTC2990_MODE_V1_MINUS_V2_V3_V4:
-	case ADLTC2990_MODE_V1_MINUS_V2_V3_MINUS_V4: {
+	case ADLTC2990_MODE_V1_MINUS_V2_V3_MINUS_V4:
 		type = VOLTAGE_DIFFERENTIAL;
 		break;
-	}
+
 	case ADLTC2990_MODE_TR1_V3_V4:
-	case ADLTC2990_MODE_TR1_V3_MINUS_V4: {
+	case ADLTC2990_MODE_TR1_V3_MINUS_V4:
 	case ADLTC2990_MODE_TR1_TR2:
 		type = TEMPERATURE;
 		break;
-	}
-	default: {
+
+	default:
 		break;
 	}
-	}
 	return type;
 }
 
@@ -70,38 +73,34 @@ static enum adltc2990_monitoring_type adltc2990_get_v3_v4_measurement_modes(uint
 	switch (mode_2_0) {
 	case ADLTC2990_MODE_V1_V2_TR2:
 	case ADLTC2990_MODE_V1_MINUS_V2_TR2:
-	case ADLTC2990_MODE_TR1_TR2: {
+	case ADLTC2990_MODE_TR1_TR2:
 		type = TEMPERATURE;
 		break;
-	}
 
 	case ADLTC2990_MODE_V1_MINUS_V2_V3_V4:
 	case ADLTC2990_MODE_TR1_V3_V4:
-	case ADLTC2990_MODE_V1_V2_V3_V4: {
+	case ADLTC2990_MODE_V1_V2_V3_V4:
 		type = VOLTAGE_SINGLEENDED;
 		break;
-	}
+
 	case ADLTC2990_MODE_TR1_V3_MINUS_V4:
-	case ADLTC2990_MODE_V1_MINUS_V2_V3_MINUS_V4: {
+	case ADLTC2990_MODE_V1_MINUS_V2_V3_MINUS_V4:
 		type = VOLTAGE_DIFFERENTIAL;
 		break;
-	}
-	default: {
+
+	default:
 		break;
 	}
-	}
 	return type;
 }
 
-static int adltc2990_is_busy(const struct device *dev, bool *is_busy)
+int adltc2990_is_busy(const struct device *dev, bool *is_busy)
 {
 	const struct adltc2990_config *cfg = dev->config;
 	uint8_t status_reg = 0;
-	int ret;
 
-	ret = i2c_reg_read_byte_dt(&cfg->bus, ADLTC2990_REG_STATUS, &status_reg);
-	if (ret) {
-		return ret;
+	if (i2c_reg_read_byte_dt(&cfg->bus, ADLTC2990_REG_STATUS, &status_reg)) {
+		return -EIO;
 	}
 
 	*is_busy = status_reg & BIT(0);
@@ -134,17 +133,37 @@ static void adltc2990_get_v3_v4_val(const struct device *dev, struct sensor_valu
 	}
 }
 
-static int adltc2990_trigger_measurement(const struct device *dev)
+int adltc2990_trigger_measurement(const struct device *dev,
+				  enum adltc2990_acquisition_format format)
 {
 	const struct adltc2990_config *cfg = dev->config;
+	struct adltc2990_data *data = dev->data;
+
+	if (data->acq_format == format) {
+		goto trigger_conversion;
+	}
+
+	data->acq_format = format;
+	uint8_t ctrl_reg_setting;
+
+	if (i2c_reg_read_byte_dt(&cfg->bus, ADLTC2990_REG_CONTROL, &ctrl_reg_setting)) {
+		LOG_ERR("reading control register failed.");
+		return -EIO;
+	}
+
+	ctrl_reg_setting |= format << 6;
+	if (i2c_reg_write_byte_dt(&cfg->bus, ADLTC2990_REG_CONTROL, ctrl_reg_setting)) {
+		LOG_ERR("configuring for single bus failed.");
+		return -EIO;
+	}
 
+trigger_conversion:
 	return i2c_reg_write_byte_dt(&cfg->bus, ADLTC2990_REG_TRIGGER, 0x1);
 }
 
 static int adltc2990_fetch_property_value(const struct device *dev,
 					  enum adltc2990_monitoring_type type,
-					  enum adltc2990_monitor_pins pin,
-					  int32_t *output)
+					  enum adltc2990_monitor_pins pin, int32_t *output)
 {
 	const struct adltc2990_config *cfg = dev->config;
 
@@ -152,52 +171,49 @@ static int adltc2990_fetch_property_value(const struct device *dev,
 	uint8_t msb_address, lsb_address;
 
 	switch (pin) {
-	case V1: {
+	case V1:
 		msb_address = ADLTC2990_REG_V1_MSB;
 		lsb_address = ADLTC2990_REG_V1_LSB;
 		break;
-	}
-	case V2: {
+
+	case V2:
 		msb_address = ADLTC2990_REG_V2_MSB;
 		lsb_address = ADLTC2990_REG_V2_LSB;
 		break;
-	}
-	case V3: {
+
+	case V3:
 		msb_address = ADLTC2990_REG_V3_MSB;
 		lsb_address = ADLTC2990_REG_V3_LSB;
 		break;
-	}
-	case V4: {
+
+	case V4:
 		msb_address = ADLTC2990_REG_V4_MSB;
 		lsb_address = ADLTC2990_REG_V4_LSB;
 		break;
-	}
-	case INTERNAL_TEMPERATURE: {
+
+	case INTERNAL_TEMPERATURE:
 		msb_address = ADLTC2990_REG_INTERNAL_TEMP_MSB;
 		lsb_address = ADLTC2990_REG_INTERNAL_TEMP_LSB;
 		break;
-	}
-	case SUPPLY_VOLTAGE: {
+
+	case SUPPLY_VOLTAGE:
 		msb_address = ADLTC2990_REG_VCC_MSB;
 		lsb_address = ADLTC2990_REG_VCC_LSB;
 		break;
-	}
-	default: {
+
+	default:
 		LOG_ERR("Trying to access illegal register");
 		return -EINVAL;
 	}
-	}
-	int ret;
 
-	ret = i2c_reg_read_byte_dt(&cfg->bus, msb_address, &msb_value);
-	if (ret) {
-		return ret;
+	if (i2c_reg_read_byte_dt(&cfg->bus, msb_address, &msb_value)) {
+		return -EIO;
 	}
 
-	ret = i2c_reg_read_byte_dt(&cfg->bus, lsb_address, &lsb_value);
-	if (ret) {
-		return ret;
+	if (i2c_reg_read_byte_dt(&cfg->bus, lsb_address, &lsb_value)) {
+		return -EIO;
 	}
+
 	uint16_t conversion_factor;
 	uint8_t negative_bit_index = 14U, sensor_val_divisor = 100U;
 
@@ -228,6 +244,7 @@ static int adltc2990_fetch_property_value(const struct device *dev,
 static int adltc2990_init(const struct device *dev)
 {
 	const struct adltc2990_config *cfg = dev->config;
+	struct adltc2990_data *data = dev->data;
 	int err;
 
 	if (!i2c_is_ready_dt(&cfg->bus)) {
@@ -235,17 +252,16 @@ static int adltc2990_init(const struct device *dev)
 		return -ENODEV;
 	}
 
-	const uint8_t ctrl_reg_setting = cfg->temp_format << 7 | cfg->acq_format << 6 | 0 << 5 |
+	const uint8_t ctrl_reg_setting = cfg->temp_format << 7 | data->acq_format << 6 | 0 << 5 |
 					 cfg->measurement_mode[1] << 3 | cfg->measurement_mode[0];
 
 	LOG_DBG("Setting Control Register to: 0x%x", ctrl_reg_setting);
-	err = i2c_reg_write_byte_dt(&cfg->bus, ADLTC2990_REG_CONTROL, ctrl_reg_setting);
-	if (err < 0) {
-		LOG_ERR("configuring for single bus failed: %d", err);
-		return err;
+	if (i2c_reg_write_byte_dt(&cfg->bus, ADLTC2990_REG_CONTROL, ctrl_reg_setting)) {
+		LOG_ERR("configuring for single bus failed.");
+		return -EIO;
 	}
 
-	err = adltc2990_trigger_measurement(dev);
+	err = adltc2990_trigger_measurement(dev, data->acq_format);
 	if (err < 0) {
 		LOG_ERR("triggering measurement failed: %d", err);
 	}
@@ -254,6 +270,171 @@ static int adltc2990_init(const struct device *dev)
 	return 0;
 }
 
+static int fetch_pin_differential_voltage_value(const struct device *dev,
+						const enum adltc2990_monitoring_type mode,
+						const enum adltc2990_monitor_pins pin)
+{
+	if (mode != VOLTAGE_DIFFERENTIAL) {
+		LOG_DBG("Pin is not configured to measure voltage differential");
+		return 0;
+	}
+
+	struct adltc2990_data *data = dev->data;
+	int32_t value;
+	int ret;
+
+	ret = adltc2990_fetch_property_value(dev, VOLTAGE_DIFFERENTIAL, pin, &value);
+	if (ret) {
+		return ret;
+	}
+
+	switch (pin) {
+	case V1:
+	case V2:
+		data->pins_v1_v2_values[0] = value;
+		break;
+
+	case V3:
+	case V4:
+		data->pins_v3_v4_values[0] = value;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int fetch_pin_single_ended_voltage_value(const struct device *dev,
+						const enum adltc2990_monitoring_type mode,
+						const enum adltc2990_monitor_pins pin_1,
+						const enum adltc2990_monitor_pins pin_2)
+{
+	if (mode != VOLTAGE_SINGLEENDED) {
+		LOG_DBG("Pin is not configured to measure voltage single ended");
+		return 0;
+	}
+
+	const struct adltc2990_config *cfg = dev->config;
+	struct adltc2990_data *data = dev->data;
+	int value_1, value_2, ret;
+
+	ret = adltc2990_fetch_property_value(dev, VOLTAGE_SINGLEENDED, pin_1, &value_1);
+	if (ret) {
+		return ret;
+	}
+
+	ret = adltc2990_fetch_property_value(dev, VOLTAGE_SINGLEENDED, pin_2, &value_2);
+	if (ret) {
+		return ret;
+	}
+
+	if (pin_1 == V1 && pin_2 == V2) {
+
+		uint32_t v1_r1 = cfg->pins_v1_v2.voltage_divider_resistors.v1_r1_r2[0];
+		uint32_t v1_r2 = cfg->pins_v1_v2.voltage_divider_resistors.v1_r1_r2[1];
+
+		float voltage_divider_ratio = (v1_r1 + v1_r2) / (float)v1_r2;
+
+		data->pins_v1_v2_values[0] = value_1 * voltage_divider_ratio;
+
+		uint32_t v2_r1 = cfg->pins_v1_v2.voltage_divider_resistors.v2_r1_r2[0];
+		uint32_t v2_r2 = cfg->pins_v1_v2.voltage_divider_resistors.v2_r1_r2[1];
+
+		voltage_divider_ratio = (v2_r1 + v2_r2) / (float)v2_r2;
+
+		data->pins_v1_v2_values[1] = value_2 * voltage_divider_ratio;
+
+	} else if (pin_1 == V3 && pin_2 == V4) {
+
+		uint32_t v3_r1 = cfg->pins_v3_v4.voltage_divider_resistors.v3_r1_r2[0];
+		uint32_t v3_r2 = cfg->pins_v3_v4.voltage_divider_resistors.v3_r1_r2[1];
+
+		float voltage_divider_ratio = (v3_r1 + v3_r2) / (float)v3_r2;
+
+		data->pins_v3_v4_values[0] = value_1 * voltage_divider_ratio;
+
+		uint32_t v4_r1 = cfg->pins_v3_v4.voltage_divider_resistors.v4_r1_r2[0];
+		uint32_t v4_r2 = cfg->pins_v3_v4.voltage_divider_resistors.v4_r1_r2[1];
+
+		voltage_divider_ratio = (v4_r1 + v4_r2) / (float)v4_r2;
+
+		data->pins_v3_v4_values[1] = value_2 * voltage_divider_ratio;
+
+	} else {
+		LOG_ERR("Invalid pin configuration");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int fetch_pin_temperature_value(const struct device *dev,
+				       const enum adltc2990_monitoring_type mode,
+				       const enum adltc2990_monitor_pins pin)
+{
+	if (mode != TEMPERATURE) {
+		LOG_DBG("Pin is not configured to measure temperature");
+		return 0;
+	}
+
+	struct adltc2990_data *data = dev->data;
+	int32_t value;
+	int ret;
+
+	ret = adltc2990_fetch_property_value(dev, TEMPERATURE, pin, &value);
+	if (ret) {
+		return ret;
+	}
+
+	switch (pin) {
+	case V1:
+	case V2:
+		data->pins_v1_v2_values[0] = value;
+		break;
+
+	case V3:
+	case V4:
+		data->pins_v3_v4_values[0] = value;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int fetch_pin_current_value(const struct device *dev,
+				   const enum adltc2990_monitoring_type mode,
+				   const enum adltc2990_monitor_pins pin)
+{
+	int ret;
+
+	ret = fetch_pin_differential_voltage_value(dev, mode, pin);
+	if (ret) {
+		return ret;
+	}
+
+	const struct adltc2990_config *cfg = dev->config;
+	struct adltc2990_data *data = dev->data;
+
+	switch (pin) {
+	case V1:
+	case V2:
+		data->pins_v1_v2_values[0] *= (ADLTC2990_MICROOHM_CONVERSION_FACTOR /
+					       (float)cfg->pins_v1_v2.pins_current_resistor);
+		break;
+
+	case V3:
+	case V4:
+		data->pins_v3_v4_values[0] *= (ADLTC2990_MICROOHM_CONVERSION_FACTOR /
+					       (float)cfg->pins_v3_v4.pins_current_resistor);
+		break;
+
+	default:
+		break;
+	}
+
+	return 0;
+}
+
 static int adltc2990_sample_fetch(const struct device *dev, enum sensor_channel chan)
 {
 	struct adltc2990_data *data = dev->data;
@@ -262,13 +443,11 @@ static int adltc2990_sample_fetch(const struct device *dev, enum sensor_channel
 		cfg->measurement_mode[1], cfg->measurement_mode[0]);
 	enum adltc2990_monitoring_type mode_v3_v4 = adltc2990_get_v3_v4_measurement_modes(
 		cfg->measurement_mode[1], cfg->measurement_mode[0]);
-
-	float voltage_divider_ratio;
 	int ret;
 	int32_t value;
 
 	switch (chan) {
-	case SENSOR_CHAN_DIE_TEMP: {
+	case SENSOR_CHAN_DIE_TEMP:
 		ret = adltc2990_fetch_property_value(dev, TEMPERATURE, INTERNAL_TEMPERATURE,
 						     &value);
 		if (ret) {
@@ -276,32 +455,26 @@ static int adltc2990_sample_fetch(const struct device *dev, enum sensor_channel
 		}
 		data->internal_temperature = value;
 		break;
-	}
-	case SENSOR_CHAN_CURRENT: {
+
+	case SENSOR_CHAN_CURRENT:
 		if (!(mode_v1_v2 == VOLTAGE_DIFFERENTIAL || mode_v3_v4 == VOLTAGE_DIFFERENTIAL)) {
 			LOG_ERR("Sensor is not configured to measure Current");
 			return -EINVAL;
 		}
-		if (mode_v1_v2 == VOLTAGE_DIFFERENTIAL) {
-			ret = adltc2990_fetch_property_value(dev, VOLTAGE_DIFFERENTIAL, V1, &value);
-			if (ret) {
-				return ret;
-			}
-			data->pins_v1_v2_values[0] =
-				value * (ADLTC2990_MICROOHM_CONVERSION_FACTOR /
-				 (float)cfg->pins_v1_v2.pins_current_resistor);
+
+		ret = fetch_pin_current_value(dev, mode_v1_v2, V1);
+		if (ret) {
+			return ret;
 		}
-		if (mode_v3_v4 == VOLTAGE_DIFFERENTIAL) {
-			ret = adltc2990_fetch_property_value(dev, VOLTAGE_DIFFERENTIAL, V3, &value);
-			if (ret) {
-				return ret;
-			}
-			data->pins_v3_v4_values[0] = value * (ADLTC2990_MICROOHM_CONVERSION_FACTOR /
-				 (float)cfg->pins_v3_v4.pins_current_resistor);
+
+		ret = fetch_pin_current_value(dev, mode_v3_v4, V3);
+		if (ret) {
+			return ret;
 		}
+
 		break;
-	}
-	case SENSOR_CHAN_VOLTAGE: {
+
+	case SENSOR_CHAN_VOLTAGE:
 		ret = adltc2990_fetch_property_value(dev, VOLTAGE_SINGLEENDED, SUPPLY_VOLTAGE,
 						     &value);
 		if (ret) {
@@ -309,109 +482,49 @@ static int adltc2990_sample_fetch(const struct device *dev, enum sensor_channel
 		}
 		data->supply_voltage = value + 2500000;
 
-		if (mode_v1_v2 == VOLTAGE_DIFFERENTIAL) {
-			ret = adltc2990_fetch_property_value(dev, VOLTAGE_DIFFERENTIAL, V1, &value);
-			if (ret) {
-				return ret;
-			}
-			data->pins_v1_v2_values[0] = value;
-		} else if (mode_v1_v2 == VOLTAGE_SINGLEENDED) {
-			uint32_t v1_r1 = cfg->pins_v1_v2.voltage_divider_resistors.v1_r1_r2[0];
-
-			uint32_t v1_r2 = cfg->pins_v1_v2.voltage_divider_resistors.v1_r1_r2[1];
-
-			voltage_divider_ratio = (v1_r1 + v1_r2) / (float)v1_r2;
-			ret = adltc2990_fetch_property_value(dev, VOLTAGE_SINGLEENDED, V1, &value);
-			if (ret) {
-				return ret;
-			}
-			data->pins_v1_v2_values[0] = value * voltage_divider_ratio;
-
-			uint32_t v2_r1 = cfg->pins_v1_v2.voltage_divider_resistors.v2_r1_r2[0];
-
-			uint32_t v2_r2 = cfg->pins_v1_v2.voltage_divider_resistors.v2_r1_r2[1];
-
-			voltage_divider_ratio = (v2_r1 + v2_r2) / (float)v2_r2;
-			ret = adltc2990_fetch_property_value(dev, VOLTAGE_SINGLEENDED, V2, &value);
-			if (ret) {
-				return ret;
-			}
-			data->pins_v1_v2_values[1] = value * voltage_divider_ratio;
+		ret = fetch_pin_differential_voltage_value(dev, mode_v1_v2, V1);
+		if (ret) {
+			return ret;
 		}
 
-		if (mode_v3_v4 == VOLTAGE_DIFFERENTIAL) {
-			ret = adltc2990_fetch_property_value(dev, VOLTAGE_DIFFERENTIAL, V3, &value);
-			if (ret) {
-				return ret;
-			}
-			data->pins_v3_v4_values[0] = value;
-		} else if (mode_v3_v4 == VOLTAGE_SINGLEENDED) {
-			uint32_t v3_r1 = cfg->pins_v3_v4.voltage_divider_resistors.v3_r1_r2[0];
-
-			uint32_t v3_r2 = cfg->pins_v3_v4.voltage_divider_resistors.v3_r1_r2[1];
-
-			voltage_divider_ratio = (v3_r1 + v3_r2) / (float)v3_r2;
-			ret = adltc2990_fetch_property_value(dev, VOLTAGE_SINGLEENDED, V3, &value);
-			if (ret) {
-				return ret;
-			}
-			data->pins_v3_v4_values[0] = value * voltage_divider_ratio;
-
-			uint32_t v4_r1 = cfg->pins_v3_v4.voltage_divider_resistors.v4_r1_r2[0];
-
-			uint32_t v4_r2 = cfg->pins_v3_v4.voltage_divider_resistors.v4_r1_r2[1];
+		ret = fetch_pin_differential_voltage_value(dev, mode_v3_v4, V3);
+		if (ret) {
+			return ret;
+		}
 
-			voltage_divider_ratio = (v4_r1 + v4_r2) / (float)v4_r2;
+		ret = fetch_pin_single_ended_voltage_value(dev, mode_v1_v2, V1, V2);
+		if (ret) {
+			return ret;
+		}
 
-			ret = adltc2990_fetch_property_value(dev, VOLTAGE_SINGLEENDED, V4, &value);
-			if (ret) {
-				return ret;
-			}
-			data->pins_v3_v4_values[1] = value * voltage_divider_ratio;
+		ret = fetch_pin_single_ended_voltage_value(dev, mode_v3_v4, V3, V4);
+		if (ret) {
+			return ret;
 		}
+
 		break;
-	}
-	case SENSOR_CHAN_AMBIENT_TEMP: {
+
+	case SENSOR_CHAN_AMBIENT_TEMP:
 		if (!(mode_v1_v2 == TEMPERATURE || mode_v3_v4 == TEMPERATURE)) {
 			LOG_ERR("Sensor is not configured to measure Ambient Temperature");
 			return -EINVAL;
 		}
-		if (mode_v1_v2 == TEMPERATURE) {
-			ret = adltc2990_fetch_property_value(dev, TEMPERATURE, V1, &value);
-			if (ret) {
-				return ret;
-			}
-			data->pins_v1_v2_values[0] = value;
-		}
-		if (mode_v3_v4 == TEMPERATURE) {
-			ret = adltc2990_fetch_property_value(dev, TEMPERATURE, V3, &value);
-			if (ret) {
-				return ret;
-			}
-			data->pins_v3_v4_values[0] = value;
-		}
-		break;
-	}
-	case SENSOR_CHAN_ALL: {
-		bool is_busy;
 
-		ret = adltc2990_is_busy(dev, &is_busy);
+		ret = fetch_pin_temperature_value(dev, mode_v1_v2, V1);
 		if (ret) {
 			return ret;
 		}
 
-		if (is_busy) {
-			LOG_INF("ADLTC2990 conversion ongoing");
-			return -EBUSY;
+		ret = fetch_pin_temperature_value(dev, mode_v3_v4, V3);
+		if (ret) {
+			return ret;
 		}
-		adltc2990_trigger_measurement(dev);
 		break;
-	}
-	default: {
+
+	default:
 		LOG_ERR("does not measure channel: %d", chan);
 		return -ENOTSUP;
 	}
-	}
 
 	return 0;
 }
@@ -433,13 +546,13 @@ static int adltc2990_channel_get(const struct device *dev, enum sensor_channel c
 	uint8_t offset_index = 0, num_values_v1_v2 = 0, num_values_v3_v4 = 0;
 
 	switch (chan) {
-	case SENSOR_CHAN_DIE_TEMP: {
+	case SENSOR_CHAN_DIE_TEMP:
 		val->val1 = (data->internal_temperature) / 1000000;
 		val->val2 = (data->internal_temperature) % 1000000;
 		LOG_DBG("Internal Temperature Value is:%d.%d", val->val1, val->val2);
 		break;
-	}
-	case SENSOR_CHAN_VOLTAGE: {
+
+	case SENSOR_CHAN_VOLTAGE:
 		if (mode_v1_v2 == VOLTAGE_SINGLEENDED) {
 			LOG_DBG("Getting V1,V2");
 			num_values_v1_v2 = ADLTC2990_VOLTAGE_SINGLE_ENDED_VALUES;
@@ -458,8 +571,8 @@ static int adltc2990_channel_get(const struct device *dev, enum sensor_channel c
 		val[num_values_v1_v2 + num_values_v3_v4].val1 = data->supply_voltage / 1000000;
 		val[num_values_v1_v2 + num_values_v3_v4].val2 = data->supply_voltage % 1000000;
 		break;
-	}
-	case SENSOR_CHAN_CURRENT: {
+
+	case SENSOR_CHAN_CURRENT:
 		if (!(mode_v1_v2 == VOLTAGE_DIFFERENTIAL || mode_v3_v4 == VOLTAGE_DIFFERENTIAL)) {
 			LOG_ERR("Sensor is not configured to measure Current");
 			return -EINVAL;
@@ -476,8 +589,8 @@ static int adltc2990_channel_get(const struct device *dev, enum sensor_channel c
 			num_values_v3_v4 = ADLTC2990_CURRENT_VALUES;
 		}
 		break;
-	}
-	case SENSOR_CHAN_AMBIENT_TEMP: {
+
+	case SENSOR_CHAN_AMBIENT_TEMP:
 		if (!(mode_v1_v2 == TEMPERATURE || mode_v3_v4 == TEMPERATURE)) {
 			LOG_ERR("Sensor is not configured to measure Ambient Temperature");
 			return -EINVAL;
@@ -494,11 +607,10 @@ static int adltc2990_channel_get(const struct device *dev, enum sensor_channel c
 			num_values_v3_v4 = ADLTC2990_TEMP_VALUES;
 		}
 		break;
-	}
-	default: {
+
+	default:
 		return -ENOTSUP;
 	}
-	}
 
 	adltc2990_get_v1_v2_val(dev, val, num_values_v1_v2, &offset_index);
 	adltc2990_get_v3_v4_val(dev, val, num_values_v3_v4, &offset_index);
@@ -511,11 +623,12 @@ static DEVICE_API(sensor, adltc2990_driver_api) = {
 };
 
 #define ADLTC2990_DEFINE(inst)                                                                     \
-	static struct adltc2990_data adltc2990_data_##inst;                                        \
+	static struct adltc2990_data adltc2990_data_##inst = {                                     \
+		.acq_format = DT_INST_PROP(inst, acquistion_format),                               \
+	};                                                                                         \
 	static const struct adltc2990_config adltc2990_config_##inst = {                           \
 		.bus = I2C_DT_SPEC_INST_GET(inst),                                                 \
 		.temp_format = DT_INST_PROP(inst, temperature_format),                             \
-		.acq_format = DT_INST_PROP(inst, acquistion_format),                               \
 		.measurement_mode = DT_INST_PROP(inst, measurement_mode),                          \
 		.pins_v1_v2.pins_current_resistor =                                                \
 			DT_INST_PROP_OR(inst, pins_v1_v2_current_resistor, 1),                     \
diff --git a/drivers/sensor/adi/adltc2990/adltc2990.h b/drivers/sensor/adi/adltc2990/adltc2990.h
deleted file mode 100644
index af2d1995531..00000000000
--- a/drivers/sensor/adi/adltc2990/adltc2990.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2023 Carl Zeiss Meditec AG
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_DRIVERS_SENSOR_ADLTC2990_H
-#define ZEPHYR_DRIVERS_SENSOR_ADLTC2990_H
-
-#include <zephyr/types.h>
-#include <zephyr/device.h>
-#include <zephyr/drivers/gpio.h>
-#include <zephyr/drivers/i2c.h>
-#include <zephyr/drivers/sensor.h>
-
-enum adltc2990_monitor_pins {
-	V1,
-	V2,
-	V3,
-	V4,
-	INTERNAL_TEMPERATURE,
-	SUPPLY_VOLTAGE
-};
-
-enum adltc2990_monitoring_type {
-	NOTHING,
-	VOLTAGE_DIFFERENTIAL,
-	VOLTAGE_SINGLEENDED,
-	TEMPERATURE
-};
-
-union voltage_divider_resistors {
-	struct {
-		uint32_t v1_r1_r2[2];
-		uint32_t v2_r1_r2[2];
-	};
-	struct {
-		uint32_t v3_r1_r2[2];
-		uint32_t v4_r1_r2[2];
-	};
-};
-
-struct pins_configuration {
-	uint32_t pins_current_resistor;
-	union voltage_divider_resistors voltage_divider_resistors;
-};
-
-struct adltc2990_data {
-	int32_t internal_temperature;
-	int32_t supply_voltage;
-	int32_t pins_v1_v2_values[2];
-	int32_t pins_v3_v4_values[2];
-};
-
-struct adltc2990_config {
-	struct i2c_dt_spec bus;
-	uint8_t temp_format;
-	uint8_t acq_format;
-	uint8_t measurement_mode[2];
-	struct pins_configuration pins_v1_v2;
-	struct pins_configuration pins_v3_v4;
-};
-
-#endif /* ZEPHYR_DRIVERS_SENSOR_ADLTC2990_H */
diff --git a/drivers/sensor/adi/adltc2990/adltc2990_emul.c b/drivers/sensor/adi/adltc2990/adltc2990_emul.c
index 80078f21dc5..d4b9c310ea3 100644
--- a/drivers/sensor/adi/adltc2990/adltc2990_emul.c
+++ b/drivers/sensor/adi/adltc2990/adltc2990_emul.c
@@ -1,5 +1,6 @@
 /*
  * SPDX-FileCopyrightText: Copyright (c) 2023 Carl Zeiss Meditec AG
+ * SPDX-FileCopyrightText: Copyright (c) 2024 Jilay Sandeep Pandya
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -13,7 +14,7 @@
 #include <zephyr/logging/log.h>
 #include <zephyr/sys/util.h>
 
-#include "adltc2990.h"
+#include "adltc2990_internal.h"
 #include "adltc2990_reg.h"
 #include "adltc2990_emul.h"
 
diff --git a/drivers/sensor/adi/adltc2990/adltc2990_internal.h b/drivers/sensor/adi/adltc2990/adltc2990_internal.h
new file mode 100644
index 00000000000..a58db120ee9
--- /dev/null
+++ b/drivers/sensor/adi/adltc2990/adltc2990_internal.h
@@ -0,0 +1,64 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2023 Carl Zeiss Meditec AG
+ * SPDX-FileCopyrightText: Copyright (c) 2024 Jilay Sandeep Pandya
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_ADLTC2990_H
+#define ZEPHYR_DRIVERS_SENSOR_ADLTC2990_H
+
+#include <zephyr/types.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/sensor.h>
+
+enum adltc2990_monitor_pins {
+	V1,
+	V2,
+	V3,
+	V4,
+	INTERNAL_TEMPERATURE,
+	SUPPLY_VOLTAGE
+};
+
+enum adltc2990_monitoring_type {
+	NOTHING,
+	VOLTAGE_DIFFERENTIAL,
+	VOLTAGE_SINGLEENDED,
+	TEMPERATURE
+};
+
+union voltage_divider_resistors {
+	struct {
+		uint32_t v1_r1_r2[2];
+		uint32_t v2_r1_r2[2];
+	};
+	struct {
+		uint32_t v3_r1_r2[2];
+		uint32_t v4_r1_r2[2];
+	};
+};
+
+struct pins_configuration {
+	uint32_t pins_current_resistor;
+	union voltage_divider_resistors voltage_divider_resistors;
+};
+
+struct adltc2990_data {
+	uint8_t acq_format;
+	int32_t internal_temperature;
+	int32_t supply_voltage;
+	int32_t pins_v1_v2_values[2];
+	int32_t pins_v3_v4_values[2];
+};
+
+struct adltc2990_config {
+	struct i2c_dt_spec bus;
+	uint8_t temp_format;
+	uint8_t measurement_mode[2];
+	struct pins_configuration pins_v1_v2;
+	struct pins_configuration pins_v3_v4;
+};
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_ADLTC2990_H */
diff --git a/drivers/sensor/adi/adxl345/Kconfig b/drivers/sensor/adi/adxl345/Kconfig
index cb3680a86c5..e9799f51a61 100644
--- a/drivers/sensor/adi/adxl345/Kconfig
+++ b/drivers/sensor/adi/adxl345/Kconfig
@@ -13,6 +13,8 @@ config ADXL345
 	help
 	  Enable driver for ADXL345 Three-Axis Digital Accelerometer.
 
+if ADXL345
+
 choice ADXL345_TRIGGER_MODE
 	prompt "Trigger mode"
 	default ADXL345_TRIGGER_NONE
@@ -37,7 +39,6 @@ endchoice
 config ADXL345_STREAM
 	bool "Use FIFO to stream data"
 	select ADXL345_TRIGGER
-	default y
 	depends on (SPI_RTIO || I2C_RTIO)
 	depends on SENSOR_ASYNC_API
 	help
@@ -59,3 +60,5 @@ config ADXL345_THREAD_STACK_SIZE
 	default 1024
 	help
 	  Stack size of thread used by the driver to handle interrupts.
+
+endif # ADXL345
diff --git a/drivers/sensor/adi/adxl345/adxl345.c b/drivers/sensor/adi/adxl345/adxl345.c
index e887b749088..14463392bb7 100644
--- a/drivers/sensor/adi/adxl345/adxl345.c
+++ b/drivers/sensor/adi/adxl345/adxl345.c
@@ -229,7 +229,7 @@ static int adxl345_attr_set_odr(const struct device *dev,
 				const struct sensor_value *val)
 {
 	enum adxl345_odr odr;
-	struct adxl345_dev_config *cfg = (struct adxl345_dev_config *)dev->config;
+	struct adxl345_dev_data *data = dev->data;
 
 	switch (val->val1) {
 	case 12:
@@ -257,7 +257,7 @@ static int adxl345_attr_set_odr(const struct device *dev,
 	int ret = adxl345_set_odr(dev, odr);
 
 	if (ret == 0) {
-		cfg->odr = odr;
+		data->odr = odr;
 	}
 
 	return ret;
@@ -281,6 +281,7 @@ int adxl345_read_sample(const struct device *dev,
 {
 	int16_t raw_x, raw_y, raw_z;
 	uint8_t axis_data[6], status1;
+	struct adxl345_dev_data *data = dev->data;
 
 	if (!IS_ENABLED(CONFIG_ADXL345_TRIGGER)) {
 		do {
@@ -303,6 +304,9 @@ int adxl345_read_sample(const struct device *dev,
 	sample->y = raw_y;
 	sample->z = raw_z;
 
+	sample->selected_range = data->selected_range;
+	sample->is_full_res = data->is_full_res;
+
 	return 0;
 }
 
@@ -453,11 +457,13 @@ static int adxl345_init(const struct device *dev)
 		return -ENODEV;
 	}
 
+#if CONFIG_ADXL345_STREAM
 	rc = adxl345_reg_write_byte(dev, ADXL345_FIFO_CTL_REG, ADXL345_FIFO_STREAM_MODE);
 	if (rc < 0) {
 		LOG_ERR("FIFO enable failed\n");
 		return -EIO;
 	}
+#endif
 
 	rc = adxl345_reg_write_byte(dev, ADXL345_DATA_FORMAT_REG, ADXL345_RANGE_8G);
 	if (rc < 0) {
diff --git a/drivers/sensor/adi/adxl345/adxl345.h b/drivers/sensor/adi/adxl345/adxl345.h
index 44d47531831..8bc25f50340 100644
--- a/drivers/sensor/adi/adxl345/adxl345.h
+++ b/drivers/sensor/adi/adxl345/adxl345.h
@@ -156,6 +156,7 @@ struct adxl345_dev_data {
 	struct adxl345_fifo_config fifo_config;
 	uint8_t is_full_res;
 	uint8_t selected_range;
+	enum adxl345_odr odr;
 #ifdef CONFIG_ADXL345_TRIGGER
 	struct gpio_callback gpio_cb;
 
@@ -204,6 +205,7 @@ struct adxl345_sample {
 	uint8_t res: 7;
 #endif /* CONFIG_ADXL345_STREAM */
 	uint8_t selected_range;
+	bool is_full_res;
 	int16_t x;
 	int16_t y;
 	int16_t z;
diff --git a/drivers/sensor/adi/adxl345/adxl345_decoder.c b/drivers/sensor/adi/adxl345/adxl345_decoder.c
index 7a1bf53cb05..1f39fb9d1d1 100644
--- a/drivers/sensor/adi/adxl345/adxl345_decoder.c
+++ b/drivers/sensor/adi/adxl345/adxl345_decoder.c
@@ -6,17 +6,42 @@
 
 #include "adxl345.h"
 
-#ifdef CONFIG_ADXL345_STREAM
+/** The q-scale factor will always be the same, as the nominal LSB/g
+ * changes at the same rate the selected shift parameter per range:
+ *
+ * - At 2G: 256 LSB/g, 10-bits resolution.
+ * - At 4g: 128 LSB/g, 10-bits resolution.
+ * - At 8g: 64 LSB/g, 10-bits resolution.
+ * - At 16g 32 LSB/g, 10-bits resolution.
+ */
+static const uint32_t qscale_factor_no_full_res[] = {
+	/* (1.0 / Resolution-LSB-per-g * (2^31 / 2^5) * SENSOR_G / 1000000 */
+	[ADXL345_RANGE_2G] = UINT32_C(2570754),
+	/* (1.0 / Resolution-LSB-per-g) * (2^31 / 2^6) * SENSOR_G / 1000000  */
+	[ADXL345_RANGE_4G] = UINT32_C(2570754),
+	/* (1.0 / Resolution-LSB-per-g) * (2^31 / 2^7) ) * SENSOR_G / 1000000 */
+	[ADXL345_RANGE_8G] = UINT32_C(2570754),
+	/* (1.0 / Resolution-LSB-per-g) * (2^31 / 2^8) ) * SENSOR_G / 1000000 */
+	[ADXL345_RANGE_16G] = UINT32_C(2570754),
+};
 
-#define SENSOR_SCALING_FACTOR (SENSOR_G / (16 * 1000 / 100))
 
-static const uint32_t accel_period_ns[] = {
-	[ADXL345_ODR_12HZ] = UINT32_C(1000000000) / 12,
-	[ADXL345_ODR_25HZ] = UINT32_C(1000000000) / 25,
-	[ADXL345_ODR_50HZ] = UINT32_C(1000000000) / 50,
-	[ADXL345_ODR_100HZ] = UINT32_C(1000000000) / 100,
-	[ADXL345_ODR_200HZ] = UINT32_C(1000000000) / 200,
-	[ADXL345_ODR_400HZ] = UINT32_C(1000000000) / 400,
+/** Sensitivities based on Range:
+ *
+ * - At 2G: 256 LSB/g, 10-bits resolution.
+ * - At 4g: 256 LSB/g, 11-bits resolution.
+ * - At 8g: 256 LSB/g, 12-bits resolution.
+ * - At 16g 256 LSB/g, 13-bits resolution.
+ */
+static const uint32_t qscale_factor_full_res[] = {
+	/* (1.0 / Resolution-LSB-per-g) * (2^31 / 2^5) * SENSOR_G / 1000000 */
+	[ADXL345_RANGE_2G] = UINT32_C(2570754),
+	/* (1.0 / Resolution-LSB-per-g) * (2^31 / 2^6) * SENSOR_G / 1000000  */
+	[ADXL345_RANGE_4G] = UINT32_C(1285377),
+	/* (1.0 / Resolution-LSB-per-g) * (2^31 / 2^7) ) * SENSOR_G / 1000000 */
+	[ADXL345_RANGE_8G] = UINT32_C(642688),
+	/* (1.0 / Resolution-LSB-per-g) * (2^31 / 2^8) ) * SENSOR_G / 1000000 */
+	[ADXL345_RANGE_16G] = UINT32_C(321344),
 };
 
 static const uint32_t range_to_shift[] = {
@@ -26,30 +51,6 @@ static const uint32_t range_to_shift[] = {
 	[ADXL345_RANGE_16G] = 8,
 };
 
-/* (1 / sensitivity) * (pow(2,31) / pow(2,shift)) * (unit_scaler) */
-static const uint32_t qscale_factor_no_full_res[] = {
-	/* (1.0 / ADXL362_ACCEL_2G_LSB_PER_G) * (2^31 / 2^5) * SENSOR_G / 1000000 */
-	[ADXL345_RANGE_2G] = UINT32_C(2569011),
-	/* (1.0 / ADXL362_ACCEL_4G_LSB_PER_G) * (2^31 / 2^6) * SENSOR_G / 1000000  */
-	[ADXL345_RANGE_4G] = UINT32_C(642253),
-	/* (1.0 / ADXL362_ACCEL_8G_LSB_PER_G) * (2^31 / 2^7) ) * SENSOR_G / 1000000 */
-	[ADXL345_RANGE_8G] = UINT32_C(160563),
-	/* (1.0 / ADXL362_ACCEL_8G_LSB_PER_G) * (2^31 / 2^8) ) * SENSOR_G / 1000000 */
-	[ADXL345_RANGE_16G] = UINT32_C(40141),
-};
-
-/* (1 / sensitivity) * (pow(2,31) / pow(2,shift)) * (unit_scaler) */
-static const uint32_t qscale_factor_full_res[] = {
-	/* (1.0 / ADXL362_ACCEL_2G_LSB_PER_G) * (2^31 / 2^5) * SENSOR_G / 1000000 */
-	[ADXL345_RANGE_2G] = UINT32_C(2569011),
-	/* (1.0 / ADXL362_ACCEL_4G_LSB_PER_G) * (2^31 / 2^6) * SENSOR_G / 1000000  */
-	[ADXL345_RANGE_4G] = UINT32_C(1284506),
-	/* (1.0 / ADXL362_ACCEL_8G_LSB_PER_G) * (2^31 / 2^7) ) * SENSOR_G / 1000000 */
-	[ADXL345_RANGE_8G] = UINT32_C(642253),
-	/* (1.0 / ADXL362_ACCEL_8G_LSB_PER_G) * (2^31 / 2^8) ) * SENSOR_G / 1000000 */
-	[ADXL345_RANGE_16G] = UINT32_C(321126),
-};
-
 static inline void adxl345_accel_convert_q31(q31_t *out, int16_t sample, int32_t range,
 					uint8_t is_full_res)
 {
@@ -76,15 +77,28 @@ static inline void adxl345_accel_convert_q31(q31_t *out, int16_t sample, int32_t
 			}
 			break;
 		}
+		*out = sample * qscale_factor_full_res[range];
 	} else {
 		if (sample & BIT(9)) {
 			sample |= ADXL345_COMPLEMENT;
 		}
+		*out = sample * qscale_factor_no_full_res[range];
 	}
-
-	*out = sample * qscale_factor_no_full_res[range];
 }
 
+#ifdef CONFIG_ADXL345_STREAM
+
+#define SENSOR_SCALING_FACTOR (SENSOR_G / (16 * 1000 / 100))
+
+static const uint32_t accel_period_ns[] = {
+	[ADXL345_ODR_12HZ] = UINT32_C(1000000000) / 12,
+	[ADXL345_ODR_25HZ] = UINT32_C(1000000000) / 25,
+	[ADXL345_ODR_50HZ] = UINT32_C(1000000000) / 50,
+	[ADXL345_ODR_100HZ] = UINT32_C(1000000000) / 100,
+	[ADXL345_ODR_200HZ] = UINT32_C(1000000000) / 200,
+	[ADXL345_ODR_400HZ] = UINT32_C(1000000000) / 400,
+};
+
 static int adxl345_decode_stream(const uint8_t *buffer, struct sensor_chan_spec chan_spec,
 				 uint32_t *fit, uint16_t max_count, void *data_out)
 {
@@ -208,7 +222,12 @@ static int adxl345_decode_sample(const struct adxl345_sample *data,
 				 struct sensor_chan_spec chan_spec, uint32_t *fit,
 				 uint16_t max_count, void *data_out)
 {
-	struct sensor_value *out = (struct sensor_value *)data_out;
+	struct sensor_three_axis_data *out = (struct sensor_three_axis_data *)data_out;
+
+	memset(out, 0, sizeof(struct sensor_three_axis_data));
+	out->header.base_timestamp_ns = k_ticks_to_ns_floor64(k_uptime_ticks());
+	out->header.reading_count = 1;
+	out->shift = range_to_shift[data->selected_range];
 
 	if (*fit > 0) {
 		return -ENOTSUP;
@@ -216,9 +235,12 @@ static int adxl345_decode_sample(const struct adxl345_sample *data,
 
 	switch (chan_spec.chan_type) {
 	case SENSOR_CHAN_ACCEL_XYZ:
-		adxl345_accel_convert(out++, data->x);
-		adxl345_accel_convert(out++, data->y);
-		adxl345_accel_convert(out, data->z);
+		adxl345_accel_convert_q31(&out->readings->x, data->x, data->selected_range,
+					  data->is_full_res);
+		adxl345_accel_convert_q31(&out->readings->y, data->y, data->selected_range,
+					  data->is_full_res);
+		adxl345_accel_convert_q31(&out->readings->z, data->z, data->selected_range,
+					  data->is_full_res);
 		break;
 	default:
 		return -ENOTSUP;
@@ -226,7 +248,7 @@ static int adxl345_decode_sample(const struct adxl345_sample *data,
 
 	*fit = 1;
 
-	return 0;
+	return 1;
 }
 
 static int adxl345_decoder_decode(const uint8_t *buffer, struct sensor_chan_spec chan_spec,
@@ -259,10 +281,33 @@ static bool adxl345_decoder_has_trigger(const uint8_t *buffer, enum sensor_trigg
 	}
 }
 
+static int adxl345_get_size_info(struct sensor_chan_spec channel, size_t *base_size,
+				 size_t *frame_size)
+{
+	__ASSERT_NO_MSG(base_size != NULL);
+	__ASSERT_NO_MSG(frame_size != NULL);
+
+	if (channel.chan_type >= SENSOR_CHAN_ALL) {
+		return -ENOTSUP;
+	}
+
+	switch (channel.chan_type) {
+	case SENSOR_CHAN_ACCEL_XYZ:
+		*base_size = sizeof(struct sensor_three_axis_data);
+		*frame_size = sizeof(struct sensor_three_axis_sample_data);
+		return 0;
+	default:
+		break;
+	}
+
+	return -ENOTSUP;
+}
+
 SENSOR_DECODER_API_DT_DEFINE() = {
 	.get_frame_count = adxl345_decoder_get_frame_count,
 	.decode = adxl345_decoder_decode,
 	.has_trigger = adxl345_decoder_has_trigger,
+	.get_size_info = adxl345_get_size_info,
 };
 
 int adxl345_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder)
diff --git a/drivers/sensor/adi/adxl345/adxl345_stream.c b/drivers/sensor/adi/adxl345/adxl345_stream.c
index 054ca555f08..ac62f3fbf6a 100644
--- a/drivers/sensor/adi/adxl345/adxl345_stream.c
+++ b/drivers/sensor/adi/adxl345/adxl345_stream.c
@@ -6,7 +6,7 @@
 
 #include <zephyr/logging/log.h>
 #include <zephyr/drivers/sensor.h>
-
+#include <zephyr/drivers/sensor_clock.h>
 #include "adxl345.h"
 
 LOG_MODULE_DECLARE(ADXL345, CONFIG_SENSOR_LOG_LEVEL);
@@ -159,7 +159,7 @@ static void adxl345_process_fifo_samples_cb(struct rtio *r, const struct rtio_sq
 	hdr->int_status = data->status1;
 	hdr->is_full_res = data->is_full_res;
 	hdr->selected_range = data->selected_range;
-	hdr->accel_odr = cfg->odr;
+	hdr->accel_odr = data->odr;
 	hdr->sample_set_size = sample_set_size;
 
 	uint32_t buf_avail = buf_len;
@@ -358,11 +358,21 @@ void adxl345_stream_irq_handler(const struct device *dev)
 {
 	struct adxl345_dev_data *data = (struct adxl345_dev_data *) dev->data;
 	const struct adxl345_dev_config *cfg = (const struct adxl345_dev_config *) dev->config;
+	uint64_t cycles;
+	int rc;
 
 	if (data->sqe == NULL) {
 		return;
 	}
-	data->timestamp = k_ticks_to_ns_floor64(k_uptime_ticks());
+
+	rc = sensor_clock_get_cycles(&cycles);
+	if (rc != 0) {
+		LOG_ERR("Failed to get sensor clock cycles");
+		rtio_iodev_sqe_err(data->sqe, rc);
+		return;
+	}
+
+	data->timestamp = sensor_clock_cycles_to_ns(cycles);
 	struct rtio_sqe *write_status_addr = rtio_sqe_acquire(data->rtio_ctx);
 	struct rtio_sqe *read_status_reg = rtio_sqe_acquire(data->rtio_ctx);
 	struct rtio_sqe *check_status_reg = rtio_sqe_acquire(data->rtio_ctx);
diff --git a/drivers/sensor/adi/adxl362/adxl362_stream.c b/drivers/sensor/adi/adxl362/adxl362_stream.c
index 55175a4f9b0..453ed334348 100644
--- a/drivers/sensor/adi/adxl362/adxl362_stream.c
+++ b/drivers/sensor/adi/adxl362/adxl362_stream.c
@@ -6,7 +6,7 @@
 
 #include <zephyr/logging/log.h>
 #include <zephyr/drivers/sensor.h>
-
+#include <zephyr/drivers/sensor_clock.h>
 #include "adxl362.h"
 
 LOG_MODULE_DECLARE(ADXL362, CONFIG_SENSOR_LOG_LEVEL);
@@ -384,12 +384,20 @@ static void adxl362_process_status_cb(struct rtio *r, const struct rtio_sqe *sqr
 void adxl362_stream_irq_handler(const struct device *dev)
 {
 	struct adxl362_data *data = (struct adxl362_data *) dev->data;
-
+	uint64_t cycles;
+	int rc;
 	if (data->sqe == NULL) {
 		return;
 	}
 
-	data->timestamp = k_ticks_to_ns_floor64(k_uptime_ticks());
+	rc = sensor_clock_get_cycles(&cycles);
+	if (rc != 0) {
+		LOG_ERR("Failed to get sensor clock cycles");
+		rtio_iodev_sqe_err(data->sqe, rc);
+		return;
+	}
+
+	data->timestamp = sensor_clock_cycles_to_ns(cycles);
 
 	struct rtio_sqe *write_status_addr = rtio_sqe_acquire(data->rtio_ctx);
 	struct rtio_sqe *read_status_reg = rtio_sqe_acquire(data->rtio_ctx);
diff --git a/drivers/sensor/adi/adxl367/adxl367_decoder.c b/drivers/sensor/adi/adxl367/adxl367_decoder.c
index 85c3f466b89..daeb8f88f9c 100644
--- a/drivers/sensor/adi/adxl367/adxl367_decoder.c
+++ b/drivers/sensor/adi/adxl367/adxl367_decoder.c
@@ -75,7 +75,7 @@ static inline void adxl367_temp_convert_q31(q31_t *out, const uint8_t *buff,
 		}
 		break;
 
-	case ADXL367_14B_CHID:
+	case ADXL367_14B_CHID: {
 		uint16_t *tmp_buf = (uint16_t *)buff;
 
 		data_in = (int16_t)(((*tmp_buf >> 8) & 0xFF) | ((*tmp_buf << 8) & 0xFF00));
@@ -85,6 +85,7 @@ static inline void adxl367_temp_convert_q31(q31_t *out, const uint8_t *buff,
 			convert_value = 1;
 		}
 		break;
+	}
 
 	default:
 		break;
@@ -136,7 +137,7 @@ static inline void adxl367_accel_convert_q31(q31_t *out, const uint8_t *buff,
 		}
 		break;
 
-	case ADXL367_14B_CHID:
+	case ADXL367_14B_CHID: {
 		uint16_t *tmp_buf = (uint16_t *)buff;
 
 		data_in = (int16_t)(((*tmp_buf >> 8) & 0xFF) | ((*tmp_buf << 8) & 0xFF00));
@@ -146,6 +147,7 @@ static inline void adxl367_accel_convert_q31(q31_t *out, const uint8_t *buff,
 			convert_value = 1;
 		}
 		break;
+	}
 
 	default:
 		break;
diff --git a/drivers/sensor/adi/adxl367/adxl367_stream.c b/drivers/sensor/adi/adxl367/adxl367_stream.c
index 5826ed8d6cc..27fd5f1fe51 100644
--- a/drivers/sensor/adi/adxl367/adxl367_stream.c
+++ b/drivers/sensor/adi/adxl367/adxl367_stream.c
@@ -6,7 +6,7 @@
 
 #include <zephyr/logging/log.h>
 #include <zephyr/drivers/sensor.h>
-
+#include <zephyr/drivers/sensor_clock.h>
 #include "adxl367.h"
 
 LOG_MODULE_DECLARE(ADXL362, CONFIG_SENSOR_LOG_LEVEL);
@@ -206,7 +206,7 @@ static void adxl367_process_fifo_samples_cb(struct rtio *r, const struct rtio_sq
 	case ADXL367_8B:
 		fifo_bytes = fifo_packet_cnt;
 		break;
-	case ADXL367_12B:
+	case ADXL367_12B: {
 		unsigned int fifo_bits = fifo_packet_cnt * sample_numb * 12;
 
 		if (fifo_bits % 8 == 0) {
@@ -235,7 +235,7 @@ static void adxl367_process_fifo_samples_cb(struct rtio *r, const struct rtio_sq
 			packet_size++;
 		}
 		break;
-
+	}
 	default:
 		fifo_bytes = fifo_packet_cnt * 2;
 		packet_size *= 2;
@@ -363,7 +363,7 @@ static void adxl367_process_fifo_samples_cb(struct rtio *r, const struct rtio_sq
 
 	((struct adxl367_fifo_data *)buf)->fifo_byte_count = read_len;
 
-	__ASSERT_NO_MSG(read_len % pkt_size == 0);
+	__ASSERT_NO_MSG(read_len % packet_size == 0);
 
 	uint8_t *read_buf = buf + sizeof(*hdr);
 
@@ -537,12 +537,20 @@ static void adxl367_process_status_cb(struct rtio *r, const struct rtio_sqe *sqr
 void adxl367_stream_irq_handler(const struct device *dev)
 {
 	struct adxl367_data *data = (struct adxl367_data *) dev->data;
-
+	uint64_t cycles;
+	int rc;
 	if (data->sqe == NULL) {
 		return;
 	}
 
-	data->timestamp = k_ticks_to_ns_floor64(k_uptime_ticks());
+	rc = sensor_clock_get_cycles(&cycles);
+	if (rc != 0) {
+		LOG_ERR("Failed to get sensor clock cycles");
+		rtio_iodev_sqe_err(data->sqe, rc);
+		return;
+	}
+
+	data->timestamp = sensor_clock_cycles_to_ns(cycles);
 
 	struct rtio_sqe *write_status_addr = rtio_sqe_acquire(data->rtio_ctx);
 	struct rtio_sqe *read_status_reg = rtio_sqe_acquire(data->rtio_ctx);
diff --git a/drivers/sensor/adi/adxl372/adxl372.c b/drivers/sensor/adi/adxl372/adxl372.c
index 675d91705d3..dbffe36ec3d 100644
--- a/drivers/sensor/adi/adxl372/adxl372.c
+++ b/drivers/sensor/adi/adxl372/adxl372.c
@@ -550,7 +550,7 @@ static int adxl372_attr_set_odr(const struct device *dev,
 				const struct sensor_value *val)
 {
 	enum adxl372_odr odr;
-	struct adxl372_dev_config *cfg = (struct adxl372_dev_config *)dev->config;
+	struct adxl372_data *data = dev->data;
 
 	switch (val->val1) {
 	case 400:
@@ -575,7 +575,7 @@ static int adxl372_attr_set_odr(const struct device *dev,
 	int ret = adxl372_set_odr(dev, odr);
 
 	if (ret == 0) {
-		cfg->odr = odr;
+		data->odr = odr;
 	}
 
 	return ret;
diff --git a/drivers/sensor/adi/adxl372/adxl372.h b/drivers/sensor/adi/adxl372/adxl372.h
index a3f93cebb32..acfcf5fddb4 100644
--- a/drivers/sensor/adi/adxl372/adxl372.h
+++ b/drivers/sensor/adi/adxl372/adxl372.h
@@ -312,6 +312,7 @@ struct adxl372_data {
 	const struct adxl372_transfer_function *hw_tf;
 	struct adxl372_fifo_config fifo_config;
 	enum adxl372_act_proc_mode act_proc_mode;
+	enum adxl372_odr odr;
 #ifdef CONFIG_ADXL372_TRIGGER
 	struct gpio_callback gpio_cb;
 
diff --git a/drivers/sensor/adi/adxl372/adxl372_decoder.c b/drivers/sensor/adi/adxl372/adxl372_decoder.c
index eaa3ce7f5c3..9964d2868a3 100644
--- a/drivers/sensor/adi/adxl372/adxl372_decoder.c
+++ b/drivers/sensor/adi/adxl372/adxl372_decoder.c
@@ -50,7 +50,7 @@ static int adxl372_decode_stream(const uint8_t *buffer, struct sensor_chan_spec
 	memset(data, 0, sizeof(struct sensor_three_axis_data));
 	data->header.base_timestamp_ns = enc_data->timestamp;
 	data->header.reading_count = 1;
-	data->header.shift = 11; /* Sensor shift */
+	data->shift = 11; /* Sensor shift */
 
 	buffer += sizeof(struct adxl372_fifo_data);
 
diff --git a/drivers/sensor/adi/adxl372/adxl372_stream.c b/drivers/sensor/adi/adxl372/adxl372_stream.c
index a4dda2f2ce8..c2ecc42dffb 100644
--- a/drivers/sensor/adi/adxl372/adxl372_stream.c
+++ b/drivers/sensor/adi/adxl372/adxl372_stream.c
@@ -6,6 +6,7 @@
 
 #include <zephyr/logging/log.h>
 #include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/sensor_clock.h>
 
 #include "adxl372.h"
 
@@ -213,7 +214,7 @@ static void adxl372_process_fifo_samples_cb(struct rtio *r, const struct rtio_sq
 	hdr->is_fifo = 1;
 	hdr->timestamp = data->timestamp;
 	hdr->int_status = data->status1;
-	hdr->accel_odr = cfg->odr;
+	hdr->accel_odr = data->odr;
 	hdr->sample_set_size = sample_set_size;
 
 	if ((cfg->fifo_config.fifo_format == ADXL372_X_FIFO) ||
@@ -248,7 +249,7 @@ static void adxl372_process_fifo_samples_cb(struct rtio *r, const struct rtio_sq
 
 	((struct adxl372_fifo_data *)buf)->fifo_byte_count = read_len;
 
-	__ASSERT_NO_MSG(read_len % pkt_size == 0);
+	__ASSERT_NO_MSG(read_len % sample_set_size == 0);
 
 	uint8_t *read_buf = buf + sizeof(*hdr);
 
@@ -424,12 +425,20 @@ static void adxl372_process_status1_cb(struct rtio *r, const struct rtio_sqe *sq
 void adxl372_stream_irq_handler(const struct device *dev)
 {
 	struct adxl372_data *data = (struct adxl372_data *)dev->data;
-
+	uint64_t cycles;
+	int rc;
 	if (data->sqe == NULL) {
 		return;
 	}
 
-	data->timestamp = k_ticks_to_ns_floor64(k_uptime_ticks());
+	rc = sensor_clock_get_cycles(&cycles);
+	if (rc != 0) {
+		LOG_ERR("Failed to get sensor clock cycles");
+		rtio_iodev_sqe_err(data->sqe, rc);
+		return;
+	}
+
+	data->timestamp = sensor_clock_cycles_to_ns(cycles);
 
 	struct rtio_sqe *write_status_addr = rtio_sqe_acquire(data->rtio_ctx);
 	struct rtio_sqe *read_status_reg = rtio_sqe_acquire(data->rtio_ctx);
diff --git a/drivers/sensor/ams/tsl2591/tsl2591.c b/drivers/sensor/ams/tsl2591/tsl2591.c
index 51bc0891f10..bc378ecd289 100644
--- a/drivers/sensor/ams/tsl2591/tsl2591.c
+++ b/drivers/sensor/ams/tsl2591/tsl2591.c
@@ -418,11 +418,11 @@ static int tsl2591_setup(const struct device *dev)
 	uint8_t device_id;
 	int ret;
 
-	ret = tsl2591_reg_write(dev, TSL2591_REG_CONFIG, TSL2591_SRESET);
-	if (ret < 0) {
-		LOG_ERR("Failed to reset device");
-		return ret;
-	}
+	/* Reset the sensor. Although this is not clearly documented in the datasheet,
+	 * it is  suspected that because the sensor is reset, it doesn't explicitly send
+	 * an ACK. Thus, don't check the return code.
+	 */
+	tsl2591_reg_write(dev, TSL2591_REG_CONFIG, TSL2591_SRESET);
 
 	ret = tsl2591_reg_read(dev, TSL2591_REG_ID, &device_id, 1U);
 	if (ret < 0) {
diff --git a/drivers/sensor/apds9253/apds9253.c b/drivers/sensor/apds9253/apds9253.c
index b20507e9da9..57d8a2d6bfb 100644
--- a/drivers/sensor/apds9253/apds9253.c
+++ b/drivers/sensor/apds9253/apds9253.c
@@ -121,9 +121,97 @@ static int apds9253_channel_get(const struct device *dev, enum sensor_channel ch
 	return 0;
 }
 
+static int apds9253_attr_set_gain(const struct device *dev, uint8_t gain)
+{
+	const struct apds9253_config *config = dev->config;
+	struct apds9253_data *drv_data = dev->data;
+	uint8_t value;
+
+	if (drv_data->gain == gain) {
+		return 0;
+	}
+
+	static uint8_t value_map[] = {
+		APDS9253_LS_GAIN_RANGE_1, APDS9253_LS_GAIN_RANGE_3,  APDS9253_LS_GAIN_RANGE_6,
+		APDS9253_LS_GAIN_RANGE_9, APDS9253_LS_GAIN_RANGE_18,
+	};
+
+	if (gain < APDS9253_LS_GAIN_RANGE_1 || gain > APDS9253_LS_GAIN_RANGE_18) {
+		return -EINVAL;
+	}
+	value = value_map[gain];
+
+	if (i2c_reg_update_byte_dt(&config->i2c, APDS9253_LS_GAIN_REG, APDS9253_LS_GAIN_MASK,
+				   (value & APDS9253_LS_GAIN_MASK))) {
+		LOG_ERR("Not able to set light, sensor gain is not set");
+		return -EIO;
+	}
+
+	drv_data->gain = gain;
+
+	return 0;
+}
+
+static int apds9253_attr_set_sampl_freq(const struct device *dev,
+					const struct sensor_value *sampl_freq)
+{
+	const struct apds9253_config *config = dev->config;
+	struct apds9253_data *drv_data = dev->data;
+	uint8_t period_val;
+	uint32_t freq_mhz = sampl_freq->val1 * 1000 + (sampl_freq->val2 / 1000);
+
+	if (freq_mhz >= 40000) {
+		period_val = APDS9253_LS_MEAS_RATE_MES_25MS;
+	} else if (freq_mhz >= 20000) {
+		period_val = APDS9253_LS_MEAS_RATE_MES_50MS;
+	} else if (freq_mhz >= 10000) {
+		period_val = APDS9253_LS_MEAS_RATE_MES_100MS;
+	} else if (freq_mhz >= 5000) {
+		period_val = APDS9253_LS_MEAS_RATE_MES_200MS;
+	} else if (freq_mhz >= 2000) {
+		period_val = APDS9253_LS_MEAS_RATE_MES_500MS;
+	} else if (freq_mhz >= 1000) {
+		period_val = APDS9253_LS_MEAS_RATE_MES_1000MS;
+	} else if (freq_mhz >= 500) {
+		period_val = APDS9253_LS_MEAS_RATE_MES_2000MS;
+	} else {
+		LOG_INF("Frequency below minimum range, setting to minimum supported value: "
+			"0.5Hz.");
+		period_val = APDS9253_LS_MEAS_RATE_MES_2000MS;
+	}
+
+	if (i2c_reg_update_byte_dt(&config->i2c, APDS9253_LS_MEAS_RATE_REG,
+				   APDS9253_LS_MEAS_RATE_MES_MASK,
+				   (period_val & APDS9253_LS_MEAS_RATE_MES_MASK))) {
+		LOG_ERR("Not able to set light sensor measurement rate is not set");
+		return -EIO;
+	}
+
+	drv_data->meas_rate_mes = period_val;
+
+	return 0;
+}
+
+static int apds9253_attr_set(const struct device *dev, enum sensor_channel chan,
+			     enum sensor_attribute attr, const struct sensor_value *val)
+{
+	switch (attr) {
+	case SENSOR_ATTR_GAIN:
+		return apds9253_attr_set_gain(dev, val->val1);
+	case SENSOR_ATTR_SAMPLING_FREQUENCY:
+		return apds9253_attr_set_sampl_freq(dev, val);
+	default:
+		LOG_DBG("Sensor attribute not supported.");
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
 static int apds9253_sensor_setup(const struct device *dev)
 {
 	const struct apds9253_config *config = dev->config;
+	struct apds9253_data *drv_data = dev->data;
 	uint8_t chip_id;
 
 	if (i2c_reg_read_byte_dt(&config->i2c, APDS9253_PART_ID, &chip_id)) {
@@ -162,6 +250,9 @@ static int apds9253_sensor_setup(const struct device *dev)
 		return -EIO;
 	}
 
+	drv_data->gain = config->ls_gain;
+	drv_data->meas_rate_mes = config->ls_rate;
+
 	return 0;
 }
 
@@ -229,6 +320,7 @@ static int apds9253_init(const struct device *dev)
 static DEVICE_API(sensor, apds9253_driver_api) = {
 	.sample_fetch = &apds9253_sample_fetch,
 	.channel_get = &apds9253_channel_get,
+	.attr_set = &apds9253_attr_set,
 };
 
 #define APDS9253_INIT(n)                                                                           \
diff --git a/drivers/sensor/apds9253/apds9253.h b/drivers/sensor/apds9253/apds9253.h
index 9fbe4a43bc3..b4ab49eb327 100644
--- a/drivers/sensor/apds9253/apds9253.h
+++ b/drivers/sensor/apds9253/apds9253.h
@@ -100,6 +100,8 @@ struct apds9253_data {
 	const struct device *dev;
 	uint32_t sample_crgb[4];
 	uint8_t pdata;
+	uint8_t gain;
+	uint8_t meas_rate_mes;
 	struct k_sem data_sem;
 };
 
diff --git a/drivers/sensor/asahi_kasei/akm09918c/Kconfig b/drivers/sensor/asahi_kasei/akm09918c/Kconfig
index d7dac11f424..301165106aa 100644
--- a/drivers/sensor/asahi_kasei/akm09918c/Kconfig
+++ b/drivers/sensor/asahi_kasei/akm09918c/Kconfig
@@ -7,6 +7,7 @@ config AKM09918C
 	default y
 	depends on DT_HAS_ASAHI_KASEI_AKM09918C_ENABLED
 	select I2C
+	select I2C_RTIO if SENSOR_ASYNC_API
 	select RTIO_WORKQ if SENSOR_ASYNC_API
 	help
 	  Enable driver for AK8975 magnetometer.
diff --git a/drivers/sensor/asahi_kasei/akm09918c/akm09918c.c b/drivers/sensor/asahi_kasei/akm09918c/akm09918c.c
index 9bc9efaa223..b8c5e9a68fe 100644
--- a/drivers/sensor/asahi_kasei/akm09918c/akm09918c.c
+++ b/drivers/sensor/asahi_kasei/akm09918c/akm09918c.c
@@ -28,7 +28,7 @@ LOG_MODULE_REGISTER(AKM09918C, CONFIG_SENSOR_LOG_LEVEL);
  * @param chan Channel ID for starting the measurement
  * @return int 0 if successful or error code
  */
-int akm09918c_start_measurement(const struct device *dev, enum sensor_channel chan)
+int akm09918c_start_measurement_blocking(const struct device *dev, enum sensor_channel chan)
 {
 	struct akm09918c_data *data = dev->data;
 	const struct akm09918c_config *cfg = dev->config;
@@ -59,7 +59,8 @@ int akm09918c_start_measurement(const struct device *dev, enum sensor_channel ch
  * @param z Location to write Z channel sample.
  * @return int 0 if successful or error code
  */
-int akm09918c_fetch_measurement(const struct device *dev, int16_t *x, int16_t *y, int16_t *z)
+int akm09918c_fetch_measurement_blocking(const struct device *dev, int16_t *x, int16_t *y,
+					 int16_t *z)
 {
 	const struct akm09918c_config *cfg = dev->config;
 	uint8_t buf[9] = {0};
@@ -86,7 +87,7 @@ static int akm09918c_sample_fetch(const struct device *dev, enum sensor_channel
 {
 	struct akm09918c_data *data = dev->data;
 
-	int ret = akm09918c_start_measurement(dev, chan);
+	int ret = akm09918c_start_measurement_blocking(dev, chan);
 
 	if (ret) {
 		return ret;
@@ -95,7 +96,8 @@ static int akm09918c_sample_fetch(const struct device *dev, enum sensor_channel
 	LOG_DBG("Waiting for sample...");
 	k_usleep(AKM09918C_MEASURE_TIME_US);
 
-	return akm09918c_fetch_measurement(dev, &data->x_sample, &data->y_sample, &data->z_sample);
+	return akm09918c_fetch_measurement_blocking(dev, &data->x_sample, &data->y_sample,
+						    &data->z_sample);
 }
 
 static void akm09918c_convert(struct sensor_value *val, int16_t sample)
@@ -249,8 +251,13 @@ static DEVICE_API(sensor, akm09918c_driver_api) = {
 };
 
 #define AKM09918C_DEFINE(inst)                                                                     \
-	static struct akm09918c_data akm09918c_data_##inst;                                        \
-                                                                                                   \
+	IF_ENABLED(CONFIG_I2C_RTIO, \
+		(I2C_DT_IODEV_DEFINE(akm09918c_iodev_##inst, DT_DRV_INST(inst));)) \
+	IF_ENABLED(CONFIG_I2C_RTIO, (RTIO_DEFINE( \
+		akm09918c_rtio_ctx_##inst, CONFIG_I2C_RTIO_SQ_SIZE, CONFIG_I2C_RTIO_CQ_SIZE);)) \
+	static struct akm09918c_data akm09918c_data_##inst = {                                     \
+		IF_ENABLED(CONFIG_I2C_RTIO, (.rtio_ctx = \
+			&akm09918c_rtio_ctx_##inst, .iodev = &akm09918c_iodev_##inst)) }; \
 	static const struct akm09918c_config akm09918c_config_##inst = {                           \
 		.i2c = I2C_DT_SPEC_INST_GET(inst),                                                 \
 	};                                                                                         \
diff --git a/drivers/sensor/asahi_kasei/akm09918c/akm09918c.h b/drivers/sensor/asahi_kasei/akm09918c/akm09918c.h
index f8a4f5c7c43..d8929a4c7c0 100644
--- a/drivers/sensor/asahi_kasei/akm09918c/akm09918c.h
+++ b/drivers/sensor/asahi_kasei/akm09918c/akm09918c.h
@@ -41,6 +41,9 @@ struct akm09918c_data {
 		uint64_t timestamp;
 		struct k_work_delayable async_fetch_work;
 	} work_ctx;
+	/* for communication to the bus controller */
+	struct rtio *rtio_ctx;
+	struct rtio_iodev *iodev;
 #endif
 };
 
@@ -82,9 +85,10 @@ static inline void akm09918c_reg_to_hz(uint8_t reg, struct sensor_value *val)
 		break;
 	}
 }
-int akm09918c_start_measurement(const struct device *dev, enum sensor_channel chan);
+int akm09918c_start_measurement_blocking(const struct device *dev, enum sensor_channel chan);
 
-int akm09918c_fetch_measurement(const struct device *dev, int16_t *x, int16_t *y, int16_t *z);
+int akm09918c_fetch_measurement_blocking(const struct device *dev, int16_t *x, int16_t *y,
+					 int16_t *z);
 /*
  * RTIO types
  */
@@ -95,7 +99,12 @@ struct akm09918c_decoder_header {
 
 struct akm09918c_encoded_data {
 	struct akm09918c_decoder_header header;
-	int16_t readings[3];
+	struct __packed {
+		uint8_t st1;
+		int16_t data[3];
+		uint8_t tmps; /* not used  - only for padding */
+		uint8_t st2;  /* not used but includes overflow data */
+	} reading;
 };
 
 void akm09918_async_fetch(struct k_work *work);
@@ -103,5 +112,7 @@ void akm09918_async_fetch(struct k_work *work);
 int akm09918c_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder);
 
 void akm09918c_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe);
+void akm09918_after_start_cb(struct rtio *rtio_ctx, const struct rtio_sqe *sqe, void *arg0);
+void akm09918_complete_cb(struct rtio *rtio_ctx, const struct rtio_sqe *sqe, void *arg0);
 
 #endif /* ZEPHYR_DRIVERS_SENSOR_AKM09918C_AKM09918C_H_ */
diff --git a/drivers/sensor/asahi_kasei/akm09918c/akm09918c_async.c b/drivers/sensor/asahi_kasei/akm09918c/akm09918c_async.c
index 832d046bdd7..2ae54305330 100644
--- a/drivers/sensor/asahi_kasei/akm09918c/akm09918c_async.c
+++ b/drivers/sensor/asahi_kasei/akm09918c/akm09918c_async.c
@@ -7,20 +7,39 @@
  */
 
 #include <zephyr/logging/log.h>
-#include <zephyr/rtio/work.h>
+#include <zephyr/rtio/rtio.h>
+#include <zephyr/drivers/sensor_clock.h>
+#include <zephyr/sys/byteorder.h>
 
 #include "akm09918c.h"
 
 LOG_MODULE_DECLARE(AKM09918C, CONFIG_SENSOR_LOG_LEVEL);
 
-void akm09918c_submit_sync(struct rtio_iodev_sqe *iodev_sqe)
+static int akm09918c_flush_cqes(struct rtio *rtio_ctx)
+{
+	/* Flush completions */
+	struct rtio_cqe *cqe;
+	int res = 0;
+
+	do {
+		cqe = rtio_cqe_consume(rtio_ctx);
+		if (cqe != NULL) {
+			if ((cqe->result < 0 && res == 0)) {
+				LOG_ERR("Bus error: %d", cqe->result);
+				res = cqe->result;
+			}
+			rtio_cqe_release(rtio_ctx, cqe);
+		}
+	} while (cqe != NULL);
+	return res;
+}
+
+void akm09918c_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
 {
 	const struct sensor_read_config *cfg = iodev_sqe->sqe.iodev->data;
-	const struct device *dev = cfg->sensor;
 	struct akm09918c_data *data = dev->data;
 	const struct sensor_chan_spec *const channels = cfg->channels;
 	const size_t num_channels = cfg->count;
-	int rc;
 
 	/* Check if the requested channels are supported */
 	for (size_t i = 0; i < num_channels; i++) {
@@ -37,19 +56,48 @@ void akm09918c_submit_sync(struct rtio_iodev_sqe *iodev_sqe)
 			return;
 		}
 	}
+	struct rtio_sqe *writeByte_sqe = i2c_rtio_copy_reg_write_byte(
+		data->rtio_ctx, data->iodev, AKM09918C_REG_CNTL2, AKM09918C_CNTL2_SINGLE_MEASURE);
+	struct rtio_sqe *cb_sqe = rtio_sqe_acquire(data->rtio_ctx);
+
+	writeByte_sqe->flags |= RTIO_SQE_CHAINED;
+	rtio_sqe_prep_callback_no_cqe(cb_sqe, akm09918_after_start_cb, (void *)iodev_sqe, NULL);
+
+	if (writeByte_sqe != NULL && cb_sqe != NULL) {
+		rtio_submit(data->rtio_ctx, 0);
+	} else {
+		rtio_sqe_drop_all(data->rtio_ctx);
+		rtio_iodev_sqe_err(iodev_sqe, -ENOMEM);
+	}
+}
 
-	/* start the measurement in the sensor */
-	rc = akm09918c_start_measurement(dev, SENSOR_CHAN_MAGN_XYZ);
+void akm09918_after_start_cb(struct rtio *rtio_ctx, const struct rtio_sqe *sqe, void *arg0)
+{
+	const struct rtio_iodev_sqe *parent_iodev_sqe = (struct rtio_iodev_sqe *)arg0;
+	const struct sensor_read_config *cfg = parent_iodev_sqe->sqe.iodev->data;
+	const struct device *dev = cfg->sensor;
+	struct akm09918c_data *data = dev->data;
+	struct rtio_iodev_sqe *iodev_sqe = (struct rtio_iodev_sqe *)arg0;
+	uint64_t cycles;
+	int rc;
+
+	rc = sensor_clock_get_cycles(&cycles);
 	if (rc != 0) {
-		LOG_ERR("Failed to fetch samples.");
+		LOG_ERR("Failed to get sensor clock cycles");
 		rtio_iodev_sqe_err(iodev_sqe, rc);
 		return;
 	}
 
 	/* save information for the work item */
-	data->work_ctx.timestamp = k_ticks_to_ns_floor64(k_uptime_ticks());
+	data->work_ctx.timestamp = sensor_clock_cycles_to_ns(cycles);
 	data->work_ctx.iodev_sqe = iodev_sqe;
 
+	rc = akm09918c_flush_cqes(data->rtio_ctx);
+	if (rc != 0) {
+		rtio_iodev_sqe_err(iodev_sqe, rc);
+		return;
+	}
+
 	rc = k_work_schedule(&data->work_ctx.async_fetch_work, K_USEC(AKM09918C_MEASURE_TIME_US));
 	if (rc == 0) {
 		LOG_ERR("The last fetch has not finished yet. "
@@ -59,20 +107,6 @@ void akm09918c_submit_sync(struct rtio_iodev_sqe *iodev_sqe)
 	return;
 }
 
-void akm09918c_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
-{
-	struct rtio_work_req *req = rtio_work_req_alloc();
-
-	if (req == NULL) {
-		LOG_ERR("RTIO work item allocation failed. Consider to increase "
-			"CONFIG_RTIO_WORKQ_POOL_ITEMS.");
-		rtio_iodev_sqe_err(iodev_sqe, -ENOMEM);
-		return;
-	}
-
-	rtio_work_req_submit(req, iodev_sqe, akm09918c_submit_sync);
-}
-
 void akm09918_async_fetch(struct k_work *work)
 {
 	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
@@ -80,6 +114,7 @@ void akm09918_async_fetch(struct k_work *work)
 		CONTAINER_OF(dwork, struct akm09918c_async_fetch_ctx, async_fetch_work);
 	const struct sensor_read_config *cfg = ctx->iodev_sqe->sqe.iodev->data;
 	const struct device *dev = cfg->sensor;
+	struct akm09918c_data *data = dev->data;
 	uint32_t req_buf_len = sizeof(struct akm09918c_encoded_data);
 	uint32_t buf_len;
 	uint8_t *buf;
@@ -94,11 +129,49 @@ void akm09918_async_fetch(struct k_work *work)
 		return;
 	}
 	edata = (struct akm09918c_encoded_data *)buf;
-	rc = akm09918c_fetch_measurement(dev, &edata->readings[0], &edata->readings[1],
-					 &edata->readings[2]);
+
+	struct rtio_sqe *burstRead_sqe =
+		i2c_rtio_copy_reg_burst_read(data->rtio_ctx, data->iodev, AKM09918C_REG_ST1,
+					     &(edata->reading), sizeof(edata->reading));
+
+	edata->header.timestamp = ctx->timestamp;
+
+	struct rtio_sqe *cb_sqe = rtio_sqe_acquire(data->rtio_ctx);
+
+	rtio_sqe_prep_callback_no_cqe(cb_sqe, akm09918_complete_cb, (void *)ctx->iodev_sqe, NULL);
+
+	if (burstRead_sqe != NULL && cb_sqe != NULL) {
+		burstRead_sqe->flags |= RTIO_SQE_CHAINED;
+		rtio_submit(data->rtio_ctx, 0);
+	} else {
+		rtio_sqe_drop_all(data->rtio_ctx);
+		rtio_iodev_sqe_err(ctx->iodev_sqe, -ENOMEM);
+	}
+}
+
+void akm09918_complete_cb(struct rtio *rtio_ctx, const struct rtio_sqe *sqe, void *arg0)
+{
+	struct rtio_iodev_sqe *parent_iodev_sqe = (struct rtio_iodev_sqe *)arg0;
+	struct rtio_sqe *parent_sqe = &parent_iodev_sqe->sqe;
+	struct akm09918c_encoded_data *edata =
+		(struct akm09918c_encoded_data *)(parent_sqe->rx.buf);
+	int rc;
+
+	rc = akm09918c_flush_cqes(rtio_ctx);
 	if (rc != 0) {
-		rtio_iodev_sqe_err(ctx->iodev_sqe, rc);
+		rtio_iodev_sqe_err(parent_iodev_sqe, rc);
+		return;
+	}
+
+	if (FIELD_GET(AKM09918C_ST1_DRDY, edata->reading.st1) == 0) {
+		LOG_ERR("Data not ready, st1=0x%02x", edata->reading.st1);
+		rtio_iodev_sqe_err(parent_iodev_sqe, -EBUSY);
 		return;
 	}
-	rtio_iodev_sqe_ok(ctx->iodev_sqe, 0);
+
+	edata->reading.data[0] = sys_le16_to_cpu(edata->reading.data[0]);
+	edata->reading.data[1] = sys_le16_to_cpu(edata->reading.data[1]);
+	edata->reading.data[2] = sys_le16_to_cpu(edata->reading.data[2]);
+
+	rtio_iodev_sqe_ok(parent_iodev_sqe, 0);
 }
diff --git a/drivers/sensor/asahi_kasei/akm09918c/akm09918c_decoder.c b/drivers/sensor/asahi_kasei/akm09918c/akm09918c_decoder.c
index 7a17e959dc4..b282e9f8347 100644
--- a/drivers/sensor/asahi_kasei/akm09918c/akm09918c_decoder.c
+++ b/drivers/sensor/asahi_kasei/akm09918c/akm09918c_decoder.c
@@ -70,9 +70,9 @@ static int akm09918c_decoder_decode(const uint8_t *buffer, struct sensor_chan_sp
 		out->header.reading_count = 1;
 		out->shift = AKM09918C_SHIFT;
 
-		akm09918c_convert_raw_to_q31(edata->readings[0], &out->readings[0].x);
-		akm09918c_convert_raw_to_q31(edata->readings[1], &out->readings[0].y);
-		akm09918c_convert_raw_to_q31(edata->readings[2], &out->readings[0].z);
+		akm09918c_convert_raw_to_q31(edata->reading.data[0], &out->readings[0].x);
+		akm09918c_convert_raw_to_q31(edata->reading.data[1], &out->readings[0].y);
+		akm09918c_convert_raw_to_q31(edata->reading.data[2], &out->readings[0].z);
 		*fit = 1;
 
 		return 1;
diff --git a/drivers/sensor/bosch/bma4xx/CMakeLists.txt b/drivers/sensor/bosch/bma4xx/CMakeLists.txt
index a0151e081d6..0f8556e22dc 100644
--- a/drivers/sensor/bosch/bma4xx/CMakeLists.txt
+++ b/drivers/sensor/bosch/bma4xx/CMakeLists.txt
@@ -2,6 +2,15 @@
 
 zephyr_library()
 
-zephyr_library_sources(bma4xx.c)
-zephyr_library_sources(bma4xx_i2c.c)
-zephyr_library_sources(bma4xx_spi.c)
+zephyr_library_sources(
+    bma4xx.c
+    bma4xx_common.c
+    bma4xx_decoder.c
+    bma4xx_rtio.c
+)
+
+zephyr_library_sources_ifdef(CONFIG_I2C bma4xx_i2c.c)
+zephyr_library_sources_ifdef(CONFIG_SPI bma4xx_spi.c)
+zephyr_library_sources_ifdef(CONFIG_BMA4XX_STREAM bma4xx_rtio_stream.c)
+zephyr_library_sources_ifdef(CONFIG_BMA4XX_STREAM bma4xx_interrupt.c)
+zephyr_library_sources_ifdef(CONFIG_EMUL_BMA4XX bma4xx_emul.c)
diff --git a/drivers/sensor/bosch/bma4xx/Kconfig b/drivers/sensor/bosch/bma4xx/Kconfig
index 1d980635b80..12aee6a403a 100644
--- a/drivers/sensor/bosch/bma4xx/Kconfig
+++ b/drivers/sensor/bosch/bma4xx/Kconfig
@@ -2,23 +2,26 @@
 #
 # Copyright (c) 2023 Google LLC
 # Copyright (c) 2024 Croxel Inc.
+# Copyright (c) 2024 Cienet
 #
 # SPDX-License-Identifier: Apache-2.0
 
-config BMA4XX
+menuconfig BMA4XX
 	bool "BMA4XX 3-axis acceleration sensor"
 	default y
 	depends on DT_HAS_BOSCH_BMA4XX_ENABLED
 	depends on SENSOR_ASYNC_API
 	select I2C
+	select I2C_RTIO
 	select RTIO_WORKQ
 	help
 	  Enable driver for Bosch BMA4XX (I2C-based)
 
+if BMA4XX
+
 config BMA4XX_TEMPERATURE
 	bool "Allow reading the BMA4XX die temperature"
 	default n
-	depends on BMA4XX
 	help
 	  Allow reading the BMA4xx's on-chip temperature sensor. This creates
 	  extra bus activity and increases code size.
@@ -26,8 +29,17 @@ config BMA4XX_TEMPERATURE
 config EMUL_BMA4XX
 	bool "Emulator for the BMA4XX"
 	default y
-	depends on BMA4XX
 	depends on EMUL
 	help
 	  Enable the hardware emulator for the BMA4XX. Doing so allows exercising
 	  sensor APIs for this sensor in native_sim and qemu.
+
+config BMA4XX_STREAM
+	bool "Use hardware FIFO to stream data"
+	default y
+	depends on GPIO
+	depends on $(dt_compat_any_has_prop,$(DT_COMPAT_BOSCH_BMA4XX),int1-gpios)
+	help
+	  Use this config option to enable streaming sensor data via RTIO subsystem.
+
+endif # BMA4XX
diff --git a/drivers/sensor/bosch/bma4xx/bma4xx.c b/drivers/sensor/bosch/bma4xx/bma4xx.c
index 219d65dc5ed..a9afda946bb 100644
--- a/drivers/sensor/bosch/bma4xx/bma4xx.c
+++ b/drivers/sensor/bosch/bma4xx/bma4xx.c
@@ -2,6 +2,7 @@
  *
  * Copyright (c) 2023 Google LLC
  * Copyright (c) 2024 Croxel Inc.
+ * Copyright (c) 2024 Cienet
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,8 +16,12 @@
 #include <zephyr/pm/device.h>
 #include <zephyr/rtio/work.h>
 
-LOG_MODULE_REGISTER(bma4xx, CONFIG_SENSOR_LOG_LEVEL);
 #include "bma4xx.h"
+#include "bma4xx_interrupt.h"
+#include "bma4xx_decoder.h"
+#include "bma4xx_rtio.h"
+
+LOG_MODULE_REGISTER(bma4xx, CONFIG_SENSOR_LOG_LEVEL);
 
 /**
  * @brief Helper for converting m/s^2 offset values into register values
@@ -108,12 +113,11 @@ static int bma4xx_odr_to_reg(uint32_t microhertz, uint8_t *reg_val)
 }
 
 /**
- * Set the sensor's acceleration offset (per axis). Use bma4xx_commit_nvm() to save these
- * offsets to nonvolatile memory so they are automatically set during power-on-reset.
+ * Set the sensor's acceleration offset (per axis).
  */
-static int bma4xx_attr_set_odr(const struct device *dev, const struct sensor_value *val)
+static int bma4xx_attr_set_odr(const struct sensor_value *val,
+			       struct bma4xx_runtime_config *new_config)
 {
-	struct bma4xx_data *bma4xx = dev->data;
 	int status;
 	uint8_t reg_val;
 
@@ -123,13 +127,8 @@ static int bma4xx_attr_set_odr(const struct device *dev, const struct sensor_val
 		return status;
 	}
 
-	status = bma4xx->hw_ops->update_reg(dev, BMA4XX_REG_ACCEL_CONFIG, BMA4XX_MASK_ACC_CONF_ODR,
-					    reg_val);
-	if (status < 0) {
-		return status;
-	}
+	new_config->accel_odr = reg_val;
 
-	bma4xx->accel_odr = reg_val;
 	return 0;
 }
 
@@ -163,9 +162,9 @@ static int bma4xx_fs_to_reg(int32_t range_ug, uint8_t *reg_val)
 /**
  * Set the sensor's full-scale range
  */
-static int bma4xx_attr_set_range(const struct device *dev, const struct sensor_value *val)
+static int bma4xx_attr_set_range(const struct sensor_value *val,
+				 struct bma4xx_runtime_config *new_config)
 {
-	struct bma4xx_data *bma4xx = dev->data;
 	int status;
 	uint8_t reg_val;
 
@@ -175,30 +174,25 @@ static int bma4xx_attr_set_range(const struct device *dev, const struct sensor_v
 		return status;
 	}
 
-	status = bma4xx->hw_ops->update_reg(dev, BMA4XX_REG_ACCEL_RANGE, BMA4XX_MASK_ACC_RANGE,
-					    reg_val);
-	if (status < 0) {
-		return status;
-	}
+	new_config->accel_fs_range = reg_val;
 
-	bma4xx->accel_fs_range = reg_val;
 	return 0;
 }
 
 /**
  * Set the sensor's bandwidth parameter (one of BMA4XX_BWP_*)
  */
-static int bma4xx_attr_set_bwp(const struct device *dev, const struct sensor_value *val)
+static int bma4xx_attr_set_bwp(const struct sensor_value *val,
+			       struct bma4xx_runtime_config *new_config)
 {
 	/* Require that `val2` is unused, and that `val1` is in range of a valid BWP */
 	if (val->val2 || val->val1 < BMA4XX_BWP_OSR4_AVG1 || val->val1 > BMA4XX_BWP_RES_AVG128) {
 		return -EINVAL;
 	}
 
-	struct bma4xx_data *bma4xx = dev->data;
+	new_config->accel_bwp = (((uint8_t)val->val1) << BMA4XX_SHIFT_ACC_CONF_BWP);
 
-	return bma4xx->hw_ops->update_reg(dev, BMA4XX_REG_ACCEL_CONFIG, BMA4XX_MASK_ACC_CONF_BWP,
-					  (((uint8_t)val->val1) << BMA4XX_SHIFT_ACC_CONF_BWP));
+	return 0;
 }
 
 /**
@@ -207,19 +201,54 @@ static int bma4xx_attr_set_bwp(const struct device *dev, const struct sensor_val
 static int bma4xx_attr_set(const struct device *dev, enum sensor_channel chan,
 			   enum sensor_attribute attr, const struct sensor_value *val)
 {
-	switch (attr) {
-	case SENSOR_ATTR_SAMPLING_FREQUENCY:
-		return bma4xx_attr_set_odr(dev, val);
-	case SENSOR_ATTR_FULL_SCALE:
-		return bma4xx_attr_set_range(dev, val);
-	case SENSOR_ATTR_OFFSET:
-		return bma4xx_attr_set_offset(dev, chan, val);
-	case SENSOR_ATTR_CONFIGURATION:
-		/* Use for setting the bandwidth parameter (BWP) */
-		return bma4xx_attr_set_bwp(dev, val);
+	const struct bma4xx_data *data = dev->data;
+	struct bma4xx_runtime_config new_config = data->cfg;
+	int res = 0;
+
+	__ASSERT_NO_MSG(val != NULL);
+
+	switch (chan) {
+	case SENSOR_CHAN_ACCEL_X:
+	case SENSOR_CHAN_ACCEL_Y:
+	case SENSOR_CHAN_ACCEL_Z:
+	case SENSOR_CHAN_ACCEL_XYZ:
+		if (attr == SENSOR_ATTR_SAMPLING_FREQUENCY) {
+			res = bma4xx_attr_set_odr(val, &new_config);
+		} else if (attr == SENSOR_ATTR_FULL_SCALE) {
+			res = bma4xx_attr_set_range(val, &new_config);
+		} else if (attr == SENSOR_ATTR_OFFSET) {
+			res = bma4xx_attr_set_offset(dev, chan, val);
+		} else if (attr == SENSOR_ATTR_CONFIGURATION) {
+			/* Use for setting the bandwidth parameter (BWP) */
+			res = bma4xx_attr_set_bwp(val, &new_config);
+		} else {
+			LOG_ERR("Unsupported attribute");
+			res = -ENOTSUP;
+		}
+		break;
+	case SENSOR_CHAN_ALL:
+		if (attr == SENSOR_ATTR_BATCH_DURATION) {
+			if (val->val1 < 0) {
+				return -EINVAL;
+			}
+			new_config.batch_ticks = val->val1;
+		} else {
+			LOG_ERR("Unsupported attribute");
+			res = -EINVAL;
+		}
+		break;
 	default:
-		return -ENOTSUP;
+		LOG_ERR("Unsupported channel");
+		res = -EINVAL;
+		break;
+	}
+
+	if (res) {
+		LOG_ERR("Failed to set attribute");
+		return res;
 	}
+
+	return bma4xx_safely_configure(dev, &new_config);
 }
 
 /**
@@ -234,7 +263,7 @@ static int bma4xx_chip_init(const struct device *dev)
 	/* Sensor bus-specific initialization */
 	status = cfg->bus_init(dev);
 	if (status) {
-		LOG_ERR("bus_init failed: %d", status);
+		LOG_ERR("Failed to initialize bus: %d", status);
 		return status;
 	}
 
@@ -257,425 +286,25 @@ static int bma4xx_chip_init(const struct device *dev)
 		return status;
 	}
 
-	k_sleep(K_USEC(1000));
-
-	/* Default is: range = +/-4G, ODR = 100 Hz, BWP = "NORM_AVG4" */
-	bma4xx->accel_fs_range = BMA4XX_RANGE_4G;
-	bma4xx->accel_bwp = BMA4XX_BWP_NORM_AVG4;
-	bma4xx->accel_odr = BMA4XX_ODR_100;
-
-	/* Switch to performance power mode */
-	status = bma4xx->hw_ops->update_reg(dev, BMA4XX_REG_ACCEL_CONFIG, BMA4XX_BIT_ACC_PERF_MODE,
-					    BMA4XX_BIT_ACC_PERF_MODE);
-	if (status) {
-		LOG_ERR("Could not enable performance power save mode: %d", status);
-		return status;
-	}
-
-	/* Enable accelerometer */
-	status = bma4xx->hw_ops->update_reg(dev, BMA4XX_REG_POWER_CTRL, BMA4XX_BIT_ACC_EN,
-					    BMA4XX_BIT_ACC_EN);
-	if (status) {
-		LOG_ERR("Could not enable accel: %d", status);
-		return status;
-	}
-
-	return status;
-}
-
-/*
- * Sample fetch and conversion
- */
-
-/**
- * @brief Read accelerometer data from the BMA4xx
- */
-static int bma4xx_sample_fetch(const struct device *dev, int16_t *x, int16_t *y, int16_t *z)
-{
-	struct bma4xx_data *bma4xx = dev->data;
-	uint8_t read_data[6];
-	int status;
-
-	/* Burst read regs DATA_8 through DATA_13, which holds the accel readings */
-	status = bma4xx->hw_ops->read_data(dev, BMA4XX_REG_DATA_8, (uint8_t *)&read_data,
-					   BMA4XX_REG_DATA_13 - BMA4XX_REG_DATA_8 + 1);
-	if (status < 0) {
-		LOG_ERR("Cannot read accel data: %d", status);
-		return status;
+	if (IS_ENABLED(CONFIG_BMA4XX_STREAM)) {
+		status = bma4xx_init_interrupt(dev);
+		if (status != 0) {
+			LOG_ERR("Failed to initialize bma4xx interrupt");
+			return status;
+		}
 	}
 
-	LOG_DBG("Raw values [0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x, 0x%02x]", read_data[0],
-		read_data[1], read_data[2], read_data[3], read_data[4], read_data[5]);
-	/* Values in accel_data[N] are left-aligned and will read 16x actual */
-	*x = ((int16_t)read_data[1] << 4) | FIELD_GET(GENMASK(7, 4), read_data[0]);
-	*y = ((int16_t)read_data[3] << 4) | FIELD_GET(GENMASK(7, 4), read_data[2]);
-	*z = ((int16_t)read_data[5] << 4) | FIELD_GET(GENMASK(7, 4), read_data[4]);
-
-	LOG_DBG("XYZ reg vals are %d, %d, %d", *x, *y, *z);
-
-	return 0;
-}
-
-#ifdef CONFIG_BMA4XX_TEMPERATURE
-/**
- * @brief Read temperature register on BMA4xx
- */
-static int bma4xx_temp_fetch(const struct device *dev, int8_t *temp)
-{
-	struct bma4xx_data *bma4xx = dev->data;
-	int status;
+	/* Default is: range = +/-4G, ODR = 100 Hz, BWP = "NORM_AVG4" */
+	bma4xx->cfg.accel_fs_range = BMA4XX_RANGE_4G;
+	bma4xx->cfg.accel_bwp = BMA4XX_BWP_NORM_AVG4;
+	bma4xx->cfg.accel_odr = BMA4XX_ODR_100;
 
-	status = bma4xx->hw_ops->read_reg(dev, BMA4XX_REG_TEMPERATURE, temp);
+	status = bma4xx_configure(dev, &bma4xx->cfg);
 	if (status) {
-		LOG_ERR("could not read temp reg: %d", status);
+		LOG_ERR("Failed to initialize bma4xx trigger");
 		return status;
 	}
 
-	LOG_DBG("temp reg val is %d", *temp);
-	return 0;
-}
-#endif
-
-/*
- * RTIO submit and encoding
- */
-
-static void bma4xx_submit_one_shot(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
-{
-	struct bma4xx_data *bma4xx = dev->data;
-
-	const struct sensor_read_config *cfg = iodev_sqe->sqe.iodev->data;
-	const struct sensor_chan_spec *const channels = cfg->channels;
-	const size_t num_channels = cfg->count;
-
-	uint32_t min_buf_len = sizeof(struct bma4xx_encoded_data);
-	struct bma4xx_encoded_data *edata;
-	uint8_t *buf;
-	uint32_t buf_len;
-	int rc;
-
-	/* Get the buffer for the frame, it may be allocated dynamically by the rtio context */
-	rc = rtio_sqe_rx_buf(iodev_sqe, min_buf_len, min_buf_len, &buf, &buf_len);
-	if (rc != 0) {
-		LOG_ERR("Failed to get a read buffer of size %u bytes", min_buf_len);
-		rtio_iodev_sqe_err(iodev_sqe, rc);
-		return;
-	}
-
-	/* Prepare response */
-	edata = (struct bma4xx_encoded_data *)buf;
-	edata->header.is_fifo = false;
-	edata->header.accel_fs = bma4xx->accel_fs_range;
-	edata->header.timestamp = k_ticks_to_ns_floor64(k_uptime_ticks());
-	edata->has_accel = 0;
-	edata->has_temp = 0;
-
-	/* Determine what channels we need to fetch */
-	for (int i = 0; i < num_channels; i++) {
-		if (channels[i].chan_idx != 0) {
-			LOG_ERR("Only channel index 0 supported");
-			rtio_iodev_sqe_err(iodev_sqe, -ENOTSUP);
-			return;
-		}
-		switch (channels[i].chan_type) {
-		case SENSOR_CHAN_ALL:
-			edata->has_accel = 1;
-#ifdef CONFIG_BMA4XX_TEMPERATURE
-			edata->has_temp = 1;
-#endif /* CONFIG_BMA4XX_TEMPERATURE */
-			break;
-		case SENSOR_CHAN_ACCEL_X:
-		case SENSOR_CHAN_ACCEL_Y:
-		case SENSOR_CHAN_ACCEL_Z:
-		case SENSOR_CHAN_ACCEL_XYZ:
-			edata->has_accel = 1;
-			break;
-#ifdef CONFIG_BMA4XX_TEMPERATURE
-		case SENSOR_CHAN_DIE_TEMP:
-			edata->has_temp = 1;
-			break;
-#endif /* CONFIG_BMA4XX_TEMPERATURE */
-		default:
-			LOG_ERR("Requested unsupported channel type %d, idx %d",
-				channels[i].chan_type, channels[i].chan_idx);
-			rtio_iodev_sqe_err(iodev_sqe, -ENOTSUP);
-			return;
-		}
-	}
-
-	if (edata->has_accel) {
-		rc = bma4xx_sample_fetch(dev, &edata->accel_xyz[0], &edata->accel_xyz[1],
-					 &edata->accel_xyz[2]);
-		if (rc != 0) {
-			LOG_ERR("Failed to fetch accel samples");
-			rtio_iodev_sqe_err(iodev_sqe, rc);
-			return;
-		}
-	}
-
-#ifdef CONFIG_BMA4XX_TEMPERATURE
-	if (edata->has_temp) {
-		rc = bma4xx_temp_fetch(dev, &edata->temp);
-		if (rc != 0) {
-			LOG_ERR("Failed to fetch temp sample");
-			rtio_iodev_sqe_err(iodev_sqe, rc);
-			return;
-		}
-	}
-#endif /* CONFIG_BMA4XX_TEMPERATURE */
-
-	rtio_iodev_sqe_ok(iodev_sqe, 0);
-}
-
-static void bma4xx_submit_sync(struct rtio_iodev_sqe *iodev_sqe)
-{
-	const struct sensor_read_config *cfg = iodev_sqe->sqe.iodev->data;
-	const struct device *dev = cfg->sensor;
-
-	/* TODO: Add streaming support */
-	if (!cfg->is_streaming) {
-		bma4xx_submit_one_shot(dev, iodev_sqe);
-	} else {
-		rtio_iodev_sqe_err(iodev_sqe, -ENOTSUP);
-	}
-}
-
-static void bma4xx_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
-{
-	struct rtio_work_req *req = rtio_work_req_alloc();
-
-	if (req == NULL) {
-		LOG_ERR("RTIO work item allocation failed. Consider to increase "
-			"CONFIG_RTIO_WORKQ_POOL_ITEMS.");
-		rtio_iodev_sqe_err(iodev_sqe, -ENOMEM);
-		return;
-	}
-
-	rtio_work_req_submit(req, iodev_sqe, bma4xx_submit_sync);
-}
-
-/*
- * RTIO decoder
- */
-
-static int bma4xx_decoder_get_frame_count(const uint8_t *buffer, struct sensor_chan_spec ch,
-					  uint16_t *frame_count)
-{
-	const struct bma4xx_encoded_data *edata = (const struct bma4xx_encoded_data *)buffer;
-	const struct bma4xx_decoder_header *header = &edata->header;
-
-	if (ch.chan_idx != 0) {
-		return -ENOTSUP;
-	}
-
-	if (!header->is_fifo) {
-		switch (ch.chan_type) {
-		case SENSOR_CHAN_ACCEL_X:
-		case SENSOR_CHAN_ACCEL_Y:
-		case SENSOR_CHAN_ACCEL_Z:
-		case SENSOR_CHAN_ACCEL_XYZ:
-			*frame_count = edata->has_accel ? 1 : 0;
-			return 0;
-		case SENSOR_CHAN_DIE_TEMP:
-			*frame_count = edata->has_temp ? 1 : 0;
-			return 0;
-		default:
-			return -ENOTSUP;
-		}
-		return 0;
-	}
-
-	/* FIFO (streaming) mode operation is not yet supported */
-	return -ENOTSUP;
-}
-
-static int bma4xx_decoder_get_size_info(struct sensor_chan_spec ch, size_t *base_size,
-					size_t *frame_size)
-{
-	switch (ch.chan_type) {
-	case SENSOR_CHAN_ACCEL_X:
-	case SENSOR_CHAN_ACCEL_Y:
-	case SENSOR_CHAN_ACCEL_Z:
-	case SENSOR_CHAN_ACCEL_XYZ:
-		*base_size = sizeof(struct sensor_three_axis_data);
-		*frame_size = sizeof(struct sensor_three_axis_sample_data);
-		return 0;
-	case SENSOR_CHAN_DIE_TEMP:
-		*base_size = sizeof(struct sensor_q31_data);
-		*frame_size = sizeof(struct sensor_q31_sample_data);
-		return 0;
-	default:
-		return -ENOTSUP;
-	}
-}
-
-static int bma4xx_get_shift(struct sensor_chan_spec ch, uint8_t accel_fs, int8_t *shift)
-{
-	switch (ch.chan_type) {
-	case SENSOR_CHAN_ACCEL_X:
-	case SENSOR_CHAN_ACCEL_Y:
-	case SENSOR_CHAN_ACCEL_Z:
-	case SENSOR_CHAN_ACCEL_XYZ:
-		switch (accel_fs) {
-		case BMA4XX_RANGE_2G:
-			/* 2 G's = 19.62 m/s^2. Use shift of 5 (+/-32) */
-			*shift = 5;
-			return 0;
-		case BMA4XX_RANGE_4G:
-			*shift = 6;
-			return 0;
-		case BMA4XX_RANGE_8G:
-			*shift = 7;
-			return 0;
-		case BMA4XX_RANGE_16G:
-			*shift = 8;
-			return 0;
-		default:
-			return -EINVAL;
-		}
-	case SENSOR_CHAN_DIE_TEMP:
-		*shift = BMA4XX_TEMP_SHIFT;
-		return 0;
-	default:
-		return -EINVAL;
-	}
-}
-
-static void bma4xx_convert_raw_accel_to_q31(int16_t raw_val, q31_t *out)
-{
-	/* The full calculation is (assuming floating math):
-	 *   value_ms2 = raw_value * range * 9.8065 / BIT(11)
-	 * We can treat 'range * 9.8065' as a scale, the scale is calculated by first getting 1g
-	 * represented as a q31 value with the same shift as our result:
-	 *   1g = (9.8065 * BIT(31)) >> shift
-	 * Next, we need to multiply it by our range in g, which for this driver is one of
-	 * [2, 4, 8, 16] and maps to a left shift of [1, 2, 3, 4]:
-	 *   1g <<= log2(range)
-	 * Note we used a right shift by 'shift' and left shift by log2(range). 'shift' is
-	 * [5, 6, 7, 8] for range values [2, 4, 8, 16] since it's the final shift in m/s2. It is
-	 * calculated via:
-	 *   shift = ceil(log2(range * 9.8065))
-	 * This means that we can shorten the above 1g alterations to:
-	 *   1g = (1g >> ceil(log2(range * 9.8065))) << log2(range)
-	 * For the range values [2, 4, 8, 16], the following is true:
-	 *   (x >> ceil(log2(range * 9.8065))) << log2(range)
-	 *   = x >> 4
-	 * Since the range cancels out in the right and left shift, we've now reduced the following:
-	 *   range * 9.8065 = 9.8065 * BIT(31 - 4)
-	 * All that's left is to divide by the bma4xx's maximum range BIT(11).
-	 */
-	const int64_t scale = (int64_t)(9.8065 * BIT64(31 - 4));
-
-	*out = CLAMP(((int64_t)raw_val * scale) >> 11, INT32_MIN, INT32_MAX);
-}
-
-#ifdef CONFIG_BMA4XX_TEMPERATURE
-/**
- * @brief Convert the 8-bit temp register value into a Q31 celsius value
- */
-static void bma4xx_convert_raw_temp_to_q31(int8_t raw_val, q31_t *out)
-{
-	/* Value of 0 equals 23 degrees C. Each bit count equals 1 degree C */
-
-	int64_t intermediate =
-		((int64_t)raw_val + 23) * ((int64_t)INT32_MAX + 1) / (1 << BMA4XX_TEMP_SHIFT);
-
-	*out = CLAMP(intermediate, INT32_MIN, INT32_MAX);
-}
-#endif /* CONFIG_BMA4XX_TEMPERATURE */
-
-static int bma4xx_one_shot_decode(const uint8_t *buffer, struct sensor_chan_spec ch,
-				  uint32_t *fit, uint16_t max_count, void *data_out)
-{
-	const struct bma4xx_encoded_data *edata = (const struct bma4xx_encoded_data *)buffer;
-	const struct bma4xx_decoder_header *header = &edata->header;
-	int rc;
-
-	if (*fit != 0) {
-		return 0;
-	}
-	if (max_count == 0 || ch.chan_idx != 0) {
-		return -EINVAL;
-	}
-
-	switch (ch.chan_type) {
-	case SENSOR_CHAN_ACCEL_X:
-	case SENSOR_CHAN_ACCEL_Y:
-	case SENSOR_CHAN_ACCEL_Z:
-	case SENSOR_CHAN_ACCEL_XYZ: {
-		if (!edata->has_accel) {
-			return -ENODATA;
-		}
-
-		struct sensor_three_axis_data *out = (struct sensor_three_axis_data *)data_out;
-
-		out->header.base_timestamp_ns = edata->header.timestamp;
-		out->header.reading_count = 1;
-		rc = bma4xx_get_shift((struct sensor_chan_spec){.chan_type = SENSOR_CHAN_ACCEL_XYZ,
-								.chan_idx = 0},
-				      header->accel_fs, &out->shift);
-		if (rc != 0) {
-			return -EINVAL;
-		}
-
-		bma4xx_convert_raw_accel_to_q31(edata->accel_xyz[0], &out->readings[0].x);
-		bma4xx_convert_raw_accel_to_q31(edata->accel_xyz[1], &out->readings[0].y);
-		bma4xx_convert_raw_accel_to_q31(edata->accel_xyz[2], &out->readings[0].z);
-
-		*fit = 1;
-		return 1;
-	}
-#ifdef CONFIG_BMA4XX_TEMPERATURE
-	case SENSOR_CHAN_DIE_TEMP: {
-		if (!edata->has_temp) {
-			return -ENODATA;
-		}
-
-		struct sensor_q31_data *out = (struct sensor_q31_data *)data_out;
-
-		out->header.base_timestamp_ns = edata->header.timestamp;
-		out->header.reading_count = 1;
-		rc = bma4xx_get_shift(SENSOR_CHAN_DIE_TEMP, 0, &out->shift);
-		if (rc != 0) {
-			return -EINVAL;
-		}
-
-		bma4xx_convert_raw_temp_to_q31(edata->temp, &out->readings[0].temperature);
-
-		*fit = 1;
-		return 1;
-	}
-#endif /* CONFIG_BMA4XX_TEMPERATURE */
-	default:
-		return -EINVAL;
-	}
-}
-
-static int bma4xx_decoder_decode(const uint8_t *buffer, struct sensor_chan_spec ch,
-				 uint32_t *fit, uint16_t max_count,
-				 void *data_out)
-{
-	const struct bma4xx_decoder_header *header = (const struct bma4xx_decoder_header *)buffer;
-
-	if (header->is_fifo) {
-		/* FIFO (streaming) mode operation is not yet supported */
-		return -ENOTSUP;
-	}
-
-	return bma4xx_one_shot_decode(buffer, ch, fit, max_count, data_out);
-}
-
-SENSOR_DECODER_API_DT_DEFINE() = {
-	.get_frame_count = bma4xx_decoder_get_frame_count,
-	.get_size_info = bma4xx_decoder_get_size_info,
-	.decode = bma4xx_decoder_decode,
-};
-
-static int bma4xx_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder)
-{
-	ARG_UNUSED(dev);
-	*decoder = &SENSOR_DECODER_NAME();
-
 	return 0;
 }
 
@@ -685,40 +314,71 @@ static int bma4xx_get_decoder(const struct device *dev, const struct sensor_deco
 
 static DEVICE_API(sensor, bma4xx_driver_api) = {
 	.attr_set = bma4xx_attr_set,
-	.submit = bma4xx_submit,
 	.get_decoder = bma4xx_get_decoder,
+	.submit = bma4xx_submit,
 };
 
 /*
  * Device instantiation macros
  */
 
+#define BMA4XX_RTIO_I2C_DEFINE(inst)                                                               \
+	I2C_DT_IODEV_DEFINE(bma4xx_iodev_##inst, DT_DRV_INST(inst));                               \
+	RTIO_DEFINE(bma4xx_rtio_##inst, 8, 8);
+
+#define BMA4XX_RTIO_SPI_DEFINE(inst)                                                               \
+	SPI_DT_IODEV_DEFINE(bma4xx_iodev_##inst, DT_DRV_INST(inst));                               \
+	RTIO_DEFINE(bma4xx_rtio_##inst, 8, 8);
+
+#define BMA4XX_DEFINE_RTIO(inst)                                                                   \
+	COND_CODE_1(DT_INST_ON_BUS(inst, spi), (BMA4XX_RTIO_SPI_DEFINE(inst)), \
+	(BMA4XX_RTIO_I2C_DEFINE(inst)))
+
 /* Initializes a struct bma4xx_config for an instance on a SPI bus.
  * SPI operation is not currently supported.
  */
-
 #define BMA4XX_CONFIG_SPI(inst)                                                                    \
-	{                                                                                          \
-		.bus_cfg.spi = SPI_DT_SPEC_INST_GET(inst, 0, 0), .bus_init = &bma_spi_init,        \
-	}
+	.bus_cfg.spi = SPI_DT_SPEC_INST_GET(inst, 0, 0), .bus_init = &bma4xx_spi_init,             \
+	.bus_type = BMA4XX_BUS_SPI,
 
 /* Initializes a struct bma4xx_config for an instance on an I2C bus. */
 #define BMA4XX_CONFIG_I2C(inst)                                                                    \
+	.bus_cfg.i2c = I2C_DT_SPEC_INST_GET(inst), .bus_init = &bma4xx_i2c_init,                   \
+	.bus_type = BMA4XX_BUS_I2C,
+
+#define BMA4XX_DEFINE_BUS(inst)                                                                    \
+	COND_CODE_1(DT_INST_ON_BUS(inst, spi), (BMA4XX_CONFIG_SPI(inst)), (BMA4XX_CONFIG_I2C(inst)))
+
+#define BMA4XX_DT_CONFIG_INIT(inst)                                                                \
 	{                                                                                          \
-		.bus_cfg.i2c = I2C_DT_SPEC_INST_GET(inst), .bus_init = &bma4xx_i2c_init,           \
+		.fifo_en = IS_ENABLED(CONFIG_BMA4XX_STREAM),                                       \
+		.batch_ticks = 0,                                                                  \
+		.interrupt1_fifo_wm = false,                                                       \
+		.interrupt1_fifo_full = false,                                                     \
 	}
 
+#define BMA4XX_DEFINE_DATA(inst)                                                                   \
+	BMA4XX_DEFINE_RTIO(inst);                                                                  \
+	static struct bma4xx_data bma4xx_driver_##inst = {                                         \
+		.cfg = BMA4XX_DT_CONFIG_INIT(inst),                                                \
+		.r = &bma4xx_rtio_##inst,                                                          \
+		.iodev = &bma4xx_iodev_##inst,                                                     \
+	};
+
 /*
  * Main instantiation macro, which selects the correct bus-specific
  * instantiation macros for the instance.
  */
-#define BMA4XX_DEFINE(inst)                                                                        \
-	static struct bma4xx_data bma4xx_data_##inst;                                              \
-	static const struct bma4xx_config bma4xx_config_##inst = COND_CODE_1(                      \
-		DT_INST_ON_BUS(inst, spi), (BMA4XX_CONFIG_SPI(inst)), (BMA4XX_CONFIG_I2C(inst)));  \
+#define BMA4XX_INIT(inst)                                                                          \
+	BMA4XX_DEFINE_DATA(inst);                                                                  \
+                                                                                                   \
+	static const struct bma4xx_config bma4xx_config_##inst = {                                 \
+		BMA4XX_DEFINE_BUS(inst)                                                            \
+			IF_ENABLED(CONFIG_BMA4XX_STREAM, ( \
+		.gpio_interrupt = GPIO_DT_SPEC_INST_GET_OR(inst, int1_gpios, {0}),))};         \
                                                                                                    \
-	SENSOR_DEVICE_DT_INST_DEFINE(inst, bma4xx_chip_init, NULL, &bma4xx_data_##inst,            \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, bma4xx_chip_init, NULL, &bma4xx_driver_##inst,          \
 				     &bma4xx_config_##inst, POST_KERNEL,                           \
 				     CONFIG_SENSOR_INIT_PRIORITY, &bma4xx_driver_api);
 
-DT_INST_FOREACH_STATUS_OKAY(BMA4XX_DEFINE)
+DT_INST_FOREACH_STATUS_OKAY(BMA4XX_INIT);
diff --git a/drivers/sensor/bosch/bma4xx/bma4xx.h b/drivers/sensor/bosch/bma4xx/bma4xx.h
index 6184e40b062..e07f2fe6fff 100644
--- a/drivers/sensor/bosch/bma4xx/bma4xx.h
+++ b/drivers/sensor/bosch/bma4xx/bma4xx.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2023 Google LLC
+ * Copyright (c) 2024 Cienet
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,6 +11,8 @@
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/gpio.h>
+#include "bma4xx_defs.h"
 
 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
 #include <zephyr/drivers/spi.h>
@@ -19,157 +22,13 @@
 #include <zephyr/drivers/i2c.h>
 #endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */
 
-/*
- * Register definitions
- */
-
-#define BMA4XX_REG_CHIP_ID         (0x00)
-#define BMA4XX_REG_ERROR           (0x02)
-#define BMA4XX_REG_STATUS          (0x03)
-#define BMA4XX_REG_DATA_0          (0x0A)
-#define BMA4XX_REG_DATA_1          (0x0B)
-#define BMA4XX_REG_DATA_2          (0x0C)
-#define BMA4XX_REG_DATA_3          (0x0D)
-#define BMA4XX_REG_DATA_4          (0x0E)
-#define BMA4XX_REG_DATA_5          (0x0F)
-#define BMA4XX_REG_DATA_6          (0x10)
-#define BMA4XX_REG_DATA_7          (0x11)
-#define BMA4XX_REG_DATA_8          (0x12)
-#define BMA4XX_REG_DATA_9          (0x13)
-#define BMA4XX_REG_DATA_10         (0x14)
-#define BMA4XX_REG_DATA_11         (0x15)
-#define BMA4XX_REG_DATA_12         (0x16)
-#define BMA4XX_REG_DATA_13         (0x17)
-#define BMA4XX_REG_SENSORTIME_0    (0x18)
-#define BMA4XX_REG_INT_STAT_0      (0x1C)
-#define BMA4XX_REG_INT_STAT_1      (0x1D)
-#define BMA4XX_REG_STEP_CNT_OUT_0  (0x1E)
-#define BMA4XX_REG_HIGH_G_OUT      (0x1F)
-#define BMA4XX_REG_TEMPERATURE     (0x22)
-#define BMA4XX_REG_FIFO_LENGTH_0   (0x24)
-#define BMA4XX_REG_FIFO_LENGTH_1   (0x25)
-#define BMA4XX_REG_FIFO_DATA       (0x26)
-#define BMA4XX_REG_ACTIVITY_OUT    (0x27)
-#define BMA4XX_REG_ORIENTATION_OUT (0x28)
-#define BMA4XX_REG_ACCEL_CONFIG    (0x40)
-#define BMA4XX_REG_ACCEL_RANGE     (0x41)
-#define BMA4XX_REG_AUX_CONFIG      (0x44)
-#define BMA4XX_REG_FIFO_DOWN       (0x45)
-#define BMA4XX_REG_FIFO_WTM_0      (0x46)
-#define BMA4XX_REG_FIFO_CONFIG_0   (0x48)
-#define BMA4XX_REG_FIFO_CONFIG_1   (0x49)
-#define BMA4XX_REG_AUX_DEV_ID      (0x4B)
-#define BMA4XX_REG_AUX_IF_CONF     (0x4C)
-#define BMA4XX_REG_AUX_RD          (0x4D)
-#define BMA4XX_REG_AUX_WR          (0x4E)
-#define BMA4XX_REG_AUX_WR_DATA     (0x4F)
-#define BMA4XX_REG_INT1_IO_CTRL    (0x53)
-#define BMA4XX_REG_INT2_IO_CTRL    (0x54)
-#define BMA4XX_REG_INT_LATCH       (0x55)
-#define BMA4XX_REG_INT_MAP_1       (0x56)
-#define BMA4XX_REG_INT_MAP_2       (0x57)
-#define BMA4XX_REG_INT_MAP_DATA    (0x58)
-#define BMA4XX_REG_INIT_CTRL       (0x59)
-#define BMA4XX_REG_RESERVED_REG_5B (0x5B)
-#define BMA4XX_REG_RESERVED_REG_5C (0x5C)
-#define BMA4XX_REG_FEATURE_CONFIG  (0x5E)
-#define BMA4XX_REG_IF_CONFIG       (0x6B)
-#define BMA4XX_REG_ACC_SELF_TEST   (0x6D)
-#define BMA4XX_REG_NV_CONFIG       (0x70)
-#define BMA4XX_REG_OFFSET_0        (0x71)
-#define BMA4XX_REG_OFFSET_1        (0x72)
-#define BMA4XX_REG_OFFSET_2        (0x73)
-#define BMA4XX_REG_POWER_CONF      (0x7C)
-#define BMA4XX_REG_POWER_CTRL      (0x7D)
-#define BMA4XX_REG_CMD             (0x7E)
-
-/*
- * Bit positions and masks
- */
-
-#define BMA4XX_BIT_ADV_PWR_SAVE BIT(0)
-
-#define BMA4XX_MASK_ACC_CONF_ODR  GENMASK(3, 0)
-#define BMA4XX_MASK_ACC_CONF_BWP  GENMASK(6, 4)
-#define BMA4XX_SHIFT_ACC_CONF_BWP (4)
-
-#define BMA4XX_MASK_ACC_RANGE GENMASK(1, 0)
-
-#define BMA4XX_BIT_ACC_PERF_MODE BIT(7)
-
-#define BMA4XX_BIT_ACC_EN BIT(2)
-
-/* INT_STATUS_1 accelerometer data ready to interrupt */
-#define BMA4XX_ACC_DRDY_INT BIT(7)
-
-/* CMD: Clears all data in FIFO, does not change FIFO_CONFIG and FIFO_DOWNS register */
-#define BMA4XX_CMD_FIFO_FLUSH (0xB0)
-
-/* FIFO_CONFIG_1 enable: Store Accelerometer data in FIFO (all 3 axes) */
-#define BMA4XX_FIFO_ACC_EN BIT(6)
-
-/* Bandwidth parameters */
-#define BMA4XX_BWP_OSR4_AVG1  (0x0)
-#define BMA4XX_BWP_OSR2_AVG2  (0x1)
-#define BMA4XX_BWP_NORM_AVG4  (0x2)
-#define BMA4XX_BWP_CIC_AVG8   (0x3)
-#define BMA4XX_BWP_RES_AVG16  (0x4)
-#define BMA4XX_BWP_RES_AVG32  (0x5)
-#define BMA4XX_BWP_RES_AVG64  (0x6)
-#define BMA4XX_BWP_RES_AVG128 (0x7)
-
-/* Full-scale ranges */
-#define BMA4XX_RANGE_2G  (0x0)
-#define BMA4XX_RANGE_4G  (0x1)
-#define BMA4XX_RANGE_8G  (0x2)
-#define BMA4XX_RANGE_16G (0x3)
-
-/* Output data rates (ODR) */
-#define BMA4XX_ODR_RESERVED (0x00)
-#define BMA4XX_ODR_0_78125  (0x01)
-#define BMA4XX_ODR_1_5625   (0x02)
-#define BMA4XX_ODR_3_125    (0x03)
-#define BMA4XX_ODR_6_25     (0x04)
-#define BMA4XX_ODR_12_5     (0x05)
-#define BMA4XX_ODR_25       (0x06)
-#define BMA4XX_ODR_50       (0x07)
-#define BMA4XX_ODR_100      (0x08)
-#define BMA4XX_ODR_200      (0x09)
-#define BMA4XX_ODR_400      (0x0a)
-#define BMA4XX_ODR_800      (0x0b)
-#define BMA4XX_ODR_1600     (0x0c)
-#define BMA4XX_ODR_3200     (0x0d)
-#define BMA4XX_ODR_6400     (0x0e)
-#define BMA4XX_ODR_12800    (0x0f)
-
-/*
- * BMA4xx commands
- */
-
-#define BMA4XX_CMD_SOFT_RESET (0xB6)
-
-#define BMA4XX_CHIP_ID_BMA422 (0x12)
-#define BMA4XX_CHIP_ID_BMA423 (0x13)
-
-/*
- * Other constants
- */
-
-/* Each bit count is 3.9mG or 3900uG */
-#define BMA4XX_OFFSET_MICROG_PER_BIT (3900)
-#define BMA4XX_OFFSET_MICROG_MIN     (INT8_MIN * BMA4XX_OFFSET_MICROG_PER_BIT)
-#define BMA4XX_OFFSET_MICROG_MAX     (INT8_MAX * BMA4XX_OFFSET_MICROG_PER_BIT)
-
-/* Range is -104C to 150C. Use shift of 8 (+/-256) */
-#define BMA4XX_TEMP_SHIFT (8)
-
-/* The total number of used registers specified in bma422 datasheet is 7E */
-#define BMA4XX_NUM_REGS 0x7E
-
 /*
  * Types
  */
 
+#define BMA4XX_BUS_I2C 0
+#define BMA4XX_BUS_SPI 1
+
 union bma4xx_bus_cfg {
 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
 	struct i2c_dt_spec i2c;
@@ -183,6 +42,9 @@ union bma4xx_bus_cfg {
 struct bma4xx_config {
 	int (*bus_init)(const struct device *dev);
 	const union bma4xx_bus_cfg bus_cfg;
+	uint8_t bus_type;
+
+	const struct gpio_dt_spec gpio_interrupt;
 };
 
 /** Used to implement bus-specific R/W operations. See bma4xx_i2c.c and
@@ -196,46 +58,101 @@ struct bma4xx_hw_operations {
 	int (*update_reg)(const struct device *dev, uint8_t reg_addr, uint8_t mask, uint8_t value);
 };
 
-struct bma4xx_data {
+struct bma4xx_runtime_config {
+	bool fifo_en;
+	int32_t batch_ticks;
+
+	bool interrupt1_fifo_wm;
+	bool interrupt1_fifo_full;
+
+	uint8_t accel_pwr_mode;
+	uint8_t aux_pwr_mode;
+
 	/** Current full-scale range setting as a register value */
 	uint8_t accel_fs_range;
 	/** Current bandwidth parameter (BWP) as a register value */
 	uint8_t accel_bwp;
 	/** Current output data rate as a register value */
 	uint8_t accel_odr;
+};
+
+struct bma4xx_data {
+	struct bma4xx_runtime_config cfg;
 	/** Pointer to bus-specific I/O API */
 	const struct bma4xx_hw_operations *hw_ops;
 	/** Chip ID value stored in BMA4XX_REG_CHIP_ID */
 	uint8_t chip_id;
+	struct rtio *r;
+	struct rtio_iodev *iodev;
+#ifdef CONFIG_BMA4XX_STREAM
+	struct rtio_iodev_sqe *streaming_sqe;
+	uint8_t int_status;
+	uint16_t fifo_count;
+	uint64_t timestamp;
+	const struct device *dev;
+	struct gpio_callback gpio_cb;
+#endif /* CONFIG_BMA4XX_STREAM */
 };
 
-/*
- * RTIO types
- */
+static inline int bma4xx_accel_reg_to_hz(uint8_t odr, struct sensor_value *out)
+{
+	static const struct sensor_value odr_values[] = {
+		{0, 0},    {0, 781250}, {1, 562500}, {3, 125000}, {6, 250000}, {12, 500000},
+		{25, 0},   {50, 0},     {100, 0},    {200, 0},    {400, 0},    {800, 0},
+		{1600, 0}, {3200, 0},   {6400, 0},   {12800, 0},
+	};
 
-struct bma4xx_decoder_header {
-	uint64_t timestamp;
-	uint8_t is_fifo: 1;
-	uint8_t accel_fs: 2;
-	uint8_t reserved: 5;
-} __attribute__((__packed__));
-
-struct bma4xx_encoded_data {
-	struct bma4xx_decoder_header header;
-	struct {
-		/** Set if `accel_xyz` has data */
-		uint8_t has_accel: 1;
-		/** Set if `temp` has data */
-		uint8_t has_temp: 1;
-		uint8_t reserved: 6;
-	} __attribute__((__packed__));
-	int16_t accel_xyz[3];
-#ifdef CONFIG_BMA4XX_TEMPERATURE
-	int8_t temp;
-#endif /* CONFIG_BMA4XX_TEMPERATURE */
-};
+	if (odr >= ARRAY_SIZE(odr_values)) {
+		return -EINVAL;
+	}
 
+	*out = odr_values[odr];
+
+	return 0;
+}
+
+/**
+ * @brief Initialize the SPI bus
+ *
+ * @param dev bma4xx device pointer
+ *
+ * @retval 0 success
+ * @retval -errdev Error
+ */
 int bma4xx_spi_init(const struct device *dev);
+
+/**
+ * @brief Initialize the I2C bus
+ *
+ * @param dev bma4xx device pointer
+ *
+ * @retval 0 success
+ * @retval -errdev Error
+ */
 int bma4xx_i2c_init(const struct device *dev);
 
+/**
+ * @brief (Re)Configure the sensor with the given configuration
+ *
+ * @param dev bma4xx device pointer
+ * @param cfg bma4xx_runtime_config pointer
+ *
+ * @retval 0 success
+ * @retval -errno Error
+ */
+int bma4xx_configure(const struct device *dev, struct bma4xx_runtime_config *cfg);
+
+/**
+ * @brief Safely (re)Configure the sensor with the given configuration
+ *
+ * Will rollback to prior configuration if new configuration is invalid
+ *
+ * @param dev bma4xx device pointer
+ * @param cfg bma4xx_runtime_config pointer
+ *
+ * @retval 0 success
+ * @retval -errno Error
+ */
+int bma4xx_safely_configure(const struct device *dev, struct bma4xx_runtime_config *cfg);
+
 #endif /* ZEPHYR_DRIVERS_SENSOR_BMA4XX_BMA4XX_H_ */
diff --git a/drivers/sensor/bosch/bma4xx/bma4xx_common.c b/drivers/sensor/bosch/bma4xx/bma4xx_common.c
new file mode 100644
index 00000000000..0609e9285db
--- /dev/null
+++ b/drivers/sensor/bosch/bma4xx/bma4xx_common.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2024 Cienet
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT bosch_bma4xx
+
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/sensor_clock.h>
+#include "bma4xx.h"
+#include "bma4xx_interrupt.h"
+#include "bma4xx_defs.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(bma4xx, CONFIG_SENSOR_LOG_LEVEL);
+
+#ifdef CONFIG_BMA4XX_STREAM
+
+static uint16_t bma4xx_compute_fifo_wm(const struct bma4xx_runtime_config *new_cfg)
+{
+	int64_t odr;
+	int rc;
+	const bool accel_enabled = new_cfg->accel_pwr_mode != 0;
+	const bool aux_enabled = new_cfg->aux_pwr_mode != 0;
+
+	if (new_cfg->batch_ticks == 0 || !accel_enabled) {
+		return 0;
+	}
+
+	const int pkt_size = (accel_enabled && aux_enabled)
+				     ? BMA4XX_FIFO_MA_LENGTH + BMA4XX_FIFO_HEADER_LENGTH
+				     : BMA4XX_FIFO_A_LENGTH + BMA4XX_FIFO_HEADER_LENGTH;
+
+	struct sensor_value val = {0};
+
+	rc = bma4xx_accel_reg_to_hz(new_cfg->accel_odr, &val);
+
+	if (rc) {
+		LOG_ERR("Invalid ord value");
+		return -EINVAL;
+	}
+
+	/* Measured in Hz */
+	odr = sensor_value_to_micro(&val) / INT64_C(1000000);
+
+	/* Convert 'odr' to bytes * batch_ticks / sec */
+	odr *= (int64_t)new_cfg->batch_ticks * pkt_size;
+
+	/* 'odr' = byte_ticks_per_sec * sensor_ns_per_tick / NSEC_PER_SEC = bytes */
+	odr = DIV_ROUND_UP(sensor_clock_cycles_to_ns(odr), NSEC_PER_SEC);
+
+	return (uint16_t)MIN(odr, 0x3ff);
+}
+
+#endif /* CONFIG_BMA4XX_STREAM */
+
+int bma4xx_configure(const struct device *dev, struct bma4xx_runtime_config *cfg)
+{
+	struct bma4xx_data *dev_data = dev->data;
+	int res;
+	uint8_t value;
+
+	/* Disable interrupts, reconfigured at end */
+	res = dev_data->hw_ops->write_reg(dev, BMA4XX_REG_INT_MAP_DATA, 0);
+	__ASSERT(res == 0, "%s could not disable interrupts", __func__);
+
+	/* If FIFO is enabled now, disable and flush */
+	if (dev_data->cfg.fifo_en) {
+		res |= dev_data->hw_ops->write_reg(dev, BMA4XX_REG_FIFO_CONFIG_1,
+						   FIELD_PREP(BMA4XX_FIFO_ACC_EN, 0));
+		__ASSERT(res == 0, "%s could not disable fifo acceleration", __func__);
+
+		res |= dev_data->hw_ops->write_reg(dev, BMA4XX_REG_CMD,
+						   FIELD_PREP(BMA4XX_CMD_FIFO_FLUSH, 1));
+		__ASSERT(res == 0, "%s could not flush fifo", __func__);
+	}
+
+	/* Switch to performance power mode */
+	res |= dev_data->hw_ops->write_reg(dev, BMA4XX_REG_ACCEL_CONFIG,
+					   FIELD_PREP(BMA4XX_BIT_ACC_PERF_MODE, 1));
+	__ASSERT(res == 0, "%s could not enable performance power mode", __func__);
+
+	/* Enable non-latch mode
+	 * Regarding the discussion in the Bosch Community, enabling latch mode on bma4xx
+	 * might result in multiple FIFO interrupts. Therefore, it is recommended to use
+	 * non-latch mode instead.
+	 * Reference:
+	 * https://community.bosch-sensortec.com/mems-sensors-forum-jrmujtaw/post/bma456-sends-multiple-fifo-interrupt-bma4-fifo-wm-int-vWCT2Uz7Alv6flK
+	 */
+	res |= dev_data->hw_ops->write_reg(dev, BMA4XX_REG_INT_LATCH, 0);
+	__ASSERT(res == 0, "%s could not enable non-latch mode", __func__);
+
+	if (dev_data->cfg.accel_odr > 0) {
+		/* Enable accelerometer */
+		res |= dev_data->hw_ops->write_reg(dev, BMA4XX_REG_POWER_CTRL,
+						   FIELD_PREP(BMA4XX_BIT_POWER_CTRL_ACC_EN, 1));
+		__ASSERT(res == 0, "%s could not enable accelerometer", __func__);
+	} else {
+		LOG_DBG("Sample rate is 0, accelerometer not enabled");
+	}
+
+	/* Disable advance power save mode */
+	res |= dev_data->hw_ops->write_reg(dev, BMA4XX_REG_POWER_CONF,
+					   FIELD_PREP(BMA4XX_BIT_POWER_CONF_ADV_PWR_SAVE, 0));
+	__ASSERT(res == 0, "%s could not disable advance power save mode", __func__);
+
+	/* Write acceleration range */
+	res |= dev_data->hw_ops->write_reg(dev, BMA4XX_REG_ACCEL_RANGE,
+					   FIELD_PREP(BMA4XX_MASK_ACC_RANGE, cfg->accel_fs_range));
+	__ASSERT(res == 0, "%s could not write acceleration range", __func__);
+
+	/* Write data rate and bandwidth */
+	uint8_t odr_bw_value = FIELD_PREP(BMA4XX_MASK_ACC_CONF_ODR, cfg->accel_odr) |
+			       FIELD_PREP(BMA4XX_MASK_ACC_CONF_BWP, cfg->accel_bwp);
+
+	res |= dev_data->hw_ops->write_reg(dev, BMA4XX_REG_ACCEL_CONFIG, odr_bw_value);
+	__ASSERT(res == 0, "%s could not write data rate and bandwidth", __func__);
+
+	res |= dev_data->hw_ops->read_reg(dev, BMA4XX_REG_INT_STAT_1, &value);
+	__ASSERT(res == 0, "%s could not clear interrupt status", __func__);
+
+#ifdef CONFIG_BMA4XX_STREAM
+	if (cfg->fifo_en) {
+		LOG_INF("FIFO ENABLED");
+
+		/* Enable FIFO header mode and FIFO acceleration data and
+		 * disable FIFO auxiliary data.
+		 */
+		uint8_t fifo_config_1_value = FIELD_PREP(BMA4XX_FIFO_HEADER_EN, 1) |
+					      FIELD_PREP(BMA4XX_FIFO_ACC_EN, 1) |
+					      FIELD_PREP(BMA4XX_FIFO_AUX_EN, 0);
+
+		LOG_DBG("FIFO_CONFIG1 (0x%x) 0x%x", BMA4XX_REG_FIFO_CONFIG_1, fifo_config_1_value);
+		res |= dev_data->hw_ops->write_reg(dev, BMA4XX_REG_FIFO_CONFIG_1,
+						   fifo_config_1_value);
+		__ASSERT(res == 0, "%s could not write fifo config 1", __func__);
+
+		uint8_t pwr_ctrl_value = 0;
+
+		res |= dev_data->hw_ops->read_reg(dev, BMA4XX_REG_POWER_CTRL, &pwr_ctrl_value);
+		__ASSERT(res == 0, "%s could not read power ctrl value", __func__);
+
+		cfg->accel_pwr_mode = FIELD_GET(BMA4XX_BIT_POWER_CTRL_ACC_EN, pwr_ctrl_value);
+		cfg->aux_pwr_mode = FIELD_GET(BMA4XX_BIT_POWER_CTRL_AUX_EN, pwr_ctrl_value);
+
+		/* Set watermark and interrupt handling first */
+		uint16_t fifo_wm = bma4xx_compute_fifo_wm(cfg);
+
+		__ASSERT(fifo_wm >= 0, "%s could not get valid watermark value", __func__);
+
+		uint8_t fifo_wml = fifo_wm & 0xFF;
+
+		LOG_DBG("FIFO_WTM_0( (0x%x)) (WM Low) 0x%x", BMA4XX_REG_FIFO_WTM_0, fifo_wml);
+		res |= dev_data->hw_ops->write_reg(dev, BMA4XX_REG_FIFO_WTM_0, fifo_wml);
+		__ASSERT(res == 0, "%s could not write watermark level LSB", __func__);
+
+		uint8_t fifo_wmh = (fifo_wm >> 8) & 0x0F;
+
+		LOG_DBG("FIFO_WTM_1 (0x%x) (WM High) 0x%x", BMA4XX_REG_FIFO_WTM_1, fifo_wmh);
+		res |= dev_data->hw_ops->write_reg(dev, BMA4XX_REG_FIFO_WTM_1, fifo_wmh);
+		__ASSERT(res == 0, "%s could not write watermark level MSB", __func__);
+
+		res |= bma4xx_enable_interrupt1(dev, cfg);
+		__ASSERT(res == 0, "%s could not enable interrupts", __func__);
+
+	} else {
+#endif /* CONFIG_BMA4XX_STREAM */
+		LOG_INF("FIFO DISABLED");
+
+		/* No fifo mode so set data ready as interrupt source */
+		uint8_t int_map_data = FIELD_PREP(BMA4XX_BIT_INT_MAP_DATA_INT1_DRDY, 1);
+
+		LOG_DBG("MAP_DATA (0x%x) 0x%x", BMA4XX_REG_INT_MAP_DATA, int_map_data);
+		res |= dev_data->hw_ops->write_reg(dev, BMA4XX_REG_INT_MAP_DATA, int_map_data);
+		__ASSERT(res == 0, "%s could not enable FIFO data ready interrupt", __func__);
+
+#ifdef CONFIG_BMA4XX_STREAM
+	}
+#endif /* CONFIG_BMA4XX_STREAM */
+
+	return res;
+}
+
+int bma4xx_safely_configure(const struct device *dev, struct bma4xx_runtime_config *cfg)
+{
+	struct bma4xx_data *drv_data = dev->data;
+	int ret = bma4xx_configure(dev, cfg);
+
+	if (ret == 0) {
+		memcpy(&drv_data->cfg, cfg, sizeof(struct bma4xx_runtime_config));
+	} else {
+		ret = bma4xx_configure(dev, &drv_data->cfg);
+	}
+
+	return ret;
+}
diff --git a/drivers/sensor/bosch/bma4xx/bma4xx_decoder.c b/drivers/sensor/bosch/bma4xx/bma4xx_decoder.c
new file mode 100644
index 00000000000..58172173eca
--- /dev/null
+++ b/drivers/sensor/bosch/bma4xx/bma4xx_decoder.c
@@ -0,0 +1,411 @@
+/*
+ * Copyright (c) 2024 Cienet
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT bosch_bma4xx
+
+#include "bma4xx_decoder.h"
+#include "bma4xx_defs.h"
+#include "bma4xx.h"
+#include <errno.h>
+#include <zephyr/sys/byteorder.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(bma4xx, CONFIG_SENSOR_LOG_LEVEL);
+
+#define IS_ACCEL(chan)                                                                             \
+	((chan) == SENSOR_CHAN_ACCEL_X || (chan) == SENSOR_CHAN_ACCEL_Y ||                         \
+	 (chan) == SENSOR_CHAN_ACCEL_Z || (chan) == SENSOR_CHAN_ACCEL_XYZ)
+
+#ifdef CONFIG_BMA4XX_STREAM
+
+static uint64_t accel_period_ns[] = {
+	[BMA4XX_ODR_0_78125] = UINT64_C(100000000000000) / 78125,
+	[BMA4XX_ODR_1_5625] = UINT64_C(10000000000000) / 15625,
+	[BMA4XX_ODR_3_125] = UINT64_C(10000000000000) / 31250,
+	[BMA4XX_ODR_6_25] = UINT64_C(10000000000000) / 62500,
+	[BMA4XX_ODR_12_5] = UINT64_C(1000000000000) / 12500,
+	[BMA4XX_ODR_25] = UINT64_C(1000000000) / 25,
+	[BMA4XX_ODR_50] = UINT64_C(1000000000) / 50,
+	[BMA4XX_ODR_100] = UINT64_C(1000000000) / 100,
+	[BMA4XX_ODR_200] = UINT64_C(1000000000) / 200,
+	[BMA4XX_ODR_400] = UINT64_C(1000000000) / 400,
+	[BMA4XX_ODR_800] = UINT64_C(1000000000) / 800,
+	[BMA4XX_ODR_1600] = UINT64_C(10000000) / 16,
+	[BMA4XX_ODR_3200] = UINT64_C(10000000) / 32,
+	[BMA4XX_ODR_6400] = UINT64_C(10000000) / 64,
+	[BMA4XX_ODR_12800] = UINT64_C(10000000) / 128,
+};
+
+#endif /* CONFIG_BMA4XX_STREAM */
+
+/*
+ * RTIO decoder
+ */
+
+static int bma4xx_decoder_get_frame_count(const uint8_t *buffer, struct sensor_chan_spec ch,
+					  uint16_t *frame_count)
+{
+	const struct bma4xx_fifo_data *edata = (const struct bma4xx_fifo_data *)buffer;
+	const struct bma4xx_decoder_header *header = &edata->header;
+
+	if (ch.chan_idx != 0) {
+		return -ENOTSUP;
+	}
+
+	if (!header->is_fifo) {
+		switch (ch.chan_type) {
+		case SENSOR_CHAN_ACCEL_X:
+		case SENSOR_CHAN_ACCEL_Y:
+		case SENSOR_CHAN_ACCEL_Z:
+		case SENSOR_CHAN_ACCEL_XYZ:
+		case SENSOR_CHAN_DIE_TEMP:
+			*frame_count = 1;
+			return 0;
+		default:
+			return -ENOTSUP;
+		}
+	}
+
+	if (!IS_ACCEL(ch.chan_type)) {
+		return -ENOTSUP;
+	}
+	/* Skip the header */
+	buffer += sizeof(struct bma4xx_fifo_data);
+
+	uint16_t count = 0;
+	const uint8_t *end = buffer + edata->fifo_count;
+
+	while (buffer < end) {
+		uint8_t size = BMA4XX_FIFO_HEADER_LENGTH;
+		const bool has_accel = FIELD_GET(BMA4XX_BIT_FIFO_HEADER_ACCEL, buffer[0]) == 1;
+		const bool has_aux = FIELD_GET(BMA4XX_BIT_FIFO_HEADER_AUX, buffer[0]) == 1;
+
+		if (FIELD_GET(BMA4XX_BIT_FIFO_HEADER_REGULAR, buffer[0])) {
+			if (has_accel && has_aux) {
+				size += BMA4XX_FIFO_MA_LENGTH;
+			} else if (has_accel) {
+				size += BMA4XX_FIFO_A_LENGTH;
+			} else if (has_aux) {
+				size += BMA4XX_FIFO_M_LENGTH;
+			}
+			++count;
+		} else if (FIELD_GET(BMA4XX_BIT_FIFO_HEADER_CONTROL, buffer[0])) {
+			if (FIELD_GET(BMA4XX_BIT_FIFO_HEADER_SENSORTIME, buffer[0])) {
+				size += BMA4XX_FIFO_ST_LENGTH;
+			} else if (FIELD_GET(BMA4XX_BIT_FIFO_HEAD_OVER_READ_MSB, buffer[0])) {
+				size = *end;
+			} else {
+				size += BMA4XX_FIFO_CF_LENGTH;
+			}
+		}
+
+		buffer += size;
+	}
+
+	*frame_count = count;
+
+	return 0;
+}
+
+static int bma4xx_decoder_get_size_info(struct sensor_chan_spec ch, size_t *base_size,
+					size_t *frame_size)
+{
+	switch (ch.chan_type) {
+	case SENSOR_CHAN_ACCEL_X:
+	case SENSOR_CHAN_ACCEL_Y:
+	case SENSOR_CHAN_ACCEL_Z:
+	case SENSOR_CHAN_ACCEL_XYZ:
+		*base_size = sizeof(struct sensor_three_axis_data);
+		*frame_size = sizeof(struct sensor_three_axis_sample_data);
+		return 0;
+	case SENSOR_CHAN_DIE_TEMP:
+		*base_size = sizeof(struct sensor_q31_data);
+		*frame_size = sizeof(struct sensor_q31_sample_data);
+		return 0;
+	default:
+		return -ENOTSUP;
+	}
+}
+
+static int bma4xx_get_shift(struct sensor_chan_spec ch, uint8_t accel_fs, int8_t *shift)
+{
+	switch (ch.chan_type) {
+	case SENSOR_CHAN_ACCEL_X:
+	case SENSOR_CHAN_ACCEL_Y:
+	case SENSOR_CHAN_ACCEL_Z:
+	case SENSOR_CHAN_ACCEL_XYZ:
+		switch (accel_fs) {
+		case BMA4XX_RANGE_2G:
+			/* 2 G's = 19.62 m/s^2. Use shift of 5 (+/-32) */
+			*shift = 5;
+			return 0;
+		case BMA4XX_RANGE_4G:
+			*shift = 6;
+			return 0;
+		case BMA4XX_RANGE_8G:
+			*shift = 7;
+			return 0;
+		case BMA4XX_RANGE_16G:
+			*shift = 8;
+			return 0;
+		default:
+			return -EINVAL;
+		}
+	case SENSOR_CHAN_DIE_TEMP:
+		*shift = BMA4XX_TEMP_SHIFT;
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
+static void bma4xx_convert_raw_accel_to_q31(int16_t raw_val, q31_t *out)
+{
+	/* The full calculation is (assuming floating math):
+	 *   value_ms2 = raw_value * range * 9.80665 / BIT(11)
+	 * We can treat 'range * 9.80665' as a scale, the scale is calculated by first getting 1g
+	 * represented as a q31 value with the same shift as our result:
+	 *   1g = (9.80665 * BIT(31)) >> shift
+	 * Next, we need to multiply it by our range in g, which for this driver is one of
+	 * [2, 4, 8, 16] and maps to a left shift of [1, 2, 3, 4]:
+	 *   1g <<= log2(range)
+	 * Note we used a right shift by 'shift' and left shift by log2(range). 'shift' is
+	 * [5, 6, 7, 8] for range values [2, 4, 8, 16] since it's the final shift in m/s2. It is
+	 * calculated via:
+	 *   shift = ceil(log2(range * 9.80665))
+	 * This means that we can shorten the above 1g alterations to:
+	 *   1g = (1g >> ceil(log2(range * 9.80665))) << log2(range)
+	 * For the range values [2, 4, 8, 16], the following is true:
+	 *   (x >> ceil(log2(range * 9.80665))) << log2(range)
+	 *   = x >> 4
+	 * Since the range cancels out in the right and left shift, we've now reduced the following:
+	 *   range * 9.80665 = 9.80665 * BIT(31 - 4)
+	 * All that's left is to divide by the bma4xx's maximum range BIT(11).
+	 */
+
+	int16_t value = (int16_t)sys_le16_to_cpu(raw_val << 4) >> 4;
+
+	const int64_t scale = (int64_t)(9.80665 * BIT64(31 - 4));
+
+	*out = CLAMP(((int64_t)value * scale) >> 11, INT32_MIN, INT32_MAX);
+}
+
+#ifdef CONFIG_BMA4XX_STREAM
+
+static void bma4xx_unpack_accel_data(const uint8_t *pkt, uint8_t data_start_index, q31_t *out)
+{
+	uint8_t offset = BMA4XX_FIFO_HEADER_LENGTH + (data_start_index * 2);
+	const bool has_aux = FIELD_GET(BMA4XX_BIT_FIFO_HEADER_AUX, pkt[0]) == 1;
+
+	if (has_aux) {
+		offset += BMA4XX_FIFO_M_LENGTH;
+	}
+
+	int16_t value = (pkt[offset + 1] << 4) | FIELD_GET(GENMASK(7, 4), pkt[offset]);
+
+	bma4xx_convert_raw_accel_to_q31((int16_t)value, out);
+}
+
+#endif /* CONFIG_BMA4XX_STREAM */
+
+#ifdef CONFIG_BMA4XX_TEMPERATURE
+/**
+ * @brief Convert the 8-bit temp register value into a Q31 celsius value
+ */
+static void bma4xx_convert_raw_temp_to_q31(int8_t raw_val, q31_t *out)
+{
+	/* Value of 0 equals 23 degrees C. Each bit count equals 1 degree C */
+
+	int64_t intermediate =
+		((int64_t)raw_val + 23) * ((int64_t)INT32_MAX + 1) / (1 << BMA4XX_TEMP_SHIFT);
+
+	*out = CLAMP(intermediate, INT32_MIN, INT32_MAX);
+}
+#endif /* CONFIG_BMA4XX_TEMPERATURE */
+
+static int bma4xx_one_shot_decode(const uint8_t *buffer, struct sensor_chan_spec ch, uint32_t *fit,
+				  uint16_t max_count, void *data_out)
+{
+	const struct bma4xx_encoded_data *edata = (const struct bma4xx_encoded_data *)buffer;
+	const struct bma4xx_decoder_header *header = &edata->header;
+	int16_t raw_x, raw_y, raw_z;
+	int rc;
+
+	if (*fit != 0) {
+		return 0;
+	}
+	if (max_count == 0 || ch.chan_idx != 0) {
+		return -EINVAL;
+	}
+
+	switch (ch.chan_type) {
+	case SENSOR_CHAN_ACCEL_X:
+	case SENSOR_CHAN_ACCEL_Y:
+	case SENSOR_CHAN_ACCEL_Z:
+	case SENSOR_CHAN_ACCEL_XYZ: {
+		struct sensor_three_axis_data *out = (struct sensor_three_axis_data *)data_out;
+
+		out->header.base_timestamp_ns = edata->header.timestamp;
+		out->header.reading_count = 1;
+		rc = bma4xx_get_shift((struct sensor_chan_spec){.chan_type = SENSOR_CHAN_ACCEL_XYZ,
+								.chan_idx = 3},
+				      header->accel_fs, &out->shift);
+		if (rc != 0) {
+			return -EINVAL;
+		}
+
+		raw_x = (((int16_t)edata->accel_xyz_raw_data[1]) << 4) |
+			FIELD_GET(GENMASK(7, 4), edata->accel_xyz_raw_data[0]);
+		raw_y = (((int16_t)edata->accel_xyz_raw_data[3]) << 4) |
+			FIELD_GET(GENMASK(7, 4), edata->accel_xyz_raw_data[2]);
+		raw_z = (((int16_t)edata->accel_xyz_raw_data[5]) << 4) |
+			FIELD_GET(GENMASK(7, 4), edata->accel_xyz_raw_data[4]);
+
+		bma4xx_convert_raw_accel_to_q31(raw_x, &out->readings[0].x);
+		bma4xx_convert_raw_accel_to_q31(raw_y, &out->readings[0].y);
+		bma4xx_convert_raw_accel_to_q31(raw_z, &out->readings[0].z);
+
+		*fit = 1;
+		return 1;
+	}
+#ifdef CONFIG_BMA4XX_TEMPERATURE
+	case SENSOR_CHAN_DIE_TEMP: {
+		struct sensor_q31_data *out = (struct sensor_q31_data *)data_out;
+
+		out->header.base_timestamp_ns = edata->header.timestamp;
+		out->header.reading_count = 1;
+		rc = bma4xx_get_shift((struct sensor_chan_spec){.chan_type = SENSOR_CHAN_DIE_TEMP,
+								.chan_idx = 12},
+				      0, &out->shift);
+
+		if (rc != 0) {
+			return -EINVAL;
+		}
+
+		bma4xx_convert_raw_temp_to_q31(edata->temp, &out->readings[0].temperature);
+
+		*fit = 1;
+		return 1;
+	}
+#endif /* CONFIG_BMA4XX_TEMPERATURE */
+	default:
+		return -EINVAL;
+	}
+}
+
+#ifdef CONFIG_BMA4XX_STREAM
+
+static int bma4xx_fifo_decode(const uint8_t *buffer, struct sensor_chan_spec ch, uint32_t *fit,
+			      uint16_t max_count, void *data_out)
+{
+	const struct bma4xx_fifo_data *edata = (const struct bma4xx_fifo_data *)buffer;
+	const uint8_t *buffer_end = buffer + sizeof(struct bma4xx_fifo_data) + edata->fifo_count;
+	int accel_frame_count = 0;
+	int count = 0;
+
+	if ((uintptr_t)buffer_end <= *fit || ch.chan_idx != 0) {
+		return 0;
+	}
+
+	if (!IS_ACCEL(ch.chan_type)) {
+		return -ENOTSUP;
+	}
+
+	((struct sensor_data_header *)data_out)->base_timestamp_ns = edata->header.timestamp;
+
+	buffer += sizeof(struct bma4xx_fifo_data);
+
+	while (count < max_count && buffer < buffer_end) {
+		const bool has_accel = FIELD_GET(BMA4XX_BIT_FIFO_HEADER_ACCEL, buffer[0]) == 1;
+		const bool has_aux = FIELD_GET(BMA4XX_BIT_FIFO_HEADER_AUX, buffer[0]) == 1;
+		const uint8_t *frame_end = buffer;
+
+		if (FIELD_GET(BMA4XX_BIT_FIFO_HEADER_REGULAR, buffer[0])) {
+			if (has_accel && has_aux) {
+				frame_end += BMA4XX_FIFO_MA_LENGTH + BMA4XX_FIFO_HEADER_LENGTH;
+				accel_frame_count++;
+			} else if (has_accel) {
+				frame_end += BMA4XX_FIFO_A_LENGTH + BMA4XX_FIFO_HEADER_LENGTH;
+				accel_frame_count++;
+			} else if (has_aux) {
+				frame_end += BMA4XX_FIFO_M_LENGTH + BMA4XX_FIFO_HEADER_LENGTH;
+			}
+		} else if (FIELD_GET(BMA4XX_BIT_FIFO_HEADER_CONTROL, buffer[0])) {
+			if (FIELD_GET(BMA4XX_BIT_FIFO_HEADER_SENSORTIME, buffer[0])) {
+				frame_end += BMA4XX_FIFO_ST_LENGTH + BMA4XX_FIFO_HEADER_LENGTH;
+			} else if (FIELD_GET(BMA4XX_BIT_FIFO_HEAD_OVER_READ_MSB, buffer[0])) {
+				frame_end = buffer_end;
+			} else {
+				frame_end += BMA4XX_FIFO_CF_LENGTH + BMA4XX_FIFO_HEADER_LENGTH;
+			}
+		}
+
+		if ((uintptr_t)buffer < *fit) {
+			/* This frame was already decoded, move on to the next frame */
+			buffer = frame_end;
+			continue;
+		}
+
+		if (has_accel) {
+			struct sensor_three_axis_data *data =
+				(struct sensor_three_axis_data *)data_out;
+
+			uint64_t period_ns = accel_period_ns[edata->accel_odr];
+
+			bma4xx_get_shift(
+				(struct sensor_chan_spec){.chan_type = SENSOR_CHAN_ACCEL_XYZ,
+							  .chan_idx = 3},
+				edata->header.accel_fs, &data->shift);
+			data->readings[count].timestamp_delta = (accel_frame_count - 1) * period_ns;
+			bma4xx_unpack_accel_data(buffer, 0, &data->readings[count].x);
+			bma4xx_unpack_accel_data(buffer, 1, &data->readings[count].y);
+			bma4xx_unpack_accel_data(buffer, 2, &data->readings[count].z);
+		}
+
+		buffer = frame_end;
+		*fit = (uintptr_t)frame_end;
+		count++;
+	}
+
+	return count;
+}
+
+#endif /* CONFIG_BMA4XX_STREAM */
+
+static int bma4xx_decoder_decode(const uint8_t *buffer, struct sensor_chan_spec ch, uint32_t *fit,
+				 uint16_t max_count, void *data_out)
+{
+#ifdef CONFIG_BMA4XX_STREAM
+
+	const struct bma4xx_decoder_header *header = (const struct bma4xx_decoder_header *)buffer;
+
+	if (header->is_fifo) {
+		return bma4xx_fifo_decode(buffer, ch, fit, max_count, data_out);
+	}
+#endif
+
+	return bma4xx_one_shot_decode(buffer, ch, fit, max_count, data_out);
+}
+
+static bool bma4xx_decoder_has_trigger(const uint8_t *buffer, enum sensor_trigger_type trigger)
+{
+	return false;
+}
+
+SENSOR_DECODER_API_DT_DEFINE() = {
+	.get_frame_count = bma4xx_decoder_get_frame_count,
+	.get_size_info = bma4xx_decoder_get_size_info,
+	.decode = bma4xx_decoder_decode,
+	.has_trigger = bma4xx_decoder_has_trigger,
+};
+
+int bma4xx_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder)
+{
+	ARG_UNUSED(dev);
+	*decoder = &SENSOR_DECODER_NAME();
+
+	return 0;
+}
diff --git a/drivers/sensor/bosch/bma4xx/bma4xx_decoder.h b/drivers/sensor/bosch/bma4xx/bma4xx_decoder.h
new file mode 100644
index 00000000000..5be6883ecc8
--- /dev/null
+++ b/drivers/sensor/bosch/bma4xx/bma4xx_decoder.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2024 Cienet
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_BMA4XX_DECODER_H_
+#define ZEPHYR_DRIVERS_SENSOR_BMA4XX_DECODER_H_
+
+#include <stdint.h>
+#include <zephyr/drivers/sensor.h>
+
+/*
+ * RTIO types
+ */
+
+struct bma4xx_decoder_header {
+	uint64_t timestamp;
+	uint8_t is_fifo: 1;
+	uint8_t accel_fs: 2;
+	uint8_t reserved: 5;
+} __attribute__((__packed__));
+
+struct bma4xx_fifo_data {
+	struct bma4xx_decoder_header header;
+	uint8_t int_status;
+	uint16_t accel_odr: 4;
+	uint16_t fifo_count: 10;
+	uint16_t reserved: 1;
+} __attribute__((__packed__));
+
+struct bma4xx_encoded_data {
+	struct bma4xx_decoder_header header;
+	uint8_t accel_xyz_raw_data[6];
+#ifdef CONFIG_BMA4XX_TEMPERATURE
+	int8_t temp;
+#endif /* CONFIG_BMA4XX_TEMPERATURE */
+};
+
+int bma4xx_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder);
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_BMA4XX_DECODER_H_ */
diff --git a/drivers/sensor/bosch/bma4xx/bma4xx_defs.h b/drivers/sensor/bosch/bma4xx/bma4xx_defs.h
new file mode 100644
index 00000000000..243b8eafd3e
--- /dev/null
+++ b/drivers/sensor/bosch/bma4xx/bma4xx_defs.h
@@ -0,0 +1,219 @@
+/*
+ * Copyright (c) 2024 Cienet
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_BMA4XX_REG_H_
+#define ZEPHYR_DRIVERS_SENSOR_BMA4XX_REG_H_
+
+#include <zephyr/sys/util.h>
+
+/*
+ * Register definitions
+ */
+
+#define BMA4XX_REG_CHIP_ID         (0x00)
+#define BMA4XX_REG_ERROR           (0x02)
+#define BMA4XX_REG_STATUS          (0x03)
+#define BMA4XX_REG_DATA_0          (0x0A)
+#define BMA4XX_REG_DATA_1          (0x0B)
+#define BMA4XX_REG_DATA_2          (0x0C)
+#define BMA4XX_REG_DATA_3          (0x0D)
+#define BMA4XX_REG_DATA_4          (0x0E)
+#define BMA4XX_REG_DATA_5          (0x0F)
+#define BMA4XX_REG_DATA_6          (0x10)
+#define BMA4XX_REG_DATA_7          (0x11)
+#define BMA4XX_REG_DATA_8          (0x12)
+#define BMA4XX_REG_DATA_9          (0x13)
+#define BMA4XX_REG_DATA_10         (0x14)
+#define BMA4XX_REG_DATA_11         (0x15)
+#define BMA4XX_REG_DATA_12         (0x16)
+#define BMA4XX_REG_DATA_13         (0x17)
+#define BMA4XX_REG_SENSORTIME_0    (0x18)
+#define BMA4XX_REG_EVENT           (0x1B)
+#define BMA4XX_REG_INT_STAT_0      (0x1C)
+#define BMA4XX_REG_INT_STAT_1      (0x1D)
+#define BMA4XX_REG_STEP_CNT_OUT_0  (0x1E)
+#define BMA4XX_REG_HIGH_G_OUT      (0x1F)
+#define BMA4XX_REG_TEMPERATURE     (0x22)
+#define BMA4XX_REG_FIFO_LENGTH_0   (0x24)
+#define BMA4XX_REG_FIFO_LENGTH_1   (0x25)
+#define BMA4XX_REG_FIFO_DATA       (0x26)
+#define BMA4XX_REG_ACTIVITY_OUT    (0x27)
+#define BMA4XX_REG_ORIENTATION_OUT (0x28)
+#define BMA4XX_REG_ACCEL_CONFIG    (0x40)
+#define BMA4XX_REG_ACCEL_RANGE     (0x41)
+#define BMA4XX_REG_AUX_CONFIG      (0x44)
+#define BMA4XX_REG_FIFO_DOWN       (0x45)
+#define BMA4XX_REG_FIFO_WTM_0      (0x46)
+#define BMA4XX_REG_FIFO_WTM_1      (0x47)
+#define BMA4XX_REG_FIFO_CONFIG_0   (0x48)
+#define BMA4XX_REG_FIFO_CONFIG_1   (0x49)
+#define BMA4XX_REG_AUX_DEV_ID      (0x4B)
+#define BMA4XX_REG_AUX_IF_CONF     (0x4C)
+#define BMA4XX_REG_AUX_RD          (0x4D)
+#define BMA4XX_REG_AUX_WR          (0x4E)
+#define BMA4XX_REG_AUX_WR_DATA     (0x4F)
+#define BMA4XX_REG_INT1_IO_CTRL    (0x53)
+#define BMA4XX_REG_INT2_IO_CTRL    (0x54)
+#define BMA4XX_REG_INT_LATCH       (0x55)
+#define BMA4XX_REG_INT_MAP_1       (0x56)
+#define BMA4XX_REG_INT_MAP_2       (0x57)
+#define BMA4XX_REG_INT_MAP_DATA    (0x58)
+#define BMA4XX_REG_INIT_CTRL       (0x59)
+#define BMA4XX_REG_RESERVED_REG_5B (0x5B)
+#define BMA4XX_REG_RESERVED_REG_5C (0x5C)
+#define BMA4XX_REG_FEATURE_CONFIG  (0x5E)
+#define BMA4XX_REG_IF_CONFIG       (0x6B)
+#define BMA4XX_REG_ACC_SELF_TEST   (0x6D)
+#define BMA4XX_REG_NV_CONFIG       (0x70)
+#define BMA4XX_REG_OFFSET_0        (0x71)
+#define BMA4XX_REG_OFFSET_1        (0x72)
+#define BMA4XX_REG_OFFSET_2        (0x73)
+#define BMA4XX_REG_POWER_CONF      (0x7C)
+#define BMA4XX_REG_POWER_CTRL      (0x7D)
+#define BMA4XX_REG_CMD             (0x7E)
+
+/* BMA4xx I2C register */
+#define BMA4XX_REG_I2C_SDO_HIGH (0x19)
+#define BMA4XX_REG_I2C_SDO_LOW  (0x18)
+
+/*
+ * Bit positions and masks
+ */
+
+#define BMA4XX_REG_ADDRESS_MASK GENMASK(7, 0)
+
+#define BMA4XX_BIT_ADV_PWR_SAVE BIT(0)
+
+#define BMA4XX_MASK_ACC_CONF_ODR  GENMASK(3, 0)
+#define BMA4XX_MASK_ACC_CONF_BWP  GENMASK(6, 4)
+#define BMA4XX_SHIFT_ACC_CONF_BWP (4)
+
+#define BMA4XX_MASK_ACC_RANGE GENMASK(1, 0)
+
+#define BMA4XX_BIT_ACC_PERF_MODE BIT(7)
+
+/* CMD: Clears all data in FIFO, does not change FIFO_CONFIG and FIFO_DOWNS register */
+#define BMA4XX_CMD_FIFO_FLUSH (0xB0)
+
+/* BMA4xx EVENT bit definition */
+#define BMA4XX_BIT_POR_DETECTED BIT(0)
+
+/* BMA4xx INT1_IO_CTRL bit definition */
+#define BMA4XX_BIT_INT1_IO_CTRL_EDGE_CTRL BIT(0)
+#define BMA4XX_BIT_INT1_IO_CTRL_LVL       BIT(1)
+#define BMA4XX_BIT_INT1_IO_CTRL_OD        BIT(2)
+#define BMA4XX_BIT_INT1_IO_CTRL_OUTPUT_EN BIT(3)
+#define BMA4XX_BIT_INT1_IO_CTRL_INPUT_EN  BIT(4)
+
+/* BMA4xx INT_MAP_DATA bit definition */
+#define BMA4XX_BIT_INT_MAP_DATA_INT1_FFUL BIT(0)
+#define BMA4XX_BIT_INT_MAP_DATA_INT1_FWM  BIT(1)
+#define BMA4XX_BIT_INT_MAP_DATA_INT1_DRDY BIT(2)
+
+/* BMA4xx INT_STATUS_1 bit definition */
+#define BMA4XX_BIT_INT_STAT_1_FFULL_INT    BIT(0)
+#define BMA4XX_BIT_INT_STAT_1_FWM_INT      BIT(1)
+#define BMA4XX_BIT_INT_STAT_1_ACC_DRDY_INT BIT(7)
+
+/* BMA4xx PWR_CTRL bit definition */
+#define BMA4XX_BIT_POWER_CTRL_AUX_EN BIT(0)
+#define BMA4XX_BIT_POWER_CTRL_ACC_EN BIT(2)
+
+/* BMA4xx PWR_CONF bit definition */
+#define BMA4XX_BIT_POWER_CONF_ADV_PWR_SAVE BIT(0)
+
+/* BMA4xx EVENT bit definition */
+#define BMA4XX_BIT_EVENT_POR_DETECTED BIT(0)
+
+/* BMA4xx FIFO_CONFIG_1 bit definition */
+#define BMA4XX_FIFO_ACC_EN    BIT(6)
+#define BMA4XX_FIFO_AUX_EN    BIT(5)
+#define BMA4XX_FIFO_HEADER_EN BIT(4)
+
+/* Bandwidth parameters */
+#define BMA4XX_BWP_OSR4_AVG1  (0x0)
+#define BMA4XX_BWP_OSR2_AVG2  (0x1)
+#define BMA4XX_BWP_NORM_AVG4  (0x2)
+#define BMA4XX_BWP_CIC_AVG8   (0x3)
+#define BMA4XX_BWP_RES_AVG16  (0x4)
+#define BMA4XX_BWP_RES_AVG32  (0x5)
+#define BMA4XX_BWP_RES_AVG64  (0x6)
+#define BMA4XX_BWP_RES_AVG128 (0x7)
+
+/* Full-scale ranges */
+#define BMA4XX_RANGE_2G  (0x0)
+#define BMA4XX_RANGE_4G  (0x1)
+#define BMA4XX_RANGE_8G  (0x2)
+#define BMA4XX_RANGE_16G (0x3)
+
+/* Output data rates (ODR) */
+#define BMA4XX_ODR_RESERVED (0x00)
+#define BMA4XX_ODR_0_78125  (0x01)
+#define BMA4XX_ODR_1_5625   (0x02)
+#define BMA4XX_ODR_3_125    (0x03)
+#define BMA4XX_ODR_6_25     (0x04)
+#define BMA4XX_ODR_12_5     (0x05)
+#define BMA4XX_ODR_25       (0x06)
+#define BMA4XX_ODR_50       (0x07)
+#define BMA4XX_ODR_100      (0x08)
+#define BMA4XX_ODR_200      (0x09)
+#define BMA4XX_ODR_400      (0x0a)
+#define BMA4XX_ODR_800      (0x0b)
+#define BMA4XX_ODR_1600     (0x0c)
+#define BMA4XX_ODR_3200     (0x0d)
+#define BMA4XX_ODR_6400     (0x0e)
+#define BMA4XX_ODR_12800    (0x0f)
+
+/* BMA4xx soft-reset commands */
+#define BMA4XX_CMD_SOFT_RESET (0xB6)
+
+/* BMA4xx chip id */
+#define BMA4XX_CHIP_ID_BMA422 (0x12)
+#define BMA4XX_CHIP_ID_BMA423 (0x13)
+
+#define BMA4XX_REG_I2C_READ_BIT BIT(7)
+
+/*
+ * BMA4xx FIFO Header bit definition
+ */
+
+/* fh_parm, regular */
+#define BMA4XX_BIT_FIFO_HEADER_ACCEL BIT(2)
+#define BMA4XX_BIT_FIFO_HEADER_AUX   BIT(4)
+
+/* fh_mode */
+#define BMA4XX_BIT_FIFO_HEADER_CONTROL BIT(6)
+#define BMA4XX_BIT_FIFO_HEADER_REGULAR BIT(7)
+
+/* fh_parm, control */
+#define BMA4XX_BIT_FIFO_HEADER_SENSORTIME  BIT(2)
+#define BMA4XX_BIT_FIFO_HEAD_OVER_READ_MSB BIT(5)
+
+/*
+ * Other constants
+ */
+
+/* BMA4xx FIFO Length definition */
+#define BMA4XX_FIFO_HEADER_LENGTH UINT8_C(1)
+#define BMA4XX_FIFO_A_LENGTH      UINT8_C(6)
+#define BMA4XX_FIFO_M_LENGTH      UINT8_C(8)
+#define BMA4XX_FIFO_MA_LENGTH     UINT8_C(14)
+#define BMA4XX_FIFO_ST_LENGTH     UINT8_C(3)
+#define BMA4XX_FIFO_CF_LENGTH     UINT8_C(1)
+#define BMA4XX_FIFO_DATA_LENGTH   UINT8_C(2)
+
+/* Each bit count is 3.9mG or 3900uG */
+#define BMA4XX_OFFSET_MICROG_PER_BIT (3900)
+#define BMA4XX_OFFSET_MICROG_MIN     (INT8_MIN * BMA4XX_OFFSET_MICROG_PER_BIT)
+#define BMA4XX_OFFSET_MICROG_MAX     (INT8_MAX * BMA4XX_OFFSET_MICROG_PER_BIT)
+
+/* Range is -104C to 150C. Use shift of 8 (+/-256) */
+#define BMA4XX_TEMP_SHIFT (8)
+
+/* The total number of used registers specified in bma422 datasheet is 7E */
+#define BMA4XX_NUM_REGS 0x7E
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_BMA4XX_REG_H_ */
diff --git a/drivers/sensor/bosch/bma4xx/bma4xx_emul.c b/drivers/sensor/bosch/bma4xx/bma4xx_emul.c
index ec5f069da53..65818c91767 100644
--- a/drivers/sensor/bosch/bma4xx/bma4xx_emul.c
+++ b/drivers/sensor/bosch/bma4xx/bma4xx_emul.c
@@ -22,7 +22,7 @@
 
 #define DT_DRV_COMPAT bosch_bma4xx
 
-LOG_MODULE_REGISTER(bma4xx_emul, CONFIG_SENSOR_LOG_LEVEL);
+LOG_MODULE_DECLARE(bma4xx, CONFIG_SENSOR_LOG_LEVEL);
 
 struct bma4xx_emul_data {
 	/* Holds register data. */
@@ -44,6 +44,7 @@ void bma4xx_emul_set_reg(const struct emul *target, uint8_t reg_addr, const uint
 void bma4xx_emul_get_reg(const struct emul *target, uint8_t reg_addr, uint8_t *val, size_t count)
 {
 	struct bma4xx_emul_data *data = target->data;
+	LOG_INF("*** bma4xx_emul_get_reg: %x, %d", reg_addr, count);
 
 	__ASSERT_NO_MSG(reg_addr + count <= BMA4XX_NUM_REGS);
 	memcpy(val, data->regs + reg_addr, count);
@@ -125,11 +126,11 @@ static int bma4xx_emul_write_byte(const struct emul *target, int reg, uint8_t va
 		data->regs[reg] = val;
 		return 0;
 	case BMA4XX_REG_POWER_CTRL:
-		if ((val & ~BMA4XX_BIT_ACC_EN) != 0) {
+		if ((val & ~BMA4XX_BIT_POWER_CTRL_ACC_EN) != 0) {
 			LOG_ERR("unhandled bits in POWER_CTRL write: %#x", val);
 			return -ENOTSUP;
 		}
-		data->regs[reg] = (val & BMA4XX_BIT_ACC_EN) != 0;
+		data->regs[reg] = (val & BMA4XX_BIT_POWER_CTRL_ACC_EN) != 0;
 		return 0;
 	case BMA4XX_REG_CMD:
 		if (val == BMA4XX_CMD_FIFO_FLUSH) { /* fifo_flush */
@@ -151,6 +152,7 @@ static int bma4xx_emul_init(const struct emul *target, const struct device *pare
 
 	data->regs[BMA4XX_REG_CHIP_ID] = BMA4XX_CHIP_ID_BMA422;
 	data->regs[BMA4XX_REG_ACCEL_RANGE] = BMA4XX_RANGE_4G;
+	data->regs[BMA4XX_REG_EVENT] = 0x01;
 
 	return 0;
 }
@@ -209,6 +211,8 @@ void bma4xx_emul_set_accel_data(const struct emul *target, q31_t value, int8_t s
 
 	intermediate /= accel_range;
 
+	intermediate = intermediate > 0 ? intermediate + 1 : intermediate;
+
 	reg_val = CLAMP(intermediate, -2048, 2047);
 
 	/* lsb register uses top 12 of 16 bits to hold value so shift by 4 to fill it */
@@ -245,7 +249,7 @@ static int bma4xx_emul_backend_set_channel(const struct emul *target, struct sen
 	}
 
 	/* Set data ready flag */
-	data->regs[BMA4XX_REG_INT_STAT_1] |= BMA4XX_ACC_DRDY_INT;
+	data->regs[BMA4XX_REG_INT_STAT_1] |= BMA4XX_BIT_INT_STAT_1_ACC_DRDY_INT;
 
 	return 0;
 }
@@ -270,34 +274,36 @@ static int bma4xx_emul_backend_get_sample_range(const struct emul *target,
 
 	struct bma4xx_emul_data *data = target->data;
 
+	int16_t upper_bound_scale = (BIT(11) - 1);
+
 	switch (data->regs[BMA4XX_REG_ACCEL_RANGE]) {
 	case BMA4XX_RANGE_2G:
 		*shift = 5;
-		*upper = (q31_t)(2 * 9.80665 * BIT(31 - 5));
-		*lower = -*upper;
-		/* (1 << (31 - shift) >> 12) * 2 (where 2 comes from 2g range) */
-		*epsilon = BIT(31 - 5 - 12 + 1);
+		*upper = (q31_t)(2 * 9.80665 * upper_bound_scale * BIT(31 - 11 - 5));
+		*lower = -(q31_t)(2 * 9.80665 * BIT(31 - 5));
+		/* (1 << (31 - shift) >> 11) * 2 (where 2 comes from 2g range) */
+		*epsilon = 9.80665 * BIT(31 - 5 - 11 + 1);
 		break;
 	case BMA4XX_RANGE_4G:
 		*shift = 6;
-		*upper = (q31_t)(4 * 9.80665 * BIT(31 - 6));
-		*lower = -*upper;
-		/* (1 << (31 - shift) >> 12) * 4 (where 4 comes from 4g range) */
-		*epsilon = BIT(31 - 6 - 12 + 2);
+		*upper = (q31_t)(4 * 9.80665 * upper_bound_scale * BIT(31 - 11 - 6));
+		*lower = -(q31_t)(4 * 9.80665 * BIT(31 - 6));
+		/* (1 << (31 - shift) >> 11) * 4 (where 4 comes from 4g range) */
+		*epsilon = 9.80665 * BIT(31 - 6 - 11 + 2);
 		break;
 	case BMA4XX_RANGE_8G:
 		*shift = 7;
-		*upper = (q31_t)(8 * 9.80665 * BIT(31 - 7));
-		*lower = -*upper;
-		/* (1 << (31 - shift) >> 12) * 8 (where 8 comes from 8g range) */
-		*epsilon = BIT(31 - 7 - 12 + 3);
+		*upper = (q31_t)(8 * 9.80665 * upper_bound_scale * BIT(31 - 11 - 7));
+		*lower = -(q31_t)(8 * 9.80665 * BIT(31 - 7));
+		/* (1 << (31 - shift) >> 11) * 8 (where 8 comes from 8g range) */
+		*epsilon = 9.80665 * BIT(31 - 7 - 11 + 3);
 		break;
 	case BMA4XX_RANGE_16G:
 		*shift = 8;
-		*upper = (q31_t)(16 * 9.80665 * BIT(31 - 8));
-		*lower = -*upper;
-		/* (1 << (31 - shift) >> 12) * 16 (where 16 comes from 16g range) */
-		*epsilon = BIT(31 - 8 - 12 + 4);
+		*upper = (q31_t)(16 * 9.80665 * upper_bound_scale * BIT(31 - 11 - 8));
+		*lower = -(q31_t)(16 * 9.80665 * BIT(31 - 8));
+		/* (1 << (31 - shift) >> 11) * 16 (where 16 comes from 16g range) */
+		*epsilon = 9.80665 * BIT(31 - 8 - 11 + 4);
 		break;
 	default:
 		return -ENOTSUP;
diff --git a/drivers/sensor/bosch/bma4xx/bma4xx_i2c.c b/drivers/sensor/bosch/bma4xx/bma4xx_i2c.c
index e21631c45fe..321be8cc232 100644
--- a/drivers/sensor/bosch/bma4xx/bma4xx_i2c.c
+++ b/drivers/sensor/bosch/bma4xx/bma4xx_i2c.c
@@ -29,9 +29,26 @@ static int bma4xx_i2c_write_data(const struct device *dev, uint8_t reg_addr,
 				  uint8_t *value, uint8_t len)
 {
 	const struct bma4xx_config *cfg = dev->config;
+	const struct bma4xx_data *bma4xx = dev->data;
+	int res = 0;
 
-	return i2c_burst_write_dt(&cfg->bus_cfg.i2c, reg_addr, value,
-				  len);
+	res = i2c_burst_write_dt(&cfg->bus_cfg.i2c, reg_addr, value, len);
+	if (res) {
+		LOG_ERR("Could not perform i2c write data");
+		return -ENOTSUP;
+	}
+
+	/* A 1.3us delay is required after write operation when device operates in
+	 * power performance mode whereas 1000us is required when the device operates
+	 * in low power mode.
+	 */
+	if (bma4xx->cfg.accel_pwr_mode) {
+		k_sleep(K_NSEC(1300));
+	} else {
+		k_sleep(K_USEC(1000));
+	}
+
+	return 0;
 }
 
 static int bma4xx_i2c_read_reg(const struct device *dev, uint8_t reg_addr,
@@ -46,16 +63,51 @@ static int bma4xx_i2c_write_reg(const struct device *dev, uint8_t reg_addr,
 				uint8_t value)
 {
 	const struct bma4xx_config *cfg = dev->config;
+	const struct bma4xx_data *bma4xx = dev->data;
+	int res = 0;
+
+	res = i2c_reg_write_byte_dt(&cfg->bus_cfg.i2c, reg_addr, value);
+	if (res) {
+		LOG_ERR("Could not perform i2c write reg");
+		return -ENOTSUP;
+	}
 
-	return i2c_reg_write_byte_dt(&cfg->bus_cfg.i2c, reg_addr, value);
+	/* A 1.3us delay is required after write operation when device operates in
+	 * power performance mode whereas 1000us is required when the device operates
+	 * in low power mode.
+	 */
+	if (bma4xx->cfg.accel_pwr_mode) {
+		k_sleep(K_NSEC(1300));
+	} else {
+		k_sleep(K_USEC(1000));
+	}
+
+	return 0;
 }
 
 static int bma4xx_i2c_update_reg(const struct device *dev, uint8_t reg_addr,
 				  uint8_t mask, uint8_t value)
 {
 	const struct bma4xx_config *cfg = dev->config;
+	const struct bma4xx_data *bma4xx = dev->data;
+	int res = 0;
 
-	return i2c_reg_update_byte_dt(&cfg->bus_cfg.i2c, reg_addr, mask, value);
+	res = i2c_reg_update_byte_dt(&cfg->bus_cfg.i2c, reg_addr, mask, value);
+	if (res) {
+		LOG_ERR("Could not perform i2c update data");
+		return -ENOTSUP;
+	}
+
+	/* A 1.3us delay is required after write operation when device operates in
+	 * power performance mode whereas 1000us is required when the device operates
+	 * in low power mode.
+	 */
+	if (bma4xx->cfg.accel_pwr_mode) {
+		k_sleep(K_NSEC(1300));
+	} else {
+		k_sleep(K_USEC(1000));
+	}
+	return 0;
 }
 
 static const struct bma4xx_hw_operations i2c_ops = {
diff --git a/drivers/sensor/bosch/bma4xx/bma4xx_interrupt.c b/drivers/sensor/bosch/bma4xx/bma4xx_interrupt.c
new file mode 100644
index 00000000000..4eacdb3059f
--- /dev/null
+++ b/drivers/sensor/bosch/bma4xx/bma4xx_interrupt.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2024 Cienet
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT bosch_bma4xx
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/util.h>
+
+#include "bma4xx.h"
+#include "bma4xx_interrupt.h"
+#include "bma4xx_defs.h"
+#include "bma4xx_rtio.h"
+
+LOG_MODULE_DECLARE(bma4xx, CONFIG_SENSOR_LOG_LEVEL);
+
+#ifdef CONFIG_BMA4XX_STREAM
+
+static void bma4xx_gpio_callback(const struct device *dev, struct gpio_callback *cb, uint32_t pins)
+{
+	struct bma4xx_data *data = CONTAINER_OF(cb, struct bma4xx_data, gpio_cb);
+
+	ARG_UNUSED(dev);
+	ARG_UNUSED(pins);
+
+	bma4xx_fifo_event(data->dev);
+}
+
+int bma4xx_init_interrupt(const struct device *dev)
+{
+	struct bma4xx_data *data = dev->data;
+	const struct bma4xx_config *cfg = dev->config;
+	int ret = 0;
+
+	if (!cfg->gpio_interrupt.port) {
+		LOG_ERR("Stream enabled but no interrupt gpio supplied");
+		return -ENODEV;
+	}
+
+	if (!gpio_is_ready_dt(&cfg->gpio_interrupt)) {
+		LOG_ERR("GPIO interrupt not ready");
+		return -ENODEV;
+	}
+
+	ret = gpio_pin_configure_dt(&cfg->gpio_interrupt, GPIO_INPUT);
+	if (ret < 0) {
+		LOG_ERR("Failed to configure gpio pin");
+		return ret;
+	}
+
+	gpio_init_callback(&data->gpio_cb, bma4xx_gpio_callback, BIT(cfg->gpio_interrupt.pin));
+
+	ret = gpio_add_callback(cfg->gpio_interrupt.port, &data->gpio_cb);
+	if (ret < 0) {
+		LOG_ERR("Failed to add gpio callback");
+		return ret;
+	}
+
+	data->dev = dev;
+
+	return 0;
+}
+
+int bma4xx_enable_interrupt1(const struct device *dev, struct bma4xx_runtime_config *new_cfg)
+{
+	struct bma4xx_data *data = dev->data;
+	uint8_t value = 0;
+
+	if (new_cfg->interrupt1_fifo_wm) {
+		value |= FIELD_PREP(BMA4XX_BIT_INT_MAP_DATA_INT1_FWM, 1);
+	}
+	if (new_cfg->interrupt1_fifo_full) {
+		value |= FIELD_PREP(BMA4XX_BIT_INT_MAP_DATA_INT1_FFUL, 1);
+	}
+
+	return data->hw_ops->write_reg(dev, BMA4XX_REG_INT_MAP_DATA, value);
+}
+
+#endif /* CONFIG_BMA4XX_STREAM */
diff --git a/drivers/sensor/bosch/bma4xx/bma4xx_interrupt.h b/drivers/sensor/bosch/bma4xx/bma4xx_interrupt.h
new file mode 100644
index 00000000000..51802ff5229
--- /dev/null
+++ b/drivers/sensor/bosch/bma4xx/bma4xx_interrupt.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2024 Cienet
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_BMA4XX_INTERRUPT_H_
+#define ZEPHYR_DRIVERS_SENSOR_BMA4XX_INTERRUPT_H_
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/sensor.h>
+
+/**
+ * @brief Initialize the bma4xx interrupt system
+ *
+ * @param dev bma4xx device pointer
+ * @return int 0 on success, negative error code otherwise
+ */
+int bma4xx_init_interrupt(const struct device *dev);
+
+/**
+ * @brief Enable the trigger gpio interrupt1
+ *
+ * @param dev bma4xx device pointer
+ * @param new_cfg New configuration to use for the device
+ * @return int 0 on success, negative error code otherwise
+ */
+int bma4xx_enable_interrupt1(const struct device *dev, struct bma4xx_runtime_config *new_cfg);
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_BMA4XX_INTERRUPT_H_ */
diff --git a/drivers/sensor/bosch/bma4xx/bma4xx_rtio.c b/drivers/sensor/bosch/bma4xx/bma4xx_rtio.c
new file mode 100644
index 00000000000..5027646aecd
--- /dev/null
+++ b/drivers/sensor/bosch/bma4xx/bma4xx_rtio.c
@@ -0,0 +1,153 @@
+/*
+ * Copyright (c) 2024 Cienet
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT bosch_bma4xx
+
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/rtio/work.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/drivers/sensor_clock.h>
+
+#include "bma4xx.h"
+#include "bma4xx_decoder.h"
+#include "bma4xx_defs.h"
+#include "bma4xx_rtio.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(bma4xx, CONFIG_SENSOR_LOG_LEVEL);
+
+static void bma4xx_complete_result(struct rtio *ctx, const struct rtio_sqe *sqe, void *arg)
+{
+	struct rtio_iodev_sqe *iodev_sqe = (struct rtio_iodev_sqe *)sqe->userdata;
+	struct rtio_cqe *cqe;
+	int err = 0;
+
+	do {
+		cqe = rtio_cqe_consume(ctx);
+		if (cqe != NULL) {
+			err = cqe->result;
+			rtio_cqe_release(ctx, cqe);
+		}
+	} while (cqe != NULL);
+	if (err) {
+		rtio_iodev_sqe_err(iodev_sqe, err);
+	} else {
+		rtio_iodev_sqe_ok(iodev_sqe, 0);
+	}
+	LOG_DBG("bma4xx_submit_fetch completed");
+}
+
+/*
+ * RTIO submit and encoding
+ */
+
+static void bma4xx_submit_one_shot(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
+{
+	const struct bma4xx_data *bma4xx = dev->data;
+	const struct bma4xx_config *drv_cfg = dev->config;
+	struct bma4xx_encoded_data *edata;
+	uint8_t *buf;
+	uint32_t buf_len;
+	uint32_t min_buf_len = sizeof(struct bma4xx_encoded_data);
+	uint64_t cycles;
+	int rc;
+
+	/* Get the buffer for the frame, it may be allocated dynamically by the rtio context */
+	rc = rtio_sqe_rx_buf(iodev_sqe, min_buf_len, min_buf_len, &buf, &buf_len);
+	if (rc != 0) {
+		LOG_ERR("Failed to get a read buffer of size %u bytes", min_buf_len);
+		rtio_iodev_sqe_err(iodev_sqe, rc);
+		return;
+	}
+
+	/* Prepare response */
+	edata = (struct bma4xx_encoded_data *)buf;
+
+	if (IS_ENABLED(CONFIG_BMA4XX_STREAM)) {
+		edata->header.is_fifo = false;
+	}
+
+	edata->header.accel_fs = bma4xx->cfg.accel_fs_range;
+
+	rc = sensor_clock_get_cycles(&cycles);
+	if (rc != 0) {
+		LOG_ERR("Failed to get sensor clock cycles");
+		rtio_iodev_sqe_err(iodev_sqe, rc);
+		return;
+	}
+
+	edata->header.timestamp = sensor_clock_cycles_to_ns(cycles);
+
+	struct rtio_sqe *write_accel_sqe = rtio_sqe_acquire(bma4xx->r);
+	struct rtio_sqe *read_accel_sqe = rtio_sqe_acquire(bma4xx->r);
+
+	if (!write_accel_sqe || !read_accel_sqe) {
+		LOG_ERR("Failed to acquire RTIO SQEs");
+		rtio_iodev_sqe_err(iodev_sqe, -ENOMEM);
+		return;
+	}
+
+	const uint8_t reg_accel = BMA4XX_REG_DATA_8;
+
+	rtio_sqe_prep_tiny_write(write_accel_sqe, bma4xx->iodev, RTIO_PRIO_HIGH, &reg_accel, 1,
+				 NULL);
+	write_accel_sqe->flags |= RTIO_SQE_TRANSACTION;
+
+	rtio_sqe_prep_read(read_accel_sqe, bma4xx->iodev, RTIO_PRIO_HIGH, edata->accel_xyz_raw_data,
+			   BMA4XX_REG_DATA_13 - BMA4XX_REG_DATA_8 + 1, NULL);
+	read_accel_sqe->flags |= RTIO_SQE_CHAINED;
+
+	if (drv_cfg->bus_type == BMA4XX_BUS_I2C) {
+		read_accel_sqe->iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART;
+	}
+
+#ifdef CONFIG_BMA4XX_TEMPERATURE
+	struct rtio_sqe *write_temp_sqe = rtio_sqe_acquire(bma4xx->r);
+	struct rtio_sqe *read_temp_sqe = rtio_sqe_acquire(bma4xx->r);
+
+	if (!write_temp_sqe || !read_temp_sqe) {
+		LOG_ERR("Failed to acquire RTIO SQEs");
+		rtio_iodev_sqe_err(iodev_sqe, -ENOMEM);
+		return;
+	}
+
+	const uint8_t reg_temp = BMA4XX_REG_TEMPERATURE;
+
+	rtio_sqe_prep_tiny_write(write_temp_sqe, bma4xx->iodev, RTIO_PRIO_HIGH, &reg_temp, 1, NULL);
+	write_temp_sqe->flags |= RTIO_SQE_TRANSACTION;
+
+	rtio_sqe_prep_read(read_temp_sqe, bma4xx->iodev, RTIO_PRIO_HIGH, &edata->temp, 1, NULL);
+	read_temp_sqe->flags |= RTIO_SQE_CHAINED;
+
+	if (drv_cfg->bus_type == BMA4XX_BUS_I2C) {
+		read_temp_sqe->iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART;
+	}
+#endif /* CONFIG_BMA4XX_TEMPERATURE */
+
+	struct rtio_sqe *complete_sqe = rtio_sqe_acquire(bma4xx->r);
+
+	if (!complete_sqe) {
+		LOG_ERR("Failed to acquire RTIO SQEs");
+		rtio_iodev_sqe_err(iodev_sqe, -ENOMEM);
+		return;
+	}
+
+	rtio_sqe_prep_callback_no_cqe(complete_sqe, bma4xx_complete_result, (void *)dev, iodev_sqe);
+	rtio_submit(bma4xx->r, 0);
+}
+
+void bma4xx_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
+{
+	const struct sensor_read_config *cfg = iodev_sqe->sqe.iodev->data;
+
+	if (!cfg->is_streaming) {
+		bma4xx_submit_one_shot(dev, iodev_sqe);
+	} else if (IS_ENABLED(CONFIG_BMA4XX_STREAM)) {
+		bma4xx_submit_stream(dev, iodev_sqe);
+	} else {
+		rtio_iodev_sqe_err(iodev_sqe, -ENOTSUP);
+	}
+}
diff --git a/drivers/sensor/bosch/bma4xx/bma4xx_rtio.h b/drivers/sensor/bosch/bma4xx/bma4xx_rtio.h
new file mode 100644
index 00000000000..382d6f8be37
--- /dev/null
+++ b/drivers/sensor/bosch/bma4xx/bma4xx_rtio.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2023 Google LLC
+ * Copyright (c) 2024 Cienet
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_BMA4XX_RTIO_H_
+#define ZEPHYR_DRIVERS_SENSOR_BMA4XX_RTIO_H_
+
+#include <zephyr/device.h>
+#include <zephyr/rtio/rtio.h>
+
+void bma4xx_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe);
+
+void bma4xx_submit_stream(const struct device *sensor, struct rtio_iodev_sqe *iodev_sqe);
+
+void bma4xx_fifo_event(const struct device *dev);
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_BMA4XX_RTIO_H_ */
diff --git a/drivers/sensor/bosch/bma4xx/bma4xx_rtio_stream.c b/drivers/sensor/bosch/bma4xx/bma4xx_rtio_stream.c
new file mode 100644
index 00000000000..563c0f3cd81
--- /dev/null
+++ b/drivers/sensor/bosch/bma4xx/bma4xx_rtio_stream.c
@@ -0,0 +1,355 @@
+/*
+ * Copyright (c) 2024 Cienet
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT bosch_bma4xx
+
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/sensor_clock.h>
+
+#include "bma4xx.h"
+#include "bma4xx_defs.h"
+#include "bma4xx_decoder.h"
+#include "bma4xx_rtio.h"
+
+#ifdef CONFIG_BMA4XX_STREAM
+
+LOG_MODULE_DECLARE(bma4xx, CONFIG_SENSOR_LOG_LEVEL);
+
+void bma4xx_submit_stream(const struct device *sensor, struct rtio_iodev_sqe *iodev_sqe)
+{
+	const struct sensor_read_config *cfg = iodev_sqe->sqe.iodev->data;
+	struct bma4xx_data *data = sensor->data;
+	struct bma4xx_runtime_config new_config = data->cfg;
+	const struct bma4xx_config *cfg_bma4xx = sensor->config;
+	int ret;
+
+	ret = gpio_pin_interrupt_configure_dt(&cfg_bma4xx->gpio_interrupt, GPIO_INT_DISABLE);
+	if (ret) {
+		LOG_DBG("Failed to disable interrupt");
+		rtio_iodev_sqe_err(iodev_sqe, ret);
+		return;
+	}
+
+	new_config.interrupt1_fifo_wm = false;
+	new_config.interrupt1_fifo_full = false;
+	/* Only one trigger will be sent per time */
+	for (int i = 0; i < cfg->count; ++i) {
+		switch (cfg->triggers[i].trigger) {
+		case SENSOR_TRIG_FIFO_WATERMARK:
+			new_config.interrupt1_fifo_wm = true;
+			break;
+		case SENSOR_TRIG_FIFO_FULL:
+			new_config.interrupt1_fifo_full = true;
+			break;
+		default:
+			LOG_DBG("Trigger (%d) not supported", cfg->triggers[i].trigger);
+			rtio_iodev_sqe_err(iodev_sqe, -ENOTSUP);
+			return;
+		}
+	}
+
+	if (new_config.interrupt1_fifo_wm != data->cfg.interrupt1_fifo_wm ||
+	    new_config.interrupt1_fifo_full != data->cfg.interrupt1_fifo_full) {
+
+		ret = bma4xx_safely_configure(sensor, &new_config);
+
+		if (ret != 0) {
+			LOG_ERR("Failed to configure sensor");
+			rtio_iodev_sqe_err(iodev_sqe, ret);
+			return;
+		}
+	}
+
+	ret = gpio_pin_interrupt_configure_dt(&cfg_bma4xx->gpio_interrupt, GPIO_INT_EDGE_TO_ACTIVE);
+	if (ret) {
+		LOG_DBG("Failed to set interrupt");
+		rtio_iodev_sqe_err(iodev_sqe, ret);
+		return;
+	}
+
+	data->streaming_sqe = iodev_sqe;
+}
+
+static struct sensor_stream_trigger *
+bma4xx_get_read_config_trigger(const struct sensor_read_config *cfg, enum sensor_trigger_type trig)
+{
+	for (int i = 0; i < cfg->count; ++i) {
+		if (cfg->triggers[i].trigger == trig) {
+			return &cfg->triggers[i];
+		}
+	}
+	LOG_DBG("Unsupported trigger (%d)", trig);
+	return NULL;
+}
+
+static void bma4xx_complete_cb(struct rtio *r, const struct rtio_sqe *sqe, void *arg)
+{
+	const struct device *dev = arg;
+	struct bma4xx_data *drv_data = dev->data;
+	const struct bma4xx_config *drv_cfg = dev->config;
+	struct rtio_iodev_sqe *iodev_sqe = sqe->userdata;
+
+	rtio_iodev_sqe_ok(iodev_sqe, drv_data->fifo_count);
+
+	gpio_pin_interrupt_configure_dt(&drv_cfg->gpio_interrupt, GPIO_INT_EDGE_TO_ACTIVE);
+}
+
+static void bma4xx_fifo_count_cb(struct rtio *r, const struct rtio_sqe *sqe, void *arg)
+{
+	const struct device *dev = arg;
+	struct bma4xx_data *drv_data = dev->data;
+	const struct bma4xx_config *drv_cfg = dev->config;
+	struct rtio_iodev *iodev = drv_data->iodev;
+	uint8_t *fifo_count_buf = (uint8_t *)&drv_data->fifo_count;
+	uint16_t fifo_count = (((fifo_count_buf[1] & 0x3F) << 8) | fifo_count_buf[0]);
+
+	drv_data->fifo_count = fifo_count;
+
+	/* Pull a operation from our device iodev queue, validated to only be reads */
+	struct rtio_iodev_sqe *iodev_sqe = drv_data->streaming_sqe;
+
+	drv_data->streaming_sqe = NULL;
+
+	/* Not inherently an underrun/overrun as we may have a buffer to fill next time */
+	if (iodev_sqe == NULL) {
+		LOG_DBG("No pending SQE");
+		gpio_pin_interrupt_configure_dt(&drv_cfg->gpio_interrupt, GPIO_INT_EDGE_TO_ACTIVE);
+		return;
+	}
+
+	const size_t packet_size = (drv_data->cfg.accel_pwr_mode && drv_data->cfg.aux_pwr_mode)
+					   ? BMA4XX_FIFO_MA_LENGTH + BMA4XX_FIFO_HEADER_LENGTH
+					   : BMA4XX_FIFO_A_LENGTH + BMA4XX_FIFO_HEADER_LENGTH;
+	const size_t min_read_size = sizeof(struct bma4xx_fifo_data) + packet_size;
+	const size_t ideal_read_size = sizeof(struct bma4xx_fifo_data) + fifo_count;
+	uint8_t *buf;
+	uint32_t buf_len;
+
+	if (rtio_sqe_rx_buf(iodev_sqe, min_read_size, ideal_read_size, &buf, &buf_len) != 0) {
+		LOG_ERR("Failed to get buffer");
+		rtio_iodev_sqe_err(iodev_sqe, -ENOMEM);
+		return;
+	}
+	LOG_DBG("Requesting buffer [%u, %u] got %u", (unsigned int)min_read_size,
+		(unsigned int)ideal_read_size, buf_len);
+
+	/* Read FIFO and call back to rtio with rtio_sqe completion */
+	struct bma4xx_fifo_data hdr;
+
+	hdr.header.is_fifo = true;
+	hdr.header.accel_fs = drv_data->cfg.accel_fs_range;
+	hdr.header.timestamp = drv_data->timestamp;
+	hdr.int_status = drv_data->int_status;
+	hdr.accel_odr = drv_data->cfg.accel_odr;
+
+	uint32_t buf_avail = buf_len;
+
+	memcpy(buf, &hdr, sizeof(hdr));
+	buf_avail -= sizeof(hdr);
+
+	uint32_t read_len = MIN(fifo_count, buf_avail);
+	uint32_t pkts = read_len / packet_size;
+
+	read_len = pkts * packet_size;
+	((struct bma4xx_fifo_data *)buf)->fifo_count = read_len;
+
+	__ASSERT_NO_MSG(read_len % packet_size == 0);
+
+	uint8_t *read_buf = buf + sizeof(hdr);
+
+	/* Flush out completions  */
+	struct rtio_cqe *cqe;
+
+	do {
+		cqe = rtio_cqe_consume(r);
+		if (cqe != NULL) {
+			rtio_cqe_release(r, cqe);
+		}
+	} while (cqe != NULL);
+
+	/* Setup new rtio chain to read the fifo data and report then check the
+	 * result
+	 */
+	struct rtio_sqe *write_fifo_addr = rtio_sqe_acquire(r);
+	struct rtio_sqe *read_fifo_data = rtio_sqe_acquire(r);
+	struct rtio_sqe *complete_op = rtio_sqe_acquire(r);
+	const uint8_t reg_addr = BMA4XX_REG_FIFO_DATA;
+
+	rtio_sqe_prep_tiny_write(write_fifo_addr, iodev, RTIO_PRIO_NORM, &reg_addr, 1, NULL);
+	write_fifo_addr->flags = RTIO_SQE_TRANSACTION;
+	rtio_sqe_prep_read(read_fifo_data, iodev, RTIO_PRIO_NORM, read_buf, read_len, iodev_sqe);
+	read_fifo_data->flags = RTIO_SQE_CHAINED;
+
+	if (drv_cfg->bus_type == BMA4XX_BUS_I2C) {
+		read_fifo_data->iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART;
+	}
+
+	rtio_sqe_prep_callback(complete_op, bma4xx_complete_cb, (void *)dev, iodev_sqe);
+
+	rtio_submit(r, 0);
+}
+
+static void bma4xx_int_status_cb(struct rtio *r, const struct rtio_sqe *sqr, void *arg)
+{
+	const struct device *dev = arg;
+	struct bma4xx_data *drv_data = dev->data;
+	const struct bma4xx_config *drv_cfg = dev->config;
+	struct rtio_iodev *iodev = drv_data->iodev;
+	struct rtio_iodev_sqe *streaming_sqe = drv_data->streaming_sqe;
+	struct sensor_read_config *read_config;
+
+	if (streaming_sqe == NULL) {
+		return;
+	}
+
+	read_config = (struct sensor_read_config *)streaming_sqe->sqe.iodev->data;
+	__ASSERT_NO_MSG(read_config != NULL);
+
+	if (!read_config->is_streaming) {
+		return;
+	}
+
+	gpio_pin_interrupt_configure_dt(&drv_cfg->gpio_interrupt, GPIO_INT_DISABLE);
+
+	struct sensor_stream_trigger *fifo_wm_cfg =
+		bma4xx_get_read_config_trigger(read_config, SENSOR_TRIG_FIFO_WATERMARK);
+	bool has_fifo_wm_trig = fifo_wm_cfg != NULL &&
+				FIELD_GET(BMA4XX_BIT_INT_STAT_1_FWM_INT, drv_data->int_status) != 0;
+
+	struct sensor_stream_trigger *fifo_full_cfg =
+		bma4xx_get_read_config_trigger(read_config, SENSOR_TRIG_FIFO_FULL);
+	bool has_fifo_full_trig =
+		fifo_full_cfg != NULL &&
+		FIELD_GET(BMA4XX_BIT_INT_STAT_1_FFULL_INT, drv_data->int_status) != 0;
+
+	if (!has_fifo_wm_trig && !has_fifo_full_trig) {
+		gpio_pin_interrupt_configure_dt(&drv_cfg->gpio_interrupt, GPIO_INT_EDGE_TO_ACTIVE);
+		return;
+	}
+
+	/* Flush completions */
+	struct rtio_cqe *cqe;
+
+	do {
+		cqe = rtio_cqe_consume(r);
+		if (cqe != NULL) {
+			rtio_cqe_release(r, cqe);
+		}
+	} while (cqe != NULL);
+
+	enum sensor_stream_data_opt data_opt;
+
+	if (has_fifo_wm_trig && !has_fifo_full_trig) {
+		/* Only care about fifo threshold */
+		data_opt = fifo_wm_cfg->opt;
+	} else if (!has_fifo_wm_trig && has_fifo_full_trig) {
+		/* Only care about fifo full */
+		data_opt = fifo_full_cfg->opt;
+	} else {
+		/* Both fifo threshold and full */
+		data_opt = MIN(fifo_wm_cfg->opt, fifo_full_cfg->opt);
+	}
+
+	if (data_opt == SENSOR_STREAM_DATA_NOP || data_opt == SENSOR_STREAM_DATA_DROP) {
+		uint8_t *buf;
+		uint32_t buf_len;
+
+		/* Clear streaming_sqe since we're done with the call */
+		drv_data->streaming_sqe = NULL;
+		if (rtio_sqe_rx_buf(streaming_sqe, sizeof(struct bma4xx_fifo_data),
+				    sizeof(struct bma4xx_fifo_data), &buf, &buf_len) != 0) {
+			rtio_iodev_sqe_err(streaming_sqe, -ENOMEM);
+			return;
+		}
+
+		struct bma4xx_fifo_data *data = (struct bma4xx_fifo_data *)buf;
+
+		memset(buf, 0, buf_len);
+		data->header.timestamp = drv_data->timestamp;
+		data->int_status = drv_data->int_status;
+		data->fifo_count = 0;
+		data->header.is_fifo = true;
+		rtio_iodev_sqe_ok(streaming_sqe, 0);
+		gpio_pin_interrupt_configure_dt(&drv_cfg->gpio_interrupt, GPIO_INT_EDGE_TO_ACTIVE);
+		if (data_opt == SENSOR_STREAM_DATA_DROP) {
+			/* Flush the FIFO */
+			struct rtio_sqe *write_signal_path_reset = rtio_sqe_acquire(r);
+			uint8_t write_buffer[] = {
+				FIELD_GET(BMA4XX_REG_ADDRESS_MASK, BMA4XX_REG_CMD),
+				BMA4XX_CMD_FIFO_FLUSH,
+			};
+
+			rtio_sqe_prep_tiny_write(write_signal_path_reset, iodev, RTIO_PRIO_NORM,
+						 write_buffer, ARRAY_SIZE(write_buffer), NULL);
+			rtio_submit(r, 0);
+			ARG_UNUSED(rtio_cqe_consume(r));
+		}
+		return;
+	}
+
+	/* We need the data, read the fifo length */
+	struct rtio_sqe *write_fifo_count_reg = rtio_sqe_acquire(r);
+	struct rtio_sqe *read_fifo_count = rtio_sqe_acquire(r);
+	struct rtio_sqe *check_fifo_count = rtio_sqe_acquire(r);
+	uint8_t reg = BMA4XX_REG_FIFO_LENGTH_0;
+	uint8_t *read_buf = (uint8_t *)&drv_data->fifo_count;
+
+	rtio_sqe_prep_tiny_write(write_fifo_count_reg, iodev, RTIO_PRIO_NORM, &reg, 1, NULL);
+	write_fifo_count_reg->flags = RTIO_SQE_TRANSACTION;
+	rtio_sqe_prep_read(read_fifo_count, iodev, RTIO_PRIO_NORM, read_buf,
+			   BMA4XX_FIFO_DATA_LENGTH, NULL);
+	read_fifo_count->flags = RTIO_SQE_CHAINED;
+
+	if (drv_cfg->bus_type == BMA4XX_BUS_I2C) {
+		read_fifo_count->iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART;
+	}
+
+	rtio_sqe_prep_callback(check_fifo_count, bma4xx_fifo_count_cb, arg, NULL);
+
+	rtio_submit(r, 0);
+}
+
+void bma4xx_fifo_event(const struct device *dev)
+{
+	struct bma4xx_data *drv_data = dev->data;
+	const struct bma4xx_config *drv_cfg = dev->config;
+	struct rtio_iodev *iodev = drv_data->iodev;
+	struct rtio *r = drv_data->r;
+	uint64_t cycles;
+	int rc;
+
+	if (drv_data->streaming_sqe == NULL) {
+		return;
+	}
+
+	rc = sensor_clock_get_cycles(&cycles);
+	if (rc != 0) {
+		LOG_ERR("Failed to get sensor clock cycles");
+		rtio_iodev_sqe_err(drv_data->streaming_sqe, rc);
+		return;
+	}
+
+	drv_data->timestamp = sensor_clock_cycles_to_ns(cycles);
+
+	struct rtio_sqe *write_int_reg = rtio_sqe_acquire(r);
+	struct rtio_sqe *read_int_reg = rtio_sqe_acquire(r);
+	struct rtio_sqe *check_int_status = rtio_sqe_acquire(r);
+	uint8_t reg = BMA4XX_REG_INT_STAT_1;
+
+	rtio_sqe_prep_tiny_write(write_int_reg, iodev, RTIO_PRIO_NORM, &reg, 1, NULL);
+	write_int_reg->flags = RTIO_SQE_TRANSACTION;
+	rtio_sqe_prep_read(read_int_reg, iodev, RTIO_PRIO_NORM, &drv_data->int_status, 1, NULL);
+	read_int_reg->flags = RTIO_SQE_CHAINED;
+
+	if (drv_cfg->bus_type == BMA4XX_BUS_I2C) {
+		read_int_reg->iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART;
+	}
+
+	rtio_sqe_prep_callback(check_int_status, bma4xx_int_status_cb, (void *)dev, NULL);
+	rtio_submit(r, 0);
+}
+
+#endif /* CONFIG_BMA4XX_STREAM */
diff --git a/drivers/sensor/bosch/bme280/bme280.c b/drivers/sensor/bosch/bme280/bme280.c
index 903433b7a70..e96b3c1b46d 100644
--- a/drivers/sensor/bosch/bme280/bme280.c
+++ b/drivers/sensor/bosch/bme280/bme280.c
@@ -33,6 +33,13 @@ LOG_MODULE_REGISTER(BME280, CONFIG_SENSOR_LOG_LEVEL);
  */
 #define BME280_MEASUREMENT_TIMEOUT_MS 150
 
+/* Equation 9.1, with the fractional parts rounded down */
+#define BME280_EXPECTED_SAMPLE_TIME_MS                                                             \
+	1 + BME280_TEMP_SAMPLE_TIME + BME280_PRESS_SAMPLE_TIME + BME280_HUMIDITY_SAMPLE_TIME
+
+BUILD_ASSERT(BME280_EXPECTED_SAMPLE_TIME_MS < BME280_MEASUREMENT_TIMEOUT_MS,
+	     "Expected duration over timeout duration");
+
 struct bme280_config {
 	union bme280_bus bus;
 	const struct bme280_bus_io *bus_io;
@@ -119,6 +126,7 @@ static uint32_t bme280_compensate_humidity(struct bme280_data *data,
 	h = (h - (((((h >> 15) * (h >> 15)) >> 7) *
 		((int32_t)data->dig_h1)) >> 4));
 	h = (h > 419430400 ? 419430400 : h);
+	h = (h < 0 ? 0 : h);
 
 	return (uint32_t)(h >> 12);
 }
@@ -154,6 +162,7 @@ int bme280_sample_fetch_helper(const struct device *dev,
 	struct bme280_data *dev_data = dev->data;
 	uint8_t buf[8];
 	int32_t adc_press, adc_temp, adc_humidity;
+	uint32_t poll_timeout;
 	int size = 6;
 	int ret;
 
@@ -173,9 +182,14 @@ int bme280_sample_fetch_helper(const struct device *dev,
 	if (ret < 0) {
 		return ret;
 	}
+	/* Wait until the expected measurement time elapses */
+	k_sleep(K_MSEC(BME280_EXPECTED_SAMPLE_TIME_MS));
+	poll_timeout = BME280_MEASUREMENT_TIMEOUT_MS - BME280_EXPECTED_SAMPLE_TIME_MS;
+#else
+	poll_timeout = BME280_MEASUREMENT_TIMEOUT_MS;
 #endif
 
-	ret = bme280_wait_until_ready(dev, K_MSEC(BME280_MEASUREMENT_TIMEOUT_MS));
+	ret = bme280_wait_until_ready(dev, K_MSEC(poll_timeout));
 	if (ret < 0) {
 		return ret;
 	}
diff --git a/drivers/sensor/bosch/bme280/bme280.h b/drivers/sensor/bosch/bme280/bme280.h
index 62fbefec38c..e20f3210c2f 100644
--- a/drivers/sensor/bosch/bme280/bme280.h
+++ b/drivers/sensor/bosch/bme280/bme280.h
@@ -81,39 +81,54 @@ extern const struct bme280_bus_io bme280_bus_io_i2c;
 #endif
 
 #if defined CONFIG_BME280_TEMP_OVER_1X
-#define BME280_TEMP_OVER (1 << 5)
+#define BME280_TEMP_OVER        (1 << 5)
+#define BME280_TEMP_SAMPLE_TIME 2
 #elif defined CONFIG_BME280_TEMP_OVER_2X
-#define BME280_TEMP_OVER (2 << 5)
+#define BME280_TEMP_OVER        (2 << 5)
+#define BME280_TEMP_SAMPLE_TIME 4
 #elif defined CONFIG_BME280_TEMP_OVER_4X
-#define BME280_TEMP_OVER (3 << 5)
+#define BME280_TEMP_OVER        (3 << 5)
+#define BME280_TEMP_SAMPLE_TIME 8
 #elif defined CONFIG_BME280_TEMP_OVER_8X
-#define BME280_TEMP_OVER (4 << 5)
+#define BME280_TEMP_OVER        (4 << 5)
+#define BME280_TEMP_SAMPLE_TIME 16
 #elif defined CONFIG_BME280_TEMP_OVER_16X
-#define BME280_TEMP_OVER (5 << 5)
+#define BME280_TEMP_OVER        (5 << 5)
+#define BME280_TEMP_SAMPLE_TIME 32
 #endif
 
 #if defined CONFIG_BME280_PRESS_OVER_1X
-#define BME280_PRESS_OVER (1 << 2)
+#define BME280_PRESS_OVER        (1 << 2)
+#define BME280_PRESS_SAMPLE_TIME 2
 #elif defined CONFIG_BME280_PRESS_OVER_2X
-#define BME280_PRESS_OVER (2 << 2)
+#define BME280_PRESS_OVER        (2 << 2)
+#define BME280_PRESS_SAMPLE_TIME 4
 #elif defined CONFIG_BME280_PRESS_OVER_4X
-#define BME280_PRESS_OVER (3 << 2)
+#define BME280_PRESS_OVER        (3 << 2)
+#define BME280_PRESS_SAMPLE_TIME 8
 #elif defined CONFIG_BME280_PRESS_OVER_8X
-#define BME280_PRESS_OVER (4 << 2)
+#define BME280_PRESS_OVER        (4 << 2)
+#define BME280_PRESS_SAMPLE_TIME 16
 #elif defined CONFIG_BME280_PRESS_OVER_16X
-#define BME280_PRESS_OVER (5 << 2)
+#define BME280_PRESS_OVER        (5 << 2)
+#define BME280_PRESS_SAMPLE_TIME 32
 #endif
 
 #if defined CONFIG_BME280_HUMIDITY_OVER_1X
-#define BME280_HUMIDITY_OVER 1
+#define BME280_HUMIDITY_OVER        1
+#define BME280_HUMIDITY_SAMPLE_TIME 2
 #elif defined CONFIG_BME280_HUMIDITY_OVER_2X
-#define BME280_HUMIDITY_OVER 2
+#define BME280_HUMIDITY_OVER        2
+#define BME280_HUMIDITY_SAMPLE_TIME 4
 #elif defined CONFIG_BME280_HUMIDITY_OVER_4X
-#define BME280_HUMIDITY_OVER 3
+#define BME280_HUMIDITY_OVER        3
+#define BME280_HUMIDITY_SAMPLE_TIME 8
 #elif defined CONFIG_BME280_HUMIDITY_OVER_8X
-#define BME280_HUMIDITY_OVER 4
+#define BME280_HUMIDITY_OVER        4
+#define BME280_HUMIDITY_SAMPLE_TIME 16
 #elif defined CONFIG_BME280_HUMIDITY_OVER_16X
-#define BME280_HUMIDITY_OVER 5
+#define BME280_HUMIDITY_OVER        5
+#define BME280_HUMIDITY_SAMPLE_TIME 32
 #endif
 
 #if defined CONFIG_BME280_STANDBY_05MS
diff --git a/drivers/sensor/bosch/bme280/bme280_async.c b/drivers/sensor/bosch/bme280/bme280_async.c
index 0cf0359b094..1ad6e3d22d2 100644
--- a/drivers/sensor/bosch/bme280/bme280_async.c
+++ b/drivers/sensor/bosch/bme280/bme280_async.c
@@ -7,6 +7,7 @@
 
 #include <zephyr/rtio/work.h>
 #include <zephyr/logging/log.h>
+#include <zephyr/drivers/sensor_clock.h>
 
 #include "bme280.h"
 
@@ -16,6 +17,7 @@ void bme280_submit_sync(struct rtio_iodev_sqe *iodev_sqe)
 {
 	uint32_t min_buf_len = sizeof(struct bme280_encoded_data);
 	int rc;
+	uint64_t cycles;
 	uint8_t *buf;
 	uint32_t buf_len;
 
@@ -31,10 +33,17 @@ void bme280_submit_sync(struct rtio_iodev_sqe *iodev_sqe)
 		return;
 	}
 
+	rc = sensor_clock_get_cycles(&cycles);
+	if (rc != 0) {
+		LOG_ERR("Failed to get sensor clock cycles");
+		rtio_iodev_sqe_err(iodev_sqe, rc);
+		return;
+	}
+
 	struct bme280_encoded_data *edata;
 
 	edata = (struct bme280_encoded_data *)buf;
-	edata->header.timestamp = k_ticks_to_ns_floor64(k_uptime_ticks());
+	edata->header.timestamp = sensor_clock_cycles_to_ns(cycles);
 	edata->has_temp = 0;
 	edata->has_humidity = 0;
 	edata->has_press = 0;
diff --git a/drivers/sensor/bosch/bme680/bme680.c b/drivers/sensor/bosch/bme680/bme680.c
index 88b774e114a..363a8cd8fe4 100644
--- a/drivers/sensor/bosch/bme680/bme680.c
+++ b/drivers/sensor/bosch/bme680/bme680.c
@@ -207,7 +207,9 @@ static uint8_t bme680_calc_gas_wait(uint16_t dur)
 			dur = dur / 4;
 			factor += 1;
 		}
-		durval = dur + (factor * 64);
+		const uint16_t max_duration = dur + (factor * 64);
+
+		durval = CLAMP(max_duration, 0, 0xff);
 	}
 
 	return durval;
diff --git a/drivers/sensor/bosch/bmg160/bmg160.c b/drivers/sensor/bosch/bmg160/bmg160.c
index da16a6080bd..463c3630f61 100644
--- a/drivers/sensor/bosch/bmg160/bmg160.c
+++ b/drivers/sensor/bosch/bmg160/bmg160.c
@@ -5,7 +5,7 @@
  * SPDX-License-Identifier: Apache-2.0
  *
  * Datasheet:
- * http://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMG160-DS000-09.pdf
+ * https://web.archive.org/web/20181111220522/https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMG160-DS000-09.pdf
  */
 
 #define DT_DRV_COMPAT bosch_bmg160
diff --git a/drivers/sensor/bosch/bmi08x/bmi08x_accel.c b/drivers/sensor/bosch/bmi08x/bmi08x_accel.c
index 58f08ead3f7..4642b41ffa0 100644
--- a/drivers/sensor/bosch/bmi08x/bmi08x_accel.c
+++ b/drivers/sensor/bosch/bmi08x/bmi08x_accel.c
@@ -454,16 +454,41 @@ static int bmi08x_temp_channel_get(const struct device *dev, struct sensor_value
 {
 	uint16_t temp_raw = 0U;
 	int32_t temp_micro = 0;
+	int16_t temp_int11 = 0;
 	int ret;
 
 	ret = bmi08x_accel_word_read(dev, BMI08X_REG_TEMP_MSB, &temp_raw);
-	if (ret < 0) {
+	if (!ret) {
+		temp_int11 = (temp_raw & 0xFF) << 3;
+	} else {
+		LOG_ERR("Error reading BMI08X_REG_TEMP_MSB. (err %d)", ret);
 		return ret;
 	}
 
-	/* the scale is 1/2^5/LSB = 31250 micro degrees */
-	temp_micro = BMI08X_TEMP_OFFSET * 1000000ULL + temp_raw * 31250ULL;
+	if (temp_raw == 0x80) {
+		/* temperature invalid */
+		LOG_ERR("BMI08X returned invalid temperature.");
+		return -ENODATA;
+	}
 
+	ret = bmi08x_accel_word_read(dev, BMI08X_REG_TEMP_LSB, &temp_raw);
+	if (!ret) {
+		temp_int11 |= (temp_raw & 0xE0) >> 5;
+	} else {
+		LOG_ERR("Error reading BMI08X_REG_TEMP_LSB. (err %d)", ret);
+		return ret;
+	}
+	/*
+	 * int11 type ranges in [-1024, 1023]
+	 * the 11st bit declares +/-
+	 * if larger than 1023, it is negative.
+	 */
+	if (temp_int11 > 1023) {
+		temp_int11 -= 2048;
+	}
+	/* the value ranges in [-504, 496] */
+	/* the scale is 0.125°C/LSB = 125 micro degrees */
+	temp_micro = temp_int11 * 125 + 23 * 1000000;
 	val->val1 = temp_micro / 1000000ULL;
 	val->val2 = temp_micro % 1000000ULL;
 
diff --git a/drivers/sensor/bosch/bmi08x/bmi08x_accel_trigger.c b/drivers/sensor/bosch/bmi08x/bmi08x_accel_trigger.c
index 223b3df7f74..881bc4850c3 100644
--- a/drivers/sensor/bosch/bmi08x/bmi08x_accel_trigger.c
+++ b/drivers/sensor/bosch/bmi08x/bmi08x_accel_trigger.c
@@ -89,8 +89,8 @@ int bmi08x_trigger_set_acc(const struct device *dev, const struct sensor_trigger
 	struct bmi08x_accel_data *data = dev->data;
 
 	if ((trig->chan == SENSOR_CHAN_ACCEL_XYZ) && (trig->type == SENSOR_TRIG_DATA_READY)) {
-		data->handler_drdy_acc = handler;
 		data->drdy_trig_acc = trig;
+		data->handler_drdy_acc = handler;
 		return 0;
 	}
 
diff --git a/drivers/sensor/bosch/bmi08x/bmi08x_gyro_trigger.c b/drivers/sensor/bosch/bmi08x/bmi08x_gyro_trigger.c
index 8be14312abb..14f67b72997 100644
--- a/drivers/sensor/bosch/bmi08x/bmi08x_gyro_trigger.c
+++ b/drivers/sensor/bosch/bmi08x/bmi08x_gyro_trigger.c
@@ -89,8 +89,8 @@ int bmi08x_trigger_set_gyr(const struct device *dev, const struct sensor_trigger
 	struct bmi08x_gyro_data *data = dev->data;
 
 	if ((trig->chan == SENSOR_CHAN_GYRO_XYZ) && (trig->type == SENSOR_TRIG_DATA_READY)) {
-		data->handler_drdy_gyr = handler;
 		data->drdy_trig_gyr = trig;
+		data->handler_drdy_gyr = handler;
 		return 0;
 	}
 
diff --git a/drivers/sensor/bosch/bmi323/bmi323.c b/drivers/sensor/bosch/bmi323/bmi323.c
index c91fc7ba4f8..7fd49046078 100644
--- a/drivers/sensor/bosch/bmi323/bmi323.c
+++ b/drivers/sensor/bosch/bmi323/bmi323.c
@@ -22,8 +22,8 @@ LOG_MODULE_REGISTER(bosch_bmi323);
 /* Value taken from BMI323 Datasheet section 5.8.1 */
 #define IMU_BOSCH_FEATURE_ENGINE_STARTUP_CONFIG (0x012C)
 
-#define IMU_BOSCH_DIE_TEMP_OFFSET_MICRO_DEG_CELCIUS (23000000LL)
-#define IMU_BOSCH_DIE_TEMP_MICRO_DEG_CELCIUS_LSB    (1953L)
+#define IMU_BOSCH_DIE_TEMP_OFFSET_MICRO_DEG_CELSIUS (23000000LL)
+#define IMU_BOSCH_DIE_TEMP_MICRO_DEG_CELSIUS_LSB    (1953L)
 
 typedef void (*bosch_bmi323_gpio_callback_ptr)(const struct device *dev, struct gpio_callback *cb,
 					       uint32_t pins);
@@ -991,9 +991,9 @@ static int bosch_bmi323_driver_api_fetch_temperature(const struct device *dev)
 		return -ENODATA;
 	}
 
-	micro = bosch_bmi323_value_to_micro(buf, IMU_BOSCH_DIE_TEMP_MICRO_DEG_CELCIUS_LSB);
+	micro = bosch_bmi323_value_to_micro(buf, IMU_BOSCH_DIE_TEMP_MICRO_DEG_CELSIUS_LSB);
 
-	micro += IMU_BOSCH_DIE_TEMP_OFFSET_MICRO_DEG_CELCIUS;
+	micro += IMU_BOSCH_DIE_TEMP_OFFSET_MICRO_DEG_CELSIUS;
 
 	bosch_bmi323_sensor_value_from_micro(&data->temperature, micro);
 
diff --git a/drivers/sensor/bosch/bmp180/bmp180.c b/drivers/sensor/bosch/bmp180/bmp180.c
index b6bb086bf39..c476fb532ac 100644
--- a/drivers/sensor/bosch/bmp180/bmp180.c
+++ b/drivers/sensor/bosch/bmp180/bmp180.c
@@ -278,10 +278,16 @@ static void bmp180_compensate_temp(struct bmp180_data *data)
 {
 	int32_t partial_data1;
 	int32_t partial_data2;
+	int32_t divisor;
 	struct bmp180_cal_data *cal = &data->cal;
 
 	partial_data1 = (data->raw_temp - cal->ac6) * cal->ac5 / 0x8000;
-	partial_data2 = cal->mc * 0x800 / (partial_data1 + cal->md);
+
+	/* Check divisor before division */
+	divisor = partial_data1 + cal->md;
+	__ASSERT(divisor != 0, "divisor is zero: partial_data1=%d, md=%d", partial_data1, cal->md);
+
+	partial_data2 = cal->mc * 0x800 / divisor;
 
 	/* Store for pressure calculation */
 	data->comp_temp = (partial_data1 + partial_data2);
diff --git a/drivers/sensor/bosch/bmp581/bmp581.c b/drivers/sensor/bosch/bmp581/bmp581.c
index 732a92d3649..0927c3395a1 100644
--- a/drivers/sensor/bosch/bmp581/bmp581.c
+++ b/drivers/sensor/bosch/bmp581/bmp581.c
@@ -408,7 +408,7 @@ static int bmp581_channel_get(const struct device *dev, enum sensor_channel chan
 		*val = drv->last_sample.pressure;
 		return BMP5_OK;
 	case SENSOR_CHAN_AMBIENT_TEMP:
-		/* returns temperature in Celcius */
+		/* returns temperature in Celsius */
 		*val = drv->last_sample.temperature;
 		return BMP5_OK;
 	default:
diff --git a/drivers/sensor/current_amp/current_amp.c b/drivers/sensor/current_amp/current_amp.c
index b801d533e46..b85e9b01e0a 100644
--- a/drivers/sensor/current_amp/current_amp.c
+++ b/drivers/sensor/current_amp/current_amp.c
@@ -6,6 +6,8 @@
 
 #define DT_DRV_COMPAT current_sense_amplifier
 
+#include <stdlib.h>
+
 #include <zephyr/drivers/adc.h>
 #include <zephyr/drivers/adc/current_sense_amplifier.h>
 #include <zephyr/drivers/gpio.h>
@@ -53,6 +55,10 @@ static int get(const struct device *dev, enum sensor_channel chan, struct sensor
 		return -ENOTSUP;
 	}
 
+	if (abs(raw_val) < config->noise_threshold) {
+		return sensor_value_from_micro(val, 0);
+	}
+
 	ret = adc_raw_to_millivolts_dt(&config->port, &raw_val);
 	if (ret != 0) {
 		LOG_ERR("raw_to_mv: %d", ret);
@@ -152,7 +158,7 @@ static int current_init(const struct device *dev)
 
 	data->sequence.buffer = &data->raw;
 	data->sequence.buffer_size = sizeof(data->raw);
-	data->sequence.calibrate = true;
+	data->sequence.calibrate = config->enable_calibration;
 
 	return 0;
 }
diff --git a/drivers/sensor/default_rtio_sensor.c b/drivers/sensor/default_rtio_sensor.c
index 123d6b1ff95..511ad0b6f00 100644
--- a/drivers/sensor/default_rtio_sensor.c
+++ b/drivers/sensor/default_rtio_sensor.c
@@ -8,6 +8,7 @@
 #include <errno.h>
 
 #include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/sensor_clock.h>
 #include <zephyr/dsp/types.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/rtio/work.h>
@@ -119,11 +120,21 @@ static void sensor_submit_fallback_sync(struct rtio_iodev_sqe *iodev_sqe)
 	const struct sensor_chan_spec *const channels = cfg->channels;
 	const int num_output_samples = compute_num_samples(channels, cfg->count);
 	uint32_t min_buf_len = compute_min_buf_len(num_output_samples);
-	uint64_t timestamp_ns = k_ticks_to_ns_floor64(k_uptime_ticks());
-	int rc = sensor_sample_fetch(dev);
+	uint64_t cycles;
+	int rc;
+
+	rc = sensor_clock_get_cycles(&cycles);
+	if (rc != 0) {
+		LOG_ERR("Failed to get sensor clock cycles");
+		rtio_iodev_sqe_err(iodev_sqe, rc);
+		return;
+	}
+
+	uint64_t timestamp_ns = sensor_clock_cycles_to_ns(cycles);
 	uint8_t *buf;
 	uint32_t buf_len;
 
+	rc = sensor_sample_fetch(dev);
 	/* Check that the fetch succeeded */
 	if (rc != 0) {
 		LOG_WRN("Failed to fetch samples");
@@ -318,25 +329,44 @@ static int get_frame_count(const uint8_t *buffer, struct sensor_chan_spec channe
 
 	switch (channel.chan_type) {
 	case SENSOR_CHAN_ACCEL_XYZ:
-		channel.chan_type = SENSOR_CHAN_ACCEL_X;
-		break;
 	case SENSOR_CHAN_GYRO_XYZ:
-		channel.chan_type = SENSOR_CHAN_GYRO_X;
-		break;
 	case SENSOR_CHAN_MAGN_XYZ:
-		channel.chan_type = SENSOR_CHAN_MAGN_X;
-		break;
 	case SENSOR_CHAN_POS_DXYZ:
-		channel.chan_type = SENSOR_CHAN_POS_DX;
+		for (size_t i = 0 ; i < header->num_channels; ++i) {
+			/* For 3-axis channels, we need to verify we have each individual axis */
+			struct sensor_chan_spec channel_x = {
+				.chan_type = channel.chan_type - 3,
+				.chan_idx = channel.chan_idx,
+			};
+			struct sensor_chan_spec channel_y = {
+				.chan_type = channel.chan_type - 2,
+				.chan_idx = channel.chan_idx,
+			};
+			struct sensor_chan_spec channel_z = {
+				.chan_type = channel.chan_type - 1,
+				.chan_idx = channel.chan_idx,
+			};
+
+			/** The three axes don't need to be at the beginning of the header, but
+			 * they should be consecutive.
+			 */
+			if (((header->num_channels - i) >= 3) &&
+			    sensor_chan_spec_eq(header->channels[i], channel_x) &&
+			    sensor_chan_spec_eq(header->channels[i + 1], channel_y) &&
+			    sensor_chan_spec_eq(header->channels[i + 2], channel_z)) {
+				*frame_count = 1;
+				return 0;
+			}
+		}
 		break;
 	default:
-		break;
-	}
-	for (size_t i = 0; i < header->num_channels; ++i) {
-		if (sensor_chan_spec_eq(header->channels[i], channel)) {
-			*frame_count = 1;
-			return 0;
+		for (size_t i = 0; i < header->num_channels; ++i) {
+			if (sensor_chan_spec_eq(header->channels[i], channel)) {
+				*frame_count = 1;
+				return 0;
+			}
 		}
+		break;
 	}
 
 	return -ENOTSUP;
@@ -353,21 +383,9 @@ int sensor_natively_supported_channel_size_info(struct sensor_chan_spec channel,
 	}
 
 	switch (channel.chan_type) {
-	case SENSOR_CHAN_ACCEL_X:
-	case SENSOR_CHAN_ACCEL_Y:
-	case SENSOR_CHAN_ACCEL_Z:
 	case SENSOR_CHAN_ACCEL_XYZ:
-	case SENSOR_CHAN_GYRO_X:
-	case SENSOR_CHAN_GYRO_Y:
-	case SENSOR_CHAN_GYRO_Z:
 	case SENSOR_CHAN_GYRO_XYZ:
-	case SENSOR_CHAN_MAGN_X:
-	case SENSOR_CHAN_MAGN_Y:
-	case SENSOR_CHAN_MAGN_Z:
 	case SENSOR_CHAN_MAGN_XYZ:
-	case SENSOR_CHAN_POS_DX:
-	case SENSOR_CHAN_POS_DY:
-	case SENSOR_CHAN_POS_DZ:
 	case SENSOR_CHAN_POS_DXYZ:
 		*base_size = sizeof(struct sensor_three_axis_data);
 		*frame_size = sizeof(struct sensor_three_axis_sample_data);
@@ -480,33 +498,21 @@ static int decode(const uint8_t *buffer, struct sensor_chan_spec chan_spec,
 
 	/* Check for 3d channel mappings */
 	switch (chan_spec.chan_type) {
-	case SENSOR_CHAN_ACCEL_X:
-	case SENSOR_CHAN_ACCEL_Y:
-	case SENSOR_CHAN_ACCEL_Z:
 	case SENSOR_CHAN_ACCEL_XYZ:
 		count = decode_three_axis(header, q, data_out, SENSOR_CHAN_ACCEL_X,
 					  SENSOR_CHAN_ACCEL_Y, SENSOR_CHAN_ACCEL_Z,
 					  chan_spec.chan_idx);
 		break;
-	case SENSOR_CHAN_GYRO_X:
-	case SENSOR_CHAN_GYRO_Y:
-	case SENSOR_CHAN_GYRO_Z:
 	case SENSOR_CHAN_GYRO_XYZ:
 		count = decode_three_axis(header, q, data_out, SENSOR_CHAN_GYRO_X,
 					  SENSOR_CHAN_GYRO_Y, SENSOR_CHAN_GYRO_Z,
 					  chan_spec.chan_idx);
 		break;
-	case SENSOR_CHAN_MAGN_X:
-	case SENSOR_CHAN_MAGN_Y:
-	case SENSOR_CHAN_MAGN_Z:
 	case SENSOR_CHAN_MAGN_XYZ:
 		count = decode_three_axis(header, q, data_out, SENSOR_CHAN_MAGN_X,
 					  SENSOR_CHAN_MAGN_Y, SENSOR_CHAN_MAGN_Z,
 					  chan_spec.chan_idx);
 		break;
-	case SENSOR_CHAN_POS_DX:
-	case SENSOR_CHAN_POS_DY:
-	case SENSOR_CHAN_POS_DZ:
 	case SENSOR_CHAN_POS_DXYZ:
 		count = decode_three_axis(header, q, data_out, SENSOR_CHAN_POS_DX,
 					  SENSOR_CHAN_POS_DY, SENSOR_CHAN_POS_DZ,
diff --git a/drivers/sensor/everlight/CMakeLists.txt b/drivers/sensor/everlight/CMakeLists.txt
new file mode 100644
index 00000000000..5cc686d3928
--- /dev/null
+++ b/drivers/sensor/everlight/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Dipak Shetty <shetty.dipak@gmx.com>
+# SPDX-License-Identifier: Apache-2.0
+
+# zephyr-keep-sorted-start
+add_subdirectory_ifdef(CONFIG_EVERLIGHT_ALS_PT19 als_pt19)
+# zephyr-keep-sorted-stop
diff --git a/drivers/sensor/everlight/Kconfig b/drivers/sensor/everlight/Kconfig
new file mode 100644
index 00000000000..efe1c3df312
--- /dev/null
+++ b/drivers/sensor/everlight/Kconfig
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Dipak Shetty <shetty.dipak@gmx.com>
+# SPDX-License-Identifier: Apache-2.0
+
+# zephyr-keep-sorted-start
+source "drivers/sensor/everlight/als_pt19/Kconfig"
+# zephyr-keep-sorted-stop
diff --git a/drivers/sensor/everlight/als_pt19/CMakeLists.txt b/drivers/sensor/everlight/als_pt19/CMakeLists.txt
new file mode 100644
index 00000000000..f4a1b233265
--- /dev/null
+++ b/drivers/sensor/everlight/als_pt19/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Dipak Shetty <shetty.dipak@gmx.com>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(als_pt19.c)
diff --git a/drivers/sensor/everlight/als_pt19/Kconfig b/drivers/sensor/everlight/als_pt19/Kconfig
new file mode 100644
index 00000000000..ed73606a554
--- /dev/null
+++ b/drivers/sensor/everlight/als_pt19/Kconfig
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Dipak Shetty <shetty.dipak@gmx.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config EVERLIGHT_ALS_PT19
+	bool "Everlight ALS-PT19 Ambient Light Sensor"
+	default y
+	depends on DT_HAS_EVERLIGHT_ALS_PT19_ENABLED
+	select ADC
+	help
+	  Enable support for the Everlight ALS-PT19 ambient light sensor.
diff --git a/drivers/sensor/everlight/als_pt19/als_pt19.c b/drivers/sensor/everlight/als_pt19/als_pt19.c
new file mode 100644
index 00000000000..a346746379b
--- /dev/null
+++ b/drivers/sensor/everlight/als_pt19/als_pt19.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2025 Dipak Shetty <shetty.dipak@gmx.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT everlight_als_pt19
+
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(ALS_PT19, CONFIG_SENSOR_LOG_LEVEL);
+
+struct als_pt19_data {
+	struct adc_sequence sequence;
+	uint16_t raw;
+};
+
+struct als_pt19_config {
+	struct adc_dt_spec adc;
+	uint32_t load_resistor;
+};
+
+static int als_pt19_sample_fetch(const struct device *dev, enum sensor_channel chan)
+{
+	const struct als_pt19_config *config = dev->config;
+	struct als_pt19_data *data = dev->data;
+	int ret;
+
+	if (chan != SENSOR_CHAN_ALL && chan != SENSOR_CHAN_LIGHT) {
+		LOG_ERR("Unsupported sensor channel");
+		return -ENOTSUP;
+	}
+
+	ret = adc_read_dt(&config->adc, &data->sequence);
+	if (ret != 0) {
+		LOG_ERR("adc_read: %d", ret);
+	}
+
+	return ret;
+}
+
+static int als_pt19_channel_get(const struct device *dev, enum sensor_channel chan,
+				struct sensor_value *val)
+{
+	const struct als_pt19_config *config = dev->config;
+	struct als_pt19_data *data = dev->data;
+	int32_t raw_val = data->raw;
+	int ret;
+
+	__ASSERT_NO_MSG(val != NULL);
+
+	if (chan != SENSOR_CHAN_ALL && chan != SENSOR_CHAN_LIGHT) {
+		LOG_ERR("Unsupported sensor channel");
+		return -ENOTSUP;
+	}
+
+	ret = adc_raw_to_millivolts_dt(&config->adc, &raw_val);
+	if (ret != 0) {
+		LOG_ERR("to_mv: %d", ret);
+		return ret;
+	}
+
+	LOG_DBG("Raw voltage: %d mV", raw_val);
+
+	/* Calculate current through the load resistor (in microamps) */
+	const int32_t current_ua = (raw_val * 1000) / config->load_resistor;
+
+	/* Convert current to Lux (200µA = 1000 Lux) */
+	const int32_t lux = (current_ua * 1000) / 200;
+
+	/* Convert to sensor_value format */
+	val->val1 = lux;
+	val->val2 = 0;
+
+	LOG_DBG("ADC: %d/%dmV, Current: %duA, Lux: %d", raw_val, config->adc.vref_mv, current_ua,
+		val->val1);
+
+	return 0;
+}
+
+static DEVICE_API(sensor, als_pt19_driver_api) = {
+	.sample_fetch = als_pt19_sample_fetch,
+	.channel_get = als_pt19_channel_get,
+};
+
+static int als_pt19_init(const struct device *dev)
+{
+	const struct als_pt19_config *config = dev->config;
+	struct als_pt19_data *data = dev->data;
+	int ret;
+
+	if (!adc_is_ready_dt(&config->adc)) {
+		LOG_ERR("ADC is not ready");
+		return -ENODEV;
+	}
+
+	ret = adc_channel_setup_dt(&config->adc);
+	if (ret != 0) {
+		LOG_ERR("ADC channel setup: %d", ret);
+		return ret;
+	}
+
+	ret = adc_sequence_init_dt(&config->adc, &data->sequence);
+	if (ret != 0) {
+		LOG_ERR("ADC sequence: %d", ret);
+		return ret;
+	}
+
+	data->sequence.buffer = &data->raw;
+	data->sequence.buffer_size = sizeof(data->raw);
+
+	return 0;
+}
+
+#define ALS_PT19_INST(inst)                                                                        \
+	static struct als_pt19_data als_pt19_data_##inst;                                          \
+                                                                                                   \
+	static const struct als_pt19_config als_pt19_cfg_##inst = {                                \
+		.adc = ADC_DT_SPEC_INST_GET(inst),                                                 \
+		.load_resistor = DT_INST_PROP(inst, load_resistor)};                               \
+                                                                                                   \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, &als_pt19_init, NULL, &als_pt19_data_##inst,            \
+				     &als_pt19_cfg_##inst, POST_KERNEL,                            \
+				     CONFIG_SENSOR_INIT_PRIORITY, &als_pt19_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(ALS_PT19_INST)
diff --git a/drivers/sensor/explorir_m/explorir_m.c b/drivers/sensor/explorir_m/explorir_m.c
index 67eabb7a510..3a4d8cfbffb 100644
--- a/drivers/sensor/explorir_m/explorir_m.c
+++ b/drivers/sensor/explorir_m/explorir_m.c
@@ -23,12 +23,13 @@ LOG_MODULE_REGISTER(explorir_m_sensor, CONFIG_SENSOR_LOG_LEVEL);
 
 #define EXPLORIR_M_BEGIN_CHAR ' '
 
-#define EXPLORIR_M_SET_FILTER_CHAR     'A'
-#define EXPLORIR_M_GET_FILTER_CHAR     'a'
-#define EXPLORIR_M_MODE_CHAR           'K'
-#define EXPLORIR_M_CO2_FILTERED_CHAR   'Z'
-#define EXPLORIR_M_SCALING_CHAR        '.'
-#define EXPLORIR_M_NOT_RECOGNISED_CHAR '?'
+#define EXPLORIR_M_SET_FILTER_CHAR       'A'
+#define EXPLORIR_M_GET_FILTER_CHAR       'a'
+#define EXPLORIR_M_MODE_CHAR             'K'
+#define EXPLORIR_M_ZERO_POINT_KNOWN_CHAR 'X'
+#define EXPLORIR_M_CO2_FILTERED_CHAR     'Z'
+#define EXPLORIR_M_SCALING_CHAR          '.'
+#define EXPLORIR_M_NOT_RECOGNISED_CHAR   '?'
 
 #define EXPLORIR_M_SEPARATOR_CHAR ' '
 #define EXPLORIR_M_PRE_END_CHAR   '\r'
@@ -39,7 +40,7 @@ LOG_MODULE_REGISTER(explorir_m_sensor, CONFIG_SENSOR_LOG_LEVEL);
 
 #define EXPLORIR_M_BUFFER_LENGTH 16
 
-#define EXPLORIR_M_MAX_RESPONSE_DELAY 200 /* Add margin to the specified 100 in datasheet */
+#define EXPLORIR_M_MAX_RESPONSE_DELAY 300 /* Add margin to the specified 100 in datasheet */
 #define EXPLORIR_M_CO2_VALID_DELAY    1200
 
 struct explorir_m_data {
@@ -130,6 +131,7 @@ static int explorir_m_buffer_process(struct explorir_m_data *data, char type,
 	switch (type) {
 	case EXPLORIR_M_SET_FILTER_CHAR:
 	case EXPLORIR_M_MODE_CHAR:
+	case EXPLORIR_M_ZERO_POINT_KNOWN_CHAR:
 		break;
 
 	case EXPLORIR_M_CO2_FILTERED_CHAR:
@@ -198,18 +200,6 @@ static void explorir_m_uart_terminate(const struct device *uart_dev)
 	uart_poll_out(uart_dev, EXPLORIR_M_END_CHAR);
 }
 
-static int explorir_m_await_receive(struct explorir_m_data *data)
-{
-	int rc = k_sem_take(&data->uart_rx_sem, K_MSEC(EXPLORIR_M_MAX_RESPONSE_DELAY));
-
-	/* Reset semaphore if sensor did not respond within maximum specified response time */
-	if (rc == -EAGAIN) {
-		k_sem_reset(&data->uart_rx_sem);
-	}
-
-	return rc;
-}
-
 static int explorir_m_uart_transceive(const struct device *dev, char type, struct sensor_value *val,
 				      enum explorir_m_uart_set_usage set)
 {
@@ -225,8 +215,6 @@ static int explorir_m_uart_transceive(const struct device *dev, char type, struc
 
 	k_mutex_lock(&data->uart_mutex, K_FOREVER);
 
-	explorir_m_buffer_reset(data);
-
 	uart_poll_out(cfg->uart_dev, type);
 
 	if (set == EXPLORIR_M_SET_VAL_ONE) {
@@ -246,9 +234,12 @@ static int explorir_m_uart_transceive(const struct device *dev, char type, struc
 		uart_poll_out(cfg->uart_dev, buf[i]);
 	}
 
+	explorir_m_buffer_reset(data);
+	k_sem_reset(&data->uart_rx_sem);
+
 	explorir_m_uart_terminate(cfg->uart_dev);
 
-	rc = explorir_m_await_receive(data);
+	rc = k_sem_take(&data->uart_rx_sem, K_MSEC(EXPLORIR_M_MAX_RESPONSE_DELAY));
 	if (rc != 0) {
 		LOG_WRN("%c did not receive a response: %d", type, rc);
 	}
@@ -262,6 +253,52 @@ static int explorir_m_uart_transceive(const struct device *dev, char type, struc
 	return rc;
 }
 
+/*
+ * This calibrate function uses a known gas concentration [ppm] via val->val1 to calibrate.
+ * Calibration should be done when temperature is stabile and gas is fully diffused into the sensor.
+ */
+static int explorir_m_calibrate(const struct device *dev, struct sensor_value *val)
+{
+	struct explorir_m_data *data = dev->data;
+	struct sensor_value original;
+	struct sensor_value tmp;
+	int restore_rc;
+	int rc;
+
+	/* Prevent sensor interaction while using calibration filter value */
+	k_mutex_lock(&data->uart_mutex, K_FOREVER);
+
+	rc = explorir_m_uart_transceive(dev, EXPLORIR_M_GET_FILTER_CHAR, &original,
+					EXPLORIR_M_SET_NONE);
+	if (rc != 0) {
+		goto unlock;
+	}
+
+	/*
+	 * From datasheet section "Zero point setting":
+	 * To improve zeroing accuracy, the recommended digital filter setting is 32.
+	 */
+	tmp.val1 = 32;
+	rc = explorir_m_uart_transceive(dev, EXPLORIR_M_SET_FILTER_CHAR, &tmp,
+					EXPLORIR_M_SET_VAL_ONE);
+	if (rc == 0) {
+		tmp.val1 = val->val1 / data->filtered;
+		rc = explorir_m_uart_transceive(dev, EXPLORIR_M_ZERO_POINT_KNOWN_CHAR, &tmp,
+						EXPLORIR_M_SET_VAL_ONE);
+	}
+
+	restore_rc = explorir_m_uart_transceive(dev, EXPLORIR_M_SET_FILTER_CHAR, &original,
+						EXPLORIR_M_SET_VAL_ONE);
+	if (restore_rc != 0) {
+		LOG_ERR("Could not restore filter value");
+	}
+
+unlock:
+	k_mutex_unlock(&data->uart_mutex);
+
+	return rc != 0 ? rc : restore_rc;
+}
+
 static int explorir_m_attr_get(const struct device *dev, enum sensor_channel chan,
 			       enum sensor_attribute attr, struct sensor_value *val)
 {
@@ -286,6 +323,8 @@ static int explorir_m_attr_set(const struct device *dev, enum sensor_channel cha
 	}
 
 	switch (attr) {
+	case SENSOR_ATTR_CALIBRATION:
+		return explorir_m_calibrate(dev, (struct sensor_value *)val);
 	case SENSOR_ATTR_EXPLORIR_M_FILTER:
 		if (val->val1 < 0 || val->val1 > 255) {
 			return -ERANGE;
diff --git a/drivers/sensor/grow_r502a/grow_r502a.c b/drivers/sensor/grow_r502a/grow_r502a.c
index fd3d05832f7..055a4e9d580 100644
--- a/drivers/sensor/grow_r502a/grow_r502a.c
+++ b/drivers/sensor/grow_r502a/grow_r502a.c
@@ -101,7 +101,14 @@ static int r502a_validate_rx_packet(union r502a_packet *rx_packet)
 		return -EINVAL;
 	}
 
-	cks_start_idx = sys_be16_to_cpu(rx_packet->len) - R502A_CHECKSUM_LEN;
+	const uint16_t packet_len = sys_be16_to_cpu(rx_packet->len);
+
+	if (packet_len < R502A_CHECKSUM_LEN || packet_len > CONFIG_R502A_DATA_PKT_SIZE) {
+		LOG_ERR("Invalid packet length %d", packet_len);
+		return -EINVAL;
+	}
+
+	cks_start_idx = packet_len - R502A_CHECKSUM_LEN;
 
 	recv_cks = sys_get_be16(&rx_packet->data[cks_start_idx]);
 
diff --git a/drivers/sensor/ite/CMakeLists.txt b/drivers/sensor/ite/CMakeLists.txt
index 68883d9bc0c..85642b93ee6 100644
--- a/drivers/sensor/ite/CMakeLists.txt
+++ b/drivers/sensor/ite/CMakeLists.txt
@@ -2,6 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 # zephyr-keep-sorted-start
+add_subdirectory_ifdef(CONFIG_TACH_IT51XXX ite_tach_it51xxx)
 add_subdirectory_ifdef(CONFIG_TACH_IT8XXX2 ite_tach_it8xxx2)
 add_subdirectory_ifdef(CONFIG_VCMP_IT8XXX2 ite_vcmp_it8xxx2)
 # zephyr-keep-sorted-stop
diff --git a/drivers/sensor/ite/Kconfig b/drivers/sensor/ite/Kconfig
index 8d0bf169cea..e03616c5061 100644
--- a/drivers/sensor/ite/Kconfig
+++ b/drivers/sensor/ite/Kconfig
@@ -2,6 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 # zephyr-keep-sorted-start
+source "drivers/sensor/ite/ite_tach_it51xxx/Kconfig"
 source "drivers/sensor/ite/ite_tach_it8xxx2/Kconfig"
 source "drivers/sensor/ite/ite_vcmp_it8xxx2/Kconfig"
 # zephyr-keep-sorted-stop
diff --git a/drivers/sensor/ite/ite_tach_it51xxx/CMakeLists.txt b/drivers/sensor/ite/ite_tach_it51xxx/CMakeLists.txt
new file mode 100644
index 00000000000..6fc9f192390
--- /dev/null
+++ b/drivers/sensor/ite/ite_tach_it51xxx/CMakeLists.txt
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(tach_ite_it51xxx.c)
diff --git a/drivers/sensor/ite/ite_tach_it51xxx/Kconfig b/drivers/sensor/ite/ite_tach_it51xxx/Kconfig
new file mode 100644
index 00000000000..0054c992e25
--- /dev/null
+++ b/drivers/sensor/ite/ite_tach_it51xxx/Kconfig
@@ -0,0 +1,13 @@
+# Copyright (c) 2025 ITE Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+config TACH_IT51XXX
+	bool "ITE it51xxx Tachometer sensor"
+	default y
+	depends on DT_HAS_ITE_IT51XXX_TACH_ENABLED
+	depends on SOC_IT51XXX
+	select PINCTRL
+	help
+	  Enable the ITE it51xxx tachometer sensor,
+	  it51xxx supports three 16-bit tachometer sensor, each sensor has two
+	  input pin, and we need to select one input from them.
diff --git a/drivers/sensor/ite/ite_tach_it51xxx/tach_ite_it51xxx.c b/drivers/sensor/ite/ite_tach_it51xxx/tach_ite_it51xxx.c
new file mode 100644
index 00000000000..94c6d44525f
--- /dev/null
+++ b/drivers/sensor/ite/ite_tach_it51xxx/tach_ite_it51xxx.c
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2025 ITE Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ite_it51xxx_tach
+
+/**
+ * @file
+ * @brief ITE it51xxx tachometer sensor module driver
+ *
+ * This file contains a driver for the tachometer sensor module which contains
+ * three independent counters (T0L/MR, T1L/MR and T2L/MR). The content of the
+ * Tachometer Reading Register is still update based on the sampling counter
+ * that samples the tachometer input (T0A, T0B, T1A, T1B, T2A or T2B pins).
+ * The following is block diagram of this module:
+ *
+ *                                    Sample Rate = TACH_FREQ / 128
+ *                                                   |
+ *                            |        Tachometer 0  |                T0A (GPD6)
+ *                            |             |        | +-----------+   |
+ *                            |       +-----+-----+  | |   _   _   |<--+
+ *                            |------>|  T0L/MR   |<-+-|  | |_| |_ |<--+
+ *                            |       +-----------+    +-----------+   |
+ *                            |       capture pulses                  T0B (GPC6)
+ *                            |       in sample rate
+ *                            |       period
+ *                            |
+ *                            |        Sample Rate = TACH_FREQ / 128
+ *           +-----------+    |                      |
+ * Crystal-->| Prescaler |--->|        Tachometer 1  |                T1A (GPD7)
+ * 32.768k   +-----------+    |             |        | +-----------+   |
+ *                            |       +-----+-----+  | |   _   _   |<--+
+ *                            |------>|  T1L/MR   |<-+-|  | |_| |_ |<--+
+ *                            |       +-----------+    +-----------+   |
+ *                            |       capture pulses                  T1B (GPJ6)
+ *                            |       in sample rate
+ *                            |       period
+ *                            |
+ *                            |        Sample Rate = TACH_FREQ / 128
+ *                            |                      |
+ *                            |        Tachometer 2  |                T2A (GPJ0)
+ *                            |             |        | +-----------+   |
+ *                            |       +-----+-----+  | |   _   _   |<--+
+ *                            |------>|  T2L/MR   |<-+-|  | |_| |_ |<--+
+ *                            |       +-----------+    +-----------+   |
+ *                            |       capture pulses                  T2B (GPJ1)
+ *                            |       in sample rate
+ *                            |       period
+ *                            |
+ *
+ *
+ * Based on the counter value, we can compute the current RPM of external signal
+ * from encoders.
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/dt-bindings/sensor/it51xxx_tach.h>
+#include <errno.h>
+#include <soc.h>
+#include <soc_dt.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(tach_ite_it51xxx, CONFIG_SENSOR_LOG_LEVEL);
+
+#define TACH_FREQ IT51XXX_EC_FREQ
+
+/* 0xC0/0xD0/0xE0: Tach channel 0~2 tachometer speed (2 bytes value) */
+#define REG_TACH_CH       0x00
+/* 0xC6/0xD6/0xE6: Tach channel 0~2 control 1 */
+#define REG_TACH_CH_CTRL1 0x06
+#define TACH_CH_DVS       BIT(1)
+#define TACH_CH_SEL       BIT(0)
+
+struct tach_it51xxx_config {
+	/* Tach channel register base address */
+	uintptr_t base;
+	/* Tachometer alternate configuration */
+	const struct pinctrl_dev_config *pcfg;
+	/* Select input pin to tachometer */
+	int input_pin;
+	/* Number of pulses per round of tachometer's input */
+	int pulses_per_round;
+};
+
+struct tach_it51xxx_data {
+	/* Captured counts of tachometer */
+	uint16_t capture;
+};
+
+static bool tach_ch_is_valid(const struct device *dev, int input_pin)
+{
+	const struct tach_it51xxx_config *const config = dev->config;
+	const uintptr_t base = config->base;
+	uint8_t reg_val;
+
+	if (input_pin > IT51XXX_TACH_INPUT_PIN_B) {
+		LOG_ERR("Tach input pin %d invalid, only support 0(A) or 1(B)", input_pin);
+		return false;
+	}
+
+	reg_val = sys_read8(base + REG_TACH_CH_CTRL1);
+	if (((reg_val & TACH_CH_SEL) == input_pin) && (reg_val & TACH_CH_DVS)) {
+		/* Input pin match register setting and tachometer data valid */
+		return true;
+	}
+
+	return false;
+}
+
+static int tach_it51xxx_sample_fetch(const struct device *dev, enum sensor_channel chan)
+{
+	const struct tach_it51xxx_config *const config = dev->config;
+	const uintptr_t base = config->base;
+	int input_pin = config->input_pin;
+	struct tach_it51xxx_data *const data = dev->data;
+	uint8_t reg_val;
+
+	if ((chan != SENSOR_CHAN_RPM) && (chan != SENSOR_CHAN_ALL)) {
+		return -ENOTSUP;
+	}
+
+	if (tach_ch_is_valid(dev, input_pin)) {
+		/* If tachometer data is valid, then save it */
+		data->capture = sys_read16(base + REG_TACH_CH);
+		/* Clear tachometer data valid status */
+		reg_val = sys_read8(base + REG_TACH_CH_CTRL1);
+		sys_write8(reg_val | TACH_CH_DVS, base + REG_TACH_CH_CTRL1);
+	} else {
+		/* If tachometer data isn't valid, then clear it */
+		data->capture = 0;
+	}
+
+	return 0;
+}
+
+static int tach_it51xxx_channel_get(const struct device *dev, enum sensor_channel chan,
+				    struct sensor_value *val)
+{
+	const struct tach_it51xxx_config *const config = dev->config;
+	int p = config->pulses_per_round;
+	struct tach_it51xxx_data *const data = dev->data;
+
+	__ASSERT(p > 0, "pulses_per_round must be bigger than 0");
+
+	if (chan != SENSOR_CHAN_RPM) {
+		LOG_ERR("Sensor chan %d, only support SENSOR_CHAN_RPM", chan);
+		return -ENOTSUP;
+	}
+
+	/* Transform count unit to RPM */
+	if (data->capture > 0) {
+		/*
+		 * Fan Speed (RPM) = 60 / (1/fs * {TACH_CH_(H & L)} * P)
+		 * - P denotes the numbers of pulses per round
+		 * - {TACH_CH_(H & L)} = 0000h denotes Fan Speed is zero
+		 * - The sampling rate (fs) is TACH_FREQ / 128
+		 */
+		val->val1 = (60 * TACH_FREQ / 128 / p / (data->capture));
+	} else {
+		val->val1 = 0U;
+	}
+
+	val->val2 = 0U;
+
+	return 0;
+}
+
+static int tach_it51xxx_init(const struct device *dev)
+{
+	const struct tach_it51xxx_config *const config = dev->config;
+	const uintptr_t base = config->base;
+	int input_pin = config->input_pin;
+	int status;
+	uint8_t reg_val;
+
+	if (input_pin > IT51XXX_TACH_INPUT_PIN_B) {
+		LOG_ERR("Tach input pin %d invalid, only support 0(A) or 1(B)", input_pin);
+		return -EINVAL;
+	}
+
+	/* Select input pin to tachometer alternate mode */
+	status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+	if (status < 0) {
+		LOG_ERR("Failed to configure TACH pins");
+		return status;
+	}
+
+	reg_val = sys_read8(base + REG_TACH_CH_CTRL1);
+	if (input_pin == IT51XXX_TACH_INPUT_PIN_A) {
+		/* Select TACH_INPUT_PIN_A to tachometer */
+		reg_val &= ~TACH_CH_SEL;
+	} else {
+		/* Select TACH_INPUT_PIN_B to tachometer */
+		reg_val |= TACH_CH_SEL;
+	}
+	/* Clear tachometer data valid status */
+	sys_write8(reg_val | TACH_CH_DVS, base + REG_TACH_CH_CTRL1);
+
+	/* Tachometer sensor already start */
+	return 0;
+}
+
+static DEVICE_API(sensor, tach_it51xxx_driver_api) = {
+	.sample_fetch = tach_it51xxx_sample_fetch,
+	.channel_get = tach_it51xxx_channel_get,
+};
+
+#define TACH_IT51XXX_INIT(inst)                                                                    \
+	PINCTRL_DT_INST_DEFINE(inst);                                                              \
+                                                                                                   \
+	static const struct tach_it51xxx_config tach_it51xxx_cfg_##inst = {                        \
+		.base = DT_INST_REG_ADDR(inst),                                                    \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),                                      \
+		.input_pin = DT_INST_PROP(inst, input_pin),                                        \
+		.pulses_per_round = DT_INST_PROP(inst, pulses_per_round),                          \
+	};                                                                                         \
+                                                                                                   \
+	static struct tach_it51xxx_data tach_it51xxx_data_##inst;                                  \
+                                                                                                   \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, tach_it51xxx_init, NULL, &tach_it51xxx_data_##inst,     \
+				     &tach_it51xxx_cfg_##inst, POST_KERNEL,                        \
+				     CONFIG_SENSOR_INIT_PRIORITY, &tach_it51xxx_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(TACH_IT51XXX_INIT)
diff --git a/drivers/sensor/ite/ite_tach_it8xxx2/tach_ite_it8xxx2.c b/drivers/sensor/ite/ite_tach_it8xxx2/tach_ite_it8xxx2.c
index 3bd4281fdfa..61188e4ae93 100644
--- a/drivers/sensor/ite/ite_tach_it8xxx2/tach_ite_it8xxx2.c
+++ b/drivers/sensor/ite/ite_tach_it8xxx2/tach_ite_it8xxx2.c
@@ -56,7 +56,7 @@ LOG_MODULE_REGISTER(tach_ite_it8xxx2, CONFIG_SENSOR_LOG_LEVEL);
  * NOTE: The PWM output maximum is 324Hz in EC LPM, so if we need fan to work
  *       then don't let EC enter LPM.
  */
-#define TACH_FREQ		EC_FREQ
+#define TACH_FREQ EC_FREQ
 
 struct tach_it8xxx2_config {
 	/* Fan x tachometer LSB reading register */
@@ -110,8 +110,7 @@ static bool tach_ch_is_valid(const struct device *dev, int tach_ch)
 	return valid;
 }
 
-static int tach_it8xxx2_sample_fetch(const struct device *dev,
-				     enum sensor_channel chan)
+static int tach_it8xxx2_sample_fetch(const struct device *dev, enum sensor_channel chan)
 {
 	const struct tach_it8xxx2_config *const config = dev->config;
 	volatile uint8_t *reg_fxtlrr = (uint8_t *)config->reg_fxtlrr;
@@ -127,8 +126,14 @@ static int tach_it8xxx2_sample_fetch(const struct device *dev,
 	if (tach_ch_is_valid(dev, tach_ch)) {
 		/* If channel data of tachometer is valid, then save it */
 		data->capture = ((*reg_fxtmrr) << 8) | (*reg_fxtlrr);
-		/* Clear tachometer data valid status */
-		*reg_tswctlr |= config->dvs_bit;
+
+		if (config->dvs_bit == IT8XXX2_PWM_T0DVS) {
+			/* Only W/C tach 0 data valid status */
+			*reg_tswctlr = (*reg_tswctlr & ~IT8XXX2_PWM_T1DVS);
+		} else {
+			/* Only W/C tach 1 data valid status */
+			*reg_tswctlr = (*reg_tswctlr & ~IT8XXX2_PWM_T0DVS);
+		}
 	} else {
 		/* If channel data of tachometer isn't valid, then clear it */
 		data->capture = 0;
@@ -137,8 +142,7 @@ static int tach_it8xxx2_sample_fetch(const struct device *dev,
 	return 0;
 }
 
-static int tach_it8xxx2_channel_get(const struct device *dev,
-				    enum sensor_channel chan,
+static int tach_it8xxx2_channel_get(const struct device *dev, enum sensor_channel chan,
 				    struct sensor_value *val)
 {
 	const struct tach_it8xxx2_config *const config = dev->config;
@@ -200,13 +204,17 @@ static int tach_it8xxx2_init(const struct device *dev)
 	if (tach_ch == IT8XXX2_TACH_CHANNEL_A) {
 		/* Select IT8XXX2_TACH_CHANNEL_A output to tachometer */
 		*reg_tswctlr &= ~(config->chsel_bit);
-		/* Clear tachometer data valid status */
-		*reg_tswctlr |= config->dvs_bit;
 	} else {
 		/* Select IT8XXX2_TACH_CHANNEL_B output to tachometer */
 		*reg_tswctlr |= config->chsel_bit;
-		/* Clear tachometer data valid status */
-		*reg_tswctlr |= config->dvs_bit;
+	}
+
+	if (config->dvs_bit == IT8XXX2_PWM_T0DVS) {
+		/* Only W/C tach 0 data valid status */
+		*reg_tswctlr = (*reg_tswctlr & ~IT8XXX2_PWM_T1DVS);
+	} else {
+		/* Only W/C tach 1 data valid status */
+		*reg_tswctlr = (*reg_tswctlr & ~IT8XXX2_PWM_T0DVS);
 	}
 
 	/* Tachometer sensor already start */
@@ -218,29 +226,24 @@ static DEVICE_API(sensor, tach_it8xxx2_driver_api) = {
 	.channel_get = tach_it8xxx2_channel_get,
 };
 
-#define TACH_IT8XXX2_INIT(inst)						       \
-	PINCTRL_DT_INST_DEFINE(inst);					       \
-									       \
-	static const struct tach_it8xxx2_config tach_it8xxx2_cfg_##inst = {    \
-		.reg_fxtlrr = DT_INST_REG_ADDR_BY_IDX(inst, 0),		       \
-		.reg_fxtmrr = DT_INST_REG_ADDR_BY_IDX(inst, 1),		       \
-		.reg_tswctlr = DT_INST_REG_ADDR_BY_IDX(inst, 2),	       \
-		.dvs_bit = DT_INST_PROP(inst, dvs_bit),			       \
-		.chsel_bit = DT_INST_PROP(inst, chsel_bit),		       \
-		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),		       \
-		.channel = DT_INST_PROP(inst, channel),			       \
-		.pulses_per_round = DT_INST_PROP(inst, pulses_per_round),      \
-	};								       \
-									       \
-	static struct tach_it8xxx2_data tach_it8xxx2_data_##inst;	       \
-									       \
-	SENSOR_DEVICE_DT_INST_DEFINE(inst,				       \
-			      tach_it8xxx2_init,			       \
-			      NULL,					       \
-			      &tach_it8xxx2_data_##inst,		       \
-			      &tach_it8xxx2_cfg_##inst,			       \
-			      POST_KERNEL,				       \
-			      CONFIG_SENSOR_INIT_PRIORITY,		       \
-			      &tach_it8xxx2_driver_api);
+#define TACH_IT8XXX2_INIT(inst)                                                                    \
+	PINCTRL_DT_INST_DEFINE(inst);                                                              \
+                                                                                                   \
+	static const struct tach_it8xxx2_config tach_it8xxx2_cfg_##inst = {                        \
+		.reg_fxtlrr = DT_INST_REG_ADDR_BY_IDX(inst, 0),                                    \
+		.reg_fxtmrr = DT_INST_REG_ADDR_BY_IDX(inst, 1),                                    \
+		.reg_tswctlr = DT_INST_REG_ADDR_BY_IDX(inst, 2),                                   \
+		.dvs_bit = DT_INST_PROP(inst, dvs_bit),                                            \
+		.chsel_bit = DT_INST_PROP(inst, chsel_bit),                                        \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),                                      \
+		.channel = DT_INST_PROP(inst, channel),                                            \
+		.pulses_per_round = DT_INST_PROP(inst, pulses_per_round),                          \
+	};                                                                                         \
+                                                                                                   \
+	static struct tach_it8xxx2_data tach_it8xxx2_data_##inst;                                  \
+                                                                                                   \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, tach_it8xxx2_init, NULL, &tach_it8xxx2_data_##inst,     \
+				     &tach_it8xxx2_cfg_##inst, POST_KERNEL,                        \
+				     CONFIG_SENSOR_INIT_PRIORITY, &tach_it8xxx2_driver_api);
 
 DT_INST_FOREACH_STATUS_OKAY(TACH_IT8XXX2_INIT)
diff --git a/drivers/sensor/liteon/CMakeLists.txt b/drivers/sensor/liteon/CMakeLists.txt
new file mode 100644
index 00000000000..b3d699fd44f
--- /dev/null
+++ b/drivers/sensor/liteon/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright (c) 2025 Konrad Sikora
+# SPDX-License-Identifier: Apache-2.0
+
+# zephyr-keep-sorted-start
+add_subdirectory_ifdef(CONFIG_LTR329 ltr329)
+add_subdirectory_ifdef(CONFIG_LTR_F216A ltrf216a)
+# zephyr-keep-sorted-stop
diff --git a/drivers/sensor/liteon/Kconfig b/drivers/sensor/liteon/Kconfig
new file mode 100644
index 00000000000..802a8c57e87
--- /dev/null
+++ b/drivers/sensor/liteon/Kconfig
@@ -0,0 +1,7 @@
+# Copyright (c) 2025 Konrad Sikora
+# SPDX-License-Identifier: Apache-2.0
+
+# zephyr-keep-sorted-start
+source "drivers/sensor/liteon/ltr329/Kconfig"
+source "drivers/sensor/liteon/ltrf216a/Kconfig"
+# zephyr-keep-sorted-stop
diff --git a/drivers/sensor/liteon/ltr329/CMakeLists.txt b/drivers/sensor/liteon/ltr329/CMakeLists.txt
new file mode 100644
index 00000000000..e1282068ddd
--- /dev/null
+++ b/drivers/sensor/liteon/ltr329/CMakeLists.txt
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(ltr329.c)
diff --git a/drivers/sensor/liteon/ltr329/Kconfig b/drivers/sensor/liteon/ltr329/Kconfig
new file mode 100644
index 00000000000..3a08aabc590
--- /dev/null
+++ b/drivers/sensor/liteon/ltr329/Kconfig
@@ -0,0 +1,12 @@
+# Lite-On LTR-329 light sensor driver configuration
+
+# Copyright (c) 2025 Konrad Sikora
+# SPDX-License-Identifier: Apache-2.0
+
+config LTR329
+	bool "LiteOn LTR-329 Ambient light sensor support"
+	default y
+	depends on DT_HAS_LITEON_LTR329_ENABLED
+	select I2C
+	help
+	  Enable driver for Lite-On LTR-329 ambient light sensor.
diff --git a/drivers/sensor/liteon/ltr329/ltr329.c b/drivers/sensor/liteon/ltr329/ltr329.c
new file mode 100644
index 00000000000..1ee317af343
--- /dev/null
+++ b/drivers/sensor/liteon/ltr329/ltr329.c
@@ -0,0 +1,348 @@
+/*
+ * Copyright (c) 2025 Konrad Sikora
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT liteon_ltr329
+
+#include <zephyr/device.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/drivers/sensor.h>
+
+LOG_MODULE_REGISTER(LTR329, CONFIG_SENSOR_LOG_LEVEL);
+
+/* Register addresses */
+#define LTR329_ALS_CONTR      0x80
+#define LTR329_MEAS_RATE      0x85
+#define LTR329_PART_ID        0x86
+#define LTR329_MANUFAC_ID     0x87
+#define LTR329_ALS_DATA_CH1_0 0x88
+#define LTR329_ALS_DATA_CH1_1 0x89
+#define LTR329_ALS_DATA_CH0_0 0x8A
+#define LTR329_ALS_DATA_CH0_1 0x8B
+#define LTR329_ALS_STATUS     0x8C
+
+/* Bit masks and shifts for ALS_CONTR register */
+#define LTR329_ALS_CONTR_MODE_MASK      BIT(0)
+#define LTR329_ALS_CONTR_MODE_SHIFT     0
+#define LTR329_ALS_CONTR_SW_RESET_MASK  BIT(1)
+#define LTR329_ALS_CONTR_SW_RESET_SHIFT 1
+#define LTR329_ALS_CONTR_GAIN_MASK      GENMASK(4, 2)
+#define LTR329_ALS_CONTR_GAIN_SHIFT     2
+
+/* Bit masks and shifts for MEAS_RATE register */
+#define LTR329_MEAS_RATE_REPEAT_MASK    GENMASK(2, 0)
+#define LTR329_MEAS_RATE_REPEAT_SHIFT   0
+#define LTR329_MEAS_RATE_INT_TIME_MASK  GENMASK(5, 3)
+#define LTR329_MEAS_RATE_INT_TIME_SHIFT 3
+
+/* Bit masks and shifts for PART_ID register */
+#define LTR329_PART_ID_REVISION_MASK  GENMASK(3, 0)
+#define LTR329_PART_ID_REVISION_SHIFT 0
+#define LTR329_PART_ID_NUMBER_MASK    GENMASK(7, 4)
+#define LTR329_PART_ID_NUMBER_SHIFT   4
+
+/* Bit masks and shifts for MANUFAC_ID register */
+#define LTR329_MANUFAC_ID_IDENTIFICATION_MASK  GENMASK(7, 0)
+#define LTR329_MANUFAC_ID_IDENTIFICATION_SHIFT 0
+
+/* Bit masks and shifts for ALS_STATUS register */
+#define LTR329_ALS_STATUS_DATA_MASK        GENMASK(7, 0)
+#define LTR329_ALS_STATUS_DATA_SHIFT       0
+#define LTR329_ALS_STATUS_DATA_READY_MASK  BIT(2)
+#define LTR329_ALS_STATUS_DATA_READY_SHIFT 2
+#define LTR329_ALS_STATUS_DATA_GAIN_MASK   GENMASK(6, 4)
+#define LTR329_ALS_STATUS_DATA_GAIN_SHIFT  4
+#define LTR329_ALS_STATUS_DATA_VALID_MASK  BIT(7)
+#define LTR329_ALS_STATUS_DATA_VALID_SHIFT 7
+
+/* Expected sensor IDs */
+#define LTR329_PART_ID_VALUE         0xA0
+#define LTR329_MANUFACTURER_ID_VALUE 0x05
+
+/* Timing definitions - refer to LTR-329ALS-01 datasheet */
+#define LTR329_INIT_STARTUP_MS        100
+#define LTR329_WAKEUP_FROM_STANDBY_MS 10
+
+/* Macros to set and get register fields */
+#define LTR329_REG_SET(reg, field, value)				\
+	(((value) << reg##_##field##_SHIFT) & reg##_##field##_MASK)
+#define LTR329_REG_GET(reg, field, value)				\
+	(((value) & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
+
+struct ltr329_config {
+	const struct i2c_dt_spec bus;
+	uint8_t gain;
+	uint8_t integration_time;
+	uint8_t measurement_rate;
+};
+
+struct ltr329_data {
+	uint16_t ch0;
+	uint16_t ch1;
+};
+
+static int ltr329_check_device_id(const struct i2c_dt_spec *bus)
+{
+	uint8_t id;
+	int rc;
+
+	rc = i2c_reg_read_byte_dt(bus, LTR329_PART_ID, &id);
+	if (rc < 0) {
+		LOG_ERR("Failed to read PART_ID");
+		return rc;
+	}
+	if (id != LTR329_PART_ID_VALUE) {
+		LOG_ERR("PART_ID mismatch: expected 0x%02X, got 0x%02X", LTR329_PART_ID_VALUE, id);
+		return -ENODEV;
+	}
+
+	rc = i2c_reg_read_byte_dt(bus, LTR329_MANUFAC_ID, &id);
+	if (rc < 0) {
+		LOG_ERR("Failed to read MANUFAC_ID");
+		return rc;
+	}
+	if (id != LTR329_MANUFACTURER_ID_VALUE) {
+		LOG_ERR("MANUFAC_ID mismatch: expected 0x%02X, got 0x%02X",
+			LTR329_MANUFACTURER_ID_VALUE, id);
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static int ltr329_init_registers(const struct i2c_dt_spec *bus, const struct ltr329_config *cfg)
+{
+	const uint8_t control_reg = LTR329_REG_SET(LTR329_ALS_CONTR, MODE, 1) |
+				    LTR329_REG_SET(LTR329_ALS_CONTR, GAIN, cfg->gain);
+	const uint8_t meas_reg = LTR329_REG_SET(LTR329_MEAS_RATE, REPEAT, cfg->measurement_rate) |
+				 LTR329_REG_SET(LTR329_MEAS_RATE, INT_TIME, cfg->integration_time);
+	uint8_t buffer;
+	int rc;
+
+	rc = i2c_reg_write_byte_dt(bus, LTR329_ALS_CONTR, control_reg);
+	if (rc < 0) {
+		LOG_ERR("Failed to set ALS_CONTR register");
+		return rc;
+	}
+
+	rc = i2c_reg_write_byte_dt(bus, LTR329_MEAS_RATE, meas_reg);
+	if (rc < 0) {
+		LOG_ERR("Failed to set MEAS_RATE register");
+		return rc;
+	}
+
+	/* Read back the MEAS_RATE register to verify the settings */
+	rc = i2c_reg_read_byte_dt(bus, LTR329_MEAS_RATE, &buffer);
+	if (rc < 0) {
+		LOG_ERR("Failed to read back MEAS_RATE register");
+		return rc;
+	}
+	if (LTR329_REG_GET(LTR329_MEAS_RATE, REPEAT, buffer) != cfg->measurement_rate) {
+		LOG_ERR("Measurement rate mismatch: expected %u, got %u", cfg->measurement_rate,
+			(uint8_t)LTR329_REG_GET(LTR329_MEAS_RATE, REPEAT, buffer));
+		return -ENODEV;
+	}
+	if (LTR329_REG_GET(LTR329_MEAS_RATE, INT_TIME, buffer) != cfg->integration_time) {
+		LOG_ERR("Integration time mismatch: expected %u, got %u", cfg->integration_time,
+			(uint8_t)LTR329_REG_GET(LTR329_MEAS_RATE, INT_TIME, buffer));
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+static int ltr329_init(const struct device *dev)
+{
+	const struct ltr329_config *cfg = dev->config;
+	int rc;
+
+	if (!i2c_is_ready_dt(&cfg->bus)) {
+		LOG_ERR("I2C bus not ready");
+		return -ENODEV;
+	}
+
+	/* Wait for sensor startup */
+	k_sleep(K_MSEC(LTR329_INIT_STARTUP_MS));
+
+	rc = ltr329_check_device_id(&cfg->bus);
+	if (rc < 0) {
+		return rc;
+	}
+
+	/* Init register to enable sensor to active mode */
+	rc = ltr329_init_registers(&cfg->bus, cfg);
+	if (rc < 0) {
+		return rc;
+	}
+
+	return 0;
+}
+
+static int ltr329_check_data_ready(const struct i2c_dt_spec *bus)
+{
+	uint8_t status;
+	int rc;
+
+	rc = i2c_reg_read_byte_dt(bus, LTR329_ALS_STATUS, &status);
+	if (rc < 0) {
+		LOG_ERR("Failed to read ALS_STATUS register");
+		return rc;
+	}
+
+	if (!LTR329_REG_GET(LTR329_ALS_STATUS, DATA_READY, status)) {
+		LOG_WRN("Data not ready");
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
+static int ltr329_read_als_data(const struct i2c_dt_spec *bus, struct ltr329_data *data)
+{
+	uint8_t reg = LTR329_ALS_DATA_CH1_0;
+	uint8_t buff[4];
+	int rc;
+
+	rc = i2c_write_read_dt(bus, &reg, sizeof(reg), buff, sizeof(buff));
+	if (rc < 0) {
+		LOG_ERR("Failed to read ALS data registers");
+		return rc;
+	}
+
+	data->ch1 = sys_get_le16(buff);
+	data->ch0 = sys_get_le16(buff + 2);
+
+	return 0;
+}
+
+static int ltr329_sample_fetch(const struct device *dev, enum sensor_channel chan)
+{
+	const struct ltr329_config *cfg = dev->config;
+	struct ltr329_data *data = dev->data;
+	int rc;
+
+	if ((chan != SENSOR_CHAN_ALL) && (chan != SENSOR_CHAN_LIGHT)) {
+		return -ENOTSUP;
+	}
+
+	rc = ltr329_check_data_ready(&cfg->bus);
+	if (rc < 0) {
+		return rc;
+	}
+
+	rc = ltr329_read_als_data(&cfg->bus, data);
+	if (rc < 0) {
+		return rc;
+	}
+
+	return 0;
+}
+
+static int ltr329_get_mapped_gain(const uint8_t reg_val, uint8_t *const output)
+{
+	/* Map the register value to the gain used in the lux calculation
+	 * Indices 4 and 5 are invalid.
+	 */
+	static const uint8_t gain_lux_calc[] = {1, 2, 4, 8, 0, 0, 48, 96};
+
+	if (reg_val < ARRAY_SIZE(gain_lux_calc)) {
+		*output = gain_lux_calc[reg_val];
+		/* 0 is not a valid value */
+		return (*output == 0) ? -EINVAL : 0;
+	}
+
+	return -EINVAL;
+}
+
+static int ltr329_get_mapped_int_time(const uint8_t reg_val, uint8_t *const output)
+{
+	/* Map the register value to the integration time used in the lux calculation */
+	static const uint8_t int_time_lux_calc[] = {10, 5, 20, 40, 15, 25, 30, 35};
+
+	if (reg_val < ARRAY_SIZE(int_time_lux_calc)) {
+		*output = int_time_lux_calc[reg_val];
+		return 0;
+	}
+
+	*output = 0;
+	return -EINVAL;
+}
+
+static int ltr329_channel_get(const struct device *dev, enum sensor_channel chan,
+			      struct sensor_value *val)
+{
+	const struct ltr329_data *data = dev->data;
+	const struct ltr329_config *cfg = dev->config;
+	uint8_t gain_value;
+	uint8_t integration_time_value;
+
+	if (chan != SENSOR_CHAN_LIGHT) {
+		return -ENOTSUP;
+	}
+
+	if (ltr329_get_mapped_gain(cfg->gain, &gain_value) != 0) {
+		LOG_ERR("Invalid gain configuration");
+		return -EINVAL;
+	}
+
+	if (ltr329_get_mapped_int_time(cfg->integration_time, &integration_time_value) != 0) {
+		LOG_ERR("Invalid integration time configuration");
+		return -EINVAL;
+	}
+
+	if ((data->ch0 == 0) && (data->ch1 == 0)) {
+		LOG_WRN("Both channels are zero; cannot compute ratio");
+		return -EINVAL;
+	}
+
+	/* Calculate lux value according to the appendix A of the datasheet. */
+	uint64_t lux;
+	/* The calculation is scaled by 1000000 to avoid floating point. */
+	uint64_t scaled_ratio = (data->ch1 * UINT64_C(1000000)) / (uint64_t)(data->ch0 + data->ch1);
+
+	if (scaled_ratio < UINT64_C(450000)) {
+		lux = (UINT64_C(1774300) * data->ch0 + UINT64_C(1105900) * data->ch1);
+	} else if (scaled_ratio < UINT64_C(640000)) {
+		lux = (UINT64_C(4278500) * data->ch0 - UINT64_C(1954800) * data->ch1);
+	} else if (scaled_ratio < UINT64_C(850000)) {
+		lux = (UINT64_C(592600) * data->ch0 + UINT64_C(118500) * data->ch1);
+	} else {
+		LOG_WRN("Invalid ratio: %llu", scaled_ratio);
+		return -EINVAL;
+	}
+
+	/* Adjust lux value for gain and integration time.
+	 * Multiply by 10 before to compensate for the integration time scaling.
+	 */
+	lux = (lux * 10) / (gain_value * integration_time_value);
+
+	/* Get the integer and fractional parts from fixed point value */
+	val->val1 = (int32_t)(lux / UINT64_C(1000000));
+	val->val2 = (int32_t)(lux % UINT64_C(1000000));
+
+	return 0;
+}
+
+static DEVICE_API(sensor, ltr329_driver_api) = {
+	.sample_fetch = ltr329_sample_fetch,
+	.channel_get = ltr329_channel_get,
+};
+
+#define DEFINE_LTR329(_num)									\
+	static struct ltr329_data ltr329_data_##_num;						\
+	static const struct ltr329_config ltr329_config_##_num = {				\
+		.bus = I2C_DT_SPEC_INST_GET(_num),						\
+		.gain = DT_INST_PROP(_num, gain),						\
+		.integration_time = DT_INST_PROP(_num, integration_time),			\
+		.measurement_rate = DT_INST_PROP(_num, measurement_rate),			\
+	};											\
+	SENSOR_DEVICE_DT_INST_DEFINE(_num, ltr329_init, NULL, &ltr329_data_##_num,		\
+				     &ltr329_config_##_num, POST_KERNEL,			\
+				     CONFIG_SENSOR_INIT_PRIORITY, &ltr329_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(DEFINE_LTR329)
diff --git a/drivers/sensor/ltrf216a/CMakeLists.txt b/drivers/sensor/liteon/ltrf216a/CMakeLists.txt
similarity index 100%
rename from drivers/sensor/ltrf216a/CMakeLists.txt
rename to drivers/sensor/liteon/ltrf216a/CMakeLists.txt
diff --git a/drivers/sensor/liteon/ltrf216a/Kconfig b/drivers/sensor/liteon/ltrf216a/Kconfig
new file mode 100644
index 00000000000..cac1486e8b9
--- /dev/null
+++ b/drivers/sensor/liteon/ltrf216a/Kconfig
@@ -0,0 +1,12 @@
+# LTR-F216A light sensor configuration options
+
+# Copyright (c) 2023 Tridonic
+# SPDX-License-Identifier: Apache-2.0
+
+config LTR_F216A
+	bool "LiteOn LTR-F216A Light Sensor"
+	default y
+	depends on DT_HAS_LITEON_LTRF216A_ENABLED
+	select I2C
+	help
+	  Enable driver for LiteOn LTR-F216A light sensors.
diff --git a/drivers/sensor/ltrf216a/ltrf216a.c b/drivers/sensor/liteon/ltrf216a/ltrf216a.c
similarity index 99%
rename from drivers/sensor/ltrf216a/ltrf216a.c
rename to drivers/sensor/liteon/ltrf216a/ltrf216a.c
index 60a860828e8..aaa2b849937 100644
--- a/drivers/sensor/ltrf216a/ltrf216a.c
+++ b/drivers/sensor/liteon/ltrf216a/ltrf216a.c
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#define DT_DRV_COMPAT ltr_f216a
+#define DT_DRV_COMPAT liteon_ltrf216a
 
 #include <zephyr/device.h>
 #include <zephyr/drivers/i2c.h>
diff --git a/drivers/sensor/ltrf216a/Kconfig b/drivers/sensor/ltrf216a/Kconfig
deleted file mode 100644
index fa9cfe9fdbf..00000000000
--- a/drivers/sensor/ltrf216a/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-# LTR-F216A light sensor configuration options
-
-# Copyright (c) 2023 Tridonic
-# SPDX-License-Identifier: Apache-2.0
-
-config LTR_F216A
-	bool "LiteOn LTR-F216A Light Sensor"
-	default y
-	depends on DT_HAS_LTR_F216A_ENABLED
-	select I2C
-	help
-	  Enable driver for LiteOn LTR-F216A light sensors.
diff --git a/drivers/sensor/maxim/ds3231/ds3231.c b/drivers/sensor/maxim/ds3231/ds3231.c
index d534285e314..360d234f141 100644
--- a/drivers/sensor/maxim/ds3231/ds3231.c
+++ b/drivers/sensor/maxim/ds3231/ds3231.c
@@ -37,6 +37,16 @@ struct sensor_ds3231_conf {
 	const struct device *mfd;
 };
 
+static inline void sensor_ds3231_temp_from_raw(struct sensor_ds3231_data *data,
+					       struct sensor_value *val)
+{
+	const uint16_t raw_temp = data->raw_temp;
+	uint8_t frac = raw_temp & 3;
+
+	val->val1 = (int8_t)(raw_temp & GENMASK(8, 2)) >> 2;
+	val->val2 = (frac * 25) * pow(10, 4);
+}
+
 int sensor_ds3231_read_temp(const struct device *dev, uint16_t *raw_temp)
 {
 	const struct sensor_ds3231_conf *config = dev->config;
@@ -74,13 +84,7 @@ static int sensor_ds3231_channel_get(const struct device *dev, enum sensor_chann
 
 	switch (chan) {
 	case SENSOR_CHAN_AMBIENT_TEMP:
-		const uint16_t raw_temp = data->raw_temp;
-
-		val->val1 = (int8_t)(raw_temp & GENMASK(8, 2)) >> 2;
-
-		uint8_t frac = raw_temp & 3;
-
-		val->val2 = (frac * 25) * pow(10, 4);
+		sensor_ds3231_temp_from_raw(data, val);
 		break;
 	default:
 		return -ENOTSUP;
diff --git a/drivers/sensor/maxim/max31855/max31855.c b/drivers/sensor/maxim/max31855/max31855.c
index f594c18b1e3..2da53d035cb 100644
--- a/drivers/sensor/maxim/max31855/max31855.c
+++ b/drivers/sensor/maxim/max31855/max31855.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2020 Christian Hirsch
+ * Copyright (c) 2025 Petr Vilím
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -72,7 +73,7 @@ static int max31855_channel_get(const struct device *dev, enum sensor_channel ch
 		temp = (temp >> THERMOCOUPLE_TEMPERATURE_POS) & 0x3fff;
 
 		/* if sign bit is set, make value negative */
-		if (temp & BIT(14)) {
+		if (temp & BIT(13)) {
 			temp |= THERMOCOUPLE_SIGN_BITS;
 		}
 
@@ -86,7 +87,7 @@ static int max31855_channel_get(const struct device *dev, enum sensor_channel ch
 		temp = (temp >> INTERNAL_TEMPERATURE_POS) & 0xfff;
 
 		/* if sign bit is set, make value negative */
-		if (temp & BIT(12)) {
+		if (temp & BIT(11)) {
 			temp |= INTERNAL_SIGN_BITS;
 		}
 
diff --git a/drivers/sensor/meas/ms5837/Kconfig b/drivers/sensor/meas/ms5837/Kconfig
index d758d5970a0..96443c8ff12 100644
--- a/drivers/sensor/meas/ms5837/Kconfig
+++ b/drivers/sensor/meas/ms5837/Kconfig
@@ -1,12 +1,13 @@
 # MS5837 pressure sensor configuration options
 
 # Copyright (c) 2018 Jan Van Winkel <jan.van_winkel@dxplore.eu>
+# Copyright (c) 2025 Ivan Wagner <ivan.wagner@tecinvent.ch>
 # SPDX-License-Identifier: Apache-2.0
 
 config MS5837
 	bool "MS5837 pressure and temperature sensor"
 	default y
-	depends on DT_HAS_MEAS_MS5837_ENABLED
+	depends on DT_HAS_MEAS_MS5837_02BA_ENABLED || DT_HAS_MEAS_MS5837_30BA_ENABLED
 	select I2C
 	help
 	  Enable driver for MS5837 pressure and temperature sensor.
diff --git a/drivers/sensor/meas/ms5837/ms5837.c b/drivers/sensor/meas/ms5837/ms5837.c
index fb83ec4c802..08375da6e69 100644
--- a/drivers/sensor/meas/ms5837/ms5837.c
+++ b/drivers/sensor/meas/ms5837/ms5837.c
@@ -1,12 +1,11 @@
 /* Driver for MS5837 pressure sensor
  *
  * Copyright (c) 2018 Jan Van Winkel <jan.van_winkel@dxplore.eu>
+ * Copyright (c) 2025 Ivan Wagner <ivan.wagner@tecinvent.ch>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#define DT_DRV_COMPAT meas_ms5837
-
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
 #include <zephyr/sys/byteorder.h>
@@ -45,6 +44,8 @@ static int ms5837_get_measurement(const struct device *dev, uint32_t *val,
 	return 0;
 }
 
+#if DT_HAS_COMPAT_STATUS_OKAY(meas_ms5837_30ba)
+
 static void ms5837_compensate_30(const struct device *dev,
 				 const int32_t adc_temperature,
 				 const int32_t adc_pressure)
@@ -94,10 +95,14 @@ static void ms5837_compensate_30(const struct device *dev,
 	SENS -= SENSi;
 
 	data->temperature -= Ti;
-	data->pressure =
-	    (((SENS * adc_pressure) / (1ll << 21)) - OFF) / (1ll << 13);
+	/* Result is in mbar * 10 but store result as mbar * 100 same as 02 sensor variant */
+	data->pressure = ((((SENS * adc_pressure) / (1ll << 21)) - OFF) / (1ll << 13)) * 10;
 }
 
+#endif
+
+#if DT_HAS_COMPAT_STATUS_OKAY(meas_ms5837_02ba)
+
 /*
  * First and second order pressure and temperature calculations, as per the flowchart in the
  * MS5837-02B datasheet. (see "Pressure and Temperature Calculation", pages 6 and 7, REV a8 12/2019)
@@ -135,12 +140,16 @@ static void ms5837_compensate_02(const struct device *dev,
 	SENS -= SENSi;
 
 	data->temperature -= Ti;
+	/* Result is in mbar * 100 */
 	data->pressure = (((SENS * adc_pressure) / (1ll << 21)) - OFF) / (1ll << 15);
 }
 
+#endif
+
 static int ms5837_sample_fetch(const struct device *dev,
 			       enum sensor_channel channel)
 {
+	const struct ms5837_config *cfg = dev->config;
 	struct ms5837_data *data = dev->data;
 	int err;
 	uint32_t adc_pressure;
@@ -161,7 +170,7 @@ static int ms5837_sample_fetch(const struct device *dev,
 		return err;
 	}
 
-	data->comp_func(dev, adc_temperature, adc_pressure);
+	cfg->comp_func(dev, adc_temperature, adc_pressure);
 
 	return 0;
 }
@@ -348,34 +357,25 @@ static int ms5837_init(const struct device *dev)
 		return err;
 	}
 
-	const int type_id = (data->factory >> 5) & 0x7f;
-
-	switch (type_id) {
-	case  MS5837_02BA01:
-	case MS5837_02BA21:
-		data->comp_func = ms5837_compensate_02;
-		break;
-	case MS5837_30BA26:
-		data->comp_func = ms5837_compensate_30;
-		break;
-	default:
-		LOG_WRN(" unrecognized type: '%2x', defaulting to MS5837-30", type_id);
-		data->comp_func = ms5837_compensate_30;
-		break;
-	}
-
 	return 0;
 }
 
-#define MS5837_DEFINE(inst)								\
-	static struct ms5837_data ms5837_data_##inst;					\
-											\
-	static const struct ms5837_config ms5837_config_##inst = {			\
-		.i2c = I2C_DT_SPEC_INST_GET(inst),					\
-	};										\
-											\
-	SENSOR_DEVICE_DT_INST_DEFINE(inst, ms5837_init, NULL,				\
-			      &ms5837_data_##inst, &ms5837_config_##inst, POST_KERNEL,	\
-			      CONFIG_SENSOR_INIT_PRIORITY, &ms5837_api_funcs);		\
-
-DT_INST_FOREACH_STATUS_OKAY(MS5837_DEFINE)
+#define MS5837_DEFINE(inst, type)                                                                  \
+	static struct ms5837_data ms5837_##type##_data_##inst;                                     \
+                                                                                                   \
+	static const struct ms5837_config ms5837_##type##_config_##inst = {                        \
+		.i2c = I2C_DT_SPEC_INST_GET(inst),                                                 \
+		.comp_func = ms5837_compensate_##type                                              \
+	};                                                                                         \
+                                                                                                   \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, ms5837_init, NULL, &ms5837_##type##_data_##inst,        \
+				     &ms5837_##type##_config_##inst, POST_KERNEL,                  \
+				     CONFIG_SENSOR_INIT_PRIORITY, &ms5837_api_funcs);
+
+#undef DT_DRV_COMPAT
+#define DT_DRV_COMPAT meas_ms5837_02ba
+DT_INST_FOREACH_STATUS_OKAY_VARGS(MS5837_DEFINE, 02)
+
+#undef DT_DRV_COMPAT
+#define DT_DRV_COMPAT meas_ms5837_30ba
+DT_INST_FOREACH_STATUS_OKAY_VARGS(MS5837_DEFINE, 30)
diff --git a/drivers/sensor/meas/ms5837/ms5837.h b/drivers/sensor/meas/ms5837/ms5837.h
index e4f8fc650bb..5917e709022 100644
--- a/drivers/sensor/meas/ms5837/ms5837.h
+++ b/drivers/sensor/meas/ms5837/ms5837.h
@@ -44,12 +44,6 @@
 #define MS5837_ADC_READ_DELAY_4086 10
 #define MS5837_ADC_READ_DELAY_8129 20
 
-enum ms5837_type {
-	MS5837_02BA01 = 0x00,
-	MS5837_02BA21 = 0x15,
-	MS5837_30BA26 = 0x1A
-};
-
 typedef void (*ms5837_compensate_func)(const struct device *dev,
 				       const int32_t adc_temperature,
 				       const int32_t adc_pressure);
@@ -76,11 +70,11 @@ struct ms5837_data {
 	uint8_t presure_conv_delay;
 	uint8_t temperature_conv_delay;
 
-	ms5837_compensate_func comp_func;
 };
 
 struct ms5837_config {
 	struct i2c_dt_spec i2c;
+	ms5837_compensate_func comp_func;
 };
 
 #endif /* __SENSOR_MS5837_H__ */
diff --git a/drivers/sensor/melexis/CMakeLists.txt b/drivers/sensor/melexis/CMakeLists.txt
new file mode 100644
index 00000000000..64debd75720
--- /dev/null
+++ b/drivers/sensor/melexis/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Florian Weber <Florian.Weber@live.de>
+# SPDX-License-Identifier: Apache-2.0
+
+# zephyr-keep-sorted-start
+add_subdirectory_ifdef(CONFIG_MLX90394 mlx90394)
+# zephyr-keep-sorted-stop
diff --git a/drivers/sensor/melexis/Kconfig b/drivers/sensor/melexis/Kconfig
new file mode 100644
index 00000000000..aca3baa8b05
--- /dev/null
+++ b/drivers/sensor/melexis/Kconfig
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Florian Weber <Florian.Weber@live.de>
+# SPDX-License-Identifier: Apache-2.0
+
+# zephyr-keep-sorted-start
+source "drivers/sensor/melexis/mlx90394/Kconfig"
+# zephyr-keep-sorted-stop
diff --git a/drivers/sensor/melexis/mlx90394/CMakeLists.txt b/drivers/sensor/melexis/mlx90394/CMakeLists.txt
new file mode 100644
index 00000000000..800212bb85c
--- /dev/null
+++ b/drivers/sensor/melexis/mlx90394/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright (c) Florian Weber <Florian.weber@live.de>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(mlx90394.c)
+zephyr_library_sources_ifdef(CONFIG_SENSOR_ASYNC_API mlx90394_async.c mlx90394_decoder.c)
diff --git a/drivers/sensor/melexis/mlx90394/Kconfig b/drivers/sensor/melexis/mlx90394/Kconfig
new file mode 100644
index 00000000000..2fbb670c6e1
--- /dev/null
+++ b/drivers/sensor/melexis/mlx90394/Kconfig
@@ -0,0 +1,11 @@
+# Copyright (c) 2024 Florian Weber <Florian.Weber@live.de>
+# SPDX-License-Identifier: Apache-2.0
+
+
+config MLX90394
+	bool "MLX90394 Magnetometer"
+	default y
+	depends on DT_HAS_MELEXIS_MLX90394_ENABLED
+	select I2C
+	help
+	  Enable driver for MLX90394 magnetometer.
diff --git a/drivers/sensor/melexis/mlx90394/mlx90394.c b/drivers/sensor/melexis/mlx90394/mlx90394.c
new file mode 100644
index 00000000000..84e53ac7379
--- /dev/null
+++ b/drivers/sensor/melexis/mlx90394/mlx90394.c
@@ -0,0 +1,656 @@
+/*
+ * Copyright (c) 2024 Florian Weber <Florian.Weber@live.de>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT melexis_mlx90394
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/sensor_data_types.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/sensor/mlx90394.h>
+
+#include "mlx90394.h"
+#include "mlx90394_reg.h"
+
+LOG_MODULE_REGISTER(MLX90394, CONFIG_SENSOR_LOG_LEVEL);
+
+/*
+ * conversion time of one single axis for different filter orders if osr is enabled the value has
+ * to be doubled
+ */
+static const int32_t MLX90394_CONVERSION_TIME_US_AXIS[] = {111, 170,  270,  490,
+							   910, 1770, 3470, 6890};
+
+/* conversion time per axis dependent of filter order */
+
+/*
+ * DSP Time per measurement first index:temperature sensor count ( 0..1 ) second index:
+ * magnetic axis count (0..3) in us
+ */
+static const int32_t MLX90394_DSP_TIME_US[2][4] = {{0, 27, 50, 73}, {20, 63, 86, 110}};
+
+static void mlx90394_update_measurement_Time_us(struct mlx90394_data *data)
+{
+	int32_t en_x = FIELD_GET(MLX90394_CTRL1_X_EN, data->ctrl_reg_values.ctrl1);
+	int32_t en_y = FIELD_GET(MLX90394_CTRL1_Y_EN, data->ctrl_reg_values.ctrl1);
+	int32_t en_z = FIELD_GET(MLX90394_CTRL1_Z_EN, data->ctrl_reg_values.ctrl1);
+	int32_t en_temp = FIELD_GET(MLX90394_CTRL4_T_EN, data->ctrl_reg_values.ctrl4);
+	int32_t filter_hall_xy =
+		FIELD_GET(MLX90394_CTRL3_DIG_FILT_HALL_XY, data->ctrl_reg_values.ctrl3);
+	int32_t filter_hall_z =
+		FIELD_GET(MLX90394_CTRL4_DIG_FILT_HALL_Z, data->ctrl_reg_values.ctrl4);
+	int32_t filter_temp = FIELD_GET(MLX90394_CTRL3_DIG_FILT_TEMP, data->ctrl_reg_values.ctrl3);
+	int32_t osr_temp = FIELD_GET(MLX90394_CTRL3_OSR_TEMP, data->ctrl_reg_values.ctrl3);
+	int32_t osr_hall = FIELD_GET(MLX90394_CTRL3_OSR_HALL, data->ctrl_reg_values.ctrl3);
+
+	int32_t conversion_time_us =
+		(osr_hall + 1) * ((en_x + en_y) * MLX90394_CONVERSION_TIME_US_AXIS[filter_hall_xy] +
+				  en_z * MLX90394_CONVERSION_TIME_US_AXIS[filter_hall_z]) +
+		(osr_temp + 1) * en_temp * MLX90394_CONVERSION_TIME_US_AXIS[filter_temp];
+	int32_t dsp_time_us = MLX90394_DSP_TIME_US[en_temp][en_x + en_y + en_z];
+
+	/*
+	 * adding 5% tolerance from datasheet
+	 */
+	data->measurement_time_us = (conversion_time_us + dsp_time_us) * 105 / 100;
+}
+
+static void mlx90394_convert_magn(enum mlx90394_reg_config_val config, struct sensor_value *val,
+				  uint8_t sample_l, uint8_t sample_h)
+{
+	int64_t scale, conv_val;
+
+	if (config == MLX90394_CTRL2_CONFIG_HIGH_SENSITIVITY_LOW_NOISE) {
+		scale = MLX90394_HIGH_SENSITIVITY_MICRO_GAUSS_PER_BIT;
+	} else {
+		scale = MLX90394_HIGH_RANGE_MICRO_GAUSS_PER_BIT;
+	}
+	conv_val = (int16_t)((uint16_t)sample_l | (uint16_t)(sample_h << 8)) * scale;
+
+	val->val1 = conv_val / 1000000;               /* G */
+	val->val2 = conv_val - (val->val1 * 1000000); /* uG */
+}
+
+static void mlx90394_convert_temp(struct sensor_value *val, uint8_t sample_l, uint8_t sample_h)
+{
+	int64_t conv_val = sample_l | (sample_h << 8) * MLX90394_MICRO_CELSIUS_PER_BIT;
+
+	val->val1 = conv_val / 1000000;                 /* C */
+	val->val2 = (conv_val - (val->val1 * 1000000)); /* uC */
+}
+
+/*
+ * The user has to take care about that the requested channel was fetched before. Else the data will
+ * be random. Magnetic Flux Density is in Gauss, Temperature in Celsius
+ */
+static int mlx90394_channel_get(const struct device *dev, enum sensor_channel chan,
+				struct sensor_value *val)
+{
+	struct mlx90394_data *data = dev->data;
+
+	switch (chan) {
+	case SENSOR_CHAN_MAGN_X: {
+		mlx90394_convert_magn(data->config_val, val, data->sample.x_l, data->sample.x_h);
+	} break;
+	case SENSOR_CHAN_MAGN_Y: {
+		mlx90394_convert_magn(data->config_val, val, data->sample.y_l, data->sample.y_h);
+	} break;
+	case SENSOR_CHAN_MAGN_Z: {
+		mlx90394_convert_magn(data->config_val, val, data->sample.z_l, data->sample.z_h);
+	} break;
+	case SENSOR_CHAN_AMBIENT_TEMP: {
+		mlx90394_convert_temp(val, data->sample.temp_l, data->sample.temp_h);
+	} break;
+	case SENSOR_CHAN_MAGN_XYZ: {
+		mlx90394_convert_magn(data->config_val, val, data->sample.x_l, data->sample.x_h);
+		mlx90394_convert_magn(data->config_val, val + 1, data->sample.y_l,
+				      data->sample.y_h);
+		mlx90394_convert_magn(data->config_val, val + 2, data->sample.z_l,
+				      data->sample.z_h);
+	} break;
+	case SENSOR_CHAN_ALL: {
+		mlx90394_convert_magn(data->config_val, val, data->sample.x_l, data->sample.x_h);
+		mlx90394_convert_magn(data->config_val, val + 1, data->sample.y_l,
+				      data->sample.y_h);
+		mlx90394_convert_magn(data->config_val, val + 2, data->sample.z_l,
+				      data->sample.z_h);
+		mlx90394_convert_temp(val + 3, data->sample.temp_l, data->sample.temp_h);
+	} break;
+	default: {
+		LOG_DBG("Invalid channel %d", chan);
+		return -ENOTSUP;
+	}
+	}
+	return 0;
+}
+
+/**
+ * update a register on the device and @param old_value as well
+ */
+static inline int mlx90394_update_register(const struct device *dev, const uint8_t reg_addr,
+					   const uint8_t new_val, uint8_t *old_value)
+{
+	const struct mlx90394_config *cfg = dev->config;
+
+	if (new_val != *old_value) {
+		*old_value = new_val;
+		return i2c_reg_write_byte_dt(&cfg->i2c, reg_addr, new_val);
+	}
+	return 0;
+}
+
+static inline int mlx90394_sync_config_val(const struct device *dev)
+{
+	struct mlx90394_data *data = dev->data;
+	uint8_t updated_ctrl2;
+
+	updated_ctrl2 = MLX90394_FIELD_MOD(MLX90394_CTRL2_CONFIG, data->config_val,
+					   data->ctrl_reg_values.ctrl2);
+
+	return mlx90394_update_register(dev, MLX90394_REG_CTRL2, updated_ctrl2,
+					&data->ctrl_reg_values.ctrl2);
+}
+
+static inline int mlx90394_fs_set(const struct device *dev, const struct sensor_value *val)
+{
+	struct mlx90394_data *data = dev->data;
+
+	/*
+	 * in low current mode, only High Range is possible
+	 */
+	if (data->config_val == MLX90394_CTRL2_CONFIG_HIGH_RANGE_LOW_CURRENT) {
+		LOG_ERR("different FS values only supported in low noise mode");
+
+		return -ENOTSUP;
+	}
+
+	/* if the requested range is greater the driver switches from HIGH_SENSITIVITY to
+	 * HIGH_RANGE
+	 */
+	if (val->val1 > MLX90394_ATTR_FS_LOW_G) {
+		data->config_val = MLX90394_CTRL2_CONFIG_HIGH_RANGE_LOW_NOISE;
+	} else {
+		data->config_val = MLX90394_CTRL2_CONFIG_HIGH_SENSITIVITY_LOW_NOISE;
+	}
+
+	return mlx90394_sync_config_val(dev);
+}
+
+static inline int mlx90394_fs_get(const struct device *dev, struct sensor_value *val)
+{
+	struct mlx90394_data *data = dev->data;
+
+	val->val2 = 0;
+	if (data->config_val == MLX90394_CTRL2_CONFIG_HIGH_SENSITIVITY_LOW_NOISE) {
+		val->val1 = MLX90394_ATTR_FS_LOW_G;
+	} else {
+		val->val1 = MLX90394_ATTR_FS_HIGH_G;
+	}
+
+	return 0;
+}
+
+static inline int mlx90394_low_noise_set(const struct device *dev, struct sensor_value *val)
+{
+	struct mlx90394_data *data = dev->data;
+
+	switch (data->config_val) {
+	case MLX90394_CTRL2_CONFIG_HIGH_RANGE_LOW_CURRENT: {
+		if (val->val1) {
+			data->config_val = MLX90394_CTRL2_CONFIG_HIGH_RANGE_LOW_NOISE;
+
+			return mlx90394_sync_config_val(dev);
+		}
+	} break;
+	case MLX90394_CTRL2_CONFIG_HIGH_RANGE_LOW_NOISE: {
+		if (val->val1 == 0) {
+			data->config_val = MLX90394_CTRL2_CONFIG_HIGH_RANGE_LOW_CURRENT;
+
+			return mlx90394_sync_config_val(dev);
+		}
+	} break;
+	case MLX90394_CTRL2_CONFIG_HIGH_SENSITIVITY_LOW_NOISE: {
+		if (val->val1 == 0) {
+			LOG_ERR("High Sensitivity only supported in Low-Noise config, therefore "
+				"changing now to Low-Current config is not possible");
+
+			return -ENOTSUP;
+		}
+	} break;
+	}
+
+	return 0;
+}
+
+static inline int mlx90394_low_noise_get(const struct device *dev, struct sensor_value *val)
+{
+	struct mlx90394_data *data = dev->data;
+
+	val->val2 = 0;
+	if (data->config_val == MLX90394_CTRL2_CONFIG_HIGH_RANGE_LOW_CURRENT) {
+		val->val1 = 0;
+	} else {
+		val->val1 = 1;
+	}
+
+	return 0;
+}
+
+/*
+ * helper function to get/set attributes if set is 0 it will be a get, otherwise is interpreted
+ * as set
+ */
+static int mlx90394_attr_helper(const struct device *dev, enum sensor_channel chan,
+				unsigned int attr, struct sensor_value *val, uint8_t set)
+{
+	struct mlx90394_data *data = dev->data;
+
+	if (!data->initialized) {
+		return -ENODEV;
+	}
+
+	switch (attr) {
+	case SENSOR_ATTR_FULL_SCALE: {
+		if (chan != SENSOR_CHAN_MAGN_XYZ) {
+			return -ENOTSUP;
+		}
+
+		if (set) {
+			return mlx90394_fs_set(dev, val);
+		} else {
+			return mlx90394_fs_get(dev, val);
+		}
+	} break;
+
+	case MLX90394_SENSOR_ATTR_MAGN_LOW_NOISE: {
+		if (chan != SENSOR_CHAN_MAGN_XYZ) {
+			return -ENOTSUP;
+		}
+
+		if (set) {
+			return mlx90394_low_noise_set(dev, val);
+		} else {
+			return mlx90394_low_noise_get(dev, val);
+		}
+	} break;
+
+	case MLX90394_SENSOR_ATTR_MAGN_FILTER_XY: {
+		if (set) {
+			if (val->val1 > 7 || val->val1 < 0) {
+				return -EINVAL;
+			}
+
+			return mlx90394_update_register(
+				dev, MLX90394_REG_CTRL3,
+				MLX90394_FIELD_MOD(MLX90394_CTRL3_DIG_FILT_HALL_XY, val->val1,
+						   data->ctrl_reg_values.ctrl3),
+				&data->ctrl_reg_values.ctrl3);
+		} else {
+			val->val1 = FIELD_GET(MLX90394_CTRL3_DIG_FILT_HALL_XY,
+					      data->ctrl_reg_values.ctrl3);
+			val->val2 = 0;
+		}
+	} break;
+	case MLX90394_SENSOR_ATTR_MAGN_FILTER_Z: {
+		if (set) {
+			if (val->val1 > 7 || val->val1 < 0) {
+
+				return -EINVAL;
+			}
+
+			return mlx90394_update_register(
+				dev, MLX90394_REG_CTRL4,
+				MLX90394_FIELD_MOD(MLX90394_CTRL4_DIG_FILT_HALL_Z, val->val1,
+						   data->ctrl_reg_values.ctrl4),
+				&data->ctrl_reg_values.ctrl4);
+		} else {
+			val->val1 = FIELD_GET(MLX90394_CTRL4_DIG_FILT_HALL_Z,
+					      data->ctrl_reg_values.ctrl4);
+			val->val2 = 0;
+		}
+	} break;
+	case MLX90394_SENSOR_ATTR_MAGN_OSR: {
+		if (set) {
+			if (val->val1 > 1 || val->val1 < 0) {
+
+				return -EINVAL;
+			}
+
+			return mlx90394_update_register(
+				dev, MLX90394_REG_CTRL3,
+				MLX90394_FIELD_MOD(MLX90394_CTRL3_OSR_HALL, val->val1,
+						   data->ctrl_reg_values.ctrl3),
+				&data->ctrl_reg_values.ctrl3);
+		} else {
+			val->val1 = FIELD_GET(MLX90394_CTRL3_OSR_HALL, data->ctrl_reg_values.ctrl3);
+			val->val2 = 0;
+		}
+	} break;
+	case MLX90394_SENSOR_ATTR_TEMP_FILTER: {
+		if (set) {
+			if (val->val1 > 7 || val->val1 < 0) {
+				return -EINVAL;
+			}
+			return mlx90394_update_register(
+				dev, MLX90394_REG_CTRL3,
+				MLX90394_FIELD_MOD(MLX90394_CTRL3_DIG_FILT_TEMP, val->val1,
+						   data->ctrl_reg_values.ctrl3),
+				&data->ctrl_reg_values.ctrl3);
+		} else {
+			val->val1 = FIELD_GET(MLX90394_CTRL3_DIG_FILT_TEMP,
+					      data->ctrl_reg_values.ctrl3);
+			val->val2 = 0;
+		}
+	} break;
+	case MLX90394_SENSOR_ATTR_TEMP_OSR: {
+		if (set) {
+			if (val->val1 > 1 || val->val1 < 0) {
+				return -EINVAL;
+			}
+			return mlx90394_update_register(
+				dev, MLX90394_REG_CTRL3,
+				MLX90394_FIELD_MOD(MLX90394_CTRL3_OSR_TEMP, val->val1,
+						   data->ctrl_reg_values.ctrl3),
+				&data->ctrl_reg_values.ctrl3);
+		} else {
+			val->val1 = FIELD_GET(MLX90394_CTRL3_OSR_TEMP, data->ctrl_reg_values.ctrl3);
+			val->val2 = 0;
+		}
+	} break;
+	default: {
+		return -ENOTSUP;
+	}
+	}
+
+	return 0;
+}
+static int mlx90394_attr_get(const struct device *dev, enum sensor_channel chan,
+			     enum sensor_attribute attr, struct sensor_value *val)
+{
+	return mlx90394_attr_helper(dev, chan, (unsigned int)attr, val, 0);
+}
+
+static int mlx90394_attr_set(const struct device *dev, enum sensor_channel chan,
+			     enum sensor_attribute attr, const struct sensor_value *val)
+{
+	/*
+	 * must be a copy because val is const
+	 */
+	struct sensor_value val_copy = *val;
+	int rc;
+
+	rc = mlx90394_attr_helper(dev, chan, (unsigned int)attr, &val_copy, 1);
+	if (rc == 0) {
+		mlx90394_update_measurement_Time_us(dev->data);
+	}
+
+	return rc;
+}
+
+static inline int mlx90394_check_who_am_i(const struct i2c_dt_spec *i2c)
+{
+	uint8_t buffer[2];
+	int rc;
+
+	rc = i2c_burst_read_dt(i2c, MLX90394_REG_CID, buffer, ARRAY_SIZE(buffer));
+	if (rc != 0) {
+		LOG_ERR("Failed to read who-am-i register (rc=%d)", rc);
+		return -EIO;
+	}
+
+	if (buffer[0] != MLX90394_CID || buffer[1] != MLX90394_DID) {
+		LOG_ERR("Wrong who-am-i value");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int mlx90394_write_read_dt(const struct i2c_dt_spec *i2c, uint8_t start_addr,
+				  uint8_t *buffer_write, uint8_t *buffer_read, size_t cnt)
+{
+	int rc;
+
+	rc = i2c_burst_write_dt(i2c, start_addr, buffer_write, cnt);
+	if (rc != 0) {
+		LOG_ERR("Failed to write %d bytes to register %d (rc=%d)", cnt, start_addr, rc);
+		return -EIO;
+	}
+	rc = i2c_burst_read_dt(i2c, start_addr, buffer_read, cnt);
+	if (rc != 0) {
+		LOG_ERR("Failed to read %d bytes from register %d (rc=%d)", cnt, start_addr, rc);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+int mlx90394_sample_fetch_internal(const struct device *dev, enum sensor_channel chan)
+{
+	const struct mlx90394_config *cfg = dev->config;
+	struct mlx90394_data *data = dev->data;
+	int rc;
+
+	if (!data->initialized) {
+		return -ENODEV;
+	}
+
+	rc = i2c_burst_read_dt(&cfg->i2c, MLX90394_REG_STAT1, (uint8_t *)&data->sample,
+			       MLX90394_REG_TH + 1);
+	if (rc != 0) {
+		LOG_ERR("Failed to read bytes");
+		return rc;
+	}
+
+	if (FIELD_GET(MLX90394_STAT1_DRDY, data->sample.stat1) != 1) {
+		LOG_ERR("Data was not ready during fetch. In continues mode consider to "
+			"adjust "
+			"sample frequency");
+		return -EIO;
+	}
+	return 0;
+}
+
+int mlx90394_trigger_measurement_internal(const struct device *dev, enum sensor_channel chan)
+{
+	const struct mlx90394_config *cfg = dev->config;
+	struct mlx90394_data *data = dev->data;
+	int rc;
+
+	if (!data->initialized) {
+		return -ENODEV;
+	}
+
+	/*
+	 * set single measurement mode as default if not already done
+	 */
+	if (FIELD_GET(MLX90394_CTRL1_MODE, data->ctrl_reg_values.ctrl1) !=
+	    MLX90394_CTRL1_MODE_SINGLE) {
+		data->ctrl_reg_values.ctrl1 =
+			MLX90394_FIELD_MOD(MLX90394_CTRL1_MODE, MLX90394_CTRL1_MODE_SINGLE,
+					   data->ctrl_reg_values.ctrl1);
+	}
+
+	/*
+	 * change channel bits and update ctrl4 and the measurement time
+	 * if the channel is different than during the last measurement
+	 */
+	if (chan != data->channel) {
+		switch (chan) {
+		case SENSOR_CHAN_MAGN_X: {
+			WRITE_BIT(data->ctrl_reg_values.ctrl1, MLX90394_CTRL1_X_EN_BIT, 1);
+			WRITE_BIT(data->ctrl_reg_values.ctrl1, MLX90394_CTRL1_Y_EN_BIT, 0);
+			WRITE_BIT(data->ctrl_reg_values.ctrl1, MLX90394_CTRL1_Z_EN_BIT, 0);
+			WRITE_BIT(data->ctrl_reg_values.ctrl4, MLX90394_CTRL4_T_EN_BIT, 0);
+		} break;
+		case SENSOR_CHAN_MAGN_Y: {
+			WRITE_BIT(data->ctrl_reg_values.ctrl1, MLX90394_CTRL1_X_EN_BIT, 0);
+			WRITE_BIT(data->ctrl_reg_values.ctrl1, MLX90394_CTRL1_Y_EN_BIT, 1);
+			WRITE_BIT(data->ctrl_reg_values.ctrl1, MLX90394_CTRL1_Z_EN_BIT, 0);
+			WRITE_BIT(data->ctrl_reg_values.ctrl4, MLX90394_CTRL4_T_EN_BIT, 0);
+		} break;
+		case SENSOR_CHAN_MAGN_Z: {
+			WRITE_BIT(data->ctrl_reg_values.ctrl1, MLX90394_CTRL1_X_EN_BIT, 0);
+			WRITE_BIT(data->ctrl_reg_values.ctrl1, MLX90394_CTRL1_Y_EN_BIT, 0);
+			WRITE_BIT(data->ctrl_reg_values.ctrl1, MLX90394_CTRL1_Z_EN_BIT, 1);
+			WRITE_BIT(data->ctrl_reg_values.ctrl4, MLX90394_CTRL4_T_EN_BIT, 0);
+		} break;
+		case SENSOR_CHAN_MAGN_XYZ: {
+			WRITE_BIT(data->ctrl_reg_values.ctrl1, MLX90394_CTRL1_X_EN_BIT, 1);
+			WRITE_BIT(data->ctrl_reg_values.ctrl1, MLX90394_CTRL1_Y_EN_BIT, 1);
+			WRITE_BIT(data->ctrl_reg_values.ctrl1, MLX90394_CTRL1_Z_EN_BIT, 1);
+			WRITE_BIT(data->ctrl_reg_values.ctrl4, MLX90394_CTRL4_T_EN_BIT, 0);
+		} break;
+		case SENSOR_CHAN_AMBIENT_TEMP: {
+			WRITE_BIT(data->ctrl_reg_values.ctrl1, MLX90394_CTRL1_X_EN_BIT, 0);
+			WRITE_BIT(data->ctrl_reg_values.ctrl1, MLX90394_CTRL1_Y_EN_BIT, 0);
+			WRITE_BIT(data->ctrl_reg_values.ctrl1, MLX90394_CTRL1_Z_EN_BIT, 0);
+			WRITE_BIT(data->ctrl_reg_values.ctrl4, MLX90394_CTRL4_T_EN_BIT, 1);
+		} break;
+		case SENSOR_CHAN_ALL: {
+			WRITE_BIT(data->ctrl_reg_values.ctrl1, MLX90394_CTRL1_X_EN_BIT, 1);
+			WRITE_BIT(data->ctrl_reg_values.ctrl1, MLX90394_CTRL1_Y_EN_BIT, 1);
+			WRITE_BIT(data->ctrl_reg_values.ctrl1, MLX90394_CTRL1_Z_EN_BIT, 1);
+			WRITE_BIT(data->ctrl_reg_values.ctrl4, MLX90394_CTRL4_T_EN_BIT, 1);
+		} break;
+		default: {
+			return -ENOTSUP;
+		}
+		}
+		rc = i2c_reg_write_byte_dt(&cfg->i2c, MLX90394_REG_CTRL4,
+					   data->ctrl_reg_values.ctrl4);
+		if (rc != 0) {
+			LOG_ERR("Failed to write ctrl4");
+			return rc;
+		}
+
+		data->channel = chan;
+		mlx90394_update_measurement_Time_us(data);
+	}
+
+	rc = i2c_reg_write_byte_dt(&cfg->i2c, MLX90394_REG_CTRL1, data->ctrl_reg_values.ctrl1);
+	if (rc != 0) {
+		LOG_ERR("Failed to write ctrl1");
+	}
+
+	return rc;
+}
+
+static int mlx90394_sample_fetch(const struct device *dev, enum sensor_channel chan)
+{
+	int rc;
+	struct mlx90394_data *data = dev->data;
+
+	rc = mlx90394_trigger_measurement_internal(dev, chan);
+	if (rc != 0) {
+		return rc;
+	}
+
+	k_usleep(data->measurement_time_us);
+	rc = mlx90394_sample_fetch_internal(dev, chan);
+
+	return rc;
+}
+
+static int mlx90394_init(const struct device *dev)
+{
+	const struct mlx90394_config *cfg = dev->config;
+	struct mlx90394_data *data = dev->data;
+	int rc;
+
+	if (!i2c_is_ready_dt(&cfg->i2c)) {
+		LOG_ERR("I2C bus device not ready");
+		return -ENODEV;
+	}
+
+	/*
+	 * Soft reset the chip
+	 */
+	rc = i2c_reg_write_byte_dt(&cfg->i2c, MLX90394_REG_RST, MLX90394_RST);
+	if (rc != 0) {
+		LOG_ERR("Failed to soft reset");
+		return -EIO;
+	}
+	k_usleep(MLX90394_STARTUP_TIME_US);
+
+	/*
+	 * check chip ID
+	 */
+	rc = mlx90394_check_who_am_i(&cfg->i2c);
+	if (rc != 0) {
+		return rc;
+	}
+
+	/*
+	 * set all to default and read the settings back
+	 */
+	rc = mlx90394_write_read_dt(&cfg->i2c, MLX90394_REG_CTRL1,
+				    (uint8_t *)&data->ctrl_reg_values.ctrl1,
+				    (uint8_t *)&data->ctrl_reg_values.ctrl1, 2);
+	if (rc != 0) {
+		return rc;
+	}
+
+	rc = mlx90394_write_read_dt(&cfg->i2c, MLX90394_REG_CTRL3,
+				    (uint8_t *)&data->ctrl_reg_values.ctrl3,
+				    (uint8_t *)&data->ctrl_reg_values.ctrl3, 2);
+	if (rc != 0) {
+		return rc;
+	}
+
+	mlx90394_update_measurement_Time_us(data);
+
+#ifdef CONFIG_SENSOR_ASYNC_API
+	data->dev = dev;
+	/*
+	 * init work for fetching after measurement has completed
+	 */
+	k_work_init_delayable(&data->async_fetch_work, mlx90394_async_fetch);
+#endif
+	data->initialized = true;
+	return 0;
+}
+
+static DEVICE_API(sensor, mlx90394_driver_api) = {
+	.sample_fetch = mlx90394_sample_fetch,
+	.channel_get = mlx90394_channel_get,
+	.attr_get = mlx90394_attr_get,
+	.attr_set = mlx90394_attr_set,
+#ifdef CONFIG_SENSOR_ASYNC_API
+	.submit = mlx90394_submit,
+	.get_decoder = mlx90394_get_decoder,
+#endif
+};
+
+#define MLX90394_DEFINE(inst)                                                                      \
+	static struct mlx90394_data mlx90394_data_##inst = {                                       \
+		.sample = {.x_l = 0,                                                               \
+			   .x_h = 0,                                                               \
+			   .y_l = 0,                                                               \
+			   .y_h = 0,                                                               \
+			   .z_l = 0,                                                               \
+			   .z_h = 0,                                                               \
+			   .temp_l = 0,                                                            \
+			   .temp_h = 0},                                                           \
+		.channel = SENSOR_CHAN_MAGN_XYZ,                                                   \
+		.config_val = FIELD_GET(MLX90394_CTRL2_CONFIG, MLX90394_CTRL2_DEFAULT),            \
+		.measurement_time_us = 0,                                                          \
+		.ctrl_reg_values = {.ctrl1 = MLX90394_CTRL1_DEFAULT,                               \
+				    .ctrl2 = MLX90394_CTRL2_DEFAULT,                               \
+				    .ctrl3 = MLX90394_CTRL3_DEFAULT,                               \
+				    .ctrl4 = MLX90394_CTRL4_DEFAULT},                              \
+		.initialized = false};                                                             \
+	static const struct mlx90394_config mlx90394_config_##inst = {                             \
+		.i2c = I2C_DT_SPEC_INST_GET(inst)};                                                \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, mlx90394_init, NULL, &mlx90394_data_##inst,             \
+				     &mlx90394_config_##inst, POST_KERNEL,                         \
+				     CONFIG_SENSOR_INIT_PRIORITY, &mlx90394_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(MLX90394_DEFINE)
diff --git a/drivers/sensor/melexis/mlx90394/mlx90394.h b/drivers/sensor/melexis/mlx90394/mlx90394.h
new file mode 100644
index 00000000000..3c61e1f5069
--- /dev/null
+++ b/drivers/sensor/melexis/mlx90394/mlx90394.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2024 Florian Weber <Florian.Weber@live.de>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_MLX90394_MLX90394_H_
+#define ZEPHYR_DRIVERS_SENSOR_MLX90394_MLX90394_H_
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/rtio/rtio.h>
+
+#include "mlx90394_reg.h"
+
+/*
+ * Time it takes to start-up the device and switch to powerdown mode (after powercycle or soft
+ * reset)
+ */
+#define MLX90394_STARTUP_TIME_US 400
+
+/* Conversion values */
+#define MLX90394_HIGH_RANGE_MICRO_GAUSS_PER_BIT       INT64_C(15000)
+#define MLX90394_HIGH_SENSITIVITY_MICRO_GAUSS_PER_BIT INT64_C(1500)
+#define MLX90394_MICRO_CELSIUS_PER_BIT                INT64_C(20000)
+
+/* values for setting SENSOR_ATTR_FULL_SCALE */
+#define MLX90394_ATTR_FS_HIGH_G INT32_C(500)
+#define MLX90394_ATTR_FS_LOW_G  INT32_C(50)
+
+struct mlx90394_data {
+	struct __packed {
+		uint8_t stat1;
+		uint8_t x_l;
+		uint8_t x_h;
+		uint8_t y_l;
+		uint8_t y_h;
+		uint8_t z_l;
+		uint8_t z_h;
+		uint8_t stat2;
+		uint8_t temp_l;
+		uint8_t temp_h;
+	} sample;
+	enum sensor_channel channel;
+	enum mlx90394_reg_config_val config_val;
+	int32_t measurement_time_us;
+	struct __packed {
+		uint8_t ctrl1;
+		uint8_t ctrl2;
+		uint8_t ctrl3;
+		uint8_t ctrl4;
+	} ctrl_reg_values;
+	bool initialized;
+#ifdef CONFIG_SENSOR_ASYNC_API
+	struct {
+		struct rtio_iodev_sqe *iodev_sqe;
+		uint64_t timestamp;
+		enum mlx90394_reg_config_val config_val;
+	} work_ctx;
+	struct k_work_delayable async_fetch_work;
+	const struct device *dev;
+#endif
+};
+
+struct mlx90394_config {
+	struct i2c_dt_spec i2c;
+};
+
+int mlx90394_sample_fetch_internal(const struct device *dev, enum sensor_channel chan);
+int mlx90394_trigger_measurement_internal(const struct device *dev, enum sensor_channel chan);
+
+/* RTIO types and defines */
+#ifdef CONFIG_SENSOR_ASYNC_API
+
+/* shift value to use. */
+#define MLX90394_SHIFT_MAGN_HIGH_SENSITIVITY (6)
+#define MLX90394_SHIFT_MAGN_HIGH_RANGE       (9)
+#define MLX90394_SHIFT_TEMP                  (10)
+
+void mlx90394_async_fetch(struct k_work *work);
+
+struct mlx90394_decoder_header {
+	uint64_t timestamp;
+	enum mlx90394_reg_config_val config_val;
+};
+
+struct mlx90394_encoded_data {
+	struct mlx90394_decoder_header header;
+	int16_t readings[4];
+};
+
+int mlx90394_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder);
+void mlx90394_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe);
+#endif
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_MLX90394_MLX90394_H_ */
diff --git a/drivers/sensor/melexis/mlx90394/mlx90394_async.c b/drivers/sensor/melexis/mlx90394/mlx90394_async.c
new file mode 100644
index 00000000000..f3309da68de
--- /dev/null
+++ b/drivers/sensor/melexis/mlx90394/mlx90394_async.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2024 Florian Weber <Florian.Weber@live.de>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT melexis_mlx90394
+
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/sensor_clock.h>
+
+#include "mlx90394.h"
+#include "mlx90394_reg.h"
+
+#include <stddef.h>
+
+LOG_MODULE_DECLARE(MLX90394, CONFIG_SENSOR_LOG_LEVEL);
+
+void mlx90394_async_fetch(struct k_work *work)
+{
+	int rc;
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct mlx90394_data *data = CONTAINER_OF(dwork, struct mlx90394_data, async_fetch_work);
+	const struct device *dev = data->dev;
+	const struct sensor_read_config *cfg =
+		data->work_ctx.iodev_sqe->sqe.iodev->data;
+	struct mlx90394_encoded_data *edata;
+	uint32_t buf_len = sizeof(struct mlx90394_encoded_data);
+	uint8_t *buf;
+
+	rc = mlx90394_sample_fetch_internal(dev, cfg->channels->chan_type);
+	if (rc != 0) {
+		LOG_ERR("Failed to fetch samples");
+		rtio_iodev_sqe_err(data->work_ctx.iodev_sqe, rc);
+		return;
+	}
+	/* Get the buffer for the frame, it may be allocated dynamically by the rtio context */
+	rc = rtio_sqe_rx_buf(data->work_ctx.iodev_sqe, buf_len, buf_len, &buf, &buf_len);
+	if (rc != 0) {
+		LOG_ERR("Failed to get a read buffer of size %u bytes", buf_len);
+		rtio_iodev_sqe_err(data->work_ctx.iodev_sqe, rc);
+		return;
+	}
+
+	edata = (struct mlx90394_encoded_data *)buf;
+
+	/* buffered from submit */
+	edata->header.timestamp = data->work_ctx.timestamp;
+	edata->header.config_val = data->work_ctx.config_val;
+
+	switch (cfg->channels->chan_type) {
+	case SENSOR_CHAN_MAGN_X: {
+		edata->readings[0] =
+			(int16_t)((uint16_t)data->sample.x_l | (uint16_t)(data->sample.x_h << 8));
+	} break;
+	case SENSOR_CHAN_MAGN_Y: {
+		edata->readings[1] =
+			(int16_t)((uint16_t)data->sample.y_l | (uint16_t)(data->sample.y_h << 8));
+	} break;
+	case SENSOR_CHAN_MAGN_Z: {
+		edata->readings[2] =
+			(int16_t)((uint16_t)data->sample.z_l | (uint16_t)(data->sample.z_h << 8));
+	} break;
+	case SENSOR_CHAN_AMBIENT_TEMP: {
+		edata->readings[3] = (int16_t)((uint16_t)data->sample.temp_l |
+					       (uint16_t)(data->sample.temp_h << 8));
+	} break;
+	case SENSOR_CHAN_MAGN_XYZ: {
+		edata->readings[0] =
+			(int16_t)((uint16_t)data->sample.x_l | (uint16_t)(data->sample.x_h << 8));
+		edata->readings[1] =
+			(int16_t)((uint16_t)data->sample.y_l | (uint16_t)(data->sample.y_h << 8));
+		edata->readings[2] =
+			(int16_t)((uint16_t)data->sample.z_l | (uint16_t)(data->sample.z_h << 8));
+	} break;
+	case SENSOR_CHAN_ALL: {
+		edata->readings[0] =
+			(int16_t)((uint16_t)data->sample.x_l | (uint16_t)(data->sample.x_h << 8));
+		edata->readings[1] =
+			(int16_t)((uint16_t)data->sample.y_l | (uint16_t)(data->sample.y_h << 8));
+		edata->readings[2] =
+			(int16_t)((uint16_t)data->sample.z_l | (uint16_t)(data->sample.z_h << 8));
+		edata->readings[3] = (int16_t)((uint16_t)data->sample.temp_l |
+					       (uint16_t)(data->sample.temp_h << 8));
+	} break;
+	default: {
+		LOG_DBG("Invalid channel %d", cfg->channels->chan_type);
+		rtio_iodev_sqe_err(data->work_ctx.iodev_sqe, -ENOTSUP);
+		return;
+	}
+	}
+	rtio_iodev_sqe_ok(data->work_ctx.iodev_sqe, 0);
+}
+
+void mlx90394_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
+{
+	int rc;
+	const struct sensor_read_config *cfg = iodev_sqe->sqe.iodev->data;
+	struct mlx90394_data *data = dev->data;
+	uint64_t cycles;
+
+	rc = mlx90394_trigger_measurement_internal(dev, cfg->channels->chan_type);
+	if (rc != 0) {
+		LOG_ERR("Failed to trigger measurement");
+		rtio_iodev_sqe_err(iodev_sqe, rc);
+		return;
+	}
+
+	rc = sensor_clock_get_cycles(&cycles);
+	if (rc != 0) {
+		LOG_ERR("Failed to get sensor clock cycles");
+		rtio_iodev_sqe_err(iodev_sqe, rc);
+		return;
+	}
+
+	/* save information for the work item */
+	data->work_ctx.timestamp = sensor_clock_cycles_to_ns(cycles);
+	data->work_ctx.iodev_sqe = iodev_sqe;
+	data->work_ctx.config_val = data->config_val;
+
+	/* schedule work to read out sensor and inform the executor about completion with success */
+	k_work_schedule(&data->async_fetch_work, K_USEC(data->measurement_time_us));
+}
diff --git a/drivers/sensor/melexis/mlx90394/mlx90394_decoder.c b/drivers/sensor/melexis/mlx90394/mlx90394_decoder.c
new file mode 100644
index 00000000000..46365f7dbd4
--- /dev/null
+++ b/drivers/sensor/melexis/mlx90394/mlx90394_decoder.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2024 Florian Weber <Florian.Weber@live.de>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "mlx90394.h"
+#include <zephyr/drivers/sensor.h>
+
+#define DT_DRV_COMPAT melexis_mlx90394
+
+static int mlx90394_decoder_get_frame_count(const uint8_t *buffer, struct sensor_chan_spec channel,
+					    uint16_t *frame_count)
+{
+	ARG_UNUSED(buffer);
+	ARG_UNUSED(channel);
+
+	/* This sensor lacks a FIFO; there will always only be one frame at a time. */
+	*frame_count = 1;
+	return 0;
+}
+
+static int mlx90394_decoder_get_size_info(struct sensor_chan_spec channel, size_t *base_size,
+					  size_t *frame_size)
+{
+	switch (channel.chan_type) {
+	case SENSOR_CHAN_MAGN_X:
+	case SENSOR_CHAN_MAGN_Y:
+	case SENSOR_CHAN_MAGN_Z:
+	case SENSOR_CHAN_MAGN_XYZ: {
+		*base_size = sizeof(struct sensor_three_axis_data);
+		*frame_size = sizeof(struct sensor_three_axis_sample_data);
+	} break;
+	case SENSOR_CHAN_AMBIENT_TEMP: {
+		*base_size = sizeof(struct sensor_q31_data);
+		*frame_size = sizeof(struct sensor_q31_sample_data);
+	} break;
+	default:
+		return -ENOTSUP;
+	}
+	return 0;
+}
+
+static int mlx90394_convert_raw_magn_to_q31(int16_t reading, q31_t *out,
+					    const enum mlx90394_reg_config_val config_val)
+{
+	int64_t intermediate;
+
+	if (config_val == MLX90394_CTRL2_CONFIG_HIGH_SENSITIVITY_LOW_NOISE) {
+		intermediate = ((int64_t)reading * MLX90394_HIGH_SENSITIVITY_MICRO_GAUSS_PER_BIT) *
+			       ((int64_t)INT32_MAX + 1) /
+			       ((1 << MLX90394_SHIFT_MAGN_HIGH_SENSITIVITY) * INT64_C(1000000));
+	} else {
+		intermediate = ((int64_t)reading * MLX90394_HIGH_RANGE_MICRO_GAUSS_PER_BIT) *
+			       ((int64_t)INT32_MAX + 1) /
+			       ((1 << MLX90394_SHIFT_MAGN_HIGH_RANGE) * INT64_C(1000000));
+	}
+
+	*out = CLAMP(intermediate, INT32_MIN, INT32_MAX);
+	return 0;
+}
+static int mlx90394_convert_raw_temp_to_q31(int16_t reading, q31_t *out)
+{
+
+	int64_t intermediate = ((int64_t)reading * MLX90394_MICRO_CELSIUS_PER_BIT) *
+			       ((int64_t)INT32_MAX + 1) /
+			       ((1 << MLX90394_SHIFT_TEMP) * INT64_C(1000000));
+
+	*out = CLAMP(intermediate, INT32_MIN, INT32_MAX);
+	return 0;
+}
+
+static int mlx90394_decoder_decode(const uint8_t *buffer, struct sensor_chan_spec channel,
+				   uint32_t *fit, uint16_t max_count, void *data_out)
+{
+	const struct mlx90394_encoded_data *edata = (const struct mlx90394_encoded_data *)buffer;
+
+	if (*fit != 0) {
+		return 0;
+	}
+
+	switch (channel.chan_type) {
+	case SENSOR_CHAN_MAGN_X:
+	case SENSOR_CHAN_MAGN_Y:
+	case SENSOR_CHAN_MAGN_Z:
+	case SENSOR_CHAN_MAGN_XYZ: {
+		struct sensor_three_axis_data *out = data_out;
+
+		out->header.base_timestamp_ns = edata->header.timestamp;
+		out->header.reading_count = 1;
+		if (edata->header.config_val == MLX90394_CTRL2_CONFIG_HIGH_SENSITIVITY_LOW_NOISE) {
+			out->shift = MLX90394_SHIFT_MAGN_HIGH_SENSITIVITY;
+		} else {
+			out->shift = MLX90394_SHIFT_MAGN_HIGH_RANGE;
+		}
+
+		mlx90394_convert_raw_magn_to_q31(edata->readings[0], &out->readings[0].x,
+						 edata->header.config_val);
+		mlx90394_convert_raw_magn_to_q31(edata->readings[1], &out->readings[0].y,
+						 edata->header.config_val);
+		mlx90394_convert_raw_magn_to_q31(edata->readings[2], &out->readings[0].z,
+						 edata->header.config_val);
+		*fit = 1;
+	} break;
+	case SENSOR_CHAN_AMBIENT_TEMP: {
+		struct sensor_q31_data *out = data_out;
+
+		out->header.base_timestamp_ns = edata->header.timestamp;
+		out->header.reading_count = 1;
+		out->shift = MLX90394_SHIFT_TEMP;
+		mlx90394_convert_raw_temp_to_q31(edata->readings[3], &out->readings[0].temperature);
+		*fit = 1;
+	} break;
+	default:
+		return -ENOTSUP;
+	}
+	return 1;
+}
+
+SENSOR_DECODER_API_DT_DEFINE() = {
+	.get_frame_count = mlx90394_decoder_get_frame_count,
+	.get_size_info = mlx90394_decoder_get_size_info,
+	.decode = mlx90394_decoder_decode,
+};
+
+int mlx90394_get_decoder(const struct device *dev, const struct sensor_decoder_api **decoder)
+{
+	ARG_UNUSED(dev);
+	*decoder = &SENSOR_DECODER_NAME();
+
+	return 0;
+}
diff --git a/drivers/sensor/melexis/mlx90394/mlx90394_reg.h b/drivers/sensor/melexis/mlx90394/mlx90394_reg.h
new file mode 100644
index 00000000000..5ad185cf251
--- /dev/null
+++ b/drivers/sensor/melexis/mlx90394/mlx90394_reg.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2024 Florian Weber <Florian.Weber@live.de>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_MLX90394_MLX90394_REG_H
+#define ZEPHYR_DRIVERS_SENSOR_MLX90394_MLX90394_REG_H
+
+#include <zephyr/sys/util_macro.h>
+/* REGISTERS */
+/* Status and measurent output */
+#define MLX90394_REG_STAT1 0x00
+#define MLX90394_REG_BXL   0x01
+#define MLX90394_REG_BXH   0x02
+#define MLX90394_REG_BYL   0x03
+#define MLX90394_REG_BYH   0x04
+#define MLX90394_REG_BZL   0x05
+#define MLX90394_REG_BZH   0x06
+#define MLX90394_REG_STAT2 0x07
+#define MLX90394_REG_TL    0x08
+#define MLX90394_REG_TH    0x09
+
+/* Who Am I registers */
+#define MLX90394_REG_CID 0x0A
+#define MLX90394_REG_DID 0x0B
+
+/* Control registers */
+#define MLX90394_REG_CTRL1 0x0E
+#define MLX90394_REG_CTRL2 0x0F
+#define MLX90394_REG_CTRL3 0x14
+#define MLX90394_REG_CTRL4 0x15
+
+/* Reset register */
+#define MLX90394_REG_RST 0x11
+
+/* Wake On Change registers  */
+#define MLX90394_REG_WOC_XL 0x58
+#define MLX90394_REG_WOC_XH 0x59
+#define MLX90394_REG_WOC_YL 0x5A
+#define MLX90394_REG_WOC_YH 0x5B
+#define MLX90394_REG_WOC_ZL 0x5C
+#define MLX90394_REG_WOC_ZH 0x5D
+
+/* VALUES */
+/* STAT1 values RO */
+#define MLX90394_STAT1_DRDY    BIT(0)
+#define MLX90394_STAT1_DOR     BIT(3)
+#define MLX90394_STAT1_RT      BIT(3)
+#define MLX90394_STAT1_INT     BIT(4)
+#define MLX90394_STAT1_DEFAULT (MLX90394_STAT1_RT)
+
+/* STAT2 values RO */
+#define MLX90394_STAT2_HOVF_X  BIT(0)
+#define MLX90394_STAT2_HOVF_Y  BIT(1)
+#define MLX90394_STAT2_HOVF_Z  BIT(2)
+#define MLX90394_STAT2_DOR     BIT(3)
+#define MLX90394_STAT2_DEFAULT 0
+
+/* Who-I-Am register values RO */
+#define MLX90394_CID 0x94
+#define MLX90394_DID 0xaa
+
+/* Write this value to reset Register soft resets the chip RW */
+#define MLX90394_RST 0x06
+
+/* CTRL1 values RW */
+#define MLX90394_CTRL1_X_EN_BIT    4
+#define MLX90394_CTRL1_Y_EN_BIT    5
+#define MLX90394_CTRL1_Z_EN_BIT    6
+#define MLX90394_CTRL1_MODE        GENMASK(3, 0)
+#define MLX90394_CTRL1_MODE_SINGLE 1
+#define MLX90394_CTRL1_X_EN        BIT(MLX90394_CTRL1_X_EN_BIT)
+#define MLX90394_CTRL1_Y_EN        BIT(MLX90394_CTRL1_Y_EN_BIT)
+#define MLX90394_CTRL1_Z_EN        BIT(MLX90394_CTRL1_Z_EN_BIT)
+#define MLX90394_CTRL1_SWOK        BIT(7)
+#define MLX90394_CTRL1_PREP(MODE, X_EN, Y_EN, Z_EN, SWOK)                                          \
+	(FIELD_PREP(MLX90394_CTRL1_MODE, MODE) | FIELD_PREP(MLX90394_CTRL1_X_EN, X_EN) |           \
+	 FIELD_PREP(MLX90394_CTRL1_Y_EN, Y_EN) | FIELD_PREP(MLX90394_CTRL1_Z_EN, Z_EN) |           \
+	 FIELD_PREP(MLX90394_CTRL1_SWOK, SWOK))
+#define MLX90394_CTRL1_DEFAULT MLX90394_CTRL1_PREP(0, 1, 1, 1, 0)
+
+/* CTRL2 values RW */
+enum mlx90394_reg_config_val {
+	MLX90394_CTRL2_CONFIG_HIGH_RANGE_LOW_CURRENT = 0,
+	MLX90394_CTRL2_CONFIG_HIGH_RANGE_LOW_NOISE,
+	MLX90394_CTRL2_CONFIG_HIGH_SENSITIVITY_LOW_NOISE
+};
+#define MLX90394_CTRL2_WOC_MODE   GENMASK(1, 0)
+#define MLX90394_CTRL2_INTREPB    BIT(2)
+#define MLX90394_CTRL2_INTB_SCL_B BIT(3)
+#define MLX90394_CTRL2_INTDUR     GENMASK(5, 4)
+#define MLX90394_CTRL2_CONFIG     GENMASK(7, 6)
+#define MLX90394_CTRL2_PREP(WOC_MODE, INTREPB, INTB_SCL_B, INTDUR, CONFIG)                         \
+	(FIELD_PREP(MLX90394_CTRL2_WOC_MODE, WOC_MODE) |                                           \
+	 FIELD_PREP(MLX90394_CTRL2_INTREPB, INTREPB) |                                             \
+	 FIELD_PREP(MLX90394_CTRL2_INTB_SCL_B, INTB_SCL_B) |                                       \
+	 FIELD_PREP(MLX90394_CTRL2_INTDUR, INTDUR) | FIELD_PREP(MLX90394_CTRL2_CONFIG, CONFIG))
+#define MLX90394_CTRL2_DEFAULT                                                                     \
+	MLX90394_CTRL2_PREP(0, 0, 1, 0, MLX90394_CTRL2_CONFIG_HIGH_RANGE_LOW_NOISE)
+
+/* CTRL3 values RW */
+#define MLX90394_CTRL3_DIG_FILT_TEMP    GENMASK(2, 0)
+#define MLX90394_CTRL3_DIG_FILT_HALL_XY GENMASK(5, 3)
+#define MLX90394_CTRL3_OSR_TEMP         BIT(6)
+#define MLX90394_CTRL3_OSR_HALL         BIT(7)
+#define MLX90394_CTRL3_PREP(DIG_FILT_TEMP, DIG_FILT_HALL_XY, OSR_TEMP, OSR_HALL)                   \
+	(FIELD_PREP(MLX90394_CTRL3_DIG_FILT_TEMP, DIG_FILT_TEMP) |                                 \
+	 FIELD_PREP(MLX90394_CTRL3_DIG_FILT_HALL_XY, DIG_FILT_HALL_XY) |                           \
+	 FIELD_PREP(MLX90394_CTRL3_OSR_TEMP, OSR_TEMP) |                                           \
+	 FIELD_PREP(MLX90394_CTRL3_OSR_HALL, OSR_HALL))
+#define MLX90394_CTRL3_DEFAULT MLX90394_CTRL3_PREP(1, 4, 1, 1)
+
+/* CTRL4 values RW BIT(6) has to be always 0 so it is not included here */
+#define MLX90394_CTRL4_T_EN_BIT        5
+#define MLX90394_CTRL4_DIG_FILT_HALL_Z GENMASK(2, 0)
+#define MLX90394_CTRL4_DRDY_EN         BIT(3)
+#define MLX90394_CTRL4_T_EN            BIT(MLX90394_CTRL4_T_EN_BIT)
+#define MLX90394_CTRL4_PREP(DIG_FILT_HALL_Z, DRDY_EN, T_EN)                                        \
+	(FIELD_PREP(MLX90394_CTRL4_DIG_FILT_HALL_Z, DIG_FILT_HALL_Z) |                             \
+	 FIELD_PREP(MLX90394_CTRL4_DRDY_EN, DRDY_EN) | FIELD_PREP(MLX90394_CTRL4_T_EN, T_EN) |     \
+	 BIT(4) | BIT(7))
+#define MLX90394_CTRL4_DEFAULT MLX90394_CTRL4_PREP(5, 0, 0)
+
+/* helper function to modify only one field */
+#define MLX90394_FIELD_MOD(mask, new_field_val, val)                                               \
+	((val & ~mask) | FIELD_PREP(mask, new_field_val))
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_MLX90394_MLX90394_REG_H */
diff --git a/drivers/sensor/memsic/mmc56x3/mmc56x3_async.c b/drivers/sensor/memsic/mmc56x3/mmc56x3_async.c
index 353293d3609..63b8e931899 100644
--- a/drivers/sensor/memsic/mmc56x3/mmc56x3_async.c
+++ b/drivers/sensor/memsic/mmc56x3/mmc56x3_async.c
@@ -5,6 +5,7 @@
 
 #include <zephyr/logging/log.h>
 #include <zephyr/rtio/work.h>
+#include <zephyr/drivers/sensor_clock.h>
 
 #include "mmc56x3.h"
 
@@ -16,6 +17,7 @@ void mmc56x3_submit_sync(struct rtio_iodev_sqe *iodev_sqe)
 	int rc;
 	uint8_t *buf;
 	uint32_t buf_len;
+	uint64_t cycles;
 
 	const struct sensor_read_config *cfg = iodev_sqe->sqe.iodev->data;
 	const struct device *dev = cfg->sensor;
@@ -29,10 +31,17 @@ void mmc56x3_submit_sync(struct rtio_iodev_sqe *iodev_sqe)
 		return;
 	}
 
+	rc = sensor_clock_get_cycles(&cycles);
+	if (rc != 0) {
+		LOG_ERR("Failed to get sensor clock cycles");
+		rtio_iodev_sqe_err(iodev_sqe, rc);
+		return;
+	}
+
 	struct mmc56x3_encoded_data *edata;
 
 	edata = (struct mmc56x3_encoded_data *)buf;
-	edata->header.timestamp = k_ticks_to_ns_floor64(k_uptime_ticks());
+	edata->header.timestamp = sensor_clock_cycles_to_ns(cycles);
 	edata->has_temp = 0;
 	edata->has_magn_x = 0;
 	edata->has_magn_y = 0;
diff --git a/drivers/sensor/nordic/npm1300_charger/npm1300_charger.c b/drivers/sensor/nordic/npm1300_charger/npm1300_charger.c
index eb49859f3e8..838cb2b6734 100644
--- a/drivers/sensor/nordic/npm1300_charger/npm1300_charger.c
+++ b/drivers/sensor/nordic/npm1300_charger/npm1300_charger.c
@@ -166,7 +166,7 @@ static void calc_temp(const struct npm1300_charger_config *const config, uint16_
 static void calc_dietemp(const struct npm1300_charger_config *const config, uint16_t code,
 			 struct sensor_value *valp)
 {
-	/* Ref: Datasheet Figure 36: Die temperature (Celcius) */
+	/* Ref: Datasheet Figure 36: Die temperature (Celsius) */
 	int32_t temp =
 		DIETEMP_OFFSET_MDEGC - (((int32_t)code * DIETEMP_FACTOR_MUL) / DIETEMP_FACTOR_DIV);
 
diff --git a/drivers/sensor/nxp/fxls8974/fxls8974.c b/drivers/sensor/nxp/fxls8974/fxls8974.c
index bbe602a76d3..bb9f6d43ec4 100644
--- a/drivers/sensor/nxp/fxls8974/fxls8974.c
+++ b/drivers/sensor/nxp/fxls8974/fxls8974.c
@@ -379,9 +379,7 @@ static int fxls8974_channel_get(const struct device *dev,
 
 			val += FXLS8974_MAX_ACCEL_CHANNELS;
 
-			if (fxls8974_get_temp_data(dev, val)) {
-				return -EIO;
-			}
+			return fxls8974_get_temp_data(dev, val);
 			break;
 		case SENSOR_CHAN_ACCEL_XYZ:
 			return fxls8974_get_accel_data(dev, val, SENSOR_CHAN_ACCEL_XYZ);
@@ -401,7 +399,7 @@ static int fxls8974_channel_get(const struct device *dev,
 		return 0;
 }
 
-int fxls8974_get_active(const struct device *dev, enum fxls8974_active *active)
+int fxls8974_get_active(const struct device *dev, uint8_t *active)
 {
 		const struct fxls8974_config *cfg = dev->config;
 		uint8_t val;
@@ -417,7 +415,7 @@ int fxls8974_get_active(const struct device *dev, enum fxls8974_active *active)
 		return 0;
 }
 
-int fxls8974_set_active(const struct device *dev, enum fxls8974_active active)
+int fxls8974_set_active(const struct device *dev, uint8_t active)
 {
 		const struct fxls8974_config *cfg = dev->config;
 
@@ -493,14 +491,13 @@ static int fxls8974_init(const struct device *dev)
 			return -EIO;
 		}
 
-		if (data->whoami == WHOAMI_ID_FXLS8974) {
-			LOG_DBG("Device ID 0x%x, FXLS8974", data->whoami);
-		} else {
+		if (data->whoami != WHOAMI_ID_FXLS8964 &&
+		data->whoami != WHOAMI_ID_FXLS8974) {
 			LOG_ERR("Unknown Device ID 0x%x", data->whoami);
-			return -EIO;
+			return -ENXIO;
 		}
 
-		if (fxls8974_get_active(dev, (enum fxls8974_active *)&regVal)) {
+		if (fxls8974_get_active(dev, &regVal)) {
 			LOG_ERR("Failed to set standby mode");
 			return -EIO;
 		}
@@ -562,7 +559,7 @@ static int fxls8974_init(const struct device *dev)
 			return -EIO;
 		}
 
-		if (fxls8974_get_active(dev, (enum fxls8974_active *)&regVal)) {
+		if (fxls8974_get_active(dev, &regVal)) {
 			LOG_ERR("Failed to get active mode");
 			return -EIO;
 		}
diff --git a/drivers/sensor/nxp/fxls8974/fxls8974.h b/drivers/sensor/nxp/fxls8974/fxls8974.h
index e01cc78fe7c..01ffc4eef56 100644
--- a/drivers/sensor/nxp/fxls8974/fxls8974.h
+++ b/drivers/sensor/nxp/fxls8974/fxls8974.h
@@ -26,6 +26,7 @@
 #define FXLS8974_REG_CTRLREG4				0x18
 #define FXLS8974_REG_CTRLREG5				0x19
 
+#define WHOAMI_ID_FXLS8964				0x84
 #define WHOAMI_ID_FXLS8974				0x86
 
 #define FXLS8974_CTRLREG1_ACTIVE_MASK			0x01
@@ -155,8 +156,8 @@ struct fxls8974_data {
 #endif
 };
 
-int fxls8974_get_active(const struct device *dev, enum fxls8974_active *active);
-int fxls8974_set_active(const struct device *dev, enum fxls8974_active active);
+int fxls8974_get_active(const struct device *dev, uint8_t *active);
+int fxls8974_set_active(const struct device *dev, uint8_t active);
 
 #if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
 int fxls8974_byte_write_spi(const struct device *dev,
diff --git a/drivers/sensor/nxp/mcux_acmp/Kconfig b/drivers/sensor/nxp/mcux_acmp/Kconfig
index 1934e4d93f7..9b68edbc8ce 100644
--- a/drivers/sensor/nxp/mcux_acmp/Kconfig
+++ b/drivers/sensor/nxp/mcux_acmp/Kconfig
@@ -9,7 +9,6 @@ config SENSOR_MCUX_ACMP
 	default y
 	depends on DT_HAS_NXP_KINETIS_ACMP_ENABLED
 	select PINCTRL
-	select MCUX_ACMP
 	help
 	  Enable driver for the NXP MCUX Analog Comparator (ACMP).
 
diff --git a/drivers/sensor/pixart/CMakeLists.txt b/drivers/sensor/pixart/CMakeLists.txt
new file mode 100644
index 00000000000..73f35838608
--- /dev/null
+++ b/drivers/sensor/pixart/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Croxel Inc.
+# Copyright (c) 2025 CogniPilot Foundation
+# Copyright (c) 2025 Paul Timke <ptimkec@live.com>
+# SPDX-License-Identifier: Apache-2.0
+
+# zephyr-keep-sorted-start
+add_subdirectory_ifdef(CONFIG_PAA3905 paa3905)
+add_subdirectory_ifdef(CONFIG_PAJ7620 paj7620)
+add_subdirectory_ifdef(CONFIG_PAT9136 pat9136)
+# zephyr-keep-sorted-stop
diff --git a/drivers/sensor/pixart/Kconfig b/drivers/sensor/pixart/Kconfig
new file mode 100644
index 00000000000..14db51f6f52
--- /dev/null
+++ b/drivers/sensor/pixart/Kconfig
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Croxel Inc.
+# Copyright (c) 2025 CogniPilot Foundation
+# Copyright (c) 2025 Paul Timke <ptimkec@live.com>
+# SPDX-License-Identifier: Apache-2.0
+
+# zephyr-keep-sorted-start
+source "drivers/sensor/pixart/paa3905/Kconfig"
+source "drivers/sensor/pixart/paj7620/Kconfig"
+source "drivers/sensor/pixart/pat9136/Kconfig"
+# zephyr-keep-sorted-stop
diff --git a/drivers/sensor/pixart/paa3905/CMakeLists.txt b/drivers/sensor/pixart/paa3905/CMakeLists.txt
new file mode 100644
index 00000000000..79655203746
--- /dev/null
+++ b/drivers/sensor/pixart/paa3905/CMakeLists.txt
@@ -0,0 +1,13 @@
+# Copyright (c) 2025 Croxel Inc.
+# Copyright (c) 2025 CogniPilot Foundation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+zephyr_library_sources(
+	paa3905.c
+	paa3905_decoder.c
+)
+
+zephyr_library_sources_ifdef(CONFIG_PAA3905_STREAM
+	paa3905_stream.c
+)
diff --git a/drivers/sensor/pixart/paa3905/Kconfig b/drivers/sensor/pixart/paa3905/Kconfig
new file mode 100644
index 00000000000..201998e9b5b
--- /dev/null
+++ b/drivers/sensor/pixart/paa3905/Kconfig
@@ -0,0 +1,24 @@
+# Copyright (c) 2025 Croxel Inc.
+# Copyright (c) 2025 CogniPilot Foundation
+# SPDX-License-Identifier: Apache-2.0
+
+config PAA3905
+	bool "Optical Flow Sensor PAA3905"
+	default y
+	depends on DT_HAS_PIXART_PAA3905_ENABLED
+	select SPI
+	select SPI_RTIO
+	select SENSOR_ASYNC_API
+	help
+	  Enable driver for PAA3905 Optical Flow sensor.
+
+if PAA3905
+
+config PAA3905_STREAM
+	bool "Streaming mode"
+	depends on $(dt_compat_any_has_prop,$(DT_COMPAT_PIXART_PAA3905),int-gpios)
+	select RTIO_WORKQ
+	help
+	  Enable streaming mode for the PAA3905 sensor.
+
+endif # PAA3905
diff --git a/drivers/sensor/pixart/paa3905/paa3905.c b/drivers/sensor/pixart/paa3905/paa3905.c
new file mode 100644
index 00000000000..8b845108e6d
--- /dev/null
+++ b/drivers/sensor/pixart/paa3905/paa3905.c
@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT pixart_paa3905
+
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/rtio/rtio.h>
+
+#include "paa3905.h"
+#include "paa3905_bus.h"
+#include "paa3905_stream.h"
+#include "paa3905_decoder.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(PAA3905, CONFIG_SENSOR_LOG_LEVEL);
+
+/* Helper struct used to set reg-val sequences for op-modes */
+struct reg_val_pair {
+	uint8_t reg;
+	uint8_t val;
+};
+
+static void paa3905_complete_result(struct rtio *ctx,
+				    const struct rtio_sqe *sqe,
+				    void *arg)
+{
+	struct rtio_iodev_sqe *iodev_sqe = (struct rtio_iodev_sqe *)sqe->userdata;
+	struct rtio_cqe *cqe;
+	int err = 0;
+
+	do {
+		cqe = rtio_cqe_consume(ctx);
+		if (cqe != NULL) {
+			err = cqe->result;
+			rtio_cqe_release(ctx, cqe);
+		}
+	} while (cqe != NULL);
+
+	if (err) {
+		rtio_iodev_sqe_err(iodev_sqe, err);
+	} else {
+		rtio_iodev_sqe_ok(iodev_sqe, 0);
+	}
+
+	LOG_DBG("One-shot fetch completed");
+}
+
+static void paa3905_submit_one_shot(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
+{
+	const struct sensor_read_config *cfg = iodev_sqe->sqe.iodev->data;
+	const struct sensor_chan_spec *const channels = cfg->channels;
+	struct paa3905_data *data = dev->data;
+	const size_t num_channels = cfg->count;
+	uint32_t min_buf_len = sizeof(struct paa3905_encoded_data);
+	int err;
+	uint8_t *buf;
+	uint32_t buf_len;
+	struct paa3905_encoded_data *edata;
+
+	err = rtio_sqe_rx_buf(iodev_sqe, min_buf_len, min_buf_len, &buf, &buf_len);
+	if (err) {
+		LOG_ERR("Failed to get a read buffer of size %u bytes", min_buf_len);
+		rtio_iodev_sqe_err(iodev_sqe, err);
+		return;
+	}
+
+	edata = (struct paa3905_encoded_data *)buf;
+
+	err = paa3905_encode(dev, channels, num_channels, buf);
+	if (err != 0) {
+		LOG_ERR("Failed to encode sensor data");
+		rtio_iodev_sqe_err(iodev_sqe, err);
+		return;
+	}
+
+	struct rtio_sqe *write_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	struct rtio_sqe *read_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	struct rtio_sqe *complete_sqe = rtio_sqe_acquire(data->rtio.ctx);
+
+	if (!write_sqe || !read_sqe | !complete_sqe) {
+		LOG_ERR("Failed to acquire RTIO SQEs");
+		rtio_iodev_sqe_err(iodev_sqe, -ENOMEM);
+		return;
+	}
+
+	uint8_t val = REG_BURST_READ | REG_SPI_READ_BIT;
+
+	rtio_sqe_prep_tiny_write(write_sqe,
+				 data->rtio.iodev,
+				 RTIO_PRIO_HIGH,
+				 &val,
+				 1,
+				NULL);
+	write_sqe->flags |= RTIO_SQE_TRANSACTION;
+
+	rtio_sqe_prep_read(read_sqe,
+			   data->rtio.iodev,
+			   RTIO_PRIO_HIGH,
+			   edata->buf,
+			   sizeof(edata->buf),
+			   NULL);
+	read_sqe->flags |= RTIO_SQE_CHAINED;
+
+	rtio_sqe_prep_callback_no_cqe(complete_sqe,
+				      paa3905_complete_result,
+				      (void *)dev,
+				      iodev_sqe);
+
+	rtio_submit(data->rtio.ctx, 0);
+}
+
+static void paa3905_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
+{
+	const struct sensor_read_config *cfg = iodev_sqe->sqe.iodev->data;
+
+	if (!cfg->is_streaming) {
+		paa3905_submit_one_shot(dev, iodev_sqe);
+	} else if (IS_ENABLED(CONFIG_PAA3905_STREAM)) {
+		paa3905_stream_submit(dev, iodev_sqe);
+	} else {
+		LOG_ERR("Streaming not supported");
+		rtio_iodev_sqe_err(iodev_sqe, -ENOTSUP);
+	}
+}
+
+static DEVICE_API(sensor, paa3905_driver_api) = {
+	.submit = paa3905_submit,
+	.get_decoder = paa3905_get_decoder,
+};
+
+static int detection_mode_standard(const struct device *dev)
+{
+	int err;
+	/** As per datasheet, set of values configure the sensor in Standard mode. */
+	const static struct reg_val_pair paa3905_detection_mode_std[] = {
+		{.reg = 0x7F, .val = 0x00}, {.reg = 0x51, .val = 0xFF}, {.reg = 0x4E, .val = 0x2A},
+		{.reg = 0x66, .val = 0x3E}, {.reg = 0x7F, .val = 0x14}, {.reg = 0x7E, .val = 0x71},
+		{.reg = 0x55, .val = 0x00}, {.reg = 0x59, .val = 0x00}, {.reg = 0x6F, .val = 0x2C},
+		{.reg = 0x7F, .val = 0x05}, {.reg = 0x4D, .val = 0xAC}, {.reg = 0x4E, .val = 0x32},
+		{.reg = 0x7F, .val = 0x09}, {.reg = 0x5C, .val = 0xAF}, {.reg = 0x5F, .val = 0xAF},
+		{.reg = 0x70, .val = 0x08}, {.reg = 0x71, .val = 0x04}, {.reg = 0x72, .val = 0x06},
+		{.reg = 0x74, .val = 0x3C}, {.reg = 0x75, .val = 0x28}, {.reg = 0x76, .val = 0x20},
+		{.reg = 0x4E, .val = 0xBF}, {.reg = 0x7F, .val = 0x03}, {.reg = 0x64, .val = 0x14},
+		{.reg = 0x65, .val = 0x0A}, {.reg = 0x66, .val = 0x10}, {.reg = 0x55, .val = 0x3C},
+		{.reg = 0x56, .val = 0x28}, {.reg = 0x57, .val = 0x20}, {.reg = 0x4A, .val = 0x2D},
+		{.reg = 0x4B, .val = 0x2D}, {.reg = 0x4E, .val = 0x4B}, {.reg = 0x69, .val = 0xFA},
+		{.reg = 0x7F, .val = 0x05}, {.reg = 0x69, .val = 0x1F}, {.reg = 0x47, .val = 0x1F},
+		{.reg = 0x48, .val = 0x0C}, {.reg = 0x5A, .val = 0x20}, {.reg = 0x75, .val = 0x0F},
+		{.reg = 0x4A, .val = 0x0F}, {.reg = 0x42, .val = 0x02}, {.reg = 0x45, .val = 0x03},
+		{.reg = 0x65, .val = 0x00}, {.reg = 0x67, .val = 0x76}, {.reg = 0x68, .val = 0x76},
+		{.reg = 0x6A, .val = 0xC5}, {.reg = 0x43, .val = 0x00}, {.reg = 0x7F, .val = 0x06},
+		{.reg = 0x4A, .val = 0x18}, {.reg = 0x4B, .val = 0x0C}, {.reg = 0x4C, .val = 0x0C},
+		{.reg = 0x4D, .val = 0x0C}, {.reg = 0x46, .val = 0x0A}, {.reg = 0x59, .val = 0xCD},
+		{.reg = 0x7F, .val = 0x0A}, {.reg = 0x4A, .val = 0x2A}, {.reg = 0x48, .val = 0x96},
+		{.reg = 0x52, .val = 0xB4}, {.reg = 0x7F, .val = 0x00}, {.reg = 0x5B, .val = 0xA0},
+	};
+
+	for (size_t i = 0 ; i < ARRAY_SIZE(paa3905_detection_mode_std) ; i++) {
+		err = paa3905_bus_write(dev,
+					paa3905_detection_mode_std[i].reg,
+					&paa3905_detection_mode_std[i].val,
+					1);
+		if (err) {
+			LOG_ERR("Failed to write detection mode standard");
+			return err;
+		}
+	}
+
+	return 0;
+}
+
+static int paa3905_configure(const struct device *dev)
+{
+	const struct paa3905_config *cfg = dev->config;
+	uint8_t val;
+	int err;
+
+	/* Configure registers for Standard detection mode */
+	err = detection_mode_standard(dev);
+	if (err) {
+		LOG_ERR("Failed to configure detection mode");
+		return err;
+	}
+
+	val = cfg->resolution;
+	err = paa3905_bus_write(dev, REG_RESOLUTION, &val, 1);
+	if (err) {
+		LOG_ERR("Failed to configure resolution");
+		return err;
+	}
+
+	if (cfg->led_control) {
+		struct reg_val_pair led_control_regs[] = {
+			{.reg = 0x7F, .val = 0x14},
+			{.reg = 0x6F, .val = 0x0C},
+			{.reg = 0x7F, .val = 0x00},
+		};
+
+		for (size_t i = 0 ; i < ARRAY_SIZE(led_control_regs) ; i++) {
+			err = paa3905_bus_write(dev,
+						led_control_regs[i].reg,
+						&led_control_regs[i].val,
+						1);
+			if (err) {
+				LOG_ERR("Failed to write LED control reg");
+				return err;
+			}
+		}
+	}
+
+	return 0;
+}
+
+int paa3905_recover(const struct device *dev)
+{
+	int err;
+	uint8_t val;
+
+	/* Write 0x5A to Power up reset reg */
+	val = POWER_UP_RESET_VAL;
+	err = paa3905_bus_write(dev, REG_POWER_UP_RESET, &val, 1);
+	if (err) {
+		LOG_ERR("Failed to write Power up reset reg");
+		return err;
+	}
+	/* As per datasheet, writing power-up reset requires 1-ms afterwards. */
+	k_sleep(K_MSEC(1));
+
+	/* Configure registers for Standard detection mode */
+	err = paa3905_configure(dev);
+	if (err) {
+		LOG_ERR("Failed to configure");
+		return err;
+	}
+
+	return err;
+}
+
+static int paa3905_init(const struct device *dev)
+{
+	int err;
+	uint8_t val;
+	uint8_t motion_data[6];
+
+	/* Power-up sequence delay */
+	k_sleep(K_MSEC(140));
+
+	/* Read Product ID */
+	err = paa3905_bus_read(dev, REG_PRODUCT_ID, &val, 1);
+	if (err) {
+		LOG_ERR("Failed to read Product ID");
+		return err;
+	} else if (val != PRODUCT_ID) {
+		LOG_ERR("Invalid Product ID: 0x%02X", val);
+		return -EIO;
+	}
+
+	/* Write 0x5A to Power up reset reg */
+	val = POWER_UP_RESET_VAL;
+	err = paa3905_bus_write(dev, REG_POWER_UP_RESET, &val, 1);
+	if (err) {
+		LOG_ERR("Failed to write Power up reset reg");
+		return err;
+	}
+	/* As per datasheet, writing power-up reset requires 1-ms afterwards. */
+	k_sleep(K_MSEC(1));
+
+	/* Read reg's 0x02-0x06 to clear motion data. */
+	err = paa3905_bus_read(dev, REG_MOTION, motion_data, sizeof(motion_data));
+	if (err) {
+		LOG_ERR("Failed to read motion data");
+		return err;
+	}
+
+	if (IS_ENABLED(CONFIG_PAA3905_STREAM)) {
+		err = paa3905_stream_init(dev);
+		if (err) {
+			LOG_ERR("Failed to initialize streaming");
+			return err;
+		}
+	}
+
+	err = paa3905_configure(dev);
+	if (err) {
+		LOG_ERR("Failed to configure");
+		return err;
+	}
+
+	return 0;
+}
+
+#define PAA3905_INIT(inst)									   \
+												   \
+	BUILD_ASSERT(DT_PROP(DT_DRV_INST(inst), resolution) > 0 &&				   \
+		     DT_PROP(DT_DRV_INST(inst), resolution) <= 0xFF,				   \
+		     "Resolution must be in range 1-255");					   \
+												   \
+	RTIO_DEFINE(paa3905_rtio_ctx_##inst, 8, 8);						   \
+	SPI_DT_IODEV_DEFINE(paa3905_bus_##inst,							   \
+			    DT_DRV_INST(inst),							   \
+			    SPI_OP_MODE_MASTER | SPI_WORD_SET(8) | SPI_TRANSFER_MSB,		   \
+			    0U);								   \
+												   \
+	static const struct paa3905_config paa3905_cfg_##inst = {				   \
+		.int_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, {0}),			   \
+		.backup_timer_period = DT_PROP(DT_DRV_INST(inst), backup_timer_ms),		   \
+		.resolution = DT_PROP(DT_DRV_INST(inst), resolution),				   \
+		.led_control = DT_PROP_OR(DT_DRV_INST(inst), led_control, false),		   \
+	};											   \
+												   \
+	static struct paa3905_data paa3905_data_##inst = {					   \
+		.rtio = {									   \
+			.iodev = &paa3905_bus_##inst,						   \
+			.ctx = &paa3905_rtio_ctx_##inst,					   \
+		},										   \
+	};											   \
+												   \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst,							   \
+				     paa3905_init,						   \
+				     NULL,							   \
+				     &paa3905_data_##inst,					   \
+				     &paa3905_cfg_##inst,					   \
+				     POST_KERNEL,						   \
+				     CONFIG_SENSOR_INIT_PRIORITY,				   \
+				     &paa3905_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(PAA3905_INIT)
diff --git a/drivers/sensor/pixart/paa3905/paa3905.h b/drivers/sensor/pixart/paa3905/paa3905.h
new file mode 100644
index 00000000000..23ed177e4ea
--- /dev/null
+++ b/drivers/sensor/pixart/paa3905/paa3905.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_PAA3905_H_
+#define ZEPHYR_DRIVERS_SENSOR_PAA3905_H_
+
+#include <stdint.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/rtio/rtio.h>
+
+struct paa3905_encoded_data {
+	struct {
+		uint64_t timestamp;
+		uint8_t channels : 3;
+		struct {
+			bool drdy : 1;
+			bool motion : 1;
+		} events;
+	} header;
+	union {
+		uint8_t buf[14];
+		struct {
+			uint8_t motion;
+			uint8_t observation;
+			struct {
+				int16_t x;
+				int16_t y;
+			} delta;
+			uint8_t challenging_conditions;
+			uint8_t squal;
+			uint8_t raw_sum;
+			uint8_t raw_max;
+			uint8_t raw_min;
+			uint32_t shutter : 24;
+		} __attribute__((__packed__));
+	};
+};
+
+struct paa3905_stream {
+	struct gpio_callback cb;
+	const struct device *dev;
+	struct rtio_iodev_sqe *iodev_sqe;
+	struct k_timer timer;
+	struct {
+		struct {
+			bool drdy : 1;
+			bool motion : 1;
+		} enabled;
+		struct {
+			enum sensor_stream_data_opt drdy;
+			enum sensor_stream_data_opt motion;
+		} opt;
+	} settings;
+};
+
+struct paa3905_data {
+	struct {
+		struct rtio_iodev *iodev;
+		struct rtio *ctx;
+	} rtio;
+#if defined(CONFIG_PAA3905_STREAM)
+	struct paa3905_stream stream;
+#endif /* CONFIG_PAA3905_STREAM */
+};
+
+struct paa3905_config {
+	struct gpio_dt_spec int_gpio;
+	int resolution;
+	bool led_control;
+	uint32_t backup_timer_period;
+};
+
+/** Made public in order to perform chip recovery if erratic behavior
+ * is detected.
+ */
+int paa3905_recover(const struct device *dev);
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_PAA3905_H_ */
diff --git a/drivers/sensor/pixart/paa3905/paa3905_bus.h b/drivers/sensor/pixart/paa3905/paa3905_bus.h
new file mode 100644
index 00000000000..9b39049f97c
--- /dev/null
+++ b/drivers/sensor/pixart/paa3905/paa3905_bus.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_PAA3905_BUS_H_
+#define ZEPHYR_DRIVERS_SENSOR_PAA3905_BUS_H_
+
+#include <stdint.h>
+#include <zephyr/rtio/rtio.h>
+
+#include "paa3905.h"
+#include "paa3905_reg.h"
+
+static inline int paa3905_bus_read(const struct device *dev,
+				   uint8_t reg,
+				   uint8_t *buf,
+				   uint16_t len)
+{
+	struct paa3905_data *data = dev->data;
+	struct rtio *ctx = data->rtio.ctx;
+	struct rtio_iodev *iodev = data->rtio.iodev;
+	struct rtio_sqe *write_sqe = rtio_sqe_acquire(ctx);
+	struct rtio_sqe *read_sqe = rtio_sqe_acquire(ctx);
+	struct rtio_cqe *cqe;
+	int err;
+
+	if (!write_sqe || !read_sqe) {
+		return -ENOMEM;
+	}
+
+	reg = reg | REG_SPI_READ_BIT;
+
+	rtio_sqe_prep_write(write_sqe, iodev, RTIO_PRIO_HIGH, &reg, 1, NULL);
+	write_sqe->flags |= RTIO_SQE_TRANSACTION;
+	rtio_sqe_prep_read(read_sqe, iodev, RTIO_PRIO_HIGH, buf, len, NULL);
+
+	err = rtio_submit(ctx, 2);
+	if (err) {
+		return err;
+	}
+
+	do {
+		cqe = rtio_cqe_consume(ctx);
+		if (cqe != NULL) {
+			err = cqe->result;
+			rtio_cqe_release(ctx, cqe);
+		}
+	} while (cqe != NULL);
+
+	return err;
+}
+
+static inline int paa3905_bus_write(const struct device *dev,
+				    uint8_t reg,
+				    const uint8_t *buf,
+				    uint16_t len)
+{
+	struct paa3905_data *data = dev->data;
+	struct rtio *ctx = data->rtio.ctx;
+	struct rtio_iodev *iodev = data->rtio.iodev;
+	struct rtio_sqe *write_reg_sqe = rtio_sqe_acquire(ctx);
+	struct rtio_sqe *write_buf_sqe = rtio_sqe_acquire(ctx);
+	struct rtio_cqe *cqe;
+	int err;
+
+	if (!write_reg_sqe || !write_buf_sqe) {
+		return -ENOMEM;
+	}
+
+	reg = reg | REG_SPI_WRITE_BIT;
+
+	rtio_sqe_prep_write(write_reg_sqe, iodev, RTIO_PRIO_HIGH, &reg, 1, NULL);
+	write_reg_sqe->flags |= RTIO_SQE_TRANSACTION;
+	rtio_sqe_prep_write(write_buf_sqe, iodev, RTIO_PRIO_HIGH, buf, len, NULL);
+
+	err = rtio_submit(ctx, 2);
+	if (err) {
+		return err;
+	}
+
+	do {
+		cqe = rtio_cqe_consume(ctx);
+		if (cqe != NULL) {
+			err = cqe->result;
+			rtio_cqe_release(ctx, cqe);
+		}
+	} while (cqe != NULL);
+
+	return err;
+}
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_PAA3905_BUS_H_ */
diff --git a/drivers/sensor/pixart/paa3905/paa3905_decoder.c b/drivers/sensor/pixart/paa3905/paa3905_decoder.c
new file mode 100644
index 00000000000..9ef3beb4631
--- /dev/null
+++ b/drivers/sensor/pixart/paa3905/paa3905_decoder.c
@@ -0,0 +1,252 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/sensor_clock.h>
+#include <zephyr/sys/byteorder.h>
+
+#include "paa3905.h"
+#include "paa3905_reg.h"
+#include "paa3905_decoder.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(PAA3905_DECODER, CONFIG_SENSOR_LOG_LEVEL);
+
+#define DT_DRV_COMPAT pixart_paa3905
+
+uint8_t paa3905_encode_channel(enum sensor_channel chan)
+{
+	switch (chan) {
+	case SENSOR_CHAN_POS_DX:
+		return BIT(0);
+	case SENSOR_CHAN_POS_DY:
+		return BIT(1);
+	case SENSOR_CHAN_POS_DXYZ:
+		return BIT(2);
+	default:
+		return 0;
+	}
+}
+
+static bool is_data_valid(const struct paa3905_encoded_data *edata)
+{
+	uint8_t squal_min;
+	uint32_t shutter_max;
+	uint32_t shutter;
+
+	if (!REG_MOTION_DETECTED(edata->motion)) {
+		LOG_WRN("Invalid data - No motion detected");
+		return false;
+	}
+
+	if (REG_MOTION_CHALLENGING_COND(edata->motion)) {
+		LOG_WRN("Invalid data - Challenging conditions");
+		return false;
+	}
+
+	switch (REG_OBSERVATION_MODE(edata->observation)) {
+	case OBSERVATION_MODE_BRIGHT:
+		squal_min = SQUAL_MIN_BRIGHT;
+		shutter_max = SHUTTER_MAX_BRIGHT;
+		break;
+	case OBSERVATION_MODE_LOW_LIGHT:
+		squal_min = SQUAL_MIN_LOW_LIGHT;
+		shutter_max = SHUTTER_MAX_LOW_LIGHT;
+		break;
+	case OBSERVATION_MODE_SUPER_LOW_LIGHT:
+		squal_min = SQUAL_MIN_SUPER_LOW_LIGHT;
+		shutter_max = SHUTTER_MAX_SUPER_LOW_LIGHT;
+		break;
+	default:
+		LOG_ERR("Invalid op mode");
+		return false;
+	}
+
+	shutter = sys_be24_to_cpu(edata->shutter);
+
+	if (edata->squal < squal_min || shutter >= shutter_max) {
+		LOG_WRN("Invalid data - mode: %d squal: 0x%02X shutter: 0x%06X",
+			(uint8_t)REG_OBSERVATION_MODE(edata->observation), edata->squal, shutter);
+
+		return false;
+	}
+
+	return true;
+}
+
+static int paa3905_decoder_get_frame_count(const uint8_t *buffer,
+					   struct sensor_chan_spec chan_spec,
+					   uint16_t *frame_count)
+{
+	struct paa3905_encoded_data *edata = (struct paa3905_encoded_data *)buffer;
+
+	if (chan_spec.chan_idx != 0) {
+		return -ENOTSUP;
+	}
+
+	uint8_t channel_request = paa3905_encode_channel(chan_spec.chan_type);
+
+	if (((edata->header.channels & channel_request) != channel_request) ||
+	    !is_data_valid(edata)) {
+		return -ENODATA;
+	}
+
+	switch (chan_spec.chan_type) {
+	case SENSOR_CHAN_POS_DX:
+	case SENSOR_CHAN_POS_DY:
+	case SENSOR_CHAN_POS_DXYZ:
+		*frame_count = 1;
+		return 0;
+	default:
+		return -ENOTSUP;
+	}
+
+	return -1;
+}
+
+static int paa3905_decoder_get_size_info(struct sensor_chan_spec chan_spec,
+					 size_t *base_size,
+					 size_t *frame_size)
+{
+	switch (chan_spec.chan_type) {
+	case SENSOR_CHAN_POS_DX:
+	case SENSOR_CHAN_POS_DY:
+		*base_size = sizeof(struct sensor_q31_data);
+		*frame_size = sizeof(struct sensor_q31_sample_data);
+		return 0;
+	case SENSOR_CHAN_POS_DXYZ:
+		*base_size = sizeof(struct sensor_three_axis_data);
+		*frame_size = sizeof(struct sensor_three_axis_data);
+		return 0;
+	default:
+		return -ENOTSUP;
+	}
+}
+
+static int paa3905_decoder_decode(const uint8_t *buffer,
+				  struct sensor_chan_spec chan_spec,
+				  uint32_t *fit,
+				  uint16_t max_count,
+				  void *data_out)
+{
+	struct paa3905_encoded_data *edata = (struct paa3905_encoded_data *)buffer;
+	uint8_t channel_request;
+
+	if (*fit != 0) {
+		return 0;
+	}
+
+	if (max_count == 0 || chan_spec.chan_idx != 0) {
+		return -EINVAL;
+	}
+
+	switch (chan_spec.chan_type) {
+	case SENSOR_CHAN_POS_DX:
+	case SENSOR_CHAN_POS_DY: {
+		channel_request = paa3905_encode_channel(chan_spec.chan_type);
+		if (((edata->header.channels & channel_request) != channel_request) ||
+		    !is_data_valid(edata)) {
+			LOG_ERR("No data available");
+			return -ENODATA;
+		}
+
+		struct sensor_q31_data *out = (struct sensor_q31_data *)data_out;
+
+		out->header.base_timestamp_ns = edata->header.timestamp;
+		out->header.reading_count = 1;
+		out->shift = 31;
+
+		out->readings->value = (chan_spec.chan_type == SENSOR_CHAN_POS_DX) ?
+				       edata->delta.x :
+				       edata->delta.y;
+
+		*fit = 1;
+		return 1;
+	}
+	case SENSOR_CHAN_POS_DXYZ: {
+		channel_request = paa3905_encode_channel(chan_spec.chan_type);
+		if (((edata->header.channels & channel_request) != channel_request) ||
+		    !is_data_valid(edata)) {
+			LOG_ERR("No data available");
+			return -ENODATA;
+		}
+
+		struct sensor_three_axis_data *out = (struct sensor_three_axis_data *)data_out;
+
+		out->header.base_timestamp_ns = edata->header.timestamp;
+		out->header.reading_count = 1;
+		out->shift = 31;
+
+		out->readings[0].x = edata->delta.x;
+		out->readings[0].y = edata->delta.y;
+		out->readings[0].z = 0;
+
+		*fit = 1;
+		return 1;
+	}
+	default:
+		return -EINVAL;
+	}
+
+	return -1;
+}
+
+static bool paa3905_decoder_has_trigger(const uint8_t *buffer, enum sensor_trigger_type trigger)
+{
+	struct paa3905_encoded_data *edata = (struct paa3905_encoded_data *)buffer;
+
+	switch (trigger) {
+	case SENSOR_TRIG_DATA_READY:
+		return edata->header.events.drdy;
+	case SENSOR_TRIG_MOTION:
+		return edata->header.events.motion;
+	default:
+		return false;
+	}
+}
+
+SENSOR_DECODER_API_DT_DEFINE() = {
+	.get_frame_count = paa3905_decoder_get_frame_count,
+	.get_size_info = paa3905_decoder_get_size_info,
+	.decode = paa3905_decoder_decode,
+	.has_trigger = paa3905_decoder_has_trigger,
+};
+
+int paa3905_get_decoder(const struct device *dev,
+	const struct sensor_decoder_api **decoder)
+{
+	ARG_UNUSED(dev);
+	*decoder = &SENSOR_DECODER_NAME();
+
+	return 0;
+}
+
+int paa3905_encode(const struct device *dev,
+		   const struct sensor_chan_spec *const channels,
+		   size_t num_channels,
+		   uint8_t *buf)
+{
+	struct paa3905_encoded_data *edata = (struct paa3905_encoded_data *)buf;
+	uint64_t cycles;
+	int err;
+
+	edata->header.channels = 0;
+	edata->header.events.drdy = false;
+	edata->header.events.motion = false;
+
+	for (size_t i = 0 ; i < num_channels; i++) {
+		edata->header.channels |= paa3905_encode_channel(channels[i].chan_type);
+	}
+
+	err = sensor_clock_get_cycles(&cycles);
+	if (err != 0) {
+		return err;
+	}
+
+	edata->header.timestamp = sensor_clock_cycles_to_ns(cycles);
+
+	return 0;
+}
diff --git a/drivers/sensor/pixart/paa3905/paa3905_decoder.h b/drivers/sensor/pixart/paa3905/paa3905_decoder.h
new file mode 100644
index 00000000000..c010368893f
--- /dev/null
+++ b/drivers/sensor/pixart/paa3905/paa3905_decoder.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_PAA3905_DECODER_H_
+#define ZEPHYR_DRIVERS_SENSOR_PAA3905_DECODER_H_
+
+#include <stdint.h>
+#include <zephyr/drivers/sensor.h>
+#include "paa3905.h"
+
+int paa3905_encode(const struct device *dev,
+		   const struct sensor_chan_spec *const channels,
+		   size_t num_channels,
+		   uint8_t *buf);
+
+uint8_t paa3905_encode_channel(enum sensor_channel chan);
+
+int paa3905_get_decoder(const struct device *dev,
+			const struct sensor_decoder_api **decoder);
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_PAA3905_DECODER_H_ */
diff --git a/drivers/sensor/pixart/paa3905/paa3905_reg.h b/drivers/sensor/pixart/paa3905/paa3905_reg.h
new file mode 100644
index 00000000000..7cd1333a246
--- /dev/null
+++ b/drivers/sensor/pixart/paa3905/paa3905_reg.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_PAA3905_REG_H_
+#define ZEPHYR_DRIVERS_SENSOR_PAA3905_REG_H_
+
+#define REG_SPI_READ_BIT			0
+#define REG_SPI_WRITE_BIT			BIT(7)
+
+/* Registers */
+#define REG_PRODUCT_ID				0x00
+#define REG_MOTION				0x02
+#define REG_DELTA_X_L				0x03
+#define REG_DELTA_X_H				0x04
+#define REG_DELTA_Y_L				0x05
+#define REG_DELTA_Y_H				0x06
+#define REG_BURST_READ				0x16
+#define REG_POWER_UP_RESET			0x3A
+#define REG_RESOLUTION				0x4E
+
+/* Misc. Defines */
+#define PRODUCT_ID				0xA2
+#define POWER_UP_RESET_VAL			0x5A
+
+#define REG_MOTION_DETECTED(val)		((val) & BIT(7))
+#define REG_MOTION_CHALLENGING_COND(val)	((val) & BIT(0))
+
+#define REG_OBSERVATION_MODE(val)		(((val) & (BIT(7) | BIT(6))) >> 6)
+#define REG_OBSERVATION_CHIP_OK(val)		(((val) & BIT_MASK(6)) == 0x3F)
+
+#define OBSERVATION_MODE_BRIGHT			0
+#define OBSERVATION_MODE_LOW_LIGHT		1
+#define OBSERVATION_MODE_SUPER_LOW_LIGHT	2
+
+/* Data validation boundaries */
+#define SQUAL_MIN_BRIGHT			0x19
+#define SHUTTER_MAX_BRIGHT			0x00FF80
+
+#define SQUAL_MIN_LOW_LIGHT			0x46
+#define SHUTTER_MAX_LOW_LIGHT			0x00FF80
+
+#define SQUAL_MIN_SUPER_LOW_LIGHT		0x55
+#define SHUTTER_MAX_SUPER_LOW_LIGHT		0x025998
+
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_PAA3905_REG_H_ */
diff --git a/drivers/sensor/pixart/paa3905/paa3905_stream.c b/drivers/sensor/pixart/paa3905/paa3905_stream.c
new file mode 100644
index 00000000000..d888be1c6dc
--- /dev/null
+++ b/drivers/sensor/pixart/paa3905/paa3905_stream.c
@@ -0,0 +1,356 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/sensor_clock.h>
+#include <zephyr/sys/check.h>
+#include <zephyr/rtio/rtio.h>
+#include <zephyr/rtio/work.h>
+
+#include "paa3905.h"
+#include "paa3905_reg.h"
+#include "paa3905_stream.h"
+#include "paa3905_decoder.h"
+#include "paa3905_bus.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(PAA3905_STREAM, CONFIG_SENSOR_LOG_LEVEL);
+
+static void paa3905_chip_recovery_handler(struct rtio_iodev_sqe *iodev_sqe)
+{
+	const struct sensor_read_config *cfg = iodev_sqe->sqe.iodev->data;
+	const struct device *dev = cfg->sensor;
+	int err;
+
+	err = paa3905_recover(dev);
+
+	if (err) {
+		rtio_iodev_sqe_err(iodev_sqe, err);
+	} else {
+		rtio_iodev_sqe_ok(iodev_sqe, 0);
+	}
+}
+
+static void start_drdy_backup_timer(const struct device *dev)
+{
+	struct paa3905_data *data = dev->data;
+	const struct paa3905_config *cfg = dev->config;
+
+	k_timer_start(&data->stream.timer,
+		      K_MSEC(cfg->backup_timer_period),
+		      K_NO_WAIT);
+}
+
+static void paa3905_complete_result(struct rtio *ctx,
+				    const struct rtio_sqe *sqe,
+				    void *arg)
+{
+	const struct device *dev = (const struct device *)arg;
+	struct paa3905_data *data = dev->data;
+	struct rtio_iodev_sqe *iodev_sqe = data->stream.iodev_sqe;
+	struct paa3905_encoded_data *edata = sqe->userdata;
+	struct rtio_cqe *cqe;
+	int err;
+
+	edata->header.events.drdy = true &&
+				    data->stream.settings.enabled.drdy;
+	edata->header.events.motion = REG_MOTION_DETECTED(edata->motion) &&
+				      data->stream.settings.enabled.motion;
+	edata->header.channels = 0;
+
+	if ((data->stream.settings.enabled.drdy &&
+	      data->stream.settings.opt.drdy == SENSOR_STREAM_DATA_INCLUDE) ||
+	    (data->stream.settings.enabled.motion &&
+	      data->stream.settings.opt.motion == SENSOR_STREAM_DATA_INCLUDE)) {
+		edata->header.channels |= paa3905_encode_channel(SENSOR_CHAN_POS_DXYZ);
+	}
+
+	if (data->stream.settings.enabled.drdy) {
+		start_drdy_backup_timer(dev);
+	}
+
+	/** Attempt chip recovery if erratic behavior is detected  */
+	if (!REG_OBSERVATION_CHIP_OK(edata->observation)) {
+
+		LOG_WRN("CHIP OK register indicates issues. Attempting chip recovery");
+		struct rtio_work_req *req = rtio_work_req_alloc();
+
+		CHECKIF(!req) {
+			LOG_ERR("Failed to allocate RTIO work request");
+			rtio_iodev_sqe_err(iodev_sqe, -ENOMEM);
+			return;
+		}
+
+		rtio_work_req_submit(req, iodev_sqe, paa3905_chip_recovery_handler);
+	} else {
+		rtio_iodev_sqe_ok(iodev_sqe, 0);
+	}
+
+	/* Flush RTIO bus CQEs */
+	do {
+		cqe = rtio_cqe_consume(ctx);
+		if (cqe != NULL) {
+			err = cqe->result;
+			rtio_cqe_release(ctx, cqe);
+		}
+	} while (cqe != NULL);
+}
+
+static void paa3905_stream_get_data(const struct device *dev)
+{
+	struct paa3905_data *data = dev->data;
+	uint64_t cycles;
+	int err;
+
+	CHECKIF(!data->stream.iodev_sqe) {
+		LOG_WRN("No RTIO submission with an INT GPIO event");
+		return;
+	}
+
+	struct paa3905_encoded_data *buf;
+	uint32_t buf_len;
+	uint32_t buf_len_required = sizeof(struct paa3905_encoded_data);
+
+	err = rtio_sqe_rx_buf(data->stream.iodev_sqe,
+			      buf_len_required,
+			      buf_len_required,
+			      (uint8_t **)&buf,
+			      &buf_len);
+	__ASSERT(err == 0, "Failed to acquire buffer (len: %d) for encoded data: %d. "
+			   "Please revisit RTIO queue sizing and look for "
+			   "bottlenecks during sensor data processing",
+			   buf_len_required, err);
+
+	/** Still throw an error even if asserts are off */
+	if (err) {
+		struct rtio_iodev_sqe *iodev_sqe = data->stream.iodev_sqe;
+
+		LOG_ERR("Failed to acquire buffer for encoded data: %d", err);
+
+		data->stream.iodev_sqe = NULL;
+		rtio_iodev_sqe_err(iodev_sqe, err);
+		return;
+	}
+
+	struct rtio_sqe *write_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	struct rtio_sqe *read_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	struct rtio_sqe *cb_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	uint8_t val;
+
+	err = sensor_clock_get_cycles(&cycles);
+	CHECKIF(err) {
+		struct rtio_iodev_sqe *iodev_sqe = data->stream.iodev_sqe;
+
+		LOG_ERR("Failed to get timestamp: %d", err);
+
+		data->stream.iodev_sqe = NULL;
+		rtio_iodev_sqe_err(iodev_sqe, err);
+		return;
+	}
+	buf->header.timestamp = sensor_clock_cycles_to_ns(cycles);
+
+	CHECKIF(!write_sqe || !read_sqe || !cb_sqe) {
+		LOG_ERR("Failed to acquire RTIO SQE's");
+		rtio_iodev_sqe_err(data->stream.iodev_sqe, -ENOMEM);
+		return;
+	}
+
+	val = REG_BURST_READ | REG_SPI_READ_BIT;
+
+	rtio_sqe_prep_tiny_write(write_sqe,
+				 data->rtio.iodev,
+				 RTIO_PRIO_HIGH,
+				 &val,
+				 1,
+				 NULL);
+	write_sqe->flags |= RTIO_SQE_TRANSACTION;
+
+	rtio_sqe_prep_read(read_sqe,
+			   data->rtio.iodev,
+			   RTIO_PRIO_HIGH,
+			   buf->buf,
+			   sizeof(buf->buf),
+			   NULL);
+	read_sqe->flags |= RTIO_SQE_CHAINED;
+
+	rtio_sqe_prep_callback_no_cqe(cb_sqe,
+				      paa3905_complete_result,
+				      (void *)dev,
+				      buf);
+
+	rtio_submit(data->rtio.ctx, 0);
+}
+
+static void paa3905_gpio_callback(const struct device *gpio_dev,
+				  struct gpio_callback *cb,
+				  uint32_t pins)
+{
+	struct paa3905_stream *stream = CONTAINER_OF(cb,
+						     struct paa3905_stream,
+						     cb);
+	const struct device *dev = stream->dev;
+	const struct paa3905_config *cfg = dev->config;
+	int err;
+
+	/* Disable interrupts */
+	err = gpio_pin_interrupt_configure_dt(&cfg->int_gpio,
+					      GPIO_INT_MODE_DISABLED);
+	if (err) {
+		LOG_ERR("Failed to disable interrupt");
+		return;
+	}
+
+	paa3905_stream_get_data(dev);
+}
+
+static void paa3905_stream_drdy_timeout(struct k_timer *timer)
+{
+	struct paa3905_stream *stream = CONTAINER_OF(timer,
+						     struct paa3905_stream,
+						     timer);
+	const struct device *dev = stream->dev;
+	const struct paa3905_config *cfg = dev->config;
+	int err;
+
+	/* Disable interrupts */
+	err = gpio_pin_interrupt_configure_dt(&cfg->int_gpio,
+					      GPIO_INT_MODE_DISABLED);
+	if (err) {
+		LOG_ERR("Failed to disable interrupt");
+		return;
+	}
+
+	paa3905_stream_get_data(dev);
+}
+
+static inline bool settings_changed(const struct paa3905_stream *a,
+				    const struct paa3905_stream *b)
+{
+	return (a->settings.enabled.drdy != b->settings.enabled.drdy) ||
+	       (a->settings.opt.drdy != b->settings.opt.drdy) ||
+	       (a->settings.enabled.motion != b->settings.enabled.motion) ||
+	       (a->settings.opt.motion != b->settings.opt.motion);
+}
+
+void paa3905_stream_submit(const struct device *dev,
+			   struct rtio_iodev_sqe *iodev_sqe)
+{
+	const struct sensor_read_config *read_config = iodev_sqe->sqe.iodev->data;
+	struct paa3905_data *data = dev->data;
+	const struct paa3905_config *cfg = dev->config;
+	int err;
+
+	/** This separate struct is required due to the streaming API using a
+	 * multi-shot RTIO submission: meaning, re-submitting itself after
+	 * completion; hence, we don't have context to determine if this was
+	 * the first submission that kicked things off. We're then, inferring
+	 * this by comparing if the read-config has changed, and only restart
+	 * in such case.
+	 */
+	struct paa3905_stream stream = {0};
+
+	for (size_t i = 0 ; i < read_config->count ; i++) {
+		switch (read_config->channels[i].chan_type) {
+		case SENSOR_TRIG_DATA_READY:
+			stream.settings.enabled.drdy = true;
+			stream.settings.opt.drdy = read_config->triggers[i].opt;
+			break;
+		case SENSOR_TRIG_MOTION:
+			stream.settings.enabled.motion = true;
+			stream.settings.opt.motion = read_config->triggers[i].opt;
+			break;
+		default:
+			LOG_ERR("Unsupported trigger (%d)", read_config->triggers[i].trigger);
+			rtio_iodev_sqe_err(iodev_sqe, -ENOTSUP);
+			return;
+		}
+	}
+
+	/* Store context for next submission (handled within callbacks) */
+	data->stream.iodev_sqe = iodev_sqe;
+
+	if (settings_changed(&data->stream, &stream)) {
+		uint8_t motion_data[6];
+
+		data->stream.settings = stream.settings;
+
+		/* Disable interrupts */
+		err = gpio_pin_interrupt_configure_dt(&cfg->int_gpio,
+						      GPIO_INT_MODE_DISABLED);
+		if (err) {
+			LOG_ERR("Failed to disable interrupt");
+			rtio_iodev_sqe_err(iodev_sqe, err);
+			return;
+		}
+
+		/* Read reg's 0x02-0x06 to clear motion data. */
+		err = paa3905_bus_read(dev, REG_MOTION, motion_data, sizeof(motion_data));
+		if (err) {
+			LOG_ERR("Failed to read motion data");
+			rtio_iodev_sqe_err(iodev_sqe, err);
+			return;
+		}
+	}
+
+	/* Re-enable interrupts */
+	err = gpio_pin_interrupt_configure_dt(&cfg->int_gpio,
+						GPIO_INT_LEVEL_ACTIVE);
+	if (err) {
+		LOG_ERR("Failed to enable interrupt");
+		rtio_iodev_sqe_err(iodev_sqe, err);
+		return;
+	}
+
+	/** Back-up timer allows us to keep checking in with the sensor in
+	 * spite of not having any motion. This results in allowing sensor
+	 * recovery if falling in erratic state.
+	 */
+	if (data->stream.settings.enabled.drdy) {
+		start_drdy_backup_timer(dev);
+	}
+}
+
+int paa3905_stream_init(const struct device *dev)
+{
+	const struct paa3905_config *cfg = dev->config;
+	struct paa3905_data *data = dev->data;
+	int err;
+
+	/** Needed to get back the device handle from the callback context */
+	data->stream.dev = dev;
+
+	if (!cfg->int_gpio.port) {
+		LOG_ERR("Interrupt GPIO not supplied");
+		return -ENODEV;
+	}
+
+	if (!gpio_is_ready_dt(&cfg->int_gpio)) {
+		LOG_ERR("Interrupt GPIO not ready");
+		return -ENODEV;
+	}
+
+	err = gpio_pin_configure_dt(&cfg->int_gpio, GPIO_INPUT);
+	if (err) {
+		LOG_ERR("Failed to configure interrupt GPIO");
+		return -EIO;
+	}
+
+	gpio_init_callback(&data->stream.cb,
+			   paa3905_gpio_callback,
+			   BIT(cfg->int_gpio.pin));
+
+	err = gpio_add_callback(cfg->int_gpio.port, &data->stream.cb);
+	if (err) {
+		LOG_ERR("Failed to add interrupt callback");
+		return -EIO;
+	}
+
+	k_timer_init(&data->stream.timer, paa3905_stream_drdy_timeout, NULL);
+
+	return err;
+}
diff --git a/drivers/sensor/pixart/paa3905/paa3905_stream.h b/drivers/sensor/pixart/paa3905/paa3905_stream.h
new file mode 100644
index 00000000000..5eb36be9713
--- /dev/null
+++ b/drivers/sensor/pixart/paa3905/paa3905_stream.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/rtio/rtio.h>
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_PAA3905_STREAM_H_
+#define ZEPHYR_DRIVERS_SENSOR_PAA3905_STREAM_H_
+
+int paa3905_stream_init(const struct device *dev);
+
+void paa3905_stream_submit(const struct device *dev,
+			   struct rtio_iodev_sqe *iodev_sqe);
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_PAA3905_STREAM_H_ */
diff --git a/drivers/sensor/pixart/paj7620/CMakeLists.txt b/drivers/sensor/pixart/paj7620/CMakeLists.txt
new file mode 100644
index 00000000000..b115ffef01c
--- /dev/null
+++ b/drivers/sensor/pixart/paj7620/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright (c) 2025 Paul Timke <ptimkec@live.com>
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(paj7620.c)
+zephyr_library_sources_ifdef(CONFIG_PAJ7620_TRIGGER paj7620_trigger.c)
diff --git a/drivers/sensor/pixart/paj7620/Kconfig b/drivers/sensor/pixart/paj7620/Kconfig
new file mode 100644
index 00000000000..6dca4e7ab15
--- /dev/null
+++ b/drivers/sensor/pixart/paj7620/Kconfig
@@ -0,0 +1,21 @@
+# PAJ7620 gesture sensor configuration options
+
+# Copyright (c) 2025 Paul Timke <ptimkec@live.com>
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig PAJ7620
+	bool "PAJ7620 gesture sensor driver"
+	default y
+	depends on DT_HAS_PIXART_PAJ7620_ENABLED
+	select I2C
+	help
+	  Enable driver for the PAJ7620 gesture sensor
+
+if PAJ7620
+
+module = PAJ7620
+thread_priority = 10
+thread_stack_size = 1024
+source "drivers/sensor/Kconfig.trigger_template"
+
+endif # PAJ7620
diff --git a/drivers/sensor/pixart/paj7620/paj7620.c b/drivers/sensor/pixart/paj7620/paj7620.c
new file mode 100644
index 00000000000..d729fe75bf9
--- /dev/null
+++ b/drivers/sensor/pixart/paj7620/paj7620.c
@@ -0,0 +1,295 @@
+/*
+ * Copyright (c) 2025 Paul Timke <ptimkec@live.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT pixart_paj7620
+
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/sensor/paj7620.h>
+
+#include "paj7620.h"
+#include "paj7620_reg.h"
+
+LOG_MODULE_REGISTER(paj7620, CONFIG_SENSOR_LOG_LEVEL);
+
+static int paj7620_select_register_bank(const struct device *dev, enum paj7620_mem_bank bank)
+{
+	int ret;
+	uint8_t bank_selection;
+	const struct paj7620_config *config = dev->config;
+
+	switch (bank) {
+	case PAJ7620_MEMBANK_0:
+		bank_selection = PAJ7620_VAL_BANK_SEL_BANK_0;
+		break;
+	case PAJ7620_MEMBANK_1:
+		bank_selection = PAJ7620_VAL_BANK_SEL_BANK_1;
+		break;
+	default:
+		LOG_ERR("Nonexistent memory bank %d", (int)bank);
+		return -EINVAL;
+	}
+
+	ret = i2c_reg_write_byte_dt(&config->i2c, PAJ7620_REG_BANK_SEL, bank_selection);
+	if (ret < 0) {
+		LOG_ERR("Failed to change memory bank");
+		return ret;
+	}
+
+	return 0;
+}
+
+static int paj7620_get_hw_id(const struct device *dev, uint16_t *result)
+{
+	uint8_t ret;
+	uint8_t hw_id[2];
+	const struct paj7620_config *config = dev->config;
+
+	/* Part ID is stored in bank 0 */
+	ret = paj7620_select_register_bank(dev, PAJ7620_MEMBANK_0);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = i2c_reg_read_byte_dt(&config->i2c, PAJ7620_REG_PART_ID_LSB, &hw_id[0]);
+	if (ret < 0) {
+		LOG_ERR("Failed to read hardware ID");
+		return ret;
+	}
+
+	ret = i2c_reg_read_byte_dt(&config->i2c, PAJ7620_REG_PART_ID_MSB, &hw_id[1]);
+	if (ret < 0) {
+		LOG_ERR("Failed to read hardware ID");
+		return ret;
+	}
+
+	*result = sys_get_le16(hw_id);
+	LOG_DBG("Obtained hardware ID 0x%04x", *result);
+
+	return 0;
+}
+
+static int paj7620_write_initial_reg_settings(const struct device *dev)
+{
+	int ret;
+	uint8_t reg_addr;
+	uint8_t value;
+	const struct paj7620_config *config = dev->config;
+
+	/**
+	 * Initializes registers with default values according to section 8.1
+	 * from Datasheet v1.5:
+	 * https://files.seeedstudio.com/wiki/Grove_Gesture_V_1.0/res/PAJ7620U2_DS_v1.5_05012022_Confidential.pdf
+	 */
+
+	for (int i = 0; i < ARRAY_SIZE(initial_register_array); i++) {
+		reg_addr = initial_register_array[i][0];
+		value = initial_register_array[i][1];
+
+		ret = i2c_reg_write_byte_dt(&config->i2c, reg_addr, value);
+		if (ret < 0) {
+			return ret;
+		}
+	}
+
+	return ret;
+}
+
+static int paj7620_set_sampling_rate(const struct device *dev, const struct sensor_value *val)
+{
+	int ret;
+	int fps;
+	const struct paj7620_config *config = dev->config;
+	int64_t uval = val->val1 * 1000000 + val->val2;
+
+	if (uval <= 120000000) {
+		fps = PAJ7620_NORMAL_SPEED;
+	} else if (uval <= 240000000) {
+		fps = PAJ7620_GAME_SPEED;
+	} else {
+		LOG_ERR("Unsupported sample rate");
+		return -ENOTSUP;
+	}
+
+	ret = paj7620_select_register_bank(dev, PAJ7620_MEMBANK_1);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = i2c_reg_write_byte_dt(&config->i2c, PAJ7620_REG_R_IDLE_TIME_LSB, fps);
+	if (ret < 0) {
+		LOG_ERR("Failed to set sample rate");
+		return ret;
+	}
+
+	ret = paj7620_select_register_bank(dev, PAJ7620_MEMBANK_0);
+	if (ret < 0) {
+		return ret;
+	}
+
+	LOG_DBG("Sample rate set to %s mode", fps == PAJ7620_GAME_SPEED ? "game" : "normal");
+
+	return 0;
+}
+
+static int paj7620_sample_fetch(const struct device *dev, enum sensor_channel chan)
+{
+	int ret;
+	struct paj7620_data *data = dev->data;
+	const struct paj7620_config *config = dev->config;
+	uint8_t gest_data[2];
+
+	if (chan != SENSOR_CHAN_ALL
+		&& ((enum sensor_channel_paj7620)chan != SENSOR_CHAN_PAJ7620_GESTURES)) {
+		return -ENOTSUP;
+	}
+
+	/* We read from REG_INT_FLAG_1 and REG_INT_FLAG_2 even on polling mode
+	 * (without using interrupts) because that's where the gesture
+	 * detection flags are set.
+	 * NOTE: A set bit means that the corresponding gesture has been detected
+	 */
+
+	ret = i2c_burst_read_dt(&config->i2c, PAJ7620_REG_INT_FLAG_1, gest_data, sizeof(gest_data));
+	if (ret < 0) {
+		LOG_ERR("Failed to read gesture data");
+		return ret;
+	}
+
+	data->gesture_flags = sys_get_le16(gest_data);
+
+	return 0;
+}
+
+static int paj7620_channel_get(const struct device *dev,
+				enum sensor_channel chan,
+				struct sensor_value *val)
+{
+	struct paj7620_data *data = dev->data;
+
+	switch ((uint32_t)chan) {
+	case SENSOR_CHAN_PAJ7620_GESTURES:
+		val->val1 = data->gesture_flags;
+		val->val2 = 0;
+		break;
+	default:
+		LOG_ERR("Unsupported sensor channel");
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static int paj7620_attr_set(const struct device *dev,
+			    enum sensor_channel chan,
+			    enum sensor_attribute attr,
+			    const struct sensor_value *val)
+{
+	int ret;
+
+	if (chan != SENSOR_CHAN_ALL
+		&& ((enum sensor_channel_paj7620)chan != SENSOR_CHAN_PAJ7620_GESTURES)) {
+		return -ENOTSUP;
+	}
+
+	switch ((uint32_t)attr) {
+	case SENSOR_ATTR_SAMPLING_FREQUENCY:
+		ret = paj7620_set_sampling_rate(dev, val);
+		break;
+
+	default:
+		return -ENOTSUP;
+	}
+
+	return ret;
+}
+
+static int paj7620_init(const struct device *dev)
+{
+	int ret;
+	uint16_t hw_id;
+	const struct paj7620_config *config = dev->config;
+
+	if (!i2c_is_ready_dt(&config->i2c)) {
+		LOG_ERR("I2C bus device not ready");
+		return -ENODEV;
+	}
+
+	/**
+	 * According to the datasheet section 8.1, we must wait this amount
+	 * of time for sensor to stabilize after power up
+	 */
+	k_usleep(PAJ7620_POWERUP_STABILIZATION_TIME_US);
+
+	/**
+	 * Make a write to the sensor to wake it up. After waking it, the
+	 * the sensor still needs some time to be ready to listen. Without it,
+	 * it may NACK subsequent transactions.
+	 */
+	(void)paj7620_select_register_bank(dev, PAJ7620_MEMBANK_0);
+	k_usleep(PAJ7620_WAKEUP_TIME_US);
+
+	/** Verify this is not some other sensor with the same address */
+	ret = paj7620_get_hw_id(dev, &hw_id);
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (hw_id != PAJ7620_PART_ID) {
+		LOG_ERR("Hardware ID 0x%04x does not match for PAJ7620", hw_id);
+		return -ENOTSUP;
+	}
+
+	/** Initialize settings (it defaults to gesture mode) */
+	ret = paj7620_write_initial_reg_settings(dev);
+	if (ret < 0) {
+		LOG_ERR("Failed to initialize device registers");
+		return ret;
+	}
+
+	if (IS_ENABLED(CONFIG_PAJ7620_TRIGGER)) {
+		ret = paj7620_trigger_init(dev);
+		if (ret < 0) {
+			LOG_ERR("Failed to enable interrupts");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static DEVICE_API(sensor, paj7620_driver_api) = {
+	.sample_fetch = paj7620_sample_fetch,
+	.channel_get = paj7620_channel_get,
+	.attr_set = paj7620_attr_set,
+#if CONFIG_PAJ7620_TRIGGER
+	.trigger_set = paj7620_trigger_set,
+#endif
+};
+
+#define PAJ7620_INIT(n)                                                                    \
+	static const struct paj7620_config paj7620_config_##n = {                          \
+		.i2c = I2C_DT_SPEC_INST_GET(n),					           \
+		IF_ENABLED(CONFIG_PAJ7620_TRIGGER,                                         \
+				(.int_gpio = GPIO_DT_SPEC_INST_GET_OR(n, int_gpios, {0}))) \
+	};                                                                                 \
+                                                                                           \
+	static struct paj7620_data paj7620_data_##n;                                       \
+                                                                                           \
+	SENSOR_DEVICE_DT_INST_DEFINE(n,                                                    \
+				paj7620_init,                                              \
+				NULL,                                                      \
+				&paj7620_data_##n,                                         \
+				&paj7620_config_##n,                                       \
+				POST_KERNEL,                                               \
+				CONFIG_SENSOR_INIT_PRIORITY,                               \
+				&paj7620_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(PAJ7620_INIT);
diff --git a/drivers/sensor/pixart/paj7620/paj7620.h b/drivers/sensor/pixart/paj7620/paj7620.h
new file mode 100644
index 00000000000..688bf0ad86b
--- /dev/null
+++ b/drivers/sensor/pixart/paj7620/paj7620.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2025 Paul Timke <ptimkec@live.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_PAJ7620_H_
+#define ZEPHYR_DRIVERS_SENSOR_PAJ7620_H_
+
+#include <zephyr/drivers/sensor/paj7620.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/gpio.h>
+
+/** Sensor hardcoded Part ID */
+#define PAJ7620_PART_ID ((PAJ7620_VAL_PART_ID_MSB << 8) | (PAJ7620_VAL_PART_ID_LSB & 0x00FF))
+
+/** Sensor FPS values */
+#define PAJ7620_NORMAL_SPEED 0xAC /* Normal speed 120 fps */
+#define PAJ7620_GAME_SPEED   0x30 /* Game mode speed 240 fps */
+
+/** Sensor stabilization time microseconds (us) */
+#define PAJ7620_POWERUP_STABILIZATION_TIME_US 700
+
+/** Sensor stabilization time after I2C wakeup (us).
+ * PAJ7620 still needs some time to wake up after waking it
+ * with an I2C write. This value was obtained experimentally
+ */
+#define PAJ7620_WAKEUP_TIME_US 200
+
+enum paj7620_mem_bank {
+	PAJ7620_MEMBANK_0 = 0,
+	PAJ7620_MEMBANK_1,
+};
+
+struct paj7620_config {
+	const struct i2c_dt_spec i2c;
+#if CONFIG_PAJ7620_TRIGGER
+	struct gpio_dt_spec int_gpio;
+#endif
+};
+
+struct paj7620_data {
+	struct k_sem sem;
+	uint16_t gesture_flags;
+
+#ifdef CONFIG_PAJ7620_TRIGGER
+	const struct device *dev;
+	struct gpio_callback gpio_cb;
+	sensor_trigger_handler_t motion_handler;
+	const struct sensor_trigger *motion_trig;
+#endif
+#ifdef CONFIG_PAJ7620_TRIGGER_OWN_THREAD
+	K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_PAJ7620_THREAD_STACK_SIZE);
+	struct k_thread thread;
+	struct k_sem trig_sem;
+#endif
+#ifdef CONFIG_PAJ7620_TRIGGER_GLOBAL_THREAD
+	struct k_work work;
+#endif
+};
+
+int paj7620_trigger_init(const struct device *dev);
+int paj7620_trigger_set(const struct device *dev,
+		const struct sensor_trigger *trig,
+		sensor_trigger_handler_t handler);
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_PAJ7620_H_ */
diff --git a/drivers/sensor/pixart/paj7620/paj7620_reg.h b/drivers/sensor/pixart/paj7620/paj7620_reg.h
new file mode 100644
index 00000000000..b4a4e667255
--- /dev/null
+++ b/drivers/sensor/pixart/paj7620/paj7620_reg.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright (c) 2025 Paul Timke <ptimkec@live.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_PAJ7620_REG_H_
+#define ZEPHYR_DRIVERS_SENSOR_PAJ7620_REG_H_
+
+#include <stdint.h>
+
+/**
+ * @file
+ * @brief PAJ7620 Register addresses and values. Not all registers from the
+ * data sheet are listed here, only the ones directly used by the driver.
+ * For more information about the registers, refer to:
+ * https://files.seeedstudio.com/wiki/Grove_Gesture_V_1.0/res/PAJ7620U2_DS_v1.5_05012022_Confidential.pdf
+ */
+
+/**
+ * BANK 0 REGISTER ADDRESSES
+ */
+
+/* Chip / Version ID */
+#define PAJ7620_REG_PART_ID_LSB 0x00
+#define PAJ7620_REG_PART_ID_MSB 0x01
+
+/** Register bank select */
+#define PAJ7620_REG_BANK_SEL 0xEF
+
+/** Interrupt Controls */
+/* Note: If the corresponding bit is 1, the corresponding interrupt is enabled */
+#define PAJ7620_REG_MCU_INT_CTRL 0x40 /* Configure auto clean and active high/low */
+#define PAJ7620_REG_INT_1_EN     0x41 /* Enable int 1 interrupts */
+#define PAJ7620_REG_INT_2_EN     0x42 /* Enable int 2 interrupts */
+#define PAJ7620_REG_INT_FLAG_1   0x43 /* Gesture detection results */
+#define PAJ7620_REG_INT_FLAG_2   0x44 /* Gesture detection results (wave and others) */
+
+/**
+ * BANK 0 REGISTER VALUES AND MASKS
+ */
+#define PAJ7620_VAL_PART_ID_LSB 0x20
+#define PAJ7620_VAL_PART_ID_MSB 0x76
+
+/** Register bank select values */
+#define PAJ7620_VAL_BANK_SEL_BANK_0 0x00
+#define PAJ7620_VAL_BANK_SEL_BANK_1 0x01
+
+/** Interrupt controls masks and values */
+#define PAJ7620_MASK_MCU_INT_FLAG_GCLR               BIT(1)
+#define PAJ7620_VAL_MCU_INT_FLAG_AUTO_CLEAN_DISABLE  0x00
+#define PAJ7620_VAL_MCU_INT_FLAG_AUTO_CLEAN_ENABLE   0x01
+
+#define PAJ7620_MASK_MCU_INT_FLAG_INV                BIT(4)
+#define PAJ7620_VAL_MCU_INT_FLAG_PIN_ACTIVE_LOW      0x00
+#define PAJ7620_VAL_MCU_INT_FLAG_PIN_ACTIVE_HIGH     0x01
+
+#define PAJ7620_MASK_ALL_GESTURE_INTS_ENABLE         0xFF
+#define PAJ7620_MASK_ALL_GESTURE_INTS_DISABLE        0x00
+
+/**
+ * BANK 1 REGISTER ADDRESSES
+ */
+#define PAJ7620_REG_R_IDLE_TIME_LSB 0x65
+#define PAJ7620_REG_R_IDLE_TIME_MSB 0x66
+
+/**
+ * INITIALIZATION ARRAYS
+ * The following 'initial_register_array' is taken 'as is' from Section 8
+ * (Firmware Guides) of the PAJ7620 datasheet v1.5.
+ * It encodes pairs of register addresses and values for those registers
+ * needed to initialize the sensor or change its operation mode
+ *
+ * Reference:
+ * https://files.seeedstudio.com/wiki/Grove_Gesture_V_1.0/res/PAJ7620U2_DS_v1.5_05012022_Confidential.pdf
+ */
+
+static const uint8_t initial_register_array[][2] = {
+	{0xEF, 0x00}, /* Select memory bank 0 */
+	{0x41, 0xFF}, /* Enable gesture interrupts */
+	{0x42, 0x01},
+	{0x46, 0x2D},
+	{0x47, 0x0F},
+	{0x48, 0x80},
+	{0x49, 0x00},
+	{0x4A, 0x40},
+	{0x4B, 0x00},
+	{0x4C, 0x20},
+	{0x4D, 0x00},
+	{0x51, 0x10},
+	{0x5C, 0x02},
+	{0x5E, 0x10},
+	{0x80, 0x41},
+	{0x81, 0x44},
+	{0x82, 0x0C},
+	{0x83, 0x20},
+	{0x84, 0x20},
+	{0x85, 0x00},
+	{0x86, 0x10},
+	{0x87, 0x00},
+	{0x8B, 0x01},
+	{0x8D, 0x00},
+	{0x90, 0x0C},
+	{0x91, 0x0C},
+	{0x93, 0x0D},
+	{0x94, 0x0A},
+	{0x95, 0x0A},
+	{0x96, 0x0C},
+	{0x97, 0x05},
+	{0x9A, 0x14},
+	{0x9C, 0x3F},
+	{0x9F, 0xF9},
+	{0xA0, 0x48},
+	{0xA5, 0x19},
+	{0xCC, 0x19},
+	{0xCD, 0x0B},
+	{0xCE, 0x13},
+	{0xCF, 0x62},
+	{0xD0, 0x21},
+	{0xEF, 0x01}, /* Select memory bank 1 */
+	{0x00, 0x1E},
+	{0x01, 0x1E},
+	{0x02, 0x0F},
+	{0x03, 0x0F},
+	{0x04, 0x02},
+	{0x25, 0x01},
+	{0x26, 0x00},
+	{0x27, 0x39},
+	{0x28, 0x7F},
+	{0x29, 0x08},
+	{0x30, 0x03},
+	{0x3E, 0xFF},
+	{0x5E, 0x3D},
+	{0x65, 0xAC}, /* Set fps to 'normal' mode */
+	{0x66, 0x00},
+	{0x67, 0x97},
+	{0x68, 0x01},
+	{0x69, 0xCD},
+	{0x6A, 0x01},
+	{0x6B, 0xB0},
+	{0x6C, 0x04},
+	{0x6D, 0x2C},
+	{0x6E, 0x01},
+	{0x72, 0x01},
+	{0x73, 0x35},
+	{0x74, 0x00}, /* Set to gesture mode */
+	{0x77, 0x01},
+	{0xEF, 0x00}, /* Reselect memory bank 0 */
+};
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_PAJ7620_REG_H_ */
diff --git a/drivers/sensor/pixart/paj7620/paj7620_trigger.c b/drivers/sensor/pixart/paj7620/paj7620_trigger.c
new file mode 100644
index 00000000000..b5388ac5ea9
--- /dev/null
+++ b/drivers/sensor/pixart/paj7620/paj7620_trigger.c
@@ -0,0 +1,137 @@
+/*
+ * Copyright (c) 2025 Paul Timke <ptimkec@live.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT pixart_paj7620
+
+#include "paj7620.h"
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/gpio.h>
+
+LOG_MODULE_REGISTER(paj7620, CONFIG_SENSOR_LOG_LEVEL);
+
+static void paj7620_gpio_callback(const struct device *dev,
+				struct gpio_callback *cb,
+				uint32_t pin_mask)
+{
+	struct paj7620_data *data =
+		CONTAINER_OF(cb, struct paj7620_data, gpio_cb);
+	const struct paj7620_config *config = data->dev->config;
+
+	if ((pin_mask & BIT(config->int_gpio.pin)) == 0U) {
+		return;
+	}
+
+#ifdef CONFIG_PAJ7620_TRIGGER_OWN_THREAD
+	k_sem_give(&data->trig_sem);
+#elif CONFIG_PAJ7620_TRIGGER_GLOBAL_THREAD
+	k_work_submit(&data->work);
+#endif
+}
+
+static void paj7620_handle_int(const struct device *dev)
+{
+	struct paj7620_data *data = dev->data;
+
+	if (data->motion_handler) {
+		data->motion_handler(dev, data->motion_trig);
+	}
+}
+
+#ifdef CONFIG_PAJ7620_TRIGGER_OWN_THREAD
+static void paj7620_thread_main(void *p1, void *p2, void *p3)
+{
+	ARG_UNUSED(p1);
+	ARG_UNUSED(p2);
+
+	struct paj7620_data *data = p1;
+
+	while (1) {
+		k_sem_take(&data->trig_sem, K_FOREVER);
+		paj7620_handle_int(data->dev);
+	}
+}
+#endif
+
+#ifdef CONFIG_PAJ7620_TRIGGER_GLOBAL_THREAD
+static void paj7620_work_handler(struct k_work *work)
+{
+	struct paj7620_data *data =
+		CONTAINER_OF(work, struct paj7620_data, work);
+
+	paj7620_handle_int(data->dev);
+}
+#endif
+
+int paj7620_trigger_set(const struct device *dev,
+			const struct sensor_trigger *trig,
+			sensor_trigger_handler_t handler)
+{
+	struct paj7620_data *data = dev->data;
+	const struct paj7620_config *cfg = dev->config;
+
+	if (cfg->int_gpio.port == NULL) {
+		return -ENOTSUP;
+	}
+
+	if (trig->type != SENSOR_TRIG_MOTION) {
+		LOG_ERR("Unsupported sensor trigger");
+		return -ENOTSUP;
+	}
+
+	data->motion_handler = handler;
+	data->motion_trig = trig;
+
+	if (handler == NULL) {
+		return gpio_pin_interrupt_configure_dt(&cfg->int_gpio, GPIO_INT_DISABLE);
+	}
+
+	return gpio_pin_interrupt_configure_dt(&cfg->int_gpio, GPIO_INT_EDGE_FALLING);
+}
+
+int paj7620_trigger_init(const struct device *dev)
+{
+	int ret;
+	const struct paj7620_config *config = dev->config;
+	struct paj7620_data *data = dev->data;
+
+	data->dev = dev;
+
+#ifdef CONFIG_PAJ7620_TRIGGER_OWN_THREAD
+	k_sem_init(&data->trig_sem, 0, K_SEM_MAX_LIMIT);
+	k_thread_create(&data->thread,
+			data->thread_stack,
+			K_KERNEL_STACK_SIZEOF(data->thread_stack),
+			paj7620_thread_main,
+			data,
+			NULL,
+			NULL,
+			K_PRIO_COOP(CONFIG_PAJ7620_THREAD_PRIORITY),
+			0,
+			K_NO_WAIT);
+#elif CONFIG_PAJ7620_TRIGGER_GLOBAL_THREAD
+	data->work.handler = paj7620_work_handler;
+#endif
+
+	/* Configure GPIO */
+	if (!gpio_is_ready_dt(&config->int_gpio)) {
+		LOG_ERR("GPIO device not ready");
+		return -ENODEV;
+	}
+
+	ret = gpio_pin_configure_dt(&config->int_gpio, GPIO_INPUT);
+	if (ret < 0) {
+		return ret;
+	}
+
+	gpio_init_callback(&data->gpio_cb, paj7620_gpio_callback, BIT(config->int_gpio.pin));
+
+	ret = gpio_add_callback(config->int_gpio.port, &data->gpio_cb);
+	if (ret < 0) {
+		return ret;
+	}
+
+	return 0;
+}
diff --git a/drivers/sensor/pixart/pat9136/CMakeLists.txt b/drivers/sensor/pixart/pat9136/CMakeLists.txt
new file mode 100644
index 00000000000..7a5fa5e3950
--- /dev/null
+++ b/drivers/sensor/pixart/pat9136/CMakeLists.txt
@@ -0,0 +1,13 @@
+# Copyright (c) 2025 Croxel Inc.
+# Copyright (c) 2025 CogniPilot Foundation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+zephyr_library_sources(
+	pat9136.c
+	pat9136_decoder.c
+)
+
+zephyr_library_sources_ifdef(CONFIG_PAT9136_STREAM
+	pat9136_stream.c
+)
diff --git a/drivers/sensor/pixart/pat9136/Kconfig b/drivers/sensor/pixart/pat9136/Kconfig
new file mode 100644
index 00000000000..5123088bb60
--- /dev/null
+++ b/drivers/sensor/pixart/pat9136/Kconfig
@@ -0,0 +1,24 @@
+# Copyright (c) 2025 Croxel Inc.
+# Copyright (c) 2025 CogniPilot Foundation
+# SPDX-License-Identifier: Apache-2.0
+
+config PAT9136
+	bool "Optical Flow Sensor PAT9136"
+	default y
+	depends on DT_HAS_PIXART_PAT9136_ENABLED
+	select SPI
+	select SPI_RTIO
+	select RTIO_WORKQ
+	select SENSOR_ASYNC_API
+	help
+	  Enable driver for PAT9136 Optical Flow sensor.
+
+if PAT9136
+
+config PAT9136_STREAM
+	bool "Streaming mode"
+	depends on $(dt_compat_any_has_prop,$(DT_COMPAT_PIXART_PAT9136),int-gpios)
+	help
+	  Enable streaming mode for the PAT9136 sensor.
+
+endif # PAT9136
diff --git a/drivers/sensor/pixart/pat9136/pat9136.c b/drivers/sensor/pixart/pat9136/pat9136.c
new file mode 100644
index 00000000000..4ccb66fa791
--- /dev/null
+++ b/drivers/sensor/pixart/pat9136/pat9136.c
@@ -0,0 +1,470 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT pixart_pat9136
+
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/rtio/rtio.h>
+#include <zephyr/rtio/work.h>
+#include <zephyr/sys/check.h>
+
+#include "pat9136.h"
+#include "pat9136_reg.h"
+#include "pat9136_bus.h"
+#include "pat9136_decoder.h"
+#include "pat9136_stream.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(PAT9136, CONFIG_SENSOR_LOG_LEVEL);
+
+struct reg_val_pair {
+	uint8_t reg;
+	uint8_t val;
+	bool op_read;
+	int (*handler)(const struct device *dev, const struct reg_val_pair *self);
+};
+
+static int perform_reg_ops(const struct device *dev, const struct reg_val_pair *ops, size_t len)
+{
+	int err;
+
+	for (size_t i = 0 ; i < len ; i++) {
+
+		/* Copying in order to allow reading data back and keeping the ops array const. */
+		struct reg_val_pair op = ops[i];
+
+		if (op.op_read) {
+			err = pat9136_bus_read(dev, op.reg, &op.val, 1);
+		} else {
+			err = pat9136_bus_write(dev, op.reg, &op.val, 1);
+		}
+
+		if (err) {
+			LOG_ERR("Failed op: %s, idx: %d, reg: 0x%02X, val: 0x%02X",
+				op.op_read ? "read" : "write", i,
+				op.reg, op.val);
+			return err;
+		}
+
+		if (op.handler) {
+			err = op.handler(dev, &op);
+			if (err) {
+				LOG_ERR("Failed to handle op: %d", err);
+				return err;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static void pat9136_complete_result(struct rtio *ctx,
+				    const struct rtio_sqe *sqe,
+				    void *arg)
+{
+	struct rtio_iodev_sqe *iodev_sqe = (struct rtio_iodev_sqe *)sqe->userdata;
+	struct rtio_cqe *cqe;
+	int err = 0;
+
+	do {
+		cqe = rtio_cqe_consume(ctx);
+		if (cqe != NULL) {
+			err = cqe->result;
+			rtio_cqe_release(ctx, cqe);
+		}
+	} while (cqe != NULL);
+
+	if (err) {
+		rtio_iodev_sqe_err(iodev_sqe, err);
+	} else {
+		rtio_iodev_sqe_ok(iodev_sqe, 0);
+	}
+
+	LOG_DBG("One-shot fetch completed");
+}
+
+static void pat9136_submit_one_shot(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
+{
+	const struct sensor_read_config *cfg = iodev_sqe->sqe.iodev->data;
+	const struct sensor_chan_spec *const channels = cfg->channels;
+	const size_t num_channels = cfg->count;
+	uint32_t min_buf_len = sizeof(struct pat9136_encoded_data);
+	int err;
+	uint8_t *buf;
+	uint32_t buf_len;
+	struct pat9136_encoded_data *edata;
+	struct pat9136_data *data = dev->data;
+
+	err = rtio_sqe_rx_buf(iodev_sqe, min_buf_len, min_buf_len, &buf, &buf_len);
+	CHECKIF(err) {
+		LOG_ERR("Failed to get a read buffer of size %u bytes", min_buf_len);
+		rtio_iodev_sqe_err(iodev_sqe, err);
+		return;
+	}
+
+	edata = (struct pat9136_encoded_data *)buf;
+
+	err = pat9136_encode(dev, channels, num_channels, buf);
+	if (err != 0) {
+		LOG_ERR("Failed to encode sensor data");
+		rtio_iodev_sqe_err(iodev_sqe, err);
+		return;
+	}
+
+	struct rtio_sqe *write_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	struct rtio_sqe *read_sqe = rtio_sqe_acquire(data->rtio.ctx);
+
+	CHECKIF(!write_sqe || !read_sqe) {
+		LOG_ERR("Failed to acquire RTIO SQEs");
+		rtio_iodev_sqe_err(iodev_sqe, -ENOMEM);
+		return;
+	}
+
+	uint8_t val = REG_BURST_READ | REG_SPI_READ_BIT;
+
+	rtio_sqe_prep_tiny_write(write_sqe,
+				 data->rtio.iodev,
+				 RTIO_PRIO_HIGH,
+				 &val,
+				 1,
+				 NULL);
+	write_sqe->flags |= RTIO_SQE_TRANSACTION;
+
+	rtio_sqe_prep_read(read_sqe,
+			   data->rtio.iodev,
+			   RTIO_PRIO_HIGH,
+			   edata->buf,
+			   sizeof(edata->buf),
+			   NULL);
+	read_sqe->flags |= RTIO_SQE_CHAINED;
+
+	/** Chip only supports "burst reads" for the Data, and hence we can't
+	 * just perform a multi-byte read here. Hence, we're iterating over all
+	 * resolution registers.
+	 */
+	for (size_t i = 0 ; i < sizeof(edata->header.resolution.buf) ; i++) {
+		struct rtio_sqe *res_write_sqe = rtio_sqe_acquire(data->rtio.ctx);
+		struct rtio_sqe *res_read_sqe = rtio_sqe_acquire(data->rtio.ctx);
+
+		CHECKIF(!res_write_sqe || !res_read_sqe) {
+			LOG_ERR("Failed to acquire RTIO SQEs");
+			rtio_iodev_sqe_err(iodev_sqe, -ENOMEM);
+			return;
+		}
+
+		val = (REG_RESOLUTION_X_LOWER + i) | REG_SPI_READ_BIT;
+
+		rtio_sqe_prep_tiny_write(res_write_sqe,
+					 data->rtio.iodev,
+					 RTIO_PRIO_HIGH,
+					 &val,
+					 1,
+					 NULL);
+		res_write_sqe->flags |= RTIO_SQE_TRANSACTION;
+
+		rtio_sqe_prep_read(res_read_sqe,
+				   data->rtio.iodev,
+				   RTIO_PRIO_HIGH,
+				   (uint8_t *)&edata->header.resolution.buf[i],
+				   1,
+				   NULL);
+		res_read_sqe->flags |= RTIO_SQE_CHAINED;
+	}
+
+	struct rtio_sqe *cb_sqe = rtio_sqe_acquire(data->rtio.ctx);
+
+	CHECKIF(!cb_sqe) {
+		LOG_ERR("Failed to acquire RTIO SQEs");
+		rtio_iodev_sqe_err(iodev_sqe, -ENOMEM);
+		return;
+	}
+
+	rtio_sqe_prep_callback_no_cqe(cb_sqe,
+				      pat9136_complete_result,
+				      NULL,
+				      iodev_sqe);
+
+
+	rtio_submit(data->rtio.ctx, 0);
+}
+
+static void pat9136_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
+{
+	const struct sensor_read_config *cfg = iodev_sqe->sqe.iodev->data;
+
+	if (!cfg->is_streaming) {
+		pat9136_submit_one_shot(dev, iodev_sqe);
+	} else if (IS_ENABLED(CONFIG_PAT9136_STREAM)) {
+		pat9136_stream_submit(dev, iodev_sqe);
+	} else {
+		LOG_ERR("Streaming not supported");
+		rtio_iodev_sqe_err(iodev_sqe, -ENOTSUP);
+	}
+}
+
+static DEVICE_API(sensor, pat9136_driver_api) = {
+	.submit = pat9136_submit,
+	.get_decoder = pat9136_get_decoder,
+};
+
+static int conditional_write_fn(const struct device *dev, const struct reg_val_pair *self)
+{
+	struct reg_val_pair cond_write[] = {
+		{.reg = 0x58, .val = 0},
+		{.reg = 0x57, .val = 0},
+	};
+
+	if (self->val & BIT(7)) {
+		cond_write[0].val = 0x04;
+		cond_write[1].val = 0x80;
+	} else {
+		cond_write[0].val = 0x84;
+		cond_write[1].val = 0x00;
+	}
+
+	return perform_reg_ops(dev, cond_write, ARRAY_SIZE(cond_write));
+}
+
+static int delay_100ms_fn(const struct device *dev, const struct reg_val_pair *self)
+{
+	k_sleep(K_MSEC(100));
+
+	return 0;
+}
+
+static int pat9136_init_sequence(const struct device *dev)
+{
+	const static struct reg_val_pair paa9136_init_sequence[] = {
+		{.reg = 0x3A, .val = 0x5A}, {.reg = 0x7F, .val = 0x00}, {.reg = 0x40, .val = 0x80},
+		{.reg = 0x7F, .val = 0x14}, {.reg = 0x4D, .val = 0x00}, {.reg = 0x53, .val = 0x0D},
+		{.reg = 0x4B, .val = 0x20}, {.reg = 0x42, .val = 0xBC}, {.reg = 0x43, .val = 0x74},
+		{.reg = 0x58, .val = 0x4C}, {.reg = 0x79, .val = 0x00}, {.reg = 0x7F, .val = 0x0E},
+		{.reg = 0x54, .val = 0x04}, {.reg = 0x7F, .val = 0x0E}, {.reg = 0x55, .val = 0x0D},
+		{.reg = 0x58, .val = 0xD5}, {.reg = 0x56, .val = 0xFB}, {.reg = 0x57, .val = 0xEB},
+		{.reg = 0x7F, .val = 0x15},
+
+		/** Per datasheet, depending on the value read for this register,
+		 * the written content will vary:
+		 * - BIT(7) = 0 -> reg(0x58) = 0x04, reg(0x57) = 0x80.
+		 * - BIT(7) = 1 -> reg(0x58) = 0x84, reg(0x57) = 0x00.
+		 */
+		{
+			.reg = 0x58,
+			.op_read = true,
+			.handler = conditional_write_fn,
+		},
+
+		{.reg = 0x7F, .val = 0x07}, {.reg = 0x40, .val = 0x43}, {.reg = 0x7F, .val = 0x13},
+		{.reg = 0x49, .val = 0x20}, {.reg = 0x7F, .val = 0x14}, {.reg = 0x54, .val = 0x02},
+		{.reg = 0x7F, .val = 0x15}, {.reg = 0x60, .val = 0x00}, {.reg = 0x7F, .val = 0x06},
+		{.reg = 0x74, .val = 0x50}, {.reg = 0x7B, .val = 0x02}, {.reg = 0x7F, .val = 0x00},
+		{.reg = 0x64, .val = 0x74}, {.reg = 0x65, .val = 0x03}, {.reg = 0x72, .val = 0x0E},
+		{.reg = 0x73, .val = 0x00}, {.reg = 0x7F, .val = 0x14}, {.reg = 0x61, .val = 0x3E},
+		{.reg = 0x62, .val = 0x1E}, {.reg = 0x63, .val = 0x1E}, {.reg = 0x7F, .val = 0x15},
+		{.reg = 0x69, .val = 0x1E}, {.reg = 0x7F, .val = 0x07}, {.reg = 0x40, .val = 0x40},
+		{.reg = 0x7F, .val = 0x00}, {.reg = 0x61, .val = 0x00}, {.reg = 0x7F, .val = 0x15},
+		{.reg = 0x63, .val = 0x00}, {.reg = 0x62, .val = 0x00}, {.reg = 0x7F, .val = 0x00},
+		{.reg = 0x61, .val = 0xAD}, {.reg = 0x7F, .val = 0x15}, {.reg = 0x5D, .val = 0x2C},
+
+		/** Per datasheet, on this write we need to wait for 100-ms before moving on */
+		{
+			.reg = 0x5E,
+			.val = 0xC4,
+			.op_read = false,
+			.handler = delay_100ms_fn,
+		},
+
+		{.reg = 0x5D, .val = 0x04}, {.reg = 0x5E, .val = 0xEC},
+		{.reg = 0x7F, .val = 0x05}, {.reg = 0x42, .val = 0x48}, {.reg = 0x43, .val = 0xE7},
+		{.reg = 0x7F, .val = 0x06}, {.reg = 0x71, .val = 0x03}, {.reg = 0x7F, .val = 0x09},
+		{.reg = 0x60, .val = 0x1C}, {.reg = 0x61, .val = 0x1E}, {.reg = 0x62, .val = 0x02},
+		{.reg = 0x63, .val = 0x04}, {.reg = 0x64, .val = 0x1E}, {.reg = 0x65, .val = 0x1F},
+		{.reg = 0x66, .val = 0x01}, {.reg = 0x67, .val = 0x02}, {.reg = 0x68, .val = 0x02},
+		{.reg = 0x69, .val = 0x01}, {.reg = 0x6A, .val = 0x1F}, {.reg = 0x6B, .val = 0x1E},
+		{.reg = 0x6C, .val = 0x04}, {.reg = 0x6D, .val = 0x02}, {.reg = 0x6E, .val = 0x1E},
+		{.reg = 0x6F, .val = 0x1C}, {.reg = 0x7F, .val = 0x05}, {.reg = 0x45, .val = 0x94},
+		{.reg = 0x45, .val = 0x14}, {.reg = 0x44, .val = 0x45}, {.reg = 0x45, .val = 0x17},
+		{.reg = 0x7F, .val = 0x09}, {.reg = 0x47, .val = 0x4F}, {.reg = 0x4F, .val = 0x00},
+		{.reg = 0x52, .val = 0x04}, {.reg = 0x7F, .val = 0x0C}, {.reg = 0x4E, .val = 0x00},
+		{.reg = 0x5B, .val = 0x00}, {.reg = 0x7F, .val = 0x0D}, {.reg = 0x71, .val = 0x92},
+		{.reg = 0x70, .val = 0x07}, {.reg = 0x73, .val = 0x92}, {.reg = 0x72, .val = 0x07},
+		{.reg = 0x7F, .val = 0x00}, {.reg = 0x5B, .val = 0x20}, {.reg = 0x48, .val = 0x13},
+		{.reg = 0x49, .val = 0x00}, {.reg = 0x4A, .val = 0x13}, {.reg = 0x4B, .val = 0x00},
+		{.reg = 0x47, .val = 0x01}, {.reg = 0x54, .val = 0x55}, {.reg = 0x5A, .val = 0x50},
+		{.reg = 0x66, .val = 0x03}, {.reg = 0x67, .val = 0x00}, {.reg = 0x7F, .val = 0x07},
+		{.reg = 0x40, .val = 0x43}, {.reg = 0x7F, .val = 0x05}, {.reg = 0x4D, .val = 0x00},
+		{.reg = 0x6D, .val = 0x96}, {.reg = 0x55, .val = 0x62}, {.reg = 0x59, .val = 0x21},
+		{.reg = 0x5F, .val = 0xD8}, {.reg = 0x6A, .val = 0x22}, {.reg = 0x7F, .val = 0x07},
+		{.reg = 0x42, .val = 0x30}, {.reg = 0x43, .val = 0x00}, {.reg = 0x7F, .val = 0x06},
+		{.reg = 0x4C, .val = 0x01}, {.reg = 0x54, .val = 0x02}, {.reg = 0x62, .val = 0x01},
+		{.reg = 0x7F, .val = 0x09}, {.reg = 0x41, .val = 0x01}, {.reg = 0x4F, .val = 0x00},
+		{.reg = 0x7F, .val = 0x0A}, {.reg = 0x4C, .val = 0x18}, {.reg = 0x51, .val = 0x8F},
+		{.reg = 0x7F, .val = 0x07}, {.reg = 0x40, .val = 0x40}, {.reg = 0x7F, .val = 0x00},
+		{.reg = 0x40, .val = 0x80}, {.reg = 0x7F, .val = 0x09}, {.reg = 0x40, .val = 0x03},
+		{.reg = 0x44, .val = 0x08}, {.reg = 0x4F, .val = 0x08}, {.reg = 0x7F, .val = 0x0A},
+		{.reg = 0x51, .val = 0x8E}, {.reg = 0x7F, .val = 0x00}, {.reg = 0x66, .val = 0x11},
+		{.reg = 0x67, .val = 0x08},
+	};
+
+	return perform_reg_ops(dev, paa9136_init_sequence, ARRAY_SIZE(paa9136_init_sequence));
+}
+
+static int pat9136_set_resolution(const struct device *dev)
+{
+	const struct pat9136_config *cfg = dev->config;
+	struct reg_val_pair paa9136_resolution_ops[] = {
+		{.reg = REG_RESOLUTION_X_LOWER, .val = cfg->resolution & 0xFF},
+		{.reg = REG_RESOLUTION_X_UPPER, .val = 0},
+		{.reg = REG_RESOLUTION_Y_LOWER, .val = cfg->resolution & 0xFF},
+		{.reg = REG_RESOLUTION_Y_UPPER, .val = 0},
+		{.reg = REG_RESOLUTION_SET, .val = 0x01},
+	};
+
+	return perform_reg_ops(dev, paa9136_resolution_ops, ARRAY_SIZE(paa9136_resolution_ops));
+}
+
+static int pat9136_configure(const struct device *dev)
+{
+	int err;
+	uint8_t val;
+	uint8_t motion_data[6];
+
+	/* Clear device config by issuing a software reset request */
+	val = POWER_UP_RESET_VAL;
+	err = pat9136_bus_write(dev, REG_POWER_UP_RESET, &val, 1);
+	if (err) {
+		LOG_ERR("Failed to write Power up reset reg");
+		return err;
+	}
+	k_sleep(K_MSEC(50));
+
+	/* Clear observation register and read back the register, */
+	uint8_t retries = 3;
+
+	do {
+		val = 0x00;
+		err = pat9136_bus_write(dev, REG_OBSERVATION, &val, 1);
+		if (err) {
+			LOG_ERR("Failed to read Product ID");
+			return err;
+		}
+		k_sleep(K_MSEC(1));
+
+		err = pat9136_bus_read(dev, REG_OBSERVATION, &val, 1);
+		if (err) {
+			LOG_ERR("Failed to read observation register");
+			return err;
+		}
+		if (REG_OBSERVATION_READ_IS_VALID(val)) {
+			break;
+		}
+	} while (err == 0 && (retries-- > 0));
+
+	if (!REG_OBSERVATION_READ_IS_VALID(val)) {
+		LOG_ERR("Invalid observation register value: 0x%02X", val);
+		return -EIO;
+	}
+
+	/** Load performance optimization settings */
+	err = pat9136_init_sequence(dev);
+	if (err) {
+		LOG_ERR("Failed to init sequence");
+		return err;
+	}
+
+	/* Set resolution */
+	err = pat9136_set_resolution(dev);
+	if (err) {
+		LOG_ERR("Failed to set resolution");
+		return err;
+	}
+
+	/* Read reg's 0x02-0x06 to clear motion data. */
+	err = pat9136_bus_read(dev, REG_MOTION, motion_data, sizeof(motion_data));
+	if (err) {
+		LOG_ERR("Failed to read motion data");
+		return err;
+	}
+
+	return 0;
+}
+
+static int pat9136_init(const struct device *dev)
+{
+	int err;
+	uint8_t val;
+
+	/* Power-up sequence delay */
+	k_sleep(K_MSEC(50));
+
+	/* Read Product ID */
+	err = pat9136_bus_read(dev, REG_PRODUCT_ID, &val, 1);
+	if (err) {
+		LOG_ERR("Failed to read Product ID");
+		return err;
+	} else if (val != PRODUCT_ID) {
+		LOG_ERR("Invalid Product ID: 0x%02X", val);
+		return -EIO;
+	}
+
+	if (IS_ENABLED(CONFIG_PAT9136_STREAM)) {
+		err = pat9136_stream_init(dev);
+		if (err) {
+			LOG_ERR("Failed to initialize streaming");
+			return err;
+		}
+	}
+
+	err = pat9136_configure(dev);
+	if (err) {
+		LOG_ERR("Failed to configure");
+		return err;
+	}
+
+	return 0;
+}
+
+#define PAT9136_INIT(inst)									   \
+												   \
+	BUILD_ASSERT(DT_PROP(DT_DRV_INST(inst), resolution) >= 0 &&				   \
+		     DT_PROP(DT_DRV_INST(inst), resolution) <= 0xC7,				   \
+		     "Resolution must be in range 0-199");					   \
+	BUILD_ASSERT(DT_PROP(DT_DRV_INST(inst), cooldown_timer_ms) <				   \
+		     DT_PROP(DT_DRV_INST(inst), backup_timer_ms),				   \
+		     "Cooldown timer must be less than backup timer");				   \
+												   \
+	RTIO_DEFINE(pat9136_rtio_ctx_##inst, 16, 16);						   \
+	SPI_DT_IODEV_DEFINE(pat9136_bus_##inst,							   \
+			    DT_DRV_INST(inst),							   \
+			    SPI_OP_MODE_MASTER | SPI_WORD_SET(8) | SPI_TRANSFER_MSB,		   \
+			    0U);								   \
+												   \
+	static const struct pat9136_config pat9136_cfg_##inst = {				   \
+		.int_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, {0}),			   \
+		.backup_timer_period = DT_PROP(DT_DRV_INST(inst), backup_timer_ms),		   \
+		.cooldown_timer_period = DT_PROP(DT_DRV_INST(inst), cooldown_timer_ms),		   \
+		.resolution = DT_INST_PROP(inst, resolution),					   \
+	};											   \
+												   \
+	static struct pat9136_data pat9136_data_##inst = {					   \
+		.rtio = {									   \
+			.iodev = &pat9136_bus_##inst,						   \
+			.ctx = &pat9136_rtio_ctx_##inst,					   \
+		},										   \
+	};											   \
+												   \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst,							   \
+				     pat9136_init,						   \
+				     NULL,							   \
+				     &pat9136_data_##inst,					   \
+				     &pat9136_cfg_##inst,					   \
+				     POST_KERNEL,						   \
+				     CONFIG_SENSOR_INIT_PRIORITY,				   \
+				     &pat9136_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(PAT9136_INIT)
diff --git a/drivers/sensor/pixart/pat9136/pat9136.h b/drivers/sensor/pixart/pat9136/pat9136.h
new file mode 100644
index 00000000000..94aaaa64c49
--- /dev/null
+++ b/drivers/sensor/pixart/pat9136/pat9136.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_PAT9136_H_
+#define ZEPHYR_DRIVERS_SENSOR_PAT9136_H_
+
+#include <stdint.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/rtio/rtio.h>
+
+struct pat9136_encoded_data {
+	struct {
+		uint64_t timestamp;
+		uint8_t channels : 6;
+		struct {
+			bool drdy : 1;
+			bool motion : 1;
+		} events;
+		union {
+			uint8_t buf[4];
+			struct {
+				uint16_t x;
+				uint16_t y;
+			} __attribute__((__packed__));
+		} resolution;
+	} header;
+	union {
+		uint8_t buf[12];
+		struct {
+			uint8_t motion;
+			uint8_t observation;
+			struct {
+				int16_t x;
+				int16_t y;
+			} delta;
+			uint8_t squal;
+			uint8_t raw_sum;
+			uint8_t raw_max;
+			uint8_t raw_min;
+			uint16_t shutter;
+		} __attribute__((__packed__));
+	};
+};
+
+struct pat9136_stream {
+	struct gpio_callback cb;
+	const struct device *dev;
+	struct rtio_iodev_sqe *iodev_sqe;
+	struct {
+		struct k_timer backup;
+		struct {
+			atomic_t armed;
+			struct k_timer timer;
+		} cooldown;
+	} timer;
+	struct {
+		struct {
+			bool drdy : 1;
+			bool motion : 1;
+		} enabled;
+		struct {
+			enum sensor_stream_data_opt drdy;
+			enum sensor_stream_data_opt motion;
+		} opt;
+	} settings;
+};
+
+struct pat9136_data {
+	struct {
+		struct rtio_iodev *iodev;
+		struct rtio *ctx;
+	} rtio;
+#if defined(CONFIG_PAT9136_STREAM)
+	struct pat9136_stream stream;
+#endif /* CONFIG_PAT9136_STREAM */
+};
+
+struct pat9136_config {
+	struct gpio_dt_spec int_gpio;
+	uint16_t resolution;
+	uint32_t backup_timer_period;
+	uint32_t cooldown_timer_period;
+};
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_PAT9136_H_ */
diff --git a/drivers/sensor/pixart/pat9136/pat9136_bus.h b/drivers/sensor/pixart/pat9136/pat9136_bus.h
new file mode 100644
index 00000000000..db61b54b9b9
--- /dev/null
+++ b/drivers/sensor/pixart/pat9136/pat9136_bus.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_PAT9136_BUS_H_
+#define ZEPHYR_DRIVERS_SENSOR_PAT9136_BUS_H_
+
+#include <stdint.h>
+#include <zephyr/rtio/rtio.h>
+
+#include "pat9136.h"
+#include "pat9136_reg.h"
+
+static inline int pat9136_bus_read(const struct device *dev,
+				   uint8_t reg,
+				   uint8_t *buf,
+				   uint16_t len)
+{
+	struct pat9136_data *data = dev->data;
+	struct rtio *ctx = data->rtio.ctx;
+	struct rtio_iodev *iodev = data->rtio.iodev;
+	struct rtio_sqe *write_sqe = rtio_sqe_acquire(ctx);
+	struct rtio_sqe *read_sqe = rtio_sqe_acquire(ctx);
+	struct rtio_cqe *cqe;
+	int err;
+
+	if (!write_sqe || !read_sqe) {
+		return -ENOMEM;
+	}
+
+	reg = reg | REG_SPI_READ_BIT;
+
+	rtio_sqe_prep_write(write_sqe, iodev, RTIO_PRIO_HIGH, &reg, 1, NULL);
+	write_sqe->flags |= RTIO_SQE_TRANSACTION;
+	rtio_sqe_prep_read(read_sqe, iodev, RTIO_PRIO_HIGH, buf, len, NULL);
+
+	err = rtio_submit(ctx, 2);
+	if (err) {
+		return err;
+	}
+
+	do {
+		cqe = rtio_cqe_consume(ctx);
+		if (cqe != NULL) {
+			err = cqe->result;
+			rtio_cqe_release(ctx, cqe);
+		}
+	} while (cqe != NULL);
+
+	return err;
+}
+
+static inline int pat9136_bus_write(const struct device *dev,
+				    uint8_t reg,
+				    const uint8_t *buf,
+				    uint16_t len)
+{
+	struct pat9136_data *data = dev->data;
+	struct rtio *ctx = data->rtio.ctx;
+	struct rtio_iodev *iodev = data->rtio.iodev;
+	struct rtio_sqe *write_reg_sqe = rtio_sqe_acquire(ctx);
+	struct rtio_sqe *write_buf_sqe = rtio_sqe_acquire(ctx);
+	struct rtio_cqe *cqe;
+	int err;
+
+	if (!write_reg_sqe || !write_buf_sqe) {
+		return -ENOMEM;
+	}
+
+	reg = reg | REG_SPI_WRITE_BIT;
+
+	rtio_sqe_prep_write(write_reg_sqe, iodev, RTIO_PRIO_HIGH, &reg, 1, NULL);
+	write_reg_sqe->flags |= RTIO_SQE_TRANSACTION;
+	rtio_sqe_prep_write(write_buf_sqe, iodev, RTIO_PRIO_HIGH, buf, len, NULL);
+
+	err = rtio_submit(ctx, 2);
+	if (err) {
+		return err;
+	}
+
+	do {
+		cqe = rtio_cqe_consume(ctx);
+		if (cqe != NULL) {
+			err = cqe->result;
+			rtio_cqe_release(ctx, cqe);
+		}
+	} while (cqe != NULL);
+
+	return err;
+}
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_PAT9136_BUS_H_ */
diff --git a/drivers/sensor/pixart/pat9136/pat9136_decoder.c b/drivers/sensor/pixart/pat9136/pat9136_decoder.c
new file mode 100644
index 00000000000..6fc869fe1c8
--- /dev/null
+++ b/drivers/sensor/pixart/pat9136/pat9136_decoder.c
@@ -0,0 +1,349 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/sensor_clock.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/drivers/sensor/pat9136.h>
+
+#include "pat9136.h"
+#include "pat9136_reg.h"
+#include "pat9136_decoder.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(PAT9136_DECODER, CONFIG_SENSOR_LOG_LEVEL);
+
+#define DT_DRV_COMPAT pixart_pat9136
+
+static int pat9136_get_shift(uint16_t channel,
+			     uint16_t res_x,
+			     uint16_t res_y,
+			     int8_t *shift)
+{
+	/** Table generated based on calculation of required bits:
+	 * - resolution_cpi (per datasheet) = (1 + resolution) * 100
+	 * - value_mm = value * 25.4 / resolution_cpi
+	 *  - Bits Required = round_up( Log2(value_mm) )
+	 */
+	struct {
+		uint16_t min;
+		uint16_t max;
+		int8_t shift;
+	} const static shift_based_on_ranges[] = {
+		{.min = 0, .max = 0, .shift = 14},
+		{.min = 1, .max = 1, .shift = 13},
+		{.min = 2, .max = 3, .shift = 12},
+		{.min = 4, .max = 7, .shift = 11},
+		{.min = 8, .max = 15, .shift = 10},
+		{.min = 16, .max = 31, .shift = 9},
+		{.min = 32, .max = 63, .shift = 8},
+		{.min = 64, .max = 127, .shift = 7},
+		{.min = 128, .max = 199, .shift = 6},
+	};
+	/** Going with lowest resolution to be able to represent biggest value */
+	uint16_t resolution = MIN(res_x, res_y);
+
+	switch (channel) {
+	case SENSOR_CHAN_POS_DX:
+	case SENSOR_CHAN_POS_DY:
+	case SENSOR_CHAN_POS_DXYZ:
+		*shift = 31;
+		return 0;
+	case SENSOR_CHAN_POS_DX_MM:
+	case SENSOR_CHAN_POS_DY_MM:
+	case SENSOR_CHAN_POS_DXYZ_MM:
+		for (size_t i = 0 ; i < ARRAY_SIZE(shift_based_on_ranges) ; i++) {
+			if (resolution >= shift_based_on_ranges[i].min &&
+			    resolution <= shift_based_on_ranges[i].max) {
+				*shift = shift_based_on_ranges[i].shift;
+				return 0;
+			}
+		}
+	default:
+		return -EINVAL;
+	}
+
+	return -EIO;
+}
+
+static void pat9136_convert_raw_to_q31(struct pat9136_encoded_data *edata,
+				       uint16_t chan,
+				       int32_t reading,
+				       q31_t *out)
+{
+	int8_t shift;
+	uint32_t resolution_setting = MIN(edata->header.resolution.x,
+					  edata->header.resolution.y);
+	int64_t intermediate;
+
+	(void)pat9136_get_shift(chan,
+				resolution_setting,
+				resolution_setting,
+				&shift);
+
+	switch (chan) {
+	case SENSOR_CHAN_POS_DX:
+	case SENSOR_CHAN_POS_DY:
+		*out = (q31_t)reading;
+		return;
+	case SENSOR_CHAN_POS_DX_MM:
+	case SENSOR_CHAN_POS_DY_MM: {
+		uint32_t resolution = (chan == SENSOR_CHAN_POS_DX_MM) ?
+				      (edata->header.resolution.x + 1) * 100 :
+				      (edata->header.resolution.y + 1) * 100;
+
+		intermediate = (((int64_t)reading * INT64_C(1000000) * 25.4));
+		intermediate /= resolution;
+
+		intermediate *= ((int64_t)INT32_MAX + 1) / ((1 << shift) * INT64_C(1000000));
+
+		*out = CLAMP(intermediate, INT32_MIN, INT32_MAX);
+
+		return;
+	}
+	default:
+		CODE_UNREACHABLE;
+	}
+}
+
+uint8_t pat9136_encode_channel(uint16_t chan)
+{
+	switch (chan) {
+	case SENSOR_CHAN_POS_DX:
+		return BIT(0);
+	case SENSOR_CHAN_POS_DY:
+		return BIT(1);
+	case SENSOR_CHAN_POS_DXYZ:
+		return BIT(2);
+	case SENSOR_CHAN_POS_DX_MM:
+		return BIT(3);
+	case SENSOR_CHAN_POS_DY_MM:
+		return BIT(4);
+	case SENSOR_CHAN_POS_DXYZ_MM:
+		return BIT(5);
+	case SENSOR_CHAN_ALL:
+		return BIT_MASK(6);
+	default:
+		return 0;
+	}
+}
+
+static bool is_data_valid(const struct pat9136_encoded_data *edata)
+{
+	if (!REG_MOTION_DETECTED(edata->motion)) {
+		LOG_WRN("Invalid data - No motion detected");
+		return false;
+	}
+
+	if (!REG_OBSERVATION_READ_IS_VALID(edata->observation)) {
+		LOG_WRN("Invalid data - Observation read is not valid");
+		return false;
+	}
+
+	return true;
+}
+
+static int pat9136_decoder_get_frame_count(const uint8_t *buffer,
+					   struct sensor_chan_spec chan_spec,
+					   uint16_t *frame_count)
+{
+	struct pat9136_encoded_data *edata = (struct pat9136_encoded_data *)buffer;
+
+	if (chan_spec.chan_idx != 0) {
+		return -ENOTSUP;
+	}
+
+	uint8_t channel_request = pat9136_encode_channel(chan_spec.chan_type);
+
+	if (((edata->header.channels & channel_request) != channel_request) ||
+	    !is_data_valid(edata)) {
+		return -ENODATA;
+	}
+
+	switch (chan_spec.chan_type) {
+	case SENSOR_CHAN_POS_DX:
+	case SENSOR_CHAN_POS_DY:
+	case SENSOR_CHAN_POS_DXYZ:
+	case SENSOR_CHAN_POS_DX_MM:
+	case SENSOR_CHAN_POS_DY_MM:
+	case SENSOR_CHAN_POS_DXYZ_MM:
+		*frame_count = 1;
+		return 0;
+	default:
+		return -ENOTSUP;
+	}
+
+	return -1;
+}
+
+static int pat9136_decoder_get_size_info(struct sensor_chan_spec chan_spec,
+					 size_t *base_size,
+					 size_t *frame_size)
+{
+	switch (chan_spec.chan_type) {
+	case SENSOR_CHAN_POS_DX:
+	case SENSOR_CHAN_POS_DY:
+	case SENSOR_CHAN_POS_DX_MM:
+	case SENSOR_CHAN_POS_DY_MM:
+		*base_size = sizeof(struct sensor_q31_data);
+		*frame_size = sizeof(struct sensor_q31_sample_data);
+		return 0;
+	case SENSOR_CHAN_POS_DXYZ:
+	case SENSOR_CHAN_POS_DXYZ_MM:
+		*base_size = sizeof(struct sensor_three_axis_data);
+		*frame_size = sizeof(struct sensor_three_axis_data);
+		return 0;
+	default:
+		return -ENOTSUP;
+	}
+}
+
+static int pat9136_decoder_decode(const uint8_t *buffer,
+				  struct sensor_chan_spec chan_spec,
+				  uint32_t *fit,
+				  uint16_t max_count,
+				  void *data_out)
+{
+	struct pat9136_encoded_data *edata = (struct pat9136_encoded_data *)buffer;
+	uint8_t channel_request;
+
+	if (*fit != 0) {
+		return 0;
+	}
+
+	if (max_count == 0 || chan_spec.chan_idx != 0) {
+		return -EINVAL;
+	}
+
+	switch (chan_spec.chan_type) {
+	case SENSOR_CHAN_POS_DX_MM:
+	case SENSOR_CHAN_POS_DY_MM:
+	case SENSOR_CHAN_POS_DX:
+	case SENSOR_CHAN_POS_DY: {
+		channel_request = pat9136_encode_channel(chan_spec.chan_type);
+		if (((edata->header.channels & channel_request) != channel_request) ||
+		    !is_data_valid(edata)) {
+			LOG_ERR("No data available");
+			return -ENODATA;
+		}
+
+		struct sensor_q31_data *out = (struct sensor_q31_data *)data_out;
+		int16_t raw_value = (chan_spec.chan_type == SENSOR_CHAN_POS_DX ||
+				     chan_spec.chan_type == SENSOR_CHAN_POS_DX_MM) ?
+				    edata->delta.x :
+				    edata->delta.y;
+
+		out->header.base_timestamp_ns = edata->header.timestamp;
+		out->header.reading_count = 1;
+
+		(void)pat9136_get_shift(chan_spec.chan_type,
+					edata->header.resolution.x,
+					edata->header.resolution.y,
+					&out->shift);
+
+		(void)pat9136_convert_raw_to_q31(edata,
+						 chan_spec.chan_type,
+						 raw_value,
+						 &out->readings->value);
+
+		*fit = 1;
+		return 1;
+	}
+	case SENSOR_CHAN_POS_DXYZ_MM:
+	case SENSOR_CHAN_POS_DXYZ: {
+		channel_request = pat9136_encode_channel(chan_spec.chan_type);
+		if (((edata->header.channels & channel_request) != channel_request) ||
+		    !is_data_valid(edata)) {
+			LOG_ERR("No data available");
+			return -ENODATA;
+		}
+
+		struct sensor_three_axis_data *out = (struct sensor_three_axis_data *)data_out;
+
+		out->header.base_timestamp_ns = edata->header.timestamp;
+		out->header.reading_count = 1;
+
+		(void)pat9136_get_shift(chan_spec.chan_type,
+					edata->header.resolution.x,
+					edata->header.resolution.y,
+					&out->shift);
+
+		(void)pat9136_convert_raw_to_q31(edata,
+						 chan_spec.chan_type - 3,
+						 edata->delta.x,
+						 &out->readings[0].x);
+		(void)pat9136_convert_raw_to_q31(edata,
+						 chan_spec.chan_type - 2,
+						 edata->delta.y,
+						 &out->readings[0].y);
+		out->readings[0].z = 0;
+
+		*fit = 1;
+		return 1;
+	}
+	default:
+		return -EINVAL;
+	}
+
+	return -1;
+}
+
+static bool pat9136_decoder_has_trigger(const uint8_t *buffer, enum sensor_trigger_type trigger)
+{
+	struct pat9136_encoded_data *edata = (struct pat9136_encoded_data *)buffer;
+
+	switch (trigger) {
+	case SENSOR_TRIG_DATA_READY:
+		return edata->header.events.drdy;
+	case SENSOR_TRIG_MOTION:
+		return edata->header.events.motion;
+	default:
+		return false;
+	}
+}
+
+SENSOR_DECODER_API_DT_DEFINE() = {
+	.get_frame_count = pat9136_decoder_get_frame_count,
+	.get_size_info = pat9136_decoder_get_size_info,
+	.decode = pat9136_decoder_decode,
+	.has_trigger = pat9136_decoder_has_trigger,
+};
+
+int pat9136_get_decoder(const struct device *dev,
+	const struct sensor_decoder_api **decoder)
+{
+	ARG_UNUSED(dev);
+	*decoder = &SENSOR_DECODER_NAME();
+
+	return 0;
+}
+
+int pat9136_encode(const struct device *dev,
+		   const struct sensor_chan_spec *const channels,
+		   size_t num_channels,
+		   uint8_t *buf)
+{
+	struct pat9136_encoded_data *edata = (struct pat9136_encoded_data *)buf;
+	uint64_t cycles;
+	int err;
+
+	edata->header.channels = 0;
+	edata->header.events.drdy = 0;
+	edata->header.events.motion = 0;
+
+	for (size_t i = 0 ; i < num_channels; i++) {
+		edata->header.channels |= pat9136_encode_channel(channels[i].chan_type);
+	}
+
+	err = sensor_clock_get_cycles(&cycles);
+	if (err != 0) {
+		return err;
+	}
+
+	edata->header.timestamp = sensor_clock_cycles_to_ns(cycles);
+
+	return 0;
+}
diff --git a/drivers/sensor/pixart/pat9136/pat9136_decoder.h b/drivers/sensor/pixart/pat9136/pat9136_decoder.h
new file mode 100644
index 00000000000..5d7e77fcedd
--- /dev/null
+++ b/drivers/sensor/pixart/pat9136/pat9136_decoder.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_PAT9136_DECODER_H_
+#define ZEPHYR_DRIVERS_SENSOR_PAT9136_DECODER_H_
+
+#include <stdint.h>
+#include <zephyr/drivers/sensor.h>
+#include "pat9136.h"
+
+int pat9136_encode(const struct device *dev,
+		   const struct sensor_chan_spec *const channels,
+		   size_t num_channels,
+		   uint8_t *buf);
+
+uint8_t pat9136_encode_channel(uint16_t chan);
+
+int pat9136_get_decoder(const struct device *dev,
+			const struct sensor_decoder_api **decoder);
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_PAT9136_DECODER_H_ */
diff --git a/drivers/sensor/pixart/pat9136/pat9136_reg.h b/drivers/sensor/pixart/pat9136/pat9136_reg.h
new file mode 100644
index 00000000000..0a5e56dcab0
--- /dev/null
+++ b/drivers/sensor/pixart/pat9136/pat9136_reg.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_PAT9136_REG_H_
+#define ZEPHYR_DRIVERS_SENSOR_PAT9136_REG_H_
+
+#define REG_SPI_READ_BIT			0
+#define REG_SPI_WRITE_BIT			BIT(7)
+
+/* Registers */
+#define REG_PRODUCT_ID				0x00
+#define REG_MOTION				0x02
+#define REG_OBSERVATION				0x15
+#define REG_BURST_READ				0x16
+#define REG_POWER_UP_RESET			0x3A
+#define REG_RESOLUTION_SET			0x47
+#define REG_RESOLUTION_X_LOWER			0x48
+#define REG_RESOLUTION_X_UPPER			0x49
+#define REG_RESOLUTION_Y_LOWER			0x4A
+#define REG_RESOLUTION_Y_UPPER			0x4B
+
+/* Misc. Defines */
+#define PRODUCT_ID				0x4F
+#define POWER_UP_RESET_VAL			0x5A
+
+#define REG_MOTION_DETECTED(val)		((val) & BIT(7))
+
+#define REG_OBSERVATION_READ_IS_VALID(val)	(((val) == 0xB7) || ((val) == 0xBF))
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_PAT9136_REG_H_ */
diff --git a/drivers/sensor/pixart/pat9136/pat9136_stream.c b/drivers/sensor/pixart/pat9136/pat9136_stream.c
new file mode 100644
index 00000000000..3f7bff784f2
--- /dev/null
+++ b/drivers/sensor/pixart/pat9136/pat9136_stream.c
@@ -0,0 +1,442 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/sensor_clock.h>
+#include <zephyr/sys/check.h>
+#include <zephyr/rtio/rtio.h>
+#include <zephyr/rtio/work.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/drivers/sensor/pat9136.h>
+
+#include "pat9136.h"
+#include "pat9136_reg.h"
+#include "pat9136_stream.h"
+#include "pat9136_decoder.h"
+#include "pat9136_bus.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(PAT9136_STREAM, CONFIG_SENSOR_LOG_LEVEL);
+
+static void start_drdy_backup_timer(const struct device *dev)
+{
+	struct pat9136_data *data = dev->data;
+	const struct pat9136_config *cfg = dev->config;
+
+	k_timer_start(&data->stream.timer.backup,
+		      K_MSEC(cfg->backup_timer_period),
+		      K_NO_WAIT);
+}
+
+static void start_drdy_cooldown_timer(const struct device *dev)
+{
+	struct pat9136_data *data = dev->data;
+	const struct pat9136_config *cfg = dev->config;
+
+	k_timer_start(&data->stream.timer.cooldown.timer,
+		      K_MSEC(cfg->cooldown_timer_period),
+		      K_NO_WAIT);
+}
+
+static void pat9136_complete_result(struct rtio *ctx,
+				    const struct rtio_sqe *sqe,
+				    void *arg)
+{
+	const struct device *dev = (const struct device *)arg;
+	struct pat9136_data *data = dev->data;
+	struct rtio_iodev_sqe *iodev_sqe = data->stream.iodev_sqe;
+	struct pat9136_encoded_data *edata = sqe->userdata;
+
+	data->stream.iodev_sqe = NULL;
+
+	edata->header.events.drdy = true &&
+				    data->stream.settings.enabled.drdy;
+	edata->header.events.motion = REG_MOTION_DETECTED(edata->motion) &&
+				      data->stream.settings.enabled.motion;
+	edata->header.channels = 0;
+
+	if ((data->stream.settings.enabled.drdy &&
+	      data->stream.settings.opt.drdy == SENSOR_STREAM_DATA_INCLUDE) ||
+	    (data->stream.settings.enabled.motion &&
+	      data->stream.settings.opt.motion == SENSOR_STREAM_DATA_INCLUDE)) {
+		edata->header.channels |= pat9136_encode_channel(SENSOR_CHAN_POS_DXYZ);
+		edata->header.channels |= pat9136_encode_channel(SENSOR_CHAN_POS_DXYZ_MM);
+	}
+
+	if (data->stream.settings.enabled.drdy) {
+		start_drdy_backup_timer(dev);
+	}
+
+	/** Attempt chip recovery if erratic behavior is detected  */
+	if (!REG_OBSERVATION_READ_IS_VALID(edata->observation)) {
+
+		LOG_WRN("CHIP OK register indicates issues. Attempting chip recovery: 0x%02X",
+			edata->observation);
+
+		rtio_iodev_sqe_err(iodev_sqe, -EAGAIN);
+	} else {
+		rtio_iodev_sqe_ok(iodev_sqe, 0);
+	}
+}
+
+static void pat9136_stream_get_data(const struct device *dev)
+{
+	struct pat9136_data *data = dev->data;
+	uint64_t cycles;
+	int err;
+
+	CHECKIF(!data->stream.iodev_sqe) {
+		LOG_WRN("No RTIO submission with an INT GPIO event");
+		return;
+	}
+
+	/** This sensor may trigger data at a very fast pace (20,000 fps) and this
+	 * may not be useful for the application. Instead, it may affect its
+	 * proper functioning. Therefore, this timer keeps the INT line disabled
+	 * (which happens on every submission) until the cool-down the time has expired.
+	 * This, in order to "throttle" the interrupt-servicing rate of this sensor
+	 * (see: pat9136_stream_cooldown_timeout).
+	 *
+	 * Please note that this does not mean the sensor discards data: as the
+	 * value is accumulative until read by the application.
+	 */
+	start_drdy_cooldown_timer(dev);
+
+	struct pat9136_encoded_data *buf;
+	uint32_t buf_len;
+	uint32_t buf_len_required = sizeof(struct pat9136_encoded_data);
+
+	err = rtio_sqe_rx_buf(data->stream.iodev_sqe,
+			      buf_len_required,
+			      buf_len_required,
+			      (uint8_t **)&buf,
+			      &buf_len);
+	__ASSERT(err == 0, "Failed to acquire buffer (len: %d) for encoded data: %d. "
+			   "Please revisit RTIO queue sizing and look for "
+			   "bottlenecks during sensor data processing",
+			   buf_len_required, err);
+
+	/** Still throw an error even if asserts are off */
+	if (err) {
+		struct rtio_iodev_sqe *iodev_sqe = data->stream.iodev_sqe;
+
+		LOG_ERR("Failed to acquire buffer for encoded data: %d", err);
+
+		data->stream.iodev_sqe = NULL;
+		rtio_iodev_sqe_err(iodev_sqe, err);
+		return;
+	}
+
+	struct rtio_sqe *write_res_x_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	struct rtio_sqe *read_res_x_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	struct rtio_sqe *write_res_y_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	struct rtio_sqe *read_res_y_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	struct rtio_sqe *write_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	struct rtio_sqe *read_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	struct rtio_sqe *cb_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	uint8_t val;
+
+	err = sensor_clock_get_cycles(&cycles);
+	CHECKIF(err) {
+		struct rtio_iodev_sqe *iodev_sqe = data->stream.iodev_sqe;
+
+		LOG_ERR("Failed to get timestamp: %d", err);
+
+		data->stream.iodev_sqe = NULL;
+		rtio_iodev_sqe_err(iodev_sqe, err);
+		return;
+	}
+	buf->header.timestamp = sensor_clock_cycles_to_ns(cycles);
+
+	CHECKIF(!write_res_x_sqe || !read_res_x_sqe ||
+		!write_res_y_sqe || !read_res_y_sqe ||
+		!write_sqe || !read_sqe || !cb_sqe) {
+		LOG_ERR("Failed to acquire RTIO SQE's. Dropping all pending SQE's");
+		rtio_sqe_drop_all(data->rtio.ctx);
+
+		data->stream.iodev_sqe = NULL;
+		rtio_iodev_sqe_err(data->stream.iodev_sqe, -ENOMEM);
+		return;
+	}
+
+	/* X Resolution used for decoding DXY in mm */
+	{
+		val = REG_RESOLUTION_X_LOWER | REG_SPI_READ_BIT;
+
+		rtio_sqe_prep_tiny_write(write_res_x_sqe,
+					 data->rtio.iodev,
+					 RTIO_PRIO_HIGH,
+					 &val,
+					 1,
+					 NULL);
+		write_res_x_sqe->flags |= RTIO_SQE_TRANSACTION;
+
+		rtio_sqe_prep_read(read_res_x_sqe,
+				   data->rtio.iodev,
+				   RTIO_PRIO_HIGH,
+				   &buf->header.resolution.buf[0],
+				   1,
+				   NULL);
+		read_res_x_sqe->flags |= RTIO_SQE_CHAINED;
+	}
+
+	/* Y Resolution used for decoding DY in mm */
+	{
+		val = REG_RESOLUTION_Y_LOWER | REG_SPI_READ_BIT;
+
+		rtio_sqe_prep_tiny_write(write_res_y_sqe,
+					 data->rtio.iodev,
+					 RTIO_PRIO_HIGH,
+					 &val,
+					 1,
+					 NULL);
+		write_res_y_sqe->flags |= RTIO_SQE_TRANSACTION;
+
+		rtio_sqe_prep_read(read_res_y_sqe,
+				   data->rtio.iodev,
+				   RTIO_PRIO_HIGH,
+				   &buf->header.resolution.buf[2],
+				   1,
+				   NULL);
+		read_res_y_sqe->flags |= RTIO_SQE_CHAINED;
+	}
+
+	/* Pull out data */
+	{
+		val = REG_BURST_READ | REG_SPI_READ_BIT;
+
+		rtio_sqe_prep_tiny_write(write_sqe,
+					 data->rtio.iodev,
+					 RTIO_PRIO_HIGH,
+					 &val,
+					 1,
+					 NULL);
+		write_sqe->flags |= RTIO_SQE_TRANSACTION;
+
+		rtio_sqe_prep_read(read_sqe,
+				   data->rtio.iodev,
+				   RTIO_PRIO_HIGH,
+				   buf->buf,
+				   sizeof(buf->buf),
+				   NULL);
+		read_sqe->flags |= RTIO_SQE_CHAINED;
+	}
+
+	rtio_sqe_prep_callback_no_cqe(cb_sqe,
+				      pat9136_complete_result,
+				      (void *)dev,
+				      buf);
+
+	rtio_submit(data->rtio.ctx, 0);
+}
+
+static void pat9136_gpio_callback(const struct device *gpio_dev,
+				  struct gpio_callback *cb,
+				  uint32_t pins)
+{
+	struct pat9136_stream *stream = CONTAINER_OF(cb,
+						     struct pat9136_stream,
+						     cb);
+	const struct device *dev = stream->dev;
+	const struct pat9136_config *cfg = dev->config;
+	int err;
+
+	/* Disable interrupts until cool-down expires */
+	err = gpio_pin_interrupt_configure_dt(&cfg->int_gpio,
+					      GPIO_INT_MODE_DISABLED);
+	if (err) {
+		LOG_ERR("Failed to disable interrupt");
+		return;
+	}
+
+	pat9136_stream_get_data(dev);
+}
+
+static void pat9136_stream_drdy_timeout(struct k_timer *timer)
+{
+	struct pat9136_stream *stream = CONTAINER_OF(timer,
+						     struct pat9136_stream,
+						     timer.backup);
+	const struct device *dev = stream->dev;
+	const struct pat9136_config *cfg = dev->config;
+	int err;
+
+	/* Disable interrupts */
+	err = gpio_pin_interrupt_configure_dt(&cfg->int_gpio,
+					      GPIO_INT_MODE_DISABLED);
+	if (err) {
+		LOG_ERR("Failed to disable interrupt");
+		return;
+	}
+
+	pat9136_stream_get_data(dev);
+}
+
+static void pat9136_stream_cooldown_timeout(struct k_timer *timer)
+{
+	struct pat9136_stream *stream = CONTAINER_OF(timer,
+						     struct pat9136_stream,
+						     timer.cooldown.timer);
+	const struct device *dev = stream->dev;
+	const struct pat9136_config *cfg = dev->config;
+	int err;
+
+	/** Disarm Cooldown timer as it has expired. Needs another
+	 * submission to re-enable.
+	 */
+	if (!atomic_cas(&stream->timer.cooldown.armed, 1, 0)) {
+		return;
+	}
+
+	/* Re-enable interrupts */
+	err = gpio_pin_interrupt_configure_dt(&cfg->int_gpio,
+					      GPIO_INT_LEVEL_ACTIVE);
+	if (err) {
+		LOG_ERR("Failed to enable interrupt");
+		return;
+	}
+}
+
+static inline bool settings_changed(const struct pat9136_stream *a,
+				    const struct pat9136_stream *b)
+{
+	return (a->settings.enabled.drdy != b->settings.enabled.drdy) ||
+	       (a->settings.opt.drdy != b->settings.opt.drdy) ||
+	       (a->settings.enabled.motion != b->settings.enabled.motion) ||
+	       (a->settings.opt.motion != b->settings.opt.motion);
+}
+
+void pat9136_stream_submit(const struct device *dev,
+			   struct rtio_iodev_sqe *iodev_sqe)
+{
+	const struct sensor_read_config *read_config = iodev_sqe->sqe.iodev->data;
+	struct pat9136_data *data = dev->data;
+	const struct pat9136_config *cfg = dev->config;
+	int err;
+
+	/** This separate struct is required due to the streaming API using a
+	 * multi-shot RTIO submission: meaning, re-submitting itself after
+	 * completion; hence, we don't have context to determine if this was
+	 * the first submission that kicked things off. We're then, inferring
+	 * this by comparing if the read-config has changed, and only restart
+	 * in such case.
+	 */
+	struct pat9136_stream stream = {0};
+
+	for (size_t i = 0 ; i < read_config->count ; i++) {
+		switch (read_config->channels[i].chan_type) {
+		case SENSOR_TRIG_DATA_READY:
+			stream.settings.enabled.drdy = true;
+			stream.settings.opt.drdy = read_config->triggers[i].opt;
+			break;
+		case SENSOR_TRIG_MOTION:
+			stream.settings.enabled.motion = true;
+			stream.settings.opt.motion = read_config->triggers[i].opt;
+			break;
+		default:
+			LOG_ERR("Unsupported trigger (%d)", read_config->triggers[i].trigger);
+			rtio_iodev_sqe_err(iodev_sqe, -ENOTSUP);
+			return;
+		}
+	}
+
+	/* Store context for next submission (handled within callbacks) */
+	data->stream.iodev_sqe = iodev_sqe;
+
+	if (settings_changed(&data->stream, &stream)) {
+		uint8_t motion_data[6];
+
+		data->stream.settings = stream.settings;
+
+		/* Disable interrupts */
+		err = gpio_pin_interrupt_configure_dt(&cfg->int_gpio,
+						      GPIO_INT_MODE_DISABLED);
+		if (err) {
+			LOG_ERR("Failed to disable interrupt");
+			data->stream.iodev_sqe = NULL;
+			rtio_iodev_sqe_err(iodev_sqe, err);
+			return;
+		}
+
+		/* Read reg's 0x02-0x06 to clear motion data. */
+		err = pat9136_bus_read(dev, REG_MOTION, motion_data, sizeof(motion_data));
+		if (err) {
+			LOG_ERR("Failed to read motion data");
+			data->stream.iodev_sqe = NULL;
+			rtio_iodev_sqe_err(iodev_sqe, err);
+			return;
+		}
+
+		/** Re-enable interrupts if settings changed. Otherwise wait
+		 * for cooldown timeout in the event of periodic streaming
+		 * submission.
+		 */
+		err = gpio_pin_interrupt_configure_dt(&cfg->int_gpio,
+						      GPIO_INT_LEVEL_ACTIVE);
+		if (err) {
+			LOG_ERR("Failed to enable interrupt");
+			data->stream.iodev_sqe = NULL;
+			rtio_iodev_sqe_err(iodev_sqe, err);
+			return;
+		}
+	}
+
+	/** Back-up timer allows us to keep checking in with the sensor in
+	 * spite of not having any motion. This results in allowing sensor
+	 * recovery if falling in erratic state.
+	 */
+	if (data->stream.settings.enabled.drdy) {
+		start_drdy_backup_timer(dev);
+	}
+
+	/** Arm cooldown timer once for each submission. */
+	atomic_set(&data->stream.timer.cooldown.armed, 1);
+}
+
+int pat9136_stream_init(const struct device *dev)
+{
+	const struct pat9136_config *cfg = dev->config;
+	struct pat9136_data *data = dev->data;
+	int err;
+
+	/** Needed to get back the device handle from the callback context */
+	data->stream.dev = dev;
+
+	if (!cfg->int_gpio.port) {
+		LOG_ERR("Interrupt GPIO not supplied");
+		return -ENODEV;
+	}
+
+	if (!gpio_is_ready_dt(&cfg->int_gpio)) {
+		LOG_ERR("Interrupt GPIO not ready");
+		return -ENODEV;
+	}
+
+	err = gpio_pin_configure_dt(&cfg->int_gpio, GPIO_INPUT);
+	if (err) {
+		LOG_ERR("Failed to configure interrupt GPIO");
+		return -EIO;
+	}
+
+	gpio_init_callback(&data->stream.cb,
+			   pat9136_gpio_callback,
+			   BIT(cfg->int_gpio.pin));
+
+	err = gpio_add_callback(cfg->int_gpio.port, &data->stream.cb);
+	if (err) {
+		LOG_ERR("Failed to add interrupt callback");
+		return -EIO;
+	}
+
+	k_timer_init(&data->stream.timer.backup, pat9136_stream_drdy_timeout, NULL);
+	k_timer_init(&data->stream.timer.cooldown.timer, pat9136_stream_cooldown_timeout, NULL);
+
+	atomic_clear(&data->stream.timer.cooldown.armed);
+
+	return err;
+}
diff --git a/drivers/sensor/pixart/pat9136/pat9136_stream.h b/drivers/sensor/pixart/pat9136/pat9136_stream.h
new file mode 100644
index 00000000000..d7af57770d2
--- /dev/null
+++ b/drivers/sensor/pixart/pat9136/pat9136_stream.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/rtio/rtio.h>
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_PAT9136_STREAM_H_
+#define ZEPHYR_DRIVERS_SENSOR_PAT9136_STREAM_H_
+
+int pat9136_stream_init(const struct device *dev);
+
+void pat9136_stream_submit(const struct device *dev,
+			   struct rtio_iodev_sqe *iodev_sqe);
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_PAT9136_STREAM_H_ */
diff --git a/drivers/sensor/realtek/CMakeLists.txt b/drivers/sensor/realtek/CMakeLists.txt
new file mode 100644
index 00000000000..c69984afe4a
--- /dev/null
+++ b/drivers/sensor/realtek/CMakeLists.txt
@@ -0,0 +1,4 @@
+# Copyright (c) 2025, Realtek, SIBG-SD7
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory_ifdef(CONFIG_TACH_RTS5912 rts5912)
diff --git a/drivers/sensor/realtek/Kconfig b/drivers/sensor/realtek/Kconfig
new file mode 100644
index 00000000000..bca4a9dcc89
--- /dev/null
+++ b/drivers/sensor/realtek/Kconfig
@@ -0,0 +1,4 @@
+# Copyright (c) 2025, Realtek, SIBG-SD7
+# SPDX-License-Identifier: Apache-2.0
+
+source "drivers/sensor/realtek/rts5912/Kconfig"
diff --git a/drivers/sensor/realtek/rts5912/CMakeLists.txt b/drivers/sensor/realtek/rts5912/CMakeLists.txt
new file mode 100644
index 00000000000..bc870db466b
--- /dev/null
+++ b/drivers/sensor/realtek/rts5912/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2025, Realtek, SIBG-SD7
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(rts5912.c)
diff --git a/drivers/sensor/realtek/rts5912/Kconfig b/drivers/sensor/realtek/rts5912/Kconfig
new file mode 100644
index 00000000000..649567dfab1
--- /dev/null
+++ b/drivers/sensor/realtek/rts5912/Kconfig
@@ -0,0 +1,9 @@
+# Copyright (c) 2025, Realtek, SIBG-SD7
+# SPDX-License-Identifier: Apache-2.0
+
+config TACH_RTS5912
+	bool "RTS5912 Tachometer sensor"
+	default y
+	depends on DT_HAS_REALTEK_RTS5912_TACH_ENABLED
+	help
+	  Enable the Realtek RTS5912 tachometer sensor.
diff --git a/drivers/sensor/realtek/rts5912/rts5912.c b/drivers/sensor/realtek/rts5912/rts5912.c
new file mode 100644
index 00000000000..5b6fcf740d2
--- /dev/null
+++ b/drivers/sensor/realtek/rts5912/rts5912.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright (c) 2025 Realtek, SIBG-SD7
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT realtek_rts5912_tach
+
+#include <errno.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/clock_control_rts5912.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/sys/sys_io.h>
+#include <zephyr/logging/log.h>
+
+#include "reg/reg_tacho.h"
+
+LOG_MODULE_REGISTER(tach_rts5912, CONFIG_SENSOR_LOG_LEVEL);
+
+struct tach_rts5912_config {
+	volatile struct tacho_regs *regs;
+	uint32_t clk_grp;
+	uint32_t clk_idx;
+	uint32_t clk_src;
+	uint32_t clk_div;
+	const struct device *clk_dev;
+	const struct pinctrl_dev_config *pcfg;
+	int pulses_per_round;
+};
+
+struct tach_rts5912_data {
+	uint16_t count;
+};
+
+#define COUNT_100KHZ_SEC  100000U
+#define SEC_TO_MINUTE     60U
+#define PIN_STUCK_TIMEOUT (100U * USEC_PER_MSEC)
+
+int tach_rts5912_sample_fetch(const struct device *dev, enum sensor_channel chan)
+{
+	const struct tach_rts5912_config *const cfg = dev->config;
+	struct tach_rts5912_data *const data = dev->data;
+	volatile struct tacho_regs *const tach = cfg->regs;
+
+	if (chan != SENSOR_CHAN_RPM && chan != SENSOR_CHAN_ALL) {
+		return -ENOTSUP;
+	}
+
+	tach->status = TACHO_STS_CNTRDY;
+
+	if (WAIT_FOR(tach->status & TACHO_STS_CNTRDY, PIN_STUCK_TIMEOUT, k_msleep(1))) {
+		/* See whether internal counter is already latched */
+		if (tach->status & TACHO_STS_CNTRDY) {
+			tach->status = TACHO_STS_CNTRDY;
+			data->count = (tach->ctrl & TACHO_CTRL_CNT_Msk) >> TACHO_CTRL_CNT_Pos;
+		}
+	} else {
+		data->count = 0;
+	}
+
+	return 0;
+}
+
+static int tach_rts5912_channel_get(const struct device *dev, enum sensor_channel chan,
+				    struct sensor_value *val)
+{
+	const struct tach_rts5912_config *const cfg = dev->config;
+	struct tach_rts5912_data *const data = dev->data;
+
+	if (chan != SENSOR_CHAN_RPM) {
+		return -ENOTSUP;
+	}
+
+	/* Convert the count per 100khz cycles to rpm */
+	if (data->count != 0U) {
+		val->val1 =
+			(SEC_TO_MINUTE * COUNT_100KHZ_SEC) / (cfg->pulses_per_round * data->count);
+	} else {
+		val->val1 = 0U;
+	}
+
+	val->val2 = 0U;
+
+	return 0;
+}
+
+static int tach_rts5912_init(const struct device *dev)
+{
+	const struct tach_rts5912_config *const cfg = dev->config;
+	volatile struct tacho_regs *const tach = cfg->regs;
+	int ret;
+
+	struct rts5912_sccon_subsys sccon_subsys = {
+		.clk_grp = cfg->clk_grp,
+		.clk_idx = cfg->clk_idx,
+	};
+
+	if (!device_is_ready(cfg->clk_dev)) {
+		return -ENODEV;
+	}
+
+	ret = clock_control_on(cfg->clk_dev, (clock_control_subsys_t)&sccon_subsys);
+	if (ret != 0) {
+		LOG_ERR("RTS5912 Tachometer clock control failed (%d)", ret);
+		return ret;
+	}
+
+#ifdef CONFIG_PINCTRL
+	ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
+
+	if (ret != 0) {
+		LOG_ERR("RTS5912 pinctrl failed (%d)", ret);
+		return ret;
+	}
+#endif
+
+	/* write one clear the status */
+	tach->status = TACHO_STS_LIMIT | TACHO_STS_CHG | TACHO_STS_CNTRDY;
+	tach->ctrl &= ~TACHO_CTRL_SELEDGE_Msk;
+	tach->ctrl = ((0x01ul << TACHO_CTRL_SELEDGE_Pos) | TACHO_CTRL_READMODE | TACHO_CTRL_EN);
+
+	return 0;
+}
+
+static DEVICE_API(sensor, tach_rts5912_driver_api) = {
+	.sample_fetch = tach_rts5912_sample_fetch,
+	.channel_get = tach_rts5912_channel_get,
+};
+
+#define REALTEK_TACH_INIT(inst)                                                                    \
+	PINCTRL_DT_INST_DEFINE(inst);                                                              \
+                                                                                                   \
+	static const struct tach_rts5912_config tach_cfg_##inst = {                                \
+		.regs = (struct tacho_regs *const)DT_INST_REG_ADDR(inst),                          \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),                                      \
+		.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)),                               \
+		.clk_grp = DT_INST_CLOCKS_CELL_BY_NAME(inst, tacho, clk_grp),                      \
+		.clk_idx = DT_INST_CLOCKS_CELL_BY_NAME(inst, tacho, clk_idx),                      \
+		.pulses_per_round = DT_INST_PROP(inst, pulses_per_round),                          \
+	};                                                                                         \
+                                                                                                   \
+	static struct tach_rts5912_data tach_data_##inst;                                          \
+                                                                                                   \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, tach_rts5912_init, NULL, &tach_data_##inst,             \
+				     &tach_cfg_##inst, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY,   \
+				     &tach_rts5912_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(REALTEK_TACH_INIT)
diff --git a/drivers/sensor/renesas/hs400x/hs400x.c b/drivers/sensor/renesas/hs400x/hs400x.c
index a739a0256da..44f6f394ef3 100644
--- a/drivers/sensor/renesas/hs400x/hs400x.c
+++ b/drivers/sensor/renesas/hs400x/hs400x.c
@@ -80,9 +80,9 @@ static int hs400x_sample_fetch(const struct device *dev, enum sensor_channel cha
 
 	/*
 	 * According to datasheet maximum time to make temperature and humidity
-	 * measurements is 33ms, add a little safety margin...
+	 * measurements is 1.7 ms, add a little safety margin...
 	 */
-	k_msleep(50);
+	k_msleep(3);
 
 	rc = hs400x_read_sample(dev, &data->t_sample, &data->rh_sample);
 	if (rc < 0) {
@@ -137,15 +137,45 @@ static int hs400x_channel_get(const struct device *dev, enum sensor_channel chan
 	return 0;
 }
 
+static void hs400x_all_measurements_stop(const struct device *dev)
+{
+	const struct hs400x_config *cfg = dev->config;
+	const uint8_t periodic_measurement_stop = 0x30;
+	uint8_t dummy[2];
+
+	/*
+	 * Stop previous periodic measurement.
+	 * If a periodic measurement is not running, HS400x device replies with NACK.
+	 */
+	i2c_write_dt(&cfg->bus, &periodic_measurement_stop, 1);
+
+	/*
+	 * Clear previous no-hold measurement.
+	 * If a measurement is not complete, HS400x device replies with NACK.
+	 */
+	i2c_read_dt(&cfg->bus, dummy, 2);
+}
+
 static int hs400x_init(const struct device *dev)
 {
 	const struct hs400x_config *cfg = dev->config;
+	const uint8_t reset_command = 0xFE;
+	int rc;
 
 	if (!i2c_is_ready_dt(&cfg->bus)) {
 		LOG_ERR("I2C dev %s not ready", cfg->bus.bus->name);
 		return -ENODEV;
 	}
 
+	hs400x_all_measurements_stop(dev);
+
+	rc = i2c_write_dt(&cfg->bus, &reset_command, 1);
+	if (rc < 0) {
+		LOG_ERR("Failed to send reset command.");
+		return rc;
+	}
+	k_msleep(500);
+
 	return 0;
 }
 
diff --git a/drivers/sensor/sensirion/scd4x/scd4x.c b/drivers/sensor/sensirion/scd4x/scd4x.c
index e989c155d50..cdefce2d5c5 100644
--- a/drivers/sensor/sensirion/scd4x/scd4x.c
+++ b/drivers/sensor/sensirion/scd4x/scd4x.c
@@ -630,7 +630,7 @@ static int scd4x_channel_get(const struct device *dev, enum sensor_channel chan,
 			     struct sensor_value *val)
 {
 	const struct scd4x_data *data = dev->data;
-	int32_t tmp_val;
+	int64_t tmp_val;
 
 	switch ((enum sensor_channel)chan) {
 	case SENSOR_CHAN_AMBIENT_TEMP:
diff --git a/drivers/sensor/sensirion/scd4x/scd4x.h b/drivers/sensor/sensirion/scd4x/scd4x.h
index 3955d202199..2e7c8e0dcc4 100644
--- a/drivers/sensor/sensirion/scd4x/scd4x.h
+++ b/drivers/sensor/sensirion/scd4x/scd4x.h
@@ -29,7 +29,7 @@
 #define SCD4X_CMD_FACTORY_RESET                  17
 #define SCD4X_CMD_MEASURE_SINGLE_SHOT            18
 #define SCD4X_CMD_MEASURE_SINGLE_SHOT_RHT        19
-#define SCD4X_CMD_POWER_DOWN                     10
+#define SCD4X_CMD_POWER_DOWN                     20
 #define SCD4X_CMD_WAKE_UP                        21
 #define SCD4X_CMD_SET_SELF_CALIB_INITIAL_PERIOD  22
 #define SCD4X_CMD_GET_SELF_CALIB_INITIAL_PERIOD  23
diff --git a/drivers/sensor/sensor_clock_external.c b/drivers/sensor/sensor_clock_external.c
new file mode 100644
index 00000000000..5baf1ac1563
--- /dev/null
+++ b/drivers/sensor/sensor_clock_external.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2024 Cienet
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/drivers/counter.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/init.h>
+
+LOG_MODULE_REGISTER(sensor_clock, CONFIG_SENSOR_LOG_LEVEL);
+
+static const struct device *external_sensor_clock = DEVICE_DT_GET(DT_CHOSEN(zephyr_sensor_clock));
+static uint32_t freq;
+
+static int external_sensor_clock_init(void)
+{
+	int rc;
+
+	rc = counter_start(external_sensor_clock);
+	if (rc != 0) {
+		LOG_ERR("Failed to start sensor clock counter: %d\n", rc);
+		return rc;
+	}
+
+	freq = counter_get_frequency(external_sensor_clock);
+	if (freq == 0) {
+		LOG_ERR("Sensor clock %s has no fixed frequency\n", external_sensor_clock->name);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int sensor_clock_get_cycles(uint64_t *cycles)
+{
+	__ASSERT_NO_MSG(counter_is_counting_up(external_sensor_clock));
+
+	int rc;
+	const struct counter_driver_api *api =
+		(const struct counter_driver_api *)external_sensor_clock->api;
+
+	if (api->get_value_64) {
+		rc = counter_get_value_64(external_sensor_clock, cycles);
+	} else {
+		uint32_t result_32;
+
+		rc = counter_get_value(external_sensor_clock, &result_32);
+		*cycles = (uint64_t)result_32;
+	}
+
+	return rc;
+}
+
+uint64_t sensor_clock_cycles_to_ns(uint64_t cycles)
+{
+	return (cycles * NSEC_PER_SEC) / freq;
+}
+
+SYS_INIT(external_sensor_clock_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
diff --git a/drivers/sensor/sensor_clock_sys.c b/drivers/sensor/sensor_clock_sys.c
new file mode 100644
index 00000000000..e9829268466
--- /dev/null
+++ b/drivers/sensor/sensor_clock_sys.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2024 Cienet
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/sensor_clock.h>
+#include <zephyr/sys_clock.h>
+
+int sensor_clock_get_cycles(uint64_t *cycles)
+{
+	if (cycles == NULL) {
+		return -EINVAL;
+	}
+
+#ifdef CONFIG_TIMER_HAS_64BIT_CYCLE_COUNTER
+	*cycles = k_cycle_get_64();
+#else
+	*cycles = (uint64_t)k_cycle_get_32();
+#endif
+
+	return 0;
+}
+
+uint64_t sensor_clock_cycles_to_ns(uint64_t cycles)
+{
+	return (cycles * NSEC_PER_SEC) / sys_clock_hw_cycles_per_sec();
+}
diff --git a/drivers/sensor/sensor_shell.c b/drivers/sensor/sensor_shell.c
index b8e8be269c2..775c53d009f 100644
--- a/drivers/sensor/sensor_shell.c
+++ b/drivers/sensor/sensor_shell.c
@@ -88,6 +88,7 @@ static const char *sensor_channel_name[SENSOR_CHAN_COMMON_COUNT] = {
 	[SENSOR_CHAN_POS_DZ] = "pos_dz",
 	[SENSOR_CHAN_POS_DXYZ] = "pos_dxyz",
 	[SENSOR_CHAN_RPM] = "rpm",
+	[SENSOR_CHAN_FREQUENCY] = "frequency",
 	[SENSOR_CHAN_GAUGE_VOLTAGE] = "gauge_voltage",
 	[SENSOR_CHAN_GAUGE_AVG_CURRENT] = "gauge_avg_current",
 	[SENSOR_CHAN_GAUGE_STDBY_CURRENT] = "gauge_stdby_current",
@@ -282,7 +283,7 @@ static int parse_sensor_value(const char *val_str, struct sensor_value *out)
 {
 	const bool is_negative = val_str[0] == '-';
 	const char *decimal_pos = strchr(val_str, '.');
-	long value;
+	int64_t value;
 	char *endptr;
 
 	/* Parse int portion */
@@ -364,23 +365,6 @@ void sensor_shell_processing_callback(int result, uint8_t *buf, uint32_t buf_len
 		size_t frame_size;
 		uint16_t frame_count;
 
-		/* Channels with multi-axis equivalents are skipped */
-		switch (ch.chan_type) {
-		case SENSOR_CHAN_ACCEL_X:
-		case SENSOR_CHAN_ACCEL_Y:
-		case SENSOR_CHAN_ACCEL_Z:
-		case SENSOR_CHAN_GYRO_X:
-		case SENSOR_CHAN_GYRO_Y:
-		case SENSOR_CHAN_GYRO_Z:
-		case SENSOR_CHAN_MAGN_X:
-		case SENSOR_CHAN_MAGN_Y:
-		case SENSOR_CHAN_MAGN_Z:
-		case SENSOR_CHAN_POS_DX:
-		case SENSOR_CHAN_POS_DY:
-		case SENSOR_CHAN_POS_DZ:
-			continue;
-		}
-
 		rc = decoder->get_size_info(ch, &base_size, &frame_size);
 		if (rc != 0) {
 			LOG_DBG("skipping unsupported channel %s:%d",
@@ -869,7 +853,7 @@ static void device_name_get(size_t idx, struct shell_static_entry *entry)
 
 static void device_name_get_for_attr(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_lookup(idx, NULL);
+	const struct device *dev = shell_device_filter(idx, sensor_device_check);
 
 	current_cmd_ctx = CTX_ATTR_GET_SET;
 	entry->syntax = (dev != NULL) ? dev->name : NULL;
@@ -924,7 +908,7 @@ SHELL_DYNAMIC_CMD_CREATE(dsub_trigger_onoff, trigger_on_off_get);
 
 static void device_name_get_for_trigger(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_lookup(idx, NULL);
+	const struct device *dev = shell_device_filter(idx, sensor_device_check);
 
 	entry->syntax = (dev != NULL) ? dev->name : NULL;
 	entry->handler = NULL;
@@ -936,7 +920,7 @@ SHELL_DYNAMIC_CMD_CREATE(dsub_trigger, device_name_get_for_trigger);
 
 static void device_name_get_for_stream(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_lookup(idx, NULL);
+	const struct device *dev = shell_device_filter(idx, sensor_device_check);
 
 	current_cmd_ctx = CTX_STREAM_ON_OFF;
 	entry->syntax = (dev != NULL) ? dev->name : NULL;
diff --git a/drivers/sensor/silabs/si7006/Kconfig b/drivers/sensor/silabs/si7006/Kconfig
index 37872744bdd..33b2a95b9a0 100644
--- a/drivers/sensor/silabs/si7006/Kconfig
+++ b/drivers/sensor/silabs/si7006/Kconfig
@@ -6,6 +6,7 @@ config SI7006
 	default y
 	depends on DT_HAS_SILABS_SI7006_ENABLED || DT_HAS_SENSIRION_SHT21_ENABLED
 	select I2C
+	select REGULATOR if $(dt_compat_any_has_prop,$(DT_COMPAT_SILABS_SI7006),vin-supply)
 	help
 	  Enable I2C-based driver for several humidity and temperature sensors
 	  compatible with the Sensirion SHT21, such as the Silicon Labs
diff --git a/drivers/sensor/silabs/si7006/si7006.c b/drivers/sensor/silabs/si7006/si7006.c
index bbfe67df49a..90e33a2e55a 100644
--- a/drivers/sensor/silabs/si7006/si7006.c
+++ b/drivers/sensor/silabs/si7006/si7006.c
@@ -7,11 +7,11 @@
 
 #include <zephyr/device.h>
 #include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/regulator.h>
 #include <zephyr/drivers/sensor.h>
 #include <zephyr/kernel.h>
 #include <zephyr/sys/byteorder.h>
 #include <zephyr/sys/__assert.h>
-#include <zephyr/drivers/i2c.h>
 #include <stdio.h>
 #include <stdlib.h>
 #include <zephyr/sys/util.h>
@@ -27,6 +27,7 @@ struct si7006_data {
 
 struct si7006_config {
 	struct i2c_dt_spec i2c;
+	const struct device *vin_supply;
 	/** Use "read temp" vs "read old temp" command, the latter only with SiLabs sensors. */
 	uint8_t read_temp_cmd;
 };
@@ -192,6 +193,13 @@ static int si7006_init(const struct device *dev)
 		return -ENODEV;
 	}
 
+	if (IS_ENABLED(CONFIG_REGULATOR) && config->vin_supply) {
+		regulator_enable(config->vin_supply);
+
+		/* As stated by the Si7006 spec - Maximum powerup time is 80ms */
+		k_msleep(80);
+	}
+
 	LOG_DBG("si7006 init ok");
 
 	return 0;
@@ -202,6 +210,7 @@ static int si7006_init(const struct device *dev)
 											\
 	static const struct si7006_config si7006_config_##name##_##inst = {		\
 		.i2c = I2C_DT_SPEC_INST_GET(inst),					\
+		.vin_supply = DEVICE_DT_GET_OR_NULL(DT_INST_PHANDLE(inst, vin_supply)),	\
 		.read_temp_cmd = temp_cmd,						\
 	};										\
 											\
diff --git a/drivers/sensor/silabs/si7055/si7055.c b/drivers/sensor/silabs/si7055/si7055.c
index 198e8e6e35b..96943110fdf 100644
--- a/drivers/sensor/silabs/si7055/si7055.c
+++ b/drivers/sensor/silabs/si7055/si7055.c
@@ -101,14 +101,13 @@ static int si7055_channel_get(const struct device *dev,
 
 	if (chan == SENSOR_CHAN_AMBIENT_TEMP) {
 
-		int32_t temp_ucelcius = (((SI7055_CONV_FACTOR_1 *
-					(int32_t)si_data->temperature) /
-					(__UINT16_MAX__ + 1)) -
-					SI7055_CONV_FACTOR_2) *
+		int32_t temp_ucelsius = (((SI7055_CONV_FACTOR_1 * (int32_t)si_data->temperature) /
+					  (__UINT16_MAX__ + 1)) -
+					 SI7055_CONV_FACTOR_2) *
 					SI7055_MULTIPLIER;
 
-		val->val1 = temp_ucelcius / SI7055_DIVIDER;
-		val->val2 = temp_ucelcius % SI7055_DIVIDER;
+		val->val1 = temp_ucelsius / SI7055_DIVIDER;
+		val->val2 = temp_ucelsius % SI7055_DIVIDER;
 
 		LOG_DBG("temperature = val1:%d, val2:%d",
 			val->val1, val->val2);
diff --git a/drivers/sensor/silabs/si7060/si7060.c b/drivers/sensor/silabs/si7060/si7060.c
index 47bd44669ab..ec98709f3e7 100644
--- a/drivers/sensor/silabs/si7060/si7060.c
+++ b/drivers/sensor/silabs/si7060/si7060.c
@@ -58,15 +58,20 @@ static int si7060_sample_fetch(const struct device *dev,
 	uint8_t dspsigl;
 
 	retval = si7060_reg_read(dev, SI7060_REG_TEMP_HIGH, &dspsigm);
-	retval += si7060_reg_read(dev, SI7060_REG_TEMP_LOW, &dspsigl);
+	if (retval != 0) {
+		LOG_ERR("Error reading temperature high register");
+		return retval;
+	}
 
-	if (retval == 0) {
-		drv_data->temperature = (256 * (dspsigm & SIGN_BIT_MASK))
-		+ dspsigl;
-	} else {
-		LOG_ERR("Read register err");
+	retval = si7060_reg_read(dev, SI7060_REG_TEMP_LOW, &dspsigl);
+	if (retval != 0) {
+		LOG_ERR("Error reading temperature low register");
+		return retval;
 	}
 
+	drv_data->temperature = (256 * (dspsigm & SIGN_BIT_MASK))
+	+ dspsigl;
+
 	LOG_DBG("Sample_fetch retval: %d", retval);
 
 	return retval;
diff --git a/drivers/sensor/st/Kconfig b/drivers/sensor/st/Kconfig
index 79a57bb6168..a38b1210941 100644
--- a/drivers/sensor/st/Kconfig
+++ b/drivers/sensor/st/Kconfig
@@ -37,6 +37,7 @@ source "drivers/sensor/st/stm32_digi_temp/Kconfig"
 source "drivers/sensor/st/stm32_temp/Kconfig"
 source "drivers/sensor/st/stm32_vbat/Kconfig"
 source "drivers/sensor/st/stm32_vref/Kconfig"
+source "drivers/sensor/st/stmemsc/Kconfig"
 source "drivers/sensor/st/stts22h/Kconfig"
 source "drivers/sensor/st/stts751/Kconfig"
 source "drivers/sensor/st/vl53l0x/Kconfig"
diff --git a/drivers/sensor/st/hts221/hts221.c b/drivers/sensor/st/hts221/hts221.c
index 9cc8f5afc94..6dbb771207a 100644
--- a/drivers/sensor/st/hts221/hts221.c
+++ b/drivers/sensor/st/hts221/hts221.c
@@ -72,7 +72,8 @@ static int hts221_sample_fetch(const struct device *dev,
 	uint8_t buf[4];
 	int status;
 
-	__ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL);
+	__ASSERT_NO_MSG(chan == SENSOR_CHAN_HUMIDITY || chan == SENSOR_CHAN_AMBIENT_TEMP ||
+			chan == SENSOR_CHAN_ALL);
 
 	status = hts221_read_reg(ctx, HTS221_HUMIDITY_OUT_L |
 				 HTS221_AUTOINCREMENT_ADDR, buf, 4);
diff --git a/drivers/sensor/st/iis2iclx/iis2iclx.c b/drivers/sensor/st/iis2iclx/iis2iclx.c
index c7222a3ff07..864e13e2f57 100644
--- a/drivers/sensor/st/iis2iclx/iis2iclx.c
+++ b/drivers/sensor/st/iis2iclx/iis2iclx.c
@@ -65,20 +65,6 @@ static int iis2iclx_accel_range_to_fs_val(int32_t range)
 	return -EINVAL;
 }
 
-static inline int iis2iclx_reboot(const struct device *dev)
-{
-	const struct iis2iclx_config *cfg = dev->config;
-
-	if (iis2iclx_boot_set((stmdev_ctx_t *)&cfg->ctx, 1) < 0) {
-		return -EIO;
-	}
-
-	/* Wait sensor turn-on time as per datasheet */
-	k_msleep(35);
-
-	return 0;
-}
-
 static int iis2iclx_accel_set_fs_raw(const struct device *dev, uint8_t fs)
 {
 	const struct iis2iclx_config *cfg = dev->config;
diff --git a/drivers/sensor/st/iis3dhhc/iis3dhhc.c b/drivers/sensor/st/iis3dhhc/iis3dhhc.c
index 9b428db526f..dfa3e15e6ef 100644
--- a/drivers/sensor/st/iis3dhhc/iis3dhhc.c
+++ b/drivers/sensor/st/iis3dhhc/iis3dhhc.c
@@ -26,7 +26,7 @@ static int iis3dhhc_sample_fetch(const struct device *dev,
 	struct iis3dhhc_data *data = dev->data;
 	int16_t raw_accel[3];
 
-	__ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL);
+	__ASSERT_NO_MSG(chan == SENSOR_CHAN_ACCEL_XYZ || chan == SENSOR_CHAN_ALL);
 
 	iis3dhhc_acceleration_raw_get(data->ctx, raw_accel);
 	data->acc[0] = raw_accel[0];
diff --git a/drivers/sensor/st/ism330dhcx/ism330dhcx.c b/drivers/sensor/st/ism330dhcx/ism330dhcx.c
index c6f7087ddde..44b8506664e 100644
--- a/drivers/sensor/st/ism330dhcx/ism330dhcx.c
+++ b/drivers/sensor/st/ism330dhcx/ism330dhcx.c
@@ -104,20 +104,6 @@ static int ism330dhcx_gyro_range_to_fs_val(int32_t range)
 	return -EINVAL;
 }
 
-static inline int ism330dhcx_reboot(const struct device *dev)
-{
-	struct ism330dhcx_data *data = dev->data;
-
-	if (ism330dhcx_boot_set(data->ctx, 1) < 0) {
-		return -EIO;
-	}
-
-	/* Wait sensor turn-on time as per datasheet */
-	k_busy_wait(35 * USEC_PER_MSEC);
-
-	return 0;
-}
-
 static int ism330dhcx_accel_set_fs_raw(const struct device *dev, uint8_t fs)
 {
 	struct ism330dhcx_data *data = dev->data;
@@ -713,6 +699,15 @@ static int ism330dhcx_init_chip(const struct device *dev)
 
 	k_busy_wait(100);
 
+	/*
+	 * Set device_conf bit to 1 for a proper configuration
+	 * as stated in DS chapter paragraph 9.20
+	 */
+	if (ism330dhcx_device_conf_set(ism330dhcx->ctx, 1) < 0) {
+		LOG_DBG("Failed setting device_conf bit");
+		return -EIO;
+	}
+
 	LOG_DBG("accel range is %d", cfg->accel_range);
 	if (ism330dhcx_accel_range_set(dev, cfg->accel_range) < 0) {
 		LOG_DBG("failed to set accelerometer full-scale");
diff --git a/drivers/sensor/st/lis2de12/lis2de12.c b/drivers/sensor/st/lis2de12/lis2de12.c
index 77d5e59f018..bd32b66553a 100644
--- a/drivers/sensor/st/lis2de12/lis2de12.c
+++ b/drivers/sensor/st/lis2de12/lis2de12.c
@@ -435,7 +435,7 @@ static int lis2de12_init(const struct device *dev)
 
 #define LIS2DE12_CONFIG_SPI(inst)						\
 	{									\
-		STMEMSC_CTX_SPI(&lis2de12_config_##inst.stmemsc_cfg),		\
+		STMEMSC_CTX_SPI_INCR(&lis2de12_config_##inst.stmemsc_cfg),		\
 		.stmemsc_cfg = {						\
 			.spi = SPI_DT_SPEC_INST_GET(inst, LIS2DE12_SPI_OP, 0),	\
 		},								\
diff --git a/drivers/sensor/st/lis2dh/lis2dh.c b/drivers/sensor/st/lis2dh/lis2dh.c
index ec476ea53e2..1721fd963bf 100644
--- a/drivers/sensor/st/lis2dh/lis2dh.c
+++ b/drivers/sensor/st/lis2dh/lis2dh.c
@@ -271,6 +271,21 @@ static int lis2dh_acc_range_set(const struct device *dev, int32_t range)
 }
 #endif
 
+#ifdef CONFIG_LIS2DH_ACCEL_HP_FILTERS
+static int lis2dh_acc_hp_filter_set(const struct device *dev, int32_t val)
+{
+	struct lis2dh_data *lis2dh = dev->data;
+	int status;
+
+	status = lis2dh->hw_tf->write_reg(dev, LIS2DH_REG_CTRL2, val);
+	if (status < 0) {
+		LOG_ERR("Failed to set high pass filters");
+	}
+
+	return status;
+}
+#endif
+
 static int lis2dh_acc_config(const struct device *dev,
 			     enum sensor_channel chan,
 			     enum sensor_attribute attr,
diff --git a/drivers/sensor/st/lis2dh/lis2dh.h b/drivers/sensor/st/lis2dh/lis2dh.h
index f746e983e28..d18d8fb3cd8 100644
--- a/drivers/sensor/st/lis2dh/lis2dh.h
+++ b/drivers/sensor/st/lis2dh/lis2dh.h
@@ -87,9 +87,12 @@
 #define LIS2DH_REG_CTRL2		0x21
 #define LIS2DH_HPIS1_EN_BIT		BIT(0)
 #define LIS2DH_HPIS2_EN_BIT		BIT(1)
+#define LIS2DH_HPCLICK_EN_BIT		BIT(2)
 #define LIS2DH_FDS_EN_BIT		BIT(3)
-
-#define LIS2DH_HPIS_EN_MASK		BIT_MASK(2)
+#define LIS2DH_HPCF0_EN_BIT		BIT(4)
+#define LIS2DH_HPCF1_EN_BIT		BIT(5)
+#define LIS2DH_HPM0_EN_BIT		BIT(6)
+#define LIS2DH_HPM1_EN_BIT		BIT(7)
 
 #define LIS2DH_REG_CTRL3		0x22
 #define LIS2DH_EN_CLICK_INT1		BIT(7)
@@ -305,11 +308,6 @@ int lis2dh_acc_slope_config(const struct device *dev,
 			    const struct sensor_value *val);
 #endif
 
-#ifdef CONFIG_LIS2DH_ACCEL_HP_FILTERS
-int lis2dh_acc_hp_filter_set(const struct device *dev,
-			     int32_t val);
-#endif
-
 int lis2dh_spi_init(const struct device *dev);
 int lis2dh_i2c_init(const struct device *dev);
 
diff --git a/drivers/sensor/st/lis2dh/lis2dh_trigger.c b/drivers/sensor/st/lis2dh/lis2dh_trigger.c
index 16b0ea52fb8..eb24bba445c 100644
--- a/drivers/sensor/st/lis2dh/lis2dh_trigger.c
+++ b/drivers/sensor/st/lis2dh/lis2dh_trigger.c
@@ -361,22 +361,6 @@ int lis2dh_acc_slope_config(const struct device *dev,
 	return status;
 }
 
-#ifdef CONFIG_LIS2DH_ACCEL_HP_FILTERS
-int lis2dh_acc_hp_filter_set(const struct device *dev, int32_t val)
-{
-	struct lis2dh_data *lis2dh = dev->data;
-	int status;
-
-	status = lis2dh->hw_tf->update_reg(dev, LIS2DH_REG_CTRL2,
-					   LIS2DH_HPIS_EN_MASK, val);
-	if (status < 0) {
-		LOG_ERR("Failed to set high pass filters");
-	}
-
-	return status;
-}
-#endif
-
 static void lis2dh_gpio_int1_callback(const struct device *dev,
 				      struct gpio_callback *cb, uint32_t pins)
 {
diff --git a/drivers/sensor/st/lis2dw12/lis2dw12.c b/drivers/sensor/st/lis2dw12/lis2dw12.c
index bea05819f36..93e223b6578 100644
--- a/drivers/sensor/st/lis2dw12/lis2dw12.c
+++ b/drivers/sensor/st/lis2dw12/lis2dw12.c
@@ -97,11 +97,11 @@ static inline void lis2dw12_channel_get_temp(const struct device *dev, struct se
 	struct lis2dw12_data *lis2dw12 = dev->data;
 	int64_t dval_uc;
 
-	/* The calcul is in micro Celcius to keep it efficient */
+	/* The calcul is in micro Celsius to keep it efficient */
 	dval_uc = ((lis2dw12->temp >> LIS2DW12_SHIFT_TEMP) * LIS2DW12_TEMP_SCALE_FACTOR);
 	dval_uc += 25000000;
 
-	/* switch to Celcius when we split the integer and fractional parts of the value */
+	/* switch to Celsius when we split the integer and fractional parts of the value */
 	val->val1 = dval_uc / 1000000LL;
 	val->val2 = dval_uc % 1000000LL;
 }
@@ -190,18 +190,6 @@ static int lis2dw12_config(const struct device *dev, enum sensor_channel chan,
 	return -ENOTSUP;
 }
 
-
-static inline int32_t sensor_ms2_to_mg(const struct sensor_value *ms2)
-{
-	int64_t nano_ms2 = (ms2->val1 * 1000000LL + ms2->val2) * 1000LL;
-
-	if (nano_ms2 > 0) {
-		return (nano_ms2 + SENSOR_G / 2) / SENSOR_G;
-	} else {
-		return (nano_ms2 - SENSOR_G / 2) / SENSOR_G;
-	}
-}
-
 #if (CONFIG_LIS2DW12_SLEEP || CONFIG_LIS2DW12_WAKEUP)
 
 /* Converts a lis2dw12_fs_t range to its value in milli-g
diff --git a/drivers/sensor/st/lis3mdl/lis3mdl.c b/drivers/sensor/st/lis3mdl/lis3mdl.c
index 52bcb13f786..14bd64dc0ad 100644
--- a/drivers/sensor/st/lis3mdl/lis3mdl.c
+++ b/drivers/sensor/st/lis3mdl/lis3mdl.c
@@ -11,6 +11,7 @@
 #include <zephyr/sys/__assert.h>
 #include <zephyr/sys/byteorder.h>
 #include <zephyr/drivers/sensor.h>
+#include <zephyr/pm/device.h>
 #include <string.h>
 #include <zephyr/logging/log.h>
 
@@ -66,7 +67,7 @@ int lis3mdl_sample_fetch(const struct device *dev, enum sensor_channel chan)
 	const struct lis3mdl_config *config = dev->config;
 	int16_t buf[4];
 
-	__ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL);
+	__ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL || chan == SENSOR_CHAN_MAGN_XYZ);
 
 	/* fetch magnetometer sample */
 	if (i2c_burst_read_dt(&config->i2c, LIS3MDL_REG_SAMPLE_START,
@@ -162,6 +163,41 @@ int lis3mdl_init(const struct device *dev)
 	return 0;
 }
 
+#ifdef CONFIG_PM_DEVICE
+static int lis3mdl_pm_action(const struct device *dev, enum pm_device_action action)
+{
+	const struct lis3mdl_config *config = dev->config;
+	uint8_t ctrl_reg3;
+
+	switch (action) {
+	case PM_DEVICE_ACTION_RESUME:
+		ctrl_reg3 = LIS3MDL_MD_CONTINUOUS;
+
+		if (i2c_reg_write_byte_dt(&config->i2c, LIS3MDL_REG_CTRL3, ctrl_reg3) < 0) {
+			LOG_DBG("Failed to configure chip.");
+			return -EIO;
+		}
+
+		LOG_DBG("State changed to active");
+		break;
+	case PM_DEVICE_ACTION_SUSPEND:
+		ctrl_reg3 = LIS3MDL_MD_POWER_DOWN;
+
+		if (i2c_reg_write_byte_dt(&config->i2c, LIS3MDL_REG_CTRL3, ctrl_reg3) < 0) {
+			LOG_DBG("Failed to configure chip.");
+			return -EIO;
+		}
+
+		LOG_DBG("State changed to inactive");
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+#endif
+
 #define LIS3MDL_DEFINE(inst)									\
 	static struct lis3mdl_data lis3mdl_data_##inst;						\
 												\
@@ -171,7 +207,10 @@ int lis3mdl_init(const struct device *dev)
 			   (.irq_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, irq_gpios, { 0 }),))	\
 	};											\
 												\
-	SENSOR_DEVICE_DT_INST_DEFINE(inst, lis3mdl_init, NULL,					\
+	PM_DEVICE_DT_INST_DEFINE(inst, lis3mdl_pm_action);					\
+												\
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, lis3mdl_init,					\
+				PM_DEVICE_DT_INST_GET(inst),					\
 			      &lis3mdl_data_##inst, &lis3mdl_config_##inst, POST_KERNEL,	\
 			      CONFIG_SENSOR_INIT_PRIORITY, &lis3mdl_driver_api);		\
 
diff --git a/drivers/sensor/st/lps22hb/lps22hb.c b/drivers/sensor/st/lps22hb/lps22hb.c
index 3c230300232..e32b9d7e28c 100644
--- a/drivers/sensor/st/lps22hb/lps22hb.c
+++ b/drivers/sensor/st/lps22hb/lps22hb.c
@@ -36,7 +36,7 @@ static int lps22hb_sample_fetch(const struct device *dev,
 	const struct lps22hb_config *config = dev->config;
 	uint8_t out[5];
 
-	__ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL);
+	__ASSERT_NO_MSG(chan == SENSOR_CHAN_PRESS || chan == SENSOR_CHAN_ALL);
 
 	if (i2c_burst_read_dt(&config->i2c, LPS22HB_REG_PRESS_OUT_XL,
 			      out, 5) < 0) {
diff --git a/drivers/sensor/st/lps25hb/lps25hb.c b/drivers/sensor/st/lps25hb/lps25hb.c
index 402e8d85838..87094fa0718 100644
--- a/drivers/sensor/st/lps25hb/lps25hb.c
+++ b/drivers/sensor/st/lps25hb/lps25hb.c
@@ -46,7 +46,7 @@ static int lps25hb_sample_fetch(const struct device *dev,
 	uint8_t out[5];
 	int offset;
 
-	__ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL);
+	__ASSERT_NO_MSG(chan == SENSOR_CHAN_PRESS || chan == SENSOR_CHAN_ALL);
 
 	for (offset = 0; offset < sizeof(out); ++offset) {
 		if (i2c_reg_read_byte_dt(&config->i2c,
diff --git a/drivers/sensor/st/lps2xdf/lps2xdf.c b/drivers/sensor/st/lps2xdf/lps2xdf.c
index 3a7392c8276..480f49255db 100644
--- a/drivers/sensor/st/lps2xdf/lps2xdf.c
+++ b/drivers/sensor/st/lps2xdf/lps2xdf.c
@@ -136,7 +136,7 @@ static int lps2xdf_sample_fetch(const struct device *dev, enum sensor_channel ch
 	const struct lps2xdf_config *const cfg = dev->config;
 	const struct lps2xdf_chip_api *chip_api = cfg->chip_api;
 
-	__ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL);
+	__ASSERT_NO_MSG(chan == SENSOR_CHAN_PRESS || chan == SENSOR_CHAN_ALL);
 
 	return chip_api->sample_fetch(dev, chan);
 }
diff --git a/drivers/sensor/st/lsm6dso/lsm6dso.c b/drivers/sensor/st/lsm6dso/lsm6dso.c
index 8d5902465f8..d3cdaf9dfd2 100644
--- a/drivers/sensor/st/lsm6dso/lsm6dso.c
+++ b/drivers/sensor/st/lsm6dso/lsm6dso.c
@@ -86,21 +86,6 @@ static int lsm6dso_gyro_range_to_fs_val(int32_t range)
 	return -EINVAL;
 }
 
-static inline int lsm6dso_reboot(const struct device *dev)
-{
-	const struct lsm6dso_config *cfg = dev->config;
-	stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
-
-	if (lsm6dso_boot_set(ctx, 1) < 0) {
-		return -EIO;
-	}
-
-	/* Wait sensor turn-on time as per datasheet */
-	k_busy_wait(35 * USEC_PER_MSEC);
-
-	return 0;
-}
-
 static int lsm6dso_accel_set_fs_raw(const struct device *dev, uint8_t fs)
 {
 	const struct lsm6dso_config *cfg = dev->config;
diff --git a/drivers/sensor/st/lsm6dso16is/lsm6dso16is.c b/drivers/sensor/st/lsm6dso16is/lsm6dso16is.c
index 1c4113c7c35..1171d7fa380 100644
--- a/drivers/sensor/st/lsm6dso16is/lsm6dso16is.c
+++ b/drivers/sensor/st/lsm6dso16is/lsm6dso16is.c
@@ -80,21 +80,6 @@ static int lsm6dso16is_gyro_range_to_fs_val(int32_t range)
 	return -EINVAL;
 }
 
-static inline int lsm6dso16is_reboot(const struct device *dev)
-{
-	const struct lsm6dso16is_config *cfg = dev->config;
-	stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
-
-	if (lsm6dso16is_boot_set(ctx, 1) < 0) {
-		return -EIO;
-	}
-
-	/* Wait sensor turn-on time as per datasheet */
-	k_sleep(K_MSEC(35)); /* turn-on time in ms */
-
-	return 0;
-}
-
 static int lsm6dso16is_accel_set_fs_raw(const struct device *dev, uint8_t fs)
 {
 	const struct lsm6dso16is_config *cfg = dev->config;
diff --git a/drivers/sensor/st/lsm6dsv16x/Kconfig b/drivers/sensor/st/lsm6dsv16x/Kconfig
index 9d41fdda255..06f713cf4a1 100644
--- a/drivers/sensor/st/lsm6dsv16x/Kconfig
+++ b/drivers/sensor/st/lsm6dsv16x/Kconfig
@@ -4,13 +4,16 @@
 # SPDX-License-Identifier: Apache-2.0
 
 menuconfig LSM6DSV16X
-	bool "LSM6DSV16X I3C/I2C/SPI accelerometer and gyroscope Chip"
+	bool "LSM6DSV16X/LSM6DSV32X I3C/I2C/SPI accelerometer and gyroscope chip"
 	default y
-	depends on DT_HAS_ST_LSM6DSV16X_ENABLED
+	depends on DT_HAS_ST_LSM6DSV16X_ENABLED || DT_HAS_ST_LSM6DSV32X_ENABLED
 	depends on ZEPHYR_HAL_ST_MODULE
-	select I2C if $(dt_compat_on_bus,$(DT_COMPAT_ST_LSM6DSV16X),i2c)
-	select I3C if $(dt_compat_on_bus,$(DT_COMPAT_ST_LSM6DSV16X),i3c)
-	select SPI if $(dt_compat_on_bus,$(DT_COMPAT_ST_LSM6DSV16X),spi)
+	select I2C if $(dt_compat_on_bus,$(DT_COMPAT_ST_LSM6DSV16X),i2c) ||\
+		      $(dt_compat_on_bus,$(DT_COMPAT_ST_LSM6DSV32X),i2c)
+	select I3C if $(dt_compat_on_bus,$(DT_COMPAT_ST_LSM6DSV16X),i3c) ||\
+		      $(dt_compat_on_bus,$(DT_COMPAT_ST_LSM6DSV32X),i3c)
+	select SPI if $(dt_compat_on_bus,$(DT_COMPAT_ST_LSM6DSV16X),spi) ||\
+		      $(dt_compat_on_bus,$(DT_COMPAT_ST_LSM6DSV32X),spi)
 	select HAS_STMEMSC
 	select USE_STDC_LSM6DSV16X
 	select RTIO_WORKQ if SENSOR_ASYNC_API
@@ -44,7 +47,10 @@ config LSM6DSV16X_TRIGGER_GLOBAL_THREAD
 	depends on GPIO || I3C
 	depends on $(dt_compat_any_has_prop,$(DT_COMPAT_ST_LSM6DSV16X),int1-gpios) ||\
 		   $(dt_compat_any_has_prop,$(DT_COMPAT_ST_LSM6DSV16X),int2-gpios) ||\
-		   $(dt_compat_on_bus,$(DT_COMPAT_ST_LSM6DSV16X),i3c)
+		   $(dt_compat_on_bus,$(DT_COMPAT_ST_LSM6DSV16X),i3c) ||\
+		   $(dt_compat_any_has_prop,$(DT_COMPAT_ST_LSM6DSV32X),int1-gpios) ||\
+		   $(dt_compat_any_has_prop,$(DT_COMPAT_ST_LSM6DSV32X),int2-gpios) ||\
+		   $(dt_compat_on_bus,$(DT_COMPAT_ST_LSM6DSV32X),i3c)
 	select LSM6DSV16X_TRIGGER
 
 config LSM6DSV16X_TRIGGER_OWN_THREAD
@@ -52,7 +58,10 @@ config LSM6DSV16X_TRIGGER_OWN_THREAD
 	depends on GPIO || I3C
 	depends on $(dt_compat_any_has_prop,$(DT_COMPAT_ST_LSM6DSV16X),int1-gpios) ||\
 		   $(dt_compat_any_has_prop,$(DT_COMPAT_ST_LSM6DSV16X),int2-gpios) ||\
-		   $(dt_compat_on_bus,$(DT_COMPAT_ST_LSM6DSV16X),i3c)
+		   $(dt_compat_on_bus,$(DT_COMPAT_ST_LSM6DSV16X),i3c) ||\
+		   $(dt_compat_any_has_prop,$(DT_COMPAT_ST_LSM6DSV32X),int1-gpios) ||\
+		   $(dt_compat_any_has_prop,$(DT_COMPAT_ST_LSM6DSV32X),int2-gpios) ||\
+		   $(dt_compat_on_bus,$(DT_COMPAT_ST_LSM6DSV32X),i3c)
 	select LSM6DSV16X_TRIGGER
 
 endchoice
diff --git a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.c b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.c
index 2e156301c5e..54affd497df 100644
--- a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.c
+++ b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.c
@@ -4,26 +4,38 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  *
- * Datasheet:
+ * Datasheets:
  * https://www.st.com/resource/en/datasheet/lsm6dsv16x.pdf
+ * https://www.st.com/resource/en/datasheet/lsm6dsv32x.pdf
  */
 
-#define DT_DRV_COMPAT st_lsm6dsv16x
-
 #include <zephyr/drivers/sensor.h>
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
+#include <zephyr/pm/device.h>
 #include <string.h>
 #include <zephyr/sys/__assert.h>
 #include <zephyr/logging/log.h>
 
+#include <zephyr/dt-bindings/sensor/lsm6dsv16x.h>
 #include "lsm6dsv16x.h"
 #include "lsm6dsv16x_decoder.h"
 #include "lsm6dsv16x_rtio.h"
 
 LOG_MODULE_REGISTER(LSM6DSV16X, CONFIG_SENSOR_LOG_LEVEL);
 
+bool lsm6dsv16x_is_active(const struct device *dev)
+{
+#if defined(CONFIG_PM_DEVICE)
+	enum pm_device_state state;
+	(void)pm_device_state_get(dev, &state);
+	return (state == PM_DEVICE_STATE_ACTIVE);
+#else
+	return true;
+#endif /* CONFIG_PM_DEVICE*/
+}
+
 /*
  * values taken from lsm6dsv16x_data_rate_t in hal/st module. The mode/accuracy
  * should be selected through accel-odr property in DT
@@ -69,14 +81,21 @@ static int lsm6dsv16x_freq_to_odr_val(const struct device *dev, uint16_t freq)
 	return -EINVAL;
 }
 
+#define ACCEL_FS_MAP_SIZE 4
+#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT_LSM6DSV16X)
 static const uint16_t lsm6dsv16x_accel_fs_map[] = {2, 4, 8, 16};
+#endif
+#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT_LSM6DSV32X)
+static const uint16_t lsm6dsv32x_accel_fs_map[] = {4, 8, 16, 32};
+#endif
 
-static int lsm6dsv16x_accel_range_to_fs_val(int32_t range)
+static int lsm6dsv16x_accel_range_to_fs_val(const struct device *dev, int32_t range)
 {
+	const struct lsm6dsv16x_config *cfg = dev->config;
 	size_t i;
 
-	for (i = 0; i < ARRAY_SIZE(lsm6dsv16x_accel_fs_map); i++) {
-		if (range == lsm6dsv16x_accel_fs_map[i]) {
+	for (i = 0; i < ACCEL_FS_MAP_SIZE; i++) {
+		if (range == cfg->accel_fs_map[i]) {
 			return i;
 		}
 	}
@@ -88,12 +107,14 @@ static const uint16_t lsm6dsv16x_gyro_fs_map[] = {125, 250, 500, 1000, 2000, 0,
 						  0,   0,   0,   0,    0,    4000};
 static const uint16_t lsm6dsv16x_gyro_fs_sens[] = {1, 2, 4, 8, 16, 0, 0, 0, 0, 0, 0, 0, 32};
 
-int lsm6dsv16x_calc_accel_gain(uint8_t fs)
+static int lsm6dsv16x_calc_accel_gain(const struct device *dev, uint8_t fs)
 {
-	return lsm6dsv16x_accel_fs_map[fs] * GAIN_UNIT_XL / 2;
+	const struct lsm6dsv16x_config *cfg = dev->config;
+
+	return cfg->accel_fs_map[fs] * GAIN_UNIT_XL / 2;
 }
 
-int lsm6dsv16x_calc_gyro_gain(uint8_t fs)
+static int lsm6dsv16x_calc_gyro_gain(uint8_t fs)
 {
 	return lsm6dsv16x_gyro_fs_sens[fs] * GAIN_UNIT_G;
 }
@@ -144,7 +165,7 @@ static int lsm6dsv16x_accel_set_fs_raw(const struct device *dev, uint8_t fs)
 	return 0;
 }
 
-static int lsm6dsv16x_accel_set_odr_raw(const struct device *dev, uint8_t odr)
+int lsm6dsv16x_accel_set_odr_raw(const struct device *dev, uint8_t odr)
 {
 	const struct lsm6dsv16x_config *cfg = dev->config;
 	stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
@@ -173,15 +194,17 @@ static int lsm6dsv16x_gyro_set_fs_raw(const struct device *dev, uint8_t fs)
 	return 0;
 }
 
-static int lsm6dsv16x_gyro_set_odr_raw(const struct device *dev, uint8_t odr)
+int lsm6dsv16x_gyro_set_odr_raw(const struct device *dev, uint8_t odr)
 {
 	const struct lsm6dsv16x_config *cfg = dev->config;
 	stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
+	struct lsm6dsv16x_data *data = dev->data;
 
 	if (lsm6dsv16x_gy_data_rate_set(ctx, odr) < 0) {
 		return -EIO;
 	}
 
+	data->gyro_freq = odr;
 	return 0;
 }
 
@@ -207,7 +230,7 @@ static int lsm6dsv16x_accel_range_set(const struct device *dev, int32_t range)
 	int fs;
 	struct lsm6dsv16x_data *data = dev->data;
 
-	fs = lsm6dsv16x_accel_range_to_fs_val(range);
+	fs = lsm6dsv16x_accel_range_to_fs_val(dev, range);
 	if (fs < 0) {
 		return fs;
 	}
@@ -217,10 +240,59 @@ static int lsm6dsv16x_accel_range_set(const struct device *dev, int32_t range)
 		return -EIO;
 	}
 
-	data->acc_gain = lsm6dsv16x_calc_accel_gain(fs);
+	data->acc_gain = lsm6dsv16x_calc_accel_gain(dev, fs);
 	return 0;
 }
 
+#define LSM6DSV16X_WU_INACT_THS_W_MAX 5
+#define LSM6DSV16X_WAKE_UP_THS_MAX    0x3FU
+static const float wu_inact_ths_w_lsb[] = {7.8125f, 15.625f, 31.25f, 62.5f, 125.0f, 250.0f};
+
+static int lsm6dsv16x_accel_wake_threshold_set(const struct device *dev,
+					       const struct sensor_value *val)
+{
+	const struct lsm6dsv16x_config *cfg = dev->config;
+	stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
+	lsm6dsv16x_act_thresholds_t thresholds;
+
+	if (lsm6dsv16x_act_thresholds_get(ctx, &thresholds) < 0) {
+		LOG_DBG("failed to get thresholds");
+		return -EIO;
+	}
+
+	float val_mg = sensor_ms2_to_ug(val) / 1000.0f;
+
+	thresholds.inactivity_cfg.wu_inact_ths_w = LSM6DSV16X_WU_INACT_THS_W_MAX;
+	thresholds.threshold = LSM6DSV16X_WAKE_UP_THS_MAX;
+
+	for (uint8_t i = 0; i <= LSM6DSV16X_WU_INACT_THS_W_MAX; i++) {
+		if (val_mg < (wu_inact_ths_w_lsb[i] * (float)LSM6DSV16X_WAKE_UP_THS_MAX)) {
+			thresholds.inactivity_cfg.wu_inact_ths_w = i;
+			thresholds.threshold = (uint8_t)(val_mg / wu_inact_ths_w_lsb[i]);
+			break;
+		}
+	}
+
+	return lsm6dsv16x_act_thresholds_set(ctx, &thresholds);
+}
+
+static int lsm6dsv16x_accel_wake_duration_set(const struct device *dev,
+					      const struct sensor_value *val)
+{
+	const struct lsm6dsv16x_config *cfg = dev->config;
+	stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
+	lsm6dsv16x_act_thresholds_t thresholds;
+
+	if (lsm6dsv16x_act_thresholds_get(ctx, &thresholds) < 0) {
+		LOG_DBG("failed to get thresholds");
+		return -EIO;
+	}
+
+	thresholds.duration = MIN(val->val1, 3);
+
+	return lsm6dsv16x_act_thresholds_set(ctx, &thresholds);
+}
+
 static int lsm6dsv16x_accel_config(const struct device *dev,
 				enum sensor_channel chan,
 				enum sensor_attribute attr,
@@ -235,6 +307,10 @@ static int lsm6dsv16x_accel_config(const struct device *dev,
 		return lsm6dsv16x_accel_range_set(dev, sensor_ms2_to_g(val));
 	case SENSOR_ATTR_SAMPLING_FREQUENCY:
 		return lsm6dsv16x_accel_odr_set(dev, val->val1);
+	case SENSOR_ATTR_SLOPE_TH:
+		return lsm6dsv16x_accel_wake_threshold_set(dev, val);
+	case SENSOR_ATTR_SLOPE_DUR:
+		return lsm6dsv16x_accel_wake_duration_set(dev, val);
 	case SENSOR_ATTR_CONFIGURATION:
 		switch (val->val1) {
 		case 0: /* High Performance */
@@ -361,6 +437,10 @@ static int lsm6dsv16x_attr_set(const struct device *dev,
 	struct lsm6dsv16x_data *data = dev->data;
 #endif /* CONFIG_LSM6DSV16X_SENSORHUB */
 
+	if (!lsm6dsv16x_is_active(dev)) {
+		return -EBUSY;
+	}
+
 	switch (chan) {
 	case SENSOR_CHAN_ACCEL_XYZ:
 		return lsm6dsv16x_accel_config(dev, chan, attr, val);
@@ -377,6 +457,10 @@ static int lsm6dsv16x_attr_set(const struct device *dev,
 
 		return lsm6dsv16x_shub_config(dev, chan, attr, val);
 #endif /* CONFIG_LSM6DSV16X_SENSORHUB */
+#ifdef CONFIG_LSM6DSV16X_STREAM
+	case SENSOR_CHAN_GBIAS_XYZ:
+		return lsm6dsv16x_gbias_config(dev, chan, attr, val);
+#endif /* CONFIG_LSM6DSV16X_STREAM */
 	default:
 		LOG_WRN("attr_set() not supported on this channel.");
 		return -ENOTSUP;
@@ -385,6 +469,43 @@ static int lsm6dsv16x_attr_set(const struct device *dev,
 	return 0;
 }
 
+static int lsm6dsv16x_accel_wake_threshold_get(const struct device *dev, struct sensor_value *val)
+{
+	const struct lsm6dsv16x_config *cfg = dev->config;
+	stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
+	lsm6dsv16x_act_thresholds_t thresholds;
+	float val_mg;
+
+	if (lsm6dsv16x_act_thresholds_get(ctx, &thresholds) < 0) {
+		LOG_DBG("failed to get thresholds");
+		return -EIO;
+	}
+
+	val_mg = wu_inact_ths_w_lsb[thresholds.inactivity_cfg.wu_inact_ths_w];
+	val_mg *= (float)thresholds.threshold;
+
+	sensor_ug_to_ms2(1000.0f * val_mg, val);
+
+	return 0;
+}
+
+static int lsm6dsv16x_accel_wake_duration_get(const struct device *dev, struct sensor_value *val)
+{
+	const struct lsm6dsv16x_config *cfg = dev->config;
+	stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
+	lsm6dsv16x_act_thresholds_t thresholds;
+
+	if (lsm6dsv16x_act_thresholds_get(ctx, &thresholds) < 0) {
+		LOG_DBG("failed to get thresholds");
+		return -EIO;
+	}
+
+	val->val1 = thresholds.duration;
+	val->val2 = 0;
+
+	return 0;
+}
+
 static int lsm6dsv16x_accel_get_config(const struct device *dev,
 				       enum sensor_channel chan,
 				       enum sensor_attribute attr,
@@ -396,7 +517,7 @@ static int lsm6dsv16x_accel_get_config(const struct device *dev,
 
 	switch (attr) {
 	case SENSOR_ATTR_FULL_SCALE:
-		sensor_g_to_ms2(lsm6dsv16x_accel_fs_map[data->accel_fs], val);
+		sensor_g_to_ms2(cfg->accel_fs_map[data->accel_fs], val);
 		break;
 	case SENSOR_ATTR_SAMPLING_FREQUENCY: {
 		lsm6dsv16x_data_rate_t odr;
@@ -412,6 +533,10 @@ static int lsm6dsv16x_accel_get_config(const struct device *dev,
 		val->val2 = 0;
 		break;
 	}
+	case SENSOR_ATTR_SLOPE_TH:
+		return lsm6dsv16x_accel_wake_threshold_get(dev, val);
+	case SENSOR_ATTR_SLOPE_DUR:
+		return lsm6dsv16x_accel_wake_duration_get(dev, val);
 	case SENSOR_ATTR_CONFIGURATION: {
 		lsm6dsv16x_xl_mode_t mode;
 
@@ -512,16 +637,22 @@ static int lsm6dsv16x_gyro_get_config(const struct device *dev,
 	return 0;
 }
 
-static int lsm6dsv16x_attr_get(const struct device *dev,
-			       enum sensor_channel chan,
-			       enum sensor_attribute attr,
-			       struct sensor_value *val)
+static int lsm6dsv16x_attr_get(const struct device *dev, enum sensor_channel chan,
+			       enum sensor_attribute attr, struct sensor_value *val)
 {
+	if (!lsm6dsv16x_is_active(dev)) {
+		return -EBUSY;
+	}
+
 	switch (chan) {
 	case SENSOR_CHAN_ACCEL_XYZ:
 		return lsm6dsv16x_accel_get_config(dev, chan, attr, val);
 	case SENSOR_CHAN_GYRO_XYZ:
 		return lsm6dsv16x_gyro_get_config(dev, chan, attr, val);
+#ifdef CONFIG_LSM6DSV16X_STREAM
+	case SENSOR_CHAN_GBIAS_XYZ:
+		return lsm6dsv16x_gbias_get_config(dev, chan, attr, val);
+#endif /* CONFIG_LSM6DSV16X_STREAM */
 	default:
 		LOG_WRN("attr_get() not supported on this channel.");
 		return -ENOTSUP;
@@ -593,6 +724,10 @@ static int lsm6dsv16x_sample_fetch(const struct device *dev,
 	struct lsm6dsv16x_data *data = dev->data;
 #endif /* CONFIG_LSM6DSV16X_SENSORHUB */
 
+	if (!lsm6dsv16x_is_active(dev)) {
+		return -EBUSY;
+	}
+
 	switch (chan) {
 	case SENSOR_CHAN_ACCEL_XYZ:
 		lsm6dsv16x_sample_fetch_accel(dev);
@@ -864,6 +999,10 @@ static int lsm6dsv16x_channel_get(const struct device *dev,
 {
 	struct lsm6dsv16x_data *data = dev->data;
 
+	if (!lsm6dsv16x_is_active(dev)) {
+		return -EBUSY;
+	}
+
 	switch (chan) {
 	case SENSOR_CHAN_ACCEL_X:
 	case SENSOR_CHAN_ACCEL_Y:
@@ -951,7 +1090,7 @@ static int lsm6dsv16x_init_chip(const struct device *dev)
 	uint8_t chip_id;
 	uint8_t odr, fs;
 
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
+#if LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
 	if (cfg->i3c.bus != NULL) {
 		/*
 		 * Need to grab the pointer to the I3C device descriptor
@@ -1014,7 +1153,7 @@ static int lsm6dsv16x_init_chip(const struct device *dev)
 		LOG_ERR("failed to set accelerometer range %d", fs);
 		return -EIO;
 	}
-	lsm6dsv16x->acc_gain = lsm6dsv16x_calc_accel_gain(fs);
+	lsm6dsv16x->acc_gain = lsm6dsv16x_calc_accel_gain(dev, fs);
 
 	odr = cfg->accel_odr;
 	LOG_DBG("accel odr is %d", odr);
@@ -1033,13 +1172,12 @@ static int lsm6dsv16x_init_chip(const struct device *dev)
 
 	odr = cfg->gyro_odr;
 	LOG_DBG("gyro odr is %d", odr);
-	lsm6dsv16x->gyro_freq = odr;
 	if (lsm6dsv16x_gyro_set_odr_raw(dev, odr) < 0) {
 		LOG_ERR("failed to set gyroscope odr %d", odr);
 		return -EIO;
 	}
 
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
+#if LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
 	if (IS_ENABLED(CONFIG_LSM6DSV16X_STREAM) && (ON_I3C_BUS(cfg))) {
 		/*
 		 * Set MRL to the Max Size of the FIFO so the entire FIFO can be read
@@ -1099,7 +1237,48 @@ static int lsm6dsv16x_init(const struct device *dev)
 	return 0;
 }
 
-#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 0
+#if defined(CONFIG_PM_DEVICE)
+static int lsm6dsv16x_pm_action(const struct device *dev, enum pm_device_action action)
+{
+	struct lsm6dsv16x_data *data = dev->data;
+	const struct lsm6dsv16x_config *cfg = dev->config;
+	stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
+	int ret = 0;
+
+	LOG_DBG("PM action: %d", (int)action);
+
+	switch (action) {
+	case PM_DEVICE_ACTION_RESUME:
+		if (lsm6dsv16x_xl_data_rate_set(ctx, data->accel_freq) < 0) {
+			LOG_ERR("failed to set accelerometer odr %d", (int)data->accel_freq);
+			ret = -EIO;
+		}
+		if (lsm6dsv16x_gy_data_rate_set(ctx, data->gyro_freq) < 0) {
+			LOG_ERR("failed to set gyroscope odr %d", (int)data->gyro_freq);
+			ret = -EIO;
+		}
+		break;
+	case PM_DEVICE_ACTION_SUSPEND:
+		if (lsm6dsv16x_xl_data_rate_set(ctx, LSM6DSV16X_DT_ODR_OFF) < 0) {
+			LOG_ERR("failed to disable accelerometer");
+			ret = -EIO;
+		}
+		if (lsm6dsv16x_gy_data_rate_set(ctx, LSM6DSV16X_DT_ODR_OFF) < 0) {
+			LOG_ERR("failed to disable gyroscope");
+			ret = -EIO;
+		}
+		break;
+	default:
+		ret = -ENOTSUP;
+		break;
+	}
+
+	return ret;
+}
+#endif /* CONFIG_PM_DEVICE */
+
+#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT_LSM6DSV16X) == 0 &&                                      \
+	DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT_LSM6DSV32X) == 0
 #warning "LSM6DSV16X driver enabled without any devices"
 #endif
 
@@ -1108,15 +1287,14 @@ static int lsm6dsv16x_init(const struct device *dev)
  * LSM6DSV16X_DEFINE_I2C().
  */
 
-#define LSM6DSV16X_DEVICE_INIT(inst)					\
-	SENSOR_DEVICE_DT_INST_DEFINE(inst,				\
-			    lsm6dsv16x_init,				\
-			    NULL,					\
-			    &lsm6dsv16x_data_##inst,			\
-			    &lsm6dsv16x_config_##inst,			\
-			    POST_KERNEL,				\
-			    CONFIG_SENSOR_INIT_PRIORITY,		\
-			    &lsm6dsv16x_driver_api);
+/* clang-format off */
+
+#define LSM6DSV16X_DEVICE_INIT(inst, prefix)							\
+	PM_DEVICE_DT_INST_DEFINE(inst, lsm6dsv16x_pm_action);					\
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, lsm6dsv16x_init, PM_DEVICE_DT_INST_GET(inst),	\
+				     &prefix##_data_##inst, &prefix##_config_##inst,		\
+				     POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY,			\
+				     &lsm6dsv16x_driver_api);
 
 #ifdef CONFIG_LSM6DSV16X_TRIGGER
 #define LSM6DSV16X_CFG_IRQ(inst)					\
@@ -1129,9 +1307,10 @@ static int lsm6dsv16x_init(const struct device *dev)
 #define LSM6DSV16X_CFG_IRQ(inst)
 #endif /* CONFIG_LSM6DSV16X_TRIGGER */
 
-#define LSM6DSV16X_CONFIG_COMMON(inst)						\
+#define LSM6DSV16X_CONFIG_COMMON(inst, prefix)					\
 	.accel_odr = DT_INST_PROP(inst, accel_odr),				\
-	.accel_range = DT_INST_PROP(inst, accel_range),				\
+	.accel_range = DT_INST_ENUM_IDX(inst, accel_range),			\
+	.accel_fs_map = prefix##_accel_fs_map,					\
 	.gyro_odr = DT_INST_PROP(inst, gyro_odr),				\
 	.gyro_range = DT_INST_PROP(inst, gyro_range),				\
 	IF_ENABLED(CONFIG_LSM6DSV16X_STREAM,					\
@@ -1154,111 +1333,126 @@ static int lsm6dsv16x_init(const struct device *dev)
 			 SPI_MODE_CPOL |				\
 			 SPI_MODE_CPHA)					\
 
-#define LSM6DSV16X_SPI_RTIO_DEFINE(inst)				\
-	SPI_DT_IODEV_DEFINE(lsm6dsv16x_iodev_##inst,			\
+#define LSM6DSV16X_SPI_RTIO_DEFINE(inst, prefix)			\
+	SPI_DT_IODEV_DEFINE(prefix##_iodev_##inst,			\
 		DT_DRV_INST(inst), LSM6DSV16X_SPI_OP, 0U);		\
-	RTIO_DEFINE(lsm6dsv16x_rtio_ctx_##inst, 4, 4);
+	RTIO_DEFINE(prefix##_rtio_ctx_##inst, 4, 4);
 
-#define LSM6DSV16X_CONFIG_SPI(inst)					\
+#define LSM6DSV16X_CONFIG_SPI(inst, prefix)				\
 	{								\
-		STMEMSC_CTX_SPI(&lsm6dsv16x_config_##inst.stmemsc_cfg),	\
+		STMEMSC_CTX_SPI(&prefix##_config_##inst.stmemsc_cfg),	\
 		.stmemsc_cfg = {					\
 			.spi = SPI_DT_SPEC_INST_GET(inst,		\
 					   LSM6DSV16X_SPI_OP,		\
 					   0),				\
 		},							\
-		LSM6DSV16X_CONFIG_COMMON(inst)				\
+		LSM6DSV16X_CONFIG_COMMON(inst, prefix)			\
 	}
 
-#define LSM6DSV16X_DEFINE_SPI(inst)					\
-	IF_ENABLED(CONFIG_LSM6DSV16X_STREAM, (LSM6DSV16X_SPI_RTIO_DEFINE(inst))); \
-	static struct lsm6dsv16x_data lsm6dsv16x_data_##inst =	{	\
-		IF_ENABLED(CONFIG_LSM6DSV16X_STREAM,			\
-			(.rtio_ctx = &lsm6dsv16x_rtio_ctx_##inst,	\
-			 .iodev = &lsm6dsv16x_iodev_##inst,		\
+#define LSM6DSV16X_DEFINE_SPI(inst, prefix)				\
+	IF_ENABLED(UTIL_AND(CONFIG_LSM6DSV16X_STREAM,			\
+			    CONFIG_SPI_RTIO),				\
+		   (LSM6DSV16X_SPI_RTIO_DEFINE(inst, prefix)));		\
+	static struct lsm6dsv16x_data prefix##_data_##inst =	{	\
+		IF_ENABLED(UTIL_AND(CONFIG_LSM6DSV16X_STREAM,		\
+				    CONFIG_SPI_RTIO),			\
+			(.rtio_ctx = &prefix##_rtio_ctx_##inst,	\
+			 .iodev = &prefix##_iodev_##inst,		\
 			 .bus_type = BUS_SPI,))				\
 	};								\
-	static const struct lsm6dsv16x_config lsm6dsv16x_config_##inst = \
-		LSM6DSV16X_CONFIG_SPI(inst);				\
+	static const struct lsm6dsv16x_config prefix##_config_##inst =	\
+		LSM6DSV16X_CONFIG_SPI(inst, prefix);
 
 /*
  * Instantiation macros used when a device is on an I2C bus.
  */
 
-#define LSM6DSV16X_I2C_RTIO_DEFINE(inst)				\
-	I2C_DT_IODEV_DEFINE(lsm6dsv16x_iodev_##inst, DT_DRV_INST(inst));\
-	RTIO_DEFINE(lsm6dsv16x_rtio_ctx_##inst, 4, 4);
+#define LSM6DSV16X_I2C_RTIO_DEFINE(inst, prefix)			\
+	I2C_DT_IODEV_DEFINE(prefix##_iodev_##inst, DT_DRV_INST(inst));	\
+	RTIO_DEFINE(prefix##_rtio_ctx_##inst, 4, 4);
 
-#define LSM6DSV16X_CONFIG_I2C(inst)					\
+#define LSM6DSV16X_CONFIG_I2C(inst, prefix)				\
 	{								\
-		STMEMSC_CTX_I2C(&lsm6dsv16x_config_##inst.stmemsc_cfg),	\
+		STMEMSC_CTX_I2C(&prefix##_config_##inst.stmemsc_cfg),	\
 		.stmemsc_cfg = {					\
 			.i2c = I2C_DT_SPEC_INST_GET(inst),		\
 		},							\
-		LSM6DSV16X_CONFIG_COMMON(inst)				\
+		LSM6DSV16X_CONFIG_COMMON(inst, prefix)			\
 	}
 
-
-#define LSM6DSV16X_DEFINE_I2C(inst)					\
-	IF_ENABLED(CONFIG_LSM6DSV16X_STREAM, (LSM6DSV16X_I2C_RTIO_DEFINE(inst))); \
-	static struct lsm6dsv16x_data lsm6dsv16x_data_##inst =	{	\
-		IF_ENABLED(CONFIG_LSM6DSV16X_STREAM,			\
-			(.rtio_ctx = &lsm6dsv16x_rtio_ctx_##inst,	\
-			 .iodev = &lsm6dsv16x_iodev_##inst,		\
+#define LSM6DSV16X_DEFINE_I2C(inst, prefix)				\
+	IF_ENABLED(UTIL_AND(CONFIG_LSM6DSV16X_STREAM,			\
+			    CONFIG_I2C_RTIO),				\
+		   (LSM6DSV16X_I2C_RTIO_DEFINE(inst, prefix)));		\
+	static struct lsm6dsv16x_data prefix##_data_##inst =	{	\
+		IF_ENABLED(UTIL_AND(CONFIG_LSM6DSV16X_STREAM,		\
+				    CONFIG_I2C_RTIO),			\
+			(.rtio_ctx = &prefix##_rtio_ctx_##inst,	\
+			 .iodev = &prefix##_iodev_##inst,		\
 			 .bus_type = BUS_I2C,))				\
 	};								\
-	static const struct lsm6dsv16x_config lsm6dsv16x_config_##inst = \
-		LSM6DSV16X_CONFIG_I2C(inst);				\
+	static const struct lsm6dsv16x_config prefix##_config_##inst =	\
+		LSM6DSV16X_CONFIG_I2C(inst, prefix);
 
 /*
  * Instantiation macros used when a device is on an I3C bus.
  */
 
-#define LSM6DSV16X_I3C_RTIO_DEFINE(inst)                                       \
-	I3C_DT_IODEV_DEFINE(lsm6dsv16x_i3c_iodev_##inst, DT_DRV_INST(inst));   \
-	RTIO_DEFINE(lsm6dsv16x_rtio_ctx_##inst, 4, 4);
-
-#define LSM6DSV16X_CONFIG_I3C(inst)					            \
-	{								            \
-		STMEMSC_CTX_I3C(&lsm6dsv16x_config_##inst.stmemsc_cfg),	            \
-		.stmemsc_cfg = {					            \
-			.i3c = &lsm6dsv16x_data_##inst.i3c_dev,		            \
-		},							            \
-		.i3c.bus = DEVICE_DT_GET(DT_INST_BUS(inst)),		            \
-		.i3c.dev_id = I3C_DEVICE_ID_DT_INST(inst),		            \
-		IF_ENABLED(CONFIG_LSM6DSV16X_TRIGGER,                               \
-			  (.int_en_i3c = DT_INST_PROP(inst, int_en_i3c),            \
-			   .bus_act_sel = DT_INST_ENUM_IDX(inst, bus_act_sel_us),)) \
-		LSM6DSV16X_CONFIG_COMMON(inst)				            \
-	}
-
-#define LSM6DSV16X_DEFINE_I3C(inst)					\
-	IF_ENABLED(CONFIG_LSM6DSV16X_STREAM, (LSM6DSV16X_I3C_RTIO_DEFINE(inst))); \
-	static struct lsm6dsv16x_data lsm6dsv16x_data_##inst = {	\
-		IF_ENABLED(CONFIG_LSM6DSV16X_STREAM,			\
-			(.rtio_ctx = &lsm6dsv16x_rtio_ctx_##inst,	\
-			 .iodev = &lsm6dsv16x_i3c_iodev_##inst,		\
+#define LSM6DSV16X_I3C_RTIO_DEFINE(inst, prefix)				\
+	I3C_DT_IODEV_DEFINE(prefix##_i3c_iodev_##inst, DT_DRV_INST(inst));	\
+	RTIO_DEFINE(prefix##_rtio_ctx_##inst, 4, 4);
+
+#define LSM6DSV16X_CONFIG_I3C(inst, prefix)						\
+	{										\
+		STMEMSC_CTX_I3C(&prefix##_config_##inst.stmemsc_cfg),			\
+		.stmemsc_cfg = {							\
+			.i3c = &prefix##_data_##inst.i3c_dev,				\
+		},									\
+		.i3c.bus = DEVICE_DT_GET(DT_INST_BUS(inst)),				\
+		.i3c.dev_id = I3C_DEVICE_ID_DT_INST(inst),				\
+		IF_ENABLED(CONFIG_LSM6DSV16X_TRIGGER,					\
+			  (.int_en_i3c = DT_INST_PROP(inst, int_en_i3c),		\
+			   .bus_act_sel = DT_INST_ENUM_IDX(inst, bus_act_sel_us),))	\
+		LSM6DSV16X_CONFIG_COMMON(inst, prefix)					\
+	}
+
+#define LSM6DSV16X_DEFINE_I3C(inst, prefix)				\
+	IF_ENABLED(UTIL_AND(CONFIG_LSM6DSV16X_STREAM,			\
+			    CONFIG_I3C_RTIO),				\
+		   (LSM6DSV16X_I3C_RTIO_DEFINE(inst, prefix)));		\
+	static struct lsm6dsv16x_data prefix##_data_##inst = {		\
+		IF_ENABLED(UNTIL_AND(CONFIG_LSM6DSV16X_STREAM,		\
+				     CONFIG_I3C_RTIO),			\
+			(.rtio_ctx = &prefix##_rtio_ctx_##inst,		\
+			 .iodev = &prefix##_i3c_iodev_##inst,		\
 			 .bus_type = BUS_I3C,))				\
 	};								\
-	static const struct lsm6dsv16x_config lsm6dsv16x_config_##inst = \
-		LSM6DSV16X_CONFIG_I3C(inst);				\
+	static const struct lsm6dsv16x_config prefix##_config_##inst =	\
+		LSM6DSV16X_CONFIG_I3C(inst, prefix);
 
-#define LSM6DSV16X_DEFINE_I3C_OR_I2C(inst)				\
+#define LSM6DSV16X_DEFINE_I3C_OR_I2C(inst, prefix)			\
 	COND_CODE_0(DT_INST_PROP_BY_IDX(inst, reg, 1),			\
-		    (LSM6DSV16X_DEFINE_I2C(inst)),			\
-		    (LSM6DSV16X_DEFINE_I3C(inst)))
+		    (LSM6DSV16X_DEFINE_I2C(inst, prefix)),		\
+		    (LSM6DSV16X_DEFINE_I3C(inst, prefix)))
 
 /*
  * Main instantiation macro. Use of COND_CODE_1() selects the right
  * bus-specific macro at preprocessor time.
  */
 
-#define LSM6DSV16X_DEFINE(inst)							\
+#define LSM6DSV16X_DEFINE(inst, prefix)						\
 	COND_CODE_1(DT_INST_ON_BUS(inst, spi),					\
-		(LSM6DSV16X_DEFINE_SPI(inst)),					\
+		(LSM6DSV16X_DEFINE_SPI(inst, prefix)),				\
 		(COND_CODE_1(DT_INST_ON_BUS(inst, i3c),				\
-			(LSM6DSV16X_DEFINE_I3C_OR_I2C(inst)),			\
-			(LSM6DSV16X_DEFINE_I2C(inst)))));			\
-	LSM6DSV16X_DEVICE_INIT(inst)
+			     (LSM6DSV16X_DEFINE_I3C_OR_I2C(inst, prefix)),	\
+			     (LSM6DSV16X_DEFINE_I2C(inst, prefix)))));		\
+	LSM6DSV16X_DEVICE_INIT(inst, prefix)
+
+/* clang-format on */
+
+#define DT_DRV_COMPAT DT_DRV_COMPAT_LSM6DSV16X
+DT_INST_FOREACH_STATUS_OKAY_VARGS(LSM6DSV16X_DEFINE, lsm6dsv16x)
 
-DT_INST_FOREACH_STATUS_OKAY(LSM6DSV16X_DEFINE)
+#undef DT_DRV_COMPAT
+#define DT_DRV_COMPAT DT_DRV_COMPAT_LSM6DSV32X
+DT_INST_FOREACH_STATUS_OKAY_VARGS(LSM6DSV16X_DEFINE, lsm6dsv32x)
diff --git a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.h b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.h
index a6e26b6954e..244be1b24ac 100644
--- a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.h
+++ b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x.h
@@ -18,24 +18,33 @@
 #include <stmemsc.h>
 #include "lsm6dsv16x_reg.h"
 
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
+#define DT_DRV_COMPAT_LSM6DSV16X st_lsm6dsv16x
+#define DT_DRV_COMPAT_LSM6DSV32X st_lsm6dsv32x
+
+#define LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(bus)                                                \
+	(DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(DT_DRV_COMPAT_LSM6DSV16X, bus) ||                        \
+	 DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(DT_DRV_COMPAT_LSM6DSV32X, bus))
+
+#if LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(spi)
 #include <zephyr/drivers/spi.h>
-#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */
+#endif /* LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(spi) */
 
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
+#if LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
 #include <zephyr/drivers/i2c.h>
-#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */
+#endif /* LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */
 
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
+#if LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
 #include <zephyr/drivers/i3c.h>
-#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c) */
+#endif /* LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i3c) */
+
+bool lsm6dsv16x_is_active(const struct device *dev);
 
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
-	#define ON_I3C_BUS(cfg)  (cfg->i3c.bus != NULL)
-	#define I3C_INT_PIN(cfg) (cfg->int_en_i3c)
+#if LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
+#define ON_I3C_BUS(cfg)  (cfg->i3c.bus != NULL)
+#define I3C_INT_PIN(cfg) (cfg->int_en_i3c)
 #else
-	#define ON_I3C_BUS(cfg)  (false)
-	#define I3C_INT_PIN(cfg) (false)
+#define ON_I3C_BUS(cfg)  (false)
+#define I3C_INT_PIN(cfg) (false)
 #endif
 
 #define LSM6DSV16X_EN_BIT					0x01
@@ -47,25 +56,23 @@
 /* Gyro sensor sensitivity grain is 4.375 udps/LSB */
 #define GAIN_UNIT_G				(4375LL)
 
-int lsm6dsv16x_calc_accel_gain(uint8_t fs);
-int lsm6dsv16x_calc_gyro_gain(uint8_t fs);
-
 struct lsm6dsv16x_config {
 	stmdev_ctx_t ctx;
 	union {
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
+#if LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
 		const struct i2c_dt_spec i2c;
 #endif
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
+#if LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(spi)
 		const struct spi_dt_spec spi;
 #endif
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
+#if LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
 		struct i3c_device_desc **i3c;
 #endif
 	} stmemsc_cfg;
 	uint8_t accel_pm;
 	uint8_t accel_odr;
 	uint8_t accel_range;
+	const uint16_t *accel_fs_map;
 	uint8_t gyro_pm;
 	uint8_t gyro_odr;
 	uint8_t gyro_range;
@@ -83,13 +90,13 @@ struct lsm6dsv16x_config {
 	const struct gpio_dt_spec int2_gpio;
 	uint8_t drdy_pin;
 	bool trig_enabled;
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
+#if LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
 	bool int_en_i3c;
 	lsm6dsv16x_i3c_ibi_time_t bus_act_sel;
-#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c) */
+#endif /* LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i3c) */
 #endif /* CONFIG_LSM6DSV16X_TRIGGER */
 
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
+#if LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
 	struct {
 		const struct device *bus;
 		const struct i3c_device_id dev_id;
@@ -162,6 +169,9 @@ struct lsm6dsv16x_data {
 	uint8_t bus_type : 2; /* I2C is 0, SPI is 1, I3C is 2 */
 	uint8_t sflp_batch_odr : 3;
 	uint8_t reserved : 1;
+	int32_t gbias_x_udps;
+	int32_t gbias_y_udps;
+	int32_t gbias_z_udps;
 #endif
 
 #ifdef CONFIG_LSM6DSV16X_TRIGGER
@@ -172,8 +182,8 @@ struct lsm6dsv16x_data {
 	const struct sensor_trigger *trig_drdy_acc;
 	sensor_trigger_handler_t handler_drdy_gyr;
 	const struct sensor_trigger *trig_drdy_gyr;
-	sensor_trigger_handler_t handler_drdy_temp;
-	const struct sensor_trigger *trig_drdy_temp;
+	sensor_trigger_handler_t handler_wakeup;
+	const struct sensor_trigger *trig_wakeup;
 
 #if defined(CONFIG_LSM6DSV16X_TRIGGER_OWN_THREAD)
 	K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_LSM6DSV16X_THREAD_STACK_SIZE);
@@ -184,7 +194,7 @@ struct lsm6dsv16x_data {
 #endif
 #endif /* CONFIG_LSM6DSV16X_TRIGGER */
 
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
+#if LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
 	struct i3c_device_desc *i3c_dev;
 	struct lsm6dsv16x_ibi_payload ibi_payload;
 #endif
@@ -204,6 +214,9 @@ static inline uint8_t lsm6dsv16x_bus_reg(struct lsm6dsv16x_data *data, uint8_t x
 #define LSM6DSV16X_FIFO_SIZE(x) (x * LSM6DSV16X_FIFO_ITEM_LEN)
 #endif
 
+int lsm6dsv16x_accel_set_odr_raw(const struct device *dev, uint8_t odr);
+int lsm6dsv16x_gyro_set_odr_raw(const struct device *dev, uint8_t odr);
+
 #if defined(CONFIG_LSM6DSV16X_SENSORHUB)
 int lsm6dsv16x_shub_init(const struct device *dev);
 int lsm6dsv16x_shub_fetch_external_devs(const struct device *dev);
diff --git a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_decoder.c b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_decoder.c
index 1ea21ace988..3c9b05e6852 100644
--- a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_decoder.c
+++ b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_decoder.c
@@ -66,7 +66,7 @@ static const uint32_t sflp_period_ns[] = {
  * Expand val to q31_t according to its range; this is achieved multiplying by 2^31/2^range.
  */
 #define Q31_SHIFT_VAL(val, range) \
-	(q31_t) (round((val) * ((int64_t)1 << (31 - (range)))))
+	(q31_t) (roundf((val) * ((int64_t)1 << (31 - (range)))))
 
 /*
  * Expand micro_val (a generic micro unit) to q31_t according to its range; this is achieved
@@ -75,12 +75,18 @@ static const uint32_t sflp_period_ns[] = {
 #define Q31_SHIFT_MICROVAL(micro_val, range) \
 	(q31_t) ((int64_t)(micro_val) * ((int64_t)1 << (31 - (range))) / 1000000LL)
 
-/* bit range for Accelerometer for a given fs */
+/* bit range for Accelerometer for a given accel_fs_idx value */
 static const int8_t accel_range[] = {
-	[LSM6DSV16X_DT_FS_2G] = 5,
-	[LSM6DSV16X_DT_FS_4G] = 6,
-	[LSM6DSV16X_DT_FS_8G] = 7,
-	[LSM6DSV16X_DT_FS_16G] = 8,
+	/* LSM6DSV16X_DT_FS_2G */
+	5,
+	/* LSM6DSV16X_DT_FS_4G / LSM6DSV32X_DT_FS_4G*/
+	6,
+	/* LSM6DSV16X_DT_FS_8G / LSM6DSV32X_DT_FS_8G */
+	7,
+	/* LSM6DSV16X_DT_FS_16G / LSM6DSV32X_DT_FS_16G */
+	8,
+	/* LSM6DSV32X_DT_FS_32G */
+	9,
 };
 
 /* bit range for Gyroscope for a given fs */
@@ -108,14 +114,20 @@ static const int8_t temp_range = 9;
 	(int32_t)((ug_lsb) * SENSOR_G / 1000000LL)
 
 /*
- * Accelerometer scaling factors table (indexed by full scale)
+ * Accelerometer scaling factors table for a given accel_fs_idx value
  * GAIN_UNIT_XL is expressed in ug/LSB.
  */
 static const int32_t accel_scaler[] = {
-	[LSM6DSV16X_DT_FS_2G] = SENSOR_SCALE_UG_TO_UMS2(GAIN_UNIT_XL),
-	[LSM6DSV16X_DT_FS_4G] = SENSOR_SCALE_UG_TO_UMS2(2 * GAIN_UNIT_XL),
-	[LSM6DSV16X_DT_FS_8G] = SENSOR_SCALE_UG_TO_UMS2(4 * GAIN_UNIT_XL),
-	[LSM6DSV16X_DT_FS_16G] = SENSOR_SCALE_UG_TO_UMS2(8 * GAIN_UNIT_XL),
+	/* LSM6DSV16X_DT_FS_2G */
+	SENSOR_SCALE_UG_TO_UMS2(GAIN_UNIT_XL),
+	/* LSM6DSV16X_DT_FS_4G / LSM6DSV32X_DT_FS_4G */
+	SENSOR_SCALE_UG_TO_UMS2(2 * GAIN_UNIT_XL),
+	/* LSM6DSV16X_DT_FS_8G / LSM6DSV32X_DT_FS_8G*/
+	SENSOR_SCALE_UG_TO_UMS2(4 * GAIN_UNIT_XL),
+	/* LSM6DSV16X_DT_FS_16G / LSM6DSV32X_DT_FS_16G */
+	SENSOR_SCALE_UG_TO_UMS2(8 * GAIN_UNIT_XL),
+	/* LSM6DSV32X_DT_FS_32G */
+	SENSOR_SCALE_UG_TO_UMS2(16 * GAIN_UNIT_XL),
 };
 
 /* Calculate scaling factor to transform micro-dps/LSB unit into micro-rads/LSB */
@@ -318,7 +330,7 @@ static int lsm6dsv16x_decode_fifo(const uint8_t *buffer, struct sensor_chan_spec
 		case LSM6DSV16X_XL_NC_TAG: {
 			struct sensor_three_axis_data *out = data_out;
 			int16_t x, y, z;
-			const int32_t scale = accel_scaler[header->accel_fs];
+			const int32_t scale = accel_scaler[header->accel_fs_idx];
 
 			xl_count++;
 			if ((uintptr_t)buffer < *fit) {
@@ -339,7 +351,7 @@ static int lsm6dsv16x_decode_fifo(const uint8_t *buffer, struct sensor_chan_spec
 			y = *(int16_t *)&buffer[3];
 			z = *(int16_t *)&buffer[5];
 
-			out->shift = accel_range[header->accel_fs];
+			out->shift = accel_range[header->accel_fs_idx];
 
 			out->readings[count].x = Q31_SHIFT_MICROVAL(scale * x, out->shift);
 			out->readings[count].y = Q31_SHIFT_MICROVAL(scale * y, out->shift);
@@ -561,7 +573,7 @@ static int lsm6dsv16x_decode_sample(const uint8_t *buffer, struct sensor_chan_sp
 	case SENSOR_CHAN_ACCEL_Y:
 	case SENSOR_CHAN_ACCEL_Z:
 	case SENSOR_CHAN_ACCEL_XYZ: {
-		const int32_t scale = accel_scaler[header->accel_fs];
+		const int32_t scale = accel_scaler[header->accel_fs_idx];
 
 		if (edata->has_accel == 0) {
 			return -ENODATA;
@@ -572,7 +584,7 @@ static int lsm6dsv16x_decode_sample(const uint8_t *buffer, struct sensor_chan_sp
 		out->header.base_timestamp_ns = edata->header.timestamp;
 		out->header.reading_count = 1;
 
-		out->shift = accel_range[header->accel_fs];
+		out->shift = accel_range[header->accel_fs_idx];
 
 		out->readings[0].x = Q31_SHIFT_MICROVAL(scale * edata->acc[0], out->shift);
 		out->readings[0].y = Q31_SHIFT_MICROVAL(scale * edata->acc[1], out->shift);
diff --git a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_decoder.h b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_decoder.h
index 22553c96651..4ec25ec974f 100644
--- a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_decoder.h
+++ b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_decoder.h
@@ -12,12 +12,17 @@
 #include <stdint.h>
 #include <zephyr/drivers/sensor.h>
 
+/*
+ * This macro converts the Accelerometer full-scale range value (which should be a power of 2) to
+ * an index value used by the decoder. Note: this index is not the same as the RAW register value.
+ */
+#define LSM6DSV16X_ACCEL_FS_VAL_TO_FS_IDX(x) (__builtin_ctz(x) - 1)
+
 struct lsm6dsv16x_decoder_header {
 	uint64_t timestamp;
 	uint8_t is_fifo: 1;
 	uint8_t gyro_fs: 4;
-	uint8_t accel_fs: 2;
-	uint8_t reserved: 1;
+	uint8_t accel_fs_idx: 3;
 } __attribute__((__packed__));
 
 struct lsm6dsv16x_fifo_data {
diff --git a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_rtio.c b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_rtio.c
index c43f0c9b898..4d5cc6f9f44 100644
--- a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_rtio.c
+++ b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_rtio.c
@@ -11,6 +11,7 @@
 #include "lsm6dsv16x_rtio.h"
 #include "lsm6dsv16x_decoder.h"
 #include <zephyr/rtio/work.h>
+#include <zephyr/drivers/sensor_clock.h>
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(LSM6DSV16X_RTIO, CONFIG_SENSOR_LOG_LEVEL);
@@ -21,6 +22,7 @@ static void lsm6dsv16x_submit_sample(const struct device *dev, struct rtio_iodev
 	const struct sensor_chan_spec *const channels = cfg->channels;
 	const size_t num_channels = cfg->count;
 	uint32_t min_buf_len = sizeof(struct lsm6dsv16x_rtio_data);
+	uint64_t cycles;
 	int rc = 0;
 	uint8_t *buf;
 	uint32_t buf_len;
@@ -112,10 +114,18 @@ static void lsm6dsv16x_submit_sample(const struct device *dev, struct rtio_iodev
 		}
 	}
 
+	rc = sensor_clock_get_cycles(&cycles);
+	if (rc != 0) {
+		LOG_ERR("Failed to get sensor clock cycles");
+		rtio_iodev_sqe_err(iodev_sqe, rc);
+		goto err;
+	}
+
 	edata->header.is_fifo = false;
-	edata->header.accel_fs = data->accel_fs;
+	edata->header.accel_fs_idx =
+		LSM6DSV16X_ACCEL_FS_VAL_TO_FS_IDX(config->accel_fs_map[data->accel_fs]);
 	edata->header.gyro_fs = data->gyro_fs;
-	edata->header.timestamp = k_ticks_to_ns_floor64(k_uptime_ticks());
+	edata->header.timestamp = sensor_clock_cycles_to_ns(cycles);
 
 	rtio_iodev_sqe_ok(iodev_sqe, 0);
 
@@ -144,6 +154,10 @@ void lsm6dsv16x_submit_sync(struct rtio_iodev_sqe *iodev_sqe)
 
 void lsm6dsv16x_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
 {
+	if (!lsm6dsv16x_is_active(dev)) {
+		return;
+	}
+
 	struct rtio_work_req *req = rtio_work_req_alloc();
 
 	if (req == NULL) {
diff --git a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_rtio.h b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_rtio.h
index 9aa838ddd45..dc32327c852 100644
--- a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_rtio.h
+++ b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_rtio.h
@@ -12,6 +12,11 @@
 #include <zephyr/device.h>
 #include <zephyr/rtio/rtio.h>
 
+int lsm6dsv16x_gbias_config(const struct device *dev, enum sensor_channel chan,
+			    enum sensor_attribute attr,
+			    const struct sensor_value *val);
+int lsm6dsv16x_gbias_get_config(const struct device *dev, enum sensor_channel chan,
+				enum sensor_attribute attr, struct sensor_value *val);
 void lsm6dsv16x_submit(const struct device *sensor, struct rtio_iodev_sqe *iodev_sqe);
 
 void lsm6dsv16x_submit_stream(const struct device *sensor, struct rtio_iodev_sqe *iodev_sqe);
diff --git a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_rtio_stream.c b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_rtio_stream.c
index 27635c3e910..011d4dfbcaf 100644
--- a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_rtio_stream.c
+++ b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_rtio_stream.c
@@ -6,13 +6,12 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#define DT_DRV_COMPAT st_lsm6dsv16x
-
 #include <zephyr/dt-bindings/sensor/lsm6dsv16x.h>
 #include <zephyr/drivers/sensor.h>
 #include "lsm6dsv16x.h"
 #include "lsm6dsv16x_decoder.h"
 #include <zephyr/rtio/work.h>
+#include <zephyr/drivers/sensor_clock.h>
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_DECLARE(LSM6DSV16X_RTIO);
@@ -20,6 +19,45 @@ LOG_MODULE_DECLARE(LSM6DSV16X_RTIO);
 #define FIFO_TH 1
 #define FIFO_FULL 2
 
+int lsm6dsv16x_gbias_config(const struct device *dev, enum sensor_channel chan,
+			    enum sensor_attribute attr,
+			    const struct sensor_value *val)
+{
+	struct lsm6dsv16x_data *lsm6dsv16x = dev->data;
+
+	switch (attr) {
+	case SENSOR_ATTR_OFFSET:
+		lsm6dsv16x->gbias_x_udps = 10 * sensor_rad_to_10udegrees(&val[0]);
+		lsm6dsv16x->gbias_y_udps = 10 * sensor_rad_to_10udegrees(&val[1]);
+		lsm6dsv16x->gbias_z_udps = 10 * sensor_rad_to_10udegrees(&val[2]);
+		break;
+	default:
+		LOG_DBG("Accel attribute not supported.");
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+int lsm6dsv16x_gbias_get_config(const struct device *dev, enum sensor_channel chan,
+				enum sensor_attribute attr, struct sensor_value *val)
+{
+	struct lsm6dsv16x_data *lsm6dsv16x = dev->data;
+
+	switch (attr) {
+	case SENSOR_ATTR_OFFSET:
+		sensor_10udegrees_to_rad(lsm6dsv16x->gbias_x_udps / 10, &val[0]);
+		sensor_10udegrees_to_rad(lsm6dsv16x->gbias_y_udps / 10, &val[1]);
+		sensor_10udegrees_to_rad(lsm6dsv16x->gbias_z_udps / 10, &val[2]);
+		break;
+	default:
+		LOG_DBG("Accel attribute not supported.");
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
 static void lsm6dsv16x_config_fifo(const struct device *dev, uint8_t fifo_irq)
 {
 	struct lsm6dsv16x_data *lsm6dsv16x = dev->data;
@@ -33,6 +71,7 @@ static void lsm6dsv16x_config_fifo(const struct device *dev, uint8_t fifo_irq)
 	lsm6dsv16x_fifo_mode_t fifo_mode = LSM6DSV16X_BYPASS_MODE;
 	lsm6dsv16x_sflp_data_rate_t sflp_odr = LSM6DSV16X_SFLP_120Hz;
 	lsm6dsv16x_fifo_sflp_raw_t sflp_fifo = { 0 };
+	lsm6dsv16x_sflp_gbias_t gbias;
 
 	/* disable FIFO as first thing */
 	lsm6dsv16x_fifo_mode_set(ctx, LSM6DSV16X_BYPASS_MODE);
@@ -90,6 +129,52 @@ static void lsm6dsv16x_config_fifo(const struct device *dev, uint8_t fifo_irq)
 	lsm6dsv16x_fifo_sflp_batch_set(ctx, sflp_fifo);
 	lsm6dsv16x_sflp_game_rotation_set(ctx, PROPERTY_ENABLE);
 
+	/*
+	 * Temporarly set Accel and gyro odr same as sensor fusion LP in order to
+	 * make the SFLP gbias setting effective. Then restore it to saved values.
+	 */
+	switch (sflp_odr) {
+	case LSM6DSV16X_DT_SFLP_ODR_AT_480Hz:
+		lsm6dsv16x_accel_set_odr_raw(dev, LSM6DSV16X_DT_ODR_AT_480Hz);
+		lsm6dsv16x_gyro_set_odr_raw(dev, LSM6DSV16X_DT_ODR_AT_480Hz);
+		break;
+
+	case LSM6DSV16X_DT_SFLP_ODR_AT_240Hz:
+		lsm6dsv16x_accel_set_odr_raw(dev, LSM6DSV16X_DT_ODR_AT_240Hz);
+		lsm6dsv16x_gyro_set_odr_raw(dev, LSM6DSV16X_DT_ODR_AT_240Hz);
+		break;
+
+	case LSM6DSV16X_DT_SFLP_ODR_AT_120Hz:
+		lsm6dsv16x_accel_set_odr_raw(dev, LSM6DSV16X_DT_ODR_AT_120Hz);
+		lsm6dsv16x_gyro_set_odr_raw(dev, LSM6DSV16X_DT_ODR_AT_120Hz);
+		break;
+
+	case LSM6DSV16X_DT_SFLP_ODR_AT_60Hz:
+		lsm6dsv16x_accel_set_odr_raw(dev, LSM6DSV16X_DT_ODR_AT_60Hz);
+		lsm6dsv16x_gyro_set_odr_raw(dev, LSM6DSV16X_DT_ODR_AT_60Hz);
+		break;
+
+	case LSM6DSV16X_DT_SFLP_ODR_AT_30Hz:
+		lsm6dsv16x_accel_set_odr_raw(dev, LSM6DSV16X_DT_ODR_AT_30Hz);
+		lsm6dsv16x_gyro_set_odr_raw(dev, LSM6DSV16X_DT_ODR_AT_30Hz);
+		break;
+
+	case LSM6DSV16X_DT_SFLP_ODR_AT_15Hz:
+		lsm6dsv16x_accel_set_odr_raw(dev, LSM6DSV16X_DT_ODR_AT_15Hz);
+		lsm6dsv16x_gyro_set_odr_raw(dev, LSM6DSV16X_DT_ODR_AT_15Hz);
+		break;
+	}
+
+	/* set sflp gbias */
+	gbias.gbias_x = (float)lsm6dsv16x->gbias_x_udps / 1000000;
+	gbias.gbias_y = (float)lsm6dsv16x->gbias_y_udps / 1000000;
+	gbias.gbias_z = (float)lsm6dsv16x->gbias_z_udps / 1000000;
+	lsm6dsv16x_sflp_game_gbias_set(ctx, &gbias);
+
+	/* restore accel/gyro odr to saved values */
+	lsm6dsv16x_accel_set_odr_raw(dev, lsm6dsv16x->accel_freq);
+	lsm6dsv16x_gyro_set_odr_raw(dev, lsm6dsv16x->gyro_freq);
+
 	/* Set pin interrupt (fifo_th could be on or off) */
 	if ((config->drdy_pin == 1) || (ON_I3C_BUS(config) && (!I3C_INT_PIN(config)))) {
 		lsm6dsv16x_pin_int1_route_set(ctx, &pin_int);
@@ -101,7 +186,7 @@ static void lsm6dsv16x_config_fifo(const struct device *dev, uint8_t fifo_irq)
 void lsm6dsv16x_submit_stream(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
 {
 	struct lsm6dsv16x_data *lsm6dsv16x = dev->data;
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
+#if LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
 	const struct lsm6dsv16x_config *config = dev->config;
 #endif
 	const struct sensor_read_config *cfg = iodev_sqe->sqe.iodev->data;
@@ -137,7 +222,7 @@ void lsm6dsv16x_submit_stream(const struct device *dev, struct rtio_iodev_sqe *i
 static void lsm6dsv16x_complete_op_cb(struct rtio *r, const struct rtio_sqe *sqe, void *arg)
 {
 	const struct device *dev = arg;
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
+#if LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
 	const struct lsm6dsv16x_config *config = dev->config;
 #endif
 	struct lsm6dsv16x_data *lsm6dsv16x = dev->data;
@@ -155,9 +240,7 @@ static void lsm6dsv16x_complete_op_cb(struct rtio *r, const struct rtio_sqe *sqe
 static void lsm6dsv16x_read_fifo_cb(struct rtio *r, const struct rtio_sqe *sqe, void *arg)
 {
 	const struct device *dev = arg;
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
 	const struct lsm6dsv16x_config *config = dev->config;
-#endif
 	struct lsm6dsv16x_data *lsm6dsv16x = dev->data;
 	struct gpio_dt_spec *irq_gpio = lsm6dsv16x->drdy_gpio;
 	struct rtio_iodev *iodev = lsm6dsv16x->iodev;
@@ -314,10 +397,12 @@ static void lsm6dsv16x_read_fifo_cb(struct rtio *r, const struct rtio_sqe *sqe,
 		return;
 	}
 
+	/* clang-format off */
 	struct lsm6dsv16x_fifo_data hdr = {
 		.header = {
 			.is_fifo = true,
-			.accel_fs = lsm6dsv16x->accel_fs,
+			.accel_fs_idx = LSM6DSV16X_ACCEL_FS_VAL_TO_FS_IDX(
+				config->accel_fs_map[lsm6dsv16x->accel_fs]),
 			.gyro_fs = lsm6dsv16x->gyro_fs,
 			.timestamp = lsm6dsv16x->fifo_timestamp,
 		},
@@ -329,6 +414,7 @@ static void lsm6dsv16x_read_fifo_cb(struct rtio *r, const struct rtio_sqe *sqe,
 #endif
 		.sflp_batch_odr = lsm6dsv16x->sflp_batch_odr,
 	};
+	/* clang-format on */
 
 	memcpy(buf, &hdr, sizeof(hdr));
 	read_buf = buf + sizeof(hdr);
@@ -374,18 +460,27 @@ void lsm6dsv16x_stream_irq_handler(const struct device *dev)
 {
 	struct lsm6dsv16x_data *lsm6dsv16x = dev->data;
 	struct rtio_iodev *iodev = lsm6dsv16x->iodev;
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
+#if LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
 	const struct lsm6dsv16x_config *config = dev->config;
 #endif
+	uint64_t cycles;
+	int rc;
 
 	if (lsm6dsv16x->streaming_sqe == NULL) {
 		return;
 	}
 
+	rc = sensor_clock_get_cycles(&cycles);
+	if (rc != 0) {
+		LOG_ERR("Failed to get sensor clock cycles");
+		rtio_iodev_sqe_err(lsm6dsv16x->streaming_sqe, rc);
+		return;
+	}
+
 	/* get timestamp as soon as the irq is served */
-	lsm6dsv16x->fifo_timestamp = k_ticks_to_ns_floor64(k_uptime_ticks());
+	lsm6dsv16x->fifo_timestamp = sensor_clock_cycles_to_ns(cycles);
 
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
+#if LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
 	if (ON_I3C_BUS(config) && (!I3C_INT_PIN(config))) {
 		/*
 		 * If we are on an I3C bus, then it should be expected that the fifo status was
diff --git a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_shub.c b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_shub.c
index 93d92290ac6..8445983c2e6 100644
--- a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_shub.c
+++ b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_shub.c
@@ -8,8 +8,6 @@
  * https://www.st.com/resource/en/datasheet/lsm6dsv16x.pdf
  */
 
-#define DT_DRV_COMPAT st_lsm6dsv16x
-
 #include <zephyr/device.h>
 #include <zephyr/drivers/i2c.h>
 #include <zephyr/sys/__assert.h>
diff --git a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_trigger.c b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_trigger.c
index 83df5c9e175..46ce9cbd161 100644
--- a/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_trigger.c
+++ b/drivers/sensor/st/lsm6dsv16x/lsm6dsv16x_trigger.c
@@ -8,8 +8,6 @@
  * https://www.st.com/resource/en/datasheet/lsm6dsv16x.pdf
  */
 
-#define DT_DRV_COMPAT st_lsm6dsv16x
-
 #include <zephyr/kernel.h>
 #include <zephyr/drivers/sensor.h>
 #include <zephyr/drivers/gpio.h>
@@ -112,6 +110,53 @@ static int lsm6dsv16x_enable_g_int(const struct device *dev, int enable)
 	return ret;
 }
 
+/**
+ * lsm6dsv16x_enable_wake_int - Enable selected int pin to generate wakeup interrupt
+ */
+static int lsm6dsv16x_enable_wake_int(const struct device *dev, int enable)
+{
+	const struct lsm6dsv16x_config *cfg = dev->config;
+	stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
+	int ret;
+	lsm6dsv16x_interrupt_mode_t int_mode;
+
+	int_mode.enable = enable ? 1 : 0;
+	int_mode.lir = !cfg->drdy_pulsed;
+	ret = lsm6dsv16x_interrupt_enable_set(ctx, int_mode);
+	if (ret < 0) {
+		LOG_ERR("interrupt_enable_set error");
+		return ret;
+	}
+
+	if ((cfg->drdy_pin == 1) || ON_I3C_BUS(cfg)) {
+		lsm6dsv16x_pin_int_route_t val;
+
+		ret = lsm6dsv16x_pin_int1_route_get(ctx, &val);
+		if (ret < 0) {
+			LOG_ERR("pint_int1_route_get error");
+			return ret;
+		}
+
+		val.wakeup = enable ? 1 : 0;
+
+		ret = lsm6dsv16x_pin_int1_route_set(ctx, &val);
+	} else {
+		lsm6dsv16x_pin_int_route_t val;
+
+		ret = lsm6dsv16x_pin_int2_route_get(ctx, &val);
+		if (ret < 0) {
+			LOG_ERR("pint_int2_route_get error");
+			return ret;
+		}
+
+		val.wakeup = enable ? 1 : 0;
+
+		ret = lsm6dsv16x_pin_int2_route_set(ctx, &val);
+	}
+
+	return ret;
+}
+
 /**
  * lsm6dsv16x_trigger_set - link external trigger to event data ready
  */
@@ -133,6 +178,10 @@ int lsm6dsv16x_trigger_set(const struct device *dev,
 		return -EINVAL;
 	}
 
+	if (!lsm6dsv16x_is_active(dev)) {
+		return -EBUSY;
+	}
+
 	switch (trig->type) {
 	case SENSOR_TRIG_DATA_READY:
 		if (trig->chan == SENSOR_CHAN_ACCEL_XYZ) {
@@ -152,7 +201,18 @@ int lsm6dsv16x_trigger_set(const struct device *dev,
 				lsm6dsv16x_enable_g_int(dev, LSM6DSV16X_DIS_BIT);
 			}
 		}
-
+		break;
+	case SENSOR_TRIG_DELTA:
+		if (trig->chan != SENSOR_CHAN_ACCEL_XYZ) {
+			return -ENOTSUP;
+		}
+		lsm6dsv16x->handler_wakeup = handler;
+		lsm6dsv16x->trig_wakeup = trig;
+		if (handler) {
+			lsm6dsv16x_enable_wake_int(dev, LSM6DSV16X_EN_BIT);
+		} else {
+			lsm6dsv16x_enable_wake_int(dev, LSM6DSV16X_DIS_BIT);
+		}
 		break;
 	default:
 		ret = -ENOTSUP;
@@ -174,6 +234,7 @@ static void lsm6dsv16x_handle_interrupt(const struct device *dev)
 	const struct lsm6dsv16x_config *cfg = dev->config;
 	stmdev_ctx_t *ctx = (stmdev_ctx_t *)&cfg->ctx;
 	lsm6dsv16x_data_ready_t status;
+	lsm6dsv16x_all_int_src_t all_int_src;
 	int ret;
 
 	while (1) {
@@ -190,7 +251,13 @@ static void lsm6dsv16x_handle_interrupt(const struct device *dev)
 			return;
 		}
 
-		if (((status.drdy_xl == 0) && (status.drdy_gy == 0)) ||
+		ret = lsm6dsv16x_read_reg(ctx, LSM6DSV16X_ALL_INT_SRC, (uint8_t *)&all_int_src, 1);
+		if (ret < 0) {
+			LOG_DBG("failed reading all_int_src reg");
+			return;
+		}
+
+		if (((status.drdy_xl == 0) && (status.drdy_gy == 0) && (all_int_src.wu_ia == 0)) ||
 		    IS_ENABLED(CONFIG_LSM6DSV16X_STREAM)) {
 			break;
 		}
@@ -203,6 +270,9 @@ static void lsm6dsv16x_handle_interrupt(const struct device *dev)
 			lsm6dsv16x->handler_drdy_gyr(dev, lsm6dsv16x->trig_drdy_gyr);
 		}
 
+		if ((all_int_src.wu_ia) && lsm6dsv16x->handler_wakeup != NULL) {
+			lsm6dsv16x->handler_wakeup(dev, lsm6dsv16x->trig_wakeup);
+		}
 	}
 
 	if (!ON_I3C_BUS(cfg) || (I3C_INT_PIN(cfg))) {
@@ -269,7 +339,7 @@ static void lsm6dsv16x_work_cb(struct k_work *work)
 }
 #endif /* CONFIG_LSM6DSV16X_TRIGGER_GLOBAL_THREAD */
 
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
+#if LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
 static int lsm6dsv16x_ibi_cb(struct i3c_device_desc *target,
 			  struct i3c_ibi_payload *payload)
 {
@@ -374,7 +444,7 @@ int lsm6dsv16x_init_interrupt(const struct device *dev)
 		return ret;
 	}
 
-#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
+#if LSM6DSVXXX_ANY_INST_ON_BUS_STATUS_OKAY(i3c)
 	if (ON_I3C_BUS(cfg)) {
 		if (I3C_INT_PIN(cfg)) {
 			/* Enable INT Pins when using I3C */
diff --git a/drivers/sensor/st/lsm9ds0_mfd/lsm9ds0_mfd.c b/drivers/sensor/st/lsm9ds0_mfd/lsm9ds0_mfd.c
index 5186eb0f009..3db5aa8d27a 100644
--- a/drivers/sensor/st/lsm9ds0_mfd/lsm9ds0_mfd.c
+++ b/drivers/sensor/st/lsm9ds0_mfd/lsm9ds0_mfd.c
@@ -38,7 +38,8 @@ static inline int lsm9ds0_mfd_reboot_memory(const struct device *dev)
 	return 0;
 }
 
-#if !defined(LSM9DS0_MFD_ACCEL_DISABLED)
+#if !defined(LSM9DS0_MFD_ACCEL_DISABLED) && defined(CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_RUNTIME)
+
 static inline int lsm9ds0_mfd_accel_set_odr_raw(const struct device *dev,
 						uint8_t odr)
 {
@@ -49,7 +50,6 @@ static inline int lsm9ds0_mfd_accel_set_odr_raw(const struct device *dev,
 				      odr << LSM9DS0_MFD_SHIFT_CTRL_REG1_XM_AODR);
 }
 
-#if defined(CONFIG_LSM9DS0_MFD_ACCEL_SAMPLING_RATE_RUNTIME)
 static const struct {
 	int freq_int;
 	int freq_micro;
@@ -122,7 +122,6 @@ static int lsm9ds0_mfd_accel_set_fs(const struct device *dev, int val)
 	return -ENOTSUP;
 }
 #endif
-#endif
 
 #if !defined(LSM9DS0_MFD_MAGN_DISABLED)
 static inline int lsm9ds0_mfd_magn_set_odr_raw(const struct device *dev,
diff --git a/drivers/sensor/st/stm32_temp/stm32_temp.c b/drivers/sensor/st/stm32_temp/stm32_temp.c
index f6d70c96f59..d306caafb9e 100644
--- a/drivers/sensor/st/stm32_temp/stm32_temp.c
+++ b/drivers/sensor/st/stm32_temp/stm32_temp.c
@@ -13,7 +13,7 @@
 #include <zephyr/pm/device_runtime.h>
 #include <stm32_ll_adc.h>
 #if defined(CONFIG_SOC_SERIES_STM32H5X)
-#include <stm32_ll_icache.h>
+#include <zephyr/cache.h>
 #endif /* CONFIG_SOC_SERIES_STM32H5X */
 
 LOG_MODULE_REGISTER(stm32_temp, CONFIG_SENSOR_LOG_LEVEL);
@@ -105,7 +105,7 @@ static void read_calibration_data(const struct stm32_temp_config *cfg,
 	 * This is required on STM32H5, where the manufacturing flash must be
 	 * accessed in non-cacheable mode - otherwise, a bus error occurs.
 	 */
-	LL_ICACHE_Disable();
+	sys_cache_instr_disable();
 #endif /* CONFIG_SOC_SERIES_STM32H5X */
 
 	calib_data[0] = fetch_mfg_data(cfg->ts_cal1_addr);
@@ -116,7 +116,7 @@ static void read_calibration_data(const struct stm32_temp_config *cfg,
 
 #if defined(CONFIG_SOC_SERIES_STM32H5X)
 	/* Re-enable the ICACHE (unconditonally - it should always be turned on) */
-	LL_ICACHE_Enable();
+	sys_cache_instr_enable();
 #endif /* CONFIG_SOC_SERIES_STM32H5X */
 }
 #endif /* HAS_CALIBRATION */
diff --git a/drivers/sensor/st/stm32_vref/stm32_vref.c b/drivers/sensor/st/stm32_vref/stm32_vref.c
index 95148e45d6c..2f2c847ea0b 100644
--- a/drivers/sensor/st/stm32_vref/stm32_vref.c
+++ b/drivers/sensor/st/stm32_vref/stm32_vref.c
@@ -14,7 +14,7 @@
 #include <zephyr/pm/device_runtime.h>
 #include <stm32_ll_adc.h>
 #if defined(CONFIG_SOC_SERIES_STM32H5X)
-#include <stm32_ll_icache.h>
+#include <zephyr/cache.h>
 #endif /* CONFIG_SOC_SERIES_STM32H5X */
 
 LOG_MODULE_REGISTER(stm32_vref, CONFIG_SENSOR_LOG_LEVEL);
@@ -103,14 +103,14 @@ static int stm32_vref_channel_get(const struct device *dev, enum sensor_channel
  * STM32H5X: accesses to flash RO region must be done with caching disabled.
  */
 #if defined(CONFIG_SOC_SERIES_STM32H5X)
-	LL_ICACHE_Disable();
+	sys_cache_instr_disable();
 #endif /* CONFIG_SOC_SERIES_STM32H5X */
 
 	/* Calculate VREF+ using VREFINT bandgap voltage and calibration data */
 	vref = (cfg->cal_mv * ((*cfg->cal_addr) >> cfg->cal_shift)) / data->raw;
 
 #if defined(CONFIG_SOC_SERIES_STM32H5X)
-	LL_ICACHE_Enable();
+	sys_cache_instr_enable();
 #endif /* CONFIG_SOC_SERIES_STM32H5X */
 
 	return sensor_value_from_milli(val, vref);
diff --git a/drivers/sensor/st/stmemsc/Kconfig b/drivers/sensor/st/stmemsc/Kconfig
new file mode 100644
index 00000000000..bf509065d4e
--- /dev/null
+++ b/drivers/sensor/st/stmemsc/Kconfig
@@ -0,0 +1,13 @@
+# ST MEMS sensor configuration options
+
+# Copyright (c) 2025 Meta Platforms
+# SPDX-License-Identifier: Apache-2.0
+
+config STMEMSC_I3C_I2C_WRITE_BUFFER_SIZE
+	int "ST memsc I2C write buffer size"
+	default 16
+	depends on I2C || I3C
+	depends on HAS_STMEMSC
+	help
+	  The size of the buffer pushed on the stack used to copy
+	  the data to be written along with the register address.
diff --git a/drivers/sensor/st/stmemsc/stmemsc_i2c.c b/drivers/sensor/st/stmemsc/stmemsc_i2c.c
index bf6ddebbd4f..25652196faa 100644
--- a/drivers/sensor/st/stmemsc/stmemsc_i2c.c
+++ b/drivers/sensor/st/stmemsc/stmemsc_i2c.c
@@ -21,7 +21,14 @@ int stmemsc_i2c_read(const struct i2c_dt_spec *stmemsc,
 int stmemsc_i2c_write(const struct i2c_dt_spec *stmemsc,
 		      uint8_t reg_addr, uint8_t *value, uint8_t len)
 {
-	return i2c_burst_write_dt(stmemsc, reg_addr, value, len);
+	uint8_t buf[CONFIG_STMEMSC_I3C_I2C_WRITE_BUFFER_SIZE];
+
+	__ASSERT_NO_MSG(len <= sizeof(buf) - 1);
+
+	buf[0] = reg_addr;
+	memcpy(&buf[1], value, len);
+
+	return i2c_write_dt(stmemsc, buf, len + 1);
 }
 
 int stmemsc_i2c_read_incr(const struct i2c_dt_spec *stmemsc,
@@ -34,6 +41,12 @@ int stmemsc_i2c_read_incr(const struct i2c_dt_spec *stmemsc,
 int stmemsc_i2c_write_incr(const struct i2c_dt_spec *stmemsc,
 			   uint8_t reg_addr, uint8_t *value, uint8_t len)
 {
-	reg_addr |= STMEMSC_I2C_ADDR_AUTO_INCR;
-	return stmemsc_i2c_write(stmemsc, reg_addr, value, len);
+	uint8_t buf[CONFIG_STMEMSC_I3C_I2C_WRITE_BUFFER_SIZE];
+
+	__ASSERT_NO_MSG(len <= sizeof(buf) - 1);
+
+	buf[0] = reg_addr | STMEMSC_I2C_ADDR_AUTO_INCR;
+	memcpy(&buf[1], value, len);
+
+	return i2c_write_dt(stmemsc, buf, len + 1);
 }
diff --git a/drivers/sensor/st/stmemsc/stmemsc_i3c.c b/drivers/sensor/st/stmemsc/stmemsc_i3c.c
index 04b7446170c..6ef6b65c754 100644
--- a/drivers/sensor/st/stmemsc/stmemsc_i3c.c
+++ b/drivers/sensor/st/stmemsc/stmemsc_i3c.c
@@ -21,6 +21,12 @@ int stmemsc_i3c_write(void *stmemsc,
 		      uint8_t reg_addr, uint8_t *value, uint8_t len)
 {
 	struct i3c_device_desc *target = **(struct i3c_device_desc ***)stmemsc;
+	uint8_t buf[CONFIG_STMEMSC_I3C_I2C_WRITE_BUFFER_SIZE];
 
-	return i3c_burst_write(target, reg_addr, value, len);
+	__ASSERT_NO_MSG(len <= sizeof(buf) - 1);
+
+	buf[0] = reg_addr;
+	memcpy(&buf[1], value, len);
+
+	return i3c_write(target, buf, len + 1);
 }
diff --git a/drivers/sensor/st/stmemsc/stmemsc_spi.c b/drivers/sensor/st/stmemsc/stmemsc_spi.c
index 3d728c78d8b..66421f17ca0 100644
--- a/drivers/sensor/st/stmemsc/stmemsc_spi.c
+++ b/drivers/sensor/st/stmemsc/stmemsc_spi.c
@@ -63,13 +63,19 @@ int stmemsc_spi_write(const struct spi_dt_spec *stmemsc,
 int stmemsc_spi_read_incr(const struct spi_dt_spec *stmemsc,
 			  uint8_t reg_addr, uint8_t *value, uint8_t len)
 {
-	reg_addr |= STMEMSC_SPI_ADDR_AUTO_INCR;
+	if (len > 1) {
+		reg_addr |= STMEMSC_SPI_ADDR_AUTO_INCR;
+	}
+
 	return stmemsc_spi_read(stmemsc, reg_addr, value, len);
 }
 
 int stmemsc_spi_write_incr(const struct spi_dt_spec *stmemsc,
 			   uint8_t reg_addr, uint8_t *value, uint8_t len)
 {
-	reg_addr |= STMEMSC_SPI_ADDR_AUTO_INCR;
+	if (len > 1) {
+		reg_addr |= STMEMSC_SPI_ADDR_AUTO_INCR;
+	}
+
 	return stmemsc_spi_write(stmemsc, reg_addr, value, len);
 }
diff --git a/drivers/sensor/st/stts751/stts751.c b/drivers/sensor/st/stts751/stts751.c
index 00bdf3288f2..66f3456b86f 100644
--- a/drivers/sensor/st/stts751/stts751.c
+++ b/drivers/sensor/st/stts751/stts751.c
@@ -35,7 +35,7 @@ static int stts751_sample_fetch(const struct device *dev,
 	struct stts751_data *data = dev->data;
 	int16_t raw_temp;
 
-	__ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL);
+	__ASSERT_NO_MSG(chan == SENSOR_CHAN_AMBIENT_TEMP || chan == SENSOR_CHAN_ALL);
 
 	if (stts751_temperature_raw_get(data->ctx, &raw_temp) < 0) {
 		LOG_DBG("Failed to read sample");
diff --git a/drivers/sensor/st/vl53l0x/vl53l0x.c b/drivers/sensor/st/vl53l0x/vl53l0x.c
index 569288f0851..b43046250cd 100644
--- a/drivers/sensor/st/vl53l0x/vl53l0x.c
+++ b/drivers/sensor/st/vl53l0x/vl53l0x.c
@@ -20,12 +20,16 @@
 #include <zephyr/types.h>
 #include <zephyr/device.h>
 #include <zephyr/logging/log.h>
+#include <zephyr/drivers/sensor/vl53l0x.h>
 
 #include "vl53l0x_api.h"
 #include "vl53l0x_platform.h"
 
 LOG_MODULE_REGISTER(VL53L0X, CONFIG_SENSOR_LOG_LEVEL);
 
+#define VL53L0X_FIXPOINT1616_SCALE_FACTOR (65536)
+#define VL53L0X_SENSOR_CHANNEL_VAL2_FACTOR (1000000)
+
 /* All the values used in this driver are coming from ST datasheet and examples.
  * It can be found here:
  *   https://www.st.com/en/embedded-software/stsw-img005.html
@@ -288,6 +292,26 @@ static int vl53l0x_channel_get(const struct device *dev,
 	} else if (chan == SENSOR_CHAN_DISTANCE) {
 		val->val1 = drv_data->RangingMeasurementData.RangeMilliMeter / 1000;
 		val->val2 = (drv_data->RangingMeasurementData.RangeMilliMeter % 1000) * 1000;
+	} else if ((enum sensor_channel_vl53l0x)chan ==
+			SENSOR_CHAN_VL53L0X_EFFECTIVE_SPAD_RTN_COUNT) {
+		val->val1 = drv_data->RangingMeasurementData.EffectiveSpadRtnCount / 256;
+		val->val2 = 0;
+	} else if ((enum sensor_channel_vl53l0x)chan == SENSOR_CHAN_VL53L0X_AMBIENT_RATE_RTN_CPS) {
+		val->val1 = (drv_data->RangingMeasurementData.AmbientRateRtnMegaCps >> 16) +
+			(((drv_data->RangingMeasurementData.AmbientRateRtnMegaCps & 0xFFFF) *
+			  VL53L0X_SENSOR_CHANNEL_VAL2_FACTOR) / VL53L0X_FIXPOINT1616_SCALE_FACTOR);
+		val->val2 = 0;
+	} else if ((enum sensor_channel_vl53l0x)chan == SENSOR_CHAN_VL53L0X_SIGNAL_RATE_RTN_CPS) {
+		val->val1 = (drv_data->RangingMeasurementData.SignalRateRtnMegaCps >> 16) +
+			(((drv_data->RangingMeasurementData.SignalRateRtnMegaCps & 0xFFFF) *
+			  VL53L0X_SENSOR_CHANNEL_VAL2_FACTOR) / VL53L0X_FIXPOINT1616_SCALE_FACTOR);
+		val->val2 = 0;
+	} else if ((enum sensor_channel_vl53l0x)chan == SENSOR_CHAN_VL53L0X_RANGE_DMAX) {
+		val->val1 = drv_data->RangingMeasurementData.RangeDMaxMilliMeter / 1000;
+		val->val2 = (drv_data->RangingMeasurementData.RangeDMaxMilliMeter % 1000) * 1000;
+	} else if ((enum sensor_channel_vl53l0x)chan == SENSOR_CHAN_VL53L0X_RANGE_STATUS) {
+		val->val1 = drv_data->RangingMeasurementData.RangeStatus;
+		val->val2 = 0;
 	} else {
 		return -ENOTSUP;
 	}
diff --git a/drivers/sensor/tdk/CMakeLists.txt b/drivers/sensor/tdk/CMakeLists.txt
index 0f5c85a2db0..09936cd4d8b 100644
--- a/drivers/sensor/tdk/CMakeLists.txt
+++ b/drivers/sensor/tdk/CMakeLists.txt
@@ -3,9 +3,11 @@
 
 # zephyr-keep-sorted-start
 add_subdirectory_ifdef(CONFIG_ICM42605 icm42605)
-add_subdirectory_ifdef(CONFIG_ICM42670 icm42670)
 add_subdirectory_ifdef(CONFIG_ICM42688 icm42688)
-add_subdirectory_ifdef(CONFIG_ICP10125 icp10125)
+add_subdirectory_ifdef(CONFIG_ICM42X70 icm42x70)
+add_subdirectory_ifdef(CONFIG_ICM45686 icm45686)
+add_subdirectory_ifdef(CONFIG_ICP101XX icp101xx)
+add_subdirectory_ifdef(CONFIG_ICP201XX icp201xx)
 add_subdirectory_ifdef(CONFIG_MPU6050 mpu6050)
 add_subdirectory_ifdef(CONFIG_MPU9250 mpu9250)
 # zephyr-keep-sorted-stop
diff --git a/drivers/sensor/tdk/Kconfig b/drivers/sensor/tdk/Kconfig
index 57d92f9faf6..2b9163a7409 100644
--- a/drivers/sensor/tdk/Kconfig
+++ b/drivers/sensor/tdk/Kconfig
@@ -3,9 +3,11 @@
 
 # zephyr-keep-sorted-start
 source "drivers/sensor/tdk/icm42605/Kconfig"
-source "drivers/sensor/tdk/icm42670/Kconfig"
 source "drivers/sensor/tdk/icm42688/Kconfig"
-source "drivers/sensor/tdk/icp10125/Kconfig"
+source "drivers/sensor/tdk/icm42x70/Kconfig"
+source "drivers/sensor/tdk/icm45686/Kconfig"
+source "drivers/sensor/tdk/icp101xx/Kconfig"
+source "drivers/sensor/tdk/icp201xx/Kconfig"
 source "drivers/sensor/tdk/mpu6050/Kconfig"
 source "drivers/sensor/tdk/mpu9250/Kconfig"
 # zephyr-keep-sorted-stop
diff --git a/drivers/sensor/tdk/icm42670/CMakeLists.txt b/drivers/sensor/tdk/icm42670/CMakeLists.txt
deleted file mode 100644
index f15f3339897..00000000000
--- a/drivers/sensor/tdk/icm42670/CMakeLists.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library()
-
-zephyr_library_sources(icm42670.c)
-
-zephyr_library_sources_ifdef(CONFIG_SPI icm42670_spi.c)
-zephyr_library_sources_ifdef(CONFIG_I2C icm42670_i2c.c)
-
-zephyr_library_sources_ifdef(CONFIG_ICM42670_TRIGGER icm42670_trigger.c)
-zephyr_library_sources_ifdef(CONFIG_TDK_APEX icm42670_apex.c)
diff --git a/drivers/sensor/tdk/icm42670/Kconfig b/drivers/sensor/tdk/icm42670/Kconfig
deleted file mode 100644
index a5b06e7af10..00000000000
--- a/drivers/sensor/tdk/icm42670/Kconfig
+++ /dev/null
@@ -1,76 +0,0 @@
-# ICM42670-P ICM42670-S Six-Axis Motion Tracking device configuration options
-#
-# Copyright (c) 2024 TDK Invensense
-# Copyright (c) 2022 Esco Medical ApS
-# Copyright (c) 2020 TDK Invensense
-#
-# SPDX-License-Identifier: Apache-2.0
-config TDK_APEX
-	bool "TDK APEX features"
-
-menuconfig ICM42670
-	bool "ICM42670-P/-S Six-Axis Motion Tracking Device"
-	default y
-	depends on DT_HAS_INVENSENSE_ICM42670P_ENABLED \
-		|| DT_HAS_INVENSENSE_ICM42670S_ENABLED
-	depends on ZEPHYR_HAL_TDK_MODULE
-	select SPI if $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM42670P),spi) \
-		|| $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM42670S),spi)
-	select I2C if $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM42670P),i2c) \
-		|| $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM42670S),i2c)
-	select TDK_APEX if $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42670p),apex,pedometer) \
-		|| $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42670p),apex,tilt) \
-		|| $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42670p),apex,smd) \
-		|| $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42670p),apex,wom) \
-		|| $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42670s),apex,pedometer) \
-		|| $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42670s),apex,tilt) \
-		|| $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42670s),apex,smd) \
-		|| $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42670s),apex,wom)
-	help
-	  Enable driver for ICM42670 SPI-based or I2C-based Six-Axis Motion Tracking device.
-
-if ICM42670
-
-choice ICM42670_TRIGGER_MODE
-	prompt "Trigger mode"
-	default ICM42670_TRIGGER_NONE
-	help
-	  Specify the type of triggering to be used by the driver.
-
-config ICM42670_TRIGGER_NONE
-	bool "No trigger"
-
-config ICM42670_TRIGGER_GLOBAL_THREAD
-	bool "Use global thread"
-	depends on GPIO
-	depends on $(dt_compat_any_has_prop,$(DT_COMPAT_INVENSENSE_ICM42670P),int-gpios) \
-		|| $(dt_compat_any_has_prop,$(DT_COMPAT_INVENSENSE_ICM42670S),int-gpios)
-	select ICM42670_TRIGGER
-
-config ICM42670_TRIGGER_OWN_THREAD
-	bool "Use own thread"
-	depends on GPIO
-	depends on $(dt_compat_any_has_prop,$(DT_COMPAT_INVENSENSE_ICM42670P),int-gpios) \
-		|| $(dt_compat_any_has_prop,$(DT_COMPAT_INVENSENSE_ICM42670S),int-gpios)
-	select ICM42670_TRIGGER
-
-endchoice
-
-config ICM42670_TRIGGER
-	bool
-
-config ICM42670_THREAD_PRIORITY
-	int "Thread priority"
-	depends on ICM42670_TRIGGER_OWN_THREAD
-	default 10
-	help
-	  Priority of thread used by the driver to handle interrupts.
-
-config ICM42670_THREAD_STACK_SIZE
-	int "Thread stack size"
-	depends on ICM42670_TRIGGER_OWN_THREAD
-	default 1024
-	help
-	  Stack size of thread used by the driver to handle interrupts.
-
-endif # ICM42670
diff --git a/drivers/sensor/tdk/icm42670/icm42670.c b/drivers/sensor/tdk/icm42670/icm42670.c
deleted file mode 100644
index a2fe604c75d..00000000000
--- a/drivers/sensor/tdk/icm42670/icm42670.c
+++ /dev/null
@@ -1,1090 +0,0 @@
-/*
- * Copyright (c) 2024 TDK Invensense
- * Copyright (c) 2022 Esco Medical ApS
- * Copyright (c) 2020 TDK Invensense
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/kernel.h>
-#include <zephyr/drivers/sensor.h>
-#include <zephyr/init.h>
-#include <zephyr/drivers/gpio.h>
-#include <zephyr/pm/device.h>
-#include <zephyr/sys/byteorder.h>
-#include <zephyr/sys/__assert.h>
-#include <zephyr/drivers/sensor/icm42670.h>
-#include <zephyr/drivers/sensor/tdk_apex.h>
-
-#include "icm42670.h"
-#include "icm42670_trigger.h"
-
-#include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(ICM42670, CONFIG_SENSOR_LOG_LEVEL);
-
-/* Convert DT enum to sensor ODR selection */
-#define ICM42670_CONVERT_ENUM_TO_ODR_POS (4)
-
-/* Maximum bytes to read/write on ICM42670 serial interface */
-#define ICM42670_SERIAL_INTERFACE_MAX_READ  (1024 * 32)
-#define ICM42670_SERIAL_INTERFACE_MAX_WRITE (1024 * 32)
-
-static inline int icm42670_reg_read(const struct device *dev, uint8_t reg, uint8_t *buf,
-				    uint32_t size)
-{
-	const struct icm42670_config *cfg = dev->config;
-
-	return cfg->bus_io->read(&cfg->bus, reg, buf, size);
-}
-
-static inline int inv_io_hal_read_reg(struct inv_imu_serif *serif, uint8_t reg, uint8_t *rbuffer,
-				      uint32_t rlen)
-{
-	return icm42670_reg_read(serif->context, reg, rbuffer, rlen);
-}
-
-static inline int icm42670_reg_write(const struct device *dev, uint8_t reg, const uint8_t *buf,
-				     uint32_t size)
-{
-	const struct icm42670_config *cfg = dev->config;
-
-	return cfg->bus_io->write(&cfg->bus, reg, (uint8_t *)buf, size);
-}
-
-static inline int inv_io_hal_write_reg(struct inv_imu_serif *serif, uint8_t reg,
-				       const uint8_t *wbuffer, uint32_t wlen)
-{
-	return icm42670_reg_write(serif->context, reg, wbuffer, wlen);
-}
-
-void inv_imu_sleep_us(uint32_t us)
-{
-	k_sleep(K_USEC(us));
-}
-
-uint64_t inv_imu_get_time_us(void)
-{
-	/* returns the elapsed time since the system booted, in milliseconds */
-	return k_uptime_get() * 1000;
-}
-
-static uint16_t convert_dt_enum_to_freq(uint8_t val)
-{
-	uint16_t freq;
-
-	switch (val) {
-	case 0:
-		freq = 0;
-		break;
-	case 1:
-		freq = 1600;
-		break;
-	case 2:
-		freq = 800;
-		break;
-	case 3:
-		freq = 400;
-		break;
-	case 4:
-		freq = 200;
-		break;
-	case 5:
-		freq = 100;
-		break;
-	case 6:
-		freq = 50;
-		break;
-	case 7:
-		freq = 25;
-		break;
-	case 8:
-		freq = 12;
-		break;
-	case 9:
-		freq = 6;
-		break;
-	case 10:
-		freq = 3;
-		break;
-	case 11:
-		freq = 1;
-		break;
-	default:
-		freq = 0;
-		break;
-	}
-	return freq;
-}
-
-static uint32_t convert_freq_to_bitfield(uint32_t val, uint16_t *freq)
-{
-	uint32_t odr_bitfield = 0;
-
-	if (val < 3 && val >= 1) {
-		odr_bitfield = ACCEL_CONFIG0_ODR_1_5625_HZ; /*(= GYRO_CONFIG0_ODR_1_5625_HZ )*/
-		*freq = 1;
-	} else if (val < 6 && val >= 3) {
-		odr_bitfield = ACCEL_CONFIG0_ODR_3_125_HZ; /*(= GYRO_CONFIG0_ODR_3_125_HZ )*/
-		*freq = 3;
-	} else if (val < 12 && val >= 6) {
-		odr_bitfield = ACCEL_CONFIG0_ODR_6_25_HZ; /*(= GYRO_CONFIG0_ODR_6_25_HZ )*/
-		*freq = 6;
-	} else if (val < 25 && val >= 12) {
-		odr_bitfield = ACCEL_CONFIG0_ODR_12_5_HZ; /*(= GYRO_CONFIG0_ODR_12_5_HZ )*/
-		*freq = 12;
-	} else if (val < 50 && val >= 25) {
-		odr_bitfield = ACCEL_CONFIG0_ODR_25_HZ; /*(= GYRO_CONFIG0_ODR_25_HZ )*/
-		*freq = 25;
-	} else if (val < 100 && val >= 50) {
-		odr_bitfield = ACCEL_CONFIG0_ODR_50_HZ; /*(GYRO_CONFIG0_ODR_50_HZ)*/
-		*freq = 50;
-	} else if (val < 200 && val >= 100) {
-		odr_bitfield = ACCEL_CONFIG0_ODR_100_HZ; /*(= GYRO_CONFIG0_ODR_100_HZ )*/
-		*freq = 100;
-	} else if (val < 400 && val >= 200) {
-		odr_bitfield = ACCEL_CONFIG0_ODR_200_HZ; /*(= GYRO_CONFIG0_ODR_200_HZ )*/
-		*freq = 200;
-	} else if (val < 800 && val >= 400) {
-		odr_bitfield = ACCEL_CONFIG0_ODR_400_HZ; /*(= GYRO_CONFIG0_ODR_400_HZ )*/
-		*freq = 400;
-	} else if (val < 1600 && val >= 800) {
-		odr_bitfield = ACCEL_CONFIG0_ODR_800_HZ; /*(= GYRO_CONFIG0_ODR_800_HZ )*/
-		*freq = 800;
-	} else if (val == 1600) {
-		odr_bitfield = ACCEL_CONFIG0_ODR_1600_HZ; /*(= GYRO_CONFIG0_ODR_1600_HZ )*/
-		*freq = 1600;
-	}
-	return odr_bitfield;
-}
-
-static uint32_t convert_acc_fs_to_bitfield(uint32_t val, uint8_t *fs)
-{
-	uint32_t bitfield = 0;
-
-	if (val < 4 && val >= 2) {
-		bitfield = ACCEL_CONFIG0_FS_SEL_2g;
-		*fs = 2;
-	} else if (val < 8 && val >= 4) {
-		bitfield = ACCEL_CONFIG0_FS_SEL_4g;
-		*fs = 4;
-	} else if (val < 16 && val >= 8) {
-		bitfield = ACCEL_CONFIG0_FS_SEL_8g;
-		*fs = 8;
-	} else if (val == 16) {
-		bitfield = ACCEL_CONFIG0_FS_SEL_16g;
-		*fs = 16;
-	}
-	return bitfield;
-}
-
-static uint32_t convert_gyr_fs_to_bitfield(uint32_t val, uint16_t *fs)
-{
-	uint32_t bitfield = 0;
-
-	if (val < 500 && val >= 250) {
-		bitfield = GYRO_CONFIG0_FS_SEL_250dps;
-		*fs = 250;
-	} else if (val < 1000 && val >= 500) {
-		bitfield = GYRO_CONFIG0_FS_SEL_500dps;
-		*fs = 500;
-	} else if (val < 2000 && val >= 1000) {
-		bitfield = GYRO_CONFIG0_FS_SEL_1000dps;
-		*fs = 1000;
-	} else if (val == 2000) {
-		bitfield = GYRO_CONFIG0_FS_SEL_2000dps;
-		*fs = 2000;
-	}
-	return bitfield;
-}
-
-static uint32_t convert_ln_bw_to_bitfield(uint32_t val)
-{
-	uint32_t bitfield = 0xFF;
-
-	if (val < 25 && val >= 16) {
-		bitfield = ACCEL_CONFIG1_ACCEL_FILT_BW_16; /* (= GYRO_CONFIG1_GYRO_FILT_BW_16) */
-	} else if (val < 34 && val >= 25) {
-		bitfield = ACCEL_CONFIG1_ACCEL_FILT_BW_25; /* (= GYRO_CONFIG1_GYRO_FILT_BW_25) */
-	} else if (val < 53 && val >= 34) {
-		bitfield = ACCEL_CONFIG1_ACCEL_FILT_BW_34; /* (= GYRO_CONFIG1_GYRO_FILT_BW_34) */
-	} else if (val < 73 && val >= 53) {
-		bitfield = ACCEL_CONFIG1_ACCEL_FILT_BW_53; /* (= GYRO_CONFIG1_GYRO_FILT_BW_53) */
-	} else if (val < 121 && val >= 73) {
-		bitfield = ACCEL_CONFIG1_ACCEL_FILT_BW_73; /* (= GYRO_CONFIG1_GYRO_FILT_BW_73) */
-	} else if (val < 180 && val >= 121) {
-		bitfield = ACCEL_CONFIG1_ACCEL_FILT_BW_121; /* (= GYRO_CONFIG1_GYRO_FILT_BW_121) */
-	} else if (val == 180) {
-		bitfield = ACCEL_CONFIG1_ACCEL_FILT_BW_180; /* (= GYRO_CONFIG1_GYRO_FILT_BW_180) */
-	} else if (val == 0) {
-		bitfield = ACCEL_CONFIG1_ACCEL_FILT_BW_NO_FILTER;
-		/*(= GYRO_CONFIG1_GYRO_FILT_BW_NO_FILTER)*/
-	}
-	return bitfield;
-}
-
-static uint32_t convert_lp_avg_to_bitfield(uint32_t val)
-{
-	uint32_t bitfield = 0xFF;
-
-	if (val < 4 && val >= 2) {
-		bitfield = ACCEL_CONFIG1_ACCEL_FILT_AVG_2;
-	} else if (val < 8 && val >= 4) {
-		bitfield = ACCEL_CONFIG1_ACCEL_FILT_AVG_4;
-	} else if (val < 16 && val >= 8) {
-		bitfield = ACCEL_CONFIG1_ACCEL_FILT_AVG_8;
-	} else if (val < 32 && val >= 16) {
-		bitfield = ACCEL_CONFIG1_ACCEL_FILT_AVG_16;
-	} else if (val < 64 && val >= 32) {
-		bitfield = ACCEL_CONFIG1_ACCEL_FILT_AVG_32;
-	} else if (val == 64) {
-		bitfield = ACCEL_CONFIG1_ACCEL_FILT_AVG_64;
-	}
-	return bitfield;
-}
-
-static uint8_t convert_bitfield_to_acc_fs(uint8_t bitfield)
-{
-	uint8_t acc_fs = 0;
-
-	if (bitfield == ACCEL_CONFIG0_FS_SEL_2g) {
-		acc_fs = 2;
-	} else if (bitfield == ACCEL_CONFIG0_FS_SEL_4g) {
-		acc_fs = 4;
-	} else if (bitfield == ACCEL_CONFIG0_FS_SEL_8g) {
-		acc_fs = 8;
-	} else if (bitfield == ACCEL_CONFIG0_FS_SEL_16g) {
-		acc_fs = 16;
-	}
-	return acc_fs;
-}
-
-static uint16_t convert_bitfield_to_gyr_fs(uint8_t bitfield)
-{
-	uint16_t gyr_fs = 0;
-
-	if (bitfield == GYRO_CONFIG0_FS_SEL_250dps) {
-		gyr_fs = 250;
-	} else if (bitfield == GYRO_CONFIG0_FS_SEL_500dps) {
-		gyr_fs = 500;
-	} else if (bitfield == GYRO_CONFIG0_FS_SEL_1000dps) {
-		gyr_fs = 1000;
-	} else if (bitfield == GYRO_CONFIG0_FS_SEL_2000dps) {
-		gyr_fs = 2000;
-	}
-	return gyr_fs;
-}
-
-static int icm42670_set_accel_power_mode(struct icm42670_data *drv_data,
-					 const struct sensor_value *val)
-{
-	if ((val->val1 == ICM42670_LOW_POWER_MODE) &&
-	    (drv_data->accel_pwr_mode != ICM42670_LOW_POWER_MODE)) {
-		if (drv_data->accel_hz != 0) {
-			if (drv_data->accel_hz <= 400) {
-				inv_imu_enable_accel_low_power_mode(&drv_data->driver);
-			} else {
-				LOG_ERR("Not supported ATTR value");
-				return -EINVAL;
-			}
-		}
-		drv_data->accel_pwr_mode = val->val1;
-	} else if ((val->val1 == ICM42670_LOW_NOISE_MODE) &&
-		   (drv_data->accel_pwr_mode != ICM42670_LOW_NOISE_MODE)) {
-		if (drv_data->accel_hz != 0) {
-			if (drv_data->accel_hz >= 12) {
-				inv_imu_enable_accel_low_noise_mode(&drv_data->driver);
-			} else {
-				LOG_ERR("Not supported ATTR value");
-				return -EINVAL;
-			}
-		}
-		drv_data->accel_pwr_mode = val->val1;
-	} else {
-		LOG_ERR("Not supported ATTR value");
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int icm42670_set_accel_odr(struct icm42670_data *drv_data, const struct sensor_value *val)
-{
-	if (val->val1 <= 1600 && val->val1 >= 1) {
-		if (drv_data->accel_hz == 0) {
-			inv_imu_set_accel_frequency(
-				&drv_data->driver,
-				convert_freq_to_bitfield(val->val1, &drv_data->accel_hz));
-			if (drv_data->accel_pwr_mode == ICM42670_LOW_POWER_MODE) {
-				inv_imu_enable_accel_low_power_mode(&drv_data->driver);
-			} else if (drv_data->accel_pwr_mode == ICM42670_LOW_NOISE_MODE) {
-				inv_imu_enable_accel_low_noise_mode(&drv_data->driver);
-			}
-		} else {
-			inv_imu_set_accel_frequency(
-				&drv_data->driver,
-				convert_freq_to_bitfield(val->val1, &drv_data->accel_hz));
-		}
-	} else if (val->val1 == 0) {
-		inv_imu_disable_accel(&drv_data->driver);
-		drv_data->accel_hz = val->val1;
-	} else {
-		LOG_ERR("Incorrect sampling value");
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int icm42670_set_accel_fs(struct icm42670_data *drv_data, const struct sensor_value *val)
-{
-	if (val->val1 > 16 || val->val1 < 2) {
-		LOG_ERR("Incorrect fullscale value");
-		return -EINVAL;
-	}
-	inv_imu_set_accel_fsr(&drv_data->driver,
-			      convert_acc_fs_to_bitfield(val->val1, &drv_data->accel_fs));
-	LOG_DBG("Set accel full scale to: %d G", drv_data->accel_fs);
-	return 0;
-}
-
-static int icm42670_accel_config(struct icm42670_data *drv_data, enum sensor_attribute attr,
-				 const struct sensor_value *val)
-{
-	if (attr == SENSOR_ATTR_CONFIGURATION) {
-		icm42670_set_accel_power_mode(drv_data, val);
-
-	} else if (attr == SENSOR_ATTR_SAMPLING_FREQUENCY) {
-		icm42670_set_accel_odr(drv_data, val);
-
-	} else if (attr == SENSOR_ATTR_FULL_SCALE) {
-		icm42670_set_accel_fs(drv_data, val);
-
-	} else if ((enum sensor_attribute_icm42670)attr == SENSOR_ATTR_BW_FILTER_LPF) {
-		if (val->val1 > 180) {
-			LOG_ERR("Incorrect low pass filter bandwidth value");
-			return -EINVAL;
-		}
-		inv_imu_set_accel_ln_bw(&drv_data->driver, convert_ln_bw_to_bitfield(val->val1));
-
-	} else if ((enum sensor_attribute_icm42670)attr == SENSOR_ATTR_AVERAGING) {
-		if (val->val1 > 64 || val->val1 < 2) {
-			LOG_ERR("Incorrect averaging filter value");
-			return -EINVAL;
-		}
-		inv_imu_set_accel_lp_avg(&drv_data->driver, convert_lp_avg_to_bitfield(val->val1));
-	} else {
-		LOG_ERR("Unsupported attribute");
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int icm42670_set_gyro_odr(struct icm42670_data *drv_data, const struct sensor_value *val)
-{
-	if (val->val1 <= 1600 && val->val1 > 12) {
-		if (drv_data->gyro_hz == 0) {
-			inv_imu_set_gyro_frequency(
-				&drv_data->driver,
-				convert_freq_to_bitfield(val->val1, &drv_data->gyro_hz));
-			inv_imu_enable_gyro_low_noise_mode(&drv_data->driver);
-		} else {
-			inv_imu_set_gyro_frequency(
-				&drv_data->driver,
-				convert_freq_to_bitfield(val->val1, &drv_data->gyro_hz));
-		}
-	} else if (val->val1 == 0) {
-		inv_imu_disable_gyro(&drv_data->driver);
-		drv_data->gyro_hz = val->val1;
-	} else {
-		LOG_ERR("Incorrect sampling value");
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int icm42670_set_gyro_fs(struct icm42670_data *drv_data, const struct sensor_value *val)
-{
-	if (val->val1 > 2000 || val->val1 < 250) {
-		LOG_ERR("Incorrect fullscale value");
-		return -EINVAL;
-	}
-	inv_imu_set_gyro_fsr(&drv_data->driver,
-			     convert_gyr_fs_to_bitfield(val->val1, &drv_data->gyro_fs));
-	LOG_DBG("Set gyro fullscale to: %d dps", drv_data->gyro_fs);
-	return 0;
-}
-
-static int icm42670_gyro_config(struct icm42670_data *drv_data, enum sensor_attribute attr,
-				const struct sensor_value *val)
-{
-	if (attr == SENSOR_ATTR_SAMPLING_FREQUENCY) {
-		icm42670_set_gyro_odr(drv_data, val);
-
-	} else if (attr == SENSOR_ATTR_FULL_SCALE) {
-		icm42670_set_gyro_fs(drv_data, val);
-
-	} else if ((enum sensor_attribute_icm42670)attr == SENSOR_ATTR_BW_FILTER_LPF) {
-		if (val->val1 > 180) {
-			LOG_ERR("Incorrect low pass filter bandwidth value");
-			return -EINVAL;
-		}
-		inv_imu_set_gyro_ln_bw(&drv_data->driver, convert_ln_bw_to_bitfield(val->val1));
-
-	} else {
-		LOG_ERR("Unsupported attribute");
-		return -EINVAL;
-	}
-	return 0;
-}
-
-static int icm42670_sensor_init(const struct device *dev)
-{
-	struct icm42670_data *data = dev->data;
-	int err = 0;
-
-	/* Initialize serial interface and device */
-	data->serif.context = (struct device *)dev;
-	data->serif.read_reg = inv_io_hal_read_reg;
-	data->serif.write_reg = inv_io_hal_write_reg;
-	data->serif.max_read = ICM42670_SERIAL_INTERFACE_MAX_READ;
-	data->serif.max_write = ICM42670_SERIAL_INTERFACE_MAX_WRITE;
-#if CONFIG_SPI
-	data->serif.serif_type = UI_SPI4;
-#endif
-#if CONFIG_I2C
-	data->serif.serif_type = UI_I2C;
-#endif
-	err = inv_imu_init(&data->driver, &data->serif, NULL);
-	if (err < 0) {
-		LOG_ERR("Init failed: %d", err);
-		return err;
-	}
-
-	err = inv_imu_get_who_am_i(&data->driver, &data->chip_id);
-	if (err < 0) {
-		LOG_ERR("ID read failed: %d", err);
-		return err;
-	}
-
-	if (data->chip_id != data->imu_whoami) {
-		LOG_ERR("invalid WHO_AM_I value, was 0x%x but expected 0x%x for %s", data->chip_id,
-			data->imu_whoami, data->imu_name);
-		return -ENOTSUP;
-	}
-
-	LOG_DBG("\"%s\" %s OK", dev->name, data->imu_name);
-	return 0;
-}
-
-static int icm42670_turn_on_sensor(const struct device *dev)
-{
-	struct icm42670_data *data = dev->data;
-	const struct icm42670_config *cfg = dev->config;
-	int err = 0;
-
-	err = inv_imu_set_accel_fsr(&data->driver,
-				    (cfg->accel_fs << ACCEL_CONFIG0_ACCEL_UI_FS_SEL_POS));
-	data->accel_fs =
-		convert_bitfield_to_acc_fs((cfg->accel_fs << ACCEL_CONFIG0_ACCEL_UI_FS_SEL_POS));
-	if ((err < 0) || (data->accel_fs == 0)) {
-		LOG_ERR("Failed to configure accel FSR");
-		return -EIO;
-	}
-	LOG_DBG("Set accel full scale to: %d G", data->accel_fs);
-
-	err = inv_imu_set_gyro_fsr(&data->driver,
-				   (cfg->gyro_fs << GYRO_CONFIG0_GYRO_UI_FS_SEL_POS));
-	data->gyro_fs =
-		convert_bitfield_to_gyr_fs((cfg->gyro_fs << GYRO_CONFIG0_GYRO_UI_FS_SEL_POS));
-	if ((err < 0) || (data->gyro_fs == 0)) {
-		LOG_ERR("Failed to configure gyro FSR");
-		return -EIO;
-	}
-	LOG_DBG("Set gyro full scale to: %d dps", data->gyro_fs);
-
-	err = inv_imu_set_accel_lp_avg(&data->driver,
-				       (cfg->accel_avg << ACCEL_CONFIG1_ACCEL_UI_AVG_POS));
-	err |= inv_imu_set_accel_ln_bw(&data->driver,
-				       (cfg->accel_filt_bw << ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS));
-	err |= inv_imu_set_gyro_ln_bw(&data->driver,
-				      (cfg->gyro_filt_bw << GYRO_CONFIG1_GYRO_UI_FILT_BW_POS));
-	if (err < 0) {
-		LOG_ERR("Failed to configure filtering.");
-		return -EIO;
-	}
-
-	if (cfg->accel_hz != 0) {
-		err |= inv_imu_set_accel_frequency(
-			&data->driver, cfg->accel_hz + ICM42670_CONVERT_ENUM_TO_ODR_POS);
-		if ((cfg->accel_pwr_mode == ICM42670_LOW_NOISE_MODE) &&
-		    (convert_dt_enum_to_freq(cfg->accel_hz) >= 12)) {
-			err |= inv_imu_enable_accel_low_noise_mode(&data->driver);
-		} else if ((cfg->accel_pwr_mode == ICM42670_LOW_POWER_MODE) &&
-			   (convert_dt_enum_to_freq(cfg->accel_hz) <= 400)) {
-			err |= inv_imu_enable_accel_low_power_mode(&data->driver);
-		} else {
-			LOG_ERR("Not supported power mode value");
-		}
-	}
-	if (cfg->gyro_hz != 0) {
-		err |= inv_imu_set_gyro_frequency(&data->driver,
-						  cfg->gyro_hz + ICM42670_CONVERT_ENUM_TO_ODR_POS);
-		err |= inv_imu_enable_gyro_low_noise_mode(&data->driver);
-	}
-
-	if (err < 0) {
-		LOG_ERR("Failed to configure ODR.");
-		return -EIO;
-	}
-
-	data->accel_pwr_mode = cfg->accel_pwr_mode;
-	data->accel_hz = convert_dt_enum_to_freq(cfg->accel_hz);
-	data->gyro_hz = convert_dt_enum_to_freq(cfg->gyro_hz);
-
-	/*
-	 * Accelerometer sensor need at least 10ms startup time
-	 * Gyroscope sensor need at least 30ms startup time
-	 */
-	k_msleep(100);
-
-	return 0;
-}
-
-static void icm42670_convert_accel(struct sensor_value *val, int16_t raw_val, uint16_t fs)
-{
-	int64_t conv_val;
-
-	/* 16 bit accelerometer. 2^15 bits represent the range in G */
-	/* see datasheet section 3.2 for details */
-	conv_val = (int64_t)raw_val * SENSOR_G * fs / INT16_MAX;
-
-	val->val1 = conv_val / 1000000;
-	val->val2 = conv_val % 1000000;
-}
-
-static void icm42670_convert_gyro(struct sensor_value *val, int16_t raw_val, uint16_t fs)
-{
-	int64_t conv_val;
-
-	/* 16 bit gyroscope. 2^15 bits represent the range in degrees/s */
-	/* see datasheet section 3.1 for details */
-	conv_val = ((int64_t)raw_val * fs * SENSOR_PI) / (INT16_MAX * 180U);
-
-	val->val1 = conv_val / 1000000;
-	val->val2 = conv_val % 1000000;
-}
-
-static void icm42670_convert_temp(struct sensor_value *val, int16_t raw_val)
-{
-	int64_t conv_val;
-
-	/* see datasheet section 15.9 for details */
-	conv_val = 25 * 1000000 + ((int64_t)raw_val * 1000000 / 2);
-	val->val1 = conv_val / 1000000;
-	val->val2 = conv_val % 1000000;
-}
-
-static int icm42670_channel_get(const struct device *dev, enum sensor_channel chan,
-				struct sensor_value *val)
-{
-	int res = 0;
-	struct icm42670_data *data = dev->data;
-#ifdef CONFIG_TDK_APEX
-	const struct icm42670_config *cfg = dev->config;
-#endif
-
-	icm42670_lock(dev);
-
-	if (chan == SENSOR_CHAN_ACCEL_XYZ) {
-		icm42670_convert_accel(&val[0], data->accel_x, data->accel_fs);
-		icm42670_convert_accel(&val[1], data->accel_y, data->accel_fs);
-		icm42670_convert_accel(&val[2], data->accel_z, data->accel_fs);
-	} else if (chan == SENSOR_CHAN_ACCEL_X) {
-		icm42670_convert_accel(val, data->accel_x, data->accel_fs);
-	} else if (chan == SENSOR_CHAN_ACCEL_Y) {
-		icm42670_convert_accel(val, data->accel_y, data->accel_fs);
-	} else if (chan == SENSOR_CHAN_ACCEL_Z) {
-		icm42670_convert_accel(val, data->accel_z, data->accel_fs);
-	} else if (chan == SENSOR_CHAN_GYRO_XYZ) {
-		icm42670_convert_gyro(&val[0], data->gyro_x, data->gyro_fs);
-		icm42670_convert_gyro(&val[1], data->gyro_y, data->gyro_fs);
-		icm42670_convert_gyro(&val[2], data->gyro_z, data->gyro_fs);
-	} else if (chan == SENSOR_CHAN_GYRO_X) {
-		icm42670_convert_gyro(val, data->gyro_x, data->gyro_fs);
-	} else if (chan == SENSOR_CHAN_GYRO_Y) {
-		icm42670_convert_gyro(val, data->gyro_y, data->gyro_fs);
-	} else if (chan == SENSOR_CHAN_GYRO_Z) {
-		icm42670_convert_gyro(val, data->gyro_z, data->gyro_fs);
-	} else if (chan == SENSOR_CHAN_DIE_TEMP) {
-		icm42670_convert_temp(val, data->temp);
-#ifdef CONFIG_TDK_APEX
-	} else if ((enum sensor_channel_tdk_apex)chan == SENSOR_CHAN_APEX_MOTION) {
-		if (cfg->apex == TDK_APEX_PEDOMETER) {
-			val[0].val1 = data->pedometer_cnt;
-			val[1].val1 = data->pedometer_activity;
-			icm42670_apex_pedometer_cadence_convert(&val[2], data->pedometer_cadence,
-								data->dmp_odr_hz);
-		} else if (cfg->apex == TDK_APEX_WOM) {
-			val[0].val1 = (data->apex_status & ICM42670_APEX_STATUS_MASK_WOM_X) ? 1 : 0;
-			val[1].val1 = (data->apex_status & ICM42670_APEX_STATUS_MASK_WOM_Y) ? 1 : 0;
-			val[2].val1 = (data->apex_status & ICM42670_APEX_STATUS_MASK_WOM_Z) ? 1 : 0;
-		} else if ((cfg->apex == TDK_APEX_TILT) || (cfg->apex == TDK_APEX_SMD)) {
-			val[0].val1 = data->apex_status;
-		}
-#endif
-	} else {
-		res = -ENOTSUP;
-	}
-
-	icm42670_unlock(dev);
-
-	return res;
-}
-
-#ifdef CONFIG_ICM42670_TRIGGER
-static int icm42670_fetch_from_fifo(const struct device *dev)
-{
-	struct icm42670_data *data = dev->data;
-	int status = 0;
-	uint8_t int_status;
-	uint16_t packet_size = FIFO_HEADER_SIZE + FIFO_ACCEL_DATA_SIZE + FIFO_GYRO_DATA_SIZE +
-			       FIFO_TEMP_DATA_SIZE + FIFO_TS_FSYNC_SIZE;
-	uint16_t fifo_idx = 0;
-
-	/* Ensure data ready status bit is set */
-	status |= inv_imu_read_reg(&data->driver, INT_STATUS, 1, &int_status);
-	if (status != 0) {
-		return status;
-	}
-
-	if ((int_status & INT_STATUS_FIFO_THS_INT_MASK) ||
-	    (int_status & INT_STATUS_FIFO_FULL_INT_MASK)) {
-		uint16_t packet_count;
-
-		/* Make sure RCOSC is enabled to guarrantee FIFO read */
-		status |= inv_imu_switch_on_mclk(&data->driver);
-
-		/* Read FIFO frame count */
-		status |= inv_imu_get_frame_count(&data->driver, &packet_count);
-
-		/* Check for error */
-		if (status != 0) {
-			status |= inv_imu_switch_off_mclk(&data->driver);
-			return status;
-		}
-
-		/* Read FIFO data */
-		status |= inv_imu_read_reg(&data->driver, FIFO_DATA, packet_size * packet_count,
-					   (uint8_t *)&data->driver.fifo_data);
-
-		/* Check for error */
-		if (status != 0) {
-			status |= inv_imu_reset_fifo(&data->driver);
-			status |= inv_imu_switch_off_mclk(&data->driver);
-			return status;
-		}
-
-		for (uint16_t i = 0; i < packet_count; i++) {
-			inv_imu_sensor_event_t event;
-
-			status |= inv_imu_decode_fifo_frame(
-				&data->driver, &data->driver.fifo_data[fifo_idx], &event);
-			fifo_idx += packet_size;
-
-			/* Check for error */
-			if (status != 0) {
-				status |= inv_imu_reset_fifo(&data->driver);
-				status |= inv_imu_switch_off_mclk(&data->driver);
-				return status;
-			}
-
-			if (event.sensor_mask & (1 << INV_SENSOR_ACCEL)) {
-				data->accel_x = event.accel[0];
-				data->accel_y = event.accel[1];
-				data->accel_z = event.accel[2];
-			}
-			if (event.sensor_mask & (1 << INV_SENSOR_GYRO)) {
-				data->gyro_x = event.gyro[0];
-				data->gyro_y = event.gyro[1];
-				data->gyro_z = event.gyro[2];
-			}
-			if (event.sensor_mask & (1 << INV_SENSOR_TEMPERATURE)) {
-				data->temp = event.temperature;
-			}
-			/*
-			 * TODO use the sensor streaming interface with RTIO to handle multiple
-			 * samples in FIFO
-			 */
-
-		} /* end of FIFO read for loop */
-
-		status |= inv_imu_switch_off_mclk(&data->driver);
-		if (status < 0) {
-			return status;
-		}
-	} /*else: FIFO threshold was not reached and FIFO was not full */
-
-	return 0;
-}
-#endif
-
-#ifndef CONFIG_ICM42670_TRIGGER
-static int icm42670_sample_fetch_accel(const struct device *dev)
-{
-	struct icm42670_data *data = dev->data;
-	uint8_t buffer[ACCEL_DATA_SIZE];
-
-	int res = inv_imu_read_reg(&data->driver, ACCEL_DATA_X1, ACCEL_DATA_SIZE, buffer);
-
-	if (res) {
-		return res;
-	}
-
-	data->accel_x = (int16_t)sys_get_be16(&buffer[0]);
-	data->accel_y = (int16_t)sys_get_be16(&buffer[2]);
-	data->accel_z = (int16_t)sys_get_be16(&buffer[4]);
-
-	return 0;
-}
-
-static int icm42670_sample_fetch_gyro(const struct device *dev)
-{
-	struct icm42670_data *data = dev->data;
-	uint8_t buffer[GYRO_DATA_SIZE];
-
-	int res = inv_imu_read_reg(&data->driver, GYRO_DATA_X1, GYRO_DATA_SIZE, buffer);
-
-	if (res) {
-		return res;
-	}
-
-	data->gyro_x = (int16_t)sys_get_be16(&buffer[0]);
-	data->gyro_y = (int16_t)sys_get_be16(&buffer[2]);
-	data->gyro_z = (int16_t)sys_get_be16(&buffer[4]);
-
-	return 0;
-}
-
-static int icm42670_sample_fetch_temp(const struct device *dev)
-{
-	struct icm42670_data *data = dev->data;
-	uint8_t buffer[TEMP_DATA_SIZE];
-
-	int res = inv_imu_read_reg(&data->driver, TEMP_DATA1, TEMP_DATA_SIZE, buffer);
-
-	if (res) {
-		return res;
-	}
-
-	data->temp = (int16_t)sys_get_be16(&buffer[0]);
-
-	return 0;
-}
-
-static int icm42670_fetch_from_registers(const struct device *dev, enum sensor_channel chan)
-{
-	struct icm42670_data *data = dev->data;
-	int res = 0;
-	uint8_t int_status;
-
-	LOG_ERR("Fetch from reg");
-
-	icm42670_lock(dev);
-
-	/* Ensure data ready status bit is set */
-	int err = inv_imu_read_reg(&data->driver, INT_STATUS_DRDY, 1, &int_status);
-
-	if (int_status & INT_STATUS_DRDY_DATA_RDY_INT_MASK) {
-		switch (chan) {
-		case SENSOR_CHAN_ALL:
-			err |= icm42670_sample_fetch_accel(dev);
-			err |= icm42670_sample_fetch_gyro(dev);
-			err |= icm42670_sample_fetch_temp(dev);
-			break;
-		case SENSOR_CHAN_ACCEL_XYZ:
-		case SENSOR_CHAN_ACCEL_X:
-		case SENSOR_CHAN_ACCEL_Y:
-		case SENSOR_CHAN_ACCEL_Z:
-			err |= icm42670_sample_fetch_accel(dev);
-			break;
-		case SENSOR_CHAN_GYRO_XYZ:
-		case SENSOR_CHAN_GYRO_X:
-		case SENSOR_CHAN_GYRO_Y:
-		case SENSOR_CHAN_GYRO_Z:
-			err |= icm42670_sample_fetch_gyro(dev);
-			break;
-		case SENSOR_CHAN_DIE_TEMP:
-			err |= icm42670_sample_fetch_temp(dev);
-			break;
-		default:
-			res = -ENOTSUP;
-			break;
-		}
-	}
-
-	icm42670_unlock(dev);
-
-	if (err < 0) {
-		res = -EIO;
-	}
-	return res;
-}
-#endif
-
-static int icm42670_sample_fetch(const struct device *dev, enum sensor_channel chan)
-{
-	int status = -ENOTSUP;
-
-	icm42670_lock(dev);
-
-#ifdef CONFIG_TDK_APEX
-	if ((enum sensor_channel_tdk_apex)chan == SENSOR_CHAN_APEX_MOTION) {
-		status = icm42670_apex_fetch_from_dmp(dev);
-	}
-#endif
-
-	if ((chan == SENSOR_CHAN_ALL) || (chan == SENSOR_CHAN_ACCEL_XYZ) ||
-	    (chan == SENSOR_CHAN_ACCEL_X) || (chan == SENSOR_CHAN_ACCEL_Y) ||
-	    (chan == SENSOR_CHAN_ACCEL_Z) || (chan == SENSOR_CHAN_GYRO_XYZ) ||
-	    (chan == SENSOR_CHAN_GYRO_X) || (chan == SENSOR_CHAN_GYRO_Y) ||
-	    (chan == SENSOR_CHAN_GYRO_Z) || (chan == SENSOR_CHAN_DIE_TEMP)) {
-#ifdef CONFIG_ICM42670_TRIGGER
-		status = icm42670_fetch_from_fifo(dev);
-#else
-		status = icm42670_fetch_from_registers(dev, chan);
-#endif
-	}
-
-	icm42670_unlock(dev);
-	return status;
-}
-
-static int icm42670_attr_set(const struct device *dev, enum sensor_channel chan,
-			     enum sensor_attribute attr, const struct sensor_value *val)
-{
-	struct icm42670_data *drv_data = dev->data;
-
-	__ASSERT_NO_MSG(val != NULL);
-
-	icm42670_lock(dev);
-
-	if ((enum sensor_channel_tdk_apex)chan == SENSOR_CHAN_APEX_MOTION) {
-		if (attr == SENSOR_ATTR_CONFIGURATION) {
-#ifdef CONFIG_TDK_APEX
-			if (val->val1 == TDK_APEX_PEDOMETER) {
-				icm42670_apex_enable(&drv_data->driver);
-				icm42670_apex_enable_pedometer(dev, &drv_data->driver);
-			} else if (val->val1 == TDK_APEX_TILT) {
-				icm42670_apex_enable(&drv_data->driver);
-				icm42670_apex_enable_tilt(&drv_data->driver);
-			} else if (val->val1 == TDK_APEX_SMD) {
-				icm42670_apex_enable(&drv_data->driver);
-				icm42670_apex_enable_smd(&drv_data->driver);
-			} else if (val->val1 == TDK_APEX_WOM) {
-				icm42670_apex_enable_wom(&drv_data->driver);
-			} else {
-				LOG_ERR("Not supported ATTR value");
-			}
-#endif
-		} else {
-			LOG_ERR("Not supported ATTR");
-			return -EINVAL;
-		}
-	} else if ((chan == SENSOR_CHAN_ACCEL_XYZ) || (chan == SENSOR_CHAN_ACCEL_X) ||
-		   (chan == SENSOR_CHAN_ACCEL_Y) || (chan == SENSOR_CHAN_ACCEL_Z)) {
-		icm42670_accel_config(drv_data, attr, val);
-
-	} else if ((chan == SENSOR_CHAN_GYRO_XYZ) || (chan == SENSOR_CHAN_GYRO_X) ||
-		   (chan == SENSOR_CHAN_GYRO_Y) || (chan == SENSOR_CHAN_GYRO_Z)) {
-		icm42670_gyro_config(drv_data, attr, val);
-
-	} else {
-		LOG_ERR("Unsupported channel");
-		(void)drv_data;
-		return -EINVAL;
-	}
-
-	icm42670_unlock(dev);
-
-	return 0;
-}
-
-static int icm42670_attr_get(const struct device *dev, enum sensor_channel chan,
-			     enum sensor_attribute attr, struct sensor_value *val)
-{
-	const struct icm42670_data *data = dev->data;
-	const struct icm42670_config *cfg = dev->config;
-	int res = 0;
-
-	__ASSERT_NO_MSG(val != NULL);
-
-	icm42670_lock(dev);
-
-	switch (chan) {
-	case SENSOR_CHAN_ACCEL_X:
-	case SENSOR_CHAN_ACCEL_Y:
-	case SENSOR_CHAN_ACCEL_Z:
-	case SENSOR_CHAN_ACCEL_XYZ:
-		if (attr == SENSOR_ATTR_SAMPLING_FREQUENCY) {
-			val->val1 = data->accel_hz;
-		} else if (attr == SENSOR_ATTR_FULL_SCALE) {
-			val->val1 = data->accel_fs;
-		} else {
-			LOG_ERR("Unsupported attribute");
-			res = -EINVAL;
-		}
-		break;
-
-	case SENSOR_CHAN_GYRO_X:
-	case SENSOR_CHAN_GYRO_Y:
-	case SENSOR_CHAN_GYRO_Z:
-	case SENSOR_CHAN_GYRO_XYZ:
-		if (attr == SENSOR_ATTR_SAMPLING_FREQUENCY) {
-			val->val1 = data->gyro_hz;
-		} else if (attr == SENSOR_ATTR_FULL_SCALE) {
-			val->val1 = data->gyro_fs;
-		} else {
-			LOG_ERR("Unsupported attribute");
-			res = -EINVAL;
-		}
-		break;
-
-	case SENSOR_CHAN_APEX_MOTION:
-		if (attr == SENSOR_ATTR_CONFIGURATION) {
-			val->val1 = cfg->apex;
-		}
-		break;
-
-	default:
-		LOG_ERR("Unsupported channel");
-		res = -EINVAL;
-		break;
-	}
-
-	icm42670_unlock(dev);
-
-	return res;
-}
-
-static inline int icm42670_bus_check(const struct device *dev)
-{
-	const struct icm42670_config *cfg = dev->config;
-
-	return cfg->bus_io->check(&cfg->bus);
-}
-
-static int icm42670_init(const struct device *dev)
-{
-	struct icm42670_data *data = dev->data;
-	int res = 0;
-
-	if (icm42670_bus_check(dev) < 0) {
-		LOG_ERR("bus check failed");
-		return -ENODEV;
-	}
-
-	data->accel_x = 0;
-	data->accel_y = 0;
-	data->accel_z = 0;
-	data->gyro_x = 0;
-	data->gyro_y = 0;
-	data->gyro_z = 0;
-	data->temp = 0;
-
-	if (icm42670_sensor_init(dev)) {
-		LOG_ERR("could not initialize sensor");
-		return -EIO;
-	}
-
-#ifdef CONFIG_ICM42670_TRIGGER
-	res |= icm42670_trigger_enable_interrupt(dev);
-	res |= icm42670_trigger_init(dev);
-	if (res < 0) {
-		LOG_ERR("Failed to initialize interrupt.");
-		return res;
-	}
-#endif
-
-	res |= icm42670_turn_on_sensor(dev);
-
-	return res;
-}
-
-#ifndef CONFIG_ICM42670_TRIGGER
-
-void icm42670_lock(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-}
-
-void icm42670_unlock(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-}
-
-#endif
-
-static DEVICE_API(sensor, icm42670_driver_api) = {
-#ifdef CONFIG_ICM42670_TRIGGER
-	.trigger_set = icm42670_trigger_set,
-#endif
-	.sample_fetch = icm42670_sample_fetch,
-	.channel_get = icm42670_channel_get,
-	.attr_set = icm42670_attr_set,
-	.attr_get = icm42670_attr_get,
-};
-
-/* device defaults to spi mode 0/3 support */
-#define ICM42670_SPI_CFG (SPI_WORD_SET(8) | SPI_TRANSFER_MSB | SPI_MODE_CPOL | SPI_MODE_CPHA)
-
-/* Initializes a common struct icm42670_config */
-#define ICM42670_CONFIG_COMMON(inst)                                                               \
-	IF_ENABLED(CONFIG_ICM42670_TRIGGER,	\
-				(.gpio_int = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, {0}),))     \
-				    .accel_fs = DT_INST_ENUM_IDX(inst, accel_fs),                  \
-				    .accel_hz = DT_INST_ENUM_IDX(inst, accel_hz),                  \
-				    .accel_avg = DT_INST_ENUM_IDX(inst, accel_avg),                \
-				    .accel_filt_bw = DT_INST_ENUM_IDX(inst, accel_filt_bw_hz),     \
-				    .gyro_fs = DT_INST_ENUM_IDX(inst, gyro_fs),                    \
-				    .gyro_hz = DT_INST_ENUM_IDX(inst, gyro_hz),                    \
-				    .gyro_filt_bw = DT_INST_ENUM_IDX(inst, gyro_filt_bw_hz),       \
-				    .accel_pwr_mode = DT_INST_ENUM_IDX(inst, power_mode),          \
-				    .apex = DT_INST_ENUM_IDX(inst, apex),
-
-/* Initializes the bus members for an instance on a SPI bus. */
-#define ICM42670_CONFIG_SPI(inst)                                                                  \
-	{.bus.spi = SPI_DT_SPEC_INST_GET(inst, ICM42670_SPI_CFG, 0),                               \
-	 .bus_io = &icm42670_bus_io_spi,                                                           \
-	 ICM42670_CONFIG_COMMON(inst)}
-
-/* Initializes the bus members for an instance on an I2C bus. */
-#define ICM42670_CONFIG_I2C(inst)                                                                  \
-	{.bus.i2c = I2C_DT_SPEC_INST_GET(inst),                                                    \
-	 .bus_io = &icm42670_bus_io_i2c,                                                           \
-	 ICM42670_CONFIG_COMMON(inst)}
-
-/*
- * Main instantiation macro, which selects the correct bus-specific
- * instantiation macros for the instance.
- */
-#define ICM42670_DEFINE(inst, name, whoami)                                                        \
-	static struct icm42670_data icm42670_data_##inst = {                                       \
-		.imu_name = name,                                                                  \
-		.imu_whoami = whoami,                                                              \
-	};                                                                                         \
-	static const struct icm42670_config icm42670_config_##inst = \
-			COND_CODE_1(DT_INST_ON_BUS(inst, spi),	\
-			(ICM42670_CONFIG_SPI(inst)),	\
-			(ICM42670_CONFIG_I2C(inst)));             \
-	SENSOR_DEVICE_DT_INST_DEFINE(inst, icm42670_init, NULL, &icm42670_data_##inst,             \
-				     &icm42670_config_##inst, POST_KERNEL,                         \
-				     CONFIG_SENSOR_INIT_PRIORITY, &icm42670_driver_api);
-
-#define DT_DRV_COMPAT invensense_icm42670p
-#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
-DT_INST_FOREACH_STATUS_OKAY_VARGS(ICM42670_DEFINE, INV_ICM42670P_STRING_ID, INV_ICM42670P_WHOAMI);
-#endif
-#undef DT_DRV_COMPAT
-
-#define DT_DRV_COMPAT invensense_icm42670s
-#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
-DT_INST_FOREACH_STATUS_OKAY_VARGS(ICM42670_DEFINE, INV_ICM42670S_STRING_ID, INV_ICM42670S_WHOAMI);
-#endif
diff --git a/drivers/sensor/tdk/icm42670/icm42670.h b/drivers/sensor/tdk/icm42670/icm42670.h
deleted file mode 100644
index c029d7c6f91..00000000000
--- a/drivers/sensor/tdk/icm42670/icm42670.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Copyright (c) 2024 TDK Invensense
- * Copyright (c) 2022 Esco Medical ApS
- * Copyright (c) 2020 TDK Invensense
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_DRIVERS_SENSOR_ICM42670_H_
-#define ZEPHYR_DRIVERS_SENSOR_ICM42670_H_
-
-#include <zephyr/drivers/gpio.h>
-#include <zephyr/drivers/sensor.h>
-#include <zephyr/drivers/spi.h>
-#include <zephyr/drivers/i2c.h>
-#include <zephyr/kernel.h>
-
-#include "imu/inv_imu_driver.h"
-#ifdef CONFIG_TDK_APEX
-#include "imu/inv_imu_apex.h"
-#endif
-
-union icm42670_bus {
-#if CONFIG_SPI
-	struct spi_dt_spec spi;
-#endif
-#if CONFIG_I2C
-	struct i2c_dt_spec i2c;
-#endif
-};
-
-typedef int (*icm42670_bus_check_fn)(const union icm42670_bus *bus);
-typedef int (*icm42670_reg_read_fn)(const union icm42670_bus *bus, uint8_t reg, uint8_t *buf,
-				    uint32_t size);
-typedef int (*icm42670_reg_write_fn)(const union icm42670_bus *bus, uint8_t reg, uint8_t *buf,
-				     uint32_t size);
-
-struct icm42670_bus_io {
-	icm42670_bus_check_fn check;
-	icm42670_reg_read_fn read;
-	icm42670_reg_write_fn write;
-};
-
-#if CONFIG_SPI
-extern const struct icm42670_bus_io icm42670_bus_io_spi;
-#endif
-
-#if CONFIG_I2C
-extern const struct icm42670_bus_io icm42670_bus_io_i2c;
-#endif
-
-struct icm42670_data {
-	struct inv_imu_serif serif;
-	struct inv_imu_device driver;
-	uint8_t imu_whoami;
-	char *imu_name;
-	uint8_t chip_id;
-	int32_t accel_x;
-	int32_t accel_y;
-	int32_t accel_z;
-	uint16_t accel_hz;
-	uint8_t accel_fs;
-	uint8_t accel_pwr_mode;
-	int32_t gyro_x;
-	int32_t gyro_y;
-	int32_t gyro_z;
-	uint16_t gyro_hz;
-	uint16_t gyro_fs;
-	int32_t temp;
-#ifdef CONFIG_TDK_APEX
-	uint8_t dmp_odr_hz;
-	uint64_t pedometer_cnt;
-	uint8_t pedometer_activity;
-	uint8_t pedometer_cadence;
-	uint8_t apex_status;
-#endif
-
-#ifdef CONFIG_ICM42670_TRIGGER
-	const struct device *dev;
-	struct gpio_callback gpio_cb;
-	sensor_trigger_handler_t data_ready_handler;
-	const struct sensor_trigger *data_ready_trigger;
-	struct k_mutex mutex;
-#endif
-#ifdef CONFIG_ICM42670_TRIGGER_OWN_THREAD
-	K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_ICM42670_THREAD_STACK_SIZE);
-	struct k_thread thread;
-	struct k_sem gpio_sem;
-#endif
-#ifdef CONFIG_ICM42670_TRIGGER_GLOBAL_THREAD
-	struct k_work work;
-#endif
-};
-
-struct icm42670_config {
-	union icm42670_bus bus;
-	const struct icm42670_bus_io *bus_io;
-	struct gpio_dt_spec gpio_int;
-	uint8_t accel_fs;
-	uint16_t accel_hz;
-	uint16_t accel_avg;
-	uint16_t accel_filt_bw;
-	uint16_t gyro_fs;
-	uint16_t gyro_hz;
-	uint16_t gyro_filt_bw;
-	uint8_t accel_pwr_mode;
-	uint8_t apex;
-};
-
-#ifdef CONFIG_TDK_APEX
-
-#define ICM42670_APEX_STATUS_MASK_TILT  BIT(0)
-#define ICM42670_APEX_STATUS_MASK_SMD   BIT(1)
-#define ICM42670_APEX_STATUS_MASK_WOM_X BIT(2)
-#define ICM42670_APEX_STATUS_MASK_WOM_Y BIT(3)
-#define ICM42670_APEX_STATUS_MASK_WOM_Z BIT(4)
-
-int icm42670_apex_enable(inv_imu_device_t *s);
-int icm42670_apex_fetch_from_dmp(const struct device *dev);
-void icm42670_apex_pedometer_cadence_convert(struct sensor_value *val, uint8_t raw_val,
-					     uint8_t dmp_odr_hz);
-int icm42670_apex_enable_pedometer(const struct device *dev, inv_imu_device_t *s);
-int icm42670_apex_enable_tilt(inv_imu_device_t *s);
-int icm42670_apex_enable_smd(inv_imu_device_t *s);
-int icm42670_apex_enable_wom(inv_imu_device_t *s);
-#endif
-
-#endif /* ZEPHYR_DRIVERS_SENSOR_ICM42670_H_ */
diff --git a/drivers/sensor/tdk/icm42670/icm42670_apex.c b/drivers/sensor/tdk/icm42670/icm42670_apex.c
deleted file mode 100644
index bdd128b6238..00000000000
--- a/drivers/sensor/tdk/icm42670/icm42670_apex.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Copyright (c) 2024 TDK Invensense
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "icm42670.h"
-#include "imu/inv_imu_apex.h"
-
-int icm42670_apex_enable(inv_imu_device_t *s)
-{
-	int err = 0;
-	inv_imu_apex_parameters_t apex_inputs;
-	inv_imu_interrupt_parameter_t config_int = {(inv_imu_interrupt_value)0};
-
-	/* Disabling FIFO to avoid extra power consumption due to ALP config */
-	err |= inv_imu_configure_fifo(s, INV_IMU_FIFO_DISABLED);
-
-	/* Enable Pedometer, Tilt and SMD interrupts */
-	config_int.INV_STEP_DET = INV_IMU_ENABLE;
-	config_int.INV_STEP_CNT_OVFL = INV_IMU_ENABLE;
-	config_int.INV_TILT_DET = INV_IMU_ENABLE;
-	config_int.INV_SMD = INV_IMU_ENABLE;
-	err |= inv_imu_set_config_int1(s, &config_int);
-
-	/* Enable accelerometer to feed the APEX Pedometer algorithm */
-	err |= inv_imu_set_accel_frequency(s, ACCEL_CONFIG0_ODR_50_HZ);
-
-	/* Set 2x averaging, in order to minimize power consumption (16x by default) */
-	err |= inv_imu_set_accel_lp_avg(s, ACCEL_CONFIG1_ACCEL_FILT_AVG_2);
-	err |= inv_imu_enable_accel_low_power_mode(s);
-
-	/* Get the default parameters for the APEX features */
-	err |= inv_imu_apex_init_parameters_struct(s, &apex_inputs);
-
-	/*
-	 * Configure the power mode Normal mode.
-	 *  Avalaible mode : Low Power mode (WoM+Pedometer),
-	 *  configure the WoM to wake-up the DMP once it goes in power save mode
-	 */
-	apex_inputs.power_save = APEX_CONFIG0_DMP_POWER_SAVE_DIS;
-	err |= inv_imu_apex_configure_parameters(s, &apex_inputs);
-
-	/* Configure sampling frequency to 50Hz */
-	err |= inv_imu_apex_set_frequency(s, APEX_CONFIG1_DMP_ODR_50Hz);
-
-	return err;
-}
-
-int icm42670_apex_fetch_from_dmp(const struct device *dev)
-{
-	struct icm42670_data *data = dev->data;
-	int rc = 0;
-	uint8_t int_status2, int_status3;
-
-	/* Read APEX interrupt status */
-	rc |= inv_imu_read_reg(&data->driver, INT_STATUS2, 1, &int_status2);
-	rc |= inv_imu_read_reg(&data->driver, INT_STATUS3, 1, &int_status3);
-
-	/* Test Pedometer interrupt */
-	if (int_status3 & (INT_STATUS3_STEP_DET_INT_MASK)) {
-		inv_imu_apex_step_activity_t apex_pedometer;
-		uint8_t step_cnt_ovflw = 0;
-
-		if (int_status3 & INT_STATUS3_STEP_CNT_OVF_INT_MASK) {
-			step_cnt_ovflw = 1;
-		}
-
-		rc |= inv_imu_apex_get_data_activity(&data->driver, &apex_pedometer);
-
-		if (data->pedometer_cnt !=
-		    apex_pedometer.step_cnt + step_cnt_ovflw * (uint64_t)UINT16_MAX) {
-			data->pedometer_cnt =
-				apex_pedometer.step_cnt + step_cnt_ovflw * (uint64_t)UINT16_MAX;
-			data->pedometer_activity = apex_pedometer.activity_class;
-			data->pedometer_cadence = apex_pedometer.step_cadence;
-		} else {
-			/* Pedometer data processing */
-			rc = 1;
-		}
-	}
-	/* Test Tilt interrupt */
-	if (int_status3 & (INT_STATUS3_TILT_DET_INT_MASK)) {
-		data->apex_status = ICM42670_APEX_STATUS_MASK_TILT;
-	}
-	/* Test SMD interrupt */
-	if ((int_status2 & (INT_STATUS2_SMD_INT_MASK)) || (rc != 0)) {
-		data->apex_status = ICM42670_APEX_STATUS_MASK_SMD;
-	}
-	/* Test WOM interrupts */
-	if (int_status2 & (INT_STATUS2_WOM_X_INT_MASK | INT_STATUS2_WOM_Y_INT_MASK |
-			   INT_STATUS2_WOM_Z_INT_MASK)) {
-		data->apex_status = 0;
-		if (int_status2 & INT_STATUS2_WOM_X_INT_MASK) {
-			data->apex_status |= ICM42670_APEX_STATUS_MASK_WOM_X;
-		}
-		if (int_status2 & INT_STATUS2_WOM_Y_INT_MASK) {
-			data->apex_status |= ICM42670_APEX_STATUS_MASK_WOM_Y;
-		}
-		if (int_status2 & INT_STATUS2_WOM_Z_INT_MASK) {
-			data->apex_status |= ICM42670_APEX_STATUS_MASK_WOM_Z;
-		}
-	}
-	return rc;
-}
-
-void icm42670_apex_pedometer_cadence_convert(struct sensor_value *val, uint8_t raw_val,
-					     uint8_t dmp_odr_hz)
-{
-	int64_t conv_val;
-
-	/* Converting u6.2 */
-	conv_val = (int64_t)(dmp_odr_hz << 2) * 1000000 / (raw_val + (raw_val & 0x03));
-	val->val1 = conv_val / 1000000;
-	val->val2 = conv_val % 1000000;
-}
-
-int icm42670_apex_enable_pedometer(const struct device *dev, inv_imu_device_t *s)
-{
-	struct icm42670_data *data = dev->data;
-
-	data->dmp_odr_hz = 50;
-	/* Enable the pedometer */
-	return inv_imu_apex_enable_pedometer(s);
-}
-
-int icm42670_apex_enable_tilt(inv_imu_device_t *s)
-{
-	/* Enable Tilt */
-	return inv_imu_apex_enable_tilt(s);
-}
-
-int icm42670_apex_enable_smd(inv_imu_device_t *s)
-{
-	int rc = 0;
-
-	/* Enable SMD (and Pedometer as SMD uses it) */
-	rc |= inv_imu_apex_enable_pedometer(s);
-	rc |= inv_imu_apex_enable_smd(s);
-
-	return rc;
-}
-
-int icm42670_apex_enable_wom(inv_imu_device_t *s)
-{
-	int rc = 0;
-	inv_imu_interrupt_parameter_t config_int = {(inv_imu_interrupt_value)0};
-
-	/*
-	 * Optimize power consumption:
-	 * - Disable FIFO usage.
-	 * - Disable data ready interrupt and enable WOM interrupts.
-	 * - Set 2X averaging.
-	 * - Use Low-Power mode at low frequency.
-	 */
-	rc |= inv_imu_configure_fifo(s, INV_IMU_FIFO_DISABLED);
-
-	config_int.INV_WOM_X = INV_IMU_ENABLE;
-	config_int.INV_WOM_Y = INV_IMU_ENABLE;
-	config_int.INV_WOM_Z = INV_IMU_ENABLE;
-	rc |= inv_imu_set_config_int1(s, &config_int);
-
-	rc |= inv_imu_set_accel_lp_avg(s, ACCEL_CONFIG1_ACCEL_FILT_AVG_2);
-	rc |= inv_imu_set_accel_frequency(s, ACCEL_CONFIG0_ODR_12_5_HZ);
-	rc |= inv_imu_enable_accel_low_power_mode(s);
-
-	/*
-	 * Configure WOM thresholds for each axis to 195 mg (Resolution 1g/256)
-	 * WOM threshold = 50 * 1000 / 256 = 195 mg
-	 * and enable WOM
-	 */
-	rc |= inv_imu_configure_wom(s, 50, 50, 50, WOM_CONFIG_WOM_INT_MODE_ORED,
-				    WOM_CONFIG_WOM_INT_DUR_1_SMPL);
-	rc |= inv_imu_enable_wom(s);
-
-	return rc;
-}
diff --git a/drivers/sensor/tdk/icm42670/icm42670_i2c.c b/drivers/sensor/tdk/icm42670/icm42670_i2c.c
deleted file mode 100644
index a3871ec25d5..00000000000
--- a/drivers/sensor/tdk/icm42670/icm42670_i2c.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (c) 2024 TDK Invensense
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/*
- * Bus-specific functionality for ICM42670 accessed via I2C.
- */
-
-#include "icm42670.h"
-
-#if CONFIG_I2C
-static int icm42670_bus_check_i2c(const union icm42670_bus *bus)
-{
-	return device_is_ready(bus->i2c.bus) ? 0 : -ENODEV;
-}
-
-static int icm42670_reg_read_i2c(const union icm42670_bus *bus, uint8_t reg, uint8_t *buf,
-				 uint32_t size)
-{
-	return i2c_burst_read_dt(&bus->i2c, reg, buf, size);
-}
-
-static int icm42670_reg_write_i2c(const union icm42670_bus *bus, uint8_t reg, uint8_t *buf,
-				  uint32_t size)
-{
-	return i2c_burst_write_dt(&bus->i2c, reg, buf, size);
-}
-
-const struct icm42670_bus_io icm42670_bus_io_i2c = {
-	.check = icm42670_bus_check_i2c,
-	.read = icm42670_reg_read_i2c,
-	.write = icm42670_reg_write_i2c,
-};
-#endif /* CONFIG_I2C */
diff --git a/drivers/sensor/tdk/icm42670/icm42670_spi.c b/drivers/sensor/tdk/icm42670/icm42670_spi.c
deleted file mode 100644
index 22c778c5ee9..00000000000
--- a/drivers/sensor/tdk/icm42670/icm42670_spi.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * Copyright (c) 2024 TDK Invensense
- * Copyright (c) 2022 Esco Medical ApS
- * Copyright (c) 2020 TDK Invensense
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/*
- * Bus-specific functionality for ICM42670 accessed via SPI.
- */
-
-#include "icm42670.h"
-
-#if CONFIG_SPI
-
-#include <zephyr/logging/log.h>
-LOG_MODULE_DECLARE(ICM42670, CONFIG_SENSOR_LOG_LEVEL);
-
-static int icm42670_bus_check_spi(const union icm42670_bus *bus)
-{
-	return spi_is_ready_dt(&bus->spi) ? 0 : -ENODEV;
-}
-
-static int icm42670_reg_read_spi(const union icm42670_bus *bus, uint8_t start, uint8_t *buf,
-				 uint32_t size)
-
-{
-	uint8_t cmd[] = {(start | 0x80)};
-	const struct spi_buf tx_buf = {.buf = cmd, .len = sizeof(cmd)};
-	const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1};
-	struct spi_buf rx_buf[2];
-	const struct spi_buf_set rx = {.buffers = rx_buf, .count = ARRAY_SIZE(rx_buf)};
-	int ret;
-
-	rx_buf[0].buf = NULL;
-	rx_buf[0].len = 1;
-
-	rx_buf[1].len = size;
-	rx_buf[1].buf = buf;
-
-	ret = spi_transceive_dt(&bus->spi, &tx, &rx);
-	if (ret) {
-		LOG_ERR("spi_transceive FAIL %d\n", ret);
-		return ret;
-	}
-	return 0;
-}
-
-static int icm42670_reg_write_spi(const union icm42670_bus *bus, uint8_t reg, uint8_t *buf,
-				  uint32_t size)
-{
-	uint8_t cmd[] = {reg & 0x7F};
-	const struct spi_buf tx_buf[2] = {{.buf = cmd, .len = sizeof(cmd)},
-					  {.buf = buf, .len = size}};
-	const struct spi_buf_set tx = {.buffers = tx_buf, .count = 2};
-	int ret = spi_write_dt(&bus->spi, &tx);
-
-	if (ret) {
-		LOG_ERR("spi_write FAIL %d\n", ret);
-		return ret;
-	}
-	return 0;
-}
-
-const struct icm42670_bus_io icm42670_bus_io_spi = {
-	.check = icm42670_bus_check_spi,
-	.read = icm42670_reg_read_spi,
-	.write = icm42670_reg_write_spi,
-};
-
-#endif /* CONFIG_SPI */
diff --git a/drivers/sensor/tdk/icm42670/icm42670_trigger.c b/drivers/sensor/tdk/icm42670/icm42670_trigger.c
deleted file mode 100644
index cfe0f0723ff..00000000000
--- a/drivers/sensor/tdk/icm42670/icm42670_trigger.c
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * Copyright (c) 2024 TDK Invensense
- * Copyright (c) 2022 Esco Medical ApS
- * Copyright (c) 2016 TDK Invensense
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/device.h>
-#include <zephyr/drivers/sensor.h>
-#include <zephyr/sys/util.h>
-#include "icm42670.h"
-#include "icm42670_trigger.h"
-
-#include <zephyr/logging/log.h>
-LOG_MODULE_DECLARE(ICM42670, CONFIG_SENSOR_LOG_LEVEL);
-
-static void icm42670_gpio_callback(const struct device *dev, struct gpio_callback *cb,
-				   uint32_t pins)
-{
-	ARG_UNUSED(dev);
-	ARG_UNUSED(pins);
-
-	struct icm42670_data *data = CONTAINER_OF(cb, struct icm42670_data, gpio_cb);
-
-#if defined(CONFIG_ICM42670_TRIGGER_OWN_THREAD)
-	k_sem_give(&data->gpio_sem);
-#elif defined(CONFIG_ICM42670_TRIGGER_GLOBAL_THREAD)
-	k_work_submit(&data->work);
-#endif
-}
-
-static void icm42670_thread_cb(const struct device *dev)
-{
-	struct icm42670_data *data = dev->data;
-	const struct icm42670_config *cfg = dev->config;
-
-	icm42670_lock(dev);
-	gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_DISABLE);
-
-	if (data->data_ready_handler) {
-		data->data_ready_handler(dev, data->data_ready_trigger);
-	}
-
-	gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_EDGE_TO_ACTIVE);
-	icm42670_unlock(dev);
-}
-
-#if defined(CONFIG_ICM42670_TRIGGER_OWN_THREAD)
-
-static void icm42670_thread(void *p1, void *p2, void *p3)
-{
-	ARG_UNUSED(p2);
-	ARG_UNUSED(p3);
-
-	struct icm42670_data *data = p1;
-
-	while (1) {
-		k_sem_take(&data->gpio_sem, K_FOREVER);
-		icm42670_thread_cb(data->dev);
-	}
-}
-#elif defined(CONFIG_ICM42670_TRIGGER_GLOBAL_THREAD)
-
-static void icm42670_work_handler(struct k_work *work)
-{
-	struct icm42670_data *data = CONTAINER_OF(work, struct icm42670_data, work);
-
-	icm42670_thread_cb(data->dev);
-}
-
-#endif
-
-int icm42670_trigger_set(const struct device *dev, const struct sensor_trigger *trig,
-			 sensor_trigger_handler_t handler)
-{
-	struct icm42670_data *data = dev->data;
-	const struct icm42670_config *cfg = dev->config;
-
-	if (!handler) {
-		return -EINVAL;
-	}
-
-	icm42670_lock(dev);
-	gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_DISABLE);
-
-	if (trig->type == SENSOR_TRIG_DATA_READY) {
-		data->data_ready_handler = handler;
-		data->data_ready_trigger = trig;
-#ifdef CONFIG_TDK_APEX
-	} else if (trig->type == SENSOR_TRIG_MOTION) {
-		data->data_ready_handler = handler;
-		data->data_ready_trigger = trig;
-#endif
-	} else {
-		return -ENOTSUP;
-	}
-
-	icm42670_unlock(dev);
-	gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_EDGE_TO_ACTIVE);
-
-	return 0;
-}
-
-int icm42670_trigger_init(const struct device *dev)
-{
-	struct icm42670_data *data = dev->data;
-	const struct icm42670_config *cfg = dev->config;
-	int res = 0;
-
-	if (!cfg->gpio_int.port) {
-		LOG_ERR("trigger enabled but no interrupt gpio supplied");
-		return -ENODEV;
-	}
-
-	if (!gpio_is_ready_dt(&cfg->gpio_int)) {
-		LOG_ERR("gpio_int gpio not ready");
-		return -ENODEV;
-	}
-
-	data->dev = dev;
-	gpio_pin_configure_dt(&cfg->gpio_int, GPIO_INPUT);
-	gpio_init_callback(&data->gpio_cb, icm42670_gpio_callback, BIT(cfg->gpio_int.pin));
-	res = gpio_add_callback(cfg->gpio_int.port, &data->gpio_cb);
-
-	if (res < 0) {
-		LOG_ERR("Failed to set gpio callback");
-		return res;
-	}
-
-	k_mutex_init(&data->mutex);
-
-#if defined(CONFIG_ICM42670_TRIGGER_OWN_THREAD)
-	k_sem_init(&data->gpio_sem, 0, K_SEM_MAX_LIMIT);
-	k_thread_create(&data->thread, data->thread_stack, CONFIG_ICM42670_THREAD_STACK_SIZE,
-			icm42670_thread, data, NULL, NULL,
-			K_PRIO_COOP(CONFIG_ICM42670_THREAD_PRIORITY), 0, K_NO_WAIT);
-#elif defined(CONFIG_ICM42670_TRIGGER_GLOBAL_THREAD)
-	data->work.handler = icm42670_work_handler;
-#endif
-
-	return gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_EDGE_TO_INACTIVE);
-}
-
-int icm42670_trigger_enable_interrupt(const struct device *dev)
-{
-	struct icm42670_data *data = dev->data;
-	int err = 0;
-	inv_imu_int1_pin_config_t int1_pin_config;
-	inv_imu_interrupt_parameter_t config_int = {(inv_imu_interrupt_value)0};
-
-	/* Set interrupt config */
-	int1_pin_config.int_polarity = INT_CONFIG_INT1_POLARITY_HIGH;
-	int1_pin_config.int_mode = INT_CONFIG_INT1_MODE_PULSED;
-	int1_pin_config.int_drive = INT_CONFIG_INT1_DRIVE_CIRCUIT_PP;
-	err |= inv_imu_set_pin_config_int1(&data->driver, &int1_pin_config);
-
-	config_int.INV_FIFO_THS = INV_IMU_ENABLE;
-	err |= inv_imu_set_config_int1(&data->driver, &config_int);
-
-	return err;
-}
-
-void icm42670_lock(const struct device *dev)
-{
-	struct icm42670_data *data = dev->data;
-
-	k_mutex_lock(&data->mutex, K_FOREVER);
-}
-
-void icm42670_unlock(const struct device *dev)
-{
-	struct icm42670_data *data = dev->data;
-
-	k_mutex_unlock(&data->mutex);
-}
diff --git a/drivers/sensor/tdk/icm42670/icm42670_trigger.h b/drivers/sensor/tdk/icm42670/icm42670_trigger.h
deleted file mode 100644
index 7a9d2e1ab0b..00000000000
--- a/drivers/sensor/tdk/icm42670/icm42670_trigger.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2022 Esco Medical ApS
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_DRIVERS_SENSOR_ICM42670_TRIGGER_H_
-#define ZEPHYR_DRIVERS_SENSOR_ICM42670_TRIGGER_H_
-
-#include <zephyr/device.h>
-
-/** implement the trigger_set sensor api function */
-int icm42670_trigger_set(const struct device *dev, const struct sensor_trigger *trig,
-			 sensor_trigger_handler_t handler);
-
-/**
- * @brief initialize the icm42670 trigger system
- *
- * @param dev icm42670 device pointer
- * @return int 0 on success, negative error code otherwise
- */
-int icm42670_trigger_init(const struct device *dev);
-
-/**
- * @brief enable the trigger gpio interrupt
- *
- * @param dev icm42670 device pointer
- * @return int 0 on success, negative error code otherwise
- */
-int icm42670_trigger_enable_interrupt(const struct device *dev);
-
-/**
- * @brief lock access to the icm42670 device driver
- *
- * @param dev icm42670 device pointer
- */
-void icm42670_lock(const struct device *dev);
-
-/**
- * @brief lock access to the icm42670 device driver
- *
- * @param dev icm42670 device pointer
- */
-void icm42670_unlock(const struct device *dev);
-
-#endif /* ZEPHYR_DRIVERS_SENSOR_ICM42670_TRIGGER_H_ */
diff --git a/drivers/sensor/tdk/icm42688/icm42688.h b/drivers/sensor/tdk/icm42688/icm42688.h
index 410f0f983fb..65c534495d2 100644
--- a/drivers/sensor/tdk/icm42688/icm42688.h
+++ b/drivers/sensor/tdk/icm42688/icm42688.h
@@ -412,10 +412,10 @@ int icm42688_read_all(const struct device *dev, uint8_t data[14]);
  * @param cfg icm42688_cfg current device configuration
  * @param in raw data value in int32_t format
  * @param out_g whole G's output in int32_t
- * @param out_ug micro (1/1000000) of a G output as uint32_t
+ * @param out_ug micro (1/1000000) of a G output as int32_t
  */
 static inline void icm42688_accel_g(struct icm42688_cfg *cfg, int32_t in, int32_t *out_g,
-				    uint32_t *out_ug)
+				    int32_t *out_ug)
 {
 	int32_t sensitivity;
 
@@ -449,10 +449,10 @@ static inline void icm42688_accel_g(struct icm42688_cfg *cfg, int32_t in, int32_
  * @param cfg icm42688_cfg current device configuration
  * @param in raw data value in int32_t format
  * @param out_dps whole deg/s output in int32_t
- * @param out_udps micro (1/1000000) deg/s as uint32_t
+ * @param out_udps micro (1/1000000) deg/s as int32_t
  */
 static inline void icm42688_gyro_dps(const struct icm42688_cfg *cfg, int32_t in, int32_t *out_dps,
-				     uint32_t *out_udps)
+				     int32_t *out_udps)
 {
 	int64_t sensitivity;
 
@@ -501,7 +501,7 @@ static inline void icm42688_gyro_dps(const struct icm42688_cfg *cfg, int32_t in,
  * @param cfg icm42688_cfg current device configuration
  * @param in raw data value in int32_t format
  * @param out_ms meters/s^2 (whole) output in int32_t
- * @param out_ums micrometers/s^2 output as uint32_t
+ * @param out_ums micrometers/s^2 output as int32_t
  */
 static inline void icm42688_accel_ms(const struct icm42688_cfg *cfg, int32_t in, int32_t *out_ms,
 				     int32_t *out_ums)
@@ -541,7 +541,7 @@ static inline void icm42688_accel_ms(const struct icm42688_cfg *cfg, int32_t in,
  * @param cfg icm42688_cfg current device configuration
  * @param in raw data value in int32_t format
  * @param out_rads whole rad/s output in int32_t
- * @param out_urads microrad/s as uint32_t
+ * @param out_urads microrad/s as int32_t
  */
 static inline void icm42688_gyro_rads(const struct icm42688_cfg *cfg, int32_t in, int32_t *out_rads,
 				      int32_t *out_urads)
@@ -593,9 +593,9 @@ static inline void icm42688_gyro_rads(const struct icm42688_cfg *cfg, int32_t in
  * @param cfg icm42688_cfg current device configuration
  * @param in raw data value in int32_t format
  * @param out_c whole celsius output in int32_t
- * @param out_uc micro (1/1000000) celsius as uint32_t
+ * @param out_uc micro (1/1000000) celsius as int32_t
  */
-static inline void icm42688_temp_c(int32_t in, int32_t *out_c, uint32_t *out_uc)
+static inline void icm42688_temp_c(int32_t in, int32_t *out_c, int32_t *out_uc)
 {
 	int64_t sensitivity = 13248; /* value equivalent for x100 1c */
 
diff --git a/drivers/sensor/tdk/icm42688/icm42688_common.c b/drivers/sensor/tdk/icm42688/icm42688_common.c
index 3a0c79869be..b674b07009a 100644
--- a/drivers/sensor/tdk/icm42688/icm42688_common.c
+++ b/drivers/sensor/tdk/icm42688/icm42688_common.c
@@ -255,8 +255,11 @@ int icm42688_configure(const struct device *dev, struct icm42688_cfg *cfg)
 		 * temp/accel/gyro en fields in cfg
 		 */
 		uint8_t fifo_cfg1 =
-			FIELD_PREP(BIT_FIFO_TEMP_EN, 1) | FIELD_PREP(BIT_FIFO_GYRO_EN, 1) |
-			FIELD_PREP(BIT_FIFO_ACCEL_EN, 1) | FIELD_PREP(BIT_FIFO_TMST_FSYNC_EN, 1);
+			FIELD_PREP(BIT_FIFO_TEMP_EN, 1) |
+			FIELD_PREP(BIT_FIFO_GYRO_EN, 1) |
+			FIELD_PREP(BIT_FIFO_ACCEL_EN, 1) |
+			FIELD_PREP(BIT_FIFO_TMST_FSYNC_EN, 1) |
+			FIELD_PREP(BIT_FIFO_HIRES_EN, 1);
 
 		LOG_DBG("FIFO_CONFIG1 (0x%x) 0x%x", REG_FIFO_CONFIG1, fifo_cfg1);
 		res = icm42688_spi_single_write(&dev_cfg->spi, REG_FIFO_CONFIG1, fifo_cfg1);
diff --git a/drivers/sensor/tdk/icm42688/icm42688_decoder.c b/drivers/sensor/tdk/icm42688/icm42688_decoder.c
index c01cc3f9c27..bb2730ef708 100644
--- a/drivers/sensor/tdk/icm42688/icm42688_decoder.c
+++ b/drivers/sensor/tdk/icm42688/icm42688_decoder.c
@@ -10,6 +10,8 @@
 #include <errno.h>
 
 #include <zephyr/logging/log.h>
+#include <zephyr/drivers/sensor_clock.h>
+
 LOG_MODULE_REGISTER(ICM42688_DECODER, CONFIG_SENSOR_LOG_LEVEL);
 
 #define DT_DRV_COMPAT invensense_icm42688
@@ -183,6 +185,8 @@ int icm42688_encode(const struct device *dev, const struct sensor_chan_spec *con
 {
 	struct icm42688_dev_data *data = dev->data;
 	struct icm42688_encoded_data *edata = (struct icm42688_encoded_data *)buf;
+	uint64_t cycles;
+	int rc;
 
 	edata->channels = 0;
 
@@ -190,10 +194,15 @@ int icm42688_encode(const struct device *dev, const struct sensor_chan_spec *con
 		edata->channels |= icm42688_encode_channel(channels[i].chan_type);
 	}
 
+	rc = sensor_clock_get_cycles(&cycles);
+	if (rc != 0) {
+		return rc;
+	}
+
 	edata->header.is_fifo = false;
 	edata->header.accel_fs = data->cfg.accel_fs;
 	edata->header.gyro_fs = data->cfg.gyro_fs;
-	edata->header.timestamp = k_ticks_to_ns_floor64(k_uptime_ticks());
+	edata->header.timestamp = sensor_clock_cycles_to_ns(cycles);
 
 	return 0;
 }
@@ -234,81 +243,33 @@ static inline q31_t icm42688_read_temperature_from_packet(const uint8_t *pkt)
 static int icm42688_read_imu_from_packet(const uint8_t *pkt, bool is_accel, int fs,
 					 uint8_t axis_offset, q31_t *out)
 {
-	int32_t value;
-	int64_t scale = 0;
-	int32_t max = BIT(15);
+	uint32_t unsigned_value;
+	int32_t signed_value;
+	bool is_hires = FIELD_GET(FIFO_HEADER_ACCEL, pkt[0]) == 1;
 	int offset = 1 + (axis_offset * 2);
 
-	if (is_accel) {
-		switch (fs) {
-		case ICM42688_DT_ACCEL_FS_2:
-			scale = INT64_C(2) * BIT(31 - 5) * 9.80665;
-			break;
-		case ICM42688_DT_ACCEL_FS_4:
-			scale = INT64_C(4) * BIT(31 - 6) * 9.80665;
-			break;
-		case ICM42688_DT_ACCEL_FS_8:
-			scale = INT64_C(8) * BIT(31 - 7) * 9.80665;
-			break;
-		case ICM42688_DT_ACCEL_FS_16:
-			scale = INT64_C(16) * BIT(31 - 8) * 9.80665;
-			break;
-		}
-	} else {
-		switch (fs) {
-		case ICM42688_DT_GYRO_FS_2000:
-			scale = 164;
-			break;
-		case ICM42688_DT_GYRO_FS_1000:
-			scale = 328;
-			break;
-		case ICM42688_DT_GYRO_FS_500:
-			scale = 655;
-			break;
-		case ICM42688_DT_GYRO_FS_250:
-			scale = 1310;
-			break;
-		case ICM42688_DT_GYRO_FS_125:
-			scale = 2620;
-			break;
-		case ICM42688_DT_GYRO_FS_62_5:
-			scale = 5243;
-			break;
-		case ICM42688_DT_GYRO_FS_31_25:
-			scale = 10486;
-			break;
-		case ICM42688_DT_GYRO_FS_15_625:
-			scale = 20972;
-			break;
-		}
-	}
+	const uint32_t scale[2][2] = {
+		/* low-res,	hi-res */
+		{35744,		8936}, /* gyro */
+		{40168,		2511}, /* accel */
+	};
 
 	if (!is_accel && FIELD_GET(FIFO_HEADER_ACCEL, pkt[0]) == 1) {
-		offset += 7;
+		offset += 6;
 	}
 
-	value = (int16_t)sys_le16_to_cpu((pkt[offset] << 8) | pkt[offset + 1]);
+	unsigned_value = (pkt[offset] << 8) | pkt[offset + 1];
 
-	if (FIELD_GET(FIFO_HEADER_20, pkt[0]) == 1) {
+	if (is_hires) {
 		uint32_t mask = is_accel ? GENMASK(7, 4) : GENMASK(3, 0);
-
-		offset = 0x11 + axis_offset;
-		value = (value << 4) | FIELD_GET(mask, pkt[offset]);
-		/* In 20 bit mode, FS can only be +/-16g and +/-2000dps */
-		scale = is_accel ? (INT64_C(16) * BIT(8) * 9.80665) : 131;
-		max = is_accel ? BIT(18) : BIT(19);
-		if (value == -524288) {
-			/* Invalid 20 bit value */
-			return -ENODATA;
-		}
+		offset = 17 + axis_offset;
+		unsigned_value = (unsigned_value << 4) | FIELD_GET(mask, pkt[offset]);
+		signed_value = unsigned_value | (0 - (unsigned_value & BIT(19)));
 	} else {
-		if (value <= -32767) {
-			/* Invalid 16 bit value */
-			return -ENODATA;
-		}
+		signed_value = unsigned_value | (0 - (unsigned_value & BIT(16)));
 	}
 
-	*out = (q31_t)(value * scale / max);
+	*out = (q31_t)(signed_value * scale[is_accel][is_hires]);
 	return 0;
 }
 
@@ -425,7 +386,7 @@ static int icm42688_fifo_decode(const uint8_t *buffer, struct sensor_chan_spec c
 			/* Decode gyro */
 			struct sensor_three_axis_data *data =
 				(struct sensor_three_axis_data *)data_out;
-			uint64_t period_ns = accel_period_ns[edata->gyro_odr];
+			uint64_t period_ns = gyro_period_ns[edata->gyro_odr];
 
 			icm42688_get_shift(SENSOR_CHAN_GYRO_XYZ, edata->header.accel_fs,
 					   edata->header.gyro_fs, &data->shift);
@@ -473,42 +434,36 @@ static int icm42688_one_shot_decode(const uint8_t *buffer, struct sensor_chan_sp
 	case SENSOR_CHAN_ACCEL_X:
 	case SENSOR_CHAN_ACCEL_Y:
 	case SENSOR_CHAN_ACCEL_Z:
-	case SENSOR_CHAN_ACCEL_XYZ: {
-		channel_request = icm42688_encode_channel(SENSOR_CHAN_ACCEL_XYZ);
+	case SENSOR_CHAN_GYRO_X:
+	case SENSOR_CHAN_GYRO_Y:
+	case SENSOR_CHAN_GYRO_Z:
+	case SENSOR_CHAN_DIE_TEMP: {
+		channel_request = icm42688_encode_channel(chan_spec.chan_type);
 		if ((channel_request & edata->channels) != channel_request) {
 			return -ENODATA;
 		}
 
-		struct sensor_three_axis_data *out = data_out;
+		struct sensor_q31_data *out = data_out;
 
 		out->header.base_timestamp_ns = edata->header.timestamp;
 		out->header.reading_count = 1;
-		rc = icm42688_get_shift(SENSOR_CHAN_ACCEL_XYZ, header->accel_fs, header->gyro_fs,
+
+		rc = icm42688_get_shift(chan_spec.chan_type, header->accel_fs, header->gyro_fs,
 					&out->shift);
 		if (rc != 0) {
 			return -EINVAL;
 		}
 
 		icm42688_convert_raw_to_q31(
-			&cfg, SENSOR_CHAN_ACCEL_X,
-			edata->readings[icm42688_get_channel_position(SENSOR_CHAN_ACCEL_X)],
-			&out->readings[0].x);
-		icm42688_convert_raw_to_q31(
-			&cfg, SENSOR_CHAN_ACCEL_Y,
-			edata->readings[icm42688_get_channel_position(SENSOR_CHAN_ACCEL_Y)],
-			&out->readings[0].y);
-		icm42688_convert_raw_to_q31(
-			&cfg, SENSOR_CHAN_ACCEL_Z,
-			edata->readings[icm42688_get_channel_position(SENSOR_CHAN_ACCEL_Z)],
-			&out->readings[0].z);
+			&cfg, chan_spec.chan_type,
+			edata->readings[icm42688_get_channel_position(chan_spec.chan_type)],
+			&out->readings[0].value);
 		*fit = 1;
 		return 1;
 	}
-	case SENSOR_CHAN_GYRO_X:
-	case SENSOR_CHAN_GYRO_Y:
-	case SENSOR_CHAN_GYRO_Z:
+	case SENSOR_CHAN_ACCEL_XYZ:
 	case SENSOR_CHAN_GYRO_XYZ: {
-		channel_request = icm42688_encode_channel(SENSOR_CHAN_GYRO_XYZ);
+		channel_request = icm42688_encode_channel(chan_spec.chan_type);
 		if ((channel_request & edata->channels) != channel_request) {
 			return -ENODATA;
 		}
@@ -517,52 +472,27 @@ static int icm42688_one_shot_decode(const uint8_t *buffer, struct sensor_chan_sp
 
 		out->header.base_timestamp_ns = edata->header.timestamp;
 		out->header.reading_count = 1;
-		rc = icm42688_get_shift(SENSOR_CHAN_GYRO_XYZ, header->accel_fs, header->gyro_fs,
+		rc = icm42688_get_shift(chan_spec.chan_type, header->accel_fs, header->gyro_fs,
 					&out->shift);
 		if (rc != 0) {
 			return -EINVAL;
 		}
 
-		out->readings[0].timestamp_delta = 0;
 		icm42688_convert_raw_to_q31(
-			&cfg, SENSOR_CHAN_GYRO_X,
-			edata->readings[icm42688_get_channel_position(SENSOR_CHAN_GYRO_X)],
+			&cfg, chan_spec.chan_type - 3,
+			edata->readings[icm42688_get_channel_position(chan_spec.chan_type - 3)],
 			&out->readings[0].x);
 		icm42688_convert_raw_to_q31(
-			&cfg, SENSOR_CHAN_GYRO_Y,
-			edata->readings[icm42688_get_channel_position(SENSOR_CHAN_GYRO_Y)],
+			&cfg, chan_spec.chan_type - 2,
+			edata->readings[icm42688_get_channel_position(chan_spec.chan_type - 2)],
 			&out->readings[0].y);
 		icm42688_convert_raw_to_q31(
-			&cfg, SENSOR_CHAN_GYRO_Z,
-			edata->readings[icm42688_get_channel_position(SENSOR_CHAN_GYRO_Z)],
+			&cfg, chan_spec.chan_type - 1,
+			edata->readings[icm42688_get_channel_position(chan_spec.chan_type - 1)],
 			&out->readings[0].z);
 		*fit = 1;
 		return 1;
 	}
-	case SENSOR_CHAN_DIE_TEMP: {
-		channel_request = icm42688_encode_channel(SENSOR_CHAN_DIE_TEMP);
-		if ((channel_request & edata->channels) != channel_request) {
-			return -ENODATA;
-		}
-
-		struct sensor_q31_data *out = data_out;
-
-		out->header.base_timestamp_ns = edata->header.timestamp;
-		out->header.reading_count = 1;
-
-		rc = icm42688_get_shift(SENSOR_CHAN_DIE_TEMP, header->accel_fs, header->gyro_fs,
-					&out->shift);
-		if (rc != 0) {
-			return -EINVAL;
-		}
-		out->readings[0].timestamp_delta = 0;
-		icm42688_convert_raw_to_q31(
-			&cfg, SENSOR_CHAN_DIE_TEMP,
-			edata->readings[icm42688_get_channel_position(SENSOR_CHAN_DIE_TEMP)],
-			&out->readings[0].temperature);
-		*fit = 1;
-		return 1;
-	}
 	default:
 		return -EINVAL;
 	}
@@ -585,12 +515,21 @@ static int icm42688_decoder_get_frame_count(const uint8_t *buffer,
 					    uint16_t *frame_count)
 {
 	const struct icm42688_fifo_data *data = (const struct icm42688_fifo_data *)buffer;
+	const struct icm42688_encoded_data *enc_data = (const struct icm42688_encoded_data *)buffer;
 	const struct icm42688_decoder_header *header = &data->header;
 
 	if (chan_spec.chan_idx != 0) {
 		return -ENOTSUP;
 	}
 
+	uint8_t channel_request = icm42688_encode_channel(chan_spec.chan_type);
+
+
+	if ((!enc_data->header.is_fifo) &&
+	    (enc_data->channels & channel_request) != channel_request) {
+		return -ENODATA;
+	}
+
 	if (!header->is_fifo) {
 		switch (chan_spec.chan_type) {
 		case SENSOR_CHAN_ACCEL_X:
@@ -645,17 +584,17 @@ static int icm42688_decoder_get_size_info(struct sensor_chan_spec chan_spec, siz
 					  size_t *frame_size)
 {
 	switch (chan_spec.chan_type) {
+	case SENSOR_CHAN_ACCEL_XYZ:
+	case SENSOR_CHAN_GYRO_XYZ:
+		*base_size = sizeof(struct sensor_three_axis_data);
+		*frame_size = sizeof(struct sensor_three_axis_sample_data);
+		return 0;
 	case SENSOR_CHAN_ACCEL_X:
 	case SENSOR_CHAN_ACCEL_Y:
 	case SENSOR_CHAN_ACCEL_Z:
-	case SENSOR_CHAN_ACCEL_XYZ:
 	case SENSOR_CHAN_GYRO_X:
 	case SENSOR_CHAN_GYRO_Y:
 	case SENSOR_CHAN_GYRO_Z:
-	case SENSOR_CHAN_GYRO_XYZ:
-		*base_size = sizeof(struct sensor_three_axis_data);
-		*frame_size = sizeof(struct sensor_three_axis_sample_data);
-		return 0;
 	case SENSOR_CHAN_DIE_TEMP:
 		*base_size = sizeof(struct sensor_q31_data);
 		*frame_size = sizeof(struct sensor_q31_sample_data);
diff --git a/drivers/sensor/tdk/icm42688/icm42688_reg.h b/drivers/sensor/tdk/icm42688/icm42688_reg.h
index 5f3b58f0b3c..486a745ad53 100644
--- a/drivers/sensor/tdk/icm42688/icm42688_reg.h
+++ b/drivers/sensor/tdk/icm42688/icm42688_reg.h
@@ -254,9 +254,9 @@
 #define BIT_FIFO_WM_GT_TH      BIT(5)
 #define BIT_FIFO_HIRES_EN      BIT(4)
 #define BIT_FIFO_TMST_FSYNC_EN BIT(3)
-#define BIT_FIFO_GYRO_EN       BIT(2)
-#define BIT_FIFO_ACCEL_EN      BIT(1)
-#define BIT_FIFO_TEMP_EN       BIT(0)
+#define BIT_FIFO_TEMP_EN       BIT(2)
+#define BIT_FIFO_GYRO_EN       BIT(1)
+#define BIT_FIFO_ACCEL_EN      BIT(0)
 
 /* Bank0 INT_SOURCE0 */
 #define BIT_UI_FSYNC_INT1_EN	    BIT(6)
diff --git a/drivers/sensor/tdk/icm42688/icm42688_rtio.c b/drivers/sensor/tdk/icm42688/icm42688_rtio.c
index aaa640699f9..1d865110758 100644
--- a/drivers/sensor/tdk/icm42688/icm42688_rtio.c
+++ b/drivers/sensor/tdk/icm42688/icm42688_rtio.c
@@ -66,7 +66,12 @@ static void icm42688_submit_one_shot(const struct device *dev, struct rtio_iodev
 
 	edata = (struct icm42688_encoded_data *)buf;
 
-	icm42688_encode(dev, channels, num_channels, buf);
+	rc = icm42688_encode(dev, channels, num_channels, buf);
+	if (rc != 0) {
+		LOG_ERR("Failed to encode sensor data");
+		rtio_iodev_sqe_err(iodev_sqe, rc);
+		return;
+	}
 
 	rc = icm42688_rtio_sample_fetch(dev, edata->readings);
 	/* Check that the fetch succeeded */
diff --git a/drivers/sensor/tdk/icm42688/icm42688_rtio_stream.c b/drivers/sensor/tdk/icm42688/icm42688_rtio_stream.c
index fd901742309..e6f2a60b8fc 100644
--- a/drivers/sensor/tdk/icm42688/icm42688_rtio_stream.c
+++ b/drivers/sensor/tdk/icm42688/icm42688_rtio_stream.c
@@ -5,7 +5,7 @@
  */
 
 #include <zephyr/logging/log.h>
-
+#include <zephyr/drivers/sensor_clock.h>
 #include "icm42688.h"
 #include "icm42688_decoder.h"
 #include "icm42688_reg.h"
@@ -130,7 +130,7 @@ static void icm42688_fifo_count_cb(struct rtio *r, const struct rtio_sqe *sqe, v
 	read_len = pkts * packet_size;
 	((struct icm42688_fifo_data *)buf)->fifo_count = read_len;
 
-	__ASSERT_NO_MSG(read_len % pkt_size == 0);
+	__ASSERT_NO_MSG(read_len % packet_size == 0);
 
 	uint8_t *read_buf = buf + sizeof(hdr);
 
@@ -292,12 +292,21 @@ void icm42688_fifo_event(const struct device *dev)
 	struct icm42688_dev_data *drv_data = dev->data;
 	struct rtio_iodev *spi_iodev = drv_data->spi_iodev;
 	struct rtio *r = drv_data->r;
+	uint64_t cycles;
+	int rc;
 
 	if (drv_data->streaming_sqe == NULL) {
 		return;
 	}
 
-	drv_data->timestamp = k_ticks_to_ns_floor64(k_uptime_ticks());
+	rc = sensor_clock_get_cycles(&cycles);
+	if (rc != 0) {
+		LOG_ERR("Failed to get sensor clock cycles");
+		rtio_iodev_sqe_err(drv_data->streaming_sqe, rc);
+		return;
+	}
+
+	drv_data->timestamp = sensor_clock_cycles_to_ns(cycles);
 
 	/*
 	 * Setup rtio chain of ops with inline calls to make decisions
diff --git a/drivers/sensor/tdk/icm42x70/CMakeLists.txt b/drivers/sensor/tdk/icm42x70/CMakeLists.txt
new file mode 100644
index 00000000000..0fd3a92aaa2
--- /dev/null
+++ b/drivers/sensor/tdk/icm42x70/CMakeLists.txt
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(icm42x70.c)
+
+zephyr_library_sources_ifdef(CONFIG_SPI icm42x70_spi.c)
+zephyr_library_sources_ifdef(CONFIG_I2C icm42x70_i2c.c)
+
+zephyr_library_sources_ifdef(CONFIG_USE_EMD_ICM42670 icm42670.c)
+
+zephyr_library_sources_ifdef(CONFIG_ICM42X70_TRIGGER icm42x70_trigger.c)
+zephyr_library_sources_ifdef(CONFIG_TDK_APEX icm42x70_apex.c)
diff --git a/drivers/sensor/tdk/icm42x70/Kconfig b/drivers/sensor/tdk/icm42x70/Kconfig
new file mode 100644
index 00000000000..bc218388e24
--- /dev/null
+++ b/drivers/sensor/tdk/icm42x70/Kconfig
@@ -0,0 +1,88 @@
+# ICM42670-P ICM42670-S Six-Axis Motion Tracking device configuration options
+#
+# Copyright (c) 2024 TDK Invensense
+# Copyright (c) 2022 Esco Medical ApS
+# Copyright (c) 2020 TDK Invensense
+#
+# SPDX-License-Identifier: Apache-2.0
+config TDK_APEX
+	bool
+
+menuconfig ICM42X70
+	bool "ICM42670-P/-S Six-Axis or ICM42370-P Three-Axis Motion Tracking Device"
+	default y
+	depends on DT_HAS_INVENSENSE_ICM42670P_ENABLED \
+		|| DT_HAS_INVENSENSE_ICM42670S_ENABLED \
+		|| DT_HAS_INVENSENSE_ICM42370P_ENABLED
+	depends on ZEPHYR_HAL_TDK_MODULE
+	select SPI if $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM42670P),spi) \
+		|| $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM42670S),spi) \
+		|| $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM42370P),spi)
+	select I2C if $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM42670P),i2c) \
+		|| $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM42670S),i2c) \
+		|| $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM42370P),i2c)
+	select TDK_APEX if $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42670p),apex,pedometer) \
+		|| $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42670p),apex,tilt) \
+		|| $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42670p),apex,smd) \
+		|| $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42670p),apex,wom) \
+		|| $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42670s),apex,pedometer) \
+		|| $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42670s),apex,tilt) \
+		|| $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42670s),apex,smd) \
+		|| $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42670s),apex,wom) \
+		|| $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42370p),apex,pedometer) \
+		|| $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42370p),apex,tilt) \
+		|| $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42370p),apex,smd) \
+		|| $(dt_node_str_prop_equals,$(dt_nodelabel_path,icm42370p),apex,wom)
+	select USE_EMD_ICM42670 if DT_HAS_INVENSENSE_ICM42670P_ENABLED || DT_HAS_INVENSENSE_ICM42670S_ENABLED
+	select USE_EMD_ICM42370 if DT_HAS_INVENSENSE_ICM42370P_ENABLED
+	select SENSOR_ASYNC_API
+	help
+	  Enable driver for ICM42x70 SPI-based or I2C-based Six-Axis or Three-Axis Motion Tracking device.
+
+if ICM42X70
+
+choice ICM42X70_TRIGGER_MODE
+	prompt "Trigger mode"
+	default ICM42X70_TRIGGER_NONE
+	help
+	  Specify the type of triggering to be used by the driver.
+
+config ICM42X70_TRIGGER_NONE
+	bool "No trigger"
+
+config ICM42X70_TRIGGER_GLOBAL_THREAD
+	bool "Use global thread"
+	depends on GPIO
+	depends on $(dt_compat_any_has_prop,$(DT_COMPAT_INVENSENSE_ICM42670P),int-gpios) \
+		|| $(dt_compat_any_has_prop,$(DT_COMPAT_INVENSENSE_ICM42670S),int-gpios) \
+		|| $(dt_compat_any_has_prop,$(DT_COMPAT_INVENSENSE_ICM42370P),int-gpios)
+	select ICM42X70_TRIGGER
+
+config ICM42X70_TRIGGER_OWN_THREAD
+	bool "Use own thread"
+	depends on GPIO
+	depends on $(dt_compat_any_has_prop,$(DT_COMPAT_INVENSENSE_ICM42670P),int-gpios) \
+		|| $(dt_compat_any_has_prop,$(DT_COMPAT_INVENSENSE_ICM42670S),int-gpios) \
+		|| $(dt_compat_any_has_prop,$(DT_COMPAT_INVENSENSE_ICM42370P),int-gpios)
+	select ICM42X70_TRIGGER
+
+endchoice
+
+config ICM42X70_TRIGGER
+	bool
+
+config ICM42X70_THREAD_PRIORITY
+	int "Thread priority"
+	depends on ICM42X70_TRIGGER_OWN_THREAD
+	default 10
+	help
+	  Priority of thread used by the driver to handle interrupts.
+
+config ICM42X70_THREAD_STACK_SIZE
+	int "Thread stack size"
+	depends on ICM42X70_TRIGGER_OWN_THREAD
+	default 1024
+	help
+	  Stack size of thread used by the driver to handle interrupts.
+
+endif # ICM42X70
diff --git a/drivers/sensor/tdk/icm42x70/icm42670.c b/drivers/sensor/tdk/icm42x70/icm42670.c
new file mode 100644
index 00000000000..5da95ed7cf2
--- /dev/null
+++ b/drivers/sensor/tdk/icm42x70/icm42670.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2025 TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "icm42670.h"
+
+#include <zephyr/drivers/sensor/icm42x70.h>
+#include <zephyr/sys/byteorder.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(ICM42670, CONFIG_SENSOR_LOG_LEVEL);
+
+static uint32_t convert_gyr_fs_to_bitfield(uint32_t val, uint16_t *fs)
+{
+	uint32_t bitfield = 0;
+
+	if (val < 500 && val >= 250) {
+		bitfield = GYRO_CONFIG0_FS_SEL_250dps;
+		*fs = 250;
+	} else if (val < 1000 && val >= 500) {
+		bitfield = GYRO_CONFIG0_FS_SEL_500dps;
+		*fs = 500;
+	} else if (val < 2000 && val >= 1000) {
+		bitfield = GYRO_CONFIG0_FS_SEL_1000dps;
+		*fs = 1000;
+	} else if (val == 2000) {
+		bitfield = GYRO_CONFIG0_FS_SEL_2000dps;
+		*fs = 2000;
+	}
+	return bitfield;
+}
+
+static int icm42670_set_gyro_odr(struct icm42x70_data *drv_data, const struct sensor_value *val)
+{
+	if (val->val1 <= 1600 && val->val1 >= 12) {
+		if (drv_data->gyro_hz == 0) {
+			inv_imu_set_gyro_frequency(
+				&drv_data->driver,
+				convert_freq_to_bitfield(val->val1, &drv_data->gyro_hz));
+			inv_imu_enable_gyro_low_noise_mode(&drv_data->driver);
+		} else {
+			inv_imu_set_gyro_frequency(
+				&drv_data->driver,
+				convert_freq_to_bitfield(val->val1, &drv_data->gyro_hz));
+		}
+	} else if (val->val1 == 0) {
+		inv_imu_disable_gyro(&drv_data->driver);
+		drv_data->gyro_hz = val->val1;
+	} else {
+		LOG_ERR("Incorrect sampling value");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int icm42670_set_gyro_fs(struct icm42x70_data *drv_data, const struct sensor_value *val)
+{
+	int32_t val_dps = sensor_rad_to_degrees(val);
+
+	if (val_dps > 2000 || val_dps < 250) {
+		LOG_ERR("Incorrect fullscale value");
+		return -EINVAL;
+	}
+	inv_imu_set_gyro_fsr(&drv_data->driver,
+			     convert_gyr_fs_to_bitfield(val_dps, &drv_data->gyro_fs));
+	LOG_DBG("Set gyro fullscale to: %d dps", drv_data->gyro_fs);
+	return 0;
+}
+
+int icm42670_gyro_config(struct icm42x70_data *drv_data, enum sensor_attribute attr,
+			 const struct sensor_value *val)
+{
+	if (attr == SENSOR_ATTR_SAMPLING_FREQUENCY) {
+		icm42670_set_gyro_odr(drv_data, val);
+
+	} else if (attr == SENSOR_ATTR_FULL_SCALE) {
+		icm42670_set_gyro_fs(drv_data, val);
+
+	} else if ((enum sensor_attribute_icm42x70)attr == SENSOR_ATTR_BW_FILTER_LPF) {
+		if (val->val1 > 180) {
+			LOG_ERR("Incorrect low pass filter bandwidth value");
+			return -EINVAL;
+		}
+		inv_imu_set_gyro_ln_bw(&drv_data->driver, convert_ln_bw_to_bitfield(val->val1));
+
+	} else {
+		LOG_ERR("Unsupported attribute");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+void icm42670_convert_gyro(struct sensor_value *val, int16_t raw_val, uint16_t fs)
+{
+	int64_t conv_val;
+
+	/* 16 bit gyroscope. 2^15 bits represent the range in degrees/s */
+	/* see datasheet section 3.1 for details */
+	conv_val = ((int64_t)raw_val * fs * SENSOR_PI) / (INT16_MAX * 180U);
+
+	val->val1 = conv_val / 1000000;
+	val->val2 = conv_val % 1000000;
+}
+
+int icm42670_sample_fetch_gyro(const struct device *dev)
+{
+	struct icm42x70_data *data = dev->data;
+	uint8_t buffer[GYRO_DATA_SIZE];
+
+	int res = inv_imu_read_reg(&data->driver, GYRO_DATA_X1, GYRO_DATA_SIZE, buffer);
+
+	if (res) {
+		return res;
+	}
+
+	data->gyro_x = (int16_t)sys_get_be16(&buffer[0]);
+	data->gyro_y = (int16_t)sys_get_be16(&buffer[2]);
+	data->gyro_z = (int16_t)sys_get_be16(&buffer[4]);
+
+	return 0;
+}
+
+uint16_t convert_bitfield_to_gyr_fs(uint8_t bitfield)
+{
+	uint16_t gyr_fs = 0;
+
+	if (bitfield == GYRO_CONFIG0_FS_SEL_250dps) {
+		gyr_fs = 250;
+	} else if (bitfield == GYRO_CONFIG0_FS_SEL_500dps) {
+		gyr_fs = 500;
+	} else if (bitfield == GYRO_CONFIG0_FS_SEL_1000dps) {
+		gyr_fs = 1000;
+	} else if (bitfield == GYRO_CONFIG0_FS_SEL_2000dps) {
+		gyr_fs = 2000;
+	}
+	return gyr_fs;
+}
diff --git a/drivers/sensor/tdk/icm42x70/icm42670.h b/drivers/sensor/tdk/icm42x70/icm42670.h
new file mode 100644
index 00000000000..abff4cf478e
--- /dev/null
+++ b/drivers/sensor/tdk/icm42x70/icm42670.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025 TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_ICM42670_H_
+#define ZEPHYR_DRIVERS_SENSOR_ICM42670_H_
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/kernel.h>
+
+#include "icm42x70.h"
+
+int icm42670_gyro_config(struct icm42x70_data *drv_data, enum sensor_attribute attr,
+			 const struct sensor_value *val);
+void icm42670_convert_gyro(struct sensor_value *val, int16_t raw_val, uint16_t fs);
+int icm42670_sample_fetch_gyro(const struct device *dev);
+uint16_t convert_bitfield_to_gyr_fs(uint8_t bitfield);
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_ICM42670_H_ */
diff --git a/drivers/sensor/tdk/icm42x70/icm42x70.c b/drivers/sensor/tdk/icm42x70/icm42x70.c
new file mode 100644
index 00000000000..4e52c83d923
--- /dev/null
+++ b/drivers/sensor/tdk/icm42x70/icm42x70.c
@@ -0,0 +1,1032 @@
+/*
+ * Copyright (c) 2024 TDK Invensense
+ * Copyright (c) 2022 Esco Medical ApS
+ * Copyright (c) 2020 TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/init.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/pm/device.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/drivers/sensor/icm42x70.h>
+#include <zephyr/drivers/sensor/tdk_apex.h>
+
+#include "icm42x70.h"
+#include "icm42x70_trigger.h"
+#include "icm42670.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(ICM42X70, CONFIG_SENSOR_LOG_LEVEL);
+
+/* Convert DT enum to sensor ODR selection */
+#define ICM42X70_CONVERT_ENUM_TO_ODR_POS (4)
+
+/* Maximum bytes to read/write on ICM42X70 serial interface */
+#define ICM42X70_SERIAL_INTERFACE_MAX_READ  (1024 * 32)
+#define ICM42X70_SERIAL_INTERFACE_MAX_WRITE (1024 * 32)
+
+static inline int icm42x70_reg_read(const struct device *dev, uint8_t reg, uint8_t *buf,
+				    uint32_t size)
+{
+	const struct icm42x70_config *cfg = dev->config;
+
+	return cfg->bus_io->read(&cfg->bus, reg, buf, size);
+}
+
+static inline int inv_io_hal_read_reg(struct inv_imu_serif *serif, uint8_t reg, uint8_t *rbuffer,
+				      uint32_t rlen)
+{
+	return icm42x70_reg_read(serif->context, reg, rbuffer, rlen);
+}
+
+static inline int icm42x70_reg_write(const struct device *dev, uint8_t reg, const uint8_t *buf,
+				     uint32_t size)
+{
+	const struct icm42x70_config *cfg = dev->config;
+
+	return cfg->bus_io->write(&cfg->bus, reg, (uint8_t *)buf, size);
+}
+
+static inline int inv_io_hal_write_reg(struct inv_imu_serif *serif, uint8_t reg,
+				       const uint8_t *wbuffer, uint32_t wlen)
+{
+	return icm42x70_reg_write(serif->context, reg, wbuffer, wlen);
+}
+
+void inv_imu_sleep_us(uint32_t us)
+{
+	k_sleep(K_USEC(us));
+}
+
+uint64_t inv_imu_get_time_us(void)
+{
+	/* returns the elapsed time since the system booted, in milliseconds */
+	return k_uptime_get() * 1000;
+}
+
+static uint16_t convert_dt_enum_to_freq(uint8_t val)
+{
+	uint16_t freq;
+
+	switch (val) {
+	case 0:
+		freq = 0;
+		break;
+	case 1:
+		freq = 1600;
+		break;
+	case 2:
+		freq = 800;
+		break;
+	case 3:
+		freq = 400;
+		break;
+	case 4:
+		freq = 200;
+		break;
+	case 5:
+		freq = 100;
+		break;
+	case 6:
+		freq = 50;
+		break;
+	case 7:
+		freq = 25;
+		break;
+	case 8:
+		freq = 12;
+		break;
+	case 9:
+		freq = 6;
+		break;
+	case 10:
+		freq = 3;
+		break;
+	case 11:
+		freq = 1;
+		break;
+	default:
+		freq = 0;
+		break;
+	}
+	return freq;
+}
+
+uint32_t convert_freq_to_bitfield(uint32_t val, uint16_t *freq)
+{
+	uint32_t odr_bitfield = 0;
+
+	if (val < 3 && val >= 1) {
+		odr_bitfield = ACCEL_CONFIG0_ODR_1_5625_HZ; /*(= GYRO_CONFIG0_ODR_1_5625_HZ )*/
+		*freq = 1;
+	} else if (val < 6 && val >= 3) {
+		odr_bitfield = ACCEL_CONFIG0_ODR_3_125_HZ; /*(= GYRO_CONFIG0_ODR_3_125_HZ )*/
+		*freq = 3;
+	} else if (val < 12 && val >= 6) {
+		odr_bitfield = ACCEL_CONFIG0_ODR_6_25_HZ; /*(= GYRO_CONFIG0_ODR_6_25_HZ )*/
+		*freq = 6;
+	} else if (val < 25 && val >= 12) {
+		odr_bitfield = ACCEL_CONFIG0_ODR_12_5_HZ; /*(= GYRO_CONFIG0_ODR_12_5_HZ )*/
+		*freq = 12;
+	} else if (val < 50 && val >= 25) {
+		odr_bitfield = ACCEL_CONFIG0_ODR_25_HZ; /*(= GYRO_CONFIG0_ODR_25_HZ )*/
+		*freq = 25;
+	} else if (val < 100 && val >= 50) {
+		odr_bitfield = ACCEL_CONFIG0_ODR_50_HZ; /*(GYRO_CONFIG0_ODR_50_HZ)*/
+		*freq = 50;
+	} else if (val < 200 && val >= 100) {
+		odr_bitfield = ACCEL_CONFIG0_ODR_100_HZ; /*(= GYRO_CONFIG0_ODR_100_HZ )*/
+		*freq = 100;
+	} else if (val < 400 && val >= 200) {
+		odr_bitfield = ACCEL_CONFIG0_ODR_200_HZ; /*(= GYRO_CONFIG0_ODR_200_HZ )*/
+		*freq = 200;
+	} else if (val < 800 && val >= 400) {
+		odr_bitfield = ACCEL_CONFIG0_ODR_400_HZ; /*(= GYRO_CONFIG0_ODR_400_HZ )*/
+		*freq = 400;
+	} else if (val < 1600 && val >= 800) {
+		odr_bitfield = ACCEL_CONFIG0_ODR_800_HZ; /*(= GYRO_CONFIG0_ODR_800_HZ )*/
+		*freq = 800;
+	} else if (val == 1600) {
+		odr_bitfield = ACCEL_CONFIG0_ODR_1600_HZ; /*(= GYRO_CONFIG0_ODR_1600_HZ )*/
+		*freq = 1600;
+	}
+	return odr_bitfield;
+}
+
+static uint32_t convert_acc_fs_to_bitfield(uint32_t val, uint8_t *fs)
+{
+	uint32_t bitfield = 0;
+
+	if (val < 4 && val >= 2) {
+		bitfield = ACCEL_CONFIG0_FS_SEL_2g;
+		*fs = 2;
+	} else if (val < 8 && val >= 4) {
+		bitfield = ACCEL_CONFIG0_FS_SEL_4g;
+		*fs = 4;
+	} else if (val < 16 && val >= 8) {
+		bitfield = ACCEL_CONFIG0_FS_SEL_8g;
+		*fs = 8;
+	} else if (val == 16) {
+		bitfield = ACCEL_CONFIG0_FS_SEL_16g;
+		*fs = 16;
+	}
+	return bitfield;
+}
+
+uint32_t convert_ln_bw_to_bitfield(uint32_t val)
+{
+	uint32_t bitfield = 0xFF;
+
+	if (val < 25 && val >= 16) {
+		bitfield = ACCEL_CONFIG1_ACCEL_FILT_BW_16; /* (= GYRO_CONFIG1_GYRO_FILT_BW_16) */
+	} else if (val < 34 && val >= 25) {
+		bitfield = ACCEL_CONFIG1_ACCEL_FILT_BW_25; /* (= GYRO_CONFIG1_GYRO_FILT_BW_25) */
+	} else if (val < 53 && val >= 34) {
+		bitfield = ACCEL_CONFIG1_ACCEL_FILT_BW_34; /* (= GYRO_CONFIG1_GYRO_FILT_BW_34) */
+	} else if (val < 73 && val >= 53) {
+		bitfield = ACCEL_CONFIG1_ACCEL_FILT_BW_53; /* (= GYRO_CONFIG1_GYRO_FILT_BW_53) */
+	} else if (val < 121 && val >= 73) {
+		bitfield = ACCEL_CONFIG1_ACCEL_FILT_BW_73; /* (= GYRO_CONFIG1_GYRO_FILT_BW_73) */
+	} else if (val < 180 && val >= 121) {
+		bitfield = ACCEL_CONFIG1_ACCEL_FILT_BW_121; /* (= GYRO_CONFIG1_GYRO_FILT_BW_121) */
+	} else if (val == 180) {
+		bitfield = ACCEL_CONFIG1_ACCEL_FILT_BW_180; /* (= GYRO_CONFIG1_GYRO_FILT_BW_180) */
+	} else if (val == 0) {
+		bitfield = ACCEL_CONFIG1_ACCEL_FILT_BW_NO_FILTER;
+		/*(= GYRO_CONFIG1_GYRO_FILT_BW_NO_FILTER)*/
+	}
+	return bitfield;
+}
+
+static uint32_t convert_lp_avg_to_bitfield(uint32_t val)
+{
+	uint32_t bitfield = 0xFF;
+
+	if (val < 4 && val >= 2) {
+		bitfield = ACCEL_CONFIG1_ACCEL_FILT_AVG_2;
+	} else if (val < 8 && val >= 4) {
+		bitfield = ACCEL_CONFIG1_ACCEL_FILT_AVG_4;
+	} else if (val < 16 && val >= 8) {
+		bitfield = ACCEL_CONFIG1_ACCEL_FILT_AVG_8;
+	} else if (val < 32 && val >= 16) {
+		bitfield = ACCEL_CONFIG1_ACCEL_FILT_AVG_16;
+	} else if (val < 64 && val >= 32) {
+		bitfield = ACCEL_CONFIG1_ACCEL_FILT_AVG_32;
+	} else if (val == 64) {
+		bitfield = ACCEL_CONFIG1_ACCEL_FILT_AVG_64;
+	}
+	return bitfield;
+}
+
+static uint8_t convert_bitfield_to_acc_fs(uint8_t bitfield)
+{
+	uint8_t acc_fs = 0;
+
+	if (bitfield == ACCEL_CONFIG0_FS_SEL_2g) {
+		acc_fs = 2;
+	} else if (bitfield == ACCEL_CONFIG0_FS_SEL_4g) {
+		acc_fs = 4;
+	} else if (bitfield == ACCEL_CONFIG0_FS_SEL_8g) {
+		acc_fs = 8;
+	} else if (bitfield == ACCEL_CONFIG0_FS_SEL_16g) {
+		acc_fs = 16;
+	}
+	return acc_fs;
+}
+
+static int icm42x70_set_accel_power_mode(struct icm42x70_data *drv_data,
+					 const struct sensor_value *val)
+{
+	if ((val->val1 == ICM42X70_LOW_POWER_MODE) &&
+	    (drv_data->accel_pwr_mode != ICM42X70_LOW_POWER_MODE)) {
+		if (drv_data->accel_hz != 0) {
+			if (drv_data->accel_hz <= 400) {
+				inv_imu_enable_accel_low_power_mode(&drv_data->driver);
+			} else {
+				LOG_ERR("Not supported ATTR value");
+				return -EINVAL;
+			}
+		}
+		drv_data->accel_pwr_mode = val->val1;
+	} else if ((val->val1 == ICM42X70_LOW_NOISE_MODE) &&
+		   (drv_data->accel_pwr_mode != ICM42X70_LOW_NOISE_MODE)) {
+		if (drv_data->accel_hz != 0) {
+			if (drv_data->accel_hz >= 12) {
+				inv_imu_enable_accel_low_noise_mode(&drv_data->driver);
+			} else {
+				LOG_ERR("Not supported ATTR value");
+				return -EINVAL;
+			}
+		}
+		drv_data->accel_pwr_mode = val->val1;
+	} else {
+		LOG_ERR("Not supported ATTR value");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int icm42x70_set_accel_odr(struct icm42x70_data *drv_data, const struct sensor_value *val)
+{
+	if (val->val1 <= 1600 && val->val1 >= 1) {
+		if (drv_data->accel_hz == 0) {
+			inv_imu_set_accel_frequency(
+				&drv_data->driver,
+				convert_freq_to_bitfield(val->val1, &drv_data->accel_hz));
+			if (drv_data->accel_pwr_mode == ICM42X70_LOW_POWER_MODE) {
+				inv_imu_enable_accel_low_power_mode(&drv_data->driver);
+			} else if (drv_data->accel_pwr_mode == ICM42X70_LOW_NOISE_MODE) {
+				inv_imu_enable_accel_low_noise_mode(&drv_data->driver);
+			}
+		} else {
+			inv_imu_set_accel_frequency(
+				&drv_data->driver,
+				convert_freq_to_bitfield(val->val1, &drv_data->accel_hz));
+		}
+	} else if (val->val1 == 0) {
+		inv_imu_disable_accel(&drv_data->driver);
+		drv_data->accel_hz = val->val1;
+	} else {
+		LOG_ERR("Incorrect sampling value");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int icm42x70_set_accel_fs(struct icm42x70_data *drv_data, const struct sensor_value *val)
+{
+	if (val->val1 > 16 || val->val1 < 2) {
+		LOG_ERR("Incorrect fullscale value");
+		return -EINVAL;
+	}
+	inv_imu_set_accel_fsr(&drv_data->driver,
+			      convert_acc_fs_to_bitfield(val->val1, &drv_data->accel_fs));
+	LOG_DBG("Set accel full scale to: %d G", drv_data->accel_fs);
+	return 0;
+}
+
+static int icm42x70_accel_config(struct icm42x70_data *drv_data, enum sensor_attribute attr,
+				 const struct sensor_value *val)
+{
+	if (attr == SENSOR_ATTR_CONFIGURATION) {
+		icm42x70_set_accel_power_mode(drv_data, val);
+
+	} else if (attr == SENSOR_ATTR_SAMPLING_FREQUENCY) {
+		icm42x70_set_accel_odr(drv_data, val);
+
+	} else if (attr == SENSOR_ATTR_FULL_SCALE) {
+		icm42x70_set_accel_fs(drv_data, val);
+
+	} else if ((enum sensor_attribute_icm42x70)attr == SENSOR_ATTR_BW_FILTER_LPF) {
+		if (val->val1 > 180) {
+			LOG_ERR("Incorrect low pass filter bandwidth value");
+			return -EINVAL;
+		}
+		inv_imu_set_accel_ln_bw(&drv_data->driver, convert_ln_bw_to_bitfield(val->val1));
+
+	} else if ((enum sensor_attribute_icm42x70)attr == SENSOR_ATTR_AVERAGING) {
+		if (val->val1 > 64 || val->val1 < 2) {
+			LOG_ERR("Incorrect averaging filter value");
+			return -EINVAL;
+		}
+		inv_imu_set_accel_lp_avg(&drv_data->driver, convert_lp_avg_to_bitfield(val->val1));
+	} else {
+		LOG_ERR("Unsupported attribute");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int icm42x70_sensor_init(const struct device *dev)
+{
+	struct icm42x70_data *data = dev->data;
+	const struct icm42x70_config *config = dev->config;
+	int err = 0;
+
+	/* Initialize serial interface and device */
+	data->serif.context = (struct device *)dev;
+	data->serif.read_reg = inv_io_hal_read_reg;
+	data->serif.write_reg = inv_io_hal_write_reg;
+	data->serif.max_read = ICM42X70_SERIAL_INTERFACE_MAX_READ;
+	data->serif.max_write = ICM42X70_SERIAL_INTERFACE_MAX_WRITE;
+	data->serif.serif_type = config->serif_type;
+	err = inv_imu_init(&data->driver, &data->serif, NULL);
+	if (err < 0) {
+		LOG_ERR("Init failed: %d", err);
+		return err;
+	}
+
+	err = inv_imu_get_who_am_i(&data->driver, &data->chip_id);
+	if (err < 0) {
+		LOG_ERR("ID read failed: %d", err);
+		return err;
+	}
+
+	if (data->chip_id != data->imu_whoami) {
+		LOG_ERR("invalid WHO_AM_I value, was 0x%x but expected 0x%x for %s", data->chip_id,
+			data->imu_whoami, data->imu_name);
+		return -ENOTSUP;
+	}
+
+	LOG_DBG("\"%s\" %s OK", dev->name, data->imu_name);
+	return 0;
+}
+
+static int icm42x70_turn_on_sensor(const struct device *dev)
+{
+	struct icm42x70_data *data = dev->data;
+	const struct icm42x70_config *cfg = dev->config;
+	int err = 0;
+
+	err = inv_imu_set_accel_fsr(&data->driver,
+				    (cfg->accel_fs << ACCEL_CONFIG0_ACCEL_UI_FS_SEL_POS));
+	data->accel_fs =
+		convert_bitfield_to_acc_fs((cfg->accel_fs << ACCEL_CONFIG0_ACCEL_UI_FS_SEL_POS));
+	if ((err < 0) || (data->accel_fs == 0)) {
+		LOG_ERR("Failed to configure accel FSR");
+		return -EIO;
+	}
+	LOG_DBG("Set accel full scale to: %d G", data->accel_fs);
+
+#if CONFIG_USE_EMD_ICM42670
+	if ((data->imu_whoami == INV_ICM42670P_WHOAMI) ||
+	    (data->imu_whoami == INV_ICM42670S_WHOAMI)) {
+		err = inv_imu_set_gyro_fsr(&data->driver,
+					   (cfg->gyro_fs << GYRO_CONFIG0_GYRO_UI_FS_SEL_POS));
+		data->gyro_fs = convert_bitfield_to_gyr_fs(
+			(cfg->gyro_fs << GYRO_CONFIG0_GYRO_UI_FS_SEL_POS));
+		if ((err < 0) || (data->gyro_fs == 0)) {
+			LOG_ERR("Failed to configure gyro FSR");
+			return -EIO;
+		}
+		LOG_DBG("Set gyro full scale to: %d dps", data->gyro_fs);
+	}
+#endif
+
+	err = inv_imu_set_accel_lp_avg(&data->driver,
+				       (cfg->accel_avg << ACCEL_CONFIG1_ACCEL_UI_AVG_POS));
+	err |= inv_imu_set_accel_ln_bw(&data->driver,
+				       (cfg->accel_filt_bw << ACCEL_CONFIG1_ACCEL_UI_FILT_BW_POS));
+#if CONFIG_USE_EMD_ICM42670
+	if ((data->imu_whoami == INV_ICM42670P_WHOAMI) ||
+	    (data->imu_whoami == INV_ICM42670S_WHOAMI)) {
+		err |= inv_imu_set_gyro_ln_bw(
+			&data->driver, (cfg->gyro_filt_bw << GYRO_CONFIG1_GYRO_UI_FILT_BW_POS));
+	}
+#endif
+	if (err < 0) {
+		LOG_ERR("Failed to configure filtering.");
+		return -EIO;
+	}
+
+	if (cfg->accel_hz != 0) {
+		err |= inv_imu_set_accel_frequency(
+			&data->driver, cfg->accel_hz + ICM42X70_CONVERT_ENUM_TO_ODR_POS);
+		if ((cfg->accel_pwr_mode == ICM42X70_LOW_NOISE_MODE) &&
+		    (convert_dt_enum_to_freq(cfg->accel_hz) >= 12)) {
+			err |= inv_imu_enable_accel_low_noise_mode(&data->driver);
+		} else if ((cfg->accel_pwr_mode == ICM42X70_LOW_POWER_MODE) &&
+			   (convert_dt_enum_to_freq(cfg->accel_hz) <= 400)) {
+			err |= inv_imu_enable_accel_low_power_mode(&data->driver);
+		} else {
+			LOG_ERR("Not supported power mode value");
+		}
+	}
+#if CONFIG_USE_EMD_ICM42670
+	if ((data->imu_whoami == INV_ICM42670P_WHOAMI) ||
+	    (data->imu_whoami == INV_ICM42670S_WHOAMI)) {
+		if (cfg->gyro_hz != 0) {
+			err |= inv_imu_set_gyro_frequency(
+				&data->driver, cfg->gyro_hz + ICM42X70_CONVERT_ENUM_TO_ODR_POS);
+			err |= inv_imu_enable_gyro_low_noise_mode(&data->driver);
+		}
+	}
+#endif
+	if (err < 0) {
+		LOG_ERR("Failed to configure ODR.");
+		return -EIO;
+	}
+
+	data->accel_pwr_mode = cfg->accel_pwr_mode;
+	data->accel_hz = convert_dt_enum_to_freq(cfg->accel_hz);
+#if CONFIG_USE_EMD_ICM42670
+	if ((data->imu_whoami == INV_ICM42670P_WHOAMI) ||
+	    (data->imu_whoami == INV_ICM42670S_WHOAMI)) {
+		data->gyro_hz = convert_dt_enum_to_freq(cfg->gyro_hz);
+	}
+#endif
+
+	/*
+	 * Accelerometer sensor need at least 10ms startup time
+	 * Gyroscope sensor need at least 30ms startup time
+	 */
+	k_msleep(100);
+
+	return 0;
+}
+
+static void icm42x70_convert_accel(struct sensor_value *val, int16_t raw_val, uint16_t fs)
+{
+	int64_t conv_val;
+
+	/* 16 bit accelerometer. 2^15 bits represent the range in G */
+	/* see datasheet section 3.2 for details */
+	conv_val = (int64_t)raw_val * SENSOR_G * fs / INT16_MAX;
+
+	val->val1 = conv_val / 1000000;
+	val->val2 = conv_val % 1000000;
+}
+
+static void icm42x70_convert_temp(struct sensor_value *val, int16_t raw_val)
+{
+	int64_t conv_val;
+
+	/* see datasheet section 15.9 for details */
+	conv_val = 25 * 1000000 + ((int64_t)raw_val * 1000000 / 2);
+	val->val1 = conv_val / 1000000;
+	val->val2 = conv_val % 1000000;
+}
+
+static int icm42x70_channel_get(const struct device *dev, enum sensor_channel chan,
+				struct sensor_value *val)
+{
+	int res = 0;
+	struct icm42x70_data *data = dev->data;
+#ifdef CONFIG_TDK_APEX
+	const struct icm42x70_config *cfg = dev->config;
+#endif
+
+	icm42x70_lock(dev);
+
+	if (chan == SENSOR_CHAN_ACCEL_XYZ) {
+		icm42x70_convert_accel(&val[0], data->accel_x, data->accel_fs);
+		icm42x70_convert_accel(&val[1], data->accel_y, data->accel_fs);
+		icm42x70_convert_accel(&val[2], data->accel_z, data->accel_fs);
+	} else if (chan == SENSOR_CHAN_ACCEL_X) {
+		icm42x70_convert_accel(val, data->accel_x, data->accel_fs);
+	} else if (chan == SENSOR_CHAN_ACCEL_Y) {
+		icm42x70_convert_accel(val, data->accel_y, data->accel_fs);
+	} else if (chan == SENSOR_CHAN_ACCEL_Z) {
+		icm42x70_convert_accel(val, data->accel_z, data->accel_fs);
+#if CONFIG_USE_EMD_ICM42670
+	} else if ((chan == SENSOR_CHAN_GYRO_XYZ) && ((data->imu_whoami == INV_ICM42670P_WHOAMI) ||
+						      (data->imu_whoami == INV_ICM42670S_WHOAMI))) {
+		icm42670_convert_gyro(&val[0], data->gyro_x, data->gyro_fs);
+		icm42670_convert_gyro(&val[1], data->gyro_y, data->gyro_fs);
+		icm42670_convert_gyro(&val[2], data->gyro_z, data->gyro_fs);
+	} else if ((chan == SENSOR_CHAN_GYRO_X) && ((data->imu_whoami == INV_ICM42670P_WHOAMI) ||
+						    (data->imu_whoami == INV_ICM42670S_WHOAMI))) {
+		icm42670_convert_gyro(val, data->gyro_x, data->gyro_fs);
+	} else if ((chan == SENSOR_CHAN_GYRO_Y) && ((data->imu_whoami == INV_ICM42670P_WHOAMI) ||
+						    (data->imu_whoami == INV_ICM42670S_WHOAMI))) {
+		icm42670_convert_gyro(val, data->gyro_y, data->gyro_fs);
+	} else if ((chan == SENSOR_CHAN_GYRO_Z) && ((data->imu_whoami == INV_ICM42670P_WHOAMI) ||
+						    (data->imu_whoami == INV_ICM42670S_WHOAMI))) {
+		icm42670_convert_gyro(val, data->gyro_z, data->gyro_fs);
+#endif
+	} else if (chan == SENSOR_CHAN_DIE_TEMP) {
+		icm42x70_convert_temp(val, data->temp);
+#ifdef CONFIG_TDK_APEX
+	} else if ((enum sensor_channel_tdk_apex)chan == SENSOR_CHAN_APEX_MOTION) {
+		if (cfg->apex == TDK_APEX_PEDOMETER) {
+			val[0].val1 = data->pedometer_cnt;
+			val[1].val1 = data->pedometer_activity;
+			icm42x70_apex_pedometer_cadence_convert(&val[2], data->pedometer_cadence,
+								data->dmp_odr_hz);
+		} else if (cfg->apex == TDK_APEX_WOM) {
+			val[0].val1 = (data->apex_status & ICM42X70_APEX_STATUS_MASK_WOM_X) ? 1 : 0;
+			val[1].val1 = (data->apex_status & ICM42X70_APEX_STATUS_MASK_WOM_Y) ? 1 : 0;
+			val[2].val1 = (data->apex_status & ICM42X70_APEX_STATUS_MASK_WOM_Z) ? 1 : 0;
+		} else if ((cfg->apex == TDK_APEX_TILT) || (cfg->apex == TDK_APEX_SMD)) {
+			val[0].val1 = data->apex_status;
+		}
+#endif
+	} else {
+		res = -ENOTSUP;
+	}
+
+	icm42x70_unlock(dev);
+
+	return res;
+}
+
+#ifdef CONFIG_ICM42X70_TRIGGER
+static int icm42x70_fetch_from_fifo(const struct device *dev)
+{
+	struct icm42x70_data *data = dev->data;
+	int status = 0;
+	uint8_t int_status;
+	uint16_t packet_size = FIFO_HEADER_SIZE + FIFO_ACCEL_DATA_SIZE + FIFO_GYRO_DATA_SIZE +
+			       FIFO_TEMP_DATA_SIZE + FIFO_TS_FSYNC_SIZE;
+	uint16_t fifo_idx = 0;
+
+	/* Ensure data ready status bit is set */
+	status |= inv_imu_read_reg(&data->driver, INT_STATUS, 1, &int_status);
+	if (status != 0) {
+		return status;
+	}
+
+	if ((int_status & INT_STATUS_FIFO_THS_INT_MASK) ||
+	    (int_status & INT_STATUS_FIFO_FULL_INT_MASK)) {
+		uint16_t packet_count;
+
+		/* Make sure RCOSC is enabled to guarrantee FIFO read */
+		status |= inv_imu_switch_on_mclk(&data->driver);
+
+		/* Read FIFO frame count */
+		status |= inv_imu_get_frame_count(&data->driver, &packet_count);
+
+		/* Check for error */
+		if (status != 0) {
+			status |= inv_imu_switch_off_mclk(&data->driver);
+			return status;
+		}
+
+		/* Read FIFO data */
+		status |= inv_imu_read_reg(&data->driver, FIFO_DATA, packet_size * packet_count,
+					   (uint8_t *)&data->driver.fifo_data);
+
+		/* Check for error */
+		if (status != 0) {
+			status |= inv_imu_reset_fifo(&data->driver);
+			status |= inv_imu_switch_off_mclk(&data->driver);
+			return status;
+		}
+
+		for (uint16_t i = 0; i < packet_count; i++) {
+			inv_imu_sensor_event_t event;
+
+			status |= inv_imu_decode_fifo_frame(
+				&data->driver, &data->driver.fifo_data[fifo_idx], &event);
+			fifo_idx += packet_size;
+
+			/* Check for error */
+			if (status != 0) {
+				status |= inv_imu_reset_fifo(&data->driver);
+				status |= inv_imu_switch_off_mclk(&data->driver);
+				return status;
+			}
+
+			if (event.sensor_mask & (1 << INV_SENSOR_ACCEL)) {
+				data->accel_x = event.accel[0];
+				data->accel_y = event.accel[1];
+				data->accel_z = event.accel[2];
+			}
+#if CONFIG_USE_EMD_ICM42670
+			if ((data->imu_whoami == INV_ICM42670P_WHOAMI) ||
+			    (data->imu_whoami == INV_ICM42670S_WHOAMI)) {
+				if (event.sensor_mask & (1 << INV_SENSOR_GYRO)) {
+					data->gyro_x = event.gyro[0];
+					data->gyro_y = event.gyro[1];
+					data->gyro_z = event.gyro[2];
+				}
+			}
+#endif
+			if (event.sensor_mask & (1 << INV_SENSOR_TEMPERATURE)) {
+				data->temp = event.temperature;
+			}
+			/*
+			 * TODO use the sensor streaming interface with RTIO to handle multiple
+			 * samples in FIFO
+			 */
+
+		} /* end of FIFO read for loop */
+
+		status |= inv_imu_switch_off_mclk(&data->driver);
+		if (status < 0) {
+			return status;
+		}
+	} /*else: FIFO threshold was not reached and FIFO was not full */
+
+	return 0;
+}
+#endif
+
+#ifndef CONFIG_ICM42X70_TRIGGER
+static int icm42x70_sample_fetch_accel(const struct device *dev)
+{
+	struct icm42x70_data *data = dev->data;
+	uint8_t buffer[ACCEL_DATA_SIZE];
+
+	int res = inv_imu_read_reg(&data->driver, ACCEL_DATA_X1, ACCEL_DATA_SIZE, buffer);
+
+	if (res) {
+		return res;
+	}
+
+	data->accel_x = (int16_t)sys_get_be16(&buffer[0]);
+	data->accel_y = (int16_t)sys_get_be16(&buffer[2]);
+	data->accel_z = (int16_t)sys_get_be16(&buffer[4]);
+
+	return 0;
+}
+
+static int icm42x70_sample_fetch_temp(const struct device *dev)
+{
+	struct icm42x70_data *data = dev->data;
+	uint8_t buffer[TEMP_DATA_SIZE];
+
+	int res = inv_imu_read_reg(&data->driver, TEMP_DATA1, TEMP_DATA_SIZE, buffer);
+
+	if (res) {
+		return res;
+	}
+
+	data->temp = (int16_t)sys_get_be16(&buffer[0]);
+
+	return 0;
+}
+
+static int icm42x70_fetch_from_registers(const struct device *dev, enum sensor_channel chan)
+{
+	struct icm42x70_data *data = dev->data;
+	int res = 0;
+	uint8_t int_status;
+
+	LOG_DBG("Fetch from reg");
+
+	icm42x70_lock(dev);
+
+	/* Ensure data ready status bit is set */
+	int err = inv_imu_read_reg(&data->driver, INT_STATUS_DRDY, 1, &int_status);
+
+	if (int_status & INT_STATUS_DRDY_DATA_RDY_INT_MASK) {
+		switch (chan) {
+		case SENSOR_CHAN_ALL:
+			err |= icm42x70_sample_fetch_accel(dev);
+#if CONFIG_USE_EMD_ICM42670
+			if ((data->imu_whoami == INV_ICM42670P_WHOAMI) ||
+			    (data->imu_whoami == INV_ICM42670S_WHOAMI)) {
+				err |= icm42670_sample_fetch_gyro(dev);
+			}
+#endif
+			err |= icm42x70_sample_fetch_temp(dev);
+			break;
+		case SENSOR_CHAN_ACCEL_XYZ:
+		case SENSOR_CHAN_ACCEL_X:
+		case SENSOR_CHAN_ACCEL_Y:
+		case SENSOR_CHAN_ACCEL_Z:
+			err |= icm42x70_sample_fetch_accel(dev);
+			break;
+#if CONFIG_USE_EMD_ICM42670
+		case SENSOR_CHAN_GYRO_XYZ:
+		case SENSOR_CHAN_GYRO_X:
+		case SENSOR_CHAN_GYRO_Y:
+		case SENSOR_CHAN_GYRO_Z:
+			if ((data->imu_whoami == INV_ICM42670P_WHOAMI) ||
+			    (data->imu_whoami == INV_ICM42670S_WHOAMI)) {
+				err |= icm42670_sample_fetch_gyro(dev);
+			} else {
+				res = -ENOTSUP;
+			}
+			break;
+#endif
+		case SENSOR_CHAN_DIE_TEMP:
+			err |= icm42x70_sample_fetch_temp(dev);
+			break;
+		default:
+			res = -ENOTSUP;
+			break;
+		}
+	}
+
+	icm42x70_unlock(dev);
+
+	if (err < 0) {
+		res = -EIO;
+	}
+	return res;
+}
+#endif
+
+static int icm42x70_sample_fetch(const struct device *dev, enum sensor_channel chan)
+{
+#if CONFIG_USE_EMD_ICM42670
+	struct icm42x70_data *data = dev->data;
+#endif
+	int status = -ENOTSUP;
+
+	icm42x70_lock(dev);
+
+#ifdef CONFIG_TDK_APEX
+	if ((enum sensor_channel_tdk_apex)chan == SENSOR_CHAN_APEX_MOTION) {
+		status = icm42x70_apex_fetch_from_dmp(dev);
+	}
+#endif
+
+	if ((chan == SENSOR_CHAN_ALL) || SENSOR_CHANNEL_IS_ACCEL(chan) ||
+#if CONFIG_USE_EMD_ICM42670
+	    (SENSOR_CHANNEL_IS_GYRO(chan) && ((data->imu_whoami == INV_ICM42670P_WHOAMI) ||
+					      (data->imu_whoami == INV_ICM42670S_WHOAMI))) ||
+#endif
+	    (chan == SENSOR_CHAN_DIE_TEMP)) {
+#ifdef CONFIG_ICM42X70_TRIGGER
+		status = icm42x70_fetch_from_fifo(dev);
+#else
+		status = icm42x70_fetch_from_registers(dev, chan);
+#endif
+	}
+
+	icm42x70_unlock(dev);
+	return status;
+}
+
+static int icm42x70_attr_set(const struct device *dev, enum sensor_channel chan,
+			     enum sensor_attribute attr, const struct sensor_value *val)
+{
+	struct icm42x70_data *drv_data = dev->data;
+
+	__ASSERT_NO_MSG(val != NULL);
+
+	icm42x70_lock(dev);
+
+	if ((enum sensor_channel_tdk_apex)chan == SENSOR_CHAN_APEX_MOTION) {
+		if (attr == SENSOR_ATTR_CONFIGURATION) {
+#ifdef CONFIG_TDK_APEX
+			if (val->val1 == TDK_APEX_PEDOMETER) {
+				icm42x70_apex_enable(&drv_data->driver);
+				icm42x70_apex_enable_pedometer(dev, &drv_data->driver);
+			} else if (val->val1 == TDK_APEX_TILT) {
+				icm42x70_apex_enable(&drv_data->driver);
+				icm42x70_apex_enable_tilt(&drv_data->driver);
+			} else if (val->val1 == TDK_APEX_SMD) {
+				icm42x70_apex_enable(&drv_data->driver);
+				icm42x70_apex_enable_smd(&drv_data->driver);
+			} else if (val->val1 == TDK_APEX_WOM) {
+				icm42x70_apex_enable_wom(&drv_data->driver);
+			} else {
+				LOG_ERR("Not supported ATTR value");
+			}
+#endif
+		} else {
+			LOG_ERR("Not supported ATTR");
+			return -EINVAL;
+		}
+	} else if (SENSOR_CHANNEL_IS_ACCEL(chan)) {
+		icm42x70_accel_config(drv_data, attr, val);
+#if CONFIG_USE_EMD_ICM42670
+	} else if ((SENSOR_CHANNEL_IS_GYRO(chan)) &&
+		   ((drv_data->imu_whoami == INV_ICM42670P_WHOAMI) ||
+		    (drv_data->imu_whoami == INV_ICM42670S_WHOAMI))) {
+		icm42670_gyro_config(drv_data, attr, val);
+#endif
+	} else {
+		LOG_ERR("Unsupported channel");
+		(void)drv_data;
+		return -EINVAL;
+	}
+
+	icm42x70_unlock(dev);
+
+	return 0;
+}
+
+static int icm42x70_attr_get(const struct device *dev, enum sensor_channel chan,
+			     enum sensor_attribute attr, struct sensor_value *val)
+{
+	const struct icm42x70_data *data = dev->data;
+	const struct icm42x70_config *cfg = dev->config;
+	int res = 0;
+
+	__ASSERT_NO_MSG(val != NULL);
+
+	icm42x70_lock(dev);
+
+	switch (chan) {
+	case SENSOR_CHAN_ACCEL_X:
+	case SENSOR_CHAN_ACCEL_Y:
+	case SENSOR_CHAN_ACCEL_Z:
+	case SENSOR_CHAN_ACCEL_XYZ:
+		if (attr == SENSOR_ATTR_SAMPLING_FREQUENCY) {
+			val->val1 = data->accel_hz;
+		} else if (attr == SENSOR_ATTR_FULL_SCALE) {
+			val->val1 = data->accel_fs;
+		} else {
+			LOG_ERR("Unsupported attribute");
+			res = -EINVAL;
+		}
+		break;
+#if CONFIG_USE_EMD_ICM42670
+	case SENSOR_CHAN_GYRO_X:
+	case SENSOR_CHAN_GYRO_Y:
+	case SENSOR_CHAN_GYRO_Z:
+	case SENSOR_CHAN_GYRO_XYZ:
+		if ((data->imu_whoami == INV_ICM42670P_WHOAMI) ||
+		    (data->imu_whoami == INV_ICM42670S_WHOAMI)) {
+			if (attr == SENSOR_ATTR_SAMPLING_FREQUENCY) {
+				val->val1 = data->gyro_hz;
+			} else if (attr == SENSOR_ATTR_FULL_SCALE) {
+				val->val1 = data->gyro_fs;
+			} else {
+				LOG_ERR("Unsupported attribute");
+				res = -EINVAL;
+			}
+		} else {
+			res = -EINVAL;
+		}
+		break;
+#endif
+	case SENSOR_CHAN_APEX_MOTION:
+		if (attr == SENSOR_ATTR_CONFIGURATION) {
+			val->val1 = cfg->apex;
+		}
+		break;
+
+	default:
+		LOG_ERR("Unsupported channel");
+		res = -EINVAL;
+		break;
+	}
+
+	icm42x70_unlock(dev);
+
+	return res;
+}
+
+static inline int icm42x70_bus_check(const struct device *dev)
+{
+	const struct icm42x70_config *cfg = dev->config;
+
+	return cfg->bus_io->check(&cfg->bus);
+}
+
+static int icm42x70_init(const struct device *dev)
+{
+	struct icm42x70_data *data = dev->data;
+	int res = 0;
+
+	if (icm42x70_bus_check(dev) < 0) {
+		LOG_ERR("bus check failed");
+		return -ENODEV;
+	}
+
+	data->accel_x = 0;
+	data->accel_y = 0;
+	data->accel_z = 0;
+#if CONFIG_USE_EMD_ICM42670
+	if ((data->imu_whoami == INV_ICM42670P_WHOAMI) ||
+	    (data->imu_whoami == INV_ICM42670S_WHOAMI)) {
+		data->gyro_x = 0;
+		data->gyro_y = 0;
+		data->gyro_z = 0;
+	}
+#endif
+	data->temp = 0;
+
+	if (icm42x70_sensor_init(dev)) {
+		LOG_ERR("could not initialize sensor");
+		return -EIO;
+	}
+
+#ifdef CONFIG_ICM42X70_TRIGGER
+	res |= icm42x70_trigger_enable_interrupt(dev);
+	res |= icm42x70_trigger_init(dev);
+	if (res < 0) {
+		LOG_ERR("Failed to initialize interrupt.");
+		return res;
+	}
+#endif
+
+	res |= icm42x70_turn_on_sensor(dev);
+
+	return res;
+}
+
+#ifndef CONFIG_ICM42X70_TRIGGER
+
+void icm42x70_lock(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+}
+
+void icm42x70_unlock(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+}
+
+#endif
+
+static DEVICE_API(sensor, icm42x70_driver_api) = {
+#ifdef CONFIG_ICM42X70_TRIGGER
+	.trigger_set = icm42x70_trigger_set,
+#endif
+	.sample_fetch = icm42x70_sample_fetch,
+	.channel_get = icm42x70_channel_get,
+	.attr_set = icm42x70_attr_set,
+	.attr_get = icm42x70_attr_get,
+};
+
+/* device defaults to spi mode 0/3 support */
+#define ICM42X70_SPI_CFG (SPI_WORD_SET(8) | SPI_TRANSFER_MSB | SPI_MODE_CPOL | SPI_MODE_CPHA)
+
+/* Initializes a common struct icm42x70_config */
+#define ICM42X70_CONFIG_COMMON(inst)                                                               \
+	IF_ENABLED(CONFIG_ICM42X70_TRIGGER,	\
+				(.gpio_int = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, {0}),))     \
+				    .accel_fs = DT_INST_ENUM_IDX(inst, accel_fs),                  \
+				    .accel_hz = DT_INST_ENUM_IDX(inst, accel_hz),                  \
+				    .accel_avg = DT_INST_ENUM_IDX(inst, accel_avg),                \
+				    .accel_filt_bw = DT_INST_ENUM_IDX(inst, accel_filt_bw_hz),     \
+				    .accel_pwr_mode = DT_INST_ENUM_IDX(inst, power_mode),          \
+				    .apex = DT_INST_ENUM_IDX(inst, apex),                          \
+				    .accel_pwr_mode = DT_INST_ENUM_IDX(inst, power_mode),          \
+				    .apex = DT_INST_ENUM_IDX(inst, apex),                          \
+		 IF_ENABLED(CONFIG_USE_EMD_ICM42670,                                       \
+				(.gyro_fs = DT_INST_ENUM_IDX(inst, gyro_fs),))                     \
+		 IF_ENABLED(CONFIG_USE_EMD_ICM42670,                                       \
+				(.gyro_hz = DT_INST_ENUM_IDX(inst, gyro_hz),))                     \
+		 IF_ENABLED(CONFIG_USE_EMD_ICM42670,                                       \
+				(.gyro_filt_bw = DT_INST_ENUM_IDX(inst, gyro_filt_bw_hz),))
+
+/* Initializes the bus members for an instance on a SPI bus. */
+#define ICM42X70_CONFIG_SPI(inst)                                                                  \
+	{.bus.spi = SPI_DT_SPEC_INST_GET(inst, ICM42X70_SPI_CFG, 0),                               \
+	 .bus_io = &icm42x70_bus_io_spi,                                                           \
+	 .serif_type = UI_SPI4,                                                                    \
+	 ICM42X70_CONFIG_COMMON(inst)}
+
+/* Initializes the bus members for an instance on an I2C bus. */
+#define ICM42X70_CONFIG_I2C(inst)                                                                  \
+	{.bus.i2c = I2C_DT_SPEC_INST_GET(inst),                                                    \
+	 .bus_io = &icm42x70_bus_io_i2c,                                                           \
+	 .serif_type = UI_I2C,                                                                     \
+	 ICM42X70_CONFIG_COMMON(inst)}
+
+/*
+ * Main instantiation macro, which selects the correct bus-specific
+ * instantiation macros for the instance.
+ */
+#define ICM42X70_DEFINE(inst, name, whoami)                                                        \
+	static struct icm42x70_data icm42x70_data_##inst = {                                       \
+		.imu_name = name,                                                                  \
+		.imu_whoami = whoami,                                                              \
+	};                                                                                         \
+	static const struct icm42x70_config icm42x70_config_##inst = \
+			COND_CODE_1(DT_INST_ON_BUS(inst, spi),	\
+			(ICM42X70_CONFIG_SPI(inst)),	\
+			(ICM42X70_CONFIG_I2C(inst)));             \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, icm42x70_init, NULL, &icm42x70_data_##inst,             \
+				     &icm42x70_config_##inst, POST_KERNEL,                         \
+				     CONFIG_SENSOR_INIT_PRIORITY, &icm42x70_driver_api);
+
+#define DT_DRV_COMPAT invensense_icm42670p
+#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
+DT_INST_FOREACH_STATUS_OKAY_VARGS(ICM42X70_DEFINE, INV_ICM42670P_STRING_ID, INV_ICM42670P_WHOAMI);
+#endif
+#undef DT_DRV_COMPAT
+
+#define DT_DRV_COMPAT invensense_icm42670s
+#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
+DT_INST_FOREACH_STATUS_OKAY_VARGS(ICM42X70_DEFINE, INV_ICM42670S_STRING_ID, INV_ICM42670S_WHOAMI);
+#endif
+#undef DT_DRV_COMPAT
+
+#define DT_DRV_COMPAT invensense_icm42370p
+#if DT_HAS_COMPAT_STATUS_OKAY(DT_DRV_COMPAT)
+DT_INST_FOREACH_STATUS_OKAY_VARGS(ICM42X70_DEFINE, INV_ICM42370P_STRING_ID, INV_ICM42370P_WHOAMI);
+#endif
diff --git a/drivers/sensor/tdk/icm42x70/icm42x70.h b/drivers/sensor/tdk/icm42x70/icm42x70.h
new file mode 100644
index 00000000000..10461268b2b
--- /dev/null
+++ b/drivers/sensor/tdk/icm42x70/icm42x70.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2024 TDK Invensense
+ * Copyright (c) 2022 Esco Medical ApS
+ * Copyright (c) 2020 TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_ICM42X70_H_
+#define ZEPHYR_DRIVERS_SENSOR_ICM42X70_H_
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/kernel.h>
+
+#include "imu/inv_imu_driver.h"
+#ifdef CONFIG_TDK_APEX
+#include "imu/inv_imu_apex.h"
+#endif
+
+union icm42x70_bus {
+#if CONFIG_SPI
+	struct spi_dt_spec spi;
+#endif
+#if CONFIG_I2C
+	struct i2c_dt_spec i2c;
+#endif
+};
+
+typedef int (*icm42x70_bus_check_fn)(const union icm42x70_bus *bus);
+typedef int (*icm42x70_reg_read_fn)(const union icm42x70_bus *bus, uint8_t reg, uint8_t *buf,
+				    uint32_t size);
+typedef int (*icm42x70_reg_write_fn)(const union icm42x70_bus *bus, uint8_t reg, uint8_t *buf,
+				     uint32_t size);
+
+struct icm42x70_bus_io {
+	icm42x70_bus_check_fn check;
+	icm42x70_reg_read_fn read;
+	icm42x70_reg_write_fn write;
+};
+
+#if CONFIG_SPI
+extern const struct icm42x70_bus_io icm42x70_bus_io_spi;
+#endif
+
+#if CONFIG_I2C
+extern const struct icm42x70_bus_io icm42x70_bus_io_i2c;
+#endif
+
+struct icm42x70_data {
+	struct inv_imu_serif serif;
+	struct inv_imu_device driver;
+	uint8_t imu_whoami;
+	char *imu_name;
+	uint8_t chip_id;
+	int32_t accel_x;
+	int32_t accel_y;
+	int32_t accel_z;
+	uint16_t accel_hz;
+	uint8_t accel_fs;
+	uint8_t accel_pwr_mode;
+#if CONFIG_USE_EMD_ICM42670
+	int32_t gyro_x;
+	int32_t gyro_y;
+	int32_t gyro_z;
+	uint16_t gyro_hz;
+	uint16_t gyro_fs;
+#endif
+	int32_t temp;
+#ifdef CONFIG_TDK_APEX
+	uint8_t dmp_odr_hz;
+	uint64_t pedometer_cnt;
+	uint8_t pedometer_activity;
+	uint8_t pedometer_cadence;
+	uint8_t apex_status;
+#endif
+
+#ifdef CONFIG_ICM42X70_TRIGGER
+	const struct device *dev;
+	struct gpio_callback gpio_cb;
+	sensor_trigger_handler_t data_ready_handler;
+	const struct sensor_trigger *data_ready_trigger;
+	struct k_mutex mutex;
+#endif
+#ifdef CONFIG_ICM42X70_TRIGGER_OWN_THREAD
+	K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_ICM42X70_THREAD_STACK_SIZE);
+	struct k_thread thread;
+	struct k_sem gpio_sem;
+#endif
+#ifdef CONFIG_ICM42X70_TRIGGER_GLOBAL_THREAD
+	struct k_work work;
+#endif
+};
+
+struct icm42x70_config {
+	union icm42x70_bus bus;
+	const struct icm42x70_bus_io *bus_io;
+	uint32_t serif_type;
+	struct gpio_dt_spec gpio_int;
+	uint8_t accel_fs;
+	uint16_t accel_hz;
+	uint16_t accel_avg;
+	uint16_t accel_filt_bw;
+#if CONFIG_USE_EMD_ICM42670
+	uint16_t gyro_fs;
+	uint16_t gyro_hz;
+	uint16_t gyro_filt_bw;
+#endif
+	uint8_t accel_pwr_mode;
+	uint8_t apex;
+};
+
+uint32_t convert_freq_to_bitfield(uint32_t val, uint16_t *freq);
+uint32_t convert_ln_bw_to_bitfield(uint32_t val);
+
+#ifdef CONFIG_TDK_APEX
+
+#define ICM42X70_APEX_STATUS_MASK_TILT  BIT(0)
+#define ICM42X70_APEX_STATUS_MASK_SMD   BIT(1)
+#define ICM42X70_APEX_STATUS_MASK_WOM_X BIT(2)
+#define ICM42X70_APEX_STATUS_MASK_WOM_Y BIT(3)
+#define ICM42X70_APEX_STATUS_MASK_WOM_Z BIT(4)
+
+int icm42x70_apex_enable(inv_imu_device_t *s);
+int icm42x70_apex_fetch_from_dmp(const struct device *dev);
+void icm42x70_apex_pedometer_cadence_convert(struct sensor_value *val, uint8_t raw_val,
+					     uint8_t dmp_odr_hz);
+int icm42x70_apex_enable_pedometer(const struct device *dev, inv_imu_device_t *s);
+int icm42x70_apex_enable_tilt(inv_imu_device_t *s);
+int icm42x70_apex_enable_smd(inv_imu_device_t *s);
+int icm42x70_apex_enable_wom(inv_imu_device_t *s);
+#endif
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_ICM42X70_H_ */
diff --git a/drivers/sensor/tdk/icm42x70/icm42x70_apex.c b/drivers/sensor/tdk/icm42x70/icm42x70_apex.c
new file mode 100644
index 00000000000..0761ff9db69
--- /dev/null
+++ b/drivers/sensor/tdk/icm42x70/icm42x70_apex.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2024 TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "icm42x70.h"
+#include "imu/inv_imu_apex.h"
+
+int icm42x70_apex_enable(inv_imu_device_t *s)
+{
+	int err = 0;
+	inv_imu_apex_parameters_t apex_inputs;
+	inv_imu_interrupt_parameter_t config_int = {(inv_imu_interrupt_value)0};
+
+	/* Disabling FIFO to avoid extra power consumption due to ALP config */
+	err |= inv_imu_configure_fifo(s, INV_IMU_FIFO_DISABLED);
+
+	/* Enable Pedometer, Tilt and SMD interrupts */
+	config_int.INV_STEP_DET = INV_IMU_ENABLE;
+	config_int.INV_STEP_CNT_OVFL = INV_IMU_ENABLE;
+	config_int.INV_TILT_DET = INV_IMU_ENABLE;
+	config_int.INV_SMD = INV_IMU_ENABLE;
+	err |= inv_imu_set_config_int1(s, &config_int);
+
+	/* Enable accelerometer to feed the APEX Pedometer algorithm */
+	err |= inv_imu_set_accel_frequency(s, ACCEL_CONFIG0_ODR_50_HZ);
+
+	/* Set 2x averaging, in order to minimize power consumption (16x by default) */
+	err |= inv_imu_set_accel_lp_avg(s, ACCEL_CONFIG1_ACCEL_FILT_AVG_2);
+	err |= inv_imu_enable_accel_low_power_mode(s);
+
+	/* Get the default parameters for the APEX features */
+	err |= inv_imu_apex_init_parameters_struct(s, &apex_inputs);
+
+	/*
+	 * Configure the power mode Normal mode.
+	 *  Avalaible mode : Low Power mode (WoM+Pedometer),
+	 *  configure the WoM to wake-up the DMP once it goes in power save mode
+	 */
+	apex_inputs.power_save = APEX_CONFIG0_DMP_POWER_SAVE_DIS;
+	err |= inv_imu_apex_configure_parameters(s, &apex_inputs);
+
+	/* Configure sampling frequency to 50Hz */
+	err |= inv_imu_apex_set_frequency(s, APEX_CONFIG1_DMP_ODR_50Hz);
+
+	return err;
+}
+
+int icm42x70_apex_fetch_from_dmp(const struct device *dev)
+{
+	struct icm42x70_data *data = dev->data;
+	int rc = 0;
+	uint8_t int_status2, int_status3;
+
+	/* Read APEX interrupt status */
+	rc |= inv_imu_read_reg(&data->driver, INT_STATUS2, 1, &int_status2);
+	rc |= inv_imu_read_reg(&data->driver, INT_STATUS3, 1, &int_status3);
+
+	/* Test Pedometer interrupt */
+	if (int_status3 & (INT_STATUS3_STEP_DET_INT_MASK)) {
+		inv_imu_apex_step_activity_t apex_pedometer;
+		uint8_t step_cnt_ovflw = 0;
+
+		if (int_status3 & INT_STATUS3_STEP_CNT_OVF_INT_MASK) {
+			step_cnt_ovflw = 1;
+		}
+
+		rc |= inv_imu_apex_get_data_activity(&data->driver, &apex_pedometer);
+
+		if (data->pedometer_cnt !=
+		    apex_pedometer.step_cnt + step_cnt_ovflw * (uint64_t)UINT16_MAX) {
+			data->pedometer_cnt =
+				apex_pedometer.step_cnt + step_cnt_ovflw * (uint64_t)UINT16_MAX;
+			data->pedometer_activity = apex_pedometer.activity_class;
+			data->pedometer_cadence = apex_pedometer.step_cadence;
+		} else {
+			/* Pedometer data processing */
+			rc = 1;
+		}
+	}
+	/* Test Tilt interrupt */
+	if (int_status3 & (INT_STATUS3_TILT_DET_INT_MASK)) {
+		data->apex_status = ICM42X70_APEX_STATUS_MASK_TILT;
+	}
+	/* Test SMD interrupt */
+	if ((int_status2 & (INT_STATUS2_SMD_INT_MASK)) || (rc != 0)) {
+		data->apex_status = ICM42X70_APEX_STATUS_MASK_SMD;
+	}
+	/* Test WOM interrupts */
+	if (int_status2 & (INT_STATUS2_WOM_X_INT_MASK | INT_STATUS2_WOM_Y_INT_MASK |
+			   INT_STATUS2_WOM_Z_INT_MASK)) {
+		data->apex_status = 0;
+		if (int_status2 & INT_STATUS2_WOM_X_INT_MASK) {
+			data->apex_status |= ICM42X70_APEX_STATUS_MASK_WOM_X;
+		}
+		if (int_status2 & INT_STATUS2_WOM_Y_INT_MASK) {
+			data->apex_status |= ICM42X70_APEX_STATUS_MASK_WOM_Y;
+		}
+		if (int_status2 & INT_STATUS2_WOM_Z_INT_MASK) {
+			data->apex_status |= ICM42X70_APEX_STATUS_MASK_WOM_Z;
+		}
+	}
+	return rc;
+}
+
+void icm42x70_apex_pedometer_cadence_convert(struct sensor_value *val, uint8_t raw_val,
+					     uint8_t dmp_odr_hz)
+{
+	int64_t conv_val;
+
+	/* Converting u6.2 */
+	conv_val = (int64_t)(dmp_odr_hz << 2) * 1000000 / (raw_val + (raw_val & 0x03));
+	val->val1 = conv_val / 1000000;
+	val->val2 = conv_val % 1000000;
+}
+
+int icm42x70_apex_enable_pedometer(const struct device *dev, inv_imu_device_t *s)
+{
+	struct icm42x70_data *data = dev->data;
+
+	data->dmp_odr_hz = 50;
+	/* Enable the pedometer */
+	return inv_imu_apex_enable_pedometer(s);
+}
+
+int icm42x70_apex_enable_tilt(inv_imu_device_t *s)
+{
+	/* Enable Tilt */
+	return inv_imu_apex_enable_tilt(s);
+}
+
+int icm42x70_apex_enable_smd(inv_imu_device_t *s)
+{
+	int rc = 0;
+
+	/* Enable SMD (and Pedometer as SMD uses it) */
+	rc |= inv_imu_apex_enable_pedometer(s);
+	rc |= inv_imu_apex_enable_smd(s);
+
+	return rc;
+}
+
+int icm42x70_apex_enable_wom(inv_imu_device_t *s)
+{
+	int rc = 0;
+	inv_imu_interrupt_parameter_t config_int = {(inv_imu_interrupt_value)0};
+
+	/*
+	 * Optimize power consumption:
+	 * - Disable FIFO usage.
+	 * - Disable data ready interrupt and enable WOM interrupts.
+	 * - Set 2X averaging.
+	 * - Use Low-Power mode at low frequency.
+	 */
+	rc |= inv_imu_configure_fifo(s, INV_IMU_FIFO_DISABLED);
+
+	config_int.INV_WOM_X = INV_IMU_ENABLE;
+	config_int.INV_WOM_Y = INV_IMU_ENABLE;
+	config_int.INV_WOM_Z = INV_IMU_ENABLE;
+	rc |= inv_imu_set_config_int1(s, &config_int);
+
+	rc |= inv_imu_set_accel_lp_avg(s, ACCEL_CONFIG1_ACCEL_FILT_AVG_2);
+	rc |= inv_imu_set_accel_frequency(s, ACCEL_CONFIG0_ODR_12_5_HZ);
+	rc |= inv_imu_enable_accel_low_power_mode(s);
+
+	/*
+	 * Configure WOM thresholds for each axis to 195 mg (Resolution 1g/256)
+	 * WOM threshold = 50 * 1000 / 256 = 195 mg
+	 * and enable WOM
+	 */
+	rc |= inv_imu_configure_wom(s, 50, 50, 50, WOM_CONFIG_WOM_INT_MODE_ORED,
+				    WOM_CONFIG_WOM_INT_DUR_1_SMPL);
+	rc |= inv_imu_enable_wom(s);
+
+	return rc;
+}
diff --git a/drivers/sensor/tdk/icm42x70/icm42x70_i2c.c b/drivers/sensor/tdk/icm42x70/icm42x70_i2c.c
new file mode 100644
index 00000000000..7f81c9bc8a7
--- /dev/null
+++ b/drivers/sensor/tdk/icm42x70/icm42x70_i2c.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2024 TDK Invensense
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Bus-specific functionality for ICM42X70 accessed via I2C.
+ */
+
+#include "icm42x70.h"
+
+#if CONFIG_I2C
+static int icm42x70_bus_check_i2c(const union icm42x70_bus *bus)
+{
+	return device_is_ready(bus->i2c.bus) ? 0 : -ENODEV;
+}
+
+static int icm42x70_reg_read_i2c(const union icm42x70_bus *bus, uint8_t reg, uint8_t *buf,
+				 uint32_t size)
+{
+	return i2c_burst_read_dt(&bus->i2c, reg, buf, size);
+}
+
+static int icm42x70_reg_write_i2c(const union icm42x70_bus *bus, uint8_t reg, uint8_t *buf,
+				  uint32_t size)
+{
+	return i2c_burst_write_dt(&bus->i2c, reg, buf, size);
+}
+
+const struct icm42x70_bus_io icm42x70_bus_io_i2c = {
+	.check = icm42x70_bus_check_i2c,
+	.read = icm42x70_reg_read_i2c,
+	.write = icm42x70_reg_write_i2c,
+};
+#endif /* CONFIG_I2C */
diff --git a/drivers/sensor/tdk/icm42x70/icm42x70_spi.c b/drivers/sensor/tdk/icm42x70/icm42x70_spi.c
new file mode 100644
index 00000000000..1e55efcd507
--- /dev/null
+++ b/drivers/sensor/tdk/icm42x70/icm42x70_spi.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2024 TDK Invensense
+ * Copyright (c) 2022 Esco Medical ApS
+ * Copyright (c) 2020 TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Bus-specific functionality for ICM42X70 accessed via SPI.
+ */
+
+#include "icm42x70.h"
+
+#if CONFIG_SPI
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(ICM42X70, CONFIG_SENSOR_LOG_LEVEL);
+
+static int icm42x70_bus_check_spi(const union icm42x70_bus *bus)
+{
+	return spi_is_ready_dt(&bus->spi) ? 0 : -ENODEV;
+}
+
+static int icm42x70_reg_read_spi(const union icm42x70_bus *bus, uint8_t start, uint8_t *buf,
+				 uint32_t size)
+
+{
+	uint8_t cmd[] = {(start | 0x80)};
+	const struct spi_buf tx_buf = {.buf = cmd, .len = sizeof(cmd)};
+	const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1};
+	struct spi_buf rx_buf[2];
+	const struct spi_buf_set rx = {.buffers = rx_buf, .count = ARRAY_SIZE(rx_buf)};
+	int ret;
+
+	rx_buf[0].buf = NULL;
+	rx_buf[0].len = 1;
+
+	rx_buf[1].len = size;
+	rx_buf[1].buf = buf;
+
+	ret = spi_transceive_dt(&bus->spi, &tx, &rx);
+	if (ret) {
+		LOG_ERR("spi_transceive FAIL %d\n", ret);
+		return ret;
+	}
+	return 0;
+}
+
+static int icm42x70_reg_write_spi(const union icm42x70_bus *bus, uint8_t reg, uint8_t *buf,
+				  uint32_t size)
+{
+	uint8_t cmd[] = {reg & 0x7F};
+	const struct spi_buf tx_buf[2] = {{.buf = cmd, .len = sizeof(cmd)},
+					  {.buf = buf, .len = size}};
+	const struct spi_buf_set tx = {.buffers = tx_buf, .count = 2};
+	int ret = spi_write_dt(&bus->spi, &tx);
+
+	if (ret) {
+		LOG_ERR("spi_write FAIL %d\n", ret);
+		return ret;
+	}
+	return 0;
+}
+
+const struct icm42x70_bus_io icm42x70_bus_io_spi = {
+	.check = icm42x70_bus_check_spi,
+	.read = icm42x70_reg_read_spi,
+	.write = icm42x70_reg_write_spi,
+};
+
+#endif /* CONFIG_SPI */
diff --git a/drivers/sensor/tdk/icm42x70/icm42x70_trigger.c b/drivers/sensor/tdk/icm42x70/icm42x70_trigger.c
new file mode 100644
index 00000000000..e6dfd0e33e1
--- /dev/null
+++ b/drivers/sensor/tdk/icm42x70/icm42x70_trigger.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2024 TDK Invensense
+ * Copyright (c) 2022 Esco Medical ApS
+ * Copyright (c) 2016 TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/sys/util.h>
+#include "icm42x70.h"
+#include "icm42x70_trigger.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(ICM42X70, CONFIG_SENSOR_LOG_LEVEL);
+
+static void icm42x70_gpio_callback(const struct device *dev, struct gpio_callback *cb,
+				   uint32_t pins)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(pins);
+
+	struct icm42x70_data *data = CONTAINER_OF(cb, struct icm42x70_data, gpio_cb);
+
+#if defined(CONFIG_ICM42X70_TRIGGER_OWN_THREAD)
+	k_sem_give(&data->gpio_sem);
+#elif defined(CONFIG_ICM42X70_TRIGGER_GLOBAL_THREAD)
+	k_work_submit(&data->work);
+#endif
+}
+
+static void icm42x70_thread_cb(const struct device *dev)
+{
+	struct icm42x70_data *data = dev->data;
+	const struct icm42x70_config *cfg = dev->config;
+
+	icm42x70_lock(dev);
+	gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_DISABLE);
+
+	if (data->data_ready_handler) {
+		data->data_ready_handler(dev, data->data_ready_trigger);
+	}
+
+	gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_EDGE_TO_ACTIVE);
+	icm42x70_unlock(dev);
+}
+
+#if defined(CONFIG_ICM42X70_TRIGGER_OWN_THREAD)
+
+static void icm42x70_thread(void *p1, void *p2, void *p3)
+{
+	ARG_UNUSED(p2);
+	ARG_UNUSED(p3);
+
+	struct icm42x70_data *data = p1;
+
+	while (1) {
+		k_sem_take(&data->gpio_sem, K_FOREVER);
+		icm42x70_thread_cb(data->dev);
+	}
+}
+#elif defined(CONFIG_ICM42X70_TRIGGER_GLOBAL_THREAD)
+
+static void icm42x70_work_handler(struct k_work *work)
+{
+	struct icm42x70_data *data = CONTAINER_OF(work, struct icm42x70_data, work);
+
+	icm42x70_thread_cb(data->dev);
+}
+
+#endif
+
+int icm42x70_trigger_set(const struct device *dev, const struct sensor_trigger *trig,
+			 sensor_trigger_handler_t handler)
+{
+	struct icm42x70_data *data = dev->data;
+	const struct icm42x70_config *cfg = dev->config;
+
+	if (!handler) {
+		return -EINVAL;
+	}
+
+	icm42x70_lock(dev);
+	gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_DISABLE);
+
+	if (trig->type == SENSOR_TRIG_DATA_READY) {
+		data->data_ready_handler = handler;
+		data->data_ready_trigger = trig;
+#ifdef CONFIG_TDK_APEX
+	} else if (trig->type == SENSOR_TRIG_MOTION) {
+		data->data_ready_handler = handler;
+		data->data_ready_trigger = trig;
+#endif
+	} else {
+		return -ENOTSUP;
+	}
+
+	icm42x70_unlock(dev);
+	gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_EDGE_TO_ACTIVE);
+
+	return 0;
+}
+
+int icm42x70_trigger_init(const struct device *dev)
+{
+	struct icm42x70_data *data = dev->data;
+	const struct icm42x70_config *cfg = dev->config;
+	int res = 0;
+
+	if (!cfg->gpio_int.port) {
+		LOG_ERR("trigger enabled but no interrupt gpio supplied");
+		return -ENODEV;
+	}
+
+	if (!gpio_is_ready_dt(&cfg->gpio_int)) {
+		LOG_ERR("gpio_int gpio not ready");
+		return -ENODEV;
+	}
+
+	data->dev = dev;
+	gpio_pin_configure_dt(&cfg->gpio_int, GPIO_INPUT);
+	gpio_init_callback(&data->gpio_cb, icm42x70_gpio_callback, BIT(cfg->gpio_int.pin));
+	res = gpio_add_callback(cfg->gpio_int.port, &data->gpio_cb);
+
+	if (res < 0) {
+		LOG_ERR("Failed to set gpio callback");
+		return res;
+	}
+
+	k_mutex_init(&data->mutex);
+
+#if defined(CONFIG_ICM42X70_TRIGGER_OWN_THREAD)
+	k_sem_init(&data->gpio_sem, 0, K_SEM_MAX_LIMIT);
+	k_thread_create(&data->thread, data->thread_stack, CONFIG_ICM42X70_THREAD_STACK_SIZE,
+			icm42x70_thread, data, NULL, NULL,
+			K_PRIO_COOP(CONFIG_ICM42X70_THREAD_PRIORITY), 0, K_NO_WAIT);
+#elif defined(CONFIG_ICM42X70_TRIGGER_GLOBAL_THREAD)
+	data->work.handler = icm42x70_work_handler;
+#endif
+
+	return gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_EDGE_TO_INACTIVE);
+}
+
+int icm42x70_trigger_enable_interrupt(const struct device *dev)
+{
+	struct icm42x70_data *data = dev->data;
+	int err = 0;
+	inv_imu_int1_pin_config_t int1_pin_config;
+	inv_imu_interrupt_parameter_t config_int = {(inv_imu_interrupt_value)0};
+
+	/* Set interrupt config */
+	int1_pin_config.int_polarity = INT_CONFIG_INT1_POLARITY_HIGH;
+	int1_pin_config.int_mode = INT_CONFIG_INT1_MODE_PULSED;
+	int1_pin_config.int_drive = INT_CONFIG_INT1_DRIVE_CIRCUIT_PP;
+	err |= inv_imu_set_pin_config_int1(&data->driver, &int1_pin_config);
+
+	config_int.INV_FIFO_THS = INV_IMU_ENABLE;
+	err |= inv_imu_set_config_int1(&data->driver, &config_int);
+
+	return err;
+}
+
+void icm42x70_lock(const struct device *dev)
+{
+	struct icm42x70_data *data = dev->data;
+
+	k_mutex_lock(&data->mutex, K_FOREVER);
+}
+
+void icm42x70_unlock(const struct device *dev)
+{
+	struct icm42x70_data *data = dev->data;
+
+	k_mutex_unlock(&data->mutex);
+}
diff --git a/drivers/sensor/tdk/icm42x70/icm42x70_trigger.h b/drivers/sensor/tdk/icm42x70/icm42x70_trigger.h
new file mode 100644
index 00000000000..bd89107ac4f
--- /dev/null
+++ b/drivers/sensor/tdk/icm42x70/icm42x70_trigger.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2022 Esco Medical ApS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_ICM42X70_TRIGGER_H_
+#define ZEPHYR_DRIVERS_SENSOR_ICM42X70_TRIGGER_H_
+
+#include <zephyr/device.h>
+
+/** implement the trigger_set sensor api function */
+int icm42x70_trigger_set(const struct device *dev, const struct sensor_trigger *trig,
+			 sensor_trigger_handler_t handler);
+
+/**
+ * @brief initialize the icm42x70 trigger system
+ *
+ * @param dev icm42x70 device pointer
+ * @return int 0 on success, negative error code otherwise
+ */
+int icm42x70_trigger_init(const struct device *dev);
+
+/**
+ * @brief enable the trigger gpio interrupt
+ *
+ * @param dev icm42x70 device pointer
+ * @return int 0 on success, negative error code otherwise
+ */
+int icm42x70_trigger_enable_interrupt(const struct device *dev);
+
+/**
+ * @brief lock access to the icm42x70 device driver
+ *
+ * @param dev icm42x70 device pointer
+ */
+void icm42x70_lock(const struct device *dev);
+
+/**
+ * @brief lock access to the icm42x70 device driver
+ *
+ * @param dev icm42x70 device pointer
+ */
+void icm42x70_unlock(const struct device *dev);
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_ICM42X70_TRIGGER_H_ */
diff --git a/drivers/sensor/tdk/icm45686/CMakeLists.txt b/drivers/sensor/tdk/icm45686/CMakeLists.txt
new file mode 100644
index 00000000000..084c244c0e3
--- /dev/null
+++ b/drivers/sensor/tdk/icm45686/CMakeLists.txt
@@ -0,0 +1,18 @@
+# Copyright (c) 2025 Croxel Inc.
+# Copyright (c) 2025 CogniPilot Foundation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+zephyr_library_include_directories(.)
+zephyr_library_sources(
+	icm45686.c
+)
+zephyr_library_sources_ifdef(CONFIG_SENSOR_ASYNC_API
+	icm45686_decoder.c
+)
+zephyr_library_sources_ifdef(CONFIG_ICM45686_TRIGGER
+	icm45686_trigger.c
+)
+zephyr_library_sources_ifdef(CONFIG_ICM45686_STREAM
+	icm45686_stream.c
+)
diff --git a/drivers/sensor/tdk/icm45686/Kconfig b/drivers/sensor/tdk/icm45686/Kconfig
new file mode 100644
index 00000000000..76e66fd6a72
--- /dev/null
+++ b/drivers/sensor/tdk/icm45686/Kconfig
@@ -0,0 +1,72 @@
+# Copyright (c) 2025 Croxel Inc.
+# Copyright (c) 2025 CogniPilot Foundation
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig ICM45686
+	bool "ICM45686 High-precision 6-Axis Motion Tracking Device"
+	default y
+	depends on DT_HAS_INVENSENSE_ICM45686_ENABLED
+	select SPI if $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM45686),spi)
+	select SPI_RTIO if $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM45686),spi)
+	select I2C if $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM45686),i2c)
+	select I2C_RTIO if $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM45686),i2c)
+	select I3C if $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM45686),i3c)
+	select I3C_RTIO if $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM45686),i3c)
+	help
+	  Enable driver for ICM45686 High-precision 6-axis motion
+	  tracking device.
+
+if ICM45686
+
+choice
+	prompt "Trigger mode"
+	default ICM45686_TRIGGER_GLOBAL_THREAD
+	help
+	  Specify the type of triggering to be used by the driver
+
+config ICM45686_TRIGGER_NONE
+	bool "No trigger"
+
+config ICM45686_TRIGGER_GLOBAL_THREAD
+	bool "Use global thread"
+	depends on GPIO
+	depends on $(dt_compat_any_has_prop,$(DT_COMPAT_INVENSENSE_ICM45686),int-gpios)
+	depends on !ICM45686_STREAM
+	select ICM45686_TRIGGER
+
+config ICM45686_TRIGGER_OWN_THREAD
+	bool "Use own thread"
+	depends on GPIO
+	depends on $(dt_compat_any_has_prop,$(DT_COMPAT_INVENSENSE_ICM45686),int-gpios)
+	depends on !ICM45686_STREAM
+	select ICM45686_TRIGGER
+
+endchoice
+
+config ICM45686_TRIGGER
+	bool
+
+config ICM45686_THREAD_PRIORITY
+	int "Own thread priority"
+	depends on ICM45686_TRIGGER_OWN_THREAD
+	default 10
+	help
+	  The priority of the thread used for handling triggers.
+
+config ICM45686_THREAD_STACK_SIZE
+	int "Own thread stack size"
+	depends on ICM45686_TRIGGER_OWN_THREAD
+	default 1024
+	help
+	  The thread stack size.
+
+config ICM45686_STREAM
+	bool "Streaming mode"
+	depends on GPIO || \
+		   $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM45686),i3c)
+	depends on $(dt_compat_any_has_prop,$(DT_COMPAT_INVENSENSE_ICM45686),int-gpios) || \
+		   $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICM45686),i3c)
+	help
+	  Enable streaming of sensor data.
+
+endif # ICM45686
diff --git a/drivers/sensor/tdk/icm45686/icm45686.c b/drivers/sensor/tdk/icm45686/icm45686.c
new file mode 100644
index 00000000000..90e992d4b97
--- /dev/null
+++ b/drivers/sensor/tdk/icm45686/icm45686.c
@@ -0,0 +1,477 @@
+/*
+ * Copyright (c) 2022 Intel Corporation
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT invensense_icm45686
+
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/i3c.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/rtio/rtio.h>
+
+#if defined(CONFIG_SENSOR_ASYNC_API)
+#include <zephyr/rtio/work.h>
+#endif /* CONFIG_SENSOR_ASYNC_API */
+
+#include "icm45686.h"
+#include "icm45686_reg.h"
+#include "icm45686_bus.h"
+#include "icm45686_decoder.h"
+#include "icm45686_trigger.h"
+#include "icm45686_stream.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(ICM45686, CONFIG_SENSOR_LOG_LEVEL);
+
+static inline int reg_write(const struct device *dev, uint8_t reg, uint8_t val)
+{
+	return icm45686_bus_write(dev, reg, &val, 1);
+}
+
+static inline int reg_read(const struct device *dev, uint8_t reg, uint8_t *val)
+{
+	return icm45686_bus_read(dev, reg, val, 1);
+}
+
+static int icm45686_sample_fetch(const struct device *dev,
+				 enum sensor_channel chan)
+{
+	int err;
+	struct icm45686_data *data = dev->data;
+	struct icm45686_encoded_data *edata = &data->edata;
+
+	if (chan != SENSOR_CHAN_ALL) {
+		return -ENOTSUP;
+	}
+
+	err = icm45686_bus_read(dev,
+				REG_ACCEL_DATA_X1_UI,
+				edata->payload.buf,
+				sizeof(edata->payload.buf));
+
+	LOG_HEXDUMP_DBG(edata->payload.buf,
+			sizeof(edata->payload.buf),
+			"ICM45686 data");
+
+	return err;
+}
+
+static int icm45686_channel_get(const struct device *dev,
+				enum sensor_channel chan,
+				struct sensor_value *val)
+{
+	struct icm45686_data *data = dev->data;
+
+	switch (chan) {
+	case SENSOR_CHAN_ACCEL_X:
+		icm45686_accel_ms(data->edata.header.accel_fs, data->edata.payload.accel.x, false,
+				  &val->val1, &val->val2);
+		break;
+	case SENSOR_CHAN_ACCEL_Y:
+		icm45686_accel_ms(data->edata.header.accel_fs, data->edata.payload.accel.y, false,
+				  &val->val1, &val->val2);
+		break;
+	case SENSOR_CHAN_ACCEL_Z:
+		icm45686_accel_ms(data->edata.header.accel_fs, data->edata.payload.accel.z, false,
+				  &val->val1, &val->val2);
+		break;
+	case SENSOR_CHAN_GYRO_X:
+		icm45686_gyro_rads(data->edata.header.gyro_fs, data->edata.payload.gyro.x, false,
+				   &val->val1, &val->val2);
+		break;
+	case SENSOR_CHAN_GYRO_Y:
+		icm45686_gyro_rads(data->edata.header.gyro_fs, data->edata.payload.gyro.y, false,
+				   &val->val1, &val->val2);
+		break;
+	case SENSOR_CHAN_GYRO_Z:
+		icm45686_gyro_rads(data->edata.header.gyro_fs, data->edata.payload.gyro.z, false,
+				   &val->val1, &val->val2);
+		break;
+	case SENSOR_CHAN_DIE_TEMP:
+		icm45686_temp_c(data->edata.payload.temp, &val->val1, &val->val2);
+		break;
+	case SENSOR_CHAN_ACCEL_XYZ:
+		icm45686_accel_ms(data->edata.header.accel_fs, data->edata.payload.accel.x, false,
+				  &val[0].val1, &val[0].val2);
+		icm45686_accel_ms(data->edata.header.accel_fs, data->edata.payload.accel.y, false,
+				  &val[1].val1, &val[1].val2);
+		icm45686_accel_ms(data->edata.header.accel_fs, data->edata.payload.accel.z, false,
+				  &val[2].val1, &val[2].val2);
+		break;
+	case SENSOR_CHAN_GYRO_XYZ:
+		icm45686_gyro_rads(data->edata.header.gyro_fs, data->edata.payload.gyro.x, false,
+				   &val->val1, &val->val2);
+		icm45686_gyro_rads(data->edata.header.gyro_fs, data->edata.payload.gyro.y, false,
+				   &val[1].val1, &val[1].val2);
+		icm45686_gyro_rads(data->edata.header.gyro_fs, data->edata.payload.gyro.z, false,
+				   &val[2].val1, &val[2].val2);
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_SENSOR_ASYNC_API)
+
+static void icm45686_complete_result(struct rtio *ctx,
+				     const struct rtio_sqe *sqe,
+				     void *arg)
+{
+	struct rtio_iodev_sqe *iodev_sqe = (struct rtio_iodev_sqe *)sqe->userdata;
+	struct rtio_cqe *cqe;
+	int err = 0;
+
+	do {
+		cqe = rtio_cqe_consume(ctx);
+		if (cqe != NULL) {
+			err = cqe->result;
+			rtio_cqe_release(ctx, cqe);
+		}
+	} while (cqe != NULL);
+
+	if (err) {
+		rtio_iodev_sqe_err(iodev_sqe, err);
+	} else {
+		rtio_iodev_sqe_ok(iodev_sqe, 0);
+	}
+
+	LOG_DBG("One-shot fetch completed");
+}
+
+static inline void icm45686_submit_one_shot(const struct device *dev,
+					    struct rtio_iodev_sqe *iodev_sqe)
+{
+	const struct sensor_read_config *cfg = iodev_sqe->sqe.iodev->data;
+	const struct sensor_chan_spec *const channels = cfg->channels;
+	const size_t num_channels = cfg->count;
+	uint32_t min_buf_len = sizeof(struct icm45686_encoded_data);
+	int err;
+	uint8_t *buf;
+	uint32_t buf_len;
+	struct icm45686_encoded_data *edata;
+	struct icm45686_data *data = dev->data;
+
+	err = rtio_sqe_rx_buf(iodev_sqe, min_buf_len, min_buf_len, &buf, &buf_len);
+	if (err != 0) {
+		LOG_ERR("Failed to get a read buffer of size %u bytes", min_buf_len);
+		rtio_iodev_sqe_err(iodev_sqe, err);
+		return;
+	}
+
+	edata = (struct icm45686_encoded_data *)buf;
+
+	err = icm45686_encode(dev, channels, num_channels, buf);
+	if (err != 0) {
+		LOG_ERR("Failed to encode sensor data");
+		rtio_iodev_sqe_err(iodev_sqe, err);
+		return;
+	}
+
+	struct rtio_sqe *write_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	struct rtio_sqe *read_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	struct rtio_sqe *complete_sqe = rtio_sqe_acquire(data->rtio.ctx);
+
+	if (!write_sqe || !read_sqe | !complete_sqe) {
+		LOG_ERR("Failed to acquire RTIO SQEs");
+		rtio_iodev_sqe_err(iodev_sqe, -ENOMEM);
+		return;
+	}
+
+	uint8_t val = REG_ACCEL_DATA_X1_UI | REG_READ_BIT;
+
+	rtio_sqe_prep_tiny_write(write_sqe,
+				 data->rtio.iodev,
+				 RTIO_PRIO_HIGH,
+				 &val,
+				 1,
+				NULL);
+	write_sqe->flags |= RTIO_SQE_TRANSACTION;
+
+	rtio_sqe_prep_read(read_sqe,
+			   data->rtio.iodev,
+			   RTIO_PRIO_HIGH,
+			   edata->payload.buf,
+			   sizeof(edata->payload.buf),
+			   NULL);
+	if (data->rtio.type == ICM45686_BUS_I2C) {
+		read_sqe->iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART;
+	} else if (data->rtio.type == ICM45686_BUS_I3C) {
+		read_sqe->iodev_flags |= RTIO_IODEV_I3C_STOP | RTIO_IODEV_I3C_RESTART;
+	}
+	read_sqe->flags |= RTIO_SQE_CHAINED;
+
+	rtio_sqe_prep_callback_no_cqe(complete_sqe,
+				      icm45686_complete_result,
+				      (void *)dev,
+				      iodev_sqe);
+
+	rtio_submit(data->rtio.ctx, 0);
+}
+
+static void icm45686_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
+{
+	const struct sensor_read_config *cfg = iodev_sqe->sqe.iodev->data;
+
+	if (!cfg->is_streaming) {
+		icm45686_submit_one_shot(dev, iodev_sqe);
+	} else if (IS_ENABLED(CONFIG_ICM45686_STREAM)) {
+		icm45686_stream_submit(dev, iodev_sqe);
+	} else {
+		LOG_ERR("Streaming not supported");
+		rtio_iodev_sqe_err(iodev_sqe, -ENOTSUP);
+	}
+}
+
+#endif /* CONFIG_SENSOR_ASYNC_API */
+
+static DEVICE_API(sensor, icm45686_driver_api) = {
+	.sample_fetch = icm45686_sample_fetch,
+	.channel_get = icm45686_channel_get,
+#if defined(CONFIG_ICM45686_TRIGGER)
+	.trigger_set = icm45686_trigger_set,
+#endif /* CONFIG_ICM45686_TRIGGER */
+#if defined(CONFIG_SENSOR_ASYNC_API)
+	.get_decoder = icm45686_get_decoder,
+	.submit = icm45686_submit,
+#endif /* CONFIG_SENSOR_ASYNC_API */
+};
+
+static int icm45686_init(const struct device *dev)
+{
+	struct icm45686_data *data = dev->data;
+	const struct icm45686_config *cfg = dev->config;
+	uint8_t read_val = 0;
+	uint8_t val;
+	int err;
+
+#if CONFIG_SPI_RTIO
+	if ((data->rtio.type == ICM45686_BUS_SPI) && !spi_is_ready_iodev(data->rtio.iodev)) {
+		LOG_ERR("Bus is not ready");
+		return -ENODEV;
+	}
+#endif
+#if CONFIG_I2C_RTIO
+	if ((data->rtio.type == ICM45686_BUS_I2C) && !i2c_is_ready_iodev(data->rtio.iodev)) {
+		LOG_ERR("Bus is not ready");
+		return -ENODEV;
+	}
+#endif
+
+	/** Soft-reset sensor to restore config to defaults,
+	 * unless it's already handled by I3C initialization.
+	 */
+	if (data->rtio.type != ICM45686_BUS_I3C) {
+		err = reg_write(dev, REG_MISC2, REG_MISC2_SOFT_RST(1));
+		if (err) {
+			LOG_ERR("Failed to write soft-reset: %d", err);
+			return err;
+		}
+		/* Wait for soft-reset to take effect */
+		k_sleep(K_MSEC(1));
+
+		/* A complete soft-reset clears the bit */
+		err = reg_read(dev, REG_MISC2, &read_val);
+		if (err) {
+			LOG_ERR("Failed to read soft-reset: %d", err);
+			return err;
+		}
+		if ((read_val & REG_MISC2_SOFT_RST(1)) != 0) {
+			LOG_ERR("Soft-reset command failed");
+			return -EIO;
+		}
+	}
+
+	/* Set Slew-rate to 10-ns typical, to allow proper SPI readouts */
+
+	err = reg_write(dev, REG_DRIVE_CONFIG0, REG_DRIVE_CONFIG0_SPI_SLEW(2));
+	if (err) {
+		LOG_ERR("Failed to write slew-rate: %d", err);
+		return err;
+	}
+	err = reg_write(dev, REG_DRIVE_CONFIG1, REG_DRIVE_CONFIG1_I3C_SLEW(3));
+	if (err) {
+		LOG_ERR("Failed to write slew-rate: %d", err);
+		return err;
+	}
+	/* Wait for register to take effect */
+	k_sleep(K_USEC(2));
+
+	/* Confirm ID Value matches */
+	err = reg_read(dev, REG_WHO_AM_I, &read_val);
+	if (err) {
+		LOG_ERR("Failed to read WHO_AM_I: %d", err);
+		return err;
+	}
+	if (read_val != WHO_AM_I_ICM45686) {
+		LOG_ERR("Unexpected WHO_AM_I value - expected: 0x%02x, actual: 0x%02x",
+			WHO_AM_I_ICM45686, read_val);
+		return -EIO;
+	}
+
+	/* Sensor Configuration */
+
+	val = REG_PWR_MGMT0_ACCEL_MODE(cfg->settings.accel.pwr_mode) |
+	      REG_PWR_MGMT0_GYRO_MODE(cfg->settings.gyro.pwr_mode);
+	err = reg_write(dev, REG_PWR_MGMT0, val);
+	if (err) {
+		LOG_ERR("Failed to write Power settings: %d", err);
+		return err;
+	}
+
+	val = REG_ACCEL_CONFIG0_ODR(cfg->settings.accel.odr) |
+	      REG_ACCEL_CONFIG0_FS(cfg->settings.accel.fs);
+	err = reg_write(dev, REG_ACCEL_CONFIG0, val);
+	if (err) {
+		LOG_ERR("Failed to write Accel settings: %d", err);
+		return err;
+	}
+
+	val = REG_GYRO_CONFIG0_ODR(cfg->settings.gyro.odr) |
+	      REG_GYRO_CONFIG0_FS(cfg->settings.gyro.fs);
+	err = reg_write(dev, REG_GYRO_CONFIG0, val);
+	if (err) {
+		LOG_ERR("Failed to write Gyro settings: %d", err);
+		return err;
+	}
+
+	/** Write Low-pass filter settings through indirect register access */
+	uint8_t gyro_lpf_write_array[] = REG_IREG_PREPARE_WRITE_ARRAY(
+						REG_IPREG_SYS1_OFFSET,
+						REG_IPREG_SYS1_REG_172,
+						REG_IPREG_SYS1_REG_172_GYRO_LPFBW_SEL(
+							cfg->settings.gyro.lpf));
+
+	err = icm45686_bus_write(dev, REG_IREG_ADDR_15_8, gyro_lpf_write_array,
+				 sizeof(gyro_lpf_write_array));
+	if (err) {
+		LOG_ERR("Failed to set Gyro BW settings: %d", err);
+		return err;
+	}
+
+	/** Wait before indirect register write is made effective
+	 * before proceeding with next one.
+	 */
+	k_sleep(K_MSEC(1));
+
+	uint8_t accel_lpf_write_array[] = REG_IREG_PREPARE_WRITE_ARRAY(
+						REG_IPREG_SYS2_OFFSET,
+						REG_IPREG_SYS2_REG_131,
+						REG_IPREG_SYS2_REG_131_ACCEL_LPFBW_SEL(
+							cfg->settings.accel.lpf));
+
+	err = icm45686_bus_write(dev, REG_IREG_ADDR_15_8, accel_lpf_write_array,
+				 sizeof(accel_lpf_write_array));
+	if (err) {
+		LOG_ERR("Failed to set Accel BW settings: %d", err);
+		return err;
+	}
+
+	if (IS_ENABLED(CONFIG_ICM45686_TRIGGER)) {
+		err = icm45686_trigger_init(dev);
+		if (err) {
+			LOG_ERR("Failed to initialize triggers: %d", err);
+			return err;
+		}
+	} else if (IS_ENABLED(CONFIG_ICM45686_STREAM)) {
+		err = icm45686_stream_init(dev);
+		if (err) {
+			LOG_ERR("Failed to initialize streaming: %d", err);
+			return err;
+		}
+	}
+
+	LOG_DBG("Init OK");
+
+	return 0;
+}
+
+#define ICM45686_VALID_ACCEL_ODR(pwr_mode, odr)							   \
+	((pwr_mode == ICM45686_DT_ACCEL_LP && odr >= ICM45686_DT_ACCEL_ODR_400) ||		   \
+	 (pwr_mode == ICM45686_DT_ACCEL_LN && odr <= ICM45686_DT_ACCEL_ODR_12_5) ||		   \
+	 (pwr_mode == ICM45686_DT_ACCEL_OFF))
+
+#define ICM45686_VALID_GYRO_ODR(pwr_mode, odr)							   \
+	((pwr_mode == ICM45686_DT_GYRO_LP && odr >= ICM45686_DT_GYRO_ODR_400) ||		   \
+	 (pwr_mode == ICM45686_DT_GYRO_LN && odr <= ICM45686_DT_GYRO_ODR_12_5) ||		   \
+	 (pwr_mode == ICM45686_DT_GYRO_OFF))
+
+#define ICM45686_INIT(inst)									   \
+												   \
+	RTIO_DEFINE(icm45686_rtio_ctx_##inst, 8, 8);						   \
+												   \
+	COND_CODE_1(DT_INST_ON_BUS(inst, i3c),							   \
+		    (I3C_DT_IODEV_DEFINE(icm45686_bus_##inst,					   \
+					 DT_DRV_INST(inst))),					   \
+	(COND_CODE_1(DT_INST_ON_BUS(inst, i2c),							   \
+		    (I2C_DT_IODEV_DEFINE(icm45686_bus_##inst,					   \
+					 DT_DRV_INST(inst))),					   \
+		    ())));									   \
+	COND_CODE_1(DT_INST_ON_BUS(inst, spi),							   \
+		    (SPI_DT_IODEV_DEFINE(icm45686_bus_##inst,					   \
+					 DT_DRV_INST(inst),					   \
+					 SPI_OP_MODE_MASTER | SPI_WORD_SET(8) | SPI_TRANSFER_MSB,  \
+					 0U)),							   \
+		    ());									   \
+												   \
+												   \
+	static const struct icm45686_config icm45686_cfg_##inst = {				   \
+		.settings = {									   \
+			.accel = {								   \
+				.pwr_mode = DT_INST_PROP(inst, accel_pwr_mode),			   \
+				.fs = DT_INST_PROP(inst, accel_fs),				   \
+				.odr = DT_INST_PROP(inst, accel_odr),				   \
+				.lpf = DT_INST_PROP_OR(inst, accel_lpf, 0),			   \
+			},									   \
+			.gyro = {								   \
+				.pwr_mode = DT_INST_PROP(inst, gyro_pwr_mode),			   \
+				.fs = DT_INST_PROP(inst, gyro_fs),				   \
+				.odr = DT_INST_PROP(inst, gyro_odr),				   \
+				.lpf = DT_INST_PROP_OR(inst, gyro_lpf, 0),			   \
+			},									   \
+			.fifo_watermark = DT_INST_PROP_OR(inst, fifo_watermark, 0),		   \
+		},										   \
+		.int_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, {0}),			   \
+	};											   \
+	static struct icm45686_data icm45686_data_##inst = {					   \
+		.edata.header = {								   \
+			.accel_fs = DT_INST_PROP(inst, accel_fs),				   \
+			.gyro_fs = DT_INST_PROP(inst, gyro_fs),					   \
+		},										   \
+		.rtio = {									   \
+			.iodev = &icm45686_bus_##inst,						   \
+			.ctx = &icm45686_rtio_ctx_##inst,					   \
+			COND_CODE_1(DT_INST_ON_BUS(inst, i3c),					   \
+				(.type = ICM45686_BUS_I3C,					   \
+				 .i3c.id = I3C_DEVICE_ID_DT_INST(inst),),			   \
+			(COND_CODE_1(DT_INST_ON_BUS(inst, i2c),					   \
+				(.type = ICM45686_BUS_I2C), ())))				   \
+			COND_CODE_1(DT_INST_ON_BUS(inst, spi),					   \
+				(.type = ICM45686_BUS_SPI), ())					   \
+		},										   \
+	};											   \
+												   \
+	/* Build-time settings verification: Inform the user of invalid settings at build time */  \
+	BUILD_ASSERT(ICM45686_VALID_ACCEL_ODR(DT_INST_PROP(inst, accel_pwr_mode),		   \
+					      DT_INST_PROP(inst, accel_odr)),			   \
+		     "Invalid accel ODR setting. Please check supported ODRs for LP and LN");	   \
+	BUILD_ASSERT(ICM45686_VALID_GYRO_ODR(DT_INST_PROP(inst, gyro_pwr_mode),			   \
+					     DT_INST_PROP(inst, gyro_odr)),			   \
+		     "Invalid gyro ODR setting. Please check supported ODRs for LP and LN");	   \
+												   \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, icm45686_init,					   \
+				     NULL,							   \
+				     &icm45686_data_##inst,					   \
+				     &icm45686_cfg_##inst,					   \
+				     POST_KERNEL,						   \
+				     CONFIG_SENSOR_INIT_PRIORITY,				   \
+				     &icm45686_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(ICM45686_INIT)
diff --git a/drivers/sensor/tdk/icm45686/icm45686.h b/drivers/sensor/tdk/icm45686/icm45686.h
new file mode 100644
index 00000000000..f26e1370a1c
--- /dev/null
+++ b/drivers/sensor/tdk/icm45686/icm45686.h
@@ -0,0 +1,287 @@
+/*
+ * Copyright (c) 2022 Intel Corporation
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_ICM45686_H_
+#define ZEPHYR_DRIVERS_SENSOR_ICM45686_H_
+
+#include <stdint.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/dt-bindings/sensor/icm45686.h>
+#include <zephyr/rtio/rtio.h>
+#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(invensense_icm45686, i3c)
+#include <zephyr/drivers/i3c.h>
+#endif
+
+struct icm45686_encoded_payload {
+	union {
+		uint8_t buf[14];
+		int16_t readings[7];
+		struct {
+			struct {
+				int16_t x;
+				int16_t y;
+				int16_t z;
+			} accel;
+			struct {
+				int16_t x;
+				int16_t y;
+				int16_t z;
+			} gyro;
+			int16_t temp;
+		} __attribute__((__packed__));
+	};
+};
+
+struct icm45686_encoded_fifo_payload {
+	union {
+		uint8_t buf[20];
+		struct {
+			uint8_t header;
+			struct {
+				int16_t x;
+				int16_t y;
+				int16_t z;
+			} accel;
+			struct {
+				int16_t x;
+				int16_t y;
+				int16_t z;
+			} gyro;
+			int16_t temp;
+			uint16_t timestamp;
+			struct {
+				uint8_t gyro_x : 4;
+				uint8_t accel_x : 4;
+				uint8_t gyro_y : 4;
+				uint8_t accel_y : 4;
+				uint8_t gyro_z : 4;
+				uint8_t accel_z : 4;
+			} lsb;
+		} __attribute__((__packed__));
+	};
+};
+
+struct icm45686_encoded_header {
+	uint64_t timestamp;
+	uint8_t accel_fs : 4;
+	uint8_t gyro_fs : 4;
+	uint8_t events : 3;
+	uint8_t channels : 7;
+	uint16_t fifo_count;
+};
+
+struct icm45686_encoded_data {
+	struct icm45686_encoded_header header;
+	union {
+		struct icm45686_encoded_payload payload;
+		struct icm45686_encoded_fifo_payload fifo_payload;
+	};
+};
+
+struct icm45686_triggers {
+		struct gpio_callback cb;
+		const struct device *dev;
+		struct k_mutex lock;
+		struct {
+			struct sensor_trigger trigger;
+			sensor_trigger_handler_t handler;
+		} entry;
+#if defined(CONFIG_ICM45686_TRIGGER_OWN_THREAD)
+		K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_ICM45686_THREAD_STACK_SIZE);
+		struct k_thread thread;
+		struct k_sem sem;
+#elif defined(CONFIG_ICM45686_TRIGGER_GLOBAL_THREAD)
+		struct k_work work;
+#endif
+};
+
+struct icm45686_stream {
+	struct gpio_callback cb;
+	const struct device *dev;
+	struct rtio_iodev_sqe *iodev_sqe;
+	atomic_t in_progress;
+	struct {
+		struct {
+			bool drdy : 1;
+			bool fifo_ths : 1;
+			bool fifo_full : 1;
+		} enabled;
+		struct {
+			enum sensor_stream_data_opt drdy;
+			enum sensor_stream_data_opt fifo_ths;
+			enum sensor_stream_data_opt fifo_full;
+		} opt;
+		bool drdy : 1;
+		bool fifo_ths : 1;
+		bool fifo_full : 1;
+	} settings;
+	struct {
+		uint64_t timestamp;
+		uint8_t int_status;
+		uint16_t fifo_count;
+		struct {
+			bool drdy : 1;
+			bool fifo_ths : 1;
+			bool fifo_full : 1;
+		} events;
+	} data;
+};
+
+enum icm45686_bus_type {
+	ICM45686_BUS_SPI,
+	ICM45686_BUS_I2C,
+	ICM45686_BUS_I3C,
+};
+
+struct icm45686_data {
+	struct {
+		struct rtio_iodev *iodev;
+		struct rtio *ctx;
+		enum icm45686_bus_type type;
+/** Required to support In-band Interrupts */
+#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(invensense_icm45686, i3c)
+		struct {
+			struct i3c_device_desc *desc;
+			const struct i3c_device_id id;
+		} i3c;
+#endif
+	} rtio;
+	/** Single-shot encoded data instance to support fetch/get API */
+	struct icm45686_encoded_data edata;
+#if defined(CONFIG_ICM45686_TRIGGER)
+	struct icm45686_triggers triggers;
+#elif defined(CONFIG_ICM45686_STREAM)
+	struct icm45686_stream stream;
+#endif /* CONFIG_ICM45686_TRIGGER */
+};
+
+struct icm45686_config {
+	struct {
+		struct {
+			uint8_t pwr_mode : 2;
+			uint8_t fs : 4;
+			uint8_t odr : 4;
+			uint8_t lpf : 3;
+		} accel;
+		struct {
+			uint8_t pwr_mode : 2;
+			uint8_t fs : 4;
+			uint8_t odr : 4;
+			uint8_t lpf : 3;
+		} gyro;
+		uint16_t fifo_watermark;
+	} settings;
+	struct gpio_dt_spec int_gpio;
+};
+
+static inline void icm45686_accel_ms(uint8_t fs,
+				     int32_t in,
+				     bool high_res,
+				     int32_t *out_ms,
+				     int32_t *out_ums)
+{
+	int64_t sensitivity;
+	uint64_t full_scale_range_lsb = high_res ? 524288 : 32768;
+
+	switch (fs) {
+	case ICM45686_DT_ACCEL_FS_32:
+		sensitivity = full_scale_range_lsb / 32;
+		break;
+	case ICM45686_DT_ACCEL_FS_16:
+		sensitivity = full_scale_range_lsb / 16;
+		break;
+	case ICM45686_DT_ACCEL_FS_8:
+		sensitivity = full_scale_range_lsb / 8;
+		break;
+	case ICM45686_DT_ACCEL_FS_4:
+		sensitivity = full_scale_range_lsb / 4;
+		break;
+	case ICM45686_DT_ACCEL_FS_2:
+		sensitivity = full_scale_range_lsb / 2;
+		break;
+	default:
+		CODE_UNREACHABLE;
+	}
+
+	/* Convert to micrometers/s^2 */
+	int64_t in_ms = in * SENSOR_G;
+
+	/* meters/s^2 whole values */
+	*out_ms = in_ms / (sensitivity * 1000000LL);
+
+	/* micrometers/s^2 */
+	*out_ums = (in_ms - (*out_ms * sensitivity * 1000000LL)) / sensitivity;
+}
+
+static inline void icm45686_gyro_rads(uint8_t fs,
+				      int32_t in,
+				      bool high_res,
+				      int32_t *out_rads,
+				      int32_t *out_urads)
+{
+	int64_t sensitivity_x10;
+	uint64_t full_scale_range_lsb = high_res ? 524288 : 32768;
+
+	switch (fs) {
+	case ICM45686_DT_GYRO_FS_4000:
+		sensitivity_x10 = full_scale_range_lsb * 10 / 4000;
+		break;
+	case ICM45686_DT_GYRO_FS_2000:
+		sensitivity_x10 = full_scale_range_lsb * 10 / 2000;
+		break;
+	case ICM45686_DT_GYRO_FS_1000:
+		sensitivity_x10 = full_scale_range_lsb * 10 / 1000;
+		break;
+	case ICM45686_DT_GYRO_FS_500:
+		sensitivity_x10 = full_scale_range_lsb * 10 / 500;
+		break;
+	case ICM45686_DT_GYRO_FS_250:
+		sensitivity_x10 = full_scale_range_lsb * 10 / 250;
+		break;
+	case ICM45686_DT_GYRO_FS_125:
+		sensitivity_x10 = full_scale_range_lsb * 10 / 125;
+		break;
+	case ICM45686_DT_GYRO_FS_62_5:
+		sensitivity_x10 = full_scale_range_lsb * 10 * 10 / 625;
+		break;
+	case ICM45686_DT_GYRO_FS_31_25:
+		sensitivity_x10 = full_scale_range_lsb * 10 * 100 / 3125;
+		break;
+	case ICM45686_DT_GYRO_FS_15_625:
+		sensitivity_x10 = full_scale_range_lsb * 10 * 1000 / 15625;
+		break;
+	default:
+		CODE_UNREACHABLE;
+	}
+
+	int64_t in10_rads = (int64_t)in * SENSOR_PI * 10LL;
+
+	/* Whole rad/s */
+	*out_rads = in10_rads / (sensitivity_x10 * 180LL * 1000000LL);
+
+	/* microrad/s */
+	*out_urads = (in10_rads - (*out_rads * sensitivity_x10 * 180LL * 1000000LL)) /
+		     (sensitivity_x10 * 180LL);
+}
+
+static inline void icm45686_temp_c(int32_t in, int32_t *out_c, uint32_t *out_uc)
+{
+	int64_t sensitivity = 13248; /* value equivalent for x100 1c */
+
+	/* Offset by 25 degrees Celsius */
+	int64_t in100 = (in * 100) + (25 * sensitivity);
+
+	/* Whole celsius */
+	*out_c = in100 / sensitivity;
+
+	/* Micro celsius */
+	*out_uc = ((in100 - (*out_c) * sensitivity) * INT64_C(1000000)) / sensitivity;
+}
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_ICM45686_H_ */
diff --git a/drivers/sensor/tdk/icm45686/icm45686_bus.h b/drivers/sensor/tdk/icm45686/icm45686_bus.h
new file mode 100644
index 00000000000..b56b7f1c3d3
--- /dev/null
+++ b/drivers/sensor/tdk/icm45686/icm45686_bus.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_ICM45686_BUS_H_
+#define ZEPHYR_DRIVERS_SENSOR_ICM45686_BUS_H_
+
+#include <stdint.h>
+#include <zephyr/rtio/rtio.h>
+
+#include "icm45686.h"
+#include "icm45686_reg.h"
+
+static inline int icm45686_bus_read(const struct device *dev,
+				    uint8_t reg,
+				    uint8_t *buf,
+				    uint16_t len)
+{
+	struct icm45686_data *data = dev->data;
+	struct rtio *ctx = data->rtio.ctx;
+	struct rtio_iodev *iodev = data->rtio.iodev;
+	struct rtio_sqe *write_sqe = rtio_sqe_acquire(ctx);
+	struct rtio_sqe *read_sqe = rtio_sqe_acquire(ctx);
+	struct rtio_cqe *cqe;
+	int err;
+
+	if (!write_sqe || !read_sqe) {
+		return -ENOMEM;
+	}
+
+	reg = reg | REG_READ_BIT;
+
+	rtio_sqe_prep_write(write_sqe, iodev, RTIO_PRIO_HIGH, &reg, 1, NULL);
+	write_sqe->flags |= RTIO_SQE_TRANSACTION;
+	rtio_sqe_prep_read(read_sqe, iodev, RTIO_PRIO_HIGH, buf, len, NULL);
+	if (data->rtio.type == ICM45686_BUS_I2C) {
+		read_sqe->iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART;
+	} else if (data->rtio.type == ICM45686_BUS_I3C) {
+		read_sqe->iodev_flags |= RTIO_IODEV_I3C_STOP | RTIO_IODEV_I3C_RESTART;
+	}
+
+	err = rtio_submit(ctx, 2);
+	if (err) {
+		return err;
+	}
+
+	do {
+		cqe = rtio_cqe_consume(ctx);
+		if (cqe != NULL) {
+			err = cqe->result;
+			rtio_cqe_release(ctx, cqe);
+		}
+	} while (cqe != NULL);
+
+	return err;
+}
+
+static inline int icm45686_bus_write(const struct device *dev,
+				     uint8_t reg,
+				     const uint8_t *buf,
+				     uint16_t len)
+{
+	struct icm45686_data *data = dev->data;
+	struct rtio *ctx = data->rtio.ctx;
+	struct rtio_iodev *iodev = data->rtio.iodev;
+	struct rtio_sqe *write_reg_sqe = rtio_sqe_acquire(ctx);
+	struct rtio_sqe *write_buf_sqe = rtio_sqe_acquire(ctx);
+	struct rtio_cqe *cqe;
+	int err;
+
+	if (!write_reg_sqe || !write_buf_sqe) {
+		return -ENOMEM;
+	}
+
+	rtio_sqe_prep_write(write_reg_sqe, iodev, RTIO_PRIO_HIGH, &reg, 1, NULL);
+	write_reg_sqe->flags |= RTIO_SQE_TRANSACTION;
+	rtio_sqe_prep_write(write_buf_sqe, iodev, RTIO_PRIO_HIGH, buf, len, NULL);
+	if (data->rtio.type == ICM45686_BUS_I2C) {
+		write_buf_sqe->iodev_flags |= RTIO_IODEV_I2C_STOP;
+	} else if (data->rtio.type == ICM45686_BUS_I3C) {
+		write_buf_sqe->iodev_flags |= RTIO_IODEV_I3C_STOP;
+	}
+
+	err = rtio_submit(ctx, 2);
+	if (err) {
+		return err;
+	}
+
+	do {
+		cqe = rtio_cqe_consume(ctx);
+		if (cqe != NULL) {
+			err = cqe->result;
+			rtio_cqe_release(ctx, cqe);
+		}
+	} while (cqe != NULL);
+
+	return err;
+}
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_ICM45686_BUS_H_ */
diff --git a/drivers/sensor/tdk/icm45686/icm45686_decoder.c b/drivers/sensor/tdk/icm45686/icm45686_decoder.c
new file mode 100644
index 00000000000..5905e8a68a2
--- /dev/null
+++ b/drivers/sensor/tdk/icm45686/icm45686_decoder.c
@@ -0,0 +1,591 @@
+/*
+ * Copyright (c) 2023 Google LLC
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/sensor_clock.h>
+
+#include "icm45686.h"
+#include "icm45686_reg.h"
+#include "icm45686_decoder.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(ICM45686_DECODER, CONFIG_SENSOR_LOG_LEVEL);
+
+#define DT_DRV_COMPAT invensense_icm45686
+
+static int icm45686_get_shift(enum sensor_channel channel,
+			      int accel_fs,
+			      int gyro_fs,
+			      int8_t *shift)
+{
+	switch (channel) {
+	case SENSOR_CHAN_ACCEL_XYZ:
+	case SENSOR_CHAN_ACCEL_X:
+	case SENSOR_CHAN_ACCEL_Y:
+	case SENSOR_CHAN_ACCEL_Z:
+		switch (accel_fs) {
+		case ICM45686_DT_ACCEL_FS_32:
+			*shift = 9;
+			return 0;
+		case ICM45686_DT_ACCEL_FS_16:
+			*shift = 8;
+			return 0;
+		case ICM45686_DT_ACCEL_FS_8:
+			*shift = 7;
+			return 0;
+		case ICM45686_DT_ACCEL_FS_4:
+			*shift = 6;
+			return 0;
+		case ICM45686_DT_ACCEL_FS_2:
+			*shift = 5;
+			return 0;
+		default:
+			return -EINVAL;
+		}
+	case SENSOR_CHAN_GYRO_XYZ:
+	case SENSOR_CHAN_GYRO_X:
+	case SENSOR_CHAN_GYRO_Y:
+	case SENSOR_CHAN_GYRO_Z:
+		switch (gyro_fs) {
+		case ICM45686_DT_GYRO_FS_4000:
+			*shift = 12;
+			return 0;
+		case ICM45686_DT_GYRO_FS_2000:
+			*shift = 11;
+			return 0;
+		case ICM45686_DT_GYRO_FS_1000:
+			*shift = 10;
+			return 0;
+		case ICM45686_DT_GYRO_FS_500:
+			*shift = 9;
+			return 0;
+		case ICM45686_DT_GYRO_FS_250:
+			*shift = 8;
+			return 0;
+		case ICM45686_DT_GYRO_FS_125:
+			*shift = 7;
+			return 0;
+		case ICM45686_DT_GYRO_FS_62_5:
+			*shift = 6;
+			return 0;
+		case ICM45686_DT_GYRO_FS_31_25:
+			*shift = 5;
+			return 0;
+		default:
+			return -EINVAL;
+		}
+	case SENSOR_CHAN_DIE_TEMP:
+		*shift = 9;
+		return 0;
+	default:
+		return -EINVAL;
+	}
+}
+
+int icm45686_convert_raw_to_q31(struct icm45686_encoded_data *edata,
+				enum sensor_channel chan,
+				int32_t reading,
+				q31_t *out)
+{
+	int32_t whole;
+	int32_t fraction;
+	int64_t intermediate;
+	int8_t shift;
+	int rc;
+
+	rc = icm45686_get_shift(chan, edata->header.accel_fs, edata->header.gyro_fs, &shift);
+	if (rc != 0) {
+		return rc;
+	}
+
+	switch (chan) {
+	case SENSOR_CHAN_ACCEL_XYZ:
+	case SENSOR_CHAN_ACCEL_X:
+	case SENSOR_CHAN_ACCEL_Y:
+	case SENSOR_CHAN_ACCEL_Z:
+		icm45686_accel_ms(edata->header.accel_fs, reading, false, &whole, &fraction);
+		break;
+	case SENSOR_CHAN_GYRO_XYZ:
+	case SENSOR_CHAN_GYRO_X:
+	case SENSOR_CHAN_GYRO_Y:
+	case SENSOR_CHAN_GYRO_Z:
+		icm45686_gyro_rads(edata->header.gyro_fs, reading, false, &whole, &fraction);
+		break;
+	case SENSOR_CHAN_DIE_TEMP:
+		icm45686_temp_c(reading, &whole, &fraction);
+		break;
+	default:
+		return -ENOTSUP;
+	}
+	intermediate = ((int64_t)whole * INT64_C(1000000) + fraction);
+	if (shift < 0) {
+		intermediate =
+			intermediate * ((int64_t)INT32_MAX + 1) * (1 << -shift) / INT64_C(1000000);
+	} else if (shift > 0) {
+		intermediate =
+			intermediate * ((int64_t)INT32_MAX + 1) / ((1 << shift) * INT64_C(1000000));
+	}
+	*out = CLAMP(intermediate, INT32_MIN, INT32_MAX);
+
+	return 0;
+}
+
+static int icm45686_get_channel_position(enum sensor_channel chan)
+{
+	switch (chan) {
+	case SENSOR_CHAN_ACCEL_XYZ:
+	case SENSOR_CHAN_ACCEL_X:
+		return offsetof(struct icm45686_encoded_payload, accel.x) / sizeof(int16_t);
+	case SENSOR_CHAN_ACCEL_Y:
+		return offsetof(struct icm45686_encoded_payload, accel.y) / sizeof(int16_t);
+	case SENSOR_CHAN_ACCEL_Z:
+		return offsetof(struct icm45686_encoded_payload, accel.z) / sizeof(int16_t);
+	case SENSOR_CHAN_GYRO_XYZ:
+	case SENSOR_CHAN_GYRO_X:
+		return offsetof(struct icm45686_encoded_payload, gyro.x) / sizeof(int16_t);
+	case SENSOR_CHAN_GYRO_Y:
+		return offsetof(struct icm45686_encoded_payload, gyro.y) / sizeof(int16_t);
+	case SENSOR_CHAN_GYRO_Z:
+		return offsetof(struct icm45686_encoded_payload, gyro.z) / sizeof(int16_t);
+	case SENSOR_CHAN_DIE_TEMP:
+		return offsetof(struct icm45686_encoded_payload, temp) / sizeof(int16_t);
+	default:
+		return 0;
+	}
+}
+
+static uint8_t icm45686_encode_channel(enum sensor_channel chan)
+{
+	uint8_t encode_bmask = 0;
+
+	switch (chan) {
+	case SENSOR_CHAN_ACCEL_X:
+	case SENSOR_CHAN_ACCEL_Y:
+	case SENSOR_CHAN_ACCEL_Z:
+	case SENSOR_CHAN_GYRO_X:
+	case SENSOR_CHAN_GYRO_Y:
+	case SENSOR_CHAN_GYRO_Z:
+	case SENSOR_CHAN_DIE_TEMP:
+		encode_bmask = BIT(icm45686_get_channel_position(chan));
+		break;
+	case SENSOR_CHAN_ACCEL_XYZ:
+		encode_bmask = BIT(icm45686_get_channel_position(SENSOR_CHAN_ACCEL_X)) |
+			       BIT(icm45686_get_channel_position(SENSOR_CHAN_ACCEL_Y)) |
+			       BIT(icm45686_get_channel_position(SENSOR_CHAN_ACCEL_Z));
+		break;
+	case SENSOR_CHAN_GYRO_XYZ:
+		encode_bmask = BIT(icm45686_get_channel_position(SENSOR_CHAN_GYRO_X)) |
+			       BIT(icm45686_get_channel_position(SENSOR_CHAN_GYRO_Y)) |
+			       BIT(icm45686_get_channel_position(SENSOR_CHAN_GYRO_Z));
+		break;
+	default:
+		break;
+	}
+
+	return encode_bmask;
+}
+
+int icm45686_encode(const struct device *dev,
+		    const struct sensor_chan_spec *const channels,
+		    const size_t num_channels,
+		    uint8_t *buf)
+{
+	struct icm45686_encoded_data *edata = (struct icm45686_encoded_data *)buf;
+	const struct icm45686_config *dev_config = dev->config;
+	uint64_t cycles;
+	int err;
+
+	edata->header.channels = 0;
+
+	for (size_t i = 0 ; i < num_channels ; i++) {
+		edata->header.channels |= icm45686_encode_channel(channels[i].chan_type);
+	}
+
+	err = sensor_clock_get_cycles(&cycles);
+	if (err != 0) {
+		return err;
+	}
+
+	edata->header.events = 0;
+	edata->header.accel_fs = dev_config->settings.accel.fs;
+	edata->header.gyro_fs = dev_config->settings.gyro.fs;
+	edata->header.timestamp = sensor_clock_cycles_to_ns(cycles);
+
+	return 0;
+}
+
+static int icm45686_decoder_get_frame_count(const uint8_t *buffer,
+					    struct sensor_chan_spec chan_spec,
+					    uint16_t *frame_count)
+{
+	struct icm45686_encoded_data *edata = (struct icm45686_encoded_data *)buffer;
+
+	if (chan_spec.chan_idx != 0) {
+		return -ENOTSUP;
+	}
+
+	uint8_t channel_request = icm45686_encode_channel(chan_spec.chan_type);
+
+	if ((edata->header.channels & channel_request) != channel_request) {
+		return -ENODATA;
+	}
+
+	if (!edata->header.events ||
+	    (edata->header.events & REG_INT1_STATUS0_DRDY(true))) {
+		switch (chan_spec.chan_type) {
+		case SENSOR_CHAN_ACCEL_X:
+		case SENSOR_CHAN_ACCEL_Y:
+		case SENSOR_CHAN_ACCEL_Z:
+		case SENSOR_CHAN_ACCEL_XYZ:
+		case SENSOR_CHAN_GYRO_X:
+		case SENSOR_CHAN_GYRO_Y:
+		case SENSOR_CHAN_GYRO_Z:
+		case SENSOR_CHAN_GYRO_XYZ:
+		case SENSOR_CHAN_DIE_TEMP:
+			*frame_count = 1;
+			return 0;
+		default:
+			return -ENOTSUP;
+		}
+	}
+
+	if (edata->header.events & REG_INT1_STATUS0_FIFO_THS(true) ||
+	    edata->header.events & REG_INT1_STATUS0_FIFO_FULL(true)) {
+		switch (chan_spec.chan_type) {
+		case SENSOR_CHAN_ACCEL_XYZ:
+		case SENSOR_CHAN_GYRO_XYZ:
+		case SENSOR_CHAN_DIE_TEMP:
+			*frame_count = edata->header.fifo_count;
+			return 0;
+		/** We're skipping individual axis for fifo packets */
+		default:
+			return -ENOTSUP;
+		}
+	}
+
+	return -1;
+}
+
+static int icm45686_decoder_get_size_info(struct sensor_chan_spec chan_spec,
+					  size_t *base_size,
+					  size_t *frame_size)
+{
+	switch (chan_spec.chan_type) {
+	case SENSOR_CHAN_ACCEL_XYZ:
+	case SENSOR_CHAN_GYRO_XYZ:
+		*base_size = sizeof(struct sensor_three_axis_data);
+		*frame_size = sizeof(struct sensor_three_axis_sample_data);
+		return 0;
+	case SENSOR_CHAN_ACCEL_X:
+	case SENSOR_CHAN_ACCEL_Y:
+	case SENSOR_CHAN_ACCEL_Z:
+	case SENSOR_CHAN_GYRO_X:
+	case SENSOR_CHAN_GYRO_Y:
+	case SENSOR_CHAN_GYRO_Z:
+	case SENSOR_CHAN_DIE_TEMP:
+		*base_size = sizeof(struct sensor_q31_data);
+		*frame_size = sizeof(struct sensor_q31_sample_data);
+		return 0;
+	default:
+		return -ENOTSUP;
+	}
+}
+
+static int icm45686_one_shot_decode(const uint8_t *buffer,
+				    struct sensor_chan_spec chan_spec,
+				    uint32_t *fit,
+				    uint16_t max_count,
+				    void *data_out)
+{
+	struct icm45686_encoded_data *edata = (struct icm45686_encoded_data *)buffer;
+	uint8_t channel_request;
+	int err;
+
+	if (*fit != 0) {
+		return 0;
+	}
+
+	if (max_count == 0 || chan_spec.chan_idx != 0) {
+		return -EINVAL;
+	}
+
+	switch (chan_spec.chan_type) {
+	case SENSOR_CHAN_ACCEL_X:
+	case SENSOR_CHAN_ACCEL_Y:
+	case SENSOR_CHAN_ACCEL_Z:
+	case SENSOR_CHAN_GYRO_X:
+	case SENSOR_CHAN_GYRO_Y:
+	case SENSOR_CHAN_GYRO_Z:
+	case SENSOR_CHAN_DIE_TEMP: {
+		channel_request = icm45686_encode_channel(chan_spec.chan_type);
+		if ((channel_request & edata->header.channels) != channel_request) {
+			return -ENODATA;
+		}
+
+		struct sensor_q31_data *out = data_out;
+
+		out->header.base_timestamp_ns = edata->header.timestamp;
+		out->header.reading_count = 1;
+
+		err = icm45686_get_shift(chan_spec.chan_type,
+					 edata->header.accel_fs,
+					 edata->header.gyro_fs,
+					 &out->shift);
+		if (err != 0) {
+			return -EINVAL;
+		}
+
+		icm45686_convert_raw_to_q31(
+			edata,
+			chan_spec.chan_type,
+			edata->payload.readings[icm45686_get_channel_position(chan_spec.chan_type)],
+			&out->readings[0].value);
+		*fit = 1;
+		return 1;
+	}
+	case SENSOR_CHAN_ACCEL_XYZ:
+	case SENSOR_CHAN_GYRO_XYZ: {
+		channel_request = icm45686_encode_channel(chan_spec.chan_type);
+		if ((channel_request & edata->header.channels) != channel_request) {
+			return -ENODATA;
+		}
+
+		struct sensor_three_axis_data *out = data_out;
+		struct icm45686_encoded_payload *payload = &edata->payload;
+
+		out->header.base_timestamp_ns = edata->header.timestamp;
+		out->header.reading_count = 1;
+
+		icm45686_convert_raw_to_q31(
+			edata,
+			chan_spec.chan_type - 3,
+			payload->readings[icm45686_get_channel_position(chan_spec.chan_type - 3)],
+			&out->readings[0].x);
+		icm45686_convert_raw_to_q31(
+			edata,
+			chan_spec.chan_type - 2,
+			payload->readings[icm45686_get_channel_position(chan_spec.chan_type - 2)],
+			&out->readings[0].y);
+		icm45686_convert_raw_to_q31(
+			edata,
+			chan_spec.chan_type - 1,
+			payload->readings[icm45686_get_channel_position(chan_spec.chan_type - 1)],
+			&out->readings[0].z);
+		*fit = 1;
+		return 1;
+	}
+	default:
+		return -EINVAL;
+	}
+}
+
+static q31_t icm45686_fifo_read_temp_from_packet(const uint8_t *pkt)
+{
+	struct icm45686_encoded_fifo_payload *fdata = (struct icm45686_encoded_fifo_payload *)pkt;
+
+	int32_t whole;
+	uint32_t fraction;
+	int64_t intermediate;
+	int8_t shift;
+	int err;
+
+	err = icm45686_get_shift(SENSOR_CHAN_DIE_TEMP, 0, 0, &shift);
+	if (err != 0) {
+		return -1;
+	}
+
+	icm45686_temp_c(fdata->temp, &whole, &fraction);
+
+	intermediate = ((int64_t)whole * INT64_C(1000000) + fraction);
+	if (shift < 0) {
+		intermediate =
+			intermediate * ((int64_t)INT32_MAX + 1) * (1 << -shift) / INT64_C(1000000);
+	} else if (shift > 0) {
+		intermediate =
+			intermediate * ((int64_t)INT32_MAX + 1) / ((1 << shift) * INT64_C(1000000));
+	}
+
+	return CLAMP(intermediate, INT32_MIN, INT32_MAX);
+}
+
+static int icm45686_fifo_read_imu_from_packet(const uint8_t *pkt,
+					      bool is_accel,
+					      uint8_t axis_offset,
+					      q31_t *out)
+{
+	uint32_t unsigned_value;
+	int32_t signed_value;
+	int offset = 1 + (axis_offset * 2)  + (is_accel ? 0 : 6);
+	uint32_t mask = is_accel ? GENMASK(7, 4) : GENMASK(3, 0);
+	uint8_t accel_fs = ICM45686_DT_ACCEL_FS_32;
+	uint8_t gyro_fs = ICM45686_DT_GYRO_FS_4000;
+
+	int32_t whole;
+	int32_t fraction;
+	int64_t intermediate;
+	int8_t shift;
+
+	unsigned_value = (pkt[offset] | (pkt[offset + 1] << 8));
+	if (unsigned_value == FIFO_NO_DATA) {
+		return -ENODATA;
+	}
+
+	unsigned_value = (unsigned_value << 4) |
+			 ((pkt[17 + axis_offset] & mask) >> (is_accel ? 4 : 0));
+	signed_value = sign_extend(unsigned_value, 19);
+
+	if (!is_accel) {
+		icm45686_get_shift(SENSOR_CHAN_GYRO_XYZ, accel_fs, gyro_fs, &shift);
+		icm45686_gyro_rads(gyro_fs, signed_value, true, &whole, &fraction);
+	} else {
+		icm45686_get_shift(SENSOR_CHAN_ACCEL_XYZ, accel_fs, gyro_fs, &shift);
+		icm45686_accel_ms(accel_fs, signed_value, true, &whole, &fraction);
+	}
+
+	intermediate = ((int64_t)whole * INT64_C(1000000) + fraction);
+	if (shift < 0) {
+		intermediate =
+			intermediate * ((int64_t)INT32_MAX + 1) * (1 << -shift) / INT64_C(1000000);
+	} else if (shift > 0) {
+		intermediate =
+			intermediate * ((int64_t)INT32_MAX + 1) / ((1 << shift) * INT64_C(1000000));
+	}
+
+	*out = CLAMP(intermediate, INT32_MIN, INT32_MAX);
+
+	return 0;
+}
+
+static int icm45686_fifo_decode(const uint8_t *buffer,
+				struct sensor_chan_spec chan_spec,
+				uint32_t *fit,
+				uint16_t max_count,
+				void *data_out)
+{
+	struct icm45686_encoded_data *edata = (struct icm45686_encoded_data *)buffer;
+	struct icm45686_encoded_fifo_payload *frame_begin = &edata->fifo_payload;
+	int count = 0;
+	int err;
+
+	if (*fit >= edata->header.fifo_count || chan_spec.chan_idx != 0) {
+		return 0;
+	}
+
+	while (count < max_count && (*fit < edata->header.fifo_count)) {
+		struct icm45686_encoded_fifo_payload *fdata = &frame_begin[*fit];
+
+		/** This driver assumes 20-byte fifo packets, with both accel and gyro,
+		 * and no auxiliary sensors.
+		 */
+		__ASSERT(!(fdata->header & FIFO_HEADER_EXT_HEADER_EN(true)) &&
+			(fdata->header & FIFO_HEADER_ACCEL_EN(true)) &&
+			(fdata->header & FIFO_HEADER_GYRO_EN(true)) &&
+			(fdata->header & FIFO_HEADER_HIRES_EN(true)),
+			"Unsupported FIFO packet format");
+
+		switch (chan_spec.chan_type) {
+		case SENSOR_CHAN_ACCEL_XYZ:
+		case SENSOR_CHAN_GYRO_XYZ: {
+			struct sensor_three_axis_data *out = data_out;
+			bool is_accel = chan_spec.chan_type == SENSOR_CHAN_ACCEL_XYZ;
+
+			icm45686_get_shift(chan_spec.chan_type,
+					   edata->header.accel_fs,
+					   edata->header.gyro_fs,
+					   &out->shift);
+
+			out->header.base_timestamp_ns = edata->header.timestamp;
+
+			err = icm45686_fifo_read_imu_from_packet((uint8_t *)fdata,
+								 is_accel,
+								 0,
+								 &out->readings[count].x);
+			err |= icm45686_fifo_read_imu_from_packet((uint8_t *)fdata,
+								  is_accel,
+								  1,
+								  &out->readings[count].y);
+			err |= icm45686_fifo_read_imu_from_packet((uint8_t *)fdata,
+								  is_accel,
+								  2,
+								  &out->readings[count].z);
+			if (err != 0) {
+				count--;
+			}
+			break;
+		}
+		case SENSOR_CHAN_DIE_TEMP: {
+			struct sensor_q31_data *out = data_out;
+
+			icm45686_get_shift(chan_spec.chan_type,
+					edata->header.accel_fs,
+					edata->header.gyro_fs,
+					&out->shift);
+
+			out->header.base_timestamp_ns = edata->header.timestamp;
+			out->readings[count].temperature =
+				icm45686_fifo_read_temp_from_packet((uint8_t *)fdata);
+			break;
+		}
+		default:
+			return 0;
+		}
+		*fit = *fit + 1;
+		count++;
+	}
+
+	return count;
+}
+
+static int icm45686_decoder_decode(const uint8_t *buffer,
+				   struct sensor_chan_spec chan_spec,
+				   uint32_t *fit,
+				   uint16_t max_count,
+				   void *data_out)
+{
+	struct icm45686_encoded_data *edata = (struct icm45686_encoded_data *)buffer;
+
+	if (edata->header.events & REG_INT1_STATUS0_FIFO_THS(true) ||
+	    edata->header.events & REG_INT1_STATUS0_FIFO_FULL(true)) {
+		return icm45686_fifo_decode(buffer, chan_spec, fit, max_count, data_out);
+	} else {
+		return icm45686_one_shot_decode(buffer, chan_spec, fit, max_count, data_out);
+	}
+}
+
+static bool icm45686_decoder_has_trigger(const uint8_t *buffer, enum sensor_trigger_type trigger)
+{
+	struct icm45686_encoded_data *edata = (struct icm45686_encoded_data *)buffer;
+
+	switch (trigger) {
+	case SENSOR_TRIG_DATA_READY:
+		return edata->header.events & REG_INT1_STATUS0_DRDY(true);
+	case SENSOR_TRIG_FIFO_WATERMARK:
+		return edata->header.events & REG_INT1_STATUS0_FIFO_THS(true);
+	case SENSOR_TRIG_FIFO_FULL:
+		return edata->header.events & REG_INT1_STATUS0_FIFO_FULL(true);
+	default:
+		break;
+	}
+
+	return false;
+}
+
+SENSOR_DECODER_API_DT_DEFINE() = {
+	.get_frame_count = icm45686_decoder_get_frame_count,
+	.get_size_info = icm45686_decoder_get_size_info,
+	.decode = icm45686_decoder_decode,
+	.has_trigger = icm45686_decoder_has_trigger,
+};
+
+int icm45686_get_decoder(const struct device *dev,
+			 const struct sensor_decoder_api **decoder)
+{
+	ARG_UNUSED(dev);
+	*decoder = &SENSOR_DECODER_NAME();
+
+	return 0;
+}
diff --git a/drivers/sensor/tdk/icm45686/icm45686_decoder.h b/drivers/sensor/tdk/icm45686/icm45686_decoder.h
new file mode 100644
index 00000000000..bb669c842c8
--- /dev/null
+++ b/drivers/sensor/tdk/icm45686/icm45686_decoder.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2023 Google LLC
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_ICM45686_DECODER_H_
+#define ZEPHYR_DRIVERS_SENSOR_ICM45686_DECODER_H_
+
+#include <stdint.h>
+#include <zephyr/drivers/sensor.h>
+#include "icm45686.h"
+
+int icm45686_encode(const struct device *dev,
+		    const struct sensor_chan_spec *const channels,
+		    const size_t num_channels,
+		    uint8_t *buf);
+
+int icm45686_get_decoder(const struct device *dev,
+			 const struct sensor_decoder_api **decoder);
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_ICM45686_DECODER_H_ */
diff --git a/drivers/sensor/tdk/icm45686/icm45686_reg.h b/drivers/sensor/tdk/icm45686/icm45686_reg.h
new file mode 100644
index 00000000000..502ec7373cb
--- /dev/null
+++ b/drivers/sensor/tdk/icm45686/icm45686_reg.h
@@ -0,0 +1,133 @@
+/*
+ * Copyright (c) 2022 Intel Corporation
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_ICM45686_REG_H_
+#define ZEPHYR_DRIVERS_SENSOR_ICM45686_REG_H_
+
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/byteorder.h>
+
+/* Address value has a read bit */
+#define REG_READ_BIT BIT(7)
+
+/* Registers */
+/* Register Bank 0 */
+#define REG_ACCEL_DATA_X1_UI			0x00
+#define REG_ACCEL_DATA_X0_UI			0x01
+#define REG_ACCEL_DATA_Y1_UI			0x02
+#define REG_ACCEL_DATA_Y0_UI			0x03
+#define REG_ACCEL_DATA_Z1_UI			0x04
+#define REG_ACCEL_DATA_Z0_UI			0x05
+#define REG_GYRO_DATA_X1_UI			0x06
+#define REG_GYRO_DATA_X0_UI			0x07
+#define REG_GYRO_DATA_Y1_UI			0x08
+#define REG_GYRO_DATA_Y0_UI			0x09
+#define REG_GYRO_DATA_Z1_UI			0x0A
+#define REG_GYRO_DATA_Z0_UI			0x0B
+#define REG_TEMP_DATA1_UI			0x0C
+#define REG_TEMP_DATA0_UI			0x0D
+#define REG_PWR_MGMT0				0x10
+#define REG_FIFO_COUNT_0			0x12
+#define REG_FIFO_COUNT_1			0x13
+#define REG_FIFO_DATA				0x14
+#define REG_INT1_CONFIG0			0x16
+#define REG_INT1_CONFIG1			0x17
+#define REG_INT1_CONFIG2			0x18
+#define REG_INT1_STATUS0			0x19
+#define REG_INT1_STATUS1			0x1A
+#define REG_ACCEL_CONFIG0			0x1B
+#define REG_GYRO_CONFIG0			0x1C
+#define REG_FIFO_CONFIG0			0x1D
+#define REG_FIFO_CONFIG1_0			0x1E
+#define REG_FIFO_CONFIG1_1			0x1F
+#define REG_FIFO_CONFIG2			0x20
+#define REG_FIFO_CONFIG3			0x21
+#define REG_FIFO_CONFIG4			0x22
+#define REG_DRIVE_CONFIG0			0x32
+#define REG_DRIVE_CONFIG1			0x33
+#define REG_WHO_AM_I				0x72
+#define REG_IREG_ADDR_15_8			0x7C
+#define REG_IREG_ADDR_7_0			0x7D
+#define REG_IREG_DATA				0x7E
+#define REG_MISC2				0x7F
+
+/* User Bank IPREG_SYS1 - Gyro-related config settings */
+#define REG_IPREG_SYS1_OFFSET			0xA400
+#define REG_IPREG_SYS1_REG_172			0xAC
+
+/* User Bank IPREG_SYS2 - Accel-related config settings */
+#define REG_IPREG_SYS2_OFFSET			0xA500
+#define REG_IPREG_SYS2_REG_131			0x83
+
+/* Helper Macros for register manipulation */
+#define REG_PWR_MGMT0_ACCEL_MODE(val)			((val) & BIT_MASK(2))
+#define REG_PWR_MGMT0_GYRO_MODE(val)			(((val) & BIT_MASK(2)) << 2)
+
+#define REG_ACCEL_CONFIG0_ODR(val)			((val) & BIT_MASK(4))
+#define REG_ACCEL_CONFIG0_FS(val)			(((val) & BIT_MASK(3)) << 4)
+
+#define REG_GYRO_CONFIG0_ODR(val)			((val) & BIT_MASK(4))
+#define REG_GYRO_CONFIG0_FS(val)			(((val) & BIT_MASK(4)) << 4)
+
+#define REG_DRIVE_CONFIG0_SPI_SLEW(val)			(((val) & BIT_MASK(2)) << 1)
+#define REG_DRIVE_CONFIG1_I3C_SLEW(val)			(((val) & BIT_MASK(3)) |		   \
+							 (((val) & BIT_MASK(3)) << 3))
+
+#define REG_MISC2_SOFT_RST(val)				((val << 1) & BIT(1))
+
+#define REG_IPREG_SYS1_REG_172_GYRO_LPFBW_SEL(val)	(val & BIT_MASK(3))
+
+#define REG_IPREG_SYS2_REG_131_ACCEL_LPFBW_SEL(val)	(val & BIT_MASK(3))
+
+#define REG_INT1_CONFIG0_STATUS_EN_DRDY(val)		(((val) & BIT_MASK(1)) << 2)
+#define REG_INT1_CONFIG0_STATUS_EN_FIFO_THS(val)	(((val) & BIT_MASK(1)) << 1)
+#define REG_INT1_CONFIG0_STATUS_EN_FIFO_FULL(val)	((val) & BIT_MASK(1))
+
+#define REG_INT1_CONFIG2_EN_OPEN_DRAIN(val)		(((val) & BIT_MASK(1)) << 2)
+#define REG_INT1_CONFIG2_EN_LATCH_MODE(val)		(((val) & BIT_MASK(1)) << 1)
+#define REG_INT1_CONFIG2_EN_ACTIVE_HIGH(val)		((val) & BIT_MASK(1))
+
+#define REG_INT1_STATUS0_DRDY(val)			(((val) & BIT_MASK(1)) << 2)
+#define REG_INT1_STATUS0_FIFO_THS(val)			(((val) & BIT_MASK(1)) << 1)
+#define REG_INT1_STATUS0_FIFO_FULL(val)			((val) & BIT_MASK(1))
+
+#define REG_FIFO_CONFIG0_FIFO_MODE_BYPASS		0
+#define REG_FIFO_CONFIG0_FIFO_MODE_STREAM		1
+#define REG_FIFO_CONFIG0_FIFO_MODE_STOP_ON_FULL		2
+
+#define REG_FIFO_CONFIG0_FIFO_DEPTH_2K			0x07
+#define REG_FIFO_CONFIG0_FIFO_DEPTH_8K			0x1F
+
+#define REG_FIFO_CONFIG0_FIFO_MODE(val)			(((val) & BIT_MASK(2)) << 6)
+#define REG_FIFO_CONFIG0_FIFO_DEPTH(val)		((val) & BIT_MASK(6))
+
+#define REG_FIFO_CONFIG1_0_FIFO_WM_THS(val)		((val) & BIT_MASK(8))
+#define REG_FIFO_CONFIG1_1_FIFO_WM_THS(val)		(((val) >> 8) & BIT_MASK(8))
+
+#define REG_FIFO_CONFIG2_FIFO_FLUSH(val)		(((val) & BIT_MASK(1)) << 7)
+#define REG_FIFO_CONFIG2_FIFO_WM_GT_THS(val)		(((val) & BIT_MASK(1)) << 3)
+
+#define REG_FIFO_CONFIG3_FIFO_HIRES_EN(val)		(((val) & BIT_MASK(1)) << 3)
+#define REG_FIFO_CONFIG3_FIFO_GYRO_EN(val)		(((val) & BIT_MASK(1)) << 2)
+#define REG_FIFO_CONFIG3_FIFO_ACCEL_EN(val)		(((val) & BIT_MASK(1)) << 1)
+#define REG_FIFO_CONFIG3_FIFO_EN(val)			((val) & BIT_MASK(1))
+
+/* Misc. Defines */
+#define WHO_AM_I_ICM45686 0xE9
+
+#define REG_IREG_PREPARE_WRITE_ARRAY(base, reg, val)	{((base) >> 8) & 0xFF, reg, val}
+
+#define FIFO_HEADER_EXT_HEADER_EN(val)			(((val) & BIT_MASK(1)) << 7)
+#define FIFO_HEADER_ACCEL_EN(val)			(((val) & BIT_MASK(1)) << 6)
+#define FIFO_HEADER_GYRO_EN(val)			(((val) & BIT_MASK(1)) << 5)
+#define FIFO_HEADER_HIRES_EN(val)			(((val) & BIT_MASK(1)) << 4)
+
+#define FIFO_NO_DATA					0x8000
+#define FIFO_COUNT_MAX_HIGH_RES				104
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_ICM45686_REG_H_ */
diff --git a/drivers/sensor/tdk/icm45686/icm45686_stream.c b/drivers/sensor/tdk/icm45686/icm45686_stream.c
new file mode 100644
index 00000000000..7b561807080
--- /dev/null
+++ b/drivers/sensor/tdk/icm45686/icm45686_stream.c
@@ -0,0 +1,709 @@
+/*
+ * Copyright (c) 2023 Google LLC
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/sensor_clock.h>
+#include <zephyr/rtio/rtio.h>
+#include <zephyr/sys/atomic.h>
+
+#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(invensense_icm45686, i3c)
+#include <zephyr/drivers/i3c.h>
+#endif
+
+#include "icm45686.h"
+#include "icm45686_bus.h"
+#include "icm45686_stream.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(ICM45686_STREAM, CONFIG_SENSOR_LOG_LEVEL);
+
+static struct sensor_stream_trigger *get_read_config_trigger(const struct sensor_read_config *cfg,
+							     enum sensor_trigger_type trig)
+{
+	for (int i = 0; i < cfg->count; ++i) {
+		if (cfg->triggers[i].trigger == trig) {
+			return &cfg->triggers[i];
+		}
+	}
+	LOG_DBG("Unsupported trigger (%d)", trig);
+	return NULL;
+}
+
+static inline bool should_flush_fifo(const struct sensor_read_config *read_cfg,
+				     uint8_t int_status)
+{
+	struct sensor_stream_trigger *trig_fifo_ths = get_read_config_trigger(
+		read_cfg,
+		SENSOR_TRIG_FIFO_WATERMARK);
+	struct sensor_stream_trigger *trig_fifo_full = get_read_config_trigger(
+		read_cfg,
+		SENSOR_TRIG_FIFO_FULL);
+
+	bool fifo_ths = int_status & REG_INT1_STATUS0_FIFO_THS(true);
+	bool fifo_full = int_status & REG_INT1_STATUS0_FIFO_FULL(true);
+
+	if ((trig_fifo_ths && trig_fifo_ths->opt == SENSOR_STREAM_DATA_DROP && fifo_ths) ||
+	    (trig_fifo_full && trig_fifo_full->opt == SENSOR_STREAM_DATA_DROP && fifo_full)) {
+		return true;
+	}
+
+	return false;
+}
+
+static inline bool should_read_fifo(const struct sensor_read_config *read_cfg,
+				    uint8_t int_status)
+{
+	struct sensor_stream_trigger *trig_fifo_ths = get_read_config_trigger(
+		read_cfg,
+		SENSOR_TRIG_FIFO_WATERMARK);
+	struct sensor_stream_trigger *trig_fifo_full = get_read_config_trigger(
+		read_cfg,
+		SENSOR_TRIG_FIFO_FULL);
+
+	bool fifo_ths = int_status & REG_INT1_STATUS0_FIFO_THS(true);
+	bool fifo_full = int_status & REG_INT1_STATUS0_FIFO_FULL(true);
+
+	if ((trig_fifo_ths && trig_fifo_ths->opt == SENSOR_STREAM_DATA_INCLUDE && fifo_ths) ||
+	    (trig_fifo_full && trig_fifo_full->opt == SENSOR_STREAM_DATA_INCLUDE && fifo_full)) {
+		return true;
+	}
+
+	return false;
+}
+
+static inline bool should_read_data(const struct sensor_read_config *read_cfg,
+				    uint8_t int_status)
+{
+	struct sensor_stream_trigger *trig_drdy = get_read_config_trigger(
+		read_cfg,
+		SENSOR_TRIG_DATA_READY);
+
+	bool drdy = int_status & REG_INT1_STATUS0_DRDY(true);
+
+	if (trig_drdy && trig_drdy->opt == SENSOR_STREAM_DATA_INCLUDE && drdy) {
+		return true;
+	}
+
+	return false;
+}
+
+static void icm45686_complete_result(struct rtio *ctx,
+				     const struct rtio_sqe *sqe,
+				     void *arg)
+{
+	const struct device *dev = (const struct device *)arg;
+	struct icm45686_data *data = dev->data;
+
+	struct rtio_iodev_sqe *iodev_sqe = data->stream.iodev_sqe;
+
+	memset(&data->stream.data, 0, sizeof(data->stream.data));
+
+	rtio_iodev_sqe_ok(iodev_sqe, 0);
+}
+
+static void icm45686_handle_event_actions(struct rtio *ctx,
+					  const struct rtio_sqe *sqe,
+					  void *arg)
+{
+	const struct device *dev = (const struct device *)arg;
+	struct icm45686_data *data = dev->data;
+	const struct sensor_read_config *read_cfg = data->stream.iodev_sqe->sqe.iodev->data;
+	uint8_t int_status = data->stream.data.int_status;
+	int err;
+
+	data->stream.data.events.drdy = int_status & REG_INT1_STATUS0_DRDY(true);
+	data->stream.data.events.fifo_ths = int_status & REG_INT1_STATUS0_FIFO_THS(true);
+	data->stream.data.events.fifo_full = int_status & REG_INT1_STATUS0_FIFO_FULL(true);
+
+	__ASSERT(data->stream.data.fifo_count > 0 &&
+		 data->stream.data.fifo_count <= FIFO_COUNT_MAX_HIGH_RES,
+		 "Invalid fifo count: %d", data->stream.data.fifo_count);
+
+	struct icm45686_encoded_data *buf;
+	uint32_t buf_len;
+	uint32_t buf_len_required = sizeof(struct icm45686_encoded_header);
+
+	/** We just need the header to communicate the events occurred during
+	 * this SQE. Only include more data if the associated trigger needs it.
+	 */
+	if (should_read_fifo(read_cfg, int_status)) {
+		buf_len_required += (data->stream.data.fifo_count *
+				     sizeof(struct icm45686_encoded_fifo_payload));
+	} else if (should_read_data(read_cfg, int_status)) {
+		buf_len_required += sizeof(struct icm45686_encoded_payload);
+	}
+
+	err = rtio_sqe_rx_buf(data->stream.iodev_sqe,
+			      buf_len_required,
+			      buf_len_required,
+			      (uint8_t **)&buf,
+			      &buf_len);
+	__ASSERT(err == 0, "Failed to acquire buffer (len: %d) for encoded data: %d. "
+			   "Please revisit RTIO queue sizing and look for "
+			   "bottlenecks during sensor data processing",
+			   buf_len_required, err);
+
+	/** Still throw an error even if asserts are off */
+	if (err) {
+		struct rtio_iodev_sqe *iodev_sqe = data->stream.iodev_sqe;
+
+		LOG_ERR("Failed to acquire buffer for encoded data: %d", err);
+
+		data->stream.iodev_sqe = NULL;
+		rtio_iodev_sqe_err(iodev_sqe, err);
+		return;
+	}
+
+	LOG_DBG("Alloc buf - required: %d, alloc: %d", buf_len_required, buf_len);
+
+	buf->header.timestamp = data->stream.data.timestamp;
+	buf->header.fifo_count = 0;
+	buf->header.channels = 0;
+	buf->header.events = REG_INT1_STATUS0_DRDY(data->stream.data.events.drdy) |
+			     REG_INT1_STATUS0_FIFO_THS(data->stream.data.events.fifo_ths) |
+			     REG_INT1_STATUS0_FIFO_FULL(data->stream.data.events.fifo_full);
+
+	if (should_read_fifo(read_cfg, int_status)) {
+
+		struct rtio_sqe *data_wr_sqe = rtio_sqe_acquire(ctx);
+		struct rtio_sqe *data_rd_sqe = rtio_sqe_acquire(ctx);
+		uint8_t read_reg;
+
+		if (!data_wr_sqe || !data_rd_sqe) {
+			struct rtio_iodev_sqe *iodev_sqe = data->stream.iodev_sqe;
+
+			LOG_ERR("Failed to acquire RTIO SQEs");
+
+			data->stream.iodev_sqe = NULL;
+			rtio_iodev_sqe_err(iodev_sqe, -ENOMEM);
+			return;
+		}
+
+		/** In FIFO data, the scale is fixed, irrespective of
+		 * the configured settings.
+		 */
+		buf->header.accel_fs = ICM45686_DT_ACCEL_FS_32;
+		buf->header.gyro_fs = ICM45686_DT_GYRO_FS_4000;
+		buf->header.channels = 0x7F; /* Signal all channels are available */
+		buf->header.fifo_count = data->stream.data.fifo_count;
+
+		read_reg = REG_FIFO_DATA | REG_READ_BIT;
+		rtio_sqe_prep_tiny_write(data_wr_sqe,
+					 data->rtio.iodev,
+					 RTIO_PRIO_HIGH,
+					 &read_reg,
+					 1,
+					 NULL);
+		data_wr_sqe->flags |= RTIO_SQE_TRANSACTION;
+
+		rtio_sqe_prep_read(data_rd_sqe,
+				   data->rtio.iodev,
+				   RTIO_PRIO_HIGH,
+				   (uint8_t *)&buf->fifo_payload,
+				   (buf->header.fifo_count *
+				   sizeof(struct icm45686_encoded_fifo_payload)),
+				   NULL);
+		if (data->rtio.type == ICM45686_BUS_I2C) {
+			data_rd_sqe->iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART;
+		} else if (data->rtio.type == ICM45686_BUS_I3C) {
+			data_rd_sqe->iodev_flags |= RTIO_IODEV_I3C_STOP | RTIO_IODEV_I3C_RESTART;
+		}
+		data_rd_sqe->flags |= RTIO_SQE_CHAINED;
+
+	} else if (should_flush_fifo(read_cfg, int_status)) {
+
+		struct rtio_sqe *write_sqe = rtio_sqe_acquire(ctx);
+
+		if (!write_sqe) {
+			struct rtio_iodev_sqe *iodev_sqe = data->stream.iodev_sqe;
+
+			LOG_ERR("Failed to acquire RTIO SQE");
+
+			data->stream.iodev_sqe = NULL;
+			rtio_iodev_sqe_err(iodev_sqe, -ENOMEM);
+			return;
+		}
+
+		uint8_t write_reg[] = {
+			REG_FIFO_CONFIG2,
+			REG_FIFO_CONFIG2_FIFO_FLUSH(true) |
+			REG_FIFO_CONFIG2_FIFO_WM_GT_THS(true)
+		};
+
+		rtio_sqe_prep_tiny_write(write_sqe,
+					 data->rtio.iodev,
+					 RTIO_PRIO_HIGH,
+					 write_reg,
+					 sizeof(write_reg),
+					 NULL);
+		if (data->rtio.type == ICM45686_BUS_I2C) {
+			write_sqe->iodev_flags |= RTIO_IODEV_I2C_STOP;
+		} else if (data->rtio.type == ICM45686_BUS_I3C) {
+			write_sqe->iodev_flags |= RTIO_IODEV_I3C_STOP;
+		}
+		write_sqe->flags |= RTIO_SQE_CHAINED;
+
+	} else if (should_read_data(read_cfg, int_status)) {
+
+		buf->header.accel_fs = data->edata.header.accel_fs;
+		buf->header.gyro_fs = data->edata.header.gyro_fs;
+		buf->header.channels = 0x7F; /* Signal all channels are available */
+
+		struct rtio_sqe *write_sqe = rtio_sqe_acquire(ctx);
+		struct rtio_sqe *read_sqe = rtio_sqe_acquire(ctx);
+
+		if (!write_sqe || !read_sqe) {
+			struct rtio_iodev_sqe *iodev_sqe = data->stream.iodev_sqe;
+
+			LOG_ERR("Failed to acquire RTIO SQEs");
+
+			data->stream.iodev_sqe = NULL;
+			rtio_iodev_sqe_err(iodev_sqe, -ENOMEM);
+			return;
+		}
+
+		uint8_t read_reg = REG_ACCEL_DATA_X1_UI | REG_READ_BIT;
+
+		rtio_sqe_prep_tiny_write(write_sqe,
+					 data->rtio.iodev,
+					 RTIO_PRIO_HIGH,
+					 &read_reg,
+					 1,
+					 NULL);
+		write_sqe->flags |= RTIO_SQE_TRANSACTION;
+
+		rtio_sqe_prep_read(read_sqe,
+				   data->rtio.iodev,
+				   RTIO_PRIO_HIGH,
+				   buf->payload.buf,
+				   sizeof(buf->payload.buf),
+				   NULL);
+		if (data->rtio.type == ICM45686_BUS_I2C) {
+			read_sqe->iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART;
+		} else if (data->rtio.type == ICM45686_BUS_I3C) {
+			read_sqe->iodev_flags |= RTIO_IODEV_I3C_STOP | RTIO_IODEV_I3C_RESTART;
+		}
+		read_sqe->flags |= RTIO_SQE_CHAINED;
+	}
+
+	struct rtio_cqe *cqe;
+
+	do {
+		cqe = rtio_cqe_consume(ctx);
+		if (cqe != NULL) {
+			err = cqe->result;
+			rtio_cqe_release(ctx, cqe);
+		}
+	} while (cqe != NULL);
+
+	struct rtio_sqe *cb_sqe = rtio_sqe_acquire(ctx);
+
+	if (!cb_sqe) {
+		LOG_ERR("Failed to acquire RTIO SQE for completion callback");
+		rtio_iodev_sqe_err(data->stream.iodev_sqe, -ENOMEM);
+		return;
+	}
+
+	rtio_sqe_prep_callback_no_cqe(cb_sqe,
+				      icm45686_complete_result,
+				      (void *)dev,
+				      data->stream.iodev_sqe);
+
+	rtio_submit(ctx, 0);
+}
+
+static void icm45686_event_handler(const struct device *dev)
+{
+	struct icm45686_data *data = dev->data;
+	uint8_t val = 0;
+	uint64_t cycles;
+	int err;
+
+	if (!data->stream.iodev_sqe ||
+	    FIELD_GET(RTIO_SQE_CANCELED, data->stream.iodev_sqe->sqe.flags)) {
+		LOG_WRN("Callback triggered with no streaming submission - Disabling interrupts");
+
+		struct rtio_sqe *write_sqe = rtio_sqe_acquire(data->rtio.ctx);
+		uint8_t wr_data[] = {REG_INT1_CONFIG0, 0x00};
+
+		rtio_sqe_prep_tiny_write(write_sqe,
+					 data->rtio.iodev,
+					 RTIO_PRIO_HIGH,
+					 wr_data,
+					 sizeof(wr_data),
+					 NULL);
+		if (data->rtio.type == ICM45686_BUS_I2C) {
+			write_sqe->iodev_flags |= RTIO_IODEV_I2C_STOP;
+		} else if (data->rtio.type == ICM45686_BUS_I3C) {
+			write_sqe->iodev_flags |= RTIO_IODEV_I3C_STOP;
+		}
+		rtio_submit(data->rtio.ctx, 0);
+
+		data->stream.settings.enabled.drdy = false;
+		data->stream.settings.enabled.fifo_ths = false;
+		data->stream.settings.enabled.fifo_full = false;
+		return;
+	} else if (!atomic_cas(&data->stream.in_progress, 0, 1)) {
+		/** There's an on-going */
+		return;
+	}
+
+	err = sensor_clock_get_cycles(&cycles);
+	if (err) {
+		struct rtio_iodev_sqe *iodev_sqe = data->stream.iodev_sqe;
+
+		LOG_ERR("Failed to get timestamp: %d", err);
+
+		data->stream.iodev_sqe = NULL;
+		rtio_iodev_sqe_err(iodev_sqe, err);
+		return;
+	}
+
+	data->stream.data.timestamp = sensor_clock_cycles_to_ns(cycles);
+
+	/** Prepare an asynchronous read of the INT status register */
+	struct rtio_sqe *write_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	struct rtio_sqe *read_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	struct rtio_sqe *write_fifo_ct_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	struct rtio_sqe *read_fifo_ct_sqe = rtio_sqe_acquire(data->rtio.ctx);
+	struct rtio_sqe *complete_sqe = rtio_sqe_acquire(data->rtio.ctx);
+
+	if (!write_sqe || !read_sqe || !complete_sqe) {
+		struct rtio_iodev_sqe *iodev_sqe = data->stream.iodev_sqe;
+
+		LOG_ERR("Failed to acquire RTIO SQEs");
+
+		data->stream.iodev_sqe = NULL;
+		rtio_iodev_sqe_err(iodev_sqe, -ENOMEM);
+		return;
+	}
+
+	/** Directly read Status Register to determine what triggered the event */
+	val = REG_INT1_STATUS0 | REG_READ_BIT;
+	rtio_sqe_prep_tiny_write(write_sqe,
+				 data->rtio.iodev,
+				 RTIO_PRIO_HIGH,
+				 &val,
+				 1,
+				 NULL);
+	write_sqe->flags |= RTIO_SQE_TRANSACTION;
+
+	rtio_sqe_prep_read(read_sqe,
+			   data->rtio.iodev,
+			   RTIO_PRIO_HIGH,
+			   &data->stream.data.int_status,
+			   1,
+			   NULL);
+	if (data->rtio.type == ICM45686_BUS_I2C) {
+		read_sqe->iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART;
+	} else if (data->rtio.type == ICM45686_BUS_I3C) {
+		read_sqe->iodev_flags |= RTIO_IODEV_I3C_STOP | RTIO_IODEV_I3C_RESTART;
+	}
+	read_sqe->flags |= RTIO_SQE_CHAINED;
+
+
+	/** Preemptively read FIFO count so we can decide on the next callback
+	 * how much FIFO data we'd read (if needed).
+	 */
+	val = REG_FIFO_COUNT_0 | REG_READ_BIT;
+	rtio_sqe_prep_tiny_write(write_fifo_ct_sqe,
+				 data->rtio.iodev,
+				 RTIO_PRIO_HIGH,
+				 &val,
+				 1,
+				 NULL);
+	write_fifo_ct_sqe->flags |= RTIO_SQE_TRANSACTION;
+
+	rtio_sqe_prep_read(read_fifo_ct_sqe,
+			   data->rtio.iodev,
+			   RTIO_PRIO_HIGH,
+			   (uint8_t *)&data->stream.data.fifo_count,
+			   2,
+			   NULL);
+	if (data->rtio.type == ICM45686_BUS_I2C) {
+		read_fifo_ct_sqe->iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART;
+	} else if (data->rtio.type == ICM45686_BUS_I3C) {
+		read_fifo_ct_sqe->iodev_flags |= RTIO_IODEV_I3C_STOP | RTIO_IODEV_I3C_RESTART;
+	}
+	read_fifo_ct_sqe->flags |= RTIO_SQE_CHAINED;
+
+	rtio_sqe_prep_callback_no_cqe(complete_sqe,
+				      icm45686_handle_event_actions,
+				      (void *)dev,
+				      data->stream.iodev_sqe);
+
+	rtio_submit(data->rtio.ctx, 0);
+}
+
+#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(invensense_icm45686, i3c)
+static int icm45686_ibi_cb(struct i3c_device_desc *target,
+			   struct i3c_ibi_payload *payload)
+{
+	icm45686_event_handler(target->dev);
+
+	return 0;
+}
+#endif
+
+static void icm45686_gpio_callback(const struct device *gpio_dev,
+				   struct gpio_callback *cb,
+				   uint32_t pins)
+{
+	struct icm45686_stream *stream = CONTAINER_OF(cb,
+						      struct icm45686_stream,
+						      cb);
+	const struct device *dev = stream->dev;
+
+	icm45686_event_handler(dev);
+}
+
+static inline bool settings_changed(const struct icm45686_stream *a,
+				    const struct icm45686_stream *b)
+{
+	return (a->settings.enabled.drdy != b->settings.enabled.drdy) ||
+	       (a->settings.opt.drdy != b->settings.opt.drdy) ||
+	       (a->settings.enabled.fifo_ths != b->settings.enabled.fifo_ths) ||
+	       (a->settings.opt.fifo_ths != b->settings.opt.fifo_ths) ||
+	       (a->settings.enabled.fifo_full != b->settings.enabled.fifo_full) ||
+	       (a->settings.opt.fifo_full != b->settings.opt.fifo_full);
+}
+
+void icm45686_stream_submit(const struct device *dev,
+			    struct rtio_iodev_sqe *iodev_sqe)
+{
+	const struct sensor_read_config *read_cfg = iodev_sqe->sqe.iodev->data;
+	struct icm45686_data *data = dev->data;
+	const struct icm45686_config *cfg = dev->config;
+	uint8_t val = 0;
+	int err;
+
+	/** This separate struct is required due to the streaming API using a
+	 * multi-shot RTIO submission: meaning, re-submitting itself after
+	 * completion; hence, we don't have context to determine if this was
+	 * the first submission that kicked things off. We're then, inferring
+	 * this by comparing if the read-config has changed, and only restart
+	 * in such case.
+	 */
+	struct icm45686_stream stream = {0};
+
+	for (size_t i = 0 ; i  < read_cfg->count ; i++) {
+		switch (read_cfg->triggers[i].trigger) {
+		case SENSOR_TRIG_DATA_READY:
+			stream.settings.enabled.drdy = true;
+			stream.settings.opt.drdy = read_cfg->triggers[i].opt;
+			break;
+		case SENSOR_TRIG_FIFO_WATERMARK:
+			stream.settings.enabled.fifo_ths = true;
+			stream.settings.opt.fifo_ths = read_cfg->triggers[i].opt;
+			break;
+		case SENSOR_TRIG_FIFO_FULL:
+			stream.settings.enabled.fifo_full = true;
+			stream.settings.opt.fifo_full = read_cfg->triggers[i].opt;
+			break;
+		default:
+			LOG_ERR("Unsupported trigger (%d)", read_cfg->triggers[i].trigger);
+			rtio_iodev_sqe_err(iodev_sqe, -ENOTSUP);
+			return;
+		}
+	}
+
+	__ASSERT(stream.settings.enabled.drdy ^
+		 ((stream.settings.enabled.fifo_ths || stream.settings.enabled.fifo_full)),
+		 "DRDY should not be enabled alongside FIFO triggers");
+
+	__ASSERT(!stream.settings.enabled.fifo_ths ||
+		 (stream.settings.enabled.fifo_ths && cfg->settings.fifo_watermark),
+		 "FIFO watermark trigger requires a watermark level. Please "
+		 "configure it on the device-tree");
+
+	/* Store context for next submission (handled within callbacks) */
+	data->stream.iodev_sqe = iodev_sqe;
+
+	(void)atomic_clear(&data->stream.in_progress);
+
+	if (settings_changed(&data->stream, &stream)) {
+
+		data->stream.settings = stream.settings;
+
+		/* Disable all interrupts before re-configuring */
+		err = icm45686_bus_write(dev, REG_INT1_CONFIG0, &val, 1);
+		if (err) {
+			LOG_ERR("Failed to disable interrupts on INT1_CONFIG0: %d", err);
+			data->stream.iodev_sqe = NULL;
+			rtio_iodev_sqe_err(iodev_sqe, err);
+			return;
+		}
+
+		/* Read flags to clear them */
+		err = icm45686_bus_read(dev, REG_INT1_STATUS0, &val, 1);
+		if (err) {
+			LOG_ERR("Failed to read INT1_STATUS0: %d", err);
+			data->stream.iodev_sqe = NULL;
+			rtio_iodev_sqe_err(iodev_sqe, err);
+			return;
+		}
+
+		val = REG_FIFO_CONFIG3_FIFO_EN(false) |
+		      REG_FIFO_CONFIG3_FIFO_ACCEL_EN(false) |
+		      REG_FIFO_CONFIG3_FIFO_GYRO_EN(false) |
+		      REG_FIFO_CONFIG3_FIFO_HIRES_EN(false);
+		err = icm45686_bus_write(dev, REG_FIFO_CONFIG3, &val, 1);
+		if (err) {
+			LOG_ERR("Failed to disable all FIFO settings: %d", err);
+			data->stream.iodev_sqe = NULL;
+			rtio_iodev_sqe_err(iodev_sqe, err);
+			return;
+		}
+
+		val = REG_INT1_CONFIG0_STATUS_EN_DRDY(data->stream.settings.enabled.drdy) |
+		      REG_INT1_CONFIG0_STATUS_EN_FIFO_THS(data->stream.settings.enabled.fifo_ths) |
+		      REG_INT1_CONFIG0_STATUS_EN_FIFO_FULL(data->stream.settings.enabled.fifo_full);
+		err = icm45686_bus_write(dev, REG_INT1_CONFIG0, &val, 1);
+		if (err) {
+			LOG_ERR("Failed to configure INT1_CONFIG0: %d", err);
+			data->stream.iodev_sqe = NULL;
+			rtio_iodev_sqe_err(iodev_sqe, err);
+			return;
+		}
+
+		val = REG_FIFO_CONFIG0_FIFO_MODE(REG_FIFO_CONFIG0_FIFO_MODE_BYPASS) |
+		      REG_FIFO_CONFIG0_FIFO_DEPTH(REG_FIFO_CONFIG0_FIFO_DEPTH_2K);
+		err = icm45686_bus_write(dev, REG_FIFO_CONFIG0, &val, 1);
+		if (err) {
+			LOG_ERR("Failed to disable FIFO: %d", err);
+			data->stream.iodev_sqe = NULL;
+			rtio_iodev_sqe_err(iodev_sqe, err);
+			return;
+		}
+
+		if (data->stream.settings.enabled.fifo_ths ||
+		    data->stream.settings.enabled.fifo_full) {
+			uint16_t fifo_ths = data->stream.settings.enabled.fifo_ths ?
+					    cfg->settings.fifo_watermark : 0;
+
+			val = REG_FIFO_CONFIG2_FIFO_WM_GT_THS(true) |
+			      REG_FIFO_CONFIG2_FIFO_FLUSH(true);
+			err = icm45686_bus_write(dev, REG_FIFO_CONFIG2, &val, 1);
+			if (err) {
+				LOG_ERR("Failed to configure greater-than FIFO threshold: %d", err);
+				data->stream.iodev_sqe = NULL;
+				rtio_iodev_sqe_err(iodev_sqe, err);
+				return;
+			}
+
+			err = icm45686_bus_write(dev, REG_FIFO_CONFIG1_0, (uint8_t *)&fifo_ths, 2);
+			if (err) {
+				LOG_ERR("Failed to configure FIFO watermark: %d", err);
+				data->stream.iodev_sqe = NULL;
+				rtio_iodev_sqe_err(iodev_sqe, err);
+				return;
+			}
+
+			val = REG_FIFO_CONFIG0_FIFO_MODE(REG_FIFO_CONFIG0_FIFO_MODE_STREAM) |
+			      REG_FIFO_CONFIG0_FIFO_DEPTH(REG_FIFO_CONFIG0_FIFO_DEPTH_2K);
+			err = icm45686_bus_write(dev, REG_FIFO_CONFIG0, &val, 1);
+			if (err) {
+				LOG_ERR("Failed to disable FIFO: %d", err);
+				data->stream.iodev_sqe = NULL;
+				rtio_iodev_sqe_err(iodev_sqe, err);
+				return;
+			}
+
+			val = REG_FIFO_CONFIG3_FIFO_EN(true) |
+			      REG_FIFO_CONFIG3_FIFO_ACCEL_EN(true) |
+			      REG_FIFO_CONFIG3_FIFO_GYRO_EN(true) |
+			      REG_FIFO_CONFIG3_FIFO_HIRES_EN(true);
+			err = icm45686_bus_write(dev, REG_FIFO_CONFIG3, &val, 1);
+			if (err) {
+				LOG_ERR("Failed to enable FIFO: %d", err);
+				data->stream.iodev_sqe = NULL;
+				rtio_iodev_sqe_err(iodev_sqe, err);
+				return;
+			}
+		}
+	}
+}
+
+int icm45686_stream_init(const struct device *dev)
+{
+	const struct icm45686_config *cfg = dev->config;
+	struct icm45686_data *data = dev->data;
+	uint8_t val = 0;
+	int err;
+
+	/** Needed to get back the device handle from the callback context */
+	data->stream.dev = dev;
+
+	(void)atomic_clear(&data->stream.in_progress);
+
+	if (cfg->int_gpio.port) {
+		if (!gpio_is_ready_dt(&cfg->int_gpio)) {
+			LOG_ERR("Interrupt GPIO not ready");
+			return -ENODEV;
+		}
+
+		err = gpio_pin_configure_dt(&cfg->int_gpio, GPIO_INPUT);
+		if (err) {
+			LOG_ERR("Failed to configure interrupt GPIO");
+			return -EIO;
+		}
+
+		gpio_init_callback(&data->stream.cb,
+				   icm45686_gpio_callback,
+				   BIT(cfg->int_gpio.pin));
+
+		err = gpio_add_callback(cfg->int_gpio.port, &data->stream.cb);
+		if (err) {
+			LOG_ERR("Failed to add interrupt callback");
+			return -EIO;
+		}
+
+		err = gpio_pin_interrupt_configure_dt(&cfg->int_gpio,
+						      GPIO_INT_EDGE_TO_ACTIVE);
+		if (err) {
+			LOG_ERR("Failed to configure interrupt");
+		}
+
+		err = icm45686_bus_write(dev, REG_INT1_CONFIG0, &val, 1);
+		if (err) {
+			LOG_ERR("Failed to disable all INTs");
+		}
+
+		val = REG_INT1_CONFIG2_EN_OPEN_DRAIN(false) |
+		      REG_INT1_CONFIG2_EN_ACTIVE_HIGH(true);
+
+		err = icm45686_bus_write(dev, REG_INT1_CONFIG2, &val, 1);
+		if (err) {
+			LOG_ERR("Failed to configure INT as push-pull: %d", err);
+		}
+#if DT_HAS_COMPAT_ON_BUS_STATUS_OKAY(invensense_icm45686, i3c)
+	/** I3C devices use IBI only if no GPIO INT pin is defined. */
+	} else if (data->rtio.type == ICM45686_BUS_I3C) {
+		const struct i3c_iodev_data *iodev_data = data->rtio.iodev->data;
+
+		data->rtio.i3c.desc = i3c_device_find(iodev_data->bus,
+						      &data->rtio.i3c.id);
+		if (data->rtio.i3c.desc == NULL) {
+			LOG_ERR("Failed to find I3C device");
+			return -ENODEV;
+		}
+		data->rtio.i3c.desc->ibi_cb = icm45686_ibi_cb;
+
+		err = i3c_ibi_enable(data->rtio.i3c.desc);
+		if (err) {
+			LOG_ERR("Failed to enable IBI: %d", err);
+			return err;
+		}
+#endif
+	} else {
+		LOG_ERR("Interrupt GPIO not supplied");
+		return -ENODEV;
+	}
+
+	return 0;
+}
diff --git a/drivers/sensor/tdk/icm45686/icm45686_stream.h b/drivers/sensor/tdk/icm45686/icm45686_stream.h
new file mode 100644
index 00000000000..18f4a02be4f
--- /dev/null
+++ b/drivers/sensor/tdk/icm45686/icm45686_stream.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_ICM45686_STREAM_H_
+#define ZEPHYR_DRIVERS_SENSOR_ICM45686_STREAM_H_
+
+int icm45686_stream_init(const struct device *dev);
+
+void icm45686_stream_submit(const struct device *dev,
+			    struct rtio_iodev_sqe *iodev_sqe);
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_ICM45686_STREAM_H_ */
diff --git a/drivers/sensor/tdk/icm45686/icm45686_trigger.c b/drivers/sensor/tdk/icm45686/icm45686_trigger.c
new file mode 100644
index 00000000000..62411593446
--- /dev/null
+++ b/drivers/sensor/tdk/icm45686/icm45686_trigger.c
@@ -0,0 +1,214 @@
+/*
+ * Copyright (c) 2022 Intel Corporation
+ * Copyright (c) 2023 Google LLC
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/gpio.h>
+
+#include "icm45686.h"
+#include "icm45686_bus.h"
+#include "icm45686_trigger.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(ICM45686_TRIGGER, CONFIG_SENSOR_LOG_LEVEL);
+
+static void icm45686_gpio_callback(const struct device *dev,
+				   struct gpio_callback *cb,
+				   uint32_t pins)
+{
+	struct icm45686_data *data = CONTAINER_OF(cb,
+						  struct icm45686_data,
+						  triggers.cb);
+
+	ARG_UNUSED(dev);
+	ARG_UNUSED(pins);
+
+#if defined(CONFIG_ICM45686_TRIGGER_OWN_THREAD)
+	k_sem_give(&data->triggers.sem);
+#elif defined(CONFIG_ICM45686_TRIGGER_GLOBAL_THREAD)
+	k_work_submit(&data->triggers.work);
+#endif
+}
+
+static void icm45686_thread_cb(const struct device *dev)
+{
+	struct icm45686_data *data = dev->data;
+
+	(void)k_mutex_lock(&data->triggers.lock, K_FOREVER);
+
+	if (data->triggers.entry.handler) {
+		data->triggers.entry.handler(dev, &data->triggers.entry.trigger);
+	}
+
+	(void)k_mutex_unlock(&data->triggers.lock);
+}
+
+#if defined(CONFIG_ICM45686_TRIGGER_OWN_THREAD)
+
+static void icm45686_thread(void *p1, void *p2, void *p3)
+{
+	ARG_UNUSED(p2);
+	ARG_UNUSED(p3);
+
+	struct icm45686_data *data = p1;
+
+	while (true) {
+		k_sem_take(&data->triggers.sem, K_FOREVER);
+
+		icm45686_thread_cb(data->triggers.dev);
+	}
+}
+
+#elif defined(CONFIG_ICM45686_TRIGGER_GLOBAL_THREAD)
+
+static void icm45686_work_handler(struct k_work *work)
+{
+	struct icm45686_data *data = CONTAINER_OF(work,
+						  struct icm45686_data,
+						  triggers.work);
+
+	icm45686_thread_cb(data->triggers.dev);
+}
+
+#endif
+
+static int icm45686_enable_drdy(const struct device *dev, bool enable)
+{
+	uint8_t val;
+	int err;
+
+	err = icm45686_bus_read(dev, REG_INT1_CONFIG0, &val, 1);
+	if (err) {
+		return err;
+	}
+
+	val &= ~REG_INT1_CONFIG0_STATUS_EN_DRDY(true);
+	err = icm45686_bus_write(dev, REG_INT1_CONFIG0, &val, 1);
+	if (err) {
+		return err;
+	}
+
+	if (enable) {
+		val |= REG_INT1_CONFIG0_STATUS_EN_DRDY(true);
+	}
+
+	return icm45686_bus_write(dev, REG_INT1_CONFIG0, &val, 1);
+}
+
+int icm45686_trigger_set(const struct device *dev,
+			 const struct sensor_trigger *trig,
+			 sensor_trigger_handler_t handler)
+{
+	int err = 0;
+	struct icm45686_data *data = dev->data;
+
+	(void)k_mutex_lock(&data->triggers.lock, K_FOREVER);
+
+	switch (trig->type) {
+	case SENSOR_TRIG_DATA_READY:
+		data->triggers.entry.trigger = *trig;
+		data->triggers.entry.handler = handler;
+
+		if (handler) {
+			/* Enable data ready interrupt */
+			err = icm45686_enable_drdy(dev, true);
+		} else {
+			/* Disable data ready interrupt */
+			err = icm45686_enable_drdy(dev, false);
+		}
+		break;
+	default:
+		err = -ENOTSUP;
+		break;
+	}
+
+	(void)k_mutex_unlock(&data->triggers.lock);
+
+	return err;
+}
+
+int icm45686_trigger_init(const struct device *dev)
+{
+	const struct icm45686_config *cfg = dev->config;
+	struct icm45686_data *data = dev->data;
+	uint8_t val = 0;
+	int err;
+
+	err = k_mutex_init(&data->triggers.lock);
+	__ASSERT_NO_MSG(!err);
+
+	/** Needed to get back the device handle from the callback context */
+	data->triggers.dev = dev;
+
+#if defined(CONFIG_ICM45686_TRIGGER_OWN_THREAD)
+
+	err = k_sem_init(&data->triggers.sem, 0, 1);
+	__ASSERT_NO_MSG(!err);
+
+	(void)k_thread_create(&data->triggers.thread,
+			      data->triggers.thread_stack,
+			      K_KERNEL_STACK_SIZEOF(data->triggers.thread_stack),
+			      icm45686_thread,
+			      data,
+			      NULL,
+			      NULL,
+			      K_PRIO_COOP(CONFIG_ICM45686_THREAD_PRIORITY),
+			      0,
+			      K_NO_WAIT);
+
+#elif defined(CONFIG_ICM45686_TRIGGER_GLOBAL_THREAD)
+	k_work_init(&data->triggers.work, icm45686_work_handler);
+#endif
+
+	if (!cfg->int_gpio.port) {
+		LOG_ERR("Interrupt GPIO not supplied");
+		return -ENODEV;
+	}
+
+	if (!gpio_is_ready_dt(&cfg->int_gpio)) {
+		LOG_ERR("Interrupt GPIO not ready");
+		return -ENODEV;
+	}
+
+	err = gpio_pin_configure_dt(&cfg->int_gpio, GPIO_INPUT);
+	if (err) {
+		LOG_ERR("Failed to configure interrupt GPIO");
+		return -EIO;
+	}
+
+	gpio_init_callback(&data->triggers.cb,
+			icm45686_gpio_callback,
+			BIT(cfg->int_gpio.pin));
+
+	err = gpio_add_callback(cfg->int_gpio.port, &data->triggers.cb);
+	if (err) {
+		LOG_ERR("Failed to add interrupt callback");
+		return -EIO;
+	}
+
+	err = gpio_pin_interrupt_configure_dt(&cfg->int_gpio,
+					      GPIO_INT_EDGE_TO_ACTIVE);
+	if (err) {
+		LOG_ERR("Failed to configure interrupt");
+	}
+
+	err = icm45686_bus_write(dev, REG_INT1_CONFIG0, &val, 1);
+	if (err) {
+		LOG_ERR("Failed to disable all INTs");
+	}
+
+	val = REG_INT1_CONFIG2_EN_OPEN_DRAIN(false) |
+	      REG_INT1_CONFIG2_EN_ACTIVE_HIGH(true);
+
+	err = icm45686_bus_write(dev, REG_INT1_CONFIG2, &val, 1);
+	if (err) {
+		LOG_ERR("Failed to configure INT as push-pull: %d", err);
+	}
+
+	return err;
+}
diff --git a/drivers/sensor/tdk/icm45686/icm45686_trigger.h b/drivers/sensor/tdk/icm45686/icm45686_trigger.h
new file mode 100644
index 00000000000..0c15ff41ba2
--- /dev/null
+++ b/drivers/sensor/tdk/icm45686/icm45686_trigger.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2022 Intel Corporation
+ * Copyright (c) 2023 Google LLC
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_ICM45686_TRIGGER_H_
+#define ZEPHYR_DRIVERS_SENSOR_ICM45686_TRIGGER_H_
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/sensor.h>
+
+/* Configure triggers for the icm45686 sensor */
+int icm45686_trigger_set(const struct device *dev,
+			 const struct sensor_trigger *trig,
+			 sensor_trigger_handler_t handler);
+
+/* Initialization for icm45686 Triggers module */
+int icm45686_trigger_init(const struct device *dev);
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_ICM45686_TRIGGER_H_ */
diff --git a/drivers/sensor/tdk/icp10125/CMakeLists.txt b/drivers/sensor/tdk/icp10125/CMakeLists.txt
deleted file mode 100644
index 12279906928..00000000000
--- a/drivers/sensor/tdk/icp10125/CMakeLists.txt
+++ /dev/null
@@ -1,6 +0,0 @@
-# Copyright (c) 2022 Mizuki Agawa <agawa.mizuki@fujitsu.com>
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library()
-
-zephyr_library_sources(icp10125.c)
diff --git a/drivers/sensor/tdk/icp10125/Kconfig b/drivers/sensor/tdk/icp10125/Kconfig
deleted file mode 100644
index 96240de1be7..00000000000
--- a/drivers/sensor/tdk/icp10125/Kconfig
+++ /dev/null
@@ -1,23 +0,0 @@
-# ICP10125 barometric pressure/temperature sensor configuration options
-
-# Copyright (c) 2022 Mizuki Agawa <agawa.mizuki@fujitsu.com>
-# SPDX-License-Identifier: Apache-2.0
-
-menuconfig ICP10125
-	bool "ICP10125 Barometric Pressure & Temperature Sensor"
-	default y
-	depends on DT_HAS_INVENSENSE_ICP10125_ENABLED
-	select I2C
-	help
-	  Enable driver for ICP10125 barometric pressure/temperature sensor.
-
-if ICP10125
-
-config ICP10125_CHECK_CRC
-	bool "Check the CRC of measument data"
-	imply CRC
-	default y
-	help
-	  Verify the CRC checksum that appended to the measurement data.
-
-endif # ICP10125
diff --git a/drivers/sensor/tdk/icp10125/icp10125.c b/drivers/sensor/tdk/icp10125/icp10125.c
deleted file mode 100644
index 7393b5bbe64..00000000000
--- a/drivers/sensor/tdk/icp10125/icp10125.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * Copyright (c) 2022 Mizuki Agawa <agawa.mizuki@fujitsu.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DT_DRV_COMPAT invensense_icp10125
-
-#include <zephyr/drivers/i2c.h>
-#include <zephyr/drivers/sensor.h>
-#include <zephyr/logging/log.h>
-#include <zephyr/sys/byteorder.h>
-
-#ifdef CONFIG_ICP10125_CHECK_CRC
-#include <zephyr/sys/crc.h>
-#endif /* CONFIG_ICP10125_CHECK_CRC */
-
-LOG_MODULE_REGISTER(ICP10125, CONFIG_SENSOR_LOG_LEVEL);
-
-#define CRC_POLY	 0x31
-#define SENSOR_DATA_SIZE 2
-
-#define AMBIENT_TEMP_DATA_NUM		1
-#define PRESS_DATA_NUM			2
-#define PRESS_AND_AMBIENT_TEMP_DATA_NUM (AMBIENT_TEMP_DATA_NUM + PRESS_DATA_NUM)
-
-enum {
-	LOW_POWER,
-	NORMAL,
-	LOW_NOISE,
-	ULTRA_LOW_NOISE,
-	NUM_MEASURE_MODE
-};
-
-struct icp10125_data {
-	uint16_t raw_ambient_temp;
-	uint32_t raw_press;
-	float sensor_constants[4];
-};
-
-struct icp10125_dev_config {
-	struct i2c_dt_spec i2c;
-	uint8_t ambient_temp_mode;
-	uint8_t press_mode;
-};
-
-struct icp10125_cmd {
-	uint8_t data[2];
-};
-
-struct icp10125_sensor_data {
-	uint8_t data[2];
-	uint8_t crc;
-};
-
-struct icp10125_otp_read_setup {
-	struct icp10125_cmd cmd;
-	uint8_t data[3];
-} __packed __aligned(1);
-
-/* ambient temperature measurement command for each mode.
- * (Section 5.2 MEASUREMENT COMMANDS in the Datasheet)
- */
-static const struct icp10125_cmd ambient_temp_measurement_cmds[] = {
-	{{0x60, 0x9C}}, {{0x68, 0x25}}, {{0x70, 0xDF}}, {{0x78, 0x66}}
-};
-
-/* pressure measurement command for each mode.
- * (Section 5.2 MEASUREMENT COMMANDS in the Datasheet)
- */
-static const struct icp10125_cmd press_measurement_cmds[] = {
-	{{0x40, 0x1A}}, {{0x48, 0xA3}}, {{0x50, 0x59}}, {{0x59, 0xE0}}
-};
-
-/* Request preparation for OTP data read. It should issue before data read request.
- * (Section 5.2 MEASUREMENT COMMANDS in the Datasheet)
- */
-static const struct icp10125_otp_read_setup otp_read_setup = {
-		.cmd = {{0xC5, 0x95}},
-		.data = {0x00, 0x66, 0x9C}
-};
-
-/* OTP data read request.
- * After issue this command 2byte x 4 sensor constant value can readable.
- */
-static const struct icp10125_cmd otp_read_request_cmd = {{0xC7, 0xF7}};
-
-/* The max conversion time for each modes.
- * (Section 2.2 OPERATION MODES in the Datasheet)
- */
-static const uint32_t conv_time_max[] = {1800, 6300, 23800, 94500};
-
-/* The typical conversion time for each modes.
- * (Section 2.2 OPERATION MODES in the Datasheet)
- */
-static const uint32_t conv_time_typ[] = {1600, 5600, 20800, 83200};
-
-/* The Datasheet has no mention of the constants and formulas.
- * Instead, it shows only how to use it in the sample code.
- * Since there is no detailed description in the ICP10125 product manual,
- * the calculation of the pressure implements is the same as shown in
- * the 5.11 SAMPLE CODE: EXAMPLE C SYNTAX
- */
-
-static void icp10125_calculate_conversion_constants(const float *p_LUT, float *A, float *B,
-						    float *C)
-{
-	const float p_Pa[] = {45000.0, 80000.0, 105000.0};
-
-	*C = (p_LUT[0] * p_LUT[1] * (p_Pa[0] - p_Pa[1]) +
-	      p_LUT[1] * p_LUT[2] * (p_Pa[1] - p_Pa[2]) +
-	      p_LUT[2] * p_LUT[0] * (p_Pa[2] - p_Pa[0])) /
-	     (p_LUT[2] * (p_Pa[0] - p_Pa[1]) + p_LUT[0] * (p_Pa[1] - p_Pa[2]) +
-	      p_LUT[1] * (p_Pa[2] - p_Pa[0]));
-	*A = (p_Pa[0] * p_LUT[0] - p_Pa[1] * p_LUT[1] - (p_Pa[1] - p_Pa[0]) * (*C)) /
-	     (p_LUT[0] - p_LUT[1]);
-	*B = (p_Pa[0] - (*A)) * (p_LUT[0] + (*C));
-}
-
-static float icp10125_calc_calibrated_ambient_temp(const struct icp10125_data *data)
-{
-	return -45.f + 175.f / 65536.f * data->raw_ambient_temp;
-}
-
-static float icp10125_calc_calibrated_press(const struct icp10125_data *data)
-{
-	const float quadr_factor = 1 / 16777216.0;
-	const float offst_factor = 2048.0;
-	const float LUT_lower = 3.5 * (1 << 20);
-	const float LUT_upper = 11.5 * (1 << 20);
-	float t;
-	float in[3];
-	float A, B, C;
-
-	t = data->raw_ambient_temp - 32768.f;
-	in[0] = LUT_lower + (data->sensor_constants[0] * t * t) * quadr_factor;
-	in[1] = offst_factor * data->sensor_constants[3] +
-		(data->sensor_constants[1] * t * t) * quadr_factor;
-	in[2] = LUT_upper + (data->sensor_constants[2] * t * t) * quadr_factor;
-	icp10125_calculate_conversion_constants(in, &A, &B, &C);
-
-	return A + B / (C + data->raw_press);
-}
-
-/* End of porting the 5.11 SAMPLE CODE: EXAMPLE C SYNTAX */
-
-static int icp10125_read_otp(const struct device *dev)
-{
-	struct icp10125_data *data = dev->data;
-	struct icp10125_sensor_data sensor_data;
-
-	const struct icp10125_dev_config *cfg = dev->config;
-	int rc = 0;
-
-	rc = i2c_write_dt(&cfg->i2c, (uint8_t *)&otp_read_setup, sizeof(otp_read_setup));
-	if (rc < 0) {
-		LOG_ERR("Failed to write otp_read_setup.\n");
-		return rc;
-	}
-
-	for (size_t i = 0; i < ARRAY_SIZE(data->sensor_constants); i++) {
-		rc = i2c_write_dt(&cfg->i2c, (uint8_t *)&otp_read_request_cmd,
-				  sizeof(otp_read_request_cmd));
-		if (rc < 0) {
-			LOG_ERR("Failed to write otp_read_request.\n");
-			return rc;
-		}
-
-		rc = i2c_read_dt(&cfg->i2c, (uint8_t *)&sensor_data, sizeof(sensor_data));
-		if (rc < 0) {
-			LOG_ERR("Failed to read otp_read_request.\n");
-			return rc;
-		}
-
-		data->sensor_constants[i] = sys_get_be16(sensor_data.data);
-	}
-
-	return 0;
-}
-
-#ifdef CONFIG_ICP10125_CHECK_CRC
-static int icp10125_check_crc(const uint8_t *data, const size_t len)
-{
-	/* Details of CRC are described in Chapter 5 Section 8 of the product
-	 * specifications.
-	 */
-	return crc8(data, len, CRC_POLY, 0xFF, false);
-}
-#endif
-
-static int icp10125_measure(const struct i2c_dt_spec *i2c, const struct icp10125_cmd *cmds,
-			    const uint8_t mode, struct icp10125_sensor_data *sensor_data,
-			    const size_t data_num)
-{
-	int rc = 0;
-
-	rc = i2c_write_dt(i2c, (uint8_t *)&cmds[mode], sizeof(cmds[mode]));
-	if (rc < 0) {
-		LOG_ERR("Failed to start measurement.\n");
-		return rc;
-	}
-
-	/* Wait for the sensor to become readable.
-	 * First wait for the typical time and then read.
-	 * If that fails, wait until the time to surely became readable.
-	 */
-	k_sleep(K_USEC(conv_time_typ[mode]));
-	if (i2c_read_dt(i2c, (uint8_t *)sensor_data, sizeof(sensor_data[0]) * data_num) < 0) {
-		k_sleep(K_USEC(conv_time_max[mode] - conv_time_typ[mode]));
-		rc = i2c_read_dt(i2c, (uint8_t *)sensor_data, sizeof(sensor_data[0]) * data_num);
-		if (rc < 0) {
-			LOG_ERR("Failed to read measurement.\n");
-			return rc;
-		}
-	}
-
-#ifdef CONFIG_ICP10125_CHECK_CRC
-	/* Calculate CRC from Chapter 5 Section 8 of ICP10125 Product manuals. */
-	for (size_t i = 0; i < data_num; i++) {
-		if (!icp10125_check_crc(sensor_data[i].data, SENSOR_DATA_SIZE)) {
-			LOG_ERR("Sensor data has invalid CRC.\n");
-			return -EIO;
-		}
-	}
-#endif /* CONFIG_ICP10125_CHECK_CRC */
-
-	return 0;
-}
-
-static int icp10125_sample_fetch(const struct device *dev, const enum sensor_channel chan)
-{
-	struct icp10125_data *data = dev->data;
-	const struct icp10125_dev_config *cfg = dev->config;
-	uint8_t endian_conversion[3];
-	struct icp10125_sensor_data sensor_data[PRESS_AND_AMBIENT_TEMP_DATA_NUM] = {0};
-	int rc = 0;
-
-	if (!(chan == SENSOR_CHAN_AMBIENT_TEMP || chan == SENSOR_CHAN_PRESS ||
-	      chan == SENSOR_CHAN_ALL)) {
-		return -ENOTSUP;
-	}
-
-	if (chan == SENSOR_CHAN_AMBIENT_TEMP) {
-		rc = icp10125_measure(&cfg->i2c, ambient_temp_measurement_cmds,
-				      cfg->ambient_temp_mode, sensor_data, AMBIENT_TEMP_DATA_NUM);
-		if (rc < 0) {
-			return rc;
-		}
-
-		data->raw_ambient_temp = sys_get_be16(sensor_data[0].data);
-	} else {
-		rc = icp10125_measure(&cfg->i2c, press_measurement_cmds, cfg->press_mode,
-				      sensor_data, PRESS_AND_AMBIENT_TEMP_DATA_NUM);
-		if (rc < 0) {
-			return rc;
-		}
-
-		endian_conversion[0] = sensor_data[0].data[0];
-		endian_conversion[1] = sensor_data[0].data[1];
-		endian_conversion[2] = sensor_data[1].data[0];
-		data->raw_press = sys_get_be24(endian_conversion);
-		data->raw_ambient_temp = sys_get_be16(sensor_data[2].data);
-	}
-
-	return 0;
-}
-
-static void icp10125_convert_press_value(struct icp10125_data *data, struct sensor_value *val)
-{
-	sensor_value_from_float(val, icp10125_calc_calibrated_press(data) / 1000.f);
-}
-
-static void icp10125_convert_ambient_temp_value(struct icp10125_data *data,
-						struct sensor_value *val)
-{
-	sensor_value_from_float(val, icp10125_calc_calibrated_ambient_temp(data));
-}
-
-static int icp10125_channel_get(const struct device *dev, enum sensor_channel chan,
-				struct sensor_value *val)
-{
-	struct icp10125_data *data = dev->data;
-
-	if (chan == SENSOR_CHAN_AMBIENT_TEMP) {
-		icp10125_convert_ambient_temp_value(data, val);
-	} else if (chan == SENSOR_CHAN_PRESS) {
-		icp10125_convert_press_value(data, val);
-	} else {
-		return -ENOTSUP;
-	}
-
-	return 0;
-}
-
-static int icp10125_init(const struct device *dev)
-{
-	int rc = icp10125_read_otp(dev);
-
-	if (rc < 0) {
-		return rc;
-	}
-
-	return 0;
-}
-
-static DEVICE_API(sensor, icp10125_api_funcs) = {
-	.sample_fetch = icp10125_sample_fetch,
-	.channel_get = icp10125_channel_get,
-};
-
-#define ICP10125_DEFINE(inst)                                                                      \
-	static struct icp10125_data icp10125_drv_##inst;                                           \
-	static const struct icp10125_dev_config icp10125_config_##inst = {                         \
-		.i2c = I2C_DT_SPEC_INST_GET(inst),                                                 \
-		.ambient_temp_mode = DT_INST_ENUM_IDX(inst, temperature_measurement_mode),         \
-		.press_mode = DT_INST_ENUM_IDX(inst, pressure_measurement_mode)};                  \
-	DEVICE_DT_INST_DEFINE(inst, icp10125_init, NULL, &icp10125_drv_##inst,                     \
-			      &icp10125_config_##inst, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY,   \
-			      &icp10125_api_funcs);
-
-DT_INST_FOREACH_STATUS_OKAY(ICP10125_DEFINE)
diff --git a/drivers/sensor/tdk/icp101xx/CMakeLists.txt b/drivers/sensor/tdk/icp101xx/CMakeLists.txt
new file mode 100644
index 00000000000..35912eaf855
--- /dev/null
+++ b/drivers/sensor/tdk/icp101xx/CMakeLists.txt
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_compile_definitions_ifdef(CONFIG_CPU_HAS_FPU ICP101XX_DRV_USE_FLOATS)
+
+zephyr_library_sources(icp101xx_drv.c)
+zephyr_library_include_directories(.)
diff --git a/drivers/sensor/tdk/icp101xx/Kconfig b/drivers/sensor/tdk/icp101xx/Kconfig
new file mode 100644
index 00000000000..32aaea0bfde
--- /dev/null
+++ b/drivers/sensor/tdk/icp101xx/Kconfig
@@ -0,0 +1,13 @@
+# Copyright (c) 2024 TDK Invensense
+
+# ICP101xx High Accuracy, Low Power, Barometric Pressure and Temperature Sensor option
+
+# SPDX-License-Identifier: Apache-2.0
+config ICP101XX
+	bool "ICP101XX Barometric Pressure and Temperature Sensor"
+	default y
+	depends on DT_HAS_INVENSENSE_ICP101XX_ENABLED
+	select I2C
+	select USE_EMD_ICP101XX
+	help
+		Enable driver for ICP101XX barometric pressure/temperature sensors.
diff --git a/drivers/sensor/tdk/icp101xx/icp101xx_drv.c b/drivers/sensor/tdk/icp101xx/icp101xx_drv.c
new file mode 100644
index 00000000000..d198cec2b73
--- /dev/null
+++ b/drivers/sensor/tdk/icp101xx/icp101xx_drv.c
@@ -0,0 +1,259 @@
+/*
+ * Copyright (c) 2024 TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT invensense_icp101xx
+
+#include <math.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/init.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/pm/device.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/__assert.h>
+
+#include <zephyr/logging/log.h>
+
+#include "icp101xx_drv.h"
+
+LOG_MODULE_REGISTER(ICP101XX, CONFIG_SENSOR_LOG_LEVEL);
+
+#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 0
+#error "ICP101XX driver enabled without any compatible device in devicetree"
+#endif
+
+inline void inv_icp101xx_sleep_us(int us)
+{
+	k_sleep(K_USEC(us));
+}
+
+static int inv_io_hal_read_reg(void *ctx, uint8_t reg, uint8_t *rbuffer, uint32_t rlen)
+{
+	struct device *dev = (struct device *)ctx;
+	const struct icp101xx_config *cfg = (const struct icp101xx_config *)dev->config;
+
+	return i2c_read_dt(&cfg->i2c, (uint8_t *)rbuffer, rlen);
+}
+
+static int inv_io_hal_write_reg(void *ctx, uint8_t reg, const uint8_t *wbuffer, uint32_t wlen)
+{
+	struct device *dev = (struct device *)ctx;
+	const struct icp101xx_config *cfg = (const struct icp101xx_config *)dev->config;
+
+	return i2c_write_dt(&cfg->i2c, (uint8_t *)wbuffer, wlen);
+}
+
+static uint8_t get_timeout_ms(enum icp101xx_meas mode)
+{
+	switch (mode) {
+	case ICP101XX_MEAS_LOW_POWER_T_FIRST:
+	case ICP101XX_MEAS_LOW_POWER_P_FIRST:
+		return 2;
+	case ICP101XX_MEAS_NORMAL_T_FIRST:
+	case ICP101XX_MEAS_NORMAL_P_FIRST:
+		return 7;
+	case ICP101XX_MEAS_LOW_NOISE_T_FIRST:
+	case ICP101XX_MEAS_LOW_NOISE_P_FIRST:
+		return 24;
+	default:
+	case ICP101XX_MEAS_ULTRA_LOW_NOISE_T_FIRST:
+	case ICP101XX_MEAS_ULTRA_LOW_NOISE_P_FIRST:
+		return 95;
+	}
+}
+
+static uint8_t get_conversion_ms(enum icp101xx_meas mode)
+{
+	switch (mode) {
+	case ICP101XX_MEAS_LOW_POWER_T_FIRST:
+	case ICP101XX_MEAS_LOW_POWER_P_FIRST:
+		return 1;
+	case ICP101XX_MEAS_NORMAL_T_FIRST:
+	case ICP101XX_MEAS_NORMAL_P_FIRST:
+		return 5;
+	case ICP101XX_MEAS_LOW_NOISE_T_FIRST:
+	case ICP101XX_MEAS_LOW_NOISE_P_FIRST:
+		return 20;
+	default:
+	case ICP101XX_MEAS_ULTRA_LOW_NOISE_T_FIRST:
+	case ICP101XX_MEAS_ULTRA_LOW_NOISE_P_FIRST:
+		return 80;
+	}
+}
+
+#ifdef ICP101XX_DRV_USE_FLOATS
+#define ATMOSPHERICAL_PRESSURE_KPA ((float)101.325)
+#define TO_KELVIN(temp_C)          ((float)273.15 + temp_C)
+/*
+ * Constant in altitude formula:
+ * M*g/R = (0,0289644 * 9,80665 / 8,31432)
+ * with M the molar mass of air.
+ * with g the gravitational force acceleration.
+ * with R the universal gaz constant.
+ */
+#define HEIGHT_TO_PRESSURE_COEFF   ((float)0.03424)
+
+/*
+ * Constant in altitude formula:
+ * R / (M*g) = 8,31432 / (0,0289644 * 9,80665)
+ * with M the molar mass of air.
+ * with g the gravitational force acceleration.
+ * with R the universal gaz constant.
+ */
+#define PRESSURE_TO_HEIGHT_COEFF   ((float)29.27127)
+/*
+ * Constant for altitude formula:
+ * logarithm of pressure at 0m
+ * ln(101.325)
+ */
+#define LOG_ATMOSPHERICAL_PRESSURE ((float)4.61833)
+
+float convertToHeight(float pressure_kp, float temperature_C)
+{
+	return PRESSURE_TO_HEIGHT_COEFF * TO_KELVIN(temperature_C) *
+	       (LOG_ATMOSPHERICAL_PRESSURE - logf(pressure_kp));
+}
+#endif
+
+static int icp101xx_attr_set(const struct device *dev, enum sensor_channel chan,
+			     enum sensor_attribute attr, const struct sensor_value *val)
+{
+	int err = 0;
+	struct icp101xx_data *data = (struct icp101xx_data *)dev->data;
+
+	__ASSERT_NO_MSG(val != NULL);
+	if (chan == SENSOR_CHAN_PRESS) {
+		if (attr == SENSOR_ATTR_CONFIGURATION) {
+			if ((val->val1 >= ICP101XX_MEAS_LOW_POWER_T_FIRST) &&
+			    (val->val1 <= ICP101XX_MEAS_ULTRA_LOW_NOISE_P_FIRST)) {
+				data->icp_device.measurement_mode = val->val1;
+			} else {
+				LOG_ERR("Not supported ATTR value");
+				return -EINVAL;
+			}
+
+		} else {
+			LOG_ERR("Not supported ATTR");
+			return -EINVAL;
+		}
+	};
+	return err;
+}
+
+static int icp101xx_sample_fetch(const struct device *dev, const enum sensor_channel chan)
+{
+	struct icp101xx_data *data = (struct icp101xx_data *)dev->data;
+	int rc = 0;
+	uint64_t timeout;
+
+	if (!((chan == SENSOR_CHAN_AMBIENT_TEMP) || (chan == SENSOR_CHAN_PRESS) ||
+	      (chan == SENSOR_CHAN_ALTITUDE) || (chan == SENSOR_CHAN_ALL))) {
+		return -ENOTSUP;
+	}
+	rc = inv_icp101xx_enable_sensor(&data->icp_device, 1);
+	/* Compute timeout for the measure */
+	timeout = k_uptime_get() + get_timeout_ms(data->icp_device.measurement_mode);
+	/* Initial sleep waiting the sensor proceeds with the measure */
+	k_sleep(K_MSEC(get_conversion_ms(data->icp_device.measurement_mode)));
+	do {
+		k_sleep(K_USEC(200));
+		rc = inv_icp101xx_get_data(&data->icp_device, &(data->raw_pressure),
+					   &(data->raw_temperature), &(data->pressure),
+					   &(data->temperature));
+	} while ((rc != 0) && (k_uptime_get() <= timeout));
+	return rc;
+}
+
+static int icp101xx_channel_get(const struct device *dev, enum sensor_channel chan,
+				struct sensor_value *val)
+{
+
+	struct icp101xx_data *data = (struct icp101xx_data *)dev->data;
+
+	val->val1 = 0;
+	val->val2 = 0;
+
+	if (!((chan == SENSOR_CHAN_AMBIENT_TEMP) || (chan == SENSOR_CHAN_PRESS) ||
+	      (chan == SENSOR_CHAN_ALTITUDE))) {
+		return -ENOTSUP;
+	}
+	/* Zephyr expects kPa while ICP101xx returns Pa */
+	if (chan == SENSOR_CHAN_AMBIENT_TEMP) {
+#ifdef ICP101XX_DRV_USE_FLOATS
+		sensor_value_from_float(val, data->temperature);
+#else
+		val->val1 = data->temperature >> 4;
+		val->val2 = (data->temperature % 16) * 1000000 / 16;
+#endif
+	} else if (chan == SENSOR_CHAN_PRESS) {
+#ifdef ICP101XX_DRV_USE_FLOATS
+		sensor_value_from_float(val, data->pressure / 1000);
+#else
+		val->val1 = data->pressure / 1000;
+		val->val2 = (data->pressure % 1000) * 1000;
+#endif
+#ifdef ICP101XX_DRV_USE_FLOATS
+	} else if (chan == SENSOR_CHAN_ALTITUDE) {
+		float altitude = convertToHeight(data->pressure / 1000, data->temperature);
+
+		sensor_value_from_float(val, altitude);
+#endif
+	} else {
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static int icp101xx_init(const struct device *dev)
+{
+	int rc = 0;
+	struct icp101xx_data *data = (struct icp101xx_data *)dev->data;
+	const struct icp101xx_config *cfg = (const struct icp101xx_config *)dev->config;
+
+	memset(&(data->icp_device), 0, sizeof(data->icp_device));
+
+	data->icp_device.serif.context = (void *)dev;
+	data->icp_device.serif.read_reg = inv_io_hal_read_reg;
+	data->icp_device.serif.write_reg = inv_io_hal_write_reg;
+	/* maximum number of bytes allowed per serial read */
+	data->icp_device.serif.max_read = 2048;
+	/* maximum number of bytes allowed per serial write */
+	data->icp_device.serif.max_write = 2048;
+
+	rc = inv_icp101xx_soft_reset(&data->icp_device);
+	if (rc != 0) {
+		LOG_ERR("Soft reset error %d", rc);
+		return rc;
+	}
+	inv_icp101xx_init(&data->icp_device);
+	if (rc != 0) {
+		LOG_ERR("Init error %d", rc);
+		return rc;
+	}
+	data->icp_device.measurement_mode = cfg->mode;
+
+	/* successful init, return 0 */
+	return 0;
+}
+
+static DEVICE_API(sensor, icp101xx_api_funcs) = {
+	.sample_fetch = icp101xx_sample_fetch,
+	.channel_get = icp101xx_channel_get,
+	.attr_set = icp101xx_attr_set,
+};
+
+#define ICP101XX_DEFINE(inst)                                                                      \
+	static struct icp101xx_data icp101xx_drv_##inst;                                           \
+	static const struct icp101xx_config icp101xx_config_##inst = {                             \
+		.i2c = I2C_DT_SPEC_INST_GET(inst),                                                 \
+		.mode = DT_INST_ENUM_IDX(inst, mode),                                              \
+	};                                                                                         \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, icp101xx_init, NULL, &icp101xx_drv_##inst,              \
+			      &icp101xx_config_##inst, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY,   \
+			      &icp101xx_api_funcs);
+
+DT_INST_FOREACH_STATUS_OKAY(ICP101XX_DEFINE)
diff --git a/drivers/sensor/tdk/icp101xx/icp101xx_drv.h b/drivers/sensor/tdk/icp101xx/icp101xx_drv.h
new file mode 100644
index 00000000000..9ecac4257f2
--- /dev/null
+++ b/drivers/sensor/tdk/icp101xx/icp101xx_drv.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2023 TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_ICP101XXX_ICP101XXX_H_
+#define ZEPHYR_DRIVERS_SENSOR_ICP101XXX_ICP101XXX_H_
+
+#include <zephyr/types.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/sensor.h>
+#include "Icp101xx.h"
+#include "Icp101xxSerif.h"
+
+#define ICP101XX_BUS_I2C DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
+
+struct icp101xx_data {
+	int raw_pressure;
+	int raw_temperature;
+#ifdef ICP101XX_DRV_USE_FLOATS
+	float pressure;
+	float temperature;
+#else
+	int32_t pressure;
+	int32_t temperature;
+#endif
+	inv_icp101xx_t icp_device;
+};
+
+struct icp101xx_config {
+	struct i2c_dt_spec i2c;
+	int mode;
+};
+
+#endif
diff --git a/drivers/sensor/tdk/icp201xx/CMakeLists.txt b/drivers/sensor/tdk/icp201xx/CMakeLists.txt
new file mode 100644
index 00000000000..6bc760701d1
--- /dev/null
+++ b/drivers/sensor/tdk/icp201xx/CMakeLists.txt
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(icp201xx_drv.c)
+zephyr_library_sources_ifdef(CONFIG_SPI icp201xx_spi.c)
+zephyr_library_sources_ifdef(CONFIG_I2C icp201xx_i2c.c)
+
+zephyr_library_sources_ifdef(CONFIG_ICP201XX_TRIGGER icp201xx_trigger.c)
+zephyr_library_include_directories(.)
diff --git a/drivers/sensor/tdk/icp201xx/Kconfig b/drivers/sensor/tdk/icp201xx/Kconfig
new file mode 100644
index 00000000000..facb97d916f
--- /dev/null
+++ b/drivers/sensor/tdk/icp201xx/Kconfig
@@ -0,0 +1,25 @@
+# ICP201xx High Accuracy, Low Power, Barometric Pressure and Temperature Sensor IC
+#
+# Copyright (c) 2025 TDK Invensense
+#
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig ICP201XX
+	bool "ICP201xx Barometric Pressure and Temperature Sensor"
+	default y
+	depends on DT_HAS_INVENSENSE_ICP201XX_ENABLED
+	select I2C if $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICP201XX),i2c)
+	select SPI if $(dt_compat_on_bus,$(DT_COMPAT_INVENSENSE_ICP201XX),spi)
+	select USE_EMD_ICP201XX
+	select FPU if CPU_HAS_FPU
+	help
+		Enable driver for ICP101xx Barometric Pressure and Temperature Sensor.
+
+if ICP201XX
+
+module = ICP201XX
+thread_priority = 10
+thread_stack_size = 1024
+source "drivers/sensor/Kconfig.trigger_template"
+
+endif # ICP201XX
diff --git a/drivers/sensor/tdk/icp201xx/icp201xx_drv.c b/drivers/sensor/tdk/icp201xx/icp201xx_drv.c
new file mode 100644
index 00000000000..dd385a0a1e9
--- /dev/null
+++ b/drivers/sensor/tdk/icp201xx/icp201xx_drv.c
@@ -0,0 +1,445 @@
+/*
+ * Copyright (c) 2025 TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/init.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/pm/device.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/__assert.h>
+
+#include <zephyr/logging/log.h>
+
+#include "icp201xx_drv.h"
+#include "Icp201xxDriver.h"
+
+LOG_MODULE_REGISTER(ICP201XX, CONFIG_SENSOR_LOG_LEVEL);
+
+#ifdef CONFIG_FPU
+#include <math.h>
+#define ATMOSPHERICAL_PRESSURE_KPA ((float)101.325)
+#define TO_KELVIN(temp_C)          (((float)273.15) + temp_C)
+/* Constant in altitude formula:
+ * M*g/R = (0,0289644 * 9,80665 / 8,31432)
+ * with M the molar mass of air.
+ * with g the gravitational force acceleration.
+ * with R the universal gaz constant.
+ */
+#define HEIGHT_TO_PRESSURE_COEFF   ((float)0.03424)
+
+/* Constant in altitude formula:
+ * R / (M*g) = 8,31432 / (0,0289644 * 9,80665)
+ * with M the molar mass of air.
+ * with g the gravitational force acceleration.
+ * with R the universal gaz constant.
+ */
+#define PRESSURE_TO_HEIGHT_COEFF   ((float)29.27127)
+/* Constant for altitude formula:
+ * logarithm of pressure at 0m
+ * ln(101.325)
+ */
+#define LOG_ATMOSPHERICAL_PRESSURE ((float)4.61833)
+#endif
+
+#define IO_DRIVE_STRENGTH_ADDR 0x0D
+
+void inv_icp201xx_sleep_us(int us)
+{
+	k_sleep(K_USEC(us));
+}
+
+static int inv_io_hal_read_reg(void *ctx, uint8_t reg, uint8_t *rbuffer, uint32_t rlen)
+{
+	struct device *dev = (struct device *)ctx;
+	const struct icp201xx_config *cfg = (const struct icp201xx_config *)dev->config;
+
+	return cfg->bus_io->read(&cfg->bus, reg, rbuffer, rlen);
+}
+
+static int inv_io_hal_write_reg(void *ctx, uint8_t reg, const uint8_t *wbuffer, uint32_t wlen)
+{
+	struct device *dev = (struct device *)ctx;
+	const struct icp201xx_config *cfg = (const struct icp201xx_config *)dev->config;
+
+	return cfg->bus_io->write(&cfg->bus, reg, (uint8_t *)wbuffer, wlen);
+}
+
+#ifdef CONFIG_FPU
+static float convertToHeight(float pressure_kp, float temperature_C)
+{
+	return PRESSURE_TO_HEIGHT_COEFF * TO_KELVIN(temperature_C) *
+	       (LOG_ATMOSPHERICAL_PRESSURE - logf(pressure_kp));
+}
+#endif
+
+/*
+ * ICP201xx warm up.
+ * If FIR filter is enabled, it will cause a settling effect on the first 14 pressure values.
+ * Therefore the first 14 pressure output values are discarded.
+ *
+ */
+void inv_icp201xx_app_warmup(inv_icp201xx_t *icp_device, icp201xx_op_mode_t op_mode,
+			     icp201xx_meas_mode_t meas_mode)
+{
+	volatile uint8_t fifo_packets = 0;
+	uint8_t fifo_packets_to_skip = 14;
+
+	do {
+		fifo_packets = 0;
+		if (!inv_icp201xx_get_fifo_count(icp_device, (uint8_t *)&fifo_packets) &&
+		    (fifo_packets >= fifo_packets_to_skip)) {
+			uint8_t i_status = 0;
+
+			inv_icp201xx_flush_fifo(icp_device);
+
+			inv_icp201xx_get_int_status(icp_device, &i_status);
+			if (i_status) {
+				inv_icp201xx_clear_int_status(icp_device, i_status);
+			}
+			break;
+		}
+		inv_icp201xx_sleep_us(2000);
+	} while (1);
+}
+
+static int icp201xx_attr_set(const struct device *dev, enum sensor_channel chan,
+			     enum sensor_attribute attr, const struct sensor_value *val)
+{
+	int err = 0;
+	struct icp201xx_data *data = (struct icp201xx_data *)dev->data;
+
+	__ASSERT_NO_MSG(val != NULL);
+	icp201xx_mutex_lock(dev);
+	if (chan == SENSOR_CHAN_PRESS) {
+		if (attr == SENSOR_ATTR_CONFIGURATION) {
+			if ((val->val1 >= ICP201XX_OP_MODE0) && (val->val1 <= ICP201XX_OP_MODE4)) {
+				data->op_mode = val->val1;
+				err = inv_icp201xx_soft_reset(&(data->icp_device));
+				err = inv_icp201xx_config(&(data->icp_device), data->op_mode,
+							  ICP201XX_FIFO_READOUT_MODE_PRES_TEMP);
+				inv_icp201xx_app_warmup(&(data->icp_device), data->op_mode,
+							ICP201XX_MEAS_MODE_CONTINUOUS);
+			} else {
+				LOG_ERR("Not supported ATTR value");
+				icp201xx_mutex_unlock(dev);
+				return -EINVAL;
+			}
+#ifdef CONFIG_ICP201XX_TRIGGER
+		} else if (attr == SENSOR_ATTR_SLOPE_TH) {
+			data->pressure_change = *val;
+		} else if ((attr == SENSOR_ATTR_LOWER_THRESH) ||
+			   (attr == SENSOR_ATTR_UPPER_THRESH)) {
+			if (val->val1 > 0) {
+				data->pressure_threshold = *val;
+			} else {
+				LOG_ERR("Not supported ATTR value");
+				icp201xx_mutex_unlock(dev);
+				return -EINVAL;
+			}
+#endif
+		} else {
+			LOG_ERR("Not supported ATTR");
+			icp201xx_mutex_unlock(dev);
+			return -EINVAL;
+		}
+	};
+	icp201xx_mutex_unlock(dev);
+	return err;
+}
+
+static int icp201xx_sample_fetch(const struct device *dev, const enum sensor_channel chan)
+{
+	struct icp201xx_data *data = (struct icp201xx_data *)dev->data;
+	uint8_t fifo_packets;
+	uint8_t fifo_data[6];
+
+	icp201xx_mutex_lock(dev);
+
+	/** Read measurements count in FIFO **/
+	if (inv_icp201xx_get_fifo_count(&(data->icp_device), &fifo_packets)) {
+		icp201xx_mutex_unlock(dev);
+		return -2;
+	}
+	if (fifo_packets == 0) {
+		icp201xx_mutex_unlock(dev);
+		return -1;
+	}
+
+	for (int i = 0; i < fifo_packets; i++) {
+		inv_icp201xx_get_fifo_data(&(data->icp_device), 1, fifo_data);
+		if (data->icp_device.serif.if_mode == ICP201XX_IF_I2C) {
+			/*
+			 * Perform dummy read to 0x00 register as last transaction after FIFO read
+			 * for I2C interface
+			 */
+			do {
+				uint8_t dummy_reg = 0;
+
+				inv_io_hal_read_reg((struct device *)dev, 0, &dummy_reg, 1);
+			} while (0);
+		}
+	}
+	inv_icp201xx_process_raw_data(&(data->icp_device), 1, fifo_data, &data->raw_pressure,
+				      &data->raw_temperature);
+	icp201xx_mutex_unlock(dev);
+	return 0;
+}
+
+static void icp201xx_convert_pressure(struct sensor_value *val, int32_t raw_val)
+{
+	/* Raw value is coded on 20-bits */
+	if (raw_val & 0x080000) {
+		raw_val |= 0xFFF00000;
+	}
+	/* P = (POUT/2^17)*40kPa + 70kPa */
+	val->val1 = (raw_val * 40) / 131072 + 70;
+	val->val2 = ((uint64_t)(raw_val * 40) % 131072) * 1000000 / 131072;
+}
+
+static void icp201xx_convert_temperature(struct sensor_value *val, int32_t raw_val)
+{
+	/* Raw value is coded on 20-bits */
+	if (raw_val & 0x080000) {
+		raw_val |= 0xFFF00000;
+	}
+	/* T = (TOUT/2^18)*65C + 25C */
+	val->val1 = (raw_val * 65) / 262144 + 25;
+	val->val2 = ((uint64_t)(raw_val * 65) % 262144) * 1000000 / 262144;
+}
+
+static int icp201xx_channel_get(const struct device *dev, enum sensor_channel chan,
+				struct sensor_value *val)
+{
+	struct icp201xx_data *data = (struct icp201xx_data *)dev->data;
+
+	if (!(chan == SENSOR_CHAN_AMBIENT_TEMP || chan == SENSOR_CHAN_PRESS ||
+	      chan == SENSOR_CHAN_ALTITUDE)) {
+		return -ENOTSUP;
+	}
+	icp201xx_mutex_lock(dev);
+
+	if (chan == SENSOR_CHAN_PRESS) {
+		icp201xx_convert_pressure(val, data->raw_pressure);
+	} else if (chan == SENSOR_CHAN_AMBIENT_TEMP) {
+		icp201xx_convert_temperature(val, data->raw_temperature);
+#ifdef CONFIG_FPU
+	} else if (chan == SENSOR_CHAN_ALTITUDE) {
+		struct sensor_value pressure_val, temp_val;
+		float pressure, temperature, altitude;
+
+		icp201xx_convert_pressure(&pressure_val, data->raw_pressure);
+		icp201xx_convert_temperature(&temp_val, data->raw_pressure);
+		pressure = pressure_val.val1 + ((float)pressure_val.val2 / 1000000);
+		temperature = temp_val.val1 + ((float)temp_val.val2 / 1000000);
+		altitude = convertToHeight(pressure, temperature);
+		sensor_value_from_float(val, altitude);
+#endif
+	} else {
+		icp201xx_mutex_unlock(dev);
+		return -ENOTSUP;
+	}
+
+	icp201xx_mutex_unlock(dev);
+	return 0;
+}
+
+static int icp201xx_set_drive_strength(const struct device *dev, uint8_t drive)
+{
+	int rc = 0;
+	const uint8_t active_mode = 0x4;
+	const uint8_t normal_mode = 0x0;
+	const uint8_t unlock = 0x1F;
+	const uint8_t lock = 0x0;
+
+	inv_icp201xx_sleep_us(4000);
+
+	/* Set Active power mode */
+	rc |= inv_io_hal_write_reg((struct device *)dev, MPUREG_MODE_SELECT, &active_mode, 1);
+	inv_icp201xx_sleep_us(4000);
+
+	/* Unlock main register write access */
+	rc |= inv_io_hal_write_reg((struct device *)dev, MPUREG_MASTER_LOCK, &unlock, 1);
+	inv_icp201xx_sleep_us(4000);
+
+	/* Write IO drive strength */
+	rc |= inv_io_hal_write_reg((struct device *)dev, IO_DRIVE_STRENGTH_ADDR, &drive, 1);
+
+	/* Lock main register write access */
+	rc |= inv_io_hal_write_reg((struct device *)dev, MPUREG_MASTER_LOCK, &lock, 1);
+
+	/* Set Normal power mode */
+	rc |= inv_io_hal_write_reg((struct device *)dev, MPUREG_MODE_SELECT, &normal_mode, 1);
+
+	inv_icp201xx_sleep_us(4000);
+
+	return rc;
+}
+
+static int icp201xx_init(const struct device *dev)
+{
+	struct icp201xx_data *data = (struct icp201xx_data *)dev->data;
+	struct icp201xx_config *config = (struct icp201xx_config *)dev->config;
+	inv_icp201xx_serif_t icp_serif;
+	int rc = 0;
+	uint8_t who_am_i;
+	uint8_t icp_version;
+
+	icp_serif.if_mode = config->if_mode;
+
+	/* Initialize serial interface between MCU and Icp201xx */
+	icp_serif.context = (void *)dev;
+	icp_serif.read_reg = inv_io_hal_read_reg;
+	icp_serif.write_reg = inv_io_hal_write_reg;
+	icp_serif.max_read = 2048;  /* maximum number of bytes allowed per serial read */
+	icp_serif.max_write = 2048; /* maximum number of bytes allowed per serial write */
+
+	data->op_mode = config->op_mode;
+
+	rc = icp201xx_set_drive_strength(dev, config->drive_strength);
+	if (rc != INV_ERROR_SUCCESS) {
+		LOG_ERR("Drive strength error");
+		return rc;
+	}
+
+	rc = inv_icp201xx_init(&(data->icp_device), &icp_serif);
+	if (rc != INV_ERROR_SUCCESS) {
+		LOG_ERR("Init error");
+		return rc;
+	}
+
+	rc = inv_icp201xx_soft_reset(&(data->icp_device));
+	if (rc != INV_ERROR_SUCCESS) {
+		LOG_ERR("Reset error");
+		return rc;
+	}
+
+	/* Check WHOAMI */
+	rc = inv_icp201xx_get_devid_version(&(data->icp_device), &who_am_i, &icp_version);
+	if (rc != 0) {
+		LOG_ERR("Device id error");
+		return -2;
+	}
+
+	if (who_am_i != EXPECTED_DEVICE_ID) {
+		LOG_ERR("Wrong device id");
+		return -3;
+	}
+
+	/* Boot up OTP config */
+	rc = inv_icp201xx_OTP_bootup_cfg(&(data->icp_device));
+	if (rc != 0) {
+		LOG_ERR("Bootup error");
+		return rc;
+	}
+	rc = inv_icp201xx_soft_reset(&(data->icp_device));
+	if (rc != 0) {
+		LOG_ERR("Reset error");
+		return rc;
+	}
+	rc = inv_icp201xx_config(&(data->icp_device), data->op_mode,
+				 ICP201XX_FIFO_READOUT_MODE_PRES_TEMP);
+	if (rc != 0) {
+		LOG_ERR("Config error");
+		return rc;
+	}
+	inv_icp201xx_app_warmup(&(data->icp_device), data->op_mode, ICP201XX_MEAS_MODE_CONTINUOUS);
+
+	if (IS_ENABLED(CONFIG_ICP201XX_TRIGGER)) {
+		rc = icp201xx_trigger_init(dev);
+		if (rc < 0) {
+			LOG_ERR("Failed to initialize interrupt.");
+			return rc;
+		}
+	}
+
+	/* successful init, return 0 */
+	return 0;
+}
+
+void icp201xx_mutex_lock(const struct device *dev)
+{
+#ifdef CONFIG_ICP201XX_TRIGGER
+	const struct icp201xx_config *config = dev->config;
+
+	if (config->gpio_int.port) {
+		struct icp201xx_data *data = dev->data;
+
+		k_mutex_lock(&data->mutex, K_FOREVER);
+	}
+#else
+	ARG_UNUSED(dev);
+#endif
+}
+
+void icp201xx_mutex_unlock(const struct device *dev)
+{
+#ifdef CONFIG_ICP201XX_TRIGGER
+	const struct icp201xx_config *config = dev->config;
+
+	if (config->gpio_int.port) {
+		struct icp201xx_data *data = dev->data;
+
+		k_mutex_unlock(&data->mutex);
+	}
+#else
+	ARG_UNUSED(dev);
+#endif
+}
+
+static DEVICE_API(sensor, icp201xx_api_funcs) = {.sample_fetch = icp201xx_sample_fetch,
+							    .channel_get = icp201xx_channel_get,
+							    .attr_set = icp201xx_attr_set,
+#ifdef CONFIG_ICP201XX_TRIGGER
+							    .trigger_set = icp201xx_trigger_set
+#endif
+};
+
+/* Common initialization for icp201xx_config */
+#define ICP201XX_CONFIG(inst)                                              \
+	IF_ENABLED(CONFIG_ICP201XX_TRIGGER,                                  \
+		(.gpio_int = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, {0}),)) \
+		.op_mode = DT_INST_ENUM_IDX(inst, op_mode),                    \
+		.drive_strength = DT_INST_ENUM_IDX(inst, drive_strength)
+
+/* Initializes a struct icp201xx_config for an instance on an I2C bus. */
+#define ICP201XX_CONFIG_I2C(inst)                          \
+	{                                                      \
+		.if_mode = ICP201XX_IF_I2C,                        \
+		.bus.i2c = I2C_DT_SPEC_INST_GET(inst),                 \
+		.bus_io = &icp201xx_bus_io_i2c,                    \
+		ICP201XX_CONFIG(inst)                                  \
+	}
+
+/* Initializes a struct icp201xx_config for an instance on a SPI bus. */
+#define ICP201XX_CONFIG_SPI(inst)                                  \
+	{                                                              \
+		.if_mode = ICP201XX_IF_4_WIRE_SPI,                         \
+		.bus.spi = SPI_DT_SPEC_INST_GET(inst,                      \
+			(SPI_OP_MODE_MASTER | SPI_WORD_SET(8) |    \
+			SPI_TRANSFER_MSB | SPI_FULL_DUPLEX |      \
+			SPI_MODE_CPHA | SPI_MODE_CPOL),           \
+			0),                                        \
+		.bus_io = &icp201xx_bus_io_spi,                            \
+		ICP201XX_CONFIG(inst)                                          \
+	}
+
+/*
+ * Main instantiation macro, which selects the correct bus-specific
+ * instantiation macros for the instance.
+ */
+#define ICP201XX_DEFINE(inst)                                            \
+	static struct icp201xx_data icp201xx_drv_##inst;                       \
+	static const struct icp201xx_config icp201xx_config_##inst =           \
+		COND_CODE_1(DT_INST_ON_BUS(inst, spi),                               \
+		(ICP201XX_CONFIG_SPI(inst)),	                                       \
+		(ICP201XX_CONFIG_I2C(inst)));                                        \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, icp201xx_init, NULL, &icp201xx_drv_##inst, \
+		&icp201xx_config_##inst, POST_KERNEL, CONFIG_SENSOR_INIT_PRIORITY,   \
+		&icp201xx_api_funcs);
+
+#define DT_DRV_COMPAT invensense_icp201xx
+DT_INST_FOREACH_STATUS_OKAY(ICP201XX_DEFINE)
diff --git a/drivers/sensor/tdk/icp201xx/icp201xx_drv.h b/drivers/sensor/tdk/icp201xx/icp201xx_drv.h
new file mode 100644
index 00000000000..32bc02991b2
--- /dev/null
+++ b/drivers/sensor/tdk/icp201xx/icp201xx_drv.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2025 TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_ICP201XXX_ICP101XXX_H_
+#define ZEPHYR_DRIVERS_SENSOR_ICP201XXX_ICP101XXX_H_
+
+#include <zephyr/types.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/drivers/sensor.h>
+#include "Icp201xx.h"
+#include "Icp201xxSerif.h"
+
+union icp201xx_bus {
+#if CONFIG_SPI
+	struct spi_dt_spec spi;
+#endif
+#if CONFIG_I2C
+	struct i2c_dt_spec i2c;
+#endif
+};
+
+typedef int (*icp201xx_reg_read_fn)(const union icp201xx_bus *bus, uint8_t reg, uint8_t *buf,
+				    uint32_t size);
+typedef int (*icp201xx_reg_write_fn)(const union icp201xx_bus *bus, uint8_t reg, uint8_t *buf,
+				     uint32_t size);
+
+struct icp201xx_bus_io {
+	icp201xx_reg_read_fn read;
+	icp201xx_reg_write_fn write;
+};
+
+extern const struct icp201xx_bus_io icp201xx_bus_io_spi;
+extern const struct icp201xx_bus_io icp201xx_bus_io_i2c;
+
+struct icp201xx_data {
+	int32_t raw_pressure;
+	int32_t raw_temperature;
+	icp201xx_op_mode_t op_mode;
+	inv_icp201xx_t icp_device;
+
+#ifdef CONFIG_ICP201XX_TRIGGER
+	struct sensor_value pressure_change;
+	struct sensor_value pressure_threshold;
+	const struct device *dev;
+	struct gpio_callback gpio_cb;
+	sensor_trigger_handler_t drdy_handler;
+	sensor_trigger_handler_t delta_handler;
+	sensor_trigger_handler_t threshold_handler;
+	const struct sensor_trigger *drdy_trigger;
+	const struct sensor_trigger *delta_trigger;
+	const struct sensor_trigger *threshold_trigger;
+	struct k_mutex mutex;
+#ifdef CONFIG_ICP201XX_TRIGGER_OWN_THREAD
+	K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_ICP201XX_THREAD_STACK_SIZE);
+	struct k_thread thread;
+	struct k_sem gpio_sem;
+#endif
+#ifdef CONFIG_ICP201XX_TRIGGER_GLOBAL_THREAD
+	struct k_work work;
+#endif
+#endif
+};
+
+struct icp201xx_config {
+	union icp201xx_bus bus;
+	const struct icp201xx_bus_io *bus_io;
+	icp201xx_if_t if_mode;
+	struct gpio_dt_spec gpio_int;
+	icp201xx_op_mode_t op_mode;
+	uint8_t drive_strength;
+};
+
+int icp201xx_trigger_set(const struct device *dev, const struct sensor_trigger *trig,
+			 sensor_trigger_handler_t handler);
+
+int icp201xx_trigger_init(const struct device *dev);
+
+void icp201xx_mutex_lock(const struct device *dev);
+void icp201xx_mutex_unlock(const struct device *dev);
+void inv_icp201xx_app_warmup(inv_icp201xx_t *icp_device, icp201xx_op_mode_t op_mode,
+			     icp201xx_meas_mode_t meas_mode);
+#endif
diff --git a/drivers/sensor/tdk/icp201xx/icp201xx_i2c.c b/drivers/sensor/tdk/icp201xx/icp201xx_i2c.c
new file mode 100644
index 00000000000..b84a9af8260
--- /dev/null
+++ b/drivers/sensor/tdk/icp201xx/icp201xx_i2c.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2025 TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Bus-specific functionality for ICP201XX accessed via I2C.
+ */
+
+#include "icp201xx_drv.h"
+
+static int icp201xx_read_reg_i2c(const union icp201xx_bus *bus, uint8_t reg, uint8_t *rbuffer,
+				 uint32_t rlen)
+{
+
+	return i2c_burst_read_dt(&bus->i2c, reg, (uint8_t *)rbuffer, rlen);
+}
+
+static int icp201xx_write_reg_i2c(const union icp201xx_bus *bus, uint8_t reg, uint8_t *wbuffer,
+				  uint32_t wlen)
+{
+	return i2c_burst_write_dt(&bus->i2c, reg, wbuffer, wlen);
+}
+
+const struct icp201xx_bus_io icp201xx_bus_io_i2c = {
+	.read = icp201xx_read_reg_i2c,
+	.write = icp201xx_write_reg_i2c,
+};
diff --git a/drivers/sensor/tdk/icp201xx/icp201xx_spi.c b/drivers/sensor/tdk/icp201xx/icp201xx_spi.c
new file mode 100644
index 00000000000..983a01c64dc
--- /dev/null
+++ b/drivers/sensor/tdk/icp201xx/icp201xx_spi.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2025 TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Bus-specific functionality for ICP201XX accessed via SPI.
+ */
+
+#include "icp201xx_drv.h"
+
+#define ICP201XX_SERIF_SPI_REG_WRITE_CMD 0X33
+#define ICP201XX_SERIF_SPI_REG_READ_CMD  0X3C
+static int icp201xx_read_reg_spi(const union icp201xx_bus *bus, uint8_t reg, uint8_t *rbuffer,
+				 uint32_t rlen)
+{
+	if (reg != 0) {
+		int rc = 0;
+
+		uint8_t cmd[] = {ICP201XX_SERIF_SPI_REG_READ_CMD, reg};
+		const struct spi_buf tx_buf = {.buf = cmd, .len = 2};
+		const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1};
+		struct spi_buf rx_buf[] = {{.buf = NULL, .len = 2}, {.buf = rbuffer, .len = rlen}};
+		const struct spi_buf_set rx = {.buffers = rx_buf, .count = 2};
+
+		rc = spi_transceive_dt(&bus->spi, &tx, &rx);
+
+		return rc;
+	}
+	return 0;
+}
+
+static int icp201xx_write_reg_spi(const union icp201xx_bus *bus, uint8_t reg, uint8_t *wbuffer,
+				  uint32_t wlen)
+{
+	if (reg != 0) {
+		int rc = 0;
+		uint8_t cmd[] = {ICP201XX_SERIF_SPI_REG_WRITE_CMD, reg};
+		const struct spi_buf tx_buf[] = {{.buf = cmd, .len = 2},
+						 {.buf = (uint8_t *)wbuffer, .len = wlen}};
+		const struct spi_buf_set tx = {.buffers = tx_buf, .count = 2};
+
+		rc = spi_write_dt(&bus->spi, &tx);
+		return rc;
+	}
+	return 0;
+}
+
+const struct icp201xx_bus_io icp201xx_bus_io_spi = {
+	.read = icp201xx_read_reg_spi,
+	.write = icp201xx_write_reg_spi,
+};
diff --git a/drivers/sensor/tdk/icp201xx/icp201xx_trigger.c b/drivers/sensor/tdk/icp201xx/icp201xx_trigger.c
new file mode 100644
index 00000000000..46a2dc0339a
--- /dev/null
+++ b/drivers/sensor/tdk/icp201xx/icp201xx_trigger.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright (c) 2025 TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/gpio.h>
+#include "icp201xx_drv.h"
+#include "Icp201xxDriver.h"
+
+LOG_MODULE_DECLARE(ICP201XX, CONFIG_SENSOR_LOG_LEVEL);
+
+static void icp201xx_gpio_callback(const struct device *dev, struct gpio_callback *cb,
+				   uint32_t pins)
+{
+	struct icp201xx_data *drv_data = CONTAINER_OF(cb, struct icp201xx_data, gpio_cb);
+	const struct icp201xx_config *cfg = (const struct icp201xx_config *)drv_data->dev->config;
+
+	ARG_UNUSED(pins);
+	gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_DISABLE);
+
+#if defined(CONFIG_ICP201XX_TRIGGER_OWN_THREAD)
+	k_sem_give(&drv_data->gpio_sem);
+#elif defined(CONFIG_ICP201XX_TRIGGER_GLOBAL_THREAD)
+	k_work_submit(&drv_data->work);
+#endif
+}
+
+static void icp201xx_thread_cb(const struct device *dev)
+{
+	struct icp201xx_data *drv_data = dev->data;
+	const struct icp201xx_config *cfg = dev->config;
+	uint8_t i_status;
+
+	icp201xx_mutex_lock(dev);
+	gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_DISABLE);
+
+	inv_icp201xx_get_int_status(&drv_data->icp_device, &i_status);
+	if (i_status) {
+		if ((i_status & ICP201XX_INT_STATUS_FIFO_WMK_HIGH) &&
+		    (drv_data->drdy_handler != NULL)) {
+			drv_data->drdy_handler(dev, drv_data->drdy_trigger);
+		}
+		if ((i_status & ICP201XX_INT_STATUS_PRESS_DELTA) &&
+		    (drv_data->delta_handler != NULL)) {
+			drv_data->delta_handler(dev, drv_data->delta_trigger);
+		}
+		if ((i_status & ICP201XX_INT_STATUS_PRESS_ABS) &&
+		    (drv_data->threshold_handler != NULL)) {
+			drv_data->threshold_handler(dev, drv_data->threshold_trigger);
+		}
+		inv_icp201xx_clear_int_status(&drv_data->icp_device, i_status);
+	}
+	gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_LEVEL_LOW);
+	icp201xx_mutex_unlock(dev);
+}
+
+#if defined(CONFIG_ICP201XX_TRIGGER_OWN_THREAD)
+static void icp201xx_thread(void *p1, void *p2, void *p3)
+{
+	ARG_UNUSED(p2);
+	ARG_UNUSED(p3);
+	struct device *dev = (struct device *)p1;
+	struct icp201xx_data *drv_data = (struct icp201xx_data *)dev->data;
+
+	while (1) {
+		k_sem_take(&drv_data->gpio_sem, K_FOREVER);
+		icp201xx_thread_cb(dev);
+	}
+}
+#elif defined(CONFIG_ICP201XX_TRIGGER_GLOBAL_THREAD)
+static void icp201xx_work_handler(struct k_work *work)
+{
+	struct icp201xx_data *data = CONTAINER_OF(work, struct icp201xx_data, work);
+
+	icp201xx_thread_cb(data->dev);
+}
+#endif
+
+static int icp201xx_fifo_interrupt(const struct device *dev, uint8_t fifo_watermark)
+{
+	int rc = 0;
+	struct icp201xx_data *data = (struct icp201xx_data *)dev->data;
+
+	inv_icp201xx_flush_fifo(&(data->icp_device));
+
+	rc |= inv_icp201xx_set_fifo_notification_config(
+		&(data->icp_device), ICP201XX_INT_MASK_FIFO_WMK_HIGH, fifo_watermark, 0);
+
+	inv_icp201xx_app_warmup(&(data->icp_device), data->op_mode, ICP201XX_MEAS_MODE_CONTINUOUS);
+	return rc;
+}
+
+static int icp201xx_pressure_interrupt(const struct device *dev, struct sensor_value pressure)
+{
+	int16_t pressure_value, pressure_delta_value;
+	uint8_t int_mask = 0;
+	int rc = 0;
+	struct icp201xx_data *data = (struct icp201xx_data *)dev->data;
+
+	inv_icp201xx_get_press_notification_config(&(data->icp_device), &int_mask, &pressure_value,
+						   &pressure_delta_value);
+	/* PABS = (P(kPa)-70kPa)/40kPa*2^13 */
+	pressure_value =
+		(8192 * (pressure.val1 - 70) + ((8192 * (uint64_t)pressure.val2) / 1000000)) / 40;
+	rc |= inv_icp201xx_set_press_notification_config(&(data->icp_device),
+							 ~int_mask | ICP201XX_INT_MASK_PRESS_ABS,
+							 pressure_value, pressure_delta_value);
+	return rc;
+}
+
+static int icp201xx_pressure_change_interrupt(const struct device *dev,
+					      struct sensor_value pressure_delta)
+{
+	int16_t pressure_value, pressure_delta_value;
+	uint8_t int_mask = 0;
+	int rc = 0;
+	struct icp201xx_data *data = (struct icp201xx_data *)dev->data;
+
+	inv_icp201xx_get_press_notification_config(&(data->icp_device), &int_mask, &pressure_value,
+						   &pressure_delta_value);
+	/* PDELTA = (P(kPa)/80)* 2^14 */
+	pressure_delta_value =
+		(16384 * pressure_delta.val1 + (16384 * (uint64_t)pressure_delta.val2 / 1000000)) /
+		80;
+	rc |= inv_icp201xx_set_press_notification_config(&(data->icp_device),
+							 ~int_mask | ICP201XX_INT_MASK_PRESS_DELTA,
+							 pressure_value, pressure_delta_value);
+	return rc;
+}
+
+int icp201xx_trigger_init(const struct device *dev)
+{
+	struct icp201xx_data *drv_data = dev->data;
+	const struct icp201xx_config *cfg = dev->config;
+	int result = 0;
+
+	if (!cfg->gpio_int.port) {
+		LOG_ERR("trigger enabled but no interrupt gpio supplied");
+		return -ENODEV;
+	}
+
+	if (!gpio_is_ready_dt(&cfg->gpio_int)) {
+		LOG_ERR("gpio_int gpio not ready");
+		return -ENODEV;
+	}
+
+	drv_data->dev = dev;
+	gpio_pin_configure_dt(&cfg->gpio_int, GPIO_INPUT);
+	gpio_init_callback(&drv_data->gpio_cb, icp201xx_gpio_callback, BIT(cfg->gpio_int.pin));
+	result = gpio_add_callback(cfg->gpio_int.port, &drv_data->gpio_cb);
+
+	if (result < 0) {
+		LOG_ERR("Failed to set gpio callback");
+		return result;
+	}
+
+	k_mutex_init(&drv_data->mutex);
+
+#if defined(CONFIG_ICP201XX_TRIGGER_OWN_THREAD)
+	k_sem_init(&drv_data->gpio_sem, 0, K_SEM_MAX_LIMIT);
+
+	k_thread_create(&drv_data->thread, drv_data->thread_stack,
+			CONFIG_ICP201XX_THREAD_STACK_SIZE, icp201xx_thread, (struct device *)dev,
+			NULL, NULL, K_PRIO_COOP(CONFIG_ICP201XX_THREAD_PRIORITY), 0, K_NO_WAIT);
+	k_thread_name_set(&drv_data->thread, "icp201xx");
+#elif defined(CONFIG_ICP201XX_TRIGGER_GLOBAL_THREAD)
+	drv_data->work.handler = icp201xx_work_handler;
+#endif
+
+	return 0;
+}
+
+int icp201xx_trigger_set(const struct device *dev, const struct sensor_trigger *trig,
+			 sensor_trigger_handler_t handler)
+{
+	int rc = 0;
+	struct icp201xx_data *drv_data = dev->data;
+	const struct icp201xx_config *cfg = dev->config;
+
+	icp201xx_mutex_lock(dev);
+	gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_DISABLE);
+	if (handler == NULL) {
+		return -1;
+	}
+
+	if ((trig->type != SENSOR_TRIG_DATA_READY) && (trig->type != SENSOR_TRIG_DELTA) &&
+	    (trig->type != SENSOR_TRIG_THRESHOLD)) {
+		icp201xx_mutex_unlock(dev);
+		return -ENOTSUP;
+	}
+
+	if (trig->type == SENSOR_TRIG_DATA_READY) {
+		rc = icp201xx_fifo_interrupt(dev, 1);
+		drv_data->drdy_handler = handler;
+		drv_data->drdy_trigger = trig;
+	} else if (trig->type == SENSOR_TRIG_DELTA) {
+		rc = icp201xx_pressure_change_interrupt(dev, drv_data->pressure_change);
+		drv_data->delta_handler = handler;
+		drv_data->delta_trigger = trig;
+	} else if (trig->type == SENSOR_TRIG_THRESHOLD) {
+		rc = icp201xx_pressure_interrupt(dev, drv_data->pressure_threshold);
+		drv_data->threshold_handler = handler;
+		drv_data->threshold_trigger = trig;
+	}
+
+	gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_LEVEL_LOW);
+	icp201xx_mutex_unlock(dev);
+
+	return rc;
+}
diff --git a/drivers/sensor/tdk/mpu6050/Kconfig b/drivers/sensor/tdk/mpu6050/Kconfig
index de42afe611f..915655d95b4 100644
--- a/drivers/sensor/tdk/mpu6050/Kconfig
+++ b/drivers/sensor/tdk/mpu6050/Kconfig
@@ -53,20 +53,4 @@ config MPU6050_THREAD_STACK_SIZE
 	help
 	  Stack size of thread used by the driver to handle interrupts.
 
-config MPU6050_ACCEL_FS
-	int "Accelerometer full-scale range"
-	default 2
-	help
-	  Magnetometer full-scale range.
-	  An X value for the config represents a range of +/- X g. Valid
-	  values are 2, 4, 8 and 16.
-
-config MPU6050_GYRO_FS
-	int "Gyroscope full-scale range"
-	default 250
-	help
-	  Gyroscope full-scale range.
-	  An X value for the config represents a range of +/- X degrees/second.
-	  Valid values are 250, 500, 1000, 2000.
-
 endif # MPU6050
diff --git a/drivers/sensor/tdk/mpu6050/mpu6050.c b/drivers/sensor/tdk/mpu6050/mpu6050.c
index 13d848a2084..0401ca41227 100644
--- a/drivers/sensor/tdk/mpu6050/mpu6050.c
+++ b/drivers/sensor/tdk/mpu6050/mpu6050.c
@@ -186,7 +186,7 @@ int mpu6050_init(const struct device *dev)
 
 	/* set accelerometer full-scale range */
 	for (i = 0U; i < 4; i++) {
-		if (BIT(i+1) == CONFIG_MPU6050_ACCEL_FS) {
+		if (BIT(i+1) == cfg->accel_fs) {
 			break;
 		}
 	}
@@ -206,7 +206,7 @@ int mpu6050_init(const struct device *dev)
 
 	/* set gyroscope full-scale range */
 	for (i = 0U; i < 4; i++) {
-		if (BIT(i) * 250 == CONFIG_MPU6050_GYRO_FS) {
+		if (BIT(i) * 250 == cfg->gyro_fs) {
 			break;
 		}
 	}
@@ -224,6 +224,12 @@ int mpu6050_init(const struct device *dev)
 
 	drv_data->gyro_sensitivity_x10 = mpu6050_gyro_sensitivity_x10[i];
 
+	if (i2c_reg_write_byte_dt(&cfg->i2c, MPU6050_REG_SMPLRT_DIV,
+				  cfg->smplrt_div) < 0) {
+		LOG_ERR("Failed to write samplerate divider.");
+		return -EIO;
+	}
+
 #ifdef CONFIG_MPU6050_TRIGGER
 	if (cfg->int_gpio.port) {
 		if (mpu6050_init_interrupt(dev) < 0) {
@@ -241,6 +247,9 @@ int mpu6050_init(const struct device *dev)
 												\
 	static const struct mpu6050_config mpu6050_config_##inst = {				\
 		.i2c = I2C_DT_SPEC_INST_GET(inst),						\
+		.accel_fs = DT_INST_PROP(inst, accel_fs),					\
+		.gyro_fs = DT_INST_PROP(inst, gyro_fs),						\
+		.smplrt_div = DT_INST_PROP(inst, smplrt_div),					\
 		IF_ENABLED(CONFIG_MPU6050_TRIGGER,						\
 			   (.int_gpio = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, { 0 }),))	\
 	};											\
diff --git a/drivers/sensor/tdk/mpu6050/mpu6050.h b/drivers/sensor/tdk/mpu6050/mpu6050.h
index 9277873cd5f..3ea669d17d9 100644
--- a/drivers/sensor/tdk/mpu6050/mpu6050.h
+++ b/drivers/sensor/tdk/mpu6050/mpu6050.h
@@ -20,6 +20,8 @@
 #define MPU9250_CHIP_ID			0x71
 #define MPU6880_CHIP_ID			0x19
 
+#define MPU6050_REG_SMPLRT_DIV		0x19
+
 #define MPU6050_REG_GYRO_CFG		0x1B
 #define MPU6050_GYRO_FS_SHIFT		3
 
@@ -80,6 +82,9 @@ struct mpu6050_data {
 
 struct mpu6050_config {
 	struct i2c_dt_spec i2c;
+	uint8_t accel_fs;
+	uint16_t gyro_fs;
+	uint8_t smplrt_div;
 #ifdef CONFIG_MPU6050_TRIGGER
 	struct gpio_dt_spec int_gpio;
 #endif /* CONFIG_MPU6050_TRIGGER */
diff --git a/drivers/sensor/ti/CMakeLists.txt b/drivers/sensor/ti/CMakeLists.txt
index 8a497df2948..9ad90eddfe9 100644
--- a/drivers/sensor/ti/CMakeLists.txt
+++ b/drivers/sensor/ti/CMakeLists.txt
@@ -19,6 +19,6 @@ add_subdirectory_ifdef(CONFIG_TMP1075 tmp1075)
 add_subdirectory_ifdef(CONFIG_TMP108 tmp108)
 add_subdirectory_ifdef(CONFIG_TMP112 tmp112)
 add_subdirectory_ifdef(CONFIG_TMP114 tmp114)
-add_subdirectory_ifdef(CONFIG_TMP116 tmp116)
+add_subdirectory_ifdef(CONFIG_TMP11X tmp11x)
 add_subdirectory_ifdef(CONFIG_TMP435 tmp435)
 # zephyr-keep-sorted-stop
diff --git a/drivers/sensor/ti/Kconfig b/drivers/sensor/ti/Kconfig
index 7e9f0e95f29..6c28e870da4 100644
--- a/drivers/sensor/ti/Kconfig
+++ b/drivers/sensor/ti/Kconfig
@@ -19,6 +19,6 @@ source "drivers/sensor/ti/tmp1075/Kconfig"
 source "drivers/sensor/ti/tmp108/Kconfig"
 source "drivers/sensor/ti/tmp112/Kconfig"
 source "drivers/sensor/ti/tmp114/Kconfig"
-source "drivers/sensor/ti/tmp116/Kconfig"
+source "drivers/sensor/ti/tmp11x/Kconfig"
 source "drivers/sensor/ti/tmp435/Kconfig"
 # zephyr-keep-sorted-stop
diff --git a/drivers/sensor/ti/opt3001/CMakeLists.txt b/drivers/sensor/ti/opt3001/CMakeLists.txt
index dac045ee40c..9cd675cb009 100644
--- a/drivers/sensor/ti/opt3001/CMakeLists.txt
+++ b/drivers/sensor/ti/opt3001/CMakeLists.txt
@@ -3,3 +3,4 @@
 zephyr_library()
 
 zephyr_library_sources(opt3001.c)
+zephyr_library_sources_ifdef(CONFIG_OPT3001_TRIGGER opt3001_trigger.c)
diff --git a/drivers/sensor/ti/opt3001/Kconfig b/drivers/sensor/ti/opt3001/Kconfig
index 6151eb24b55..e5d6ce0f5ca 100644
--- a/drivers/sensor/ti/opt3001/Kconfig
+++ b/drivers/sensor/ti/opt3001/Kconfig
@@ -10,3 +10,12 @@ config OPT3001
 	select I2C
 	help
 	  Enable driver for OPT3001 light sensors.
+
+if OPT3001
+
+module = OPT3001
+thread_priority = 10
+thread_stack_size = 1024
+source "drivers/sensor/Kconfig.trigger_template"
+
+endif # OPT3001
diff --git a/drivers/sensor/ti/opt3001/opt3001.c b/drivers/sensor/ti/opt3001/opt3001.c
index 98ab3f253d1..ea6180c79f2 100644
--- a/drivers/sensor/ti/opt3001/opt3001.c
+++ b/drivers/sensor/ti/opt3001/opt3001.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2019 Actinius
+ * Copyright (c) 2025 Bang & Olufsen A/S
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,7 +17,7 @@
 
 LOG_MODULE_REGISTER(opt3001, CONFIG_SENSOR_LOG_LEVEL);
 
-static int opt3001_reg_read(const struct device *dev, uint8_t reg,
+int opt3001_reg_read(const struct device *dev, uint8_t reg,
 			    uint16_t *val)
 {
 	const struct opt3001_config *config = dev->config;
@@ -45,7 +46,7 @@ static int opt3001_reg_write(const struct device *dev, uint8_t reg,
 	return i2c_write_dt(&config->i2c, tx_buf, sizeof(tx_buf));
 }
 
-static int opt3001_reg_update(const struct device *dev, uint8_t reg,
+int opt3001_reg_update(const struct device *dev, uint8_t reg,
 			      uint16_t mask, uint16_t val)
 {
 	uint16_t old_val;
@@ -85,6 +86,7 @@ static int opt3001_channel_get(const struct device *dev,
 			       struct sensor_value *val)
 {
 	struct opt3001_data *drv_data = dev->data;
+	uint16_t sample = drv_data->sample;
 	int32_t uval;
 
 	if (chan != SENSOR_CHAN_LIGHT) {
@@ -99,8 +101,7 @@ static int opt3001_channel_get(const struct device *dev,
 	 * lux is the integer obtained using the following formula:
 	 * (2^(exponent value)) * 0.01 * mantissa value
 	 */
-	uval = (1 << (drv_data->sample >> OPT3001_SAMPLE_EXPONENT_SHIFT))
-		* (drv_data->sample & OPT3001_MANTISSA_MASK);
+	uval = (1 << (sample >> OPT3001_SAMPLE_EXPONENT_SHIFT)) * (sample & OPT3001_MANTISSA_MASK);
 	val->val1 = uval / 100;
 	val->val2 = (uval % 100) * 10000;
 
@@ -108,6 +109,9 @@ static int opt3001_channel_get(const struct device *dev,
 }
 
 static DEVICE_API(sensor, opt3001_driver_api) = {
+#ifdef CONFIG_OPT3001_TRIGGER
+	.trigger_set = opt3001_trigger_set,
+#endif
 	.sample_fetch = opt3001_sample_fetch,
 	.channel_get = opt3001_channel_get,
 };
@@ -156,6 +160,13 @@ int opt3001_init(const struct device *dev)
 		return -EINVAL;
 	}
 
+#ifdef CONFIG_OPT3001_TRIGGER
+	if (opt3001_init_interrupt(dev)) {
+		LOG_ERR("Failed to initialize interrupt");
+		return -EIO;
+	}
+#endif
+
 	return 0;
 }
 
@@ -164,6 +175,8 @@ int opt3001_init(const struct device *dev)
 												\
 	static const struct opt3001_config opt3001_config_##inst = {				\
 		.i2c = I2C_DT_SPEC_INST_GET(inst),						\
+		IF_ENABLED(CONFIG_OPT3001_TRIGGER,						\
+			(.gpio_int = GPIO_DT_SPEC_INST_GET_OR(inst, int_gpios, {0}),))		\
 	};											\
 												\
 	SENSOR_DEVICE_DT_INST_DEFINE(inst, opt3001_init, NULL,					\
diff --git a/drivers/sensor/ti/opt3001/opt3001.h b/drivers/sensor/ti/opt3001/opt3001.h
index f14b162ad6a..2ef9caba189 100644
--- a/drivers/sensor/ti/opt3001/opt3001.h
+++ b/drivers/sensor/ti/opt3001/opt3001.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2019 Actinius
+ * Copyright (c) 2025 Bang & Olufsen A/S
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,9 +10,13 @@
 
 #include <zephyr/sys/util.h>
 #include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/kernel.h>
 
 #define OPT3001_REG_RESULT 0x00
 #define OPT3001_REG_CONFIG 0x01
+#define OPT3001_REG_LOW_LIMIT 0x02
 #define OPT3001_REG_MANUFACTURER_ID 0x7E
 #define OPT3001_REG_DEVICE_ID 0x7F
 
@@ -21,15 +26,51 @@
 #define OPT3001_CONVERSION_MODE_MASK (BIT(10) | BIT(9))
 #define OPT3001_CONVERSION_MODE_CONTINUOUS (BIT(10) | BIT(9))
 
+#define OPT3001_LIMIT_EXPONENT_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12))
+#define OPT3001_LIMIT_EXPONENT_DEFAULT 0x0000
+
 #define OPT3001_SAMPLE_EXPONENT_SHIFT 12
 #define OPT3001_MANTISSA_MASK 0xfff
 
+#ifdef CONFIG_OPT3001_TRIGGER
+int opt3001_init_interrupt(const struct device *dev);
+
+int opt3001_trigger_set(const struct device *dev, const struct sensor_trigger *trig,
+			sensor_trigger_handler_t handler);
+
+int opt3001_reg_update(const struct device *dev, uint8_t reg, uint16_t mask, uint16_t val);
+
+int opt3001_reg_read(const struct device *dev, uint8_t reg, uint16_t *val);
+
+#endif
+
 struct opt3001_data {
 	uint16_t sample;
+
+#ifdef CONFIG_OPT3001_TRIGGER
+	const struct device *dev;
+	struct gpio_callback gpio_cb_int;
+
+	const struct sensor_trigger *trigger;
+	sensor_trigger_handler_t handler;
+	struct k_mutex handler_mutex;
+
+#if defined(CONFIG_OPT3001_TRIGGER_OWN_THREAD)
+	K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_OPT3001_THREAD_STACK_SIZE);
+	struct k_sem gpio_sem;
+	struct k_thread thread;
+#elif defined(CONFIG_OPT3001_TRIGGER_GLOBAL_THREAD)
+	struct k_work work_int;
+#endif
+
+#endif
 };
 
 struct opt3001_config {
 	struct i2c_dt_spec i2c;
+#ifdef CONFIG_OPT3001_TRIGGER
+	const struct gpio_dt_spec gpio_int;
+#endif
 };
 
 #endif /* _SENSOR_OPT3001_ */
diff --git a/drivers/sensor/ti/opt3001/opt3001_trigger.c b/drivers/sensor/ti/opt3001/opt3001_trigger.c
new file mode 100644
index 00000000000..056f7214b42
--- /dev/null
+++ b/drivers/sensor/ti/opt3001/opt3001_trigger.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2025 Bang & Olufsen A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ti_opt3001
+
+#include "opt3001.h"
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/util.h>
+
+LOG_MODULE_DECLARE(opt3001, CONFIG_SENSOR_LOG_LEVEL);
+
+static void opt3001_thread_cb(const struct device *dev)
+{
+	const struct opt3001_config *cfg = dev->config;
+	struct opt3001_data *dat = dev->data;
+	uint16_t reg_cfg;
+	int ret;
+
+	/* read result then clear interrupt by reading REG_CONFIG */
+	ret = opt3001_reg_read(dat->dev, OPT3001_REG_RESULT, &dat->sample);
+	if (ret) {
+		LOG_ERR("Failed to read result, ret: %d", ret);
+		return;
+	}
+
+	ret = opt3001_reg_read(dat->dev, OPT3001_REG_CONFIG, &reg_cfg);
+	if (ret) {
+		LOG_ERR("Failed to read config, ret: %d", ret);
+		return;
+	}
+
+	ret = k_mutex_lock(&dat->handler_mutex, K_FOREVER);
+	if (ret) {
+		LOG_ERR("Failed to lock trigger mutex, ret: %d", ret);
+		return;
+	}
+
+	if (dat->handler) {
+		dat->handler(dat->dev, dat->trigger);
+	}
+
+	/* recheck handler in case it was removed during the handler invocation */
+	if (dat->handler) {
+		/* enable interrupt again */
+		gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_EDGE_TO_ACTIVE);
+	}
+
+	ret = k_mutex_unlock(&dat->handler_mutex);
+	if (ret) {
+		LOG_ERR("Failed to unlock trigger mutex, ret: %d", ret);
+	}
+}
+
+static void opt3001_isr(const struct device *dev, struct gpio_callback *gpio_cb, uint32_t pins)
+{
+	struct opt3001_data *dat = CONTAINER_OF(gpio_cb, struct opt3001_data, gpio_cb_int);
+	const struct opt3001_config *cfg = dat->dev->config;
+
+	ARG_UNUSED(pins);
+
+	/* disable interrupt from gpio during handling */
+	gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_DISABLE);
+
+#if defined(CONFIG_OPT3001_TRIGGER_OWN_THREAD)
+	k_sem_give(&dat->gpio_sem);
+#elif defined(CONFIG_OPT3001_TRIGGER_GLOBAL_THREAD)
+	k_work_submit(&dat->work_int);
+#endif
+}
+
+#ifdef CONFIG_OPT3001_TRIGGER_OWN_THREAD
+static void opt3001_thread(void *p1, void *p2, void *p3)
+{
+	ARG_UNUSED(p2);
+	ARG_UNUSED(p3);
+
+	struct opt3001_data *dat = p1;
+
+	while (1) {
+		k_sem_take(&dat->gpio_sem, K_FOREVER);
+		opt3001_thread_cb(dat->dev);
+	}
+}
+#endif
+
+#ifdef CONFIG_OPT3001_TRIGGER_GLOBAL_THREAD
+static void opt3001_int_work(struct k_work *work)
+{
+	struct opt3001_data *dat = CONTAINER_OF(work, struct opt3001_data, work_int);
+
+	opt3001_thread_cb(dat->dev);
+}
+#endif
+
+int opt3001_init_interrupt(const struct device *dev)
+{
+	const struct opt3001_config *cfg = dev->config;
+	struct opt3001_data *dat = dev->data;
+	int ret = 0;
+
+	/* setup interrupt if provided */
+	if (!cfg->gpio_int.port) {
+		LOG_DBG("int-gpios not provided, continuing without support for trigger");
+		return 0;
+	}
+
+	dat->dev = dev;
+
+	if (!gpio_is_ready_dt(&cfg->gpio_int)) {
+		LOG_ERR("Interrupt gpio not ready");
+		return -ENODEV;
+	}
+
+	ret = k_mutex_init(&dat->handler_mutex);
+	if (ret) {
+		LOG_ERR("Failed to init trigger mutex, ret: %d", ret);
+		return ret;
+	}
+
+	ret = gpio_pin_configure_dt(&cfg->gpio_int, GPIO_INPUT);
+	if (ret) {
+		LOG_ERR("Failed to configure int-gpios, ret: %d", ret);
+		return ret;
+	}
+
+	ret = gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_DISABLE);
+	if (ret) {
+		LOG_ERR("Failed to enable interrupt on int-gpios, ret: %d", ret);
+		return ret;
+	}
+
+	gpio_init_callback(&dat->gpio_cb_int, opt3001_isr, BIT(cfg->gpio_int.pin));
+
+	ret = gpio_add_callback(cfg->gpio_int.port, &dat->gpio_cb_int);
+	if (ret) {
+		LOG_ERR("Failed to add callback to int-gpios, ret: %d", ret);
+		return ret;
+	}
+
+#if defined(CONFIG_OPT3001_TRIGGER_OWN_THREAD)
+	k_sem_init(&dat->gpio_sem, 0, K_SEM_MAX_LIMIT);
+	k_thread_create(&dat->thread, dat->thread_stack, CONFIG_OPT3001_THREAD_STACK_SIZE,
+			opt3001_thread, dat, NULL, NULL,
+			K_PRIO_COOP(CONFIG_OPT3001_THREAD_PRIORITY), 0, K_NO_WAIT);
+	k_thread_name_set(&dat->thread, "opt3001_trigger");
+
+#elif defined(CONFIG_OPT3001_TRIGGER_GLOBAL_THREAD)
+	k_work_init(&dat->work_int, opt3001_int_work);
+#endif
+
+	return 0;
+}
+
+int opt3001_trigger_set(const struct device *dev, const struct sensor_trigger *trig,
+			sensor_trigger_handler_t handler)
+{
+	const struct opt3001_config *cfg = dev->config;
+	struct opt3001_data *dat = dev->data;
+	uint16_t reg_cfg;
+	int ret;
+
+	/* only allow trigger on a device with int-gpios specified */
+	if (!cfg->gpio_int.port) {
+		return -ENOSYS;
+	}
+
+	if (trig->chan != SENSOR_CHAN_LIGHT) {
+		return -EINVAL;
+	}
+
+	if (trig->type != SENSOR_TRIG_DATA_READY) {
+		return -EINVAL;
+	}
+
+	ret = k_mutex_lock(&dat->handler_mutex, K_FOREVER);
+	if (ret) {
+		LOG_ERR("Failed to lock trigger mutex, ret: %d", ret);
+		return ret;
+	}
+
+	dat->trigger = trig;
+	dat->handler = handler;
+
+	ret = gpio_pin_interrupt_configure_dt(&cfg->gpio_int,
+					      handler ? GPIO_INT_EDGE_TO_ACTIVE : GPIO_INT_DISABLE);
+	if (ret) {
+		LOG_ERR("Failed to configure gpio interrupt, ret: %d", ret);
+		return ret;
+	}
+
+	/* enable/disable interrupt on every conversion */
+	ret = opt3001_reg_update(dev, OPT3001_REG_LOW_LIMIT, OPT3001_LIMIT_EXPONENT_MASK,
+				 handler ? OPT3001_LIMIT_EXPONENT_MASK
+					 : OPT3001_LIMIT_EXPONENT_DEFAULT);
+	if (ret) {
+		LOG_ERR("Failed to enable interrupt on conversions, ret: %d", ret);
+		return ret;
+	}
+
+	/* clear any asserted interrupt by reading REG_CONFIG */
+	ret = opt3001_reg_read(dat->dev, OPT3001_REG_CONFIG, &reg_cfg);
+	if (ret) {
+		LOG_ERR("Failed to read config, ret: %d", ret);
+		return ret;
+	}
+
+	ret = k_mutex_unlock(&dat->handler_mutex);
+	if (ret) {
+		LOG_ERR("Failed to unlock trigger mutex, ret: %d", ret);
+		return ret;
+	}
+
+	return 0;
+}
diff --git a/drivers/sensor/ti/tmag5170/tmag5170.c b/drivers/sensor/ti/tmag5170/tmag5170.c
index 48f3eaaaa63..258e3c5fcfb 100644
--- a/drivers/sensor/ti/tmag5170/tmag5170.c
+++ b/drivers/sensor/ti/tmag5170/tmag5170.c
@@ -266,7 +266,7 @@ static void tmag5170_convert_temp_reading_to_celsius(struct sensor_value *output
 	output->val2 = (result % 100000) * 10;
 }
 
-static void tmag5170_covert_angle_reading_to_degrees(struct sensor_value *output,
+static void tmag5170_convert_angle_reading_to_degrees(struct sensor_value *output,
 						     uint16_t chan_reading)
 {
 	/* 12 MSBs store the integer part of the result,
@@ -427,7 +427,7 @@ static int tmag5170_channel_get(const struct device *dev,
 							     drv_data->chip_revision);
 		break;
 	case SENSOR_CHAN_ROTATION:
-		tmag5170_covert_angle_reading_to_degrees(val, drv_data->angle);
+		tmag5170_convert_angle_reading_to_degrees(val, drv_data->angle);
 		break;
 	case SENSOR_CHAN_AMBIENT_TEMP:
 		tmag5170_convert_temp_reading_to_celsius(val, drv_data->temperature);
@@ -482,7 +482,7 @@ static int tmag5170_init_registers(const struct device *dev)
 				TMAG5170_OPERATING_MODE_SET(cfg->operating_mode) |
 				TMAG5170_CONV_AVG_SET(cfg->oversampling) |
 				TMAG5170_MAG_TEMPCO_SET(cfg->magnet_type) |
-				TMAG5170_T_CH_EN_SET(cfg->tempeature_measurement) |
+				TMAG5170_T_CH_EN_SET(cfg->temperature_measurement) |
 				TMAG5170_T_RATE_SET(cfg->disable_temperature_oversampling));
 	}
 
@@ -563,7 +563,7 @@ static int tmag5170_init(const struct device *dev)
 		.z_range = DT_INST_ENUM_IDX(_num, z_range),				   \
 		.operating_mode = DT_INST_PROP(_num, operating_mode),			   \
 		.oversampling = DT_INST_ENUM_IDX(_num, oversampling),			   \
-		.tempeature_measurement = DT_INST_PROP(_num, enable_temperature_channel),  \
+		.temperature_measurement = DT_INST_PROP(_num, enable_temperature_channel), \
 		.magnet_type = DT_INST_ENUM_IDX(_num, magnet_type),			   \
 		.angle_measurement = DT_INST_ENUM_IDX(_num, angle_measurement),		   \
 		.disable_temperature_oversampling = DT_INST_PROP(_num,			   \
diff --git a/drivers/sensor/ti/tmag5170/tmag5170.h b/drivers/sensor/ti/tmag5170/tmag5170.h
index 28f76d2e12b..c694d4f34ec 100644
--- a/drivers/sensor/ti/tmag5170/tmag5170.h
+++ b/drivers/sensor/ti/tmag5170/tmag5170.h
@@ -19,7 +19,7 @@ struct tmag5170_dev_config {
 	uint8_t y_range;
 	uint8_t z_range;
 	uint8_t oversampling;
-	bool tempeature_measurement;
+	bool temperature_measurement;
 	uint8_t magnet_type;
 	uint8_t angle_measurement;
 	bool disable_temperature_oversampling;
diff --git a/drivers/sensor/ti/tmp1075/tmp1075.c b/drivers/sensor/ti/tmp1075/tmp1075.c
index 83643b80df8..c2ebb3cf3cb 100644
--- a/drivers/sensor/ti/tmp1075/tmp1075.c
+++ b/drivers/sensor/ti/tmp1075/tmp1075.c
@@ -170,7 +170,7 @@ static int setup_interrupts(const struct device *dev)
 	int result;
 
 	if (!gpio_is_ready_dt(alert_gpio)) {
-		LOG_ERR("tmp1075: gpio controller %s not ready", alert_gpio->port->name);
+		LOG_ERR("gpio controller %s not ready", alert_gpio->port->name);
 		return -ENODEV;
 	}
 
diff --git a/drivers/sensor/ti/tmp108/CMakeLists.txt b/drivers/sensor/ti/tmp108/CMakeLists.txt
index f8cce2bad85..620f9ea9283 100644
--- a/drivers/sensor/ti/tmp108/CMakeLists.txt
+++ b/drivers/sensor/ti/tmp108/CMakeLists.txt
@@ -2,4 +2,5 @@
 
 zephyr_library()
 
-zephyr_library_sources(tmp108.c tmp108_trigger.c)
+zephyr_library_sources(tmp108.c)
+zephyr_library_sources_ifdef(CONFIG_TMP108_ALERT_INTERRUPTS tmp108_trigger.c)
diff --git a/drivers/sensor/ti/tmp108/tmp108.c b/drivers/sensor/ti/tmp108/tmp108.c
index 7c130d23eec..e503a30090e 100644
--- a/drivers/sensor/ti/tmp108/tmp108.c
+++ b/drivers/sensor/ti/tmp108/tmp108.c
@@ -100,45 +100,57 @@ static int tmp108_sample_fetch(const struct device *dev,
 			       enum sensor_channel chan)
 {
 	struct tmp108_data *drv_data = dev->data;
+	uint16_t config, converting_mask;
 	int result;
 
 	if (chan != SENSOR_CHAN_ALL && chan != SENSOR_CHAN_AMBIENT_TEMP) {
 		return -ENOTSUP;
 	}
 
-	/* If one shot mode is set, query chip for reading
-	 * should be finished 30 ms later
-	 */
-	if (drv_data->one_shot_mode == true) {
+	if (!drv_data->one_shot_mode) {
+		/* Read the latest temperature result */
+		return ti_tmp108_read_temp(dev);
+	}
 
-		result = tmp108_write_config(dev,
-					     TI_TMP108_MODE_MASK(dev),
-					     TI_TMP108_MODE_ONE_SHOT(dev));
+	/* Trigger the conversion */
+	result = tmp108_write_config(dev,
+					TI_TMP108_MODE_MASK(dev),
+					TI_TMP108_MODE_ONE_SHOT(dev));
+	if (result < 0) {
+		return result;
+	}
 
-		if (result < 0) {
-			return result;
-		}
+	/* Typical conversion time:
+	 *   TMP108: 27ms
+	 *   AS6212: 36ms
+	 * Maximum conversion time:
+	 *   TMP108: 35ms
+	 *   AS6212: 51ms
+	 */
+	const uint32_t conv_time_min = 25;
+	const uint32_t conv_time_max = 100;
+	const uint32_t poll_period = 5;
 
-		/* Schedule read to start in 30 ms if mode change was successful
-		 * the typical wakeup time given in the data sheet is 27
-		 */
-		result = k_work_schedule(&drv_data->scheduled_work,
-					 K_MSEC(TMP108_WAKEUP_TIME_IN_MS(dev)));
+	k_sleep(K_MSEC(conv_time_min));
+	converting_mask = TI_TMP108_CONF_M1(dev) | TI_TMP108_CONF_M0(dev);
 
+	for (int i = conv_time_min; i < conv_time_max; i += poll_period) {
+		/* Read the config register */
+		result = tmp108_reg_read(dev, TI_TMP108_REG_CONF, &config);
 		if (result < 0) {
 			return result;
 		}
-
-		return 0;
-	}
-
-	result =  ti_tmp108_read_temp(dev);
-
-	if (result < 0) {
-		return result;
+		if ((config & converting_mask) == 0) {
+			/* Conversion has finished */
+			LOG_DBG("Conversion complete after %d ms", i);
+			return ti_tmp108_read_temp(dev);
+		}
+		/* Wait before reading again */
+		k_sleep(K_MSEC(poll_period));
 	}
 
-	return 0;
+	/* Conversion timed out */
+	return -EAGAIN;
 }
 
 static int tmp108_channel_get(const struct device *dev,
@@ -153,10 +165,7 @@ static int tmp108_channel_get(const struct device *dev,
 	}
 
 	uval = ((int32_t)drv_data->sample * TMP108_TEMP_MULTIPLIER(dev)) / TMP108_TEMP_DIVISOR(dev);
-	val->val1 = uval / 1000000;
-	val->val2 = uval % 1000000;
-
-	return 0;
+	return sensor_value_from_micro(val, uval);
 }
 
 static int tmp108_attr_get(const struct device *dev,
@@ -192,16 +201,17 @@ static int tmp108_attr_set(const struct device *dev,
 			   const struct sensor_value *val)
 {
 	struct tmp108_data *drv_data = dev->data;
-	uint16_t mode = 0;
-	uint16_t reg_value = 0;
+	__maybe_unused uint16_t reg_value;
+	__maybe_unused int32_t uval;
+	uint16_t mode;
 	int result = 0;
-	int32_t uval;
 
 	if (chan != SENSOR_CHAN_AMBIENT_TEMP && chan != SENSOR_CHAN_ALL) {
 		return -ENOTSUP;
 	}
 
 	switch ((int) attr) {
+#ifdef CONFIG_TMP108_ALERT_INTERRUPTS
 	case SENSOR_ATTR_HYSTERESIS:
 		if (TI_TMP108_HYSTER_0_C(dev) == TI_TMP108_CONF_NA) {
 			LOG_WRN("AS621x Series lacks Hysterisis setttings");
@@ -236,7 +246,7 @@ static int tmp108_attr_set(const struct device *dev,
 		break;
 
 	case SENSOR_ATTR_LOWER_THRESH:
-		uval = val->val1 * 1000000 + val->val2;
+		uval = sensor_value_to_micro(val);
 		reg_value = (uval * TMP108_TEMP_DIVISOR(dev)) / TMP108_TEMP_MULTIPLIER(dev);
 		result = tmp108_reg_write(dev,
 					  TI_TMP108_REG_LOW_LIMIT,
@@ -244,13 +254,25 @@ static int tmp108_attr_set(const struct device *dev,
 		break;
 
 	case SENSOR_ATTR_UPPER_THRESH:
-		uval = val->val1 * 1000000 + val->val2;
+		uval = sensor_value_to_micro(val);
 		reg_value = (uval * TMP108_TEMP_DIVISOR(dev)) / TMP108_TEMP_MULTIPLIER(dev);
 		result = tmp108_reg_write(dev,
 					  TI_TMP108_REG_HIGH_LIMIT,
 					  reg_value);
 		break;
 
+	case SENSOR_ATTR_TMP108_ALERT_POLARITY:
+		if (val->val1 == 1) {
+			mode = TI_TMP108_CONF_POL_HIGH(dev);
+		} else {
+			mode = TI_TMP108_CONF_POL_LOW(dev);
+		}
+		result = tmp108_write_config(dev,
+					     TI_TMP108_CONF_POL_MASK(dev),
+					     mode);
+		break;
+#endif /* CONFIG_TMP108_ALERT_INTERRUPTS */
+
 	case SENSOR_ATTR_SAMPLING_FREQUENCY:
 		if (val->val1 < 1) {
 			mode = TI_TMP108_FREQ_4_SECS(dev);
@@ -287,17 +309,6 @@ static int tmp108_attr_set(const struct device *dev,
 		drv_data->one_shot_mode = true;
 		break;
 
-	case SENSOR_ATTR_TMP108_ALERT_POLARITY:
-		if (val->val1 == 1) {
-			mode = TI_TMP108_CONF_POL_HIGH(dev);
-		} else {
-			mode = TI_TMP108_CONF_POL_LOW(dev);
-		}
-		result = tmp108_write_config(dev,
-					     TI_TMP108_CONF_POL_MASK(dev),
-					     mode);
-		break;
-
 	default:
 		return -ENOTSUP;
 	}
@@ -314,7 +325,9 @@ static DEVICE_API(sensor, tmp108_driver_api) = {
 	.attr_get = tmp108_attr_get,
 	.sample_fetch = tmp108_sample_fetch,
 	.channel_get = tmp108_channel_get,
+#ifdef CONFIG_TMP108_ALERT_INTERRUPTS
 	.trigger_set = tmp_108_trigger_set,
+#endif
 };
 
 #ifdef CONFIG_TMP108_ALERT_INTERRUPTS
@@ -362,7 +375,6 @@ static int setup_interrupts(const struct device *dev)
 static int tmp108_init(const struct device *dev)
 {
 	const struct tmp108_config *cfg = dev->config;
-	struct tmp108_data *drv_data = dev->data;
 	int result = 0;
 
 	if (!device_is_ready(cfg->i2c_spec.bus)) {
@@ -370,12 +382,12 @@ static int tmp108_init(const struct device *dev)
 		return -ENODEV;
 	}
 
-	drv_data->scheduled_work.work.handler = tmp108_trigger_handle_one_shot;
+#ifdef CONFIG_TMP108_ALERT_INTERRUPTS
+	struct tmp108_data *drv_data = dev->data;
 
 	/* save this driver instance for passing to other functions */
 	drv_data->tmp108_dev = dev;
 
-#ifdef CONFIG_TMP108_ALERT_INTERRUPTS
 	result = setup_interrupts(dev);
 
 	if (result < 0) {
@@ -389,22 +401,16 @@ static int tmp108_init(const struct device *dev)
 	return result;
 }
 
-#define TMP108_DEFINE(inst, t)						   \
-	static struct tmp108_data tmp108_prv_data_##inst##t;		   \
-	static const struct tmp108_config tmp108_config_##inst##t = {	   \
-		.i2c_spec = I2C_DT_SPEC_INST_GET(inst),			   \
-		.alert_gpio = GPIO_DT_SPEC_INST_GET_OR(inst,		   \
-						       alert_gpios, { 0 }),\
-		.reg_def = t##_CONF					   \
-	};								   \
-	SENSOR_DEVICE_DT_INST_DEFINE(inst,				   \
-			      &tmp108_init,				   \
-			      NULL,					   \
-			      &tmp108_prv_data_##inst##t,		   \
-			      &tmp108_config_##inst##t,			   \
-			      POST_KERNEL,				   \
-			      CONFIG_SENSOR_INIT_PRIORITY,		   \
-			      &tmp108_driver_api);
+#define TMP108_DEFINE(inst, t)                                                                     \
+	static struct tmp108_data tmp108_prv_data_##inst##t;                                       \
+	static const struct tmp108_config tmp108_config_##inst##t = {                              \
+		.i2c_spec = I2C_DT_SPEC_INST_GET(inst),                                            \
+		IF_ENABLED(CONFIG_TMP108_ALERT_INTERRUPTS,                                         \
+			   (.alert_gpio = GPIO_DT_SPEC_INST_GET(inst, alert_gpios),))              \
+		.reg_def = t##_CONF};                                                              \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, &tmp108_init, NULL, &tmp108_prv_data_##inst##t,         \
+				     &tmp108_config_##inst##t, POST_KERNEL,                        \
+				     CONFIG_SENSOR_INIT_PRIORITY, &tmp108_driver_api);
 
 #define TMP108_INIT(n) TMP108_DEFINE(n, TI_TMP108)
 #undef DT_DRV_COMPAT
diff --git a/drivers/sensor/ti/tmp108/tmp108.h b/drivers/sensor/ti/tmp108/tmp108.h
index 44dc2d11936..14d8f92be2c 100644
--- a/drivers/sensor/ti/tmp108/tmp108.h
+++ b/drivers/sensor/ti/tmp108/tmp108.h
@@ -20,36 +20,36 @@
 #define TI_TMP108_REG_LOW_LIMIT		0x02   /** Low alert set register */
 #define TI_TMP108_REG_HIGH_LIMIT	0x03   /** High alert set register */
 
-#define AMS_AS6212_CONF	{.CONF_HYS1 = TI_TMP108_CONF_NA,\
-			 .CONF_HYS0 = TI_TMP108_CONF_NA,\
-			 .CONF_CR0  = 0x0040,	\
-			 .CONF_CR1  = 0x0080,	\
-			 .CONF_M1   = 0x0000,	\
-			 .CONF_TM   = 0x0200,	\
-			 .CONF_POL  = 0x0400,	\
-			 .CONF_M0   = 0x8000,	\
-			 .CONF_RST  = 0x0080,	\
-			 .TEMP_MULT = 15625,	\
-			 .TEMP_DIV  = 2,        \
-			 .WAKEUP_TIME_IN_MS = 120 }
-
-#define TI_TMP108_CONF	{.CONF_HYS0  = 0x0010,	\
-			 .CONF_HYS1  = 0x0020,	\
-			 .CONF_POL   = 0x0080,	\
-			 .CONF_M0    = 0x0100,	\
-			 .CONF_M1    = 0x0200,	\
-			 .CONF_TM    = 0x0400,	\
-			 .CONF_CR0   = 0x2000,	\
-			 .CONF_CR1   = 0x4000,	\
-			 .CONF_RST   = 0x0022,	\
-			 .TEMP_MULT  = 15625,	\
-			 .TEMP_DIV   = 4,       \
-			 .WAKEUP_TIME_IN_MS = 30 }
+#define AMS_AS6212_CONF                                                                            \
+	{.CONF_CR0 = 0x0040,                                                                       \
+	 .CONF_CR1 = 0x0080,                                                                       \
+	 .CONF_SLEEP = 0x0100,                                                                     \
+	 .CONF_M1 = 0x0000,                                                                        \
+	 .CONF_TM = 0x0200,                                                                        \
+	 .CONF_M0 = 0x8000,                                                                        \
+	 .CONF_RST = 0x0080,                                                                       \
+	 .TEMP_MULT = 15625,                                                                       \
+	 .TEMP_DIV = 2,                                                                            \
+	 IF_ENABLED(CONFIG_TMP108_ALERT_INTERRUPTS, (.CONF_POL = 0x0400))}
+
+#define TI_TMP108_CONF                                                                             \
+	{.CONF_M0 = 0x0100,                                                                        \
+	 .CONF_M1 = 0x0200,                                                                        \
+	 .CONF_TM = 0x0400,                                                                        \
+	 .CONF_CR0 = 0x2000,                                                                       \
+	 .CONF_CR1 = 0x4000,                                                                       \
+	 .CONF_RST = 0x0022,                                                                       \
+	 .TEMP_MULT = 15625,                                                                       \
+	 .TEMP_DIV = 4,                                                                            \
+	 IF_ENABLED(CONFIG_TMP108_ALERT_INTERRUPTS,                                                \
+		    (.CONF_HYS0 = 0x0010, .CONF_HYS1 = 0x0020, .CONF_POL = 0x0080))}
 
 #define TI_TMP108_MODE_SHUTDOWN(x) 0
-#define TI_TMP108_MODE_ONE_SHOT(x) TI_TMP108_CONF_M0(x)
+#define TI_TMP108_MODE_ONE_SHOT(x) (TI_TMP108_CONF_M0(x) | TI_TMP108_CONF_SLEEP(x))
 #define TI_TMP108_MODE_CONTINUOUS(x) TI_TMP108_CONF_M1(x)
-#define TI_TMP108_MODE_MASK(x)	~(TI_TMP108_CONF_M0(x) | TI_TMP108_CONF_M1(x))
+#define TI_TMP108_MODE_MASK(x)	~(TI_TMP108_CONF_M0(x) | \
+				  TI_TMP108_CONF_M1(x) | \
+				  TI_TMP108_CONF_SLEEP(x))
 
 #define TI_TMP108_FREQ_4_SECS(x) 0
 #define TI_TMP108_FREQ_1_HZ(x) TI_TMP108_GET_CONF(x, CONF_CR0)
@@ -77,53 +77,54 @@
 
 #define TI_TMP108_CONF_M1(x) TI_TMP108_GET_CONF(x, CONF_M1)
 #define TI_TMP108_CONF_M0(x) TI_TMP108_GET_CONF(x, CONF_M0)
+#define TI_TMP108_CONF_SLEEP(x) TI_TMP108_GET_CONF(x, CONF_SLEEP)
 
 #define TMP108_TEMP_MULTIPLIER(x)	TI_TMP108_GET_CONF(x, TEMP_MULT)
 #define TMP108_TEMP_DIVISOR(x)	TI_TMP108_GET_CONF(x, TEMP_DIV)
-#define TMP108_WAKEUP_TIME_IN_MS(x)	TI_TMP108_GET_CONF(x, WAKEUP_TIME_IN_MS)
 #define TMP108_CONF_RST(x)	TI_TMP108_GET_CONF(x, CONF_RST)
 
 #define TI_TMP108_CONF_NA 0x0000
 
 struct tmp_108_reg_def {
-	uint16_t CONF_M0;	/** Mode 1 configuration bit */
-	uint16_t CONF_M1;	/** Mode 2 configuration bit */
-	uint16_t CONF_CR0;	/** Conversion rate 1 configuration bit */
-	uint16_t CONF_CR1;	/** Conversion rate 2 configuration bit */
-	uint16_t CONF_POL;	/** Alert pin Polarity configuration bit */
-	uint16_t CONF_TM;	/** Thermostat mode setting bit */
-	uint16_t CONF_HYS1;	/** Temperature hysteresis config 1 bit  */
-	uint16_t CONF_HYS0;	/** Temperature hysteresis config 2 bit */
-	int32_t TEMP_MULT;	/** Temperature multiplier */
-	int32_t TEMP_DIV;	/** Temperature divisor */
-	uint16_t WAKEUP_TIME_IN_MS; /** Wake up and conversion time from one shot */
-	uint16_t CONF_RST;	/** default reset values on init */
+	uint16_t CONF_M0;    /** Mode 1 configuration bit */
+	uint16_t CONF_M1;    /** Mode 2 configuration bit */
+	uint16_t CONF_SLEEP; /** Sleep mode configuration bit */
+	uint16_t CONF_CR0;   /** Conversion rate 1 configuration bit */
+	uint16_t CONF_CR1;   /** Conversion rate 2 configuration bit */
+	uint16_t CONF_TM;    /** Thermostat mode setting bit */
+	int32_t TEMP_MULT;   /** Temperature multiplier */
+	int32_t TEMP_DIV;    /** Temperature divisor */
+	uint16_t CONF_RST;   /** default reset values on init */
+#ifdef CONFIG_TMP108_ALERT_INTERRUPTS
+	uint16_t CONF_POL;  /** Alert pin Polarity configuration bit */
+	uint16_t CONF_HYS1; /** Temperature hysteresis config 1 bit  */
+	uint16_t CONF_HYS0; /** Temperature hysteresis config 2 bit */
+#endif
 };
 
 #define TI_TMP108_GET_CONF(x, cfg) ((struct tmp108_config *)(x->config))->reg_def.cfg
 
 struct tmp108_config {
 	const struct i2c_dt_spec i2c_spec;
-	const struct gpio_dt_spec alert_gpio;
 	struct tmp_108_reg_def reg_def;
+#ifdef CONFIG_TMP108_ALERT_INTERRUPTS
+	const struct gpio_dt_spec alert_gpio;
+#endif /* CONFIG_TMP108_ALERT_INTERRUPTS */
 };
 
 struct tmp108_data {
-	const struct device *tmp108_dev;
-
 	int16_t sample;
 
 	bool one_shot_mode;
 
-	struct k_work_delayable scheduled_work;
+#ifdef CONFIG_TMP108_ALERT_INTERRUPTS
+	const struct device *tmp108_dev;
 
 	const struct sensor_trigger *temp_alert_trigger;
 	sensor_trigger_handler_t temp_alert_handler;
 
-	sensor_trigger_handler_t data_ready_handler;
-	const struct sensor_trigger *data_ready_trigger;
-
 	struct gpio_callback temp_alert_gpio_cb;
+#endif /* CONFIG_TMP108_ALERT_INTERRUPTS */
 };
 
 int tmp_108_trigger_set(const struct device *dev,
diff --git a/drivers/sensor/ti/tmp108/tmp108_trigger.c b/drivers/sensor/ti/tmp108/tmp108_trigger.c
index feb587bec46..9ef840f9d92 100644
--- a/drivers/sensor/ti/tmp108/tmp108_trigger.c
+++ b/drivers/sensor/ti/tmp108/tmp108_trigger.c
@@ -10,46 +10,8 @@
 
 #include "tmp108.h"
 
-#define TMP108_ONE_SHOT_RETRY_TIME_IN_MS 10
-
 LOG_MODULE_DECLARE(TMP108, CONFIG_SENSOR_LOG_LEVEL);
 
-void tmp108_trigger_handle_one_shot(struct k_work *work)
-{
-	struct k_work_delayable *delayable_work = k_work_delayable_from_work(work);
-	struct tmp108_data *drv_data = CONTAINER_OF(delayable_work,
-						    struct tmp108_data,
-						    scheduled_work);
-
-	uint16_t config = 0;
-	bool shutdown_mode = false;
-
-	tmp108_reg_read(drv_data->tmp108_dev, TI_TMP108_REG_CONF, &config);
-
-	/* check shutdown mode which indicates a one shot read was successful */
-	shutdown_mode = (config & (TI_TMP108_CONF_M1(drv_data->tmp108_dev) |
-				   TI_TMP108_CONF_M0(drv_data->tmp108_dev))) == 0;
-
-	if (shutdown_mode == true) {
-		ti_tmp108_read_temp(drv_data->tmp108_dev);
-	} else {
-		LOG_ERR("Temperature one shot mode read failed, retrying");
-		/* Wait for typical wake up time, retry if the read fails
-		 * assuming the chip should wake up and take a reading after the typical
-		 * wake up time and call of this thread plus 10 ms time has passed
-		 */
-		k_work_reschedule(&drv_data->scheduled_work,
-				  K_MSEC(TMP108_ONE_SHOT_RETRY_TIME_IN_MS));
-		return;
-	}
-
-	/* Successful read, call set callbacks */
-	if (drv_data->data_ready_handler) {
-		drv_data->data_ready_handler(drv_data->tmp108_dev,
-					     drv_data->data_ready_trigger);
-	}
-}
-
 void tmp108_trigger_handle_alert(const struct device *gpio,
 				 struct gpio_callback *cb,
 				 gpio_port_pins_t pins)
@@ -72,12 +34,6 @@ int tmp_108_trigger_set(const struct device *dev,
 {
 	struct tmp108_data *drv_data = dev->data;
 
-	if (trig->type == SENSOR_TRIG_DATA_READY) {
-		drv_data->data_ready_handler = handler;
-		drv_data->data_ready_trigger = trig;
-		return 0;
-	}
-
 	if (trig->type == SENSOR_TRIG_THRESHOLD) {
 		drv_data->temp_alert_handler = handler;
 		drv_data->temp_alert_trigger = trig;
diff --git a/drivers/sensor/ti/tmp112/tmp112.c b/drivers/sensor/ti/tmp112/tmp112.c
index fa73b22ca3d..0de33b4cdde 100644
--- a/drivers/sensor/ti/tmp112/tmp112.c
+++ b/drivers/sensor/ti/tmp112/tmp112.c
@@ -18,8 +18,7 @@
 
 LOG_MODULE_REGISTER(TMP112, CONFIG_SENSOR_LOG_LEVEL);
 
-static int tmp112_reg_read(const struct tmp112_config *cfg,
-			   uint8_t reg, uint16_t *val)
+static int tmp112_reg_read(const struct tmp112_config *cfg, uint8_t reg, uint16_t *val)
 {
 	if (i2c_burst_read_dt(&cfg->bus, reg, (uint8_t *)val, sizeof(*val)) < 0) {
 		return -EIO;
@@ -30,8 +29,7 @@ static int tmp112_reg_read(const struct tmp112_config *cfg,
 	return 0;
 }
 
-static int tmp112_reg_write(const struct tmp112_config *cfg,
-			    uint8_t reg, uint16_t val)
+static int tmp112_reg_write(const struct tmp112_config *cfg, uint8_t reg, uint16_t val)
 {
 	uint8_t buf[3];
 
@@ -41,14 +39,12 @@ static int tmp112_reg_write(const struct tmp112_config *cfg,
 	return i2c_write_dt(&cfg->bus, buf, sizeof(buf));
 }
 
-static uint16_t set_config_flags(struct tmp112_data *data, uint16_t mask,
-				 uint16_t value)
+static uint16_t set_config_flags(struct tmp112_data *data, uint16_t mask, uint16_t value)
 {
 	return (data->config_reg & ~mask) | (value & mask);
 }
 
-static int tmp112_update_config(const struct device *dev, uint16_t mask,
-				uint16_t val)
+static int tmp112_update_config(const struct device *dev, uint16_t mask, uint16_t val)
 {
 	int rc;
 	struct tmp112_data *data = dev->data;
@@ -62,10 +58,31 @@ static int tmp112_update_config(const struct device *dev, uint16_t mask,
 	return rc;
 }
 
-static int tmp112_attr_set(const struct device *dev,
-			   enum sensor_channel chan,
-			   enum sensor_attribute attr,
-			   const struct sensor_value *val)
+static int tmp112_set_threshold(const struct device *dev, uint8_t reg, int64_t micro_c)
+{
+	struct tmp112_data *drv_data = dev->data;
+	int64_t v;
+	uint16_t reg_value;
+
+	v = DIV_ROUND_CLOSEST(micro_c, TMP112_TEMP_SCALE);
+
+	if (drv_data->config_reg & TMP112_CONFIG_EM) {
+		if (!IN_RANGE(v, TMP112_TEMP_MIN_EM, TMP112_TEMP_MAX_EM)) {
+			return -EINVAL;
+		}
+		reg_value = (uint16_t)v << TMP112_DATA_EXTENDED_SHIFT;
+	} else {
+		if (!IN_RANGE(v, TMP112_TEMP_MIN, TMP112_TEMP_MAX)) {
+			return -EINVAL;
+		}
+		reg_value = (uint16_t)v << TMP112_DATA_NORMAL_SHIFT;
+	}
+
+	return tmp112_reg_write(dev->config, reg, reg_value);
+}
+
+static int tmp112_attr_set(const struct device *dev, enum sensor_channel chan,
+			   enum sensor_attribute attr, const struct sensor_value *val)
 {
 	uint16_t value;
 	uint16_t cr;
@@ -93,8 +110,9 @@ static int tmp112_attr_set(const struct device *dev,
 		}
 		break;
 #endif
-	case SENSOR_ATTR_SAMPLING_FREQUENCY:
+
 #if CONFIG_TMP112_SAMPLING_FREQUENCY_RUNTIME
+	case SENSOR_ATTR_SAMPLING_FREQUENCY:
 		/* conversion rate in mHz */
 		cr = val->val1 * 1000 + val->val2 / 1000;
 
@@ -129,6 +147,12 @@ static int tmp112_attr_set(const struct device *dev,
 		break;
 #endif
 
+	case SENSOR_ATTR_LOWER_THRESH:
+		return tmp112_set_threshold(dev, TMP112_REG_TLOW, sensor_value_to_micro(val));
+
+	case SENSOR_ATTR_UPPER_THRESH:
+		return tmp112_set_threshold(dev, TMP112_REG_THIGH, sensor_value_to_micro(val));
+
 	default:
 		return -ENOTSUP;
 	}
@@ -136,8 +160,7 @@ static int tmp112_attr_set(const struct device *dev,
 	return 0;
 }
 
-static int tmp112_sample_fetch(const struct device *dev,
-			       enum sensor_channel chan)
+static int tmp112_sample_fetch(const struct device *dev, enum sensor_channel chan)
 {
 	struct tmp112_data *drv_data = dev->data;
 	const struct tmp112_config *cfg = dev->config;
@@ -150,32 +173,24 @@ static int tmp112_sample_fetch(const struct device *dev,
 	}
 
 	if (val & TMP112_DATA_EXTENDED) {
-		drv_data->sample = arithmetic_shift_right((int16_t)val,
-							  TMP112_DATA_EXTENDED_SHIFT);
+		drv_data->sample = arithmetic_shift_right((int16_t)val, TMP112_DATA_EXTENDED_SHIFT);
 	} else {
-		drv_data->sample = arithmetic_shift_right((int16_t)val,
-							  TMP112_DATA_NORMAL_SHIFT);
+		drv_data->sample = arithmetic_shift_right((int16_t)val, TMP112_DATA_NORMAL_SHIFT);
 	}
 
 	return 0;
 }
 
-static int tmp112_channel_get(const struct device *dev,
-			      enum sensor_channel chan,
+static int tmp112_channel_get(const struct device *dev, enum sensor_channel chan,
 			      struct sensor_value *val)
 {
 	struct tmp112_data *drv_data = dev->data;
-	int32_t uval;
 
 	if (chan != SENSOR_CHAN_AMBIENT_TEMP) {
 		return -ENOTSUP;
 	}
 
-	uval = (int32_t)drv_data->sample * TMP112_TEMP_SCALE;
-	val->val1 = uval / 1000000;
-	val->val2 = uval % 1000000;
-
-	return 0;
+	return sensor_value_from_micro(val, (int32_t)drv_data->sample * TMP112_TEMP_SCALE);
 }
 
 static DEVICE_API(sensor, tmp112_driver_api) = {
@@ -188,29 +203,49 @@ int tmp112_init(const struct device *dev)
 {
 	const struct tmp112_config *cfg = dev->config;
 	struct tmp112_data *data = dev->data;
+	int ret;
 
 	if (!device_is_ready(cfg->bus.bus)) {
 		LOG_ERR("I2C dev %s not ready", cfg->bus.bus->name);
 		return -EINVAL;
 	}
 
-	data->config_reg = TMP112_CONV_RATE(cfg->cr) | TMP112_CONV_RES_MASK
-			   | (cfg->extended_mode ? TMP112_CONFIG_EM : 0);
+	data->config_reg = TMP112_CONV_RATE(cfg->cr) | TMP112_CONV_RES_MASK |
+			   (cfg->extended_mode ? TMP112_CONFIG_EM : 0);
 
-	return tmp112_update_config(dev, 0, 0);
-}
+	ret = tmp112_update_config(dev, 0, 0);
+	if (ret) {
+		LOG_ERR("Failed to set configuration (%d)", ret);
+		return ret;
+	}
 
+	ret = tmp112_set_threshold(dev, TMP112_REG_TLOW, cfg->t_low_micro_c);
+	if (ret) {
+		LOG_ERR("Failed to set tLow threshold (%d)", ret);
+		return ret;
+	}
+
+	ret = tmp112_set_threshold(dev, TMP112_REG_THIGH, cfg->t_high_micro_c);
+	if (ret) {
+		LOG_ERR("Failed to set tHigh threshold (%d)", ret);
+		return ret;
+	}
+
+	return 0;
+}
 
-#define TMP112_INST(inst)						    \
-	static struct tmp112_data tmp112_data_##inst;			    \
-	static const struct tmp112_config tmp112_config_##inst = {	    \
-		.bus = I2C_DT_SPEC_INST_GET(inst),			    \
-		.cr = DT_INST_ENUM_IDX(inst, conversion_rate),		    \
-		.extended_mode = DT_INST_PROP(inst, extended_mode),	    \
-	};								    \
-									    \
-	SENSOR_DEVICE_DT_INST_DEFINE(inst, tmp112_init, NULL, &tmp112_data_##inst, \
-			      &tmp112_config_##inst, POST_KERNEL,	    \
-			      CONFIG_SENSOR_INIT_PRIORITY, &tmp112_driver_api);
+#define TMP112_INST(inst)                                                                          \
+	static struct tmp112_data tmp112_data_##inst;                                              \
+	static const struct tmp112_config tmp112_config_##inst = {                                 \
+		.bus = I2C_DT_SPEC_INST_GET(inst),                                                 \
+		.cr = DT_INST_ENUM_IDX(inst, conversion_rate),                                     \
+		.t_low_micro_c = DT_INST_PROP(inst, t_low_micro_c),                                \
+		.t_high_micro_c = DT_INST_PROP(inst, t_high_micro_c),                              \
+		.extended_mode = DT_INST_PROP(inst, extended_mode),                                \
+	};                                                                                         \
+                                                                                                   \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, tmp112_init, NULL, &tmp112_data_##inst,                 \
+				     &tmp112_config_##inst, POST_KERNEL,                           \
+				     CONFIG_SENSOR_INIT_PRIORITY, &tmp112_driver_api);
 
 DT_INST_FOREACH_STATUS_OKAY(TMP112_INST)
diff --git a/drivers/sensor/ti/tmp112/tmp112.h b/drivers/sensor/ti/tmp112/tmp112.h
index 6f2b3f7b32b..6ea1258115b 100644
--- a/drivers/sensor/ti/tmp112/tmp112.h
+++ b/drivers/sensor/ti/tmp112/tmp112.h
@@ -41,6 +41,16 @@
 /* scale in micro degrees Celsius */
 #define TMP112_TEMP_SCALE       62500
 
+/* RAW min/max temperature values - LSB=TMP112_TEMP_SCALE */
+/* 128C */
+#define TMP112_TEMP_MAX    2047
+/* -55C */
+#define TMP112_TEMP_MIN    -880
+/* 150C */
+#define TMP112_TEMP_MAX_EM 2400
+/* -55C */
+#define TMP112_TEMP_MIN_EM TMP112_TEMP_MIN
+
 struct tmp112_data {
 	int16_t sample;
 	uint16_t config_reg;
@@ -49,6 +59,8 @@ struct tmp112_data {
 struct tmp112_config {
 	const struct i2c_dt_spec bus;
 	uint8_t cr;
+	int32_t t_low_micro_c;
+	int32_t t_high_micro_c;
 	bool extended_mode : 1;
 };
 
diff --git a/drivers/sensor/ti/tmp114/tmp114.c b/drivers/sensor/ti/tmp114/tmp114.c
index 6d7409a6ff4..24e50d2e16d 100644
--- a/drivers/sensor/ti/tmp114/tmp114.c
+++ b/drivers/sensor/ti/tmp114/tmp114.c
@@ -9,6 +9,7 @@
 #include <zephyr/device.h>
 #include <zephyr/drivers/i2c.h>
 #include <zephyr/drivers/sensor.h>
+#include <zephyr/dt-bindings/sensor/tmp114.h>
 #include <zephyr/sys/byteorder.h>
 #include <zephyr/sys/__assert.h>
 #include <zephyr/logging/log.h>
@@ -26,8 +27,10 @@ LOG_MODULE_REGISTER(TMP114, CONFIG_SENSOR_LOG_LEVEL);
 
 #define TMP114_DEVICE_ID	0x1114
 
-#define TMP114_ALERT_DATA_READY  BIT(0)
-#define TMP114_AVG_MASK          BIT(7)
+#define TMP114_ALERT_DATA_READY BIT(0)
+#define TMP114_CFGR_AVG		BIT(7)
+#define TMP114_AVG		BIT(7)
+#define TMP114_CFGR_CONV	(BIT(0) | BIT(1) | BIT(2))
 
 struct tmp114_data {
 	uint16_t sample;
@@ -36,15 +39,15 @@ struct tmp114_data {
 
 struct tmp114_dev_config {
 	struct i2c_dt_spec bus;
+	uint16_t odr;
+	bool oversampling;
 };
 
-static int tmp114_reg_read(const struct device *dev, uint8_t reg,
-			   uint16_t *val)
+static int tmp114_reg_read(const struct device *dev, uint8_t reg, uint16_t *val)
 {
 	const struct tmp114_dev_config *cfg = dev->config;
 
-	if (i2c_burst_read_dt(&cfg->bus, reg, (uint8_t *)val, 2)
-	    < 0) {
+	if (i2c_burst_read_dt(&cfg->bus, reg, (uint8_t *)val, 2) < 0) {
 		return -EIO;
 	}
 
@@ -53,8 +56,7 @@ static int tmp114_reg_read(const struct device *dev, uint8_t reg,
 	return 0;
 }
 
-static int tmp114_reg_write(const struct device *dev, uint8_t reg,
-			    uint16_t val)
+static int tmp114_reg_write(const struct device *dev, uint8_t reg, uint16_t val)
 {
 	const struct tmp114_dev_config *cfg = dev->config;
 	uint8_t tx_buf[3] = {reg, val >> 8, val & 0xFF};
@@ -62,6 +64,29 @@ static int tmp114_reg_write(const struct device *dev, uint8_t reg,
 	return i2c_write_dt(&cfg->bus, tx_buf, sizeof(tx_buf));
 }
 
+static int tmp114_write_config(const struct device *dev, uint16_t mask, uint16_t conf)
+{
+	uint16_t config = 0;
+	int result;
+
+	result = tmp114_reg_read(dev, TMP114_REG_CFGR, &config);
+
+	if (result < 0) {
+		return result;
+	}
+
+	config &= ~mask;
+	config |= conf;
+
+	result = tmp114_reg_write(dev, TMP114_REG_CFGR, config);
+
+	if (result < 0) {
+		return result;
+	}
+
+	return 0;
+}
+
 static inline int tmp114_device_id_check(const struct device *dev, uint16_t *id)
 {
 	if (tmp114_reg_read(dev, TMP114_REG_DEVICE_ID, id) != 0) {
@@ -116,8 +141,7 @@ static int tmp114_sample_fetch(const struct device *dev,
 	return 0;
 }
 
-static int tmp114_channel_get(const struct device *dev,
-			      enum sensor_channel chan,
+static int tmp114_channel_get(const struct device *dev, enum sensor_channel chan,
 			      struct sensor_value *val)
 {
 	struct tmp114_data *drv_data = dev->data;
@@ -165,13 +189,38 @@ static int tmp114_attr_get(const struct device *dev, enum sensor_channel chan,
 	return 0;
 }
 
-static int tmp114_attr_set(const struct device *dev,
-			   enum sensor_channel chan,
-			   enum sensor_attribute attr,
-			   const struct sensor_value *val)
+static int tmp114_odr_value(const struct sensor_value *frequency, uint16_t *config_value)
 {
-	int16_t value;
-	int rc;
+	const uint32_t freq_micro = sensor_value_to_micro(frequency);
+
+	if (freq_micro <= 500000) {
+		*config_value = TMP114_DT_ODR_2000_MS; /* 2 s */
+	} else if (freq_micro <= 1000000) {
+		*config_value = TMP114_DT_ODR_1000_MS; /* 1 s */
+	} else if (freq_micro <= 2000000) {
+		*config_value = TMP114_DT_ODR_500_MS; /* 500 ms */
+	} else if (freq_micro <= 4000000) {
+		*config_value = TMP114_DT_ODR_250_MS; /* 250 ms */
+	} else if (freq_micro <= 8000000) {
+		*config_value = TMP114_DT_ODR_125_MS; /* 125 ms */
+	} else if (freq_micro <= 16000000) {
+		*config_value = TMP114_DT_ODR_62_5_MS; /* 62.5 ms */
+	} else if (freq_micro <= 32000000) {
+		*config_value = TMP114_DT_ODR_31_25_MS; /* 32.25 ms */
+	} else if (freq_micro <= 156250000) {
+		*config_value = TMP114_DT_ODR_6_4_MS; /* 6.4 ms */
+	} else {
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static int tmp114_attr_set(const struct device *dev, enum sensor_channel chan,
+			   enum sensor_attribute attr, const struct sensor_value *val)
+{
+	uint16_t value = 0;
+	int rc = 0;
 
 	if (chan != SENSOR_CHAN_AMBIENT_TEMP) {
 		return -ENOTSUP;
@@ -182,16 +231,20 @@ static int tmp114_attr_set(const struct device *dev,
 		/* Enable the AVG in tmp114. The chip will do 8 avg of 8 samples
 		 * to get a more accurate value.
 		 */
-		rc = tmp114_reg_read(dev, TMP114_REG_CFGR, &value);
+
+		if (val->val1) {
+			value = TMP114_AVG;
+		}
+
+		return tmp114_write_config(dev, TMP114_CFGR_AVG, value);
+	case SENSOR_ATTR_SAMPLING_FREQUENCY:
+		/* Set the output data rate tmp114. */
+		rc = tmp114_odr_value(val, &value);
 		if (rc < 0) {
 			return rc;
 		}
-		value = value & ~TMP114_AVG_MASK;
-		if (val->val1) {
-			value |= TMP114_AVG_MASK;
-		}
 
-		return tmp114_reg_write(dev, TMP114_REG_CFGR, value);
+		return tmp114_write_config(dev, TMP114_CFGR_CONV, value);
 	default:
 		return -ENOTSUP;
 	}
@@ -210,6 +263,7 @@ static int tmp114_init(const struct device *dev)
 	const struct tmp114_dev_config *cfg = dev->config;
 	int rc;
 	uint16_t id;
+	struct sensor_value val;
 
 	if (!i2c_is_ready_dt(&cfg->bus)) {
 		LOG_ERR("I2C dev %s not ready", cfg->bus.bus->name);
@@ -224,13 +278,28 @@ static int tmp114_init(const struct device *dev)
 	LOG_INF("Got device ID: %x", id);
 	drv_data->id = id;
 
+	rc = tmp114_write_config(dev, TMP114_CFGR_CONV, cfg->odr);
+	if (rc < 0) {
+		return rc;
+	}
+
+	val.val1 = cfg->oversampling ? 1 : 0;
+	val.val2 = 0;
+
+	rc = tmp114_attr_set(dev, SENSOR_CHAN_AMBIENT_TEMP, SENSOR_ATTR_OVERSAMPLING, &val);
+	if (rc < 0) {
+		return rc;
+	}
+
 	return 0;
 }
 
 #define DEFINE_TMP114(_num) \
 	static struct tmp114_data tmp114_data_##_num; \
 	static const struct tmp114_dev_config tmp114_config_##_num = { \
-		.bus = I2C_DT_SPEC_INST_GET(_num) \
+		.bus = I2C_DT_SPEC_INST_GET(_num), \
+		.odr = DT_INST_PROP(_num, odr), \
+		.oversampling = DT_INST_PROP(_num, oversampling), \
 	}; \
 	SENSOR_DEVICE_DT_INST_DEFINE(_num, tmp114_init, NULL, \
 		&tmp114_data_##_num, &tmp114_config_##_num, POST_KERNEL, \
diff --git a/drivers/sensor/ti/tmp116/CMakeLists.txt b/drivers/sensor/ti/tmp116/CMakeLists.txt
deleted file mode 100644
index ee8d2a64621..00000000000
--- a/drivers/sensor/ti/tmp116/CMakeLists.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_library()
-
-zephyr_library_sources(tmp116.c)
diff --git a/drivers/sensor/ti/tmp116/Kconfig b/drivers/sensor/ti/tmp116/Kconfig
deleted file mode 100644
index 37a5d60ed77..00000000000
--- a/drivers/sensor/ti/tmp116/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-# TMP116 temperature sensor configuration options
-
-# Copyright (c) 2019 Centaur Analytics, Inc
-# SPDX-License-Identifier: Apache-2.0
-
-config TMP116
-	bool "TMP116 and TMP117 Temperature Sensors"
-	default y
-	depends on DT_HAS_TI_TMP116_ENABLED
-	select I2C
-	help
-	  Enable driver for TMP116 and TMP117 temperature sensors.
diff --git a/drivers/sensor/ti/tmp116/tmp116.c b/drivers/sensor/ti/tmp116/tmp116.c
deleted file mode 100644
index 977d010a28f..00000000000
--- a/drivers/sensor/ti/tmp116/tmp116.c
+++ /dev/null
@@ -1,415 +0,0 @@
-/*
- * Copyright (c) 2019 Centaur Analytics, Inc
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DT_DRV_COMPAT ti_tmp116
-
-#include <zephyr/device.h>
-#include <zephyr/drivers/i2c.h>
-#include <zephyr/drivers/sensor.h>
-#include <zephyr/drivers/sensor/tmp116.h>
-#include <zephyr/dt-bindings/sensor/tmp116.h>
-#include <zephyr/sys/util.h>
-#include <zephyr/sys/byteorder.h>
-#include <zephyr/sys/__assert.h>
-#include <zephyr/logging/log.h>
-#include <zephyr/kernel.h>
-
-#include "tmp116.h"
-
-#define  EEPROM_SIZE_REG sizeof(uint16_t)
-#define  EEPROM_TMP117_RESERVED (2 * sizeof(uint16_t))
-#define  EEPROM_MIN_BUSY_MS 7
-
-LOG_MODULE_REGISTER(TMP116, CONFIG_SENSOR_LOG_LEVEL);
-
-static int tmp116_reg_read(const struct device *dev, uint8_t reg,
-			   uint16_t *val)
-{
-	const struct tmp116_dev_config *cfg = dev->config;
-
-	if (i2c_burst_read_dt(&cfg->bus, reg, (uint8_t *)val, 2)
-	    < 0) {
-		return -EIO;
-	}
-
-	*val = sys_be16_to_cpu(*val);
-
-	return 0;
-}
-
-static int tmp116_reg_write(const struct device *dev, uint8_t reg,
-			    uint16_t val)
-{
-	const struct tmp116_dev_config *cfg = dev->config;
-	uint8_t tx_buf[3] = {reg, val >> 8, val & 0xFF};
-
-	return i2c_write_dt(&cfg->bus, tx_buf, sizeof(tx_buf));
-}
-
-int tmp116_write_config(const struct device *dev, uint16_t mask, uint16_t conf)
-{
-	uint16_t config = 0;
-	int result;
-
-	result = tmp116_reg_read(dev, TMP116_REG_CFGR, &config);
-
-	if (result < 0) {
-		return result;
-	}
-
-	config &= ~mask;
-	config |= conf;
-
-	return tmp116_reg_write(dev, TMP116_REG_CFGR, config);
-}
-
-static bool check_eeprom_bounds(const struct device *dev, off_t offset,
-			       size_t len)
-{
-	struct tmp116_data *drv_data = dev->data;
-
-	if ((offset + len) > EEPROM_TMP116_SIZE ||
-	    offset % EEPROM_SIZE_REG != 0 ||
-	    len % EEPROM_SIZE_REG != 0) {
-		return false;
-	}
-
-	/* TMP117 uses EEPROM[2] as temperature offset register */
-	if (drv_data->id == TMP117_DEVICE_ID &&
-	    offset <= EEPROM_TMP117_RESERVED &&
-	    (offset + len) > EEPROM_TMP117_RESERVED) {
-		return false;
-	}
-
-	return true;
-}
-
-int tmp116_eeprom_write(const struct device *dev, off_t offset,
-			const void *data, size_t len)
-{
-	uint8_t reg;
-	const uint16_t *src = data;
-	int res;
-
-	if (!check_eeprom_bounds(dev, offset, len)) {
-		return -EINVAL;
-	}
-
-	res = tmp116_reg_write(dev, TMP116_REG_EEPROM_UL, TMP116_EEPROM_UL_UNLOCK);
-	if (res) {
-		return res;
-	}
-
-	for (reg = (offset / 2); reg < offset / 2 + len / 2; reg++) {
-		uint16_t val = *src;
-
-		res = tmp116_reg_write(dev, reg + TMP116_REG_EEPROM1, val);
-		if (res != 0) {
-			break;
-		}
-
-		k_sleep(K_MSEC(EEPROM_MIN_BUSY_MS));
-
-		do {
-			res = tmp116_reg_read(dev, TMP116_REG_EEPROM_UL, &val);
-			if (res != 0) {
-				break;
-			}
-		} while (val & TMP116_EEPROM_UL_BUSY);
-		src++;
-
-		if (res != 0) {
-			break;
-		}
-	}
-
-	res = tmp116_reg_write(dev, TMP116_REG_EEPROM_UL, 0);
-
-	return res;
-}
-
-int tmp116_eeprom_read(const struct device *dev, off_t offset, void *data,
-		       size_t len)
-{
-	uint8_t reg;
-	uint16_t *dst = data;
-	int res = 0;
-
-	if (!check_eeprom_bounds(dev, offset, len)) {
-		return -EINVAL;
-	}
-
-	for (reg = (offset / 2); reg < offset / 2 + len / 2; reg++) {
-		res = tmp116_reg_read(dev, reg + TMP116_REG_EEPROM1, dst);
-		if (res != 0) {
-			break;
-		}
-		dst++;
-	}
-
-	return res;
-}
-
-
-/**
- * @brief Check the Device ID
- *
- * @param[in]   dev     Pointer to the device structure
- * @param[in]	id	Pointer to the variable for storing the device id
- *
- * @retval 0 on success
- * @retval -EIO Otherwise
- */
-static inline int tmp116_device_id_check(const struct device *dev, uint16_t *id)
-{
-	if (tmp116_reg_read(dev, TMP116_REG_DEVICE_ID, id) != 0) {
-		LOG_ERR("%s: Failed to get Device ID register!",
-			dev->name);
-		return -EIO;
-	}
-
-	if ((*id != TMP116_DEVICE_ID) && (*id != TMP117_DEVICE_ID)) {
-		LOG_ERR("%s: Failed to match the device IDs!",
-			dev->name);
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static int tmp116_sample_fetch(const struct device *dev,
-			       enum sensor_channel chan)
-{
-	struct tmp116_data *drv_data = dev->data;
-	uint16_t value;
-	uint16_t cfg_reg = 0;
-	int rc;
-
-	__ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL ||
-			chan == SENSOR_CHAN_AMBIENT_TEMP);
-
-	/* clear sensor values */
-	drv_data->sample = 0U;
-
-	/* Make sure that a data is available */
-	rc = tmp116_reg_read(dev, TMP116_REG_CFGR, &cfg_reg);
-	if (rc < 0) {
-		LOG_ERR("%s, Failed to read from CFGR register",
-			dev->name);
-		return rc;
-	}
-
-	if ((cfg_reg & TMP116_CFGR_DATA_READY) == 0) {
-		LOG_DBG("%s: no data ready", dev->name);
-		return -EBUSY;
-	}
-
-	/* Get the most recent temperature measurement */
-	rc = tmp116_reg_read(dev, TMP116_REG_TEMP, &value);
-	if (rc < 0) {
-		LOG_ERR("%s: Failed to read from TEMP register!",
-			dev->name);
-		return rc;
-	}
-
-	/* store measurements to the driver */
-	drv_data->sample = (int16_t)value;
-
-	return 0;
-}
-
-static int tmp116_channel_get(const struct device *dev,
-			      enum sensor_channel chan,
-			      struct sensor_value *val)
-{
-	struct tmp116_data *drv_data = dev->data;
-	int32_t tmp;
-
-	if (chan != SENSOR_CHAN_AMBIENT_TEMP) {
-		return -ENOTSUP;
-	}
-
-	/*
-	 * See datasheet "Temperature Results and Limits" section for more
-	 * details on processing sample data.
-	 */
-	tmp = ((int16_t)drv_data->sample * (int32_t)TMP116_RESOLUTION) / 10;
-	val->val1 = tmp / 1000000; /* uCelsius */
-	val->val2 = tmp % 1000000;
-
-	return 0;
-}
-
-static int16_t tmp116_conv_value(const struct sensor_value *val)
-{
-	uint32_t freq_micro = sensor_value_to_micro(val);
-
-	switch (freq_micro) {
-	case 64000000: /* 1 / 15.5 ms has been rounded down */
-		return TMP116_DT_ODR_15_5_MS;
-	case 8000000:
-		return TMP116_DT_ODR_125_MS;
-	case 4000000:
-		return TMP116_DT_ODR_250_MS;
-	case 2000000:
-		return TMP116_DT_ODR_500_MS;
-	case 1000000:
-		return TMP116_DT_ODR_1000_MS;
-	case 250000:
-		return TMP116_DT_ODR_4000_MS;
-	case 125000:
-		return TMP116_DT_ODR_8000_MS;
-	case 62500:
-		return TMP116_DT_ODR_16000_MS;
-	default:
-		LOG_ERR("%" PRIu32 " uHz not supported", freq_micro);
-		return -EINVAL;
-	}
-}
-
-static int tmp116_attr_set(const struct device *dev,
-			   enum sensor_channel chan,
-			   enum sensor_attribute attr,
-			   const struct sensor_value *val)
-{
-	struct tmp116_data *drv_data = dev->data;
-	int16_t value;
-	uint16_t avg;
-
-	if (chan != SENSOR_CHAN_AMBIENT_TEMP) {
-		return -ENOTSUP;
-	}
-
-	switch ((int)attr) {
-	case SENSOR_ATTR_SAMPLING_FREQUENCY:
-		value = tmp116_conv_value(val);
-		if (value < 0) {
-			return value;
-		}
-
-		return tmp116_write_config(dev, TMP116_CFGR_CONV, value);
-
-	case SENSOR_ATTR_OFFSET:
-		if (drv_data->id != TMP117_DEVICE_ID) {
-			LOG_ERR("%s: Offset is only supported by TMP117",
-			dev->name);
-			return -EINVAL;
-		}
-		/*
-		 * The offset is encoded into the temperature register format.
-		 */
-		value = (((val->val1) * 10000000) + ((val->val2) * 10))
-						/ (int32_t)TMP116_RESOLUTION;
-
-		return tmp116_reg_write(dev, TMP117_REG_TEMP_OFFSET, value);
-
-	case SENSOR_ATTR_OVERSAMPLING:
-		/* sensor supports averaging 1, 8, 32 and 64 samples */
-		switch (val->val1) {
-		case 1:
-			avg = TMP116_AVG_1_SAMPLE;
-			break;
-
-		case 8:
-			avg = TMP116_AVG_8_SAMPLES;
-			break;
-
-		case 32:
-			avg = TMP116_AVG_32_SAMPLES;
-			break;
-
-		case 64:
-			avg = TMP116_AVG_64_SAMPLES;
-			break;
-
-		default:
-			return -EINVAL;
-		}
-		return tmp116_write_config(dev, TMP116_CFGR_AVG, avg);
-	case SENSOR_ATTR_TMP116_SHUTDOWN_MODE:
-		return tmp116_write_config(dev, TMP116_CFGR_MODE, TMP116_MODE_SHUTDOWN);
-
-	case SENSOR_ATTR_TMP116_CONTINUOUS_CONVERSION_MODE:
-		return tmp116_write_config(dev, TMP116_CFGR_MODE, TMP116_MODE_CONTINUOUS);
-
-	case SENSOR_ATTR_TMP116_ONE_SHOT_MODE:
-		return tmp116_write_config(dev, TMP116_CFGR_MODE, TMP116_MODE_ONE_SHOT);
-
-	default:
-		return -ENOTSUP;
-	}
-}
-
-static int tmp116_attr_get(const struct device *dev, enum sensor_channel chan,
-			   enum sensor_attribute attr, struct sensor_value *val)
-{
-	uint16_t data;
-	int rc;
-
-	if (chan != SENSOR_CHAN_AMBIENT_TEMP) {
-		return -ENOTSUP;
-	}
-
-	switch (attr) {
-	case SENSOR_ATTR_CONFIGURATION:
-		rc = tmp116_reg_read(dev, TMP116_REG_CFGR, &data);
-		if (rc < 0) {
-			return rc;
-		}
-		break;
-	default:
-		return -ENOTSUP;
-	}
-
-	val->val1 = data;
-	val->val2 = 0;
-
-	return 0;
-}
-
-static DEVICE_API(sensor, tmp116_driver_api) = {
-	.attr_set = tmp116_attr_set,
-	.attr_get = tmp116_attr_get,
-	.sample_fetch = tmp116_sample_fetch,
-	.channel_get = tmp116_channel_get
-};
-
-static int tmp116_init(const struct device *dev)
-{
-	struct tmp116_data *drv_data = dev->data;
-	const struct tmp116_dev_config *cfg = dev->config;
-	int rc;
-	uint16_t id;
-
-	if (!device_is_ready(cfg->bus.bus)) {
-		LOG_ERR("I2C dev %s not ready", cfg->bus.bus->name);
-		return -EINVAL;
-	}
-
-	/* Check the Device ID */
-	rc = tmp116_device_id_check(dev, &id);
-	if (rc < 0) {
-		return rc;
-	}
-	LOG_DBG("Got device ID: %x", id);
-	drv_data->id = id;
-
-	rc = tmp116_write_config(dev, TMP116_CFGR_CONV, cfg->odr);
-
-	return rc;
-}
-
-#define DEFINE_TMP116(_num) \
-	static struct tmp116_data tmp116_data_##_num; \
-	static const struct tmp116_dev_config tmp116_config_##_num = { \
-		.bus = I2C_DT_SPEC_INST_GET(_num), \
-		.odr = DT_INST_PROP(_num, odr), \
-	}; \
-	SENSOR_DEVICE_DT_INST_DEFINE(_num, tmp116_init, NULL, \
-		&tmp116_data_##_num, &tmp116_config_##_num, POST_KERNEL, \
-		CONFIG_SENSOR_INIT_PRIORITY, &tmp116_driver_api);
-
-DT_INST_FOREACH_STATUS_OKAY(DEFINE_TMP116)
diff --git a/drivers/sensor/ti/tmp116/tmp116.h b/drivers/sensor/ti/tmp116/tmp116.h
deleted file mode 100644
index 6211d9a71f1..00000000000
--- a/drivers/sensor/ti/tmp116/tmp116.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (c) 2019 Centaur Analytics, Inc
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_DRIVERS_SENSOR_TMP116_TMP116_H_
-#define ZEPHYR_DRIVERS_SENSOR_TMP116_TMP116_H_
-
-#include <zephyr/sys/util_macro.h>
-
-#define TMP116_REG_TEMP		0x0
-#define TMP116_REG_CFGR		0x1
-#define TMP116_REG_HIGH_LIM		0x2
-#define TMP116_REG_LOW_LIM		0x3
-#define TMP116_REG_EEPROM_UL		0x4
-#define TMP116_REG_EEPROM1		0x5
-#define TMP116_REG_EEPROM2		0x6
-#define TMP116_REG_EEPROM3		0x7
-#define TMP117_REG_TEMP_OFFSET		0x7
-#define TMP116_REG_EEPROM4		0x8
-#define TMP116_REG_DEVICE_ID		0xF
-
-#define TMP116_RESOLUTION		78125       /* in tens of uCelsius*/
-#define TMP116_RESOLUTION_DIV		10000000
-
-#define TMP116_DEVICE_ID		0x1116
-#define TMP117_DEVICE_ID		0x0117
-
-#define TMP116_CFGR_AVG			(BIT(5) | BIT(6))
-#define TMP116_CFGR_CONV		(BIT(7) | BIT(8) | BIT(9))
-#define TMP116_CFGR_MODE		(BIT(10) | BIT(11))
-#define TMP116_CFGR_DATA_READY  BIT(13)
-#define TMP116_EEPROM_UL_UNLOCK BIT(15)
-#define TMP116_EEPROM_UL_BUSY   BIT(14)
-
-#define TMP116_AVG_1_SAMPLE		0
-#define TMP116_AVG_8_SAMPLES	BIT(5)
-#define TMP116_AVG_32_SAMPLES	BIT(6)
-#define TMP116_AVG_64_SAMPLES	(BIT(5) | BIT(6))
-#define TMP116_MODE_CONTINUOUS	0
-#define TMP116_MODE_SHUTDOWN	BIT(10)
-#define TMP116_MODE_ONE_SHOT	(BIT(10) | BIT(11))
-
-struct tmp116_data {
-	uint16_t sample;
-	uint16_t id;
-};
-
-struct tmp116_dev_config {
-	struct i2c_dt_spec bus;
-	uint16_t odr;
-};
-
-#endif /*  ZEPHYR_DRIVERS_SENSOR_TMP116_TMP116_H_ */
diff --git a/drivers/sensor/ti/tmp11x/CMakeLists.txt b/drivers/sensor/ti/tmp11x/CMakeLists.txt
new file mode 100644
index 00000000000..48d083d2b1b
--- /dev/null
+++ b/drivers/sensor/ti/tmp11x/CMakeLists.txt
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(tmp11x.c)
diff --git a/drivers/sensor/ti/tmp11x/Kconfig b/drivers/sensor/ti/tmp11x/Kconfig
new file mode 100644
index 00000000000..e66ea0a7a54
--- /dev/null
+++ b/drivers/sensor/ti/tmp11x/Kconfig
@@ -0,0 +1,12 @@
+# TMP11X temperature sensor configuration options
+
+# Copyright (c) 2019 Centaur Analytics, Inc
+# SPDX-License-Identifier: Apache-2.0
+
+config TMP11X
+	bool "TMP116, TMP117 and TMP119 Temperature Sensors"
+	default y
+	depends on DT_HAS_TI_TMP11X_ENABLED
+	select I2C
+	help
+	  Enable driver for TMP116, TMP117 and TMP119 temperature sensors.
diff --git a/drivers/sensor/ti/tmp11x/tmp11x.c b/drivers/sensor/ti/tmp11x/tmp11x.c
new file mode 100644
index 00000000000..cfb1abd6a07
--- /dev/null
+++ b/drivers/sensor/ti/tmp11x/tmp11x.c
@@ -0,0 +1,420 @@
+/*
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ti_tmp11x
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/sensor/tmp11x.h>
+#include <zephyr/dt-bindings/sensor/tmp11x.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/kernel.h>
+
+#include "tmp11x.h"
+
+#define  EEPROM_SIZE_REG sizeof(uint16_t)
+#define  EEPROM_TMP117_RESERVED (2 * sizeof(uint16_t))
+#define  EEPROM_MIN_BUSY_MS 7
+
+LOG_MODULE_REGISTER(TMP11X, CONFIG_SENSOR_LOG_LEVEL);
+
+static int tmp11x_reg_read(const struct device *dev, uint8_t reg,
+			   uint16_t *val)
+{
+	const struct tmp11x_dev_config *cfg = dev->config;
+
+	if (i2c_burst_read_dt(&cfg->bus, reg, (uint8_t *)val, 2)
+	    < 0) {
+		return -EIO;
+	}
+
+	*val = sys_be16_to_cpu(*val);
+
+	return 0;
+}
+
+static int tmp11x_reg_write(const struct device *dev, uint8_t reg,
+			    uint16_t val)
+{
+	const struct tmp11x_dev_config *cfg = dev->config;
+	uint8_t tx_buf[3] = {reg, val >> 8, val & 0xFF};
+
+	return i2c_write_dt(&cfg->bus, tx_buf, sizeof(tx_buf));
+}
+
+int tmp11x_write_config(const struct device *dev, uint16_t mask, uint16_t conf)
+{
+	uint16_t config = 0;
+	int result;
+
+	result = tmp11x_reg_read(dev, TMP11X_REG_CFGR, &config);
+
+	if (result < 0) {
+		return result;
+	}
+
+	config &= ~mask;
+	config |= conf;
+
+	return tmp11x_reg_write(dev, TMP11X_REG_CFGR, config);
+}
+
+static bool check_eeprom_bounds(const struct device *dev, off_t offset,
+			       size_t len)
+{
+	struct tmp11x_data *drv_data = dev->data;
+
+	if ((offset + len) > EEPROM_TMP11X_SIZE ||
+	    offset % EEPROM_SIZE_REG != 0 ||
+	    len % EEPROM_SIZE_REG != 0) {
+		return false;
+	}
+
+	/* TMP117 and TMP119 uses EEPROM[2] as temperature offset register */
+	if ((drv_data->id == TMP117_DEVICE_ID || drv_data->id == TMP119_DEVICE_ID) &&
+	    offset <= EEPROM_TMP117_RESERVED && (offset + len) > EEPROM_TMP117_RESERVED) {
+		return false;
+	}
+
+	return true;
+}
+
+int tmp11x_eeprom_write(const struct device *dev, off_t offset,
+			const void *data, size_t len)
+{
+	uint8_t reg;
+	const uint16_t *src = data;
+	int res;
+
+	if (!check_eeprom_bounds(dev, offset, len)) {
+		return -EINVAL;
+	}
+
+	res = tmp11x_reg_write(dev, TMP11X_REG_EEPROM_UL, TMP11X_EEPROM_UL_UNLOCK);
+	if (res) {
+		return res;
+	}
+
+	for (reg = (offset / 2); reg < offset / 2 + len / 2; reg++) {
+		uint16_t val = *src;
+
+		res = tmp11x_reg_write(dev, reg + TMP11X_REG_EEPROM1, val);
+		if (res != 0) {
+			break;
+		}
+
+		k_sleep(K_MSEC(EEPROM_MIN_BUSY_MS));
+
+		do {
+			res = tmp11x_reg_read(dev, TMP11X_REG_EEPROM_UL, &val);
+			if (res != 0) {
+				break;
+			}
+		} while (val & TMP11X_EEPROM_UL_BUSY);
+		src++;
+
+		if (res != 0) {
+			break;
+		}
+	}
+
+	res = tmp11x_reg_write(dev, TMP11X_REG_EEPROM_UL, 0);
+
+	return res;
+}
+
+int tmp11x_eeprom_read(const struct device *dev, off_t offset, void *data,
+		       size_t len)
+{
+	uint8_t reg;
+	uint16_t *dst = data;
+	int res = 0;
+
+	if (!check_eeprom_bounds(dev, offset, len)) {
+		return -EINVAL;
+	}
+
+	for (reg = (offset / 2); reg < offset / 2 + len / 2; reg++) {
+		res = tmp11x_reg_read(dev, reg + TMP11X_REG_EEPROM1, dst);
+		if (res != 0) {
+			break;
+		}
+		dst++;
+	}
+
+	return res;
+}
+
+
+/**
+ * @brief Check the Device ID
+ *
+ * @param[in]   dev     Pointer to the device structure
+ * @param[in]	id	Pointer to the variable for storing the device id
+ *
+ * @retval 0 on success
+ * @retval -EIO Otherwise
+ */
+static inline int tmp11x_device_id_check(const struct device *dev, uint16_t *id)
+{
+	if (tmp11x_reg_read(dev, TMP11X_REG_DEVICE_ID, id) != 0) {
+		LOG_ERR("%s: Failed to get Device ID register!",
+			dev->name);
+		return -EIO;
+	}
+
+	if ((*id != TMP116_DEVICE_ID) && (*id != TMP117_DEVICE_ID) && (*id != TMP119_DEVICE_ID)) {
+		LOG_ERR("%s: Failed to match the device IDs!",
+			dev->name);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int tmp11x_sample_fetch(const struct device *dev,
+			       enum sensor_channel chan)
+{
+	struct tmp11x_data *drv_data = dev->data;
+	uint16_t value;
+	uint16_t cfg_reg = 0;
+	int rc;
+
+	__ASSERT_NO_MSG(chan == SENSOR_CHAN_ALL ||
+			chan == SENSOR_CHAN_AMBIENT_TEMP);
+
+	/* clear sensor values */
+	drv_data->sample = 0U;
+
+	/* Make sure that a data is available */
+	rc = tmp11x_reg_read(dev, TMP11X_REG_CFGR, &cfg_reg);
+	if (rc < 0) {
+		LOG_ERR("%s, Failed to read from CFGR register",
+			dev->name);
+		return rc;
+	}
+
+	if ((cfg_reg & TMP11X_CFGR_DATA_READY) == 0) {
+		LOG_DBG("%s: no data ready", dev->name);
+		return -EBUSY;
+	}
+
+	/* Get the most recent temperature measurement */
+	rc = tmp11x_reg_read(dev, TMP11X_REG_TEMP, &value);
+	if (rc < 0) {
+		LOG_ERR("%s: Failed to read from TEMP register!",
+			dev->name);
+		return rc;
+	}
+
+	/* store measurements to the driver */
+	drv_data->sample = (int16_t)value;
+
+	return 0;
+}
+
+static int tmp11x_channel_get(const struct device *dev,
+			      enum sensor_channel chan,
+			      struct sensor_value *val)
+{
+	struct tmp11x_data *drv_data = dev->data;
+	int32_t tmp;
+
+	if (chan != SENSOR_CHAN_AMBIENT_TEMP) {
+		return -ENOTSUP;
+	}
+
+	/*
+	 * See datasheet "Temperature Results and Limits" section for more
+	 * details on processing sample data.
+	 */
+	tmp = ((int16_t)drv_data->sample * (int32_t)TMP11X_RESOLUTION) / 10;
+	val->val1 = tmp / 1000000; /* uCelsius */
+	val->val2 = tmp % 1000000;
+
+	return 0;
+}
+
+static int16_t tmp11x_conv_value(const struct sensor_value *val)
+{
+	uint32_t freq_micro = sensor_value_to_micro(val);
+
+	switch (freq_micro) {
+	case 64000000: /* 1 / 15.5 ms has been rounded down */
+		return TMP11X_DT_ODR_15_5_MS;
+	case 8000000:
+		return TMP11X_DT_ODR_125_MS;
+	case 4000000:
+		return TMP11X_DT_ODR_250_MS;
+	case 2000000:
+		return TMP11X_DT_ODR_500_MS;
+	case 1000000:
+		return TMP11X_DT_ODR_1000_MS;
+	case 250000:
+		return TMP11X_DT_ODR_4000_MS;
+	case 125000:
+		return TMP11X_DT_ODR_8000_MS;
+	case 62500:
+		return TMP11X_DT_ODR_16000_MS;
+	default:
+		LOG_ERR("%" PRIu32 " uHz not supported", freq_micro);
+		return -EINVAL;
+	}
+}
+
+static int tmp11x_attr_set(const struct device *dev,
+			   enum sensor_channel chan,
+			   enum sensor_attribute attr,
+			   const struct sensor_value *val)
+{
+	struct tmp11x_data *drv_data = dev->data;
+	int16_t value;
+	uint16_t avg;
+
+	if (chan != SENSOR_CHAN_AMBIENT_TEMP) {
+		return -ENOTSUP;
+	}
+
+	switch ((int)attr) {
+	case SENSOR_ATTR_SAMPLING_FREQUENCY:
+		value = tmp11x_conv_value(val);
+		if (value < 0) {
+			return value;
+		}
+
+		return tmp11x_write_config(dev, TMP11X_CFGR_CONV, value);
+
+	case SENSOR_ATTR_OFFSET:
+		if (drv_data->id != TMP117_DEVICE_ID && drv_data->id != TMP119_DEVICE_ID) {
+			LOG_ERR("%s: Offset is only supported by TMP117 and TMP119",
+			dev->name);
+			return -EINVAL;
+		}
+		/*
+		 * The offset is encoded into the temperature register format.
+		 */
+		value = (((val->val1) * 10000000) + ((val->val2) * 10))
+						/ (int32_t)TMP11X_RESOLUTION;
+
+		return tmp11x_reg_write(dev, TMP117_REG_TEMP_OFFSET, value);
+
+	case SENSOR_ATTR_OVERSAMPLING:
+		/* sensor supports averaging 1, 8, 32 and 64 samples */
+		switch (val->val1) {
+		case 1:
+			avg = TMP11X_AVG_1_SAMPLE;
+			break;
+
+		case 8:
+			avg = TMP11X_AVG_8_SAMPLES;
+			break;
+
+		case 32:
+			avg = TMP11X_AVG_32_SAMPLES;
+			break;
+
+		case 64:
+			avg = TMP11X_AVG_64_SAMPLES;
+			break;
+
+		default:
+			return -EINVAL;
+		}
+		return tmp11x_write_config(dev, TMP11X_CFGR_AVG, avg);
+	case SENSOR_ATTR_TMP11X_SHUTDOWN_MODE:
+		return tmp11x_write_config(dev, TMP11X_CFGR_MODE, TMP11X_MODE_SHUTDOWN);
+
+	case SENSOR_ATTR_TMP11X_CONTINUOUS_CONVERSION_MODE:
+		return tmp11x_write_config(dev, TMP11X_CFGR_MODE, TMP11X_MODE_CONTINUOUS);
+
+	case SENSOR_ATTR_TMP11X_ONE_SHOT_MODE:
+		return tmp11x_write_config(dev, TMP11X_CFGR_MODE, TMP11X_MODE_ONE_SHOT);
+
+	default:
+		return -ENOTSUP;
+	}
+}
+
+static int tmp11x_attr_get(const struct device *dev, enum sensor_channel chan,
+			   enum sensor_attribute attr, struct sensor_value *val)
+{
+	uint16_t data;
+	int rc;
+
+	if (chan != SENSOR_CHAN_AMBIENT_TEMP) {
+		return -ENOTSUP;
+	}
+
+	switch (attr) {
+	case SENSOR_ATTR_CONFIGURATION:
+		rc = tmp11x_reg_read(dev, TMP11X_REG_CFGR, &data);
+		if (rc < 0) {
+			return rc;
+		}
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	val->val1 = data;
+	val->val2 = 0;
+
+	return 0;
+}
+
+static DEVICE_API(sensor, tmp11x_driver_api) = {
+	.attr_set = tmp11x_attr_set,
+	.attr_get = tmp11x_attr_get,
+	.sample_fetch = tmp11x_sample_fetch,
+	.channel_get = tmp11x_channel_get
+};
+
+static int tmp11x_init(const struct device *dev)
+{
+	struct tmp11x_data *drv_data = dev->data;
+	const struct tmp11x_dev_config *cfg = dev->config;
+	int rc;
+	uint16_t id;
+
+	if (!device_is_ready(cfg->bus.bus)) {
+		LOG_ERR("I2C dev %s not ready", cfg->bus.bus->name);
+		return -EINVAL;
+	}
+
+	/* Check the Device ID */
+	rc = tmp11x_device_id_check(dev, &id);
+	if (rc < 0) {
+		return rc;
+	}
+	LOG_DBG("Got device ID: %x", id);
+	drv_data->id = id;
+
+	rc = tmp11x_write_config(dev, TMP11X_CFGR_CONV, cfg->odr);
+	if (rc < 0) {
+		return rc;
+	}
+
+	rc = tmp11x_write_config(dev, TMP11X_CFGR_AVG, cfg->oversampling);
+
+	return rc;
+}
+
+#define DEFINE_TMP11X(_num) \
+	static struct tmp11x_data tmp11x_data_##_num; \
+	static const struct tmp11x_dev_config tmp11x_config_##_num = { \
+		.bus = I2C_DT_SPEC_INST_GET(_num), \
+		.odr = DT_INST_PROP(_num, odr), \
+		.oversampling = DT_INST_PROP(_num, oversampling), \
+	}; \
+	SENSOR_DEVICE_DT_INST_DEFINE(_num, tmp11x_init, NULL, \
+		&tmp11x_data_##_num, &tmp11x_config_##_num, POST_KERNEL, \
+		CONFIG_SENSOR_INIT_PRIORITY, &tmp11x_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(DEFINE_TMP11X)
diff --git a/drivers/sensor/ti/tmp11x/tmp11x.h b/drivers/sensor/ti/tmp11x/tmp11x.h
new file mode 100644
index 00000000000..c1e075955f2
--- /dev/null
+++ b/drivers/sensor/ti/tmp11x/tmp11x.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_TMP11X_TMP11X_H_
+#define ZEPHYR_DRIVERS_SENSOR_TMP11X_TMP11X_H_
+
+#include <zephyr/sys/util_macro.h>
+
+#define TMP11X_REG_TEMP		0x0
+#define TMP11X_REG_CFGR		0x1
+#define TMP11X_REG_HIGH_LIM		0x2
+#define TMP11X_REG_LOW_LIM		0x3
+#define TMP11X_REG_EEPROM_UL		0x4
+#define TMP11X_REG_EEPROM1		0x5
+#define TMP11X_REG_EEPROM2		0x6
+#define TMP11X_REG_EEPROM3		0x7
+#define TMP117_REG_TEMP_OFFSET		0x7
+#define TMP11X_REG_EEPROM4		0x8
+#define TMP11X_REG_DEVICE_ID		0xF
+
+#define TMP11X_RESOLUTION		78125       /* in tens of uCelsius*/
+#define TMP11X_RESOLUTION_DIV		10000000
+
+#define TMP116_DEVICE_ID		0x1116
+#define TMP117_DEVICE_ID		0x0117
+#define TMP119_DEVICE_ID		0x2117
+
+#define TMP11X_CFGR_AVG			(BIT(5) | BIT(6))
+#define TMP11X_CFGR_CONV		(BIT(7) | BIT(8) | BIT(9))
+#define TMP11X_CFGR_MODE		(BIT(10) | BIT(11))
+#define TMP11X_CFGR_DATA_READY  BIT(13)
+#define TMP11X_EEPROM_UL_UNLOCK BIT(15)
+#define TMP11X_EEPROM_UL_BUSY   BIT(14)
+
+#define TMP11X_AVG_1_SAMPLE		0
+#define TMP11X_AVG_8_SAMPLES	BIT(5)
+#define TMP11X_AVG_32_SAMPLES	BIT(6)
+#define TMP11X_AVG_64_SAMPLES	(BIT(5) | BIT(6))
+#define TMP11X_MODE_CONTINUOUS	0
+#define TMP11X_MODE_SHUTDOWN	BIT(10)
+#define TMP11X_MODE_ONE_SHOT	(BIT(10) | BIT(11))
+
+struct tmp11x_data {
+	uint16_t sample;
+	uint16_t id;
+};
+
+struct tmp11x_dev_config {
+	struct i2c_dt_spec bus;
+	uint16_t odr;
+	uint16_t oversampling;
+};
+
+#endif /*  ZEPHYR_DRIVERS_SENSOR_TMP11X_TMP11X_H_ */
diff --git a/drivers/sensor/ti/tmp435/tmp435.c b/drivers/sensor/ti/tmp435/tmp435.c
index 54cda9f402f..d1c27f83cd7 100644
--- a/drivers/sensor/ti/tmp435/tmp435.c
+++ b/drivers/sensor/ti/tmp435/tmp435.c
@@ -143,7 +143,7 @@ static int tmp435_channel_get(const struct device *dev, enum sensor_channel chan
 	return ret;
 }
 
-static const struct sensor_driver_api tmp435_driver_api = {
+static DEVICE_API(sensor, tmp435_driver_api) = {
 	.sample_fetch = tmp435_sample_fetch,
 	.channel_get = tmp435_channel_get,
 };
diff --git a/drivers/sensor/tsic_xx6/tsic_xx6.c b/drivers/sensor/tsic_xx6/tsic_xx6.c
index c223e222bb6..d9db1467d74 100644
--- a/drivers/sensor/tsic_xx6/tsic_xx6.c
+++ b/drivers/sensor/tsic_xx6/tsic_xx6.c
@@ -160,7 +160,7 @@ static void tsic_xx6_get_value(const struct tsic_xx6_config *config, struct tsic
 {
 	int64_t tmp;
 
-	/* Apply the datasheet formula scaled to micro celcius */
+	/* Apply the datasheet formula scaled to micro celsius */
 	tmp = (int64_t)data_bits *
 	      (config->higher_temperature_limit - config->lower_temperature_limit);
 	tmp = tmp * 1000000 / (BIT(config->data_bits) - 1);
diff --git a/drivers/sensor/vishay/vcnl4040/vcnl4040.c b/drivers/sensor/vishay/vcnl4040/vcnl4040.c
index 73690f520ed..03f0d1e4e45 100644
--- a/drivers/sensor/vishay/vcnl4040/vcnl4040.c
+++ b/drivers/sensor/vishay/vcnl4040/vcnl4040.c
@@ -136,21 +136,21 @@ static int vcnl4040_reg_setup(const struct device *dev)
 
 	/*
 	 * scale the lux depending on the value of the integration time
-	 * see page 8 of the VCNL4040 application note:
-	 * https://www.vishay.com/docs/84307/designingvcnl4040.pdf
+	 * see page 12 of the VCNL4040 application note:
+	 * https://www.vishay.com/docs/84274/vcnl4040.pdf
 	 */
 	switch (config->als_it) {
 	case VCNL4040_AMBIENT_INTEGRATION_TIME_80MS:
-		data->sensitivity = 0.12;
+		data->sensitivity = 0.1;
 		break;
 	case VCNL4040_AMBIENT_INTEGRATION_TIME_160MS:
-		data->sensitivity = 0.06;
+		data->sensitivity = 0.05;
 		break;
 	case VCNL4040_AMBIENT_INTEGRATION_TIME_320MS:
-		data->sensitivity = 0.03;
+		data->sensitivity = 0.025;
 		break;
 	case VCNL4040_AMBIENT_INTEGRATION_TIME_640MS:
-		data->sensitivity = 0.015;
+		data->sensitivity = 0.0125;
 		break;
 	default:
 		data->sensitivity = 1.0;
diff --git a/drivers/sensor/voltage_divider/voltage.c b/drivers/sensor/voltage_divider/voltage.c
index 090c879a54c..97d2523bd77 100644
--- a/drivers/sensor/voltage_divider/voltage.c
+++ b/drivers/sensor/voltage_divider/voltage.c
@@ -40,6 +40,14 @@ static int fetch(const struct device *dev, enum sensor_channel chan)
 	/* Wait until sampling is valid */
 	k_sleep(data->earliest_sample);
 
+	/* configure the active channel to be converted */
+	ret = adc_channel_setup_dt(&config->voltage.port);
+	if (ret != 0) {
+		LOG_ERR("adc_setup failed: %d", ret);
+		return ret;
+	}
+
+	/* start conversion */
 	ret = adc_read(config->voltage.port.dev, &data->sequence);
 	if (ret != 0) {
 		LOG_ERR("adc_read: %d", ret);
diff --git a/drivers/sensor/wsen/CMakeLists.txt b/drivers/sensor/wsen/CMakeLists.txt
index fc72c7754bd..035878a3ad0 100644
--- a/drivers/sensor/wsen/CMakeLists.txt
+++ b/drivers/sensor/wsen/CMakeLists.txt
@@ -4,4 +4,7 @@
 
 # zephyr-keep-sorted-start
 add_subdirectory_ifdef(CONFIG_WSEN_HIDS_2525020210002 wsen_hids_2525020210002)
+add_subdirectory_ifdef(CONFIG_WSEN_PADS_2511020213301 wsen_pads_2511020213301)
+add_subdirectory_ifdef(CONFIG_WSEN_PDUS_25131308XXXXX wsen_pdus_25131308XXXXX)
+add_subdirectory_ifdef(CONFIG_WSEN_TIDS_2521020222501 wsen_tids_2521020222501)
 # zephyr-keep-sorted-stop
diff --git a/drivers/sensor/wsen/Kconfig b/drivers/sensor/wsen/Kconfig
index 39d727f9f4f..4f7ebd9c3be 100644
--- a/drivers/sensor/wsen/Kconfig
+++ b/drivers/sensor/wsen/Kconfig
@@ -4,4 +4,7 @@
 
 # zephyr-keep-sorted-start
 source "drivers/sensor/wsen/wsen_hids_2525020210002/Kconfig"
+source "drivers/sensor/wsen/wsen_pads_2511020213301/Kconfig"
+source "drivers/sensor/wsen/wsen_pdus_25131308XXXXX/Kconfig"
+source "drivers/sensor/wsen/wsen_tids_2521020222501/Kconfig"
 # zephyr-keep-sorted-stop
diff --git a/drivers/sensor/wsen/wsen_pads_2511020213301/CMakeLists.txt b/drivers/sensor/wsen/wsen_pads_2511020213301/CMakeLists.txt
new file mode 100644
index 00000000000..60c9fbf8286
--- /dev/null
+++ b/drivers/sensor/wsen/wsen_pads_2511020213301/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(wsen_pads_2511020213301.c)
+zephyr_library_sources_ifdef(CONFIG_WSEN_PADS_2511020213301_TRIGGER wsen_pads_2511020213301_trigger.c)
diff --git a/drivers/sensor/wsen/wsen_pads_2511020213301/Kconfig b/drivers/sensor/wsen/wsen_pads_2511020213301/Kconfig
new file mode 100644
index 00000000000..489e261edf3
--- /dev/null
+++ b/drivers/sensor/wsen/wsen_pads_2511020213301/Kconfig
@@ -0,0 +1,62 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig WSEN_PADS_2511020213301
+	bool "WSEN-PADS-2511020213301 absolute pressure and temperature sensor"
+	default y
+	depends on DT_HAS_WE_WSEN_PADS_2511020213301_ENABLED
+	select I2C if $(dt_compat_on_bus,$(DT_COMPAT_WE_WSEN_PADS),i2c)
+	select SPI if $(dt_compat_on_bus,$(DT_COMPAT_WE_WSEN_PADS),spi)
+	select HAS_WESENSORS
+	help
+	  Enable driver for the WSEN-PADS-2511020213301 I2C/SPI-based absolute pressure sensor with integrated
+	  temperature sensor.
+
+if WSEN_PADS_2511020213301
+
+choice WSEN_PADS_2511020213301_TRIGGER_MODE
+	prompt "Trigger mode"
+	default WSEN_PADS_2511020213301_TRIGGER_NONE
+	help
+	  Specify the type of triggering to be used by the driver.
+
+config WSEN_PADS_2511020213301_TRIGGER_NONE
+	bool "No trigger"
+
+config WSEN_PADS_2511020213301_TRIGGER_GLOBAL_THREAD
+	bool "Use global thread"
+	depends on GPIO
+	select WSEN_PADS_2511020213301_TRIGGER
+
+config WSEN_PADS_2511020213301_TRIGGER_OWN_THREAD
+	bool "Use own thread"
+	depends on GPIO
+	select WSEN_PADS_2511020213301_TRIGGER
+
+endchoice # WSEN_PADS_2511020213301_TRIGGER_MODE
+
+config WSEN_PADS_2511020213301_TRIGGER
+	bool
+
+config WSEN_PADS_2511020213301_THREAD_PRIORITY
+	int "Thread priority"
+	depends on WSEN_PADS_2511020213301_TRIGGER_OWN_THREAD
+	default 10
+	help
+	  Priority of thread used by the driver to handle interrupts.
+
+config WSEN_PADS_2511020213301_THREAD_STACK_SIZE
+	int "Thread stack size"
+	depends on WSEN_PADS_2511020213301_TRIGGER_OWN_THREAD
+	default 1024
+	help
+	  Stack size of thread used by the driver to handle interrupts.
+
+config WSEN_PADS_2511020213301_PRESSURE_THRESHOLD
+	bool "Pressure threshold triggers"
+	depends on WSEN_PADS_2511020213301_TRIGGER
+	help
+	  Allows you to set up triggers for high and/or low pressure thresholds.
+	  if activated then data ready trigger can't be set up.
+
+endif # WSEN_PADS_2511020213301
diff --git a/drivers/sensor/wsen/wsen_pads_2511020213301/wsen_pads_2511020213301.c b/drivers/sensor/wsen/wsen_pads_2511020213301/wsen_pads_2511020213301.c
new file mode 100644
index 00000000000..996773c04dd
--- /dev/null
+++ b/drivers/sensor/wsen/wsen_pads_2511020213301/wsen_pads_2511020213301.c
@@ -0,0 +1,525 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT we_wsen_pads_2511020213301
+
+#include <string.h>
+
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/logging/log.h>
+
+#include "wsen_pads_2511020213301.h"
+
+LOG_MODULE_REGISTER(WSEN_PADS_2511020213301, CONFIG_SENSOR_LOG_LEVEL);
+
+/*
+ * List of supported output data rates. Index into this list is used as
+ * argument for PADS_setOutputDataRate()
+ */
+static const int32_t pads_2511020213301_odr_list[] = {
+	0, 1, 10, 25, 50, 75, 100, 200,
+};
+
+#define SAMPLES_TO_DISCARD (uint8_t)2
+
+#define MAX_POLL_STEP_COUNT 10
+
+static int pads_2511020213301_sample_fetch(const struct device *dev, enum sensor_channel channel)
+{
+	struct pads_2511020213301_data *data = dev->data;
+	const struct pads_2511020213301_config *cfg = dev->config;
+
+	switch (channel) {
+	case SENSOR_CHAN_ALL:
+	case SENSOR_CHAN_AMBIENT_TEMP:
+	case SENSOR_CHAN_PRESS:
+		break;
+	default:
+		LOG_ERR("Fetching is not supported on channel %d.", channel);
+		return -ENOTSUP;
+	}
+
+	if (data->sensor_odr == PADS_outputDataRatePowerDown) {
+		if (PADS_enableOneShot(&data->sensor_interface, PADS_enable) != WE_SUCCESS) {
+			LOG_ERR("Failed to fetch %s sample.", "pressure");
+			return -EIO;
+		}
+
+		switch (cfg->configuration) {
+		case PADS_lowPower:
+			k_sleep(K_USEC(4700));
+			break;
+		case PADS_lowNoise:
+			k_sleep(K_USEC(13200));
+			break;
+		default:
+			LOG_ERR("Invalid sensor configuration");
+			return -EIO;
+		}
+
+		PADS_state_t one_shot_state;
+
+		do {
+			if (PADS_isOneShotEnabled(&data->sensor_interface, &one_shot_state) !=
+			    WE_SUCCESS) {
+				LOG_ERR("Failed to check for data ready");
+				return -EIO;
+			}
+		} while (PADS_enable == one_shot_state);
+	} else {
+
+		bool data_ready = false;
+		int step_count = 0;
+		uint32_t step_sleep_duration =
+			((uint32_t)1000000000 /
+			 (pads_2511020213301_odr_list[data->sensor_odr] * 1000)) /
+			MAX_POLL_STEP_COUNT;
+
+		while (1) {
+			PADS_state_t pressure_state, temp_state;
+
+			pressure_state = temp_state = PADS_disable;
+
+			if (PADS_isDataAvailable(&data->sensor_interface, &temp_state,
+						 &pressure_state) != WE_SUCCESS) {
+				LOG_ERR("Failed to check for data available");
+				return -EIO;
+			}
+
+			switch (channel) {
+			case SENSOR_CHAN_ALL:
+				data_ready = (pressure_state == PADS_enable &&
+					      temp_state == PADS_enable);
+				break;
+			case SENSOR_CHAN_AMBIENT_TEMP:
+				data_ready = (temp_state == PADS_enable);
+				break;
+			case SENSOR_CHAN_PRESS:
+				data_ready = (pressure_state == PADS_enable);
+				break;
+			default:
+				break;
+			}
+
+			if (data_ready) {
+				break;
+			} else if (step_count >= MAX_POLL_STEP_COUNT) {
+				return -EIO;
+			}
+
+			step_count++;
+			k_sleep(K_USEC(step_sleep_duration));
+		}
+	}
+
+	switch (channel) {
+	case SENSOR_CHAN_ALL: {
+
+		if (PADS_getPressure_int(&data->sensor_interface, &data->pressure) != WE_SUCCESS) {
+			LOG_ERR("Failed to fetch %s sample.", "pressure");
+			return -EIO;
+		}
+
+		if (PADS_getTemperature_int(&data->sensor_interface, &data->temperature) !=
+		    WE_SUCCESS) {
+			LOG_ERR("Failed to fetch %s sample.", "temperature");
+			return -EIO;
+		}
+
+		break;
+	}
+	case SENSOR_CHAN_AMBIENT_TEMP: {
+
+		if (PADS_getTemperature_int(&data->sensor_interface, &data->temperature) !=
+		    WE_SUCCESS) {
+			LOG_ERR("Failed to fetch %s sample.", "temperature");
+			return -EIO;
+		}
+
+		break;
+	}
+	case SENSOR_CHAN_PRESS: {
+
+		if (PADS_getPressure_int(&data->sensor_interface, &data->pressure) != WE_SUCCESS) {
+			LOG_ERR("Failed to fetch %s sample.", "pressure");
+			return -EIO;
+		}
+
+		break;
+	}
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int pads_2511020213301_channel_get(const struct device *dev, enum sensor_channel channel,
+					  struct sensor_value *value)
+{
+	struct pads_2511020213301_data *data = dev->data;
+
+	switch (channel) {
+	case SENSOR_CHAN_AMBIENT_TEMP:
+		/* Convert temperature from 0.01 degrees Celsius to degrees Celsius */
+		value->val1 = data->temperature / 100;
+		value->val2 = ((int32_t)data->temperature % 100) * (1000000 / 100);
+		break;
+	case SENSOR_CHAN_PRESS:
+		/* Convert pressure from Pa to kPa */
+		value->val1 = data->pressure / 1000;
+		value->val2 = ((int32_t)data->pressure % 1000) * (1000000 / 1000);
+		break;
+	default:
+		LOG_ERR("Channel not supported %d", channel);
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+/* Set output data rate. See pads_2511020213301_odr_list for allowed values. */
+static int pads_2511020213301_odr_set(const struct device *dev, const struct sensor_value *odr)
+{
+	struct pads_2511020213301_data *data = dev->data;
+	const struct pads_2511020213301_config *cfg = dev->config;
+	int odr_index;
+
+	for (odr_index = 0; odr_index < ARRAY_SIZE(pads_2511020213301_odr_list); odr_index++) {
+		if (odr->val1 == pads_2511020213301_odr_list[odr_index] && odr->val2 == 0) {
+			break;
+		}
+	}
+
+	if (odr_index == ARRAY_SIZE(pads_2511020213301_odr_list)) {
+		/* ODR not allowed (was not found in pads_2511020213301_odr_list) */
+		LOG_ERR("Bad sampling frequency %d.%d", odr->val1, odr->val2);
+		return -EINVAL;
+	}
+
+	if (cfg->configuration == PADS_lowNoise &&
+	    (PADS_outputDataRate_t)odr_index > PADS_outputDataRate75Hz) {
+		LOG_ERR("Failed to set ODR > 75Hz is not possible with low noise sensor "
+			"configuration.");
+		return -EIO;
+	}
+
+	if (PADS_setOutputDataRate(&data->sensor_interface, (PADS_outputDataRate_t)odr_index) !=
+	    WE_SUCCESS) {
+		LOG_ERR("Failed to set output data rate");
+		return -EIO;
+	}
+
+	if (PADS_enableBlockDataUpdate(&data->sensor_interface,
+				       (PADS_outputDataRate_t)odr_index !=
+						       PADS_outputDataRatePowerDown
+					       ? PADS_enable
+					       : PADS_disable) != WE_SUCCESS) {
+		LOG_ERR("Failed to enable block data update.");
+		return -EIO;
+	}
+
+	data->sensor_odr = (PADS_outputDataRate_t)odr_index;
+
+	return 0;
+}
+
+/* Get output data rate. */
+static int pads_2511020213301_odr_get(const struct device *dev, struct sensor_value *odr)
+{
+
+	struct pads_2511020213301_data *data = dev->data;
+
+	PADS_outputDataRate_t odr_index;
+
+	if (PADS_getOutputDataRate(&data->sensor_interface, &odr_index) != WE_SUCCESS) {
+		LOG_ERR("Failed to get output data rate");
+		return -EIO;
+	}
+
+	data->sensor_odr = odr_index;
+
+	odr->val1 = pads_2511020213301_odr_list[odr_index];
+	odr->val2 = 0;
+
+	return 0;
+}
+
+static int pads_2511020213301_attr_get(const struct device *dev, enum sensor_channel chan,
+				       enum sensor_attribute attr, struct sensor_value *val)
+{
+
+	if (val == NULL) {
+		LOG_WRN("address of passed value is NULL.");
+		return -EFAULT;
+	}
+
+	switch ((int)attr) {
+	case SENSOR_ATTR_SAMPLING_FREQUENCY:
+		if (chan != SENSOR_CHAN_ALL) {
+			LOG_ERR("attr_get() is not supported on channel %d.", chan);
+			return -ENOTSUP;
+		}
+		return pads_2511020213301_odr_get(dev, val);
+#ifdef CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD
+	case SENSOR_ATTR_WSEN_PADS_2511020213301_REFERENCE_POINT:
+		if (chan != SENSOR_CHAN_PRESS) {
+			LOG_ERR("attr_get() is not supported on channel %d.", chan);
+			return -ENOTSUP;
+		}
+		return pads_2511020213301_reference_point_get(dev, val);
+	case SENSOR_ATTR_UPPER_THRESH:
+	case SENSOR_ATTR_LOWER_THRESH:
+		if (chan != SENSOR_CHAN_PRESS) {
+			LOG_ERR("attr_get() is not supported on channel %d.", chan);
+			return -ENOTSUP;
+		}
+		return pads_2511020213301_threshold_get(dev, val);
+#endif
+	default:
+		LOG_ERR("Operation not supported.");
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static int pads_2511020213301_attr_set(const struct device *dev, enum sensor_channel chan,
+				       enum sensor_attribute attr, const struct sensor_value *val)
+{
+	switch ((int)attr) {
+	case SENSOR_ATTR_SAMPLING_FREQUENCY:
+		if (chan != SENSOR_CHAN_ALL) {
+			LOG_ERR("attr_set() is not supported on channel %d.", chan);
+			return -ENOTSUP;
+		}
+		return pads_2511020213301_odr_set(dev, val);
+#ifdef CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD
+	case SENSOR_ATTR_WSEN_PADS_2511020213301_REFERENCE_POINT:
+		if (chan != SENSOR_CHAN_PRESS) {
+			LOG_ERR("attr_set() is not supported on channel %d.", chan);
+			return -ENOTSUP;
+		}
+		return pads_2511020213301_reference_point_set(dev, val);
+	case SENSOR_ATTR_UPPER_THRESH:
+	case SENSOR_ATTR_LOWER_THRESH:
+		if (chan != SENSOR_CHAN_PRESS) {
+			LOG_ERR("attr_set() is not supported on channel %d.", chan);
+			return -ENOTSUP;
+		}
+		return pads_2511020213301_threshold_set(dev, val);
+#endif
+	default:
+		LOG_ERR("Operation not supported.");
+		return -ENOTSUP;
+	}
+}
+
+static DEVICE_API(sensor, pads_2511020213301_driver_api) = {
+	.attr_set = pads_2511020213301_attr_set,
+#if CONFIG_WSEN_PADS_2511020213301_TRIGGER
+	.trigger_set = pads_2511020213301_trigger_set,
+#endif
+	.attr_get = pads_2511020213301_attr_get,
+	.sample_fetch = pads_2511020213301_sample_fetch,
+	.channel_get = pads_2511020213301_channel_get,
+};
+
+static int pads_2511020213301_init(const struct device *dev)
+{
+	const struct pads_2511020213301_config *config = dev->config;
+	struct pads_2511020213301_data *data = dev->data;
+	struct sensor_value odr;
+	uint8_t device_id;
+
+	/* Initialize WE sensor interface */
+	WE_sensorInterfaceType_t interface_type = data->sensor_interface.interfaceType;
+
+	PADS_getDefaultInterface(&data->sensor_interface);
+	data->sensor_interface.interfaceType = interface_type;
+
+	switch (data->sensor_interface.interfaceType) {
+#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
+	case WE_i2c:
+		if (!i2c_is_ready_dt(&config->bus_cfg.i2c)) {
+			LOG_ERR("I2C bus device not ready");
+			return -ENODEV;
+		}
+		data->sensor_interface.handle = (void *)&config->bus_cfg.i2c;
+		break;
+#endif
+#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
+	case WE_spi:
+		if (!spi_is_ready_dt(&config->bus_cfg.spi)) {
+			LOG_ERR("SPI bus device not ready");
+			return -ENODEV;
+		}
+		data->sensor_interface.handle = (void *)&config->bus_cfg.spi;
+		break;
+#endif
+	default:
+		LOG_ERR("Invalid interface type");
+		return -EINVAL;
+	}
+
+	/* needed after power up */
+	k_sleep(K_USEC(4500));
+
+	PADS_state_t boot_state = PADS_enable;
+
+	do {
+		if (PADS_getBootStatus(&data->sensor_interface, &boot_state) != WE_SUCCESS) {
+			LOG_ERR("Failed to get sensor reset state.");
+			return -EIO;
+		}
+	} while (PADS_enable == boot_state);
+
+	/* First communication test - check device ID */
+	if (PADS_getDeviceID(&data->sensor_interface, &device_id) != WE_SUCCESS) {
+		LOG_ERR("Failed to read device ID.");
+		return -EIO;
+	}
+
+	if (device_id != PADS_DEVICE_ID_VALUE) {
+		LOG_ERR("Invalid device ID 0x%x.", device_id);
+		return -EINVAL;
+	}
+
+	/* Reset sensor */
+	PADS_softReset(&data->sensor_interface, PADS_enable);
+	k_sleep(K_USEC(50));
+
+	PADS_state_t sw_reset;
+
+	do {
+		if (PADS_getSoftResetState(&data->sensor_interface, &sw_reset) != WE_SUCCESS) {
+			LOG_ERR("Failed to get sensor reset state.");
+			return -EIO;
+		}
+	} while (PADS_enable == sw_reset);
+
+	if (PADS_setPowerMode(&data->sensor_interface, config->configuration) != WE_SUCCESS) {
+		LOG_ERR("Failed to set sensor configuration.");
+		return -EIO;
+	}
+
+	odr.val1 = pads_2511020213301_odr_list[config->odr];
+	odr.val2 = 0;
+
+	if (pads_2511020213301_odr_set(dev, &odr) < 0) {
+		LOG_ERR("Failed to set output data rate.");
+		return -EIO;
+	}
+
+	if (PADS_enableLowPassFilter(&data->sensor_interface, config->alpf) != WE_SUCCESS) {
+		LOG_ERR("Failed to set additional low pass filter.");
+		return -EIO;
+	}
+
+	if (config->alpf == PADS_enable) {
+		if (PADS_setLowPassFilterConfig(&data->sensor_interface,
+						config->alpf_configuration) != WE_SUCCESS) {
+			LOG_ERR("Failed to set additional low pass filter configuration.");
+			return -EIO;
+		}
+
+		for (uint8_t i = 0; i < SAMPLES_TO_DISCARD; i++) {
+			pads_2511020213301_sample_fetch(dev, SENSOR_CHAN_ALL);
+		}
+
+		data->pressure = 0;
+		data->temperature = 0;
+	}
+
+#if CONFIG_WSEN_PADS_2511020213301_TRIGGER
+	if (pads_2511020213301_init_interrupt(dev) < 0) {
+		LOG_ERR("Failed to initialize interrupt.");
+		return -EIO;
+	}
+#endif
+
+	return 0;
+}
+
+#if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 0
+#warning "PADS driver enabled without any devices"
+#endif
+
+#ifdef CONFIG_WSEN_PADS_2511020213301_TRIGGER
+#define PADS_2511020213301_CFG_IRQ(inst)                                                           \
+	.interrupt_gpio = GPIO_DT_SPEC_INST_GET(inst, interrupt_gpios)
+#else
+#define PADS_2511020213301_CFG_IRQ(inst)
+#endif /* CONFIG_WSEN_PADS_2511020213301_TRIGGER */
+
+#define PADS_2511020213301_CFG_ALPF(inst)                                                          \
+	.alpf = COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, additional_low_pass_filter),            \
+		(PADS_enable), (PADS_disable))
+
+#define PADS_2511020213301_CONFIG_COMMON(inst)                                                     \
+	.odr = (PADS_outputDataRate_t)(DT_INST_ENUM_IDX(inst, odr)),                               \
+	.configuration = (PADS_powerMode_t)(DT_INST_ENUM_IDX(inst, configuration)),                \
+	.alpf_configuration =                                                                      \
+		(PADS_filterConf_t)DT_INST_PROP(inst, additional_low_pass_filter_configuration),   \
+	PADS_2511020213301_CFG_ALPF(inst),                                                         \
+	IF_ENABLED(CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD, \
+	(.threshold = (uint16_t)DT_INST_PROP_OR(inst, threshold, 0),))                            \
+			    COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, interrupt_gpios),		\
+	(PADS_2511020213301_CFG_IRQ(inst)), ())
+
+/*
+ * Instantiation macros used when device is on SPI bus.
+ */
+
+#define PADS_2511020213301_SPI_OPERATION                                                           \
+	(SPI_WORD_SET(8) | SPI_OP_MODE_MASTER | SPI_MODE_CPOL | SPI_MODE_CPHA)
+
+#define PADS_2511020213301_CONFIG_SPI(inst)                                                        \
+	{.bus_cfg =                                                                                \
+		 {                                                                                 \
+			 .spi = SPI_DT_SPEC_INST_GET(inst, PADS_2511020213301_SPI_OPERATION, 0),   \
+		 },                                                                                \
+	 PADS_2511020213301_CONFIG_COMMON(inst)}
+
+/*
+ * Instantiation macros used when device is on I2C bus.
+ */
+
+#define PADS_2511020213301_CONFIG_I2C(inst)                                                        \
+	{.bus_cfg =                                                                                \
+		 {                                                                                 \
+			 .i2c = I2C_DT_SPEC_INST_GET(inst),                                        \
+		 },                                                                                \
+	 PADS_2511020213301_CONFIG_COMMON(inst)}
+
+#define PADS_2511020213301_CONFIG_WE_INTERFACE(inst)                                               \
+	{COND_CODE_1(DT_INST_ON_BUS(inst, i2c), \
+		(.sensor_interface = {.interfaceType = WE_i2c}), \
+		()) COND_CODE_1(DT_INST_ON_BUS(inst, spi),  \
+		(.sensor_interface = {.interfaceType = WE_spi}), \
+		()) }
+
+/*
+ * Main instantiation macro. Use of COND_CODE_1() selects the right
+ * bus-specific macro at preprocessor time.
+ */
+#define PADS_2511020213301_DEFINE(inst)                                                            \
+	static struct pads_2511020213301_data pads_2511020213301_data_##inst =                     \
+		PADS_2511020213301_CONFIG_WE_INTERFACE(inst);                                      \
+	static const struct pads_2511020213301_config pads_2511020213301_config_##inst =           \
+		COND_CODE_1(DT_INST_ON_BUS(inst, i2c),\
+		(PADS_2511020213301_CONFIG_I2C(inst)), \
+		())                                            \
+				COND_CODE_1(DT_INST_ON_BUS(inst, spi),  \
+		(PADS_2511020213301_CONFIG_SPI(inst)),\
+		());       \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, pads_2511020213301_init, NULL,                          \
+				     &pads_2511020213301_data_##inst,                              \
+				     &pads_2511020213301_config_##inst, POST_KERNEL,               \
+				     CONFIG_SENSOR_INIT_PRIORITY, &pads_2511020213301_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(PADS_2511020213301_DEFINE)
diff --git a/drivers/sensor/wsen/wsen_pads_2511020213301/wsen_pads_2511020213301.h b/drivers/sensor/wsen/wsen_pads_2511020213301/wsen_pads_2511020213301.h
new file mode 100644
index 00000000000..8fb335e6e68
--- /dev/null
+++ b/drivers/sensor/wsen/wsen_pads_2511020213301/wsen_pads_2511020213301.h
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_WSEN_PADS_2511020213301_WSEN_PADS_2511020213301_H_
+#define ZEPHYR_DRIVERS_SENSOR_WSEN_PADS_2511020213301_WSEN_PADS_2511020213301_H_
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/sensor.h>
+
+#include <weplatform.h>
+
+#include "WSEN_PADS_2511020213301_hal.h"
+#include <zephyr/drivers/sensor/wsen_pads_2511020213301.h>
+
+#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
+#include <zephyr/drivers/spi.h>
+#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(spi) */
+
+#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
+#include <zephyr/drivers/i2c.h>
+#endif /* DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c) */
+
+struct pads_2511020213301_data {
+	/* WE sensor interface configuration */
+	WE_sensorInterface_t sensor_interface;
+
+	/* Last pressure sample */
+	int32_t pressure;
+
+	/* Last temperature sample */
+	int16_t temperature;
+
+	PADS_outputDataRate_t sensor_odr;
+
+#ifdef CONFIG_WSEN_PADS_2511020213301_TRIGGER
+	const struct device *dev;
+
+	struct gpio_callback interrupt_cb;
+
+#ifdef CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD
+	sensor_trigger_handler_t pressure_high_trigger_handler;
+	sensor_trigger_handler_t pressure_low_trigger_handler;
+	const struct sensor_trigger *pressure_high_trigger;
+	const struct sensor_trigger *pressure_low_trigger;
+#else
+	sensor_trigger_handler_t data_ready_trigger_handler;
+	const struct sensor_trigger *data_ready_trigger;
+#endif /*  CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD */
+
+#if defined(CONFIG_WSEN_PADS_2511020213301_TRIGGER_OWN_THREAD)
+	K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_WSEN_PADS_2511020213301_THREAD_STACK_SIZE);
+	struct k_thread thread;
+	struct k_sem sem;
+#elif defined(CONFIG_WSEN_PADS_2511020213301_TRIGGER_GLOBAL_THREAD)
+	struct k_work work;
+#endif
+#endif /* CONFIG_WSEN_PADS_2511020213301_TRIGGER */
+};
+
+struct pads_2511020213301_config {
+	union {
+#if DT_ANY_INST_ON_BUS_STATUS_OKAY(i2c)
+		const struct i2c_dt_spec i2c;
+#endif
+#if DT_ANY_INST_ON_BUS_STATUS_OKAY(spi)
+		const struct spi_dt_spec spi;
+#endif
+	} bus_cfg;
+
+	/* Output data rate */
+	const PADS_outputDataRate_t odr;
+
+	const PADS_powerMode_t configuration;
+
+	const PADS_state_t alpf;
+
+	const PADS_filterConf_t alpf_configuration;
+#ifdef CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD
+	const uint16_t threshold;
+#endif /*  CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD */
+#ifdef CONFIG_WSEN_PADS_2511020213301_TRIGGER
+	/* Interrupt pin */
+	const struct gpio_dt_spec interrupt_gpio;
+#endif /* CONFIG_WSEN_PADS_2511020213301_TRIGGER */
+};
+
+#ifdef CONFIG_WSEN_PADS_2511020213301_TRIGGER
+int pads_2511020213301_trigger_set(const struct device *dev, const struct sensor_trigger *trig,
+				   sensor_trigger_handler_t handler);
+
+int pads_2511020213301_init_interrupt(const struct device *dev);
+
+#ifdef CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD
+int pads_2511020213301_threshold_set(const struct device *dev,
+				     const struct sensor_value *threshold);
+
+int pads_2511020213301_threshold_get(const struct device *dev, struct sensor_value *threshold);
+
+int pads_2511020213301_reference_point_set(const struct device *dev,
+					   const struct sensor_value *reference_point);
+
+int pads_2511020213301_reference_point_get(const struct device *dev,
+					   struct sensor_value *reference_point);
+
+#endif /* CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD */
+#endif /* CONFIG_WSEN_PADS_2511020213301_TRIGGER */
+
+int pads_2511020213301_spi_init(const struct device *dev);
+int pads_2511020213301_i2c_init(const struct device *dev);
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_WSEN_PADS_2511020213301_WSEN_PADS_2511020213301_H_ */
diff --git a/drivers/sensor/wsen/wsen_pads_2511020213301/wsen_pads_2511020213301_trigger.c b/drivers/sensor/wsen/wsen_pads_2511020213301/wsen_pads_2511020213301_trigger.c
new file mode 100644
index 00000000000..5850c14ae03
--- /dev/null
+++ b/drivers/sensor/wsen/wsen_pads_2511020213301/wsen_pads_2511020213301_trigger.c
@@ -0,0 +1,341 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT we_wsen_pads_2511020213301
+
+#include <zephyr/logging/log.h>
+
+#include "wsen_pads_2511020213301.h"
+
+LOG_MODULE_DECLARE(WSEN_PADS_2511020213301, CONFIG_SENSOR_LOG_LEVEL);
+
+/* Enable/disable data-ready interrupt handling */
+static inline int pads_2511020213301_setup_interrupt(const struct device *dev, bool enable)
+{
+	const struct pads_2511020213301_config *cfg = dev->config;
+	unsigned int flags = enable ? GPIO_INT_EDGE_TO_ACTIVE : GPIO_INT_DISABLE;
+
+	return gpio_pin_interrupt_configure_dt(&cfg->interrupt_gpio, flags);
+}
+
+/*
+ * Is called when an interrupt has occurred.
+ */
+static inline void pads_2511020213301_handle_interrupt(const struct device *dev)
+{
+	struct pads_2511020213301_data *data = dev->data;
+
+	/* Disable interrupt handling until the interrupt has been processed */
+	pads_2511020213301_setup_interrupt(dev, false);
+
+#if defined(CONFIG_WSEN_PADS_2511020213301_TRIGGER_OWN_THREAD)
+	k_sem_give(&data->sem);
+#elif defined(CONFIG_WSEN_PADS_2511020213301_TRIGGER_GLOBAL_THREAD)
+	k_work_submit(&data->work);
+#endif
+}
+
+/* Calls data-ready trigger handler (if any) */
+static void pads_2511020213301_process_interrupt(const struct device *dev)
+{
+	struct pads_2511020213301_data *data = dev->data;
+
+#ifdef CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD
+	if (data->pressure_low_trigger_handler != NULL ||
+	    data->pressure_high_trigger_handler != NULL) {
+		PADS_state_t pressure_high_state, pressure_low_state;
+
+		if (PADS_getHighPressureInterruptStatus(&data->sensor_interface,
+							&pressure_high_state) != WE_SUCCESS) {
+			LOG_ERR("Failed to read pressure high state");
+			return;
+		}
+
+		if (PADS_getLowPressureInterruptStatus(&data->sensor_interface,
+						       &pressure_low_state) != WE_SUCCESS) {
+			LOG_ERR("Failed to read pressure high state");
+			return;
+		}
+
+		if (data->pressure_high_trigger_handler != NULL &&
+		    pressure_high_state == PADS_enable) {
+			data->pressure_high_trigger_handler(dev, data->pressure_high_trigger);
+		} else if (data->pressure_low_trigger_handler != NULL &&
+			   pressure_low_state == PADS_enable) {
+			data->pressure_low_trigger_handler(dev, data->pressure_low_trigger);
+		}
+	}
+#else
+	if (data->data_ready_trigger_handler != NULL) {
+		data->data_ready_trigger_handler(dev, data->data_ready_trigger);
+	}
+#endif /* CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD */
+
+	pads_2511020213301_setup_interrupt(dev, true);
+}
+
+int pads_2511020213301_trigger_set(const struct device *dev, const struct sensor_trigger *trig,
+				   sensor_trigger_handler_t handler)
+{
+	struct pads_2511020213301_data *data = dev->data;
+	const struct pads_2511020213301_config *cfg = dev->config;
+
+	if (trig->chan != SENSOR_CHAN_PRESS) {
+		LOG_ERR("Unsupported sensor trigger");
+		return -ENOTSUP;
+	}
+
+	switch ((int)trig->type) {
+#ifdef CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD
+	case SENSOR_TRIG_WSEN_PADS_2511020213301_THRESHOLD_LOWER:
+	case SENSOR_TRIG_WSEN_PADS_2511020213301_THRESHOLD_UPPER: {
+		switch ((int)trig->type) {
+		case SENSOR_TRIG_WSEN_PADS_2511020213301_THRESHOLD_LOWER:
+			data->pressure_low_trigger_handler = handler;
+			data->pressure_low_trigger = trig;
+			break;
+		case SENSOR_TRIG_WSEN_PADS_2511020213301_THRESHOLD_UPPER:
+			data->pressure_high_trigger_handler = handler;
+			data->pressure_high_trigger = trig;
+			break;
+		default:
+			break;
+		}
+
+		if (PADS_setInterruptEventControl(&data->sensor_interface,
+						  PADS_pressureHighOrLow) != WE_SUCCESS) {
+			LOG_ERR("Failed to set interrupt event control to pressure high or low");
+			return -EIO;
+		}
+
+		if (PADS_enableDiffPressureInterrupt(&data->sensor_interface,
+						     (data->pressure_high_trigger_handler ||
+						      data->pressure_low_trigger_handler)
+							     ? PADS_enable
+							     : PADS_disable) != WE_SUCCESS) {
+			LOG_ERR("Failed to enable pressure diff interrupt.");
+			return -EIO;
+		}
+
+		if (PADS_enableLowPressureInterrupt(&data->sensor_interface,
+						    (data->pressure_low_trigger_handler == NULL)
+							    ? PADS_disable
+							    : PADS_enable) != WE_SUCCESS) {
+			LOG_ERR("Failed to enable low pressure interrupt.");
+			return -EIO;
+		}
+		if (PADS_enableHighPressureInterrupt(&data->sensor_interface,
+						     (data->pressure_high_trigger_handler == NULL)
+							     ? PADS_disable
+							     : PADS_enable) != WE_SUCCESS) {
+			LOG_ERR("Failed to enable high pressure interrupt.");
+			return -EIO;
+		}
+
+		pads_2511020213301_setup_interrupt(dev, data->pressure_high_trigger_handler ||
+								data->pressure_low_trigger_handler);
+		break;
+	}
+#else
+	case SENSOR_TRIG_DATA_READY: {
+		int32_t pressure_dummy;
+		/* Read pressure to retrigger interrupt */
+		if (PADS_getPressure_int(&data->sensor_interface, &pressure_dummy) != WE_SUCCESS) {
+			LOG_ERR("Failed to read sample");
+			return -EIO;
+		}
+
+		if (PADS_setInterruptEventControl(&data->sensor_interface, PADS_dataReady)) {
+			LOG_ERR("Failed to set interrupt event control to data ready");
+			return -EIO;
+		}
+
+		/* Enable data-ready interrupt */
+		if (PADS_enableDataReadyInterrupt(&data->sensor_interface,
+						  (handler == NULL) ? PADS_disable : PADS_enable) !=
+		    WE_SUCCESS) {
+			LOG_ERR("Failed to enable data-ready interrupt.");
+			return -EIO;
+		}
+
+		data->data_ready_trigger_handler = handler;
+		data->data_ready_trigger = trig;
+
+		pads_2511020213301_setup_interrupt(dev, data->data_ready_trigger_handler);
+
+		break;
+	}
+#endif /* CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD */
+	default:
+		LOG_ERR("Unsupported sensor trigger");
+		return -ENOTSUP;
+	}
+
+	if (gpio_pin_get_dt(&cfg->interrupt_gpio) > 0) {
+		pads_2511020213301_handle_interrupt(dev);
+	}
+
+	return 0;
+}
+
+static void pads_2511020213301_callback(const struct device *dev, struct gpio_callback *cb,
+					uint32_t pins)
+{
+	struct pads_2511020213301_data *data =
+		CONTAINER_OF(cb, struct pads_2511020213301_data, interrupt_cb);
+
+	ARG_UNUSED(pins);
+
+	pads_2511020213301_handle_interrupt(data->dev);
+}
+
+#ifdef CONFIG_WSEN_PADS_2511020213301_TRIGGER_OWN_THREAD
+static void pads_2511020213301_thread(void *p1, void *p2, void *p3)
+{
+	ARG_UNUSED(p2);
+	ARG_UNUSED(p3);
+
+	struct pads_2511020213301_data *data = p1;
+
+	while (true) {
+		k_sem_take(&data->sem, K_FOREVER);
+		pads_2511020213301_process_interrupt(data->dev);
+	}
+}
+#endif /* CONFIG_WSEN_PADS_2511020213301_TRIGGER_OWN_THREAD */
+
+#ifdef CONFIG_WSEN_PADS_2511020213301_TRIGGER_GLOBAL_THREAD
+static void pads_2511020213301_work_cb(struct k_work *work)
+{
+	struct pads_2511020213301_data *data =
+		CONTAINER_OF(work, struct pads_2511020213301_data, work);
+
+	pads_2511020213301_process_interrupt(data->dev);
+}
+#endif /* CONFIG_WSEN_PADS_2511020213301_TRIGGER_GLOBAL_THREAD */
+
+#ifdef CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD
+/* Set threshold for the differential pressure interrupt. */
+int pads_2511020213301_threshold_set(const struct device *dev, const struct sensor_value *threshold)
+{
+	struct pads_2511020213301_data *data = dev->data;
+
+	if (PADS_setPressureThreshold(&data->sensor_interface, (uint32_t)threshold->val1) !=
+	    WE_SUCCESS) {
+		LOG_ERR("Failed to set threshold");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/* Get threshold for the differential pressure interrupt. */
+int pads_2511020213301_threshold_get(const struct device *dev, struct sensor_value *threshold)
+{
+
+	struct pads_2511020213301_data *data = dev->data;
+
+	if (PADS_getPressureThreshold(&data->sensor_interface, (uint32_t *)&threshold->val1) !=
+	    WE_SUCCESS) {
+		LOG_ERR("Failed to get threshold");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/* Set reference point to current measured pressure state. */
+int pads_2511020213301_reference_point_set(const struct device *dev,
+					   const struct sensor_value *reference_point)
+{
+	struct pads_2511020213301_data *data = dev->data;
+
+	if (reference_point != NULL) {
+		LOG_ERR("Sensor value should be null");
+		return -EIO;
+	}
+
+	if (PADS_enableAutoRefp(&data->sensor_interface, PADS_enable) != WE_SUCCESS) {
+		LOG_ERR("Failed to set additional low pass filter");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+/* Get reference point from registers. */
+int pads_2511020213301_reference_point_get(const struct device *dev,
+					   struct sensor_value *reference_point)
+{
+
+	struct pads_2511020213301_data *data = dev->data;
+
+	if (PADS_getReferencePressure(&data->sensor_interface,
+				      (uint32_t *)&reference_point->val1) != WE_SUCCESS) {
+		LOG_ERR("Failed to get reference point");
+		return -EIO;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD */
+
+int pads_2511020213301_init_interrupt(const struct device *dev)
+{
+	struct pads_2511020213301_data *data = dev->data;
+	const struct pads_2511020213301_config *cfg = dev->config;
+
+	data->dev = dev;
+
+	if (cfg->interrupt_gpio.port == NULL) {
+		LOG_ERR("interrupt-gpio is not defined in the device tree.");
+		return -EINVAL;
+	}
+
+	if (!gpio_is_ready_dt(&cfg->interrupt_gpio)) {
+		LOG_ERR("Device %s is not ready", cfg->interrupt_gpio.port->name);
+		return -ENODEV;
+	}
+
+	if (gpio_pin_configure_dt(&cfg->interrupt_gpio, GPIO_INPUT) < 0) {
+		LOG_ERR("Failed to configure %s.%02u", cfg->interrupt_gpio.port->name,
+			cfg->interrupt_gpio.pin);
+		return -EIO;
+	}
+
+	gpio_init_callback(&data->interrupt_cb, pads_2511020213301_callback,
+			   BIT(cfg->interrupt_gpio.pin));
+
+	if (gpio_add_callback(cfg->interrupt_gpio.port, &data->interrupt_cb) < 0) {
+		LOG_ERR("Failed to set gpio callback.");
+		return -EIO;
+	}
+#ifdef CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD
+
+	struct sensor_value threshold;
+
+	threshold.val1 = cfg->threshold;
+	threshold.val2 = 0;
+	if (pads_2511020213301_threshold_set(dev, &threshold) < 0) {
+		LOG_ERR("Failed to set threshold.");
+		return -EIO;
+	}
+
+#endif /* CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD */
+
+#if defined(CONFIG_WSEN_PADS_2511020213301_TRIGGER_OWN_THREAD)
+	k_sem_init(&data->sem, 0, K_SEM_MAX_LIMIT);
+
+	k_thread_create(&data->thread, data->thread_stack,
+			CONFIG_WSEN_PADS_2511020213301_THREAD_STACK_SIZE, pads_2511020213301_thread,
+			data, NULL, NULL,
+			K_PRIO_COOP(CONFIG_WSEN_PADS_2511020213301_THREAD_PRIORITY), 0, K_NO_WAIT);
+#elif defined(CONFIG_WSEN_PADS_2511020213301_TRIGGER_GLOBAL_THREAD)
+	data->work.handler = pads_2511020213301_work_cb;
+#endif
+
+	return 0;
+}
diff --git a/drivers/sensor/wsen/wsen_pdus_25131308XXXXX/CMakeLists.txt b/drivers/sensor/wsen/wsen_pdus_25131308XXXXX/CMakeLists.txt
new file mode 100644
index 00000000000..d88e689e54e
--- /dev/null
+++ b/drivers/sensor/wsen/wsen_pdus_25131308XXXXX/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(wsen_pdus_25131308XXXXX.c)
diff --git a/drivers/sensor/wsen/wsen_pdus_25131308XXXXX/Kconfig b/drivers/sensor/wsen/wsen_pdus_25131308XXXXX/Kconfig
new file mode 100644
index 00000000000..3257c89aaeb
--- /dev/null
+++ b/drivers/sensor/wsen/wsen_pdus_25131308XXXXX/Kconfig
@@ -0,0 +1,11 @@
+# Copyright (c) 2024 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+config WSEN_PDUS_25131308XXXXX
+	bool "WSEN-PDUS-25131308XXXXX differential pressure sensor"
+	default y
+	depends on DT_HAS_WE_WSEN_PDUS_25131308XXXXX_ENABLED
+	select I2C
+	select HAS_WESENSORS
+	help
+	  Enable driver for the WSEN-PDUS-25131308XXXXX I2C-based differential pressure sensor.
diff --git a/drivers/sensor/wsen/wsen_pdus_25131308XXXXX/wsen_pdus_25131308XXXXX.c b/drivers/sensor/wsen/wsen_pdus_25131308XXXXX/wsen_pdus_25131308XXXXX.c
new file mode 100644
index 00000000000..9b85f401902
--- /dev/null
+++ b/drivers/sensor/wsen/wsen_pdus_25131308XXXXX/wsen_pdus_25131308XXXXX.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2024 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT we_wsen_pdus_25131308xxxxx
+
+#include <stdlib.h>
+
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/logging/log.h>
+
+#include "wsen_pdus_25131308XXXXX.h"
+
+LOG_MODULE_REGISTER(WSEN_PDUS_25131308XXXXX, CONFIG_SENSOR_LOG_LEVEL);
+
+static int pdus_25131308XXXXX_sample_fetch(const struct device *dev, enum sensor_channel chan)
+{
+	struct pdus_25131308XXXXX_data *data = dev->data;
+	uint16_t pressure_dummy;
+
+	switch (chan) {
+	case SENSOR_CHAN_ALL: {
+		if (PDUS_getRawPressureAndTemperature(&data->sensor_interface, &data->pressure,
+						      &data->temperature) != WE_SUCCESS) {
+			LOG_ERR("Failed to fetch data sample");
+			return -EIO;
+		}
+		break;
+	}
+	case SENSOR_CHAN_AMBIENT_TEMP: {
+		if (PDUS_getRawPressureAndTemperature(&data->sensor_interface, &pressure_dummy,
+						      &data->temperature) != WE_SUCCESS) {
+			LOG_ERR("Failed to fetch data sample");
+			return -EIO;
+		}
+		break;
+	}
+	case SENSOR_CHAN_PRESS: {
+		if (PDUS_getRawPressure(&data->sensor_interface, &data->pressure) != WE_SUCCESS) {
+			LOG_ERR("Failed to fetch data sample");
+			return -EIO;
+		}
+		break;
+	}
+	default:
+		LOG_ERR("Fetching is not supported on channel %d.", chan);
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static int pdus_25131308XXXXX_channel_get(const struct device *dev, enum sensor_channel chan,
+					  struct sensor_value *value)
+{
+	struct pdus_25131308XXXXX_data *data = dev->data;
+	const struct pdus_25131308XXXXX_config *config = dev->config;
+
+	switch (chan) {
+	case SENSOR_CHAN_AMBIENT_TEMP: {
+		int32_t temperature_mega = ((int32_t)(data->temperature - T_MIN_VAL_PDUS)) * 4272;
+
+		value->val1 = temperature_mega / 1000000;
+		value->val2 = temperature_mega % 1000000;
+		break;
+	}
+	case SENSOR_CHAN_PRESS: {
+		int32_t pressure_temp = ((int32_t)(data->pressure - P_MIN_VAL_PDUS));
+
+		/*
+		 * these values are conversion factors based on the sensor type defined in the user
+		 * manual of the respective sensor
+		 */
+		switch (config->sensor_type) {
+		case PDUS_pdus0:
+			value->val1 = ((pressure_temp * 763) - 10000000) / 100000000;
+			value->val2 = (((pressure_temp * 763) - 10000000) % 100000000) / 100;
+			break;
+		case PDUS_pdus1:
+			value->val1 = ((pressure_temp * 763) - 10000000) / 10000000;
+			value->val2 = (((pressure_temp * 763) - 10000000) % 10000000) / 10;
+			break;
+		case PDUS_pdus2:
+			value->val1 = ((pressure_temp * 763) - 10000000) / 1000000;
+			value->val2 = ((pressure_temp * 763) - 10000000) % 1000000;
+			break;
+		case PDUS_pdus3:
+			value->val1 = (pressure_temp * 3815) / 1000000;
+			value->val2 = (pressure_temp * 3815) % 1000000;
+			break;
+		case PDUS_pdus4:
+			value->val1 = ((pressure_temp * 4196) - 10000000) / 100000;
+			value->val2 =
+				((pressure_temp * 4196) - 10000000) % 100000 * (1000000 / 100000);
+			break;
+		case PDUS_pdus5:
+			value->val1 = (pressure_temp * 5722) / 100000;
+			value->val2 = (pressure_temp * 5722) % 100000 * (1000000 / 100000);
+			break;
+		default:
+			LOG_ERR("Sensor type doesn't exist");
+			return -ENOTSUP;
+		}
+		break;
+	}
+	default:
+		LOG_ERR("Channel not supported %d", chan);
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(sensor, pdus_25131308XXXXX_driver_api) = {
+	.sample_fetch = pdus_25131308XXXXX_sample_fetch,
+	.channel_get = pdus_25131308XXXXX_channel_get
+};
+
+static int pdus_25131308XXXXX_init(const struct device *dev)
+{
+	struct pdus_25131308XXXXX_data *data = dev->data;
+	const struct pdus_25131308XXXXX_config *config = dev->config;
+
+	/* Initialize WE sensor interface */
+	PDUS_getDefaultInterface(&data->sensor_interface);
+	data->sensor_interface.interfaceType = WE_i2c;
+
+	if (!i2c_is_ready_dt(&config->bus_cfg.i2c)) {
+		LOG_ERR("I2C bus device not ready");
+		return -ENODEV;
+	}
+
+	data->sensor_interface.handle = (void *)&config->bus_cfg.i2c;
+
+	return 0;
+}
+
+/*
+ * Main instantiation macro.
+ */
+#define PDUS_25131308XXXXX_DEFINE(inst)                                                            \
+	static struct pdus_25131308XXXXX_data pdus_25131308XXXXX_data_##inst;                      \
+	static const struct pdus_25131308XXXXX_config pdus_25131308XXXXX_config_##inst = {         \
+		.bus_cfg =                                                                         \
+			{                                                                          \
+				.i2c = I2C_DT_SPEC_INST_GET(inst),                                 \
+			},                                                                         \
+		.sensor_type = (PDUS_SensorType_t)DT_INST_ENUM_IDX(inst, sensor_type)};            \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, pdus_25131308XXXXX_init, NULL,                          \
+				     &pdus_25131308XXXXX_data_##inst,                              \
+				     &pdus_25131308XXXXX_config_##inst, POST_KERNEL,               \
+				     CONFIG_SENSOR_INIT_PRIORITY, &pdus_25131308XXXXX_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(PDUS_25131308XXXXX_DEFINE)
diff --git a/drivers/sensor/wsen/wsen_pdus_25131308XXXXX/wsen_pdus_25131308XXXXX.h b/drivers/sensor/wsen/wsen_pdus_25131308XXXXX/wsen_pdus_25131308XXXXX.h
new file mode 100644
index 00000000000..ee065f0b16d
--- /dev/null
+++ b/drivers/sensor/wsen/wsen_pdus_25131308XXXXX/wsen_pdus_25131308XXXXX.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2024 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_WSEN_PDUS_25131308XXXXX_WSEN_PDUS_25131308XXXXX_H_
+#define ZEPHYR_DRIVERS_SENSOR_WSEN_PDUS_25131308XXXXX_WSEN_PDUS_25131308XXXXX_H_
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/sensor.h>
+
+#include <weplatform.h>
+
+#include "WSEN_PDUS_25131308XXX01_hal.h"
+#include <zephyr/drivers/i2c.h>
+
+struct pdus_25131308XXXXX_data {
+	/* WE sensor interface configuration */
+	WE_sensorInterface_t sensor_interface;
+
+	/* Last pressure sample */
+	uint16_t pressure;
+
+	/* Last temperature sample */
+	uint16_t temperature;
+};
+
+struct pdus_25131308XXXXX_config {
+	union {
+		const struct i2c_dt_spec i2c;
+	} bus_cfg;
+
+	PDUS_SensorType_t sensor_type;
+};
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_WSEN_PDUS_25131308XXXXX_WSEN_PDUS_25131308XXXXX_H_ */
diff --git a/drivers/sensor/wsen/wsen_tids_2521020222501/CMakeLists.txt b/drivers/sensor/wsen/wsen_tids_2521020222501/CMakeLists.txt
new file mode 100644
index 00000000000..36488ae2846
--- /dev/null
+++ b/drivers/sensor/wsen/wsen_tids_2521020222501/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(wsen_tids_2521020222501.c)
+zephyr_library_sources_ifdef(CONFIG_WSEN_TIDS_2521020222501_TRIGGER    wsen_tids_2521020222501_trigger.c)
diff --git a/drivers/sensor/wsen/wsen_tids_2521020222501/Kconfig b/drivers/sensor/wsen/wsen_tids_2521020222501/Kconfig
new file mode 100644
index 00000000000..07b5b0db478
--- /dev/null
+++ b/drivers/sensor/wsen/wsen_tids_2521020222501/Kconfig
@@ -0,0 +1,53 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig WSEN_TIDS_2521020222501
+	bool "WSEN-TIDS-2521020222501 temperature sensor"
+	default y
+	depends on DT_HAS_WE_WSEN_TIDS_2521020222501_ENABLED
+	select I2C
+	select HAS_WESENSORS
+	help
+	  Enable driver for the WSEN-TIDS-2521020222501 I2C-based temperature sensor.
+
+if WSEN_TIDS_2521020222501
+
+choice WSEN_TIDS_2521020222501_TRIGGER_MODE
+	prompt "Trigger mode"
+	default WSEN_TIDS_2521020222501_TRIGGER_NONE
+	help
+	  Specify the type of triggering to be used by the driver.
+
+config WSEN_TIDS_2521020222501_TRIGGER_NONE
+	bool "No trigger"
+
+config WSEN_TIDS_2521020222501_TRIGGER_GLOBAL_THREAD
+	bool "Use global thread"
+	depends on GPIO
+	select WSEN_TIDS_2521020222501_TRIGGER
+
+config WSEN_TIDS_2521020222501_TRIGGER_OWN_THREAD
+	bool "Use own thread"
+	depends on GPIO
+	select WSEN_TIDS_2521020222501_TRIGGER
+
+endchoice # WSEN_TIDS_2521020222501_TRIGGER_MODE
+
+config WSEN_TIDS_2521020222501_TRIGGER
+	bool
+
+config WSEN_TIDS_2521020222501_THREAD_PRIORITY
+	int "Thread priority"
+	depends on WSEN_TIDS_2521020222501_TRIGGER_OWN_THREAD
+	default 10
+	help
+	  Priority of thread used by the driver to handle interrupts.
+
+config WSEN_TIDS_2521020222501_THREAD_STACK_SIZE
+	int "Thread stack size"
+	depends on WSEN_TIDS_2521020222501_TRIGGER_OWN_THREAD
+	default 1024
+	help
+	  Stack size of thread used by the driver to handle interrupts.
+
+endif # WSEN_TIDS_2521020222501
diff --git a/drivers/sensor/wsen/wsen_tids_2521020222501/wsen_tids_2521020222501.c b/drivers/sensor/wsen/wsen_tids_2521020222501/wsen_tids_2521020222501.c
new file mode 100644
index 00000000000..e014945bb1c
--- /dev/null
+++ b/drivers/sensor/wsen/wsen_tids_2521020222501/wsen_tids_2521020222501.c
@@ -0,0 +1,330 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT we_wsen_tids_2521020222501
+
+#include <stdlib.h>
+
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/logging/log.h>
+
+#include "wsen_tids_2521020222501.h"
+
+LOG_MODULE_REGISTER(WSEN_TIDS_2521020222501, CONFIG_SENSOR_LOG_LEVEL);
+
+static const struct sensor_value tids_2521020222501_odr_list[] = {{.val1 = 0, .val2 = 0},
+								  {.val1 = 25, .val2 = 0},
+								  {.val1 = 50, .val2 = 0},
+								  {.val1 = 100, .val2 = 0},
+								  {.val1 = 200, .val2 = 0}};
+
+static int tids_2521020222501_sample_fetch(const struct device *dev, enum sensor_channel chan)
+{
+	struct tids_2521020222501_data *data = dev->data;
+	int16_t raw_temperature;
+
+	switch (chan) {
+	case SENSOR_CHAN_ALL:
+	case SENSOR_CHAN_AMBIENT_TEMP:
+		break;
+	default:
+		LOG_ERR("Fetching is not supported on channel %d.", chan);
+		return -ENOTSUP;
+	}
+	if (data->sensor_odr == ((uint8_t)tids_2521020222501_odr_list[0].val1)) {
+
+		TIDS_softReset(&data->sensor_interface, TIDS_enable);
+
+		k_sleep(K_USEC(5));
+
+		TIDS_softReset(&data->sensor_interface, TIDS_disable);
+
+		if (TIDS_enableOneShot(&data->sensor_interface, TIDS_enable) != WE_SUCCESS) {
+			LOG_ERR("Failed to enable one shot");
+			return -EIO;
+		}
+
+		TIDS_state_t busy = TIDS_enable;
+
+		do {
+			if (TIDS_isBusy(&data->sensor_interface, &busy) != WE_SUCCESS) {
+				LOG_ERR("Failed to check for data ready");
+				return -EIO;
+			}
+		} while (TIDS_enable == busy);
+	}
+
+	if (TIDS_getRawTemperature(&data->sensor_interface, &raw_temperature) != WE_SUCCESS) {
+		LOG_ERR("Failed to fetch data sample");
+		return -EIO;
+	}
+
+	data->temperature = raw_temperature;
+
+	return 0;
+}
+
+static int tids_2521020222501_channel_get(const struct device *dev, enum sensor_channel chan,
+					  struct sensor_value *val)
+{
+	struct tids_2521020222501_data *data = dev->data;
+
+	switch (chan) {
+	case SENSOR_CHAN_AMBIENT_TEMP:
+		/* Convert temperature from 0.01 degrees Celsius to degrees Celsius */
+		val->val1 = data->temperature / 100;
+		val->val2 = ((int32_t)data->temperature % 100) * (1000000 / 100);
+		break;
+	default:
+		LOG_ERR("Channel not supported %d", chan);
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+/* Set output data rate. See tids_2521020222501_odr_list for allowed values. */
+static int tids_2521020222501_odr_set(const struct device *dev, const struct sensor_value *odr)
+{
+	struct tids_2521020222501_data *data = dev->data;
+
+	int odr_index;
+
+	for (odr_index = 0; odr_index < ARRAY_SIZE(tids_2521020222501_odr_list); odr_index++) {
+		if (odr->val1 == tids_2521020222501_odr_list[odr_index].val1 &&
+		    odr->val2 == tids_2521020222501_odr_list[odr_index].val2) {
+			break;
+		}
+	}
+
+	if (odr_index == ARRAY_SIZE(tids_2521020222501_odr_list)) {
+		/* ODR not allowed (was not found in tids_2521020222501_odr_list) */
+		LOG_ERR("Bad sampling frequency %d.%d", odr->val1, odr->val2);
+		return -EINVAL;
+	}
+
+	if (odr->val1 == tids_2521020222501_odr_list[0].val1) {
+		if (TIDS_enableBlockDataUpdate(&data->sensor_interface, TIDS_disable) !=
+		    WE_SUCCESS) {
+			LOG_ERR("Failed to enable block data update.");
+			return -EIO;
+		}
+
+		if (TIDS_enableContinuousMode(&data->sensor_interface, TIDS_disable) !=
+		    WE_SUCCESS) {
+			LOG_ERR("Failed to enable continuous mode.");
+			return -EIO;
+		}
+	} else {
+		if (TIDS_setOutputDataRate(&data->sensor_interface,
+					   (TIDS_outputDataRate_t)(odr->val1 - 1)) != WE_SUCCESS) {
+			LOG_ERR("Failed to set output data rate");
+			return -EIO;
+		}
+
+		if (TIDS_enableBlockDataUpdate(&data->sensor_interface, TIDS_enable) !=
+		    WE_SUCCESS) {
+			LOG_ERR("Failed to enable block data update.");
+			return -EIO;
+		}
+
+		if (TIDS_enableContinuousMode(&data->sensor_interface, TIDS_enable) != WE_SUCCESS) {
+			LOG_ERR("Failed to enable continuous mode.");
+			return -EIO;
+		}
+	}
+
+	data->sensor_odr = (uint8_t)odr->val1;
+
+	return 0;
+}
+
+/* Get output data rate. */
+static int tids_2521020222501_odr_get(const struct device *dev, struct sensor_value *odr)
+{
+
+	struct tids_2521020222501_data *data = dev->data;
+
+	TIDS_state_t continuous_mode_state;
+
+	if (TIDS_isContinuousModeEnabled(&data->sensor_interface, &continuous_mode_state) !=
+	    WE_SUCCESS) {
+		LOG_ERR("Failed to get continuous mode.");
+		return -EIO;
+	}
+
+	if (continuous_mode_state == TIDS_disable) {
+		odr->val1 = tids_2521020222501_odr_list[0].val1;
+	} else {
+		TIDS_outputDataRate_t odrIndex;
+
+		if (TIDS_getOutputDataRate(&data->sensor_interface, &odrIndex) != WE_SUCCESS) {
+			LOG_ERR("Failed to get output data rate");
+			return -EIO;
+		}
+
+		odr->val1 = tids_2521020222501_odr_list[odrIndex + 1].val1;
+	}
+
+	data->sensor_odr = (uint8_t)odr->val1;
+
+	odr->val2 = 0;
+
+	return 0;
+}
+
+static int tids_2521020222501_attr_set(const struct device *dev, enum sensor_channel chan,
+				       enum sensor_attribute attr, const struct sensor_value *val)
+{
+
+	switch (chan) {
+	case SENSOR_CHAN_ALL:
+	case SENSOR_CHAN_AMBIENT_TEMP:
+		break;
+	default:
+		LOG_ERR("attr_set() is not supported on channel %d.", chan);
+		return -ENOTSUP;
+	}
+
+	switch (attr) {
+	case SENSOR_ATTR_SAMPLING_FREQUENCY:
+		return tids_2521020222501_odr_set(dev, val);
+#ifdef CONFIG_WSEN_TIDS_2521020222501_TRIGGER
+	case SENSOR_ATTR_LOWER_THRESH:
+		return tids_2521020222501_threshold_lower_set(dev, val);
+	case SENSOR_ATTR_UPPER_THRESH:
+		return tids_2521020222501_threshold_upper_set(dev, val);
+#endif /* CONFIG_WSEN_TIDS_2521020222501_TRIGGER */
+
+	default:
+		LOG_ERR("Operation not supported.");
+		return -ENOTSUP;
+	}
+}
+
+static int tids_2521020222501_attr_get(const struct device *dev, enum sensor_channel chan,
+				       enum sensor_attribute attr, struct sensor_value *val)
+{
+
+	if (val == NULL) {
+		LOG_WRN("address of passed value is NULL.");
+		return -EFAULT;
+	}
+
+	switch (chan) {
+	case SENSOR_CHAN_ALL:
+	case SENSOR_CHAN_AMBIENT_TEMP:
+		break;
+	default:
+		LOG_ERR("attr_get() is not supported on channel %d.", chan);
+		return -ENOTSUP;
+	}
+
+	switch (attr) {
+	case SENSOR_ATTR_SAMPLING_FREQUENCY:
+		return tids_2521020222501_odr_get(dev, val);
+#ifdef CONFIG_WSEN_TIDS_2521020222501_TRIGGER
+	case SENSOR_ATTR_LOWER_THRESH:
+		return tids_2521020222501_threshold_lower_get(dev, val);
+	case SENSOR_ATTR_UPPER_THRESH:
+		return tids_2521020222501_threshold_upper_get(dev, val);
+#endif /* CONFIG_WSEN_TIDS_2521020222501_TRIGGER */
+	default:
+		LOG_ERR("Operation not supported.");
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(sensor, tids_2521020222501_driver_api) = {
+	.attr_set = tids_2521020222501_attr_set,
+#if CONFIG_WSEN_TIDS_2521020222501_TRIGGER
+	.trigger_set = tids_2521020222501_trigger_set,
+#endif
+	.attr_get = tids_2521020222501_attr_get,
+	.sample_fetch = tids_2521020222501_sample_fetch,
+	.channel_get = tids_2521020222501_channel_get,
+};
+
+static int tids_2521020222501_init(const struct device *dev)
+{
+	const struct tids_2521020222501_config *const config = dev->config;
+	struct tids_2521020222501_data *data = dev->data;
+	uint8_t device_id;
+
+	/* Initialize WE sensor interface */
+	TIDS_getDefaultInterface(&data->sensor_interface);
+	data->sensor_interface.interfaceType = WE_i2c;
+	if (!i2c_is_ready_dt(&config->bus_cfg.i2c)) {
+		LOG_ERR("I2C bus device not ready");
+		return -ENODEV;
+	}
+	data->sensor_interface.handle = (void *)&config->bus_cfg.i2c;
+
+	/* Needed after power up */
+	k_sleep(K_MSEC(12));
+
+	/* First communication test - check device ID */
+	if (TIDS_getDeviceID(&data->sensor_interface, &device_id) != WE_SUCCESS) {
+		LOG_ERR("Failed to read device ID.");
+		return -EIO;
+	}
+
+	if (device_id != TIDS_DEVICE_ID_VALUE) {
+		LOG_ERR("Invalid device ID 0x%x.", device_id);
+		return -EIO;
+	}
+
+	/* Reset the sensor with an arbitrary off time of 5 us */
+	TIDS_softReset(&data->sensor_interface, TIDS_enable);
+	k_sleep(K_USEC(5));
+	TIDS_softReset(&data->sensor_interface, TIDS_disable);
+
+	if (tids_2521020222501_odr_set(dev, &tids_2521020222501_odr_list[config->odr]) < 0) {
+		LOG_ERR("Failed to set output data rate.");
+		return -EIO;
+	}
+
+#ifdef CONFIG_WSEN_TIDS_2521020222501_TRIGGER
+	if (tids_2521020222501_init_interrupt(dev) < 0) {
+		LOG_ERR("Failed to initialize interrupt.");
+		return -EIO;
+	}
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_WSEN_TIDS_2521020222501_TRIGGER
+#define TIDS_2521020222501_CFG_IRQ(inst)                                                           \
+	.interrupt_gpio = GPIO_DT_SPEC_INST_GET(inst, interrupt_gpios),                            \
+	.high_threshold = DT_INST_PROP(inst, temp_high_threshold),                                 \
+	.low_threshold = DT_INST_PROP(inst, temp_low_threshold)
+#else
+#define TIDS_2521020222501_CFG_IRQ(inst)
+#endif /* CONFIG_WSEN_TIDS_2521020222501_TRIGGER */
+
+/*
+ * Main instantiation macro.
+ */
+#define TIDS_2521020222501_DEFINE(inst)                                                            \
+	static struct tids_2521020222501_data tids_2521020222501_data_##inst;                      \
+	static const struct tids_2521020222501_config tids_2521020222501_config_##inst = {         \
+		.bus_cfg =                                                                         \
+			{                                                                          \
+				.i2c = I2C_DT_SPEC_INST_GET(inst),                                 \
+			},                                                                         \
+		.odr = (uint8_t)(DT_INST_ENUM_IDX(inst, odr)),                                     \
+		COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, interrupt_gpios),                          \
+			    (TIDS_2521020222501_CFG_IRQ(inst)), ())};         \
+	SENSOR_DEVICE_DT_INST_DEFINE(inst, tids_2521020222501_init, NULL,                          \
+				     &tids_2521020222501_data_##inst,                              \
+				     &tids_2521020222501_config_##inst, POST_KERNEL,               \
+				     CONFIG_SENSOR_INIT_PRIORITY, &tids_2521020222501_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(TIDS_2521020222501_DEFINE)
diff --git a/drivers/sensor/wsen/wsen_tids_2521020222501/wsen_tids_2521020222501.h b/drivers/sensor/wsen/wsen_tids_2521020222501/wsen_tids_2521020222501.h
new file mode 100644
index 00000000000..46051ac5fc1
--- /dev/null
+++ b/drivers/sensor/wsen/wsen_tids_2521020222501/wsen_tids_2521020222501.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_WSEN_TIDS_2521020222501_WSEN_TIDS_2521020222501_H_
+#define ZEPHYR_DRIVERS_SENSOR_WSEN_TIDS_2521020222501_WSEN_TIDS_2521020222501_H_
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/sensor.h>
+
+#include <weplatform.h>
+
+#include "WSEN_TIDS_2521020222501_hal.h"
+#include <zephyr/drivers/sensor/wsen_tids_2521020222501.h>
+
+#include <zephyr/drivers/i2c.h>
+
+struct tids_2521020222501_data {
+	/* WE sensor interface configuration */
+	WE_sensorInterface_t sensor_interface;
+
+	/* Last temperature sample */
+	int16_t temperature;
+
+	uint8_t sensor_odr;
+
+#ifdef CONFIG_WSEN_TIDS_2521020222501_TRIGGER
+	const struct device *dev;
+
+	/* Callback for high/low limit interrupts */
+	struct gpio_callback interrupt_cb;
+
+	int32_t sensor_high_threshold;
+	int32_t sensor_low_threshold;
+
+	sensor_trigger_handler_t temperature_high_handler;
+	sensor_trigger_handler_t temperature_low_handler;
+
+	const struct sensor_trigger *temperature_high_trigger;
+	const struct sensor_trigger *temperature_low_trigger;
+
+#if defined(CONFIG_WSEN_TIDS_2521020222501_TRIGGER_OWN_THREAD)
+	K_KERNEL_STACK_MEMBER(thread_stack, CONFIG_WSEN_TIDS_2521020222501_THREAD_STACK_SIZE);
+	struct k_thread thread;
+	struct k_sem sem;
+#elif defined(CONFIG_WSEN_TIDS_2521020222501_TRIGGER_GLOBAL_THREAD)
+	struct k_work work;
+#endif
+#endif /* CONFIG_WSEN_TIDS_2521020222501_TRIGGER */
+};
+
+struct tids_2521020222501_config {
+	union {
+		const struct i2c_dt_spec i2c;
+	} bus_cfg;
+
+	/* Output data rate */
+	const uint8_t odr;
+
+#ifdef CONFIG_WSEN_TIDS_2521020222501_TRIGGER
+	/* Interrupt pin used for high and low limit interrupt events */
+	const struct gpio_dt_spec interrupt_gpio;
+
+	/* High temperature interrupt threshold */
+	const int32_t high_threshold;
+
+	/* Low temperature interrupt threshold */
+	const int32_t low_threshold;
+#endif
+};
+
+#ifdef CONFIG_WSEN_TIDS_2521020222501_TRIGGER
+int tids_2521020222501_trigger_set(const struct device *dev, const struct sensor_trigger *trig,
+				   sensor_trigger_handler_t handler);
+
+int tids_2521020222501_threshold_upper_set(const struct device *dev,
+					   const struct sensor_value *thresh_value);
+
+int tids_2521020222501_threshold_upper_get(const struct device *dev,
+					   struct sensor_value *thresh_value);
+
+int tids_2521020222501_threshold_lower_set(const struct device *dev,
+					   const struct sensor_value *thresh_value);
+
+int tids_2521020222501_threshold_lower_get(const struct device *dev,
+					   struct sensor_value *thresh_value);
+
+int tids_2521020222501_init_interrupt(const struct device *dev);
+#endif
+
+int tids_2521020222501_i2c_init(const struct device *dev);
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_WSEN_TIDS_2521020222501_WSEN_TIDS_2521020222501_H_ */
diff --git a/drivers/sensor/wsen/wsen_tids_2521020222501/wsen_tids_2521020222501_trigger.c b/drivers/sensor/wsen/wsen_tids_2521020222501/wsen_tids_2521020222501_trigger.c
new file mode 100644
index 00000000000..62fd442829d
--- /dev/null
+++ b/drivers/sensor/wsen/wsen_tids_2521020222501/wsen_tids_2521020222501_trigger.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT we_wsen_tids_2521020222501
+
+#include <stdlib.h>
+
+#include <zephyr/logging/log.h>
+
+#include "wsen_tids_2521020222501.h"
+
+LOG_MODULE_DECLARE(WSEN_TIDS_2521020222501, CONFIG_SENSOR_LOG_LEVEL);
+
+/* Enable/disable interrupt handling */
+static inline void tids_2521020222501_setup_interrupt(const struct device *dev, bool enable)
+{
+	const struct tids_2521020222501_config *cfg = dev->config;
+	unsigned int flags = enable ? GPIO_INT_EDGE_TO_ACTIVE : GPIO_INT_DISABLE;
+
+	gpio_pin_interrupt_configure_dt(&cfg->interrupt_gpio, flags);
+}
+
+/*
+ * Is called when an interrupt has occurred.
+ */
+static void tids_2521020222501_handle_interrupt(const struct device *dev)
+{
+	struct tids_2521020222501_data *data = dev->data;
+
+	/* Disable interrupt handling until the interrupt has been processed */
+	tids_2521020222501_setup_interrupt(dev, false);
+
+#if defined(CONFIG_WSEN_TIDS_2521020222501_TRIGGER_OWN_THREAD)
+	k_sem_give(&data->sem);
+#elif defined(CONFIG_WSEN_TIDS_2521020222501_TRIGGER_GLOBAL_THREAD)
+	k_work_submit(&data->work);
+#endif
+}
+
+/*
+ * Calls trigger handles.
+ */
+static void tids_2521020222501_process_interrupt(const struct device *dev)
+{
+	struct tids_2521020222501_data *data = dev->data;
+
+	if (data->temperature_high_handler != NULL || data->temperature_low_handler != NULL) {
+		/*
+		 * Read the sensor's status register - this also causes the interrupt pin
+		 * to be de-asserted
+		 */
+		TIDS_status_t status;
+
+		if (TIDS_getStatusRegister(&data->sensor_interface, &status) != WE_SUCCESS) {
+			LOG_ERR("Failed to read status register");
+			return;
+		}
+
+		if (data->temperature_high_handler != NULL &&
+		    status.upperLimitExceeded == TIDS_enable) {
+			data->temperature_high_handler(dev, data->temperature_high_trigger);
+		} else if (data->temperature_low_handler != NULL &&
+			   status.lowerLimitExceeded == TIDS_enable) {
+			data->temperature_low_handler(dev, data->temperature_low_trigger);
+		}
+	}
+
+	tids_2521020222501_setup_interrupt(dev, true);
+}
+
+/* Enables/disables processing of the "threshold exceeded" interrupt. */
+int tids_2521020222501_trigger_set(const struct device *dev, const struct sensor_trigger *trig,
+				   sensor_trigger_handler_t handler)
+{
+	struct tids_2521020222501_data *data = dev->data;
+	const struct tids_2521020222501_config *cfg = dev->config;
+
+	switch (trig->chan) {
+	case SENSOR_CHAN_ALL:
+	case SENSOR_CHAN_AMBIENT_TEMP:
+		break;
+	default:
+		LOG_ERR("Unsupported sensor trigger");
+		return -ENOTSUP;
+	}
+
+	struct sensor_value interruptOFF = {.val1 = -40, .val2 = -320000};
+	struct sensor_value threshold;
+
+	switch ((int)trig->type) {
+	case SENSOR_TRIG_WSEN_TIDS_2521020222501_THRESHOLD_LOWER: {
+
+		threshold.val1 = data->sensor_low_threshold / 1000;
+		threshold.val2 = ((int32_t)data->sensor_low_threshold % 1000) * (1000000 / 1000);
+
+		if (tids_2521020222501_threshold_lower_set(
+			    dev, (handler == NULL) ? &interruptOFF : &threshold) < 0) {
+			LOG_ERR("Failed to set low temp threshold");
+		}
+		data->temperature_low_handler = handler;
+		data->temperature_low_trigger = trig;
+		break;
+	}
+	case SENSOR_TRIG_WSEN_TIDS_2521020222501_THRESHOLD_UPPER: {
+
+		threshold.val1 = data->sensor_high_threshold / 1000;
+		threshold.val2 = ((int32_t)data->sensor_high_threshold % 1000) * (1000000 / 1000);
+
+		if (tids_2521020222501_threshold_upper_set(
+			    dev, (handler == NULL) ? &interruptOFF : &threshold) < 0) {
+			LOG_ERR("Failed to set high temp threshold");
+		}
+		data->temperature_high_handler = handler;
+		data->temperature_high_trigger = trig;
+		break;
+	}
+	default:
+		LOG_ERR("Unsupported sensor trigger");
+		return -ENOTSUP;
+	}
+
+	tids_2521020222501_setup_interrupt(dev, data->temperature_high_handler ||
+							data->temperature_low_handler);
+
+	if (gpio_pin_get_dt(&cfg->interrupt_gpio) > 0) {
+		tids_2521020222501_handle_interrupt(dev);
+	}
+
+	return 0;
+}
+
+static void tids_2521020222501_callback(const struct device *dev, struct gpio_callback *cb,
+					uint32_t pins)
+{
+	struct tids_2521020222501_data *data =
+		CONTAINER_OF(cb, struct tids_2521020222501_data, interrupt_cb);
+
+	ARG_UNUSED(pins);
+
+	tids_2521020222501_handle_interrupt(data->dev);
+}
+
+#ifdef CONFIG_WSEN_TIDS_2521020222501_TRIGGER_OWN_THREAD
+static void tids_2521020222501_thread(void *p1, void *p2, void *p3)
+{
+	ARG_UNUSED(p2);
+	ARG_UNUSED(p3);
+
+	struct tids_2521020222501_data *tids_2521020222501 = p1;
+
+	while (true) {
+		k_sem_take(&tids_2521020222501->sem, K_FOREVER);
+		tids_2521020222501_process_interrupt(tids_2521020222501->dev);
+	}
+}
+#endif /* CONFIG_WSEN_TIDS_2521020222501_TRIGGER_OWN_THREAD */
+
+#ifdef CONFIG_WSEN_TIDS_2521020222501_TRIGGER_GLOBAL_THREAD
+static void tids_2521020222501_work_cb(struct k_work *work)
+{
+	struct tids_2521020222501_data *tids_2521020222501 =
+		CONTAINER_OF(work, struct tids_2521020222501_data, work);
+
+	tids_2521020222501_process_interrupt(tids_2521020222501->dev);
+}
+#endif /* CONFIG_WSEN_TIDS_2521020222501_TRIGGER_GLOBAL_THREAD */
+
+int tids_2521020222501_threshold_upper_set(const struct device *dev,
+					   const struct sensor_value *thresh_value)
+{
+	struct tids_2521020222501_data *data = dev->data;
+	int32_t thresh = thresh_value->val1 * 1000 + thresh_value->val2 / 1000;
+
+	if (TIDS_setTempHighLimit(&data->sensor_interface, thresh) != WE_SUCCESS) {
+		LOG_ERR("Failed to set high temperature threshold.");
+		return -EIO;
+	}
+
+	data->sensor_high_threshold = thresh;
+
+	return 0;
+}
+
+int tids_2521020222501_threshold_upper_get(const struct device *dev,
+					   struct sensor_value *thresh_value)
+{
+	struct tids_2521020222501_data *data = dev->data;
+	int32_t thresh;
+
+	if (TIDS_getTempHighLimit(&data->sensor_interface, &thresh) != WE_SUCCESS) {
+		LOG_ERR("Failed to get high temperature threshold.");
+		return -EIO;
+	}
+
+	thresh_value->val1 = thresh / 1000;
+	thresh_value->val2 = (thresh % 1000) * (1000000 / 1000);
+
+	return 0;
+}
+
+int tids_2521020222501_threshold_lower_set(const struct device *dev,
+					   const struct sensor_value *thresh_value)
+{
+	struct tids_2521020222501_data *data = dev->data;
+	int32_t thresh = thresh_value->val1 * 1000 + thresh_value->val2 / 1000;
+
+	if (TIDS_setTempLowLimit(&data->sensor_interface, thresh) != WE_SUCCESS) {
+		LOG_ERR("Failed to set low temperature threshold.");
+		return -EIO;
+	}
+
+	data->sensor_low_threshold = thresh;
+
+	return 0;
+}
+
+int tids_2521020222501_threshold_lower_get(const struct device *dev,
+					   struct sensor_value *thresh_value)
+{
+	struct tids_2521020222501_data *data = dev->data;
+	int32_t thresh;
+
+	if (TIDS_getTempLowLimit(&data->sensor_interface, &thresh) != WE_SUCCESS) {
+		LOG_ERR("Failed to get low temperature threshold.");
+		return -EIO;
+	}
+
+	thresh_value->val1 = thresh / 1000;
+	thresh_value->val2 = (thresh % 1000) * (1000000 / 1000);
+
+	return 0;
+}
+
+int tids_2521020222501_init_interrupt(const struct device *dev)
+{
+	struct tids_2521020222501_data *data = dev->data;
+	const struct tids_2521020222501_config *cfg = dev->config;
+	struct sensor_value upper_limit, lower_limit;
+
+	if (cfg->interrupt_gpio.port == NULL) {
+		LOG_ERR("interrupt-gpios is not defined in the device tree.");
+		return -EINVAL;
+	}
+
+	if (!gpio_is_ready_dt(&cfg->interrupt_gpio)) {
+		LOG_ERR("Device %s is not ready", cfg->interrupt_gpio.port->name);
+		return -ENODEV;
+	}
+
+	data->dev = dev;
+
+	/* Setup threshold gpio interrupt */
+	if (gpio_pin_configure_dt(&cfg->interrupt_gpio, GPIO_INPUT) < 0) {
+		LOG_ERR("Failed to configure %s.%02u", cfg->interrupt_gpio.port->name,
+			cfg->interrupt_gpio.pin);
+		return -EIO;
+	}
+
+	gpio_init_callback(&data->interrupt_cb, tids_2521020222501_callback,
+			   BIT(cfg->interrupt_gpio.pin));
+
+	if (gpio_add_callback(cfg->interrupt_gpio.port, &data->interrupt_cb) < 0) {
+		LOG_ERR("Failed to set gpio callback.");
+		return -EIO;
+	}
+
+	/*
+	 * Enable interrupt on high/low temperature (interrupt generation is enabled if at
+	 * least one threshold is non-zero)
+	 */
+
+	upper_limit.val1 = cfg->high_threshold / 1000;
+	upper_limit.val2 = ((int32_t)cfg->high_threshold % 1000) * (1000000 / 1000);
+
+	lower_limit.val1 = cfg->low_threshold / 1000;
+	lower_limit.val2 = ((int32_t)cfg->low_threshold % 1000) * (1000000 / 1000);
+
+	if (tids_2521020222501_threshold_upper_set(dev, &upper_limit) < 0) {
+		LOG_ERR("Failed to set upper threshold");
+		return -EIO;
+	}
+
+	if (tids_2521020222501_threshold_lower_set(dev, &lower_limit) < 0) {
+		LOG_ERR("Failed to set lower threshold");
+		return -EIO;
+	}
+
+#if defined(CONFIG_WSEN_TIDS_2521020222501_TRIGGER_OWN_THREAD)
+	k_sem_init(&data->sem, 0, K_SEM_MAX_LIMIT);
+
+	k_thread_create(&data->thread, data->thread_stack,
+			CONFIG_WSEN_TIDS_2521020222501_THREAD_STACK_SIZE, tids_2521020222501_thread,
+			data, NULL, NULL,
+			K_PRIO_COOP(CONFIG_WSEN_TIDS_2521020222501_THREAD_PRIORITY), 0, K_NO_WAIT);
+#elif defined(CONFIG_WSEN_TIDS_2521020222501_TRIGGER_GLOBAL_THREAD)
+	data->work.handler = tids_2521020222501_work_cb;
+#endif
+
+	return 0;
+}
diff --git a/drivers/sensor/xbr818/xbr818.c b/drivers/sensor/xbr818/xbr818.c
index be396ec620e..1b426cbfefe 100644
--- a/drivers/sensor/xbr818/xbr818.c
+++ b/drivers/sensor/xbr818/xbr818.c
@@ -410,7 +410,7 @@ static int xbr818_init(const struct device *dev)
 	return ret;
 }
 
-static const struct sensor_driver_api xbr818_api = {
+static DEVICE_API(sensor, xbr818_api) = {
 	.sample_fetch = xbr818_sample_fetch,
 	.channel_get = xbr818_channel_get,
 	.attr_set = xbr818_attr_set,
diff --git a/drivers/serial/CMakeLists.txt b/drivers/serial/CMakeLists.txt
index c29700ac858..1a070d66c59 100644
--- a/drivers/serial/CMakeLists.txt
+++ b/drivers/serial/CMakeLists.txt
@@ -9,18 +9,22 @@ zephyr_library_sources_ifdef(CONFIG_SERIAL_TEST serial_test.c)
 zephyr_library_sources_ifdef(CONFIG_UART_ASYNC_RX_HELPER uart_async_rx.c)
 zephyr_library_sources_ifdef(CONFIG_UART_ASYNC_TO_INT_DRIVEN_API uart_async_to_irq.c)
 zephyr_library_sources_ifdef(CONFIG_UART_SHELL uart_shell.c)
+zephyr_library_sources_ifdef(CONFIG_USBD_CDC_ACM_CLASS ${ZEPHYR_BASE}/misc/empty_file.c)
 zephyr_library_sources_ifdef(CONFIG_USB_CDC_ACM ${ZEPHYR_BASE}/misc/empty_file.c)
 # zephyr-keep-sorted-stop
 
 # zephyr-keep-sorted-start
 zephyr_library_sources_ifdef(CONFIG_LEUART_GECKO leuart_gecko.c)
+zephyr_library_sources_ifdef(CONFIG_LPUART_ESP32 lpuart_esp32.c)
 zephyr_library_sources_ifdef(CONFIG_SERIAL_ESP32_USB serial_esp32_usb.c)
 zephyr_library_sources_ifdef(CONFIG_UART_ALTERA uart_altera.c)
 zephyr_library_sources_ifdef(CONFIG_UART_ALTERA_JTAG uart_altera_jtag.c)
 zephyr_library_sources_ifdef(CONFIG_UART_APBUART uart_apbuart.c)
 zephyr_library_sources_ifdef(CONFIG_UART_BCM2711_MU uart_bcm2711.c)
+zephyr_library_sources_ifdef(CONFIG_UART_BFLB uart_bflb.c)
 zephyr_library_sources_ifdef(CONFIG_UART_BT uart_bt.c)
 zephyr_library_sources_ifdef(CONFIG_UART_CC13XX_CC26XX uart_cc13xx_cc26xx.c)
+zephyr_library_sources_ifdef(CONFIG_UART_CC23X0 uart_cc23x0.c)
 zephyr_library_sources_ifdef(CONFIG_UART_CC32XX uart_cc32xx.c)
 zephyr_library_sources_ifdef(CONFIG_UART_CDNS uart_cdns.c)
 zephyr_library_sources_ifdef(CONFIG_UART_CMSDK_APB uart_cmsdk_apb.c)
@@ -33,10 +37,12 @@ zephyr_library_sources_ifdef(CONFIG_UART_HOSTLINK uart_hostlink.c)
 zephyr_library_sources_ifdef(CONFIG_UART_IMX uart_imx.c)
 zephyr_library_sources_ifdef(CONFIG_UART_INFINEON_CAT1 uart_ifx_cat1.c)
 zephyr_library_sources_ifdef(CONFIG_UART_INTEL_LW uart_intel_lw.c)
+zephyr_library_sources_ifdef(CONFIG_UART_ITE_IT51XXX uart_ite_it51xxx.c)
 zephyr_library_sources_ifdef(CONFIG_UART_ITE_IT8XXX2 uart_ite_it8xxx2.c)
 zephyr_library_sources_ifdef(CONFIG_UART_LITEX uart_litex.c)
 zephyr_library_sources_ifdef(CONFIG_UART_LPC11U6X uart_lpc11u6x.c)
 zephyr_library_sources_ifdef(CONFIG_UART_MAX32 uart_max32.c)
+zephyr_library_sources_ifdef(CONFIG_UART_MCHP_MEC5 uart_mchp_mec5.c)
 zephyr_library_sources_ifdef(CONFIG_UART_MCUX uart_mcux.c)
 zephyr_library_sources_ifdef(CONFIG_UART_MCUX_FLEXCOMM uart_mcux_flexcomm.c)
 zephyr_library_sources_ifdef(CONFIG_UART_MCUX_IUART uart_mcux_iuart.c)
@@ -58,7 +64,8 @@ zephyr_library_sources_ifdef(CONFIG_UART_PSOC6 uart_psoc6.c)
 zephyr_library_sources_ifdef(CONFIG_UART_QUICKLOGIC_USBSERIALPORT_S3B uart_ql_usbserialport_s3b.c)
 zephyr_library_sources_ifdef(CONFIG_UART_RA8_SCI_B uart_renesas_ra8_sci_b.c)
 zephyr_library_sources_ifdef(CONFIG_UART_RCAR uart_rcar.c)
-zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RA uart_renesas_ra.c)
+zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RZA2M_SCIF uart_renesas_rza2m_scif.c)
+zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RZ_SCI uart_renesas_rz_sci.c)
 zephyr_library_sources_ifdef(CONFIG_UART_RENESAS_RZ_SCIF uart_renesas_rz_scif.c)
 zephyr_library_sources_ifdef(CONFIG_UART_RPI_PICO_PIO uart_rpi_pico_pio.c)
 zephyr_library_sources_ifdef(CONFIG_UART_RTS5912 uart_realtek_rts5912.c)
@@ -71,6 +78,8 @@ zephyr_library_sources_ifdef(CONFIG_UART_SCI_RA uart_renesas_ra_sci.c)
 zephyr_library_sources_ifdef(CONFIG_UART_SEDI uart_sedi.c)
 zephyr_library_sources_ifdef(CONFIG_UART_SI32_USART uart_si32_usart.c)
 zephyr_library_sources_ifdef(CONFIG_UART_SIFIVE uart_sifive.c)
+zephyr_library_sources_ifdef(CONFIG_UART_SILABS_EUSART uart_silabs_eusart.c)
+zephyr_library_sources_ifdef(CONFIG_UART_SILABS_USART uart_silabs_usart.c)
 zephyr_library_sources_ifdef(CONFIG_UART_SMARTBOND uart_smartbond.c)
 zephyr_library_sources_ifdef(CONFIG_UART_STELLARIS uart_stellaris.c)
 zephyr_library_sources_ifdef(CONFIG_UART_STM32 uart_stm32.c)
@@ -98,13 +107,13 @@ if (CONFIG_UART_NRFX_UARTE)
   endif()
 endif()
 
-if(CONFIG_UART_NATIVE_POSIX)
+if(CONFIG_UART_NATIVE_PTY)
   zephyr_library_compile_definitions(NO_POSIX_CHEATS)
-  zephyr_library_sources(uart_native_ptty.c)
+  zephyr_library_sources(uart_native_pty.c)
   if (CONFIG_NATIVE_APPLICATION)
-    zephyr_library_sources(uart_native_ptty_bottom.c)
+    zephyr_library_sources(uart_native_pty_bottom.c)
   else()
-    target_sources(native_simulator INTERFACE uart_native_ptty_bottom.c)
+    target_sources(native_simulator INTERFACE uart_native_pty_bottom.c)
   endif()
 endif()
 
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index baf3f7e4121..f1cb441dcb1 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -162,8 +162,10 @@ rsource "Kconfig.altera_jtag"
 rsource "Kconfig.apbuart"
 rsource "Kconfig.b91"
 rsource "Kconfig.bcm2711"
+rsource "Kconfig.bflb"
 rsource "Kconfig.bt"
 rsource "Kconfig.cc13xx_cc26xx"
+rsource "Kconfig.cc23x0"
 rsource "Kconfig.cc32xx"
 rsource "Kconfig.cdns"
 rsource "Kconfig.cmsdk_apb"
@@ -177,6 +179,7 @@ rsource "Kconfig.hostlink"
 rsource "Kconfig.ifx_cat1"
 rsource "Kconfig.imx"
 rsource "Kconfig.intel_lw"
+rsource "Kconfig.it51xxx"
 rsource "Kconfig.it8xxx2"
 rsource "Kconfig.leuart_gecko"
 rsource "Kconfig.litex"
@@ -187,9 +190,10 @@ rsource "Kconfig.mcux_flexcomm"
 rsource "Kconfig.mcux_iuart"
 rsource "Kconfig.mcux_lpsci"
 rsource "Kconfig.mcux_lpuart"
+rsource "Kconfig.mec5"
 rsource "Kconfig.miv"
 rsource "Kconfig.msp432p4xx"
-rsource "Kconfig.native_posix"
+rsource "Kconfig.native_pty"
 rsource "Kconfig.native_tty"
 rsource "Kconfig.neorv32"
 rsource "Kconfig.npcx"
@@ -203,6 +207,7 @@ rsource "Kconfig.pl011"
 rsource "Kconfig.psoc6"
 rsource "Kconfig.ql_usbserialport_s3b"
 rsource "Kconfig.rcar"
+rsource "Kconfig.realtek_rts5912"
 rsource "Kconfig.renesas_ra"
 rsource "Kconfig.renesas_ra8"
 rsource "Kconfig.renesas_rz"
@@ -212,7 +217,10 @@ rsource "Kconfig.rv32m1_lpuart"
 rsource "Kconfig.rzt2m"
 rsource "Kconfig.sam0"
 rsource "Kconfig.sedi"
+rsource "Kconfig.si32"
 rsource "Kconfig.sifive"
+rsource "Kconfig.silabs_eusart"
+rsource "Kconfig.silabs_usart"
 rsource "Kconfig.smartbond"
 rsource "Kconfig.stellaris"
 rsource "Kconfig.stm32"
@@ -220,16 +228,11 @@ rsource "Kconfig.sy1xx"
 rsource "Kconfig.test"
 rsource "Kconfig.uart_sam"
 rsource "Kconfig.usart_sam"
+rsource "Kconfig.wch_usart"
 rsource "Kconfig.xec"
 rsource "Kconfig.xen"
 rsource "Kconfig.xlnx"
 rsource "Kconfig.xmc4xxx"
 # zephyr-keep-sorted-stop
 
-source "drivers/serial/Kconfig.si32"
-
-source "drivers/serial/Kconfig.wch_usart"
-
-source "drivers/serial/Kconfig.realtek_rts5912"
-
 endif # SERIAL
diff --git a/drivers/serial/Kconfig.bflb b/drivers/serial/Kconfig.bflb
new file mode 100644
index 00000000000..52df95d521f
--- /dev/null
+++ b/drivers/serial/Kconfig.bflb
@@ -0,0 +1,12 @@
+# Copyright (c) 2021-2025 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config UART_BFLB
+	bool "Bouffalo Lab serial driver"
+	depends on DT_HAS_BFLB_UART_ENABLED
+	select PINCTRL
+	select SERIAL_HAS_DRIVER
+	select USE_BFLB_UART
+	help
+	  This option enables the UART driver for Bouffalo Lab SoC family.
diff --git a/drivers/serial/Kconfig.cc23x0 b/drivers/serial/Kconfig.cc23x0
new file mode 100644
index 00000000000..e285ee14671
--- /dev/null
+++ b/drivers/serial/Kconfig.cc23x0
@@ -0,0 +1,14 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+# Copyright (c) 2024 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config UART_CC23X0
+	bool "TI SimpleLink CC23x0 UART driver"
+	default y
+	depends on DT_HAS_TI_CC23X0_UART_ENABLED
+	select SERIAL_HAS_DRIVER
+	select SERIAL_SUPPORT_INTERRUPT
+	select PINCTRL
+	help
+	  Enable the TI SimpleLink CC23x0 UART driver.
diff --git a/drivers/serial/Kconfig.cmsdk_apb b/drivers/serial/Kconfig.cmsdk_apb
index 141e8c12902..57650e5d9ca 100644
--- a/drivers/serial/Kconfig.cmsdk_apb
+++ b/drivers/serial/Kconfig.cmsdk_apb
@@ -9,5 +9,6 @@ config UART_CMSDK_APB
 	depends on DT_HAS_ARM_CMSDK_UART_ENABLED
 	select SERIAL_HAS_DRIVER
 	select SERIAL_SUPPORT_INTERRUPT
+	select PINCTRL
 	help
 	  This option enables the UART driver for ARM CMSDK APB UART.
diff --git a/drivers/serial/Kconfig.esp32 b/drivers/serial/Kconfig.esp32
index 83dcc3f8780..e4ea9b5d6ee 100644
--- a/drivers/serial/Kconfig.esp32
+++ b/drivers/serial/Kconfig.esp32
@@ -43,3 +43,11 @@ config UART_ESP32_RX_FIFO_THRESH
 	range 1 127
 	help
 	  Configure the RX FIFO threshold for ESP32 UART driver.
+
+config LPUART_ESP32
+	bool "ESP32 LP UART driver"
+	default y
+	depends on DT_HAS_ESPRESSIF_ESP32_LPUART_ENABLED
+	select SERIAL_HAS_DRIVER
+	help
+	  Enable the ESP32 LP UART.
diff --git a/drivers/serial/Kconfig.gecko b/drivers/serial/Kconfig.gecko
index 6160845a363..8bc311cd523 100644
--- a/drivers/serial/Kconfig.gecko
+++ b/drivers/serial/Kconfig.gecko
@@ -10,8 +10,6 @@ config UART_GECKO
 	select SERIAL_HAS_DRIVER
 	select SERIAL_SUPPORT_INTERRUPT
 	select SOC_GECKO_USART
-	select PINCTRL if (SOC_FAMILY_SILABS_S1 || SOC_FAMILY_SILABS_S2)
-	select CLOCK_CONTROL if SOC_FAMILY_SILABS_S2
-	select PM_DEVICE if PM && SOC_FAMILY_SILABS_S2
+	select PINCTRL if SOC_FAMILY_SILABS_S1
 	help
 	  Enable the Gecko uart driver.
diff --git a/drivers/serial/Kconfig.ifx_cat1 b/drivers/serial/Kconfig.ifx_cat1
index 0c32b1cda32..5ddfde91191 100644
--- a/drivers/serial/Kconfig.ifx_cat1
+++ b/drivers/serial/Kconfig.ifx_cat1
@@ -10,7 +10,9 @@ config UART_INFINEON_CAT1
 	depends on DT_HAS_INFINEON_CAT1_UART_ENABLED
 	select SERIAL_HAS_DRIVER
 	select SERIAL_SUPPORT_INTERRUPT
+	select SERIAL_SUPPORT_ASYNC
 	select USE_INFINEON_UART
 	select PINCTRL
+	select DMA if UART_ASYNC_API
 	help
 	  This option enables the UART driver for Infineon CAT1 family.
diff --git a/drivers/serial/Kconfig.it51xxx b/drivers/serial/Kconfig.it51xxx
new file mode 100644
index 00000000000..34647e84d26
--- /dev/null
+++ b/drivers/serial/Kconfig.it51xxx
@@ -0,0 +1,13 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config UART_ITE_IT51XXX
+	bool "ITE IT51XXX UART driver"
+	default y
+	select UART_NS16550_ITE_HIGH_SPEED_BAUDRATE
+	depends on DT_HAS_ITE_IT51XXX_UART_ENABLED
+	select PINCTRL
+	help
+	  IT51XXX uses shared ns16550.c driver. This wrapper primarily
+	  registers an interrupt to wake up the EC from doze or deep
+	  doze mode back to active state.
diff --git a/drivers/serial/Kconfig.max32 b/drivers/serial/Kconfig.max32
index 99b5c7b45ef..b2c86c2359e 100644
--- a/drivers/serial/Kconfig.max32
+++ b/drivers/serial/Kconfig.max32
@@ -10,7 +10,21 @@ config UART_MAX32
 	select SERIAL_HAS_DRIVER
 	select SERIAL_SUPPORT_INTERRUPT
 	select PINCTRL
+	select SERIAL_SUPPORT_ASYNC if DT_HAS_ADI_MAX32_DMA_ENABLED
+	select DMA if UART_ASYNC_API
 	help
 	  This option enables the UART driver for MAX32 family of
 	  processors.
 	  Say y if you wish to use serial port on MAX32 MCU.
+
+if UART_MAX32
+
+config UART_TX_CACHE_LEN
+	int "TX cache buffer size"
+	range 8 64
+	default 8
+	help
+	  Size of UART transmit buffer that is used when source buffer
+	  is not located in a DMA-able region.
+
+endif # UART_MAX32
diff --git a/drivers/serial/Kconfig.mec5 b/drivers/serial/Kconfig.mec5
new file mode 100644
index 00000000000..d02392a0623
--- /dev/null
+++ b/drivers/serial/Kconfig.mec5
@@ -0,0 +1,28 @@
+# Microchip MEC5 UART
+
+# Copyright (c) 2024 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config UART_MCHP_MEC5
+	bool "Microchip MEC5 family ns16550 compatible UART driver"
+	default y
+	depends on DT_HAS_MICROCHIP_MEC5_UART_ENABLED
+	select PINCTRL
+	select SERIAL_HAS_DRIVER
+	select SERIAL_SUPPORT_INTERRUPT
+	help
+	  This option enables the UART driver for Microchip MEC5
+	  family processors.
+
+if UART_MCHP_MEC5
+
+config UART_MCHP_MEC5_LINE_CTRL
+	bool "Serial Line Control for Apps"
+	depends on UART_LINE_CTRL
+	help
+	  This enables the API for apps to control the serial line,
+	  such as CTS and RTS.
+
+	  Says n if not sure.
+
+endif # UART_MCHP_MEC5
diff --git a/drivers/serial/Kconfig.native_posix b/drivers/serial/Kconfig.native_posix
deleted file mode 100644
index eaa13bb8065..00000000000
--- a/drivers/serial/Kconfig.native_posix
+++ /dev/null
@@ -1,74 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-config UART_NATIVE_POSIX
-	bool "UART driver for native_sim/posix"
-	default y
-	depends on DT_HAS_ZEPHYR_NATIVE_POSIX_UART_ENABLED
-	select SERIAL_HAS_DRIVER
-	help
-	  This enables a UART driver for the POSIX ARCH with up to 2 UARTs.
-	  For the first UART port, the driver can be configured
-	  to either connect to the terminal from which the executable was run, or into
-	  one dedicated pseudoterminal for that UART.
-
-if UART_NATIVE_POSIX
-
-choice NATIVE_UART_0
-	prompt "Native UART Port 0 connection"
-	default NATIVE_UART_0_ON_OWN_PTY
-
-config NATIVE_UART_0_ON_OWN_PTY
-	bool "Connect the UART to its own pseudo terminal"
-	help
-	  Connect this UART to its own pseudoterminal. This is the preferred
-	  option for users who want to use Zephyr's shell.
-	  Moreover this option does not conflict with any other native
-	  backend which may use the invoking shell standard input/output.
-
-config NATIVE_UART_0_ON_STDINOUT
-	bool "Connect the UART to the invoking shell stdin/stdout"
-	help
-	  Connect this UART to the stdin & stdout of the calling shell/terminal
-	  which invoked the native executable. This is good enough for
-	  automated testing, or when feeding from a file/pipe.
-	  Note that other, non UART messages, will also be printed to the
-	  terminal.
-	  It is strongly discouraged to try to use this option with the new
-	  shell interactively, as the default terminal configuration is NOT
-	  appropriate for interactive use.
-
-endchoice
-
-config UART_NATIVE_WAIT_PTS_READY_ENABLE
-	bool "Support waiting for pseudo terminal client readiness"
-	depends on NATIVE_UART_0_ON_OWN_PTY || UART_NATIVE_POSIX_PORT_1_ENABLE
-	help
-	  When this option is selected a new command line switch is provided:
-	  ``--wait_uart``
-	  When ``--wait_uart`` is used, writes to the UART will be held until a
-	  client has connected to the slave side of the pseudoterminal.
-	  Otherwise writes are sent irrespectively.
-
-config UART_NATIVE_POSIX_PORT_1_ENABLE
-	bool "Second UART port"
-	help
-	  Useful if you need to have another serial connection to host.
-	  This is used for example in PPP (Point-to-Point Protocol)
-	  implementation.
-
-config NATIVE_UART_AUTOATTACH_DEFAULT_CMD
-	string "Default command to attach the UART to a new terminal"
-	default "xterm -e screen %s &"
-	help
-	  If the native executable is called with the --attach_uart
-	  command line option, this will be the default command which will be
-	  run to attach a new terminal to the 1st UART.
-	  Note that this command must have one, and only one, '%s' as
-	  placeholder for the pseudoterminal device name (e.g. /dev/pts/35)
-	  This is only applicable if the UART_0 is configured to use its own
-	  PTY with NATIVE_UART_0_ON_OWN_PTY.
-	  The 2nd UART will not be affected by this option.
-	  If you are using GNOME, then you can use this command string
-	  'gnome-terminal -- screen %s'
-
-endif # UART_NATIVE_POSIX
diff --git a/drivers/serial/Kconfig.native_pty b/drivers/serial/Kconfig.native_pty
new file mode 100644
index 00000000000..5f98676d575
--- /dev/null
+++ b/drivers/serial/Kconfig.native_pty
@@ -0,0 +1,105 @@
+# Copyright (c) 2025, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config UART_NATIVE_PTY
+	bool "PTY based UART driver for native_sim"
+	default y
+	depends on (DT_HAS_ZEPHYR_NATIVE_PTY_UART_ENABLED || DT_HAS_ZEPHYR_NATIVE_POSIX_UART_ENABLED)
+	select SERIAL_HAS_DRIVER
+	help
+	  This enables a PTY based UART driver for the POSIX ARCH with up to 2 UARTs.
+	  For the first UART port, the driver can be configured
+	  to either connect to the terminal from which the executable was run, or into
+	  one dedicated pseudoterminal for that UART.
+
+config UART_NATIVE_POSIX
+	bool "UART driver for native_sim (deprecated)"
+	select SERIAL_HAS_DRIVER
+	select DEPRECATED
+	select UART_NATIVE_PTY
+	help
+	  Deprecated option, use UART_NATIVE_PTY instead
+
+if (UART_NATIVE_PTY || UART_NATIVE_POSIX)
+
+choice UART_NATIVE_PTY_0
+	prompt "Native PTY Port 0 connection"
+	default UART_NATIVE_PTY_0_ON_STDINOUT if NATIVE_UART_0_ON_STDINOUT
+	default UART_NATIVE_PTY_0_ON_OWN_PTY
+
+config UART_NATIVE_PTY_0_ON_OWN_PTY
+	bool "Connect the first PTY UART to its own pseudo terminal"
+	help
+	  Connect this UART to its own pseudoterminal. This is the preferred
+	  option for users who want to use Zephyr's shell.
+	  Moreover this option does not conflict with any other native
+	  backend which may use the invoking shell standard input/output.
+	  Note it can be overridden from command line
+
+config UART_NATIVE_PTY_0_ON_STDINOUT
+	bool "Connect the first PTY UART to the invoking shell stdin/stdout"
+	help
+	  Connect this UART to the stdin & stdout of the calling shell/terminal
+	  which invoked the native executable. This is good enough for
+	  automated testing, or when feeding from a file/pipe.
+	  Note that other, non UART messages, will also be printed to the
+	  terminal.
+	  It is strongly discouraged to try to use this option with the new
+	  shell interactively, as the default terminal configuration is NOT
+	  appropriate for interactive use.
+
+endchoice
+
+choice NATIVE_UART_0
+	prompt "Native UART Port 0 connection (deprecated)"
+	default NATIVE_UART_0_ON_OWN_PTY
+
+config NATIVE_UART_0_ON_OWN_PTY
+	bool "Connect the UART to its own pseudo terminal (deprecated)"
+	help
+	  Deprecated, use UART_NATIVE_PTY_0_ON_OWN_PTY instead.
+
+config NATIVE_UART_0_ON_STDINOUT
+	bool "Connect the UART to the invoking shell stdin/stdout (deprecated)"
+	select DEPRECATED
+	help
+	  Deprecated, use UART_NATIVE_PTY_0_ON_STDINOUT instead.
+
+endchoice
+
+config UART_NATIVE_WAIT_PTS_READY_ENABLE
+	bool "Support waiting for pseudo terminal client readiness (deprecated)"
+	select DEPRECATED
+	help
+	  This option is deprecated and does not do anything anymore. (The command line
+	  option --wait_uart is always available).
+
+config UART_NATIVE_POSIX_PORT_1_ENABLE
+	bool "Second UART port (deprecated)"
+	select DEPRECATED
+	help
+	  This option does not do anything anymore. Use DTS to instantiate as many
+	  "zephyr,native-pty-uart" compatible nodes as you want.
+
+config UART_NATIVE_PTY_AUTOATTACH_DEFAULT_CMD
+	string "Default command to attach a PTY UART to a new terminal"
+	default NATIVE_UART_AUTOATTACH_DEFAULT_CMD
+	help
+	  If the native executable is called with the --attach_uart
+	  command line option, this will be the default command which will be
+	  run to attach a new terminal to the 1st UART.
+	  Note that this command must have one, and only one, '%s' as
+	  placeholder for the pseudoterminal device name (e.g. /dev/pts/35)
+	  This is only applicable if the UART_0 is configured to use its own
+	  PTY with NATIVE_UART_0_ON_OWN_PTY.
+	  The 2nd UART will not be affected by this option.
+	  If you are using GNOME, then you can use this command string
+	  'gnome-terminal -- screen %s'
+
+config NATIVE_UART_AUTOATTACH_DEFAULT_CMD
+	string "Default command to attach the UART to a new terminal (deprecated)"
+	default "xterm -e screen %s &"
+	help
+	  Deprecated. Use UART_NATIVE_PTY_AUTOATTACH_DEFAULT_CMD instead
+
+endif # UART_NATIVE_PTY || UART_NATIVE_POSIX
diff --git a/drivers/serial/Kconfig.nrfx b/drivers/serial/Kconfig.nrfx
index b46991c6cff..278540ce382 100644
--- a/drivers/serial/Kconfig.nrfx
+++ b/drivers/serial/Kconfig.nrfx
@@ -35,6 +35,12 @@ config UART_NRFX_UARTE_LEGACY_SHIM
 	help
 	  Disabling this option is deprecated.
 
+config DEPRECATED_UART_NRFX_UARTE_LEGACY_SHIM
+	bool
+	default y if !UART_NRFX_UARTE_LEGACY_SHIM
+	depends on UART_NRFX_UARTE
+	select DEPRECATED
+
 config UART_NRFX_UARTE_ENHANCED_RX
 	bool "Enhanced RX handling"
 	depends on UART_ASYNC_API
diff --git a/drivers/serial/Kconfig.realtek_rts5912 b/drivers/serial/Kconfig.realtek_rts5912
index bafb518aa43..fd4c32c3c5f 100644
--- a/drivers/serial/Kconfig.realtek_rts5912
+++ b/drivers/serial/Kconfig.realtek_rts5912
@@ -5,6 +5,7 @@
 
 config UART_RTS5912
 	bool "UART driver for Realtek RTS5912 EC"
+	depends on SOC_SERIES_RTS5912
 	default y if DT_HAS_REALTEK_RTS5912_UART_ENABLED
 	select PINCTRL
 	select CLOCK_CONTROL
diff --git a/drivers/serial/Kconfig.renesas_ra b/drivers/serial/Kconfig.renesas_ra
index d79081bc506..20c399c0c66 100644
--- a/drivers/serial/Kconfig.renesas_ra
+++ b/drivers/serial/Kconfig.renesas_ra
@@ -2,16 +2,6 @@
 # Copyright (c) 2024 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-config UART_RENESAS_RA
-	bool "Renesas RA Series UART Driver"
-	default y
-	depends on DT_HAS_RENESAS_RA_UART_SCI_ENABLED
-	select SERIAL_HAS_DRIVER
-	select SERIAL_SUPPORT_INTERRUPT
-	select PINCTRL
-	help
-	  Enable Renesas RA series UART driver.
-
 config UART_SCI_RA
 	bool "Renesas RA SCI UART"
 	default y
diff --git a/drivers/serial/Kconfig.renesas_rz b/drivers/serial/Kconfig.renesas_rz
index 712529a7b20..dfbd9f13437 100644
--- a/drivers/serial/Kconfig.renesas_rz
+++ b/drivers/serial/Kconfig.renesas_rz
@@ -1,4 +1,4 @@
-# Copyright (c) 2024 Renesas Electronics Corporation
+# Copyright (c) 2024-2025 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 config UART_RENESAS_RZ_SCIF
@@ -6,11 +6,23 @@ config UART_RENESAS_RZ_SCIF
 	default y
 	depends on DT_HAS_RENESAS_RZ_SCIF_UART_ENABLED
 	select SERIAL_HAS_DRIVER
+	select SERIAL_SUPPORT_INTERRUPT
 	select USE_RZ_FSP_SCIF_UART
 	select PINCTRL
 	help
 	  Enable Renesas RZ SCIF UART Driver.
 
+config UART_RENESAS_RZ_SCI
+	bool "Renesas RZ SCI UART"
+	default y
+	depends on DT_HAS_RENESAS_RZ_SCI_UART_ENABLED
+	select PINCTRL
+	select SERIAL_HAS_DRIVER
+	select SERIAL_SUPPORT_INTERRUPT
+	select USE_RZ_FSP_SCI_UART
+	help
+	  Enable Renesas RZ SCI UART Driver.
+
 if UART_RENESAS_RZ_SCIF
 
 config UART_RENESAS_RZG_INIT_DELAY_MS
@@ -21,3 +33,13 @@ config UART_RENESAS_RZG_INIT_DELAY_MS
 	  before UART initialization of M33.
 
 endif
+
+config UART_RENESAS_RZA2M_SCIF
+	bool "Renesas A2M SCIF UART Driver"
+	default y
+	depends on DT_HAS_RENESAS_RZA2M_SCIF_UART_ENABLED
+	select SERIAL_HAS_DRIVER
+	select SERIAL_SUPPORT_INTERRUPT
+	select PINCTRL
+	help
+	  Enable Renesas SCIF UART Driver.
diff --git a/drivers/serial/Kconfig.silabs_eusart b/drivers/serial/Kconfig.silabs_eusart
new file mode 100644
index 00000000000..e13d80d37ec
--- /dev/null
+++ b/drivers/serial/Kconfig.silabs_eusart
@@ -0,0 +1,30 @@
+# Copyright (c) 2024, Yishai Jaffe
+# Copyright (c) 2025, Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config UART_SILABS_EUSART
+	bool "Silabs EUSART UART driver"
+	default y
+	depends on DT_HAS_SILABS_EUSART_UART_ENABLED
+	select SERIAL_HAS_DRIVER
+	select SERIAL_SUPPORT_INTERRUPT
+	select SOC_GECKO_EUSART
+	select SERIAL_SUPPORT_ASYNC \
+		if DT_HAS_SILABS_LDMA_ENABLED
+	select DMA if UART_ASYNC_API
+	select PINCTRL
+	select CLOCK_CONTROL
+	help
+	  Enable the eusart uart driver.
+
+if UART_SILABS_EUSART
+
+config UART_SILABS_EUSART_ASYNC
+	bool
+	depends on DMA_SILABS_LDMA
+	depends on UART_ASYNC_API
+	default y
+	help
+	  If 'y', Silabs eusart driver will compile with support for UART async API.
+
+endif
diff --git a/drivers/serial/Kconfig.silabs_usart b/drivers/serial/Kconfig.silabs_usart
new file mode 100644
index 00000000000..a2088577d42
--- /dev/null
+++ b/drivers/serial/Kconfig.silabs_usart
@@ -0,0 +1,29 @@
+# Copyright (c) 2025, Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config UART_SILABS_USART
+	bool "Silabs USART UART driver"
+	default y
+	depends on DT_HAS_SILABS_USART_UART_ENABLED
+	select SERIAL_HAS_DRIVER
+	select SERIAL_SUPPORT_INTERRUPT
+	select SOC_GECKO_USART
+	select SERIAL_SUPPORT_ASYNC \
+		if DT_HAS_SILABS_LDMA_ENABLED
+	select DMA if UART_ASYNC_API
+	select PINCTRL
+	select CLOCK_CONTROL
+	help
+	  Enable the Silicon Labs usart driver.
+
+if UART_SILABS_USART
+
+config UART_SILABS_USART_ASYNC
+	bool
+	default y
+	depends on DMA_SILABS_LDMA
+	depends on UART_ASYNC_API
+	help
+	  If 'y', Silabs usart driver will compile with support for UART async API.
+
+endif
diff --git a/drivers/serial/Kconfig.sy1xx b/drivers/serial/Kconfig.sy1xx
index 2f345b63794..5d6de8234e8 100644
--- a/drivers/serial/Kconfig.sy1xx
+++ b/drivers/serial/Kconfig.sy1xx
@@ -6,5 +6,6 @@ config UART_SY1XX
 	default y
 	depends on DT_HAS_SENSRY_SY1XX_UART_ENABLED
 	select SERIAL_HAS_DRIVER
+	select PINCTRL
 	help
 	  Driver for Sensry Sy1xx series uart.
diff --git a/drivers/serial/lpuart_esp32.c b/drivers/serial/lpuart_esp32.c
new file mode 100644
index 00000000000..8e53a4f638b
--- /dev/null
+++ b/drivers/serial/lpuart_esp32.c
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT espressif_esp32_lpuart
+
+#include <zephyr/drivers/uart.h>
+#include <zephyr/dt-bindings/clock/esp32c6_clock.h>
+
+#include <hal/uart_hal.h>
+#if defined(CONFIG_SOC_ESP32C6_HPCORE)
+#include <hal/uart_ll.h>
+#include <hal/clk_tree_ll.h>
+#include <hal/clk_tree_hal.h>
+#include <hal/rtc_io_hal.h>
+#include <soc/uart_pins.h>
+#include <soc/rtc_io_periph.h>
+#include <esp_private/esp_clk_tree_common.h>
+#include <ulp_lp_core_uart.h>
+#endif
+
+#define ESP_LP_UART_TX_IDLE_NUM_DEFAULT (0U)
+
+struct lp_uart_esp32_data {
+	uart_hal_context_t hal;
+};
+
+struct lp_uart_esp32_config {
+	uint8_t tx_io_num;
+	uint8_t rx_io_num;
+	uint8_t rts_io_num;
+	uint8_t cts_io_num;
+	int baud_rate;
+	uint8_t data_bits;
+	uint8_t parity;
+	uint8_t stop_bits;
+	uint8_t flow_ctrl;
+	uint8_t rx_flow_ctrl_thresh;
+	uint8_t lp_uart_source_clk;
+};
+
+static int lp_uart_esp32_poll_in(const struct device *dev, unsigned char *p_char)
+{
+	struct lp_uart_esp32_data *data = dev->data;
+	int inout_rd_len = 1;
+
+	if (uart_hal_get_rxfifo_len(&data->hal) == 0) {
+		return -1;
+	}
+
+	uart_hal_read_rxfifo(&data->hal, p_char, &inout_rd_len);
+
+	return 0;
+}
+
+static void lp_uart_esp32_poll_out(const struct device *dev, unsigned char c)
+{
+	struct lp_uart_esp32_data *data = dev->data;
+	int tx_len = 0;
+
+	/* Wait for space in FIFO */
+	while (uart_hal_get_txfifo_len(&data->hal) == 0) {
+		; /* Wait */
+	}
+
+	uart_hal_write_txfifo(&data->hal, (const void *)&c, 1, &tx_len);
+}
+
+#if defined(CONFIG_SOC_ESP32C6_HPCORE)
+
+static int lp_uart_esp32_param_config(const struct device *dev)
+{
+	const struct lp_uart_esp32_config *const cfg = dev->config;
+	struct lp_uart_esp32_data *data = dev->data;
+	uint32_t sclk_freq = 0;
+
+	if ((cfg->rx_flow_ctrl_thresh > SOC_LP_UART_FIFO_LEN) ||
+	    (cfg->flow_ctrl > UART_CFG_FLOW_CTRL_RTS_CTS) ||
+	    (cfg->data_bits > UART_CFG_DATA_BITS_8)) {
+		return -EINVAL;
+	}
+
+	/* Get LP UART source clock frequency */
+	switch (clk_ll_rtc_fast_get_src()) {
+	case SOC_RTC_FAST_CLK_SRC_XTAL_DIV:
+#if CONFIG_SOC_SERIES_ESP32 || CONFIG_SOC_SERIES_ESP32S2 /* SOC_RTC_FAST_CLK_SRC_XTAL_D4 */
+		sclk_freq = clk_hal_xtal_get_freq_mhz() * MHZ(1) >> 2;
+#else /* SOC_RTC_FAST_CLK_SRC_XTAL_D2 */
+		sclk_freq = clk_hal_xtal_get_freq_mhz() * MHZ(1) >> 1;
+#endif
+		break;
+	case SOC_RTC_FAST_CLK_SRC_RC_FAST:
+		sclk_freq =
+			esp_clk_tree_rc_fast_get_freq_hz(ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED) /
+			clk_ll_rc_fast_get_divider();
+		break;
+#if SOC_CLK_LP_FAST_SUPPORT_LP_PLL
+	case SOC_RTC_FAST_CLK_SRC_LP_PLL:
+		sclk_freq = clk_ll_lp_pll_get_freq_mhz() * MHZ(1);
+		break;
+#endif
+	default:
+		return -EINVAL;
+	}
+
+	lp_uart_ll_enable_bus_clock(0, true);
+	lp_uart_ll_set_source_clk(data->hal.dev, cfg->lp_uart_source_clk);
+	lp_uart_ll_sclk_enable(0);
+
+	/* Initialize LP UART HAL with default parameters */
+	uart_hal_init(&data->hal, LP_UART_NUM_0);
+
+	/* Set protocol parameters from the configuration */
+	lp_uart_ll_set_baudrate(data->hal.dev, cfg->baud_rate, sclk_freq);
+	uart_hal_set_parity(&data->hal, cfg->parity);
+	uart_hal_set_data_bit_num(&data->hal, cfg->data_bits);
+	uart_hal_set_stop_bits(&data->hal, cfg->stop_bits);
+	uart_hal_set_tx_idle_num(&data->hal, ESP_LP_UART_TX_IDLE_NUM_DEFAULT);
+	uart_hal_set_hw_flow_ctrl(&data->hal, cfg->flow_ctrl, cfg->rx_flow_ctrl_thresh);
+
+	/* Reset Tx/Rx FIFOs */
+	uart_hal_rxfifo_rst(&data->hal);
+	uart_hal_txfifo_rst(&data->hal);
+
+	return 0;
+}
+
+static void lp_uart_esp32_config_io(int pin, int direction, int func)
+{
+	int rtc_io_num = rtc_io_num_map[pin];
+
+	rtcio_hal_function_select(rtc_io_num, RTCIO_FUNC_RTC);
+	rtcio_hal_set_direction(rtc_io_num, direction);
+	rtcio_hal_iomux_func_sel(rtc_io_num, func);
+}
+
+static void lp_uart_esp32_set_pin(const struct device *dev)
+{
+	const struct lp_uart_esp32_config *const cfg = dev->config;
+
+	/* Configure Tx Pin */
+	lp_uart_esp32_config_io(cfg->tx_io_num, RTC_GPIO_MODE_OUTPUT_ONLY, LP_U0TXD_MUX_FUNC);
+
+	/* Configure Rx Pin */
+	lp_uart_esp32_config_io(cfg->rx_io_num, RTC_GPIO_MODE_INPUT_ONLY, LP_U0RXD_GPIO_NUM);
+
+	/* Configure RTS Pin */
+	lp_uart_esp32_config_io(cfg->rts_io_num, RTC_GPIO_MODE_OUTPUT_ONLY, LP_U0RTS_MUX_FUNC);
+
+	/* Configure CTS Pin */
+	lp_uart_esp32_config_io(cfg->cts_io_num, RTC_GPIO_MODE_INPUT_ONLY, LP_U0CTS_MUX_FUNC);
+}
+
+static int lp_uart_esp32_init(const struct device *dev)
+{
+	int ret = 0;
+
+	ret = lp_uart_esp32_param_config(dev);
+	if (ret != 0) {
+		return -EINVAL;
+	}
+
+	/* Configure LP UART IO pins */
+	lp_uart_esp32_set_pin(dev);
+	return 0;
+}
+
+#endif /* CONFIG_SOC_ESP32C6_HPCORE */
+
+static DEVICE_API(uart, lp_uart_esp32_api) = {
+	.poll_in = lp_uart_esp32_poll_in,
+	.poll_out = lp_uart_esp32_poll_out,
+};
+
+static struct lp_uart_esp32_data lp_uart_esp32_data = {
+	.hal =	{
+			.dev = (uart_dev_t *)DT_REG_ADDR(DT_NODELABEL(lp_uart)),
+		},
+};
+
+static const struct lp_uart_esp32_config lp_uart_esp32_cfg = {
+	.tx_io_num = DT_PROP(DT_NODELABEL(lp_uart), tx_pin),
+	.rx_io_num = DT_PROP(DT_NODELABEL(lp_uart), rx_pin),
+	.rts_io_num = DT_PROP(DT_NODELABEL(lp_uart), rts_pin),
+	.cts_io_num = DT_PROP(DT_NODELABEL(lp_uart), cts_pin),
+	.baud_rate = DT_PROP(DT_NODELABEL(lp_uart), current_speed),
+	.data_bits = DT_PROP_OR(DT_NODELABEL(lp_uart), data_bits, UART_CFG_DATA_BITS_8),
+	.parity = DT_ENUM_IDX(DT_NODELABEL(lp_uart), parity),
+	.stop_bits = DT_PROP_OR(DT_NODELABEL(lp_uart), stop_bits, UART_CFG_STOP_BITS_1),
+	.flow_ctrl = DT_PROP_OR(DT_NODELABEL(lp_uart), flow_ctrl, UART_CFG_FLOW_CTRL_NONE),
+	.rx_flow_ctrl_thresh = 0,
+	.lp_uart_source_clk = LP_UART_SCLK_DEFAULT,
+};
+
+#if defined(CONFIG_SOC_ESP32C6_HPCORE)
+#define LP_UART_ESP32_INIT_FUNC lp_uart_esp32_init
+#else
+#define LP_UART_ESP32_INIT_FUNC NULL
+#endif
+
+DEVICE_DT_DEFINE(DT_NODELABEL(lp_uart), LP_UART_ESP32_INIT_FUNC, NULL, &lp_uart_esp32_data,
+		 &lp_uart_esp32_cfg, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, &lp_uart_esp32_api);
diff --git a/drivers/serial/serial_esp32_usb.c b/drivers/serial/serial_esp32_usb.c
index 79ea1a18a55..de278ee27ab 100644
--- a/drivers/serial/serial_esp32_usb.c
+++ b/drivers/serial/serial_esp32_usb.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2022 Libre Solar Technologies GmbH
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,21 +14,11 @@
 #include <errno.h>
 #include <soc.h>
 #include <zephyr/drivers/uart.h>
-#if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-#else
 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
-#endif
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/sys/util.h>
 #include <esp_attr.h>
 
-#if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
-#define ISR_HANDLER isr_handler_t
-#else
-#define ISR_HANDLER intr_handler_t
-#endif
-
 /*
  * Timeout after which the poll_out function stops waiting for space in the tx fifo.
  *
@@ -113,7 +104,7 @@ static int serial_esp32_usb_init(const struct device *dev)
 	ret = esp_intr_alloc(config->irq_source,
 			ESP_PRIO_TO_FLAGS(config->irq_priority) |
 			ESP_INT_FLAGS_CHECK(config->irq_flags),
-			(ISR_HANDLER)serial_esp32_usb_isr,
+			(intr_handler_t)serial_esp32_usb_isr,
 			(void *)dev, NULL);
 #endif
 	return ret;
diff --git a/drivers/serial/uart_altera.c b/drivers/serial/uart_altera.c
index 9a5392c7b13..a9f469f3eea 100644
--- a/drivers/serial/uart_altera.c
+++ b/drivers/serial/uart_altera.c
@@ -960,12 +960,9 @@ static struct uart_altera_device_data uart_altera_dev_data_##n = {        \
 	.uart_cfg =                                                           \
 	{                                                                     \
 			.baudrate = DT_INST_PROP(n, current_speed),                   \
-			.parity = DT_INST_ENUM_IDX_OR(n, parity,                      \
-						 UART_CFG_PARITY_NONE),                           \
-			.stop_bits = DT_INST_ENUM_IDX_OR(n, stop_bits,                \
-						 UART_CFG_STOP_BITS_1),                           \
-			.data_bits = DT_INST_ENUM_IDX_OR(n, data_bits,                \
-						 UART_CFG_DATA_BITS_8),                           \
+			.parity = DT_INST_ENUM_IDX(n, parity),                        \
+			.stop_bits = DT_INST_ENUM_IDX(n, stop_bits),                  \
+			.data_bits = DT_INST_ENUM_IDX(n, data_bits),                  \
 			.flow_ctrl = DT_INST_PROP(n, hw_flow_control) ?               \
 				UART_CFG_FLOW_CTRL_RTS_CTS :                              \
 				UART_CFG_FLOW_CTRL_NONE,                                  \
diff --git a/drivers/serial/uart_bflb.c b/drivers/serial/uart_bflb.c
new file mode 100644
index 00000000000..504e0f82a5a
--- /dev/null
+++ b/drivers/serial/uart_bflb.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2021-2025 ATL Electronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT bflb_uart
+
+/**
+ * @brief UART driver for Bouffalo Lab MCU family.
+ */
+#include <zephyr/drivers/uart.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/pm/device.h>
+#include <soc.h>
+
+#include <bflb_pinctrl.h>
+#include <bflb_uart.h>
+#include <bflb_glb.h>
+
+#define UART_CTS_FLOWCONTROL_ENABLE (0)
+#define UART_RTS_FLOWCONTROL_ENABLE (0)
+#define UART_MSB_FIRST_ENABLE	    (0)
+#define UART_DEFAULT_RTO_TIMEOUT    (255)
+#define UART_CLOCK_DIV		    (0)
+
+struct blfb_config {
+	const struct pinctrl_dev_config *pinctrl_cfg;
+	uint32_t periph_id;
+	UART_CFG_Type uart_cfg;
+	UART_FifoCfg_Type fifo_cfg;
+};
+
+static int uart_blfb_init(const struct device *dev)
+{
+	const struct blfb_config *cfg = dev->config;
+
+	pinctrl_apply_state(cfg->pinctrl_cfg, PINCTRL_STATE_DEFAULT);
+
+	GLB_Set_UART_CLK(1, HBN_UART_CLK_160M, UART_CLOCK_DIV);
+
+	UART_IntMask(cfg->periph_id, UART_INT_ALL, 1);
+	UART_Disable(cfg->periph_id, UART_TXRX);
+
+	UART_Init(cfg->periph_id, (UART_CFG_Type *)&cfg->uart_cfg);
+	UART_TxFreeRun(cfg->periph_id, 1);
+	UART_SetRxTimeoutValue(cfg->periph_id, UART_DEFAULT_RTO_TIMEOUT);
+	UART_FifoConfig(cfg->periph_id, (UART_FifoCfg_Type *)&cfg->fifo_cfg);
+	UART_Enable(cfg->periph_id, UART_TXRX);
+
+	return 0;
+}
+
+static int uart_blfb_poll_in(const struct device *dev, unsigned char *c)
+{
+	const struct blfb_config *cfg = dev->config;
+
+	return UART_ReceiveData(cfg->periph_id, (uint8_t *)c, 1) ? 0 : -1;
+}
+
+static void uart_blfb_poll_out(const struct device *dev, unsigned char c)
+{
+	const struct blfb_config *cfg = dev->config;
+
+	while (UART_GetTxFifoCount(cfg->periph_id) == 0) {
+		;
+	}
+
+	(void)UART_SendData(cfg->periph_id, (uint8_t *)&c, 1);
+}
+
+#ifdef CONFIG_PM_DEVICE
+static int uart_blfb_pm_control(const struct device *dev,
+				enum pm_device_action action)
+{
+	const struct blfb_config *cfg = dev->config;
+
+	switch (action) {
+	case PM_DEVICE_ACTION_RESUME:
+		(void)pinctrl_apply_state(cfg->pinctrl_cfg, PINCTRL_STATE_DEFAULT);
+		UART_Enable(cfg->periph_id, UART_TXRX);
+		break;
+	case PM_DEVICE_ACTION_SUSPEND:
+		if (pinctrl_apply_state(cfg->pinctrl_cfg, PINCTRL_STATE_SLEEP)) {
+			return -ENOTSUP;
+		}
+		UART_Disable(cfg->periph_id, UART_TXRX);
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_PM_DEVICE */
+
+static DEVICE_API(uart, uart_blfb_driver_api) = {
+	.poll_in = uart_blfb_poll_in,
+	.poll_out = uart_blfb_poll_out,
+};
+
+#define BLFB_UART_INIT(n)							\
+	PINCTRL_DT_INST_DEFINE(n);						\
+	PM_DEVICE_DT_INST_DEFINE(n, uart_blfb_pm_control);			\
+	static const struct blfb_config blfb_uart##n##_config = {		\
+		.pinctrl_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),		\
+		.periph_id = DT_INST_PROP(n, peripheral_id),			\
+										\
+		.uart_cfg.baudRate = DT_INST_PROP(n, current_speed),		\
+		.uart_cfg.dataBits = UART_DATABITS_8,				\
+		.uart_cfg.stopBits = UART_STOPBITS_1,				\
+		.uart_cfg.parity = UART_PARITY_NONE,				\
+		.uart_cfg.uartClk = SOC_BOUFFALOLAB_BL_PLL160_FREQ_HZ,		\
+		.uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE,		\
+		.uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE,	\
+		.uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE,		\
+										\
+		.fifo_cfg.txFifoDmaThreshold = 1,				\
+		.fifo_cfg.rxFifoDmaThreshold = 1,				\
+		.fifo_cfg.txFifoDmaEnable = 0,					\
+		.fifo_cfg.rxFifoDmaEnable = 0,					\
+	};									\
+	DEVICE_DT_INST_DEFINE(n, &uart_blfb_init,				\
+			      PM_DEVICE_DT_INST_GET(n),				\
+			      NULL,						\
+			      &blfb_uart##n##_config, PRE_KERNEL_1,		\
+			      CONFIG_KERNEL_INIT_PRIORITY_DEVICE,		\
+			      &uart_blfb_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(BLFB_UART_INIT)
diff --git a/drivers/serial/uart_cc13xx_cc26xx.c b/drivers/serial/uart_cc13xx_cc26xx.c
index 969c8df5ec2..7d286a9ba5e 100644
--- a/drivers/serial/uart_cc13xx_cc26xx.c
+++ b/drivers/serial/uart_cc13xx_cc26xx.c
@@ -617,9 +617,9 @@ static DEVICE_API(uart, uart_cc13xx_cc26xx_driver_api) = {
 		uart_cc13xx_cc26xx_data_##n = {			     \
 		.uart_config = {				     \
 			.baudrate = DT_INST_PROP(n, current_speed),  \
-			.parity = UART_CFG_PARITY_NONE,		     \
-			.stop_bits = UART_CFG_STOP_BITS_1,	     \
-			.data_bits = UART_CFG_DATA_BITS_8,	     \
+			.parity = DT_INST_ENUM_IDX(n, parity),	     \
+			.stop_bits = DT_INST_ENUM_IDX(n, stop_bits), \
+			.data_bits = DT_INST_ENUM_IDX(n, data_bits), \
 			.flow_ctrl = UART_CFG_FLOW_CTRL_NONE,	     \
 		},						     \
 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
diff --git a/drivers/serial/uart_cc23x0.c b/drivers/serial/uart_cc23x0.c
new file mode 100644
index 00000000000..c26bb40e59f
--- /dev/null
+++ b/drivers/serial/uart_cc23x0.c
@@ -0,0 +1,405 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ti_cc23x0_uart
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/uart.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/irq.h>
+
+#include <errno.h>
+
+#include <driverlib/uart.h>
+#include <driverlib/clkctl.h>
+
+struct uart_cc23x0_config {
+	uint32_t reg;
+	uint32_t sys_clk_freq;
+	const struct pinctrl_dev_config *pcfg;
+};
+
+struct uart_cc23x0_data {
+	struct uart_config uart_config;
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	uart_irq_callback_user_data_t callback;
+	void *user_data;
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+};
+
+static int uart_cc23x0_poll_in(const struct device *dev, unsigned char *c)
+{
+	const struct uart_cc23x0_config *config = dev->config;
+
+	if (!UARTCharAvailable(config->reg)) {
+		return -1;
+	}
+
+	*c = UARTGetCharNonBlocking(config->reg);
+
+	return 0;
+}
+
+static void uart_cc23x0_poll_out(const struct device *dev, unsigned char c)
+{
+	const struct uart_cc23x0_config *config = dev->config;
+
+	UARTPutChar(config->reg, c);
+}
+
+static int uart_cc23x0_err_check(const struct device *dev)
+{
+	const struct uart_cc23x0_config *config = dev->config;
+	uint32_t flags = UARTGetRxError(config->reg);
+	int error = 0;
+
+	error |= (flags & UART_RXERROR_FRAMING) ? UART_ERROR_FRAMING : 0;
+	error |= (flags & UART_RXERROR_PARITY) ? UART_ERROR_PARITY : 0;
+	error |= (flags & UART_RXERROR_BREAK) ? UART_BREAK : 0;
+	error |= (flags & UART_RXERROR_OVERRUN) ? UART_ERROR_OVERRUN : 0;
+
+	UARTClearRxError(config->reg);
+
+	return error;
+}
+
+static int uart_cc23x0_configure(const struct device *dev, const struct uart_config *cfg)
+{
+	const struct uart_cc23x0_config *config = dev->config;
+	struct uart_cc23x0_data *data = dev->data;
+	uint32_t line_ctrl = 0;
+	bool flow_ctrl;
+
+	switch (cfg->parity) {
+	case UART_CFG_PARITY_NONE:
+		line_ctrl |= UART_CONFIG_PAR_NONE;
+		break;
+	case UART_CFG_PARITY_ODD:
+		line_ctrl |= UART_CONFIG_PAR_ODD;
+		break;
+	case UART_CFG_PARITY_EVEN:
+		line_ctrl |= UART_CONFIG_PAR_EVEN;
+		break;
+	case UART_CFG_PARITY_MARK:
+		line_ctrl |= UART_CONFIG_PAR_ONE;
+		break;
+	case UART_CFG_PARITY_SPACE:
+		line_ctrl |= UART_CONFIG_PAR_ZERO;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	switch (cfg->stop_bits) {
+	case UART_CFG_STOP_BITS_1:
+		line_ctrl |= UART_CONFIG_STOP_ONE;
+		break;
+	case UART_CFG_STOP_BITS_2:
+		line_ctrl |= UART_CONFIG_STOP_TWO;
+		break;
+	case UART_CFG_STOP_BITS_0_5:
+	case UART_CFG_STOP_BITS_1_5:
+		return -ENOTSUP;
+	default:
+		return -EINVAL;
+	}
+
+	switch (cfg->data_bits) {
+	case UART_CFG_DATA_BITS_5:
+		line_ctrl |= UART_CONFIG_WLEN_5;
+		break;
+	case UART_CFG_DATA_BITS_6:
+		line_ctrl |= UART_CONFIG_WLEN_6;
+		break;
+	case UART_CFG_DATA_BITS_7:
+		line_ctrl |= UART_CONFIG_WLEN_7;
+		break;
+	case UART_CFG_DATA_BITS_8:
+		line_ctrl |= UART_CONFIG_WLEN_8;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	switch (cfg->flow_ctrl) {
+	case UART_CFG_FLOW_CTRL_NONE:
+		flow_ctrl = false;
+		break;
+	case UART_CFG_FLOW_CTRL_RTS_CTS:
+		flow_ctrl = true;
+		break;
+	case UART_CFG_FLOW_CTRL_DTR_DSR:
+		return -ENOTSUP;
+	default:
+		return -EINVAL;
+	}
+
+	/* Disables UART before setting control registers */
+	UARTConfigSetExpClk(config->reg, config->sys_clk_freq, cfg->baudrate, line_ctrl);
+
+	if (flow_ctrl) {
+		UARTEnableCTS(config->reg);
+		UARTEnableRTS(config->reg);
+	} else {
+		UARTDisableCTS(config->reg);
+		UARTDisableRTS(config->reg);
+	}
+
+	/* Re-enable UART */
+	UARTEnable(config->reg);
+
+	/* Make use of the FIFO to reduce chances of data being lost */
+	UARTEnableFifo(config->reg);
+
+	data->uart_config = *cfg;
+
+	return 0;
+}
+
+#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
+static int uart_cc23x0_config_get(const struct device *dev, struct uart_config *cfg)
+{
+	const struct uart_cc23x0_data *data = dev->data;
+
+	*cfg = data->uart_config;
+	return 0;
+}
+#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
+
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+
+static int uart_cc23x0_fifo_fill(const struct device *dev, const uint8_t *buf, int len)
+{
+	const struct uart_cc23x0_config *config = dev->config;
+	int n = 0;
+
+	while (n < len) {
+		if (!UARTSpaceAvailable(config->reg)) {
+			break;
+		}
+		UARTPutCharNonBlocking(config->reg, buf[n]);
+		n++;
+	}
+
+	return n;
+}
+
+static int uart_cc23x0_fifo_read(const struct device *dev, uint8_t *buf, const int len)
+{
+	const struct uart_cc23x0_config *config = dev->config;
+	int c, n;
+
+	n = 0;
+	while (n < len) {
+		if (!UARTCharAvailable(config->reg)) {
+			break;
+		}
+		c = UARTGetCharNonBlocking(config->reg);
+		buf[n++] = c;
+	}
+
+	return n;
+}
+
+static void uart_cc23x0_irq_tx_enable(const struct device *dev)
+{
+	const struct uart_cc23x0_config *config = dev->config;
+
+	UARTEnableInt(config->reg, UART_INT_TX);
+}
+
+static void uart_cc23x0_irq_tx_disable(const struct device *dev)
+{
+	const struct uart_cc23x0_config *config = dev->config;
+
+	UARTDisableInt(config->reg, UART_INT_TX);
+}
+
+static int uart_cc23x0_irq_tx_ready(const struct device *dev)
+{
+	const struct uart_cc23x0_config *config = dev->config;
+
+	return UARTSpaceAvailable(config->reg) ? 1 : 0;
+}
+
+static void uart_cc23x0_irq_rx_enable(const struct device *dev)
+{
+	const struct uart_cc23x0_config *config = dev->config;
+
+	/* Trigger the ISR on both RX and Receive Timeout. This is to allow
+	 * the use of the hardware FIFOs for more efficient operation
+	 */
+	UARTEnableInt(config->reg, UART_INT_RX | UART_INT_RT);
+}
+
+static void uart_cc23x0_irq_rx_disable(const struct device *dev)
+{
+	const struct uart_cc23x0_config *config = dev->config;
+
+	UARTDisableInt(config->reg, UART_INT_RX | UART_INT_RT);
+}
+
+static int uart_cc23x0_irq_tx_complete(const struct device *dev)
+{
+	const struct uart_cc23x0_config *config = dev->config;
+
+	return UARTBusy(config->reg) ? 0 : 1;
+}
+
+static int uart_cc23x0_irq_rx_ready(const struct device *dev)
+{
+	const struct uart_cc23x0_config *config = dev->config;
+
+	return UARTCharAvailable(config->reg) ? 1 : 0;
+}
+
+static void uart_cc23x0_irq_err_enable(const struct device *dev)
+{
+	const struct uart_cc23x0_config *config = dev->config;
+
+	return UARTEnableInt(config->reg, UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE);
+}
+
+static void uart_cc23x0_irq_err_disable(const struct device *dev)
+{
+	const struct uart_cc23x0_config *config = dev->config;
+
+	return UARTDisableInt(config->reg, UART_INT_OE | UART_INT_BE | UART_INT_PE | UART_INT_FE);
+}
+
+static int uart_cc23x0_irq_is_pending(const struct device *dev)
+{
+	const struct uart_cc23x0_config *config = dev->config;
+
+	/* Read masked interrupt status */
+	uint32_t status = UARTIntStatus(config->reg, true);
+
+	return status ? 1 : 0;
+}
+
+static int uart_cc23x0_irq_update(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+	return 1;
+}
+
+static void uart_cc23x0_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
+					 void *user_data)
+{
+	struct uart_cc23x0_data *data = dev->data;
+
+	data->callback = cb;
+	data->user_data = user_data;
+}
+
+static void uart_cc23x0_isr(const struct device *dev)
+{
+	struct uart_cc23x0_data *data = dev->data;
+
+	if (data->callback) {
+		data->callback(dev, data->user_data);
+	}
+}
+
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+
+static DEVICE_API(uart, uart_cc23x0_driver_api) = {
+	.poll_in = uart_cc23x0_poll_in,
+	.poll_out = uart_cc23x0_poll_out,
+	.err_check = uart_cc23x0_err_check,
+#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
+	.configure = uart_cc23x0_configure,
+	.config_get = uart_cc23x0_config_get,
+#endif
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	.fifo_fill = uart_cc23x0_fifo_fill,
+	.fifo_read = uart_cc23x0_fifo_read,
+	.irq_tx_enable = uart_cc23x0_irq_tx_enable,
+	.irq_tx_disable = uart_cc23x0_irq_tx_disable,
+	.irq_tx_ready = uart_cc23x0_irq_tx_ready,
+	.irq_rx_enable = uart_cc23x0_irq_rx_enable,
+	.irq_rx_disable = uart_cc23x0_irq_rx_disable,
+	.irq_tx_complete = uart_cc23x0_irq_tx_complete,
+	.irq_rx_ready = uart_cc23x0_irq_rx_ready,
+	.irq_err_enable = uart_cc23x0_irq_err_enable,
+	.irq_err_disable = uart_cc23x0_irq_err_disable,
+	.irq_is_pending = uart_cc23x0_irq_is_pending,
+	.irq_update = uart_cc23x0_irq_update,
+	.irq_callback_set = uart_cc23x0_irq_callback_set,
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+};
+
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+#define UART_CC23X0_IRQ_CFG(n)                                                                     \
+	do {                                                                                       \
+		UARTClearInt(config->reg, UART_INT_RX);                                            \
+		UARTClearInt(config->reg, UART_INT_RT);                                            \
+                                                                                                   \
+		IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), uart_cc23x0_isr,            \
+			    DEVICE_DT_INST_GET(n), 0);                                             \
+		irq_enable(DT_INST_IRQN(n));                                                       \
+	} while (false)
+
+#define UART_CC23X0_INT_FIELDS .callback = NULL, .user_data = NULL,
+#else
+#define UART_CC23X0_IRQ_CFG(n)
+#define UART_CC23X0_INT_FIELDS
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+
+#define UART_CC23X0_DEVICE_DEFINE(n)                                                               \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, uart_cc23x0_init_##n, NULL, &uart_cc23x0_data_##n,                \
+			      &uart_cc23x0_config_##n, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY,  \
+			      &uart_cc23x0_driver_api)
+
+#define UART_CC23X0_INIT_FUNC(n)                                                                   \
+	static int uart_cc23x0_init_##n(const struct device *dev)                                  \
+	{                                                                                          \
+		const struct uart_cc23x0_config *config = dev->config;                             \
+		struct uart_cc23x0_data *data = dev->data;                                         \
+		int ret;                                                                           \
+                                                                                                   \
+		CLKCTLEnable(CLKCTL_BASE, CLKCTL_UART0);                                           \
+                                                                                                   \
+		ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);                    \
+		if (ret < 0) {                                                                     \
+			return ret;                                                                \
+		}                                                                                  \
+                                                                                                   \
+		/* Configure and enable UART */                                                    \
+		ret = uart_cc23x0_configure(dev, &data->uart_config);                              \
+                                                                                                   \
+		/* Enable interrupts */                                                            \
+		UART_CC23X0_IRQ_CFG(n);                                                            \
+                                                                                                   \
+		return ret;                                                                        \
+	}
+
+#define UART_CC23X0_INIT(n)                                                                        \
+	PINCTRL_DT_INST_DEFINE(n);                                                                 \
+	UART_CC23X0_INIT_FUNC(n);                                                                  \
+                                                                                                   \
+	static struct uart_cc23x0_config uart_cc23x0_config_##n = {                                \
+		.reg = DT_INST_REG_ADDR(n),                                                        \
+		.sys_clk_freq = DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency),               \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                         \
+		};                                                                                 \
+                                                                                                   \
+	static struct uart_cc23x0_data uart_cc23x0_data_##n = {                                    \
+		.uart_config =                                                                     \
+			{                                                                          \
+				.baudrate = DT_INST_PROP(n, current_speed),                        \
+				.parity = DT_INST_ENUM_IDX(n, parity),                             \
+				.stop_bits = DT_INST_ENUM_IDX(n, stop_bits),                       \
+				.data_bits = DT_INST_ENUM_IDX(n, data_bits),                       \
+				.flow_ctrl = DT_INST_PROP(n, hw_flow_control),                     \
+			},                                                                         \
+		UART_CC23X0_INT_FIELDS                                                             \
+		};                                                                                 \
+	UART_CC23X0_DEVICE_DEFINE(n);
+
+DT_INST_FOREACH_STATUS_OKAY(UART_CC23X0_INIT)
diff --git a/drivers/serial/uart_cmsdk_apb.c b/drivers/serial/uart_cmsdk_apb.c
index 04aa0d06949..3578209b355 100644
--- a/drivers/serial/uart_cmsdk_apb.c
+++ b/drivers/serial/uart_cmsdk_apb.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2021, Linaro Limited.
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,6 +16,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/arch/cpu.h>
 #include <zephyr/drivers/clock_control/arm_clock_control.h>
+#include <zephyr/drivers/pinctrl.h>
 #include <zephyr/sys/__assert.h>
 #include <zephyr/init.h>
 #include <zephyr/drivers/uart.h>
@@ -64,6 +66,7 @@ struct uart_cmsdk_apb {
 struct uart_cmsdk_apb_config {
 	volatile struct uart_cmsdk_apb *uart;
 	uint32_t sys_clk_freq;
+	const struct pinctrl_dev_config *pctrl;
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 	uart_irq_config_func_t irq_config_func;
 #endif
@@ -124,6 +127,14 @@ static void baudrate_set(const struct device *dev)
 static int uart_cmsdk_apb_init(const struct device *dev)
 {
 	const struct uart_cmsdk_apb_config * const dev_cfg = dev->config;
+	int ret = pinctrl_apply_state(dev_cfg->pctrl, PINCTRL_STATE_DEFAULT);
+
+	/* some pins are not available externally so,
+	 * ignore if there is no entry for them
+	 */
+	if (ret != -ENOENT) {
+		return ret;
+	}
 
 #ifdef CONFIG_CLOCK_CONTROL
 	/* Enable clock for subsystem */
@@ -401,9 +412,7 @@ static void uart_cmsdk_apb_irq_err_disable(const struct device *dev)
  */
 static int uart_cmsdk_apb_irq_is_pending(const struct device *dev)
 {
-	const struct uart_cmsdk_apb_config *dev_cfg = dev->config;
-
-	return (dev_cfg->uart->intstatus & (UART_RX_IN | UART_TX_IN));
+	return uart_cmsdk_apb_irq_rx_ready(dev) || uart_cmsdk_apb_irq_tx_ready(dev);
 }
 
 /**
@@ -480,10 +489,11 @@ static DEVICE_API(uart, uart_cmsdk_apb_driver_api) = {
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 static void uart_cmsdk_apb_irq_config_func_0(const struct device *dev);
 #endif
-
+PINCTRL_DT_INST_DEFINE(0);
 static const struct uart_cmsdk_apb_config uart_cmsdk_apb_dev_cfg_0 = {
 	.uart = (volatile struct uart_cmsdk_apb *)DT_INST_REG_ADDR(0),
 	.sys_clk_freq = DT_INST_PROP_BY_PHANDLE(0, clocks, clock_frequency),
+	.pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 	.irq_config_func = uart_cmsdk_apb_irq_config_func_0,
 #endif
@@ -545,10 +555,11 @@ static void uart_cmsdk_apb_irq_config_func_0(const struct device *dev)
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 static void uart_cmsdk_apb_irq_config_func_1(const struct device *dev);
 #endif
-
+PINCTRL_DT_INST_DEFINE(1);
 static const struct uart_cmsdk_apb_config uart_cmsdk_apb_dev_cfg_1 = {
 	.uart = (volatile struct uart_cmsdk_apb *)DT_INST_REG_ADDR(1),
 	.sys_clk_freq = DT_INST_PROP_BY_PHANDLE(1, clocks, clock_frequency),
+	.pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(1),
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 	.irq_config_func = uart_cmsdk_apb_irq_config_func_1,
 #endif
@@ -610,10 +621,11 @@ static void uart_cmsdk_apb_irq_config_func_1(const struct device *dev)
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 static void uart_cmsdk_apb_irq_config_func_2(const struct device *dev);
 #endif
-
+PINCTRL_DT_INST_DEFINE(2);
 static const struct uart_cmsdk_apb_config uart_cmsdk_apb_dev_cfg_2 = {
 	.uart = (volatile struct uart_cmsdk_apb *)DT_INST_REG_ADDR(2),
 	.sys_clk_freq = DT_INST_PROP_BY_PHANDLE(2, clocks, clock_frequency),
+	.pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(2),
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 	.irq_config_func = uart_cmsdk_apb_irq_config_func_2,
 #endif
@@ -675,10 +687,11 @@ static void uart_cmsdk_apb_irq_config_func_2(const struct device *dev)
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 static void uart_cmsdk_apb_irq_config_func_3(const struct device *dev);
 #endif
-
+PINCTRL_DT_INST_DEFINE(3);
 static const struct uart_cmsdk_apb_config uart_cmsdk_apb_dev_cfg_3 = {
 	.uart = (volatile struct uart_cmsdk_apb *)DT_INST_REG_ADDR(3),
 	.sys_clk_freq = DT_INST_PROP_BY_PHANDLE(3, clocks, clock_frequency),
+	.pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(3),
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 	.irq_config_func = uart_cmsdk_apb_irq_config_func_3,
 #endif
@@ -736,14 +749,14 @@ static void uart_cmsdk_apb_irq_config_func_3(const struct device *dev)
 #endif /* DT_NODE_HAS_STATUS_OKAY(DT_DRV_INST(3)) */
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_DRV_INST(4))
-
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 static void uart_cmsdk_apb_irq_config_func_4(const struct device *dev);
 #endif
-
+PINCTRL_DT_INST_DEFINE(4);
 static const struct uart_cmsdk_apb_config uart_cmsdk_apb_dev_cfg_4 = {
 	.uart = (volatile struct uart_cmsdk_apb *)DT_INST_REG_ADDR(4),
 	.sys_clk_freq = DT_INST_PROP_BY_PHANDLE(4, clocks, clock_frequency),
+	.pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(4),
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 	.irq_config_func = uart_cmsdk_apb_irq_config_func_4,
 #endif
diff --git a/drivers/serial/uart_esp32.c b/drivers/serial/uart_esp32.c
index 35986ce6254..2638b258767 100644
--- a/drivers/serial/uart_esp32.c
+++ b/drivers/serial/uart_esp32.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2019 Mohamed ElShahawi (extremegtx@hotmail.com)
- * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2023-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -51,13 +51,7 @@
 #include <soc.h>
 #include <zephyr/drivers/uart.h>
 
-#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
-	defined(CONFIG_SOC_SERIES_ESP32C3) || \
-	defined(CONFIG_SOC_SERIES_ESP32C6)
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-#else
 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
-#endif
 
 #include <zephyr/drivers/clock_control.h>
 #include <errno.h>
@@ -67,14 +61,6 @@
 
 LOG_MODULE_REGISTER(uart_esp32, CONFIG_UART_LOG_LEVEL);
 
-#if defined(CONFIG_SOC_SERIES_ESP32C2) || \
-	defined(CONFIG_SOC_SERIES_ESP32C3) || \
-	defined(CONFIG_SOC_SERIES_ESP32C6)
-#define ISR_HANDLER isr_handler_t
-#else
-#define ISR_HANDLER intr_handler_t
-#endif
-
 struct uart_esp32_config {
 	const struct device *clock_dev;
 	const struct pinctrl_dev_config *pcfg;
@@ -962,7 +948,7 @@ static int uart_esp32_init(const struct device *dev)
 	ret = esp_intr_alloc(config->irq_source,
 			ESP_PRIO_TO_FLAGS(config->irq_priority) |
 			ESP_INT_FLAGS_CHECK(config->irq_flags),
-			(ISR_HANDLER)uart_esp32_isr,
+			(intr_handler_t)uart_esp32_isr,
 			(void *)dev,
 			NULL);
 	if (ret < 0) {
@@ -1055,11 +1041,9 @@ static DEVICE_API(uart, uart_esp32_api) = {
                                                                                                    \
 	static struct uart_esp32_data uart_esp32_data_##idx = {                                    \
 		.uart_config = {.baudrate = DT_INST_PROP(idx, current_speed),                      \
-				.parity = DT_INST_ENUM_IDX_OR(idx, parity, UART_CFG_PARITY_NONE),  \
-				.stop_bits = DT_INST_ENUM_IDX_OR(idx, stop_bits,                   \
-								 UART_CFG_STOP_BITS_1),            \
-				.data_bits = DT_INST_ENUM_IDX_OR(idx, data_bits,                   \
-								 UART_CFG_DATA_BITS_8),            \
+				.parity = DT_INST_ENUM_IDX(idx, parity),                           \
+				.stop_bits = DT_INST_ENUM_IDX(idx, stop_bits),                     \
+				.data_bits = DT_INST_ENUM_IDX(idx, data_bits),                     \
 				.flow_ctrl = MAX(COND_CODE_1(DT_INST_PROP(idx, hw_rs485_hd_mode),  \
 							     (UART_CFG_FLOW_CTRL_RS485),           \
 							     (UART_CFG_FLOW_CTRL_NONE)),           \
@@ -1073,7 +1057,7 @@ static DEVICE_API(uart, uart_esp32_api) = {
 		ESP_UART_UHCI_INIT(idx)};                                                          \
                                                                                                    \
 	DEVICE_DT_INST_DEFINE(idx, uart_esp32_init, NULL, &uart_esp32_data_##idx,                  \
-			      &uart_esp32_cfg_port_##idx, PRE_KERNEL_1,                            \
+			      &uart_esp32_cfg_port_##idx, PRE_KERNEL_2,                            \
 			      CONFIG_SERIAL_INIT_PRIORITY, &uart_esp32_api);
 
 DT_INST_FOREACH_STATUS_OKAY(ESP32_UART_INIT);
diff --git a/drivers/serial/uart_gecko.c b/drivers/serial/uart_gecko.c
index ceecde5d229..78665dcd0e2 100644
--- a/drivers/serial/uart_gecko.c
+++ b/drivers/serial/uart_gecko.c
@@ -19,13 +19,7 @@
 #include <em_gpio.h>
 #endif /* CONFIG_PINCTRL */
 
-#ifdef CONFIG_CLOCK_CONTROL
-#include <zephyr/drivers/clock_control.h>
-#include <zephyr/drivers/clock_control/clock_control_silabs.h>
-#define GET_GECKO_USART_CLOCK(idx)                            \
-	.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
-	.clock_cfg = SILABS_DT_INST_CLOCK_CFG(idx),
-#elif DT_NODE_HAS_PROP(id, peripheral_id)
+#if DT_NODE_HAS_PROP(id, peripheral_id)
 #define USART_PREFIX cmuClock_USART
 #define UART_PREFIX cmuClock_UART
 #define CLOCK_USART(id) _CONCAT(USART_PREFIX, id)
@@ -130,18 +124,7 @@ struct uart_gecko_config {
 	const struct pinctrl_dev_config *pcfg;
 #endif /* CONFIG_PINCTRL */
 	USART_TypeDef *base;
-#ifdef CONFIG_CLOCK_CONTROL
-	const struct device *clock_dev;
-	const struct silabs_clock_control_cmu_config clock_cfg;
-#else
 	CMU_Clock_TypeDef clock;
-#endif
-	uint32_t baud_rate;
-#ifndef CONFIG_PINCTRL
-#ifdef UART_GECKO_HW_FLOW_CONTROL
-	bool hw_flowcontrol;
-#endif /* UART_GECKO_HW_FLOW_CONTROL */
-#endif
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 	void (*irq_config_func)(const struct device *dev);
 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
@@ -166,6 +149,7 @@ struct uart_gecko_config {
 };
 
 struct uart_gecko_data {
+	struct uart_config *uart_cfg;
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 	uart_irq_callback_user_data_t callback;
 	void *cb_data;
@@ -402,8 +386,10 @@ static void uart_gecko_init_pins(const struct device *dev)
 #endif /* CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION */
 
 #ifdef UART_GECKO_HW_FLOW_CONTROL
+	const struct uart_gecko_data *data = dev->data;
+	const struct uart_config *uart_cfg = data->uart_cfg;
 	/* Configure HW flow control (RTS, CTS) */
-	if (config->hw_flowcontrol) {
+	if (uart_cfg->flow_ctrl) {
 		GPIO_PinModeSet(config->pin_rts.port, config->pin_rts.pin,
 				config->pin_rts.mode, config->pin_rts.out);
 		GPIO_PinModeSet(config->pin_cts.port, config->pin_cts.pin,
@@ -438,6 +424,202 @@ static void uart_gecko_init_pins(const struct device *dev)
 }
 #endif /* !CONFIG_PINCTRL */
 
+static inline USART_Parity_TypeDef uart_gecko_cfg2ll_parity(enum uart_config_parity parity)
+{
+	switch (parity) {
+	case UART_CFG_PARITY_ODD:
+		return usartOddParity;
+	case UART_CFG_PARITY_EVEN:
+		return usartEvenParity;
+	case UART_CFG_PARITY_NONE:
+	default:
+		return usartNoParity;
+	}
+}
+
+static inline enum uart_config_parity uart_gecko_ll2cfg_parity(USART_Parity_TypeDef parity)
+{
+	switch (parity) {
+	case usartOddParity:
+		return UART_CFG_PARITY_ODD;
+	case usartEvenParity:
+		return UART_CFG_PARITY_EVEN;
+	case usartNoParity:
+	default:
+		return UART_CFG_PARITY_NONE;
+	}
+}
+
+static inline USART_Stopbits_TypeDef uart_gecko_cfg2ll_stopbits(enum uart_config_stop_bits sb)
+{
+	switch (sb) {
+	case UART_CFG_STOP_BITS_0_5:
+		return usartStopbits0p5;
+	case UART_CFG_STOP_BITS_1:
+		return usartStopbits1;
+	case UART_CFG_STOP_BITS_2:
+		return usartStopbits2;
+	case UART_CFG_STOP_BITS_1_5:
+		return usartStopbits1p5;
+	default:
+		return usartStopbits1;
+	}
+}
+
+static inline enum uart_config_stop_bits uart_gecko_ll2cfg_stopbits(USART_Stopbits_TypeDef sb)
+{
+	switch (sb) {
+	case usartStopbits0p5:
+		return UART_CFG_STOP_BITS_0_5;
+	case usartStopbits1:
+		return UART_CFG_STOP_BITS_1;
+	case usartStopbits1p5:
+		return UART_CFG_STOP_BITS_1_5;
+	case usartStopbits2:
+		return UART_CFG_STOP_BITS_2;
+	default:
+		return UART_CFG_STOP_BITS_1;
+	}
+}
+
+static inline USART_Databits_TypeDef uart_gecko_cfg2ll_databits(enum uart_config_data_bits db,
+								   enum uart_config_parity p)
+{
+	switch (db) {
+	case UART_CFG_DATA_BITS_7:
+		if (p == UART_CFG_PARITY_NONE) {
+			return usartDatabits7;
+		} else {
+			return usartDatabits8;
+		}
+	case UART_CFG_DATA_BITS_9:
+		return usartDatabits9;
+	case UART_CFG_DATA_BITS_8:
+	default:
+		if (p == UART_CFG_PARITY_NONE) {
+			return usartDatabits8;
+		} else {
+			return usartDatabits9;
+		}
+		return usartDatabits8;
+	}
+}
+
+static inline enum uart_config_data_bits uart_gecko_ll2cfg_databits(USART_Databits_TypeDef db,
+								    USART_Parity_TypeDef p)
+{
+	switch (db) {
+	case usartDatabits7:
+		if (p == usartNoParity) {
+			return UART_CFG_DATA_BITS_7;
+		} else {
+			return UART_CFG_DATA_BITS_6;
+		}
+	case usartDatabits9:
+		if (p == usartNoParity) {
+			return UART_CFG_DATA_BITS_9;
+		} else {
+			return UART_CFG_DATA_BITS_8;
+		}
+	case usartDatabits8:
+	default:
+		if (p == usartNoParity) {
+			return UART_CFG_DATA_BITS_8;
+		} else {
+			return UART_CFG_DATA_BITS_7;
+		}
+	}
+}
+
+#if UART_GECKO_HW_FLOW_CONTROL
+/**
+ * @brief  Get LL hardware flow control define from
+ *         Zephyr hardware flow control option.
+ * @note   Supports only UART_CFG_FLOW_CTRL_RTS_CTS and UART_CFG_FLOW_CTRL_RS485.
+ * @param  fc: Zephyr hardware flow control option.
+ * @retval usartHwFlowControlCtsAndRts, or usartHwFlowControlNone.
+ */
+static inline USART_HwFlowControl_TypeDef uart_gecko_cfg2ll_hwctrl(
+	enum uart_config_flow_control fc)
+{
+	if (fc == UART_CFG_FLOW_CTRL_RTS_CTS) {
+		return usartHwFlowControlCtsAndRts;
+	}
+
+	return usartHwFlowControlNone;
+}
+
+/**
+ * @brief  Get Zephyr hardware flow control option from
+ *         LL hardware flow control define.
+ * @note   Supports only usartHwFlowControlCtsAndRts.
+ * @param  fc: LL hardware flow control definition.
+ * @retval UART_CFG_FLOW_CTRL_RTS_CTS, or UART_CFG_FLOW_CTRL_NONE.
+ */
+static inline enum uart_config_flow_control uart_gecko_ll2cfg_hwctrl(
+	USART_HwFlowControl_TypeDef fc)
+{
+	if (fc == usartHwFlowControlCtsAndRts) {
+		return UART_CFG_FLOW_CTRL_RTS_CTS;
+	}
+
+	return UART_CFG_FLOW_CTRL_NONE;
+}
+#endif
+
+#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
+static int uart_gecko_configure(const struct device *dev,
+				const struct uart_config *cfg)
+{
+	const struct uart_gecko_config *config = dev->config;
+	USART_TypeDef *base = config->base;
+	struct uart_gecko_data *data = dev->data;
+	struct uart_config *uart_cfg = data->uart_cfg;
+
+	if (uart_cfg->parity != cfg->parity) {
+		return -ENOTSUP;
+	}
+
+	if (uart_cfg->stop_bits != cfg->stop_bits) {
+		return -ENOTSUP;
+	}
+
+	if (uart_cfg->data_bits != cfg->data_bits) {
+		return -ENOTSUP;
+	}
+
+	if (uart_cfg->flow_ctrl != cfg->flow_ctrl) {
+		return -ENOTSUP;
+	}
+
+	USART_BaudrateAsyncSet(base, 0, cfg->baudrate, usartOVS16);
+
+	/* Upon successful configuration, persist the syscall-passed
+	 * uart_config.
+	 * This allows restoring it, should the device return from a low-power
+	 * mode in which register contents are lost.
+	 */
+	*uart_cfg = *cfg;
+
+	return 0;
+};
+
+static int uart_gecko_config_get(const struct device *dev,
+				 struct uart_config *cfg)
+{
+	struct uart_gecko_data *data = dev->data;
+	struct uart_config *uart_cfg = data->uart_cfg;
+
+	cfg->baudrate = uart_cfg->baudrate;
+	cfg->parity = uart_cfg->parity;
+	cfg->stop_bits = uart_cfg->stop_bits;
+	cfg->data_bits = uart_cfg->data_bits;
+	cfg->flow_ctrl = uart_cfg->flow_ctrl;
+
+	return 0;
+}
+#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
+
 /**
  * @brief Main initializer for UART
  *
@@ -450,24 +632,22 @@ static int uart_gecko_init(const struct device *dev)
 	int err;
 #endif /* CONFIG_PINCTRL */
 	const struct uart_gecko_config *config = dev->config;
+	const struct uart_gecko_data *data = dev->data;
+	const struct uart_config *uart_cfg = data->uart_cfg;
 
 	USART_InitAsync_TypeDef usartInit = USART_INITASYNC_DEFAULT;
 
 	/* The peripheral and gpio clock are already enabled from soc and gpio driver */
 	/* Enable USART clock */
-#ifdef CONFIG_CLOCK_CONTROL
-	err = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_cfg);
-	if (err < 0) {
-		return err;
-	}
-#else
 	CMU_ClockEnable(config->clock, true);
-#endif
 
 	/* Init USART */
-	usartInit.baudrate = config->baud_rate;
+	usartInit.baudrate = uart_cfg->baudrate;
+	usartInit.parity = uart_gecko_cfg2ll_parity(uart_cfg->parity);
+	usartInit.stopbits = uart_gecko_cfg2ll_stopbits(uart_cfg->stop_bits);
+	usartInit.databits = uart_gecko_cfg2ll_databits(uart_cfg->data_bits, uart_cfg->parity);
 #ifdef UART_GECKO_HW_FLOW_CONTROL
-	usartInit.hwFlowControl = config->hw_flowcontrol ?
+	usartInit.hwFlowControl = uart_cfg->flow_ctrl ?
 		usartHwFlowControlCtsAndRts : usartHwFlowControlNone;
 #endif
 	USART_InitAsync(config->base, &usartInit);
@@ -518,6 +698,10 @@ static DEVICE_API(uart, uart_gecko_driver_api) = {
 	.poll_in = uart_gecko_poll_in,
 	.poll_out = uart_gecko_poll_out,
 	.err_check = uart_gecko_err_check,
+#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
+	.configure = uart_gecko_configure,
+	.config_get = uart_gecko_config_get,
+#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 	.fifo_fill = uart_gecko_fifo_fill,
 	.fifo_read = uart_gecko_fifo_read,
@@ -638,45 +822,51 @@ static DEVICE_API(uart, uart_gecko_driver_api) = {
 	.pin_rts = PIN_UART_RTS(idx),					       \
 	.pin_cts = PIN_UART_CTS(idx),
 
-#define GECKO_UART_HW_FLOW_CONTROL(idx)					       \
-	.hw_flowcontrol = DT_INST_PROP(idx, hw_flow_control),
-
 #else /* UART_GECKO_HW_FLOW_CONTROL */
 
 #define GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx)
 #define VALIDATE_GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx)
 #define GECKO_UART_RTS_CTS_PINS(idx)
-#define GECKO_UART_HW_FLOW_CONTROL(idx)
 
 #endif /* UART_GECKO_HW_FLOW_CONTROL */
 
-#define GECKO_UART_INIT(idx)						       \
-	VALIDATE_GECKO_UART_RX_TX_PIN_LOCATIONS(idx);			       \
-	VALIDATE_GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx);			       \
-									       \
-	GECKO_UART_IRQ_HANDLER_DECL(idx);				       \
-									       \
-	static const struct uart_gecko_config uart_gecko_cfg_##idx = {	       \
-		.base = (USART_TypeDef *)DT_INST_REG_ADDR(idx),		       \
-		GET_GECKO_UART_CLOCK(idx)				       \
-		.baud_rate = DT_INST_PROP(idx, current_speed),		       \
-		GECKO_UART_HW_FLOW_CONTROL(idx)				       \
-		GECKO_UART_RX_TX_PINS(idx)				       \
-		GECKO_UART_RTS_CTS_PINS(idx)				       \
-		GECKO_UART_RX_TX_PIN_LOCATIONS(idx)			       \
-		GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx)			       \
-		GECKO_UART_IRQ_HANDLER_FUNC(idx)			       \
-	};								       \
-									       \
-	static struct uart_gecko_data uart_gecko_data_##idx;		       \
-									       \
-	DEVICE_DT_INST_DEFINE(idx, uart_gecko_init,			       \
-			    NULL, &uart_gecko_data_##idx,		       \
-			    &uart_gecko_cfg_##idx, PRE_KERNEL_1,	       \
-			    CONFIG_SERIAL_INIT_PRIORITY,		       \
-			    &uart_gecko_driver_api);			       \
-									       \
-									       \
+#define GECKO_UART_INIT(idx)							\
+	VALIDATE_GECKO_UART_RX_TX_PIN_LOCATIONS(idx);				\
+	VALIDATE_GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx);				\
+										\
+	GECKO_UART_IRQ_HANDLER_DECL(idx);					\
+	PM_DEVICE_DT_INST_DEFINE(idx, uart_gecko_pm_action);			\
+										\
+	static struct uart_config uart_cfg_##idx = {				\
+		.baudrate  = DT_INST_PROP(idx, current_speed),			\
+		.parity    = DT_INST_ENUM_IDX(idx, parity),			\
+		.stop_bits = DT_INST_ENUM_IDX(idx, stop_bits),			\
+		.data_bits = DT_INST_ENUM_IDX(idx, data_bits),			\
+		.flow_ctrl = DT_INST_PROP(idx, hw_flow_control)			\
+					? UART_CFG_FLOW_CTRL_RTS_CTS		\
+					: UART_CFG_FLOW_CTRL_NONE,		\
+	};									\
+										\
+	static const struct uart_gecko_config uart_gecko_cfg_##idx = {		\
+		.base = (USART_TypeDef *)DT_INST_REG_ADDR(idx),			\
+		GET_GECKO_UART_CLOCK(idx)					\
+		GECKO_UART_RX_TX_PINS(idx)					\
+		GECKO_UART_RTS_CTS_PINS(idx)					\
+		GECKO_UART_RX_TX_PIN_LOCATIONS(idx)				\
+		GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx)				\
+		GECKO_UART_IRQ_HANDLER_FUNC(idx)				\
+	};									\
+										\
+										\
+	static struct uart_gecko_data uart_gecko_data_##idx = {			\
+		.uart_cfg = &uart_cfg_##idx,					\
+	};									\
+										\
+	DEVICE_DT_INST_DEFINE(idx, uart_gecko_init, PM_DEVICE_DT_INST_GET(idx),	\
+			      &uart_gecko_data_##idx, &uart_gecko_cfg_##idx,	\
+			      PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY,	\
+			      &uart_gecko_driver_api);				\
+										\
 	GECKO_UART_IRQ_HANDLER(idx)
 
 DT_INST_FOREACH_STATUS_OKAY(GECKO_UART_INIT)
@@ -709,56 +899,77 @@ DT_INST_FOREACH_STATUS_OKAY(GECKO_UART_INIT)
 #endif
 
 #ifdef CONFIG_PINCTRL
-#define GECKO_USART_INIT(idx)						       \
-	PINCTRL_DT_INST_DEFINE(idx);					       \
-	GECKO_USART_IRQ_HANDLER_DECL(idx);				       \
-	PM_DEVICE_DT_INST_DEFINE(idx, uart_gecko_pm_action);		       \
-									       \
-	static const struct uart_gecko_config usart_gecko_cfg_##idx = {        \
-		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx),		       \
-		.base = (USART_TypeDef *)DT_INST_REG_ADDR(idx),		       \
-		GET_GECKO_USART_CLOCK(idx)				       \
-		.baud_rate = DT_INST_PROP(idx, current_speed),		       \
-		GECKO_USART_IRQ_HANDLER_FUNC(idx)			       \
-		};							       \
-									       \
-	static struct uart_gecko_data usart_gecko_data_##idx;		       \
-									       \
-	DEVICE_DT_INST_DEFINE(idx, uart_gecko_init, PM_DEVICE_DT_INST_GET(idx),\
-			    &usart_gecko_data_##idx,			       \
-			    &usart_gecko_cfg_##idx, PRE_KERNEL_1,	       \
-			    CONFIG_SERIAL_INIT_PRIORITY,		       \
-			    &uart_gecko_driver_api);			       \
-									       \
+#define GECKO_USART_INIT(idx)							\
+	PINCTRL_DT_INST_DEFINE(idx);						\
+	GECKO_USART_IRQ_HANDLER_DECL(idx);					\
+	PM_DEVICE_DT_INST_DEFINE(idx, uart_gecko_pm_action);			\
+										\
+	static struct uart_config uart_cfg_##idx = {				\
+		.baudrate  = DT_INST_PROP(idx, current_speed),			\
+		.parity    = DT_INST_ENUM_IDX(idx, parity),			\
+		.stop_bits = DT_INST_ENUM_IDX(idx, stop_bits),			\
+		.data_bits = DT_INST_ENUM_IDX(idx, data_bits),			\
+		.flow_ctrl = DT_INST_PROP(idx, hw_flow_control)			\
+					? UART_CFG_FLOW_CTRL_RTS_CTS		\
+					: UART_CFG_FLOW_CTRL_NONE,		\
+	};									\
+										\
+	static const struct uart_gecko_config usart_gecko_cfg_##idx = {		\
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx),			\
+		.base = (USART_TypeDef *)DT_INST_REG_ADDR(idx),			\
+		GET_GECKO_USART_CLOCK(idx)					\
+		GECKO_USART_IRQ_HANDLER_FUNC(idx)				\
+	}	;								\
+										\
+	static struct uart_gecko_data usart_gecko_data_##idx = {		\
+		.uart_cfg = &uart_cfg_##idx,					\
+	};									\
+										\
+	DEVICE_DT_INST_DEFINE(idx, uart_gecko_init, PM_DEVICE_DT_INST_GET(idx),	\
+			    &usart_gecko_data_##idx,				\
+			    &usart_gecko_cfg_##idx, PRE_KERNEL_1,		\
+			    CONFIG_SERIAL_INIT_PRIORITY,			\
+			    &uart_gecko_driver_api);				\
+										\
 	GECKO_USART_IRQ_HANDLER(idx)
 #else
-#define GECKO_USART_INIT(idx)						       \
-	VALIDATE_GECKO_UART_RX_TX_PIN_LOCATIONS(idx);			       \
-	VALIDATE_GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx);			       \
-									       \
-	GECKO_USART_IRQ_HANDLER_DECL(idx);				       \
-	PM_DEVICE_DT_INST_DEFINE(idx, uart_gecko_pm_action);		       \
-									       \
-	static const struct uart_gecko_config usart_gecko_cfg_##idx = {        \
-		.base = (USART_TypeDef *)DT_INST_REG_ADDR(idx),		       \
-		GET_GECKO_USART_CLOCK(idx)				       \
-		.baud_rate = DT_INST_PROP(idx, current_speed),		       \
-		GECKO_UART_HW_FLOW_CONTROL(idx)				       \
-		GECKO_UART_RX_TX_PINS(idx)				       \
-		GECKO_UART_RTS_CTS_PINS(idx)				       \
-		GECKO_UART_RX_TX_PIN_LOCATIONS(idx)			       \
-		GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx)			       \
-		GECKO_USART_IRQ_HANDLER_FUNC(idx)			       \
-	};								       \
-									       \
-	static struct uart_gecko_data usart_gecko_data_##idx;		       \
-									       \
-	DEVICE_DT_INST_DEFINE(idx, uart_gecko_init, PM_DEVICE_DT_INST_GET(idx),\
-			    &usart_gecko_data_##idx,			       \
-			    &usart_gecko_cfg_##idx, PRE_KERNEL_1,	       \
-			    CONFIG_SERIAL_INIT_PRIORITY,		       \
-			    &uart_gecko_driver_api);			       \
-									       \
+#define GECKO_USART_INIT(idx)							\
+	VALIDATE_GECKO_UART_RX_TX_PIN_LOCATIONS(idx);				\
+	VALIDATE_GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx);				\
+										\
+	GECKO_USART_IRQ_HANDLER_DECL(idx);					\
+	PM_DEVICE_DT_INST_DEFINE(idx, uart_gecko_pm_action);			\
+										\
+	static struct uart_config uart_cfg_##idx = {				\
+		.baudrate  = DT_INST_PROP(idx, current_speed),			\
+		.parity    = DT_INST_ENUM_IDX(idx, parity),			\
+		.stop_bits = DT_INST_ENUM_IDX(idx, stop_bits),			\
+		.data_bits = DT_INST_ENUM_IDX(idx, data_bits),			\
+		.flow_ctrl = DT_INST_PROP(idx, hw_flow_control)			\
+					? UART_CFG_FLOW_CTRL_RTS_CTS		\
+					: UART_CFG_FLOW_CTRL_NONE,		\
+	};									\
+										\
+	static const struct uart_gecko_config usart_gecko_cfg_##idx = {		\
+		.base = (USART_TypeDef *)DT_INST_REG_ADDR(idx),			\
+		GET_GECKO_USART_CLOCK(idx)					\
+		GECKO_UART_RX_TX_PINS(idx)					\
+		GECKO_UART_RTS_CTS_PINS(idx)					\
+		GECKO_UART_RX_TX_PIN_LOCATIONS(idx)				\
+		GECKO_UART_RTS_CTS_PIN_LOCATIONS(idx)				\
+		GECKO_USART_IRQ_HANDLER_FUNC(idx)				\
+	};									\
+										\
+	static struct uart_gecko_data usart_gecko_data_##idx = {		\
+		.uart_cfg = &uart_cfg_##idx,					\
+	};									\
+										\
+	DEVICE_DT_INST_DEFINE(idx, uart_gecko_init, PM_DEVICE_DT_INST_GET(idx),	\
+			    &usart_gecko_data_##idx,				\
+			    &usart_gecko_cfg_##idx, PRE_KERNEL_1,		\
+			    CONFIG_SERIAL_INIT_PRIORITY,			\
+			    &uart_gecko_driver_api);				\
+										\
 	GECKO_USART_IRQ_HANDLER(idx)
 #endif
 
diff --git a/drivers/serial/uart_ifx_cat1.c b/drivers/serial/uart_ifx_cat1.c
index c421a01c4a9..4f9f1064f21 100644
--- a/drivers/serial/uart_ifx_cat1.c
+++ b/drivers/serial/uart_ifx_cat1.c
@@ -8,9 +8,6 @@
 /**
  * @brief UART driver for Infineon CAT1 MCU family.
  *
- * Note:
- * - Uart ASYNC functionality is not implemented in current
- *   version of Uart CAT1 driver.
  */
 
 #define DT_DRV_COMPAT infineon_cat1_uart
@@ -21,17 +18,65 @@
 #include <cyhal_utils_impl.h>
 #include <cyhal_scb_common.h>
 
+#include "cy_scb_uart.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(uart_ifx_cat1, CONFIG_UART_LOG_LEVEL);
+
+#ifdef CONFIG_UART_ASYNC_API
+#include <zephyr/drivers/dma.h>
+#include <cyhal_dma.h>
+
+extern int ifx_cat1_dma_ex_connect_digital(const struct device *dev, uint32_t channel,
+					   cyhal_source_t source, cyhal_dma_input_t input);
+
+struct ifx_cat1_dma_stream {
+	const struct device *dev;
+	uint32_t dma_channel;
+	struct dma_config dma_cfg;
+	struct dma_block_config blk_cfg;
+	uint8_t *buf;
+	size_t buf_len;
+	size_t offset;
+	size_t counter;
+	uint32_t timeout;
+	size_t dma_transmitted_bytes;
+
+	struct k_work_delayable timeout_work;
+};
+
+struct ifx_cat1_uart_async {
+	const struct device *uart_dev;
+	uart_callback_t cb;
+	void *user_data;
+
+	struct ifx_cat1_dma_stream dma_rx;
+	struct ifx_cat1_dma_stream dma_tx;
+
+	uint8_t *rx_next_buf;
+	size_t rx_next_buf_len;
+};
+
+#define CURRENT_BUFFER 0
+#define NEXT_BUFFER    1
+
+#endif /* CONFIG_UART_ASYNC_API */
+
 /* Data structure */
 struct ifx_cat1_uart_data {
-	cyhal_uart_t obj;                               /* UART CYHAL object */
+	cyhal_uart_t obj; /* UART CYHAL object */
 	struct uart_config cfg;
 	cyhal_resource_inst_t hw_resource;
 	cyhal_clock_t clock;
 
 #if CONFIG_UART_INTERRUPT_DRIVEN
-	uart_irq_callback_user_data_t irq_cb;           /* Interrupt Callback */
-	void *irq_cb_data;                              /* Interrupt Callback Arg */
-#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+	uart_irq_callback_user_data_t irq_cb; /* Interrupt Callback */
+	void *irq_cb_data;                    /* Interrupt Callback Arg */
+#endif
+
+#ifdef CONFIG_UART_ASYNC_API
+	struct ifx_cat1_uart_async async;
+#endif
 };
 
 /* Device config structure */
@@ -153,17 +198,34 @@ static uint32_t _convert_uart_data_bits_z_to_cyhal(enum uart_config_data_bits da
 
 static int32_t _get_hw_block_num(CySCB_Type *reg_addr)
 {
+	extern const uint8_t _CYHAL_SCB_BASE_ADDRESS_INDEX[_SCB_ARRAY_SIZE];
+	extern CySCB_Type *const _CYHAL_SCB_BASE_ADDRESSES[_SCB_ARRAY_SIZE];
+
 	uint32_t i;
 
 	for (i = 0u; i < _SCB_ARRAY_SIZE; i++) {
 		if (_CYHAL_SCB_BASE_ADDRESSES[i] == reg_addr) {
-			return i;
+			return _CYHAL_SCB_BASE_ADDRESS_INDEX[i];
 		}
 	}
 
 	return -1;
 }
 
+uint32_t ifx_cat1_uart_get_num_in_tx_fifo(const struct device *dev)
+{
+	const struct ifx_cat1_uart_config *const config = dev->config;
+
+	return Cy_SCB_GetNumInTxFifo(config->reg_addr);
+}
+
+bool ifx_cat1_uart_get_tx_active(const struct device *dev)
+{
+	const struct ifx_cat1_uart_config *const config = dev->config;
+
+	return Cy_SCB_GetTxSrValid(config->reg_addr) ? true : false;
+}
+
 static int ifx_cat1_uart_poll_in(const struct device *dev, unsigned char *c)
 {
 	cy_rslt_t rec;
@@ -178,7 +240,7 @@ static void ifx_cat1_uart_poll_out(const struct device *dev, unsigned char c)
 {
 	struct ifx_cat1_uart_data *data = dev->data;
 
-	(void) cyhal_uart_putc(&data->obj, (uint32_t)c);
+	(void)cyhal_uart_putc(&data->obj, (uint32_t)c);
 }
 
 static int ifx_cat1_uart_err_check(const struct device *dev)
@@ -202,8 +264,7 @@ static int ifx_cat1_uart_err_check(const struct device *dev)
 	return errors;
 }
 
-static int ifx_cat1_uart_configure(const struct device *dev,
-				   const struct uart_config *cfg)
+static int ifx_cat1_uart_configure(const struct device *dev, const struct uart_config *cfg)
 {
 	__ASSERT_NO_MSG(cfg != NULL);
 
@@ -213,8 +274,7 @@ static int ifx_cat1_uart_configure(const struct device *dev,
 	cyhal_uart_cfg_t uart_cfg = {
 		.data_bits = _convert_uart_data_bits_z_to_cyhal(cfg->data_bits),
 		.stop_bits = _convert_uart_stop_bits_z_to_cyhal(cfg->stop_bits),
-		.parity = _convert_uart_parity_z_to_cyhal(cfg->parity)
-	};
+		.parity = _convert_uart_parity_z_to_cyhal(cfg->parity)};
 
 	/* Store Uart Zephyr configuration (uart config) into data structure */
 	data->cfg = *cfg;
@@ -233,14 +293,13 @@ static int ifx_cat1_uart_configure(const struct device *dev,
 
 	/* Enable RTS/CTS flow control */
 	if ((result == CY_RSLT_SUCCESS) && cfg->flow_ctrl) {
-		Cy_SCB_UART_EnableCts(data->obj.base);
+		result = cyhal_uart_enable_flow_control(&data->obj, true, true);
 	}
 
 	return (result == CY_RSLT_SUCCESS) ? 0 : -ENOTSUP;
 };
 
-static int ifx_cat1_uart_config_get(const struct device *dev,
-				    struct uart_config *cfg)
+static int ifx_cat1_uart_config_get(const struct device *dev, struct uart_config *cfg)
 {
 	ARG_UNUSED(dev);
 
@@ -261,7 +320,7 @@ static void _uart_event_callback_irq_mode(void *arg, cyhal_uart_event_t event)
 {
 	ARG_UNUSED(event);
 
-	const struct device *dev = (const struct device *) arg;
+	const struct device *dev = (const struct device *)arg;
 	struct ifx_cat1_uart_data *const data = dev->data;
 
 	if (data->irq_cb != NULL) {
@@ -270,25 +329,23 @@ static void _uart_event_callback_irq_mode(void *arg, cyhal_uart_event_t event)
 }
 
 /* Fill FIFO with data */
-static int ifx_cat1_uart_fifo_fill(const struct device *dev,
-				   const uint8_t *tx_data, int size)
+static int ifx_cat1_uart_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size)
 {
 	struct ifx_cat1_uart_data *const data = dev->data;
-	size_t _size = (size_t) size;
+	size_t _size = (size_t)size;
 
-	(void)cyhal_uart_write(&data->obj, (uint8_t *) tx_data,  &_size);
-	return (int) _size;
+	(void)cyhal_uart_write(&data->obj, (uint8_t *)tx_data, &_size);
+	return (int)_size;
 }
 
 /* Read data from FIFO */
-static int ifx_cat1_uart_fifo_read(const struct device *dev,
-				   uint8_t *rx_data, const int size)
+static int ifx_cat1_uart_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
 {
 	struct ifx_cat1_uart_data *const data = dev->data;
-	size_t _size = (size_t) size;
+	size_t _size = (size_t)size;
 
 	(void)cyhal_uart_read(&data->obj, rx_data, &_size);
-	return (int) _size;
+	return (int)_size;
 }
 
 /* Enable TX interrupt */
@@ -297,8 +354,7 @@ static void ifx_cat1_uart_irq_tx_enable(const struct device *dev)
 	struct ifx_cat1_uart_data *const data = dev->data;
 	const struct ifx_cat1_uart_config *const config = dev->config;
 
-	cyhal_uart_enable_event(&data->obj,
-				(cyhal_uart_event_t) CYHAL_UART_IRQ_TX_EMPTY,
+	cyhal_uart_enable_event(&data->obj, (cyhal_uart_event_t)CYHAL_UART_IRQ_TX_EMPTY,
 				config->irq_priority, 1);
 }
 
@@ -308,8 +364,7 @@ static void ifx_cat1_uart_irq_tx_disable(const struct device *dev)
 	struct ifx_cat1_uart_data *const data = dev->data;
 	const struct ifx_cat1_uart_config *const config = dev->config;
 
-	cyhal_uart_enable_event(&data->obj,
-				(cyhal_uart_event_t) CYHAL_UART_IRQ_TX_EMPTY,
+	cyhal_uart_enable_event(&data->obj, (cyhal_uart_event_t)CYHAL_UART_IRQ_TX_EMPTY,
 				config->irq_priority, 0);
 }
 
@@ -327,7 +382,7 @@ static int ifx_cat1_uart_irq_tx_complete(const struct device *dev)
 {
 	struct ifx_cat1_uart_data *const data = dev->data;
 
-	return (int) !(cyhal_uart_is_tx_active(&data->obj));
+	return (int)!(cyhal_uart_is_tx_active(&data->obj));
 }
 
 /* Enable RX interrupt */
@@ -336,8 +391,7 @@ static void ifx_cat1_uart_irq_rx_enable(const struct device *dev)
 	struct ifx_cat1_uart_data *const data = dev->data;
 	const struct ifx_cat1_uart_config *const config = dev->config;
 
-	cyhal_uart_enable_event(&data->obj,
-				(cyhal_uart_event_t) CYHAL_UART_IRQ_RX_NOT_EMPTY,
+	cyhal_uart_enable_event(&data->obj, (cyhal_uart_event_t)CYHAL_UART_IRQ_RX_NOT_EMPTY,
 				config->irq_priority, 1);
 }
 
@@ -347,8 +401,7 @@ static void ifx_cat1_uart_irq_rx_disable(const struct device *dev)
 	struct ifx_cat1_uart_data *const data = dev->data;
 	const struct ifx_cat1_uart_config *const config = dev->config;
 
-	cyhal_uart_enable_event(&data->obj,
-				(cyhal_uart_event_t) CYHAL_UART_IRQ_RX_NOT_EMPTY,
+	cyhal_uart_enable_event(&data->obj, (cyhal_uart_event_t)CYHAL_UART_IRQ_RX_NOT_EMPTY,
 				config->irq_priority, 0);
 }
 
@@ -366,9 +419,9 @@ static void ifx_cat1_uart_irq_err_enable(const struct device *dev)
 	struct ifx_cat1_uart_data *const data = dev->data;
 	const struct ifx_cat1_uart_config *const config = dev->config;
 
-	cyhal_uart_enable_event(&data->obj, (cyhal_uart_event_t)
-				(CYHAL_UART_IRQ_TX_ERROR | CYHAL_UART_IRQ_RX_ERROR),
-				config->irq_priority, 1);
+	cyhal_uart_enable_event(
+		&data->obj, (cyhal_uart_event_t)(CYHAL_UART_IRQ_TX_ERROR | CYHAL_UART_IRQ_RX_ERROR),
+		config->irq_priority, 1);
 }
 
 /* Disable Error interrupts */
@@ -377,9 +430,9 @@ static void ifx_cat1_uart_irq_err_disable(const struct device *dev)
 	struct ifx_cat1_uart_data *const data = dev->data;
 	const struct ifx_cat1_uart_config *const config = dev->config;
 
-	cyhal_uart_enable_event(&data->obj, (cyhal_uart_event_t)
-				(CYHAL_UART_IRQ_TX_ERROR | CYHAL_UART_IRQ_RX_ERROR),
-				config->irq_priority, 0);
+	cyhal_uart_enable_event(
+		&data->obj, (cyhal_uart_event_t)(CYHAL_UART_IRQ_TX_ERROR | CYHAL_UART_IRQ_RX_ERROR),
+		config->irq_priority, 0);
 }
 
 /* Check if any IRQs is pending */
@@ -388,7 +441,7 @@ static int ifx_cat1_uart_irq_is_pending(const struct device *dev)
 	struct ifx_cat1_uart_data *const data = dev->data;
 	uint32_t intcause = Cy_SCB_GetInterruptCause(data->obj.base);
 
-	return (int) (intcause & (CY_SCB_TX_INTR | CY_SCB_RX_INTR));
+	return (int)(intcause & (CY_SCB_TX_INTR | CY_SCB_RX_INTR));
 }
 
 /* Start processing interrupts in ISR.
@@ -410,8 +463,7 @@ static int ifx_cat1_uart_irq_update(const struct device *dev)
 }
 
 static void ifx_cat1_uart_irq_callback_set(const struct device *dev,
-					   uart_irq_callback_user_data_t cb,
-					   void *cb_data)
+					   uart_irq_callback_user_data_t cb, void *cb_data)
 {
 	struct ifx_cat1_uart_data *data = dev->data;
 	cyhal_uart_t *uart_obj = &data->obj;
@@ -421,10 +473,455 @@ static void ifx_cat1_uart_irq_callback_set(const struct device *dev,
 	data->irq_cb_data = cb_data;
 
 	/* Register a uart general callback handler  */
-	cyhal_uart_register_callback(uart_obj, _uart_event_callback_irq_mode, (void *) dev);
+	cyhal_uart_register_callback(uart_obj, _uart_event_callback_irq_mode, (void *)dev);
 }
+
 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
 
+#ifdef CONFIG_UART_ASYNC_API
+static int ifx_cat1_uart_async_callback_set(const struct device *dev, uart_callback_t callback,
+					    void *user_data)
+{
+	struct ifx_cat1_uart_data *const data = dev->data;
+
+	data->async.cb = callback;
+	data->async.user_data = user_data;
+	data->async.dma_tx.dma_cfg.user_data = (void *)dev;
+
+	return 0;
+}
+
+/* Async DMA helper */
+static int ifx_cat1_uart_async_dma_config_buffer(const struct device *dev, bool tx)
+{
+	int ret;
+	struct ifx_cat1_uart_data *const data = dev->data;
+	struct ifx_cat1_dma_stream *dma_stream = tx ? &data->async.dma_tx : &data->async.dma_rx;
+
+	/* Configure byte mode */
+	dma_stream->blk_cfg.block_size = dma_stream->buf_len;
+
+	if (tx) {
+		dma_stream->blk_cfg.source_address = (uint32_t)dma_stream->buf;
+	} else {
+		dma_stream->blk_cfg.dest_address = (uint32_t)dma_stream->buf;
+	}
+
+	ret = dma_config(dma_stream->dev, dma_stream->dma_channel, &dma_stream->dma_cfg);
+
+	if (!ret) {
+		ret = dma_start(dma_stream->dev, dma_stream->dma_channel);
+	}
+
+	return ret;
+}
+
+static int ifx_cat1_uart_async_tx(const struct device *dev, const uint8_t *tx_data,
+				  size_t tx_data_size, int32_t timeout)
+{
+	struct ifx_cat1_uart_data *const data = dev->data;
+	const struct device *dev_dma = data->async.dma_tx.dev;
+	int err;
+
+	if (dev_dma == NULL) {
+		err = -ENODEV;
+		goto exit;
+	}
+
+	if (tx_data == NULL || tx_data_size == 0) {
+		err = -EINVAL;
+		goto exit;
+	}
+
+	/* Store information about data buffer need to send */
+	data->async.dma_tx.buf = (uint8_t *)tx_data;
+	data->async.dma_tx.buf_len = tx_data_size;
+	data->async.dma_tx.blk_cfg.block_size = 0;
+	data->async.dma_tx.dma_transmitted_bytes = 0;
+
+	/* Configure dma to transfer */
+	err = ifx_cat1_uart_async_dma_config_buffer(dev, true);
+	if (err) {
+		LOG_ERR("Error Tx DMA configure (%d)", err);
+		goto exit;
+	}
+
+	/* Configure timeout */
+	if ((timeout != SYS_FOREVER_US) && (timeout != 0)) {
+		k_work_reschedule(&data->async.dma_tx.timeout_work, K_USEC(timeout));
+	}
+
+exit:
+	return err;
+}
+
+static int ifx_cat1_uart_async_tx_abort(const struct device *dev)
+{
+	struct ifx_cat1_uart_data *data = dev->data;
+	struct uart_event evt = {0};
+	struct dma_status stat;
+	int err = 0;
+	unsigned int key = irq_lock();
+
+	k_work_cancel_delayable(&data->async.dma_tx.timeout_work);
+
+	err = dma_stop(data->async.dma_tx.dev, data->async.dma_tx.dma_channel);
+	if (err) {
+		LOG_ERR("Error stopping Tx DMA (%d)", err);
+		goto unlock;
+	}
+
+	err = dma_get_status(data->async.dma_tx.dev, data->async.dma_tx.dma_channel, &stat);
+	if (err) {
+		LOG_ERR("Error stopping Tx DMA (%d)", err);
+		goto unlock;
+	}
+
+	evt.type = UART_TX_ABORTED;
+	evt.data.tx.buf = data->async.dma_tx.buf;
+	evt.data.tx.len = 0;
+
+	if (data->async.cb) {
+		data->async.cb(dev, &evt, data->async.user_data);
+	}
+
+unlock:
+	irq_unlock(key);
+	return err;
+}
+
+static void dma_callback_tx_done(const struct device *dma_dev, void *arg, uint32_t channel,
+				 int status)
+{
+	const struct device *uart_dev = (void *)arg;
+	struct ifx_cat1_uart_data *const data = uart_dev->data;
+	unsigned int key = irq_lock();
+
+	if (status == 0) {
+
+		k_work_cancel_delayable(&data->async.dma_tx.timeout_work);
+		dma_stop(data->async.dma_tx.dev, data->async.dma_tx.dma_channel);
+
+		struct uart_event evt = {.type = UART_TX_DONE,
+					 .data.tx.buf = data->async.dma_tx.buf,
+					 .data.tx.len = data->async.dma_tx.buf_len};
+
+		data->async.dma_tx.buf = NULL;
+		data->async.dma_tx.buf_len = 0;
+
+		if (data->async.cb) {
+			data->async.cb(uart_dev, &evt, data->async.user_data);
+		}
+
+	} else {
+		/* DMA error */
+		dma_stop(data->async.dma_tx.dev, data->async.dma_tx.dma_channel);
+	}
+	irq_unlock(key);
+}
+
+static void ifx_cat1_uart_async_tx_timeout(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct ifx_cat1_dma_stream *dma_tx =
+		CONTAINER_OF(dwork, struct ifx_cat1_dma_stream, timeout_work);
+	struct ifx_cat1_uart_async *async =
+		CONTAINER_OF(dma_tx, struct ifx_cat1_uart_async, dma_tx);
+
+	(void)ifx_cat1_uart_async_tx_abort(async->uart_dev);
+}
+
+static inline void async_evt_rx_rdy(struct ifx_cat1_uart_data *data)
+{
+	struct uart_event event = {.type = UART_RX_RDY,
+				   .data.rx.buf = (uint8_t *)data->async.dma_rx.buf,
+				   .data.rx.len =
+					   data->async.dma_rx.counter - data->async.dma_rx.offset,
+				   .data.rx.offset = data->async.dma_rx.offset};
+
+	data->async.dma_rx.offset = data->async.dma_rx.counter;
+
+	if (event.data.rx.len > 0 && data->async.cb) {
+		data->async.cb(data->async.uart_dev, &event, data->async.user_data);
+	}
+}
+
+static inline void async_evt_rx_buf_request(struct ifx_cat1_uart_data *data)
+{
+	struct uart_event evt = {.type = UART_RX_BUF_REQUEST};
+
+	if (data->async.cb) {
+		data->async.cb(data->async.uart_dev, &evt, data->async.user_data);
+	}
+}
+
+static inline void async_evt_rx_release_buffer(struct ifx_cat1_uart_data *data, int buffer_type)
+{
+	struct uart_event event = {.type = UART_RX_BUF_RELEASED};
+
+	if (buffer_type == NEXT_BUFFER && !data->async.rx_next_buf) {
+		return;
+	}
+
+	if (buffer_type == CURRENT_BUFFER && !data->async.dma_rx.buf) {
+		return;
+	}
+
+	if (buffer_type == NEXT_BUFFER) {
+		event.data.rx_buf.buf = data->async.rx_next_buf;
+		data->async.rx_next_buf = NULL;
+		data->async.rx_next_buf_len = 0;
+	} else {
+		event.data.rx_buf.buf = data->async.dma_rx.buf;
+		data->async.dma_rx.buf = NULL;
+		data->async.dma_rx.buf_len = 0;
+	}
+
+	if (data->async.cb) {
+		data->async.cb(data->async.uart_dev, &event, data->async.user_data);
+	}
+}
+
+static inline void async_evt_rx_disabled(struct ifx_cat1_uart_data *data)
+{
+	struct uart_event event = {.type = UART_RX_DISABLED};
+
+	data->async.dma_rx.buf = NULL;
+	data->async.dma_rx.buf_len = 0;
+	data->async.dma_rx.offset = 0;
+	data->async.dma_rx.counter = 0;
+
+	if (data->async.cb) {
+		data->async.cb(data->async.uart_dev, &event, data->async.user_data);
+	}
+}
+
+static inline void async_evt_rx_stopped(struct ifx_cat1_uart_data *data,
+					enum uart_rx_stop_reason reason)
+{
+	struct uart_event event = {.type = UART_RX_STOPPED, .data.rx_stop.reason = reason};
+	struct uart_event_rx *rx = &event.data.rx_stop.data;
+	struct dma_status stat;
+
+	if (data->async.dma_rx.buf_len == 0 || data->async.cb == NULL) {
+		return;
+	}
+
+	rx->buf = data->async.dma_rx.buf;
+
+	if (dma_get_status(data->async.dma_rx.dev, data->async.dma_rx.dma_channel, &stat) == 0) {
+		data->async.dma_rx.counter = data->async.dma_rx.buf_len - stat.pending_length;
+	}
+	rx->len = data->async.dma_rx.counter - data->async.dma_rx.offset;
+	rx->offset = data->async.dma_rx.counter;
+
+	data->async.cb(data->async.uart_dev, &event, data->async.user_data);
+}
+
+static int ifx_cat1_uart_async_rx_enable(const struct device *dev, uint8_t *rx_data,
+					 size_t rx_data_size, int32_t timeout)
+{
+	struct ifx_cat1_uart_data *const data = dev->data;
+	struct dma_status dma_status = {0};
+	int err = 0;
+	unsigned int key = irq_lock();
+
+	if (data->async.dma_rx.dev == NULL) {
+		return -ENODEV;
+	}
+
+	if (data->async.dma_rx.buf_len != 0) {
+		return -EBUSY;
+	}
+
+	/* Store information about data buffer need to send */
+	data->async.dma_rx.buf = (uint8_t *)rx_data;
+	data->async.dma_rx.buf_len = rx_data_size;
+	data->async.dma_rx.blk_cfg.block_size = 0;
+	data->async.dma_rx.dma_transmitted_bytes = 0;
+	data->async.dma_rx.timeout = timeout;
+
+	/* Request buffers before enabling rx */
+	async_evt_rx_buf_request(data);
+
+	/* Configure dma to transfer */
+	err = ifx_cat1_uart_async_dma_config_buffer(dev, false);
+	if (err) {
+		LOG_ERR("Error Rx DMA configure (%d)", err);
+		goto unlock;
+	}
+	err = dma_get_status(data->async.dma_rx.dev, data->async.dma_rx.dma_channel, &dma_status);
+	if (err) {
+		return err;
+	}
+
+	if (dma_status.busy) {
+		return -EBUSY;
+	}
+
+	/* Configure timeout */
+	if ((timeout != SYS_FOREVER_US) && (timeout != 0)) {
+		k_work_reschedule(&data->async.dma_rx.timeout_work, K_USEC(timeout));
+	}
+
+unlock:
+	irq_unlock(key);
+	return err;
+}
+
+static void dma_callback_rx_rdy(const struct device *dma_dev, void *arg, uint32_t channel,
+				int status)
+{
+	const struct device *uart_dev = (void *)arg;
+	struct ifx_cat1_uart_data *const data = uart_dev->data;
+	unsigned int key = irq_lock();
+
+	if (status == 0) {
+		/* All data are sent, call user callback */
+
+		k_work_cancel_delayable(&data->async.dma_rx.timeout_work);
+		data->async.dma_rx.counter = data->async.dma_rx.buf_len;
+
+		async_evt_rx_rdy(data);
+		async_evt_rx_release_buffer(data, CURRENT_BUFFER);
+
+		data->async.dma_rx.buf = NULL;
+		data->async.dma_rx.buf_len = 0;
+		data->async.dma_rx.blk_cfg.block_size = 0;
+		data->async.dma_rx.dma_transmitted_bytes = 0;
+
+		if (!data->async.rx_next_buf) {
+			dma_stop(data->async.dma_rx.dev, data->async.dma_rx.dma_channel);
+			async_evt_rx_disabled(data);
+			goto unlock;
+		}
+
+		data->async.dma_rx.buf = data->async.rx_next_buf;
+		data->async.dma_rx.buf_len = data->async.rx_next_buf_len;
+		data->async.dma_rx.offset = 0;
+		data->async.dma_rx.counter = 0;
+		data->async.rx_next_buf = NULL;
+		data->async.rx_next_buf_len = 0;
+
+		ifx_cat1_uart_async_dma_config_buffer(uart_dev, false);
+
+		async_evt_rx_buf_request(data);
+
+		if ((data->async.dma_rx.timeout != SYS_FOREVER_US) &&
+		    (data->async.dma_rx.timeout != 0)) {
+			k_work_reschedule(&data->async.dma_rx.timeout_work,
+					  K_USEC(data->async.dma_rx.timeout));
+		}
+
+	} else {
+		/* DMA error */
+		dma_stop(data->async.dma_rx.dev, data->async.dma_rx.dma_channel);
+
+		async_evt_rx_stopped(data, UART_ERROR_OVERRUN);
+		async_evt_rx_release_buffer(data, CURRENT_BUFFER);
+		async_evt_rx_release_buffer(data, NEXT_BUFFER);
+		async_evt_rx_disabled(data);
+		goto unlock;
+	}
+unlock:
+	irq_unlock(key);
+}
+
+static void ifx_cat1_uart_async_rx_timeout(struct k_work *work)
+{
+
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct ifx_cat1_dma_stream *dma_rx =
+		CONTAINER_OF(dwork, struct ifx_cat1_dma_stream, timeout_work);
+	struct ifx_cat1_uart_async *async =
+		CONTAINER_OF(dma_rx, struct ifx_cat1_uart_async, dma_rx);
+	struct ifx_cat1_uart_data *data = CONTAINER_OF(async, struct ifx_cat1_uart_data, async);
+
+	struct dma_status stat;
+	unsigned int key = irq_lock();
+
+	if (dma_rx->buf_len == 0) {
+		irq_unlock(key);
+		return;
+	}
+	if (dma_get_status(dma_rx->dev, dma_rx->dma_channel, &stat) == 0) {
+		size_t rx_rcv_len = dma_rx->buf_len - stat.pending_length;
+
+		if ((rx_rcv_len > 0) && (rx_rcv_len == dma_rx->counter)) {
+			dma_rx->counter = rx_rcv_len;
+			async_evt_rx_rdy(data);
+		} else {
+			dma_rx->counter = rx_rcv_len;
+		}
+	}
+	irq_unlock(key);
+
+	if ((dma_rx->timeout != SYS_FOREVER_US) && (dma_rx->timeout != 0)) {
+		k_work_reschedule(&dma_rx->timeout_work, K_USEC(dma_rx->timeout));
+	}
+}
+
+static int ifx_cat1_uart_async_rx_disable(const struct device *dev)
+{
+	struct ifx_cat1_uart_data *data = dev->data;
+	struct dma_status stat;
+	unsigned int key;
+
+	k_work_cancel_delayable(&data->async.dma_rx.timeout_work);
+
+	key = irq_lock();
+
+	if (data->async.dma_rx.buf_len == 0) {
+		__ASSERT_NO_MSG(data->async.dma_rx.buf == NULL);
+		irq_unlock(key);
+		return -EINVAL;
+	}
+
+	dma_stop(data->async.dma_rx.dev, data->async.dma_rx.dma_channel);
+
+	if (dma_get_status(data->async.dma_rx.dev, data->async.dma_rx.dma_channel, &stat) == 0) {
+		size_t rx_rcv_len = data->async.dma_rx.buf_len - stat.pending_length;
+
+		if (rx_rcv_len > data->async.dma_rx.offset) {
+			data->async.dma_rx.counter = rx_rcv_len;
+			async_evt_rx_rdy(data);
+		}
+	}
+	async_evt_rx_release_buffer(data, CURRENT_BUFFER);
+	async_evt_rx_release_buffer(data, NEXT_BUFFER);
+	async_evt_rx_disabled(data);
+
+	irq_unlock(key);
+	return 0;
+}
+
+static int ifx_cat1_uart_async_rx_buf_rsp(const struct device *dev, uint8_t *buf, size_t len)
+{
+	struct ifx_cat1_uart_data *data = dev->data;
+	unsigned int key;
+	int ret = 0;
+
+	key = irq_lock();
+
+	if (data->async.dma_rx.buf_len == 0U) {
+		ret = -EACCES;
+		goto unlock;
+	}
+
+	if (data->async.rx_next_buf_len != 0U) {
+		ret = -EBUSY;
+		goto unlock;
+	}
+
+	data->async.rx_next_buf = buf;
+	data->async.rx_next_buf_len = len;
+
+unlock:
+	irq_unlock(key);
+	return ret;
+}
+
+#endif /*CONFIG_UART_ASYNC_API */
 
 static int ifx_cat1_uart_init(const struct device *dev)
 {
@@ -437,11 +934,7 @@ static int ifx_cat1_uart_init(const struct device *dev)
 		.resource = &data->hw_resource,
 		.config = &_cyhal_uart_default_config,
 		.clock = &data->clock,
-		.gpios = {
-			.pin_tx  = NC,
-			.pin_rts = NC,
-			.pin_cts = NC,
-		},
+		.gpios = {.pin_tx = NC, .pin_rts = NC, .pin_cts = NC},
 	};
 
 	/* Dedicate SCB HW resource */
@@ -479,6 +972,71 @@ static int ifx_cat1_uart_init(const struct device *dev)
 	data->obj.is_clock_owned = true;
 	ret = ifx_cat1_uart_configure(dev, &config->dt_cfg);
 
+#ifdef CONFIG_UART_ASYNC_API
+	data->async.uart_dev = dev;
+	if (data->async.dma_rx.dev != NULL) {
+		cyhal_source_t uart_source;
+
+		if (!device_is_ready(data->async.dma_rx.dev)) {
+			return -ENODEV;
+		}
+
+		data->async.dma_rx.blk_cfg.source_address =
+			(uint32_t)(&config->reg_addr->RX_FIFO_RD);
+		data->async.dma_rx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
+		data->async.dma_rx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;
+		data->async.dma_rx.dma_cfg.head_block = &data->async.dma_rx.blk_cfg;
+		data->async.dma_rx.dma_cfg.user_data = (void *)dev;
+		data->async.dma_rx.dma_cfg.dma_callback = dma_callback_rx_rdy;
+
+		if (cyhal_uart_enable_output(&data->obj,
+					     CYHAL_UART_OUTPUT_TRIGGER_RX_FIFO_LEVEL_REACHED,
+					     &uart_source)) {
+			return -ENOTSUP;
+		}
+
+		if (ifx_cat1_dma_ex_connect_digital(data->async.dma_rx.dev,
+						    data->async.dma_rx.dma_channel, uart_source,
+						    CYHAL_DMA_INPUT_TRIGGER_ALL_ELEMENTS)) {
+			return -ENOTSUP;
+		}
+
+		Cy_SCB_SetRxFifoLevel(config->reg_addr, 0);
+	}
+
+	if (data->async.dma_tx.dev != NULL) {
+		cyhal_source_t uart_source;
+
+		if (!device_is_ready(data->async.dma_tx.dev)) {
+			return -ENODEV;
+		}
+
+		data->async.dma_tx.blk_cfg.dest_address = (uint32_t)(&config->reg_addr->TX_FIFO_WR);
+		data->async.dma_tx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
+		data->async.dma_tx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
+		data->async.dma_tx.dma_cfg.head_block = &data->async.dma_tx.blk_cfg;
+		data->async.dma_tx.dma_cfg.user_data = (void *)dev;
+		data->async.dma_tx.dma_cfg.dma_callback = dma_callback_tx_done;
+
+		if (cyhal_uart_enable_output(&data->obj,
+					     CYHAL_UART_OUTPUT_TRIGGER_TX_FIFO_LEVEL_REACHED,
+					     &uart_source)) {
+			return -ENOTSUP;
+		}
+
+		if (ifx_cat1_dma_ex_connect_digital(data->async.dma_tx.dev,
+						    data->async.dma_tx.dma_channel, uart_source,
+						    CYHAL_DMA_INPUT_TRIGGER_ALL_ELEMENTS)) {
+			return -ENOTSUP;
+		}
+		Cy_SCB_SetTxFifoLevel(config->reg_addr, 1);
+	}
+
+	k_work_init_delayable(&data->async.dma_tx.timeout_work, ifx_cat1_uart_async_tx_timeout);
+	k_work_init_delayable(&data->async.dma_rx.timeout_work, ifx_cat1_uart_async_rx_timeout);
+
+#endif /* CONFIG_UART_ASYNC_API */
+
 	return ret;
 }
 
@@ -507,29 +1065,61 @@ static DEVICE_API(uart, ifx_cat1_uart_driver_api) = {
 	.irq_is_pending = ifx_cat1_uart_irq_is_pending,
 	.irq_update = ifx_cat1_uart_irq_update,
 	.irq_callback_set = ifx_cat1_uart_irq_callback_set,
-#endif    /* CONFIG_UART_INTERRUPT_DRIVEN */
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+
+#if CONFIG_UART_ASYNC_API
+	.callback_set = ifx_cat1_uart_async_callback_set,
+	.tx = ifx_cat1_uart_async_tx,
+	.rx_enable = ifx_cat1_uart_async_rx_enable,
+	.tx_abort = ifx_cat1_uart_async_tx_abort,
+	.rx_buf_rsp = ifx_cat1_uart_async_rx_buf_rsp,
+	.rx_disable = ifx_cat1_uart_async_rx_disable,
+#endif /*CONFIG_UART_ASYNC_API*/
+
 };
 
-#define INFINEON_CAT1_UART_INIT(n)							     \
-	PINCTRL_DT_INST_DEFINE(n);							     \
-	static struct ifx_cat1_uart_data ifx_cat1_uart##n##_data;			     \
-											     \
-	static struct ifx_cat1_uart_config ifx_cat1_uart##n##_cfg = {			     \
-		.dt_cfg.baudrate = DT_INST_PROP(n, current_speed),			     \
-		.dt_cfg.parity = DT_INST_ENUM_IDX_OR(n, parity, UART_CFG_PARITY_NONE),	     \
-		.dt_cfg.stop_bits = DT_INST_ENUM_IDX_OR(n, stop_bits, UART_CFG_STOP_BITS_1), \
-		.dt_cfg.data_bits = DT_INST_ENUM_IDX_OR(n, data_bits, UART_CFG_DATA_BITS_8), \
-		.dt_cfg.flow_ctrl = DT_INST_PROP(n, hw_flow_control),			     \
-		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),				     \
-		.reg_addr = (CySCB_Type *)DT_INST_REG_ADDR(n),				     \
-		.irq_priority = DT_INST_IRQ(n, priority)				     \
-	};										     \
-											     \
-	DEVICE_DT_INST_DEFINE(n,							     \
-			      ifx_cat1_uart_init, NULL,					     \
-			      &ifx_cat1_uart##n##_data,					     \
-			      &ifx_cat1_uart##n##_cfg, PRE_KERNEL_1,			     \
-			      CONFIG_SERIAL_INIT_PRIORITY,				     \
+#if defined(CONFIG_UART_ASYNC_API)
+#define UART_DMA_CHANNEL_INIT(index, dir, ch_dir, src_data_size, dst_data_size)                    \
+	.dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(index, dir)),                               \
+	.dma_channel = DT_INST_DMAS_CELL_BY_NAME(index, dir, channel),                             \
+	.dma_cfg = {                                                                               \
+		.channel_direction = ch_dir,                                                       \
+		.source_data_size = src_data_size,                                                 \
+		.dest_data_size = dst_data_size,                                                   \
+		.source_burst_length = 0,                                                          \
+		.dest_burst_length = 0,                                                            \
+		.block_count = 1,                                                                  \
+		.complete_callback_en = 0,                                                         \
+	},
+
+#define UART_DMA_CHANNEL(index, dir, ch_dir, src_data_size, dst_data_size)                         \
+	.async.dma_##dir = {COND_CODE_1(                                                           \
+		DT_INST_DMAS_HAS_NAME(index, dir),                                                 \
+		(UART_DMA_CHANNEL_INIT(index, dir, ch_dir, src_data_size, dst_data_size)),         \
+		(NULL))},
+
+#else
+#define UART_DMA_CHANNEL(index, dir, ch_dir, src_data_size, dst_data_size)
+#endif /* CONFIG_UART_ASYNC_API */
+
+#define INFINEON_CAT1_UART_INIT(n)                                                                 \
+	PINCTRL_DT_INST_DEFINE(n);                                                                 \
+	static struct ifx_cat1_uart_data ifx_cat1_uart##n##_data = {                               \
+		UART_DMA_CHANNEL(n, tx, MEMORY_TO_PERIPHERAL, 1, 1)                                \
+			UART_DMA_CHANNEL(n, rx, PERIPHERAL_TO_MEMORY, 1, 1)};                      \
+                                                                                                   \
+	static struct ifx_cat1_uart_config ifx_cat1_uart##n##_cfg = {                              \
+		.dt_cfg.baudrate = DT_INST_PROP(n, current_speed),                                 \
+		.dt_cfg.parity = DT_INST_ENUM_IDX(n, parity),             \
+		.dt_cfg.stop_bits = DT_INST_ENUM_IDX(n, stop_bits),       \
+		.dt_cfg.data_bits = DT_INST_ENUM_IDX(n, data_bits),       \
+		.dt_cfg.flow_ctrl = DT_INST_PROP(n, hw_flow_control),                              \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                         \
+		.reg_addr = (CySCB_Type *)DT_INST_REG_ADDR(n),                                     \
+		.irq_priority = DT_INST_IRQ(n, priority)};                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, &ifx_cat1_uart_init, NULL, &ifx_cat1_uart##n##_data,              \
+			      &ifx_cat1_uart##n##_cfg, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY,  \
 			      &ifx_cat1_uart_driver_api);
 
 DT_INST_FOREACH_STATUS_OKAY(INFINEON_CAT1_UART_INIT)
diff --git a/drivers/serial/uart_intel_lw.c b/drivers/serial/uart_intel_lw.c
index 64c0d0a6dd1..786360c2050 100644
--- a/drivers/serial/uart_intel_lw.c
+++ b/drivers/serial/uart_intel_lw.c
@@ -994,12 +994,9 @@ static struct uart_intel_lw_device_data uart_intel_lw_dev_data_##n = {      \
 	.uart_cfg =                                                         \
 	{                                                                   \
 			.baudrate = DT_INST_PROP(n, current_speed),         \
-			.parity = DT_INST_ENUM_IDX_OR(n, parity,            \
-						 UART_CFG_PARITY_NONE),     \
-			.stop_bits = DT_INST_ENUM_IDX_OR(n, stop_bits,      \
-						 UART_CFG_STOP_BITS_1),     \
-			.data_bits = DT_INST_ENUM_IDX_OR(n, data_bits,      \
-						 UART_CFG_DATA_BITS_8),     \
+			.parity = DT_INST_ENUM_IDX(n, parity),              \
+			.stop_bits = DT_INST_ENUM_IDX(n, stop_bits),        \
+			.data_bits = DT_INST_ENUM_IDX(n, data_bits),        \
 			.flow_ctrl = DT_INST_PROP(n, hw_flow_control) ?     \
 				UART_CFG_FLOW_CTRL_RTS_CTS :                \
 				UART_CFG_FLOW_CTRL_NONE,                    \
diff --git a/drivers/serial/uart_ite_it51xxx.c b/drivers/serial/uart_ite_it51xxx.c
new file mode 100644
index 00000000000..a68e6c1a15e
--- /dev/null
+++ b/drivers/serial/uart_ite_it51xxx.c
@@ -0,0 +1,163 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ite_it51xxx_uart
+
+#include <soc.h>
+#include <soc_dt.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/interrupt_controller/wuc_ite_it51xxx.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/uart.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/pm/device.h>
+#include <zephyr/pm/policy.h>
+
+LOG_MODULE_REGISTER(uart_ite_it51xxx, CONFIG_UART_LOG_LEVEL);
+
+struct it51xxx_uart_wuc_map_cfg {
+	/* WUC control device structure */
+	const struct device *wucs;
+	/* WUC pin mask */
+	uint8_t mask;
+};
+
+struct uart_it51xxx_config {
+	/* UART wake-up input source configuration list */
+	const struct it51xxx_uart_wuc_map_cfg *wuc_map_list;
+	const struct device *clk_dev;
+	/* clock configuration */
+	struct ite_clk_cfg clk_cfg;
+	/* UART interrupt */
+	uint8_t irq;
+};
+
+struct uart_it51xxx_data {
+#ifdef CONFIG_UART_CONSOLE_INPUT_EXPIRED
+	struct k_work_delayable rx_refresh_timeout_work;
+#endif
+};
+
+static void it51xxx_uart_wui_isr(const void *arg)
+{
+	const struct device *dev = arg;
+	const struct uart_it51xxx_config *const config = dev->config;
+
+	/* Disable interrupts on UART RX pin to avoid repeated interrupts. */
+	irq_disable(config->irq);
+	/* W/C wakeup interrupt status of UART pin */
+	it51xxx_wuc_clear_status(config->wuc_map_list[0].wucs, config->wuc_map_list[0].mask);
+
+	/* Refresh console expired time if got UART Rx wake-up event */
+#ifdef CONFIG_UART_CONSOLE_INPUT_EXPIRED
+	struct uart_it51xxx_data *data = dev->data;
+	k_timeout_t delay = K_MSEC(CONFIG_UART_CONSOLE_INPUT_EXPIRED_TIMEOUT);
+
+	/*
+	 * The pm state of it51xxx chip only supports standby, so here we
+	 * can directly set the constraint for standby.
+	 */
+	pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
+	k_work_reschedule(&data->rx_refresh_timeout_work, delay);
+#endif
+}
+
+static inline int uart_it51xxx_pm_action(const struct device *dev, enum pm_device_action action)
+{
+	const struct uart_it51xxx_config *const config = dev->config;
+
+	switch (action) {
+	/* Next device power state is in active. */
+	case PM_DEVICE_ACTION_RESUME:
+		/* Nothing to do. */
+		break;
+	/* Next device power state is deep doze mode */
+	case PM_DEVICE_ACTION_SUSPEND:
+		/* W/C wake-up interrupt status of UART pin */
+		it51xxx_wuc_clear_status(config->wuc_map_list[0].wucs,
+					 config->wuc_map_list[0].mask);
+		/* W/C interrupt status of UART pin */
+		ite_intc_isr_clear(config->irq);
+		/* Enable UART interrupt */
+		irq_enable(config->irq);
+
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_UART_CONSOLE_INPUT_EXPIRED
+static void uart_it51xxx_rx_refresh_timeout(struct k_work *work)
+{
+	ARG_UNUSED(work);
+
+	pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
+}
+#endif
+
+static int uart_it51xxx_init(const struct device *dev)
+{
+	const struct uart_it51xxx_config *const config = dev->config;
+	int ret;
+
+	/* Enable clock to specified peripheral */
+	ret = clock_control_on(config->clk_dev, (clock_control_subsys_t *)&config->clk_cfg);
+	if (ret < 0) {
+		LOG_ERR("Turn on clock fail %d", ret);
+		return ret;
+	}
+
+	/* Select wakeup interrupt falling-edge triggered of UART pin */
+	it51xxx_wuc_set_polarity(config->wuc_map_list[0].wucs, config->wuc_map_list[0].mask,
+				 WUC_TYPE_EDGE_FALLING);
+	/* W/C wakeup interrupt status of UART pin */
+	it51xxx_wuc_clear_status(config->wuc_map_list[0].wucs, config->wuc_map_list[0].mask);
+	/* Enable wakeup interrupt of UART pin */
+	it51xxx_wuc_enable(config->wuc_map_list[0].wucs, config->wuc_map_list[0].mask);
+
+	/*
+	 * We need to configure UART Rx interrupt as wakeup source and initialize
+	 * a delayable work for console expired time.
+	 */
+#ifdef CONFIG_UART_CONSOLE_INPUT_EXPIRED
+	struct uart_it51xxx_data *data = dev->data;
+
+	k_work_init_delayable(&data->rx_refresh_timeout_work, uart_it51xxx_rx_refresh_timeout);
+#endif
+	/*
+	 * When the system enters deep doze, all clocks are gated only the
+	 * 32.768k clock is active. We need to wakeup EC by configuring
+	 * UART Rx interrupt as a wakeup source. When the interrupt of UART
+	 * Rx falling, EC will be woken.
+	 */
+	irq_connect_dynamic(config->irq, 0, it51xxx_uart_wui_isr, dev, 0);
+
+	return 0;
+}
+
+#define UART_ITE_IT51XXX_INIT(inst)                                                                \
+	static const struct it51xxx_uart_wuc_map_cfg                                               \
+		it51xxx_uart_wuc_##inst[IT8XXX2_DT_INST_WUCCTRL_LEN(inst)] =                       \
+			IT8XXX2_DT_WUC_ITEMS_LIST(inst);                                           \
+	static struct uart_it51xxx_data uart_it51xxx_data_##inst;                                  \
+	static const struct uart_it51xxx_config uart_it51xxx_cfg_##inst = {                        \
+		.wuc_map_list = it51xxx_uart_wuc_##inst,                                           \
+		.clk_dev = DEVICE_DT_GET(DT_INST_PHANDLE(inst, clocks)),                           \
+		.clk_cfg = {.ctrl = DT_INST_CLOCKS_CELL(inst, ctrl),                               \
+			    .bits = DT_INST_CLOCKS_CELL(inst, bits)},                              \
+		.irq = DT_INST_IRQN(inst),                                                         \
+	};                                                                                         \
+	PM_DEVICE_DT_INST_DEFINE(inst, uart_it51xxx_pm_action);                                    \
+	DEVICE_DT_INST_DEFINE(inst, uart_it51xxx_init, PM_DEVICE_DT_INST_GET(inst),                \
+			      &uart_it51xxx_data_##inst, &uart_it51xxx_cfg_##inst, PRE_KERNEL_1,   \
+			      CONFIG_SERIAL_INIT_PRIORITY, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(UART_ITE_IT51XXX_INIT)
diff --git a/drivers/serial/uart_max32.c b/drivers/serial/uart_max32.c
index c09cb0b09ba..2df1025ac25 100644
--- a/drivers/serial/uart_max32.c
+++ b/drivers/serial/uart_max32.c
@@ -4,6 +4,10 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#ifdef CONFIG_UART_ASYNC_API
+#include <zephyr/drivers/dma.h>
+#include <wrap_max32_dma.h>
+#endif
 #include <zephyr/drivers/pinctrl.h>
 #include <zephyr/drivers/uart.h>
 #include <zephyr/kernel.h>
@@ -16,16 +20,61 @@
 
 LOG_MODULE_REGISTER(uart_max32, CONFIG_UART_LOG_LEVEL);
 
+#ifdef CONFIG_UART_ASYNC_API
+struct max32_uart_dma_config {
+	const struct device *dev;
+	const uint32_t channel;
+	const uint32_t slot;
+};
+#endif /* CONFIG_UART_ASYNC_API */
+
 struct max32_uart_config {
 	mxc_uart_regs_t *regs;
 	const struct pinctrl_dev_config *pctrl;
 	const struct device *clock;
 	struct max32_perclk perclk;
 	struct uart_config uart_conf;
-#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN) || defined(CONFIG_UART_ASYNC_API)
 	uart_irq_config_func_t irq_config_func;
-#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API */
+#ifdef CONFIG_UART_ASYNC_API
+	const struct max32_uart_dma_config tx_dma;
+	const struct max32_uart_dma_config rx_dma;
+#endif /* CONFIG_UART_ASYNC_API */
+};
+
+#ifdef CONFIG_UART_ASYNC_API
+#define MAX32_UART_TX_CACHE_NUM 2
+struct max32_uart_async_tx {
+	const uint8_t *buf;
+	const uint8_t *src;
+	size_t len;
+	uint8_t cache[MAX32_UART_TX_CACHE_NUM][CONFIG_UART_TX_CACHE_LEN];
+	uint8_t cache_id;
+	struct dma_block_config dma_blk;
+	int32_t timeout;
+	struct k_work_delayable timeout_work;
+};
+
+struct max32_uart_async_rx {
+	uint8_t *buf;
+	size_t len;
+	size_t offset;
+	size_t counter;
+	uint8_t *next_buf;
+	size_t next_len;
+	int32_t timeout;
+	struct k_work_delayable timeout_work;
+};
+
+struct max32_uart_async_data {
+	const struct device *uart_dev;
+	struct max32_uart_async_tx tx;
+	struct max32_uart_async_rx rx;
+	uart_callback_t cb;
+	void *user_data;
 };
+#endif
 
 struct max32_uart_data {
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
@@ -33,6 +82,9 @@ struct max32_uart_data {
 	void *cb_data;                    /* Interrupt callback arg */
 	uint32_t flags;                   /* Cached interrupt flags */
 	uint32_t status;                  /* Cached status flags */
+#endif
+#ifdef CONFIG_UART_ASYNC_API
+	struct max32_uart_async_data async;
 #endif
 	struct uart_config conf; /* baudrate, stopbits, ... */
 };
@@ -41,6 +93,10 @@ struct max32_uart_data {
 static void uart_max32_isr(const struct device *dev);
 #endif
 
+#ifdef CONFIG_UART_ASYNC_API
+static int uart_max32_tx_dma_load(const struct device *dev, uint8_t *buf, size_t len);
+#endif
+
 static void api_poll_out(const struct device *dev, unsigned char c)
 {
 	const struct max32_uart_config *cfg = dev->config;
@@ -207,11 +263,19 @@ static int api_config_get(const struct device *dev, struct uart_config *uart_cfg
 
 #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
 
+#ifdef CONFIG_UART_ASYNC_API
+static void uart_max32_async_tx_timeout(struct k_work *work);
+static void uart_max32_async_rx_timeout(struct k_work *work);
+#endif /* CONFIG_UART_ASYNC_API */
+
 static int uart_max32_init(const struct device *dev)
 {
 	int ret;
 	const struct max32_uart_config *const cfg = dev->config;
 	mxc_uart_regs_t *regs = cfg->regs;
+#ifdef CONFIG_UART_ASYNC_API
+	struct max32_uart_data *data = dev->data;
+#endif
 
 	if (!device_is_ready(cfg->clock)) {
 		LOG_ERR("Clock control device not ready");
@@ -229,6 +293,12 @@ static int uart_max32_init(const struct device *dev)
 		return ret;
 	}
 
+	ret = Wrap_MXC_UART_SetClockSource(regs, cfg->perclk.clk_src);
+	if (ret != 0) {
+		LOG_ERR("Cannot set UART clock source");
+		return ret;
+	}
+
 	ret = pinctrl_apply_state(cfg->pctrl, PINCTRL_STATE_DEFAULT);
 	if (ret) {
 		return ret;
@@ -244,12 +314,20 @@ static int uart_max32_init(const struct device *dev)
 		return ret;
 	}
 
-#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN) || defined(CONFIG_UART_ASYNC_API)
 	/* Clear any pending UART RX/TX interrupts */
 	MXC_UART_ClearFlags(regs, (ADI_MAX32_UART_INT_RX | ADI_MAX32_UART_INT_TX));
 	cfg->irq_config_func(dev);
 #endif
 
+#ifdef CONFIG_UART_ASYNC_API
+	data->async.uart_dev = dev;
+	k_work_init_delayable(&data->async.tx.timeout_work, uart_max32_async_tx_timeout);
+	k_work_init_delayable(&data->async.rx.timeout_work, uart_max32_async_rx_timeout);
+	data->async.rx.len = 0;
+	data->async.rx.offset = 0;
+#endif
+
 	return ret;
 }
 
@@ -304,21 +382,7 @@ static int api_irq_tx_ready(const struct device *dev)
 	uint32_t inten = Wrap_MXC_UART_GetRegINTEN(cfg->regs);
 
 	return ((inten & (ADI_MAX32_UART_INT_TX | ADI_MAX32_UART_INT_TX_OEM)) &&
-		!(data->status & MXC_F_UART_STATUS_TX_FULL));
-}
-
-static void api_irq_rx_enable(const struct device *dev)
-{
-	const struct max32_uart_config *cfg = dev->config;
-
-	MXC_UART_EnableInt(cfg->regs, ADI_MAX32_UART_INT_RX);
-}
-
-static void api_irq_rx_disable(const struct device *dev)
-{
-	const struct max32_uart_config *cfg = dev->config;
-
-	MXC_UART_DisableInt(cfg->regs, ADI_MAX32_UART_INT_RX);
+		!(data->status & ADI_MAX32_UART_STATUS_TX_FULL));
 }
 
 static int api_irq_tx_complete(const struct device *dev)
@@ -378,22 +442,527 @@ static int api_irq_update(const struct device *dev)
 static void api_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
 				 void *cb_data)
 {
-	struct max32_uart_data *const data = dev->data;
+	struct max32_uart_data *const dev_data = dev->data;
 
-	data->cb = cb;
-	data->cb_data = cb_data;
+	dev_data->cb = cb;
+	dev_data->cb_data = cb_data;
+}
+
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN) || defined(CONFIG_UART_ASYNC_API)
+static void api_irq_rx_enable(const struct device *dev)
+{
+	const struct max32_uart_config *cfg = dev->config;
+
+	MXC_UART_EnableInt(cfg->regs, ADI_MAX32_UART_INT_RX);
+}
+
+static void api_irq_rx_disable(const struct device *dev)
+{
+	const struct max32_uart_config *cfg = dev->config;
+
+	MXC_UART_DisableInt(cfg->regs, ADI_MAX32_UART_INT_RX);
 }
 
 static void uart_max32_isr(const struct device *dev)
 {
 	struct max32_uart_data *data = dev->data;
+	const struct max32_uart_config *cfg = dev->config;
+	uint32_t intfl;
 
+	intfl = MXC_UART_GetFlags(cfg->regs);
+
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
 	if (data->cb) {
 		data->cb(dev, data->cb_data);
 	}
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+
+#ifdef CONFIG_UART_ASYNC_API
+	if (data->async.rx.timeout != SYS_FOREVER_US && data->async.rx.timeout != 0 &&
+	    (intfl & ADI_MAX32_UART_INT_RX)) {
+		k_work_reschedule(&data->async.rx.timeout_work, K_USEC(data->async.rx.timeout));
+	}
+#endif /* CONFIG_UART_ASYNC_API */
+
+	/* Clear RX/TX interrupts flag after cb is called */
+	MXC_UART_ClearFlags(cfg->regs, intfl);
 }
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API */
 
-#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+#if defined(CONFIG_UART_ASYNC_API)
+
+static inline void async_timer_start(struct k_work_delayable *work, int32_t timeout)
+{
+	if ((timeout != SYS_FOREVER_US) && (timeout != 0)) {
+		k_work_reschedule(work, K_USEC(timeout));
+	}
+}
+
+static void async_user_callback(const struct device *dev, struct uart_event *evt)
+{
+	const struct max32_uart_data *data = dev->data;
+
+	if (data->async.cb) {
+		data->async.cb(dev, evt, data->async.user_data);
+	}
+}
+
+static uint32_t load_tx_cache(const uint8_t *src, size_t len, uint8_t *dest)
+{
+	memcpy(dest, src, MIN(len, CONFIG_UART_TX_CACHE_LEN));
+
+	return MIN(len, CONFIG_UART_TX_CACHE_LEN);
+}
+
+static void uart_max32_async_tx_callback(const struct device *dma_dev, void *user_data,
+					 uint32_t channel, int status)
+{
+	const struct device *dev = user_data;
+	const struct max32_uart_config *config = dev->config;
+	struct max32_uart_data *data = dev->data;
+	struct max32_uart_async_tx *tx = &data->async.tx;
+	struct dma_status dma_stat;
+	int ret;
+
+	unsigned int key = irq_lock();
+
+	dma_get_status(config->tx_dma.dev, config->tx_dma.channel, &dma_stat);
+	/* Skip callback if channel is still busy */
+	if (dma_stat.busy) {
+		irq_unlock(key);
+		return;
+	}
+
+	k_work_cancel_delayable(&tx->timeout_work);
+	Wrap_MXC_UART_DisableTxDMA(config->regs);
+
+	irq_unlock(key);
+
+	tx->len -= tx->dma_blk.block_size;
+	if (tx->len > 0) {
+		tx->cache_id = !(tx->cache_id);
+		ret = uart_max32_tx_dma_load(dev, tx->cache[tx->cache_id],
+					     MIN(tx->len, CONFIG_UART_TX_CACHE_LEN));
+		if (ret < 0) {
+			LOG_ERR("Error configuring Tx DMA (%d)", ret);
+			return;
+		}
+
+		ret = dma_start(config->tx_dma.dev, config->tx_dma.channel);
+		if (ret < 0) {
+			LOG_ERR("Error starting Tx DMA (%d)", ret);
+			return;
+		}
+
+		async_timer_start(&tx->timeout_work, tx->timeout);
+
+		Wrap_MXC_UART_SetTxDMALevel(config->regs, 2);
+		Wrap_MXC_UART_EnableTxDMA(config->regs);
+
+		/* Load next chunk as well */
+		if (tx->len > CONFIG_UART_TX_CACHE_LEN) {
+			tx->src += load_tx_cache(tx->src, tx->len - CONFIG_UART_TX_CACHE_LEN,
+						 tx->cache[!(tx->cache_id)]);
+		}
+	} else {
+		struct uart_event tx_done = {
+			.type = status == 0 ? UART_TX_DONE : UART_TX_ABORTED,
+			.data.tx.buf = tx->buf,
+			.data.tx.len = tx->len,
+		};
+		async_user_callback(dev, &tx_done);
+	}
+}
+
+static int uart_max32_tx_dma_load(const struct device *dev, uint8_t *buf, size_t len)
+{
+	int ret;
+	const struct max32_uart_config *config = dev->config;
+	struct max32_uart_data *data = dev->data;
+	struct dma_config dma_cfg = {0};
+	struct dma_block_config *dma_blk = &data->async.tx.dma_blk;
+
+	dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
+	dma_cfg.dma_callback = uart_max32_async_tx_callback;
+	dma_cfg.user_data = (void *)dev;
+	dma_cfg.dma_slot = config->tx_dma.slot;
+	dma_cfg.block_count = 1;
+	dma_cfg.source_data_size = 1U;
+	dma_cfg.source_burst_length = 1U;
+	dma_cfg.dest_data_size = 1U;
+	dma_cfg.head_block = dma_blk;
+	dma_blk->block_size = len;
+	dma_blk->source_address = (uint32_t)buf;
+
+	ret = dma_config(config->tx_dma.dev, config->tx_dma.channel, &dma_cfg);
+	if (ret < 0) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static int api_callback_set(const struct device *dev, uart_callback_t callback, void *user_data)
+{
+	struct max32_uart_data *data = dev->data;
+
+	data->async.cb = callback;
+	data->async.user_data = user_data;
+
+	return 0;
+}
+
+static int api_tx(const struct device *dev, const uint8_t *buf, size_t len, int32_t timeout)
+{
+	struct max32_uart_data *data = dev->data;
+	const struct max32_uart_config *config = dev->config;
+	struct dma_status dma_stat;
+	int ret;
+	bool use_cache = false;
+	unsigned int key = irq_lock();
+
+	if (config->tx_dma.channel == 0xFF) {
+		LOG_ERR("Tx DMA channel is not configured");
+		ret = -ENOTSUP;
+		goto unlock;
+	}
+
+	ret = dma_get_status(config->tx_dma.dev, config->tx_dma.channel, &dma_stat);
+	if (ret < 0 || dma_stat.busy) {
+		LOG_ERR("DMA Tx %s", ret < 0 ? "error" : "busy");
+		irq_unlock(key);
+		return ret < 0 ? ret : -EBUSY;
+	}
+
+	data->async.tx.buf = buf;
+	data->async.tx.len = len;
+	data->async.tx.src = data->async.tx.buf;
+
+	if (((uint32_t)buf < MXC_SRAM_MEM_BASE) ||
+	    (((uint32_t)buf + len) > (MXC_SRAM_MEM_BASE + MXC_SRAM_MEM_SIZE))) {
+		use_cache = true;
+		len = load_tx_cache(data->async.tx.src, MIN(len, CONFIG_UART_TX_CACHE_LEN),
+				    data->async.tx.cache[0]);
+		data->async.tx.src += len;
+		data->async.tx.cache_id = 0;
+	}
+
+	ret = uart_max32_tx_dma_load(dev, use_cache ? data->async.tx.cache[0] : ((uint8_t *)buf),
+				     len);
+	if (ret < 0) {
+		LOG_ERR("Error configuring Tx DMA (%d)", ret);
+		goto unlock;
+	}
+
+	ret = dma_start(config->tx_dma.dev, config->tx_dma.channel);
+	if (ret < 0) {
+		LOG_ERR("Error starting Tx DMA (%d)", ret);
+		goto unlock;
+	}
+
+	data->async.tx.timeout = timeout;
+	async_timer_start(&data->async.tx.timeout_work, timeout);
+
+	Wrap_MXC_UART_SetTxDMALevel(config->regs, 2);
+	Wrap_MXC_UART_EnableTxDMA(config->regs);
+
+unlock:
+	irq_unlock(key);
+
+	return ret;
+}
+
+static int api_tx_abort(const struct device *dev)
+{
+	int ret;
+	struct max32_uart_data *data = dev->data;
+	const struct max32_uart_config *config = dev->config;
+	struct dma_status dma_stat;
+	size_t bytes_sent;
+
+	unsigned int key = irq_lock();
+
+	k_work_cancel_delayable(&data->async.tx.timeout_work);
+
+	Wrap_MXC_UART_DisableTxDMA(config->regs);
+
+	ret = dma_get_status(config->tx_dma.dev, config->tx_dma.channel, &dma_stat);
+	if (!dma_stat.busy) {
+		irq_unlock(key);
+		return 0;
+	}
+
+	bytes_sent = (ret == 0) ? (data->async.tx.len - dma_stat.pending_length) : 0;
+
+	ret = dma_stop(config->tx_dma.dev, config->tx_dma.channel);
+
+	irq_unlock(key);
+
+	if (ret == 0) {
+		struct uart_event tx_aborted = {
+			.type = UART_TX_ABORTED,
+			.data.tx.buf = data->async.tx.buf,
+			.data.tx.len = bytes_sent,
+		};
+		async_user_callback(dev, &tx_aborted);
+	}
+
+	return 0;
+}
+
+static void uart_max32_async_tx_timeout(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct max32_uart_async_tx *tx =
+		CONTAINER_OF(dwork, struct max32_uart_async_tx, timeout_work);
+	struct max32_uart_async_data *async = CONTAINER_OF(tx, struct max32_uart_async_data, tx);
+	struct max32_uart_data *data = CONTAINER_OF(async, struct max32_uart_data, async);
+
+	api_tx_abort(data->async.uart_dev);
+}
+
+static int api_rx_disable(const struct device *dev)
+{
+	struct max32_uart_data *data = dev->data;
+	const struct max32_uart_config *config = dev->config;
+	int ret;
+	unsigned int key = irq_lock();
+
+	k_work_cancel_delayable(&data->async.rx.timeout_work);
+
+	Wrap_MXC_UART_DisableRxDMA(config->regs);
+
+	ret = dma_stop(config->rx_dma.dev, config->rx_dma.channel);
+	if (ret) {
+		LOG_ERR("Error stopping Rx DMA (%d)", ret);
+		irq_unlock(key);
+		return ret;
+	}
+
+	api_irq_rx_disable(dev);
+
+	irq_unlock(key);
+
+	/* Release current buffer event */
+	struct uart_event rel_event = {
+		.type = UART_RX_BUF_RELEASED,
+		.data.rx_buf.buf = data->async.rx.buf,
+	};
+	async_user_callback(dev, &rel_event);
+
+	/* Disable RX event */
+	struct uart_event rx_disabled = {.type = UART_RX_DISABLED};
+
+	async_user_callback(dev, &rx_disabled);
+
+	data->async.rx.buf = NULL;
+	data->async.rx.len = 0;
+	data->async.rx.counter = 0;
+	data->async.rx.offset = 0;
+
+	if (data->async.rx.next_buf) {
+		/* Release next buffer event */
+		struct uart_event next_rel_event = {
+			.type = UART_RX_BUF_RELEASED,
+			.data.rx_buf.buf = data->async.rx.next_buf,
+		};
+		async_user_callback(dev, &next_rel_event);
+		data->async.rx.next_buf = NULL;
+		data->async.rx.next_len = 0;
+	}
+
+	return 0;
+}
+
+static void uart_max32_async_rx_callback(const struct device *dma_dev, void *user_data,
+					 uint32_t channel, int status)
+{
+	const struct device *dev = user_data;
+	const struct max32_uart_config *config = dev->config;
+	struct max32_uart_data *data = dev->data;
+	struct max32_uart_async_data *async = &data->async;
+	struct dma_status dma_stat;
+	size_t total_rx;
+
+	unsigned int key = irq_lock();
+
+	dma_get_status(config->rx_dma.dev, config->rx_dma.channel, &dma_stat);
+
+	if (dma_stat.pending_length > 0) {
+		irq_unlock(key);
+		return;
+	}
+
+	total_rx = async->rx.len - dma_stat.pending_length;
+
+	api_irq_rx_disable(dev);
+
+	irq_unlock(key);
+
+	if (total_rx > async->rx.offset) {
+		async->rx.counter = total_rx - async->rx.offset;
+		struct uart_event rdy_event = {
+			.type = UART_RX_RDY,
+			.data.rx.buf = async->rx.buf,
+			.data.rx.len = async->rx.counter,
+			.data.rx.offset = async->rx.offset,
+		};
+		async_user_callback(dev, &rdy_event);
+	}
+
+	if (async->rx.next_buf) {
+		async->rx.offset = 0;
+		async->rx.counter = 0;
+
+		struct uart_event rel_event = {
+			.type = UART_RX_BUF_RELEASED,
+			.data.rx_buf.buf = async->rx.buf,
+		};
+		async_user_callback(dev, &rel_event);
+
+		async->rx.buf = async->rx.next_buf;
+		async->rx.len = async->rx.next_len;
+
+		async->rx.next_buf = NULL;
+		async->rx.next_len = 0;
+		struct uart_event req_event = {
+			.type = UART_RX_BUF_REQUEST,
+		};
+		async_user_callback(dev, &req_event);
+
+		dma_reload(config->rx_dma.dev, config->rx_dma.channel, config->rx_dma.slot,
+			   (uint32_t)async->rx.buf, async->rx.len);
+		dma_start(config->rx_dma.dev, config->rx_dma.channel);
+
+		api_irq_rx_enable(dev);
+		async_timer_start(&async->rx.timeout_work, async->rx.timeout);
+	} else {
+		api_rx_disable(dev);
+	}
+}
+
+static int api_rx_enable(const struct device *dev, uint8_t *buf, size_t len, int32_t timeout)
+{
+	struct max32_uart_data *data = dev->data;
+	const struct max32_uart_config *config = dev->config;
+	struct dma_status dma_stat;
+	struct dma_config dma_cfg = {0};
+	struct dma_block_config dma_blk = {0};
+	int ret;
+
+	unsigned int key = irq_lock();
+
+	if (config->rx_dma.channel == 0xFF) {
+		LOG_ERR("Rx DMA channel is not configured");
+		irq_unlock(key);
+		return -ENOTSUP;
+	}
+
+	ret = dma_get_status(config->rx_dma.dev, config->rx_dma.channel, &dma_stat);
+	if (ret < 0 || dma_stat.busy) {
+		LOG_ERR("DMA Rx %s", ret < 0 ? "error" : "busy");
+		irq_unlock(key);
+		return ret < 0 ? ret : -EBUSY;
+	}
+
+	data->async.rx.buf = buf;
+	data->async.rx.len = len;
+
+	dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
+	dma_cfg.dma_callback = uart_max32_async_rx_callback;
+	dma_cfg.user_data = (void *)dev;
+	dma_cfg.dma_slot = config->rx_dma.slot;
+	dma_cfg.block_count = 1;
+	dma_cfg.source_data_size = 1U;
+	dma_cfg.source_burst_length = 1U;
+	dma_cfg.dest_data_size = 1U;
+	dma_cfg.head_block = &dma_blk;
+	dma_blk.block_size = len;
+	dma_blk.dest_address = (uint32_t)buf;
+
+	ret = dma_config(config->rx_dma.dev, config->rx_dma.channel, &dma_cfg);
+	if (ret < 0) {
+		LOG_ERR("Error configuring Rx DMA (%d)", ret);
+		irq_unlock(key);
+		return ret;
+	}
+
+	ret = dma_start(config->rx_dma.dev, config->rx_dma.channel);
+	if (ret < 0) {
+		LOG_ERR("Error starting Rx DMA (%d)", ret);
+		irq_unlock(key);
+		return ret;
+	}
+
+	data->async.rx.timeout = timeout;
+
+	Wrap_MXC_UART_SetRxDMALevel(config->regs, 1);
+	Wrap_MXC_UART_EnableRxDMA(config->regs);
+
+	struct uart_event buf_req = {
+		.type = UART_RX_BUF_REQUEST,
+	};
+
+	async_user_callback(dev, &buf_req);
+
+	api_irq_rx_enable(dev);
+	async_timer_start(&data->async.rx.timeout_work, timeout);
+
+	irq_unlock(key);
+	return ret;
+}
+
+static int api_rx_buf_rsp(const struct device *dev, uint8_t *buf, size_t len)
+{
+	struct max32_uart_data *data = dev->data;
+
+	data->async.rx.next_buf = buf;
+	data->async.rx.next_len = len;
+
+	return 0;
+}
+
+static void uart_max32_async_rx_timeout(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct max32_uart_async_rx *rx =
+		CONTAINER_OF(dwork, struct max32_uart_async_rx, timeout_work);
+	struct max32_uart_async_data *async = CONTAINER_OF(rx, struct max32_uart_async_data, rx);
+	struct max32_uart_data *data = CONTAINER_OF(async, struct max32_uart_data, async);
+	const struct max32_uart_config *config = data->async.uart_dev->config;
+	struct dma_status dma_stat;
+	uint32_t total_rx;
+
+	unsigned int key = irq_lock();
+
+	dma_get_status(config->rx_dma.dev, config->rx_dma.channel, &dma_stat);
+
+	api_irq_rx_disable(data->async.uart_dev);
+	k_work_cancel_delayable(&data->async.rx.timeout_work);
+
+	irq_unlock(key);
+
+	total_rx = async->rx.len - dma_stat.pending_length;
+
+	if (total_rx > async->rx.offset) {
+		async->rx.counter = total_rx - async->rx.offset;
+		struct uart_event rdy_event = {
+			.type = UART_RX_RDY,
+			.data.rx.buf = async->rx.buf,
+			.data.rx.len = async->rx.counter,
+			.data.rx.offset = async->rx.offset,
+		};
+		async_user_callback(async->uart_dev, &rdy_event);
+	}
+	async->rx.offset += async->rx.counter;
+	async->rx.counter = 0;
+
+	api_irq_rx_enable(data->async.uart_dev);
+}
+
+#endif
 
 static DEVICE_API(uart, uart_max32_driver_api) = {
 	.poll_in = api_poll_in,
@@ -419,12 +988,46 @@ static DEVICE_API(uart, uart_max32_driver_api) = {
 	.irq_update = api_irq_update,
 	.irq_callback_set = api_irq_callback_set,
 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+#ifdef CONFIG_UART_ASYNC_API
+	.callback_set = api_callback_set,
+	.tx = api_tx,
+	.tx_abort = api_tx_abort,
+	.rx_enable = api_rx_enable,
+	.rx_buf_rsp = api_rx_buf_rsp,
+	.rx_disable = api_rx_disable,
+#endif /* CONFIG_UART_ASYNC_API */
 };
 
+#ifdef CONFIG_UART_ASYNC_API
+#define MAX32_DT_INST_DMA_CTLR(n, name)                                                            \
+	COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas),                                                \
+		    (DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, name))), (NULL))
+
+#define MAX32_DT_INST_DMA_CELL(n, name, cell)                                                      \
+	COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas), (DT_INST_DMAS_CELL_BY_NAME(n, name, cell)),    \
+		    (0xff))
+
+#define MAX32_UART_DMA_INIT(n)                                                                     \
+	.tx_dma.dev = MAX32_DT_INST_DMA_CTLR(n, tx),                                               \
+	.tx_dma.channel = MAX32_DT_INST_DMA_CELL(n, tx, channel),                                  \
+	.tx_dma.slot = MAX32_DT_INST_DMA_CELL(n, tx, slot),                                        \
+	.rx_dma.dev = MAX32_DT_INST_DMA_CTLR(n, rx),                                               \
+	.rx_dma.channel = MAX32_DT_INST_DMA_CELL(n, rx, channel),                                  \
+	.rx_dma.slot = MAX32_DT_INST_DMA_CELL(n, rx, slot),
+#else
+#define MAX32_UART_DMA_INIT(n)
+#endif
+
+#if defined(CONFIG_UART_INTERRUPT_DRIVEN) || defined(CONFIG_UART_ASYNC_API)
+#define MAX32_UART_USE_IRQ 1
+#else
+#define MAX32_UART_USE_IRQ 0
+#endif
+
 #define MAX32_UART_INIT(_num)                                                                      \
 	PINCTRL_DT_INST_DEFINE(_num);                                                              \
-	IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN,                                                   \
-		   (static void uart_max32_irq_init_##_num(const struct device *dev) \
+	IF_ENABLED(MAX32_UART_USE_IRQ,                                                             \
+		   (static void uart_max32_irq_init_##_num(const struct device *dev)               \
 		   {             \
 			   IRQ_CONNECT(DT_INST_IRQN(_num), DT_INST_IRQ(_num, priority),            \
 				       uart_max32_isr, DEVICE_DT_INST_GET(_num), 0);               \
@@ -438,14 +1041,14 @@ static DEVICE_API(uart, uart_max32_driver_api) = {
 		.perclk.bit = DT_INST_CLOCKS_CELL(_num, bit),                                      \
 		.perclk.clk_src =                                                                  \
 			DT_INST_PROP_OR(_num, clock_source, ADI_MAX32_PRPH_CLK_SRC_PCLK),          \
-		.uart_conf.baudrate = DT_INST_PROP_OR(_num, current_speed, 115200),                \
-		.uart_conf.parity = DT_INST_ENUM_IDX_OR(_num, parity, UART_CFG_PARITY_NONE),       \
-		.uart_conf.data_bits = DT_INST_ENUM_IDX_OR(_num, data_bits, UART_CFG_DATA_BITS_8), \
-		.uart_conf.stop_bits = DT_INST_ENUM_IDX_OR(_num, stop_bits, UART_CFG_STOP_BITS_1), \
+		.uart_conf.baudrate = DT_INST_PROP(_num, current_speed),                           \
+		.uart_conf.parity = DT_INST_ENUM_IDX(_num, parity),                                \
+		.uart_conf.data_bits = DT_INST_ENUM_IDX(_num, data_bits),                          \
+		.uart_conf.stop_bits = DT_INST_ENUM_IDX(_num, stop_bits),                          \
 		.uart_conf.flow_ctrl =                                                             \
-			DT_INST_PROP_OR(_num, hw_flow_control, UART_CFG_FLOW_CTRL_NONE),           \
-		IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN,                                           \
-			   (.irq_config_func = uart_max32_irq_init_##_num,))};                     \
+			DT_INST_PROP_OR(index, hw_flow_control, UART_CFG_FLOW_CTRL_NONE),          \
+		MAX32_UART_DMA_INIT(_num) IF_ENABLED(                                              \
+			MAX32_UART_USE_IRQ, (.irq_config_func = uart_max32_irq_init_##_num,))};    \
 	static struct max32_uart_data max32_uart_data##_num = {                                    \
 		IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, (.cb = NULL,))};                          \
 	DEVICE_DT_INST_DEFINE(_num, uart_max32_init, NULL, &max32_uart_data##_num,                 \
diff --git a/drivers/serial/uart_mchp_mec5.c b/drivers/serial/uart_mchp_mec5.c
new file mode 100644
index 00000000000..61f0a010e83
--- /dev/null
+++ b/drivers/serial/uart_mchp_mec5.c
@@ -0,0 +1,662 @@
+/*
+ * Copyright (c) 2024 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief Microchip MEC5 ns16550 compatible UART Serial Driver
+ */
+
+#define DT_DRV_COMPAT microchip_mec5_uart
+
+#include <errno.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/uart.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/irq.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/spinlock.h>
+#include <zephyr/sys/byteorder.h>
+
+LOG_MODULE_REGISTER(uart_mec5, CONFIG_UART_LOG_LEVEL);
+
+/* MEC5 HAL */
+#include <device_mec5.h>
+#include <mec_ecia_api.h>
+#include <mec_uart_api.h>
+
+#define UART_MEC_DFLT_CLK_FREQ                1843200u
+#define UART_MEC_DEVCFG_FLAG_RX_FIFO_TRIG_POS 0
+#define UART_MEC_DEVCFG_FLAG_RX_FIFO_TRIG_MSK 0x3u
+#define UART_MEC_DEVCFG_FLAG_FIFO_DIS_POS     4
+#define UART_MEC_DEVCFG_FLAG_USE_EXTCLK_POS   5
+
+struct uart_mec5_devcfg {
+	struct mec_uart_regs *regs;
+	const struct pinctrl_dev_config *pcfg;
+	uint32_t clock_freq;
+	uint32_t flags;
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	void (*irq_config_func)(const struct device *dev);
+#endif
+};
+
+struct uart_mec5_dev_data {
+	const struct device *dev;
+	struct uart_config current_config;
+	struct uart_config ucfg;
+	struct k_spinlock lock;
+	enum mec_uart_ipend ipend;
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	uart_irq_callback_user_data_t cb; /* Callback function pointer */
+	void *cb_data;                    /* Callback function arg */
+	uint32_t flags;
+	uint8_t rx_enabled;
+	uint8_t tx_enabled;
+#endif
+};
+
+static const uint8_t mec5_xlat_word_len[4] = {
+	MEC_UART_WORD_LEN_5,
+	MEC_UART_WORD_LEN_6,
+	MEC_UART_WORD_LEN_7,
+	MEC_UART_WORD_LEN_8,
+};
+
+static const uint8_t mec5_xlat_stop_bits[4] = {
+	MEC_UART_STOP_BITS_1,
+	MEC_UART_STOP_BITS_1,
+	MEC_UART_STOP_BITS_2,
+	MEC_UART_STOP_BITS_2,
+};
+
+static const uint8_t mec5_xlat_parity[5] = {
+	(uint8_t)(MEC5_UART_CFG_PARITY_NONE >> MEC5_UART_CFG_PARITY_POS),
+	(uint8_t)(MEC5_UART_CFG_PARITY_ODD >> MEC5_UART_CFG_PARITY_POS),
+	(uint8_t)(MEC5_UART_CFG_PARITY_EVEN >> MEC5_UART_CFG_PARITY_POS),
+	(uint8_t)(MEC5_UART_CFG_PARITY_MARK >> MEC5_UART_CFG_PARITY_POS),
+	(uint8_t)(MEC5_UART_CFG_PARITY_SPACE >> MEC5_UART_CFG_PARITY_POS),
+};
+
+static int uart_mec5_xlat_cfg(const struct uart_config *cfg, uint32_t *cfg_word)
+{
+	uint32_t temp;
+
+	if (!cfg || !cfg_word) {
+		return -EINVAL;
+	}
+
+	*cfg_word = 0u;
+
+	if (cfg->data_bits > UART_CFG_DATA_BITS_8) {
+		return -EINVAL;
+	}
+	temp = mec5_xlat_word_len[cfg->data_bits];
+	*cfg_word |= ((temp << MEC5_UART_CFG_WORD_LEN_POS) & MEC5_UART_CFG_WORD_LEN_MSK);
+
+	if (cfg->stop_bits > UART_CFG_STOP_BITS_2) {
+		return -EINVAL;
+	}
+	temp = mec5_xlat_stop_bits[cfg->stop_bits];
+	*cfg_word |= ((temp << MEC5_UART_CFG_STOP_BITS_POS) & MEC5_UART_CFG_STOP_BITS_MSK);
+
+	if (cfg->parity > UART_CFG_PARITY_SPACE) {
+		return -EINVAL;
+	}
+	temp = mec5_xlat_parity[cfg->parity];
+	*cfg_word |= ((temp << MEC5_UART_CFG_PARITY_POS) & MEC5_UART_CFG_PARITY_MSK);
+
+	return 0;
+}
+
+/* Configure UART TX and RX FIFOs based on device tree.
+ * Both FIFOs are fixed 16-byte.
+ * RX FIFO has a configurable interrupt trigger level of 1, 4, 8, or 14 bytes.
+ */
+static uint32_t uart_mec5_fifo_config(uint32_t mcfg, uint32_t cfg_flags)
+{
+	uint32_t new_mcfg = mcfg;
+	uint32_t temp = 0;
+
+	if (!(cfg_flags & BIT(UART_MEC_DEVCFG_FLAG_FIFO_DIS_POS))) {
+		new_mcfg |= BIT(MEC5_UART_CFG_FIFO_EN_POS);
+		temp = (cfg_flags & UART_MEC_DEVCFG_FLAG_RX_FIFO_TRIG_MSK) >>
+		       UART_MEC_DEVCFG_FLAG_RX_FIFO_TRIG_POS;
+		switch (temp) {
+		case 0:
+			new_mcfg |= MEC5_UART_CFG_RX_FIFO_TRIG_LVL_1;
+			break;
+		case 1:
+			new_mcfg |= MEC5_UART_CFG_RX_FIFO_TRIG_LVL_4;
+			break;
+		case 2:
+			new_mcfg |= MEC5_UART_CFG_RX_FIFO_TRIG_LVL_8;
+			break;
+		default:
+			new_mcfg |= MEC5_UART_CFG_RX_FIFO_TRIG_LVL_14;
+			break;
+		}
+	}
+
+	return new_mcfg;
+}
+
+static int config_mec5_uart(const struct device *dev, const struct uart_config *cfg)
+{
+	const struct uart_mec5_devcfg *devcfg = dev->config;
+	struct mec_uart_regs *const regs = devcfg->regs;
+	struct uart_mec5_dev_data *const data = dev->data;
+	int ret = 0;
+	uint32_t mcfg = 0, extclk = 0;
+
+	data->ipend = MEC_UART_IPEND_NONE;
+
+	ret = uart_mec5_xlat_cfg(cfg, &mcfg);
+	if (ret) {
+		return ret;
+	}
+
+	mcfg = uart_mec5_fifo_config(mcfg, devcfg->flags);
+	mcfg |= BIT(MEC5_UART_CFG_GIRQ_EN_POS);
+
+	if (devcfg->flags & BIT(UART_MEC_DEVCFG_FLAG_USE_EXTCLK_POS)) {
+		extclk = devcfg->clock_freq;
+	}
+
+	ret = mec_hal_uart_init(regs, cfg->baudrate, mcfg, extclk);
+	if (ret != MEC_RET_OK) {
+		return -EIO;
+	}
+
+	memcpy(&data->ucfg, cfg, sizeof(struct uart_config));
+
+	return ret;
+};
+
+#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
+/* run-time driver configuration API */
+static int uart_mec5_configure(const struct device *dev, const struct uart_config *cfg)
+{
+	const struct uart_mec5_devcfg *devcfg = dev->config;
+	struct uart_mec5_dev_data *const data = dev->data;
+	int ret = 0;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret) {
+		LOG_ERR("MEC5 UART pinctrl error (%d)", ret);
+	}
+
+	ret = config_mec5_uart(dev, cfg);
+	if (ret) {
+		LOG_ERR("MEC5 UART config error (%d)", ret);
+		return ret;
+	}
+
+	data->current_config = *cfg;
+
+	k_spin_unlock(&data->lock, key);
+
+	return ret;
+}
+
+static int uart_mec5_config_get(const struct device *dev, struct uart_config *cfg)
+{
+	struct uart_mec5_dev_data *const data = dev->data;
+
+	if (!cfg) {
+		return -EINVAL;
+	}
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	*cfg = data->current_config;
+
+	k_spin_unlock(&data->lock, key);
+
+	return 0;
+}
+#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
+
+/* Called by kernel during driver initialization phase */
+static int uart_mec5_init(const struct device *dev)
+{
+	const struct uart_mec5_devcfg *devcfg = dev->config;
+	struct uart_mec5_dev_data *data = dev->data;
+	int ret = 0;
+
+	ret = pinctrl_apply_state(devcfg->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret) {
+		LOG_ERR("MEC5 UART init pinctrl error (%d)", ret);
+		return ret;
+	}
+
+	ret = config_mec5_uart(dev, &data->ucfg);
+	if (ret != 0) {
+		return -EIO;
+	}
+
+	return ret;
+}
+
+/*
+ * Poll the UART for input.
+ * return 0 is a byte arrived else -1 if no data.
+ */
+static int uart_mec5_poll_in(const struct device *dev, unsigned char *cptr)
+{
+	const struct uart_mec5_devcfg *devcfg = dev->config;
+	struct mec_uart_regs *const regs = devcfg->regs;
+	struct uart_mec5_dev_data *data = dev->data;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+	int ret = 0;
+
+	ret = mec_hal_uart_rx_byte(regs, (uint8_t *)cptr);
+	if (ret == MEC_RET_ERR_NO_DATA) {
+		k_spin_unlock(&data->lock, key);
+		return -1;
+	}
+
+	k_spin_unlock(&data->lock, key);
+
+	return 0;
+}
+
+/* Block until UART can accept data byte. */
+static void uart_mec5_poll_out(const struct device *dev, unsigned char out_data)
+{
+	const struct uart_mec5_devcfg *devcfg = dev->config;
+	struct mec_uart_regs *const regs = devcfg->regs;
+	struct uart_mec5_dev_data *data = dev->data;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+	int ret = 0;
+
+	do {
+		ret = mec_hal_uart_tx_byte(regs, (uint8_t)out_data);
+	} while (ret == MEC_RET_ERR_BUSY);
+
+	k_spin_unlock(&data->lock, key);
+}
+
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+static inline void irq_tx_enable(const struct device *dev)
+{
+	const struct uart_mec5_devcfg *devcfg = dev->config;
+	struct mec_uart_regs *const regs = devcfg->regs;
+	struct uart_mec5_dev_data *data = dev->data;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	mec_hal_uart_intr_mask(regs, MEC_UART_IEN_FLAG_ETHREI, MEC_UART_IEN_FLAG_ETHREI);
+
+	k_spin_unlock(&data->lock, key);
+}
+
+static inline void irq_tx_disable(const struct device *dev)
+{
+	const struct uart_mec5_devcfg *devcfg = dev->config;
+	struct uart_mec5_dev_data *data = dev->data;
+	struct mec_uart_regs *const regs = devcfg->regs;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	mec_hal_uart_intr_mask(regs, MEC_UART_IEN_FLAG_ETHREI, 0);
+
+	k_spin_unlock(&data->lock, key);
+}
+
+static inline void irq_rx_enable(const struct device *dev)
+{
+	const struct uart_mec5_devcfg *const devcfg = dev->config;
+	struct uart_mec5_dev_data *data = dev->data;
+	struct mec_uart_regs *const regs = devcfg->regs;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	mec_hal_uart_intr_mask(regs, MEC_UART_IEN_FLAG_ERDAI, MEC_UART_IEN_FLAG_ERDAI);
+
+	k_spin_unlock(&data->lock, key);
+}
+
+static inline void irq_rx_disable(const struct device *dev)
+{
+	const struct uart_mec5_devcfg *const devcfg = dev->config;
+	struct uart_mec5_dev_data *data = dev->data;
+	struct mec_uart_regs *const regs = devcfg->regs;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	mec_hal_uart_intr_mask(regs, MEC_UART_IEN_FLAG_ERDAI, 0);
+
+	k_spin_unlock(&data->lock, key);
+}
+
+static int uart_mec5_fifo_fill(const struct device *dev, const uint8_t *tx_data, int len)
+{
+	const struct uart_mec5_devcfg *const devcfg = dev->config;
+	struct uart_mec5_dev_data *data = dev->data;
+	struct mec_uart_regs *const regs = devcfg->regs;
+	int num_tx = 0, ret = 0;
+
+	if (len < 0) {
+		return 0;
+	}
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	while (num_tx < len) {
+		ret = mec_hal_uart_tx_byte(regs, tx_data[num_tx]);
+		if (ret == MEC_RET_ERR_BUSY) {
+			break;
+		}
+		num_tx++;
+	}
+
+	if (data->tx_enabled) {
+		irq_tx_enable(dev);
+	}
+
+	k_spin_unlock(&data->lock, key);
+
+	return num_tx;
+}
+
+static int uart_mec5_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
+{
+	const struct uart_mec5_devcfg *const devcfg = dev->config;
+	struct uart_mec5_dev_data *data = dev->data;
+	struct mec_uart_regs *const regs = devcfg->regs;
+	int num_rx = 0, ret = 0;
+
+	if (size < 0) {
+		return 0;
+	}
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+	uint8_t *pdata = rx_data;
+
+	while (num_rx < size) {
+		ret = mec_hal_uart_rx_byte(regs, pdata);
+		if (ret != MEC_RET_OK) {
+			break;
+		}
+		pdata++;
+		num_rx++;
+	}
+
+	if (data->rx_enabled) {
+		irq_rx_enable(dev);
+	}
+
+	k_spin_unlock(&data->lock, key);
+
+	return num_rx;
+}
+
+static void uart_mec5_irq_tx_enable(const struct device *dev)
+{
+	struct uart_mec5_dev_data *data = dev->data;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	data->tx_enabled = 1;
+	irq_tx_enable(dev);
+
+	k_spin_unlock(&data->lock, key);
+}
+
+static void uart_mec5_irq_tx_disable(const struct device *dev)
+{
+	struct uart_mec5_dev_data *data = dev->data;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	irq_tx_disable(dev);
+	data->tx_enabled = 0;
+
+	k_spin_unlock(&data->lock, key);
+}
+
+static int uart_mec5_irq_tx_ready(const struct device *dev)
+{
+	struct uart_mec5_dev_data *data = dev->data;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+	int ret = 0;
+
+	if (data->ipend == MEC_UART_IPEND_TX) {
+		ret = 1;
+	}
+
+	k_spin_unlock(&data->lock, key);
+
+	return ret;
+}
+
+static void uart_mec5_irq_rx_enable(const struct device *dev)
+{
+	struct uart_mec5_dev_data *data = dev->data;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	data->rx_enabled = 1;
+	irq_rx_enable(dev);
+
+	k_spin_unlock(&data->lock, key);
+}
+
+static void uart_mec5_irq_rx_disable(const struct device *dev)
+{
+	struct uart_mec5_dev_data *data = dev->data;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	irq_rx_disable(dev);
+	data->rx_enabled = 0;
+
+	k_spin_unlock(&data->lock, key);
+}
+
+/* check if UART TX shift register is empty. Empty TX shift register indicates
+ * the UART does not need clocks and can be put into a low power state.
+ * return 1 nothing remains to be transmitted, 0 otherwise.
+ */
+static int uart_mec5_irq_tx_complete(const struct device *dev)
+{
+	const struct uart_mec5_devcfg *const devcfg = dev->config;
+	struct mec_uart_regs *const regs = devcfg->regs;
+	struct uart_mec5_dev_data *data = dev->data;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+	int ret = mec_hal_uart_is_tx_empty(regs);
+
+	k_spin_unlock(&data->lock, key);
+
+	return ret;
+}
+
+static int uart_mec5_irq_rx_ready(const struct device *dev)
+{
+	struct uart_mec5_dev_data *data = dev->data;
+	int ret = 0;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	if (data->ipend == MEC_UART_IPEND_RX_DATA) {
+		ret = 1;
+	}
+
+	k_spin_unlock(&data->lock, key);
+
+	return ret;
+}
+
+static void irq_error_enable(const struct device *dev, uint8_t enable)
+{
+	const struct uart_mec5_devcfg *const devcfg = dev->config;
+	struct mec_uart_regs *const regs = devcfg->regs;
+	uint8_t msk = 0;
+
+	if (enable) {
+		msk = MEC_UART_IEN_FLAG_ELSI;
+	}
+
+	mec_hal_uart_intr_mask(regs, MEC_UART_IEN_FLAG_ELSI, msk);
+}
+
+/*
+ * Enable received line status interrupt active when one or more of the following errors
+ * occur: overrun, parity, framing, or break.
+ */
+static void uart_mec5_irq_err_enable(const struct device *dev)
+{
+	struct uart_mec5_dev_data *data = dev->data;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	irq_error_enable(dev, 1u);
+
+	k_spin_unlock(&data->lock, key);
+}
+
+static void uart_mec5_irq_err_disable(const struct device *dev)
+{
+	struct uart_mec5_dev_data *data = dev->data;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	irq_error_enable(dev, 0);
+
+	k_spin_unlock(&data->lock, key);
+}
+
+static int uart_mec5_irq_is_pending(const struct device *dev)
+{
+	struct uart_mec5_dev_data *data = dev->data;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+	int ret = 0;
+
+	if (data->ipend != MEC_UART_IPEND_NONE) {
+		ret = 1;
+	}
+
+	k_spin_unlock(&data->lock, key);
+
+	return ret;
+}
+
+static int uart_mec5_irq_update(const struct device *dev)
+{
+	const struct uart_mec5_devcfg *const devcfg = dev->config;
+	struct mec_uart_regs *const regs = devcfg->regs;
+	struct uart_mec5_dev_data *data = dev->data;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	data->ipend = MEC_UART_IPEND_NONE;
+	mec_hal_uart_pending_status(regs, &data->ipend);
+
+	switch (data->ipend) {
+	case MEC_UART_IPEND_NONE:
+		break;
+	case MEC_UART_IPEND_TX:
+		irq_tx_disable(dev);
+		break;
+	case MEC_UART_IPEND_RX_DATA:
+		irq_rx_disable(dev);
+		break;
+	case MEC_UART_IPEND_RX_ERR:
+		irq_error_enable(dev, 0);
+		break;
+	case MEC_UART_IPEND_MODEM:
+		__fallthrough; /* fall through */
+	default:
+		k_panic();
+		break;
+	}
+
+	k_spin_unlock(&data->lock, key);
+
+	return 1;
+}
+
+static void uart_mec5_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
+				       void *cb_data)
+{
+	struct uart_mec5_dev_data *data = dev->data;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	data->cb = cb;
+	data->cb_data = cb_data;
+
+	k_spin_unlock(&data->lock, key);
+}
+
+static void uart_mec5_isr(const struct device *dev)
+{
+	struct uart_mec5_dev_data *data = dev->data;
+
+	if (data->cb) {
+		data->cb(dev, data->cb_data);
+	}
+}
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+
+static DEVICE_API(uart, uart_mec5_driver_api) = {
+	.poll_in = uart_mec5_poll_in,
+	.poll_out = uart_mec5_poll_out,
+#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
+	.configure = uart_mec5_configure,
+	.config_get = uart_mec5_config_get,
+#endif
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	.fifo_fill = uart_mec5_fifo_fill,
+	.fifo_read = uart_mec5_fifo_read,
+	.irq_tx_enable = uart_mec5_irq_tx_enable,
+	.irq_tx_disable = uart_mec5_irq_tx_disable,
+	.irq_tx_ready = uart_mec5_irq_tx_ready,
+	.irq_rx_enable = uart_mec5_irq_rx_enable,
+	.irq_rx_disable = uart_mec5_irq_rx_disable,
+	.irq_tx_complete = uart_mec5_irq_tx_complete,
+	.irq_rx_ready = uart_mec5_irq_rx_ready,
+	.irq_err_enable = uart_mec5_irq_err_enable,
+	.irq_err_disable = uart_mec5_irq_err_disable,
+	.irq_is_pending = uart_mec5_irq_is_pending,
+	.irq_update = uart_mec5_irq_update,
+	.irq_callback_set = uart_mec5_irq_callback_set,
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+};
+
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+#define UART_MEC5_CONFIGURE(n)                                                                     \
+	do {                                                                                       \
+		IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), uart_mec5_isr,              \
+			    DEVICE_DT_INST_GET(n), 0);                                             \
+                                                                                                   \
+		irq_enable(DT_INST_IRQN(n));                                                       \
+	} while (0)
+#else
+#define UART_MEC5_CONFIGURE(n)
+#endif
+
+#define UART_MEC5_DCFG_FLAGS(i)                                                                    \
+	((DT_INST_ENUM_IDX_OR(i, rx_fifo_trig, 2) & 0x3u) |                                        \
+	 ((DT_INST_PROP_OR(i, fifo_mode_disable, 0) & 0x1u) << 4) |                                \
+	 ((DT_INST_PROP_OR(i, use_extclk, 0) & 0x1u) << 5))
+
+#define DEV_DATA_FLOW_CTRL(n) DT_INST_PROP_OR(n, hw_flow_control, UART_CFG_FLOW_CTRL_NONE)
+
+#define UART_MEC5_DEVICE(i)                                                                        \
+	PINCTRL_DT_INST_DEFINE(i);                                                                 \
+	static const struct uart_mec5_devcfg uart_mec5_##i##_devcfg = {                            \
+		.regs = (struct mec_uart_regs *)DT_INST_REG_ADDR(i),                               \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(i),                                         \
+		.clock_freq = DT_INST_PROP_OR(i, clock_frequency, UART_MEC_DFLT_CLK_FREQ),         \
+		.flags = UART_MEC5_DCFG_FLAGS(i),                                                  \
+	};                                                                                         \
+	static struct uart_mec5_dev_data uart_mec5_##i##_dev_data = {                              \
+		.ucfg.baudrate = DT_INST_PROP_OR(i, current_speed, 0),                             \
+		.ucfg.parity = UART_CFG_PARITY_NONE,                                               \
+		.ucfg.stop_bits = UART_CFG_STOP_BITS_1,                                            \
+		.ucfg.data_bits = UART_CFG_DATA_BITS_8,                                            \
+		.ucfg.flow_ctrl = DEV_DATA_FLOW_CTRL(i),                                           \
+	};                                                                                         \
+	static int uart_mec5_##i##_init(const struct device *dev)                                  \
+	{                                                                                          \
+		UART_MEC5_CONFIGURE(i);                                                            \
+		return uart_mec5_init(dev);                                                        \
+	}                                                                                          \
+	DEVICE_DT_INST_DEFINE(i, uart_mec5_##i##_init, NULL, &uart_mec5_##i##_dev_data,            \
+			      &uart_mec5_##i##_devcfg, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY,  \
+			      &uart_mec5_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(UART_MEC5_DEVICE)
diff --git a/drivers/serial/uart_mcux_flexcomm.c b/drivers/serial/uart_mcux_flexcomm.c
index b0a51b4d1a3..9fdb3c26c60 100644
--- a/drivers/serial/uart_mcux_flexcomm.c
+++ b/drivers/serial/uart_mcux_flexcomm.c
@@ -14,7 +14,9 @@
 #include <zephyr/device.h>
 #include <zephyr/drivers/uart.h>
 #include <zephyr/drivers/clock_control.h>
+#include <zephyr/pm/policy.h>
 #include <zephyr/irq.h>
+#include <zephyr/pm/device.h>
 #include <fsl_usart.h>
 #include <soc.h>
 #include <fsl_device_registers.h>
@@ -86,8 +88,33 @@ struct mcux_flexcomm_data {
 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
 	struct uart_config uart_config;
 #endif
+#ifdef CONFIG_PM_POLICY_DEVICE_CONSTRAINTS
+	bool pm_policy_state_lock;
+#endif
 };
 
+#ifdef CONFIG_PM_POLICY_DEVICE_CONSTRAINTS
+static void mcux_flexcomm_pm_policy_state_lock_get(const struct device *dev)
+{
+	struct mcux_flexcomm_data *data = dev->data;
+
+	if (!data->pm_policy_state_lock) {
+		data->pm_policy_state_lock = true;
+		pm_policy_device_power_lock_get(dev);
+	}
+}
+
+static void mcux_flexcomm_pm_policy_state_lock_put(const struct device *dev)
+{
+	struct mcux_flexcomm_data *data = dev->data;
+
+	if (data->pm_policy_state_lock) {
+		data->pm_policy_state_lock = false;
+		pm_policy_device_power_lock_put(dev);
+	}
+}
+#endif
+
 static int mcux_flexcomm_poll_in(const struct device *dev, unsigned char *c)
 {
 	const struct mcux_flexcomm_config *config = dev->config;
@@ -179,6 +206,14 @@ static void mcux_flexcomm_irq_tx_enable(const struct device *dev)
 	const struct mcux_flexcomm_config *config = dev->config;
 	uint32_t mask = kUSART_TxLevelInterruptEnable;
 
+	/* Indicates that this device started a transaction that should
+	 * not be interrupted by putting the SoC in states that would
+	 * interfere with this transfer.
+	 */
+#ifdef CONFIG_PM_POLICY_DEVICE_CONSTRAINTS
+	mcux_flexcomm_pm_policy_state_lock_get(dev);
+#endif
+
 	USART_EnableInterrupts(config->base, mask);
 }
 
@@ -187,6 +222,10 @@ static void mcux_flexcomm_irq_tx_disable(const struct device *dev)
 	const struct mcux_flexcomm_config *config = dev->config;
 	uint32_t mask = kUSART_TxLevelInterruptEnable;
 
+#ifdef CONFIG_PM_POLICY_DEVICE_CONSTRAINTS
+	mcux_flexcomm_pm_policy_state_lock_put(dev);
+#endif
+
 	USART_DisableInterrupts(config->base, mask);
 }
 
@@ -467,11 +506,19 @@ static int mcux_flexcomm_uart_tx(const struct device *dev, const uint8_t *buf,
 	/* Enable TX DMA requests */
 	USART_EnableTxDMA(config->base, true);
 
+	/* Do not allow the system to suspend until the transmission has completed */
+#ifdef CONFIG_PM_POLICY_DEVICE_CONSTRAINTS
+	mcux_flexcomm_pm_policy_state_lock_get(dev);
+#endif
+
 	/* Trigger the DMA to start transfer */
 	ret = dma_start(config->tx_dma.dev, config->tx_dma.channel);
 	if (ret) {
 		irq_unlock(key);
-		return ret;
+#ifdef CONFIG_PM_POLICY_DEVICE_CONSTRAINTS
+		mcux_flexcomm_pm_policy_state_lock_put(dev);
+#endif
+	return ret;
 	}
 
 	/* Schedule a TX abort for @param timeout */
@@ -993,6 +1040,10 @@ static void mcux_flexcomm_isr(const struct device *dev)
 			data->tx_data.xfer_buf = NULL;
 
 			async_user_callback(dev, &tx_done_event);
+
+#ifdef CONFIG_PM_POLICY_DEVICE_CONSTRAINTS
+			mcux_flexcomm_pm_policy_state_lock_put(dev);
+#endif
 		}
 
 	}
@@ -1000,8 +1051,7 @@ static void mcux_flexcomm_isr(const struct device *dev)
 }
 #endif /* CONFIG_UART_MCUX_FLEXCOMM_ISR_SUPPORT */
 
-
-static int mcux_flexcomm_init(const struct device *dev)
+static int mcux_flexcomm_init_common(const struct device *dev)
 {
 	const struct mcux_flexcomm_config *config = dev->config;
 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
@@ -1067,6 +1117,41 @@ static int mcux_flexcomm_init(const struct device *dev)
 	return 0;
 }
 
+static uint32_t usart_intenset;
+static int mcux_flexcomm_pm_action(const struct device *dev, enum pm_device_action action)
+{
+	const struct mcux_flexcomm_config *config = dev->config;
+	int ret;
+
+	switch (action) {
+	case PM_DEVICE_ACTION_RESUME:
+		break;
+	case PM_DEVICE_ACTION_SUSPEND:
+		break;
+	case PM_DEVICE_ACTION_TURN_OFF:
+		usart_intenset = USART_GetEnabledInterrupts(config->base);
+		break;
+	case PM_DEVICE_ACTION_TURN_ON:
+		ret = mcux_flexcomm_init_common(dev);
+		if (ret) {
+			return ret;
+		}
+		USART_EnableInterrupts(config->base, usart_intenset);
+		break;
+	default:
+		return -ENOTSUP;
+	}
+	return 0;
+}
+
+static int mcux_flexcomm_init(const struct device *dev)
+{
+	/* Rest of the init is done from the PM_DEVICE_TURN_ON action
+	 * which is invoked by pm_device_driver_init().
+	 */
+	return pm_device_driver_init(dev, mcux_flexcomm_pm_action);
+}
+
 static DEVICE_API(uart, mcux_flexcomm_driver_api) = {
 	.poll_in = mcux_flexcomm_poll_in,
 	.poll_out = mcux_flexcomm_poll_out,
@@ -1188,7 +1273,7 @@ static const struct mcux_flexcomm_config mcux_flexcomm_##n##_config = {		\
 	.clock_subsys =								\
 	(clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),			\
 	.baud_rate = DT_INST_PROP(n, current_speed),				\
-	.parity = DT_INST_ENUM_IDX_OR(n, parity, UART_CFG_PARITY_NONE),		\
+	.parity = DT_INST_ENUM_IDX(n, parity),					\
 	.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),				\
 	UART_MCUX_FLEXCOMM_IRQ_CFG_FUNC_INIT(n)					\
 	UART_MCUX_FLEXCOMM_ASYNC_CFG(n)						\
@@ -1202,9 +1287,11 @@ static const struct mcux_flexcomm_config mcux_flexcomm_##n##_config = {		\
 										\
 	static const struct mcux_flexcomm_config mcux_flexcomm_##n##_config;	\
 										\
+	PM_DEVICE_DT_INST_DEFINE(n, mcux_flexcomm_pm_action);			\
+										\
 	DEVICE_DT_INST_DEFINE(n,						\
-			    mcux_flexcomm_init,					\
-			    NULL,						\
+			    &mcux_flexcomm_init,				\
+			    PM_DEVICE_DT_INST_GET(n),				\
 			    &mcux_flexcomm_##n##_data,				\
 			    &mcux_flexcomm_##n##_config,			\
 			    PRE_KERNEL_1,					\
diff --git a/drivers/serial/uart_mcux_iuart.c b/drivers/serial/uart_mcux_iuart.c
index 6906d6c98b6..2024efa7603 100644
--- a/drivers/serial/uart_mcux_iuart.c
+++ b/drivers/serial/uart_mcux_iuart.c
@@ -329,7 +329,7 @@ static const struct mcux_iuart_config mcux_iuart_##n##_config = {	\
 	.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),		\
 	.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),\
 	.baud_rate = DT_INST_PROP(n, current_speed),			\
-	.parity = DT_INST_ENUM_IDX_OR(n, parity, UART_CFG_PARITY_NONE),	\
+	.parity = DT_INST_ENUM_IDX(n, parity),				\
 	.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
 	IRQ_FUNC_INIT							\
 }
diff --git a/drivers/serial/uart_mcux_lpuart.c b/drivers/serial/uart_mcux_lpuart.c
index 9c31d8a34e5..9950f9ac873 100644
--- a/drivers/serial/uart_mcux_lpuart.c
+++ b/drivers/serial/uart_mcux_lpuart.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2017,2021,2023-2024 NXP
+ * Copyright 2017,2021,2023-2025 NXP
  * Copyright (c) 2020 Softube
  *
  * SPDX-License-Identifier: Apache-2.0
@@ -19,6 +19,7 @@
 #include <zephyr/drivers/dma.h>
 #endif
 #include <zephyr/logging/log.h>
+#include <zephyr/sys/util_macro.h>
 
 #include <fsl_lpuart.h>
 #if CONFIG_NXP_LP_FLEXCOMM
@@ -29,6 +30,16 @@ LOG_MODULE_REGISTER(uart_mcux_lpuart, LOG_LEVEL_ERR);
 
 #define PINCTRL_STATE_FLOWCONTROL PINCTRL_STATE_PRIV_START
 
+/* Helper macros */
+#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && \
+	FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+#define LPUART_HAS_MODEM 1
+#endif
+
+#if defined(FSL_FEATURE_LPUART_HAS_MCR) && FSL_FEATURE_LPUART_HAS_MCR
+#define LPUART_HAS_MCR 1
+#endif
+
 #if defined(CONFIG_UART_ASYNC_API) && defined(CONFIG_UART_INTERRUPT_DRIVEN)
 /* there are already going to be build errors, but at least this message will
  * be the first error from this driver making the reason clear
@@ -47,9 +58,6 @@ struct lpuart_dma_config {
 
 struct mcux_lpuart_config {
 	LPUART_Type *base;
-#ifdef CONFIG_NXP_LP_FLEXCOMM
-	const struct device *parent_dev;
-#endif
 	const struct device *clock_dev;
 	const struct pinctrl_dev_config *pincfg;
 	clock_control_subsys_t clock_subsys;
@@ -329,7 +337,7 @@ static int mcux_lpuart_irq_tx_ready(const struct device *dev)
 static void mcux_lpuart_irq_rx_enable(const struct device *dev)
 {
 	const struct mcux_lpuart_config *config = dev->config;
-	uint32_t mask = kLPUART_RxDataRegFullInterruptEnable;
+	uint32_t mask = kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable;
 
 	LPUART_EnableInterrupts(config->base, mask);
 }
@@ -337,7 +345,7 @@ static void mcux_lpuart_irq_rx_enable(const struct device *dev)
 static void mcux_lpuart_irq_rx_disable(const struct device *dev)
 {
 	const struct mcux_lpuart_config *config = dev->config;
-	uint32_t mask = kLPUART_RxDataRegFullInterruptEnable;
+	uint32_t mask = kLPUART_RxDataRegFullInterruptEnable | kLPUART_RxOverrunInterruptEnable;
 
 	LPUART_DisableInterrupts(config->base, mask);
 }
@@ -966,9 +974,43 @@ static void mcux_lpuart_isr(const struct device *dev)
 }
 #endif /* CONFIG_UART_MCUX_LPUART_ISR_SUPPORT */
 
+#if LPUART_HAS_MODEM
+static int mcux_lpuart_config_flowctrl(uint8_t flow_ctrl, lpuart_config_t *uart_config)
+{
+	switch (flow_ctrl) {
+	case UART_CFG_FLOW_CTRL_NONE:
+	case UART_CFG_FLOW_CTRL_RS485:
+		uart_config->enableTxCTS = false;
+		uart_config->enableRxRTS = false;
+		break;
+
+	case UART_CFG_FLOW_CTRL_RTS_CTS:
+		uart_config->enableTxCTS = true;
+		uart_config->enableRxRTS = true;
+		break;
+
+	default:
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+#else
+static int mcux_lpuart_config_flowctrl(uint8_t flow_ctrl, lpuart_config_t *uart_config)
+{
+	if (flow_ctrl != UART_CFG_FLOW_CTRL_NONE) {
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+#endif /* LPUART_HAS_MODEM */
+
 static int mcux_lpuart_configure_basic(const struct device *dev, const struct uart_config *cfg,
 					lpuart_config_t *uart_config)
 {
+	int ret;
+
 	/* Translate UART API enum to LPUART enum from HAL */
 	switch (cfg->parity) {
 	case UART_CFG_PARITY_NONE:
@@ -1012,22 +1054,15 @@ static int mcux_lpuart_configure_basic(const struct device *dev, const struct ua
 	}
 #endif
 
-#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && \
-	FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
-	switch (cfg->flow_ctrl) {
-	case UART_CFG_FLOW_CTRL_NONE:
-	case UART_CFG_FLOW_CTRL_RS485:
-		uart_config->enableTxCTS = false;
-		uart_config->enableRxRTS = false;
-		break;
-	case UART_CFG_FLOW_CTRL_RTS_CTS:
-		uart_config->enableTxCTS = true;
-		uart_config->enableRxRTS = true;
-		break;
-	default:
+	/* Configure for Flow Control option */
+	if (!IS_ENABLED(LPUART_HAS_MCR) && cfg->flow_ctrl == UART_CFG_FLOW_CTRL_DTR_DSR) {
 		return -ENOTSUP;
 	}
-#endif
+
+	ret = mcux_lpuart_config_flowctrl(cfg->flow_ctrl, uart_config);
+	if (ret) {
+		return ret;
+	}
 
 	uart_config->baudRate_Bps = cfg->baudrate;
 	uart_config->enableRx = true;
@@ -1101,8 +1136,7 @@ static int mcux_lpuart_configure_init(const struct device *dev, const struct uar
 
 	LPUART_Init(config->base, &uart_config, clock_freq);
 
-#if defined(FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT) && \
-	FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT
+#ifdef LPUART_HAS_MODEM
 	if (cfg->flow_ctrl == UART_CFG_FLOW_CTRL_RS485) {
 		/* Set the LPUART into RS485 mode (tx driver enable using RTS) */
 		config->base->MODIR |= LPUART_MODIR_TXRTSE(true);
@@ -1181,6 +1215,98 @@ static int mcux_lpuart_configure(const struct device *dev,
 }
 #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
 
+#ifdef CONFIG_UART_LINE_CTRL
+#if LPUART_HAS_MODEM
+static void mcux_lpuart_line_ctrl_set_rts(const struct device *dev, uint32_t val)
+{
+	const struct mcux_lpuart_config *config = dev->config;
+
+	/* Disable Transmitter and Receiver */
+	config->base->CTRL &= ~(LPUART_CTRL_TE_MASK | LPUART_CTRL_RE_MASK);
+
+	if (val >= 1U) {
+		/* Reset TXRTS to set RXRTSE bit, this provides high-level on RTS line */
+		config->base->MODIR &= ~(LPUART_MODIR_TXRTSPOL_MASK | LPUART_MODIR_TXRTSE_MASK);
+		config->base->MODIR |= LPUART_MODIR_RXRTSE_MASK;
+	} else {
+		/* Set TXRTSE to reset RXRTSE bit,this provide low-level on RTS line*/
+		config->base->MODIR &= ~(LPUART_MODIR_RXRTSE_MASK);
+		config->base->MODIR |= (LPUART_MODIR_TXRTSPOL_MASK | LPUART_MODIR_TXRTSE_MASK);
+	}
+}
+#else
+#define mcux_lpuart_line_ctrl_set_rts(dev, val) ret = -ENOTSUP
+#endif /* LPUART_HAS_MODEM */
+
+#if LPUART_HAS_MCR
+static void mcux_lpuart_set_dtr(const struct device *dev, uint32_t val)
+{
+	const struct mcux_lpuart_config *config = dev->config;
+
+	if (val >= 1U) {
+		/* assert DTR_b */
+		config->base->MCR &= ~LPUART_MCR_DTR_MASK;
+	} else {
+		/* deassert DTR_b */
+		config->base->MCR |= LPUART_MCR_DTR_MASK;
+	}
+}
+#else
+#define mcux_lpuart_set_dtr(dev, val) ret = -ENOTSUP
+#endif /* LPUART_HAS_MCR */
+
+static int mcux_lpuart_line_ctrl_set(const struct device *dev,
+		uint32_t ctrl, uint32_t val)
+{
+	int ret = 0;
+
+	switch (ctrl) {
+	case UART_LINE_CTRL_RTS:
+		mcux_lpuart_line_ctrl_set_rts(dev, val);
+		break;
+
+	case UART_LINE_CTRL_DTR:
+		mcux_lpuart_set_dtr(dev, val);
+		break;
+
+	default:
+		ret = -ENOTSUP;
+	}
+
+	return ret;
+}
+
+#if LPUART_HAS_MCR
+static int mcux_lpuart_line_ctrl_get(const struct device *dev,
+	uint32_t ctrl, uint32_t *val)
+{
+	const struct mcux_lpuart_config *config = dev->config;
+	int ret = 0;
+
+	switch (ctrl) {
+	case UART_LINE_CTRL_DSR:
+		*val = (config->base->MSR & LPUART_MSR_DSR_MASK) >> LPUART_MSR_DSR_SHIFT;
+		break;
+
+	case UART_LINE_CTRL_DCD:
+		*val = (config->base->MSR & LPUART_MSR_DCD_MASK) >> LPUART_MSR_DCD_SHIFT;
+		break;
+
+	default:
+		ret = -ENOTSUP;
+	}
+
+	return ret;
+}
+#else
+static int mcux_lpuart_line_ctrl_get(const struct device *dev,
+	uint32_t ctrl, uint32_t *val)
+{
+	return -ENOTSUP;
+}
+#endif /* LPUART_HAS_MCR */
+#endif /* CONFIG_UART_LINE_CTRL */
+
 static int mcux_lpuart_init(const struct device *dev)
 {
 	const struct mcux_lpuart_config *config = dev->config;
@@ -1211,20 +1337,12 @@ static int mcux_lpuart_init(const struct device *dev)
 	}
 
 #ifdef CONFIG_UART_MCUX_LPUART_ISR_SUPPORT
-#if CONFIG_NXP_LP_FLEXCOMM
-	/* When using LP Flexcomm driver, register the interrupt handler
-	 * so we receive notification from the LP Flexcomm interrupt handler.
-	 */
-	nxp_lp_flexcomm_setirqhandler(config->parent_dev, dev,
-				      LP_FLEXCOMM_PERIPH_LPUART, mcux_lpuart_isr);
-#else
-	/* Interrupt is managed by this driver */
 	config->irq_config_func(dev);
 #endif
+
 #ifdef CONFIG_UART_EXCLUSIVE_API_CALLBACKS
 	data->api_type = LPUART_NONE;
 #endif
-#endif
 
 #ifdef CONFIG_PM
 	data->pm_state_lock_on = false;
@@ -1267,6 +1385,10 @@ static DEVICE_API(uart, mcux_lpuart_driver_api) = {
 	.rx_buf_rsp = mcux_lpuart_rx_buf_rsp,
 	.rx_disable = mcux_lpuart_rx_disable,
 #endif /* CONFIG_UART_ASYNC_API */
+#ifdef CONFIG_UART_LINE_CTRL
+	.line_ctrl_set = mcux_lpuart_line_ctrl_set,
+	.line_ctrl_get = mcux_lpuart_line_ctrl_get,
+#endif  /* CONFIG_UART_LINE_CTRL */
 };
 
 
@@ -1279,15 +1401,26 @@ static DEVICE_API(uart, mcux_lpuart_driver_api) = {
 									\
 		irq_enable(DT_INST_IRQ_BY_IDX(n, i, irq));		\
 	} while (false)
+#define MCUX_LPUART_IRQS_INSTALL(n)					\
+		IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0),			\
+			   (MCUX_LPUART_IRQ_INSTALL(n, 0);))		\
+		IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 1),			\
+			   (MCUX_LPUART_IRQ_INSTALL(n, 1);))
+/* When using LP Flexcomm driver, register the interrupt handler
+ * so we receive notification from the LP Flexcomm interrupt handler.
+ */
+#define MCUX_LPUART_LPFLEXCOMM_IRQ_CONFIG(n)				\
+	nxp_lp_flexcomm_setirqhandler(DEVICE_DT_GET(DT_INST_PARENT(n)),	\
+					DEVICE_DT_INST_GET(n),		\
+					LP_FLEXCOMM_PERIPH_LPUART,	\
+					mcux_lpuart_isr)
 #define MCUX_LPUART_IRQ_INIT(n) .irq_config_func = mcux_lpuart_config_func_##n,
 #define MCUX_LPUART_IRQ_DEFINE(n)						\
 	static void mcux_lpuart_config_func_##n(const struct device *dev)	\
 	{									\
-		IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0),			\
-			   (MCUX_LPUART_IRQ_INSTALL(n, 0);))		\
-									\
-		IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 1),			\
-			   (MCUX_LPUART_IRQ_INSTALL(n, 1);))		\
+		COND_CODE_1(DT_NODE_HAS_COMPAT(DT_INST_PARENT(n), nxp_lp_flexcomm), \
+			    (MCUX_LPUART_LPFLEXCOMM_IRQ_CONFIG(n)),		\
+			    (MCUX_LPUART_IRQS_INSTALL(n)));			\
 	}
 #else
 #define MCUX_LPUART_IRQ_INIT(n)
@@ -1353,22 +1486,15 @@ static DEVICE_API(uart, mcux_lpuart_driver_api) = {
 		: DT_INST_PROP(n, nxp_rs485_mode)\
 				? UART_CFG_FLOW_CTRL_RS485   \
 				: UART_CFG_FLOW_CTRL_NONE
-#ifdef CONFIG_NXP_LP_FLEXCOMM
-#define PARENT_DEV(n) \
-	.parent_dev = DEVICE_DT_GET(DT_INST_PARENT(n)),
-#else
-#define PARENT_DEV(n)
-#endif /* CONFIG_NXP_LP_FLEXCOMM */
 
 #define LPUART_MCUX_DECLARE_CFG(n)                                      \
 static const struct mcux_lpuart_config mcux_lpuart_##n##_config = {     \
 	.base = (LPUART_Type *) DT_INST_REG_ADDR(n),                          \
-	PARENT_DEV(n)		\
 	.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),                   \
 	.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),	\
 	.baud_rate = DT_INST_PROP(n, current_speed),                          \
 	.flow_ctrl = FLOW_CONTROL(n),                                         \
-	.parity = DT_INST_ENUM_IDX_OR(n, parity, UART_CFG_PARITY_NONE),       \
+	.parity = DT_INST_ENUM_IDX(n, parity),                                \
 	.rs485_de_active_low = DT_INST_PROP(n, nxp_rs485_de_active_low),      \
 	.loopback_en = DT_INST_PROP(n, nxp_loopback),                         \
 	.single_wire = DT_INST_PROP(n, single_wire),	                      \
diff --git a/drivers/serial/uart_native_ptty.c b/drivers/serial/uart_native_ptty.c
deleted file mode 100644
index c0cf3036dd2..00000000000
--- a/drivers/serial/uart_native_ptty.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * Copyright (c) 2018, Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DT_DRV_COMPAT zephyr_native_posix_uart
-
-#include <stdbool.h>
-
-#include <zephyr/drivers/uart.h>
-#include <zephyr/kernel.h>
-
-#include "cmdline.h" /* native_posix command line options header */
-#include "posix_native_task.h"
-#include "uart_native_ptty_bottom.h"
-#include "nsi_host_trampolines.h"
-
-/*
- * UART driver for POSIX ARCH based boards.
- * It can support up to two UARTs.
- *
- * For the first UART:
- *
- * It can either be connected to the process STDIN+STDOUT
- * OR
- * to a dedicated pseudo terminal
- *
- * The 2nd option is the recommended one for interactive use, as the pseudo
- * terminal driver will be configured in "raw" mode, and will therefore behave
- * more like a real UART.
- *
- * When connected to its own pseudo terminal, it may also auto attach a terminal
- * emulator to it, if set so from command line.
- */
-
-static int np_uart_stdin_poll_in(const struct device *dev,
-				 unsigned char *p_char);
-static int np_uart_tty_poll_in(const struct device *dev,
-			       unsigned char *p_char);
-static void np_uart_poll_out(const struct device *dev,
-				      unsigned char out_char);
-
-static bool auto_attach;
-static bool wait_pts;
-static char *auto_attach_cmd = CONFIG_NATIVE_UART_AUTOATTACH_DEFAULT_CMD;
-
-struct native_uart_status {
-	int out_fd; /* File descriptor used for output */
-	int in_fd; /* File descriptor used for input */
-};
-
-static struct native_uart_status native_uart_status_0;
-
-static DEVICE_API(uart, np_uart_driver_api_0) = {
-	.poll_out = np_uart_poll_out,
-#if defined(CONFIG_NATIVE_UART_0_ON_OWN_PTY)
-	.poll_in = np_uart_tty_poll_in,
-#else
-	.poll_in = np_uart_stdin_poll_in,
-#endif
-};
-
-#if defined(CONFIG_UART_NATIVE_POSIX_PORT_1_ENABLE)
-static struct native_uart_status native_uart_status_1;
-
-static DEVICE_API(uart, np_uart_driver_api_1) = {
-	.poll_out = np_uart_poll_out,
-	.poll_in = np_uart_tty_poll_in,
-};
-#endif /* CONFIG_UART_NATIVE_POSIX_PORT_1_ENABLE */
-
-#define ERROR posix_print_error_and_exit
-#define WARN posix_print_warning
-
-
-
-/**
- * @brief Initialize the first native_posix serial port
- *
- * @param dev UART_0 device struct
- *
- * @return 0 (if it fails catastrophically, the execution is terminated)
- */
-static int np_uart_0_init(const struct device *dev)
-{
-	struct native_uart_status *d;
-
-	d = (struct native_uart_status *)dev->data;
-
-	if (IS_ENABLED(CONFIG_NATIVE_UART_0_ON_OWN_PTY)) {
-		int tty_fn = np_uart_open_ptty(dev->name, auto_attach_cmd, auto_attach, wait_pts);
-
-		d->in_fd = tty_fn;
-		d->out_fd = tty_fn;
-	} else { /* NATIVE_UART_0_ON_STDINOUT */
-		d->in_fd  = np_uart_ptty_get_stdin_fileno();
-		d->out_fd = np_uart_ptty_get_stdout_fileno();
-	}
-
-	return 0;
-}
-
-#if defined(CONFIG_UART_NATIVE_POSIX_PORT_1_ENABLE)
-/*
- * Initialize the 2nd UART port.
- * This port will be always attached to its own new pseudoterminal.
- */
-static int np_uart_1_init(const struct device *dev)
-{
-	struct native_uart_status *d;
-	int tty_fn;
-
-	d = (struct native_uart_status *)dev->data;
-
-	tty_fn = np_uart_open_ptty(dev->name, NULL, false, wait_pts);
-
-	d->in_fd = tty_fn;
-	d->out_fd = tty_fn;
-
-	return 0;
-}
-#endif
-
-/*
- * @brief Output a character towards the serial port
- *
- * @param dev UART device struct
- * @param out_char Character to send.
- */
-static void np_uart_poll_out(const struct device *dev,
-				      unsigned char out_char)
-{
-	int ret;
-	struct native_uart_status *d = (struct native_uart_status *)dev->data;
-
-	if (wait_pts) {
-
-		while (1) {
-			int rc = np_uart_slave_connected(d->out_fd);
-
-			if (rc == 1) {
-				break;
-			}
-			k_sleep(K_MSEC(100));
-		}
-	}
-
-	/* The return value of write() cannot be ignored (there is a warning)
-	 * but we do not need the return value for anything.
-	 */
-	ret = nsi_host_write(d->out_fd, &out_char, 1);
-	(void) ret;
-}
-
-/**
- * @brief Poll the device for input.
- *
- * @param dev UART device structure.
- * @param p_char Pointer to character.
- *
- * @retval 0 If a character arrived and was stored in p_char
- * @retval -1 If no character was available to read
- */
-static int __maybe_unused np_uart_stdin_poll_in(const struct device *dev, unsigned char *p_char)
-{
-	int in_f = ((struct native_uart_status *)dev->data)->in_fd;
-	static bool disconnected;
-	int rc;
-
-	if (disconnected == true) {
-		return -1;
-	}
-
-	rc = np_uart_stdin_poll_in_bottom(in_f, p_char);
-	if (rc == -2) {
-		disconnected = true;
-		return -1;
-	}
-
-	return rc;
-}
-
-/**
- * @brief Poll the device for input.
- *
- * @param dev UART device structure.
- * @param p_char Pointer to character.
- *
- * @retval 0 If a character arrived and was stored in p_char
- * @retval -1 If no character was available to read
- */
-static int __maybe_unused np_uart_tty_poll_in(const struct device *dev, unsigned char *p_char)
-{
-	int n = -1;
-	int in_f = ((struct native_uart_status *)dev->data)->in_fd;
-
-	n = nsi_host_read(in_f, p_char, 1);
-	if (n == -1) {
-		return -1;
-	}
-	return 0;
-}
-
-DEVICE_DT_INST_DEFINE(0,
-	    np_uart_0_init, NULL,
-	    (void *)&native_uart_status_0, NULL,
-	    PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY,
-	    &np_uart_driver_api_0);
-
-#if defined(CONFIG_UART_NATIVE_POSIX_PORT_1_ENABLE)
-DEVICE_DT_INST_DEFINE(1,
-	    np_uart_1_init, NULL,
-	    (void *)&native_uart_status_1, NULL,
-	    PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY,
-	    &np_uart_driver_api_1);
-#endif /* CONFIG_UART_NATIVE_POSIX_PORT_1_ENABLE */
-
-static void auto_attach_cmd_cb(char *argv, int offset)
-{
-	auto_attach_cmd = &argv[offset];
-	auto_attach = true;
-}
-
-static void np_add_uart_options(void)
-{
-	if (!IS_ENABLED(CONFIG_NATIVE_UART_0_ON_OWN_PTY)) {
-		return;
-	}
-
-	static struct args_struct_t uart_options[] = {
-	{
-		.is_switch = true,
-		.option = "attach_uart",
-		.type = 'b',
-		.dest = (void *)&auto_attach,
-		.descript = "Automatically attach to the UART terminal"
-	},
-	{
-		.option = "attach_uart_cmd",
-		.name = "\"cmd\"",
-		.type = 's',
-		.call_when_found = auto_attach_cmd_cb,
-		.descript = "Command used to automatically attach to the terminal (implies "
-			    "auto_attach), by default: "
-			    "'" CONFIG_NATIVE_UART_AUTOATTACH_DEFAULT_CMD "'"
-	},
-	IF_ENABLED(CONFIG_UART_NATIVE_WAIT_PTS_READY_ENABLE, (
-		{
-		.is_switch = true,
-		.option = "wait_uart",
-		.type = 'b',
-		.dest = (void *)&wait_pts,
-		.descript = "Hold writes to the uart/pts until a client is connected/ready"
-		},
-	))
-	ARG_TABLE_ENDMARKER
-	};
-
-	native_add_command_line_opts(uart_options);
-}
-
-static void np_cleanup_uart(void)
-{
-	if (IS_ENABLED(CONFIG_NATIVE_UART_0_ON_OWN_PTY)) {
-		if (native_uart_status_0.in_fd != 0) {
-			nsi_host_close(native_uart_status_0.in_fd);
-		}
-	}
-
-#if defined(CONFIG_UART_NATIVE_POSIX_PORT_1_ENABLE)
-	if (native_uart_status_1.in_fd != 0) {
-		nsi_host_close(native_uart_status_1.in_fd);
-	}
-#endif
-}
-
-NATIVE_TASK(np_add_uart_options, PRE_BOOT_1, 11);
-NATIVE_TASK(np_cleanup_uart, ON_EXIT, 99);
diff --git a/drivers/serial/uart_native_ptty_bottom.c b/drivers/serial/uart_native_ptty_bottom.c
deleted file mode 100644
index 7c44ccf68cc..00000000000
--- a/drivers/serial/uart_native_ptty_bottom.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * Copyright (c) 2018, Oticon A/S
- * Copyright (c) 2023, Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#undef _XOPEN_SOURCE
-/* Note: This is used only for interaction with the host C library, and is therefore exempt of
- * coding guidelines rule A.4&5 which applies to the embedded code using embedded libraries
- */
-#define _XOPEN_SOURCE 600
-
-#include <stdbool.h>
-#include <errno.h>
-#include <stddef.h>
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-#include <pty.h>
-#include <fcntl.h>
-#include <sys/select.h>
-#include <unistd.h>
-#include <poll.h>
-#include <nsi_tracing.h>
-
-#define ERROR nsi_print_error_and_exit
-#define WARN nsi_print_warning
-
-/**
- * @brief Poll the device for input.
- *
- * @param in_f   Input file descriptor
- * @param p_char Pointer to character.
- *
- * @retval 0 If a character arrived and was stored in p_char
- * @retval -1 If no character was available to read
- * @retval -2 if the stdin is disconnected
- */
-int np_uart_stdin_poll_in_bottom(int in_f, unsigned char *p_char)
-{
-	if (feof(stdin)) {
-		/*
-		 * The stdinput is fed from a file which finished or the user
-		 * pressed Ctrl+D
-		 */
-		return -2;
-	}
-
-	int n = -1;
-
-	int ready;
-	fd_set readfds;
-	static struct timeval timeout; /* just zero */
-
-	FD_ZERO(&readfds);
-	FD_SET(in_f, &readfds);
-
-	ready = select(in_f+1, &readfds, NULL, NULL, &timeout);
-
-	if (ready == 0) {
-		return -1;
-	} else if (ready == -1) {
-		ERROR("%s: Error on select ()\n", __func__);
-	}
-
-	n = read(in_f, p_char, 1);
-	if ((n == -1) || (n == 0)) {
-		return -1;
-	}
-
-	return 0;
-}
-
-/**
- * @brief Check if the output descriptor has something connected to the slave side
- *
- * @param fd file number
- *
- * @retval 0 Nothing connected yet
- * @retval 1 Something connected to the slave side
- */
-int np_uart_slave_connected(int fd)
-{
-	struct pollfd pfd = { .fd = fd, .events = POLLHUP };
-	int ret;
-
-	ret = poll(&pfd, 1, 0);
-	if (ret == -1) {
-		int err = errno;
-		/*
-		 * Possible errors are:
-		 *  * EINTR :A signal was received => ok
-		 *  * EFAULT and EINVAL: parameters/programming error
-		 *  * ENOMEM no RAM left
-		 */
-		if (err != EINTR) {
-			ERROR("%s: unexpected error during poll, errno=%i,%s\n",
-			      __func__, err, strerror(err));
-		}
-	}
-	if (!(pfd.revents & POLLHUP)) {
-		/* There is now a reader on the slave side */
-		return 1;
-	}
-	return 0;
-}
-
-/**
- * Attempt to connect a terminal emulator to the slave side of the pty
- * If -attach_uart_cmd=<cmd> is provided as a command line option, <cmd> will be
- * used. Otherwise, the default command,
- * CONFIG_NATIVE_UART_AUTOATTACH_DEFAULT_CMD, will be used instead
- */
-static void attach_to_tty(const char *slave_tty, const char *auto_attach_cmd)
-{
-	char command[strlen(auto_attach_cmd) + strlen(slave_tty) + 1];
-
-	sprintf(command, auto_attach_cmd, slave_tty);
-
-	int ret = system(command);
-
-	if (ret != 0) {
-		WARN("Could not attach to the UART with \"%s\"\n", command);
-		WARN("The command returned %i\n", WEXITSTATUS(ret));
-	}
-}
-/**
- * Attempt to allocate and open a new pseudoterminal
- *
- * Returns the file descriptor of the master side
- * If auto_attach was set, it will also attempt to connect a new terminal
- * emulator to its slave side.
- */
-int np_uart_open_ptty(const char *uart_name, const char *auto_attach_cmd,
-		      bool do_auto_attach, bool wait_pts)
-{
-	int master_pty;
-	char *slave_pty_name;
-	struct termios ter;
-	int err_nbr;
-	int ret;
-	int flags;
-
-	master_pty = posix_openpt(O_RDWR | O_NOCTTY);
-	if (master_pty == -1) {
-		ERROR("Could not open a new TTY for the UART\n");
-	}
-	ret = grantpt(master_pty);
-	if (ret == -1) {
-		err_nbr = errno;
-		close(master_pty);
-		ERROR("Could not grant access to the slave PTY side (%i)\n",
-			err_nbr);
-	}
-	ret = unlockpt(master_pty);
-	if (ret == -1) {
-		err_nbr = errno;
-		close(master_pty);
-		ERROR("Could not unlock the slave PTY side (%i)\n", err_nbr);
-	}
-	slave_pty_name = ptsname(master_pty);
-	if (slave_pty_name == NULL) {
-		err_nbr = errno;
-		close(master_pty);
-		ERROR("Error getting slave PTY device name (%i)\n", err_nbr);
-	}
-	/* Set the master PTY as non blocking */
-	flags = fcntl(master_pty, F_GETFL);
-	if (flags == -1) {
-		err_nbr = errno;
-		close(master_pty);
-		ERROR("Could not read the master PTY file status flags (%i)\n",
-			err_nbr);
-	}
-
-	ret = fcntl(master_pty, F_SETFL, flags | O_NONBLOCK);
-	if (ret == -1) {
-		err_nbr = errno;
-		close(master_pty);
-		ERROR("Could not set the master PTY as non-blocking (%i)\n",
-			err_nbr);
-	}
-
-	(void) err_nbr;
-
-	/*
-	 * Set terminal in "raw" mode:
-	 *  Not canonical (no line input)
-	 *  No signal generation from Ctr+{C|Z..}
-	 *  No echoing, no input or output processing
-	 *  No replacing of NL or CR
-	 *  No flow control
-	 */
-	ret = tcgetattr(master_pty, &ter);
-	if (ret == -1) {
-		ERROR("Could not read terminal driver settings\n");
-	}
-	ter.c_cc[VMIN] = 0;
-	ter.c_cc[VTIME] = 0;
-	ter.c_lflag &= ~(ICANON | ISIG | IEXTEN | ECHO);
-	ter.c_iflag &= ~(BRKINT | ICRNL | IGNBRK | IGNCR | INLCR | INPCK
-			 | ISTRIP | IXON | PARMRK);
-	ter.c_oflag &= ~OPOST;
-	ret = tcsetattr(master_pty, TCSANOW, &ter);
-	if (ret == -1) {
-		ERROR("Could not change terminal driver settings\n");
-	}
-
-	nsi_print_trace("%s connected to pseudotty: %s\n",
-			  uart_name, slave_pty_name);
-
-	if (wait_pts) {
-		/*
-		 * This trick sets the HUP flag on the tty master, making it
-		 * possible to detect a client connection using poll.
-		 * The connection of the client would cause the HUP flag to be
-		 * cleared, and in turn set again at disconnect.
-		 */
-		ret = open(slave_pty_name, O_RDWR | O_NOCTTY);
-		if (ret == -1) {
-			err_nbr = errno;
-			ERROR("%s: Could not open terminal from the slave side (%i,%s)\n",
-				__func__, err_nbr, strerror(err_nbr));
-		}
-		ret = close(ret);
-		if (ret == -1) {
-			err_nbr = errno;
-			ERROR("%s: Could not close terminal from the slave side (%i,%s)\n",
-				__func__, err_nbr, strerror(err_nbr));
-		}
-	}
-	if (do_auto_attach) {
-		attach_to_tty(slave_pty_name, auto_attach_cmd);
-	}
-
-	return master_pty;
-}
-
-int np_uart_ptty_get_stdin_fileno(void)
-{
-	return STDIN_FILENO;
-}
-
-int np_uart_ptty_get_stdout_fileno(void)
-{
-	return STDOUT_FILENO;
-}
diff --git a/drivers/serial/uart_native_ptty_bottom.h b/drivers/serial/uart_native_ptty_bottom.h
deleted file mode 100644
index cc5ec282450..00000000000
--- a/drivers/serial/uart_native_ptty_bottom.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2023, Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * "Bottom" of native ptty uart driver
- * When built with the native_simulator this will be built in the runner context,
- * that is, with the host C library, and with the host include paths.
- */
-
-#ifndef DRIVERS_SERIAL_UART_NATIVE_PTTY_BOTTOM_H
-#define DRIVERS_SERIAL_UART_NATIVE_PTTY_BOTTOM_H
-
-#include <stdbool.h>
-#include <stdint.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Note: None of these functions are public interfaces. But internal to the native ptty driver */
-
-int np_uart_stdin_poll_in_bottom(int in_f, unsigned char *p_char);
-int np_uart_slave_connected(int fd);
-int np_uart_open_ptty(const char *uart_name, const char *auto_attach_cmd,
-		      bool do_auto_attach, bool wait_pts);
-int np_uart_ptty_get_stdin_fileno(void);
-int np_uart_ptty_get_stdout_fileno(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* DRIVERS_SERIAL_UART_NATIVE_PTTY_BOTTOM_H */
diff --git a/drivers/serial/uart_native_pty.c b/drivers/serial/uart_native_pty.c
new file mode 100644
index 00000000000..c4da0450b25
--- /dev/null
+++ b/drivers/serial/uart_native_pty.c
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2018, Oticon A/S
+ * Copyright (c) 2025, Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#if DT_HAS_COMPAT_STATUS_OKAY(zephyr_native_posix_uart)
+#define DT_DRV_COMPAT zephyr_native_posix_uart
+#warning "zephyr,native-posix-uart is deprecated in favor of zephyr,native-pty-uart"
+#else
+#define DT_DRV_COMPAT zephyr_native_pty_uart
+#endif
+
+#include <stdbool.h>
+#include <zephyr/drivers/uart.h>
+#include <zephyr/kernel.h>
+#include <cmdline.h> /* native_sim command line options header */
+#include <posix_native_task.h>
+#include <nsi_host_trampolines.h>
+#include <nsi_tracing.h>
+#include "uart_native_pty_bottom.h"
+
+#define ERROR posix_print_error_and_exit
+#define WARN posix_print_warning
+
+/*
+ * UART driver for native simulator based boards.
+ * It can support a configurable number of UARTs.
+ *
+ * One (and only one) of this can be connected to the process STDIN+STDOUT otherwise, they are
+ * connected to a dedicated pseudo terminal.
+ *
+ * Connecting to a dedicated PTY is the recommended option for interactive use, as the pseudo
+ * terminal driver will be configured in "raw" mode and will therefore behave more like a real UART.
+ *
+ * When connected to its own pseudo terminal, it may also auto attach a terminal emulator to it,
+ * if set so from command line.
+ */
+
+struct native_pty_status {
+	int out_fd;       /* File descriptor used for output */
+	int in_fd;        /* File descriptor used for input */
+	bool on_stdinout; /* This UART is connected to a PTY and not STDIN/OUT */
+
+	bool auto_attach;      /* For PTY, attach a terminal emulator automatically */
+	char *auto_attach_cmd; /* If auto_attach, which command to launch the terminal emulator */
+	bool wait_pts;         /* Hold writes to the uart/pts until a client is connected/ready */
+	bool cmd_request_stdinout; /* User requested to connect this UART to the stdin/out */
+};
+
+static void np_uart_poll_out(const struct device *dev, unsigned char out_char);
+static int np_uart_poll_in(const struct device *dev, unsigned char *p_char);
+static int np_uart_init(const struct device *dev);
+
+static DEVICE_API(uart, np_uart_driver_api) = {
+	.poll_out = np_uart_poll_out,
+	.poll_in = np_uart_poll_in,
+};
+
+#define NATIVE_PTY_INSTANCE(inst)                                        \
+	static struct native_pty_status native_pty_status_##inst;        \
+								         \
+	DEVICE_DT_INST_DEFINE(inst, np_uart_init, NULL,                  \
+			      (void *)&native_pty_status_##inst, NULL,   \
+			      PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
+			      &np_uart_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(NATIVE_PTY_INSTANCE);
+
+/**
+ * @brief Initialize a native_pty serial port
+ *
+ * @param dev uart device struct
+ *
+ * @return 0 (if it fails catastrophically, the execution is terminated)
+ */
+static int np_uart_init(const struct device *dev)
+{
+
+	static bool stdinout_used;
+	struct native_pty_status *d;
+
+	d = (struct native_pty_status *)dev->data;
+
+	if (IS_ENABLED(CONFIG_UART_NATIVE_PTY_0_ON_STDINOUT)) {
+		static bool first_node = true;
+
+		if (first_node) {
+			d->on_stdinout = true;
+		}
+		first_node = false;
+	}
+
+	if (d->cmd_request_stdinout) {
+		if (stdinout_used) {
+			nsi_print_warning("%s requested to connect to STDIN/OUT, but another UART"
+					  " is already connected to it => ignoring request.\n",
+					  dev->name);
+		} else {
+			d->on_stdinout = true;
+		}
+	}
+
+	if (d->on_stdinout == true) {
+		d->in_fd  = np_uart_pty_get_stdin_fileno();
+		d->out_fd = np_uart_pty_get_stdout_fileno();
+		stdinout_used = true;
+	} else {
+		if (d->auto_attach_cmd == NULL) {
+			d->auto_attach_cmd = CONFIG_UART_NATIVE_PTY_AUTOATTACH_DEFAULT_CMD;
+		} else { /* Running with --attach_uart_cmd, implies --attach_uart */
+			d->auto_attach = true;
+		}
+		int tty_fn = np_uart_open_pty(dev->name, d->auto_attach_cmd, d->auto_attach,
+					      d->wait_pts);
+		d->in_fd = tty_fn;
+		d->out_fd = tty_fn;
+	}
+
+	return 0;
+}
+
+/*
+ * @brief Output a character towards the serial port
+ *
+ * @param dev UART device struct
+ * @param out_char Character to send.
+ */
+static void np_uart_poll_out(const struct device *dev, unsigned char out_char)
+{
+	int ret;
+	struct native_pty_status *d = (struct native_pty_status *)dev->data;
+
+	if (d->wait_pts) {
+		while (1) {
+			int rc = np_uart_slave_connected(d->out_fd);
+
+			if (rc == 1) {
+				break;
+			}
+			k_sleep(K_MSEC(100));
+		}
+	}
+
+	/* The return value of write() cannot be ignored (there is a warning)
+	 * but we do not need the return value for anything.
+	 */
+	ret = nsi_host_write(d->out_fd, &out_char, 1);
+	(void) ret;
+}
+
+/**
+ * @brief Poll the device for input.
+ *
+ * @param dev UART device structure.
+ * @param p_char Pointer to character.
+ *
+ * @retval 0 If a character arrived and was stored in p_char
+ * @retval -1 If no character was available to read
+ */
+static int np_uart_stdin_poll_in(const struct device *dev, unsigned char *p_char)
+{
+	int in_f = ((struct native_pty_status *)dev->data)->in_fd;
+	static bool disconnected;
+	int rc;
+
+	if (disconnected == true) {
+		return -1;
+	}
+
+	rc = np_uart_stdin_poll_in_bottom(in_f, p_char);
+	if (rc == -2) {
+		disconnected = true;
+		return -1;
+	}
+
+	return rc;
+}
+
+/**
+ * @brief Poll the device for input.
+ *
+ * @param dev UART device structure.
+ * @param p_char Pointer to character.
+ *
+ * @retval 0 If a character arrived and was stored in p_char
+ * @retval -1 If no character was available to read
+ */
+static int np_uart_pty_poll_in(const struct device *dev, unsigned char *p_char)
+{
+	int n = -1;
+	int in_f = ((struct native_pty_status *)dev->data)->in_fd;
+
+	n = nsi_host_read(in_f, p_char, 1);
+	if (n == -1) {
+		return -1;
+	}
+	return 0;
+}
+
+static int np_uart_poll_in(const struct device *dev, unsigned char *p_char)
+{
+	if (((struct native_pty_status *)dev->data)->on_stdinout) {
+		return np_uart_stdin_poll_in(dev, p_char);
+	} else {
+		return np_uart_pty_poll_in(dev, p_char);
+	}
+}
+
+#define NATIVE_PTY_SET_AUTO_ATTACH_CMD(inst, cmd)      \
+	native_pty_status_##inst.auto_attach_cmd = cmd;
+#define NATIVE_PTY_SET_AUTO_ATTACH(inst, value)        \
+	native_pty_status_##inst.auto_attach = value;
+#define NATIVE_PTY_SET_WAIT_PTS(inst, value)           \
+	native_pty_status_##inst.wait_pts = value;
+
+static void auto_attach_cmd_cb(char *argv, int offset)
+{
+	DT_INST_FOREACH_STATUS_OKAY_VARGS(NATIVE_PTY_SET_AUTO_ATTACH_CMD, &argv[offset]);
+	DT_INST_FOREACH_STATUS_OKAY_VARGS(NATIVE_PTY_SET_AUTO_ATTACH, true);
+}
+
+static void auto_attach_cb(char *argv, int offset)
+{
+	DT_INST_FOREACH_STATUS_OKAY_VARGS(NATIVE_PTY_SET_AUTO_ATTACH, true);
+}
+
+static void wait_pts_cb(char *argv, int offset)
+{
+	DT_INST_FOREACH_STATUS_OKAY_VARGS(NATIVE_PTY_SET_WAIT_PTS, true);
+}
+
+#define INST_NAME(inst) DEVICE_DT_NAME(DT_DRV_INST(inst))
+
+#define NATIVE_PTY_COMMAND_LINE_OPTS(inst)                                                         \
+	{                                                                                          \
+		.is_switch = true,                                                                 \
+		.option = INST_NAME(inst) "_stdinout",                                             \
+		.type = 'b',                                                                       \
+		.dest = &native_pty_status_##inst.cmd_request_stdinout,                            \
+		.descript = "Connect "INST_NAME(inst)" to STDIN/OUT instead of a PTY"              \
+			    " (can only be done for one UART)"                                     \
+	},                                                                                         \
+	{                                                                                          \
+		.is_switch = true,                                                                 \
+		.option = INST_NAME(inst) "_attach_uart",                                          \
+		.type = 'b',                                                                       \
+		.dest = &native_pty_status_##inst.auto_attach,                                     \
+		.descript = "Automatically attach "INST_NAME(inst)" to a terminal emulator."       \
+			    " (only applicable when connected to PTYs)"                            \
+	},                                                                                         \
+	{                                                                                          \
+		.option = INST_NAME(inst) "_attach_uart_cmd",                                      \
+		.name = "\"cmd\"",                                                                 \
+		.type = 's',                                                                       \
+		.dest = &native_pty_status_##inst.auto_attach_cmd,                                 \
+		.descript = "Command used to automatically attach to the terminal "INST_NAME(inst) \
+			    " (implies "INST_NAME(inst)"_auto_attach), by default: "               \
+			    "'" CONFIG_UART_NATIVE_PTY_AUTOATTACH_DEFAULT_CMD "'"                  \
+			    " (only applicable when connected to PTYs)"                            \
+	},                                                                                         \
+	{                                                                                          \
+		.is_switch = true,                                                                 \
+		.option = INST_NAME(inst) "_wait_uart",                                            \
+		.type = 'b',                                                                       \
+		.dest = &native_pty_status_##inst.wait_pts,                                        \
+		.descript = "Hold writes to "INST_NAME(inst)" until a client is connected/ready"   \
+			   " (only applicable when connected to PTYs)"                             \
+	},
+
+static void np_add_uart_options(void)
+{
+	static struct args_struct_t uart_options[] = {
+	/* Set of parameters that apply to all PTY UARTs: */
+	{
+		.is_switch = true,
+		.option = "attach_uart",
+		.type = 'b',
+		.call_when_found = auto_attach_cb,
+		.descript = "Automatically attach all PTY UARTs to a terminal emulator."
+			    " (only applicable when connected to PTYs)"
+	},
+	{
+		.option = "attach_uart_cmd",
+		.name = "\"cmd\"",
+		.type = 's',
+		.call_when_found = auto_attach_cmd_cb,
+		.descript = "Command used to automatically attach all PTY UARTs to a terminal "
+			    "emulator (implies auto_attach), by default: "
+			    "'" CONFIG_UART_NATIVE_PTY_AUTOATTACH_DEFAULT_CMD "'"
+			    " (only applicable when connected to PTYs)"
+	},
+	{
+		.is_switch = true,
+		.option = "wait_uart",
+		.type = 'b',
+		.call_when_found = wait_pts_cb,
+		.descript = "Hold writes to all PTY UARTs until a client is connected/ready"
+			    " (only applicable when connected to PTYs)"
+	},
+	/* Set of parameters that apply to each individual PTY UART: */
+	DT_INST_FOREACH_STATUS_OKAY(NATIVE_PTY_COMMAND_LINE_OPTS)
+	ARG_TABLE_ENDMARKER
+	};
+
+	native_add_command_line_opts(uart_options);
+}
+
+#define NATIVE_PTY_CLEANUP(inst)                                                                \
+	if ((!native_pty_status_##inst.on_stdinout) && (native_pty_status_##inst.in_fd != 0)) { \
+		nsi_host_close(native_pty_status_##inst.in_fd);                                 \
+		native_pty_status_##inst.in_fd = 0;                                             \
+	}
+
+static void np_cleanup_uart(void)
+{
+	DT_INST_FOREACH_STATUS_OKAY(NATIVE_PTY_CLEANUP);
+}
+
+NATIVE_TASK(np_add_uart_options, PRE_BOOT_1, 11);
+NATIVE_TASK(np_cleanup_uart, ON_EXIT, 99);
diff --git a/drivers/serial/uart_native_pty_bottom.c b/drivers/serial/uart_native_pty_bottom.c
new file mode 100644
index 00000000000..0c5546cdeda
--- /dev/null
+++ b/drivers/serial/uart_native_pty_bottom.c
@@ -0,0 +1,248 @@
+/*
+ * Copyright (c) 2018, Oticon A/S
+ * Copyright (c) 2023, Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#undef _XOPEN_SOURCE
+/* Note: This is used only for interaction with the host C library, and is therefore exempt of
+ * coding guidelines rule A.4&5 which applies to the embedded code using embedded libraries
+ */
+#define _XOPEN_SOURCE 600
+
+#include <stdbool.h>
+#include <errno.h>
+#include <stddef.h>
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <pty.h>
+#include <fcntl.h>
+#include <sys/select.h>
+#include <unistd.h>
+#include <poll.h>
+#include <nsi_tracing.h>
+
+#define ERROR nsi_print_error_and_exit
+#define WARN nsi_print_warning
+
+/**
+ * @brief Poll the device for input.
+ *
+ * @param in_f   Input file descriptor
+ * @param p_char Pointer to character.
+ *
+ * @retval 0 If a character arrived and was stored in p_char
+ * @retval -1 If no character was available to read
+ * @retval -2 if the stdin is disconnected
+ */
+int np_uart_stdin_poll_in_bottom(int in_f, unsigned char *p_char)
+{
+	if (feof(stdin)) {
+		/*
+		 * The stdinput is fed from a file which finished or the user
+		 * pressed Ctrl+D
+		 */
+		return -2;
+	}
+
+	int n = -1;
+
+	int ready;
+	fd_set readfds;
+	static struct timeval timeout; /* just zero */
+
+	FD_ZERO(&readfds);
+	FD_SET(in_f, &readfds);
+
+	ready = select(in_f+1, &readfds, NULL, NULL, &timeout);
+
+	if (ready == 0) {
+		return -1;
+	} else if (ready == -1) {
+		ERROR("%s: Error on select ()\n", __func__);
+	}
+
+	n = read(in_f, p_char, 1);
+	if ((n == -1) || (n == 0)) {
+		return -1;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Check if the output descriptor has something connected to the slave side
+ *
+ * @param fd file number
+ *
+ * @retval 0 Nothing connected yet
+ * @retval 1 Something connected to the slave side
+ */
+int np_uart_slave_connected(int fd)
+{
+	struct pollfd pfd = { .fd = fd, .events = POLLHUP };
+	int ret;
+
+	ret = poll(&pfd, 1, 0);
+	if (ret == -1) {
+		int err = errno;
+		/*
+		 * Possible errors are:
+		 *  * EINTR :A signal was received => ok
+		 *  * EFAULT and EINVAL: parameters/programming error
+		 *  * ENOMEM no RAM left
+		 */
+		if (err != EINTR) {
+			ERROR("%s: unexpected error during poll, errno=%i,%s\n",
+			      __func__, err, strerror(err));
+		}
+	}
+	if (!(pfd.revents & POLLHUP)) {
+		/* There is now a reader on the slave side */
+		return 1;
+	}
+	return 0;
+}
+
+/**
+ * Attempt to connect a terminal emulator to the slave side of the pty
+ * If -attach_uart_cmd=<cmd> is provided as a command line option, <cmd> will be
+ * used. Otherwise, the default command,
+ * CONFIG_NATIVE_UART_AUTOATTACH_DEFAULT_CMD, will be used instead
+ */
+static void attach_to_pty(const char *slave_pty, const char *auto_attach_cmd)
+{
+	char command[strlen(auto_attach_cmd) + strlen(slave_pty) + 1];
+
+	sprintf(command, auto_attach_cmd, slave_pty);
+
+	int ret = system(command);
+
+	if (ret != 0) {
+		WARN("Could not attach to the UART with \"%s\"\n", command);
+		WARN("The command returned %i\n", WEXITSTATUS(ret));
+	}
+}
+/**
+ * Attempt to allocate and open a new pseudoterminal
+ *
+ * Returns the file descriptor of the master side
+ * If auto_attach was set, it will also attempt to connect a new terminal
+ * emulator to its slave side.
+ */
+int np_uart_open_pty(const char *uart_name, const char *auto_attach_cmd,
+		     bool do_auto_attach, bool wait_pts)
+{
+	int master_pty;
+	char *slave_pty_name;
+	struct termios ter;
+	int err_nbr;
+	int ret;
+	int flags;
+
+	master_pty = posix_openpt(O_RDWR | O_NOCTTY);
+	if (master_pty == -1) {
+		ERROR("Could not open a new PTY for the UART\n");
+	}
+	ret = grantpt(master_pty);
+	if (ret == -1) {
+		err_nbr = errno;
+		close(master_pty);
+		ERROR("Could not grant access to the slave PTY side (%i)\n",
+			err_nbr);
+	}
+	ret = unlockpt(master_pty);
+	if (ret == -1) {
+		err_nbr = errno;
+		close(master_pty);
+		ERROR("Could not unlock the slave PTY side (%i)\n", err_nbr);
+	}
+	slave_pty_name = ptsname(master_pty);
+	if (slave_pty_name == NULL) {
+		err_nbr = errno;
+		close(master_pty);
+		ERROR("Error getting slave PTY device name (%i)\n", err_nbr);
+	}
+	/* Set the master PTY as non blocking */
+	flags = fcntl(master_pty, F_GETFL);
+	if (flags == -1) {
+		err_nbr = errno;
+		close(master_pty);
+		ERROR("Could not read the master PTY file status flags (%i)\n",
+			err_nbr);
+	}
+
+	ret = fcntl(master_pty, F_SETFL, flags | O_NONBLOCK);
+	if (ret == -1) {
+		err_nbr = errno;
+		close(master_pty);
+		ERROR("Could not set the master PTY as non-blocking (%i)\n",
+			err_nbr);
+	}
+
+	(void) err_nbr;
+
+	/*
+	 * Set terminal in "raw" mode:
+	 *  Not canonical (no line input)
+	 *  No signal generation from Ctr+{C|Z..}
+	 *  No echoing, no input or output processing
+	 *  No replacing of NL or CR
+	 *  No flow control
+	 */
+	ret = tcgetattr(master_pty, &ter);
+	if (ret == -1) {
+		ERROR("Could not read terminal driver settings\n");
+	}
+	ter.c_cc[VMIN] = 0;
+	ter.c_cc[VTIME] = 0;
+	ter.c_lflag &= ~(ICANON | ISIG | IEXTEN | ECHO);
+	ter.c_iflag &= ~(BRKINT | ICRNL | IGNBRK | IGNCR | INLCR | INPCK
+			 | ISTRIP | IXON | PARMRK);
+	ter.c_oflag &= ~OPOST;
+	ret = tcsetattr(master_pty, TCSANOW, &ter);
+	if (ret == -1) {
+		ERROR("Could not change terminal driver settings\n");
+	}
+
+	nsi_print_trace("%s connected to pseudotty: %s\n",
+			  uart_name, slave_pty_name);
+
+	if (wait_pts) {
+		/*
+		 * This trick sets the HUP flag on the pty master, making it
+		 * possible to detect a client connection using poll.
+		 * The connection of the client would cause the HUP flag to be
+		 * cleared, and in turn set again at disconnect.
+		 */
+		ret = open(slave_pty_name, O_RDWR | O_NOCTTY);
+		if (ret == -1) {
+			err_nbr = errno;
+			ERROR("%s: Could not open terminal from the slave side (%i,%s)\n",
+				__func__, err_nbr, strerror(err_nbr));
+		}
+		ret = close(ret);
+		if (ret == -1) {
+			err_nbr = errno;
+			ERROR("%s: Could not close terminal from the slave side (%i,%s)\n",
+				__func__, err_nbr, strerror(err_nbr));
+		}
+	}
+	if (do_auto_attach) {
+		attach_to_pty(slave_pty_name, auto_attach_cmd);
+	}
+
+	return master_pty;
+}
+
+int np_uart_pty_get_stdin_fileno(void)
+{
+	return STDIN_FILENO;
+}
+
+int np_uart_pty_get_stdout_fileno(void)
+{
+	return STDOUT_FILENO;
+}
diff --git a/drivers/serial/uart_native_pty_bottom.h b/drivers/serial/uart_native_pty_bottom.h
new file mode 100644
index 00000000000..5cbf2783795
--- /dev/null
+++ b/drivers/serial/uart_native_pty_bottom.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2023, Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * "Bottom" of native PTY UART driver
+ * When built with the native_simulator this will be built in the runner context,
+ * that is, with the host C library, and with the host include paths.
+ */
+
+#ifndef DRIVERS_SERIAL_UART_NATIVE_PTTY_BOTTOM_H
+#define DRIVERS_SERIAL_UART_NATIVE_PTTY_BOTTOM_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Note: None of these functions are public interfaces. But internal to the native ptty driver */
+
+int np_uart_stdin_poll_in_bottom(int in_f, unsigned char *p_char);
+int np_uart_slave_connected(int fd);
+int np_uart_open_pty(const char *uart_name, const char *auto_attach_cmd,
+		     bool do_auto_attach, bool wait_pts);
+int np_uart_pty_get_stdin_fileno(void);
+int np_uart_pty_get_stdout_fileno(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DRIVERS_SERIAL_UART_NATIVE_PTTY_BOTTOM_H */
diff --git a/drivers/serial/uart_native_tty.c b/drivers/serial/uart_native_tty.c
index 98006616a5a..2c559c7bd36 100644
--- a/drivers/serial/uart_native_tty.c
+++ b/drivers/serial/uart_native_tty.c
@@ -48,6 +48,10 @@ struct native_tty_data {
 	uart_irq_callback_user_data_t callback;
 	/* IRQ callback data */
 	void *cb_data;
+	/* Instance-specific RX thread. */
+	struct k_thread rx_thread;
+	/* RX thread stack. */
+	K_KERNEL_STACK_MEMBER(rx_stack, CONFIG_ARCH_POSIX_RECOMMENDED_STACK_SIZE);
 #endif
 };
 
@@ -56,8 +60,6 @@ struct native_tty_config {
 };
 
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
-static struct k_thread rx_thread;
-static K_KERNEL_STACK_DEFINE(rx_stack, CONFIG_ARCH_POSIX_RECOMMENDED_STACK_SIZE);
 #define NATIVE_TTY_INIT_LEVEL POST_KERNEL
 #else
 #define NATIVE_TTY_INIT_LEVEL PRE_KERNEL_1
@@ -311,8 +313,10 @@ static void native_tty_uart_irq_callback_set(const struct device *dev,
 
 static void native_tty_irq_init(const struct device *dev)
 {
+	struct native_tty_data *data = dev->data;
+
 	/* Create a thread which will wait for data - replacement for IRQ */
-	k_thread_create(&rx_thread, rx_stack, K_KERNEL_STACK_SIZEOF(rx_stack),
+	k_thread_create(&data->rx_thread, data->rx_stack, K_KERNEL_STACK_SIZEOF(data->rx_stack),
 			native_tty_uart_irq_function,
 			(void *)dev, NULL, NULL,
 			K_HIGHEST_THREAD_PRIO, 0, K_NO_WAIT);
diff --git a/drivers/serial/uart_neorv32.c b/drivers/serial/uart_neorv32.c
index c4668e7e27c..2dff1ea7ee8 100644
--- a/drivers/serial/uart_neorv32.c
+++ b/drivers/serial/uart_neorv32.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
+ * Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,40 +9,46 @@
 #include <zephyr/device.h>
 #include <zephyr/drivers/syscon.h>
 #include <zephyr/drivers/uart.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
 #include <zephyr/pm/device.h>
+#include <zephyr/spinlock.h>
 #include <zephyr/sys/sys_io.h>
-#include <zephyr/logging/log.h>
-#include <zephyr/irq.h>
 
 #include <soc.h>
 
 LOG_MODULE_REGISTER(uart_neorv32, CONFIG_UART_LOG_LEVEL);
 
 /* NEORV32 UART registers offsets */
-#define NEORV32_UART_CTRL_OFFSET 0x00
-#define NEORV32_UART_DATA_OFFSET 0x04
-
-/* UART_CTRL register bits */
-#define NEORV32_UART_CTRL_EN              BIT(0)
-#define NEORV32_UART_CTRL_SIM_MODE        BIT(1)
-#define NEORV32_UART_CTRL_HWFC_EN         BIT(2)
-#define NEORV32_UART_CTRL_PRSC_POS        3U
-#define NEORV32_UART_CTRL_PRSC_MASK       BIT_MASK(3)
-#define NEORV32_UART_CTRL_BAUD_POS        6U
-#define NEORV32_UART_CTRL_BAUD_MASK       BIT_MASK(10)
-#define NEORV32_UART_CTRL_RX_NEMPTY       BIT(16)
-#define NEORV32_UART_CTRL_RX_HALF         BIT(17)
-#define NEORV32_UART_CTRL_RX_FULL         BIT(18)
-#define NEORV32_UART_CTRL_TX_NEMPTY       BIT(19)
-#define NEORV32_UART_CTRL_TX_HALF         BIT(20)
-#define NEORV32_UART_CTRL_TX_FULL         BIT(21)
-#define NEORV32_UART_CTRL_IRQ_RX_NEMPTY   BIT(22)
-#define NEORV32_UART_CTRL_IRQ_RX_HALF     BIT(23)
-#define NEORV32_UART_CTRL_IRQ_RX_FULL     BIT(24)
-#define NEORV32_UART_CTRL_IRQ_TX_EMPTY    BIT(25)
-#define NEORV32_UART_CTRL_IRQ_TX_NHALF    BIT(26)
-#define NEORV32_UART_CTRL_RX_OVER         BIT(30)
-#define NEORV32_UART_CTRL_TX_BUSY         BIT(31)
+#define NEORV32_UART_CTRL 0x00
+#define NEORV32_UART_DATA 0x04
+
+/* NEORV32 UART CTRL register bits */
+#define NEORV32_UART_CTRL_EN               BIT(0)
+#define NEORV32_UART_CTRL_SIM_MODE         BIT(1)
+#define NEORV32_UART_CTRL_HWFC_EN          BIT(2)
+#define NEORV32_UART_CTRL_PRSC             GENMASK(5, 3)
+#define NEORV32_UART_CTRL_BAUD             GENMASK(15, 6)
+#define NEORV32_UART_CTRL_RX_NEMPTY        BIT(16)
+#define NEORV32_UART_CTRL_RX_HALF          BIT(17)
+#define NEORV32_UART_CTRL_RX_FULL          BIT(18)
+#define NEORV32_UART_CTRL_TX_EMPTY         BIT(19)
+#define NEORV32_UART_CTRL_TX_NHALF         BIT(20)
+#define NEORV32_UART_CTRL_TX_FULL          BIT(21)
+#define NEORV32_UART_CTRL_IRQ_RX_NEMPTY    BIT(22)
+#define NEORV32_UART_CTRL_IRQ_RX_HALF      BIT(23)
+#define NEORV32_UART_CTRL_IRQ_RX_FULL      BIT(24)
+#define NEORV32_UART_CTRL_IRQ_TX_EMPTY     BIT(25)
+#define NEORV32_UART_CTRL_IRQ_TX_NHALF     BIT(26)
+#define NEORV32_UART_CTRL_UART_CTRL_RX_CLR BIT(28)
+#define NEORV32_UART_CTRL_UART_CTRL_TX_CLR BIT(29)
+#define NEORV32_UART_CTRL_RX_OVER          BIT(30)
+#define NEORV32_UART_CTRL_TX_BUSY          BIT(31)
+
+/* NEORV32 UART DATA register bits */
+#define NEORV32_UART_DATA_RTX          GENMASK(7, 0)
+#define NEORV32_UART_DATA_RX_FIFO_SIZE GENMASK(11, 8)
+#define NEORV32_UART_DATA_TX_FIFO_SIZE GENMASK(15, 12)
 
 struct neorv32_uart_config {
 	const struct device *syscon;
@@ -50,18 +56,16 @@ struct neorv32_uart_config {
 	mm_reg_t base;
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 	void (*irq_config_func)(const struct device *dev);
-	unsigned int tx_irq;
-	unsigned int rx_irq;
 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
 };
 
 struct neorv32_uart_data {
 	struct uart_config uart_cfg;
-	uint32_t last_data;
+	struct k_spinlock lock;
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
-	struct k_timer timer;
 	uart_irq_callback_user_data_t callback;
 	void *callback_data;
+	uint32_t last_ctrl;
 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
 };
 
@@ -69,44 +73,37 @@ static inline uint32_t neorv32_uart_read_ctrl(const struct device *dev)
 {
 	const struct neorv32_uart_config *config = dev->config;
 
-	return sys_read32(config->base + NEORV32_UART_CTRL_OFFSET);
+	return sys_read32(config->base + NEORV32_UART_CTRL);
 }
 
 static inline void neorv32_uart_write_ctrl(const struct device *dev, uint32_t ctrl)
 {
 	const struct neorv32_uart_config *config = dev->config;
 
-	sys_write32(ctrl, config->base + NEORV32_UART_CTRL_OFFSET);
+	sys_write32(ctrl, config->base + NEORV32_UART_CTRL);
 }
 
 static inline uint32_t neorv32_uart_read_data(const struct device *dev)
 {
 	const struct neorv32_uart_config *config = dev->config;
-	struct neorv32_uart_data *data = dev->data;
-	uint32_t reg;
-
-	/* Cache status bits as they are cleared upon read */
-	reg = sys_read32(config->base + NEORV32_UART_DATA_OFFSET);
-	data->last_data = reg;
 
-	return reg;
+	return sys_read32(config->base + NEORV32_UART_DATA);
 }
 
 static inline void neorv32_uart_write_data(const struct device *dev, uint32_t data)
 {
 	const struct neorv32_uart_config *config = dev->config;
 
-	sys_write32(data, config->base + NEORV32_UART_DATA_OFFSET);
+	sys_write32(data, config->base + NEORV32_UART_DATA);
 }
 
 static int neorv32_uart_poll_in(const struct device *dev, unsigned char *c)
 {
-	uint32_t data;
-
-	data = neorv32_uart_read_data(dev);
+	uint32_t ctrl;
 
-	if ((data & NEORV32_UART_CTRL_RX_NEMPTY) != 0) {
-		*c = data & BIT_MASK(8);
+	ctrl = neorv32_uart_read_ctrl(dev);
+	if ((ctrl & NEORV32_UART_CTRL_RX_NEMPTY) != 0U) {
+		*c = neorv32_uart_read_data(dev) & NEORV32_UART_DATA_RTX;
 		return 0;
 	}
 
@@ -115,7 +112,7 @@ static int neorv32_uart_poll_in(const struct device *dev, unsigned char *c)
 
 static void neorv32_uart_poll_out(const struct device *dev, unsigned char c)
 {
-	while ((neorv32_uart_read_ctrl(dev) & NEORV32_UART_CTRL_TX_BUSY) != 0) {
+	while ((neorv32_uart_read_ctrl(dev) & NEORV32_UART_CTRL_TX_FULL) != 0U) {
 	}
 
 	neorv32_uart_write_data(dev, c);
@@ -123,11 +120,15 @@ static void neorv32_uart_poll_out(const struct device *dev, unsigned char c)
 
 static int neorv32_uart_configure(const struct device *dev, const struct uart_config *cfg)
 {
+	const uint16_t baudxx_max = FIELD_GET(NEORV32_UART_CTRL_BAUD, NEORV32_UART_CTRL_BAUD);
+	const uint8_t prscx_max = FIELD_GET(NEORV32_UART_CTRL_PRSC, NEORV32_UART_CTRL_PRSC);
 	const struct neorv32_uart_config *config = dev->config;
 	struct neorv32_uart_data *data = dev->data;
-	uint32_t ctrl = NEORV32_UART_CTRL_EN;
+	k_spinlock_key_t key;
 	uint16_t baudxx = 0;
 	uint8_t prscx = 0;
+	uint32_t ctrl;
+	bool hwfc_en;
 	uint32_t clk;
 	int err;
 
@@ -143,20 +144,17 @@ static int neorv32_uart_configure(const struct device *dev, const struct uart_co
 		return -ENOTSUP;
 	}
 
-	switch (cfg->parity) {
-	case UART_CFG_PARITY_NONE:
-		break;
-	default:
-		LOG_ERR("unsupported parity mode %d", cfg->parity);
+	if (cfg->parity != UART_CFG_PARITY_NONE) {
+		LOG_ERR("hardware only supports parity mode none");
 		return -ENOTSUP;
 	}
 
 	switch (cfg->flow_ctrl) {
 	case UART_CFG_FLOW_CTRL_NONE:
-		ctrl |= 0;
+		hwfc_en = false;
 		break;
 	case UART_CFG_FLOW_CTRL_RTS_CTS:
-		ctrl |= NEORV32_UART_CTRL_HWFC_EN;
+		hwfc_en = true;
 		break;
 	default:
 		LOG_ERR("unsupported flow control mode %d", cfg->flow_ctrl);
@@ -179,7 +177,7 @@ static int neorv32_uart_configure(const struct device *dev, const struct uart_co
 	 * clock / 2.
 	 */
 	baudxx = clk / (2 * cfg->baudrate);
-	while (baudxx >= NEORV32_UART_CTRL_BAUD_MASK) {
+	while (baudxx >= baudxx_max) {
 		if ((prscx == 2) || (prscx == 4)) {
 			baudxx >>= 3;
 		} else {
@@ -189,20 +187,35 @@ static int neorv32_uart_configure(const struct device *dev, const struct uart_co
 		prscx++;
 	}
 
-	if (prscx > NEORV32_UART_CTRL_PRSC_MASK) {
+	if (prscx > prscx_max) {
 		LOG_ERR("unsupported baud rate %d", cfg->baudrate);
 		return -ENOTSUP;
 	}
 
-	ctrl |= (baudxx - 1) << NEORV32_UART_CTRL_BAUD_POS;
-	ctrl |= prscx << NEORV32_UART_CTRL_PRSC_POS;
+	key = k_spin_lock(&data->lock);
+
+	ctrl = neorv32_uart_read_ctrl(dev);
+	ctrl |= NEORV32_UART_CTRL_EN;
+
+	if (hwfc_en) {
+		ctrl |= NEORV32_UART_CTRL_HWFC_EN;
+	} else {
+		ctrl &= ~NEORV32_UART_CTRL_HWFC_EN;
+	}
+
+	ctrl &= ~(NEORV32_UART_CTRL_BAUD | NEORV32_UART_CTRL_PRSC);
+	ctrl |= FIELD_PREP(NEORV32_UART_CTRL_BAUD, baudxx - 1U) |
+		FIELD_PREP(NEORV32_UART_CTRL_PRSC, prscx);
 
-	data->uart_cfg = *cfg;
 	neorv32_uart_write_ctrl(dev, ctrl);
+	data->uart_cfg = *cfg;
+
+	k_spin_unlock(&data->lock, key);
 
 	return 0;
 }
 
+#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
 static int neorv32_uart_config_get(const struct device *dev, struct uart_config *cfg)
 {
 	struct neorv32_uart_data *data = dev->data;
@@ -213,30 +226,28 @@ static int neorv32_uart_config_get(const struct device *dev, struct uart_config
 
 	return 0;
 }
+#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
 
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
-static int neorv32_uart_fifo_fill(const struct device *dev, const uint8_t *tx_data, int len)
+static int neorv32_uart_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size)
 {
-	uint32_t ctrl;
+	int count = 0;
 
-	if (len <= 0) {
+	if (size <= 0) {
 		return 0;
 	}
 
 	__ASSERT_NO_MSG(tx_data != NULL);
 
-	ctrl = neorv32_uart_read_ctrl(dev);
-	if ((ctrl & NEORV32_UART_CTRL_TX_BUSY) == 0) {
-		neorv32_uart_write_data(dev, *tx_data);
-		return 1;
+	while (count < size && (neorv32_uart_read_ctrl(dev) & NEORV32_UART_CTRL_TX_FULL) == 0U) {
+		neorv32_uart_write_data(dev, tx_data[count++]);
 	}
 
-	return 0;
+	return count;
 }
 
 static int neorv32_uart_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
 {
-	struct neorv32_uart_data *data = dev->data;
 	int count = 0;
 
 	if (size <= 0) {
@@ -245,104 +256,100 @@ static int neorv32_uart_fifo_read(const struct device *dev, uint8_t *rx_data, co
 
 	__ASSERT_NO_MSG(rx_data != NULL);
 
-	while ((data->last_data & NEORV32_UART_CTRL_RX_NEMPTY) != 0) {
-		rx_data[count++] = data->last_data & BIT_MASK(8);
-		data->last_data &= ~(NEORV32_UART_CTRL_RX_NEMPTY);
-
-		if (count >= size) {
-			break;
-		}
-
-		(void)neorv32_uart_read_data(dev);
+	while (count < size && (neorv32_uart_read_ctrl(dev) & NEORV32_UART_CTRL_RX_NEMPTY) != 0U) {
+		rx_data[count++] = neorv32_uart_read_data(dev) & NEORV32_UART_DATA_RTX;
 	}
 
 	return count;
 }
 
-static void neorv32_uart_tx_soft_isr(struct k_timer *timer)
-{
-	const struct device *dev = k_timer_user_data_get(timer);
-	struct neorv32_uart_data *data = dev->data;
-	uart_irq_callback_user_data_t callback = data->callback;
-
-	if (callback) {
-		callback(dev, data->callback_data);
-	}
-}
-
 static void neorv32_uart_irq_tx_enable(const struct device *dev)
 {
-	const struct neorv32_uart_config *config = dev->config;
 	struct neorv32_uart_data *data = dev->data;
+	k_spinlock_key_t key;
 	uint32_t ctrl;
 
-	irq_enable(config->tx_irq);
+	key = k_spin_lock(&data->lock);
 
 	ctrl = neorv32_uart_read_ctrl(dev);
-	if ((ctrl & NEORV32_UART_CTRL_TX_BUSY) == 0) {
-		/*
-		 * TX done event already generated an edge interrupt. Generate a
-		 * soft interrupt and have it call the callback function in
-		 * timer isr context.
-		 */
-		k_timer_start(&data->timer, K_NO_WAIT, K_NO_WAIT);
-	}
+	ctrl |= NEORV32_UART_CTRL_IRQ_TX_EMPTY;
+	neorv32_uart_write_ctrl(dev, ctrl);
+
+	k_spin_unlock(&data->lock, key);
 }
 
 static void neorv32_uart_irq_tx_disable(const struct device *dev)
 {
-	const struct neorv32_uart_config *config = dev->config;
+	struct neorv32_uart_data *data = dev->data;
+	k_spinlock_key_t key;
+	uint32_t ctrl;
 
-	irq_disable(config->tx_irq);
+	key = k_spin_lock(&data->lock);
+
+	ctrl = neorv32_uart_read_ctrl(dev);
+	ctrl &= ~NEORV32_UART_CTRL_IRQ_TX_EMPTY;
+	neorv32_uart_write_ctrl(dev, ctrl);
+
+	k_spin_unlock(&data->lock, key);
 }
 
 static int neorv32_uart_irq_tx_ready(const struct device *dev)
 {
-	const struct neorv32_uart_config *config = dev->config;
-	uint32_t ctrl;
+	struct neorv32_uart_data *data = dev->data;
 
-	if (!irq_is_enabled(config->tx_irq)) {
+	if ((data->last_ctrl & NEORV32_UART_CTRL_IRQ_TX_EMPTY) == 0U) {
 		return 0;
 	}
 
-	ctrl = neorv32_uart_read_ctrl(dev);
-
-	return (ctrl & NEORV32_UART_CTRL_TX_BUSY) == 0;
+	return (data->last_ctrl & NEORV32_UART_CTRL_TX_FULL) == 0U;
 }
 
 static void neorv32_uart_irq_rx_enable(const struct device *dev)
 {
-	const struct neorv32_uart_config *config = dev->config;
+	struct neorv32_uart_data *data = dev->data;
+	k_spinlock_key_t key;
+	uint32_t ctrl;
+
+	key = k_spin_lock(&data->lock);
+
+	ctrl = neorv32_uart_read_ctrl(dev);
+	ctrl |= NEORV32_UART_CTRL_IRQ_RX_NEMPTY;
+	neorv32_uart_write_ctrl(dev, ctrl);
 
-	irq_enable(config->rx_irq);
+	k_spin_unlock(&data->lock, key);
 }
 
 static void neorv32_uart_irq_rx_disable(const struct device *dev)
 {
-	const struct neorv32_uart_config *config = dev->config;
+	struct neorv32_uart_data *data = dev->data;
+	k_spinlock_key_t key;
+	uint32_t ctrl;
 
-	irq_disable(config->rx_irq);
+	key = k_spin_lock(&data->lock);
+
+	ctrl = neorv32_uart_read_ctrl(dev);
+	ctrl &= ~NEORV32_UART_CTRL_IRQ_RX_NEMPTY;
+	neorv32_uart_write_ctrl(dev, ctrl);
+
+	k_spin_unlock(&data->lock, key);
 }
 
 static int neorv32_uart_irq_tx_complete(const struct device *dev)
 {
-	uint32_t ctrl;
-
-	ctrl = neorv32_uart_read_ctrl(dev);
+	struct neorv32_uart_data *data = dev->data;
 
-	return (ctrl & NEORV32_UART_CTRL_TX_BUSY) == 0;
+	return (data->last_ctrl & NEORV32_UART_CTRL_TX_BUSY) == 0U;
 }
 
 static int neorv32_uart_irq_rx_ready(const struct device *dev)
 {
-	const struct neorv32_uart_config *config = dev->config;
 	struct neorv32_uart_data *data = dev->data;
 
-	if (!irq_is_enabled(config->rx_irq)) {
+	if ((data->last_ctrl & NEORV32_UART_CTRL_IRQ_RX_NEMPTY) == 0U) {
 		return 0;
 	}
 
-	return (data->last_data & NEORV32_UART_CTRL_RX_NEMPTY) != 0;
+	return (data->last_ctrl & NEORV32_UART_CTRL_RX_NEMPTY) != 0U;
 }
 
 static int neorv32_uart_irq_is_pending(const struct device *dev)
@@ -353,12 +360,14 @@ static int neorv32_uart_irq_is_pending(const struct device *dev)
 
 static int neorv32_uart_irq_update(const struct device *dev)
 {
-	const struct neorv32_uart_config *config = dev->config;
+	struct neorv32_uart_data *data = dev->data;
 
-	if (irq_is_enabled(config->rx_irq)) {
-		/* Cache data for use by rx_ready() and fifo_read() */
-		(void)neorv32_uart_read_data(dev);
-	}
+	/* Cache the CTRL register for use in the following functions:
+	 * - neorv32_uart_irq_tx_complete()
+	 * - neorv32_uart_irq_tx_ready()
+	 * - neorv32_uart_irq_rx_ready()
+	 */
+	data->last_ctrl = neorv32_uart_read_ctrl(dev);
 
 	return 1;
 }
@@ -395,7 +404,7 @@ static int neorv32_uart_init(const struct device *dev)
 		return -EINVAL;
 	}
 
-	err = syscon_read_reg(config->syscon, NEORV32_SYSINFO_FEATURES, &features);
+	err = syscon_read_reg(config->syscon, NEORV32_SYSINFO_SOC, &features);
 	if (err < 0) {
 		LOG_ERR("failed to determine implemented features (err %d)", err);
 		return -EIO;
@@ -407,9 +416,6 @@ static int neorv32_uart_init(const struct device *dev)
 	}
 
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
-	k_timer_init(&data->timer, &neorv32_uart_tx_soft_isr, NULL);
-	k_timer_user_data_set(&data->timer, (void *)dev);
-
 	config->irq_config_func(dev);
 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
 
@@ -420,7 +426,12 @@ static int neorv32_uart_init(const struct device *dev)
 static int neorv32_uart_pm_action(const struct device *dev,
 				  enum pm_device_action action)
 {
-	uint32_t ctrl = neorv32_uart_read_ctrl(dev);
+	struct neorv32_uart_data *data = dev->data;
+	k_spinlock_key_t key;
+	uint32_t ctrl;
+
+	key = k_spin_lock(&data->lock);
+	ctrl = neorv32_uart_read_ctrl(dev);
 
 	switch (action) {
 	case PM_DEVICE_ACTION_SUSPEND:
@@ -434,6 +445,7 @@ static int neorv32_uart_pm_action(const struct device *dev,
 	}
 
 	neorv32_uart_write_ctrl(dev, ctrl);
+	k_spin_unlock(&data->lock, key);
 
 	return 0;
 }
@@ -470,16 +482,16 @@ static DEVICE_API(uart, neorv32_uart_driver_api) = {
 			    DT_IRQ_BY_NAME(node_id, tx, priority),	\
 			    neorv32_uart_isr,				\
 			    DEVICE_DT_GET(node_id), 0);			\
+		irq_enable(DT_IRQ_BY_NAME(node_id, tx, irq));		\
 									\
 		IRQ_CONNECT(DT_IRQ_BY_NAME(node_id, rx, irq),		\
 			    DT_IRQ_BY_NAME(node_id, rx, priority),	\
 			    neorv32_uart_isr,				\
 			    DEVICE_DT_GET(node_id), 0);			\
+		irq_enable(DT_IRQ_BY_NAME(node_id, rx, irq));		\
 	}
 #define NEORV32_UART_CONFIG_INIT(node_id, n)				\
-	.irq_config_func = neorv32_uart_config_func_##n,		\
-	.tx_irq = DT_IRQ_BY_NAME(node_id, tx, irq),			\
-	.rx_irq = DT_IRQ_BY_NAME(node_id, rx, irq),
+	.irq_config_func = neorv32_uart_config_func_##n,
 #else
 #define NEORV32_UART_CONFIG_FUNC(node_id, n)
 #define NEORV32_UART_CONFIG_INIT(node_id, n)
@@ -491,8 +503,7 @@ static DEVICE_API(uart, neorv32_uart_driver_api) = {
 	static struct neorv32_uart_data neorv32_uart_##n##_data = {	\
 		.uart_cfg = {						\
 			.baudrate = DT_PROP(node_id, current_speed),	\
-			.parity = DT_ENUM_IDX_OR(node_id, parity,	\
-						 UART_CFG_PARITY_NONE),	\
+			.parity = DT_ENUM_IDX(node_id, parity),		\
 			.stop_bits = UART_CFG_STOP_BITS_1,		\
 			.data_bits = UART_CFG_DATA_BITS_8,		\
 			.flow_ctrl = DT_PROP(node_id, hw_flow_control) ? \
@@ -503,7 +514,7 @@ static DEVICE_API(uart, neorv32_uart_driver_api) = {
 									\
 	static const struct neorv32_uart_config neorv32_uart_##n##_config = { \
 		.syscon = DEVICE_DT_GET(DT_PHANDLE(node_id, syscon)),	\
-		.feature_mask = NEORV32_SYSINFO_FEATURES_IO_UART##n,	\
+		.feature_mask = NEORV32_SYSINFO_SOC_IO_UART##n,	\
 		.base = DT_REG_ADDR(node_id),				\
 		NEORV32_UART_CONFIG_INIT(node_id, n)			\
 	};								\
diff --git a/drivers/serial/uart_npcx.c b/drivers/serial/uart_npcx.c
index fc68fce79b0..14e32c62ae1 100644
--- a/drivers/serial/uart_npcx.c
+++ b/drivers/serial/uart_npcx.c
@@ -1066,6 +1066,9 @@ static int uart_npcx_init(const struct device *dev)
 	/* Disable all UART tx FIFO interrupts */
 	uart_npcx_dis_all_tx_interrupts(dev);
 
+	/* Disable rx FIFO not empty interrupt */
+	uart_npcx_irq_rx_disable(dev);
+
 	/* Clear UART rx FIFO */
 	uart_npcx_clear_rx_fifo(dev);
 
diff --git a/drivers/serial/uart_nrfx_uarte.c b/drivers/serial/uart_nrfx_uarte.c
index 6728ec8fbbf..d2136acf883 100644
--- a/drivers/serial/uart_nrfx_uarte.c
+++ b/drivers/serial/uart_nrfx_uarte.c
@@ -2512,6 +2512,18 @@ static int uarte_instance_init(const struct device *dev,
 			     : UART_CFG_FLOW_CTRL_NONE,			       \
 	}
 
+/* Macro determines if PM actions are interrupt safe. They are in case of
+ * asynchronous API (except for instance in fast power domain) and non-asynchronous
+ * API if RX is disabled. Macro must resolve to a literal 1 or 0.
+ */
+#define UARTE_PM_ISR_SAFE(idx)						       \
+	COND_CODE_1(INSTANCE_IS_FAST_PD(_, /*empty*/, idx, _),		       \
+		    (0),						       \
+		    (COND_CODE_1(CONFIG_UART_##idx##_ASYNC,		       \
+				 (PM_DEVICE_ISR_SAFE),			       \
+				 (COND_CODE_1(UARTE_PROP(idx, disable_rx),     \
+					      (PM_DEVICE_ISR_SAFE), (0))))))   \
+
 #define UART_NRF_UARTE_DEVICE(idx)					       \
 	NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP(UARTE(idx));		       \
 	UARTE_INT_DRIVEN(idx);						       \
@@ -2584,8 +2596,7 @@ static int uarte_instance_init(const struct device *dev,
 	}								       \
 									       \
 	PM_DEVICE_DT_DEFINE(UARTE(idx), uarte_nrfx_pm_action,		       \
-			    COND_CODE_1(INSTANCE_IS_FAST_PD(_, /*empty*/, idx, _),\
-				    (0), (PM_DEVICE_ISR_SAFE)));	       \
+			    UARTE_PM_ISR_SAFE(idx));			       \
 									       \
 	DEVICE_DT_DEFINE(UARTE(idx),					       \
 		      uarte_##idx##_init,				       \
diff --git a/drivers/serial/uart_ns16550.c b/drivers/serial/uart_ns16550.c
index ea80df30701..e56ef61a9e2 100644
--- a/drivers/serial/uart_ns16550.c
+++ b/drivers/serial/uart_ns16550.c
@@ -573,9 +573,7 @@ static int uart_ns16550_configure(const struct device *dev,
 	const struct uart_ns16550_dev_config * const dev_cfg = dev->config;
 	uint8_t mdc = 0U, c;
 	uint32_t pclk = 0U;
-
-	/* temp for return value if error occurs in this locked region */
-	int ret = 0;
+	int ret;
 
 	k_spinlock_key_t key = k_spin_lock(&dev_data->lock);
 
@@ -622,6 +620,11 @@ static int uart_ns16550_configure(const struct device *dev,
 			goto out;
 		}
 
+		ret = clock_control_on(dev_cfg->clock_dev, dev_cfg->clock_subsys);
+		if (ret != 0 && ret != -EALREADY && ret != -ENOSYS) {
+			goto out;
+		}
+
 		if (clock_control_get_rate(dev_cfg->clock_dev,
 					   dev_cfg->clock_subsys,
 					   &pclk) != 0) {
@@ -722,6 +725,7 @@ static int uart_ns16550_configure(const struct device *dev,
 
 	/* disable interrupts  */
 	ns16550_outbyte(dev_cfg, IER(dev), 0x00);
+	ret = 0;
 
 out:
 	k_spin_unlock(&dev_data->lock, key);
diff --git a/drivers/serial/uart_nxp_s32_linflexd.c b/drivers/serial/uart_nxp_s32_linflexd.c
index e0f958d6bab..dee4a034628 100644
--- a/drivers/serial/uart_nxp_s32_linflexd.c
+++ b/drivers/serial/uart_nxp_s32_linflexd.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022-2024 NXP
+ * Copyright 2022-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,6 +10,7 @@
 #include <zephyr/irq.h>
 #include <zephyr/drivers/uart.h>
 #include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/clock_control.h>
 
 #include <Linflexd_Uart_Ip.h>
 #include <Linflexd_Uart_Ip_Irq.h>
@@ -295,14 +296,36 @@ static int uart_nxp_s32_init(const struct device *dev)
 {
 	const struct uart_nxp_s32_config *config = dev->config;
 	int err;
+	uint32_t clock_rate;
+	Linflexd_Uart_Ip_StatusType status;
 
 	err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
 	if (err < 0) {
 		return err;
 	}
 
+	if (!device_is_ready(config->clock_dev)) {
+		return -ENODEV;
+	}
+
+	err = clock_control_on(config->clock_dev, config->clock_subsys);
+	if (err) {
+		return err;
+	}
+
+	err = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_rate);
+	if (err) {
+		return err;
+	}
+
 	Linflexd_Uart_Ip_Init(config->instance, &config->hw_cfg);
 
+	status = Linflexd_Uart_Ip_SetBaudrate(config->instance, config->hw_cfg.BaudRate,
+					      clock_rate);
+	if (status != LINFLEXD_UART_IP_STATUS_SUCCESS) {
+		return -EIO;
+	}
+
 	return 0;
 }
 
@@ -345,14 +368,30 @@ static DEVICE_API(uart, uart_nxp_s32_driver_api) = {
 
 #define UART_NXP_S32_HW_CONFIG(n)						\
 	{									\
-		.BaudRate = 115200,						\
+		.BaudRate = DT_INST_PROP(n, current_speed),			\
 		.BaudRateMantissa = 26U,					\
 		.BaudRateDivisor = 16U,						\
 		.BaudRateFractionalDivisor = 1U,				\
-		.ParityCheck = false,						\
-		.ParityType = LINFLEXD_UART_IP_PARITY_EVEN,			\
-		.StopBitsCount = LINFLEXD_UART_IP_ONE_STOP_BIT,			\
-		.WordLength = LINFLEXD_UART_IP_8_BITS,				\
+		.ParityCheck = DT_INST_ENUM_IDX(n, parity) ==			\
+				UART_CFG_PARITY_NONE ? false : true,		\
+		.ParityType = DT_INST_ENUM_IDX(n, parity) ==			\
+					UART_CFG_PARITY_ODD ?			\
+				LINFLEXD_UART_IP_PARITY_ODD :			\
+				(DT_INST_ENUM_IDX(n, parity) ==			\
+						UART_CFG_PARITY_EVEN ?		\
+					LINFLEXD_UART_IP_PARITY_ONE :		\
+					(DT_INST_ENUM_IDX(n, parity) ==		\
+							UART_CFG_PARITY_MARK ?	\
+						LINFLEXD_UART_IP_PARITY_EVEN :	\
+						LINFLEXD_UART_IP_PARITY_ZERO)),	\
+		.StopBitsCount = DT_INST_ENUM_IDX(n, stop_bits) ==		\
+						UART_CFG_STOP_BITS_1 ?		\
+					LINFLEXD_UART_IP_ONE_STOP_BIT :		\
+					LINFLEXD_UART_IP_TWO_STOP_BIT,		\
+		.WordLength = DT_INST_ENUM_IDX(n, data_bits) ==			\
+						UART_CFG_DATA_BITS_7 ?		\
+					LINFLEXD_UART_IP_7_BITS	:		\
+					LINFLEXD_UART_IP_8_BITS,		\
 		.TransferType = LINFLEXD_UART_IP_USING_INTERRUPTS,		\
 		.StateStruct = &Linflexd_Uart_Ip_apStateStructure[n],		\
 		IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, (			\
@@ -362,6 +401,17 @@ static DEVICE_API(uart, uart_nxp_s32_driver_api) = {
 	}
 
 #define UART_NXP_S32_INIT_DEVICE(n)						\
+	BUILD_ASSERT(DT_INST_ENUM_IDX(n, stop_bits) == UART_CFG_STOP_BITS_1 ||	\
+		DT_INST_ENUM_IDX(n, stop_bits) == UART_CFG_STOP_BITS_2,		\
+		"Node " DT_NODE_PATH(DT_DRV_INST(n))				\
+		" has unsupported stop bits configuration");			\
+	BUILD_ASSERT(DT_INST_ENUM_IDX(n, data_bits) == UART_CFG_DATA_BITS_7 ||	\
+		DT_INST_ENUM_IDX(n, data_bits) == UART_CFG_DATA_BITS_8,		\
+		"Node " DT_NODE_PATH(DT_DRV_INST(n))				\
+		" has unsupported data bits configuration");			\
+	BUILD_ASSERT(DT_INST_PROP(n, hw_flow_control) == UART_CFG_FLOW_CTRL_NONE,\
+		"Node " DT_NODE_PATH(DT_DRV_INST(n))				\
+		" has unsupported flow control configuration");			\
 	PINCTRL_DT_INST_DEFINE(n);						\
 	IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN,				\
 		(static struct uart_nxp_s32_data uart_nxp_s32_data_##n;))	\
@@ -370,6 +420,9 @@ static DEVICE_API(uart, uart_nxp_s32_driver_api) = {
 		.base = (LINFLEXD_Type *)DT_INST_REG_ADDR(n),			\
 		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
 		.hw_cfg = UART_NXP_S32_HW_CONFIG(n),				\
+		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),		\
+		.clock_subsys = (clock_control_subsys_t)			\
+				DT_INST_CLOCKS_CELL(n, name),			\
 	};									\
 	static int uart_nxp_s32_init_##n(const struct device *dev)		\
 	{									\
diff --git a/drivers/serial/uart_nxp_s32_linflexd.h b/drivers/serial/uart_nxp_s32_linflexd.h
index 997cd1e9112..555e303cba9 100644
--- a/drivers/serial/uart_nxp_s32_linflexd.h
+++ b/drivers/serial/uart_nxp_s32_linflexd.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022-2023 NXP
+ * Copyright 2022-2023, 2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,8 @@ struct uart_nxp_s32_config {
 	LINFLEXD_Type *base;
 	const struct pinctrl_dev_config *pincfg;
 	Linflexd_Uart_Ip_UserConfigType hw_cfg;
+	const struct device *clock_dev;
+	clock_control_subsys_t clock_subsys;
 };
 
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
diff --git a/drivers/serial/uart_pl011.c b/drivers/serial/uart_pl011.c
index cbaa507e9a7..624ae45f5c5 100644
--- a/drivers/serial/uart_pl011.c
+++ b/drivers/serial/uart_pl011.c
@@ -38,7 +38,7 @@
 #include "uart_pl011_ambiq.h"
 #endif
 
-#if defined(CONFIG_SOC_SERIES_APOLLO3X)
+#if defined(CONFIG_SOC_SERIES_APOLLO3X) || defined(CONFIG_SOC_SERIES_APOLLO5X)
 #define PM_INST_GET(n) PM_DEVICE_DT_INST_GET(n)
 #else
 #define PM_INST_GET(n) NULL
@@ -61,6 +61,7 @@ struct pl011_config {
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 	uart_irq_config_func_t irq_config_func;
 #endif
+	bool fifo_disable;
 	int (*clk_enable_func)(const struct device *dev, uint32_t clk);
 	int (*pwr_on_func)(void);
 };
@@ -74,6 +75,7 @@ struct pl011_data {
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 	volatile bool sw_call_txdrdy;
 	uart_irq_callback_user_data_t irq_cb;
+	struct k_spinlock irq_cb_lock;
 	void *irq_cb_data;
 #endif
 };
@@ -205,6 +207,7 @@ static int pl011_runtime_configure_internal(const struct device *dev,
 					const struct uart_config *cfg,
 					bool disable)
 {
+	const struct pl011_config *config = dev->config;
 	struct pl011_data *data = dev->data;
 	uint32_t lcrh;
 	int ret = -ENOTSUP;
@@ -286,7 +289,9 @@ static int pl011_runtime_configure_internal(const struct device *dev,
 
 enable:
 	if (disable) {
-		pl011_enable_fifo(dev);
+		if (!config->fifo_disable) {
+			pl011_enable_fifo(dev);
+		}
 		pl011_enable(dev);
 	}
 
@@ -342,29 +347,45 @@ static void pl011_irq_tx_enable(const struct device *dev)
 	struct pl011_data *data = dev->data;
 
 	get_uart(dev)->imsc |= PL011_IMSC_TXIM;
-	if (data->sw_call_txdrdy) {
-		/* Verify if the callback has been registered */
-		if (data->irq_cb) {
-			/*
-			 * Due to HW limitation, the first TX interrupt should
-			 * be triggered by the software.
-			 *
-			 * PL011 TX interrupt is based on a transition through
-			 * a level, rather than on the level itself[1]. So that,
-			 * enable TX interrupt can not trigger TX interrupt if
-			 * no data was filled to TX FIFO at the beginning.
-			 *
-			 * [1]: PrimeCell UART (PL011) Technical Reference Manual
-			 *      functional-overview/interrupts
-			 */
+	if (!data->sw_call_txdrdy) {
+		return;
+	}
+	data->sw_call_txdrdy = false;
+
+	/*
+	 * Verify if the callback has been registered. Due to HW limitation, the
+	 * first TX interrupt should be triggered by the software.
+	 *
+	 * PL011 TX interrupt is based on a transition through a level, rather
+	 * than on the level itself[1]. So that, enable TX interrupt can not
+	 * trigger TX interrupt if no data was filled to TX FIFO at the
+	 * beginning.
+	 *
+	 * [1]: PrimeCell UART (PL011) Technical Reference Manual
+	 *      functional-overview/interrupts
+	 */
+	if (!data->irq_cb) {
+		return;
+	}
+
+	/*
+	 * Execute callback while TX interrupt remains enabled. If
+	 * uart_fifo_fill() is called with small amounts of data, the 1/8 TX
+	 * FIFO threshold may never be reached, and the hardware TX interrupt
+	 * will never trigger.
+	 */
+	while (get_uart(dev)->imsc & PL011_IMSC_TXIM) {
+		K_SPINLOCK(&data->irq_cb_lock) {
 			data->irq_cb(dev, data->irq_cb_data);
 		}
-		data->sw_call_txdrdy = false;
 	}
 }
 
 static void pl011_irq_tx_disable(const struct device *dev)
 {
+	struct pl011_data *data = dev->data;
+
+	data->sw_call_txdrdy = true;
 	get_uart(dev)->imsc &= ~PL011_IMSC_TXIM;
 }
 
@@ -527,7 +548,9 @@ static int pl011_init(const struct device *dev)
 			| FIELD_PREP(PL011_IFLS_RXIFLSEL_M, RXIFLSEL_1_2_FULL);
 
 		/* Enabling the FIFOs */
-		pl011_enable_fifo(dev);
+		if (!config->fifo_disable) {
+			pl011_enable_fifo(dev);
+		}
 	}
 	/* initialize all IRQs as masked */
 	get_uart(dev)->imsc = 0U;
@@ -620,7 +643,9 @@ void pl011_isr(const struct device *dev)
 
 	/* Verify if the callback has been registered */
 	if (data->irq_cb) {
-		data->irq_cb(dev, data->irq_cb_data);
+		K_SPINLOCK(&data->irq_cb_lock) {
+			data->irq_cb(dev, data->irq_cb_data);
+		}
 	}
 }
 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
@@ -648,6 +673,7 @@ void pl011_isr(const struct device *dev)
 		CLOCK_INIT(n)                                                           \
 		PINCTRL_INIT(n)	                                                        \
 		.irq_config_func = pl011_irq_config_func_##n,				\
+		.fifo_disable = DT_INST_PROP(n, fifo_disable),                          \
 		.clk_enable_func = COMPAT_SPECIFIC_CLK_ENABLE_FUNC(n),		        \
 		.pwr_on_func = COMPAT_SPECIFIC_PWR_ON_FUNC(n),			        \
 	};
diff --git a/drivers/serial/uart_pl011_ambiq.h b/drivers/serial/uart_pl011_ambiq.h
index 5efb0e5e62c..3799b09ad12 100644
--- a/drivers/serial/uart_pl011_ambiq.h
+++ b/drivers/serial/uart_pl011_ambiq.h
@@ -13,9 +13,7 @@
 #include <zephyr/pm/policy.h>
 
 #include "uart_pl011_registers.h"
-#include <am_mcu_apollo.h>
-
-#define PWRCTRL_MAX_WAIT_US 5
+#include <soc.h>
 
 static inline void pl011_ambiq_enable_clk(const struct device *dev)
 {
@@ -39,6 +37,16 @@ static inline int pl011_ambiq_clk_set(const struct device *dev, uint32_t clk)
 	case 24000000:
 		clksel = PL011_CR_AMBIQ_CLKSEL_24MHZ;
 		break;
+#if !defined(CONFIG_SOC_SERIES_APOLLO3X)
+	case 48000000:
+		clksel = PL011_CR_AMBIQ_CLKSEL_48MHZ;
+		break;
+#if !defined(CONFIG_SOC_SERIES_APOLLO4X)
+	case AM_HAL_UART_PLLCLK_FREQ:
+		clksel = PL011_CR_AMBIQ_CLKSEL_PLL;
+		break;
+#endif
+#endif
 	default:
 		return -EINVAL;
 	}
@@ -160,48 +168,18 @@ static int uart_ambiq_pm_action(const struct device *dev, enum pm_device_action
 }
 #endif /* CONFIG_PM_DEVICE */
 
-/* Problem: writes to power configure register takes some time to take effective.
- * Solution: Check device's power status to ensure that register has taken effective.
- * Note: busy wait is not allowed to use here due to UART is initiated before timer starts.
- */
-#if defined(CONFIG_SOC_SERIES_APOLLO3X)
-#define DEVPWRSTATUS_OFFSET 0x10
-#define HCPA_MASK           0x4
-#define AMBIQ_UART_DEFINE(n)                                                                       \
-	PM_DEVICE_DT_INST_DEFINE(n, uart_ambiq_pm_action);                                         \
-	static int pwr_on_ambiq_uart_##n(void)                                                     \
-	{                                                                                          \
-		uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) +                    \
-				DT_INST_PHA(n, ambiq_pwrcfg, offset);                              \
-		uint32_t pwr_status_addr = addr + DEVPWRSTATUS_OFFSET;                             \
-		sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr);        \
-		while (!(sys_read32(pwr_status_addr) & HCPA_MASK)) {                               \
-		};                                                                                 \
-		return 0;                                                                          \
-	}                                                                                          \
-	static inline int clk_enable_ambiq_uart_##n(const struct device *dev, uint32_t clk)        \
-	{                                                                                          \
-		return clk_enable_ambiq_uart(dev, clk);                                            \
-	}
-#else
-#define DEVPWRSTATUS_OFFSET 0x4
 #define AMBIQ_UART_DEFINE(n)                                                                       \
 	PM_DEVICE_DT_INST_DEFINE(n, uart_ambiq_pm_action);                                         \
 	static int pwr_on_ambiq_uart_##n(void)                                                     \
 	{                                                                                          \
-		uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) +                    \
-				DT_INST_PHA(n, ambiq_pwrcfg, offset);                              \
-		uint32_t pwr_status_addr = addr + DEVPWRSTATUS_OFFSET;                             \
-		sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr);        \
-		while ((sys_read32(pwr_status_addr) & DT_INST_PHA(n, ambiq_pwrcfg, mask)) !=       \
-		       DT_INST_PHA(n, ambiq_pwrcfg, mask)) {                                       \
-		};                                                                                 \
-		return 0;                                                                          \
+		uint32_t module = (DT_INST_REG_ADDR(n) - UART0_BASE) / (UART1_BASE - UART0_BASE);  \
+		am_hal_pwrctrl_periph_e eUARTPowerModule =                                         \
+			((am_hal_pwrctrl_periph_e)(AM_HAL_PWRCTRL_PERIPH_UART0 + module));         \
+		return am_hal_pwrctrl_periph_enable(eUARTPowerModule);                             \
 	}                                                                                          \
 	static inline int clk_enable_ambiq_uart_##n(const struct device *dev, uint32_t clk)        \
 	{                                                                                          \
 		return clk_enable_ambiq_uart(dev, clk);                                            \
 	}
-#endif
 
 #endif /* ZEPHYR_DRIVERS_SERIAL_UART_PL011_AMBIQ_H_ */
diff --git a/drivers/serial/uart_pl011_registers.h b/drivers/serial/uart_pl011_registers.h
index 6f559d0041b..a46509e18b6 100644
--- a/drivers/serial/uart_pl011_registers.h
+++ b/drivers/serial/uart_pl011_registers.h
@@ -114,6 +114,7 @@ volatile struct pl011_regs *get_uart(const struct device *dev)
 #define PL011_CR_AMBIQ_CLKSEL_6MHZ	3
 #define PL011_CR_AMBIQ_CLKSEL_3MHZ	4
 #define PL011_CR_AMBIQ_CLKSEL_48MHZ	5
+#define PL011_CR_AMBIQ_CLKSEL_PLL	6
 
 /* PL011 Interrupt Fifo Level Select Register */
 #define PL011_IFLS_RXIFLSEL_M	GENMASK(5, 3)
diff --git a/drivers/serial/uart_renesas_ra.c b/drivers/serial/uart_renesas_ra.c
deleted file mode 100644
index 60758db553b..00000000000
--- a/drivers/serial/uart_renesas_ra.c
+++ /dev/null
@@ -1,733 +0,0 @@
-/*
- * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DT_DRV_COMPAT renesas_ra_uart_sci
-
-#include <zephyr/drivers/uart.h>
-#include <zephyr/drivers/clock_control.h>
-#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
-#include <zephyr/drivers/interrupt_controller/intc_ra_icu.h>
-#include <zephyr/drivers/pinctrl.h>
-#include <zephyr/irq.h>
-#include <zephyr/spinlock.h>
-
-#include <zephyr/logging/log.h>
-
-LOG_MODULE_REGISTER(ra_uart_sci, CONFIG_UART_LOG_LEVEL);
-
-enum {
-	UART_RA_INT_RXI,
-	UART_RA_INT_TXI,
-	UART_RA_INT_ERI,
-	NUM_OF_UART_RA_INT,
-};
-
-struct uart_ra_cfg {
-	mem_addr_t regs;
-	const struct device *clock_dev;
-	const struct clock_control_ra_subsys_cfg clock_id;
-	const struct pinctrl_dev_config *pcfg;
-#ifdef CONFIG_UART_INTERRUPT_DRIVEN
-	int (*irq_config_func)(const struct device *dev);
-#endif
-};
-
-struct uart_ra_data {
-	struct uart_config current_config;
-	uint32_t clk_rate;
-	struct k_spinlock lock;
-#ifdef CONFIG_UART_INTERRUPT_DRIVEN
-	uint32_t irqn[NUM_OF_UART_RA_INT];
-	uart_irq_callback_user_data_t callback;
-	void *cb_data;
-#endif
-};
-
-#define REG_MASK(reg) (BIT_MASK(_CONCAT(reg, _LEN)) << _CONCAT(reg, _POS))
-
-/* Registers */
-#define SMR  0x00 /*!< Serial Mode Register             */
-#define BRR  0x01 /*!< Bit Rate Register                */
-#define SCR  0x02 /*!< Serial Control Register          */
-#define TDR  0x03 /*!< Transmit Data Register           */
-#define SSR  0x04 /*!< Serial Status Register           */
-#define RDR  0x05 /*!< Receive Data Register            */
-#define SEMR 0x07 /*!< Serial Extended Mode Register    */
-#define MDDR 0x12 /*!< Modulation Duty Register         */
-#define LSR  0x18 /*!< Line Status Register             */
-
-/*
- * SMR (Serial Mode Register)
- *
- * - CKS[0..2]:  Clock Select
- * - MP[2..3]:   Multi-Processor Mode(Valid only in asynchronous mode)
- * - STOP[3..4]: Stop Bit Length(Valid only in asynchronous mode)
- * - PM[4..5]:   Parity Mode (Valid only when the PE bit is 1)
- * - PE[5..6]:   Parity Enable(Valid only in asynchronous mode)
- * - CHR[6..7]:  Character Length(Valid only in asynchronous mode)
- * - CM[7..8]:   Communication Mode
- */
-#define SMR_CKS_POS  (0)
-#define SMR_CKS_LEN  (2)
-#define SMR_MP_POS   (2)
-#define SMR_MP_LEN   (1)
-#define SMR_STOP_POS (3)
-#define SMR_STOP_LEN (1)
-#define SMR_PM_POS   (4)
-#define SMR_PM_LEN   (1)
-#define SMR_PE_POS   (5)
-#define SMR_PE_LEN   (1)
-#define SMR_CHR_POS  (6)
-#define SMR_CHR_LEN  (1)
-#define SMR_CM_POS   (7)
-#define SMR_CM_LEN   (1)
-
-/**
- * SCR (Serial Control Register)
- *
- * - CKE[0..2]:  Clock Enable
- * - TEIE[2..3]: Transmit End Interrupt Enable
- * - MPIE[3..4]: Multi-Processor Interrupt Enable (Valid in asynchronous
- * - RE[4..5]:   Receive Enable
- * - TE[5..6]:   Transmit Enable
- * - RIE[6..7]:  Receive Interrupt Enable
- * - TIE[7..8]:  Transmit Interrupt Enable
- */
-#define SCR_CKE_POS  (0)
-#define SCR_CKE_LEN  (2)
-#define SCR_TEIE_POS (2)
-#define SCR_TEIE_LEN (1)
-#define SCR_MPIE_POS (3)
-#define SCR_MPIE_LEN (1)
-#define SCR_RE_POS   (4)
-#define SCR_RE_LEN   (1)
-#define SCR_TE_POS   (5)
-#define SCR_TE_LEN   (1)
-#define SCR_RIE_POS  (6)
-#define SCR_RIE_LEN  (1)
-#define SCR_TIE_POS  (7)
-#define SCR_TIE_LEN  (1)
-
-/**
- * SSR (Serial Status Register)
- *
- * - MPBT[0..1]: Multi-Processor Bit Transfer
- * - MPB[1..2]:  Multi-Processor
- * - TEND[2..3]: Transmit End Flag
- * - PER[3..4]:  Parity Error Flag
- * - FER[4..5]:  Framing Error Flag
- * - ORER[5..6]: Overrun Error Flag
- * - RDRF[6..7]: Receive Data Full Flag
- * - TDRE[7..8]: Transmit Data Empty Flag
- */
-#define SSR_MPBT_POS (0)
-#define SSR_MPBT_LEN (1)
-#define SSR_MPB_POS  (1)
-#define SSR_MPB_LEN  (1)
-#define SSR_TEND_POS (2)
-#define SSR_TEND_LEN (1)
-#define SSR_PER_POS  (3)
-#define SSR_PER_LEN  (1)
-#define SSR_FER_POS  (4)
-#define SSR_FER_LEN  (1)
-#define SSR_ORER_POS (5)
-#define SSR_ORER_LEN (1)
-#define SSR_RDRF_POS (6)
-#define SSR_RDRF_LEN (1)
-#define SSR_TDRE_POS (7)
-#define SSR_TDRE_LEN (1)
-
-/**
- * SEMR (Serial Extended Mode Register)
- *
- * - ACS0[0..1]:    Asynchronous Mode Clock Source Select
- * - PADIS[1..2]:   Preamble function Disable
- * - BRME[2..3]:    Bit Rate Modulation Enable
- * - ABCSE[3..4]:   Asynchronous Mode Extended Base Clock Select
- * - ABCS[4..5]:    Asynchronous Mode Base Clock Select
- * - NFEN[5..6]:    Digital Noise Filter Function Enable
- * - BGDM[6..7]:    Baud Rate Generator Double-Speed Mode Select
- * - RXDESEL[7..8]: Asynchronous Start Bit Edge Detection Select
- */
-#define SEMR_ACS0_POS    (0)
-#define SEMR_ACS0_LEN    (1)
-#define SEMR_PADIS_POS   (1)
-#define SEMR_PADIS_LEN   (1)
-#define SEMR_BRME_POS    (2)
-#define SEMR_BRME_LEN    (1)
-#define SEMR_ABCSE_POS   (3)
-#define SEMR_ABCSE_LEN   (1)
-#define SEMR_ABCS_POS    (4)
-#define SEMR_ABCS_LEN    (1)
-#define SEMR_NFEN_POS    (5)
-#define SEMR_NFEN_LEN    (1)
-#define SEMR_BGDM_POS    (6)
-#define SEMR_BGDM_LEN    (1)
-#define SEMR_RXDESEL_POS (7)
-#define SEMR_RXDESEL_LEN (1)
-
-/**
- * LSR (Line Status Register)
- *
- * - ORER[0..1]:  Overrun Error Flag
- * - FNUM[2..7]:  Framing Error Count
- * - PNUM[8..13]: Parity Error Count
- */
-#define LSR_ORER_POS (0)
-#define LSR_ORER_LEN (1)
-#define LSR_FNUM_POS (2)
-#define LSR_FNUM_LEN (5)
-#define LSR_PNUM_POS (8)
-#define LSR_PNUM_LEN (5)
-
-static uint8_t uart_ra_read_8(const struct device *dev, uint32_t offs)
-{
-	const struct uart_ra_cfg *config = dev->config;
-
-	return sys_read8(config->regs + offs);
-}
-
-static void uart_ra_write_8(const struct device *dev, uint32_t offs, uint8_t value)
-{
-	const struct uart_ra_cfg *config = dev->config;
-
-	sys_write8(value, config->regs + offs);
-}
-
-static uint16_t uart_ra_read_16(const struct device *dev, uint32_t offs)
-{
-	const struct uart_ra_cfg *config = dev->config;
-
-	return sys_read16(config->regs + offs);
-}
-
-static void uart_ra_write_16(const struct device *dev, uint32_t offs, uint16_t value)
-{
-	const struct uart_ra_cfg *config = dev->config;
-
-	sys_write16(value, config->regs + offs);
-}
-
-static void uart_ra_set_baudrate(const struct device *dev, uint32_t baud_rate)
-{
-	struct uart_ra_data *data = dev->data;
-	uint8_t reg_val;
-
-	reg_val = uart_ra_read_8(dev, SEMR);
-	reg_val |= (REG_MASK(SEMR_BGDM) | REG_MASK(SEMR_ABCS));
-	reg_val &= ~(REG_MASK(SEMR_BRME) | REG_MASK(SEMR_ABCSE));
-	uart_ra_write_8(dev, SEMR, reg_val);
-
-	reg_val = (data->clk_rate / (8 * data->current_config.baudrate)) - 1;
-	uart_ra_write_8(dev, BRR, reg_val);
-}
-
-static int uart_ra_poll_in(const struct device *dev, unsigned char *p_char)
-{
-	struct uart_ra_data *data = dev->data;
-	int ret = 0;
-
-	k_spinlock_key_t key = k_spin_lock(&data->lock);
-
-	/* If interrupts are enabled, return -EINVAL */
-	if ((uart_ra_read_8(dev, SCR) & REG_MASK(SCR_RIE))) {
-		ret = -EINVAL;
-		goto unlock;
-	}
-
-	if ((uart_ra_read_8(dev, SSR) & REG_MASK(SSR_RDRF)) == 0) {
-		ret = -1;
-		goto unlock;
-	}
-
-	*p_char = uart_ra_read_8(dev, RDR);
-unlock:
-	k_spin_unlock(&data->lock, key);
-
-	return ret;
-}
-
-static void uart_ra_poll_out(const struct device *dev, unsigned char out_char)
-{
-	struct uart_ra_data *data = dev->data;
-	uint8_t reg_val;
-	k_spinlock_key_t key = k_spin_lock(&data->lock);
-
-	while (!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TEND)) ||
-	       !(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TDRE))) {
-		;
-	}
-
-	/* If interrupts are enabled, temporarily disable them */
-	reg_val = uart_ra_read_8(dev, SCR);
-	uart_ra_write_8(dev, SCR, reg_val & ~REG_MASK(SCR_TIE));
-
-	uart_ra_write_8(dev, TDR, out_char);
-	while (!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TEND)) ||
-	       !(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_TDRE))) {
-		;
-	}
-
-	uart_ra_write_8(dev, SCR, reg_val);
-	k_spin_unlock(&data->lock, key);
-}
-
-static int uart_ra_err_check(const struct device *dev)
-{
-	struct uart_ra_data *data = dev->data;
-
-	uint8_t reg_val;
-	int errors = 0;
-	k_spinlock_key_t key;
-
-	key = k_spin_lock(&data->lock);
-	reg_val = uart_ra_read_8(dev, SSR);
-
-	if (reg_val & REG_MASK(SSR_PER)) {
-		errors |= UART_ERROR_PARITY;
-	}
-
-	if (reg_val & REG_MASK(SSR_FER)) {
-		errors |= UART_ERROR_FRAMING;
-	}
-
-	if (reg_val & REG_MASK(SSR_ORER)) {
-		errors |= UART_ERROR_OVERRUN;
-	}
-
-	reg_val &= ~(REG_MASK(SSR_PER) | REG_MASK(SSR_FER) | REG_MASK(SSR_ORER));
-	uart_ra_write_8(dev, SSR, reg_val);
-
-	k_spin_unlock(&data->lock, key);
-
-	return errors;
-}
-
-static int uart_ra_configure(const struct device *dev, const struct uart_config *cfg)
-{
-	struct uart_ra_data *data = dev->data;
-
-	uint16_t reg_val;
-	k_spinlock_key_t key;
-
-	if (cfg->parity != UART_CFG_PARITY_NONE || cfg->stop_bits != UART_CFG_STOP_BITS_1 ||
-	    cfg->data_bits != UART_CFG_DATA_BITS_8 || cfg->flow_ctrl != UART_CFG_FLOW_CTRL_NONE) {
-		return -ENOTSUP;
-	}
-
-	key = k_spin_lock(&data->lock);
-
-	/* Disable Transmit and Receive */
-	reg_val = uart_ra_read_8(dev, SCR);
-	reg_val &= ~(REG_MASK(SCR_TE) | REG_MASK(SCR_RE));
-	uart_ra_write_8(dev, SCR, reg_val);
-
-	/* Resetting Errors Registers */
-	reg_val = uart_ra_read_8(dev, SSR);
-	reg_val &= ~(REG_MASK(SSR_PER) | REG_MASK(SSR_FER) | REG_MASK(SSR_ORER) |
-		     REG_MASK(SSR_RDRF) | REG_MASK(SSR_TDRE));
-	uart_ra_write_8(dev, SSR, reg_val);
-
-	reg_val = uart_ra_read_16(dev, LSR);
-	reg_val &= ~(REG_MASK(LSR_ORER));
-	uart_ra_write_16(dev, LSR, reg_val);
-
-	/* Select internal clock */
-	reg_val = uart_ra_read_8(dev, SCR);
-	reg_val &= ~(REG_MASK(SCR_CKE));
-	uart_ra_write_8(dev, SCR, reg_val);
-
-	/* Serial Configuration (8N1) & Clock divider selection */
-	reg_val = uart_ra_read_8(dev, SMR);
-	reg_val &= ~(REG_MASK(SMR_CM) | REG_MASK(SMR_CHR) | REG_MASK(SMR_PE) | REG_MASK(SMR_PM) |
-		     REG_MASK(SMR_STOP) | REG_MASK(SMR_CKS));
-	uart_ra_write_8(dev, SMR, reg_val);
-
-	/* Set baudrate */
-	uart_ra_set_baudrate(dev, cfg->baudrate);
-
-	/* Enable Transmit & Receive + disable Interrupts */
-	reg_val = uart_ra_read_8(dev, SCR);
-	reg_val |= (REG_MASK(SCR_TE) | REG_MASK(SCR_RE));
-	reg_val &=
-		~(REG_MASK(SCR_TIE) | REG_MASK(SCR_RIE) | REG_MASK(SCR_MPIE) | REG_MASK(SCR_TEIE));
-	uart_ra_write_8(dev, SCR, reg_val);
-
-	data->current_config = *cfg;
-
-	k_spin_unlock(&data->lock, key);
-
-	return 0;
-}
-
-#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
-static int uart_ra_config_get(const struct device *dev, struct uart_config *cfg)
-{
-	struct uart_ra_data *data = dev->data;
-
-	*cfg = data->current_config;
-
-	return 0;
-}
-#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
-
-static int uart_ra_init(const struct device *dev)
-{
-	const struct uart_ra_cfg *config = dev->config;
-	struct uart_ra_data *data = dev->data;
-	int ret;
-
-	/* Configure dt provided device signals when available */
-	ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
-	if (ret < 0) {
-		return ret;
-	}
-
-	if (!device_is_ready(config->clock_dev)) {
-		return -ENODEV;
-	}
-
-	ret = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_id);
-	if (ret < 0) {
-		return ret;
-	}
-
-	ret = clock_control_get_rate(config->clock_dev, (clock_control_subsys_t)&config->clock_id,
-				     &data->clk_rate);
-	if (ret < 0) {
-		return ret;
-	}
-
-	ret = uart_ra_configure(dev, &data->current_config);
-	if (ret != 0) {
-		return ret;
-	}
-
-#ifdef CONFIG_UART_INTERRUPT_DRIVEN
-	ret = config->irq_config_func(dev);
-	if (ret != 0) {
-		return ret;
-	}
-#endif
-
-	return 0;
-}
-
-#ifdef CONFIG_UART_INTERRUPT_DRIVEN
-
-static bool uart_ra_irq_is_enabled(const struct device *dev, uint32_t irq)
-{
-	return uart_ra_read_8(dev, SCR) & irq;
-}
-
-static int uart_ra_fifo_fill(const struct device *dev, const uint8_t *tx_data, int len)
-{
-	struct uart_ra_data *data = dev->data;
-	uint8_t reg_val;
-	k_spinlock_key_t key;
-
-	if (len <= 0 || tx_data == NULL) {
-		return 0;
-	}
-
-	key = k_spin_lock(&data->lock);
-	reg_val = uart_ra_read_8(dev, SCR);
-	reg_val &= ~(REG_MASK(SCR_TIE));
-	uart_ra_write_8(dev, SCR, reg_val);
-
-	uart_ra_write_8(dev, TDR, tx_data[0]);
-
-	reg_val |= REG_MASK(SCR_TIE);
-	uart_ra_write_8(dev, SCR, reg_val);
-
-	k_spin_unlock(&data->lock, key);
-
-	return 1;
-}
-
-static int uart_ra_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
-{
-	uint8_t data;
-
-	if (size <= 0) {
-		return 0;
-	}
-
-	if ((uart_ra_read_8(dev, SSR) & REG_MASK(SSR_RDRF)) == 0) {
-		return 0;
-	}
-
-	data = uart_ra_read_8(dev, RDR);
-
-	if (rx_data) {
-		rx_data[0] = data;
-	}
-
-	return 1;
-}
-
-static void uart_ra_irq_tx_enable(const struct device *dev)
-{
-	struct uart_ra_data *data = dev->data;
-	k_spinlock_key_t key;
-	uint16_t reg_val;
-
-	key = k_spin_lock(&data->lock);
-
-	reg_val = uart_ra_read_8(dev, SCR);
-	reg_val |= (REG_MASK(SCR_TIE));
-	uart_ra_write_8(dev, SCR, reg_val);
-
-	irq_enable(data->irqn[UART_RA_INT_TXI]);
-
-	k_spin_unlock(&data->lock, key);
-}
-
-static void uart_ra_irq_tx_disable(const struct device *dev)
-{
-	struct uart_ra_data *data = dev->data;
-	k_spinlock_key_t key;
-	uint16_t reg_val;
-
-	key = k_spin_lock(&data->lock);
-
-	reg_val = uart_ra_read_8(dev, SCR);
-	reg_val &= ~(REG_MASK(SCR_TIE));
-	uart_ra_write_8(dev, SCR, reg_val);
-
-	irq_disable(data->irqn[UART_RA_INT_TXI]);
-
-	k_spin_unlock(&data->lock, key);
-}
-
-static int uart_ra_irq_tx_ready(const struct device *dev)
-{
-	const uint8_t reg_val = uart_ra_read_8(dev, SSR);
-	const uint8_t mask = REG_MASK(SSR_TEND) & REG_MASK(SSR_TDRE);
-
-	return (reg_val & mask) == mask;
-}
-
-static void uart_ra_irq_rx_enable(const struct device *dev)
-{
-	struct uart_ra_data *data = dev->data;
-	k_spinlock_key_t key;
-	uint16_t reg_val;
-
-	key = k_spin_lock(&data->lock);
-
-	reg_val = uart_ra_read_8(dev, SCR);
-	reg_val |= REG_MASK(SCR_RIE);
-	uart_ra_write_8(dev, SCR, reg_val);
-
-	irq_enable(data->irqn[UART_RA_INT_RXI]);
-
-	k_spin_unlock(&data->lock, key);
-}
-
-static void uart_ra_irq_rx_disable(const struct device *dev)
-{
-	struct uart_ra_data *data = dev->data;
-	k_spinlock_key_t key;
-	uint16_t reg_val;
-
-	key = k_spin_lock(&data->lock);
-
-	reg_val = uart_ra_read_8(dev, SCR);
-	reg_val &= ~REG_MASK(SCR_RIE);
-	uart_ra_write_8(dev, SCR, reg_val);
-
-	irq_disable(data->irqn[UART_RA_INT_RXI]);
-
-	k_spin_unlock(&data->lock, key);
-}
-
-static int uart_ra_irq_rx_ready(const struct device *dev)
-{
-	return !!(uart_ra_read_8(dev, SSR) & REG_MASK(SSR_RDRF));
-}
-
-static void uart_ra_irq_err_enable(const struct device *dev)
-{
-	struct uart_ra_data *data = dev->data;
-
-	irq_enable(data->irqn[UART_RA_INT_ERI]);
-}
-
-static void uart_ra_irq_err_disable(const struct device *dev)
-{
-	struct uart_ra_data *data = dev->data;
-
-	irq_disable(data->irqn[UART_RA_INT_ERI]);
-}
-
-static int uart_ra_irq_is_pending(const struct device *dev)
-{
-	return (uart_ra_irq_rx_ready(dev) && uart_ra_irq_is_enabled(dev, REG_MASK(SCR_RIE))) ||
-	       (uart_ra_irq_tx_ready(dev) && uart_ra_irq_is_enabled(dev, REG_MASK(SCR_TIE)));
-}
-
-static int uart_ra_irq_update(const struct device *dev)
-{
-	return 1;
-}
-
-static void uart_ra_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
-				     void *cb_data)
-{
-	struct uart_ra_data *data = dev->data;
-
-	data->callback = cb;
-	data->cb_data = cb_data;
-}
-
-/**
- * @brief Interrupt service routine.
- *
- * This simply calls the callback function, if one exists.
- *
- * @param arg Argument to ISR.
- */
-static inline void uart_ra_isr(const struct device *dev)
-{
-	struct uart_ra_data *data = dev->data;
-
-	if (data->callback) {
-		data->callback(dev, data->cb_data);
-	}
-}
-
-static void uart_ra_isr_rxi(const void *param)
-{
-	const struct device *dev = param;
-	struct uart_ra_data *data = dev->data;
-
-	uart_ra_isr(dev);
-	ra_icu_clear_int_flag(data->irqn[UART_RA_INT_RXI]);
-}
-
-static void uart_ra_isr_txi(const void *param)
-{
-	const struct device *dev = param;
-	struct uart_ra_data *data = dev->data;
-
-	uart_ra_isr(dev);
-	ra_icu_clear_int_flag(data->irqn[UART_RA_INT_TXI]);
-}
-
-static void uart_ra_isr_eri(const void *param)
-{
-	const struct device *dev = param;
-	struct uart_ra_data *data = dev->data;
-
-	uart_ra_isr(dev);
-	ra_icu_clear_int_flag(data->irqn[UART_RA_INT_ERI]);
-}
-
-#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
-
-static DEVICE_API(uart, uart_ra_driver_api) = {
-	.poll_in = uart_ra_poll_in,
-	.poll_out = uart_ra_poll_out,
-	.err_check = uart_ra_err_check,
-#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
-	.configure = uart_ra_configure,
-	.config_get = uart_ra_config_get,
-#endif
-#ifdef CONFIG_UART_INTERRUPT_DRIVEN
-	.fifo_fill = uart_ra_fifo_fill,
-	.fifo_read = uart_ra_fifo_read,
-	.irq_tx_enable = uart_ra_irq_tx_enable,
-	.irq_tx_disable = uart_ra_irq_tx_disable,
-	.irq_tx_ready = uart_ra_irq_tx_ready,
-	.irq_rx_enable = uart_ra_irq_rx_enable,
-	.irq_rx_disable = uart_ra_irq_rx_disable,
-	.irq_rx_ready = uart_ra_irq_rx_ready,
-	.irq_err_enable = uart_ra_irq_err_enable,
-	.irq_err_disable = uart_ra_irq_err_disable,
-	.irq_is_pending = uart_ra_irq_is_pending,
-	.irq_update = uart_ra_irq_update,
-	.irq_callback_set = uart_ra_irq_callback_set,
-#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
-};
-
-/* Device Instantiation */
-#define UART_RA_INIT_CFG(n)                                                                        \
-	PINCTRL_DT_DEFINE(DT_INST_PARENT(n));                                                      \
-	static const struct uart_ra_cfg uart_ra_cfg_##n = {                                        \
-		.regs = DT_REG_ADDR(DT_INST_PARENT(n)),                                            \
-		.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(DT_INST_PARENT(n))),                     \
-		.clock_id =                                                                        \
-			{                                                                          \
-				.mstp = DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, mstp),         \
-				.stop_bit = DT_CLOCKS_CELL_BY_IDX(DT_INST_PARENT(n), 0, stop_bit), \
-			},                                                                         \
-		.pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST_PARENT(n)),                              \
-		IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN,                                           \
-			   (.irq_config_func = irq_config_func_##n,))}
-
-#ifdef CONFIG_UART_INTERRUPT_DRIVEN
-
-#define RA_IRQ_CONNECT_DYNAMIC(n, name, dev, isr)                                                  \
-	ra_icu_irq_connect_dynamic(DT_IRQ_BY_NAME(DT_INST_PARENT(n), name, irq),                   \
-				   DT_IRQ_BY_NAME(DT_INST_PARENT(n), name, priority), isr, dev,    \
-				   DT_IRQ_BY_NAME(DT_INST_PARENT(n), name, flags));
-
-#define RA_IRQ_DISCONNECT_DYNAMIC(n, name, dev, isr)                                               \
-	ra_icu_irq_disconnect_dynamic(irqn, 0, NULL, NULL, 0)
-
-#define UART_RA_CONFIG_FUNC(n)                                                                     \
-	static int irq_config_func_##n(const struct device *dev)                                   \
-	{                                                                                          \
-		struct uart_ra_data *data = dev->data;                                             \
-		int irqn;                                                                          \
-                                                                                                   \
-		irqn = RA_IRQ_CONNECT_DYNAMIC(n, rxi, dev, uart_ra_isr_rxi);                       \
-		if (irqn < 0) {                                                                    \
-			return irqn;                                                               \
-		}                                                                                  \
-		data->irqn[UART_RA_INT_RXI] = irqn;                                                \
-		irqn = RA_IRQ_CONNECT_DYNAMIC(n, txi, dev, uart_ra_isr_txi);                       \
-		if (irqn < 0) {                                                                    \
-			goto err_txi;                                                              \
-		}                                                                                  \
-		data->irqn[UART_RA_INT_TXI] = irqn;                                                \
-		irqn = RA_IRQ_CONNECT_DYNAMIC(n, eri, dev, uart_ra_isr_eri);                       \
-		if (irqn < 0) {                                                                    \
-			goto err_eri;                                                              \
-		}                                                                                  \
-		data->irqn[UART_RA_INT_ERI] = irqn;                                                \
-		return 0;                                                                          \
-                                                                                                   \
-err_eri:                                                                                           \
-		RA_IRQ_DISCONNECT_DYNAMIC(data->irq[UART_RA_INT_TXI], eri, dev, uart_ra_isr_eri);  \
-err_txi:                                                                                           \
-		RA_IRQ_DISCONNECT_DYNAMIC(data->irq[UART_RA_INT_RXI], txi, dev, uart_ra_isr_txi);  \
-                                                                                                   \
-		return irqn;                                                                       \
-	}
-#else
-#define UART_RA_CONFIG_FUNC(n)
-#endif
-
-#define UART_RA_INIT(n)                                                                            \
-	UART_RA_CONFIG_FUNC(n)                                                                     \
-	UART_RA_INIT_CFG(n);                                                                       \
-                                                                                                   \
-	static struct uart_ra_data uart_ra_data_##n = {                                            \
-		.current_config = {                                                                \
-			.baudrate = DT_INST_PROP(n, current_speed),                                \
-			.parity = UART_CFG_PARITY_NONE,                                            \
-			.stop_bits = UART_CFG_STOP_BITS_1,                                         \
-			.data_bits = UART_CFG_DATA_BITS_8,                                         \
-			.flow_ctrl = UART_CFG_FLOW_CTRL_NONE,                                      \
-		},                                                                                 \
-	};                                                                                         \
-                                                                                                   \
-	DEVICE_DT_INST_DEFINE(n, uart_ra_init, NULL, &uart_ra_data_##n, &uart_ra_cfg_##n,          \
-			      PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, &uart_ra_driver_api);
-
-DT_INST_FOREACH_STATUS_OKAY(UART_RA_INIT)
diff --git a/drivers/serial/uart_renesas_ra8_sci_b.c b/drivers/serial/uart_renesas_ra8_sci_b.c
index e9209ffcc29..cfb8c923f6c 100644
--- a/drivers/serial/uart_renesas_ra8_sci_b.c
+++ b/drivers/serial/uart_renesas_ra8_sci_b.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -10,6 +10,9 @@
 #include <zephyr/drivers/pinctrl.h>
 #include <zephyr/sys/util.h>
 #include <zephyr/irq.h>
+#include <zephyr/pm/device.h>
+#include <zephyr/pm/policy.h>
+#include <zephyr/pm/device_runtime.h>
 #include <soc.h>
 #include "r_sci_b_uart.h"
 #include "r_dtc.h"
@@ -73,8 +76,78 @@ struct uart_ra_sci_b_data {
 	uart_callback_t async_user_cb;
 	void *async_user_cb_data;
 #endif
+#ifdef CONFIG_PM
+	bool rx_ongoing;
+	bool tx_ongoing;
+#endif
 };
 
+#if CONFIG_PM
+static inline void uart_ra_sci_b_rx_pm_policy_state_lock_get(const struct device *dev)
+{
+	struct uart_ra_sci_b_data *data = dev->data;
+
+	if (!data->rx_ongoing) {
+		data->rx_ongoing = true;
+#if CONFIG_PM_NEED_ALL_DEVICES_IDLE
+		pm_device_busy_set(dev);
+#else
+		pm_policy_state_lock_get(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES);
+		pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
+#endif
+	}
+}
+
+static inline void uart_ra_sci_b_rx_pm_policy_state_lock_put(const struct device *dev)
+{
+	struct uart_ra_sci_b_data *data = dev->data;
+
+	if (data->rx_ongoing) {
+		data->rx_ongoing = false;
+#if CONFIG_PM_NEED_ALL_DEVICES_IDLE
+		if (!data->tx_ongoing) {
+			pm_device_busy_clear(dev);
+		}
+#else
+		pm_policy_state_lock_put(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES);
+		pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
+#endif
+	}
+}
+
+static inline void uart_ra_sci_b_tx_pm_policy_state_lock_get(const struct device *dev)
+{
+	struct uart_ra_sci_b_data *data = dev->data;
+
+	if (!data->tx_ongoing) {
+		data->tx_ongoing = true;
+#if CONFIG_PM_NEED_ALL_DEVICES_IDLE
+		pm_device_busy_set(dev);
+#else
+		pm_policy_state_lock_get(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES);
+		pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
+#endif
+	}
+}
+
+static inline void uart_ra_sci_b_tx_pm_policy_state_lock_put(const struct device *dev)
+{
+	struct uart_ra_sci_b_data *data = dev->data;
+
+	if (data->tx_ongoing) {
+		data->tx_ongoing = false;
+#if CONFIG_PM_NEED_ALL_DEVICES_IDLE
+		if (!data->rx_ongoing) {
+			pm_device_busy_clear(dev);
+		}
+#else
+		pm_policy_state_lock_put(PM_STATE_RUNTIME_IDLE, PM_ALL_SUBSTATES);
+		pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
+#endif
+	}
+}
+#endif
+
 static int uart_ra_sci_b_poll_in(const struct device *dev, unsigned char *c)
 {
 	const struct uart_ra_sci_b_config *cfg = dev->config;
@@ -100,10 +173,21 @@ static void uart_ra_sci_b_poll_out(const struct device *dev, unsigned char c)
 {
 	const struct uart_ra_sci_b_config *cfg = dev->config;
 
+#if CONFIG_PM
+	uart_ra_sci_b_tx_pm_policy_state_lock_get(dev);
+#endif
+
 	while (cfg->regs->CSR_b.TEND == 0U) {
 	}
 
 	cfg->regs->TDR_BY = c;
+
+	while (cfg->regs->CSR_b.TEND == 0U) {
+	}
+
+#if CONFIG_PM
+	uart_ra_sci_b_tx_pm_policy_state_lock_put(dev);
+#endif
 }
 
 static int uart_ra_sci_b_err_check(const struct device *dev)
@@ -311,6 +395,10 @@ static void uart_ra_sci_b_irq_tx_enable(const struct device *dev)
 {
 	const struct uart_ra_sci_b_config *cfg = dev->config;
 
+#if CONFIG_PM
+	uart_ra_sci_b_tx_pm_policy_state_lock_get(dev);
+#endif
+
 	cfg->regs->CCR0 |= (BIT(R_SCI_B0_CCR0_TIE_Pos) | BIT(R_SCI_B0_CCR0_TEIE_Pos));
 }
 
@@ -319,6 +407,10 @@ static void uart_ra_sci_b_irq_tx_disable(const struct device *dev)
 	const struct uart_ra_sci_b_config *cfg = dev->config;
 
 	cfg->regs->CCR0 &= ~(BIT(R_SCI_B0_CCR0_TIE_Pos) | BIT(R_SCI_B0_CCR0_TEIE_Pos));
+
+#if CONFIG_PM
+	uart_ra_sci_b_tx_pm_policy_state_lock_put(dev);
+#endif
 }
 
 static int uart_ra_sci_b_irq_tx_ready(const struct device *dev)
@@ -342,6 +434,10 @@ static void uart_ra_sci_b_irq_rx_enable(const struct device *dev)
 {
 	const struct uart_ra_sci_b_config *cfg = dev->config;
 
+#if CONFIG_PM
+	uart_ra_sci_b_rx_pm_policy_state_lock_get(dev);
+#endif
+
 	cfg->regs->CCR0_b.RIE = 1U;
 }
 
@@ -350,6 +446,10 @@ static void uart_ra_sci_b_irq_rx_disable(const struct device *dev)
 	const struct uart_ra_sci_b_config *cfg = dev->config;
 
 	cfg->regs->CCR0_b.RIE = 0U;
+
+#if CONFIG_PM
+	uart_ra_sci_b_rx_pm_policy_state_lock_put(dev);
+#endif
 }
 
 static int uart_ra_sci_b_irq_rx_ready(const struct device *dev)
@@ -637,6 +737,10 @@ static int uart_ra_sci_b_async_tx(const struct device *dev, const uint8_t *buf,
 	data->tx_buffer = (uint8_t *)buf;
 	data->tx_buffer_cap = len;
 
+#if CONFIG_PM
+	uart_ra_sci_b_tx_pm_policy_state_lock_get(dev);
+#endif
+
 	uart_ra_sci_b_async_timer_start(&data->tx_timeout_work, timeout);
 
 unlock:
@@ -687,6 +791,10 @@ static int uart_ra_sci_b_async_tx_abort(const struct device *dev)
 
 	async_tx_abort(dev);
 
+#if CONFIG_PM
+	uart_ra_sci_b_tx_pm_policy_state_lock_put(dev);
+#endif
+
 	return 0;
 }
 
@@ -720,6 +828,10 @@ static int uart_ra_sci_b_async_rx_enable(const struct device *dev, uint8_t *buf,
 		goto unlock;
 	}
 
+#if CONFIG_PM
+	uart_ra_sci_b_rx_pm_policy_state_lock_get(dev);
+#endif
+
 	data->rx_timeout = timeout;
 	data->rx_buffer = buf;
 	data->rx_buffer_cap = len;
@@ -772,6 +884,10 @@ static int uart_ra_sci_b_async_rx_disable(const struct device *dev)
 	cfg->regs->CFCLR_b.RDRFC = 1U;
 
 unlock:
+#if CONFIG_PM
+	uart_ra_sci_b_rx_pm_policy_state_lock_put(dev);
+#endif
+
 	irq_unlock(key);
 	return err;
 }
@@ -833,6 +949,40 @@ static void uart_ra_sci_b_callback_adapter(struct st_uart_callback_arg *fsp_args
 
 #endif /* CONFIG_UART_ASYNC_API */
 
+#ifdef CONFIG_PM_DEVICE
+static int uart_ra_sci_b_pm_action(const struct device *dev, enum pm_device_action action)
+{
+	struct uart_ra_sci_b_data *data = dev->data;
+	fsp_err_t fsp_err;
+
+	switch (action) {
+	case PM_DEVICE_ACTION_SUSPEND:
+		/* Deinitialize the device */
+		fsp_err = R_SCI_B_UART_Close(&data->sci);
+		__ASSERT(fsp_err == 0, "sci_uart: initialization: close failed");
+		break;
+
+	case PM_DEVICE_ACTION_RESUME:
+		/* Reinitialize the device */
+		int ret = uart_ra_sci_b_apply_config(&data->uart_config, &data->fsp_config,
+						     &data->fsp_config_extend,
+						     &data->fsp_baud_setting);
+		if (ret < 0) {
+			return ret;
+		}
+
+		fsp_err = R_SCI_B_UART_Open(&data->sci, &data->fsp_config);
+		__ASSERT(fsp_err == 0, "sci_uart: initialization: open failed");
+		break;
+
+	default:
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_PM_DEVICE */
+
 static DEVICE_API(uart, uart_ra_sci_b_driver_api) = {
 	.poll_in = uart_ra_sci_b_poll_in,
 	.poll_out = uart_ra_sci_b_poll_out,
@@ -971,6 +1121,9 @@ static void uart_ra_sci_b_tei_isr(const struct device *dev)
 #if defined(CONFIG_UART_ASYNC_API)
 	k_work_cancel_delayable(&data->tx_timeout_work);
 	sci_b_uart_tei_isr();
+#if CONFIG_PM
+	uart_ra_sci_b_tx_pm_policy_state_lock_put(dev);
+#endif
 #else
 	R_ICU->IELSR_b[data->fsp_config.tei_irq].IR = 0U;
 #endif
@@ -995,28 +1148,23 @@ static void uart_ra_sci_b_eri_isr(const struct device *dev)
 
 #endif /* defined(CONFIG_UART_INTERRUPT_DRIVEN) || defined(CONFIG_UART_ASYNC_API) */
 
-#define _ELC_EVENT_SCI_RXI(channel) ELC_EVENT_SCI##channel##_RXI
-#define _ELC_EVENT_SCI_TXI(channel) ELC_EVENT_SCI##channel##_TXI
-#define _ELC_EVENT_SCI_TEI(channel) ELC_EVENT_SCI##channel##_TEI
-#define _ELC_EVENT_SCI_ERI(channel) ELC_EVENT_SCI##channel##_ERI
-
-#define ELC_EVENT_SCI_RXI(channel) _ELC_EVENT_SCI_RXI(channel)
-#define ELC_EVENT_SCI_TXI(channel) _ELC_EVENT_SCI_TXI(channel)
-#define ELC_EVENT_SCI_TEI(channel) _ELC_EVENT_SCI_TEI(channel)
-#define ELC_EVENT_SCI_ERI(channel) _ELC_EVENT_SCI_ERI(channel)
+#define EVENT_SCI_RXI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_SCI, channel, _RXI))
+#define EVENT_SCI_TXI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_SCI, channel, _TXI))
+#define EVENT_SCI_TEI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_SCI, channel, _TEI))
+#define EVENT_SCI_ERI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_SCI, channel, _ERI))
 
 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) || defined(CONFIG_UART_ASYNC_API)
 
 #define UART_RA_SCI_B_IRQ_CONFIG_INIT(index)                                                       \
 	do {                                                                                       \
 		R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq)] =                    \
-			ELC_EVENT_SCI_RXI(DT_INST_PROP(index, channel));                           \
+			EVENT_SCI_RXI(DT_INST_PROP(index, channel));                               \
 		R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq)] =                    \
-			ELC_EVENT_SCI_TXI(DT_INST_PROP(index, channel));                           \
+			EVENT_SCI_TXI(DT_INST_PROP(index, channel));                               \
 		R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq)] =                    \
-			ELC_EVENT_SCI_TEI(DT_INST_PROP(index, channel));                           \
+			EVENT_SCI_TEI(DT_INST_PROP(index, channel));                               \
 		R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, irq)] =                    \
-			ELC_EVENT_SCI_ERI(DT_INST_PROP(index, channel));                           \
+			EVENT_SCI_ERI(DT_INST_PROP(index, channel));                               \
                                                                                                    \
 		IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq),                       \
 			    DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, priority),                  \
@@ -1108,6 +1256,10 @@ static void uart_ra_sci_b_eri_isr(const struct device *dev)
 #define UART_RA_SCI_B_DTC_INIT(index)
 #endif
 
+#define FLOW_CTRL_PARAMETER(index)                                                                 \
+	COND_CODE_1(DT_INST_PROP(index, hw_flow_control),                                          \
+	(UART_CFG_FLOW_CTRL_RTS_CTS), (UART_CFG_FLOW_CTRL_NONE))
+
 #define UART_RA_SCI_B_INIT(index)                                                                  \
 	PINCTRL_DT_DEFINE(DT_INST_PARENT(index));                                                  \
                                                                                                    \
@@ -1123,9 +1275,7 @@ static void uart_ra_sci_b_eri_isr(const struct device *dev)
 				.parity = UART_CFG_PARITY_NONE,                                    \
 				.stop_bits = UART_CFG_STOP_BITS_1,                                 \
 				.data_bits = UART_CFG_DATA_BITS_8,                                 \
-				.flow_ctrl = COND_CODE_1(DT_INST_PROP(index, hw_flow_control),     \
-							 (UART_CFG_FLOW_CTRL_RTS_CTS),             \
-							 (UART_CFG_FLOW_CTRL_NONE)),               \
+				.flow_ctrl = FLOW_CTRL_PARAMETER(index),                           \
 			},                                                                         \
 		.fsp_config =                                                                      \
 			{                                                                          \
@@ -1155,7 +1305,8 @@ static void uart_ra_sci_b_eri_isr(const struct device *dev)
 		return 0;                                                                          \
 	}                                                                                          \
                                                                                                    \
-	DEVICE_DT_INST_DEFINE(index, uart_ra_sci_b_init_##index, NULL,                             \
+	PM_DEVICE_DT_INST_DEFINE(index, uart_ra_sci_b_pm_action);                                  \
+	DEVICE_DT_INST_DEFINE(index, uart_ra_sci_b_init_##index, PM_DEVICE_DT_INST_GET(index),     \
 			      &uart_ra_sci_b_data_##index, &uart_ra_sci_b_config_##index,          \
 			      PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY,                           \
 			      &uart_ra_sci_b_driver_api);
diff --git a/drivers/serial/uart_renesas_ra_sci.c b/drivers/serial/uart_renesas_ra_sci.c
index 24ce1f0a2f8..a6fa77332af 100644
--- a/drivers/serial/uart_renesas_ra_sci.c
+++ b/drivers/serial/uart_renesas_ra_sci.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -33,7 +33,6 @@ void sci_uart_eri_isr(void);
 
 struct uart_ra_sci_config {
 	const struct pinctrl_dev_config *pcfg;
-
 	R_SCI0_Type * const regs;
 };
 
@@ -1054,15 +1053,10 @@ static void uart_ra_sci_eri_isr(const struct device *dev)
 }
 #endif
 
-#define _ELC_EVENT_SCI_RXI(channel) ELC_EVENT_SCI##channel##_RXI
-#define _ELC_EVENT_SCI_TXI(channel) ELC_EVENT_SCI##channel##_TXI
-#define _ELC_EVENT_SCI_TEI(channel) ELC_EVENT_SCI##channel##_TEI
-#define _ELC_EVENT_SCI_ERI(channel) ELC_EVENT_SCI##channel##_ERI
-
-#define ELC_EVENT_SCI_RXI(channel) _ELC_EVENT_SCI_RXI(channel)
-#define ELC_EVENT_SCI_TXI(channel) _ELC_EVENT_SCI_TXI(channel)
-#define ELC_EVENT_SCI_TEI(channel) _ELC_EVENT_SCI_TEI(channel)
-#define ELC_EVENT_SCI_ERI(channel) _ELC_EVENT_SCI_ERI(channel)
+#define EVENT_SCI_RXI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_SCI, channel, _RXI))
+#define EVENT_SCI_TXI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_SCI, channel, _TXI))
+#define EVENT_SCI_TEI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_SCI, channel, _TEI))
+#define EVENT_SCI_ERI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_SCI, channel, _ERI))
 
 #if CONFIG_UART_ASYNC_API
 #define UART_RA_SCI_ASYNC_INIT(index)                                                              \
@@ -1137,13 +1131,13 @@ static void uart_ra_sci_eri_isr(const struct device *dev)
 #define UART_RA_SCI_IRQ_INIT(index)                                                                \
 	{                                                                                          \
 		R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq)] =                    \
-			ELC_EVENT_SCI_RXI(DT_INST_PROP(index, channel));                           \
+			EVENT_SCI_RXI(DT_INST_PROP(index, channel));                               \
 		R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), txi, irq)] =                    \
-			ELC_EVENT_SCI_TXI(DT_INST_PROP(index, channel));                           \
+			EVENT_SCI_TXI(DT_INST_PROP(index, channel));                               \
 		R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), tei, irq)] =                    \
-			ELC_EVENT_SCI_TEI(DT_INST_PROP(index, channel));                           \
+			EVENT_SCI_TEI(DT_INST_PROP(index, channel));                               \
 		R_ICU->IELSR[DT_IRQ_BY_NAME(DT_INST_PARENT(index), eri, irq)] =                    \
-			ELC_EVENT_SCI_ERI(DT_INST_PROP(index, channel));                           \
+			EVENT_SCI_ERI(DT_INST_PROP(index, channel));                               \
                                                                                                    \
 		IRQ_CONNECT(DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, irq),                       \
 			    DT_IRQ_BY_NAME(DT_INST_PARENT(index), rxi, priority),                  \
@@ -1166,6 +1160,10 @@ static void uart_ra_sci_eri_isr(const struct device *dev)
 #define UART_RA_SCI_IRQ_INIT(index)
 #endif
 
+#define FLOW_CTRL_PARAMETER(index)                                                                 \
+	COND_CODE_1(DT_INST_PROP(index, hw_flow_control),                                          \
+	(UART_CFG_FLOW_CTRL_RTS_CTS), (UART_CFG_FLOW_CTRL_NONE))
+
 #define UART_RA_SCI_INIT(index)                                                                    \
 	PINCTRL_DT_DEFINE(DT_INST_PARENT(index));                                                  \
 	static const struct uart_ra_sci_config uart_ra_sci_config_##index = {                      \
@@ -1180,9 +1178,7 @@ static void uart_ra_sci_eri_isr(const struct device *dev)
 				.parity = UART_CFG_PARITY_NONE,                                    \
 				.stop_bits = UART_CFG_STOP_BITS_1,                                 \
 				.data_bits = UART_CFG_DATA_BITS_8,                                 \
-				.flow_ctrl = COND_CODE_1(DT_INST_PROP(index, hw_flow_control),     \
-							 (UART_CFG_FLOW_CTRL_RTS_CTS),             \
-							 (UART_CFG_FLOW_CTRL_NONE)),               \
+				.flow_ctrl = FLOW_CTRL_PARAMETER(index),                           \
 			},                                                                         \
 		.fsp_config =                                                                      \
 			{                                                                          \
diff --git a/drivers/serial/uart_renesas_rz_sci.c b/drivers/serial/uart_renesas_rz_sci.c
new file mode 100644
index 00000000000..3cd63a4f75d
--- /dev/null
+++ b/drivers/serial/uart_renesas_rz_sci.c
@@ -0,0 +1,501 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_rz_sci_uart
+
+#include <zephyr/drivers/uart.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/irq.h>
+#include "r_sci_uart.h"
+
+LOG_MODULE_REGISTER(rz_sci_uart);
+
+struct uart_rz_sci_config {
+	const struct pinctrl_dev_config *pin_config;
+	const uart_api_t *fsp_api;
+};
+
+struct uart_rz_sci_int {
+	bool rx_fifo_busy;
+	bool irq_rx_enable;
+	bool irq_tx_enable;
+	uint8_t rx_byte;
+	uint8_t tx_byte;
+	uart_event_t event;
+};
+
+struct uart_rz_sci_data {
+	struct uart_config uart_config;
+	uart_cfg_t *fsp_cfg;
+	struct uart_rz_sci_int int_data;
+	sci_uart_instance_ctrl_t *fsp_ctrl;
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	uart_irq_callback_user_data_t callback;
+	void *callback_data;
+#endif
+};
+
+#define SCI_UART_ERROR_RATE_x1000 (5000)
+
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+void sci_uart_rxi_isr(void);
+void sci_uart_txi_isr(void);
+void sci_uart_tei_isr(void);
+void sci_uart_eri_isr(void);
+#endif
+
+static int uart_rz_sci_poll_in(const struct device *dev, unsigned char *c)
+{
+	struct uart_rz_sci_data *data = dev->data;
+	R_SCI0_Type *reg = data->fsp_ctrl->p_reg;
+
+	if (reg->FRSR_b.R == 0U) {
+		/* There are no characters available to read. */
+		return -1;
+	}
+
+	*c = (unsigned char)reg->RDR_b.RDAT;
+	return 0;
+}
+
+static void uart_rz_sci_poll_out(const struct device *dev, unsigned char c)
+{
+	struct uart_rz_sci_data *data = dev->data;
+	R_SCI0_Type *reg = data->fsp_ctrl->p_reg;
+	uint8_t key;
+
+	key = irq_lock();
+	while (!reg->CSR_b.TDRE) {
+		;
+	}
+
+	reg->TDR_b.TDAT = c;
+	reg->CFCLR_b.TDREC = 1;
+
+	while (!reg->CSR_b.TEND) {
+		;
+	}
+	irq_unlock(key);
+}
+
+static int uart_rz_sci_err_check(const struct device *dev)
+{
+	struct uart_rz_sci_data *data = dev->data;
+	uart_event_t event = data->int_data.event;
+	int err = 0;
+
+	if (event & UART_EVENT_ERR_OVERFLOW) {
+		err |= UART_ERROR_OVERRUN;
+	}
+	if (event & UART_EVENT_ERR_FRAMING) {
+		err |= UART_ERROR_FRAMING;
+	}
+	if (event & UART_EVENT_ERR_PARITY) {
+		err |= UART_ERROR_PARITY;
+	}
+
+	return err;
+}
+
+static int uart_rz_sci_apply_config(const struct device *dev)
+{
+	struct uart_rz_sci_data *data = dev->data;
+
+	struct uart_config *uart_config = &data->uart_config;
+	uart_cfg_t *fsp_cfg = data->fsp_cfg;
+
+	sci_baud_setting_t baud_setting;
+	sci_uart_extended_cfg_t *fsp_config_extend = (sci_uart_extended_cfg_t *)fsp_cfg->p_extend;
+
+	fsp_err_t fsp_err;
+	sci_uart_baud_calculation_t baud_target;
+
+	baud_target.baudrate = uart_config->baudrate;
+	baud_target.bitrate_modulation = false;
+	baud_target.baud_rate_error_x_1000 = SCI_UART_ERROR_RATE_x1000;
+
+	fsp_err = R_SCI_UART_BaudCalculate(&baud_target, fsp_config_extend->clock_source,
+					   &baud_setting);
+	if (fsp_err) {
+		return -EIO;
+	}
+
+	memcpy(fsp_config_extend->p_baud_setting, &baud_setting, sizeof(sci_baud_setting_t));
+
+	switch (uart_config->data_bits) {
+	case UART_CFG_DATA_BITS_7:
+		fsp_cfg->data_bits = UART_DATA_BITS_7;
+		break;
+	case UART_CFG_DATA_BITS_8:
+		fsp_cfg->data_bits = UART_DATA_BITS_8;
+		break;
+	case UART_CFG_DATA_BITS_9:
+		fsp_cfg->data_bits = UART_DATA_BITS_9;
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	switch (uart_config->parity) {
+	case UART_CFG_PARITY_NONE:
+		fsp_cfg->parity = UART_PARITY_OFF;
+		break;
+	case UART_CFG_PARITY_ODD:
+		fsp_cfg->parity = UART_PARITY_ODD;
+		break;
+	case UART_CFG_PARITY_EVEN:
+		fsp_cfg->parity = UART_PARITY_EVEN;
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	switch (uart_config->stop_bits) {
+	case UART_CFG_STOP_BITS_1:
+		fsp_cfg->stop_bits = UART_STOP_BITS_1;
+		break;
+	case UART_CFG_STOP_BITS_2:
+		fsp_cfg->stop_bits = UART_STOP_BITS_2;
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	switch (uart_config->flow_ctrl) {
+	case UART_CFG_FLOW_CTRL_NONE:
+		fsp_config_extend->flow_control = 0;
+		fsp_config_extend->rs485_setting.enable = SCI_UART_RS485_DISABLE;
+		break;
+	case UART_CFG_FLOW_CTRL_RTS_CTS:
+		fsp_config_extend->flow_control = SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS;
+		fsp_config_extend->rs485_setting.enable = SCI_UART_RS485_DISABLE;
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
+
+static int uart_rz_sci_configure(const struct device *dev, const struct uart_config *cfg)
+{
+	int err;
+	fsp_err_t fsp_err;
+	const struct uart_rz_sci_config *config = dev->config;
+	struct uart_rz_sci_data *data = dev->data;
+
+	memcpy(&data->uart_config, cfg, sizeof(struct uart_config));
+
+	err = uart_rz_sci_apply_config(dev);
+	if (err) {
+		return err;
+	}
+
+	fsp_err = config->fsp_api->close(data->fsp_ctrl);
+	if (fsp_err) {
+		return -EIO;
+	}
+
+	fsp_err = config->fsp_api->open(data->fsp_ctrl, data->fsp_cfg);
+	if (fsp_err) {
+		return -EIO;
+	}
+
+	return err;
+}
+
+static int uart_rz_sci_config_get(const struct device *dev, struct uart_config *cfg)
+{
+	struct uart_rz_sci_data *data = dev->data;
+
+	memcpy(cfg, &data->uart_config, sizeof(struct uart_config));
+	return 0;
+}
+
+#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
+
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+
+static int uart_rz_sci_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size)
+{
+	struct uart_rz_sci_data *data = dev->data;
+	sci_uart_instance_ctrl_t *fsp_ctrl = data->fsp_ctrl;
+
+	fsp_ctrl->tx_src_bytes = size;
+	fsp_ctrl->p_tx_src = tx_data;
+
+	sci_uart_txi_isr();
+
+	return (size - fsp_ctrl->tx_src_bytes);
+}
+
+static int uart_rz_sci_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
+{
+	struct uart_rz_sci_data *data = dev->data;
+	sci_uart_instance_ctrl_t *fsp_ctrl = data->fsp_ctrl;
+
+	fsp_ctrl->rx_dest_bytes = size;
+	fsp_ctrl->p_rx_dest = rx_data;
+
+	sci_uart_rxi_isr();
+
+	data->int_data.rx_fifo_busy = false;
+
+	return (size - fsp_ctrl->rx_dest_bytes);
+}
+
+static void uart_rz_sci_irq_rx_enable(const struct device *dev)
+{
+	const struct uart_rz_sci_config *config = dev->config;
+	struct uart_rz_sci_data *data = dev->data;
+
+	data->int_data.irq_rx_enable = true;
+
+	/* Prepare 1-byte buffer to receive, it will be overwritten by fifo read */
+	config->fsp_api->read(data->fsp_ctrl, &(data->int_data.rx_byte), 1);
+}
+
+static void uart_rz_sci_irq_rx_disable(const struct device *dev)
+{
+	struct uart_rz_sci_data *data = dev->data;
+
+	data->int_data.irq_rx_enable = false;
+}
+
+static void uart_rz_sci_irq_tx_enable(const struct device *dev)
+{
+	struct uart_rz_sci_data *data = dev->data;
+	const struct uart_rz_sci_config *config = dev->config;
+
+	data->int_data.irq_tx_enable = true;
+
+	/* Trigger TX with a NULL frame */
+	/* It is expected not to be sent, and will be overwritten by the fifo fill */
+	data->int_data.tx_byte = '\0';
+	config->fsp_api->write(data->fsp_ctrl, &data->int_data.tx_byte, 1);
+}
+
+static void uart_rz_sci_irq_tx_disable(const struct device *dev)
+{
+	struct uart_rz_sci_data *data = dev->data;
+
+	data->int_data.irq_tx_enable = false;
+}
+
+static int uart_rz_sci_irq_tx_ready(const struct device *dev)
+{
+	struct uart_rz_sci_data *data = dev->data;
+
+	return data->int_data.irq_tx_enable;
+}
+
+static int uart_rz_sci_irq_rx_ready(const struct device *dev)
+{
+	struct uart_rz_sci_data *data = dev->data;
+
+	return data->int_data.rx_fifo_busy && data->int_data.irq_rx_enable;
+}
+
+static int uart_rz_sci_irq_is_pending(const struct device *dev)
+{
+	return (uart_rz_sci_irq_tx_ready(dev)) || (uart_rz_sci_irq_rx_ready(dev));
+}
+
+static void uart_rz_sci_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
+					 void *cb_data)
+{
+	struct uart_rz_sci_data *data = dev->data;
+
+	data->callback = cb;
+	data->callback_data = cb_data;
+}
+
+static int uart_rz_sci_irq_update(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+	return 1;
+}
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+
+static DEVICE_API(uart, uart_rz_sci_driver_api) = {
+	.poll_in = uart_rz_sci_poll_in,
+	.poll_out = uart_rz_sci_poll_out,
+	.err_check = uart_rz_sci_err_check,
+#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
+	.configure = uart_rz_sci_configure,
+	.config_get = uart_rz_sci_config_get,
+#endif
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	.fifo_fill = uart_rz_sci_fifo_fill,
+	.fifo_read = uart_rz_sci_fifo_read,
+	.irq_rx_enable = uart_rz_sci_irq_rx_enable,
+	.irq_rx_disable = uart_rz_sci_irq_rx_disable,
+	.irq_tx_enable = uart_rz_sci_irq_tx_enable,
+	.irq_tx_disable = uart_rz_sci_irq_tx_disable,
+	.irq_tx_ready = uart_rz_sci_irq_tx_ready,
+	.irq_rx_ready = uart_rz_sci_irq_rx_ready,
+	.irq_is_pending = uart_rz_sci_irq_is_pending,
+	.irq_callback_set = uart_rz_sci_irq_callback_set,
+	.irq_update = uart_rz_sci_irq_update,
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+};
+
+static int uart_rz_init(const struct device *dev)
+{
+	const struct uart_rz_sci_config *config = dev->config;
+	struct uart_rz_sci_data *data = dev->data;
+	int ret;
+
+	ret = pinctrl_apply_state(config->pin_config, PINCTRL_STATE_DEFAULT);
+	if (ret < 0) {
+		return ret;
+	}
+
+	/* uart_rz_sci_apply_config must be called first before open api */
+	ret = uart_rz_sci_apply_config(dev);
+	if (ret < 0) {
+		return ret;
+	}
+
+	config->fsp_api->open(data->fsp_ctrl, data->fsp_cfg);
+
+	return 0;
+}
+
+static void uart_rz_sci_rxi_isr(const struct device *dev)
+{
+	struct uart_rz_sci_data *data = dev->data;
+
+	data->int_data.rx_fifo_busy = true;
+	if (data->callback) {
+		data->callback(dev, data->callback_data);
+	}
+}
+
+static void uart_rz_sci_txi_isr(const struct device *dev)
+{
+	struct uart_rz_sci_data *data = dev->data;
+
+	if (data->callback) {
+		data->callback(dev, data->callback_data);
+	}
+}
+
+static void uart_rz_sci_tei_isr(const struct device *dev)
+{
+	sci_uart_tei_isr();
+}
+
+static void uart_rz_sci_eri_isr(const struct device *dev)
+{
+	sci_uart_eri_isr();
+}
+
+static void uart_rz_sci_event_handler(uart_callback_args_t *p_args)
+{
+	const struct device *dev = (const struct device *)p_args->p_context;
+	struct uart_rz_sci_data *data = dev->data;
+
+	data->int_data.event = p_args->event;
+	switch (p_args->event) {
+	case UART_EVENT_RX_CHAR:
+		data->int_data.rx_byte = p_args->data;
+		break;
+	case UART_EVENT_RX_COMPLETE:
+		break;
+	case UART_EVENT_TX_DATA_EMPTY:
+		break;
+	case UART_EVENT_TX_COMPLETE:
+		break;
+	default:
+		break;
+	}
+}
+
+#define SCI_NODE(idx) DT_INST_PARENT(idx)
+#define UART_RZ_IRQ_CONNECT(n, irq_name, isr)                                                      \
+	do {                                                                                       \
+		IRQ_CONNECT(DT_IRQ_BY_NAME(SCI_NODE(n), irq_name, irq),                            \
+			    DT_IRQ_BY_NAME(SCI_NODE(n), irq_name, priority), isr,                  \
+			    DEVICE_DT_INST_GET(n), DT_IRQ_BY_NAME(SCI_NODE(n), irq_name, flags));  \
+		irq_enable(DT_IRQ_BY_NAME(SCI_NODE(n), irq_name, irq));                            \
+	} while (0)
+
+#define UART_RZ_CONFIG_FUNC(n)                                                                     \
+	UART_RZ_IRQ_CONNECT(n, eri, uart_rz_sci_eri_isr);                                          \
+	UART_RZ_IRQ_CONNECT(n, rxi, uart_rz_sci_rxi_isr);                                          \
+	UART_RZ_IRQ_CONNECT(n, txi, uart_rz_sci_txi_isr);                                          \
+	UART_RZ_IRQ_CONNECT(n, tei, uart_rz_sci_tei_isr);
+
+#define UART_RZ_INIT(n)                                                                            \
+	static sci_baud_setting_t g_uart##n##_baud_setting;                                        \
+	static sci_uart_extended_cfg_t g_uart##n##_cfg_extend = {                                  \
+		.clock = SCI_UART_CLOCK_INT,                                                       \
+		.rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE,                                  \
+		.noise_cancel = SCI_UART_NOISE_CANCELLATION_ENABLE,                                \
+		.rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX,                                   \
+		.p_baud_setting = &g_uart##n##_baud_setting,                                       \
+		.clock_source = SCI_UART_CLOCK_SOURCE_SCI0ASYNCCLK,                                \
+		.flow_control = SCI_UART_FLOW_CONTROL_RTS,                                         \
+		.flow_control_pin = 0xFF,                                                          \
+		.rs485_setting =                                                                   \
+			{                                                                          \
+				.enable = SCI_UART_RS485_DISABLE,                                  \
+				.polarity = SCI_UART_RS485_DE_POLARITY_HIGH,                       \
+				.assertion_time = 1,                                               \
+				.negation_time = 1,                                                \
+			},                                                                         \
+	};                                                                                         \
+	static uart_cfg_t g_uart##n##_cfg = {                                                      \
+		.channel = DT_PROP(SCI_NODE(n), channel),                                          \
+		.p_extend = &g_uart##n##_cfg_extend,                                               \
+		.p_transfer_tx = NULL,                                                             \
+		.p_transfer_rx = NULL,                                                             \
+		.rxi_ipl = DT_IRQ_BY_NAME(SCI_NODE(n), rxi, priority),                             \
+		.rxi_irq = DT_IRQ_BY_NAME(SCI_NODE(n), rxi, irq),                                  \
+		.txi_ipl = DT_IRQ_BY_NAME(SCI_NODE(n), txi, priority),                             \
+		.txi_irq = DT_IRQ_BY_NAME(SCI_NODE(n), txi, irq),                                  \
+		.tei_ipl = DT_IRQ_BY_NAME(SCI_NODE(n), tei, priority),                             \
+		.tei_irq = DT_IRQ_BY_NAME(SCI_NODE(n), tei, irq),                                  \
+		.eri_ipl = DT_IRQ_BY_NAME(SCI_NODE(n), eri, priority),                             \
+		.eri_irq = DT_IRQ_BY_NAME(SCI_NODE(n), eri, irq),                                  \
+		IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, (                                         \
+			 .p_callback = uart_rz_sci_event_handler,                                  \
+			 .p_context = (void *)DEVICE_DT_INST_GET(n),)) };                          \
+	PINCTRL_DT_DEFINE(SCI_NODE(n));                                                            \
+	static struct uart_rz_sci_config uart_rz_config_##n = {                                    \
+		.pin_config = PINCTRL_DT_DEV_CONFIG_GET(SCI_NODE(n)),                              \
+		.fsp_api = &g_uart_on_sci,                                                         \
+	};                                                                                         \
+	static sci_uart_instance_ctrl_t g_uart##n##_ctrl;                                          \
+	static struct uart_rz_sci_data uart_rz_sci_data_##n = {                                    \
+		.fsp_ctrl = &g_uart##n##_ctrl,                                                     \
+		.fsp_cfg = &g_uart##n##_cfg,                                                       \
+		.uart_config =                                                                     \
+			{                                                                          \
+				.baudrate = DT_INST_PROP_OR(n, current_speed, 115200),             \
+				.parity = DT_INST_ENUM_IDX_OR(n, parity, UART_CFG_PARITY_NONE),    \
+				.stop_bits =                                                       \
+					DT_INST_ENUM_IDX_OR(n, stop_bits, UART_CFG_STOP_BITS_1),   \
+				.data_bits =                                                       \
+					DT_INST_ENUM_IDX_OR(n, data_bits, UART_CFG_DATA_BITS_8),   \
+				.flow_ctrl = DT_INST_PROP_OR(n, hw_flow_control,                   \
+							     UART_CFG_FLOW_CTRL_NONE),             \
+			},                                                                         \
+	};                                                                                         \
+	static int uart_rz_init_##n(const struct device *dev)                                      \
+	{                                                                                          \
+		IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN,                  \
+			(UART_RZ_CONFIG_FUNC(n);))                        \
+		return uart_rz_init(dev);                                                          \
+	}                                                                                          \
+	DEVICE_DT_INST_DEFINE(n, &uart_rz_init_##n, NULL, &uart_rz_sci_data_##n,                   \
+			      &uart_rz_config_##n, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY,      \
+			      &uart_rz_sci_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(UART_RZ_INIT)
diff --git a/drivers/serial/uart_renesas_rz_scif.c b/drivers/serial/uart_renesas_rz_scif.c
index 6b63f694324..37506e3415c 100644
--- a/drivers/serial/uart_renesas_rz_scif.c
+++ b/drivers/serial/uart_renesas_rz_scif.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -8,6 +8,7 @@
 #include <zephyr/drivers/pinctrl.h>
 #include <zephyr/drivers/uart.h>
 #include <zephyr/logging/log.h>
+#include <zephyr/irq.h>
 #include "r_scif_uart.h"
 
 LOG_MODULE_REGISTER(rz_scif_uart);
@@ -17,12 +18,36 @@ struct uart_rz_scif_config {
 	const uart_api_t *fsp_api;
 };
 
+struct uart_rz_scif_int {
+	bool rxi_flag;
+	bool tei_flag;
+	bool rx_fifo_busy;
+	bool irq_rx_enable;
+	bool irq_tx_enable;
+	uint8_t rx_byte;
+	uint8_t tx_byte;
+	uart_event_t event;
+};
+
 struct uart_rz_scif_data {
 	struct uart_config uart_config;
 	uart_cfg_t *fsp_cfg;
+	struct uart_rz_scif_int int_data;
 	scif_uart_instance_ctrl_t *fsp_ctrl;
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	uart_irq_callback_user_data_t callback;
+	void *callback_data;
+#endif
 };
 
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+void scif_uart_rxi_isr(void *irq);
+void scif_uart_txi_isr(void *irq);
+void scif_uart_tei_isr(void *irq);
+void scif_uart_eri_isr(void *irq);
+void scif_uart_bri_isr(void *irq);
+#endif
+
 static int uart_rz_scif_poll_in(const struct device *dev, unsigned char *c)
 {
 	struct uart_rz_scif_data *data = dev->data;
@@ -41,6 +66,9 @@ static void uart_rz_scif_poll_out(const struct device *dev, unsigned char c)
 {
 	struct uart_rz_scif_data *data = dev->data;
 	R_SCIFA0_Type *reg = data->fsp_ctrl->p_reg;
+	uint8_t key;
+
+	key = irq_lock();
 
 	while (!reg->FSR_b.TDFE) {
 	}
@@ -49,28 +77,27 @@ static void uart_rz_scif_poll_out(const struct device *dev, unsigned char c)
 
 	while (!reg->FSR_b.TEND) {
 	}
+
+	irq_unlock(key);
 }
 
 static int uart_rz_scif_err_check(const struct device *dev)
 {
 	struct uart_rz_scif_data *data = dev->data;
-	R_SCIFA0_Type *reg = data->fsp_ctrl->p_reg;
+	uart_event_t event = data->int_data.event;
+	int err = 0;
 
-	const uint32_t fsr = reg->FSR;
-	const uint32_t lsr = reg->LSR;
-	int errors = 0;
-
-	if ((lsr & R_SCIFA0_LSR_ORER_Msk) != 0) {
-		errors |= UART_ERROR_OVERRUN;
+	if (event & UART_EVENT_ERR_OVERFLOW) {
+		err |= UART_ERROR_OVERRUN;
 	}
-	if ((fsr & R_SCIFA0_FSR_PER_Msk) != 0) {
-		errors |= UART_ERROR_PARITY;
+	if (event & UART_EVENT_ERR_FRAMING) {
+		err |= UART_ERROR_FRAMING;
 	}
-	if ((fsr & R_SCIFA0_FSR_FER_Pos) != 0) {
-		errors |= UART_ERROR_FRAMING;
+	if (event & UART_EVENT_ERR_PARITY) {
+		err |= UART_ERROR_PARITY;
 	}
 
-	return errors;
+	return err;
 }
 
 static int uart_rz_scif_apply_config(const struct device *dev)
@@ -79,10 +106,10 @@ static int uart_rz_scif_apply_config(const struct device *dev)
 
 	struct uart_config *uart_config = &data->uart_config;
 	uart_cfg_t *fsp_cfg = data->fsp_cfg;
+	data->fsp_ctrl->p_cfg = data->fsp_cfg;
 
 	scif_baud_setting_t baud_setting;
-	scif_uart_extended_cfg_t config_extend;
-	const scif_uart_extended_cfg_t *fsp_config_extend = fsp_cfg->p_extend;
+	scif_uart_extended_cfg_t *fsp_config_extend = (scif_uart_extended_cfg_t *)fsp_cfg->p_extend;
 
 	fsp_err_t fsp_err;
 
@@ -130,25 +157,21 @@ static int uart_rz_scif_apply_config(const struct device *dev)
 		return -ENOTSUP;
 	}
 
-	memcpy(&config_extend, fsp_config_extend->p_baud_setting, sizeof(scif_baud_setting_t));
-
 	switch (uart_config->flow_ctrl) {
 	case UART_CFG_FLOW_CTRL_NONE:
-		config_extend.flow_control = SCIF_UART_FLOW_CONTROL_NONE;
-		config_extend.uart_mode = SCIF_UART_MODE_RS232;
-		config_extend.rs485_setting.enable = SCI_UART_RS485_DISABLE;
+		fsp_config_extend->flow_control = SCIF_UART_FLOW_CONTROL_NONE;
+		fsp_config_extend->uart_mode = SCIF_UART_MODE_RS232;
+		fsp_config_extend->rs485_setting.enable = 0;
 		break;
 	case UART_CFG_FLOW_CTRL_RTS_CTS:
-		config_extend.flow_control = SCIF_UART_FLOW_CONTROL_AUTO;
-		config_extend.uart_mode = SCIF_UART_MODE_RS232;
-		config_extend.rs485_setting.enable = SCI_UART_RS485_DISABLE;
+		fsp_config_extend->flow_control = SCIF_UART_FLOW_CONTROL_AUTO;
+		fsp_config_extend->uart_mode = SCIF_UART_MODE_RS232;
+		fsp_config_extend->rs485_setting.enable = 0;
 		break;
 	default:
 		return -ENOTSUP;
 	}
 
-	memcpy(fsp_config_extend->p_baud_setting, &config_extend, sizeof(scif_baud_setting_t));
-
 	return 0;
 }
 
@@ -179,11 +202,6 @@ static int uart_rz_scif_configure(const struct device *dev, const struct uart_co
 		return -EIO;
 	}
 
-	R_SCIFA0_Type *reg = data->fsp_ctrl->p_reg;
-	/* Temporarily disable the DRI interrupt caused by receive data ready */
-	/* TODO: support interrupt-driven api */
-	reg->SCR_b.RIE = 0;
-
 	return err;
 }
 
@@ -197,6 +215,195 @@ static int uart_rz_scif_config_get(const struct device *dev, struct uart_config
 
 #endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
 
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+
+static int uart_rz_scif_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size)
+{
+	struct uart_rz_scif_data *data = dev->data;
+	scif_uart_instance_ctrl_t *fsp_ctrl = data->fsp_ctrl;
+
+	fsp_ctrl->tx_src_bytes = size;
+	fsp_ctrl->p_tx_src = tx_data;
+
+	scif_uart_txi_isr((void *)fsp_ctrl->p_cfg->txi_irq);
+
+	return (size - fsp_ctrl->tx_src_bytes);
+}
+
+static int uart_rz_scif_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
+{
+	struct uart_rz_scif_data *data = dev->data;
+
+	scif_uart_instance_ctrl_t *fsp_ctrl = data->fsp_ctrl;
+
+	fsp_ctrl->rx_dest_bytes = size;
+	fsp_ctrl->p_rx_dest = rx_data;
+
+	/* Read all available data in the FIFO */
+	/* If there are more available data than required, they will be lost */
+	if (data->int_data.rxi_flag) {
+		scif_uart_rxi_isr((void *)fsp_ctrl->p_cfg->rxi_irq);
+	} else {
+		scif_uart_tei_isr((void *)fsp_ctrl->p_cfg->tei_irq);
+	}
+
+	data->int_data.rx_fifo_busy = false;
+
+	return (size - fsp_ctrl->rx_dest_bytes);
+}
+
+static void uart_rz_scif_irq_rx_enable(const struct device *dev)
+{
+	const struct uart_rz_scif_config *config = dev->config;
+	struct uart_rz_scif_data *data = dev->data;
+
+	data->int_data.irq_rx_enable = true;
+
+	/* Prepare 1-byte buffer to receive, it will be overwritten by fifo read */
+	config->fsp_api->read(data->fsp_ctrl, &(data->int_data.rx_byte), 1);
+}
+
+static void uart_rz_scif_irq_rx_disable(const struct device *dev)
+{
+	struct uart_rz_scif_data *data = dev->data;
+
+	data->int_data.irq_rx_enable = false;
+	data->int_data.rx_fifo_busy = false;
+}
+
+static void uart_rz_scif_irq_tx_enable(const struct device *dev)
+{
+	struct uart_rz_scif_data *data = dev->data;
+	const struct uart_rz_scif_config *config = dev->config;
+
+	data->int_data.irq_tx_enable = true;
+
+	/* Trigger TX with a NULL frame */
+	/* It is expected not to be sent, and will be overwritten by the fifo fill */
+	data->int_data.tx_byte = '\0';
+	config->fsp_api->write(data->fsp_ctrl, &data->int_data.tx_byte, 1);
+}
+
+static void uart_rz_scif_irq_tx_disable(const struct device *dev)
+{
+	struct uart_rz_scif_data *data = dev->data;
+
+	data->int_data.irq_tx_enable = false;
+}
+
+static int uart_rz_scif_irq_tx_ready(const struct device *dev)
+{
+	struct uart_rz_scif_data *data = dev->data;
+
+	return data->int_data.irq_tx_enable;
+}
+
+static int uart_rz_scif_irq_rx_ready(const struct device *dev)
+{
+	struct uart_rz_scif_data *data = dev->data;
+
+	return data->int_data.rx_fifo_busy && data->int_data.irq_rx_enable;
+}
+
+static int uart_rz_scif_irq_is_pending(const struct device *dev)
+{
+	return (uart_rz_scif_irq_tx_ready(dev)) || (uart_rz_scif_irq_rx_ready(dev));
+}
+
+static void uart_rz_scif_irq_callback_set(const struct device *dev,
+					  uart_irq_callback_user_data_t cb, void *cb_data)
+{
+	struct uart_rz_scif_data *data = dev->data;
+
+	data->callback = cb;
+	data->callback_data = cb_data;
+}
+
+static int uart_rz_scif_irq_update(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+	return 1;
+}
+
+static void uart_rz_scif_rxi_isr(const struct device *dev)
+{
+	struct uart_rz_scif_data *data = dev->data;
+
+	data->int_data.rxi_flag = true;
+	data->int_data.rx_fifo_busy = true;
+	if (data->callback) {
+		data->callback(dev, data->callback_data);
+	}
+}
+
+static void uart_rz_scif_txi_isr(const struct device *dev)
+{
+	struct uart_rz_scif_data *data = dev->data;
+
+	data->int_data.tei_flag = false;
+	if (data->callback) {
+		data->callback(dev, data->callback_data);
+	}
+}
+
+static void uart_rz_scif_tei_isr(const struct device *dev)
+{
+	struct uart_rz_scif_data *data = dev->data;
+	scif_uart_instance_ctrl_t *fsp_ctrl = data->fsp_ctrl;
+
+	if (data->int_data.tei_flag) {
+		scif_uart_tei_isr((void *)fsp_ctrl->p_cfg->tei_irq);
+	} else {
+		data->int_data.rxi_flag = false;
+		data->int_data.rx_fifo_busy = true;
+		if (data->callback) {
+			data->callback(dev, data->callback_data);
+		}
+	}
+}
+
+static void uart_rz_scif_eri_isr(const struct device *dev)
+{
+	struct uart_rz_scif_data *data = dev->data;
+	scif_uart_instance_ctrl_t *fsp_ctrl = data->fsp_ctrl;
+
+	scif_uart_eri_isr((void *)fsp_ctrl->p_cfg->eri_irq);
+}
+
+static void uart_rz_scif_bri_isr(const struct device *dev)
+{
+	struct uart_rz_scif_data *data = dev->data;
+	uart_cfg_t *fsp_cfg = data->fsp_cfg;
+	scif_uart_extended_cfg_t *fsp_extend = (scif_uart_extended_cfg_t *)fsp_cfg->p_extend;
+
+	scif_uart_bri_isr((void *)fsp_extend->bri_irq);
+}
+
+static void uart_rz_scif_event_handler(uart_callback_args_t *p_args)
+{
+	const struct device *dev = (const struct device *)p_args->p_context;
+	struct uart_rz_scif_data *data = dev->data;
+
+	data->int_data.event = p_args->event;
+	switch (p_args->event) {
+	case UART_EVENT_RX_CHAR:
+		data->int_data.rx_byte = p_args->data;
+		break;
+	case UART_EVENT_RX_COMPLETE:
+		break;
+	case UART_EVENT_TX_DATA_EMPTY:
+		data->int_data.tei_flag = true;
+		break;
+	case UART_EVENT_TX_COMPLETE:
+		data->int_data.tei_flag = false;
+		break;
+	default:
+		break;
+	}
+}
+
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+
 static DEVICE_API(uart, uart_rz_scif_driver_api) = {
 	.poll_in = uart_rz_scif_poll_in,
 	.poll_out = uart_rz_scif_poll_out,
@@ -205,6 +412,19 @@ static DEVICE_API(uart, uart_rz_scif_driver_api) = {
 	.configure = uart_rz_scif_configure,
 	.config_get = uart_rz_scif_config_get,
 #endif
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	.fifo_fill = uart_rz_scif_fifo_fill,
+	.fifo_read = uart_rz_scif_fifo_read,
+	.irq_rx_enable = uart_rz_scif_irq_rx_enable,
+	.irq_rx_disable = uart_rz_scif_irq_rx_disable,
+	.irq_tx_enable = uart_rz_scif_irq_tx_enable,
+	.irq_tx_disable = uart_rz_scif_irq_tx_disable,
+	.irq_tx_ready = uart_rz_scif_irq_tx_ready,
+	.irq_rx_ready = uart_rz_scif_irq_rx_ready,
+	.irq_is_pending = uart_rz_scif_irq_is_pending,
+	.irq_callback_set = uart_rz_scif_irq_callback_set,
+	.irq_update = uart_rz_scif_irq_update,
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
 };
 
 static int uart_rz_scif_init(const struct device *dev)
@@ -227,15 +447,31 @@ static int uart_rz_scif_init(const struct device *dev)
 
 	config->fsp_api->open(data->fsp_ctrl, data->fsp_cfg);
 
-	R_SCIFA0_Type *reg = data->fsp_ctrl->p_reg;
-	/* Temporarily disable the DRI interrupt caused by receive data ready */
-	/* TODO: support interrupt-driven api */
-	reg->SCR_b.RIE = 0;
-
 	return 0;
 }
 
-#define UART_RZG_INIT(n)                                                                           \
+#ifdef CONFIG_CPU_CORTEX_M
+#define GET_IRQ_FLAGS(index) 0
+#else /* Cortex-A/R */
+#define GET_IRQ_FLAGS(index) DT_INST_IRQ_BY_IDX(index, 0, flags)
+#endif
+
+#define UART_RZ_IRQ_CONNECT(n, irq_name, isr)                                                      \
+	do {                                                                                       \
+		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, irq_name, irq),                                 \
+			    DT_INST_IRQ_BY_NAME(n, irq_name, priority), isr,                       \
+			    DEVICE_DT_INST_GET(n), GET_IRQ_FLAGS(n));                              \
+		irq_enable(DT_INST_IRQ_BY_NAME(n, irq_name, irq));                                 \
+	} while (0)
+
+#define UART_RZ_CONFIG_FUNC(n)                                                                     \
+	UART_RZ_IRQ_CONNECT(n, eri, uart_rz_scif_eri_isr);                                         \
+	UART_RZ_IRQ_CONNECT(n, rxi, uart_rz_scif_rxi_isr);                                         \
+	UART_RZ_IRQ_CONNECT(n, txi, uart_rz_scif_txi_isr);                                         \
+	UART_RZ_IRQ_CONNECT(n, tei, uart_rz_scif_tei_isr);                                         \
+	UART_RZ_IRQ_CONNECT(n, bri, uart_rz_scif_bri_isr);
+
+#define UART_RZ_INIT(n)                                                                            \
 	static scif_uart_instance_ctrl_t g_uart##n##_ctrl;                                         \
 	static scif_baud_setting_t g_uart##n##_baud_setting;                                       \
 	static scif_uart_extended_cfg_t g_uart##n##_cfg_extend = {                                 \
@@ -244,22 +480,20 @@ static int uart_rz_scif_init(const struct device *dev)
 		.clock = SCIF_UART_CLOCK_INT,                                                      \
 		.noise_cancel = SCIF_UART_NOISE_CANCELLATION_ENABLE,                               \
 		.p_baud_setting = &g_uart##n##_baud_setting,                                       \
-		.rx_fifo_trigger = SCIF_UART_RECEIVE_TRIGGER_MAX,                                  \
+		.rx_fifo_trigger = 3,                                                              \
 		.rts_fifo_trigger = SCIF_UART_RTS_TRIGGER_14,                                      \
 		.uart_mode = SCIF_UART_MODE_RS232,                                                 \
 		.flow_control = SCIF_UART_FLOW_CONTROL_NONE,                                       \
 		.rs485_setting =                                                                   \
 			{                                                                          \
-				.enable = (sci_uart_rs485_enable_t)NULL,                           \
-				.polarity = SCI_UART_RS485_DE_POLARITY_HIGH,                       \
+				.enable = 0,                                                       \
+				.polarity = 0,                                                     \
 				.de_control_pin =                                                  \
 					(bsp_io_port_pin_t)SCIF_UART_INVALID_16BIT_PARAM,          \
 			},                                                                         \
 	};                                                                                         \
 	static uart_cfg_t g_uart##n##_cfg = {                                                      \
 		.channel = DT_INST_PROP(n, channel),                                               \
-		.p_callback = NULL,                                                                \
-		.p_context = NULL,                                                                 \
 		.p_extend = &g_uart##n##_cfg_extend,                                               \
 		.p_transfer_tx = NULL,                                                             \
 		.p_transfer_rx = NULL,                                                             \
@@ -271,19 +505,21 @@ static int uart_rz_scif_init(const struct device *dev)
 		.txi_irq = DT_INST_IRQ_BY_NAME(n, txi, irq),                                       \
 		.tei_irq = DT_INST_IRQ_BY_NAME(n, tei, irq),                                       \
 		.eri_irq = DT_INST_IRQ_BY_NAME(n, eri, irq),                                       \
-	};                                                                                         \
+		IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN, (                                         \
+			 .p_callback = uart_rz_scif_event_handler,                                 \
+			 .p_context = (void *)DEVICE_DT_INST_GET(n),)) };                          \
 	PINCTRL_DT_INST_DEFINE(n);                                                                 \
 	static const struct uart_rz_scif_config uart_rz_scif_config_##n = {                        \
-		.pin_config = PINCTRL_DT_INST_DEV_CONFIG_GET(n), .fsp_api = &g_uart_on_scif};      \
+		.pin_config = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                   \
+		.fsp_api = &g_uart_on_scif,                                                        \
+	};                                                                                         \
 	static struct uart_rz_scif_data uart_rz_scif_data_##n = {                                  \
 		.uart_config =                                                                     \
 			{                                                                          \
-				.baudrate = DT_INST_PROP_OR(n, current_speed, 115200),             \
-				.parity = DT_INST_ENUM_IDX_OR(n, parity, UART_CFG_PARITY_NONE),    \
-				.stop_bits =                                                       \
-					DT_INST_ENUM_IDX_OR(n, stop_bits, UART_CFG_STOP_BITS_1),   \
-				.data_bits =                                                       \
-					DT_INST_ENUM_IDX_OR(n, data_bits, UART_CFG_DATA_BITS_8),   \
+				.baudrate = DT_INST_PROP(n, current_speed),                        \
+				.parity = DT_INST_ENUM_IDX(n, parity),                             \
+				.stop_bits = DT_INST_ENUM_IDX(n, stop_bits),                       \
+				.data_bits = DT_INST_ENUM_IDX(n, data_bits),                       \
 				.flow_ctrl = DT_INST_PROP_OR(n, hw_flow_control,                   \
 							     UART_CFG_FLOW_CTRL_NONE),             \
 			},                                                                         \
@@ -292,10 +528,12 @@ static int uart_rz_scif_init(const struct device *dev)
 	};                                                                                         \
 	static int uart_rz_scif_init_##n(const struct device *dev)                                 \
 	{                                                                                          \
+		IF_ENABLED(CONFIG_UART_INTERRUPT_DRIVEN,                    \
+			    (UART_RZ_CONFIG_FUNC(n);))                      \
 		return uart_rz_scif_init(dev);                                                     \
 	}                                                                                          \
 	DEVICE_DT_INST_DEFINE(n, &uart_rz_scif_init_##n, NULL, &uart_rz_scif_data_##n,             \
 			      &uart_rz_scif_config_##n, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
 			      &uart_rz_scif_driver_api);
 
-DT_INST_FOREACH_STATUS_OKAY(UART_RZG_INIT)
+DT_INST_FOREACH_STATUS_OKAY(UART_RZ_INIT)
diff --git a/drivers/serial/uart_renesas_rza2m_scif.c b/drivers/serial/uart_renesas_rza2m_scif.c
new file mode 100644
index 00000000000..c6b8068781e
--- /dev/null
+++ b/drivers/serial/uart_renesas_rza2m_scif.c
@@ -0,0 +1,786 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT renesas_rza2m_scif_uart
+
+#include <zephyr/drivers/uart.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/interrupt_controller/gic.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/irq.h>
+#include <zephyr/spinlock.h>
+
+LOG_MODULE_REGISTER(uart_renesas_rza2m_scif, CONFIG_UART_LOG_LEVEL);
+
+struct scif_reg {
+	uint8_t offset, size;
+};
+
+enum {
+	RZA2M_SMR,  /* Serial Mode Register */
+	RZA2M_BRR,  /* Bit Rate Register */
+	RZA2M_SCR,  /* Serial Control Register */
+	RZA2M_FSR,  /* Serial Status Register */
+	RZA2M_FCR,  /* FIFO Control Register */
+	RZA2M_FDR,  /* FIFO Data Count Register */
+	RZA2M_FTDR, /* Transmit (FIFO) Data Register */
+	RZA2M_FRDR, /* Receive (FIFO) Data Register */
+	RZA2M_LSR,  /* Line Status Register */
+	RZA2M_TFDR, /* Transmit FIFO Data Count Register */
+	RZA2M_RFDR, /* Receive FIFO Data Count Register */
+	RZA2M_SPTR, /* Serial Port Register */
+	RZA2M_SEMR, /* Serial extended mode register */
+	RZA2M_FTCR, /* FIFO Trigger Control Register */
+
+	RZA2M_SCIF_NR_REGS,
+};
+
+struct scif_params {
+	const struct scif_reg regs[RZA2M_SCIF_NR_REGS];
+	uint16_t init_lsr_mask;
+	uint16_t init_interrupt_mask;
+};
+
+struct uart_rza2m_scif_cfg {
+	DEVICE_MMIO_ROM; /* Must be first */
+	const struct device *clock_dev;
+	clock_control_subsys_t clock_subsys;
+	const struct pinctrl_dev_config *pcfg;
+	const struct scif_params *params;
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	void (*irq_config_func)(const struct device *dev);
+#endif
+};
+
+struct uart_rza2m_scif_int {
+	uint16_t rxi_status;
+	uint16_t line_status;
+};
+
+struct uart_rza2m_scif_data {
+	DEVICE_MMIO_RAM; /* Must be first */
+	struct uart_config current_config;
+	uint8_t channel;
+	uint32_t clk_rate;
+	struct k_spinlock lock;
+	struct uart_rza2m_scif_int int_data;
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	uart_irq_callback_user_data_t irq_cb;
+	void *irq_cb_data;
+#endif
+};
+
+#define RZA2M_SCIF_DEFAULT_SPEED     115200
+#define RZA2M_SCIF_DEFAULT_PARITY    UART_CFG_PARITY_NONE
+#define RZA2M_SCIF_DEFAULT_STOP_BITS UART_CFG_STOP_BITS_1
+#define RZA2M_SCIF_DEFAULT_DATA_BITS UART_CFG_DATA_BITS_8
+
+/* SMR (Serial Mode Register) */
+#define RZA2M_SMR_C_A       BIT(7)            /* Communication Mode */
+#define RZA2M_SMR_CHR       BIT(6)            /* 7-bit Character Length */
+#define RZA2M_SMR_PE        BIT(5)            /* Parity Enable */
+#define RZA2M_SMR_O_E       BIT(4)            /* Odd Parity */
+#define RZA2M_SMR_STOP      BIT(3)            /* Stop Bit Length */
+#define RZA2M_SMR_CKS_MASK  (BIT(0) | BIT(1)) /* Clock Select */
+#define RZA2M_SMR_CKS_SHIFT 0                 /* Clock Select shift */
+
+/* SCR (Serial Control Register) */
+#define RZA2M_SCR_TIE  BIT(7) /* Transmit Interrupt Enable */
+#define RZA2M_SCR_RIE  BIT(6) /* Receive Interrupt Enable */
+#define RZA2M_SCR_TE   BIT(5) /* Transmit Enable */
+#define RZA2M_SCR_RE   BIT(4) /* Receive Enable */
+#define RZA2M_SCR_REIE BIT(3) /* Receive Error Interrupt Enable */
+#define RZA2M_SCR_TEIE BIT(2) /* Transmit End Interrupt Enable */
+#define RZA2M_SCR_CKE1 BIT(1) /* Clock Enable 1 */
+#define RZA2M_SCR_CKE0 BIT(0) /* Clock Enable 0 */
+
+/* FCR (FIFO Control Register) */
+#define RZA2M_FCR_RTRG1 BIT(7) /* Receive FIFO Data Count Trigger 1 */
+#define RZA2M_FCR_RTRG0 BIT(6) /* Receive FIFO Data Count Trigger 0 */
+#define RZA2M_FCR_TTRG1 BIT(5) /* Transmit FIFO Data Count Trigger 1 */
+#define RZA2M_FCR_TTRG0 BIT(4) /* Transmit FIFO Data Count Trigger 0 */
+#define RZA2M_FCR_MCE   BIT(3) /* Modem Control Enable */
+#define RZA2M_FCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */
+#define RZA2M_FCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */
+#define RZA2M_FCR_LOOP  BIT(0) /* Loopback Test */
+
+/* FSR (Serial Status Register) */
+#define RZA2M_FSR_PER3 BIT(15) /* Parity Error Count 3 */
+#define RZA2M_FSR_PER2 BIT(14) /* Parity Error Count 2 */
+#define RZA2M_FSR_PER1 BIT(13) /* Parity Error Count 1 */
+#define RZA2M_FSR_PER0 BIT(12) /* Parity Error Count 0 */
+#define RZA2M_FSR_FER3 BIT(11) /* Framing Error Count 3 */
+#define RZA2M_FSR_FER2 BIT(10) /* Framing Error Count 2 */
+#define RZA2M_FSR_FER1 BIT(9)  /* Framing Error Count 1 */
+#define RZA2M_FSR_FER0 BIT(8)  /* Framing Error Count 0 */
+#define RZA2M_FSR_ER   BIT(7)  /* Receive Error */
+#define RZA2M_FSR_TEND BIT(6)  /* Transmission ended */
+#define RZA2M_FSR_TDFE BIT(5)  /* Transmit FIFO Data Empty */
+#define RZA2M_FSR_BRK  BIT(4)  /* Break Detect */
+#define RZA2M_FSR_FER  BIT(3)  /* Framing Error */
+#define RZA2M_FSR_PER  BIT(2)  /* Parity Error */
+#define RZA2M_FSR_RDF  BIT(1)  /* Receive FIFO Data Full */
+#define RZA2M_FSR_DR   BIT(0)  /* Receive Data Ready */
+
+/* SPTR (Serial Port Register) on SCIFA */
+#define RZA2M_SPTR_SPB2IO BIT(1) /* Serial Port Break Input/Output */
+#define RZA2M_SPTR_SPB2DT BIT(0) /* Serial Port Break Data Select */
+
+/* LSR (Line Status Register) on SCIFA */
+#define RZA2M_LSR_TO_SCIFA BIT(2) /* Timeout on SCIFA */
+#define RZA2M_LSR_ORER     BIT(0) /* Overrun Error */
+
+/* Serial Extended Mode Register */
+#define RZA2M_SEMR_ABCS0 BIT(0) /* Asynchronous Base Clock Select */
+#define RZA2M_SEMR_NFEN  BIT(2) /* Noise Cancellation Enable */
+#define RZA2M_SEMR_DIR   BIT(3) /* Data Transfer Direction Select */
+#define RZA2M_SEMR_MDDRS BIT(4) /* Modulation Duty Register Select */
+#define RZA2M_SEMR_BRME  BIT(5) /* Bit Rate Modulation Enable */
+/* Baud Rate Generator Double-Speed Mode Select */
+#define RZA2M_SEMR_BGDM  BIT(7)
+
+#define RZA2M_SCIF_DRV_ERR (-1)
+
+/* clang-format off */
+/* Registers */
+static const struct scif_params port_params = {
+	.regs = {
+			[RZA2M_SMR] = {0x00, 16},
+			[RZA2M_BRR] = {0x02, 8},
+			[RZA2M_SCR] = {0x04, 16},
+			[RZA2M_FTDR] = {0x06, 8},
+			[RZA2M_FSR] = {0x08, 16},
+			[RZA2M_FRDR] = {0x0A, 8},
+			[RZA2M_FCR] = {0x0C, 16},
+			[RZA2M_FDR] = {0x0E, 16},
+			[RZA2M_SPTR] = {0x10, 16},
+			[RZA2M_LSR] = {0x12, 16},
+			[RZA2M_SEMR] = {0x14, 8},
+			[RZA2M_FTCR] = {0x16, 16},
+		},
+	.init_lsr_mask = RZA2M_LSR_ORER,
+	.init_interrupt_mask =
+		RZA2M_SCR_TIE | RZA2M_SCR_RIE | RZA2M_SCR_REIE | RZA2M_SCR_TEIE,
+};
+/* clang-format on */
+
+#define RZA2M_NUM_DIVISORS_ASYNC (9)
+
+/* Baud divisor info */
+/**
+ * When ABCS = 0 & BGDM = 0, divisor = 64 x 2^(2n - 1)
+ * When ABCS = 1 & BGDM = 0 OR ABCS = 0 & BGDM = 1, divisor = 32 x 2^(2n - 1)
+ * When ABCS = 1 & BGDM = 1, divisor = 16 x 2^(2n - 1)
+ */
+
+typedef struct {
+	int16_t divisor; /* Clock divisor */
+	uint8_t abcs;    /* ABCS value to get divisor */
+	uint8_t bgdm;    /* BGDM value to get divisor */
+	uint8_t cks;     /* CKS value to get divisor (CKS = n) */
+} st_baud_divisorb_t;
+
+/* Divisor result, ABCS, BGDM, n */
+static const st_baud_divisorb_t gs_scifa_async_baud[RZA2M_NUM_DIVISORS_ASYNC] = {
+	{8, 1, 1, 0},   {16, 0, 1, 0},  {32, 0, 0, 0},   {64, 0, 1, 1},  {128, 0, 0, 1},
+	{256, 0, 1, 2}, {512, 0, 0, 2}, {1024, 0, 1, 3}, {2048, 0, 0, 3}};
+
+static uint8_t uart_rza2m_scif_read_8(const struct device *dev, uint32_t offs)
+{
+	const struct uart_rza2m_scif_cfg *config = dev->config;
+	uint32_t offset = config->params->regs[offs].offset;
+
+	return sys_read8(DEVICE_MMIO_GET(dev) + offset);
+}
+
+static void uart_rza2m_scif_write_8(const struct device *dev, uint32_t offs, uint8_t value)
+{
+	const struct uart_rza2m_scif_cfg *config = dev->config;
+	uint32_t offset = config->params->regs[offs].offset;
+
+	sys_write8(value, DEVICE_MMIO_GET(dev) + offset);
+}
+
+static uint16_t uart_rza2m_scif_read_16(const struct device *dev, uint32_t offs)
+{
+	const struct uart_rza2m_scif_cfg *config = dev->config;
+	uint32_t offset = config->params->regs[offs].offset;
+
+	return sys_read16(DEVICE_MMIO_GET(dev) + offset);
+}
+
+static void uart_rza2m_scif_write_16(const struct device *dev, uint32_t offs, uint16_t value)
+{
+	const struct uart_rza2m_scif_cfg *config = dev->config;
+	uint32_t offset = config->params->regs[offs].offset;
+
+	sys_write16(value, DEVICE_MMIO_GET(dev) + offset);
+}
+
+static uint8_t find_divisor_index(uint8_t channel, uint32_t desired_baud_rate, uint32_t clock_freq)
+{
+	/* Find the divisor; table has associated ABCS, BGDM and CKS values */
+	/* BRR must be 255 or less */
+	/* BRR = (PCLK / (divisor * desired_baud)) - 1 */
+	/* BRR = (ratio / divisor) - 1 */
+
+	uint32_t ratio = clock_freq / desired_baud_rate;
+	uint8_t divisor_index = 0;
+
+	if (channel == 0) {
+		/* The hardware manual states that for channel 0, P1f/16 input is not provided */
+		/* So the setting CKS [1:0] 1 0 cannot be used */
+		/* This restriction may be lifted in future releases */
+
+		while ((divisor_index < RZA2M_NUM_DIVISORS_ASYNC) &&
+		       ((ratio >= (uint32_t)(gs_scifa_async_baud[divisor_index].divisor * 256)) ||
+			(2 == gs_scifa_async_baud[divisor_index].cks))) {
+			divisor_index++;
+		}
+	} else {
+		/* Cast to uint32_t for comparison with ratio */
+		while ((divisor_index < RZA2M_NUM_DIVISORS_ASYNC) &&
+		       (ratio >= (uint32_t)(gs_scifa_async_baud[divisor_index].divisor * 256))) {
+			divisor_index++;
+		}
+	}
+
+	return divisor_index;
+}
+
+static int uart_rza2m_scif_set_baudrate(const struct device *dev, uint8_t channel,
+					uint32_t baud_rate)
+{
+	struct uart_rza2m_scif_data *data = dev->data;
+	uint16_t reg_16;
+	uint8_t reg_8;
+	uint32_t clk_freq = data->clk_rate;
+	uint8_t divisor_index;
+	uint32_t divisor;
+	uint32_t brr;
+
+	divisor_index = find_divisor_index(channel, baud_rate, clk_freq);
+	divisor = (uint32_t)gs_scifa_async_baud[divisor_index].divisor;
+
+	brr = clk_freq / (divisor * baud_rate);
+
+	if (brr == 0) {
+		return RZA2M_SCIF_DRV_ERR; /* Illegal value; return error */
+	}
+
+	/* Divide by half the divisor */
+	brr = clk_freq / ((divisor * baud_rate) / 2);
+
+	/* Formula: BRR = (PCLK / (divisor * desired_baud)) - 1 */
+	/* If (BRR * 2) is odd, "round up" by ignoring -1; divide by 2 again for rest of divisor */
+	brr = ((brr & 0x01) ? (brr / 2) : ((brr / 2) - 1));
+
+	/* Write BRR */
+	uart_rza2m_scif_write_8(dev, RZA2M_BRR, brr);
+
+	/* Write CKS[1:0] */
+	reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_SMR);
+	reg_16 &= ~(RZA2M_SMR_CKS_MASK << RZA2M_SMR_CKS_SHIFT);
+	reg_16 |= (gs_scifa_async_baud[divisor_index].cks & RZA2M_SMR_CKS_MASK)
+		  << RZA2M_SMR_CKS_SHIFT;
+	uart_rza2m_scif_write_16(dev, RZA2M_SMR, reg_16);
+
+	/* Write ABCS0 and BGDM */
+	reg_8 = uart_rza2m_scif_read_8(dev, RZA2M_SEMR);
+	reg_8 = reg_8 | (gs_scifa_async_baud[divisor_index].abcs ? RZA2M_SEMR_ABCS0 : 0);
+	reg_8 = reg_8 | (gs_scifa_async_baud[divisor_index].bgdm ? RZA2M_SEMR_BGDM : 0);
+	uart_rza2m_scif_write_8(dev, RZA2M_SEMR, reg_8);
+
+	return 0;
+}
+
+static int uart_rza2m_scif_poll_in(const struct device *dev, unsigned char *p_char)
+{
+	struct uart_rza2m_scif_data *data = dev->data;
+	uint16_t reg_16;
+	int ret = 0;
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	/* Receive FIFO empty */
+	if (!(uart_rza2m_scif_read_16(dev, RZA2M_FSR) & RZA2M_FSR_RDF)) {
+		ret = -1;
+		goto unlock;
+	}
+
+	*p_char = uart_rza2m_scif_read_8(dev, RZA2M_FRDR);
+
+	reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_FSR);
+	reg_16 &= ~RZA2M_FSR_RDF;
+	uart_rza2m_scif_write_16(dev, RZA2M_FSR, reg_16);
+
+unlock:
+	k_spin_unlock(&data->lock, key);
+
+	return ret;
+}
+
+static void uart_rza2m_scif_poll_out(const struct device *dev, unsigned char out_char)
+{
+	struct uart_rza2m_scif_data *data = dev->data;
+
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	/* Wait for empty space in transmit FIFO */
+	while (!(uart_rza2m_scif_read_16(dev, RZA2M_FSR) & RZA2M_FSR_TDFE)) {
+	}
+
+	uart_rza2m_scif_write_8(dev, RZA2M_FTDR, out_char);
+
+	while (!(uart_rza2m_scif_read_16(dev, RZA2M_FSR) & RZA2M_FSR_TEND)) {
+	}
+
+	k_spin_unlock(&data->lock, key);
+}
+
+static int uart_rza2m_scif_err_check(const struct device *dev)
+{
+	struct uart_rza2m_scif_data *data = dev->data;
+	struct uart_rza2m_scif_int int_data = data->int_data;
+	int err = 0;
+
+	if (int_data.line_status & RZA2M_LSR_ORER) {
+		err |= UART_ERROR_OVERRUN;
+	}
+	if (int_data.rxi_status & RZA2M_FSR_FER) {
+		err |= UART_ERROR_FRAMING;
+	}
+	if (int_data.rxi_status & RZA2M_FSR_PER) {
+		err |= UART_ERROR_PARITY;
+	}
+	if (int_data.rxi_status & RZA2M_FSR_BRK) {
+		err |= UART_BREAK;
+	}
+
+	return err;
+}
+
+static int uart_rza2m_scif_configure(const struct device *dev, const struct uart_config *cfg)
+{
+	const struct uart_rza2m_scif_cfg *config = dev->config;
+	struct uart_rza2m_scif_data *data = dev->data;
+	uint16_t reg_16;
+	k_spinlock_key_t key;
+	int err;
+
+	err = 0;
+
+	if (cfg->data_bits < UART_CFG_DATA_BITS_7 || cfg->data_bits > UART_CFG_DATA_BITS_8 ||
+	    cfg->stop_bits == UART_CFG_STOP_BITS_0_5 || cfg->stop_bits == UART_CFG_STOP_BITS_1_5 ||
+	    cfg->flow_ctrl != UART_CFG_FLOW_CTRL_NONE) {
+		return -ENOTSUP;
+	}
+
+	key = k_spin_lock(&data->lock);
+
+	/* Set the TXD output high */
+	reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_SPTR);
+	reg_16 |= (RZA2M_SPTR_SPB2DT | RZA2M_SPTR_SPB2IO);
+	uart_rza2m_scif_write_16(dev, RZA2M_SPTR, reg_16);
+
+	/* Disable Transmit and Receive */
+	reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_SCR);
+	reg_16 &= ~(RZA2M_SCR_TE | RZA2M_SCR_RE | RZA2M_SCR_TIE | RZA2M_SCR_RIE);
+	reg_16 &= ~(RZA2M_SCR_TEIE);
+	uart_rza2m_scif_write_16(dev, RZA2M_SCR, reg_16);
+
+	/* Emptying Transmit and Receive FIFO */
+	reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_FCR);
+	reg_16 |= (RZA2M_FCR_TFRST | RZA2M_FCR_RFRST);
+	uart_rza2m_scif_write_16(dev, RZA2M_FCR, reg_16);
+
+	/* Resetting Errors Registers */
+	reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_FSR);
+	reg_16 &= ~(RZA2M_FSR_ER | RZA2M_FSR_DR | RZA2M_FSR_BRK | RZA2M_FSR_RDF);
+	uart_rza2m_scif_write_16(dev, RZA2M_FSR, reg_16);
+
+	reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_LSR);
+	reg_16 &= ~(config->params->init_lsr_mask);
+	uart_rza2m_scif_write_16(dev, RZA2M_LSR, reg_16);
+
+	/* Select internal clock */
+	reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_SCR);
+	reg_16 &= ~(RZA2M_SCR_CKE1 | RZA2M_SCR_CKE0);
+	uart_rza2m_scif_write_16(dev, RZA2M_SCR, reg_16);
+
+	/* Serial Configuration (8N1) & Clock divider selection */
+	reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_SMR);
+	reg_16 &= ~(RZA2M_SMR_C_A | RZA2M_SMR_CHR | RZA2M_SMR_PE | RZA2M_SMR_O_E | RZA2M_SMR_STOP);
+	switch (cfg->parity) {
+	case UART_CFG_PARITY_NONE:
+		break;
+	case UART_CFG_PARITY_ODD:
+		reg_16 |= RZA2M_SMR_PE | RZA2M_SMR_O_E;
+		break;
+	case UART_CFG_PARITY_EVEN:
+		reg_16 |= RZA2M_SMR_PE;
+		break;
+	default:
+		return -ENOTSUP;
+	}
+	if (cfg->stop_bits == UART_CFG_STOP_BITS_2) {
+		reg_16 |= RZA2M_SMR_STOP;
+	}
+	if (cfg->data_bits == UART_CFG_DATA_BITS_7) {
+		reg_16 |= RZA2M_SMR_CHR;
+	}
+	uart_rza2m_scif_write_16(dev, RZA2M_SMR, reg_16);
+
+	/* Set baudrate */
+	err = uart_rza2m_scif_set_baudrate(dev, data->channel, cfg->baudrate);
+	if (err) {
+		return -EIO;
+	}
+
+	/* FIFOs data count trigger configuration */
+	reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_FCR);
+	reg_16 &= ~(RZA2M_FCR_RTRG1 | RZA2M_FCR_RTRG0 | RZA2M_FCR_TTRG1 | RZA2M_FCR_TTRG0 |
+		    RZA2M_FCR_MCE | RZA2M_FCR_TFRST | RZA2M_FCR_RFRST);
+	uart_rza2m_scif_write_16(dev, RZA2M_FCR, reg_16);
+
+	/* Enable Transmit & Receive + disable Interrupts */
+	reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_SCR);
+	reg_16 |= (RZA2M_SCR_TE | RZA2M_SCR_RE);
+	reg_16 &= ~(config->params->init_interrupt_mask);
+	uart_rza2m_scif_write_16(dev, RZA2M_SCR, reg_16);
+
+	data->current_config = *cfg;
+
+	k_spin_unlock(&data->lock, key);
+
+	return err;
+}
+
+#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
+static int uart_rza2m_scif_config_get(const struct device *dev, struct uart_config *cfg)
+{
+	struct uart_rza2m_scif_data *data = dev->data;
+
+	*cfg = data->current_config;
+
+	return 0;
+}
+#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
+
+static int uart_rza2m_scif_init(const struct device *dev)
+{
+	const struct uart_rza2m_scif_cfg *config = dev->config;
+	struct uart_rza2m_scif_data *data = dev->data;
+	int ret;
+
+	/* Configure dt provided device signals when available */
+	ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (!device_is_ready(config->clock_dev)) {
+		return -ENODEV;
+	}
+
+	ret = clock_control_on(config->clock_dev, (clock_control_subsys_t)config->clock_subsys);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = clock_control_get_rate(config->clock_dev,
+				     (clock_control_subsys_t)config->clock_subsys, &data->clk_rate);
+	if (ret < 0) {
+		return ret;
+	}
+
+	DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
+
+	ret = uart_rza2m_scif_configure(dev, &data->current_config);
+	if (ret != 0) {
+		return ret;
+	}
+
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	config->irq_config_func(dev);
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+
+static bool uart_rza2m_scif_irq_is_enabled(const struct device *dev, uint32_t irq)
+{
+	return !!(uart_rza2m_scif_read_16(dev, RZA2M_SCR) & irq);
+}
+
+static int uart_rza2m_scif_fifo_fill(const struct device *dev, const uint8_t *tx_data, int len)
+{
+	struct uart_rza2m_scif_data *data = dev->data;
+	int num_tx = 0;
+	uint16_t reg_16;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	while (((len - num_tx) > 0) && (uart_rza2m_scif_read_16(dev, RZA2M_FSR) & RZA2M_FSR_TDFE)) {
+		/* Send current byte */
+		uart_rza2m_scif_write_8(dev, RZA2M_FTDR, tx_data[num_tx]);
+
+		reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_FSR);
+		reg_16 &= ~(RZA2M_FSR_TDFE | RZA2M_FSR_TEND);
+		uart_rza2m_scif_write_16(dev, RZA2M_FSR, reg_16);
+
+		num_tx++;
+	}
+
+	k_spin_unlock(&data->lock, key);
+
+	return num_tx;
+}
+
+static int uart_rza2m_scif_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
+{
+	struct uart_rza2m_scif_data *data = dev->data;
+	int num_rx = 0;
+	uint16_t reg_16;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	while (((size - num_rx) > 0) && (uart_rza2m_scif_read_16(dev, RZA2M_FSR) & RZA2M_FSR_RDF)) {
+		/* Receive current byte */
+		rx_data[num_rx++] = uart_rza2m_scif_read_8(dev, RZA2M_FRDR);
+
+		reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_FSR);
+		reg_16 &= ~(RZA2M_FSR_RDF);
+		uart_rza2m_scif_write_16(dev, RZA2M_FSR, reg_16);
+	}
+
+	k_spin_unlock(&data->lock, key);
+
+	return num_rx;
+}
+
+static void uart_rza2m_scif_irq_tx_enable(const struct device *dev)
+{
+	struct uart_rza2m_scif_data *data = dev->data;
+
+	uint16_t reg_16;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_SCR);
+	reg_16 |= (RZA2M_SCR_TIE);
+	uart_rza2m_scif_write_16(dev, RZA2M_SCR, reg_16);
+
+	k_spin_unlock(&data->lock, key);
+}
+
+static void uart_rza2m_scif_irq_tx_disable(const struct device *dev)
+{
+	struct uart_rza2m_scif_data *data = dev->data;
+
+	uint16_t reg_16;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_SCR);
+	reg_16 &= ~(RZA2M_SCR_TIE);
+	uart_rza2m_scif_write_16(dev, RZA2M_SCR, reg_16);
+
+	k_spin_unlock(&data->lock, key);
+}
+
+static int uart_rza2m_scif_irq_tx_ready(const struct device *dev)
+{
+	return !!(uart_rza2m_scif_read_16(dev, RZA2M_FSR) & RZA2M_FSR_TDFE);
+}
+
+static void uart_rza2m_scif_irq_rx_enable(const struct device *dev)
+{
+	struct uart_rza2m_scif_data *data = dev->data;
+
+	uint16_t reg_16;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_SCR);
+	reg_16 |= (RZA2M_SCR_RIE);
+	uart_rza2m_scif_write_16(dev, RZA2M_SCR, reg_16);
+
+	k_spin_unlock(&data->lock, key);
+}
+
+static void uart_rza2m_scif_irq_rx_disable(const struct device *dev)
+{
+	struct uart_rza2m_scif_data *data = dev->data;
+
+	uint16_t reg_16;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_SCR);
+	reg_16 &= ~(RZA2M_SCR_RIE);
+	uart_rza2m_scif_write_16(dev, RZA2M_SCR, reg_16);
+
+	k_spin_unlock(&data->lock, key);
+}
+
+static int uart_rza2m_scif_irq_rx_ready(const struct device *dev)
+{
+	return !!(uart_rza2m_scif_read_16(dev, RZA2M_FSR) & RZA2M_FSR_RDF);
+}
+
+static void uart_rza2m_scif_irq_err_enable(const struct device *dev)
+{
+	struct uart_rza2m_scif_data *data = dev->data;
+
+	uint16_t reg_16;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_SCR);
+	reg_16 |= (RZA2M_SCR_REIE);
+	uart_rza2m_scif_write_16(dev, RZA2M_SCR, reg_16);
+
+	k_spin_unlock(&data->lock, key);
+}
+
+static void uart_rza2m_scif_irq_err_disable(const struct device *dev)
+{
+	struct uart_rza2m_scif_data *data = dev->data;
+
+	uint16_t reg_16;
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
+
+	reg_16 = uart_rza2m_scif_read_16(dev, RZA2M_SCR);
+	reg_16 &= ~(RZA2M_SCR_REIE);
+	uart_rza2m_scif_write_16(dev, RZA2M_SCR, reg_16);
+
+	k_spin_unlock(&data->lock, key);
+}
+
+static int uart_rza2m_scif_irq_is_pending(const struct device *dev)
+{
+	return (uart_rza2m_scif_irq_rx_ready(dev) &&
+		uart_rza2m_scif_irq_is_enabled(dev, RZA2M_SCR_RIE)) ||
+	       (uart_rza2m_scif_irq_tx_ready(dev) &&
+		uart_rza2m_scif_irq_is_enabled(dev, RZA2M_SCR_TIE));
+}
+
+static int uart_rza2m_scif_irq_update(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return 1;
+}
+
+static void uart_rza2m_scif_irq_callback_set(const struct device *dev,
+					     uart_irq_callback_user_data_t cb, void *cb_data)
+{
+	struct uart_rza2m_scif_data *data = dev->data;
+
+	data->irq_cb = cb;
+	data->irq_cb_data = cb_data;
+}
+
+void uart_rza2m_scif_isr(const struct device *dev)
+{
+	struct uart_rza2m_scif_data *data = dev->data;
+
+	if (data->irq_cb) {
+		data->irq_cb(dev, data->irq_cb_data);
+	}
+
+	/* Get interrupt status */
+	data->int_data.rxi_status = uart_rza2m_scif_read_16(dev, RZA2M_FSR);
+	data->int_data.rxi_status &= (RZA2M_FSR_FER | RZA2M_FSR_PER | RZA2M_FSR_BRK);
+	data->int_data.line_status = uart_rza2m_scif_read_16(dev, RZA2M_LSR);
+	data->int_data.line_status &= RZA2M_LSR_ORER;
+}
+
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+
+static DEVICE_API(uart, uart_rza2m_scif_driver_api) = {
+	.poll_in = uart_rza2m_scif_poll_in,
+	.poll_out = uart_rza2m_scif_poll_out,
+	.err_check = uart_rza2m_scif_err_check,
+#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
+	.configure = uart_rza2m_scif_configure,
+	.config_get = uart_rza2m_scif_config_get,
+#endif
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	.fifo_fill = uart_rza2m_scif_fifo_fill,
+	.fifo_read = uart_rza2m_scif_fifo_read,
+	.irq_tx_enable = uart_rza2m_scif_irq_tx_enable,
+	.irq_tx_disable = uart_rza2m_scif_irq_tx_disable,
+	.irq_tx_ready = uart_rza2m_scif_irq_tx_ready,
+	.irq_rx_enable = uart_rza2m_scif_irq_rx_enable,
+	.irq_rx_disable = uart_rza2m_scif_irq_rx_disable,
+	.irq_rx_ready = uart_rza2m_scif_irq_rx_ready,
+	.irq_err_enable = uart_rza2m_scif_irq_err_enable,
+	.irq_err_disable = uart_rza2m_scif_irq_err_disable,
+	.irq_is_pending = uart_rza2m_scif_irq_is_pending,
+	.irq_update = uart_rza2m_scif_irq_update,
+	.irq_callback_set = uart_rza2m_scif_irq_callback_set,
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+};
+
+/* Device Instantiation */
+#define UART_RZA2M_DECLARE_CFG(n, IRQ_FUNC_INIT)                                                   \
+	PINCTRL_DT_INST_DEFINE(n);                                                                 \
+	uint32_t clock_subsys##n = DT_INST_CLOCKS_CELL(n, clk_id);                                 \
+	static const struct uart_rza2m_scif_cfg uart_rza2m_scif_cfg_##n = {                        \
+		DEVICE_MMIO_ROM_INIT(DT_DRV_INST(n)),                                              \
+		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),                                \
+		.clock_subsys = (clock_control_subsys_t)(&clock_subsys##n),                        \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                         \
+		.params = &port_params,                                                            \
+		IRQ_FUNC_INIT}
+
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+#define UART_RZA2M_SET_IRQ(n, name)                                                                \
+	IRQ_CONNECT(DT_INST_IRQ_BY_NAME(n, name, irq) - GIC_SPI_INT_BASE,                          \
+		    DT_INST_IRQ_BY_NAME(n, name, priority), uart_rza2m_scif_isr,                   \
+		    DEVICE_DT_INST_GET(n), 0);                                                     \
+                                                                                                   \
+	irq_enable(DT_INST_IRQ_BY_NAME(n, name, irq) - GIC_SPI_INT_BASE);
+
+#define UART_RZA2M_IRQ_CONFIG_FUNC(n)                                                              \
+	static void irq_config_func_##n(const struct device *dev)                                  \
+	{                                                                                          \
+		UART_RZA2M_SET_IRQ(n, eri);                                                        \
+		UART_RZA2M_SET_IRQ(n, rxi);                                                        \
+		UART_RZA2M_SET_IRQ(n, txi);                                                        \
+		UART_RZA2M_SET_IRQ(n, tei);                                                        \
+	}
+#define UART_RZA2M_IRQ_CFG_FUNC_INIT(n) .irq_config_func = irq_config_func_##n
+#define UART_RZA2M_INIT_CFG(n)          UART_RZA2M_DECLARE_CFG(n, UART_RZA2M_IRQ_CFG_FUNC_INIT(n))
+#else
+#define UART_RZA2M_IRQ_CONFIG_FUNC(n)
+#define UART_RZA2M_IRQ_CFG_FUNC_INIT
+#define UART_RZA2M_INIT_CFG(n) UART_RZA2M_DECLARE_CFG(n, UART_RZA2M_IRQ_CFG_FUNC_INIT)
+#endif
+
+#define UART_RZA2M_INIT(n)                                                                         \
+	static struct uart_rza2m_scif_data uart_rza2m_scif_data_##n = {                            \
+		.current_config =                                                                  \
+			{                                                                          \
+				.baudrate = DT_INST_PROP_OR(n, current_speed,                      \
+							    RZA2M_SCIF_DEFAULT_SPEED),             \
+				.parity =                                                          \
+					DT_INST_ENUM_IDX_OR(n, parity, RZA2M_SCIF_DEFAULT_PARITY), \
+				.stop_bits = DT_INST_ENUM_IDX_OR(n, stop_bits,                     \
+								 RZA2M_SCIF_DEFAULT_STOP_BITS),    \
+				.data_bits = DT_INST_ENUM_IDX_OR(n, data_bits,                     \
+								 RZA2M_SCIF_DEFAULT_DATA_BITS),    \
+				.flow_ctrl = UART_CFG_FLOW_CTRL_NONE,                              \
+			},                                                                         \
+		.channel = DT_INST_PROP(n, channel),                                               \
+	};                                                                                         \
+	static const struct uart_rza2m_scif_cfg uart_rza2m_scif_cfg_##n;                           \
+	DEVICE_DT_INST_DEFINE(n, uart_rza2m_scif_init, NULL, &uart_rza2m_scif_data_##n,            \
+			      &uart_rza2m_scif_cfg_##n, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
+			      &uart_rza2m_scif_driver_api);                                        \
+                                                                                                   \
+	UART_RZA2M_IRQ_CONFIG_FUNC(n)                                                              \
+	UART_RZA2M_INIT_CFG(n);
+
+DT_INST_FOREACH_STATUS_OKAY(UART_RZA2M_INIT)
diff --git a/drivers/serial/uart_rpi_pico_pio.c b/drivers/serial/uart_rpi_pico_pio.c
index cfbd084c86b..7e221d4ad0a 100644
--- a/drivers/serial/uart_rpi_pico_pio.c
+++ b/drivers/serial/uart_rpi_pico_pio.c
@@ -39,15 +39,15 @@ RPI_PICO_PIO_DEFINE_PROGRAM(uart_tx, 0, 3,
 		/* .wrap */
 );
 
-RPI_PICO_PIO_DEFINE_PROGRAM(uart_rx, 0, 8,
+RPI_PICO_PIO_DEFINE_PROGRAM(uart_rx, 1, 8,
+	0x20a0, /*  0: wait   1 pin, 0                    */
 		/*  .wrap_target */
-	0x2020, /*  0: wait   0 pin, 0                    */
-	0xea27, /*  1: set    x, 7                   [10] */
-	0x4001, /*  2: in     pins, 1                     */
-	0x0642, /*  3: jmp    x--, 2                 [6]  */
-	0x00c8, /*  4: jmp    pin, 8                      */
-	0xc014, /*  5: irq    nowait 4 rel                */
-	0x20a0, /*  6: wait   1 pin, 0                    */
+	0x2020, /*  1: wait   0 pin, 0                    */
+	0xea27, /*  2: set    x, 7                   [10] */
+	0x4001, /*  3: in     pins, 1                     */
+	0x0643, /*  4: jmp    x--, 3                 [6]  */
+	0x00c8, /*  5: jmp    pin, 8                      */
+	0xc014, /*  6: irq    nowait 4 rel                */
 	0x0000, /*  7: jmp    0                           */
 	0x8020, /*  8: push   block                       */
 		/*  .wrap */
diff --git a/drivers/serial/uart_rzt2m.c b/drivers/serial/uart_rzt2m.c
index 83b929619ea..e42f3e7e743 100644
--- a/drivers/serial/uart_rzt2m.c
+++ b/drivers/serial/uart_rzt2m.c
@@ -427,11 +427,9 @@ static void uart_rzt2m_isr(const struct device *dev)
 		.uart_cfg =                                                                        \
 			{                                                                          \
 				.baudrate = DT_INST_ENUM_IDX(n, current_speed),                    \
-				.parity = DT_INST_ENUM_IDX_OR(n, parity, UART_CFG_PARITY_NONE),    \
-				.stop_bits =                                                       \
-					DT_INST_ENUM_IDX_OR(n, stop_bits, UART_CFG_STOP_BITS_1),   \
-				.data_bits =                                                       \
-					DT_INST_ENUM_IDX_OR(n, data_bits, UART_CFG_DATA_BITS_8),   \
+				.parity = DT_INST_ENUM_IDX(n, parity),                             \
+				.stop_bits = DT_INST_ENUM_IDX(n, stop_bits),                       \
+				.data_bits = DT_INST_ENUM_IDX(n, data_bits),                       \
 			},                                                                         \
 	};                                                                                         \
 	UART_RZT2M_CONFIG_FUNC(n);                                                                 \
diff --git a/drivers/serial/uart_sam0.c b/drivers/serial/uart_sam0.c
index 10e222f12c6..407e2ebe7b6 100644
--- a/drivers/serial/uart_sam0.c
+++ b/drivers/serial/uart_sam0.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2017 Google LLC.
+ * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,6 +18,8 @@
 #include <string.h>
 #include <zephyr/irq.h>
 
+/* clang-format off */
+
 #ifndef SERCOM_USART_CTRLA_MODE_USART_INT_CLK
 #define SERCOM_USART_CTRLA_MODE_USART_INT_CLK SERCOM_USART_CTRLA_MODE(0x1)
 #endif
@@ -35,14 +38,11 @@ struct uart_sam0_dev_cfg {
 	uint32_t baudrate;
 	uint32_t pads;
 	bool     collision_detect;
-#ifdef MCLK
 	volatile uint32_t *mclk;
 	uint32_t mclk_mask;
-	uint16_t gclk_core_id;
-#else
-	uint32_t pm_apbcmask;
-	uint16_t gclk_clkctrl_id;
-#endif
+	uint32_t gclk_gen;
+	uint16_t gclk_id;
+
 #if CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_SAM0_ASYNC
 	void (*irq_config_func)(const struct device *dev);
 #endif
@@ -510,20 +510,15 @@ static int uart_sam0_init(const struct device *dev)
 
 	SercomUsart * const usart = cfg->regs;
 
-#ifdef MCLK
-	/* Enable the GCLK */
-	GCLK->PCHCTRL[cfg->gclk_core_id].reg = GCLK_PCHCTRL_GEN_GCLK0 |
-					       GCLK_PCHCTRL_CHEN;
-
-	/* Enable SERCOM clock in MCLK */
 	*cfg->mclk |= cfg->mclk_mask;
-#else
-	/* Enable the GCLK */
-	GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 |
-			    GCLK_CLKCTRL_CLKEN;
 
-	/* Enable SERCOM clock in PM */
-	PM->APBCMASK.reg |= cfg->pm_apbcmask;
+#ifdef MCLK
+	GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_CHEN
+					| GCLK_PCHCTRL_GEN(cfg->gclk_gen);
+#else
+	GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
+			  | GCLK_CLKCTRL_GEN(cfg->gclk_gen)
+			  | GCLK_CLKCTRL_ID(cfg->gclk_id);
 #endif
 
 	/* Disable all USART interrupts */
@@ -1272,34 +1267,23 @@ static void uart_sam0_irq_config_##n(const struct device *dev)		\
 #define UART_SAM0_SERCOM_COLLISION_DETECT(n) \
 	(DT_INST_PROP(n, collision_detection))
 
-#ifdef MCLK
-#define UART_SAM0_CONFIG_DEFN(n)					\
-static const struct uart_sam0_dev_cfg uart_sam0_config_##n = {		\
-	.regs = (SercomUsart *)DT_INST_REG_ADDR(n),			\
-	.baudrate = DT_INST_PROP(n, current_speed),			\
-	.mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(n),	\
-	.mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)),	\
-	.gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),\
-	.pads = UART_SAM0_SERCOM_PADS(n),				\
-	.collision_detect = UART_SAM0_SERCOM_COLLISION_DETECT(n),	\
-	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
-	UART_SAM0_IRQ_HANDLER_FUNC(n)					\
-	UART_SAM0_DMA_CHANNELS(n)					\
-}
-#else
+#define ASSIGNED_CLOCKS_CELL_BY_NAME					\
+	ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_NAME
+
 #define UART_SAM0_CONFIG_DEFN(n)					\
 static const struct uart_sam0_dev_cfg uart_sam0_config_##n = {		\
 	.regs = (SercomUsart *)DT_INST_REG_ADDR(n),			\
 	.baudrate = DT_INST_PROP(n, current_speed),			\
-	.pm_apbcmask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, pm, bit)),	\
-	.gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id),\
+	.gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen),		\
+	.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id),		\
+	.mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n),		\
+	.mclk_mask = ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(n, bit),	\
 	.pads = UART_SAM0_SERCOM_PADS(n),				\
 	.collision_detect = UART_SAM0_SERCOM_COLLISION_DETECT(n),	\
 	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
 	UART_SAM0_IRQ_HANDLER_FUNC(n)					\
 	UART_SAM0_DMA_CHANNELS(n)					\
 }
-#endif
 
 #define UART_SAM0_DEVICE_INIT(n)					\
 PINCTRL_DT_INST_DEFINE(n);						\
@@ -1314,3 +1298,5 @@ DEVICE_DT_INST_DEFINE(n, uart_sam0_init, NULL,				\
 UART_SAM0_IRQ_HANDLER(n)
 
 DT_INST_FOREACH_STATUS_OKAY(UART_SAM0_DEVICE_INIT)
+
+/* clang-format on */
diff --git a/drivers/serial/uart_sedi.c b/drivers/serial/uart_sedi.c
index 3a82a9a7747..1bee633b36c 100644
--- a/drivers/serial/uart_sedi.c
+++ b/drivers/serial/uart_sedi.c
@@ -8,6 +8,7 @@
 #include <zephyr/device.h>
 #include <zephyr/drivers/uart.h>
 #include <zephyr/pm/device.h>
+#include <zephyr/pm/device_runtime.h>
 #include "sedi_driver_uart.h"
 
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
@@ -63,11 +64,11 @@ static void uart_sedi_cb(struct device *port);
 	};							      \
 								      \
 	static struct uart_sedi_drv_data drv_data_##n;		      \
-	PM_DEVICE_DT_DEFINE(DT_NODELABEL(uart##n),                    \
+	PM_DEVICE_DT_INST_DEFINE(n,                                   \
 			    uart_sedi_pm_action);		      \
-	DEVICE_DT_DEFINE(DT_NODELABEL(uart##n),		              \
+	DEVICE_DT_INST_DEFINE(n,			              \
 		      &uart_sedi_init,				      \
-		      PM_DEVICE_DT_GET(DT_NODELABEL(uart##n)),        \
+		      PM_DEVICE_DT_INST_GET(n),			      \
 		      &drv_data_##n, &config_info_##n,		      \
 		      PRE_KERNEL_1,				      \
 		      CONFIG_SERIAL_INIT_PRIORITY, &api);	      \
@@ -222,6 +223,8 @@ static int uart_sedi_poll_in(const struct device *dev, unsigned char *data)
 	uint32_t status;
 	int ret = 0;
 
+	(void)pm_device_runtime_get(dev);
+
 	sedi_uart_get_status(instance, (uint32_t *) &status);
 
 	/* In order to check if there is any data to read from UART
@@ -236,6 +239,9 @@ static int uart_sedi_poll_in(const struct device *dev, unsigned char *data)
 			ret = -1;
 		}
 	}
+
+	pm_device_runtime_put(dev);
+
 	return ret;
 }
 
@@ -244,7 +250,11 @@ static void uart_sedi_poll_out(const struct device *dev,
 {
 	sedi_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
 
+	(void)pm_device_runtime_get(dev);
+
 	sedi_uart_write(instance, data);
+
+	pm_device_runtime_put(dev);
 }
 
 #ifdef CONFIG_UART_LINE_CTRL
@@ -281,6 +291,8 @@ static int uart_sedi_err_check(const struct device *dev)
 	uint32_t status;
 	int ret_status = 0;
 
+	(void)pm_device_runtime_get(dev);
+
 	sedi_uart_get_status(instance, (uint32_t *const)&status);
 	if (status &  SEDI_UART_RX_OE) {
 		ret_status = UART_ERROR_OVERRUN;
@@ -298,6 +310,8 @@ static int uart_sedi_err_check(const struct device *dev)
 		ret_status = UART_BREAK;
 	}
 
+	pm_device_runtime_put(dev);
+
 	return ret_status;
 }
 
@@ -308,30 +322,52 @@ static int uart_sedi_fifo_fill(const struct device *dev, const uint8_t *tx_data,
 			       int size)
 {
 	sedi_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
+	int ret = 0;
+
+	pm_device_runtime_get(dev);
 
-	return sedi_uart_fifo_fill(instance, tx_data, size);
+	ret = sedi_uart_fifo_fill(instance, tx_data, size);
+
+	pm_device_runtime_put(dev);
+
+	return ret;
 }
 
 static int uart_sedi_fifo_read(const struct device *dev, uint8_t *rx_data,
 			       const int size)
 {
 	sedi_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
+	int ret = 0;
+
+	pm_device_runtime_get(dev);
+
+	ret = sedi_uart_fifo_read(instance, rx_data, size);
 
-	return sedi_uart_fifo_read(instance, rx_data, size);
+	pm_device_runtime_put(dev);
+
+	return ret;
 }
 
 static void uart_sedi_irq_tx_enable(const struct device *dev)
 {
 	sedi_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
 
+	pm_device_runtime_get(dev);
+
 	sedi_uart_irq_tx_enable(instance);
+
+	pm_device_runtime_put(dev);
 }
 
 static void uart_sedi_irq_tx_disable(const struct device *dev)
 {
 	sedi_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
 
+	pm_device_runtime_get(dev);
+
 	sedi_uart_irq_tx_disable(instance);
+
+	pm_device_runtime_put(dev);
 }
 
 static int uart_sedi_irq_tx_ready(const struct device *dev)
@@ -344,15 +380,26 @@ static int uart_sedi_irq_tx_ready(const struct device *dev)
 static int uart_sedi_irq_tx_complete(const struct device *dev)
 {
 	sedi_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
+	int ret = 0;
+
+	pm_device_runtime_get(dev);
 
-	return sedi_uart_is_tx_complete(instance);
+	ret = sedi_uart_is_tx_complete(instance);
+
+	pm_device_runtime_put(dev);
+
+	return ret;
 }
 
 static void uart_sedi_irq_rx_enable(const struct device *dev)
 {
 	sedi_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
 
+#ifdef CONFIG_PM_DEVICE_RUNTIME
+	pm_device_runtime_get(dev);
+#else
 	uart_busy_set(dev);
+#endif
 	sedi_uart_irq_rx_enable(instance);
 }
 
@@ -361,7 +408,11 @@ static void uart_sedi_irq_rx_disable(const struct device *dev)
 	sedi_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
 
 	sedi_uart_irq_rx_disable(instance);
+#ifdef CONFIG_PM_DEVICE_RUNTIME
+	pm_device_runtime_put(dev);
+#else
 	uart_busy_clear(dev);
+#endif
 }
 
 static int uart_sedi_irq_rx_ready(const struct device *dev)
@@ -375,14 +426,22 @@ static void uart_sedi_irq_err_enable(const struct device *dev)
 {
 	sedi_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
 
+	pm_device_runtime_get(dev);
+
 	sedi_uart_irq_err_enable(instance);
+
+	pm_device_runtime_put(dev);
 }
 
 static void uart_sedi_irq_err_disable(const struct device *dev)
 {
 	sedi_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
 
+	pm_device_runtime_get(dev);
+
 	sedi_uart_irq_err_disable(instance);
+
+	pm_device_runtime_put(dev);
 }
 
 static int uart_sedi_irq_is_pending(const struct device *dev)
@@ -397,7 +456,12 @@ static int uart_sedi_irq_update(const struct device *dev)
 {
 	sedi_uart_t instance = GET_CONTROLLER_INSTANCE(dev);
 
+	pm_device_runtime_get(dev);
+
 	sedi_uart_update_irq_cache(instance);
+
+	pm_device_runtime_put(dev);
+
 	return 1;
 }
 
@@ -444,6 +508,9 @@ static int uart_sedi_line_ctrl_set(struct device *dev,
 	int ret;
 
 	k_mutex_lock(GET_MUTEX(dev), K_FOREVER);
+
+	pm_device_runtime_get(dev);
+
 	switch (ctrl) {
 	case UART_LINE_CTRL_BAUD_RATE:
 		sedi_uart_get_config(instance, &cfg);
@@ -454,6 +521,9 @@ static int uart_sedi_line_ctrl_set(struct device *dev,
 	default:
 		ret = -ENODEV;
 	}
+
+	pm_device_runtime_put(dev);
+
 	k_mutex_unlock(GET_MUTEX(dev));
 	ret = get_xfer_error(ret);
 	return ret;
@@ -468,6 +538,9 @@ static int uart_sedi_line_ctrl_get(struct device *dev,
 	int ret;
 
 	k_mutex_lock(GET_MUTEX(dev), K_FOREVER);
+
+	pm_device_runtime_get(dev);
+
 	switch (ctrl) {
 	case UART_LINE_CTRL_BAUD_RATE:
 		ret = sedi_uart_get_config(instance, &cfg);
@@ -506,6 +579,9 @@ static int uart_sedi_line_ctrl_get(struct device *dev,
 	default:
 		ret = -ENODEV;
 	}
+
+	pm_device_runtime_put(dev);
+
 	k_mutex_unlock(GET_MUTEX(dev));
 	ret = get_xfer_error(ret);
 	return ret;
@@ -562,6 +638,8 @@ static int uart_sedi_init(const struct device *dev)
 	config->uart_irq_config_func(dev);
 #endif  /* CONFIG_UART_INTERRUPT_DRIVEN */
 
+	pm_device_runtime_enable(dev);
+
 	return 0;
 }
 
diff --git a/drivers/serial/uart_shell.c b/drivers/serial/uart_shell.c
index 2e29ab954cd..129fba143fb 100644
--- a/drivers/serial/uart_shell.c
+++ b/drivers/serial/uart_shell.c
@@ -16,6 +16,26 @@ static bool device_is_uart(const struct device *dev)
 	return DEVICE_API_IS(uart, dev);
 }
 
+static int cmd_uart_write(const struct shell *sh, size_t argc, char **argv)
+{
+	char *s_dev_name = argv[1];
+	const struct device *dev = shell_device_get_binding(s_dev_name);
+
+	if (!dev || !device_is_uart(dev)) {
+		shell_error(sh, "UART: Device driver %s not found.", s_dev_name);
+		return -ENODEV;
+	}
+
+	char *buf = argv[2];
+	int msg_len = strlen(buf);
+
+	for (int i = 0; i < msg_len; i++) {
+		uart_poll_out(dev, buf[i]);
+	}
+
+	return 0;
+}
+
 static int cmd_uart_baudrate(const struct shell *sh, size_t argc, char **argv)
 {
 	char *s_dev_name = argv[1];
@@ -102,14 +122,18 @@ static void device_name_get(size_t idx, struct shell_static_entry *entry)
 SHELL_DYNAMIC_CMD_CREATE(dsub_device_name, device_name_get);
 
 SHELL_STATIC_SUBCMD_SET_CREATE(sub_uart_cmds,
+	SHELL_CMD_ARG(write, &dsub_device_name,
+		      "Write data to the UART device\n"
+		      "Usage: write <device> <data>",
+		      cmd_uart_write, 3, 0),
 	SHELL_CMD_ARG(baudrate, &dsub_device_name,
-			  "Configure UART device baudrate\n"
-			  "Usage: baudrate <device> <baudrate>",
-			  cmd_uart_baudrate, 3, 0),
+		      "Configure UART device baudrate\n"
+		      "Usage: baudrate <device> <baudrate>",
+		      cmd_uart_baudrate, 3, 0),
 	SHELL_CMD_ARG(fc, &dsub_device_name,
-			  "Configure UART device flow control\n"
-			  "Usage: fc <device> <none|rtscts|dtrdsr|rs485>",
-			  cmd_uart_flow_control, 3, 0),
+		      "Configure UART device flow control\n"
+		      "Usage: fc <device> <none|rtscts|dtrdsr|rs485>",
+		      cmd_uart_flow_control, 3, 0),
 	SHELL_SUBCMD_SET_END     /* Array terminated. */
 );
 
diff --git a/drivers/serial/uart_si32_usart.c b/drivers/serial/uart_si32_usart.c
index 472f53c244c..89283e4639b 100644
--- a/drivers/serial/uart_si32_usart.c
+++ b/drivers/serial/uart_si32_usart.c
@@ -378,7 +378,7 @@ static int usart_si32_init(const struct device *dev)
 	static const struct usart_si32_config usart_si32_cfg_##index = {                           \
 		.usart = (SI32_USART_A_Type *)DT_INST_REG_ADDR(index),                             \
 		.hw_flow_control = DT_INST_PROP(index, hw_flow_control),                           \
-		.parity = DT_INST_ENUM_IDX_OR(index, parity, UART_CFG_PARITY_NONE),                \
+		.parity = DT_INST_ENUM_IDX(index, parity),                                         \
 		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(index)),                            \
 		SI32_USART_IRQ_HANDLER_FUNC(index)};                                               \
                                                                                                    \
diff --git a/drivers/serial/uart_silabs_eusart.c b/drivers/serial/uart_silabs_eusart.c
new file mode 100644
index 00000000000..e9244dfa3e1
--- /dev/null
+++ b/drivers/serial/uart_silabs_eusart.c
@@ -0,0 +1,1186 @@
+/*
+ * Copyright (c) 2024, Yishai Jaffe
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT silabs_eusart_uart
+
+#include <errno.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/clock_control_silabs.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/uart.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/pm/device.h>
+#include <zephyr/pm/policy.h>
+#include <em_eusart.h>
+#include <zephyr/drivers/dma.h>
+#include <zephyr/drivers/dma/dma_silabs_ldma.h>
+
+LOG_MODULE_REGISTER(uart_silabs_eusart, CONFIG_UART_LOG_LEVEL);
+
+struct eusart_dma_channel {
+	const struct device *dma_dev;
+	uint32_t dma_channel;
+	struct dma_block_config blk_cfg;
+	struct dma_config dma_cfg;
+	uint8_t priority;
+	uint8_t *buffer;
+	size_t buffer_length;
+	size_t counter;
+	size_t offset;
+	struct k_work_delayable timeout_work;
+	int32_t timeout;
+	bool enabled;
+};
+
+struct eusart_config {
+	EUSART_TypeDef *eusart;
+	const struct pinctrl_dev_config *pcfg;
+	const struct device *clock_dev;
+	const struct silabs_clock_control_cmu_config clock_cfg;
+	void (*irq_config_func)(const struct device *dev);
+};
+
+enum eusart_pm_lock {
+	EUSART_PM_LOCK_TX,
+	EUSART_PM_LOCK_TX_POLL,
+	EUSART_PM_LOCK_RX,
+	EUSART_PM_LOCK_COUNT,
+};
+
+struct eusart_data {
+	struct uart_config uart_cfg;
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	uart_irq_callback_user_data_t callback;
+	void *cb_data;
+#endif
+#ifdef CONFIG_UART_SILABS_EUSART_ASYNC
+	const struct device *uart_dev;
+	uart_callback_t async_cb;
+	void *async_user_data;
+	struct eusart_dma_channel dma_rx;
+	struct eusart_dma_channel dma_tx;
+	uint8_t *rx_next_buffer;
+	size_t rx_next_buffer_len;
+#endif
+#ifdef CONFIG_PM
+	ATOMIC_DEFINE(pm_lock, EUSART_PM_LOCK_COUNT);
+#endif
+};
+
+static int eusart_pm_action(const struct device *dev, enum pm_device_action action);
+
+/**
+ * @brief Get PM lock on low power states
+ *
+ * @param dev  UART device struct
+ * @param lock UART PM lock type
+ *
+ * @return true if lock was taken, false otherwise
+ */
+static bool eusart_pm_lock_get(const struct device *dev, enum eusart_pm_lock lock)
+{
+#ifdef CONFIG_PM
+	struct eusart_data *data = dev->data;
+	bool was_locked = atomic_test_and_set_bit(data->pm_lock, lock);
+
+	if (!was_locked) {
+		/* Lock out low-power states that would interfere with UART traffic */
+		pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
+		pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
+	}
+
+	return !was_locked;
+#else
+	return false;
+#endif
+}
+
+/**
+ * @brief Release PM lock on low power states
+ *
+ * @param dev  UART device struct
+ * @param lock UART PM lock type
+ *
+ * @return true if lock was released, false otherwise
+ */
+static bool eusart_pm_lock_put(const struct device *dev, enum eusart_pm_lock lock)
+{
+#ifdef CONFIG_PM
+	struct eusart_data *data = dev->data;
+	bool was_locked = atomic_test_and_clear_bit(data->pm_lock, lock);
+
+	if (was_locked) {
+		/* Unlock low-power states that would interfere with UART traffic */
+		pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
+		pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
+	}
+
+	return was_locked;
+#else
+	return false;
+#endif
+}
+
+static int eusart_poll_in(const struct device *dev, unsigned char *c)
+{
+	const struct eusart_config *config = dev->config;
+
+	if (EUSART_StatusGet(config->eusart) & EUSART_STATUS_RXFL) {
+		*c = EUSART_Rx(config->eusart);
+		return 0;
+	}
+
+	return -1;
+}
+
+static void eusart_poll_out(const struct device *dev, unsigned char c)
+{
+	const struct eusart_config *config = dev->config;
+
+	if (eusart_pm_lock_get(dev, EUSART_PM_LOCK_TX_POLL)) {
+		EUSART_IntEnable(config->eusart, EUSART_IF_TXC);
+	}
+	/* EUSART_Tx function already waits for the transmit buffer being empty
+	 * and waits for the bus to be free to transmit.
+	 */
+	EUSART_Tx(config->eusart, c);
+}
+
+static int eusart_err_check(const struct device *dev)
+{
+	const struct eusart_config *config = dev->config;
+	uint32_t flags = EUSART_IntGet(config->eusart);
+	int err = 0;
+
+	if (flags & EUSART_IF_RXOF) {
+		err |= UART_ERROR_OVERRUN;
+	}
+
+	if (flags & EUSART_IF_PERR) {
+		err |= UART_ERROR_PARITY;
+	}
+
+	if (flags & EUSART_IF_FERR) {
+		err |= UART_ERROR_FRAMING;
+	}
+
+	EUSART_IntClear(config->eusart, EUSART_IF_RXOF | EUSART_IF_PERR | EUSART_IF_FERR);
+
+	return err;
+}
+
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+static int eusart_fifo_fill(const struct device *dev, const uint8_t *tx_data, int len)
+{
+	const struct eusart_config *config = dev->config;
+	int i = 0;
+
+	while ((i < len) && (EUSART_StatusGet(config->eusart) & EUSART_STATUS_TXFL)) {
+		config->eusart->TXDATA = (uint32_t)tx_data[i++];
+	}
+
+	if (!(EUSART_StatusGet(config->eusart) & EUSART_STATUS_TXFL)) {
+		EUSART_IntClear(config->eusart, EUSART_IF_TXFL);
+	}
+
+	return i;
+}
+
+static int eusart_fifo_read(const struct device *dev, uint8_t *rx_data, const int len)
+{
+	const struct eusart_config *config = dev->config;
+	int i = 0;
+
+	while ((i < len) && (EUSART_StatusGet(config->eusart) & EUSART_STATUS_RXFL)) {
+		rx_data[i++] = (uint8_t)config->eusart->RXDATA;
+	}
+
+	if (!(EUSART_StatusGet(config->eusart) & EUSART_STATUS_RXFL)) {
+		EUSART_IntClear(config->eusart, EUSART_IF_RXFL);
+	}
+
+	return i;
+}
+
+static void eusart_irq_tx_enable(const struct device *dev)
+{
+	const struct eusart_config *config = dev->config;
+
+	eusart_pm_lock_get(dev, EUSART_PM_LOCK_TX);
+	EUSART_IntClear(config->eusart, EUSART_IEN_TXFL | EUSART_IEN_TXC);
+	EUSART_IntEnable(config->eusart, EUSART_IEN_TXFL | EUSART_IEN_TXC);
+}
+
+static void eusart_irq_tx_disable(const struct device *dev)
+{
+	const struct eusart_config *config = dev->config;
+
+	EUSART_IntDisable(config->eusart, EUSART_IEN_TXFL | EUSART_IEN_TXC);
+	EUSART_IntClear(config->eusart, EUSART_IEN_TXFL | EUSART_IEN_TXC);
+	eusart_pm_lock_put(dev, EUSART_PM_LOCK_TX);
+}
+
+static int eusart_irq_tx_complete(const struct device *dev)
+{
+	const struct eusart_config *config = dev->config;
+	uint32_t flags = EUSART_IntGet(config->eusart);
+
+	EUSART_IntClear(config->eusart, EUSART_IF_TXC);
+
+	return !!(flags & EUSART_IF_TXC);
+}
+
+static int eusart_irq_tx_ready(const struct device *dev)
+{
+	const struct eusart_config *config = dev->config;
+
+	return (config->eusart->IEN & EUSART_IEN_TXFL) &&
+	       (EUSART_IntGet(config->eusart) & EUSART_IF_TXFL);
+}
+
+static void eusart_irq_rx_enable(const struct device *dev)
+{
+	const struct eusart_config *config = dev->config;
+
+	eusart_pm_lock_get(dev, EUSART_PM_LOCK_RX);
+	EUSART_IntClear(config->eusart, EUSART_IEN_RXFL);
+	EUSART_IntEnable(config->eusart, EUSART_IEN_RXFL);
+}
+
+static void eusart_irq_rx_disable(const struct device *dev)
+{
+	const struct eusart_config *config = dev->config;
+
+	EUSART_IntDisable(config->eusart, EUSART_IEN_RXFL);
+	EUSART_IntClear(config->eusart, EUSART_IEN_RXFL);
+	eusart_pm_lock_put(dev, EUSART_PM_LOCK_RX);
+}
+
+static int eusart_irq_rx_ready(const struct device *dev)
+{
+	const struct eusart_config *config = dev->config;
+
+	return (config->eusart->IEN & EUSART_IEN_RXFL) &&
+	       (EUSART_IntGet(config->eusart) & EUSART_IF_RXFL);
+}
+
+static void eusart_irq_err_enable(const struct device *dev)
+{
+	const struct eusart_config *config = dev->config;
+
+	EUSART_IntClear(config->eusart, EUSART_IF_RXOF | EUSART_IF_PERR | EUSART_IF_FERR);
+	EUSART_IntEnable(config->eusart, EUSART_IF_RXOF | EUSART_IF_PERR | EUSART_IF_FERR);
+}
+
+static void eusart_irq_err_disable(const struct device *dev)
+{
+	const struct eusart_config *config = dev->config;
+
+	EUSART_IntDisable(config->eusart, EUSART_IF_RXOF | EUSART_IF_PERR | EUSART_IF_FERR);
+	EUSART_IntClear(config->eusart, EUSART_IF_RXOF | EUSART_IF_PERR | EUSART_IF_FERR);
+}
+
+static int eusart_irq_is_pending(const struct device *dev)
+{
+	return eusart_irq_tx_ready(dev) || eusart_irq_rx_ready(dev);
+}
+
+static int eusart_irq_update(const struct device *dev)
+{
+	return 1;
+}
+
+static void eusart_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
+				    void *cb_data)
+{
+	struct eusart_data *data = dev->data;
+
+	data->callback = cb;
+	data->cb_data = cb_data;
+}
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+
+#ifdef CONFIG_UART_SILABS_EUSART_ASYNC
+static void eusart_async_user_callback(struct eusart_data *data, struct uart_event *event)
+{
+	if (data->async_cb) {
+		data->async_cb(data->uart_dev, event, data->async_user_data);
+	}
+}
+
+static void eusart_async_timer_start(struct k_work_delayable *work, int32_t timeout)
+{
+	if (timeout != SYS_FOREVER_US && timeout != 0) {
+		k_work_reschedule(work, K_USEC(timeout));
+	}
+}
+
+static void eusart_async_evt_rx_rdy(struct eusart_data *data)
+{
+	struct uart_event event = {
+		.type = UART_RX_RDY,
+		.data.rx.buf = data->dma_rx.buffer,
+		.data.rx.len = data->dma_rx.counter - data->dma_rx.offset,
+		.data.rx.offset = data->dma_rx.offset
+	};
+
+	data->dma_rx.offset = data->dma_rx.counter;
+
+	if (event.data.rx.len > 0) {
+		eusart_async_user_callback(data, &event);
+	}
+}
+
+static void eusart_async_evt_tx_done(struct eusart_data *data)
+{
+	struct uart_event event = {
+		.type = UART_TX_DONE,
+		.data.tx.buf = data->dma_tx.buffer,
+		.data.tx.len = data->dma_tx.counter
+	};
+
+	data->dma_tx.buffer_length = 0;
+	data->dma_tx.counter = 0;
+
+	eusart_async_user_callback(data, &event);
+}
+
+static void eusart_async_evt_tx_abort(struct eusart_data *data)
+{
+	struct uart_event event = {
+		.type = UART_TX_ABORTED,
+		.data.tx.buf = data->dma_tx.buffer,
+		.data.tx.len = data->dma_tx.counter
+	};
+
+	data->dma_tx.buffer_length = 0;
+	data->dma_tx.counter = 0;
+
+	eusart_async_user_callback(data, &event);
+}
+
+static void eusart_async_evt_rx_err(struct eusart_data *data, int err_code)
+{
+	struct uart_event event = {
+		.type = UART_RX_STOPPED,
+		.data.rx_stop.reason = err_code,
+		.data.rx_stop.data.len = data->dma_rx.counter,
+		.data.rx_stop.data.offset = 0,
+		.data.rx_stop.data.buf = data->dma_rx.buffer
+	};
+
+	eusart_async_user_callback(data, &event);
+}
+
+static void eusart_async_evt_rx_buf_release(struct eusart_data *data)
+{
+	struct uart_event evt = {
+		.type = UART_RX_BUF_RELEASED,
+		.data.rx_buf.buf = data->dma_rx.buffer,
+	};
+
+	eusart_async_user_callback(data, &evt);
+}
+
+static void eusart_async_evt_rx_buf_request(struct eusart_data *data)
+{
+	struct uart_event evt = {
+		.type = UART_RX_BUF_REQUEST,
+	};
+
+	eusart_async_user_callback(data, &evt);
+}
+
+static int eusart_async_callback_set(const struct device *dev, uart_callback_t callback,
+				     void *user_data)
+{
+	struct eusart_data *data = dev->data;
+
+	data->async_cb = callback;
+	data->async_user_data = user_data;
+
+	return 0;
+}
+
+static void eusart_dma_replace_buffer(const struct device *dev)
+{
+	struct eusart_data *data = dev->data;
+
+	data->dma_rx.offset = 0;
+	data->dma_rx.counter = 0;
+	data->dma_rx.buffer = data->rx_next_buffer;
+	data->dma_rx.buffer_length = data->rx_next_buffer_len;
+	data->rx_next_buffer = NULL;
+	data->rx_next_buffer_len = 0;
+
+	eusart_async_evt_rx_buf_request(data);
+}
+
+static void eusart_dma_rx_flush(struct eusart_data *data)
+{
+	struct dma_status stat;
+	size_t rx_rcv_len;
+
+	if (!dma_get_status(data->dma_rx.dma_dev, data->dma_rx.dma_channel, &stat)) {
+		rx_rcv_len = data->dma_rx.buffer_length - stat.pending_length;
+		if (rx_rcv_len > data->dma_rx.offset) {
+			data->dma_rx.counter = rx_rcv_len;
+			eusart_async_evt_rx_rdy(data);
+		}
+	}
+}
+
+__maybe_unused static void eusart_dma_rx_cb(const struct device *dma_dev, void *user_data,
+					    uint32_t channel, int status)
+{
+	const struct device *uart_dev = user_data;
+	struct eusart_data *data = uart_dev->data;
+	struct uart_event disabled_event = {
+		.type = UART_RX_DISABLED
+	};
+
+	if (status < 0) {
+		eusart_async_evt_rx_err(data, status);
+		return;
+	}
+
+	k_work_cancel_delayable(&data->dma_rx.timeout_work);
+
+	data->dma_rx.counter = data->dma_rx.buffer_length;
+
+	eusart_async_evt_rx_rdy(data);
+
+	if (data->rx_next_buffer) {
+		eusart_async_evt_rx_buf_release(data);
+		eusart_dma_replace_buffer(uart_dev);
+	} else {
+		dma_stop(data->dma_rx.dma_dev, data->dma_rx.dma_channel);
+		data->dma_rx.enabled = false;
+		eusart_async_evt_rx_buf_release(data);
+		eusart_async_user_callback(data, &disabled_event);
+	}
+}
+
+__maybe_unused static void eusart_dma_tx_cb(const struct device *dma_dev, void *user_data,
+					    uint32_t channel, int status)
+{
+	const struct device *uart_dev = user_data;
+	struct eusart_data *data = uart_dev->data;
+
+	dma_stop(data->dma_tx.dma_dev, data->dma_tx.dma_channel);
+	data->dma_tx.enabled = false;
+}
+
+static int eusart_async_tx(const struct device *dev, const uint8_t *tx_data, size_t buf_size,
+			   int32_t timeout)
+{
+	const struct eusart_config *config = dev->config;
+	struct eusart_data *data = dev->data;
+	int ret;
+
+	if (!data->dma_tx.dma_dev) {
+		return -ENODEV;
+	}
+
+	if (data->dma_tx.buffer_length) {
+		return -EBUSY;
+	}
+
+	data->dma_tx.buffer = (uint8_t *)tx_data;
+	data->dma_tx.buffer_length = buf_size;
+	data->dma_tx.timeout = timeout;
+
+	data->dma_tx.blk_cfg.source_address = (uint32_t)data->dma_tx.buffer;
+	data->dma_tx.blk_cfg.block_size = data->dma_tx.buffer_length;
+
+	eusart_pm_lock_get(dev, EUSART_PM_LOCK_TX);
+
+	EUSART_IntClear(config->eusart, EUSART_IF_TXC);
+	EUSART_IntEnable(config->eusart, EUSART_IF_TXC);
+
+	ret = dma_config(data->dma_tx.dma_dev, data->dma_tx.dma_channel, &data->dma_tx.dma_cfg);
+	if (ret) {
+		LOG_ERR("dma tx config error!");
+		return ret;
+	}
+
+	/* These 2 lines need to be call before dma_start otherwise uart and dma callback are
+	 * called just after before the execution of these lines.
+	 */
+	data->dma_tx.enabled = true;
+
+	eusart_async_timer_start(&data->dma_tx.timeout_work, data->dma_tx.timeout);
+
+	ret = dma_start(data->dma_tx.dma_dev, data->dma_tx.dma_channel);
+	if (ret) {
+		LOG_ERR("UART err: TX DMA start failed!");
+		data->dma_tx.enabled = false;
+		k_work_cancel_delayable(&data->dma_tx.timeout_work);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int eusart_async_tx_abort(const struct device *dev)
+{
+	const struct eusart_config *config = dev->config;
+	struct eusart_data *data = dev->data;
+	size_t tx_buffer_length = data->dma_tx.buffer_length;
+	struct dma_status stat;
+
+	if (!tx_buffer_length) {
+		return -EFAULT;
+	}
+
+	dma_stop(data->dma_tx.dma_dev, data->dma_tx.dma_channel);
+
+	EUSART_IntDisable(config->eusart, EUSART_IF_TXC);
+	EUSART_IntClear(config->eusart, EUSART_IF_TXC);
+	eusart_pm_lock_put(dev, EUSART_PM_LOCK_TX);
+
+	k_work_cancel_delayable(&data->dma_tx.timeout_work);
+
+	if (!dma_get_status(data->dma_tx.dma_dev, data->dma_tx.dma_channel, &stat)) {
+		data->dma_tx.counter = tx_buffer_length - stat.pending_length;
+	}
+
+	data->dma_tx.enabled = false;
+
+	eusart_async_evt_tx_abort(data);
+
+	return 0;
+}
+
+static int eusart_async_rx_enable(const struct device *dev, uint8_t *rx_buf, size_t buf_size,
+				  int32_t timeout)
+{
+	const struct eusart_config *config = dev->config;
+	struct eusart_data *data = dev->data;
+	int ret;
+
+	if (!data->dma_rx.dma_dev) {
+		return -ENODEV;
+	}
+
+	if (data->dma_rx.enabled) {
+		LOG_WRN("RX was already enabled");
+		return -EBUSY;
+	}
+
+	data->dma_rx.offset = 0;
+	data->dma_rx.buffer = rx_buf;
+	data->dma_rx.buffer_length = buf_size;
+	data->dma_rx.counter = 0;
+	data->dma_rx.timeout = timeout;
+	data->dma_rx.blk_cfg.block_size = buf_size;
+	data->dma_rx.blk_cfg.dest_address = (uint32_t)data->dma_rx.buffer;
+
+	ret = dma_config(data->dma_rx.dma_dev, data->dma_rx.dma_channel, &data->dma_rx.dma_cfg);
+
+	if (ret) {
+		LOG_ERR("UART ERR: RX DMA config failed!");
+		return -EINVAL;
+	}
+
+	if (dma_start(data->dma_rx.dma_dev, data->dma_rx.dma_channel)) {
+		LOG_ERR("UART ERR: RX DMA start failed!");
+		return -EFAULT;
+	}
+
+	eusart_pm_lock_get(dev, EUSART_PM_LOCK_RX);
+	EUSART_IntClear(config->eusart, EUSART_IF_RXOF | EUSART_IF_RXTO);
+	EUSART_IntEnable(config->eusart, EUSART_IF_RXOF);
+	EUSART_IntEnable(config->eusart, EUSART_IF_RXTO);
+
+	data->dma_rx.enabled = true;
+
+	eusart_async_evt_rx_buf_request(data);
+
+	return ret;
+}
+
+static int eusart_async_rx_disable(const struct device *dev)
+{
+	const struct eusart_config *config = dev->config;
+	EUSART_TypeDef *eusart = config->eusart;
+	struct eusart_data *data = dev->data;
+	struct uart_event disabled_event = {
+		.type = UART_RX_DISABLED
+	};
+
+	if (!data->dma_rx.enabled) {
+		return -EFAULT;
+	}
+
+	dma_stop(data->dma_rx.dma_dev, data->dma_rx.dma_channel);
+
+	EUSART_IntDisable(eusart, EUSART_IF_RXOF);
+	EUSART_IntDisable(eusart, EUSART_IF_RXTO);
+	EUSART_IntClear(eusart, EUSART_IF_RXOF | EUSART_IF_RXTO);
+	eusart_pm_lock_put(dev, EUSART_PM_LOCK_RX);
+
+	k_work_cancel_delayable(&data->dma_rx.timeout_work);
+
+	eusart_dma_rx_flush(data);
+
+	eusart_async_evt_rx_buf_release(data);
+
+	if (data->rx_next_buffer) {
+		struct uart_event rx_next_buf_release_evt = {
+			.type = UART_RX_BUF_RELEASED,
+			.data.rx_buf.buf = data->rx_next_buffer,
+		};
+		eusart_async_user_callback(data, &rx_next_buf_release_evt);
+	}
+
+	data->rx_next_buffer = NULL;
+	data->rx_next_buffer_len = 0;
+
+	data->dma_rx.enabled = false;
+
+	eusart_async_user_callback(data, &disabled_event);
+
+	return 0;
+}
+
+static int eusart_async_rx_buf_rsp(const struct device *dev, uint8_t *buf, size_t len)
+{
+	struct eusart_data *data = dev->data;
+	unsigned int key;
+	int ret;
+
+	key = irq_lock();
+
+	if (data->rx_next_buffer) {
+		return -EBUSY;
+	} else if (!data->dma_rx.enabled) {
+		return -EACCES;
+	}
+
+	data->rx_next_buffer = buf;
+	data->rx_next_buffer_len = len;
+	data->dma_rx.blk_cfg.dest_address = (uint32_t)buf;
+	data->dma_rx.blk_cfg.block_size = len;
+
+	irq_unlock(key);
+
+	ret = silabs_ldma_append_block(data->dma_rx.dma_dev, data->dma_rx.dma_channel,
+				       &data->dma_rx.dma_cfg);
+	if (ret) {
+		LOG_ERR("UART ERR: RX DMA append failed!");
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+static void eusart_async_rx_timeout(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct eusart_dma_channel *rx_channel =
+		CONTAINER_OF(dwork, struct eusart_dma_channel, timeout_work);
+	struct eusart_data *data = CONTAINER_OF(rx_channel, struct eusart_data, dma_rx);
+
+	eusart_dma_rx_flush(data);
+}
+
+static void eusart_async_tx_timeout(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct eusart_dma_channel *tx_channel =
+		CONTAINER_OF(dwork, struct eusart_dma_channel, timeout_work);
+	struct eusart_data *data = CONTAINER_OF(tx_channel, struct eusart_data, dma_tx);
+	const struct device *dev = data->uart_dev;
+
+	eusart_async_tx_abort(dev);
+}
+
+static int eusart_async_init(const struct device *dev)
+{
+	const struct eusart_config *config = dev->config;
+	EUSART_TypeDef *eusart = config->eusart;
+	struct eusart_data *data = dev->data;
+
+	data->uart_dev = dev;
+
+	if (data->dma_rx.dma_dev) {
+		if (!device_is_ready(data->dma_rx.dma_dev)) {
+			return -ENODEV;
+		}
+
+		data->dma_rx.dma_channel = dma_request_channel(data->dma_rx.dma_dev, NULL);
+	}
+
+	if (data->dma_tx.dma_dev) {
+		if (!device_is_ready(data->dma_tx.dma_dev)) {
+			return -ENODEV;
+		}
+
+		data->dma_tx.dma_channel = dma_request_channel(data->dma_tx.dma_dev, NULL);
+	}
+
+	data->dma_rx.enabled = false;
+	data->dma_tx.enabled = false;
+
+	k_work_init_delayable(&data->dma_rx.timeout_work, eusart_async_rx_timeout);
+	k_work_init_delayable(&data->dma_tx.timeout_work, eusart_async_tx_timeout);
+
+	memset(&data->dma_rx.blk_cfg, 0, sizeof(data->dma_rx.blk_cfg));
+	data->dma_rx.blk_cfg.source_address = (uintptr_t)&(eusart->RXDATA);
+	data->dma_rx.blk_cfg.dest_address = 0;
+	data->dma_rx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
+	data->dma_rx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;
+	data->dma_rx.dma_cfg.complete_callback_en = 1;
+	data->dma_rx.dma_cfg.channel_priority = 3;
+	data->dma_rx.dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
+	data->dma_rx.dma_cfg.head_block = &data->dma_rx.blk_cfg;
+	data->dma_rx.dma_cfg.user_data = (void *)dev;
+	data->rx_next_buffer = NULL;
+	data->rx_next_buffer_len = 0;
+
+	memset(&data->dma_tx.blk_cfg, 0, sizeof(data->dma_tx.blk_cfg));
+	data->dma_tx.blk_cfg.dest_address = (uintptr_t)&(eusart->TXDATA);
+	data->dma_tx.blk_cfg.source_address = 0;
+	data->dma_tx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
+	data->dma_tx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
+	data->dma_tx.dma_cfg.complete_callback_en = 1;
+	data->dma_tx.dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
+	data->dma_tx.dma_cfg.head_block = &data->dma_tx.blk_cfg;
+	data->dma_tx.dma_cfg.user_data = (void *)dev;
+
+	return 0;
+}
+#endif /* CONFIG_UART_SILABS_EUSART_ASYNC */
+
+static void eusart_isr(const struct device *dev)
+{
+	__maybe_unused struct eusart_data *data = dev->data;
+	const struct eusart_config *config = dev->config;
+	EUSART_TypeDef *eusart = config->eusart;
+	uint32_t flags = EUSART_IntGet(eusart);
+	__maybe_unused struct dma_status stat;
+
+	if (flags & EUSART_IF_TXC) {
+		if (eusart_pm_lock_put(dev, EUSART_PM_LOCK_TX_POLL)) {
+			EUSART_IntDisable(eusart, EUSART_IEN_TXC);
+			EUSART_IntClear(eusart, EUSART_IF_TXC);
+		}
+	}
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	if (data->callback) {
+		data->callback(dev, data->cb_data);
+	}
+#endif
+#ifdef CONFIG_UART_SILABS_EUSART_ASYNC
+
+	if (flags & EUSART_IF_RXTO) {
+		if (data->dma_rx.timeout == 0) {
+			eusart_dma_rx_flush(data);
+		} else {
+			eusart_async_timer_start(&data->dma_rx.timeout_work, data->dma_rx.timeout);
+		}
+
+		EUSART_IntClear(eusart, EUSART_IF_RXTO);
+	}
+
+	if (flags & EUSART_IF_RXOF) {
+		eusart_async_evt_rx_err(data, UART_ERROR_OVERRUN);
+
+		eusart_async_rx_disable(dev);
+
+		EUSART_IntClear(eusart, EUSART_IF_RXOF);
+	}
+
+	if (flags & EUSART_IF_TXC) {
+		k_work_cancel_delayable(&data->dma_tx.timeout_work);
+
+		if (!dma_get_status(data->dma_tx.dma_dev, data->dma_tx.dma_channel, &stat)) {
+			data->dma_tx.counter = data->dma_tx.buffer_length - stat.pending_length;
+		}
+
+		if (data->dma_tx.counter == data->dma_tx.buffer_length) {
+			EUSART_IntDisable(eusart, EUSART_IF_TXC);
+			EUSART_IntClear(eusart, EUSART_IF_TXC);
+			eusart_pm_lock_put(dev, EUSART_PM_LOCK_TX);
+		}
+
+		eusart_async_evt_tx_done(data);
+	}
+#endif /* CONFIG_UART_SILABS_EUSART_ASYNC */
+}
+
+static EUSART_Parity_TypeDef eusart_cfg2ll_parity(enum uart_config_parity parity)
+{
+	switch (parity) {
+	case UART_CFG_PARITY_ODD:
+		return eusartOddParity;
+	case UART_CFG_PARITY_EVEN:
+		return eusartEvenParity;
+	case UART_CFG_PARITY_NONE:
+	default:
+		return eusartNoParity;
+	}
+}
+
+static inline enum uart_config_parity eusart_ll2cfg_parity(EUSART_Parity_TypeDef parity)
+{
+	switch (parity) {
+	case eusartOddParity:
+		return UART_CFG_PARITY_ODD;
+	case eusartEvenParity:
+		return UART_CFG_PARITY_EVEN;
+	case eusartNoParity:
+	default:
+		return UART_CFG_PARITY_NONE;
+	}
+}
+
+static EUSART_Stopbits_TypeDef eusart_cfg2ll_stopbits(enum uart_config_stop_bits sb)
+{
+	switch (sb) {
+	case UART_CFG_STOP_BITS_0_5:
+		return eusartStopbits0p5;
+	case UART_CFG_STOP_BITS_1:
+		return eusartStopbits1;
+	case UART_CFG_STOP_BITS_2:
+		return eusartStopbits2;
+	case UART_CFG_STOP_BITS_1_5:
+		return eusartStopbits1p5;
+	default:
+		return eusartStopbits1;
+	}
+}
+
+static inline enum uart_config_stop_bits eusart_ll2cfg_stopbits(EUSART_Stopbits_TypeDef sb)
+{
+	switch (sb) {
+	case eusartStopbits0p5:
+		return UART_CFG_STOP_BITS_0_5;
+	case eusartStopbits1:
+		return UART_CFG_STOP_BITS_1;
+	case eusartStopbits1p5:
+		return UART_CFG_STOP_BITS_1_5;
+	case eusartStopbits2:
+		return UART_CFG_STOP_BITS_2;
+	default:
+		return UART_CFG_STOP_BITS_1;
+	}
+}
+
+static EUSART_Databits_TypeDef eusart_cfg2ll_databits(enum uart_config_data_bits db,
+						      enum uart_config_parity p)
+{
+	switch (db) {
+	case UART_CFG_DATA_BITS_7:
+		if (p == UART_CFG_PARITY_NONE) {
+			return eusartDataBits7;
+		} else {
+			return eusartDataBits8;
+		}
+	case UART_CFG_DATA_BITS_9:
+		return eusartDataBits9;
+	case UART_CFG_DATA_BITS_8:
+	default:
+		if (p == UART_CFG_PARITY_NONE) {
+			return eusartDataBits8;
+		} else {
+			return eusartDataBits9;
+		}
+		return eusartDataBits8;
+	}
+}
+
+static inline enum uart_config_data_bits eusart_ll2cfg_databits(EUSART_Databits_TypeDef db,
+								EUSART_Parity_TypeDef p)
+{
+	switch (db) {
+	case eusartDataBits7:
+		if (p == eusartNoParity) {
+			return UART_CFG_DATA_BITS_7;
+		} else {
+			return UART_CFG_DATA_BITS_6;
+		}
+	case eusartDataBits9:
+		if (p == eusartNoParity) {
+			return UART_CFG_DATA_BITS_9;
+		} else {
+			return UART_CFG_DATA_BITS_8;
+		}
+	case eusartDataBits8:
+	default:
+		if (p == eusartNoParity) {
+			return UART_CFG_DATA_BITS_8;
+		} else {
+			return UART_CFG_DATA_BITS_7;
+		}
+	}
+}
+
+static EUSART_HwFlowControl_TypeDef eusart_cfg2ll_hwctrl(enum uart_config_flow_control fc)
+{
+	if (fc == UART_CFG_FLOW_CTRL_RTS_CTS) {
+		return eusartHwFlowControlCtsAndRts;
+	}
+
+	return eusartHwFlowControlNone;
+}
+
+static inline enum uart_config_flow_control eusart_ll2cfg_hwctrl(EUSART_HwFlowControl_TypeDef fc)
+{
+	if (fc == eusartHwFlowControlCtsAndRts) {
+		return UART_CFG_FLOW_CTRL_RTS_CTS;
+	}
+
+	return UART_CFG_FLOW_CTRL_NONE;
+}
+
+static void eusart_configure_peripheral(const struct device *dev, bool enable)
+{
+	const struct eusart_config *config = dev->config;
+	const struct eusart_data *data = dev->data;
+	const struct uart_config *uart_cfg = &data->uart_cfg;
+	EUSART_UartInit_TypeDef eusartInit = EUSART_UART_INIT_DEFAULT_HF;
+	EUSART_AdvancedInit_TypeDef advancedSettings = EUSART_ADVANCED_INIT_DEFAULT;
+
+	eusartInit.baudrate = uart_cfg->baudrate;
+	eusartInit.parity = eusart_cfg2ll_parity(uart_cfg->parity);
+	eusartInit.stopbits = eusart_cfg2ll_stopbits(uart_cfg->stop_bits);
+	eusartInit.databits = eusart_cfg2ll_databits(uart_cfg->data_bits, uart_cfg->parity);
+	advancedSettings.hwFlowControl = eusart_cfg2ll_hwctrl(uart_cfg->flow_ctrl);
+	eusartInit.advancedSettings = &advancedSettings;
+	eusartInit.enable = eusartDisable;
+
+	EUSART_UartInitHf(config->eusart, &eusartInit);
+
+	if (IS_ENABLED(CONFIG_UART_SILABS_EUSART_ASYNC)) {
+		config->eusart->CFG1 |= EUSART_CFG1_RXTIMEOUT_ONEFRAME;
+	}
+
+	if (enable) {
+		EUSART_Enable(config->eusart, eusartEnable);
+	}
+}
+
+#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
+static int eusart_configure(const struct device *dev, const struct uart_config *cfg)
+{
+	const struct eusart_config *config = dev->config;
+	EUSART_TypeDef *eusart = config->eusart;
+	struct eusart_data *data = dev->data;
+	struct uart_config *uart_cfg = &data->uart_cfg;
+
+#ifdef CONFIG_UART_SILABS_EUSART_ASYNC
+	if (data->dma_rx.enabled || data->dma_tx.enabled) {
+		return -EBUSY;
+	}
+#endif
+
+	if (cfg->parity == UART_CFG_PARITY_MARK || cfg->parity == UART_CFG_PARITY_SPACE) {
+		return -ENOSYS;
+	}
+
+	if (cfg->flow_ctrl == UART_CFG_FLOW_CTRL_DTR_DSR ||
+	    cfg->flow_ctrl == UART_CFG_FLOW_CTRL_RS485) {
+		return -ENOSYS;
+	}
+
+	*uart_cfg = *cfg;
+
+	EUSART_Enable(eusart, eusartDisable);
+	eusart_configure_peripheral(dev, true);
+
+	return 0;
+};
+
+static int eusart_config_get(const struct device *dev, struct uart_config *cfg)
+{
+	struct eusart_data *data = dev->data;
+	struct uart_config *uart_cfg = &data->uart_cfg;
+
+	*cfg = *uart_cfg;
+
+	return 0;
+}
+#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
+
+static int eusart_init(const struct device *dev)
+{
+	int err;
+	const struct eusart_config *config = dev->config;
+
+	/* The peripheral and gpio clock are already enabled from soc and gpio driver */
+	/* Enable EUSART clock */
+	err = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_cfg);
+	if (err < 0) {
+		return err;
+	}
+
+	eusart_configure_peripheral(dev, false);
+
+	config->irq_config_func(dev);
+
+#ifdef CONFIG_UART_SILABS_EUSART_ASYNC
+	err = eusart_async_init(dev);
+	if (err < 0) {
+		return err;
+	}
+#endif
+
+	return pm_device_driver_init(dev, eusart_pm_action);
+}
+
+static int eusart_pm_action(const struct device *dev, enum pm_device_action action)
+{
+	__maybe_unused struct eusart_data *data = dev->data;
+	const struct eusart_config *config = dev->config;
+	int err;
+
+	if (action == PM_DEVICE_ACTION_RESUME) {
+		err = clock_control_on(config->clock_dev,
+				       (clock_control_subsys_t)&config->clock_cfg);
+		if (err < 0 && err != -EALREADY) {
+			return err;
+		}
+
+		err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+		if (err < 0) {
+			return err;
+		}
+
+		EUSART_Enable(config->eusart, eusartEnable);
+	} else if (IS_ENABLED(CONFIG_PM_DEVICE) && (action == PM_DEVICE_ACTION_SUSPEND)) {
+#ifdef CONFIG_UART_SILABS_EUSART_ASYNC
+		/* Entering suspend requires there to be no active asynchronous calls. */
+		__ASSERT_NO_MSG(!data->dma_rx.enabled);
+		__ASSERT_NO_MSG(!data->dma_tx.enabled);
+#endif
+		EUSART_Enable(config->eusart, eusartDisable);
+
+		err = clock_control_off(config->clock_dev,
+					(clock_control_subsys_t)&config->clock_cfg);
+		if (err < 0) {
+			return err;
+		}
+
+		err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
+		if (err < 0 && err != -ENOENT) {
+			return err;
+		}
+
+	} else {
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(uart, eusart_driver_api) = {
+	.poll_in = eusart_poll_in,
+	.poll_out = eusart_poll_out,
+	.err_check = eusart_err_check,
+#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
+	.configure = eusart_configure,
+	.config_get = eusart_config_get,
+#endif
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	.fifo_fill = eusart_fifo_fill,
+	.fifo_read = eusart_fifo_read,
+	.irq_tx_enable = eusart_irq_tx_enable,
+	.irq_tx_disable = eusart_irq_tx_disable,
+	.irq_tx_complete = eusart_irq_tx_complete,
+	.irq_tx_ready = eusart_irq_tx_ready,
+	.irq_rx_enable = eusart_irq_rx_enable,
+	.irq_rx_disable = eusart_irq_rx_disable,
+	.irq_rx_ready = eusart_irq_rx_ready,
+	.irq_err_enable = eusart_irq_err_enable,
+	.irq_err_disable = eusart_irq_err_disable,
+	.irq_is_pending = eusart_irq_is_pending,
+	.irq_update = eusart_irq_update,
+	.irq_callback_set = eusart_irq_callback_set,
+#endif
+#ifdef CONFIG_UART_SILABS_EUSART_ASYNC
+	.callback_set = eusart_async_callback_set,
+	.tx = eusart_async_tx,
+	.tx_abort = eusart_async_tx_abort,
+	.rx_enable = eusart_async_rx_enable,
+	.rx_disable = eusart_async_rx_disable,
+	.rx_buf_rsp = eusart_async_rx_buf_rsp,
+#endif
+};
+
+#ifdef CONFIG_UART_SILABS_EUSART_ASYNC
+
+#define EUSART_DMA_CHANNEL_INIT(index, dir)                                                        \
+	.dma_##dir = {                                                                             \
+		.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(index, dir)),                   \
+		.dma_cfg = {                                                                       \
+			.dma_slot = SILABS_LDMA_REQSEL_TO_SLOT(                                    \
+				    DT_INST_DMAS_CELL_BY_NAME(index, dir, slot)),                  \
+			.source_data_size = 1,                                                     \
+			.dest_data_size = 1,                                                       \
+			.source_burst_length = 1,                                                  \
+			.dest_burst_length = 1,                                                    \
+			.dma_callback = eusart_dma_##dir##_cb,                                     \
+		}                                                                                  \
+	},
+#define EUSART_DMA_CHANNEL(index, dir)                                                             \
+	COND_CODE_1(DT_INST_NODE_HAS_PROP(index, dmas),                                            \
+		 (EUSART_DMA_CHANNEL_INIT(index, dir)), ())
+#else
+#define EUSART_DMA_CHANNEL(index, dir)
+#endif
+
+
+#define SILABS_EUSART_IRQ_HANDLER_FUNC(idx) .irq_config_func = eusart_config_func_##idx,
+#define SILABS_EUSART_IRQ_HANDLER(idx)                                                             \
+	static void eusart_config_func_##idx(const struct device *dev)                             \
+	{                                                                                          \
+		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, rx, irq),                                     \
+			    DT_INST_IRQ_BY_NAME(idx, rx, priority), eusart_isr,                    \
+			    DEVICE_DT_INST_GET(idx), 0);                                           \
+		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, tx, irq),                                     \
+			    DT_INST_IRQ_BY_NAME(idx, tx, priority), eusart_isr,                    \
+			    DEVICE_DT_INST_GET(idx), 0);                                           \
+                                                                                                   \
+		irq_enable(DT_INST_IRQ_BY_NAME(idx, rx, irq));                                     \
+		irq_enable(DT_INST_IRQ_BY_NAME(idx, tx, irq));                                     \
+	}
+
+#define SILABS_EUSART_INIT(idx)                                                                    \
+	SILABS_EUSART_IRQ_HANDLER(idx);                                                            \
+	PINCTRL_DT_INST_DEFINE(idx);                                                               \
+	PM_DEVICE_DT_INST_DEFINE(idx, eusart_pm_action);                                           \
+                                                                                                   \
+	static const struct eusart_config eusart_cfg_##idx = {                                     \
+		.eusart = (EUSART_TypeDef *)DT_INST_REG_ADDR(idx),                                 \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx),                                       \
+		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)),                              \
+		.clock_cfg = SILABS_DT_INST_CLOCK_CFG(idx),                                        \
+		SILABS_EUSART_IRQ_HANDLER_FUNC(idx)                                                \
+	};                                                                                         \
+                                                                                                   \
+	static struct eusart_data eusart_data_##idx = {                                            \
+		.uart_cfg = {                                                                      \
+			.baudrate  = DT_INST_PROP(idx, current_speed),                             \
+			.parity    = DT_INST_ENUM_IDX(idx, parity),                                \
+			.stop_bits = DT_INST_ENUM_IDX(idx, stop_bits),                             \
+			.data_bits = DT_INST_ENUM_IDX(idx, data_bits),                             \
+			.flow_ctrl = DT_INST_PROP(idx, hw_flow_control)                            \
+						? UART_CFG_FLOW_CTRL_RTS_CTS                       \
+						: UART_CFG_FLOW_CTRL_NONE,                         \
+		},                                                                                 \
+		EUSART_DMA_CHANNEL(idx, rx)                                                        \
+		EUSART_DMA_CHANNEL(idx, tx)                                                        \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(idx, eusart_init, PM_DEVICE_DT_INST_GET(idx), &eusart_data_##idx,    \
+			      &eusart_cfg_##idx, PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY,        \
+			      &eusart_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(SILABS_EUSART_INIT)
diff --git a/drivers/serial/uart_silabs_usart.c b/drivers/serial/uart_silabs_usart.c
new file mode 100644
index 00000000000..3937ffbf07b
--- /dev/null
+++ b/drivers/serial/uart_silabs_usart.c
@@ -0,0 +1,1189 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT silabs_usart_uart
+
+#include <errno.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/clock_control_silabs.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/uart.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/pm/device.h>
+#include <zephyr/pm/policy.h>
+#include <em_usart.h>
+#ifdef CONFIG_UART_SILABS_USART_ASYNC
+#include <zephyr/drivers/dma.h>
+#include <zephyr/drivers/dma/dma_silabs_ldma.h>
+#endif
+
+LOG_MODULE_REGISTER(uart_silabs_usart, CONFIG_UART_LOG_LEVEL);
+
+#define SILABS_USART_TIMER_COMPARE_VALUE 0xff
+#define SILABS_USART_TIMEOUT_TO_TIMERCOUNTER(timeout, baudrate)                                    \
+	((timeout * NSEC_PER_USEC) / ((NSEC_PER_SEC / baudrate) * SILABS_USART_TIMER_COMPARE_VALUE))
+
+#ifdef CONFIG_UART_SILABS_USART_ASYNC
+struct uart_dma_channel {
+	const struct device *dma_dev;
+	uint32_t dma_channel;
+	struct dma_block_config blk_cfg;
+	struct dma_config dma_cfg;
+	uint8_t priority;
+	uint8_t *buffer;
+	size_t buffer_length;
+	volatile size_t counter;
+	size_t offset;
+	int32_t timeout_cnt;
+	int32_t timeout;
+	bool enabled;
+};
+#endif
+struct uart_silabs_config {
+	const struct pinctrl_dev_config *pcfg;
+	const struct device *clock_dev;
+	const struct silabs_clock_control_cmu_config clock_cfg;
+	USART_TypeDef *base;
+	void (*irq_config_func)(const struct device *dev);
+};
+
+enum uart_silabs_pm_lock {
+	UART_SILABS_PM_LOCK_TX,
+	UART_SILABS_PM_LOCK_TX_POLL,
+	UART_SILABS_PM_LOCK_RX,
+	UART_SILABS_PM_LOCK_COUNT,
+};
+
+struct uart_silabs_data {
+	struct uart_config *uart_cfg;
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	uart_irq_callback_user_data_t callback;
+	void *cb_data;
+#endif
+#ifdef CONFIG_UART_SILABS_USART_ASYNC
+	const struct device *uart_dev;
+	uart_callback_t async_cb;
+	void *async_user_data;
+	struct uart_dma_channel dma_rx;
+	struct uart_dma_channel dma_tx;
+	uint8_t *rx_next_buffer;
+	size_t rx_next_buffer_len;
+#endif
+#ifdef CONFIG_PM
+	ATOMIC_DEFINE(pm_lock, UART_SILABS_PM_LOCK_COUNT);
+#endif
+};
+
+static int uart_silabs_pm_action(const struct device *dev, enum pm_device_action action);
+
+/**
+ * @brief Get PM lock on low power states
+ *
+ * @param dev  UART device struct
+ * @param lock UART PM lock type
+ *
+ * @return true if lock was taken, false otherwise
+ */
+static bool uart_silabs_pm_lock_get(const struct device *dev, enum uart_silabs_pm_lock lock)
+{
+#ifdef CONFIG_PM
+	struct uart_silabs_data *data = dev->data;
+	bool was_locked = atomic_test_and_set_bit(data->pm_lock, lock);
+
+	if (!was_locked) {
+		/* Lock out low-power states that would interfere with UART traffic */
+		pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
+		pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
+	}
+
+	return !was_locked;
+#else
+	return false;
+#endif
+}
+
+/**
+ * @brief Release PM lock on low power states
+ *
+ * @param dev  UART device struct
+ * @param lock UART PM lock type
+ *
+ * @return true if lock was released, false otherwise
+ */
+static bool uart_silabs_pm_lock_put(const struct device *dev, enum uart_silabs_pm_lock lock)
+{
+#ifdef CONFIG_PM
+	struct uart_silabs_data *data = dev->data;
+	bool was_locked = atomic_test_and_clear_bit(data->pm_lock, lock);
+
+	if (was_locked) {
+		/* Unlock low-power states that would interfere with UART traffic */
+		pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
+		pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
+	}
+
+	return was_locked;
+#else
+	return false;
+#endif
+}
+
+static int uart_silabs_poll_in(const struct device *dev, unsigned char *c)
+{
+	const struct uart_silabs_config *config = dev->config;
+	uint32_t flags = USART_StatusGet(config->base);
+
+	if (flags & USART_STATUS_RXDATAV) {
+		*c = USART_Rx(config->base);
+		return 0;
+	}
+
+	return -1;
+}
+
+static void uart_silabs_poll_out(const struct device *dev, unsigned char c)
+{
+	const struct uart_silabs_config *config = dev->config;
+
+	if (uart_silabs_pm_lock_get(dev, UART_SILABS_PM_LOCK_TX_POLL)) {
+		USART_IntEnable(config->base, USART_IF_TXC);
+	}
+
+	USART_Tx(config->base, c);
+}
+
+static int uart_silabs_err_check(const struct device *dev)
+{
+	const struct uart_silabs_config *config = dev->config;
+	uint32_t flags = USART_IntGet(config->base);
+	int err = 0;
+
+	if (flags & USART_IF_RXOF) {
+		err |= UART_ERROR_OVERRUN;
+	}
+
+	if (flags & USART_IF_PERR) {
+		err |= UART_ERROR_PARITY;
+	}
+
+	if (flags & USART_IF_FERR) {
+		err |= UART_ERROR_FRAMING;
+	}
+
+	USART_IntClear(config->base, USART_IF_RXOF | USART_IF_PERR | USART_IF_FERR);
+
+	return err;
+}
+
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+static int uart_silabs_fifo_fill(const struct device *dev, const uint8_t *tx_data, int len)
+{
+	const struct uart_silabs_config *config = dev->config;
+	int i = 0;
+
+	while ((i < len) && (config->base->STATUS & USART_STATUS_TXBL)) {
+		config->base->TXDATA = tx_data[i++];
+	}
+
+	return i;
+}
+
+static int uart_silabs_fifo_read(const struct device *dev, uint8_t *rx_data, const int len)
+{
+	const struct uart_silabs_config *config = dev->config;
+	int i = 0;
+
+	while ((i < len) && (config->base->STATUS & USART_STATUS_RXDATAV)) {
+		rx_data[i++] = (uint8_t)config->base->RXDATA;
+	}
+
+	return i;
+}
+
+static void uart_silabs_irq_tx_enable(const struct device *dev)
+{
+	const struct uart_silabs_config *config = dev->config;
+
+	(void)uart_silabs_pm_lock_get(dev, UART_SILABS_PM_LOCK_TX);
+	USART_IntEnable(config->base, USART_IEN_TXBL | USART_IEN_TXC);
+}
+
+static void uart_silabs_irq_tx_disable(const struct device *dev)
+{
+	const struct uart_silabs_config *config = dev->config;
+
+	USART_IntDisable(config->base, USART_IEN_TXBL | USART_IEN_TXC);
+	(void)uart_silabs_pm_lock_put(dev, UART_SILABS_PM_LOCK_TX);
+}
+
+static int uart_silabs_irq_tx_complete(const struct device *dev)
+{
+	const struct uart_silabs_config *config = dev->config;
+	uint32_t flags = USART_IntGet(config->base);
+
+	USART_IntClear(config->base, USART_IF_TXC);
+
+	return !!(flags & USART_IF_TXC);
+}
+
+static int uart_silabs_irq_tx_ready(const struct device *dev)
+{
+	const struct uart_silabs_config *config = dev->config;
+	uint32_t flags = USART_IntGetEnabled(config->base);
+
+	return !!(flags & USART_IF_TXBL);
+}
+
+static void uart_silabs_irq_rx_enable(const struct device *dev)
+{
+	const struct uart_silabs_config *config = dev->config;
+
+	(void)uart_silabs_pm_lock_get(dev, UART_SILABS_PM_LOCK_RX);
+	USART_IntEnable(config->base, USART_IEN_RXDATAV);
+}
+
+static void uart_silabs_irq_rx_disable(const struct device *dev)
+{
+	const struct uart_silabs_config *config = dev->config;
+
+	USART_IntDisable(config->base, USART_IEN_RXDATAV);
+	(void)uart_silabs_pm_lock_put(dev, UART_SILABS_PM_LOCK_RX);
+}
+
+static int uart_silabs_irq_rx_full(const struct device *dev)
+{
+	const struct uart_silabs_config *config = dev->config;
+	uint32_t flags = USART_IntGet(config->base);
+
+	return !!(flags & USART_IF_RXDATAV);
+}
+
+static int uart_silabs_irq_rx_ready(const struct device *dev)
+{
+	const struct uart_silabs_config *config = dev->config;
+
+	return (config->base->IEN & USART_IEN_RXDATAV) && uart_silabs_irq_rx_full(dev);
+}
+
+static void uart_silabs_irq_err_enable(const struct device *dev)
+{
+	const struct uart_silabs_config *config = dev->config;
+
+	USART_IntEnable(config->base, USART_IF_RXOF | USART_IF_PERR | USART_IF_FERR);
+}
+
+static void uart_silabs_irq_err_disable(const struct device *dev)
+{
+	const struct uart_silabs_config *config = dev->config;
+
+	USART_IntDisable(config->base, USART_IF_RXOF | USART_IF_PERR | USART_IF_FERR);
+}
+
+static int uart_silabs_irq_is_pending(const struct device *dev)
+{
+	return uart_silabs_irq_tx_ready(dev) || uart_silabs_irq_rx_ready(dev);
+}
+
+static int uart_silabs_irq_update(const struct device *dev)
+{
+	return 1;
+}
+
+static void uart_silabs_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
+					 void *cb_data)
+{
+	struct uart_silabs_data *data = dev->data;
+
+	data->callback = cb;
+	data->cb_data = cb_data;
+}
+#endif /* CONFIG_UART_INTERRUPT_DRIVEN */
+
+#ifdef CONFIG_UART_SILABS_USART_ASYNC
+static inline void async_user_callback(struct uart_silabs_data *data, struct uart_event *event)
+{
+	if (data->async_cb) {
+		data->async_cb(data->uart_dev, event, data->async_user_data);
+	}
+}
+
+static inline void async_evt_rx_rdy(struct uart_silabs_data *data)
+{
+	struct uart_event event = {
+		.type = UART_RX_RDY,
+		.data.rx.buf = data->dma_rx.buffer,
+		.data.rx.len = data->dma_rx.counter - data->dma_rx.offset,
+		.data.rx.offset = data->dma_rx.offset
+	};
+
+	data->dma_rx.offset = data->dma_rx.counter;
+
+	if (event.data.rx.len > 0) {
+		async_user_callback(data, &event);
+	}
+}
+
+static inline void async_evt_tx_done(struct uart_silabs_data *data)
+{
+	struct uart_event event = {
+		.type = UART_TX_DONE,
+		.data.tx.buf = data->dma_tx.buffer,
+		.data.tx.len = data->dma_tx.counter
+	};
+
+	data->dma_tx.buffer_length = 0;
+	data->dma_tx.counter = 0;
+
+	async_user_callback(data, &event);
+}
+
+static inline void async_evt_tx_abort(struct uart_silabs_data *data)
+{
+	struct uart_event event = {
+		.type = UART_TX_ABORTED,
+		.data.tx.buf = data->dma_tx.buffer,
+		.data.tx.len = data->dma_tx.counter
+	};
+
+	data->dma_tx.buffer_length = 0;
+	data->dma_tx.counter = 0;
+
+	async_user_callback(data, &event);
+}
+
+static inline void async_evt_rx_err(struct uart_silabs_data *data, int err_code)
+{
+	struct uart_event event = {
+		.type = UART_RX_STOPPED,
+		.data.rx_stop.reason = err_code,
+		.data.rx_stop.data.len = data->dma_rx.counter,
+		.data.rx_stop.data.offset = 0,
+		.data.rx_stop.data.buf = data->dma_rx.buffer
+	};
+
+	async_user_callback(data, &event);
+}
+
+static inline void async_evt_rx_buf_release(struct uart_silabs_data *data)
+{
+	struct uart_event evt = {
+		.type = UART_RX_BUF_RELEASED,
+		.data.rx_buf.buf = data->dma_rx.buffer,
+	};
+
+	async_user_callback(data, &evt);
+}
+
+static inline void async_evt_rx_buf_request(struct uart_silabs_data *data)
+{
+	struct uart_event evt = {
+		.type = UART_RX_BUF_REQUEST,
+	};
+
+	async_user_callback(data, &evt);
+}
+
+static int uart_silabs_async_callback_set(const struct device *dev, uart_callback_t callback,
+					  void *user_data)
+{
+	struct uart_silabs_data *data = dev->data;
+
+	data->async_cb = callback;
+	data->async_user_data = user_data;
+
+	return 0;
+}
+
+static void uart_silabs_dma_replace_buffer(const struct device *dev)
+{
+	struct uart_silabs_data *data = dev->data;
+
+	data->dma_rx.offset = 0;
+	data->dma_rx.counter = 0;
+	data->dma_rx.buffer = data->rx_next_buffer;
+	data->dma_rx.buffer_length = data->rx_next_buffer_len;
+	data->rx_next_buffer = NULL;
+	data->rx_next_buffer_len = 0;
+
+	async_evt_rx_buf_request(data);
+}
+
+static void uart_silabs_dma_rx_flush(struct uart_silabs_data *data)
+{
+	struct dma_status stat;
+	size_t rx_rcv_len;
+
+	if (!dma_get_status(data->dma_rx.dma_dev, data->dma_rx.dma_channel, &stat)) {
+		rx_rcv_len = data->dma_rx.buffer_length - stat.pending_length;
+		if (rx_rcv_len > data->dma_rx.offset) {
+			data->dma_rx.counter = rx_rcv_len;
+			async_evt_rx_rdy(data);
+		}
+	}
+}
+
+void uart_silabs_dma_rx_cb(const struct device *dma_dev, void *user_data, uint32_t channel,
+			   int status)
+{
+	const struct device *uart_dev = user_data;
+	struct uart_silabs_data *data = uart_dev->data;
+	struct uart_event disabled_event = {.type = UART_RX_DISABLED};
+
+	if (status < 0) {
+		async_evt_rx_err(data, status);
+		return;
+	}
+
+	data->dma_rx.counter = data->dma_rx.buffer_length;
+
+	async_evt_rx_rdy(data);
+
+	if (data->rx_next_buffer) {
+		async_evt_rx_buf_release(data);
+		uart_silabs_dma_replace_buffer(uart_dev);
+	} else {
+		dma_stop(data->dma_rx.dma_dev, data->dma_rx.dma_channel);
+		data->dma_rx.enabled = false;
+		async_evt_rx_buf_release(data);
+		async_user_callback(data, &disabled_event);
+	}
+}
+
+void uart_silabs_dma_tx_cb(const struct device *dma_dev, void *user_data, uint32_t channel,
+			   int status)
+{
+	const struct device *uart_dev = user_data;
+	struct uart_silabs_data *data = uart_dev->data;
+
+	dma_stop(data->dma_tx.dma_dev, data->dma_tx.dma_channel);
+	data->dma_tx.enabled = false;
+}
+
+static int uart_silabs_async_tx(const struct device *dev, const uint8_t *tx_data, size_t buf_size,
+				int32_t timeout)
+{
+	const struct uart_silabs_config *config = dev->config;
+	struct uart_silabs_data *data = dev->data;
+	int ret;
+
+	if (!data->dma_tx.dma_dev) {
+		return -ENODEV;
+	}
+
+	if (data->dma_tx.buffer_length) {
+		return -EBUSY;
+	}
+
+	data->dma_tx.buffer = (uint8_t *)tx_data;
+	data->dma_tx.buffer_length = buf_size;
+
+	/* User timeout is expressed as number of TCMP2 interrupt which occurs every
+	 * SILABS_USART_TIMER_COMPARE_VALUE baud-times
+	 */
+	if (data->uart_cfg->baudrate > 0 && timeout >= 0) {
+		data->dma_tx.timeout =
+			SILABS_USART_TIMEOUT_TO_TIMERCOUNTER(timeout, data->uart_cfg->baudrate);
+	} else {
+		data->dma_tx.timeout = 0;
+	}
+
+	data->dma_tx.blk_cfg.source_address = (uint32_t)data->dma_tx.buffer;
+	data->dma_tx.blk_cfg.block_size = data->dma_tx.buffer_length;
+
+	(void)uart_silabs_pm_lock_get(dev, UART_SILABS_PM_LOCK_TX);
+	USART_IntClear(config->base, USART_IF_TXC | USART_IF_TCMP2);
+	USART_IntEnable(config->base, USART_IF_TXC);
+	if (timeout >= 0) {
+		USART_IntEnable(config->base, USART_IF_TCMP2);
+	}
+
+	ret = dma_config(data->dma_tx.dma_dev, data->dma_tx.dma_channel, &data->dma_tx.dma_cfg);
+	if (ret) {
+		LOG_ERR("dma tx config error!");
+		return ret;
+	}
+
+	ret = dma_start(data->dma_tx.dma_dev, data->dma_tx.dma_channel);
+	if (ret) {
+		LOG_ERR("UART err: TX DMA start failed!");
+		return ret;
+	}
+
+	data->dma_tx.enabled = true;
+
+	return 0;
+}
+
+static int uart_silabs_async_tx_abort(const struct device *dev)
+{
+	const struct uart_silabs_config *config = dev->config;
+	struct uart_silabs_data *data = dev->data;
+	size_t tx_buffer_length = data->dma_tx.buffer_length;
+	struct dma_status stat;
+
+	if (!tx_buffer_length) {
+		return -EFAULT;
+	}
+
+	USART_IntDisable(config->base, USART_IF_TXC);
+	USART_IntDisable(config->base, USART_IF_TCMP2);
+	USART_IntClear(config->base, USART_IF_TXC | USART_IF_TCMP2);
+	(void)uart_silabs_pm_lock_put(dev, UART_SILABS_PM_LOCK_TX);
+
+	if (!dma_get_status(data->dma_tx.dma_dev, data->dma_tx.dma_channel, &stat)) {
+		data->dma_tx.counter = tx_buffer_length - stat.pending_length;
+	}
+
+	dma_stop(data->dma_tx.dma_dev, data->dma_tx.dma_channel);
+	data->dma_tx.enabled = false;
+
+	async_evt_tx_abort(data);
+
+	return 0;
+}
+
+static int uart_silabs_async_rx_enable(const struct device *dev, uint8_t *rx_buf, size_t buf_size,
+				       int32_t timeout)
+{
+	const struct uart_silabs_config *config = dev->config;
+	struct uart_silabs_data *data = dev->data;
+	int ret;
+
+	if (!data->dma_rx.dma_dev) {
+		return -ENODEV;
+	}
+
+	if (data->dma_rx.enabled) {
+		LOG_WRN("RX was already enabled");
+		return -EBUSY;
+	}
+
+	data->dma_rx.offset = 0;
+	data->dma_rx.buffer = rx_buf;
+	data->dma_rx.buffer_length = buf_size;
+	data->dma_rx.counter = 0;
+
+	/* User timeout is expressed as number of TCMP1 interrupt which occurs every
+	 * SILABS_USART_TIMER_COMPARE_VALUE baud-times
+	 */
+	if (data->uart_cfg->baudrate > 0 && timeout >= 0) {
+		data->dma_rx.timeout =
+			SILABS_USART_TIMEOUT_TO_TIMERCOUNTER(timeout, data->uart_cfg->baudrate);
+	} else {
+		data->dma_rx.timeout = 0;
+	}
+
+	data->dma_rx.blk_cfg.block_size = buf_size;
+	data->dma_rx.blk_cfg.dest_address = (uint32_t)data->dma_rx.buffer;
+
+	ret = dma_config(data->dma_rx.dma_dev, data->dma_rx.dma_channel, &data->dma_rx.dma_cfg);
+
+	if (ret) {
+		LOG_ERR("UART ERR: RX DMA config failed!");
+		return -EINVAL;
+	}
+
+	if (dma_start(data->dma_rx.dma_dev, data->dma_rx.dma_channel)) {
+		LOG_ERR("UART ERR: RX DMA start failed!");
+		return -EFAULT;
+	}
+
+	(void)uart_silabs_pm_lock_get(dev, UART_SILABS_PM_LOCK_RX);
+	USART_IntClear(config->base, USART_IF_RXOF | USART_IF_TCMP1);
+	USART_IntEnable(config->base, USART_IF_RXOF);
+
+	if (timeout >= 0) {
+		USART_IntEnable(config->base, USART_IF_TCMP1);
+	}
+
+	data->dma_rx.enabled = true;
+
+	async_evt_rx_buf_request(data);
+
+	return ret;
+}
+
+static int uart_silabs_async_rx_disable(const struct device *dev)
+{
+	const struct uart_silabs_config *config = dev->config;
+	USART_TypeDef *usart = config->base;
+	struct uart_silabs_data *data = dev->data;
+	struct uart_event disabled_event = {.type = UART_RX_DISABLED};
+
+	if (!data->dma_rx.enabled) {
+		return -EFAULT;
+	}
+
+	dma_stop(data->dma_rx.dma_dev, data->dma_rx.dma_channel);
+
+	USART_IntDisable(usart, USART_IF_RXOF);
+	USART_IntDisable(usart, USART_IF_TCMP1);
+	USART_IntClear(usart, USART_IF_RXOF | USART_IF_TCMP1);
+	(void)uart_silabs_pm_lock_put(dev, UART_SILABS_PM_LOCK_RX);
+
+	if (!data->dma_rx.enabled) {
+		usart->CMD = USART_CMD_CLEARRX;
+	}
+
+	uart_silabs_dma_rx_flush(data);
+
+	async_evt_rx_buf_release(data);
+
+	if (data->rx_next_buffer) {
+		struct uart_event rx_next_buf_release_evt = {
+			.type = UART_RX_BUF_RELEASED,
+			.data.rx_buf.buf = data->rx_next_buffer,
+		};
+		async_user_callback(data, &rx_next_buf_release_evt);
+	}
+
+	data->rx_next_buffer = NULL;
+	data->rx_next_buffer_len = 0;
+
+	data->dma_rx.enabled = false;
+
+	async_user_callback(data, &disabled_event);
+
+	return 0;
+}
+
+static int uart_silabs_async_rx_buf_rsp(const struct device *dev, uint8_t *buf, size_t len)
+{
+	struct uart_silabs_data *data = dev->data;
+	unsigned int key;
+	int ret;
+
+	key = irq_lock();
+
+	if (data->rx_next_buffer) {
+		return -EBUSY;
+	} else if (!data->dma_rx.enabled) {
+		return -EACCES;
+	}
+
+	data->rx_next_buffer = buf;
+	data->rx_next_buffer_len = len;
+	data->dma_rx.blk_cfg.dest_address = (uint32_t)buf;
+	data->dma_rx.blk_cfg.block_size = len;
+
+	irq_unlock(key);
+
+	ret = silabs_ldma_append_block(data->dma_rx.dma_dev, data->dma_rx.dma_channel,
+				       &data->dma_rx.dma_cfg);
+	if (ret) {
+		LOG_ERR("UART ERR: RX DMA append failed!");
+		return -EINVAL;
+	}
+
+	return ret;
+}
+
+static int uart_silabs_async_init(const struct device *dev)
+{
+	const struct uart_silabs_config *config = dev->config;
+	USART_TypeDef *usart = config->base;
+	struct uart_silabs_data *data = dev->data;
+
+	data->uart_dev = dev;
+
+	if (data->dma_rx.dma_dev) {
+		if (!device_is_ready(data->dma_rx.dma_dev)) {
+			return -ENODEV;
+		}
+		data->dma_rx.dma_channel = dma_request_channel(data->dma_rx.dma_dev, NULL);
+	}
+
+	if (data->dma_tx.dma_dev) {
+		if (!device_is_ready(data->dma_tx.dma_dev)) {
+			return -ENODEV;
+		}
+		data->dma_tx.dma_channel = dma_request_channel(data->dma_tx.dma_dev, NULL);
+	}
+
+	data->dma_rx.enabled = false;
+	data->dma_tx.enabled = false;
+
+	memset(&data->dma_rx.blk_cfg, 0, sizeof(data->dma_rx.blk_cfg));
+	data->dma_rx.blk_cfg.source_address = (uintptr_t)&(usart->RXDATA);
+	data->dma_rx.blk_cfg.dest_address = 0;
+	data->dma_rx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
+	data->dma_rx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;
+	data->dma_rx.dma_cfg.complete_callback_en = 1;
+	data->dma_rx.dma_cfg.channel_priority = 3;
+	data->dma_rx.dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
+	data->dma_rx.dma_cfg.head_block = &data->dma_rx.blk_cfg;
+	data->dma_rx.dma_cfg.user_data = (void *)dev;
+	data->rx_next_buffer = NULL;
+	data->rx_next_buffer_len = 0;
+
+	memset(&data->dma_tx.blk_cfg, 0, sizeof(data->dma_tx.blk_cfg));
+	data->dma_tx.blk_cfg.dest_address = (uintptr_t)&(usart->TXDATA);
+	data->dma_tx.blk_cfg.source_address = 0;
+	data->dma_tx.blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
+	data->dma_tx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
+	data->dma_tx.dma_cfg.complete_callback_en = 1;
+	data->dma_tx.dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
+	data->dma_tx.dma_cfg.head_block = &data->dma_tx.blk_cfg;
+	data->dma_tx.dma_cfg.user_data = (void *)dev;
+
+	config->base->CMD = USART_CMD_CLEARRX | USART_CMD_CLEARTX;
+	config->base->TIMECMP1 =
+		USART_TIMECMP1_TSTOP_RXACT | USART_TIMECMP1_TSTART_RXEOF |
+		USART_TIMECMP1_RESTARTEN |
+		(SILABS_USART_TIMER_COMPARE_VALUE << _USART_TIMECMP1_TCMPVAL_SHIFT);
+	config->base->TIMECMP2 =
+		USART_TIMECMP2_TSTOP_TXST | USART_TIMECMP2_TSTART_TXEOF | USART_TIMECMP2_RESTARTEN |
+		(SILABS_USART_TIMER_COMPARE_VALUE << _USART_TIMECMP2_TCMPVAL_SHIFT);
+
+	return 0;
+}
+#endif /* CONFIG_UART_SILABS_USART_ASYNC */
+
+static void uart_silabs_isr(const struct device *dev)
+{
+	__maybe_unused struct uart_silabs_data *data = dev->data;
+	const struct uart_silabs_config *config = dev->config;
+	USART_TypeDef *usart = config->base;
+	uint32_t flags = USART_IntGet(usart);
+#ifdef CONFIG_UART_SILABS_USART_ASYNC
+	struct dma_status stat;
+#endif
+
+	if (flags & USART_IF_TXC) {
+		if (uart_silabs_pm_lock_put(dev, UART_SILABS_PM_LOCK_TX_POLL)) {
+			USART_IntDisable(usart, USART_IEN_TXC);
+			USART_IntClear(usart, USART_IF_TXC);
+		}
+	}
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	if (data->callback) {
+		data->callback(dev, data->cb_data);
+	}
+#endif
+#ifdef CONFIG_UART_SILABS_USART_ASYNC
+	if (flags & USART_IF_TCMP1) {
+
+		data->dma_rx.timeout_cnt++;
+		if (data->dma_rx.timeout_cnt >= data->dma_rx.timeout) {
+			uart_silabs_dma_rx_flush(data);
+
+			usart->TIMECMP1 &= ~_USART_TIMECMP1_TSTART_MASK;
+			usart->TIMECMP1 |= USART_TIMECMP1_TSTART_RXEOF;
+			data->dma_rx.timeout_cnt = 0;
+		}
+
+		USART_IntClear(usart, USART_IF_TCMP1);
+	}
+	if (flags & USART_IF_RXOF) {
+		async_evt_rx_err(data, UART_ERROR_OVERRUN);
+
+		uart_silabs_async_rx_disable(dev);
+
+		USART_IntClear(usart, USART_IF_RXOF);
+	}
+	if (flags & USART_IF_TXC) {
+		if (!dma_get_status(data->dma_tx.dma_dev, data->dma_tx.dma_channel, &stat)) {
+			data->dma_tx.counter = data->dma_tx.buffer_length - stat.pending_length;
+		}
+
+		if (data->dma_tx.counter == data->dma_tx.buffer_length) {
+			USART_IntDisable(config->base, USART_IF_TXC);
+			USART_IntDisable(config->base, USART_IF_TCMP2);
+			USART_IntClear(usart, USART_IF_TXC | USART_IF_TCMP2);
+			(void)uart_silabs_pm_lock_put(dev, UART_SILABS_PM_LOCK_TX);
+
+			usart->TIMECMP2 &= ~_USART_TIMECMP2_TSTART_MASK;
+			usart->TIMECMP2 |= USART_TIMECMP2_TSTART_DISABLE;
+		}
+
+		async_evt_tx_done(data);
+	}
+	if (flags & USART_IF_TCMP2) {
+		data->dma_tx.timeout_cnt++;
+		if (data->dma_tx.timeout_cnt >= data->dma_tx.timeout) {
+			usart->TIMECMP2 &= ~_USART_TIMECMP2_TSTART_MASK;
+			usart->TIMECMP2 |= USART_TIMECMP2_TSTART_DISABLE;
+			data->dma_tx.timeout_cnt = 0;
+
+			uart_silabs_async_tx_abort(dev);
+		}
+
+		USART_IntClear(usart, USART_IF_TCMP2);
+	}
+#endif /* CONFIG_UART_SILABS_USART_ASYNC */
+}
+
+static inline USART_Parity_TypeDef uart_silabs_cfg2ll_parity(
+	enum uart_config_parity parity)
+{
+	switch (parity) {
+	case UART_CFG_PARITY_ODD:
+		return usartOddParity;
+	case UART_CFG_PARITY_EVEN:
+		return usartEvenParity;
+	case UART_CFG_PARITY_NONE:
+	default:
+		return usartNoParity;
+	}
+}
+
+static inline USART_Stopbits_TypeDef uart_silabs_cfg2ll_stopbits(
+	enum uart_config_stop_bits sb)
+{
+	switch (sb) {
+	case UART_CFG_STOP_BITS_0_5:
+		return usartStopbits0p5;
+	case UART_CFG_STOP_BITS_1:
+		return usartStopbits1;
+	case UART_CFG_STOP_BITS_2:
+		return usartStopbits2;
+	case UART_CFG_STOP_BITS_1_5:
+		return usartStopbits1p5;
+	default:
+		return usartStopbits1;
+	}
+}
+
+static inline USART_Databits_TypeDef uart_silabs_cfg2ll_databits(
+	enum uart_config_data_bits db, enum uart_config_parity p)
+{
+	switch (db) {
+	case UART_CFG_DATA_BITS_7:
+		if (p == UART_CFG_PARITY_NONE) {
+			return usartDatabits7;
+		} else {
+			return usartDatabits8;
+		}
+	case UART_CFG_DATA_BITS_9:
+		return usartDatabits9;
+	case UART_CFG_DATA_BITS_8:
+	default:
+		if (p == UART_CFG_PARITY_NONE) {
+			return usartDatabits8;
+		} else {
+			return usartDatabits9;
+		}
+		return usartDatabits8;
+	}
+}
+
+static inline USART_HwFlowControl_TypeDef uart_silabs_cfg2ll_hwctrl(
+	enum uart_config_flow_control fc)
+{
+	if (fc == UART_CFG_FLOW_CTRL_RTS_CTS) {
+		return usartHwFlowControlCtsAndRts;
+	}
+
+	return usartHwFlowControlNone;
+}
+
+static inline enum uart_config_parity uart_silabs_ll2cfg_parity(USART_Parity_TypeDef parity)
+{
+	switch (parity) {
+	case usartOddParity:
+		return UART_CFG_PARITY_ODD;
+	case usartEvenParity:
+		return UART_CFG_PARITY_EVEN;
+	case usartNoParity:
+	default:
+		return UART_CFG_PARITY_NONE;
+	}
+}
+
+static inline enum uart_config_stop_bits uart_silabs_ll2cfg_stopbits(USART_Stopbits_TypeDef sb)
+{
+	switch (sb) {
+	case usartStopbits0p5:
+		return UART_CFG_STOP_BITS_0_5;
+	case usartStopbits1:
+		return UART_CFG_STOP_BITS_1;
+	case usartStopbits1p5:
+		return UART_CFG_STOP_BITS_1_5;
+	case usartStopbits2:
+		return UART_CFG_STOP_BITS_2;
+	default:
+		return UART_CFG_STOP_BITS_1;
+	}
+}
+
+static inline enum uart_config_data_bits uart_silabs_ll2cfg_databits(USART_Databits_TypeDef db,
+								    USART_Parity_TypeDef p)
+{
+	switch (db) {
+	case usartDatabits7:
+		if (p == usartNoParity) {
+			return UART_CFG_DATA_BITS_7;
+		} else {
+			return UART_CFG_DATA_BITS_6;
+		}
+	case usartDatabits9:
+		if (p == usartNoParity) {
+			return UART_CFG_DATA_BITS_9;
+		} else {
+			return UART_CFG_DATA_BITS_8;
+		}
+	case usartDatabits8:
+	default:
+		if (p == usartNoParity) {
+			return UART_CFG_DATA_BITS_8;
+		} else {
+			return UART_CFG_DATA_BITS_7;
+		}
+	}
+}
+
+static inline enum uart_config_flow_control uart_silabs_ll2cfg_hwctrl(
+	USART_HwFlowControl_TypeDef fc)
+{
+	if (fc == usartHwFlowControlCtsAndRts) {
+		return UART_CFG_FLOW_CTRL_RTS_CTS;
+	}
+
+	return UART_CFG_FLOW_CTRL_NONE;
+}
+
+static void uart_silabs_configure_peripheral(const struct device *dev, bool enable)
+{
+	const struct uart_silabs_config *config = dev->config;
+	const struct uart_silabs_data *data = dev->data;
+	USART_InitAsync_TypeDef usartInit = USART_INITASYNC_DEFAULT;
+
+	usartInit.baudrate = data->uart_cfg->baudrate;
+	usartInit.parity = uart_silabs_cfg2ll_parity(data->uart_cfg->parity);
+	usartInit.stopbits = uart_silabs_cfg2ll_stopbits(data->uart_cfg->stop_bits);
+	usartInit.databits = uart_silabs_cfg2ll_databits(data->uart_cfg->data_bits,
+							 data->uart_cfg->parity);
+	usartInit.hwFlowControl = uart_silabs_cfg2ll_hwctrl(data->uart_cfg->flow_ctrl);
+	usartInit.enable = enable ? usartEnable : usartDisable;
+
+	USART_InitAsync(config->base, &usartInit);
+}
+
+#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
+static int uart_silabs_configure(const struct device *dev,
+				const struct uart_config *cfg)
+{
+	const struct uart_silabs_config *config = dev->config;
+	USART_TypeDef *base = config->base;
+	struct uart_silabs_data *data = dev->data;
+
+#ifdef CONFIG_UART_SILABS_USART_ASYNC
+	if (data->dma_rx.enabled || data->dma_tx.enabled) {
+		return -EBUSY;
+	}
+#endif
+
+	if ((cfg->parity == UART_CFG_PARITY_MARK) ||
+	    (cfg->parity == UART_CFG_PARITY_SPACE)) {
+		return -ENOSYS;
+	}
+
+	if (cfg->flow_ctrl == UART_CFG_FLOW_CTRL_DTR_DSR ||
+	    cfg->flow_ctrl == UART_CFG_FLOW_CTRL_RS485) {
+		return -ENOSYS;
+	}
+
+	*data->uart_cfg = *cfg;
+	USART_Enable(base, usartDisable);
+
+	uart_silabs_configure_peripheral(dev, true);
+
+	return 0;
+};
+
+static int uart_silabs_config_get(const struct device *dev,
+				 struct uart_config *cfg)
+{
+	struct uart_silabs_data *data = dev->data;
+	struct uart_config *uart_cfg = data->uart_cfg;
+
+	cfg->baudrate = uart_cfg->baudrate;
+	cfg->parity = uart_cfg->parity;
+	cfg->stop_bits = uart_cfg->stop_bits;
+	cfg->data_bits = uart_cfg->data_bits;
+	cfg->flow_ctrl = uart_cfg->flow_ctrl;
+
+	return 0;
+}
+#endif /* CONFIG_UART_USE_RUNTIME_CONFIGURE */
+
+static int uart_silabs_init(const struct device *dev)
+{
+	int err;
+	const struct uart_silabs_config *config = dev->config;
+
+	/* The peripheral and gpio clock are already enabled from soc and gpio driver */
+	/* Enable USART clock */
+	err = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_cfg);
+	if (err < 0) {
+		return err;
+	}
+
+	uart_silabs_configure_peripheral(dev, false);
+
+	config->irq_config_func(dev);
+
+#ifdef CONFIG_UART_SILABS_USART_ASYNC
+	err = uart_silabs_async_init(dev);
+	if (err < 0) {
+		return err;
+	}
+#endif
+	return pm_device_driver_init(dev, uart_silabs_pm_action);
+}
+
+static int uart_silabs_pm_action(const struct device *dev, enum pm_device_action action)
+{
+	int err;
+	const struct uart_silabs_config *config = dev->config;
+	__maybe_unused struct uart_silabs_data *data = dev->data;
+
+	if (action == PM_DEVICE_ACTION_RESUME) {
+		err = clock_control_on(config->clock_dev,
+				       (clock_control_subsys_t)&config->clock_cfg);
+		if (err < 0 && err != -EALREADY) {
+			return err;
+		}
+
+		err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+		if (err < 0) {
+			return err;
+		}
+
+		USART_Enable(config->base, usartEnable);
+	} else if (IS_ENABLED(CONFIG_PM_DEVICE) && (action == PM_DEVICE_ACTION_SUSPEND)) {
+#ifdef CONFIG_UART_SILABS_USART_ASYNC
+		/* Entering suspend requires there to be no active asynchronous calls. */
+		__ASSERT_NO_MSG(!data->dma_rx.enabled);
+		__ASSERT_NO_MSG(!data->dma_tx.enabled);
+#endif
+		USART_Enable(config->base, usartDisable);
+
+		err = clock_control_off(config->clock_dev,
+					(clock_control_subsys_t)&config->clock_cfg);
+		if (err < 0) {
+			return err;
+		}
+
+		err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
+		if (err < 0 && err != -ENOENT) {
+			return err;
+		}
+
+	} else {
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(uart, uart_silabs_driver_api) = {
+	.poll_in = uart_silabs_poll_in,
+	.poll_out = uart_silabs_poll_out,
+	.err_check = uart_silabs_err_check,
+#ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
+	.configure = uart_silabs_configure,
+	.config_get = uart_silabs_config_get,
+#endif
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	.fifo_fill = uart_silabs_fifo_fill,
+	.fifo_read = uart_silabs_fifo_read,
+	.irq_tx_enable = uart_silabs_irq_tx_enable,
+	.irq_tx_disable = uart_silabs_irq_tx_disable,
+	.irq_tx_complete = uart_silabs_irq_tx_complete,
+	.irq_tx_ready = uart_silabs_irq_tx_ready,
+	.irq_rx_enable = uart_silabs_irq_rx_enable,
+	.irq_rx_disable = uart_silabs_irq_rx_disable,
+	.irq_rx_ready = uart_silabs_irq_rx_ready,
+	.irq_err_enable = uart_silabs_irq_err_enable,
+	.irq_err_disable = uart_silabs_irq_err_disable,
+	.irq_is_pending = uart_silabs_irq_is_pending,
+	.irq_update = uart_silabs_irq_update,
+	.irq_callback_set = uart_silabs_irq_callback_set,
+#endif
+#ifdef CONFIG_UART_SILABS_USART_ASYNC
+	.callback_set = uart_silabs_async_callback_set,
+	.tx = uart_silabs_async_tx,
+	.tx_abort = uart_silabs_async_tx_abort,
+	.rx_enable = uart_silabs_async_rx_enable,
+	.rx_disable = uart_silabs_async_rx_disable,
+	.rx_buf_rsp = uart_silabs_async_rx_buf_rsp,
+#endif
+};
+
+#ifdef CONFIG_UART_SILABS_USART_ASYNC
+
+#define UART_DMA_CHANNEL_INIT(index, dir)                                                          \
+	.dma_##dir = {                                                                             \
+		.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(index, dir)),                   \
+		.dma_cfg = {                                                                       \
+			.dma_slot = SILABS_LDMA_REQSEL_TO_SLOT(                                    \
+				    DT_INST_DMAS_CELL_BY_NAME(index, dir, slot)),                  \
+			.source_data_size = 1,                                                     \
+			.dest_data_size = 1,                                                       \
+			.source_burst_length = 1,                                                  \
+			.dest_burst_length = 1,                                                    \
+			.dma_callback = uart_silabs_dma_##dir##_cb,                                \
+		}                                                                                  \
+	},
+#define UART_DMA_CHANNEL(index, dir)                                                               \
+	COND_CODE_1(DT_INST_NODE_HAS_PROP(index, dmas),                                            \
+		 (UART_DMA_CHANNEL_INIT(index, dir)), ())
+#else
+
+#define UART_DMA_CHANNEL(index, dir)
+
+#endif
+
+#define SILABS_USART_IRQ_HANDLER_FUNC(idx) .irq_config_func = usart_silabs_config_func_##idx,
+#define SILABS_USART_IRQ_HANDLER(idx)                                                              \
+	static void usart_silabs_config_func_##idx(const struct device *dev)                       \
+	{                                                                                          \
+		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, rx, irq),                                     \
+			    DT_INST_IRQ_BY_NAME(idx, rx, priority), uart_silabs_isr,               \
+			    DEVICE_DT_INST_GET(idx), 0);                                           \
+		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(idx, tx, irq),                                     \
+			    DT_INST_IRQ_BY_NAME(idx, tx, priority), uart_silabs_isr,               \
+			    DEVICE_DT_INST_GET(idx), 0);                                           \
+                                                                                                   \
+		irq_enable(DT_INST_IRQ_BY_NAME(idx, rx, irq));                                     \
+		irq_enable(DT_INST_IRQ_BY_NAME(idx, tx, irq));                                     \
+	}
+
+#define SILABS_USART_INIT(idx)                                                                     \
+	SILABS_USART_IRQ_HANDLER(idx);                                                             \
+	PINCTRL_DT_INST_DEFINE(idx);                                                               \
+	PM_DEVICE_DT_INST_DEFINE(idx, uart_silabs_pm_action);                                      \
+                                                                                                   \
+	static struct uart_config uart_cfg_##idx = {                                               \
+		.baudrate = DT_INST_PROP(idx, current_speed),                                      \
+		.parity = DT_INST_ENUM_IDX(idx, parity),                                           \
+		.stop_bits = DT_INST_ENUM_IDX(idx, stop_bits),                                     \
+		.data_bits = DT_INST_ENUM_IDX(idx, data_bits),                                     \
+		.flow_ctrl = DT_INST_PROP(idx, hw_flow_control) ? UART_CFG_FLOW_CTRL_RTS_CTS       \
+								: UART_CFG_FLOW_CTRL_NONE,         \
+	};                                                                                         \
+                                                                                                   \
+	static const struct uart_silabs_config uart_silabs_cfg_##idx = {                           \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx),                                       \
+		.base = (USART_TypeDef *)DT_INST_REG_ADDR(idx),                                    \
+		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)),                              \
+		.clock_cfg = SILABS_DT_INST_CLOCK_CFG(idx),                                        \
+		SILABS_USART_IRQ_HANDLER_FUNC(idx)                                                 \
+	};                                                                                         \
+                                                                                                   \
+	static struct uart_silabs_data uart_silabs_data_##idx = {                                  \
+		.uart_cfg = &uart_cfg_##idx,                                                       \
+		UART_DMA_CHANNEL(idx, rx)                                                          \
+		UART_DMA_CHANNEL(idx, tx)                                                          \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(idx, uart_silabs_init, PM_DEVICE_DT_INST_GET(idx),                   \
+			      &uart_silabs_data_##idx, &uart_silabs_cfg_##idx, PRE_KERNEL_1,       \
+			      CONFIG_SERIAL_INIT_PRIORITY, &uart_silabs_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(SILABS_USART_INIT)
diff --git a/drivers/serial/uart_stm32.c b/drivers/serial/uart_stm32.c
index d0c511b3b4a..f1e560dba9c 100644
--- a/drivers/serial/uart_stm32.c
+++ b/drivers/serial/uart_stm32.c
@@ -39,11 +39,9 @@
 #include <stm32_ll_exti.h>
 #endif /* CONFIG_PM */
 
-#ifdef CONFIG_DCACHE
 #include <zephyr/linker/linker-defs.h>
 #include <zephyr/mem_mgmt/mem_attr.h>
 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
-#endif /* CONFIG_DCACHE */
 
 #include <zephyr/logging/log.h>
 #include <zephyr/irq.h>
@@ -99,17 +97,34 @@ uint32_t lpuartdiv_calc(const uint64_t clock_rate, const uint32_t baud_rate)
 #endif /* USART_PRESC_PRESCALER */
 #endif /* HAS_LPUART */
 
+#ifdef CONFIG_UART_ASYNC_API
+#define STM32_ASYNC_STATUS_TIMEOUT (DMA_STATUS_BLOCK + 1)
+#endif
+
 #ifdef CONFIG_PM
+static void uart_stm32_pm_policy_state_lock_get_unconditional(void)
+{
+	pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
+	if (IS_ENABLED(CONFIG_PM_S2RAM)) {
+		pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_RAM, PM_ALL_SUBSTATES);
+	}
+}
+
 static void uart_stm32_pm_policy_state_lock_get(const struct device *dev)
 {
 	struct uart_stm32_data *data = dev->data;
 
 	if (!data->pm_policy_state_on) {
 		data->pm_policy_state_on = true;
-		pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
-		if (IS_ENABLED(CONFIG_PM_S2RAM)) {
-			pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_RAM, PM_ALL_SUBSTATES);
-		}
+		uart_stm32_pm_policy_state_lock_get_unconditional();
+	}
+}
+
+static void uart_stm32_pm_policy_state_lock_put_unconditional(void)
+{
+	pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
+	if (IS_ENABLED(CONFIG_PM_S2RAM)) {
+		pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_RAM, PM_ALL_SUBSTATES);
 	}
 }
 
@@ -119,10 +134,7 @@ static void uart_stm32_pm_policy_state_lock_put(const struct device *dev)
 
 	if (data->pm_policy_state_on) {
 		data->pm_policy_state_on = false;
-		pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
-		if (IS_ENABLED(CONFIG_PM_S2RAM)) {
-			pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_RAM, PM_ALL_SUBSTATES);
-		}
+		uart_stm32_pm_policy_state_lock_put_unconditional();
 	}
 }
 #endif /* CONFIG_PM */
@@ -1117,11 +1129,16 @@ static inline void async_evt_rx_rdy(struct uart_stm32_data *data)
 		.data.rx.offset = data->dma_rx.offset
 	};
 
-	/* update the current pos for new data */
-	data->dma_rx.offset = data->dma_rx.counter;
+	/* When cyclic DMA is used, buffer positions are not updated - call callback every time*/
+	if (data->dma_rx.dma_cfg.cyclic == 0) {
+		/* update the current pos for new data */
+		data->dma_rx.offset = data->dma_rx.counter;
 
-	/* send event only for new data */
-	if (event.data.rx.len > 0) {
+		/* send event only for new data */
+		if (event.data.rx.len > 0) {
+			async_user_callback(data, &event);
+		}
+	} else {
 		async_user_callback(data, &event);
 	}
 }
@@ -1154,6 +1171,9 @@ static inline void async_evt_tx_done(struct uart_stm32_data *data)
 	/* Reset tx buffer */
 	data->dma_tx.buffer_length = 0;
 	data->dma_tx.counter = 0;
+#ifdef CONFIG_PM
+	data->tx_int_stream_on = false;
+#endif
 
 	async_user_callback(data, &event);
 }
@@ -1171,6 +1191,9 @@ static inline void async_evt_tx_abort(struct uart_stm32_data *data)
 	/* Reset tx buffer */
 	data->dma_tx.buffer_length = 0;
 	data->dma_tx.counter = 0;
+#ifdef CONFIG_PM
+	data->tx_int_stream_on = false;
+#endif
 
 	async_user_callback(data, &event);
 }
@@ -1204,20 +1227,45 @@ static inline void async_timer_start(struct k_work_delayable *work,
 	}
 }
 
-static void uart_stm32_dma_rx_flush(const struct device *dev)
+static void uart_stm32_dma_rx_flush(const struct device *dev, int status)
 {
 	struct dma_status stat;
 	struct uart_stm32_data *data = dev->data;
 
-	if (dma_get_status(data->dma_rx.dma_dev,
-				data->dma_rx.dma_channel, &stat) == 0) {
-		size_t rx_rcv_len = data->dma_rx.buffer_length -
-					stat.pending_length;
-		if (rx_rcv_len > data->dma_rx.offset) {
-			data->dma_rx.counter = rx_rcv_len;
+	size_t rx_rcv_len = 0;
 
-			async_evt_rx_rdy(data);
+	switch (status) {
+	case DMA_STATUS_COMPLETE:
+		/* fully complete */
+		data->dma_rx.counter = data->dma_rx.buffer_length;
+		break;
+	case DMA_STATUS_BLOCK:
+		/* half complete */
+		data->dma_rx.counter = data->dma_rx.buffer_length / 2;
+
+		break;
+	default: /* likely STM32_ASYNC_STATUS_TIMEOUT */
+		if (dma_get_status(data->dma_rx.dma_dev, data->dma_rx.dma_channel, &stat) == 0) {
+			rx_rcv_len = data->dma_rx.buffer_length - stat.pending_length;
+			data->dma_rx.counter = rx_rcv_len;
 		}
+		break;
+	}
+
+	async_evt_rx_rdy(data);
+
+	switch (status) { /* update offset*/
+	case DMA_STATUS_COMPLETE:
+		/* fully complete */
+		data->dma_rx.offset = 0;
+		break;
+	case DMA_STATUS_BLOCK:
+		/* half complete */
+		data->dma_rx.offset = data->dma_rx.buffer_length / 2;
+		break;
+	default: /* likely STM32_ASYNC_STATUS_TIMEOUT */
+		data->dma_rx.offset += rx_rcv_len - data->dma_rx.offset;
+		break;
 	}
 }
 
@@ -1260,6 +1308,26 @@ static void uart_stm32_isr(const struct device *dev)
 	}
 #endif /* CONFIG_UART_INTERRUPT_DRIVEN */
 
+#if defined(CONFIG_PM) && defined(IS_UART_WAKEUP_FROMSTOP_INSTANCE) \
+	&& defined(USART_CR3_WUFIE)
+	if (LL_USART_IsEnabledIT_WKUP(usart) &&
+		LL_USART_IsActiveFlag_WKUP(usart)) {
+
+		LL_USART_ClearFlag_WKUP(usart);
+
+		if (!data->rx_woken) {
+			/* Prevent SoC from entering STOP mode until RX goes IDLE */
+			uart_stm32_pm_policy_state_lock_get_unconditional();
+			data->rx_woken = true;
+		}
+
+#ifdef USART_ISR_REACK
+		while (LL_USART_IsActiveFlag_REACK(usart) == 0) {
+		}
+#endif
+	}
+#endif
+
 #ifdef CONFIG_UART_ASYNC_API
 	if (LL_USART_IsEnabledIT_IDLE(usart) &&
 			LL_USART_IsActiveFlag_IDLE(usart)) {
@@ -1268,8 +1336,16 @@ static void uart_stm32_isr(const struct device *dev)
 
 		LOG_DBG("idle interrupt occurred");
 
+#ifdef CONFIG_PM
+		if (data->rx_woken) {
+			/* Allow SoC to enter STOP mode now that RX is IDLE */
+			uart_stm32_pm_policy_state_lock_put_unconditional();
+			data->rx_woken = false;
+		}
+#endif
+
 		if (data->dma_rx.timeout == 0) {
-			uart_stm32_dma_rx_flush(dev);
+			uart_stm32_dma_rx_flush(dev, STM32_ASYNC_STATUS_TIMEOUT);
 		} else {
 			/* Start the RX timer not null */
 			async_timer_start(&data->dma_rx.timeout_work,
@@ -1281,9 +1357,8 @@ static void uart_stm32_isr(const struct device *dev)
 		LL_USART_DisableIT_TC(usart);
 		/* Generate TX_DONE event when transmission is done */
 		async_evt_tx_done(data);
-
 #ifdef CONFIG_PM
-		uart_stm32_pm_policy_state_lock_put(dev);
+		uart_stm32_pm_policy_state_lock_put_unconditional();
 #endif
 	} else if (LL_USART_IsEnabledIT_RXNE(usart) &&
 			LL_USART_IsActiveFlag_RXNE(usart)) {
@@ -1300,18 +1375,6 @@ static void uart_stm32_isr(const struct device *dev)
 	uart_stm32_err_check(dev);
 #endif /* CONFIG_UART_ASYNC_API */
 
-#if defined(CONFIG_PM) && defined(IS_UART_WAKEUP_FROMSTOP_INSTANCE) \
-	&& defined(USART_CR3_WUFIE)
-	if (LL_USART_IsEnabledIT_WKUP(usart) &&
-		LL_USART_IsActiveFlag_WKUP(usart)) {
-
-		LL_USART_ClearFlag_WKUP(usart);
-#ifdef USART_ISR_REACK
-		while (LL_USART_IsActiveFlag_REACK(usart) == 0) {
-		}
-#endif
-	}
-#endif
 }
 #endif /* CONFIG_UART_INTERRUPT_DRIVEN || CONFIG_UART_ASYNC_API || CONFIG_PM */
 
@@ -1330,11 +1393,13 @@ static bool buf_in_nocache(uintptr_t buf, size_t len_bytes)
 	}
 #endif /* CONFIG_NOCACHE_MEMORY */
 
+#ifdef CONFIG_MEM_ATTR
 	buf_within_nocache = mem_attr_check_buf(
 		(void *)buf, len_bytes, DT_MEM_ARM_MPU_RAM_NOCACHE) == 0;
 	if (buf_within_nocache) {
 		return true;
 	}
+#endif /* CONFIG_MEM_ATTR */
 
 	buf_within_nocache = (buf >= ((uintptr_t)__rodata_region_start)) &&
 		((buf + len_bytes - 1) <= ((uintptr_t)__rodata_region_end));
@@ -1417,7 +1482,7 @@ static int uart_stm32_async_rx_disable(const struct device *dev)
 
 	LL_USART_DisableIT_IDLE(usart);
 
-	uart_stm32_dma_rx_flush(dev);
+	uart_stm32_dma_rx_flush(dev, STM32_ASYNC_STATUS_TIMEOUT);
 
 	async_evt_rx_buf_release(data);
 
@@ -1517,27 +1582,32 @@ void uart_stm32_dma_rx_cb(const struct device *dma_dev, void *user_data,
 
 	(void)k_work_cancel_delayable(&data->dma_rx.timeout_work);
 
-	/* true since this functions occurs when buffer if full */
-	data->dma_rx.counter = data->dma_rx.buffer_length;
+	/* If we are in NORMAL MODE */
+	if (data->dma_rx.dma_cfg.cyclic == 0) {
 
-	async_evt_rx_rdy(data);
+		/* true since this functions occurs when buffer is full */
+		data->dma_rx.counter = data->dma_rx.buffer_length;
+		async_evt_rx_rdy(data);
+		if (data->rx_next_buffer != NULL) {
+			async_evt_rx_buf_release(data);
 
-	if (data->rx_next_buffer != NULL) {
-		async_evt_rx_buf_release(data);
-
-		/* replace the buffer when the current
-		 * is full and not the same as the next
-		 * one.
-		 */
-		uart_stm32_dma_replace_buffer(uart_dev);
+			/* replace the buffer when the current
+			 * is full and not the same as the next
+			 * one.
+			 */
+			uart_stm32_dma_replace_buffer(uart_dev);
+		} else {
+			/* Buffer full without valid next buffer,
+			 * an UART_RX_DISABLED event must be generated,
+			 * but uart_stm32_async_rx_disable() cannot be
+			 * called in ISR context. So force the RX timeout
+			 * to minimum value and let the RX timeout to do the job.
+			 */
+			k_work_reschedule(&data->dma_rx.timeout_work, K_TICKS(1));
+		}
 	} else {
-		/* Buffer full without valid next buffer,
-		 * an UART_RX_DISABLED event must be generated,
-		 * but uart_stm32_async_rx_disable() cannot be
-		 * called in ISR context. So force the RX timeout
-		 * to minimum value and let the RX timeout to do the job.
-		 */
-		k_work_reschedule(&data->dma_rx.timeout_work, K_TICKS(1));
+		/* CIRCULAR MODE */
+		uart_stm32_dma_rx_flush(data->uart_dev, status);
 	}
 }
 
@@ -1564,6 +1634,10 @@ static int uart_stm32_async_tx(const struct device *dev,
 	}
 #endif /* CONFIG_DCACHE */
 
+#ifdef CONFIG_PM
+	data->tx_poll_stream_on = false;
+	data->tx_int_stream_on = true;
+#endif
 	data->dma_tx.buffer = (uint8_t *)tx_data;
 	data->dma_tx.buffer_length = buf_size;
 	data->dma_tx.timeout = timeout;
@@ -1599,7 +1673,7 @@ static int uart_stm32_async_tx(const struct device *dev,
 #ifdef CONFIG_PM
 
 	/* Do not allow system to suspend until transmission has completed */
-	uart_stm32_pm_policy_state_lock_get(dev);
+	uart_stm32_pm_policy_state_lock_get_unconditional();
 #endif
 
 	/* Enable TX DMA requests */
@@ -1722,7 +1796,7 @@ static void uart_stm32_async_rx_timeout(struct k_work *work)
 	if (data->dma_rx.counter == data->dma_rx.buffer_length) {
 		uart_stm32_async_rx_disable(dev);
 	} else {
-		uart_stm32_dma_rx_flush(dev);
+		uart_stm32_dma_rx_flush(dev, STM32_ASYNC_STATUS_TIMEOUT);
 	}
 }
 
@@ -1829,9 +1903,10 @@ static int uart_stm32_async_init(const struct device *dev)
 		data->dma_rx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
 	}
 
-	/* RX disable circular buffer */
-	data->dma_rx.blk_cfg.source_reload_en  = 0;
-	data->dma_rx.blk_cfg.dest_reload_en = 0;
+	/* Enable/disable RX circular buffer */
+	data->dma_rx.blk_cfg.source_reload_en = data->dma_rx.dma_cfg.cyclic;
+	data->dma_rx.blk_cfg.dest_reload_en = data->dma_rx.dma_cfg.cyclic;
+
 	data->dma_rx.blk_cfg.fifo_mode_control = data->dma_rx.fifo_threshold;
 
 	data->dma_rx.dma_cfg.head_block = &data->dma_rx.blk_cfg;
@@ -1868,6 +1943,10 @@ static int uart_stm32_async_init(const struct device *dev)
 		data->dma_tx.blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
 	}
 
+	/* Enable/disable TX circular buffer */
+	data->dma_tx.blk_cfg.source_reload_en = data->dma_tx.dma_cfg.cyclic;
+	data->dma_tx.blk_cfg.dest_reload_en = data->dma_tx.dma_cfg.cyclic;
+
 	data->dma_tx.blk_cfg.fifo_mode_control = data->dma_tx.fifo_threshold;
 
 	data->dma_tx.dma_cfg.head_block = &data->dma_tx.blk_cfg;
@@ -2225,6 +2304,8 @@ static int uart_stm32_pm_action(const struct device *dev,
 		.dma_slot = STM32_DMA_SLOT(index, dir, slot),\
 		.channel_direction = STM32_DMA_CONFIG_DIRECTION(	\
 					STM32_DMA_CHANNEL_CONFIG(index, dir)),\
+		.cyclic =  STM32_DMA_CONFIG_CYCLIC(			\
+				STM32_DMA_CHANNEL_CONFIG(index, dir)),  \
 		.channel_priority = STM32_DMA_CONFIG_PRIORITY(		\
 				STM32_DMA_CHANNEL_CONFIG(index, dir)),	\
 		.source_data_size = STM32_DMA_CONFIG_##src_dev##_DATA_SIZE(\
@@ -2299,18 +2380,13 @@ static void uart_stm32_irq_config_func_##index(const struct device *dev)	\
  */
 #define STM32_UART_CHECK_DT_PARITY(index)				\
 BUILD_ASSERT(								\
-	!(DT_INST_ENUM_IDX_OR(index, parity, STM32_UART_DEFAULT_PARITY)	\
-					== UART_CFG_PARITY_MARK ||	\
-	DT_INST_ENUM_IDX_OR(index, parity, STM32_UART_DEFAULT_PARITY)	\
-					== UART_CFG_PARITY_SPACE),	\
+	!(DT_INST_ENUM_IDX(index, parity) == UART_CFG_PARITY_MARK ||	\
+	DT_INST_ENUM_IDX(index, parity) == UART_CFG_PARITY_SPACE),	\
 	"Node " DT_NODE_PATH(DT_DRV_INST(index))			\
 	" has unsupported parity configuration");			\
 BUILD_ASSERT(								\
-	!(DT_INST_ENUM_IDX_OR(index, parity, STM32_UART_DEFAULT_PARITY)	\
-					!= UART_CFG_PARITY_NONE	&&	\
-	DT_INST_ENUM_IDX_OR(index, data_bits,				\
-			    STM32_UART_DEFAULT_DATA_BITS)		\
-					== UART_CFG_DATA_BITS_9),	\
+	!(DT_INST_ENUM_IDX(index, parity) != UART_CFG_PARITY_NONE &&	\
+	DT_INST_ENUM_IDX(index, data_bits) == UART_CFG_DATA_BITS_9),	\
 	"Node " DT_NODE_PATH(DT_DRV_INST(index))			\
 		" has unsupported parity + data bits combination");
 
@@ -2321,32 +2397,18 @@ BUILD_ASSERT(								\
 #ifdef LL_USART_DATAWIDTH_7B
 #define STM32_UART_CHECK_DT_DATA_BITS(index)				\
 BUILD_ASSERT(								\
-	!(DT_INST_ENUM_IDX_OR(index, data_bits,				\
-			      STM32_UART_DEFAULT_DATA_BITS)		\
-					== UART_CFG_DATA_BITS_5 ||	\
-		(DT_INST_ENUM_IDX_OR(index, data_bits,			\
-				    STM32_UART_DEFAULT_DATA_BITS)	\
-					== UART_CFG_DATA_BITS_6 &&	\
-		DT_INST_ENUM_IDX_OR(index, parity,			\
-				    STM32_UART_DEFAULT_PARITY)		\
-					== UART_CFG_PARITY_NONE)),	\
+	!(DT_INST_ENUM_IDX(index, data_bits) == UART_CFG_DATA_BITS_5 ||	\
+	(DT_INST_ENUM_IDX(index, data_bits) == UART_CFG_DATA_BITS_6 &&	\
+	DT_INST_ENUM_IDX(index, parity) == UART_CFG_PARITY_NONE)),	\
 	"Node " DT_NODE_PATH(DT_DRV_INST(index))			\
 		" has unsupported data bits configuration");
 #else
 #define STM32_UART_CHECK_DT_DATA_BITS(index)				\
 BUILD_ASSERT(								\
-	!(DT_INST_ENUM_IDX_OR(index, data_bits,				\
-			      STM32_UART_DEFAULT_DATA_BITS)		\
-					== UART_CFG_DATA_BITS_5 ||	\
-	DT_INST_ENUM_IDX_OR(index, data_bits,				\
-			    STM32_UART_DEFAULT_DATA_BITS)		\
-					== UART_CFG_DATA_BITS_6 ||	\
-		(DT_INST_ENUM_IDX_OR(index, data_bits,			\
-			    STM32_UART_DEFAULT_DATA_BITS)		\
-					== UART_CFG_DATA_BITS_7 &&	\
-		DT_INST_ENUM_IDX_OR(index, parity,			\
-				    STM32_UART_DEFAULT_PARITY)		\
-					== UART_CFG_PARITY_NONE)),	\
+	!(DT_INST_ENUM_IDX(index, data_bits) == UART_CFG_DATA_BITS_5 ||	\
+	DT_INST_ENUM_IDX(index, data_bits) == UART_CFG_DATA_BITS_6 ||	\
+	(DT_INST_ENUM_IDX(index, data_bits) == UART_CFG_DATA_BITS_7 &&	\
+	DT_INST_ENUM_IDX(index, parity) == UART_CFG_PARITY_NONE)),	\
 	"Node " DT_NODE_PATH(DT_DRV_INST(index))			\
 		" has unsupported data bits configuration");
 #endif
@@ -2358,9 +2420,7 @@ BUILD_ASSERT(								\
 #ifndef LL_USART_STOPBITS_0_5
 #define STM32_UART_CHECK_DT_STOP_BITS_0_5(index)			\
 BUILD_ASSERT(								\
-	!(DT_INST_ENUM_IDX_OR(index, stop_bits,				\
-			      STM32_UART_DEFAULT_STOP_BITS)		\
-					== UART_CFG_STOP_BITS_0_5),	\
+	DT_INST_ENUM_IDX(index, stop_bits) != UART_CFG_STOP_BITS_0_5,	\
 	"Node " DT_NODE_PATH(DT_DRV_INST(index))			\
 		" has unsupported stop bits configuration");
 /* LPUARTs don't support 0.5 stop bits configurations */
@@ -2368,9 +2428,7 @@ BUILD_ASSERT(								\
 #define STM32_UART_CHECK_DT_STOP_BITS_0_5(index)			\
 BUILD_ASSERT(								\
 	!(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_lpuart) &&			\
-	  DT_INST_ENUM_IDX_OR(index, stop_bits,				\
-			      STM32_UART_DEFAULT_STOP_BITS)		\
-					== UART_CFG_STOP_BITS_0_5),	\
+	DT_INST_ENUM_IDX(index, stop_bits) == UART_CFG_STOP_BITS_0_5),	\
 	"Node " DT_NODE_PATH(DT_DRV_INST(index))			\
 		" has unsupported stop bits configuration");
 #endif
@@ -2382,9 +2440,7 @@ BUILD_ASSERT(								\
 #ifndef LL_USART_STOPBITS_1_5
 #define STM32_UART_CHECK_DT_STOP_BITS_1_5(index)			\
 BUILD_ASSERT(								\
-	DT_INST_ENUM_IDX_OR(index, stop_bits,				\
-			    STM32_UART_DEFAULT_STOP_BITS)		\
-					!= UART_CFG_STOP_BITS_1_5,	\
+	DT_INST_ENUM_IDX(index, stop_bits) != UART_CFG_STOP_BITS_1_5,	\
 	"Node " DT_NODE_PATH(DT_DRV_INST(index))			\
 		" has unsupported stop bits configuration");
 /* LPUARTs don't support 1.5 stop bits configurations */
@@ -2392,9 +2448,7 @@ BUILD_ASSERT(								\
 #define STM32_UART_CHECK_DT_STOP_BITS_1_5(index)			\
 BUILD_ASSERT(								\
 	!(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_lpuart) &&			\
-	  DT_INST_ENUM_IDX_OR(index, stop_bits,				\
-			      STM32_UART_DEFAULT_STOP_BITS)		\
-					== UART_CFG_STOP_BITS_1_5),	\
+	DT_INST_ENUM_IDX(index, stop_bits) == UART_CFG_STOP_BITS_1_5),	\
 	"Node " DT_NODE_PATH(DT_DRV_INST(index))			\
 		" has unsupported stop bits configuration");
 #endif
@@ -2408,14 +2462,10 @@ static const struct stm32_pclken pclken_##index[] =			\
 					    STM32_DT_INST_CLOCKS(index);\
 									\
 static struct uart_config uart_cfg_##index = {				\
-	.baudrate  = DT_INST_PROP_OR(index, current_speed,		\
-				     STM32_UART_DEFAULT_BAUDRATE),	\
-	.parity    = DT_INST_ENUM_IDX_OR(index, parity,			\
-					 STM32_UART_DEFAULT_PARITY),	\
-	.stop_bits = DT_INST_ENUM_IDX_OR(index, stop_bits,		\
-					 STM32_UART_DEFAULT_STOP_BITS),	\
-	.data_bits = DT_INST_ENUM_IDX_OR(index, data_bits,		\
-					 STM32_UART_DEFAULT_DATA_BITS),	\
+	.baudrate = DT_INST_PROP(index, current_speed),			\
+	.parity = DT_INST_ENUM_IDX(index, parity),			\
+	.stop_bits = DT_INST_ENUM_IDX(index, stop_bits),		\
+	.data_bits = DT_INST_ENUM_IDX(index, data_bits),		\
 	.flow_ctrl = DT_INST_PROP(index, hw_flow_control)		\
 					? UART_CFG_FLOW_CTRL_RTS_CTS	\
 					: UART_CFG_FLOW_CTRL_NONE,	\
diff --git a/drivers/serial/uart_stm32.h b/drivers/serial/uart_stm32.h
index 7c6f432a504..d50dbc77c0d 100644
--- a/drivers/serial/uart_stm32.h
+++ b/drivers/serial/uart_stm32.h
@@ -18,11 +18,6 @@
 
 #include <stm32_ll_usart.h>
 
-#define STM32_UART_DEFAULT_BAUDRATE	115200
-#define STM32_UART_DEFAULT_PARITY	UART_CFG_PARITY_NONE
-#define STM32_UART_DEFAULT_STOP_BITS	UART_CFG_STOP_BITS_1
-#define STM32_UART_DEFAULT_DATA_BITS	UART_CFG_DATA_BITS_8
-
 /* device config */
 struct uart_stm32_config {
 	/* USART instance */
@@ -108,6 +103,7 @@ struct uart_stm32_data {
 	bool tx_poll_stream_on;
 	bool tx_int_stream_on;
 	bool pm_policy_state_on;
+	bool rx_woken;
 #endif
 };
 
diff --git a/drivers/serial/uart_sy1xx.c b/drivers/serial/uart_sy1xx.c
index 7bc4de39380..7027849b9bb 100644
--- a/drivers/serial/uart_sy1xx.c
+++ b/drivers/serial/uart_sy1xx.c
@@ -11,10 +11,12 @@
 #include <zephyr/sys/printk.h>
 #include <udma.h>
 #include <pad_ctrl.h>
+#include <zephyr/drivers/pinctrl.h>
 
 struct sy1xx_uart_config {
 	uint32_t base;
 	uint32_t inst;
+	const struct pinctrl_dev_config *pcfg;
 };
 
 typedef struct {
@@ -259,28 +261,11 @@ static int sy1xx_uart_init(const struct device *dev)
 	sy1xx_udma_enable_clock(SY1XX_UDMA_MODULE_UART, config->inst);
 
 	/* PAD config */
-	uint32_t pad_config_tx =
-		SY1XX_PAD_CONFIG(0, SY1XX_PAD_SMT_DISABLE, SY1XX_PAD_SLEW_LOW, SY1XX_PAD_PULLUP_DIS,
-				 SY1XX_PAD_PULLDOWN_DIS, SY1XX_PAD_DRIVE_2PF, SY1XX_PAD_PMOD_NORMAL,
-				 SY1XX_PAD_DIR_OUTPUT);
+	int32_t ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
 
-	uint32_t pad_config_rx =
-		SY1XX_PAD_CONFIG(8, SY1XX_PAD_SMT_DISABLE, SY1XX_PAD_SLEW_LOW, SY1XX_PAD_PULLUP_DIS,
-				 SY1XX_PAD_PULLDOWN_DIS, SY1XX_PAD_DRIVE_2PF, SY1XX_PAD_PMOD_NORMAL,
-				 SY1XX_PAD_DIR_INPUT);
-
-	uint32_t pad_config_cts =
-		SY1XX_PAD_CONFIG(16, SY1XX_PAD_SMT_DISABLE, SY1XX_PAD_SLEW_LOW, SY1XX_PAD_PULLUP_EN,
-				 SY1XX_PAD_PULLDOWN_DIS, SY1XX_PAD_DRIVE_2PF, SY1XX_PAD_PMOD_NORMAL,
-				 SY1XX_PAD_DIR_INPUT);
-
-	uint32_t pad_config_rts =
-		SY1XX_PAD_CONFIG(24, SY1XX_PAD_SMT_DISABLE, SY1XX_PAD_SLEW_LOW,
-				 SY1XX_PAD_PULLUP_DIS, SY1XX_PAD_PULLDOWN_DIS, SY1XX_PAD_DRIVE_2PF,
-				 SY1XX_PAD_PMOD_NORMAL, SY1XX_PAD_DIR_OUTPUT);
-
-	sys_write32((pad_config_tx | pad_config_rx | pad_config_cts | pad_config_rts),
-		    SY1XX_PAD_CONFIG_ADDR_UART + (config->inst * 4 + 0));
+	if (ret < 0) {
+		return ret;
+	}
 
 	sy1xx_uartConfig_t default_config = {
 		.baudrate = 1000000,
@@ -306,9 +291,12 @@ static DEVICE_API(uart, sy1xx_uart_driver_api) = {
 
 #define SYS1XX_UART_INIT(n)                                                                        \
                                                                                                    \
+	PINCTRL_DT_INST_DEFINE(n);                                                                 \
+                                                                                                   \
 	static const struct sy1xx_uart_config sy1xx_uart_##n##_cfg = {                             \
 		.base = (uint32_t)DT_INST_REG_ADDR(n),                                             \
 		.inst = (uint32_t)DT_INST_PROP(n, instance),                                       \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                         \
 	};                                                                                         \
                                                                                                    \
 	static struct sy1xx_uart_data __attribute__((section(".udma_access")))                     \
diff --git a/drivers/serial/uart_wch_usart.c b/drivers/serial/uart_wch_usart.c
index 169dc681fbe..720da6f17f5 100644
--- a/drivers/serial/uart_wch_usart.c
+++ b/drivers/serial/uart_wch_usart.c
@@ -274,7 +274,6 @@ static int usart_wch_irq_update(const struct device *dev)
 static void usart_wch_irq_callback_set(const struct device *dev, uart_irq_callback_user_data_t cb,
 				       void *user_data)
 {
-	const struct usart_wch_config *config = dev->config;
 	struct usart_wch_data *data = dev->data;
 
 	data->cb = cb;
@@ -313,7 +312,7 @@ static DEVICE_API(uart, usart_wch_driver_api) = {
 #define USART_WCH_IRQ_HANDLER(idx)                                                                 \
 	static void usart_wch_irq_config_func_##idx(const struct device *dev)                      \
 	{                                                                                          \
-		IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(index, priority), usart_wch_isr,        \
+		IRQ_CONNECT(DT_INST_IRQN(idx), DT_INST_IRQ(idx, priority), usart_wch_isr,        \
 			    DEVICE_DT_INST_GET(idx), 0);                                           \
 		irq_enable(DT_INST_IRQN(idx));                                                     \
 	}
@@ -330,7 +329,7 @@ static DEVICE_API(uart, usart_wch_driver_api) = {
 	static const struct usart_wch_config usart_wch_##idx##_config = {                          \
 		.regs = (USART_TypeDef *)DT_INST_REG_ADDR(idx),                                    \
 		.current_speed = DT_INST_PROP(idx, current_speed),                                 \
-		.parity = DT_INST_ENUM_IDX_OR(idx, parity, UART_CFG_PARITY_NONE),                  \
+		.parity = DT_INST_ENUM_IDX(idx, parity),                                           \
 		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)),                              \
 		.clock_id = DT_INST_CLOCKS_CELL(idx, id),                                          \
 		.pin_cfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx),                                    \
diff --git a/drivers/serial/uart_xlnx_ps.c b/drivers/serial/uart_xlnx_ps.c
index 122ac11a80d..c8aad9049c1 100644
--- a/drivers/serial/uart_xlnx_ps.c
+++ b/drivers/serial/uart_xlnx_ps.c
@@ -25,7 +25,6 @@
 #include <zephyr/kernel.h>
 #include <zephyr/arch/cpu.h>
 #include <zephyr/types.h>
-#include <soc.h>
 
 #include <zephyr/init.h>
 #include <zephyr/toolchain.h>
@@ -43,98 +42,98 @@
  */
 
 /* Register offsets within the UART device's register space */
-#define XUARTPS_CR_OFFSET	0x0000U  /**< Control Register [8:0] */
-#define XUARTPS_MR_OFFSET	0x0004U  /**< Mode Register [9:0] */
-#define XUARTPS_IER_OFFSET	0x0008U  /**< Interrupt Enable [12:0] */
-#define XUARTPS_IDR_OFFSET	0x000CU  /**< Interrupt Disable [12:0] */
-#define XUARTPS_IMR_OFFSET	0x0010U  /**< Interrupt Mask [12:0] */
-#define XUARTPS_ISR_OFFSET	0x0014U  /**< Interrupt Status [12:0]*/
-#define XUARTPS_BAUDGEN_OFFSET	0x0018U  /**< Baud Rate Generator [15:0] */
-#define XUARTPS_RXTOUT_OFFSET	0x001CU  /**< RX Timeout [7:0] */
-#define XUARTPS_RXWM_OFFSET	0x0020U  /**< RX FIFO Trigger Level [5:0] */
-#define XUARTPS_MODEMCR_OFFSET	0x0024U  /**< Modem Control [5:0] */
-#define XUARTPS_MODEMSR_OFFSET	0x0028U  /**< Modem Status [8:0] */
-#define XUARTPS_SR_OFFSET	0x002CU  /**< Channel Status [14:0] */
-#define XUARTPS_FIFO_OFFSET	0x0030U  /**< FIFO [7:0] */
-#define XUARTPS_BAUDDIV_OFFSET	0x0034U  /**< Baud Rate Divider [7:0] */
-#define XUARTPS_FLOWDEL_OFFSET	0x0038U  /**< Flow Delay [5:0] */
-#define XUARTPS_TXWM_OFFSET	0x0044U  /**< TX FIFO Trigger Level [5:0] */
-#define XUARTPS_RXBS_OFFSET	0x0048U  /**< RX FIFO Byte Status [11:0] */
+#define XUARTPS_CR_OFFSET      0x0000U /**< Control Register [8:0] */
+#define XUARTPS_MR_OFFSET      0x0004U /**< Mode Register [9:0] */
+#define XUARTPS_IER_OFFSET     0x0008U /**< Interrupt Enable [12:0] */
+#define XUARTPS_IDR_OFFSET     0x000CU /**< Interrupt Disable [12:0] */
+#define XUARTPS_IMR_OFFSET     0x0010U /**< Interrupt Mask [12:0] */
+#define XUARTPS_ISR_OFFSET     0x0014U /**< Interrupt Status [12:0]*/
+#define XUARTPS_BAUDGEN_OFFSET 0x0018U /**< Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET  0x001CU /**< RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET    0x0020U /**< RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET 0x0024U /**< Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET 0x0028U /**< Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET      0x002CU /**< Channel Status [14:0] */
+#define XUARTPS_FIFO_OFFSET    0x0030U /**< FIFO [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET 0x0034U /**< Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET 0x0038U /**< Flow Delay [5:0] */
+#define XUARTPS_TXWM_OFFSET    0x0044U /**< TX FIFO Trigger Level [5:0] */
+#define XUARTPS_RXBS_OFFSET    0x0048U /**< RX FIFO Byte Status [11:0] */
 
 /* Control Register Bits Definition */
-#define XUARTPS_CR_STOPBRK	0x00000100U  /**< Stop transmission of break */
-#define XUARTPS_CR_STARTBRK	0x00000080U  /**< Set break */
-#define XUARTPS_CR_TORST	0x00000040U  /**< RX timeout counter restart */
-#define XUARTPS_CR_TX_DIS	0x00000020U  /**< TX disabled. */
-#define XUARTPS_CR_TX_EN	0x00000010U  /**< TX enabled */
-#define XUARTPS_CR_RX_DIS	0x00000008U  /**< RX disabled. */
-#define XUARTPS_CR_RX_EN	0x00000004U  /**< RX enabled */
-#define XUARTPS_CR_EN_DIS_MASK	0x0000003CU  /**< Enable/disable Mask */
-#define XUARTPS_CR_TXRST	0x00000002U  /**< TX logic reset */
-#define XUARTPS_CR_RXRST	0x00000001U  /**< RX logic reset */
+#define XUARTPS_CR_STOPBRK     0x00000100U /**< Stop transmission of break */
+#define XUARTPS_CR_STARTBRK    0x00000080U /**< Set break */
+#define XUARTPS_CR_TORST       0x00000040U /**< RX timeout counter restart */
+#define XUARTPS_CR_TX_DIS      0x00000020U /**< TX disabled. */
+#define XUARTPS_CR_TX_EN       0x00000010U /**< TX enabled */
+#define XUARTPS_CR_RX_DIS      0x00000008U /**< RX disabled. */
+#define XUARTPS_CR_RX_EN       0x00000004U /**< RX enabled */
+#define XUARTPS_CR_EN_DIS_MASK 0x0000003CU /**< Enable/disable Mask */
+#define XUARTPS_CR_TXRST       0x00000002U /**< TX logic reset */
+#define XUARTPS_CR_RXRST       0x00000001U /**< RX logic reset */
 
 /* Mode Register Bits Definition */
-#define XUARTPS_MR_CCLK			0x00000400U /**< Input clock select */
-#define XUARTPS_MR_CHMODE_R_LOOP	0x00000300U /**< Remote loopback mode */
-#define XUARTPS_MR_CHMODE_L_LOOP	0x00000200U /**< Local loopback mode */
-#define XUARTPS_MR_CHMODE_ECHO		0x00000100U /**< Auto echo mode */
-#define XUARTPS_MR_CHMODE_NORM		0x00000000U /**< Normal mode */
-#define XUARTPS_MR_CHMODE_SHIFT		8U  /**< Mode shift */
-#define XUARTPS_MR_CHMODE_MASK		0x00000300U /**< Mode mask */
-#define XUARTPS_MR_STOPMODE_2_BIT	0x00000080U /**< 2 stop bits */
-#define XUARTPS_MR_STOPMODE_1_5_BIT	0x00000040U /**< 1.5 stop bits */
-#define XUARTPS_MR_STOPMODE_1_BIT	0x00000000U /**< 1 stop bit */
-#define XUARTPS_MR_STOPMODE_SHIFT	6U  /**< Stop bits shift */
-#define XUARTPS_MR_STOPMODE_MASK	0x000000A0U /**< Stop bits mask */
-#define XUARTPS_MR_PARITY_NONE		0x00000020U /**< No parity mode */
-#define XUARTPS_MR_PARITY_MARK		0x00000018U /**< Mark parity mode */
-#define XUARTPS_MR_PARITY_SPACE		0x00000010U /**< Space parity mode */
-#define XUARTPS_MR_PARITY_ODD		0x00000008U /**< Odd parity mode */
-#define XUARTPS_MR_PARITY_EVEN		0x00000000U /**< Even parity mode */
-#define XUARTPS_MR_PARITY_SHIFT		3U  /**< Parity setting shift */
-#define XUARTPS_MR_PARITY_MASK		0x00000038U /**< Parity mask */
-#define XUARTPS_MR_CHARLEN_6_BIT	0x00000006U /**< 6 bits data */
-#define XUARTPS_MR_CHARLEN_7_BIT	0x00000004U /**< 7 bits data */
-#define XUARTPS_MR_CHARLEN_8_BIT	0x00000000U /**< 8 bits data */
-#define XUARTPS_MR_CHARLEN_SHIFT	1U  /**< Data Length shift */
-#define XUARTPS_MR_CHARLEN_MASK		0x00000006U /**< Data length mask */
-#define XUARTPS_MR_CLKSEL		0x00000001U /**< Input clock select */
+#define XUARTPS_MR_CCLK             0x00000400U /**< Input clock select */
+#define XUARTPS_MR_CHMODE_R_LOOP    0x00000300U /**< Remote loopback mode */
+#define XUARTPS_MR_CHMODE_L_LOOP    0x00000200U /**< Local loopback mode */
+#define XUARTPS_MR_CHMODE_ECHO      0x00000100U /**< Auto echo mode */
+#define XUARTPS_MR_CHMODE_NORM      0x00000000U /**< Normal mode */
+#define XUARTPS_MR_CHMODE_SHIFT     8U          /**< Mode shift */
+#define XUARTPS_MR_CHMODE_MASK      0x00000300U /**< Mode mask */
+#define XUARTPS_MR_STOPMODE_2_BIT   0x00000080U /**< 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_5_BIT 0x00000040U /**< 1.5 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT   0x00000000U /**< 1 stop bit */
+#define XUARTPS_MR_STOPMODE_SHIFT   6U          /**< Stop bits shift */
+#define XUARTPS_MR_STOPMODE_MASK    0x000000A0U /**< Stop bits mask */
+#define XUARTPS_MR_PARITY_NONE      0x00000020U /**< No parity mode */
+#define XUARTPS_MR_PARITY_MARK      0x00000018U /**< Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE     0x00000010U /**< Space parity mode */
+#define XUARTPS_MR_PARITY_ODD       0x00000008U /**< Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN      0x00000000U /**< Even parity mode */
+#define XUARTPS_MR_PARITY_SHIFT     3U          /**< Parity setting shift */
+#define XUARTPS_MR_PARITY_MASK      0x00000038U /**< Parity mask */
+#define XUARTPS_MR_CHARLEN_6_BIT    0x00000006U /**< 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT    0x00000004U /**< 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT    0x00000000U /**< 8 bits data */
+#define XUARTPS_MR_CHARLEN_SHIFT    1U          /**< Data Length shift */
+#define XUARTPS_MR_CHARLEN_MASK     0x00000006U /**< Data length mask */
+#define XUARTPS_MR_CLKSEL           0x00000001U /**< Input clock select */
 
 /* Interrupt Register Bits Definition */
-#define XUARTPS_IXR_RBRK	0x00002000U /**< Rx FIFO break detect interrupt */
-#define XUARTPS_IXR_TOVR	0x00001000U /**< Tx FIFO Overflow interrupt */
-#define XUARTPS_IXR_TNFUL	0x00000800U /**< Tx FIFO Nearly Full interrupt */
-#define XUARTPS_IXR_TTRIG	0x00000400U /**< Tx Trig interrupt */
-#define XUARTPS_IXR_DMS		0x00000200U /**< Modem status change interrupt */
-#define XUARTPS_IXR_TOUT	0x00000100U /**< Timeout error interrupt */
-#define XUARTPS_IXR_PARITY	0x00000080U /**< Parity error interrupt */
-#define XUARTPS_IXR_FRAMING	0x00000040U /**< Framing error interrupt */
-#define XUARTPS_IXR_RXOVR	0x00000020U /**< Overrun error interrupt */
-#define XUARTPS_IXR_TXFULL	0x00000010U /**< TX FIFO full interrupt. */
-#define XUARTPS_IXR_TXEMPTY	0x00000008U /**< TX FIFO empty interrupt. */
-#define XUARTPS_IXR_RXFULL	0x00000004U /**< RX FIFO full interrupt. */
-#define XUARTPS_IXR_RXEMPTY	0x00000002U /**< RX FIFO empty interrupt. */
-#define XUARTPS_IXR_RTRIG	0x00000001U /**< RX FIFO trigger interrupt. */
-#define XUARTPS_IXR_MASK	0x00003FFFU /**< Valid bit mask */
+#define XUARTPS_IXR_RBRK    0x00002000U /**< Rx FIFO break detect interrupt */
+#define XUARTPS_IXR_TOVR    0x00001000U /**< Tx FIFO Overflow interrupt */
+#define XUARTPS_IXR_TNFUL   0x00000800U /**< Tx FIFO Nearly Full interrupt */
+#define XUARTPS_IXR_TTRIG   0x00000400U /**< Tx Trig interrupt */
+#define XUARTPS_IXR_DMS     0x00000200U /**< Modem status change interrupt */
+#define XUARTPS_IXR_TOUT    0x00000100U /**< Timeout error interrupt */
+#define XUARTPS_IXR_PARITY  0x00000080U /**< Parity error interrupt */
+#define XUARTPS_IXR_FRAMING 0x00000040U /**< Framing error interrupt */
+#define XUARTPS_IXR_RXOVR   0x00000020U /**< Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL  0x00000010U /**< TX FIFO full interrupt. */
+#define XUARTPS_IXR_TXEMPTY 0x00000008U /**< TX FIFO empty interrupt. */
+#define XUARTPS_IXR_RXFULL  0x00000004U /**< RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY 0x00000002U /**< RX FIFO empty interrupt. */
+#define XUARTPS_IXR_RTRIG   0x00000001U /**< RX FIFO trigger interrupt. */
+#define XUARTPS_IXR_MASK    0x00003FFFU /**< Valid bit mask */
 
 /* Modem Control Register Bits Definition */
-#define XUARTPS_MODEMCR_FCM_RTS_CTS	0x00000020 /**< RTS/CTS hardware flow control. */
-#define XUARTPS_MODEMCR_FCM_NONE	0x00000000 /**< No hardware flow control. */
-#define XUARTPS_MODEMCR_FCM_MASK	0x00000020 /**< Hardware flow control mask. */
-#define XUARTPS_MODEMCR_RTS_SHIFT	1U         /**< RTS bit shift */
-#define XUARTPS_MODEMCR_DTR_SHIFT	0U         /**< DTR bit shift */
+#define XUARTPS_MODEMCR_FCM_RTS_CTS 0x00000020 /**< RTS/CTS hardware flow control. */
+#define XUARTPS_MODEMCR_FCM_NONE    0x00000000 /**< No hardware flow control. */
+#define XUARTPS_MODEMCR_FCM_MASK    0x00000020 /**< Hardware flow control mask. */
+#define XUARTPS_MODEMCR_RTS_SHIFT   1U         /**< RTS bit shift */
+#define XUARTPS_MODEMCR_DTR_SHIFT   0U         /**< DTR bit shift */
 
 /* Channel Status Register */
-#define XUARTPS_SR_TNFUL	0x00004000U /**< TX FIFO Nearly Full Status */
-#define XUARTPS_SR_TTRIG	0x00002000U /**< TX FIFO Trigger Status */
-#define XUARTPS_SR_FLOWDEL	0x00001000U /**< RX FIFO fill over flow delay */
-#define XUARTPS_SR_TACTIVE	0x00000800U /**< TX active */
-#define XUARTPS_SR_RACTIVE	0x00000400U /**< RX active */
-#define XUARTPS_SR_TXFULL	0x00000010U /**< TX FIFO full */
-#define XUARTPS_SR_TXEMPTY	0x00000008U /**< TX FIFO empty */
-#define XUARTPS_SR_RXFULL	0x00000004U /**< RX FIFO full */
-#define XUARTPS_SR_RXEMPTY	0x00000002U /**< RX FIFO empty */
-#define XUARTPS_SR_RTRIG	0x00000001U /**< RX FIFO fill over trigger */
+#define XUARTPS_SR_TNFUL   0x00004000U /**< TX FIFO Nearly Full Status */
+#define XUARTPS_SR_TTRIG   0x00002000U /**< TX FIFO Trigger Status */
+#define XUARTPS_SR_FLOWDEL 0x00001000U /**< RX FIFO fill over flow delay */
+#define XUARTPS_SR_TACTIVE 0x00000800U /**< TX active */
+#define XUARTPS_SR_RACTIVE 0x00000400U /**< RX active */
+#define XUARTPS_SR_TXFULL  0x00000010U /**< TX FIFO full */
+#define XUARTPS_SR_TXEMPTY 0x00000008U /**< TX FIFO empty */
+#define XUARTPS_SR_RXFULL  0x00000004U /**< RX FIFO full */
+#define XUARTPS_SR_RXEMPTY 0x00000002U /**< RX FIFO empty */
+#define XUARTPS_SR_RTRIG   0x00000001U /**< RX FIFO fill over trigger */
 
 /** Device configuration structure */
 struct uart_xlnx_ps_dev_config {
@@ -158,6 +157,8 @@ struct uart_xlnx_ps_dev_data_t {
 	uint32_t flowctrl;
 
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	const struct device *dev;
+	struct k_timer timer;
 	uart_irq_callback_user_data_t user_cb;
 	void *user_data;
 #endif
@@ -254,7 +255,7 @@ static void set_baudrate(const struct device *dev, uint32_t baud_rate)
 			} else {
 				bauderr = tmpbaud - baud;
 			}
-			if (((bauderr * 100) / baud) < 3) {
+			if (((bauderr * 1000) / baud) < 3) {
 				break;
 			}
 		}
@@ -270,6 +271,25 @@ static void set_baudrate(const struct device *dev, uint32_t baud_rate)
 	}
 }
 
+#ifdef CONFIG_UART_INTERRUPT_DRIVEN
+
+/**
+ * @brief Trigger a UART callback based on a timer.
+ *
+ * @param timer Timer that triggered the callback
+ */
+static void uart_xlnx_ps_soft_isr(struct k_timer *timer)
+{
+	struct uart_xlnx_ps_dev_data_t *data =
+		CONTAINER_OF(timer, struct uart_xlnx_ps_dev_data_t, timer);
+
+	if (data->user_cb) {
+		data->user_cb(data->dev, data->user_data);
+	}
+}
+
+#endif
+
 /**
  * @brief Initialize individual UART port
  *
@@ -290,9 +310,6 @@ static int uart_xlnx_ps_init(const struct device *dev)
 	DEVICE_MMIO_MAP(dev, K_MEM_CACHE_NONE);
 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);
 
-	/* Disable RX/TX before changing any configuration data */
-	xlnx_ps_disable_uart(reg_base);
-
 #ifdef CONFIG_PINCTRL
 	err = pinctrl_apply_state(dev_cfg->pincfg, PINCTRL_STATE_DEFAULT);
 	if (err < 0) {
@@ -300,12 +317,15 @@ static int uart_xlnx_ps_init(const struct device *dev)
 	}
 #endif
 
+	/* Set RX/TX reset and disable RX/TX */
+	sys_write32(XUARTPS_CR_STOPBRK | XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS | XUARTPS_CR_TXRST |
+			    XUARTPS_CR_RXRST,
+		    reg_base + XUARTPS_CR_OFFSET);
+
 	/* Set initial character length / start/stop bit / parity configuration */
 	reg_val = sys_read32(reg_base + XUARTPS_MR_OFFSET);
-	reg_val &= (~(XUARTPS_MR_CHARLEN_MASK | XUARTPS_MR_STOPMODE_MASK |
-		    XUARTPS_MR_PARITY_MASK));
-	reg_val |= XUARTPS_MR_CHARLEN_8_BIT | XUARTPS_MR_STOPMODE_1_BIT |
-		   XUARTPS_MR_PARITY_NONE;
+	reg_val &= (~(XUARTPS_MR_CHARLEN_MASK | XUARTPS_MR_STOPMODE_MASK | XUARTPS_MR_PARITY_MASK));
+	reg_val |= XUARTPS_MR_CHARLEN_8_BIT | XUARTPS_MR_STOPMODE_1_BIT | XUARTPS_MR_PARITY_NONE;
 	sys_write32(reg_val, reg_base + XUARTPS_MR_OFFSET);
 
 	/* Set RX FIFO trigger at 1 data bytes. */
@@ -318,10 +338,14 @@ static int uart_xlnx_ps_init(const struct device *dev)
 	set_baudrate(dev, dev_cfg->baud_rate);
 
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
+	struct uart_xlnx_ps_dev_data_t *dev_data = dev->data;
 
 	/* Clear any pending interrupt flags */
 	sys_write32(XUARTPS_IXR_MASK, reg_base + XUARTPS_ISR_OFFSET);
 
+	dev_data->dev = dev;
+	k_timer_init(&dev_data->timer, &uart_xlnx_ps_soft_isr, NULL);
+
 	/* Attach to & unmask the corresponding interrupt vector */
 	dev_cfg->irq_config_func(dev);
 
@@ -356,7 +380,7 @@ static int uart_xlnx_ps_poll_in(const struct device *dev, unsigned char *c)
 /**
  * @brief Output a character in polled mode.
  *
- * Checks if the transmitter is empty. If empty, a character is written to
+ * Checks if the transmitter has available TX FIFO space. If so, a character is written to
  * the data register.
  *
  * If the hardware flow control is enabled then the handshake signal CTS has to
@@ -370,18 +394,54 @@ static int uart_xlnx_ps_poll_in(const struct device *dev, unsigned char *c)
 static void uart_xlnx_ps_poll_out(const struct device *dev, unsigned char c)
 {
 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);
-	uint32_t reg_val;
 
-	/* wait for transmitter to ready to accept a character */
-	do {
-		reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);
-	} while ((reg_val & XUARTPS_SR_TXEMPTY) == 0);
+	/* wait for transmitter to be ready to accept a character */
+	while ((sys_read32(reg_base + XUARTPS_SR_OFFSET) & XUARTPS_SR_TXFULL) != 0) {
+	}
 
 	sys_write32((uint32_t)(c & 0xFF), reg_base + XUARTPS_FIFO_OFFSET);
+}
+
+/**
+ * Check for pending TX/TX errors on the port.
+ *
+ * @param dev UART device struct
+ * @return 0 if no errors, UART_ERROR_* flags otherwise
+ */
+static int uart_xlnx_ps_err_check(const struct device *dev)
+{
+	uintptr_t reg_base = DEVICE_MMIO_GET(dev);
+	uint32_t reg_val = sys_read32(reg_base + XUARTPS_ISR_OFFSET);
+	int err = 0;
+
+	if (reg_val & XUARTPS_IXR_RBRK) {
+		err |= UART_BREAK;
+	}
+
+	if (reg_val & XUARTPS_IXR_TOVR) {
+		err |= UART_ERROR_OVERRUN;
+	}
+
+	if (reg_val & XUARTPS_IXR_TOUT) {
+		err |= UART_ERROR_NOISE;
+	}
 
-	do {
-		reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);
-	} while ((reg_val & XUARTPS_SR_TXEMPTY) == 0);
+	if (reg_val & XUARTPS_IXR_PARITY) {
+		err |= UART_ERROR_PARITY;
+	}
+
+	if (reg_val & XUARTPS_IXR_FRAMING) {
+		err |= UART_ERROR_FRAMING;
+	}
+
+	if (reg_val & XUARTPS_IXR_RXOVR) {
+		err |= UART_ERROR_OVERRUN;
+	}
+	sys_write32(reg_val & (XUARTPS_IXR_RBRK | XUARTPS_IXR_TOVR | XUARTPS_IXR_TOUT |
+			       XUARTPS_IXR_PARITY | XUARTPS_IXR_FRAMING | XUARTPS_IXR_RXOVR),
+		    reg_base + XUARTPS_ISR_OFFSET);
+
+	return err;
 }
 
 /**
@@ -403,9 +463,7 @@ static void uart_xlnx_ps_poll_out(const struct device *dev, unsigned char c)
  *         as all parity modes supported by the API are also supported
  *         by the hardware.
  */
-static inline bool uart_xlnx_ps_cfg2ll_parity(
-	uint32_t *mode_reg,
-	enum uart_config_parity parity)
+static inline bool uart_xlnx_ps_cfg2ll_parity(uint32_t *mode_reg, enum uart_config_parity parity)
 {
 	/*
 	 * Translate the new parity configuration to the mode register's
@@ -457,9 +515,8 @@ static inline bool uart_xlnx_ps_cfg2ll_parity(
  * @return Indication of success or failure in case of an unsupported
  *         stop bit configuration being provided by the caller.
  */
-static inline bool uart_xlnx_ps_cfg2ll_stopbits(
-	uint32_t *mode_reg,
-	enum uart_config_stop_bits stopbits)
+static inline bool uart_xlnx_ps_cfg2ll_stopbits(uint32_t *mode_reg,
+						enum uart_config_stop_bits stopbits)
 {
 	/*
 	 * Translate the new stop bit configuration to the mode register's
@@ -507,9 +564,8 @@ static inline bool uart_xlnx_ps_cfg2ll_stopbits(
  * @return Indication of success or failure in case of an unsupported
  *         data bit configuration being provided by the caller.
  */
-static inline bool uart_xlnx_ps_cfg2ll_databits(
-	uint32_t *mode_reg,
-	enum uart_config_data_bits databits)
+static inline bool uart_xlnx_ps_cfg2ll_databits(uint32_t *mode_reg,
+						enum uart_config_data_bits databits)
 {
 	/*
 	 * Translate the new data bit configuration to the mode register's
@@ -559,9 +615,8 @@ static inline bool uart_xlnx_ps_cfg2ll_databits(
  * @return Indication of success or failure in case of an unsupported
  *         flow control configuration being provided by the caller.
  */
-static inline bool uart_xlnx_ps_cfg2ll_hwctrl(
-	uint32_t *modemcr_reg,
-	enum uart_config_flow_control hwctrl)
+static inline bool uart_xlnx_ps_cfg2ll_hwctrl(uint32_t *modemcr_reg,
+					      enum uart_config_flow_control hwctrl)
 {
 	/*
 	 * Translate the new flow control configuration to the modem
@@ -572,7 +627,7 @@ static inline bool uart_xlnx_ps_cfg2ll_hwctrl(
 
 	if (hwctrl == UART_CFG_FLOW_CTRL_RTS_CTS) {
 		*modemcr_reg |= XUARTPS_MODEMCR_FCM_RTS_CTS;
-	} else if (hwctrl ==  UART_CFG_FLOW_CTRL_NONE) {
+	} else if (hwctrl == UART_CFG_FLOW_CTRL_NONE) {
 		*modemcr_reg |= XUARTPS_MODEMCR_FCM_NONE;
 	} else {
 		/* Only no flow control or RTS/CTS is supported. */
@@ -595,31 +650,29 @@ static inline bool uart_xlnx_ps_cfg2ll_hwctrl(
  * @return 0 if the configuration completed successfully, ENOTSUP
  *         error if an unsupported configuration parameter is detected.
  */
-static int uart_xlnx_ps_configure(const struct device *dev,
-				  const struct uart_config *cfg)
+static int uart_xlnx_ps_configure(const struct device *dev, const struct uart_config *cfg)
 {
-	struct uart_xlnx_ps_dev_config *dev_cfg =
-	(struct uart_xlnx_ps_dev_config *)dev->config;
+	struct uart_xlnx_ps_dev_config *dev_cfg = (struct uart_xlnx_ps_dev_config *)dev->config;
 
-	uintptr_t reg_base   = DEVICE_MMIO_GET(dev);
-	uint32_t mode_reg    = 0;
+	uintptr_t reg_base = DEVICE_MMIO_GET(dev);
+	uint32_t mode_reg = 0;
 	uint32_t modemcr_reg = 0;
 
 	/* Read the current mode register & modem control register values */
-	mode_reg    = sys_read32(reg_base + XUARTPS_MR_OFFSET);
+	mode_reg = sys_read32(reg_base + XUARTPS_MR_OFFSET);
 	modemcr_reg = sys_read32(reg_base + XUARTPS_MODEMCR_OFFSET);
 
 	/* Mask out all items that might be re-configured */
-	mode_reg    &= (~XUARTPS_MR_PARITY_MASK);
-	mode_reg    &= (~XUARTPS_MR_STOPMODE_MASK);
-	mode_reg    &= (~XUARTPS_MR_CHARLEN_MASK);
+	mode_reg &= (~XUARTPS_MR_PARITY_MASK);
+	mode_reg &= (~XUARTPS_MR_STOPMODE_MASK);
+	mode_reg &= (~XUARTPS_MR_CHARLEN_MASK);
 	modemcr_reg &= (~XUARTPS_MODEMCR_FCM_MASK);
 
 	/* Assemble the updated registers, validity checks contained within */
 	if ((!uart_xlnx_ps_cfg2ll_parity(&mode_reg, cfg->parity)) ||
-		(!uart_xlnx_ps_cfg2ll_stopbits(&mode_reg, cfg->stop_bits)) ||
-		(!uart_xlnx_ps_cfg2ll_databits(&mode_reg, cfg->data_bits)) ||
-		(!uart_xlnx_ps_cfg2ll_hwctrl(&modemcr_reg, cfg->flow_ctrl))) {
+	    (!uart_xlnx_ps_cfg2ll_stopbits(&mode_reg, cfg->stop_bits)) ||
+	    (!uart_xlnx_ps_cfg2ll_databits(&mode_reg, cfg->data_bits)) ||
+	    (!uart_xlnx_ps_cfg2ll_hwctrl(&modemcr_reg, cfg->flow_ctrl))) {
 		return -ENOTSUP;
 	}
 
@@ -631,7 +684,7 @@ static int uart_xlnx_ps_configure(const struct device *dev,
 	dev_cfg->baud_rate = cfg->baudrate;
 
 	/* Write the two control registers */
-	sys_write32(mode_reg,    reg_base + XUARTPS_MR_OFFSET);
+	sys_write32(mode_reg, reg_base + XUARTPS_MR_OFFSET);
 	sys_write32(modemcr_reg, reg_base + XUARTPS_MODEMCR_OFFSET);
 
 	/* Re-enable the controller */
@@ -655,8 +708,7 @@ static int uart_xlnx_ps_configure(const struct device *dev,
  * @return The current parity setting mapped to the UART driver API's
  *         enum type.
  */
-static inline enum uart_config_parity uart_xlnx_ps_ll2cfg_parity(
-	uint32_t mode_reg)
+static inline enum uart_config_parity uart_xlnx_ps_ll2cfg_parity(uint32_t mode_reg)
 {
 	/*
 	 * Obtain the current parity configuration from the mode register's
@@ -697,8 +749,7 @@ static inline enum uart_config_parity uart_xlnx_ps_ll2cfg_parity(
  * @return The current stop bit setting mapped to the UART driver API's
  *         enum type.
  */
-static inline enum uart_config_stop_bits uart_xlnx_ps_ll2cfg_stopbits(
-	uint32_t mode_reg)
+static inline enum uart_config_stop_bits uart_xlnx_ps_ll2cfg_stopbits(uint32_t mode_reg)
 {
 	/*
 	 * Obtain the current stop bit configuration from the mode register's
@@ -734,8 +785,7 @@ static inline enum uart_config_stop_bits uart_xlnx_ps_ll2cfg_stopbits(
  * @return The current data bit setting mapped to the UART driver API's
  *         enum type.
  */
-static inline enum uart_config_data_bits uart_xlnx_ps_ll2cfg_databits(
-	uint32_t mode_reg)
+static inline enum uart_config_data_bits uart_xlnx_ps_ll2cfg_databits(uint32_t mode_reg)
 {
 	/*
 	 * Obtain the current data bit configuration from the mode register's
@@ -770,8 +820,7 @@ static inline enum uart_config_data_bits uart_xlnx_ps_ll2cfg_databits(
  * @return The current flow control setting mapped to the UART driver API's
  *         enum type.
  */
-static inline enum uart_config_flow_control uart_xlnx_ps_ll2cfg_hwctrl(
-	uint32_t modemcr_reg)
+static inline enum uart_config_flow_control uart_xlnx_ps_ll2cfg_hwctrl(uint32_t modemcr_reg)
 {
 	/*
 	 * Obtain the current flow control configuration from the modem
@@ -780,8 +829,7 @@ static inline enum uart_config_flow_control uart_xlnx_ps_ll2cfg_hwctrl(
 	 *  1b : RTS/CTS
 	 */
 
-	if ((modemcr_reg & XUARTPS_MODEMCR_FCM_MASK)
-		== XUARTPS_MODEMCR_FCM_RTS_CTS) {
+	if ((modemcr_reg & XUARTPS_MODEMCR_FCM_MASK) == XUARTPS_MODEMCR_FCM_RTS_CTS) {
 		return UART_CFG_FLOW_CTRL_RTS_CTS;
 	}
 
@@ -802,8 +850,7 @@ static inline enum uart_config_flow_control uart_xlnx_ps_ll2cfg_hwctrl(
  *
  * @return always 0.
  */
-static int uart_xlnx_ps_config_get(const struct device *dev,
-				   struct uart_config *cfg)
+static int uart_xlnx_ps_config_get(const struct device *dev, struct uart_config *cfg)
 {
 	const struct uart_xlnx_ps_dev_config *dev_cfg = dev->config;
 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);
@@ -814,11 +861,11 @@ static int uart_xlnx_ps_config_get(const struct device *dev,
 	 * Register) and the current flow control setting (Modem
 	 * Control register).
 	 */
-	uint32_t mode_reg    = sys_read32(reg_base + XUARTPS_MR_OFFSET);
+	uint32_t mode_reg = sys_read32(reg_base + XUARTPS_MR_OFFSET);
 	uint32_t modemcr_reg = sys_read32(reg_base + XUARTPS_MODEMCR_OFFSET);
 
-	cfg->baudrate  = dev_cfg->baud_rate;
-	cfg->parity    = uart_xlnx_ps_ll2cfg_parity(mode_reg);
+	cfg->baudrate = dev_cfg->baud_rate;
+	cfg->parity = uart_xlnx_ps_ll2cfg_parity(mode_reg);
 	cfg->stop_bits = uart_xlnx_ps_ll2cfg_stopbits(mode_reg);
 	cfg->data_bits = uart_xlnx_ps_ll2cfg_databits(mode_reg);
 	cfg->flow_ctrl = uart_xlnx_ps_ll2cfg_hwctrl(modemcr_reg);
@@ -838,22 +885,17 @@ static int uart_xlnx_ps_config_get(const struct device *dev,
  *
  * @return Number of bytes sent
  */
-static int uart_xlnx_ps_fifo_fill(const struct device *dev,
-				  const uint8_t *tx_data,
-				  int size)
+static int uart_xlnx_ps_fifo_fill(const struct device *dev, const uint8_t *tx_data, int size)
 {
 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);
-	uint32_t data_iter = 0;
+	int count = 0;
 
-	sys_write32(XUARTPS_IXR_TXEMPTY, reg_base + XUARTPS_IDR_OFFSET);
-	while (size--) {
-		while ((sys_read32(reg_base + XUARTPS_SR_OFFSET) & XUARTPS_SR_TXFULL) != 0) {
-		}
-		sys_write32((uint32_t)tx_data[data_iter++], reg_base + XUARTPS_FIFO_OFFSET);
+	while (count < size &&
+	       (sys_read32(reg_base + XUARTPS_SR_OFFSET) & XUARTPS_SR_TXFULL) == 0) {
+		sys_write32((uint32_t)tx_data[count++], reg_base + XUARTPS_FIFO_OFFSET);
 	}
-	sys_write32(XUARTPS_IXR_TXEMPTY, reg_base + XUARTPS_IER_OFFSET);
 
-	return data_iter;
+	return count;
 }
 
 /**
@@ -865,21 +907,17 @@ static int uart_xlnx_ps_fifo_fill(const struct device *dev,
  *
  * @return Number of bytes read
  */
-static int uart_xlnx_ps_fifo_read(const struct device *dev, uint8_t *rx_data,
-				  const int size)
+static int uart_xlnx_ps_fifo_read(const struct device *dev, uint8_t *rx_data, const int size)
 {
 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);
-	uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);
-	int inum = 0;
+	int count = 0;
 
-	while (inum < size && (reg_val & XUARTPS_SR_RXEMPTY) == 0) {
-		rx_data[inum] = (uint8_t)sys_read32(reg_base
-				+ XUARTPS_FIFO_OFFSET);
-		inum++;
-		reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);
+	while (count < size &&
+	       (sys_read32(reg_base + XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY) == 0) {
+		rx_data[count++] = (uint8_t)sys_read32(reg_base + XUARTPS_FIFO_OFFSET);
 	}
 
-	return inum;
+	return count;
 }
 
 /**
@@ -889,11 +927,20 @@ static int uart_xlnx_ps_fifo_read(const struct device *dev, uint8_t *rx_data,
  */
 static void uart_xlnx_ps_irq_tx_enable(const struct device *dev)
 {
+	struct uart_xlnx_ps_dev_data_t *dev_data = dev->data;
 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);
 
-	sys_write32(
-		(XUARTPS_IXR_TTRIG | XUARTPS_IXR_TXEMPTY),
-		reg_base + XUARTPS_IER_OFFSET);
+	sys_write32((XUARTPS_IXR_TTRIG | XUARTPS_IXR_TXEMPTY), reg_base + XUARTPS_IER_OFFSET);
+	if ((sys_read32(reg_base + XUARTPS_SR_OFFSET) & (XUARTPS_SR_TTRIG | XUARTPS_SR_TXEMPTY)) !=
+	    0) {
+		/*
+		 * Enabling TX empty interrupts does not cause an interrupt
+		 * if the FIFO is already empty.
+		 * Generate a soft interrupt and have it call the
+		 * callback function in timer isr context.
+		 */
+		k_timer_start(&dev_data->timer, K_NO_WAIT, K_NO_WAIT);
+	}
 }
 
 /**
@@ -905,9 +952,7 @@ static void uart_xlnx_ps_irq_tx_disable(const struct device *dev)
 {
 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);
 
-	sys_write32(
-		(XUARTPS_IXR_TTRIG | XUARTPS_IXR_TXEMPTY),
-		reg_base + XUARTPS_IDR_OFFSET);
+	sys_write32((XUARTPS_IXR_TTRIG | XUARTPS_IXR_TXEMPTY), reg_base + XUARTPS_IDR_OFFSET);
 }
 
 /**
@@ -941,11 +986,7 @@ static int uart_xlnx_ps_irq_tx_complete(const struct device *dev)
 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);
 	uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);
 
-	if ((reg_val & XUARTPS_SR_TXEMPTY) == 0) {
-		return 0;
-	} else {
-		return 1;
-	}
+	return (reg_val & XUARTPS_SR_TXEMPTY) != 0;
 }
 
 /**
@@ -955,9 +996,19 @@ static int uart_xlnx_ps_irq_tx_complete(const struct device *dev)
  */
 static void uart_xlnx_ps_irq_rx_enable(const struct device *dev)
 {
+	struct uart_xlnx_ps_dev_data_t *dev_data = dev->data;
 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);
 
 	sys_write32(XUARTPS_IXR_RTRIG, reg_base + XUARTPS_IER_OFFSET);
+	if ((sys_read32(reg_base + XUARTPS_SR_OFFSET) & XUARTPS_SR_RXEMPTY) == 0) {
+		/*
+		 * Enabling RX trigger interrupts does not cause an interrupt
+		 * if the FIFO already contains RX data.
+		 * Generate a soft interrupt and have it call the
+		 * callback function in timer isr context.
+		 */
+		k_timer_start(&dev_data->timer, K_NO_WAIT, K_NO_WAIT);
+	}
 }
 
 /**
@@ -982,14 +1033,9 @@ static void uart_xlnx_ps_irq_rx_disable(const struct device *dev)
 static int uart_xlnx_ps_irq_rx_ready(const struct device *dev)
 {
 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);
-	uint32_t reg_val = sys_read32(reg_base + XUARTPS_ISR_OFFSET);
+	uint32_t reg_val = sys_read32(reg_base + XUARTPS_SR_OFFSET);
 
-	if ((reg_val & XUARTPS_IXR_RTRIG) == 0) {
-		return 0;
-	} else {
-		sys_write32(XUARTPS_IXR_RTRIG, reg_base + XUARTPS_ISR_OFFSET);
-		return 1;
-	}
+	return (reg_val & XUARTPS_SR_RXEMPTY) == 0;
 }
 
 /**
@@ -1001,13 +1047,13 @@ static void uart_xlnx_ps_irq_err_enable(const struct device *dev)
 {
 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);
 
-	sys_write32(
-		  XUARTPS_IXR_TOVR    /* [12] Transmitter FIFO Overflow */
-		| XUARTPS_IXR_TOUT    /* [8]  Receiver Timerout */
-		| XUARTPS_IXR_PARITY  /* [7]  Parity Error */
-		| XUARTPS_IXR_FRAMING /* [6]  Receiver Framing Error */
-		| XUARTPS_IXR_RXOVR,  /* [5]  Receiver Overflow Error */
-	    reg_base + XUARTPS_IER_OFFSET);
+	sys_write32(XUARTPS_IXR_RBRK              /* [13] Receiver Break */
+			    | XUARTPS_IXR_TOVR    /* [12] Transmitter FIFO Overflow */
+			    | XUARTPS_IXR_TOUT    /* [8]  Receiver Timerout */
+			    | XUARTPS_IXR_PARITY  /* [7]  Parity Error */
+			    | XUARTPS_IXR_FRAMING /* [6]  Receiver Framing Error */
+			    | XUARTPS_IXR_RXOVR,  /* [5]  Receiver Overflow Error */
+		    reg_base + XUARTPS_IER_OFFSET);
 }
 
 /**
@@ -1021,13 +1067,13 @@ static void uart_xlnx_ps_irq_err_disable(const struct device *dev)
 {
 	uintptr_t reg_base = DEVICE_MMIO_GET(dev);
 
-	sys_write32(
-		  XUARTPS_IXR_TOVR    /* [12] Transmitter FIFO Overflow */
-		| XUARTPS_IXR_TOUT    /* [8]  Receiver Timerout */
-		| XUARTPS_IXR_PARITY  /* [7]  Parity Error */
-		| XUARTPS_IXR_FRAMING /* [6]  Receiver Framing Error */
-		| XUARTPS_IXR_RXOVR,  /* [5]  Receiver Overflow Error */
-	    reg_base + XUARTPS_IDR_OFFSET);
+	sys_write32(XUARTPS_IXR_RBRK              /* [13] Receiver Break */
+			    | XUARTPS_IXR_TOVR    /* [12] Transmitter FIFO Overflow */
+			    | XUARTPS_IXR_TOUT    /* [8]  Receiver Timerout */
+			    | XUARTPS_IXR_PARITY  /* [7]  Parity Error */
+			    | XUARTPS_IXR_FRAMING /* [6]  Receiver Framing Error */
+			    | XUARTPS_IXR_RXOVR,  /* [5]  Receiver Overflow Error */
+		    reg_base + XUARTPS_IDR_OFFSET);
 }
 
 /**
@@ -1059,7 +1105,11 @@ static int uart_xlnx_ps_irq_is_pending(const struct device *dev)
  */
 static int uart_xlnx_ps_irq_update(const struct device *dev)
 {
-	ARG_UNUSED(dev);
+	uintptr_t reg_base = DEVICE_MMIO_GET(dev);
+
+	/* Clear RX/TX interrupts */
+	sys_write32(XUARTPS_IXR_TTRIG | XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RTRIG,
+		    reg_base + XUARTPS_ISR_OFFSET);
 	return 1;
 }
 
@@ -1070,8 +1120,7 @@ static int uart_xlnx_ps_irq_update(const struct device *dev)
  * @param cb Callback function pointer.
  */
 static void uart_xlnx_ps_irq_callback_set(const struct device *dev,
-					    uart_irq_callback_user_data_t cb,
-					    void *cb_data)
+					  uart_irq_callback_user_data_t cb, void *cb_data)
 {
 	struct uart_xlnx_ps_dev_data_t *dev_data = dev->data;
 
@@ -1099,6 +1148,7 @@ static void uart_xlnx_ps_isr(const struct device *dev)
 static DEVICE_API(uart, uart_xlnx_ps_driver_api) = {
 	.poll_in = uart_xlnx_ps_poll_in,
 	.poll_out = uart_xlnx_ps_poll_out,
+	.err_check = uart_xlnx_ps_err_check,
 #ifdef CONFIG_UART_USE_RUNTIME_CONFIGURE
 	.configure = uart_xlnx_ps_configure,
 	.config_get = uart_xlnx_ps_config_get,
@@ -1123,18 +1173,15 @@ static DEVICE_API(uart, uart_xlnx_ps_driver_api) = {
 
 #ifdef CONFIG_UART_INTERRUPT_DRIVEN
 
-#define UART_XLNX_PS_IRQ_CONF_FUNC_SET(port) \
-	.irq_config_func = uart_xlnx_ps_irq_config_##port,
-
-#define UART_XLNX_PS_IRQ_CONF_FUNC(port) \
-static void uart_xlnx_ps_irq_config_##port(const struct device *dev) \
-{ \
-	IRQ_CONNECT(DT_INST_IRQN(port), \
-	DT_INST_IRQ(port, priority), \
-	uart_xlnx_ps_isr, DEVICE_DT_INST_GET(port), \
-	0); \
-	irq_enable(DT_INST_IRQN(port)); \
-}
+#define UART_XLNX_PS_IRQ_CONF_FUNC_SET(port) .irq_config_func = uart_xlnx_ps_irq_config_##port,
+
+#define UART_XLNX_PS_IRQ_CONF_FUNC(port)                                                           \
+	static void uart_xlnx_ps_irq_config_##port(const struct device *dev)                       \
+	{                                                                                          \
+		IRQ_CONNECT(DT_INST_IRQN(port), DT_INST_IRQ(port, priority), uart_xlnx_ps_isr,     \
+			    DEVICE_DT_INST_GET(port), 0);                                          \
+		irq_enable(DT_INST_IRQN(port));                                                    \
+	}
 
 #else
 
@@ -1143,40 +1190,34 @@ static void uart_xlnx_ps_irq_config_##port(const struct device *dev) \
 
 #endif /*CONFIG_UART_INTERRUPT_DRIVEN */
 
-#define UART_XLNX_PS_DEV_DATA(port) \
-static struct uart_xlnx_ps_dev_data_t uart_xlnx_ps_dev_data_##port
+#define UART_XLNX_PS_DEV_DATA(port)                                                                \
+	static struct uart_xlnx_ps_dev_data_t uart_xlnx_ps_dev_data_##port
 
 #if CONFIG_PINCTRL
 #define UART_XLNX_PS_PINCTRL_DEFINE(port) PINCTRL_DT_INST_DEFINE(port);
-#define UART_XLNX_PS_PINCTRL_INIT(port) .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(port),
+#define UART_XLNX_PS_PINCTRL_INIT(port)   .pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(port),
 #else
 #define UART_XLNX_PS_PINCTRL_DEFINE(port)
 #define UART_XLNX_PS_PINCTRL_INIT(port)
 #endif /* CONFIG_PINCTRL */
 
-#define UART_XLNX_PS_DEV_CFG(port) \
-static struct uart_xlnx_ps_dev_config uart_xlnx_ps_dev_cfg_##port = { \
-	DEVICE_MMIO_ROM_INIT(DT_DRV_INST(port)), \
-	.sys_clk_freq = DT_INST_PROP(port, clock_frequency), \
-	.baud_rate = DT_INST_PROP(port, current_speed), \
-	UART_XLNX_PS_IRQ_CONF_FUNC_SET(port) \
-	UART_XLNX_PS_PINCTRL_INIT(port) \
-}
-
-#define UART_XLNX_PS_INIT(port) \
-DEVICE_DT_INST_DEFINE(port, \
-	uart_xlnx_ps_init, \
-	NULL, \
-	&uart_xlnx_ps_dev_data_##port, \
-	&uart_xlnx_ps_dev_cfg_##port, \
-	PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY, \
-	&uart_xlnx_ps_driver_api)
-
-#define UART_XLNX_INSTANTIATE(inst)		\
-	UART_XLNX_PS_PINCTRL_DEFINE(inst)	\
-	UART_XLNX_PS_IRQ_CONF_FUNC(inst);	\
-	UART_XLNX_PS_DEV_DATA(inst);		\
-	UART_XLNX_PS_DEV_CFG(inst);		\
+#define UART_XLNX_PS_DEV_CFG(port)                                                                 \
+	static struct uart_xlnx_ps_dev_config uart_xlnx_ps_dev_cfg_##port = {                      \
+		DEVICE_MMIO_ROM_INIT(DT_DRV_INST(port)),                                           \
+		.sys_clk_freq = DT_INST_PROP(port, clock_frequency),                               \
+		.baud_rate = DT_INST_PROP(port, current_speed),                                    \
+		UART_XLNX_PS_IRQ_CONF_FUNC_SET(port) UART_XLNX_PS_PINCTRL_INIT(port)}
+
+#define UART_XLNX_PS_INIT(port)                                                                    \
+	DEVICE_DT_INST_DEFINE(port, uart_xlnx_ps_init, NULL, &uart_xlnx_ps_dev_data_##port,        \
+			      &uart_xlnx_ps_dev_cfg_##port, PRE_KERNEL_1,                          \
+			      CONFIG_SERIAL_INIT_PRIORITY, &uart_xlnx_ps_driver_api)
+
+#define UART_XLNX_INSTANTIATE(inst)                                                                \
+	UART_XLNX_PS_PINCTRL_DEFINE(inst)                                                          \
+	UART_XLNX_PS_IRQ_CONF_FUNC(inst);                                                          \
+	UART_XLNX_PS_DEV_DATA(inst);                                                               \
+	UART_XLNX_PS_DEV_CFG(inst);                                                                \
 	UART_XLNX_PS_INIT(inst);
 
 DT_INST_FOREACH_STATUS_OKAY(UART_XLNX_INSTANTIATE)
diff --git a/drivers/serial/uart_xlnx_uartlite.c b/drivers/serial/uart_xlnx_uartlite.c
index 6ae60cf1d0b..8898ff67833 100644
--- a/drivers/serial/uart_xlnx_uartlite.c
+++ b/drivers/serial/uart_xlnx_uartlite.c
@@ -382,7 +382,7 @@ static DEVICE_API(uart, xlnx_uartlite_driver_api) = {
 			    xlnx_uartlite_isr,				\
 			    DEVICE_DT_INST_GET(n), 0);			\
 									\
-		irq_enable(DT_INST_IRQ_BY_IDX(n, i, irq));		\
+		irq_enable(DT_INST_IRQN_BY_IDX(n, i));			\
 	} while (false)
 #define XLNX_UARTLITE_CONFIG_FUNC(n)					\
 	static void xlnx_uartlite_config_func_##n(const struct device *dev) \
diff --git a/drivers/serial/usart_gd32.c b/drivers/serial/usart_gd32.c
index 9936a818124..bbccf6525ce 100644
--- a/drivers/serial/usart_gd32.c
+++ b/drivers/serial/usart_gd32.c
@@ -335,7 +335,7 @@ static DEVICE_API(uart, usart_gd32_driver_api) = {
 		.clkid = DT_INST_CLOCKS_CELL(n, id),				\
 		.reset = RESET_DT_SPEC_INST_GET(n),				\
 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
-		.parity = DT_INST_ENUM_IDX_OR(n, parity, UART_CFG_PARITY_NONE),	\
+		.parity = DT_INST_ENUM_IDX(n, parity),				\
 		 GD32_USART_IRQ_HANDLER_FUNC_INIT(n)				\
 	};									\
 	DEVICE_DT_INST_DEFINE(n, usart_gd32_init,				\
diff --git a/drivers/spi/CMakeLists.txt b/drivers/spi/CMakeLists.txt
index e7746e17edb..57724a71ad5 100644
--- a/drivers/spi/CMakeLists.txt
+++ b/drivers/spi/CMakeLists.txt
@@ -20,11 +20,11 @@ zephyr_library_sources_ifdef(CONFIG_SPI_AMBIQ_SPID spi_ambiq_spid.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_ANDES_ATCSPI200 spi_andes_atcspi200.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_BITBANG spi_bitbang.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_CC13XX_CC26XX spi_cc13xx_cc26xx.c)
+zephyr_library_sources_ifdef(CONFIG_SPI_CC23X0 spi_cc23x0.c)
+zephyr_library_sources_ifdef(CONFIG_SPI_CDNS spi_cdns.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_DW spi_dw.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_EMUL spi_emul.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_GD32 spi_gd32.c)
-zephyr_library_sources_ifdef(CONFIG_SPI_GECKO_EUSART spi_gecko_eusart.c)
-zephyr_library_sources_ifdef(CONFIG_SPI_GECKO_USART spi_gecko_usart.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_GRLIB_SPIMCTRL spi_grlib_spimctrl.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_INFINEON_CAT1 spi_ifx_cat1.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_ITE_IT8XXX2 spi_it8xxx2.c)
@@ -37,7 +37,6 @@ zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_DSPI spi_mcux_dspi.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_ECSPI spi_mcux_ecspi.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_FLEXCOMM spi_mcux_flexcomm.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_FLEXIO spi_mcux_flexio.c)
-zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_LPSPI spi_mcux_lpspi.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_NPCX_SPIP spi_npcx_spip.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_NRFX_SPI spi_nrfx_spi.c spi_nrfx_common.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_NRFX_SPIM spi_nrfx_spim.c spi_nrfx_common.c)
@@ -56,6 +55,8 @@ zephyr_library_sources_ifdef(CONFIG_SPI_SAM spi_sam.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_SAM0 spi_sam0.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_SEDI spi_sedi.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_SIFIVE spi_sifive.c)
+zephyr_library_sources_ifdef(CONFIG_SPI_SILABS_EUSART spi_silabs_eusart.c)
+zephyr_library_sources_ifdef(CONFIG_SPI_SILABS_USART spi_silabs_usart.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_SMARTBOND spi_smartbond.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_STM32 spi_ll_stm32.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_TELINK_B91 spi_b91.c)
@@ -65,3 +66,5 @@ zephyr_library_sources_ifdef(CONFIG_SPI_XEC_QMSPI_LDMA spi_xec_qmspi_ldma.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_XLNX_AXI_QUADSPI spi_xlnx_axi_quadspi.c)
 zephyr_library_sources_ifdef(CONFIG_SPI_XMC4XXX spi_xmc4xxx.c)
 # zephyr-keep-sorted-stop
+
+add_subdirectory(spi_nxp_lpspi)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 136a1fcca56..7f2a5996ff0 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -37,6 +37,24 @@ config SPI_RTIO
 	  This option enables the RTIO API calls. RTIO support is
 	  experimental as the API itself is unstable.
 
+if SPI_RTIO
+
+config SPI_RTIO_FALLBACK_MSGS
+	int "Number of available spi_buf structs for the default handler to use"
+	default 4
+	help
+		When RTIO is used with a driver that does not yet implement the submit API
+		natively the submissions are converted back to struct spi_buf values that
+		are given to spi_transfer. This requires some number of msgs be available to convert
+		the submissions into on the stack. MISRA rules dictate we must know this in
+		advance.
+
+		In all likelihood 4 is going to work for everyone, but in case you do end up with
+		an issue where you are using RTIO, your driver does not implement submit natively,
+		and get an error relating to not enough spi msgs this is the Kconfig to manipulate.
+
+endif # SPI_RTIO
+
 config SPI_SLAVE
 	bool "Slave support [EXPERIMENTAL]"
 	select EXPERIMENTAL
@@ -81,11 +99,11 @@ source "drivers/spi/Kconfig.andes_atcspi200"
 source "drivers/spi/Kconfig.b91"
 source "drivers/spi/Kconfig.bitbang"
 source "drivers/spi/Kconfig.cc13xx_cc26xx"
+source "drivers/spi/Kconfig.cc23x0"
+source "drivers/spi/Kconfig.cdns"
 source "drivers/spi/Kconfig.dw"
 source "drivers/spi/Kconfig.esp32"
 source "drivers/spi/Kconfig.gd32"
-source "drivers/spi/Kconfig.gecko_eusart"
-source "drivers/spi/Kconfig.gecko_usart"
 source "drivers/spi/Kconfig.grlib_spimctrl"
 source "drivers/spi/Kconfig.ifx_cat1"
 source "drivers/spi/Kconfig.it8xxx2"
@@ -97,7 +115,6 @@ source "drivers/spi/Kconfig.mcux_dspi"
 source "drivers/spi/Kconfig.mcux_ecspi"
 source "drivers/spi/Kconfig.mcux_flexcomm"
 source "drivers/spi/Kconfig.mcux_flexio"
-source "drivers/spi/Kconfig.mcux_lpspi"
 source "drivers/spi/Kconfig.npcx"
 source "drivers/spi/Kconfig.nrfx"
 source "drivers/spi/Kconfig.numaker"
@@ -115,6 +132,8 @@ source "drivers/spi/Kconfig.sam"
 source "drivers/spi/Kconfig.sam0"
 source "drivers/spi/Kconfig.sedi"
 source "drivers/spi/Kconfig.sifive"
+source "drivers/spi/Kconfig.silabs_eusart"
+source "drivers/spi/Kconfig.silabs_usart"
 source "drivers/spi/Kconfig.smartbond"
 source "drivers/spi/Kconfig.spi_emul"
 source "drivers/spi/Kconfig.stm32"
@@ -122,6 +141,7 @@ source "drivers/spi/Kconfig.test"
 source "drivers/spi/Kconfig.xec_qmspi"
 source "drivers/spi/Kconfig.xlnx"
 source "drivers/spi/Kconfig.xmc4xxx"
+source "drivers/spi/spi_nxp_lpspi/Kconfig"
 # zephyr-keep-sorted-stop
 
 endif # SPI
diff --git a/drivers/spi/Kconfig.cc23x0 b/drivers/spi/Kconfig.cc23x0
new file mode 100644
index 00000000000..83747b56343
--- /dev/null
+++ b/drivers/spi/Kconfig.cc23x0
@@ -0,0 +1,12 @@
+# TI CC23x0 SPI configuration options
+
+# Copyright (c) 2024 BayLibre, SAS
+# SPDX-License-Identifier: Apache-2.0
+
+config SPI_CC23X0
+	bool "TI SimpleLink CC23x0 SPI driver"
+	default y
+	depends on DT_HAS_TI_CC23X0_SPI_ENABLED
+	select PINCTRL
+	help
+	  Enable support for the TI SimpleLink CC23x0 SPI peripheral
diff --git a/drivers/spi/Kconfig.cdns b/drivers/spi/Kconfig.cdns
new file mode 100644
index 00000000000..7bc3166c9b2
--- /dev/null
+++ b/drivers/spi/Kconfig.cdns
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Meta Platforms
+# SPDX-License-Identifier: Apache-2.0
+
+config SPI_CDNS
+	bool "Cadence SPI controller driver"
+	depends on DT_HAS_CDNS_SPI_ENABLED
+	help
+	  Enable the SPI peripherals based on Cadence IP6524
diff --git a/drivers/spi/Kconfig.gecko_eusart b/drivers/spi/Kconfig.gecko_eusart
deleted file mode 100644
index 0734658d4ad..00000000000
--- a/drivers/spi/Kconfig.gecko_eusart
+++ /dev/null
@@ -1,14 +0,0 @@
-# Gecko SPI configuration option
-
-# Copyright (c) 2024 Daikin Comfort Technologies North America, Inc.
-# SPDX-License-Identifier: Apache-2.0
-
-config SPI_GECKO_EUSART
-	bool "Gecko EUSART SPI controller driver"
-	default y
-	depends on DT_HAS_SILABS_GECKO_SPI_EUSART_ENABLED
-	depends on GPIO
-	select SOC_GECKO_EUSART
-	select PINCTRL if SOC_FAMILY_SILABS_S2
-	help
-	  Enable the EUSART SPI peripherals on Gecko
diff --git a/drivers/spi/Kconfig.gecko_usart b/drivers/spi/Kconfig.gecko_usart
deleted file mode 100644
index cba8f4f5278..00000000000
--- a/drivers/spi/Kconfig.gecko_usart
+++ /dev/null
@@ -1,15 +0,0 @@
-# Gecko SPI configuration option
-
-# Copyright (c) 2019 Christian Taedcke <hacking@taedcke.com>
-# SPDX-License-Identifier: Apache-2.0
-
-config SPI_GECKO_USART
-	bool "Gecko SPI controller driver"
-	default y
-	depends on DT_HAS_SILABS_GECKO_SPI_USART_ENABLED
-	depends on GPIO
-	select SOC_GECKO_USART
-	select CLOCK_CONTROL_SILABS_SERIES if SOC_FAMILY_SILABS_S2
-	select PINCTRL if SOC_FAMILY_SILABS_S2
-	help
-	  Enable the SPI peripherals on Gecko
diff --git a/drivers/spi/Kconfig.mcux_lpspi b/drivers/spi/Kconfig.mcux_lpspi
deleted file mode 100644
index 20e2c4bed91..00000000000
--- a/drivers/spi/Kconfig.mcux_lpspi
+++ /dev/null
@@ -1,36 +0,0 @@
-# MCUXpresso SDK SPI
-
-# Copyright (c) 2018, NXP
-# SPDX-License-Identifier: Apache-2.0
-
-config SPI_MCUX_LPSPI
-	bool "MCUX LPSPI driver"
-	default y
-	depends on DT_HAS_NXP_LPSPI_ENABLED
-	depends on CLOCK_CONTROL
-	select PINCTRL
-	help
-	  Enable support for MCUX LPSPI driver.
-
-if SPI_MCUX_LPSPI
-config SPI_MCUX_LPSPI_DMA
-	bool "MCUX LPSPI SPI DMA Support"
-	select DMA
-	help
-	  Enable the SPI DMA mode for SPI instances
-	  that enable dma channels in their device tree node.
-
-if SPI_RTIO
-config SPI_MCUX_RTIO_SQ_SIZE
-	int "number of available submission queue entries"
-	default 8 # sensible default that covers most common spi transactions
-	help
-	  when rtio is use with spi each driver holds a context with which blocking
-	  api calls use to perform spi transactions. this queue needs to be as deep
-	  as the longest set of spi_buf_sets used, where normal spi operations are
-	  used (equal length buffers). it may need to be slightly deeper where the
-	  spi buffer sets for transmit/receive are not always matched equally in
-	  length as these are transformed into normal transceives.
-endif # SPI_RTIO
-
-endif # SPI_MCUX_LPSPI
diff --git a/drivers/spi/Kconfig.pl022 b/drivers/spi/Kconfig.pl022
index 65a0d0aedc3..4a0b00a74c9 100644
--- a/drivers/spi/Kconfig.pl022
+++ b/drivers/spi/Kconfig.pl022
@@ -4,7 +4,7 @@
 config SPI_PL022
 	default y
 	depends on DT_HAS_ARM_PL022_ENABLED
-	select PINCTRL if DT_HAS_RASPBERRYPI_PICO_SPI_ENABLED
+	select PINCTRL if $(dt_compat_any_has_prop,$(DT_COMPAT_ARM_PL022),pinctrl-0)
 	bool "ARM PL022 SPI driver"
 
 if SPI_PL022
diff --git a/drivers/spi/Kconfig.renesas_ra b/drivers/spi/Kconfig.renesas_ra
index f0e012d98ec..a7ae2c1d0c9 100644
--- a/drivers/spi/Kconfig.renesas_ra
+++ b/drivers/spi/Kconfig.renesas_ra
@@ -26,10 +26,10 @@ config SPI_RA_DTC
 	  Enable the SPI DTC mode for SPI instances
 
 config SPI_USE_HW_SS
-	bool "RA MCU SPI Hardware Slave Select support"
+	bool "RA MCU SPI Hardware Peripheral Select support"
 	default y
-	depends on !SOC_SERIES_RA2A1
+	depends on !(SOC_SERIES_RA2A1 || SOC_SERIES_RA4M1)
 	help
-	  Use Slave Select pin instead of software Slave Select.
+	  Use Hardware Peripheral Select instead of Software Peripheral Select.
 
 endif # SPI_RENESAS_RA
diff --git a/drivers/spi/Kconfig.rpi_pico b/drivers/spi/Kconfig.rpi_pico
index 70bd45f19ec..64d15b40daf 100644
--- a/drivers/spi/Kconfig.rpi_pico
+++ b/drivers/spi/Kconfig.rpi_pico
@@ -2,11 +2,11 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SPI_RPI_PICO_PIO
-	bool "Raspberry Pi PICO PIO SPI controller driver"
+	bool "Raspberry Pi Pico PIO SPI controller driver"
 	default y
 	depends on DT_HAS_RASPBERRYPI_PICO_SPI_PIO_ENABLED
 	select PICOSDK_USE_PIO
 	select PICOSDK_USE_CLAIM
 	select PINCTRL
 	help
-	  Enable driving SPI via PIO on the PICO
+	  Enable driving SPI via PIO on the Pico
diff --git a/drivers/spi/Kconfig.silabs_eusart b/drivers/spi/Kconfig.silabs_eusart
new file mode 100644
index 00000000000..a2644fd13ed
--- /dev/null
+++ b/drivers/spi/Kconfig.silabs_eusart
@@ -0,0 +1,28 @@
+# Silabs EUSART SPI configuration option
+
+# Copyright (c) 2024 Daikin Comfort Technologies North America, Inc.
+# Copyright (c) 2025 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SPI_SILABS_EUSART
+	bool "Silabs EUSART SPI controller driver"
+	default y
+	depends on DT_HAS_SILABS_EUSART_SPI_ENABLED
+	depends on GPIO
+	select SOC_GECKO_EUSART
+	select PINCTRL if SOC_FAMILY_SILABS_S2
+	help
+	  Enable the EUSART SPI driver
+
+config SPI_SILABS_EUSART_DMA
+	bool "Silabs EUSART SPI controller driver DMA enabled transfer"
+	depends on SPI_SILABS_EUSART
+	select DMA
+	default y if SPI_ASYNC
+
+config SPI_SILABS_EUSART_DMA_MAX_BLOCKS
+	int "Silabs EUSART SPI controller driver maximum DMA transfer block per channel for a transaction."
+	depends on SPI_SILABS_EUSART_DMA
+	default 8
+	help
+	  One block is needed for every chunk found in the SPI transaction and every 2048 bytes
diff --git a/drivers/spi/Kconfig.silabs_usart b/drivers/spi/Kconfig.silabs_usart
new file mode 100644
index 00000000000..23a93a57847
--- /dev/null
+++ b/drivers/spi/Kconfig.silabs_usart
@@ -0,0 +1,15 @@
+# Silabs USART SPI configuration option
+
+# Copyright (c) 2019 Christian Taedcke <hacking@taedcke.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SPI_SILABS_USART
+	bool "Silabs USART SPI controller driver"
+	default y
+	depends on DT_HAS_SILABS_USART_SPI_ENABLED
+	depends on GPIO
+	select SOC_GECKO_USART
+	select CLOCK_CONTROL_SILABS_SERIES if SOC_FAMILY_SILABS_S2
+	select PINCTRL if SOC_FAMILY_SILABS_S2
+	help
+	  Enable the USART SPI driver
diff --git a/drivers/spi/Kconfig.stm32 b/drivers/spi/Kconfig.stm32
index 895cc2c190d..60fe2742bab 100644
--- a/drivers/spi/Kconfig.stm32
+++ b/drivers/spi/Kconfig.stm32
@@ -8,7 +8,6 @@ menuconfig SPI_STM32
 	default y
 	depends on DT_HAS_ST_STM32_SPI_ENABLED
 	select PINCTRL
-	select USE_STM32_LL_SPI
 	help
 	  Enable SPI support on the STM32 family of processors.
 
diff --git a/drivers/spi/spi_ambiq_bleif.c b/drivers/spi/spi_ambiq_bleif.c
index 299920842ff..075edc4f802 100644
--- a/drivers/spi/spi_ambiq_bleif.c
+++ b/drivers/spi/spi_ambiq_bleif.c
@@ -21,17 +21,12 @@ LOG_MODULE_REGISTER(spi_ambiq_bleif);
 #include <stdlib.h>
 #include <errno.h>
 #include "spi_context.h"
-#include <am_mcu_apollo.h>
-
-#define PWRCTRL_MAX_WAIT_US 5
-
-typedef int (*ambiq_spi_pwr_func_t)(void);
+#include <soc.h>
 
 struct spi_ambiq_config {
 	uint32_t base;
 	int size;
 	const struct pinctrl_dev_config *pcfg;
-	ambiq_spi_pwr_func_t pwr_func;
 };
 
 struct spi_ambiq_data {
@@ -170,17 +165,18 @@ static DEVICE_API(spi, spi_ambiq_driver_api) = {
 static int spi_ambiq_init(const struct device *dev)
 {
 	struct spi_ambiq_data *data = dev->data;
-	const struct spi_ambiq_config *cfg = dev->config;
 	int ret;
 
 #if defined(CONFIG_SPI_AMBIQ_BLEIF_TIMING_TRACE)
+	const struct spi_ambiq_config *cfg = dev->config;
+
 	ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
 	if (ret) {
 		return ret;
 	}
 #endif /* CONFIG_SPI_AMBIQ_BLEIF_TIMING_TRACE */
 
-	ret = am_hal_ble_initialize((cfg->base - BLEIF_BASE) / cfg->size, &data->BLEhandle);
+	ret = am_hal_ble_initialize(0, &data->BLEhandle);
 	if (ret) {
 		return ret;
 	}
@@ -190,29 +186,18 @@ static int spi_ambiq_init(const struct device *dev)
 		return ret;
 	}
 
-	ret = cfg->pwr_func();
-
 	return ret;
 }
 
 #define AMBIQ_SPI_BLEIF_INIT(n)                                                                    \
 	PINCTRL_DT_INST_DEFINE(n);                                                                 \
-	static int pwr_on_ambiq_spi_##n(void)                                                      \
-	{                                                                                          \
-		uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) +                    \
-				DT_INST_PHA(n, ambiq_pwrcfg, offset);                              \
-		sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr);        \
-		k_busy_wait(PWRCTRL_MAX_WAIT_US);                                                  \
-		return 0;                                                                          \
-	}                                                                                          \
 	static struct spi_ambiq_data spi_ambiq_data##n = {                                         \
 		SPI_CONTEXT_INIT_LOCK(spi_ambiq_data##n, ctx),                                     \
 		SPI_CONTEXT_INIT_SYNC(spi_ambiq_data##n, ctx)};                                    \
 	static const struct spi_ambiq_config spi_ambiq_config##n = {                               \
 		.base = DT_INST_REG_ADDR(n),                                                       \
 		.size = DT_INST_REG_SIZE(n),                                                       \
-		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                         \
-		.pwr_func = pwr_on_ambiq_spi_##n};                                                 \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n)};                                        \
 	SPI_DEVICE_DT_INST_DEFINE(n, spi_ambiq_init, NULL, &spi_ambiq_data##n,                     \
 				  &spi_ambiq_config##n, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,     \
 				  &spi_ambiq_driver_api);
diff --git a/drivers/spi/spi_ambiq_spic.c b/drivers/spi/spi_ambiq_spic.c
index 19e7bf1d145..3f65b8496dd 100644
--- a/drivers/spi/spi_ambiq_spic.c
+++ b/drivers/spi/spi_ambiq_spic.c
@@ -21,18 +21,32 @@ LOG_MODULE_REGISTER(spi_ambiq);
 #include <stdlib.h>
 #include <errno.h>
 #include "spi_context.h"
-#include <am_mcu_apollo.h>
+#include <soc.h>
 
-#define PWRCTRL_MAX_WAIT_US 5
+#include <zephyr/mem_mgmt/mem_attr.h>
 
-typedef int (*ambiq_spi_pwr_func_t)(void);
+#ifdef CONFIG_DCACHE
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#endif /* CONFIG_DCACHE */
+
+#ifdef CONFIG_NOCACHE_MEMORY
+#include <zephyr/linker/linker-defs.h>
+#elif defined(CONFIG_CACHE_MANAGEMENT)
+#include <zephyr/arch/cache.h>
+#endif /* CONFIG_NOCACHE_MEMORY */
+
+#if defined(CONFIG_DCACHE) && !defined(CONFIG_NOCACHE_MEMORY)
+#define SPI_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED 1
+#else
+#define SPI_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED 0
+#endif /* defined(CONFIG_DCACHE) && !defined(CONFIG_NOCACHE_MEMORY) */
 
 struct spi_ambiq_config {
 	uint32_t base;
 	int size;
+	int inst_idx;
 	uint32_t clock_freq;
 	const struct pinctrl_dev_config *pcfg;
-	ambiq_spi_pwr_func_t pwr_func;
 	void (*irq_config_func)(void);
 };
 
@@ -40,7 +54,6 @@ struct spi_ambiq_data {
 	struct spi_context ctx;
 	am_hal_iom_config_t iom_cfg;
 	void *iom_handler;
-	int inst_idx;
 	bool cont;
 	bool pm_policy_state_on;
 };
@@ -76,9 +89,15 @@ static void spi_ambiq_pm_policy_state_lock_put(const struct device *dev)
 }
 
 #ifdef CONFIG_SPI_AMBIQ_DMA
+/*
+ * If Nocache Memory is supported, buffer will be placed in nocache region by
+ * the linker to avoid potential DMA cache-coherency problems.
+ * If Nocache Memory is not supported, cache coherency might need to be kept
+ * manually. See SPI_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED.
+ */
 static __aligned(32) struct {
 	__aligned(32) uint32_t buf[CONFIG_SPI_DMA_TCB_BUFFER_SIZE];
-} spi_dma_tcb_buf[DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT)] __attribute__((__section__(".nocache")));
+} spi_dma_tcb_buf[DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT)] __nocache;
 
 static void spi_ambiq_callback(void *callback_ctxt, uint32_t status)
 {
@@ -92,6 +111,41 @@ static void spi_ambiq_callback(void *callback_ctxt, uint32_t status)
 	}
 	spi_context_complete(ctx, dev, (status == AM_HAL_STATUS_SUCCESS) ? 0 : -EIO);
 }
+
+#ifdef CONFIG_DCACHE
+static bool buf_in_nocache(uintptr_t buf, size_t len_bytes)
+{
+	bool buf_within_nocache = false;
+
+#ifdef CONFIG_NOCACHE_MEMORY
+	/* Check if buffer is in nocache region defined by the linker */
+	buf_within_nocache = (buf >= ((uintptr_t)_nocache_ram_start)) &&
+			     ((buf + len_bytes - 1) <= ((uintptr_t)_nocache_ram_end));
+	if (buf_within_nocache) {
+		return true;
+	}
+#endif /* CONFIG_NOCACHE_MEMORY */
+
+	/* Check if buffer is in nocache memory region defined in DT */
+	buf_within_nocache =
+		mem_attr_check_buf((void *)buf, len_bytes, DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)) == 0;
+
+	return buf_within_nocache;
+}
+
+static bool spi_buf_set_in_nocache(const struct spi_buf_set *bufs)
+{
+	for (size_t i = 0; i < bufs->count; i++) {
+		const struct spi_buf *buf = &bufs->buffers[i];
+
+		if (!buf_in_nocache((uintptr_t)buf->buf, buf->len)) {
+			return false;
+		}
+	}
+	return true;
+}
+#endif /* CONFIG_DCACHE */
+
 #endif
 
 static void spi_ambiq_reset(const struct device *dev)
@@ -190,7 +244,7 @@ static int spi_config(const struct device *dev, const struct spi_config *config)
 	ctx->config = config;
 
 #ifdef CONFIG_SPI_AMBIQ_DMA
-	data->iom_cfg.pNBTxnBuf = spi_dma_tcb_buf[data->inst_idx].buf;
+	data->iom_cfg.pNBTxnBuf = spi_dma_tcb_buf[cfg->inst_idx].buf;
 	data->iom_cfg.ui32NBTxnBufLength = CONFIG_SPI_DMA_TCB_BUFFER_SIZE;
 #endif
 
@@ -239,6 +293,13 @@ static int spi_ambiq_xfer_half_duplex(const struct device *dev, am_hal_iom_dir_e
 			is_last = true;
 		}
 #ifdef CONFIG_SPI_AMBIQ_DMA
+#if SPI_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED
+		/* Clean Dcache before DMA write */
+		if ((trans.eDirection == AM_HAL_IOM_TX) && (trans.pui32TxBuffer)) {
+			sys_cache_data_flush_range((void *)trans.pui32TxBuffer,
+							    trans.ui32NumBytes);
+		}
+#endif /* SPI_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED */
 		if (AM_HAL_STATUS_SUCCESS !=
 		    am_hal_iom_nonblocking_transfer(data->iom_handler, &trans,
 						    ((is_last == true) ? spi_ambiq_callback : NULL),
@@ -247,6 +308,13 @@ static int spi_ambiq_xfer_half_duplex(const struct device *dev, am_hal_iom_dir_e
 		}
 		if (is_last) {
 			ret = spi_context_wait_for_completion(ctx);
+#if SPI_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED
+			/* Invalidate Dcache after DMA read */
+			if ((trans.eDirection == AM_HAL_IOM_RX) && (trans.pui32RxBuffer)) {
+				sys_cache_data_invd_range((void *)trans.pui32RxBuffer,
+								    trans.ui32NumBytes);
+			}
+#endif /* SPI_AMBIQ_MANUAL_CACHE_COHERENCY_REQUIRED */
 		}
 #else
 		ret = am_hal_iom_blocking_transfer(data->iom_handler, &trans);
@@ -375,6 +443,13 @@ static int spi_ambiq_transceive(const struct device *dev, const struct spi_confi
 		return 0;
 	}
 
+#if defined(CONFIG_SPI_AMBIQ_DMA) && defined(CONFIG_DCACHE)
+	if ((tx_bufs != NULL && !spi_buf_set_in_nocache(tx_bufs)) ||
+	    (rx_bufs != NULL && !spi_buf_set_in_nocache(rx_bufs))) {
+		return -EFAULT;
+	}
+#endif /* CONFIG_DCACHE */
+
 	/* context setup */
 	spi_context_lock(&data->ctx, false, NULL, NULL, config);
 
@@ -431,13 +506,12 @@ static int spi_ambiq_init(const struct device *dev)
 	const struct spi_ambiq_config *cfg = dev->config;
 	int ret = 0;
 
-	if (AM_HAL_STATUS_SUCCESS !=
-	    am_hal_iom_initialize((cfg->base - IOM0_BASE) / cfg->size, &data->iom_handler)) {
+	if (AM_HAL_STATUS_SUCCESS != am_hal_iom_initialize(cfg->inst_idx, &data->iom_handler)) {
 		LOG_ERR("Fail to initialize SPI\n");
 		return -ENXIO;
 	}
 
-	ret = cfg->pwr_func();
+	ret = am_hal_iom_power_ctrl(data->iom_handler, AM_HAL_SYSCTRL_WAKE, false);
 
 	ret |= pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
 	ret |= spi_context_cs_configure_all(&data->ctx);
@@ -491,31 +565,24 @@ static int spi_ambiq_pm_action(const struct device *dev, enum pm_device_action a
 
 #define AMBIQ_SPI_INIT(n)                                                                          \
 	PINCTRL_DT_INST_DEFINE(n);                                                                 \
-	static int pwr_on_ambiq_spi_##n(void)                                                      \
-	{                                                                                          \
-		uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) +                    \
-				DT_INST_PHA(n, ambiq_pwrcfg, offset);                              \
-		sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr);        \
-		k_busy_wait(PWRCTRL_MAX_WAIT_US);                                                  \
-		return 0;                                                                          \
-	}                                                                                          \
 	static void spi_irq_config_func_##n(void)                                                  \
 	{                                                                                          \
-		IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), spi_ambiq_isr,              \
-			    DEVICE_DT_INST_GET(n), 0);                                             \
-		irq_enable(DT_INST_IRQN(n));                                                       \
+		IRQ_CONNECT(DT_IRQN(DT_INST_PARENT(n)), DT_IRQ(DT_INST_PARENT(n), priority),       \
+			    spi_ambiq_isr, DEVICE_DT_INST_GET(n), 0);                              \
+		irq_enable(DT_IRQN(DT_INST_PARENT(n)));                                            \
 	};                                                                                         \
 	static struct spi_ambiq_data spi_ambiq_data##n = {                                         \
 		SPI_CONTEXT_INIT_LOCK(spi_ambiq_data##n, ctx),                                     \
 		SPI_CONTEXT_INIT_SYNC(spi_ambiq_data##n, ctx),                                     \
-		SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx).inst_idx = n};                \
+		SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx)};                             \
 	static const struct spi_ambiq_config spi_ambiq_config##n = {                               \
-		.base = DT_INST_REG_ADDR(n),                                                       \
-		.size = DT_INST_REG_SIZE(n),                                                       \
+		.base = DT_REG_ADDR(DT_INST_PARENT(n)),                                            \
+		.size = DT_REG_SIZE(DT_INST_PARENT(n)),                                            \
+		.inst_idx =                                                                        \
+			(DT_REG_ADDR(DT_INST_PARENT(n)) - IOM0_BASE) / (IOM1_BASE - IOM0_BASE),    \
 		.clock_freq = DT_INST_PROP(n, clock_frequency),                                    \
 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                         \
-		.irq_config_func = spi_irq_config_func_##n,                                        \
-		.pwr_func = pwr_on_ambiq_spi_##n};                                                 \
+		.irq_config_func = spi_irq_config_func_##n};                                       \
 	PM_DEVICE_DT_INST_DEFINE(n, spi_ambiq_pm_action);                                          \
 	SPI_DEVICE_DT_INST_DEFINE(n, spi_ambiq_init, PM_DEVICE_DT_INST_GET(n), &spi_ambiq_data##n, \
 				  &spi_ambiq_config##n, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,     \
diff --git a/drivers/spi/spi_ambiq_spid.c b/drivers/spi/spi_ambiq_spid.c
index 822332ac93a..9967cadb464 100644
--- a/drivers/spi/spi_ambiq_spid.c
+++ b/drivers/spi/spi_ambiq_spid.c
@@ -20,18 +20,15 @@ LOG_MODULE_REGISTER(spi_ambiq_spid);
 #include <stdlib.h>
 #include <errno.h>
 #include "spi_context.h"
-#include <am_mcu_apollo.h>
-
-#define AMBIQ_SPID_PWRCTRL_MAX_WAIT_US 5
-
-typedef int (*ambiq_spi_pwr_func_t)(void);
+#include <soc.h>
 
+#define SPID_ADDR_INTERVAL 1
 struct spi_ambiq_config {
 	const struct gpio_dt_spec int_gpios;
 	uint32_t base;
 	int size;
+	int inst_idx;
 	const struct pinctrl_dev_config *pcfg;
-	ambiq_spi_pwr_func_t pwr_func;
 	void (*irq_config_func)(void);
 };
 
@@ -39,7 +36,6 @@ struct spi_ambiq_data {
 	struct spi_context ctx;
 	am_hal_ios_config_t ios_cfg;
 	void *ios_handler;
-	int inst_idx;
 	struct k_sem spim_wrcmp_sem;
 };
 
@@ -336,13 +332,12 @@ static int spi_ambiq_init(const struct device *dev)
 	const struct spi_ambiq_config *cfg = dev->config;
 	int ret = 0;
 
-	if (AM_HAL_STATUS_SUCCESS !=
-	    am_hal_ios_initialize((cfg->base - IOSLAVE_BASE) / cfg->size, &data->ios_handler)) {
+	if (AM_HAL_STATUS_SUCCESS != am_hal_ios_initialize(cfg->inst_idx, &data->ios_handler)) {
 		LOG_ERR("Fail to initialize SPID\n");
 		return -ENXIO;
 	}
 
-	ret = cfg->pwr_func();
+	ret = am_hal_ios_power_ctrl(data->ios_handler, AM_HAL_SYSCTRL_WAKE, false);
 
 	ret |= pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
 	if (ret < 0) {
@@ -396,14 +391,6 @@ static int spi_ambiq_pm_action(const struct device *dev, enum pm_device_action a
 
 #define AMBIQ_SPID_INIT(n)                                                                         \
 	PINCTRL_DT_INST_DEFINE(n);                                                                 \
-	static int pwr_on_ambiq_spi_##n(void)                                                      \
-	{                                                                                          \
-		uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) +                    \
-				DT_INST_PHA(n, ambiq_pwrcfg, offset);                              \
-		sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr);        \
-		k_busy_wait(AMBIQ_SPID_PWRCTRL_MAX_WAIT_US);                                       \
-		return 0;                                                                          \
-	}                                                                                          \
 	static void spi_irq_config_func_##n(void)                                                  \
 	{                                                                                          \
 		IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), spi_ambiq_isr,              \
@@ -413,15 +400,14 @@ static int spi_ambiq_pm_action(const struct device *dev, enum pm_device_action a
 	static struct spi_ambiq_data spi_ambiq_data##n = {                                         \
 		SPI_CONTEXT_INIT_LOCK(spi_ambiq_data##n, ctx),                                     \
 		SPI_CONTEXT_INIT_SYNC(spi_ambiq_data##n, ctx),                                     \
-		.spim_wrcmp_sem = Z_SEM_INITIALIZER(spi_ambiq_data##n.spim_wrcmp_sem, 0, 1),       \
-		.inst_idx = n};                                                                    \
+		.spim_wrcmp_sem = Z_SEM_INITIALIZER(spi_ambiq_data##n.spim_wrcmp_sem, 0, 1)};      \
 	static const struct spi_ambiq_config spi_ambiq_config##n = {                               \
 		.int_gpios = GPIO_DT_SPEC_INST_GET(n, int_gpios),                                  \
 		.base = DT_INST_REG_ADDR(n),                                                       \
 		.size = DT_INST_REG_SIZE(n),                                                       \
+		.inst_idx = (DT_INST_REG_ADDR(n) - IOSLAVE_BASE) / SPID_ADDR_INTERVAL,             \
 		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                         \
-		.irq_config_func = spi_irq_config_func_##n,                                        \
-		.pwr_func = pwr_on_ambiq_spi_##n};                                                 \
+		.irq_config_func = spi_irq_config_func_##n};                                       \
 	PM_DEVICE_DT_INST_DEFINE(n, spi_ambiq_pm_action);                                          \
 	SPI_DEVICE_DT_INST_DEFINE(n, spi_ambiq_init, PM_DEVICE_DT_INST_GET(n), &spi_ambiq_data##n, \
 				  &spi_ambiq_config##n, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,     \
diff --git a/drivers/spi/spi_b_renesas_ra8.c b/drivers/spi/spi_b_renesas_ra8.c
index d2fbc3a8f79..6f015eed0cb 100644
--- a/drivers/spi/spi_b_renesas_ra8.c
+++ b/drivers/spi/spi_b_renesas_ra8.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -402,10 +402,9 @@ static int ra_spi_b_release(const struct device *dev, const struct spi_config *c
 
 static DEVICE_API(spi, ra_spi_driver_api) = {.transceive = ra_spi_b_transceive,
 #ifdef CONFIG_SPI_ASYNC
-							.transceive_async =
-								ra_spi_b_transceive_async,
+					     .transceive_async = ra_spi_b_transceive_async,
 #endif /* CONFIG_SPI_ASYNC */
-							.release = ra_spi_b_release};
+					     .release = ra_spi_b_release};
 
 static spi_b_clock_source_t ra_spi_b_clock_name(const struct device *clock_dev)
 {
@@ -604,15 +603,10 @@ static void ra_spi_eri_isr(const struct device *dev)
 }
 #endif
 
-#define _ELC_EVENT_SPI_RXI(channel) ELC_EVENT_SPI##channel##_RXI
-#define _ELC_EVENT_SPI_TXI(channel) ELC_EVENT_SPI##channel##_TXI
-#define _ELC_EVENT_SPI_TEI(channel) ELC_EVENT_SPI##channel##_TEI
-#define _ELC_EVENT_SPI_ERI(channel) ELC_EVENT_SPI##channel##_ERI
-
-#define ELC_EVENT_SPI_RXI(channel) _ELC_EVENT_SPI_RXI(channel)
-#define ELC_EVENT_SPI_TXI(channel) _ELC_EVENT_SPI_TXI(channel)
-#define ELC_EVENT_SPI_TEI(channel) _ELC_EVENT_SPI_TEI(channel)
-#define ELC_EVENT_SPI_ERI(channel) _ELC_EVENT_SPI_ERI(channel)
+#define EVENT_SPI_RXI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_SPI, channel, _RXI))
+#define EVENT_SPI_TXI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_SPI, channel, _TXI))
+#define EVENT_SPI_TEI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_SPI, channel, _TEI))
+#define EVENT_SPI_ERI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_SPI, channel, _ERI))
 
 #if defined(CONFIG_SPI_B_INTERRUPT)
 
@@ -621,13 +615,13 @@ static void ra_spi_eri_isr(const struct device *dev)
 		ARG_UNUSED(dev);                                                                   \
                                                                                                    \
 		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, rxi, irq)] =                               \
-			ELC_EVENT_SPI_RXI(DT_INST_PROP(index, channel));                           \
+			EVENT_SPI_RXI(DT_INST_PROP(index, channel));                               \
 		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, txi, irq)] =                               \
-			ELC_EVENT_SPI_TXI(DT_INST_PROP(index, channel));                           \
+			EVENT_SPI_TXI(DT_INST_PROP(index, channel));                               \
 		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, tei, irq)] =                               \
-			ELC_EVENT_SPI_TEI(DT_INST_PROP(index, channel));                           \
+			EVENT_SPI_TEI(DT_INST_PROP(index, channel));                               \
 		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, eri, irq)] =                               \
-			ELC_EVENT_SPI_ERI(DT_INST_PROP(index, channel));                           \
+			EVENT_SPI_ERI(DT_INST_PROP(index, channel));                               \
                                                                                                    \
 		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, rxi, irq),                                  \
 			    DT_INST_IRQ_BY_NAME(index, rxi, priority), ra_spi_rxi_isr,             \
diff --git a/drivers/spi/spi_cc13xx_cc26xx.c b/drivers/spi/spi_cc13xx_cc26xx.c
index 26a4ad4007c..68a28fbadc1 100644
--- a/drivers/spi/spi_cc13xx_cc26xx.c
+++ b/drivers/spi/spi_cc13xx_cc26xx.c
@@ -81,8 +81,9 @@ static int spi_cc13xx_cc26xx_configure(const struct device *dev,
 		return -EINVAL;
 	}
 
-	if (config->frequency < 2000000) {
-		LOG_ERR("Frequencies lower than 2 MHz are not supported");
+	if (config->frequency < CPU_FREQ / (254 * (255 + 1))) {
+		LOG_ERR("Frequencies lower than %d Hz are not supported",
+			CPU_FREQ / (254 * (255 + 1)));
 		return -EINVAL;
 	}
 
diff --git a/drivers/spi/spi_cc23x0.c b/drivers/spi/spi_cc23x0.c
new file mode 100644
index 00000000000..0c6e0009fc1
--- /dev/null
+++ b/drivers/spi/spi_cc23x0.c
@@ -0,0 +1,350 @@
+/*
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ti_cc23x0_spi
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(spi_cc23x0, CONFIG_SPI_LOG_LEVEL);
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/irq.h>
+#include <zephyr/sys/util.h>
+
+#include <driverlib/clkctl.h>
+#include <driverlib/spi.h>
+
+#include "spi_context.h"
+
+/*
+ * SPI bit rate = (SPI functional clock frequency) / ((SCR + 1) * 2)
+ * Serial clock divider value (SCR) can be from 0 to 1023.
+ */
+#define SPI_CC23_MIN_FREQ	DIV_ROUND_UP(TI_CC23X0_DT_CPU_CLK_FREQ_HZ, 2048)
+#define SPI_CC23_MAX_FREQ	(TI_CC23X0_DT_CPU_CLK_FREQ_HZ >> 1)
+
+#define SPI_CC23_DATA_WIDTH	8
+#define SPI_CC23_DFS		(SPI_CC23_DATA_WIDTH >> 3)
+
+#define SPI_CC23_INT_MASK	(SPI_TXEMPTY | SPI_IDLE | SPI_RX)
+
+struct spi_cc23x0_config {
+	uint32_t base;
+	const struct pinctrl_dev_config *pincfg;
+	void (*irq_config_func)(void);
+};
+
+struct spi_cc23x0_data {
+	struct spi_context ctx;
+	size_t tx_len_left;
+	uint32_t tx_count;
+	uint32_t rx_count;
+	bool xfer_done;
+};
+
+static void spi_cc23x0_isr(const struct device *dev)
+{
+	const struct spi_cc23x0_config *cfg = dev->config;
+	struct spi_cc23x0_data *data = dev->data;
+	struct spi_context *ctx = &data->ctx;
+	uint32_t txd = 0, rxd;
+	uint32_t status;
+
+	status = SPIIntStatus(cfg->base, true);
+	LOG_DBG("status = %08x", status);
+
+	/*
+	 * Disabling the interrupts in this ISR when SPI has completed
+	 * the transfer triggers a subsequent spurious interrupt, with
+	 * a null status. Let's ignore this event.
+	 */
+	if (!status) {
+		return;
+	}
+
+	if (status & SPI_RX) {
+		/* Rx FIFO contains 1 byte */
+		LOG_DBG("SPI_RX");
+
+		SPIClearInt(cfg->base, SPI_RX);
+
+		SPIGetDataNonBlocking(cfg->base, &rxd);
+
+		if (spi_context_rx_buf_on(ctx)) {
+			*ctx->rx_buf = rxd;
+			spi_context_update_rx(ctx, SPI_CC23_DFS, 1);
+		}
+
+		data->rx_count++;
+	}
+
+	if (status & SPI_IDLE) {
+		/* The byte has been transferred and SPI has moved to idle mode */
+		LOG_DBG("SPI_IDLE (tx_len_left = %d)", data->tx_len_left);
+
+		SPIClearInt(cfg->base, SPI_IDLE);
+
+		if (!data->tx_len_left) {
+			LOG_DBG("xfer_done");
+			data->xfer_done = true;
+		}
+	}
+
+	/*
+	 * Do not push a new Tx byte in the Tx FIFO while the current Rx byte (if any)
+	 * has not been pulled from the Rx FIFO. In other words, Tx count and Rx count
+	 * must be equal so a new Tx byte can be pushed.
+	 */
+	if (status & SPI_TXEMPTY && !data->xfer_done && data->tx_count == data->rx_count) {
+		/*
+		 * The previous byte in the Tx FIFO (if any) has been moved
+		 * to the shift register
+		 */
+		LOG_DBG("SPI_TXEMPTY");
+
+		SPIClearInt(cfg->base, SPI_TXEMPTY);
+
+		if (spi_context_tx_buf_on(ctx)) {
+			txd = *ctx->tx_buf;
+			spi_context_update_tx(ctx, SPI_CC23_DFS, 1);
+		}
+
+		SPIPutDataNonBlocking(cfg->base, txd);
+
+		data->tx_count++;
+		data->tx_len_left--;
+	}
+
+	if (data->xfer_done) {
+		LOG_DBG("complete");
+		SPIDisableInt(cfg->base, SPI_CC23_INT_MASK);
+		spi_context_complete(ctx, dev, 0);
+	}
+}
+
+static int spi_cc23x0_configure(const struct device *dev,
+				const struct spi_config *config)
+{
+	const struct spi_cc23x0_config *cfg = dev->config;
+	struct spi_cc23x0_data *data = dev->data;
+	uint32_t protocol;
+
+	if (spi_context_configured(&data->ctx, config)) {
+		/* Nothing to do */
+		return 0;
+	}
+
+	if (config->operation & SPI_HALF_DUPLEX) {
+		LOG_ERR("Half-duplex is not supported");
+		return -ENOTSUP;
+	}
+
+	/* Peripheral mode has not been implemented */
+	if (SPI_OP_MODE_GET(config->operation) != SPI_OP_MODE_MASTER) {
+		LOG_ERR("Peripheral mode is not supported");
+		return -ENOTSUP;
+	}
+
+	/* Word sizes other than 8 bits has not been implemented */
+	if (SPI_WORD_SIZE_GET(config->operation) != SPI_CC23_DATA_WIDTH) {
+		LOG_ERR("Word sizes other than %d bits are not supported", SPI_CC23_DATA_WIDTH);
+		return -ENOTSUP;
+	}
+
+	if (config->operation & SPI_TRANSFER_LSB) {
+		LOG_ERR("Transfer LSB first mode is not supported");
+		return -EINVAL;
+	}
+
+	if (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES) &&
+	    (config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
+		LOG_ERR("Multiple lines are not supported");
+		return -EINVAL;
+	}
+
+	if (config->operation & SPI_CS_ACTIVE_HIGH && !spi_cs_is_gpio(config)) {
+		LOG_ERR("Active high CS requires emulation through a GPIO line");
+		return -EINVAL;
+	}
+
+	if (config->frequency < SPI_CC23_MIN_FREQ) {
+		LOG_ERR("Frequencies lower than %d Hz are not supported", SPI_CC23_MIN_FREQ);
+		return -EINVAL;
+	}
+
+	if (config->frequency > SPI_CC23_MAX_FREQ) {
+		LOG_ERR("Frequency greater than %d Hz are not supported", SPI_CC23_MAX_FREQ);
+		return -EINVAL;
+	}
+
+	if (SPI_MODE_GET(config->operation) & SPI_MODE_CPOL) {
+		if (SPI_MODE_GET(config->operation) & SPI_MODE_CPHA) {
+			protocol = SPI_FRF_MOTO_MODE_7;
+		} else {
+			protocol = SPI_FRF_MOTO_MODE_6;
+		}
+	} else {
+		if (SPI_MODE_GET(config->operation) & SPI_MODE_CPHA) {
+			protocol = SPI_FRF_MOTO_MODE_5;
+		} else {
+			protocol = SPI_FRF_MOTO_MODE_4;
+		}
+	}
+
+	/* Enable clock */
+	CLKCTLEnable(CLKCTL_BASE, CLKCTL_SPI0);
+
+	/* Disable SPI before making configuration changes */
+	SPIDisable(cfg->base);
+
+	/* Configure SPI */
+	SPIConfigSetExpClk(cfg->base, TI_CC23X0_DT_CPU_CLK_FREQ_HZ,
+			   protocol, SPI_MODE_CONTROLLER,
+			   config->frequency, SPI_CC23_DATA_WIDTH);
+
+	data->ctx.config = config;
+
+	/* Configure Rx FIFO level */
+	HWREG(cfg->base + SPI_O_IFLS) = SPI_IFLS_RXSEL_LEVEL_1;
+
+	/* Re-enable SPI after making configuration changes */
+	SPIEnable(cfg->base);
+
+	return 0;
+}
+
+static void spi_cc23x0_initialize_data(struct spi_cc23x0_data *data)
+{
+	data->tx_len_left = MAX(spi_context_total_tx_len(&data->ctx),
+				spi_context_total_rx_len(&data->ctx));
+	data->tx_count = 0;
+	data->rx_count = 0;
+	data->xfer_done = false;
+}
+
+static int spi_cc23x0_transceive(const struct device *dev,
+				 const struct spi_config *config,
+				 const struct spi_buf_set *tx_bufs,
+				 const struct spi_buf_set *rx_bufs)
+{
+	const struct spi_cc23x0_config *cfg = dev->config;
+	struct spi_cc23x0_data *data = dev->data;
+	struct spi_context *ctx = &data->ctx;
+	int ret;
+
+	spi_context_lock(ctx, false, NULL, NULL, config);
+
+	ret = spi_cc23x0_configure(dev, config);
+	if (ret) {
+		goto ctx_release;
+	}
+
+	spi_context_buffers_setup(ctx, tx_bufs, rx_bufs, SPI_CC23_DFS);
+
+	spi_cc23x0_initialize_data(data);
+
+	spi_context_cs_control(ctx, true);
+
+	SPIEnableInt(cfg->base, SPI_CC23_INT_MASK);
+
+	ret = spi_context_wait_for_completion(ctx);
+	if (ret) {
+		SPIDisableInt(cfg->base, SPI_CC23_INT_MASK);
+		LOG_ERR("SPI transfer failed (%d)", ret);
+	} else {
+		LOG_DBG("SPI transfer completed");
+	}
+
+	spi_context_cs_control(ctx, false);
+
+ctx_release:
+	spi_context_release(ctx, ret);
+	return ret;
+}
+
+static int spi_cc23x0_release(const struct device *dev,
+			      const struct spi_config *config)
+{
+	const struct spi_cc23x0_config *cfg = dev->config;
+	struct spi_cc23x0_data *data = dev->data;
+
+	if (!spi_context_configured(&data->ctx, config)) {
+		return -EINVAL;
+	}
+
+	if (SPIBusy(cfg->base)) {
+		return -EBUSY;
+	}
+
+	spi_context_unlock_unconditionally(&data->ctx);
+
+	return 0;
+}
+
+static const struct spi_driver_api spi_cc23x0_driver_api = {
+	.transceive = spi_cc23x0_transceive,
+	.release = spi_cc23x0_release,
+};
+
+static int spi_cc23x0_init(const struct device *dev)
+{
+	const struct spi_cc23x0_config *cfg = dev->config;
+	struct spi_cc23x0_data *data = dev->data;
+	int ret;
+
+	cfg->irq_config_func();
+
+	ret = pinctrl_apply_state(cfg->pincfg, PINCTRL_STATE_DEFAULT);
+	if (ret) {
+		LOG_ERR("Failed to apply SPI pinctrl state");
+		return ret;
+	}
+
+	ret = spi_context_cs_configure_all(&data->ctx);
+	if (ret) {
+		return ret;
+	}
+
+	spi_context_unlock_unconditionally(&data->ctx);
+
+	return 0;
+}
+
+#define SPI_CC23X0_INIT(n)						\
+	PINCTRL_DT_INST_DEFINE(n);					\
+									\
+	static void spi_irq_config_func_##n(void)			\
+	{								\
+		IRQ_CONNECT(DT_INST_IRQN(n),				\
+			    DT_INST_IRQ(n, priority),			\
+			    spi_cc23x0_isr,				\
+			    DEVICE_DT_INST_GET(n), 0);			\
+		irq_enable(DT_INST_IRQN(n));				\
+	};								\
+									\
+	static const struct spi_cc23x0_config spi_cc23x0_config_##n = {	\
+		.base = DT_INST_REG_ADDR(n),				\
+		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),		\
+		.irq_config_func = spi_irq_config_func_##n		\
+	};								\
+									\
+	static struct spi_cc23x0_data spi_cc23x0_data_##n = {		\
+		SPI_CONTEXT_INIT_LOCK(spi_cc23x0_data_##n, ctx),	\
+		SPI_CONTEXT_INIT_SYNC(spi_cc23x0_data_##n, ctx),	\
+		SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx)	\
+	};								\
+									\
+	DEVICE_DT_INST_DEFINE(n,					\
+			      spi_cc23x0_init,				\
+			      NULL,					\
+			      &spi_cc23x0_data_##n,			\
+			      &spi_cc23x0_config_##n,			\
+			      POST_KERNEL,				\
+			      CONFIG_SPI_INIT_PRIORITY,			\
+			      &spi_cc23x0_driver_api)
+
+DT_INST_FOREACH_STATUS_OKAY(SPI_CC23X0_INIT)
diff --git a/drivers/spi/spi_cdns.c b/drivers/spi/spi_cdns.c
new file mode 100644
index 00000000000..22c70bc57b9
--- /dev/null
+++ b/drivers/spi/spi_cdns.c
@@ -0,0 +1,871 @@
+/*
+ * Copyright (c) 2024 Meta Platforms
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/sys/sys_io.h>
+#include <zephyr/pm/device.h>
+#include <zephyr/pm/device_runtime.h>
+#include <zephyr/sys/util.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(spi_cadence, CONFIG_SPI_LOG_LEVEL);
+
+#include "spi_context.h"
+
+/*******************************************************************************
+ * Macro Definition
+ ******************************************************************************/
+/* Register offset address */
+#define SPI_CONF             0x00
+#define SPI_INT_STATUS       0x04
+#define SPI_INT_ENABLE       0x08
+#define SPI_INT_DISABLE      0x0c
+#define SPI_INT_MASK         0x10
+#define SPI_SPI_ENABLE       0x14
+#define SPI_DELAY            0x18
+#define SPI_TX_DATA          0x1c
+#define SPI_RX_DATA          0x20
+#define SPI_SLAVE_IDLE_COUNT 0x24
+#define SPI_TX_THRESHOLD     0x28
+#define SPI_RX_THRESHOLD     0x2c
+
+/* Configuration register bit offset */
+#define SPI_CONF_PCSL_OFFSET 10
+#define SPI_CONF_MRCS_OFFSET 8
+#define SPI_CONF_TWS_OFFSET  6
+#define SPI_CONF_MBRD_OFFSET 3
+
+/* Configuration register bit mask */
+#define SPI_CONF_TXCLR     BIT(20)
+#define SPI_CONF_RXCLR     BIT(19)
+#define SPI_CONF_SPSE      BIT(18)
+#define SPI_CONF_MFGE      BIT(17)
+#define SPI_CONF_MSC       BIT(16)
+#define SPI_CONF_MSE       BIT(15)
+#define SPI_CONF_MCSE      BIT(14)
+#define SPI_CONF_PCSL_MASK GENMASK(13, 10)
+#define SPI_CONF_PSD       BIT(9)
+#define SPI_CONF_MRCS      BIT(8)
+#define SPI_CONF_TWS_MASK  GENMASK(7, 6)
+#define SPI_CONF_MBRD_MASK GENMASK(5, 3)
+#define SPI_CONF_CPHA      BIT(2)
+#define SPI_CONF_CPOL      BIT(1)
+#define SPI_CONF_MSEL      BIT(0)
+
+#define SPI_CONF_INITIAL_VAL (SPI_CONF_PCSL_MASK | SPI_CONF_MCSE | SPI_CONF_MRCS | SPI_CONF_MSEL)
+
+/* Interrupt register bit mask */
+#define SPI_INT_TUF BIT(6)
+#define SPI_INT_RF  BIT(5)
+#define SPI_INT_RNE BIT(4)
+#define SPI_INT_TF  BIT(3)
+#define SPI_INT_TNF BIT(2)
+#define SPI_INT_MF  BIT(1)
+#define SPI_INT_ROF BIT(0)
+
+#define SPI_INT_DEFAULT (SPI_INT_RNE | SPI_INT_TNF | SPI_INT_ROF | SPI_INT_TUF)
+
+/* SPI enable register bit offset */
+#define SPI_SPI_ENABLE_SPIE BIT(0)
+
+/* Maximum baud rate divisor */
+#define SPI_MBRD_MIN 0
+#define SPI_MBRD_MAX 7
+
+#define SPI_FREQ_LIST_MAX ((SPI_MBRD_MAX + 1) * 2 + 1)
+
+#define SPI_CFG(dev)         ((struct spi_cdns_cfg *)(dev->config))
+#define SPI_REG(dev, offset) ((mem_addr_t)(SPI_CFG(dev)->base + (offset)))
+/*******************************************************************************
+ * Types Definition
+ ******************************************************************************/
+typedef void (*irq_config_func_t)(void);
+
+/**
+ * @brief SPI Driver config information.
+ *
+ * This parameter isn't updated after initialization.
+ *
+ * @param base                         SPI register base address.
+ * @param clock_frequency              Peripheral bus clock
+ * @param ext_clock                    External clock frequency.
+ * @param cs_setup_us                  Array of durations from CS assert to
+ *                                     SCLK in us for slaves.
+ * @param cs_hold_us                   Array of durations from CS assert to
+ *                                     SCLK in us for slaves.
+ * @param irq_config                   Interrupt configuration function.
+ * @param leave_enabled_during_config  Conditionally enable or
+ *                                     disable the SPI bus during
+ *                                     configuration
+ * @param freq_list                    Selectable clock
+ *                                     frequency list.
+ */
+struct spi_cdns_cfg {
+	uint32_t base;
+	uint32_t clock_frequency;
+	uint32_t ext_clock;
+	irq_config_func_t irq_config;
+#ifdef CONFIG_PINCTRL
+	const struct pinctrl_dev_config *pcfg;
+#endif
+	uint8_t fifo_width;
+	uint16_t rx_fifo_depth;
+	uint16_t tx_fifo_depth;
+};
+
+/**
+ * @brief SPI Driver private data.
+ *
+ * @param ctx             Transceive context information.
+ * @param config          Current SPI controller configuration structure
+ * @param freq            Actual transfer frequency.
+ * @param tx_remain_entry Remain entries to Tx-FIFO.
+ * @param fifo_diff       Difference between Tx-FIFO entry and Rx-FIFO entry.
+ */
+struct spi_cdns_data {
+	struct spi_context ctx;
+	struct spi_config config;
+	uint32_t freq;
+	uint32_t tx_remain_entry;
+	int32_t fifo_diff;
+};
+
+/*******************************************************************************
+ * Private Functions Code
+ ******************************************************************************/
+
+/**
+ * @brief Mask-write 32-bit value to register.
+ *
+ * @param addr register address.
+ * @param mask 32-bit Mask value.
+ * @param value 32-bit value to be written.
+ * @return None.
+ */
+static inline void sys_set_mask32(mem_addr_t addr, uint32_t mask, uint32_t value)
+{
+	uint32_t temp = sys_read32(addr);
+
+	temp &= ~(mask);
+	temp |= value;
+
+	sys_write32(temp, addr);
+}
+
+/**
+ * @brief Check whether to update context configuration.
+ *
+ * @param dev Device structure (In memory) per driver instance
+ * @param config SPI controller configuration structure
+ * @retval true Configuration is same.
+ * @retval false Configuration is differ.
+ */
+static inline bool spi_cdns_context_configured(const struct device *dev,
+					       const struct spi_config *config)
+{
+	struct spi_cdns_data *data = dev->data;
+
+	if (spi_context_configured(&data->ctx, config) &&
+	    (data->config.frequency == config->frequency) &&
+	    (data->config.operation == config->operation) &&
+	    (data->config.slave == config->slave)) {
+		return true;
+	}
+
+	return false;
+}
+
+/**
+ * @brief Enable/Disable SPI controller
+ *
+ * @param dev Device structure (In memory) per driver instance
+ * @param on SPI enable flag (True: Enable, False: Disable)
+ * @return None.
+ */
+static inline void spi_cdns_spi_enable(const struct device *dev, bool on)
+{
+	if (on) {
+		sys_set_bits(SPI_REG(dev, SPI_SPI_ENABLE), SPI_SPI_ENABLE_SPIE);
+	} else {
+		sys_clear_bits(SPI_REG(dev, SPI_SPI_ENABLE), SPI_SPI_ENABLE_SPIE);
+	}
+}
+
+/**
+ * @brief Assert/Deassert chip select line
+ *
+ * @param dev Device structure (In memory) per driver instance
+ * @param on Assert chip select (True: Assert, False: Deassert)
+ * @return None.
+ */
+static inline void spi_cdns_cs_control(const struct device *dev, bool on)
+{
+	struct spi_cdns_data *data = dev->data;
+
+	if (IS_ENABLED(CONFIG_SPI_SLAVE) && spi_context_is_slave(&data->ctx)) {
+		/* Skip slave select assert/de-assert in slave mode */
+		return;
+	}
+
+	if (on) {
+		uint32_t val = SPI_CONF_PCSL_MASK &
+			       ~(1 << (SPI_CONF_PCSL_OFFSET + data->ctx.config->slave));
+		sys_set_mask32(SPI_REG(dev, SPI_CONF), SPI_CONF_PCSL_MASK, val);
+		k_busy_wait(data->ctx.config->cs.delay);
+	} else if (!(data->ctx.config->operation & SPI_HOLD_ON_CS)) {
+		k_busy_wait(data->ctx.config->cs.delay);
+		sys_set_mask32(SPI_REG(dev, SPI_CONF), SPI_CONF_PCSL_MASK, SPI_CONF_PCSL_MASK);
+	}
+}
+
+static void spi_cdns_config_clock_freq(const struct device *dev, uint32_t spi_freq)
+{
+	const struct spi_cdns_cfg *cfg = dev->config;
+	uint32_t ctrl_reg, baud_rate_div;
+	uint32_t clock_freq;
+
+	clock_freq = cfg->clock_frequency;
+
+	ctrl_reg = sys_read32(SPI_REG(dev, SPI_CONF));
+
+	/*
+	 * Set the clock frequency
+	 * first valid value is 0 (/2)
+	 */
+	baud_rate_div = SPI_MBRD_MIN;
+	while ((baud_rate_div < SPI_MBRD_MAX) && (clock_freq / (2 << baud_rate_div)) > spi_freq) {
+		baud_rate_div++;
+	}
+
+	ctrl_reg &= ~SPI_CONF_MBRD_MASK;
+	ctrl_reg |= baud_rate_div << SPI_CONF_MBRD_OFFSET;
+
+	LOG_DBG("%s: spi baud rate %uHz", dev->name, clock_freq / (2 << baud_rate_div));
+
+	sys_write32(ctrl_reg, SPI_REG(dev, SPI_CONF));
+}
+
+/**
+ * @brief Send 1-entry to Tx-FIFO
+ *
+ * @param dev Device structure (In memory) per driver instance
+ * @return None.
+ */
+static void spi_cdns_send(const struct device *dev)
+{
+	const struct spi_cdns_cfg *config = dev->config;
+	struct spi_cdns_data *data = dev->data;
+	struct spi_context *ctx = &data->ctx;
+	uint8_t dfs = SPI_WORD_SIZE_GET(ctx->config->operation) / 8;
+	uint32_t val = 0;
+	int i, loop;
+
+	loop = (config->fifo_width / 8) / dfs;
+	for (i = 0; i < loop; i++) {
+		if (spi_context_tx_buf_on(ctx)) {
+			switch (dfs) {
+			case 1:
+				if (config->fifo_width == 8) {
+					val |= UNALIGNED_GET((uint8_t *)ctx->tx_buf);
+				} else if (config->fifo_width == 16) {
+					val |= UNALIGNED_GET((uint8_t *)ctx->tx_buf) << 8 * (1 - i);
+				} else if (config->fifo_width == 32) {
+					val |= UNALIGNED_GET((uint8_t *)ctx->tx_buf) << 8 * (3 - i);
+				}
+				break;
+			case 2:
+				if (config->fifo_width == 16) {
+					val |= UNALIGNED_GET((uint16_t *)ctx->tx_buf);
+				} else if (config->fifo_width == 32) {
+					val |= UNALIGNED_GET((uint16_t *)ctx->tx_buf)
+					       << 16 * (1 - i);
+				}
+				break;
+			case 4:
+				if (config->fifo_width == 32) {
+					val |= UNALIGNED_GET((uint32_t *)ctx->tx_buf);
+				}
+				break;
+			}
+		}
+		if ((spi_context_tx_buf_on(ctx) || spi_context_rx_buf_on(ctx))) {
+			if (data->tx_remain_entry > 0) {
+				data->tx_remain_entry--;
+				data->fifo_diff++;
+			}
+		}
+		spi_context_update_tx(&data->ctx, dfs, 1);
+	}
+
+	sys_write32(val, SPI_REG(dev, SPI_TX_DATA));
+}
+
+/**
+ * @brief Receive 1-entry from Rx-FIFO
+ *
+ * @param dev Device structure (In memory) per driver instance
+ * @return None.
+ */
+static void spi_cdns_recv(const struct device *dev)
+{
+	const struct spi_cdns_cfg *config = dev->config;
+	struct spi_cdns_data *data = dev->data;
+	struct spi_context *ctx = &data->ctx;
+	uint8_t dfs = SPI_WORD_SIZE_GET(ctx->config->operation) / 8;
+	uint32_t val;
+	int i, loop;
+
+	val = sys_read32(SPI_REG(dev, SPI_RX_DATA));
+
+	loop = (config->fifo_width / 8) / dfs;
+	for (i = 0; i < loop; i++) {
+		if (spi_context_rx_buf_on(ctx)) {
+			switch (dfs) {
+			case 1:
+				if (config->fifo_width == 8) {
+					UNALIGNED_PUT(val & 0xFF, (uint8_t *)ctx->rx_buf);
+				} else if (config->fifo_width == 16) {
+					UNALIGNED_PUT((val >> 8 * (1 - i)) & 0xFF,
+						      (uint8_t *)ctx->rx_buf);
+				} else if (config->fifo_width == 32) {
+					UNALIGNED_PUT((val >> 8 * (3 - i)) & 0xFF,
+						      (uint8_t *)ctx->rx_buf);
+				}
+				break;
+			case 2:
+				if (config->fifo_width == 16) {
+					UNALIGNED_PUT(val & 0xFFFF, (uint16_t *)ctx->rx_buf);
+				} else if (config->fifo_width == 32) {
+					UNALIGNED_PUT((val >> 16 * (1 - i)) & 0xFFFF,
+						      (uint16_t *)ctx->rx_buf);
+				}
+				break;
+			case 4:
+				if (config->fifo_width == 32) {
+					UNALIGNED_PUT(val, (uint32_t *)ctx->rx_buf);
+				}
+				break;
+			}
+		}
+		if (data->fifo_diff > 0) {
+			data->fifo_diff--;
+		}
+		spi_context_update_rx(ctx, dfs, 1);
+	}
+}
+
+/**
+ * @brief Push to Tx-FIFO
+ *
+ * @param dev Device structure (In memory) per driver instance
+ * @return None.
+ */
+static void spi_cdns_push_data(const struct device *dev)
+{
+	const struct spi_cdns_cfg *config = dev->config;
+	struct spi_cdns_data *data = dev->data;
+	uint32_t tx_entry;
+
+	if (spi_context_is_slave(&data->ctx)) {
+		/*
+		 * while tx fifo is not full and there is data to transmit, as we are a target fill
+		 * it up until we are full
+		 */
+		while ((!(sys_read32(SPI_REG(dev, SPI_INT_STATUS)) & SPI_INT_TF)) &&
+		       (data->tx_remain_entry > 0)) {
+			spi_cdns_send(dev);
+		}
+	} else {
+		/*
+		 * We can't fill until we are full as we could chase our tail with waiting until we
+		 * are full, while at the same time data is being sent out faster than we can check
+		 * if we are full
+		 */
+		tx_entry = MIN(config->tx_fifo_depth - data->fifo_diff, data->tx_remain_entry);
+		while (tx_entry > 0) {
+			spi_cdns_send(dev);
+			tx_entry--;
+		}
+	}
+}
+
+/**
+ * @brief Pull from Rx-FIFO
+ *
+ * @param dev Device structure (In memory) per driver instance
+ * @return None.
+ */
+static void spi_cdns_pull_data(const struct device *dev)
+{
+	const struct spi_cdns_cfg *config = dev->config;
+	struct spi_cdns_data *data = dev->data;
+	uint32_t rx_threshold_tmp;
+	uint32_t rx_remain_entry;
+
+	/*
+	 * As there is no rx fifo empty status bit, Write the rx threshold
+	 * to so the rne status bit will report when there is less than 1
+	 * item in the fifo
+	 */
+	rx_threshold_tmp = sys_read32(SPI_REG(dev, SPI_RX_THRESHOLD));
+	sys_write32(1, SPI_REG(dev, SPI_RX_THRESHOLD));
+
+	while (sys_read32(SPI_REG(dev, SPI_INT_STATUS)) & SPI_INT_RNE) {
+		spi_cdns_recv(dev);
+	}
+
+	/*
+	 * The threshold is designed to trigger by FIFO I/O.
+	 * Therefore, it is necessary to set rx threshold before pulling.
+	 */
+	rx_remain_entry = DIV_ROUND_UP(data->fifo_diff, (config->fifo_width / 8));
+	if ((rx_remain_entry != 0) && (rx_remain_entry < rx_threshold_tmp)) {
+		sys_write32(rx_remain_entry, SPI_REG(dev, SPI_RX_THRESHOLD));
+	} else {
+		sys_write32(rx_threshold_tmp, SPI_REG(dev, SPI_RX_THRESHOLD));
+	}
+}
+
+/**
+ * @brief Configure SPI controller
+ *
+ * @param dev Device structure (In memory) per driver instance
+ * @param config SPI controller configuration structure
+ * @retval 0 No errors.
+ * @retval -EINVAL Invalid argument error.
+ * @retval -ENOTSUP Unsupported value error.
+ */
+static int spi_cdns_configure(const struct device *dev, const struct spi_config *config)
+{
+	const struct spi_cdns_cfg *dev_config = dev->config;
+	struct spi_cdns_data *data = dev->data;
+	uint32_t word_size, conf_val;
+
+	if (spi_cdns_context_configured(dev, config)) {
+		/* Nothing to do */
+		return 0;
+	}
+
+	if (config->operation & (SPI_MODE_LOOP | SPI_TRANSFER_LSB | SPI_LINES_DUAL |
+				 SPI_LINES_QUAD | SPI_LINES_OCTAL)) {
+		return -ENOTSUP;
+	}
+
+	/* Active High CS is not supported with hardware CS */
+	if (!spi_cs_is_gpio(config) && (config->operation & SPI_CS_ACTIVE_HIGH)) {
+		return -ENOTSUP;
+	}
+
+	if ((config->operation & SPI_OP_MODE_SLAVE) && !IS_ENABLED(CONFIG_SPI_SLAVE)) {
+		LOG_ERR("Kconfig for enable SPI in slave mode is not enabled");
+		return -ENOTSUP;
+	}
+
+	/* Word Sizes are only compatible with certain fifo widths */
+	word_size = SPI_WORD_SIZE_GET(config->operation);
+	if (((word_size != 8) && (word_size != 16) && (word_size != 32)) ||
+	    (word_size > dev_config->fifo_width) ||
+	    ((dev_config->fifo_width == 24) && (word_size == 16)) ||
+	    ((dev_config->fifo_width == 32) && (word_size == 24))) {
+		return -ENOTSUP;
+	}
+
+	data->ctx.config = config;
+	data->config = *config;
+
+	conf_val = SPI_CONF_PCSL_MASK | SPI_CONF_MCSE | SPI_CONF_MRCS;
+
+	/* Configure for Master or Slave */
+	if (config->operation & SPI_OP_MODE_SLAVE) {
+		conf_val &= ~(SPI_CONF_MSEL);
+	} else {
+		conf_val |= SPI_CONF_MSEL;
+	}
+
+	/* Set the polarity */
+	if (config->operation & SPI_MODE_CPHA) {
+		conf_val |= SPI_CONF_CPHA;
+	} else {
+		conf_val &= ~(SPI_CONF_CPHA);
+	}
+
+	/* Set the phase */
+	if (config->operation & SPI_MODE_CPOL) {
+		conf_val |= SPI_CONF_CPOL;
+	} else {
+		conf_val &= ~(SPI_CONF_CPOL);
+	}
+
+	/*
+	 * Set clock frequency.
+	 * SPI clock is generated based on pclk or ext_clk, and the frequency closest
+	 * to the value obtained by dividing the two base clocks is selected.
+	 */
+	spi_cdns_config_clock_freq(dev, config->frequency);
+
+	/* Set transfer word size */
+	conf_val &= ~(SPI_CONF_TWS_MASK);
+	conf_val |= ((word_size / 8) - 1) << SPI_CONF_TWS_OFFSET;
+
+	sys_write32(conf_val, SPI_REG(dev, SPI_CONF));
+
+	return 0;
+}
+
+/**
+ * @brief Interrupt handler
+ *
+ * @param dev Device structure (In memory) per driver instance
+ * @return None.
+ */
+static void spi_cdns_isr(const struct device *dev)
+{
+	struct spi_cdns_data *data = dev->data;
+	int32_t int_status;
+	int error = 0;
+
+	int_status = sys_read32(SPI_REG(dev, SPI_INT_STATUS));
+	sys_write32(int_status, SPI_REG(dev, SPI_INT_STATUS));
+
+	if ((int_status & SPI_INT_ROF) && spi_context_rx_buf_on(&data->ctx)) {
+		LOG_ERR("%s: rx fifo overflow", dev->name);
+		error = -EIO;
+		goto complete;
+	}
+
+	if ((int_status & SPI_INT_TUF) && spi_context_tx_buf_on(&data->ctx)) {
+		LOG_ERR("%s: tx fifo underflow", dev->name);
+		error = -EIO;
+		goto complete;
+	}
+
+	if (int_status & SPI_INT_RNE) {
+		spi_cdns_pull_data(dev);
+	}
+
+	if (int_status & SPI_INT_TNF) {
+		spi_cdns_push_data(dev);
+	}
+
+	if (!spi_context_tx_buf_on(&data->ctx)) {
+		/* Disable Tx-FIFO interrupt for no transfer data */
+		sys_write32(SPI_INT_TNF, SPI_REG(dev, SPI_INT_DISABLE));
+	}
+
+	if (spi_context_tx_buf_on(&data->ctx) || spi_context_rx_buf_on(&data->ctx)) {
+		return;
+	}
+
+	if (data->fifo_diff != 0) {
+		return;
+	}
+
+complete:
+	sys_write32(SPI_INT_DEFAULT, SPI_REG(dev, SPI_INT_DISABLE));
+#if CONFIG_SPI_ASYNC
+	if (data->ctx.asynchronous) {
+		if (spi_cs_is_gpio(data->ctx.config)) {
+			spi_context_cs_control(&data->ctx, false);
+		} else {
+			spi_cdns_cs_control(dev, false);
+		}
+		pm_device_busy_clear(dev);
+		pm_device_runtime_put(dev);
+	}
+#endif
+
+	spi_context_complete(&data->ctx, dev, error);
+}
+
+/**
+ * @brief Initialize SPI driver
+ *
+ * @param dev Device structure (In memory) per driver instance
+ * @return None.
+ */
+static int spi_cdns_init(const struct device *dev)
+{
+	const struct spi_cdns_cfg *cfg = dev->config;
+	struct spi_cdns_data *data = dev->data;
+
+	cfg->irq_config();
+
+	sys_write32(SPI_CONF_INITIAL_VAL, SPI_REG(dev, SPI_CONF));
+
+	/* Disable interrupt */
+	sys_write32(SPI_INT_DEFAULT, SPI_REG(dev, SPI_INT_DISABLE));
+	/* Clear Pending Interrupts */
+	(void)sys_read32(SPI_REG(dev, SPI_INT_STATUS));
+
+	/* TxFIFO and RxFIFO clear */
+	sys_set_mask32(SPI_REG(dev, SPI_CONF), SPI_CONF_TXCLR | SPI_CONF_RXCLR,
+		       SPI_CONF_TXCLR | SPI_CONF_RXCLR);
+
+	spi_cdns_spi_enable(dev, true);
+
+	/* Make sure the context is unlocked */
+	spi_context_unlock_unconditionally(&data->ctx);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * Public Functions Code
+ ******************************************************************************/
+/**
+ * @brief Internal read/write the specified amount of data.
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @param config Pointer to a valid spi_config structure instance.
+ * @param tx_bufs Buffer array where data to be sent originates from, or NULL if none.
+ * @param rx_bufs Buffer array where data to be read will be written to, or NULL if none.
+ * @param asynchronous Asynchronous flag
+ * @param signal A pointer to a valid and ready to be signaled struct k_poll_signal.
+ *
+ * @retval 0 Success.
+ * @retval -EINVAL Invalid argument error.
+ * @retval -ENOTSUP Unsupported value error.
+ * @retval -EBUSY Waiting period timed out.
+ * @retval -EIO Rx FIFO overflow.
+ */
+static int spi_cdns_transceive(const struct device *dev, const struct spi_config *config,
+			       const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs,
+			       bool asynchronous, spi_callback_t cb, void *userdata)
+{
+	const struct spi_cdns_cfg *dev_config = dev->config;
+	struct spi_cdns_data *data = dev->data;
+	uint32_t dfs;
+	int ret;
+
+	spi_context_lock(&data->ctx, asynchronous, cb, userdata, config);
+
+	pm_device_runtime_get(dev);
+	pm_device_busy_set(dev);
+
+	spi_cdns_spi_enable(dev, false);
+
+	ret = spi_cdns_configure(dev, config);
+	if (ret < 0) {
+		spi_cdns_spi_enable(dev, true);
+		goto out;
+	}
+
+	/* Disable interrupt */
+	sys_write32(SPI_INT_DEFAULT, SPI_REG(dev, SPI_INT_DISABLE));
+	/* Clear Pending Interrupts */
+	(void)sys_read32(SPI_REG(dev, SPI_INT_STATUS));
+
+	/* Reset semaphore for waiting for completion */
+	k_sem_reset(&data->ctx.sync);
+
+	/* TxFIFO and RxFIFO clear */
+	sys_set_mask32(SPI_REG(dev, SPI_CONF), SPI_CONF_TXCLR | SPI_CONF_RXCLR,
+		       SPI_CONF_TXCLR | SPI_CONF_RXCLR);
+	spi_cdns_spi_enable(dev, true);
+
+	data->fifo_diff = 0;
+
+	dfs = SPI_WORD_SIZE_GET(data->ctx.config->operation) / 8;
+	spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, dfs);
+
+	data->tx_remain_entry =
+		MAX(spi_context_total_rx_len(&data->ctx), spi_context_total_tx_len(&data->ctx));
+
+	/* 0 byte transfer */
+	if ((spi_context_total_rx_len(&data->ctx) == 0) &&
+	    (spi_context_total_tx_len(&data->ctx) == 0)) {
+		if (asynchronous) {
+			spi_context_complete(&data->ctx, dev, 0);
+		}
+		goto out;
+	}
+
+	/* Set fifo thresholds */
+	if (spi_context_is_slave(&data->ctx)) {
+		sys_write32(1, SPI_REG(dev, SPI_RX_THRESHOLD));
+		sys_write32(dev_config->tx_fifo_depth - 1, SPI_REG(dev, SPI_TX_THRESHOLD));
+	} else {
+		uint32_t fifo_words = MIN(DIV_ROUND_UP(spi_context_total_rx_len(&data->ctx),
+						       (dev_config->fifo_width / 8)),
+					  dev_config->rx_fifo_depth * 5 / 8);
+		sys_write32(fifo_words, SPI_REG(dev, SPI_RX_THRESHOLD));
+		sys_write32(dev_config->tx_fifo_depth / 2, SPI_REG(dev, SPI_TX_THRESHOLD));
+	}
+
+	if (spi_cs_is_gpio(data->ctx.config)) {
+		spi_context_cs_control(&data->ctx, true);
+	} else {
+		spi_cdns_cs_control(dev, true);
+	}
+
+	sys_write32(SPI_INT_DEFAULT, SPI_REG(dev, SPI_INT_ENABLE));
+
+	ret = spi_context_wait_for_completion(&data->ctx);
+
+	if (!asynchronous) {
+		if (spi_cs_is_gpio(data->ctx.config)) {
+			spi_context_cs_control(&data->ctx, false);
+		} else {
+			spi_cdns_cs_control(dev, false);
+		}
+		pm_device_busy_clear(dev);
+		pm_device_runtime_put(dev);
+	}
+
+#ifdef CONFIG_SPI_SLAVE
+	if (spi_context_is_slave(&data->ctx) && !ret) {
+		ret = data->ctx.recv_frames;
+	}
+#endif /* CONFIG_SPI_SLAVE */
+
+out:
+	spi_context_release(&data->ctx, ret);
+
+	return ret;
+}
+
+/**
+ * @brief Read/write the specified amount of data from the SPI driver.
+ *
+ * Note: This function is synchronous.
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @param config Pointer to a valid spi_config structure instance.
+ * @param tx_bufs Buffer array where data to be sent originates from, or NULL if none.
+ * @param rx_bufs Buffer array where data to be read will be written to, or NULL if none.
+ *
+ * @retval 0 Success.
+ * @retval -EINVAL Invalid argument error.
+ * @retval -ENOTSUP Unsupported value error.
+ * @retval -EBUSY Waiting period timed out.
+ * @retval -EIO Rx FIFO overflow.
+ */
+static int spi_cdns_transceive_sync(const struct device *dev, const struct spi_config *config,
+				    const struct spi_buf_set *tx_bufs,
+				    const struct spi_buf_set *rx_bufs)
+{
+	return spi_cdns_transceive(dev, config, tx_bufs, rx_bufs, false, NULL, NULL);
+}
+
+#ifdef CONFIG_SPI_ASYNC
+/**
+ * @brief Read/write the specified amount of data from the SPI driver.
+ *
+ * Note: This function is asynchronous.
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @param config Pointer to a valid spi_config structure instance.
+ * @param tx_bufs Buffer array where data to be sent originates from, or NULL if none.
+ * @param rx_bufs Buffer array where data to be read will be written to, or NULL if none.
+ * @param async A pointer to a valid and ready to be signaled struct k_poll_signal.
+ *
+ * @retval 0 Success.
+ * @retval -EINVAL Invalid argument error.
+ * @retval -ENOTSUP Unsupported value error.
+ */
+static int spi_cdns_transceive_async(const struct device *dev, const struct spi_config *config,
+				     const struct spi_buf_set *tx_bufs,
+				     const struct spi_buf_set *rx_bufs, spi_callback_t cb,
+				     void *userdata)
+{
+	return spi_cdns_transceive(dev, config, tx_bufs, rx_bufs, true, cb, userdata);
+}
+#endif /* CONFIG_SPI_ASYNC */
+
+/**
+ * @brief Release the SPI device locked on by the current config
+ *
+ * @param dev Pointer to the device structure for the driver instance
+ * @param config Pointer to a valid spi_config structure instance.
+ */
+static int spi_cdns_release(const struct device *dev, const struct spi_config *config)
+{
+	struct spi_cdns_data *data = dev->data;
+
+	if (spi_cs_is_gpio(data->ctx.config)) {
+		spi_context_cs_control(&data->ctx, false);
+	} else {
+		spi_cdns_cs_control(dev, false);
+	}
+	spi_context_unlock_unconditionally(&data->ctx);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM_DEVICE
+static int spi_cdns_pm_action(const struct device *dev, enum pm_device_action action)
+{
+	const struct spi_cdns_cfg *cfg = dev->config;
+	int ret;
+
+	switch (action) {
+	case PM_DEVICE_ACTION_RESUME:
+		/* TODO: Enable SPI Clock */
+#ifdef CONFIG_PINCTRL
+		ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
+		if (ret < 0) {
+			return ret;
+		}
+#endif
+		break;
+	case PM_DEVICE_ACTION_SUSPEND:
+		/* TODO: Disable SPI Clock */
+#ifdef CONFIG_PINCTRL
+		ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_SLEEP);
+		if (ret < 0) {
+			return ret;
+		}
+#endif
+		break;
+	default:
+		ret = -ENOTSUP;
+	}
+
+	return ret;
+}
+#endif /* CONFIG_PM_DEVICE */
+
+/**
+ * SPI driver API registered in Zephyr spi framework
+ */
+static DEVICE_API(spi, spi_cdns_api) = {
+	.transceive = spi_cdns_transceive_sync,
+#ifdef CONFIG_SPI_ASYNC
+	.transceive_async = spi_cdns_transceive_async,
+#endif /* CONFIG_SPI_ASYNC */
+	.release = spi_cdns_release,
+};
+
+/* Set clock-frequency-ext to pclk / 5 if there is no clock-frequency-ext */
+#define SPI_CLOCK_FREQUENCY_EXT(n)                                                                 \
+	COND_CODE_1(DT_INST_NODE_HAS_PROP(n, clock_frequency_ext), \
+		(DT_INST_PROP(n, clock_frequency_ext)),            \
+		(DT_INST_PROP(n, clock_frequency) / 5))
+
+#define SPI_CDNS_INIT(n)                                                                           \
+	static void spi_cdns_irq_config_##n(void);                                                 \
+	static struct spi_cdns_data spi_cdns_data_##n = {                                          \
+		SPI_CONTEXT_INIT_LOCK(spi_cdns_data_##n, ctx),                                     \
+		SPI_CONTEXT_INIT_SYNC(spi_cdns_data_##n, ctx),                                     \
+	};                                                                                         \
+	static struct spi_cdns_cfg spi_cdns_cfg_##n = {                                            \
+		.base = DT_INST_REG_ADDR(n),                                                       \
+		.irq_config = spi_cdns_irq_config_##n,                                             \
+		.clock_frequency = DT_INST_PROP(n, clock_frequency),                               \
+		.ext_clock = SPI_CLOCK_FREQUENCY_EXT(n),                                           \
+	};                                                                                         \
+	SPI_DEVICE_DT_INST_DEFINE(n, spi_cdns_init, spi_cdns_pm_action, &spi_cdns_data_##n,        \
+				  &spi_cdns_cfg_##n, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,        \
+				  &spi_cdns_api);                                                  \
+	static void spi_cdns_irq_config_##n(void)                                                  \
+	{                                                                                          \
+		IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), spi_cdns_isr,               \
+			    DEVICE_DT_INST_GET(n), 0);                                             \
+		irq_enable(DT_INST_IRQN(n));                                                       \
+	}
+
+#define DT_DRV_COMPAT cdns_spi
+DT_INST_FOREACH_STATUS_OKAY(SPI_CDNS_INIT)
diff --git a/drivers/spi/spi_context.h b/drivers/spi/spi_context.h
index 7ae3cfb2bba..e86fb8ba9c9 100644
--- a/drivers/spi/spi_context.h
+++ b/drivers/spi/spi_context.h
@@ -75,17 +75,30 @@ struct spi_context {
 	},										\
 	._ctx_name.num_cs_gpios = DT_PROP_LEN_OR(_node_id, cs_gpios, 0),
 
+/*
+ * Checks if a spi config is the same as the one stored in the spi_context
+ * The intention of this function is to be used to check if a driver can skip
+ * some reconfiguration for a transfer in a fast code path.
+ */
 static inline bool spi_context_configured(struct spi_context *ctx,
 					  const struct spi_config *config)
 {
 	return !!(ctx->config == config);
 }
 
+/* Returns true if the spi configuration stored for this context
+ * specifies a slave mode configuration, returns false otherwise
+ */
 static inline bool spi_context_is_slave(struct spi_context *ctx)
 {
 	return (ctx->config->operation & SPI_OP_MODE_SLAVE);
 }
 
+/*
+ * The purpose of the context lock is to synchronize the usage of the driver/hardware.
+ * The driver should call this function to claim or wait for ownership of the spi resource.
+ * Usually the appropriate time to call this is at the start of the transceive API implementation.
+ */
 static inline void spi_context_lock(struct spi_context *ctx,
 				    bool asynchronous,
 				    spi_callback_t callback,
@@ -108,6 +121,13 @@ static inline void spi_context_lock(struct spi_context *ctx,
 #endif /* CONFIG_SPI_ASYNC */
 }
 
+/*
+ * This function must be called by a driver which has called spi_context_lock in order
+ * to release the ownership of the spi resource.
+ * Usually the appropriate time to call this would be at the end of a transfer that was
+ * initiated by a transceive API call, except in the case that the SPI_LOCK_ON bit was set
+ * in the configuration.
+ */
 static inline void spi_context_release(struct spi_context *ctx, int status)
 {
 #ifdef CONFIG_SPI_SLAVE
@@ -132,6 +152,13 @@ static inline void spi_context_release(struct spi_context *ctx, int status)
 static inline size_t spi_context_total_tx_len(struct spi_context *ctx);
 static inline size_t spi_context_total_rx_len(struct spi_context *ctx);
 
+/* This function essentially is a way for a driver to seamlessly implement both the
+ * synchronous transceive API and the asynchronous transceive_async API in the same way.
+ *
+ * The exact way this function is used may depend on driver implementation, but
+ * essentially this will block waiting for a signal from spi_context_complete,
+ * unless the transfer is asynchronous, in which case it does nothing in master mode.
+ */
 static inline int spi_context_wait_for_completion(struct spi_context *ctx)
 {
 	int status = 0;
@@ -180,6 +207,12 @@ static inline int spi_context_wait_for_completion(struct spi_context *ctx)
 	return status;
 }
 
+/* For synchronous transfers, this will signal to a thread waiting
+ * on spi_context_wait for completion.
+ *
+ * For asynchronous tranfers, this will call the async callback function
+ * with the user data.
+ */
 static inline void spi_context_complete(struct spi_context *ctx,
 					const struct device *dev,
 					int status)
@@ -212,6 +245,14 @@ static inline void spi_context_complete(struct spi_context *ctx,
 #endif /* CONFIG_SPI_ASYNC */
 }
 
+/*
+ * This function initializes all the chip select GPIOs associated with a spi controller.
+ * The context first must be initialized using the SPI_CONTEXT_CS_GPIOS_INITIALIZE macro.
+ * This function should be called during the device init sequence so that
+ * all the CS lines are configured properly before the first transfer begins.
+ * Note: If a controller has native CS control in SPI hardware, they should also be initialized
+ * during device init by the driver with hardware-specific code.
+ */
 static inline int spi_context_cs_configure_all(struct spi_context *ctx)
 {
 	int ret;
@@ -233,6 +274,7 @@ static inline int spi_context_cs_configure_all(struct spi_context *ctx)
 	return 0;
 }
 
+/* Helper function to control the GPIO CS, not meant to be used directly by drivers */
 static inline void _spi_context_cs_control(struct spi_context *ctx,
 					   bool on, bool force_off)
 {
@@ -252,11 +294,22 @@ static inline void _spi_context_cs_control(struct spi_context *ctx,
 	}
 }
 
+/* This function should be called by drivers to control the chip select line in master mode
+ * in the case of the CS being a GPIO. The de facto usage of the zephyr SPI API expects that the
+ * chip select be asserted throughout the entire transfer specified by a transceive call,
+ * ie all buffers in a spi_buf_set should be finished before deasserting CS. And usually
+ * the deassertion is at the end of the transfer, except in the case that the
+ * SPI_HOLD_ON_CS bit was set in the configuration.
+ */
 static inline void spi_context_cs_control(struct spi_context *ctx, bool on)
 {
 	_spi_context_cs_control(ctx, on, false);
 }
 
+/* Forcefully releases the spi context and removes the owner, allowing taking the lock
+ * with spi_context_lock without the previous owner releasing the lock.
+ * This is usually used to aid in implementation of the spi_release driver API.
+ */
 static inline void spi_context_unlock_unconditionally(struct spi_context *ctx)
 {
 	/* Forcing CS to go to inactive status */
@@ -268,6 +321,11 @@ static inline void spi_context_unlock_unconditionally(struct spi_context *ctx)
 	}
 }
 
+/*
+ * Helper function for incrementing buffer pointer.
+ * Generally not needed to be used directly by drivers.
+ * Use spi_context_update_(tx/rx) instead.
+ */
 static inline void *spi_context_get_next_buf(const struct spi_buf **current,
 					     size_t *count,
 					     size_t *buf_len,
@@ -287,6 +345,17 @@ static inline void *spi_context_get_next_buf(const struct spi_buf **current,
 	return NULL;
 }
 
+/*
+ * The spi context private api works with the driver by providing code to
+ * keep track of how much of the transfer has been completed. The driver
+ * calls functions to report when some tx or rx has finished, and the driver
+ * then can use the spi context to keep track of how much is left to do.
+ */
+
+/*
+ * This function must be called at the start of a transfer by the driver
+ * to initialize the spi context fields for tracking the progress.
+ */
 static inline
 void spi_context_buffers_setup(struct spi_context *ctx,
 			       const struct spi_buf_set *tx_bufs,
@@ -322,8 +391,10 @@ void spi_context_buffers_setup(struct spi_context *ctx,
 }
 
 /*
- * Note: dfs is the number of bytes needed to store a data frame,
- * while len is the number of data frames sent.
+ * Should be called to update the tracking of TX being completed.
+ *
+ * Parameter "dfs" is the number of bytes needed to store a data frame.
+ * Parameter "len" is the number of data frames of TX that were sent.
  */
 static ALWAYS_INLINE
 void spi_context_update_tx(struct spi_context *ctx, uint8_t dfs, uint32_t len)
@@ -353,12 +424,18 @@ void spi_context_update_tx(struct spi_context *ctx, uint8_t dfs, uint32_t len)
 	LOG_DBG("tx buf/len %p/%zu", (void *)ctx->tx_buf, ctx->tx_len);
 }
 
+/* Returns true if there is still TX buffers left in the spi_buf_set
+ * even if they are "null" (nop) buffers.
+ */
 static ALWAYS_INLINE
 bool spi_context_tx_on(struct spi_context *ctx)
 {
 	return !!(ctx->tx_len);
 }
 
+/* Similar to spi_context_tx_on, but only returns true if the current buffer is
+ * not a null/NOP placeholder.
+ */
 static ALWAYS_INLINE
 bool spi_context_tx_buf_on(struct spi_context *ctx)
 {
@@ -366,8 +443,10 @@ bool spi_context_tx_buf_on(struct spi_context *ctx)
 }
 
 /*
- * Note: dfs is the number of bytes needed to store a data frame,
- * while len is the number of data frames received.
+ * Should be called to update the tracking of RX being completed.
+ *
+ * @param dfs is the number of bytes needed to store a data frame.
+ * @param len is the number of data frames of RX that were received.
  */
 static ALWAYS_INLINE
 void spi_context_update_rx(struct spi_context *ctx, uint8_t dfs, uint32_t len)
@@ -404,12 +483,18 @@ void spi_context_update_rx(struct spi_context *ctx, uint8_t dfs, uint32_t len)
 	LOG_DBG("rx buf/len %p/%zu", (void *)ctx->rx_buf, ctx->rx_len);
 }
 
+/* Returns true if there is still RX buffers left in the spi_buf_set
+ * even if they are "null" (nop) buffers.
+ */
 static ALWAYS_INLINE
 bool spi_context_rx_on(struct spi_context *ctx)
 {
 	return !!(ctx->rx_len);
 }
 
+/* Similar to spi_context_rx_on, but only returns true if the current buffer is
+ * not a null/NOP placeholder.
+ */
 static ALWAYS_INLINE
 bool spi_context_rx_buf_on(struct spi_context *ctx)
 {
@@ -420,6 +505,10 @@ bool spi_context_rx_buf_on(struct spi_context *ctx)
  * Returns the maximum length of a transfer for which all currently active
  * directions have a continuous buffer, i.e. the maximum SPI transfer that
  * can be done with DMA that handles only non-scattered buffers.
+ *
+ * In other words, returns the length of the smaller of the current RX or current TX buffer.
+ * Except if either RX or TX buf length is 0, returns the length of the other.
+ * And if both are 0 then will return 0 and should indicate transfer completion.
  */
 static inline size_t spi_context_max_continuous_chunk(struct spi_context *ctx)
 {
@@ -432,35 +521,71 @@ static inline size_t spi_context_max_continuous_chunk(struct spi_context *ctx)
 	return MIN(ctx->tx_len, ctx->rx_len);
 }
 
+/* Returns the length of the longer of the current RX or current TX buffer. */
 static inline size_t spi_context_longest_current_buf(struct spi_context *ctx)
 {
 	return ctx->tx_len > ctx->rx_len ? ctx->tx_len : ctx->rx_len;
 }
 
-static inline size_t spi_context_total_tx_len(struct spi_context *ctx)
+/* Helper function, not intended to be used by drivers directly */
+static size_t spi_context_count_tx_buf_lens(struct spi_context *ctx, size_t start_index)
 {
 	size_t n;
 	size_t total_len = 0;
 
-	for (n = 0; n < ctx->tx_count; ++n) {
+	for (n = start_index; n < ctx->tx_count; ++n) {
 		total_len += ctx->current_tx[n].len;
 	}
 
 	return total_len;
 }
 
-static inline size_t spi_context_total_rx_len(struct spi_context *ctx)
+/* Helper function, not intended to be used by drivers directly */
+static size_t spi_context_count_rx_buf_lens(struct spi_context *ctx, size_t start_index)
 {
 	size_t n;
 	size_t total_len = 0;
 
-	for (n = 0; n < ctx->rx_count; ++n) {
+	for (n = start_index; n < ctx->rx_count; ++n) {
 		total_len += ctx->current_rx[n].len;
 	}
 
 	return total_len;
 }
 
+
+/* Returns the length of the sum of the remaining TX buffers in the buf set, including
+ * the current buffer in the total.
+ */
+static inline size_t spi_context_total_tx_len(struct spi_context *ctx)
+{
+	return spi_context_count_tx_buf_lens(ctx, 0);
+}
+
+/* Returns the length of the sum of the remaining RX buffers in the buf set, including
+ * the current buffer in the total.
+ */
+static inline size_t spi_context_total_rx_len(struct spi_context *ctx)
+{
+	return spi_context_count_rx_buf_lens(ctx, 0);
+}
+
+/* Similar to spi_context_total_tx_len, except does not count words that have been finished
+ * in the current buffer, ie only including what is remaining in the current buffer in the sum.
+ */
+static inline size_t spi_context_tx_len_left(struct spi_context *ctx)
+{
+	return ctx->tx_len + spi_context_count_tx_buf_lens(ctx, 1);
+}
+
+/* Similar to spi_context_total_rx_len, except does not count words that have been finished
+ * in the current buffer, ie only including what is remaining in the current buffer in the sum.
+ */
+static inline size_t spi_context_rx_len_left(struct spi_context *ctx)
+{
+	return ctx->rx_len + spi_context_count_rx_buf_lens(ctx, 1);
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/drivers/spi/spi_dw.c b/drivers/spi/spi_dw.c
index e320aa39547..6941bfdaaa7 100644
--- a/drivers/spi/spi_dw.c
+++ b/drivers/spi/spi_dw.c
@@ -234,7 +234,7 @@ static int spi_dw_configure(const struct device *dev,
 	}
 
 	/* Word size */
-	if (info->max_xfer_size == 32) {
+	if (!IS_ENABLED(CONFIG_SPI_DW_HSSI) && (info->max_xfer_size == 32)) {
 		ctrlr0 |= DW_SPI_CTRLR0_DFS_32(SPI_WORD_SIZE_GET(config->operation));
 	} else {
 		ctrlr0 |= DW_SPI_CTRLR0_DFS_16(SPI_WORD_SIZE_GET(config->operation));
@@ -332,6 +332,18 @@ static void spi_dw_update_txftlr(const struct device *dev,
 		} else if (spi->ctx.tx_len < dw_spi_txftlr_dflt) {
 			reg_data = spi->ctx.tx_len - 1;
 		}
+	} else {
+#if defined(CONFIG_SPI_DW_HSSI) && defined(CONFIG_SPI_EXTENDED_MODES)
+		/*
+		 * TXFTLR field in the TXFTLR register is valid only for
+		 * Controller mode operation
+		 */
+		if (!spi->ctx.tx_len) {
+			reg_data = 0U;
+		} else if (spi->ctx.tx_len < dw_spi_txftlr_dflt) {
+			reg_data = (spi->ctx.tx_len - 1) << DW_SPI_TXFTLR_TXFTLR_SHIFT;
+		}
+#endif
 	}
 
 	LOG_DBG("TxFTLR: %u", reg_data);
@@ -579,6 +591,12 @@ int spi_dw_init(const struct device *dev)
 	write_imr(dev, DW_SPI_IMR_MASK);
 	clear_bit_ssienr(dev);
 
+	/* SSI component version */
+	spi->version = read_ssi_comp_version(dev);
+	LOG_DBG("Version: %c.%c%c%c", (spi->version >> 24) & 0xff,
+		(spi->version >> 16) & 0xff, (spi->version >> 8) & 0xff,
+		spi->version & 0xff);
+
 	LOG_DBG("Designware SPI driver initialized on device: %p", dev);
 
 	err = spi_context_cs_configure_all(&spi->ctx);
diff --git a/drivers/spi/spi_dw.h b/drivers/spi/spi_dw.h
index e1df26d1c14..55a25804664 100644
--- a/drivers/spi/spi_dw.h
+++ b/drivers/spi/spi_dw.h
@@ -48,6 +48,7 @@ struct spi_dw_config {
 struct spi_dw_data {
 	DEVICE_MMIO_RAM;
 	struct spi_context ctx;
+	uint32_t version;	/* ssi comp version */
 	uint8_t dfs;	/* dfs in bytes: 1,2 or 4 */
 	uint8_t fifo_diff;	/* cannot be bigger than FIFO depth */
 };
@@ -194,6 +195,11 @@ static int reg_test_bit(uint8_t bit, mm_reg_t addr, uint32_t off)
 #define DW_SPI_CTRLR0_SRL_BIT		(13)
 #endif
 
+#if defined(CONFIG_SPI_DW_HSSI) && defined(CONFIG_SPI_EXTENDED_MODES)
+/* TXFTLR setting. Only valid for Controller operation mode. */
+#define DW_SPI_TXFTLR_TXFTLR_SHIFT	(16)
+#endif
+
 #define DW_SPI_CTRLR0_SCPH		BIT(DW_SPI_CTRLR0_SCPH_BIT)
 #define DW_SPI_CTRLR0_SCPOL		BIT(DW_SPI_CTRLR0_SCPOL_BIT)
 #define DW_SPI_CTRLR0_SRL		BIT(DW_SPI_CTRLR0_SRL_BIT)
diff --git a/drivers/spi/spi_esp32_spim.c b/drivers/spi/spi_esp32_spim.c
index 8ad679b76ec..f672d26ff56 100644
--- a/drivers/spi/spi_esp32_spim.c
+++ b/drivers/spi/spi_esp32_spim.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2020-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,13 +17,7 @@ LOG_MODULE_REGISTER(esp32_spi, CONFIG_SPI_LOG_LEVEL);
 #include <soc.h>
 #include <esp_memory_utils.h>
 #include <zephyr/drivers/spi.h>
-#include <zephyr/drivers/spi/rtio.h>
-#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3) ||                    \
-	defined(CONFIG_SOC_SERIES_ESP32C6)
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-#else
 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
-#endif
 #ifdef SOC_GDMA_SUPPORTED
 #include <hal/gdma_hal.h>
 #include <hal/gdma_ll.h>
@@ -32,13 +26,6 @@ LOG_MODULE_REGISTER(esp32_spi, CONFIG_SPI_LOG_LEVEL);
 #include "spi_context.h"
 #include "spi_esp32_spim.h"
 
-#if defined(CONFIG_SOC_SERIES_ESP32C2) || defined(CONFIG_SOC_SERIES_ESP32C3) ||                    \
-	defined(CONFIG_SOC_SERIES_ESP32C6)
-#define ISR_HANDLER isr_handler_t
-#else
-#define ISR_HANDLER intr_handler_t
-#endif
-
 #define SPI_DMA_MAX_BUFFER_SIZE 4092
 
 static bool spi_esp32_transfer_ongoing(struct spi_esp32_data *data)
@@ -250,7 +237,7 @@ static int spi_esp32_init(const struct device *dev)
 	err = esp_intr_alloc(cfg->irq_source,
 			ESP_PRIO_TO_FLAGS(cfg->irq_priority) |
 			ESP_INT_FLAGS_CHECK(cfg->irq_flags) | ESP_INTR_FLAG_IRAM,
-			(ISR_HANDLER)spi_esp32_isr,
+			(intr_handler_t)spi_esp32_isr,
 			(void *)dev,
 			NULL);
 
diff --git a/drivers/spi/spi_gecko_eusart.c b/drivers/spi/spi_gecko_eusart.c
deleted file mode 100644
index 1ad75d2615d..00000000000
--- a/drivers/spi/spi_gecko_eusart.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * Copyright (c) 2024 Daikin Comfort Technologies North America, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DT_DRV_COMPAT silabs_gecko_spi_eusart
-
-#include <stdbool.h>
-
-#include <zephyr/sys/sys_io.h>
-#include <zephyr/device.h>
-#include <zephyr/drivers/spi.h>
-#include <zephyr/drivers/clock_control.h>
-#include <zephyr/drivers/clock_control/clock_control_silabs.h>
-#include <zephyr/drivers/pinctrl.h>
-#include <zephyr/logging/log.h>
-
-#include <em_cmu.h>
-#include <em_eusart.h>
-
-LOG_MODULE_REGISTER(spi_gecko_eusart, CONFIG_SPI_LOG_LEVEL);
-
-#include "spi_context.h"
-
-#define SPI_WORD_SIZE 8
-
-/* Structure Declarations */
-
-struct spi_gecko_eusart_data {
-	struct spi_context ctx;
-};
-
-struct spi_gecko_eusart_config {
-	EUSART_TypeDef *base;
-	const struct device *clock_dev;
-	const struct silabs_clock_control_cmu_config clock_cfg;
-	uint32_t clock_frequency;
-	const struct pinctrl_dev_config *pcfg;
-};
-
-/* Helper Functions */
-static int spi_eusart_config(const struct device *dev, const struct spi_config *config,
-			     uint16_t *control)
-{
-	struct spi_gecko_eusart_data *data = dev->data;
-	const struct spi_gecko_eusart_config *gecko_config = dev->config;
-	uint32_t spi_frequency;
-
-	EUSART_SpiAdvancedInit_TypeDef eusartAdvancedSpiInit = EUSART_SPI_ADVANCED_INIT_DEFAULT;
-	EUSART_SpiInit_TypeDef eusartInit = EUSART_SPI_MASTER_INIT_DEFAULT_HF;
-
-	int err;
-
-	err = clock_control_get_rate(gecko_config->clock_dev,
-				     (clock_control_subsys_t)&gecko_config->clock_cfg,
-				     &spi_frequency);
-	if (err) {
-		return err;
-	}
-	/* Max supported SPI frequency is half the source clock */
-	spi_frequency /= 2;
-
-	if (spi_context_configured(&data->ctx, config)) {
-		/* Already configured. No need to do it again. */
-		return 0;
-	}
-
-	if (config->operation & SPI_HALF_DUPLEX) {
-		LOG_ERR("Half-duplex not supported");
-		return -ENOTSUP;
-	}
-
-	if (SPI_WORD_SIZE_GET(config->operation) != SPI_WORD_SIZE) {
-		LOG_ERR("Word size must be %d", SPI_WORD_SIZE);
-		return -ENOTSUP;
-	}
-
-	if (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES) &&
-	    (config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
-		LOG_ERR("Only supports single mode");
-		return -ENOTSUP;
-	}
-
-	if (config->operation & SPI_OP_MODE_SLAVE) {
-		LOG_ERR("Slave mode not supported");
-		return -ENOTSUP;
-	}
-
-	/* Set frequency to the minimum of what the device supports, what the
-	 * user has configured the controller to, and the max frequency for the
-	 * transaction.
-	 */
-	if (gecko_config->clock_frequency > spi_frequency) {
-		LOG_ERR("SPI clock-frequency too high");
-		return -EINVAL;
-	}
-	spi_frequency = MIN(gecko_config->clock_frequency, spi_frequency);
-	if (config->frequency) {
-		spi_frequency = MIN(config->frequency, spi_frequency);
-	}
-	eusartInit.bitRate = spi_frequency;
-
-	if (config->operation & SPI_MODE_LOOP) {
-		eusartInit.loopbackEnable = eusartLoopbackEnable;
-	} else {
-		eusartInit.loopbackEnable = eusartLoopbackDisable;
-	}
-
-	/* Set Clock Mode */
-	if (config->operation & SPI_MODE_CPOL) {
-		if (config->operation & SPI_MODE_CPHA) {
-			eusartInit.clockMode = eusartClockMode3;
-		} else {
-			eusartInit.clockMode = eusartClockMode2;
-		}
-	} else {
-		if (config->operation & SPI_MODE_CPHA) {
-			eusartInit.clockMode = eusartClockMode1;
-		} else {
-			eusartInit.clockMode = eusartClockMode0;
-		}
-	}
-
-	if (config->operation & SPI_CS_ACTIVE_HIGH) {
-		eusartAdvancedSpiInit.csPolarity = eusartCsActiveHigh;
-	} else {
-		eusartAdvancedSpiInit.csPolarity = eusartCsActiveLow;
-	}
-
-	eusartAdvancedSpiInit.msbFirst = !(config->operation & SPI_TRANSFER_LSB);
-	eusartAdvancedSpiInit.autoCsEnable = !spi_cs_is_gpio(config);
-	eusartInit.databits = eusartDataBits8;
-	eusartInit.advancedSettings = &eusartAdvancedSpiInit;
-
-	/* Enable EUSART clock */
-	err = clock_control_on(gecko_config->clock_dev,
-						  (clock_control_subsys_t)&gecko_config->clock_cfg);
-	if (err < 0) {
-		return err;
-	}
-
-	/* Initialize the EUSART */
-	EUSART_SpiInit(gecko_config->base, &eusartInit);
-
-	data->ctx.config = config;
-
-	/* Enable the peripheral */
-	gecko_config->base->CMD = (uint32_t)eusartEnable;
-
-	return 0;
-}
-
-static void spi_gecko_eusart_send(EUSART_TypeDef *eusart, uint8_t frame)
-{
-	/* Write frame to register */
-	EUSART_Tx(eusart, frame);
-
-	/* Wait until the transfer ends */
-	while (!(eusart->STATUS & EUSART_STATUS_TXC)) {
-	}
-}
-
-static uint8_t spi_gecko_eusart_recv(EUSART_TypeDef *eusart)
-{
-	/* Return data inside rx register */
-	return EUSART_Rx(eusart);
-}
-
-static bool spi_eusart_transfer_ongoing(struct spi_gecko_eusart_data *data)
-{
-	return spi_context_tx_on(&data->ctx) || spi_context_rx_on(&data->ctx);
-}
-
-static inline uint8_t spi_eusart_next_tx(struct spi_gecko_eusart_data *data)
-{
-	uint8_t tx_frame = 0;
-
-	if (spi_context_tx_buf_on(&data->ctx)) {
-		tx_frame = UNALIGNED_GET((uint8_t *)(data->ctx.tx_buf));
-	}
-
-	return tx_frame;
-}
-
-static int spi_eusart_shift_frames(EUSART_TypeDef *eusart, struct spi_gecko_eusart_data *data)
-{
-	uint8_t tx_frame;
-	uint8_t rx_frame;
-
-	tx_frame = spi_eusart_next_tx(data);
-	spi_gecko_eusart_send(eusart, tx_frame);
-	spi_context_update_tx(&data->ctx, 1, 1);
-
-	rx_frame = spi_gecko_eusart_recv(eusart);
-
-	if (spi_context_rx_buf_on(&data->ctx)) {
-		UNALIGNED_PUT(rx_frame, (uint8_t *)data->ctx.rx_buf);
-	}
-	spi_context_update_rx(&data->ctx, 1, 1);
-	return 0;
-}
-
-static void spi_gecko_eusart_xfer(const struct device *dev, const struct spi_config *config)
-{
-	int ret;
-	struct spi_gecko_eusart_data *data = dev->data;
-	struct spi_context *ctx = &data->ctx;
-	const struct spi_gecko_eusart_config *gecko_config = dev->config;
-
-	spi_context_cs_control(ctx, true);
-
-	do {
-		ret = spi_eusart_shift_frames(gecko_config->base, data);
-	} while (!ret && spi_eusart_transfer_ongoing(data));
-
-	spi_context_cs_control(ctx, false);
-	spi_context_complete(ctx, dev, 0);
-}
-
-/* API Functions */
-static int spi_gecko_eusart_init(const struct device *dev)
-{
-	int err;
-	const struct spi_gecko_eusart_config *config = dev->config;
-	struct spi_gecko_eusart_data *data = dev->data;
-
-	err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
-	if (err < 0) {
-		return err;
-	}
-
-	err = spi_context_cs_configure_all(&data->ctx);
-	if (err < 0) {
-		return err;
-	}
-	spi_context_unlock_unconditionally(&data->ctx);
-
-	return 0;
-}
-
-static int spi_gecko_eusart_transceive(const struct device *dev, const struct spi_config *config,
-				       const struct spi_buf_set *tx_bufs,
-				       const struct spi_buf_set *rx_bufs)
-{
-	struct spi_gecko_eusart_data *data = dev->data;
-	uint16_t control = 0;
-	int ret;
-
-	spi_context_lock(&data->ctx, false, NULL, NULL, config);
-
-	ret = spi_eusart_config(dev, config, &control);
-	if (ret < 0) {
-		spi_context_release(&data->ctx, ret);
-		return ret;
-	}
-
-	spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
-	spi_gecko_eusart_xfer(dev, config);
-
-	spi_context_release(&data->ctx, ret);
-
-	return 0;
-}
-
-#ifdef CONFIG_SPI_ASYNC
-static int spi_gecko_eusart_transceive_async(const struct device *dev,
-					     const struct spi_config *config,
-					     const struct spi_buf_set *tx_bufs,
-					     const struct spi_buf_set *rx_bufs,
-					     struct k_poll_signal *async)
-{
-	return -ENOTSUP;
-}
-#endif /* CONFIG_SPI_ASYNC */
-
-static int spi_gecko_eusart_release(const struct device *dev, const struct spi_config *config)
-{
-	const struct spi_gecko_eusart_config *gecko_config = dev->config;
-	struct spi_gecko_eusart_data *data = dev->data;
-
-	spi_context_unlock_unconditionally(&data->ctx);
-
-	if (!(gecko_config->base->STATUS & EUSART_STATUS_TXIDLE)) {
-		return -EBUSY;
-	}
-	return 0;
-}
-
-/* Device Instantiation */
-static DEVICE_API(spi, spi_gecko_eusart_api) = {
-	.transceive = spi_gecko_eusart_transceive,
-#ifdef CONFIG_SPI_ASYNC
-	.transceive_async = spi_gecko_eusart_transceive_async,
-#endif /* CONFIG_SPI_ASYNC */
-	.release = spi_gecko_eusart_release,
-};
-
-#define SPI_INIT(n)                                                                    \
-	PINCTRL_DT_INST_DEFINE(n);                                                         \
-	static struct spi_gecko_eusart_data spi_gecko_eusart_data_##n = {                  \
-		SPI_CONTEXT_INIT_LOCK(spi_gecko_eusart_data_##n, ctx),                         \
-		SPI_CONTEXT_INIT_SYNC(spi_gecko_eusart_data_##n, ctx),                         \
-		SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx)};                         \
-	static struct spi_gecko_eusart_config spi_gecko_eusart_cfg_##n = {                 \
-		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                     \
-		.base = (EUSART_TypeDef *)DT_INST_REG_ADDR(n),                                 \
-		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),                            \
-		.clock_cfg = SILABS_DT_INST_CLOCK_CFG(n),                                      \
-		.clock_frequency = DT_INST_PROP_OR(n, clock_frequency, 1000000)                \
-	};                                                                                 \
-	SPI_DEVICE_DT_INST_DEFINE(n, spi_gecko_eusart_init, NULL, &spi_gecko_eusart_data_##n,  \
-			      &spi_gecko_eusart_cfg_##n, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,    \
-			      &spi_gecko_eusart_api);
-
-DT_INST_FOREACH_STATUS_OKAY(SPI_INIT)
diff --git a/drivers/spi/spi_gecko_usart.c b/drivers/spi/spi_gecko_usart.c
deleted file mode 100644
index a116e88d49a..00000000000
--- a/drivers/spi/spi_gecko_usart.c
+++ /dev/null
@@ -1,494 +0,0 @@
-/*
- * Copyright (c) 2019 Christian Taedcke <hacking@taedcke.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DT_DRV_COMPAT silabs_gecko_spi_usart
-
-#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
-#include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(spi_gecko);
-#include "spi_context.h"
-
-#include <zephyr/sys/sys_io.h>
-#include <zephyr/device.h>
-#include <zephyr/drivers/spi.h>
-#include <zephyr/drivers/spi/rtio.h>
-#include <soc.h>
-
-#include "em_cmu.h"
-#include "em_usart.h"
-
-#include <stdbool.h>
-
-#ifdef CONFIG_PINCTRL
-#include <zephyr/drivers/pinctrl.h>
-#else
-#ifndef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
-#error "Individual pin location support is required"
-#endif
-#endif /* CONFIG_PINCTRL */
-
-#ifdef CONFIG_CLOCK_CONTROL
-#include <zephyr/drivers/clock_control.h>
-#include <zephyr/drivers/clock_control/clock_control_silabs.h>
-#define GET_GECKO_USART_CLOCK(idx)                            \
-	.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
-	.clock_cfg = SILABS_DT_INST_CLOCK_CFG(idx),
-#elif DT_NODE_HAS_PROP(n, peripheral_id)
-#define CLOCK_USART(id) _CONCAT(cmuClock_USART, id)
-#define GET_GECKO_USART_CLOCK(n) \
-	.clock = CLOCK_USART(DT_INST_PROP(n, peripheral_id)),
-#else
-#if (USART_COUNT == 1)
-#define CLOCK_USART(ref)	(((ref) == USART0) ? cmuClock_USART0 \
-			       : -1)
-#elif (USART_COUNT == 2)
-#define CLOCK_USART(ref)	(((ref) == USART0) ? cmuClock_USART0 \
-			       : ((ref) == USART1) ? cmuClock_USART1 \
-			       : -1)
-#elif (USART_COUNT == 3)
-#define CLOCK_USART(ref)	(((ref) == USART0) ? cmuClock_USART0 \
-			       : ((ref) == USART1) ? cmuClock_USART1 \
-			       : ((ref) == USART2) ? cmuClock_USART2 \
-			       : -1)
-#elif (USART_COUNT == 4)
-#define CLOCK_USART(ref)	(((ref) == USART0) ? cmuClock_USART0 \
-			       : ((ref) == USART1) ? cmuClock_USART1 \
-			       : ((ref) == USART2) ? cmuClock_USART2 \
-			       : ((ref) == USART3) ? cmuClock_USART3 \
-			       : -1)
-#elif (USART_COUNT == 5)
-#define CLOCK_USART(ref)	(((ref) == USART0) ? cmuClock_USART0 \
-			       : ((ref) == USART1) ? cmuClock_USART1 \
-			       : ((ref) == USART2) ? cmuClock_USART2 \
-			       : ((ref) == USART3) ? cmuClock_USART3 \
-			       : ((ref) == USART4) ? cmuClock_USART4 \
-			       : -1)
-#elif (USART_COUNT == 6)
-#define CLOCK_USART(ref)	(((ref) == USART0) ? cmuClock_USART0 \
-			       : ((ref) == USART1) ? cmuClock_USART1 \
-			       : ((ref) == USART2) ? cmuClock_USART2 \
-			       : ((ref) == USART3) ? cmuClock_USART3 \
-			       : ((ref) == USART4) ? cmuClock_USART4 \
-			       : ((ref) == USART5) ? cmuClock_USART5 \
-			       : -1)
-#else
-#error "Undefined number of USARTs."
-#endif /* USART_COUNT */
-#define GET_GECKO_USART_CLOCK(id) \
-	.clock = CLOCK_USART((USART_TypeDef *)DT_INST_REG_ADDR(id)),
-#endif /* DT_NODE_HAS_PROP(n, peripheral_id) */
-
-
-#define SPI_WORD_SIZE 8
-
-/* Structure Declarations */
-
-struct spi_gecko_data {
-	struct spi_context ctx;
-};
-
-struct spi_gecko_config {
-	USART_TypeDef *base;
-#ifdef CONFIG_CLOCK_CONTROL
-	const struct device *clock_dev;
-	const struct silabs_clock_control_cmu_config clock_cfg;
-#else
-	CMU_Clock_TypeDef clock;
-#endif
-	uint32_t clock_frequency;
-#ifdef CONFIG_PINCTRL
-	const struct pinctrl_dev_config *pcfg;
-#else
-	struct soc_gpio_pin pin_rx;
-	struct soc_gpio_pin pin_tx;
-	struct soc_gpio_pin pin_clk;
-	uint8_t loc_rx;
-	uint8_t loc_tx;
-	uint8_t loc_clk;
-#endif /* CONFIG_PINCTRL */
-};
-
-
-/* Helper Functions */
-static int spi_config(const struct device *dev,
-		      const struct spi_config *config,
-		      uint16_t *control)
-{
-	const struct spi_gecko_config *gecko_config = dev->config;
-	struct spi_gecko_data *data = dev->data;
-	mem_addr_t ctrl_reg = (mem_addr_t)&gecko_config->base->CTRL;
-	uint32_t spi_frequency;
-
-#ifdef CONFIG_CLOCK_CONTROL
-	int err;
-
-	err = clock_control_get_rate(gecko_config->clock_dev,
-				     (clock_control_subsys_t)&gecko_config->clock_cfg,
-				     &spi_frequency);
-	if (err) {
-		return err;
-	}
-	/* Max supported SPI frequency is half the source clock */
-	spi_frequency /= 2;
-#else
-	spi_frequency = CMU_ClockFreqGet(gecko_config->clock) / 2;
-#endif
-
-	if (config->operation & SPI_HALF_DUPLEX) {
-		LOG_ERR("Half-duplex not supported");
-		return -ENOTSUP;
-	}
-
-	if (SPI_WORD_SIZE_GET(config->operation) != SPI_WORD_SIZE) {
-		LOG_ERR("Word size must be %d", SPI_WORD_SIZE);
-		return -ENOTSUP;
-	}
-
-	if (config->operation & SPI_CS_ACTIVE_HIGH) {
-		sys_set_bit(ctrl_reg, _USART_CTRL_CSINV_SHIFT);
-	} else {
-		sys_clear_bit(ctrl_reg, _USART_CTRL_CSINV_SHIFT);
-	}
-
-	if (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES) &&
-	    (config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
-		LOG_ERR("Only supports single mode");
-		return -ENOTSUP;
-	}
-
-	if (config->operation & SPI_TRANSFER_LSB) {
-		sys_clear_bit(ctrl_reg, _USART_CTRL_MSBF_SHIFT);
-	} else {
-		sys_set_bit(ctrl_reg, _USART_CTRL_MSBF_SHIFT);
-	}
-
-	if (config->operation & SPI_OP_MODE_SLAVE) {
-		LOG_ERR("Slave mode not supported");
-		return -ENOTSUP;
-	}
-
-	/* Set frequency to the minimum of what the device supports, what the
-	 * user has configured the controller to, and the max frequency for the
-	 * transaction.
-	 */
-	if (gecko_config->clock_frequency > spi_frequency) {
-		LOG_ERR("SPI clock-frequency too high");
-		return -EINVAL;
-	}
-	spi_frequency = MIN(gecko_config->clock_frequency, spi_frequency);
-	if (config->frequency) {
-		spi_frequency = MIN(config->frequency, spi_frequency);
-	}
-	USART_BaudrateSyncSet(gecko_config->base, 0, spi_frequency);
-
-	/* Set Loopback */
-	if (config->operation & SPI_MODE_LOOP) {
-		gecko_config->base->CTRL |= USART_CTRL_LOOPBK;
-	} else {
-		gecko_config->base->CTRL &= ~USART_CTRL_LOOPBK;
-	}
-
-	/* Set CPOL */
-	if (config->operation & SPI_MODE_CPOL) {
-		gecko_config->base->CTRL |= USART_CTRL_CLKPOL;
-	} else {
-		gecko_config->base->CTRL &= ~USART_CTRL_CLKPOL;
-	}
-
-	/* Set CPHA */
-	if (config->operation & SPI_MODE_CPHA) {
-		gecko_config->base->CTRL |= USART_CTRL_CLKPHA;
-	} else {
-		gecko_config->base->CTRL &= ~USART_CTRL_CLKPHA;
-	}
-
-	/* Set word size */
-	gecko_config->base->FRAME = usartDatabits8
-	    | USART_FRAME_STOPBITS_DEFAULT
-	    | USART_FRAME_PARITY_DEFAULT;
-
-	/* At this point, it's mandatory to set this on the context! */
-	data->ctx.config = config;
-
-	return 0;
-}
-
-static void spi_gecko_send(USART_TypeDef *usart, uint8_t frame)
-{
-	/* Write frame to register */
-	USART_Tx(usart, frame);
-
-	/* Wait until the transfer ends */
-	while (!(usart->STATUS & USART_STATUS_TXC)) {
-	}
-}
-
-static uint8_t spi_gecko_recv(USART_TypeDef *usart)
-{
-	/* Return data inside rx register */
-	return (uint8_t)usart->RXDATA;
-}
-
-static bool spi_gecko_transfer_ongoing(struct spi_gecko_data *data)
-{
-	return spi_context_tx_on(&data->ctx) || spi_context_rx_on(&data->ctx);
-}
-
-static inline uint8_t spi_gecko_next_tx(struct spi_gecko_data *data)
-{
-	uint8_t tx_frame = 0;
-
-	if (spi_context_tx_buf_on(&data->ctx)) {
-		tx_frame = UNALIGNED_GET((uint8_t *)(data->ctx.tx_buf));
-	}
-
-	return tx_frame;
-}
-
-static int spi_gecko_shift_frames(USART_TypeDef *usart,
-				  struct spi_gecko_data *data)
-{
-	uint8_t tx_frame;
-	uint8_t rx_frame;
-
-	tx_frame = spi_gecko_next_tx(data);
-	spi_gecko_send(usart, tx_frame);
-	spi_context_update_tx(&data->ctx, 1, 1);
-
-	rx_frame = spi_gecko_recv(usart);
-
-	if (spi_context_rx_buf_on(&data->ctx)) {
-		UNALIGNED_PUT(rx_frame, (uint8_t *)data->ctx.rx_buf);
-	}
-	spi_context_update_rx(&data->ctx, 1, 1);
-	return 0;
-}
-
-
-static void spi_gecko_xfer(const struct device *dev,
-			   const struct spi_config *config)
-{
-	int ret;
-	struct spi_gecko_data *data = dev->data;
-	struct spi_context *ctx = &data->ctx;
-	const struct spi_gecko_config *gecko_config = dev->config;
-
-	spi_context_cs_control(ctx, true);
-
-	do {
-		ret = spi_gecko_shift_frames(gecko_config->base, data);
-	} while (!ret && spi_gecko_transfer_ongoing(data));
-
-	spi_context_cs_control(ctx, false);
-	spi_context_complete(ctx, dev, 0);
-}
-
-#ifndef CONFIG_PINCTRL
-static void spi_gecko_init_pins(const struct device *dev)
-{
-	const struct spi_gecko_config *config = dev->config;
-
-	GPIO_PinModeSet(config->pin_rx.port, config->pin_rx.pin,
-			 config->pin_rx.mode, config->pin_rx.out);
-	GPIO_PinModeSet(config->pin_tx.port, config->pin_tx.pin,
-			 config->pin_tx.mode, config->pin_tx.out);
-	GPIO_PinModeSet(config->pin_clk.port, config->pin_clk.pin,
-			 config->pin_clk.mode, config->pin_clk.out);
-
-	/* disable all pins while configuring */
-	config->base->ROUTEPEN = 0;
-
-	config->base->ROUTELOC0 =
-		(config->loc_tx << _USART_ROUTELOC0_TXLOC_SHIFT) |
-		(config->loc_rx << _USART_ROUTELOC0_RXLOC_SHIFT) |
-		(config->loc_clk << _USART_ROUTELOC0_CLKLOC_SHIFT);
-
-	config->base->ROUTELOC1 = _USART_ROUTELOC1_RESETVALUE;
-
-	config->base->ROUTEPEN = USART_ROUTEPEN_RXPEN | USART_ROUTEPEN_TXPEN |
-		USART_ROUTEPEN_CLKPEN;
-}
-#endif /* !CONFIG_PINCTRL */
-
-
-/* API Functions */
-
-static int spi_gecko_init(const struct device *dev)
-{
-	int err;
-	const struct spi_gecko_config *config = dev->config;
-	struct spi_gecko_data *data = dev->data;
-	USART_InitSync_TypeDef usartInit = USART_INITSYNC_DEFAULT;
-
-	/* The peripheral and gpio clock are already enabled from soc and gpio
-	 * driver
-	 */
-
-	usartInit.enable = usartDisable;
-	usartInit.baudrate = 1000000;
-	usartInit.databits = usartDatabits8;
-	usartInit.master = 1;
-	usartInit.msbf = 1;
-	usartInit.clockMode = usartClockMode0;
-#if defined(USART_INPUT_RXPRS) && defined(USART_TRIGCTRL_AUTOTXTEN)
-	usartInit.prsRxEnable = 0;
-	usartInit.prsRxCh = 0;
-	usartInit.autoTx = 0;
-#endif
-
-	/* Enable USART clock */
-#ifdef CONFIG_CLOCK_CONTROL
-	err = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_cfg);
-	if (err < 0) {
-		return err;
-	}
-#else
-	CMU_ClockEnable(config->clock, true);
-#endif
-
-	/* Init USART */
-	USART_InitSync(config->base, &usartInit);
-
-#ifdef CONFIG_PINCTRL
-	err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
-	if (err < 0) {
-		return err;
-	}
-#else
-	/* Initialize USART pins */
-	spi_gecko_init_pins(dev);
-#endif /* CONFIG_PINCTRL */
-
-	err = spi_context_cs_configure_all(&data->ctx);
-	if (err < 0) {
-		return err;
-	}
-
-	/* Enable the peripheral */
-	config->base->CMD = (uint32_t) usartEnable;
-
-	spi_context_unlock_unconditionally(&data->ctx);
-
-	return 0;
-}
-
-static int spi_gecko_transceive(const struct device *dev,
-				const struct spi_config *config,
-				const struct spi_buf_set *tx_bufs,
-				const struct spi_buf_set *rx_bufs)
-{
-	struct spi_gecko_data *data = dev->data;
-	uint16_t control = 0;
-	int ret;
-
-	spi_context_lock(&data->ctx, false, NULL, NULL, config);
-
-	ret = spi_config(dev, config, &control);
-	if (ret < 0) {
-		spi_context_release(&data->ctx, ret);
-		return ret;
-	}
-
-	spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
-	spi_gecko_xfer(dev, config);
-
-	spi_context_release(&data->ctx, ret);
-
-	return 0;
-}
-
-#ifdef CONFIG_SPI_ASYNC
-static int spi_gecko_transceive_async(const struct device *dev,
-				      const struct spi_config *config,
-				      const struct spi_buf_set *tx_bufs,
-				      const struct spi_buf_set *rx_bufs,
-				      struct k_poll_signal *async)
-{
-	return -ENOTSUP;
-}
-#endif /* CONFIG_SPI_ASYNC */
-
-static int spi_gecko_release(const struct device *dev,
-			     const struct spi_config *config)
-{
-	struct spi_gecko_data *data = dev->data;
-
-	spi_context_unlock_unconditionally(&data->ctx);
-
-	return 0;
-}
-
-/* Device Instantiation */
-static DEVICE_API(spi, spi_gecko_api) = {
-	.transceive = spi_gecko_transceive,
-#ifdef CONFIG_SPI_ASYNC
-	.transceive_async = spi_gecko_transceive_async,
-#endif /* CONFIG_SPI_ASYNC */
-#ifdef CONFIG_SPI_RTIO
-	.iodev_submit = spi_rtio_iodev_default_submit,
-#endif
-	.release = spi_gecko_release,
-};
-
-#ifdef CONFIG_PINCTRL
-#define SPI_INIT(n)				    \
-	PINCTRL_DT_INST_DEFINE(n);			    \
-	static struct spi_gecko_data spi_gecko_data_##n = { \
-		SPI_CONTEXT_INIT_LOCK(spi_gecko_data_##n, ctx), \
-		SPI_CONTEXT_INIT_SYNC(spi_gecko_data_##n, ctx), \
-		SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx)	\
-	}; \
-	static struct spi_gecko_config spi_gecko_cfg_##n = { \
-	    .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
-	    .base = (USART_TypeDef *) \
-		 DT_INST_REG_ADDR(n), \
-	    GET_GECKO_USART_CLOCK(n) \
-	    .clock_frequency = DT_INST_PROP_OR(n, clock_frequency, 1000000) \
-	}; \
-	SPI_DEVICE_DT_INST_DEFINE(n, \
-			spi_gecko_init, \
-			NULL, \
-			&spi_gecko_data_##n, \
-			&spi_gecko_cfg_##n, \
-			POST_KERNEL, \
-			CONFIG_SPI_INIT_PRIORITY, \
-			&spi_gecko_api);
-#else
-#define SPI_INIT(n)				    \
-	static struct spi_gecko_data spi_gecko_data_##n = { \
-		SPI_CONTEXT_INIT_LOCK(spi_gecko_data_##n, ctx), \
-		SPI_CONTEXT_INIT_SYNC(spi_gecko_data_##n, ctx), \
-		SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx)	\
-	}; \
-	static struct spi_gecko_config spi_gecko_cfg_##n = { \
-	    .base = (USART_TypeDef *) \
-		 DT_INST_REG_ADDR(n), \
-	    GET_GECKO_USART_CLOCK(n) \
-	    .clock_frequency = DT_INST_PROP_OR(n, clock_frequency, 1000000), \
-	    .pin_rx = { DT_INST_PROP_BY_IDX(n, location_rx, 1), \
-			DT_INST_PROP_BY_IDX(n, location_rx, 2), \
-			gpioModeInput, 1},				\
-	    .pin_tx = { DT_INST_PROP_BY_IDX(n, location_tx, 1), \
-			DT_INST_PROP_BY_IDX(n, location_tx, 2), \
-			gpioModePushPull, 1},				\
-	    .pin_clk = { DT_INST_PROP_BY_IDX(n, location_clk, 1), \
-			DT_INST_PROP_BY_IDX(n, location_clk, 2), \
-			gpioModePushPull, 1},				\
-	    .loc_rx = DT_INST_PROP_BY_IDX(n, location_rx, 0), \
-	    .loc_tx = DT_INST_PROP_BY_IDX(n, location_tx, 0), \
-	    .loc_clk = DT_INST_PROP_BY_IDX(n, location_clk, 0), \
-	}; \
-	SPI_DEVICE_DT_INST_DEFINE(n, \
-			spi_gecko_init, \
-			NULL, \
-			&spi_gecko_data_##n, \
-			&spi_gecko_cfg_##n, \
-			POST_KERNEL, \
-			CONFIG_SPI_INIT_PRIORITY, \
-			&spi_gecko_api);
-#endif /* CONFIG_PINCTRL */
-
-DT_INST_FOREACH_STATUS_OKAY(SPI_INIT)
diff --git a/drivers/spi/spi_ifx_cat1.c b/drivers/spi/spi_ifx_cat1.c
index bec34768556..2a1cf0b6a8b 100644
--- a/drivers/spi/spi_ifx_cat1.c
+++ b/drivers/spi/spi_ifx_cat1.c
@@ -45,11 +45,14 @@ struct ifx_cat1_spi_data {
 
 static int32_t get_hw_block_num(CySCB_Type *reg_addr)
 {
+	extern const uint8_t _CYHAL_SCB_BASE_ADDRESS_INDEX[_SCB_ARRAY_SIZE];
+	extern CySCB_Type *const _CYHAL_SCB_BASE_ADDRESSES[_SCB_ARRAY_SIZE];
+
 	uint32_t i;
 
 	for (i = 0u; i < _SCB_ARRAY_SIZE; i++) {
 		if (_CYHAL_SCB_BASE_ADDRESSES[i] == reg_addr) {
-			return i;
+			return _CYHAL_SCB_BASE_ADDRESS_INDEX[i];
 		}
 	}
 
diff --git a/drivers/spi/spi_ll_stm32.c b/drivers/spi/spi_ll_stm32.c
index f509115592e..dbca9c77e6a 100644
--- a/drivers/spi/spi_ll_stm32.c
+++ b/drivers/spi/spi_ll_stm32.c
@@ -30,16 +30,9 @@ LOG_MODULE_REGISTER(spi_ll_stm32);
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/irq.h>
 #include <zephyr/mem_mgmt/mem_attr.h>
-
-#ifdef CONFIG_DCACHE
 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
-#endif /* CONFIG_DCACHE */
-
-#ifdef CONFIG_NOCACHE_MEMORY
 #include <zephyr/linker/linker-defs.h>
-#elif defined(CONFIG_CACHE_MANAGEMENT)
 #include <zephyr/arch/cache.h>
-#endif /* CONFIG_NOCACHE_MEMORY */
 
 #include "spi_ll_stm32.h"
 
@@ -274,23 +267,35 @@ static int spi_stm32_dma_rx_load(const struct device *dev, uint8_t *buf,
 	return dma_start(data->dma_rx.dma_dev, data->dma_rx.channel);
 }
 
-static int spi_dma_move_buffers(const struct device *dev, size_t len)
+static int spi_dma_move_rx_buffers(const struct device *dev, size_t len)
 {
 	struct spi_stm32_data *data = dev->data;
-	int ret;
 	size_t dma_segment_len;
 
 	dma_segment_len = len * data->dma_rx.dma_cfg.dest_data_size;
-	ret = spi_stm32_dma_rx_load(dev, data->ctx.rx_buf, dma_segment_len);
+	return spi_stm32_dma_rx_load(dev, data->ctx.rx_buf, dma_segment_len);
+}
+
+static int spi_dma_move_tx_buffers(const struct device *dev, size_t len)
+{
+	struct spi_stm32_data *data = dev->data;
+	size_t dma_segment_len;
+
+	dma_segment_len = len * data->dma_tx.dma_cfg.source_data_size;
+	return spi_stm32_dma_tx_load(dev, data->ctx.tx_buf, dma_segment_len);
+}
+
+static int spi_dma_move_buffers(const struct device *dev, size_t len)
+{
+	int ret;
+
+	ret = spi_dma_move_rx_buffers(dev, len);
 
 	if (ret != 0) {
 		return ret;
 	}
 
-	dma_segment_len = len * data->dma_tx.dma_cfg.source_data_size;
-	ret = spi_stm32_dma_tx_load(dev, data->ctx.tx_buf, dma_segment_len);
-
-	return ret;
+	return spi_dma_move_tx_buffers(dev, len);
 }
 
 #endif /* CONFIG_SPI_STM32_DMA */
@@ -366,11 +371,15 @@ static int spi_stm32_get_err(SPI_TypeDef *spi)
 
 static void spi_stm32_shift_fifo(SPI_TypeDef *spi, struct spi_stm32_data *data)
 {
-	if (ll_func_rx_is_not_empty(spi)) {
+	uint32_t transfer_dir = LL_SPI_GetTransferDirection(spi);
+
+	if (transfer_dir != LL_SPI_HALF_DUPLEX_TX &&
+		ll_func_rx_is_not_empty(spi)) {
 		spi_stm32_read_next_frame(spi, data);
 	}
 
-	if (ll_func_tx_is_not_full(spi)) {
+	if (transfer_dir != LL_SPI_HALF_DUPLEX_RX &&
+		ll_func_tx_is_not_full(spi)) {
 		spi_stm32_send_next_frame(spi, data);
 	}
 }
@@ -382,17 +391,23 @@ static void spi_stm32_shift_m(const struct spi_stm32_config *cfg,
 	if (cfg->fifo_enabled) {
 		spi_stm32_shift_fifo(cfg->spi, data);
 	} else {
-		while (!ll_func_tx_is_not_full(cfg->spi)) {
-			/* NOP */
-		}
+		uint32_t transfer_dir = LL_SPI_GetTransferDirection(cfg->spi);
 
-		spi_stm32_send_next_frame(cfg->spi, data);
+		if (transfer_dir != LL_SPI_HALF_DUPLEX_RX) {
+			while (!ll_func_tx_is_not_full(cfg->spi)) {
+				/* NOP */
+			}
 
-		while (!ll_func_rx_is_not_empty(cfg->spi)) {
-			/* NOP */
+			spi_stm32_send_next_frame(cfg->spi, data);
 		}
 
-		spi_stm32_read_next_frame(cfg->spi, data);
+		if (transfer_dir != LL_SPI_HALF_DUPLEX_TX) {
+			while (!ll_func_rx_is_not_empty(cfg->spi)) {
+				/* NOP */
+			}
+
+			spi_stm32_read_next_frame(cfg->spi, data);
+		}
 	}
 }
 
@@ -440,7 +455,7 @@ static void spi_stm32_shift_s(SPI_TypeDef *spi, struct spi_stm32_data *data)
 static int spi_stm32_shift_frames(const struct spi_stm32_config *cfg,
 	struct spi_stm32_data *data)
 {
-	uint16_t operation = data->ctx.config->operation;
+	spi_operation_t operation = data->ctx.config->operation;
 
 	if (SPI_OP_MODE_GET(operation) == SPI_OP_MODE_MASTER) {
 		spi_stm32_shift_m(cfg, data);
@@ -511,11 +526,15 @@ static void spi_stm32_complete(const struct device *dev, int status)
 	}
 
 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
+	uint32_t transfer_dir = LL_SPI_GetTransferDirection(spi);
+
 	if (cfg->fifo_enabled) {
 		LL_SPI_ClearFlag_TXTF(spi);
 		LL_SPI_ClearFlag_OVR(spi);
 		LL_SPI_ClearFlag_EOT(spi);
 		LL_SPI_SetTransferSize(spi, 0);
+	} else if (transfer_dir == LL_SPI_HALF_DUPLEX_RX) {
+		LL_SPI_SetTransferSize(spi, 0);
 	}
 #endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi) */
 
@@ -557,14 +576,31 @@ static void spi_stm32_isr(const struct device *dev)
 		err = spi_stm32_shift_frames(cfg, data);
 	}
 
-	if (err || !spi_stm32_transfer_ongoing(data)) {
+	if (err) {
 		spi_stm32_complete(dev, err);
 	}
+
+	uint32_t transfer_dir = LL_SPI_GetTransferDirection(spi);
+
+	if (transfer_dir == LL_SPI_FULL_DUPLEX) {
+		if (!spi_stm32_transfer_ongoing(data)) {
+			spi_stm32_complete(dev, err);
+		}
+	} else if (transfer_dir == LL_SPI_HALF_DUPLEX_TX) {
+		if (!spi_context_tx_on(&data->ctx)) {
+			spi_stm32_complete(dev, err);
+		}
+	} else {
+		if (!spi_context_rx_on(&data->ctx)) {
+			spi_stm32_complete(dev, err);
+		}
+	}
 }
 #endif /* CONFIG_SPI_STM32_INTERRUPT */
 
 static int spi_stm32_configure(const struct device *dev,
-			       const struct spi_config *config)
+			       const struct spi_config *config,
+			       bool write)
 {
 	const struct spi_stm32_config *cfg = dev->config;
 	struct spi_stm32_data *data = dev->data;
@@ -583,7 +619,13 @@ static int spi_stm32_configure(const struct device *dev,
 	int br;
 
 	if (spi_context_configured(&data->ctx, config)) {
-		/* Nothing to do */
+		if (config->operation & SPI_HALF_DUPLEX) {
+			if (write) {
+				LL_SPI_SetTransferDirection(spi, LL_SPI_HALF_DUPLEX_TX);
+			} else {
+				LL_SPI_SetTransferDirection(spi, LL_SPI_HALF_DUPLEX_RX);
+			}
+		}
 		return 0;
 	}
 
@@ -652,7 +694,15 @@ static int spi_stm32_configure(const struct device *dev,
 		LL_SPI_SetClockPhase(spi, LL_SPI_PHASE_1EDGE);
 	}
 
-	LL_SPI_SetTransferDirection(spi, LL_SPI_FULL_DUPLEX);
+	if (config->operation & SPI_HALF_DUPLEX) {
+		if (write) {
+			LL_SPI_SetTransferDirection(spi, LL_SPI_HALF_DUPLEX_TX);
+		} else {
+			LL_SPI_SetTransferDirection(spi, LL_SPI_HALF_DUPLEX_RX);
+		}
+	} else {
+		LL_SPI_SetTransferDirection(spi, LL_SPI_FULL_DUPLEX);
+	}
 
 	if (config->operation & SPI_TRANSFER_LSB) {
 		LL_SPI_SetTransferBitOrder(spi, LL_SPI_LSB_FIRST);
@@ -744,7 +794,14 @@ static int32_t spi_stm32_count_bufset_frames(const struct spi_config *config,
 	if ((num_bytes % bytes_per_frame) != 0) {
 		return -EINVAL;
 	}
-	return num_bytes / bytes_per_frame;
+
+	int frames = num_bytes / bytes_per_frame;
+
+	if (frames > UINT16_MAX) {
+		return -EMSGSIZE;
+	}
+
+	return frames;
 }
 
 static int32_t spi_stm32_count_total_frames(const struct spi_config *config,
@@ -763,14 +820,80 @@ static int32_t spi_stm32_count_total_frames(const struct spi_config *config,
 		return rx_frames;
 	}
 
-	if (tx_frames > UINT16_MAX || rx_frames > UINT16_MAX) {
-		return -EMSGSIZE;
-	}
-
 	return MAX(rx_frames, tx_frames);
 }
 #endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi) */
 
+static int spi_stm32_half_duplex_switch_to_receive(const struct spi_stm32_config *cfg,
+	struct spi_stm32_data *data)
+{
+	SPI_TypeDef *spi = cfg->spi;
+
+	if (!spi_context_tx_on(&data->ctx) &&
+		spi_context_rx_on(&data->ctx)) {
+#ifndef CONFIG_SPI_STM32_INTERRUPT
+		while (ll_func_spi_is_busy(spi)) {
+			/* NOP */
+		}
+		LL_SPI_Disable(spi);
+#endif /* CONFIG_SPI_STM32_INTERRUPT*/
+
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
+		const struct spi_config *config = data->ctx.config;
+
+		if (SPI_OP_MODE_GET(config->operation) == SPI_OP_MODE_MASTER) {
+			int num_bytes = spi_context_total_rx_len(&data->ctx);
+			uint8_t bytes_per_frame = SPI_WORD_SIZE_GET(config->operation) / 8;
+
+			if ((num_bytes % bytes_per_frame) != 0) {
+				return -EINVAL;
+			}
+
+			LL_SPI_SetTransferSize(spi, (uint32_t) num_bytes / bytes_per_frame);
+		}
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi) */
+
+		LL_SPI_SetTransferDirection(spi, LL_SPI_HALF_DUPLEX_RX);
+
+		LL_SPI_Enable(spi);
+
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
+		/* With the STM32MP1, STM32U5 and the STM32H7,
+		 * if the device is the SPI master,
+		 * we need to enable the start of the transfer with
+		 * LL_SPI_StartMasterTransfer(spi).
+		 */
+		if (LL_SPI_GetMode(spi) == LL_SPI_MODE_MASTER) {
+			LL_SPI_StartMasterTransfer(spi);
+			while (!LL_SPI_IsActiveMasterTransfer(spi)) {
+				/* NOP */
+			}
+		}
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi) */
+
+#if CONFIG_SOC_SERIES_STM32H7X
+		/*
+		 * Add a small delay after enabling to prevent transfer stalling at high
+		 * system clock frequency (see errata sheet ES0392).
+		 */
+		k_busy_wait(WAIT_1US);
+#endif
+
+#ifdef CONFIG_SPI_STM32_INTERRUPT
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
+		if (cfg->fifo_enabled) {
+			LL_SPI_EnableIT_EOT(spi);
+		}
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi) */
+
+		ll_func_enable_int_errors(spi);
+		ll_func_enable_int_rx_not_empty(spi);
+#endif /* CONFIG_SPI_STM32_INTERRUPT */
+	}
+
+	return 0;
+}
+
 static int transceive(const struct device *dev,
 		      const struct spi_config *config,
 		      const struct spi_buf_set *tx_bufs,
@@ -798,7 +921,7 @@ static int transceive(const struct device *dev,
 
 	spi_stm32_pm_policy_state_lock_get(dev);
 
-	ret = spi_stm32_configure(dev, config);
+	ret = spi_stm32_configure(dev, config, tx_bufs != NULL);
 	if (ret) {
 		goto end;
 	}
@@ -810,10 +933,23 @@ static int transceive(const struct device *dev,
 		spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 2);
 	}
 
+	uint32_t transfer_dir = LL_SPI_GetTransferDirection(spi);
+
 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
 	if (cfg->fifo_enabled && SPI_OP_MODE_GET(config->operation) == SPI_OP_MODE_MASTER) {
-		int total_frames = spi_stm32_count_total_frames(
-			config, tx_bufs, rx_bufs);
+		int total_frames;
+
+		if (transfer_dir == LL_SPI_FULL_DUPLEX) {
+			total_frames = spi_stm32_count_total_frames(
+				config, tx_bufs, rx_bufs);
+		} else if (transfer_dir == LL_SPI_HALF_DUPLEX_TX) {
+			total_frames = spi_stm32_count_bufset_frames(
+				config, tx_bufs);
+		} else {
+			total_frames = spi_stm32_count_bufset_frames(
+				config, rx_bufs);
+		}
+
 		if (total_frames < 0) {
 			ret = total_frames;
 			goto end;
@@ -866,10 +1002,24 @@ static int transceive(const struct device *dev,
 
 	ll_func_enable_int_tx_empty(spi);
 
-	ret = spi_context_wait_for_completion(&data->ctx);
+	do {
+		ret = spi_context_wait_for_completion(&data->ctx);
+
+		if (!ret &&
+			transfer_dir == LL_SPI_HALF_DUPLEX_TX) {
+			ret = spi_stm32_half_duplex_switch_to_receive(cfg, data);
+			transfer_dir = LL_SPI_GetTransferDirection(spi);
+		}
+	} while (!ret && spi_stm32_transfer_ongoing(data));
 #else /* CONFIG_SPI_STM32_INTERRUPT */
 	do {
 		ret = spi_stm32_shift_frames(cfg, data);
+
+		if (!ret &&
+			transfer_dir == LL_SPI_HALF_DUPLEX_TX) {
+			ret = spi_stm32_half_duplex_switch_to_receive(cfg, data);
+			transfer_dir = LL_SPI_GetTransferDirection(spi);
+		}
 	} while (!ret && spi_stm32_transfer_ongoing(data));
 
 	spi_stm32_complete(dev, ret);
@@ -925,7 +1075,7 @@ static int wait_dma_rx_tx_done(const struct device *dev)
 }
 
 #ifdef CONFIG_DCACHE
-static bool buf_in_nocache(uintptr_t buf, size_t len_bytes)
+static bool buf_in_nocache(uintptr_t buf __maybe_unused, size_t len_bytes __maybe_unused)
 {
 	bool buf_within_nocache = false;
 
@@ -938,9 +1088,11 @@ static bool buf_in_nocache(uintptr_t buf, size_t len_bytes)
 	}
 #endif /* CONFIG_NOCACHE_MEMORY */
 
+#ifdef CONFIG_MEM_ATTR
 	/* Check if buffer is in nocache memory region defined in DT */
 	buf_within_nocache = mem_attr_check_buf(
 		(void *)buf, len_bytes, DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)) == 0;
+#endif /* CONFIG_MEM_ATTR */
 
 	return buf_within_nocache;
 }
@@ -999,11 +1151,26 @@ static int transceive_dma(const struct device *dev,
 
 	k_sem_reset(&data->status_sem);
 
-	ret = spi_stm32_configure(dev, config);
+	ret = spi_stm32_configure(dev, config, tx_bufs != NULL);
 	if (ret) {
 		goto end;
 	}
 
+	uint32_t transfer_dir = LL_SPI_GetTransferDirection(spi);
+
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
+	if (transfer_dir == LL_SPI_HALF_DUPLEX_RX) {
+		int frames = spi_stm32_count_bufset_frames(config, rx_bufs);
+
+		if (frames < 0) {
+			ret = frames;
+			goto end;
+		}
+
+		LL_SPI_SetTransferSize(cfg->spi, frames);
+	}
+#endif /* st_stm32h7_spi */
+
 	/* Set buffers info */
 	if (SPI_WORD_SIZE_GET(config->operation) == 8) {
 		spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
@@ -1013,11 +1180,22 @@ static int transceive_dma(const struct device *dev,
 
 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
 	/* set request before enabling (else SPI CFG1 reg is write protected) */
-	LL_SPI_EnableDMAReq_RX(spi);
-	LL_SPI_EnableDMAReq_TX(spi);
+	if (transfer_dir == LL_SPI_FULL_DUPLEX) {
+		LL_SPI_EnableDMAReq_RX(spi);
+		LL_SPI_EnableDMAReq_TX(spi);
+	} else if (transfer_dir == LL_SPI_HALF_DUPLEX_TX) {
+		LL_SPI_EnableDMAReq_TX(spi);
+	} else {
+		LL_SPI_EnableDMAReq_RX(spi);
+	}
 
 	LL_SPI_Enable(spi);
-	if (LL_SPI_GetMode(spi) == LL_SPI_MODE_MASTER) {
+
+	/* In half-duplex rx mode, start transfer after
+	 * setting DMA configurations
+	 */
+	if (transfer_dir != LL_SPI_HALF_DUPLEX_RX &&
+		LL_SPI_GetMode(spi) == LL_SPI_MODE_MASTER) {
 		LL_SPI_StartMasterTransfer(spi);
 	}
 #else
@@ -1030,17 +1208,33 @@ static int transceive_dma(const struct device *dev,
 	while (data->ctx.rx_len > 0 || data->ctx.tx_len > 0) {
 		size_t dma_len;
 
-		if (data->ctx.rx_len == 0) {
+		data->status_flags = 0;
+
+		if (transfer_dir == LL_SPI_FULL_DUPLEX) {
+			if (data->ctx.rx_len == 0) {
+				dma_len = data->ctx.tx_len;
+			} else if (data->ctx.tx_len == 0) {
+				dma_len = data->ctx.rx_len;
+			} else {
+				dma_len = MIN(data->ctx.tx_len, data->ctx.rx_len);
+			}
+
+			ret = spi_dma_move_buffers(dev, dma_len);
+		} else if (transfer_dir == LL_SPI_HALF_DUPLEX_TX) {
 			dma_len = data->ctx.tx_len;
-		} else if (data->ctx.tx_len == 0) {
-			dma_len = data->ctx.rx_len;
+			ret = spi_dma_move_tx_buffers(dev, dma_len);
 		} else {
-			dma_len = MIN(data->ctx.tx_len, data->ctx.rx_len);
+			dma_len = data->ctx.rx_len;
+			ret = spi_dma_move_rx_buffers(dev, dma_len);
 		}
 
-		data->status_flags = 0;
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
+		if (transfer_dir == LL_SPI_HALF_DUPLEX_RX &&
+			LL_SPI_GetMode(spi) == LL_SPI_MODE_MASTER) {
+			LL_SPI_StartMasterTransfer(spi);
+		}
+#endif /* st_stm32h7_spi */
 
-		ret = spi_dma_move_buffers(dev, dma_len);
 		if (ret != 0) {
 			break;
 		}
@@ -1048,8 +1242,14 @@ static int transceive_dma(const struct device *dev,
 #if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
 
 		/* toggle the DMA request to restart the transfer */
-		LL_SPI_EnableDMAReq_RX(spi);
-		LL_SPI_EnableDMAReq_TX(spi);
+		if (transfer_dir == LL_SPI_FULL_DUPLEX) {
+			LL_SPI_EnableDMAReq_RX(spi);
+			LL_SPI_EnableDMAReq_TX(spi);
+		} else if (transfer_dir == LL_SPI_HALF_DUPLEX_TX) {
+			LL_SPI_EnableDMAReq_TX(spi);
+		} else {
+			LL_SPI_EnableDMAReq_RX(spi);
+		}
 #endif /* ! st_stm32h7_spi */
 
 		ret = wait_dma_rx_tx_done(dev);
@@ -1081,8 +1281,38 @@ static int transceive_dma(const struct device *dev,
 		uint8_t frame_size_bytes = bits2bytes(
 			SPI_WORD_SIZE_GET(config->operation));
 
-		spi_context_update_tx(&data->ctx, frame_size_bytes, dma_len);
-		spi_context_update_rx(&data->ctx, frame_size_bytes, dma_len);
+		if (transfer_dir == LL_SPI_FULL_DUPLEX) {
+			spi_context_update_tx(&data->ctx, frame_size_bytes, dma_len);
+			spi_context_update_rx(&data->ctx, frame_size_bytes, dma_len);
+		} else if (transfer_dir == LL_SPI_HALF_DUPLEX_TX) {
+			spi_context_update_tx(&data->ctx, frame_size_bytes, dma_len);
+		} else {
+			spi_context_update_rx(&data->ctx, frame_size_bytes, dma_len);
+		}
+
+		if (transfer_dir == LL_SPI_HALF_DUPLEX_TX &&
+			!spi_context_tx_on(&data->ctx) &&
+			spi_context_rx_on(&data->ctx)) {
+			LL_SPI_Disable(spi);
+			LL_SPI_SetTransferDirection(spi, LL_SPI_HALF_DUPLEX_RX);
+
+			transfer_dir = LL_SPI_HALF_DUPLEX_RX;
+
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_spi)
+			int frames = spi_stm32_count_bufset_frames(config, rx_bufs);
+
+			if (frames < 0) {
+				ret = frames;
+				break;
+			}
+
+			LL_SPI_SetTransferSize(cfg->spi, frames);
+
+			LL_SPI_EnableDMAReq_RX(spi);
+#endif /* st_stm32h7_spi */
+
+			LL_SPI_Enable(spi);
+		}
 	}
 
 	/* spi complete relies on SPI Status Reg which cannot be disabled */
diff --git a/drivers/spi/spi_max32.c b/drivers/spi/spi_max32.c
index 1dd488cc3f9..1c2d66ede12 100644
--- a/drivers/spi/spi_max32.c
+++ b/drivers/spi/spi_max32.c
@@ -539,6 +539,8 @@ static int transceive_dma(const struct device *dev, const struct spi_config *con
 
 	spi_context_lock(ctx, async, cb, userdata, config);
 
+	MXC_SPI_ClearTXFIFO(spi);
+
 	ret = dma_get_status(cfg->tx_dma.dev, cfg->tx_dma.channel, &status);
 	if (ret < 0 || status.busy) {
 		ret = ret < 0 ? ret : -EBUSY;
@@ -568,13 +570,13 @@ static int transceive_dma(const struct device *dev, const struct spi_config *con
 	/* Assert the CS line if HW control disabled */
 	if (!hw_cs_ctrl) {
 		spi_context_cs_control(ctx, true);
+	} else {
+		spi->ctrl0 = (spi->ctrl0 & ~MXC_F_SPI_CTRL0_START) | MXC_F_SPI_CTRL0_SS_CTRL;
 	}
 
 	MXC_SPI_SetSlave(cfg->regs, ctx->config->slave);
 
 	do {
-		spi->ctrl0 &= ~(MXC_F_SPI_CTRL0_EN);
-
 		len = spi_context_max_continuous_chunk(ctx);
 		dfs_shift = spi_max32_get_dfs_shift(ctx);
 		word_count = len >> dfs_shift;
@@ -603,17 +605,24 @@ static int transceive_dma(const struct device *dev, const struct spi_config *con
 			goto unlock;
 		}
 
-		spi->ctrl0 |= MXC_F_SPI_CTRL0_EN;
-
 		data->dma_stat = 0;
 		MXC_SPI_StartTransmission(spi);
 		ret = spi_context_wait_for_completion(ctx);
 	} while (!ret && (spi_context_tx_on(ctx) || spi_context_rx_on(ctx)));
 
+	if (ret < 0) {
+		dma_stop(cfg->tx_dma.dev, cfg->tx_dma.channel);
+		dma_stop(cfg->rx_dma.dev, cfg->rx_dma.channel);
+	}
+
 unlock:
 	/* Deassert the CS line if hw control disabled */
 	if (!hw_cs_ctrl) {
 		spi_context_cs_control(ctx, false);
+	} else {
+		spi->ctrl0 &=
+			~(MXC_F_SPI_CTRL0_START | MXC_F_SPI_CTRL0_SS_CTRL | MXC_F_SPI_CTRL0_EN);
+		spi->ctrl0 |= MXC_F_SPI_CTRL0_EN;
 	}
 
 	spi_context_release(ctx, ret);
diff --git a/drivers/spi/spi_mcux_ecspi.c b/drivers/spi/spi_mcux_ecspi.c
index 778855ff019..8138e7fdc2a 100644
--- a/drivers/spi/spi_mcux_ecspi.c
+++ b/drivers/spi/spi_mcux_ecspi.c
@@ -93,7 +93,8 @@ static void spi_mcux_transfer_next_packet(const struct device *dev)
 		transfer.txData = NULL;
 	}
 
-	transfer.dataSize = data->dfs;
+	/* Burst length is set in the configure step */
+	transfer.dataSize = 1;
 
 	status = ECSPI_MasterTransferNonBlocking(base, &data->handle, &transfer);
 	if (status != kStatus_Success) {
@@ -163,7 +164,7 @@ static int spi_mcux_configure(const struct device *dev,
 		return -ENOTSUP;
 	}
 
-	if (spi_cfg->slave > kECSPI_Channel3) {
+	if (!spi_cs_is_gpio(spi_cfg) && spi_cfg->slave > kECSPI_Channel3) {
 		LOG_ERR("Slave %d is greater than %d", spi_cfg->slave, kECSPI_Channel3);
 		return -EINVAL;
 	}
@@ -181,7 +182,8 @@ static int spi_mcux_configure(const struct device *dev,
 
 	ECSPI_MasterGetDefaultConfig(&master_config);
 
-	master_config.channel = (ecspi_channel_source_t)spi_cfg->slave;
+	master_config.channel =
+		spi_cs_is_gpio(spi_cfg) ? kECSPI_Channel0 : (ecspi_channel_source_t)spi_cfg->slave;
 	master_config.channelConfig.polarity =
 		(SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL)
 		? kECSPI_PolarityActiveLow
diff --git a/drivers/spi/spi_mcux_flexio.c b/drivers/spi/spi_mcux_flexio.c
index 56a2c19fbf1..f15bd0871b7 100644
--- a/drivers/spi/spi_mcux_flexio.c
+++ b/drivers/spi/spi_mcux_flexio.c
@@ -102,11 +102,11 @@ static int spi_mcux_flexio_isr(void *user_data)
 	const struct spi_mcux_flexio_config *config = dev->config;
 	struct spi_mcux_flexio_data *data = dev->data;
 
-#if defined(CONFIG_SOC_SERIES_KE1XZ)
 	/* Wait until data transfer complete. */
-	WAIT_FOR((0U == (FLEXIO_SPI_GetStatusFlags(config->flexio_spi)
-		& (uint32_t)kFLEXIO_SPI_TxBufferEmptyFlag)), 100, NULL);
-#endif
+	WAIT_FOR((3U == (FLEXIO_SPI_GetStatusFlags(config->flexio_spi)
+		& (uint32_t)(kFLEXIO_SPI_TxBufferEmptyFlag | kFLEXIO_SPI_RxBufferFullFlag))),
+		100, NULL);
+
 	FLEXIO_SPI_MasterTransferHandleIRQ(config->flexio_spi, &data->handle);
 
 	return 0;
diff --git a/drivers/spi/spi_mcux_lpspi.c b/drivers/spi/spi_mcux_lpspi.c
deleted file mode 100644
index 6ac17c16f7c..00000000000
--- a/drivers/spi/spi_mcux_lpspi.c
+++ /dev/null
@@ -1,876 +0,0 @@
-/*
- * Copyright 2018, 2024 NXP
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DT_DRV_COMPAT nxp_lpspi
-
-#include <zephyr/drivers/spi.h>
-#include <zephyr/drivers/pinctrl.h>
-#include <zephyr/drivers/clock_control.h>
-#include <zephyr/irq.h>
-
-#include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(spi_mcux_lpspi, CONFIG_SPI_LOG_LEVEL);
-
-#ifdef CONFIG_SPI_RTIO
-#include <zephyr/drivers/spi/rtio.h>
-#endif
-
-#include "spi_context.h"
-
-#if CONFIG_NXP_LP_FLEXCOMM
-#include <zephyr/drivers/mfd/nxp_lp_flexcomm.h>
-#endif
-
-#include <fsl_lpspi.h>
-
-/* If any hardware revisions change this, make it into a DT property.
- * DONT'T make #ifdefs here by platform.
- */
-#define LPSPI_CHIP_SELECT_COUNT   4
-#define LPSPI_MIN_FRAME_SIZE_BITS 8
-
-/* Required by DEVICE_MMIO_NAMED_* macros */
-#define DEV_CFG(_dev)  ((const struct spi_mcux_config *)(_dev)->config)
-#define DEV_DATA(_dev) ((struct spi_mcux_data *)(_dev)->data)
-
-/* Argument to MCUX SDK IRQ handler */
-#define LPSPI_IRQ_HANDLE_ARG COND_CODE_1(CONFIG_NXP_LP_FLEXCOMM, (LPSPI_GetInstance(base)), (base))
-
-/* flag for SDK API for master transfers */
-#define LPSPI_MASTER_XFER_CFG_FLAGS(slave)                                                         \
-	kLPSPI_MasterPcsContinuous | (slave << LPSPI_MASTER_PCS_SHIFT)
-
-#ifdef CONFIG_SPI_MCUX_LPSPI_DMA
-#include <zephyr/drivers/dma.h>
-
-/* These flags are arbitrary */
-#define LPSPI_DMA_ERROR_FLAG   BIT(0)
-#define LPSPI_DMA_RX_DONE_FLAG BIT(1)
-#define LPSPI_DMA_TX_DONE_FLAG BIT(2)
-#define LPSPI_DMA_DONE_FLAG    (LPSPI_DMA_RX_DONE_FLAG | LPSPI_DMA_TX_DONE_FLAG)
-
-struct spi_dma_stream {
-	const struct device *dma_dev;
-	uint32_t channel; /* stores the channel for dma */
-	struct dma_config dma_cfg;
-	struct dma_block_config dma_blk_cfg;
-};
-#endif /* CONFIG_SPI_MCUX_LPSPI_DMA */
-
-struct spi_mcux_config {
-	DEVICE_MMIO_NAMED_ROM(reg_base);
-	const struct device *clock_dev;
-	clock_control_subsys_t clock_subsys;
-	void (*irq_config_func)(const struct device *dev);
-	uint32_t pcs_sck_delay;
-	uint32_t sck_pcs_delay;
-	uint32_t transfer_delay;
-	const struct pinctrl_dev_config *pincfg;
-	lpspi_pin_config_t data_pin_config;
-};
-
-struct spi_mcux_data {
-	DEVICE_MMIO_NAMED_RAM(reg_base);
-	const struct device *dev;
-	lpspi_master_handle_t handle;
-	struct spi_context ctx;
-	size_t transfer_len;
-#ifdef CONFIG_SPI_RTIO
-	struct spi_rtio *rtio_ctx;
-#endif
-#ifdef CONFIG_SPI_MCUX_LPSPI_DMA
-	volatile uint32_t status_flags;
-	struct spi_dma_stream dma_rx;
-	struct spi_dma_stream dma_tx;
-	/* dummy value used for transferring NOP when tx buf is null */
-	uint32_t dummy_buffer;
-#endif
-};
-
-static int spi_mcux_transfer_next_packet(const struct device *dev);
-
-static void spi_mcux_isr(const struct device *dev)
-{
-	struct spi_mcux_data *data = dev->data;
-	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
-
-	LPSPI_MasterTransferHandleIRQ(LPSPI_IRQ_HANDLE_ARG, &data->handle);
-}
-
-static void spi_mcux_master_callback(LPSPI_Type *base, lpspi_master_handle_t *handle,
-				     status_t status, void *userData)
-{
-	struct spi_mcux_data *data = userData;
-
-	spi_context_update_tx(&data->ctx, 1, data->transfer_len);
-	spi_context_update_rx(&data->ctx, 1, data->transfer_len);
-
-	spi_mcux_transfer_next_packet(data->dev);
-}
-
-static int spi_mcux_transfer_next_packet(const struct device *dev)
-{
-	struct spi_mcux_data *data = dev->data;
-	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
-	struct spi_context *ctx = &data->ctx;
-	size_t max_chunk = spi_context_max_continuous_chunk(ctx);
-	lpspi_transfer_t transfer;
-	status_t status;
-
-	if (max_chunk == 0) {
-		spi_context_cs_control(ctx, false);
-		spi_context_complete(ctx, dev, 0);
-		return 0;
-	}
-
-	data->transfer_len = max_chunk;
-
-	transfer.configFlags = LPSPI_MASTER_XFER_CFG_FLAGS(ctx->config->slave);
-	transfer.txData = (ctx->tx_len == 0 ? NULL : ctx->tx_buf);
-	transfer.rxData = (ctx->rx_len == 0 ? NULL : ctx->rx_buf);
-	transfer.dataSize = max_chunk;
-
-	status = LPSPI_MasterTransferNonBlocking(base, &data->handle, &transfer);
-	if (status != kStatus_Success) {
-		LOG_ERR("Transfer could not start on %s: %d", dev->name, status);
-		return status == kStatus_LPSPI_Busy ? -EBUSY : -EINVAL;
-	}
-
-	return 0;
-}
-
-static int spi_mcux_configure(const struct device *dev, const struct spi_config *spi_cfg)
-{
-	const struct spi_mcux_config *config = dev->config;
-	struct spi_mcux_data *data = dev->data;
-	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
-	uint32_t word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
-	lpspi_master_config_t master_config;
-	uint32_t clock_freq;
-	int ret;
-
-	if (spi_cfg->operation & SPI_HALF_DUPLEX) {
-		/* the IP DOES support half duplex, need to implement driver support */
-		LOG_ERR("Half-duplex not supported");
-		return -ENOTSUP;
-	}
-
-	if (word_size < 8 || (word_size % 32 == 1)) {
-		/* Zephyr word size == hardware FRAME size (not word size)
-		 * Max frame size: 4096 bits
-		 *   (zephyr field is 6 bit wide for max 64 bit size, no need to check)
-		 * Min frame size: 8 bits.
-		 * Minimum hardware word size is 2. Since this driver is intended to work
-		 * for 32 bit platforms, and 64 bits is max size, then only 33 and 1 are invalid.
-		 */
-		LOG_ERR("Word size %d not allowed", word_size);
-		return -EINVAL;
-	}
-
-	if (spi_cfg->slave > LPSPI_CHIP_SELECT_COUNT) {
-		LOG_ERR("Peripheral %d select exceeds max %d", spi_cfg->slave,
-			LPSPI_CHIP_SELECT_COUNT - 1);
-		return -EINVAL;
-	}
-
-	ret = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_freq);
-	if (ret) {
-		return ret;
-	}
-
-	if (data->ctx.config != NULL) {
-		/* Setting the baud rate in LPSPI_MasterInit requires module to be disabled. Only
-		 * disable if already configured, otherwise the clock is not enabled and the
-		 * CR register cannot be written.
-		 */
-		LPSPI_Enable(base, false);
-		while ((base->CR & LPSPI_CR_MEN_MASK) != 0U) {
-			/* Wait until LPSPI is disabled. Datasheet:
-			 * After writing 0, MEN (Module Enable) remains set until the LPSPI has
-			 * completed the current transfer and is idle.
-			 */
-		}
-	}
-
-	data->ctx.config = spi_cfg;
-
-	LPSPI_MasterGetDefaultConfig(&master_config);
-
-	master_config.bitsPerFrame = word_size;
-	master_config.cpol = (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL)
-				     ? kLPSPI_ClockPolarityActiveLow
-				     : kLPSPI_ClockPolarityActiveHigh;
-	master_config.cpha = (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA)
-				     ? kLPSPI_ClockPhaseSecondEdge
-				     : kLPSPI_ClockPhaseFirstEdge;
-	master_config.direction =
-		(spi_cfg->operation & SPI_TRANSFER_LSB) ? kLPSPI_LsbFirst : kLPSPI_MsbFirst;
-	master_config.baudRate = spi_cfg->frequency;
-	master_config.pcsToSckDelayInNanoSec = config->pcs_sck_delay;
-	master_config.lastSckToPcsDelayInNanoSec = config->sck_pcs_delay;
-	master_config.betweenTransferDelayInNanoSec = config->transfer_delay;
-	master_config.pinCfg = config->data_pin_config;
-
-	LPSPI_MasterInit(base, &master_config, clock_freq);
-	LPSPI_SetDummyData(base, 0);
-
-	if (IS_ENABLED(CONFIG_DEBUG)) {
-		base->CR |= LPSPI_CR_DBGEN_MASK;
-	}
-
-	return 0;
-}
-
-#ifdef CONFIG_SPI_MCUX_LPSPI_DMA
-static bool lpspi_inst_has_dma(const struct spi_mcux_data *data)
-{
-	return (data->dma_tx.dma_dev && data->dma_rx.dma_dev);
-}
-
-/* This function is executed in the interrupt context */
-static void spi_mcux_dma_callback(const struct device *dev, void *arg, uint32_t channel, int status)
-{
-	/* arg directly holds the spi device */
-	const struct device *spi_dev = arg;
-	struct spi_mcux_data *data = (struct spi_mcux_data *)spi_dev->data;
-	char debug_char;
-
-	if (status < 0) {
-		goto error;
-	}
-
-	/* identify the origin of this callback */
-	if (channel == data->dma_tx.channel) {
-		/* this part of the transfer ends */
-		data->status_flags |= LPSPI_DMA_TX_DONE_FLAG;
-		debug_char = 'T';
-	} else if (channel == data->dma_rx.channel) {
-		/* this part of the transfer ends */
-		data->status_flags |= LPSPI_DMA_RX_DONE_FLAG;
-		debug_char = 'R';
-	} else {
-		goto error;
-	}
-
-	LOG_DBG("DMA %cX Block Complete", debug_char);
-
-#if CONFIG_SPI_ASYNC
-	if (data->ctx.asynchronous && (data->status_flags & LPSPI_DMA_DONE_FLAG)) {
-		/* Load dma blocks of equal length */
-		size_t dma_size = spi_context_max_continuous_chunk(data->ctx);
-
-		if (dma_size != 0) {
-			return;
-		}
-
-		spi_context_update_tx(&data->ctx, 1, dma_size);
-		spi_context_update_rx(&data->ctx, 1, dma_size);
-	}
-#endif
-
-	goto done;
-error:
-	LOG_ERR("DMA callback error with channel %d.", channel);
-	data->status_flags |= LPSPI_DMA_ERROR_FLAG;
-done:
-	spi_context_complete(&data->ctx, spi_dev, 0);
-}
-
-static struct dma_block_config *spi_mcux_dma_common_load(struct spi_dma_stream *stream,
-							 const struct device *dev,
-							 const uint8_t *buf, size_t len)
-{
-	struct spi_mcux_data *data = dev->data;
-	struct dma_block_config *blk_cfg = &stream->dma_blk_cfg;
-
-	/* prepare the block for this TX DMA channel */
-	memset(blk_cfg, 0, sizeof(struct dma_block_config));
-
-	blk_cfg->block_size = len;
-
-	if (buf == NULL) {
-		blk_cfg->source_address = (uint32_t)&data->dummy_buffer;
-		blk_cfg->dest_address = (uint32_t)&data->dummy_buffer;
-		/* pretend it is peripheral xfer so DMA just xfer to dummy buf */
-		stream->dma_cfg.channel_direction = PERIPHERAL_TO_PERIPHERAL;
-	} else {
-		blk_cfg->source_address = (uint32_t)buf;
-		blk_cfg->dest_address = (uint32_t)buf;
-	}
-
-	/* Transfer 1 byte each DMA loop */
-	stream->dma_cfg.source_burst_length = 1;
-	stream->dma_cfg.user_data = (void *)dev;
-	stream->dma_cfg.head_block = blk_cfg;
-
-	return blk_cfg;
-}
-
-static int spi_mcux_dma_tx_load(const struct device *dev, const uint8_t *buf, size_t len)
-{
-	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
-	struct spi_mcux_data *data = dev->data;
-	/* remember active TX DMA channel (used in callback) */
-	struct spi_dma_stream *stream = &data->dma_tx;
-	struct dma_block_config *blk_cfg = spi_mcux_dma_common_load(stream, dev, buf, len);
-
-	if (buf != NULL) {
-		/* tx direction has memory as source and periph as dest. */
-		stream->dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
-	}
-
-	/* Dest is LPSPI tx fifo */
-	blk_cfg->dest_address = LPSPI_GetTxRegisterAddress(base);
-
-	/* give the client dev as arg, as the callback comes from the dma */
-	/* pass our client origin to the dma: data->dma_tx.dma_channel */
-	return dma_config(stream->dma_dev, stream->channel, &stream->dma_cfg);
-}
-
-static int spi_mcux_dma_rx_load(const struct device *dev, uint8_t *buf, size_t len)
-{
-	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
-	struct spi_mcux_data *data = dev->data;
-	/* retrieve active RX DMA channel (used in callback) */
-	struct spi_dma_stream *stream = &data->dma_rx;
-	struct dma_block_config *blk_cfg = spi_mcux_dma_common_load(stream, dev, buf, len);
-
-	if (buf != NULL) {
-		/* rx direction has periph as source and mem as dest. */
-		stream->dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
-	}
-
-	/* Source is LPSPI rx fifo */
-	blk_cfg->source_address = LPSPI_GetRxRegisterAddress(base);
-
-	/* pass our client origin to the dma: data->dma_rx.channel */
-	return dma_config(stream->dma_dev, stream->channel, &stream->dma_cfg);
-}
-
-static int wait_dma_rx_tx_done(const struct device *dev)
-{
-	struct spi_mcux_data *data = dev->data;
-	int ret;
-
-	do {
-		ret = spi_context_wait_for_completion(&data->ctx);
-		if (ret) {
-			LOG_DBG("Timed out waiting for SPI context to complete");
-			return ret;
-		} else if (data->status_flags & LPSPI_DMA_ERROR_FLAG) {
-			return -EIO;
-		}
-	} while (!((data->status_flags & LPSPI_DMA_DONE_FLAG) == LPSPI_DMA_DONE_FLAG));
-
-	LOG_DBG("DMA block completed");
-	return 0;
-}
-
-static inline int spi_mcux_dma_rxtx_load(const struct device *dev, size_t *dma_size)
-{
-	struct spi_mcux_data *data = dev->data;
-	struct spi_context *ctx = &data->ctx;
-	int ret = 0;
-
-	/* Clear status flags */
-	data->status_flags = 0U;
-
-	/* Load dma blocks of equal length */
-	*dma_size = spi_context_max_continuous_chunk(ctx);
-
-	ret = spi_mcux_dma_tx_load(dev, ctx->tx_buf, *dma_size);
-	if (ret != 0) {
-		return ret;
-	}
-
-	ret = spi_mcux_dma_rx_load(dev, ctx->rx_buf, *dma_size);
-	if (ret != 0) {
-		return ret;
-	}
-
-	/* Start DMA */
-	ret = dma_start(data->dma_tx.dma_dev, data->dma_tx.channel);
-	if (ret != 0) {
-		return ret;
-	}
-
-	ret = dma_start(data->dma_rx.dma_dev, data->dma_rx.channel);
-	return ret;
-}
-
-#ifdef CONFIG_SPI_ASYNC
-static int transceive_dma_async(const struct device *dev, spi_callback_t cb, void *userdata)
-{
-	struct spi_mcux_data *data = dev->data;
-	struct spi_context *ctx = &data->ctx;
-	size_t dma_size;
-	int ret;
-
-	ctx->asynchronous = true;
-	ctx->callback = cb;
-	ctx->callback_data = userdata;
-
-	ret = spi_mcux_dma_rxtx_load(dev, &dma_size);
-	if (ret) {
-		return ret;
-	}
-
-	/* Enable DMA Requests */
-	LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
-
-	return 0;
-}
-#else
-#define transceive_dma_async(...) 0
-#endif /* CONFIG_SPI_ASYNC */
-
-static int transceive_dma_sync(const struct device *dev)
-{
-	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
-	struct spi_mcux_data *data = dev->data;
-	struct spi_context *ctx = &data->ctx;
-	size_t dma_size;
-	int ret;
-
-	spi_context_cs_control(ctx, true);
-
-	/* Send each spi buf via DMA, updating context as DMA completes */
-	while (ctx->rx_len > 0 || ctx->tx_len > 0) {
-		/* Load dma block */
-		ret = spi_mcux_dma_rxtx_load(dev, &dma_size);
-		if (ret) {
-			return ret;
-		}
-
-#ifdef CONFIG_SOC_SERIES_MCXN
-		while (!(LPSPI_GetStatusFlags(base) & kLPSPI_TxDataRequestFlag)) {
-			/* wait until previous tx finished */
-		}
-#endif
-
-		/* Enable DMA Requests */
-		LPSPI_EnableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
-
-		/* Wait for DMA to finish */
-		ret = wait_dma_rx_tx_done(dev);
-		if (ret) {
-			return ret;
-		}
-
-#ifndef CONFIG_SOC_SERIES_MCXN
-		while ((LPSPI_GetStatusFlags(base) & kLPSPI_ModuleBusyFlag)) {
-			/* wait until module is idle */
-		}
-#endif
-
-		/* Disable DMA */
-		LPSPI_DisableDMA(base, kLPSPI_TxDmaEnable | kLPSPI_RxDmaEnable);
-
-		/* Update SPI contexts with amount of data we just sent */
-		spi_context_update_tx(ctx, 1, dma_size);
-		spi_context_update_rx(ctx, 1, dma_size);
-	}
-
-	spi_context_cs_control(ctx, false);
-
-	base->TCR = 0;
-
-	return 0;
-}
-
-static int transceive_dma(const struct device *dev, const struct spi_config *spi_cfg,
-			  const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs,
-			  bool asynchronous, spi_callback_t cb, void *userdata)
-{
-	struct spi_mcux_data *data = dev->data;
-	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
-	int ret;
-
-	if (!asynchronous) {
-		spi_context_lock(&data->ctx, asynchronous, cb, userdata, spi_cfg);
-	}
-
-	ret = spi_mcux_configure(dev, spi_cfg);
-	if (ret && !asynchronous) {
-		goto out;
-	} else if (ret) {
-		return ret;
-	}
-
-#ifdef CONFIG_SOC_SERIES_MCXN
-	base->TCR |= LPSPI_TCR_CONT_MASK;
-#endif
-
-	/* DMA is fast enough watermarks are not required */
-	LPSPI_SetFifoWatermarks(base, 0U, 0U);
-
-	spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
-
-	if (asynchronous) {
-		ret = transceive_dma_async(dev, cb, userdata);
-	} else {
-		ret = transceive_dma_sync(dev);
-	}
-
-out:
-	spi_context_release(&data->ctx, ret);
-	return ret;
-}
-#else
-#define lpspi_inst_has_dma(arg) arg != arg
-#define transceive_dma(...)     0
-#endif /* CONFIG_SPI_MCUX_LPSPI_DMA */
-
-#ifdef CONFIG_SPI_RTIO
-static void spi_mcux_iodev_complete(const struct device *dev, int status);
-
-static void spi_mcux_master_rtio_callback(LPSPI_Type *base, lpspi_master_handle_t *handle,
-					  status_t status, void *userData)
-{
-	struct spi_mcux_data *data = userData;
-	struct spi_rtio *rtio_ctx = data->rtio_ctx;
-
-	if (rtio_ctx->txn_head != NULL) {
-		spi_mcux_iodev_complete(data->dev, status);
-		return;
-	}
-
-	spi_mcux_master_callback(base, handle, status, userData);
-}
-
-static void spi_mcux_iodev_start(const struct device *dev)
-{
-	struct spi_mcux_data *data = dev->data;
-	struct spi_rtio *rtio_ctx = data->rtio_ctx;
-	struct rtio_sqe *sqe = &rtio_ctx->txn_curr->sqe;
-	struct spi_dt_spec *spi_dt_spec = sqe->iodev->data;
-	struct spi_config *spi_cfg = &spi_dt_spec->config;
-	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
-	lpspi_transfer_t transfer;
-	status_t status;
-
-	status = spi_mcux_configure(dev, spi_cfg);
-	if (status) {
-		LOG_ERR("Error configuring lpspi");
-		return;
-	}
-
-	LPSPI_MasterTransferCreateHandle(base, &data->handle, spi_mcux_master_rtio_callback, data);
-
-	transfer.configFlags = LPSPI_MASTER_XFER_CFG_FLAGS(spi_cfg->slave);
-
-	switch (sqe->op) {
-	case RTIO_OP_RX:
-		transfer.txData = NULL;
-		transfer.rxData = sqe->rx.buf;
-		transfer.dataSize = sqe->rx.buf_len;
-		break;
-	case RTIO_OP_TX:
-		transfer.rxData = NULL;
-		transfer.txData = sqe->tx.buf;
-		transfer.dataSize = sqe->tx.buf_len;
-		break;
-	case RTIO_OP_TINY_TX:
-		transfer.rxData = NULL;
-		transfer.txData = sqe->tiny_tx.buf;
-		transfer.dataSize = sqe->tiny_tx.buf_len;
-		break;
-	case RTIO_OP_TXRX:
-		transfer.txData = sqe->txrx.tx_buf;
-		transfer.rxData = sqe->txrx.rx_buf;
-		transfer.dataSize = sqe->txrx.buf_len;
-		break;
-	default:
-		LOG_ERR("Invalid op code %d for submission %p\n", sqe->op, (void *)sqe);
-		spi_mcux_iodev_complete(dev, -EINVAL);
-		return;
-	}
-
-	data->transfer_len = transfer.dataSize;
-
-	spi_context_cs_control(&data->ctx, true);
-
-	status = LPSPI_MasterTransferNonBlocking(base, &data->handle, &transfer);
-	if (status != kStatus_Success) {
-		LOG_ERR("Transfer could not start on %s: %d", dev->name, status);
-		spi_mcux_iodev_complete(dev, -EIO);
-	}
-}
-
-static void spi_mcux_iodev_complete(const struct device *dev, int status)
-{
-	struct spi_mcux_data *data = dev->data;
-	struct spi_rtio *rtio_ctx = data->rtio_ctx;
-
-	if (!status && rtio_ctx->txn_curr->sqe.flags & RTIO_SQE_TRANSACTION) {
-		rtio_ctx->txn_curr = rtio_txn_next(rtio_ctx->txn_curr);
-		spi_mcux_iodev_start(dev);
-		return;
-	}
-
-	/** De-assert CS-line to space from next transaction */
-	spi_context_cs_control(&data->ctx, false);
-
-	if (spi_rtio_complete(rtio_ctx, status)) {
-		spi_mcux_iodev_start(dev);
-	}
-}
-
-static void spi_mcux_iodev_submit(const struct device *dev, struct rtio_iodev_sqe *iodev_sqe)
-{
-	struct spi_mcux_data *data = dev->data;
-	struct spi_rtio *rtio_ctx = data->rtio_ctx;
-
-	if (spi_rtio_submit(rtio_ctx, iodev_sqe)) {
-		spi_mcux_iodev_start(dev);
-	}
-}
-
-static inline int transceive_rtio(const struct device *dev, const struct spi_config *spi_cfg,
-				  const struct spi_buf_set *tx_bufs,
-				  const struct spi_buf_set *rx_bufs)
-{
-	struct spi_mcux_data *data = dev->data;
-	struct spi_rtio *rtio_ctx = data->rtio_ctx;
-	int ret;
-
-	spi_context_lock(&data->ctx, false, NULL, NULL, spi_cfg);
-
-	ret = spi_rtio_transceive(rtio_ctx, spi_cfg, tx_bufs, rx_bufs);
-
-	spi_context_release(&data->ctx, ret);
-
-	return ret;
-}
-#else
-#define transceive_rtio(...) 0
-#endif /* CONFIG_SPI_RTIO */
-
-static int transceive(const struct device *dev, const struct spi_config *spi_cfg,
-		      const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs,
-		      bool asynchronous, spi_callback_t cb, void *userdata)
-{
-	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
-	struct spi_mcux_data *data = dev->data;
-	int ret;
-
-	spi_context_lock(&data->ctx, asynchronous, cb, userdata, spi_cfg);
-
-	ret = spi_mcux_configure(dev, spi_cfg);
-	if (ret) {
-		goto out;
-	}
-
-	LPSPI_MasterTransferCreateHandle(base, &data->handle, spi_mcux_master_callback, data);
-
-	spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
-
-	spi_context_cs_control(&data->ctx, true);
-
-	ret = spi_mcux_transfer_next_packet(dev);
-	if (ret) {
-		goto out;
-	}
-
-	ret = spi_context_wait_for_completion(&data->ctx);
-out:
-	spi_context_release(&data->ctx, ret);
-
-	return ret;
-}
-
-static int spi_mcux_transceive(const struct device *dev, const struct spi_config *spi_cfg,
-			       const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs,
-			       spi_callback_t cb, void *userdata, bool async)
-{
-	struct spi_mcux_data *data = dev->data;
-
-	if (lpspi_inst_has_dma(data)) {
-		return transceive_dma(dev, spi_cfg, tx_bufs, rx_bufs, async, cb, userdata);
-	}
-
-	if (IS_ENABLED(CONFIG_SPI_RTIO)) {
-		return transceive_rtio(dev, spi_cfg, tx_bufs, rx_bufs);
-	}
-
-	return transceive(dev, spi_cfg, tx_bufs, rx_bufs, async, cb, userdata);
-}
-
-static int spi_mcux_transceive_sync(const struct device *dev, const struct spi_config *spi_cfg,
-				    const struct spi_buf_set *tx_bufs,
-				    const struct spi_buf_set *rx_bufs)
-{
-	return spi_mcux_transceive(dev, spi_cfg, tx_bufs, rx_bufs, NULL, NULL, false);
-}
-
-#ifdef CONFIG_SPI_ASYNC
-static int spi_mcux_transceive_async(const struct device *dev, const struct spi_config *spi_cfg,
-				     const struct spi_buf_set *tx_bufs,
-				     const struct spi_buf_set *rx_bufs, spi_callback_t cb,
-				     void *userdata)
-{
-	return spi_mcux_transceive(dev, spi_cfg, tx_bufs, rx_bufs, cb, userdata, true);
-}
-#endif /* CONFIG_SPI_ASYNC */
-
-static int spi_mcux_release(const struct device *dev, const struct spi_config *spi_cfg)
-{
-	struct spi_mcux_data *data = dev->data;
-
-	spi_context_unlock_unconditionally(&data->ctx);
-
-	return 0;
-}
-
-static DEVICE_API(spi, spi_mcux_driver_api) = {
-	.transceive = spi_mcux_transceive_sync,
-#ifdef CONFIG_SPI_ASYNC
-	.transceive_async = spi_mcux_transceive_async,
-#endif
-#ifdef CONFIG_SPI_RTIO
-	.iodev_submit = spi_mcux_iodev_submit,
-#endif
-	.release = spi_mcux_release,
-};
-
-#if defined(CONFIG_SPI_MCUX_LPSPI_DMA)
-static int lpspi_dma_dev_ready(const struct device *dma_dev)
-{
-	if (!device_is_ready(dma_dev)) {
-		LOG_ERR("%s device is not ready", dma_dev->name);
-		return -ENODEV;
-	}
-
-	return 0;
-}
-
-static int lpspi_dma_devs_ready(struct spi_mcux_data *data)
-{
-	return lpspi_dma_dev_ready(data->dma_tx.dma_dev) |
-	       lpspi_dma_dev_ready(data->dma_rx.dma_dev);
-}
-#else
-#define lpspi_dma_devs_ready(...) 0
-#endif /* CONFIG_SPI_MCUX_LPSPI_DMA */
-
-static int spi_mcux_init(const struct device *dev)
-{
-	const struct spi_mcux_config *config = dev->config;
-	struct spi_mcux_data *data = dev->data;
-	int err = 0;
-
-	DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP);
-
-	data->dev = dev;
-
-	if (!device_is_ready(config->clock_dev)) {
-		LOG_ERR("clock control device not ready");
-		return -ENODEV;
-	}
-
-	if (IS_ENABLED(CONFIG_SPI_MCUX_LPSPI_DMA) && lpspi_inst_has_dma(data)) {
-		err = lpspi_dma_devs_ready(data);
-	}
-	if (err < 0) {
-		return err;
-	}
-
-	err = spi_context_cs_configure_all(&data->ctx);
-	if (err < 0) {
-		return err;
-	}
-
-	err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
-	if (err) {
-		return err;
-	}
-
-	config->irq_config_func(dev);
-
-#ifdef CONFIG_SPI_RTIO
-	spi_rtio_init(data->rtio_ctx, dev);
-#endif
-	spi_context_unlock_unconditionally(&data->ctx);
-
-	return 0;
-}
-
-#define SPI_MCUX_RTIO_DEFINE(n)                                                                    \
-	SPI_RTIO_DEFINE(spi_mcux_rtio_##n, CONFIG_SPI_MCUX_RTIO_SQ_SIZE,                           \
-			CONFIG_SPI_MCUX_RTIO_SQ_SIZE)
-
-#ifdef CONFIG_SPI_MCUX_LPSPI_DMA
-#define SPI_DMA_CHANNELS(n)                                                                        \
-	IF_ENABLED(                                                                                \
-		DT_INST_DMAS_HAS_NAME(n, tx),                                                      \
-		(.dma_tx = {.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, tx)),            \
-			    .channel = DT_INST_DMAS_CELL_BY_NAME(n, tx, mux),                      \
-			    .dma_cfg = {.channel_direction = MEMORY_TO_PERIPHERAL,                 \
-					.dma_callback = spi_mcux_dma_callback,                     \
-					.source_data_size = 1,                                     \
-					.dest_data_size = 1,                                       \
-					.block_count = 1,                                          \
-					.dma_slot = DT_INST_DMAS_CELL_BY_NAME(n, tx, source)}},))  \
-	IF_ENABLED(                                                                                \
-		DT_INST_DMAS_HAS_NAME(n, rx),                                                      \
-		(.dma_rx = {.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, rx)),            \
-			    .channel = DT_INST_DMAS_CELL_BY_NAME(n, rx, mux),                      \
-			    .dma_cfg = {.channel_direction = PERIPHERAL_TO_MEMORY,                 \
-					.dma_callback = spi_mcux_dma_callback,                     \
-					.source_data_size = 1,                                     \
-					.dest_data_size = 1,                                       \
-					.block_count = 1,                                          \
-					.dma_slot = DT_INST_DMAS_CELL_BY_NAME(n, rx, source)}},))
-#else
-#define SPI_DMA_CHANNELS(n)
-#endif /* CONFIG_SPI_MCUX_LPSPI_DMA */
-
-#if defined(CONFIG_NXP_LP_FLEXCOMM)
-#define SPI_MCUX_LPSPI_IRQ_FUNC(n)                                                                 \
-	nxp_lp_flexcomm_setirqhandler(DEVICE_DT_GET(DT_INST_PARENT(n)), DEVICE_DT_INST_GET(n),     \
-				      LP_FLEXCOMM_PERIPH_LPSPI, spi_mcux_isr);
-#else
-#define SPI_MCUX_LPSPI_IRQ_FUNC(n)                                                                 \
-	IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), spi_mcux_isr,                       \
-		    DEVICE_DT_INST_GET(n), 0);                                                     \
-	irq_enable(DT_INST_IRQN(n));
-#endif
-
-#define SPI_MCUX_LPSPI_INIT(n)                                                                     \
-	PINCTRL_DT_INST_DEFINE(n);                                                                 \
-	COND_CODE_1(CONFIG_SPI_RTIO, (SPI_MCUX_RTIO_DEFINE(n)), ());                               \
-                                                                                                   \
-	static void spi_mcux_config_func_##n(const struct device *dev)                             \
-	{                                                                                          \
-		SPI_MCUX_LPSPI_IRQ_FUNC(n)                                                         \
-	}                                                                                          \
-                                                                                                   \
-	static const struct spi_mcux_config spi_mcux_config_##n = {                                \
-		DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)),                              \
-		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),                                \
-		.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),              \
-		.irq_config_func = spi_mcux_config_func_##n,                                       \
-		.pcs_sck_delay = UTIL_AND(DT_INST_NODE_HAS_PROP(n, pcs_sck_delay),                 \
-					  DT_INST_PROP(n, pcs_sck_delay)),                         \
-		.sck_pcs_delay = UTIL_AND(DT_INST_NODE_HAS_PROP(n, sck_pcs_delay),                 \
-					  DT_INST_PROP(n, sck_pcs_delay)),                         \
-		.transfer_delay = UTIL_AND(DT_INST_NODE_HAS_PROP(n, transfer_delay),               \
-					   DT_INST_PROP(n, transfer_delay)),                       \
-		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                       \
-		.data_pin_config = DT_INST_ENUM_IDX(n, data_pin_config),                           \
-	};                                                                                         \
-                                                                                                   \
-	static struct spi_mcux_data spi_mcux_data_##n = {                                          \
-		SPI_CONTEXT_INIT_LOCK(spi_mcux_data_##n, ctx),                                     \
-		SPI_CONTEXT_INIT_SYNC(spi_mcux_data_##n, ctx),                                     \
-		SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx) SPI_DMA_CHANNELS(n)           \
-			IF_ENABLED(CONFIG_SPI_RTIO, (.rtio_ctx = &spi_mcux_rtio_##n,))             \
-	};                                                                                         \
-                                                                                                   \
-	SPI_DEVICE_DT_INST_DEFINE(n, spi_mcux_init, NULL, &spi_mcux_data_##n, &spi_mcux_config_##n,\
-			      POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, &spi_mcux_driver_api);
-
-DT_INST_FOREACH_STATUS_OKAY(SPI_MCUX_LPSPI_INIT)
diff --git a/drivers/spi/spi_nrfx_spi.c b/drivers/spi/spi_nrfx_spi.c
index 2151cd9e2bf..e0aeb668029 100644
--- a/drivers/spi/spi_nrfx_spi.c
+++ b/drivers/spi/spi_nrfx_spi.c
@@ -92,6 +92,7 @@ static int configure(const struct device *dev,
 	struct spi_context *ctx = &dev_data->ctx;
 	nrfx_spi_config_t config;
 	nrfx_err_t result;
+	uint32_t sck_pin;
 
 	if (dev_data->initialized && spi_context_configured(ctx, spi_cfg)) {
 		/* Already configured. No need to do it again. */
@@ -135,8 +136,11 @@ static int configure(const struct device *dev,
 	config.mode      = get_nrf_spi_mode(spi_cfg->operation);
 	config.bit_order = get_nrf_spi_bit_order(spi_cfg->operation);
 
-	nrf_gpio_pin_write(nrf_spi_sck_pin_get(dev_config->spi.p_reg),
-			   spi_cfg->operation & SPI_MODE_CPOL ? 1 : 0);
+	sck_pin = nrf_spi_sck_pin_get(dev_config->spi.p_reg);
+
+	if (sck_pin != NRF_SPI_PIN_NOT_CONNECTED) {
+		nrf_gpio_pin_write(sck_pin, spi_cfg->operation & SPI_MODE_CPOL ? 1 : 0);
+	}
 
 	if (dev_data->initialized) {
 		nrfx_spi_uninit(&dev_config->spi);
diff --git a/drivers/spi/spi_nrfx_spim.c b/drivers/spi/spi_nrfx_spim.c
index 7e688a5fa6a..20456b2a247 100644
--- a/drivers/spi/spi_nrfx_spim.c
+++ b/drivers/spi/spi_nrfx_spim.c
@@ -227,6 +227,7 @@ static int configure(const struct device *dev,
 	uint32_t max_freq = dev_config->max_freq;
 	nrfx_spim_config_t config;
 	nrfx_err_t result;
+	uint32_t sck_pin;
 
 	if (dev_data->initialized && spi_context_configured(ctx, spi_cfg)) {
 		/* Already configured. No need to do it again. */
@@ -283,8 +284,11 @@ static int configure(const struct device *dev,
 	config.mode      = get_nrf_spim_mode(spi_cfg->operation);
 	config.bit_order = get_nrf_spim_bit_order(spi_cfg->operation);
 
-	nrfy_gpio_pin_write(nrfy_spim_sck_pin_get(dev_config->spim.p_reg),
-			    spi_cfg->operation & SPI_MODE_CPOL ? 1 : 0);
+	sck_pin = nrfy_spim_sck_pin_get(dev_config->spim.p_reg);
+
+	if (sck_pin != NRF_SPIM_PIN_NOT_CONNECTED) {
+		nrfy_gpio_pin_write(sck_pin, spi_cfg->operation & SPI_MODE_CPOL ? 1 : 0);
+	}
 
 	if (dev_data->initialized) {
 		nrfx_spim_uninit(&dev_config->spim);
diff --git a/drivers/spi/spi_nxp_lpspi/CMakeLists.txt b/drivers/spi/spi_nxp_lpspi/CMakeLists.txt
new file mode 100644
index 00000000000..a494fd06153
--- /dev/null
+++ b/drivers/spi/spi_nxp_lpspi/CMakeLists.txt
@@ -0,0 +1,5 @@
+# Copyright 2024 NXP
+
+zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_LPSPI spi_nxp_lpspi_common.c)
+zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_LPSPI_CPU spi_nxp_lpspi.c)
+zephyr_library_sources_ifdef(CONFIG_SPI_MCUX_LPSPI_DMA spi_nxp_lpspi_dma.c)
diff --git a/drivers/spi/spi_nxp_lpspi/Kconfig b/drivers/spi/spi_nxp_lpspi/Kconfig
new file mode 100644
index 00000000000..aabb4d51ce7
--- /dev/null
+++ b/drivers/spi/spi_nxp_lpspi/Kconfig
@@ -0,0 +1,39 @@
+# Copyright 2018, 2024-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SPI_MCUX_LPSPI
+	bool "NXP LPSPI peripheral"
+	default y
+	depends on DT_HAS_NXP_LPSPI_ENABLED
+	depends on CLOCK_CONTROL
+	select PINCTRL
+	help
+	  Enable driver support for NXP LPSPI.
+
+if SPI_MCUX_LPSPI
+
+config SPI_MCUX_LPSPI_DMA
+	bool "NXP LPSPI DMA-based Driver"
+	default y
+	select DMA
+	depends on $(dt_compat_any_has_prop,$(DT_COMPAT_NXP_LPSPI),dmas)
+	help
+	  Enable DMA-based transfers for LPSPI peripherals
+	  that have a dmas property specified in their DT node.
+	  The DMA based driver prioritizes bandwidth over latency, due to
+	  DMA being more efficient for larger data transfers, to avoid CPU
+	  having to be utilized to do the work. However, setting up a DMA
+	  transfer is more complicated setup than just starting the transfer
+	  immediately with CPU, so there could be more latency between
+	  the point of requesting a transfer and when it actually starts.
+
+config SPI_MCUX_LPSPI_CPU
+	bool "NXP LPSPI CPU-based driver"
+	default y
+	depends on $(dt_compat_any_not_has_prop,$(DT_COMPAT_NXP_LPSPI),dmas) || !SPI_MCUX_LPSPI_DMA
+	help
+	  Enable "normal" CPU based SPI driver for LPSPI.
+	  This has lower latency than DMA-based driver but over the
+	  longer transfers will likely have less bandwidth and use more CPU time.
+
+endif # SPI_MCUX_LPSPI
diff --git a/drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi.c b/drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi.c
new file mode 100644
index 00000000000..05a7c6cf382
--- /dev/null
+++ b/drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi.c
@@ -0,0 +1,421 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_lpspi
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(spi_lpspi, CONFIG_SPI_LOG_LEVEL);
+
+#include "spi_nxp_lpspi_priv.h"
+
+struct lpspi_driver_data {
+	size_t fill_len;
+	uint8_t word_size_bytes;
+};
+
+static inline uint8_t rx_fifo_cur_len(LPSPI_Type *base)
+{
+	return (base->FSR & LPSPI_FSR_RXCOUNT_MASK) >> LPSPI_FSR_RXCOUNT_SHIFT;
+}
+
+static inline uint8_t tx_fifo_cur_len(LPSPI_Type *base)
+{
+	return (base->FSR & LPSPI_FSR_TXCOUNT_MASK) >> LPSPI_FSR_TXCOUNT_SHIFT;
+}
+
+/* Reads a word from the RX fifo and handles writing it into the RX spi buf */
+static inline void lpspi_rx_word_write_bytes(const struct device *dev, size_t offset)
+{
+	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
+	struct lpspi_data *data = dev->data;
+	struct lpspi_driver_data *lpspi_data = (struct lpspi_driver_data *)data->driver_data;
+	struct spi_context *ctx = &data->ctx;
+	uint8_t num_bytes = lpspi_data->word_size_bytes;
+	uint8_t *buf = ctx->rx_buf + offset;
+	uint32_t word = base->RDR;
+
+	if (!spi_context_rx_buf_on(ctx) && spi_context_rx_on(ctx)) {
+		/* receive no actual data if rx buf is NULL */
+		return;
+	}
+
+	for (uint8_t i = 0; i < num_bytes; i++) {
+		buf[i] = (uint8_t)(word >> (BITS_PER_BYTE * i));
+	}
+}
+
+/* Reads a maximum number of words from RX fifo and writes them to the remainder of the RX buf */
+static inline size_t lpspi_rx_buf_write_words(const struct device *dev, uint8_t max_read)
+{
+	struct lpspi_data *data = dev->data;
+	struct lpspi_driver_data *lpspi_data = (struct lpspi_driver_data *)data->driver_data;
+	struct spi_context *ctx = &data->ctx;
+	size_t buf_len = ctx->rx_len;
+	uint8_t words_read = 0;
+	size_t offset = 0;
+
+	while (buf_len-- > 0 && max_read-- > 0) {
+		lpspi_rx_word_write_bytes(dev, offset);
+		offset += lpspi_data->word_size_bytes;
+		words_read++;
+	}
+
+	return words_read;
+}
+
+static inline void lpspi_handle_rx_irq(const struct device *dev)
+{
+	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
+	struct lpspi_data *data = dev->data;
+	struct lpspi_driver_data *lpspi_data = (struct lpspi_driver_data *)data->driver_data;
+	struct spi_context *ctx = &data->ctx;
+	uint8_t rx_fsr = rx_fifo_cur_len(base);
+	uint8_t total_words_written = 0;
+	uint8_t total_words_read = 0;
+	uint8_t words_read;
+
+	base->SR = LPSPI_SR_RDF_MASK;
+
+	LOG_DBG("RX FIFO: %d, RX BUF: %p", rx_fsr, ctx->rx_buf);
+
+	while ((rx_fsr = rx_fifo_cur_len(base)) > 0 && spi_context_rx_on(ctx)) {
+		words_read = lpspi_rx_buf_write_words(dev, rx_fsr);
+		total_words_read += words_read;
+		total_words_written += (spi_context_rx_buf_on(ctx) ? words_read : 0);
+		spi_context_update_rx(ctx, lpspi_data->word_size_bytes, words_read);
+	}
+
+	LOG_DBG("RX done %d words to spi buf", total_words_written);
+
+	if (spi_context_rx_len_left(ctx) == 0) {
+		base->IER &= ~LPSPI_IER_RDIE_MASK;
+		base->CR |= LPSPI_CR_RRF_MASK; /* flush rx fifo */
+	}
+}
+
+/* constructs the next word from the buffer */
+static inline uint32_t lpspi_next_tx_word(const struct device *dev, const uint8_t *buf,
+					  int offset, size_t max_bytes)
+{
+	const uint8_t *byte = buf + offset;
+	uint32_t next_word = 0;
+
+	for (uint8_t i = 0; i < max_bytes; i++) {
+		next_word |= byte[i] << (BITS_PER_BYTE * i);
+	}
+
+	return next_word;
+}
+
+/* fills the TX fifo with specified amount of data from the specified buffer */
+static inline void lpspi_fill_tx_fifo(const struct device *dev, const uint8_t *buf,
+				      size_t buf_len, size_t fill_len)
+{
+	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
+	struct lpspi_data *data = dev->data;
+	struct lpspi_driver_data *lpspi_data = (struct lpspi_driver_data *)data->driver_data;
+	uint8_t word_size = lpspi_data->word_size_bytes;
+	size_t buf_remaining_bytes = buf_len * word_size;
+	size_t offset = 0;
+	uint32_t next_word;
+	uint32_t next_word_bytes;
+
+	for (int word_count = 0; word_count < fill_len; word_count++) {
+		next_word_bytes = MIN(word_size, buf_remaining_bytes);
+		next_word = lpspi_next_tx_word(dev, buf, offset, next_word_bytes);
+		base->TDR = next_word;
+		offset += word_size;
+		buf_remaining_bytes -= word_size;
+	}
+
+	LOG_DBG("Filled TX FIFO to %d words (%d bytes)", lpspi_data->fill_len, offset);
+}
+
+/* just fills TX fifo with the specified amount of NOPS */
+static void lpspi_fill_tx_fifo_nop(const struct device *dev, size_t fill_len)
+{
+	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
+
+	for (int i = 0; i < fill_len; i++) {
+		base->TDR = 0;
+	}
+
+	LOG_DBG("Filled TX fifo with %d NOPs", fill_len);
+}
+
+/* handles refilling the TX fifo from empty */
+static void lpspi_next_tx_fill(const struct device *dev)
+{
+	const struct lpspi_config *config = dev->config;
+	struct lpspi_data *data = dev->data;
+	struct lpspi_driver_data *lpspi_data = (struct lpspi_driver_data *)data->driver_data;
+	struct spi_context *ctx = &data->ctx;
+	size_t fill_len;
+	size_t actual_filled = 0;
+
+	fill_len = MIN(ctx->tx_len, config->tx_fifo_size);
+
+	const struct spi_buf *current_buf = ctx->current_tx;
+	const uint8_t *cur_buf_pos = ctx->tx_buf;
+	size_t cur_buf_len_left = ctx->tx_len;
+	size_t bufs_left = ctx->tx_count;
+
+	while (fill_len > 0) {
+		size_t next_buf_fill = MIN(cur_buf_len_left, fill_len);
+
+		if (cur_buf_pos == NULL) {
+			lpspi_fill_tx_fifo_nop(dev, next_buf_fill);
+		} else {
+			lpspi_fill_tx_fifo(dev, cur_buf_pos,
+						current_buf->len, next_buf_fill);
+		}
+
+		fill_len -= next_buf_fill;
+		cur_buf_pos += next_buf_fill;
+
+		/* in the case where we just filled as much as we could from the current buffer,
+		 * this logic while wrong should have no effect, since fill_len will be 0,
+		 * so I choose not to make the code extra complex
+		 */
+		bufs_left--;
+		if (bufs_left > 0) {
+			current_buf += 1;
+			cur_buf_len_left = current_buf->len;
+			cur_buf_pos = current_buf->buf;
+		} else {
+			fill_len = 0;
+		}
+
+		actual_filled += next_buf_fill;
+	}
+
+	lpspi_data->fill_len = actual_filled;
+}
+
+static inline void lpspi_handle_tx_irq(const struct device *dev)
+{
+	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
+	struct lpspi_data *data = dev->data;
+	struct lpspi_driver_data *lpspi_data = (struct lpspi_driver_data *)data->driver_data;
+	struct spi_context *ctx = &data->ctx;
+
+	while (spi_context_tx_on(ctx) && lpspi_data->fill_len > 0) {
+		size_t this_buf_words_sent = MIN(lpspi_data->fill_len, ctx->tx_len);
+
+		spi_context_update_tx(ctx, lpspi_data->word_size_bytes, this_buf_words_sent);
+		lpspi_data->fill_len -= this_buf_words_sent;
+	}
+
+	base->SR = LPSPI_SR_TDF_MASK;
+
+	if (!spi_context_tx_on(ctx)) {
+		base->IER &= ~LPSPI_IER_TDIE_MASK;
+		return;
+	}
+
+	lpspi_next_tx_fill(data->dev);
+}
+
+static inline void lpspi_end_xfer(const struct device *dev)
+{
+	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
+	const struct lpspi_config *config = dev->config;
+	struct lpspi_data *data = dev->data;
+	struct spi_context *ctx = &data->ctx;
+
+	spi_context_complete(ctx, dev, 0);
+	NVIC_ClearPendingIRQ(config->irqn);
+	if (!(ctx->config->operation & SPI_HOLD_ON_CS)) {
+		base->TCR &= ~(LPSPI_TCR_CONT_MASK | LPSPI_TCR_CONTC_MASK);
+	}
+	lpspi_wait_tx_fifo_empty(dev);
+	spi_context_cs_control(ctx, false);
+	spi_context_release(&data->ctx, 0);
+}
+
+static void lpspi_isr(const struct device *dev)
+{
+	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
+	const struct lpspi_config *config = dev->config;
+	struct lpspi_data *data = dev->data;
+	struct lpspi_driver_data *lpspi_data = (struct lpspi_driver_data *)data->driver_data;
+	struct spi_context *ctx = &data->ctx;
+	uint32_t status_flags = base->SR;
+
+	if (status_flags & LPSPI_SR_RDF_MASK) {
+		lpspi_handle_rx_irq(dev);
+	}
+
+	if (status_flags & LPSPI_SR_TDF_MASK) {
+		lpspi_handle_tx_irq(dev);
+	}
+
+	if (spi_context_tx_on(ctx)) {
+		return;
+	}
+
+	if (spi_context_rx_on(ctx)) {
+		size_t rx_fifo_len = rx_fifo_cur_len(base);
+		size_t expected_rx_left = rx_fifo_len < ctx->rx_len ? ctx->rx_len - rx_fifo_len : 0;
+		size_t max_fill = MIN(expected_rx_left, config->rx_fifo_size);
+		size_t tx_current_fifo_len = tx_fifo_cur_len(base);
+
+		size_t fill_len = tx_current_fifo_len < ctx->rx_len ?
+					max_fill - tx_current_fifo_len : 0;
+
+		lpspi_fill_tx_fifo_nop(dev, fill_len);
+		lpspi_data->fill_len = fill_len;
+	}
+
+	if (spi_context_rx_len_left(ctx) == 1 && (LPSPI_VERID_MAJOR(base->VERID) < 2)) {
+		/* Due to stalling behavior on older LPSPI,
+		 * need to end xfer in order to get last bit clocked out on bus.
+		 */
+		base->TCR |= LPSPI_TCR_CONT_MASK;
+	} else if (spi_context_rx_len_left(ctx) == 0) {
+		lpspi_end_xfer(dev);
+	}
+}
+
+static int transceive(const struct device *dev, const struct spi_config *spi_cfg,
+		      const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs,
+		      bool asynchronous, spi_callback_t cb, void *userdata)
+{
+	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
+	struct lpspi_data *data = dev->data;
+	struct lpspi_driver_data *lpspi_data = (struct lpspi_driver_data *)data->driver_data;
+	struct spi_context *ctx = &data->ctx;
+	int ret = 0;
+
+	spi_context_lock(&data->ctx, asynchronous, cb, userdata, spi_cfg);
+
+	lpspi_data->word_size_bytes =
+		DIV_ROUND_UP(SPI_WORD_SIZE_GET(spi_cfg->operation), BITS_PER_BYTE);
+	if (lpspi_data->word_size_bytes > 4) {
+		LOG_ERR("Maximum 4 byte word size");
+		ret = -EINVAL;
+		goto error;
+	}
+
+	spi_context_buffers_setup(ctx, tx_bufs, rx_bufs, lpspi_data->word_size_bytes);
+
+	ret = spi_mcux_configure(dev, spi_cfg);
+	if (ret) {
+		goto error;
+	}
+
+	base->CR |= LPSPI_CR_RTF_MASK | LPSPI_CR_RRF_MASK; /* flush fifos */
+	base->IER = 0;                                     /* disable all interrupts */
+	base->FCR = 0;                                     /* set watermarks to 0 */
+	base->SR |= LPSPI_INTERRUPT_BITS;
+
+	LOG_DBG("Starting LPSPI transfer");
+	spi_context_cs_control(ctx, true);
+
+	base->CR |= LPSPI_CR_MEN_MASK;
+
+	/* keep the chip select asserted until the end of the zephyr xfer by using
+	 * continunous transfer mode. If SPI_HOLD_ON_CS is requested, we need
+	 * to also set CONTC in order to continue the previous command to keep CS
+	 * asserted.
+	 */
+	if (spi_cfg->operation & SPI_HOLD_ON_CS || base->TCR & LPSPI_TCR_CONTC_MASK) {
+		base->TCR |= LPSPI_TCR_CONTC_MASK | LPSPI_TCR_CONT_MASK;
+	} else {
+		base->TCR |= LPSPI_TCR_CONT_MASK;
+	}
+	/* tcr is written to tx fifo */
+	lpspi_wait_tx_fifo_empty(dev);
+
+	/* start the transfer sequence which are handled by irqs */
+	lpspi_next_tx_fill(dev);
+
+	base->IER |= LPSPI_IER_TDIE_MASK | LPSPI_IER_RDIE_MASK;
+
+	ret = spi_context_wait_for_completion(ctx);
+	if (ret >= 0) {
+		return ret;
+	}
+
+error:
+	spi_context_release(ctx, ret);
+	return ret;
+}
+
+static int lpspi_transceive_sync(const struct device *dev, const struct spi_config *spi_cfg,
+				    const struct spi_buf_set *tx_bufs,
+				    const struct spi_buf_set *rx_bufs)
+{
+	return transceive(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL);
+}
+
+#ifdef CONFIG_SPI_ASYNC
+static int lpspi_transceive_async(const struct device *dev, const struct spi_config *spi_cfg,
+				     const struct spi_buf_set *tx_bufs,
+				     const struct spi_buf_set *rx_bufs, spi_callback_t cb,
+				     void *userdata)
+{
+	return transceive(dev, spi_cfg, tx_bufs, rx_bufs, true, cb, userdata);
+}
+#endif /* CONFIG_SPI_ASYNC */
+
+static DEVICE_API(spi, lpspi_driver_api) = {
+	.transceive = lpspi_transceive_sync,
+#ifdef CONFIG_SPI_ASYNC
+	.transceive_async = lpspi_transceive_async,
+#endif
+#ifdef CONFIG_SPI_RTIO
+	.iodev_submit = spi_rtio_iodev_default_submit,
+#endif
+	.release = spi_lpspi_release,
+};
+
+static int lpspi_init(const struct device *dev)
+{
+	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
+	struct lpspi_data *data = dev->data;
+	int err = 0;
+
+	err = spi_nxp_init_common(dev);
+	if (err) {
+		return err;
+	}
+
+	/* Starting config should be master with active low CS, to make sure
+	 * the CS lines are configured properly at init for the most common use
+	 * cases. This can be changed later on transceive call if user specifies
+	 * different spi configuration.
+	 */
+	base->CFGR1 |= LPSPI_CFGR1_MASTER_MASK;
+	base->CFGR1 &= ~LPSPI_CFGR1_PCSPOL_MASK;
+
+	spi_context_unlock_unconditionally(&data->ctx);
+
+	return 0;
+}
+
+#define LPSPI_INIT(n)                                                                              \
+	SPI_NXP_LPSPI_COMMON_INIT(n)                                                               \
+	SPI_LPSPI_CONFIG_INIT(n)                                                              \
+                                                                                                   \
+	static struct lpspi_driver_data lpspi_##n##_driver_data;                                   \
+                                                                                                   \
+	static struct lpspi_data lpspi_data_##n = {                                             \
+		SPI_NXP_LPSPI_COMMON_DATA_INIT(n)                                                  \
+		.driver_data = &lpspi_##n##_driver_data,                                           \
+	};                                                                                         \
+                                                                                                   \
+	SPI_DEVICE_DT_INST_DEFINE(n, lpspi_init, NULL, &lpspi_data_##n,                            \
+				  &lpspi_config_##n, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,     \
+				  &lpspi_driver_api);
+
+#define SPI_LPSPI_INIT_IF_DMA(n) IF_DISABLED(SPI_NXP_LPSPI_HAS_DMAS(n), (LPSPI_INIT(n)))
+
+#define SPI_LPSPI_INIT(n)                                                                     \
+	COND_CODE_1(CONFIG_SPI_MCUX_LPSPI_DMA,				   \
+						(SPI_LPSPI_INIT_IF_DMA(n)), (LPSPI_INIT(n)))
+
+DT_INST_FOREACH_STATUS_OKAY(SPI_LPSPI_INIT)
diff --git a/drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_common.c b/drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_common.c
new file mode 100644
index 00000000000..5cd9d1cde5f
--- /dev/null
+++ b/drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_common.c
@@ -0,0 +1,231 @@
+/*
+ * Copyright 2018, 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(spi_lpspi, CONFIG_SPI_LOG_LEVEL);
+
+#include "spi_nxp_lpspi_priv.h"
+#include <fsl_lpspi.h>
+
+#if defined(LPSPI_RSTS) || defined(LPSPI_CLOCKS)
+static LPSPI_Type *const lpspi_bases[] = LPSPI_BASE_PTRS;
+#endif
+
+#ifdef LPSPI_RSTS
+static const reset_ip_name_t lpspi_resets[] = LPSPI_RSTS;
+
+static inline reset_ip_name_t lpspi_get_reset(LPSPI_Type *const base)
+{
+	reset_ip_name_t rst = -1; /* invalid initial value */
+
+	ARRAY_FOR_EACH(lpspi_bases, idx) {
+		if (lpspi_bases[idx] == base) {
+			rst = lpspi_resets[idx];
+			break;
+		}
+	}
+
+	__ASSERT_NO_MSG(rst != -1);
+	return rst;
+
+}
+#endif
+
+#ifdef LPSPI_CLOCKS
+static const clock_ip_name_t lpspi_clocks[] = LPSPI_CLOCKS;
+
+static inline clock_ip_name_t lpspi_get_clock(LPSPI_Type *const base)
+{
+	clock_ip_name_t clk = -1; /* invalid initial value */
+
+	ARRAY_FOR_EACH(lpspi_bases, idx) {
+		if (lpspi_bases[idx] == base) {
+			clk = lpspi_clocks[idx];
+			break;
+		}
+	}
+
+	__ASSERT_NO_MSG(clk != -1);
+	return clk;
+}
+#endif
+
+void lpspi_wait_tx_fifo_empty(const struct device *dev)
+{
+	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
+
+	while (LPSPI_GetTxFifoCount(base) != 0) {
+	}
+}
+
+int spi_lpspi_release(const struct device *dev, const struct spi_config *spi_cfg)
+{
+	struct lpspi_data *data = dev->data;
+
+	spi_context_unlock_unconditionally(&data->ctx);
+
+	return 0;
+}
+
+static inline int lpspi_validate_xfer_args(const struct spi_config *spi_cfg)
+{
+	uint32_t word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
+	uint32_t pcs = spi_cfg->slave;
+
+	if (spi_cfg->operation & SPI_HALF_DUPLEX) {
+		/* the IP DOES support half duplex, need to implement driver support */
+		LOG_WRN("Half-duplex not supported");
+		return -ENOTSUP;
+	}
+
+	if (word_size < 2 || (word_size % 32 == 1)) {
+		/* Zephyr word size == hardware FRAME size (not word size)
+		 * Max frame size: 4096 bits
+		 *   (zephyr field is 6 bit wide for max 64 bit size, no need to check)
+		 * Min frame size: 8 bits.
+		 * Minimum hardware word size is 2. Since this driver is intended to work
+		 * for 32 bit platforms, and 64 bits is max size, then only 33 and 1 are invalid.
+		 */
+		LOG_WRN("Word size %d not allowed", word_size);
+		return -EINVAL;
+	}
+
+	if (pcs > LPSPI_CHIP_SELECT_COUNT - 1) {
+		LOG_WRN("Peripheral %d select exceeds max %d", pcs, LPSPI_CHIP_SELECT_COUNT - 1);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int spi_mcux_configure(const struct device *dev, const struct spi_config *spi_cfg)
+{
+	const struct lpspi_config *config = dev->config;
+	struct lpspi_data *data = dev->data;
+	struct spi_context *ctx = &data->ctx;
+	bool already_configured = spi_context_configured(ctx, spi_cfg);
+	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
+	uint32_t word_size = SPI_WORD_SIZE_GET(spi_cfg->operation);
+	lpspi_master_config_t master_config;
+	uint32_t clock_freq;
+	int ret;
+
+	/* fast path to avoid reconfigure */
+	/* TODO: S32K3 errata ERR050456 requiring module reset before every transfer,
+	 * investigate alternative workaround so we don't have this latency for S32.
+	 */
+	if (already_configured && !IS_ENABLED(CONFIG_SOC_FAMILY_NXP_S32)) {
+		return 0;
+	}
+
+	ret = lpspi_validate_xfer_args(spi_cfg);
+	if (ret) {
+		return ret;
+	}
+
+	ret = clock_control_get_rate(config->clock_dev, config->clock_subsys, &clock_freq);
+	if (ret) {
+		return ret;
+	}
+
+	if (already_configured) {
+		/* Setting the baud rate in LPSPI_MasterInit requires module to be disabled. Only
+		 * disable if already configured, otherwise the clock is not enabled and the
+		 * CR register cannot be written.
+		 */
+		LPSPI_Enable(base, false);
+		while ((base->CR & LPSPI_CR_MEN_MASK) != 0U) {
+			/* Wait until LPSPI is disabled. Datasheet:
+			 * After writing 0, MEN (Module Enable) remains set until the LPSPI has
+			 * completed the current transfer and is idle.
+			 */
+		}
+
+		/* this is workaround for ERR050456 */
+		base->CR |= LPSPI_CR_RST_MASK;
+		base->CR |= LPSPI_CR_RRF_MASK | LPSPI_CR_RTF_MASK;
+		base->CR = 0x00U;
+	}
+
+	data->ctx.config = spi_cfg;
+
+	LPSPI_MasterGetDefaultConfig(&master_config);
+
+	master_config.bitsPerFrame = word_size < 8 ? 8 : word_size; /* minimum FRAMSZ is 8 */
+	master_config.cpol = (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPOL)
+				     ? kLPSPI_ClockPolarityActiveLow
+				     : kLPSPI_ClockPolarityActiveHigh;
+	master_config.cpha = (SPI_MODE_GET(spi_cfg->operation) & SPI_MODE_CPHA)
+				     ? kLPSPI_ClockPhaseSecondEdge
+				     : kLPSPI_ClockPhaseFirstEdge;
+	master_config.direction =
+		(spi_cfg->operation & SPI_TRANSFER_LSB) ? kLPSPI_LsbFirst : kLPSPI_MsbFirst;
+	master_config.baudRate = spi_cfg->frequency;
+	master_config.pcsToSckDelayInNanoSec = config->pcs_sck_delay;
+	master_config.lastSckToPcsDelayInNanoSec = config->sck_pcs_delay;
+	master_config.betweenTransferDelayInNanoSec = config->transfer_delay;
+	master_config.whichPcs = spi_cfg->slave + kLPSPI_Pcs0;
+	master_config.pcsActiveHighOrLow = (spi_cfg->operation & SPI_CS_ACTIVE_HIGH)
+				    ? kLPSPI_PcsActiveHigh : kLPSPI_PcsActiveLow;
+	master_config.pinCfg = config->data_pin_config;
+	master_config.dataOutConfig = config->tristate_output ? kLpspiDataOutTristate :
+								kLpspiDataOutRetained;
+
+	LPSPI_MasterInit(base, &master_config, clock_freq);
+	LPSPI_SetDummyData(base, 0);
+
+	if (IS_ENABLED(CONFIG_DEBUG)) {
+		base->CR |= LPSPI_CR_DBGEN_MASK;
+	}
+
+	return 0;
+}
+
+static void lpspi_module_system_init(LPSPI_Type *base)
+{
+#ifdef LPSPI_CLOCKS
+	CLOCK_EnableClock(lpspi_get_clock(base));
+#endif
+
+#ifdef LPSPI_RSTS
+	RESET_ReleasePeripheralReset(lpspi_get_reset(base));
+#endif
+}
+
+int spi_nxp_init_common(const struct device *dev)
+{
+	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
+	const struct lpspi_config *config = dev->config;
+	struct lpspi_data *data = dev->data;
+	int err = 0;
+
+	DEVICE_MMIO_NAMED_MAP(dev, reg_base, K_MEM_CACHE_NONE | K_MEM_DIRECT_MAP);
+
+	data->dev = dev;
+
+	if (!device_is_ready(config->clock_dev)) {
+		LOG_ERR("clock control device not ready");
+		return -ENODEV;
+	}
+
+	lpspi_module_system_init(base);
+
+	err = spi_context_cs_configure_all(&data->ctx);
+	if (err < 0) {
+		return err;
+	}
+
+	err = pinctrl_apply_state(config->pincfg, PINCTRL_STATE_DEFAULT);
+	if (err) {
+		return err;
+	}
+
+	LPSPI_Reset(base);
+
+	config->irq_config_func(dev);
+
+	return err;
+}
diff --git a/drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_dma.c b/drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_dma.c
new file mode 100644
index 00000000000..5b14a66fc19
--- /dev/null
+++ b/drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_dma.c
@@ -0,0 +1,356 @@
+/*
+ * Copyright 2018, 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_lpspi
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(spi_lpspi, CONFIG_SPI_LOG_LEVEL);
+
+#include <zephyr/drivers/dma.h>
+#include "spi_nxp_lpspi_priv.h"
+
+/* dummy memory used for transferring NOP when tx buf is null */
+static uint32_t tx_nop_val; /* check compliance says no init to 0, but should be 0 in bss */
+/* dummy memory for transferring to when RX buf is null */
+static uint32_t dummy_buffer;
+
+struct spi_dma_stream {
+	const struct device *dma_dev;
+	uint32_t channel;
+	struct dma_config dma_cfg;
+	struct dma_block_config dma_blk_cfg;
+	bool chunk_done;
+};
+
+struct spi_nxp_dma_data {
+	struct spi_dma_stream dma_rx;
+	struct spi_dma_stream dma_tx;
+};
+
+static struct dma_block_config *lpspi_dma_common_load(struct spi_dma_stream *stream,
+							 const struct device *dev,
+							 const uint8_t *buf, size_t len)
+{
+	struct dma_block_config *blk_cfg = &stream->dma_blk_cfg;
+
+	memset(blk_cfg, 0, sizeof(struct dma_block_config));
+
+	blk_cfg->block_size = len;
+
+	stream->dma_cfg.source_burst_length = 1;
+	stream->dma_cfg.user_data = (void *)dev;
+	stream->dma_cfg.head_block = blk_cfg;
+
+	return blk_cfg;
+}
+
+static int lpspi_dma_tx_load(const struct device *dev, const uint8_t *buf, size_t len)
+{
+	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
+	struct lpspi_data *data = dev->data;
+	struct spi_nxp_dma_data *dma_data = (struct spi_nxp_dma_data *)data->driver_data;
+	struct spi_dma_stream *stream = &dma_data->dma_tx;
+	struct dma_block_config *blk_cfg = lpspi_dma_common_load(stream, dev, buf, len);
+
+	if (buf == NULL) {
+		/* pretend that nop value comes from peripheral so dma doesn't move source */
+		blk_cfg->source_address = (uint32_t)&tx_nop_val;
+		stream->dma_cfg.channel_direction = PERIPHERAL_TO_PERIPHERAL;
+	} else {
+		blk_cfg->source_address = (uint32_t)buf;
+		stream->dma_cfg.channel_direction = MEMORY_TO_PERIPHERAL;
+	}
+
+	blk_cfg->dest_address = (uint32_t) &(base->TDR);
+
+	return dma_config(stream->dma_dev, stream->channel, &stream->dma_cfg);
+}
+
+static int lpspi_dma_rx_load(const struct device *dev, uint8_t *buf, size_t len)
+{
+	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
+	struct lpspi_data *data = dev->data;
+	struct spi_nxp_dma_data *dma_data = (struct spi_nxp_dma_data *)data->driver_data;
+	struct spi_dma_stream *stream = &dma_data->dma_rx;
+	struct dma_block_config *blk_cfg = lpspi_dma_common_load(stream, dev, buf, len);
+
+	if (buf == NULL) {
+		/* pretend it is peripheral xfer so DMA just xfer to dummy buf */
+		stream->dma_cfg.channel_direction = PERIPHERAL_TO_PERIPHERAL;
+		blk_cfg->dest_address = (uint32_t)&dummy_buffer;
+	} else {
+		stream->dma_cfg.channel_direction = PERIPHERAL_TO_MEMORY;
+		blk_cfg->dest_address = (uint32_t)buf;
+	}
+
+	blk_cfg->source_address = (uint32_t) &(base->RDR);
+
+	return dma_config(stream->dma_dev, stream->channel, &stream->dma_cfg);
+}
+
+static inline int lpspi_dma_rxtx_load(const struct device *dev)
+{
+	struct lpspi_data *data = dev->data;
+	struct spi_nxp_dma_data *dma_data = (struct spi_nxp_dma_data *)data->driver_data;
+	struct spi_dma_stream *rx = &dma_data->dma_rx;
+	struct spi_dma_stream *tx = &dma_data->dma_tx;
+	struct spi_context *ctx = &data->ctx;
+	size_t next_chunk_size = spi_context_max_continuous_chunk(ctx);
+	int ret = 0;
+
+	if (next_chunk_size == 0) {
+		/* In case both buffers are 0 length, we should not even be here
+		 * and attempting to set up a DMA transfer like this will cause
+		 * errors that lock up the system in some cases with eDMA.
+		 */
+		return -ENODATA;
+	}
+
+	ret = lpspi_dma_tx_load(dev, ctx->tx_buf, next_chunk_size);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = lpspi_dma_rx_load(dev, ctx->rx_buf, next_chunk_size);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = dma_start(rx->dma_dev, rx->channel);
+	if (ret != 0) {
+		return ret;
+	}
+
+	return dma_start(tx->dma_dev, tx->channel);
+}
+
+static int lpspi_dma_next_fill(const struct device *dev)
+{
+	struct lpspi_data *data = (struct lpspi_data *)dev->data;
+	struct spi_nxp_dma_data *dma_data = (struct spi_nxp_dma_data *)data->driver_data;
+	struct spi_dma_stream *rx = &dma_data->dma_rx;
+	struct spi_dma_stream *tx = &dma_data->dma_tx;
+
+	rx->chunk_done = false;
+	tx->chunk_done = false;
+
+	return lpspi_dma_rxtx_load(dev);
+}
+
+static void spi_mcux_dma_callback(const struct device *dev, void *arg, uint32_t channel, int status)
+{
+	const struct device *spi_dev = arg;
+	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(spi_dev, reg_base);
+	struct lpspi_data *data = (struct lpspi_data *)spi_dev->data;
+	struct spi_nxp_dma_data *dma_data = (struct spi_nxp_dma_data *)data->driver_data;
+	struct spi_dma_stream *rx = &dma_data->dma_rx;
+	struct spi_dma_stream *tx = &dma_data->dma_tx;
+	struct spi_context *ctx = &data->ctx;
+	char debug_char;
+
+	if (status < 0) {
+		goto error;
+	} else {
+		/* don't care about positive values, normalize to "okay" = 0 */
+		status = 0;
+	}
+
+	if (channel == rx->channel) {
+		spi_context_update_rx(ctx, 1, rx->dma_blk_cfg.block_size);
+		debug_char = 'R';
+		rx->chunk_done = true;
+	} else if (channel == tx->channel) {
+		spi_context_update_tx(ctx, 1, tx->dma_blk_cfg.block_size);
+		debug_char = 'T';
+		tx->chunk_done = true;
+	} else {
+		/* invalid channel */
+		status = -EIO;
+		goto error;
+	}
+
+	LOG_DBG("DMA %cX Block Complete", debug_char);
+
+	/* wait for the other channel to finish if needed */
+	if (!rx->chunk_done || !tx->chunk_done) {
+		return;
+	}
+
+
+	while ((IS_ENABLED(CONFIG_SOC_FAMILY_NXP_IMXRT) ||
+		IS_ENABLED(CONFIG_SOC_FAMILY_KINETIS)) &&
+		(base->SR & LPSPI_SR_MBF_MASK)) {
+		/* wait until module is idle */
+	}
+
+	if (spi_context_max_continuous_chunk(ctx) == 0) {
+		goto done;
+	}
+
+	status = lpspi_dma_next_fill(spi_dev);
+	if (status) {
+		goto error;
+	}
+
+	return;
+error:
+	LOG_ERR("DMA callback error with channel %d err %d.", channel, status);
+done:
+	base->DER &= ~(LPSPI_DER_TDDE_MASK | LPSPI_DER_RDDE_MASK);
+	base->TCR &= ~LPSPI_TCR_CONT_MASK;
+	lpspi_wait_tx_fifo_empty(spi_dev);
+	spi_context_cs_control(ctx, false);
+	base->CR |= LPSPI_CR_RTF_MASK | LPSPI_CR_RRF_MASK;
+	spi_context_complete(ctx, spi_dev, status);
+	spi_context_release(ctx, status);
+}
+
+static int transceive_dma(const struct device *dev, const struct spi_config *spi_cfg,
+			  const struct spi_buf_set *tx_bufs, const struct spi_buf_set *rx_bufs,
+			  bool asynchronous, spi_callback_t cb, void *userdata)
+{
+	LPSPI_Type *base = (LPSPI_Type *)DEVICE_MMIO_NAMED_GET(dev, reg_base);
+	struct lpspi_data *data = dev->data;
+	struct spi_context *ctx = &data->ctx;
+	int ret;
+
+	spi_context_lock(ctx, asynchronous, cb, userdata, spi_cfg);
+
+	ret = spi_mcux_configure(dev, spi_cfg);
+	if (ret) {
+		goto out;
+	}
+
+	spi_context_buffers_setup(ctx, tx_bufs, rx_bufs, 1);
+
+	ret = lpspi_dma_next_fill(dev);
+	if (ret == -ENODATA) {
+		/* No transfer to do? So just exit */
+		ret = 0;
+		goto out;
+	} else if (ret) {
+		goto out;
+	}
+
+	if (!(IS_ENABLED(CONFIG_SOC_FAMILY_NXP_IMXRT) || IS_ENABLED(CONFIG_SOC_FAMILY_KINETIS))) {
+		base->TCR |= LPSPI_TCR_CONT_MASK;
+	}
+
+	spi_context_cs_control(ctx, true);
+
+	base->CR |= LPSPI_CR_RTF_MASK | LPSPI_CR_RRF_MASK;
+
+	base->DER |= LPSPI_DER_TDDE_MASK | LPSPI_DER_RDDE_MASK;
+
+	ret = spi_context_wait_for_completion(ctx);
+	if (ret >= 0) {
+		return ret;
+	}
+out:
+	spi_context_release(ctx, ret);
+	return ret;
+}
+
+static int lpspi_dma_dev_ready(const struct device *dma_dev)
+{
+	if (!device_is_ready(dma_dev)) {
+		LOG_ERR("%s device is not ready", dma_dev->name);
+		return false;
+	}
+
+	return true;
+}
+
+static int spi_mcux_dma_init(const struct device *dev)
+{
+	struct lpspi_data *data = dev->data;
+	struct spi_nxp_dma_data *dma_data = (struct spi_nxp_dma_data *)data->driver_data;
+	int err = 0;
+
+	if (!lpspi_dma_dev_ready(dma_data->dma_tx.dma_dev) ||
+	    !lpspi_dma_dev_ready(dma_data->dma_rx.dma_dev)) {
+		return -ENODEV;
+	}
+
+	err = spi_nxp_init_common(dev);
+	if (err) {
+		return err;
+	}
+
+	spi_context_unlock_unconditionally(&data->ctx);
+
+	return 0;
+}
+
+static int spi_nxp_dma_transceive_sync(const struct device *dev, const struct spi_config *spi_cfg,
+				       const struct spi_buf_set *tx_bufs,
+				       const struct spi_buf_set *rx_bufs)
+{
+	return transceive_dma(dev, spi_cfg, tx_bufs, rx_bufs, false, NULL, NULL);
+}
+
+#ifdef CONFIG_SPI_ASYNC
+static int spi_nxp_dma_transceive_async(const struct device *dev, const struct spi_config *spi_cfg,
+					const struct spi_buf_set *tx_bufs,
+					const struct spi_buf_set *rx_bufs, spi_callback_t cb,
+					void *userdata)
+{
+	return transceive_dma(dev, spi_cfg, tx_bufs, rx_bufs, true, cb, userdata);
+}
+#endif /* CONFIG_SPI_ASYNC */
+
+static DEVICE_API(spi, lpspi_dma_driver_api) = {
+	.transceive = spi_nxp_dma_transceive_sync,
+#ifdef CONFIG_SPI_ASYNC
+	.transceive_async = spi_nxp_dma_transceive_async,
+#endif
+#ifdef CONFIG_SPI_RTIO
+	.iodev_submit = spi_rtio_iodev_default_submit,
+#endif
+	.release = spi_lpspi_release,
+};
+
+static void lpspi_isr(const struct device *dev)
+{
+	/* ISR not used for DMA based LPSPI driver */
+}
+
+#define LPSPI_DMA_COMMON_CFG(n)			\
+	.dma_callback = spi_mcux_dma_callback,	\
+	.source_data_size = 1,			\
+	.dest_data_size = 1,			\
+	.block_count = 1
+
+#define SPI_DMA_CHANNELS(n)                                                                        \
+	IF_ENABLED(DT_INST_DMAS_HAS_NAME(n, tx),                                                   \
+		(.dma_tx = {.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, tx)),            \
+			    .channel = DT_INST_DMAS_CELL_BY_NAME(n, tx, mux),                      \
+			    .dma_cfg = {.channel_direction = MEMORY_TO_PERIPHERAL,                 \
+			    LPSPI_DMA_COMMON_CFG(n),						   \
+			    .dma_slot = DT_INST_DMAS_CELL_BY_NAME(n, tx, source)}},))		   \
+	IF_ENABLED(DT_INST_DMAS_HAS_NAME(n, rx),                                                   \
+		(.dma_rx = {.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(n, rx)),            \
+			    .channel = DT_INST_DMAS_CELL_BY_NAME(n, rx, mux),                      \
+			    .dma_cfg = {.channel_direction = PERIPHERAL_TO_MEMORY,                 \
+			    LPSPI_DMA_COMMON_CFG(n),						   \
+			    .dma_slot = DT_INST_DMAS_CELL_BY_NAME(n, rx, source)}},))
+
+#define LPSPI_DMA_INIT(n)                                                                          \
+	SPI_NXP_LPSPI_COMMON_INIT(n)                                                               \
+	SPI_LPSPI_CONFIG_INIT(n)                                                              \
+                                                                                                   \
+	static struct spi_nxp_dma_data lpspi_dma_data##n = {SPI_DMA_CHANNELS(n)};                  \
+                                                                                                   \
+	static struct lpspi_data lpspi_data_##n = {.driver_data = &lpspi_dma_data##n,        \
+							 SPI_NXP_LPSPI_COMMON_DATA_INIT(n)};       \
+                                                                                                   \
+	SPI_DEVICE_DT_INST_DEFINE(n, spi_mcux_dma_init, NULL, &lpspi_data_##n,                  \
+				  &lpspi_config_##n, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,     \
+				  &lpspi_dma_driver_api);
+
+#define SPI_NXP_LPSPI_DMA_INIT(n) IF_ENABLED(SPI_NXP_LPSPI_HAS_DMAS(n), (LPSPI_DMA_INIT(n)))
+
+DT_INST_FOREACH_STATUS_OKAY(SPI_NXP_LPSPI_DMA_INIT)
diff --git a/drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_priv.h b/drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_priv.h
new file mode 100644
index 00000000000..2054000de2e
--- /dev/null
+++ b/drivers/spi/spi_nxp_lpspi/spi_nxp_lpspi_priv.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2018, 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/spi.h>
+#include <zephyr/drivers/spi/rtio.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/irq.h>
+
+#include "../spi_context.h"
+
+#if CONFIG_NXP_LP_FLEXCOMM
+#include <zephyr/drivers/mfd/nxp_lp_flexcomm.h>
+#endif
+
+/* If any hardware revisions change this, make it into a DT property.
+ * DONT'T make #ifdefs here by platform.
+ */
+#define LPSPI_CHIP_SELECT_COUNT   4
+#define LPSPI_MIN_FRAME_SIZE_BITS 8
+
+#define LPSPI_INTERRUPT_BITS GENMASK(8, 13)
+
+/* Required by DEVICE_MMIO_NAMED_* macros */
+#define DEV_CFG(_dev)  ((const struct lpspi_config *)(_dev)->config)
+#define DEV_DATA(_dev) ((struct lpspi_data *)(_dev)->data)
+
+struct lpspi_config {
+	DEVICE_MMIO_NAMED_ROM(reg_base);
+	const struct device *clock_dev;
+	clock_control_subsys_t clock_subsys;
+	void (*irq_config_func)(const struct device *dev);
+	uint32_t pcs_sck_delay;
+	uint32_t sck_pcs_delay;
+	uint32_t transfer_delay;
+	const struct pinctrl_dev_config *pincfg;
+	uint8_t data_pin_config;
+	bool tristate_output;
+	uint8_t tx_fifo_size;
+	uint8_t rx_fifo_size;
+	uint8_t irqn;
+};
+
+struct lpspi_data {
+	DEVICE_MMIO_NAMED_RAM(reg_base);
+	const struct device *dev;
+	struct spi_context ctx;
+	void *driver_data;
+	size_t transfer_len;
+};
+
+/* verifies spi_cfg validity and set up configuration of hardware for xfer */
+int spi_mcux_configure(const struct device *dev, const struct spi_config *spi_cfg);
+
+/* Does these things:
+ * Set data.dev
+ * Check clocks device is ready
+ * Configure cs gpio pin if needed
+ * Mux pinctrl to lpspi
+ * Enable LPSPI IRQ at system level
+ */
+int spi_nxp_init_common(const struct device *dev);
+
+/* common api function for now */
+int spi_lpspi_release(const struct device *dev, const struct spi_config *spi_cfg);
+
+void lpspi_wait_tx_fifo_empty(const struct device *dev);
+
+#define SPI_LPSPI_IRQ_FUNC_LP_FLEXCOMM(n)                                                     \
+	nxp_lp_flexcomm_setirqhandler(DEVICE_DT_GET(DT_INST_PARENT(n)), DEVICE_DT_INST_GET(n),     \
+				      LP_FLEXCOMM_PERIPH_LPSPI, lpspi_isr);
+
+#define SPI_LPSPI_IRQ_FUNC_DISTINCT(n)                                                        \
+	IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), lpspi_isr, DEVICE_DT_INST_GET(n),   \
+		    0);                                                                            \
+	irq_enable(DT_INST_IRQN(n));
+
+#define SPI_LPSPI_IRQ_FUNC(n) COND_CODE_1(DT_NODE_HAS_COMPAT(DT_INST_PARENT(n),                    \
+								  nxp_lp_flexcomm),                \
+						(SPI_LPSPI_IRQ_FUNC_LP_FLEXCOMM(n)),               \
+						(SPI_LPSPI_IRQ_FUNC_DISTINCT(n)))
+
+#define LPSPI_IRQN(n) COND_CODE_1(DT_NODE_HAS_COMPAT(DT_INST_PARENT(n), nxp_lp_flexcomm),	   \
+					(DT_IRQN(DT_INST_PARENT(n))), (DT_INST_IRQN(n)))
+
+#define SPI_LPSPI_CONFIG_INIT(n)                                                              \
+	static const struct lpspi_config lpspi_config_##n = {                                \
+		DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)),                              \
+		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),                                \
+		.clock_subsys = (clock_control_subsys_t)DT_INST_CLOCKS_CELL(n, name),              \
+		.irq_config_func = lpspi_config_func_##n,                                          \
+		.pcs_sck_delay = UTIL_AND(DT_INST_NODE_HAS_PROP(n, pcs_sck_delay),                 \
+					  DT_INST_PROP(n, pcs_sck_delay)),                         \
+		.sck_pcs_delay = UTIL_AND(DT_INST_NODE_HAS_PROP(n, sck_pcs_delay),                 \
+					  DT_INST_PROP(n, sck_pcs_delay)),                         \
+		.transfer_delay = UTIL_AND(DT_INST_NODE_HAS_PROP(n, transfer_delay),               \
+					   DT_INST_PROP(n, transfer_delay)),                       \
+		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),                                       \
+		.data_pin_config = (uint8_t)DT_INST_ENUM_IDX(n, data_pin_config),                  \
+		.tristate_output = DT_INST_PROP(n, tristate_output),                               \
+		.rx_fifo_size = (uint8_t)DT_INST_PROP(n, rx_fifo_size),                            \
+		.tx_fifo_size = (uint8_t)DT_INST_PROP(n, tx_fifo_size),                            \
+		.irqn = (uint8_t)LPSPI_IRQN(n),                                                    \
+	};
+
+#define SPI_NXP_LPSPI_COMMON_INIT(n)                                                               \
+	PINCTRL_DT_INST_DEFINE(n);                                                                 \
+                                                                                                   \
+	static void lpspi_config_func_##n(const struct device *dev)                                \
+	{                                                                                          \
+		SPI_LPSPI_IRQ_FUNC(n)                                                         \
+	}
+
+#define SPI_NXP_LPSPI_COMMON_DATA_INIT(n)                                                          \
+	SPI_CONTEXT_INIT_LOCK(lpspi_data_##n, ctx),                                             \
+		SPI_CONTEXT_INIT_SYNC(lpspi_data_##n, ctx),                                     \
+		SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx)
+
+#define SPI_NXP_LPSPI_HAS_DMAS(n)                                                                  \
+	UTIL_AND(DT_INST_DMAS_HAS_NAME(n, tx), DT_INST_DMAS_HAS_NAME(n, rx))
diff --git a/drivers/spi/spi_renesas_ra.c b/drivers/spi/spi_renesas_ra.c
index c580cb4d711..9653b6510d5 100644
--- a/drivers/spi/spi_renesas_ra.c
+++ b/drivers/spi/spi_renesas_ra.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -462,9 +462,9 @@ static int ra_spi_release(const struct device *dev, const struct spi_config *con
 
 static DEVICE_API(spi, ra_spi_driver_api) = {.transceive = ra_spi_transceive,
 #ifdef CONFIG_SPI_ASYNC
-							.transceive_async = ra_spi_transceive_async,
+					     .transceive_async = ra_spi_transceive_async,
 #endif /* CONFIG_SPI_ASYNC */
-							.release = ra_spi_release};
+					     .release = ra_spi_release};
 
 static int spi_ra_init(const struct device *dev)
 {
@@ -664,15 +664,10 @@ static void ra_spi_eri_isr(const struct device *dev)
 }
 #endif
 
-#define _ELC_EVENT_SPI_RXI(channel) ELC_EVENT_SPI##channel##_RXI
-#define _ELC_EVENT_SPI_TXI(channel) ELC_EVENT_SPI##channel##_TXI
-#define _ELC_EVENT_SPI_TEI(channel) ELC_EVENT_SPI##channel##_TEI
-#define _ELC_EVENT_SPI_ERI(channel) ELC_EVENT_SPI##channel##_ERI
-
-#define ELC_EVENT_SPI_RXI(channel) _ELC_EVENT_SPI_RXI(channel)
-#define ELC_EVENT_SPI_TXI(channel) _ELC_EVENT_SPI_TXI(channel)
-#define ELC_EVENT_SPI_TEI(channel) _ELC_EVENT_SPI_TEI(channel)
-#define ELC_EVENT_SPI_ERI(channel) _ELC_EVENT_SPI_ERI(channel)
+#define EVENT_SPI_RXI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_SPI, channel, _RXI))
+#define EVENT_SPI_TXI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_SPI, channel, _TXI))
+#define EVENT_SPI_TEI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_SPI, channel, _TEI))
+#define EVENT_SPI_ERI(channel) BSP_PRV_IELS_ENUM(CONCAT(EVENT_SPI, channel, _ERI))
 
 #if defined(CONFIG_SPI_INTERRUPT)
 
@@ -681,13 +676,13 @@ static void ra_spi_eri_isr(const struct device *dev)
 		ARG_UNUSED(dev);                                                                   \
                                                                                                    \
 		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, rxi, irq)] =                               \
-			ELC_EVENT_SPI_RXI(DT_INST_PROP(index, channel));                           \
+			EVENT_SPI_RXI(DT_INST_PROP(index, channel));                               \
 		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, txi, irq)] =                               \
-			ELC_EVENT_SPI_TXI(DT_INST_PROP(index, channel));                           \
+			EVENT_SPI_TXI(DT_INST_PROP(index, channel));                               \
 		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, tei, irq)] =                               \
-			ELC_EVENT_SPI_TEI(DT_INST_PROP(index, channel));                           \
+			EVENT_SPI_TEI(DT_INST_PROP(index, channel));                               \
 		R_ICU->IELSR[DT_INST_IRQ_BY_NAME(index, eri, irq)] =                               \
-			ELC_EVENT_SPI_ERI(DT_INST_PROP(index, channel));                           \
+			EVENT_SPI_ERI(DT_INST_PROP(index, channel));                               \
                                                                                                    \
 		IRQ_CONNECT(DT_INST_IRQ_BY_NAME(index, rxi, irq),                                  \
 			    DT_INST_IRQ_BY_NAME(index, rxi, priority), ra_spi_rxi_isr,             \
diff --git a/drivers/spi/spi_rpi_pico_pio.c b/drivers/spi/spi_rpi_pico_pio.c
index 484707ab2ad..1da7cc33cfa 100644
--- a/drivers/spi/spi_rpi_pico_pio.c
+++ b/drivers/spi/spi_rpi_pico_pio.c
@@ -68,6 +68,22 @@ RPI_PICO_PIO_DEFINE_PROGRAM(spi_mode_0_0, SPI_MODE_0_0_WRAP_TARGET, SPI_MODE_0_0
 				    /*     .wrap */
 );
 
+/* ------------ */
+/* spi_mode_0_1 */
+/* ------------ */
+
+#define SPI_MODE_0_1_WRAP_TARGET 0
+#define SPI_MODE_0_1_WRAP        2
+#define SPI_MODE_0_1_CYCLES      4
+
+RPI_PICO_PIO_DEFINE_PROGRAM(spi_mode_0_1, SPI_MODE_0_1_WRAP_TARGET, SPI_MODE_0_1_WRAP,
+			    /*     .wrap_target */
+			    0x6021,   /* 0: out    x, 1            side 0 */
+			    0xb101,   /* 1: mov    pins, x         side 1 [1] */
+			    0x4001,   /* 2: in     pins, 1         side 0 */
+				      /*     .wrap */
+);
+
 /* ------------ */
 /* spi_mode_1_1 */
 /* ------------ */
@@ -365,8 +381,13 @@ static int spi_pico_pio_configure(const struct spi_pico_pio_config *dev_cfg,
 			wrap_target = RPI_PICO_PIO_GET_WRAP_TARGET(spi_mode_1_1);
 			wrap = RPI_PICO_PIO_GET_WRAP(spi_mode_1_1);
 			cycles = SPI_MODE_1_1_CYCLES;
+		} else if ((cpol == 0) && (cpha == 1)) {
+			program = RPI_PICO_PIO_GET_PROGRAM(spi_mode_0_1);
+			wrap_target = RPI_PICO_PIO_GET_WRAP_TARGET(spi_mode_0_1);
+			wrap = RPI_PICO_PIO_GET_WRAP(spi_mode_0_1);
+			cycles = SPI_MODE_0_1_CYCLES;
 		} else {
-			LOG_ERR("Not supported:  cpol=%d, cpha=%d\n", cpol, cpha);
+			LOG_ERR("Not supported:  cpol=%d, cpha=%d", cpol, cpha);
 			return -ENOTSUP;
 		}
 
diff --git a/drivers/spi/spi_rtio.c b/drivers/spi/spi_rtio.c
index 975636a098a..1a051ba9d7d 100644
--- a/drivers/spi/spi_rtio.c
+++ b/drivers/spi/spi_rtio.c
@@ -12,7 +12,7 @@
 #include <zephyr/sys/mpsc_lockfree.h>
 
 #include <zephyr/logging/log.h>
-LOG_MODULE_DECLARE(spi_rtio, CONFIG_SPI_LOG_LEVEL);
+LOG_MODULE_REGISTER(spi_rtio, CONFIG_SPI_LOG_LEVEL);
 
 const struct rtio_iodev_api spi_iodev_api = {
 	.submit = spi_iodev_submit,
@@ -22,6 +22,7 @@ static void spi_rtio_iodev_default_submit_sync(struct rtio_iodev_sqe *iodev_sqe)
 {
 	struct spi_dt_spec *dt_spec = iodev_sqe->sqe.iodev->data;
 	const struct device *dev = dt_spec->bus;
+	uint8_t num_msgs = 0;
 	int err = 0;
 
 	LOG_DBG("Sync RTIO work item for: %p", (void *)dev);
@@ -33,67 +34,103 @@ static void spi_rtio_iodev_default_submit_sync(struct rtio_iodev_sqe *iodev_sqe)
 	struct rtio_iodev_sqe *txn_head = iodev_sqe;
 	struct rtio_iodev_sqe *txn_curr = iodev_sqe;
 
+	/* We allocate the spi_buf's on the stack, to do so
+	 * the count of messages needs to be determined to
+	 * ensure we don't go over the statically sized array.
+	 */
 	do {
-		struct rtio_sqe *sqe = &txn_curr->sqe;
-		struct spi_buf tx_buf = {0};
-		struct spi_buf_set tx_buf_set = {
-			.buffers = &tx_buf,
-		};
+		switch (txn_curr->sqe.op) {
+		case RTIO_OP_RX:
+		case RTIO_OP_TX:
+		case RTIO_OP_TINY_TX:
+		case RTIO_OP_TXRX:
+			num_msgs++;
+			break;
+		default:
+			LOG_ERR("Invalid op code %d for submission %p", txn_curr->sqe.op,
+				(void *)&txn_curr->sqe);
+			err = -EIO;
+			break;
+		}
+		txn_curr = rtio_txn_next(txn_curr);
+	} while (err == 0 && txn_curr != NULL);
 
-		struct spi_buf rx_buf = {0};
-		struct spi_buf_set rx_buf_set = {
-			.buffers = &rx_buf,
-		};
+	if (err != 0) {
+		rtio_iodev_sqe_err(txn_head, err);
+		return;
+	}
+
+	/* Allocate msgs on the stack, MISRA doesn't like VLAs so we need a statically
+	 * sized array here. It's pretty unlikely we have more than 4 spi messages
+	 * in a transaction as we typically would only have 2, one to write a
+	 * register address, and another to read/write the register into an array
+	 */
+	if (num_msgs > CONFIG_SPI_RTIO_FALLBACK_MSGS) {
+		LOG_ERR("At most CONFIG_SPI_RTIO_FALLBACK_MSGS"
+			" submissions in a transaction are"
+			" allowed in the default handler");
+		rtio_iodev_sqe_err(txn_head, -ENOMEM);
+		return;
+	}
+
+	struct spi_buf tx_bufs[CONFIG_SPI_RTIO_FALLBACK_MSGS];
+	struct spi_buf rx_bufs[CONFIG_SPI_RTIO_FALLBACK_MSGS];
+	struct spi_buf_set tx_buf_set = {
+		.buffers = tx_bufs,
+		.count = num_msgs,
+	};
+	struct spi_buf_set rx_buf_set = {
+		.buffers = rx_bufs,
+		.count = num_msgs,
+	};
 
-		LOG_DBG("Preparing transfer: %p", txn_curr);
+	txn_curr = txn_head;
+
+	for (size_t i = 0 ; i < num_msgs ; i++) {
+		struct rtio_sqe *sqe = &txn_curr->sqe;
 
 		switch (sqe->op) {
 		case RTIO_OP_RX:
-			rx_buf.buf = sqe->rx.buf;
-			rx_buf.len = sqe->rx.buf_len;
-			rx_buf_set.count = 1;
+			rx_bufs[i].buf = sqe->rx.buf;
+			rx_bufs[i].len = sqe->rx.buf_len;
+			tx_bufs[i].buf = NULL;
+			tx_bufs[i].len = sqe->rx.buf_len;
 			break;
 		case RTIO_OP_TX:
-			tx_buf.buf = (uint8_t *)sqe->tx.buf;
-			tx_buf.len = sqe->tx.buf_len;
-			tx_buf_set.count = 1;
+			rx_bufs[i].buf = NULL;
+			rx_bufs[i].len = sqe->tx.buf_len;
+			tx_bufs[i].buf = (uint8_t *)sqe->tx.buf;
+			tx_bufs[i].len = sqe->tx.buf_len;
 			break;
 		case RTIO_OP_TINY_TX:
-			tx_buf.buf = (uint8_t *)sqe->tiny_tx.buf;
-			tx_buf.len = sqe->tiny_tx.buf_len;
-			tx_buf_set.count = 1;
+			rx_bufs[i].buf = NULL;
+			rx_bufs[i].len = sqe->tiny_tx.buf_len;
+			tx_bufs[i].buf = (uint8_t *)sqe->tiny_tx.buf;
+			tx_bufs[i].len = sqe->tiny_tx.buf_len;
 			break;
 		case RTIO_OP_TXRX:
-			rx_buf.buf = sqe->txrx.rx_buf;
-			rx_buf.len = sqe->txrx.buf_len;
-			tx_buf.buf = (uint8_t *)sqe->txrx.tx_buf;
-			tx_buf.len = sqe->txrx.buf_len;
-			rx_buf_set.count = 1;
-			tx_buf_set.count = 1;
+			rx_bufs[i].buf = sqe->txrx.rx_buf;
+			rx_bufs[i].len = sqe->txrx.buf_len;
+			tx_bufs[i].buf = (uint8_t *)sqe->txrx.tx_buf;
+			tx_bufs[i].len = sqe->txrx.buf_len;
 			break;
 		default:
-			LOG_ERR("Invalid op code %d for submission %p\n", sqe->op, (void *)sqe);
 			err = -EIO;
 			break;
 		}
 
-		if (!err) {
-			struct spi_buf_set *tx_buf_ptr = tx_buf_set.count > 0 ? &tx_buf_set : NULL;
-			struct spi_buf_set *rx_buf_ptr = rx_buf_set.count > 0 ? &rx_buf_set : NULL;
-
-			err = spi_transceive_dt(dt_spec, tx_buf_ptr, rx_buf_ptr);
+		txn_curr = rtio_txn_next(txn_curr);
+	}
 
-			/* NULL if this submission is not a transaction */
-			txn_curr = rtio_txn_next(txn_curr);
-		}
-	} while (err >= 0 && txn_curr != NULL);
+	if (err == 0) {
+		__ASSERT_NO_MSG(num_msgs > 0);
+		err = spi_transceive_dt(dt_spec, &tx_buf_set, &rx_buf_set);
+	}
 
-	if (err < 0) {
-		LOG_ERR("Transfer failed: %d", err);
+	if (err != 0) {
 		rtio_iodev_sqe_err(txn_head, err);
 	} else {
-		LOG_DBG("Transfer OK: %d", err);
-		rtio_iodev_sqe_ok(txn_head, err);
+		rtio_iodev_sqe_ok(txn_head, 0);
 	}
 }
 
diff --git a/drivers/spi/spi_sam0.c b/drivers/spi/spi_sam0.c
index ddf820e5579..6dd2d64fad5 100644
--- a/drivers/spi/spi_sam0.c
+++ b/drivers/spi/spi_sam0.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2017 Google LLC.
+ * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,6 +10,8 @@
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(spi_sam0);
 
+/* clang-format off */
+
 #include "spi_context.h"
 #include <errno.h>
 #include <zephyr/device.h>
@@ -27,14 +30,12 @@ struct spi_sam0_config {
 	SercomSpi *regs;
 	uint32_t pads;
 	const struct pinctrl_dev_config *pcfg;
-#ifdef MCLK
+
 	volatile uint32_t *mclk;
 	uint32_t mclk_mask;
-	uint16_t gclk_core_id;
-#else
-	uint32_t pm_apbcmask;
-	uint16_t gclk_clkctrl_id;
-#endif
+	uint32_t gclk_gen;
+	uint16_t gclk_id;
+
 #ifdef CONFIG_SPI_ASYNC
 	const struct device *dma_dev;
 	uint8_t tx_dma_request;
@@ -645,20 +646,15 @@ static int spi_sam0_init(const struct device *dev)
 	struct spi_sam0_data *data = dev->data;
 	SercomSpi *regs = cfg->regs;
 
-#ifdef MCLK
-	/* Enable the GCLK */
-	GCLK->PCHCTRL[cfg->gclk_core_id].reg = GCLK_PCHCTRL_GEN_GCLK0 |
-					       GCLK_PCHCTRL_CHEN;
-
-	/* Enable the MCLK */
 	*cfg->mclk |= cfg->mclk_mask;
-#else
-	/* Enable the GCLK */
-	GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 |
-			    GCLK_CLKCTRL_CLKEN;
 
-	/* Enable SERCOM clock in PM */
-	PM->APBCMASK.reg |= cfg->pm_apbcmask;
+#ifdef MCLK
+	GCLK->PCHCTRL[cfg->gclk_id].reg = GCLK_PCHCTRL_CHEN
+					| GCLK_PCHCTRL_GEN(cfg->gclk_gen);
+#else
+	GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
+			  | GCLK_CLKCTRL_GEN(cfg->gclk_gen)
+			  | GCLK_CLKCTRL_ID(cfg->gclk_id);
 #endif
 
 	/* Disable all SPI interrupts */
@@ -717,13 +713,17 @@ static DEVICE_API(spi, spi_sam0_driver_api) = {
 	SERCOM_SPI_CTRLA_DIPO(DT_INST_PROP(n, dipo)) | \
 	SERCOM_SPI_CTRLA_DOPO(DT_INST_PROP(n, dopo))
 
+#define ASSIGNED_CLOCKS_CELL_BY_NAME					\
+	ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_NAME
+
 #ifdef MCLK
 #define SPI_SAM0_DEFINE_CONFIG(n)					\
 static const struct spi_sam0_config spi_sam0_config_##n = {		\
 	.regs = (SercomSpi *)DT_INST_REG_ADDR(n),			\
-	.mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(n),	\
-	.mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)),	\
-	.gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),\
+	.gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen),		\
+	.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id),		\
+	.mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n),		\
+	.mclk_mask = ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(n, bit),	\
 	.pads = SPI_SAM0_SERCOM_PADS(n),				\
 	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
 	SPI_SAM0_DMA_CHANNELS(n)					\
@@ -732,8 +732,10 @@ static const struct spi_sam0_config spi_sam0_config_##n = {		\
 #define SPI_SAM0_DEFINE_CONFIG(n)					\
 static const struct spi_sam0_config spi_sam0_config_##n = {		\
 	.regs = (SercomSpi *)DT_INST_REG_ADDR(n),			\
-	.pm_apbcmask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, pm, bit)),	\
-	.gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id),\
+	.gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen),		\
+	.gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id),		\
+	.mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n),		\
+	.mclk_mask = ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(n, bit),	\
 	.pads = SPI_SAM0_SERCOM_PADS(n),				\
 	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
 	SPI_SAM0_DMA_CHANNELS(n)					\
@@ -755,3 +757,5 @@ static const struct spi_sam0_config spi_sam0_config_##n = {		\
 			    &spi_sam0_driver_api);
 
 DT_INST_FOREACH_STATUS_OKAY(SPI_SAM0_DEVICE_INIT)
+
+/* clang-format on */
diff --git a/drivers/spi/spi_sedi.c b/drivers/spi/spi_sedi.c
index 67a682a2beb..ed4c2b5cc01 100644
--- a/drivers/spi/spi_sedi.c
+++ b/drivers/spi/spi_sedi.c
@@ -406,10 +406,10 @@ static int spi_sedi_device_ctrl(const struct device *dev,
 		DEVICE_MMIO_ROM_INIT(DT_DRV_INST(num)),                        \
 		.spi_device = num, .irq_config = spi_##num##_irq_init,         \
 	};								       \
-	PM_DEVICE_DEFINE(spi_##num, spi_sedi_device_ctrl);		       \
+	PM_DEVICE_DT_INST_DEFINE(spi_##num, spi_sedi_device_ctrl);	       \
 	SPI_DEVICE_DT_INST_DEFINE(num,					       \
 			      spi_sedi_init,				       \
-			      PM_DEVICE_GET(spi_##num),		               \
+			      PM_DEVICE_DT_INST_GET(spi_##num),	               \
 			      &spi_##num##_data,			       \
 			      &spi_##num##_config,			       \
 			      POST_KERNEL,				       \
diff --git a/drivers/spi/spi_shell.c b/drivers/spi/spi_shell.c
index 16d97da886d..9ca6bc5bffb 100644
--- a/drivers/spi/spi_shell.c
+++ b/drivers/spi/spi_shell.c
@@ -17,6 +17,10 @@
 #define CONF_ARGV_FREQUENCY (2)
 #define CONF_ARGV_SETTINGS  (3)
 
+#define CS_ARGV_GPIO_DEV    (1)
+#define CS_ARGV_GPIO_PIN    (2)
+#define CS_ARGV_GPIO_FLAGS  (3)
+
 /* Maximum bytes we can write and read at once */
 #define MAX_SPI_BYTES MIN((CONFIG_SHELL_ARGC_MAX - TXRX_ARGV_BYTES), 32)
 
@@ -24,9 +28,14 @@ static struct device *spi_device;
 static struct spi_config config = {.frequency = 1000000,
 				   .operation = SPI_OP_MODE_MASTER | SPI_WORD_SET(8)};
 
+static bool device_is_spi(const struct device *dev)
+{
+	return DEVICE_API_IS(spi, dev);
+}
+
 static void device_name_get(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_lookup(idx, "spi");
+	const struct device *dev = shell_device_filter(idx, device_is_spi);
 
 	entry->syntax = (dev != NULL) ? dev->name : NULL;
 	entry->handler = NULL;
@@ -135,6 +144,41 @@ static int cmd_spi_conf(const struct shell *ctx, size_t argc, char **argv)
 	return 0;
 }
 
+static int cmd_spi_conf_cs(const struct shell *ctx, size_t argc, char **argv)
+{
+	struct device *dev = (struct device *)shell_device_get_binding(argv[CS_ARGV_GPIO_DEV]);
+	char *endptr = NULL;
+
+	if (dev == NULL) {
+		shell_error(ctx, "device %s not found.", argv[CS_ARGV_GPIO_DEV]);
+		return -ENODEV;
+	}
+
+	int pin = strtol(argv[CS_ARGV_GPIO_PIN], &endptr, 10);
+
+	if (endptr == argv[CS_ARGV_GPIO_PIN] || (pin < 0)) {
+		shell_error(ctx, "invalid pin number: %s", argv[CS_ARGV_GPIO_PIN]);
+		return -EINVAL;
+	}
+
+	config.cs.gpio.port = dev;
+	config.cs.gpio.pin = pin;
+
+	/* Include flags if provided */
+	if (argc == (CS_ARGV_GPIO_FLAGS + 1)) {
+		uint32_t flags = strtol(argv[CS_ARGV_GPIO_FLAGS], &endptr, 16);
+
+		if (endptr == argv[CS_ARGV_GPIO_FLAGS]) {
+			shell_error(ctx, "invalid gpio flags: %s", argv[CS_ARGV_GPIO_FLAGS]);
+			return -EINVAL;
+		}
+
+		config.cs.gpio.dt_flags = flags;
+	}
+
+	return 0;
+}
+
 SHELL_STATIC_SUBCMD_SET_CREATE(sub_spi_cmds,
 			       SHELL_CMD_ARG(conf, &dsub_device_name,
 					     "Configure SPI\n"
@@ -146,6 +190,11 @@ SHELL_STATIC_SUBCMD_SET_CREATE(sub_spi_cmds,
 					     "T - SPI_FRAME_FORMAT_TI\n"
 					     "example: spi conf spi1 1000000 ol",
 					     cmd_spi_conf, 3, 1),
+			       SHELL_CMD_ARG(cs, &dsub_device_name,
+					     "Assign CS GPIO to SPI device\n"
+					     "Usage: spi cs <gpio-device> <pin> [<gpio flags>]"
+					     "example: spi conf gpio1 3 0x01",
+					     cmd_spi_conf_cs, 3, 1),
 			       SHELL_CMD_ARG(transceive, NULL,
 					     "Transceive data to and from an SPI device\n"
 					     "Usage: spi transceive <TX byte 1> [<TX byte 2> ...]",
diff --git a/drivers/spi/spi_silabs_eusart.c b/drivers/spi/spi_silabs_eusart.c
new file mode 100644
index 00000000000..71fedef0292
--- /dev/null
+++ b/drivers/spi/spi_silabs_eusart.c
@@ -0,0 +1,772 @@
+/*
+ * Copyright (c) 2024 Daikin Comfort Technologies North America, Inc.
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT silabs_eusart_spi
+
+#include <stdbool.h>
+#include <stddef.h>
+
+#include <zephyr/sys/sys_io.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/device.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/clock_control_silabs.h>
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/dma/dma_silabs_ldma.h>
+#include <zephyr/drivers/dma.h>
+#include <zephyr/pm/device.h>
+#include <zephyr/pm/policy.h>
+#include <zephyr/pm/device_runtime.h>
+#include <em_cmu.h>
+#include <em_eusart.h>
+
+LOG_MODULE_REGISTER(spi_silabs_eusart, CONFIG_SPI_LOG_LEVEL);
+
+/* Required by spi_context.h */
+#include "spi_context.h"
+
+#if defined(CONFIG_SPI_ASYNC) && !defined(CONFIG_SPI_SILABS_EUSART_DMA)
+#warning "Silabs eusart SPI driver ASYNC without DMA is not supported"
+#endif
+
+#define SPI_WORD_SIZE 8
+#ifdef CONFIG_SPI_SILABS_EUSART_DMA
+#define SPI_DMA_MAX_DESCRIPTOR_TRANSFER_SIZE (0x800U)
+
+struct dma_channel {
+	const struct device *dma_dev;
+	uint8_t dma_slot;
+	int chan_nb;
+	struct dma_block_config dma_descriptors[CONFIG_SPI_SILABS_EUSART_DMA_MAX_BLOCKS];
+};
+#endif
+
+struct spi_silabs_eusart_data {
+	struct spi_context ctx;
+#ifdef CONFIG_SPI_SILABS_EUSART_DMA
+	struct dma_channel dma_chan_rx;
+	struct dma_channel dma_chan_tx;
+#endif
+};
+
+struct spi_silabs_eusart_config {
+	EUSART_TypeDef *base;
+	const struct device *clock_dev;
+	const struct silabs_clock_control_cmu_config clock_cfg;
+	uint32_t clock_frequency;
+	const struct pinctrl_dev_config *pcfg;
+	uint8_t mosi_overrun;
+};
+
+#ifdef CONFIG_SPI_SILABS_EUSART_DMA
+static volatile uint8_t empty_buffer;
+#endif
+
+static bool spi_silabs_eusart_is_dma_enabled_instance(const struct device *dev)
+{
+#ifdef CONFIG_SPI_SILABS_EUSART_DMA
+	struct spi_silabs_eusart_data *data = dev->data;
+
+	__ASSERT_NO_MSG(!!data->dma_chan_tx.dma_dev == !!data->dma_chan_rx.dma_dev);
+
+	return data->dma_chan_rx.dma_dev != NULL;
+#else
+	return false;
+#endif
+}
+
+static int spi_silabs_eusart_configure(const struct device *dev, const struct spi_config *config)
+{
+	struct spi_silabs_eusart_data *data = dev->data;
+	const struct spi_silabs_eusart_config *eusart_cfg = dev->config;
+	uint32_t spi_frequency;
+
+	EUSART_SpiAdvancedInit_TypeDef eusartAdvancedSpiInit = EUSART_SPI_ADVANCED_INIT_DEFAULT;
+	EUSART_SpiInit_TypeDef eusartInit = EUSART_SPI_MASTER_INIT_DEFAULT_HF;
+
+	int err;
+
+	if (spi_context_configured(&data->ctx, config)) {
+		/* Already configured. No need to do it again, but must re-enable in case
+		 * TXEN/RXEN were cleared.
+		 */
+		EUSART_Enable(eusart_cfg->base, eusartEnable);
+
+		return 0;
+	}
+
+	err = clock_control_get_rate(eusart_cfg->clock_dev,
+				     (clock_control_subsys_t)&eusart_cfg->clock_cfg,
+				     &spi_frequency);
+	if (err) {
+		return err;
+	}
+	/* Max supported SPI frequency is half the source clock */
+	spi_frequency /= 2;
+
+	if (config->operation & SPI_HALF_DUPLEX) {
+		LOG_ERR("Half-duplex not supported");
+		return -ENOTSUP;
+	}
+
+	if (SPI_WORD_SIZE_GET(config->operation) != SPI_WORD_SIZE) {
+		LOG_ERR("Word size must be %d", SPI_WORD_SIZE);
+		return -ENOTSUP;
+	}
+
+	if (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES) &&
+	    (config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
+		LOG_ERR("Only supports single mode");
+		return -ENOTSUP;
+	}
+
+	if (config->operation & SPI_OP_MODE_SLAVE) {
+		LOG_ERR("Slave mode not supported");
+		return -ENOTSUP;
+	}
+
+	/* Set frequency to the minimum of what the device supports, what the
+	 * user has configured the controller to, and the max frequency for the
+	 * transaction.
+	 */
+	if (eusart_cfg->clock_frequency > spi_frequency) {
+		LOG_ERR("SPI clock-frequency too high");
+		return -EINVAL;
+	}
+	spi_frequency = MIN(eusart_cfg->clock_frequency, spi_frequency);
+	if (config->frequency) {
+		spi_frequency = MIN(config->frequency, spi_frequency);
+	}
+	eusartInit.bitRate = spi_frequency;
+
+	if (config->operation & SPI_MODE_LOOP) {
+		eusartInit.loopbackEnable = eusartLoopbackEnable;
+	} else {
+		eusartInit.loopbackEnable = eusartLoopbackDisable;
+	}
+
+	/* Set Clock Mode */
+	if (config->operation & SPI_MODE_CPOL) {
+		if (config->operation & SPI_MODE_CPHA) {
+			eusartInit.clockMode = eusartClockMode3;
+		} else {
+			eusartInit.clockMode = eusartClockMode2;
+		}
+	} else {
+		if (config->operation & SPI_MODE_CPHA) {
+			eusartInit.clockMode = eusartClockMode1;
+		} else {
+			eusartInit.clockMode = eusartClockMode0;
+		}
+	}
+
+	if (config->operation & SPI_CS_ACTIVE_HIGH) {
+		eusartAdvancedSpiInit.csPolarity = eusartCsActiveHigh;
+	} else {
+		eusartAdvancedSpiInit.csPolarity = eusartCsActiveLow;
+	}
+
+	eusartAdvancedSpiInit.msbFirst = !(config->operation & SPI_TRANSFER_LSB);
+	eusartAdvancedSpiInit.autoCsEnable = !spi_cs_is_gpio(config);
+	eusartInit.databits = eusartDataBits8;
+	eusartInit.advancedSettings = &eusartAdvancedSpiInit;
+
+#ifdef CONFIG_SPI_SILABS_EUSART_DMA
+	if (spi_silabs_eusart_is_dma_enabled_instance(dev)) {
+		if (!device_is_ready(data->dma_chan_tx.dma_dev)) {
+			return -ENODEV;
+		}
+
+		eusartAdvancedSpiInit.TxFifoWatermark = eusartTxFiFoWatermark1Frame;
+		eusartAdvancedSpiInit.RxFifoWatermark = eusartRxFiFoWatermark1Frame;
+
+		if (data->dma_chan_rx.chan_nb < 0) {
+			data->dma_chan_rx.chan_nb =
+				dma_request_channel(data->dma_chan_rx.dma_dev, NULL);
+		}
+
+		if (data->dma_chan_rx.chan_nb < 0) {
+			LOG_ERR("DMA channel request failed");
+			return -EAGAIN;
+		}
+
+		if (data->dma_chan_tx.chan_nb < 0) {
+			data->dma_chan_tx.chan_nb =
+				dma_request_channel(data->dma_chan_tx.dma_dev, NULL);
+		}
+
+		if (data->dma_chan_tx.chan_nb < 0) {
+			dma_release_channel(data->dma_chan_rx.dma_dev, data->dma_chan_rx.chan_nb);
+			data->dma_chan_rx.chan_nb = -1;
+			LOG_ERR("DMA channel request failed");
+			return -EAGAIN;
+		}
+	}
+#endif
+	/* Enable EUSART clock */
+	err = clock_control_on(eusart_cfg->clock_dev,
+			       (clock_control_subsys_t)&eusart_cfg->clock_cfg);
+	if (err < 0 && err != -EALREADY) {
+		goto exit;
+	}
+
+	/* Initialize the EUSART */
+	EUSART_SpiInit(eusart_cfg->base, &eusartInit);
+
+	data->ctx.config = config;
+
+	return 0;
+
+exit:
+#ifdef CONFIG_SPI_SILABS_EUSART_DMA
+	if (spi_silabs_eusart_is_dma_enabled_instance(dev)) {
+		dma_release_channel(data->dma_chan_rx.dma_dev, data->dma_chan_rx.chan_nb);
+		dma_release_channel(data->dma_chan_tx.dma_dev, data->dma_chan_tx.chan_nb);
+		data->dma_chan_rx.chan_nb = -1;
+		data->dma_chan_tx.chan_nb = -1;
+	}
+#endif
+	return err;
+}
+
+static inline void spi_silabs_eusart_pm_policy_get(const struct device *dev)
+{
+	pm_policy_state_lock_get(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
+	pm_policy_state_lock_get(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
+}
+
+static inline void spi_silabs_eusart_pm_policy_put(const struct device *dev)
+{
+	pm_policy_state_lock_put(PM_STATE_SUSPEND_TO_IDLE, PM_ALL_SUBSTATES);
+	pm_policy_state_lock_put(PM_STATE_STANDBY, PM_ALL_SUBSTATES);
+}
+
+static int spi_silabs_eusart_pm_action(const struct device *dev, enum pm_device_action action)
+{
+	const struct spi_silabs_eusart_config *eusart_config = dev->config;
+	int ret;
+
+	switch (action) {
+	case PM_DEVICE_ACTION_RESUME:
+		ret = clock_control_on(eusart_config->clock_dev,
+				       (clock_control_subsys_t)&eusart_config->clock_cfg);
+
+		if (ret == -EALREADY) {
+			ret = 0;
+		} else if (ret < 0) {
+			break;
+		}
+
+		pinctrl_apply_state(eusart_config->pcfg, PINCTRL_STATE_DEFAULT);
+
+		break;
+	case PM_DEVICE_ACTION_SUSPEND:
+		pinctrl_apply_state(eusart_config->pcfg, PINCTRL_STATE_SLEEP);
+
+		EUSART_Enable(eusart_config->base, eusartDisable);
+		ret = clock_control_off(eusart_config->clock_dev,
+					(clock_control_subsys_t)&eusart_config->clock_cfg);
+		if (ret == -EALREADY) {
+			ret = 0;
+		}
+
+		break;
+	default:
+		ret = -ENOTSUP;
+	}
+
+	return ret;
+}
+
+#ifdef CONFIG_SPI_SILABS_EUSART_DMA
+static void spi_silabs_dma_rx_callback(const struct device *dev, void *user_data, uint32_t channel,
+				       int status)
+{
+	const struct device *spi_dev = (const struct device *)user_data;
+	struct spi_silabs_eusart_data *data = spi_dev->data;
+	struct spi_context *instance_ctx = &data->ctx;
+
+	ARG_UNUSED(dev);
+
+	if (status >= 0 && status != DMA_STATUS_COMPLETE) {
+		return;
+	}
+
+	if (status < 0) {
+		dma_stop(data->dma_chan_tx.dma_dev, data->dma_chan_tx.chan_nb);
+		dma_stop(data->dma_chan_rx.dma_dev, data->dma_chan_rx.chan_nb);
+	}
+
+	spi_context_cs_control(instance_ctx, false);
+	spi_silabs_eusart_pm_policy_put(spi_dev);
+	spi_context_complete(instance_ctx, spi_dev, status);
+}
+
+static void spi_silabs_eusart_clear_txrx_fifos(EUSART_TypeDef *eusart)
+{
+	sys_write32(EUSART_CMD_CLEARTX, (mem_addr_t)&eusart->CMD_SET);
+
+	while (sys_read32((mem_addr_t)&eusart->STATUS) & EUSART_STATUS_RXFL) {
+		(void)sys_read32((mem_addr_t)&eusart->RXDATA);
+	}
+
+	while (sys_read32((mem_addr_t)&eusart->STATUS) & EUSART_STATUS_CLEARTXBUSY) {
+	}
+}
+
+static size_t spi_silabs_longest_transfer_size(struct spi_context *instance_ctx)
+{
+	uint32_t tx_transfer_size = spi_context_total_tx_len(instance_ctx);
+	uint32_t rx_transfer_size = spi_context_total_rx_len(instance_ctx);
+
+	return MAX(tx_transfer_size, rx_transfer_size);
+}
+
+static int spi_silabs_dma_config(const struct device *dev,
+				 struct dma_channel *channel,
+				 uint32_t block_count, bool is_tx)
+{
+	struct dma_config cfg = {
+		.channel_direction = is_tx ? MEMORY_TO_PERIPHERAL : PERIPHERAL_TO_MEMORY,
+		.complete_callback_en = 0,
+		.source_data_size = 1,
+		.dest_data_size = 1,
+		.source_burst_length = 1,
+		.dest_burst_length = 1,
+		.block_count = block_count,
+		.head_block = channel->dma_descriptors,
+		.dma_slot = channel->dma_slot,
+		.dma_callback = !is_tx ? &spi_silabs_dma_rx_callback : NULL,
+		.user_data = (void *)dev,
+	};
+
+	return dma_config(channel->dma_dev, channel->chan_nb, &cfg);
+}
+
+static uint32_t spi_eusart_fill_desc(const struct spi_silabs_eusart_config *cfg,
+				     struct dma_block_config *new_blk_cfg, uint8_t *buffer,
+				     size_t requested_transaction_size, bool is_tx)
+{
+	/* Set-up source and destination address with increment behavior */
+	if (is_tx) {
+		new_blk_cfg->dest_address = (uint32_t)&cfg->base->TXDATA;
+		new_blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
+		if (buffer) {
+			new_blk_cfg->source_address = (uint32_t)buffer;
+			new_blk_cfg->source_addr_adj = DMA_ADDR_ADJ_INCREMENT;
+		} else {
+			/* Null buffer pointer means sending dummy byte */
+			new_blk_cfg->source_address = (uint32_t)&(cfg->mosi_overrun);
+			new_blk_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
+		}
+	} else {
+		new_blk_cfg->source_address = (uint32_t)&cfg->base->RXDATA;
+		new_blk_cfg->source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
+		if (buffer) {
+			new_blk_cfg->dest_address = (uint32_t)buffer;
+			new_blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_INCREMENT;
+		} else {
+			/* Null buffer pointer means rx to null byte */
+			new_blk_cfg->dest_address = (uint32_t)&empty_buffer;
+			new_blk_cfg->dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE;
+		}
+	}
+	/* Setup max transfer according to requested transaction size.
+	 * Will top if bigger than the maximum transfer size.
+	 */
+	new_blk_cfg->block_size = MIN(requested_transaction_size,
+				      SPI_DMA_MAX_DESCRIPTOR_TRANSFER_SIZE);
+	return new_blk_cfg->block_size;
+}
+
+struct dma_block_config *spi_eusart_fill_data_desc(const struct spi_silabs_eusart_config *cfg,
+						   struct dma_block_config *desc,
+						   const struct spi_buf buffers[],
+						   int buffer_count,
+						   size_t transaction_len,
+						   bool is_tx)
+{
+	__ASSERT(transaction_len > 0, "Not supported");
+
+	size_t offset = 0;
+	int i = 0;
+	uint8_t *buffer = NULL;
+
+	while (i != buffer_count) {
+		if (!buffers[i].len) {
+			i++;
+			continue;
+		}
+		if (!desc) {
+			return NULL;
+		}
+		buffer = buffers[i].buf ? (uint8_t *)buffers[i].buf + offset : NULL;
+		offset += spi_eusart_fill_desc(cfg, desc,
+					       buffer,
+					       buffers[i].len - offset,
+					       is_tx);
+		if (offset == buffers[i].len) {
+			transaction_len -= offset;
+			offset = 0;
+			i++;
+		}
+		if (transaction_len) {
+			desc = desc->next_block;
+		}
+	}
+
+	while (transaction_len) {
+		if (!desc) {
+			return NULL;
+		}
+
+		transaction_len -= spi_eusart_fill_desc(cfg, desc, NULL, transaction_len, is_tx);
+		if (transaction_len) {
+			desc = desc->next_block;
+		}
+	}
+
+	desc->next_block = NULL;
+	return desc;
+}
+
+static void spi_eusart_reset_desc(struct dma_channel *channel)
+{
+	int i;
+
+	memset(channel->dma_descriptors, 0, sizeof(channel->dma_descriptors));
+	for (i = 0; i < ARRAY_SIZE(channel->dma_descriptors) - 1; i++) {
+		channel->dma_descriptors[i].next_block = &channel->dma_descriptors[i + 1];
+	}
+}
+
+static int spi_eusart_prepare_dma_channel(const struct device *spi_dev,
+					  const struct spi_buf *buffer,
+					  size_t buffer_count,
+					  struct dma_channel *channel,
+					  size_t padded_transaction_size,
+					  bool is_tx)
+{
+	const struct spi_silabs_eusart_config *cfg = spi_dev->config;
+	struct dma_block_config *desc;
+	int ret = 0;
+
+	spi_eusart_reset_desc(channel);
+	desc = spi_eusart_fill_data_desc(cfg, channel->dma_descriptors,
+					 buffer, buffer_count, padded_transaction_size, is_tx);
+	if (!desc) {
+		return -ENOMEM;
+	}
+
+	ret = spi_silabs_dma_config(spi_dev, channel,
+				    ARRAY_INDEX(channel->dma_descriptors, desc),
+				    is_tx);
+
+	return ret;
+}
+
+static int spi_eusart_prepare_dma_transaction(const struct device *dev,
+					      size_t padded_transaction_size)
+{
+	int ret;
+	struct spi_silabs_eusart_data *data = dev->data;
+
+	if (padded_transaction_size == 0) {
+		/* Nothing to do */
+		return 0;
+	}
+
+	ret = spi_eusart_prepare_dma_channel(dev, data->ctx.current_tx, data->ctx.tx_count,
+					     &data->dma_chan_tx, padded_transaction_size,
+					     true);
+	if (ret) {
+		return ret;
+	}
+
+	ret = spi_eusart_prepare_dma_channel(dev, data->ctx.current_rx, data->ctx.rx_count,
+					     &data->dma_chan_rx, padded_transaction_size, false);
+	return ret;
+}
+
+#endif
+
+static void spi_silabs_eusart_send(EUSART_TypeDef *eusart, uint8_t frame)
+{
+	/* Write frame to register */
+	EUSART_Tx(eusart, frame);
+
+	/* Wait until the transfer ends */
+	while (!(eusart->STATUS & EUSART_STATUS_TXC)) {
+	}
+}
+
+static uint8_t spi_silabs_eusart_recv(EUSART_TypeDef *eusart)
+{
+	/* Return data inside rx register */
+	return EUSART_Rx(eusart);
+}
+
+static bool spi_silabs_eusart_transfer_ongoing(struct spi_silabs_eusart_data *data)
+{
+	return spi_context_tx_on(&data->ctx) || spi_context_rx_on(&data->ctx);
+}
+
+static inline uint8_t spi_silabs_eusart_next_tx(struct spi_silabs_eusart_data *data)
+{
+	uint8_t tx_frame = 0;
+
+	if (spi_context_tx_buf_on(&data->ctx)) {
+		tx_frame = UNALIGNED_GET((uint8_t *)(data->ctx.tx_buf));
+	}
+
+	return tx_frame;
+}
+
+static int spi_silabs_eusart_shift_frames(EUSART_TypeDef *eusart,
+					  struct spi_silabs_eusart_data *data)
+{
+	uint8_t tx_frame;
+	uint8_t rx_frame;
+
+	tx_frame = spi_silabs_eusart_next_tx(data);
+	spi_silabs_eusart_send(eusart, tx_frame);
+	spi_context_update_tx(&data->ctx, 1, 1);
+
+	rx_frame = spi_silabs_eusart_recv(eusart);
+
+	if (spi_context_rx_buf_on(&data->ctx)) {
+		UNALIGNED_PUT(rx_frame, (uint8_t *)data->ctx.rx_buf);
+	}
+
+	spi_context_update_rx(&data->ctx, 1, 1);
+
+	return 0;
+}
+
+static int spi_silabs_eusart_xfer_dma(const struct device *dev, const struct spi_config *config)
+{
+#ifdef CONFIG_SPI_SILABS_EUSART_DMA
+	const struct spi_silabs_eusart_config *eusart_config = dev->config;
+	struct spi_silabs_eusart_data *data = dev->data;
+	struct spi_context *ctx = &data->ctx;
+	int ret = 0;
+
+	size_t padded_transaction_size = spi_silabs_longest_transfer_size(ctx);
+
+	if (padded_transaction_size == 0) {
+		return -EINVAL;
+	}
+
+	spi_silabs_eusart_clear_txrx_fifos(eusart_config->base);
+
+	ret = spi_eusart_prepare_dma_transaction(dev, padded_transaction_size);
+	if (ret) {
+		return ret;
+	}
+
+	spi_silabs_eusart_pm_policy_get(dev);
+
+	spi_context_cs_control(ctx, true);
+
+	/* RX channel needs to be ready before TX channel actually starts */
+	ret = dma_start(data->dma_chan_rx.dma_dev, data->dma_chan_rx.chan_nb);
+	if (ret) {
+		goto force_transaction_close;
+	}
+
+	ret = dma_start(data->dma_chan_tx.dma_dev, data->dma_chan_tx.chan_nb);
+	if (ret) {
+
+		goto force_transaction_close;
+	}
+
+	ret = spi_context_wait_for_completion(&data->ctx);
+	if (ret < 0) {
+		goto force_transaction_close;
+	}
+
+	/* Successful transaction. DMA transfer done interrupt ended the transaction. */
+	return 0;
+force_transaction_close:
+	dma_stop(data->dma_chan_rx.dma_dev, data->dma_chan_rx.chan_nb);
+	dma_stop(data->dma_chan_tx.dma_dev, data->dma_chan_tx.chan_nb);
+	spi_context_cs_control(ctx, false);
+	spi_silabs_eusart_pm_policy_put(dev);
+	return ret;
+#else
+	return -ENOTSUP;
+#endif
+}
+
+static int spi_silabs_eusart_xfer_polling(const struct device *dev,
+					  const struct spi_config *config)
+{
+	const struct spi_silabs_eusart_config *eusart_config = dev->config;
+	struct spi_silabs_eusart_data *data = dev->data;
+	struct spi_context *ctx = &data->ctx;
+	int ret;
+
+	spi_silabs_eusart_pm_policy_get(dev);
+	spi_context_cs_control(ctx, true);
+
+	ret = 0;
+	while (!ret && spi_silabs_eusart_transfer_ongoing(data)) {
+		ret = spi_silabs_eusart_shift_frames(eusart_config->base, data);
+	}
+
+	spi_context_cs_control(ctx, false);
+	spi_context_complete(ctx, dev, 0);
+
+	spi_silabs_eusart_pm_policy_put(dev);
+	return ret;
+}
+
+static int spi_silabs_eusart_transceive(const struct device *dev,
+					const struct spi_config *config,
+					const struct spi_buf_set *tx_bufs,
+					const struct spi_buf_set *rx_bufs,
+					bool asynchronous,
+					spi_callback_t cb,
+					void *userdata)
+{
+	struct spi_silabs_eusart_data *data = dev->data;
+	struct spi_context *ctx = &data->ctx;
+	int ret;
+
+	spi_context_lock(ctx, asynchronous, cb, userdata, config);
+
+	ret = spi_silabs_eusart_configure(dev, config);
+	if (ret) {
+		goto out;
+	}
+
+	spi_context_buffers_setup(ctx, tx_bufs, rx_bufs, 1);
+
+	if (spi_silabs_eusart_is_dma_enabled_instance(dev)) {
+		/* DMA transfer handle a/synchronous transfers */
+		ret = spi_silabs_eusart_xfer_dma(dev, config);
+	} else if (!asynchronous) {
+		ret = spi_silabs_eusart_xfer_polling(dev, config);
+	} else {
+		/* Asynchronous transfers without DMA is not implemented,
+		 * please configure the device tree
+		 * instance with the proper DMA configuration.
+		 */
+		ret = -ENOTSUP;
+	}
+
+out:
+	spi_context_release(ctx, ret);
+
+	return ret;
+}
+
+/* API Functions */
+static int spi_silabs_eusart_init(const struct device *dev)
+{
+	struct spi_silabs_eusart_data *data = dev->data;
+	int err;
+
+	err = spi_context_cs_configure_all(&data->ctx);
+	if (err < 0) {
+		return err;
+	}
+
+	spi_context_unlock_unconditionally(&data->ctx);
+
+	return pm_device_driver_init(dev, spi_silabs_eusart_pm_action);
+}
+
+static int spi_silabs_eusart_transceive_sync(const struct device *dev,
+					     const struct spi_config *config,
+					     const struct spi_buf_set *tx_bufs,
+					     const struct spi_buf_set *rx_bufs)
+{
+	return spi_silabs_eusart_transceive(dev,
+					    config,
+					    tx_bufs,
+					    rx_bufs,
+					    false,
+					    NULL,
+					    NULL);
+}
+
+#ifdef CONFIG_SPI_ASYNC
+static int spi_silabs_eusart_transceive_async(const struct device *dev,
+					      const struct spi_config *config,
+					      const struct spi_buf_set *tx_bufs,
+					      const struct spi_buf_set *rx_bufs,
+					      spi_callback_t cb,
+					      void *userdata)
+{
+	return spi_silabs_eusart_transceive(dev, config, tx_bufs, rx_bufs, true, cb, userdata);
+}
+#endif
+
+static int spi_silabs_eusart_release(const struct device *dev, const struct spi_config *config)
+{
+	const struct spi_silabs_eusart_config *eusart_config = dev->config;
+	struct spi_silabs_eusart_data *data = dev->data;
+
+	spi_context_unlock_unconditionally(&data->ctx);
+
+	if (!(eusart_config->base->STATUS & EUSART_STATUS_TXIDLE)) {
+		return -EBUSY;
+	}
+
+	return 0;
+}
+
+/* Device Instantiation */
+static DEVICE_API(spi, spi_silabs_eusart_api) = {
+	.transceive = spi_silabs_eusart_transceive_sync,
+#ifdef CONFIG_SPI_ASYNC
+	.transceive_async = spi_silabs_eusart_transceive_async,
+#endif
+	.release = spi_silabs_eusart_release,
+};
+
+#ifdef CONFIG_SPI_SILABS_EUSART_DMA
+#define SPI_SILABS_EUSART_DMA_CHANNEL_INIT(index, dir)						\
+	.dma_chan_##dir = {									\
+		.chan_nb = -1,									\
+		.dma_dev = DEVICE_DT_GET(DT_INST_DMAS_CTLR_BY_NAME(index, dir)),		\
+		.dma_slot =									\
+			SILABS_LDMA_REQSEL_TO_SLOT(DT_INST_DMAS_CELL_BY_NAME(index, dir, slot)),\
+	},
+#define SPI_SILABS_EUSART_DMA_CHANNEL(index, dir) \
+	COND_CODE_1(DT_INST_NODE_HAS_PROP(index, dmas), \
+		    (SPI_SILABS_EUSART_DMA_CHANNEL_INIT(index, dir)), ())
+#else
+#define SPI_SILABS_EUSART_DMA_CHANNEL(index, dir)
+#endif
+
+#define SPI_INIT(n) \
+	PINCTRL_DT_INST_DEFINE(n); \
+	static struct spi_silabs_eusart_data spi_silabs_eusart_data_##n = { \
+		SPI_CONTEXT_INIT_LOCK(spi_silabs_eusart_data_##n, ctx), \
+		SPI_CONTEXT_INIT_SYNC(spi_silabs_eusart_data_##n, ctx), \
+		SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx) \
+		SPI_SILABS_EUSART_DMA_CHANNEL(n, rx) \
+		SPI_SILABS_EUSART_DMA_CHANNEL(n, tx) \
+	}; \
+	static struct spi_silabs_eusart_config spi_silabs_eusart_cfg_##n = { \
+		.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
+		.base = (EUSART_TypeDef *)DT_INST_REG_ADDR(n), \
+		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
+		.clock_cfg = SILABS_DT_INST_CLOCK_CFG(n), \
+		.mosi_overrun = (uint8_t)SPI_MOSI_OVERRUN_DT(n), \
+		.clock_frequency = DT_INST_PROP_OR(n, clock_frequency, 1000000), \
+	}; \
+	PM_DEVICE_DT_INST_DEFINE(n, spi_silabs_eusart_pm_action); \
+	SPI_DEVICE_DT_INST_DEFINE(n, spi_silabs_eusart_init, PM_DEVICE_DT_INST_GET(n), \
+				  &spi_silabs_eusart_data_##n, &spi_silabs_eusart_cfg_##n, \
+				  POST_KERNEL, CONFIG_SPI_INIT_PRIORITY, &spi_silabs_eusart_api);
+
+DT_INST_FOREACH_STATUS_OKAY(SPI_INIT)
diff --git a/drivers/spi/spi_silabs_usart.c b/drivers/spi/spi_silabs_usart.c
new file mode 100644
index 00000000000..1c7e0365956
--- /dev/null
+++ b/drivers/spi/spi_silabs_usart.c
@@ -0,0 +1,494 @@
+/*
+ * Copyright (c) 2019 Christian Taedcke <hacking@taedcke.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT silabs_usart_spi
+
+#define LOG_LEVEL CONFIG_SPI_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(spi_silabs_usart);
+#include "spi_context.h"
+
+#include <zephyr/sys/sys_io.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/spi.h>
+#include <zephyr/drivers/spi/rtio.h>
+#include <soc.h>
+
+#include "em_cmu.h"
+#include "em_usart.h"
+
+#include <stdbool.h>
+
+#ifdef CONFIG_PINCTRL
+#include <zephyr/drivers/pinctrl.h>
+#else
+#ifndef CONFIG_SOC_GECKO_HAS_INDIVIDUAL_PIN_LOCATION
+#error "Individual pin location support is required"
+#endif
+#endif /* CONFIG_PINCTRL */
+
+#ifdef CONFIG_CLOCK_CONTROL
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/clock_control_silabs.h>
+#define GET_USART_CLOCK(idx)                            \
+	.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(idx)), \
+	.clock_cfg = SILABS_DT_INST_CLOCK_CFG(idx),
+#elif DT_NODE_HAS_PROP(n, peripheral_id)
+#define CLOCK_USART(id) _CONCAT(cmuClock_USART, id)
+#define GET_USART_CLOCK(n) \
+	.clock = CLOCK_USART(DT_INST_PROP(n, peripheral_id)),
+#else
+#if (USART_COUNT == 1)
+#define CLOCK_USART(ref)	(((ref) == USART0) ? cmuClock_USART0 \
+			       : -1)
+#elif (USART_COUNT == 2)
+#define CLOCK_USART(ref)	(((ref) == USART0) ? cmuClock_USART0 \
+			       : ((ref) == USART1) ? cmuClock_USART1 \
+			       : -1)
+#elif (USART_COUNT == 3)
+#define CLOCK_USART(ref)	(((ref) == USART0) ? cmuClock_USART0 \
+			       : ((ref) == USART1) ? cmuClock_USART1 \
+			       : ((ref) == USART2) ? cmuClock_USART2 \
+			       : -1)
+#elif (USART_COUNT == 4)
+#define CLOCK_USART(ref)	(((ref) == USART0) ? cmuClock_USART0 \
+			       : ((ref) == USART1) ? cmuClock_USART1 \
+			       : ((ref) == USART2) ? cmuClock_USART2 \
+			       : ((ref) == USART3) ? cmuClock_USART3 \
+			       : -1)
+#elif (USART_COUNT == 5)
+#define CLOCK_USART(ref)	(((ref) == USART0) ? cmuClock_USART0 \
+			       : ((ref) == USART1) ? cmuClock_USART1 \
+			       : ((ref) == USART2) ? cmuClock_USART2 \
+			       : ((ref) == USART3) ? cmuClock_USART3 \
+			       : ((ref) == USART4) ? cmuClock_USART4 \
+			       : -1)
+#elif (USART_COUNT == 6)
+#define CLOCK_USART(ref)	(((ref) == USART0) ? cmuClock_USART0 \
+			       : ((ref) == USART1) ? cmuClock_USART1 \
+			       : ((ref) == USART2) ? cmuClock_USART2 \
+			       : ((ref) == USART3) ? cmuClock_USART3 \
+			       : ((ref) == USART4) ? cmuClock_USART4 \
+			       : ((ref) == USART5) ? cmuClock_USART5 \
+			       : -1)
+#else
+#error "Undefined number of USARTs."
+#endif /* USART_COUNT */
+#define GET_USART_CLOCK(id) \
+	.clock = CLOCK_USART((USART_TypeDef *)DT_INST_REG_ADDR(id)),
+#endif /* DT_NODE_HAS_PROP(n, peripheral_id) */
+
+
+#define SPI_WORD_SIZE 8
+
+/* Structure Declarations */
+
+struct spi_silabs_usart_data {
+	struct spi_context ctx;
+};
+
+struct spi_silabs_usart_config {
+	USART_TypeDef *base;
+#ifdef CONFIG_CLOCK_CONTROL
+	const struct device *clock_dev;
+	const struct silabs_clock_control_cmu_config clock_cfg;
+#else
+	CMU_Clock_TypeDef clock;
+#endif
+	uint32_t clock_frequency;
+#ifdef CONFIG_PINCTRL
+	const struct pinctrl_dev_config *pcfg;
+#else
+	struct soc_gpio_pin pin_rx;
+	struct soc_gpio_pin pin_tx;
+	struct soc_gpio_pin pin_clk;
+	uint8_t loc_rx;
+	uint8_t loc_tx;
+	uint8_t loc_clk;
+#endif /* CONFIG_PINCTRL */
+};
+
+
+/* Helper Functions */
+static int spi_config(const struct device *dev,
+		      const struct spi_config *config,
+		      uint16_t *control)
+{
+	const struct spi_silabs_usart_config *usart_config = dev->config;
+	struct spi_silabs_usart_data *data = dev->data;
+	mem_addr_t ctrl_reg = (mem_addr_t)&usart_config->base->CTRL;
+	uint32_t spi_frequency;
+
+#ifdef CONFIG_CLOCK_CONTROL
+	int err;
+
+	err = clock_control_get_rate(usart_config->clock_dev,
+				     (clock_control_subsys_t)&usart_config->clock_cfg,
+				     &spi_frequency);
+	if (err) {
+		return err;
+	}
+	/* Max supported SPI frequency is half the source clock */
+	spi_frequency /= 2;
+#else
+	spi_frequency = CMU_ClockFreqGet(usart_config->clock) / 2;
+#endif
+
+	if (config->operation & SPI_HALF_DUPLEX) {
+		LOG_ERR("Half-duplex not supported");
+		return -ENOTSUP;
+	}
+
+	if (SPI_WORD_SIZE_GET(config->operation) != SPI_WORD_SIZE) {
+		LOG_ERR("Word size must be %d", SPI_WORD_SIZE);
+		return -ENOTSUP;
+	}
+
+	if (config->operation & SPI_CS_ACTIVE_HIGH) {
+		sys_set_bit(ctrl_reg, _USART_CTRL_CSINV_SHIFT);
+	} else {
+		sys_clear_bit(ctrl_reg, _USART_CTRL_CSINV_SHIFT);
+	}
+
+	if (IS_ENABLED(CONFIG_SPI_EXTENDED_MODES) &&
+	    (config->operation & SPI_LINES_MASK) != SPI_LINES_SINGLE) {
+		LOG_ERR("Only supports single mode");
+		return -ENOTSUP;
+	}
+
+	if (config->operation & SPI_TRANSFER_LSB) {
+		sys_clear_bit(ctrl_reg, _USART_CTRL_MSBF_SHIFT);
+	} else {
+		sys_set_bit(ctrl_reg, _USART_CTRL_MSBF_SHIFT);
+	}
+
+	if (config->operation & SPI_OP_MODE_SLAVE) {
+		LOG_ERR("Slave mode not supported");
+		return -ENOTSUP;
+	}
+
+	/* Set frequency to the minimum of what the device supports, what the
+	 * user has configured the controller to, and the max frequency for the
+	 * transaction.
+	 */
+	if (usart_config->clock_frequency > spi_frequency) {
+		LOG_ERR("SPI clock-frequency too high");
+		return -EINVAL;
+	}
+	spi_frequency = MIN(usart_config->clock_frequency, spi_frequency);
+	if (config->frequency) {
+		spi_frequency = MIN(config->frequency, spi_frequency);
+	}
+	USART_BaudrateSyncSet(usart_config->base, 0, spi_frequency);
+
+	/* Set Loopback */
+	if (config->operation & SPI_MODE_LOOP) {
+		usart_config->base->CTRL |= USART_CTRL_LOOPBK;
+	} else {
+		usart_config->base->CTRL &= ~USART_CTRL_LOOPBK;
+	}
+
+	/* Set CPOL */
+	if (config->operation & SPI_MODE_CPOL) {
+		usart_config->base->CTRL |= USART_CTRL_CLKPOL;
+	} else {
+		usart_config->base->CTRL &= ~USART_CTRL_CLKPOL;
+	}
+
+	/* Set CPHA */
+	if (config->operation & SPI_MODE_CPHA) {
+		usart_config->base->CTRL |= USART_CTRL_CLKPHA;
+	} else {
+		usart_config->base->CTRL &= ~USART_CTRL_CLKPHA;
+	}
+
+	/* Set word size */
+	usart_config->base->FRAME = usartDatabits8
+	    | USART_FRAME_STOPBITS_DEFAULT
+	    | USART_FRAME_PARITY_DEFAULT;
+
+	/* At this point, it's mandatory to set this on the context! */
+	data->ctx.config = config;
+
+	return 0;
+}
+
+static void spi_silabs_usart_send(USART_TypeDef *usart, uint8_t frame)
+{
+	/* Write frame to register */
+	USART_Tx(usart, frame);
+
+	/* Wait until the transfer ends */
+	while (!(usart->STATUS & USART_STATUS_TXC)) {
+	}
+}
+
+static uint8_t spi_silabs_usart_recv(USART_TypeDef *usart)
+{
+	/* Return data inside rx register */
+	return (uint8_t)usart->RXDATA;
+}
+
+static bool spi_silabs_usart_transfer_ongoing(struct spi_silabs_usart_data *data)
+{
+	return spi_context_tx_on(&data->ctx) || spi_context_rx_on(&data->ctx);
+}
+
+static inline uint8_t spi_silabs_usart_next_tx(struct spi_silabs_usart_data *data)
+{
+	uint8_t tx_frame = 0;
+
+	if (spi_context_tx_buf_on(&data->ctx)) {
+		tx_frame = UNALIGNED_GET((uint8_t *)(data->ctx.tx_buf));
+	}
+
+	return tx_frame;
+}
+
+static int spi_silabs_usart_shift_frames(USART_TypeDef *usart,
+				  struct spi_silabs_usart_data *data)
+{
+	uint8_t tx_frame;
+	uint8_t rx_frame;
+
+	tx_frame = spi_silabs_usart_next_tx(data);
+	spi_silabs_usart_send(usart, tx_frame);
+	spi_context_update_tx(&data->ctx, 1, 1);
+
+	rx_frame = spi_silabs_usart_recv(usart);
+
+	if (spi_context_rx_buf_on(&data->ctx)) {
+		UNALIGNED_PUT(rx_frame, (uint8_t *)data->ctx.rx_buf);
+	}
+	spi_context_update_rx(&data->ctx, 1, 1);
+	return 0;
+}
+
+
+static void spi_silabs_usart_xfer(const struct device *dev,
+			   const struct spi_config *config)
+{
+	int ret;
+	struct spi_silabs_usart_data *data = dev->data;
+	struct spi_context *ctx = &data->ctx;
+	const struct spi_silabs_usart_config *usart_config = dev->config;
+
+	spi_context_cs_control(ctx, true);
+
+	do {
+		ret = spi_silabs_usart_shift_frames(usart_config->base, data);
+	} while (!ret && spi_silabs_usart_transfer_ongoing(data));
+
+	spi_context_cs_control(ctx, false);
+	spi_context_complete(ctx, dev, 0);
+}
+
+#ifndef CONFIG_PINCTRL
+static void spi_silabs_usart_init_pins(const struct device *dev)
+{
+	const struct spi_silabs_usart_config *config = dev->config;
+
+	GPIO_PinModeSet(config->pin_rx.port, config->pin_rx.pin,
+			 config->pin_rx.mode, config->pin_rx.out);
+	GPIO_PinModeSet(config->pin_tx.port, config->pin_tx.pin,
+			 config->pin_tx.mode, config->pin_tx.out);
+	GPIO_PinModeSet(config->pin_clk.port, config->pin_clk.pin,
+			 config->pin_clk.mode, config->pin_clk.out);
+
+	/* disable all pins while configuring */
+	config->base->ROUTEPEN = 0;
+
+	config->base->ROUTELOC0 =
+		(config->loc_tx << _USART_ROUTELOC0_TXLOC_SHIFT) |
+		(config->loc_rx << _USART_ROUTELOC0_RXLOC_SHIFT) |
+		(config->loc_clk << _USART_ROUTELOC0_CLKLOC_SHIFT);
+
+	config->base->ROUTELOC1 = _USART_ROUTELOC1_RESETVALUE;
+
+	config->base->ROUTEPEN = USART_ROUTEPEN_RXPEN | USART_ROUTEPEN_TXPEN |
+		USART_ROUTEPEN_CLKPEN;
+}
+#endif /* !CONFIG_PINCTRL */
+
+
+/* API Functions */
+
+static int spi_silabs_usart_init(const struct device *dev)
+{
+	int err;
+	const struct spi_silabs_usart_config *config = dev->config;
+	struct spi_silabs_usart_data *data = dev->data;
+	USART_InitSync_TypeDef usartInit = USART_INITSYNC_DEFAULT;
+
+	/* The peripheral and gpio clock are already enabled from soc and gpio
+	 * driver
+	 */
+
+	usartInit.enable = usartDisable;
+	usartInit.baudrate = 1000000;
+	usartInit.databits = usartDatabits8;
+	usartInit.master = 1;
+	usartInit.msbf = 1;
+	usartInit.clockMode = usartClockMode0;
+#if defined(USART_INPUT_RXPRS) && defined(USART_TRIGCTRL_AUTOTXTEN)
+	usartInit.prsRxEnable = 0;
+	usartInit.prsRxCh = 0;
+	usartInit.autoTx = 0;
+#endif
+
+	/* Enable USART clock */
+#ifdef CONFIG_CLOCK_CONTROL
+	err = clock_control_on(config->clock_dev, (clock_control_subsys_t)&config->clock_cfg);
+	if (err < 0) {
+		return err;
+	}
+#else
+	CMU_ClockEnable(config->clock, true);
+#endif
+
+	/* Init USART */
+	USART_InitSync(config->base, &usartInit);
+
+#ifdef CONFIG_PINCTRL
+	err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+	if (err < 0) {
+		return err;
+	}
+#else
+	/* Initialize USART pins */
+	spi_silabs_usart_init_pins(dev);
+#endif /* CONFIG_PINCTRL */
+
+	err = spi_context_cs_configure_all(&data->ctx);
+	if (err < 0) {
+		return err;
+	}
+
+	/* Enable the peripheral */
+	config->base->CMD = (uint32_t) usartEnable;
+
+	spi_context_unlock_unconditionally(&data->ctx);
+
+	return 0;
+}
+
+static int spi_silabs_usart_transceive(const struct device *dev,
+				const struct spi_config *config,
+				const struct spi_buf_set *tx_bufs,
+				const struct spi_buf_set *rx_bufs)
+{
+	struct spi_silabs_usart_data *data = dev->data;
+	uint16_t control = 0;
+	int ret;
+
+	spi_context_lock(&data->ctx, false, NULL, NULL, config);
+
+	ret = spi_config(dev, config, &control);
+	if (ret < 0) {
+		spi_context_release(&data->ctx, ret);
+		return ret;
+	}
+
+	spi_context_buffers_setup(&data->ctx, tx_bufs, rx_bufs, 1);
+	spi_silabs_usart_xfer(dev, config);
+
+	spi_context_release(&data->ctx, ret);
+
+	return 0;
+}
+
+#ifdef CONFIG_SPI_ASYNC
+static int spi_silabs_usart_transceive_async(const struct device *dev,
+				      const struct spi_config *config,
+				      const struct spi_buf_set *tx_bufs,
+				      const struct spi_buf_set *rx_bufs,
+				      struct k_poll_signal *async)
+{
+	return -ENOTSUP;
+}
+#endif /* CONFIG_SPI_ASYNC */
+
+static int spi_silabs_usart_release(const struct device *dev,
+			     const struct spi_config *config)
+{
+	struct spi_silabs_usart_data *data = dev->data;
+
+	spi_context_unlock_unconditionally(&data->ctx);
+
+	return 0;
+}
+
+/* Device Instantiation */
+static DEVICE_API(spi, spi_silabs_usart_api) = {
+	.transceive = spi_silabs_usart_transceive,
+#ifdef CONFIG_SPI_ASYNC
+	.transceive_async = spi_silabs_usart_transceive_async,
+#endif /* CONFIG_SPI_ASYNC */
+#ifdef CONFIG_SPI_RTIO
+	.iodev_submit = spi_rtio_iodev_default_submit,
+#endif
+	.release = spi_silabs_usart_release,
+};
+
+#ifdef CONFIG_PINCTRL
+#define SPI_INIT(n)				    \
+	PINCTRL_DT_INST_DEFINE(n);			    \
+	static struct spi_silabs_usart_data spi_silabs_usart_data_##n = { \
+		SPI_CONTEXT_INIT_LOCK(spi_silabs_usart_data_##n, ctx), \
+		SPI_CONTEXT_INIT_SYNC(spi_silabs_usart_data_##n, ctx), \
+		SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx)	\
+	}; \
+	static struct spi_silabs_usart_config spi_silabs_usart_cfg_##n = { \
+	    .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
+	    .base = (USART_TypeDef *) \
+		 DT_INST_REG_ADDR(n), \
+	    GET_USART_CLOCK(n) \
+	    .clock_frequency = DT_INST_PROP_OR(n, clock_frequency, 1000000) \
+	}; \
+	SPI_DEVICE_DT_INST_DEFINE(n, \
+			spi_silabs_usart_init, \
+			NULL, \
+			&spi_silabs_usart_data_##n, \
+			&spi_silabs_usart_cfg_##n, \
+			POST_KERNEL, \
+			CONFIG_SPI_INIT_PRIORITY, \
+			&spi_silabs_usart_api);
+#else
+#define SPI_INIT(n)				    \
+	static struct spi_silabs_usart_data spi_silabs_usart_data_##n = { \
+		SPI_CONTEXT_INIT_LOCK(spi_silabs_usart_data_##n, ctx), \
+		SPI_CONTEXT_INIT_SYNC(spi_silabs_usart_data_##n, ctx), \
+		SPI_CONTEXT_CS_GPIOS_INITIALIZE(DT_DRV_INST(n), ctx)	\
+	}; \
+	static struct spi_silabs_usart_config spi_silabs_usart_cfg_##n = { \
+	    .base = (USART_TypeDef *) \
+		 DT_INST_REG_ADDR(n), \
+	    GET_USART_CLOCK(n) \
+	    .clock_frequency = DT_INST_PROP_OR(n, clock_frequency, 1000000), \
+	    .pin_rx = { DT_INST_PROP_BY_IDX(n, location_rx, 1), \
+			DT_INST_PROP_BY_IDX(n, location_rx, 2), \
+			gpioModeInput, 1},				\
+	    .pin_tx = { DT_INST_PROP_BY_IDX(n, location_tx, 1), \
+			DT_INST_PROP_BY_IDX(n, location_tx, 2), \
+			gpioModePushPull, 1},				\
+	    .pin_clk = { DT_INST_PROP_BY_IDX(n, location_clk, 1), \
+			DT_INST_PROP_BY_IDX(n, location_clk, 2), \
+			gpioModePushPull, 1},				\
+	    .loc_rx = DT_INST_PROP_BY_IDX(n, location_rx, 0), \
+	    .loc_tx = DT_INST_PROP_BY_IDX(n, location_tx, 0), \
+	    .loc_clk = DT_INST_PROP_BY_IDX(n, location_clk, 0), \
+	}; \
+	SPI_DEVICE_DT_INST_DEFINE(n, \
+			spi_silabs_usart_init, \
+			NULL, \
+			&spi_silabs_usart_data_##n, \
+			&spi_silabs_usart_cfg_##n, \
+			POST_KERNEL, \
+			CONFIG_SPI_INIT_PRIORITY, \
+			&spi_silabs_usart_api);
+#endif /* CONFIG_PINCTRL */
+
+DT_INST_FOREACH_STATUS_OKAY(SPI_INIT)
diff --git a/drivers/spi/spi_xmc4xxx.c b/drivers/spi/spi_xmc4xxx.c
index 7d48c5caced..0a7a036dc50 100644
--- a/drivers/spi/spi_xmc4xxx.c
+++ b/drivers/spi/spi_xmc4xxx.c
@@ -23,6 +23,7 @@ LOG_MODULE_REGISTER(spi_xmc4xxx);
 #define USIC_IRQ_MIN  84
 #define USIC_IRQ_MAX  101
 #define IRQS_PER_USIC 6
+#define CLOCK_POLARITY_CHANGE_DELAY 10
 
 #define SPI_XMC4XXX_DMA_ERROR_FLAG   BIT(0)
 #define SPI_XMC4XXX_DMA_RX_DONE_FLAG BIT(1)
@@ -189,6 +190,7 @@ static void spi_xmc4xxx_isr(const struct device *dev)
 static int spi_xmc4xxx_configure(const struct device *dev, const struct spi_config *spi_cfg)
 {
 	int ret;
+	bool clock_polarity_delay = false;
 	struct spi_xmc4xxx_data *data = dev->data;
 	const struct spi_xmc4xxx_config *config = dev->config;
 	struct spi_context *ctx = &data->ctx;
@@ -203,6 +205,11 @@ static int spi_xmc4xxx_configure(const struct device *dev, const struct spi_conf
 		return 0;
 	}
 
+	if (ctx->config == NULL ||
+	    ((SPI_MODE_GET(ctx->config->operation) & SPI_MODE_CPOL) != CPOL)) {
+		clock_polarity_delay = true;
+	}
+
 	ctx->config = spi_cfg;
 
 	if (spi_cfg->operation & SPI_HALF_DUPLEX) {
@@ -253,6 +260,10 @@ static int spi_xmc4xxx_configure(const struct device *dev, const struct spi_conf
 
 	XMC_SPI_CH_SetWordLength(config->spi, 8);
 
+	if (clock_polarity_delay) {
+		k_busy_wait(CLOCK_POLARITY_CHANGE_DELAY);
+	}
+
 	return 0;
 }
 
diff --git a/drivers/stepper/CMakeLists.txt b/drivers/stepper/CMakeLists.txt
index 7f135001497..1cda468fac4 100644
--- a/drivers/stepper/CMakeLists.txt
+++ b/drivers/stepper/CMakeLists.txt
@@ -5,6 +5,7 @@ zephyr_syscall_header(${ZEPHYR_BASE}/include/zephyr/drivers/stepper.h)
 
 # zephyr-keep-sorted-start
 add_subdirectory_ifdef(CONFIG_STEPPER_ADI_TMC adi_tmc)
+add_subdirectory_ifdef(CONFIG_STEPPER_ALLEGRO allegro)
 add_subdirectory_ifdef(CONFIG_STEPPER_TI ti)
 add_subdirectory_ifdef(CONFIG_STEP_DIR_STEPPER step_dir)
 # zephyr-keep-sorted-stop
diff --git a/drivers/stepper/Kconfig b/drivers/stepper/Kconfig
index f8dd4a43b1b..075c9130e33 100644
--- a/drivers/stepper/Kconfig
+++ b/drivers/stepper/Kconfig
@@ -34,6 +34,7 @@ comment "Stepper Drivers"
 rsource "Kconfig.fake"
 rsource "Kconfig.gpio"
 rsource "adi_tmc/Kconfig"
+rsource "allegro/Kconfig"
 rsource "ti/Kconfig"
 # zephyr-keep-sorted-stop
 
diff --git a/drivers/stepper/Kconfig.gpio b/drivers/stepper/Kconfig.gpio
index 99e35057895..4b43140cd28 100644
--- a/drivers/stepper/Kconfig.gpio
+++ b/drivers/stepper/Kconfig.gpio
@@ -2,13 +2,7 @@
 # SPDX-FileCopyrightText: Copyright (c) 2024 Jilay Sandeep Pandya
 # SPDX-License-Identifier: Apache-2.0
 
-menu "GPIO stepper driver"
-
 config GPIO_STEPPER
 	bool "Activate driver for gpio stepper control"
 	depends on DT_HAS_ZEPHYR_GPIO_STEPPER_ENABLED
 	default y
-	help
-	  GPIO Stepper driver for stepper motor control with darlington arrays or dual H-bridge.
-
-endmenu
diff --git a/drivers/stepper/adi_tmc/CMakeLists.txt b/drivers/stepper/adi_tmc/CMakeLists.txt
index c302952f5ad..c16479183f7 100644
--- a/drivers/stepper/adi_tmc/CMakeLists.txt
+++ b/drivers/stepper/adi_tmc/CMakeLists.txt
@@ -5,5 +5,6 @@ zephyr_library()
 zephyr_library_property(ALLOW_EMPTY TRUE)
 
 zephyr_library_sources_ifdef(CONFIG_STEPPER_ADI_TMC_SPI adi_tmc_spi.c)
-zephyr_library_sources_ifdef(CONFIG_STEPPER_ADI_TMC2209 adi_tmc22xx_stepper_controller.c)
-zephyr_library_sources_ifdef(CONFIG_STEPPER_ADI_TMC5041 adi_tmc5041_stepper_controller.c)
+zephyr_library_sources_ifdef(CONFIG_STEPPER_ADI_TMC2209 tmc22xx.c)
+zephyr_library_sources_ifdef(CONFIG_STEPPER_ADI_TMC50XX tmc50xx.c)
+zephyr_library_sources_ifdef(CONFIG_STEPPER_ADI_TMC51XX tmc51xx.c)
diff --git a/drivers/stepper/adi_tmc/Kconfig b/drivers/stepper/adi_tmc/Kconfig
index 51060a5d469..e8a86e6a439 100644
--- a/drivers/stepper/adi_tmc/Kconfig
+++ b/drivers/stepper/adi_tmc/Kconfig
@@ -20,6 +20,7 @@ config STEPPER_ADI_TMC_SPI
 comment "Trinamic Stepper Drivers"
 
 rsource "Kconfig.tmc22xx"
-rsource "Kconfig.tmc5041"
+rsource "Kconfig.tmc50xx"
+rsource "Kconfig.tmc51xx"
 
 endif # STEPPER_ADI_TMC
diff --git a/drivers/stepper/adi_tmc/Kconfig.tmc5041 b/drivers/stepper/adi_tmc/Kconfig.tmc5041
deleted file mode 100644
index e6f01ebb1ae..00000000000
--- a/drivers/stepper/adi_tmc/Kconfig.tmc5041
+++ /dev/null
@@ -1,14 +0,0 @@
-# SPDX-FileCopyrightText: Copyright (c) 2024 Fabian Blatz <fabianblatz@gmail.com>
-# SPDX-License-Identifier: Apache-2.0
-
-config STEPPER_ADI_TMC5041
-	bool "Activate trinamic tmc5041 stepper driver"
-	depends on DT_HAS_ADI_TMC5041_ENABLED && STEPPER_ADI_TMC
-	select STEPPER_ADI_TMC_SPI
-	default y
-	help
-	  Stepper driver for TMC5041.
-
-module = TMC5041
-module-str = tmc5041
-rsource "Kconfig.tmc_rampgen_template"
diff --git a/drivers/stepper/adi_tmc/Kconfig.tmc50xx b/drivers/stepper/adi_tmc/Kconfig.tmc50xx
new file mode 100644
index 00000000000..eeb17293456
--- /dev/null
+++ b/drivers/stepper/adi_tmc/Kconfig.tmc50xx
@@ -0,0 +1,13 @@
+# SPDX-FileCopyrightText: Copyright (c) 2024 Fabian Blatz <fabianblatz@gmail.com>
+# SPDX-FileCopyrightText: Copyright (c) 2025 Jilay Sandeep Pandya
+# SPDX-License-Identifier: Apache-2.0
+
+config STEPPER_ADI_TMC50XX
+	bool "Activate trinamic tmc50xx stepper driver"
+	depends on DT_HAS_ADI_TMC50XX_ENABLED && STEPPER_ADI_TMC
+	select STEPPER_ADI_TMC_SPI
+	default y
+
+module = TMC50XX
+module-str = tmc50xx
+rsource "Kconfig.tmc_rampgen_template"
diff --git a/drivers/stepper/adi_tmc/Kconfig.tmc51xx b/drivers/stepper/adi_tmc/Kconfig.tmc51xx
new file mode 100644
index 00000000000..99e88ac1143
--- /dev/null
+++ b/drivers/stepper/adi_tmc/Kconfig.tmc51xx
@@ -0,0 +1,12 @@
+# SPDX-FileCopyrightText: Copyright (c) 2025 Prevas A/S
+# SPDX-License-Identifier: Apache-2.0
+
+config STEPPER_ADI_TMC51XX
+	bool "Activate trinamic tmc51xx stepper driver"
+	depends on DT_HAS_ADI_TMC51XX_ENABLED && STEPPER_ADI_TMC
+	select STEPPER_ADI_TMC_SPI
+	default y
+
+module = TMC51XX
+module-str = tmc51xx
+rsource "Kconfig.tmc_rampgen_template"
diff --git a/drivers/stepper/adi_tmc/Kconfig.tmc_rampgen_template b/drivers/stepper/adi_tmc/Kconfig.tmc_rampgen_template
index 34064f73b22..4636ac5c76e 100644
--- a/drivers/stepper/adi_tmc/Kconfig.tmc_rampgen_template
+++ b/drivers/stepper/adi_tmc/Kconfig.tmc_rampgen_template
@@ -19,9 +19,16 @@ config STEPPER_ADI_$(module)_RAMPSTAT_POLL_INTERVAL_IN_MSEC
 	help
 	  The interval in ms to poll the ramp status on TMC.
 
+config STEPPER_ADI_$(module)_RAMPSTAT_POLL_STALLGUARD_LOG
+	bool "log $(module-str) stallguard"
+	depends on STEPPER_ADI_$(module)_RAMPSTAT_POLL
+	default n
+	help
+	  Enable stallguard log while polling rampstat.
+
 config STEPPER_ADI_$(module)_RAMP_GEN
 	bool "Use $(module-str) with Ramp Generator"
 	depends on STEPPER_ADI_$(module)
 	default y
 	help
-	  Enable ramp generator for trinamic stepper controller
+	  Enable ramp generator for trinamic stepper controller.
diff --git a/drivers/stepper/adi_tmc/adi_tmc22xx_stepper_controller.c b/drivers/stepper/adi_tmc/adi_tmc22xx_stepper_controller.c
deleted file mode 100644
index f93cb6efd18..00000000000
--- a/drivers/stepper/adi_tmc/adi_tmc22xx_stepper_controller.c
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2024 Fabian Blatz <fabianblatz@gmail.com>
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "../step_dir/step_dir_stepper_common.h"
-
-#include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(tmc22xx, CONFIG_STEPPER_LOG_LEVEL);
-
-#define MSX_PIN_COUNT       2
-#define MSX_PIN_STATE_COUNT 4
-
-struct tmc22xx_config {
-	struct step_dir_stepper_common_config common;
-	const struct gpio_dt_spec enable_pin;
-	const struct gpio_dt_spec *msx_pins;
-	enum stepper_micro_step_resolution *msx_resolutions;
-};
-
-struct tmc22xx_data {
-	struct step_dir_stepper_common_data common;
-	enum stepper_micro_step_resolution resolution;
-};
-
-STEP_DIR_STEPPER_STRUCT_CHECK(struct tmc22xx_config, struct tmc22xx_data);
-
-static int tmc22xx_stepper_enable(const struct device *dev, const bool enable)
-{
-	const struct tmc22xx_config *config = dev->config;
-
-	LOG_DBG("Stepper motor controller %s %s", dev->name, enable ? "enabled" : "disabled");
-	if (enable) {
-		return gpio_pin_set_dt(&config->enable_pin, 1);
-	} else {
-		return gpio_pin_set_dt(&config->enable_pin, 0);
-	}
-}
-
-static int tmc22xx_stepper_set_micro_step_res(const struct device *dev,
-					      enum stepper_micro_step_resolution micro_step_res)
-{
-	struct tmc22xx_data *data = dev->data;
-	const struct tmc22xx_config *config = dev->config;
-	int ret;
-
-	if (!config->msx_pins) {
-		LOG_ERR("Microstep resolution pins are not configured");
-		return -ENODEV;
-	}
-
-	for (uint8_t i = 0; i < MSX_PIN_STATE_COUNT; i++) {
-		if (micro_step_res != config->msx_resolutions[i]) {
-			continue;
-		}
-
-		ret = gpio_pin_set_dt(&config->msx_pins[0], i & 0x01);
-		if (ret < 0) {
-			LOG_ERR("Failed to set MS1 pin: %d", ret);
-			return ret;
-		}
-
-		ret = gpio_pin_set_dt(&config->msx_pins[1], (i & 0x02) >> 1);
-		if (ret < 0) {
-			LOG_ERR("Failed to set MS2 pin: %d", ret);
-			return ret;
-		}
-
-		data->resolution = micro_step_res;
-		return 0;
-	}
-
-	LOG_ERR("Unsupported microstep resolution: %d", micro_step_res);
-	return -EINVAL;
-}
-
-static int tmc22xx_stepper_get_micro_step_res(const struct device *dev,
-					      enum stepper_micro_step_resolution *micro_step_res)
-{
-	struct tmc22xx_data *data = dev->data;
-
-	*micro_step_res = data->resolution;
-	return 0;
-}
-
-static int tmc22xx_stepper_configure_msx_pins(const struct device *dev)
-{
-	const struct tmc22xx_config *config = dev->config;
-	int ret;
-
-	for (uint8_t i = 0; i < MSX_PIN_COUNT; i++) {
-		if (!gpio_is_ready_dt(&config->msx_pins[i])) {
-			LOG_ERR("MSX pin %u are not ready", i);
-			return -ENODEV;
-		}
-
-		ret = gpio_pin_configure_dt(&config->msx_pins[i], GPIO_OUTPUT);
-		if (ret < 0) {
-			LOG_ERR("Failed to configure msx pin %u", i);
-			return ret;
-		}
-	}
-	return 0;
-}
-
-static int tmc22xx_stepper_init(const struct device *dev)
-{
-	const struct tmc22xx_config *config = dev->config;
-	struct tmc22xx_data *data = dev->data;
-	int ret;
-
-	if (!gpio_is_ready_dt(&config->enable_pin)) {
-		LOG_ERR("GPIO pins are not ready");
-		return -ENODEV;
-	}
-
-	ret = gpio_pin_configure_dt(&config->enable_pin, GPIO_OUTPUT);
-	if (ret < 0) {
-		LOG_ERR("Failed to configure enable pin: %d", ret);
-		return ret;
-	}
-
-	if (config->msx_pins) {
-		ret = tmc22xx_stepper_configure_msx_pins(dev);
-		if (ret < 0) {
-			LOG_ERR("Failed to configure MSX pins: %d", ret);
-			return ret;
-		}
-
-		ret = tmc22xx_stepper_set_micro_step_res(dev, data->resolution);
-		if (ret < 0) {
-			LOG_ERR("Failed to set microstep resolution: %d", ret);
-			return ret;
-		}
-	}
-
-	ret = step_dir_stepper_common_init(dev);
-	if (ret < 0) {
-		LOG_ERR("Failed to init step dir common stepper: %d", ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-static DEVICE_API(stepper, tmc22xx_stepper_api) = {
-	.enable = tmc22xx_stepper_enable,
-	.move_by = step_dir_stepper_common_move_by,
-	.is_moving = step_dir_stepper_common_is_moving,
-	.set_reference_position = step_dir_stepper_common_set_reference_position,
-	.get_actual_position = step_dir_stepper_common_get_actual_position,
-	.move_to = step_dir_stepper_common_move_to,
-	.set_max_velocity = step_dir_stepper_common_set_max_velocity,
-	.run = step_dir_stepper_common_run,
-	.set_event_callback = step_dir_stepper_common_set_event_callback,
-	.set_micro_step_res = tmc22xx_stepper_set_micro_step_res,
-	.get_micro_step_res = tmc22xx_stepper_get_micro_step_res,
-};
-
-#define TMC22XX_STEPPER_DEFINE(inst, msx_table)                                                    \
-	IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, msx_gpios), (                                       \
-	static const struct gpio_dt_spec tmc22xx_stepper_msx_pins_##inst[] = {                     \
-		DT_INST_FOREACH_PROP_ELEM_SEP(                                                     \
-			inst, msx_gpios, GPIO_DT_SPEC_GET_BY_IDX, (,)                              \
-		),                                                                                 \
-	};                                                                                         \
-	BUILD_ASSERT(                                                                              \
-		ARRAY_SIZE(tmc22xx_stepper_msx_pins_##inst) == MSX_PIN_COUNT,                      \
-		"Two microstep config pins needed");                                               \
-	))                                                                                         \
-                                                                                                   \
-	static const struct tmc22xx_config tmc22xx_config_##inst = {                               \
-		.common = STEP_DIR_STEPPER_DT_INST_COMMON_CONFIG_INIT(inst),                       \
-		.enable_pin = GPIO_DT_SPEC_INST_GET(inst, en_gpios),	                           \
-		.msx_resolutions = msx_table,                                                      \
-		IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, msx_gpios),				   \
-		(.msx_pins = tmc22xx_stepper_msx_pins_##inst))					   \
-	};                                                                                         \
-	static struct tmc22xx_data tmc22xx_data_##inst = {                                         \
-		.common = STEP_DIR_STEPPER_DT_INST_COMMON_DATA_INIT(inst),                         \
-		.resolution = DT_INST_PROP(inst, micro_step_res),                                  \
-	};                                                                                         \
-	DEVICE_DT_INST_DEFINE(inst, tmc22xx_stepper_init, NULL, &tmc22xx_data_##inst,              \
-			      &tmc22xx_config_##inst, POST_KERNEL, CONFIG_STEPPER_INIT_PRIORITY,   \
-			      &tmc22xx_stepper_api);
-
-#define DT_DRV_COMPAT adi_tmc2209
-static enum stepper_micro_step_resolution tmc2209_msx_resolutions[MSX_PIN_STATE_COUNT] = {
-	STEPPER_MICRO_STEP_8,
-	STEPPER_MICRO_STEP_32,
-	STEPPER_MICRO_STEP_64,
-	STEPPER_MICRO_STEP_16,
-};
-DT_INST_FOREACH_STATUS_OKAY_VARGS(TMC22XX_STEPPER_DEFINE, tmc2209_msx_resolutions)
-#undef DT_DRV_COMPAT
diff --git a/drivers/stepper/adi_tmc/adi_tmc5041_stepper_controller.c b/drivers/stepper/adi_tmc/adi_tmc5041_stepper_controller.c
deleted file mode 100644
index fd89e99c0c2..00000000000
--- a/drivers/stepper/adi_tmc/adi_tmc5041_stepper_controller.c
+++ /dev/null
@@ -1,763 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2024 Carl Zeiss Meditec AG
- * SPDX-FileCopyrightText: Copyright (c) 2024 Jilay Sandeep Pandya
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DT_DRV_COMPAT adi_tmc5041
-
-#include <stdlib.h>
-
-#include <zephyr/drivers/stepper.h>
-#include <zephyr/drivers/stepper/stepper_trinamic.h>
-
-#include "adi_tmc_spi.h"
-#include "adi_tmc5xxx_common.h"
-
-#include <zephyr/logging/log.h>
-
-LOG_MODULE_REGISTER(tmc5041, CONFIG_STEPPER_LOG_LEVEL);
-
-struct tmc5041_data {
-	struct k_sem sem;
-};
-
-struct tmc5041_config {
-	const uint32_t gconf;
-	struct spi_dt_spec spi;
-	const uint32_t clock_frequency;
-};
-
-struct tmc5041_stepper_data {
-	struct k_work_delayable stallguard_dwork;
-	/* Work item to run the callback in a thread context. */
-#ifdef CONFIG_STEPPER_ADI_TMC5041_RAMPSTAT_POLL
-	struct k_work_delayable rampstat_callback_dwork;
-#endif
-	/* device pointer required to access config in k_work */
-	const struct device *stepper;
-	stepper_event_callback_t callback;
-	void *event_cb_user_data;
-};
-
-struct tmc5041_stepper_config {
-	const uint8_t index;
-	const uint16_t default_micro_step_res;
-	const int8_t sg_threshold;
-	const bool is_sg_enabled;
-	const uint32_t sg_velocity_check_interval_ms;
-	const uint32_t sg_threshold_velocity;
-	/* parent controller required for bus communication */
-	const struct device *controller;
-#ifdef CONFIG_STEPPER_ADI_TMC5041_RAMP_GEN
-	const struct tmc_ramp_generator_data default_ramp_config;
-#endif
-};
-
-static int tmc5041_write(const struct device *dev, const uint8_t reg_addr, const uint32_t reg_val)
-{
-	const struct tmc5041_config *config = dev->config;
-	struct tmc5041_data *data = dev->data;
-	const struct spi_dt_spec bus = config->spi;
-	int err;
-
-	k_sem_take(&data->sem, K_FOREVER);
-
-	err = tmc_spi_write_register(&bus, TMC5XXX_WRITE_BIT, reg_addr, reg_val);
-
-	k_sem_give(&data->sem);
-
-	if (err) {
-		LOG_ERR("Failed to write register 0x%x with value 0x%x", reg_addr, reg_val);
-		return err;
-	}
-	return 0;
-}
-
-static int tmc5041_read(const struct device *dev, const uint8_t reg_addr, uint32_t *reg_val)
-{
-	const struct tmc5041_config *config = dev->config;
-	struct tmc5041_data *data = dev->data;
-	const struct spi_dt_spec bus = config->spi;
-	int err;
-
-	k_sem_take(&data->sem, K_FOREVER);
-
-	err = tmc_spi_read_register(&bus, TMC5XXX_ADDRESS_MASK, reg_addr, reg_val);
-
-	k_sem_give(&data->sem);
-
-	if (err) {
-		LOG_ERR("Failed to read register 0x%x", reg_addr);
-		return err;
-	}
-	return 0;
-}
-
-static int tmc5041_stepper_set_event_callback(const struct device *dev,
-					      stepper_event_callback_t callback, void *user_data)
-{
-	struct tmc5041_stepper_data *data = dev->data;
-
-	data->callback = callback;
-	data->event_cb_user_data = user_data;
-	return 0;
-}
-
-static int stallguard_enable(const struct device *dev, const bool enable)
-{
-	const struct tmc5041_stepper_config *config = dev->config;
-	uint32_t reg_value;
-	int err;
-
-	err = tmc5041_read(config->controller, TMC5041_SWMODE(config->index), &reg_value);
-	if (err) {
-		LOG_ERR("Failed to read SWMODE register");
-		return -EIO;
-	}
-
-	if (enable) {
-		reg_value |= TMC5XXX_SW_MODE_SG_STOP_ENABLE;
-
-		int32_t actual_velocity;
-
-		err = tmc5041_read(config->controller, TMC5041_VACTUAL(config->index),
-				   &actual_velocity);
-		if (err) {
-			LOG_ERR("Failed to read VACTUAL register");
-			return -EIO;
-		}
-
-		actual_velocity = (actual_velocity << (31 - TMC_RAMP_VACTUAL_SHIFT)) >>
-				  (31 - TMC_RAMP_VACTUAL_SHIFT);
-		LOG_DBG("actual velocity: %d", actual_velocity);
-
-		if (abs(actual_velocity) < config->sg_threshold_velocity) {
-			return -EAGAIN;
-		}
-	} else {
-		reg_value &= ~TMC5XXX_SW_MODE_SG_STOP_ENABLE;
-	}
-	err = tmc5041_write(config->controller, TMC5041_SWMODE(config->index), reg_value);
-	if (err) {
-		LOG_ERR("Failed to write SWMODE register");
-		return -EIO;
-	}
-	return 0;
-}
-
-static void stallguard_work_handler(struct k_work *work)
-{
-	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
-	struct tmc5041_stepper_data *stepper_data =
-		CONTAINER_OF(dwork, struct tmc5041_stepper_data, stallguard_dwork);
-	int err;
-	const struct tmc5041_stepper_config *stepper_config = stepper_data->stepper->config;
-
-	err = stallguard_enable(stepper_data->stepper, true);
-	if (err == -EAGAIN) {
-		LOG_ERR("retrying stallguard activation");
-		k_work_reschedule(dwork, K_MSEC(stepper_config->sg_velocity_check_interval_ms));
-	}
-	if (err == -EIO) {
-		LOG_ERR("Failed to enable stallguard because of I/O error");
-		return;
-	}
-}
-
-#ifdef CONFIG_STEPPER_ADI_TMC5041_RAMPSTAT_POLL
-
-static void execute_callback(const struct device *dev, const enum stepper_event event)
-{
-	struct tmc5041_stepper_data *data = dev->data;
-
-	if (!data->callback) {
-		LOG_WRN_ONCE("No callback registered");
-		return;
-	}
-	data->callback(dev, event, data->event_cb_user_data);
-}
-
-static void rampstat_work_handler(struct k_work *work)
-{
-	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
-
-	struct tmc5041_stepper_data *stepper_data =
-		CONTAINER_OF(dwork, struct tmc5041_stepper_data, rampstat_callback_dwork);
-	const struct tmc5041_stepper_config *stepper_config = stepper_data->stepper->config;
-
-	__ASSERT_NO_MSG(stepper_config->controller != NULL);
-
-	uint32_t drv_status;
-	int err;
-
-	err = tmc5041_read(stepper_config->controller, TMC5041_DRVSTATUS(stepper_config->index),
-			   &drv_status);
-	if (err != 0) {
-		LOG_ERR("%s: Failed to read DRVSTATUS register", stepper_data->stepper->name);
-		return;
-	}
-
-	if (FIELD_GET(TMC5XXX_DRV_STATUS_SG_STATUS_MASK, drv_status) == 1U) {
-		LOG_INF("%s: Stall detected", stepper_data->stepper->name);
-		err = tmc5041_write(stepper_config->controller,
-				    TMC5041_RAMPMODE(stepper_config->index),
-				    TMC5XXX_RAMPMODE_HOLD_MODE);
-		if (err != 0) {
-			LOG_ERR("%s: Failed to stop motor", stepper_data->stepper->name);
-			return;
-		}
-	}
-
-	uint32_t rampstat_value;
-
-	err = tmc5041_read(stepper_config->controller, TMC5041_RAMPSTAT(stepper_config->index),
-			   &rampstat_value);
-	if (err != 0) {
-		LOG_ERR("%s: Failed to read RAMPSTAT register", stepper_data->stepper->name);
-		return;
-	}
-
-	const uint8_t ramp_stat_values = FIELD_GET(TMC5XXX_RAMPSTAT_INT_MASK, rampstat_value);
-
-	if (ramp_stat_values > 0) {
-		switch (ramp_stat_values) {
-
-		case TMC5XXX_STOP_LEFT_EVENT:
-			LOG_DBG("RAMPSTAT %s:Left end-stop detected", stepper_data->stepper->name);
-			execute_callback(stepper_data->stepper,
-					 STEPPER_EVENT_LEFT_END_STOP_DETECTED);
-			break;
-
-		case TMC5XXX_STOP_RIGHT_EVENT:
-			LOG_DBG("RAMPSTAT %s:Right end-stop detected", stepper_data->stepper->name);
-			execute_callback(stepper_data->stepper,
-					 STEPPER_EVENT_RIGHT_END_STOP_DETECTED);
-			break;
-
-		case TMC5XXX_POS_REACHED_EVENT:
-			LOG_DBG("RAMPSTAT %s:Position reached", stepper_data->stepper->name);
-			execute_callback(stepper_data->stepper, STEPPER_EVENT_STEPS_COMPLETED);
-			break;
-
-		case TMC5XXX_STOP_SG_EVENT:
-			LOG_DBG("RAMPSTAT %s:Stall detected", stepper_data->stepper->name);
-			stallguard_enable(stepper_data->stepper, false);
-			execute_callback(stepper_data->stepper, STEPPER_EVENT_STALL_DETECTED);
-			break;
-		default:
-			LOG_ERR("Illegal ramp stat bit field");
-			break;
-		}
-	} else {
-		k_work_reschedule(
-			&stepper_data->rampstat_callback_dwork,
-			K_MSEC(CONFIG_STEPPER_ADI_TMC5041_RAMPSTAT_POLL_INTERVAL_IN_MSEC));
-	}
-}
-
-#endif
-
-static int tmc5041_stepper_enable(const struct device *dev, const bool enable)
-{
-	LOG_DBG("Stepper motor controller %s %s", dev->name, enable ? "enabled" : "disabled");
-	const struct tmc5041_stepper_config *config = dev->config;
-	uint32_t reg_value;
-	int err;
-
-	err = tmc5041_read(config->controller, TMC5041_CHOPCONF(config->index), &reg_value);
-	if (err != 0) {
-		return -EIO;
-	}
-
-	if (enable) {
-		reg_value |= TMC5XXX_CHOPCONF_DRV_ENABLE_MASK;
-	} else {
-		reg_value &= ~TMC5XXX_CHOPCONF_DRV_ENABLE_MASK;
-	}
-
-	err = tmc5041_write(config->controller, TMC5041_CHOPCONF(config->index), reg_value);
-	if (err != 0) {
-		return -EIO;
-	}
-	return 0;
-}
-
-static int tmc5041_stepper_is_moving(const struct device *dev, bool *is_moving)
-{
-	const struct tmc5041_stepper_config *config = dev->config;
-	uint32_t reg_value;
-	int err;
-
-	err = tmc5041_read(config->controller, TMC5041_DRVSTATUS(config->index), &reg_value);
-
-	if (err != 0) {
-		LOG_ERR("%s: Failed to read DRVSTATUS register", dev->name);
-		return -EIO;
-	}
-
-	*is_moving = (FIELD_GET(TMC5XXX_DRV_STATUS_STST_BIT, reg_value) != 1U);
-	LOG_DBG("Stepper motor controller %s is moving: %d", dev->name, *is_moving);
-	return 0;
-}
-
-static int tmc5041_stepper_move_by(const struct device *dev, const int32_t micro_steps)
-{
-	const struct tmc5041_stepper_config *config = dev->config;
-	struct tmc5041_stepper_data *data = dev->data;
-	int err;
-
-	if (config->is_sg_enabled) {
-		err = stallguard_enable(dev, false);
-		if (err != 0) {
-			return -EIO;
-		}
-	}
-
-	int32_t position;
-
-	err = stepper_get_actual_position(dev, &position);
-	if (err != 0) {
-		return -EIO;
-	}
-	int32_t target_position = position + micro_steps;
-
-	err = tmc5041_write(config->controller, TMC5041_RAMPMODE(config->index),
-			    TMC5XXX_RAMPMODE_POSITIONING_MODE);
-	if (err != 0) {
-		return -EIO;
-	}
-	LOG_DBG("Stepper motor controller %s moved to %d by steps: %d", dev->name, target_position,
-		micro_steps);
-	err = tmc5041_write(config->controller, TMC5041_XTARGET(config->index), target_position);
-	if (err != 0) {
-		return -EIO;
-	}
-
-	if (config->is_sg_enabled) {
-		k_work_reschedule(&data->stallguard_dwork,
-				  K_MSEC(config->sg_velocity_check_interval_ms));
-	}
-#ifdef CONFIG_STEPPER_ADI_TMC5041_RAMPSTAT_POLL
-	if (data->callback) {
-		k_work_reschedule(
-			&data->rampstat_callback_dwork,
-			K_MSEC(CONFIG_STEPPER_ADI_TMC5041_RAMPSTAT_POLL_INTERVAL_IN_MSEC));
-	}
-#endif
-	return 0;
-}
-
-static int tmc5041_stepper_set_max_velocity(const struct device *dev, uint32_t velocity)
-{
-	const struct tmc5041_stepper_config *config = dev->config;
-	const struct tmc5041_config *tmc5041_config = config->controller->config;
-	const uint32_t clock_frequency = tmc5041_config->clock_frequency;
-	uint32_t velocity_fclk;
-	int err;
-
-	velocity_fclk = tmc5xxx_calculate_velocity_from_hz_to_fclk(velocity, clock_frequency);
-
-	err = tmc5041_write(config->controller, TMC5041_VMAX(config->index), velocity_fclk);
-	if (err != 0) {
-		LOG_ERR("%s: Failed to set max velocity", dev->name);
-		return -EIO;
-	}
-	return 0;
-}
-
-static int tmc5041_stepper_set_micro_step_res(const struct device *dev,
-					      enum stepper_micro_step_resolution res)
-{
-	const struct tmc5041_stepper_config *config = dev->config;
-	uint32_t reg_value;
-	int err;
-
-	err = tmc5041_read(config->controller, TMC5041_CHOPCONF(config->index), &reg_value);
-	if (err != 0) {
-		return -EIO;
-	}
-
-	reg_value &= ~TMC5XXX_CHOPCONF_MRES_MASK;
-	reg_value |= ((MICRO_STEP_RES_INDEX(STEPPER_MICRO_STEP_256) - LOG2(res))
-		      << TMC5XXX_CHOPCONF_MRES_SHIFT);
-
-	err = tmc5041_write(config->controller, TMC5041_CHOPCONF(config->index), reg_value);
-	if (err != 0) {
-		return -EIO;
-	}
-
-	LOG_DBG("Stepper motor controller %s set micro step resolution to 0x%x", dev->name,
-		reg_value);
-	return 0;
-}
-
-static int tmc5041_stepper_get_micro_step_res(const struct device *dev,
-					      enum stepper_micro_step_resolution *res)
-{
-	const struct tmc5041_stepper_config *config = dev->config;
-	uint32_t reg_value;
-	int err;
-
-	err = tmc5041_read(config->controller, TMC5041_CHOPCONF(config->index), &reg_value);
-	if (err != 0) {
-		return -EIO;
-	}
-	reg_value &= TMC5XXX_CHOPCONF_MRES_MASK;
-	reg_value >>= TMC5XXX_CHOPCONF_MRES_SHIFT;
-	*res = (1 << (MICRO_STEP_RES_INDEX(STEPPER_MICRO_STEP_256) - reg_value));
-	LOG_DBG("Stepper motor controller %s get micro step resolution: %d", dev->name, *res);
-	return 0;
-}
-
-static int tmc5041_stepper_set_reference_position(const struct device *dev, const int32_t position)
-{
-	const struct tmc5041_stepper_config *config = dev->config;
-	int err;
-
-	err = tmc5041_write(config->controller, TMC5041_RAMPMODE(config->index),
-			    TMC5XXX_RAMPMODE_HOLD_MODE);
-	if (err != 0) {
-		return -EIO;
-	}
-
-	err = tmc5041_write(config->controller, TMC5041_XACTUAL(config->index), position);
-	if (err != 0) {
-		return -EIO;
-	}
-	LOG_DBG("Stepper motor controller %s set actual position to %d", dev->name, position);
-	return 0;
-}
-
-static int tmc5041_stepper_get_actual_position(const struct device *dev, int32_t *position)
-{
-	const struct tmc5041_stepper_config *config = dev->config;
-	int err;
-
-	err = tmc5041_read(config->controller, TMC5041_XACTUAL(config->index), position);
-	if (err != 0) {
-		return -EIO;
-	}
-	LOG_DBG("%s actual position: %d", dev->name, *position);
-	return 0;
-}
-
-static int tmc5041_stepper_move_to(const struct device *dev, const int32_t micro_steps)
-{
-	LOG_DBG("Stepper motor controller %s set target position to %d", dev->name, micro_steps);
-	const struct tmc5041_stepper_config *config = dev->config;
-	struct tmc5041_stepper_data *data = dev->data;
-	int err;
-
-	if (config->is_sg_enabled) {
-		stallguard_enable(dev, false);
-	}
-
-	err = tmc5041_write(config->controller, TMC5041_RAMPMODE(config->index),
-			    TMC5XXX_RAMPMODE_POSITIONING_MODE);
-	if (err != 0) {
-		return -EIO;
-	}
-	err = tmc5041_write(config->controller, TMC5041_XTARGET(config->index), micro_steps);
-	if (err != 0) {
-		return -EIO;
-	}
-
-	if (config->is_sg_enabled) {
-		k_work_reschedule(&data->stallguard_dwork,
-				  K_MSEC(config->sg_velocity_check_interval_ms));
-	}
-#ifdef CONFIG_STEPPER_ADI_TMC5041_RAMPSTAT_POLL
-	if (data->callback) {
-		k_work_reschedule(
-			&data->rampstat_callback_dwork,
-			K_MSEC(CONFIG_STEPPER_ADI_TMC5041_RAMPSTAT_POLL_INTERVAL_IN_MSEC));
-	}
-#endif
-	return 0;
-}
-
-static int tmc5041_stepper_run(const struct device *dev, const enum stepper_direction direction,
-			       const uint32_t velocity)
-{
-	LOG_DBG("Stepper motor controller %s run with velocity %d", dev->name, velocity);
-	const struct tmc5041_stepper_config *config = dev->config;
-	const struct tmc5041_config *tmc5041_config = config->controller->config;
-	struct tmc5041_stepper_data *data = dev->data;
-	const uint32_t clock_frequency = tmc5041_config->clock_frequency;
-	uint32_t velocity_fclk;
-	int err;
-
-	velocity_fclk = tmc5xxx_calculate_velocity_from_hz_to_fclk(velocity, clock_frequency);
-
-	if (config->is_sg_enabled) {
-		err = stallguard_enable(dev, false);
-		if (err != 0) {
-			return -EIO;
-		}
-	}
-
-	switch (direction) {
-	case STEPPER_DIRECTION_POSITIVE:
-		err = tmc5041_write(config->controller, TMC5041_RAMPMODE(config->index),
-				    TMC5XXX_RAMPMODE_POSITIVE_VELOCITY_MODE);
-		if (err != 0) {
-			return -EIO;
-		}
-		err = tmc5041_write(config->controller, TMC5041_VMAX(config->index), velocity_fclk);
-		if (err != 0) {
-			return -EIO;
-		}
-		break;
-
-	case STEPPER_DIRECTION_NEGATIVE:
-		err = tmc5041_write(config->controller, TMC5041_RAMPMODE(config->index),
-				    TMC5XXX_RAMPMODE_NEGATIVE_VELOCITY_MODE);
-		if (err != 0) {
-			return -EIO;
-		}
-		err = tmc5041_write(config->controller, TMC5041_VMAX(config->index), velocity_fclk);
-		if (err != 0) {
-			return -EIO;
-		}
-		break;
-	}
-
-	if (config->is_sg_enabled) {
-		k_work_reschedule(&data->stallguard_dwork,
-				  K_MSEC(config->sg_velocity_check_interval_ms));
-	}
-#ifdef CONFIG_STEPPER_ADI_TMC5041_RAMPSTAT_POLL
-	if (data->callback) {
-		k_work_reschedule(
-			&data->rampstat_callback_dwork,
-			K_MSEC(CONFIG_STEPPER_ADI_TMC5041_RAMPSTAT_POLL_INTERVAL_IN_MSEC));
-	}
-#endif
-	return 0;
-}
-
-#ifdef CONFIG_STEPPER_ADI_TMC5041_RAMP_GEN
-
-int tmc5041_stepper_set_ramp(const struct device *dev,
-			     const struct tmc_ramp_generator_data *ramp_data)
-{
-	LOG_DBG("Stepper motor controller %s set ramp", dev->name);
-	const struct tmc5041_stepper_config *config = dev->config;
-	int err;
-
-	err = tmc5041_write(config->controller, TMC5041_VSTART(config->index), ramp_data->vstart);
-	if (err != 0) {
-		return -EIO;
-	}
-	err = tmc5041_write(config->controller, TMC5041_A1(config->index), ramp_data->a1);
-	if (err != 0) {
-		return -EIO;
-	}
-	err = tmc5041_write(config->controller, TMC5041_AMAX(config->index), ramp_data->amax);
-	if (err != 0) {
-		return -EIO;
-	}
-	err = tmc5041_write(config->controller, TMC5041_D1(config->index), ramp_data->d1);
-	if (err != 0) {
-		return -EIO;
-	}
-	err = tmc5041_write(config->controller, TMC5041_DMAX(config->index), ramp_data->dmax);
-	if (err != 0) {
-		return -EIO;
-	}
-	err = tmc5041_write(config->controller, TMC5041_V1(config->index), ramp_data->v1);
-	if (err != 0) {
-		return -EIO;
-	}
-	err = tmc5041_write(config->controller, TMC5041_VMAX(config->index), ramp_data->vmax);
-	if (err != 0) {
-		return -EIO;
-	}
-	err = tmc5041_write(config->controller, TMC5041_VSTOP(config->index), ramp_data->vstop);
-	if (err != 0) {
-		return -EIO;
-	}
-	err = tmc5041_write(config->controller, TMC5041_TZEROWAIT(config->index),
-			    ramp_data->tzerowait);
-	if (err != 0) {
-		return -EIO;
-	}
-	err = tmc5041_write(config->controller, TMC5041_VHIGH(config->index), ramp_data->vhigh);
-	if (err != 0) {
-		return -EIO;
-	}
-	err = tmc5041_write(config->controller, TMC5041_VCOOLTHRS(config->index),
-			    ramp_data->vcoolthrs);
-	if (err != 0) {
-		return -EIO;
-	}
-	err = tmc5041_write(config->controller, TMC5041_IHOLD_IRUN(config->index),
-			    ramp_data->iholdrun);
-	if (err != 0) {
-		return -EIO;
-	}
-	return 0;
-}
-
-#endif
-
-static int tmc5041_init(const struct device *dev)
-{
-	LOG_DBG("TMC5041 stepper motor controller %s initialized", dev->name);
-	struct tmc5041_data *data = dev->data;
-	const struct tmc5041_config *config = dev->config;
-	int err;
-
-	k_sem_init(&data->sem, 1, 1);
-
-	if (!spi_is_ready_dt(&config->spi)) {
-		LOG_ERR("SPI bus is not ready");
-		return -ENODEV;
-	}
-
-	/* Init non motor-index specific registers here. */
-	LOG_DBG("GCONF: %d", config->gconf);
-	err = tmc5041_write(dev, TMC5XXX_GCONF, config->gconf);
-	if (err != 0) {
-		return -EIO;
-	}
-
-	/* Read GSTAT register values to clear any errors SPI Datagram. */
-	uint32_t gstat_value;
-
-	err = tmc5041_read(dev, TMC5XXX_GSTAT, &gstat_value);
-	if (err != 0) {
-		return -EIO;
-	}
-
-	LOG_DBG("Device %s initialized", dev->name);
-	return 0;
-}
-
-static int tmc5041_stepper_init(const struct device *dev)
-{
-	const struct tmc5041_stepper_config *stepper_config = dev->config;
-	struct tmc5041_stepper_data *data = dev->data;
-	int err;
-
-	LOG_DBG("Controller: %s, Stepper: %s", stepper_config->controller->name, dev->name);
-
-	if (stepper_config->is_sg_enabled) {
-		k_work_init_delayable(&data->stallguard_dwork, stallguard_work_handler);
-
-		err = tmc5041_write(stepper_config->controller,
-				    TMC5041_SWMODE(stepper_config->index), BIT(10));
-		if (err != 0) {
-			return -EIO;
-		}
-
-		LOG_DBG("Setting stall guard to %d with delay %d ms", stepper_config->sg_threshold,
-			stepper_config->sg_velocity_check_interval_ms);
-		if (!IN_RANGE(stepper_config->sg_threshold, TMC5XXX_SG_MIN_VALUE,
-			      TMC5XXX_SG_MAX_VALUE)) {
-			LOG_ERR("Stallguard threshold out of range");
-			return -EINVAL;
-		}
-
-		int32_t stall_guard_threshold = (int32_t)stepper_config->sg_threshold;
-
-		err = tmc5041_write(
-			stepper_config->controller, TMC5041_COOLCONF(stepper_config->index),
-			stall_guard_threshold << TMC5XXX_COOLCONF_SG2_THRESHOLD_VALUE_SHIFT);
-		if (err != 0) {
-			return -EIO;
-		}
-		err = stallguard_enable(dev, true);
-		if (err == -EAGAIN) {
-			LOG_ERR("retrying stallguard activation");
-			k_work_reschedule(&data->stallguard_dwork,
-					  K_MSEC(stepper_config->sg_velocity_check_interval_ms));
-		}
-	}
-
-#ifdef CONFIG_STEPPER_ADI_TMC5041_RAMP_GEN
-	err = tmc5041_stepper_set_ramp(dev, &stepper_config->default_ramp_config);
-	if (err != 0) {
-		return -EIO;
-	}
-#endif
-
-#if CONFIG_STEPPER_ADI_TMC5041_RAMPSTAT_POLL
-	k_work_init_delayable(&data->rampstat_callback_dwork, rampstat_work_handler);
-	k_work_reschedule(&data->rampstat_callback_dwork,
-			  K_MSEC(CONFIG_STEPPER_ADI_TMC5041_RAMPSTAT_POLL_INTERVAL_IN_MSEC));
-#endif
-	err = tmc5041_stepper_set_micro_step_res(dev, stepper_config->default_micro_step_res);
-	if (err != 0) {
-		return -EIO;
-	}
-	return 0;
-}
-
-#define TMC5041_SHAFT_CONFIG(child)								\
-	(DT_PROP(child, invert_direction) << TMC5041_GCONF_SHAFT_SHIFT(DT_REG_ADDR(child))) |
-
-#define TMC5041_STEPPER_CONFIG_DEFINE(child)							\
-	COND_CODE_1(DT_PROP_EXISTS(child, stallguard_threshold_velocity),			\
-	BUILD_ASSERT(DT_PROP(child, stallguard_threshold_velocity),				\
-		     "stallguard threshold velocity must be a positive value"), ());		\
-	IF_ENABLED(CONFIG_STEPPER_ADI_TMC5041_RAMP_GEN, (CHECK_RAMP_DT_DATA(child)));		\
-	static const struct tmc5041_stepper_config tmc5041_stepper_config_##child = {		\
-		.controller = DEVICE_DT_GET(DT_PARENT(child)),					\
-		.default_micro_step_res = DT_PROP(child, micro_step_res),			\
-		.index = DT_REG_ADDR(child),							\
-		.sg_threshold = DT_PROP(child, stallguard2_threshold),				\
-		.sg_threshold_velocity = DT_PROP(child, stallguard_threshold_velocity),		\
-		.sg_velocity_check_interval_ms = DT_PROP(child,					\
-						stallguard_velocity_check_interval_ms),		\
-		.is_sg_enabled = DT_PROP(child, activate_stallguard2),				\
-		IF_ENABLED(CONFIG_STEPPER_ADI_TMC5041_RAMP_GEN,					\
-		(.default_ramp_config = TMC_RAMP_DT_SPEC_GET(child))) };
-
-#define TMC5041_STEPPER_DATA_DEFINE(child)							\
-	static struct tmc5041_stepper_data tmc5041_stepper_data_##child = {			\
-		.stepper = DEVICE_DT_GET(child),};
-
-#define TMC5041_STEPPER_API_DEFINE(child)							\
-	static DEVICE_API(stepper, tmc5041_stepper_api_##child) = {				\
-		.enable = tmc5041_stepper_enable,						\
-		.is_moving = tmc5041_stepper_is_moving,						\
-		.move_by = tmc5041_stepper_move_by,						\
-		.set_max_velocity = tmc5041_stepper_set_max_velocity,				\
-		.set_micro_step_res = tmc5041_stepper_set_micro_step_res,			\
-		.get_micro_step_res = tmc5041_stepper_get_micro_step_res,			\
-		.set_reference_position = tmc5041_stepper_set_reference_position,		\
-		.get_actual_position = tmc5041_stepper_get_actual_position,			\
-		.move_to = tmc5041_stepper_move_to,						\
-		.run = tmc5041_stepper_run,							\
-		.set_event_callback = tmc5041_stepper_set_event_callback, };
-
-#define TMC5041_STEPPER_DEFINE(child)								\
-	DEVICE_DT_DEFINE(child, tmc5041_stepper_init, NULL, &tmc5041_stepper_data_##child,	\
-			 &tmc5041_stepper_config_##child, POST_KERNEL,				\
-			 CONFIG_STEPPER_INIT_PRIORITY, &tmc5041_stepper_api_##child);
-
-#define TMC5041_DEFINE(inst)									\
-	BUILD_ASSERT(DT_INST_CHILD_NUM(inst) <= 2, "tmc5041 can drive two steppers at max");	\
-	BUILD_ASSERT((DT_INST_PROP(inst, clock_frequency) > 0),					\
-		     "clock frequency must be non-zero positive value");			\
-	static struct tmc5041_data tmc5041_data_##inst;						\
-	static const struct tmc5041_config tmc5041_config_##inst = {				\
-		.gconf = (									\
-		(DT_INST_PROP(inst, poscmp_enable) << TMC5041_GCONF_POSCMP_ENABLE_SHIFT) |	\
-		(DT_INST_PROP(inst, test_mode) << TMC5041_GCONF_TEST_MODE_SHIFT) |		\
-		DT_INST_FOREACH_CHILD(inst, TMC5041_SHAFT_CONFIG)				\
-		(DT_INST_PROP(inst, lock_gconf) << TMC5041_LOCK_GCONF_SHIFT)),			\
-		.spi = SPI_DT_SPEC_INST_GET(inst, (SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB |	\
-					SPI_MODE_CPOL | SPI_MODE_CPHA |	SPI_WORD_SET(8)), 0),	\
-		.clock_frequency = DT_INST_PROP(inst, clock_frequency),};			\
-	DT_INST_FOREACH_CHILD(inst, TMC5041_STEPPER_CONFIG_DEFINE);				\
-	DT_INST_FOREACH_CHILD(inst, TMC5041_STEPPER_DATA_DEFINE);				\
-	DT_INST_FOREACH_CHILD(inst, TMC5041_STEPPER_API_DEFINE);				\
-	DT_INST_FOREACH_CHILD(inst, TMC5041_STEPPER_DEFINE);					\
-	DEVICE_DT_INST_DEFINE(inst, tmc5041_init, NULL, &tmc5041_data_##inst,			\
-			      &tmc5041_config_##inst, POST_KERNEL, CONFIG_STEPPER_INIT_PRIORITY,\
-			      NULL);
-
-DT_INST_FOREACH_STATUS_OKAY(TMC5041_DEFINE)
diff --git a/drivers/stepper/adi_tmc/adi_tmc_reg.h b/drivers/stepper/adi_tmc/adi_tmc_reg.h
index eff9f86cea8..616b405442c 100644
--- a/drivers/stepper/adi_tmc/adi_tmc_reg.h
+++ b/drivers/stepper/adi_tmc/adi_tmc_reg.h
@@ -7,6 +7,7 @@
 
 /*
  * SPDX-FileCopyrightText: Copyright (c) 2024 Carl Zeiss Meditec AG
+ * SPDX-FileCopyrightText: Copyright (c) 2025 Prevas A/S
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -17,13 +18,13 @@
 extern "C" {
 #endif
 
-/** Common Registers for TMC5041 and TMC51XX */
-#if defined(CONFIG_STEPPER_ADI_TMC5041)
+/** Common Registers for TMC50XX and TMC51XX */
+#if defined(CONFIG_STEPPER_ADI_TMC50XX) || defined(CONFIG_STEPPER_ADI_TMC51XX)
 
 #define TMC5XXX_WRITE_BIT        0x80U
 #define TMC5XXX_ADDRESS_MASK     0x7FU
 
- #define TMC5XXX_CLOCK_FREQ_SHIFT 24
+#define TMC5XXX_CLOCK_FREQ_SHIFT 24
 
 #define TMC5XXX_GCONF 0x00
 #define TMC5XXX_GSTAT 0x01
@@ -79,66 +80,102 @@ extern "C" {
 #define TMC5XXX_DRV_STATUS_SG_STATUS_MASK  BIT(24)
 #define TMC5XXX_DRV_STATUS_SG_STATUS_SHIFT 24
 
+#define TMC50XX_MOTOR_ADDR(m)     (0x20 << (m))
+#define TMC50XX_MOTOR_ADDR_DRV(m) ((m) << 4)
+
+#define TMC50XX_RAMPMODE(motor)   (0x00 | TMC50XX_MOTOR_ADDR(motor))
+#define TMC50XX_XACTUAL(motor)    (0x01 | TMC50XX_MOTOR_ADDR(motor))
+#define TMC50XX_VACTUAL(motor)    (0x02 | TMC50XX_MOTOR_ADDR(motor))
+#define TMC50XX_VSTART(motor)     (0x03 | TMC50XX_MOTOR_ADDR(motor))
+#define TMC50XX_A1(motor)         (0x04 | TMC50XX_MOTOR_ADDR(motor))
+#define TMC50XX_V1(motor)         (0x05 | TMC50XX_MOTOR_ADDR(motor))
+#define TMC50XX_AMAX(motor)       (0x06 | TMC50XX_MOTOR_ADDR(motor))
+#define TMC50XX_VMAX(motor)       (0x07 | TMC50XX_MOTOR_ADDR(motor))
+#define TMC50XX_DMAX(motor)       (0x08 | TMC50XX_MOTOR_ADDR(motor))
+#define TMC50XX_D1(motor)         (0x0A | TMC50XX_MOTOR_ADDR(motor))
+#define TMC50XX_VSTOP(motor)      (0x0B | TMC50XX_MOTOR_ADDR(motor))
+#define TMC50XX_TZEROWAIT(motor)  (0x0C | TMC50XX_MOTOR_ADDR(motor))
+#define TMC50XX_XTARGET(motor)    (0x0D | TMC50XX_MOTOR_ADDR(motor))
+#define TMC50XX_SWMODE(motor)     (0x14 | TMC50XX_MOTOR_ADDR(motor))
+#define TMC50XX_RAMPSTAT(motor)   (0x15 | TMC50XX_MOTOR_ADDR(motor))
+#define TMC50XX_CHOPCONF(motor)   (0x6C | TMC50XX_MOTOR_ADDR_DRV(motor))
+#define TMC50XX_COOLCONF(motor)   (0x6D | TMC50XX_MOTOR_ADDR_DRV(motor))
+#define TMC50XX_DRVSTATUS(motor)  (0x6F | TMC50XX_MOTOR_ADDR_DRV(motor))
+
 #endif
 
-#ifdef CONFIG_STEPPER_ADI_TMC5041
+#ifdef CONFIG_STEPPER_ADI_TMC50XX
 
-#define TMC5041_MOTOR_ADDR(m)     (0x20 << (m))
-#define TMC5041_MOTOR_ADDR_DRV(m) ((m) << 4)
-#define TMC5041_MOTOR_ADDR_PWM(m) ((m) << 3)
+#define TMC50XX_MOTOR_ADDR_PWM(m) ((m) << 3)
 
 /**
- * @name TMC5041 module registers
- * @anchor TMC5041_REGISTERS
+ * @name TMC50XX module registers
+ * @anchor TMC50XX_REGISTERS
  *
  * @{
  */
 
-#define TMC5041_GCONF_POSCMP_ENABLE_SHIFT 3
-#define TMC5041_GCONF_TEST_MODE_SHIFT     7
-#define TMC5041_GCONF_SHAFT_SHIFT(n)      ((n) ? 8 : 9)
-#define TMC5041_LOCK_GCONF_SHIFT          10
-
-#define TMC5041_PWMCONF(motor)    (0x10 | TMC5041_MOTOR_ADDR_PWM(motor))
-#define TMC5041_PWM_STATUS(motor) (0x11 | TMC5041_MOTOR_ADDR_PWM(motor))
-
-#define TMC5041_RAMPMODE(motor)   (0x00 | TMC5041_MOTOR_ADDR(motor))
-#define TMC5041_XACTUAL(motor)    (0x01 | TMC5041_MOTOR_ADDR(motor))
-#define TMC5041_VACTUAL(motor)    (0x02 | TMC5041_MOTOR_ADDR(motor))
-#define TMC5041_VSTART(motor)     (0x03 | TMC5041_MOTOR_ADDR(motor))
-#define TMC5041_A1(motor)         (0x04 | TMC5041_MOTOR_ADDR(motor))
-#define TMC5041_V1(motor)         (0x05 | TMC5041_MOTOR_ADDR(motor))
-#define TMC5041_AMAX(motor)       (0x06 | TMC5041_MOTOR_ADDR(motor))
-#define TMC5041_VMAX(motor)       (0x07 | TMC5041_MOTOR_ADDR(motor))
-#define TMC5041_DMAX(motor)       (0x08 | TMC5041_MOTOR_ADDR(motor))
-#define TMC5041_D1(motor)         (0x0A | TMC5041_MOTOR_ADDR(motor))
-#define TMC5041_VSTOP(motor)      (0x0B | TMC5041_MOTOR_ADDR(motor))
-#define TMC5041_TZEROWAIT(motor)  (0x0C | TMC5041_MOTOR_ADDR(motor))
-#define TMC5041_XTARGET(motor)    (0x0D | TMC5041_MOTOR_ADDR(motor))
-#define TMC5041_IHOLD_IRUN(motor) (0x10 | TMC5041_MOTOR_ADDR(motor))
-#define TMC5041_VCOOLTHRS(motor)  (0x11 | TMC5041_MOTOR_ADDR(motor))
-#define TMC5041_VHIGH(motor)      (0x12 | TMC5041_MOTOR_ADDR(motor))
-#define TMC5041_SWMODE(motor)     (0x14 | TMC5041_MOTOR_ADDR(motor))
-#define TMC5041_RAMPSTAT(motor)   (0x15 | TMC5041_MOTOR_ADDR(motor))
-#define TMC5041_XLATCH(motor)     (0x16 | TMC5041_MOTOR_ADDR(motor))
-
-#define TMC5041_MSLUT0(motor)     (0x60 | TMC5041_MOTOR_ADDR_DRV(motor))
-#define TMC5041_MSLUT1(motor)     (0x61 | TMC5041_MOTOR_ADDR_DRV(motor))
-#define TMC5041_MSLUT2(motor)     (0x62 | TMC5041_MOTOR_ADDR_DRV(motor))
-#define TMC5041_MSLUT3(motor)     (0x63 | TMC5041_MOTOR_ADDR_DRV(motor))
-#define TMC5041_MSLUT4(motor)     (0x64 | TMC5041_MOTOR_ADDR_DRV(motor))
-#define TMC5041_MSLUT5(motor)     (0x65 | TMC5041_MOTOR_ADDR_DRV(motor))
-#define TMC5041_MSLUT6(motor)     (0x66 | TMC5041_MOTOR_ADDR_DRV(motor))
-#define TMC5041_MSLUT7(motor)     (0x67 | TMC5041_MOTOR_ADDR_DRV(motor))
-#define TMC5041_MSLUTSEL(motor)   (0x68 | TMC5041_MOTOR_ADDR_DRV(motor))
-#define TMC5041_MSLUTSTART(motor) (0x69 | TMC5041_MOTOR_ADDR_DRV(motor))
-#define TMC5041_MSCNT(motor)      (0x6A | TMC5041_MOTOR_ADDR_DRV(motor))
-#define TMC5041_MSCURACT(motor)   (0x6B | TMC5041_MOTOR_ADDR_DRV(motor))
-#define TMC5041_CHOPCONF(motor)   (0x6C | TMC5041_MOTOR_ADDR_DRV(motor))
-#define TMC5041_COOLCONF(motor)   (0x6D | TMC5041_MOTOR_ADDR_DRV(motor))
-#define TMC5041_DRVSTATUS(motor)  (0x6F | TMC5041_MOTOR_ADDR_DRV(motor))
-
-#endif
+#define TMC50XX_GCONF_POSCMP_ENABLE_SHIFT 3
+#define TMC50XX_GCONF_TEST_MODE_SHIFT     7
+#define TMC50XX_GCONF_SHAFT_SHIFT(n)      ((n) ? 8 : 9)
+#define TMC50XX_LOCK_GCONF_SHIFT          10
+
+#define TMC50XX_PWMCONF(motor)    (0x10 | TMC50XX_MOTOR_ADDR_PWM(motor))
+#define TMC50XX_PWM_STATUS(motor) (0x11 | TMC50XX_MOTOR_ADDR_PWM(motor))
+
+#define TMC50XX_IHOLD_IRUN(motor) (0x10 | TMC50XX_MOTOR_ADDR(motor))
+#define TMC50XX_VCOOLTHRS(motor)  (0x11 | TMC50XX_MOTOR_ADDR(motor))
+#define TMC50XX_VHIGH(motor)      (0x12 | TMC50XX_MOTOR_ADDR(motor))
+#define TMC50XX_XLATCH(motor)     (0x16 | TMC50XX_MOTOR_ADDR(motor))
+
+#define TMC50XX_MSLUT0(motor)     (0x60 | TMC50XX_MOTOR_ADDR_DRV(motor))
+#define TMC50XX_MSLUT1(motor)     (0x61 | TMC50XX_MOTOR_ADDR_DRV(motor))
+#define TMC50XX_MSLUT2(motor)     (0x62 | TMC50XX_MOTOR_ADDR_DRV(motor))
+#define TMC50XX_MSLUT3(motor)     (0x63 | TMC50XX_MOTOR_ADDR_DRV(motor))
+#define TMC50XX_MSLUT4(motor)     (0x64 | TMC50XX_MOTOR_ADDR_DRV(motor))
+#define TMC50XX_MSLUT5(motor)     (0x65 | TMC50XX_MOTOR_ADDR_DRV(motor))
+#define TMC50XX_MSLUT6(motor)     (0x66 | TMC50XX_MOTOR_ADDR_DRV(motor))
+#define TMC50XX_MSLUT7(motor)     (0x67 | TMC50XX_MOTOR_ADDR_DRV(motor))
+#define TMC50XX_MSLUTSEL(motor)   (0x68 | TMC50XX_MOTOR_ADDR_DRV(motor))
+#define TMC50XX_MSLUTSTART(motor) (0x69 | TMC50XX_MOTOR_ADDR_DRV(motor))
+#define TMC50XX_MSCNT(motor)      (0x6A | TMC50XX_MOTOR_ADDR_DRV(motor))
+#define TMC50XX_MSCURACT(motor)   (0x6B | TMC50XX_MOTOR_ADDR_DRV(motor))
+
+#endif /* CONFIG_STEPPER_ADI_TMC50XX */
+
+#ifdef CONFIG_STEPPER_ADI_TMC51XX
+
+#define TMC51XX_GCONF_EN_PWM_MODE_SHIFT	2
+#define TMC51XX_GCONF_SHAFT_SHIFT	4
+#define TMC51XX_GCONF_TEST_MODE_SHIFT	17
+
+#define TMC51XX_IHOLD_IRUN	0x10
+#define TMC51XX_TPOWER_DOWN	0x11
+#define TMC51XX_TSTEP		0x12
+#define TMC51XX_TPWMTHRS	0x13
+#define TMC51XX_TCOOLTHRS	0x14
+#define TMC51XX_THIGH		0x15
+
+#define TMC51XX_RAMPMODE   	TMC50XX_RAMPMODE(0)
+#define TMC51XX_XACTUAL    	TMC50XX_XACTUAL(0)
+#define TMC51XX_VACTUAL    	TMC50XX_VACTUAL(0)
+#define TMC51XX_VSTART     	TMC50XX_VSTART(0)
+#define TMC51XX_A1         	TMC50XX_A1(0)
+#define TMC51XX_V1         	TMC50XX_V1(0)
+#define TMC51XX_AMAX       	TMC50XX_AMAX(0)
+#define TMC51XX_VMAX       	TMC50XX_VMAX(0)
+#define TMC51XX_DMAX       	TMC50XX_DMAX(0)
+#define TMC51XX_D1         	TMC50XX_D1(0)
+#define TMC51XX_VSTOP      	TMC50XX_VSTOP(0)
+#define TMC51XX_TZEROWAIT  	TMC50XX_TZEROWAIT(0)
+#define TMC51XX_XTARGET    	TMC50XX_XTARGET(0)
+#define TMC51XX_SWMODE     	TMC50XX_SWMODE(0)
+#define TMC51XX_RAMPSTAT   	TMC50XX_RAMPSTAT(0)
+#define TMC51XX_CHOPCONF   	TMC50XX_CHOPCONF(0)
+#define TMC51XX_COOLCONF   	TMC50XX_COOLCONF(0)
+#define TMC51XX_DRVSTATUS  	TMC50XX_DRVSTATUS(0)
+
+#endif /* CONFIG_STEPPER_ADI_TMC51XX */
 
 /**
  * @}
diff --git a/drivers/stepper/adi_tmc/tmc22xx.c b/drivers/stepper/adi_tmc/tmc22xx.c
new file mode 100644
index 00000000000..fb73dc35fc2
--- /dev/null
+++ b/drivers/stepper/adi_tmc/tmc22xx.c
@@ -0,0 +1,201 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2024 Fabian Blatz <fabianblatz@gmail.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../step_dir/step_dir_stepper_common.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(tmc22xx, CONFIG_STEPPER_LOG_LEVEL);
+
+#define MSX_PIN_COUNT       2
+#define MSX_PIN_STATE_COUNT 4
+
+struct tmc22xx_config {
+	struct step_dir_stepper_common_config common;
+	const struct gpio_dt_spec enable_pin;
+	const struct gpio_dt_spec *msx_pins;
+	enum stepper_micro_step_resolution *msx_resolutions;
+};
+
+struct tmc22xx_data {
+	struct step_dir_stepper_common_data common;
+	enum stepper_micro_step_resolution resolution;
+};
+
+STEP_DIR_STEPPER_STRUCT_CHECK(struct tmc22xx_config, struct tmc22xx_data);
+
+static int tmc22xx_stepper_enable(const struct device *dev)
+{
+	const struct tmc22xx_config *config = dev->config;
+
+	LOG_DBG("Enabling Stepper motor controller %s", dev->name);
+	return gpio_pin_set_dt(&config->enable_pin, 1);
+}
+
+static int tmc22xx_stepper_disable(const struct device *dev)
+{
+	const struct tmc22xx_config *config = dev->config;
+
+	LOG_DBG("Disabling Stepper motor controller %s", dev->name);
+	return gpio_pin_set_dt(&config->enable_pin, 0);
+}
+
+static int tmc22xx_stepper_set_micro_step_res(const struct device *dev,
+					      enum stepper_micro_step_resolution micro_step_res)
+{
+	struct tmc22xx_data *data = dev->data;
+	const struct tmc22xx_config *config = dev->config;
+	int ret;
+
+	if (!config->msx_pins) {
+		LOG_ERR("Microstep resolution pins are not configured");
+		return -ENODEV;
+	}
+
+	for (uint8_t i = 0; i < MSX_PIN_STATE_COUNT; i++) {
+		if (micro_step_res != config->msx_resolutions[i]) {
+			continue;
+		}
+
+		ret = gpio_pin_set_dt(&config->msx_pins[0], i & 0x01);
+		if (ret < 0) {
+			LOG_ERR("Failed to set MS1 pin: %d", ret);
+			return ret;
+		}
+
+		ret = gpio_pin_set_dt(&config->msx_pins[1], (i & 0x02) >> 1);
+		if (ret < 0) {
+			LOG_ERR("Failed to set MS2 pin: %d", ret);
+			return ret;
+		}
+
+		data->resolution = micro_step_res;
+		return 0;
+	}
+
+	LOG_ERR("Unsupported microstep resolution: %d", micro_step_res);
+	return -ENOTSUP;
+}
+
+static int tmc22xx_stepper_get_micro_step_res(const struct device *dev,
+					      enum stepper_micro_step_resolution *micro_step_res)
+{
+	struct tmc22xx_data *data = dev->data;
+
+	*micro_step_res = data->resolution;
+	return 0;
+}
+
+static int tmc22xx_stepper_configure_msx_pins(const struct device *dev)
+{
+	const struct tmc22xx_config *config = dev->config;
+	int ret;
+
+	for (uint8_t i = 0; i < MSX_PIN_COUNT; i++) {
+		if (!gpio_is_ready_dt(&config->msx_pins[i])) {
+			LOG_ERR("MSX pin %u are not ready", i);
+			return -ENODEV;
+		}
+
+		ret = gpio_pin_configure_dt(&config->msx_pins[i], GPIO_OUTPUT);
+		if (ret < 0) {
+			LOG_ERR("Failed to configure msx pin %u", i);
+			return ret;
+		}
+	}
+	return 0;
+}
+
+static int tmc22xx_stepper_init(const struct device *dev)
+{
+	const struct tmc22xx_config *config = dev->config;
+	struct tmc22xx_data *data = dev->data;
+	int ret;
+
+	if (!gpio_is_ready_dt(&config->enable_pin)) {
+		LOG_ERR("GPIO pins are not ready");
+		return -ENODEV;
+	}
+
+	ret = gpio_pin_configure_dt(&config->enable_pin, GPIO_OUTPUT);
+	if (ret < 0) {
+		LOG_ERR("Failed to configure enable pin: %d", ret);
+		return ret;
+	}
+
+	if (config->msx_pins) {
+		ret = tmc22xx_stepper_configure_msx_pins(dev);
+		if (ret < 0) {
+			LOG_ERR("Failed to configure MSX pins: %d", ret);
+			return ret;
+		}
+
+		ret = tmc22xx_stepper_set_micro_step_res(dev, data->resolution);
+		if (ret < 0) {
+			LOG_ERR("Failed to set microstep resolution: %d", ret);
+			return ret;
+		}
+	}
+
+	ret = step_dir_stepper_common_init(dev);
+	if (ret < 0) {
+		LOG_ERR("Failed to init step dir common stepper: %d", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(stepper, tmc22xx_stepper_api) = {
+	.enable = tmc22xx_stepper_enable,
+	.disable = tmc22xx_stepper_disable,
+	.move_by = step_dir_stepper_common_move_by,
+	.is_moving = step_dir_stepper_common_is_moving,
+	.set_reference_position = step_dir_stepper_common_set_reference_position,
+	.get_actual_position = step_dir_stepper_common_get_actual_position,
+	.move_to = step_dir_stepper_common_move_to,
+	.set_microstep_interval = step_dir_stepper_common_set_microstep_interval,
+	.run = step_dir_stepper_common_run,
+	.stop = step_dir_stepper_common_stop,
+	.set_event_callback = step_dir_stepper_common_set_event_callback,
+	.set_micro_step_res = tmc22xx_stepper_set_micro_step_res,
+	.get_micro_step_res = tmc22xx_stepper_get_micro_step_res,
+};
+
+#define TMC22XX_STEPPER_DEFINE(inst, msx_table)                                                    \
+	IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, msx_gpios), (                                       \
+	static const struct gpio_dt_spec tmc22xx_stepper_msx_pins_##inst[] = {                     \
+		DT_INST_FOREACH_PROP_ELEM_SEP(                                                     \
+			inst, msx_gpios, GPIO_DT_SPEC_GET_BY_IDX, (,)                              \
+		),                                                                                 \
+	};                                                                                         \
+	BUILD_ASSERT(                                                                              \
+		ARRAY_SIZE(tmc22xx_stepper_msx_pins_##inst) == MSX_PIN_COUNT,                      \
+		"Two microstep config pins needed");                                               \
+	))                                                                                         \
+                                                                                                   \
+	static const struct tmc22xx_config tmc22xx_config_##inst = {                               \
+		.common = STEP_DIR_STEPPER_DT_INST_COMMON_CONFIG_INIT(inst),                       \
+		.enable_pin = GPIO_DT_SPEC_INST_GET(inst, en_gpios),	                           \
+		.msx_resolutions = msx_table,                                                      \
+		IF_ENABLED(DT_INST_NODE_HAS_PROP(inst, msx_gpios),				   \
+		(.msx_pins = tmc22xx_stepper_msx_pins_##inst))					   \
+	};                                                                                         \
+	static struct tmc22xx_data tmc22xx_data_##inst = {                                         \
+		.common = STEP_DIR_STEPPER_DT_INST_COMMON_DATA_INIT(inst),                         \
+		.resolution = DT_INST_PROP(inst, micro_step_res),                                  \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(inst, tmc22xx_stepper_init, NULL, &tmc22xx_data_##inst,              \
+			      &tmc22xx_config_##inst, POST_KERNEL, CONFIG_STEPPER_INIT_PRIORITY,   \
+			      &tmc22xx_stepper_api);
+
+#define DT_DRV_COMPAT adi_tmc2209
+static enum stepper_micro_step_resolution tmc2209_msx_resolutions[MSX_PIN_STATE_COUNT] = {
+	STEPPER_MICRO_STEP_8,
+	STEPPER_MICRO_STEP_32,
+	STEPPER_MICRO_STEP_64,
+	STEPPER_MICRO_STEP_16,
+};
+DT_INST_FOREACH_STATUS_OKAY_VARGS(TMC22XX_STEPPER_DEFINE, tmc2209_msx_resolutions)
+#undef DT_DRV_COMPAT
diff --git a/drivers/stepper/adi_tmc/tmc50xx.c b/drivers/stepper/adi_tmc/tmc50xx.c
new file mode 100644
index 00000000000..87fdf0631a0
--- /dev/null
+++ b/drivers/stepper/adi_tmc/tmc50xx.c
@@ -0,0 +1,773 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2024 Carl Zeiss Meditec AG
+ * SPDX-FileCopyrightText: Copyright (c) 2025 Jilay Sandeep Pandya
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT adi_tmc50xx
+
+#include <stdlib.h>
+
+#include <zephyr/drivers/stepper.h>
+#include <zephyr/drivers/stepper/stepper_trinamic.h>
+
+#include "adi_tmc_spi.h"
+#include "adi_tmc5xxx_common.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(tmc50xx, CONFIG_STEPPER_LOG_LEVEL);
+
+struct tmc50xx_data {
+	struct k_sem sem;
+};
+
+struct tmc50xx_config {
+	const uint32_t gconf;
+	struct spi_dt_spec spi;
+	const uint32_t clock_frequency;
+};
+
+struct tmc50xx_stepper_data {
+	struct k_work_delayable stallguard_dwork;
+	/* Work item to run the callback in a thread context. */
+#ifdef CONFIG_STEPPER_ADI_TMC50XX_RAMPSTAT_POLL
+	struct k_work_delayable rampstat_callback_dwork;
+#endif
+	/* device pointer required to access config in k_work */
+	const struct device *stepper;
+	stepper_event_callback_t callback;
+	void *event_cb_user_data;
+};
+
+struct tmc50xx_stepper_config {
+	const uint8_t index;
+	const uint16_t default_micro_step_res;
+	const int8_t sg_threshold;
+	const bool is_sg_enabled;
+	const uint32_t sg_velocity_check_interval_ms;
+	const uint32_t sg_threshold_velocity;
+	/* parent controller required for bus communication */
+	const struct device *controller;
+#ifdef CONFIG_STEPPER_ADI_TMC50XX_RAMP_GEN
+	const struct tmc_ramp_generator_data default_ramp_config;
+#endif
+};
+
+static int read_actual_position(const struct tmc50xx_stepper_config *config, int32_t *position);
+
+static int tmc50xx_write(const struct device *dev, const uint8_t reg_addr, const uint32_t reg_val)
+{
+	const struct tmc50xx_config *config = dev->config;
+	struct tmc50xx_data *data = dev->data;
+	const struct spi_dt_spec bus = config->spi;
+	int err;
+
+	k_sem_take(&data->sem, K_FOREVER);
+
+	err = tmc_spi_write_register(&bus, TMC5XXX_WRITE_BIT, reg_addr, reg_val);
+
+	k_sem_give(&data->sem);
+
+	if (err < 0) {
+		LOG_ERR("Failed to write register 0x%x with value 0x%x", reg_addr, reg_val);
+		return err;
+	}
+	return 0;
+}
+
+static int tmc50xx_read(const struct device *dev, const uint8_t reg_addr, uint32_t *reg_val)
+{
+	const struct tmc50xx_config *config = dev->config;
+	struct tmc50xx_data *data = dev->data;
+	const struct spi_dt_spec bus = config->spi;
+	int err;
+
+	k_sem_take(&data->sem, K_FOREVER);
+
+	err = tmc_spi_read_register(&bus, TMC5XXX_ADDRESS_MASK, reg_addr, reg_val);
+
+	k_sem_give(&data->sem);
+
+	if (err < 0) {
+		LOG_ERR("Failed to read register 0x%x", reg_addr);
+		return err;
+	}
+	return 0;
+}
+
+static int tmc50xx_stepper_set_event_callback(const struct device *dev,
+					      stepper_event_callback_t callback, void *user_data)
+{
+	struct tmc50xx_stepper_data *data = dev->data;
+
+	data->callback = callback;
+	data->event_cb_user_data = user_data;
+	return 0;
+}
+
+static int read_vactual(const struct tmc50xx_stepper_config *config, int32_t *actual_velocity)
+{
+	int err;
+
+	err = tmc50xx_read(config->controller, TMC50XX_VACTUAL(config->index), actual_velocity);
+	if (err) {
+		LOG_ERR("Failed to read VACTUAL register");
+		return err;
+	}
+
+	*actual_velocity = sign_extend(*actual_velocity, TMC_RAMP_VACTUAL_SHIFT);
+	if (actual_velocity) {
+		LOG_DBG("actual velocity: %d", *actual_velocity);
+	}
+	return 0;
+}
+
+static int stallguard_enable(const struct device *dev, const bool enable)
+{
+	const struct tmc50xx_stepper_config *config = dev->config;
+	uint32_t reg_value;
+	int err;
+
+	err = tmc50xx_read(config->controller, TMC50XX_SWMODE(config->index), &reg_value);
+	if (err) {
+		LOG_ERR("Failed to read SWMODE register");
+		return -EIO;
+	}
+
+	if (enable) {
+		reg_value |= TMC5XXX_SW_MODE_SG_STOP_ENABLE;
+
+		int32_t actual_velocity;
+
+		err = read_vactual(config, &actual_velocity);
+		if (err) {
+			return -EIO;
+		}
+		if (abs(actual_velocity) < config->sg_threshold_velocity) {
+			return -EAGAIN;
+		}
+	} else {
+		reg_value &= ~TMC5XXX_SW_MODE_SG_STOP_ENABLE;
+	}
+	err = tmc50xx_write(config->controller, TMC50XX_SWMODE(config->index), reg_value);
+	if (err) {
+		LOG_ERR("Failed to write SWMODE register");
+		return -EIO;
+	}
+
+	LOG_DBG("Stallguard %s", enable ? "enabled" : "disabled");
+	return 0;
+}
+
+static void stallguard_work_handler(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct tmc50xx_stepper_data *stepper_data =
+		CONTAINER_OF(dwork, struct tmc50xx_stepper_data, stallguard_dwork);
+	int err;
+	const struct tmc50xx_stepper_config *stepper_config = stepper_data->stepper->config;
+
+	err = stallguard_enable(stepper_data->stepper, true);
+	if (err == -EAGAIN) {
+		k_work_reschedule(dwork, K_MSEC(stepper_config->sg_velocity_check_interval_ms));
+	}
+	if (err == -EIO) {
+		LOG_ERR("Failed to enable stallguard because of I/O error");
+		return;
+	}
+}
+
+#ifdef CONFIG_STEPPER_ADI_TMC50XX_RAMPSTAT_POLL
+
+static void execute_callback(const struct device *dev, const enum stepper_event event)
+{
+	struct tmc50xx_stepper_data *data = dev->data;
+
+	if (!data->callback) {
+		LOG_WRN_ONCE("No callback registered");
+		return;
+	}
+	data->callback(dev, event, data->event_cb_user_data);
+}
+
+#ifdef CONFIG_STEPPER_ADI_TMC50XX_RAMPSTAT_POLL_STALLGUARD_LOG
+
+static void log_stallguard(struct tmc50xx_stepper_data *stepper_data, const uint32_t drv_status)
+{
+	const struct tmc50xx_stepper_config *stepper_config = stepper_data->stepper->config;
+	int32_t position;
+	int err;
+
+	err = read_actual_position(stepper_config, &position);
+	if (err != 0) {
+		LOG_ERR("%s: Failed to read XACTUAL register", stepper_data->stepper->name);
+		return;
+	}
+
+	const uint8_t sg_result = FIELD_GET(TMC5XXX_DRV_STATUS_SG_RESULT_MASK, drv_status);
+	const bool sg_status = FIELD_GET(TMC5XXX_DRV_STATUS_SG_STATUS_MASK, drv_status);
+
+	LOG_DBG("%s position: %d | sg result: %3d status: %d",
+		stepper_data->stepper->name, position, sg_result, sg_status);
+}
+
+#endif
+
+static void rampstat_work_reschedule(struct k_work_delayable *rampstat_callback_dwork)
+{
+	k_work_reschedule(rampstat_callback_dwork,
+		K_MSEC(CONFIG_STEPPER_ADI_TMC50XX_RAMPSTAT_POLL_INTERVAL_IN_MSEC));
+}
+
+static void rampstat_work_handler(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+
+	struct tmc50xx_stepper_data *stepper_data =
+		CONTAINER_OF(dwork, struct tmc50xx_stepper_data, rampstat_callback_dwork);
+	const struct tmc50xx_stepper_config *stepper_config = stepper_data->stepper->config;
+
+	__ASSERT_NO_MSG(stepper_config->controller != NULL);
+
+	uint32_t drv_status;
+	int err;
+
+	err = tmc50xx_read(stepper_config->controller, TMC50XX_DRVSTATUS(stepper_config->index),
+			   &drv_status);
+	if (err != 0) {
+		LOG_ERR("%s: Failed to read DRVSTATUS register", stepper_data->stepper->name);
+		return;
+	}
+#ifdef CONFIG_STEPPER_ADI_TMC50XX_RAMPSTAT_POLL_STALLGUARD_LOG
+	log_stallguard(stepper_data, drv_status);
+#endif
+	if (FIELD_GET(TMC5XXX_DRV_STATUS_SG_STATUS_MASK, drv_status) == 1U) {
+		LOG_INF("%s: Stall detected", stepper_data->stepper->name);
+		err = tmc50xx_write(stepper_config->controller,
+				    TMC50XX_RAMPMODE(stepper_config->index),
+				    TMC5XXX_RAMPMODE_HOLD_MODE);
+		if (err != 0) {
+			LOG_ERR("%s: Failed to stop motor", stepper_data->stepper->name);
+			return;
+		}
+	}
+
+	uint32_t rampstat_value;
+
+	err = tmc50xx_read(stepper_config->controller, TMC50XX_RAMPSTAT(stepper_config->index),
+			   &rampstat_value);
+	if (err != 0) {
+		LOG_ERR("%s: Failed to read RAMPSTAT register", stepper_data->stepper->name);
+		return;
+	}
+
+	const uint8_t ramp_stat_values = FIELD_GET(TMC5XXX_RAMPSTAT_INT_MASK, rampstat_value);
+
+	if (ramp_stat_values > 0) {
+		switch (ramp_stat_values) {
+
+		case TMC5XXX_STOP_LEFT_EVENT:
+			LOG_DBG("RAMPSTAT %s:Left end-stop detected", stepper_data->stepper->name);
+			execute_callback(stepper_data->stepper,
+					 STEPPER_EVENT_LEFT_END_STOP_DETECTED);
+			break;
+
+		case TMC5XXX_STOP_RIGHT_EVENT:
+			LOG_DBG("RAMPSTAT %s:Right end-stop detected", stepper_data->stepper->name);
+			execute_callback(stepper_data->stepper,
+					 STEPPER_EVENT_RIGHT_END_STOP_DETECTED);
+			break;
+
+		case TMC5XXX_POS_REACHED_EVENT:
+			LOG_DBG("RAMPSTAT %s:Position reached", stepper_data->stepper->name);
+			execute_callback(stepper_data->stepper, STEPPER_EVENT_STEPS_COMPLETED);
+			break;
+
+		case TMC5XXX_STOP_SG_EVENT:
+			LOG_DBG("RAMPSTAT %s:Stall detected", stepper_data->stepper->name);
+			stallguard_enable(stepper_data->stepper, false);
+			execute_callback(stepper_data->stepper, STEPPER_EVENT_STALL_DETECTED);
+			break;
+		default:
+			LOG_ERR("Illegal ramp stat bit field");
+			break;
+		}
+	} else {
+		rampstat_work_reschedule(&stepper_data->rampstat_callback_dwork);
+	}
+}
+
+#endif
+
+static int tmc50xx_stepper_enable(const struct device *dev)
+{
+	LOG_DBG("Enabling Stepper motor controller %s", dev->name);
+	const struct tmc50xx_stepper_config *config = dev->config;
+	uint32_t reg_value;
+	int err;
+
+	err = tmc50xx_read(config->controller, TMC50XX_CHOPCONF(config->index), &reg_value);
+	if (err != 0) {
+		return -EIO;
+	}
+
+	reg_value |= TMC5XXX_CHOPCONF_DRV_ENABLE_MASK;
+
+	return tmc50xx_write(config->controller, TMC50XX_CHOPCONF(config->index), reg_value);
+}
+
+static int tmc50xx_stepper_disable(const struct device *dev)
+{
+	LOG_DBG("Disabling Stepper motor controller %s", dev->name);
+	const struct tmc50xx_stepper_config *config = dev->config;
+	uint32_t reg_value;
+	int err;
+
+	err = tmc50xx_read(config->controller, TMC50XX_CHOPCONF(config->index), &reg_value);
+	if (err != 0) {
+		return -EIO;
+	}
+
+	reg_value &= ~TMC5XXX_CHOPCONF_DRV_ENABLE_MASK;
+
+	return tmc50xx_write(config->controller, TMC50XX_CHOPCONF(config->index), reg_value);
+}
+
+static int tmc50xx_stepper_is_moving(const struct device *dev, bool *is_moving)
+{
+	const struct tmc50xx_stepper_config *config = dev->config;
+	uint32_t reg_value;
+	int err;
+
+	err = tmc50xx_read(config->controller, TMC50XX_DRVSTATUS(config->index), &reg_value);
+
+	if (err != 0) {
+		LOG_ERR("%s: Failed to read DRVSTATUS register", dev->name);
+		return -EIO;
+	}
+
+	*is_moving = (FIELD_GET(TMC5XXX_DRV_STATUS_STST_BIT, reg_value) == 1U);
+	LOG_DBG("Stepper motor controller %s is moving: %d", dev->name, *is_moving);
+	return 0;
+}
+
+int tmc50xx_stepper_set_max_velocity(const struct device *dev, uint32_t velocity)
+{
+	const struct tmc50xx_stepper_config *config = dev->config;
+	const struct tmc50xx_config *tmc50xx_config = config->controller->config;
+	const uint32_t clock_frequency = tmc50xx_config->clock_frequency;
+	uint32_t velocity_fclk;
+	int err;
+
+	velocity_fclk = tmc5xxx_calculate_velocity_from_hz_to_fclk(velocity, clock_frequency);
+
+	err = tmc50xx_write(config->controller, TMC50XX_VMAX(config->index), velocity_fclk);
+	if (err != 0) {
+		LOG_ERR("%s: Failed to set max velocity", dev->name);
+		return -EIO;
+	}
+	return 0;
+}
+
+static int tmc50xx_stepper_set_micro_step_res(const struct device *dev,
+					      enum stepper_micro_step_resolution res)
+{
+	if (!VALID_MICRO_STEP_RES(res)) {
+		LOG_ERR("Invalid micro step resolution %d", res);
+		return -ENOTSUP;
+	}
+
+	const struct tmc50xx_stepper_config *config = dev->config;
+	uint32_t reg_value;
+	int err;
+
+	err = tmc50xx_read(config->controller, TMC50XX_CHOPCONF(config->index), &reg_value);
+	if (err != 0) {
+		return -EIO;
+	}
+
+	reg_value &= ~TMC5XXX_CHOPCONF_MRES_MASK;
+	reg_value |= ((MICRO_STEP_RES_INDEX(STEPPER_MICRO_STEP_256) - LOG2(res))
+		      << TMC5XXX_CHOPCONF_MRES_SHIFT);
+
+	err = tmc50xx_write(config->controller, TMC50XX_CHOPCONF(config->index), reg_value);
+	if (err != 0) {
+		return -EIO;
+	}
+
+	LOG_DBG("Stepper motor controller %s set micro step resolution to 0x%x", dev->name,
+		reg_value);
+	return 0;
+}
+
+static int tmc50xx_stepper_get_micro_step_res(const struct device *dev,
+					      enum stepper_micro_step_resolution *res)
+{
+	const struct tmc50xx_stepper_config *config = dev->config;
+	uint32_t reg_value;
+	int err;
+
+	err = tmc50xx_read(config->controller, TMC50XX_CHOPCONF(config->index), &reg_value);
+	if (err != 0) {
+		return -EIO;
+	}
+	reg_value &= TMC5XXX_CHOPCONF_MRES_MASK;
+	reg_value >>= TMC5XXX_CHOPCONF_MRES_SHIFT;
+	*res = (1 << (MICRO_STEP_RES_INDEX(STEPPER_MICRO_STEP_256) - reg_value));
+	LOG_DBG("Stepper motor controller %s get micro step resolution: %d", dev->name, *res);
+	return 0;
+}
+
+static int tmc50xx_stepper_set_reference_position(const struct device *dev, const int32_t position)
+{
+	const struct tmc50xx_stepper_config *config = dev->config;
+	int err;
+
+	err = tmc50xx_write(config->controller, TMC50XX_RAMPMODE(config->index),
+			    TMC5XXX_RAMPMODE_HOLD_MODE);
+	if (err != 0) {
+		return -EIO;
+	}
+
+	err = tmc50xx_write(config->controller, TMC50XX_XACTUAL(config->index), position);
+	if (err != 0) {
+		return -EIO;
+	}
+	LOG_DBG("Stepper motor controller %s set actual position to %d", dev->name, position);
+	return 0;
+}
+
+static int read_actual_position(const struct tmc50xx_stepper_config *config, int32_t *position)
+{
+	int err;
+
+	err = tmc50xx_read(config->controller, TMC50XX_XACTUAL(config->index), position);
+	if (err != 0) {
+		return -EIO;
+	}
+	return 0;
+}
+
+static int tmc50xx_stepper_get_actual_position(const struct device *dev, int32_t *position)
+{
+	const struct tmc50xx_stepper_config *config = dev->config;
+	int err;
+
+	err = read_actual_position(config, position);
+	if (err != 0) {
+		return -EIO;
+	}
+	LOG_DBG("%s actual position: %d", dev->name, *position);
+	return 0;
+}
+
+static int tmc50xx_stepper_move_to(const struct device *dev, const int32_t micro_steps)
+{
+	LOG_DBG("%s set target position to %d", dev->name, micro_steps);
+	const struct tmc50xx_stepper_config *config = dev->config;
+	struct tmc50xx_stepper_data *data = dev->data;
+	int err;
+
+	if (config->is_sg_enabled) {
+		stallguard_enable(dev, false);
+	}
+
+	err = tmc50xx_write(config->controller, TMC50XX_RAMPMODE(config->index),
+			    TMC5XXX_RAMPMODE_POSITIONING_MODE);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc50xx_write(config->controller, TMC50XX_XTARGET(config->index), micro_steps);
+	if (err != 0) {
+		return -EIO;
+	}
+
+	if (config->is_sg_enabled) {
+		k_work_reschedule(&data->stallguard_dwork,
+				  K_MSEC(config->sg_velocity_check_interval_ms));
+	}
+#ifdef CONFIG_STEPPER_ADI_TMC50XX_RAMPSTAT_POLL
+	if (data->callback) {
+		rampstat_work_reschedule(&data->rampstat_callback_dwork);
+	}
+#endif
+	return 0;
+}
+
+static int tmc50xx_stepper_move_by(const struct device *dev, const int32_t micro_steps)
+{
+	int err;
+	int32_t position;
+
+	err = stepper_get_actual_position(dev, &position);
+	if (err != 0) {
+		return -EIO;
+	}
+	int32_t target_position = position + micro_steps;
+
+	LOG_DBG("%s moved to %d by steps: %d", dev->name, target_position, micro_steps);
+
+	return tmc50xx_stepper_move_to(dev, target_position);
+}
+
+static int tmc50xx_stepper_run(const struct device *dev, const enum stepper_direction direction)
+{
+	LOG_DBG("Stepper motor controller %s run", dev->name);
+	const struct tmc50xx_stepper_config *config = dev->config;
+	struct tmc50xx_stepper_data *data = dev->data;
+	int err;
+
+	if (config->is_sg_enabled) {
+		err = stallguard_enable(dev, false);
+		if (err != 0) {
+			return -EIO;
+		}
+	}
+
+	switch (direction) {
+	case STEPPER_DIRECTION_POSITIVE:
+		err = tmc50xx_write(config->controller, TMC50XX_RAMPMODE(config->index),
+				    TMC5XXX_RAMPMODE_POSITIVE_VELOCITY_MODE);
+		if (err != 0) {
+			return -EIO;
+		}
+		break;
+
+	case STEPPER_DIRECTION_NEGATIVE:
+		err = tmc50xx_write(config->controller, TMC50XX_RAMPMODE(config->index),
+				    TMC5XXX_RAMPMODE_NEGATIVE_VELOCITY_MODE);
+		if (err != 0) {
+			return -EIO;
+		}
+		break;
+	}
+
+	if (config->is_sg_enabled) {
+		k_work_reschedule(&data->stallguard_dwork,
+				  K_MSEC(config->sg_velocity_check_interval_ms));
+	}
+#ifdef CONFIG_STEPPER_ADI_TMC50XX_RAMPSTAT_POLL
+	if (data->callback) {
+		rampstat_work_reschedule(&data->rampstat_callback_dwork);
+	}
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_STEPPER_ADI_TMC50XX_RAMP_GEN
+
+int tmc50xx_stepper_set_ramp(const struct device *dev,
+			     const struct tmc_ramp_generator_data *ramp_data)
+{
+	LOG_DBG("Stepper motor controller %s set ramp", dev->name);
+	const struct tmc50xx_stepper_config *config = dev->config;
+	int err;
+
+	err = tmc50xx_write(config->controller, TMC50XX_VSTART(config->index), ramp_data->vstart);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc50xx_write(config->controller, TMC50XX_A1(config->index), ramp_data->a1);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc50xx_write(config->controller, TMC50XX_AMAX(config->index), ramp_data->amax);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc50xx_write(config->controller, TMC50XX_D1(config->index), ramp_data->d1);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc50xx_write(config->controller, TMC50XX_DMAX(config->index), ramp_data->dmax);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc50xx_write(config->controller, TMC50XX_V1(config->index), ramp_data->v1);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc50xx_write(config->controller, TMC50XX_VMAX(config->index), ramp_data->vmax);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc50xx_write(config->controller, TMC50XX_VSTOP(config->index), ramp_data->vstop);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc50xx_write(config->controller, TMC50XX_TZEROWAIT(config->index),
+			    ramp_data->tzerowait);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc50xx_write(config->controller, TMC50XX_VHIGH(config->index), ramp_data->vhigh);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc50xx_write(config->controller, TMC50XX_VCOOLTHRS(config->index),
+			    ramp_data->vcoolthrs);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc50xx_write(config->controller, TMC50XX_IHOLD_IRUN(config->index),
+			    ramp_data->iholdrun);
+	if (err != 0) {
+		return -EIO;
+	}
+	return 0;
+}
+
+#endif
+
+static int tmc50xx_init(const struct device *dev)
+{
+	LOG_DBG("TMC50XX stepper motor controller %s initialized", dev->name);
+	struct tmc50xx_data *data = dev->data;
+	const struct tmc50xx_config *config = dev->config;
+	int err;
+
+	k_sem_init(&data->sem, 1, 1);
+
+	if (!spi_is_ready_dt(&config->spi)) {
+		LOG_ERR("SPI bus is not ready");
+		return -ENODEV;
+	}
+
+	/* Init non motor-index specific registers here. */
+	LOG_DBG("GCONF: %d", config->gconf);
+	err = tmc50xx_write(dev, TMC5XXX_GCONF, config->gconf);
+	if (err != 0) {
+		return -EIO;
+	}
+
+	/* Read GSTAT register values to clear any errors SPI Datagram. */
+	uint32_t gstat_value;
+
+	err = tmc50xx_read(dev, TMC5XXX_GSTAT, &gstat_value);
+	if (err != 0) {
+		return -EIO;
+	}
+
+	LOG_DBG("Device %s initialized", dev->name);
+	return 0;
+}
+
+static int tmc50xx_stepper_init(const struct device *dev)
+{
+	const struct tmc50xx_stepper_config *stepper_config = dev->config;
+	struct tmc50xx_stepper_data *data = dev->data;
+	int err;
+
+	LOG_DBG("Controller: %s, Stepper: %s", stepper_config->controller->name, dev->name);
+
+	if (stepper_config->is_sg_enabled) {
+		k_work_init_delayable(&data->stallguard_dwork, stallguard_work_handler);
+
+		err = tmc50xx_write(stepper_config->controller,
+				    TMC50XX_SWMODE(stepper_config->index), BIT(10));
+		if (err != 0) {
+			return -EIO;
+		}
+
+		LOG_DBG("Setting stall guard to %d with delay %d ms", stepper_config->sg_threshold,
+			stepper_config->sg_velocity_check_interval_ms);
+		if (!IN_RANGE(stepper_config->sg_threshold, TMC5XXX_SG_MIN_VALUE,
+			      TMC5XXX_SG_MAX_VALUE)) {
+			LOG_ERR("Stallguard threshold out of range");
+			return -EINVAL;
+		}
+
+		int32_t stall_guard_threshold = (int32_t)stepper_config->sg_threshold;
+
+		err = tmc50xx_write(
+			stepper_config->controller, TMC50XX_COOLCONF(stepper_config->index),
+			stall_guard_threshold << TMC5XXX_COOLCONF_SG2_THRESHOLD_VALUE_SHIFT);
+		if (err != 0) {
+			return -EIO;
+		}
+		k_work_reschedule(&data->stallguard_dwork, K_NO_WAIT);
+	}
+
+#ifdef CONFIG_STEPPER_ADI_TMC50XX_RAMP_GEN
+	err = tmc50xx_stepper_set_ramp(dev, &stepper_config->default_ramp_config);
+	if (err != 0) {
+		return -EIO;
+	}
+#endif
+
+#if CONFIG_STEPPER_ADI_TMC50XX_RAMPSTAT_POLL
+	k_work_init_delayable(&data->rampstat_callback_dwork, rampstat_work_handler);
+	rampstat_work_reschedule(&data->rampstat_callback_dwork);
+#endif
+	err = tmc50xx_stepper_set_micro_step_res(dev, stepper_config->default_micro_step_res);
+	if (err != 0) {
+		return -EIO;
+	}
+	return 0;
+}
+
+static DEVICE_API(stepper, tmc50xx_stepper_api) = {
+	.enable = tmc50xx_stepper_enable,
+	.disable = tmc50xx_stepper_disable,
+	.is_moving = tmc50xx_stepper_is_moving,
+	.move_by = tmc50xx_stepper_move_by,
+	.set_micro_step_res = tmc50xx_stepper_set_micro_step_res,
+	.get_micro_step_res = tmc50xx_stepper_get_micro_step_res,
+	.set_reference_position = tmc50xx_stepper_set_reference_position,
+	.get_actual_position = tmc50xx_stepper_get_actual_position,
+	.move_to = tmc50xx_stepper_move_to,
+	.run = tmc50xx_stepper_run,
+	.set_event_callback = tmc50xx_stepper_set_event_callback,
+};
+
+#define TMC50XX_SHAFT_CONFIG(child)								\
+	(DT_PROP(child, invert_direction) << TMC50XX_GCONF_SHAFT_SHIFT(DT_REG_ADDR(child))) |
+
+#define TMC50XX_STEPPER_CONFIG_DEFINE(child)							\
+	COND_CODE_1(DT_PROP_EXISTS(child, stallguard_threshold_velocity),			\
+	BUILD_ASSERT(DT_PROP(child, stallguard_threshold_velocity),				\
+		     "stallguard threshold velocity must be a positive value"), ());		\
+	IF_ENABLED(CONFIG_STEPPER_ADI_TMC50XX_RAMP_GEN, (CHECK_RAMP_DT_DATA(child)));		\
+	static const struct tmc50xx_stepper_config tmc50xx_stepper_config_##child = {		\
+		.controller = DEVICE_DT_GET(DT_PARENT(child)),					\
+		.default_micro_step_res = DT_PROP(child, micro_step_res),			\
+		.index = DT_REG_ADDR(child),							\
+		.sg_threshold = DT_PROP(child, stallguard2_threshold),				\
+		.sg_threshold_velocity = DT_PROP(child, stallguard_threshold_velocity),		\
+		.sg_velocity_check_interval_ms = DT_PROP(child,					\
+						stallguard_velocity_check_interval_ms),		\
+		.is_sg_enabled = DT_PROP(child, activate_stallguard2),				\
+		IF_ENABLED(CONFIG_STEPPER_ADI_TMC50XX_RAMP_GEN,					\
+		(.default_ramp_config = TMC_RAMP_DT_SPEC_GET_TMC50XX(child))) };
+
+#define TMC50XX_STEPPER_DATA_DEFINE(child)							\
+	static struct tmc50xx_stepper_data tmc50xx_stepper_data_##child = {			\
+		.stepper = DEVICE_DT_GET(child),};
+
+#define TMC50XX_STEPPER_DEFINE(child)								\
+	DEVICE_DT_DEFINE(child, tmc50xx_stepper_init, NULL, &tmc50xx_stepper_data_##child,	\
+			 &tmc50xx_stepper_config_##child, POST_KERNEL,				\
+			 CONFIG_STEPPER_INIT_PRIORITY, &tmc50xx_stepper_api);
+
+#define TMC50XX_DEFINE(inst)									\
+	BUILD_ASSERT(DT_INST_CHILD_NUM(inst) <= 2, "tmc50xx can drive two steppers at max");	\
+	BUILD_ASSERT((DT_INST_PROP(inst, clock_frequency) > 0),					\
+		     "clock frequency must be non-zero positive value");			\
+	static struct tmc50xx_data tmc50xx_data_##inst;						\
+	static const struct tmc50xx_config tmc50xx_config_##inst = {				\
+		.gconf = (									\
+		(DT_INST_PROP(inst, poscmp_enable) << TMC50XX_GCONF_POSCMP_ENABLE_SHIFT) |	\
+		(DT_INST_PROP(inst, test_mode) << TMC50XX_GCONF_TEST_MODE_SHIFT) |		\
+		DT_INST_FOREACH_CHILD(inst, TMC50XX_SHAFT_CONFIG)				\
+		(DT_INST_PROP(inst, lock_gconf) << TMC50XX_LOCK_GCONF_SHIFT)),			\
+		.spi = SPI_DT_SPEC_INST_GET(inst, (SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB |	\
+					SPI_MODE_CPOL | SPI_MODE_CPHA |	SPI_WORD_SET(8)), 0),	\
+		.clock_frequency = DT_INST_PROP(inst, clock_frequency),};			\
+	DT_INST_FOREACH_CHILD(inst, TMC50XX_STEPPER_CONFIG_DEFINE);				\
+	DT_INST_FOREACH_CHILD(inst, TMC50XX_STEPPER_DATA_DEFINE);				\
+	DT_INST_FOREACH_CHILD(inst, TMC50XX_STEPPER_DEFINE);					\
+	DEVICE_DT_INST_DEFINE(inst, tmc50xx_init, NULL, &tmc50xx_data_##inst,			\
+			      &tmc50xx_config_##inst, POST_KERNEL, CONFIG_STEPPER_INIT_PRIORITY,\
+			      NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(TMC50XX_DEFINE)
diff --git a/drivers/stepper/adi_tmc/tmc51xx.c b/drivers/stepper/adi_tmc/tmc51xx.c
new file mode 100644
index 00000000000..965fb3460ca
--- /dev/null
+++ b/drivers/stepper/adi_tmc/tmc51xx.c
@@ -0,0 +1,744 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2025 Prevas A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT adi_tmc51xx
+
+#include <stdlib.h>
+
+#include <zephyr/drivers/stepper.h>
+#include <zephyr/drivers/stepper/stepper_trinamic.h>
+
+#include "adi_tmc_spi.h"
+#include "adi_tmc5xxx_common.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(tmc51xx, CONFIG_STEPPER_LOG_LEVEL);
+
+struct tmc51xx_data {
+	struct k_sem sem;
+	struct k_work_delayable stallguard_dwork;
+	/* Work item to run the callback in a thread context. */
+#ifdef CONFIG_STEPPER_ADI_TMC51XX_RAMPSTAT_POLL
+	struct k_work_delayable rampstat_callback_dwork;
+#endif
+	/* device pointer required to access config in k_work */
+	const struct device *stepper;
+	stepper_event_callback_t callback;
+	void *event_cb_user_data;
+};
+
+struct tmc51xx_config {
+	const uint32_t gconf;
+	struct spi_dt_spec spi;
+	const uint32_t clock_frequency;
+	const uint16_t default_micro_step_res;
+	const int8_t sg_threshold;
+	const bool is_sg_enabled;
+	const uint32_t sg_velocity_check_interval_ms;
+	const uint32_t sg_threshold_velocity;
+#ifdef CONFIG_STEPPER_ADI_TMC51XX_RAMP_GEN
+	const struct tmc_ramp_generator_data default_ramp_config;
+#endif
+};
+
+static int read_actual_position(const struct device *dev, int32_t *position);
+
+static int tmc51xx_write(const struct device *dev, const uint8_t reg_addr, const uint32_t reg_val)
+{
+	const struct tmc51xx_config *config = dev->config;
+	struct tmc51xx_data *data = dev->data;
+	const struct spi_dt_spec bus = config->spi;
+	int err;
+
+	k_sem_take(&data->sem, K_FOREVER);
+
+	err = tmc_spi_write_register(&bus, TMC5XXX_WRITE_BIT, reg_addr, reg_val);
+
+	k_sem_give(&data->sem);
+
+	if (err < 0) {
+		LOG_ERR("Failed to write register 0x%x with value 0x%x", reg_addr, reg_val);
+		return err;
+	}
+	return 0;
+}
+
+static int tmc51xx_read(const struct device *dev, const uint8_t reg_addr, uint32_t *reg_val)
+{
+	const struct tmc51xx_config *config = dev->config;
+	struct tmc51xx_data *data = dev->data;
+	const struct spi_dt_spec bus = config->spi;
+	int err;
+
+	k_sem_take(&data->sem, K_FOREVER);
+
+	err = tmc_spi_read_register(&bus, TMC5XXX_ADDRESS_MASK, reg_addr, reg_val);
+
+	k_sem_give(&data->sem);
+
+	if (err < 0) {
+		LOG_ERR("Failed to read register 0x%x", reg_addr);
+		return err;
+	}
+	return 0;
+}
+
+static int tmc51xx_stepper_set_event_callback(const struct device *dev,
+					      stepper_event_callback_t callback, void *user_data)
+{
+	struct tmc51xx_data *data = dev->data;
+
+	data->callback = callback;
+	data->event_cb_user_data = user_data;
+	return 0;
+}
+
+static int read_vactual(const struct device *dev, int32_t *actual_velocity)
+{
+	int err;
+
+	err = tmc51xx_read(dev, TMC51XX_VACTUAL, actual_velocity);
+	if (err) {
+		LOG_ERR("Failed to read VACTUAL register");
+		return err;
+	}
+
+	*actual_velocity = sign_extend(*actual_velocity, TMC_RAMP_VACTUAL_SHIFT);
+	if (*actual_velocity) {
+		LOG_DBG("actual velocity: %d", *actual_velocity);
+	}
+	return 0;
+}
+
+static int stallguard_enable(const struct device *dev, const bool enable)
+{
+	const struct tmc51xx_config *config = dev->config;
+	uint32_t reg_value;
+	int err;
+
+	err = tmc51xx_read(dev, TMC51XX_SWMODE, &reg_value);
+	if (err) {
+		LOG_ERR("Failed to read SWMODE register");
+		return -EIO;
+	}
+
+	if (enable) {
+		reg_value |= TMC5XXX_SW_MODE_SG_STOP_ENABLE;
+
+		int32_t actual_velocity;
+
+		err = read_vactual(dev, &actual_velocity);
+		if (err) {
+			return -EIO;
+		}
+		if (abs(actual_velocity) < config->sg_threshold_velocity) {
+			return -EAGAIN;
+		}
+	} else {
+		reg_value &= ~TMC5XXX_SW_MODE_SG_STOP_ENABLE;
+	}
+	err = tmc51xx_write(dev, TMC51XX_SWMODE, reg_value);
+	if (err) {
+		LOG_ERR("Failed to write SWMODE register");
+		return -EIO;
+	}
+
+	LOG_DBG("Stallguard %s", enable ? "enabled" : "disabled");
+	return 0;
+}
+
+static void stallguard_work_handler(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct tmc51xx_data *stepper_data =
+		CONTAINER_OF(dwork, struct tmc51xx_data, stallguard_dwork);
+	const struct device *dev = stepper_data->stepper;
+	const struct tmc51xx_config *config = dev->config;
+	int err;
+
+	err = stallguard_enable(dev, true);
+	if (err == -EAGAIN) {
+		k_work_reschedule(dwork, K_MSEC(config->sg_velocity_check_interval_ms));
+	}
+	if (err == -EIO) {
+		LOG_ERR("Failed to enable stallguard because of I/O error");
+		return;
+	}
+}
+
+#ifdef CONFIG_STEPPER_ADI_TMC51XX_RAMPSTAT_POLL
+
+static void execute_callback(const struct device *dev, const enum stepper_event event)
+{
+	struct tmc51xx_data *data = dev->data;
+
+	if (!data->callback) {
+		LOG_WRN_ONCE("No callback registered");
+		return;
+	}
+	data->callback(dev, event, data->event_cb_user_data);
+}
+
+#ifdef CONFIG_STEPPER_ADI_TMC51XX_RAMPSTAT_POLL_STALLGUARD_LOG
+
+static void log_stallguard(const struct device *dev, const uint32_t drv_status)
+{
+	int32_t position;
+	int err;
+
+	err = read_actual_position(dev, &position);
+	if (err != 0) {
+		LOG_ERR("%s: Failed to read XACTUAL register", dev->name);
+		return;
+	}
+
+	const uint8_t sg_result = FIELD_GET(TMC5XXX_DRV_STATUS_SG_RESULT_MASK, drv_status);
+	const bool sg_status = FIELD_GET(TMC5XXX_DRV_STATUS_SG_STATUS_MASK, drv_status);
+
+	LOG_DBG("%s position: %d | sg result: %3d status: %d",
+		dev->name, position, sg_result, sg_status);
+}
+
+#endif
+
+static void rampstat_work_reschedule(struct k_work_delayable *rampstat_callback_dwork)
+{
+	k_work_reschedule(rampstat_callback_dwork,
+		K_MSEC(CONFIG_STEPPER_ADI_TMC51XX_RAMPSTAT_POLL_INTERVAL_IN_MSEC));
+}
+
+static int rampstat_read_clear(const struct device *dev, uint32_t *rampstat_value)
+{
+	int err;
+
+	err = tmc51xx_read(dev, TMC51XX_RAMPSTAT, rampstat_value);
+	if (err == 0) {
+		err = tmc51xx_write(dev, TMC51XX_RAMPSTAT, *rampstat_value);
+	}
+	return err;
+}
+
+static void rampstat_work_handler(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+
+	struct tmc51xx_data *stepper_data =
+		CONTAINER_OF(dwork, struct tmc51xx_data, rampstat_callback_dwork);
+	const struct device *dev = stepper_data->stepper;
+
+	__ASSERT_NO_MSG(dev != NULL);
+
+	uint32_t drv_status;
+	int err;
+
+	err = tmc51xx_read(dev, TMC51XX_DRVSTATUS,
+			   &drv_status);
+	if (err != 0) {
+		LOG_ERR("%s: Failed to read DRVSTATUS register", dev->name);
+		return;
+	}
+#ifdef CONFIG_STEPPER_ADI_TMC51XX_RAMPSTAT_POLL_STALLGUARD_LOG
+	log_stallguard(dev, drv_status);
+#endif
+	if (FIELD_GET(TMC5XXX_DRV_STATUS_SG_STATUS_MASK, drv_status) == 1U) {
+		LOG_INF("%s: Stall detected", dev->name);
+		err = tmc51xx_write(dev,
+				    TMC51XX_RAMPMODE,
+				    TMC5XXX_RAMPMODE_HOLD_MODE);
+		if (err != 0) {
+			LOG_ERR("%s: Failed to stop motor", dev->name);
+			return;
+		}
+	}
+
+	uint32_t rampstat_value;
+
+	err = rampstat_read_clear(dev, &rampstat_value);
+	if (err != 0) {
+		LOG_ERR("%s: Failed to read RAMPSTAT register", dev->name);
+		return;
+	}
+
+	const uint8_t ramp_stat_values = FIELD_GET(TMC5XXX_RAMPSTAT_INT_MASK, rampstat_value);
+
+	if (ramp_stat_values > 0) {
+		switch (ramp_stat_values) {
+
+		case TMC5XXX_STOP_LEFT_EVENT:
+			LOG_DBG("RAMPSTAT %s:Left end-stop detected", dev->name);
+			execute_callback(dev,
+					 STEPPER_EVENT_LEFT_END_STOP_DETECTED);
+			break;
+
+		case TMC5XXX_STOP_RIGHT_EVENT:
+			LOG_DBG("RAMPSTAT %s:Right end-stop detected", dev->name);
+			execute_callback(dev,
+					 STEPPER_EVENT_RIGHT_END_STOP_DETECTED);
+			break;
+
+		case TMC5XXX_POS_REACHED_EVENT:
+			LOG_DBG("RAMPSTAT %s:Position reached", dev->name);
+			execute_callback(dev, STEPPER_EVENT_STEPS_COMPLETED);
+			break;
+
+		case TMC5XXX_STOP_SG_EVENT:
+			LOG_DBG("RAMPSTAT %s:Stall detected", dev->name);
+			stallguard_enable(dev, false);
+			execute_callback(dev, STEPPER_EVENT_STALL_DETECTED);
+			break;
+		default:
+			LOG_ERR("Illegal ramp stat bit field");
+			break;
+		}
+	} else {
+		rampstat_work_reschedule(&stepper_data->rampstat_callback_dwork);
+	}
+}
+
+#endif
+
+static int tmc51xx_stepper_enable(const struct device *dev)
+{
+	LOG_DBG("Enabling Stepper motor controller %s", dev->name);
+	uint32_t reg_value;
+	int err;
+
+	err = tmc51xx_read(dev, TMC51XX_CHOPCONF, &reg_value);
+	if (err != 0) {
+		return -EIO;
+	}
+
+	reg_value |= TMC5XXX_CHOPCONF_DRV_ENABLE_MASK;
+
+	return tmc51xx_write(dev, TMC51XX_CHOPCONF, reg_value);
+}
+
+static int tmc51xx_stepper_disable(const struct device *dev)
+{
+	LOG_DBG("Disabling Stepper motor controller %s", dev->name);
+	uint32_t reg_value;
+	int err;
+
+	err = tmc51xx_read(dev, TMC51XX_CHOPCONF, &reg_value);
+	if (err != 0) {
+		return -EIO;
+	}
+
+	reg_value &= ~TMC5XXX_CHOPCONF_DRV_ENABLE_MASK;
+
+	return tmc51xx_write(dev, TMC51XX_CHOPCONF, reg_value);
+}
+
+static int tmc51xx_stepper_is_moving(const struct device *dev, bool *is_moving)
+{
+	uint32_t reg_value;
+	int err;
+
+	err = tmc51xx_read(dev, TMC51XX_DRVSTATUS, &reg_value);
+
+	if (err != 0) {
+		LOG_ERR("%s: Failed to read DRVSTATUS register", dev->name);
+		return -EIO;
+	}
+
+	*is_moving = (FIELD_GET(TMC5XXX_DRV_STATUS_STST_BIT, reg_value) == 1U);
+	LOG_DBG("Stepper motor controller %s is moving: %d", dev->name, *is_moving);
+	return 0;
+}
+
+int tmc51xx_stepper_set_max_velocity(const struct device *dev, uint32_t velocity)
+{
+	const struct tmc51xx_config *config = dev->config;
+	const uint32_t clock_frequency = config->clock_frequency;
+	uint32_t velocity_fclk;
+	int err;
+
+	velocity_fclk = tmc5xxx_calculate_velocity_from_hz_to_fclk(velocity, clock_frequency);
+
+	err = tmc51xx_write(dev, TMC51XX_VMAX, velocity_fclk);
+	if (err != 0) {
+		LOG_ERR("%s: Failed to set max velocity", dev->name);
+		return -EIO;
+	}
+	return 0;
+}
+
+static int tmc51xx_stepper_set_micro_step_res(const struct device *dev,
+					      enum stepper_micro_step_resolution res)
+{
+	if (!VALID_MICRO_STEP_RES(res)) {
+		LOG_ERR("Invalid micro step resolution %d", res);
+		return -ENOTSUP;
+	}
+
+	uint32_t reg_value;
+	int err;
+
+	err = tmc51xx_read(dev, TMC51XX_CHOPCONF, &reg_value);
+	if (err != 0) {
+		return -EIO;
+	}
+
+	reg_value &= ~TMC5XXX_CHOPCONF_MRES_MASK;
+	reg_value |= ((MICRO_STEP_RES_INDEX(STEPPER_MICRO_STEP_256) - LOG2(res))
+		      << TMC5XXX_CHOPCONF_MRES_SHIFT);
+
+	err = tmc51xx_write(dev, TMC51XX_CHOPCONF, reg_value);
+	if (err != 0) {
+		return -EIO;
+	}
+
+	LOG_DBG("Stepper motor controller %s set micro step resolution to 0x%x", dev->name,
+		reg_value);
+	return 0;
+}
+
+static int tmc51xx_stepper_get_micro_step_res(const struct device *dev,
+					      enum stepper_micro_step_resolution *res)
+{
+	uint32_t reg_value;
+	int err;
+
+	err = tmc51xx_read(dev, TMC51XX_CHOPCONF, &reg_value);
+	if (err != 0) {
+		return -EIO;
+	}
+	reg_value &= TMC5XXX_CHOPCONF_MRES_MASK;
+	reg_value >>= TMC5XXX_CHOPCONF_MRES_SHIFT;
+	*res = (1 << (MICRO_STEP_RES_INDEX(STEPPER_MICRO_STEP_256) - reg_value));
+	LOG_DBG("Stepper motor controller %s get micro step resolution: %d", dev->name, *res);
+	return 0;
+}
+
+static int tmc51xx_stepper_set_reference_position(const struct device *dev, const int32_t position)
+{
+	int err;
+
+	err = tmc51xx_write(dev, TMC51XX_RAMPMODE,
+			    TMC5XXX_RAMPMODE_HOLD_MODE);
+	if (err != 0) {
+		return -EIO;
+	}
+
+	err = tmc51xx_write(dev, TMC51XX_XACTUAL, position);
+	if (err != 0) {
+		return -EIO;
+	}
+	LOG_DBG("Stepper motor controller %s set actual position to %d", dev->name, position);
+	return 0;
+}
+
+static int read_actual_position(const struct device *dev, int32_t *position)
+{
+	int err;
+
+	err = tmc51xx_read(dev, TMC51XX_XACTUAL, position);
+	if (err != 0) {
+		return -EIO;
+	}
+	return 0;
+}
+
+static int tmc51xx_stepper_get_actual_position(const struct device *dev, int32_t *position)
+{
+	int err;
+
+	err = read_actual_position(dev, position);
+	if (err != 0) {
+		return -EIO;
+	}
+	LOG_DBG("%s actual position: %d", dev->name, *position);
+	return 0;
+}
+
+static int tmc51xx_stepper_move_to(const struct device *dev, const int32_t micro_steps)
+{
+	LOG_DBG("%s set target position to %d", dev->name, micro_steps);
+	const struct tmc51xx_config *config = dev->config;
+	struct tmc51xx_data *data = dev->data;
+	int err;
+
+	if (config->is_sg_enabled) {
+		stallguard_enable(dev, false);
+	}
+
+	err = tmc51xx_write(dev, TMC51XX_RAMPMODE,
+			    TMC5XXX_RAMPMODE_POSITIONING_MODE);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc51xx_write(dev, TMC51XX_XTARGET, micro_steps);
+	if (err != 0) {
+		return -EIO;
+	}
+
+	if (config->is_sg_enabled) {
+		k_work_reschedule(&data->stallguard_dwork,
+				  K_MSEC(config->sg_velocity_check_interval_ms));
+	}
+#ifdef CONFIG_STEPPER_ADI_TMC51XX_RAMPSTAT_POLL
+	if (data->callback) {
+		rampstat_work_reschedule(&data->rampstat_callback_dwork);
+	}
+#endif
+	return 0;
+}
+
+static int tmc51xx_stepper_move_by(const struct device *dev, const int32_t micro_steps)
+{
+	int err;
+	int32_t position;
+
+	err = stepper_get_actual_position(dev, &position);
+	if (err != 0) {
+		return -EIO;
+	}
+	int32_t target_position = position + micro_steps;
+
+	LOG_DBG("%s moved to %d by steps: %d", dev->name, target_position, micro_steps);
+
+	return tmc51xx_stepper_move_to(dev, target_position);
+}
+
+static int tmc51xx_stepper_run(const struct device *dev, const enum stepper_direction direction)
+{
+	LOG_DBG("Stepper motor controller %s run", dev->name);
+	const struct tmc51xx_config *config = dev->config;
+	struct tmc51xx_data *data = dev->data;
+	int err;
+
+	if (config->is_sg_enabled) {
+		err = stallguard_enable(dev, false);
+		if (err != 0) {
+			return -EIO;
+		}
+	}
+
+	switch (direction) {
+	case STEPPER_DIRECTION_POSITIVE:
+		err = tmc51xx_write(dev, TMC51XX_RAMPMODE,
+				    TMC5XXX_RAMPMODE_POSITIVE_VELOCITY_MODE);
+		if (err != 0) {
+			return -EIO;
+		}
+		break;
+
+	case STEPPER_DIRECTION_NEGATIVE:
+		err = tmc51xx_write(dev, TMC51XX_RAMPMODE,
+				    TMC5XXX_RAMPMODE_NEGATIVE_VELOCITY_MODE);
+		if (err != 0) {
+			return -EIO;
+		}
+		break;
+	}
+
+	if (config->is_sg_enabled) {
+		k_work_reschedule(&data->stallguard_dwork,
+				  K_MSEC(config->sg_velocity_check_interval_ms));
+	}
+#ifdef CONFIG_STEPPER_ADI_TMC51XX_RAMPSTAT_POLL
+	if (data->callback) {
+		rampstat_work_reschedule(&data->rampstat_callback_dwork);
+	}
+#endif
+	return 0;
+}
+
+#ifdef CONFIG_STEPPER_ADI_TMC51XX_RAMP_GEN
+
+int tmc51xx_stepper_set_ramp(const struct device *dev,
+			     const struct tmc_ramp_generator_data *ramp_data)
+{
+	LOG_DBG("Stepper motor controller %s set ramp", dev->name);
+	int err;
+
+	err = tmc51xx_write(dev, TMC51XX_VSTART, ramp_data->vstart);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc51xx_write(dev, TMC51XX_A1, ramp_data->a1);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc51xx_write(dev, TMC51XX_AMAX, ramp_data->amax);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc51xx_write(dev, TMC51XX_D1, ramp_data->d1);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc51xx_write(dev, TMC51XX_DMAX, ramp_data->dmax);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc51xx_write(dev, TMC51XX_V1, ramp_data->v1);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc51xx_write(dev, TMC51XX_VMAX, ramp_data->vmax);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc51xx_write(dev, TMC51XX_VSTOP, ramp_data->vstop);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc51xx_write(dev, TMC51XX_TZEROWAIT,
+			    ramp_data->tzerowait);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc51xx_write(dev, TMC51XX_THIGH, ramp_data->thigh);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc51xx_write(dev, TMC51XX_TCOOLTHRS, ramp_data->tcoolthrs);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc51xx_write(dev, TMC51XX_TPWMTHRS, ramp_data->tpwmthrs);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc51xx_write(dev, TMC51XX_TPOWER_DOWN, ramp_data->tpowerdown);
+	if (err != 0) {
+		return -EIO;
+	}
+	err = tmc51xx_write(dev, TMC51XX_IHOLD_IRUN, ramp_data->iholdrun);
+	if (err != 0) {
+		return -EIO;
+	}
+	return 0;
+}
+
+#endif
+
+static int tmc51xx_init(const struct device *dev)
+{
+	LOG_DBG("TMC51XX stepper motor controller %s initialized", dev->name);
+	struct tmc51xx_data *data = dev->data;
+	const struct tmc51xx_config *config = dev->config;
+	int err;
+
+	k_sem_init(&data->sem, 1, 1);
+
+	if (!spi_is_ready_dt(&config->spi)) {
+		LOG_ERR("SPI bus is not ready");
+		return -ENODEV;
+	}
+
+	LOG_DBG("GCONF: %d", config->gconf);
+	err = tmc51xx_write(dev, TMC5XXX_GCONF, config->gconf);
+	if (err != 0) {
+		return -EIO;
+	}
+
+	/* Read and write GSTAT register to clear any SPI Datagram errors. */
+	uint32_t gstat_value;
+
+	err = tmc51xx_read(dev, TMC5XXX_GSTAT, &gstat_value);
+	if (err != 0) {
+		return -EIO;
+	}
+
+	err = tmc51xx_write(dev, TMC5XXX_GSTAT, gstat_value);
+	if (err != 0) {
+		return -EIO;
+	}
+
+	if (config->is_sg_enabled) {
+		k_work_init_delayable(&data->stallguard_dwork, stallguard_work_handler);
+
+		err = tmc51xx_write(dev,
+				    TMC51XX_SWMODE, BIT(10));
+		if (err != 0) {
+			return -EIO;
+		}
+
+		LOG_DBG("Setting stall guard to %d with delay %d ms", config->sg_threshold,
+			config->sg_velocity_check_interval_ms);
+		if (!IN_RANGE(config->sg_threshold, TMC5XXX_SG_MIN_VALUE,
+			      TMC5XXX_SG_MAX_VALUE)) {
+			LOG_ERR("Stallguard threshold out of range");
+			return -EINVAL;
+		}
+
+		int32_t stall_guard_threshold = (int32_t)config->sg_threshold;
+
+		err = tmc51xx_write(
+			dev, TMC51XX_COOLCONF,
+			stall_guard_threshold << TMC5XXX_COOLCONF_SG2_THRESHOLD_VALUE_SHIFT);
+		if (err != 0) {
+			return -EIO;
+		}
+		k_work_reschedule(&data->stallguard_dwork, K_NO_WAIT);
+	}
+
+#ifdef CONFIG_STEPPER_ADI_TMC51XX_RAMP_GEN
+	err = tmc51xx_stepper_set_ramp(dev, &config->default_ramp_config);
+	if (err != 0) {
+		return -EIO;
+	}
+#endif
+
+#if CONFIG_STEPPER_ADI_TMC51XX_RAMPSTAT_POLL
+	k_work_init_delayable(&data->rampstat_callback_dwork, rampstat_work_handler);
+	uint32_t rampstat_value;
+
+	(void)rampstat_read_clear(dev, &rampstat_value);
+#endif
+	err = tmc51xx_stepper_set_micro_step_res(dev, config->default_micro_step_res);
+	if (err != 0) {
+		return -EIO;
+	}
+	return 0;
+}
+
+static DEVICE_API(stepper, tmc51xx_api) = {
+	.enable = tmc51xx_stepper_enable,
+	.disable = tmc51xx_stepper_disable,
+	.is_moving = tmc51xx_stepper_is_moving,
+	.move_by = tmc51xx_stepper_move_by,
+	.set_micro_step_res = tmc51xx_stepper_set_micro_step_res,
+	.get_micro_step_res = tmc51xx_stepper_get_micro_step_res,
+	.set_reference_position = tmc51xx_stepper_set_reference_position,
+	.get_actual_position = tmc51xx_stepper_get_actual_position,
+	.move_to = tmc51xx_stepper_move_to,
+	.run = tmc51xx_stepper_run,
+	.set_event_callback = tmc51xx_stepper_set_event_callback,
+};
+
+#define TMC51XX_DEFINE(inst)									\
+	BUILD_ASSERT((DT_INST_PROP(inst, clock_frequency) > 0),					\
+		     "clock frequency must be non-zero positive value");			\
+	static struct tmc51xx_data tmc51xx_data_##inst = {					\
+		.stepper = DEVICE_DT_GET(DT_DRV_INST(inst))};					\
+	COND_CODE_1(DT_PROP_EXISTS(inst, stallguard_threshold_velocity),			\
+	BUILD_ASSERT(DT_PROP(inst, stallguard_threshold_velocity),				\
+		     "stallguard threshold velocity must be a positive value"), ());		\
+	IF_ENABLED(CONFIG_STEPPER_ADI_TMC51XX_RAMP_GEN, (CHECK_RAMP_DT_DATA(inst)));		\
+	static const struct tmc51xx_config tmc51xx_config_##inst = {				\
+		.gconf = (									\
+		(DT_INST_PROP(inst, en_pwm_mode) << TMC51XX_GCONF_EN_PWM_MODE_SHIFT) |		\
+		(DT_INST_PROP(inst, test_mode) << TMC51XX_GCONF_TEST_MODE_SHIFT) |		\
+		(DT_INST_PROP(inst, invert_direction) << TMC51XX_GCONF_SHAFT_SHIFT)),		\
+		.spi = SPI_DT_SPEC_INST_GET(inst, (SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB |	\
+					SPI_MODE_CPOL | SPI_MODE_CPHA |	SPI_WORD_SET(8)), 0),	\
+		.clock_frequency = DT_INST_PROP(inst, clock_frequency),				\
+		.default_micro_step_res = DT_INST_PROP(inst, micro_step_res),			\
+		.sg_threshold = DT_INST_PROP(inst, stallguard2_threshold),			\
+		.sg_threshold_velocity = DT_INST_PROP(inst, stallguard_threshold_velocity),	\
+		.sg_velocity_check_interval_ms = DT_INST_PROP(inst,				\
+						stallguard_velocity_check_interval_ms),		\
+		.is_sg_enabled = DT_INST_PROP(inst, activate_stallguard2),			\
+		IF_ENABLED(CONFIG_STEPPER_ADI_TMC51XX_RAMP_GEN,					\
+		(.default_ramp_config = TMC_RAMP_DT_SPEC_GET_TMC51XX(inst)))};			\
+	DEVICE_DT_INST_DEFINE(inst, tmc51xx_init, NULL, &tmc51xx_data_##inst,			\
+			      &tmc51xx_config_##inst, POST_KERNEL, CONFIG_STEPPER_INIT_PRIORITY,\
+			      &tmc51xx_api);
+
+DT_INST_FOREACH_STATUS_OKAY(TMC51XX_DEFINE)
diff --git a/drivers/stepper/allegro/CMakeLists.txt b/drivers/stepper/allegro/CMakeLists.txt
new file mode 100644
index 00000000000..63576a655c6
--- /dev/null
+++ b/drivers/stepper/allegro/CMakeLists.txt
@@ -0,0 +1,7 @@
+# SPDX-FileCopyrightText: Copyright (c) 2025 Carl Zeiss Meditec AG
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+zephyr_library_property(ALLOW_EMPTY TRUE)
+
+zephyr_library_sources_ifdef(CONFIG_A4979_STEPPER a4979.c)
diff --git a/drivers/stepper/allegro/Kconfig b/drivers/stepper/allegro/Kconfig
new file mode 100644
index 00000000000..39d24bdf1f9
--- /dev/null
+++ b/drivers/stepper/allegro/Kconfig
@@ -0,0 +1,19 @@
+# SPDX-FileCopyrightText: Copyright (c) 2025 Carl Zeiss Meditec AG
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig STEPPER_ALLEGRO
+	bool "Allegro Stepper Controller"
+	depends on STEPPER
+	default y
+	help
+	  Enable allegro stepper controller
+
+if STEPPER_ALLEGRO
+
+comment "Allegro Stepper Drivers"
+
+# zephyr-keep-sorted-start
+rsource "Kconfig.a4979"
+# zephyr-keep-sorted-stop
+
+endif # STEPPER_ALLEGRO
diff --git a/drivers/stepper/allegro/Kconfig.a4979 b/drivers/stepper/allegro/Kconfig.a4979
new file mode 100644
index 00000000000..1abca3f87ef
--- /dev/null
+++ b/drivers/stepper/allegro/Kconfig.a4979
@@ -0,0 +1,10 @@
+# SPDX-FileCopyrightText: Copyright (c) 2025 Carl Zeiss Meditec AG
+# SPDX-License-Identifier: Apache-2.0
+
+config A4979_STEPPER
+	bool "Activate allegro A4979 stepper driver"
+	default y
+	depends on DT_HAS_ALLEGRO_A4979_ENABLED
+	select STEP_DIR_STEPPER
+	help
+	  Microstepping motor driver for stepper motors.
diff --git a/drivers/stepper/allegro/a4979.c b/drivers/stepper/allegro/a4979.c
new file mode 100644
index 00000000000..f08dbd61d37
--- /dev/null
+++ b/drivers/stepper/allegro/a4979.c
@@ -0,0 +1,302 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2025 Carl Zeiss Meditec AG
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT allegro_a4979
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/stepper.h>
+#include <zephyr/drivers/gpio.h>
+#include "../step_dir/step_dir_stepper_common.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(a4979, CONFIG_STEPPER_LOG_LEVEL);
+
+struct a4979_config {
+	const struct step_dir_stepper_common_config common;
+	const struct gpio_dt_spec en_pin;
+	const struct gpio_dt_spec reset_pin;
+	const struct gpio_dt_spec m0_pin;
+	const struct gpio_dt_spec m1_pin;
+};
+
+struct a4979_data {
+	const struct step_dir_stepper_common_data common;
+	enum stepper_micro_step_resolution micro_step_res;
+	bool enabled;
+};
+
+STEP_DIR_STEPPER_STRUCT_CHECK(struct a4979_config, struct a4979_data);
+
+static int a4979_set_microstep_pin(const struct device *dev, const struct gpio_dt_spec *pin,
+				   int value)
+{
+	int ret;
+
+	/* Reset microstep pin as it may have been disconnected. */
+	ret = gpio_pin_configure_dt(pin, GPIO_OUTPUT_INACTIVE);
+	if (ret != 0) {
+		LOG_ERR("Failed to configure microstep pin (error: %d)", ret);
+		return ret;
+	}
+
+	ret = gpio_pin_set_dt(pin, value);
+	if (ret != 0) {
+		LOG_ERR("Failed to set microstep pin (error: %d)", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int a4979_stepper_enable(const struct device *dev)
+{
+	int ret;
+	const struct a4979_config *config = dev->config;
+	struct a4979_data *data = dev->data;
+	bool has_enable_pin = config->en_pin.port != NULL;
+
+	/* Check availability of enable pin, as it might be hardwired. */
+	if (!has_enable_pin) {
+		LOG_ERR("%s: Enable pin undefined.", dev->name);
+		return -ENOTSUP;
+	}
+
+	ret = gpio_pin_set_dt(&config->en_pin, 1);
+	if (ret != 0) {
+		LOG_ERR("%s: Failed to set en_pin (error: %d)", dev->name, ret);
+		return ret;
+	}
+
+	data->enabled = true;
+
+	return 0;
+}
+
+static int a4979_stepper_disable(const struct device *dev)
+{
+	int ret;
+	const struct a4979_config *config = dev->config;
+	struct a4979_data *data = dev->data;
+	bool has_enable_pin = config->en_pin.port != NULL;
+
+	/* Check availability of enable pin, as it might be hardwired. */
+	if (!has_enable_pin) {
+		LOG_ERR("%s: Enable pin undefined.", dev->name);
+		return -ENOTSUP;
+	}
+
+	ret = gpio_pin_set_dt(&config->en_pin, 0);
+	if (ret != 0) {
+		LOG_ERR("%s: Failed to set en_pin (error: %d)", dev->name, ret);
+		return ret;
+	}
+
+	config->common.timing_source->stop(dev);
+	data->enabled = false;
+
+	return 0;
+}
+
+static int a4979_stepper_set_micro_step_res(const struct device *dev,
+					    const enum stepper_micro_step_resolution micro_step_res)
+{
+	const struct a4979_config *config = dev->config;
+	struct a4979_data *data = dev->data;
+	int ret;
+
+	uint8_t m0_value = 0;
+	uint8_t m1_value = 0;
+
+	switch (micro_step_res) {
+	case STEPPER_MICRO_STEP_1:
+		m0_value = 0;
+		m1_value = 0;
+		break;
+	case STEPPER_MICRO_STEP_2:
+		m0_value = 1;
+		m1_value = 0;
+		break;
+	case STEPPER_MICRO_STEP_4:
+		m0_value = 0;
+		m1_value = 1;
+	case STEPPER_MICRO_STEP_16:
+		m0_value = 1;
+		m1_value = 1;
+		break;
+	default:
+		LOG_ERR("Unsupported micro step resolution %d", micro_step_res);
+		return -ENOTSUP;
+	}
+
+	ret = a4979_set_microstep_pin(dev, &config->m0_pin, m0_value);
+	if (ret != 0) {
+		return ret;
+	}
+	ret = a4979_set_microstep_pin(dev, &config->m1_pin, m1_value);
+	if (ret != 0) {
+		return ret;
+	}
+
+	data->micro_step_res = micro_step_res;
+	return 0;
+}
+
+static int a4979_stepper_get_micro_step_res(const struct device *dev,
+					    enum stepper_micro_step_resolution *micro_step_res)
+{
+	struct a4979_data *data = dev->data;
+
+	*micro_step_res = data->micro_step_res;
+	return 0;
+}
+
+static int a4979_move_to(const struct device *dev, int32_t target)
+{
+	struct a4979_data *data = dev->data;
+
+	if (!data->enabled) {
+		LOG_ERR("Failed to move to target position, device is not enabled");
+		return -ECANCELED;
+	}
+
+	return step_dir_stepper_common_move_to(dev, target);
+}
+
+static int a4979_stepper_move_by(const struct device *dev, const int32_t micro_steps)
+{
+	struct a4979_data *data = dev->data;
+
+	if (!data->enabled) {
+		LOG_ERR("Failed to move by delta, device is not enabled");
+		return -ECANCELED;
+	}
+
+	return step_dir_stepper_common_move_by(dev, micro_steps);
+}
+
+static int a4979_run(const struct device *dev, enum stepper_direction direction)
+{
+	struct a4979_data *data = dev->data;
+
+	if (!data->enabled) {
+		LOG_ERR("Failed to run stepper, device is not enabled");
+		return -ECANCELED;
+	}
+
+	return step_dir_stepper_common_run(dev, direction);
+}
+
+static int a4979_init(const struct device *dev)
+{
+	const struct a4979_config *config = dev->config;
+	struct a4979_data *data = dev->data;
+	int ret;
+
+	bool has_enable_pin = config->en_pin.port != NULL;
+	bool has_reset_pin = config->reset_pin.port != NULL;
+
+	LOG_DBG("Initializing %s gpios", dev->name);
+
+	/* Configure reset pin if it is available */
+	if (has_reset_pin) {
+		if (!gpio_is_ready_dt(&config->reset_pin)) {
+			LOG_ERR("Enable Pin is not ready");
+			return -ENODEV;
+		}
+
+		ret = gpio_pin_configure_dt(&config->reset_pin, GPIO_OUTPUT_ACTIVE);
+		if (ret != 0) {
+			LOG_ERR("%s: Failed to configure reset_pin (error: %d)", dev->name, ret);
+			return ret;
+		}
+	}
+
+	/* Configure enable pin if it is available */
+	if (has_enable_pin) {
+		if (!gpio_is_ready_dt(&config->en_pin)) {
+			LOG_ERR("Enable Pin is not ready");
+			return -ENODEV;
+		}
+
+		ret = gpio_pin_configure_dt(&config->en_pin, GPIO_OUTPUT_INACTIVE);
+		if (ret != 0) {
+			LOG_ERR("%s: Failed to configure en_pin (error: %d)", dev->name, ret);
+			return ret;
+		}
+	}
+
+	/* Configure microstep pin 0 */
+	if (!gpio_is_ready_dt(&config->m0_pin)) {
+		LOG_ERR("m0 Pin is not ready");
+		return -ENODEV;
+	}
+	ret = gpio_pin_configure_dt(&config->m0_pin, GPIO_OUTPUT_INACTIVE);
+	if (ret != 0) {
+		LOG_ERR("%s: Failed to configure m0_pin (error: %d)", dev->name, ret);
+		return ret;
+	}
+
+	/* Configure microstep pin 1 */
+	if (!gpio_is_ready_dt(&config->m1_pin)) {
+		LOG_ERR("m1 Pin is not ready");
+		return -ENODEV;
+	}
+	ret = gpio_pin_configure_dt(&config->m1_pin, GPIO_OUTPUT_INACTIVE);
+	if (ret != 0) {
+		LOG_ERR("%s: Failed to configure m1_pin (error: %d)", dev->name, ret);
+		return ret;
+	}
+
+	ret = a4979_stepper_set_micro_step_res(dev, data->micro_step_res);
+	if (ret != 0) {
+		LOG_ERR("Failed to set micro step resolution: %d", ret);
+		return ret;
+	}
+
+	ret = step_dir_stepper_common_init(dev);
+	if (ret != 0) {
+		LOG_ERR("Failed to initialize common stepper data: %d", ret);
+		return ret;
+	}
+	gpio_pin_set_dt(&config->common.step_pin, 0);
+
+	return 0;
+}
+
+static DEVICE_API(stepper, a4979_stepper_api) = {
+	.enable = a4979_stepper_enable,
+	.disable = a4979_stepper_disable,
+	.move_by = a4979_stepper_move_by,
+	.move_to = a4979_move_to,
+	.is_moving = step_dir_stepper_common_is_moving,
+	.set_reference_position = step_dir_stepper_common_set_reference_position,
+	.get_actual_position = step_dir_stepper_common_get_actual_position,
+	.set_microstep_interval = step_dir_stepper_common_set_microstep_interval,
+	.run = a4979_run,
+	.stop = step_dir_stepper_common_stop,
+	.set_micro_step_res = a4979_stepper_set_micro_step_res,
+	.get_micro_step_res = a4979_stepper_get_micro_step_res,
+	.set_event_callback = step_dir_stepper_common_set_event_callback,
+};
+
+#define A4979_DEVICE(inst)                                                                         \
+                                                                                                   \
+	static const struct a4979_config a4979_config_##inst = {                                   \
+		.common = STEP_DIR_STEPPER_DT_INST_COMMON_CONFIG_INIT(inst),                       \
+		.en_pin = GPIO_DT_SPEC_INST_GET_OR(inst, en_gpios, {0}),                           \
+		.reset_pin = GPIO_DT_SPEC_INST_GET_OR(inst, reset_gpios, {0}),                     \
+		.m0_pin = GPIO_DT_SPEC_INST_GET(inst, m0_gpios),                                   \
+		.m1_pin = GPIO_DT_SPEC_INST_GET(inst, m1_gpios),                                   \
+	};                                                                                         \
+                                                                                                   \
+	static struct a4979_data a4979_data_##inst = {                                             \
+		.common = STEP_DIR_STEPPER_DT_INST_COMMON_DATA_INIT(inst),                         \
+		.micro_step_res = DT_INST_PROP(inst, micro_step_res),                              \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(inst, a4979_init, NULL, &a4979_data_##inst, &a4979_config_##inst,    \
+			      POST_KERNEL, CONFIG_STEPPER_INIT_PRIORITY, &a4979_stepper_api);
+
+DT_INST_FOREACH_STATUS_OKAY(A4979_DEVICE)
diff --git a/drivers/stepper/fake_stepper_controller.c b/drivers/stepper/fake_stepper_controller.c
index 519c8dd2c67..3abce9726c5 100644
--- a/drivers/stepper/fake_stepper_controller.c
+++ b/drivers/stepper/fake_stepper_controller.c
@@ -19,13 +19,15 @@ struct fake_stepper_data {
 	int32_t actual_position;
 };
 
-DEFINE_FAKE_VALUE_FUNC(int, fake_stepper_enable, const struct device *, bool);
+DEFINE_FAKE_VALUE_FUNC(int, fake_stepper_enable, const struct device *);
+
+DEFINE_FAKE_VALUE_FUNC(int, fake_stepper_disable, const struct device *);
 
 DEFINE_FAKE_VALUE_FUNC(int, fake_stepper_is_moving, const struct device *, bool *);
 
 DEFINE_FAKE_VALUE_FUNC(int, fake_stepper_move_by, const struct device *, int32_t);
 
-DEFINE_FAKE_VALUE_FUNC(int, fake_stepper_set_max_velocity, const struct device *, uint32_t);
+DEFINE_FAKE_VALUE_FUNC(int, fake_stepper_set_microstep_interval, const struct device *, uint64_t);
 
 DEFINE_FAKE_VALUE_FUNC(int, fake_stepper_set_micro_step_res, const struct device *,
 		       enum stepper_micro_step_resolution);
@@ -39,8 +41,9 @@ DEFINE_FAKE_VALUE_FUNC(int, fake_stepper_get_actual_position, const struct devic
 
 DEFINE_FAKE_VALUE_FUNC(int, fake_stepper_move_to, const struct device *, int32_t);
 
-DEFINE_FAKE_VALUE_FUNC(int, fake_stepper_run, const struct device *, enum stepper_direction,
-		       uint32_t);
+DEFINE_FAKE_VALUE_FUNC(int, fake_stepper_run, const struct device *, enum stepper_direction);
+
+DEFINE_FAKE_VALUE_FUNC(int, fake_stepper_stop, const struct device *);
 
 DEFINE_FAKE_VALUE_FUNC(int, fake_stepper_set_event_callback, const struct device *,
 		       stepper_event_callback_t, void *);
@@ -90,15 +93,17 @@ static void fake_stepper_reset_rule_before(const struct ztest_unit_test *test, v
 	ARG_UNUSED(fixture);
 
 	RESET_FAKE(fake_stepper_enable);
+	RESET_FAKE(fake_stepper_disable);
 	RESET_FAKE(fake_stepper_move_by);
 	RESET_FAKE(fake_stepper_is_moving);
-	RESET_FAKE(fake_stepper_set_max_velocity);
+	RESET_FAKE(fake_stepper_set_microstep_interval);
 	RESET_FAKE(fake_stepper_set_micro_step_res);
 	RESET_FAKE(fake_stepper_get_micro_step_res);
 	RESET_FAKE(fake_stepper_set_reference_position);
 	RESET_FAKE(fake_stepper_get_actual_position);
 	RESET_FAKE(fake_stepper_move_to);
 	RESET_FAKE(fake_stepper_run);
+	RESET_FAKE(fake_stepper_stop);
 
 	/* Install custom fakes for the setter and getter functions */
 	fake_stepper_set_micro_step_res_fake.custom_fake = fake_stepper_set_micro_step_res_delegate;
@@ -126,15 +131,17 @@ static int fake_stepper_init(const struct device *dev)
 
 static DEVICE_API(stepper, fake_stepper_driver_api) = {
 	.enable = fake_stepper_enable,
+	.disable = fake_stepper_disable,
 	.move_by = fake_stepper_move_by,
 	.is_moving = fake_stepper_is_moving,
-	.set_max_velocity = fake_stepper_set_max_velocity,
+	.set_microstep_interval = fake_stepper_set_microstep_interval,
 	.set_micro_step_res = fake_stepper_set_micro_step_res,
 	.get_micro_step_res = fake_stepper_get_micro_step_res,
 	.set_reference_position = fake_stepper_set_reference_position,
 	.get_actual_position = fake_stepper_get_actual_position,
 	.move_to = fake_stepper_move_to,
 	.run = fake_stepper_run,
+	.stop = fake_stepper_stop,
 	.set_event_callback = fake_stepper_set_event_callback,
 };
 
diff --git a/drivers/stepper/gpio_stepper_controller.c b/drivers/stepper/gpio_stepper_controller.c
index aa5d706f67f..331d2413ec1 100644
--- a/drivers/stepper/gpio_stepper_controller.c
+++ b/drivers/stepper/gpio_stepper_controller.c
@@ -37,7 +37,7 @@ struct gpio_stepper_data {
 	uint8_t coil_charge;
 	struct k_work_delayable stepper_dwork;
 	int32_t actual_position;
-	uint32_t delay_in_us;
+	uint64_t delay_in_ns;
 	int32_t step_count;
 	bool is_enabled;
 	stepper_event_callback_t callback;
@@ -78,12 +78,12 @@ static void decrement_coil_charge(const struct device *dev)
 	}
 }
 
-static int power_down_coils(const struct device *dev)
+static int energize_coils(const struct device *dev, const bool energized)
 {
 	const struct gpio_stepper_config *config = dev->config;
 
 	for (int i = 0; i < NUM_CONTROL_PINS; i++) {
-		const int err = gpio_pin_set_dt(&config->control_pins[i], 0u);
+		const int err = gpio_pin_set_dt(&config->control_pins[i], energized);
 
 		if (err != 0) {
 			LOG_ERR("Failed to power down coil %d", i);
@@ -107,20 +107,14 @@ static void update_coil_charge(const struct device *dev)
 	}
 }
 
-static void update_remaining_steps(struct gpio_stepper_data *data)
+static void update_remaining_steps(const struct device *dev)
 {
+	struct gpio_stepper_data *data = dev->data;
+
 	if (data->step_count > 0) {
 		data->step_count--;
-		(void)k_work_reschedule(&data->stepper_dwork, K_USEC(data->delay_in_us));
 	} else if (data->step_count < 0) {
 		data->step_count++;
-		(void)k_work_reschedule(&data->stepper_dwork, K_USEC(data->delay_in_us));
-	} else {
-		if (!data->callback) {
-			LOG_WRN_ONCE("No callback set");
-			return;
-		}
-		data->callback(data->dev, STEPPER_EVENT_STEPS_COMPLETED, data->event_cb_user_data);
 	}
 }
 
@@ -141,11 +135,18 @@ static void position_mode_task(const struct device *dev)
 {
 	struct gpio_stepper_data *data = dev->data;
 
+	update_remaining_steps(dev);
+	(void)stepper_motor_set_coil_charge(dev);
+	update_coil_charge(dev);
 	if (data->step_count) {
-		(void)stepper_motor_set_coil_charge(dev);
-		update_coil_charge(dev);
+		(void)k_work_reschedule(&data->stepper_dwork, K_NSEC(data->delay_in_ns));
+	} else {
+		if (data->callback) {
+			data->callback(data->dev, STEPPER_EVENT_STEPS_COMPLETED,
+				       data->event_cb_user_data);
+		}
+		(void)k_work_cancel_delayable(&data->stepper_dwork);
 	}
-	update_remaining_steps(dev->data);
 }
 
 static void velocity_mode_task(const struct device *dev)
@@ -154,7 +155,7 @@ static void velocity_mode_task(const struct device *dev)
 
 	(void)stepper_motor_set_coil_charge(dev);
 	update_coil_charge(dev);
-	(void)k_work_reschedule(&data->stepper_dwork, K_USEC(data->delay_in_us));
+	(void)k_work_reschedule(&data->stepper_dwork, K_NSEC(data->delay_in_ns));
 }
 
 static void stepper_work_step_handler(struct k_work *work)
@@ -187,8 +188,8 @@ static int gpio_stepper_move_by(const struct device *dev, int32_t micro_steps)
 		return -ECANCELED;
 	}
 
-	if (data->delay_in_us == 0) {
-		LOG_ERR("Velocity not set or invalid velocity set");
+	if (data->delay_in_ns == 0) {
+		LOG_ERR("Step interval not set or invalid step interval set");
 		return -EINVAL;
 	}
 	K_SPINLOCK(&data->lock) {
@@ -223,23 +224,12 @@ static int gpio_stepper_get_actual_position(const struct device *dev, int32_t *p
 static int gpio_stepper_move_to(const struct device *dev, int32_t micro_steps)
 {
 	struct gpio_stepper_data *data = dev->data;
+	int32_t steps_to_move;
 
-	if (!data->is_enabled) {
-		LOG_ERR("Stepper motor is not enabled");
-		return -ECANCELED;
-	}
-
-	if (data->delay_in_us == 0) {
-		LOG_ERR("Velocity not set or invalid velocity set");
-		return -EINVAL;
-	}
 	K_SPINLOCK(&data->lock) {
-		data->run_mode = STEPPER_RUN_MODE_POSITION;
-		data->step_count = micro_steps - data->actual_position;
-		update_direction_from_step_count(dev);
-		(void)k_work_reschedule(&data->stepper_dwork, K_NO_WAIT);
+		steps_to_move = micro_steps - data->actual_position;
 	}
-	return 0;
+	return gpio_stepper_move_by(dev, steps_to_move);
 }
 
 static int gpio_stepper_is_moving(const struct device *dev, bool *is_moving)
@@ -251,29 +241,24 @@ static int gpio_stepper_is_moving(const struct device *dev, bool *is_moving)
 	return 0;
 }
 
-static int gpio_stepper_set_max_velocity(const struct device *dev, uint32_t velocity)
+static int gpio_stepper_set_microstep_interval(const struct device *dev,
+					       uint64_t microstep_interval_ns)
 {
 	struct gpio_stepper_data *data = dev->data;
 
-	if (velocity == 0) {
-		LOG_ERR("Velocity cannot be zero");
-		return -EINVAL;
-	}
-
-	if (velocity > USEC_PER_SEC) {
-		LOG_ERR("Velocity cannot be greater than %d micro_steps_per_second", USEC_PER_SEC);
+	if (microstep_interval_ns == 0) {
+		LOG_ERR("Step interval is invalid.");
 		return -EINVAL;
 	}
 
 	K_SPINLOCK(&data->lock) {
-		data->delay_in_us = USEC_PER_SEC / velocity;
+		data->delay_in_ns = microstep_interval_ns;
 	}
-	LOG_DBG("Setting Motor Speed to %d", velocity);
+	LOG_DBG("Setting Motor step interval to %llu", microstep_interval_ns);
 	return 0;
 }
 
-static int gpio_stepper_run(const struct device *dev, const enum stepper_direction direction,
-			    const uint32_t velocity)
+static int gpio_stepper_run(const struct device *dev, const enum stepper_direction direction)
 {
 	struct gpio_stepper_data *data = dev->data;
 
@@ -285,12 +270,7 @@ static int gpio_stepper_run(const struct device *dev, const enum stepper_directi
 	K_SPINLOCK(&data->lock) {
 		data->run_mode = STEPPER_RUN_MODE_VELOCITY;
 		data->direction = direction;
-		if (velocity != 0) {
-			data->delay_in_us = USEC_PER_SEC / velocity;
-			(void)k_work_reschedule(&data->stepper_dwork, K_NO_WAIT);
-		} else {
-			(void)k_work_cancel_delayable(&data->stepper_dwork);
-		}
+		(void)k_work_reschedule(&data->stepper_dwork, K_NO_WAIT);
 	}
 	return 0;
 }
@@ -299,6 +279,7 @@ static int gpio_stepper_set_micro_step_res(const struct device *dev,
 					   enum stepper_micro_step_resolution micro_step_res)
 {
 	struct gpio_stepper_data *data = dev->data;
+	int err = 0;
 
 	K_SPINLOCK(&data->lock) {
 		switch (micro_step_res) {
@@ -308,10 +289,10 @@ static int gpio_stepper_set_micro_step_res(const struct device *dev,
 			break;
 		default:
 			LOG_ERR("Unsupported micro step resolution %d", micro_step_res);
-			return -ENOTSUP;
+			err = -ENOTSUP;
 		}
 	}
-	return 0;
+	return err;
 }
 
 static int gpio_stepper_get_micro_step_res(const struct device *dev,
@@ -334,26 +315,54 @@ static int gpio_stepper_set_event_callback(const struct device *dev,
 	return 0;
 }
 
-static int gpio_stepper_enable(const struct device *dev, bool enable)
+static int gpio_stepper_enable(const struct device *dev)
+{
+	struct gpio_stepper_data *data = dev->data;
+	int err;
+
+	if (data->is_enabled) {
+		LOG_WRN("Stepper motor is already enabled");
+		return 0;
+	}
+
+	K_SPINLOCK(&data->lock) {
+		err = energize_coils(dev, true);
+		if (err == 0) {
+			data->is_enabled = true;
+		}
+	}
+	return err;
+}
+
+static int gpio_stepper_disable(const struct device *dev)
 {
 	struct gpio_stepper_data *data = dev->data;
+	int err;
 
 	K_SPINLOCK(&data->lock) {
+		(void)k_work_cancel_delayable(&data->stepper_dwork);
+		err = energize_coils(dev, false);
+		if (err == 0) {
+			data->is_enabled = false;
+		}
+	}
+	return err;
+}
 
-		data->is_enabled = enable;
+static int gpio_stepper_stop(const struct device *dev)
+{
+	struct gpio_stepper_data *data = dev->data;
+	int err;
 
-		if (enable) {
-			(void)k_work_reschedule(&data->stepper_dwork, K_NO_WAIT);
-		} else {
-			(void)k_work_cancel_delayable(&data->stepper_dwork);
-			const int err = power_down_coils(dev);
+	K_SPINLOCK(&data->lock) {
+		(void)k_work_cancel_delayable(&data->stepper_dwork);
+		err = energize_coils(dev, true);
 
-			if (err != 0) {
-				return -EIO;
-			}
+		if (data->callback && !err) {
+			data->callback(data->dev, STEPPER_EVENT_STOPPED, data->event_cb_user_data);
 		}
 	}
-	return 0;
+	return err;
 }
 
 static int gpio_stepper_init(const struct device *dev)
@@ -372,16 +381,18 @@ static int gpio_stepper_init(const struct device *dev)
 
 static DEVICE_API(stepper, gpio_stepper_api) = {
 	.enable = gpio_stepper_enable,
-	.move_by = gpio_stepper_move_by,
-	.is_moving = gpio_stepper_is_moving,
+	.disable = gpio_stepper_disable,
+	.set_micro_step_res = gpio_stepper_set_micro_step_res,
+	.get_micro_step_res = gpio_stepper_get_micro_step_res,
 	.set_reference_position = gpio_stepper_set_reference_position,
 	.get_actual_position = gpio_stepper_get_actual_position,
+	.set_event_callback = gpio_stepper_set_event_callback,
+	.set_microstep_interval = gpio_stepper_set_microstep_interval,
+	.move_by = gpio_stepper_move_by,
 	.move_to = gpio_stepper_move_to,
-	.set_max_velocity = gpio_stepper_set_max_velocity,
 	.run = gpio_stepper_run,
-	.set_micro_step_res = gpio_stepper_set_micro_step_res,
-	.get_micro_step_res = gpio_stepper_get_micro_step_res,
-	.set_event_callback = gpio_stepper_set_event_callback,
+	.stop = gpio_stepper_stop,
+	.is_moving = gpio_stepper_is_moving,
 };
 
 #define GPIO_STEPPER_DEFINE(inst)								\
diff --git a/drivers/stepper/step_dir/step_dir_stepper_common.c b/drivers/stepper/step_dir/step_dir_stepper_common.c
index 86be8d5d3c3..bd4eac4b996 100644
--- a/drivers/stepper/step_dir/step_dir_stepper_common.c
+++ b/drivers/stepper/step_dir/step_dir_stepper_common.c
@@ -16,10 +16,10 @@ static inline int step_dir_stepper_perform_step(const struct device *dev)
 
 	switch (data->direction) {
 	case STEPPER_DIRECTION_POSITIVE:
-		ret = gpio_pin_set_dt(&config->dir_pin, 1);
+		ret = gpio_pin_set_dt(&config->dir_pin, 1 ^ config->invert_direction);
 		break;
 	case STEPPER_DIRECTION_NEGATIVE:
-		ret = gpio_pin_set_dt(&config->dir_pin, 0);
+		ret = gpio_pin_set_dt(&config->dir_pin, 0 ^ config->invert_direction);
 		break;
 	default:
 		LOG_ERR("Unsupported direction: %d", data->direction);
@@ -53,7 +53,7 @@ static inline int step_dir_stepper_perform_step(const struct device *dev)
 	return 0;
 }
 
-static void stepper_trigger_callback(const struct device *dev, enum stepper_event event)
+void stepper_trigger_callback(const struct device *dev, enum stepper_event event)
 {
 	struct step_dir_stepper_common_data *data = dev->data;
 
@@ -228,15 +228,15 @@ int step_dir_stepper_common_move_by(const struct device *dev, const int32_t micr
 	struct step_dir_stepper_common_data *data = dev->data;
 	const struct step_dir_stepper_common_config *config = dev->config;
 
-	if (data->max_velocity == 0) {
-		LOG_ERR("Velocity not set or invalid velocity set");
+	if (data->microstep_interval_ns == 0) {
+		LOG_ERR("Step interval not set or invalid step interval set");
 		return -EINVAL;
 	}
 
 	K_SPINLOCK(&data->lock) {
 		data->run_mode = STEPPER_RUN_MODE_POSITION;
 		data->step_count = micro_steps;
-		config->timing_source->update(dev, data->max_velocity);
+		config->timing_source->update(dev, data->microstep_interval_ns);
 		update_direction_from_step_count(dev);
 		config->timing_source->start(dev);
 	}
@@ -244,24 +244,20 @@ int step_dir_stepper_common_move_by(const struct device *dev, const int32_t micr
 	return 0;
 }
 
-int step_dir_stepper_common_set_max_velocity(const struct device *dev, const uint32_t velocity)
+int step_dir_stepper_common_set_microstep_interval(const struct device *dev,
+					      const uint64_t microstep_interval_ns)
 {
 	struct step_dir_stepper_common_data *data = dev->data;
 	const struct step_dir_stepper_common_config *config = dev->config;
 
-	if (velocity == 0) {
-		LOG_ERR("Velocity cannot be zero");
-		return -EINVAL;
-	}
-
-	if (velocity > USEC_PER_SEC) {
-		LOG_ERR("Velocity cannot be greater than %d micro steps per second", USEC_PER_SEC);
+	if (microstep_interval_ns == 0) {
+		LOG_ERR("Step interval cannot be zero");
 		return -EINVAL;
 	}
 
 	K_SPINLOCK(&data->lock) {
-		data->max_velocity = velocity;
-		config->timing_source->update(dev, velocity);
+		data->microstep_interval_ns = microstep_interval_ns;
+		config->timing_source->update(dev, microstep_interval_ns);
 	}
 
 	return 0;
@@ -292,22 +288,14 @@ int step_dir_stepper_common_get_actual_position(const struct device *dev, int32_
 int step_dir_stepper_common_move_to(const struct device *dev, const int32_t value)
 {
 	struct step_dir_stepper_common_data *data = dev->data;
-	const struct step_dir_stepper_common_config *config = dev->config;
-
-	if (data->max_velocity == 0) {
-		LOG_ERR("Velocity not set or invalid velocity set");
-		return -EINVAL;
-	}
+	int32_t steps_to_move;
 
+	/* Calculate the relative movement required */
 	K_SPINLOCK(&data->lock) {
-		data->run_mode = STEPPER_RUN_MODE_POSITION;
-		data->step_count = value - data->actual_position;
-		config->timing_source->update(dev, data->max_velocity);
-		update_direction_from_step_count(dev);
-		config->timing_source->start(dev);
+		steps_to_move = value - data->actual_position;
 	}
 
-	return 0;
+	return step_dir_stepper_common_move_by(dev, steps_to_move);
 }
 
 int step_dir_stepper_common_is_moving(const struct device *dev, bool *is_moving)
@@ -318,8 +306,7 @@ int step_dir_stepper_common_is_moving(const struct device *dev, bool *is_moving)
 	return 0;
 }
 
-int step_dir_stepper_common_run(const struct device *dev, const enum stepper_direction direction,
-				const uint32_t velocity)
+int step_dir_stepper_common_run(const struct device *dev, const enum stepper_direction direction)
 {
 	struct step_dir_stepper_common_data *data = dev->data;
 	const struct step_dir_stepper_common_config *config = dev->config;
@@ -327,15 +314,25 @@ int step_dir_stepper_common_run(const struct device *dev, const enum stepper_dir
 	K_SPINLOCK(&data->lock) {
 		data->run_mode = STEPPER_RUN_MODE_VELOCITY;
 		data->direction = direction;
-		data->max_velocity = velocity;
-		config->timing_source->update(dev, velocity);
-		if (velocity != 0) {
-			config->timing_source->start(dev);
-		} else {
-			config->timing_source->stop(dev);
-		}
+		config->timing_source->update(dev, data->microstep_interval_ns);
+		config->timing_source->start(dev);
+	}
+
+	return 0;
+}
+
+int step_dir_stepper_common_stop(const struct device *dev)
+{
+	const struct step_dir_stepper_common_config *config = dev->config;
+	int ret;
+
+	ret = config->timing_source->stop(dev);
+	if (ret != 0) {
+		LOG_ERR("Failed to stop timing source: %d", ret);
+		return ret;
 	}
 
+	stepper_trigger_callback(dev, STEPPER_EVENT_STOPPED);
 	return 0;
 }
 
diff --git a/drivers/stepper/step_dir/step_dir_stepper_common.h b/drivers/stepper/step_dir/step_dir_stepper_common.h
index a6fe92476c1..b345cf5d68a 100644
--- a/drivers/stepper/step_dir/step_dir_stepper_common.h
+++ b/drivers/stepper/step_dir/step_dir_stepper_common.h
@@ -32,6 +32,7 @@ struct step_dir_stepper_common_config {
 	bool dual_edge;
 	const struct stepper_timing_source_api *timing_source;
 	const struct device *counter;
+	bool invert_direction;
 };
 
 /**
@@ -47,6 +48,7 @@ struct step_dir_stepper_common_config {
 		.dir_pin = GPIO_DT_SPEC_GET(node_id, dir_gpios),                                   \
 		.dual_edge = DT_PROP_OR(node_id, dual_edge_step, false),                           \
 		.counter = DEVICE_DT_GET_OR_NULL(DT_PHANDLE(node_id, counter)),                    \
+		.invert_direction = DT_PROP(node_id, invert_direction),                            \
 		.timing_source = COND_CODE_1(DT_NODE_HAS_PROP(node_id, counter),                   \
 						(&step_counter_timing_source_api),                 \
 						(&step_work_timing_source_api)),                   \
@@ -70,7 +72,7 @@ struct step_dir_stepper_common_data {
 	enum stepper_direction direction;
 	enum stepper_run_mode run_mode;
 	int32_t actual_position;
-	uint32_t max_velocity;
+	uint64_t microstep_interval_ns;
 	int32_t step_count;
 	stepper_event_callback_t callback;
 	void *event_cb_user_data;
@@ -141,13 +143,14 @@ int step_dir_stepper_common_init(const struct device *dev);
 int step_dir_stepper_common_move_by(const struct device *dev, const int32_t micro_steps);
 
 /**
- * @brief Set the maximum velocity in micro_steps per second.
+ * @brief Set the step interval of the stepper motor.
  *
  * @param dev Pointer to the device structure.
- * @param velocity Maximum velocity in micro_steps per second.
+ * @param microstep_interval_ns The step interval in nanoseconds.
  * @return 0 on success, or a negative error code on failure.
  */
-int step_dir_stepper_common_set_max_velocity(const struct device *dev, const uint32_t velocity);
+int step_dir_stepper_common_set_microstep_interval(const struct device *dev,
+					      const uint64_t microstep_interval_ns);
 
 /**
  * @brief Set the reference position of the stepper motor.
@@ -186,15 +189,21 @@ int step_dir_stepper_common_move_to(const struct device *dev, const int32_t valu
 int step_dir_stepper_common_is_moving(const struct device *dev, bool *is_moving);
 
 /**
- * @brief Run the stepper with a given velocity in a given direction.
+ * @brief Run the stepper with a given direction and step interval.
  *
  * @param dev Pointer to the device structure.
  * @param direction The direction of movement (positive or negative).
- * @param velocity The velocity in micro_steps per second.
  * @return 0 on success, or a negative error code on failure.
  */
-int step_dir_stepper_common_run(const struct device *dev, const enum stepper_direction direction,
-				const uint32_t velocity);
+int step_dir_stepper_common_run(const struct device *dev, const enum stepper_direction direction);
+
+/**
+ * @brief Stop the stepper motor.
+ *
+ * @param dev Pointer to the device structure.
+ * @return 0 on success, or a negative error code on failure.
+ */
+int step_dir_stepper_common_stop(const struct device *dev);
 
 /**
  * @brief Set a callback function for stepper motor events.
@@ -216,6 +225,13 @@ int step_dir_stepper_common_set_event_callback(const struct device *dev,
  */
 void stepper_handle_timing_signal(const struct device *dev);
 
+/**
+ * @brief Trigger callback function for stepper motor events.
+ * @param dev Pointer to the device structure.
+ * @param event The stepper_event to rigger the callback for.
+ */
+void stepper_trigger_callback(const struct device *dev, enum stepper_event event);
+
 /** @} */
 
 #endif /* ZEPHYR_DRIVER_STEPPER_STEP_DIR_STEPPER_COMMON_H_ */
diff --git a/drivers/stepper/step_dir/step_dir_stepper_counter_timing.c b/drivers/stepper/step_dir/step_dir_stepper_counter_timing.c
index 6a99b434632..bad216961e5 100644
--- a/drivers/stepper/step_dir/step_dir_stepper_counter_timing.c
+++ b/drivers/stepper/step_dir/step_dir_stepper_counter_timing.c
@@ -17,18 +17,19 @@ static void step_counter_top_interrupt(const struct device *dev, void *user_data
 	stepper_handle_timing_signal(data->dev);
 }
 
-int step_counter_timing_source_update(const struct device *dev, const uint32_t velocity)
+int step_counter_timing_source_update(const struct device *dev,
+				      const uint64_t microstep_interval_ns)
 {
 	const struct step_dir_stepper_common_config *config = dev->config;
 	struct step_dir_stepper_common_data *data = dev->data;
 	int ret;
 
-	if (velocity == 0) {
+	if (microstep_interval_ns == 0) {
 		return -EINVAL;
 	}
 
-	data->counter_top_cfg.ticks =
-		DIV_ROUND_UP(counter_us_to_ticks(config->counter, USEC_PER_SEC), velocity);
+	data->counter_top_cfg.ticks = DIV_ROUND_UP(
+		counter_get_frequency(config->counter) * microstep_interval_ns, NSEC_PER_SEC);
 
 	/* Lock interrupts while modifying counter settings */
 	int key = irq_lock();
diff --git a/drivers/stepper/step_dir/step_dir_stepper_timing_source.h b/drivers/stepper/step_dir/step_dir_stepper_timing_source.h
index b2d369f968c..4c77993614a 100644
--- a/drivers/stepper/step_dir/step_dir_stepper_timing_source.h
+++ b/drivers/stepper/step_dir/step_dir_stepper_timing_source.h
@@ -20,10 +20,11 @@ typedef int (*stepper_timing_source_init)(const struct device *dev);
  * @brief Update the stepper timing source.
  *
  * @param dev Pointer to the device structure.
- * @param velocity Velocity in microsteps per second.
+ * @param microstep_interval_ns Step interval in nanoseconds.
  * @return 0 on success, or a negative error code on failure.
  */
-typedef int (*stepper_timing_source_update)(const struct device *dev, uint32_t velocity);
+typedef int (*stepper_timing_source_update)(const struct device *dev,
+					    uint64_t microstep_interval_ns);
 
 /**
  * @brief Start the stepper timing source.
diff --git a/drivers/stepper/step_dir/step_dir_stepper_work_timing.c b/drivers/stepper/step_dir/step_dir_stepper_work_timing.c
index 8d3bc861414..ac605f1f497 100644
--- a/drivers/stepper/step_dir/step_dir_stepper_work_timing.c
+++ b/drivers/stepper/step_dir/step_dir_stepper_work_timing.c
@@ -10,11 +10,11 @@ static k_timeout_t stepper_movement_delay(const struct device *dev)
 {
 	const struct step_dir_stepper_common_data *data = dev->data;
 
-	if (data->max_velocity == 0) {
+	if (data->microstep_interval_ns == 0) {
 		return K_FOREVER;
 	}
 
-	return K_USEC(USEC_PER_SEC / data->max_velocity);
+	return K_NSEC(data->microstep_interval_ns);
 }
 
 static void stepper_work_step_handler(struct k_work *work)
@@ -35,10 +35,10 @@ int step_work_timing_source_init(const struct device *dev)
 	return 0;
 }
 
-int step_work_timing_source_update(const struct device *dev, const uint32_t velocity)
+int step_work_timing_source_update(const struct device *dev, const uint64_t microstep_interval_ns)
 {
 	ARG_UNUSED(dev);
-	ARG_UNUSED(velocity);
+	ARG_UNUSED(microstep_interval_ns);
 	return 0;
 }
 
diff --git a/drivers/stepper/stepper_shell.c b/drivers/stepper/stepper_shell.c
index 97f05c99e04..1e96fb20c5f 100644
--- a/drivers/stepper/stepper_shell.c
+++ b/drivers/stepper/stepper_shell.c
@@ -61,15 +61,21 @@ static void print_callback(const struct device *dev, const enum stepper_event ev
 	case STEPPER_EVENT_RIGHT_END_STOP_DETECTED:
 		shell_info(sh, "%s: Right limit switch pressed.", dev->name);
 		break;
+	case STEPPER_EVENT_STOPPED:
+		shell_info(sh, "%s: Stepper stopped.", dev->name);
+		break;
+	case STEPPER_EVENT_FAULT_DETECTED:
+		shell_info(sh, "%s: Fault detected.", dev->name);
+		break;
 	default:
 		shell_info(sh, "%s: Unknown signal received.", dev->name);
 		break;
 	}
 }
 
-static bool stepper_device_check(const struct device *dev)
+static bool device_is_stepper(const struct device *dev)
 {
-	return DEVICE_API_IS(stepper, dev) && device_is_ready(dev);
+	return DEVICE_API_IS(stepper, dev);
 }
 
 static const struct stepper_direction_map stepper_direction_map[] = {
@@ -119,7 +125,7 @@ SHELL_DYNAMIC_CMD_CREATE(dsub_stepper_microstep, cmd_stepper_microstep);
 
 static void cmd_pos_stepper_motor_name(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_filter(idx, stepper_device_check);
+	const struct device *dev = shell_device_filter(idx, device_is_stepper);
 
 	entry->syntax = (dev != NULL) ? dev->name : NULL;
 	entry->handler = NULL;
@@ -131,7 +137,7 @@ SHELL_DYNAMIC_CMD_CREATE(dsub_pos_stepper_motor_name, cmd_pos_stepper_motor_name
 
 static void cmd_pos_stepper_motor_name_dir(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_filter(idx, stepper_device_check);
+	const struct device *dev = shell_device_filter(idx, device_is_stepper);
 
 	if (dev != NULL) {
 		entry->syntax = dev->name;
@@ -147,7 +153,7 @@ SHELL_DYNAMIC_CMD_CREATE(dsub_pos_stepper_motor_name_dir, cmd_pos_stepper_motor_
 
 static void cmd_pos_stepper_motor_name_microstep(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_filter(idx, stepper_device_check);
+	const struct device *dev = shell_device_filter(idx, device_is_stepper);
 
 	if (dev != NULL) {
 		entry->syntax = dev->name;
@@ -175,19 +181,32 @@ static int parse_device_arg(const struct shell *sh, char **argv, const struct de
 static int cmd_stepper_enable(const struct shell *sh, size_t argc, char **argv)
 {
 	const struct device *dev;
-	int err = 0;
-	bool enable = shell_strtobool(argv[ARG_IDX_PARAM], 10, &err);
+	int err;
 
+	err = parse_device_arg(sh, argv, &dev);
 	if (err < 0) {
 		return err;
 	}
 
+	err = stepper_enable(dev);
+	if (err) {
+		shell_error(sh, "Error: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_stepper_disable(const struct shell *sh, size_t argc, char **argv)
+{
+	const struct device *dev;
+	int err;
+
 	err = parse_device_arg(sh, argv, &dev);
 	if (err < 0) {
 		return err;
 	}
 
-	err = stepper_enable(dev, enable);
+	err = stepper_disable(dev);
 	if (err) {
 		shell_error(sh, "Error: %d", err);
 	}
@@ -195,6 +214,30 @@ static int cmd_stepper_enable(const struct shell *sh, size_t argc, char **argv)
 	return err;
 }
 
+static int cmd_stepper_stop(const struct shell *sh, size_t argc, char **argv)
+{
+	const struct device *dev;
+	int err = 0;
+
+	err = parse_device_arg(sh, argv, &dev);
+	if (err < 0) {
+		return err;
+	}
+
+	err = stepper_stop(dev);
+	if (err) {
+		shell_error(sh, "Error: %d", err);
+		return err;
+	}
+
+	err = stepper_set_event_callback(dev, print_callback, (void *)sh);
+	if (err != 0) {
+		shell_error(sh, "Failed to set callback: %d", err);
+	}
+
+	return err;
+}
+
 static int cmd_stepper_move_by(const struct shell *sh, size_t argc, char **argv)
 {
 	const struct device *dev;
@@ -224,11 +267,11 @@ static int cmd_stepper_move_by(const struct shell *sh, size_t argc, char **argv)
 	return err;
 }
 
-static int cmd_stepper_set_max_velocity(const struct shell *sh, size_t argc, char **argv)
+static int cmd_stepper_set_microstep_interval(const struct shell *sh, size_t argc, char **argv)
 {
 	const struct device *dev;
 	int err = 0;
-	uint32_t velocity = shell_strtoul(argv[ARG_IDX_PARAM], 10, &err);
+	uint64_t step_interval = shell_strtoull(argv[ARG_IDX_PARAM], 10, &err);
 
 	if (err < 0) {
 		return err;
@@ -239,7 +282,7 @@ static int cmd_stepper_set_max_velocity(const struct shell *sh, size_t argc, cha
 		return err;
 	}
 
-	err = stepper_set_max_velocity(dev, velocity);
+	err = stepper_set_microstep_interval(dev, step_interval);
 	if (err) {
 		shell_error(sh, "Error: %d", err);
 	}
@@ -389,12 +432,6 @@ static int cmd_stepper_run(const struct shell *sh, size_t argc, char **argv)
 		return err;
 	}
 
-	uint32_t velocity = shell_strtoul(argv[ARG_IDX_VALUE], 10, &err);
-
-	if (err < 0) {
-		return err;
-	}
-
 	err = parse_device_arg(sh, argv, &dev);
 	if (err < 0) {
 		return err;
@@ -405,7 +442,7 @@ static int cmd_stepper_run(const struct shell *sh, size_t argc, char **argv)
 		shell_error(sh, "Failed to set callback: %d", err);
 	}
 
-	err = stepper_run(dev, direction, velocity);
+	err = stepper_run(dev, direction);
 	if (err) {
 		shell_error(sh, "Error: %d", err);
 		return err;
@@ -456,12 +493,8 @@ static int cmd_stepper_info(const struct shell *sh, size_t argc, char **argv)
 
 SHELL_STATIC_SUBCMD_SET_CREATE(
 	stepper_cmds,
-	SHELL_CMD_ARG(enable, &dsub_pos_stepper_motor_name, "<device> <on/off>", cmd_stepper_enable,
-		      3, 0),
-	SHELL_CMD_ARG(move_by, &dsub_pos_stepper_motor_name, "<device> <micro_steps>",
-		      cmd_stepper_move_by, 3, 0),
-	SHELL_CMD_ARG(set_max_velocity, &dsub_pos_stepper_motor_name, "<device> <velocity>",
-		      cmd_stepper_set_max_velocity, 3, 0),
+	SHELL_CMD_ARG(enable, &dsub_pos_stepper_motor_name, "<device>", cmd_stepper_enable, 2, 0),
+	SHELL_CMD_ARG(disable, &dsub_pos_stepper_motor_name, "<device>", cmd_stepper_disable, 2, 0),
 	SHELL_CMD_ARG(set_micro_step_res, &dsub_pos_stepper_motor_name_microstep,
 		      "<device> <resolution>", cmd_stepper_set_micro_step_res, 3, 0),
 	SHELL_CMD_ARG(get_micro_step_res, &dsub_pos_stepper_motor_name, "<device>",
@@ -470,10 +503,15 @@ SHELL_STATIC_SUBCMD_SET_CREATE(
 		      cmd_stepper_set_reference_position, 3, 0),
 	SHELL_CMD_ARG(get_actual_position, &dsub_pos_stepper_motor_name, "<device>",
 		      cmd_stepper_get_actual_position, 2, 0),
-	SHELL_CMD_ARG(move_to, &dsub_pos_stepper_motor_name, "<device> <micro_steps>",
+	SHELL_CMD_ARG(set_microstep_interval, &dsub_pos_stepper_motor_name,
+		      "<device> <microstep_interval_ns>", cmd_stepper_set_microstep_interval, 3, 0),
+	SHELL_CMD_ARG(move_by, &dsub_pos_stepper_motor_name, "<device> <microsteps>",
+		      cmd_stepper_move_by, 3, 0),
+	SHELL_CMD_ARG(move_to, &dsub_pos_stepper_motor_name, "<device> <microsteps>",
 		      cmd_stepper_move_to, 3, 0),
-	SHELL_CMD_ARG(run, &dsub_pos_stepper_motor_name_dir, "<device> <direction> <velocity>",
-		      cmd_stepper_run, 4, 0),
+	SHELL_CMD_ARG(run, &dsub_pos_stepper_motor_name_dir, "<device> <direction>",
+		      cmd_stepper_run, 3, 0),
+	SHELL_CMD_ARG(stop, &dsub_pos_stepper_motor_name, "<device>", cmd_stepper_stop, 2, 0),
 	SHELL_CMD_ARG(info, &dsub_pos_stepper_motor_name, "<device>", cmd_stepper_info, 2, 0),
 	SHELL_SUBCMD_SET_END);
 
diff --git a/drivers/stepper/ti/CMakeLists.txt b/drivers/stepper/ti/CMakeLists.txt
index 8594fb8e1ed..4075008cfef 100644
--- a/drivers/stepper/ti/CMakeLists.txt
+++ b/drivers/stepper/ti/CMakeLists.txt
@@ -4,4 +4,4 @@
 zephyr_library()
 zephyr_library_property(ALLOW_EMPTY TRUE)
 
-zephyr_library_sources_ifdef(CONFIG_DRV8424 drv8424.c)
+zephyr_library_sources_ifdef(CONFIG_DRV84XX drv84xx.c)
diff --git a/drivers/stepper/ti/Kconfig b/drivers/stepper/ti/Kconfig
index f096aa56ebf..18804a89094 100644
--- a/drivers/stepper/ti/Kconfig
+++ b/drivers/stepper/ti/Kconfig
@@ -2,16 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config STEPPER_TI
-	bool "TI Stepper Controller"
+	bool
 	depends on STEPPER
-	default y
-	help
-	  Enable ti stepper controller
 
-if STEPPER_TI
-
-comment "TI Stepper Drivers"
-
-rsource "Kconfig.drv8424"
-
-endif # STEPPER_TI
+rsource "Kconfig.drv84xx"
diff --git a/drivers/stepper/ti/Kconfig.drv8424 b/drivers/stepper/ti/Kconfig.drv8424
deleted file mode 100644
index 38421ae645f..00000000000
--- a/drivers/stepper/ti/Kconfig.drv8424
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-FileCopyrightText: Copyright (c) 2024 Navimatix GmbH
-# SPDX-License-Identifier: Apache-2.0
-
-config DRV8424
-	bool "TI DRV8424 stepper motor driver"
-	default y
-	depends on DT_HAS_TI_DRV8424_ENABLED
-	select STEP_DIR_STEPPER
-	select STEPPER_STEP_DIR_GENERATE_ISR_SAFE_EVENTS
-	help
-	  Enable driver for TI DRV8424 stepper motor driver.
diff --git a/drivers/stepper/ti/Kconfig.drv84xx b/drivers/stepper/ti/Kconfig.drv84xx
new file mode 100644
index 00000000000..e5466890c66
--- /dev/null
+++ b/drivers/stepper/ti/Kconfig.drv84xx
@@ -0,0 +1,12 @@
+# SPDX-FileCopyrightText: Copyright (c) 2024 Navimatix GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+config DRV84XX
+	bool "TI DRV84XX stepper motor driver"
+	default y
+	depends on DT_HAS_TI_DRV84XX_ENABLED
+	select STEPPER_TI
+	select STEP_DIR_STEPPER
+	select STEPPER_STEP_DIR_GENERATE_ISR_SAFE_EVENTS
+	help
+	  Enable driver for TI DRV84XX stepper motor driver.
diff --git a/drivers/stepper/ti/drv8424.c b/drivers/stepper/ti/drv8424.c
deleted file mode 100644
index 57aa64f9ff4..00000000000
--- a/drivers/stepper/ti/drv8424.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2024 Navimatix GmbH
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define DT_DRV_COMPAT ti_drv8424
-
-#include <zephyr/kernel.h>
-#include <zephyr/drivers/stepper.h>
-#include <zephyr/drivers/gpio.h>
-#include <zephyr/drivers/stepper/stepper_drv8424.h>
-#include "../step_dir/step_dir_stepper_common.h"
-
-#include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(drv8424, CONFIG_STEPPER_LOG_LEVEL);
-
-/**
- * @brief DRV8424 stepper driver configuration data.
- *
- * This structure contains all of the devicetree specifications for the pins
- * needed by a given DRV8424 stepper driver.
- */
-struct drv8424_config {
-	struct step_dir_stepper_common_config common;
-	struct gpio_dt_spec sleep_pin;
-	struct gpio_dt_spec en_pin;
-	struct gpio_dt_spec m0_pin;
-	struct gpio_dt_spec m1_pin;
-};
-
-/* Struct for storing the states of output pins. */
-struct drv8424_pin_states {
-	uint8_t sleep: 1;
-	uint8_t en: 1;
-	uint8_t m0: 2;
-	uint8_t m1: 2;
-};
-
-/**
- * @brief DRV8424 stepper driver data.
- *
- * This structure contains mutable data used by a DRV8424 stepper driver.
- */
-struct drv8424_data {
-	const struct step_dir_stepper_common_data common;
-	bool enabled;
-	struct drv8424_pin_states pin_states;
-	enum stepper_micro_step_resolution ustep_res;
-};
-
-STEP_DIR_STEPPER_STRUCT_CHECK(struct drv8424_config, struct drv8424_data);
-
-static int drv8424_set_microstep_pin(const struct device *dev, const struct gpio_dt_spec *pin,
-				     int value)
-{
-	int ret;
-
-	/* Reset microstep pin as it may have been disconnected. */
-	ret = gpio_pin_configure_dt(pin, GPIO_OUTPUT_INACTIVE);
-	if (ret != 0) {
-		LOG_ERR("%s: Failed to reset micro-step pin (error: %d)", dev->name, ret);
-		return ret;
-	}
-
-	/* Set microstep pin */
-	switch (value) {
-	case 0:
-		ret = gpio_pin_set_dt(pin, 0);
-		break;
-	case 1:
-		ret = gpio_pin_set_dt(pin, 1);
-		break;
-	case 2:
-		/* Hi-Z is set by configuring pin as disconnected, not
-		 * all gpio controllers support this.
-		 */
-		ret = gpio_pin_configure_dt(pin, GPIO_DISCONNECTED);
-		break;
-	default:
-		break;
-	}
-
-	if (ret != 0) {
-		LOG_ERR("%s: Failed to set micro-step pin (error: %d)", dev->name, ret);
-		return ret;
-	}
-	return 0;
-}
-
-/*
- * If microstep setter fails, attempt to recover into previous state.
- */
-int drv8424_microstep_recovery(const struct device *dev)
-{
-	const struct drv8424_config *config = dev->config;
-	struct drv8424_data *data = dev->data;
-	int ret;
-
-	uint8_t m0_value = data->pin_states.m0;
-	uint8_t m1_value = data->pin_states.m1;
-
-	ret = drv8424_set_microstep_pin(dev, &config->m0_pin, m0_value);
-	if (ret != 0) {
-		LOG_ERR("%s: Failed to restore microstep configuration (error: %d)", dev->name,
-			ret);
-		return ret;
-	}
-
-	ret = drv8424_set_microstep_pin(dev, &config->m1_pin, m1_value);
-	if (ret != 0) {
-		LOG_ERR("%s: Failed to restore microstep configuration (error: %d)", dev->name,
-			ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-static int drv8424_enable(const struct device *dev, bool enable)
-{
-	int ret;
-	const struct drv8424_config *config = dev->config;
-	struct drv8424_data *data = dev->data;
-	bool has_enable_pin = config->en_pin.port != NULL;
-	bool has_sleep_pin = config->sleep_pin.port != NULL;
-
-	/* Check availability of sleep and enable pins, as these might be hardwired. */
-	if (!has_sleep_pin && !has_enable_pin) {
-		LOG_ERR("%s: Failed to enable/disable device, neither sleep pin nor enable pin are "
-			"available. The device is always on.",
-			dev->name);
-		return -ENOTSUP;
-	}
-
-	if (has_sleep_pin) {
-		ret = gpio_pin_set_dt(&config->sleep_pin, !enable);
-		if (ret != 0) {
-			LOG_ERR("%s: Failed to set sleep_pin (error: %d)", dev->name, ret);
-			return ret;
-		}
-		data->pin_states.sleep = enable ? 0U : 1U;
-	}
-
-	if (has_enable_pin) {
-		ret = gpio_pin_set_dt(&config->en_pin, enable);
-		if (ret != 0) {
-			LOG_ERR("%s: Failed to set en_pin (error: %d)", dev->name, ret);
-			return ret;
-		}
-		data->pin_states.en = enable ? 1U : 0U;
-	}
-
-	data->enabled = enable;
-	if (!enable) {
-		config->common.timing_source->stop(dev);
-		gpio_pin_set_dt(&config->common.step_pin, 0);
-	}
-
-	return 0;
-}
-
-static int drv8424_set_micro_step_res(const struct device *dev,
-				      enum stepper_micro_step_resolution micro_step_res)
-{
-	const struct drv8424_config *config = dev->config;
-	struct drv8424_data *data = dev->data;
-	int ret;
-
-	uint8_t m0_value = 0;
-	uint8_t m1_value = 0;
-
-	/* 0: low
-	 * 1: high
-	 * 2: Hi-Z
-	 * 3: 330kΩ
-	 */
-	switch (micro_step_res) {
-	case STEPPER_MICRO_STEP_1:
-		m0_value = 0;
-		m1_value = 0;
-		break;
-	case STEPPER_MICRO_STEP_2:
-		m0_value = 2;
-		m1_value = 0;
-		break;
-	case STEPPER_MICRO_STEP_4:
-		m0_value = 0;
-		m1_value = 1;
-		break;
-	case STEPPER_MICRO_STEP_8:
-		m0_value = 1;
-		m1_value = 1;
-		break;
-	case STEPPER_MICRO_STEP_16:
-		m0_value = 2;
-		m1_value = 1;
-		break;
-	case STEPPER_MICRO_STEP_32:
-		m0_value = 0;
-		m1_value = 2;
-		break;
-	case STEPPER_MICRO_STEP_64:
-		m0_value = 2;
-		m1_value = 3;
-		break;
-	case STEPPER_MICRO_STEP_128:
-		m0_value = 2;
-		m1_value = 2;
-		break;
-	case STEPPER_MICRO_STEP_256:
-		m0_value = 1;
-		m1_value = 2;
-		break;
-	default:
-		return -EINVAL;
-	};
-
-	ret = drv8424_set_microstep_pin(dev, &config->m0_pin, m0_value);
-	if (ret != 0) {
-		return ret;
-	}
-
-	ret = drv8424_set_microstep_pin(dev, &config->m1_pin, m1_value);
-	if (ret != 0) {
-		return ret;
-	}
-
-	data->ustep_res = micro_step_res;
-	data->pin_states.m0 = m0_value;
-	data->pin_states.m1 = m1_value;
-
-	return 0;
-}
-
-static int drv8424_get_micro_step_res(const struct device *dev,
-				      enum stepper_micro_step_resolution *micro_step_res)
-{
-	struct drv8424_data *data = dev->data;
-	*micro_step_res = data->ustep_res;
-	return 0;
-}
-
-static int drv8424_move_to(const struct device *dev, int32_t target)
-{
-	struct drv8424_data *data = dev->data;
-
-	if (!data->enabled) {
-		LOG_ERR("Failed to move to target position, device is not enabled");
-		return -ECANCELED;
-	}
-
-	return step_dir_stepper_common_move_to(dev, target);
-}
-
-static int drv8424_move_by(const struct device *dev, int32_t steps)
-{
-	struct drv8424_data *data = dev->data;
-
-	if (!data->enabled) {
-		LOG_ERR("Failed to move by delta, device is not enabled");
-		return -ECANCELED;
-	}
-
-	return step_dir_stepper_common_move_by(dev, steps);
-}
-
-static int drv8424_run(const struct device *dev, enum stepper_direction direction,
-		       uint32_t velocity)
-{
-	struct drv8424_data *data = dev->data;
-
-	if (!data->enabled) {
-		LOG_ERR("Failed to run stepper, device is not enabled");
-		return -ECANCELED;
-	}
-
-	return step_dir_stepper_common_run(dev, direction, velocity);
-}
-
-static int drv8424_init(const struct device *dev)
-{
-	const struct drv8424_config *const config = dev->config;
-	struct drv8424_data *const data = dev->data;
-	int ret;
-
-	/* Configure sleep pin if it is available */
-	if (config->sleep_pin.port != NULL) {
-		ret = gpio_pin_configure_dt(&config->sleep_pin, GPIO_OUTPUT_ACTIVE);
-		if (ret != 0) {
-			LOG_ERR("%s: Failed to configure sleep_pin (error: %d)", dev->name, ret);
-			return ret;
-		}
-		data->pin_states.sleep = 1U;
-	}
-
-	/* Configure enable pin if it is available */
-	if (config->en_pin.port != NULL) {
-		ret = gpio_pin_configure_dt(&config->en_pin, GPIO_OUTPUT_INACTIVE);
-		if (ret != 0) {
-			LOG_ERR("%s: Failed to configure en_pin (error: %d)", dev->name, ret);
-			return ret;
-		}
-		data->pin_states.en = 0U;
-	}
-
-	/* Configure microstep pin 0 */
-	ret = gpio_pin_configure_dt(&config->m0_pin, GPIO_OUTPUT_INACTIVE);
-	if (ret != 0) {
-		LOG_ERR("%s: Failed to configure m0_pin (error: %d)", dev->name, ret);
-		return ret;
-	}
-	data->pin_states.m0 = 0U;
-
-	/* Configure microstep pin 1 */
-	ret = gpio_pin_configure_dt(&config->m1_pin, GPIO_OUTPUT_INACTIVE);
-	if (ret != 0) {
-		LOG_ERR("%s: Failed to configure m1_pin (error: %d)", dev->name, ret);
-		return ret;
-	}
-	data->pin_states.m1 = 0U;
-
-	ret = drv8424_set_micro_step_res(dev, data->ustep_res);
-	if (ret != 0) {
-		return ret;
-	}
-
-	ret = step_dir_stepper_common_init(dev);
-	if (ret != 0) {
-		LOG_ERR("Failed to initialize common step direction stepper (error: %d)", ret);
-		return ret;
-	}
-
-	return 0;
-}
-
-static DEVICE_API(stepper, drv8424_stepper_api) = {
-	.enable = drv8424_enable,
-	.move_by = drv8424_move_by,
-	.move_to = drv8424_move_to,
-	.is_moving = step_dir_stepper_common_is_moving,
-	.set_reference_position = step_dir_stepper_common_set_reference_position,
-	.get_actual_position = step_dir_stepper_common_get_actual_position,
-	.set_max_velocity = step_dir_stepper_common_set_max_velocity,
-	.run = drv8424_run,
-	.set_micro_step_res = drv8424_set_micro_step_res,
-	.get_micro_step_res = drv8424_get_micro_step_res,
-	.set_event_callback = step_dir_stepper_common_set_event_callback,
-};
-
-#define DRV8424_DEVICE(inst)                                                                       \
-                                                                                                   \
-	static const struct drv8424_config drv8424_config_##inst = {                               \
-		.common = STEP_DIR_STEPPER_DT_INST_COMMON_CONFIG_INIT(inst),                       \
-		.sleep_pin = GPIO_DT_SPEC_INST_GET_OR(inst, sleep_gpios, {0}),                     \
-		.en_pin = GPIO_DT_SPEC_INST_GET_OR(inst, en_gpios, {0}),                           \
-		.m0_pin = GPIO_DT_SPEC_INST_GET(inst, m0_gpios),                                   \
-		.m1_pin = GPIO_DT_SPEC_INST_GET(inst, m1_gpios),                                   \
-	};                                                                                         \
-                                                                                                   \
-	static struct drv8424_data drv8424_data_##inst = {                                         \
-		.common = STEP_DIR_STEPPER_DT_INST_COMMON_DATA_INIT(inst),                         \
-		.ustep_res = DT_INST_PROP(inst, micro_step_res),                                   \
-	};                                                                                         \
-                                                                                                   \
-	DEVICE_DT_INST_DEFINE(inst, &drv8424_init, NULL, &drv8424_data_##inst,                     \
-			      &drv8424_config_##inst, POST_KERNEL, CONFIG_STEPPER_INIT_PRIORITY,   \
-			      &drv8424_stepper_api);
-
-DT_INST_FOREACH_STATUS_OKAY(DRV8424_DEVICE)
diff --git a/drivers/stepper/ti/drv84xx.c b/drivers/stepper/ti/drv84xx.c
new file mode 100644
index 00000000000..cc4a8651e8a
--- /dev/null
+++ b/drivers/stepper/ti/drv84xx.c
@@ -0,0 +1,515 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2024 Navimatix GmbH
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ti_drv84xx
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/stepper.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/stepper/stepper_drv84xx.h>
+#include "../step_dir/step_dir_stepper_common.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(drv84xx, CONFIG_STEPPER_LOG_LEVEL);
+
+/* Enable and wake up times of the drv84xx stepper controller family. Only after they have elapsed
+ * are controller output signals guaranteed to be valid.
+ */
+#define DRV84XX_ENABLE_TIME  K_USEC(5)
+#define DRV84XX_WAKE_UP_TIME K_USEC(1200)
+
+/**
+ * @brief DRV84XX stepper driver configuration data.
+ *
+ * This structure contains all of the devicetree specifications for the pins
+ * needed by a given DRV84XX stepper driver.
+ */
+struct drv84xx_config {
+	struct step_dir_stepper_common_config common;
+	struct gpio_dt_spec sleep_pin;
+	struct gpio_dt_spec en_pin;
+	struct gpio_dt_spec m0_pin;
+	struct gpio_dt_spec m1_pin;
+	struct gpio_dt_spec fault_pin;
+};
+
+/* Struct for storing the states of output pins. */
+struct drv84xx_pin_states {
+	uint8_t sleep: 1;
+	uint8_t en: 1;
+	uint8_t m0: 2;
+	uint8_t m1: 2;
+};
+
+/**
+ * @brief DRV84XX stepper driver data.
+ */
+struct drv84xx_data {
+	const struct step_dir_stepper_common_data common;
+	const struct device *dev;
+	bool enabled;
+	struct drv84xx_pin_states pin_states;
+	enum stepper_micro_step_resolution ustep_res;
+	struct gpio_callback fault_cb_data;
+};
+
+STEP_DIR_STEPPER_STRUCT_CHECK(struct drv84xx_config, struct drv84xx_data);
+
+static int drv84xx_set_microstep_pin(const struct device *dev, const struct gpio_dt_spec *pin,
+				     int value)
+{
+	int ret;
+
+	/* Reset microstep pin as it may have been disconnected. */
+	ret = gpio_pin_configure_dt(pin, GPIO_OUTPUT_INACTIVE);
+	if (ret != 0) {
+		LOG_ERR("%s: Failed to reset micro-step pin (error: %d)", dev->name, ret);
+		return ret;
+	}
+
+	/* Set microstep pin */
+	switch (value) {
+	case 0:
+		ret = gpio_pin_set_dt(pin, 0);
+		break;
+	case 1:
+		ret = gpio_pin_set_dt(pin, 1);
+		break;
+	case 2:
+		/* Hi-Z is set by configuring pin as disconnected, not
+		 * all gpio controllers support this.
+		 */
+		ret = gpio_pin_configure_dt(pin, GPIO_DISCONNECTED);
+		break;
+	default:
+		break;
+	}
+
+	if (ret != 0) {
+		LOG_ERR("%s: Failed to set micro-step pin (error: %d)", dev->name, ret);
+		return ret;
+	}
+	return 0;
+}
+
+/*
+ * If microstep setter fails, attempt to recover into previous state.
+ */
+int drv84xx_microstep_recovery(const struct device *dev)
+{
+	const struct drv84xx_config *config = dev->config;
+	struct drv84xx_data *data = dev->data;
+	int ret;
+
+	uint8_t m0_value = data->pin_states.m0;
+	uint8_t m1_value = data->pin_states.m1;
+
+	ret = drv84xx_set_microstep_pin(dev, &config->m0_pin, m0_value);
+	if (ret != 0) {
+		LOG_ERR("%s: Failed to restore microstep configuration (error: %d)", dev->name,
+			ret);
+		return ret;
+	}
+
+	ret = drv84xx_set_microstep_pin(dev, &config->m1_pin, m1_value);
+	if (ret != 0) {
+		LOG_ERR("%s: Failed to restore microstep configuration (error: %d)", dev->name,
+			ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int drv84xx_check_en_sleep_pin(const struct drv84xx_config *config)
+{
+	bool has_sleep_pin = config->sleep_pin.port != NULL;
+	bool has_enable_pin = config->en_pin.port != NULL;
+
+	if (!has_sleep_pin && !has_enable_pin) {
+		LOG_ERR("Failed to enable/disable device, neither sleep pin nor enable pin are "
+			"available. The device is always on.");
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static int drv84xx_set_en_pin_state(const struct device *dev, bool enable)
+{
+	const struct drv84xx_config *config = dev->config;
+	struct drv84xx_data *data = dev->data;
+	bool has_enable_pin = config->en_pin.port != NULL;
+	int ret;
+
+	if (has_enable_pin) {
+		ret = gpio_pin_set_dt(&config->en_pin, enable);
+		if (ret != 0) {
+			LOG_ERR("%s: Failed to set en_pin (error: %d)", dev->name, ret);
+			return ret;
+		}
+		data->pin_states.en = enable ? 1U : 0U;
+	}
+
+	return 0;
+}
+
+static int drv84xx_set_sleep_pin_state(const struct device *dev, bool enable)
+{
+	int ret;
+	const struct drv84xx_config *config = dev->config;
+	struct drv84xx_data *data = dev->data;
+	bool has_sleep_pin = config->sleep_pin.port != NULL;
+
+	if (has_sleep_pin) {
+		ret = gpio_pin_set_dt(&config->sleep_pin, !enable);
+		if (ret != 0) {
+			LOG_ERR("%s: Failed to set sleep_pin (error: %d)", dev->name, ret);
+			return ret;
+		}
+		data->pin_states.sleep = enable ? 0U : 1U;
+	}
+
+	return 0;
+}
+
+static int drv84xx_enable(const struct device *dev)
+{
+	const struct drv84xx_config *config = dev->config;
+	struct drv84xx_data *data = dev->data;
+	bool has_enable_pin = config->en_pin.port != NULL;
+	bool has_sleep_pin = config->sleep_pin.port != NULL;
+	bool has_fault_pin = config->fault_pin.port != NULL;
+	k_timeout_t enable_timeout;
+	int ret;
+
+	ret = drv84xx_check_en_sleep_pin(config);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = drv84xx_set_sleep_pin_state(dev, true);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = drv84xx_set_en_pin_state(dev, true);
+	if (ret != 0) {
+		return ret;
+	}
+
+	if (has_enable_pin) {
+		enable_timeout = DRV84XX_ENABLE_TIME;
+	}
+
+	if (has_sleep_pin) {
+		enable_timeout = DRV84XX_WAKE_UP_TIME;
+	}
+
+	if (has_fault_pin) {
+		/* Wait after enable/wakeup until the fault pin is guaranteed to be in the
+		 * proper state.
+		 */
+		k_sleep(enable_timeout);
+		ret = gpio_add_callback_dt(&config->fault_pin, &data->fault_cb_data);
+		if (ret != 0) {
+			LOG_ERR("%s: Failed to add fault callback (error: %d)", dev->name, ret);
+			return ret;
+		}
+	}
+
+	data->enabled = true;
+
+	return ret;
+}
+
+static int drv84xx_disable(const struct device *dev)
+{
+	const struct drv84xx_config *config = dev->config;
+	struct drv84xx_data *data = dev->data;
+	bool has_fault_pin = config->fault_pin.port != NULL;
+	int ret;
+
+	ret = drv84xx_check_en_sleep_pin(config);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = drv84xx_set_sleep_pin_state(dev, false);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = drv84xx_set_en_pin_state(dev, false);
+	if (ret != 0) {
+		return ret;
+	}
+
+	if (has_fault_pin) {
+		ret = gpio_remove_callback_dt(&config->fault_pin, &data->fault_cb_data);
+		if (ret != 0) {
+			LOG_ERR("%s: Failed to remove fault callback (error: %d)", dev->name, ret);
+			return ret;
+		}
+	}
+
+	config->common.timing_source->stop(dev);
+
+	data->enabled = false;
+
+	return ret;
+}
+
+static int drv84xx_set_micro_step_res(const struct device *dev,
+				      enum stepper_micro_step_resolution micro_step_res)
+{
+	const struct drv84xx_config *config = dev->config;
+	struct drv84xx_data *data = dev->data;
+	int ret;
+
+	uint8_t m0_value = 0;
+	uint8_t m1_value = 0;
+
+	if ((config->m0_pin.port == NULL) || (config->m1_pin.port == NULL)) {
+
+		LOG_ERR("%s: Failed to set microstep resolution: microstep pins are not defined "
+			"(error: %d)",
+			dev->name, -ENOTSUP);
+		return -ENOTSUP;
+	}
+
+	/* 0: low
+	 * 1: high
+	 * 2: Hi-Z
+	 * 3: 330kΩ
+	 */
+	switch (micro_step_res) {
+	case STEPPER_MICRO_STEP_1:
+		m0_value = 0;
+		m1_value = 0;
+		break;
+	case STEPPER_MICRO_STEP_2:
+		m0_value = 2;
+		m1_value = 0;
+		break;
+	case STEPPER_MICRO_STEP_4:
+		m0_value = 0;
+		m1_value = 1;
+		break;
+	case STEPPER_MICRO_STEP_8:
+		m0_value = 1;
+		m1_value = 1;
+		break;
+	case STEPPER_MICRO_STEP_16:
+		m0_value = 2;
+		m1_value = 1;
+		break;
+	case STEPPER_MICRO_STEP_32:
+		m0_value = 0;
+		m1_value = 2;
+		break;
+	case STEPPER_MICRO_STEP_64:
+		m0_value = 2;
+		m1_value = 3;
+		break;
+	case STEPPER_MICRO_STEP_128:
+		m0_value = 2;
+		m1_value = 2;
+		break;
+	case STEPPER_MICRO_STEP_256:
+		m0_value = 1;
+		m1_value = 2;
+		break;
+	default:
+		return -ENOTSUP;
+	};
+
+	ret = drv84xx_set_microstep_pin(dev, &config->m0_pin, m0_value);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = drv84xx_set_microstep_pin(dev, &config->m1_pin, m1_value);
+	if (ret != 0) {
+		return ret;
+	}
+
+	data->ustep_res = micro_step_res;
+	data->pin_states.m0 = m0_value;
+	data->pin_states.m1 = m1_value;
+
+	return 0;
+}
+
+static int drv84xx_get_micro_step_res(const struct device *dev,
+				      enum stepper_micro_step_resolution *micro_step_res)
+{
+	struct drv84xx_data *data = dev->data;
+	*micro_step_res = data->ustep_res;
+	return 0;
+}
+
+static int drv84xx_move_to(const struct device *dev, int32_t target)
+{
+	struct drv84xx_data *data = dev->data;
+
+	if (!data->enabled) {
+		LOG_ERR("Failed to move to target position, device is not enabled");
+		return -ECANCELED;
+	}
+
+	return step_dir_stepper_common_move_to(dev, target);
+}
+
+static int drv84xx_move_by(const struct device *dev, int32_t steps)
+{
+	struct drv84xx_data *data = dev->data;
+
+	if (!data->enabled) {
+		LOG_ERR("Failed to move by delta, device is not enabled");
+		return -ECANCELED;
+	}
+
+	return step_dir_stepper_common_move_by(dev, steps);
+}
+
+static int drv84xx_run(const struct device *dev, enum stepper_direction direction)
+{
+	struct drv84xx_data *data = dev->data;
+
+	if (!data->enabled) {
+		LOG_ERR("Failed to run stepper, device is not enabled");
+		return -ECANCELED;
+	}
+
+	return step_dir_stepper_common_run(dev, direction);
+}
+
+void fault_event(const struct device *dev, struct gpio_callback *cb, uint32_t pins)
+{
+	struct drv84xx_data *data = CONTAINER_OF(cb, struct drv84xx_data, fault_cb_data);
+
+	stepper_trigger_callback(data->dev, STEPPER_EVENT_FAULT_DETECTED);
+}
+
+static int drv84xx_init(const struct device *dev)
+{
+	const struct drv84xx_config *const config = dev->config;
+	struct drv84xx_data *const data = dev->data;
+	int ret;
+
+	/* Configure sleep pin if it is available */
+	if (config->sleep_pin.port != NULL) {
+		ret = gpio_pin_configure_dt(&config->sleep_pin, GPIO_OUTPUT_ACTIVE);
+		if (ret != 0) {
+			LOG_ERR("%s: Failed to configure sleep_pin (error: %d)", dev->name, ret);
+			return ret;
+		}
+		data->pin_states.sleep = 1U;
+	}
+
+	/* Configure enable pin if it is available */
+	if (config->en_pin.port != NULL) {
+		ret = gpio_pin_configure_dt(&config->en_pin, GPIO_OUTPUT_INACTIVE);
+		if (ret != 0) {
+			LOG_ERR("%s: Failed to configure en_pin (error: %d)", dev->name, ret);
+			return ret;
+		}
+		data->pin_states.en = 0U;
+	}
+
+	/* Configure microstep pin 0 if it is available */
+	if (config->m0_pin.port != NULL) {
+		ret = gpio_pin_configure_dt(&config->m0_pin, GPIO_OUTPUT_INACTIVE);
+		if (ret != 0) {
+			LOG_ERR("%s: Failed to configure m0_pin (error: %d)", dev->name, ret);
+			return ret;
+		}
+		data->pin_states.m0 = 0U;
+	}
+
+	/* Configure microstep pin 1 if it is available */
+	if (config->m1_pin.port != NULL) {
+		ret = gpio_pin_configure_dt(&config->m1_pin, GPIO_OUTPUT_INACTIVE);
+		if (ret != 0) {
+			LOG_ERR("%s: Failed to configure m1_pin (error: %d)", dev->name, ret);
+			return ret;
+		}
+		data->pin_states.m1 = 0U;
+	}
+
+	if ((config->m0_pin.port != NULL) && (config->m1_pin.port != NULL)) {
+		ret = drv84xx_set_micro_step_res(dev, data->ustep_res);
+		if (ret != 0) {
+			return ret;
+		}
+	}
+
+	ret = step_dir_stepper_common_init(dev);
+	if (ret != 0) {
+		LOG_ERR("Failed to initialize common step direction stepper (error: %d)", ret);
+		return ret;
+	}
+
+	/* Configure fault pin if it is available */
+	if (config->fault_pin.port != NULL) {
+		ret = gpio_pin_configure_dt(&config->fault_pin, GPIO_INPUT);
+		if (ret != 0) {
+			LOG_ERR("%s: Failed to configure fault_pin (error: %d)", dev->name, ret);
+			return ret;
+		}
+
+		ret = gpio_pin_interrupt_configure_dt(&config->fault_pin,
+						      GPIO_INT_EDGE_TO_INACTIVE);
+		if (ret != 0) {
+			LOG_ERR("Error %d: failed to configure interrupt on %s pin %d", ret,
+				config->fault_pin.port->name, config->fault_pin.pin);
+			return ret;
+		}
+
+		gpio_init_callback(&data->fault_cb_data, fault_event, BIT(config->fault_pin.pin));
+	}
+
+	return 0;
+}
+
+static DEVICE_API(stepper, drv84xx_stepper_api) = {
+	.enable = drv84xx_enable,
+	.disable = drv84xx_disable,
+	.move_by = drv84xx_move_by,
+	.move_to = drv84xx_move_to,
+	.is_moving = step_dir_stepper_common_is_moving,
+	.set_reference_position = step_dir_stepper_common_set_reference_position,
+	.get_actual_position = step_dir_stepper_common_get_actual_position,
+	.set_microstep_interval = step_dir_stepper_common_set_microstep_interval,
+	.run = drv84xx_run,
+	.stop = step_dir_stepper_common_stop,
+	.set_micro_step_res = drv84xx_set_micro_step_res,
+	.get_micro_step_res = drv84xx_get_micro_step_res,
+	.set_event_callback = step_dir_stepper_common_set_event_callback,
+};
+
+#define DRV84XX_DEVICE(inst)                                                                       \
+                                                                                                   \
+	static const struct drv84xx_config drv84xx_config_##inst = {                               \
+		.common = STEP_DIR_STEPPER_DT_INST_COMMON_CONFIG_INIT(inst),                       \
+		.sleep_pin = GPIO_DT_SPEC_INST_GET_OR(inst, sleep_gpios, {0}),                     \
+		.en_pin = GPIO_DT_SPEC_INST_GET_OR(inst, en_gpios, {0}),                           \
+		.m0_pin = GPIO_DT_SPEC_INST_GET_OR(inst, m0_gpios, {0}),                           \
+		.m1_pin = GPIO_DT_SPEC_INST_GET_OR(inst, m1_gpios, {0}),                           \
+		.fault_pin = GPIO_DT_SPEC_INST_GET_OR(inst, fault_gpios, {0}),                     \
+	};                                                                                         \
+                                                                                                   \
+	static struct drv84xx_data drv84xx_data_##inst = {                                         \
+		.common = STEP_DIR_STEPPER_DT_INST_COMMON_DATA_INIT(inst),                         \
+		.ustep_res = DT_INST_PROP(inst, micro_step_res),                                   \
+		.dev = DEVICE_DT_INST_GET(inst),                                                   \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(inst, &drv84xx_init, NULL, &drv84xx_data_##inst,                     \
+			      &drv84xx_config_##inst, POST_KERNEL, CONFIG_STEPPER_INIT_PRIORITY,   \
+			      &drv84xx_stepper_api);
+
+DT_INST_FOREACH_STATUS_OKAY(DRV84XX_DEVICE)
diff --git a/drivers/timer/CMakeLists.txt b/drivers/timer/CMakeLists.txt
index 51b0e552f4a..b642faa8b97 100644
--- a/drivers/timer/CMakeLists.txt
+++ b/drivers/timer/CMakeLists.txt
@@ -12,11 +12,13 @@ zephyr_library_sources_ifdef(CONFIG_ARCV2_TIMER arcv2_timer0.c)
 zephyr_library_sources_ifdef(CONFIG_ARM_ARCH_TIMER arm_arch_timer.c)
 zephyr_library_sources_ifdef(CONFIG_INTEL_ADSP_TIMER intel_adsp_timer.c)
 zephyr_library_sources_ifdef(CONFIG_CC13XX_CC26XX_RTC_TIMER cc13xx_cc26xx_rtc_timer.c)
+zephyr_library_sources_ifdef(CONFIG_CC23X0_SYSTIM_TIMER cc23x0_systim_timer.c)
 zephyr_library_sources_ifdef(CONFIG_CH32V00X_SYSTICK wch_systick_ch32v00x.c)
 zephyr_library_sources_ifdef(CONFIG_CORTEX_M_SYSTICK cortex_m_systick.c)
 zephyr_library_sources_ifdef(CONFIG_ESP32_SYS_TIMER esp32_sys_timer.c)
 zephyr_library_sources_ifdef(CONFIG_GECKO_BURTC_TIMER gecko_burtc_timer.c)
 zephyr_library_sources_ifdef(CONFIG_HPET_TIMER hpet.c)
+zephyr_library_sources_ifdef(CONFIG_ITE_IT51XXX_TIMER ite_it51xxx_timer.c)
 zephyr_library_sources_ifdef(CONFIG_ITE_IT8XXX2_TIMER ite_it8xxx2_timer.c)
 zephyr_library_sources_ifdef(CONFIG_LEON_GPTIMER leon_gptimer.c)
 zephyr_library_sources_ifdef(CONFIG_LITEX_TIMER litex_timer.c)
@@ -26,11 +28,12 @@ zephyr_library_sources_ifdef(CONFIG_MCUX_LPTMR_TIMER mcux_lptmr_timer.c)
 zephyr_library_sources_ifdef(CONFIG_MCUX_OS_TIMER mcux_os_timer.c)
 zephyr_library_sources_ifdef(CONFIG_MCUX_GPT_TIMER mcux_gpt_timer.c)
 zephyr_library_sources_ifdef(CONFIG_MIPS_CP0_TIMER mips_cp0_timer.c)
-zephyr_library_sources_ifdef(CONFIG_NATIVE_POSIX_TIMER native_posix_timer.c)
+zephyr_library_sources_ifdef(CONFIG_NATIVE_SIM_TIMER native_sim_timer.c)
 zephyr_library_sources_ifdef(CONFIG_NPCX_ITIM_TIMER npcx_itim_timer.c)
 zephyr_library_sources_ifdef(CONFIG_NRF_GRTC_TIMER nrf_grtc_timer.c)
 zephyr_library_sources_ifdef(CONFIG_NRF_RTC_TIMER nrf_rtc_timer.c)
 zephyr_library_sources_ifdef(CONFIG_RCAR_CMT_TIMER rcar_cmt_timer.c)
+zephyr_library_sources_ifdef(CONFIG_RENESAS_RA_ULPT_TIMER renesas_ra_ulpt_timer.c)
 zephyr_library_sources_ifdef(CONFIG_RISCV_MACHINE_TIMER riscv_machine_timer.c)
 zephyr_library_sources_ifdef(CONFIG_RV32M1_LPTMR_TIMER rv32m1_lptmr_timer.c)
 zephyr_library_sources_ifdef(CONFIG_REALTEK_RTS5912_RTMR realtek_rts5912_rtmr.c)
@@ -43,3 +46,4 @@ zephyr_library_sources_ifdef(CONFIG_XTENSA_TIMER xtensa_sys_timer.c)
 zephyr_library_sources_ifdef(CONFIG_SMARTBOND_TIMER smartbond_timer.c)
 zephyr_library_sources_ifdef(CONFIG_MTK_ADSP_TIMER mtk_adsp_timer.c)
 zephyr_library_sources_ifdef(CONFIG_SY1XX_SYS_TIMER sy1xx_sys_timer.c)
+zephyr_library_sources_ifdef(CONFIG_RZA2M_OS_TIMER renesas_rza2m_os_timer.c)
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index f017589a60e..225f23fef35 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -70,10 +70,12 @@ source "drivers/timer/Kconfig.arcv2"
 source "drivers/timer/Kconfig.arm_arch"
 source "drivers/timer/Kconfig.cavs"
 source "drivers/timer/Kconfig.cc13xx_cc26xx_rtc"
+source "drivers/timer/Kconfig.cc23x0_systim"
 source "drivers/timer/Kconfig.wch_ch32v00x"
 source "drivers/timer/Kconfig.cortex_m_systick"
 source "drivers/timer/Kconfig.esp32"
 source "drivers/timer/Kconfig.gecko"
+source "drivers/timer/Kconfig.it51xxx"
 source "drivers/timer/Kconfig.ite_it8xxx2"
 source "drivers/timer/Kconfig.leon_gptimer"
 source "drivers/timer/Kconfig.litex"
@@ -83,7 +85,7 @@ source "drivers/timer/Kconfig.mcux_lptmr"
 source "drivers/timer/Kconfig.mcux_os"
 source "drivers/timer/Kconfig.mec5"
 source "drivers/timer/Kconfig.mips_cp0"
-source "drivers/timer/Kconfig.native_posix"
+source "drivers/timer/Kconfig.native_sim"
 source "drivers/timer/Kconfig.npcx_itim"
 source "drivers/timer/Kconfig.nrf_rtc"
 source "drivers/timer/Kconfig.nrf_grtc"
@@ -101,6 +103,8 @@ source "drivers/timer/Kconfig.xlnx_psttc"
 source "drivers/timer/Kconfig.xtensa"
 source "drivers/timer/Kconfig.mtk_adsp"
 source "drivers/timer/Kconfig.sy1xx_sys_timer"
+source "drivers/timer/Kconfig.renesas_ra_ulpt"
+source "drivers/timer/Kconfig.renesas_rza2m"
 
 endmenu
 
diff --git a/drivers/timer/Kconfig.cc23x0_systim b/drivers/timer/Kconfig.cc23x0_systim
new file mode 100644
index 00000000000..41db73e6d52
--- /dev/null
+++ b/drivers/timer/Kconfig.cc23x0_systim
@@ -0,0 +1,13 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+# Copyright (c) 2024 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config CC23X0_SYSTIM_TIMER
+	bool "TI SimpleLink CC23X0 system clock timer"
+	default y
+	depends on HAS_CC23X0_SDK
+	select TICKLESS_CAPABLE
+	help
+	  This module provides the "system clock driver" interfaces
+	  for the TI Simplelink CC23X0 devices.
diff --git a/drivers/timer/Kconfig.cortex_m_systick b/drivers/timer/Kconfig.cortex_m_systick
index 2a4f48832cf..c0e8140fcb5 100644
--- a/drivers/timer/Kconfig.cortex_m_systick
+++ b/drivers/timer/Kconfig.cortex_m_systick
@@ -43,20 +43,69 @@ config CORTEX_M_SYSTICK_64BIT_CYCLE_COUNTER
 	  This is set to y by default when the hardware clock is fast enough
 	  to wrap sys_clock_cycle_get_32() in about a minute or less.
 
-config CORTEX_M_SYSTICK_IDLE_TIMER
-	bool "Use an additional timer while entering IDLE"
-	default $(dt_chosen_enabled,$(DT_CHOSEN_IDLE_TIMER))
+choice CORTEX_M_SYSTICK_LPM_TIMER
+	prompt "SysTick companion low-power mode timer"
+	# If all dependencies are enabled, and /chosen/cortex-m-idle-timer
+	# is enabled, default to using the Counter API-based LPM timer.
+	# Otherwise, the first choice (LPM_TIMER_NONE) will be selected
+	# automatically, and no LPM timer will be enabled.
+	default CORTEX_M_SYSTICK_LPM_TIMER_COUNTER
+	help
+	  It is common for SoCs equipped with SysTick to use it as system timer.
+	  However, depending on the SoC implementation, entering low-power mode
+	  may turn off the SysTick clock or place SysTick under reset.
+
+	  On such SoCs, a vendor-specific timer that remains active in low-power
+	  mode will usually be provided - however, it may be unfit for usage as
+	  system timer, for example because its frequency is too low.
+
+	  With this option, such vendor-specific timer can be selected and used by
+	  the SysTick driver to ensure proper system operation in low-power mode.
+
+	  NOTE: since Power Management has to be enabled if the SoC may enter in
+	  low-power mode, no LPM timer can be selected if PM is not enabled.
+	  Tickless kernel must also be enabled, since periodic interrupts would
+	  prevent the system from entering in low-power modes.
+
+config CORTEX_M_SYSTICK_LPM_TIMER_NONE
+	bool "None"
+	help
+	  Use no additional device as low-power mode timer.
+
+	  The SoC must never enter a low-power mode where SysTick is disabled when
+	  this option is selected; otherwise, system behavior becomes unpredictable.
+
+if TICKLESS_KERNEL && PM
+
+config CORTEX_M_SYSTICK_LPM_TIMER_COUNTER
+	bool "Counter API timer"
+	depends on $(dt_chosen_enabled,$(DT_CHOSEN_IDLE_TIMER))
 	depends on COUNTER
-	depends on TICKLESS_KERNEL
-	depends on PM
 	help
-	  There are chips e.g. STMFX family that use SysTick as a system timer,
-	  but SysTick is not clocked in low power mode. These chips usually have
-	  another timer that is not stopped, but it has lower frequency e.g.
-	  RTC, thus it can't be used as a main system timer.
+	  Use a device that implements the counter API as low-power mode timer.
+
+	  The device is selected by property "/chosen/cortex-m-idle-timer".
+
+config CORTEX_M_SYSTICK_LPM_TIMER_HOOKS
+	bool "Hook-based timer"
+	help
+	  Use hooks in the SysTick driver to configure the low-power mode timer.
+	  Refer to `include/drivers/timer/cortex_m_systick.h` for more details.
+
+endif # PM
+endchoice # CORTEX_M_SYSTICK_LPM_TIMER
+
+config CORTEX_M_SYSTICK_RESET_BY_LPM
+	bool
+	depends on !CORTEX_M_SYSTICK_LPM_TIMER_NONE
+	help
+	  Some SoCs provide one or more low-power mode which, as part of their
+	  operation, place SysTick or the entire CPU under reset. This requires
+	  special care from the driver - notably, SysTick needs to be restarted
+	  after waking up from such a low-power mode.
 
-	  Use the IDLE timer for timeout (wakeup) when the system is entering
-	  IDLE state.
+	  Select this symbol if your SoC has a low-power mode that places SysTick
+	  under reset. Note that this requires that the platform provides a timer
+	  active in low-power mode, since SysTick cannot be used for timekeeping.
 
-	  The chosen IDLE timer node has to support setting alarm from the
-	  counter API.
+	  Refer to CONFIG_CORTEX_M_SYSTICK_LPM_TIMER for more details.
diff --git a/drivers/timer/Kconfig.esp32 b/drivers/timer/Kconfig.esp32
index 304ad1271b7..ff10f017866 100644
--- a/drivers/timer/Kconfig.esp32
+++ b/drivers/timer/Kconfig.esp32
@@ -5,7 +5,7 @@
 
 config ESP32_SYS_TIMER
 	bool "ESP32 sys-timer support (ESP32Cx series)"
-	depends on SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
+	depends on SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || (SOC_SERIES_ESP32C6 && !SOC_ESP32C6_LPCORE)
 	default y
 	select TICKLESS_CAPABLE
 	select TIMER_HAS_64BIT_CYCLE_COUNTER
diff --git a/drivers/timer/Kconfig.it51xxx b/drivers/timer/Kconfig.it51xxx
new file mode 100644
index 00000000000..6d260909539
--- /dev/null
+++ b/drivers/timer/Kconfig.it51xxx
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config ITE_IT51XXX_TIMER
+	bool "ITE it51xxx timer driver"
+	default y
+	depends on DT_HAS_ITE_IT51XXX_TIMER_ENABLED
+	select TICKLESS_CAPABLE
+	help
+	  This module implements a kernel device driver for the ITE IT51XXX
+	  HW timer model.
diff --git a/drivers/timer/Kconfig.mcux_lptmr b/drivers/timer/Kconfig.mcux_lptmr
index 851c49ebbfb..0e68b22b399 100644
--- a/drivers/timer/Kconfig.mcux_lptmr
+++ b/drivers/timer/Kconfig.mcux_lptmr
@@ -5,22 +5,11 @@
 
 config MCUX_LPTMR_TIMER
 	bool "MCUX LPTMR timer"
-	default y
-	depends on DT_HAS_NXP_KINETIS_LPTMR_ENABLED || \
-		   MCUX_KINETIS_LPTMR
+	default n
+	depends on DT_HAS_NXP_LPTMR_ENABLED
 	depends on !COUNTER_MCUX_LPTMR
 	select SYSTEM_TIMER_HAS_DISABLE_SUPPORT
 	help
 	  This module implements a kernel device driver for the NXP MCUX Low
 	  Power Timer (LPTMR) and provides the standard "system clock driver"
 	  interfaces.
-
-config MCUX_KINETIS_LPTMR
-	bool
-	default y
-	depends on DT_HAS_NXP_KINETIS_LPTMR_ENABLED
-	select DEPRECATED
-	help
-	  The compatible string "nxp,kinetis-lptmr" should
-	  be swiched to "nxp,lptmr" in DT. The former will
-	  be removed eventually.
diff --git a/drivers/timer/Kconfig.mtk_adsp b/drivers/timer/Kconfig.mtk_adsp
index d3b7501e307..46052395a13 100644
--- a/drivers/timer/Kconfig.mtk_adsp
+++ b/drivers/timer/Kconfig.mtk_adsp
@@ -3,6 +3,7 @@
 
 config MTK_ADSP_TIMER
 	bool "MediaTek Audio DSP timer"
+	depends on SOC_FAMILY_MTK
 	select TICKLESS_CAPABLE
 	select TIMER_HAS_64BIT_CYCLE_COUNTER
 	select SYSTEM_CLOCK_LOCK_FREE_COUNT
diff --git a/drivers/timer/Kconfig.native_posix b/drivers/timer/Kconfig.native_posix
deleted file mode 100644
index ad2c4acad76..00000000000
--- a/drivers/timer/Kconfig.native_posix
+++ /dev/null
@@ -1,15 +0,0 @@
-# Copyright (c) 2014-2015 Wind River Systems, Inc.
-# Copyright (c) 2016 Cadence Design Systems, Inc.
-# Copyright (c) 2019 Intel Corp.
-# SPDX-License-Identifier: Apache-2.0
-
-config NATIVE_POSIX_TIMER
-	bool "(POSIX) native_sim/posix timer driver"
-	default y
-	depends on BOARD_NATIVE_POSIX || BOARD_NATIVE_SIM
-	select TICKLESS_CAPABLE
-	select TIMER_HAS_64BIT_CYCLE_COUNTER
-	select SYSTEM_TIMER_HAS_DISABLE_SUPPORT
-	help
-	  This module implements a kernel device driver for the native_sim/posix HW timer
-	  model
diff --git a/drivers/timer/Kconfig.native_sim b/drivers/timer/Kconfig.native_sim
new file mode 100644
index 00000000000..780517b973a
--- /dev/null
+++ b/drivers/timer/Kconfig.native_sim
@@ -0,0 +1,22 @@
+# Copyright (c) 2014-2015 Wind River Systems, Inc.
+# Copyright (c) 2016 Cadence Design Systems, Inc.
+# Copyright (c) 2019 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+config NATIVE_SIM_TIMER
+	bool "(POSIX) native_sim timer driver"
+	default y
+	depends on BOARD_NATIVE_SIM
+	select TICKLESS_CAPABLE
+	select TIMER_HAS_64BIT_CYCLE_COUNTER
+	select SYSTEM_TIMER_HAS_DISABLE_SUPPORT
+	help
+	  This module implements a kernel device driver for the native_sim HW timer model
+
+config NATIVE_POSIX_TIMER
+	bool "(POSIX) native_sim/posix timer driver (deprecated)"
+	select NATIVE_SIM_TIMER
+	select DEPRECATED
+	depends on BOARD_NATIVE_SIM
+	help
+	  Deprecated option. Replaced by NATIVE_SIM_TIMER
diff --git a/drivers/timer/Kconfig.realtek_rts5912_rtmr b/drivers/timer/Kconfig.realtek_rts5912_rtmr
index 560ea7a7059..a41e0649591 100644
--- a/drivers/timer/Kconfig.realtek_rts5912_rtmr
+++ b/drivers/timer/Kconfig.realtek_rts5912_rtmr
@@ -5,6 +5,7 @@
 
 config REALTEK_RTS5912_RTMR
 	bool "Realtek RTS5912 RTOS Timer"
+	depends on SOC_SERIES_RTS5912
 	default y if DT_HAS_REALTEK_RTS5912_RTMR_ENABLED
 	select TICKLESS_CAPABLE
 	select SYSTEM_TIMER_HAS_DISABLE_SUPPORT
diff --git a/drivers/timer/Kconfig.renesas_ra_ulpt b/drivers/timer/Kconfig.renesas_ra_ulpt
new file mode 100644
index 00000000000..baaf86ca934
--- /dev/null
+++ b/drivers/timer/Kconfig.renesas_ra_ulpt
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config RENESAS_RA_ULPT_TIMER
+	bool "Renesas RA Series ULPT Timer"
+	default y if PM
+	depends on DT_HAS_RENESAS_RA_ULPT_TIMER_ENABLED
+	select TICKLESS_CAPABLE
+	help
+	  This module implements a kernel device driver for the Renesas RA series
+	  ULPT timer and provides the standard "system clock driver" interfaces.
diff --git a/drivers/timer/Kconfig.renesas_rza2m b/drivers/timer/Kconfig.renesas_rza2m
new file mode 100644
index 00000000000..1e486a9b3cb
--- /dev/null
+++ b/drivers/timer/Kconfig.renesas_rza2m
@@ -0,0 +1,13 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config RZA2M_OS_TIMER
+	bool "Renesas RZ/A2M OS timer"
+	default y
+	depends on DT_HAS_RENESAS_RZA2M_OSTM_ENABLED
+	select TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
+	select SYSTEM_TIMER_HAS_DISABLE_SUPPORT
+	select TICKLESS_CAPABLE
+	help
+	  This module implements a kernel device driver for the Renesas RZ/A2M
+	  platform provides the standard "system clock driver" interfaces.
diff --git a/drivers/timer/Kconfig.riscv_machine b/drivers/timer/Kconfig.riscv_machine
index efbd4d322f7..be90604da30 100644
--- a/drivers/timer/Kconfig.riscv_machine
+++ b/drivers/timer/Kconfig.riscv_machine
@@ -6,13 +6,8 @@
 config RISCV_MACHINE_TIMER
 	bool "RISCV Machine Timer"
 	default y
-	depends on DT_HAS_ANDESTECH_MACHINE_TIMER_ENABLED || \
-		   DT_HAS_NEORV32_MACHINE_TIMER_ENABLED || \
-		   DT_HAS_NUCLEI_SYSTIMER_ENABLED || \
-		   DT_HAS_SIFIVE_CLINT0_ENABLED || \
-		   DT_HAS_TELINK_MACHINE_TIMER_ENABLED || \
-		   DT_HAS_LOWRISC_MACHINE_TIMER_ENABLED || \
-		   DT_HAS_NIOSV_MACHINE_TIMER_ENABLED
+	depends on DT_HAS_RISCV_MACHINE_TIMER_ENABLED || \
+		   DT_HAS_NUCLEI_SYSTIMER_ENABLED
 	select TICKLESS_CAPABLE
 	select TIMER_HAS_64BIT_CYCLE_COUNTER
 	help
diff --git a/drivers/timer/Kconfig.sam0_rtc b/drivers/timer/Kconfig.sam0_rtc
index 14c4ee73939..6d97d16c564 100644
--- a/drivers/timer/Kconfig.sam0_rtc
+++ b/drivers/timer/Kconfig.sam0_rtc
@@ -1,12 +1,14 @@
 # Copyright (c) 2014-2015 Wind River Systems, Inc.
 # Copyright (c) 2016 Cadence Design Systems, Inc.
 # Copyright (c) 2019 Intel Corp.
+# Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
 config SAM0_RTC_TIMER
 	bool "Atmel SAM0 series RTC timer"
 	default y
-	depends on DT_HAS_ATMEL_SAM0_RTC_ENABLED
+	depends on DT_HAS_ATMEL_SAM0_RTC_ENABLED \
+		&& $(dt_nodelabel_bool_prop,rtc,systimer)
 	select PINCTRL
 	select TICKLESS_CAPABLE
 	help
diff --git a/drivers/timer/Kconfig.silabs b/drivers/timer/Kconfig.silabs
index 2e9abba8ef6..aa7a013e9c0 100644
--- a/drivers/timer/Kconfig.silabs
+++ b/drivers/timer/Kconfig.silabs
@@ -3,7 +3,7 @@
 
 config SILABS_SLEEPTIMER_TIMER
 	bool "Silabs Sleeptimer system clock driver"
-	depends on SOC_FAMILY_SILABS_S2
+	depends on SOC_FAMILY_SILABS_S2 || SOC_FAMILY_SILABS_SIWX91X
 	depends on DT_HAS_SILABS_GECKO_STIMER_ENABLED
 	select SOC_SILABS_SLEEPTIMER
 	select TICKLESS_CAPABLE
diff --git a/drivers/timer/Kconfig.wch_ch32v00x b/drivers/timer/Kconfig.wch_ch32v00x
index 3a180d691eb..744d54c2c0d 100644
--- a/drivers/timer/Kconfig.wch_ch32v00x
+++ b/drivers/timer/Kconfig.wch_ch32v00x
@@ -3,6 +3,6 @@
 
 config CH32V00X_SYSTICK
 	bool "CH32V00X systick timer"
-	depends on SOC_CH32V003
+	depends on SOC_CH32V003 || SOC_SERIES_QINGKE_V4C
 	default y
 	depends on DT_HAS_WCH_SYSTICK_ENABLED
diff --git a/drivers/timer/ambiq_stimer.c b/drivers/timer/ambiq_stimer.c
index f7748cce25a..045d2f9422d 100644
--- a/drivers/timer/ambiq_stimer.c
+++ b/drivers/timer/ambiq_stimer.c
@@ -20,20 +20,27 @@
 #include <zephyr/spinlock.h>
 
 /* ambiq-sdk includes */
-#include <am_mcu_apollo.h>
+#include <soc.h>
 
 #define COUNTER_MAX UINT32_MAX
 
 #define CYC_PER_TICK (sys_clock_hw_cycles_per_sec() / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
 #define MAX_TICKS    ((k_ticks_t)(COUNTER_MAX / CYC_PER_TICK) - 1)
 #define MAX_CYCLES   (MAX_TICKS * CYC_PER_TICK)
-#if defined(CONFIG_SOC_SERIES_APOLLO3X)
+#if defined(CONFIG_SOC_SERIES_APOLLO3X) || defined(CONFIG_SOC_SERIES_APOLLO5X)
 #define MIN_DELAY 1
-#elif defined(CONFIG_SOC_SERIES_APOLLO4X)
+#else
 #define MIN_DELAY 4
 #endif
 
+#if defined(CONFIG_SOC_SERIES_APOLLO5X)
+#define COMPARE_INTERRUPT AM_HAL_STIMER_INT_COMPAREA
+#else
+/* A Possible clock glitch could rarely cause the Stimer interrupt to be lost.
+ * Set up a backup comparator to handle this case
+ */
 #define COMPARE_INTERRUPT (AM_HAL_STIMER_INT_COMPAREA | AM_HAL_STIMER_INT_COMPAREB)
+#endif
 
 #define COMPAREA_IRQ (DT_INST_IRQN(0))
 #define COMPAREB_IRQ (COMPAREA_IRQ + 1)
@@ -82,7 +89,9 @@ static void update_tick_counter(void)
 static void ambiq_stimer_delta_set(uint32_t ui32Delta)
 {
 	am_hal_stimer_compare_delta_set(0, ui32Delta);
+#if !defined(CONFIG_SOC_SERIES_APOLLO5X)
 	am_hal_stimer_compare_delta_set(1, ui32Delta + 1);
+#endif
 }
 
 static void stimer_isr(const void *arg)
@@ -201,10 +210,14 @@ static int stimer_init(void)
 	am_hal_stimer_config((oldCfg & ~(AM_HAL_STIMER_CFG_FREEZE | CTIMER_STCFG_CLKSEL_Msk)) |
 			     TIMER_CLKSRC | AM_HAL_STIMER_CFG_COMPARE_A_ENABLE |
 			     AM_HAL_STIMER_CFG_COMPARE_B_ENABLE);
-#else
+#elif defined(CONFIG_SOC_SERIES_APOLLO4X)
 	am_hal_stimer_config((oldCfg & ~(AM_HAL_STIMER_CFG_FREEZE | STIMER_STCFG_CLKSEL_Msk)) |
 			     TIMER_CLKSRC | AM_HAL_STIMER_CFG_COMPARE_A_ENABLE |
 			     AM_HAL_STIMER_CFG_COMPARE_B_ENABLE);
+#elif defined(CONFIG_SOC_SERIES_APOLLO5X)
+	/* No need for backup comparator any more */
+	am_hal_stimer_config((oldCfg & ~(AM_HAL_STIMER_CFG_FREEZE | STIMER_STCFG_CLKSEL_Msk)) |
+			     TIMER_CLKSRC | AM_HAL_STIMER_CFG_COMPARE_A_ENABLE);
 #endif
 	g_last_time_stamp = am_hal_stimer_counter_get();
 
@@ -212,12 +225,13 @@ static int stimer_init(void)
 	 * Set up a backup comparator to handle this case
 	 */
 	NVIC_ClearPendingIRQ(COMPAREA_IRQ);
-	NVIC_ClearPendingIRQ(COMPAREB_IRQ);
 	IRQ_CONNECT(COMPAREA_IRQ, 0, stimer_isr, 0, 0);
-	IRQ_CONNECT(COMPAREB_IRQ, 0, stimer_isr, 0, 0);
 	irq_enable(COMPAREA_IRQ);
+#if !defined(CONFIG_SOC_SERIES_APOLLO5X)
+	NVIC_ClearPendingIRQ(COMPAREB_IRQ);
+	IRQ_CONNECT(COMPAREB_IRQ, 0, stimer_isr, 0, 0);
 	irq_enable(COMPAREB_IRQ);
-
+#endif
 	am_hal_stimer_int_enable(COMPARE_INTERRUPT);
 	/* Start timer with period CYC_PER_TICK if tickless is not enabled */
 	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
diff --git a/drivers/timer/cc23x0_systim_timer.c b/drivers/timer/cc23x0_systim_timer.c
new file mode 100644
index 00000000000..1bc264ba179
--- /dev/null
+++ b/drivers/timer/cc23x0_systim_timer.c
@@ -0,0 +1,154 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ti_cc23x0_systim_timer
+
+/*
+ * TI SimpleLink CC23X0 timer driver based on SYSTIM
+ */
+
+#include <soc.h>
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/timer/system_timer.h>
+#include <zephyr/irq.h>
+#include <zephyr/spinlock.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/sys/util.h>
+
+#include <inc/hw_types.h>
+#include <inc/hw_memmap.h>
+#include <inc/hw_systim.h>
+#include <inc/hw_evtsvt.h>
+
+/* Kernel tick period in microseconds (same timebase as systim) */
+#define TICK_PERIOD_MICRO_SEC (1000000 / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
+
+/*
+ * Max number of systim ticks into the future
+ *
+ * Under the hood, the kernel timer uses the SysTimer whose events trigger
+ * immediately if the compare value is less than 2^22 systimer ticks in the past
+ * (4.194sec at 1us resolution). Therefore, the max number of SysTimer ticks you
+ * can schedule into the future is 2^32 - 2^22 - 1 ticks (~= 4290 sec at 1us
+ * resolution).
+ */
+#define SYSTIM_TIMEOUT_MAX 0xFFBFFFFFU
+
+/* Set systim interrupt to lowest priority */
+#define SYSTIM_ISR_PRIORITY 3U
+
+/* Keep track of systim counter at previous announcement to the kernel */
+static uint32_t last_systim_count;
+
+static void systim_isr(const void *arg);
+static int sys_clock_driver_init(void);
+
+/*
+ * Set system clock timeout.
+ */
+void sys_clock_set_timeout(int32_t ticks, bool idle)
+{
+	ARG_UNUSED(idle);
+
+	/* If timeout is necessary */
+	if (ticks != K_TICKS_FOREVER) {
+		/* Get current value as early as possible */
+		uint32_t now_tick = HWREG(SYSTIM_BASE + SYSTIM_O_TIME1U);
+		uint32_t timeout = ticks * TICK_PERIOD_MICRO_SEC;
+
+		if (timeout > SYSTIM_TIMEOUT_MAX) {
+			timeout = SYSTIM_TIMEOUT_MAX;
+		}
+		/* This should wrap around */
+		HWREG(SYSTIM_BASE + SYSTIM_O_CH0CC) = now_tick + timeout;
+	}
+}
+
+uint32_t sys_clock_elapsed(void)
+{
+	/* Get current value as early as possible */
+	uint32_t current_systim_count = HWREG(SYSTIM_BASE + SYSTIM_O_TIME1U);
+	uint32_t elapsed_systim;
+
+	if (current_systim_count >= last_systim_count) {
+		elapsed_systim = current_systim_count - last_systim_count;
+	} else {
+		elapsed_systim = (UINT32_MAX - last_systim_count) + current_systim_count;
+	}
+
+	int32_t elapsed_ticks = elapsed_systim / TICK_PERIOD_MICRO_SEC;
+
+	return elapsed_ticks;
+}
+
+uint32_t sys_clock_cycle_get_32(void)
+{
+	return HWREG(SYSTIM_BASE + SYSTIM_O_TIME1U);
+}
+
+void systim_isr(const void *arg)
+{
+	/* Get current value as early as possible */
+	uint32_t current_systim_count = HWREG(SYSTIM_BASE + SYSTIM_O_TIME1U);
+	uint32_t elapsed_systim;
+
+	if (current_systim_count >= last_systim_count) {
+		elapsed_systim = current_systim_count - last_systim_count;
+	} else {
+		elapsed_systim = (UINT32_MAX - last_systim_count) + current_systim_count;
+	}
+
+	int32_t elapsed_ticks = elapsed_systim / TICK_PERIOD_MICRO_SEC;
+
+	sys_clock_announce(elapsed_ticks);
+
+	last_systim_count = current_systim_count;
+
+	/* Do not re-arm systim. Zephyr will do so through sys_clock_set_timeout */
+}
+
+static int sys_clock_driver_init(void)
+{
+	uint32_t now_tick;
+
+	/* Get current value as early as possible */
+	now_tick = HWREG(SYSTIM_BASE + SYSTIM_O_TIME1U);
+	last_systim_count = now_tick;
+
+	/* Clear any pending interrupts on SysTimer channel 0 */
+	HWREG(SYSTIM_BASE + SYSTIM_O_ICLR) = SYSTIM_ICLR_EV0_CLR;
+
+	/*
+	 * Configure SysTimer channel 0 to compare mode with timer
+	 * resolution of 1 us.
+	 */
+	HWREG(SYSTIM_BASE + SYSTIM_O_CH0CFG) = 0;
+
+	/* Make SysTimer halt on CPU debug halt */
+	HWREG(SYSTIM_BASE + SYSTIM_O_EMU) = SYSTIM_EMU_HALT_STOP;
+
+	HWREG(EVTSVT_BASE + EVTSVT_O_CPUIRQ16SEL) = EVTSVT_CPUIRQ16SEL_PUBID_SYSTIM0;
+
+	/*
+	 * Set IMASK for channel 0. IMASK is used by the power driver to know
+	 * which systimer channels are active.
+	 */
+	HWREG(SYSTIM_BASE + SYSTIM_O_IMSET) = SYSTIM_IMSET_EV0_SET;
+
+	/* This should wrap around and set a maximum timeout */
+	HWREG(SYSTIM_BASE + SYSTIM_O_CH0CC) = now_tick + SYSTIM_TIMEOUT_MAX;
+
+	/* Take configurable interrupt IRQ16 for systimer */
+	IRQ_CONNECT(CPUIRQ16_IRQn, SYSTIM_ISR_PRIORITY, systim_isr, 0, 0);
+	irq_enable(CPUIRQ16_IRQn);
+
+	return 0;
+}
+
+SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
diff --git a/drivers/timer/cortex_m_systick.c b/drivers/timer/cortex_m_systick.c
index 1a3183af5e7..029738900ef 100644
--- a/drivers/timer/cortex_m_systick.c
+++ b/drivers/timer/cortex_m_systick.c
@@ -12,6 +12,8 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/drivers/counter.h>
 
+#include "cortex_m_systick.h"
+
 #define COUNTER_MAX 0x00ffffff
 #define TIMER_STOPPED 0xff000000
 
@@ -76,7 +78,7 @@ static cycle_t announced_cycles;
  */
 static volatile uint32_t overflow_cyc;
 
-#ifdef CONFIG_CORTEX_M_SYSTICK_IDLE_TIMER
+#if !defined(CONFIG_CORTEX_M_SYSTICK_LPM_TIMER_NONE)
 /* This local variable indicates that the timeout was set right before
  * entering idle state.
  *
@@ -86,15 +88,76 @@ static volatile uint32_t overflow_cyc;
  */
 static bool timeout_idle;
 
+#if !defined(CONFIG_CORTEX_M_SYSTICK_RESET_BY_LPM)
 /* Cycle counter before entering the idle state. */
 static cycle_t cycle_pre_idle;
+#endif /* !CONFIG_CORTEX_M_SYSTICK_RESET_BY_LPM */
 
+#if defined(CONFIG_CORTEX_M_SYSTICK_LPM_TIMER_COUNTER)
 /* Idle timer value before entering the idle state. */
 static uint32_t idle_timer_pre_idle;
 
 /* Idle timer used for timer while entering the idle state */
 static const struct device *idle_timer = DEVICE_DT_GET(DT_CHOSEN(zephyr_cortex_m_idle_timer));
-#endif /* CONFIG_CORTEX_M_SYSTICK_IDLE_TIMER */
+#endif /* CONFIG_CORTEX_M_SYSTICK_LPM_TIMER_COUNTER */
+#endif /* !CONFIG_CORTEX_M_SYSTICK_LPM_TIMER_NONE */
+
+#if defined(CONFIG_CORTEX_M_SYSTICK_LPM_TIMER_COUNTER)
+/**
+ * To simplify the driver, implement the callout to Counter API
+ * as hooks that would be provided by platform drivers if
+ * CONFIG_CORTEX_M_SYSTICK_LPM_TIMER_HOOKS was selected instead.
+ */
+void z_cms_lptim_hook_on_lpm_entry(uint64_t max_lpm_time_us)
+{
+	struct counter_alarm_cfg cfg = {
+		.callback = NULL,
+		.ticks = counter_us_to_ticks(idle_timer, max_lpm_time_us),
+		.user_data = NULL,
+		.flags = 0,
+	};
+
+	/**
+	 * Disable the counter alarm in case it was already running.
+	 */
+	counter_cancel_channel_alarm(idle_timer, 0);
+
+	/* Set the alarm using timer that runs the idle.
+	 * Needed rump-up/setting time, lower accurency etc. should be
+	 * included in the exit-latency in the power state definition.
+	 */
+	counter_set_channel_alarm(idle_timer, 0, &cfg);
+
+	/* Store current value of the selected timer to calculate a
+	 * difference in measurements after exiting the idle state.
+	 */
+	counter_get_value(idle_timer, &idle_timer_pre_idle);
+}
+
+uint64_t z_cms_lptim_hook_on_lpm_exit(void)
+{
+	/**
+	 * Calculate how much time elapsed according to counter.
+	 */
+	uint32_t idle_timer_post, idle_timer_diff;
+
+	counter_get_value(idle_timer, &idle_timer_post);
+
+	/**
+	 * Check for counter timer overflow
+	 * (TODO: this doesn't work for downcounting timers!)
+	 */
+	if (idle_timer_pre_idle > idle_timer_post) {
+		idle_timer_diff =
+			(counter_get_top_value(idle_timer) - idle_timer_pre_idle) +
+			idle_timer_post + 1;
+	} else {
+		idle_timer_diff = idle_timer_post - idle_timer_pre_idle;
+	}
+
+	return (uint64_t)counter_ticks_to_us(idle_timer, idle_timer_diff);
+}
+#endif /* CONFIG_CORTEX_M_SYSTICK_LPM_TIMER_COUNTER */
 
 /* This internal function calculates the amount of HW cycles that have
  * elapsed since the last time the absolute HW cycles counter has been
@@ -169,6 +232,10 @@ static uint32_t elapsed(void)
 ARCH_ISR_DIAG_OFF
 __attribute__((interrupt("IRQ"))) void sys_clock_isr(void)
 {
+#ifdef CONFIG_TRACING_ISR
+	sys_trace_isr_enter();
+#endif /* CONFIG_TRACING_ISR */
+
 	uint32_t dcycles;
 	uint32_t dticks;
 
@@ -181,7 +248,7 @@ __attribute__((interrupt("IRQ"))) void sys_clock_isr(void)
 	cycle_count += overflow_cyc;
 	overflow_cyc = 0;
 
-#ifdef CONFIG_CORTEX_M_SYSTICK_IDLE_TIMER
+#if defined(CONFIG_CORTEX_M_SYSTICK_LPM_TIMER_COUNTER)
 	/* Rare case, when the interrupt was triggered, with previously programmed
 	 * LOAD value, just before entering the idle mode (SysTick is clocked) or right
 	 * after exiting the idle mode, before executing the procedure in the
@@ -193,7 +260,7 @@ __attribute__((interrupt("IRQ"))) void sys_clock_isr(void)
 
 		return;
 	}
-#endif /* CONFIG_CORTEX_M_SYSTICK_IDLE_TIMER */
+#endif /* CONFIG_CORTEX_M_SYSTICK_LPM_TIMER_COUNTER */
 
 	if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
 		/* In TICKLESS mode, the SysTick.LOAD is re-programmed
@@ -217,6 +284,11 @@ __attribute__((interrupt("IRQ"))) void sys_clock_isr(void)
 	}
 
 	ISR_DIRECT_PM();
+
+#ifdef CONFIG_TRACING_ISR
+	sys_trace_isr_exit();
+#endif /* CONFIG_TRACING_ISR */
+
 	z_arm_int_exit();
 }
 ARCH_ISR_DIAG_ON
@@ -235,35 +307,40 @@ void sys_clock_set_timeout(int32_t ticks, bool idle)
 		return;
 	}
 
-#ifdef CONFIG_CORTEX_M_SYSTICK_IDLE_TIMER
+#if !defined(CONFIG_CORTEX_M_SYSTICK_LPM_TIMER_NONE)
 	if (idle) {
 		uint64_t timeout_us =
 			((uint64_t)ticks * USEC_PER_SEC) / CONFIG_SYS_CLOCK_TICKS_PER_SEC;
-		struct counter_alarm_cfg cfg = {
-			.callback = NULL,
-			.ticks = counter_us_to_ticks(idle_timer, timeout_us),
-			.user_data = NULL,
-			.flags = 0,
-		};
 
 		timeout_idle = true;
 
-		/* Set the alarm using timer that runs the idle.
-		 * Needed rump-up/setting time, lower accurency etc. should be
-		 * included in the exit-latency in the power state definition.
+		/**
+		 * Invoke platform-specific layer to configure LPTIM
+		 * such that system wakes up after timeout elapses.
 		 */
-		counter_cancel_channel_alarm(idle_timer, 0);
-		counter_set_channel_alarm(idle_timer, 0, &cfg);
+		z_cms_lptim_hook_on_lpm_entry(timeout_us);
 
-		/* Store current values to calculate a difference in
-		 * measurements after exiting the idle state.
+#if !defined(CONFIG_CORTEX_M_SYSTICK_RESET_BY_LPM)
+		/* Store current value of SysTick counter to be able to
+		 * calculate a difference in measurements after exiting
+		 * the low-power state.
 		 */
-		counter_get_value(idle_timer, &idle_timer_pre_idle);
 		cycle_pre_idle = cycle_count + elapsed();
+#else /* CONFIG_CORTEX_M_SYSTICK_RESET_BY_LPM */
+		/**
+		 * SysTick will be placed under reset once we enter
+		 * low-power mode. Turn it off right now then update
+		 * the cycle counter now, since we won't be able to
+		 * to it after waking up.
+		 */
+		sys_clock_disable();
 
+		cycle_count += elapsed();
+		overflow_cyc = 0;
+#endif /* !CONFIG_CORTEX_M_SYSTICK_RESET_BY_LPM */
 		return;
 	}
-#endif /* CONFIG_CORTEX_M_SYSTICK_IDLE_TIMER */
+#endif /* !CONFIG_CORTEX_M_SYSTICK_LPM_TIMER_NONE */
 
 #if defined(CONFIG_TICKLESS_KERNEL)
 	uint32_t delay;
@@ -369,29 +446,29 @@ uint64_t sys_clock_cycle_get_64(void)
 
 void sys_clock_idle_exit(void)
 {
-#ifdef CONFIG_CORTEX_M_SYSTICK_IDLE_TIMER
+#if !defined(CONFIG_CORTEX_M_SYSTICK_LPM_TIMER_NONE)
 	if (timeout_idle) {
 		cycle_t systick_diff, missed_cycles;
-		uint32_t idle_timer_diff, idle_timer_post, dcycles, dticks;
+		uint32_t dcycles, dticks;
 		uint64_t systick_us, idle_timer_us;
 
-		/* Get current values for both timers */
-		counter_get_value(idle_timer, &idle_timer_post);
+#if !defined(CONFIG_CORTEX_M_SYSTICK_RESET_BY_LPM)
+		/**
+		 * Get current value for SysTick and calculate how
+		 * much time has passed since last measurement.
+		 */
 		systick_diff = cycle_count + elapsed() - cycle_pre_idle;
-
-		/* Calculate has much time has pasted since last measurement for both timers */
-		/* Check IDLE timer overflow */
-		if (idle_timer_pre_idle > idle_timer_post) {
-			idle_timer_diff =
-				(counter_get_top_value(idle_timer) - idle_timer_pre_idle) +
-				idle_timer_post + 1;
-
-		} else {
-			idle_timer_diff = idle_timer_post - idle_timer_pre_idle;
-		}
-		idle_timer_us = counter_ticks_to_us(idle_timer, idle_timer_diff);
 		systick_us =
 			((uint64_t)systick_diff * USEC_PER_SEC) / sys_clock_hw_cycles_per_sec();
+#else /* CONFIG_CORTEX_M_SYSTICK_RESET_BY_LPM */
+		/* SysTick was placed under reset so it didn't tick */
+		systick_diff = systick_us = 0;
+#endif /* !CONFIG_CORTEX_M_SYSTICK_RESET_BY_LPM */
+
+		/**
+		 * Query platform-specific code for elapsed time according to LPTIM.
+		 */
+		idle_timer_us = z_cms_lptim_hook_on_lpm_exit();
 
 		/* Calculate difference in measurements to get how much time
 		 * the SysTick missed in idle state.
@@ -423,11 +500,11 @@ void sys_clock_idle_exit(void)
 		/* We've alredy performed all needed operations */
 		timeout_idle = false;
 	}
-#endif /* CONFIG_CORTEX_M_SYSTICK_IDLE_TIMER */
+#endif /* !CONFIG_CORTEX_M_SYSTICK_LPM_TIMER_NONE */
 
-	if (last_load == TIMER_STOPPED) {
-		/* We really don’t know here how much time has passed,
-		 * so let’s restart the timer from scratch.
+	if (last_load == TIMER_STOPPED || IS_ENABLED(CONFIG_CORTEX_M_SYSTICK_RESET_BY_LPM)) {
+		/* SysTick was stopped or placed under reset.
+		 * Restart the timer from scratch.
 		 */
 		K_SPINLOCK(&lock) {
 			last_load = CYC_PER_TICK;
diff --git a/drivers/timer/cortex_m_systick.h b/drivers/timer/cortex_m_systick.h
new file mode 100644
index 00000000000..e8727666467
--- /dev/null
+++ b/drivers/timer/cortex_m_systick.h
@@ -0,0 +1,68 @@
+/**
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_TIMER_CORTEX_M_SYSTICK_H_
+#define ZEPHYR_INCLUDE_DRIVERS_TIMER_CORTEX_M_SYSTICK_H_
+
+#include <zephyr/types.h>
+
+/**
+ * Hooks/callbacks definitions for interaction between the Cortex-M
+ * SysTick driver and a platform-specific low-power timer driver.
+ *
+ * These functions are invoked by the Cortex-M SysTick driver to
+ * configure a platform-specific timer that remains active when
+ * the system enters a low-power mode.
+ *
+ * In the rest of this file, the "platform-specific low-power mode timer"
+ * is named "LPTIM", and the platform-specific driver that configures the
+ * LPTIM (and implements these hooks/callbacks) is named "LPTIM driver".
+ *
+ * The following behavior is observed when this option is enabled:
+ *
+ * |------(1)---(2)--------------------(3)-------(4)--------------> Time
+ *
+ * (1) cmsd_hook_on_lpm_entry() is invoked
+ * (2) The system enters in low-power mode
+ * (3) The system exits low-power mode (due to timeout or HW event)
+ * (4) cmsd_hook_lpm_time_elapsed() is called
+ *
+ * The return value of cmsd_hook_lpm_time_elapsed() should be as close
+ * as possible to the real time interval between events (1) and (4).
+ *
+ * These hooks should be implemented by the application if and only if
+ * CONFIG_CORTEX_M_SYSTICK_LPM_TIMER_HOOKS is enabled.
+ *
+ * NOTE: the hooks are not invoked when the system enters in low-power
+ * mode for an indefinite amount of time (requires CONFIG_TICKLESS_KERNEL
+ * and no thread PENDING with timeout).
+ */
+
+/**
+ * @brief Hook invoked when the system is about to enter low-power mode
+ *
+ * @param max_lpm_time_us Maximal time allowed in low-power mode (µs)
+ *
+ * The LPTIM driver should configure the LPTIM to wake up the system
+ * after at most @a{max_lpm_time_us} elapses; depending on hardware
+ * capabilities, the LPTIM may have to be configured to wake up the
+ * system earlier than requested (but no later!).
+ *
+ * Note that this hook is not called if the system enters low-power
+ * mode for an indefinite amount of time (i.e., when no threads are
+ * runnable or waiting with timeout).
+ */
+void z_cms_lptim_hook_on_lpm_entry(uint64_t max_lpm_time_us);
+
+/**
+ * @brief Callback invoked after system exits low-power mode
+ *
+ * This function should return the time elapsed, in microseconds,
+ * since entry in low-power mode occurred (i.e., since the call
+ * to @ref{cmsd_hook_on_lpm_entry}).
+ */
+uint64_t z_cms_lptim_hook_on_lpm_exit(void);
+#endif /* ZEPHYR_INCLUDE_DRIVERS_TIMER_CORTEX_M_SYSTICK_H_ */
diff --git a/drivers/timer/esp32_sys_timer.c b/drivers/timer/esp32_sys_timer.c
index bb36445d113..46bc17877e7 100644
--- a/drivers/timer/esp32_sys_timer.c
+++ b/drivers/timer/esp32_sys_timer.c
@@ -1,8 +1,9 @@
 /*
- * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2021-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+
 #include <soc/soc_caps.h>
 #include <soc/soc.h>
 
@@ -12,7 +13,7 @@
 #include <rom/ets_sys.h>
 #include <esp_attr.h>
 
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
+#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
 #include <zephyr/drivers/timer/system_timer.h>
 #include <zephyr/sys_clock.h>
 #include <soc.h>
@@ -56,7 +57,7 @@ static uint64_t get_systimer_alarm(void)
 	return systimer_hal_get_counter_value(&systimer_hal, SYSTIMER_COUNTER_OS_TICK);
 }
 
-static void sys_timer_isr(const void *arg)
+static void sys_timer_isr(void *arg)
 {
 	ARG_UNUSED(arg);
 	systimer_ll_clear_alarm_int(systimer_hal.dev, SYSTIMER_ALARM_OS_TICK_CORE0);
@@ -167,5 +168,5 @@ static int sys_clock_driver_init(void)
 	return 0;
 }
 
-SYS_INIT(sys_clock_driver_init, PRE_KERNEL_1,
+SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
 	 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
diff --git a/drivers/timer/gecko_burtc_timer.c b/drivers/timer/gecko_burtc_timer.c
index 3e0805f56ac..835fc2ded6f 100644
--- a/drivers/timer/gecko_burtc_timer.c
+++ b/drivers/timer/gecko_burtc_timer.c
@@ -54,7 +54,7 @@ const int32_t z_sys_timer_irq_for_test = TIMER_IRQ;
 /* With CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME, that's where we
  * should write hw_cycles timer clock frequency upon init
  */
-extern int z_clock_hw_cycles_per_sec;
+extern unsigned int z_clock_hw_cycles_per_sec;
 
 /* Number of hw_cycles clocks per 1 kernel tick */
 static uint32_t g_cyc_per_tick;
diff --git a/drivers/timer/hpet.c b/drivers/timer/hpet.c
index 8a7134a762e..c9c58f6e2ce 100644
--- a/drivers/timer/hpet.c
+++ b/drivers/timer/hpet.c
@@ -415,7 +415,7 @@ void sys_clock_idle_exit(void)
 __boot_func
 static int sys_clock_driver_init(void)
 {
-	extern int z_clock_hw_cycles_per_sec;
+	extern unsigned int z_clock_hw_cycles_per_sec;
 	uint32_t hz, reg;
 
 	ARG_UNUSED(hz);
diff --git a/drivers/timer/ite_it51xxx_timer.c b/drivers/timer/ite_it51xxx_timer.c
new file mode 100644
index 00000000000..7791d57e368
--- /dev/null
+++ b/drivers/timer/ite_it51xxx_timer.c
@@ -0,0 +1,421 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ite_it51xxx_timer
+
+#include <soc.h>
+#include <zephyr/drivers/timer/system_timer.h>
+#include <zephyr/irq.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys_clock.h>
+
+LOG_MODULE_REGISTER(timer, LOG_LEVEL_ERR);
+
+BUILD_ASSERT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 32768,
+	     "Hardware timer frequency is fixed at 32768Hz");
+
+/* it51xxx timer registers definition */
+static mm_reg_t timer_base = DT_REG_ADDR(DT_NODELABEL(timer));
+
+/* 0x10, 0x18, 0x20, 0x28, 0x30, 0x38: External Timer 3-8 Control Register (n=0 to 5) */
+#define TIMER_ETNCTRL(n)   (0x10 + ((n) * 8))
+#define TIMER_ETCOMB       BIT(3)
+#define TIMER_ETNRST       BIT(1)
+#define TIMER_ETNEN        BIT(0)
+/* 0x11, 0x19, 0x21, 0x29, 0x31, 0x39: External Timer 3-8 Prescaler Register (n=0 to 5) */
+#define TIMER_ETNPSR(n)    (0x11 + ((n) * 8))
+/* 0x14, 0x1c, 0x24, 0x2c, 0x34, 0x3c: External Timer 3-8 Counter Register (n=0 to 5) */
+#define TIMER_ETNCNTLLR(n) (0x14 + ((n) * 8))
+/* 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c: External Timer 3-8 Counter Observation Register (n=0 to 5) */
+#define TIMER_ETNCNTOLR(n) (0x48 + ((n) * 4))
+
+/*
+ * 24-bit timers: external timer 3, 5, and 7
+ * 32-bit timers: external timer 4, 6, and 8
+ */
+enum ext_timer_idx {
+	EXT_TIMER_3 = 0, /* Event timer */
+	EXT_TIMER_4,     /* Free run timer */
+	EXT_TIMER_5,     /* Busy wait low timer */
+	EXT_TIMER_6,     /* Busy wait high timer */
+	EXT_TIMER_7,
+	EXT_TIMER_8,
+};
+
+enum ext_clk_src_sel {
+	EXT_PSR_32P768K = 0,
+	EXT_PSR_1P024K,
+	EXT_PSR_32,
+	EXT_PSR_EC_CLK,
+};
+
+enum ext_timer_raw_cnt {
+	EXT_NOT_RAW_CNT = 0,
+	EXT_RAW_CNT,
+};
+
+enum ext_timer_int {
+	EXT_WITHOUT_TIMER_INT = 0,
+	EXT_WITH_TIMER_INT,
+};
+
+enum ext_timer_start {
+	EXT_NOT_START_TIMER = 0,
+	EXT_START_TIMER,
+};
+
+/* Event timer configurations */
+#define EVENT_TIMER               EXT_TIMER_3
+#define EVENT_TIMER_IRQ           DT_IRQ_BY_IDX(DT_NODELABEL(timer), 0, irq)
+#define EVENT_TIMER_FLAG          DT_IRQ_BY_IDX(DT_NODELABEL(timer), 0, flags)
+/* Event timer max count is 512 sec (base on clock source 32768Hz) */
+#define EVENT_TIMER_MAX_CNT       0x00FFFFFFUL
+/* Free run timer configurations */
+#define FREE_RUN_TIMER            EXT_TIMER_4
+#define FREE_RUN_TIMER_IRQ        DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, irq)
+#define FREE_RUN_TIMER_FLAG       DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, flags)
+/* Free run timer max count is 36.4 hr (base on clock source 32768Hz) */
+#define FREE_RUN_TIMER_MAX_CNT    0xFFFFFFFFUL
+/* Busy wait low timer configurations */
+#define BUSY_WAIT_L_TIMER         EXT_TIMER_5
+#define BUSY_WAIT_L_TIMER_IRQ     DT_INST_IRQ_BY_IDX(0, 2, irq)
+#define BUSY_WAIT_L_TIMER_FLAG    DT_INST_IRQ_BY_IDX(0, 2, flags)
+/* Busy wait high timer configurations */
+#define BUSY_WAIT_H_TIMER         EXT_TIMER_6
+#define BUSY_WAIT_H_TIMER_IRQ     DT_INST_IRQ_BY_IDX(0, 3, irq)
+#define BUSY_WAIT_H_TIMER_FLAG    DT_INST_IRQ_BY_IDX(0, 3, flags)
+/* Busy wait high timer max count is 7.78min (base on EC clock source 9.2MHz) */
+#define BUSY_WAIT_TIMER_H_MAX_CNT 0xFFFFFFFFUL
+
+#define MS_TO_COUNT(hz, ms) ((hz) * (ms) / 1000)
+#define ETPSR_9200K         KHZ(9200)
+#define ETPSR_32768         32768
+#define ETPSR_1024          1024
+#define ETPSR_32            32
+#define EC_CLOCK            ETPSR_9200K
+#define COUNT_1US           (EC_CLOCK / USEC_PER_SEC)
+
+/*
+ * One system (kernel) tick is as how much HW timer counts
+ *
+ * NOTE: Event and free run timer individually select the same clock source frequency, so they can
+ *       use the same HW_CNT_PER_SYS_TICK to transform unit between HW count and system tick. If
+ *       clock source frequency is different, then we should define another to transform.
+ */
+#define HW_CNT_PER_SYS_TICK (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
+
+/* Event timer max count is as how much system (kernel) tick */
+#define EVEN_TIMER_MAX_CNT_SYS_TICK (EVENT_TIMER_MAX_CNT / HW_CNT_PER_SYS_TICK)
+
+static struct k_spinlock lock;
+/* Last HW count that we called sys_clock_announce() */
+static volatile uint32_t last_announced_hw_cnt;
+/* Last system (kernel) elapse and ticks */
+static volatile uint32_t last_elapsed;
+static volatile uint32_t last_ticks;
+
+#if defined(CONFIG_TEST)
+const int32_t z_sys_timer_irq_for_test = DT_IRQ_BY_IDX(DT_NODELABEL(timer), 4, irq);
+#endif
+
+static uint32_t read_timer_obser(enum ext_timer_idx timer_idx)
+{
+	uint32_t obser;
+	__unused uint8_t etnpsr;
+
+	/* Workaround for observation register latch issue */
+	obser = sys_read32(timer_base + TIMER_ETNCNTOLR(timer_idx));
+	etnpsr = sys_read8(timer_base + TIMER_ETNPSR(timer_idx));
+	obser = sys_read32(timer_base + TIMER_ETNCNTOLR(timer_idx));
+
+	return obser;
+}
+
+static void ext_timer_disable(enum ext_timer_idx timer_idx)
+{
+	uint8_t etnctrl;
+
+	/* Disable event timer */
+	etnctrl = sys_read8(timer_base + TIMER_ETNCTRL(timer_idx));
+	sys_write8(etnctrl & ~TIMER_ETNEN, timer_base + TIMER_ETNCTRL(timer_idx));
+}
+
+static void ext_timer_enable(enum ext_timer_idx timer_idx)
+{
+	uint8_t etnctrl;
+
+	/* Enable and re-start event timer */
+	etnctrl = sys_read8(timer_base + TIMER_ETNCTRL(timer_idx));
+	sys_write8(etnctrl | TIMER_ETNRST | TIMER_ETNEN, timer_base + TIMER_ETNCTRL(timer_idx));
+}
+
+static void evt_timer_isr(const void *unused)
+{
+	ARG_UNUSED(unused);
+
+	ext_timer_disable(EVENT_TIMER);
+	/* W/C event timer interrupt status */
+	ite_intc_isr_clear(EVENT_TIMER_IRQ);
+
+	if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
+		/*
+		 * Get free run observer count from last time announced and transform unit to
+		 * system tick
+		 */
+		uint32_t dticks = (~(read_timer_obser(FREE_RUN_TIMER))-last_announced_hw_cnt) /
+				  HW_CNT_PER_SYS_TICK;
+		last_announced_hw_cnt += (dticks * HW_CNT_PER_SYS_TICK);
+		last_ticks += dticks;
+		last_elapsed = 0;
+
+		sys_clock_announce(dticks);
+	} else {
+		ext_timer_enable(EVENT_TIMER);
+		/* Informs kernel that one system tick has elapsed */
+		sys_clock_announce(MS_TO_COUNT(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, 1));
+	}
+}
+
+static void free_run_timer_overflow_isr(const void *unused)
+{
+	ARG_UNUSED(unused);
+
+	/* Read to clear terminal count flag */
+	__unused uint8_t rc_tc = sys_read8(timer_base + TIMER_ETNCTRL(FREE_RUN_TIMER));
+	/* TODO: to increment 32-bit "top half" here for software 64-bit timer emulation. */
+}
+
+void sys_clock_set_timeout(int32_t ticks, bool idle)
+{
+	ARG_UNUSED(idle);
+
+	uint32_t hw_cnt, next_cycs, now, dcycles;
+
+	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
+		/* Always return for non-tickless kernel system */
+		return;
+	}
+
+	/* Critical section */
+	k_spinlock_key_t key = k_spin_lock(&lock);
+
+	/* Disable event timer */
+	ext_timer_disable(EVENT_TIMER);
+
+	if (ticks == K_TICKS_FOREVER) {
+		/*
+		 * If kernel doesn't have a timeout:
+		 * 1.CONFIG_SYSTEM_CLOCK_SLOPPY_IDLE = y (no future timer interrupts are expected),
+		 *   kernel pass K_TICKS_FOREVER (0xFFFF FFFF FFFF FFFF), we handle this case in
+		 *   here.
+		 * 2.CONFIG_SYSTEM_CLOCK_SLOPPY_IDLE = n (schedule timeout as far into the future
+		 *   as possible), kernel pass INT_MAX (0x7FFF FFFF), we handle it in later else {}.
+		 */
+		k_spin_unlock(&lock, key);
+		return;
+	}
+	/*
+	 * If ticks <= 1 means the kernel wants the tick announced as soon as possible,
+	 * ideally no more than one system tick in the future. So set event timer count
+	 * to 1 HW tick.
+	 */
+	ticks = CLAMP(ticks, 1, (int32_t)EVEN_TIMER_MAX_CNT_SYS_TICK);
+	next_cycs = (last_ticks + last_elapsed + ticks) * HW_CNT_PER_SYS_TICK;
+	now = ~read_timer_obser(FREE_RUN_TIMER);
+	if (unlikely(next_cycs <= now)) {
+		hw_cnt = 1;
+	} else {
+		dcycles = next_cycs - now;
+		hw_cnt = MIN(dcycles, EVENT_TIMER_MAX_CNT);
+	}
+
+	/* Set event timer 24-bit count */
+	sys_write32(hw_cnt, timer_base + TIMER_ETNCNTLLR(EVENT_TIMER));
+
+	/* W/C event timer interrupt status */
+	ite_intc_isr_clear(EVENT_TIMER_IRQ);
+
+	/* Enable event timer */
+	ext_timer_enable(EVENT_TIMER);
+
+	k_spin_unlock(&lock, key);
+}
+
+uint32_t sys_clock_elapsed(void)
+{
+	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
+		/* Always return 0 for non-tickless kernel system */
+		return 0;
+	}
+
+	/* Critical section */
+	k_spinlock_key_t key = k_spin_lock(&lock);
+
+	/* Get free run observer count from last time announced and transform unit to system tick */
+	uint32_t dticks =
+		(~(read_timer_obser(FREE_RUN_TIMER))-last_announced_hw_cnt) / HW_CNT_PER_SYS_TICK;
+
+	last_elapsed = dticks;
+
+	k_spin_unlock(&lock, key);
+
+	return dticks;
+}
+
+uint32_t sys_clock_cycle_get_32(void)
+{
+	uint32_t dticks = ~read_timer_obser(FREE_RUN_TIMER);
+
+	return dticks;
+}
+
+static int timer_init(enum ext_timer_idx ext_timer, enum ext_clk_src_sel clock_source_sel,
+		      enum ext_timer_raw_cnt raw, uint32_t ms, uint32_t irq_num, uint32_t irq_flag,
+		      enum ext_timer_int with_int, enum ext_timer_start start)
+{
+	uint32_t hw_cnt;
+
+	if (raw == EXT_RAW_CNT) {
+		hw_cnt = ms;
+	} else {
+		if (clock_source_sel == EXT_PSR_32P768K) {
+			hw_cnt = MS_TO_COUNT(ETPSR_32768, ms);
+		} else if (clock_source_sel == EXT_PSR_1P024K) {
+			hw_cnt = MS_TO_COUNT(ETPSR_1024, ms);
+		} else if (clock_source_sel == EXT_PSR_32) {
+			hw_cnt = MS_TO_COUNT(ETPSR_32, ms);
+		} else if (clock_source_sel == EXT_PSR_EC_CLK) {
+			hw_cnt = MS_TO_COUNT(ETPSR_9200K, ms);
+		} else {
+			LOG_ERR("Timer %d clock source error !", ext_timer);
+			return -EINVAL;
+		}
+	}
+
+	if (hw_cnt == 0) {
+		LOG_ERR("Timer %d count shouldn't be 0 !", ext_timer);
+		return -EINVAL;
+	}
+
+	/* First time enable */
+	ext_timer_enable(ext_timer);
+	ext_timer_disable(ext_timer);
+
+	/* Set rising edge triggered of external timer x */
+	ite_intc_irq_polarity_set(irq_num, irq_flag);
+
+	/* Clear interrupt status of external timer x */
+	ite_intc_isr_clear(irq_num);
+
+	/* Set clock source of external timer */
+	sys_write8(clock_source_sel, timer_base + TIMER_ETNPSR(ext_timer));
+
+	/* Set count of external timer */
+	sys_write32(hw_cnt, timer_base + TIMER_ETNCNTLLR(ext_timer));
+
+	ext_timer_disable(ext_timer);
+	if (start == EXT_START_TIMER) {
+		ext_timer_enable(ext_timer);
+	}
+
+	if (with_int == EXT_WITH_TIMER_INT) {
+		irq_enable(irq_num);
+	} else {
+		irq_disable(irq_num);
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT
+void arch_busy_wait(uint32_t usec_to_wait)
+{
+	uint32_t start = read_timer_obser(BUSY_WAIT_H_TIMER);
+
+	if (!usec_to_wait) {
+		return;
+	}
+
+	/* Decrease 1us here to calibrate our access registers latency */
+	usec_to_wait--;
+
+	for (;;) {
+		if ((read_timer_obser(BUSY_WAIT_H_TIMER) - start) >= usec_to_wait) {
+			break;
+		}
+	}
+}
+#endif
+
+static int sys_clock_driver_init(void)
+{
+	int ret;
+
+	/* Enable 32-bit free run timer overflow interrupt */
+	IRQ_CONNECT(FREE_RUN_TIMER_IRQ, 0, free_run_timer_overflow_isr, NULL, FREE_RUN_TIMER_FLAG);
+	/* Set 32-bit timer4 for free run*/
+	ret = timer_init(FREE_RUN_TIMER, EXT_PSR_32P768K, EXT_RAW_CNT, FREE_RUN_TIMER_MAX_CNT,
+			 FREE_RUN_TIMER_IRQ, FREE_RUN_TIMER_FLAG, EXT_WITH_TIMER_INT,
+			 EXT_START_TIMER);
+	if (ret < 0) {
+		LOG_ERR("Init free run timer failed");
+		return ret;
+	}
+
+	/* Set 24-bit timer3 for timeout event */
+	IRQ_CONNECT(EVENT_TIMER_IRQ, 0, evt_timer_isr, NULL, EVENT_TIMER_FLAG);
+	if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
+		ret = timer_init(EVENT_TIMER, EXT_PSR_32P768K, EXT_RAW_CNT, EVENT_TIMER_MAX_CNT,
+				 EVENT_TIMER_IRQ, EVENT_TIMER_FLAG, EXT_WITH_TIMER_INT,
+				 EXT_NOT_START_TIMER);
+	} else {
+		/* Start a event timer in one system tick */
+		ret = timer_init(EVENT_TIMER, EXT_PSR_32P768K, EXT_NOT_RAW_CNT,
+				 MAX((1 * HW_CNT_PER_SYS_TICK), 1), EVENT_TIMER_IRQ,
+				 EVENT_TIMER_FLAG, EXT_WITH_TIMER_INT, EXT_START_TIMER);
+	}
+	if (ret < 0) {
+		LOG_ERR("Init event timer failed");
+		return ret;
+	}
+
+	if (IS_ENABLED(CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT)) {
+		/* Set timer5 and timer6 combinational mode for busy wait */
+		sys_write8(TIMER_ETCOMB, timer_base + TIMER_ETNCTRL(BUSY_WAIT_L_TIMER));
+
+		/*
+		 * Set 32-bit timer6 to count-- every 1us
+		 * NOTE: When the combinational mode. the counter observation value of timer 6 will
+		 *       in incremental order.
+		 */
+		ret = timer_init(BUSY_WAIT_H_TIMER, EXT_PSR_EC_CLK, EXT_RAW_CNT,
+				 BUSY_WAIT_TIMER_H_MAX_CNT, BUSY_WAIT_H_TIMER_IRQ,
+				 BUSY_WAIT_H_TIMER_FLAG, EXT_WITHOUT_TIMER_INT, EXT_START_TIMER);
+		if (ret < 0) {
+			LOG_ERR("Init busy wait high timer failed");
+			return ret;
+		}
+
+		/*
+		 * Set 24-bit timer5 to overflow every 1us
+		 * NOTE: When the timer5 count down to overflow in combinational mode, timer6
+		 *       counter will automatically decrease one count and timer5 will
+		 *       automatically re-start counting down from COUNT_1US. Timer5 clock
+		 *       source is EC_CLOCK, so the time period from COUNT_1US to overflow is
+		 *       (1 / EC_CLOCK) * (EC_CLOCK / USEC_PER_SEC) = 1us.
+		 */
+		ret = timer_init(BUSY_WAIT_L_TIMER, EXT_PSR_EC_CLK, EXT_RAW_CNT, COUNT_1US,
+				 BUSY_WAIT_L_TIMER_IRQ, BUSY_WAIT_L_TIMER_FLAG,
+				 EXT_WITHOUT_TIMER_INT, EXT_START_TIMER);
+		if (ret < 0) {
+			LOG_ERR("Init busy wait low timer failed");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
diff --git a/drivers/timer/mcux_lptmr_timer.c b/drivers/timer/mcux_lptmr_timer.c
index 930058f4ea4..f83e4c39e26 100644
--- a/drivers/timer/mcux_lptmr_timer.c
+++ b/drivers/timer/mcux_lptmr_timer.c
@@ -4,15 +4,11 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/devicetree.h>
-#if DT_HAS_COMPAT_STATUS_OKAY(nxp_kinetis_lptmr)
-#define DT_DRV_COMPAT nxp_kinetis_lptmr
-#else
 #define DT_DRV_COMPAT nxp_lptmr
-#endif
 
 #include <zephyr/init.h>
 #include <zephyr/drivers/timer/system_timer.h>
+#include <zephyr/devicetree.h>
 #include <zephyr/kernel.h>
 #include <zephyr/sys/time_units.h>
 #include <fsl_lptmr.h>
diff --git a/drivers/timer/mcux_os_timer.c b/drivers/timer/mcux_os_timer.c
index c6eb776e43a..1402f696c55 100644
--- a/drivers/timer/mcux_os_timer.c
+++ b/drivers/timer/mcux_os_timer.c
@@ -22,6 +22,8 @@
 
 #define CYC_PER_TICK ((uint32_t)((uint64_t)sys_clock_hw_cycles_per_sec()	\
 			      / (uint64_t)CONFIG_SYS_CLOCK_TICKS_PER_SEC))
+#define CYC_PER_US ((uint32_t)((uint64_t)sys_clock_hw_cycles_per_sec()	\
+			      / (uint64_t)USEC_PER_SEC))
 #define MAX_CYC INT_MAX
 #define MAX_TICKS ((MAX_CYC - CYC_PER_TICK) / CYC_PER_TICK)
 #define MIN_DELAY 1000
@@ -37,7 +39,12 @@ static OSTIMER_Type *base;
  */
 static uint64_t cyc_sys_compensated;
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(standby)) && CONFIG_PM
+/* This is the counter device used when OS timer is not available in
+ * standby mode.
+ */
 static const struct device *counter_dev;
+/* Indicates if the counter is running. */
+bool counter_running;
 #endif
 
 static uint64_t mcux_lpc_ostick_get_compensated_timer_value(void)
@@ -86,8 +93,7 @@ static uint32_t mcux_lpc_ostick_set_counter_timeout(int32_t curr_timeout)
 		uint32_t timeout;
 		int32_t ticks;
 		struct counter_top_cfg top_cfg = { 0 };
-
-		timeout = k_ticks_to_us_ceil32(curr_timeout);
+		timeout = k_ticks_to_us_near32(curr_timeout);
 
 		ticks = counter_us_to_ticks(counter_dev, timeout);
 		ticks = CLAMP(ticks, 1, counter_get_max_top_value(counter_dev));
@@ -111,17 +117,18 @@ static uint32_t mcux_lpc_ostick_set_counter_timeout(int32_t curr_timeout)
 			}
 		}
 
+		/* Counter is set to wakeup the system after the requested time */
+		if (counter_start(counter_dev) != 0) {
+			ret = 1;
+			goto done;
+		}
+		counter_running = true;
 #if CONFIG_MCUX_OS_TIMER_PM_POWERED_OFF
 		/* Capture the current timer value for cases where it loses its state
 		 * in low power modes.
 		 */
 		cyc_sys_compensated += OSTIMER_GetCurrentTimerValue(base);
 #endif
-
-		/* Counter is set to wakeup the system after the requested time */
-		if (counter_start(counter_dev) != 0) {
-			ret = 1;
-		}
 	} else {
 		ret = 1;
 	}
@@ -137,34 +144,37 @@ static uint32_t mcux_lpc_ostick_set_counter_timeout(int32_t curr_timeout)
  */
 static uint32_t mcux_lpc_ostick_compensate_system_timer(void)
 {
-	uint32_t ret = 0;
-
-	if (counter_dev) {
-		uint32_t slept_time_ticks;
-		uint32_t slept_time_us;
+	uint32_t slept_time_ticks;
+	uint32_t slept_time_us;
 
-		counter_stop(counter_dev);
+	if (!counter_dev) {
+		return 1;
+	}
 
-		counter_get_value(counter_dev, &slept_time_ticks);
+	if (!counter_running) {
+		return 0;
+	}
 
-		if (!(counter_is_counting_up(counter_dev))) {
-			slept_time_ticks = counter_get_top_value(counter_dev) - slept_time_ticks;
-		}
-		slept_time_us = counter_ticks_to_us(counter_dev, slept_time_ticks);
-		cyc_sys_compensated += (k_us_to_ticks_floor32(slept_time_us) * CYC_PER_TICK);
+	counter_stop(counter_dev);
+	counter_running = false;
+	counter_get_value(counter_dev, &slept_time_ticks);
 
+	if (!(counter_is_counting_up(counter_dev))) {
+		slept_time_ticks = counter_get_top_value(counter_dev) -
+				   slept_time_ticks;
+	}
+	slept_time_us = counter_ticks_to_us(counter_dev, slept_time_ticks);
+	cyc_sys_compensated += CYC_PER_US * slept_time_us;
 #if CONFIG_MCUX_OS_TIMER_PM_POWERED_OFF
-		/* Reactivate os_timer for cases where it loses its state */
-		OSTIMER_Init(base);
+	/* Reset the OS Timer to a known state */
+	RESET_PeripheralReset(kOSEVENT_TIMER_RST_SHIFT_RSTn);
+	/* Reactivate os_timer for cases where it loses its state */
+	OSTIMER_Init(base);
 #endif
+	/* Announce the time slept to the kernel*/
+	mcux_lpc_ostick_isr(NULL);
 
-		/* Announce the time slept to the kernel*/
-		mcux_lpc_ostick_isr(NULL);
-	} else {
-		ret = 1;
-	}
-
-	return ret;
+	return 0;
 }
 
 #endif
diff --git a/drivers/timer/native_posix_timer.c b/drivers/timer/native_posix_timer.c
deleted file mode 100644
index db2706a2306..00000000000
--- a/drivers/timer/native_posix_timer.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright (c) 2017-2019 Oticon A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * Driver for the timer model of the POSIX native_sim/posix board
- * It provides the interfaces required by the kernel and the sanity testcases
- * It also provides a custom k_busy_wait() which can be used with the
- * POSIX arch and InfClock SOC
- */
-#include <zephyr/types.h>
-#include <zephyr/irq.h>
-#include <zephyr/init.h>
-#include <zephyr/drivers/timer/system_timer.h>
-#include <zephyr/sys_clock.h>
-#include "timer_model.h"
-#include "soc.h"
-#include <zephyr/arch/posix/posix_trace.h>
-
-static uint64_t tick_period; /* System tick period in microseconds */
-/* Time (microseconds since boot) of the last timer tick interrupt */
-static uint64_t last_tick_time;
-
-/**
- * Return the current HW cycle counter
- * (number of microseconds since boot in 32bits)
- */
-uint32_t sys_clock_cycle_get_32(void)
-{
-	return hwm_get_time();
-}
-
-uint64_t sys_clock_cycle_get_64(void)
-{
-	return hwm_get_time();
-}
-
-/**
- * Interrupt handler for the timer interrupt
- * Announce to the kernel that a number of ticks have passed
- */
-static void np_timer_isr(const void *arg)
-{
-	ARG_UNUSED(arg);
-
-	uint64_t now = hwm_get_time();
-	int32_t elapsed_ticks = (now - last_tick_time)/tick_period;
-
-	last_tick_time += elapsed_ticks*tick_period;
-	sys_clock_announce(elapsed_ticks);
-}
-
-/**
- * This function exists only to enable tests to call into the timer ISR
- */
-void np_timer_isr_test_hook(const void *arg)
-{
-	np_timer_isr(NULL);
-}
-
-/**
- * @brief Set system clock timeout
- *
- * Informs the system clock driver that the next needed call to
- * sys_clock_announce() will not be until the specified number of ticks
- * from the current time have elapsed.
- *
- * See system_timer.h for more information
- *
- * @param ticks Timeout in tick units
- * @param idle Hint to the driver that the system is about to enter
- *        the idle state immediately after setting the timeout
- */
-void sys_clock_set_timeout(int32_t ticks, bool idle)
-{
-	ARG_UNUSED(idle);
-
-#if defined(CONFIG_TICKLESS_KERNEL)
-	uint64_t silent_ticks;
-
-	/* Note that we treat INT_MAX literally as anyhow the maximum amount of
-	 * ticks we can report with sys_clock_announce() is INT_MAX
-	 */
-	if (ticks == K_TICKS_FOREVER) {
-		silent_ticks = INT64_MAX;
-	} else if (ticks > 0) {
-		silent_ticks = ticks - 1;
-	} else {
-		silent_ticks = 0;
-	}
-	hwtimer_set_silent_ticks(silent_ticks);
-#endif
-}
-
-/**
- * @brief Ticks elapsed since last sys_clock_announce() call
- *
- * Queries the clock driver for the current time elapsed since the
- * last call to sys_clock_announce() was made.  The kernel will call
- * this with appropriate locking, the driver needs only provide an
- * instantaneous answer.
- */
-uint32_t sys_clock_elapsed(void)
-{
-	return (hwm_get_time() - last_tick_time)/tick_period;
-}
-
-/**
- * @brief Stop announcing sys ticks into the kernel
- *
- * Disable the system ticks generation
- */
-void sys_clock_disable(void)
-{
-	irq_disable(TIMER_TICK_IRQ);
-	hwtimer_set_silent_ticks(INT64_MAX);
-}
-
-/**
- * @brief Initialize system timer driver
- *
- * Enable the hw timer, setting its tick period, and setup its interrupt
- */
-static int sys_clock_driver_init(void)
-{
-
-	tick_period = 1000000ul / CONFIG_SYS_CLOCK_TICKS_PER_SEC;
-
-	last_tick_time = hwm_get_time();
-	hwtimer_enable(tick_period);
-
-	IRQ_CONNECT(TIMER_TICK_IRQ, 1, np_timer_isr, 0, 0);
-	irq_enable(TIMER_TICK_IRQ);
-
-	return 0;
-}
-
-SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
-	 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
diff --git a/drivers/timer/native_sim_timer.c b/drivers/timer/native_sim_timer.c
new file mode 100644
index 00000000000..458c81f7907
--- /dev/null
+++ b/drivers/timer/native_sim_timer.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2017-2019 Oticon A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * Driver for the native_sim board timer
+ * It provides the same API required by the kernel as any other timer driver
+ */
+#include <zephyr/types.h>
+#include <zephyr/irq.h>
+#include <zephyr/init.h>
+#include <zephyr/drivers/timer/system_timer.h>
+#include <zephyr/sys_clock.h>
+#include "nsi_hw_scheduler.h"
+#include "nsi_timer_model.h"
+#include "soc.h"
+
+static uint64_t tick_period; /* System tick period in microseconds */
+/* Time (microseconds since boot) of the last timer tick interrupt */
+static uint64_t last_tick_time;
+
+/**
+ * Return the current HW cycle counter
+ * (number of microseconds since boot in 32bits)
+ */
+uint32_t sys_clock_cycle_get_32(void)
+{
+	return nsi_hws_get_time();
+}
+
+uint64_t sys_clock_cycle_get_64(void)
+{
+	return nsi_hws_get_time();
+}
+
+/**
+ * Interrupt handler for the timer interrupt
+ * Announce to the kernel that a number of ticks have passed
+ */
+static void np_timer_isr(const void *arg)
+{
+	ARG_UNUSED(arg);
+
+	uint64_t now = nsi_hws_get_time();
+	int32_t elapsed_ticks = (now - last_tick_time)/tick_period;
+
+	last_tick_time += elapsed_ticks*tick_period;
+	sys_clock_announce(elapsed_ticks);
+}
+
+/**
+ * This function exists only to enable tests to call into the timer ISR
+ */
+void np_timer_isr_test_hook(const void *arg)
+{
+	np_timer_isr(NULL);
+}
+
+/**
+ * @brief Set system clock timeout
+ *
+ * Informs the system clock driver that the next needed call to
+ * sys_clock_announce() will not be until the specified number of ticks
+ * from the current time have elapsed.
+ *
+ * See system_timer.h for more information
+ *
+ * @param ticks Timeout in tick units
+ * @param idle Hint to the driver that the system is about to enter
+ *        the idle state immediately after setting the timeout
+ */
+void sys_clock_set_timeout(int32_t ticks, bool idle)
+{
+	ARG_UNUSED(idle);
+
+#if defined(CONFIG_TICKLESS_KERNEL)
+	uint64_t silent_ticks;
+
+	/* Note that we treat INT_MAX literally as anyhow the maximum amount of
+	 * ticks we can report with sys_clock_announce() is INT_MAX
+	 */
+	if (ticks == K_TICKS_FOREVER) {
+		silent_ticks = INT64_MAX;
+	} else if (ticks > 0) {
+		silent_ticks = ticks - 1;
+	} else {
+		silent_ticks = 0;
+	}
+	hwtimer_set_silent_ticks(silent_ticks);
+#endif
+}
+
+/**
+ * @brief Ticks elapsed since last sys_clock_announce() call
+ *
+ * Queries the clock driver for the current time elapsed since the
+ * last call to sys_clock_announce() was made.  The kernel will call
+ * this with appropriate locking, the driver needs only provide an
+ * instantaneous answer.
+ */
+uint32_t sys_clock_elapsed(void)
+{
+	return (nsi_hws_get_time() - last_tick_time)/tick_period;
+}
+
+/**
+ * @brief Stop announcing sys ticks into the kernel
+ *
+ * Disable the system ticks generation
+ */
+void sys_clock_disable(void)
+{
+	irq_disable(TIMER_TICK_IRQ);
+	hwtimer_set_silent_ticks(INT64_MAX);
+}
+
+/**
+ * @brief Initialize system timer driver
+ *
+ * Enable the hw timer, setting its tick period, and setup its interrupt
+ */
+static int sys_clock_driver_init(void)
+{
+
+	tick_period = 1000000ul / CONFIG_SYS_CLOCK_TICKS_PER_SEC;
+
+	last_tick_time = nsi_hws_get_time();
+	hwtimer_enable(tick_period);
+
+	IRQ_CONNECT(TIMER_TICK_IRQ, 1, np_timer_isr, 0, 0);
+	irq_enable(TIMER_TICK_IRQ);
+
+	return 0;
+}
+
+SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
+	 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
diff --git a/drivers/timer/nrf_grtc_timer.c b/drivers/timer/nrf_grtc_timer.c
index bec83e1a088..285e48a57fd 100644
--- a/drivers/timer/nrf_grtc_timer.c
+++ b/drivers/timer/nrf_grtc_timer.c
@@ -509,23 +509,23 @@ static int sys_clock_driver_init(void)
 	nrfy_grtc_clkout_set(NRF_GRTC, NRF_GRTC_CLKOUT_32K, true);
 #endif
 
-#if DT_NODE_HAS_PROP(GRTC_NODE, clkout_fast_frequency)
+#if DT_NODE_HAS_PROP(GRTC_NODE, clkout_fast_frequency_hz)
 #if !DT_NODE_HAS_PROP(HFCLK_NODE, clock_frequency)
 #error "hfclock reference required when fast clock output is enabled."
 #endif
 
-#if DT_PROP(GRTC_NODE, clkout_fast_frequency) > (DT_PROP(HFCLK_NODE, clock_frequency) / 2)
+#if DT_PROP(GRTC_NODE, clkout_fast_frequency_hz) > (DT_PROP(HFCLK_NODE, clock_frequency) / 2)
 #error "Invalid frequency value for fast clock output."
 #endif
 	uint32_t base_frequency = DT_PROP(HFCLK_NODE, clock_frequency);
-	uint32_t requested_frequency = DT_PROP(GRTC_NODE, clkout_fast_frequency);
+	uint32_t requested_frequency = DT_PROP(GRTC_NODE, clkout_fast_frequency_hz);
 	uint32_t grtc_div = base_frequency / (requested_frequency * 2);
 
 	nrfy_grtc_clkout_divider_set(NRF_GRTC, (uint8_t)grtc_div);
 	nrfy_grtc_clkout_set(NRF_GRTC, NRF_GRTC_CLKOUT_FAST, true);
 #endif
 
-#if DT_PROP(GRTC_NODE, clkout_32k) || DT_NODE_HAS_PROP(GRTC_NODE, clkout_fast_frequency)
+#if DT_PROP(GRTC_NODE, clkout_32k) || DT_NODE_HAS_PROP(GRTC_NODE, clkout_fast_frequency_hz)
 	PINCTRL_DT_DEFINE(GRTC_NODE);
 	const struct pinctrl_dev_config *pcfg = PINCTRL_DT_DEV_CONFIG_GET(GRTC_NODE);
 
diff --git a/drivers/timer/realtek_rts5912_rtmr.c b/drivers/timer/realtek_rts5912_rtmr.c
index 3476e730999..21e0b14ca5e 100644
--- a/drivers/timer/realtek_rts5912_rtmr.c
+++ b/drivers/timer/realtek_rts5912_rtmr.c
@@ -28,8 +28,7 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
 
 #define RTMR_REG ((RTOSTMR_Type *)DT_INST_REG_ADDR(0))
 
-#define SLWTMR_REG                                                                                 \
-	((RTOSTMR_Type *)(DT_REG_ADDR(DT_COMPAT_GET_ANY_STATUS_OKAY(realtek_rts5912_slwtimer))))
+#define SLWTMR_REG ((RTOSTMR_Type *)(DT_REG_ADDR(DT_NODELABEL(slwtmr0))))
 
 #define SSCON_REG ((SYSTEM_Type *)(DT_REG_ADDR(DT_NODELABEL(sccon))))
 
@@ -39,8 +38,9 @@ BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
 
 #define MAX_TICKS ((k_ticks_t)(RTMR_COUNTER_MAX / CYCLES_PER_TICK) - 1)
 
-#define RTMR_ADJUST_LIMIT  2
-#define RTMR_ADJUST_CYCLES 1
+/* Adjust cycle count programmed into timer for HW restart latency */
+#define RTMR_ADJUST_LIMIT  8
+#define RTMR_ADJUST_CYCLES 7
 
 static struct k_spinlock lock;
 static uint32_t accumulated_cycles;
@@ -134,7 +134,7 @@ void sys_clock_set_timeout(int32_t ticks, bool idle)
 
 	partial_cycles = CYCLES_PER_TICK - (accumulated_cycles % CYCLES_PER_TICK);
 	previous_cnt = full_cycles + partial_cycles;
-
+	/* adjust for up to one 32KHz cycle startup time */
 	temp = previous_cnt;
 	if (temp > RTMR_ADJUST_LIMIT) {
 		temp -= RTMR_ADJUST_CYCLES;
diff --git a/drivers/timer/renesas_ra_ulpt_timer.c b/drivers/timer/renesas_ra_ulpt_timer.c
new file mode 100644
index 00000000000..f491f7d5b47
--- /dev/null
+++ b/drivers/timer/renesas_ra_ulpt_timer.c
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/timer/system_timer.h>
+#include <zephyr/irq.h>
+#include <zephyr/spinlock.h>
+#include <zephyr/sys_clock.h>
+#include <soc.h>
+
+#define DT_DRV_COMPAT renesas_ra_ulpt_timer
+
+/* Ensure there are exactly two ULPT timer instances
+ * enabled in the device tree.
+ */
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 2,
+	     "Requires two instances of the ULPT timer to be enabled.");
+
+/* ULPT instance 0: Used to announce ticks to the kernel. */
+#define RA_ULPT_INST0_NODE    DT_INST_PARENT(0)
+#define RA_ULPT_INST0_REG     ((R_ULPT0_Type *)DT_REG_ADDR(RA_ULPT_INST0_NODE))
+#define RA_ULPT_INST0_IRQN    DT_IRQ_BY_NAME(RA_ULPT_INST0_NODE, ulpti, irq)
+#define RA_ULPT_INST0_IRQP    0U
+#define RA_ULPT_INST0_CHANNEL DT_PROP(RA_ULPT_INST0_NODE, channel)
+
+/* ULPT instance 1: Used for synchronization with hardware cycle clock. */
+#define RA_ULPT_INST1_NODE    DT_INST_PARENT(1)
+#define RA_ULPT_INST1_REG     ((R_ULPT0_Type *)DT_REG_ADDR(RA_ULPT_INST1_NODE))
+#define RA_ULPT_INST1_CHANNEL DT_PROP(RA_ULPT_INST1_NODE, channel)
+
+/* Constants for timer configuration and behavior. */
+#define RA_ULPT_RELOAD_DELAY 4U
+#define RA_ULPT_RELOAD_MIN   4U
+#define RA_ULPT_RELOAD_MAX   UINT32_MAX
+
+#define RA_ULPT_PRV_ULPTCR_STATUS_FLAGS 0xE0U
+#define RA_ULPT_PRV_ULPTCR_START_TIMER  0xE1U
+
+/* Macro to get ELC event for ULPT interrupt based on the channel. */
+#define ELC_EVENT_ULPT_INT(channel) CONCAT(ELC_EVENT_ULPT, channel, _INT)
+
+/* Calculated constants for timer operation. */
+#define CYCLE_PER_TICK ((sys_clock_hw_cycles_per_sec() / CONFIG_SYS_CLOCK_TICKS_PER_SEC))
+#define MAX_TICKS      ((k_ticks_t)(RA_ULPT_RELOAD_MAX / CYCLE_PER_TICK) - 1)
+
+/* Static variables for maintaining timer state. */
+static uint32_t cycle_announced;
+static struct k_spinlock lock;
+
+static void ra_ulpt_timer_isr(void)
+{
+	uint32_t cycles;
+	uint32_t dcycles;
+	uint32_t dticks;
+	IRQn_Type irq = R_FSP_CurrentIrqGet();
+
+	/* Clear pending IRQ to prevent re-triggering. */
+	R_BSP_IrqStatusClear(irq);
+
+	if (RA_ULPT_INST0_REG->ULPTCR_b.TUNDF) {
+		k_spinlock_key_t key = k_spin_lock(&lock);
+
+		if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
+			/* Calculate elapsed cycles and ticks. */
+			cycles = ~RA_ULPT_INST1_REG->ULPTCNT;
+			dcycles = cycles - cycle_announced;
+			dticks = dcycles / CYCLE_PER_TICK;
+			cycle_announced += dticks * CYCLE_PER_TICK;
+		} else {
+			/* In tickful mode, announce one tick at a time. */
+			dticks = 1;
+		}
+		/* Clear the underflow flag. */
+		RA_ULPT_INST0_REG->ULPTCR_b.TUNDF = 0;
+		k_spin_unlock(&lock, key);
+
+		/* Announce the elapsed ticks to the kernel. */
+		sys_clock_announce(dticks);
+	}
+}
+
+void sys_clock_set_timeout(int32_t ticks, bool idle)
+{
+	ARG_UNUSED(idle);
+
+	/* Timeout configuration is unsupported in tickful mode. */
+	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
+		return;
+	}
+
+	/* No timeout change for K_TICKS_FOREVER or INT32_MAX. */
+	if (ticks == K_TICKS_FOREVER || ticks == INT32_MAX) {
+		return;
+	}
+
+	/* Clamp the ticks value to a valid range. */
+	ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
+
+	/* Calculate the timer delay in cycles. */
+	uint32_t cycles = ~RA_ULPT_INST1_REG->ULPTCNT;
+	uint32_t unannounced = cycles - cycle_announced;
+	uint32_t delay = ticks * CYCLE_PER_TICK;
+
+	/* Adjust delay to align with tick boundaries. */
+	delay += unannounced;
+	delay = DIV_ROUND_UP(delay, CYCLE_PER_TICK) * CYCLE_PER_TICK;
+	delay -= unannounced;
+	delay = MAX(delay, RA_ULPT_RELOAD_MIN + RA_ULPT_RELOAD_DELAY);
+	delay -= RA_ULPT_RELOAD_DELAY;
+
+	/* Update the timer counter. */
+	RA_ULPT_INST0_REG->ULPTCNT = delay - 1U;
+}
+
+uint32_t sys_clock_elapsed(void)
+{
+	/* Elapsed time calculation is unsupported in tickful mode. */
+	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
+		return 0;
+	}
+
+	/* Calculate and return the number of elapsed cycles. */
+	uint32_t cycles = ~RA_ULPT_INST1_REG->ULPTCNT - cycle_announced;
+
+	return (cycles / CYCLE_PER_TICK);
+}
+
+uint32_t sys_clock_cycle_get_32(void)
+{
+	return ~RA_ULPT_INST1_REG->ULPTCNT;
+}
+
+static int sys_clock_driver_init(void)
+{
+	/* Power on ULPT modules. */
+	R_BSP_MODULE_START(FSP_IP_ULPT, RA_ULPT_INST0_CHANNEL);
+	R_BSP_MODULE_START(FSP_IP_ULPT, RA_ULPT_INST1_CHANNEL);
+
+	/* Stop timers and reset control registers. */
+	RA_ULPT_INST0_REG->ULPTCR = 0U;
+	RA_ULPT_INST1_REG->ULPTCR = 0U;
+
+	/* Wait for timers to stop. */
+	FSP_HARDWARE_REGISTER_WAIT(0U, RA_ULPT_INST0_REG->ULPTCR_b.TCSTF);
+	FSP_HARDWARE_REGISTER_WAIT(0U, RA_ULPT_INST1_REG->ULPTCR_b.TCSTF);
+
+	/* Clear configuration registers before setup. */
+	RA_ULPT_INST0_REG->ULPTMR2 = 0U;
+	RA_ULPT_INST1_REG->ULPTMR2 = 0U;
+
+	/* Configure timer instance 0. */
+	RA_ULPT_INST0_REG->ULPTMR1 = 0U;
+	RA_ULPT_INST0_REG->ULPTMR2 = 0U;
+	RA_ULPT_INST0_REG->ULPTMR3 = 0U;
+	RA_ULPT_INST0_REG->ULPTIOC = 0U;
+	RA_ULPT_INST0_REG->ULPTISR = 0U;
+	RA_ULPT_INST0_REG->ULPTCMSR = 0U;
+
+	/* Configure timer instance 1. */
+	RA_ULPT_INST1_REG->ULPTMR1 = 0U;
+	RA_ULPT_INST1_REG->ULPTMR2 = 0U;
+	RA_ULPT_INST1_REG->ULPTMR3 = 0U;
+	RA_ULPT_INST1_REG->ULPTIOC = 0U;
+	RA_ULPT_INST1_REG->ULPTISR = 0U;
+	RA_ULPT_INST1_REG->ULPTCMSR = 0U;
+
+	/* Initialize timer counters. */
+	RA_ULPT_INST0_REG->ULPTCNT = CYCLE_PER_TICK - 1U;
+	RA_ULPT_INST1_REG->ULPTCNT = RA_ULPT_RELOAD_MAX;
+
+	/* Set up interrupts for timer instance 0. */
+	R_ICU->IELSR[RA_ULPT_INST0_IRQN] = ELC_EVENT_ULPT_INT(RA_ULPT_INST0_CHANNEL);
+	IRQ_CONNECT(RA_ULPT_INST0_IRQN, RA_ULPT_INST0_IRQP, ra_ulpt_timer_isr, NULL, 0);
+	irq_enable(RA_ULPT_INST0_IRQN);
+
+	/* Start both timers. */
+	RA_ULPT_INST0_REG->ULPTCR = RA_ULPT_PRV_ULPTCR_START_TIMER;
+	RA_ULPT_INST1_REG->ULPTCR = RA_ULPT_PRV_ULPTCR_START_TIMER;
+
+	/* Wait for timers to start completely. */
+	FSP_HARDWARE_REGISTER_WAIT(RA_ULPT_INST0_REG->ULPTCR_b.TSTART,
+				   RA_ULPT_INST0_REG->ULPTCR_b.TCSTF);
+	FSP_HARDWARE_REGISTER_WAIT(RA_ULPT_INST1_REG->ULPTCR_b.TSTART,
+				   RA_ULPT_INST1_REG->ULPTCR_b.TCSTF);
+	cycle_announced = 0U;
+
+	return 0;
+}
+
+/* Initialize the system timer driver during pre-kernel stage 2. */
+SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
diff --git a/drivers/timer/renesas_rza2m_os_timer.c b/drivers/timer/renesas_rza2m_os_timer.c
new file mode 100644
index 00000000000..5109c3f38ee
--- /dev/null
+++ b/drivers/timer/renesas_rza2m_os_timer.c
@@ -0,0 +1,227 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/spinlock.h>
+#include <zephyr/drivers/interrupt_controller/gic.h>
+#include <zephyr/drivers/timer/system_timer.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/irq.h>
+#include <zephyr/sys_clock.h>
+
+#define DT_DRV_COMPAT renesas_rza2m_ostm
+
+DEVICE_MMIO_TOPLEVEL_STATIC(ostm_base, DT_DRV_INST(0));
+
+/* The interrupt numbers in the device tree are interrupt IDs and need to be converted to SPI
+ * interrupt numbers
+ */
+#define OSTM_IRQ_NUM (DT_INST_IRQN(0) - GIC_SPI_INT_BASE)
+
+#if defined(CONFIG_TEST)
+const int32_t z_sys_timer_irq_for_test = OSTM_IRQ_NUM;
+#endif
+
+#define cycle_diff_t   uint32_t
+#define CYCLE_DIFF_MAX (~(cycle_diff_t)0)
+
+#define OSTM_REG_ADDR(off) ((mm_reg_t)(DEVICE_MMIO_TOPLEVEL_GET(ostm_base) + (off)))
+
+#define OSTM_CMP_OFFSET 0x0 /* Compare register */
+#define OSTM_CNT_OFFSET 0x4 /* Counter register */
+
+#define OSTM_TE_OFFSET 0x10   /* Count enable status register */
+#define OSTM_TE_ENABLE BIT(0) /* Timer enabled */
+
+#define OSTM_TS_OFFSET 0x14   /* Count start trigger register */
+#define OSTM_TS_START  BIT(0) /* Trigger start of the timer */
+
+#define OSTM_TT_OFFSET 0x18   /* Count stop trigger register */
+#define OSTM_TT_STOP   BIT(0) /* Trigger stop of the timer */
+
+#define OSTM_CTL_OFFSET            0x20 /* Control register */
+/*
+ * Bit 0 of CTL controls enabling/disabling of OSTMnTINT interrupt requests when counting starts
+ *    0: Disables the interrupts when counting starts
+ *    1: Enables the interrupts when counting starts
+ */
+#define OSTM_CTL_TRIG_IRQ_ON_START 1
+/*
+ * Bit 1 of CTL specifies the operating mode for the counter
+ *    0: Interval timer mode
+ *    1: Free-running comparison mode
+ */
+#define OSTM_CTL_INTERVAL          0
+#define OSTM_CTL_FREERUN           2
+
+/*
+ * We have two constraints on the maximum number of cycles we can wait for.
+ *
+ * 1) sys_clock_announce() accepts at most INT32_MAX ticks.
+ *
+ * 2) The number of cycles between two reports must fit in a cycle_diff_t
+ *    variable before converting it to ticks.
+ *
+ * Then:
+ *
+ * 3) Pick the smallest between (1) and (2).
+ *
+ * 4) Take into account some room for the unavoidable IRQ servicing latency.
+ *    Let's use 3/4 of the max range.
+ *
+ * Finally let's add the LSB value to the result so to clear out a bunch of
+ * consecutive set bits coming from the original max values to produce a
+ * nicer literal for assembly generation.
+ */
+#define CYCLES_MAX_1 ((uint64_t)INT32_MAX * (uint64_t)CYC_PER_TICK)
+#define CYCLES_MAX_2 ((uint64_t)CYCLE_DIFF_MAX)
+#define CYCLES_MAX_3 MIN(CYCLES_MAX_1, CYCLES_MAX_2)
+#define CYCLES_MAX_4 (CYCLES_MAX_3 / 2 + CYCLES_MAX_3 / 4)
+#define CYCLES_MAX_5 (CYCLES_MAX_4 + LSB_GET(CYCLES_MAX_4))
+
+/* Precompute CYCLES_MAX and CYC_PER_TICK at driver init to avoid runtime double divisions */
+static uint64_t cycles_max;
+static uint32_t cyc_per_tick;
+#define CYCLES_MAX   cycles_max
+#define CYC_PER_TICK cyc_per_tick
+
+static struct k_spinlock lock;
+static uint64_t last_cycle;
+static uint64_t last_tick;
+static uint32_t last_elapsed;
+extern unsigned int z_clock_hw_cycles_per_sec;
+
+static void ostm_irq_handler(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	uint32_t delta_cycles = sys_clock_cycle_get_32() - last_cycle;
+	uint32_t delta_ticks = delta_cycles / CYC_PER_TICK;
+
+	last_cycle += (cycle_diff_t)delta_ticks * CYC_PER_TICK;
+	last_tick += delta_ticks;
+	last_elapsed = 0;
+
+	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
+		uint32_t next_cycle = last_cycle + CYC_PER_TICK;
+
+		sys_write32(next_cycle, OSTM_REG_ADDR(OSTM_CMP_OFFSET));
+	} else {
+		irq_disable(OSTM_IRQ_NUM);
+	}
+
+	/* Announce to the kernel */
+	sys_clock_announce(delta_ticks);
+}
+
+void sys_clock_set_timeout(int32_t ticks, bool idle)
+{
+	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
+		return;
+	}
+
+	if (idle && ticks == K_TICKS_FOREVER) {
+		return;
+	}
+
+	uint32_t next_cycle;
+
+	k_spinlock_key_t key = k_spin_lock(&lock);
+
+	if (ticks == K_TICKS_FOREVER) {
+		next_cycle = last_cycle + CYCLES_MAX;
+	} else {
+		next_cycle = (last_tick + last_elapsed + ticks) * CYC_PER_TICK;
+		if ((next_cycle - last_cycle) > CYCLES_MAX) {
+			next_cycle = last_cycle + CYCLES_MAX;
+		}
+	}
+
+	sys_write32(next_cycle, OSTM_REG_ADDR(OSTM_CMP_OFFSET));
+	irq_enable(OSTM_IRQ_NUM);
+
+	k_spin_unlock(&lock, key);
+}
+
+uint32_t sys_clock_elapsed(void)
+{
+	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
+		return 0;
+	}
+
+	uint32_t delta_cycles = sys_clock_cycle_get_32() - last_cycle;
+	uint32_t delta_ticks = delta_cycles / CYC_PER_TICK;
+
+	last_elapsed = delta_ticks;
+
+	return delta_ticks;
+}
+
+void sys_clock_disable(void)
+{
+	if ((sys_read8(OSTM_REG_ADDR(OSTM_TE_OFFSET)) & OSTM_TE_ENABLE) != OSTM_TE_ENABLE) {
+		return;
+	}
+
+	sys_write8(OSTM_TT_STOP, OSTM_REG_ADDR(OSTM_TT_OFFSET));
+	while ((sys_read8(OSTM_REG_ADDR(OSTM_TE_OFFSET)) & OSTM_TE_ENABLE) == OSTM_TE_ENABLE) {
+		;
+	}
+}
+
+uint32_t sys_clock_cycle_get_32(void)
+{
+	k_spinlock_key_t key = k_spin_lock(&lock);
+	uint32_t ostm_cnt = sys_read32(OSTM_REG_ADDR(OSTM_CNT_OFFSET));
+
+	k_spin_unlock(&lock, key);
+
+	return ostm_cnt;
+}
+
+static int sys_clock_driver_init(void)
+{
+	int ret;
+	const struct device *clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0));
+	uint32_t clock_subsys = DT_INST_CLOCKS_CELL(0, clk_id);
+
+	if (!device_is_ready(clock_dev)) {
+		return -ENODEV;
+	}
+
+	ret = clock_control_on(clock_dev, (clock_control_subsys_t)&clock_subsys);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = clock_control_get_rate(clock_dev, (clock_control_subsys_t)&clock_subsys,
+				     &z_clock_hw_cycles_per_sec);
+	if (ret < 0) {
+		return ret;
+	}
+
+	last_tick = 0;
+	last_cycle = 0;
+	cyc_per_tick = sys_clock_hw_cycles_per_sec() / CONFIG_SYS_CLOCK_TICKS_PER_SEC;
+	cycles_max = CYCLES_MAX_5;
+
+	DEVICE_MMIO_TOPLEVEL_MAP(ostm_base, K_MEM_CACHE_NONE);
+
+	IRQ_CONNECT(OSTM_IRQ_NUM, DT_INST_IRQ(0, priority), ostm_irq_handler, NULL,
+		    DT_INST_IRQ(0, flags));
+
+	/* Restarting the timer will cause reset of CNT register in free-running mode */
+	sys_clock_disable();
+
+	sys_write32(cyc_per_tick, OSTM_REG_ADDR(OSTM_CMP_OFFSET));
+	sys_write8(OSTM_CTL_FREERUN, OSTM_REG_ADDR(OSTM_CTL_OFFSET));
+	sys_write8(OSTM_TS_START, OSTM_REG_ADDR(OSTM_TS_OFFSET));
+
+	irq_enable(OSTM_IRQ_NUM);
+	return 0;
+}
+SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
diff --git a/drivers/timer/riscv_machine_timer.c b/drivers/timer/riscv_machine_timer.c
index 36e29c6aadb..2d0f0703508 100644
--- a/drivers/timer/riscv_machine_timer.c
+++ b/drivers/timer/riscv_machine_timer.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
  * Copyright (c) 2018-2023 Intel Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
@@ -13,71 +14,16 @@
 #include <zephyr/spinlock.h>
 #include <zephyr/irq.h>
 
-/* andestech,machine-timer */
-#if DT_HAS_COMPAT_STATUS_OKAY(andestech_machine_timer)
-#define DT_DRV_COMPAT andestech_machine_timer
-
-#define MTIME_REG	DT_INST_REG_ADDR(0)
-#define MTIMECMP_REG	(DT_INST_REG_ADDR(0) + 8)
-#define TIMER_IRQN	DT_INST_IRQN(0)
-/* neorv32-machine-timer */
-#elif DT_HAS_COMPAT_STATUS_OKAY(neorv32_machine_timer)
-#define DT_DRV_COMPAT neorv32_machine_timer
-
-#define MTIME_REG	DT_INST_REG_ADDR(0)
-#define MTIMECMP_REG	(DT_INST_REG_ADDR(0) + 8)
-#define TIMER_IRQN	DT_INST_IRQN(0)
-/* nuclei,systimer */
-#elif DT_HAS_COMPAT_STATUS_OKAY(nuclei_systimer)
-#define DT_DRV_COMPAT nuclei_systimer
-
-#define MTIME_REG	DT_INST_REG_ADDR(0)
-#define MTIMECMP_REG	(DT_INST_REG_ADDR(0) + 8)
-#define TIMER_IRQN	DT_INST_IRQ_BY_IDX(0, 1, irq)
-/* sifive,clint0 */
-#elif DT_HAS_COMPAT_STATUS_OKAY(sifive_clint0)
-#define DT_DRV_COMPAT sifive_clint0
-
-#define MTIME_REG	(DT_INST_REG_ADDR(0) + 0xbff8U)
-#define MTIMECMP_REG	(DT_INST_REG_ADDR(0) + 0x4000U)
-#define TIMER_IRQN	DT_INST_IRQ_BY_IDX(0, 1, irq)
-/* telink,machine-timer */
-#elif DT_HAS_COMPAT_STATUS_OKAY(telink_machine_timer)
-#define DT_DRV_COMPAT telink_machine_timer
-
-#define MTIME_REG	DT_INST_REG_ADDR(0)
-#define MTIMECMP_REG	(DT_INST_REG_ADDR(0) + 8)
-#define TIMER_IRQN	DT_INST_IRQN(0)
-/* lowrisc,machine-timer */
-#elif DT_HAS_COMPAT_STATUS_OKAY(lowrisc_machine_timer)
-#define DT_DRV_COMPAT lowrisc_machine_timer
-
-#define MTIME_REG	(DT_INST_REG_ADDR(0) + 0x110)
-#define MTIMECMP_REG	(DT_INST_REG_ADDR(0) + 0x118)
-#define TIMER_IRQN	DT_INST_IRQN(0)
-/* niosv-machine-timer */
-#elif DT_HAS_COMPAT_STATUS_OKAY(niosv_machine_timer)
-#define DT_DRV_COMPAT niosv_machine_timer
-
-#define MTIMECMP_REG	DT_INST_REG_ADDR(0)
-#define MTIME_REG	(DT_INST_REG_ADDR(0) + 8)
-#define TIMER_IRQN	DT_INST_IRQN(0)
-/* scr,machine-timer*/
-#elif DT_HAS_COMPAT_STATUS_OKAY(scr_machine_timer)
-#define DT_DRV_COMPAT scr_machine_timer
-#define MTIMER_HAS_DIVIDER
-
-#define MTIMEDIV_REG	(DT_INST_REG_ADDR_U64(0) + 4)
-#define MTIME_REG	(DT_INST_REG_ADDR_U64(0) + 8)
-#define MTIMECMP_REG	(DT_INST_REG_ADDR_U64(0) + 16)
-#define TIMER_IRQN	DT_INST_IRQN(0)
-#endif
+#define DT_DRV_COMPAT riscv_machine_timer
+
+#define MTIME_REG    DT_INST_REG_ADDR_BY_IDX(0, 0)
+#define MTIMECMP_REG DT_INST_REG_ADDR_BY_IDX(0, 1)
+#define TIMER_IRQN   DT_INST_IRQN(0)
 
-#define CYC_PER_TICK (uint32_t)(sys_clock_hw_cycles_per_sec() \
-				/ CONFIG_SYS_CLOCK_TICKS_PER_SEC)
+#define CYC_PER_TICK (uint32_t)(sys_clock_hw_cycles_per_sec() / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
 
 /* the unsigned long cast limits divisions to native CPU register width */
-#define cycle_diff_t unsigned long
+#define cycle_diff_t   unsigned long
 #define CYCLE_DIFF_MAX (~(cycle_diff_t)0)
 
 /*
@@ -99,11 +45,11 @@
  * consecutive set bits coming from the original max values to produce a
  * nicer literal for assembly generation.
  */
-#define CYCLES_MAX_1	((uint64_t)INT32_MAX * (uint64_t)CYC_PER_TICK)
-#define CYCLES_MAX_2	((uint64_t)CYCLE_DIFF_MAX)
-#define CYCLES_MAX_3	MIN(CYCLES_MAX_1, CYCLES_MAX_2)
-#define CYCLES_MAX_4	(CYCLES_MAX_3 / 2 + CYCLES_MAX_3 / 4)
-#define CYCLES_MAX	(CYCLES_MAX_4 + LSB_GET(CYCLES_MAX_4))
+#define CYCLES_MAX_1 ((uint64_t)INT32_MAX * (uint64_t)CYC_PER_TICK)
+#define CYCLES_MAX_2 ((uint64_t)CYCLE_DIFF_MAX)
+#define CYCLES_MAX_3 MIN(CYCLES_MAX_1, CYCLES_MAX_2)
+#define CYCLES_MAX_4 (CYCLES_MAX_3 / 2 + CYCLES_MAX_3 / 4)
+#define CYCLES_MAX   (CYCLES_MAX_4 + LSB_GET(CYCLES_MAX_4))
 
 static struct k_spinlock lock;
 static uint64_t last_count;
@@ -138,14 +84,6 @@ static void set_mtimecmp(uint64_t time)
 #endif
 }
 
-static void set_divider(void)
-{
-#ifdef MTIMER_HAS_DIVIDER
-	*(volatile uint32_t *)MTIMEDIV_REG =
-		CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER;
-#endif
-}
-
 static uint64_t mtime(void)
 {
 #ifdef CONFIG_64BIT
@@ -240,9 +178,6 @@ uint64_t sys_clock_cycle_get_64(void)
 
 static int sys_clock_driver_init(void)
 {
-
-	set_divider();
-
 	IRQ_CONNECT(TIMER_IRQN, 0, timer_isr, NULL, 0);
 	last_ticks = mtime() / CYC_PER_TICK;
 	last_count = last_ticks * CYC_PER_TICK;
@@ -259,5 +194,4 @@ void smp_timer_init(void)
 }
 #endif
 
-SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
-	 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
+SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
diff --git a/drivers/timer/sam0_rtc_timer.c b/drivers/timer/sam0_rtc_timer.c
index 8e87b1848bb..f4c4c9e4662 100644
--- a/drivers/timer/sam0_rtc_timer.c
+++ b/drivers/timer/sam0_rtc_timer.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018 omSquare s.r.o.
+ * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -25,6 +26,8 @@
 #include <zephyr/irq.h>
 #include <zephyr/sys/util.h>
 
+/* clang-format off */
+
 /* RTC registers. */
 #define RTC0 ((RtcMode0 *) DT_INST_REG_ADDR(0))
 
@@ -66,10 +69,6 @@ BUILD_ASSERT(CYCLES_PER_TICK > 1,
 
 #endif /* CONFIG_TICKLESS_KERNEL */
 
-/* Helper macro to get the correct GCLK GEN based on configuration. */
-#define GCLK_GEN(n) GCLK_EVAL(n)
-#define GCLK_EVAL(n) GCLK_CLKCTRL_GEN_GCLK##n
-
 /* Tick/cycle count of the last announce call. */
 static volatile uint32_t rtc_last;
 
@@ -245,29 +244,35 @@ uint32_t sys_clock_cycle_get_32(void)
 	return rtc_count();
 }
 
+#define ASSIGNED_CLOCKS_CELL_BY_NAME						\
+	ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_NAME
+
 static int sys_clock_driver_init(void)
 {
-	int retval;
+	volatile uint32_t *mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(0);
+	uint32_t mclk_mask = ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(0, bit);
 
+	*mclk |= mclk_mask;
 
 #ifdef MCLK
-	MCLK->APBAMASK.reg |= MCLK_APBAMASK_RTC;
 	OSC32KCTRL->RTCCTRL.reg = OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K;
 #else
-	/* Set up bus clock and GCLK generator. */
-	PM->APBAMASK.reg |= PM_APBAMASK_RTC;
-	GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(RTC_GCLK_ID) | GCLK_CLKCTRL_CLKEN
-			    | GCLK_GEN(DT_INST_PROP(0, clock_generator));
+	GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN
+			  | GCLK_CLKCTRL_GEN(ASSIGNED_CLOCKS_CELL_BY_NAME(0, gclk, gen))
+			  | GCLK_CLKCTRL_ID(DT_INST_CLOCKS_CELL_BY_NAME(0, gclk, id));
 
 	/* Synchronize GCLK. */
 	while (GCLK->STATUS.bit.SYNCBUSY) {
 	}
 #endif
 
-	retval = pinctrl_apply_state(pcfg, PINCTRL_STATE_DEFAULT);
-	if (retval < 0) {
+#ifndef CONFIG_TICKLESS_KERNEL
+	int retval = pinctrl_apply_state(pcfg, PINCTRL_STATE_DEFAULT);
+
+	if (retval < 0 && retval != -ENOENT) {
 		return retval;
 	}
+#endif
 
 	/* Reset module to hardware defaults. */
 	rtc_reset();
@@ -330,3 +335,5 @@ static int sys_clock_driver_init(void)
 
 SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
 	 CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
+
+/* clang-format on */
diff --git a/drivers/timer/silabs_sleeptimer_timer.c b/drivers/timer/silabs_sleeptimer_timer.c
index 405fa1496a5..d0e643d21bf 100644
--- a/drivers/timer/silabs_sleeptimer_timer.c
+++ b/drivers/timer/silabs_sleeptimer_timer.c
@@ -21,7 +21,6 @@ LOG_MODULE_REGISTER(silabs_sleeptimer_timer);
 
 /* Maximum time interval between timer interrupts (in hw_cycles) */
 #define MAX_TIMEOUT_CYC (UINT32_MAX >> 1)
-#define MIN_DELAY_CYC   (4U)
 
 #define DT_RTC DT_COMPAT_GET_ANY_STATUS_OKAY(silabs_gecko_stimer)
 
@@ -31,7 +30,7 @@ LOG_MODULE_REGISTER(silabs_sleeptimer_timer);
 /* With CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME, this global variable holds the clock frequency,
  * and must be written by the driver at init.
  */
-extern int z_clock_hw_cycles_per_sec;
+extern unsigned int z_clock_hw_cycles_per_sec;
 
 /* Global timer state */
 struct sleeptimer_timer_data {
@@ -73,16 +72,15 @@ static void sleeptimer_clock_set_timeout(int32_t ticks, struct sleeptimer_timer_
 	k_spinlock_key_t key = k_spin_lock(&timer->lock);
 
 	uint32_t curr = sl_sleeptimer_get_tick_count();
-	uint32_t prev = atomic_get(&timer->last_count);
-	uint32_t pending = curr - prev;
+	uint32_t pending = curr % timer->cyc_per_tick;
 	uint32_t next = ticks * timer->cyc_per_tick;
 
 	/* Next timeout is N ticks in the future, minus the current progress
-	 * towards the timeout. If we are behind, set the timeout to the first
-	 * possible upcoming tick.
+	 * into the tick if using multiple cycles per tick. The HAL API must
+	 * be called with a timeout of at least one cycle.
 	 */
-	while (next < (pending + MIN_DELAY_CYC)) {
-		next += timer->cyc_per_tick;
+	if (next == 0) {
+		next = timer->cyc_per_tick;
 	}
 	next -= pending;
 
@@ -136,17 +134,11 @@ static int sleeptimer_init(void)
 
 	timer->cyc_per_tick = z_clock_hw_cycles_per_sec / CONFIG_SYS_CLOCK_TICKS_PER_SEC;
 
-	__ASSERT(timer->cyc_per_tick >= MIN_DELAY_CYC,
-		 "A tick of %u cycles is too short to be scheduled "
-		 "(min is %u). Config: SYS_CLOCK_TICKS_PER_SEC is "
-		 "%d and timer frequency is %u",
-		 timer->cyc_per_tick, MIN_DELAY_CYC, CONFIG_SYS_CLOCK_TICKS_PER_SEC,
-		 z_clock_hw_cycles_per_sec);
-
 	timer->max_timeout_ticks = MAX_TIMEOUT_CYC / timer->cyc_per_tick;
 	timer->initialized = true;
 
-	atomic_set(&timer->last_count, sl_sleeptimer_get_tick_count());
+	atomic_set(&timer->last_count,
+		   ROUND_DOWN(sl_sleeptimer_get_tick_count(), timer->cyc_per_tick));
 
 	/* Start the timer and announce 1 kernel tick */
 	if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
diff --git a/drivers/timer/smartbond_timer.c b/drivers/timer/smartbond_timer.c
index afa86617e0e..0e4e0a021fa 100644
--- a/drivers/timer/smartbond_timer.c
+++ b/drivers/timer/smartbond_timer.c
@@ -103,7 +103,7 @@ void sys_clock_set_timeout(int32_t ticks, bool idle)
 	 * as soon as system is awaken. Following code makes sure that
 	 * system never goes to sleep for longer time that watchdog reload value.
 	 */
-	if (!IS_ENABLED(CONFIG_WDT_SMARTBOND) && IS_ENABLED(CONFIG_PM)) {
+	if (IS_ENABLED(CONFIG_PM)) {
 		uint32_t watchdog_expire_ticks;
 
 		if (CRG_TOP->CLK_RCX_REG & CRG_TOP_CLK_RCX_REG_RCX_ENABLE_Msk) {
@@ -120,7 +120,8 @@ void sys_clock_set_timeout(int32_t ticks, bool idle)
 			 * RC32K maximum frequency.
 			 */
 			watchdog_expire_ticks = SYS_WDOG->WATCHDOG_REG *
-				CONFIG_SYS_CLOCK_TICKS_PER_SEC / (get_rc32k_max_frequency() / 320);
+				CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC /
+				(get_rc32k_max_frequency() / 320);
 		}
 		if (watchdog_expire_ticks - 2 < ticks) {
 			ticks = watchdog_expire_ticks - 2;
diff --git a/drivers/timer/ti_dmtimer.c b/drivers/timer/ti_dmtimer.c
index e19db1dd69f..03940c0ce17 100644
--- a/drivers/timer/ti_dmtimer.c
+++ b/drivers/timer/ti_dmtimer.c
@@ -17,30 +17,40 @@
 
 #define DT_DRV_COMPAT ti_am654_timer
 
-#define TIMER_BASE_ADDR DT_INST_REG_ADDR(0)
-
 #define TIMER_IRQ_NUM   DT_INST_IRQN(0)
 #define TIMER_IRQ_PRIO  DT_INST_IRQ(0, priority)
 #define TIMER_IRQ_FLAGS DT_INST_IRQ(0, flags)
 
-#define CYC_PER_TICK ((uint32_t)(sys_clock_hw_cycles_per_sec() \
-				/ CONFIG_SYS_CLOCK_TICKS_PER_SEC))
+#if defined(CONFIG_TEST)
+const int32_t z_sys_timer_irq_for_test = TIMER_IRQ_NUM;
+#endif
+
+#define CYC_PER_TICK ((uint32_t)(sys_clock_hw_cycles_per_sec() / CONFIG_SYS_CLOCK_TICKS_PER_SEC))
 
 #define MAX_TICKS ((k_ticks_t)(UINT32_MAX / CYC_PER_TICK) - 1)
 
-static struct k_spinlock lock;
+#define DEV_CFG(_dev)  ((const struct ti_dm_timer_config *)(_dev)->config)
+#define DEV_DATA(_dev) ((struct ti_dm_timer_data *)(_dev)->data)
+
+struct ti_dm_timer_config {
+	DEVICE_MMIO_NAMED_ROM(reg_base);
+};
+
+struct ti_dm_timer_data {
+	DEVICE_MMIO_NAMED_RAM(reg_base);
+	struct k_spinlock lock;
+	uint32_t last_cycle;
+};
 
-static uint32_t last_cycle;
+static const struct device *systick_timer_dev;
 
-#define TI_DM_TIMER_READ(reg) sys_read32(TIMER_BASE_ADDR + TI_DM_TIMER_ ## reg)
+#define TI_DM_TIMER_MASK(reg)  TI_DM_TIMER_##reg##_MASK
+#define TI_DM_TIMER_SHIFT(reg) TI_DM_TIMER_##reg##_SHIFT
 
-#define TI_DM_TIMER_MASK(reg) TI_DM_TIMER_ ## reg ## _MASK
-#define TI_DM_TIMER_SHIFT(reg) TI_DM_TIMER_ ## reg ## _SHIFT
-#define TI_DM_TIMER_WRITE(data, reg, bits) \
-	ti_dm_timer_write_masks(data, \
-		TIMER_BASE_ADDR + TI_DM_TIMER_ ## reg, \
-		TI_DM_TIMER_MASK(reg ## _ ## bits), \
-		TI_DM_TIMER_SHIFT(reg ## _ ## bits))
+#define TI_DM_TIMER_READ(dev, reg) sys_read32(DEVICE_MMIO_GET(dev) + TI_DM_TIMER_##reg)
+#define TI_DM_TIMER_WRITE(dev, data, reg, bits)                                                    \
+	ti_dm_timer_write_masks(data, DEVICE_MMIO_GET(dev) + TI_DM_TIMER_##reg,                    \
+				TI_DM_TIMER_MASK(reg##_##bits), TI_DM_TIMER_SHIFT(reg##_##bits))
 
 static void ti_dm_timer_write_masks(uint32_t data, uint32_t reg, uint32_t mask, uint32_t shift)
 {
@@ -51,32 +61,36 @@ static void ti_dm_timer_write_masks(uint32_t data, uint32_t reg, uint32_t mask,
 	sys_write32(reg_val, reg);
 }
 
-static void ti_dmtimer_isr(void *data)
+static void ti_dmtimer_isr(void *param)
 {
+	ARG_UNUSED(param);
+
+	struct ti_dm_timer_data *data = systick_timer_dev->data;
+
 	/* If no pending event */
-	if (!TI_DM_TIMER_READ(IRQSTATUS)) {
+	if (!TI_DM_TIMER_READ(systick_timer_dev, IRQSTATUS)) {
 		return;
 	}
 
-	k_spinlock_key_t key = k_spin_lock(&lock);
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
 
-	uint32_t curr_cycle = TI_DM_TIMER_READ(TCRR);
-	uint32_t delta_cycles = curr_cycle - last_cycle;
+	uint32_t curr_cycle = TI_DM_TIMER_READ(systick_timer_dev, TCRR);
+	uint32_t delta_cycles = curr_cycle - data->last_cycle;
 	uint32_t delta_ticks = delta_cycles / CYC_PER_TICK;
 
-	last_cycle = curr_cycle;
+	data->last_cycle = curr_cycle;
 
 	/* ACK match interrupt */
-	TI_DM_TIMER_WRITE(1, IRQSTATUS, MAT_IT_FLAG);
+	TI_DM_TIMER_WRITE(systick_timer_dev, 1, IRQSTATUS, MAT_IT_FLAG);
 
 	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
 		/* Setup next match time */
 		uint64_t next_cycle = curr_cycle + CYC_PER_TICK;
 
-		TI_DM_TIMER_WRITE(next_cycle, TMAR, COMPARE_VALUE);
+		TI_DM_TIMER_WRITE(systick_timer_dev, next_cycle, TMAR, COMPARE_VALUE);
 	}
 
-	k_spin_unlock(&lock, key);
+	k_spin_unlock(&data->lock, key);
 
 	sys_clock_announce(delta_ticks);
 }
@@ -84,6 +98,9 @@ static void ti_dmtimer_isr(void *data)
 void sys_clock_set_timeout(int32_t ticks, bool idle)
 {
 	ARG_UNUSED(idle);
+
+	struct ti_dm_timer_data *data = systick_timer_dev->data;
+
 	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
 		/* Not supported on tickful kernels */
 		return;
@@ -92,80 +109,101 @@ void sys_clock_set_timeout(int32_t ticks, bool idle)
 	ticks = (ticks == K_TICKS_FOREVER) ? MAX_TICKS : ticks;
 	ticks = CLAMP(ticks, 1, (int32_t)MAX_TICKS);
 
-	k_spinlock_key_t key = k_spin_lock(&lock);
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
 
 	/* Setup next match time */
-	uint32_t curr_cycle = TI_DM_TIMER_READ(TCRR);
+	uint32_t curr_cycle = TI_DM_TIMER_READ(systick_timer_dev, TCRR);
 	uint32_t next_cycle = curr_cycle + (ticks * CYC_PER_TICK);
 
-	TI_DM_TIMER_WRITE(next_cycle, TMAR, COMPARE_VALUE);
+	TI_DM_TIMER_WRITE(systick_timer_dev, next_cycle, TMAR, COMPARE_VALUE);
 
-	k_spin_unlock(&lock, key);
+	k_spin_unlock(&data->lock, key);
 }
 
 uint32_t sys_clock_cycle_get_32(void)
 {
-	k_spinlock_key_t key = k_spin_lock(&lock);
+	struct ti_dm_timer_data *data = systick_timer_dev->data;
 
-	uint32_t curr_cycle = TI_DM_TIMER_READ(TCRR);
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
 
-	k_spin_unlock(&lock, key);
+	uint32_t curr_cycle = TI_DM_TIMER_READ(systick_timer_dev, TCRR);
+
+	k_spin_unlock(&data->lock, key);
 
 	return curr_cycle;
 }
 
 unsigned int sys_clock_elapsed(void)
 {
+	struct ti_dm_timer_data *data = systick_timer_dev->data;
+
 	if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
 		/* Always return 0 for tickful kernel system */
 		return 0;
 	}
 
-	k_spinlock_key_t key = k_spin_lock(&lock);
+	k_spinlock_key_t key = k_spin_lock(&data->lock);
 
-	uint32_t curr_cycle = TI_DM_TIMER_READ(TCRR);
-	uint32_t delta_cycles = curr_cycle - last_cycle;
+	uint32_t curr_cycle = TI_DM_TIMER_READ(systick_timer_dev, TCRR);
+	uint32_t delta_cycles = curr_cycle - data->last_cycle;
 	uint32_t delta_ticks = delta_cycles / CYC_PER_TICK;
 
-	k_spin_unlock(&lock, key);
+	k_spin_unlock(&data->lock, key);
 
 	return delta_ticks;
 }
 
 static int sys_clock_driver_init(void)
 {
-	last_cycle = 0;
+	struct ti_dm_timer_data *data;
+
+	systick_timer_dev = DEVICE_DT_GET(DT_NODELABEL(systick_timer));
+
+	data = systick_timer_dev->data;
+
+	data->last_cycle = 0;
+
+	DEVICE_MMIO_NAMED_MAP(systick_timer_dev, reg_base, K_MEM_CACHE_NONE);
 
 	IRQ_CONNECT(TIMER_IRQ_NUM, TIMER_IRQ_PRIO, ti_dmtimer_isr, NULL, TIMER_IRQ_FLAGS);
 
 	/* Disable prescalar */
-	TI_DM_TIMER_WRITE(0, TCLR, PRE);
+	TI_DM_TIMER_WRITE(systick_timer_dev, 0, TCLR, PRE);
 
 	/* Select autoreload mode */
-	TI_DM_TIMER_WRITE(1, TCLR, AR);
+	TI_DM_TIMER_WRITE(systick_timer_dev, 1, TCLR, AR);
 
 	/* Enable match interrupt */
-	TI_DM_TIMER_WRITE(1, IRQENABLE_SET, MAT_EN_FLAG);
+	TI_DM_TIMER_WRITE(systick_timer_dev, 1, IRQENABLE_SET, MAT_EN_FLAG);
 
 	/* Load timer counter value */
-	TI_DM_TIMER_WRITE(0, TCRR, TIMER_COUNTER);
+	TI_DM_TIMER_WRITE(systick_timer_dev, 0, TCRR, TIMER_COUNTER);
 
 	/* Load timer load value */
-	TI_DM_TIMER_WRITE(0, TLDR, LOAD_VALUE);
+	TI_DM_TIMER_WRITE(systick_timer_dev, 0, TLDR, LOAD_VALUE);
 
 	/* Load timer compare value */
-	TI_DM_TIMER_WRITE(CYC_PER_TICK, TMAR, COMPARE_VALUE);
+	TI_DM_TIMER_WRITE(systick_timer_dev, CYC_PER_TICK, TMAR, COMPARE_VALUE);
 
 	/* Enable compare mode */
-	TI_DM_TIMER_WRITE(1, TCLR, CE);
+	TI_DM_TIMER_WRITE(systick_timer_dev, 1, TCLR, CE);
 
 	/* Start the timer */
-	TI_DM_TIMER_WRITE(1, TCLR, ST);
+	TI_DM_TIMER_WRITE(systick_timer_dev, 1, TCLR, ST);
 
 	irq_enable(TIMER_IRQ_NUM);
 
 	return 0;
 }
 
-SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
-	CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
+#define TI_DM_TIMER(n)                                                                             \
+	static struct ti_dm_timer_data ti_dm_timer_data_##n;                                       \
+	static const struct ti_dm_timer_config ti_dm_timer_config_##n = {                          \
+		DEVICE_MMIO_NAMED_ROM_INIT(reg_base, DT_DRV_INST(n)),                              \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(n, NULL, NULL, &ti_dm_timer_data_##n, &ti_dm_timer_config_##n,       \
+			      PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(TI_DM_TIMER);
+
+SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
diff --git a/drivers/usb/common/Kconfig b/drivers/usb/common/Kconfig
index 7f6a02614b8..d5a0d4dc1b4 100644
--- a/drivers/usb/common/Kconfig
+++ b/drivers/usb/common/Kconfig
@@ -1,4 +1,8 @@
 # Copyright (c) 2023 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
+menu "USB common"
+
 rsource "nrf_usbd_common/Kconfig"
+
+endmenu
diff --git a/drivers/usb/device/usb_dc_kinetis.c b/drivers/usb/device/usb_dc_kinetis.c
index c6ff25aabde..0bdbb0cbde3 100644
--- a/drivers/usb/device/usb_dc_kinetis.c
+++ b/drivers/usb/device/usb_dc_kinetis.c
@@ -40,6 +40,13 @@ LOG_MODULE_REGISTER(usb_dc_kinetis);
 #define KINETIS_EP_NUMOF_MASK	0xf
 #define KINETIS_ADDR2IDX(addr)	((addr) & (KINETIS_EP_NUMOF_MASK))
 
+/*
+ * In some SoC USB0 base register is defined as USBFS0
+ */
+#if !defined(USB0) && defined(USBFS0)
+#define USB0				USBFS0
+#endif
+
 /*
  * Buffer Descriptor (BD) entry provides endpoint buffer control
  * information for USBFS controller. Every endpoint direction requires
diff --git a/drivers/usb/device/usb_dc_mcux.c b/drivers/usb/device/usb_dc_mcux.c
index 14a8918d106..d6dd8e0b0c2 100644
--- a/drivers/usb/device/usb_dc_mcux.c
+++ b/drivers/usb/device/usb_dc_mcux.c
@@ -90,6 +90,7 @@ BUILD_ASSERT(NUM_INSTS <= 1, "Only one USB device supported");
 #define CONTROLLER_ID	kUSB_ControllerLpcIp3511Fs0
 #endif /* LPC55s69 */
 #elif defined(CONFIG_SOC_SERIES_IMXRT11XX) || \
+	defined(CONFIG_SOC_SERIES_IMXRT118X) || \
 	defined(CONFIG_SOC_SERIES_IMXRT10XX) || \
 	defined(CONFIG_SOC_SERIES_MCXN)
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1))
@@ -97,11 +98,8 @@ BUILD_ASSERT(NUM_INSTS <= 1, "Only one USB device supported");
 #elif DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb2))
 #define CONTROLLER_ID kUSB_ControllerEhci1
 #endif /* IMX RT */
-#elif defined(CONFIG_SOC_SERIES_RW6XX)
-#define CONTROLLER_ID kUSB_ControllerEhci0
 #else
-/* If SOC has EHCI or LPCIP3511 then probably just need to add controller ID to this code */
-#error "USB driver does not yet support this SOC"
+#define CONTROLLER_ID kUSB_ControllerEhci0
 #endif /* CONTROLLER ID */
 
 /* We do not need a buffer for the write side on platforms that have USB RAM.
diff --git a/drivers/usb/device/usb_dc_rpi_pico.c b/drivers/usb/device/usb_dc_rpi_pico.c
index c0b55a7de5f..24485ee7f4c 100644
--- a/drivers/usb/device/usb_dc_rpi_pico.c
+++ b/drivers/usb/device/usb_dc_rpi_pico.c
@@ -524,6 +524,9 @@ static int udc_rpi_init(void)
 		hw_set_alias(usb_hw)->sie_ctrl = USB_SIE_CTRL_PULLUP_EN_BITS;
 	}
 
+	IRQ_CONNECT(USB_IRQ, USB_IRQ_PRI, udc_rpi_isr, 0, 0);
+	irq_enable(USB_IRQ);
+
 	return 0;
 }
 
@@ -1072,9 +1075,6 @@ static int usb_rpi_init(void)
 		return ret;
 	}
 
-	IRQ_CONNECT(USB_IRQ, USB_IRQ_PRI, udc_rpi_isr, 0, 0);
-	irq_enable(USB_IRQ);
-
 	return 0;
 }
 
diff --git a/drivers/usb/device/usb_dc_stm32.c b/drivers/usb/device/usb_dc_stm32.c
index dd435842306..16b91470dee 100644
--- a/drivers/usb/device/usb_dc_stm32.c
+++ b/drivers/usb/device/usb_dc_stm32.c
@@ -67,15 +67,16 @@ LOG_MODULE_REGISTER(usb_dc_stm32);
 
 static const struct stm32_pclken pclken[] = STM32_DT_INST_CLOCKS(0);
 
-#if DT_INST_NODE_HAS_PROP(0, maximum_speed)
-#define USB_MAXIMUM_SPEED	DT_INST_PROP(0, maximum_speed)
-#endif
-
+#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_otghs)
 PINCTRL_DT_INST_DEFINE(0);
 static const struct pinctrl_dev_config *usb_pcfg =
 					PINCTRL_DT_INST_DEV_CONFIG_GET(0);
+#endif
 
-#define USB_OTG_HS_EMB_PHY (DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) && \
+#define USB_OTG_HS_EMB_PHYC (DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) && \
+			     DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs))
+
+#define USB_OTG_HS_EMB_PHY (DT_HAS_COMPAT_STATUS_OKAY(st_stm32u5_otghs_phy) && \
 			    DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs))
 
 #define USB_OTG_HS_ULPI_PHY (DT_HAS_COMPAT_STATUS_OKAY(usb_ulpi_phy) && \
@@ -86,6 +87,22 @@ static const struct gpio_dt_spec ulpi_reset =
 	GPIO_DT_SPEC_GET_OR(DT_PHANDLE(DT_INST(0, st_stm32_otghs), phys), reset_gpios, {0});
 #endif
 
+/**
+ * The following defines are used to map the value of the "maxiumum-speed"
+ * DT property to the corresponding definition used by the STM32 HAL.
+ */
+#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(USB_OTG_HS_EMB_PHYC) || \
+	defined(USB_OTG_HS_EMB_PHY)
+#define USB_DC_STM32_HIGH_SPEED             USB_OTG_SPEED_HIGH_IN_FULL
+#else
+#define USB_DC_STM32_HIGH_SPEED             USB_OTG_SPEED_HIGH
+#endif
+
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usb)
+#define USB_DC_STM32_FULL_SPEED             PCD_SPEED_FULL
+#else
+#define USB_DC_STM32_FULL_SPEED             USB_OTG_SPEED_FULL
+#endif
 /*
  * USB, USB_OTG_FS and USB_DRD_FS are defined in STM32Cube HAL and allows to
  * distinguish between two kind of USB DC. STM32 F0, F3, L0 and G4 series
@@ -324,6 +341,14 @@ static int usb_dc_stm32_phy_specific_clock_enable(const struct device *const clk
 	 * with LL_PWR_EnableVDDUSB function (higher case)
 	 */
 	LL_PWR_EnableVDDUSB();
+#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_otghs)
+	/* Enable Vdd USB voltage monitoring */
+	LL_PWR_EnableVddUSBMonitoring();
+	while (__HAL_PWR_GET_FLAG(PWR_FLAG_USB33RDY)) {
+		/* Wait for VDD33USB ready */
+	}
+	/* Enable VDDUSB */
+	LL_PWR_EnableVddUSB();
 #endif
 
 	if (DT_INST_NUM_CLOCKS(0) > 1) {
@@ -402,13 +427,15 @@ static int usb_dc_stm32_clock_enable(void)
 	/* Both OTG HS and USBPHY sleep clock MUST be disabled here at the same time */
 	LL_AHB2_GRP1_DisableClockStopSleep(LL_AHB2_GRP1_PERIPH_OTG_HS ||
 						LL_AHB2_GRP1_PERIPH_USBPHY);
-#else
+#elif !DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_otghs)
 	LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
 #endif
 
-#if USB_OTG_HS_EMB_PHY
+#if USB_OTG_HS_EMB_PHYC
+#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_otghs)
 	LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
 #endif
+#endif
 #endif /* USB_OTG_HS_ULPI_PHY */
 
 	return 0;
@@ -429,66 +456,28 @@ static int usb_dc_stm32_clock_disable(void)
 	return 0;
 }
 
-#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
-static uint32_t usb_dc_stm32_get_maximum_speed(void)
-{
-	/*
-	 * If max-speed is not passed via DT, set it to USB controller's
-	 * maximum hardware capability.
-	 */
-#if USB_OTG_HS_EMB_PHY || USB_OTG_HS_ULPI_PHY
-	uint32_t speed = USB_OTG_SPEED_HIGH;
-#else
-	uint32_t speed = USB_OTG_SPEED_FULL;
-#endif
-
-#ifdef USB_MAXIMUM_SPEED
-
-	if (!strncmp(USB_MAXIMUM_SPEED, "high-speed", 10)) {
-		speed = USB_OTG_SPEED_HIGH;
-	} else if (!strncmp(USB_MAXIMUM_SPEED, "full-speed", 10)) {
-#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(USB_OTG_HS_EMB_PHY)
-		speed = USB_OTG_SPEED_HIGH_IN_FULL;
-#else
-		speed = USB_OTG_SPEED_FULL;
-#endif
-	} else {
-		LOG_DBG("Unsupported maximum speed defined in device tree. "
-			"USB controller will default to its maximum HW "
-			"capability");
-	}
-#endif
-
-	return speed;
-}
-#endif /* USB_OTG_FS || USB_OTG_HS */
-
 static int usb_dc_stm32_init(void)
 {
 	HAL_StatusTypeDef status;
-	int ret;
 	unsigned int i;
 
+	usb_dc_stm32_state.pcd.Init.speed =
+			UTIL_CAT(USB_DC_STM32_, DT_INST_STRING_UPPER_TOKEN(0, maximum_speed));
+
 #if defined(USB) || defined(USB_DRD_FS)
 #ifdef USB
 	usb_dc_stm32_state.pcd.Instance = USB;
 #else
 	usb_dc_stm32_state.pcd.Instance = USB_DRD_FS;
 #endif
-	usb_dc_stm32_state.pcd.Init.speed = PCD_SPEED_FULL;
 	usb_dc_stm32_state.pcd.Init.dev_endpoints = USB_NUM_BIDIR_ENDPOINTS;
 	usb_dc_stm32_state.pcd.Init.phy_itface = PCD_PHY_EMBEDDED;
 	usb_dc_stm32_state.pcd.Init.ep0_mps = PCD_EP0MPS_64;
 	usb_dc_stm32_state.pcd.Init.low_power_enable = 0;
 #else /* USB_OTG_FS || USB_OTG_HS */
-#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
-	usb_dc_stm32_state.pcd.Instance = USB_OTG_HS;
-#else
-	usb_dc_stm32_state.pcd.Instance = USB_OTG_FS;
-#endif
+	usb_dc_stm32_state.pcd.Instance = (USB_OTG_GlobalTypeDef *)USB_BASE_ADDRESS;
 	usb_dc_stm32_state.pcd.Init.dev_endpoints = USB_NUM_BIDIR_ENDPOINTS;
-	usb_dc_stm32_state.pcd.Init.speed = usb_dc_stm32_get_maximum_speed();
-#if USB_OTG_HS_EMB_PHY
+#if USB_OTG_HS_EMB_PHYC || USB_OTG_HS_EMB_PHY
 	usb_dc_stm32_state.pcd.Init.phy_itface = USB_OTG_HS_EMBEDDED_PHY;
 #elif USB_OTG_HS_ULPI_PHY
 	usb_dc_stm32_state.pcd.Init.phy_itface = USB_OTG_ULPI_PHY;
@@ -529,12 +518,14 @@ static int usb_dc_stm32_init(void)
 	}
 #endif
 
+#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_otghs)
 	LOG_DBG("Pinctrl signals configuration");
-	ret = pinctrl_apply_state(usb_pcfg, PINCTRL_STATE_DEFAULT);
+	int ret = pinctrl_apply_state(usb_pcfg, PINCTRL_STATE_DEFAULT);
 	if (ret < 0) {
 		LOG_ERR("USB pinctrl setup failed (%d)", ret);
 		return ret;
 	}
+#endif
 
 	LOG_DBG("HAL_PCD_Init");
 	status = HAL_PCD_Init(&usb_dc_stm32_state.pcd);
@@ -1277,6 +1268,19 @@ void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 	}
 }
 
+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+	uint8_t ep_idx = USB_EP_GET_IDX(epnum);
+	uint8_t ep = ep_idx | USB_EP_DIR_IN;
+	struct usb_dc_stm32_ep_state *ep_state = usb_dc_stm32_get_ep_state(ep);
+
+	LOG_DBG("epnum 0x%02x", epnum);
+
+	__ASSERT(ep_state, "No corresponding ep_state for ep");
+
+	k_sem_give(&ep_state->write_sem);
+}
+
 #if (defined(USB) || defined(USB_DRD_FS)) && DT_INST_NODE_HAS_PROP(0, disconnect_gpios)
 void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
 {
diff --git a/drivers/usb/udc/CMakeLists.txt b/drivers/usb/udc/CMakeLists.txt
index 0fdc321a314..c8fbc9b6011 100644
--- a/drivers/usb/udc/CMakeLists.txt
+++ b/drivers/usb/udc/CMakeLists.txt
@@ -20,3 +20,4 @@ zephyr_library_sources_ifdef(CONFIG_UDC_NUMAKER udc_numaker.c)
 zephyr_library_sources_ifdef(CONFIG_UDC_RPI_PICO udc_rpi_pico.c)
 zephyr_library_sources_ifdef(CONFIG_UDC_AMBIQ udc_ambiq.c)
 zephyr_library_sources_ifdef(CONFIG_UDC_RENESAS_RA udc_renesas_ra.c)
+zephyr_library_sources_ifdef(CONFIG_UDC_MAX32 udc_max32.c)
diff --git a/drivers/usb/udc/Kconfig b/drivers/usb/udc/Kconfig
index fd5e25cf113..997da20d7cb 100644
--- a/drivers/usb/udc/Kconfig
+++ b/drivers/usb/udc/Kconfig
@@ -11,6 +11,16 @@ menuconfig UDC_DRIVER
 
 if UDC_DRIVER
 
+config UDC_DRIVER_HAS_HIGH_SPEED_SUPPORT
+	bool
+
+config UDC_DRIVER_HIGH_SPEED_SUPPORT_ENABLED
+	bool "Allow High-Speed chirp"
+	default y if UDC_DRIVER_HAS_HIGH_SPEED_SUPPORT
+	help
+	  Allow High-Speed capable device to operate at High-Speed. Disable this
+	  option to force Full-Speed only operation.
+
 config UDC_BUF_COUNT
 	int "Number of buffers in the pool"
 	range 16 256
@@ -67,5 +77,6 @@ source "drivers/usb/udc/Kconfig.numaker"
 source "drivers/usb/udc/Kconfig.rpi_pico"
 source "drivers/usb/udc/Kconfig.ambiq"
 source "drivers/usb/udc/Kconfig.renesas_ra"
+source "drivers/usb/udc/Kconfig.max32"
 
 endif # UDC_DRIVER
diff --git a/drivers/usb/udc/Kconfig.ambiq b/drivers/usb/udc/Kconfig.ambiq
index 93566cfbf5d..5508b6d3288 100644
--- a/drivers/usb/udc/Kconfig.ambiq
+++ b/drivers/usb/udc/Kconfig.ambiq
@@ -11,16 +11,16 @@ config UDC_AMBIQ
 	help
 	  Enable USB Device Controller Driver.
 
+if UDC_AMBIQ
+
 config UDC_AMBIQ_STACK_SIZE
 	int "UDC AMBIQ driver internal thread stack size"
-	depends on UDC_AMBIQ
 	default 2048
 	help
 	  AMBIQ driver internal thread stack size.
 
 config UDC_AMBIQ_THREAD_PRIORITY
 	int "UDC AMBIQ driver thread priority"
-	depends on UDC_AMBIQ
 	default 8
 	help
 	  AMBIQ driver thread priority.
@@ -32,3 +32,5 @@ config UDC_AMBIQ_MAX_QMESSAGES
 	default 8
 	help
 	  AMBIQ maximum number of ISR event messages.
+
+endif # UDC_AMBIQ
diff --git a/drivers/usb/udc/Kconfig.dwc2 b/drivers/usb/udc/Kconfig.dwc2
index 2f40c8f71a2..9486f88c3ba 100644
--- a/drivers/usb/udc/Kconfig.dwc2
+++ b/drivers/usb/udc/Kconfig.dwc2
@@ -5,6 +5,7 @@ config UDC_DWC2
 	bool "DWC2 USB device controller driver"
 	default y
 	depends on DT_HAS_SNPS_DWC2_ENABLED
+	select UDC_DRIVER_HAS_HIGH_SPEED_SUPPORT
 	select NRFS if NRFS_HAS_VBUS_DETECTOR_SERVICE
 	select NRFS_VBUS_DETECTOR_SERVICE_ENABLED if NRFS_HAS_VBUS_DETECTOR_SERVICE
 	select EVENTS
diff --git a/drivers/usb/udc/Kconfig.max32 b/drivers/usb/udc/Kconfig.max32
new file mode 100644
index 00000000000..78c5444171b
--- /dev/null
+++ b/drivers/usb/udc/Kconfig.max32
@@ -0,0 +1,32 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config UDC_MAX32
+	bool "MAX32 USB device controller driver"
+	default y
+	depends on DT_HAS_ADI_MAX32_USBHS_ENABLED
+	help
+	  MAX32 USB device controller driver.
+
+if UDC_MAX32
+
+config UDC_MAX32_THREAD_PRIORITY
+	int "MAX32 USB device controller driver thread priority"
+	default 8
+	help
+	  MAX32 USB device device controller driver thread priority.
+
+config UDC_MAX32_THREAD_STACK_SIZE
+	int "MAX32 UDC driver internal thread stack size"
+	default 1024
+	help
+	  Size of the stack for the driver internal thread.
+
+config UDC_MAX32_MAX_QMESSAGES
+	int "MAX32 UDC driver maximum number of ISR event messages"
+	range 4 64
+	default 8
+	help
+	  Maximum number of messages for handling of MAX32 USBD ISR events.
+
+endif # UDC_MAX32
diff --git a/drivers/usb/udc/Kconfig.mcux b/drivers/usb/udc/Kconfig.mcux
index be744a1122e..7ebace0e7f7 100644
--- a/drivers/usb/udc/Kconfig.mcux
+++ b/drivers/usb/udc/Kconfig.mcux
@@ -5,8 +5,9 @@ config UDC_NXP_EHCI
 	bool "NXP MCUX USB EHCI Device controller driver"
 	default y
 	depends on DT_HAS_NXP_EHCI_ENABLED
+	select UDC_DRIVER_HAS_HIGH_SPEED_SUPPORT
 	select PINCTRL
-	select NOCACHE_MEMORY if HAS_MCUX_CACHE && CPU_HAS_DCACHE
+	select NOCACHE_MEMORY if CPU_HAS_DCACHE
 	imply UDC_BUF_FORCE_NOCACHE
 	imply UDC_WORKQUEUE
 	help
@@ -16,6 +17,7 @@ config UDC_NXP_IP3511
 	bool "NXP MCUX USB IP3511 Device controller driver"
 	default y
 	depends on DT_HAS_NXP_LPCIP3511_ENABLED
+	select UDC_DRIVER_HAS_HIGH_SPEED_SUPPORT
 	select PINCTRL
 	imply UDC_WORKQUEUE
 	help
diff --git a/drivers/usb/udc/Kconfig.nrf b/drivers/usb/udc/Kconfig.nrf
index 93c5090bed2..bcb0e1f017b 100644
--- a/drivers/usb/udc/Kconfig.nrf
+++ b/drivers/usb/udc/Kconfig.nrf
@@ -7,6 +7,7 @@ config UDC_NRF
 	depends on DT_HAS_NORDIC_NRF_USBD_ENABLED
 	select NRF_USBD_COMMON
 	select NRFX_POWER
+	select EVENTS
 	help
 	  nRF USB device controller driver.
 
@@ -18,11 +19,4 @@ config UDC_NRF_THREAD_STACK_SIZE
 	help
 	  Size of the stack used in the driver for nRF USBD ISR event handling.
 
-config UDC_NRF_MAX_QMESSAGES
-	int "nRF UDC driver maximum number of ISR event messages"
-	range 4 64
-	default 8
-	help
-	  Maximum number of messages for handling of nRF USBD ISR events.
-
 endif # UDC_NRF
diff --git a/drivers/usb/udc/Kconfig.rpi_pico b/drivers/usb/udc/Kconfig.rpi_pico
index 3656a754afc..fd194520c72 100644
--- a/drivers/usb/udc/Kconfig.rpi_pico
+++ b/drivers/usb/udc/Kconfig.rpi_pico
@@ -6,6 +6,8 @@ config UDC_RPI_PICO
 	default y
 	depends on DT_HAS_RASPBERRYPI_PICO_USBD_ENABLED
 	select SYS_MEM_BLOCKS
+	select EVENTS
+	imply PINCTRL
 	help
 	  Driver for an Raspberry PI Pico USB device controller.
 
diff --git a/drivers/usb/udc/Kconfig.skeleton b/drivers/usb/udc/Kconfig.skeleton
index bf7eb01323b..b6d96e0b895 100644
--- a/drivers/usb/udc/Kconfig.skeleton
+++ b/drivers/usb/udc/Kconfig.skeleton
@@ -5,6 +5,7 @@ config UDC_SKELETON
 	bool "Skeleton for an USB device controller driver"
 	default y
 	depends on DT_HAS_ZEPHYR_UDC_SKELETON_ENABLED
+	select UDC_DRIVER_HAS_HIGH_SPEED_SUPPORT
 	help
 	  Skeleton for an USB device controller driver.
 
diff --git a/drivers/usb/udc/Kconfig.stm32 b/drivers/usb/udc/Kconfig.stm32
index 3afe6b15e3f..2d7684469a9 100644
--- a/drivers/usb/udc/Kconfig.stm32
+++ b/drivers/usb/udc/Kconfig.stm32
@@ -13,3 +13,34 @@ config UDC_STM32
 	default y
 	help
 	  STM32 USB device controller driver.
+
+if UDC_STM32
+
+config UDC_STM32_STACK_SIZE
+	int "UDC controller driver internal thread stack size"
+	default 512
+	help
+	  STM32 USB device controller driver internal thread stack size.
+
+config UDC_STM32_THREAD_PRIORITY
+	int "STM32 USB controller driver thread priority"
+	default 8
+	help
+	  STM32 USB device controller driver thread priority.
+
+config UDC_STM32_MAX_QMESSAGES
+	int "STM32 UDC driver maximum number of ISR event messages"
+	range 4 64
+	default 8
+	help
+	  Maximum number of messages for handling of STM32 USBD ISR events.
+
+config UDC_STM32_CLOCK_CHECK
+	bool "Runtime USB 48MHz clock check"
+	default y if !(SOC_SERIES_STM32F1X || SOC_SERIES_STM32F3X || SOC_SERIES_STM32U5X)
+	help
+	  Enable USB clock 48MHz configuration runtime check.
+	  In specific cases, this check might provide wrong verdict and should
+	  be disabled.
+
+endif
diff --git a/drivers/usb/udc/Kconfig.virtual b/drivers/usb/udc/Kconfig.virtual
index b84e14ba971..7aff8ca8e20 100644
--- a/drivers/usb/udc/Kconfig.virtual
+++ b/drivers/usb/udc/Kconfig.virtual
@@ -6,6 +6,7 @@ config UDC_VIRTUAL
 	select UVB
 	default y
 	depends on DT_HAS_ZEPHYR_UDC_VIRTUAL_ENABLED
+	select UDC_DRIVER_HAS_HIGH_SPEED_SUPPORT
 	help
 	  Virtual USB device controller driver.
 
diff --git a/drivers/usb/udc/udc_ambiq.c b/drivers/usb/udc/udc_ambiq.c
index 11d26865df1..6e5f2603edd 100644
--- a/drivers/usb/udc/udc_ambiq.c
+++ b/drivers/usb/udc/udc_ambiq.c
@@ -5,7 +5,6 @@
  */
 
 #include <soc.h>
-#include "am_mcu_apollo.h"
 #include <string.h>
 #include <zephyr/drivers/clock_control/clock_control_ambiq.h>
 #include <zephyr/sys/util.h>
@@ -18,7 +17,6 @@
 #include <zephyr/logging/log.h>
 #include <zephyr/irq.h>
 #include "udc_common.h"
-#include <usb_dwc2_hw.h>
 
 LOG_MODULE_REGISTER(udc_ambiq, CONFIG_UDC_DRIVER_LOG_LEVEL);
 
@@ -408,16 +406,16 @@ static int udc_ambiq_test_mode(const struct device *dev, const uint8_t mode, con
 	struct udc_ambiq_data *priv = udc_get_private(dev);
 
 	switch (mode) {
-	case USB_DWC2_DCTL_TSTCTL_TESTJ:
+	case USB_SFS_TEST_MODE_J:
 		am_usb_test_mode = AM_HAL_USB_TEST_J;
 		break;
-	case USB_DWC2_DCTL_TSTCTL_TESTK:
+	case USB_SFS_TEST_MODE_K:
 		am_usb_test_mode = AM_HAL_USB_TEST_K;
 		break;
-	case USB_DWC2_DCTL_TSTCTL_TESTSN:
+	case USB_SFS_TEST_MODE_SE0_NAK:
 		am_usb_test_mode = AM_HAL_USB_TEST_SE0_NAK;
 		break;
-	case USB_DWC2_DCTL_TSTCTL_TESTPM:
+	case USB_SFS_TEST_MODE_PACKET:
 		am_usb_test_mode = AM_HAL_USB_TEST_PACKET;
 		break;
 	default:
diff --git a/drivers/usb/udc/udc_dwc2.c b/drivers/usb/udc/udc_dwc2.c
index 5920ae10b78..818bd691d58 100644
--- a/drivers/usb/udc/udc_dwc2.c
+++ b/drivers/usb/udc/udc_dwc2.c
@@ -105,9 +105,9 @@ struct udc_dwc2_data {
 	/* Main events the driver thread waits for */
 	struct k_event drv_evt;
 	/* Transfer triggers (IN on bits 0-15, OUT on bits 16-31) */
-	struct k_event xfer_new;
+	atomic_t xfer_new;
 	/* Finished transactions (IN on bits 0-15, OUT on bits 16-31) */
-	struct k_event xfer_finished;
+	atomic_t xfer_finished;
 	struct dwc2_reg_backup backup;
 	uint32_t ghwcfg1;
 	uint32_t max_xfersize;
@@ -404,7 +404,7 @@ static int dwc2_ctrl_feed_dout(const struct device *dev, const size_t length)
 	}
 
 	udc_buf_put(ep_cfg, buf);
-	k_event_post(&priv->xfer_new, BIT(16));
+	atomic_set_bit(&priv->xfer_new, 16);
 	k_event_post(&priv->drv_evt, BIT(DWC2_DRV_EVT_XFER));
 
 	return 0;
@@ -820,7 +820,7 @@ static int dwc2_handle_evt_setup(const struct device *dev)
 	 * transfer beforehand. In Buffer DMA the SETUP can be copied to any EP0
 	 * OUT buffer. If there is any buffer queued, it is obsolete now.
 	 */
-	k_event_clear(&priv->xfer_finished, BIT(0) | BIT(16));
+	atomic_and(&priv->xfer_finished, ~(BIT(0) | BIT(16)));
 
 	buf = udc_buf_get_all(cfg_out);
 	if (buf) {
@@ -1727,15 +1727,15 @@ static int udc_dwc2_ep_clear_halt(const struct device *dev,
 
 	/* Resume queued transfers if any */
 	if (udc_buf_peek(cfg)) {
-		uint32_t ep_bit;
+		int ep_bit;
 
 		if (USB_EP_DIR_IS_IN(cfg->addr)) {
-			ep_bit = BIT(USB_EP_GET_IDX(cfg->addr));
+			ep_bit = USB_EP_GET_IDX(cfg->addr);
 		} else {
-			ep_bit = BIT(16 + USB_EP_GET_IDX(cfg->addr));
+			ep_bit = 16 + USB_EP_GET_IDX(cfg->addr);
 		}
 
-		k_event_post(&priv->xfer_new, ep_bit);
+		atomic_set_bit(&priv->xfer_new, ep_bit);
 		k_event_post(&priv->drv_evt, BIT(DWC2_DRV_EVT_XFER));
 	}
 
@@ -1752,15 +1752,15 @@ static int udc_dwc2_ep_enqueue(const struct device *dev,
 	udc_buf_put(cfg, buf);
 
 	if (!cfg->stat.halted) {
-		uint32_t ep_bit;
+		int ep_bit;
 
 		if (USB_EP_DIR_IS_IN(cfg->addr)) {
-			ep_bit = BIT(USB_EP_GET_IDX(cfg->addr));
+			ep_bit = USB_EP_GET_IDX(cfg->addr);
 		} else {
-			ep_bit = BIT(16 + USB_EP_GET_IDX(cfg->addr));
+			ep_bit = 16 + USB_EP_GET_IDX(cfg->addr);
 		}
 
-		k_event_post(&priv->xfer_new, ep_bit);
+		atomic_set_bit(&priv->xfer_new, ep_bit);
 		k_event_post(&priv->drv_evt, BIT(DWC2_DRV_EVT_XFER));
 	}
 
@@ -2041,15 +2041,21 @@ static int udc_dwc2_init_controller(const struct device *dev)
 	case USB_DWC2_GHWCFG2_HSPHYTYPE_ULPI:
 		gusbcfg |= USB_DWC2_GUSBCFG_PHYSEL_USB20 |
 			   USB_DWC2_GUSBCFG_ULPI_UTMI_SEL_ULPI;
-		dcfg |= USB_DWC2_DCFG_DEVSPD_USBHS20
-			<< USB_DWC2_DCFG_DEVSPD_POS;
+		if (IS_ENABLED(CONFIG_UDC_DRIVER_HIGH_SPEED_SUPPORT_ENABLED)) {
+			dcfg |= usb_dwc2_set_dcfg_devspd(USB_DWC2_DCFG_DEVSPD_USBHS20);
+		} else {
+			dcfg |= usb_dwc2_set_dcfg_devspd(USB_DWC2_DCFG_DEVSPD_USBFS20);
+		}
 		hs_phy = true;
 		break;
 	case USB_DWC2_GHWCFG2_HSPHYTYPE_UTMIPLUS:
 		gusbcfg |= USB_DWC2_GUSBCFG_PHYSEL_USB20 |
 			   USB_DWC2_GUSBCFG_ULPI_UTMI_SEL_UTMI;
-		dcfg |= USB_DWC2_DCFG_DEVSPD_USBHS20
-			<< USB_DWC2_DCFG_DEVSPD_POS;
+		if (IS_ENABLED(CONFIG_UDC_DRIVER_HIGH_SPEED_SUPPORT_ENABLED)) {
+			dcfg |= usb_dwc2_set_dcfg_devspd(USB_DWC2_DCFG_DEVSPD_USBHS20);
+		} else {
+			dcfg |= usb_dwc2_set_dcfg_devspd(USB_DWC2_DCFG_DEVSPD_USBFS20);
+		}
 		hs_phy = true;
 		break;
 	case USB_DWC2_GHWCFG2_HSPHYTYPE_NO_HS:
@@ -2060,8 +2066,7 @@ static int udc_dwc2_init_controller(const struct device *dev)
 			gusbcfg |= USB_DWC2_GUSBCFG_PHYSEL_USB11;
 		}
 
-		dcfg |= USB_DWC2_DCFG_DEVSPD_USBFS1148
-			<< USB_DWC2_DCFG_DEVSPD_POS;
+		dcfg |= usb_dwc2_set_dcfg_devspd(USB_DWC2_DCFG_DEVSPD_USBFS1148);
 		hs_phy = false;
 	}
 
@@ -2291,8 +2296,8 @@ static int dwc2_driver_preinit(const struct device *dev)
 	k_mutex_init(&data->mutex);
 
 	k_event_init(&priv->drv_evt);
-	k_event_init(&priv->xfer_new);
-	k_event_init(&priv->xfer_finished);
+	atomic_clear(&priv->xfer_new);
+	atomic_clear(&priv->xfer_finished);
 
 	data->caps.rwup = true;
 	data->caps.addr_before_status = true;
@@ -2553,7 +2558,7 @@ static inline void dwc2_handle_in_xfercompl(const struct device *dev,
 		return;
 	}
 
-	k_event_post(&priv->xfer_finished, BIT(ep_idx));
+	atomic_set_bit(&priv->xfer_finished, ep_idx);
 	k_event_post(&priv->drv_evt, BIT(DWC2_DRV_EVT_EP_FINISHED));
 }
 
@@ -2659,7 +2664,7 @@ static inline void dwc2_handle_out_xfercompl(const struct device *dev,
 	    net_buf_tailroom(buf)) {
 		dwc2_prep_rx(dev, buf, ep_cfg);
 	} else {
-		k_event_post(&priv->xfer_finished, BIT(16 + ep_idx));
+		atomic_set_bit(&priv->xfer_finished, 16 + ep_idx);
 		k_event_post(&priv->drv_evt, BIT(DWC2_DRV_EVT_EP_FINISHED));
 	}
 }
@@ -2990,16 +2995,16 @@ static void dwc2_handle_hibernation_exit(const struct device *dev,
 
 	if (bus_reset) {
 		/* Clear all pending transfers */
-		k_event_clear(&priv->xfer_new, UINT32_MAX);
-		k_event_clear(&priv->xfer_finished, UINT32_MAX);
+		atomic_clear(&priv->xfer_new);
+		atomic_clear(&priv->xfer_finished);
 		dwc2_on_bus_reset(dev);
 	} else {
 		/* Resume any pending transfer handling */
-		if (k_event_test(&priv->xfer_new, UINT32_MAX)) {
+		if (atomic_get(&priv->xfer_new)) {
 			k_event_post(&priv->drv_evt, BIT(DWC2_DRV_EVT_XFER));
 		}
 
-		if (k_event_test(&priv->xfer_finished, UINT32_MAX)) {
+		if (atomic_get(&priv->xfer_finished)) {
 			k_event_post(&priv->drv_evt, BIT(DWC2_DRV_EVT_EP_FINISHED));
 		}
 	}
@@ -3054,7 +3059,7 @@ static ALWAYS_INLINE void dwc2_thread_handler(void *const arg)
 
 		if (!priv->hibernated) {
 			LOG_DBG("New transfer(s) in the queue");
-			eps = k_event_clear(&priv->xfer_new, UINT32_MAX);
+			eps = atomic_clear(&priv->xfer_new);
 		} else {
 			/* Events will be handled after hibernation exit */
 			eps = 0;
@@ -3076,7 +3081,7 @@ static ALWAYS_INLINE void dwc2_thread_handler(void *const arg)
 		k_event_clear(&priv->drv_evt, BIT(DWC2_DRV_EVT_EP_FINISHED));
 
 		if (!priv->hibernated) {
-			eps = k_event_clear(&priv->xfer_finished, UINT32_MAX);
+			eps = atomic_clear(&priv->xfer_finished);
 		} else {
 			/* Events will be handled after hibernation exit */
 			eps = 0;
diff --git a/drivers/usb/udc/udc_it82xx2.c b/drivers/usb/udc/udc_it82xx2.c
index fd00587dd65..85ec9431c63 100644
--- a/drivers/usb/udc/udc_it82xx2.c
+++ b/drivers/usb/udc/udc_it82xx2.c
@@ -1215,7 +1215,7 @@ static void xfer_work_handler(const struct device *dev)
 		}
 
 		if (evt.ep != USB_CONTROL_EP_OUT && !udc_ep_is_busy(ep_cfg)) {
-			if (work_handler_xfer_next(ep_cfg) == 0) {
+			if (work_handler_xfer_next(dev, ep_cfg) == 0) {
 				udc_ep_set_busy(ep_cfg, true);
 			}
 		}
diff --git a/drivers/usb/udc/udc_max32.c b/drivers/usb/udc/udc_max32.c
new file mode 100644
index 00000000000..1e09f5ef7c6
--- /dev/null
+++ b/drivers/usb/udc/udc_max32.c
@@ -0,0 +1,852 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "udc_common.h"
+
+#include <string.h>
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/usb/udc.h>
+
+#include <wrap_max32_usb.h>
+#include <zephyr/drivers/clock_control/adi_max32_clock_control.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(udc_max32, CONFIG_UDC_DRIVER_LOG_LEVEL);
+
+#define DT_DRV_COMPAT adi_max32_usbhs
+
+enum udc_max32_event_type {
+	/* Shim driver event to trigger transfer */
+	UDC_MAX32_EVT_XFER,
+	/* Setup event */
+	UDC_MAX32_EVT_SETUP,
+};
+
+struct udc_max32_evt {
+	enum udc_max32_event_type type;
+	struct udc_ep_config *ep_cfg;
+};
+
+K_MSGQ_DEFINE(drv_msgq, sizeof(struct udc_max32_evt), CONFIG_UDC_MAX32_MAX_QMESSAGES,
+	      sizeof(uint32_t));
+
+struct udc_max32_config {
+	mxc_usbhs_regs_t *base;
+	size_t num_of_in_eps;
+	size_t num_of_out_eps;
+	struct udc_ep_config *ep_cfg_in;
+	struct udc_ep_config *ep_cfg_out;
+	void (*make_thread)(const struct device *dev);
+	int speed_idx;
+	const struct device *clock;
+	struct max32_perclk perclk;
+	void (*irq_func)(void);
+};
+
+struct req_cb_data {
+	const struct device *dev;
+	uint8_t ep;
+};
+
+struct udc_max32_data {
+	struct k_thread thread_data;
+	MXC_USB_Req_t *ep_request;
+	struct req_cb_data *req_cb_data;
+};
+
+static void udc_event_xfer_ctrl_status(const struct device *dev, struct net_buf *const buf)
+{
+	if (udc_ctrl_stage_is_status_in(dev) || udc_ctrl_stage_is_no_data(dev)) {
+		MXC_USB_Ackstat(0);
+
+		/* Status stage finished, notify upper layer */
+		udc_ctrl_submit_status(dev, buf);
+	}
+
+	if (udc_ctrl_stage_is_data_in(dev)) {
+		/*
+		 * s-in-[status] finished, release buffer.
+		 * Since the controller supports auto-status we cannot use
+		 * if (udc_ctrl_stage_is_status_out()) after state update.
+		 */
+		net_buf_unref(buf);
+	}
+
+	/* Update to next stage of control transfer */
+	udc_ctrl_update_stage(dev, buf);
+}
+
+static void udc_event_xfer_in_callback(void *cbdata)
+{
+	struct req_cb_data *req_cb_data = (struct req_cb_data *)cbdata;
+	struct udc_max32_data *priv = udc_get_private(req_cb_data->dev);
+	MXC_USB_Req_t *ep_request = &priv->ep_request[USB_EP_GET_IDX(req_cb_data->ep)];
+	struct net_buf *buf;
+
+	buf = udc_buf_get(udc_get_ep_cfg(req_cb_data->dev, req_cb_data->ep));
+
+	udc_ep_set_busy(udc_get_ep_cfg(req_cb_data->dev, req_cb_data->ep), false);
+
+	if (ep_request->error_code) {
+		LOG_ERR("ep 0x%02x error: %x", req_cb_data->ep, ep_request->error_code);
+		udc_submit_ep_event(req_cb_data->dev, buf, ep_request->error_code);
+		return;
+	}
+
+	if (udc_ep_buf_has_zlp(buf)) {
+		udc_ep_buf_clear_zlp(buf);
+	}
+
+	if (req_cb_data->ep == USB_CONTROL_EP_IN) {
+		udc_event_xfer_ctrl_status(req_cb_data->dev, buf);
+	} else {
+		udc_submit_ep_event(req_cb_data->dev, buf, 0);
+	}
+}
+
+static void udc_event_xfer_out_callback(void *cbdata)
+{
+	struct req_cb_data *req_cb_data = (struct req_cb_data *)cbdata;
+	struct udc_max32_data *priv = udc_get_private(req_cb_data->dev);
+	MXC_USB_Req_t *ep_request = &priv->ep_request[USB_EP_GET_IDX(req_cb_data->ep)];
+	struct net_buf *buf;
+
+	buf = udc_buf_get(udc_get_ep_cfg(req_cb_data->dev, req_cb_data->ep));
+	net_buf_add(buf, ep_request->actlen);
+
+	udc_ep_set_busy(udc_get_ep_cfg(req_cb_data->dev, req_cb_data->ep), false);
+
+	if (ep_request->error_code) {
+		LOG_ERR("ep 0x%02x error: %x", req_cb_data->ep, ep_request->error_code);
+		udc_submit_ep_event(req_cb_data->dev, buf, ep_request->error_code);
+		return;
+	}
+
+	if (req_cb_data->ep == USB_CONTROL_EP_OUT) {
+		/* Update to next stage of control transfer */
+		udc_ctrl_update_stage(req_cb_data->dev, buf);
+
+		udc_ctrl_submit_s_out_status(req_cb_data->dev, buf);
+	} else {
+		udc_submit_ep_event(req_cb_data->dev, buf, 0);
+	}
+}
+
+static void udc_event_xfer_in(const struct device *dev, struct udc_ep_config *ep_cfg)
+{
+	struct udc_max32_data *priv = udc_get_private(dev);
+	MXC_USB_Req_t *ep_request = &priv->ep_request[USB_EP_GET_IDX(ep_cfg->addr)];
+	struct req_cb_data *req_cb_data = &priv->req_cb_data[USB_EP_GET_IDX(ep_cfg->addr)];
+	struct net_buf *buf;
+	int ret;
+
+	if (udc_ep_is_busy(ep_cfg)) {
+		return;
+	}
+
+	memset(ep_request, 0, sizeof(MXC_USB_Req_t));
+
+	buf = udc_buf_peek(ep_cfg);
+	if (buf == NULL) {
+		LOG_ERR("Failed to peek net_buf for ep 0x%02x", ep_cfg->addr);
+		return;
+	}
+
+	if (buf->len == 0 && ep_cfg->addr == USB_CONTROL_EP_IN) {
+		buf = udc_buf_get(ep_cfg);
+		udc_event_xfer_ctrl_status(dev, buf);
+		return;
+	}
+
+	req_cb_data->dev = dev;
+	req_cb_data->ep = ep_cfg->addr;
+
+	ep_request->ep = USB_EP_GET_IDX(ep_cfg->addr);
+	ep_request->data = buf->data;
+	ep_request->reqlen = buf->len;
+	ep_request->actlen = 0;
+	ep_request->error_code = 0;
+	ep_request->callback = udc_event_xfer_in_callback;
+	ep_request->cbdata = req_cb_data;
+	if (udc_ep_buf_has_zlp(buf)) {
+		ep_request->has_zlp = true;
+	}
+
+	udc_ep_set_busy(ep_cfg, true);
+	ret = MXC_USB_WriteEndpoint(ep_request);
+	if (ret != 0) {
+		udc_ep_set_busy(ep_cfg, false);
+		LOG_ERR("ep 0x%02x error: %x", ep_cfg->addr, ret);
+		udc_submit_ep_event(dev, buf, -ECONNREFUSED);
+	}
+}
+
+static void udc_event_xfer_out(const struct device *dev, struct udc_ep_config *ep_cfg)
+{
+	struct udc_max32_data *priv = udc_get_private(dev);
+	MXC_USB_Req_t *ep_request = &priv->ep_request[USB_EP_GET_IDX(ep_cfg->addr)];
+	struct req_cb_data *req_cb_data = &priv->req_cb_data[USB_EP_GET_IDX(ep_cfg->addr)];
+	struct net_buf *buf;
+	int ret;
+
+	if (udc_ep_is_busy(ep_cfg)) {
+		return;
+	}
+
+	buf = udc_buf_peek(ep_cfg);
+	if (buf == NULL) {
+		LOG_ERR("Failed to peek net_buf for ep 0x%02x", ep_cfg->addr);
+		return;
+	}
+
+	req_cb_data->dev = dev;
+	req_cb_data->ep = ep_cfg->addr;
+
+	ep_request->ep = USB_EP_GET_IDX(ep_cfg->addr);
+	ep_request->data = buf->data;
+	ep_request->reqlen = buf->size;
+	ep_request->actlen = 0;
+	ep_request->error_code = 0;
+	ep_request->callback = udc_event_xfer_out_callback;
+	ep_request->cbdata = req_cb_data;
+	ep_request->type = MAXUSB_TYPE_PKT;
+
+	udc_ep_set_busy(ep_cfg, true);
+	ret = MXC_USB_ReadEndpoint(ep_request);
+	if (ret != 0) {
+		udc_ep_set_busy(ep_cfg, false);
+		LOG_ERR("ep 0x%02x error: %x", ep_cfg->addr, ret);
+		udc_submit_ep_event(dev, buf, -ECONNREFUSED);
+	}
+}
+
+static int udc_ctrl_feed_dout(const struct device *dev, const size_t length)
+{
+	struct udc_max32_data *priv = udc_get_private(dev);
+	const struct udc_max32_config *config = dev->config;
+	MXC_USB_Req_t *ep_request = &priv->ep_request[USB_EP_GET_IDX(USB_CONTROL_EP_OUT)];
+	struct req_cb_data *req_cb_data = &priv->req_cb_data[USB_EP_GET_IDX(USB_CONTROL_EP_OUT)];
+	struct net_buf *buf;
+	int ret;
+
+	/* Allocate buffer for data stage OUT */
+	buf = udc_ctrl_alloc(dev, USB_CONTROL_EP_OUT, length);
+	if (buf == NULL) {
+		return -ENOMEM;
+	}
+	memset(buf->data, 0, length);
+	udc_buf_put(udc_get_ep_cfg(dev, USB_CONTROL_EP_OUT), buf);
+
+	req_cb_data->dev = dev;
+	req_cb_data->ep = USB_CONTROL_EP_OUT;
+
+	ep_request->ep = USB_EP_GET_IDX(USB_CONTROL_EP_OUT);
+	ep_request->data = buf->data;
+	ep_request->reqlen = length;
+	ep_request->actlen = 0;
+	ep_request->error_code = 0;
+	ep_request->callback = udc_event_xfer_out_callback;
+	ep_request->cbdata = req_cb_data;
+	ep_request->type = MAXUSB_TYPE_TRANS;
+
+	ret = MXC_USB_ReadEndpoint(ep_request);
+	if (ret != 0) {
+		LOG_ERR("ep 0x%02x error: %x", USB_CONTROL_EP_OUT, ret);
+		udc_submit_ep_event(dev, buf, -ECONNREFUSED);
+	}
+
+	/*
+	 * Set the SERV_OUTPKTRDY bit to trigger the interrupt after creating a read request.
+	 * Otherwise program miss this interrupt because of race condition.
+	 */
+	config->base->csr0 |= MXC_F_USBHS_CSR0_SERV_OUTPKTRDY;
+
+	return ret;
+}
+
+static int udc_event_setup(const struct device *dev)
+{
+	const struct udc_max32_config *config = dev->config;
+	struct net_buf *buf;
+	int ret;
+
+	buf = udc_ctrl_alloc(dev, USB_CONTROL_EP_OUT, sizeof(struct usb_setup_packet));
+	if (buf == NULL) {
+		LOG_ERR("Failed to allocate for setup");
+		return -ENOMEM;
+	}
+
+	udc_ep_buf_set_setup(buf);
+	memset(buf->data, 0, sizeof(MXC_USB_SetupPkt));
+	if (MXC_USB_GetSetup((MXC_USB_SetupPkt *)buf->data) < 0) {
+		LOG_ERR("Failed to get setup data");
+		return -1;
+	}
+	net_buf_add(buf, sizeof(MXC_USB_SetupPkt));
+
+	/* Update to next stage of control transfer */
+	udc_ctrl_update_stage(dev, buf);
+
+	if (udc_ctrl_stage_is_data_out(dev)) {
+		/*  Allocate and feed buffer for data OUT stage */
+		LOG_DBG("s:%p|feed for -out-", buf);
+		ret = udc_ctrl_feed_dout(dev, udc_data_stage_length(buf));
+		if (ret == -ENOMEM) {
+			ret = udc_submit_ep_event(dev, buf, ret);
+		}
+	} else if (udc_ctrl_stage_is_data_in(dev)) {
+		/*
+		 * Moved following line from MSDK driver to here because of the solution of
+		 * ctrl_data_out stage's problem.
+		 */
+		config->base->csr0 |= MXC_F_USBHS_CSR0_SERV_OUTPKTRDY;
+		LOG_INF("Setup: IN");
+		ret = udc_ctrl_submit_s_in_status(dev);
+	} else {
+		ret = udc_ctrl_submit_s_status(dev);
+	}
+
+	return ret;
+}
+
+static ALWAYS_INLINE void max32_thread_handler(void *const arg)
+{
+	const struct device *dev = (const struct device *)arg;
+
+	LOG_DBG("Driver %p thread started", dev);
+	while (true) {
+		bool start_xfer = false;
+		struct udc_max32_evt evt;
+
+		k_msgq_get(&drv_msgq, &evt, K_FOREVER);
+
+		switch (evt.type) {
+		case UDC_MAX32_EVT_SETUP:
+			udc_event_setup(dev);
+			break;
+		case UDC_MAX32_EVT_XFER:
+			start_xfer = true;
+			break;
+		default:
+			break;
+		}
+
+		if (start_xfer) {
+			if (USB_EP_DIR_IS_IN(evt.ep_cfg->addr)) {
+				udc_event_xfer_in(dev, evt.ep_cfg);
+			} else {
+				udc_event_xfer_out(dev, evt.ep_cfg);
+			}
+		}
+	}
+}
+
+static int udc_max32_ep_enqueue(const struct device *dev, struct udc_ep_config *const cfg,
+				struct net_buf *buf)
+{
+	struct udc_max32_evt evt = {
+		.type = UDC_MAX32_EVT_XFER,
+		.ep_cfg = cfg,
+	};
+
+	LOG_DBG("%p enqueue %p", dev, buf);
+	udc_buf_put(cfg, buf);
+
+	if (cfg->stat.halted) {
+		LOG_DBG("ep 0x%02x halted", cfg->addr);
+		return 0;
+	}
+
+	k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
+
+	return 0;
+}
+
+static int udc_max32_ep_dequeue(const struct device *dev, struct udc_ep_config *const cfg)
+{
+	unsigned int lock_key;
+	struct net_buf *buf;
+
+	lock_key = irq_lock();
+
+	buf = udc_buf_get_all(cfg);
+	if (buf) {
+		udc_submit_ep_event(dev, buf, -ECONNABORTED);
+	} else {
+		LOG_INF("ep 0x%02x queue is empty", cfg->addr);
+	}
+
+	irq_unlock(lock_key);
+
+	return 0;
+}
+
+static int udc_max32_ep_enable(const struct device *dev, struct udc_ep_config *const cfg)
+{
+	maxusb_ep_type_t ep_type;
+	int ret;
+
+	if (USB_EP_GET_IDX(cfg->addr) == 0) {
+		return 0;
+	}
+
+	if (cfg->caps.in) {
+		ep_type = MAXUSB_EP_TYPE_IN;
+	} else if (cfg->caps.out) {
+		ep_type = MAXUSB_EP_TYPE_OUT;
+	} else {
+		LOG_ERR("ep 0x%02x is not IN or OUT", cfg->addr);
+		return -ENODEV;
+	}
+
+	ret = MXC_USB_ConfigEp(USB_EP_GET_IDX(cfg->addr), ep_type, cfg->mps);
+	if (ret != 0) {
+		LOG_ERR("Failed to configure ep 0x%02x", cfg->addr);
+		return ret;
+	}
+
+	return 0;
+}
+
+static int udc_max32_ep_disable(const struct device *dev, struct udc_ep_config *const cfg)
+{
+	int ret;
+
+	if (USB_EP_GET_IDX(cfg->addr) == 0) {
+		return 0;
+	}
+
+	ret = MXC_USB_ResetEp(USB_EP_GET_IDX(cfg->addr));
+
+	return ret;
+}
+
+static int udc_max32_ep_set_halt(const struct device *dev, struct udc_ep_config *const cfg)
+{
+	int ret;
+
+	if (cfg->stat.halted == true) {
+		LOG_WRN("ep 0x%02x is already as halt", cfg->addr);
+		return 0;
+	}
+
+	LOG_DBG("Set halt ep 0x%02x", cfg->addr);
+
+	ret = MXC_USB_Stall(USB_EP_GET_IDX(cfg->addr));
+	if (ret != 0) {
+		LOG_ERR("Failed to set halt ep 0x%02x", cfg->addr);
+		return ret;
+	}
+
+	cfg->stat.halted = true;
+
+	return 0;
+}
+
+static int udc_max32_ep_clear_halt(const struct device *dev, struct udc_ep_config *const cfg)
+{
+	int ret;
+
+	if (cfg->stat.halted == false) {
+		LOG_WRN("ep 0x%02x is not set as halt, no need to clear halt.", cfg->addr);
+		return 0;
+	}
+
+	LOG_DBG("Clear halt ep 0x%02x", cfg->addr);
+
+	ret = MXC_USB_Unstall(USB_EP_GET_IDX(cfg->addr));
+	if (ret != 0) {
+		LOG_ERR("Failed to clear halt ep 0x%02x", cfg->addr);
+		return ret;
+	}
+
+	cfg->stat.halted = false;
+
+	/* If there is a request for this endpoint, enqueue the request. */
+	if (udc_buf_peek(cfg) != NULL) {
+		struct udc_max32_evt evt = {
+			.type = UDC_MAX32_EVT_XFER,
+			.ep_cfg = cfg,
+		};
+
+		k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
+	}
+
+	return 0;
+}
+
+static int udc_max32_set_address(const struct device *dev, const uint8_t addr)
+{
+	int ret;
+
+	LOG_DBG("Set new address %u for %p", addr, dev);
+
+	ret = MXC_USB_SetFuncAddr(addr);
+	if (ret != 0) {
+		LOG_ERR("Failed to set device address %u", addr);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int udc_max32_host_wakeup(const struct device *dev)
+{
+	LOG_DBG("Remote wakeup from %p", dev);
+
+	MXC_USB_RemoteWakeup();
+
+	return 0;
+}
+
+static enum udc_bus_speed udc_max32_device_speed(const struct device *dev)
+{
+	struct udc_data *data = dev->data;
+
+	return data->caps.hs ? UDC_BUS_SPEED_HS : UDC_BUS_SPEED_FS;
+}
+
+static int udc_max32_event_callback(maxusb_event_t event, void *cbdata)
+{
+	const struct device *dev = (const struct device *)cbdata;
+
+	switch (event) {
+	case MAXUSB_EVENT_NOVBUS:
+		LOG_DBG("NOVBUS event occurred");
+		udc_submit_event(dev, UDC_EVT_VBUS_REMOVED, 0);
+		break;
+	case MAXUSB_EVENT_VBUS:
+		LOG_DBG("VBUS event occurred");
+		udc_submit_event(dev, UDC_EVT_VBUS_READY, 0);
+		break;
+	case MAXUSB_EVENT_SUSP:
+		LOG_DBG("SUSP event occurred");
+		udc_set_suspended(dev, true);
+		udc_submit_event(dev, UDC_EVT_SUSPEND, 0);
+		break;
+	case MAXUSB_EVENT_DPACT:
+		LOG_DBG("DPACT event occurred");
+		udc_set_suspended(dev, false);
+		udc_submit_event(dev, UDC_EVT_SOF, 0);
+		break;
+	case MAXUSB_EVENT_BRST:
+		LOG_DBG("BRST event occurred");
+		udc_set_suspended(dev, false);
+		udc_submit_event(dev, UDC_EVT_RESET, 0);
+		break;
+	case MAXUSB_EVENT_SUDAV:
+		LOG_DBG("SUDAV event occurred");
+		struct udc_max32_evt evt = {
+			.type = UDC_MAX32_EVT_SETUP,
+			.ep_cfg = udc_get_ep_cfg(dev, USB_CONTROL_EP_OUT),
+		};
+
+		k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int udc_max32_enable(const struct device *dev)
+{
+	int ret;
+
+	LOG_DBG("Enable device %p", dev);
+
+	MXC_USB_EventClear(MAXUSB_EVENT_SUDAV);
+	ret = MXC_USB_EventEnable(MAXUSB_EVENT_SUDAV, udc_max32_event_callback, (void *)dev);
+	if (ret != 0) {
+		LOG_ERR("Failed to enable SUDAV event.");
+		return ret;
+	}
+
+	MXC_USB_EventClear(MAXUSB_EVENT_SUSP);
+	ret = MXC_USB_EventEnable(MAXUSB_EVENT_SUSP, udc_max32_event_callback, (void *)dev);
+	if (ret != 0) {
+		LOG_ERR("Failed to enable SUSP event.");
+		return ret;
+	}
+
+	MXC_USB_EventClear(MAXUSB_EVENT_DPACT);
+	ret = MXC_USB_EventEnable(MAXUSB_EVENT_DPACT, udc_max32_event_callback, (void *)dev);
+	if (ret != 0) {
+		LOG_ERR("Failed to enable DPACT event.");
+		return ret;
+	}
+
+	MXC_USB_EventClear(MAXUSB_EVENT_BRST);
+	ret = MXC_USB_EventEnable(MAXUSB_EVENT_BRST, udc_max32_event_callback, (void *)dev);
+	if (ret != 0) {
+		LOG_ERR("Failed to enable BRST event.");
+		return ret;
+	}
+
+	ret = MXC_USB_Connect();
+
+	return ret;
+}
+
+static int udc_max32_disable(const struct device *dev)
+{
+	int ret;
+
+	LOG_DBG("Disable device %p", dev);
+	ret = MXC_USB_Disconnect();
+
+	return ret;
+}
+
+static void udc_max32_delay_us(unsigned int usec)
+{
+	k_usleep(usec);
+}
+
+static int udc_max32_init(const struct device *dev)
+{
+	const struct udc_max32_config *config = dev->config;
+	struct udc_data *data = dev->data;
+	maxusb_cfg_options_t usb_opts;
+	int ret;
+
+	if (data->caps.hs) {
+		usb_opts.enable_hs = 1;
+	}
+	usb_opts.delay_us = udc_max32_delay_us;
+	usb_opts.init_callback = NULL;
+	usb_opts.shutdown_callback = NULL;
+
+	/* Enable clock */
+	ret = clock_control_on(config->clock, (clock_control_subsys_t)&config->perclk);
+	if (ret != 0) {
+		LOG_ERR("Failed to enable USB peripheral clock");
+		return ret;
+	}
+
+	MXC_SYS_Reset_Periph(MXC_SYS_RESET0_USB);
+
+	ret = Wrap_MXC_USB_Init(&usb_opts);
+	if (ret != 0) {
+		LOG_ERR("Failed to initialize USB.");
+		return ret;
+	}
+
+	ret = MXC_USB_EventEnable(MAXUSB_EVENT_NOVBUS, udc_max32_event_callback, (void *)dev);
+	if (ret != 0) {
+		LOG_ERR("Failed to enable NOVBUS event.");
+		return ret;
+	}
+	ret = MXC_USB_EventEnable(MAXUSB_EVENT_VBUS, udc_max32_event_callback, (void *)dev);
+	if (ret != 0) {
+		LOG_ERR("Failed to enable VBUS event.");
+		return ret;
+	}
+
+	if (udc_ep_enable_internal(dev, USB_CONTROL_EP_OUT, USB_EP_TYPE_CONTROL, 64, 0)) {
+		LOG_ERR("Failed to enable control endpoint");
+		return -EIO;
+	}
+
+	if (udc_ep_enable_internal(dev, USB_CONTROL_EP_IN, USB_EP_TYPE_CONTROL, 64, 0)) {
+		LOG_ERR("Failed to enable control endpoint");
+		return -EIO;
+	}
+
+	config->irq_func(); /* UDC IRQ enable*/
+
+	return 0;
+}
+
+static int udc_max32_shutdown(const struct device *dev)
+{
+	MXC_USB_Shutdown();
+	irq_disable(DT_INST_IRQN(0));
+
+	if (udc_ep_disable_internal(dev, USB_CONTROL_EP_OUT)) {
+		LOG_ERR("Failed to disable control endpoint");
+		return -EIO;
+	}
+
+	if (udc_ep_disable_internal(dev, USB_CONTROL_EP_IN)) {
+		LOG_ERR("Failed to disable control endpoint");
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int udc_max32_driver_preinit(const struct device *dev)
+{
+	const struct udc_max32_config *config = dev->config;
+	struct udc_data *data = dev->data;
+	uint16_t mps = 64;
+	int ret;
+
+	k_mutex_init(&data->mutex);
+
+	data->caps.rwup = true;
+	data->caps.can_detect_vbus = true;
+	data->caps.out_ack = true;
+	data->caps.mps0 = UDC_MPS0_64;
+	if (config->speed_idx == 2) {
+		data->caps.hs = true;
+		mps = 512;
+	}
+
+	for (int i = 0; i < config->num_of_out_eps; i++) {
+		config->ep_cfg_out[i].caps.out = 1;
+		if (i == 0) {
+			config->ep_cfg_out[i].caps.control = 1;
+			config->ep_cfg_out[i].caps.mps = 64;
+		} else {
+			config->ep_cfg_out[i].caps.bulk = 1;
+			config->ep_cfg_out[i].caps.interrupt = 1;
+			config->ep_cfg_out[i].caps.iso = 1;
+			config->ep_cfg_out[i].caps.mps = mps;
+		}
+
+		config->ep_cfg_out[i].addr = USB_EP_DIR_OUT | i;
+		ret = udc_register_ep(dev, &config->ep_cfg_out[i]);
+		if (ret != 0) {
+			LOG_ERR("Failed to register endpoint");
+			return ret;
+		}
+	}
+
+	for (int i = 0; i < config->num_of_in_eps; i++) {
+		config->ep_cfg_in[i].caps.in = 1;
+		if (i == 0) {
+			config->ep_cfg_in[i].caps.control = 1;
+			config->ep_cfg_in[i].caps.mps = 64;
+			config->ep_cfg_in[i].addr = USB_EP_DIR_IN | i;
+		} else {
+			config->ep_cfg_in[i].caps.bulk = 1;
+			config->ep_cfg_in[i].caps.interrupt = 1;
+			config->ep_cfg_in[i].caps.iso = 1;
+			config->ep_cfg_in[i].caps.mps = mps;
+			/* Set different endpoint indexes from out endpoints */
+			config->ep_cfg_in[i].addr =
+				USB_EP_DIR_IN | (config->num_of_out_eps + i - 1);
+		}
+
+		ret = udc_register_ep(dev, &config->ep_cfg_in[i]);
+		if (ret != 0) {
+			LOG_ERR("Failed to register endpoint");
+			return ret;
+		}
+	}
+
+	config->make_thread(dev);
+	LOG_INF("Device %p (max. speed %d)", dev, config->speed_idx);
+
+	return 0;
+}
+
+static void udc_max32_isr(const struct device *dev)
+{
+	MXC_USB_EventHandler();
+}
+
+static void udc_max32_lock(const struct device *dev)
+{
+	udc_lock_internal(dev, K_FOREVER);
+}
+
+static void udc_max32_unlock(const struct device *dev)
+{
+	udc_unlock_internal(dev);
+}
+
+static const struct udc_api udc_max32_api = {
+	.lock = udc_max32_lock,
+	.unlock = udc_max32_unlock,
+	.device_speed = udc_max32_device_speed,
+	.init = udc_max32_init,
+	.enable = udc_max32_enable,
+	.disable = udc_max32_disable,
+	.shutdown = udc_max32_shutdown,
+	.set_address = udc_max32_set_address,
+	.host_wakeup = udc_max32_host_wakeup,
+	.ep_enable = udc_max32_ep_enable,
+	.ep_disable = udc_max32_ep_disable,
+	.ep_set_halt = udc_max32_ep_set_halt,
+	.ep_clear_halt = udc_max32_ep_clear_halt,
+	.ep_enqueue = udc_max32_ep_enqueue,
+	.ep_dequeue = udc_max32_ep_dequeue,
+};
+
+#define UDC_MAX32_DEVICE_DEFINE(n)                                                                 \
+	static void udc_max32_irq_init_##n(void)                                                   \
+	{                                                                                          \
+		IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), udc_max32_isr,              \
+			    DEVICE_DT_INST_GET(n), 0);                                             \
+		irq_enable(DT_INST_IRQN(n));                                                       \
+	}                                                                                          \
+                                                                                                   \
+	K_THREAD_STACK_DEFINE(udc_max32_stack_##n, CONFIG_UDC_MAX32_THREAD_STACK_SIZE);            \
+                                                                                                   \
+	static void udc_max32_thread_##n(void *dev, void *arg1, void *arg2)                        \
+	{                                                                                          \
+		ARG_UNUSED(arg1);                                                                  \
+		ARG_UNUSED(arg2);                                                                  \
+		max32_thread_handler(dev);                                                         \
+	}                                                                                          \
+                                                                                                   \
+	static void udc_max32_make_thread_##n(const struct device *dev)                            \
+	{                                                                                          \
+		struct udc_max32_data *priv = udc_get_private(dev);                                \
+                                                                                                   \
+		k_thread_create(&priv->thread_data, udc_max32_stack_##n,                           \
+				K_THREAD_STACK_SIZEOF(udc_max32_stack_##n), udc_max32_thread_##n,  \
+				(void *)dev, NULL, NULL,                                           \
+				K_PRIO_COOP(CONFIG_UDC_MAX32_THREAD_PRIORITY), K_ESSENTIAL,        \
+				K_NO_WAIT);                                                        \
+		k_thread_name_set(&priv->thread_data, dev->name);                                  \
+	}                                                                                          \
+                                                                                                   \
+	static struct udc_ep_config ep_cfg_out_##n[DT_INST_PROP(n, num_out_endpoints)];            \
+	static struct udc_ep_config ep_cfg_in_##n[DT_INST_PROP(n, num_in_endpoints)];              \
+                                                                                                   \
+	static const struct udc_max32_config udc_max32_config_##n = {                              \
+		.base = (mxc_usbhs_regs_t *)DT_INST_REG_ADDR(n),                                   \
+		.num_of_in_eps = DT_INST_PROP(n, num_out_endpoints),                               \
+		.num_of_out_eps = DT_INST_PROP(n, num_in_endpoints),                               \
+		.ep_cfg_in = ep_cfg_out_##n,                                                       \
+		.ep_cfg_out = ep_cfg_in_##n,                                                       \
+		.make_thread = udc_max32_make_thread_##n,                                          \
+		.speed_idx = DT_ENUM_IDX(DT_DRV_INST(n), maximum_speed),                           \
+		.clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),                                    \
+		.perclk.bus = DT_INST_CLOCKS_CELL(n, offset),                                      \
+		.perclk.bit = DT_INST_CLOCKS_CELL(n, bit),                                         \
+		.irq_func = &udc_max32_irq_init_##n,                                               \
+	};                                                                                         \
+                                                                                                   \
+	static MXC_USB_Req_t ep_request_##n[DT_INST_PROP(n, num_out_endpoints) +                   \
+					    DT_INST_PROP(n, num_in_endpoints) - 1];                \
+                                                                                                   \
+	static struct req_cb_data req_cb_data_##n[DT_INST_PROP(n, num_out_endpoints) +             \
+						  DT_INST_PROP(n, num_in_endpoints) - 1];          \
+                                                                                                   \
+	static struct udc_max32_data udc_priv_##n = {                                              \
+		.ep_request = ep_request_##n,                                                      \
+		.req_cb_data = req_cb_data_##n,                                                    \
+	};                                                                                         \
+                                                                                                   \
+	static struct udc_data udc_data_##n = {                                                    \
+		.mutex = Z_MUTEX_INITIALIZER(udc_data_##n.mutex),                                  \
+		.priv = &udc_priv_##n,                                                             \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(n, udc_max32_driver_preinit, NULL, &udc_data_##n,                    \
+			      &udc_max32_config_##n, POST_KERNEL,                                  \
+			      CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &udc_max32_api);
+
+DT_INST_FOREACH_STATUS_OKAY(UDC_MAX32_DEVICE_DEFINE)
diff --git a/drivers/usb/udc/udc_mcux_ehci.c b/drivers/usb/udc/udc_mcux_ehci.c
index fc5f65b7644..0feda0bd414 100644
--- a/drivers/usb/udc/udc_mcux_ehci.c
+++ b/drivers/usb/udc/udc_mcux_ehci.c
@@ -360,7 +360,7 @@ static bool udc_mcux_handler_zlt(const struct device *dev, uint8_t ep, struct ne
 			usb_status_t status;
 
 			udc_ep_buf_clear_zlp(buf);
-			status = mcux_if->deviceRecv(priv->mcux_device.controllerHandle,
+			status = mcux_if->deviceSend(priv->mcux_device.controllerHandle,
 					ep, NULL, 0);
 			if (status != kStatus_USB_Success) {
 				udc_submit_event(dev, UDC_EVT_ERROR, -EIO);
diff --git a/drivers/usb/udc/udc_mcux_ip3511.c b/drivers/usb/udc/udc_mcux_ip3511.c
index 564f2f9357b..312acae1784 100644
--- a/drivers/usb/udc/udc_mcux_ip3511.c
+++ b/drivers/usb/udc/udc_mcux_ip3511.c
@@ -360,7 +360,7 @@ static bool udc_mcux_handler_zlt(const struct device *dev, uint8_t ep, struct ne
 			usb_status_t status;
 
 			udc_ep_buf_clear_zlp(buf);
-			status = mcux_if->deviceRecv(priv->mcux_device.controllerHandle,
+			status = mcux_if->deviceSend(priv->mcux_device.controllerHandle,
 					ep, NULL, 0);
 			if (status != kStatus_USB_Success) {
 				udc_submit_event(dev, UDC_EVT_ERROR, -EIO);
diff --git a/drivers/usb/udc/udc_nrf.c b/drivers/usb/udc/udc_nrf.c
index 8e43313bd19..71eebbd70d3 100644
--- a/drivers/usb/udc/udc_nrf.c
+++ b/drivers/usb/udc/udc_nrf.c
@@ -4,75 +4,1160 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/**
- * @file  udc_nrf.c
- * @brief Nordic USB device controller (UDC) driver
+#include <string.h>
+#include <stdio.h>
+#include <soc.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/usb/udc.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/nrf_clock_control.h>
+#include <zephyr/dt-bindings/regulator/nrf5x.h>
+
+#include <nrf_usbd_common.h>
+#include <nrf_usbd_common_errata.h>
+#include <hal/nrf_usbd.h>
+#include <nrfx_power.h>
+#include "udc_common.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(udc_nrf, CONFIG_UDC_DRIVER_LOG_LEVEL);
+
+/*
+ * There is no real advantage to change control endpoint size
+ * but we can use it for testing UDC driver API and higher layers.
+ */
+#define UDC_NRF_MPS0		UDC_MPS0_64
+#define UDC_NRF_EP0_SIZE	64
+
+enum udc_nrf_event_type {
+	/* Trigger next transfer (buffer enqueued) */
+	UDC_NRF_EVT_XFER,
+	/* Transfer finished */
+	UDC_NRF_EVT_EP_FINISHED,
+	/* SETUP data received */
+	UDC_NRF_EVT_SETUP,
+	/* USB bus suspended */
+	UDC_NRF_EVT_SUSPEND,
+	/* USB bus resumed */
+	UDC_NRF_EVT_RESUME,
+	/* Remote Wakeup initiated */
+	UDC_NRF_EVT_WUREQ,
+	/* Let controller perform status stage */
+	UDC_NRF_EVT_STATUS_IN,
+};
+
+/* Main events the driver thread waits for */
+static K_EVENT_DEFINE(drv_evt);
+/* Transfer triggers */
+static atomic_t xfer_new;
+/* Finished transactions */
+static atomic_t xfer_finished;
+
+static K_KERNEL_STACK_DEFINE(drv_stack, CONFIG_UDC_NRF_THREAD_STACK_SIZE);
+static struct k_thread drv_stack_data;
+
+/* USB device controller access from devicetree */
+#define DT_DRV_COMPAT nordic_nrf_usbd
+
+#define CFG_EPIN_CNT		DT_INST_PROP(0, num_in_endpoints)
+#define CFG_EPOUT_CNT		DT_INST_PROP(0, num_out_endpoints)
+#define CFG_EP_ISOIN_CNT	DT_INST_PROP(0, num_isoin_endpoints)
+#define CFG_EP_ISOOUT_CNT	DT_INST_PROP(0, num_isoout_endpoints)
+
+static struct udc_ep_config ep_cfg_out[CFG_EPOUT_CNT + CFG_EP_ISOOUT_CNT + 1];
+static struct udc_ep_config ep_cfg_in[CFG_EPIN_CNT + CFG_EP_ISOIN_CNT + 1];
+static bool udc_nrf_setup_set_addr, udc_nrf_fake_setup;
+static uint8_t udc_nrf_address;
+const static struct device *udc_nrf_dev;
+
+#define NRF_USBD_COMMON_EPIN_CNT      9
+#define NRF_USBD_COMMON_EPOUT_CNT     9
+#define NRF_USBD_COMMON_EP_NUM(ep)    (ep & 0xF)
+#define NRF_USBD_COMMON_EP_IS_IN(ep)  ((ep & 0x80) == 0x80)
+#define NRF_USBD_COMMON_EP_IS_OUT(ep) ((ep & 0x80) == 0)
+#define NRF_USBD_COMMON_EP_IS_ISO(ep) ((ep & 0xF) >= 8)
+
+#ifndef NRF_USBD_COMMON_ISO_DEBUG
+/* Also generate information about ISOCHRONOUS events and transfers.
+ * Turn this off if no ISOCHRONOUS transfers are going to be debugged and this
+ * option generates a lot of useless messages.
+ */
+#define NRF_USBD_COMMON_ISO_DEBUG 1
+#endif
+
+#ifndef NRF_USBD_COMMON_USE_WORKAROUND_FOR_ANOMALY_211
+/* Anomaly 211 - Device remains in SUSPEND too long when host resumes
+ * a bus activity (sending SOF packets) without a RESUME condition.
+ */
+#define NRF_USBD_COMMON_USE_WORKAROUND_FOR_ANOMALY_211 0
+#endif
+
+/* Assert endpoint is valid */
+#define NRF_USBD_COMMON_ASSERT_EP_VALID(ep) __ASSERT_NO_MSG(         \
+	((NRF_USBD_COMMON_EP_IS_IN(ep) &&                            \
+	 (NRF_USBD_COMMON_EP_NUM(ep) < NRF_USBD_COMMON_EPIN_CNT)) || \
+	 (NRF_USBD_COMMON_EP_IS_OUT(ep) &&                           \
+	 (NRF_USBD_COMMON_EP_NUM(ep) < NRF_USBD_COMMON_EPOUT_CNT))));
+
+/* Lowest IN endpoint bit position */
+#define NRF_USBD_COMMON_EPIN_BITPOS_0 0
+
+/* Lowest OUT endpoint bit position */
+#define NRF_USBD_COMMON_EPOUT_BITPOS_0 16
+
+/* Input endpoint bits mask */
+#define NRF_USBD_COMMON_EPIN_BIT_MASK (0xFFFFU << NRF_USBD_COMMON_EPIN_BITPOS_0)
+
+/* Output endpoint bits mask */
+#define NRF_USBD_COMMON_EPOUT_BIT_MASK (0xFFFFU << NRF_USBD_COMMON_EPOUT_BITPOS_0)
+
+/* Isochronous endpoint bit mask */
+#define USBD_EPISO_BIT_MASK                                                    \
+	((1U << NRF_USBD_COMMON_EP_BITPOS(NRF_USBD_COMMON_EPOUT8)) |           \
+	 (1U << NRF_USBD_COMMON_EP_BITPOS(NRF_USBD_COMMON_EPIN8)))
+
+/* Convert endpoint number to bit position */
+#define NRF_USBD_COMMON_EP_BITPOS(ep) ((NRF_USBD_COMMON_EP_IS_IN(ep)      \
+	? NRF_USBD_COMMON_EPIN_BITPOS_0 : NRF_USBD_COMMON_EPOUT_BITPOS_0) \
+	+ NRF_USBD_COMMON_EP_NUM(ep))
+
+/* Check it the bit positions values match defined DATAEPSTATUS bit positions */
+BUILD_ASSERT(
+	(NRF_USBD_COMMON_EP_BITPOS(NRF_USBD_COMMON_EPIN1) == USBD_EPDATASTATUS_EPIN1_Pos) &&
+	(NRF_USBD_COMMON_EP_BITPOS(NRF_USBD_COMMON_EPIN2) == USBD_EPDATASTATUS_EPIN2_Pos) &&
+	(NRF_USBD_COMMON_EP_BITPOS(NRF_USBD_COMMON_EPIN3) == USBD_EPDATASTATUS_EPIN3_Pos) &&
+	(NRF_USBD_COMMON_EP_BITPOS(NRF_USBD_COMMON_EPIN4) == USBD_EPDATASTATUS_EPIN4_Pos) &&
+	(NRF_USBD_COMMON_EP_BITPOS(NRF_USBD_COMMON_EPIN5) == USBD_EPDATASTATUS_EPIN5_Pos) &&
+	(NRF_USBD_COMMON_EP_BITPOS(NRF_USBD_COMMON_EPIN6) == USBD_EPDATASTATUS_EPIN6_Pos) &&
+	(NRF_USBD_COMMON_EP_BITPOS(NRF_USBD_COMMON_EPIN7) == USBD_EPDATASTATUS_EPIN7_Pos) &&
+	(NRF_USBD_COMMON_EP_BITPOS(NRF_USBD_COMMON_EPOUT1) == USBD_EPDATASTATUS_EPOUT1_Pos) &&
+	(NRF_USBD_COMMON_EP_BITPOS(NRF_USBD_COMMON_EPOUT2) == USBD_EPDATASTATUS_EPOUT2_Pos) &&
+	(NRF_USBD_COMMON_EP_BITPOS(NRF_USBD_COMMON_EPOUT3) == USBD_EPDATASTATUS_EPOUT3_Pos) &&
+	(NRF_USBD_COMMON_EP_BITPOS(NRF_USBD_COMMON_EPOUT4) == USBD_EPDATASTATUS_EPOUT4_Pos) &&
+	(NRF_USBD_COMMON_EP_BITPOS(NRF_USBD_COMMON_EPOUT5) == USBD_EPDATASTATUS_EPOUT5_Pos) &&
+	(NRF_USBD_COMMON_EP_BITPOS(NRF_USBD_COMMON_EPOUT6) == USBD_EPDATASTATUS_EPOUT6_Pos) &&
+	(NRF_USBD_COMMON_EP_BITPOS(NRF_USBD_COMMON_EPOUT7) == USBD_EPDATASTATUS_EPOUT7_Pos),
+	"NRF_USBD_COMMON bit positions do not match hardware"
+);
+
+/* True if USB bus is suspended, updated in interrupt handler */
+static volatile bool m_bus_suspend;
+
+/* Data Stage direction used to map EP0DATADONE to actual endpoint */
+static uint8_t m_ep0_data_dir;
+
+/* Set bit indicates that endpoint is ready for DMA transfer.
+ *
+ * OUT endpoint is ready when DATA packet has been ACKed by device.
+ * IN endpoint is ready when IN endpoint buffer has no pending data.
+ *
+ * When endpoint is ready it responds with NAK to any further traffic.
+ */
+static uint32_t m_ep_ready;
+
+/* Set bit indicates that endpoint is waiting for DMA transfer, i.e. there is
+ * USB stack buffer queued for the transfer.
+ */
+static uint32_t m_ep_dma_waiting;
+
+/* Set bit indicates that endpoint is armed.
+ *
+ * OUT endpoint armed means that valid DATA packet from host will be ACKed.
+ * IN endpoint armed means that device will respond with DATA packet.
+ */
+static uint32_t m_ep_armed;
+
+/* Semaphore to guard EasyDMA access.
+ * In USBD there is only one DMA channel working in background, and new transfer
+ * cannot be started when there is ongoing transfer on any other channel.
+ */
+static K_SEM_DEFINE(dma_available, 1, 1);
+
+/* Endpoint on which DMA was started. */
+static nrf_usbd_common_ep_t dma_ep;
+
+/* Tracks whether total bytes transferred by DMA is even or odd. */
+static uint8_t m_dma_odd;
+
+/* First time enabling after reset. Used in nRF52 errata 223. */
+static bool m_first_enable = true;
+
+#define NRF_USBD_COMMON_FEEDER_BUFFER_SIZE NRF_USBD_COMMON_EPSIZE
+
+/* Bounce buffer for sending data from FLASH */
+static uint32_t m_tx_buffer[NRFX_CEIL_DIV(NRF_USBD_COMMON_FEEDER_BUFFER_SIZE, sizeof(uint32_t))];
+
+/* Early declaration. Documentation above definition. */
+static void usbd_dmareq_process(void);
+static inline void usbd_int_rise(void);
+static void nrf_usbd_common_stop(void);
+static void nrf_usbd_legacy_transfer_out_drop(nrf_usbd_common_ep_t ep);
+static size_t nrf_usbd_legacy_epout_size_get(nrf_usbd_common_ep_t ep);
+static bool nrf_usbd_legacy_suspend_check(void);
+
+/* Get EasyDMA end event address for given endpoint */
+static volatile uint32_t *usbd_ep_to_endevent(nrf_usbd_common_ep_t ep)
+{
+	int ep_in = NRF_USBD_COMMON_EP_IS_IN(ep);
+	int ep_num = NRF_USBD_COMMON_EP_NUM(ep);
+
+	NRF_USBD_COMMON_ASSERT_EP_VALID(ep);
+
+	if (!NRF_USBD_COMMON_EP_IS_ISO(ep_num)) {
+		if (ep_in) {
+			return &NRF_USBD->EVENTS_ENDEPIN[ep_num];
+		} else {
+			return &NRF_USBD->EVENTS_ENDEPOUT[ep_num];
+		}
+	}
+
+	return ep_in ? &NRF_USBD->EVENTS_ENDISOIN : &NRF_USBD->EVENTS_ENDISOOUT;
+}
+
+/* Return number of bytes last transferred by EasyDMA on given endpoint */
+static uint32_t usbd_ep_amount_get(nrf_usbd_common_ep_t ep)
+{
+	int ep_in = NRF_USBD_COMMON_EP_IS_IN(ep);
+	int ep_num = NRF_USBD_COMMON_EP_NUM(ep);
+
+	NRF_USBD_COMMON_ASSERT_EP_VALID(ep);
+
+	if (!NRF_USBD_COMMON_EP_IS_ISO(ep_num)) {
+		if (ep_in) {
+			return NRF_USBD->EPIN[ep_num].AMOUNT;
+		} else {
+			return NRF_USBD->EPOUT[ep_num].AMOUNT;
+		}
+	}
+
+	return ep_in ? NRF_USBD->ISOIN.AMOUNT : NRF_USBD->ISOOUT.AMOUNT;
+}
+
+/* Start EasyDMA on given endpoint */
+static void usbd_ep_dma_start(nrf_usbd_common_ep_t ep, uint32_t addr, size_t len)
+{
+	int ep_in = NRF_USBD_COMMON_EP_IS_IN(ep);
+	int ep_num = NRF_USBD_COMMON_EP_NUM(ep);
+
+	NRF_USBD_COMMON_ASSERT_EP_VALID(ep);
+
+	if (!NRF_USBD_COMMON_EP_IS_ISO(ep_num)) {
+		if (ep_in) {
+			NRF_USBD->EPIN[ep_num].PTR = addr;
+			NRF_USBD->EPIN[ep_num].MAXCNT = len;
+			NRF_USBD->TASKS_STARTEPIN[ep_num] = 1;
+		} else {
+			NRF_USBD->EPOUT[ep_num].PTR = addr;
+			NRF_USBD->EPOUT[ep_num].MAXCNT = len;
+			NRF_USBD->TASKS_STARTEPOUT[ep_num] = 1;
+		}
+	} else if (ep_in) {
+		NRF_USBD->ISOIN.PTR = addr;
+		NRF_USBD->ISOIN.MAXCNT = len;
+		NRF_USBD->TASKS_STARTISOIN = 1;
+	} else {
+		NRF_USBD->ISOOUT.PTR = addr;
+		NRF_USBD->ISOOUT.MAXCNT = len;
+		NRF_USBD->TASKS_STARTISOOUT = 1;
+	}
+}
+
+/* Convert endpoint number to bit position matching EPDATASTATUS register.
+ * Control and isochronous endpoints occupy unused EPDATASTATUS bits.
+ */
+static inline uint8_t ep2bit(nrf_usbd_common_ep_t ep)
+{
+	NRF_USBD_COMMON_ASSERT_EP_VALID(ep);
+	return NRF_USBD_COMMON_EP_BITPOS(ep);
+}
+
+static inline nrf_usbd_common_ep_t bit2ep(uint8_t bitpos)
+{
+	BUILD_ASSERT(NRF_USBD_COMMON_EPOUT_BITPOS_0 > NRF_USBD_COMMON_EPIN_BITPOS_0,
+		     "OUT endpoint bits should be higher than IN endpoint bits");
+	return (nrf_usbd_common_ep_t)((bitpos >= NRF_USBD_COMMON_EPOUT_BITPOS_0)
+		? NRF_USBD_COMMON_EPOUT(bitpos - NRF_USBD_COMMON_EPOUT_BITPOS_0)
+		: NRF_USBD_COMMON_EPIN(bitpos));
+}
+
+/* Prepare DMA for transfer */
+static inline void usbd_dma_pending_set(void)
+{
+	if (nrf_usbd_common_errata_199()) {
+		*((volatile uint32_t *)0x40027C1C) = 0x00000082;
+	}
+}
+
+/* DMA transfer finished */
+static inline void usbd_dma_pending_clear(void)
+{
+	if (nrf_usbd_common_errata_199()) {
+		*((volatile uint32_t *)0x40027C1C) = 0x00000000;
+	}
+}
+
+static void disarm_endpoint(uint8_t ep)
+{
+	if (ep == USB_CONTROL_EP_OUT || ep == USB_CONTROL_EP_IN) {
+		/* EP0 cannot be disarmed. This is not a problem because SETUP
+		 * token automatically disarms EP0 IN and EP0 OUT.
+		 */
+		return;
+	}
+
+	if (NRF_USBD_COMMON_EP_IS_ISO(ep)) {
+		/* Isochronous endpoints cannot be disarmed */
+		return;
+	}
+
+	if (!(m_ep_armed & BIT(ep2bit(ep)))) {
+		/* Endpoint is not armed, nothing to do */
+		return;
+	}
+
+	m_ep_armed &= ~BIT(ep2bit(ep));
+
+	/* Disarm the endpoint if there is any data buffered. For OUT endpoints
+	 * disarming means that the endpoint won't ACK (will NAK) DATA packet.
+	 */
+	*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7B6 +
+		2 * (USB_EP_GET_IDX(ep) - 1) + USB_EP_DIR_IS_OUT(ep) * 0x10;
+	*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)) |= BIT(1);
+}
+
+static inline void usbd_ep_abort(nrf_usbd_common_ep_t ep)
+{
+	unsigned int irq_lock_key = irq_lock();
+
+	disarm_endpoint(ep);
+
+	/* Do not process any data until endpoint is enqueued again */
+	m_ep_dma_waiting &= ~BIT(ep2bit(ep));
+
+	if (!NRF_USBD_COMMON_EP_IS_ISO(ep)) {
+		if (NRF_USBD_COMMON_EP_IS_OUT(ep)) {
+			m_ep_ready &= ~BIT(ep2bit(ep));
+		} else {
+			m_ep_ready |= BIT(ep2bit(ep));
+		}
+	}
+
+	/* Disarming endpoint is inherently a race between the driver and host.
+	 * Clear EPDATASTATUS to prevent interrupt handler from processing the
+	 * data if disarming lost the race (i.e. host finished first).
+	 */
+	NRF_USBD->EPDATASTATUS = BIT(ep2bit(ep));
+
+	irq_unlock(irq_lock_key);
+}
+
+static void nrf_usbd_legacy_ep_abort(nrf_usbd_common_ep_t ep)
+{
+	/* Only abort if there is no active DMA */
+	k_sem_take(&dma_available, K_FOREVER);
+	usbd_ep_abort(ep);
+	k_sem_give(&dma_available);
+
+	/* This function was holding DMA semaphore and could potentially prevent
+	 * next DMA from executing. Fire IRQ handler to check if any DMA needs
+	 * to be started.
+	 */
+	usbd_int_rise();
+}
+
+static void usbd_ep_abort_all(void)
+{
+	uint32_t ep_waiting = m_ep_dma_waiting | (m_ep_ready & NRF_USBD_COMMON_EPOUT_BIT_MASK);
+
+	while (ep_waiting != 0) {
+		uint8_t bitpos = NRF_CTZ(ep_waiting);
+
+		if (!NRF_USBD_COMMON_EP_IS_ISO(bit2ep(bitpos))) {
+			usbd_ep_abort(bit2ep(bitpos));
+		}
+		ep_waiting &= ~(1U << bitpos);
+	}
+
+	m_ep_ready = (((1U << NRF_USBD_COMMON_EPIN_CNT) - 1U) << NRF_USBD_COMMON_EPIN_BITPOS_0);
+}
+
+/* Rise USBD interrupt to trigger interrupt handler */
+static inline void usbd_int_rise(void)
+{
+	NVIC_SetPendingIRQ(USBD_IRQn);
+}
+
+static void ev_usbreset_handler(void)
+{
+	m_bus_suspend = false;
+
+	LOG_INF("Reset");
+	udc_submit_event(udc_nrf_dev, UDC_EVT_RESET, 0);
+}
+
+static void nrf_usbd_dma_finished(nrf_usbd_common_ep_t ep)
+{
+	/* DMA finished, track if total bytes transferred is even or odd */
+	m_dma_odd ^= usbd_ep_amount_get(ep) & 1;
+	usbd_dma_pending_clear();
+
+	if ((m_ep_dma_waiting & BIT(ep2bit(ep))) == 0) {
+		if (NRF_USBD_COMMON_EP_IS_OUT(ep) || (ep == NRF_USBD_COMMON_EPIN8)) {
+			/* Send event to the user - for an ISO IN or any OUT endpoint,
+			 * the whole transfer is finished in this moment
+			 */
+			atomic_set_bit(&xfer_finished, ep2bit(ep));
+			k_event_post(&drv_evt, BIT(UDC_NRF_EVT_EP_FINISHED));
+		}
+	} else if (ep == NRF_USBD_COMMON_EPOUT0) {
+		/* Allow receiving next OUT Data Stage chunk */
+		NRF_USBD->TASKS_EP0RCVOUT = 1;
+	}
+
+	if (NRF_USBD_COMMON_EP_IS_IN(ep) ||
+	    (ep >= NRF_USBD_COMMON_EPOUT1 && ep <= NRF_USBD_COMMON_EPOUT7)) {
+		m_ep_armed |= BIT(ep2bit(ep));
+	}
+
+	k_sem_give(&dma_available);
+}
+
+static void ev_sof_handler(void)
+{
+	/* Process isochronous endpoints */
+	uint32_t iso_ready_mask = (1U << ep2bit(NRF_USBD_COMMON_EPIN8));
+
+	/* SIZE.ISOOUT is 0 only when no packet was received at all */
+	if (NRF_USBD->SIZE.ISOOUT) {
+		iso_ready_mask |= (1U << ep2bit(NRF_USBD_COMMON_EPOUT8));
+	}
+	m_ep_ready |= iso_ready_mask;
+
+	m_ep_armed &= ~USBD_EPISO_BIT_MASK;
+
+	udc_submit_event(udc_nrf_dev, UDC_EVT_SOF, 0);
+}
+
+static void usbd_in_packet_sent(uint8_t ep)
+{
+	struct udc_ep_config *ep_cfg = udc_get_ep_cfg(udc_nrf_dev, ep);
+	struct net_buf *buf = udc_buf_peek(ep_cfg);
+
+	net_buf_pull(buf, usbd_ep_amount_get(ep));
+
+	if (buf->len) {
+		/* More packets will be sent, nothing to do here */
+	} else if (udc_ep_buf_has_zlp(buf)) {
+		/* Actual payload sent, only ZLP left */
+		udc_ep_buf_clear_zlp(buf);
+	} else {
+		LOG_DBG("USBD event: EndpointData: In finished");
+		/* No more data to be send - transmission finished */
+		atomic_set_bit(&xfer_finished, ep2bit(ep));
+		k_event_post(&drv_evt, BIT(UDC_NRF_EVT_EP_FINISHED));
+	}
+}
+
+static void ev_setup_handler(void)
+{
+	LOG_DBG("USBD event: Setup (rt:%.2x r:%.2x v:%.4x i:%.4x l:%u )",
+		       NRF_USBD->BMREQUESTTYPE, NRF_USBD->BREQUEST,
+		       NRF_USBD->WVALUEL | (NRF_USBD->WVALUEH << 8),
+		       NRF_USBD->WINDEXL | (NRF_USBD->WINDEXH << 8),
+		       NRF_USBD->WLENGTHL | (NRF_USBD->WLENGTHH << 8));
+
+	m_ep_dma_waiting &= ~((1U << ep2bit(NRF_USBD_COMMON_EPOUT0)) |
+			      (1U << ep2bit(NRF_USBD_COMMON_EPIN0)));
+	m_ep_ready &= ~(1U << ep2bit(NRF_USBD_COMMON_EPOUT0));
+	m_ep_ready |= 1U << ep2bit(NRF_USBD_COMMON_EPIN0);
+
+	m_ep_armed &= ~(BIT(ep2bit(USB_CONTROL_EP_OUT)) |
+			BIT(ep2bit(USB_CONTROL_EP_IN)));
+
+	k_event_post(&drv_evt, BIT(UDC_NRF_EVT_SETUP));
+}
+
+static void ev_usbevent_handler(void)
+{
+	uint32_t event = NRF_USBD->EVENTCAUSE;
+
+	/* Clear handled events */
+	NRF_USBD->EVENTCAUSE = event;
+
+	if (event & USBD_EVENTCAUSE_ISOOUTCRC_Msk) {
+		LOG_DBG("USBD event: ISOOUTCRC");
+		/* Currently no support */
+	}
+	if (event & USBD_EVENTCAUSE_SUSPEND_Msk) {
+		LOG_DBG("USBD event: SUSPEND");
+		m_bus_suspend = true;
+
+		k_event_post(&drv_evt, BIT(UDC_NRF_EVT_SUSPEND));
+	}
+	if (event & USBD_EVENTCAUSE_RESUME_Msk) {
+		LOG_DBG("USBD event: RESUME");
+		m_bus_suspend = false;
+
+		k_event_post(&drv_evt, BIT(UDC_NRF_EVT_RESUME));
+	}
+	if (event & USBD_EVENTCAUSE_USBWUALLOWED_Msk) {
+		LOG_DBG("USBD event: WUREQ (%s)", m_bus_suspend ? "In Suspend" : "Active");
+		if (m_bus_suspend) {
+			__ASSERT_NO_MSG(!nrf_usbd_legacy_suspend_check());
+			m_bus_suspend = false;
+
+			NRF_USBD->DPDMVALUE = USBD_DPDMVALUE_STATE_Resume
+				<< USBD_DPDMVALUE_STATE_Pos;
+			NRF_USBD->TASKS_DPDMDRIVE = 1;
+
+			k_event_post(&drv_evt, BIT(UDC_NRF_EVT_WUREQ));
+		}
+	}
+}
+
+static void ev_epdata_handler(uint32_t dataepstatus)
+{
+	if (dataepstatus) {
+		LOG_DBG("USBD event: EndpointEPStatus: %x", dataepstatus);
+
+		/* Mark endpoints ready for next DMA access */
+		m_ep_ready |= dataepstatus & ~USBD_EPISO_BIT_MASK;
+
+		/* IN endpoints are no longer armed after host read the data.
+		 * OUT endpoints are no longer armed before DMA reads the data.
+		 */
+		m_ep_armed &= ~(dataepstatus & ~USBD_EPISO_BIT_MASK);
+
+		/* Peripheral automatically enables endpoint for data reception
+		 * after OUT endpoint DMA transfer. This makes the device ACK
+		 * the OUT DATA even if the stack did not enqueue any buffer.
+		 *
+		 * This behaviour most likely cannot be avoided and therefore
+		 * there's nothing more to do for OUT endpoints.
+		 */
+		dataepstatus &= NRF_USBD_COMMON_EPIN_BIT_MASK;
+	}
+
+	/* Prepare next packet on IN endpoints */
+	while (dataepstatus) {
+		uint8_t bitpos = NRF_CTZ(dataepstatus);
+
+		dataepstatus &= ~BIT(bitpos);
+
+		usbd_in_packet_sent(bit2ep(bitpos));
+	}
+}
+
+/* Select endpoint for next DMA transfer.
+ *
+ * Passed value has at least one bit set. Each bit set indicates which endpoints
+ * can have data transferred between peripheral and USB stack buffer.
  *
- * The driver implements the interface between the nRF USBD peripheral
- * driver from nrfx package and UDC API.
+ * Return bit position indicating which endpoint to transfer.
  */
+static uint8_t usbd_dma_scheduler_algorithm(uint32_t req)
+{
+	/* Only prioritized scheduling mode is supported. */
+	return NRF_CTZ(req);
+}
+
+/* Process next DMA request, called at the end of interrupt handler */
+static void usbd_dmareq_process(void)
+{
+	uint32_t req = m_ep_dma_waiting & m_ep_ready;
+	struct net_buf *buf;
+	struct udc_ep_config *ep_cfg;
+	uint8_t *payload_buf;
+	size_t payload_len;
+	bool last_packet;
+	uint8_t pos;
+
+	if (req == 0 || nrf_usbd_legacy_suspend_check() ||
+	    k_sem_take(&dma_available, K_NO_WAIT) != 0) {
+		/* DMA cannot be started */
+		return;
+	}
+
+	if (NRFX_USBD_CONFIG_DMASCHEDULER_ISO_BOOST &&
+	    ((req & USBD_EPISO_BIT_MASK) != 0)) {
+		pos = usbd_dma_scheduler_algorithm(req & USBD_EPISO_BIT_MASK);
+	} else {
+		pos = usbd_dma_scheduler_algorithm(req);
+	}
+
+	nrf_usbd_common_ep_t ep = bit2ep(pos);
+
+	ep_cfg = udc_get_ep_cfg(udc_nrf_dev, ep);
+	buf = udc_buf_peek(ep_cfg);
+
+	__ASSERT_NO_MSG(buf);
+
+	if (NRF_USBD_COMMON_EP_IS_IN(ep)) {
+		/* Device -> Host */
+		payload_buf = buf->data;
+
+		if (buf->len > udc_mps_ep_size(ep_cfg)) {
+			payload_len = udc_mps_ep_size(ep_cfg);
+			last_packet = false;
+		} else {
+			payload_len = buf->len;
+			last_packet = !udc_ep_buf_has_zlp(buf);
+		}
+
+		if (!nrfx_is_in_ram(payload_buf)) {
+			__ASSERT_NO_MSG(payload_len <= NRF_USBD_COMMON_FEEDER_BUFFER_SIZE);
+			memcpy(m_tx_buffer, payload_buf, payload_len);
+			payload_buf = (uint8_t *)m_tx_buffer;
+		}
+	} else {
+		/* Host -> Device */
+		const size_t received = nrf_usbd_legacy_epout_size_get(ep);
+
+		payload_buf = net_buf_tail(buf);
+		payload_len = net_buf_tailroom(buf);
+
+		__ASSERT_NO_MSG(nrfx_is_in_ram(payload_buf));
+
+		if (received > payload_len) {
+			LOG_ERR("buffer too small: r: %u, l: %u", received, payload_len);
+		} else {
+			payload_len = received;
+		}
+
+		/* DMA will copy the received data, update the buffer here so received
+		 * does not have to be stored (can be done because there is no cache).
+		 */
+		net_buf_add(buf, payload_len);
+
+		last_packet = (udc_mps_ep_size(ep_cfg) != received) ||
+			      (net_buf_tailroom(buf) == 0);
+	}
+
+	if (last_packet) {
+		m_ep_dma_waiting &= ~BIT(pos);
+	}
+
+	usbd_dma_pending_set();
+	m_ep_ready &= ~BIT(pos);
+	if (NRF_USBD_COMMON_ISO_DEBUG || (!NRF_USBD_COMMON_EP_IS_ISO(ep))) {
+		LOG_DBG("USB DMA process: Starting transfer on EP: %x, size: %u",
+			ep, payload_len);
+	}
+
+	/* Start transfer to the endpoint buffer */
+	dma_ep = ep;
+	usbd_ep_dma_start(ep, (uint32_t)payload_buf, payload_len);
+}
+
+static inline void usbd_errata_171_begin(void)
+{
+	unsigned int irq_lock_key = irq_lock();
+
+	if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000) {
+		*((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+		*((volatile uint32_t *)(0x4006EC14)) = 0x000000C0;
+		*((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+	} else {
+		*((volatile uint32_t *)(0x4006EC14)) = 0x000000C0;
+	}
+
+	irq_unlock(irq_lock_key);
+}
+
+static inline void usbd_errata_171_end(void)
+{
+	unsigned int irq_lock_key = irq_lock();
+
+	if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000) {
+		*((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+		*((volatile uint32_t *)(0x4006EC14)) = 0x00000000;
+		*((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+	} else {
+		*((volatile uint32_t *)(0x4006EC14)) = 0x00000000;
+	}
+
+	irq_unlock(irq_lock_key);
+}
+
+static inline void usbd_errata_187_211_begin(void)
+{
+	unsigned int irq_lock_key = irq_lock();
+
+	if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000) {
+		*((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+		*((volatile uint32_t *)(0x4006ED14)) = 0x00000003;
+		*((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+	} else {
+		*((volatile uint32_t *)(0x4006ED14)) = 0x00000003;
+	}
+
+	irq_unlock(irq_lock_key);
+}
+
+static inline void usbd_errata_187_211_end(void)
+{
+	unsigned int irq_lock_key = irq_lock();
+
+	if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000) {
+		*((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+		*((volatile uint32_t *)(0x4006ED14)) = 0x00000000;
+		*((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+	} else {
+		*((volatile uint32_t *)(0x4006ED14)) = 0x00000000;
+	}
+
+	irq_unlock(irq_lock_key);
+}
+
+static void nrf_usbd_peripheral_enable(void)
+{
+	if (nrf_usbd_common_errata_187()) {
+		usbd_errata_187_211_begin();
+	}
+
+	if (nrf_usbd_common_errata_171()) {
+		usbd_errata_171_begin();
+	}
+
+	/* Enable the peripheral */
+	NRF_USBD->ENABLE = 1;
+
+	/* Waiting for peripheral to enable, this should take a few us */
+	while ((NRF_USBD->EVENTCAUSE & USBD_EVENTCAUSE_READY_Msk) == 0) {
+	}
+	NRF_USBD->EVENTCAUSE = USBD_EVENTCAUSE_READY_Msk;
+
+	if (nrf_usbd_common_errata_171()) {
+		usbd_errata_171_end();
+	}
+
+	if (nrf_usbd_common_errata_187()) {
+		usbd_errata_187_211_end();
+	}
+}
+
+static void nrf_usbd_irq_handler(void)
+{
+	volatile uint32_t *dma_endevent;
+	uint32_t epdatastatus = 0;
+
+	/* Always check and clear SOF but call handler only if SOF interrupt
+	 * is actually enabled.
+	 */
+	if (NRF_USBD->EVENTS_SOF) {
+		NRF_USBD->EVENTS_SOF = 0;
+		if (NRF_USBD->INTENSET & USBD_INTEN_SOF_Msk) {
+			ev_sof_handler();
+		}
+	}
+
+	/* Clear EPDATA event and only then get and clear EPDATASTATUS to make
+	 * sure we don't miss any event.
+	 */
+	if (NRF_USBD->EVENTS_EPDATA) {
+		NRF_USBD->EVENTS_EPDATA = 0;
+		epdatastatus = NRF_USBD->EPDATASTATUS;
+		NRF_USBD->EPDATASTATUS = epdatastatus;
+	}
+
+	/* Use common variable to store EP0DATADONE processing needed flag */
+	if (NRF_USBD->EVENTS_EP0DATADONE) {
+		NRF_USBD->EVENTS_EP0DATADONE = 0;
+		epdatastatus |= BIT(ep2bit(m_ep0_data_dir));
+	}
+
+	/* Check DMA end event only for last enabled DMA channel. Other channels
+	 * cannot be active and there's no harm in rechecking the event multiple
+	 * times (it is not a problem to check it even if DMA is not active).
+	 *
+	 * It is important to check DMA and handle DMA finished event before
+	 * handling acknowledged data transfer bits (epdatastatus) to avoid
+	 * a race condition between interrupt handler and host IN token.
+	 */
+	dma_endevent = usbd_ep_to_endevent(dma_ep);
+	if (*dma_endevent) {
+		*dma_endevent = 0;
+		nrf_usbd_dma_finished(dma_ep);
+	}
+
+	/* Process acknowledged transfers so we can prepare next DMA (if any) */
+	ev_epdata_handler(epdatastatus);
+
+	if (NRF_USBD->EVENTS_USBRESET) {
+		NRF_USBD->EVENTS_USBRESET = 0;
+		ev_usbreset_handler();
+	}
+
+	if (NRF_USBD->EVENTS_USBEVENT) {
+		NRF_USBD->EVENTS_USBEVENT = 0;
+		ev_usbevent_handler();
+	}
+
+	/* Handle SETUP only if there is no active DMA on EP0 */
+	if (unlikely(NRF_USBD->EVENTS_EP0SETUP) &&
+	    (k_sem_count_get(&dma_available) ||
+	     (dma_ep != NRF_USBD_COMMON_EPIN0 && dma_ep != NRF_USBD_COMMON_EPOUT0))) {
+		NRF_USBD->EVENTS_EP0SETUP = 0;
+		ev_setup_handler();
+	}
+
+	usbd_dmareq_process();
+}
+
+static void nrf_usbd_legacy_enable(void)
+{
+	/* Prepare for READY event receiving */
+	NRF_USBD->EVENTCAUSE = USBD_EVENTCAUSE_READY_Msk;
+
+	nrf_usbd_peripheral_enable();
+
+	if (nrf_usbd_common_errata_223() && m_first_enable) {
+		NRF_USBD->ENABLE = 0;
+
+		nrf_usbd_peripheral_enable();
+
+		m_first_enable = false;
+	}
+
+#if NRF_USBD_COMMON_USE_WORKAROUND_FOR_ANOMALY_211
+	if (nrf_usbd_common_errata_187() || nrf_usbd_common_errata_211()) {
+#else
+	if (nrf_usbd_common_errata_187()) {
+#endif
+		usbd_errata_187_211_begin();
+	}
+
+	if (nrf_usbd_common_errata_166()) {
+		*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x800)) = 0x7E3;
+		*((volatile uint32_t *)((uint32_t)(NRF_USBD) + 0x804)) = 0x40;
+		__ISB();
+		__DSB();
+	}
+
+	NRF_USBD->ISOSPLIT = USBD_ISOSPLIT_SPLIT_HalfIN << USBD_ISOSPLIT_SPLIT_Pos;
+
+	if (IS_ENABLED(CONFIG_NRF_USBD_ISO_IN_ZLP)) {
+		NRF_USBD->ISOINCONFIG = USBD_ISOINCONFIG_RESPONSE_ZeroData
+			<< USBD_ISOINCONFIG_RESPONSE_Pos;
+	} else {
+		NRF_USBD->ISOINCONFIG = USBD_ISOINCONFIG_RESPONSE_NoResp
+			<< USBD_ISOINCONFIG_RESPONSE_Pos;
+	}
+
+	m_ep_ready = (((1U << NRF_USBD_COMMON_EPIN_CNT) - 1U) << NRF_USBD_COMMON_EPIN_BITPOS_0);
+	m_ep_dma_waiting = 0;
+	m_ep_armed = 0;
+	m_dma_odd = 0;
+	__ASSERT_NO_MSG(k_sem_count_get(&dma_available) == 1);
+	usbd_dma_pending_clear();
+	m_ep0_data_dir = USB_CONTROL_EP_OUT;
+
+#if NRF_USBD_COMMON_USE_WORKAROUND_FOR_ANOMALY_211
+	if (nrf_usbd_common_errata_187() && !nrf_usbd_common_errata_211()) {
+#else
+	if (nrf_usbd_common_errata_187()) {
+#endif
+		usbd_errata_187_211_end();
+	}
+}
+
+static void nrf_usbd_legacy_disable(void)
+{
+	/* Make sure DMA is not active */
+	k_sem_take(&dma_available, K_FOREVER);
+
+	/* Stop just in case */
+	nrf_usbd_common_stop();
+
+	/* Disable all parts */
+	if (m_dma_odd) {
+		/* Prevent invalid bus request after next USBD enable by ensuring
+		 * that total number of bytes transferred by DMA is even.
+		 */
+		NRF_USBD->EVENTS_ENDEPIN[0] = 0;
+		usbd_ep_dma_start(NRF_USBD_COMMON_EPIN0, (uint32_t)&m_dma_odd, 1);
+		while (!NRF_USBD->EVENTS_ENDEPIN[0]) {
+		}
+		NRF_USBD->EVENTS_ENDEPIN[0] = 0;
+		m_dma_odd = 0;
+	}
+	NRF_USBD->ENABLE = 0;
+	usbd_dma_pending_clear();
+	k_sem_give(&dma_available);
 
-#include <string.h>
-#include <stdio.h>
-#include <soc.h>
+#if NRF_USBD_COMMON_USE_WORKAROUND_FOR_ANOMALY_211
+	if (nrf_usbd_common_errata_211()) {
+		usbd_errata_187_211_end();
+	}
+#endif
+}
 
-#include <zephyr/kernel.h>
-#include <zephyr/drivers/usb/udc.h>
-#include <zephyr/drivers/clock_control.h>
-#include <zephyr/drivers/clock_control/nrf_clock_control.h>
-#include <zephyr/dt-bindings/regulator/nrf5x.h>
+static void nrf_usbd_legacy_start(bool enable_sof)
+{
+	m_bus_suspend = false;
+
+	uint32_t int_mask = USBD_INTEN_USBRESET_Msk | USBD_INTEN_ENDEPIN0_Msk |
+		USBD_INTEN_ENDEPIN1_Msk | USBD_INTEN_ENDEPIN2_Msk |
+		USBD_INTEN_ENDEPIN3_Msk | USBD_INTEN_ENDEPIN4_Msk |
+		USBD_INTEN_ENDEPIN5_Msk | USBD_INTEN_ENDEPIN6_Msk |
+		USBD_INTEN_ENDEPIN7_Msk | USBD_INTEN_EP0DATADONE_Msk |
+		USBD_INTEN_ENDISOIN_Msk | USBD_INTEN_ENDEPOUT0_Msk |
+		USBD_INTEN_ENDEPOUT1_Msk | USBD_INTEN_ENDEPOUT2_Msk |
+		USBD_INTEN_ENDEPOUT3_Msk | USBD_INTEN_ENDEPOUT4_Msk |
+		USBD_INTEN_ENDEPOUT5_Msk | USBD_INTEN_ENDEPOUT6_Msk |
+		USBD_INTEN_ENDEPOUT7_Msk | USBD_INTEN_ENDISOOUT_Msk |
+		USBD_INTEN_USBEVENT_Msk | USBD_INTEN_EP0SETUP_Msk |
+		USBD_INTEN_EPDATA_Msk;
+
+	if (enable_sof) {
+		int_mask |= USBD_INTEN_SOF_Msk;
+	}
 
-#include <nrf_usbd_common.h>
-#include <hal/nrf_usbd.h>
-#include <nrfx_power.h>
-#include "udc_common.h"
+	/* Enable all required interrupts */
+	NRF_USBD->INTEN = int_mask;
 
-#include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(udc_nrf, CONFIG_UDC_DRIVER_LOG_LEVEL);
+	/* Enable interrupt globally */
+	irq_enable(USBD_IRQn);
 
-/*
- * There is no real advantage to change control endpoint size
- * but we can use it for testing UDC driver API and higher layers.
- */
-#define UDC_NRF_MPS0		UDC_MPS0_64
-#define UDC_NRF_EP0_SIZE	64
+	/* Enable pullups */
+	NRF_USBD->USBPULLUP = 1;
+}
 
-enum udc_nrf_event_type {
-	/* An event generated by the HAL driver */
-	UDC_NRF_EVT_HAL,
-	/* Shim driver event to trigger next transfer */
-	UDC_NRF_EVT_XFER,
-	/* Let controller perform status stage */
-	UDC_NRF_EVT_STATUS_IN,
-};
+static void nrf_usbd_common_stop(void)
+{
+	/* Clear interrupt */
+	NVIC_ClearPendingIRQ(USBD_IRQn);
 
-struct udc_nrf_evt {
-	enum udc_nrf_event_type type;
-	union {
-		nrf_usbd_common_evt_t hal_evt;
-		uint8_t ep;
-	};
-};
+	if (irq_is_enabled(USBD_IRQn)) {
+		/* Abort transfers */
+		usbd_ep_abort_all();
 
-K_MSGQ_DEFINE(drv_msgq, sizeof(struct udc_nrf_evt),
-	      CONFIG_UDC_NRF_MAX_QMESSAGES, sizeof(uint32_t));
+		/* Disable pullups */
+		NRF_USBD->USBPULLUP = 0;
 
-static K_KERNEL_STACK_DEFINE(drv_stack, CONFIG_UDC_NRF_THREAD_STACK_SIZE);
-static struct k_thread drv_stack_data;
+		/* Disable interrupt globally */
+		irq_disable(USBD_IRQn);
 
-/* USB device controller access from devicetree */
-#define DT_DRV_COMPAT nordic_nrf_usbd
+		/* Disable all interrupts */
+		NRF_USBD->INTEN = 0;
+	}
+}
 
-#define CFG_EPIN_CNT		DT_INST_PROP(0, num_in_endpoints)
-#define CFG_EPOUT_CNT		DT_INST_PROP(0, num_out_endpoints)
-#define CFG_EP_ISOIN_CNT	DT_INST_PROP(0, num_isoin_endpoints)
-#define CFG_EP_ISOOUT_CNT	DT_INST_PROP(0, num_isoout_endpoints)
+static bool nrf_usbd_legacy_suspend(void)
+{
+	bool suspended = false;
+	unsigned int irq_lock_key;
+
+	/* DMA doesn't work in Low Power mode, ensure there is no active DMA */
+	k_sem_take(&dma_available, K_FOREVER);
+	irq_lock_key = irq_lock();
+
+	if (m_bus_suspend) {
+		if (!(NRF_USBD->EVENTCAUSE & USBD_EVENTCAUSE_RESUME_Msk)) {
+			NRF_USBD->LOWPOWER = USBD_LOWPOWER_LOWPOWER_LowPower
+				<< USBD_LOWPOWER_LOWPOWER_Pos;
+			(void)NRF_USBD->LOWPOWER;
+			if (NRF_USBD->EVENTCAUSE & USBD_EVENTCAUSE_RESUME_Msk) {
+				NRF_USBD->LOWPOWER = USBD_LOWPOWER_LOWPOWER_ForceNormal
+					<< USBD_LOWPOWER_LOWPOWER_Pos;
+			} else {
+				suspended = true;
+			}
+		}
+	}
 
-static struct udc_ep_config ep_cfg_out[CFG_EPOUT_CNT + CFG_EP_ISOOUT_CNT + 1];
-static struct udc_ep_config ep_cfg_in[CFG_EPIN_CNT + CFG_EP_ISOIN_CNT + 1];
-static bool udc_nrf_setup_rcvd, udc_nrf_setup_set_addr, udc_nrf_fake_setup;
-static uint8_t udc_nrf_address;
-const static struct device *udc_nrf_dev;
+	irq_unlock(irq_lock_key);
+	k_sem_give(&dma_available);
+
+	return suspended;
+}
+
+static bool nrf_usbd_legacy_wakeup_req(void)
+{
+	bool started = false;
+	unsigned int irq_lock_key = irq_lock();
+
+	if (m_bus_suspend && nrf_usbd_legacy_suspend_check()) {
+		NRF_USBD->LOWPOWER = USBD_LOWPOWER_LOWPOWER_ForceNormal
+			<< USBD_LOWPOWER_LOWPOWER_Pos;
+		started = true;
+
+		if (nrf_usbd_common_errata_171()) {
+			if (*((volatile uint32_t *)(0x4006EC00)) == 0x00000000) {
+				*((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+				*((volatile uint32_t *)(0x4006EC14)) = 0x000000C0;
+				*((volatile uint32_t *)(0x4006EC00)) = 0x00009375;
+			} else {
+				*((volatile uint32_t *)(0x4006EC14)) = 0x000000C0;
+			}
+		}
+	}
+
+	irq_unlock(irq_lock_key);
+
+	return started;
+}
+
+static bool nrf_usbd_legacy_suspend_check(void)
+{
+	return NRF_USBD->LOWPOWER !=
+		(USBD_LOWPOWER_LOWPOWER_ForceNormal << USBD_LOWPOWER_LOWPOWER_Pos);
+}
+
+static bool nrf_usbd_legacy_ep_enable_check(nrf_usbd_common_ep_t ep)
+{
+	int ep_in = NRF_USBD_COMMON_EP_IS_IN(ep);
+	int ep_num = NRF_USBD_COMMON_EP_NUM(ep);
+
+	NRF_USBD_COMMON_ASSERT_EP_VALID(ep);
+
+	return (ep_in ? NRF_USBD->EPINEN : NRF_USBD->EPOUTEN) & BIT(ep_num);
+}
+
+static void nrf_usbd_legacy_ep_enable(nrf_usbd_common_ep_t ep)
+{
+	int ep_in = NRF_USBD_COMMON_EP_IS_IN(ep);
+	int ep_num = NRF_USBD_COMMON_EP_NUM(ep);
+
+	if (nrf_usbd_legacy_ep_enable_check(ep)) {
+		return;
+	}
+
+	if (ep_in) {
+		NRF_USBD->EPINEN |= BIT(ep_num);
+	} else {
+		NRF_USBD->EPOUTEN |= BIT(ep_num);
+	}
+}
+
+static void nrf_usbd_legacy_ep_disable(nrf_usbd_common_ep_t ep)
+{
+	int ep_in = NRF_USBD_COMMON_EP_IS_IN(ep);
+	int ep_num = NRF_USBD_COMMON_EP_NUM(ep);
+
+	/* Only disable endpoint if there is no active DMA */
+	k_sem_take(&dma_available, K_FOREVER);
+	usbd_ep_abort(ep);
+	if (ep_in) {
+		NRF_USBD->EPINEN &= ~BIT(ep_num);
+	} else {
+		NRF_USBD->EPOUTEN &= ~BIT(ep_num);
+	}
+	k_sem_give(&dma_available);
+
+	/* This function was holding DMA semaphore and could potentially prevent
+	 * next DMA from executing. Fire IRQ handler to check if any DMA needs
+	 * to be started.
+	 */
+	usbd_int_rise();
+}
+
+static void nrf_usbd_start_transfer(uint8_t ep)
+{
+	const uint8_t ep_bitpos = ep2bit(ep);
+	unsigned int irq_lock_key = irq_lock();
+
+	if (ep >= NRF_USBD_COMMON_EPOUT1 && ep <= NRF_USBD_COMMON_EPOUT7) {
+		if (!(m_ep_armed & BIT(ep_bitpos)) &&
+		    !(m_ep_ready & BIT(ep_bitpos))) {
+			/* Allow receiving DATA packet on OUT endpoint */
+			NRF_USBD->SIZE.EPOUT[NRF_USBD_COMMON_EP_NUM(ep)] = 0;
+			m_ep_armed |= BIT(ep_bitpos);
+		}
+	} else if (ep == NRF_USBD_COMMON_EPIN8) {
+		/* ISO IN endpoint can be already armed if application is double
+		 * buffering ISO IN data. When the endpoint is already armed it
+		 * must not be ready for next DMA transfer (until SOF).
+		 */
+		__ASSERT(!(m_ep_armed & BIT(ep_bitpos)) ||
+			 !(m_ep_ready & BIT(ep_bitpos)),
+			 "ISO IN must not be armed and ready");
+	} else if (NRF_USBD_COMMON_EP_IS_IN(ep)) {
+		/* IN endpoint must not have data armed */
+		__ASSERT(!(m_ep_armed & BIT(ep_bitpos)),
+			 "ep 0x%02x already armed", ep);
+	}
+
+	__ASSERT(!(m_ep_dma_waiting & BIT(ep_bitpos)),
+		 "ep 0x%02x already waiting", ep);
+
+	m_ep_dma_waiting |= BIT(ep_bitpos);
+	usbd_int_rise();
+
+	irq_unlock(irq_lock_key);
+}
+
+static size_t nrf_usbd_legacy_epout_size_get(nrf_usbd_common_ep_t ep)
+{
+	if (NRF_USBD_COMMON_EP_IS_ISO(ep)) {
+		size_t size = NRF_USBD->SIZE.ISOOUT;
+
+		if ((size & USBD_SIZE_ISOOUT_ZERO_Msk) ==
+		    (USBD_SIZE_ISOOUT_ZERO_ZeroData << USBD_SIZE_ISOOUT_ZERO_Pos)) {
+			size = 0;
+		}
+		return size;
+	}
+
+	return NRF_USBD->SIZE.EPOUT[NRF_USBD_COMMON_EP_NUM(ep)];
+}
+
+static void nrf_usbd_legacy_ep_stall(nrf_usbd_common_ep_t ep)
+{
+	__ASSERT_NO_MSG(!NRF_USBD_COMMON_EP_IS_ISO(ep));
+
+	LOG_DBG("USB: EP %x stalled.", ep);
+	NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_Stall << USBD_EPSTALL_STALL_Pos) | ep;
+}
+
+static bool nrf_usbd_legacy_ep_stall_check(nrf_usbd_common_ep_t ep)
+{
+	int ep_in = NRF_USBD_COMMON_EP_IS_IN(ep);
+	int ep_num = NRF_USBD_COMMON_EP_NUM(ep);
+
+	if (!NRF_USBD_COMMON_EP_IS_ISO(ep_num)) {
+		if (ep_in) {
+			return NRF_USBD->HALTED.EPIN[ep_num];
+		} else {
+			return NRF_USBD->HALTED.EPOUT[ep_num];
+		}
+	}
+
+	return false;
+}
+
+static void nrf_usbd_legacy_ep_stall_clear(nrf_usbd_common_ep_t ep)
+{
+	__ASSERT_NO_MSG(!NRF_USBD_COMMON_EP_IS_ISO(ep));
+
+	if (NRF_USBD_COMMON_EP_IS_OUT(ep) && nrf_usbd_legacy_ep_stall_check(ep)) {
+		nrf_usbd_legacy_transfer_out_drop(ep);
+	}
+	NRF_USBD->EPSTALL = (USBD_EPSTALL_STALL_UnStall << USBD_EPSTALL_STALL_Pos) | ep;
+}
+
+static void nrf_usbd_legacy_ep_dtoggle_clear(nrf_usbd_common_ep_t ep)
+{
+	__ASSERT_NO_MSG(!NRF_USBD_COMMON_EP_IS_ISO(ep));
+
+	NRF_USBD->DTOGGLE = ep | (USBD_DTOGGLE_VALUE_Nop << USBD_DTOGGLE_VALUE_Pos);
+	NRF_USBD->DTOGGLE = ep | (USBD_DTOGGLE_VALUE_Data0 << USBD_DTOGGLE_VALUE_Pos);
+}
+
+static void nrf_usbd_legacy_transfer_out_drop(nrf_usbd_common_ep_t ep)
+{
+	unsigned int irq_lock_key = irq_lock();
+
+	__ASSERT_NO_MSG(NRF_USBD_COMMON_EP_IS_OUT(ep));
+
+	m_ep_ready &= ~(1U << ep2bit(ep));
+	if (!NRF_USBD_COMMON_EP_IS_ISO(ep)) {
+		NRF_USBD->SIZE.EPOUT[NRF_USBD_COMMON_EP_NUM(ep)] = 0;
+	}
+
+	irq_unlock(irq_lock_key);
+}
 
 struct udc_nrf_config {
 	clock_control_subsys_t clock;
@@ -83,17 +1168,6 @@ struct udc_nrf_config {
 static struct onoff_manager *hfxo_mgr;
 static struct onoff_client hfxo_cli;
 
-static void udc_nrf_clear_control_out(const struct device *dev)
-{
-	if (nrf_usbd_common_last_setup_dir_get() == USB_CONTROL_EP_OUT &&
-	    udc_nrf_setup_rcvd) {
-		/* Allow data chunk on EP0 OUT */
-		nrf_usbd_common_setup_data_clear();
-		udc_nrf_setup_rcvd = false;
-		LOG_INF("Allow data OUT");
-	}
-}
-
 static void udc_event_xfer_in_next(const struct device *dev, const uint8_t ep)
 {
 	struct udc_ep_config *ep_cfg = udc_get_ep_cfg(dev, ep);
@@ -105,22 +1179,8 @@ static void udc_event_xfer_in_next(const struct device *dev, const uint8_t ep)
 
 	buf = udc_buf_peek(ep_cfg);
 	if (buf != NULL) {
-		nrf_usbd_common_transfer_t xfer = {
-			.p_data = {.tx = buf->data},
-			.size = buf->len,
-			.flags = udc_ep_buf_has_zlp(buf) ?
-				 NRF_USBD_COMMON_TRANSFER_ZLP_FLAG : 0,
-		};
-		nrfx_err_t err;
-
-		err = nrf_usbd_common_ep_transfer(ep, &xfer);
-		if (err != NRFX_SUCCESS) {
-			LOG_ERR("ep 0x%02x nrfx error: %x", ep, err);
-			/* REVISE: remove from endpoint queue? ASSERT? */
-			udc_submit_ep_event(dev, buf, -ECONNREFUSED);
-		} else {
-			udc_ep_set_busy(ep_cfg, true);
-		}
+		nrf_usbd_start_transfer(ep);
+		udc_ep_set_busy(ep_cfg, true);
 	}
 }
 
@@ -146,7 +1206,8 @@ static void udc_event_xfer_ctrl_in(const struct device *dev,
 	udc_ctrl_update_stage(dev, buf);
 
 	if (!udc_nrf_setup_set_addr) {
-		nrf_usbd_common_setup_clear();
+		/* Allow status stage */
+		NRF_USBD->TASKS_EP0STATUS = 1;
 	}
 }
 
@@ -165,51 +1226,25 @@ static void udc_event_fake_status_in(const struct device *dev)
 	udc_event_xfer_ctrl_in(dev, buf);
 }
 
-static void udc_event_xfer_in(const struct device *dev,
-			      nrf_usbd_common_evt_t const *const event)
+static void udc_event_xfer_in(const struct device *dev, const uint8_t ep)
 {
 	struct udc_ep_config *ep_cfg;
-	uint8_t ep = event->data.eptransfer.ep;
 	struct net_buf *buf;
 
 	ep_cfg = udc_get_ep_cfg(dev, ep);
 
-	switch (event->data.eptransfer.status) {
-	case NRF_USBD_COMMON_EP_OK:
-		buf = udc_buf_get(ep_cfg);
-		if (buf == NULL) {
-			LOG_ERR("ep 0x%02x queue is empty", ep);
-			__ASSERT_NO_MSG(false);
-			return;
-		}
-
-		udc_ep_set_busy(ep_cfg, false);
-		if (ep == USB_CONTROL_EP_IN) {
-			udc_event_xfer_ctrl_in(dev, buf);
-			return;
-		}
+	buf = udc_buf_get(ep_cfg);
+	if (buf == NULL) {
+		LOG_ERR("ep 0x%02x queue is empty", ep);
+		__ASSERT_NO_MSG(false);
+		return;
+	}
 
+	udc_ep_set_busy(ep_cfg, false);
+	if (ep == USB_CONTROL_EP_IN) {
+		udc_event_xfer_ctrl_in(dev, buf);
+	} else {
 		udc_submit_ep_event(dev, buf, 0);
-		break;
-
-	case NRF_USBD_COMMON_EP_ABORTED:
-		LOG_WRN("aborted IN ep 0x%02x", ep);
-		buf = udc_buf_get_all(ep_cfg);
-
-		if (buf == NULL) {
-			LOG_DBG("ep 0x%02x queue is empty", ep);
-			return;
-		}
-
-		udc_ep_set_busy(ep_cfg, false);
-		udc_submit_ep_event(dev, buf, -ECONNABORTED);
-		break;
-
-	default:
-		LOG_ERR("Unexpected event (nrfx_usbd): %d, ep 0x%02x",
-			event->data.eptransfer.status, ep);
-		udc_submit_event(dev, UDC_EVT_ERROR, -EIO);
-		break;
 	}
 }
 
@@ -240,78 +1275,36 @@ static void udc_event_xfer_out_next(const struct device *dev, const uint8_t ep)
 
 	buf = udc_buf_peek(ep_cfg);
 	if (buf != NULL) {
-		nrf_usbd_common_transfer_t xfer = {
-			.p_data = {.rx = buf->data},
-			.size = buf->size,
-			.flags = 0,
-		};
-		nrfx_err_t err;
-
-		err = nrf_usbd_common_ep_transfer(ep, &xfer);
-		if (err != NRFX_SUCCESS) {
-			LOG_ERR("ep 0x%02x nrfx error: %x", ep, err);
-			/* REVISE: remove from endpoint queue? ASSERT? */
-			udc_submit_ep_event(dev, buf, -ECONNREFUSED);
-		} else {
-			udc_ep_set_busy(ep_cfg, true);
-		}
+		nrf_usbd_start_transfer(ep);
+		udc_ep_set_busy(ep_cfg, true);
 	} else {
 		LOG_DBG("ep 0x%02x waiting, queue is empty", ep);
 	}
 }
 
-static void udc_event_xfer_out(const struct device *dev,
-			       nrf_usbd_common_evt_t const *const event)
+static void udc_event_xfer_out(const struct device *dev, const uint8_t ep)
 {
 	struct udc_ep_config *ep_cfg;
-	uint8_t ep = event->data.eptransfer.ep;
-	nrf_usbd_common_ep_status_t err_code;
 	struct net_buf *buf;
-	size_t len;
 
-	switch (event->data.eptransfer.status) {
-	case NRF_USBD_COMMON_EP_WAITING:
-		/*
-		 * There is nothing to do here, new transfer
-		 * will be tried in both cases later.
-		 */
-		break;
-
-	case NRF_USBD_COMMON_EP_OK:
-		err_code = nrf_usbd_common_ep_status_get(ep, &len);
-		if (err_code != NRF_USBD_COMMON_EP_OK) {
-			LOG_ERR("OUT transfer failed %d", err_code);
-		}
-
-		ep_cfg = udc_get_ep_cfg(dev, ep);
-		buf = udc_buf_get(ep_cfg);
-		if (buf == NULL) {
-			LOG_ERR("ep 0x%02x ok, queue is empty", ep);
-			return;
-		}
-
-		net_buf_add(buf, len);
-		udc_ep_set_busy(ep_cfg, false);
-		if (ep == USB_CONTROL_EP_OUT) {
-			udc_event_xfer_ctrl_out(dev, buf);
-		} else {
-			udc_submit_ep_event(dev, buf, 0);
-		}
-
-		break;
+	ep_cfg = udc_get_ep_cfg(dev, ep);
+	buf = udc_buf_get(ep_cfg);
+	if (buf == NULL) {
+		LOG_ERR("ep 0x%02x ok, queue is empty", ep);
+		return;
+	}
 
-	default:
-		LOG_ERR("Unexpected event (nrfx_usbd): %d, ep 0x%02x",
-			event->data.eptransfer.status, ep);
-		udc_submit_event(dev, UDC_EVT_ERROR, -EIO);
-		break;
+	udc_ep_set_busy(ep_cfg, false);
+	if (ep == USB_CONTROL_EP_OUT) {
+		udc_event_xfer_ctrl_out(dev, buf);
+	} else {
+		udc_submit_ep_event(dev, buf, 0);
 	}
 }
 
 static int usbd_ctrl_feed_dout(const struct device *dev,
 			       const size_t length)
 {
-
 	struct udc_ep_config *cfg = udc_get_ep_cfg(dev, USB_CONTROL_EP_OUT);
 	struct net_buf *buf;
 
@@ -320,18 +1313,39 @@ static int usbd_ctrl_feed_dout(const struct device *dev,
 		return -ENOMEM;
 	}
 
-	k_fifo_put(&cfg->fifo, buf);
-	udc_nrf_clear_control_out(dev);
+	udc_buf_put(cfg, buf);
+
+	__ASSERT_NO_MSG(k_current_get() == &drv_stack_data);
+	udc_event_xfer_out_next(dev, USB_CONTROL_EP_OUT);
+
+	/* Allow receiving first OUT Data Stage packet */
+	NRF_USBD->TASKS_EP0RCVOUT = 1;
 
 	return 0;
 }
 
 static int udc_event_xfer_setup(const struct device *dev)
 {
-	nrf_usbd_common_setup_t *setup;
+	struct udc_ep_config *cfg_out = udc_get_ep_cfg(dev, USB_CONTROL_EP_OUT);
+	struct udc_ep_config *cfg_in = udc_get_ep_cfg(dev, USB_CONTROL_EP_IN);
+	struct usb_setup_packet *setup;
 	struct net_buf *buf;
 	int err;
 
+	/* Make sure there isn't any obsolete data stage buffer queued */
+	buf = udc_buf_get_all(cfg_out);
+	if (buf) {
+		net_buf_unref(buf);
+	}
+
+	buf = udc_buf_get_all(cfg_in);
+	if (buf) {
+		net_buf_unref(buf);
+	}
+
+	udc_ep_set_busy(cfg_out, false);
+	udc_ep_set_busy(cfg_in, false);
+
 	buf = udc_ctrl_alloc(dev, USB_CONTROL_EP_OUT,
 			     sizeof(struct usb_setup_packet));
 	if (buf == NULL) {
@@ -340,8 +1354,12 @@ static int udc_event_xfer_setup(const struct device *dev)
 	}
 
 	udc_ep_buf_set_setup(buf);
-	setup = (nrf_usbd_common_setup_t *)buf->data;
-	nrf_usbd_common_setup_get(setup);
+	setup = (struct usb_setup_packet *)buf->data;
+	setup->bmRequestType = NRF_USBD->BMREQUESTTYPE;
+	setup->bRequest = NRF_USBD->BREQUEST;
+	setup->wValue = NRF_USBD->WVALUEL | (NRF_USBD->WVALUEH << 8);
+	setup->wIndex = NRF_USBD->WINDEXL | (NRF_USBD->WINDEXH << 8);
+	setup->wLength = NRF_USBD->WLENGTHL | (NRF_USBD->WLENGTHH << 8);
 
 	/* USBD peripheral automatically handles Set Address in slightly
 	 * different manner than the USB stack.
@@ -412,7 +1430,6 @@ static int udc_event_xfer_setup(const struct device *dev)
 	}
 
 	net_buf_add(buf, sizeof(nrf_usbd_common_setup_t));
-	udc_nrf_setup_rcvd = true;
 
 	/* Update to next stage of control transfer */
 	udc_ctrl_update_stage(dev, buf);
@@ -420,11 +1437,13 @@ static int udc_event_xfer_setup(const struct device *dev)
 	if (udc_ctrl_stage_is_data_out(dev)) {
 		/*  Allocate and feed buffer for data OUT stage */
 		LOG_DBG("s:%p|feed for -out-", buf);
+		m_ep0_data_dir = USB_CONTROL_EP_OUT;
 		err = usbd_ctrl_feed_dout(dev, udc_data_stage_length(buf));
 		if (err == -ENOMEM) {
 			err = udc_submit_ep_event(dev, buf, err);
 		}
 	} else if (udc_ctrl_stage_is_data_in(dev)) {
+		m_ep0_data_dir = USB_CONTROL_EP_IN;
 		err = udc_ctrl_submit_s_in_status(dev);
 	} else {
 		err = udc_ctrl_submit_s_status(dev);
@@ -433,65 +1452,63 @@ static int udc_event_xfer_setup(const struct device *dev)
 	return err;
 }
 
-static void udc_nrf_thread(void *p1, void *p2, void *p3)
+static void udc_nrf_thread_handler(const struct device *dev)
 {
-	ARG_UNUSED(p2);
-	ARG_UNUSED(p3);
+	uint32_t evt;
 
-	const struct device *dev = p1;
+	/* Wait for at least one event */
+	k_event_wait(&drv_evt, UINT32_MAX, false, K_FOREVER);
 
-	while (true) {
-		bool start_xfer = false;
-		struct udc_nrf_evt evt;
-		uint8_t ep;
-
-		k_msgq_get(&drv_msgq, &evt, K_FOREVER);
-
-		switch (evt.type) {
-		case UDC_NRF_EVT_HAL:
-			ep = evt.hal_evt.data.eptransfer.ep;
-			switch (evt.hal_evt.type) {
-			case NRF_USBD_COMMON_EVT_SUSPEND:
-				LOG_INF("SUSPEND state detected");
-				nrf_usbd_common_suspend();
-				udc_set_suspended(udc_nrf_dev, true);
-				udc_submit_event(udc_nrf_dev, UDC_EVT_SUSPEND, 0);
-				break;
-			case NRF_USBD_COMMON_EVT_RESUME:
-				LOG_INF("RESUMING from suspend");
-				udc_set_suspended(udc_nrf_dev, false);
-				udc_submit_event(udc_nrf_dev, UDC_EVT_RESUME, 0);
-				break;
-			case NRF_USBD_COMMON_EVT_WUREQ:
-				LOG_INF("Remote wakeup initiated");
-				udc_set_suspended(udc_nrf_dev, false);
-				udc_submit_event(udc_nrf_dev, UDC_EVT_RESUME, 0);
-				break;
-			case NRF_USBD_COMMON_EVT_EPTRANSFER:
-				start_xfer = true;
-				if (USB_EP_DIR_IS_IN(ep)) {
-					udc_event_xfer_in(dev, &evt.hal_evt);
-				} else {
-					udc_event_xfer_out(dev, &evt.hal_evt);
-				}
-				break;
-			case NRF_USBD_COMMON_EVT_SETUP:
-				udc_event_xfer_setup(dev);
-				break;
-			default:
-				break;
+	/* Process all events that are set */
+	evt = k_event_clear(&drv_evt, UINT32_MAX);
+
+	if (evt & BIT(UDC_NRF_EVT_SUSPEND)) {
+		LOG_INF("SUSPEND state detected");
+		nrf_usbd_legacy_suspend();
+		udc_set_suspended(dev, true);
+		udc_submit_event(dev, UDC_EVT_SUSPEND, 0);
+	}
+
+	if (evt & BIT(UDC_NRF_EVT_RESUME)) {
+		LOG_INF("RESUMING from suspend");
+		udc_set_suspended(dev, false);
+		udc_submit_event(dev, UDC_EVT_RESUME, 0);
+	}
+
+	if (evt & BIT(UDC_NRF_EVT_WUREQ)) {
+		LOG_INF("Remote wakeup initiated");
+		udc_set_suspended(dev, false);
+		udc_submit_event(dev, UDC_EVT_RESUME, 0);
+	}
+
+	if (evt & BIT(UDC_NRF_EVT_EP_FINISHED)) {
+		uint32_t eps = atomic_clear(&xfer_finished);
+
+		while (eps) {
+			uint8_t bitpos = NRF_CTZ(eps);
+			nrf_usbd_common_ep_t ep = bit2ep(bitpos);
+
+			eps &= ~BIT(bitpos);
+
+			if (USB_EP_DIR_IS_IN(ep)) {
+				udc_event_xfer_in(dev, ep);
+				udc_event_xfer_in_next(dev, ep);
+			} else {
+				udc_event_xfer_out(dev, ep);
+				udc_event_xfer_out_next(dev, ep);
 			}
-			break;
-		case UDC_NRF_EVT_XFER:
-			start_xfer = true;
-			ep = evt.ep;
-			break;
-		case UDC_NRF_EVT_STATUS_IN:
-			udc_event_fake_status_in(dev);
-			break;
 		}
+	}
+
+	if (evt & BIT(UDC_NRF_EVT_XFER)) {
+		uint32_t eps = atomic_clear(&xfer_new);
+
+		while (eps) {
+			uint8_t bitpos = NRF_CTZ(eps);
+			nrf_usbd_common_ep_t ep = bit2ep(bitpos);
+
+			eps &= ~BIT(bitpos);
 
-		if (start_xfer) {
 			if (USB_EP_DIR_IS_IN(ep)) {
 				udc_event_xfer_in_next(dev, ep);
 			} else {
@@ -499,56 +1516,25 @@ static void udc_nrf_thread(void *p1, void *p2, void *p3)
 			}
 		}
 	}
-}
 
-static void udc_sof_check_iso_out(const struct device *dev)
-{
-	const uint8_t iso_out_addr = 0x08;
-	struct udc_nrf_evt evt = {
-		.type = UDC_NRF_EVT_XFER,
-		.ep = iso_out_addr,
-	};
-	struct udc_ep_config *ep_cfg;
-
-	ep_cfg = udc_get_ep_cfg(dev, iso_out_addr);
-	if (ep_cfg == NULL) {
-		return;
+	if (evt & BIT(UDC_NRF_EVT_STATUS_IN)) {
+		udc_event_fake_status_in(dev);
 	}
 
-	if (ep_cfg->stat.enabled && !k_fifo_is_empty(&ep_cfg->fifo)) {
-		k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
+	if (evt & BIT(UDC_NRF_EVT_SETUP)) {
+		udc_event_xfer_setup(dev);
 	}
 }
 
-static void usbd_event_handler(nrf_usbd_common_evt_t const *const hal_evt)
+static void udc_nrf_thread(void *p1, void *p2, void *p3)
 {
-	switch (hal_evt->type) {
-	case NRF_USBD_COMMON_EVT_RESET:
-		LOG_INF("Reset");
-		udc_submit_event(udc_nrf_dev, UDC_EVT_RESET, 0);
-		break;
-	case NRF_USBD_COMMON_EVT_SOF:
-		udc_submit_event(udc_nrf_dev, UDC_EVT_SOF, 0);
-		udc_sof_check_iso_out(udc_nrf_dev);
-		break;
-	case NRF_USBD_COMMON_EVT_SUSPEND:
-	case NRF_USBD_COMMON_EVT_RESUME:
-	case NRF_USBD_COMMON_EVT_WUREQ:
-	case NRF_USBD_COMMON_EVT_EPTRANSFER:
-	case NRF_USBD_COMMON_EVT_SETUP: {
-		struct udc_nrf_evt evt = {
-			.type = UDC_NRF_EVT_HAL,
-			.hal_evt = *hal_evt,
-		};
-
-		/* Forward these two to the thread since mutually exclusive
-		 * access to the controller is necessary.
-		 */
-		k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
-		break;
-	}
-	default:
-		break;
+	ARG_UNUSED(p2);
+	ARG_UNUSED(p3);
+
+	const struct device *dev = p1;
+
+	while (true) {
+		udc_nrf_thread_handler(dev);
 	}
 }
 
@@ -561,7 +1547,7 @@ static void udc_nrf_power_handler(nrfx_power_usb_evt_t pwr_evt)
 		break;
 	case NRFX_POWER_USB_EVT_READY:
 		LOG_DBG("POWER event ready");
-		nrf_usbd_common_start(true);
+		nrf_usbd_legacy_start(true);
 		break;
 	case NRFX_POWER_USB_EVT_REMOVED:
 		LOG_DBG("POWER event removed");
@@ -572,41 +1558,24 @@ static void udc_nrf_power_handler(nrfx_power_usb_evt_t pwr_evt)
 	}
 }
 
-static bool udc_nrf_fake_status_in(const struct device *dev)
-{
-	struct udc_nrf_evt evt = {
-		.type = UDC_NRF_EVT_STATUS_IN,
-		.ep = USB_CONTROL_EP_IN,
-	};
-
-	if (nrf_usbd_common_last_setup_dir_get() == USB_CONTROL_EP_OUT ||
-	    udc_nrf_fake_setup) {
-		/* Let controller perform status IN stage */
-		k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
-		return true;
-	}
-
-	return false;
-}
-
 static int udc_nrf_ep_enqueue(const struct device *dev,
 			      struct udc_ep_config *cfg,
 			      struct net_buf *buf)
 {
-	struct udc_nrf_evt evt = {
-		.type = UDC_NRF_EVT_XFER,
-		.ep = cfg->addr,
-	};
-
 	udc_buf_put(cfg, buf);
 
 	if (cfg->addr == USB_CONTROL_EP_IN && buf->len == 0) {
-		if (udc_nrf_fake_status_in(dev)) {
+		const struct udc_buf_info *bi = udc_get_buf_info(buf);
+
+		if (bi->status) {
+			/* Controller automatically performs status IN stage */
+			k_event_post(&drv_evt, BIT(UDC_NRF_EVT_STATUS_IN));
 			return 0;
 		}
 	}
 
-	k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
+	atomic_set_bit(&xfer_new, ep2bit(cfg->addr));
+	k_event_post(&drv_evt, BIT(UDC_NRF_EVT_XFER));
 
 	return 0;
 }
@@ -614,23 +1583,15 @@ static int udc_nrf_ep_enqueue(const struct device *dev,
 static int udc_nrf_ep_dequeue(const struct device *dev,
 			      struct udc_ep_config *cfg)
 {
-	bool busy = nrf_usbd_common_ep_is_busy(cfg->addr);
-
-	nrf_usbd_common_ep_abort(cfg->addr);
-	if (USB_EP_DIR_IS_OUT(cfg->addr) || !busy) {
-		struct net_buf *buf;
+	struct net_buf *buf;
 
-		/*
-		 * HAL driver does not generate event for an OUT endpoint
-		 * or when IN endpoint is not busy.
-		 */
-		buf = udc_buf_get_all(cfg);
-		if (buf) {
-			udc_submit_ep_event(dev, buf, -ECONNABORTED);
-		} else {
-			LOG_INF("ep 0x%02x queue is empty", cfg->addr);
-		}
+	nrf_usbd_legacy_ep_abort(cfg->addr);
 
+	buf = udc_buf_get_all(cfg);
+	if (buf) {
+		udc_submit_ep_event(dev, buf, -ECONNABORTED);
+	} else {
+		LOG_INF("ep 0x%02x queue is empty", cfg->addr);
 	}
 
 	udc_ep_set_busy(cfg, false);
@@ -645,14 +1606,13 @@ static int udc_nrf_ep_enable(const struct device *dev,
 
 	__ASSERT_NO_MSG(cfg);
 	mps = (udc_mps_ep_size(cfg) == 0) ? cfg->caps.mps : udc_mps_ep_size(cfg);
-	nrf_usbd_common_ep_max_packet_size_set(cfg->addr, mps);
-	nrf_usbd_common_ep_enable(cfg->addr);
+	nrf_usbd_legacy_ep_enable(cfg->addr);
 	if (!NRF_USBD_EPISO_CHECK(cfg->addr)) {
 		/* ISO transactions for full-speed device do not support
 		 * toggle sequencing and should only send DATA0 PID.
 		 */
-		nrf_usbd_common_ep_dtoggle_clear(cfg->addr);
-		nrf_usbd_common_ep_stall_clear(cfg->addr);
+		nrf_usbd_legacy_ep_dtoggle_clear(cfg->addr);
+		nrf_usbd_legacy_ep_stall_clear(cfg->addr);
 	}
 
 	LOG_DBG("Enable ep 0x%02x", cfg->addr);
@@ -664,7 +1624,7 @@ static int udc_nrf_ep_disable(const struct device *dev,
 			      struct udc_ep_config *cfg)
 {
 	__ASSERT_NO_MSG(cfg);
-	nrf_usbd_common_ep_disable(cfg->addr);
+	nrf_usbd_legacy_ep_disable(cfg->addr);
 	LOG_DBG("Disable ep 0x%02x", cfg->addr);
 
 	return 0;
@@ -677,9 +1637,9 @@ static int udc_nrf_ep_set_halt(const struct device *dev,
 
 	if (cfg->addr == USB_CONTROL_EP_OUT ||
 	    cfg->addr == USB_CONTROL_EP_IN) {
-		nrf_usbd_common_setup_stall();
+		NRF_USBD->TASKS_EP0STALL = 1;
 	} else {
-		nrf_usbd_common_ep_stall(cfg->addr);
+		nrf_usbd_legacy_ep_stall(cfg->addr);
 	}
 
 	return 0;
@@ -690,8 +1650,8 @@ static int udc_nrf_ep_clear_halt(const struct device *dev,
 {
 	LOG_DBG("Clear halt ep 0x%02x", cfg->addr);
 
-	nrf_usbd_common_ep_dtoggle_clear(cfg->addr);
-	nrf_usbd_common_ep_stall_clear(cfg->addr);
+	nrf_usbd_legacy_ep_dtoggle_clear(cfg->addr);
+	nrf_usbd_legacy_ep_stall_clear(cfg->addr);
 
 	return 0;
 }
@@ -719,17 +1679,10 @@ static int udc_nrf_set_address(const struct device *dev, const uint8_t addr)
 	udc_nrf_address = addr;
 
 	if (udc_nrf_fake_setup) {
-		struct udc_nrf_evt evt = {
-			.type = UDC_NRF_EVT_HAL,
-			.hal_evt = {
-				.type = NRF_USBD_COMMON_EVT_SETUP,
-			},
-		};
-
 		/* Finished handling lost Set Address, now handle the pending
 		 * SETUP transfer.
 		 */
-		k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
+		k_event_post(&drv_evt, BIT(UDC_NRF_EVT_SETUP));
 	}
 
 	return 0;
@@ -737,7 +1690,7 @@ static int udc_nrf_set_address(const struct device *dev, const uint8_t addr)
 
 static int udc_nrf_host_wakeup(const struct device *dev)
 {
-	bool res = nrf_usbd_common_wakeup_req();
+	bool res = nrf_usbd_legacy_wakeup_req();
 
 	LOG_DBG("Host wakeup request");
 	if (!res) {
@@ -752,12 +1705,6 @@ static int udc_nrf_enable(const struct device *dev)
 	unsigned int key;
 	int ret;
 
-	ret = nrf_usbd_common_init(usbd_event_handler);
-	if (ret != NRFX_SUCCESS) {
-		LOG_ERR("nRF USBD driver initialization failed");
-		return -EIO;
-	}
-
 	if (udc_ep_enable_internal(dev, USB_CONTROL_EP_OUT,
 				   USB_EP_TYPE_CONTROL, UDC_NRF_EP0_SIZE, 0)) {
 		LOG_ERR("Failed to enable control endpoint");
@@ -779,7 +1726,7 @@ static int udc_nrf_enable(const struct device *dev)
 
 	/* Disable interrupts until USBD is enabled */
 	key = irq_lock();
-	nrf_usbd_common_enable();
+	nrf_usbd_legacy_enable();
 	irq_unlock(key);
 
 	return 0;
@@ -789,7 +1736,7 @@ static int udc_nrf_disable(const struct device *dev)
 {
 	int ret;
 
-	nrf_usbd_common_disable();
+	nrf_usbd_legacy_disable();
 
 	if (udc_ep_disable_internal(dev, USB_CONTROL_EP_OUT)) {
 		LOG_ERR("Failed to disable control endpoint");
@@ -801,8 +1748,6 @@ static int udc_nrf_disable(const struct device *dev)
 		return -EIO;
 	}
 
-	nrf_usbd_common_uninit();
-
 	ret = onoff_cancel_or_release(hfxo_mgr, &hfxo_cli);
 	if (ret < 0) {
 		LOG_ERR("Failed to stop HFXO %d", ret);
@@ -828,7 +1773,7 @@ static int udc_nrf_init(const struct device *dev)
 #endif
 
 	IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
-		    nrfx_isr, nrf_usbd_common_irq_handler, 0);
+		    nrfx_isr, nrf_usbd_irq_handler, 0);
 
 	(void)nrfx_power_init(&cfg->pwr);
 	nrfx_power_usbevt_init(&cfg->evt);
diff --git a/drivers/usb/udc/udc_numaker.c b/drivers/usb/udc/udc_numaker.c
index 736ded93fc5..983a9210b36 100644
--- a/drivers/usb/udc/udc_numaker.c
+++ b/drivers/usb/udc/udc_numaker.c
@@ -961,7 +961,7 @@ static int numaker_usbd_msg_handle_out(const struct device *dev, struct numaker_
 	__ASSERT_NO_MSG(msg->type == NUMAKER_USBD_MSG_TYPE_OUT);
 
 	ep = msg->out.ep;
-	ep_cfg = udc_get_ep_cfg(ep);
+	ep_cfg = udc_get_ep_cfg(dev, ep);
 
 	udc_ep_set_busy(ep_cfg, false);
 
@@ -1573,7 +1573,7 @@ static int udc_numaker_enable(const struct device *dev)
 
 static int udc_numaker_disable(const struct device *dev)
 {
-	LOG_DBG("Enable device %p", dev);
+	LOG_DBG("Disable device %p", dev);
 
 	/* S/W disconnect */
 	numaker_usbd_sw_disconnect(dev);
diff --git a/drivers/usb/udc/udc_renesas_ra.c b/drivers/usb/udc/udc_renesas_ra.c
index 60f32d86b30..4c9a9438db7 100644
--- a/drivers/usb/udc/udc_renesas_ra.c
+++ b/drivers/usb/udc/udc_renesas_ra.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,6 +17,8 @@ LOG_MODULE_REGISTER(udc_renesas_ra, CONFIG_UDC_DRIVER_LOG_LEVEL);
 
 struct udc_renesas_ra_config {
 	const struct pinctrl_dev_config *pcfg;
+	const struct device **clocks;
+	size_t num_of_clocks;
 	size_t num_of_eps;
 	struct udc_ep_config *ep_cfg_in;
 	struct udc_ep_config *ep_cfg_out;
@@ -491,7 +493,7 @@ static int udc_renesas_ra_disable(const struct device *dev)
 		return -EIO;
 	}
 
-	LOG_DBG("Enable device %p", dev);
+	LOG_DBG("Disable device %p", dev);
 
 	return 0;
 }
@@ -500,43 +502,6 @@ static int udc_renesas_ra_init(const struct device *dev)
 {
 	struct udc_renesas_ra_data *data = udc_get_private(dev);
 
-#if !USBHS_PHY_CLOCK_SOURCE_IS_XTAL
-	if (data->udc_cfg.usb_speed == USBD_SPEED_HS) {
-		LOG_ERR("High-speed operation is not supported in case PHY clock source is not "
-			"XTAL");
-		return -ENOTSUP;
-	}
-
-	uint32_t uclk_src = RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(uclk)));
-	uint32_t uclk_div = DT_PROP_OR(DT_NODELABEL(uclk), div, 1);
-	uint32_t u60clk_src = RA_CGC_CLK_SRC(DT_CLOCKS_CTLR(DT_NODELABEL(u60clk)));
-	uint32_t u60clk_div = DT_PROP_OR(DT_NODELABEL(u60clk), div, 1);
-
-	if (uclk_src == BSP_CLOCKS_CLOCK_DISABLED || u60clk_src == BSP_CLOCKS_CLOCK_DISABLED) {
-		LOG_ERR("PHY clock is not working");
-		return -EINVAL;
-	}
-
-	uint32_t uclk_clock_rate = R_BSP_SourceClockHzGet(uclk_src) / uclk_div;
-	uint32_t u60clk_clock_rate = R_BSP_SourceClockHzGet(u60clk_src) / u60clk_div;
-
-	if (uclk_clock_rate != 48000000) {
-		LOG_ERR("Setting for uclk should be 48Mhz");
-		return -ENOTSUP;
-	}
-
-	if (u60clk_clock_rate != 60000000) {
-		LOG_ERR("Setting for u60clk should be 60Mhz");
-		return -ENOTSUP;
-	}
-#endif
-
-	if (!(data->udc_cfg.usb_speed == USBD_SPEED_HS ||
-	      data->udc_cfg.usb_speed == USBD_SPEED_FS)) {
-		LOG_ERR("USB device mode support full-speed and high-speed only");
-		return -ENOTSUP;
-	}
-
 	if (FSP_SUCCESS != R_USBD_Open(&data->udc, &data->udc_cfg)) {
 		return -EIO;
 	}
@@ -551,7 +516,19 @@ static int udc_renesas_ra_init(const struct device *dev)
 		return -EIO;
 	}
 
-	irq_enable(data->udc_cfg.hs_irq);
+#if DT_HAS_COMPAT_STATUS_OKAY(renesas_ra_usbhs)
+	if (data->udc_cfg.hs_irq != (IRQn_Type)BSP_IRQ_DISABLED) {
+		irq_enable(data->udc_cfg.hs_irq);
+	}
+#endif
+
+	if (data->udc_cfg.irq != (IRQn_Type)BSP_IRQ_DISABLED) {
+		irq_enable(data->udc_cfg.irq);
+	}
+
+	if (data->udc_cfg.irq_r != (IRQn_Type)BSP_IRQ_DISABLED) {
+		irq_enable(data->udc_cfg.irq_r);
+	}
 
 	return 0;
 }
@@ -577,13 +554,86 @@ static int udc_renesas_ra_shutdown(const struct device *dev)
 	return 0;
 }
 
+static int udc_renesas_ra_clock_check(const struct device *dev)
+{
+	const struct udc_renesas_ra_config *config = dev->config;
+
+#if USBHS_PHY_CLOCK_SOURCE_IS_XTAL
+	if (config->speed_idx == UDC_BUS_SPEED_HS) {
+		if (BSP_CFG_XTAL_HZ == 0) {
+			LOG_ERR("XTAL clock should be provided");
+			return -EINVAL;
+		}
+
+		return 0;
+	}
+#endif
+
+	for (size_t i = 0; i < config->num_of_clocks; i++) {
+		const struct device *clock_dev = *(config->clocks + i);
+		const struct clock_control_ra_pclk_cfg *clock_cfg = clock_dev->config;
+		uint32_t clk_src_rate;
+		uint32_t clock_rate;
+
+		if (!device_is_ready(clock_dev)) {
+			LOG_ERR("%s is not ready", clock_dev->name);
+			return -ENODEV;
+		}
+
+		clk_src_rate = R_BSP_SourceClockHzGet(clock_cfg->clk_src);
+		clock_rate = clk_src_rate / clock_cfg->clk_div;
+
+		if (strcmp(clock_dev->name, "uclk") == 0 && clock_rate != MHZ(48)) {
+			LOG_ERR("Setting for uclk should be 48Mhz");
+			return -ENOTSUP;
+		}
+
+#if DT_HAS_COMPAT_STATUS_OKAY(renesas_ra_usbhs)
+		if (strcmp(clock_dev->name, "u60clk") == 0 && clock_rate != MHZ(60)) {
+			LOG_ERR("Setting for u60clk should be 60Mhz");
+			return -ENOTSUP;
+		}
+#endif
+	}
+
+	return 0;
+}
+
 static int udc_renesas_ra_driver_preinit(const struct device *dev)
 {
 	const struct udc_renesas_ra_config *config = dev->config;
+	struct udc_renesas_ra_data *priv = udc_get_private(dev);
 	struct udc_data *data = dev->data;
 	uint16_t mps = 1023;
 	int err;
 
+#if !USBHS_PHY_CLOCK_SOURCE_IS_XTAL
+	if (priv->udc_cfg.usb_speed == USBD_SPEED_HS) {
+		LOG_ERR("High-speed operation is not supported in case PHY clock source is not "
+			"XTAL");
+		return -ENOTSUP;
+	}
+#endif
+
+	if (config->speed_idx == UDC_BUS_SPEED_HS) {
+		if (!(priv->udc_cfg.usb_speed == USBD_SPEED_HS ||
+		      priv->udc_cfg.usb_speed == USBD_SPEED_FS)) {
+			LOG_ERR("USBHS module only support high-speed and full-speed device");
+			return -ENOTSUP;
+		}
+	} else {
+		/* config->speed_idx == UDC_BUS_SPEED_FS */
+		if (priv->udc_cfg.usb_speed != USBD_SPEED_FS) {
+			LOG_ERR("USBFS module only support full-speed device");
+			return -ENOTSUP;
+		}
+	}
+
+	err = udc_renesas_ra_clock_check(dev);
+	if (err < 0) {
+		return err;
+	}
+
 	err = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
 	if (err < 0) {
 		return err;
@@ -593,7 +643,7 @@ static int udc_renesas_ra_driver_preinit(const struct device *dev)
 
 	data->caps.rwup = true;
 	data->caps.mps0 = UDC_MPS0_64;
-	if (config->speed_idx == UDC_BUS_SPEED_HS) {
+	if (priv->udc_cfg.usb_speed == USBD_SPEED_HS) {
 		data->caps.hs = true;
 		mps = 1024;
 	}
@@ -638,8 +688,22 @@ static int udc_renesas_ra_driver_preinit(const struct device *dev)
 		}
 	}
 
+#if DT_HAS_COMPAT_STATUS_OKAY(renesas_ra_usbhs)
+	if (priv->udc_cfg.hs_irq != (IRQn_Type)BSP_IRQ_DISABLED) {
+		R_ICU->IELSR[priv->udc_cfg.hs_irq] = BSP_PRV_IELS_ENUM(EVENT_USBHS_USB_INT_RESUME);
+	}
+#endif
+
+	if (priv->udc_cfg.irq != (IRQn_Type)BSP_IRQ_DISABLED) {
+		R_ICU->IELSR[priv->udc_cfg.irq] = BSP_PRV_IELS_ENUM(EVENT_USBFS_INT);
+	}
+
+	if (priv->udc_cfg.irq_r != (IRQn_Type)BSP_IRQ_DISABLED) {
+		R_ICU->IELSR[priv->udc_cfg.irq_r] = BSP_PRV_IELS_ENUM(EVENT_USBFS_RESUME);
+	}
+
 	config->make_thread(dev);
-	LOG_INF("Device %p (max. speed %d)", dev, config->speed_idx);
+	LOG_INF("Device %p (max. speed %d)", dev, priv->udc_cfg.usb_speed);
 
 	return 0;
 }
@@ -674,32 +738,36 @@ static const struct udc_api udc_renesas_ra_api = {
 
 #define DT_DRV_COMPAT renesas_ra_udc
 
-#define USB_MODULE_NUMBER(n) ((DT_REG_ADDR(DT_INST_PARENT(n))) == R_USB_HS0_BASE ? 1 : 0)
+#define USB_RENESAS_RA_MODULE_NUMBER(id) (DT_REG_ADDR(id) == R_USB_FS0_BASE ? 0 : 1)
 
-#define RENESAS_RA_USB_IRQ_CONFIG_FUNC(n)                                                          \
-	static int udc_renesas_ra_irq_config_func_##n(const struct device *dev)                    \
-	{                                                                                          \
-		struct udc_renesas_ra_data *data = udc_get_private(dev);                           \
-                                                                                                   \
-		data->udc_cfg.hs_irq = DT_IRQ_BY_NAME(DT_INST_PARENT(n), usbhs_ir, irq);           \
-		data->udc_cfg.hsirq_d0 = DT_IRQ_BY_NAME(DT_INST_PARENT(n), usbhs_d0, irq);         \
-		data->udc_cfg.hsirq_d1 = DT_IRQ_BY_NAME(DT_INST_PARENT(n), usbhs_d1, irq);         \
-		data->udc_cfg.hsipl = DT_IRQ_BY_NAME(DT_INST_PARENT(n), usbhs_ir, priority);       \
-		data->udc_cfg.hsipl_d0 = DT_IRQ_BY_NAME(DT_INST_PARENT(n), usbhs_d0, priority);    \
-		data->udc_cfg.hsipl_d1 = DT_IRQ_BY_NAME(DT_INST_PARENT(n), usbhs_d1, priority);    \
-                                                                                                   \
-		R_ICU->IELSR[DT_IRQ_BY_NAME(DT_NODELABEL(usbhs), usbhs_ir, irq)] =                 \
-			ELC_EVENT_USBHS_USB_INT_RESUME;                                            \
-		IRQ_CONNECT(DT_IRQ_BY_NAME(DT_NODELABEL(usbhs), usbhs_ir, irq),                    \
-			    DT_IRQ_BY_NAME(DT_NODELABEL(usbhs), usbhs_ir, priority),               \
-			    udc_renesas_ra_interrupt_handler, DEVICE_DT_INST_GET(n), 0);           \
-		return 0;                                                                          \
-	}
+#define USB_RENESAS_RA_IRQ_GET(id, name, cell)                                                     \
+	COND_CODE_1(DT_IRQ_HAS_NAME(id, name), (DT_IRQ_BY_NAME(id, name, cell)),                   \
+		    ((IRQn_Type) BSP_IRQ_DISABLED))
+
+#define USB_RENESAS_RA_MAX_SPEED_IDX(id)                                                           \
+	(DT_NODE_HAS_COMPAT(id, renesas_ra_usbhs) ? UDC_BUS_SPEED_HS : UDC_BUS_SPEED_FS)
+
+#define USB_RENESAS_RA_SPEED_IDX(id)                                                               \
+	(DT_NODE_HAS_COMPAT(id, renesas_ra_usbhs)                                                  \
+		 ? DT_ENUM_IDX_OR(id, maximum_speed, UDC_BUS_SPEED_HS)                             \
+		 : DT_ENUM_IDX_OR(id, maximum_speed, UDC_BUS_SPEED_FS))
+
+#define USB_RENESAS_RA_IRQ_CONNECT(idx, n)                                                         \
+	IRQ_CONNECT(DT_IRQ_BY_IDX(DT_INST_PARENT(n), idx, irq),                                    \
+		    DT_IRQ_BY_IDX(DT_INST_PARENT(n), idx, priority),                               \
+		    udc_renesas_ra_interrupt_handler, DEVICE_DT_INST_GET(n), 0)
+
+#define USB_RENESAS_RA_CLOCKS_GET(idx, id)                                                         \
+	DEVICE_DT_GET_OR_NULL(DT_PHANDLE_BY_IDX(id, phys_clock, idx))
 
 #define UDC_RENESAS_RA_DEVICE_DEFINE(n)                                                            \
 	PINCTRL_DT_DEFINE(DT_INST_PARENT(n));                                                      \
 	K_THREAD_STACK_DEFINE(udc_renesas_ra_stack_##n, CONFIG_UDC_RENESAS_RA_STACK_SIZE);         \
-	RENESAS_RA_USB_IRQ_CONFIG_FUNC(n);                                                         \
+                                                                                                   \
+	static const struct device *udc_renesas_ra_clock_dev_##n[] = {                             \
+		LISTIFY(DT_PROP_LEN_OR(DT_INST_PARENT(n), phys_clock, 0),                          \
+			USB_RENESAS_RA_CLOCKS_GET, (,), DT_INST_PARENT(n))                         \
+	};                                                                                         \
                                                                                                    \
 	static void udc_renesas_ra_thread_##n(void *dev, void *arg1, void *arg2)                   \
 	{                                                                                          \
@@ -724,29 +792,38 @@ static const struct udc_api udc_renesas_ra_api = {
                                                                                                    \
 	static const struct udc_renesas_ra_config udc_renesas_ra_config_##n = {                    \
 		.pcfg = PINCTRL_DT_DEV_CONFIG_GET(DT_INST_PARENT(n)),                              \
+		.clocks = udc_renesas_ra_clock_dev_##n,                                            \
+		.num_of_clocks = DT_PROP_LEN_OR(DT_INST_PARENT(n), phys_clock, 0),                 \
 		.num_of_eps = DT_PROP(DT_INST_PARENT(n), num_bidir_endpoints),                     \
 		.ep_cfg_in = ep_cfg_in##n,                                                         \
 		.ep_cfg_out = ep_cfg_out##n,                                                       \
 		.make_thread = udc_renesas_ra_make_thread_##n,                                     \
-		.speed_idx = DT_ENUM_IDX_OR(DT_INST_PARENT(n), maximum_speed, UDC_BUS_SPEED_HS),   \
+		.speed_idx = USB_RENESAS_RA_MAX_SPEED_IDX(DT_INST_PARENT(n)),                      \
 	};                                                                                         \
                                                                                                    \
 	static struct udc_renesas_ra_data udc_priv_##n = {                                         \
 		.udc_cfg = {                                                                       \
-			.module_number = USB_MODULE_NUMBER(n),                                     \
-			.usb_speed = DT_ENUM_IDX_OR(DT_INST_PARENT(n), maximum_speed,              \
-						    UDC_BUS_SPEED_HS),                             \
+			.module_number = USB_RENESAS_RA_MODULE_NUMBER(DT_INST_PARENT(n)),          \
+			.usb_speed = USB_RENESAS_RA_SPEED_IDX(DT_INST_PARENT(n)),                  \
+			.irq = USB_RENESAS_RA_IRQ_GET(DT_INST_PARENT(n), usbfs_i, irq),            \
+			.irq_r = USB_RENESAS_RA_IRQ_GET(DT_INST_PARENT(n), usbfs_r, irq),          \
+			.hs_irq = USB_RENESAS_RA_IRQ_GET(DT_INST_PARENT(n), usbhs_ir, irq),        \
+			.ipl = USB_RENESAS_RA_IRQ_GET(DT_INST_PARENT(n), usbfs_i, priority),       \
+			.ipl_r = USB_RENESAS_RA_IRQ_GET(DT_INST_PARENT(n), usbfs_r, priority),     \
+			.hsipl = USB_RENESAS_RA_IRQ_GET(DT_INST_PARENT(n), usbhs_ir, priority),    \
 			.p_context = DEVICE_DT_INST_GET(n),                                        \
 			.p_callback = udc_renesas_ra_event_handler,                                \
-		}};                                                                                \
+		},                                                                                 \
+	};                                                                                         \
                                                                                                    \
 	static struct udc_data udc_data_##n = {                                                    \
 		.mutex = Z_MUTEX_INITIALIZER(udc_data_##n.mutex),                                  \
 		.priv = &udc_priv_##n,                                                             \
 	};                                                                                         \
+                                                                                                   \
 	int udc_renesas_ra_driver_preinit##n(const struct device *dev)                             \
 	{                                                                                          \
-		udc_renesas_ra_irq_config_func_##n(dev);                                           \
+		LISTIFY(DT_NUM_IRQS(DT_INST_PARENT(n)), USB_RENESAS_RA_IRQ_CONNECT, (;), n);       \
 		return udc_renesas_ra_driver_preinit(dev);                                         \
 	}                                                                                          \
                                                                                                    \
diff --git a/drivers/usb/udc/udc_rpi_pico.c b/drivers/usb/udc/udc_rpi_pico.c
index 763e5a3d802..31561f6fce6 100644
--- a/drivers/usb/udc/udc_rpi_pico.c
+++ b/drivers/usb/udc/udc_rpi_pico.c
@@ -17,6 +17,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/sys/mem_blocks.h>
 #include <zephyr/drivers/usb/udc.h>
+#include <zephyr/drivers/pinctrl.h>
 #include <zephyr/drivers/clock_control.h>
 
 #include <zephyr/logging/log.h>
@@ -33,6 +34,7 @@ struct rpi_pico_config {
 	void (*irq_enable_func)(const struct device *dev);
 	void (*irq_disable_func)(const struct device *dev);
 	const struct device *clk_dev;
+	struct pinctrl_dev_config *const pcfg;
 	clock_control_subsys_t clk_sys;
 };
 
@@ -41,32 +43,57 @@ struct rpi_pico_ep_data {
 	uint8_t next_pid;
 };
 
+enum rpi_pico_event_type {
+	/* Setup packet received */
+	RPI_PICO_EVT_SETUP,
+	/* Trigger new transfer (except control OUT) */
+	RPI_PICO_EVT_XFER_NEW,
+	/* Transfer for specific endpoint is finished */
+	RPI_PICO_EVT_XFER_FINISHED,
+};
+
 struct rpi_pico_data {
 	struct k_thread thread_data;
+	/*
+	 * events are events that the driver thread waits.
+	 * xfer_new and xfer_finished contain information on which endpoints
+	 * events RPI_PICO_EVT_XFER_NEW or RPI_PICO_EVT_XFER_FINISHED are
+	 * triggered. The mapping is bits 31..16 for IN endpoints and bits
+	 * 15..0 for OUT endpoints.
+	 */
+	struct k_event events;
+	atomic_t xfer_new;
+	atomic_t xfer_finished;
 	struct rpi_pico_ep_data out_ep[USB_NUM_ENDPOINTS];
 	struct rpi_pico_ep_data in_ep[USB_NUM_ENDPOINTS];
 	bool rwu_pending;
 	uint8_t setup[8];
 };
 
-enum rpi_pico_event_type {
-	/* Trigger next transfer, must not be used for control OUT */
-	RPI_PICO_EVT_XFER,
-	/* Setup packet received */
-	RPI_PICO_EVT_SETUP,
-	/* OUT transaction for specific endpoint is finished */
-	RPI_PICO_EVT_DOUT,
-	/* IN transaction for specific endpoint is finished */
-	RPI_PICO_EVT_DIN,
-};
+static inline int udc_ep_to_bnum(const uint8_t ep)
+{
+	if (USB_EP_DIR_IS_IN(ep)) {
+		return 16UL + USB_EP_GET_IDX(ep);
+	}
 
-struct rpi_pico_event {
-	const struct device *dev;
-	enum rpi_pico_event_type type;
-	uint8_t ep;
-};
+	return USB_EP_GET_IDX(ep);
+}
 
-K_MSGQ_DEFINE(drv_msgq, sizeof(struct rpi_pico_event), 16, sizeof(void *));
+static inline uint8_t udc_pull_ep_from_bmsk(uint32_t *const bitmap)
+{
+	unsigned int bit;
+
+	__ASSERT_NO_MSG(bitmap && *bitmap);
+
+	bit = find_lsb_set(*bitmap) - 1;
+	*bitmap &= ~BIT(bit);
+
+	if (bit >= 16) {
+		return USB_EP_DIR_IN | (bit - 16);
+	} else {
+		return USB_EP_DIR_OUT | bit;
+	}
+}
 
 /* Use Atomic Register Access to set bits */
 static void ALWAYS_INLINE rpi_pico_bit_set(const mm_reg_t reg, const uint32_t bit)
@@ -80,6 +107,19 @@ static void ALWAYS_INLINE rpi_pico_bit_clr(const mm_reg_t reg, const uint32_t bi
 	sys_write32(bit, REG_ALIAS_CLR_BITS | reg);
 }
 
+
+static void sie_dp_pullup(const struct device *dev, const bool enable)
+{
+	const struct rpi_pico_config *config = dev->config;
+	usb_hw_t *base = config->base;
+
+	if (enable) {
+		rpi_pico_bit_set((mm_reg_t)&base->sie_ctrl, USB_SIE_CTRL_PULLUP_EN_BITS);
+	} else {
+		rpi_pico_bit_clr((mm_reg_t)&base->sie_ctrl, USB_SIE_CTRL_PULLUP_EN_BITS);
+	}
+}
+
 static void ALWAYS_INLINE sie_status_clr(const struct device *dev, const uint32_t bit)
 {
 	const struct rpi_pico_config *config = dev->config;
@@ -163,6 +203,7 @@ static void write_ep_ctrl_reg(const struct device *dev, const uint8_t ep,
 static void rpi_pico_ep_cancel(const struct device *dev, const uint8_t ep)
 {
 	bool abort_handshake_supported = rp2040_chip_version() >= 2;
+	struct udc_ep_config *ep_cfg = udc_get_ep_cfg(dev, ep);
 	const struct rpi_pico_config *config = dev->config;
 	usb_hw_t *base = config->base;
 	mm_reg_t abort_done_reg = (mm_reg_t)&base->abort_done;
@@ -173,6 +214,7 @@ static void rpi_pico_ep_cancel(const struct device *dev, const uint8_t ep)
 	buf_ctrl = read_buf_ctrl_reg(dev, ep);
 	if (!(buf_ctrl & USB_BUF_CTRL_AVAIL)) {
 		/* The buffer is not used by the controller */
+		udc_ep_set_busy(ep_cfg, false);
 		return;
 	}
 
@@ -189,6 +231,7 @@ static void rpi_pico_ep_cancel(const struct device *dev, const uint8_t ep)
 		rpi_pico_bit_clr(abort_reg, ep_mask);
 	}
 
+	udc_ep_set_busy(ep_cfg, false);
 	LOG_INF("Canceled ep 0x%02x transaction", ep);
 }
 
@@ -196,6 +239,7 @@ static int rpi_pico_prep_rx(const struct device *dev,
 			    struct net_buf *const buf, struct udc_ep_config *const cfg)
 {
 	struct rpi_pico_ep_data *const ep_data = get_ep_data(dev, cfg->addr);
+	unsigned int lock_key;
 	uint32_t buf_ctrl;
 
 	buf_ctrl = read_buf_ctrl_reg(dev, cfg->addr);
@@ -207,6 +251,8 @@ static int rpi_pico_prep_rx(const struct device *dev,
 	LOG_DBG("Prepare RX ep 0x%02x len %u pid: %u",
 		cfg->addr, net_buf_tailroom(buf), ep_data->next_pid);
 
+	lock_key = irq_lock();
+
 	buf_ctrl = cfg->mps;
 	buf_ctrl |= ep_data->next_pid ? USB_BUF_CTRL_DATA1_PID : USB_BUF_CTRL_DATA0_PID;
 	ep_data->next_pid ^= 1U;
@@ -221,6 +267,8 @@ static int rpi_pico_prep_rx(const struct device *dev,
 	arch_nop();
 	write_buf_ctrl_reg(dev, cfg->addr, buf_ctrl | USB_BUF_CTRL_AVAIL);
 
+	irq_unlock(lock_key);
+
 	return 0;
 }
 
@@ -228,6 +276,7 @@ static int rpi_pico_prep_tx(const struct device *dev,
 			    struct net_buf *const buf, struct udc_ep_config *const cfg)
 {
 	struct rpi_pico_ep_data *const ep_data = get_ep_data(dev, cfg->addr);
+	unsigned int lock_key;
 	uint32_t buf_ctrl;
 	size_t len;
 
@@ -237,6 +286,8 @@ static int rpi_pico_prep_tx(const struct device *dev,
 		return -EBUSY;
 	}
 
+	lock_key = irq_lock();
+
 	len = MIN(cfg->mps, buf->len);
 	memcpy(ep_data->buf, buf->data, len);
 
@@ -258,6 +309,8 @@ static int rpi_pico_prep_tx(const struct device *dev,
 	arch_nop();
 	write_buf_ctrl_reg(dev, cfg->addr, buf_ctrl | USB_BUF_CTRL_AVAIL);
 
+	irq_unlock(lock_key);
+
 	return 0;
 }
 
@@ -423,6 +476,10 @@ static void rpi_pico_handle_xfer_next(const struct device *dev,
 	}
 
 	if (USB_EP_DIR_IS_OUT(cfg->addr)) {
+		if (cfg->stat.halted) {
+			return;
+		}
+
 		err = rpi_pico_prep_rx(dev, buf, cfg);
 	} else {
 		err = rpi_pico_prep_tx(dev, buf, cfg);
@@ -438,33 +495,64 @@ static void rpi_pico_handle_xfer_next(const struct device *dev,
 static ALWAYS_INLINE void rpi_pico_thread_handler(void *const arg)
 {
 	const struct device *dev = (const struct device *)arg;
+	struct rpi_pico_data *priv = udc_get_private(dev);
 	struct udc_ep_config *ep_cfg;
-	struct rpi_pico_event evt;
+	uint32_t evt;
+	uint32_t eps;
+	uint8_t ep;
 
-	k_msgq_get(&drv_msgq, &evt, K_FOREVER);
-	ep_cfg = udc_get_ep_cfg(dev, evt.ep);
+	evt = k_event_wait(&priv->events, UINT32_MAX, false, K_FOREVER);
+	udc_lock_internal(dev, K_FOREVER);
+
+	if (evt & BIT(RPI_PICO_EVT_XFER_FINISHED)) {
+		k_event_clear(&priv->events, BIT(RPI_PICO_EVT_XFER_FINISHED));
+
+		eps = atomic_clear(&priv->xfer_finished);
+
+		while (eps) {
+			ep = udc_pull_ep_from_bmsk(&eps);
+			ep_cfg = udc_get_ep_cfg(dev, ep);
+			LOG_DBG("Finished event ep 0x%02x", ep);
+
+			if (USB_EP_DIR_IS_IN(ep)) {
+				rpi_pico_handle_evt_din(dev, ep_cfg);
+			} else {
+				rpi_pico_handle_evt_dout(dev, ep_cfg);
+			}
+
+			if (!udc_ep_is_busy(ep_cfg)) {
+				rpi_pico_handle_xfer_next(dev, ep_cfg);
+			} else {
+				LOG_ERR("Endpoint 0x%02x busy", ep);
+			}
+		}
+	}
+
+	if (evt & BIT(RPI_PICO_EVT_XFER_NEW)) {
+		k_event_clear(&priv->events, BIT(RPI_PICO_EVT_XFER_NEW));
+
+		eps = atomic_clear(&priv->xfer_new);
+
+		while (eps) {
+			ep = udc_pull_ep_from_bmsk(&eps);
+			ep_cfg = udc_get_ep_cfg(dev, ep);
+			LOG_DBG("New transfer ep 0x%02x in the queue", ep);
+
+			if (!udc_ep_is_busy(ep_cfg)) {
+				rpi_pico_handle_xfer_next(dev, ep_cfg);
+			} else {
+				LOG_ERR("Endpoint 0x%02x busy", ep);
+			}
+		}
+	}
 
-	switch (evt.type) {
-	case RPI_PICO_EVT_XFER:
-		LOG_DBG("New transfer in the queue");
-		break;
-	case RPI_PICO_EVT_SETUP:
+	if (evt & BIT(RPI_PICO_EVT_SETUP)) {
+		k_event_clear(&priv->events, BIT(RPI_PICO_EVT_SETUP));
 		LOG_DBG("SETUP event");
 		rpi_pico_handle_evt_setup(dev);
-		break;
-	case RPI_PICO_EVT_DOUT:
-		LOG_DBG("DOUT event ep 0x%02x", ep_cfg->addr);
-		rpi_pico_handle_evt_dout(dev, ep_cfg);
-		break;
-	case RPI_PICO_EVT_DIN:
-		LOG_DBG("DIN event");
-		rpi_pico_handle_evt_din(dev, ep_cfg);
-		break;
 	}
 
-	if (ep_cfg->addr != USB_CONTROL_EP_OUT && !udc_ep_is_busy(ep_cfg)) {
-		rpi_pico_handle_xfer_next(dev, ep_cfg);
-	}
+	udc_unlock_internal(dev);
 }
 
 static void rpi_pico_handle_setup(const struct device *dev)
@@ -472,11 +560,6 @@ static void rpi_pico_handle_setup(const struct device *dev)
 	const struct rpi_pico_config *config = dev->config;
 	struct rpi_pico_data *priv = udc_get_private(dev);
 	usb_device_dpram_t *dpram = config->dpram;
-	struct rpi_pico_event evt = {
-		.type = RPI_PICO_EVT_SETUP,
-		.ep = USB_CONTROL_EP_OUT,
-	};
-
 	/*
 	 * Host may issue a new setup packet even if the previous control transfer
 	 * did not complete. Cancel any active transaction.
@@ -491,16 +574,13 @@ static void rpi_pico_handle_setup(const struct device *dev)
 	get_ep_data(dev, USB_CONTROL_EP_IN)->next_pid = 1;
 	get_ep_data(dev, USB_CONTROL_EP_OUT)->next_pid = 1;
 
-	k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
+	k_event_post(&priv->events, BIT(RPI_PICO_EVT_SETUP));
 }
 
 static void rpi_pico_handle_buff_status_in(const struct device *dev, const uint8_t ep)
 {
 	struct udc_ep_config *ep_cfg = udc_get_ep_cfg(dev, ep);
-	struct rpi_pico_event evt = {
-		.ep = ep,
-		.type = RPI_PICO_EVT_DIN,
-	};
+	struct rpi_pico_data *priv = udc_get_private(dev);
 	__maybe_unused int err;
 	struct net_buf *buf;
 	size_t len;
@@ -524,7 +604,8 @@ static void rpi_pico_handle_buff_status_in(const struct device *dev, const uint8
 			__ASSERT(err == 0, "Failed to start new IN transaction");
 			udc_ep_buf_clear_zlp(buf);
 		} else {
-			k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
+			atomic_set_bit(&priv->xfer_finished, udc_ep_to_bnum(ep));
+			k_event_post(&priv->events, BIT(RPI_PICO_EVT_XFER_FINISHED));
 		}
 	}
 }
@@ -533,10 +614,7 @@ static void rpi_pico_handle_buff_status_out(const struct device *dev, const uint
 {
 	struct rpi_pico_ep_data *ep_data = get_ep_data(dev, ep);
 	struct udc_ep_config *ep_cfg = udc_get_ep_cfg(dev, ep);
-	struct rpi_pico_event evt = {
-		.ep = ep,
-		.type = RPI_PICO_EVT_DOUT,
-	};
+	struct rpi_pico_data *priv = udc_get_private(dev);
 	struct net_buf *buf;
 	size_t len;
 
@@ -550,14 +628,14 @@ static void rpi_pico_handle_buff_status_out(const struct device *dev, const uint
 	len = read_buf_ctrl_reg(dev, ep) & USB_BUF_CTRL_LEN_MASK;
 	net_buf_add_mem(buf, ep_data->buf, MIN(len, net_buf_tailroom(buf)));
 
-	if (net_buf_tailroom(buf) >= udc_mps_ep_size(ep_cfg) &&
-	    len == udc_mps_ep_size(ep_cfg)) {
+	if (net_buf_tailroom(buf) && len == udc_mps_ep_size(ep_cfg)) {
 		__unused int err;
 
 		err = rpi_pico_prep_rx(dev, buf, ep_cfg);
 		__ASSERT(err == 0, "Failed to start new OUT transaction");
 	} else {
-		k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
+		atomic_set_bit(&priv->xfer_finished, udc_ep_to_bnum(ep));
+		k_event_post(&priv->events, BIT(RPI_PICO_EVT_XFER_FINISHED));
 	}
 }
 
@@ -575,6 +653,7 @@ static void rpi_pico_handle_buff_status(const struct device *dev)
 			continue;
 		}
 
+		rpi_pico_bit_clr((mm_reg_t)&base->buf_status, BIT(i));
 		/* Odd bits in the register correspond to OUT endpoints */
 		if (i & 1U) {
 			ep = USB_EP_DIR_OUT | (i >> 1U);
@@ -584,7 +663,6 @@ static void rpi_pico_handle_buff_status(const struct device *dev)
 			rpi_pico_handle_buff_status_in(dev, ep);
 		}
 
-		rpi_pico_bit_clr((mm_reg_t)&base->buf_status, BIT(i));
 		buf_status &= ~BIT(i);
 	}
 }
@@ -592,6 +670,7 @@ static void rpi_pico_handle_buff_status(const struct device *dev)
 static void rpi_pico_isr_handler(const struct device *dev)
 {
 	const struct rpi_pico_config *config = dev->config;
+	const struct pinctrl_dev_config *const pcfg = config->pcfg;
 	struct rpi_pico_data *priv = udc_get_private(dev);
 	usb_hw_t *base = config->base;
 	uint32_t status = base->ints;
@@ -605,15 +684,35 @@ static void rpi_pico_isr_handler(const struct device *dev)
 	if (status & USB_INTS_DEV_CONN_DIS_BITS) {
 		uint32_t sie_status;
 
+		sie_status = sys_read32((mm_reg_t)&base->sie_status);
+		LOG_DBG("CONNECTED bit %u, VBUS_DETECTED bit %u",
+			(bool)(sie_status & USB_SIE_STATUS_CONNECTED_BITS),
+			(bool)(sie_status & USB_SIE_STATUS_VBUS_DETECTED_BITS));
+
+		if (pcfg != NULL && !(sie_status & USB_SIE_STATUS_CONNECTED_BITS) &&
+		    !(sie_status & USB_SIE_STATUS_VBUS_DETECTED_BITS)) {
+			sie_dp_pullup(dev, false);
+			udc_submit_event(dev, UDC_EVT_VBUS_REMOVED, 0);
+		}
+
 		handled |= USB_INTS_DEV_CONN_DIS_BITS;
 		sie_status_clr(dev, USB_SIE_STATUS_CONNECTED_BITS);
+	}
+
+	if (status & USB_INTS_VBUS_DETECT_BITS) {
+		uint32_t sie_status;
 
 		sie_status = sys_read32((mm_reg_t)&base->sie_status);
-		if (sie_status & USB_SIE_STATUS_CONNECTED_BITS) {
+		LOG_DBG("VBUS_DETECTED bit %u",
+			(bool)(sie_status & USB_SIE_STATUS_VBUS_DETECTED_BITS));
+
+		if (pcfg != NULL && (sie_status & USB_SIE_STATUS_VBUS_DETECTED_BITS)) {
+			sie_dp_pullup(dev, true);
 			udc_submit_event(dev, UDC_EVT_VBUS_READY, 0);
-		} else {
-			udc_submit_event(dev, UDC_EVT_VBUS_REMOVED, 0);
 		}
+
+		handled |= USB_INTS_VBUS_DETECT_BITS;
+		sie_status_clr(dev, USB_SIE_STATUS_VBUS_DETECTED_BITS);
 	}
 
 	if ((status & (USB_INTS_BUFF_STATUS_BITS | USB_INTS_SETUP_REQ_BITS)) &&
@@ -633,6 +732,7 @@ static void rpi_pico_isr_handler(const struct device *dev)
 		sie_status_clr(dev, USB_SIE_STATUS_RESUME_BITS);
 
 		priv->rwu_pending = false;
+		udc_set_suspended(dev, false);
 		udc_submit_event(dev, UDC_EVT_RESUME, 0);
 	}
 
@@ -640,6 +740,7 @@ static void rpi_pico_isr_handler(const struct device *dev)
 		handled |= USB_INTS_DEV_SUSPEND_BITS;
 		sie_status_clr(dev, USB_SIE_STATUS_SUSPENDED_BITS);
 
+		udc_set_suspended(dev, true);
 		udc_submit_event(dev, UDC_EVT_SUSPEND, 0);
 	}
 
@@ -654,9 +755,13 @@ static void rpi_pico_isr_handler(const struct device *dev)
 	if (status & USB_INTS_ERROR_DATA_SEQ_BITS) {
 		handled |= USB_INTS_ERROR_DATA_SEQ_BITS;
 		sie_status_clr(dev, USB_SIE_STATUS_DATA_SEQ_ERROR_BITS);
-
-		LOG_ERR("Data Sequence Error");
-		udc_submit_event(dev, UDC_EVT_ERROR, -EINVAL);
+		/*
+		 * This can be triggered before the STALL handshake response
+		 * to the OUT DATAx. Handling IRQ_ON_STALL to fix the expected
+		 * DATA PID is too much overhead since the endpoint is halted
+		 * anyway.
+		 */
+		LOG_WRN("Data Sequence Error");
 	}
 
 	if (status & USB_INTS_ERROR_RX_TIMEOUT_BITS) {
@@ -718,15 +823,13 @@ static int udc_rpi_pico_ep_enqueue(const struct device *dev,
 				   struct udc_ep_config *const cfg,
 				   struct net_buf *buf)
 {
-	struct rpi_pico_event evt = {
-		.ep = cfg->addr,
-		.type = RPI_PICO_EVT_XFER,
-	};
+	struct rpi_pico_data *priv = udc_get_private(dev);
 
 	udc_buf_put(cfg, buf);
 
 	if (!cfg->stat.halted) {
-		k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
+		atomic_set_bit(&priv->xfer_new, udc_ep_to_bnum(cfg->addr));
+		k_event_post(&priv->events, BIT(RPI_PICO_EVT_XFER_NEW));
 	}
 
 	return 0;
@@ -818,21 +921,39 @@ static int udc_rpi_pico_ep_set_halt(const struct device *dev,
 	const struct rpi_pico_config *config = dev->config;
 	mem_addr_t buf_ctrl_reg = get_buf_ctrl_reg(dev, cfg->addr);
 	usb_hw_t *base = config->base;
+	unsigned int lock_key;
+	uint32_t bits;
 
+	lock_key = irq_lock();
 	if (USB_EP_GET_IDX(cfg->addr) == 0) {
-		uint32_t bit = USB_EP_DIR_IS_OUT(cfg->addr) ?
-			       USB_EP_STALL_ARM_EP0_OUT_BITS : USB_EP_STALL_ARM_EP0_IN_BITS;
+		bits = USB_EP_DIR_IS_OUT(cfg->addr) ?
+		       USB_EP_STALL_ARM_EP0_OUT_BITS : USB_EP_STALL_ARM_EP0_IN_BITS;
+		rpi_pico_bit_set((mm_reg_t)&base->ep_stall_arm, bits);
+	}
 
-		rpi_pico_bit_set((mm_reg_t)&base->ep_stall_arm, bit);
+	if (USB_EP_DIR_IS_OUT(cfg->addr)) {
+		/*
+		 * Cancel any transfer in progress.  The available bit must be
+		 * set for the controller to respond to OUT DATAx with a STALL
+		 * handshake.
+		 */
+		rpi_pico_ep_cancel(dev, cfg->addr);
+		bits = USB_BUF_CTRL_STALL | USB_BUF_CTRL_AVAIL;
+	} else {
+		/* Only STALL bit needs to be set here. */
+		bits = USB_BUF_CTRL_STALL;
 	}
 
-	rpi_pico_bit_set(buf_ctrl_reg, USB_BUF_CTRL_STALL);
+	rpi_pico_bit_set(buf_ctrl_reg, bits);
 
-	LOG_INF("Set halt ep 0x%02x", cfg->addr);
 	if (USB_EP_GET_IDX(cfg->addr) != 0) {
 		cfg->stat.halted = true;
 	}
 
+	irq_unlock(lock_key);
+	LOG_DBG("Set halt ep 0x%02x buf_ctrl 0x%08x busy %u",
+		cfg->addr, sys_read32(buf_ctrl_reg), udc_ep_is_busy(cfg));
+
 	return 0;
 }
 
@@ -840,32 +961,35 @@ static int udc_rpi_pico_ep_clear_halt(const struct device *dev,
 				      struct udc_ep_config *const cfg)
 {
 	struct rpi_pico_ep_data *const ep_data = get_ep_data(dev, cfg->addr);
+	struct rpi_pico_data *priv = udc_get_private(dev);
 	mem_addr_t buf_ctrl_reg = get_buf_ctrl_reg(dev, cfg->addr);
-	struct rpi_pico_event evt = {
-		.ep = cfg->addr,
-		.type = RPI_PICO_EVT_XFER,
-	};
+	unsigned int lock_key;
 
-	if (USB_EP_GET_IDX(cfg->addr) != 0) {
-		ep_data->next_pid = 0;
-		rpi_pico_bit_clr(buf_ctrl_reg, USB_BUF_CTRL_DATA1_PID);
-		/*
-		 * By default, clk_sys runs at 125MHz, wait 3 nop instructions
-		 * before clearing the CTRL_STALL bit. See 4.1.2.5.4.
-		 */
-		arch_nop();
-		arch_nop();
-		arch_nop();
-		rpi_pico_bit_clr(buf_ctrl_reg, USB_BUF_CTRL_STALL);
+	if (USB_EP_GET_IDX(cfg->addr) == 0) {
+		return 0;
+	}
 
-		if (udc_buf_peek(cfg)) {
-			k_msgq_put(&drv_msgq, &evt, K_NO_WAIT);
-		}
+	lock_key = irq_lock();
+	if (USB_EP_DIR_IS_OUT(cfg->addr)) {
+		/* Cancel responds with a STALL handshake.*/
+		rpi_pico_ep_cancel(dev, cfg->addr);
+	} else {
+		rpi_pico_bit_clr(buf_ctrl_reg, USB_BUF_CTRL_STALL);
 	}
 
+	ep_data->next_pid = 0;
 	cfg->stat.halted = false;
-	LOG_INF("Clear halt ep 0x%02x buf_ctrl 0x%08x",
-		cfg->addr, sys_read32(buf_ctrl_reg));
+	irq_unlock(lock_key);
+
+	if (udc_ep_is_busy(cfg)) {
+		rpi_pico_handle_xfer_next(dev, cfg);
+	} else if (udc_buf_peek(cfg)) {
+		atomic_set_bit(&priv->xfer_new, udc_ep_to_bnum(cfg->addr));
+		k_event_post(&priv->events, BIT(RPI_PICO_EVT_XFER_NEW));
+	}
+
+	LOG_DBG("Clear halt ep 0x%02x buf_ctrl 0x%08x busy %u",
+		cfg->addr, sys_read32(buf_ctrl_reg), udc_ep_is_busy(cfg));
 
 	return 0;
 }
@@ -898,6 +1022,7 @@ static int udc_rpi_pico_host_wakeup(const struct device *dev)
 static int udc_rpi_pico_enable(const struct device *dev)
 {
 	const struct rpi_pico_config *config = dev->config;
+	const struct pinctrl_dev_config *const pcfg = config->pcfg;
 	usb_device_dpram_t *dpram = config->dpram;
 	usb_hw_t *base = config->base;
 
@@ -913,9 +1038,11 @@ static int udc_rpi_pico_enable(const struct device *dev)
 	sys_write32(USB_USB_MUXING_TO_PHY_BITS | USB_USB_MUXING_SOFTCON_BITS,
 		    (mm_reg_t)&base->muxing);
 
-	/* Force VBUS detect so the device thinks it is plugged into a host */
-	sys_write32(USB_USB_PWR_VBUS_DETECT_BITS | USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS,
-		    (mm_reg_t)&base->pwr);
+	if (pcfg == NULL) {
+		/* Force VBUS detect so the device thinks it is plugged into a host */
+		sys_write32(USB_USB_PWR_VBUS_DETECT_BITS |
+			    USB_USB_PWR_VBUS_DETECT_OVERRIDE_EN_BITS, (mm_reg_t)&base->pwr);
+	}
 
 	/* Enable an interrupt per EP0 transaction */
 	sys_write32(USB_SIE_CTRL_EP0_INT_1BUF_BITS, (mm_reg_t)&base->sie_ctrl);
@@ -936,8 +1063,10 @@ static int udc_rpi_pico_enable(const struct device *dev)
 		    USB_INTE_BUFF_STATUS_BITS,
 		    (mm_reg_t)&base->inte);
 
-	/* Present full speed device by enabling pull up on DP */
-	rpi_pico_bit_set((mm_reg_t)&base->sie_ctrl, USB_SIE_CTRL_PULLUP_EN_BITS);
+	if (sys_read32((mm_reg_t)&base->sie_status) & USB_SIE_STATUS_VBUS_DETECTED_BITS) {
+		/* Present full speed device by enabling pull up on DP */
+		sie_dp_pullup(dev, true);
+	}
 
 	/* Enable the USB controller in device mode. */
 	sys_write32(USB_MAIN_CTRL_CONTROLLER_EN_BITS, (mm_reg_t)&base->main_ctrl);
@@ -954,7 +1083,7 @@ static int udc_rpi_pico_disable(const struct device *dev)
 	const struct rpi_pico_config *config = dev->config;
 
 	config->irq_disable_func(dev);
-	LOG_DBG("Enable device %p", dev);
+	LOG_DBG("Disable device %p", dev);
 
 	return 0;
 }
@@ -962,6 +1091,8 @@ static int udc_rpi_pico_disable(const struct device *dev)
 static int udc_rpi_pico_init(const struct device *dev)
 {
 	const struct rpi_pico_config *config = dev->config;
+	const struct pinctrl_dev_config *const pcfg = config->pcfg;
+	int err;
 
 	if (udc_ep_enable_internal(dev, USB_CONTROL_EP_OUT,
 				   USB_EP_TYPE_CONTROL, 64, 0)) {
@@ -975,6 +1106,14 @@ static int udc_rpi_pico_init(const struct device *dev)
 		return -EIO;
 	}
 
+	if (pcfg != NULL) {
+		err = pinctrl_apply_state(pcfg, PINCTRL_STATE_DEFAULT);
+		if (err) {
+			LOG_ERR("Failed to apply default pinctrl state (%d)", err);
+			return err;
+		}
+	}
+
 	return clock_control_on(config->clk_dev, config->clk_sys);
 }
 
@@ -998,11 +1137,15 @@ static int udc_rpi_pico_shutdown(const struct device *dev)
 static int udc_rpi_pico_driver_preinit(const struct device *dev)
 {
 	const struct rpi_pico_config *config = dev->config;
+	struct rpi_pico_data *priv = udc_get_private(dev);
 	struct udc_data *data = dev->data;
 	uint16_t mps = 1023;
 	int err;
 
 	k_mutex_init(&data->mutex);
+	k_event_init(&priv->events);
+	atomic_clear(&priv->xfer_new);
+	atomic_clear(&priv->xfer_finished);
 
 	data->caps.rwup = true;
 	data->caps.mps0 = UDC_MPS0_64;
@@ -1054,12 +1197,14 @@ static int udc_rpi_pico_driver_preinit(const struct device *dev)
 
 static void udc_rpi_pico_lock(const struct device *dev)
 {
+	k_sched_lock();
 	udc_lock_internal(dev, K_FOREVER);
 }
 
 static void udc_rpi_pico_unlock(const struct device *dev)
 {
 	udc_unlock_internal(dev);
+	k_sched_unlock();
 }
 
 static const struct udc_api udc_rpi_pico_api = {
@@ -1081,7 +1226,16 @@ static const struct udc_api udc_rpi_pico_api = {
 
 #define DT_DRV_COMPAT raspberrypi_pico_usbd
 
+#define UDC_RPI_PICO_PINCTRL_DT_INST_DEFINE(n)						\
+	COND_CODE_1(DT_INST_PINCTRL_HAS_NAME(n, default),				\
+		    (PINCTRL_DT_INST_DEFINE(n)), ())
+
+#define UDC_RPI_PICO_PINCTRL_DT_INST_DEV_CONFIG_GET(n)					\
+	COND_CODE_1(DT_INST_PINCTRL_HAS_NAME(n, default),				\
+		    ((void *)PINCTRL_DT_INST_DEV_CONFIG_GET(n)), (NULL))
+
 #define UDC_RPI_PICO_DEVICE_DEFINE(n)							\
+	UDC_RPI_PICO_PINCTRL_DT_INST_DEFINE(n);						\
 	K_THREAD_STACK_DEFINE(udc_rpi_pico_stack_##n, CONFIG_UDC_RPI_PICO_STACK_SIZE);	\
 											\
 	SYS_MEM_BLOCKS_DEFINE_STATIC_WITH_EXT_BUF(rpi_pico_mb_##n,			\
@@ -1139,6 +1293,7 @@ static const struct udc_api udc_rpi_pico_api = {
 		.make_thread = udc_rpi_pico_make_thread_##n,				\
 		.irq_enable_func = udc_rpi_pico_irq_enable_func_##n,			\
 		.irq_disable_func = udc_rpi_pico_irq_disable_func_##n,			\
+		.pcfg = UDC_RPI_PICO_PINCTRL_DT_INST_DEV_CONFIG_GET(n),			\
 		.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)),			\
 		.clk_sys = (void *)DT_INST_PHA_BY_IDX(n, clocks, 0, clk_id),		\
 	};										\
diff --git a/drivers/usb/udc/udc_skeleton.c b/drivers/usb/udc/udc_skeleton.c
index 86c7cdc75f7..c808cc98ad8 100644
--- a/drivers/usb/udc/udc_skeleton.c
+++ b/drivers/usb/udc/udc_skeleton.c
@@ -209,7 +209,7 @@ static int udc_skeleton_enable(const struct device *dev)
 
 static int udc_skeleton_disable(const struct device *dev)
 {
-	LOG_DBG("Enable device %p", dev);
+	LOG_DBG("Disable device %p", dev);
 
 	return 0;
 }
@@ -363,7 +363,8 @@ static const struct udc_api udc_skeleton_api = {
  * driver, even if your platform does not require it.
  */
 #define UDC_SKELETON_DEVICE_DEFINE(n)						\
-	K_THREAD_STACK_DEFINE(udc_skeleton_stack_##n, CONFIG_UDC_SKELETON);	\
+	K_THREAD_STACK_DEFINE(udc_skeleton_stack_##n,				\
+			      CONFIG_UDC_SKELETON_STACK_SIZE);			\
 										\
 	static void udc_skeleton_thread_##n(void *dev, void *arg1, void *arg2)	\
 	{									\
diff --git a/drivers/usb/udc/udc_stm32.c b/drivers/usb/udc/udc_stm32.c
index 99136d1ba44..bec4860c375 100644
--- a/drivers/usb/udc/udc_stm32.c
+++ b/drivers/usb/udc/udc_stm32.c
@@ -23,8 +23,6 @@
 
 #include "udc_common.h"
 
-#include "stm32_hsem.h"
-
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(udc_stm32, CONFIG_UDC_DRIVER_LOG_LEVEL);
 
@@ -39,9 +37,32 @@ LOG_MODULE_REGISTER(udc_stm32, CONFIG_UDC_DRIVER_LOG_LEVEL);
 #define UDC_STM32_IRQ_NAME     usb
 #endif
 
+#define UDC_STM32_BASE_ADDRESS	DT_INST_REG_ADDR(0)
 #define UDC_STM32_IRQ		DT_INST_IRQ_BY_NAME(0, UDC_STM32_IRQ_NAME, irq)
 #define UDC_STM32_IRQ_PRI	DT_INST_IRQ_BY_NAME(0, UDC_STM32_IRQ_NAME, priority)
 
+#define USB_OTG_HS_EMB_PHY (DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) && \
+			    DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs))
+
+#define USB_OTG_HS_ULPI_PHY (DT_HAS_COMPAT_STATUS_OKAY(usb_ulpi_phy) && \
+			    DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs))
+
+/**
+ * The following defines are used to map the value of the "maxiumum-speed"
+ * DT property to the corresponding definition used by the STM32 HAL.
+ */
+#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(USB_OTG_HS_EMB_PHY)
+#define UDC_STM32_HIGH_SPEED             USB_OTG_SPEED_HIGH_IN_FULL
+#else
+#define UDC_STM32_HIGH_SPEED             USB_OTG_SPEED_HIGH
+#endif
+
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usb)
+#define UDC_STM32_FULL_SPEED             PCD_SPEED_FULL
+#else
+#define UDC_STM32_FULL_SPEED             USB_OTG_SPEED_FULL
+#endif
+
 struct udc_stm32_data  {
 	PCD_HandleTypeDef pcd;
 	const struct device *dev;
@@ -50,6 +71,8 @@ struct udc_stm32_data  {
 	void (*pcd_prepare)(const struct device *dev);
 	int (*clk_enable)(void);
 	int (*clk_disable)(void);
+	struct k_thread thread_data;
+	struct k_msgq msgq_data;
 };
 
 struct udc_stm32_config {
@@ -58,6 +81,19 @@ struct udc_stm32_config {
 	uint32_t dram_size;
 	uint16_t ep0_mps;
 	uint16_t ep_mps;
+	int speed_idx;
+};
+
+enum udc_stm32_msg_type {
+	UDC_STM32_MSG_SETUP,
+	UDC_STM32_MSG_DATA_OUT,
+	UDC_STM32_MSG_DATA_IN,
+};
+
+struct udc_stm32_msg {
+	uint8_t type;
+	uint8_t ep;
+	uint16_t rx_count;
 };
 
 static void udc_stm32_lock(const struct device *dev)
@@ -125,6 +161,26 @@ void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
 	udc_submit_event(priv->dev, UDC_EVT_RESUME, 0);
 }
 
+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
+{
+	struct udc_stm32_data *priv = hpcd2data(hpcd);
+	struct udc_stm32_msg msg = {.type = UDC_STM32_MSG_SETUP};
+	int err;
+
+	err = k_msgq_put(&priv->msgq_data, &msg, K_NO_WAIT);
+
+	if (err < 0) {
+		LOG_ERR("UDC Message queue overrun");
+	}
+}
+
+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+{
+	struct udc_stm32_data *priv = hpcd2data(hpcd);
+
+	udc_submit_event(priv->dev, UDC_EVT_SOF, 0);
+}
+
 static int usbd_ctrl_feed_dout(const struct device *dev, const size_t length)
 {
 	struct udc_stm32_data *priv = udc_get_private(dev);
@@ -143,55 +199,12 @@ static int usbd_ctrl_feed_dout(const struct device *dev, const size_t length)
 	return 0;
 }
 
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
-{
-	struct udc_stm32_data *priv = hpcd2data(hpcd);
-	struct usb_setup_packet *setup = (void *)priv->pcd.Setup;
-	const struct device *dev = priv->dev;
-	struct net_buf *buf;
-	int err;
-
-	buf = udc_ctrl_alloc(dev, USB_CONTROL_EP_OUT,
-			     sizeof(struct usb_setup_packet));
-	if (buf == NULL) {
-		LOG_ERR("Failed to allocate for setup");
-		return;
-	}
-
-	udc_ep_buf_set_setup(buf);
-	memcpy(buf->data, setup, 8);
-	net_buf_add(buf, 8);
-
-	udc_ctrl_update_stage(dev, buf);
-
-	if (!buf->len) {
-		return;
-	}
-
-	if ((setup->bmRequestType == 0) &&
-	    (setup->bRequest == USB_SREQ_SET_ADDRESS)) {
-		/* HAL requires we set the address before submitting status */
-		HAL_PCD_SetAddress(&priv->pcd, setup->wValue);
-	}
-
-	if (udc_ctrl_stage_is_data_out(dev)) {
-		/*  Allocate and feed buffer for data OUT stage */
-		err = usbd_ctrl_feed_dout(dev, udc_data_stage_length(buf));
-		if (err == -ENOMEM) {
-			udc_submit_ep_event(dev, buf, err);
-		}
-	} else if (udc_ctrl_stage_is_data_in(dev)) {
-		udc_ctrl_submit_s_in_status(dev);
-	} else {
-		udc_ctrl_submit_s_status(dev);
-	}
-}
-
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
+static void udc_stm32_flush_tx_fifo(const struct device *dev)
 {
-	struct udc_stm32_data *priv = hpcd2data(hpcd);
+	struct udc_stm32_data *priv = udc_get_private(dev);
+	struct udc_ep_config *cfg = udc_get_ep_cfg(dev, USB_CONTROL_EP_OUT);
 
-	udc_submit_event(priv->dev, UDC_EVT_SOF, 0);
+	HAL_PCD_EP_Receive(&priv->pcd, cfg->addr, NULL, 0);
 }
 
 static int udc_stm32_tx(const struct device *dev, struct udc_ep_config *epcfg,
@@ -230,7 +243,11 @@ static int udc_stm32_tx(const struct device *dev, struct udc_ep_config *epcfg,
 		/* Wait for an empty package from the host.
 		 * This also flushes the TX FIFO to the host.
 		 */
-		usbd_ctrl_feed_dout(dev, 0);
+		if (DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usb)) {
+			udc_stm32_flush_tx_fifo(dev);
+		} else {
+			usbd_ctrl_feed_dout(dev, 0);
+		}
 	}
 
 	return 0;
@@ -263,6 +280,36 @@ void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 {
 	uint32_t rx_count = HAL_PCD_EP_GetRxCount(hpcd, epnum);
 	struct udc_stm32_data *priv = hpcd2data(hpcd);
+	struct udc_stm32_msg msg = {
+		.type = UDC_STM32_MSG_DATA_OUT,
+		.ep = epnum,
+		.rx_count = rx_count,
+	};
+	int err;
+
+	err = k_msgq_put(&priv->msgq_data, &msg, K_NO_WAIT);
+	if (err != 0) {
+		LOG_ERR("UDC Message queue overrun");
+	}
+}
+
+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+{
+	struct udc_stm32_data *priv = hpcd2data(hpcd);
+	struct udc_stm32_msg msg = {
+		.type = UDC_STM32_MSG_DATA_IN,
+		.ep = epnum,
+	};
+	int err;
+
+	err = k_msgq_put(&priv->msgq_data, &msg, K_NO_WAIT);
+	if (err != 0) {
+		LOG_ERR("UDC Message queue overrun");
+	}
+}
+
+static void handle_msg_data_out(struct udc_stm32_data *priv, uint8_t epnum, uint16_t rx_count)
+{
 	const struct device *dev = priv->dev;
 	struct udc_ep_config *epcfg;
 	uint8_t ep = epnum | USB_EP_DIR_OUT;
@@ -302,9 +349,8 @@ void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 	}
 }
 
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
+static void handle_msg_data_in(struct udc_stm32_data *priv, uint8_t epnum)
 {
-	struct udc_stm32_data *priv = hpcd2data(hpcd);
 	const struct device *dev = priv->dev;
 	struct udc_ep_config *epcfg;
 	uint8_t ep = epnum | USB_EP_DIR_IN;
@@ -332,7 +378,7 @@ void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 		return;
 	}
 
-	if (udc_ep_buf_has_zlp(buf) && ep != USB_CONTROL_EP_IN) {
+	if (udc_ep_buf_has_zlp(buf)) {
 		udc_ep_buf_clear_zlp(buf);
 		HAL_PCD_EP_Transmit(&priv->pcd, ep, buf->data, 0);
 
@@ -370,6 +416,69 @@ void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
 	}
 }
 
+static void handle_msg_setup(struct udc_stm32_data *priv)
+{
+	struct usb_setup_packet *setup = (void *)priv->pcd.Setup;
+	const struct device *dev = priv->dev;
+	struct net_buf *buf;
+	int err;
+
+	buf = udc_ctrl_alloc(dev, USB_CONTROL_EP_OUT, sizeof(struct usb_setup_packet));
+	if (buf == NULL) {
+		LOG_ERR("Failed to allocate for setup");
+		return;
+	}
+
+	udc_ep_buf_set_setup(buf);
+	memcpy(buf->data, setup, 8);
+	net_buf_add(buf, 8);
+
+	udc_ctrl_update_stage(dev, buf);
+
+	if (!buf->len) {
+		return;
+	}
+
+	if ((setup->bmRequestType == 0) && (setup->bRequest == USB_SREQ_SET_ADDRESS)) {
+		/* HAL requires we set the address before submitting status */
+		HAL_PCD_SetAddress(&priv->pcd, setup->wValue);
+	}
+
+	if (udc_ctrl_stage_is_data_out(dev)) {
+		/*  Allocate and feed buffer for data OUT stage */
+		err = usbd_ctrl_feed_dout(dev, udc_data_stage_length(buf));
+		if (err == -ENOMEM) {
+			udc_submit_ep_event(dev, buf, err);
+		}
+	} else if (udc_ctrl_stage_is_data_in(dev)) {
+		udc_ctrl_submit_s_in_status(dev);
+	} else {
+		udc_ctrl_submit_s_status(dev);
+	}
+}
+
+static void udc_stm32_thread_handler(void *arg1, void *arg2, void *arg3)
+{
+	const struct device *dev = arg1;
+	struct udc_stm32_data *priv = udc_get_private(dev);
+	struct udc_stm32_msg msg;
+
+	while (true) {
+		k_msgq_get(&priv->msgq_data, &msg, K_FOREVER);
+		switch (msg.type) {
+		case UDC_STM32_MSG_SETUP:
+			handle_msg_setup(priv);
+			break;
+		case UDC_STM32_MSG_DATA_IN:
+			handle_msg_data_in(priv, msg.ep);
+			break;
+		case UDC_STM32_MSG_DATA_OUT:
+			handle_msg_data_out(priv, msg.ep, msg.rx_count);
+			break;
+		}
+	}
+}
+
 #if DT_INST_NODE_HAS_PROP(0, disconnect_gpios)
 void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
 {
@@ -464,9 +573,9 @@ static void udc_stm32_mem_init(const struct device *dev)
 	}
 
 	/* The documentation is not clear at all about RX FiFo size requirement,
-	 * Allocate a minimum of 0x40 words, which seems to work reliably.
+	 * 160 has been selected through trial and error.
 	 */
-	words = MAX(0x40, cfg->ep_mps / 4);
+	words = MAX(160, cfg->ep_mps / 4);
 	HAL_PCDEx_SetRxFiFo(&priv->pcd, words);
 	priv->occupied_mem = words * 4;
 
@@ -860,12 +969,6 @@ static const struct udc_api udc_stm32_api = {
 #define USB_BTABLE_SIZE 0
 #endif /* USB */
 
-#define USB_OTG_HS_EMB_PHY (DT_HAS_COMPAT_STATUS_OKAY(st_stm32_usbphyc) && \
-			    DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs))
-
-#define USB_OTG_HS_ULPI_PHY (DT_HAS_COMPAT_STATUS_OKAY(usb_ulpi_phy) && \
-			    DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs))
-
 static struct udc_stm32_data udc0_priv;
 
 static struct udc_data udc0_data = {
@@ -879,50 +982,9 @@ static const struct udc_stm32_config udc0_cfg  = {
 	.pma_offset = USB_BTABLE_SIZE,
 	.ep0_mps = EP0_MPS,
 	.ep_mps = EP_MPS,
+	.speed_idx = DT_ENUM_IDX_OR(DT_DRV_INST(0), maximum_speed, 1),
 };
 
-#if defined(USB_OTG_FS) || defined(USB_OTG_HS)
-static uint32_t usb_dc_stm32_get_maximum_speed(void)
-{
-/*
- * STM32L4 series USB LL API doesn't provide HIGH and HIGH_IN_FULL speed
- * defines.
- */
-#if defined(CONFIG_SOC_SERIES_STM32L4X)
-#define USB_OTG_SPEED_HIGH                     0U
-#define USB_OTG_SPEED_HIGH_IN_FULL             1U
-#endif /* CONFIG_SOC_SERIES_STM32L4X */
-/*
- * If max-speed is not passed via DT, set it to USB controller's
- * maximum hardware capability.
- */
-#if USB_OTG_HS_EMB_PHY || USB_OTG_HS_ULPI_PHY
-	uint32_t speed = USB_OTG_SPEED_HIGH;
-#else
-	uint32_t speed = USB_OTG_SPEED_FULL;
-#endif
-
-#ifdef USB_MAXIMUM_SPEED
-
-	if (!strncmp(USB_MAXIMUM_SPEED, "high-speed", 10)) {
-		speed = USB_OTG_SPEED_HIGH;
-	} else if (!strncmp(USB_MAXIMUM_SPEED, "full-speed", 10)) {
-#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(USB_OTG_HS_EMB_PHY)
-		speed = USB_OTG_SPEED_HIGH_IN_FULL;
-#else
-		speed = USB_OTG_SPEED_FULL;
-#endif
-	} else {
-		LOG_DBG("Unsupported maximum speed defined in device tree. "
-			"USB controller will default to its maximum HW "
-			"capability");
-	}
-#endif
-
-	return speed;
-}
-#endif /* USB_OTG_FS || USB_OTG_HS */
-
 static void priv_pcd_prepare(const struct device *dev)
 {
 	struct udc_stm32_data *priv = udc_get_private(dev);
@@ -933,20 +995,15 @@ static void priv_pcd_prepare(const struct device *dev)
 	/* Default values */
 	priv->pcd.Init.dev_endpoints = cfg->num_endpoints;
 	priv->pcd.Init.ep0_mps = cfg->ep0_mps;
-	priv->pcd.Init.speed = PCD_SPEED_FULL;
+	priv->pcd.Init.speed = UTIL_CAT(UDC_STM32_, DT_INST_STRING_UPPER_TOKEN(0, maximum_speed));
 
 	/* Per controller/Phy values */
 #if defined(USB)
 	priv->pcd.Instance = USB;
 #elif defined(USB_DRD_FS)
 	priv->pcd.Instance = USB_DRD_FS;
-#elif defined(USB_OTG_FS) || defined(USB_OTG_HS)
-	priv->pcd.Init.speed = usb_dc_stm32_get_maximum_speed();
-#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
-	priv->pcd.Instance = USB_OTG_HS;
-#else
-	priv->pcd.Instance = USB_OTG_FS;
-#endif
+#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs) || DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otghs)
+	priv->pcd.Instance = (USB_OTG_GlobalTypeDef *)UDC_STM32_BASE_ADDRESS;
 #endif /* USB */
 
 #if USB_OTG_HS_EMB_PHY
@@ -1001,6 +1058,15 @@ static int priv_clock_enable(void)
 	HAL_SYSCFG_SetOTGPHYReferenceClockSelection(SYSCFG_OTG_HS_PHY_CLK_SELECT_1);
 	/* Configuring the SYSCFG registers OTG_HS PHY : OTG_HS PHY enable*/
 	HAL_SYSCFG_EnableOTGPHY(SYSCFG_OTG_HS_PHY_ENABLE);
+#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_otghs)
+	/* Enable Vdd USB voltage monitoring */
+	LL_PWR_EnableVddUSBMonitoring();
+	while (__HAL_PWR_GET_FLAG(PWR_FLAG_USB33RDY)) {
+		/* Wait FOR VDD33USB ready */
+	}
+
+	/* Enable VDDUSB */
+	LL_PWR_EnableVddUSB();
 #elif defined(PWR_USBSCR_USB33SV) || defined(PWR_SVMCR_USV)
 	/*
 	 * VDDUSB independent USB supply (PWR clock is on)
@@ -1033,7 +1099,7 @@ static int priv_clock_enable(void)
 		return -EIO;
 	}
 
-	if (IS_ENABLED(CONFIG_USB_DC_STM32_CLOCK_CHECK)) {
+	if (IS_ENABLED(CONFIG_UDC_STM32_CLOCK_CHECK)) {
 		uint32_t usb_clock_rate;
 
 		if (clock_control_get_rate(clk,
@@ -1076,13 +1142,15 @@ static int priv_clock_enable(void)
 	/* Both OTG HS and USBPHY sleep clock MUST be disabled here at the same time */
 	LL_AHB2_GRP1_DisableClockStopSleep(LL_AHB2_GRP1_PERIPH_OTG_HS ||
 						LL_AHB2_GRP1_PERIPH_USBPHY);
-#else
+#elif !DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_otghs)
 	LL_AHB1_GRP1_DisableClockLowPower(LL_AHB1_GRP1_PERIPH_OTGHSULPI);
 #endif /* defined(CONFIG_SOC_SERIES_STM32H7X) */
 
 #if USB_OTG_HS_EMB_PHY
+#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_otghs)
 	LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_OTGPHYC);
 #endif
+#endif
 #elif defined(CONFIG_SOC_SERIES_STM32H7X) && DT_HAS_COMPAT_STATUS_OKAY(st_stm32_otgfs)
 	/* The USB2 controller only works in FS mode, but the ULPI clock needs
 	 * to be disabled in sleep mode for it to work.
@@ -1111,15 +1179,21 @@ static int priv_clock_disable(void)
 static struct udc_ep_config ep_cfg_in[DT_INST_PROP(0, num_bidir_endpoints)];
 static struct udc_ep_config ep_cfg_out[DT_INST_PROP(0, num_bidir_endpoints)];
 
+#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_otghs)
 PINCTRL_DT_INST_DEFINE(0);
 static const struct pinctrl_dev_config *usb_pcfg =
 					PINCTRL_DT_INST_DEV_CONFIG_GET(0);
+#endif
 
 #if USB_OTG_HS_ULPI_PHY
 static const struct gpio_dt_spec ulpi_reset =
 	GPIO_DT_SPEC_GET_OR(DT_PHANDLE(DT_INST(0, st_stm32_otghs), phys), reset_gpios, {0});
 #endif
 
+static char udc_msgq_buf_0[CONFIG_UDC_STM32_MAX_QMESSAGES * sizeof(struct udc_stm32_msg)];
+
+K_THREAD_STACK_DEFINE(udc_stm32_stack_0, CONFIG_UDC_STM32_STACK_SIZE);
+
 static int udc_stm32_driver_init0(const struct device *dev)
 {
 	struct udc_stm32_data *priv = udc_get_private(dev);
@@ -1170,6 +1244,9 @@ static int udc_stm32_driver_init0(const struct device *dev)
 	data->caps.rwup = true;
 	data->caps.out_ack = false;
 	data->caps.mps0 = UDC_MPS0_64;
+	if (cfg->speed_idx == 2) {
+		data->caps.hs = true;
+	}
 
 	priv->dev = dev;
 	priv->irq = UDC_STM32_IRQ;
@@ -1177,14 +1254,25 @@ static int udc_stm32_driver_init0(const struct device *dev)
 	priv->clk_disable = priv_clock_disable;
 	priv->pcd_prepare = priv_pcd_prepare;
 
+	k_msgq_init(&priv->msgq_data, udc_msgq_buf_0, sizeof(struct udc_stm32_msg),
+		    CONFIG_UDC_STM32_MAX_QMESSAGES);
+
+	k_thread_create(&priv->thread_data, udc_stm32_stack_0,
+			K_THREAD_STACK_SIZEOF(udc_stm32_stack_0), udc_stm32_thread_handler,
+			(void *)dev, NULL, NULL, K_PRIO_COOP(CONFIG_UDC_STM32_THREAD_PRIORITY),
+			K_ESSENTIAL, K_NO_WAIT);
+	k_thread_name_set(&priv->thread_data, dev->name);
+
 	IRQ_CONNECT(UDC_STM32_IRQ, UDC_STM32_IRQ_PRI, udc_stm32_irq,
 		    DEVICE_DT_INST_GET(0), 0);
 
+#if !DT_HAS_COMPAT_STATUS_OKAY(st_stm32n6_otghs)
 	err = pinctrl_apply_state(usb_pcfg, PINCTRL_STATE_DEFAULT);
 	if (err < 0) {
 		LOG_ERR("USB pinctrl setup failed (%d)", err);
 		return err;
 	}
+#endif
 
 #ifdef SYSCFG_CFGR1_USB_IT_RMP
 	/*
diff --git a/drivers/usb/uhc/uhc_common.c b/drivers/usb/uhc/uhc_common.c
index 15377500a66..097d4a01457 100644
--- a/drivers/usb/uhc/uhc_common.c
+++ b/drivers/usb/uhc/uhc_common.c
@@ -92,16 +92,15 @@ void uhc_xfer_buf_free(const struct device *dev, struct net_buf *const buf)
 }
 
 struct uhc_transfer *uhc_xfer_alloc(const struct device *dev,
-				    const uint8_t addr,
 				    const uint8_t ep,
-				    const uint8_t attrib,
-				    const uint16_t mps,
-				    const uint16_t timeout,
-				    void *const udev,
-				    void *const cb)
+				    struct usb_device *const udev,
+				    void *const cb,
+				    void *const cb_priv)
 {
+	uint8_t ep_idx = USB_EP_GET_IDX(ep) & 0xF;
 	const struct uhc_api *api = dev->api;
 	struct uhc_transfer *xfer = NULL;
+	uint16_t mps;
 
 	api->lock(dev);
 
@@ -109,8 +108,26 @@ struct uhc_transfer *uhc_xfer_alloc(const struct device *dev,
 		goto xfer_alloc_error;
 	}
 
-	LOG_DBG("Allocate xfer, ep 0x%02x attrib 0x%02x cb %p",
-		ep, attrib, cb);
+	if (ep_idx == 0) {
+		mps = udev->dev_desc.bMaxPacketSize0;
+	} else {
+		struct usb_ep_descriptor *ep_desc;
+
+		if (USB_EP_DIR_IS_IN(ep)) {
+			ep_desc = udev->ep_in[ep_idx].desc;
+		} else {
+			ep_desc = udev->ep_out[ep_idx].desc;
+		}
+
+		if (ep_desc == NULL) {
+			LOG_ERR("Endpoint 0x%02x is not configured", ep);
+			goto xfer_alloc_error;
+		}
+
+		mps = ep_desc->wMaxPacketSize;
+	}
+
+	LOG_DBG("Allocate xfer, ep 0x%02x mps %u cb %p", ep, mps, cb);
 
 	if (k_mem_slab_alloc(&uhc_xfer_pool, (void **)&xfer, K_NO_WAIT)) {
 		LOG_ERR("Failed to allocate transfer");
@@ -118,13 +135,11 @@ struct uhc_transfer *uhc_xfer_alloc(const struct device *dev,
 	}
 
 	memset(xfer, 0, sizeof(struct uhc_transfer));
-	xfer->addr = addr;
 	xfer->ep = ep;
-	xfer->attrib = attrib;
 	xfer->mps = mps;
-	xfer->timeout = timeout;
 	xfer->udev = udev;
 	xfer->cb = cb;
+	xfer->priv = cb_priv;
 
 xfer_alloc_error:
 	api->unlock(dev);
@@ -133,13 +148,10 @@ struct uhc_transfer *uhc_xfer_alloc(const struct device *dev,
 }
 
 struct uhc_transfer *uhc_xfer_alloc_with_buf(const struct device *dev,
-					     const uint8_t addr,
 					     const uint8_t ep,
-					     const uint8_t attrib,
-					     const uint16_t mps,
-					     const uint16_t timeout,
-					     void *const udev,
+					     struct usb_device *const udev,
 					     void *const cb,
+					     void *const cb_priv,
 					     size_t size)
 {
 	struct uhc_transfer *xfer;
@@ -150,7 +162,7 @@ struct uhc_transfer *uhc_xfer_alloc_with_buf(const struct device *dev,
 		return NULL;
 	}
 
-	xfer = uhc_xfer_alloc(dev, addr, ep, attrib, mps, timeout, udev, cb);
+	xfer = uhc_xfer_alloc(dev, ep, udev, cb, cb_priv);
 	if (xfer == NULL) {
 		net_buf_unref(buf);
 		return NULL;
@@ -298,7 +310,8 @@ int uhc_disable(const struct device *dev)
 	return ret;
 }
 
-int uhc_init(const struct device *dev, uhc_event_cb_t event_cb)
+int uhc_init(const struct device *dev,
+	     uhc_event_cb_t event_cb, const void *const event_ctx)
 {
 	const struct uhc_api *api = dev->api;
 	struct uhc_data *data = dev->data;
@@ -316,6 +329,7 @@ int uhc_init(const struct device *dev, uhc_event_cb_t event_cb)
 	}
 
 	data->event_cb = event_cb;
+	data->event_ctx = event_ctx;
 	sys_dlist_init(&data->ctrl_xfers);
 	sys_dlist_init(&data->bulk_xfers);
 
diff --git a/drivers/usb/uhc/uhc_max3421e.c b/drivers/usb/uhc/uhc_max3421e.c
index ac9aa2a526d..64a6e167cbf 100644
--- a/drivers/usb/uhc/uhc_max3421e.c
+++ b/drivers/usb/uhc/uhc_max3421e.c
@@ -377,12 +377,14 @@ static int max3421e_xfer_bulk(const struct device *dev,
 static int max3421e_schedule_xfer(const struct device *dev)
 {
 	struct max3421e_data *priv = uhc_get_private(dev);
-	const uint8_t hirq = priv->hirq;
-	const uint8_t hrsl = priv->hrsl;
+	uint8_t hrsl = priv->hrsl;
 
 	if (priv->last_xfer == NULL) {
 		int ret;
 
+		/* Do not restart last transfer */
+		hrsl = 0;
+
 		priv->last_xfer = uhc_xfer_get_next(dev);
 		if (priv->last_xfer == NULL) {
 			LOG_DBG("Nothing to transfer");
@@ -390,20 +392,12 @@ static int max3421e_schedule_xfer(const struct device *dev)
 		}
 
 		LOG_DBG("Next transfer %p", priv->last_xfer);
-		ret = max3421e_peraddr(dev, priv->last_xfer->addr);
+		ret = max3421e_peraddr(dev, priv->last_xfer->udev->addr);
 		if (ret) {
 			return ret;
 		}
 	}
 
-	if (hirq & MAX3421E_FRAME) {
-		if (priv->last_xfer->timeout) {
-			priv->last_xfer->timeout--;
-		} else {
-			LOG_INF("Transfer timeout");
-		}
-	}
-
 	/*
 	 * TODO: currently we only support control transfers and
 	 * treat all others as bulk.
@@ -425,6 +419,23 @@ static void max3421e_xfer_drop_active(const struct device *dev, int err)
 	}
 }
 
+static void max3421e_xfer_cleanup_cancelled(const struct device *dev)
+{
+	struct max3421e_data *priv = uhc_get_private(dev);
+	struct uhc_data *data = dev->data;
+	struct uhc_transfer *tmp;
+
+	if (priv->last_xfer != NULL && priv->last_xfer->err == -ECONNRESET) {
+		max3421e_xfer_drop_active(dev, -ECONNRESET);
+	}
+
+	SYS_DLIST_FOR_EACH_CONTAINER(&data->ctrl_xfers, tmp, node) {
+		if (tmp->err == -ECONNRESET) {
+			uhc_xfer_return(dev, tmp, -ECONNRESET);
+		}
+	}
+}
+
 static int max3421e_hrslt_success(const struct device *dev)
 {
 	struct max3421e_data *priv = uhc_get_private(dev);
@@ -527,17 +538,6 @@ static int max3421e_handle_hxfrdn(const struct device *dev)
 
 	switch (MAX3421E_HRSLT(hrsl)) {
 	case MAX3421E_HR_NAK:
-		/*
-		 * The transfer did not take place within
-		 * the specified number of frames.
-		 *
-		 * TODO: Transfer cancel request (xfer->cancel)
-		 * can be handled here as well.
-		 */
-		if (xfer->timeout == 0) {
-			max3421e_xfer_drop_active(dev, -ETIMEDOUT);
-		}
-
 		break;
 	case MAX3421E_HR_STALL:
 		max3421e_xfer_drop_active(dev, -EPIPE);
@@ -682,7 +682,9 @@ static void uhc_max3421e_thread(void *p1, void *p2, void *p3)
 		/* Host Transfer Done Interrupt */
 		if (priv->hirq & MAX3421E_HXFRDN) {
 			err = max3421e_handle_hxfrdn(dev);
-			schedule = true;
+			if (unlikely(err)) {
+				uhc_submit_event(dev, UHC_EVT_ERROR, err);
+			}
 		}
 
 		/* Frame Generator Interrupt */
@@ -704,6 +706,8 @@ static void uhc_max3421e_thread(void *p1, void *p2, void *p3)
 			uhc_submit_event(dev, UHC_EVT_ERROR, err);
 		}
 
+		max3421e_xfer_cleanup_cancelled(dev);
+
 		if (schedule) {
 			err = max3421e_schedule_xfer(dev);
 			if (unlikely(err)) {
@@ -797,7 +801,19 @@ static int max3421e_enqueue(const struct device *dev,
 static int max3421e_dequeue(const struct device *dev,
 			    struct uhc_transfer *const xfer)
 {
-	/* TODO */
+	struct uhc_data *data = dev->data;
+	struct uhc_transfer *tmp;
+	unsigned int key;
+
+	key = irq_lock();
+	SYS_DLIST_FOR_EACH_CONTAINER(&data->ctrl_xfers, tmp, node) {
+		if (xfer == tmp) {
+			tmp->err = -ECONNRESET;
+		}
+	}
+
+	irq_unlock(key);
+
 	return 0;
 }
 
diff --git a/drivers/usb/uhc/uhc_virtual.c b/drivers/usb/uhc/uhc_virtual.c
index 9e33f755573..c582cfe1e7a 100644
--- a/drivers/usb/uhc/uhc_virtual.c
+++ b/drivers/usb/uhc/uhc_virtual.c
@@ -24,23 +24,36 @@
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(uhc_vrt, CONFIG_UHC_DRIVER_LOG_LEVEL);
 
+#define FRAME_MAX_TRANSFERS 16
+
 struct uhc_vrt_config {
 };
 
+struct uhc_vrt_slot {
+	sys_dnode_t node;
+	struct uhc_transfer *xfer;
+};
+
+struct uhc_vrt_frame {
+	struct uhc_vrt_slot slots[FRAME_MAX_TRANSFERS];
+	sys_dnode_t *ptr;
+	sys_dlist_t list;
+	uint8_t count;
+};
+
 struct uhc_vrt_data {
 	const struct device *dev;
 	struct uvb_node *host_node;
 	struct k_work work;
 	struct k_fifo fifo;
 	struct uhc_transfer *last_xfer;
+	struct uhc_vrt_frame frame;
 	struct k_timer sof_timer;
-	bool busy;
+	uint16_t frame_number;
 	uint8_t req;
 };
 
 enum uhc_vrt_event_type {
-	/* Trigger next transfer */
-	UHC_VRT_EVT_XFER,
 	/* SoF generator event */
 	UHC_VRT_EVT_SOF,
 	/* Request reply received */
@@ -86,7 +99,7 @@ static int vrt_xfer_control(const struct device *dev,
 	if (xfer->stage == UHC_CONTROL_STAGE_SETUP) {
 		LOG_DBG("Handle SETUP stage");
 		uvb_pkt = uvb_alloc_pkt(UVB_REQUEST_SETUP,
-					xfer->addr, USB_CONTROL_EP_OUT,
+					xfer->udev->addr, USB_CONTROL_EP_OUT,
 					xfer->setup_pkt, sizeof(xfer->setup_pkt));
 		if (uvb_pkt == NULL) {
 			LOG_ERR("Failed to allocate UVB packet");
@@ -94,7 +107,6 @@ static int vrt_xfer_control(const struct device *dev,
 		}
 
 		priv->req = UVB_REQUEST_SETUP;
-		priv->busy = true;
 
 		return uvb_advert_pkt(priv->host_node, uvb_pkt);
 	}
@@ -110,7 +122,7 @@ static int vrt_xfer_control(const struct device *dev,
 
 		LOG_DBG("Handle DATA stage");
 		uvb_pkt = uvb_alloc_pkt(UVB_REQUEST_DATA,
-					xfer->addr, xfer->ep,
+					xfer->udev->addr, xfer->ep,
 					data, length);
 		if (uvb_pkt == NULL) {
 			LOG_ERR("Failed to allocate UVB packet");
@@ -118,7 +130,6 @@ static int vrt_xfer_control(const struct device *dev,
 		}
 
 		priv->req = UVB_REQUEST_DATA;
-		priv->busy = true;
 
 		return uvb_advert_pkt(priv->host_node, uvb_pkt);
 	}
@@ -134,7 +145,7 @@ static int vrt_xfer_control(const struct device *dev,
 		}
 
 		uvb_pkt = uvb_alloc_pkt(UVB_REQUEST_DATA,
-					xfer->addr, ep,
+					xfer->udev->addr, ep,
 					NULL, 0);
 		if (uvb_pkt == NULL) {
 			LOG_ERR("Failed to allocate UVB packet");
@@ -142,7 +153,6 @@ static int vrt_xfer_control(const struct device *dev,
 		}
 
 		priv->req = UVB_REQUEST_DATA;
-		priv->busy = true;
 
 		return uvb_advert_pkt(priv->host_node, uvb_pkt);
 	}
@@ -167,7 +177,7 @@ static int vrt_xfer_bulk(const struct device *dev,
 		data = buf->data;
 	}
 
-	uvb_pkt = uvb_alloc_pkt(UVB_REQUEST_DATA, xfer->addr, xfer->ep,
+	uvb_pkt = uvb_alloc_pkt(UVB_REQUEST_DATA, xfer->udev->addr, xfer->ep,
 				data, length);
 	if (uvb_pkt == NULL) {
 		LOG_ERR("Failed to allocate UVB packet");
@@ -177,25 +187,97 @@ static int vrt_xfer_bulk(const struct device *dev,
 	return uvb_advert_pkt(priv->host_node, uvb_pkt);
 }
 
-static int vrt_schedule_xfer(const struct device *dev)
+static inline uint8_t get_xfer_ep_idx(const uint8_t ep)
 {
-	struct uhc_vrt_data *priv = uhc_get_private(dev);
+	/* We do not need to differentiate the direction for the control
+	 * transfers because they are handled as a whole.
+	 */
+	if (USB_EP_DIR_IS_OUT(ep) || USB_EP_GET_IDX(ep) == 0) {
+		return USB_EP_GET_IDX(ep & BIT_MASK(4));
+	}
+
+	return USB_EP_GET_IDX(ep & BIT_MASK(4)) + 16U;
+}
+
+static void vrt_assemble_frame(const struct device *dev)
+{
+	struct uhc_vrt_data *const priv = uhc_get_private(dev);
+	struct uhc_vrt_frame *const frame = &priv->frame;
+	struct uhc_data *const data = dev->data;
+	struct uhc_transfer *tmp;
+	unsigned int n = 0;
+	unsigned int key;
+	uint32_t bm = 0;
+
+	sys_dlist_init(&frame->list);
+	frame->ptr = NULL;
+	frame->count = 0;
+	key = irq_lock();
+
+	/* TODO: add periodic transfers up to 90% */
+	SYS_DLIST_FOR_EACH_CONTAINER(&data->ctrl_xfers, tmp, node) {
+		uint8_t idx = get_xfer_ep_idx(tmp->ep);
+
+		/* There could be multiple transfers queued for the same
+		 * endpoint, for now we only allow one to be scheduled per frame.
+		 */
+		if (bm & BIT(idx)) {
+			continue;
+		}
+
+		if (tmp->interval) {
+			if (tmp->start_frame != priv->frame_number) {
+				continue;
+			}
+
+			tmp->start_frame = priv->frame_number + tmp->interval;
+			LOG_DBG("Interrupt transfer s.f. %u f.n. %u interval %u",
+				tmp->start_frame, priv->frame_number, tmp->interval);
+		}
+
+		bm |= BIT(idx);
+		frame->slots[n].xfer = tmp;
+		sys_dlist_append(&frame->list, &frame->slots[n].node);
+		n++;
+
+		if (n >= FRAME_MAX_TRANSFERS) {
+			/* No more free slots */
+			break;
+		}
+	}
+
+	irq_unlock(key);
+}
+
+static int vrt_schedule_frame(const struct device *dev)
+{
+	struct uhc_vrt_data *const priv = uhc_get_private(dev);
+	struct uhc_vrt_frame *const frame = &priv->frame;
+	struct uhc_vrt_slot *slot;
 
 	if (priv->last_xfer == NULL) {
-		priv->last_xfer = uhc_xfer_get_next(dev);
-		if (priv->last_xfer == NULL) {
-			LOG_DBG("Nothing to transfer");
+		if (frame->count >= FRAME_MAX_TRANSFERS) {
+			LOG_DBG("Frame finished");
+			return 0;
+		}
+
+		frame->ptr = sys_dlist_get(&frame->list);
+		slot = SYS_DLIST_CONTAINER(frame->ptr, slot, node);
+		if (slot == NULL) {
+			LOG_DBG("No more transfers for the frame");
 			return 0;
 		}
 
-		LOG_DBG("Next transfer is %p", priv->last_xfer);
+		priv->last_xfer = slot->xfer;
+		frame->count++;
+		LOG_DBG("Next transfer is %p (count %u)",
+			(void *)priv->last_xfer, frame->count);
 	}
 
 	if (USB_EP_GET_IDX(priv->last_xfer->ep) == 0) {
 		return vrt_xfer_control(dev, priv->last_xfer);
 	}
 
-	/* TODO: Isochronous transfers */
 	return vrt_xfer_bulk(dev, priv->last_xfer);
 }
 
@@ -276,6 +358,7 @@ static int vrt_handle_reply(const struct device *dev,
 			    struct uvb_packet *const pkt)
 {
 	struct uhc_vrt_data *priv = uhc_get_private(dev);
+	struct uhc_vrt_frame *const frame = &priv->frame;
 	struct uhc_transfer *const xfer = priv->last_xfer;
 	int ret = 0;
 
@@ -285,11 +368,12 @@ static int vrt_handle_reply(const struct device *dev,
 		goto handle_reply_err;
 	}
 
-	priv->busy = false;
-
 	switch (pkt->reply) {
 	case UVB_REPLY_NACK:
-		/* Restart last transaction */
+		/* Move the transfer back to the list. */
+		sys_dlist_append(&frame->list, frame->ptr);
+		priv->last_xfer = NULL;
+		LOG_DBG("NACK 0x%02x count %u", xfer->ep, frame->count);
 		break;
 	case UVB_REPLY_STALL:
 		vrt_xfer_drop_active(dev, -EPIPE);
@@ -308,6 +392,23 @@ static int vrt_handle_reply(const struct device *dev,
 	return ret;
 }
 
+static void vrt_xfer_cleanup_cancelled(const struct device *dev)
+{
+	struct uhc_vrt_data *priv = uhc_get_private(dev);
+	struct uhc_data *data = dev->data;
+	struct uhc_transfer *tmp;
+
+	if (priv->last_xfer != NULL && priv->last_xfer->err == -ECONNRESET) {
+		vrt_xfer_drop_active(dev, -ECONNRESET);
+	}
+
+	SYS_DLIST_FOR_EACH_CONTAINER(&data->ctrl_xfers, tmp, node) {
+		if (tmp->err == -ECONNRESET) {
+			uhc_xfer_return(dev, tmp, -ECONNRESET);
+		}
+	}
+}
+
 static void xfer_work_handler(struct k_work *work)
 {
 	struct uhc_vrt_data *priv = CONTAINER_OF(work, struct uhc_vrt_data, work);
@@ -319,6 +420,12 @@ static void xfer_work_handler(struct k_work *work)
 		int err;
 
 		switch (ev->type) {
+		case UHC_VRT_EVT_SOF:
+			priv->frame_number++;
+			vrt_xfer_cleanup_cancelled(dev);
+			vrt_assemble_frame(dev);
+			schedule = true;
+			break;
 		case UHC_VRT_EVT_REPLY:
 			err = vrt_handle_reply(dev, ev->pkt);
 			if (unlikely(err)) {
@@ -327,30 +434,16 @@ static void xfer_work_handler(struct k_work *work)
 
 			schedule = true;
 			break;
-		case UHC_VRT_EVT_XFER:
-			LOG_DBG("Transfer triggered for %p", dev);
-			schedule = true;
-			break;
-		case UHC_VRT_EVT_SOF:
-			if (priv->last_xfer != NULL) {
-				if (priv->last_xfer->timeout) {
-					priv->last_xfer->timeout--;
-				} else {
-					vrt_xfer_drop_active(dev, -ETIMEDOUT);
-					priv->busy = false;
-					LOG_WRN("Transfer timeout");
-				}
-			}
-			break;
 		default:
 			break;
 		}
 
-		if (schedule && !priv->busy) {
-			err = vrt_schedule_xfer(dev);
+		if (schedule) {
+			err = vrt_schedule_frame(dev);
 			if (unlikely(err)) {
 				uhc_submit_event(dev, UHC_EVT_ERROR, err);
 			}
+
 		}
 
 		k_mem_slab_free(&uhc_vrt_slab, (void *)ev);
@@ -367,6 +460,7 @@ static void sof_timer_handler(struct k_timer *timer)
 static void vrt_device_act(const struct device *dev,
 			   const enum uvb_device_act act)
 {
+	struct uhc_vrt_data *priv = uhc_get_private(dev);
 	enum uhc_event_type type;
 
 	switch (act) {
@@ -375,9 +469,11 @@ static void vrt_device_act(const struct device *dev,
 		break;
 	case UVB_DEVICE_ACT_FS:
 		type = UHC_EVT_DEV_CONNECTED_FS;
+		k_timer_start(&priv->sof_timer, K_MSEC(1), K_MSEC(1));
 		break;
 	case UVB_DEVICE_ACT_HS:
 		type = UHC_EVT_DEV_CONNECTED_HS;
+		k_timer_start(&priv->sof_timer, K_MSEC(1), K_USEC(125));
 		break;
 	case UVB_DEVICE_ACT_REMOVED:
 		type = UHC_EVT_DEV_REMOVED;
@@ -406,7 +502,10 @@ static void uhc_vrt_uvb_cb(const void *const vrt_priv,
 
 static int uhc_vrt_sof_enable(const struct device *dev)
 {
-	/* TODO */
+	struct uhc_vrt_data *priv = uhc_get_private(dev);
+
+	k_timer_start(&priv->sof_timer, K_MSEC(1), K_MSEC(1));
+
 	return 0;
 }
 
@@ -423,17 +522,21 @@ static int uhc_vrt_bus_suspend(const struct device *dev)
 static int uhc_vrt_bus_reset(const struct device *dev)
 {
 	struct uhc_vrt_data *priv = uhc_get_private(dev);
+	int ret;
 
 	k_timer_stop(&priv->sof_timer);
+	ret = uvb_advert(priv->host_node, UVB_EVT_RESET, NULL);
+	/* TDRSTR */
+	k_msleep(50);
+	k_timer_start(&priv->sof_timer, K_MSEC(1), K_MSEC(1));
 
-	return uvb_advert(priv->host_node, UVB_EVT_RESET, NULL);
+	return ret;
 }
 
 static int uhc_vrt_bus_resume(const struct device *dev)
 {
 	struct uhc_vrt_data *priv = uhc_get_private(dev);
 
-	k_timer_init(&priv->sof_timer, sof_timer_handler, NULL);
 	k_timer_start(&priv->sof_timer, K_MSEC(1), K_MSEC(1));
 
 	return uvb_advert(priv->host_node, UVB_EVT_RESUME, NULL);
@@ -442,8 +545,15 @@ static int uhc_vrt_bus_resume(const struct device *dev)
 static int uhc_vrt_enqueue(const struct device *dev,
 			   struct uhc_transfer *const xfer)
 {
+	struct uhc_vrt_data *priv = uhc_get_private(dev);
+
+	if (xfer->interval) {
+		xfer->start_frame = priv->frame_number + xfer->interval;
+		LOG_DBG("New interrupt transfer s.f. %u f.n. %u interval %u",
+			xfer->start_frame, priv->frame_number, xfer->interval);
+	}
+
 	uhc_xfer_append(dev, xfer);
-	vrt_event_submit(dev, UHC_VRT_EVT_XFER, NULL);
 
 	return 0;
 }
@@ -451,7 +561,20 @@ static int uhc_vrt_enqueue(const struct device *dev,
 static int uhc_vrt_dequeue(const struct device *dev,
 			    struct uhc_transfer *const xfer)
 {
-	/* TODO */
+	struct uhc_data *data = dev->data;
+	struct uhc_transfer *tmp;
+	unsigned int key;
+
+	key = irq_lock();
+
+	SYS_DLIST_FOR_EACH_CONTAINER(&data->ctrl_xfers, tmp, node) {
+		if (xfer == tmp) {
+			tmp->err = -ECONNRESET;
+		}
+	}
+
+	irq_unlock(key);
+
 	return 0;
 }
 
diff --git a/drivers/usb_c/ppc/shell.c b/drivers/usb_c/ppc/shell.c
index 53cb6529889..092f9e633b5 100644
--- a/drivers/usb_c/ppc/shell.c
+++ b/drivers/usb_c/ppc/shell.c
@@ -10,7 +10,7 @@
 /** Macro used to iterate over USB-C connector and call a function if the node has PPC property */
 #define CALL_IF_HAS_PPC(usb_node, func)                                                            \
 	COND_CODE_1(DT_NODE_HAS_PROP(usb_node, ppc),                                               \
-		    (ret |= func(DEVICE_DT_GET(DT_PHANDLE_BY_IDX(usb_node, ppc, 0)));), ())
+		    (ret |= func(DEVICE_DT_GET_BY_IDX(usb_node, ppc, 0));), ())
 
 /**
  * @brief Command that dumps registers of one or all of the PPCs
diff --git a/drivers/usb_c/tcpc/CMakeLists.txt b/drivers/usb_c/tcpc/CMakeLists.txt
index 7bf2ff781c9..d1a428fceb0 100644
--- a/drivers/usb_c/tcpc/CMakeLists.txt
+++ b/drivers/usb_c/tcpc/CMakeLists.txt
@@ -7,3 +7,4 @@ zephyr_library_sources_ifdef(CONFIG_USBC_TCPC_STM32 ucpd_stm32.c)
 zephyr_library_sources_ifdef(CONFIG_USBC_TCPC_NUMAKER ucpd_numaker.c)
 zephyr_library_sources_ifdef(CONFIG_USBC_TCPC_TCPCI tcpci.c)
 zephyr_library_sources_ifdef(CONFIG_USBC_TCPC_PS8XXX ps8xxx.c)
+zephyr_library_sources_ifdef(CONFIG_USBC_TCPC_RT1715 rt1715.c)
diff --git a/drivers/usb_c/tcpc/Kconfig b/drivers/usb_c/tcpc/Kconfig
index b4fdd64f090..3b1a9ccc284 100644
--- a/drivers/usb_c/tcpc/Kconfig
+++ b/drivers/usb_c/tcpc/Kconfig
@@ -29,6 +29,7 @@ source "drivers/usb_c/tcpc/Kconfig.tcpc_stm32"
 source "drivers/usb_c/tcpc/Kconfig.tcpc_numaker"
 source "drivers/usb_c/tcpc/Kconfig.tcpc_tcpci"
 source "drivers/usb_c/tcpc/Kconfig.tcpc_ps8xxx"
+source "drivers/usb_c/tcpc/Kconfig.tcpc_rt1715"
 
 module = USBC
 module-str = usbc
diff --git a/drivers/usb_c/tcpc/Kconfig.tcpc_rt1715 b/drivers/usb_c/tcpc/Kconfig.tcpc_rt1715
new file mode 100644
index 00000000000..d61dfb3bad4
--- /dev/null
+++ b/drivers/usb_c/tcpc/Kconfig.tcpc_rt1715
@@ -0,0 +1,28 @@
+# USB-C RT1715 TCPC configuration options
+
+# Copyright (c) 2024 Jianxiong Gu <jianxiong.gu@outlook.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config USBC_TCPC_RT1715
+	bool "USB-C TCPC device controller driver"
+	select USBC_TCPC_TCPCI
+	default y
+	depends on DT_HAS_RICHTEK_RT1715_ENABLED
+	help
+	  Enable USB-C TCPC support for the Richtek RT1715
+
+if USBC_TCPC_RT1715
+
+config USBC_TCPC_RT1715_INIT_DELAY
+	int "RT1715 init delay"
+	default 5
+	help
+	  Delay between each try of the TCPC initialization
+
+config USBC_TCPC_RT1715_INIT_RETRIES
+	int "RT1715 init retries"
+	default 10
+	help
+	  Number of initialization tries that will be performed
+
+endif
diff --git a/drivers/usb_c/tcpc/ps8xxx.c b/drivers/usb_c/tcpc/ps8xxx.c
index 386c63cdbc4..cdc57228d23 100644
--- a/drivers/usb_c/tcpc/ps8xxx.c
+++ b/drivers/usb_c/tcpc/ps8xxx.c
@@ -67,18 +67,12 @@ struct ps8xxx_cfg {
 static int tcpci_init_alert_mask(const struct device *dev)
 {
 	const struct ps8xxx_cfg *cfg = dev->config;
-	int ret;
 
 	uint16_t mask = TCPC_REG_ALERT_TX_COMPLETE | TCPC_REG_ALERT_RX_STATUS |
 			TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS |
 			TCPC_REG_ALERT_FAULT | TCPC_REG_ALERT_POWER_STATUS;
 
-	ret = tcpci_write_reg16(&cfg->bus, TCPC_REG_ALERT_MASK, mask);
-	if (ret != 0) {
-		return ret;
-	}
-
-	return 0;
+	return tcpci_tcpm_mask_status_register(&cfg->bus, TCPC_ALERT_STATUS, mask);
 }
 
 static int ps8xxx_tcpc_init(const struct device *dev)
@@ -136,20 +130,14 @@ int ps8xxx_tcpc_select_rp_value(const struct device *dev, enum tc_rp_value rp)
 
 	data->cc_changed = true;
 
-	return tcpci_update_reg8(&cfg->bus, TCPC_REG_ROLE_CTRL, TCPC_REG_ROLE_CTRL_RP_MASK,
-				 TCPC_REG_ROLE_CTRL_SET(0, rp, 0, 0));
+	return tcpci_tcpm_select_rp_value(&cfg->bus, rp);
 }
 
 int ps8xxx_tcpc_get_rp_value(const struct device *dev, enum tc_rp_value *rp)
 {
 	const struct ps8xxx_cfg *cfg = dev->config;
-	uint8_t reg_value = 0;
-	int ret;
 
-	ret = tcpci_read_reg8(&cfg->bus, TCPC_REG_ROLE_CTRL, &reg_value);
-	*rp = TCPC_REG_ROLE_CTRL_RP(reg_value);
-
-	return ret;
+	return tcpci_tcpm_get_rp_value(&cfg->bus, rp);
 }
 
 int ps8xxx_tcpc_set_cc(const struct device *dev, enum tc_cc_pull pull)
@@ -163,9 +151,7 @@ int ps8xxx_tcpc_set_cc(const struct device *dev, enum tc_cc_pull pull)
 
 	data->cc_changed = true;
 
-	return tcpci_update_reg8(&cfg->bus, TCPC_REG_ROLE_CTRL,
-				 TCPC_REG_ROLE_CTRL_CC1_MASK | TCPC_REG_ROLE_CTRL_CC2_MASK,
-				 TCPC_REG_ROLE_CTRL_SET(0, 0, pull, pull));
+	return tcpci_tcpm_set_cc(&cfg->bus, pull);
 }
 
 void ps8xxx_tcpc_set_vconn_discharge_cb(const struct device *dev, tcpc_vconn_discharge_cb_t cb)
@@ -202,8 +188,7 @@ int ps8xxx_tcpc_set_vconn(const struct device *dev, bool enable)
 	}
 
 	data->cc_changed = true;
-	ret = tcpci_update_reg8(&cfg->bus, TCPC_REG_POWER_CTRL, TCPC_REG_POWER_CTRL_VCONN_EN,
-				enable ? TCPC_REG_POWER_CTRL_VCONN_EN : 0);
+	ret = tcpci_tcpm_set_vconn(&cfg->bus, enable);
 
 	if (ret != 0) {
 		return ret;
@@ -221,8 +206,7 @@ int ps8xxx_tcpc_set_roles(const struct device *dev, enum tc_power_role power_rol
 {
 	const struct ps8xxx_cfg *cfg = dev->config;
 
-	return tcpci_update_reg8(&cfg->bus, TCPC_REG_MSG_HDR_INFO, TCPC_REG_MSG_HDR_INFO_ROLES_MASK,
-				 TCPC_REG_MSG_HDR_INFO_SET(PD_REV30, data_role, power_role));
+	return tcpci_tcpm_set_roles(&cfg->bus, PD_REV30, power_role, data_role);
 }
 
 int ps8xxx_tcpc_get_rx_pending_msg(const struct device *dev, struct pd_msg *msg)
@@ -302,7 +286,7 @@ int ps8xxx_tcpc_set_rx_enable(const struct device *dev, bool enable)
 	const struct ps8xxx_cfg *cfg = dev->config;
 	int detect_sop_en = enable ? TCPC_REG_RX_DETECT_SOP_HRST_MASK : 0;
 
-	return tcpci_write_reg8(&cfg->bus, TCPC_REG_RX_DETECT, detect_sop_en);
+	return tcpci_tcpm_set_rx_type(&cfg->bus, detect_sop_en);
 }
 
 int ps8xxx_tcpc_set_cc_polarity(const struct device *dev, enum tc_cc_polarity polarity)
@@ -315,9 +299,7 @@ int ps8xxx_tcpc_set_cc_polarity(const struct device *dev, enum tc_cc_polarity po
 		return -EIO;
 	}
 
-	ret = tcpci_update_reg8(
-		&cfg->bus, TCPC_REG_TCPC_CTRL, TCPC_REG_TCPC_CTRL_PLUG_ORIENTATION,
-		(polarity == TC_POLARITY_CC1) ? 0 : TCPC_REG_TCPC_CTRL_PLUG_ORIENTATION);
+	ret = tcpci_tcpm_set_cc_polarity(&cfg->bus, polarity);
 
 	if (ret != 0) {
 		return ret;
@@ -332,90 +314,16 @@ int ps8xxx_tcpc_transmit_data(const struct device *dev, struct pd_msg *msg)
 {
 	const struct ps8xxx_cfg *cfg = dev->config;
 
-	int reg = TCPC_REG_TX_BUFFER;
-	int rv;
-	int cnt = 4 * msg->header.number_of_data_objects;
-
-	/* If not SOP* transmission, just write to the transmit register */
-	if (msg->header.message_type >= NUM_SOP_STAR_TYPES) {
-		/*
-		 * Per TCPCI spec, do not specify retry (although the TCPC
-		 * should ignore retry field for these 3 types).
-		 */
-		return tcpci_write_reg8(
-			&cfg->bus, TCPC_REG_TRANSMIT,
-			TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(msg->header.message_type));
-	}
-
-	if (cnt > 0) {
-		reg = TCPC_REG_TX_BUFFER;
-		/* TX_BYTE_CNT includes extra bytes for message header */
-		cnt += sizeof(msg->header.raw_value);
-
-		struct i2c_msg buf[3];
-
-		uint8_t tmp[2] = {TCPC_REG_TX_BUFFER, cnt};
-
-		buf[0].buf = tmp;
-		buf[0].len = 2;
-		buf[0].flags = I2C_MSG_WRITE;
-
-		buf[1].buf = (uint8_t *)&msg->header.raw_value;
-		buf[1].len = sizeof(msg->header.raw_value);
-		buf[1].flags = I2C_MSG_WRITE;
-
-		buf[2].buf = (uint8_t *)msg->data;
-		buf[2].len = msg->len;
-		buf[2].flags = I2C_MSG_WRITE | I2C_MSG_STOP;
-
-		if (cnt > sizeof(msg->header.raw_value)) {
-			rv = i2c_transfer(cfg->bus.bus, buf, 3, cfg->bus.addr);
-		} else {
-			buf[1].flags |= I2C_MSG_STOP;
-			rv = i2c_transfer(cfg->bus.bus, buf, 2, cfg->bus.addr);
-		}
-
-		/* If tcpc write fails, return error */
-		if (rv) {
-			return rv;
-		}
-	}
-
-	/*
-	 * We always retry in TCPC hardware since the TCPM is too slow to
-	 * respond within tRetry (~195 usec).
-	 *
-	 * The retry count used is dependent on the maximum PD revision
-	 * supported at build time.
-	 */
-	rv = tcpci_write_reg8(&cfg->bus, TCPC_REG_TRANSMIT,
-			      TCPC_REG_TRANSMIT_SET_WITH_RETRY(cfg->transmit_retries, msg->type));
-
-	return rv;
+	return tcpci_tcpm_transmit_data(&cfg->bus, msg, cfg->transmit_retries);
 }
 
 int ps8xxx_tcpc_dump_std_reg(const struct device *dev)
 {
 	const struct ps8xxx_cfg *cfg = dev->config;
-	uint16_t value;
 
 	LOG_INF("TCPC %s:%s registers:", cfg->bus.bus->name, dev->name);
-	for (unsigned int a = 0; a < TCPCI_STD_REGS_SIZE; a++) {
-		switch (tcpci_std_regs[a].size) {
-		case 1:
-			tcpci_read_reg8(&cfg->bus, tcpci_std_regs[a].addr, (uint8_t *)&value);
-			LOG_INF("- %-30s(0x%02x) =   0x%02x", tcpci_std_regs[a].name,
-				tcpci_std_regs[a].addr, (uint8_t)value);
-			break;
-		case 2:
-			tcpci_read_reg16(&cfg->bus, tcpci_std_regs[a].addr, &value);
-			LOG_INF("- %-30s(0x%02x) = 0x%04x", tcpci_std_regs[a].name,
-				tcpci_std_regs[a].addr, value);
-			break;
-		}
-	}
 
-	return 0;
+	return tcpci_tcpm_dump_std_reg(&cfg->bus);
 }
 
 void ps8xxx_tcpc_alert_handler_cb(const struct device *dev, void *data, enum tcpc_alert alert)
@@ -490,9 +398,7 @@ int ps8xxx_tcpc_get_chip_info(const struct device *dev, struct tcpc_chip_info *c
 		return -EIO;
 	}
 
-	ret |= tcpci_read_reg16(&cfg->bus, TCPC_REG_VENDOR_ID, &chip_info->vendor_id);
-	ret |= tcpci_read_reg16(&cfg->bus, TCPC_REG_PRODUCT_ID, &chip_info->product_id);
-	ret |= tcpci_read_reg16(&cfg->bus, TCPC_REG_BCD_DEV, &chip_info->device_id);
+	ret = tcpci_tcpm_get_chip_info(&cfg->bus, chip_info);
 
 	/* Vendor specific register for PS8815 model only */
 	if (chip_info->product_id == PS8815_PRODUCT_ID) {
@@ -596,7 +502,7 @@ void ps8xxx_alert_work_cb(struct k_work *work)
 		return;
 	}
 
-	tcpci_read_reg16(&cfg->bus, TCPC_REG_ALERT, &alert_reg);
+	tcpci_tcpm_get_status_register(&cfg->bus, TCPC_ALERT_STATUS, &alert_reg);
 
 	while (alert_reg != 0) {
 		enum tcpc_alert alert_type = tcpci_alert_reg_to_enum(alert_reg);
@@ -608,30 +514,36 @@ void ps8xxx_alert_work_cb(struct k_work *work)
 		} else if (alert_type == TCPC_ALERT_FAULT_STATUS) {
 			uint8_t fault;
 
-			tcpci_read_reg8(&cfg->bus, TCPC_REG_FAULT_STATUS, &fault);
-			tcpci_write_reg8(&cfg->bus, TCPC_REG_FAULT_STATUS, fault);
+			tcpci_tcpm_get_status_register(&cfg->bus, TCPC_FAULT_STATUS,
+						       (uint16_t *)&fault);
+			tcpci_tcpm_clear_status_register(&cfg->bus, TCPC_FAULT_STATUS,
+							 (uint16_t)fault);
 
 			LOG_DBG("PS8xxx fault: %02x", fault);
 		} else if (alert_type == TCPC_ALERT_EXTENDED_STATUS) {
 			uint8_t ext_status;
 
-			tcpci_read_reg8(&cfg->bus, TCPC_REG_EXT_STATUS, &ext_status);
-			tcpci_write_reg8(&cfg->bus, TCPC_REG_EXT_STATUS, ext_status);
+			tcpci_tcpm_get_status_register(&cfg->bus, TCPC_EXTENDED_STATUS,
+						       (uint16_t *)&ext_status);
+			tcpci_tcpm_clear_status_register(&cfg->bus, TCPC_EXTENDED_STATUS,
+							 (uint16_t)ext_status);
 
 			data->cc_changed = true;
 			LOG_DBG("PS8xxx ext status: %02x", ext_status);
 		} else if (alert_type == TCPC_ALERT_POWER_STATUS) {
 			uint8_t pwr_status;
 
-			tcpci_read_reg8(&cfg->bus, TCPC_REG_POWER_STATUS, &pwr_status);
-			tcpci_write_reg8(&cfg->bus, TCPC_REG_POWER_STATUS, pwr_status);
+			tcpci_tcpm_get_status_register(&cfg->bus, TCPC_POWER_STATUS,
+						       (uint16_t *)&pwr_status);
 
 			LOG_DBG("PS8xxx power status: %02x", pwr_status);
 		} else if (alert_type == TCPC_ALERT_EXTENDED) {
 			uint8_t alert_status;
 
-			tcpci_read_reg8(&cfg->bus, TCPC_REG_ALERT_EXT, &alert_status);
-			tcpci_write_reg8(&cfg->bus, TCPC_REG_ALERT_EXT, alert_status);
+			tcpci_tcpm_get_status_register(&cfg->bus, TCPC_EXTENDED_ALERT_STATUS,
+						       (uint16_t *)&alert_status);
+			tcpci_tcpm_clear_status_register(&cfg->bus, TCPC_EXTENDED_ALERT_STATUS,
+							 (uint16_t)alert_status);
 
 			LOG_DBG("PS8xxx ext alert: %02x", alert_status);
 		} else if (alert_type == TCPC_ALERT_MSG_STATUS) {
@@ -641,16 +553,16 @@ void ps8xxx_alert_work_cb(struct k_work *work)
 		}
 
 		if (data->alert_handler != NULL) {
-			data->alert_handler(data->dev, data->alert_handler_data, alert_type);
+			data->alert_handler(dev, data->alert_handler_data, alert_type);
 		}
 
 		clear_flags |= BIT(alert_type);
 		alert_reg &= ~BIT(alert_type);
 	}
 
-	tcpci_write_reg16(&cfg->bus, TCPC_REG_ALERT, clear_flags);
+	tcpci_tcpm_clear_status_register(&cfg->bus, TCPC_ALERT_STATUS, clear_flags);
+	tcpci_tcpm_get_status_register(&cfg->bus, TCPC_ALERT_STATUS, &alert_reg);
 
-	tcpci_read_reg16(&cfg->bus, TCPC_REG_ALERT, &alert_reg);
 	if (alert_reg != 0) {
 		k_work_submit(work);
 	}
@@ -663,14 +575,12 @@ void ps8xxx_init_work_cb(struct k_work *work)
 
 	const struct ps8xxx_cfg *cfg = data->dev->config;
 	uint8_t power_reg = 0;
-	uint16_t idVendor = 0;
-	uint16_t idProduct = 0;
-	uint16_t idDevice = 0;
-	int res;
+	struct tcpc_chip_info chip_info;
+	int ret;
 
 	LOG_INF("Initializing PS8xxx chip: %s", data->dev->name);
-	res = tcpci_read_reg8(&cfg->bus, TCPC_REG_POWER_STATUS, &power_reg);
-	if (res != 0 || (power_reg & TCPC_REG_POWER_STATUS_UNINIT)) {
+	ret = tcpci_tcpm_get_status_register(&cfg->bus, TCPC_POWER_STATUS, (uint16_t *)&power_reg);
+	if (ret != 0 || (power_reg & TCPC_REG_POWER_STATUS_UNINIT)) {
 		data->init_retries++;
 
 		if (data->init_retries > CONFIG_USBC_TCPC_PS8XXX_INIT_RETRIES) {
@@ -679,16 +589,14 @@ void ps8xxx_init_work_cb(struct k_work *work)
 		}
 
 		LOG_DBG("Postpone chip initialization %d", data->init_retries);
-		k_work_schedule_for_queue(&k_sys_work_q, &data->init_dwork,
-					  K_MSEC(CONFIG_USBC_TCPC_PS8XXX_INIT_DELAY));
+		k_work_schedule(&data->init_dwork, K_MSEC(CONFIG_USBC_TCPC_PS8XXX_INIT_DELAY));
 
 		return;
 	}
 
-	tcpci_read_reg16(&cfg->bus, TCPC_REG_VENDOR_ID, &idVendor);
-	tcpci_read_reg16(&cfg->bus, TCPC_REG_PRODUCT_ID, &idProduct);
-	tcpci_read_reg16(&cfg->bus, TCPC_REG_BCD_DEV, &idDevice);
-	LOG_INF("Initialized chip is: %04x:%04x:%04x", idVendor, idProduct, idDevice);
+	ps8xxx_tcpc_get_chip_info(data->dev, &chip_info);
+	LOG_INF("Initialized chip is: %04x:%04x:%04x", chip_info.vendor_id, chip_info.product_id,
+		chip_info.device_id);
 
 	/* Initialize alert interrupt */
 	gpio_pin_configure_dt(&cfg->alert_gpio, GPIO_INPUT);
@@ -718,8 +626,7 @@ static int ps8xxx_dev_init(const struct device *dev)
 	}
 
 	k_work_init_delayable(&data->init_dwork, ps8xxx_init_work_cb);
-	k_work_schedule_for_queue(&k_sys_work_q, &data->init_dwork,
-				  K_MSEC(CONFIG_USBC_TCPC_PS8XXX_INIT_DELAY));
+	k_work_schedule(&data->init_dwork, K_MSEC(CONFIG_USBC_TCPC_PS8XXX_INIT_DELAY));
 
 	k_work_init(&data->alert_work, ps8xxx_alert_work_cb);
 
diff --git a/drivers/usb_c/tcpc/rt1715.c b/drivers/usb_c/tcpc/rt1715.c
new file mode 100644
index 00000000000..a1941ebd4b2
--- /dev/null
+++ b/drivers/usb_c/tcpc/rt1715.c
@@ -0,0 +1,699 @@
+/*
+ * Copyright (c) 2024 Jianxiong Gu <jianxiong.gu@outlook.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/i2c.h>
+#include <zephyr/drivers/usb_c/tcpci_priv.h>
+#include <zephyr/usb_c/usbc.h>
+#include <zephyr/usb_c/tcpci.h>
+#include <zephyr/shell/shell.h>
+#include "rt1715.h"
+
+#define DT_DRV_COMPAT richtek_rt1715
+LOG_MODULE_REGISTER(rt1715, CONFIG_USBC_LOG_LEVEL);
+
+/** Data structure for device instances */
+struct rt1715_data {
+	/** Device structure used to retrieve it in k_work functions */
+	const struct device *const dev;
+	/** Delayable work item for chip initialization */
+	struct k_work_delayable init_dwork;
+	/** Initialization retries counter */
+	int init_retries;
+	/** Boolean value if chip was successfully initialized */
+	bool initialized;
+
+	/** Callback for alert GPIO */
+	struct gpio_callback alert_cb;
+	/** Work item for alert handling out of interrupt context */
+	struct k_work alert_work;
+
+	/** Boolean value if there is a message pending */
+	bool msg_pending;
+	/** One-slot Rx FIFO */
+	struct pd_msg rx_msg;
+
+	/** Alert handler set by USB-C stack */
+	tcpc_alert_handler_cb_t alert_handler;
+	/** Alert handler data set by USB-C stack */
+	void *alert_handler_data;
+
+	/** VCONN discharge callback set by USB-C stack */
+	tcpc_vconn_discharge_cb_t vconn_discharge_cb;
+	/** VCONN discharge callback data set by USB-C stack */
+	tcpc_vconn_control_cb_t vconn_cb;
+	/** Polarity of CC lines for PD and VCONN */
+	enum tc_cc_polarity cc_polarity;
+
+	/** Boolean value if there was a change on the CC lines since last check */
+	bool cc_changed;
+	/** State of CC1 line */
+	enum tc_cc_voltage_state cc1;
+	/** State of CC2 line */
+	enum tc_cc_voltage_state cc2;
+
+	/* Flag to receive or ignore SOP Prime messages */
+	bool rx_sop_prime_enable;
+};
+
+/** Configuration structure for device instances */
+struct rt1715_cfg {
+	/** I2C bus and address used for communication */
+	const struct i2c_dt_spec bus;
+	/** GPIO specification for alert pin */
+	const struct gpio_dt_spec alert_gpio;
+	/** GPIO specification for VCONN power control pin */
+	const struct gpio_dt_spec vconn_ctrl_gpio;
+	/** GPIO specification for VCONN discharge control pin */
+	const struct gpio_dt_spec vconn_disc_gpio;
+	/** Maximum number of packet retransmissions done by TCPC */
+	const uint8_t transmit_retries;
+};
+
+static int tcpci_init_alert_mask(const struct device *dev)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+
+	uint16_t mask = TCPC_REG_ALERT_TX_COMPLETE | TCPC_REG_ALERT_RX_STATUS |
+			TCPC_REG_ALERT_RX_HARD_RST | TCPC_REG_ALERT_CC_STATUS |
+			TCPC_REG_ALERT_POWER_STATUS | TCPC_REG_ALERT_FAULT |
+			TCPC_REG_ALERT_RX_BUF_OVF;
+
+	return tcpci_tcpm_mask_status_register(&cfg->bus, TCPC_ALERT_STATUS, mask);
+}
+
+static int rt1715_tcpc_init(const struct device *dev)
+{
+	struct rt1715_data *data = dev->data;
+
+	if (!data->initialized) {
+		if (data->init_retries > CONFIG_USBC_TCPC_RT1715_INIT_RETRIES) {
+			LOG_ERR("TCPC was not initialized correctly");
+			return -EIO;
+		}
+
+		return -EAGAIN;
+	}
+
+	data->rx_sop_prime_enable = false;
+	data->msg_pending = false;
+	memset(&data->rx_msg, 0x00, sizeof(data->rx_msg));
+
+	LOG_INF("RT1715 TCPC initialized");
+	return 0;
+}
+
+static int rt1715_tcpc_get_cc(const struct device *dev, enum tc_cc_voltage_state *cc1,
+			      enum tc_cc_voltage_state *cc2)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+	struct rt1715_data *data = dev->data;
+	int ret;
+
+	if (!data->initialized) {
+		return -EIO;
+	}
+
+	if (IS_ENABLED(CONFIG_USBC_CSM_SINK_ONLY) && !data->cc_changed) {
+		*cc1 = data->cc1;
+		*cc2 = data->cc2;
+
+		return 0;
+	}
+
+	data->cc_changed = false;
+
+	ret = tcpci_tcpm_get_cc(&cfg->bus, cc1, cc2);
+
+	if (IS_ENABLED(CONFIG_USBC_CSM_SINK_ONLY) || *cc1 != data->cc1 || *cc2 != data->cc2) {
+		LOG_DBG("CC changed values: %d->%d, %d->%d", data->cc1, *cc1, data->cc2, *cc2);
+		data->cc1 = *cc1;
+		data->cc2 = *cc2;
+	}
+
+	return ret;
+}
+
+static int rt1715_tcpc_select_rp_value(const struct device *dev, enum tc_rp_value rp)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+	struct rt1715_data *data = dev->data;
+
+	data->cc_changed = true;
+
+	return tcpci_tcpm_select_rp_value(&cfg->bus, rp);
+}
+
+static int rt1715_tcpc_get_rp_value(const struct device *dev, enum tc_rp_value *rp)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+
+	return tcpci_tcpm_get_rp_value(&cfg->bus, rp);
+}
+
+static int rt1715_tcpc_set_cc(const struct device *dev, enum tc_cc_pull pull)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+	struct rt1715_data *data = dev->data;
+
+	if (!data->initialized) {
+		return -EIO;
+	}
+
+	data->cc_changed = true;
+
+	return tcpci_tcpm_set_cc(&cfg->bus, pull);
+}
+
+static void rt1715_tcpc_set_vconn_discharge_cb(const struct device *dev,
+					       tcpc_vconn_discharge_cb_t cb)
+{
+	struct rt1715_data *data = dev->data;
+
+	data->vconn_discharge_cb = cb;
+}
+
+static void rt1715_tcpc_set_vconn_cb(const struct device *dev, tcpc_vconn_control_cb_t vconn_cb)
+{
+	struct rt1715_data *data = dev->data;
+
+	data->vconn_cb = vconn_cb;
+}
+
+static int rt1715_tcpc_vconn_discharge(const struct device *dev, bool enable)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+
+	if (cfg->vconn_disc_gpio.port == NULL) {
+		/* RT1715 does not have built-in VCONN discharge path */
+		LOG_ERR("VCONN discharge GPIO is not defined");
+		return -EIO;
+	}
+
+	return gpio_pin_set_dt(&cfg->vconn_disc_gpio, enable);
+}
+
+static int rt1715_tcpc_set_vconn(const struct device *dev, bool enable)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+	struct rt1715_data *data = dev->data;
+	int ret;
+
+	if (!data->initialized) {
+		return -EIO;
+	}
+
+	if (enable == true && cfg->vconn_ctrl_gpio.port != NULL) {
+		/* Enable external VCONN power supply */
+		gpio_pin_set_dt(&cfg->vconn_ctrl_gpio, true);
+	}
+
+	data->cc_changed = true;
+	ret = tcpci_tcpm_set_vconn(&cfg->bus, enable);
+
+	if (ret != 0) {
+		return ret;
+	}
+
+	if (enable == false && cfg->vconn_ctrl_gpio.port != NULL) {
+		/* Disable external VCONN power supply */
+		gpio_pin_set_dt(&cfg->vconn_ctrl_gpio, false);
+	}
+
+	if (data->vconn_cb != NULL) {
+		ret = data->vconn_cb(dev, data->cc_polarity, enable);
+	}
+
+	return ret;
+}
+
+static int rt1715_tcpc_set_roles(const struct device *dev, enum tc_power_role power_role,
+				 enum tc_data_role data_role)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+
+	return tcpci_tcpm_set_roles(&cfg->bus, PD_REV30, power_role, data_role);
+}
+
+static int rt1715_tcpc_get_rx_pending_msg(const struct device *dev, struct pd_msg *msg)
+{
+	struct rt1715_data *data = dev->data;
+
+	/* Rx message pending? */
+	if (!data->msg_pending) {
+		return -ENODATA;
+	}
+
+	/* Query status only? */
+	if (msg == NULL) {
+		return 0;
+	}
+
+	/* Dequeue Rx FIFO */
+	*msg = data->rx_msg;
+	data->msg_pending = false;
+
+	/* Indicate Rx message returned */
+	return 1;
+}
+
+static int rt1715_tcpc_rx_fifo_enqueue(const struct device *dev)
+{
+	const struct rt1715_cfg *const cfg = dev->config;
+	struct rt1715_data *data = dev->data;
+	uint8_t buf[4];
+	uint8_t rxbcnt;
+	uint8_t rxftype;
+	uint16_t rxhead;
+	uint8_t rx_data_size;
+	struct pd_msg *msg = &data->rx_msg;
+	int ret = 0;
+
+	ret = i2c_burst_read_dt(&cfg->bus, TCPC_REG_RX_BUFFER, buf, sizeof(buf));
+	if (ret != 0) {
+		return ret;
+	}
+
+	rxbcnt = buf[0];
+	rxftype = buf[1];
+	rxhead = (buf[3] << 8) | buf[2];
+
+	/* rxbcnt = 1 (frame type) + 2 (Message Header) + Rx data byte count */
+	if (rxbcnt < 3) {
+		LOG_ERR("Invalid RXBCNT: %d", rxbcnt);
+		return -EIO;
+	}
+	rx_data_size = rxbcnt - 3;
+
+	/* Not support Unchunked Extended Message exceeding PD_CONVERT_PD_HEADER_COUNT_TO_BYTES */
+	if (rx_data_size > (PD_MAX_EXTENDED_MSG_LEGACY_LEN + 2)) {
+		LOG_ERR("Not support Unchunked Extended Message exceeding "
+			"PD_CONVERT_PD_HEADER_COUNT_TO_BYTES: %d",
+			rx_data_size);
+		return -EIO;
+	}
+
+	/* Rx frame type */
+	msg->type = rxftype;
+
+	/* Rx header */
+	msg->header.raw_value = (uint16_t)rxhead;
+
+	/* Rx data size */
+	msg->len = rx_data_size;
+
+	/* Rx data */
+	if (rx_data_size > 0) {
+		ret = i2c_burst_read_dt(&cfg->bus, TCPC_REG_RX_BUFFER + 4, msg->data, rx_data_size);
+		if (ret) {
+			LOG_ERR("Failed to read Rx data: %d", ret);
+		}
+	}
+
+	return ret;
+}
+
+static int rt1715_tcpc_set_rx_enable(const struct device *dev, bool enable)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+	struct rt1715_data *data = dev->data;
+
+	if (!enable) {
+		return tcpci_tcpm_set_rx_type(&cfg->bus, 0);
+	}
+
+	if (data->rx_sop_prime_enable) {
+		return tcpci_tcpm_set_rx_type(&cfg->bus,
+					      TCPC_REG_RX_DETECT_SOP_SOPP_SOPPP_HRST_MASK);
+	} else {
+		return tcpci_tcpm_set_rx_type(&cfg->bus, TCPC_REG_RX_DETECT_SOP_HRST_MASK);
+	}
+}
+
+static int rt1715_tcpc_set_cc_polarity(const struct device *dev, enum tc_cc_polarity polarity)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+	struct rt1715_data *data = dev->data;
+	int ret;
+
+	if (!data->initialized) {
+		return -EIO;
+	}
+
+	ret = tcpci_tcpm_set_cc_polarity(&cfg->bus, polarity);
+
+	if (ret != 0) {
+		return ret;
+	}
+
+	data->cc_changed = true;
+	data->cc_polarity = polarity;
+	return 0;
+}
+
+static int rt1715_tcpc_transmit_data(const struct device *dev, struct pd_msg *msg)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+
+	return tcpci_tcpm_transmit_data(&cfg->bus, msg, cfg->transmit_retries);
+}
+
+static int rt1715_tcpc_dump_std_reg(const struct device *dev)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+
+	LOG_INF("TCPC %s:%s registers:", cfg->bus.bus->name, dev->name);
+
+	return tcpci_tcpm_dump_std_reg(&cfg->bus);
+}
+
+void rt1715_tcpc_alert_handler_cb(const struct device *dev, void *data, enum tcpc_alert alert)
+{
+}
+
+static int rt1715_tcpc_get_status_register(const struct device *dev, enum tcpc_status_reg reg,
+					   uint32_t *status)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+
+	if (reg == TCPC_VENDOR_DEFINED_STATUS) {
+		return tcpci_read_reg8(&cfg->bus, RT1715_REG_RT_INT, (uint8_t *)status);
+	}
+
+	return tcpci_tcpm_get_status_register(&cfg->bus, reg, (uint16_t *)status);
+}
+
+static int rt1715_tcpc_clear_status_register(const struct device *dev, enum tcpc_status_reg reg,
+					     uint32_t mask)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+
+	if (reg == TCPC_VENDOR_DEFINED_STATUS) {
+		return tcpci_write_reg8(&cfg->bus, RT1715_REG_RT_INT, (uint8_t)mask);
+	}
+
+	return tcpci_tcpm_clear_status_register(&cfg->bus, reg, (uint16_t)mask);
+}
+
+static int rt1715_tcpc_mask_status_register(const struct device *dev, enum tcpc_status_reg reg,
+					    uint32_t mask)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+
+	if (reg == TCPC_VENDOR_DEFINED_STATUS) {
+		return tcpci_write_reg8(&cfg->bus, RT1715_REG_RT_INT_MASK, (uint8_t)mask);
+	}
+
+	return tcpci_tcpm_mask_status_register(&cfg->bus, reg, (uint16_t)mask);
+}
+
+static int rt1715_tcpc_set_drp_toggle(const struct device *dev, bool enable)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+
+	return tcpci_tcpm_set_drp_toggle(&cfg->bus, enable);
+}
+
+static int rt1715_tcpc_get_chip_info(const struct device *dev, struct tcpc_chip_info *chip_info)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+
+	if (chip_info == NULL) {
+		return -EIO;
+	}
+
+	chip_info->fw_version_number = 0;
+	chip_info->min_req_fw_version_number = 0;
+
+	return tcpci_tcpm_get_chip_info(&cfg->bus, chip_info);
+}
+
+static int rt1715_tcpc_set_low_power_mode(const struct device *dev, bool enable)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+	int ret;
+
+	ret = tcpci_write_reg8(&cfg->bus, RT1715_REG_SYS_WAKEUP, RT1715_REG_SYS_WAKEUP_EN);
+	if (ret < 0) {
+		return ret;
+	}
+
+	return tcpci_update_reg8(&cfg->bus, RT1715_REG_SYS_CTRL_1,
+				 RT1715_REG_SYS_CTRL_1_BMCIO_LP_EN,
+				 enable ? RT1715_REG_SYS_CTRL_1_BMCIO_LP_EN : 0);
+}
+
+static int rt1715_tcpc_sop_prime_enable(const struct device *dev, bool enable)
+{
+	struct rt1715_data *data = dev->data;
+
+	data->rx_sop_prime_enable = enable;
+
+	return 0;
+}
+
+static int rt1715_tcpc_set_bist_test_mode(const struct device *dev, bool enable)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+
+	return tcpci_tcpm_set_bist_test_mode(&cfg->bus, enable);
+}
+
+static int rt1715_tcpc_set_alert_handler_cb(const struct device *dev,
+					    tcpc_alert_handler_cb_t handler, void *handler_data)
+{
+	struct rt1715_data *data = dev->data;
+
+	if (data->alert_handler == handler && data->alert_handler_data == handler_data) {
+		return 0;
+	}
+
+	data->alert_handler = handler;
+	data->alert_handler_data = handler_data;
+
+	return 0;
+}
+
+static DEVICE_API(tcpc, rt1715_driver_api) = {
+	.init = rt1715_tcpc_init,
+	.get_cc = rt1715_tcpc_get_cc,
+	.select_rp_value = rt1715_tcpc_select_rp_value,
+	.get_rp_value = rt1715_tcpc_get_rp_value,
+	.set_cc = rt1715_tcpc_set_cc,
+	.set_vconn_discharge_cb = rt1715_tcpc_set_vconn_discharge_cb,
+	.set_vconn_cb = rt1715_tcpc_set_vconn_cb,
+	.vconn_discharge = rt1715_tcpc_vconn_discharge,
+	.set_vconn = rt1715_tcpc_set_vconn,
+	.set_roles = rt1715_tcpc_set_roles,
+	.get_rx_pending_msg = rt1715_tcpc_get_rx_pending_msg,
+	.set_rx_enable = rt1715_tcpc_set_rx_enable,
+	.set_cc_polarity = rt1715_tcpc_set_cc_polarity,
+	.transmit_data = rt1715_tcpc_transmit_data,
+	.dump_std_reg = rt1715_tcpc_dump_std_reg,
+	.alert_handler_cb = rt1715_tcpc_alert_handler_cb,
+	.get_status_register = rt1715_tcpc_get_status_register,
+	.clear_status_register = rt1715_tcpc_clear_status_register,
+	.mask_status_register = rt1715_tcpc_mask_status_register,
+	.set_drp_toggle = rt1715_tcpc_set_drp_toggle,
+	.get_chip_info = rt1715_tcpc_get_chip_info,
+	.set_low_power_mode = rt1715_tcpc_set_low_power_mode,
+	.sop_prime_enable = rt1715_tcpc_sop_prime_enable,
+	.set_bist_test_mode = rt1715_tcpc_set_bist_test_mode,
+	.set_alert_handler_cb = rt1715_tcpc_set_alert_handler_cb,
+};
+
+void rt1715_alert_cb(const struct device *port, struct gpio_callback *cb, gpio_port_pins_t pins)
+{
+	struct rt1715_data *data = CONTAINER_OF(cb, struct rt1715_data, alert_cb);
+
+	k_work_submit(&data->alert_work);
+}
+
+void rt1715_alert_work_cb(struct k_work *work)
+{
+	struct rt1715_data *data = CONTAINER_OF(work, struct rt1715_data, alert_work);
+	const struct device *dev = data->dev;
+	const struct rt1715_cfg *cfg = dev->config;
+	uint16_t alert_reg = 0;
+	uint16_t clear_flags = 0;
+
+	if (!data->initialized) {
+		return;
+	}
+
+	tcpci_tcpm_get_status_register(&cfg->bus, TCPC_ALERT_STATUS, &alert_reg);
+
+	while (alert_reg != 0) {
+		enum tcpc_alert alert_type = tcpci_alert_reg_to_enum(alert_reg);
+
+		if (alert_type == TCPC_ALERT_HARD_RESET_RECEIVED) {
+			LOG_DBG("hard rst received");
+			tcpci_init_alert_mask(dev);
+			data->cc_changed = true;
+		} else if (alert_type == TCPC_ALERT_FAULT_STATUS) {
+			uint8_t fault;
+
+			tcpci_tcpm_get_status_register(&cfg->bus, TCPC_FAULT_STATUS,
+						       (uint16_t *)&fault);
+			tcpci_tcpm_clear_status_register(&cfg->bus, TCPC_FAULT_STATUS,
+							 (uint16_t)fault);
+
+			LOG_DBG("fault: %02x", fault);
+		} else if (alert_type == TCPC_ALERT_POWER_STATUS) {
+			uint8_t pwr_status;
+
+			tcpci_tcpm_get_status_register(&cfg->bus, TCPC_POWER_STATUS,
+						       (uint16_t *)&pwr_status);
+
+			LOG_DBG("power status: %02x", pwr_status);
+		} else if (alert_type == TCPC_ALERT_MSG_STATUS) {
+			LOG_DBG("MSG pending");
+
+			if (rt1715_tcpc_rx_fifo_enqueue(dev) == 0) {
+				data->msg_pending = true;
+			}
+		} else if (alert_type == TCPC_ALERT_CC_STATUS) {
+			data->cc_changed = true;
+		}
+
+		if (data->alert_handler != NULL) {
+			data->alert_handler(dev, data->alert_handler_data, alert_type);
+		}
+
+		clear_flags |= BIT(alert_type);
+		alert_reg &= ~BIT(alert_type);
+	}
+
+	tcpci_tcpm_clear_status_register(&cfg->bus, TCPC_ALERT_STATUS, clear_flags);
+	tcpci_tcpm_get_status_register(&cfg->bus, TCPC_ALERT_STATUS, &alert_reg);
+
+	/* If alert_reg is not 0 or the interrupt signal is still active */
+	if ((alert_reg != 0) || gpio_pin_get_dt(&cfg->alert_gpio)) {
+		k_work_submit(work);
+	}
+}
+
+void rt1715_init_work_cb(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct rt1715_data *data = CONTAINER_OF(dwork, struct rt1715_data, init_dwork);
+
+	const struct rt1715_cfg *cfg = data->dev->config;
+	uint8_t power_reg, lp_reg = 0;
+	struct tcpc_chip_info chip_info;
+	int ret;
+
+	LOG_INF("Initializing RT1715 chip: %s", data->dev->name);
+
+	ret = tcpci_tcpm_get_status_register(&cfg->bus, TCPC_POWER_STATUS, (uint16_t *)&power_reg);
+	if (ret != 0 || (power_reg & TCPC_REG_POWER_STATUS_UNINIT)) {
+		data->init_retries++;
+
+		if (data->init_retries > CONFIG_USBC_TCPC_RT1715_INIT_RETRIES) {
+			LOG_ERR("Chip didn't respond");
+			return;
+		}
+
+		LOG_DBG("Postpone chip initialization %d", data->init_retries);
+		k_work_schedule(&data->init_dwork, K_MSEC(CONFIG_USBC_TCPC_RT1715_INIT_DELAY));
+
+		return;
+	}
+
+	rt1715_tcpc_get_chip_info(data->dev, &chip_info);
+	LOG_INF("Initialized chip is: %04x:%04x:%04x", chip_info.vendor_id, chip_info.product_id,
+		chip_info.device_id);
+
+	/* Exit shutdown mode & Enable ext messages */
+	lp_reg = RT1715_REG_LP_CTRL_SHUTDOWN_OFF | RT1715_REG_LP_CTRL_ENEXTMSG;
+	/* Disable idle mode */
+	lp_reg &= ~RT1715_REG_LP_CTRL_AUTOIDLE_EN;
+	tcpci_write_reg8(&cfg->bus, RT1715_REG_LP_CTRL, lp_reg);
+
+	/* Initialize alert interrupt */
+	gpio_pin_configure_dt(&cfg->alert_gpio, GPIO_INPUT);
+
+	gpio_init_callback(&data->alert_cb, rt1715_alert_cb, BIT(cfg->alert_gpio.pin));
+
+	ret = gpio_add_callback(cfg->alert_gpio.port, &data->alert_cb);
+
+	if (ret != 0) {
+		LOG_ERR("Failed to add alert callback: %d", ret);
+		return;
+	}
+
+	gpio_pin_interrupt_configure_dt(&cfg->alert_gpio, GPIO_INT_EDGE_TO_ACTIVE);
+
+	tcpci_init_alert_mask(data->dev);
+	data->initialized = true;
+
+	/* Disable the vconn and open CC lines to reinitialize the communication with partner */
+	rt1715_tcpc_set_vconn(data->dev, false);
+	rt1715_tcpc_set_cc(data->dev, TC_CC_OPEN);
+
+	/* Check and clear any alert set after initialization */
+	k_work_submit(&data->alert_work);
+}
+
+static int rt1715_dev_init(const struct device *dev)
+{
+	const struct rt1715_cfg *cfg = dev->config;
+	struct rt1715_data *data = dev->data;
+	int ret;
+
+	if (!device_is_ready(cfg->bus.bus)) {
+		return -EIO;
+	}
+
+	/* Resets the chip */
+	ret = tcpci_write_reg8(&cfg->bus, RT1715_REG_SW_RST, RT1715_REG_SW_RST_EN);
+	if (ret != 0) {
+		LOG_ERR("Failed to reset chip: %d", ret);
+		return ret;
+	}
+
+	k_work_init_delayable(&data->init_dwork, rt1715_init_work_cb);
+	k_work_schedule(&data->init_dwork, K_MSEC(CONFIG_USBC_TCPC_RT1715_INIT_DELAY));
+
+	k_work_init(&data->alert_work, rt1715_alert_work_cb);
+
+	return 0;
+}
+
+#define RT1715_DRIVER_DATA_INIT(node)                                                              \
+	{                                                                                          \
+		.dev = DEVICE_DT_GET(node),                                                        \
+		.init_retries = 0,                                                                 \
+		.cc_changed = true,                                                                \
+	}
+
+#define VCONN_CTRL_GPIO(node)                                                                      \
+	.vconn_ctrl_gpio = COND_CODE_1(DT_INST_NODE_HAS_PROP(node, vconn_ctrl_gpios),              \
+				       (GPIO_DT_SPEC_INST_GET(node, vconn_ctrl_gpios)), ({0}))
+
+#define VCONN_DISC_GPIO(node)                                                                      \
+	.vconn_disc_gpio = COND_CODE_1(DT_INST_NODE_HAS_PROP(node, vconn_disc_gpios),              \
+				       (GPIO_DT_SPEC_INST_GET(node, vconn_disc_gpios)), ({0}))
+
+#define RT1715_DRIVER_CFG_INIT(node)                                                               \
+	{                                                                                          \
+		.bus = I2C_DT_SPEC_GET(node),                                                      \
+		.alert_gpio = GPIO_DT_SPEC_GET(node, irq_gpios),                                   \
+		.transmit_retries = DT_PROP(node, transmit_retries),                               \
+		VCONN_CTRL_GPIO(node),                                                             \
+		VCONN_DISC_GPIO(node),                                                             \
+	}
+
+#define RT1715_DRIVER_INIT(inst)                                                                   \
+	static struct rt1715_data drv_data_rt1715##inst =                                          \
+		RT1715_DRIVER_DATA_INIT(DT_DRV_INST(inst));                                        \
+	static struct rt1715_cfg drv_cfg_rt1715##inst = RT1715_DRIVER_CFG_INIT(DT_DRV_INST(inst)); \
+	DEVICE_DT_INST_DEFINE(inst, &rt1715_dev_init, NULL, &drv_data_rt1715##inst,                \
+			      &drv_cfg_rt1715##inst, POST_KERNEL, CONFIG_USBC_TCPC_INIT_PRIORITY,  \
+			      &rt1715_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(RT1715_DRIVER_INIT)
diff --git a/drivers/usb_c/tcpc/rt1715.h b/drivers/usb_c/tcpc/rt1715.h
new file mode 100644
index 00000000000..823aa5f5326
--- /dev/null
+++ b/drivers/usb_c/tcpc/rt1715.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2024 Jianxiong Gu <jianxiong.gu@outlook.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_USBC_TCPC_RT1715_H_
+#define ZEPHYR_DRIVERS_USBC_TCPC_RT1715_H_
+
+#define RT1715_REG_SYS_CTRL_1                    0x90
+/** VCONN OVP occurs and discharge path turn-on */
+#define RT1715_REG_SYS_CTRL_1_VCONN_DISCHARGE_EN BIT(5)
+/** Low power mode Rd or Rp */
+#define RT1715_REG_SYS_CTRL_1_BMCIO_LPR_PRD      BIT(4)
+/** Low power mode enable */
+#define RT1715_REG_SYS_CTRL_1_BMCIO_LP_EN        BIT(3)
+/** BMCIO BandGap enable */
+#define RT1715_REG_SYS_CTRL_1_BMCIO_BG_EN        BIT(2)
+/** VBUS detection enable */
+#define RT1715_REG_SYS_CTRL_1_VBUS_DETECT_EN     BIT(1)
+/** 24M oscillator for BMC communication */
+#define RT1715_REG_SYS_CTRL_1_BMCIO_OSC_EN       BIT(0)
+
+#define RT1715_REG_OCP                0x93
+/** VCONN over-current control selection */
+#define RT1715_REG_OCP_BMCIO_VCON_OCP GENMASK(7, 5)
+#define RT1715_VCON_OCP_200MA         (0 << 5)
+#define RT1715_VCON_OCP_300MA         (1 << 5)
+#define RT1715_VCON_OCP_400MA         (2 << 5)
+#define RT1715_VCON_OCP_500MA         (3 << 5)
+#define RT1715_VCON_OCP_600MA         (4 << 5)
+
+#define RT1715_REG_RT_ST         0x97
+/** If VBUS under 0.8V */
+#define RT1715_REG_RT_ST_VBUS_80 BIT(1)
+
+#define RT1715_REG_RT_INT           0x98
+/** Ra detach */
+#define RT1715_REG_RT_INT_RA_DETACH BIT(5)
+/** VBUS under 0.8V */
+#define RT1715_REG_RT_INT_VBUS_80   BIT(1)
+/** Low power mode exited */
+#define RT1715_REG_RT_INT_WAKEUP    BIT(0)
+
+#define RT1715_REG_RT_INT_MASK 0x99
+
+#define RT1715_REG_LP_CTRL                  0x9B
+/** Clock_300K divided from Clock_24M */
+#define RT1715_REG_LP_CTRL_CK_300K_SEL      BIT(7)
+/** Non-Shutdown mode */
+#define RT1715_REG_LP_CTRL_SHUTDOWN_OFF     BIT(5)
+/** Enable PD3.0 Extended message */
+#define RT1715_REG_LP_CTRL_ENEXTMSG         BIT(4)
+/** Auto enter idle mode enable */
+#define RT1715_REG_LP_CTRL_AUTOIDLE_EN      BIT(3)
+/** Enter idle mode timeout time */
+#define RT1715_REG_LP_CTRL_AUTOIDLE_TIMEOUT GENMASK(2, 0)
+#define RT1715_AUTOIDLE_TIMEOUT_96P0_MS     7
+#define RT1715_AUTOIDLE_TIMEOUT_83P2_MS     6
+#define RT1715_AUTOIDLE_TIMEOUT_70P4_MS     5
+#define RT1715_AUTOIDLE_TIMEOUT_57P6_MS     4
+#define RT1715_AUTOIDLE_TIMEOUT_44P8_MS     3
+#define RT1715_AUTOIDLE_TIMEOUT_32P0_MS     2
+#define RT1715_AUTOIDLE_TIMEOUT_19P2_MS     1
+#define RT1715_AUTOIDLE_TIMEOUT_6P4_MS      0
+
+#define RT1715_REG_SYS_WAKEUP    0x9F
+/** Wakeup function enable */
+#define RT1715_REG_SYS_WAKEUP_EN BIT(7)
+
+#define RT1715_REG_SW_RST    0xA0
+/** Write 1 to trigger software reset */
+#define RT1715_REG_SW_RST_EN BIT(0)
+
+#define RT1715_REG_DRP_CTRL_1      0xA2
+/**
+ * The period a DRP will complete a Source to Sink and back advertisement.
+ * (Period = TDRP * 6.4 + 51.2ms)
+ */
+#define RT1715_REG_DRP_CTRL_1_TDRP GENMASK(3, 0)
+
+#define RT1715_REG_DRP_CTRL_2          0xA3
+/**
+ * The percent of time that a DRP will advertise Source during tDRP.
+ * (DUTY = (DCSRCDRP[9:0] + 1) / 1024)
+ */
+#define RT1715_REG_DRP_CTRL_2_DCSRCDRP GENMASK(9, 0)
+
+#endif /* ZEPHYR_DRIVERS_USBC_TCPC_UCPD_NUMAKER_H_ */
diff --git a/drivers/usb_c/tcpc/tcpci.c b/drivers/usb_c/tcpc/tcpci.c
index ffac0bc8195..17a7291d933 100644
--- a/drivers/usb_c/tcpc/tcpci.c
+++ b/drivers/usb_c/tcpc/tcpci.c
@@ -446,3 +446,241 @@ int tcpci_tcpm_get_cc(const struct i2c_dt_spec *bus, enum tc_cc_voltage_state *c
 
 	return 0;
 }
+
+int tcpci_tcpm_get_chip_info(const struct i2c_dt_spec *bus, struct tcpc_chip_info *chip_info)
+{
+	int ret;
+
+	if (chip_info == NULL) {
+		return -EIO;
+	}
+
+	ret = tcpci_read_reg16(bus, TCPC_REG_VENDOR_ID, &chip_info->vendor_id);
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = tcpci_read_reg16(bus, TCPC_REG_PRODUCT_ID, &chip_info->product_id);
+	if (ret != 0) {
+		return ret;
+	}
+
+	return tcpci_read_reg16(bus, TCPC_REG_BCD_DEV, &chip_info->device_id);
+}
+
+int tcpci_tcpm_dump_std_reg(const struct i2c_dt_spec *bus)
+{
+	uint16_t value;
+
+	for (unsigned int a = 0; a < ARRAY_SIZE(tcpci_std_regs); a++) {
+		switch (tcpci_std_regs[a].size) {
+		case 1:
+			tcpci_read_reg8(bus, tcpci_std_regs[a].addr, (uint8_t *)&value);
+			LOG_INF("- %-30s(0x%02x) =   0x%02x", tcpci_std_regs[a].name,
+				tcpci_std_regs[a].addr, (uint8_t)value);
+			break;
+		case 2:
+			tcpci_read_reg16(bus, tcpci_std_regs[a].addr, &value);
+			LOG_INF("- %-30s(0x%02x) = 0x%04x", tcpci_std_regs[a].name,
+				tcpci_std_regs[a].addr, value);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+int tcpci_tcpm_set_bist_test_mode(const struct i2c_dt_spec *bus, bool enable)
+{
+	return tcpci_update_reg8(bus, TCPC_REG_TCPC_CTRL, TCPC_REG_TCPC_CTRL_BIST_TEST_MODE,
+				 enable ? TCPC_REG_TCPC_CTRL_BIST_TEST_MODE : 0);
+}
+
+int tcpci_tcpm_transmit_data(const struct i2c_dt_spec *bus, struct pd_msg *msg,
+			     const uint8_t retries)
+{
+	int reg = TCPC_REG_TX_BUFFER;
+	int rv;
+	int cnt = 4 * msg->header.number_of_data_objects;
+
+	/* If not SOP* transmission, just write to the transmit register */
+	if (msg->header.message_type >= NUM_SOP_STAR_TYPES) {
+		/*
+		 * Per TCPCI spec, do not specify retry (although the TCPC
+		 * should ignore retry field for these 3 types).
+		 */
+		return tcpci_write_reg8(
+			bus, TCPC_REG_TRANSMIT,
+			TCPC_REG_TRANSMIT_SET_WITHOUT_RETRY(msg->header.message_type));
+	}
+
+	if (cnt > 0) {
+		reg = TCPC_REG_TX_BUFFER;
+		/* TX_BYTE_CNT includes extra bytes for message header */
+		cnt += sizeof(msg->header.raw_value);
+
+		struct i2c_msg buf[3];
+
+		uint8_t tmp[2] = {TCPC_REG_TX_BUFFER, cnt};
+
+		buf[0].buf = tmp;
+		buf[0].len = 2;
+		buf[0].flags = I2C_MSG_WRITE;
+
+		buf[1].buf = (uint8_t *)&msg->header.raw_value;
+		buf[1].len = sizeof(msg->header.raw_value);
+		buf[1].flags = I2C_MSG_WRITE;
+
+		buf[2].buf = (uint8_t *)msg->data;
+		buf[2].len = msg->len;
+		buf[2].flags = I2C_MSG_WRITE | I2C_MSG_STOP;
+
+		if (cnt > sizeof(msg->header.raw_value)) {
+			rv = i2c_transfer(bus->bus, buf, 3, bus->addr);
+		} else {
+			buf[1].flags |= I2C_MSG_STOP;
+			rv = i2c_transfer(bus->bus, buf, 2, bus->addr);
+		}
+
+		/* If tcpc write fails, return error */
+		if (rv) {
+			return rv;
+		}
+	}
+
+	/*
+	 * We always retry in TCPC hardware since the TCPM is too slow to
+	 * respond within tRetry (~195 usec).
+	 *
+	 * The retry count used is dependent on the maximum PD revision
+	 * supported at build time.
+	 */
+	rv = tcpci_write_reg8(bus, TCPC_REG_TRANSMIT,
+			      TCPC_REG_TRANSMIT_SET_WITH_RETRY(retries, msg->type));
+
+	return rv;
+}
+
+int tcpci_tcpm_select_rp_value(const struct i2c_dt_spec *bus, enum tc_rp_value rp)
+{
+	return tcpci_update_reg8(bus, TCPC_REG_ROLE_CTRL, TCPC_REG_ROLE_CTRL_RP_MASK,
+				 TCPC_REG_ROLE_CTRL_SET(0, rp, 0, 0));
+}
+
+int tcpci_tcpm_get_rp_value(const struct i2c_dt_spec *bus, enum tc_rp_value *rp)
+{
+	uint8_t reg_value = 0;
+	int ret;
+
+	ret = tcpci_read_reg8(bus, TCPC_REG_ROLE_CTRL, &reg_value);
+	*rp = TCPC_REG_ROLE_CTRL_RP(reg_value);
+
+	return ret;
+}
+
+int tcpci_tcpm_set_cc(const struct i2c_dt_spec *bus, enum tc_cc_pull pull)
+{
+	return tcpci_update_reg8(bus, TCPC_REG_ROLE_CTRL,
+				 TCPC_REG_ROLE_CTRL_CC1_MASK | TCPC_REG_ROLE_CTRL_CC2_MASK,
+				 TCPC_REG_ROLE_CTRL_SET(0, 0, pull, pull));
+}
+
+int tcpci_tcpm_set_vconn(const struct i2c_dt_spec *bus, bool enable)
+{
+	return tcpci_update_reg8(bus, TCPC_REG_POWER_CTRL, TCPC_REG_POWER_CTRL_VCONN_EN,
+				 enable ? TCPC_REG_POWER_CTRL_VCONN_EN : 0);
+}
+
+int tcpci_tcpm_set_roles(const struct i2c_dt_spec *bus, enum pd_rev_type pd_rev,
+			 enum tc_power_role power_role, enum tc_data_role data_role)
+{
+	return tcpci_update_reg8(bus, TCPC_REG_MSG_HDR_INFO, TCPC_REG_MSG_HDR_INFO_ROLES_MASK,
+				 TCPC_REG_MSG_HDR_INFO_SET(pd_rev, data_role, power_role));
+}
+
+int tcpci_tcpm_set_drp_toggle(const struct i2c_dt_spec *bus, bool enable)
+{
+	return tcpci_update_reg8(bus, TCPC_REG_ROLE_CTRL, TCPC_REG_ROLE_CTRL_DRP_MASK,
+				 TCPC_REG_ROLE_CTRL_SET(enable, 0, 0, 0));
+}
+
+int tcpci_tcpm_set_rx_type(const struct i2c_dt_spec *bus, uint8_t rx_type)
+{
+	return tcpci_write_reg8(bus, TCPC_REG_RX_DETECT, rx_type);
+}
+
+int tcpci_tcpm_set_cc_polarity(const struct i2c_dt_spec *bus, enum tc_cc_polarity polarity)
+{
+	return tcpci_update_reg8(
+		bus, TCPC_REG_TCPC_CTRL, TCPC_REG_TCPC_CTRL_PLUG_ORIENTATION,
+		(polarity == TC_POLARITY_CC1) ? 0 : TCPC_REG_TCPC_CTRL_PLUG_ORIENTATION);
+}
+
+int tcpci_tcpm_get_status_register(const struct i2c_dt_spec *bus, enum tcpc_status_reg reg,
+				   uint16_t *status)
+{
+	switch (reg) {
+	case TCPC_ALERT_STATUS:
+		return tcpci_read_reg16(bus, TCPC_REG_ALERT, status);
+	case TCPC_CC_STATUS:
+		return tcpci_read_reg8(bus, TCPC_REG_CC_STATUS, (uint8_t *)status);
+	case TCPC_POWER_STATUS:
+		return tcpci_read_reg8(bus, TCPC_REG_POWER_STATUS, (uint8_t *)status);
+	case TCPC_FAULT_STATUS:
+		return tcpci_read_reg8(bus, TCPC_REG_FAULT_STATUS, (uint8_t *)status);
+	case TCPC_EXTENDED_STATUS:
+		return tcpci_read_reg8(bus, TCPC_REG_EXT_STATUS, (uint8_t *)status);
+	case TCPC_EXTENDED_ALERT_STATUS:
+		return tcpci_read_reg8(bus, TCPC_REG_ALERT_EXT, (uint8_t *)status);
+	default:
+		LOG_ERR("Not a TCPCI-specified reg address");
+		return -EINVAL;
+	}
+}
+
+int tcpci_tcpm_clear_status_register(const struct i2c_dt_spec *bus, enum tcpc_status_reg reg,
+				     uint16_t mask)
+{
+	switch (reg) {
+	case TCPC_ALERT_STATUS:
+		return tcpci_write_reg16(bus, TCPC_REG_ALERT, mask);
+	case TCPC_CC_STATUS:
+		LOG_ERR("CC_STATUS is cleared by the TCPC");
+		return -EINVAL;
+	case TCPC_POWER_STATUS:
+		LOG_ERR("POWER_STATUS is cleared by the TCPC");
+		return -EINVAL;
+	case TCPC_FAULT_STATUS:
+		return tcpci_write_reg8(bus, TCPC_REG_FAULT_STATUS, (uint8_t)mask);
+	case TCPC_EXTENDED_STATUS:
+		return tcpci_write_reg8(bus, TCPC_REG_EXT_STATUS, (uint8_t)mask);
+	case TCPC_EXTENDED_ALERT_STATUS:
+		return tcpci_write_reg8(bus, TCPC_REG_ALERT_EXT, (uint8_t)mask);
+	default:
+		LOG_ERR("Not a TCPCI-specified reg address");
+		return -EINVAL;
+	}
+}
+
+int tcpci_tcpm_mask_status_register(const struct i2c_dt_spec *bus, enum tcpc_status_reg reg,
+				    uint16_t mask)
+{
+	switch (reg) {
+	case TCPC_ALERT_STATUS:
+		return tcpci_write_reg16(bus, TCPC_REG_ALERT_MASK, mask);
+	case TCPC_CC_STATUS:
+		LOG_ERR("CC_STATUS does not have a corresponding mask register");
+		return -EINVAL;
+	case TCPC_POWER_STATUS:
+		return tcpci_write_reg8(bus, TCPC_REG_POWER_STATUS_MASK, (uint8_t)mask);
+	case TCPC_FAULT_STATUS:
+		return tcpci_write_reg8(bus, TCPC_REG_FAULT_STATUS_MASK, (uint8_t)mask);
+	case TCPC_EXTENDED_STATUS:
+		return tcpci_write_reg8(bus, TCPC_REG_EXT_STATUS_MASK, (uint8_t)mask);
+	case TCPC_EXTENDED_ALERT_STATUS:
+		return tcpci_write_reg8(bus, TCPC_REG_ALERT_EXT_MASK, (uint8_t)mask);
+	default:
+		LOG_ERR("Not a TCPCI-specified reg address");
+		return -EINVAL;
+	}
+}
diff --git a/drivers/video/CMakeLists.txt b/drivers/video/CMakeLists.txt
index 6210f8d881d..102a841648e 100644
--- a/drivers/video/CMakeLists.txt
+++ b/drivers/video/CMakeLists.txt
@@ -3,6 +3,8 @@
 zephyr_library()
 
 zephyr_library_sources(video_common.c)
+zephyr_library_sources(video_ctrls.c)
+zephyr_library_sources(video_device.c)
 
 zephyr_library_sources_ifdef(CONFIG_VIDEO_MCUX_CSI	video_mcux_csi.c)
 zephyr_library_sources_ifdef(CONFIG_VIDEO_MCUX_MIPI_CSI2RX video_mcux_mipi_csi2rx.c)
@@ -18,3 +20,5 @@ zephyr_library_sources_ifdef(CONFIG_VIDEO_ESP32		video_esp32_dvp.c)
 zephyr_library_sources_ifdef(CONFIG_VIDEO_MCUX_SDMA	video_mcux_smartdma.c)
 zephyr_library_sources_ifdef(CONFIG_VIDEO_EMUL_IMAGER	video_emul_imager.c)
 zephyr_library_sources_ifdef(CONFIG_VIDEO_EMUL_RX	video_emul_rx.c)
+
+zephyr_linker_sources(DATA_SECTIONS video.ld)
diff --git a/drivers/video/Kconfig.emul_imager b/drivers/video/Kconfig.emul_imager
index d2752fdd53b..fc495617833 100644
--- a/drivers/video/Kconfig.emul_imager
+++ b/drivers/video/Kconfig.emul_imager
@@ -6,13 +6,9 @@ config VIDEO_EMUL_IMAGER
 	depends on DT_HAS_ZEPHYR_VIDEO_EMUL_IMAGER_ENABLED
 	default y
 	help
-	  Enable driver for the emulated Imager.
-
-config VIDEO_EMUL_IMAGER_FRAMEBUFFER_SIZE
-	int "Internal framebuffer size used for link emulation purpose"
-	default 4096
-	help
-	  Configure the size of the internal framebuffer the emulated Imager
-	  driver uses to simulate MIPI transfers. This is the first field of
-	  dev->data, and the emulated video MIPI driver will `memcpy()` it
-	  into the video buffer.
+	  Enable driver for the emulated Imager. A line buffer contains
+	  the color pattern within the imager data struct, at the first
+	  field, and the "zephyr,video-emul-rx" driver will memcpy() this
+	  line over a full frame, simulating a MIPI link transmetting
+	  the lines of data from the imager to the memory.  The default
+	  value fits 2 bit-per-pixel, 640 pixel-wide frames.
diff --git a/drivers/video/gc2145.c b/drivers/video/gc2145.c
index f7c779f7fc8..3b6596453ee 100644
--- a/drivers/video/gc2145.c
+++ b/drivers/video/gc2145.c
@@ -14,21 +14,25 @@
 #include <zephyr/drivers/gpio.h>
 
 #include <zephyr/logging/log.h>
+
+#include "video_ctrls.h"
+#include "video_device.h"
+
 LOG_MODULE_REGISTER(video_gc2145, CONFIG_VIDEO_LOG_LEVEL);
 
 #define GC2145_REG_AMODE1               0x17
 #define GC2145_AMODE1_WINDOW_MASK       0xFC
 #define GC2145_REG_AMODE1_DEF           0x14
 #define GC2145_REG_OUTPUT_FMT           0x84
+#define GC2145_REG_OUTPUT_FMT_MASK      0x1F
 #define GC2145_REG_OUTPUT_FMT_RGB565    0x06
+#define GC2145_REG_OUTPUT_FMT_YCBYCR    0x02
 #define GC2145_REG_SYNC_MODE            0x86
 #define GC2145_REG_SYNC_MODE_DEF        0x23
 #define GC2145_REG_SYNC_MODE_COL_SWITCH 0x10
 #define GC2145_REG_SYNC_MODE_ROW_SWITCH 0x20
 #define GC2145_REG_RESET                0xFE
 #define GC2145_REG_SW_RESET             0x80
-#define GC2145_PID_VAL                  0x21
-#define GC2145_REV_VAL                  0x55
 #define GC2145_SET_P0_REGS              0x00
 #define GC2145_REG_CROP_ENABLE          0x90
 #define GC2145_CROP_SET_ENABLE          0x01
@@ -79,8 +83,8 @@ static const struct gc2145_reg default_regs[] = {
 	{0x9a, 0x0E}, /* Subsample mode */
 
 	{0x12, 0x2e},
-	{GC2145_REG_OUTPUT_FMT, 0x14}, /* Analog Mode 1 (vflip/mirror[1:0]) */
-	{0x18, 0x22},                  /* Analog Mode 2 */
+	{0x17, 0x14}, /* Analog Mode 1 (vflip/mirror[1:0]) */
+	{0x18, 0x22}, /* Analog Mode 2 */
 	{0x19, 0x0e},
 	{0x1a, 0x01},
 	{0x1b, 0x4b},
@@ -681,12 +685,21 @@ static const struct gc2145_reg default_regs[] = {
 
 struct gc2145_config {
 	struct i2c_dt_spec i2c;
+#if DT_INST_NODE_HAS_PROP(0, pwdn_gpios)
+	struct gpio_dt_spec pwdn_gpio;
+#endif
 #if DT_INST_NODE_HAS_PROP(0, reset_gpios)
 	struct gpio_dt_spec reset_gpio;
 #endif
 };
 
+struct gc2145_ctrls {
+	struct video_ctrl hflip;
+	struct video_ctrl vflip;
+};
+
 struct gc2145_data {
+	struct gc2145_ctrls ctrls;
 	struct video_format fmt;
 };
 
@@ -696,18 +709,23 @@ struct gc2145_data {
 		.height_min = height, .height_max = height, .width_step = 0, .height_step = 0,     \
 	}
 
-enum resolutions {
-	QVGA_RESOLUTION = 0,
-	VGA_RESOLUTION,
-	UXGA_RESOLUTION,
-	RESOLUTIONS_MAX,
-};
+#define RESOLUTION_QVGA_W	320
+#define RESOLUTION_QVGA_H	240
+
+#define RESOLUTION_VGA_W	640
+#define RESOLUTION_VGA_H	480
+
+#define RESOLUTION_UXGA_W	1600
+#define RESOLUTION_UXGA_H	1200
 
 static const struct video_format_cap fmts[] = {
-	[QVGA_RESOLUTION] = GC2145_VIDEO_FORMAT_CAP(320, 240, VIDEO_PIX_FMT_RGB565),   /* QVGA */
-	[VGA_RESOLUTION] = GC2145_VIDEO_FORMAT_CAP(640, 480, VIDEO_PIX_FMT_RGB565),    /* VGA  */
-	[UXGA_RESOLUTION] = GC2145_VIDEO_FORMAT_CAP(1600, 1200, VIDEO_PIX_FMT_RGB565), /* UXGA */
-	[RESOLUTIONS_MAX] = {0},
+	GC2145_VIDEO_FORMAT_CAP(RESOLUTION_QVGA_W, RESOLUTION_QVGA_H, VIDEO_PIX_FMT_RGB565),
+	GC2145_VIDEO_FORMAT_CAP(RESOLUTION_VGA_W, RESOLUTION_VGA_H, VIDEO_PIX_FMT_RGB565),
+	GC2145_VIDEO_FORMAT_CAP(RESOLUTION_UXGA_W, RESOLUTION_UXGA_H, VIDEO_PIX_FMT_RGB565),
+	GC2145_VIDEO_FORMAT_CAP(RESOLUTION_QVGA_W, RESOLUTION_QVGA_H, VIDEO_PIX_FMT_YUYV),
+	GC2145_VIDEO_FORMAT_CAP(RESOLUTION_VGA_W, RESOLUTION_VGA_H, VIDEO_PIX_FMT_YUYV),
+	GC2145_VIDEO_FORMAT_CAP(RESOLUTION_UXGA_W, RESOLUTION_UXGA_H, VIDEO_PIX_FMT_YUYV),
+	{0},
 };
 
 static int gc2145_write_reg(const struct i2c_dt_spec *spec, uint8_t reg_addr, uint8_t value)
@@ -728,8 +746,7 @@ static int gc2145_write_reg(const struct i2c_dt_spec *spec, uint8_t reg_addr, ui
 		}
 		/* If writing failed wait 5ms before next attempt */
 		k_msleep(5);
-
-	} while (tries--);
+	} while (tries-- > 0);
 
 	LOG_ERR("failed to write 0x%x to 0x%x,", value, reg_addr);
 	return ret;
@@ -753,8 +770,7 @@ static int gc2145_read_reg(const struct i2c_dt_spec *spec, uint8_t reg_addr, uin
 		}
 		/* If writing failed wait 5ms before next attempt */
 		k_msleep(5);
-
-	} while (tries--);
+	} while (tries-- > 0);
 
 	LOG_ERR("failed to read 0x%x register", reg_addr);
 	return ret;
@@ -883,6 +899,7 @@ static int gc2145_set_window(const struct device *dev, uint16_t reg, uint16_t x,
 static int gc2145_set_output_format(const struct device *dev, int output_format)
 {
 	int ret;
+	uint8_t old_value;
 	const struct gc2145_config *cfg = dev->config;
 
 	ret = gc2145_write_reg(&cfg->i2c, GC2145_REG_RESET, GC2145_SET_P0_REGS);
@@ -890,13 +907,23 @@ static int gc2145_set_output_format(const struct device *dev, int output_format)
 		return ret;
 	}
 
-	if (output_format != VIDEO_PIX_FMT_RGB565) {
+	/* Map format to sensor format */
+	if (output_format == VIDEO_PIX_FMT_RGB565) {
+		output_format = GC2145_REG_OUTPUT_FMT_RGB565;
+	} else if (output_format == VIDEO_PIX_FMT_YUYV) {
+		output_format = GC2145_REG_OUTPUT_FMT_YCBYCR;
+	} else {
 		LOG_ERR("Image format not supported");
 		return -ENOTSUP;
 	}
 
-	/* Disable JPEG compression and set output to RGB565 */
-	ret = gc2145_write_reg(&cfg->i2c, GC2145_REG_OUTPUT_FMT, GC2145_REG_OUTPUT_FMT_RGB565);
+	ret = gc2145_read_reg(&cfg->i2c, GC2145_REG_OUTPUT_FMT, &old_value);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = gc2145_write_reg(&cfg->i2c, GC2145_REG_OUTPUT_FMT,
+			(old_value & ~GC2145_REG_OUTPUT_FMT_MASK) | output_format);
 	if (ret < 0) {
 		return ret;
 	}
@@ -906,13 +933,11 @@ static int gc2145_set_output_format(const struct device *dev, int output_format)
 	return 0;
 }
 
-static int gc2145_set_resolution(const struct device *dev, enum resolutions res)
+static int gc2145_set_resolution(const struct device *dev, uint32_t w, uint32_t h)
 {
 	int ret;
 	const struct gc2145_config *cfg = dev->config;
 
-	uint16_t w;
-	uint16_t h;
 	uint16_t win_w;
 	uint16_t win_h;
 	uint16_t c_ratio;
@@ -922,29 +947,22 @@ static int gc2145_set_resolution(const struct device *dev, enum resolutions res)
 	uint16_t win_x;
 	uint16_t win_y;
 
-	if (res >= RESOLUTIONS_MAX) {
-		return -EIO;
-	}
-
-	w = fmts[res].width_min;
-	h = fmts[res].height_min;
-
 	/* Add the subsampling factor depending on resolution */
-	switch (res) {
-	case QVGA_RESOLUTION:
+	switch (w) {
+	case RESOLUTION_QVGA_W:
 		c_ratio = 3;
 		r_ratio = 3;
 		break;
-	case VGA_RESOLUTION:
+	case RESOLUTION_VGA_W:
 		c_ratio = 2;
 		r_ratio = 2;
 		break;
-	case UXGA_RESOLUTION:
+	case RESOLUTION_UXGA_W:
 		c_ratio = 1;
 		r_ratio = 1;
 		break;
 	default:
-		LOG_ERR("Unsupported resolution %d", res);
+		LOG_ERR("Unsupported resolution %d %d", w, h);
 		return -EIO;
 	};
 
@@ -1000,21 +1018,23 @@ static uint8_t gc2145_check_connection(const struct device *dev)
 {
 	int ret;
 	const struct gc2145_config *cfg = dev->config;
-	uint8_t reg_pid_val;
-	uint8_t reg_ver_val;
+	uint8_t reg_chip_id[2];
+	uint16_t chip_id;
 
-	ret = gc2145_read_reg(&cfg->i2c, 0xf0, &reg_pid_val);
+	ret = gc2145_read_reg(&cfg->i2c, 0xf0, &reg_chip_id[0]);
 	if (ret < 0) {
 		return ret;
 	}
 
-	ret = gc2145_read_reg(&cfg->i2c, 0xf1, &reg_ver_val);
+	ret = gc2145_read_reg(&cfg->i2c, 0xf1, &reg_chip_id[1]);
 	if (ret < 0) {
 		return ret;
 	}
 
-	if ((reg_ver_val != GC2145_REV_VAL) || (reg_pid_val != GC2145_PID_VAL)) {
-		LOG_WRN("Unexpected GC2145 pid: 0x%x or rev: 0x%x", reg_pid_val, reg_ver_val);
+	chip_id = reg_chip_id[0] << 8 | reg_chip_id[1];
+
+	if (chip_id != 0x2145 && chip_id != 0x2155) {
+		LOG_WRN("Unexpected GC2145 chip ID: 0x%04x", chip_id);
 	}
 
 	return 0;
@@ -1024,29 +1044,23 @@ static int gc2145_set_fmt(const struct device *dev, enum video_endpoint_id ep,
 			  struct video_format *fmt)
 {
 	struct gc2145_data *drv_data = dev->data;
-	enum resolutions res = RESOLUTIONS_MAX;
+	size_t res = ARRAY_SIZE(fmts);
 	int ret;
 
-	/* We only support RGB565 formats */
-	if (fmt->pixelformat != VIDEO_PIX_FMT_RGB565) {
-		LOG_ERR("gc2145 camera supports only RGB565");
-		return -ENOTSUP;
-	}
-
 	if (memcmp(&drv_data->fmt, fmt, sizeof(drv_data->fmt)) == 0) {
 		/* nothing to do */
 		return 0;
 	}
 
 	/* Check if camera is capable of handling given format */
-	for (int i = 0; i < RESOLUTIONS_MAX; i++) {
+	for (int i = 0; i < ARRAY_SIZE(fmts) - 1; i++) {
 		if (fmts[i].width_min == fmt->width && fmts[i].height_min == fmt->height &&
 		    fmts[i].pixelformat == fmt->pixelformat) {
-			res = (enum resolutions)i;
+			res = i;
 			break;
 		}
 	}
-	if (res == RESOLUTIONS_MAX) {
+	if (res == ARRAY_SIZE(fmts)) {
 		LOG_ERR("Image format not supported");
 		return -ENOTSUP;
 	}
@@ -1061,7 +1075,8 @@ static int gc2145_set_fmt(const struct device *dev, enum video_endpoint_id ep,
 	}
 
 	/* Set window size */
-	ret = gc2145_set_resolution(dev, res);
+	ret = gc2145_set_resolution(dev, fmt->width, fmt->height);
+
 	if (ret < 0) {
 		LOG_ERR("Failed to set the resolution");
 		return ret;
@@ -1080,18 +1095,12 @@ static int gc2145_get_fmt(const struct device *dev, enum video_endpoint_id ep,
 	return 0;
 }
 
-static int gc2145_stream_start(const struct device *dev)
+static int gc2145_set_stream(const struct device *dev, bool enable)
 {
 	const struct gc2145_config *cfg = dev->config;
 
-	return gc2145_write_reg(&cfg->i2c, 0xf2, 0x0f);
-}
-
-static int gc2145_stream_stop(const struct device *dev)
-{
-	const struct gc2145_config *cfg = dev->config;
-
-	return gc2145_write_reg(&cfg->i2c, 0xf2, 0x00);
+	return enable ? gc2145_write_reg(&cfg->i2c, 0xf2, 0x0f)
+		      : gc2145_write_reg(&cfg->i2c, 0xf2, 0x00);
 }
 
 static int gc2145_get_caps(const struct device *dev, enum video_endpoint_id ep,
@@ -1101,13 +1110,15 @@ static int gc2145_get_caps(const struct device *dev, enum video_endpoint_id ep,
 	return 0;
 }
 
-static int gc2145_set_ctrl(const struct device *dev, unsigned int cid, void *value)
+static int gc2145_set_ctrl(const struct device *dev, uint32_t id)
 {
-	switch (cid) {
+	struct gc2145_data *drv_data = dev->data;
+
+	switch (id) {
 	case VIDEO_CID_HFLIP:
-		return gc2145_set_ctrl_hmirror(dev, (int)value);
+		return gc2145_set_ctrl_hmirror(dev, drv_data->ctrls.hflip.val);
 	case VIDEO_CID_VFLIP:
-		return gc2145_set_ctrl_vflip(dev, (int)value);
+		return gc2145_set_ctrl_vflip(dev, drv_data->ctrls.vflip.val);
 	default:
 		return -ENOTSUP;
 	}
@@ -1117,19 +1128,42 @@ static DEVICE_API(video, gc2145_driver_api) = {
 	.set_format = gc2145_set_fmt,
 	.get_format = gc2145_get_fmt,
 	.get_caps = gc2145_get_caps,
-	.stream_start = gc2145_stream_start,
-	.stream_stop = gc2145_stream_stop,
+	.set_stream = gc2145_set_stream,
 	.set_ctrl = gc2145_set_ctrl,
 };
 
+static int gc2145_init_controls(const struct device *dev)
+{
+	int ret;
+	struct gc2145_data *drv_data = dev->data;
+	struct gc2145_ctrls *ctrls = &drv_data->ctrls;
+
+	ret = video_init_ctrl(&ctrls->hflip, dev, VIDEO_CID_HFLIP,
+			      (struct video_ctrl_range){.min = 0, .max = 1, .step = 1, .def = 0});
+	if (ret) {
+		return ret;
+	}
+
+	return video_init_ctrl(&ctrls->vflip, dev, VIDEO_CID_VFLIP,
+			       (struct video_ctrl_range){.min = 0, .max = 1, .step = 1, .def = 0});
+}
+
 static int gc2145_init(const struct device *dev)
 {
 	struct video_format fmt;
 	int ret;
-
-#if DT_INST_NODE_HAS_PROP(0, reset_gpios)
 	const struct gc2145_config *cfg = dev->config;
+	(void) cfg;
 
+#if DT_INST_NODE_HAS_PROP(0, pwdn_gpios)
+	ret = gpio_pin_configure_dt(&cfg->pwdn_gpio, GPIO_OUTPUT_INACTIVE);
+	if (ret) {
+		return ret;
+	}
+
+	k_sleep(K_MSEC(10));
+#endif
+#if DT_INST_NODE_HAS_PROP(0, reset_gpios)
 	ret = gpio_pin_configure_dt(&cfg->reset_gpio, GPIO_OUTPUT_ACTIVE);
 	if (ret) {
 		return ret;
@@ -1150,9 +1184,9 @@ static int gc2145_init(const struct device *dev)
 
 	/* set default/init format QVGA RGB565 */
 	fmt.pixelformat = VIDEO_PIX_FMT_RGB565;
-	fmt.width = fmts[QVGA_RESOLUTION].width_min;
-	fmt.height = fmts[QVGA_RESOLUTION].height_min;
-	fmt.pitch = fmts[QVGA_RESOLUTION].width_min * 2;
+	fmt.width = RESOLUTION_QVGA_W;
+	fmt.height = RESOLUTION_QVGA_H;
+	fmt.pitch = RESOLUTION_QVGA_W * 2;
 
 	ret = gc2145_set_fmt(dev, VIDEO_EP_OUT, &fmt);
 	if (ret) {
@@ -1160,12 +1194,16 @@ static int gc2145_init(const struct device *dev)
 		return ret;
 	}
 
-	return 0;
+	/* Initialize controls */
+	return gc2145_init_controls(dev);
 }
 
 /* Unique Instance */
 static const struct gc2145_config gc2145_cfg_0 = {
 	.i2c = I2C_DT_SPEC_INST_GET(0),
+#if DT_INST_NODE_HAS_PROP(0, pwdn_gpios)
+	.pwdn_gpio = GPIO_DT_SPEC_INST_GET(0, pwdn_gpios),
+#endif
 #if DT_INST_NODE_HAS_PROP(0, reset_gpios)
 	.reset_gpio = GPIO_DT_SPEC_INST_GET(0, reset_gpios),
 #endif
@@ -1181,6 +1219,12 @@ static int gc2145_init_0(const struct device *dev)
 		return -ENODEV;
 	}
 
+#if DT_INST_NODE_HAS_PROP(0, pwdn_gpios)
+	if (!gpio_is_ready_dt(&cfg->pwdn_gpio)) {
+		LOG_ERR("%s: device %s is not ready", dev->name, cfg->pwdn_gpio.port->name);
+		return -ENODEV;
+	}
+#endif
 #if DT_INST_NODE_HAS_PROP(0, reset_gpios)
 	if (!gpio_is_ready_dt(&cfg->reset_gpio)) {
 		LOG_ERR("%s: device %s is not ready", dev->name, cfg->reset_gpio.port->name);
@@ -1193,3 +1237,5 @@ static int gc2145_init_0(const struct device *dev)
 
 DEVICE_DT_INST_DEFINE(0, &gc2145_init_0, NULL, &gc2145_data_0, &gc2145_cfg_0, POST_KERNEL,
 		      CONFIG_VIDEO_INIT_PRIORITY, &gc2145_driver_api);
+
+VIDEO_DEVICE_DEFINE(gc2145, DEVICE_DT_INST_GET(0), NULL);
diff --git a/drivers/video/mt9m114.c b/drivers/video/mt9m114.c
index 28d1481d684..16d4e61bb39 100644
--- a/drivers/video/mt9m114.c
+++ b/drivers/video/mt9m114.c
@@ -15,6 +15,9 @@
 #include <zephyr/drivers/video-controls.h>
 #include <zephyr/drivers/i2c.h>
 
+#include "video_ctrls.h"
+#include "video_device.h"
+
 LOG_MODULE_REGISTER(video_mt9m114, CONFIG_VIDEO_LOG_LEVEL);
 
 #define MT9M114_CHIP_ID_VAL 0x2481
@@ -63,7 +66,13 @@ struct mt9m114_config {
 	struct i2c_dt_spec i2c;
 };
 
+struct mt9m114_ctrls {
+	struct video_ctrl hflip;
+	struct video_ctrl vflip;
+};
+
 struct mt9m114_data {
+	struct mt9m114_ctrls ctrls;
 	struct video_format fmt;
 };
 
@@ -451,14 +460,10 @@ static int mt9m114_get_fmt(const struct device *dev, enum video_endpoint_id ep,
 	return 0;
 }
 
-static int mt9m114_stream_start(const struct device *dev)
-{
-	return mt9m114_set_state(dev, MT9M114_SYS_STATE_START_STREAMING);
-}
-
-static int mt9m114_stream_stop(const struct device *dev)
+static int mt9m114_set_stream(const struct device *dev, bool enable)
 {
-	return mt9m114_set_state(dev, MT9M114_SYS_STATE_ENTER_SUSPEND);
+	return enable ? mt9m114_set_state(dev, MT9M114_SYS_STATE_START_STREAMING)
+		      : mt9m114_set_state(dev, MT9M114_SYS_STATE_ENTER_SUSPEND);
 }
 
 static int mt9m114_get_caps(const struct device *dev, enum video_endpoint_id ep,
@@ -468,20 +473,23 @@ static int mt9m114_get_caps(const struct device *dev, enum video_endpoint_id ep,
 	return 0;
 }
 
-static int mt9m114_set_ctrl(const struct device *dev, unsigned int cid, void *value)
+static int mt9m114_set_ctrl(const struct device *dev, uint32_t id)
 {
 	int ret = 0;
+	struct mt9m114_data *drv_data = dev->data;
 
-	switch (cid) {
+	switch (id) {
 	case VIDEO_CID_HFLIP:
-		ret = mt9m114_modify_reg(dev, MT9M114_CAM_SENSOR_CTRL_READ_MODE, 2,
-					MT9M114_CAM_SENSOR_CTRL_HORZ_FLIP_EN,
-					(int)value ? MT9M114_CAM_SENSOR_CTRL_HORZ_FLIP_EN : 0);
+		ret = mt9m114_modify_reg(
+			dev, MT9M114_CAM_SENSOR_CTRL_READ_MODE, 2,
+			MT9M114_CAM_SENSOR_CTRL_HORZ_FLIP_EN,
+			drv_data->ctrls.hflip.val ? MT9M114_CAM_SENSOR_CTRL_HORZ_FLIP_EN : 0);
 		break;
 	case VIDEO_CID_VFLIP:
-		ret = mt9m114_modify_reg(dev, MT9M114_CAM_SENSOR_CTRL_READ_MODE, 2,
-					MT9M114_CAM_SENSOR_CTRL_VERT_FLIP_EN,
-					(int)value ? MT9M114_CAM_SENSOR_CTRL_VERT_FLIP_EN : 0);
+		ret = mt9m114_modify_reg(
+			dev, MT9M114_CAM_SENSOR_CTRL_READ_MODE, 2,
+			MT9M114_CAM_SENSOR_CTRL_VERT_FLIP_EN,
+			drv_data->ctrls.vflip.val ? MT9M114_CAM_SENSOR_CTRL_VERT_FLIP_EN : 0);
 		break;
 	default:
 		return -ENOTSUP;
@@ -499,11 +507,26 @@ static DEVICE_API(video, mt9m114_driver_api) = {
 	.set_format = mt9m114_set_fmt,
 	.get_format = mt9m114_get_fmt,
 	.get_caps = mt9m114_get_caps,
-	.stream_start = mt9m114_stream_start,
-	.stream_stop = mt9m114_stream_stop,
+	.set_stream = mt9m114_set_stream,
 	.set_ctrl = mt9m114_set_ctrl,
 };
 
+static int mt9m114_init_controls(const struct device *dev)
+{
+	int ret;
+	struct mt9m114_data *drv_data = dev->data;
+	struct mt9m114_ctrls *ctrls = &drv_data->ctrls;
+
+	ret = video_init_ctrl(&ctrls->hflip, dev, VIDEO_CID_HFLIP,
+			      (struct video_ctrl_range){.min = 0, .max = 1, .step = 1, .def = 0});
+	if (ret) {
+		return ret;
+	}
+
+	return video_init_ctrl(&ctrls->vflip, dev, VIDEO_CID_VFLIP,
+			       (struct video_ctrl_range){.min = 0, .max = 1, .step = 1, .def = 0});
+}
+
 static int mt9m114_init(const struct device *dev)
 {
 	struct video_format fmt;
@@ -549,7 +572,8 @@ static int mt9m114_init(const struct device *dev)
 	/* Suspend any stream */
 	mt9m114_set_state(dev, MT9M114_SYS_STATE_ENTER_SUSPEND);
 
-	return 0;
+	/* Initialize controls */
+	return mt9m114_init_controls(dev);
 }
 
 #if 1 /* Unique Instance */
@@ -574,4 +598,7 @@ static int mt9m114_init_0(const struct device *dev)
 
 DEVICE_DT_INST_DEFINE(0, &mt9m114_init_0, NULL, &mt9m114_data_0, &mt9m114_cfg_0, POST_KERNEL,
 		      CONFIG_VIDEO_INIT_PRIORITY, &mt9m114_driver_api);
+
+VIDEO_DEVICE_DEFINE(mt9m114, DEVICE_DT_INST_GET(0), NULL);
+
 #endif
diff --git a/drivers/video/ov2640.c b/drivers/video/ov2640.c
index 987d97aa305..5da0c2d504e 100644
--- a/drivers/video/ov2640.c
+++ b/drivers/video/ov2640.c
@@ -14,6 +14,9 @@
 #include <zephyr/drivers/i2c.h>
 #include <zephyr/drivers/gpio.h>
 
+#include "video_ctrls.h"
+#include "video_device.h"
+
 LOG_MODULE_REGISTER(video_ov2640, CONFIG_VIDEO_LOG_LEVEL);
 
 /* DSP register bank FF=0x00*/
@@ -439,7 +442,21 @@ struct ov2640_config {
 	uint8_t clock_rate_control;
 };
 
+struct ov2640_ctrls {
+	struct video_ctrl hflip;
+	struct video_ctrl vflip;
+	struct video_ctrl ae;
+	struct video_ctrl awb;
+	struct video_ctrl gain;
+	struct video_ctrl contrast;
+	struct video_ctrl brightness;
+	struct video_ctrl saturation;
+	struct video_ctrl jpeg;
+	struct video_ctrl test_pattern;
+};
+
 struct ov2640_data {
+	struct ov2640_ctrls ctrls;
 	struct video_format fmt;
 };
 
@@ -490,7 +507,7 @@ static int ov2640_write_reg(const struct i2c_dt_spec *spec, uint8_t reg_addr,
 	 * just to be sure that the connection error is not caused by driver
 	 * itself.
 	 */
-	while (tries--) {
+	while (tries-- > 0) {
 		if (!i2c_reg_write_byte_dt(spec, reg_addr, value)) {
 			return 0;
 		}
@@ -513,7 +530,7 @@ static int ov2640_read_reg(const struct i2c_dt_spec *spec, uint8_t reg_addr)
 	 * just to be sure that the connection error is not caused by driver
 	 * itself.
 	 */
-	while (tries--) {
+	while (tries-- > 0) {
 		if (!i2c_reg_read_byte_dt(spec, reg_addr, &value)) {
 			return value;
 		}
@@ -563,10 +580,7 @@ static int ov2640_set_level(const struct device *dev, int level,
 	int ret = 0;
 	const struct ov2640_config *cfg = dev->config;
 
-	level += (max_level / 2 + 1);
-	if (level < 0 || level > max_level) {
-		return -ENOTSUP;
-	}
+	level += max_level / 2 + 1;
 
 	/* Switch to DSP register bank */
 	ret |= ov2640_write_reg(&cfg->i2c, BANK_SEL, BANK_SEL_DSP);
@@ -578,48 +592,6 @@ static int ov2640_set_level(const struct device *dev, int level,
 	return ret;
 }
 
-static int ov2640_set_brightness(const struct device *dev, int level)
-{
-	int ret = 0;
-
-	ret = ov2640_set_level(dev, level, NUM_BRIGHTNESS_LEVELS,
-			ARRAY_SIZE(brightness_regs[0]), brightness_regs);
-
-	if (ret == -ENOTSUP) {
-		LOG_ERR("Brightness level %d not supported", level);
-	}
-
-	return ret;
-}
-
-static int ov2640_set_saturation(const struct device *dev, int level)
-{
-	int ret = 0;
-
-	ret = ov2640_set_level(dev, level, NUM_SATURATION_LEVELS,
-			ARRAY_SIZE(saturation_regs[0]), saturation_regs);
-
-	if (ret == -ENOTSUP) {
-		LOG_ERR("Saturation level %d not supported", level);
-	}
-
-	return ret;
-}
-
-static int ov2640_set_contrast(const struct device *dev, int level)
-{
-	int ret = 0;
-
-	ret = ov2640_set_level(dev, level, NUM_CONTRAST_LEVELS,
-			ARRAY_SIZE(contrast_regs[0]), contrast_regs);
-
-	if (ret == -ENOTSUP) {
-		LOG_ERR("Contrast level %d not supported", level);
-	}
-
-	return ret;
-}
-
 static int ov2640_set_output_format(const struct device *dev,
 				int output_format)
 {
@@ -910,12 +882,7 @@ static int ov2640_get_fmt(const struct device *dev,
 	return 0;
 }
 
-static int ov2640_stream_start(const struct device *dev)
-{
-	return 0;
-}
-
-static int ov2640_stream_stop(const struct device *dev)
+static int ov2640_set_stream(const struct device *dev, bool enable)
 {
 	return 0;
 }
@@ -928,58 +895,113 @@ static int ov2640_get_caps(const struct device *dev,
 	return 0;
 }
 
-static int ov2640_set_ctrl(const struct device *dev,
-				unsigned int cid, void *value)
+static int ov2640_set_ctrl(const struct device *dev, uint32_t id)
 {
-	int ret = 0;
+	struct ov2640_data *drv_data = dev->data;
+	struct ov2640_ctrls *ctrls = &drv_data->ctrls;
 
-	switch (cid) {
+	switch (id) {
 	case VIDEO_CID_HFLIP:
-		ret |= ov2640_set_horizontal_mirror(dev, (int)value);
-		break;
+		return ov2640_set_horizontal_mirror(dev, ctrls->hflip.val);
 	case VIDEO_CID_VFLIP:
-		ret |= ov2640_set_vertical_flip(dev, (int)value);
-		break;
+		return ov2640_set_vertical_flip(dev, ctrls->vflip.val);
 	case VIDEO_CID_EXPOSURE:
-		ret |= ov2640_set_exposure_ctrl(dev, (int)value);
-		break;
+		return ov2640_set_exposure_ctrl(dev, ctrls->ae.val);
+	case VIDEO_CID_WHITE_BALANCE_TEMPERATURE:
+		return ov2640_set_white_bal(dev, ctrls->awb.val);
 	case VIDEO_CID_GAIN:
-		ret |= ov2640_set_gain_ctrl(dev, (int)value);
-		break;
+		return ov2640_set_gain_ctrl(dev, ctrls->gain.val);
 	case VIDEO_CID_BRIGHTNESS:
-		ret |= ov2640_set_brightness(dev, (int)value);
-		break;
-	case VIDEO_CID_SATURATION:
-		ret |= ov2640_set_saturation(dev, (int)value);
-		break;
-	case VIDEO_CID_WHITE_BALANCE_TEMPERATURE:
-		ret |= ov2640_set_white_bal(dev, (int)value);
-		break;
+		return ov2640_set_level(dev, ctrls->brightness.val, NUM_BRIGHTNESS_LEVELS,
+					ARRAY_SIZE(brightness_regs[0]), brightness_regs);
 	case VIDEO_CID_CONTRAST:
-		ret |= ov2640_set_contrast(dev, (int)value);
-		break;
-	case VIDEO_CID_TEST_PATTERN:
-		ret |= ov2640_set_colorbar(dev, (int)value);
-		break;
+		return ov2640_set_level(dev, ctrls->contrast.val, NUM_CONTRAST_LEVELS,
+					ARRAY_SIZE(contrast_regs[0]), contrast_regs);
+	case VIDEO_CID_SATURATION:
+		return ov2640_set_level(dev, ctrls->saturation.val, NUM_SATURATION_LEVELS,
+					ARRAY_SIZE(saturation_regs[0]), saturation_regs);
 	case VIDEO_CID_JPEG_COMPRESSION_QUALITY:
-		ret |= ov2640_set_quality(dev, (int)value);
-		break;
+		return ov2640_set_quality(dev, ctrls->jpeg.val);
+	case VIDEO_CID_TEST_PATTERN:
+		return ov2640_set_colorbar(dev, ctrls->test_pattern.val);
 	default:
 		return -ENOTSUP;
 	}
-
-	return ret;
 }
 
 static DEVICE_API(video, ov2640_driver_api) = {
 	.set_format = ov2640_set_fmt,
 	.get_format = ov2640_get_fmt,
 	.get_caps = ov2640_get_caps,
-	.stream_start = ov2640_stream_start,
-	.stream_stop = ov2640_stream_stop,
+	.set_stream = ov2640_set_stream,
 	.set_ctrl = ov2640_set_ctrl,
 };
 
+static int ov2640_init_controls(const struct device *dev)
+{
+	int ret;
+	struct ov2640_data *drv_data = dev->data;
+	struct ov2640_ctrls *ctrls = &drv_data->ctrls;
+
+	ret = video_init_ctrl(&ctrls->hflip, dev, VIDEO_CID_HFLIP,
+			      (struct video_ctrl_range){.min = 0, .max = 1, .step = 1, .def = 0});
+	if (ret) {
+		return ret;
+	}
+
+	ret = video_init_ctrl(&ctrls->vflip, dev, VIDEO_CID_VFLIP,
+			      (struct video_ctrl_range){.min = 0, .max = 1, .step = 1, .def = 0});
+	if (ret) {
+		return ret;
+	}
+
+	ret = video_init_ctrl(&ctrls->ae, dev, VIDEO_CID_EXPOSURE,
+			      (struct video_ctrl_range){.min = 0, .max = 1, .step = 1, .def = 1});
+	if (ret) {
+		return ret;
+	}
+
+	ret = video_init_ctrl(&ctrls->awb, dev, VIDEO_CID_WHITE_BALANCE_TEMPERATURE,
+			      (struct video_ctrl_range){.min = 0, .max = 1, .step = 1, .def = 1});
+	if (ret) {
+		return ret;
+	}
+
+	ret = video_init_ctrl(&ctrls->gain, dev, VIDEO_CID_GAIN,
+			      (struct video_ctrl_range){.min = 0, .max = 1, .step = 1, .def = 1});
+	if (ret) {
+		return ret;
+	}
+
+	ret = video_init_ctrl(&ctrls->brightness, dev, VIDEO_CID_BRIGHTNESS,
+			      (struct video_ctrl_range){.min = -2, .max = 2, .step = 1, .def = 0});
+	if (ret) {
+		return ret;
+	}
+
+	ret = video_init_ctrl(&ctrls->contrast, dev, VIDEO_CID_CONTRAST,
+			      (struct video_ctrl_range){.min = -2, .max = 2, .step = 1, .def = 0});
+	if (ret) {
+		return ret;
+	}
+
+	ret = video_init_ctrl(&ctrls->saturation, dev, VIDEO_CID_SATURATION,
+			      (struct video_ctrl_range){.min = -2, .max = 2, .step = 1, .def = 0});
+	if (ret) {
+		return ret;
+	}
+
+	ret = video_init_ctrl(
+		&ctrls->jpeg, dev, VIDEO_CID_JPEG_COMPRESSION_QUALITY,
+		(struct video_ctrl_range){.min = 5, .max = 100, .step = 1, .def = 50});
+	if (ret) {
+		return ret;
+	}
+
+	return video_init_ctrl(&ctrls->test_pattern, dev, VIDEO_CID_TEST_PATTERN,
+			       (struct video_ctrl_range){.min = 0, .max = 1, .step = 1, .def = 0});
+}
+
 static int ov2640_init(const struct device *dev)
 {
 	struct video_format fmt;
@@ -1024,7 +1046,12 @@ static int ov2640_init(const struct device *dev)
 	ret |= ov2640_set_exposure_ctrl(dev, 1);
 	ret |= ov2640_set_white_bal(dev, 1);
 
-	return ret;
+	if (ret) {
+		return ret;
+	}
+
+	/* Initialize controls */
+	return ov2640_init_controls(dev);
 }
 
 /* Unique Instance */
@@ -1068,3 +1095,5 @@ DEVICE_DT_INST_DEFINE(0, &ov2640_init_0, NULL,
 			&ov2640_data_0, &ov2640_cfg_0,
 			POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY,
 			&ov2640_driver_api);
+
+VIDEO_DEVICE_DEFINE(ov2640, DEVICE_DT_INST_GET(0), NULL);
diff --git a/drivers/video/ov5640.c b/drivers/video/ov5640.c
index 7b871fb5e28..c70908a2434 100644
--- a/drivers/video/ov5640.c
+++ b/drivers/video/ov5640.c
@@ -1,5 +1,6 @@
 /*
  * Copyright 2024 NXP
+ * Copyright (c) 2025, Charles Dias
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,6 +17,10 @@
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/drivers/video.h>
 #include <zephyr/drivers/video-controls.h>
+#include <zephyr/dt-bindings/video/video-interfaces.h>
+
+#include "video_ctrls.h"
+#include "video_device.h"
 
 LOG_MODULE_REGISTER(video_ov5640, CONFIG_VIDEO_LOG_LEVEL);
 
@@ -114,6 +119,7 @@ struct ov5640_config {
 	struct i2c_dt_spec i2c;
 	struct gpio_dt_spec reset_gpio;
 	struct gpio_dt_spec powerdown_gpio;
+	int bus_type;
 };
 
 struct ov5640_reg {
@@ -131,20 +137,39 @@ struct ov5640_mipi_frmrate_config {
 struct ov5640_mode_config {
 	uint16_t width;
 	uint16_t height;
+	uint16_t array_size_res_params;
 	const struct ov5640_reg *res_params;
 	const struct ov5640_mipi_frmrate_config *mipi_frmrate_config;
 	uint16_t max_frmrate;
 	uint16_t def_frmrate;
 };
 
+struct ov5640_ctrls {
+	/* gain auto-cluster */
+	struct {
+		struct video_ctrl auto_gain;
+		struct video_ctrl gain;
+	};
+	struct video_ctrl brightness;
+	struct video_ctrl contrast;
+	struct video_ctrl hue;
+	struct video_ctrl saturation;
+	struct video_ctrl hflip;
+	struct video_ctrl vflip;
+	struct video_ctrl light_freq;
+	struct video_ctrl test_pattern;
+	struct video_ctrl pixel_rate;
+};
+
 struct ov5640_data {
+	struct ov5640_ctrls ctrls;
 	struct video_format fmt;
 	uint64_t cur_pixrate;
 	uint16_t cur_frmrate;
 	const struct ov5640_mode_config *cur_mode;
 };
 
-static const struct ov5640_reg init_params[] = {
+static const struct ov5640_reg init_params_common[] = {
 	/* Power down */
 	{SYS_CTRL0_REG, SYS_CTRL0_SW_PWDN},
 
@@ -359,14 +384,131 @@ static const struct ov5640_reg init_params[] = {
 	{0x5000, 0xa7},
 };
 
-static const struct ov5640_reg low_res_params[] = {
+static const struct ov5640_reg init_params_dvp[] = {
+	{0x4740, 0x21},
+	{0x4050, 0x6e},
+	{0x4051, 0x8f},
+	{0x3017, 0xff},
+	{0x3018, 0xff},
+	{0x302c, 0x02},
+	{0x3108, 0x01},
+	{0x3630, 0x2e},
+	{0x3a18, 0x00},
+	{0x3a19, 0xf8},
+	{0x3635, 0x1c},
+	{0x3c04, 0x28},
+	{0x3c05, 0x98},
+	{0x3c06, 0x00},
+	{0x3c07, 0x08},
+	{0x3c08, 0x00},
+	{0x3c09, 0x1c},
+	{0x3c0a, 0x9c},
+	{0x3c0b, 0x40},
+	{TIMING_TC_REG20_REG, 0x47},
+	{TIMING_TC_REG21_REG, 0x01},
+	{0x3800, 0x00},
+	{0x3801, 0x00},
+	{0x3802, 0x00},
+	{0x3803, 0x04},
+	{0x3804, 0x0a},
+	{0x3805, 0x3f},
+	{0x3806, 0x07},
+	{0x3807, 0x9b},
+	{0x3808, 0x05},
+	{0x3809, 0x00},
+	{0x380a, 0x03},
+	{0x380b, 0xc0},
+	{0x3810, 0x00},
+	{0x3811, 0x10},
+	{0x3812, 0x00},
+	{0x3813, 0x06},
+	{0x3814, 0x31},
+	{0x3815, 0x31},
+	{0x3034, 0x1a},
+	{0x3035, 0x11},
+	{0x3036, 0x64},
+	{0x3037, 0x13},
+	{0x3038, 0x00},
+	{0x3039, 0x00},
+	{0x380c, 0x07},
+	{0x380d, 0x68},
+	{0x380e, 0x03},
+	{0x380f, 0xd8},
+	{0x3c01, 0xb4},
+	{0x3c00, 0x04},
+	{0x3a08, 0x00},
+	{0x3a09, 0x93},
+	{0x3a0e, 0x06},
+	{0x3a0a, 0x00},
+	{0x3a0b, 0x7b},
+	{0x3a0d, 0x08},
+	{0x3a00, 0x38},
+	{0x3a02, 0x05},
+	{0x3a03, 0xc4},
+	{0x3a14, 0x05},
+	{0x3a15, 0xc4},
+	{0x300e, 0x58},
+	{0x302e, 0x00},
+	{0x4300, 0x30},
+	{0x501f, 0x00},
+	{0x4713, 0x04},
+	{0x4407, 0x04},
+	{0x460b, 0x35},
+	{0x460c, 0x22},
+	{0x3824, 0x02},
+	{0x3406, 0x01},
+	{0x3400, 0x06},
+	{0x3401, 0x80},
+	{0x3402, 0x04},
+	{0x3403, 0x00},
+	{0x3404, 0x06},
+	{0x3405, 0x00},
+	{0x5688, 0x22},
+	{0x5689, 0x22},
+	{0x568a, 0x42},
+	{0x568b, 0x24},
+	{0x568c, 0x42},
+	{0x568d, 0x24},
+	{0x568e, 0x22},
+	{0x568f, 0x22},
+	{0x5025, 0x00},
+	{0x3406, 0x00},
+	{0x3503, 0x00},
+	{0x3008, 0x02},
+	{0x3a02, 0x07},
+	{0x3a03, 0xae},
+	{0x3a08, 0x01},
+	{0x3a09, 0x27},
+	{0x3a0a, 0x00},
+	{0x3a0b, 0xf6},
+	{0x3a0e, 0x06},
+	{0x3a0d, 0x08},
+	{0x3a14, 0x07},
+	{0x3a15, 0xae},
+};
+
+static const struct ov5640_reg csi2_qqvga_res_params[] = {
+	{0x3800, 0x00}, {0x3801, 0x10}, {0x3802, 0x00}, {0x3803, 0x0E}, {0x3804, 0x0a},
+	{0x3805, 0x2f}, {0x3806, 0x07}, {0x3807, 0xa5}, {0x3808, 0x00}, {0x3809, 0xa0},
+	{0x380a, 0x00}, {0x380b, 0x78}, {0x380c, 0x06}, {0x380d, 0x40}, {0x380e, 0x03},
+	{0x380f, 0xe6}, {0x3810, 0x00}, {0x3811, 0x02}, {0x3812, 0x00}, {0x3813, 0x04},
+	{0x3814, 0x31}, {0x3815, 0x31}, {0x3824, 0x02}, {0x460c, 0x22}};
+
+static const struct ov5640_reg csi2_qvga_res_params[] = {
+	{0x3800, 0x00}, {0x3801, 0x10}, {0x3802, 0x00}, {0x3803, 0x0E}, {0x3804, 0x0a},
+	{0x3805, 0x2f}, {0x3806, 0x07}, {0x3807, 0xa5}, {0x3808, 0x01}, {0x3809, 0x40},
+	{0x380a, 0x00}, {0x380b, 0xf0}, {0x380c, 0x06}, {0x380d, 0x40}, {0x380e, 0x03},
+	{0x380f, 0xe8}, {0x3810, 0x00}, {0x3811, 0x02}, {0x3812, 0x00}, {0x3813, 0x04},
+	{0x3814, 0x31}, {0x3815, 0x31}, {0x3824, 0x02}, {0x460c, 0x22}};
+
+static const struct ov5640_reg csi2_vga_res_params[] = {
 	{0x3800, 0x00}, {0x3801, 0x00}, {0x3802, 0x00}, {0x3803, 0x04}, {0x3804, 0x0a},
 	{0x3805, 0x3f}, {0x3806, 0x07}, {0x3807, 0x9b}, {0x3808, 0x02}, {0x3809, 0x80},
 	{0x380a, 0x01}, {0x380b, 0xe0}, {0x380c, 0x07}, {0x380d, 0x68}, {0x380e, 0x03},
 	{0x380f, 0xd8}, {0x3810, 0x00}, {0x3811, 0x10}, {0x3812, 0x00}, {0x3813, 0x06},
 	{0x3814, 0x31}, {0x3815, 0x31}, {0x3824, 0x02}, {0x460c, 0x22}};
 
-static const struct ov5640_reg hd_res_params[] = {
+static const struct ov5640_reg csi2_hd_res_params[] = {
 	{0x3800, 0x00}, {0x3801, 0x00}, {0x3802, 0x00}, {0x3803, 0xfa}, {0x3804, 0x0a},
 	{0x3805, 0x3f}, {0x3806, 0x06}, {0x3807, 0xa9}, {0x3808, 0x05}, {0x3809, 0x00},
 	{0x380a, 0x02}, {0x380b, 0xd0}, {0x380c, 0x07}, {0x380d, 0x64}, {0x380e, 0x02},
@@ -379,11 +521,36 @@ static const struct ov5640_mipi_frmrate_config mipi_hd_frmrate_params[] = {
 static const struct ov5640_mipi_frmrate_config mipi_vga_frmrate_params[] = {
 	{15, 0x22, 0x38, 24000000}, {30, 0x14, 0x38, 24000000}, {60, 0x14, 0x70, 48000000}};
 
-static const struct ov5640_mode_config modes[] = {
+static const struct ov5640_mipi_frmrate_config mipi_qvga_frmrate_params[] = {
+	{15, 0x22, 0x30, 24000000}, {30, 0x14, 0x30, 24000000}, {60, 0x14, 0x60, 48000000}};
+
+static const struct ov5640_mipi_frmrate_config mipi_qqvga_frmrate_params[] = {
+	{15, 0x22, 0x30, 24000000}, {30, 0x14, 0x30, 24000000}, {60, 0x14, 0x60, 48000000}};
+
+static const struct ov5640_mode_config csi2_modes[] = {
+	{
+		.width = 160,
+		.height = 120,
+		.array_size_res_params = ARRAY_SIZE(csi2_qqvga_res_params),
+		.res_params = csi2_qqvga_res_params,
+		.mipi_frmrate_config = mipi_qqvga_frmrate_params,
+		.max_frmrate = OV5640_60_FPS,
+		.def_frmrate = OV5640_30_FPS,
+	},
+	{
+		.width = 320,
+		.height = 240,
+		.array_size_res_params = ARRAY_SIZE(csi2_qvga_res_params),
+		.res_params = csi2_qvga_res_params,
+		.mipi_frmrate_config = mipi_qvga_frmrate_params,
+		.max_frmrate = OV5640_60_FPS,
+		.def_frmrate = OV5640_30_FPS,
+	},
 	{
 		.width = 640,
 		.height = 480,
-		.res_params = low_res_params,
+		.array_size_res_params = ARRAY_SIZE(csi2_vga_res_params),
+		.res_params = csi2_vga_res_params,
 		.mipi_frmrate_config = mipi_vga_frmrate_params,
 		.max_frmrate = OV5640_60_FPS,
 		.def_frmrate = OV5640_30_FPS,
@@ -391,7 +558,8 @@ static const struct ov5640_mode_config modes[] = {
 	{
 		.width = 1280,
 		.height = 720,
-		.res_params = hd_res_params,
+		.array_size_res_params = ARRAY_SIZE(csi2_hd_res_params),
+		.res_params = csi2_hd_res_params,
 		.mipi_frmrate_config = mipi_hd_frmrate_params,
 		.max_frmrate = OV5640_60_FPS,
 		.def_frmrate = OV5640_30_FPS,
@@ -399,19 +567,90 @@ static const struct ov5640_mode_config modes[] = {
 
 static const int ov5640_frame_rates[] = {OV5640_15_FPS, OV5640_30_FPS, OV5640_60_FPS};
 
-#define OV5640_VIDEO_FORMAT_CAP(width, height, format)                                             \
-	{                                                                                          \
-		.pixelformat = (format), .width_min = (width), .width_max = (width),               \
-		.height_min = (height), .height_max = (height), .width_step = 0, .height_step = 0  \
-	}
+/* Initialization sequence for QQVGA resolution (160x120) */
+static const struct ov5640_reg dvp_160x120_res_params[] = {
+	{0x3800, 0x00}, {0x3801, 0x08}, {0x3802, 0x00}, {0x3803, 0x02}, {0x3804, 0x0a},
+	{0x3805, 0x37}, {0x3806, 0x07}, {0x3807, 0xa1}, {0x3808, 0x00}, {0x3809, 0xa0},
+	{0x380a, 0x00}, {0x380b, 0x78}, {0x380c, 0x06}, {0x380d, 0x14}, {0x380e, 0x03},
+	{0x380f, 0xe8}, {0x3810, 0x00}, {0x3811, 0x04}, {0x3812, 0x00}, {0x3813, 0x02},
+	{0x3814, 0x31}, {0x3815, 0x31}, {0x3820, 0x47}, {0x3821, 0x01}, {0x4602, 0x00},
+	{0x4603, 0xa0}, {0x4604, 0x00}, {0x4605, 0x78}};
+
+/* Initialization sequence for QVGA resolution (320x240) */
+static const struct ov5640_reg dvp_320x240_res_params[] = {
+	{0x3800, 0x00}, {0x3801, 0x08}, {0x3802, 0x00}, {0x3803, 0x02}, {0x3804, 0x0a},
+	{0x3805, 0x37}, {0x3806, 0x07}, {0x3807, 0xa1}, {0x3808, 0x01}, {0x3809, 0x40},
+	{0x380a, 0x00}, {0x380b, 0xf0}, {0x380c, 0x06}, {0x380d, 0x14}, {0x380e, 0x03},
+	{0x380f, 0xe8}, {0x3810, 0x00}, {0x3811, 0x04}, {0x3812, 0x00}, {0x3813, 0x02},
+	{0x3814, 0x31}, {0x3815, 0x31}, {0x3820, 0x47}, {0x3821, 0x01}, {0x4602, 0x01},
+	{0x4603, 0x40}, {0x4604, 0x00}, {0x4605, 0xf0}};
+
+/* Initialization sequence for WQVGA resolution (480x272) */
+static const struct ov5640_reg dvp_480x272_res_params[] = {
+	{0x3800, 0x00}, {0x3801, 0x08}, {0x3802, 0x00}, {0x3803, 0x02}, {0x3804, 0x0a},
+	{0x3805, 0x37}, {0x3806, 0x07}, {0x3807, 0xa1}, {0x3808, 0x01}, {0x3809, 0xe0},
+	{0x380a, 0x01}, {0x380b, 0x10}, {0x380c, 0x06}, {0x380d, 0x14}, {0x380e, 0x03},
+	{0x380f, 0xe8}, {0x3810, 0x00}, {0x3811, 0x04}, {0x3812, 0x00}, {0x3813, 0x79},
+	{0x3814, 0x31}, {0x3815, 0x31}, {0x3820, 0x47}, {0x3821, 0x01}, {0x4602, 0x01},
+	{0x4603, 0xe0}, {0x4604, 0x01}, {0x4605, 0x10}};
+
+static const struct ov5640_mode_config dvp_modes[] = {
+	{
+		.width = 160,
+		.height = 120,
+		.array_size_res_params = ARRAY_SIZE(dvp_160x120_res_params),
+		.res_params = dvp_160x120_res_params,
+		.max_frmrate = OV5640_60_FPS,
+		.def_frmrate = OV5640_30_FPS,
+	},
+	{
+		.width = 320,
+		.height = 240,
+		.array_size_res_params = ARRAY_SIZE(dvp_320x240_res_params),
+		.res_params = dvp_320x240_res_params,
+		.max_frmrate = OV5640_60_FPS,
+		.def_frmrate = OV5640_30_FPS,
+	},
+	{
+		.width = 480,
+		.height = 272,
+		.array_size_res_params = ARRAY_SIZE(dvp_480x272_res_params),
+		.res_params = dvp_480x272_res_params,
+		.max_frmrate = OV5640_60_FPS,
+		.def_frmrate = OV5640_30_FPS,
+	}};
 
-static const struct video_format_cap fmts[] = {
+#define OV5640_VIDEO_FORMAT_CAP(width, height, format)                                             \
+	{.pixelformat = (format),                                                                  \
+	 .width_min = (width),                                                                     \
+	 .width_max = (width),                                                                     \
+	 .height_min = (height),                                                                   \
+	 .height_max = (height),                                                                   \
+	 .width_step = 0,                                                                          \
+	 .height_step = 0}
+
+static const struct video_format_cap csi2_fmts[] = {
 	OV5640_VIDEO_FORMAT_CAP(1280, 720, VIDEO_PIX_FMT_RGB565),
 	OV5640_VIDEO_FORMAT_CAP(1280, 720, VIDEO_PIX_FMT_YUYV),
 	OV5640_VIDEO_FORMAT_CAP(640, 480, VIDEO_PIX_FMT_RGB565),
 	OV5640_VIDEO_FORMAT_CAP(640, 480, VIDEO_PIX_FMT_YUYV),
+	OV5640_VIDEO_FORMAT_CAP(320, 240, VIDEO_PIX_FMT_RGB565),
+	OV5640_VIDEO_FORMAT_CAP(160, 120, VIDEO_PIX_FMT_RGB565),
+	{0}};
+
+static const struct video_format_cap dvp_fmts[] = {
+	OV5640_VIDEO_FORMAT_CAP(160, 120, VIDEO_PIX_FMT_RGB565),
+	OV5640_VIDEO_FORMAT_CAP(320, 240, VIDEO_PIX_FMT_RGB565),
+	OV5640_VIDEO_FORMAT_CAP(480, 272, VIDEO_PIX_FMT_RGB565),
 	{0}};
 
+static inline bool ov5640_is_dvp(const struct device *dev)
+{
+	const struct ov5640_config *cfg = dev->config;
+
+	return cfg->bus_type == VIDEO_BUS_TYPE_PARALLEL;
+}
+
 static int ov5640_read_reg(const struct i2c_dt_spec *spec, const uint16_t addr, void *val,
 			   const uint8_t val_size)
 {
@@ -500,6 +739,34 @@ static int ov5640_write_multi_regs(const struct i2c_dt_spec *spec, const struct
 	return 0;
 }
 
+static int ov5640_set_fmt_dvp(const struct ov5640_config *cfg)
+{
+	int ret = 0;
+
+	ret = ov5640_modify_reg(&cfg->i2c, TIMING_TC_REG21_REG, 0x20, 0x00);
+
+	if (ret) {
+		LOG_ERR("Unable to configure REG: %d on DVP", TIMING_TC_REG21_REG);
+		return ret;
+	}
+
+	ret = ov5640_modify_reg(&cfg->i2c, SYS_RESET02_REG, 0x1C, 0x1C);
+
+	if (ret) {
+		LOG_ERR("Unable to configure REG: %d on DVP", SYS_RESET02_REG);
+		return ret;
+	}
+
+	ret = ov5640_modify_reg(&cfg->i2c, SYS_CLK_ENABLE02_REG, 0x28, 0x00);
+
+	if (ret) {
+		LOG_ERR("Unable to configure REG: %d on DVP", SYS_CLK_ENABLE02_REG);
+		return ret;
+	}
+
+	return 0;
+}
+
 static int ov5640_set_frmival(const struct device *dev, enum video_endpoint_id ep,
 			      struct video_frmival *frmival)
 {
@@ -509,6 +776,10 @@ static int ov5640_set_frmival(const struct device *dev, enum video_endpoint_id e
 	uint8_t i, ind = 0;
 	uint32_t desired_frmrate, best_match = ov5640_frame_rates[ind];
 
+	if (ov5640_is_dvp(dev)) {
+		return -ENOTSUP;
+	}
+
 	desired_frmrate = DIV_ROUND_CLOSEST(frmival->denominator, frmival->numerator);
 
 	/* Find the supported frame rate closest to the desired one */
@@ -543,6 +814,9 @@ static int ov5640_set_frmival(const struct device *dev, enum video_endpoint_id e
 	drv_data->cur_frmrate = best_match;
 	drv_data->cur_pixrate = drv_data->cur_mode->mipi_frmrate_config[ind].pixelrate;
 
+	/* Update pixerate control */
+	drv_data->ctrls.pixel_rate.val = drv_data->cur_pixrate;
+
 	frmival->numerator = 1;
 	frmival->denominator = best_match;
 
@@ -556,8 +830,24 @@ static int ov5640_set_fmt(const struct device *dev, enum video_endpoint_id ep,
 	const struct ov5640_config *cfg = dev->config;
 	int ret, i;
 	struct video_frmival def_frmival;
+	const struct video_format_cap *fmts;
+	const struct ov5640_mode_config *modes;
+	size_t num_fmts;
+	size_t array_size_modes;
+
+	if (ov5640_is_dvp(dev)) {
+		fmts = dvp_fmts;
+		modes = dvp_modes;
+		num_fmts = ARRAY_SIZE(dvp_fmts);
+		array_size_modes = ARRAY_SIZE(dvp_modes);
+	} else {
+		fmts = csi2_fmts;
+		modes = csi2_modes;
+		num_fmts = ARRAY_SIZE(csi2_fmts);
+		array_size_modes = ARRAY_SIZE(csi2_modes);
+	}
 
-	for (i = 0; i < ARRAY_SIZE(fmts); ++i) {
+	for (i = 0; i < num_fmts; ++i) {
 		if (fmt->pixelformat == fmts[i].pixelformat && fmt->width >= fmts[i].width_min &&
 		    fmt->width <= fmts[i].width_max && fmt->height >= fmts[i].height_min &&
 		    fmt->height <= fmts[i].height_max) {
@@ -565,7 +855,7 @@ static int ov5640_set_fmt(const struct device *dev, enum video_endpoint_id ep,
 		}
 	}
 
-	if (i == ARRAY_SIZE(fmts)) {
+	if (i == num_fmts) {
 		LOG_ERR("Unsupported pixel format or resolution");
 		return -ENOTSUP;
 	}
@@ -577,12 +867,10 @@ static int ov5640_set_fmt(const struct device *dev, enum video_endpoint_id ep,
 	drv_data->fmt = *fmt;
 
 	/* Set resolution */
-	for (i = 0; i < ARRAY_SIZE(modes); i++) {
+	for (i = 0; i < array_size_modes; i++) {
 		if (fmt->width == modes[i].width && fmt->height == modes[i].height) {
 			ret = ov5640_write_multi_regs(&cfg->i2c, modes[i].res_params,
-						      modes[i].res_params == hd_res_params
-							      ? ARRAY_SIZE(hd_res_params)
-							      : ARRAY_SIZE(low_res_params));
+						      modes[i].array_size_res_params);
 			if (ret) {
 				LOG_ERR("Unable to set resolution parameters");
 				return ret;
@@ -610,6 +898,10 @@ static int ov5640_set_fmt(const struct device *dev, enum video_endpoint_id ep,
 		return ret;
 	}
 
+	if (ov5640_is_dvp(dev)) {
+		return ov5640_set_fmt_dvp(cfg);
+	}
+
 	/* Set frame rate */
 	def_frmival.denominator = drv_data->cur_mode->def_frmrate;
 	def_frmival.numerator = 1;
@@ -630,34 +922,25 @@ static int ov5640_get_fmt(const struct device *dev, enum video_endpoint_id ep,
 static int ov5640_get_caps(const struct device *dev, enum video_endpoint_id ep,
 			   struct video_caps *caps)
 {
-	caps->format_caps = fmts;
+	caps->format_caps = ov5640_is_dvp(dev) ? dvp_fmts : csi2_fmts;
 	return 0;
 }
 
-static int ov5640_stream_start(const struct device *dev)
+static int ov5640_set_stream(const struct device *dev, bool enable)
 {
 	const struct ov5640_config *cfg = dev->config;
-	/* Power up MIPI PHY HS Tx & LP Rx in 2 data lanes mode */
-	int ret = ov5640_write_reg(&cfg->i2c, IO_MIPI_CTRL00_REG, 0x45);
 
-	if (ret) {
-		LOG_ERR("Unable to power up MIPI PHY");
-		return ret;
+	if (!ov5640_is_dvp(dev)) {
+		/* Power up / down MIPI PHY HS Tx & LP Rx in 2 data lanes mode */
+		int ret = ov5640_write_reg(&cfg->i2c, IO_MIPI_CTRL00_REG, enable ? 0x45 : 0x40);
+		if (ret) {
+			LOG_ERR("Unable to power up / down MIPI PHY");
+			return ret;
+		}
 	}
-	return ov5640_write_reg(&cfg->i2c, SYS_CTRL0_REG, SYS_CTRL0_SW_PWUP);
-}
 
-static int ov5640_stream_stop(const struct device *dev)
-{
-	const struct ov5640_config *cfg = dev->config;
-	/* Power down MIPI PHY HS Tx & LP Rx */
-	int ret = ov5640_write_reg(&cfg->i2c, IO_MIPI_CTRL00_REG, 0x40);
-
-	if (ret) {
-		LOG_ERR("Unable to power down MIPI PHY");
-		return ret;
-	}
-	return ov5640_write_reg(&cfg->i2c, SYS_CTRL0_REG, SYS_CTRL0_SW_PWDN);
+	return ov5640_write_reg(&cfg->i2c, SYS_CTRL0_REG,
+				enable ? SYS_CTRL0_SW_PWUP : SYS_CTRL0_SW_PWDN);
 }
 
 #define TEST_PATTERN_ENABLE  BIT(7)
@@ -673,14 +956,19 @@ static const uint8_t test_pattern_val[] = {
 	TEST_PATTERN_ENABLE | TEST_PATTERN_SQUARE | TEST_PATTERN_ROLLING,
 };
 
+static const char *const test_pattern_menu[] = {
+	"Disabled",
+	"Color bars",
+	"Color bars with rolling bar",
+	"Color squares",
+	"Color squares with rolling bar",
+	NULL
+};
+
 static int ov5640_set_ctrl_test_pattern(const struct device *dev, int value)
 {
 	const struct ov5640_config *cfg = dev->config;
 
-	if (!IN_RANGE(value, 0, ARRAY_SIZE(test_pattern_val) - 1)) {
-		return -EINVAL;
-	}
-
 	return ov5640_write_reg(&cfg->i2c, PRE_ISP_TEST_SET1, test_pattern_val[value]);
 }
 
@@ -689,10 +977,6 @@ static int ov5640_set_ctrl_hue(const struct device *dev, int value)
 	const struct ov5640_config *cfg = dev->config;
 	int cos_coef, sin_coef, sign = 0;
 
-	if (!IN_RANGE(value, 0, 360)) {
-		return -EINVAL;
-	}
-
 	double rad_val = value;
 	int ret = ov5640_modify_reg(&cfg->i2c, SDE_CTRL0_REG, BIT(0), BIT(0));
 
@@ -725,10 +1009,6 @@ static int ov5640_set_ctrl_saturation(const struct device *dev, int value)
 {
 	const struct ov5640_config *cfg = dev->config;
 
-	if (!IN_RANGE(value, 0, UINT8_MAX)) {
-		return -EINVAL;
-	}
-
 	struct ov5640_reg saturation_params[] = {{SDE_CTRL3_REG, value}, {SDE_CTRL4_REG, value}};
 	int ret = ov5640_modify_reg(&cfg->i2c, SDE_CTRL8_REG, BIT(6) | BIT(0), BIT(6) | BIT(0));
 
@@ -743,10 +1023,6 @@ static int ov5640_set_ctrl_brightness(const struct device *dev, int value)
 {
 	const struct ov5640_config *cfg = dev->config;
 
-	if (!IN_RANGE(value, -UINT8_MAX, UINT8_MAX)) {
-		return -EINVAL;
-	}
-
 	struct ov5640_reg brightness_params[] = {{SDE_CTRL8_REG, value >= 0 ? 0x01 : 0x09},
 						 {SDE_CTRL7_REG, abs(value) & 0xff}};
 	int ret = ov5640_modify_reg(&cfg->i2c, SDE_CTRL0_REG, BIT(2), BIT(2));
@@ -762,10 +1038,6 @@ static int ov5640_set_ctrl_contrast(const struct device *dev, int value)
 {
 	const struct ov5640_config *cfg = dev->config;
 
-	if (!IN_RANGE(value, 0, UINT8_MAX)) {
-		return -EINVAL;
-	}
-
 	int ret = ov5640_modify_reg(&cfg->i2c, SDE_CTRL0_REG, BIT(2), BIT(2));
 
 	if (ret) {
@@ -775,28 +1047,30 @@ static int ov5640_set_ctrl_contrast(const struct device *dev, int value)
 	return ov5640_write_reg(&cfg->i2c, SDE_CTRL6_REG, value & 0xff);
 }
 
-static int ov5640_set_ctrl_gain(const struct device *dev, int value)
+static int ov5640_set_ctrl_gain(const struct device *dev)
 {
 	const struct ov5640_config *cfg = dev->config;
+	struct ov5640_data *drv_data = dev->data;
+	struct ov5640_ctrls *ctrls = &drv_data->ctrls;
 
-	if (!IN_RANGE(value, 0, UINT16_MAX)) {
-		return -EINVAL;
-	}
+	int ret = ov5640_modify_reg(&cfg->i2c, AEC_PK_MANUAL, BIT(1),
+				    ctrls->auto_gain.val ? 0 : BIT(1));
 
-	if (value) {
-		int ret = ov5640_modify_reg(&cfg->i2c, AEC_PK_MANUAL, BIT(1), BIT(0));
+	if (ret) {
+		return ret;
+	}
 
+	if (!ctrls->auto_gain.val) {
+		ret = ov5640_modify_reg(&cfg->i2c, AEC_PK_REAL_GAIN, 0x03,
+					(ctrls->gain.val >> 8) & 0x03);
 		if (ret) {
 			return ret;
 		}
 
-		struct ov5640_reg gain_params[] = {{AEC_PK_REAL_GAIN, value >> 8},
-						   {AEC_PK_REAL_GAIN + 1, value & 0xff}};
-
-		return ov5640_write_multi_regs(&cfg->i2c, gain_params, ARRAY_SIZE(gain_params));
-	} else {
-		return ov5640_write_reg(&cfg->i2c, AEC_PK_MANUAL, 0);
+		ret = ov5640_write_reg(&cfg->i2c, AEC_PK_REAL_GAIN + 1, ctrls->gain.val & 0xff);
 	}
+
+	return ret;
 }
 
 static int ov5640_set_ctrl_hflip(const struct device *dev, int value)
@@ -841,44 +1115,66 @@ static int ov5640_set_ctrl_power_line_freq(const struct device *dev, int value)
 	return ov5640_modify_reg(&cfg->i2c, HZ5060_CTRL01_REG, BIT(7), BIT(7));
 }
 
-static int ov5640_set_ctrl(const struct device *dev, unsigned int cid, void *value)
+static int ov5640_set_ctrl(const struct device *dev, uint32_t id)
 {
-	switch (cid) {
+	struct ov5640_data *drv_data = dev->data;
+	struct ov5640_ctrls *ctrls = &drv_data->ctrls;
+
+	switch (id) {
 	case VIDEO_CID_TEST_PATTERN:
-		return ov5640_set_ctrl_test_pattern(dev, (int)value);
+		return ov5640_set_ctrl_test_pattern(dev, ctrls->test_pattern.val);
 	case VIDEO_CID_HUE:
-		return ov5640_set_ctrl_hue(dev, (int)value);
+		return ov5640_set_ctrl_hue(dev, ctrls->hue.val);
 	case VIDEO_CID_SATURATION:
-		return ov5640_set_ctrl_saturation(dev, (int)(value));
+		return ov5640_set_ctrl_saturation(dev, ctrls->saturation.val);
 	case VIDEO_CID_BRIGHTNESS:
-		return ov5640_set_ctrl_brightness(dev, (int)(value));
+		return ov5640_set_ctrl_brightness(dev, ctrls->brightness.val);
 	case VIDEO_CID_CONTRAST:
-		return ov5640_set_ctrl_contrast(dev, (int)value);
-	case VIDEO_CID_GAIN:
-		return ov5640_set_ctrl_gain(dev, (int)(value));
+		return ov5640_set_ctrl_contrast(dev, ctrls->contrast.val);
+	case VIDEO_CID_AUTOGAIN:
+		return ov5640_set_ctrl_gain(dev);
 	case VIDEO_CID_HFLIP:
-		return ov5640_set_ctrl_hflip(dev, (int)(value));
+		return ov5640_set_ctrl_hflip(dev, ctrls->hflip.val);
 	case VIDEO_CID_VFLIP:
-		return ov5640_set_ctrl_vflip(dev, (int)(value));
+		return ov5640_set_ctrl_vflip(dev, ctrls->vflip.val);
 	case VIDEO_CID_POWER_LINE_FREQUENCY:
-		return ov5640_set_ctrl_power_line_freq(dev, (int)(value));
+		return ov5640_set_ctrl_power_line_freq(dev, ctrls->light_freq.val);
 	default:
 		return -ENOTSUP;
 	}
 }
 
-static inline int ov5640_get_ctrl(const struct device *dev, unsigned int cid, void *value)
+static int ov5640_get_gain(const struct device *dev)
 {
-	struct ov5640_data *drv_data = dev->data;
+	int ret;
+	uint16_t gain;
+	const struct ov5640_config *cfg = dev->config;
 
-	switch (cid) {
-	case VIDEO_CID_PIXEL_RATE:
-		*((uint64_t *)value) = drv_data->cur_pixrate;
+	ret = ov5640_read_reg(&cfg->i2c, AEC_PK_REAL_GAIN, &gain, sizeof(gain));
+	if (ret) {
+		return ret;
+	}
 
-		return 0;
-	default:
-		return -ENOTSUP;
+	return gain & 0x3ff;
+}
+
+static int ov5640_get_volatile_ctrl(const struct device *dev, uint32_t id)
+{
+	int val;
+	struct ov5640_data *drv_data = dev->data;
+	struct ov5640_ctrls *ctrls = &drv_data->ctrls;
+
+	switch (id) {
+	case VIDEO_CID_AUTOGAIN:
+		val = ov5640_get_gain(dev);
+		if (val < 0) {
+			return val;
+		}
+		ctrls->gain.val = val;
+		break;
 	}
+
+	return 0;
 }
 
 static int ov5640_get_frmival(const struct device *dev, enum video_endpoint_id ep,
@@ -886,6 +1182,10 @@ static int ov5640_get_frmival(const struct device *dev, enum video_endpoint_id e
 {
 	struct ov5640_data *drv_data = dev->data;
 
+	if (ov5640_is_dvp(dev)) {
+		return -ENOTSUP;
+	}
+
 	frmival->numerator = 1;
 	frmival->denominator = drv_data->cur_frmrate;
 
@@ -897,14 +1197,19 @@ static int ov5640_enum_frmival(const struct device *dev, enum video_endpoint_id
 {
 	uint8_t i = 0;
 
-	for (i = 0; i < ARRAY_SIZE(modes); i++) {
-		if (fie->format->width == modes[i].width &&
-		    fie->format->height == modes[i].height) {
+	if (ov5640_is_dvp(dev)) {
+		return -ENOTSUP;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(csi2_modes); i++) {
+		if (fie->format->width == csi2_modes[i].width &&
+		    fie->format->height == csi2_modes[i].height) {
 			break;
 		}
 	}
-	if (i == ARRAY_SIZE(modes) || fie->index >= ARRAY_SIZE(ov5640_frame_rates) ||
-	    ov5640_frame_rates[fie->index] > modes[i].max_frmrate) {
+
+	if (i == ARRAY_SIZE(csi2_modes) || fie->index >= ARRAY_SIZE(ov5640_frame_rates) ||
+	    ov5640_frame_rates[fie->index] > csi2_modes[i].max_frmrate) {
 		return -EINVAL;
 	}
 
@@ -919,15 +1224,95 @@ static DEVICE_API(video, ov5640_driver_api) = {
 	.set_format = ov5640_set_fmt,
 	.get_format = ov5640_get_fmt,
 	.get_caps = ov5640_get_caps,
-	.stream_start = ov5640_stream_start,
-	.stream_stop = ov5640_stream_stop,
+	.set_stream = ov5640_set_stream,
 	.set_ctrl = ov5640_set_ctrl,
-	.get_ctrl = ov5640_get_ctrl,
+	.get_volatile_ctrl = ov5640_get_volatile_ctrl,
 	.set_frmival = ov5640_set_frmival,
 	.get_frmival = ov5640_get_frmival,
 	.enum_frmival = ov5640_enum_frmival,
 };
 
+static int ov5640_init_controls(const struct device *dev)
+{
+	int ret;
+	struct ov5640_data *drv_data = dev->data;
+	struct ov5640_ctrls *ctrls = &drv_data->ctrls;
+
+	ret = video_init_ctrl(&ctrls->auto_gain, dev, VIDEO_CID_AUTOGAIN,
+			      (struct video_ctrl_range){.min = 0, .max = 1, .step = 1, .def = 1});
+	if (ret) {
+		return ret;
+	}
+
+	ret = video_init_ctrl(
+		&ctrls->gain, dev, VIDEO_CID_ANALOGUE_GAIN,
+		(struct video_ctrl_range){.min = 0, .max = 1023, .step = 1, .def = 0});
+	if (ret) {
+		return ret;
+	}
+
+	video_auto_cluster_ctrl(&ctrls->auto_gain, 2, true);
+
+	ret = video_init_ctrl(
+		&ctrls->brightness, dev, VIDEO_CID_BRIGHTNESS,
+		(struct video_ctrl_range){.min = -15, .max = 15, .step = 1, .def = 0});
+	if (ret) {
+		return ret;
+	}
+
+	ret = video_init_ctrl(&ctrls->contrast, dev, VIDEO_CID_CONTRAST,
+			      (struct video_ctrl_range){.min = 0, .max = 255, .step = 1, .def = 0});
+	if (ret) {
+		return ret;
+	}
+
+	ret = video_init_ctrl(&ctrls->hue, dev, VIDEO_CID_HUE,
+			      (struct video_ctrl_range){.min = 0, .max = 359, .step = 1, .def = 0});
+	if (ret) {
+		return ret;
+	}
+
+	ret = video_init_ctrl(
+		&ctrls->saturation, dev, VIDEO_CID_SATURATION,
+		(struct video_ctrl_range){.min = 0, .max = 255, .step = 1, .def = 64});
+	if (ret) {
+		return ret;
+	}
+
+	ret = video_init_ctrl(&ctrls->hflip, dev, VIDEO_CID_HFLIP,
+			      (struct video_ctrl_range){.min = 0, .max = 1, .step = 1, .def = 0});
+	if (ret) {
+		return ret;
+	}
+
+	ret = video_init_ctrl(&ctrls->vflip, dev, VIDEO_CID_VFLIP,
+			      (struct video_ctrl_range){.min = 0, .max = 1, .step = 1, .def = 0});
+	if (ret) {
+		return ret;
+	}
+
+	ret = video_init_menu_ctrl(&ctrls->light_freq, dev, VIDEO_CID_POWER_LINE_FREQUENCY,
+				   VIDEO_CID_POWER_LINE_FREQUENCY_50HZ, NULL);
+	if (ret) {
+		return ret;
+	}
+
+	ret = video_init_menu_ctrl(&ctrls->test_pattern, dev, VIDEO_CID_TEST_PATTERN, 0,
+				   test_pattern_menu);
+	if (ret) {
+		return ret;
+	}
+
+	return video_init_ctrl(
+		&ctrls->pixel_rate, dev, VIDEO_CID_PIXEL_RATE,
+		(struct video_ctrl_range){
+			.min64 = mipi_qqvga_frmrate_params[0].pixelrate,
+			.max64 = mipi_hd_frmrate_params[ARRAY_SIZE(mipi_hd_frmrate_params) - 1]
+					 .pixelrate,
+			.step64 = 1,
+			.def64 = mipi_hd_frmrate_params[1].pixelrate});
+}
+
 static int ov5640_init(const struct device *dev)
 {
 	const struct ov5640_config *cfg = dev->config;
@@ -979,6 +1364,13 @@ static int ov5640_init(const struct device *dev)
 
 	k_sleep(K_MSEC(20));
 
+	/* Reset all registers */
+	ret = ov5640_write_reg(&cfg->i2c, SCCB_SYS_CTRL1_REG, 0x11);
+	if (ret) {
+		LOG_ERR("Unable to write to reset all registers");
+		return -EIO;
+	}
+
 	/* Software reset */
 	ret = ov5640_write_reg(&cfg->i2c, SYS_CTRL0_REG, SYS_CTRL0_SW_RST);
 	if (ret) {
@@ -989,17 +1381,29 @@ static int ov5640_init(const struct device *dev)
 	k_sleep(K_MSEC(5));
 
 	/* Initialize register values */
-	ret = ov5640_write_multi_regs(&cfg->i2c, init_params, ARRAY_SIZE(init_params));
+	ret = ov5640_write_multi_regs(&cfg->i2c, init_params_common,
+				      ARRAY_SIZE(init_params_common));
 	if (ret) {
 		LOG_ERR("Unable to initialize the sensor");
 		return -EIO;
 	}
 
-	/* Set virtual channel */
-	ret = ov5640_modify_reg(&cfg->i2c, 0x4814, 3U << 6, (uint8_t)(DEFAULT_MIPI_CHANNEL) << 6);
-	if (ret) {
-		LOG_ERR("Unable to set virtual channel");
-		return -EIO;
+	if (ov5640_is_dvp(dev)) {
+		ret = ov5640_write_multi_regs(&cfg->i2c, init_params_dvp,
+					      ARRAY_SIZE(init_params_dvp));
+
+		if (ret) {
+			LOG_ERR("Unable to initialize the sensor with DVP parameters");
+			return -EIO;
+		}
+	} else {
+		/* Set virtual channel */
+		ret = ov5640_modify_reg(&cfg->i2c, 0x4814, 3U << 6,
+					(uint8_t)(DEFAULT_MIPI_CHANNEL) << 6);
+		if (ret) {
+			LOG_ERR("Unable to set virtual channel");
+			return -EIO;
+		}
 	}
 
 	/* Check sensor chip id */
@@ -1016,8 +1420,15 @@ static int ov5640_init(const struct device *dev)
 
 	/* Set default format */
 	fmt.pixelformat = VIDEO_PIX_FMT_RGB565;
-	fmt.width = 1280;
-	fmt.height = 720;
+	if (ov5640_is_dvp(dev)) {
+		/* Set default resolution to QQVGA (160x120) */
+		fmt.width = 160;
+		fmt.height = 120;
+	} else {
+		/* Set default resolution to 720p */
+		fmt.width = 1280;
+		fmt.height = 720;
+	}
 	fmt.pitch = fmt.width * 2;
 	ret = ov5640_set_fmt(dev, VIDEO_EP_OUT, &fmt);
 	if (ret) {
@@ -1025,7 +1436,8 @@ static int ov5640_init(const struct device *dev)
 		return -EIO;
 	}
 
-	return 0;
+	/* Initialize controls */
+	return ov5640_init_controls(dev);
 }
 
 #define OV5640_INIT(n)                                                                             \
@@ -1035,9 +1447,13 @@ static int ov5640_init(const struct device *dev)
 		.i2c = I2C_DT_SPEC_INST_GET(n),                                                    \
 		.reset_gpio = GPIO_DT_SPEC_INST_GET_OR(n, reset_gpios, {0}),                       \
 		.powerdown_gpio = GPIO_DT_SPEC_INST_GET_OR(n, powerdown_gpios, {0}),               \
+		.bus_type = DT_PROP_OR(DT_CHILD(DT_INST_CHILD(n, port), endpoint), bus_type,       \
+				       VIDEO_BUS_TYPE_CSI2_DPHY),                                  \
 	};                                                                                         \
                                                                                                    \
 	DEVICE_DT_INST_DEFINE(n, &ov5640_init, NULL, &ov5640_data_##n, &ov5640_cfg_##n,            \
-			      POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY, &ov5640_driver_api);
+			      POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY, &ov5640_driver_api);        \
+                                                                                                   \
+	VIDEO_DEVICE_DEFINE(ov5640_##n, DEVICE_DT_INST_GET(n), NULL);
 
 DT_INST_FOREACH_STATUS_OKAY(OV5640_INIT)
diff --git a/drivers/video/ov7670.c b/drivers/video/ov7670.c
index 84107a8bac5..17fce01cd5a 100644
--- a/drivers/video/ov7670.c
+++ b/drivers/video/ov7670.c
@@ -9,8 +9,12 @@
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/drivers/i2c.h>
 #include <zephyr/drivers/video.h>
+#include <zephyr/drivers/video-controls.h>
 #include <zephyr/logging/log.h>
 
+#include "video_ctrls.h"
+#include "video_device.h"
+
 LOG_MODULE_REGISTER(video_ov7670, CONFIG_VIDEO_LOG_LEVEL);
 
 /* Initialization register structure */
@@ -29,7 +33,13 @@ struct ov7670_config {
 #endif
 };
 
+struct ov7670_ctrls {
+	struct video_ctrl hflip;
+	struct video_ctrl vflip;
+};
+
 struct ov7670_data {
+	struct ov7670_ctrls ctrls;
 	struct video_format fmt;
 };
 
@@ -181,6 +191,8 @@ const struct ov7670_resolution_cfg OV7670_RESOLUTION_VGA = {
 
 /* OV7670 definitions */
 #define OV7670_PROD_ID 0x76
+#define OV7670_MVFP_HFLIP 0x20
+#define OV7670_MVFP_VFLIP 0x10
 
 #define OV7670_VIDEO_FORMAT_CAP(width, height, format)                                             \
 	{                                                                                          \
@@ -204,11 +216,11 @@ static const struct video_format_cap fmts[] = {
  * Note that this table assumes the camera is fed a 6MHz XCLK signal
  */
 static const struct ov7670_reg ov7670_init_regtbl[] = {
-	{OV7670_MVFP, 0x20}, /* MVFP: Mirror/VFlip,Normal image */
+	{OV7670_MVFP, 0x00}, /* MVFP: Mirror/VFlip,Normal image */
 
 	/* configure the output timing */
-	/* PCLK does not toggle during horizontal blank, one PCLK, one pixel */
-	{OV7670_COM10, 0x20}, /* COM10 */
+	/* Free running PCLK, default VSYNC, HSYNC and PCLK */
+	{OV7670_COM10, 0x00}, /* COM10 */
 	{OV7670_COM12, 0x00}, /* COM12,No HREF when VSYNC is low */
 	/* Brightness Control, with signal -128 to +128, 0x00 is middle value */
 	{OV7670_BRIGHT, 0x2f},
@@ -253,7 +265,7 @@ static const struct ov7670_reg ov7670_init_regtbl[] = {
 
 	/* display , need retain */
 	{OV7670_COM15, 0xD0}, /* Common Control 15 */
-	{OV7670_TSLB, 0x0C},  /* Line Buffer Test Option */
+	{OV7670_TSLB, 0x04},  /* Reserved */
 	{OV7670_COM13, 0x80}, /* Common Control 13 */
 	{OV7670_MANU, 0x11},  /* Manual U Value */
 	{OV7670_MANV, 0xFF},  /* Manual V Value */
@@ -446,6 +458,22 @@ static int ov7670_get_fmt(const struct device *dev, enum video_endpoint_id ep,
 	return 0;
 }
 
+static int ov7670_init_controls(const struct device *dev)
+{
+	int ret;
+	struct ov7670_data *drv_data = dev->data;
+	struct ov7670_ctrls *ctrls = &drv_data->ctrls;
+
+	ret = video_init_ctrl(&ctrls->hflip, dev, VIDEO_CID_HFLIP,
+			      (struct video_ctrl_range){.min = 0, .max = 1, .step = 1, .def = 0});
+	if (ret) {
+		return ret;
+	}
+
+	return video_init_ctrl(&ctrls->vflip, dev, VIDEO_CID_VFLIP,
+			       (struct video_ctrl_range){.min = 0, .max = 1, .step = 1, .def = 0});
+}
+
 static int ov7670_init(const struct device *dev)
 {
 	const struct ov7670_config *config = dev->config;
@@ -544,13 +572,39 @@ static int ov7670_init(const struct device *dev)
 		}
 	}
 
+	/* Initialize controls */
+	return ov7670_init_controls(dev);
+}
+
+static int ov7670_set_stream(const struct device *dev, bool enable)
+{
 	return 0;
 }
 
+static int ov7670_set_ctrl(const struct device *dev, uint32_t id)
+{
+	const struct ov7670_config *config = dev->config;
+	struct ov7670_data *drv_data = dev->data;
+	struct ov7670_ctrls *ctrls = &drv_data->ctrls;
+
+	switch (id) {
+	case VIDEO_CID_HFLIP:
+		return i2c_reg_update_byte_dt(&config->bus, OV7670_MVFP, OV7670_MVFP_HFLIP,
+					      ctrls->hflip.val ? OV7670_MVFP_HFLIP : 0);
+	case VIDEO_CID_VFLIP:
+		return i2c_reg_update_byte_dt(&config->bus, OV7670_MVFP, OV7670_MVFP_VFLIP,
+					      ctrls->vflip.val ? OV7670_MVFP_VFLIP : 0);
+	default:
+		return -ENOTSUP;
+	}
+}
+
 static DEVICE_API(video, ov7670_api) = {
 	.set_format = ov7670_set_fmt,
 	.get_format = ov7670_get_fmt,
 	.get_caps = ov7670_get_caps,
+	.set_stream = ov7670_set_stream,
+	.set_ctrl = ov7670_set_ctrl,
 };
 
 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(reset_gpios)
@@ -572,6 +626,8 @@ static DEVICE_API(video, ov7670_api) = {
 	struct ov7670_data ov7670_data_##inst;                                                     \
                                                                                                    \
 	DEVICE_DT_INST_DEFINE(inst, ov7670_init, NULL, &ov7670_data_##inst, &ov7670_config_##inst, \
-			      POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY, &ov7670_api);
+			      POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY, &ov7670_api);               \
+                                                                                                   \
+	VIDEO_DEVICE_DEFINE(ov7670_##inst, DEVICE_DT_INST_GET(inst), NULL);
 
 DT_INST_FOREACH_STATUS_OKAY(OV7670_INIT)
diff --git a/drivers/video/ov7725.c b/drivers/video/ov7725.c
index efcd8ab14d9..9297d4a401d 100644
--- a/drivers/video/ov7725.c
+++ b/drivers/video/ov7725.c
@@ -14,6 +14,8 @@
 #include <zephyr/drivers/i2c.h>
 #include <zephyr/drivers/gpio.h>
 
+#include "video_device.h"
+
 LOG_MODULE_REGISTER(video_ov7725, CONFIG_VIDEO_LOG_LEVEL);
 
 #define OV7725_REVISION  0x7721U
@@ -517,12 +519,7 @@ static int ov7725_get_fmt(const struct device *dev,
 	return 0;
 }
 
-static int ov7725_stream_start(const struct device *dev)
-{
-	return 0;
-}
-
-static int ov7725_stream_stop(const struct device *dev)
+static int ov7725_set_stream(const struct device *dev, bool enable)
 {
 	return 0;
 }
@@ -552,8 +549,7 @@ static DEVICE_API(video, ov7725_driver_api) = {
 	.set_format = ov7725_set_fmt,
 	.get_format = ov7725_get_fmt,
 	.get_caps = ov7725_get_caps,
-	.stream_start = ov7725_stream_start,
-	.stream_stop = ov7725_stream_stop,
+	.set_stream = ov7725_set_stream,
 };
 
 static int ov7725_init(const struct device *dev)
@@ -645,3 +641,5 @@ DEVICE_DT_INST_DEFINE(0, &ov7725_init_0, NULL,
 		    &ov7725_data_0, &ov7725_cfg_0,
 		    POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY,
 		    &ov7725_driver_api);
+
+VIDEO_DEVICE_DEFINE(ov7725, DEVICE_DT_INST_GET(0), NULL);
diff --git a/drivers/video/video.ld b/drivers/video/video.ld
new file mode 100644
index 00000000000..935ee1ed302
--- /dev/null
+++ b/drivers/video/video.ld
@@ -0,0 +1,3 @@
+#include <zephyr/linker/iterable_sections.h>
+
+ITERABLE_SECTION_RAM(video_device, Z_LINK_ITERABLE_SUBALIGN)
diff --git a/drivers/video/video_ctrls.c b/drivers/video/video_ctrls.c
new file mode 100644
index 00000000000..25906f13c31
--- /dev/null
+++ b/drivers/video/video_ctrls.c
@@ -0,0 +1,514 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+
+#include <zephyr/drivers/video.h>
+#include <zephyr/drivers/video-controls.h>
+#include <zephyr/logging/log.h>
+
+#include "video_ctrls.h"
+#include "video_device.h"
+
+LOG_MODULE_REGISTER(video_ctrls, CONFIG_VIDEO_LOG_LEVEL);
+
+static inline const char *const *video_get_std_menu_ctrl(uint32_t id)
+{
+	static const char *const camera_power_line_frequency[] = {"Disabled", "50 Hz", "60 Hz",
+								  "Auto", NULL};
+	static const char *const camera_exposure_auto[] = {"Auto Mode", "Manual Mode",
+							   "Shutter Priority Mode",
+							   "Aperture Priority Mode", NULL};
+
+	switch (id) {
+	case VIDEO_CID_POWER_LINE_FREQUENCY:
+		return camera_power_line_frequency;
+	case VIDEO_CID_EXPOSURE_AUTO:
+		return camera_exposure_auto;
+	default:
+		return NULL;
+	}
+}
+
+static inline int check_range(enum video_ctrl_type type, struct video_ctrl_range range)
+{
+	switch (type) {
+	case VIDEO_CTRL_TYPE_BOOLEAN:
+		if (range.step != 1 || range.max > 1 || range.min < 0) {
+			return -ERANGE;
+		}
+		return 0;
+	case VIDEO_CTRL_TYPE_INTEGER:
+		if (range.step == 0 || range.min > range.max ||
+		    !IN_RANGE(range.def, range.min, range.max)) {
+			return -ERANGE;
+		}
+		return 0;
+	case VIDEO_CTRL_TYPE_INTEGER64:
+		if (range.step64 == 0 || range.min64 > range.max64 ||
+		    !IN_RANGE(range.def64, range.min64, range.max64)) {
+			return -ERANGE;
+		}
+		return 0;
+	case VIDEO_CTRL_TYPE_MENU:
+		if (!IN_RANGE(range.min, 0, range.max) ||
+		    !IN_RANGE(range.def, range.min, range.max)) {
+			return -ERANGE;
+		}
+		return 0;
+	default:
+		return 0;
+	}
+}
+
+static inline void set_type_flag(uint32_t id, enum video_ctrl_type *type, uint32_t *flags)
+{
+	*flags = 0;
+
+	switch (id) {
+	case VIDEO_CID_HFLIP:
+	case VIDEO_CID_VFLIP:
+		*type = VIDEO_CTRL_TYPE_BOOLEAN;
+		break;
+	case VIDEO_CID_POWER_LINE_FREQUENCY:
+	case VIDEO_CID_TEST_PATTERN:
+		*type = VIDEO_CTRL_TYPE_MENU;
+		break;
+	case VIDEO_CID_PIXEL_RATE:
+		*type = VIDEO_CTRL_TYPE_INTEGER64;
+		*flags |= VIDEO_CTRL_FLAG_READ_ONLY;
+		break;
+	default:
+		*type = VIDEO_CTRL_TYPE_INTEGER;
+		break;
+	}
+}
+
+int video_init_ctrl(struct video_ctrl *ctrl, const struct device *dev, uint32_t id,
+		    struct video_ctrl_range range)
+{
+	int ret;
+	uint32_t flags;
+	enum video_ctrl_type type;
+	struct video_ctrl *vc;
+	struct video_device *vdev = video_find_vdev(dev);
+
+	if (!vdev) {
+		return -EINVAL;
+	}
+
+	/* Sanity checks */
+	if (id < VIDEO_CID_BASE) {
+		return -EINVAL;
+	}
+
+	set_type_flag(id, &type, &flags);
+
+	ret = check_range(type, range);
+	if (ret) {
+		return ret;
+	}
+
+	ctrl->cluster_sz = 0;
+	ctrl->cluster = NULL;
+	ctrl->is_auto = false;
+	ctrl->has_volatiles = false;
+	ctrl->menu = NULL;
+	ctrl->vdev = vdev;
+	ctrl->id = id;
+	ctrl->type = type;
+	ctrl->flags = flags;
+	ctrl->range = range;
+
+	if (type == VIDEO_CTRL_TYPE_INTEGER64) {
+		ctrl->val64 = range.def64;
+	} else {
+		ctrl->val = range.def;
+	}
+
+	/* Insert in an ascending order of ctrl's id */
+	SYS_DLIST_FOR_EACH_CONTAINER(&vdev->ctrls, vc, node) {
+		if (vc->id > ctrl->id) {
+			sys_dlist_insert(&vc->node, &ctrl->node);
+			return 0;
+		}
+	}
+
+	sys_dlist_append(&vdev->ctrls, &ctrl->node);
+
+	return 0;
+}
+
+int video_init_menu_ctrl(struct video_ctrl *ctrl, const struct device *dev, uint32_t id,
+			 uint8_t def, const char *const menu[])
+{
+	int ret;
+	uint8_t sz = 0;
+	const char *const *_menu = menu ? menu : video_get_std_menu_ctrl(id);
+
+	if (!_menu) {
+		return -EINVAL;
+	}
+
+	while (_menu[sz]) {
+		sz++;
+	}
+
+	ret = video_init_ctrl(
+		ctrl, dev, id,
+		(struct video_ctrl_range){.min = 0, .max = sz - 1, .step = 1, .def = def});
+
+	if (ret) {
+		return ret;
+	}
+
+	ctrl->menu = _menu;
+
+	return 0;
+}
+
+/* By definition, the cluster is in manual mode if the master control value is 0 */
+static inline bool is_cluster_manual(const struct video_ctrl *master)
+{
+	return master->type == VIDEO_CTRL_TYPE_INTEGER64 ? master->val64 == 0 : master->val == 0;
+}
+
+void video_cluster_ctrl(struct video_ctrl *ctrls, uint8_t sz)
+{
+	bool has_volatiles = false;
+
+	__ASSERT(!sz && !ctrls, "The 1st control, i.e. the master, must not be NULL");
+
+	for (uint8_t i = 0; i < sz; i++) {
+		ctrls[i].cluster_sz = sz;
+		ctrls[i].cluster = ctrls;
+		if (ctrls[i].flags & VIDEO_CTRL_FLAG_VOLATILE) {
+			has_volatiles = true;
+		}
+	}
+
+	ctrls->has_volatiles = has_volatiles;
+}
+
+void video_auto_cluster_ctrl(struct video_ctrl *ctrls, uint8_t sz, bool set_volatile)
+{
+	video_cluster_ctrl(ctrls, sz);
+
+	__ASSERT(sz > 1, "Control auto cluster size must be > 1");
+	__ASSERT(!(set_volatile && !DEVICE_API_GET(video, ctrls->vdev->dev)->get_volatile_ctrl),
+		 "Volatile is set but no ops");
+
+	ctrls->is_auto = true;
+	ctrls->has_volatiles = set_volatile;
+	ctrls->flags |= VIDEO_CTRL_FLAG_UPDATE;
+
+	/* If the cluster is in automatic mode, mark all manual controls inactive and volatile */
+	for (uint8_t i = 1; i < sz; i++) {
+		if (!is_cluster_manual(ctrls)) {
+			ctrls[i].flags |= VIDEO_CTRL_FLAG_INACTIVE |
+					  (set_volatile ? VIDEO_CTRL_FLAG_VOLATILE : 0);
+		}
+	}
+}
+
+static int video_find_ctrl(const struct device *dev, uint32_t id, struct video_ctrl **ctrl)
+{
+	struct video_device *vdev = video_find_vdev(dev);
+
+	while (vdev) {
+		SYS_DLIST_FOR_EACH_CONTAINER(&vdev->ctrls, *ctrl, node) {
+			if ((*ctrl)->id == id) {
+				return 0;
+			}
+		}
+
+		vdev = video_find_vdev(vdev->src_dev);
+	}
+
+	return -ENOTSUP;
+}
+
+int video_get_ctrl(const struct device *dev, struct video_control *control)
+{
+	struct video_ctrl *ctrl = NULL;
+
+	int ret = video_find_ctrl(dev, control->id, &ctrl);
+
+	if (ret) {
+		return ret;
+	}
+
+	if (ctrl->flags & VIDEO_CTRL_FLAG_WRITE_ONLY) {
+		LOG_ERR("Control id 0x%x is write-only\n", control->id);
+		return -EACCES;
+	}
+
+	if (ctrl->flags & VIDEO_CTRL_FLAG_VOLATILE) {
+		if (DEVICE_API_GET(video, ctrl->vdev->dev)->get_volatile_ctrl == NULL) {
+			return -ENOSYS;
+		}
+
+		/* Call driver's get_volatile_ctrl */
+		ret = DEVICE_API_GET(video, ctrl->vdev->dev)
+			      ->get_volatile_ctrl(ctrl->vdev->dev,
+						  ctrl->cluster ? ctrl->cluster->id : ctrl->id);
+		if (ret) {
+			return ret;
+		}
+	}
+
+	/* Give the control's current value to user */
+	if (ctrl->type == VIDEO_CTRL_TYPE_INTEGER64) {
+		control->val64 = ctrl->val64;
+	} else {
+		control->val = ctrl->val;
+	}
+
+	return 0;
+}
+
+int video_set_ctrl(const struct device *dev, struct video_control *control)
+{
+	struct video_ctrl *ctrl = NULL;
+	int ret = video_find_ctrl(dev, control->id, &ctrl);
+	uint8_t i = 0;
+	int32_t val = 0;
+	int64_t val64 = 0;
+
+	if (ret) {
+		return ret;
+	}
+
+	if (ctrl->flags & VIDEO_CTRL_FLAG_READ_ONLY) {
+		LOG_ERR("Control id 0x%x is read-only\n", control->id);
+		return -EACCES;
+	}
+
+	if (ctrl->flags & VIDEO_CTRL_FLAG_INACTIVE) {
+		LOG_ERR("Control id 0x%x is inactive\n", control->id);
+		return -EACCES;
+	}
+
+	if (ctrl->type == VIDEO_CTRL_TYPE_INTEGER64
+		    ? !IN_RANGE(control->val64, ctrl->range.min64, ctrl->range.max64)
+		    : !IN_RANGE(control->val, ctrl->range.min, ctrl->range.max)) {
+		LOG_ERR("Control value is invalid\n");
+		return -EINVAL;
+	}
+
+	/* No new value */
+	if (ctrl->type == VIDEO_CTRL_TYPE_INTEGER64 ? ctrl->val64 == control->val64
+						    : ctrl->val == control->val) {
+		return 0;
+	}
+
+	/* Backup the control's value then set it to the new value */
+	if (ctrl->type == VIDEO_CTRL_TYPE_INTEGER64) {
+		val64 = ctrl->val64;
+		ctrl->val64 = control->val64;
+	} else {
+		val = ctrl->val;
+		ctrl->val = control->val;
+	}
+
+	/*
+	 * For auto-clusters having volatiles, before switching to manual mode, get the current
+	 * volatile values since those will become the initial manual values after this switch.
+	 */
+	if (ctrl == ctrl->cluster && ctrl->is_auto && ctrl->has_volatiles &&
+	    is_cluster_manual(ctrl)) {
+
+		if (DEVICE_API_GET(video, ctrl->vdev->dev)->get_volatile_ctrl == NULL) {
+			ret = -ENOSYS;
+			goto restore;
+		}
+
+		ret = DEVICE_API_GET(video, ctrl->vdev->dev)
+			      ->get_volatile_ctrl(ctrl->vdev->dev, ctrl->id);
+		if (ret) {
+			goto restore;
+		}
+	}
+
+	/* Call driver's set_ctrl */
+	if (DEVICE_API_GET(video, ctrl->vdev->dev)->set_ctrl) {
+		ret = DEVICE_API_GET(video, ctrl->vdev->dev)
+				->set_ctrl(ctrl->vdev->dev, ctrl->cluster ? ctrl->cluster->id : ctrl->id);
+		if (ret) {
+			goto restore;
+		}
+	}
+
+	/* Update the manual controls' flags of the cluster */
+	if (ctrl->cluster && ctrl->cluster->is_auto) {
+		for (i = 1; i < ctrl->cluster_sz; i++) {
+			if (!is_cluster_manual(ctrl->cluster)) {
+				/* Automatic mode: set the inactive and volatile flags of the manual
+				 * controls
+				 */
+				ctrl->cluster[i].flags |=
+					VIDEO_CTRL_FLAG_INACTIVE |
+					(ctrl->cluster->has_volatiles ? VIDEO_CTRL_FLAG_VOLATILE
+								      : 0);
+			} else {
+				/* Manual mode: clear the inactive and volatile flags of the manual
+				 * controls
+				 */
+				ctrl->cluster[i].flags &=
+					~(VIDEO_CTRL_FLAG_INACTIVE | VIDEO_CTRL_FLAG_VOLATILE);
+			}
+		}
+	}
+
+	return 0;
+
+restore:
+	/* Restore the old control's value */
+	if (ctrl->type == VIDEO_CTRL_TYPE_INTEGER64) {
+		ctrl->val64 = val64;
+	} else {
+		ctrl->val = val;
+	}
+
+	return ret;
+}
+
+static inline const char *video_get_ctrl_name(uint32_t id)
+{
+	switch (id) {
+	/* User controls */
+	case VIDEO_CID_BRIGHTNESS:
+		return "Brightness";
+	case VIDEO_CID_CONTRAST:
+		return "Contrast";
+	case VIDEO_CID_SATURATION:
+		return "Saturation";
+	case VIDEO_CID_HUE:
+		return "Hue";
+	case VIDEO_CID_EXPOSURE:
+		return "Exposure";
+	case VIDEO_CID_AUTOGAIN:
+		return "Gain, Automatic";
+	case VIDEO_CID_GAIN:
+		return "Gain";
+	case VIDEO_CID_ANALOGUE_GAIN:
+		return "Analogue Gain";
+	case VIDEO_CID_HFLIP:
+		return "Horizontal Flip";
+	case VIDEO_CID_VFLIP:
+		return "Vertical Flip";
+	case VIDEO_CID_POWER_LINE_FREQUENCY:
+		return "Power Line Frequency";
+
+	/* Camera controls */
+	case VIDEO_CID_ZOOM_ABSOLUTE:
+		return "Zoom, Absolute";
+
+	/* JPEG encoder controls */
+	case VIDEO_CID_JPEG_COMPRESSION_QUALITY:
+		return "Compression Quality";
+
+	/* Image processing controls */
+	case VIDEO_CID_PIXEL_RATE:
+		return "Pixel Rate";
+	case VIDEO_CID_TEST_PATTERN:
+		return "Test Pattern";
+	default:
+		return NULL;
+	}
+}
+
+int video_query_ctrl(const struct device *dev, struct video_ctrl_query *cq)
+{
+	int ret;
+	struct video_device *vdev;
+	struct video_ctrl *ctrl = NULL;
+
+	if (cq->id & VIDEO_CTRL_FLAG_NEXT_CTRL) {
+		vdev = video_find_vdev(dev);
+		cq->id &= ~VIDEO_CTRL_FLAG_NEXT_CTRL;
+		while (vdev) {
+			SYS_DLIST_FOR_EACH_CONTAINER(&vdev->ctrls, ctrl, node) {
+				if (ctrl->id > cq->id) {
+					goto fill_query;
+				}
+			}
+			vdev = video_find_vdev(vdev->src_dev);
+		}
+		return -ENOTSUP;
+	}
+
+	ret = video_find_ctrl(dev, cq->id, &ctrl);
+	if (ret) {
+		return ret;
+	}
+
+fill_query:
+	cq->id = ctrl->id;
+	cq->type = ctrl->type;
+	cq->flags = ctrl->flags;
+	cq->range = ctrl->range;
+	cq->menu = ctrl->menu;
+	cq->name = video_get_ctrl_name(cq->id);
+
+	return 0;
+}
+
+void video_print_ctrl(const struct device *const dev, const struct video_ctrl_query *const cq)
+{
+	uint8_t i = 0;
+	const char *type = NULL;
+	char typebuf[8];
+
+	__ASSERT(dev && cq, "Invalid arguments");
+
+	/* Get type of the control */
+	switch (cq->type) {
+	case VIDEO_CTRL_TYPE_BOOLEAN:
+		type = "bool";
+		break;
+	case VIDEO_CTRL_TYPE_INTEGER:
+		type = "int";
+		break;
+	case VIDEO_CTRL_TYPE_INTEGER64:
+		type = "int64";
+		break;
+	case VIDEO_CTRL_TYPE_MENU:
+		type = "menu";
+		break;
+	case VIDEO_CTRL_TYPE_STRING:
+		type = "string";
+		break;
+	default:
+		break;
+	}
+	snprintf(typebuf, sizeof(typebuf), "(%s)", type);
+
+	/* Get current value of the control */
+	struct video_control vc = {.id = cq->id};
+
+	video_get_ctrl(dev, &vc);
+
+	/* Print the control information */
+	if (cq->type == VIDEO_CTRL_TYPE_INTEGER64) {
+		LOG_INF("%32s 0x%08x %-8s (flags=0x%02x) : min=%lld max=%lld step=%lld "
+			"default=%lld value=%lld ",
+			cq->name, cq->id, typebuf, cq->flags, cq->range.min64, cq->range.max64,
+			cq->range.step64, cq->range.def64, vc.val64);
+	} else {
+		LOG_INF("%32s 0x%08x %-8s (flags=0x%02x) : min=%d max=%d step=%d default=%d "
+			"value=%d ",
+			cq->name, cq->id, typebuf, cq->flags, cq->range.min, cq->range.max,
+			cq->range.step, cq->range.def, vc.val);
+	}
+
+	if (cq->menu) {
+		while (cq->menu[i]) {
+			LOG_INF("%*s %u: %s", 32, "", i, cq->menu[i]);
+			i++;
+		}
+	}
+}
diff --git a/drivers/video/video_ctrls.h b/drivers/video/video_ctrls.h
new file mode 100644
index 00000000000..07c6c5575f3
--- /dev/null
+++ b/drivers/video/video_ctrls.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DRIVERS_VIDEO_VIDEO_CTRLS_H_
+#define ZEPHYR_INCLUDE_DRIVERS_VIDEO_VIDEO_CTRLS_H_
+
+#include <zephyr/device.h>
+#include <zephyr/sys/dlist.h>
+
+/** Control is read-only */
+#define VIDEO_CTRL_FLAG_READ_ONLY  BIT(0)
+/** Control is write-only */
+#define VIDEO_CTRL_FLAG_WRITE_ONLY BIT(1)
+/** Control that needs a freshly read as constanly updated by HW */
+#define VIDEO_CTRL_FLAG_VOLATILE   BIT(2)
+/** Control is inactive, e.g. manual controls of an autocluster in automatic mode */
+#define VIDEO_CTRL_FLAG_INACTIVE   BIT(3)
+/** Control that affects other controls, e.g. the master control of a cluster */
+#define VIDEO_CTRL_FLAG_UPDATE     BIT(4)
+
+enum video_ctrl_type {
+	/** Boolean type */
+	VIDEO_CTRL_TYPE_BOOLEAN = 1,
+	/** Integer type */
+	VIDEO_CTRL_TYPE_INTEGER = 2,
+	/** 64-bit integer type */
+	VIDEO_CTRL_TYPE_INTEGER64 = 3,
+	/** Menu type, standard or driver-defined menu */
+	VIDEO_CTRL_TYPE_MENU = 4,
+	/** String type */
+	VIDEO_CTRL_TYPE_STRING = 5,
+};
+
+struct video_device;
+
+/**
+ * @see video_control for the struct used in public API
+ */
+struct video_ctrl {
+	/* Fields should not touched by drivers, used only for the 1st control of a cluster */
+	struct video_ctrl *cluster;
+	uint8_t cluster_sz;
+	bool is_auto;
+	bool has_volatiles;
+
+	const struct video_device *vdev;
+	uint32_t id;
+	enum video_ctrl_type type;
+	unsigned long flags;
+	struct video_ctrl_range range;
+	union {
+		int32_t val;
+		int64_t val64;
+	};
+	const char *const *menu;
+	sys_dnode_t node;
+};
+
+int video_init_ctrl(struct video_ctrl *ctrl, const struct device *dev, uint32_t id,
+		    struct video_ctrl_range range);
+
+int video_init_menu_ctrl(struct video_ctrl *ctrl, const struct device *dev, uint32_t id,
+			 uint8_t def, const char *const menu[]);
+
+void video_cluster_ctrl(struct video_ctrl *ctrls, uint8_t sz);
+
+void video_auto_cluster_ctrl(struct video_ctrl *ctrls, uint8_t sz, bool set_volatile);
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_VIDEO_VIDEO_CTRLS_H_ */
diff --git a/drivers/video/video_device.c b/drivers/video/video_device.c
new file mode 100644
index 00000000000..a895fed42f1
--- /dev/null
+++ b/drivers/video/video_device.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "video_device.h"
+
+struct video_device *video_find_vdev(const struct device *dev)
+{
+	if (!dev) {
+		return NULL;
+	}
+
+	STRUCT_SECTION_FOREACH(video_device, vdev) {
+		if (vdev->dev == dev) {
+			return vdev;
+		}
+	}
+
+	return NULL;
+}
diff --git a/drivers/video/video_device.h b/drivers/video/video_device.h
new file mode 100644
index 00000000000..3ba2ee3486c
--- /dev/null
+++ b/drivers/video/video_device.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_VIDEO_VIDEO_DEVICE_H_
+#define ZEPHYR_INCLUDE_DRIVERS_VIDEO_VIDEO_DEVICE_H_
+
+#include <zephyr/device.h>
+#include <zephyr/sys/dlist.h>
+
+struct video_device {
+	const struct device *dev;
+	const struct device *src_dev;
+	sys_dlist_t ctrls;
+};
+
+#define VIDEO_DEVICE_DEFINE(name, device, source)                                                  \
+	static STRUCT_SECTION_ITERABLE(video_device, name) = {                                     \
+		.dev = device,                                                                     \
+		.src_dev = source,                                                                 \
+		.ctrls = SYS_DLIST_STATIC_INIT(&name.ctrls),                                       \
+	}
+
+struct video_device *video_find_vdev(const struct device *dev);
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_VIDEO_VIDEO_DEVICE_H_ */
diff --git a/drivers/video/video_emul_imager.c b/drivers/video/video_emul_imager.c
index 63ce00be8d7..8dffbba11f6 100644
--- a/drivers/video/video_emul_imager.c
+++ b/drivers/video/video_emul_imager.c
@@ -17,6 +17,9 @@
 #include <zephyr/drivers/i2c.h>
 #include <zephyr/logging/log.h>
 
+#include "video_ctrls.h"
+#include "video_device.h"
+
 LOG_MODULE_REGISTER(video_emul_imager, CONFIG_VIDEO_LOG_LEVEL);
 
 #define EMUL_IMAGER_REG_SENSOR_ID 0x0000
@@ -27,19 +30,21 @@ LOG_MODULE_REGISTER(video_emul_imager, CONFIG_VIDEO_LOG_LEVEL);
 #define EMUL_IMAGER_REG_TIMING1   0x0004
 #define EMUL_IMAGER_REG_TIMING2   0x0005
 #define EMUL_IMAGER_REG_TIMING3   0x0006
-#define EMUL_IMAGER_REG_EXPOSURE  0x0007
-#define EMUL_IMAGER_REG_GAIN      0x0008
-#define EMUL_IMAGER_REG_PATTERN   0x0009
+#define EMUL_IMAGER_REG_CUSTOM    0x0007
+#define EMUL_IMAGER_REG_FORMAT    0x000a
 #define EMUL_IMAGER_PATTERN_OFF   0x00
 #define EMUL_IMAGER_PATTERN_BARS1 0x01
 #define EMUL_IMAGER_PATTERN_BARS2 0x02
 
+/* Custom control that is just an I2C write for example and test purpose */
+#define EMUL_IMAGER_CID_CUSTOM (VIDEO_CID_PRIVATE_BASE + 0x01)
+
 /* Emulated register bank */
 uint8_t emul_imager_fake_regs[10];
 
 enum emul_imager_fmt_id {
-	RGB565_64x20,
-	YUYV_64x20,
+	RGB565_320x240,
+	YUYV_320x240,
 };
 
 struct emul_imager_reg {
@@ -53,7 +58,7 @@ struct emul_imager_mode {
 	 * This permits to deduplicate the list of registers in case some lare sections
 	 * are repeated across modes, such as the resolution for different FPS.
 	 */
-	const struct emul_imager_reg *regs[2];
+	const struct emul_imager_reg *regs[3];
 	/* More fields can be added according to the needs of the sensor driver */
 };
 
@@ -61,102 +66,101 @@ struct emul_imager_config {
 	struct i2c_dt_spec i2c;
 };
 
+struct emul_imager_ctrls {
+	struct video_ctrl custom;
+};
+
 struct emul_imager_data {
-	/* First field is a framebuffer for I/O emulation purpose */
-	uint8_t framebuffer[CONFIG_VIDEO_EMUL_IMAGER_FRAMEBUFFER_SIZE];
+	/* First field is a line buffer for I/O emulation purpose */
+	uint8_t framebuffer[320 * sizeof(uint16_t)];
 	/* Other fields are shared with real hardware drivers */
 	const struct emul_imager_mode *mode;
 	enum emul_imager_fmt_id fmt_id;
 	struct video_format fmt;
+	struct emul_imager_ctrls ctrls;
 };
 
-/* Initial parameters of the sensors common to all modes. */
+/* All the I2C registers sent on various scenario */
 static const struct emul_imager_reg emul_imager_init_regs[] = {
 	{EMUL_IMAGER_REG_CTRL, 0x00},
-	/* Example comment about REG_INIT1 */
 	{EMUL_IMAGER_REG_INIT1, 0x10},
 	{EMUL_IMAGER_REG_INIT2, 0x00},
+	/* Undocumented registers from the vendor */
+	{0x1200, 0x01},
+	{0x1204, 0x01},
+	{0x1205, 0x20},
+	{0x1209, 0x7f},
 	{0},
 };
-
-/* List of registers aggregated together in "modes" that can be applied
- * to set the timing parameters and other mode-dependent configuration.
- */
-
-static const struct emul_imager_reg emul_imager_rgb565_64x20[] = {
-	{EMUL_IMAGER_REG_TIMING1, 0x64},
-	{EMUL_IMAGER_REG_TIMING2, 0x20},
-	{0},
-};
-static const struct emul_imager_reg emul_imager_rgb565_64x20_15fps[] = {
-	{EMUL_IMAGER_REG_TIMING3, 15},
+static const struct emul_imager_reg emul_imager_rgb565[] = {
+	{EMUL_IMAGER_REG_FORMAT, 0x01},
 	{0},
 };
-static const struct emul_imager_reg emul_imager_rgb565_64x20_30fps[] = {
-	{EMUL_IMAGER_REG_TIMING3, 30},
+static const struct emul_imager_reg emul_imager_yuyv[] = {
+	{EMUL_IMAGER_REG_FORMAT, 0x02},
 	{0},
 };
-static const struct emul_imager_reg emul_imager_rgb565_64x20_60fps[] = {
-	{EMUL_IMAGER_REG_TIMING3, 60},
+static const struct emul_imager_reg emul_imager_320x240[] = {
+	{EMUL_IMAGER_REG_TIMING1, 0x32},
+	{EMUL_IMAGER_REG_TIMING2, 0x24},
 	{0},
 };
-struct emul_imager_mode emul_imager_rgb565_64x20_modes[] = {
-	{.fps = 15, .regs = {emul_imager_rgb565_64x20, emul_imager_rgb565_64x20_15fps}},
-	{.fps = 30, .regs = {emul_imager_rgb565_64x20, emul_imager_rgb565_64x20_30fps}},
-	{.fps = 60, .regs = {emul_imager_rgb565_64x20, emul_imager_rgb565_64x20_60fps}},
+static const struct emul_imager_reg emul_imager_15fps[] = {
+	{EMUL_IMAGER_REG_TIMING3, 15},
 	{0},
 };
-
-static const struct emul_imager_reg emul_imager_yuyv_64x20[] = {
-	{EMUL_IMAGER_REG_TIMING1, 0x64},
-	{EMUL_IMAGER_REG_TIMING2, 0x20},
+static const struct emul_imager_reg emul_imager_30fps[] = {
+	{EMUL_IMAGER_REG_TIMING3, 30},
 	{0},
 };
-static const struct emul_imager_reg emul_imager_yuyv_64x20_15fps[] = {
-	{EMUL_IMAGER_REG_TIMING3, 15},
+static const struct emul_imager_reg emul_imager_60fps[] = {
+	{EMUL_IMAGER_REG_TIMING3, 60},
 	{0},
 };
-static const struct emul_imager_reg emul_imager_yuyv_64x20_30fps[] = {
-	{EMUL_IMAGER_REG_TIMING3, 30},
+
+/* Description of "modes", that pick lists of registesr that will be all sentto the imager */
+struct emul_imager_mode emul_imager_rgb565_320x240_modes[] = {
+	{.fps = 15, .regs = {emul_imager_320x240, emul_imager_rgb565, emul_imager_15fps}},
+	{.fps = 30, .regs = {emul_imager_320x240, emul_imager_rgb565, emul_imager_30fps}},
+	{.fps = 60, .regs = {emul_imager_320x240, emul_imager_rgb565, emul_imager_60fps}},
 	{0},
 };
-struct emul_imager_mode emul_imager_yuyv_64x20_modes[] = {
-	{.fps = 15, .regs = {emul_imager_yuyv_64x20, emul_imager_yuyv_64x20_15fps}},
-	{.fps = 30, .regs = {emul_imager_yuyv_64x20, emul_imager_yuyv_64x20_30fps}},
+struct emul_imager_mode emul_imager_yuyv_320x240_modes[] = {
+	{.fps = 15, .regs = {emul_imager_320x240, emul_imager_yuyv, emul_imager_15fps}},
+	{.fps = 30, .regs = {emul_imager_320x240, emul_imager_yuyv, emul_imager_30fps}},
 	{0},
 };
 
-/* Summary of all the modes of all the frame formats, with the format ID as
- * index, matching fmts[].
- */
+/* Summary of all the modes of all the frame formats, with indexes matching those of fmts[]. */
 static const struct emul_imager_mode *emul_imager_modes[] = {
-	[RGB565_64x20] = emul_imager_rgb565_64x20_modes,
-	[YUYV_64x20] = emul_imager_yuyv_64x20_modes,
+	[RGB565_320x240] = emul_imager_rgb565_320x240_modes,
+	[YUYV_320x240] = emul_imager_yuyv_320x240_modes,
 };
 
 /* Video device capabilities where the supported resolutions and pixel formats are listed.
  * The format ID is used as index to fetch the matching mode from the list above.
  */
-#define EMUL_IMAGER_VIDEO_FORMAT_CAP(width, height, format)                                        \
+#define EMUL_IMAGER_VIDEO_FORMAT_CAP(format, width, height)                                        \
 	{                                                                                          \
+		/* For a real imager, the width and height would be macro parameters */            \
 		.pixelformat = (format),                                                           \
 		.width_min = (width),                                                              \
 		.width_max = (width),                                                              \
+		.width_step = 0,                                                                   \
 		.height_min = (height),                                                            \
 		.height_max = (height),                                                            \
-		.width_step = 0,                                                                   \
 		.height_step = 0,                                                                  \
 	}
 static const struct video_format_cap fmts[] = {
-	[RGB565_64x20] = EMUL_IMAGER_VIDEO_FORMAT_CAP(64, 20, VIDEO_PIX_FMT_RGB565),
-	[YUYV_64x20] = EMUL_IMAGER_VIDEO_FORMAT_CAP(64, 20, VIDEO_PIX_FMT_YUYV),
+	[RGB565_320x240] = EMUL_IMAGER_VIDEO_FORMAT_CAP(VIDEO_PIX_FMT_RGB565, 320, 240),
+	[YUYV_320x240] = EMUL_IMAGER_VIDEO_FORMAT_CAP(VIDEO_PIX_FMT_YUYV, 320, 240),
 	{0},
 };
 
 /* Emulated I2C register interface, to replace with actual I2C calls for real hardware */
 static int emul_imager_read_reg(const struct device *const dev, uint8_t reg_addr, uint8_t *value)
 {
-	LOG_DBG("%s placeholder for I2C read from 0x%02x", dev->name, reg_addr);
+	LOG_DBG("Placeholder for I2C read from 0x%02x", reg_addr);
 	switch (reg_addr) {
 	case EMUL_IMAGER_REG_SENSOR_ID:
 		*value = EMUL_IMAGER_SENSOR_ID;
@@ -167,21 +171,10 @@ static int emul_imager_read_reg(const struct device *const dev, uint8_t reg_addr
 	return 0;
 }
 
-/* Helper to read a full integer directly from a register */
-static int emul_imager_read_int(const struct device *const dev, uint8_t reg_addr, int *value)
-{
-	uint8_t val8;
-	int ret;
-
-	ret = emul_imager_read_reg(dev, reg_addr, &val8);
-	*value = val8;
-	return ret;
-}
-
 /* Some sensors will need reg8 or reg16 variants. */
 static int emul_imager_write_reg(const struct device *const dev, uint8_t reg_addr, uint8_t value)
 {
-	LOG_DBG("%s placeholder for I2C write 0x%08x to 0x%02x", dev->name, value, reg_addr);
+	LOG_DBG("Placeholder for I2C write 0x%08x to 0x%02x", value, reg_addr);
 	emul_imager_fake_regs[reg_addr] = value;
 	return 0;
 }
@@ -200,37 +193,11 @@ static int emul_imager_write_multi(const struct device *const dev,
 	return 0;
 }
 
-static int emul_imager_set_ctrl(const struct device *dev, unsigned int cid, void *value)
-{
-	switch (cid) {
-	case VIDEO_CID_EXPOSURE:
-		return emul_imager_write_reg(dev, EMUL_IMAGER_REG_EXPOSURE, (int)value);
-	case VIDEO_CID_GAIN:
-		return emul_imager_write_reg(dev, EMUL_IMAGER_REG_GAIN, (int)value);
-	case VIDEO_CID_TEST_PATTERN:
-		return emul_imager_write_reg(dev, EMUL_IMAGER_REG_PATTERN, (int)value);
-	default:
-		return -ENOTSUP;
-	}
-}
-
-static int emul_imager_get_ctrl(const struct device *dev, unsigned int cid, void *value)
+static int emul_imager_set_ctrl(const struct device *dev, uint32_t id)
 {
 	struct emul_imager_data *data = dev->data;
 
-	switch (cid) {
-	case VIDEO_CID_EXPOSURE:
-		return emul_imager_read_int(dev, EMUL_IMAGER_REG_EXPOSURE, value);
-	case VIDEO_CID_GAIN:
-		return emul_imager_read_int(dev, EMUL_IMAGER_REG_GAIN, value);
-	case VIDEO_CID_TEST_PATTERN:
-		return emul_imager_read_int(dev, EMUL_IMAGER_REG_PATTERN, value);
-	case VIDEO_CID_PIXEL_RATE:
-		*(int64_t *)value = (int64_t)data->fmt.width * data->fmt.pitch * data->mode->fps;
-		return 0;
-	default:
-		return -ENOTSUP;
-	}
+	return emul_imager_write_reg(dev, EMUL_IMAGER_REG_CUSTOM, data->ctrls.custom.val);
 }
 
 /* Customize this function according to your "struct emul_imager_mode". */
@@ -256,7 +223,7 @@ static int emul_imager_set_mode(const struct device *dev, const struct emul_imag
 	data->mode = mode;
 	return 0;
 err:
-	LOG_ERR("Could not apply %s mode %p (%u FPS)", dev->name, mode, mode->fps);
+	LOG_ERR("Could not apply mode %p (%u FPS)", mode, mode->fps);
 	return ret;
 }
 
@@ -315,48 +282,6 @@ static int emul_imager_enum_frmival(const struct device *dev, enum video_endpoin
 	return mode->fps == 0;
 }
 
-/* White, Yellow, Cyan, Green, Magenta, Red, Blue, Black */
-static const uint16_t pattern_8bars_yuv[8][3] = {
-	{0xFF, 0x7F, 0x7F}, {0xFF, 0x00, 0xFF}, {0xFF, 0xFF, 0x00}, {0x7F, 0x00, 0x00},
-	{0x00, 0xFF, 0xFF}, {0x00, 0x00, 0xFF}, {0x00, 0xFF, 0x00}, {0x00, 0x7F, 0x7F}};
-static const uint16_t pattern_8bars_rgb[8][3] = {
-	{0xFF, 0xFF, 0xFF}, {0xFF, 0xFF, 0x00}, {0x00, 0xFF, 0xFF}, {0x00, 0xFF, 0x00},
-	{0xFF, 0x00, 0xFF}, {0xFF, 0x00, 0x00}, {0x00, 0x00, 0xFF}, {0x00, 0x00, 0x00}};
-static void emul_imager_fill_framebuffer(const struct device *const dev, struct video_format *fmt)
-{
-	struct emul_imager_data *data = dev->data;
-	uint16_t *fb16 = (uint16_t *)data->framebuffer;
-	uint16_t r, g, b, y, uv;
-
-	/* Fill the first row of the emulated framebuffer */
-	switch (fmt->pixelformat) {
-	case VIDEO_PIX_FMT_YUYV:
-		for (size_t i = 0; i < fmt->width; i++) {
-			y = pattern_8bars_yuv[i * 8 / fmt->width][0];
-			uv = pattern_8bars_yuv[i * 8 / fmt->width][1 + i % 2];
-			fb16[i] = sys_cpu_to_be16(y << 8 | uv << 0);
-		}
-		break;
-	case VIDEO_PIX_FMT_RGB565:
-		for (size_t i = 0; i < fmt->width; i++) {
-			r = pattern_8bars_rgb[i * 8 / fmt->width][0] >> (8 - 5);
-			g = pattern_8bars_rgb[i * 8 / fmt->width][1] >> (8 - 6);
-			b = pattern_8bars_rgb[i * 8 / fmt->width][2] >> (8 - 5);
-			fb16[i] = sys_cpu_to_le16((r << 11) | (g << 6) | (b << 0));
-		}
-		break;
-	default:
-		LOG_WRN("Unsupported pixel format %x, supported: %x, %x", fmt->pixelformat,
-			VIDEO_PIX_FMT_YUYV, VIDEO_PIX_FMT_RGB565);
-		memset(fb16, 0, fmt->pitch);
-	}
-
-	/* Duplicate the first row over the whole frame */
-	for (size_t i = 1; i < fmt->height; i++) {
-		memcpy(data->framebuffer + fmt->pitch * i, data->framebuffer, fmt->pitch);
-	}
-}
-
 static int emul_imager_set_fmt(const struct device *const dev, enum video_endpoint_id ep,
 			       struct video_format *fmt)
 {
@@ -368,21 +293,13 @@ static int emul_imager_set_fmt(const struct device *const dev, enum video_endpoi
 		return -EINVAL;
 	}
 
-	if (fmt->pitch * fmt->height > CONFIG_VIDEO_EMUL_IMAGER_FRAMEBUFFER_SIZE) {
-		LOG_ERR("%s has %u bytes of memory, unable to support %x %ux%u (%u bytes)",
-			dev->name, CONFIG_VIDEO_EMUL_IMAGER_FRAMEBUFFER_SIZE, fmt->pixelformat,
-			fmt->width, fmt->height, fmt->pitch * fmt->height);
-		return -ENOMEM;
-	}
-
 	if (memcmp(&data->fmt, fmt, sizeof(data->fmt)) == 0) {
 		return 0;
 	}
 
 	ret = video_format_caps_index(fmts, fmt, &fmt_id);
 	if (ret < 0) {
-		LOG_ERR("Format %x %ux%u not found for %s", fmt->pixelformat, fmt->width,
-			fmt->height, dev->name);
+		LOG_ERR("Format %x %ux%u not found", fmt->pixelformat, fmt->width, fmt->height);
 		return ret;
 	}
 
@@ -391,8 +308,16 @@ static int emul_imager_set_fmt(const struct device *const dev, enum video_endpoi
 		return ret;
 	}
 
-	/* Change the image pattern on the framebuffer */
-	emul_imager_fill_framebuffer(dev, fmt);
+	/* For the purpose of simulation, fill the image line buffer with 50% gray, this data
+	 * will be collected by the video_emul_rx driver.
+	 */
+	if (fmt->pixelformat == VIDEO_PIX_FMT_RGB565) {
+		for (int i = 0; i < fmt->width; i++) {
+			((uint16_t *)data->framebuffer)[i] = sys_cpu_to_le16(0x7bef);
+		}
+	} else {
+		memset(data->framebuffer, 0x7f, fmt->pitch);
+	}
 
 	data->fmt_id = fmt_id;
 	data->fmt = *fmt;
@@ -423,29 +348,31 @@ static int emul_imager_get_caps(const struct device *dev, enum video_endpoint_id
 	return 0;
 }
 
-static int emul_imager_stream_start(const struct device *dev)
+static int emul_imager_set_stream(const struct device *dev, bool enable)
 {
-	return emul_imager_write_reg(dev, EMUL_IMAGER_REG_CTRL, 1);
-}
-
-static int emul_imager_stream_stop(const struct device *dev)
-{
-	return emul_imager_write_reg(dev, EMUL_IMAGER_REG_CTRL, 0);
+	return emul_imager_write_reg(dev, EMUL_IMAGER_REG_CTRL, enable ? 1 : 0);
 }
 
 static DEVICE_API(video, emul_imager_driver_api) = {
 	.set_ctrl = emul_imager_set_ctrl,
-	.get_ctrl = emul_imager_get_ctrl,
 	.set_frmival = emul_imager_set_frmival,
 	.get_frmival = emul_imager_get_frmival,
 	.enum_frmival = emul_imager_enum_frmival,
 	.set_format = emul_imager_set_fmt,
 	.get_format = emul_imager_get_fmt,
 	.get_caps = emul_imager_get_caps,
-	.stream_start = emul_imager_stream_start,
-	.stream_stop = emul_imager_stream_stop,
+	.set_stream = emul_imager_set_stream,
 };
 
+static int emul_imager_init_controls(const struct device *dev)
+{
+	struct emul_imager_data *drv_data = dev->data;
+
+	return video_init_ctrl(
+		&drv_data->ctrls.custom, dev, EMUL_IMAGER_CID_CUSTOM,
+		(struct video_ctrl_range){.min = 0, .max = 255, .step = 1, .def = 128});
+}
+
 int emul_imager_init(const struct device *dev)
 {
 	struct video_format fmt;
@@ -459,13 +386,13 @@ int emul_imager_init(const struct device *dev)
 
 	ret = emul_imager_read_reg(dev, EMUL_IMAGER_REG_SENSOR_ID, &sensor_id);
 	if (ret < 0 || sensor_id != EMUL_IMAGER_SENSOR_ID) {
-		LOG_ERR("Failed to get %s correct sensor ID (0x%x", dev->name, sensor_id);
+		LOG_ERR("Failed to get a correct sensor ID 0x%x",  sensor_id);
 		return ret;
 	}
 
 	ret = emul_imager_write_multi(dev, emul_imager_init_regs);
 	if (ret < 0) {
-		LOG_ERR("Could not set %s initial registers", dev->name);
+		LOG_ERR("Could not set initial registers");
 		return ret;
 	}
 
@@ -476,11 +403,12 @@ int emul_imager_init(const struct device *dev)
 
 	ret = emul_imager_set_fmt(dev, VIDEO_EP_OUT, &fmt);
 	if (ret < 0) {
-		LOG_ERR("Failed to set %s to default format %x %ux%u", dev->name, fmt.pixelformat,
-			fmt.width, fmt.height);
+		LOG_ERR("Failed to set to default format %x %ux%u",
+			fmt.pixelformat, fmt.width, fmt.height);
 	}
 
-	return 0;
+	/* Initialize controls */
+	return emul_imager_init_controls(dev);
 }
 
 #define EMUL_IMAGER_DEFINE(inst)                                                                   \
@@ -492,6 +420,8 @@ int emul_imager_init(const struct device *dev)
                                                                                                    \
 	DEVICE_DT_INST_DEFINE(inst, &emul_imager_init, NULL, &emul_imager_data_##inst,             \
 			      &emul_imager_cfg_##inst, POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY,    \
-			      &emul_imager_driver_api);
+			      &emul_imager_driver_api);                                            \
+                                                                                                   \
+	VIDEO_DEVICE_DEFINE(emul_imager_##inst, DEVICE_DT_INST_GET(inst), NULL);
 
 DT_INST_FOREACH_STATUS_OKAY(EMUL_IMAGER_DEFINE)
diff --git a/drivers/video/video_emul_rx.c b/drivers/video/video_emul_rx.c
index 415d969970c..7b7d1f580a7 100644
--- a/drivers/video/video_emul_rx.c
+++ b/drivers/video/video_emul_rx.c
@@ -15,6 +15,8 @@
 #include <zephyr/drivers/i2c.h>
 #include <zephyr/logging/log.h>
 
+#include "video_device.h"
+
 LOG_MODULE_REGISTER(video_emul_rx, CONFIG_VIDEO_LOG_LEVEL);
 
 struct emul_rx_config {
@@ -29,22 +31,6 @@ struct emul_rx_data {
 	struct k_fifo fifo_out;
 };
 
-static int emul_rx_set_ctrl(const struct device *dev, unsigned int cid, void *value)
-{
-	const struct emul_rx_config *cfg = dev->config;
-
-	/* Forward all controls to the source */
-	return video_set_ctrl(cfg->source_dev, cid, value);
-}
-
-static int emul_rx_get_ctrl(const struct device *dev, unsigned int cid, void *value)
-{
-	const struct emul_rx_config *cfg = dev->config;
-
-	/* Forward all controls to the source */
-	return video_get_ctrl(cfg->source_dev, cid, value);
-}
-
 static int emul_rx_set_frmival(const struct device *dev, enum video_endpoint_id ep,
 			       struct video_frmival *frmival)
 {
@@ -131,20 +117,12 @@ static int emul_rx_get_caps(const struct device *dev, enum video_endpoint_id ep,
 	return video_get_caps(cfg->source_dev, VIDEO_EP_OUT, caps);
 }
 
-static int emul_rx_stream_start(const struct device *dev)
-{
-	const struct emul_rx_config *cfg = dev->config;
-
-	/* A real hardware driver would first start its own peripheral */
-	return video_stream_start(cfg->source_dev);
-}
-
-static int emul_rx_stream_stop(const struct device *dev)
+static int emul_rx_set_stream(const struct device *dev, bool enable)
 {
 	const struct emul_rx_config *cfg = dev->config;
 
-	return video_stream_stop(cfg->source_dev);
-	/* A real hardware driver would then stop its own peripheral */
+	/* A real hardware driver would first start / stop its own peripheral */
+	return enable ? video_stream_start(cfg->source_dev) : video_stream_stop(cfg->source_dev);
 }
 
 static void emul_rx_worker(struct k_work *work)
@@ -164,10 +142,13 @@ static void emul_rx_worker(struct k_work *work)
 
 		LOG_DBG("Inserting %u bytes into buffer %p", vbuf->bytesused, vbuf->buffer);
 
-		/* Simulate the MIPI/DVP hardware transferring image data from the imager to the
-		 * video buffer memory using DMA. The vbuf->size is checked in emul_rx_enqueue().
+		/* Simulate the MIPI/DVP hardware transferring image data line-by-line from the
+		 * imager to the video buffer memory using DMA copying the data line-by-line over
+		 * the whole frame. vbuf->size is already checked in emul_rx_enqueue().
 		 */
-		memcpy(vbuf->buffer, cfg->source_dev->data, vbuf->bytesused);
+		for (size_t i = 0; i + fmt->pitch <= vbuf->bytesused; i += fmt->pitch) {
+			memcpy(vbuf->buffer + i, cfg->source_dev->data, fmt->pitch);
+		}
 
 		/* Once the buffer is completed, submit it to the video buffer */
 		k_fifo_put(&data->fifo_out, vbuf);
@@ -232,9 +213,6 @@ static int emul_rx_flush(const struct device *dev, enum video_endpoint_id ep, bo
 	if (cancel) {
 		struct video_buffer *vbuf;
 
-		/* First, stop the hardware processing */
-		emul_rx_stream_stop(dev);
-
 		/* Cancel the jobs that were not running */
 		k_work_cancel(&data->work);
 
@@ -254,16 +232,13 @@ static int emul_rx_flush(const struct device *dev, enum video_endpoint_id ep, bo
 }
 
 static DEVICE_API(video, emul_rx_driver_api) = {
-	.set_ctrl = emul_rx_set_ctrl,
-	.get_ctrl = emul_rx_get_ctrl,
 	.set_frmival = emul_rx_set_frmival,
 	.get_frmival = emul_rx_get_frmival,
 	.enum_frmival = emul_rx_enum_frmival,
 	.set_format = emul_rx_set_fmt,
 	.get_format = emul_rx_get_fmt,
 	.get_caps = emul_rx_get_caps,
-	.stream_start = emul_rx_stream_start,
-	.stream_stop = emul_rx_stream_stop,
+	.set_stream = emul_rx_set_stream,
 	.enqueue = emul_rx_enqueue,
 	.dequeue = emul_rx_dequeue,
 	.flush = emul_rx_flush,
@@ -294,10 +269,11 @@ int emul_rx_init(const struct device *dev)
 	return 0;
 }
 
+#define SOURCE_DEV(n) DEVICE_DT_GET(DT_NODE_REMOTE_DEVICE(DT_INST_ENDPOINT_BY_ID(n, 0, 0)))
+
 #define EMUL_RX_DEFINE(n)                                                                          \
 	static const struct emul_rx_config emul_rx_cfg_##n = {                                     \
-		.source_dev =                                                                      \
-			DEVICE_DT_GET(DT_NODE_REMOTE_DEVICE(DT_INST_ENDPOINT_BY_ID(n, 0, 0))),     \
+		.source_dev = SOURCE_DEV(n),                                                       \
 	};                                                                                         \
                                                                                                    \
 	static struct emul_rx_data emul_rx_data_##n = {                                            \
@@ -305,6 +281,8 @@ int emul_rx_init(const struct device *dev)
 	};                                                                                         \
                                                                                                    \
 	DEVICE_DT_INST_DEFINE(n, &emul_rx_init, NULL, &emul_rx_data_##n, &emul_rx_cfg_##n,         \
-			      POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY, &emul_rx_driver_api);
+			      POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY, &emul_rx_driver_api);       \
+                                                                                                   \
+	VIDEO_DEVICE_DEFINE(emul_rx_##n, DEVICE_DT_INST_GET(n), SOURCE_DEV(n));
 
 DT_INST_FOREACH_STATUS_OKAY(EMUL_RX_DEFINE)
diff --git a/drivers/video/video_esp32_dvp.c b/drivers/video/video_esp32_dvp.c
index b93f81dc5ce..07d60d85c96 100644
--- a/drivers/video/video_esp32_dvp.c
+++ b/drivers/video/video_esp32_dvp.c
@@ -21,6 +21,9 @@
 #include <hal/cam_ll.h>
 
 #include <zephyr/logging/log.h>
+
+#include "video_device.h"
+
 LOG_MODULE_REGISTER(video_esp32_lcd_cam, CONFIG_VIDEO_LOG_LEVEL);
 
 #define VIDEO_ESP32_DMA_BUFFER_MAX_SIZE 4095
@@ -133,7 +136,7 @@ void video_esp32_dma_rx_done(const struct device *dev, void *user_data, uint32_t
 	video_esp32_reload_dma(data);
 }
 
-static int video_esp32_stream_start(const struct device *dev)
+static int video_esp32_set_stream(const struct device *dev, bool enable)
 {
 	const struct video_esp32_config *cfg = dev->config;
 	struct video_esp32_data *data = dev->data;
@@ -143,6 +146,25 @@ static int video_esp32_stream_start(const struct device *dev)
 	uint32_t buffer_size = 0;
 	int error = 0;
 
+	if (!enable) {
+		LOG_DBG("Stop streaming");
+
+		if (video_stream_stop(cfg->source_dev)) {
+			return -EIO;
+		}
+
+		data->is_streaming = false;
+		error = dma_stop(cfg->dma_dev, cfg->rx_dma_channel);
+		if (error) {
+			LOG_ERR("Unable to stop DMA (%d)", error);
+			return error;
+		}
+
+		cam_hal_stop_streaming(&data->hal);
+
+		return 0;
+	}
+
 	if (data->is_streaming) {
 		return -EBUSY;
 	}
@@ -219,29 +241,6 @@ static int video_esp32_stream_start(const struct device *dev)
 	return 0;
 }
 
-static int video_esp32_stream_stop(const struct device *dev)
-{
-	const struct video_esp32_config *cfg = dev->config;
-	struct video_esp32_data *data = dev->data;
-	int ret = 0;
-
-	LOG_DBG("Stop streaming");
-
-	if (video_stream_stop(cfg->source_dev)) {
-		return -EIO;
-	}
-
-	data->is_streaming = false;
-	ret = dma_stop(cfg->dma_dev, cfg->rx_dma_channel);
-	if (ret) {
-		LOG_ERR("Unable to stop DMA (%d)", ret);
-		return ret;
-	}
-
-	cam_hal_stop_streaming(&data->hal);
-	return 0;
-}
-
 static int video_esp32_get_caps(const struct device *dev, enum video_endpoint_id ep,
 				struct video_caps *caps)
 {
@@ -329,18 +328,34 @@ static int video_esp32_dequeue(const struct device *dev, enum video_endpoint_id
 	return 0;
 }
 
-static int video_esp32_set_ctrl(const struct device *dev, unsigned int cid, void *value)
+static int video_esp32_flush(const struct device *dev, enum video_endpoint_id ep, bool cancel)
 {
-	const struct video_esp32_config *cfg = dev->config;
-
-	return video_set_ctrl(cfg->source_dev, cid, value);
-}
+	struct video_esp32_data *data = dev->data;
+	struct video_buffer *vbuf = NULL;
 
-static int video_esp32_get_ctrl(const struct device *dev, unsigned int cid, void *value)
-{
-	const struct video_esp32_config *cfg = dev->config;
+	if (cancel) {
+		if (data->is_streaming) {
+			video_esp32_set_stream(dev, false);
+		}
+		if (data->active_vbuf) {
+			k_fifo_put(&data->fifo_out, data->active_vbuf);
+			data->active_vbuf = NULL;
+		}
+		while ((vbuf = k_fifo_get(&data->fifo_in, K_NO_WAIT)) != NULL) {
+			k_fifo_put(&data->fifo_out, vbuf);
+#ifdef CONFIG_POLL
+			if (data->signal_out) {
+				k_poll_signal_raise(data->signal_out, VIDEO_BUF_ABORTED);
+			}
+#endif
+		}
+	} else {
+		while (!k_fifo_is_empty(&data->fifo_in)) {
+			k_sleep(K_MSEC(1));
+		}
+	}
 
-	return video_get_ctrl(cfg->source_dev, cid, value);
+	return 0;
 }
 
 #ifdef CONFIG_POLL
@@ -400,15 +415,12 @@ static DEVICE_API(video, esp32_driver_api) = {
 	/* mandatory callbacks */
 	.set_format = video_esp32_set_fmt,
 	.get_format = video_esp32_get_fmt,
-	.stream_start = video_esp32_stream_start,
-	.stream_stop = video_esp32_stream_stop,
+	.set_stream = video_esp32_set_stream,
 	.get_caps = video_esp32_get_caps,
 	/* optional callbacks */
 	.enqueue = video_esp32_enqueue,
 	.dequeue = video_esp32_dequeue,
-	.flush = NULL,
-	.set_ctrl = video_esp32_set_ctrl,
-	.get_ctrl = video_esp32_get_ctrl,
+	.flush = video_esp32_flush,
 #ifdef CONFIG_POLL
 	.set_signal = video_esp32_set_signal,
 #endif
@@ -416,9 +428,11 @@ static DEVICE_API(video, esp32_driver_api) = {
 
 PINCTRL_DT_INST_DEFINE(0);
 
+#define SOURCE_DEV(n) DEVICE_DT_GET(DT_INST_PHANDLE(n, source))
+
 static const struct video_esp32_config esp32_config = {
 	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
-	.source_dev = DEVICE_DT_GET(DT_INST_PHANDLE(0, source)),
+	.source_dev = SOURCE_DEV(0),
 	.dma_dev = ESP32_DT_INST_DMA_CTLR(0, rx),
 	.rx_dma_channel = DT_INST_DMAS_CELL_BY_NAME(0, rx, channel),
 	.data_width = DT_INST_PROP_OR(0, data_width, 8),
@@ -438,6 +452,8 @@ static struct video_esp32_data esp32_data = {0};
 DEVICE_DT_INST_DEFINE(0, video_esp32_init, NULL, &esp32_data, &esp32_config, POST_KERNEL,
 		      CONFIG_VIDEO_INIT_PRIORITY, &esp32_driver_api);
 
+VIDEO_DEVICE_DEFINE(esp32, DEVICE_DT_INST_GET(0), SOURCE_DEV(0));
+
 static int video_esp32_cam_init_master_clock(void)
 {
 	int ret = 0;
diff --git a/drivers/video/video_mcux_csi.c b/drivers/video/video_mcux_csi.c
index 101549969d1..4c9675ee2be 100644
--- a/drivers/video/video_mcux_csi.c
+++ b/drivers/video/video_mcux_csi.c
@@ -18,6 +18,8 @@
 #include <fsl_cache.h>
 #endif
 
+#include "video_device.h"
+
 struct video_mcux_csi_config {
 	CSI_Type *base;
 	const struct device *source_dev;
@@ -123,7 +125,7 @@ static inline void video_pix_fmt_convert(struct video_format *fmt, bool isGetFmt
 		break;
 	}
 
-	fmt->pitch = fmt->width * video_pix_fmt_bpp(fmt->pixelformat);
+	fmt->pitch = fmt->width * video_bits_per_pixel(fmt->pixelformat) / BITS_PER_BYTE;
 }
 #endif
 
@@ -132,7 +134,7 @@ static int video_mcux_csi_set_fmt(const struct device *dev, enum video_endpoint_
 {
 	const struct video_mcux_csi_config *config = dev->config;
 	struct video_mcux_csi_data *data = dev->data;
-	unsigned int bpp = video_pix_fmt_bpp(fmt->pixelformat);
+	unsigned int bpp = video_bits_per_pixel(fmt->pixelformat) / BITS_PER_BYTE;
 	status_t ret;
 	struct video_format format = *fmt;
 
@@ -194,37 +196,30 @@ static int video_mcux_csi_get_fmt(const struct device *dev, enum video_endpoint_
 	return -EIO;
 }
 
-static int video_mcux_csi_stream_start(const struct device *dev)
+static int video_mcux_csi_set_stream(const struct device *dev, bool enable)
 {
 	const struct video_mcux_csi_config *config = dev->config;
 	struct video_mcux_csi_data *data = dev->data;
 	status_t ret;
 
-	ret = CSI_TransferStart(config->base, &data->csi_handle);
-	if (ret != kStatus_Success) {
-		return -EIO;
-	}
-
-	if (config->source_dev && video_stream_start(config->source_dev)) {
-		return -EIO;
-	}
-
-	return 0;
-}
-
-static int video_mcux_csi_stream_stop(const struct device *dev)
-{
-	const struct video_mcux_csi_config *config = dev->config;
-	struct video_mcux_csi_data *data = dev->data;
-	status_t ret;
+	if (enable) {
+		ret = CSI_TransferStart(config->base, &data->csi_handle);
+		if (ret != kStatus_Success) {
+			return -EIO;
+		}
 
-	if (config->source_dev && video_stream_stop(config->source_dev)) {
-		return -EIO;
-	}
+		if (config->source_dev && video_stream_start(config->source_dev)) {
+			return -EIO;
+		}
+	} else {
+		if (config->source_dev && video_stream_stop(config->source_dev)) {
+			return -EIO;
+		}
 
-	ret = CSI_TransferStop(config->base, &data->csi_handle);
-	if (ret != kStatus_Success) {
-		return -EIO;
+		ret = CSI_TransferStop(config->base, &data->csi_handle);
+		if (ret != kStatus_Success) {
+			return -EIO;
+		}
 	}
 
 	return 0;
@@ -305,32 +300,6 @@ static int video_mcux_csi_dequeue(const struct device *dev, enum video_endpoint_
 	return 0;
 }
 
-static inline int video_mcux_csi_set_ctrl(const struct device *dev, unsigned int cid, void *value)
-{
-	const struct video_mcux_csi_config *config = dev->config;
-	int ret = -ENOTSUP;
-
-	/* Forward to source dev if any */
-	if (config->source_dev) {
-		ret = video_set_ctrl(config->source_dev, cid, value);
-	}
-
-	return ret;
-}
-
-static inline int video_mcux_csi_get_ctrl(const struct device *dev, unsigned int cid, void *value)
-{
-	const struct video_mcux_csi_config *config = dev->config;
-	int ret = -ENOTSUP;
-
-	/* Forward to source dev if any */
-	if (config->source_dev) {
-		ret = video_get_ctrl(config->source_dev, cid, value);
-	}
-
-	return ret;
-}
-
 static int video_mcux_csi_get_caps(const struct device *dev, enum video_endpoint_id ep,
 				   struct video_caps *caps)
 {
@@ -471,13 +440,10 @@ static int video_mcux_csi_enum_frmival(const struct device *dev, enum video_endp
 static DEVICE_API(video, video_mcux_csi_driver_api) = {
 	.set_format = video_mcux_csi_set_fmt,
 	.get_format = video_mcux_csi_get_fmt,
-	.stream_start = video_mcux_csi_stream_start,
-	.stream_stop = video_mcux_csi_stream_stop,
+	.set_stream = video_mcux_csi_set_stream,
 	.flush = video_mcux_csi_flush,
 	.enqueue = video_mcux_csi_enqueue,
 	.dequeue = video_mcux_csi_dequeue,
-	.set_ctrl = video_mcux_csi_set_ctrl,
-	.get_ctrl = video_mcux_csi_get_ctrl,
 	.get_caps = video_mcux_csi_get_caps,
 	.set_frmival = video_mcux_csi_set_frmival,
 	.get_frmival = video_mcux_csi_get_frmival,
@@ -490,9 +456,11 @@ static DEVICE_API(video, video_mcux_csi_driver_api) = {
 #if 1 /* Unique Instance */
 PINCTRL_DT_INST_DEFINE(0);
 
+#define SOURCE_DEV(n) DEVICE_DT_GET(DT_NODE_REMOTE_DEVICE(DT_INST_ENDPOINT_BY_ID(n, 0, 0)))
+
 static const struct video_mcux_csi_config video_mcux_csi_config_0 = {
 	.base = (CSI_Type *)DT_INST_REG_ADDR(0),
-	.source_dev = DEVICE_DT_GET(DT_NODE_REMOTE_DEVICE(DT_INST_ENDPOINT_BY_ID(0, 0, 0))),
+	.source_dev = SOURCE_DEV(0),
 	.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
 };
 
@@ -514,4 +482,7 @@ static int video_mcux_csi_init_0(const struct device *dev)
 DEVICE_DT_INST_DEFINE(0, &video_mcux_csi_init_0, NULL, &video_mcux_csi_data_0,
 		      &video_mcux_csi_config_0, POST_KERNEL, CONFIG_VIDEO_MCUX_CSI_INIT_PRIORITY,
 		      &video_mcux_csi_driver_api);
+
+VIDEO_DEVICE_DEFINE(csi, DEVICE_DT_INST_GET(0), SOURCE_DEV(0));
+
 #endif
diff --git a/drivers/video/video_mcux_mipi_csi2rx.c b/drivers/video/video_mcux_mipi_csi2rx.c
index efb96637c52..fb3cf5efa1e 100644
--- a/drivers/video/video_mcux_mipi_csi2rx.c
+++ b/drivers/video/video_mcux_mipi_csi2rx.c
@@ -15,6 +15,8 @@
 
 #include <fsl_mipi_csi2rx.h>
 
+#include "video_device.h"
+
 LOG_MODULE_REGISTER(video_mipi_csi2rx, CONFIG_VIDEO_LOG_LEVEL);
 
 #define MAX_SUPPORTED_PIXEL_RATE MHZ(96)
@@ -51,10 +53,10 @@ static int mipi_csi2rx_update_settings(const struct device *dev, enum video_endp
 	const struct mipi_csi2rx_config *config = dev->config;
 	struct mipi_csi2rx_data *drv_data = dev->data;
 	uint8_t bpp;
-	uint64_t sensor_pixel_rate;
 	uint32_t root_clk_rate, ui_clk_rate, sensor_byte_clk, best_match;
 	int ret, ind = 0;
 	struct video_format fmt;
+	struct video_control sensor_rate = {.id = VIDEO_CID_PIXEL_RATE, .val64 = -1};
 
 	ret = video_get_format(config->sensor_dev, ep, &fmt);
 	if (ret) {
@@ -62,19 +64,14 @@ static int mipi_csi2rx_update_settings(const struct device *dev, enum video_endp
 		return ret;
 	}
 
-	ret = video_get_ctrl(config->sensor_dev, VIDEO_CID_PIXEL_RATE, &sensor_pixel_rate);
-	if (ret) {
-		LOG_ERR("Can not get sensor_dev pixel rate");
-		return ret;
-	}
-
-	if (sensor_pixel_rate > MAX_SUPPORTED_PIXEL_RATE) {
-		LOG_ERR("Sensor pixel rate is not supported");
+	video_get_ctrl(config->sensor_dev, &sensor_rate);
+	if (!IN_RANGE(sensor_rate.val64, 0, MAX_SUPPORTED_PIXEL_RATE)) {
+		LOG_ERR("Sensor pixel rate is not supported %lld", sensor_rate.val64);
 		return -ENOTSUP;
 	}
 
-	bpp = video_pix_fmt_bpp(fmt.pixelformat) * 8;
-	sensor_byte_clk = sensor_pixel_rate * bpp / drv_data->csi2rxConfig.laneNum / 8;
+	bpp = video_bits_per_pixel(fmt.pixelformat);
+	sensor_byte_clk = sensor_rate.val64 * bpp / drv_data->csi2rxConfig.laneNum / BITS_PER_BYTE;
 
 	ret = clock_control_get_rate(drv_data->clock_dev, drv_data->clock_root, &root_clk_rate);
 	if (ret) {
@@ -94,10 +91,10 @@ static int mipi_csi2rx_update_settings(const struct device *dev, enum video_endp
 		return ret;
 	}
 
-	if (sensor_pixel_rate > ui_clk_rate) {
+	if (sensor_rate.val64 > ui_clk_rate) {
 		ret = clock_control_set_rate(
 			drv_data->clock_dev, drv_data->clock_ui,
-			(clock_control_subsys_rate_t)(uint32_t)sensor_pixel_rate);
+			(clock_control_subsys_rate_t)(uint32_t)sensor_rate.val64);
 		if (ret) {
 			return ret;
 		}
@@ -106,7 +103,7 @@ static int mipi_csi2rx_update_settings(const struct device *dev, enum video_endp
 	/* Find the supported sensor_pixel_rate closest to the desired one */
 	best_match = tHsSettleEscClk_configs[ind].pixel_rate;
 	for (uint8_t i = 0; i < ARRAY_SIZE(tHsSettleEscClk_configs); i++) {
-		if (ABS(tHsSettleEscClk_configs[i].pixel_rate, sensor_pixel_rate) <
+		if (ABS(tHsSettleEscClk_configs[i].pixel_rate, sensor_rate.val64) <
 		    ABS(tHsSettleEscClk_configs[i].pixel_rate, best_match)) {
 			best_match = tHsSettleEscClk_configs[i].pixel_rate;
 			ind = i;
@@ -146,33 +143,27 @@ static int mipi_csi2rx_get_fmt(const struct device *dev, enum video_endpoint_id
 	return 0;
 }
 
-static int mipi_csi2rx_stream_start(const struct device *dev)
+static int mipi_csi2rx_set_stream(const struct device *dev, bool enable)
 {
 	const struct mipi_csi2rx_config *config = dev->config;
-	struct mipi_csi2rx_data *drv_data = dev->data;
 
-	CSI2RX_Init((MIPI_CSI2RX_Type *)config->base, &drv_data->csi2rxConfig);
+	if (enable) {
+		struct mipi_csi2rx_data *drv_data = dev->data;
 
-	if (video_stream_start(config->sensor_dev)) {
-		return -EIO;
+		CSI2RX_Init((MIPI_CSI2RX_Type *)config->base, &drv_data->csi2rxConfig);
+		if (video_stream_start(config->sensor_dev)) {
+			return -EIO;
+		}
+	} else {
+		if (video_stream_stop(config->sensor_dev)) {
+			return -EIO;
+		}
+		CSI2RX_Deinit((MIPI_CSI2RX_Type *)config->base);
 	}
 
 	return 0;
 }
 
-static int mipi_csi2rx_stream_stop(const struct device *dev)
-{
-	const struct mipi_csi2rx_config *config = dev->config;
-
-	if (video_stream_stop(config->sensor_dev)) {
-		return -EIO;
-	}
-
-	CSI2RX_Deinit((MIPI_CSI2RX_Type *)config->base);
-
-	return 0;
-}
-
 static int mipi_csi2rx_get_caps(const struct device *dev, enum video_endpoint_id ep,
 				struct video_caps *caps)
 {
@@ -186,17 +177,6 @@ static int mipi_csi2rx_get_caps(const struct device *dev, enum video_endpoint_id
 	return video_get_caps(config->sensor_dev, ep, caps);
 }
 
-static inline int mipi_csi2rx_set_ctrl(const struct device *dev, unsigned int cid, void *value)
-{
-	const struct mipi_csi2rx_config *config = dev->config;
-
-	if (config->sensor_dev) {
-		return video_set_ctrl(config->sensor_dev, cid, value);
-	}
-
-	return -ENOTSUP;
-}
-
 static int mipi_csi2rx_set_frmival(const struct device *dev, enum video_endpoint_id ep,
 				   struct video_frmival *frmival)
 {
@@ -224,7 +204,7 @@ static int mipi_csi2rx_get_frmival(const struct device *dev, enum video_endpoint
 
 static uint64_t mipi_csi2rx_cal_frame_size(const struct video_format *fmt)
 {
-	return fmt->height * fmt->width * video_pix_fmt_bpp(fmt->pixelformat) * 8;
+	return fmt->height * fmt->width * video_bits_per_pixel(fmt->pixelformat);
 }
 
 static uint64_t mipi_csi2rx_estimate_pixel_rate(const struct video_frmival *cur_fmival,
@@ -245,21 +225,16 @@ static int mipi_csi2rx_enum_frmival(const struct device *dev, enum video_endpoin
 	const struct mipi_csi2rx_config *config = dev->config;
 	struct mipi_csi2rx_data *drv_data = dev->data;
 	int ret;
-	uint64_t cur_pixel_rate, est_pixel_rate;
+	uint64_t est_pixel_rate;
 	struct video_frmival cur_frmival;
 	struct video_format cur_fmt;
+	struct video_control sensor_rate = {.id = VIDEO_CID_PIXEL_RATE, .val64 = -1};
 
 	ret = video_enum_frmival(config->sensor_dev, ep, fie);
 	if (ret) {
 		return ret;
 	}
 
-	ret = video_get_ctrl(config->sensor_dev, VIDEO_CID_PIXEL_RATE, &cur_pixel_rate);
-	if (ret) {
-		LOG_ERR("Cannot get sensor_dev pixel rate");
-		return ret;
-	}
-
 	ret = video_get_frmival(config->sensor_dev, ep, &cur_frmival);
 	if (ret) {
 		LOG_ERR("Cannot get sensor_dev frame rate");
@@ -272,9 +247,14 @@ static int mipi_csi2rx_enum_frmival(const struct device *dev, enum video_endpoin
 		return ret;
 	}
 
+	ret = video_get_ctrl(config->sensor_dev, &sensor_rate);
+	if (ret) {
+		return ret;
+	}
+
 	if (fie->type == VIDEO_FRMIVAL_TYPE_DISCRETE) {
 		est_pixel_rate = mipi_csi2rx_estimate_pixel_rate(
-			&cur_frmival, &fie->discrete, &cur_fmt, fie->format, cur_pixel_rate,
+			&cur_frmival, &fie->discrete, &cur_fmt, fie->format, sensor_rate.val64,
 			drv_data->csi2rxConfig.laneNum);
 		if (est_pixel_rate > MAX_SUPPORTED_PIXEL_RATE) {
 			return -EINVAL;
@@ -283,7 +263,7 @@ static int mipi_csi2rx_enum_frmival(const struct device *dev, enum video_endpoin
 	} else {
 		/* Check the lane rate of the lower bound framerate */
 		est_pixel_rate = mipi_csi2rx_estimate_pixel_rate(
-			&cur_frmival, &fie->stepwise.min, &cur_fmt, fie->format, cur_pixel_rate,
+			&cur_frmival, &fie->stepwise.min, &cur_fmt, fie->format, sensor_rate.val64,
 			drv_data->csi2rxConfig.laneNum);
 		if (est_pixel_rate > MAX_SUPPORTED_PIXEL_RATE) {
 			return -EINVAL;
@@ -291,13 +271,13 @@ static int mipi_csi2rx_enum_frmival(const struct device *dev, enum video_endpoin
 
 		/* Check the lane rate of the upper bound framerate */
 		est_pixel_rate = mipi_csi2rx_estimate_pixel_rate(
-			&cur_frmival, &fie->stepwise.max, &cur_fmt, fie->format, cur_pixel_rate,
+			&cur_frmival, &fie->stepwise.max, &cur_fmt, fie->format, sensor_rate.val64,
 			drv_data->csi2rxConfig.laneNum);
 		if (est_pixel_rate > MAX_SUPPORTED_PIXEL_RATE) {
 			fie->stepwise.max.denominator =
 				(mipi_csi2rx_cal_frame_size(&cur_fmt) * MAX_SUPPORTED_PIXEL_RATE *
 				 cur_frmival.denominator) /
-				(mipi_csi2rx_cal_frame_size(fie->format) * cur_pixel_rate *
+				(mipi_csi2rx_cal_frame_size(fie->format) * sensor_rate.val64 *
 				 cur_frmival.numerator);
 			fie->stepwise.max.numerator = 1;
 		}
@@ -310,9 +290,7 @@ static DEVICE_API(video, mipi_csi2rx_driver_api) = {
 	.get_caps = mipi_csi2rx_get_caps,
 	.get_format = mipi_csi2rx_get_fmt,
 	.set_format = mipi_csi2rx_set_fmt,
-	.stream_start = mipi_csi2rx_stream_start,
-	.stream_stop = mipi_csi2rx_stream_stop,
-	.set_ctrl = mipi_csi2rx_set_ctrl,
+	.set_stream = mipi_csi2rx_set_stream,
 	.set_frmival = mipi_csi2rx_set_frmival,
 	.get_frmival = mipi_csi2rx_get_frmival,
 	.enum_frmival = mipi_csi2rx_enum_frmival,
@@ -342,6 +320,8 @@ static int mipi_csi2rx_init(const struct device *dev)
 	return mipi_csi2rx_update_settings(dev, VIDEO_EP_ALL);
 }
 
+#define SOURCE_DEV(n) DEVICE_DT_GET(DT_NODE_REMOTE_DEVICE(DT_INST_ENDPOINT_BY_ID(n, 1, 0)))
+
 #define MIPI_CSI2RX_INIT(n)                                                                        \
 	static struct mipi_csi2rx_data mipi_csi2rx_data_##n = {                                    \
 		.csi2rxConfig.laneNum = DT_PROP_LEN(DT_INST_ENDPOINT_BY_ID(n, 1, 0), data_lanes),  \
@@ -353,12 +333,13 @@ static int mipi_csi2rx_init(const struct device *dev)
                                                                                                    \
 	static const struct mipi_csi2rx_config mipi_csi2rx_config_##n = {                          \
 		.base = (MIPI_CSI2RX_Type *)DT_INST_REG_ADDR(n),                                   \
-		.sensor_dev =                                                                      \
-			DEVICE_DT_GET(DT_NODE_REMOTE_DEVICE(DT_INST_ENDPOINT_BY_ID(n, 1, 0))),     \
+		.sensor_dev = SOURCE_DEV(n),                                                       \
 	};                                                                                         \
                                                                                                    \
 	DEVICE_DT_INST_DEFINE(n, &mipi_csi2rx_init, NULL, &mipi_csi2rx_data_##n,                   \
 			      &mipi_csi2rx_config_##n, POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY,    \
-			      &mipi_csi2rx_driver_api);
+			      &mipi_csi2rx_driver_api);                                            \
+                                                                                                   \
+	VIDEO_DEVICE_DEFINE(mipi_csi2rx_##n, DEVICE_DT_INST_GET(n), SOURCE_DEV(n));
 
 DT_INST_FOREACH_STATUS_OKAY(MIPI_CSI2RX_INIT)
diff --git a/drivers/video/video_mcux_smartdma.c b/drivers/video/video_mcux_smartdma.c
index 7cf200b11cf..d9388b0951d 100644
--- a/drivers/video/video_mcux_smartdma.c
+++ b/drivers/video/video_mcux_smartdma.c
@@ -18,6 +18,8 @@
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(nxp_video_sdma);
 
+#include "video_device.h"
+
 struct nxp_video_sdma_config {
 	const struct device *dma_dev;
 	const struct device *sensor_dev;
@@ -93,13 +95,17 @@ static void nxp_video_sdma_callback(const struct device *dev, void *user_data,
 	data->buf_reload_flag = !data->buf_reload_flag;
 }
 
-static int nxp_video_sdma_stream_start(const struct device *dev)
+static int nxp_video_sdma_set_stream(const struct device *dev, bool enable)
 {
 	const struct nxp_video_sdma_config *config = dev->config;
 	struct nxp_video_sdma_data *data = dev->data;
 	struct dma_config sdma_config = {0};
 	int ret;
 
+	if (!enable) {
+		return dma_stop(config->dma_dev, 0);
+	}
+
 	/* Setup dma configuration for SmartDMA */
 	sdma_config.dma_slot = kSMARTDMA_CameraDiv16FrameQVGA;
 	sdma_config.dma_callback = nxp_video_sdma_callback;
@@ -142,14 +148,6 @@ static int nxp_video_sdma_stream_start(const struct device *dev)
 	return 0;
 }
 
-static int nxp_video_sdma_stream_stop(const struct device *dev)
-{
-	const struct nxp_video_sdma_config *config = dev->config;
-
-	/* Stop DMA engine */
-	return dma_stop(config->dma_dev, 0);
-}
-
 static int nxp_video_sdma_enqueue(const struct device *dev,
 				  enum video_endpoint_id ep,
 				  struct video_buffer *vbuf)
@@ -170,7 +168,7 @@ static int nxp_video_sdma_enqueue(const struct device *dev,
 	k_fifo_put(&data->fifo_in, vbuf);
 	if (data->stream_starved) {
 		/* Kick SmartDMA off */
-		nxp_video_sdma_stream_start(dev);
+		nxp_video_sdma_set_stream(dev, true);
 	}
 	return 0;
 }
@@ -361,31 +359,32 @@ static DEVICE_API(video, nxp_video_sdma_api) = {
 	.get_format = nxp_video_sdma_get_format,
 	.set_format = nxp_video_sdma_set_format,
 	.get_caps = nxp_video_sdma_get_caps,
-	.stream_start = nxp_video_sdma_stream_start,
-	.stream_stop = nxp_video_sdma_stream_stop,
+	.set_stream = nxp_video_sdma_set_stream,
 	.enqueue = nxp_video_sdma_enqueue,
 	.dequeue = nxp_video_sdma_dequeue,
 	.flush = nxp_video_sdma_flush
 };
 
-#define NXP_VIDEO_SDMA_INIT(inst)						\
-	PINCTRL_DT_INST_DEFINE(inst);						\
-	const struct nxp_video_sdma_config sdma_config_##inst = {		\
-		.dma_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)),			\
-		.sensor_dev = DEVICE_DT_GET(DT_INST_PHANDLE(inst, sensor)),	\
-		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),			\
-		.vsync_pin = DT_INST_PROP(inst, vsync_pin),			\
-		.hsync_pin = DT_INST_PROP(inst, hsync_pin),			\
-		.pclk_pin = DT_INST_PROP(inst, pclk_pin),			\
-	};									\
-	struct nxp_video_sdma_data sdma_data_##inst = {				\
-		.config = &sdma_config_##inst,					\
-	};									\
-										\
-	DEVICE_DT_INST_DEFINE(inst, nxp_video_sdma_init, NULL,			\
-				&sdma_data_##inst, &sdma_config_##inst,		\
-				POST_KERNEL,					\
-				CONFIG_KERNEL_INIT_PRIORITY_DEVICE,		\
-				&nxp_video_sdma_api);
+#define SOURCE_DEV(inst) DEVICE_DT_GET(DT_INST_PHANDLE(inst, sensor))
+
+#define NXP_VIDEO_SDMA_INIT(inst)                                                                  \
+	PINCTRL_DT_INST_DEFINE(inst);                                                              \
+	const struct nxp_video_sdma_config sdma_config_##inst = {                                  \
+		.dma_dev = DEVICE_DT_GET(DT_INST_PARENT(inst)),                                    \
+		.sensor_dev = SOURCE_DEV(n),                                                       \
+		.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(inst),                                    \
+		.vsync_pin = DT_INST_PROP(inst, vsync_pin),                                        \
+		.hsync_pin = DT_INST_PROP(inst, hsync_pin),                                        \
+		.pclk_pin = DT_INST_PROP(inst, pclk_pin),                                          \
+	};                                                                                         \
+	struct nxp_video_sdma_data sdma_data_##inst = {                                            \
+		.config = &sdma_config_##inst,                                                     \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_INST_DEFINE(inst, nxp_video_sdma_init, NULL, &sdma_data_##inst,                  \
+			      &sdma_config_##inst, POST_KERNEL,                                    \
+			      CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &nxp_video_sdma_api);            \
+                                                                                                   \
+	VIDEO_DEVICE_DEFINE(sdma_##inst, DEVICE_DT_INST_GET(inst), SOURCE_DEV(inst));
 
 DT_INST_FOREACH_STATUS_OKAY(NXP_VIDEO_SDMA_INIT)
diff --git a/drivers/video/video_stm32_dcmi.c b/drivers/video/video_stm32_dcmi.c
index 599d1a5d5a1..53afb33c0b5 100644
--- a/drivers/video/video_stm32_dcmi.c
+++ b/drivers/video/video_stm32_dcmi.c
@@ -20,9 +20,13 @@
 
 #include <stm32_ll_dma.h>
 
+#include "video_device.h"
+
 LOG_MODULE_REGISTER(video_stm32_dcmi, CONFIG_VIDEO_LOG_LEVEL);
 
-K_HEAP_DEFINE(video_stm32_buffer_pool, CONFIG_VIDEO_BUFFER_POOL_SZ_MAX);
+#if CONFIG_VIDEO_BUFFER_POOL_NUM_MAX < 2
+#error "The minimum required number of buffers for video_stm32 is 2"
+#endif
 
 typedef void (*irq_config_func_t)(const struct device *dev);
 
@@ -43,7 +47,7 @@ struct video_stm32_dcmi_data {
 	uint32_t height;
 	uint32_t width;
 	uint32_t pitch;
-	uint8_t *buffer;
+	struct video_buffer *vbuf;
 };
 
 struct video_stm32_dcmi_config {
@@ -75,7 +79,7 @@ void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
 	}
 
 	vbuf->timestamp = k_uptime_get_32();
-	memcpy(vbuf->buffer, dev_data->buffer, vbuf->bytesused);
+	memcpy(vbuf->buffer, dev_data->vbuf->buffer, vbuf->bytesused);
 
 	k_fifo_put(&dev_data->fifo_out, vbuf);
 
@@ -198,12 +202,16 @@ static int video_stm32_dcmi_set_fmt(const struct device *dev,
 {
 	const struct video_stm32_dcmi_config *config = dev->config;
 	struct video_stm32_dcmi_data *data = dev->data;
-	unsigned int bpp = video_pix_fmt_bpp(fmt->pixelformat);
+	unsigned int bpp = video_bits_per_pixel(fmt->pixelformat) / BITS_PER_BYTE;
 
 	if (bpp == 0 || (ep != VIDEO_EP_OUT && ep != VIDEO_EP_ALL)) {
 		return -EINVAL;
 	}
 
+	if ((fmt->pitch * fmt->height) > CONFIG_VIDEO_BUFFER_POOL_SZ_MAX) {
+		return -EINVAL;
+	}
+
 	data->pixel_format = fmt->pixelformat;
 	data->pitch = fmt->pitch;
 	data->height = fmt->height;
@@ -240,48 +248,44 @@ static int video_stm32_dcmi_get_fmt(const struct device *dev,
 	return 0;
 }
 
-static int video_stm32_dcmi_stream_start(const struct device *dev)
+static int video_stm32_dcmi_set_stream(const struct device *dev, bool enable)
 {
+	int err;
 	struct video_stm32_dcmi_data *data = dev->data;
 	const struct video_stm32_dcmi_config *config = dev->config;
-	size_t buffer_size = data->pitch * data->height;
 
-	data->buffer = k_heap_alloc(&video_stm32_buffer_pool, buffer_size, K_NO_WAIT);
-	if (data->buffer == NULL) {
-		LOG_ERR("Failed to allocate DCMI buffer for image. Size %d bytes", buffer_size);
-		return -ENOMEM;
-	}
+	if (!enable) {
+		if (video_stream_stop(config->sensor_dev)) {
+			return -EIO;
+		}
 
-	int err = HAL_DCMI_Start_DMA(&data->hdcmi, DCMI_MODE_CONTINUOUS,
-			(uint32_t)data->buffer, buffer_size / 4);
-	if (err != HAL_OK) {
-		LOG_ERR("Failed to start DCMI DMA");
-		return -EIO;
-	}
+		err = HAL_DCMI_Stop(&data->hdcmi);
+		if (err != HAL_OK) {
+			LOG_ERR("Failed to stop DCMI");
+			return -EIO;
+		}
 
-	if (video_stream_start(config->sensor_dev)) {
-		return -EIO;
+		/* Release the video buffer allocated when start streaming */
+		k_fifo_put(&data->fifo_in, data->vbuf);
+
+		return 0;
 	}
 
-	return 0;
-}
+	data->vbuf = k_fifo_get(&data->fifo_in, K_NO_WAIT);
 
-static int video_stm32_dcmi_stream_stop(const struct device *dev)
-{
-	struct video_stm32_dcmi_data *data = dev->data;
-	const struct video_stm32_dcmi_config *config = dev->config;
-	int err;
+	if (data->vbuf == NULL) {
+		LOG_ERR("Failed to dequeue a DCMI buffer.");
+		return -ENOMEM;
+	}
 
-	if (video_stream_stop(config->sensor_dev)) {
+	err = HAL_DCMI_Start_DMA(&data->hdcmi, DCMI_MODE_CONTINUOUS,
+			(uint32_t)data->vbuf->buffer, data->vbuf->bytesused / 4);
+	if (err != HAL_OK) {
+		LOG_ERR("Failed to start DCMI DMA");
 		return -EIO;
 	}
 
-	/* Release the buffer allocated in stream_start */
-	k_heap_free(&video_stm32_buffer_pool, data->buffer);
-
-	err = HAL_DCMI_Stop(&data->hdcmi);
-	if (err != HAL_OK) {
-		LOG_ERR("Failed to stop DCMI");
+	if (video_stream_start(config->sensor_dev)) {
 		return -EIO;
 	}
 
@@ -350,38 +354,13 @@ static int video_stm32_dcmi_get_caps(const struct device *dev,
 	return ret;
 }
 
-static inline int video_stm32_dcmi_set_ctrl(const struct device *dev, unsigned int cid, void *value)
-{
-	const struct video_stm32_dcmi_config *config = dev->config;
-	int ret;
-
-	/* Forward to source dev if any */
-	ret = video_set_ctrl(config->sensor_dev, cid, value);
-
-	return ret;
-}
-
-static inline int video_stm32_dcmi_get_ctrl(const struct device *dev, unsigned int cid, void *value)
-{
-	const struct video_stm32_dcmi_config *config = dev->config;
-	int ret;
-
-	/* Forward to source dev if any */
-	ret = video_get_ctrl(config->sensor_dev, cid, value);
-
-	return ret;
-}
-
 static DEVICE_API(video, video_stm32_dcmi_driver_api) = {
 	.set_format = video_stm32_dcmi_set_fmt,
 	.get_format = video_stm32_dcmi_get_fmt,
-	.stream_start = video_stm32_dcmi_stream_start,
-	.stream_stop = video_stm32_dcmi_stream_stop,
+	.set_stream = video_stm32_dcmi_set_stream,
 	.enqueue = video_stm32_dcmi_enqueue,
 	.dequeue = video_stm32_dcmi_dequeue,
 	.get_caps = video_stm32_dcmi_get_caps,
-	.set_ctrl = video_stm32_dcmi_set_ctrl,
-	.get_ctrl = video_stm32_dcmi_get_ctrl,
 };
 
 static void video_stm32_dcmi_irq_config_func(const struct device *dev)
@@ -457,6 +436,8 @@ static struct video_stm32_dcmi_data video_stm32_dcmi_data_0 = {
 	},
 };
 
+#define SOURCE_DEV(n) DEVICE_DT_GET(DT_INST_PHANDLE(n, sensor))
+
 static const struct video_stm32_dcmi_config video_stm32_dcmi_config_0 = {
 	.pclken = {
 		.enr = DT_INST_CLOCKS_CELL(0, bits),
@@ -464,7 +445,7 @@ static const struct video_stm32_dcmi_config video_stm32_dcmi_config_0 = {
 	},
 	.irq_config = video_stm32_dcmi_irq_config_func,
 	.pctrl = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
-	.sensor_dev = DEVICE_DT_GET(DT_INST_PHANDLE(0, sensor)),
+	.sensor_dev = SOURCE_DEV(0),
 	DCMI_DMA_CHANNEL(0, PERIPHERAL, MEMORY)
 };
 
@@ -520,3 +501,5 @@ DEVICE_DT_INST_DEFINE(0, &video_stm32_dcmi_init,
 		    &video_stm32_dcmi_config_0,
 		    POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY,
 		    &video_stm32_dcmi_driver_api);
+
+VIDEO_DEVICE_DEFINE(dcmi, DEVICE_DT_INST_GET(0), SOURCE_DEV(0));
diff --git a/drivers/video/video_sw_generator.c b/drivers/video/video_sw_generator.c
index c786d9c26b5..ed8ade5270c 100644
--- a/drivers/video/video_sw_generator.c
+++ b/drivers/video/video_sw_generator.c
@@ -11,6 +11,9 @@
 #include <zephyr/drivers/video-controls.h>
 #include <zephyr/logging/log.h>
 
+#include "video_ctrls.h"
+#include "video_device.h"
+
 LOG_MODULE_REGISTER(video_sw_generator, CONFIG_VIDEO_LOG_LEVEL);
 
 #define VIDEO_PATTERN_COLOR_BAR 0
@@ -24,16 +27,19 @@ LOG_MODULE_REGISTER(video_sw_generator, CONFIG_VIDEO_LOG_LEVEL);
  */
 #define MAX_FRAME_RATE          60
 
+struct sw_ctrls {
+	struct video_ctrl hflip;
+};
+
 struct video_sw_generator_data {
 	const struct device *dev;
+	struct sw_ctrls ctrls;
 	struct video_format fmt;
 	struct k_fifo fifo_in;
 	struct k_fifo fifo_out;
 	struct k_work_delayable buf_work;
 	struct k_work_sync work_sync;
 	int pattern;
-	bool ctrl_hflip;
-	bool ctrl_vflip;
 	struct k_poll_signal *signal;
 	uint32_t frame_rate;
 };
@@ -99,20 +105,15 @@ static int video_sw_generator_get_fmt(const struct device *dev, enum video_endpo
 	return 0;
 }
 
-static int video_sw_generator_stream_start(const struct device *dev)
+static int video_sw_generator_set_stream(const struct device *dev, bool enable)
 {
 	struct video_sw_generator_data *data = dev->data;
 
-	k_work_schedule(&data->buf_work, K_MSEC(1000 / data->frame_rate));
-
-	return 0;
-}
-
-static int video_sw_generator_stream_stop(const struct device *dev)
-{
-	struct video_sw_generator_data *data = dev->data;
-
-	k_work_cancel_delayable_sync(&data->buf_work, &data->work_sync);
+	if (enable) {
+		k_work_schedule(&data->buf_work, K_MSEC(1000 / data->frame_rate));
+	} else {
+		k_work_cancel_delayable_sync(&data->buf_work, &data->work_sync);
+	}
 
 	return 0;
 }
@@ -130,7 +131,7 @@ static void __fill_buffer_colorbar(struct video_sw_generator_data *data, struct
 
 	for (h = 0; h < data->fmt.height; h++) {
 		for (w = 0; w < data->fmt.width; w++) {
-			int color_idx = data->ctrl_vflip ? 7 - w / bw : w / bw;
+			int color_idx = data->ctrls.hflip.val ? 7 - w / bw : w / bw;
 			if (data->fmt.pixelformat == VIDEO_PIX_FMT_RGB565) {
 				uint16_t *pixel = (uint16_t *)&vbuf->buffer[i];
 				*pixel = rgb565_colorbar_value[color_idx];
@@ -260,22 +261,6 @@ static int video_sw_generator_set_signal(const struct device *dev, enum video_en
 }
 #endif
 
-static inline int video_sw_generator_set_ctrl(const struct device *dev, unsigned int cid,
-					      void *value)
-{
-	struct video_sw_generator_data *data = dev->data;
-
-	switch (cid) {
-	case VIDEO_CID_VFLIP:
-		data->ctrl_vflip = (bool)value;
-		break;
-	default:
-		return -ENOTSUP;
-	}
-
-	return 0;
-}
-
 static int video_sw_generator_set_frmival(const struct device *dev, enum video_endpoint_id ep,
 					  struct video_frmival *frmival)
 {
@@ -340,13 +325,11 @@ static int video_sw_generator_enum_frmival(const struct device *dev, enum video_
 static DEVICE_API(video, video_sw_generator_driver_api) = {
 	.set_format = video_sw_generator_set_fmt,
 	.get_format = video_sw_generator_get_fmt,
-	.stream_start = video_sw_generator_stream_start,
-	.stream_stop = video_sw_generator_stream_stop,
+	.set_stream = video_sw_generator_set_stream,
 	.flush = video_sw_generator_flush,
 	.enqueue = video_sw_generator_enqueue,
 	.dequeue = video_sw_generator_dequeue,
 	.get_caps = video_sw_generator_get_caps,
-	.set_ctrl = video_sw_generator_set_ctrl,
 	.set_frmival = video_sw_generator_set_frmival,
 	.get_frmival = video_sw_generator_get_frmival,
 	.enum_frmival = video_sw_generator_enum_frmival,
@@ -363,6 +346,14 @@ static struct video_sw_generator_data video_sw_generator_data_0 = {
 	.frame_rate = DEFAULT_FRAME_RATE,
 };
 
+static int video_sw_generator_init_controls(const struct device *dev)
+{
+	struct video_sw_generator_data *data = dev->data;
+
+	return video_init_ctrl(&data->ctrls.hflip, dev, VIDEO_CID_HFLIP,
+			       (struct video_ctrl_range){.min = 0, .max = 1, .step = 1, .def = 0});
+}
+
 static int video_sw_generator_init(const struct device *dev)
 {
 	struct video_sw_generator_data *data = dev->data;
@@ -372,9 +363,11 @@ static int video_sw_generator_init(const struct device *dev)
 	k_fifo_init(&data->fifo_out);
 	k_work_init_delayable(&data->buf_work, __buffer_work);
 
-	return 0;
+	return video_sw_generator_init_controls(dev);
 }
 
 DEVICE_DEFINE(video_sw_generator, "VIDEO_SW_GENERATOR", &video_sw_generator_init, NULL,
 	      &video_sw_generator_data_0, NULL, POST_KERNEL, CONFIG_VIDEO_INIT_PRIORITY,
 	      &video_sw_generator_driver_api);
+
+VIDEO_DEVICE_DEFINE(video_sw_generator, DEVICE_GET(video_sw_generator), NULL);
diff --git a/drivers/watchdog/CMakeLists.txt b/drivers/watchdog/CMakeLists.txt
index e2ebb95cc76..2c5140eea9a 100644
--- a/drivers/watchdog/CMakeLists.txt
+++ b/drivers/watchdog/CMakeLists.txt
@@ -17,10 +17,12 @@ zephyr_library_sources_ifdef(CONFIG_WDT_CC13XX_CC26XX wdt_cc13xx_cc26xx.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_ESP32 wdt_esp32.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_XT_ESP32 xt_wdt_esp32.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_GECKO wdt_gecko.c)
+zephyr_library_sources_ifdef(CONFIG_WDT_ITE_IT51XXX wdt_ite_it51xxx.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_ITE_IT8XXX2 wdt_ite_it8xxx2.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_LITEX wdt_litex.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_MAX32 wdt_max32.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_MCUX_IMX_WDOG wdt_mcux_imx_wdog.c)
+zephyr_library_sources_ifdef(CONFIG_WDT_MCUX_RTWDOG wdt_mcux_rtwdog.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_MCUX_WDOG wdt_mcux_wdog.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_MCUX_WDOG32 wdt_mcux_wdog32.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_MCUX_WWDT wdt_mcux_wwdt.c)
@@ -30,9 +32,12 @@ zephyr_library_sources_ifdef(CONFIG_WDT_NPM2100 wdt_npm2100.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_NPM6001 wdt_npm6001.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_NRFX wdt_nrfx.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_RPI_PICO wdt_rpi_pico.c)
+zephyr_library_sources_ifdef(CONFIG_WDT_RTS5912 wdt_rts5912.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_SAM wdt_sam.c)
+zephyr_library_sources_ifdef(CONFIG_WDT_SAM4L wdt_sam4l.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_SAM0 wdt_sam0.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_SIFIVE wdt_sifive.c)
+zephyr_library_sources_ifdef(CONFIG_WDT_SILABS_SIWX91X wdt_silabs_siwx91x.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_TCO wdt_tco.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_XEC wdt_mchp_xec.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_COUNTER wdt_counter.c)
@@ -52,5 +57,6 @@ zephyr_library_sources_ifdef(CONFIG_WDT_INTEL_ADSP wdt_intel_adsp.c wdt_dw_commo
 zephyr_library_sources_ifdef(CONFIG_WDT_ANDES_ATCWDT200 wdt_andes_atcwdt200.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_NXP_FS26 wdt_nxp_fs26.c)
 zephyr_library_sources_ifdef(CONFIG_WDT_SHELL wdt_shell.c)
+zephyr_library_sources_ifdef(CONFIG_WDT_RENESAS_RA wdt_renesas_ra.c)
 
 zephyr_library_sources_ifdef(CONFIG_USERSPACE wdt_handlers.c)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 38824f2f353..6bb30ff61b4 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -69,9 +69,11 @@ source "drivers/watchdog/Kconfig.stm32"
 
 source "drivers/watchdog/Kconfig.cmsdk_apb"
 
+source "drivers/watchdog/Kconfig.esp32"
+
 source "drivers/watchdog/Kconfig.sam"
 
-source "drivers/watchdog/Kconfig.esp32"
+source "drivers/watchdog/Kconfig.sam4l"
 
 source "drivers/watchdog/Kconfig.sam0"
 
@@ -85,6 +87,8 @@ source "drivers/watchdog/Kconfig.xec"
 
 source "drivers/watchdog/Kconfig.gecko"
 
+source "drivers/watchdog/Kconfig.siwx91x"
+
 source "drivers/watchdog/Kconfig.sifive"
 
 source "drivers/watchdog/Kconfig.npcx"
@@ -93,6 +97,8 @@ source "drivers/watchdog/Kconfig.cc32xx"
 
 source "drivers/watchdog/Kconfig.cc13xx_cc26xx"
 
+source "drivers/watchdog/Kconfig.it51xxx"
+
 source "drivers/watchdog/Kconfig.it8xxx2"
 
 source "drivers/watchdog/Kconfig.rpi_pico"
@@ -141,4 +147,8 @@ source "drivers/watchdog/Kconfig.ene"
 
 source "drivers/watchdog/Kconfig.litex"
 
+source "drivers/watchdog/Kconfig.rts5912"
+
+source "drivers/watchdog/Kconfig.renesas_ra"
+
 endif # WATCHDOG
diff --git a/drivers/watchdog/Kconfig.it51xxx b/drivers/watchdog/Kconfig.it51xxx
new file mode 100644
index 00000000000..2ac7c7307ee
--- /dev/null
+++ b/drivers/watchdog/Kconfig.it51xxx
@@ -0,0 +1,29 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config WDT_ITE_IT51XXX
+	bool "ITE it51xxx Watchdog Timer (WDT) driver"
+	default y
+	depends on DT_HAS_ITE_IT51XXX_WATCHDOG_ENABLED
+	select HAS_WDT_DISABLE_AT_BOOT
+	help
+	  This option enables the Watchdog Timer driver for ITE it51xxx.
+	  This driver supports only one channel that id is 0 and 16-bits
+	  resolution WDT.
+
+config WDT_ITE_WARNING_LEADING_TIME_MS
+	int "Number of ms before generating watchdog event/signal"
+	depends on WDT_ITE_IT51XXX
+	default 500
+	help
+	  This option defines the window in which a watchdog event must be
+	  handled. After this time window, the watchdog reset triggers
+	  immediately.
+
+config WDT_ITE_REDUCE_WARNING_LEADING_TIME
+	bool "Reduce warning leading time"
+	depends on WDT_ITE_IT51XXX
+	help
+	  Once warning timer triggered, if watchdog timer isn't reloaded,
+	  then we will reduce interval of warning timer to 30ms to print
+	  more warning messages before watchdog reset.
diff --git a/drivers/watchdog/Kconfig.mcux b/drivers/watchdog/Kconfig.mcux
index 32ccd4c7822..a604bdd3c69 100644
--- a/drivers/watchdog/Kconfig.mcux
+++ b/drivers/watchdog/Kconfig.mcux
@@ -37,3 +37,10 @@ config WDT_MCUX_WWDT_WARNING_INTERRUPT_CFG
 	  the number of watchdog counter ticks before timeout.
 
 endif # WDT_MCUX_WWDT
+
+config WDT_MCUX_RTWDOG
+	bool "MCUX RTWDOG driver"
+	default y
+	depends on DT_HAS_NXP_RTWDOG_ENABLED
+	help
+	  Enable the mcux rtwdog driver.
diff --git a/drivers/watchdog/Kconfig.renesas_ra b/drivers/watchdog/Kconfig.renesas_ra
new file mode 100644
index 00000000000..7c6a49a56da
--- /dev/null
+++ b/drivers/watchdog/Kconfig.renesas_ra
@@ -0,0 +1,30 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config WDT_RENESAS_RA
+	bool "Watchdog Driver for Renesas RA family"
+	default y
+	depends on DT_HAS_RENESAS_RA_WDT_ENABLED
+	select HAS_WDT_DISABLE_AT_BOOT
+	select SOC_OPTION_SETTING_MEMORY if SOC_SERIES_RA4M1
+	select USE_RA_FSP_WDT
+	help
+	  Enable watchdog driver for Renesas RA MCUs
+
+if WDT_RENESAS_RA
+
+config WDT_RENESAS_RA_NMI
+	bool "NMI interrupt enable"
+	default y
+	select RUNTIME_NMI
+	help
+	  Watchdog timer generates NMI at value 0
+
+config WDT_RENESAS_RA_START_IN_BOOT
+	bool "Start WDT in boot time"
+	default y
+	depends on !HAS_WDT_DISABLE_AT_BOOT
+	help
+	  Start watchdog in boot time
+
+endif # WDT_RENESAS_RA
diff --git a/drivers/watchdog/Kconfig.rts5912 b/drivers/watchdog/Kconfig.rts5912
new file mode 100644
index 00000000000..223b7c0a693
--- /dev/null
+++ b/drivers/watchdog/Kconfig.rts5912
@@ -0,0 +1,11 @@
+# Copyright (c) 2025, Realtek, SIBG-SD7
+# SPDX-License-Identifier: Apache-2.0
+
+config WDT_RTS5912
+	bool "Realtek RTS5912 Embedded Controller Watchdog Driver"
+	default y
+	depends on DT_HAS_REALTEK_RTS5912_WATCHDOG_ENABLED
+	select HAS_WDT_DISABLE_AT_BOOT
+	help
+	  This option enables the WDT driver for Realtek RTS5912 family of
+	  processors.
diff --git a/drivers/watchdog/Kconfig.sam4l b/drivers/watchdog/Kconfig.sam4l
new file mode 100644
index 00000000000..5a212c163bd
--- /dev/null
+++ b/drivers/watchdog/Kconfig.sam4l
@@ -0,0 +1,10 @@
+# Copyright (C) 2024-2025, Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config WDT_SAM4L
+	bool "Atmel SAM4L MCU Family Watchdog (WDT) Driver"
+	default y
+	depends on DT_HAS_ATMEL_SAM4L_WATCHDOG_ENABLED
+	select HAS_WDT_DISABLE_AT_BOOT
+	help
+	  Enable WDT driver for Atmel SAM4L MCUs.
diff --git a/drivers/watchdog/Kconfig.siwx91x b/drivers/watchdog/Kconfig.siwx91x
new file mode 100644
index 00000000000..d2441a3b274
--- /dev/null
+++ b/drivers/watchdog/Kconfig.siwx91x
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config WDT_SILABS_SIWX91X
+	bool "Silabs SiWx91x Watchdog driver"
+	default y
+	depends on DT_HAS_SILABS_SIWX91X_WDT_ENABLED
+	help
+	  Enable the Watchdog driver for the Silabs SiWx91x SoC series.
diff --git a/drivers/watchdog/wdt_ambiq.c b/drivers/watchdog/wdt_ambiq.c
index e886af3feb3..e2078730f98 100644
--- a/drivers/watchdog/wdt_ambiq.c
+++ b/drivers/watchdog/wdt_ambiq.c
@@ -10,7 +10,7 @@
 #include <zephyr/drivers/watchdog.h>
 
 #include <errno.h>
-#include <am_mcu_apollo.h>
+#include <soc.h>
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(wdt_ambiq, CONFIG_WDT_LOG_LEVEL);
@@ -85,8 +85,9 @@ static int wdt_ambiq_setup(const struct device *dev, uint8_t options)
 	cfg.ui32InterruptValue = data->timeout;
 	cfg.bResetEnable = data->reset;
 	cfg.ui32ResetValue = data->timeout;
+#if defined(CONFIG_SOC_SERIES_APOLLO4X)
 	cfg.bAlertOnDSPReset = false;
-
+#endif
 	am_hal_wdt_config(AM_HAL_WDT_MCU, &cfg);
 	am_hal_wdt_interrupt_enable(AM_HAL_WDT_MCU, AM_HAL_WDT_INTERRUPT_MCU);
 	am_hal_wdt_start(AM_HAL_WDT_MCU, false);
diff --git a/drivers/watchdog/wdt_cmsdk_apb.c b/drivers/watchdog/wdt_cmsdk_apb.c
index d5f05b0153a..2e97d429e26 100644
--- a/drivers/watchdog/wdt_cmsdk_apb.c
+++ b/drivers/watchdog/wdt_cmsdk_apb.c
@@ -69,6 +69,7 @@ const struct device *wdog_r;
 static unsigned int reload_cycles = CMSDK_APB_WDOG_RELOAD;
 static uint8_t assigned_channels;
 static uint8_t flags;
+static bool enabled;
 
 static void (*user_cb)(const struct device *dev, int channel_id);
 
@@ -88,9 +89,19 @@ static int wdog_cmsdk_apb_setup(const struct device *dev, uint8_t options)
 	ARG_UNUSED(dev);
 	ARG_UNUSED(options);
 
+	/* Check if watchdog is already running */
+	if (enabled) {
+		return -EBUSY;
+	}
+
+	/* Reset pending interrupts before starting */
+	wdog->intclr = CMSDK_APB_WDOG_INTCLR;
+	wdog->load = reload_cycles;
+
 	/* Start the watchdog counter with INTEN bit */
 	wdog->ctrl = (CMSDK_APB_WDOG_CTRL_RESEN | CMSDK_APB_WDOG_CTRL_INTEN);
 
+	enabled = true;
 	return 0;
 }
 
@@ -103,6 +114,7 @@ static int wdog_cmsdk_apb_disable(const struct device *dev)
 	/* Stop the watchdog counter with INTEN bit */
 	wdog->ctrl = ~(CMSDK_APB_WDOG_CTRL_RESEN | CMSDK_APB_WDOG_CTRL_INTEN);
 
+	enabled = false;
 	assigned_channels = 0;
 
 	return 0;
@@ -119,6 +131,9 @@ static int wdog_cmsdk_apb_install_timeout(const struct device *dev,
 	if (config->window.max == 0) {
 		return -EINVAL;
 	}
+	if (enabled == true) {
+		return -EBUSY;
+	}
 	if (assigned_channels == 1) {
 		return -ENOMEM;
 	}
diff --git a/drivers/watchdog/wdt_esp32.c b/drivers/watchdog/wdt_esp32.c
index 66caa75bdc6..acaf7d7ce0c 100644
--- a/drivers/watchdog/wdt_esp32.c
+++ b/drivers/watchdog/wdt_esp32.c
@@ -1,12 +1,12 @@
 /*
  * Copyright (C) 2017 Intel Corporation
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #define DT_DRV_COMPAT espressif_esp32_watchdog
 
-/* Include esp-idf headers first to avoid redefining BIT() macro */
 #if defined(CONFIG_SOC_SERIES_ESP32C6)
 #include <soc/lp_aon_reg.h>
 #else
@@ -19,22 +19,12 @@
 #include <string.h>
 #include <zephyr/drivers/watchdog.h>
 #include <zephyr/drivers/clock_control.h>
-#if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-#else
 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
-#endif
 #include <zephyr/device.h>
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(wdt_esp32, CONFIG_WDT_LOG_LEVEL);
 
-#if defined(CONFIG_SOC_SERIES_ESP32C3) || defined(CONFIG_SOC_SERIES_ESP32C6)
-#define ISR_HANDLER isr_handler_t
-#else
-#define ISR_HANDLER intr_handler_t
-#endif
-
 #define MWDT_TICK_PRESCALER		40000
 #define MWDT_TICKS_PER_US		500
 
@@ -170,7 +160,7 @@ static int wdt_esp32_init(const struct device *dev)
 	wdt_hal_init(&data->hal, config->wdt_inst, MWDT_TICK_PRESCALER, true);
 
 	flags = ESP_PRIO_TO_FLAGS(config->irq_priority) | ESP_INT_FLAGS_CHECK(config->irq_flags);
-	ret = esp_intr_alloc(config->irq_source, flags, (ISR_HANDLER)wdt_esp32_isr, (void *)dev,
+	ret = esp_intr_alloc(config->irq_source, flags, (intr_handler_t)wdt_esp32_isr, (void *)dev,
 			     NULL);
 
 	if (ret != 0) {
diff --git a/drivers/watchdog/wdt_gecko.c b/drivers/watchdog/wdt_gecko.c
index 581fd7c054a..7ec18a9a574 100644
--- a/drivers/watchdog/wdt_gecko.c
+++ b/drivers/watchdog/wdt_gecko.c
@@ -98,6 +98,10 @@ static int wdt_gecko_setup(const struct device *dev, uint8_t options)
 		return -EINVAL;
 	}
 
+#if defined(_WDOG_CFG_EM1RUN_MASK)
+	data->wdog_config.em1Run =
+		(options & WDT_OPT_PAUSE_IN_SLEEP) == 0U;
+#endif
 	data->wdog_config.em2Run =
 		(options & WDT_OPT_PAUSE_IN_SLEEP) == 0U;
 	data->wdog_config.em3Run =
diff --git a/drivers/watchdog/wdt_ite_it51xxx.c b/drivers/watchdog/wdt_ite_it51xxx.c
new file mode 100644
index 00000000000..17ed95a86c1
--- /dev/null
+++ b/drivers/watchdog/wdt_ite_it51xxx.c
@@ -0,0 +1,322 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT ite_it51xxx_watchdog
+
+#include <errno.h>
+#include <soc.h>
+#include <zephyr/drivers/watchdog.h>
+#include <zephyr/irq.h>
+
+#include <zephyr/logging/log.h>
+#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
+LOG_MODULE_REGISTER(wdt_ite_it51xxx);
+
+#define IT51XXX_WATCHDOG_MAGIC_BYTE                 0x5c
+#define WARNING_TIMER_PERIOD_MS_TO_1024HZ_COUNT(ms) ((ms) * 1024 / 1000)
+
+/* 0x81: External Timer1/WDT Configuration */
+#define REG_ETWCFG          0x01
+#define WDT_EWDKEYEN        BIT(5)
+#define WDT_EWDSRC          BIT(4)
+#define WDT_LEWDCNTL        BIT(3)
+#define WDT_LET1CNTL        BIT(2)
+#define WDT_LET1PS          BIT(1)
+#define WDT_LETWCFG         BIT(0)
+/* 0x82: External Timer1 Prescaler */
+#define REG_ET1PSR          0x02
+#define WDT_ETPS_32P768_KHZ 0x00
+#define WDT_ETPS_1P024_KHZ  0x01
+#define WDT_ETPS_32_HZ      0x02
+/* 0x83: External Timer1 Counter High Byte */
+#define REG_ET1CNTLHR       0x03
+/* 0x84: External Timer1 Counter Low Byte */
+#define REG_ET1CNTLLR       0x04
+/* 0x85: External Timer1/WDT Control */
+#define REG_ETWCTRL         0x05
+#define WDT_EWDSCEN         BIT(5)
+#define WDT_EWDSCMS         BIT(4)
+#define WDT_ET1TC           BIT(1)
+#define WDT_ET1RST          BIT(0)
+/* 0x86: External WDT Counter Low Byte */
+#define REG_EWDCNTLR        0x06
+/* 0x87: External WDT Key */
+#define REG_EWDKEYR         0x07
+/* 0x89: External WDT Counter High Byte */
+#define REG_EWDCNTHR        0x09
+
+/* device config */
+struct wdt_it51xxx_config {
+	/* wdt register base address */
+	uintptr_t base;
+};
+
+/* driver data */
+struct wdt_it51xxx_data {
+	/* timeout callback used to handle watchdog event */
+	wdt_callback_t callback;
+	/* indicate whether a watchdog timeout is installed */
+	bool timeout_installed;
+	/* watchdog feed timeout in milliseconds */
+	uint32_t timeout;
+	/* pre-warning timer1 fired times */
+	int wdt_warning_fired;
+};
+
+static int wdt_it51xxx_install_timeout(const struct device *dev,
+				       const struct wdt_timeout_cfg *config)
+{
+	const struct wdt_it51xxx_config *const wdt_config = dev->config;
+	struct wdt_it51xxx_data *data = dev->data;
+	const uintptr_t base = wdt_config->base;
+
+	/* if watchdog is already running */
+	if (sys_read8(base + REG_ETWCFG) & WDT_LEWDCNTL) {
+		return -EBUSY;
+	}
+
+	/*
+	 * Not support lower limit window timeouts (min value must be equal to
+	 * 0). Upper limit window timeouts can't be 0 when we install timeout.
+	 */
+	if ((config->window.min != 0) || (config->window.max == 0)) {
+		data->timeout_installed = false;
+		return -EINVAL;
+	}
+
+	/* save watchdog timeout */
+	data->timeout = config->window.max;
+
+	/* install user timeout isr */
+	data->callback = config->callback;
+
+	/* mark installed */
+	data->timeout_installed = true;
+
+	return 0;
+}
+
+static int wdt_it51xxx_setup(const struct device *dev, uint8_t options)
+{
+	const struct wdt_it51xxx_config *const wdt_config = dev->config;
+	struct wdt_it51xxx_data *data = dev->data;
+	const uintptr_t base = wdt_config->base;
+	uint16_t cnt0 = WARNING_TIMER_PERIOD_MS_TO_1024HZ_COUNT(data->timeout);
+	uint16_t cnt1 = WARNING_TIMER_PERIOD_MS_TO_1024HZ_COUNT(
+		(data->timeout + CONFIG_WDT_ITE_WARNING_LEADING_TIME_MS));
+	uint8_t reg_val;
+
+	/* disable pre-warning timer1 interrupt */
+	irq_disable(DT_INST_IRQN(0));
+
+	if (!data->timeout_installed) {
+		LOG_ERR("No valid WDT timeout installed");
+		return -EINVAL;
+	}
+
+	if (sys_read8(base + REG_ETWCFG) & WDT_LEWDCNTL) {
+		LOG_ERR("WDT is already running");
+		return -EBUSY;
+	}
+
+	if ((options & WDT_OPT_PAUSE_IN_SLEEP) != 0) {
+		LOG_ERR("WDT_OPT_PAUSE_IN_SLEEP is not supported");
+		return -ENOTSUP;
+	}
+
+	/* pre-warning timer1 is 16-bit counter down timer */
+	sys_write8((cnt0 >> 8) & 0xff, base + REG_ET1CNTLHR);
+	sys_write8(cnt0 & 0xff, base + REG_ET1CNTLLR);
+
+	/* clear pre-warning timer1 interrupt status */
+	ite_intc_isr_clear(DT_INST_IRQN(0));
+
+	/* enable pre-warning timer1 interrupt */
+	irq_enable(DT_INST_IRQN(0));
+
+	/* don't stop watchdog timer counting */
+	reg_val = sys_read8(base + REG_ETWCTRL);
+	sys_write8(reg_val & ~WDT_EWDSCEN, base + REG_ETWCTRL);
+
+	/* set watchdog timer count */
+	sys_write8((cnt1 >> 8) & 0xff, base + REG_EWDCNTHR);
+	sys_write8(cnt1 & 0xff, base + REG_EWDCNTLR);
+
+	/* allow to write timer1 count register */
+	reg_val = sys_read8(base + REG_ETWCFG);
+	sys_write8(reg_val & ~WDT_LET1CNTL, base + REG_ETWCFG);
+
+	/*
+	 * bit5 = 1: enable key match function to touch watchdog
+	 * bit4 = 1: select watchdog clock source from prescaler
+	 * bit3 = 1: lock watchdog count register (also mark as watchdog running)
+	 * bit1 = 1: lock timer1 prescaler register
+	 */
+	sys_write8((WDT_EWDKEYEN | WDT_EWDSRC | WDT_LEWDCNTL | WDT_LET1PS), base + REG_ETWCFG);
+
+	LOG_DBG("WDT Setup and enabled");
+
+	return 0;
+}
+
+/*
+ * reload the WDT and pre-warning timer1 counter
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @param channel_id Index of the fed channel, and we only support
+ *                   channel_id = 0 now.
+ */
+static int wdt_it51xxx_feed(const struct device *dev, int channel_id)
+{
+	const struct wdt_it51xxx_config *const wdt_config = dev->config;
+	struct wdt_it51xxx_data *data = dev->data;
+	const uintptr_t base = wdt_config->base;
+	uint16_t cnt0 = WARNING_TIMER_PERIOD_MS_TO_1024HZ_COUNT(data->timeout);
+	uint8_t reg_val;
+
+	ARG_UNUSED(channel_id);
+
+	/* reset pre-warning timer1 */
+	reg_val = sys_read8(base + REG_ETWCTRL);
+	sys_write8(reg_val | WDT_ET1RST, base + REG_ETWCTRL);
+
+	/* restart watchdog timer */
+	sys_write8(IT51XXX_WATCHDOG_MAGIC_BYTE, base + REG_EWDKEYR);
+
+	/* reset pre-warning timer1 to default if time is touched */
+	if (data->wdt_warning_fired) {
+		data->wdt_warning_fired = 0;
+
+		/* pre-warning timer1 is 16-bit counter down timer */
+		sys_write8((cnt0 >> 8) & 0xff, base + REG_ET1CNTLHR);
+		sys_write8(cnt0 & 0xff, base + REG_ET1CNTLLR);
+
+		/* clear timer1 interrupt status */
+		ite_intc_isr_clear(DT_INST_IRQN(0));
+
+		/* enable timer1 interrupt */
+		irq_enable(DT_INST_IRQN(0));
+	}
+
+	LOG_DBG("WDT Kicking");
+
+	return 0;
+}
+
+static int wdt_it51xxx_disable(const struct device *dev)
+{
+	const struct wdt_it51xxx_config *const wdt_config = dev->config;
+	struct wdt_it51xxx_data *data = dev->data;
+	const uintptr_t base = wdt_config->base;
+	uint8_t reg_val;
+
+	/* stop watchdog timer counting */
+	reg_val = sys_read8(base + REG_ETWCTRL);
+	sys_write8(reg_val | WDT_EWDSCEN, base + REG_ETWCTRL);
+
+	/* unlock watchdog count register (also mark as watchdog not running) */
+	reg_val = sys_read8(base + REG_ETWCFG);
+	sys_write8(reg_val & ~WDT_LEWDCNTL, base + REG_ETWCFG);
+
+	/* disable pre-warning timer1 interrupt */
+	irq_disable(DT_INST_IRQN(0));
+
+	/* mark uninstalled */
+	data->timeout_installed = false;
+
+	LOG_DBG("WDT Disabled");
+
+	return 0;
+}
+
+static void wdt_it51xxx_isr(const struct device *dev)
+{
+	const struct wdt_it51xxx_config *const wdt_config = dev->config;
+	struct wdt_it51xxx_data *data = dev->data;
+	const uintptr_t base = wdt_config->base;
+	uint8_t reg_val;
+
+	/* clear pre-warning timer1 interrupt status */
+	ite_intc_isr_clear(DT_INST_IRQN(0));
+
+	/* reset pre-warning timer1 */
+	reg_val = sys_read8(base + REG_ETWCTRL);
+	sys_write8(reg_val | WDT_ET1RST, base + REG_ETWCTRL);
+
+	/* callback function, ex. print warning message */
+	if (data->callback) {
+		data->callback(dev, 0);
+	}
+
+	if (IS_ENABLED(CONFIG_WDT_ITE_REDUCE_WARNING_LEADING_TIME)) {
+		/*
+		 * Once warning timer triggered: if watchdog timer isn't reloaded,
+		 * then we will reduce interval of warning timer to 30ms to print
+		 * more warning messages before watchdog reset.
+		 */
+		if (!(data->wdt_warning_fired)) {
+			uint16_t cnt0 = WARNING_TIMER_PERIOD_MS_TO_1024HZ_COUNT(30);
+
+			/* pre-warning timer1 is 16-bit counter down timer */
+			sys_write8((cnt0 >> 8) & 0xff, base + REG_ET1CNTLHR);
+			sys_write8(cnt0 & 0xff, base + REG_ET1CNTLLR);
+
+			/* clear pre-warning timer1 interrupt status */
+			ite_intc_isr_clear(DT_INST_IRQN(0));
+		}
+	}
+	data->wdt_warning_fired++;
+
+	LOG_DBG("WDT ISR");
+}
+
+static DEVICE_API(wdt, wdt_it51xxx_api) = {
+	.setup = wdt_it51xxx_setup,
+	.disable = wdt_it51xxx_disable,
+	.install_timeout = wdt_it51xxx_install_timeout,
+	.feed = wdt_it51xxx_feed,
+};
+
+static int wdt_it51xxx_init(const struct device *dev)
+{
+	const struct wdt_it51xxx_config *const wdt_config = dev->config;
+	const uintptr_t base = wdt_config->base;
+	uint8_t reg_val;
+
+	if (IS_ENABLED(CONFIG_WDT_DISABLE_AT_BOOT)) {
+		wdt_it51xxx_disable(dev);
+	}
+
+	/* unlock access to watchdog registers */
+	sys_write8(0x00, base + REG_ETWCFG);
+
+	/* set WDT and timer1 to use 1.024kHz clock */
+	sys_write8(WDT_ETPS_1P024_KHZ, base + REG_ET1PSR);
+
+	/* set WDT key match enabled and WDT clock to use ET1PSR */
+	sys_write8(WDT_EWDKEYEN | WDT_EWDSRC, base + REG_ETWCFG);
+
+	/*
+	 * select the mode that watchdog can be stopped, this is needed for
+	 * wdt_it51xxx_disable() api and WDT_OPT_PAUSE_HALTED_BY_DBG flag
+	 */
+	reg_val = sys_read8(base + REG_ETWCTRL);
+	sys_write8(reg_val | WDT_EWDSCMS, base + REG_ETWCTRL);
+
+	IRQ_CONNECT(DT_INST_IRQN(0), 0, wdt_it51xxx_isr, DEVICE_DT_INST_GET(0), 0);
+	return 0;
+}
+
+static const struct wdt_it51xxx_config wdt_it51xxx_cfg_0 = {
+	.base = DT_INST_REG_ADDR(0),
+};
+
+static struct wdt_it51xxx_data wdt_it51xxx_dev_data;
+
+DEVICE_DT_INST_DEFINE(0, wdt_it51xxx_init, NULL, &wdt_it51xxx_dev_data, &wdt_it51xxx_cfg_0,
+		      PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &wdt_it51xxx_api);
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1,
+	     "only one ite,it51xxx-watchdog compatible node can be supported");
diff --git a/drivers/watchdog/wdt_iwdg_stm32.c b/drivers/watchdog/wdt_iwdg_stm32.c
index da045de447c..682963b1070 100644
--- a/drivers/watchdog/wdt_iwdg_stm32.c
+++ b/drivers/watchdog/wdt_iwdg_stm32.c
@@ -10,10 +10,12 @@
 #define DT_DRV_COMPAT st_stm32_watchdog
 
 #include <zephyr/drivers/watchdog.h>
+#include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <zephyr/kernel.h>
 #include <zephyr/sys_clock.h>
 #include <soc.h>
 #include <stm32_ll_bus.h>
+#include <stm32_ll_rcc.h>
 #include <stm32_ll_iwdg.h>
 #include <stm32_ll_system.h>
 #include <errno.h>
@@ -84,20 +86,22 @@ static void iwdg_stm32_convert_timeout(uint32_t timeout,
 
 static int iwdg_stm32_setup(const struct device *dev, uint8_t options)
 {
-	struct iwdg_stm32_data *data = IWDG_STM32_DATA(dev);
-	IWDG_TypeDef *iwdg = IWDG_STM32_STRUCT(dev);
+	const struct iwdg_stm32_config *cfg = dev->config;
+	struct iwdg_stm32_data *data = dev->data;
 	uint32_t tickstart;
 
 	/* Deactivate running when debugger is attached. */
 	if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
-#if defined(CONFIG_SOC_SERIES_STM32F0X)
+#if defined(CONFIG_SOC_SERIES_STM32WB0X)
+		/* STM32WB0 watchdog does not support halt by debugger */
+		return -ENOTSUP;
+#elif defined(CONFIG_SOC_SERIES_STM32F0X)
 		LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU);
 #elif defined(CONFIG_SOC_SERIES_STM32C0X) || defined(CONFIG_SOC_SERIES_STM32G0X)
 		LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU);
 #elif defined(CONFIG_SOC_SERIES_STM32L0X)
 		LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
-#endif
-#if defined(CONFIG_SOC_SERIES_STM32H7X)
+#elif defined(CONFIG_SOC_SERIES_STM32H7X)
 		LL_DBGMCU_APB4_GRP1_FreezePeriph(LL_DBGMCU_APB4_GRP1_IWDG1_STOP);
 #elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
 		LL_DBGMCU_APB4_GRP1_FreezePeriph(LL_DBGMCU_APB4_GRP1_IWDG_STOP);
@@ -111,23 +115,23 @@ static int iwdg_stm32_setup(const struct device *dev, uint8_t options)
 	}
 
 	/* Enable the IWDG now and write IWDG registers at the same time */
-	LL_IWDG_Enable(iwdg);
-	LL_IWDG_EnableWriteAccess(iwdg);
+	LL_IWDG_Enable(cfg->instance);
+	LL_IWDG_EnableWriteAccess(cfg->instance);
 	/* Write the prescaler and reload counter to the IWDG registers*/
-	LL_IWDG_SetPrescaler(iwdg, data->prescaler);
-	LL_IWDG_SetReloadCounter(iwdg, data->reload);
+	LL_IWDG_SetPrescaler(cfg->instance, data->prescaler);
+	LL_IWDG_SetReloadCounter(cfg->instance, data->reload);
 
 	tickstart = k_uptime_get_32();
 
 	/* Wait for the update operation completed */
-	while (LL_IWDG_IsReady(iwdg) == 0) {
+	while (LL_IWDG_IsReady(cfg->instance) == 0) {
 		if ((k_uptime_get_32() - tickstart) > IWDG_SR_UPDATE_TIMEOUT) {
 			return -ENODEV;
 		}
 	}
 
 	/* Reload counter just before leaving */
-	LL_IWDG_ReloadCounter(iwdg);
+	LL_IWDG_ReloadCounter(cfg->instance);
 
 	return 0;
 }
@@ -143,7 +147,7 @@ static int iwdg_stm32_disable(const struct device *dev)
 static int iwdg_stm32_install_timeout(const struct device *dev,
 				      const struct wdt_timeout_cfg *config)
 {
-	struct iwdg_stm32_data *data = IWDG_STM32_DATA(dev);
+	struct iwdg_stm32_data *data = dev->data;
 	uint32_t timeout = config->window.max * USEC_PER_MSEC;
 	uint32_t prescaler = 0U;
 	uint32_t reload = 0U;
@@ -151,6 +155,10 @@ static int iwdg_stm32_install_timeout(const struct device *dev,
 	if (config->callback != NULL) {
 		return -ENOTSUP;
 	}
+	if (data->reload) {
+		/* Timeout has already been configured */
+		return -ENOMEM;
+	}
 
 	/* Calculating parameters to be applied later, on setup */
 	iwdg_stm32_convert_timeout(timeout, &prescaler, &reload);
@@ -171,10 +179,10 @@ static int iwdg_stm32_install_timeout(const struct device *dev,
 
 static int iwdg_stm32_feed(const struct device *dev, int channel_id)
 {
-	IWDG_TypeDef *iwdg = IWDG_STM32_STRUCT(dev);
+	const struct iwdg_stm32_config *cfg = dev->config;
 
 	ARG_UNUSED(channel_id);
-	LL_IWDG_ReloadCounter(iwdg);
+	LL_IWDG_ReloadCounter(cfg->instance);
 
 	return 0;
 }
@@ -188,6 +196,43 @@ static DEVICE_API(wdt, iwdg_stm32_api) = {
 
 static int iwdg_stm32_init(const struct device *dev)
 {
+/* Enable watchdog clock if needed */
+#if DT_INST_NODE_HAS_PROP(0, clocks)
+	const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
+	const struct stm32_pclken clk_cfg = STM32_CLOCK_INFO(0, DT_DRV_INST(0));
+	int err = clock_control_on(clk, (clock_control_subsys_t)&clk_cfg);
+
+	if (err < 0) {
+		return err;
+	}
+#if defined(CONFIG_SOC_SERIES_STM32WB0X)
+	/**
+	 * On STM32WB0, application must wait two slow clock cycles
+	 * before accessing the IWDG IP after turning on the WDGEN
+	 * bit in RCC registers. However, there is no register that
+	 * can be polled for this event.
+	 * To work around this limitation, force the IWDG to go
+	 * through a reset cycle, which also takes two slow clock
+	 * cycles, but can polled on (bit WDGRSTF of RCC_CIFR).
+	 */
+
+	/* Clear bit beforehand to avoid early exit of polling loop */
+	LL_RCC_ClearFlag_WDGRSTREL();
+
+	/* Place IWDG under reset, then release the reset */
+	LL_APB0_GRP1_ForceReset(LL_APB0_GRP1_PERIPH_WDG);
+	LL_APB0_GRP1_ReleaseReset(LL_APB0_GRP1_PERIPH_WDG);
+	while (!LL_RCC_IsActiveFlag_WDGRSTREL()) {
+		/* Wait for IWDG reset release event,
+		 * which takes two slow clock cycles
+		 */
+	}
+
+	/* Clear WDRSTF bit after polling completes */
+	LL_RCC_ClearFlag_WDGRSTREL();
+#endif /* defined(CONFIG_SOC_SERIES_STM32WB0X) */
+#endif /* DT_INST_NODE_HAS_PROP(0, clocks) */
+
 #ifndef CONFIG_WDT_DISABLE_AT_BOOT
 	struct wdt_timeout_cfg config = {
 		.window.max = CONFIG_IWDG_STM32_INITIAL_TIMEOUT
@@ -210,11 +255,12 @@ static int iwdg_stm32_init(const struct device *dev)
 	return 0;
 }
 
-static struct iwdg_stm32_data iwdg_stm32_dev_data = {
-	.Instance = (IWDG_TypeDef *)DT_INST_REG_ADDR(0)
+static const struct iwdg_stm32_config iwdg_stm32_dev_cfg = {
+	.instance = (IWDG_TypeDef *)DT_INST_REG_ADDR(0),
 };
+static struct iwdg_stm32_data iwdg_stm32_dev_data;
 
 DEVICE_DT_INST_DEFINE(0, iwdg_stm32_init, NULL,
-		    &iwdg_stm32_dev_data, NULL,
+		    &iwdg_stm32_dev_data, &iwdg_stm32_dev_cfg,
 		    POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
 		    &iwdg_stm32_api);
diff --git a/drivers/watchdog/wdt_iwdg_stm32.h b/drivers/watchdog/wdt_iwdg_stm32.h
index d953f61b99d..2d3e5a81570 100644
--- a/drivers/watchdog/wdt_iwdg_stm32.h
+++ b/drivers/watchdog/wdt_iwdg_stm32.h
@@ -20,18 +20,14 @@
  *
  */
 
-/* driver data */
-struct iwdg_stm32_data {
+struct iwdg_stm32_config {
 	/* IWDG peripheral instance. */
-	IWDG_TypeDef *Instance;
+	IWDG_TypeDef *instance;
+};
+
+struct iwdg_stm32_data {
 	uint32_t prescaler;
 	uint32_t reload;
 };
 
-#define IWDG_STM32_DATA(dev)					\
-	((struct iwdg_stm32_data * const)(dev)->data)
-
-#define IWDG_STM32_STRUCT(dev)					\
-	((IWDG_TypeDef *)(IWDG_STM32_DATA(dev))->Instance)
-
 #endif	/* ZEPHYR_DRIVERS_WATCHDOG_IWDG_STM32_H_ */
diff --git a/drivers/watchdog/wdt_mcux_rtwdog.c b/drivers/watchdog/wdt_mcux_rtwdog.c
new file mode 100644
index 00000000000..57a026917dc
--- /dev/null
+++ b/drivers/watchdog/wdt_mcux_rtwdog.c
@@ -0,0 +1,225 @@
+/*
+ * Copyright 2024, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT nxp_rtwdog
+
+#include <zephyr/drivers/pinctrl.h>
+#include <zephyr/drivers/watchdog.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/sys_clock.h>
+#include <fsl_rtwdog.h>
+
+#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
+#include <zephyr/logging/log.h>
+#include <zephyr/irq.h>
+LOG_MODULE_REGISTER(wdt_mcux_rtwdog);
+
+#define MSEC_TO_RTWDOG_TICKS(clock_freq, divider, msec)                                            \
+	((uint32_t)(clock_freq * msec / 1000U / divider))
+
+#define RTWDOG_MIN_TIMEOUT 1U
+
+struct mcux_rtwdog_config {
+	RTWDOG_Type *base;
+	uint32_t clock_frequency;
+	rtwdog_clock_source_t clk_source;
+	rtwdog_clock_prescaler_t clk_divider;
+	void (*irq_config_func)(const struct device *dev);
+};
+
+struct mcux_rtwdog_data {
+	wdt_callback_t callback;
+	rtwdog_config_t wdog_config;
+	bool timeout_valid;
+	bool enabled;
+};
+
+static int mcux_rtwdog_setup(const struct device *dev, uint8_t options)
+{
+	const struct mcux_rtwdog_config *config = dev->config;
+	struct mcux_rtwdog_data *data = dev->data;
+	RTWDOG_Type *base = config->base;
+
+	if (!data->timeout_valid) {
+		LOG_ERR("No valid timeouts installed");
+		return -EINVAL;
+	}
+
+	if (data->enabled) {
+		LOG_ERR("This watchdog has been enabled");
+		return -EBUSY;
+	}
+
+	if ((options & WDT_OPT_PAUSE_IN_SLEEP) != 0U) {
+		LOG_ERR("Not support WDT_OPT_PAUSE_IN_SLEEP");
+		return -ENOTSUP;
+	}
+
+	data->wdog_config.workMode.enableDebug = ((options & WDT_OPT_PAUSE_HALTED_BY_DBG) == 0U);
+
+	RTWDOG_Init(base, &data->wdog_config);
+	data->enabled = true;
+	LOG_DBG("Setup the watchdog");
+
+	return 0;
+}
+
+static int mcux_rtwdog_disable(const struct device *dev)
+{
+	const struct mcux_rtwdog_config *config = dev->config;
+	struct mcux_rtwdog_data *data = dev->data;
+	RTWDOG_Type *base = config->base;
+
+	data->timeout_valid = false;
+
+	if (!data->enabled) {
+		LOG_ERR("Disabled when watchdog is not enabled");
+		return -EFAULT;
+	}
+
+	RTWDOG_Deinit(base);
+	data->enabled = false;
+	LOG_DBG("Disabled the watchdog");
+
+	return 0;
+}
+
+static int mcux_rtwdog_install_timeout(const struct device *dev, const struct wdt_timeout_cfg *cfg)
+{
+	const struct mcux_rtwdog_config *config = dev->config;
+	struct mcux_rtwdog_data *data = dev->data;
+	uint32_t clock_freq;
+	uint32_t clk_divider;
+
+	if (data->enabled) {
+		LOG_ERR("Timeout can not be installed while watchdog has already been setup");
+		return -EBUSY;
+	}
+
+	if (data->timeout_valid) {
+		LOG_ERR("No more timeouts can be installed");
+		return -ENOMEM;
+	}
+
+	if (cfg->flags == WDT_FLAG_RESET_NONE) {
+		LOG_ERR("Not support WDT_FLAG_RESET_NONE");
+		return -ENOTSUP;
+	}
+
+	RTWDOG_GetDefaultConfig(&data->wdog_config);
+
+	clock_freq = config->clock_frequency;
+	clk_divider = config->clk_divider == kRTWDOG_ClockPrescalerDivide1 ? 1U : 256U;
+
+	data->wdog_config.clockSource = config->clk_source;
+	data->wdog_config.prescaler = config->clk_divider;
+	data->wdog_config.timeoutValue =
+		MSEC_TO_RTWDOG_TICKS(clock_freq, clk_divider, cfg->window.max);
+
+	if (data->wdog_config.timeoutValue > UINT16_MAX) {
+		LOG_ERR("Invalid window max");
+		return -EINVAL;
+	}
+
+	if (cfg->window.min != 0U) {
+		data->wdog_config.enableWindowMode = true;
+		data->wdog_config.windowValue =
+			MSEC_TO_RTWDOG_TICKS(clock_freq, clk_divider, cfg->window.min);
+	} else {
+		data->wdog_config.enableWindowMode = false;
+		data->wdog_config.windowValue = 0;
+	}
+
+	if ((data->wdog_config.timeoutValue < RTWDOG_MIN_TIMEOUT) ||
+	    (data->wdog_config.timeoutValue <= data->wdog_config.windowValue)) {
+		LOG_ERR("Invalid timeout");
+		return -EINVAL;
+	}
+
+	data->wdog_config.enableInterrupt = cfg->callback != NULL;
+	data->callback = cfg->callback;
+	data->timeout_valid = true;
+
+	return 0;
+}
+
+static int mcux_rtwdog_feed(const struct device *dev, int channel_id)
+{
+	const struct mcux_rtwdog_config *config = dev->config;
+	struct mcux_rtwdog_data *data = dev->data;
+	RTWDOG_Type *base = config->base;
+
+	if (channel_id != 0) {
+		LOG_ERR("Invalid channel id");
+		return -EINVAL;
+	}
+
+	if (!data->enabled) {
+		LOG_ERR("Feed disabled watchdog");
+		return -EINVAL;
+	}
+
+	RTWDOG_Refresh(base);
+	LOG_DBG("Fed the watchdog");
+
+	return 0;
+}
+
+static void mcux_rtwdog_isr(const struct device *dev)
+{
+	const struct mcux_rtwdog_config *config = dev->config;
+	struct mcux_rtwdog_data *data = dev->data;
+	RTWDOG_Type *base = config->base;
+
+	RTWDOG_ClearStatusFlags(base, kRTWDOG_InterruptFlag);
+
+	if (data->callback) {
+		data->callback(dev, 0);
+	}
+}
+
+static int mcux_rtwdog_init(const struct device *dev)
+{
+	const struct mcux_rtwdog_config *config = dev->config;
+
+	config->irq_config_func(dev);
+
+	return 0;
+}
+
+static DEVICE_API(wdt, mcux_rtwdog_api) = {
+	.setup = mcux_rtwdog_setup,
+	.disable = mcux_rtwdog_disable,
+	.install_timeout = mcux_rtwdog_install_timeout,
+	.feed = mcux_rtwdog_feed,
+};
+
+#define TO_RTWDOG_CLK_SRC(val) _DO_CONCAT(kRTWDOG_ClockSource, val)
+#define TO_RTWDOG_CLK_DIV(val) _DO_CONCAT(kRTWDOG_ClockPrescalerDivide, val)
+
+#define MCUX_RTWDOG_INIT(n)                                                                        \
+                                                                                                   \
+	static struct mcux_rtwdog_data mcux_rtwdog_data_##n;                                       \
+	static void mcux_rtwdog_config_func_##n(const struct device *dev);                         \
+                                                                                                   \
+	static const struct mcux_rtwdog_config mcux_rtwdog_config_##n = {                          \
+		.base = (RTWDOG_Type *)DT_INST_REG_ADDR(n),                                        \
+		.irq_config_func = mcux_rtwdog_config_func_##n,                                    \
+		.clock_frequency = DT_INST_PROP_BY_PHANDLE(n, clocks, clock_frequency),            \
+		.clk_source = TO_RTWDOG_CLK_SRC(DT_INST_PROP(n, clk_source)),                      \
+		.clk_divider = TO_RTWDOG_CLK_DIV(DT_INST_PROP(n, clk_divider)),                    \
+	};                                                                                         \
+	static void mcux_rtwdog_config_func_##n(const struct device *dev)                          \
+	{                                                                                          \
+		IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), mcux_rtwdog_isr,            \
+			    DEVICE_DT_INST_GET(n), 0);                                             \
+		irq_enable(DT_INST_IRQN(n));                                                       \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(n, &mcux_rtwdog_init, NULL, &mcux_rtwdog_data_##n,                   \
+			      &mcux_rtwdog_config_##n, POST_KERNEL,                                \
+			      CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &mcux_rtwdog_api);
+
+DT_INST_FOREACH_STATUS_OKAY(MCUX_RTWDOG_INIT)
diff --git a/drivers/watchdog/wdt_mcux_wwdt.c b/drivers/watchdog/wdt_mcux_wwdt.c
index 015f331e978..81ab8a5b001 100644
--- a/drivers/watchdog/wdt_mcux_wwdt.c
+++ b/drivers/watchdog/wdt_mcux_wwdt.c
@@ -83,7 +83,8 @@ static int mcux_wwdt_install_timeout(const struct device *dev,
 	}
 
 #if defined(CONFIG_SOC_MIMXRT685S_CM33) || defined(CONFIG_SOC_MIMXRT595S_CM33) \
-	|| defined(CONFIG_SOC_SERIES_MCXN)
+	|| defined(CONFIG_SOC_SERIES_MCXN) || defined(CONFIG_SOC_MIMXRT798S_CM33_CPU0) \
+	|| defined(CONFIG_SOC_MIMXRT798S_CM33_CPU1)
 	clock_freq = CLOCK_GetWdtClkFreq(0);
 #elif defined(CONFIG_SOC_SERIES_RW6XX)
 	clock_freq = CLOCK_GetWdtClkFreq();
diff --git a/drivers/watchdog/wdt_npcx.c b/drivers/watchdog/wdt_npcx.c
index 24979ce88de..c3245a50b78 100644
--- a/drivers/watchdog/wdt_npcx.c
+++ b/drivers/watchdog/wdt_npcx.c
@@ -61,7 +61,8 @@ LOG_MODULE_REGISTER(wdt_npcx, CONFIG_WDT_LOG_LEVEL);
 #define NPCX_WDT_MIN_WND_TIME 100UL
 
 /* Timeout for reloading and restarting Timer 0. (Unit:ms) */
-#define NPCX_T0CSR_RST_TIMEOUT 2
+#define NPCX_T0CSR_RST_CLEAR_TIMEOUT 2
+#define NPCX_T0CSR_RST_SET_TIMEOUT   1
 
 /* Timeout for stopping watchdog. (Unit:ms) */
 #define NPCX_WATCHDOG_STOP_TIMEOUT 1
@@ -100,10 +101,22 @@ static inline int wdt_t0out_reload(const struct device *dev)
 	/* Reload and restart T0 timer */
 	inst->T0CSR = (inst->T0CSR & ~BIT(NPCX_T0CSR_WDRST_STS)) |
 		      BIT(NPCX_T0CSR_RST);
+	/*
+	 * Wait for the T0CSR_RST bit to change from 0 to 1. This transition is expected to occur
+	 * over multiple LFCLK cycles. If a timeout occurs, we can assume that the bit has changed
+	 * from 0 -> 1 -> 0, but the polling thread missed it because it was preempted by
+	 * higher-priority threads. In this case, we can simply return.
+	 */
+	st = k_uptime_get();
+	while (!IS_BIT_SET(inst->T0CSR, NPCX_T0CSR_RST)) {
+		if (k_uptime_get() - st > NPCX_T0CSR_RST_SET_TIMEOUT) {
+			return 0;
+		}
+	}
 	/* Wait for timer is loaded and restart */
 	st = k_uptime_get();
 	while (IS_BIT_SET(inst->T0CSR, NPCX_T0CSR_RST)) {
-		if (k_uptime_get() - st > NPCX_T0CSR_RST_TIMEOUT) {
+		if (k_uptime_get() - st > NPCX_T0CSR_RST_CLEAR_TIMEOUT) {
 			/* RST bit is still set? */
 			if (IS_BIT_SET(inst->T0CSR, NPCX_T0CSR_RST)) {
 				LOG_ERR("Timeout: reload T0 timer!");
diff --git a/drivers/watchdog/wdt_renesas_ra.c b/drivers/watchdog/wdt_renesas_ra.c
new file mode 100644
index 00000000000..78790b9ccc0
--- /dev/null
+++ b/drivers/watchdog/wdt_renesas_ra.c
@@ -0,0 +1,332 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/drivers/watchdog.h>
+#include "r_wdt.h"
+
+LOG_MODULE_REGISTER(wdt_renesas_ra, CONFIG_WDT_LOG_LEVEL);
+
+struct wdt_renesas_ra_config {
+	const struct device *clock_dev;
+	const struct clock_control_ra_subsys_cfg clock_subsys;
+};
+
+struct wdt_renesas_ra_data {
+	struct wdt_timeout_cfg timeout;
+	struct st_wdt_instance_ctrl wdt_ctrl;
+	struct st_wdt_cfg wdt_cfg;
+	struct k_mutex inst_lock;
+	atomic_t device_state;
+};
+
+#define WDT_RENESAS_RA_ATOMIC_ENABLE      (0)
+#define WDT_RENESAS_RA_ATOMIC_TIMEOUT_SET (1)
+
+/* Lookup table for WDT period raw cycle */
+const float timeout_period_lut[] = {
+	[WDT_TIMEOUT_128] = 128,    [WDT_TIMEOUT_512] = 512,   [WDT_TIMEOUT_1024] = 1024,
+	[WDT_TIMEOUT_2048] = 2048,  [WDT_TIMEOUT_4096] = 4096, [WDT_TIMEOUT_8192] = 8192,
+	[WDT_TIMEOUT_16384] = 16384};
+
+/* Lookup table for the division value of the input clock count */
+const float clock_div_lut[] = {[WDT_CLOCK_DIVISION_1] = 1,       [WDT_CLOCK_DIVISION_4] = 4,
+			       [WDT_CLOCK_DIVISION_16] = 16,     [WDT_CLOCK_DIVISION_32] = 32,
+			       [WDT_CLOCK_DIVISION_64] = 64,     [WDT_CLOCK_DIVISION_128] = 128,
+			       [WDT_CLOCK_DIVISION_256] = 256,   [WDT_CLOCK_DIVISION_512] = 512,
+			       [WDT_CLOCK_DIVISION_2048] = 2048, [WDT_CLOCK_DIVISION_8192] = 8192};
+
+#define WDT_WINDOW_INVALID (-1)
+
+/* Lookup table for the window start position setting */
+const int window_start_lut[] = {
+	[0] = WDT_WINDOW_START_100, [1] = WDT_WINDOW_START_75, [2] = WDT_WINDOW_START_50,
+	[3] = WDT_WINDOW_START_25,  [4] = WDT_WINDOW_INVALID,
+};
+
+/* Lookup table for the window end position setting */
+const int window_end_lut[] = {
+	[0] = WDT_WINDOW_INVALID, [1] = WDT_WINDOW_END_75, [2] = WDT_WINDOW_END_50,
+	[3] = WDT_WINDOW_END_25,  [4] = WDT_WINDOW_END_0,
+};
+
+static inline void wdt_renesas_ra_inst_lock(const struct device *dev)
+{
+	struct wdt_renesas_ra_data *data = dev->data;
+
+	k_mutex_lock(&data->inst_lock, K_FOREVER);
+}
+
+static inline void wdt_renesas_ra_inst_unlock(const struct device *dev)
+{
+	struct wdt_renesas_ra_data *data = dev->data;
+
+	k_mutex_unlock(&data->inst_lock);
+}
+
+static int wdt_renesas_ra_timeout_calculate(const struct device *dev,
+					    const struct wdt_timeout_cfg *config)
+{
+	struct wdt_renesas_ra_data *data = dev->data;
+	const struct wdt_renesas_ra_config *cfg = dev->config;
+	struct st_wdt_cfg *p_cfg = &data->wdt_cfg;
+	unsigned int window_start_idx;
+	unsigned int window_end_idx;
+	unsigned int best_divisor = WDT_CLOCK_DIVISION_1;
+	unsigned int best_timeout = WDT_TIMEOUT_128;
+	unsigned int best_period_ms = UINT_MAX;
+	unsigned int min_delta = UINT_MAX;
+	uint32_t clock_rate;
+	int ret;
+
+	if (atomic_test_bit(&data->device_state, WDT_RENESAS_RA_ATOMIC_TIMEOUT_SET)) {
+		if (config->window.min != data->timeout.window.min ||
+		    config->window.max != data->timeout.window.max ||
+		    config->flags != data->timeout.flags) {
+			LOG_ERR("wdt support only one timeout setting value");
+			return -EINVAL;
+		}
+
+		data->timeout.callback = config->callback;
+		return 0;
+	}
+
+	ret = clock_control_get_rate(cfg->clock_dev, (clock_control_subsys_t)&cfg->clock_subsys,
+				     &clock_rate);
+	if (unlikely(ret)) {
+		return ret;
+	}
+
+	for (unsigned int divisor = WDT_CLOCK_DIVISION_1; divisor < ARRAY_SIZE(clock_div_lut);
+	     divisor++) {
+		for (unsigned int timeout = WDT_TIMEOUT_128;
+		     timeout < ARRAY_SIZE(timeout_period_lut); timeout++) {
+			unsigned int period_ms =
+				(unsigned int)(1000.0F * clock_div_lut[divisor] *
+					       timeout_period_lut[timeout] / (float)clock_rate);
+			unsigned int delta = period_ms > config->window.max
+						     ? period_ms - config->window.max
+						     : config->window.max - period_ms;
+
+			if (delta < min_delta) {
+				min_delta = delta;
+				best_divisor = divisor;
+				best_timeout = timeout;
+				best_period_ms = period_ms;
+			}
+		}
+	}
+
+	if (min_delta == UINT_MAX) {
+		LOG_ERR("wdt timeout out of range");
+		return -EINVAL;
+	}
+
+	window_start_idx = (config->window.min * 4 + best_period_ms - 1) / best_period_ms;
+	window_end_idx = (config->window.max * 4 + best_period_ms - 1) / best_period_ms;
+
+	if (window_start_lut[window_start_idx] == WDT_WINDOW_INVALID ||
+	    window_end_lut[window_end_idx] == WDT_WINDOW_INVALID) {
+		LOG_ERR("this wdt timeout is not supported");
+		return -ENOTSUP;
+	}
+
+	p_cfg->clock_division = (wdt_clock_division_t)best_divisor;
+	p_cfg->timeout = (wdt_timeout_t)best_timeout;
+	p_cfg->window_start = (wdt_window_start_t)window_start_lut[window_start_idx];
+	p_cfg->window_end = (wdt_window_end_t)window_end_lut[window_end_idx];
+
+	LOG_INF("actual window min = %.2f ms", window_start_idx * best_period_ms * 0.25);
+	LOG_INF("actual window max = %.2f ms", window_end_idx * best_period_ms * 0.25);
+
+	memcpy(&data->timeout, config, sizeof(struct wdt_timeout_cfg));
+
+	return 0;
+}
+
+static int wdt_renesas_ra_setup(const struct device *dev, uint8_t options)
+{
+	struct wdt_renesas_ra_data *data = dev->data;
+	int ret = 0;
+
+	/*
+	 * TODO: WDT must be restarted with wdt_feed call after sleep -> will be added later when PM
+	 * mode is supported
+	 */
+	if ((options & WDT_OPT_PAUSE_IN_SLEEP) != 0) {
+		LOG_ERR("wdt pause in sleep mode not supported");
+		return -ENOTSUP;
+	}
+
+	wdt_renesas_ra_inst_lock(dev);
+
+	if (atomic_test_bit(&data->device_state, WDT_RENESAS_RA_ATOMIC_ENABLE)) {
+		LOG_ERR("wdt has been already setup");
+		ret = -EBUSY;
+		goto end;
+	}
+
+	if (!atomic_test_bit(&data->device_state, WDT_RENESAS_RA_ATOMIC_TIMEOUT_SET)) {
+		LOG_ERR("wdt timeout should be installed before");
+		ret = -EFAULT;
+		goto end;
+	}
+
+	/* Pause watchdog timer when CPU is halted by the debugger. */
+	R_DEBUG->DBGSTOPCR_b.DBGSTOP_WDT = (options & WDT_OPT_PAUSE_HALTED_BY_DBG) != 0 ? 1 : 0;
+
+	if (R_WDT_Open(&data->wdt_ctrl, &data->wdt_cfg) != FSP_SUCCESS) {
+		LOG_ERR("wdt setup failed");
+		ret = -EIO;
+		goto end;
+	}
+
+	if (R_WDT_Refresh(&data->wdt_ctrl) != FSP_SUCCESS) {
+		LOG_ERR("wdt start failed");
+		ret = -EIO;
+		goto end;
+	}
+
+	atomic_set_bit(&data->device_state, WDT_RENESAS_RA_ATOMIC_ENABLE);
+
+end:
+	wdt_renesas_ra_inst_unlock(dev);
+
+	return ret;
+}
+
+static int wdt_renesas_ra_disable(const struct device *dev)
+{
+	struct wdt_renesas_ra_data *data = dev->data;
+
+	if (!atomic_test_bit(&data->device_state, WDT_RENESAS_RA_ATOMIC_ENABLE)) {
+		LOG_ERR("wdt has not been enabled yet");
+		return -EFAULT;
+	}
+
+	LOG_ERR("wdt can not be stopped once it has started");
+	return -EPERM;
+}
+
+#ifdef CONFIG_WDT_RENESAS_RA_NMI
+void wdt_renesas_ra_callback_adapter(wdt_callback_args_t *p_args)
+{
+	const struct device *dev = p_args->p_context;
+	struct wdt_renesas_ra_data *data = dev->data;
+	wdt_callback_t callback = data->timeout.callback;
+
+	if (callback != NULL) {
+		callback(dev, 0);
+	}
+}
+#endif /* CONFIG_WDT_RENESAS_RA_NMI */
+
+#define WDT_RENESAS_RA_SUPPORTED_FLAGS (WDT_FLAG_RESET_NONE | WDT_FLAG_RESET_SOC)
+
+static int wdt_renesas_ra_install_timeout(const struct device *dev,
+					  const struct wdt_timeout_cfg *config)
+{
+	struct wdt_renesas_ra_data *data = dev->data;
+	struct st_wdt_cfg *p_config = &data->wdt_cfg;
+	int ret = 0;
+
+	if (config->window.min > config->window.max || config->window.max == 0) {
+		return -EINVAL;
+	}
+
+	if ((config->flags & ~WDT_RENESAS_RA_SUPPORTED_FLAGS) != 0) {
+		return -ENOTSUP;
+	}
+
+	if (config->callback == NULL && (config->flags & WDT_FLAG_RESET_MASK) == 0) {
+		LOG_ERR("no timeout response was chosen");
+		return -EINVAL;
+	}
+
+	if (config->callback != NULL && (config->flags & WDT_FLAG_RESET_MASK) != 0) {
+		LOG_ERR("WDT_FLAG_RESET_NONE should be chosen in case of interrupt response");
+		return -ENOTSUP;
+	}
+
+	wdt_renesas_ra_inst_lock(dev);
+
+	if (atomic_test_bit(&data->device_state, WDT_RENESAS_RA_ATOMIC_ENABLE)) {
+		LOG_ERR("cannot change timeout settings after wdt setup");
+		ret = -EBUSY;
+		goto end;
+	}
+
+#ifndef CONFIG_WDT_RENESAS_RA_NMI
+	if (config->callback != NULL) {
+		LOG_ERR("interrupt response only available in case CONFIG_WDT_RENESAS_RA_NMI=y");
+		ret = -ENOTSUP;
+		goto end;
+	}
+#else
+	p_config->reset_control = (config->flags & WDT_FLAG_RESET_MASK) != 0
+					  ? WDT_RESET_CONTROL_RESET
+					  : WDT_RESET_CONTROL_NMI;
+#endif
+
+	ret = wdt_renesas_ra_timeout_calculate(dev, config);
+	if (ret < 0) {
+		goto end;
+	}
+
+	atomic_set_bit(&data->device_state, WDT_RENESAS_RA_ATOMIC_TIMEOUT_SET);
+	LOG_INF("wdt timeout was set successfully");
+
+end:
+	wdt_renesas_ra_inst_unlock(dev);
+
+	return ret;
+}
+
+static int wdt_renesas_ra_feed(const struct device *dev, int channel_id)
+{
+	struct wdt_renesas_ra_data *data = dev->data;
+
+	if (!atomic_test_bit(&data->device_state, WDT_RENESAS_RA_ATOMIC_ENABLE) ||
+	    channel_id != 0) {
+		return -EINVAL;
+	}
+
+	if (R_WDT_Refresh(&data->wdt_ctrl) != FSP_SUCCESS) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static DEVICE_API(wdt, wdt_renesas_ra_api) = {
+	.setup = wdt_renesas_ra_setup,
+	.disable = wdt_renesas_ra_disable,
+	.install_timeout = wdt_renesas_ra_install_timeout,
+	.feed = wdt_renesas_ra_feed,
+};
+
+#define WDT_RENESAS_RA_DEFINE(id)                                                                  \
+	static struct wdt_renesas_ra_config wdt_renesas_ra_cfg##id = {                             \
+		.clock_dev = DEVICE_DT_GET(DT_CLOCKS_CTLR(id)),                                    \
+		.clock_subsys = {.mstp = DT_CLOCKS_CELL(id, mstp),                                 \
+				 .stop_bit = DT_CLOCKS_CELL(id, stop_bit)},                        \
+	};                                                                                         \
+                                                                                                   \
+	static struct wdt_renesas_ra_data wdt_renesas_ra_data##id = {                              \
+		.device_state = ATOMIC_INIT(0),                                                    \
+		.wdt_cfg = {.stop_control = WDT_STOP_CONTROL_DISABLE,                              \
+			    .reset_control = WDT_RESET_CONTROL_RESET,                              \
+			    .p_callback = wdt_renesas_ra_callback_adapter,                         \
+			    .p_context = DEVICE_DT_GET(id)},                                       \
+	};                                                                                         \
+                                                                                                   \
+	DEVICE_DT_DEFINE(id, NULL, NULL, &wdt_renesas_ra_data##id, &wdt_renesas_ra_cfg##id,        \
+			 POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, &wdt_renesas_ra_api);
+
+DT_FOREACH_STATUS_OKAY(renesas_ra_wdt, WDT_RENESAS_RA_DEFINE)
diff --git a/drivers/watchdog/wdt_rts5912.c b/drivers/watchdog/wdt_rts5912.c
new file mode 100644
index 00000000000..c030a95b049
--- /dev/null
+++ b/drivers/watchdog/wdt_rts5912.c
@@ -0,0 +1,247 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 Realtek Semiconductor Corporation, SIBG-SD7, Dylan Hsieh
+ */
+
+#define DT_DRV_COMPAT realtek_rts5912_watchdog
+
+#include <soc.h>
+#include <errno.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/watchdog.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/clock_control_rts5912.h>
+#include <zephyr/irq.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(wdt_rts5912, CONFIG_WDT_LOG_LEVEL);
+
+#include "reg/reg_wdt.h"
+
+#define WDT_MAX_CNT   256
+#define WDT_CLK_CYCLE 32768UL
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) == 1, "multiple instances not supported");
+
+struct wdt_rts5912_config {
+	uint32_t base;
+	uint32_t div;
+	const struct device *clk_dev;
+	uint32_t clk_grp;
+	uint32_t clk_idx;
+};
+
+struct wdt_rts5912_data {
+	wdt_callback_t callback;
+	bool timeout_installed;
+	uint32_t timeout;
+};
+
+static void wdt_rts5912_isr(const struct device *dev)
+{
+	const struct wdt_rts5912_config *const cfg = dev->config;
+	struct wdt_rts5912_data *data = dev->data;
+	WDT_Type *wdt_reg = (WDT_Type *)cfg->base;
+
+	LOG_DBG("WDT ISR");
+
+	wdt_reg->CTRL |= WDT_CTRL_CLRRSTFLAG;
+
+	if (data->callback) {
+		data->callback(dev, 0);
+	}
+}
+
+static int wdt_rts5912_setup(const struct device *dev, uint8_t options)
+{
+	const struct wdt_rts5912_config *const config = dev->config;
+	struct wdt_rts5912_data *data = dev->data;
+	WDT_Type *wdt_reg = (WDT_Type *)config->base;
+
+	if (!data->timeout_installed) {
+		LOG_ERR("No valid WDT timeout installed");
+		return -EINVAL;
+	}
+
+	if (wdt_reg->CTRL & WDT_CTRL_EN) {
+		LOG_ERR("WDT is already running");
+		return -EBUSY;
+	}
+
+	if (options & WDT_OPT_PAUSE_IN_SLEEP) {
+		LOG_ERR("WDT_OPT_PAUSE_IN_SLEEP is not supported");
+		return -ENOTSUP;
+	}
+
+	if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
+		LOG_ERR("Pause when halted by debugger not supported");
+		return -ENOTSUP;
+	}
+
+	irq_enable(DT_INST_IRQN(0));
+
+	wdt_reg->INTEN = WDT_INTEN_WDTINTEN;
+	wdt_reg->CTRL |= (WDT_CTRL_CLRRSTFLAG | WDT_CTRL_RELOAD);
+	wdt_reg->CTRL |= WDT_CTRL_EN;
+
+	LOG_DBG("WDT setup and enabled");
+
+	return 0;
+}
+
+static int wdt_rts5912_disable(const struct device *dev)
+{
+	const struct wdt_rts5912_config *const config = dev->config;
+	struct wdt_rts5912_data *data = dev->data;
+	WDT_Type *wdt_reg = (WDT_Type *)config->base;
+
+	if (!(wdt_reg->CTRL & WDT_CTRL_EN)) {
+		return -EALREADY;
+	}
+
+	wdt_reg->INTEN = 0ul;
+	wdt_reg->CTRL |= WDT_CTRL_CLRRSTFLAG;
+	wdt_reg->CTRL &= ~WDT_CTRL_EN;
+
+	data->timeout_installed = false;
+
+	LOG_DBG("WDT disabled");
+
+	return 0;
+}
+
+static int wdt_rts5912_install_timeout(const struct device *dev,
+				       const struct wdt_timeout_cfg *config)
+{
+	const struct wdt_rts5912_config *const cfg = dev->config;
+	struct wdt_rts5912_data *data = dev->data;
+	WDT_Type *wdt_reg = (WDT_Type *)cfg->base;
+
+	uint32_t timeout;
+	uint32_t max, min;
+
+	LOG_DBG("WDT intstall timeout");
+
+	if (wdt_reg->CTRL & WDT_CTRL_EN) {
+		LOG_ERR("WDT is already running");
+		return -EBUSY;
+	}
+
+	if (config->window.min > 0U) {
+		LOG_ERR("Lower limit of watchdog is not supported, keep it zero");
+		data->timeout_installed = false;
+		return -EINVAL;
+	}
+
+	switch (config->flags) {
+	case WDT_FLAG_RESET_SOC:
+		wdt_reg->CTRL |= WDT_CTRL_RSTEN;
+		break;
+	case WDT_FLAG_RESET_NONE:
+		wdt_reg->CTRL &= ~WDT_CTRL_RSTEN;
+		break;
+	case WDT_FLAG_RESET_CPU_CORE:
+		LOG_ERR("WDT_FLAG_RESET_CPU_CORE is not supported\n");
+		break;
+	default:
+		LOG_ERR("Unsupported watchdog config Flag\n");
+		return -ENOTSUP;
+	}
+
+	timeout = config->window.max * 1000U;
+	min = (cfg->div * USEC_PER_SEC) / WDT_CLK_CYCLE;
+	max = min * WDT_MAX_CNT;
+
+	if ((timeout < min) || (timeout > max)) {
+		LOG_ERR("Invalid timeout value allowed range:"
+			"%d ms to %d ms",
+			min / MSEC_PER_SEC, max / MSEC_PER_SEC);
+		return -EINVAL;
+	}
+
+	wdt_reg->CNT = timeout / min;
+
+	data->callback = config->callback;
+	data->timeout_installed = true;
+
+	LOG_DBG("DIV: 0x%08x, CNT: 0x%08x", wdt_reg->DIV, wdt_reg->CNT);
+
+	return 0;
+}
+
+static int wdt_rts5912_feed(const struct device *dev, int channel_id)
+{
+	const struct wdt_rts5912_config *const cfg = dev->config;
+	WDT_Type *wdt_reg = (WDT_Type *)cfg->base;
+
+	ARG_UNUSED(dev);
+	ARG_UNUSED(channel_id);
+
+	if (!(wdt_reg->CTRL & WDT_CTRL_EN)) {
+		return -EINVAL;
+	}
+
+	wdt_reg->CTRL |= WDT_CTRL_RELOAD;
+
+	LOG_DBG("WDT feed");
+
+	return 0;
+}
+
+static DEVICE_API(wdt, wdt_rts5912_api) = {
+	.setup = wdt_rts5912_setup,
+	.disable = wdt_rts5912_disable,
+	.install_timeout = wdt_rts5912_install_timeout,
+	.feed = wdt_rts5912_feed,
+};
+
+static int wdt_rts5912_init(const struct device *dev)
+{
+	int rc;
+
+	const struct wdt_rts5912_config *const cfg = dev->config;
+	struct rts5912_sccon_subsys sccon;
+	WDT_Type *wdt_reg = (WDT_Type *)cfg->base;
+
+	LOG_DBG("WDT init");
+
+	if (!device_is_ready(cfg->clk_dev)) {
+		return -ENODEV;
+	}
+
+	sccon.clk_grp = cfg->clk_grp;
+	sccon.clk_idx = cfg->clk_idx;
+	rc = clock_control_on(cfg->clk_dev, (clock_control_subsys_t)&sccon);
+	if (rc != 0) {
+		return rc;
+	}
+
+	if (IS_ENABLED(CONFIG_WDT_DISABLE_AT_BOOT)) {
+		wdt_rts5912_disable(dev);
+	}
+
+	wdt_reg->CTRL = 0ul;
+	wdt_reg->DIV = cfg->div;
+
+	wdt_reg->CTRL |= WDT_CTRL_CLRRSTFLAG;
+	NVIC_ClearPendingIRQ(DT_INST_IRQN(0));
+
+	IRQ_CONNECT(DT_INST_IRQN(0), 0, wdt_rts5912_isr, DEVICE_DT_INST_GET(0), 0);
+	irq_enable(DT_INST_IRQN(0));
+
+	return 0;
+}
+
+static const struct wdt_rts5912_config wdt_rts5912_cfg = {
+	.base = DT_INST_REG_ADDR(0),
+	.div = DT_INST_PROP(0, clk_divider),
+	.clk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(0)),
+	.clk_grp = DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(wdog), watchdog, clk_grp),
+	.clk_idx = DT_CLOCKS_CELL_BY_NAME(DT_NODELABEL(wdog), watchdog, clk_idx),
+};
+
+static struct wdt_rts5912_data wdt_rts5912_dev_data;
+
+DEVICE_DT_INST_DEFINE(0, wdt_rts5912_init, NULL, &wdt_rts5912_dev_data, &wdt_rts5912_cfg,
+		      PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &wdt_rts5912_api);
diff --git a/drivers/watchdog/wdt_sam4l.c b/drivers/watchdog/wdt_sam4l.c
new file mode 100644
index 00000000000..22eab06f155
--- /dev/null
+++ b/drivers/watchdog/wdt_sam4l.c
@@ -0,0 +1,346 @@
+/*
+ * Copyright (C) 2024-2025, Gerson Fernando Budke <nandojve@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT atmel_sam4l_watchdog
+
+/**
+ * @brief Watchdog (WDT) Driver for Atmel SAM4L MCUs
+ *
+ * Note:
+ * - SAM4L watchdog has a fuse bit to automatically enable the watchdog at boot.
+ *   It should be enabled to keep compatibility with SAM family.
+ * - Since the MCU boots with WDT enabled, the CONFIG_WDT_DISABLE_AT_BOOT
+ *   is set default at boot and watchdog module is disabled in the MCU for
+ *   systems that don't need watchdog functionality.
+ * - If the application needs to use the watchdog in the system, then
+ *   CONFIG_WDT_DISABLE_AT_BOOT must be unset in the app's config file
+ */
+
+#include <zephyr/drivers/watchdog.h>
+#include <zephyr/drivers/clock_control/atmel_sam_pmc.h>
+#include <zephyr/irq.h>
+#include <soc.h>
+
+#define LOG_LEVEL CONFIG_WDT_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(wdt_sam4l);
+
+#define WDT_FIRST_KEY		  0x55ul
+#define WDT_SECOND_KEY		  0xAAul
+
+enum wdt_sam4l_clock_src {
+	WDT_SAM4L_CLK_SRC_RCSYS   = 0,
+	WDT_SAM4L_CLK_SRC_OSC32K  = 1,
+};
+
+struct wdt_sam4l_dev_cfg {
+	Wdt *regs;
+	void (*irq_cfg_func)(const struct device *dev);
+	const struct atmel_sam_pmc_config clock_cfg;
+	enum wdt_sam4l_clock_src clock_src;
+	bool lock;
+};
+
+struct wdt_sam4l_dev_data {
+	wdt_callback_t cb;
+	uint32_t flags;
+};
+
+/**
+ * @brief Sets the Watchdog Timer Control register to the @a ctrl value.
+ *
+ * @param ctrl  Value to set the WatchDog Timer Control register to.
+ */
+static void wdt_sam4l_set_ctrl(const struct wdt_sam4l_dev_cfg *cfg,
+			       const uint32_t ctrl)
+{
+	Wdt *const wdt = cfg->regs;
+	volatile uint32_t delay;
+
+	/* Calculate delay for internal synchronization, see 45.1.3 WDT errata */
+	if (cfg->clock_src == WDT_SAM4L_CLK_SRC_OSC32K) {
+		delay = DIV_ROUND_UP(SOC_ATMEL_SAM_MCK_FREQ_HZ * 2, SOC_ATMEL_SAM_RC32K_NOMINAL_HZ);
+	} else {
+		delay = DIV_ROUND_UP(SOC_ATMEL_SAM_MCK_FREQ_HZ * 2, SOC_ATMEL_SAM_RCSYS_NOMINAL_HZ);
+	}
+	/* ~8 cycles for one while loop */
+	delay >>= 3;
+	while (delay--) {
+	}
+	wdt->CTRL = WDT_CTRL_KEY(WDT_FIRST_KEY)
+		  | ctrl;
+	wdt->CTRL = WDT_CTRL_KEY(WDT_SECOND_KEY)
+		  | ctrl;
+}
+
+/**
+ * @brief Calculate timeout scale factor based on a input in milliseconds
+ *
+ * timeout(ms) = (2pow(scale + 1) * 1000) / wdt_clk
+ *
+ * @param cfg  Configuration
+ * @param time Timeout value in milliseconds
+ */
+static int wdt_sam4l_calc_timeout(const struct wdt_sam4l_dev_cfg *cfg,
+				  uint32_t time)
+{
+	uint32_t wdt_clk = cfg->clock_src == WDT_SAM4L_CLK_SRC_OSC32K
+			 ? SOC_ATMEL_SAM_RC32K_NOMINAL_HZ
+			 : SOC_ATMEL_SAM_RCSYS_NOMINAL_HZ;
+
+	for (int scale = 7; scale <= 31; ++scale) {
+		uint32_t timeout = (BIT64(scale + 1) * 1000ull) / wdt_clk;
+
+		if (time <= timeout) {
+			return scale;
+		}
+	}
+
+	return -EINVAL;
+}
+
+/**
+ * @brief Calculate both the Banned and Prescale Select timeout to be installed
+ * in the watchdog timer.
+ *
+ * The config->min value will define the banned timeout. The prescaler timeout
+ * then should be defined by the interval of (config->max - config-min).
+ *
+ * @param config Timeout Window configuration value in milliseconds.
+ * @param tban   Pointer to the banned timeout
+ * @param psel   Pointer to the timeout perscaller selection
+ */
+static int wdt_sam4l_convert_timeout(const struct wdt_sam4l_dev_cfg *cfg,
+				     const struct wdt_timeout_cfg *config,
+				     uint32_t *tban, uint32_t *psel)
+{
+	int scale;
+
+	if (config->window.max < config->window.min || config->window.max == 0) {
+		LOG_ERR("The watchdog window should have a valid period");
+		return -EINVAL;
+	}
+
+	scale = wdt_sam4l_calc_timeout(cfg, config->window.min);
+	if (scale < 0) {
+		LOG_ERR("Window minimal value is too big");
+		return -EINVAL;
+	}
+	*tban = scale;
+
+	scale = wdt_sam4l_calc_timeout(cfg, config->window.max - config->window.min);
+	if (scale < 0) {
+		LOG_ERR("Window maximal value is too big");
+		return -EINVAL;
+	}
+	*psel = scale;
+
+	return 0;
+}
+
+static int wdt_sam4l_setup(const struct device *dev, uint8_t options)
+{
+	const struct wdt_sam4l_dev_cfg *cfg = dev->config;
+	Wdt *const wdt = cfg->regs;
+	volatile uint32_t reg;
+
+	if (options & WDT_OPT_PAUSE_IN_SLEEP) {
+		LOG_ERR("Pause in Sleep is an invalid option");
+		return -ENOTSUP;
+	}
+
+	if (options & WDT_OPT_PAUSE_HALTED_BY_DBG) {
+		LOG_ERR("Pause on CPU halted by debug is an invalid option");
+		return -ENOTSUP;
+	}
+
+	reg = wdt->CTRL;
+
+	if (reg & WDT_CTRL_EN) {
+		LOG_ERR("Watchdog is running and can not be changed");
+		return -EPERM;
+	}
+
+	if (reg & WDT_CTRL_SFV) {
+		LOG_ERR("Watchdog is locked and can not be changed");
+		return -EPERM;
+	}
+
+	if (!(reg & WDT_CTRL_PSEL_Msk)) {
+		LOG_ERR("No valid timeouts installed");
+		return -EINVAL;
+	}
+
+	reg = wdt->CTRL
+	    | (cfg->lock ? WDT_CTRL_SFV : 0)
+	    | WDT_CTRL_EN;
+
+	wdt_sam4l_set_ctrl(cfg, reg);
+	while ((wdt->CTRL & WDT_CTRL_EN) != WDT_CTRL_EN) {
+	}
+
+	return 0;
+}
+
+static int wdt_sam4l_disable(const struct device *dev)
+{
+	const struct wdt_sam4l_dev_cfg *cfg = dev->config;
+	Wdt *const wdt = cfg->regs;
+
+	if (wdt->CTRL & WDT_CTRL_SFV) {
+		LOG_ERR("Watchdog is already locked");
+		return -EPERM;
+	}
+
+	wdt_sam4l_set_ctrl(cfg, wdt->CTRL & ~WDT_CTRL_EN);
+	while (wdt->CTRL & WDT_CTRL_EN) {
+	}
+
+	wdt_sam4l_set_ctrl(cfg, wdt->CTRL & ~WDT_CTRL_CEN);
+	while (wdt->CTRL & WDT_CTRL_CEN) {
+	}
+
+	return 0;
+}
+
+static int wdt_sam4l_install_timeout(const struct device *dev,
+				     const struct wdt_timeout_cfg *config)
+{
+	const struct wdt_sam4l_dev_cfg *cfg = dev->config;
+	struct wdt_sam4l_dev_data *const data = dev->data;
+	Wdt *const wdt = cfg->regs;
+	volatile uint32_t reg;
+	uint32_t tban, psel;
+
+	if (wdt->CTRL & WDT_CTRL_MODE) {
+		LOG_ERR("No more timeouts can be installed");
+		return -ENOMEM;
+	}
+
+	if (config->flags & WDT_FLAG_RESET_CPU_CORE) {
+		LOG_ERR("The SAM4L watchdog does not support reset CPU core");
+		return -ENOTSUP;
+	}
+
+	if (wdt_sam4l_convert_timeout(cfg, config, &tban, &psel)) {
+		return -EINVAL;
+	}
+
+	reg = wdt->CTRL;
+
+	if (reg & WDT_CTRL_EN) {
+		LOG_ERR("Watchdog is running and can not be changed");
+		return -EPERM;
+	}
+
+	if (reg & WDT_CTRL_SFV) {
+		LOG_ERR("Watchdog is locked and can not be changed");
+		return -EPERM;
+	}
+
+	data->cb = config->callback;
+	data->flags = config->flags;
+	reg = (cfg->clock_src == WDT_SAM4L_CLK_SRC_OSC32K ? WDT_CTRL_CSSEL : 0)
+	    | (config->callback ? WDT_CTRL_IM : 0)
+	    | (config->window.min ? WDT_CTRL_MODE : 0)
+	    | (config->window.min ? WDT_CTRL_TBAN(tban) : 0)
+	    | WDT_CTRL_PSEL(psel);
+	wdt_sam4l_set_ctrl(cfg, reg);
+
+	wdt_sam4l_set_ctrl(cfg, wdt->CTRL | WDT_CTRL_CEN);
+	while (!(wdt->CTRL & WDT_CTRL_CEN)) {
+	}
+
+	return 0;
+}
+
+static int wdt_sam4l_feed(const struct device *dev, int channel_id)
+{
+	const struct wdt_sam4l_dev_cfg *cfg = dev->config;
+	Wdt *const wdt = cfg->regs;
+
+	ARG_UNUSED(channel_id);
+
+	while ((wdt->SR & WDT_SR_CLEARED) != WDT_SR_CLEARED) {
+	}
+	wdt->CLR = WDT_CLR_WDTCLR
+		 | WDT_CLR_KEY(WDT_FIRST_KEY);
+	wdt->CLR = WDT_CLR_WDTCLR
+		 | WDT_CLR_KEY(WDT_SECOND_KEY);
+
+	return 0;
+}
+
+/* If the callback blocks or ISR do not clear flags the system will trigger a
+ * CPU reset on the next watchdog timeout, see 20.5.3 Interrupt Mode
+ */
+static void wdt_sam4l_isr(const struct device *dev)
+{
+	const struct wdt_sam4l_dev_cfg *cfg = dev->config;
+	struct wdt_sam4l_dev_data *const data = dev->data;
+	Wdt *const wdt = cfg->regs;
+
+	wdt->ICR = WDT_ICR_WINT;
+	data->cb(dev, 0);
+}
+
+static DEVICE_API(wdt, wdt_sam4l_driver_api) = {
+	.setup = wdt_sam4l_setup,
+	.disable = wdt_sam4l_disable,
+	.install_timeout = wdt_sam4l_install_timeout,
+	.feed = wdt_sam4l_feed,
+};
+
+static int wdt_sam4l_init(const struct device *dev)
+{
+	const struct wdt_sam4l_dev_cfg *const cfg = dev->config;
+	Wdt *const wdt = cfg->regs;
+
+	/* Enable WDT clock in PMC */
+	(void)clock_control_on(SAM_DT_PMC_CONTROLLER,
+			       (clock_control_subsys_t)&cfg->clock_cfg);
+
+	if (IS_ENABLED(CONFIG_WDT_DISABLE_AT_BOOT)) {
+		wdt_sam4l_disable(dev);
+		return 0;
+	}
+
+	wdt->IDR = WDT_IDR_MASK;
+	cfg->irq_cfg_func(dev);
+	wdt->IER = WDT_IER_WINT;
+
+	return 0;
+}
+
+#define WDT_SAM4L_INIT(n)						\
+	static void wdt##n##_sam4l_irq_cfg(const struct device *dev)	\
+	{								\
+		IRQ_CONNECT(DT_INST_IRQN(n),				\
+			    DT_INST_IRQ(n, priority),			\
+			    wdt_sam4l_isr,				\
+			    DEVICE_DT_INST_GET(n), 0);			\
+		irq_enable(DT_INST_IRQN(n));				\
+	}								\
+									\
+	static const struct wdt_sam4l_dev_cfg wdt##n##_sam4l_cfg = {	\
+		.regs = (Wdt *)DT_INST_REG_ADDR(n),			\
+		.irq_cfg_func = wdt##n##_sam4l_irq_cfg,			\
+		.clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(n),		\
+		.clock_src = DT_INST_ENUM_IDX(n, clk_source),		\
+		.lock = DT_INST_PROP(n, lock_mode),			\
+	};								\
+									\
+	static struct wdt_sam4l_dev_data wdt##n##_sam4l_data;		\
+									\
+	DEVICE_DT_INST_DEFINE(n, wdt_sam4l_init,			\
+			    NULL,					\
+			    &wdt##n##_sam4l_data,			\
+			    &wdt##n##_sam4l_cfg,			\
+			    PRE_KERNEL_1,				\
+			    CONFIG_KERNEL_INIT_PRIORITY_DEVICE,		\
+			    &wdt_sam4l_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(WDT_SAM4L_INIT)
diff --git a/drivers/watchdog/wdt_shell.c b/drivers/watchdog/wdt_shell.c
index 83889f692d5..f0433205264 100644
--- a/drivers/watchdog/wdt_shell.c
+++ b/drivers/watchdog/wdt_shell.c
@@ -160,10 +160,15 @@ static int cmd_feed(const struct shell *sh, size_t argc, char *argv[])
 	return wdt_feed(dev, channel_id);
 }
 
+static bool device_is_wdt(const struct device *dev)
+{
+	return DEVICE_API_IS(wdt, dev);
+}
+
 /* Device name autocompletion support */
 static void device_name_get(size_t idx, struct shell_static_entry *entry)
 {
-	const struct device *dev = shell_device_lookup(idx, NULL);
+	const struct device *dev = shell_device_filter(idx, device_is_wdt);
 
 	entry->syntax = (dev != NULL) ? dev->name : NULL;
 	entry->handler = NULL;
diff --git a/drivers/watchdog/wdt_silabs_siwx91x.c b/drivers/watchdog/wdt_silabs_siwx91x.c
new file mode 100644
index 00000000000..4da0813ed5c
--- /dev/null
+++ b/drivers/watchdog/wdt_silabs_siwx91x.c
@@ -0,0 +1,270 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <zephyr/irq.h>
+#include <zephyr/types.h>
+#include <zephyr/device.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/bitarray.h>
+#include <zephyr/drivers/watchdog.h>
+#include <zephyr/drivers/clock_control.h>
+#include <math.h>
+#include "rsi_wwdt.h"
+#include "rsi_sysrtc.h"
+
+#define DT_DRV_COMPAT                       silabs_siwx91x_wdt
+#define SIWX91X_WDT_SYSTEM_RESET_TIMER_MASK 0x0000001F
+
+struct siwx91x_wdt_config {
+	/* WDT register base address */
+	MCU_WDT_Type *reg;
+	/* Pointer to the clock device structure */
+	const struct device *clock_dev;
+	/* Clock control subsystem */
+	clock_control_subsys_t clock_subsys;
+	/* Function pointer for the IRQ (Interrupt Request) configuration */
+	void (*irq_config)(void);
+};
+
+struct siwx91x_wdt_data {
+	/* Callback function to be called on watchdog timer events */
+	wdt_callback_t callback;
+	/* WDT operating clock (LF-FSM) frequency */
+	uint32_t clock_frequency;
+	/* Timer system reset duration in ms */
+	uint8_t delay_reset;
+	/* Timer interrupt duration in ms */
+	uint8_t delay_irq;
+	/* Flag indicating the timeout install status */
+	bool timeout_install_status;
+	/* Flag indicating the setup status */
+	bool setup_status;
+};
+
+/* Function to get the delay in milliseconds from the register value */
+static uint32_t siwx91x_wdt_delay_from_hw(uint8_t value, int clock_frequency)
+{
+	uint32_t ticks = BIT(value);
+	float timeout = (float)ticks / clock_frequency;
+
+	timeout *= 1000;
+	/* Return the timeout value as an unsigned 32-bit integer in milliseconds */
+	return (uint32_t)timeout;
+}
+
+/* Function to get the register value from the delay in milliseconds */
+static uint8_t siwx91x_wdt_delay_to_hw(uint32_t delay, int clock_frequency)
+{
+	/* reg_value = log((timeout * clock_frequency)/1000)base2 */
+	float value = ((float)delay * (float)clock_frequency) / 1000;
+	float result = log2f(value);
+
+	/* Round the result to nearest integer */
+	result = roundf(result);
+
+	return (uint8_t)result;
+}
+
+static int siwx91x_wdt_install_timeout(const struct device *dev, const struct wdt_timeout_cfg *cfg)
+{
+	struct siwx91x_wdt_data *data = dev->data;
+
+	/* Check the WDT setup status */
+	if (data->setup_status) {
+		/* WDT setup is already done */
+		return -EBUSY;
+	}
+
+	/* Check the WDT timeout  status */
+	if (data->timeout_install_status) {
+		/* Only single timeout can be installed */
+		return -ENOMEM;
+	}
+
+	if (cfg->window.max > siwx91x_wdt_delay_from_hw(SIWX91X_WDT_SYSTEM_RESET_TIMER_MASK,
+							data->clock_frequency) ||
+	    cfg->window.max == 0) {
+		/* Requested value is out of range */
+		return -EINVAL;
+	}
+
+	if (cfg->window.min > 0) {
+		/* This feature is currently not supported */
+		return -ENOTSUP;
+	}
+
+	switch (cfg->flags) {
+	case WDT_FLAG_RESET_SOC:
+	case WDT_FLAG_RESET_CPU_CORE:
+		if (cfg->callback != NULL) {
+			/* Callback is not supported for reset flags */
+			return -ENOTSUP;
+		}
+		data->delay_reset = siwx91x_wdt_delay_to_hw(cfg->window.max, data->clock_frequency);
+		/* During a system or CPU core reset, interrupts are not needed. Thus, we set
+		 * the interrupt time to 0 to ensure no interrupts occur while resetting.
+		 */
+		data->delay_irq = 0;
+		/* Mask the WWDT interrupt */
+		RSI_WWDT_IntrMask();
+		break;
+
+	case WDT_FLAG_RESET_NONE:
+		/* Set the reset time to maximum value */
+		data->delay_reset = SIWX91X_WDT_SYSTEM_RESET_TIMER_MASK;
+		data->delay_irq = siwx91x_wdt_delay_to_hw(cfg->window.max, data->clock_frequency);
+		if (cfg->callback != NULL) {
+			data->callback = cfg->callback;
+		}
+		break;
+
+	default:
+		/* Unsupported WDT config options */
+		return -ENOTSUP;
+	}
+
+	data->timeout_install_status = true;
+	return 0;
+}
+
+/* Function to setup and start WDT */
+static int siwx91x_wdt_setup(const struct device *dev, uint8_t options)
+{
+	const struct siwx91x_wdt_config *config = dev->config;
+	struct siwx91x_wdt_data *data = dev->data;
+
+	/* Check the WDT setup status */
+	if (data->setup_status) {
+		/* WDT is already running */
+		return -EBUSY;
+	}
+
+	/* Check the WDT timeout  status */
+	if (!data->timeout_install_status) {
+		/* Timeout need to be set before setup */
+		return -ENOTSUP;
+	}
+
+	if (options & (WDT_OPT_PAUSE_IN_SLEEP)) {
+		return -ENOTSUP;
+	}
+
+	RSI_WWDT_ConfigSysRstTimer(config->reg, data->delay_reset);
+	RSI_WWDT_ConfigIntrTimer(config->reg, data->delay_irq);
+
+	RSI_WWDT_Start(config->reg);
+
+	data->setup_status = true;
+
+	return 0;
+}
+
+static int siwx91x_wdt_disable(const struct device *dev)
+{
+	const struct siwx91x_wdt_config *config = dev->config;
+	struct siwx91x_wdt_data *data = dev->data;
+
+	if (!data->timeout_install_status) {
+		/* No timeout installed */
+		return -EFAULT;
+	}
+
+	RSI_WWDT_Disable(config->reg);
+
+	data->timeout_install_status = false;
+	data->setup_status = false;
+
+	return 0;
+}
+
+static int siwx91x_wdt_feed(const struct device *dev, int channel_id)
+{
+	const struct siwx91x_wdt_config *config = dev->config;
+	struct siwx91x_wdt_data *data = dev->data;
+
+	if (!(data->timeout_install_status && data->setup_status)) {
+		/* WDT is not configured */
+		return -EINVAL;
+	}
+
+	if (channel_id != 0) {
+		/* Channel id must be 0 */
+		return -EINVAL;
+	}
+
+	RSI_WWDT_ReStart(config->reg);
+	return 0;
+}
+
+static void siwx91x_wdt_isr(const struct device *dev)
+{
+	const struct siwx91x_wdt_config *config = dev->config;
+	struct siwx91x_wdt_data *data = dev->data;
+
+	/* Clear WDT interrupt */
+	RSI_WWDT_IntrClear();
+
+	if (data->delay_irq) {
+		/* Restart the timer */
+		RSI_WWDT_ReStart(config->reg);
+	}
+
+	if (data->callback != NULL) {
+		data->callback(dev, 0);
+	}
+}
+
+static int siwx91x_wdt_init(const struct device *dev)
+{
+	const struct siwx91x_wdt_config *config = dev->config;
+	struct siwx91x_wdt_data *data = dev->data;
+	int ret;
+
+	ret = clock_control_on(config->clock_dev, config->clock_subsys);
+	if (ret) {
+		return ret;
+	}
+	ret = clock_control_get_rate(config->clock_dev, config->clock_subsys,
+				     &data->clock_frequency);
+	if (ret) {
+		return ret;
+	}
+
+	RSI_WWDT_Init(config->reg);
+
+	config->irq_config();
+	RSI_WWDT_IntrUnMask();
+
+	return 0;
+}
+
+static DEVICE_API(wdt, siwx91x_wdt_driver_api) = {
+	.setup = siwx91x_wdt_setup,
+	.disable = siwx91x_wdt_disable,
+	.install_timeout = siwx91x_wdt_install_timeout,
+	.feed = siwx91x_wdt_feed,
+};
+
+#define siwx91x_WDT_INIT(inst)                                                                     \
+	static struct siwx91x_wdt_data siwx91x_wdt_data_##inst;                                    \
+	static void siwx91x_wdt_irq_configure_##inst(void)                                         \
+	{                                                                                          \
+		IRQ_CONNECT(DT_INST_IRQ(inst, irq), DT_INST_IRQ(inst, priority), siwx91x_wdt_isr,  \
+			    DEVICE_DT_INST_GET(inst), 0);                                          \
+		irq_enable(DT_INST_IRQ(inst, irq));                                                \
+	}                                                                                          \
+	static const struct siwx91x_wdt_config siwx91x_wdt_config_##inst = {                       \
+		.reg = (MCU_WDT_Type *)DT_INST_REG_ADDR(inst),                                     \
+		.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(inst)),                             \
+		.clock_subsys = (clock_control_subsys_t)DT_INST_PHA(inst, clocks, clkid),          \
+		.irq_config = siwx91x_wdt_irq_configure_##inst,                                    \
+	};                                                                                         \
+	DEVICE_DT_INST_DEFINE(inst, &siwx91x_wdt_init, NULL, &siwx91x_wdt_data_##inst,             \
+			      &siwx91x_wdt_config_##inst, PRE_KERNEL_1,                            \
+			      CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &siwx91x_wdt_driver_api);
+
+DT_INST_FOREACH_STATUS_OKAY(siwx91x_WDT_INIT)
diff --git a/drivers/watchdog/xt_wdt_esp32.c b/drivers/watchdog/xt_wdt_esp32.c
index 3c6fd8ef510..29b75552187 100644
--- a/drivers/watchdog/xt_wdt_esp32.c
+++ b/drivers/watchdog/xt_wdt_esp32.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -14,22 +14,12 @@
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/drivers/clock_control/esp32_clock_control.h>
 
-#ifndef CONFIG_SOC_SERIES_ESP32C3
 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
-#else
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-#endif
 #include <zephyr/device.h>
 #include <zephyr/logging/log.h>
 
 LOG_MODULE_REGISTER(xt_wdt_esp32, CONFIG_WDT_LOG_LEVEL);
 
-#ifdef CONFIG_SOC_SERIES_ESP32C3
-#define ISR_HANDLER isr_handler_t
-#else
-#define ISR_HANDLER intr_handler_t
-#endif
-
 #define ESP32_XT_WDT_MAX_TIMEOUT 255
 
 struct esp32_xt_wdt_data {
@@ -134,7 +124,7 @@ static int esp32_xt_wdt_init(const struct device *dev)
 
 	flags = ESP_PRIO_TO_FLAGS(cfg->irq_priority) | ESP_INT_FLAGS_CHECK(cfg->irq_flags) |
 		ESP_INTR_FLAG_SHARED;
-	err = esp_intr_alloc(cfg->irq_source, flags, (ISR_HANDLER)esp32_xt_wdt_isr, (void *)dev,
+	err = esp_intr_alloc(cfg->irq_source, flags, (intr_handler_t)esp32_xt_wdt_isr, (void *)dev,
 			     NULL);
 	if (err) {
 		LOG_ERR("Failed to register ISR\n");
diff --git a/drivers/wifi/CMakeLists.txt b/drivers/wifi/CMakeLists.txt
index 8192278f6dd..96c24d245b6 100644
--- a/drivers/wifi/CMakeLists.txt
+++ b/drivers/wifi/CMakeLists.txt
@@ -26,3 +26,4 @@ add_subdirectory_ifdef(CONFIG_WIFI_WINC1500     winc1500)
 add_subdirectory_ifdef(CONFIG_WIFI_NXP          nxp)
 add_subdirectory_ifdef(CONFIG_WIFI_AIROC        infineon)
 add_subdirectory_ifdef(CONFIG_WIFI_NRF70        nrf_wifi)
+add_subdirectory_ifdef(CONFIG_WIFI_SILABS_SIWX91X siwx91x)
diff --git a/drivers/wifi/Kconfig b/drivers/wifi/Kconfig
index 55b2a943ff2..b6f7cfcb84c 100644
--- a/drivers/wifi/Kconfig
+++ b/drivers/wifi/Kconfig
@@ -43,5 +43,6 @@ source "drivers/wifi/esp32/Kconfig.esp32"
 source "drivers/wifi/nxp/Kconfig.nxp"
 source "drivers/wifi/infineon/Kconfig.airoc"
 source "drivers/wifi/nrf_wifi/Kconfig.nrfwifi"
+source "drivers/wifi/siwx91x/Kconfig.siwx91x"
 
 endif # WIFI
diff --git a/drivers/wifi/esp32/Kconfig.esp32 b/drivers/wifi/esp32/Kconfig.esp32
index 8f2c2f6ace3..87a2b4be405 100644
--- a/drivers/wifi/esp32/Kconfig.esp32
+++ b/drivers/wifi/esp32/Kconfig.esp32
@@ -8,6 +8,7 @@ menuconfig WIFI_ESP32
 	depends on !SMP
 	select THREAD_CUSTOM_DATA
 	select NET_L2_WIFI_MGMT
+	select NET_L2_ETHERNET
 	select WIFI_USE_NATIVE_NETWORKING
 	select MBEDTLS
 	select THREAD_STACK_INFO
@@ -20,12 +21,22 @@ menuconfig WIFI_ESP32
 
 if WIFI_ESP32
 
-config HEAP_MEM_POOL_ADD_SIZE_WIFI
+config HEAP_MEM_POOL_ADD_SIZE_ESP_WIFI
 	int
-	default 4096
+	default 40960 if ESP_WIFI_HEAP_SYSTEM
+	default 0
 	help
 	  Make sure there is a minimal heap available for Wi-Fi driver.
 
+choice ESP_WIFI_HEAP
+	prompt "Wi-Fi adapter heap memory"
+	default ESP_WIFI_HEAP_SYSTEM
+
+	config ESP_WIFI_HEAP_SYSTEM
+		bool "Wi-Fi adapter use kernel mempool heap (k_malloc)"
+
+endchoice # ESP_WIFI_HEAP
+
 config NET_TCP_WORKQ_STACK_SIZE
 	default 2048
 
@@ -54,10 +65,12 @@ config ESP32_WIFI_STA_RECONNECT
 	help
 	  Set auto WiFI reconnection when disconnected.
 
-config ESP32_WIFI_SW_COEXIST_ENABLE
-	bool
+config ESP32_WIFI_STA_SCAN_ALL
+	bool "Scan all available APs when connecting in station mode"
 	help
-	  Software controls WiFi/Bluetooth coexistence. Not supported yet.
+	  When connecting in station mode, scan all channels and connect to the channel with the
+	  highest RSSI. Without this, a fast scan is performed which connects to the first AP
+	  found.
 
 config ESP32_WIFI_NET_ALLOC_SPIRAM
 	bool "Allocate memory of WiFi and NET in SPIRAM"
@@ -210,7 +223,6 @@ config ESP32_WIFI_RX_MGMT_BUF_NUM_DEF
 
 config ESP32_WIFI_CSI_ENABLED
 	bool "WiFi CSI(Channel State Information)"
-	default n
 	help
 	  Select this option to enable CSI(Channel State Information) feature.
 	  CSI takes about CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM KB of RAM.
@@ -263,7 +275,6 @@ config ESP32_WIFI_RX_BA_WIN
 config ESP32_WIFI_AMSDU_TX_ENABLED
 	bool "WiFi AMSDU TX"
 	depends on ESP_SPIRAM
-	default n
 	help
 	  Select this option to enable AMSDU TX feature
 
@@ -276,8 +287,6 @@ config ESP32_WIFI_MGMT_SBUF_NUM
 
 config ESP32_WIFI_IRAM_OPT
 	bool "WiFi IRAM speed optimization"
-	default n if (BT && ESP_SPIRAM && SOC_SERIES_ESP32)
-	default y
 	help
 	  Select this option to place frequently called Wi-Fi library functions in IRAM.
 	  When this option is disabled, more than 10Kbytes of IRAM memory will be saved
@@ -285,7 +294,6 @@ config ESP32_WIFI_IRAM_OPT
 
 config ESP32_WIFI_RX_IRAM_OPT
 	bool "WiFi RX IRAM speed optimization"
-	default n if (BT && ESP_SPIRAM && SOC_SERIES_ESP32)
 	help
 	  Select this option to place frequently called Wi-Fi library RX functions in IRAM.
 	  When this option is disabled, more than 17Kbytes of IRAM memory will be saved
@@ -326,26 +334,8 @@ config ESP32_WIFI_SLP_DEFAULT_WAIT_BROADCAST_DATA_TIME
 	  before entering the sleep process. If a broadcast packet is received with more data bits, the time
 	  will refreshed. unit: milliseconds.
 
-choice ESP_WIFI_HEAP
-	prompt "Wifi adapter heap in use"
-	default ESP_WIFI_HEAP_RUNTIME
-
-	config ESP_WIFI_HEAP_RUNTIME
-		bool "Wifi adapter use ESP runtime heap"
-		depends on ESP_HEAP_RUNTIME
-
-	config ESP_WIFI_HEAP_SPIRAM
-		bool "Wifi adapter use SPIRAM heap"
-		depends on ESP_SPIRAM
-
-	config ESP_WIFI_HEAP_SYSTEM
-		bool "Wifi adapter use system heap"
-
-endchoice # ESP_WIFI_HEAP
-
 config ESP32_WIFI_FTM_ENABLE
 	bool "WiFi FTM"
-	default n
 	depends on SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
 	help
 	  Enable feature Fine Timing Measurement for calculating WiFi Round-Trip-Time (RTT).
@@ -368,7 +358,6 @@ config ESP32_WIFI_SOFTAP_SUPPORT
 
 config ESP32_WIFI_MBEDTLS_CRYPTO
 	bool "Use MbedTLS crypto APIs"
-	default n
 	select MBEDTLS_ECP_C
 	select MBEDTLS_ECDH_C
 	select MBEDTLS_ECDSA_C
@@ -382,7 +371,6 @@ config ESP32_WIFI_MBEDTLS_CRYPTO
 
 config ESP32_WIFI_ENABLE_WPA3_SAE
 	bool "WPA3-Personal"
-	default n
 	select ESP32_WIFI_MBEDTLS_CRYPTO
 	help
 	  Select this option to allow the device to establish a WPA3-Personal connection.
@@ -403,7 +391,6 @@ config ESP32_WIFI_ENABLE_SAE_PK
 
 config ESP32_WIFI_DEBUG_PRINT
 	bool "Print debug messages from WPA Supplicant"
-	default n
 	help
 	  Select this option to print logging information from WPA supplicant,
 	  this includes handshake information and key hex dumps depending
diff --git a/drivers/wifi/esp32/src/esp_wifi_drv.c b/drivers/wifi/esp32/src/esp_wifi_drv.c
index cd7f979dc68..06cc6781387 100644
--- a/drivers/wifi/esp32/src/esp_wifi_drv.c
+++ b/drivers/wifi/esp32/src/esp_wifi_drv.c
@@ -95,6 +95,10 @@ static int esp32_wifi_send(const struct device *dev, struct net_pkt *pkt)
 	const int pkt_len = net_pkt_get_len(pkt);
 	esp_interface_t ifx = data->state == ESP32_AP_CONNECTED ? ESP_IF_WIFI_AP : ESP_IF_WIFI_STA;
 
+	if (esp32_data.state != ESP32_STA_CONNECTED && esp32_data.state != ESP32_AP_CONNECTED) {
+		return -EIO;
+	}
+
 	/* Read the packet payload */
 	if (net_pkt_read(pkt, data->frame_buf, pkt_len) < 0) {
 		goto out;
@@ -568,6 +572,11 @@ static int esp32_wifi_connect(const struct device *dev,
 		return -EIO;
 	}
 
+#if defined(CONFIG_ESP32_WIFI_STA_SCAN_ALL)
+	wifi_config.sta.scan_method = WIFI_ALL_CHANNEL_SCAN;
+	wifi_config.sta.sort_method = WIFI_CONNECT_AP_BY_SIGNAL;
+#endif
+
 	if (params->channel == WIFI_CHANNEL_ANY) {
 		wifi_config.sta.channel = 0U;
 		data->status.channel = 0U;
@@ -768,6 +777,13 @@ static int esp32_wifi_status(const struct device *dev, struct wifi_iface_status
 	status->mfp = WIFI_MFP_DISABLE;
 
 	if (esp_wifi_get_mode(&mode) == ESP_OK) {
+#if defined(CONFIG_ESP32_WIFI_AP_STA_MODE)
+		if (mode == ESP32_WIFI_MODE_APSTA && data == &esp32_data) {
+			mode = ESP32_WIFI_MODE_STA;
+		} else if (mode == ESP32_WIFI_MODE_APSTA && data == &esp32_ap_sta_data) {
+			mode = ESP32_WIFI_MODE_AP;
+		}
+#endif
 		if (mode == ESP32_WIFI_MODE_STA) {
 			wifi_phy_mode_t phy_mode;
 			esp_err_t err;
@@ -837,21 +853,14 @@ static void esp32_wifi_init(struct net_if *iface)
 #if defined(CONFIG_ESP32_WIFI_AP_STA_MODE)
 	struct wifi_nm_instance *nm = wifi_nm_get_instance("esp32_wifi_nm");
 
-	if (!esp32_wifi_iface_ap) {
-		esp32_wifi_iface_ap = iface;
-		dev_data->state = ESP32_AP_STOPPED;
+	esp32_wifi_iface = iface;
+	dev_data->state = ESP32_STA_STOPPED;
 
-		esp_read_mac(dev_data->mac_addr, ESP_MAC_WIFI_SOFTAP);
-		wifi_nm_register_mgd_type_iface(nm, WIFI_TYPE_SAP, esp32_wifi_iface_ap);
-	} else {
-		esp32_wifi_iface = iface;
-		dev_data->state = ESP32_STA_STOPPED;
+	/* Start interface when we are actually connected with Wi-Fi network */
+	esp_read_mac(dev_data->mac_addr, ESP_MAC_WIFI_STA);
+	esp_wifi_internal_reg_rxcb(ESP_IF_WIFI_STA, eth_esp32_rx);
+	wifi_nm_register_mgd_type_iface(nm, WIFI_TYPE_STA, esp32_wifi_iface);
 
-		/* Start interface when we are actually connected with Wi-Fi network */
-		esp_read_mac(dev_data->mac_addr, ESP_MAC_WIFI_STA);
-		esp_wifi_internal_reg_rxcb(ESP_IF_WIFI_STA, eth_esp32_rx);
-		wifi_nm_register_mgd_type_iface(nm, WIFI_TYPE_STA, esp32_wifi_iface);
-	}
 #else
 
 	esp32_wifi_iface = iface;
@@ -870,6 +879,31 @@ static void esp32_wifi_init(struct net_if *iface)
 	net_if_carrier_off(iface);
 }
 
+#if defined(CONFIG_ESP32_WIFI_AP_STA_MODE)
+static void esp32_wifi_init_ap(struct net_if *iface)
+{
+	const struct device *dev = net_if_get_device(iface);
+	struct esp32_wifi_runtime *dev_data = dev->data;
+	struct ethernet_context *eth_ctx = net_if_l2_data(iface);
+
+	eth_ctx->eth_if_type = L2_ETH_IF_TYPE_WIFI;
+
+	struct wifi_nm_instance *nm = wifi_nm_get_instance("esp32_wifi_nm");
+
+	esp32_wifi_iface_ap = iface;
+	dev_data->state = ESP32_AP_STOPPED;
+
+	esp_read_mac(dev_data->mac_addr, ESP_MAC_WIFI_SOFTAP);
+	wifi_nm_register_mgd_type_iface(nm, WIFI_TYPE_SAP, esp32_wifi_iface_ap);
+
+	/* Assign link local address. */
+	net_if_set_link_addr(iface, dev_data->mac_addr, 6, NET_LINK_ETHERNET);
+
+	ethernet_init(iface);
+	net_if_carrier_off(iface);
+}
+#endif
+
 #if defined(CONFIG_NET_STATISTICS_WIFI)
 static int esp32_wifi_stats(const struct device *dev, struct net_stats_wifi *stats)
 {
@@ -900,6 +934,7 @@ static int esp32_wifi_dev_init(const struct device *dev)
 
 	wifi_init_config_t config = WIFI_INIT_CONFIG_DEFAULT();
 	esp_err_t ret = esp_wifi_init(&config);
+	esp_wifi_set_mode(ESP32_WIFI_MODE_NULL);
 
 	if (ret == ESP_ERR_NO_MEM) {
 		LOG_ERR("Not enough memory to initialize Wi-Fi.");
@@ -934,6 +969,13 @@ static const struct net_wifi_mgmt_offload esp32_api = {
 	.wifi_iface.send = esp32_wifi_send,
 	.wifi_mgmt_api = &esp32_wifi_mgmt,
 };
+#if defined(CONFIG_ESP32_WIFI_AP_STA_MODE)
+static const struct net_wifi_mgmt_offload esp32_api_ap = {
+	.wifi_iface.iface_api.init = esp32_wifi_init_ap,
+	.wifi_iface.send = esp32_wifi_send,
+	.wifi_mgmt_api = &esp32_wifi_mgmt,
+};
+#endif
 
 NET_DEVICE_DT_INST_DEFINE(0,
 		esp32_wifi_dev_init, NULL,
@@ -945,7 +987,7 @@ NET_DEVICE_DT_INST_DEFINE(0,
 NET_DEVICE_DT_INST_DEFINE(1,
 		NULL, NULL,
 		&esp32_ap_sta_data, NULL, CONFIG_WIFI_INIT_PRIORITY,
-		&esp32_api, ETHERNET_L2,
+		&esp32_api_ap, ETHERNET_L2,
 		NET_L2_GET_CTX_TYPE(ETHERNET_L2), NET_ETH_MTU);
 
 DEFINE_WIFI_NM_INSTANCE(esp32_wifi_nm, &esp32_wifi_mgmt);
diff --git a/drivers/wifi/esp_at/Kconfig.esp_at b/drivers/wifi/esp_at/Kconfig.esp_at
index 1b611e8ba3f..f3714bcb8a7 100644
--- a/drivers/wifi/esp_at/Kconfig.esp_at
+++ b/drivers/wifi/esp_at/Kconfig.esp_at
@@ -163,6 +163,7 @@ config WIFI_ESP_AT_DNS_USE
 
 config WIFI_ESP_AT_CIPDINFO_USE
 	bool "Use CIPDINFO to get peer ip and port"
+	default y if DNS_RESOLVER
 	help
 	  Enable AT+CIPDINFO to get peer ip-address and port.
 
diff --git a/drivers/wifi/esp_at/esp.c b/drivers/wifi/esp_at/esp.c
index e0627a8d39e..c68ea98ee0f 100644
--- a/drivers/wifi/esp_at/esp.c
+++ b/drivers/wifi/esp_at/esp.c
@@ -825,7 +825,13 @@ static int cmd_ipd_parse_hdr(struct esp_data *dev,
 		char *remote_ip;
 		long port;
 
-		err = esp_pull_quoted(&str, str_end, &remote_ip);
+		if (IS_ENABLED(CONFIG_WIFI_ESP_AT_VERSION_1_7)) {
+			/* NOT quoted per AT version 1.7.0 */
+			err = esp_pull_raw(&str, str_end, &remote_ip);
+		} else {
+			/* Quoted per AT version 2.1.0/2.2.0 */
+			err = esp_pull_quoted(&str, str_end, &remote_ip);
+		}
 		if (err) {
 			if (err == -EAGAIN && match_len >= MAX_IPD_LEN) {
 				LOG_ERR("Failed to pull remote_ip");
diff --git a/drivers/wifi/nrf_wifi/CMakeLists.txt b/drivers/wifi/nrf_wifi/CMakeLists.txt
index 383d58490c5..d59a6ef6e9f 100644
--- a/drivers/wifi/nrf_wifi/CMakeLists.txt
+++ b/drivers/wifi/nrf_wifi/CMakeLists.txt
@@ -27,11 +27,9 @@ zephyr_library_sources_ifndef(CONFIG_NRF70_OFFLOADED_RAW_TX
   src/fmac_main.c
 )
 
-if(NOT CONFIG_NRF71_ON_IPC)
-  zephyr_library_sources_ifdef(CONFIG_NRF_WIFI_PATCHES_BUILTIN
-    src/fw_load.c
-  )
-endif()
+zephyr_library_sources_ifdef(CONFIG_NRF_WIFI_PATCHES_BUILTIN
+  src/fw_load.c
+)
 
 if(NOT CONFIG_NRF70_RADIO_TEST AND NOT CONFIG_NRF70_OFFLOADED_RAW_TX)
   zephyr_library_sources(
diff --git a/drivers/wifi/nrf_wifi/Kconfig.nrfwifi b/drivers/wifi/nrf_wifi/Kconfig.nrfwifi
index 6f3fddec714..a8bd7e83fa8 100644
--- a/drivers/wifi/nrf_wifi/Kconfig.nrfwifi
+++ b/drivers/wifi/nrf_wifi/Kconfig.nrfwifi
@@ -5,9 +5,6 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-# TODO: Use DTS generated Kconfig once the board support is added
-DT_COMPAT_NORDIC_WIFI71 := nordic,wifi71
-
 menuconfig WIFI_NRF70
 	bool "nRF70 driver"
 	select NET_L2_WIFI_MGMT if NETWORKING
@@ -19,8 +16,7 @@ menuconfig WIFI_NRF70
 	depends on \
 		DT_HAS_NORDIC_NRF7002_SPI_ENABLED || DT_HAS_NORDIC_NRF7002_QSPI_ENABLED || \
 		DT_HAS_NORDIC_NRF7001_SPI_ENABLED || DT_HAS_NORDIC_NRF7001_QSPI_ENABLED || \
-		DT_HAS_NORDIC_NRF7000_SPI_ENABLED || DT_HAS_NORDIC_NRF7000_QSPI_ENABLED || \
-		$(dt_compat_enabled,$(DT_COMPAT_NORDIC_WIFI71))
+		DT_HAS_NORDIC_NRF7000_SPI_ENABLED || DT_HAS_NORDIC_NRF7000_QSPI_ENABLED
 	help
 	  Nordic Wi-Fi Driver
 
@@ -28,7 +24,7 @@ if WIFI_NRF70
 # Hidden symbols for internal use
 config WIFI_NRF7002
 	bool
-	default y if DT_HAS_NORDIC_NRF7002_SPI_ENABLED || DT_HAS_NORDIC_NRF7002_QSPI_ENABLED || $(dt_compat_enabled,$(DT_COMPAT_NORDIC_WIFI71))
+	default y if DT_HAS_NORDIC_NRF7002_SPI_ENABLED || DT_HAS_NORDIC_NRF7002_QSPI_ENABLED
 
 config WIFI_NRF7001
 	bool
@@ -52,18 +48,35 @@ choice NRF70_OPER_MODES
 config NRF70_SCAN_ONLY
 	bool "nRF70 scan only mode"
 	help
-	  Select this option to enable scan only mode of the nRF70 driver
+	  Select this option to enable scan-only mode of the nRF70 driver.
+	  In this mode, the driver can only perform scanning operations
+	  to discover nearby Wi-Fi networks, but cannot establish connections
+	  or transmit/receive data. Mainly used for location accuracy
+	  improvement.
 
 config NRF70_SYSTEM_MODE
 	bool "System mode of the nRF70 driver"
 	help
-	  Select this option to enable system mode of the nRF70 driver
+	  Select this option to enable system mode of the nRF70 driver.
+	  This is the normal operating mode that supports full Wi-Fi
+	  functionality including sub-modes like STA, AP, and P2P.
 
 config NRF70_RADIO_TEST
 	bool "Radio test mode of the nRF70 driver"
+	help
+	  Select this option to enable radio test mode of the nRF70 driver.
+	  This mode is used for testing RF performance and regulatory
+	  compliance. It provides direct control of the radio hardware
+	  for transmitting test patterns and measuring RF parameters.
 
 config NRF70_OFFLOADED_RAW_TX
 	bool "Offloaded raw TX mode of the nRF70 driver"
+	help
+	  Select this option to enable offloaded raw TX mode.
+	  In this mode, raw 802.11 frames can be transmitted directly
+	  without normal Wi-Fi protocol processing. The frame construction
+	  and transmission timing is handled by the Wi-Fi hardware,
+	  reducing CPU load.
 
 endchoice
 
@@ -137,7 +150,7 @@ endchoice
 
 config NRF_WIFI_LOW_POWER
 	bool "Low power mode in nRF Wi-Fi chipsets"
-	depends on !NRF71_ON_IPC
+	depends on !NRF70_RADIO_TEST && !NRF70_AP_MODE
 	default y
 
 config NRF70_TCP_IP_CHECKSUM_OFFLOAD
@@ -178,10 +191,10 @@ config NRF70_2_4G_ONLY
 config NRF70_SR_COEX
 	bool "Wi-Fi and SR coexistence support"
 
+if NRF70_SR_COEX
 config NRF70_SR_COEX_RF_SWITCH
 	bool "GPIO configuration to control SR side RF switch position"
 	depends on $(dt_nodelabel_has_prop,nrf70,srrf-switch-gpios)
-	depends on NRF70_SR_COEX
 	help
 	  Select this option to enable GPIO configuration to control SR side RF switch position.
 	  If this GPIO is asserted (1), the SR side RF switch is connected to the Wi-Fi side (shared antenna).
@@ -189,7 +202,6 @@ config NRF70_SR_COEX_RF_SWITCH
 
 config NRF70_SR_COEX_SLEEP_CTRL_GPIO_CTRL
 	bool "Configuration of GPIO control for coexistence"
-	depends on !NRF71_ON_IPC
 	default y
 
 config NRF70_SR_COEX_SWCTRL1_OUTPUT
@@ -199,6 +211,7 @@ config NRF70_SR_COEX_SWCTRL1_OUTPUT
 config NRF70_SR_COEX_BT_GRANT_ACTIVE_LOW
 	int "Configure BT grant active low"
 	default 1
+endif # NRF70_SR_COEX
 
 config NRF70_WORKQ_STACK_SIZE
 	int "Stack size for workqueue"
@@ -574,11 +587,22 @@ config NET_TC_TX_COUNT
 
 endif # NETWORKING
 
+config NRF_WIFI_USE_VARIABLE_NET_BUFS
+	bool "Use variable network buffers"
+	default y
+	help
+	  This option enables the use of variable network buffers in the nRF70 driver.
+	  Variable network buffers optimize RAM usage by allocating buffers of different sizes
+	  based on the data size. This option is enabled by default to optimize RAM usage.
+	  Samples and applications can override this option for higher performance.
+
+if NRF_WIFI_USE_VARIABLE_NET_BUFS
 # nRF70 now uses variable buffers as default to optimize RAM usage. Default pool sizes are used, samples/apps can override
 # for higher performance.
 choice NET_PKT_DATA_ALLOC_TYPE
 	default NET_BUF_VARIABLE_DATA_SIZE
 endchoice
+endif # NRF_WIFI_USE_VARIABLE_NET_BUFS
 
 config MAIN_STACK_SIZE
 	default 4096
@@ -664,9 +688,8 @@ config NRF_WIFI_AP_DEAD_DETECT_TIMEOUT
 
 config NRF_WIFI_RPU_RECOVERY
 	bool "RPU recovery mechanism"
-	# Relies on power-save mode, so, LPM is needed and AP mode is not supported
+	# Relies on power-save mode, so, LPM is needed
 	depends on NRF_WIFI_LOW_POWER
-	depends on !NRF70_AP_MODE
 	default y
 	select EXPERIMENTAL
 	help
diff --git a/drivers/wifi/nrf_wifi/src/fmac_main.c b/drivers/wifi/nrf_wifi/src/fmac_main.c
index f26a7cd67d3..0559ca48f7c 100644
--- a/drivers/wifi/nrf_wifi/src/fmac_main.c
+++ b/drivers/wifi/nrf_wifi/src/fmac_main.c
@@ -75,6 +75,11 @@ BUILD_ASSERT(RPU_PKTRAM_SIZE - TOTAL_RX_SIZE >= TOTAL_TX_SIZE,
 BUILD_ASSERT(CONFIG_NRF70_TX_MAX_DATA_SIZE >= MAX_TX_FRAME_SIZE,
 	"TX buffer size must be at least as big as the MTU and headroom");
 
+BUILD_ASSERT(CONFIG_NRF70_TX_MAX_DATA_SIZE % 4 == 0,
+	"TX buffer size must be a multiple of 4");
+BUILD_ASSERT(CONFIG_NRF70_RX_MAX_DATA_SIZE % 4 == 0,
+	"RX buffer size must be a multiple of 4");
+
 static const unsigned char aggregation = 1;
 static const unsigned char max_num_tx_agg_sessions = 4;
 static const unsigned char max_num_rx_agg_sessions = 8;
@@ -357,6 +362,7 @@ int nrf_wifi_reg_domain(const struct device *dev, struct wifi_reg_domain *reg_do
 			goto out;
 		}
 
+		ret = 0;
 		goto out;
 	}
 #endif
@@ -479,12 +485,8 @@ void reg_change_callbk_fn(void *vif_ctx,
 }
 #endif /* !CONFIG_NRF70_RADIO_TEST */
 
-#ifdef CONFIG_NRF71_ON_IPC
-#define MAX_TX_PWR(label) DT_PROP(DT_NODELABEL(wifi), label) * 4
-#else
 /* DTS uses 1dBm as the unit for TX power, while the RPU uses 0.25dBm */
 #define MAX_TX_PWR(label) DT_PROP(DT_NODELABEL(nrf70), label) * 4
-#endif /* CONFIG_NRF71_ON_IPC */
 
 void configure_tx_pwr_settings(struct nrf_wifi_tx_pwr_ctrl_params *tx_pwr_ctrl_params,
 				struct nrf_wifi_tx_pwr_ceil_params *tx_pwr_ceil_params)
@@ -637,7 +639,7 @@ enum nrf_wifi_status nrf_wifi_fmac_dev_add_zep(struct nrf_wifi_drv_priv_zep *drv
 
 #if defined(CONFIG_NRF70_SR_COEX_SLEEP_CTRL_GPIO_CTRL) && \
 	defined(CONFIG_NRF70_SYSTEM_MODE)
-	LOG_INF("Configuring SLEEP CTRL GPIO control register\n");
+	LOG_DBG("Configuring SLEEP CTRL GPIO control register\n");
 	status = nrf_wifi_coex_config_sleep_ctrl_gpio_ctrl(rpu_ctx_zep->rpu_ctx,
 			alt_swctrl1_function_bt_coex_status1,
 			invert_bt_coex_grant_output);
@@ -960,7 +962,7 @@ DEVICE_DT_INST_DEFINE(0,
 	      POST_KERNEL,
 	      CONFIG_WIFI_INIT_PRIORITY, /* prio */
 	      NULL); /* api */
-#endif /* CONFIG_NRF70_STA_MODE */
+#endif /* CONFIG_NET_L2_ETHERNET */
 
 #ifdef CONFIG_NET_CONNECTION_MANAGER_CONNECTIVITY_WIFI_MGMT
 CONNECTIVITY_WIFI_MGMT_BIND(Z_DEVICE_DT_DEV_ID(DT_DRV_INST(0)));
diff --git a/drivers/wifi/nrf_wifi/src/fw_load.c b/drivers/wifi/nrf_wifi/src/fw_load.c
index f09643a585a..9204d295d30 100644
--- a/drivers/wifi/nrf_wifi/src/fw_load.c
+++ b/drivers/wifi/nrf_wifi/src/fw_load.c
@@ -31,13 +31,12 @@ enum nrf_wifi_status nrf_wifi_fw_load(void *rpu_ctx)
 		LOG_ERR("%s: nrf_wifi_fmac_fw_parse failed", __func__);
 		return status;
 	}
-#ifndef CONFIG_NRF71_ON_IPC
 	/* Load the FW patches to the RPU */
 	status = nrf_wifi_fmac_fw_load(rpu_ctx, &fw_info);
 
 	if (status != NRF_WIFI_STATUS_SUCCESS) {
 		LOG_ERR("%s: nrf_wifi_fmac_fw_load failed", __func__);
 	}
-#endif /* !CONFIG_NRF71_ON_IPC */
+
 	return status;
 }
diff --git a/drivers/wifi/nrf_wifi/src/net_if.c b/drivers/wifi/nrf_wifi/src/net_if.c
index 68c0f0c45f1..633ee48f901 100644
--- a/drivers/wifi/nrf_wifi/src/net_if.c
+++ b/drivers/wifi/nrf_wifi/src/net_if.c
@@ -358,6 +358,7 @@ int nrf_wifi_if_send(const struct device *dev,
 	struct nrf_wifi_sys_fmac_dev_ctx *sys_dev_ctx = NULL;
 	struct rpu_host_stats *host_stats = NULL;
 	void *nbuf = NULL;
+	bool locked = false;
 
 	if (!dev || !pkt) {
 		LOG_ERR("%s: vif_ctx_zep is NULL", __func__);
@@ -371,24 +372,27 @@ int nrf_wifi_if_send(const struct device *dev,
 		goto out;
 	}
 
+	/* Allocate packet before locking mutex (blocks until allocation success) */
+	nbuf = net_pkt_to_nbuf(pkt);
+
 	ret = k_mutex_lock(&vif_ctx_zep->vif_lock, K_FOREVER);
 	if (ret != 0) {
 		LOG_ERR("%s: Failed to lock vif_lock", __func__);
-		goto out;
+		goto drop;
 	}
+	locked = true;
 
 	rpu_ctx_zep = vif_ctx_zep->rpu_ctx_zep;
 	if (!rpu_ctx_zep || !rpu_ctx_zep->rpu_ctx) {
-		goto unlock;
+		goto drop;
 	}
 
 	sys_dev_ctx = wifi_dev_priv(rpu_ctx_zep->rpu_ctx);
 	host_stats = &sys_dev_ctx->host_stats;
-	nbuf = net_pkt_to_nbuf(pkt);
-	if (!nbuf) {
-		LOG_DBG("Failed to allocate net_pkt");
-		host_stats->total_tx_drop_pkts++;
-		goto out;
+
+	if (nbuf == NULL) {
+		LOG_ERR("%s: allocation failed", __func__);
+		goto drop;
 	}
 
 #ifdef CONFIG_NRF70_RAW_DATA_TX
@@ -415,10 +419,16 @@ int nrf_wifi_if_send(const struct device *dev,
 #endif /* CONFIG_NRF70_RAW_DATA_TX */
 	goto unlock;
 drop:
-	host_stats->total_tx_drop_pkts++;
-	nrf_wifi_osal_nbuf_free(nbuf);
+	if (host_stats != NULL) {
+		host_stats->total_tx_drop_pkts++;
+	}
+	if (nbuf != NULL) {
+		nrf_wifi_osal_nbuf_free(nbuf);
+	}
 unlock:
-	k_mutex_unlock(&vif_ctx_zep->vif_lock);
+	if (locked) {
+		k_mutex_unlock(&vif_ctx_zep->vif_lock);
+	}
 #else
 	ARG_UNUSED(dev);
 	ARG_UNUSED(pkt);
@@ -565,7 +575,6 @@ enum nrf_wifi_status nrf_wifi_get_mac_addr(struct nrf_wifi_vif_ctx_zep *vif_ctx_
 		random_mac_addr,
 		WIFI_MAC_ADDR_LEN);
 #elif CONFIG_WIFI_OTP_MAC_ADDRESS
-#ifndef CONFIG_NRF71_ON_IPC
 	status = nrf_wifi_fmac_otp_mac_addr_get(fmac_dev_ctx,
 				vif_ctx_zep->vif_idx,
 				vif_ctx_zep->mac_addr.addr);
@@ -574,15 +583,6 @@ enum nrf_wifi_status nrf_wifi_get_mac_addr(struct nrf_wifi_vif_ctx_zep *vif_ctx_
 			__func__);
 		goto unlock;
 	}
-#else
-	/* Set dummy MAC address */
-	vif_ctx_zep->mac_addr.addr[0] = 0x00;
-	vif_ctx_zep->mac_addr.addr[1] = 0x00;
-	vif_ctx_zep->mac_addr.addr[2] = 0x5E;
-	vif_ctx_zep->mac_addr.addr[3] = 0x00;
-	vif_ctx_zep->mac_addr.addr[4] = 0x10;
-	vif_ctx_zep->mac_addr.addr[5] = 0x00;
-#endif /* !CONFIG_NRF71_ON_IPC */
 #endif
 
 	if (!nrf_wifi_utils_is_mac_addr_valid(vif_ctx_zep->mac_addr.addr)) {
diff --git a/drivers/wifi/nxp/Kconfig.nxp b/drivers/wifi/nxp/Kconfig.nxp
index 174f368d8e2..424083fb38a 100644
--- a/drivers/wifi/nxp/Kconfig.nxp
+++ b/drivers/wifi/nxp/Kconfig.nxp
@@ -3,9 +3,10 @@
 
 menuconfig WIFI_NXP
 	bool "NXP Wi-Fi driver support"
-	select NET_L2_WIFI_MGMT if NETWORKING
-	select WIFI_USE_NATIVE_NETWORKING if NETWORKING
-	select NET_L2_ETHERNET_MGMT if NETWORKING && NET_L2_ETHERNET
+	select NET_L2_WIFI_MGMT
+	select WIFI_USE_NATIVE_NETWORKING
+	select NET_L2_ETHERNET
+	select NET_L2_ETHERNET_MGMT
 	select SDHC if !SOC_SERIES_RW6XX
 	select SDIO_STACK if !SOC_SERIES_RW6XX
 	select WIFI_NM
@@ -305,7 +306,7 @@ endchoice
 
 config NXP_WIFI_SHELL
 	bool "NXP Wi-Fi shell"
-	depends on SHELL
+	default y if SHELL
 	help
 	  NXP Wi-Fi shell commands support.
 
@@ -539,7 +540,8 @@ config NXP_WIFI_SOFTAP_SUPPORT
 	bool "Wi-Fi SoftAP Support"
 	select NET_DHCPV4_SERVER
 	select WIFI_NM_HOSTAPD_AP if WIFI_NM_WPA_SUPPLICANT
-	default y
+	imply WIFI_NM_HOSTAPD_WPS if WIFI_NM_HOSTAPD_AP && WIFI_NM_WPA_SUPPLICANT_WPS
+	imply WIFI_NM_HOSTAPD_CRYPTO_ENTERPRISE if WIFI_NM_HOSTAPD_AP && WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
 	help
 	  Option to enable Wi-Fi SoftAP functions in the Wi-Fi driver.
 
@@ -688,7 +690,7 @@ config NXP_WIFI_5GHz_SUPPORT
 
 config NXP_WIFI_TX_RX_ZERO_COPY
 	bool "Zero memory copy TX/RX data packets"
-	default y if NXP_RW610
+	depends on NXP_RW610
 	imply NET_IPV4_FRAGMENT
 	help
 	  This option enables the Zero memory copy of data packets in Wi-Fi driver data path.
@@ -720,6 +722,7 @@ config NXP_WIFI_RESET
 config NXP_WIFI_ECSA
 	bool "ECSA"
 	default y
+	depends on NXP_WIFI_SOFTAP_SUPPORT
 	help
 	  This option is used to do channel switch according to spec.
 
@@ -835,6 +838,11 @@ config NXP_WIFI_WLAN_CALDATA_3ANT_DIVERSITY
 	help
 	  This option is used to enable three antenna diversity.
 
+config NXP_OVERRIDE_CALIBRATION_DATA
+	bool "override default calibriation data"
+	help
+	  This option is used to override default calibration data.
+
 endif # NXP_RW610
 
 config NXP_WIFI_11AX_TWT
@@ -992,9 +1000,9 @@ if NXP_WIFI_SMOKE_TESTS
 config NXP_WIFI_SIGMA_AGENT
 	bool "Wi-Fi Alliance Sigma Agent Support"
 	select POSIX_API
-	select PTHREAD_IPC
+	select POSIX_THREADS
 	select PTHREAD_CREATE_BARRIER
-	select TIMER
+	select POSIX_TIMERS
 	help
 	  This option is to enable Wi-Fi Alliance Sigma Agent support in the Wi-Fi driver.
 
diff --git a/drivers/wifi/nxp/nxp_wifi_drv.c b/drivers/wifi/nxp/nxp_wifi_drv.c
index 26cb7d462f2..ac952b6ad4b 100644
--- a/drivers/wifi/nxp/nxp_wifi_drv.c
+++ b/drivers/wifi/nxp/nxp_wifi_drv.c
@@ -49,7 +49,9 @@ LOG_MODULE_REGISTER(nxp_wifi, CONFIG_WIFI_LOG_LEVEL);
  ******************************************************************************/
 static int s_nxp_wifi_State = NXP_WIFI_NOT_INITIALIZED;
 static bool s_nxp_wifi_StaConnected;
+#ifdef CONFIG_NXP_WIFI_SOFTAP_SUPPORT
 static bool s_nxp_wifi_UapActivated;
+#endif
 static struct k_event s_nxp_wifi_SyncEvent;
 
 static struct nxp_wifi_dev nxp_wifi0; /* static instance */
@@ -59,7 +61,7 @@ static struct wlan_network nxp_wlan_network;
 static struct wlan_network nxp_wlan_uap_network;
 #endif
 
-#ifndef CONFIG_WIFI_NM_HOSTAPD_AP
+#if defined(CONFIG_NXP_WIFI_SOFTAP_SUPPORT) && !defined(CONFIG_WIFI_NM_HOSTAPD_AP)
 static char uap_ssid[IEEEtypes_SSID_SIZE + 1];
 #endif
 
@@ -103,9 +105,9 @@ int nxp_wifi_wlan_event_callback(enum wlan_event_reason reason, void *data)
 	struct in_addr dhcps_addr4;
 	struct in_addr base_addr;
 	struct in_addr netmask_addr;
-#endif
 	struct wifi_iface_status status = { 0 };
 	struct wifi_ap_sta_info ap_sta_info = { 0 };
+#endif
 
 	LOG_DBG("WLAN: received event %d", reason);
 
@@ -151,6 +153,10 @@ int nxp_wifi_wlan_event_callback(enum wlan_event_reason reason, void *data)
 		net_if_dormant_off(g_mlan.netif);
 #endif
 		LOG_DBG("WLAN: associated to nxp_wlan_network");
+#ifdef CONFIG_NET_STATISTICS_WIFI
+		g_mlan.stats.sta_mgmt.beacons_rx = 0;
+		g_mlan.stats.sta_mgmt.beacons_miss = 0;
+#endif
 		break;
 	case WLAN_REASON_SUCCESS:
 		LOG_DBG("WLAN: connected to nxp_wlan_network");
@@ -196,10 +202,12 @@ int nxp_wifi_wlan_event_callback(enum wlan_event_reason reason, void *data)
 	case WLAN_REASON_CONNECT_FAILED:
 		net_if_dormant_on(g_mlan.netif);
 		LOG_WRN("WLAN: connect failed");
+		wifi_mgmt_raise_connect_result_event(g_mlan.netif, WIFI_STATUS_CONN_FAIL);
 		break;
 	case WLAN_REASON_NETWORK_NOT_FOUND:
 		net_if_dormant_on(g_mlan.netif);
 		LOG_WRN("WLAN: nxp_wlan_network not found");
+		wifi_mgmt_raise_connect_result_event(g_mlan.netif, WIFI_STATUS_CONN_AP_NOT_FOUND);
 		break;
 	case WLAN_REASON_NETWORK_AUTH_FAILED:
 		LOG_WRN("WLAN: nxp_wlan_network authentication failed");
@@ -210,6 +218,7 @@ int nxp_wifi_wlan_event_callback(enum wlan_event_reason reason, void *data)
 			auth_fail = 0;
 		}
 		net_if_dormant_on(g_mlan.netif);
+		wifi_mgmt_raise_connect_result_event(g_mlan.netif, WIFI_STATUS_CONN_WRONG_PASSWORD);
 		break;
 	case WLAN_REASON_ADDRESS_SUCCESS:
 		LOG_DBG("wlan_network mgr: DHCP new lease");
@@ -275,12 +284,6 @@ int nxp_wifi_wlan_event_callback(enum wlan_event_reason reason, void *data)
 		s_nxp_wifi_UapActivated = true;
 		break;
 	case WLAN_REASON_UAP_CLIENT_ASSOC:
-		LOG_DBG("WLAN: UAP a Client Associated");
-		LOG_DBG("Client => ");
-		print_mac((const char *)data);
-		LOG_DBG("Associated with Soft AP");
-		break;
-	case WLAN_REASON_UAP_CLIENT_CONN:
 		wlan_get_current_uap_network(&nxp_wlan_uap_network);
 #ifdef CONFIG_NXP_WIFI_11AX
 		if (nxp_wlan_uap_network.dot11ax) {
@@ -303,6 +306,12 @@ int nxp_wifi_wlan_event_callback(enum wlan_event_reason reason, void *data)
 		ap_sta_info.twt_capable = status.twt_capable;
 
 		wifi_mgmt_raise_ap_sta_connected_event(g_uap.netif, &ap_sta_info);
+		LOG_DBG("WLAN: UAP a Client Associated");
+		LOG_DBG("Client => ");
+		print_mac((const char *)data);
+		LOG_DBG("Associated with Soft AP");
+		break;
+	case WLAN_REASON_UAP_CLIENT_CONN:
 		LOG_DBG("WLAN: UAP a Client Connected");
 		LOG_DBG("Client => ");
 		print_mac((const char *)data);
@@ -489,6 +498,11 @@ static int nxp_wifi_start_ap(const struct device *dev, struct wifi_connect_req_p
 			nxp_wlan_uap_network.channel = params->channel;
 		}
 
+		if (nxp_wlan_uap_network.channel == 0) {
+			nxp_wlan_uap_network.acs_band =
+				(params->band == WIFI_FREQ_BAND_5_GHZ) ? 1 : 0;
+		}
+
 		if (params->mfp == WIFI_MFP_REQUIRED) {
 			nxp_wlan_uap_network.security.mfpc = true;
 			nxp_wlan_uap_network.security.mfpr = true;
@@ -503,17 +517,32 @@ static int nxp_wifi_start_ap(const struct device *dev, struct wifi_connect_req_p
 			nxp_wlan_uap_network.security.type = WLAN_SECURITY_WPA2;
 			nxp_wlan_uap_network.security.psk_len = params->psk_length;
 			strncpy(nxp_wlan_uap_network.security.psk, params->psk, params->psk_length);
-		}
-#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT
-		else if (params->security == WIFI_SECURITY_TYPE_PSK_SHA256) {
+		} else if (params->security == WIFI_SECURITY_TYPE_PSK_SHA256) {
 			nxp_wlan_uap_network.security.type = WLAN_SECURITY_WPA2;
-			nxp_wlan_uap_network.security.key_mgmt |= WLAN_KEY_MGMT_PSK_SHA256;
+			nxp_wlan_uap_network.security.key_mgmt = WLAN_KEY_MGMT_PSK_SHA256;
 			nxp_wlan_uap_network.security.psk_len = params->psk_length;
 			strncpy(nxp_wlan_uap_network.security.psk, params->psk, params->psk_length);
-		}
-#endif
-		else if (params->security == WIFI_SECURITY_TYPE_SAE) {
+		} else if (params->security == WIFI_SECURITY_TYPE_SAE) {
+			nxp_wlan_uap_network.security.type = WLAN_SECURITY_WPA3_SAE;
+			nxp_wlan_uap_network.security.password_len = params->psk_length;
+			strncpy(nxp_wlan_uap_network.security.password, params->psk,
+				params->psk_length);
+		} else if (params->security == WIFI_SECURITY_TYPE_SAE_H2E) {
+			nxp_wlan_uap_network.security.type = WLAN_SECURITY_WPA3_SAE;
+			nxp_wlan_uap_network.security.pwe_derivation = 1;
+			nxp_wlan_uap_network.security.password_len = params->psk_length;
+			strncpy(nxp_wlan_uap_network.security.password, params->psk,
+				params->psk_length);
+		} else if (params->security == WIFI_SECURITY_TYPE_SAE_AUTO) {
 			nxp_wlan_uap_network.security.type = WLAN_SECURITY_WPA3_SAE;
+			nxp_wlan_uap_network.security.pwe_derivation = 2;
+			nxp_wlan_uap_network.security.password_len = params->psk_length;
+			strncpy(nxp_wlan_uap_network.security.password, params->psk,
+				params->psk_length);
+		} else if (params->security == WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL) {
+			nxp_wlan_uap_network.security.type = WLAN_SECURITY_WPA2_WPA3_SAE_MIXED;
+			nxp_wlan_uap_network.security.psk_len = params->psk_length;
+			strncpy(nxp_wlan_uap_network.security.psk, params->psk, params->psk_length);
 			nxp_wlan_uap_network.security.password_len = params->psk_length;
 			strncpy(nxp_wlan_uap_network.security.password, params->psk,
 				params->psk_length);
@@ -553,6 +582,9 @@ static int nxp_wifi_start_ap(const struct device *dev, struct wifi_connect_req_p
 		return -ENOENT;
 	}
 
+	nxp_wlan_uap_network.beacon_period = NXP_WIFI_SAP_BEACON_PERIOD_DEFAULT;
+	nxp_wlan_uap_network.dtim_period = NXP_WIFI_SAP_DTIM_PERIOD_DEFAULT;
+
 	ret = wlan_add_network(&nxp_wlan_uap_network);
 	if (ret != WM_SUCCESS) {
 		status = NXP_WIFI_RET_FAIL;
@@ -684,20 +716,29 @@ static int nxp_wifi_process_results(unsigned int count)
 		res.security = WIFI_SECURITY_TYPE_NONE;
 
 		if (scan_result.wpa2_entp) {
-			res.security = WIFI_SECURITY_TYPE_EAP_TLS;
+			res.security = WIFI_SECURITY_TYPE_EAP;
 		}
 		if (scan_result.wpa2) {
 			res.security = WIFI_SECURITY_TYPE_PSK;
 		}
-#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT
 		if (scan_result.wpa2_sha256) {
 			res.security = WIFI_SECURITY_TYPE_PSK_SHA256;
 		}
-#endif
 		if (scan_result.wpa3_sae) {
 			res.security = WIFI_SECURITY_TYPE_SAE;
 		}
 
+		if (scan_result.wpa3_entp) {
+			res.wpa3_ent_type = WIFI_WPA3_ENTERPRISE_ONLY;
+			res.security = WIFI_SECURITY_TYPE_EAP;
+		} else if (scan_result.wpa3_1x_sha256) {
+			res.wpa3_ent_type = WIFI_WPA3_ENTERPRISE_SUITEB;
+			res.security = WIFI_SECURITY_TYPE_EAP;
+		} else if (scan_result.wpa3_1x_sha384) {
+			res.wpa3_ent_type = WIFI_WPA3_ENTERPRISE_SUITEB_192;
+			res.security = WIFI_SECURITY_TYPE_EAP;
+		}
+
 		if (scan_result.ap_mfpr) {
 			res.mfp = WIFI_MFP_REQUIRED;
 		} else if (scan_result.ap_mfpc) {
@@ -899,17 +940,32 @@ static int nxp_wifi_connect(const struct device *dev, struct wifi_connect_req_pa
 			nxp_wlan_network.security.type = WLAN_SECURITY_WPA2;
 			nxp_wlan_network.security.psk_len = params->psk_length;
 			strncpy(nxp_wlan_network.security.psk, params->psk, params->psk_length);
-		}
-#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT
-		else if (params->security == WIFI_SECURITY_TYPE_PSK_SHA256) {
+		} else if (params->security == WIFI_SECURITY_TYPE_PSK_SHA256) {
 			nxp_wlan_network.security.type = WLAN_SECURITY_WPA2;
-			nxp_wlan_network.security.key_mgmt |= WLAN_KEY_MGMT_PSK_SHA256;
+			nxp_wlan_network.security.key_mgmt = WLAN_KEY_MGMT_PSK_SHA256;
 			nxp_wlan_network.security.psk_len = params->psk_length;
 			strncpy(nxp_wlan_network.security.psk, params->psk, params->psk_length);
-		}
-#endif
-		else if (params->security == WIFI_SECURITY_TYPE_SAE) {
+		} else if (params->security == WIFI_SECURITY_TYPE_SAE) {
+			nxp_wlan_network.security.type = WLAN_SECURITY_WPA3_SAE;
+			nxp_wlan_network.security.password_len = params->psk_length;
+			strncpy(nxp_wlan_network.security.password, params->psk,
+				params->psk_length);
+		} else if (params->security == WIFI_SECURITY_TYPE_SAE_H2E) {
 			nxp_wlan_network.security.type = WLAN_SECURITY_WPA3_SAE;
+			nxp_wlan_network.security.pwe_derivation = 1;
+			nxp_wlan_network.security.password_len = params->psk_length;
+			strncpy(nxp_wlan_network.security.password, params->psk,
+				params->psk_length);
+		} else if (params->security == WIFI_SECURITY_TYPE_SAE_AUTO) {
+			nxp_wlan_network.security.type = WLAN_SECURITY_WPA3_SAE;
+			nxp_wlan_network.security.pwe_derivation = 2;
+			nxp_wlan_network.security.password_len = params->psk_length;
+			strncpy(nxp_wlan_network.security.password, params->psk,
+				params->psk_length);
+		} else if (params->security == WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL) {
+			nxp_wlan_network.security.type = WLAN_SECURITY_WPA2_WPA3_SAE_MIXED;
+			nxp_wlan_network.security.psk_len = params->psk_length;
+			strncpy(nxp_wlan_network.security.psk, params->psk, params->psk_length);
 			nxp_wlan_network.security.password_len = params->psk_length;
 			strncpy(nxp_wlan_network.security.password, params->psk,
 				params->psk_length);
@@ -977,15 +1033,47 @@ static int nxp_wifi_disconnect(const struct device *dev)
 	return 0;
 }
 
-static inline enum wifi_security_type nxp_wifi_security_type(enum wlan_security_type type)
+#ifdef CONFIG_NXP_WIFI_SOFTAP_SUPPORT
+static int nxp_wifi_uap_disconnect_sta(const struct device *dev, const uint8_t *mac)
 {
-	switch (type) {
-	case WLAN_SECURITY_NONE:
+	int ret;
+
+	if (!is_uap_started()) {
+		LOG_ERR("Please start uap first!");
+		return -EAGAIN;
+	}
+
+	ret = wlan_uap_disconnect_sta((uint8_t *)mac);
+	if (ret != WM_SUCCESS) {
+		LOG_ERR("Failed to disconnect STA");
+	}
+
+	return ret;
+}
+#endif
+
+static inline enum wifi_security_type nxp_wifi_key_mgmt_to_zephyr(int key_mgmt, int pwe)
+{
+	switch (key_mgmt) {
+	case WLAN_KEY_MGMT_NONE:
 		return WIFI_SECURITY_TYPE_NONE;
-	case WLAN_SECURITY_WPA2:
+	case WLAN_KEY_MGMT_PSK:
+		return WIFI_SECURITY_TYPE_PSK;
+	case WLAN_KEY_MGMT_PSK_SHA256:
+		return WIFI_SECURITY_TYPE_PSK_SHA256;
+	case WLAN_KEY_MGMT_PSK | WLAN_KEY_MGMT_PSK_SHA256:
 		return WIFI_SECURITY_TYPE_PSK;
-	case WLAN_SECURITY_WPA3_SAE:
+	case WLAN_KEY_MGMT_SAE:
+		if (pwe == 1) {
+			return WIFI_SECURITY_TYPE_SAE_H2E;
+		} else if (pwe == 2) {
+			return WIFI_SECURITY_TYPE_SAE_AUTO;
+		} else {
+			return WIFI_SECURITY_TYPE_SAE_HNP;
+		}
 		return WIFI_SECURITY_TYPE_SAE;
+	case WLAN_KEY_MGMT_SAE | WLAN_KEY_MGMT_PSK:
+		return WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL;
 	default:
 		return WIFI_SECURITY_TYPE_UNKNOWN;
 	}
@@ -1022,12 +1110,16 @@ static int nxp_wifi_uap_status(const struct device *dev, struct wifi_iface_statu
 
 			status->rssi = nxp_wlan_uap_network.rssi;
 
-			status->channel = nxp_wlan_uap_network.channel;
+			wlan_get_uap_channel(&status->channel);
 
 			status->beacon_interval = nxp_wlan_uap_network.beacon_period;
 
 			status->dtim_period = nxp_wlan_uap_network.dtim_period;
 
+#ifdef CONFIG_NXP_WIFI_11AX_TWT
+			status->twt_capable = true;
+#endif
+
 			if (if_handle->state.interface == WLAN_BSS_TYPE_STA) {
 				status->iface_mode = WIFI_MODE_INFRA;
 			} else if (if_handle->state.interface == WLAN_BSS_TYPE_UAP) {
@@ -1050,10 +1142,16 @@ static int nxp_wifi_uap_status(const struct device *dev, struct wifi_iface_statu
 				status->link_mode = WIFI_3;
 			}
 
-			status->band = nxp_wlan_uap_network.channel > 14 ? WIFI_FREQ_BAND_5_GHZ
-									 : WIFI_FREQ_BAND_2_4_GHZ;
-			status->security =
-				nxp_wifi_security_type(nxp_wlan_uap_network.security.type);
+			if (nxp_wlan_uap_network.channel != 0) {
+				status->band = nxp_wlan_uap_network.channel > 14 ?
+					WIFI_FREQ_BAND_5_GHZ : WIFI_FREQ_BAND_2_4_GHZ;
+			} else {
+				status->band = nxp_wlan_uap_network.acs_band;
+			}
+
+			status->security = nxp_wifi_key_mgmt_to_zephyr(
+				nxp_wlan_uap_network.security.key_mgmt,
+				nxp_wlan_uap_network.security.pwe_derivation);
 			status->mfp =
 				nxp_wlan_uap_network.security.mfpr
 					? WIFI_MFP_REQUIRED
@@ -1090,6 +1188,7 @@ static int nxp_wifi_status(const struct device *dev, struct wifi_iface_status *s
 	} else if (connection_state == WLAN_AUTHENTICATED
 			|| connection_state == WLAN_CONNECTED) {
 		status->state = WIFI_STATE_COMPLETED;
+		wlan_ds_rate ds_rate = {0};
 
 		if (!wlan_get_current_network(&nxp_wlan_network)) {
 			strncpy(status->ssid, nxp_wlan_network.ssid, WIFI_SSID_MAX_LEN - 1);
@@ -1133,19 +1232,58 @@ static int nxp_wifi_status(const struct device *dev, struct wifi_iface_status *s
 
 			status->band = nxp_wlan_network.channel > 14 ? WIFI_FREQ_BAND_5_GHZ
 								     : WIFI_FREQ_BAND_2_4_GHZ;
-			status->security = nxp_wifi_security_type(nxp_wlan_network.security.type);
+			status->security = nxp_wifi_key_mgmt_to_zephyr(
+				nxp_wlan_network.security.key_mgmt,
+				nxp_wlan_network.security.pwe_derivation);
 			status->mfp = nxp_wlan_network.security.mfpr ? WIFI_MFP_REQUIRED :
 				(nxp_wlan_network.security.mfpc ? WIFI_MFP_OPTIONAL : 0);
 		}
+		ds_rate.sub_command = WIFI_DS_GET_DATA_RATE;
+		if (!wlan_get_data_rate(&ds_rate, WLAN_BSS_TYPE_STA)) {
+			wifi_data_rate_t *datarate = (wifi_data_rate_t *)&ds_rate.param.data_rate;
+			int lg_rate[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54};
+
+			if (datarate->tx_rate_format == MLAN_RATE_FORMAT_LG &&
+			    datarate->tx_data_rate < 12) {
+				/* Legacy rates (in bps) */
+				/* Need to feed Zephyr L2 Wi-Fi with rate value in unit of Mbps*/
+				status->current_phy_tx_rate = lg_rate[datarate->tx_data_rate];
+			} else if (datarate->tx_rate_format <= 3) {
+				/* HT, VHT, HE rates (in bps) */
+				/* Need to feed Zephyr L2 Wi-Fi with rate value in unit of Mbps*/
+				status->current_phy_tx_rate = (datarate->tx_data_rate >> 1);
+			}
+		}
 	}
 
 	return 0;
 }
 
 #if defined(CONFIG_NET_STATISTICS_WIFI)
+#ifdef CONFIG_NXP_WIFI_GET_LOG
+static int nxp_wifi_get_detail_stats(int bss_type, wlan_pkt_stats_t *stats)
+{
+	int ret = -ENODEV;
+
+	if (bss_type == WLAN_BSS_TYPE_STA) {
+		ret = wlan_get_log(stats);
+	}
+#ifdef CONFIG_NXP_WIFI_SOFTAP_SUPPORT
+	else if (bss_type == WLAN_BSS_TYPE_UAP) {
+		ret = wlan_uap_get_log(stats);
+	}
+#endif
+	return ret;
+}
+#endif
+
 static int nxp_wifi_stats(const struct device *dev, struct net_stats_wifi *stats)
 {
 	struct interface *if_handle = (struct interface *)dev->data;
+#ifdef CONFIG_NXP_WIFI_GET_LOG
+	int ret;
+	wlan_pkt_stats_t *wifi_stats;
+#endif
 
 	stats->bytes.received = if_handle->stats.bytes.received;
 	stats->bytes.sent = if_handle->stats.bytes.sent;
@@ -1157,8 +1295,87 @@ static int nxp_wifi_stats(const struct device *dev, struct net_stats_wifi *stats
 	stats->broadcast.tx = if_handle->stats.broadcast.tx;
 	stats->multicast.rx = if_handle->stats.multicast.rx;
 	stats->multicast.tx = if_handle->stats.multicast.tx;
-	stats->sta_mgmt.beacons_rx = if_handle->stats.sta_mgmt.beacons_rx;
-	stats->sta_mgmt.beacons_miss = if_handle->stats.sta_mgmt.beacons_miss;
+	stats->unicast.rx = if_handle->stats.unicast.rx;
+	stats->unicast.tx = if_handle->stats.unicast.tx;
+	stats->overrun_count = if_handle->stats.errors.rx + if_handle->stats.errors.tx;
+
+	if (!net_if_is_admin_up(net_if_lookup_by_dev(dev))) {
+		return 0;
+	}
+
+#ifdef CONFIG_NXP_WIFI_GET_LOG
+	wifi_stats = k_malloc(sizeof(wlan_pkt_stats_t));
+	if (!wifi_stats) {
+		LOG_WRN("No mem for detailed statistics");
+		return 0;
+	}
+
+	memset(wifi_stats, 0, sizeof(wlan_pkt_stats_t));
+	ret = nxp_wifi_get_detail_stats(if_handle->state.interface, wifi_stats);
+	if (ret != 0) {
+		LOG_ERR("Get detailed statistics from Wi-Fi failed ret %d", ret);
+		k_free(wifi_stats);
+		return ret;
+	}
+
+	if (wifi_stats->bcn_rcv_cnt >= if_handle->stats.sta_mgmt.beacons_rx) {
+		stats->sta_mgmt.beacons_rx = wifi_stats->bcn_rcv_cnt -
+			if_handle->stats.sta_mgmt.beacons_rx;
+	} else {
+		/** we might have a new connection since last stats reset,
+		 *  so stored stats is invalid
+		 */
+		stats->sta_mgmt.beacons_rx = wifi_stats->bcn_rcv_cnt;
+	}
+
+	if (wifi_stats->bcn_miss_cnt >= if_handle->stats.sta_mgmt.beacons_miss) {
+		stats->sta_mgmt.beacons_miss = wifi_stats->bcn_miss_cnt -
+			if_handle->stats.sta_mgmt.beacons_miss;
+	} else {
+		stats->sta_mgmt.beacons_miss = wifi_stats->bcn_miss_cnt;
+	}
+
+	k_free(wifi_stats);
+#endif
+	return 0;
+}
+
+int nxp_wifi_reset_stats(const struct device *dev)
+{
+	struct interface *if_handle = (struct interface *)dev->data;
+#ifdef CONFIG_NXP_WIFI_GET_LOG
+	int ret;
+	wlan_pkt_stats_t *wifi_stats;
+#endif
+
+	/* clear local statistics */
+	memset(&if_handle->stats, 0, sizeof(if_handle->stats));
+
+	if (!net_if_is_admin_up(net_if_lookup_by_dev(dev))) {
+		return 0;
+	}
+
+#ifdef CONFIG_NXP_WIFI_GET_LOG
+	/* store firmware statistics */
+	wifi_stats = k_malloc(sizeof(wlan_pkt_stats_t));
+	if (!wifi_stats) {
+		LOG_WRN("No mem to reset detailed statistics");
+		return 0;
+	}
+
+	memset(wifi_stats, 0, sizeof(wlan_pkt_stats_t));
+	ret = nxp_wifi_get_detail_stats(if_handle->state.interface, wifi_stats);
+	if (ret != 0) {
+		LOG_ERR("Reset detailed statistics from Wi-Fi failed ret %d", ret);
+		k_free(wifi_stats);
+		return ret;
+	}
+
+	if_handle->stats.sta_mgmt.beacons_rx =  wifi_stats->bcn_rcv_cnt;
+	if_handle->stats.sta_mgmt.beacons_miss = wifi_stats->bcn_miss_cnt;
+
+	k_free(wifi_stats);
+#endif
 
 	return 0;
 }
@@ -1216,6 +1433,33 @@ static int nxp_wifi_11k_cfg(const struct device *dev, struct wifi_11k_params *pa
 
 	return 0;
 }
+
+static int nxp_wifi_11k_neighbor_request(const struct device *dev, struct wifi_11k_params *params)
+{
+	int ret = WM_SUCCESS;
+
+	if (params != NULL) {
+		if (strlen(params->ssid) > WIFI_SSID_MAX_LEN) {
+			LOG_ERR("ssid too long");
+			return -EINVAL;
+		}
+
+		ret = wlan_host_11k_neighbor_req(params->ssid);
+		if (ret != WM_SUCCESS) {
+			LOG_ERR("send neighbor report request fail");
+			return -EAGAIN;
+		}
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_NXP_WIFI_11V
+static int nxp_wifi_btm_query(const struct device *dev, uint8_t reason)
+{
+	return wlan_host_11v_bss_trans_query(reason);
+}
 #endif
 
 static int nxp_wifi_power_save(const struct device *dev, struct wifi_ps_params *params)
@@ -1523,6 +1767,7 @@ static int nxp_wifi_set_twt(const struct device *dev, struct wifi_twt_params *pa
 	return ret;
 }
 
+#ifdef CONFIG_NXP_WIFI_SOFTAP_SUPPORT
 static int nxp_wifi_set_btwt(const struct device *dev, struct wifi_twt_params *params)
 {
 	wlan_btwt_config_t btwt_config;
@@ -1539,6 +1784,7 @@ static int nxp_wifi_set_btwt(const struct device *dev, struct wifi_twt_params *p
 	return wlan_set_btwt_cfg(&btwt_config);
 }
 #endif
+#endif
 
 static int nxp_wifi_set_rts_threshold(const struct device *dev, unsigned int rts_threshold)
 {
@@ -1555,6 +1801,7 @@ static int nxp_wifi_set_rts_threshold(const struct device *dev, unsigned int rts
 	return ret;
 }
 
+#ifdef CONFIG_NXP_WIFI_SOFTAP_SUPPORT
 static int nxp_wifi_ap_set_rts_threshold(const struct device *dev, unsigned int rts_threshold)
 {
 	int ret = -1;
@@ -1569,6 +1816,7 @@ static int nxp_wifi_ap_set_rts_threshold(const struct device *dev, unsigned int
 
 	return ret;
 }
+#endif
 
 static void nxp_wifi_sta_init(struct net_if *iface)
 {
@@ -1669,6 +1917,8 @@ static NXP_WIFI_SET_FUNC_ATTR int nxp_wifi_send(const struct device *dev, struct
 		if_handle->stats.multicast.tx++;
 	} else if (net_eth_is_addr_broadcast(&hdr->dst)) {
 		if_handle->stats.broadcast.tx++;
+	} else {
+		if_handle->stats.unicast.tx++;
 	}
 #endif
 
@@ -1698,6 +1948,8 @@ static NXP_WIFI_SET_FUNC_ATTR int nxp_wifi_recv(struct net_if *iface, struct net
 		if_handle->stats.broadcast.rx++;
 	} else if (net_eth_is_addr_multicast(&hdr->dst)) {
 		if_handle->stats.multicast.rx++;
+	} else {
+		if_handle->stats.unicast.rx++;
 	}
 
 	if_handle->stats.bytes.received += pkt_len;
@@ -1863,9 +2115,14 @@ static const struct wifi_mgmt_ops nxp_wifi_sta_mgmt = {
 	.iface_status = nxp_wifi_status,
 #if defined(CONFIG_NET_STATISTICS_WIFI)
 	.get_stats = nxp_wifi_stats,
+	.reset_stats = nxp_wifi_reset_stats,
 #endif
 #ifdef CONFIG_NXP_WIFI_11K
 	.cfg_11k = nxp_wifi_11k_cfg,
+	.send_11k_neighbor_request = nxp_wifi_11k_neighbor_request,
+#endif
+#ifdef CONFIG_NXP_WIFI_11V
+	.btm_query = nxp_wifi_btm_query,
 #endif
 	.set_power_save = nxp_wifi_power_save,
 	.get_power_save_config = nxp_wifi_get_power_save,
@@ -1944,6 +2201,7 @@ static const struct wifi_mgmt_ops nxp_wifi_uap_mgmt = {
 	.iface_status = nxp_wifi_uap_status,
 #if defined(CONFIG_NET_STATISTICS_WIFI)
 	.get_stats = nxp_wifi_stats,
+	.reset_stats = nxp_wifi_reset_stats,
 #endif
 	.set_power_save = nxp_wifi_power_save,
 	.get_power_save_config = nxp_wifi_get_power_save,
@@ -1951,6 +2209,7 @@ static const struct wifi_mgmt_ops nxp_wifi_uap_mgmt = {
 #ifdef CONFIG_NXP_WIFI_11AX_TWT
 	.set_btwt = nxp_wifi_set_btwt,
 #endif
+	.ap_sta_disconnect = nxp_wifi_uap_disconnect_sta,
 	.set_rts_threshold = nxp_wifi_ap_set_rts_threshold,
 };
 
diff --git a/drivers/wifi/nxp/nxp_wifi_drv.h b/drivers/wifi/nxp/nxp_wifi_drv.h
index d4c1620e8ad..f7dd1955783 100644
--- a/drivers/wifi/nxp/nxp_wifi_drv.h
+++ b/drivers/wifi/nxp/nxp_wifi_drv.h
@@ -48,6 +48,9 @@
 #define NXP_WIFI_SYNC_PS_GROUP                                                                     \
 	NXP_WIFI_EVENT_BIT(WLAN_REASON_PS_ENTER) | NXP_WIFI_EVENT_BIT(WLAN_REASON_PS_EXIT)
 
+#define NXP_WIFI_SAP_BEACON_PERIOD_DEFAULT 100
+#define NXP_WIFI_SAP_DTIM_PERIOD_DEFAULT 1
+
 enum nxp_wifi_ret {
 	NXP_WIFI_RET_SUCCESS,
 	NXP_WIFI_RET_FAIL,
diff --git a/drivers/wifi/siwx91x/CMakeLists.txt b/drivers/wifi/siwx91x/CMakeLists.txt
new file mode 100644
index 00000000000..4085341bca0
--- /dev/null
+++ b/drivers/wifi/siwx91x/CMakeLists.txt
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2024 Silicon Laboratories Inc.
+
+if(CONFIG_WIFI_SILABS_SIWX91X)
+  zephyr_library_sources(siwx91x_wifi.c)
+
+  if(CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_OFFLOAD)
+    zephyr_library_sources(siwx91x_wifi_socket.c)
+  endif()
+endif()
diff --git a/drivers/wifi/siwx91x/Kconfig.siwx91x b/drivers/wifi/siwx91x/Kconfig.siwx91x
new file mode 100644
index 00000000000..e1ece13c9b9
--- /dev/null
+++ b/drivers/wifi/siwx91x/Kconfig.siwx91x
@@ -0,0 +1,154 @@
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config WIFI_SILABS_SIWX91X
+	bool "Silabs SiWx91x SoC series WiFi driver"
+	default y
+	depends on DT_HAS_SILABS_SIWX91X_WIFI_ENABLED
+	depends on NETWORKING
+	select WISECONNECT_NETWORK_STACK
+	select EVENTS
+	select NET_L2_WIFI_MGMT
+	help
+	  Enable WiFi driver for the Silabs SiWx91x SoC series.
+
+if WIFI_SILABS_SIWX91X
+
+choice
+	prompt "Network stack"
+	default WIFI_SILABS_SIWX91X_NET_STACK_NATIVE
+	help
+	  Choose "Native" stack if you want a better compatibility with Zephyr
+	  features. "Offloaded" stack may provide better resource (power and
+	  memory) consumption.
+
+config WIFI_SILABS_SIWX91X_NET_STACK_NATIVE
+	bool "Native"
+	select WIFI_USE_NATIVE_NETWORKING
+	select NET_L2_ETHERNET
+
+config WIFI_SILABS_SIWX91X_NET_STACK_OFFLOAD
+	bool "Offloaded"
+	select WIFI_OFFLOAD
+
+endchoice
+
+config NET_TCP_WORKQ_STACK_SIZE
+	default 2048
+
+config NET_RX_STACK_SIZE
+	default 2048
+
+config NET_MGMT_EVENT_STACK_SIZE
+	default 2048
+
+config NET_MGMT_EVENT_QUEUE_SIZE
+	default 10
+
+config WIFI_SILABS_SIWX91X_ENABLE_ROAMING
+	bool "WiFi roaming support"
+	help
+	  Enable this option to configure roaming parameters.
+	  Roaming will be enabled automatically when the
+	  background scan is active, improving connectivity
+	  and performance during transitions between access points.
+
+config WIFI_SILABS_SIWX91X_ROAMING_USE_DEAUTH
+	bool "Use deauth frames for roaming"
+	depends on WIFI_SILABS_SIWX91X_ENABLE_ROAMING
+	help
+	  Enable this option to allow roaming using
+	  deauthentication frames. By default, roaming
+	  is performed using Null data packets.
+
+config WIFI_SILABS_SIWX91X_ROAMING_TRIGGER_LEVEL
+	int "Default value of roam trigger level (in dBm)"
+	default -70
+	range -10 -100
+	depends on WIFI_SILABS_SIWX91X_ENABLE_ROAMING
+	help
+	  Sets the default roam trigger level. Higher values trigger
+	  earlier roaming; lower values delay it. It determines
+	  when to start searching for a new AP.
+
+config WIFI_SILABS_SIWX91X_ROAMING_TRIGGER_LEVEL_CHANGE
+	int "Default value of roam trigger level change (in dBm)"
+	default 5
+	range 0 90
+	depends on WIFI_SILABS_SIWX91X_ENABLE_ROAMING
+	help
+	  Configure the default trigger level change for WiFi roaming.
+	  This value determines the change in signal strength (in dBm)
+	  required to initiate a roaming event. A smaller value may result
+	  in more sensitive roaming behavior, while a larger value can
+	  reduce the frequency of roaming events. It determines
+	  the signal difference needed to switch to a new AP.
+
+config WIFI_SILABS_SIWX91X_ADV_SCAN_THRESHOLD
+	int "Advanced scan threshold (in dBm)"
+	default -40
+	help
+	  Configure the default advanced scan threshold for WiFi scanning.
+	  This value determines the signal strength (in dBm) below which
+	  the advanced scan mechanism will be triggered. Adjust this value
+	  to optimize scanning behavior based on your network environment.
+
+config WIFI_SILABS_SIWX91X_ADV_RSSI_TOLERANCE_THRESHOLD
+	int "Advanced RSSI tolerance threshold (in dBm)"
+	default 5
+	help
+	  Configure the default RSSI tolerance threshold for advanced WiFi scanning.
+	  This value determines the acceptable variation in signal strength (in dBm)
+	  during advanced scanning. Adjust this value to fine-tune the sensitivity
+	  of the scanning mechanism to signal fluctuations.
+
+config WIFI_SILABS_SIWX91X_ADV_ACTIVE_SCAN_DURATION
+	int "Advanced active scan duration (in ms)"
+	default 15
+	help
+	  Configure the default advanced active scan duration for WiFi scanning.
+	  This value determines the time (in milliseconds) spent on each
+	  channel during an advanced active scan. Adjust this value to optimize
+	  scanning speed and accuracy based on your network environment.
+
+config WIFI_SILABS_SIWX91X_ADV_PASSIVE_SCAN_DURATION
+	int "Advanced passive scan duration (in ms)"
+	default 20
+	help
+	  Configure the default advanced passive scan duration for WiFi scanning.
+	  This value determines the time (in milliseconds) spent on each
+	  channel during an advanced passive scan. Adjust this value to optimize
+	  scanning speed and accuracy based on your network environment.
+
+config WIFI_SILABS_SIWX91X_ADV_MULTIPROBE
+	int "Advanced multiprobe setting"
+	default 0
+	help
+	  Configure the advanced multiprobe setting for WiFi scanning.
+	  When set to 1, multiple probe requests will be sent to all access
+	  points in addition to the connected SSID during scanning. Adjust
+	  this value to fine-tune scanning behavior based on your network
+	  requirements.
+
+config WIFI_SILABS_SIWX91X_ADV_SCAN_PERIODICITY
+	int "Advanced scan periodicity (in ms)"
+	default 10
+	help
+	  Configure the default advanced scan periodicity for WiFi scanning.
+	  This value determines the interval (in milliseconds) between consecutive
+	  advanced scans. Adjust this value to balance scanning frequency
+	  and power consumption based on your network environment.
+
+config WIFI_SILABS_SIWX91X_ENABLE_INSTANT_SCAN
+	int "Instant scan support"
+	default 1
+	help
+	  Enable support to start an advanced scan immediately. When enabled, the device
+	  can perform an advanced scan without waiting for the periodic
+	  scan interval, enabling quicker detection of available networks.
+
+# Override the WIFI_MGMT_SCAN_SSID_FILT_MAX parameter for the Wi-Fi subsystem.
+# This device supports filtering scan results for only one SSID.
+config WIFI_MGMT_SCAN_SSID_FILT_MAX
+	default 1
+endif
diff --git a/drivers/wifi/siwx91x/siwx91x_wifi.c b/drivers/wifi/siwx91x/siwx91x_wifi.c
new file mode 100644
index 00000000000..e86b4f6fd0b
--- /dev/null
+++ b/drivers/wifi/siwx91x/siwx91x_wifi.c
@@ -0,0 +1,1003 @@
+/*
+ * Copyright (c) 2023 Antmicro
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#define DT_DRV_COMPAT silabs_siwx91x_wifi
+
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/version.h>
+
+#include <nwp.h>
+#include "siwx91x_wifi.h"
+#include "siwx91x_wifi_socket.h"
+
+#include "sl_rsi_utility.h"
+#include "sl_net_constants.h"
+#include "sl_wifi_types.h"
+#include "sl_wifi_callback_framework.h"
+#include "sl_net_default_values.h"
+#include "sl_wifi.h"
+#include "sl_net.h"
+#include "sl_wifi_constants.h"
+
+#define SIWX91X_DRIVER_VERSION KERNEL_VERSION_STRING
+
+LOG_MODULE_REGISTER(siwx91x_wifi);
+
+NET_BUF_POOL_FIXED_DEFINE(siwx91x_tx_pool, 1, _NET_ETH_MAX_FRAME_SIZE, 0, NULL);
+
+static int siwx91x_sl_to_z_mode(sl_wifi_interface_t interface)
+{
+	switch (interface) {
+	case SL_WIFI_CLIENT_INTERFACE:
+		return WIFI_STA_MODE;
+	case SL_WIFI_AP_INTERFACE:
+		return WIFI_AP_MODE;
+	default:
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int siwx91x_bandwidth(enum wifi_frequency_bandwidths bandwidth)
+{
+	switch (bandwidth) {
+	case WIFI_FREQ_BANDWIDTH_20MHZ:
+		return SL_WIFI_BANDWIDTH_20MHz;
+	case WIFI_FREQ_BANDWIDTH_40MHZ:
+		return SL_WIFI_BANDWIDTH_40MHz;
+	case WIFI_FREQ_BANDWIDTH_80MHZ:
+		return SL_WIFI_BANDWIDTH_80MHz;
+	default:
+		return -EINVAL;
+	}
+}
+
+static int siwx91x_map_ap_security(enum wifi_security_type security)
+{
+	switch (security) {
+	case WIFI_SECURITY_TYPE_NONE:
+		return SL_WIFI_OPEN;
+	case WIFI_SECURITY_TYPE_WPA_PSK:
+		return SL_WIFI_WPA;
+	case WIFI_SECURITY_TYPE_PSK:
+		return SL_WIFI_WPA2;
+	case WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL:
+		return SL_WIFI_WPA_WPA2_MIXED;
+	default:
+		return -EINVAL;
+	}
+}
+
+static enum wifi_mfp_options siwx91x_set_sta_mfp_option(sl_wifi_security_t security,
+							enum wifi_mfp_options mfp_conf)
+{
+	uint8_t join_config;
+
+	switch (security) {
+	case SL_WIFI_OPEN:
+	case SL_WIFI_WPA:
+		return WIFI_MFP_DISABLE;
+	case SL_WIFI_WPA2:
+	case SL_WIFI_WPA_WPA2_MIXED:
+		if (mfp_conf == WIFI_MFP_REQUIRED) {
+			/* Handling the case for WPA2_SHA256 security type */
+			/* Directly enabling the MFP Required bit in the Join Feature
+			 * bitmap. This ensures that MFP is enforced for connections using
+			 * WPA2_SHA256.
+			 *
+			 * Note: This is a workaround to configure MFP as the current SDK
+			 * does not provide a dedicated API to configure MFP settings.
+			 * By manipulating the join feature bitmap directly, we achieve
+			 * the desired MFP configuration for enhanced security.
+			 *
+			 * This case will be updated in the future when the SDK adds
+			 * dedicated support for configuring MFP.
+			 */
+			sl_si91x_get_join_configuration(SL_WIFI_CLIENT_INTERFACE, &join_config);
+			join_config |= SL_SI91X_JOIN_FEAT_MFP_CAPABLE_REQUIRED;
+			sl_si91x_set_join_configuration(SL_WIFI_CLIENT_INTERFACE, join_config);
+			return WIFI_MFP_REQUIRED;
+		}
+		/* Handling the case for WPA2 security type */
+		/* Ensuring the connection happened in WPA2-PSK
+		 * by clearing the MFP Required bit in the Join Feature bitmap.
+		 */
+		sl_si91x_get_join_configuration(SL_WIFI_CLIENT_INTERFACE, &join_config);
+		join_config &= ~(SL_SI91X_JOIN_FEAT_MFP_CAPABLE_REQUIRED);
+		sl_si91x_set_join_configuration(SL_WIFI_CLIENT_INTERFACE, join_config);
+		return WIFI_MFP_OPTIONAL;
+	case SL_WIFI_WPA3:
+		return WIFI_MFP_REQUIRED;
+	case SL_WIFI_WPA3_TRANSITION:
+		return WIFI_MFP_OPTIONAL;
+	default:
+		return WIFI_MFP_DISABLE;
+	}
+
+	return WIFI_MFP_UNKNOWN;
+}
+
+static unsigned int siwx91x_on_join(sl_wifi_event_t event,
+				    char *result, uint32_t result_size, void *arg)
+{
+	struct siwx91x_dev *sidev = arg;
+
+	if (*result != 'C') {
+		/* TODO: report the real reason of failure */
+		wifi_mgmt_raise_connect_result_event(sidev->iface, WIFI_STATUS_CONN_FAIL);
+		sidev->state = WIFI_STATE_INACTIVE;
+		return 0;
+	}
+
+	wifi_mgmt_raise_connect_result_event(sidev->iface, WIFI_STATUS_CONN_SUCCESS);
+	sidev->state = WIFI_STATE_COMPLETED;
+
+	if (IS_ENABLED(CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_NATIVE)) {
+		net_if_dormant_off(sidev->iface);
+	}
+
+	siwx91x_on_join_ipv4(sidev);
+	siwx91x_on_join_ipv6(sidev);
+
+	return 0;
+}
+
+static int siwx91x_ap_enable(const struct device *dev, struct wifi_connect_req_params *params)
+{
+	struct siwx91x_dev *sidev = dev->data;
+	/* Wiseconnect requires a valid PSK even if WIFI_SECURITY_TYPE_NONE is selected */
+	static const char dummy_psk[] = "dummy_value";
+	sl_status_t ret;
+	int sec;
+
+	sl_wifi_ap_configuration_t siwx91x_ap_cfg = {
+		.credential_id       = SL_NET_DEFAULT_WIFI_AP_CREDENTIAL_ID,
+		.keepalive_type      = SL_SI91X_AP_NULL_BASED_KEEP_ALIVE,
+		.rate_protocol       = SL_WIFI_RATE_PROTOCOL_AUTO,
+		.encryption          = SL_WIFI_DEFAULT_ENCRYPTION,
+		.ssid.length         = params->ssid_length,
+		.tdi_flags           = SL_WIFI_TDI_NONE,
+		.client_idle_timeout = 0xFF,
+		.beacon_interval     = 100,
+		.dtim_beacon_count   = 3,
+		.maximum_clients     = 4,
+		.beacon_stop         = 0,
+		.options             = 0,
+		.is_11n_enabled      = 1,
+	};
+
+	if (params->band != WIFI_FREQ_BAND_UNKNOWN && params->band != WIFI_FREQ_BAND_2_4_GHZ) {
+		return -ENOTSUP;
+	}
+
+	if (params->channel == WIFI_CHANNEL_ANY) {
+		siwx91x_ap_cfg.channel.channel = SL_WIFI_AUTO_CHANNEL;
+	} else {
+		siwx91x_ap_cfg.channel.channel = params->channel;
+	}
+
+	if (siwx91x_bandwidth(params->bandwidth) < 0) {
+		return -EINVAL;
+	}
+
+	siwx91x_ap_cfg.channel.bandwidth = siwx91x_bandwidth(params->bandwidth);
+	strncpy(siwx91x_ap_cfg.ssid.value, params->ssid, params->ssid_length);
+
+	sec = siwx91x_map_ap_security(params->security);
+	if (sec < 0) {
+		LOG_ERR("Invalid security type");
+		return -EINVAL;
+	}
+
+	siwx91x_ap_cfg.security = sec;
+
+	if (params->security == WIFI_SECURITY_TYPE_NONE) {
+		ret = sl_net_set_credential(siwx91x_ap_cfg.credential_id, SL_NET_WIFI_PSK,
+					    dummy_psk, strlen(dummy_psk));
+	} else {
+		ret = sl_net_set_credential(siwx91x_ap_cfg.credential_id, SL_NET_WIFI_PSK,
+					    params->psk, params->psk_length);
+	}
+
+	if (ret != SL_STATUS_OK) {
+		return -EINVAL;
+	}
+
+	if (params->mfp != WIFI_MFP_DISABLE) {
+		LOG_WRN("Needed MFP disable but got MFP %s, hence setting to MFP disable",
+			wifi_mfp_txt(params->mfp));
+	}
+
+	ret = sl_wifi_start_ap(SL_WIFI_AP_INTERFACE | SL_WIFI_2_4GHZ_INTERFACE, &siwx91x_ap_cfg);
+	if (ret != SL_STATUS_OK) {
+		LOG_ERR("Failed to enable AP mode: 0x%x", ret);
+		return -EIO;
+	}
+
+	sidev->state = WIFI_STATE_COMPLETED;
+	return 0;
+}
+
+static int siwx91x_ap_disable(const struct device *dev)
+{
+	struct siwx91x_dev *sidev = dev->data;
+	int ret;
+
+	ret = sl_wifi_stop_ap(SL_WIFI_AP_2_4GHZ_INTERFACE);
+	if (ret) {
+		LOG_ERR("Failed to disable Wi-Fi AP mode: 0x%x", ret);
+		return -EIO;
+	}
+
+	sidev->state = WIFI_STATE_INTERFACE_DISABLED;
+	return ret;
+}
+
+static int siwx91x_ap_sta_disconnect(const struct device *dev, const uint8_t *mac_addr)
+{
+	ARG_UNUSED(dev);
+	sl_mac_address_t mac = { };
+	int ret;
+
+	__ASSERT(mac_addr, "mac_addr cannot be NULL");
+
+	memcpy(mac.octet, mac_addr, ARRAY_SIZE(mac.octet));
+
+	ret = sl_wifi_disconnect_ap_client(SL_WIFI_AP_INTERFACE | SL_WIFI_2_4GHZ_INTERFACE,
+					  &mac, SL_WIFI_DEAUTH);
+	if (ret) {
+		LOG_ERR("Failed	to disconnect: 0x%x", ret);
+		return -EIO;
+	}
+
+	return ret;
+}
+
+static sl_status_t siwx91x_on_ap_sta_connect(sl_wifi_event_t event, void *data,
+					     uint32_t data_length, void *arg)
+{
+	ARG_UNUSED(event);
+	struct siwx91x_dev *sidev = arg;
+	struct wifi_ap_sta_info sta_info = { };
+
+	__ASSERT(data, "data cannot be NULL");
+	__ASSERT(arg, "arg cannot be NULL");
+
+	memcpy(sta_info.mac, data, data_length);
+	sta_info.mac_length = data_length;
+	sta_info.link_mode = WIFI_LINK_MODE_UNKNOWN;
+
+	wifi_mgmt_raise_ap_sta_connected_event(sidev->iface, &sta_info);
+
+	return SL_STATUS_OK;
+}
+
+static sl_status_t siwx91x_on_ap_sta_disconnect(sl_wifi_event_t event, void *data,
+						uint32_t data_length, void *arg)
+{
+	ARG_UNUSED(event);
+	struct siwx91x_dev *sidev = arg;
+	struct wifi_ap_sta_info sta_info = { };
+
+	__ASSERT(data, "data cannot be NULL");
+	__ASSERT(arg, "arg cannot be NULL");
+
+	memcpy(sta_info.mac, data, data_length);
+	sta_info.mac_length = data_length;
+	wifi_mgmt_raise_ap_sta_disconnected_event(sidev->iface, &sta_info);
+
+	return SL_STATUS_OK;
+}
+
+static int siwx91x_connect(const struct device *dev, struct wifi_connect_req_params *params)
+{
+	sl_wifi_client_configuration_t wifi_config = {
+		.bss_type = SL_WIFI_BSS_TYPE_INFRASTRUCTURE,
+		.encryption = SL_WIFI_DEFAULT_ENCRYPTION,
+		.credential_id = SL_NET_DEFAULT_WIFI_CLIENT_CREDENTIAL_ID,
+	};
+	enum wifi_mfp_options mfp_conf;
+	int ret = 0;
+
+	switch (params->security) {
+	case WIFI_SECURITY_TYPE_NONE:
+		wifi_config.security = SL_WIFI_OPEN;
+		break;
+	case WIFI_SECURITY_TYPE_WPA_PSK:
+		wifi_config.security = SL_WIFI_WPA;
+		break;
+	case WIFI_SECURITY_TYPE_PSK:
+		/* This case is meant to fall through to the next */
+	case WIFI_SECURITY_TYPE_PSK_SHA256:
+		/* Use WPA2 security as the device supports only SHA256
+		 * key derivation for WPA2-PSK
+		 */
+		wifi_config.security = SL_WIFI_WPA2;
+		break;
+	case WIFI_SECURITY_TYPE_SAE_AUTO:
+		/* Use WPA3 security as the device supports only HNP and H2E
+		 * methods for SAE
+		 */
+		wifi_config.security = SL_WIFI_WPA3;
+		break;
+	case WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL:
+		/* Use WPA2/WPA3 security as the device supports both */
+		wifi_config.security = SL_WIFI_WPA3_TRANSITION;
+		break;
+	/* Zephyr WiFi shell doesn't specify how to pass credential for these
+	 * key managements.
+	 */
+	case WIFI_SECURITY_TYPE_WEP: /* SL_WIFI_WEP/SL_WIFI_WEP_ENCRYPTION */
+	case WIFI_SECURITY_TYPE_EAP: /* SL_WIFI_WPA2_ENTERPRISE/<various> */
+	case WIFI_SECURITY_TYPE_WAPI:
+	default:
+		return -ENOTSUP;
+	}
+
+	if (params->band != WIFI_FREQ_BAND_UNKNOWN && params->band != WIFI_FREQ_BAND_2_4_GHZ) {
+		return -ENOTSUP;
+	}
+
+	if (params->psk_length) {
+		ret = sl_net_set_credential(SL_NET_DEFAULT_WIFI_CLIENT_CREDENTIAL_ID,
+					    SL_NET_WIFI_PSK, params->psk, params->psk_length);
+	} else if (params->sae_password_length) {
+		ret = sl_net_set_credential(SL_NET_DEFAULT_WIFI_CLIENT_CREDENTIAL_ID,
+					    SL_NET_WIFI_PSK, params->sae_password,
+					    params->sae_password_length);
+	}
+
+	if (ret != SL_STATUS_OK) {
+		LOG_ERR("Failed to set credentials: 0x%x", ret);
+		return -EINVAL;
+	}
+
+	if (params->security == WIFI_SECURITY_TYPE_PSK_SHA256) {
+		mfp_conf = siwx91x_set_sta_mfp_option(wifi_config.security, WIFI_MFP_REQUIRED);
+	} else {
+		mfp_conf = siwx91x_set_sta_mfp_option(wifi_config.security, params->mfp);
+	}
+
+	if (params->mfp != mfp_conf) {
+		LOG_WRN("Needed MFP %s but got MFP %s, hence setting to MFP %s",
+			wifi_mfp_txt(mfp_conf), wifi_mfp_txt(params->mfp), wifi_mfp_txt(mfp_conf));
+	}
+
+	if (params->channel != WIFI_CHANNEL_ANY) {
+		wifi_config.channel.channel = params->channel;
+	}
+
+	wifi_config.ssid.length = params->ssid_length,
+	memcpy(wifi_config.ssid.value, params->ssid, params->ssid_length);
+
+	ret = sl_wifi_connect(SL_WIFI_CLIENT_INTERFACE, &wifi_config, 0);
+	if (ret != SL_STATUS_IN_PROGRESS) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int siwx91x_disconnect(const struct device *dev)
+{
+	struct siwx91x_dev *sidev = dev->data;
+	int ret;
+
+	ret = sl_wifi_disconnect(SL_WIFI_CLIENT_INTERFACE);
+	if (ret) {
+		return -EIO;
+	}
+	if (IS_ENABLED(CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_NATIVE)) {
+		net_if_dormant_on(sidev->iface);
+	}
+	sidev->state = WIFI_STATE_DISCONNECTED;
+	return 0;
+}
+
+static void siwx91x_report_scan_res(struct siwx91x_dev *sidev, sl_wifi_scan_result_t *result,
+				    int item)
+{
+	static const struct {
+		int sl_val;
+		int z_val;
+	} security_convert[] = {
+		{ SL_WIFI_OPEN,            WIFI_SECURITY_TYPE_NONE    },
+		{ SL_WIFI_WEP,             WIFI_SECURITY_TYPE_WEP     },
+		{ SL_WIFI_WPA,             WIFI_SECURITY_TYPE_WPA_PSK },
+		{ SL_WIFI_WPA2,            WIFI_SECURITY_TYPE_PSK     },
+		{ SL_WIFI_WPA3,            WIFI_SECURITY_TYPE_SAE     },
+		{ SL_WIFI_WPA3_TRANSITION, WIFI_SECURITY_TYPE_SAE     },
+		{ SL_WIFI_WPA_ENTERPRISE,  WIFI_SECURITY_TYPE_EAP     },
+		{ SL_WIFI_WPA2_ENTERPRISE, WIFI_SECURITY_TYPE_EAP     },
+	};
+
+	struct wifi_scan_result tmp = {
+		.channel = result->scan_info[item].rf_channel,
+		.rssi = result->scan_info[item].rssi_val,
+		.ssid_length = strlen(result->scan_info[item].ssid),
+		.mac_length = sizeof(result->scan_info[item].bssid),
+		.security = WIFI_SECURITY_TYPE_UNKNOWN,
+		.mfp = WIFI_MFP_UNKNOWN,
+		.band = WIFI_FREQ_BAND_2_4_GHZ,
+	};
+
+	if (result->scan_count == 0) {
+		return;
+	}
+
+	if (result->scan_info[item].rf_channel <= 0 || result->scan_info[item].rf_channel > 14) {
+		LOG_WRN("Unexpected scan result");
+		tmp.band = WIFI_FREQ_BAND_UNKNOWN;
+	}
+
+	memcpy(tmp.ssid, result->scan_info[item].ssid, tmp.ssid_length);
+	memcpy(tmp.mac, result->scan_info[item].bssid, tmp.mac_length);
+
+	ARRAY_FOR_EACH(security_convert, i) {
+		if (security_convert[i].sl_val == result->scan_info[item].security_mode) {
+			tmp.security = security_convert[i].z_val;
+		}
+	}
+
+	sidev->scan_res_cb(sidev->iface, 0, &tmp);
+}
+
+static unsigned int siwx91x_on_scan(sl_wifi_event_t event, sl_wifi_scan_result_t *result,
+				    uint32_t result_size, void *arg)
+{
+	struct siwx91x_dev *sidev = arg;
+	int i, scan_count;
+
+	if (!sidev->scan_res_cb) {
+		return -EFAULT;
+	}
+
+	if (event & SL_WIFI_EVENT_FAIL_INDICATION) {
+		memset(result, 0, sizeof(*result));
+	}
+
+	if (sidev->scan_max_bss_cnt) {
+		scan_count = MIN(result->scan_count, sidev->scan_max_bss_cnt);
+	} else {
+		scan_count = result->scan_count;
+	}
+
+	for (i = 0; i < scan_count; i++) {
+		siwx91x_report_scan_res(sidev, result, i);
+	}
+
+	sidev->scan_res_cb(sidev->iface, 0, NULL);
+	sidev->state = sidev->scan_prev_state;
+
+	return 0;
+}
+
+static int
+siwx91x_configure_scan_dwell_time(sl_wifi_scan_type_t scan_type, uint16_t dwell_time_active,
+				  uint16_t dwell_time_passive,
+				  sl_wifi_advanced_scan_configuration_t *advanced_scan_config)
+{
+	int ret = 0;
+
+	if (dwell_time_active && (dwell_time_active < 5 || dwell_time_active > 1000)) {
+		LOG_ERR("Invalid active scan dwell time");
+		return -EINVAL;
+	}
+
+	if (dwell_time_passive && (dwell_time_passive < 10 || dwell_time_passive > 1000)) {
+		LOG_ERR("Invalid passive scan dwell time");
+		return -EINVAL;
+	}
+
+	switch (scan_type) {
+	case SL_WIFI_SCAN_TYPE_ACTIVE:
+		if (!dwell_time_active) {
+			dwell_time_active = SL_WIFI_DEFAULT_ACTIVE_CHANNEL_SCAN_TIME;
+		}
+		ret = sl_si91x_configure_timeout(SL_SI91X_CHANNEL_ACTIVE_SCAN_TIMEOUT,
+						 dwell_time_active);
+		break;
+	case SL_WIFI_SCAN_TYPE_PASSIVE:
+		if (!dwell_time_passive) {
+			dwell_time_passive = SL_WIFI_DEFAULT_PASSIVE_CHANNEL_SCAN_TIME;
+		}
+		ret = sl_si91x_configure_timeout(SL_SI91X_CHANNEL_PASSIVE_SCAN_TIMEOUT,
+						 dwell_time_passive);
+		break;
+	case SL_WIFI_SCAN_TYPE_ADV_SCAN:
+		__ASSERT(advanced_scan_config, "advanced_scan_config cannot be NULL");
+
+		if (!dwell_time_active) {
+			dwell_time_active = CONFIG_WIFI_SILABS_SIWX91X_ADV_ACTIVE_SCAN_DURATION;
+		}
+		advanced_scan_config->active_channel_time = dwell_time_active;
+
+		if (!dwell_time_passive) {
+			dwell_time_passive = CONFIG_WIFI_SILABS_SIWX91X_ADV_PASSIVE_SCAN_DURATION;
+		}
+		advanced_scan_config->passive_channel_time = dwell_time_passive;
+		break;
+	default:
+		break;
+	}
+
+	return ret;
+}
+
+static int siwx91x_scan(const struct device *dev, struct wifi_scan_params *z_scan_config,
+			scan_result_cb_t cb)
+{
+	sl_wifi_scan_configuration_t sl_scan_config = { };
+	sl_wifi_advanced_scan_configuration_t advanced_scan_config = {
+		.trigger_level = CONFIG_WIFI_SILABS_SIWX91X_ADV_SCAN_THRESHOLD,
+		.trigger_level_change = CONFIG_WIFI_SILABS_SIWX91X_ADV_RSSI_TOLERANCE_THRESHOLD,
+		.enable_multi_probe = CONFIG_WIFI_SILABS_SIWX91X_ADV_MULTIPROBE,
+		.enable_instant_scan = CONFIG_WIFI_SILABS_SIWX91X_ENABLE_INSTANT_SCAN,
+	};
+	sl_wifi_roam_configuration_t roam_configuration = {
+#ifdef CONFIG_WIFI_SILABS_SIWX91X_ENABLE_ROAMING
+		.trigger_level = CONFIG_WIFI_SILABS_SIWX91X_ROAMING_TRIGGER_LEVEL,
+		.trigger_level_change = CONFIG_WIFI_SILABS_SIWX91X_ROAMING_TRIGGER_LEVEL_CHANGE,
+#else
+		.trigger_level = SL_WIFI_NEVER_ROAM,
+		.trigger_level_change = 0,
+#endif
+	};
+	struct siwx91x_dev *sidev = dev->data;
+	sl_wifi_interface_t interface;
+	sl_wifi_ssid_t ssid = { };
+	int ret;
+
+	__ASSERT(z_scan_config, "z_scan_config cannot be NULL");
+
+	interface = sl_wifi_get_default_interface();
+	if (FIELD_GET(SIWX91X_INTERFACE_MASK, interface) != SL_WIFI_CLIENT_INTERFACE) {
+		LOG_ERR("Interface not in STA mode");
+		return -EINVAL;
+	}
+
+	if (sidev->state != WIFI_STATE_DISCONNECTED && sidev->state != WIFI_STATE_INACTIVE &&
+	    sidev->state != WIFI_STATE_COMPLETED) {
+		LOG_ERR("Command given in invalid state");
+		return -EBUSY;
+	}
+
+	if (z_scan_config->bands & ~(BIT(WIFI_FREQ_BAND_UNKNOWN) | BIT(WIFI_FREQ_BAND_2_4_GHZ))) {
+		LOG_ERR("Invalid band entered");
+		return -EINVAL;
+	}
+
+	if (sidev->state == WIFI_STATE_COMPLETED) {
+		siwx91x_configure_scan_dwell_time(SL_WIFI_SCAN_TYPE_ADV_SCAN,
+						  z_scan_config->dwell_time_active,
+						  z_scan_config->dwell_time_passive,
+						  &advanced_scan_config);
+
+		ret = sl_wifi_set_advanced_scan_configuration(&advanced_scan_config);
+		if (ret != SL_STATUS_OK) {
+			LOG_ERR("advanced scan configuration failed with status %x", ret);
+			return -EINVAL;
+		}
+
+		ret = sl_wifi_set_roam_configuration(interface, &roam_configuration);
+		if (ret != SL_STATUS_OK) {
+			LOG_ERR("roaming configuration failed with status %x", ret);
+			return -EINVAL;
+		}
+
+		sl_scan_config.type = SL_WIFI_SCAN_TYPE_ADV_SCAN;
+		sl_scan_config.periodic_scan_interval =
+			CONFIG_WIFI_SILABS_SIWX91X_ADV_SCAN_PERIODICITY;
+	} else {
+		if (z_scan_config->scan_type == WIFI_SCAN_TYPE_ACTIVE) {
+			sl_scan_config.type = SL_WIFI_SCAN_TYPE_ACTIVE;
+			ret = siwx91x_configure_scan_dwell_time(SL_WIFI_SCAN_TYPE_ACTIVE,
+								z_scan_config->dwell_time_active,
+								z_scan_config->dwell_time_passive,
+								NULL);
+		} else {
+			sl_scan_config.type = SL_WIFI_SCAN_TYPE_PASSIVE;
+			ret = siwx91x_configure_scan_dwell_time(SL_WIFI_SCAN_TYPE_PASSIVE,
+								z_scan_config->dwell_time_active,
+								z_scan_config->dwell_time_passive,
+								NULL);
+		}
+		if (ret != SL_STATUS_OK) {
+			LOG_ERR("Failed to configure timeout");
+			return -EINVAL;
+		}
+	}
+
+	for (int i = 0; i < ARRAY_SIZE(z_scan_config->band_chan); i++) {
+		/* End of channel list */
+		if (z_scan_config->band_chan[i].channel == 0) {
+			break;
+		}
+
+		if (z_scan_config->band_chan[i].band == WIFI_FREQ_BAND_2_4_GHZ) {
+			sl_scan_config.channel_bitmap_2g4 |=
+				BIT(z_scan_config->band_chan[i].channel - 1);
+		}
+	}
+
+	if (z_scan_config->band_chan[0].channel && !sl_scan_config.channel_bitmap_2g4) {
+		LOG_ERR("No supported channels in the request");
+		return -EINVAL;
+	}
+
+	if (IS_ENABLED(CONFIG_WIFI_MGMT_SCAN_SSID_FILT_MAX)) {
+		if (z_scan_config->ssids[0]) {
+			strncpy(ssid.value, z_scan_config->ssids[0], WIFI_SSID_MAX_LEN);
+			ssid.length = strlen(z_scan_config->ssids[0]);
+		}
+	}
+
+	sidev->scan_max_bss_cnt = z_scan_config->max_bss_cnt;
+	sidev->scan_res_cb = cb;
+	ret = sl_wifi_start_scan(SL_WIFI_CLIENT_2_4GHZ_INTERFACE, (ssid.length > 0) ? &ssid : NULL,
+				 &sl_scan_config);
+	if (ret != SL_STATUS_IN_PROGRESS) {
+		return -EIO;
+	}
+	sidev->scan_prev_state = sidev->state;
+	sidev->state = WIFI_STATE_SCANNING;
+
+	return 0;
+}
+
+static int siwx91x_status(const struct device *dev, struct wifi_iface_status *status)
+{
+	sl_si91x_rsp_wireless_info_t wlan_info = { };
+	struct siwx91x_dev *sidev = dev->data;
+	uint8_t join_config;
+	sl_wifi_interface_t interface;
+	int32_t rssi;
+	int ret;
+
+	__ASSERT(status, "status cannot be NULL");
+
+	memset(status, 0, sizeof(*status));
+
+	status->state = sidev->state;
+	if (sidev->state <= WIFI_STATE_INACTIVE) {
+		return 0;
+	}
+
+	interface = sl_wifi_get_default_interface();
+	ret = sl_wifi_get_wireless_info(&wlan_info);
+	if (ret) {
+		LOG_ERR("Failed to get the wireless info: 0x%x", ret);
+		return -EIO;
+	}
+
+	strncpy(status->ssid, wlan_info.ssid, WIFI_SSID_MAX_LEN);
+	status->ssid_len = strlen(status->ssid);
+	memcpy(status->bssid, wlan_info.mac_address, WIFI_MAC_ADDR_LEN);
+	status->wpa3_ent_type = WIFI_WPA3_ENTERPRISE_NA;
+
+	ret = sl_si91x_get_join_configuration(interface, &join_config);
+	if (ret != SL_STATUS_OK) {
+		LOG_ERR("Failed to get join configuration: 0x%x", ret);
+		return -EINVAL;
+	}
+
+	if (join_config & SL_SI91X_JOIN_FEAT_MFP_CAPABLE_REQUIRED) {
+		status->mfp = WIFI_MFP_REQUIRED;
+	} else if (join_config & SL_SI91X_JOIN_FEAT_MFP_CAPABLE_ONLY) {
+		status->mfp = WIFI_MFP_OPTIONAL;
+	} else {
+		status->mfp = WIFI_MFP_DISABLE;
+	}
+
+	if (interface & SL_WIFI_2_4GHZ_INTERFACE) {
+		status->band = WIFI_FREQ_BAND_2_4_GHZ;
+	}
+
+	if (FIELD_GET(SIWX91X_INTERFACE_MASK, interface) == SL_WIFI_CLIENT_INTERFACE) {
+		sl_wifi_operational_statistics_t operational_statistics = { };
+
+		status->link_mode = WIFI_LINK_MODE_UNKNOWN;
+		status->iface_mode = WIFI_MODE_INFRA;
+		status->channel = wlan_info.channel_number;
+		status->twt_capable = true;
+		ret = sl_wifi_get_signal_strength(SL_WIFI_CLIENT_INTERFACE, &rssi);
+		if (ret) {
+			LOG_ERR("Failed to get signal strength: 0x%x", ret);
+			return -EINVAL;
+		}
+		status->rssi = rssi;
+
+		ret = sl_wifi_get_operational_statistics(SL_WIFI_CLIENT_INTERFACE,
+							 &operational_statistics);
+		if (ret) {
+			LOG_ERR("Failed to get operational statistics: 0x%x", ret);
+			return -EINVAL;
+		}
+
+		status->beacon_interval = sys_get_le16(operational_statistics.beacon_interval);
+		status->dtim_period = operational_statistics.dtim_period;
+	} else if (FIELD_GET(SIWX91X_INTERFACE_MASK, interface) == SL_WIFI_AP_INTERFACE) {
+		sl_wifi_ap_configuration_t sl_ap_cfg = { };
+
+		ret = sl_wifi_get_ap_configuration(SL_WIFI_AP_INTERFACE, &sl_ap_cfg);
+		if (ret) {
+			LOG_ERR("Failed to get the AP configuration: 0x%x", ret);
+			return -EINVAL;
+		}
+
+		status->twt_capable = false;
+		status->link_mode = WIFI_4;
+		status->iface_mode = WIFI_MODE_AP;
+		status->channel = sl_ap_cfg.channel.channel;
+		status->beacon_interval = sl_ap_cfg.beacon_interval;
+		status->dtim_period = sl_ap_cfg.dtim_beacon_count;
+		wlan_info.sec_type = (uint8_t)sl_ap_cfg.security;
+	} else {
+		status->link_mode = WIFI_LINK_MODE_UNKNOWN;
+		status->iface_mode = WIFI_MODE_UNKNOWN;
+		status->channel = 0;
+
+		return -EINVAL;
+	}
+
+	switch (wlan_info.sec_type) {
+	case SL_WIFI_OPEN:
+		status->security = WIFI_SECURITY_TYPE_NONE;
+		break;
+	case SL_WIFI_WPA:
+		status->security = WIFI_SECURITY_TYPE_WPA_PSK;
+		break;
+	case SL_WIFI_WPA2:
+		status->security = WIFI_SECURITY_TYPE_PSK;
+		break;
+	case SL_WIFI_WPA_WPA2_MIXED:
+		status->security = WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL;
+		break;
+	case SL_WIFI_WPA3:
+		status->security = WIFI_SECURITY_TYPE_SAE;
+		break;
+	default:
+		status->security = WIFI_SECURITY_TYPE_UNKNOWN;
+	}
+
+	return ret;
+}
+
+static int siwx91x_mode(const struct device *dev, struct wifi_mode_info *mode)
+{
+	sl_wifi_interface_t interface = sl_wifi_get_default_interface();
+	struct siwx91x_dev *sidev = dev->data;
+	int cur_mode;
+	int ret = 0;
+
+	__ASSERT(mode, "mode cannot be NULL");
+
+	cur_mode = siwx91x_sl_to_z_mode(FIELD_GET(SIWX91X_INTERFACE_MASK, interface));
+	if (cur_mode < 0) {
+		return -EIO;
+	}
+
+	if (mode->oper == WIFI_MGMT_GET) {
+		mode->mode = cur_mode;
+	} else if (mode->oper == WIFI_MGMT_SET) {
+		if (cur_mode != mode->mode) {
+			ret = siwx91x_nwp_mode_switch(mode->mode);
+			if (ret < 0) {
+				return ret;
+			}
+		}
+		sidev->state = WIFI_STATE_INACTIVE;
+	}
+
+	return 0;
+}
+
+#ifdef CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_NATIVE
+
+static int siwx91x_send(const struct device *dev, struct net_pkt *pkt)
+{
+	size_t pkt_len = net_pkt_get_len(pkt);
+	struct net_buf *buf = NULL;
+	int ret;
+
+	if (net_pkt_get_len(pkt) > _NET_ETH_MAX_FRAME_SIZE) {
+		LOG_ERR("unexpected buffer size");
+		return -ENOBUFS;
+	}
+	buf = net_buf_alloc(&siwx91x_tx_pool, K_FOREVER);
+	if (!buf) {
+		return -ENOBUFS;
+	}
+	if (net_pkt_read(pkt, buf->data, pkt_len)) {
+		net_buf_unref(buf);
+		return -ENOBUFS;
+	}
+	net_buf_add(buf, pkt_len);
+
+	ret = sl_wifi_send_raw_data_frame(SL_WIFI_CLIENT_INTERFACE, buf->data, pkt_len);
+	if (ret) {
+		net_buf_unref(buf);
+		return -EIO;
+	}
+
+	net_pkt_unref(pkt);
+	net_buf_unref(buf);
+
+	return 0;
+}
+
+/* Receive callback. Keep the name as it is declared weak in WiseConnect */
+sl_status_t sl_si91x_host_process_data_frame(sl_wifi_interface_t interface,
+					     sl_wifi_buffer_t *buffer)
+{
+	sl_si91x_packet_t *si_pkt = sl_si91x_host_get_buffer_data(buffer, 0, NULL);
+	struct net_if *iface = net_if_get_first_wifi();
+	struct net_pkt *pkt;
+	int ret;
+
+	pkt = net_pkt_rx_alloc_with_buffer(iface, buffer->length, AF_UNSPEC, 0, K_NO_WAIT);
+	if (!pkt) {
+		LOG_ERR("net_pkt_rx_alloc_with_buffer() failed");
+		return SL_STATUS_FAIL;
+	}
+	ret = net_pkt_write(pkt, si_pkt->data, si_pkt->length);
+	if (ret < 0) {
+		LOG_ERR("net_pkt_write(): %d", ret);
+		goto unref;
+	}
+	ret = net_recv_data(iface, pkt);
+	if (ret < 0) {
+		LOG_ERR("net_recv_data((): %d", ret);
+		goto unref;
+	}
+	return 0;
+
+unref:
+	net_pkt_unref(pkt);
+	return SL_STATUS_FAIL;
+}
+
+#endif
+
+static void siwx91x_ethernet_init(struct net_if *iface)
+{
+	struct ethernet_context *eth_ctx;
+
+	if (IS_ENABLED(CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_NATIVE)) {
+		eth_ctx = net_if_l2_data(iface);
+		eth_ctx->eth_if_type = L2_ETH_IF_TYPE_WIFI;
+		ethernet_init(iface);
+	}
+}
+
+#if defined(CONFIG_NET_STATISTICS_WIFI)
+static int siwx91x_stats(const struct device *dev, struct net_stats_wifi *stats)
+{
+	ARG_UNUSED(dev);
+	sl_wifi_interface_t interface;
+	sl_wifi_statistics_t statistics = { };
+	int ret;
+
+	__ASSERT(stats, "stats cannot be NULL");
+
+	interface = sl_wifi_get_default_interface();
+	ret = sl_wifi_get_statistics(FIELD_GET(SIWX91X_INTERFACE_MASK, interface), &statistics);
+	if (ret) {
+		LOG_ERR("Failed to get stat: 0x%x", ret);
+		return -EINVAL;
+	}
+
+	stats->multicast.rx = statistics.mcast_rx_count;
+	stats->multicast.tx = statistics.mcast_tx_count;
+	stats->unicast.rx = statistics.ucast_rx_count;
+	stats->unicast.tx = statistics.ucast_tx_count;
+	stats->sta_mgmt.beacons_rx = statistics.beacon_rx_count;
+	stats->sta_mgmt.beacons_miss = statistics.beacon_lost_count;
+	stats->overrun_count = statistics.overrun_count;
+
+	return ret;
+}
+#endif
+
+static int siwx91x_get_version(const struct device *dev, struct wifi_version *params)
+{
+	sl_wifi_firmware_version_t fw_version = { };
+	struct siwx91x_dev *sidev = dev->data;
+	static char fw_version_str[32];
+	sl_status_t status;
+
+	__ASSERT(params, "params cannot be NULL");
+
+	if (sidev->state == WIFI_STATE_INTERFACE_DISABLED) {
+		return -EIO;
+	}
+
+	status = sl_wifi_get_firmware_version(&fw_version);
+	if (status != SL_STATUS_OK) {
+		return -EINVAL;
+	}
+
+	snprintf(fw_version_str, sizeof(fw_version_str), "%02x%02x.%d.%d.%d.%d.%d.%d",
+		 fw_version.chip_id,     fw_version.rom_id,
+		 fw_version.major,       fw_version.minor,
+		 fw_version.security_version, fw_version.patch_num,
+		 fw_version.customer_id, fw_version.build_num);
+
+	params->fw_version = fw_version_str;
+	params->drv_version = SIWX91X_DRIVER_VERSION;
+
+	return 0;
+}
+
+static void siwx91x_iface_init(struct net_if *iface)
+{
+	struct siwx91x_dev *sidev = iface->if_dev->dev->data;
+	sl_status_t status;
+
+	sidev->state = WIFI_STATE_INTERFACE_DISABLED;
+	sidev->iface = iface;
+
+	sl_wifi_set_callback(SL_WIFI_SCAN_RESULT_EVENTS,
+			     (sl_wifi_callback_function_t)siwx91x_on_scan, sidev);
+	sl_wifi_set_callback(SL_WIFI_JOIN_EVENTS, (sl_wifi_callback_function_t)siwx91x_on_join,
+			     sidev);
+	sl_wifi_set_callback(SL_WIFI_CLIENT_CONNECTED_EVENTS, siwx91x_on_ap_sta_connect, sidev);
+	sl_wifi_set_callback(SL_WIFI_CLIENT_DISCONNECTED_EVENTS, siwx91x_on_ap_sta_disconnect,
+			     sidev);
+
+	status = sl_wifi_get_mac_address(SL_WIFI_CLIENT_INTERFACE, &sidev->macaddr);
+	if (status) {
+		LOG_ERR("sl_wifi_get_mac_address(): %#04x", status);
+		return;
+	}
+	net_if_set_link_addr(iface, sidev->macaddr.octet, sizeof(sidev->macaddr.octet),
+			     NET_LINK_ETHERNET);
+	siwx91x_sock_init(iface);
+	siwx91x_ethernet_init(iface);
+
+	sidev->state = WIFI_STATE_INACTIVE;
+}
+
+static int siwx91x_dev_init(const struct device *dev)
+{
+	return 0;
+}
+
+static const struct wifi_mgmt_ops siwx91x_mgmt = {
+	.scan			= siwx91x_scan,
+	.connect		= siwx91x_connect,
+	.disconnect		= siwx91x_disconnect,
+	.ap_enable		= siwx91x_ap_enable,
+	.ap_disable		= siwx91x_ap_disable,
+	.ap_sta_disconnect	= siwx91x_ap_sta_disconnect,
+	.iface_status		= siwx91x_status,
+	.mode			= siwx91x_mode,
+#if defined(CONFIG_NET_STATISTICS_WIFI)
+	.get_stats		= siwx91x_stats,
+#endif
+	.get_version		= siwx91x_get_version,
+};
+
+static const struct net_wifi_mgmt_offload siwx91x_api = {
+	.wifi_iface.iface_api.init = siwx91x_iface_init,
+#ifdef CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_NATIVE
+	.wifi_iface.send = siwx91x_send,
+#else
+	.wifi_iface.get_type = siwx91x_get_type,
+#endif
+	.wifi_mgmt_api = &siwx91x_mgmt,
+};
+
+static struct siwx91x_dev sidev;
+
+#ifdef CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_NATIVE
+ETH_NET_DEVICE_DT_INST_DEFINE(0, siwx91x_dev_init, NULL, &sidev, NULL,
+			      CONFIG_WIFI_INIT_PRIORITY, &siwx91x_api, NET_ETH_MTU);
+#else
+NET_DEVICE_DT_INST_OFFLOAD_DEFINE(0, siwx91x_dev_init, NULL, &sidev, NULL,
+				  CONFIG_WIFI_INIT_PRIORITY, &siwx91x_api, NET_ETH_MTU);
+#endif
diff --git a/drivers/wifi/siwx91x/siwx91x_wifi.h b/drivers/wifi/siwx91x/siwx91x_wifi.h
new file mode 100644
index 00000000000..045e7980765
--- /dev/null
+++ b/drivers/wifi/siwx91x/siwx91x_wifi.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef SIWX91X_WIFI_H
+#define SIWX91X_WIFI_H
+
+#include <zephyr/net/net_context.h>
+#include <zephyr/net/wifi_mgmt.h>
+#include <zephyr/net/wifi.h>
+#include <zephyr/kernel.h>
+
+#include "sl_ieee802_types.h"
+#include "sl_si91x_types.h"
+#include "sl_si91x_protocol_types.h"
+
+struct siwx91x_dev {
+	struct net_if *iface;
+	sl_mac_address_t macaddr;
+	enum wifi_iface_state state;
+	enum wifi_iface_state scan_prev_state;
+	scan_result_cb_t scan_res_cb;
+	uint16_t scan_max_bss_cnt;
+
+#ifdef CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_OFFLOAD
+	struct k_event fds_recv_event;
+	sl_si91x_fd_set fds_watch;
+	struct {
+		net_context_recv_cb_t cb;
+		void *user_data;
+		struct net_context *context;
+	} fds_cb[NUMBER_OF_SOCKETS];
+#endif
+};
+
+#endif
diff --git a/drivers/wifi/siwx91x/siwx91x_wifi_socket.c b/drivers/wifi/siwx91x/siwx91x_wifi_socket.c
new file mode 100644
index 00000000000..47440176bec
--- /dev/null
+++ b/drivers/wifi/siwx91x/siwx91x_wifi_socket.c
@@ -0,0 +1,414 @@
+/*
+ * Copyright (c) 2023 Antmicro
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/net/net_offload.h>
+#include <zephyr/logging/log.h>
+#include <assert.h>
+
+#include "siwx91x_wifi.h"
+#include "siwx91x_wifi_socket.h"
+
+#include "sl_status.h"
+#include "sl_net_ip_types.h"
+#include "sl_net_si91x.h"
+#include "sl_si91x_types.h"
+#include "sl_si91x_socket.h"
+#include "sl_si91x_socket_utility.h"
+
+LOG_MODULE_DECLARE(siwx91x_wifi);
+
+BUILD_ASSERT(NUMBER_OF_SOCKETS < sizeof(uint32_t) * 8);
+BUILD_ASSERT(NUMBER_OF_SOCKETS < SIZEOF_FIELD(sl_si91x_fd_set, __fds_bits) * 8);
+
+NET_BUF_POOL_FIXED_DEFINE(siwx91x_tx_pool, 1, NET_ETH_MTU, 0, NULL);
+NET_BUF_POOL_FIXED_DEFINE(siwx91x_rx_pool, 10, NET_ETH_MTU, 0, NULL);
+
+enum offloaded_net_if_types siwx91x_get_type(void)
+{
+	return L2_OFFLOADED_NET_IF_TYPE_WIFI;
+}
+
+/* SiWx91x does not use the standard struct sockaddr (despite it uses the same
+ * name):
+ *   - uses Little Endian for port number while Posix uses big endian
+ *   - IPv6 addresses are bytes swapped
+ * Note: this function allows to have in == out.
+ */
+static void siwx91x_sockaddr_swap_bytes(struct sockaddr *out,
+					const struct sockaddr *in, socklen_t in_len)
+{
+	const struct sockaddr_in6 *in6 = (const struct sockaddr_in6 *)in;
+	struct sockaddr_in6 *out6 = (struct sockaddr_in6 *)out;
+
+	/* In Zephyr, size of sockaddr == size of sockaddr_storage
+	 * (while in Posix sockaddr is smaller than sockaddr_storage).
+	 */
+	memcpy(out, in, in_len);
+	if (in->sa_family == AF_INET6) {
+		ARRAY_FOR_EACH(in6->sin6_addr.s6_addr32, i) {
+			out6->sin6_addr.s6_addr32[i] = ntohl(in6->sin6_addr.s6_addr32[i]);
+		}
+		out6->sin6_port = ntohs(in6->sin6_port);
+	} else if (in->sa_family == AF_INET) {
+		out6->sin6_port = ntohs(in6->sin6_port);
+	}
+}
+
+void siwx91x_on_join_ipv4(struct siwx91x_dev *sidev)
+{
+	sl_net_ip_configuration_t ip_config4 = {
+		.mode = SL_IP_MANAGEMENT_DHCP,
+		.type = SL_IPV4,
+	};
+	struct in_addr addr4 = { };
+	int ret;
+
+	if (!IS_ENABLED(CONFIG_NET_IPV4)) {
+		return;
+	}
+	/* FIXME: support for static IP configuration */
+	ret = sl_si91x_configure_ip_address(&ip_config4, SL_SI91X_WIFI_CLIENT_VAP_ID);
+	if (!ret) {
+		memcpy(addr4.s4_addr, ip_config4.ip.v4.ip_address.bytes, sizeof(addr4.s4_addr));
+		/* FIXME: also report gateway (net_if_ipv4_router_add()) */
+		net_if_ipv4_addr_add(sidev->iface, &addr4, NET_ADDR_DHCP, 0);
+	} else {
+		LOG_ERR("sl_si91x_configure_ip_address(): %#04x", ret);
+	}
+}
+
+void siwx91x_on_join_ipv6(struct siwx91x_dev *sidev)
+{
+	sl_net_ip_configuration_t ip_config6 = {
+		.mode = SL_IP_MANAGEMENT_DHCP,
+		.type = SL_IPV6,
+	};
+	struct in6_addr addr6 = { };
+	int ret;
+
+	if (!IS_ENABLED(CONFIG_NET_IPV6)) {
+		return;
+	}
+	/* FIXME: support for static IP configuration */
+	ret = sl_si91x_configure_ip_address(&ip_config6, SL_SI91X_WIFI_CLIENT_VAP_ID);
+	if (!ret) {
+		ARRAY_FOR_EACH(addr6.s6_addr32, i) {
+			addr6.s6_addr32[i] = ntohl(ip_config6.ip.v6.global_address.value[i]);
+		}
+		/* SiWx91x already take care of DAD and sending ND is not
+		 * supported anyway.
+		 */
+		net_if_flag_set(sidev->iface, NET_IF_IPV6_NO_ND);
+		/* FIXME: also report gateway and link local address */
+		net_if_ipv6_addr_add(sidev->iface, &addr6, NET_ADDR_AUTOCONF, 0);
+	} else {
+		LOG_ERR("sl_si91x_configure_ip_address(): %#04x", ret);
+	}
+}
+
+static int siwx91x_sock_recv_sync(struct net_context *context,
+				  net_context_recv_cb_t cb, void *user_data)
+{
+	struct net_if *iface = net_context_get_iface(context);
+	int sockfd = (int)context->offload_context;
+	struct net_pkt *pkt;
+	struct net_buf *buf;
+	int ret;
+
+	pkt = net_pkt_rx_alloc_on_iface(iface, K_MSEC(100));
+	if (!pkt) {
+		return -ENOBUFS;
+	}
+	buf = net_buf_alloc(&siwx91x_rx_pool, K_MSEC(100));
+	if (!buf) {
+		net_pkt_unref(pkt);
+		return -ENOBUFS;
+	}
+	net_pkt_append_buffer(pkt, buf);
+
+	ret = sl_si91x_recvfrom(sockfd, buf->data, NET_ETH_MTU, 0, NULL, NULL);
+	if (ret < 0) {
+		net_pkt_unref(pkt);
+		ret = -errno;
+	} else {
+		net_buf_add(buf, ret);
+		net_pkt_cursor_init(pkt);
+		ret = 0;
+	}
+	if (cb) {
+		cb(context, pkt, NULL, NULL, ret, user_data);
+	}
+	return ret;
+}
+
+static void siwx91x_sock_on_recv(sl_si91x_fd_set *read_fd, sl_si91x_fd_set *write_fd,
+				 sl_si91x_fd_set *except_fd, int status)
+{
+	/* When CONFIG_NET_SOCKETS_OFFLOAD is set, only one interface exist */
+	struct siwx91x_dev *sidev = net_if_get_first_wifi()->if_dev->dev->data;
+
+	ARRAY_FOR_EACH(sidev->fds_cb, i) {
+		if (SL_SI91X_FD_ISSET(i, read_fd)) {
+			if (sidev->fds_cb[i].cb) {
+				siwx91x_sock_recv_sync(sidev->fds_cb[i].context,
+						       sidev->fds_cb[i].cb,
+						       sidev->fds_cb[i].user_data);
+			} else {
+				SL_SI91X_FD_CLR(i, &sidev->fds_watch);
+				k_event_post(&sidev->fds_recv_event, 1U << i);
+			}
+		}
+	}
+
+	sl_si91x_select(NUMBER_OF_SOCKETS, &sidev->fds_watch, NULL, NULL, NULL,
+			siwx91x_sock_on_recv);
+}
+
+static int siwx91x_sock_get(sa_family_t family, enum net_sock_type type,
+			    enum net_ip_protocol ip_proto, struct net_context **context)
+{
+	struct siwx91x_dev *sidev = net_if_get_first_wifi()->if_dev->dev->data;
+	int sockfd;
+
+	sockfd = sl_si91x_socket(family, type, ip_proto);
+	if (sockfd < 0) {
+		return -errno;
+	}
+	assert(!sidev->fds_cb[sockfd].cb);
+	(*context)->offload_context = (void *)sockfd;
+	return sockfd;
+}
+
+static int siwx91x_sock_put(struct net_context *context)
+{
+	struct siwx91x_dev *sidev = net_context_get_iface(context)->if_dev->dev->data;
+	int sockfd = (int)context->offload_context;
+	int ret;
+
+	SL_SI91X_FD_CLR(sockfd, &sidev->fds_watch);
+	memset(&sidev->fds_cb[sockfd], 0, sizeof(sidev->fds_cb[sockfd]));
+	sl_si91x_select(NUMBER_OF_SOCKETS, &sidev->fds_watch, NULL, NULL, NULL,
+			siwx91x_sock_on_recv);
+	ret = sl_si91x_shutdown(sockfd, 0);
+	if (ret < 0) {
+		ret = -errno;
+	}
+	return ret;
+}
+
+static int siwx91x_sock_bind(struct net_context *context,
+			     const struct sockaddr *addr, socklen_t addrlen)
+{
+	struct siwx91x_dev *sidev = net_context_get_iface(context)->if_dev->dev->data;
+	int sockfd = (int)context->offload_context;
+	struct sockaddr addr_le;
+	int ret;
+
+	/* Zephyr tends to call bind() even if the TCP socket is a client. 917
+	 * return an error in this case.
+	 */
+	if (net_context_get_proto(context) == IPPROTO_TCP &&
+	    !((struct sockaddr_in *)addr)->sin_port) {
+		return 0;
+	}
+	siwx91x_sockaddr_swap_bytes(&addr_le, addr, addrlen);
+	ret = sl_si91x_bind(sockfd, &addr_le, addrlen);
+	if (ret) {
+		return -errno;
+	}
+	/* WiseConnect refuses to run select on TCP listening sockets */
+	if (net_context_get_proto(context) == IPPROTO_UDP) {
+		SL_SI91X_FD_SET(sockfd, &sidev->fds_watch);
+		sl_si91x_select(NUMBER_OF_SOCKETS, &sidev->fds_watch, NULL, NULL, NULL,
+				siwx91x_sock_on_recv);
+	}
+	return 0;
+}
+
+static int siwx91x_sock_connect(struct net_context *context,
+				const struct sockaddr *addr, socklen_t addrlen,
+				net_context_connect_cb_t cb, int32_t timeout, void *user_data)
+{
+	struct siwx91x_dev *sidev = net_context_get_iface(context)->if_dev->dev->data;
+	int sockfd = (int)context->offload_context;
+	struct sockaddr addr_le;
+	int ret;
+
+	/* sl_si91x_connect() always return immediately, so we ignore timeout */
+	siwx91x_sockaddr_swap_bytes(&addr_le, addr, addrlen);
+	ret = sl_si91x_connect(sockfd, &addr_le, addrlen);
+	if (ret) {
+		ret = -errno;
+	}
+	SL_SI91X_FD_SET(sockfd, &sidev->fds_watch);
+	sl_si91x_select(NUMBER_OF_SOCKETS, &sidev->fds_watch, NULL, NULL, NULL,
+			siwx91x_sock_on_recv);
+	net_context_set_state(context, NET_CONTEXT_CONNECTED);
+	if (cb) {
+		cb(context, ret, user_data);
+	}
+	return ret;
+}
+
+static int siwx91x_sock_listen(struct net_context *context, int backlog)
+{
+	int sockfd = (int)context->offload_context;
+	int ret;
+
+	ret = sl_si91x_listen(sockfd, backlog);
+	if (ret) {
+		return -errno;
+	}
+	net_context_set_state(context, NET_CONTEXT_LISTENING);
+	return 0;
+}
+
+static int siwx91x_sock_accept(struct net_context *context,
+			       net_tcp_accept_cb_t cb, int32_t timeout, void *user_data)
+{
+	struct siwx91x_dev *sidev = net_context_get_iface(context)->if_dev->dev->data;
+	int sockfd = (int)context->offload_context;
+	struct net_context *newcontext;
+	struct sockaddr addr_le;
+	int ret;
+
+	/* TODO: support timeout != K_FOREVER */
+	assert(timeout < 0);
+
+	ret = net_context_get(net_context_get_family(context),
+			      net_context_get_type(context),
+			      net_context_get_proto(context), &newcontext);
+	if (ret < 0) {
+		return ret;
+	}
+	/* net_context_get() calls siwx91x_sock_get() but sl_si91x_accept() also
+	 * allocates a socket.
+	 */
+	ret = siwx91x_sock_put(newcontext);
+	if (ret < 0) {
+		return ret;
+	}
+	/* The iface is reset when getting a new context. */
+	newcontext->iface = context->iface;
+	ret = sl_si91x_accept(sockfd, &addr_le, sizeof(addr_le));
+	if (ret < 0) {
+		return -errno;
+	}
+	newcontext->flags |= NET_CONTEXT_REMOTE_ADDR_SET;
+	newcontext->offload_context = (void *)ret;
+	siwx91x_sockaddr_swap_bytes(&newcontext->remote, &addr_le, sizeof(addr_le));
+
+	SL_SI91X_FD_SET(ret, &sidev->fds_watch);
+	sl_si91x_select(NUMBER_OF_SOCKETS, &sidev->fds_watch, NULL, NULL, NULL,
+			siwx91x_sock_on_recv);
+	if (cb) {
+		cb(newcontext, &addr_le, sizeof(addr_le), 0, user_data);
+	}
+
+	return 0;
+}
+
+static int siwx91x_sock_sendto(struct net_pkt *pkt,
+			       const struct sockaddr *addr, socklen_t addrlen,
+			       net_context_send_cb_t cb, int32_t timeout, void *user_data)
+{
+	struct net_context *context = pkt->context;
+	int sockfd = (int)context->offload_context;
+	struct sockaddr addr_le;
+	struct net_buf *buf;
+	int ret;
+
+	/* struct net_pkt use fragmented buffers while SiWx91x API need a
+	 * continuous buffer.
+	 */
+	if (net_pkt_get_len(pkt) > NET_ETH_MTU) {
+		LOG_ERR("unexpected buffer size");
+		ret = -ENOBUFS;
+		goto out_cb;
+	}
+	buf = net_buf_alloc(&siwx91x_tx_pool, K_FOREVER);
+	if (!buf) {
+		ret = -ENOBUFS;
+		goto out_cb;
+	}
+	if (net_pkt_read(pkt, buf->data, net_pkt_get_len(pkt))) {
+		ret = -ENOBUFS;
+		goto out_release_buf;
+	}
+	net_buf_add(buf, net_pkt_get_len(pkt));
+
+	/* sl_si91x_sendto() always return immediately, so we ignore timeout */
+	siwx91x_sockaddr_swap_bytes(&addr_le, addr, addrlen);
+	ret = sl_si91x_sendto(sockfd, buf->data, net_pkt_get_len(pkt), 0, &addr_le, addrlen);
+	if (ret < 0) {
+		ret = -errno;
+		goto out_release_buf;
+	}
+	net_pkt_unref(pkt);
+
+out_release_buf:
+	net_buf_unref(buf);
+
+out_cb:
+	if (cb) {
+		cb(pkt->context, ret, user_data);
+	}
+	return ret;
+}
+
+static int siwx91x_sock_send(struct net_pkt *pkt,
+			     net_context_send_cb_t cb, int32_t timeout, void *user_data)
+{
+	return siwx91x_sock_sendto(pkt, NULL, 0, cb, timeout, user_data);
+}
+
+static int siwx91x_sock_recv(struct net_context *context,
+			     net_context_recv_cb_t cb, int32_t timeout, void *user_data)
+{
+	struct net_if *iface = net_context_get_iface(context);
+	struct siwx91x_dev *sidev = iface->if_dev->dev->data;
+	int sockfd = (int)context->offload_context;
+	int ret;
+
+	ret = k_event_wait(&sidev->fds_recv_event, 1U << sockfd, false,
+			   timeout < 0 ? K_FOREVER : K_MSEC(timeout));
+	if (timeout == 0) {
+		sidev->fds_cb[sockfd].context = context;
+		sidev->fds_cb[sockfd].cb = cb;
+		sidev->fds_cb[sockfd].user_data = user_data;
+	} else {
+		memset(&sidev->fds_cb[sockfd], 0, sizeof(sidev->fds_cb[sockfd]));
+	}
+
+	if (ret) {
+		k_event_clear(&sidev->fds_recv_event, 1U << sockfd);
+		ret = siwx91x_sock_recv_sync(context, cb, user_data);
+		SL_SI91X_FD_SET(sockfd, &sidev->fds_watch);
+	}
+
+	sl_si91x_select(NUMBER_OF_SOCKETS, &sidev->fds_watch, NULL, NULL, NULL,
+			siwx91x_sock_on_recv);
+	return ret;
+}
+
+static struct net_offload siwx91x_offload = {
+	.get      = siwx91x_sock_get,
+	.put      = siwx91x_sock_put,
+	.bind     = siwx91x_sock_bind,
+	.listen   = siwx91x_sock_listen,
+	.connect  = siwx91x_sock_connect,
+	.accept   = siwx91x_sock_accept,
+	.sendto   = siwx91x_sock_sendto,
+	.send     = siwx91x_sock_send,
+	.recv     = siwx91x_sock_recv,
+};
+
+void siwx91x_sock_init(struct net_if *iface)
+{
+	struct siwx91x_dev *sidev = iface->if_dev->dev->data;
+
+	iface->if_dev->offload = &siwx91x_offload;
+	k_event_init(&sidev->fds_recv_event);
+}
diff --git a/drivers/wifi/siwx91x/siwx91x_wifi_socket.h b/drivers/wifi/siwx91x/siwx91x_wifi_socket.h
new file mode 100644
index 00000000000..6ae06aaee4e
--- /dev/null
+++ b/drivers/wifi/siwx91x/siwx91x_wifi_socket.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2023 Antmicro
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef SIWX91X_WIFI_SOCKET_H
+#define SIWX91X_WIFI_SOCKET_H
+
+#include <zephyr/net/net_if.h>
+#include <zephyr/net/offloaded_netdev.h>
+#include <assert.h>
+
+struct siwx91x_dev;
+
+#ifdef CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_OFFLOAD
+
+enum offloaded_net_if_types siwx91x_get_type(void);
+void siwx91x_on_join_ipv4(struct siwx91x_dev *sidev);
+void siwx91x_on_join_ipv6(struct siwx91x_dev *sidev);
+void siwx91x_sock_init(struct net_if *iface);
+
+#else /* CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_OFFLOAD */
+
+enum offloaded_net_if_types siwx91x_get_type(void)
+{
+	assert(0);
+}
+
+void siwx91x_on_join_ipv4(struct siwx91x_dev *sidev)
+{
+}
+
+void siwx91x_on_join_ipv6(struct siwx91x_dev *sidev)
+{
+}
+
+void siwx91x_sock_init(struct net_if *iface)
+{
+}
+
+#endif /* CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_OFFLOAD */
+
+#endif
diff --git a/drivers/wifi/winc1500/wifi_winc1500.c b/drivers/wifi/winc1500/wifi_winc1500.c
index 8ef41f71215..b0788a04c56 100644
--- a/drivers/wifi/winc1500/wifi_winc1500.c
+++ b/drivers/wifi/winc1500/wifi_winc1500.c
@@ -42,16 +42,16 @@ typedef void (*tpfAppSocketCb) (SOCKET sock, uint8 u8Msg, void *pvMsg);
 typedef void (*tpfAppResolveCb) (uint8 *pu8DomainName, uint32 u32ServerIP);
 NMI_API void registerSocketCallback(tpfAppSocketCb socket_cb,
 				    tpfAppResolveCb resolve_cb);
-NMI_API SOCKET socket(uint16 u16Domain, uint8 u8Type, uint8 u8Flags);
-NMI_API sint8 bind(SOCKET sock, struct sockaddr *pstrAddr, uint8 u8AddrLen);
-NMI_API sint8 listen(SOCKET sock, uint8 backlog);
-NMI_API sint8 accept(SOCKET sock, struct sockaddr *addr, uint8 *addrlen);
-NMI_API sint8 connect(SOCKET sock, struct sockaddr *pstrAddr, uint8 u8AddrLen);
-NMI_API sint16 recv(SOCKET sock, void *pvRecvBuf,
+NMI_API SOCKET winc1500_socket(uint16 u16Domain, uint8 u8Type, uint8 u8Flags);
+NMI_API sint8 winc1500_socket_bind(SOCKET sock, struct sockaddr *pstrAddr, uint8 u8AddrLen);
+NMI_API sint8 winc1500_socket_listen(SOCKET sock, uint8 backlog);
+NMI_API sint8 winc1500_socket_accept(SOCKET sock, struct sockaddr *addr, uint8 *addrlen);
+NMI_API sint8 winc1500_socket_connect(SOCKET sock, struct sockaddr *pstrAddr, uint8 u8AddrLen);
+NMI_API sint16 winc1500_socket_recv(SOCKET sock, void *pvRecvBuf,
 		    uint16 u16BufLen, uint32 u32Timeoutmsec);
-NMI_API sint16 send(SOCKET sock, void *pvSendBuffer,
+NMI_API sint16 winc1500_socket_send(SOCKET sock, void *pvSendBuffer,
 		    uint16 u16SendLength, uint16 u16Flags);
-NMI_API sint16 sendto(SOCKET sock, void *pvSendBuffer,
+NMI_API sint16 winc1500_socket_sendto(SOCKET sock, void *pvSendBuffer,
 		      uint16 u16SendLength, uint16 flags,
 		      struct sockaddr *pstrDestAddr, uint8 u8AddrLen);
 NMI_API sint8 winc1500_close(SOCKET sock);
@@ -306,7 +306,7 @@ static int winc1500_get(sa_family_t family,
 	 * we have checked if family is AF_INET so we can hardcode this
 	 * for now.
 	 */
-	sock = socket(2, type, 0);
+	sock = winc1500_socket(2, type, 0);
 	if (sock < 0) {
 		LOG_ERR("socket error!");
 		return -1;
@@ -337,7 +337,8 @@ static int winc1500_bind(struct net_context *context,
 		return 0;
 	}
 
-	ret = bind((intptr_t)context->offload_context, (struct sockaddr *)addr, addrlen);
+	ret = winc1500_socket_bind((intptr_t)context->offload_context, (struct sockaddr *)addr,
+		   addrlen);
 	if (ret) {
 		LOG_ERR("bind error %d %s!",
 			ret, socket_message_to_string(ret));
@@ -362,7 +363,7 @@ static int winc1500_listen(struct net_context *context, int backlog)
 	SOCKET socket = (intptr_t)context->offload_context;
 	int ret;
 
-	ret = listen((intptr_t)context->offload_context, backlog);
+	ret = winc1500_socket_listen((intptr_t)context->offload_context, backlog);
 	if (ret) {
 		LOG_ERR("listen error %d %s!",
 			ret, socket_error_string(ret));
@@ -395,7 +396,7 @@ static int winc1500_connect(struct net_context *context,
 	w1500_data.socket_data[socket].connect_user_data = user_data;
 	w1500_data.socket_data[socket].ret_code = 0;
 
-	ret = connect(socket, (struct sockaddr *)addr, addrlen);
+	ret = winc1500_socket_connect(socket, (struct sockaddr *)addr, addrlen);
 	if (ret) {
 		LOG_ERR("connect error %d %s!",
 			ret, socket_error_string(ret));
@@ -425,7 +426,7 @@ static int winc1500_accept(struct net_context *context,
 	w1500_data.socket_data[socket].accept_cb = cb;
 	w1500_data.socket_data[socket].accept_user_data = user_data;
 
-	ret = accept(socket, NULL, 0);
+	ret = winc1500_socket_accept(socket, NULL, 0);
 	if (ret) {
 		LOG_ERR("accept error %d %s!",
 			ret, socket_error_string(ret));
@@ -467,7 +468,7 @@ static int winc1500_send(struct net_pkt *pkt,
 
 	net_buf_add(buf, net_pkt_get_len(pkt));
 
-	ret = send(socket, buf->data, buf->len, 0);
+	ret = winc1500_socket_send(socket, buf->data, buf->len, 0);
 	if (ret) {
 		LOG_ERR("send error %d %s!", ret, socket_error_string(ret));
 		goto out;
@@ -507,7 +508,7 @@ static int winc1500_sendto(struct net_pkt *pkt,
 
 	net_buf_add(buf, net_pkt_get_len(pkt));
 
-	ret = sendto(socket, buf->data, buf->len, 0,
+	ret = winc1500_socket_sendto(socket, buf->data, buf->len, 0,
 		     (struct sockaddr *)dst_addr, addrlen);
 	if (ret) {
 		LOG_ERR("sendto error %d %s!", ret, socket_error_string(ret));
@@ -571,7 +572,7 @@ static int winc1500_recv(struct net_context *context,
 	}
 
 
-	ret = recv(socket, w1500_data.socket_data[socket].pkt_buf->data,
+	ret = winc1500_socket_recv(socket, w1500_data.socket_data[socket].pkt_buf->data,
 		   CONFIG_WIFI_WINC1500_MAX_PACKET_SIZE, timeout);
 	if (ret) {
 		LOG_ERR("recv error %d %s!",
@@ -682,7 +683,7 @@ static void reset_scan_data(void)
 static void handle_scan_result(void *pvMsg)
 {
 	tstrM2mWifiscanResult *pstrScanResult = (tstrM2mWifiscanResult *)pvMsg;
-	struct wifi_scan_result result;
+	struct wifi_scan_result result = { 0 };
 
 	if (!w1500_data.scan_cb) {
 		return;
@@ -816,6 +817,8 @@ static bool handle_socket_msg_recv(SOCKET sock,
 			}
 	} else if (pstrRx->pu8Buffer == NULL) {
 		if (pstrRx->s16BufferSize == SOCK_ERR_CONN_ABORTED) {
+			winc1500_close(sock);
+
 			net_pkt_unref(sd->rx_pkt);
 			return false;
 		}
@@ -904,6 +907,8 @@ static void handle_socket_msg_accept(struct socket_data *sd, void *pvMsg)
 		/** The iface is reset when getting a new context. */
 		a_sd->context->iface = sd->context->iface;
 
+		net_context_set_state(a_sd->context, NET_CONTEXT_CONNECTED);
+
 		/** Setup remote */
 		a_sd->context->remote.sa_family = AF_INET;
 		net_sin(&a_sd->context->remote)->sin_port =
@@ -1066,7 +1071,8 @@ static int winc1500_mgmt_ap_enable(const struct device *dev,
 	tstrM2MAPConfig strM2MAPConfig;
 
 	memset(&strM2MAPConfig, 0x00, sizeof(tstrM2MAPConfig));
-	strcpy((char *)&strM2MAPConfig.au8SSID, params->ssid);
+	strncpy((char *)&strM2MAPConfig.au8SSID, params->ssid,
+		params->ssid_length);
 	strM2MAPConfig.u8ListenChannel = params->channel;
 	/** security is hardcoded as open for now */
 	strM2MAPConfig.u8SecType = M2M_WIFI_SEC_OPEN;
diff --git a/drivers/wifi/winc1500/wifi_winc1500_nm_bsp.c b/drivers/wifi/winc1500/wifi_winc1500_nm_bsp.c
index 4872ddab7cf..94f118e747a 100644
--- a/drivers/wifi/winc1500/wifi_winc1500_nm_bsp.c
+++ b/drivers/wifi/winc1500/wifi_winc1500_nm_bsp.c
@@ -52,13 +52,13 @@ int8_t nm_bsp_deinit(void)
 void nm_bsp_reset(void)
 {
 	gpio_pin_set_dt(&winc1500_config.chip_en_gpio, 0);
-	gpio_pin_set_dt(&winc1500_config.reset_gpio, 0);
+	gpio_pin_set_dt(&winc1500_config.reset_gpio, 1);
 	nm_bsp_sleep(100);
 
 	gpio_pin_set_dt(&winc1500_config.chip_en_gpio, 1);
 	nm_bsp_sleep(10);
 
-	gpio_pin_set_dt(&winc1500_config.reset_gpio, 1);
+	gpio_pin_set_dt(&winc1500_config.reset_gpio, 0);
 	nm_bsp_sleep(10);
 }
 
diff --git a/drivers/xen/Kconfig b/drivers/xen/Kconfig
index 361c71a3538..99ad113887b 100644
--- a/drivers/xen/Kconfig
+++ b/drivers/xen/Kconfig
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
-# Copyright (c) 2022-2023 EPAM Systems
+# Copyright (c) 2022-2024 EPAM Systems
 
 if XEN
 
@@ -20,6 +20,15 @@ config XEN_GRANT_TABLE_INIT_PRIORITY
 	depends on XEN_GRANT_TABLE
 	default 50
 
+config NR_GRANT_FRAMES
+	int "Number of grant frames mapped to Zephyr"
+	depends on XEN_GRANT_TABLE
+	default 1
+	help
+	  This value configures how much grant frames will be supported by Zephyr
+	  grant table driver in runtime. This value should be <= max_grant_frames
+	  configured for domain in Xen hypervisor.
+
 endmenu
 
 endif # XEN
diff --git a/drivers/xen/gnttab.c b/drivers/xen/gnttab.c
index 8ceb97e2db1..ccf1b888e17 100644
--- a/drivers/xen/gnttab.c
+++ b/drivers/xen/gnttab.c
@@ -2,7 +2,7 @@
 /*
  ****************************************************************************
  * (C) 2006 - Cambridge University
- * (C) 2021-2022 - EPAM Systems
+ * (C) 2021-2024 - EPAM Systems
  ****************************************************************************
  *
  *        File: gnttab.c
@@ -35,16 +35,13 @@ LOG_MODULE_REGISTER(xen_gnttab);
 /* Timeout for grant table ops retrying */
 #define GOP_RETRY_DELAY 200
 
-#define GNTTAB_SIZE DT_REG_SIZE_BY_IDX(DT_INST(0, xen_xen), 0)
-BUILD_ASSERT(!(GNTTAB_SIZE % XEN_PAGE_SIZE), "Size of gnttab have to be aligned on XEN_PAGE_SIZE");
-
-/* NR_GRANT_FRAMES must be less than or equal to that configured in Xen */
-#define NR_GRANT_FRAMES (GNTTAB_SIZE / XEN_PAGE_SIZE)
-#define NR_GRANT_ENTRIES \
-	(NR_GRANT_FRAMES * XEN_PAGE_SIZE / sizeof(grant_entry_v1_t))
+#define GNTTAB_GREF_USED	(UINT32_MAX - 1)
+#define GNTTAB_SIZE		(CONFIG_NR_GRANT_FRAMES * XEN_PAGE_SIZE)
+#define NR_GRANT_ENTRIES	(GNTTAB_SIZE / sizeof(grant_entry_v1_t))
 
+BUILD_ASSERT(GNTTAB_SIZE <= DT_REG_SIZE_BY_IDX(DT_INST(0, xen_xen), 0),
+	     "Number of grant frames is bigger than grant table DT region!");
 BUILD_ASSERT(GNTTAB_SIZE <= CONFIG_KERNEL_VM_SIZE);
-DEVICE_MMIO_TOPLEVEL_STATIC(grant_tables, DT_INST(0, xen_xen));
 
 static struct gnttab {
 	struct k_sem sem;
@@ -64,6 +61,7 @@ static grant_ref_t get_free_entry(void)
 	__ASSERT((gref >= GNTTAB_NR_RESERVED_ENTRIES &&
 		gref < NR_GRANT_ENTRIES), "Invalid gref = %d", gref);
 	gnttab.gref_list[0] = gnttab.gref_list[gref];
+	gnttab.gref_list[gref] = GNTTAB_GREF_USED;
 	irq_unlock(flags);
 
 	return gref;
@@ -74,6 +72,12 @@ static void put_free_entry(grant_ref_t gref)
 	unsigned int flags;
 
 	flags = irq_lock();
+	if (gnttab.gref_list[gref] != GNTTAB_GREF_USED) {
+		LOG_WRN("Trying to put already free gref = %u", gref);
+
+		return;
+	}
+
 	gnttab.gref_list[gref] = gnttab.gref_list[0];
 	gnttab.gref_list[0] = gref;
 
@@ -277,7 +281,7 @@ int gnttab_map_refs(struct gnttab_map_grant_ref *map_ops, unsigned int count)
 	return 0;
 }
 
-int gnttab_unmap_refs(struct gnttab_map_grant_ref *unmap_ops, unsigned int count)
+int gnttab_unmap_refs(struct gnttab_unmap_grant_ref *unmap_ops, unsigned int count)
 {
 	return HYPERVISOR_grant_table_op(GNTTABOP_unmap_grant_ref, unmap_ops, count);
 }
@@ -295,44 +299,68 @@ const char *gnttabop_error(int16_t status)
 	}
 }
 
+/* Picked from Linux implementation */
+#define LEGACY_MAX_GNT_FRAMES_SUPPORTED		4
+static unsigned long gnttab_get_max_frames(void)
+{
+	int ret;
+	struct gnttab_query_size q = {
+		.dom = DOMID_SELF,
+	};
+
+	ret = HYPERVISOR_grant_table_op(GNTTABOP_query_size, &q, 1);
+	if ((ret < 0) || (q.status != GNTST_okay)) {
+		return LEGACY_MAX_GNT_FRAMES_SUPPORTED;
+	}
+
+	return q.max_nr_frames;
+}
+
 static int gnttab_init(void)
 {
 	grant_ref_t gref;
 	struct xen_add_to_physmap xatp;
-	struct gnttab_setup_table setup;
-	xen_pfn_t frames[NR_GRANT_FRAMES];
 	int rc = 0, i;
+	unsigned long xen_max_grant_frames;
+	uintptr_t gnttab_base = DT_REG_ADDR_BY_IDX(DT_INST(0, xen_xen), 0);
+	mm_reg_t gnttab_reg;
+
+	xen_max_grant_frames = gnttab_get_max_frames();
+	if (xen_max_grant_frames < CONFIG_NR_GRANT_FRAMES) {
+		LOG_ERR("Xen max_grant_frames is less than CONFIG_NR_GRANT_FRAMES!");
+		k_panic();
+	}
 
 	/* Will be taken/given during gnt_refs allocation/release */
-	k_sem_init(&gnttab.sem, 0, NR_GRANT_ENTRIES - GNTTAB_NR_RESERVED_ENTRIES);
-
-	for (
-		gref = GNTTAB_NR_RESERVED_ENTRIES;
-		gref < NR_GRANT_ENTRIES;
-		gref++
-	    ) {
-		put_free_entry(gref);
+	k_sem_init(&gnttab.sem, NR_GRANT_ENTRIES - GNTTAB_NR_RESERVED_ENTRIES,
+		   NR_GRANT_ENTRIES - GNTTAB_NR_RESERVED_ENTRIES);
+
+	/* Initialize O(1) allocator, gnttab.gref_list[0] always shows first free entry */
+	gnttab.gref_list[0] = GNTTAB_NR_RESERVED_ENTRIES;
+	gnttab.gref_list[NR_GRANT_ENTRIES - 1] = 0;
+	for (gref = GNTTAB_NR_RESERVED_ENTRIES; gref < NR_GRANT_ENTRIES - 1; gref++) {
+		gnttab.gref_list[gref] = gref + 1;
 	}
 
-	for (i = 0; i < NR_GRANT_FRAMES; i++) {
+	for (i = CONFIG_NR_GRANT_FRAMES - 1; i >= 0; i--) {
 		xatp.domid = DOMID_SELF;
 		xatp.size = 0;
 		xatp.space = XENMAPSPACE_grant_table;
 		xatp.idx = i;
-		xatp.gpfn = xen_virt_to_gfn(Z_TOPLEVEL_ROM_NAME(grant_tables).phys_addr) + i;
+		xatp.gpfn = xen_virt_to_gfn(gnttab_base) + i;
 		rc = HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp);
 		__ASSERT(!rc, "add_to_physmap failed; status = %d\n", rc);
 	}
 
-	setup.dom = DOMID_SELF;
-	setup.nr_frames = NR_GRANT_FRAMES;
-	set_xen_guest_handle(setup.frame_list, frames);
-	rc = HYPERVISOR_grant_table_op(GNTTABOP_setup_table, &setup, 1);
-	__ASSERT((!rc) && (!setup.status), "Table setup failed; status = %s\n",
-		gnttabop_error(setup.status));
-
-	DEVICE_MMIO_TOPLEVEL_MAP(grant_tables, K_MEM_CACHE_WB | K_MEM_PERM_RW);
-	gnttab.table = (grant_entry_v1_t *)DEVICE_MMIO_TOPLEVEL_GET(grant_tables);
+	/*
+	 * Xen DT region reserved for grant table (first reg in hypervisor node)
+	 * may be much bigger than CONFIG_NR_GRANT_FRAMES multiplied by page size.
+	 * Thus, we need to map only part of region, that is limited by config.
+	 * The size of this part is calculated in GNTTAB_SIZE macro and used as
+	 * parameter for device_map()
+	 */
+	device_map(&gnttab_reg, gnttab_base, GNTTAB_SIZE, K_MEM_CACHE_WB | K_MEM_PERM_RW);
+	gnttab.table = (grant_entry_v1_t *)gnttab_reg;
 
 	LOG_DBG("%s: grant table mapped\n", __func__);
 
diff --git a/dts/arc/synopsys/arc_hs4xd.dtsi b/dts/arc/synopsys/arc_hs4xd.dtsi
index d6650e651a9..c39c754e32c 100644
--- a/dts/arc/synopsys/arc_hs4xd.dtsi
+++ b/dts/arc/synopsys/arc_hs4xd.dtsi
@@ -135,9 +135,9 @@
 			compatible = "snps,creg-gpio";
 			reg = <0xf00014b0 0x4>;
 			ngpios = <12>;
-			bit_per_gpio = <2>;
-			off_val = <0>;
-			on_val = <2>;
+			bit-per-gpio = <2>;
+			off-val = <0>;
+			on-val = <2>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
diff --git a/dts/arc/synopsys/arc_hsdk.dtsi b/dts/arc/synopsys/arc_hsdk.dtsi
index 6388db825a0..4168df99db8 100644
--- a/dts/arc/synopsys/arc_hsdk.dtsi
+++ b/dts/arc/synopsys/arc_hsdk.dtsi
@@ -135,9 +135,9 @@
 			compatible = "snps,creg-gpio";
 			reg = <0xf00014b0 0x4>;
 			ngpios = <12>;
-			bit_per_gpio = <2>;
-			off_val = <0>;
-			on_val = <2>;
+			bit-per-gpio = <2>;
+			off-val = <0>;
+			on-val = <2>;
 
 			gpio-controller;
 			#gpio-cells = <2>;
diff --git a/dts/arm/adi/max32/max32650-pinctrl.dtsi b/dts/arm/adi/max32/max32650-pinctrl.dtsi
new file mode 100644
index 00000000000..eaf39132953
--- /dev/null
+++ b/dts/arm/adi/max32/max32650-pinctrl.dtsi
@@ -0,0 +1,641 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@40008000 {
+			/omit-if-no-ref/ spixr_sdio0_p0_1: spixr_sdio0_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixr_sdio2_p0_2: spixr_sdio2_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixr_sck_p0_3: spixr_sck_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixr_sdio3_p0_4: spixr_sdio3_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixr_sdio1_p0_5: spixr_sdio1_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixr_ss0_p0_6: spixr_ss0_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixf_ss0_p0_7: spixf_ss0_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixf_sck_p0_8: spixf_sck_p0_8 {
+				pinmux = <MAX32_PINMUX(0, 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixf_sdio1_p0_9: spixf_sdio1_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixf_sdio0_p0_10: spixf_sdio0_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixf_sdio2_p0_11: spixf_sdio2_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixf_sdio3_p0_12: spixf_sdio3_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi3_ss1_p0_13: spi3_ss1_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_g0_p0_13: clcd_g0_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi3_ss2_p0_14: spi3_ss2_p0_14 {
+				pinmux = <MAX32_PINMUX(0, 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_g1_p0_14: clcd_g1_p0_14 {
+				pinmux = <MAX32_PINMUX(0, 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi3_sdio3_p0_15: spi3_sdio3_p0_15 {
+				pinmux = <MAX32_PINMUX(0, 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_g2_p0_15: clcd_g2_p0_15 {
+				pinmux = <MAX32_PINMUX(0, 15, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi3_sck_p0_16: spi3_sck_p0_16 {
+				pinmux = <MAX32_PINMUX(0, 16, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_g3_p0_16: clcd_g3_p0_16 {
+				pinmux = <MAX32_PINMUX(0, 16, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi3_sdio2_p0_17: spi3_sdio2_p0_17 {
+				pinmux = <MAX32_PINMUX(0, 17, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_g4_p0_17: clcd_g4_p0_17 {
+				pinmux = <MAX32_PINMUX(0, 17, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi3_ss3_p0_18: spi3_ss3_p0_18 {
+				pinmux = <MAX32_PINMUX(0, 18, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_g5_p0_18: clcd_g5_p0_18 {
+				pinmux = <MAX32_PINMUX(0, 18, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi3_ss0_p0_19: spi3_ss0_p0_19 {
+				pinmux = <MAX32_PINMUX(0, 19, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_g6_p0_19: clcd_g6_p0_19 {
+				pinmux = <MAX32_PINMUX(0, 19, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi3_sdio1_p0_20: spi3_sdio1_p0_20 {
+				pinmux = <MAX32_PINMUX(0, 20, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_g7_p0_20: clcd_g7_p0_20 {
+				pinmux = <MAX32_PINMUX(0, 20, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi3_sdio0_p0_21: spi3_sdio0_p0_21 {
+				pinmux = <MAX32_PINMUX(0, 21, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0_ss0_p0_22: spi0_ss0_p0_22 {
+				pinmux = <MAX32_PINMUX(0, 22, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_vden_p0_22: clcd_vden_p0_22 {
+				pinmux = <MAX32_PINMUX(0, 22, AF2)>;
+			};
+
+			/omit-if-no-ref/ pt15_p0_23: pt15_p0_23 {
+				pinmux = <MAX32_PINMUX(0, 23, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_clk_p0_23: clcd_clk_p0_23 {
+				pinmux = <MAX32_PINMUX(0, 23, AF2)>;
+			};
+
+			/omit-if-no-ref/ rxev_p0_24: rxev_p0_24 {
+				pinmux = <MAX32_PINMUX(0, 24, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_hsync_p0_24: clcd_hsync_p0_24 {
+				pinmux = <MAX32_PINMUX(0, 24, AF2)>;
+			};
+
+			/omit-if-no-ref/ txev_p0_25: txev_p0_25 {
+				pinmux = <MAX32_PINMUX(0, 25, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_b0_p0_25: clcd_b0_p0_25 {
+				pinmux = <MAX32_PINMUX(0, 25, AF2)>;
+			};
+
+			/omit-if-no-ref/ tdi_p0_26: tdi_p0_26 {
+				pinmux = <MAX32_PINMUX(0, 26, AF1)>;
+			};
+
+			/omit-if-no-ref/ tdo_p0_27: tdo_p0_27 {
+				pinmux = <MAX32_PINMUX(0, 27, AF1)>;
+			};
+
+			/omit-if-no-ref/ tms_p0_28: tms_p0_28 {
+				pinmux = <MAX32_PINMUX(0, 28, AF1)>;
+			};
+
+			/omit-if-no-ref/ tck_p0_29: tck_p0_29 {
+				pinmux = <MAX32_PINMUX(0, 29, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_b0_p0_30: clcd_b0_p0_30 {
+				pinmux = <MAX32_PINMUX(0, 30, AF2)>;
+			};
+
+			/omit-if-no-ref/ kcal32_p0_31: kcal32_p0_31 {
+				pinmux = <MAX32_PINMUX(0, 31, AF1)>;
+			};
+
+			/omit-if-no-ref/ sdhc_cdn_p0_31: sdhc_cdn_p0_31 {
+				pinmux = <MAX32_PINMUX(0, 31, AF2)>;
+			};
+
+			/omit-if-no-ref/ sdhc_cmd_p1_0: sdhc_cmd_p1_0 {
+				pinmux = <MAX32_PINMUX(1, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixf_sdio3_p1_0: spixf_sdio3_p1_0 {
+				pinmux = <MAX32_PINMUX(1, 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ sdhc_dat2_p1_1: sdhc_dat2_p1_1 {
+				pinmux = <MAX32_PINMUX(1, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixf_sdio1_p1_1: spixf_sdio1_p1_1 {
+				pinmux = <MAX32_PINMUX(1, 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ sdhc_wp_p1_2: sdhc_wp_p1_2 {
+				pinmux = <MAX32_PINMUX(1, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixf_ss0_p1_2: spixf_ss0_p1_2 {
+				pinmux = <MAX32_PINMUX(1, 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ sdhc_dat3_p1_3: sdhc_dat3_p1_3 {
+				pinmux = <MAX32_PINMUX(1, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_clk_p1_3: clcd_clk_p1_3 {
+				pinmux = <MAX32_PINMUX(1, 3, AF2)>;
+			};
+
+			/omit-if-no-ref/ sdhc_dat0_p1_4: sdhc_dat0_p1_4 {
+				pinmux = <MAX32_PINMUX(1, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixf_sdio0_p1_4: spixf_sdio0_p1_4 {
+				pinmux = <MAX32_PINMUX(1, 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ sdhc_clk_p1_5: sdhc_clk_p1_5 {
+				pinmux = <MAX32_PINMUX(1, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixf_sck_p1_5: spixf_sck_p1_5 {
+				pinmux = <MAX32_PINMUX(1, 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ sdhc_dat1_p1_6: sdhc_dat1_p1_6 {
+				pinmux = <MAX32_PINMUX(1, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt0_p1_6: pt0_p1_6 {
+				pinmux = <MAX32_PINMUX(1, 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart2_cts_p1_7: uart2_cts_p1_7 {
+				pinmux = <MAX32_PINMUX(1, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt1_p1_7: pt1_p1_7 {
+				pinmux = <MAX32_PINMUX(1, 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart2_rts_p1_8: uart2_rts_p1_8 {
+				pinmux = <MAX32_PINMUX(1, 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt2_p1_8: pt2_p1_8 {
+				pinmux = <MAX32_PINMUX(1, 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart2_rx_p1_9: uart2_rx_p1_9 {
+				pinmux = <MAX32_PINMUX(1, 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt3_p1_9: pt3_p1_9 {
+				pinmux = <MAX32_PINMUX(1, 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart2_tx_p1_10: uart2_tx_p1_10 {
+				pinmux = <MAX32_PINMUX(1, 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt4_p1_10: pt4_p1_10 {
+				pinmux = <MAX32_PINMUX(1, 10, AF2)>;
+			};
+
+			/omit-if-no-ref/ hyp_cs0_p1_11: hyp_cs0_p1_11 {
+				pinmux = <MAX32_PINMUX(1, 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixr_sdio_p1_11: spixr_sdio_p1_11 {
+				pinmux = <MAX32_PINMUX(1, 11, AF2)>;
+			};
+
+			/omit-if-no-ref/ hyp_d0_p1_12: hyp_d0_p1_12 {
+				pinmux = <MAX32_PINMUX(1, 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixr_sdio1_p1_12: spixr_sdio1_p1_12 {
+				pinmux = <MAX32_PINMUX(1, 12, AF2)>;
+			};
+
+			/omit-if-no-ref/ hyp_d4_p1_13: hyp_d4_p1_13 {
+				pinmux = <MAX32_PINMUX(1, 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixr_ss0_p1_13: spixr_ss0_p1_13 {
+				pinmux = <MAX32_PINMUX(1, 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ hyp_rwds_p1_14: hyp_rwds_p1_14 {
+				pinmux = <MAX32_PINMUX(1, 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt5_p1_14: pt5_p1_14 {
+				pinmux = <MAX32_PINMUX(1, 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ hyp_d1_p1_15: hyp_d1_p1_15 {
+				pinmux = <MAX32_PINMUX(1, 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixr_sdio2_p1_15: spixr_sdio2_p1_15 {
+				pinmux = <MAX32_PINMUX(1, 15, AF2)>;
+			};
+
+			/omit-if-no-ref/ hyp_d5_p1_16: hyp_d5_p1_16 {
+				pinmux = <MAX32_PINMUX(1, 16, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixr_sck_p1_16: spixr_sck_p1_16 {
+				pinmux = <MAX32_PINMUX(1, 16, AF2)>;
+			};
+
+			/omit-if-no-ref/ pt9_p1_17: pt9_p1_17 {
+				pinmux = <MAX32_PINMUX(1, 17, AF1)>;
+			};
+
+			/omit-if-no-ref/ hyp_d6_p1_18: hyp_d6_p1_18 {
+				pinmux = <MAX32_PINMUX(1, 18, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt6_p1_18: pt6_p1_18 {
+				pinmux = <MAX32_PINMUX(1, 18, AF2)>;
+			};
+
+			/omit-if-no-ref/ hyp_d2_p1_19: hyp_d2_p1_19 {
+				pinmux = <MAX32_PINMUX(1, 19, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt7_p1_19: pt7_p1_19 {
+				pinmux = <MAX32_PINMUX(1, 19, AF2)>;
+			};
+
+			/omit-if-no-ref/ hyp_d3_p1_20: hyp_d3_p1_20 {
+				pinmux = <MAX32_PINMUX(1, 20, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_hsync_p1_20: clcd_hsync_p1_20 {
+				pinmux = <MAX32_PINMUX(1, 20, AF2)>;
+			};
+
+			/omit-if-no-ref/ hyp_d7_p1_21: hyp_d7_p1_21 {
+				pinmux = <MAX32_PINMUX(1, 21, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt8_p1_21: pt8_p1_21 {
+				pinmux = <MAX32_PINMUX(1, 21, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_ss0_p1_23: spi1_ss0_p1_23 {
+				pinmux = <MAX32_PINMUX(1, 23, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_b1_p1_23: clcd_b1_p1_23 {
+				pinmux = <MAX32_PINMUX(1, 23, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_ss2_p1_24: spi1_ss2_p1_24 {
+				pinmux = <MAX32_PINMUX(1, 24, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_b2_p1_24: clcd_b2_p1_24 {
+				pinmux = <MAX32_PINMUX(1, 24, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_ss1_p1_25: spi1_ss1_p1_25 {
+				pinmux = <MAX32_PINMUX(1, 25, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_b3_p1_25: clcd_b3_p1_25 {
+				pinmux = <MAX32_PINMUX(1, 25, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_sck_p1_26: spi1_sck_p1_26 {
+				pinmux = <MAX32_PINMUX(1, 26, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_b4_p1_26: clcd_b4_p1_26 {
+				pinmux = <MAX32_PINMUX(1, 26, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_ss3_p1_27: spi1_ss3_p1_27 {
+				pinmux = <MAX32_PINMUX(1, 27, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_b5_p1_27: clcd_b5_p1_27 {
+				pinmux = <MAX32_PINMUX(1, 27, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_miso_p1_28: spi1_miso_p1_28 {
+				pinmux = <MAX32_PINMUX(1, 28, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_b6_p1_28: clcd_b6_p1_28 {
+				pinmux = <MAX32_PINMUX(1, 28, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_p1_29: spi1_mosi_p1_29 {
+				pinmux = <MAX32_PINMUX(1, 29, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_b7_p1_29: clcd_b7_p1_29 {
+				pinmux = <MAX32_PINMUX(1, 29, AF2)>;
+			};
+
+			/omit-if-no-ref/ owm_pupen_p1_30: owm_pupen_p1_30 {
+				pinmux = <MAX32_PINMUX(1, 30, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_r0_p1_30: clcd_r0_p1_30 {
+				pinmux = <MAX32_PINMUX(1, 30, AF2)>;
+			};
+
+			/omit-if-no-ref/ owm_io_p1_31: owm_io_p1_31 {
+				pinmux = <MAX32_PINMUX(1, 31, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_r1_p1_31: clcd_r1_p1_31 {
+				pinmux = <MAX32_PINMUX(1, 31, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi2_ss2_p2_0: spi2_ss2_p2_0 {
+				pinmux = <MAX32_PINMUX(2, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt9_p2_0: pt9_p2_0 {
+				pinmux = <MAX32_PINMUX(2, 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi2_ss1_p2_1: spi2_ss1_p2_1 {
+				pinmux = <MAX32_PINMUX(2, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt10_p2_1: pt10_p2_1 {
+				pinmux = <MAX32_PINMUX(2, 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi2_sck_p2_2: spi2_sck_p2_2 {
+				pinmux = <MAX32_PINMUX(2, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_lend_p2_2: clcd_lend_p2_2 {
+				pinmux = <MAX32_PINMUX(2, 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi2_miso_p2_3: spi2_miso_p2_3 {
+				pinmux = <MAX32_PINMUX(2, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_pwren_p2_3: clcd_pwren_p2_3 {
+				pinmux = <MAX32_PINMUX(2, 3, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi2_mosi_p2_4: spi2_mosi_p2_4 {
+				pinmux = <MAX32_PINMUX(2, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi2_ss0_p2_5: spi2_ss0_p2_5 {
+				pinmux = <MAX32_PINMUX(2, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt11_p2_5: pt11_p2_5 {
+				pinmux = <MAX32_PINMUX(2, 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi2_ss3_p2_6: spi2_ss3_p2_6 {
+				pinmux = <MAX32_PINMUX(2, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_vsync_p2_6: clcd_vsync_p2_6 {
+				pinmux = <MAX32_PINMUX(2, 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c0_sda_p2_7: i2c0_sda_p2_7 {
+				pinmux = <MAX32_PINMUX(2, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ i2c0_scl_p2_8: i2c0_scl_p2_8 {
+				pinmux = <MAX32_PINMUX(2, 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0_cts_p2_9: uart0_cts_p2_9 {
+				pinmux = <MAX32_PINMUX(2, 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt12_p2_9: pt12_p2_9 {
+				pinmux = <MAX32_PINMUX(2, 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart0_rts_p2_10: uart0_rts_p2_10 {
+				pinmux = <MAX32_PINMUX(2, 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt14_p2_10: pt14_p2_10 {
+				pinmux = <MAX32_PINMUX(2, 10, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart0_rx_p2_11: uart0_rx_p2_11 {
+				pinmux = <MAX32_PINMUX(2, 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt13_p2_11: pt13_p2_11 {
+				pinmux = <MAX32_PINMUX(2, 11, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart0_tx_p2_12: uart0_tx_p2_12 {
+				pinmux = <MAX32_PINMUX(2, 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt15_p2_12: pt15_p2_12 {
+				pinmux = <MAX32_PINMUX(2, 12, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_cts_p2_13: uart1_cts_p2_13 {
+				pinmux = <MAX32_PINMUX(2, 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_r2_p2_13: clcd_r2_p2_13 {
+				pinmux = <MAX32_PINMUX(2, 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_rx_p2_14: uart1_rx_p2_14 {
+				pinmux = <MAX32_PINMUX(2, 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_r3_p2_14: clcd_r3_p2_14 {
+				pinmux = <MAX32_PINMUX(2, 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_rts_p2_15: uart1_rts_p2_15 {
+				pinmux = <MAX32_PINMUX(2, 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_r4_p2_15: clcd_r4_p2_15 {
+				pinmux = <MAX32_PINMUX(2, 15, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_tx_p2_16: uart1_tx_p2_16 {
+				pinmux = <MAX32_PINMUX(2, 16, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_r5_p2_16: clcd_r5_p2_16 {
+				pinmux = <MAX32_PINMUX(2, 16, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_p2_17: i2c1_sda_p2_17 {
+				pinmux = <MAX32_PINMUX(2, 17, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_r6_p2_17: clcd_r6_p2_17 {
+				pinmux = <MAX32_PINMUX(2, 17, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_p2_18: i2c1_scl_p2_18 {
+				pinmux = <MAX32_PINMUX(2, 18, AF1)>;
+			};
+
+			/omit-if-no-ref/ clcd_r7_p2_18: clcd_r7_p2_18 {
+				pinmux = <MAX32_PINMUX(2, 18, AF2)>;
+			};
+
+			/omit-if-no-ref/ pt6_p2_23: pt6_p2_23 {
+				pinmux = <MAX32_PINMUX(2, 23, AF1)>;
+			};
+
+			/omit-if-no-ref/ spixr_sdio3_p2_23: spixr_sdio3_p2_23 {
+				pinmux = <MAX32_PINMUX(2, 23, AF2)>;
+			};
+
+			/omit-if-no-ref/ pt11_p2_25: pt11_p2_25 {
+				pinmux = <MAX32_PINMUX(2, 25, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt12_p2_26: pt12_p2_26 {
+				pinmux = <MAX32_PINMUX(2, 26, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt14_p2_28: pt14_p2_28 {
+				pinmux = <MAX32_PINMUX(2, 28, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt1_p2_30: pt1_p2_30 {
+				pinmux = <MAX32_PINMUX(2, 30, AF1)>;
+			};
+
+			/omit-if-no-ref/ pdown_p3_0: pdown_p3_0 {
+				pinmux = <MAX32_PINMUX(3, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ hyp_cs1_p3_0: hyp_cs1_p3_0 {
+				pinmux = <MAX32_PINMUX(3, 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi0_miso_p3_1: spi0_miso_p3_1 {
+				pinmux = <MAX32_PINMUX(3, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0_mosi_p3_2: spi0_mosi_p3_2 {
+				pinmux = <MAX32_PINMUX(3, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0_sck_p3_3: spi0_sck_p3_3 {
+				pinmux = <MAX32_PINMUX(3, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr0_p3_4: tmr0_p3_4 {
+				pinmux = <MAX32_PINMUX(3, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr2_p3_5: tmr2_p3_5 {
+				pinmux = <MAX32_PINMUX(3, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr4_p3_6: tmr4_p3_6 {
+				pinmux = <MAX32_PINMUX(3, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr1_p3_7: tmr1_p3_7 {
+				pinmux = <MAX32_PINMUX(3, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr3_p3_8: tmr3_p3_8 {
+				pinmux = <MAX32_PINMUX(3, 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr5_p3_9: tmr5_p3_9 {
+				pinmux = <MAX32_PINMUX(3, 9, AF1)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/adi/max32/max32650.dtsi b/dts/arm/adi/max32/max32650.dtsi
new file mode 100644
index 00000000000..e2447636d15
--- /dev/null
+++ b/dts/arm/adi/max32/max32650.dtsi
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <adi/max32/max32xxx.dtsi>
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_M(1)>;
+};
+
+&flash0 {
+	reg = <0x10000000 DT_SIZE_M(3)>;
+	erase-block-size = <16384>;
+};
+
+&clk_ipo {
+	clock-frequency = <DT_FREQ_M(120)>;
+};
+
+&clk_iso {
+	clock-frequency = <DT_FREQ_M(50)>;
+};
+
+/delete-node/ &clk_erfo;
+
+/delete-node/ &i2c2;
+
+/delete-node/ &trng;
+
+&pinctrl {
+	reg = <0x40008000 0x4000>;
+
+	gpio2: gpio@4000a000 {
+		reg = <0x4000a000 0x1000>;
+		compatible = "adi,max32-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupts = <26 0>;
+		clocks = <&gcr ADI_MAX32_CLOCK_BUS0 2>;
+		status = "disabled";
+	};
+
+	gpio3: gpio@4000b000 {
+		reg = <0x4000b000 0x1000>;
+		compatible = "adi,max32-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupts = <58 0>;
+		clocks = <&gcr ADI_MAX32_CLOCK_BUS1 6>;
+		status = "disabled";
+	};
+};
+
+/* MAX32650 extra peripherals. */
+/ {
+	soc {
+		trng: trng@400b5000 {
+			compatible = "adi,max32-trng";
+			reg = <0x400b5000 0x1000>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 2>;
+			status = "disabled";
+		};
+
+		timer4: timer@40014000 {
+			compatible = "adi,max32-timer";
+			reg = <0x40014000 0x1000>;
+			interrupts = <9 0>;
+			status = "disabled";
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 19>;
+			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
+			prescaler = <1>;
+
+			counter {
+				compatible = "adi,max32-counter";
+				status = "disabled";
+			};
+
+			pwm {
+				compatible = "adi,max32-pwm";
+				status = "disabled";
+				#pwm-cells = <3>;
+			};
+		};
+
+		timer5: timer@40015000 {
+			compatible = "adi,max32-timer";
+			reg = <0x40015000 0x1000>;
+			interrupts = <10 0>;
+			status = "disabled";
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 20>;
+			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
+			prescaler = <1>;
+
+			counter {
+				compatible = "adi,max32-counter";
+				status = "disabled";
+			};
+
+			pwm {
+				compatible = "adi,max32-pwm";
+				status = "disabled";
+				#pwm-cells = <3>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/adi/max32/max32655.dtsi b/dts/arm/adi/max32/max32655.dtsi
index 71bbc485fad..fd148a6ac8d 100644
--- a/dts/arm/adi/max32/max32655.dtsi
+++ b/dts/arm/adi/max32/max32655.dtsi
@@ -6,6 +6,7 @@
 
 #include <arm/armv7-m.dtsi>
 #include <adi/max32/max32xxx.dtsi>
+#include <zephyr/dt-bindings/dma/max32655_dma.h>
 
 &pinctrl {
 	reg = <0x40008000 0x2400>;
diff --git a/dts/arm/adi/max32/max32660-pinctrl.dtsi b/dts/arm/adi/max32/max32660-pinctrl.dtsi
new file mode 100644
index 00000000000..cfb872c11d3
--- /dev/null
+++ b/dts/arm/adi/max32/max32660-pinctrl.dtsi
@@ -0,0 +1,149 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@40008000 {
+			/omit-if-no-ref/ swdio_p0_0: swdio_p0_0 {
+				pinmux = <MAX32_PINMUX(0, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1_miso_p0_0: spi1_miso_p0_0 {
+				pinmux = <MAX32_PINMUX(0, 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_tx_p0_0: uart1_tx_p0_0 {
+				pinmux = <MAX32_PINMUX(0, 0, AF3)>;
+			};
+
+			/omit-if-no-ref/ swdclk_p0_1: swdclk_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_p0_1: spi1_mosi_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_rx_p0_1: uart1_rx_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF3)>;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_p0_2: i2c1_scl_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1_sck_p0_2: spi1_sck_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ cal32k_p0_2: cal32k_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF3)>;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_p0_3: i2c1_sda_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi1_ss0_p0_3: spi1_ss0_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr0_p0_3: tmr0_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF3)>;
+			};
+
+			/omit-if-no-ref/ spi0_miso_p0_4: spi0_miso_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0_tx_p0_4: uart0_tx_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi0_mosi_p0_5: spi0_mosi_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0_rx_p0_5: uart0_rx_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi0_sck_p0_6: spi0_sck_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0_cts_p0_6: uart0_cts_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_tx_p0_6: uart1_tx_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF3)>;
+			};
+
+			/omit-if-no-ref/ spi0_ss0_p0_7: spi0_ss0_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0_rts_p0_7: uart0_rts_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_rx_p0_7: uart1_rx_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF3)>;
+			};
+
+			/omit-if-no-ref/ i2c0_scl_p0_8: i2c0_scl_p0_8 {
+				pinmux = <MAX32_PINMUX(0, 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ swdio_p0_8: swdio_p0_8 {
+				pinmux = <MAX32_PINMUX(0, 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c0_sda_p0_9: i2c0_sda_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ swdclk_p0_9: swdclk_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_miso_p0_10: spi1_miso_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1_tx_p0_10: uart1_tx_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_p0_11: spi1_mosi_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1_rx_p0_11: uart1_rx_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_sck_p0_12: spi1_sck_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1_cts_p0_12: uart1_cts_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_ss0_p0_13: spi1_ss0_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart1_rts_p0_13: uart1_rts_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF2)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/adi/max32/max32660.dtsi b/dts/arm/adi/max32/max32660.dtsi
new file mode 100644
index 00000000000..b93b451ffd8
--- /dev/null
+++ b/dts/arm/adi/max32/max32660.dtsi
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <adi/max32/max32xxx.dtsi>
+#include <zephyr/dt-bindings/dma/max32660_dma.h>
+
+&clk_ipo {
+	clock-frequency = <DT_FREQ_M(96)>;
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(16)>;
+};
+
+/delete-node/ &clk_iso;
+/delete-node/ &clk_ibro;
+/delete-node/ &clk_erfo;
+/delete-node/ &adc;
+/delete-node/ &gpio1;
+/delete-node/ &i2c2;
+/delete-node/ &uart2;
+/delete-node/ &timer3;
+/delete-node/ &trng;
+/delete-node/ &flash0;
+
+&flc0 {
+	flash0: flash@0{
+		compatible = "soc-nv-flash";
+		reg = <0x00000000 DT_SIZE_K(256)>;
+		write-block-size = <16>;
+		erase-block-size = <8192>;
+	};
+};
+
+/* MAX32660 extra peripherals. */
+/ {
+	chosen {
+		/delete-property/ zephyr,entropy;
+	};
+
+	soc {
+		sram1: memory@20004000 {
+			compatible = "mmio-sram";
+			reg = <0x20004000 DT_SIZE_K(16)>;
+		};
+
+		sram2: memory@20008000 {
+			compatible = "mmio-sram";
+			reg = <0x20008000 DT_SIZE_K(32)>;
+		};
+
+		sram3: memory@20010000 {
+			compatible = "mmio-sram";
+			reg = <0x20010000 DT_SIZE_K(32)>;
+		};
+
+		dma0: dma@40028000 {
+			compatible = "adi,max32-dma";
+			reg = <0x40028000 0x1000>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
+			interrupts = <28 0>, <29 0>, <30 0>, <31 0>;
+			dma-channels = <4>;
+			status = "disabled";
+			#dma-cells = <2>;
+		};
+
+		spi0: spi@40046000 {
+			compatible = "adi,max32-spi";
+			reg = <0x40046000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
+			interrupts = <16 0>;
+			status = "disabled";
+		};
+
+		spi1: spi@40019000 {
+			compatible = "adi,max32-spi";
+			reg = <0x40019000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
+			interrupts = <17 0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/dts/arm/adi/max32/max32662.dtsi b/dts/arm/adi/max32/max32662.dtsi
index 51a4e8201eb..b2d8c6614ad 100644
--- a/dts/arm/adi/max32/max32662.dtsi
+++ b/dts/arm/adi/max32/max32662.dtsi
@@ -24,6 +24,10 @@
 
 /delete-node/ &timer3;
 
+/delete-node/ &i2c2;
+
+/delete-node/ &rtc_counter;
+
 &adc {
 	compatible = "adi,max32-adc-sar", "adi,max32-adc";
 	clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
@@ -116,5 +120,12 @@
 				status = "disabled";
 			};
 		};
+
+		rtc_counter: rtc_counter@40106000 {
+			compatible = "adi,max32-rtc-counter";
+			reg = <0x40106000 0x400>;
+			interrupts = <3 0>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/dts/arm/adi/max32/max32666.dtsi b/dts/arm/adi/max32/max32666.dtsi
index e697a912b41..d49cb6c4921 100644
--- a/dts/arm/adi/max32/max32666.dtsi
+++ b/dts/arm/adi/max32/max32666.dtsi
@@ -174,5 +174,19 @@
 			interrupts = <67 0>;
 			status = "disabled";
 		};
+
+		sdhc0: sdhc@400b6000 {
+			compatible = "adi,max32-sdhc";
+			reg = <0x400b6000 0x1000>;
+			interrupts = <66 0>;
+			status = "disabled";
+			mmc {
+				compatible = "zephyr,sdmmc-disk";
+				status = "disabled";
+				disk-name = "SD";
+			};
+			power-delay-ms = <1500>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 10>;
+		};
 	};
 };
diff --git a/dts/arm/adi/max32/max32670.dtsi b/dts/arm/adi/max32/max32670.dtsi
index c15e860ea9a..cb4e1aae0bf 100644
--- a/dts/arm/adi/max32/max32670.dtsi
+++ b/dts/arm/adi/max32/max32670.dtsi
@@ -20,6 +20,12 @@
 	clock-frequency = <DT_FREQ_K(80)>;
 };
 
+&i2c2 {
+	clocks = <&gcr ADI_MAX32_CLOCK_BUS1 21>;
+};
+
+/delete-node/ &rtc_counter;
+
 /* MAX32670 extra peripherals. */
 / {
 	soc {
@@ -143,5 +149,12 @@
 				status = "disabled";
 			};
 		};
+
+		rtc_counter: rtc_counter@40106000 {
+			compatible = "adi,max32-rtc-counter";
+			reg = <0x40106000 0x400>;
+			interrupts = <3 0>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/dts/arm/adi/max32/max32672.dtsi b/dts/arm/adi/max32/max32672.dtsi
index 6fbd471ad9c..1531f4b2f6b 100644
--- a/dts/arm/adi/max32/max32672.dtsi
+++ b/dts/arm/adi/max32/max32672.dtsi
@@ -22,6 +22,8 @@
 
 /delete-node/ &clk_iso;
 
+/delete-node/ &rtc_counter;
+
 &adc {
 	compatible = "adi,max32-adc-sar", "adi,max32-adc";
 	clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
@@ -173,5 +175,12 @@
 				status = "disabled";
 			};
 		};
+
+		rtc_counter: rtc_counter@40106000 {
+			compatible = "adi,max32-rtc-counter";
+			reg = <0x40106000 0x400>;
+			interrupts = <3 0>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/dts/arm/adi/max32/max32675.dtsi b/dts/arm/adi/max32/max32675.dtsi
index 6bb2562771d..10065112d0f 100644
--- a/dts/arm/adi/max32/max32675.dtsi
+++ b/dts/arm/adi/max32/max32675.dtsi
@@ -20,8 +20,13 @@
 	clock-frequency = <DT_FREQ_K(80)>;
 };
 
+&i2c2 {
+	clocks = <&gcr ADI_MAX32_CLOCK_BUS1 21>;
+};
+
 /delete-node/ &clk_iso;
 /delete-node/ &uart1;
+/delete-node/ &rtc_counter;
 
 /* MAX32675 extra peripherals. */
 / {
@@ -90,5 +95,12 @@
 			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
 			prescaler = <1>;
 		};
+
+		rtc_counter: rtc_counter@40106000 {
+			compatible = "adi,max32-rtc-counter";
+			reg = <0x40106000 0x400>;
+			interrupts = <3 0>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/dts/arm/adi/max32/max32690.dtsi b/dts/arm/adi/max32/max32690.dtsi
index 52a93bff4e6..199ddba78df 100644
--- a/dts/arm/adi/max32/max32690.dtsi
+++ b/dts/arm/adi/max32/max32690.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023-2024 Analog Devices, Inc.
+ * Copyright (c) 2023-2025 Analog Devices, Inc.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -232,5 +232,17 @@
 			interrupts = <67 0>;
 			status = "disabled";
 		};
+
+		usbhs: usbhs@400b1000 {
+			compatible = "adi,max32-usbhs";
+			reg = <0x400b1000 0x1000>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 3>;
+			interrupts = <2 0>;
+			num-bidir-endpoints = <1>;
+			num-in-endpoints = <6>;
+			num-out-endpoints = <7>;
+			maximum-speed = "high-speed";
+			status = "disabled";
+		};
 	};
 };
diff --git a/dts/arm/adi/max32/max78000-pinctrl.dtsi b/dts/arm/adi/max32/max78000-pinctrl.dtsi
new file mode 100644
index 00000000000..0cc2d876d8b
--- /dev/null
+++ b/dts/arm/adi/max32/max78000-pinctrl.dtsi
@@ -0,0 +1,409 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
+
+/ {
+	soc {
+		pinctrl: pin-controller@40008000 {
+			/omit-if-no-ref/ uart0a_rx_p0_0: uart0a_rx_p0_0 {
+				pinmux = <MAX32_PINMUX(0, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0a_tx_p0_1: uart0a_tx_p0_1 {
+				pinmux = <MAX32_PINMUX(0, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr0a_ioa_p0_2: tmr0a_ioa_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0b_cts_p0_2: uart0b_cts_p0_2 {
+				pinmux = <MAX32_PINMUX(0, 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ ext_clk_p0_3: ext_clk_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr0a_iob_p0_3: tmr0a_iob_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ uart0b_rts_p0_3: uart0b_rts_p0_3 {
+				pinmux = <MAX32_PINMUX(0, 3, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi0_ss0_p0_4: spi0_ss0_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr0b_ioan_p0_4: tmr0b_ioan_p0_4 {
+				pinmux = <MAX32_PINMUX(0, 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi0_mosi_p0_5: spi0_mosi_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr0b_iobn_p0_5: tmr0b_iobn_p0_5 {
+				pinmux = <MAX32_PINMUX(0, 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi0_miso_p0_6: spi0_miso_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ owm_io_p0_6: owm_io_p0_6 {
+				pinmux = <MAX32_PINMUX(0, 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi0_sck_p0_7: spi0_sck_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ owm_pe_p0_7: owm_pe_p0_7 {
+				pinmux = <MAX32_PINMUX(0, 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi0_sdio2_p0_8: spi0_sdio2_p0_8 {
+				pinmux = <MAX32_PINMUX(0, 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr0b_ioa_p0_8: tmr0b_ioa_p0_8 {
+				pinmux = <MAX32_PINMUX(0, 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi0_sdio3_p0_9: spi0_sdio3_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr0b_iob_p0_9: tmr0b_iob_p0_9 {
+				pinmux = <MAX32_PINMUX(0, 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c0_scl_p0_10: i2c0_scl_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0_ss2_p0_10: spi0_ss2_p0_10 {
+				pinmux = <MAX32_PINMUX(0, 10, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c0_sda_p0_11: i2c0_sda_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF1)>;
+			};
+
+			/omit-if-no-ref/ spi0_ss1_p0_11: spi0_ss1_p0_11 {
+				pinmux = <MAX32_PINMUX(0, 11, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_rx_p0_12: uart1_rx_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr1b_ioan_p0_12: tmr1b_ioan_p0_12 {
+				pinmux = <MAX32_PINMUX(0, 12, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart1_tx_p0_13: uart1_tx_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr1b_iobn_p0_13: tmr1b_iobn_p0_13 {
+				pinmux = <MAX32_PINMUX(0, 13, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr1a_ioa_p0_14: tmr1a_ioa_p0_14 {
+				pinmux = <MAX32_PINMUX(0, 14, AF1)>;
+			};
+
+			/omit-if-no-ref/ i2s_clkext_p0_14: i2s_clkext_p0_14 {
+				pinmux = <MAX32_PINMUX(0, 14, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr1a_iob_p0_15: tmr1a_iob_p0_15 {
+				pinmux = <MAX32_PINMUX(0, 15, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_vsync_p0_15: pcif_vsync_p0_15 {
+				pinmux = <MAX32_PINMUX(0, 15, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c1_scl_p0_16: i2c1_scl_p0_16 {
+				pinmux = <MAX32_PINMUX(0, 16, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt2_p0_16: pt2_p0_16 {
+				pinmux = <MAX32_PINMUX(0, 16, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c1_sda_p0_17: i2c1_sda_p0_17 {
+				pinmux = <MAX32_PINMUX(0, 17, AF1)>;
+			};
+
+			/omit-if-no-ref/ pt3_p0_17: pt3_p0_17 {
+				pinmux = <MAX32_PINMUX(0, 17, AF2)>;
+			};
+
+			/omit-if-no-ref/ pt0_p0_18: pt0_p0_18 {
+				pinmux = <MAX32_PINMUX(0, 18, AF1)>;
+			};
+
+			/omit-if-no-ref/ owm_io_p0_18: owm_io_p0_18 {
+				pinmux = <MAX32_PINMUX(0, 18, AF2)>;
+			};
+
+			/omit-if-no-ref/ pt1_p0_19: pt1_p0_19 {
+				pinmux = <MAX32_PINMUX(0, 19, AF1)>;
+			};
+
+			/omit-if-no-ref/ owm_pe_p0_19: owm_pe_p0_19 {
+				pinmux = <MAX32_PINMUX(0, 19, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_ss0_p0_20: spi1_ss0_p0_20 {
+				pinmux = <MAX32_PINMUX(0, 20, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d0_p0_20: pcif_d0_p0_20 {
+				pinmux = <MAX32_PINMUX(0, 20, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_mosi_p0_21: spi1_mosi_p0_21 {
+				pinmux = <MAX32_PINMUX(0, 21, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d1_p0_21: pcif_d1_p0_21 {
+				pinmux = <MAX32_PINMUX(0, 21, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_miso_p0_22: spi1_miso_p0_22 {
+				pinmux = <MAX32_PINMUX(0, 22, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d2_p0_22: pcif_d2_p0_22 {
+				pinmux = <MAX32_PINMUX(0, 22, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_sck_p0_23: spi1_sck_p0_23 {
+				pinmux = <MAX32_PINMUX(0, 23, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d3_p0_23: pcif_d3_p0_23 {
+				pinmux = <MAX32_PINMUX(0, 23, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_sdio2_p0_24: spi1_sdio2_p0_24 {
+				pinmux = <MAX32_PINMUX(0, 24, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d4_p0_24: pcif_d4_p0_24 {
+				pinmux = <MAX32_PINMUX(0, 24, AF2)>;
+			};
+
+			/omit-if-no-ref/ spi1_sdio3_p0_25: spi1_sdio3_p0_25 {
+				pinmux = <MAX32_PINMUX(0, 25, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d5_p0_25: pcif_d5_p0_25 {
+				pinmux = <MAX32_PINMUX(0, 25, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr2_ioa_p0_26: tmr2_ioa_p0_26 {
+				pinmux = <MAX32_PINMUX(0, 26, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d6_p0_26: pcif_d6_p0_26 {
+				pinmux = <MAX32_PINMUX(0, 26, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr2_iob_p0_27: tmr2_iob_p0_27 {
+				pinmux = <MAX32_PINMUX(0, 27, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d7_p0_27: pcif_d7_p0_27 {
+				pinmux = <MAX32_PINMUX(0, 27, AF2)>;
+			};
+
+			/omit-if-no-ref/ swdio_p0_28: swdio_p0_28 {
+				pinmux = <MAX32_PINMUX(0, 28, AF1)>;
+			};
+
+			/omit-if-no-ref/ swclk_p0_29: swclk_p0_29 {
+				pinmux = <MAX32_PINMUX(0, 29, AF1)>;
+			};
+
+			/omit-if-no-ref/ i2c2_scl_p0_30: i2c2_scl_p0_30 {
+				pinmux = <MAX32_PINMUX(0, 30, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d8_p0_30: pcif_d8_p0_30 {
+				pinmux = <MAX32_PINMUX(0, 30, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2c2_sda_p0_31: i2c2_sda_p0_31 {
+				pinmux = <MAX32_PINMUX(0, 31, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d9_p0_31: pcif_d9_p0_31 {
+				pinmux = <MAX32_PINMUX(0, 31, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart2_rx_p1_0: uart2_rx_p1_0 {
+				pinmux = <MAX32_PINMUX(1, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ rv_tck_p1_0: rv_tck_p1_0 {
+				pinmux = <MAX32_PINMUX(1, 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ uart2_tx_p1_1: uart2_tx_p1_1 {
+				pinmux = <MAX32_PINMUX(1, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ rv_tms_p1_1: rv_tms_p1_1 {
+				pinmux = <MAX32_PINMUX(1, 1, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2s_sck_p1_2: i2s_sck_p1_2 {
+				pinmux = <MAX32_PINMUX(1, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ rv_tdi_p1_2: rv_tdi_p1_2 {
+				pinmux = <MAX32_PINMUX(1, 2, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2s_ws_p1_3: i2s_ws_p1_3 {
+				pinmux = <MAX32_PINMUX(1, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ rv_tdo_p1_3: rv_tdo_p1_3 {
+				pinmux = <MAX32_PINMUX(1, 3, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2s_sdi_p1_4: i2s_sdi_p1_4 {
+				pinmux = <MAX32_PINMUX(1, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr3b_ioa_p1_4: tmr3b_ioa_p1_4 {
+				pinmux = <MAX32_PINMUX(1, 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ i2s_sdo_p1_5: i2s_sdo_p1_5 {
+				pinmux = <MAX32_PINMUX(1, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ tmr3b_iob_p1_5: tmr3b_iob_p1_5 {
+				pinmux = <MAX32_PINMUX(1, 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr3a_ioa_p1_6: tmr3a_ioa_p1_6 {
+				pinmux = <MAX32_PINMUX(1, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d10_p1_6: pcif_d10_p1_6 {
+				pinmux = <MAX32_PINMUX(1, 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ tmr3a_iob_p1_7: tmr3a_iob_p1_7 {
+				pinmux = <MAX32_PINMUX(1, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ pcif_d11_p1_7: pcif_d11_p1_7 {
+				pinmux = <MAX32_PINMUX(1, 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ pcif_hsync_p1_8: pcif_hsync_p1_8 {
+				pinmux = <MAX32_PINMUX(1, 8, AF1)>;
+			};
+
+			/omit-if-no-ref/ rxev0_p1_8: rxev0_p1_8 {
+				pinmux = <MAX32_PINMUX(1, 8, AF2)>;
+			};
+
+			/omit-if-no-ref/ pcif_pclk_p1_9: pcif_pclk_p1_9 {
+				pinmux = <MAX32_PINMUX(1, 9, AF1)>;
+			};
+
+			/omit-if-no-ref/ txev0_p1_9: txev0_p1_9 {
+				pinmux = <MAX32_PINMUX(1, 9, AF2)>;
+			};
+
+			/omit-if-no-ref/ ain0_p2_0: ain0_p2_0 {
+				pinmux = <MAX32_PINMUX(2, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ ain1_p2_1: ain1_p2_1 {
+				pinmux = <MAX32_PINMUX(2, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ ain2_p2_2: ain2_p2_2 {
+				pinmux = <MAX32_PINMUX(2, 2, AF1)>;
+			};
+
+			/omit-if-no-ref/ ain3_p2_3: ain3_p2_3 {
+				pinmux = <MAX32_PINMUX(2, 3, AF1)>;
+			};
+
+			/omit-if-no-ref/ ain4_p2_4: ain4_p2_4 {
+				pinmux = <MAX32_PINMUX(2, 4, AF1)>;
+			};
+
+			/omit-if-no-ref/ lptmr0b_ioa_p2_4: lptmr0b_ioa_p2_4 {
+				pinmux = <MAX32_PINMUX(2, 4, AF2)>;
+			};
+
+			/omit-if-no-ref/ ain5_p2_5: ain5_p2_5 {
+				pinmux = <MAX32_PINMUX(2, 5, AF1)>;
+			};
+
+			/omit-if-no-ref/ lptmr1b_ioa_p2_5: lptmr1b_ioa_p2_5 {
+				pinmux = <MAX32_PINMUX(2, 5, AF2)>;
+			};
+
+			/omit-if-no-ref/ ain6_p2_6: ain6_p2_6 {
+				pinmux = <MAX32_PINMUX(2, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ lptmr0_clk_p2_6: lptmr0_clk_p2_6 {
+				pinmux = <MAX32_PINMUX(2, 6, AF1)>;
+			};
+
+			/omit-if-no-ref/ lpuartb_rx_p2_6: lpuartb_rx_p2_6 {
+				pinmux = <MAX32_PINMUX(2, 6, AF2)>;
+			};
+
+			/omit-if-no-ref/ ain7_p2_7: ain7_p2_7 {
+				pinmux = <MAX32_PINMUX(2, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ lptmr1_clk_p2_7: lptmr1_clk_p2_7 {
+				pinmux = <MAX32_PINMUX(2, 7, AF1)>;
+			};
+
+			/omit-if-no-ref/ lpuartb_tx_p2_7: lpuartb_tx_p2_7 {
+				pinmux = <MAX32_PINMUX(2, 7, AF2)>;
+			};
+
+			/omit-if-no-ref/ pdown_p3_0: pdown_p3_0 {
+				pinmux = <MAX32_PINMUX(3, 0, AF1)>;
+			};
+
+			/omit-if-no-ref/ wakeup_p3_0: wakeup_p3_0 {
+				pinmux = <MAX32_PINMUX(3, 0, AF2)>;
+			};
+
+			/omit-if-no-ref/ sqwout_p3_1: sqwout_p3_1 {
+				pinmux = <MAX32_PINMUX(3, 1, AF1)>;
+			};
+
+			/omit-if-no-ref/ wakeup_p3_1: wakeup_p3_1 {
+				pinmux = <MAX32_PINMUX(3, 1, AF2)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/adi/max32/max78000.dtsi b/dts/arm/adi/max32/max78000.dtsi
new file mode 100644
index 00000000000..f20b0f73f07
--- /dev/null
+++ b/dts/arm/adi/max32/max78000.dtsi
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <adi/max32/max32xxx.dtsi>
+#include <zephyr/dt-bindings/dma/max78000_dma.h>
+
+&clk_ipo {
+	clock-frequency = <DT_FREQ_M(100)>;
+};
+
+&clk_inro {
+	clock-frequency = <DT_FREQ_K(30)>;
+};
+
+/delete-node/ &clk_erfo;
+
+&pinctrl {
+	reg = <0x40008000 0x2200>;
+
+	gpio2: gpio@40080400 {
+		reg = <0x40080400 0x200>;
+		compatible = "adi,max32-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupts = <26 0>;
+		clocks = <&gcr ADI_MAX32_CLOCK_BUS2 0>;
+		status = "disabled";
+	};
+
+	gpio3: gpio@40080600 {
+		reg = <0x40080600 0x200>; // Address and size are dummy.
+		compatible = "adi,max32-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupts = <54 0>;
+		status = "disabled";
+	};
+};
+
+/* MAX78000 extra peripherals. */
+/ {
+	soc {
+		sram1: memory@20008000 {
+			compatible = "mmio-sram";
+			reg = <0x20008000 DT_SIZE_K(32)>;
+		};
+
+		sram2: memory@20010000 {
+			compatible = "mmio-sram";
+			reg = <0x20010000 DT_SIZE_K(48)>;
+		};
+
+		sram3: memory@2001c000 {
+			compatible = "mmio-sram";
+			reg = <0x2001c000 DT_SIZE_K(16)>;
+		};
+
+		uart3: serial@40081400 {
+			compatible = "adi,max32-uart";
+			reg = <0x40081400 0x400>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 4>;
+			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
+			interrupts = <88 0>;
+			status = "disabled";
+		};
+
+		spi0: spi@400be000 {
+			compatible = "adi,max32-spi";
+			reg = <0x400be000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 16>;
+			interrupts = <56 0>;
+			status = "disabled";
+		};
+
+		spi1: spi@40046000 {
+			compatible = "adi,max32-spi";
+			reg = <0x40046000 0x2000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
+			interrupts = <16 0>;
+			status = "disabled";
+		};
+
+		dma0: dma@40028000 {
+			compatible = "adi,max32-dma";
+			reg = <0x40028000 0x1000>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
+			interrupts = <28 0>, <29 0>, <30 0>, <31 0>;
+			dma-channels = <4>;
+			status = "disabled";
+			#dma-cells = <2>;
+		};
+
+		w1: w1@4003d000 {
+			compatible = "adi,max32-w1";
+			reg = <0x4003d000 0x1000>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS1 13>;
+			interrupts = <67 0>;
+			status = "disabled";
+		};
+
+		wdt1: watchdog@40080800  {
+			compatible = "adi,max32-watchdog";
+			reg = <0x40080800 0x400>;
+			interrupts = <57 0>;
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 1>;
+			clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
+			status = "disabled";
+		};
+
+		lptimer0: timer@40080c00 {
+			compatible = "adi,max32-timer";
+			reg = <0x40080c00 0x400>;
+			interrupts = <9 0>;
+			status = "disabled";
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 2>;
+			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
+			prescaler = <1>;
+
+			pwm {
+				compatible = "adi,max32-pwm";
+				status = "disabled";
+				pinctrl-0 = <&lptmr0b_ioa_p2_4>;
+				pinctrl-names = "default";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "adi,max32-counter";
+				status = "disabled";
+			};
+		};
+
+		lptimer1: timer@40081000 {
+			compatible = "adi,max32-timer";
+			reg = <0x40081000 0x400>;
+			interrupts = <10 0>;
+			status = "disabled";
+			clocks = <&gcr ADI_MAX32_CLOCK_BUS2 3>;
+			clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
+			prescaler = <1>;
+
+			pwm {
+				compatible = "adi,max32-pwm";
+				status = "disabled";
+				pinctrl-0 = <&lptmr1b_ioa_p2_5>;
+				pinctrl-names = "default";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "adi,max32-counter";
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/dts/arm/ambiq/ambiq_apollo3_blue.dtsi b/dts/arm/ambiq/ambiq_apollo3_blue.dtsi
index 53ef76bbd20..d2d1e7e47c5 100644
--- a/dts/arm/ambiq/ambiq_apollo3_blue.dtsi
+++ b/dts/arm/ambiq/ambiq_apollo3_blue.dtsi
@@ -90,12 +90,6 @@
 			};
 		};
 
-		pwrcfg: pwrcfg@40021000 {
-			compatible = "ambiq,pwrctrl";
-			reg = <0x40021000 0x400>;
-			#pwrcfg-cells = <2>;
-		};
-
 		stimer0: stimer@40008140 {
 			compatible = "ambiq,stimer";
 			reg = <0x40008140 0x80>;
@@ -182,7 +176,6 @@
 			interrupt-names = "UART0";
 			status = "disabled";
 			clocks = <&uartclk>;
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
 			zephyr,pm-device-runtime-auto;
 		};
 
@@ -193,7 +186,6 @@
 			interrupt-names = "UART1";
 			status = "disabled";
 			clocks = <&uartclk>;
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
 			zephyr,pm-device-runtime-auto;
 		};
 
@@ -204,131 +196,137 @@
 			#size-cells = <0>;
 			interrupts = <4 0>;
 			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		spi0: spi@50004000 {
+		iom0: iom@50004000 {
+			compatible = "ambiq,iom";
 			reg = <0x50004000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <6 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
-			zephyr,pm-device-runtime-auto;
-		};
-
-		spi1: spi@50005000 {
-			reg = <0x50005000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <7 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
-			zephyr,pm-device-runtime-auto;
-		};
 
-		spi2: spi@50006000 {
-			reg = <0x50006000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <8 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
-			zephyr,pm-device-runtime-auto;
-		};
-
-		spi3: spi@50007000 {
-			reg = <0x50007000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <9 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
-			zephyr,pm-device-runtime-auto;
-		};
-
-		spi4: spi@50008000 {
-			reg = <0x50008000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <10 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
-			zephyr,pm-device-runtime-auto;
-		};
-
-		spi5: spi@50009000 {
-			reg = <0x50009000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <11 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
-			zephyr,pm-device-runtime-auto;
-		};
-
-		i2c0: i2c@50004000 {
-			reg = <0x50004000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <6 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
-			zephyr,pm-device-runtime-auto;
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		i2c1: i2c@50005000 {
+		iom1: iom@50005000 {
+			compatible = "ambiq,iom";
 			reg = <0x50005000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <7 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
-			zephyr,pm-device-runtime-auto;
+
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		i2c2: i2c@50006000 {
+		iom2: iom@50006000 {
+			compatible = "ambiq,iom";
 			reg = <0x50006000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <8 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
-			zephyr,pm-device-runtime-auto;
+
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		i2c3: i2c@50007000 {
+		iom3: iom@50007000 {
+			compatible = "ambiq,iom";
 			reg = <0x50007000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <9 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
-			zephyr,pm-device-runtime-auto;
+
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		i2c4: i2c@50008000 {
+		iom4: iom@50008000 {
+			compatible = "ambiq,iom";
 			reg = <0x50008000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <10 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
-			zephyr,pm-device-runtime-auto;
+
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		i2c5: i2c@50009000 {
+		iom5: iom@50009000 {
+			compatible = "ambiq,iom";
 			reg = <0x50009000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <11 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
-			zephyr,pm-device-runtime-auto;
+
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
 		adc0: adc@50010000 {
+			compatible = "ambiq,adc";
 			reg = <0x50010000 0x400>;
 			interrupts = <18 0>;
 			interrupt-names = "ADC";
@@ -336,7 +334,6 @@
 			internal-vref-mv = <1500>;
 			status = "disabled";
 			#io-channel-cells = <1>;
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x200>;
 		};
 
 		mspi0: spi@40020000 {
@@ -346,7 +343,6 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x800>;
 		};
 
 		rtc0: rtc@40004240 {
@@ -364,7 +360,6 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x8000>;
 
 			bt_hci_apollo: bt-hci@0 {
 				compatible = "ambiq,bt-hci-spi";
diff --git a/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi b/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi
index 9679e878741..b259207e45b 100644
--- a/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi
+++ b/dts/arm/ambiq/ambiq_apollo3p_blue.dtsi
@@ -108,12 +108,6 @@
 			};
 		};
 
-		pwrcfg: pwrcfg@40021000 {
-			compatible = "ambiq,pwrctrl";
-			reg = <0x40021000 0x400>;
-			#pwrcfg-cells = <2>;
-		};
-
 		stimer0: stimer@40008140 {
 			compatible = "ambiq,stimer";
 			reg = <0x40008140 0x80>;
@@ -200,7 +194,6 @@
 			interrupt-names = "UART0";
 			status = "disabled";
 			clocks = <&uartclk>;
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x80>;
 			zephyr,pm-device-runtime-auto;
 		};
 
@@ -211,7 +204,6 @@
 			interrupt-names = "UART1";
 			status = "disabled";
 			clocks = <&uartclk>;
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x100>;
 			zephyr,pm-device-runtime-auto;
 		};
 
@@ -222,131 +214,137 @@
 			#size-cells = <0>;
 			interrupts = <4 0>;
 			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0>;
 			zephyr,pm-device-runtime-auto;
 		};
 
-		spi0: spi@50004000 {
+		iom0: iom@50004000 {
+			compatible = "ambiq,iom";
 			reg = <0x50004000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <6 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
-			zephyr,pm-device-runtime-auto;
-		};
-
-		spi1: spi@50005000 {
-			reg = <0x50005000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <7 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
-			zephyr,pm-device-runtime-auto;
-		};
 
-		spi2: spi@50006000 {
-			reg = <0x50006000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <8 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
-			zephyr,pm-device-runtime-auto;
-		};
-
-		spi3: spi@50007000 {
-			reg = <0x50007000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <9 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
-			zephyr,pm-device-runtime-auto;
-		};
-
-		spi4: spi@50008000 {
-			reg = <0x50008000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <10 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
-			zephyr,pm-device-runtime-auto;
-		};
-
-		spi5: spi@50009000 {
-			reg = <0x50009000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <11 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
-			zephyr,pm-device-runtime-auto;
-		};
-
-		i2c0: i2c@50004000 {
-			reg = <0x50004000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <6 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x2>;
-			zephyr,pm-device-runtime-auto;
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		i2c1: i2c@50005000 {
+		iom1: iom@50005000 {
+			compatible = "ambiq,iom";
 			reg = <0x50005000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <7 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x4>;
-			zephyr,pm-device-runtime-auto;
+
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		i2c2: i2c@50006000 {
+		iom2: iom@50006000 {
+			compatible = "ambiq,iom";
 			reg = <0x50006000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <8 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x8>;
-			zephyr,pm-device-runtime-auto;
+
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		i2c3: i2c@50007000 {
+		iom3: iom@50007000 {
+			compatible = "ambiq,iom";
 			reg = <0x50007000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <9 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x10>;
-			zephyr,pm-device-runtime-auto;
+
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		i2c4: i2c@50008000 {
+		iom4: iom@50008000 {
+			compatible = "ambiq,iom";
 			reg = <0x50008000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <10 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x20>;
-			zephyr,pm-device-runtime-auto;
+
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		i2c5: i2c@50009000 {
+		iom5: iom@50009000 {
+			compatible = "ambiq,iom";
 			reg = <0x50009000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <11 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x40>;
-			zephyr,pm-device-runtime-auto;
+
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
 		adc0: adc@50010000 {
+			compatible = "ambiq,adc";
 			reg = <0x50010000 0x400>;
 			interrupts = <18 0>;
 			interrupt-names = "ADC";
@@ -354,7 +352,6 @@
 			internal-vref-mv = <1500>;
 			status = "disabled";
 			#io-channel-cells = <1>;
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x200>;
 		};
 
 		mspi0: mspi@50014000 {
@@ -365,7 +362,6 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x800>;
 		};
 
 		mspi1: mspi@50015000 {
@@ -376,7 +372,6 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x1000>;
 		};
 
 		mspi2: mspi@50016000 {
@@ -387,7 +382,6 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x2000>;
 		};
 
 		rtc0: rtc@40004240 {
@@ -405,7 +399,6 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x8 0x8000>;
 
 			bt_hci_apollo: bt-hci@0 {
 				compatible = "ambiq,bt-hci-spi";
diff --git a/dts/arm/ambiq/ambiq_apollo4p.dtsi b/dts/arm/ambiq/ambiq_apollo4p.dtsi
index c5641cfd352..bdc376f1808 100644
--- a/dts/arm/ambiq/ambiq_apollo4p.dtsi
+++ b/dts/arm/ambiq/ambiq_apollo4p.dtsi
@@ -92,12 +92,6 @@
 			};
 		};
 
-		pwrcfg: pwrcfg@40021000 {
-			compatible = "ambiq,pwrctrl";
-			reg = <0x40021000 0x400>;
-			#pwrcfg-cells = <2>;
-		};
-
 		stimer0: stimer@40008800 {
 			compatible = "ambiq,stimer";
 			reg = <0x40008800 0x80>;
@@ -121,8 +115,8 @@
 			interrupt-names = "UART0";
 			status = "disabled";
 			clocks = <&uartclk>;
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
 		};
+
 		uart1: uart@4001d000 {
 			compatible = "ambiq,uart", "arm,pl011";
 			reg = <0x4001d000 0x1000>;
@@ -130,7 +124,6 @@
 			interrupt-names = "UART1";
 			status = "disabled";
 			clocks = <&uartclk>;
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
 		};
 
 		uart2: uart@4001e000 {
@@ -140,7 +133,6 @@
 			interrupt-names = "UART2";
 			status = "disabled";
 			clocks = <&uartclk>;
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
 		};
 
 		uart3: uart@4001f000 {
@@ -150,154 +142,178 @@
 			interrupt-names = "UART3";
 			status = "disabled";
 			clocks = <&uartclk>;
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
 		};
 
-		iom0_spi: spi@40050000 {
+		iom0: iom@40050000 {
+			compatible = "ambiq,iom";
 			reg = <0x40050000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <6 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
-		};
 
-		iom0_i2c: i2c@40050000 {
-			reg = <0x40050000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <6 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		iom1_spi: spi@40051000 {
+		iom1: iom@40051000 {
+			compatible = "ambiq,iom";
 			reg = <0x40051000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <7 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
-		};
 
-		iom1_i2c: i2c@40051000 {
-			reg = <0x40051000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <7 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		iom2_spi: spi@40052000 {
+		iom2: iom@40052000 {
+			compatible = "ambiq,iom";
 			reg = <0x40052000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <8 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
-		};
 
-		iom2_i2c: i2c@40052000 {
-			reg = <0x40052000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <8 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		iom3_spi: spi@40053000 {
+		iom3: iom@40053000 {
+			compatible = "ambiq,iom";
 			reg = <0x40053000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <9 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
-		};
 
-		iom3_i2c: i2c@40053000 {
-			reg = <0x40053000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <9 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		iom4_spi: spi@40054000 {
+		iom4: iom@40054000 {
+			compatible = "ambiq,iom";
 			reg = <0x40054000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <10 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
-		};
 
-		iom4_i2c: i2c@40054000 {
-			reg = <0x40054000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <10 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		iom5_spi: spi@40055000 {
+		iom5: iom@40055000 {
+			compatible = "ambiq,iom";
 			reg = <0x40055000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <11 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
-		};
 
-		iom5_i2c: i2c@40055000 {
-			reg = <0x40055000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <11 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		iom6_spi: spi@40056000 {
+		iom6: iom@40056000 {
+			compatible = "ambiq,iom";
 			reg = <0x40056000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <12 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
-		};
 
-		iom6_i2c: i2c@40056000 {
-			reg = <0x40056000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <12 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		iom7_spi: spi@40057000 {
+		iom7: iom@40057000 {
+			compatible = "ambiq,iom";
 			reg = <0x40057000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <13 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
-		};
 
-		iom7_i2c: i2c@40057000 {
-			reg = <0x40057000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <13 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
 		adc0: adc@40038000 {
+			compatible = "ambiq,adc";
 			reg = <0x40038000 0x400>;
 			interrupts = <19 0>;
 			interrupt-names = "ADC";
@@ -305,7 +321,6 @@
 			internal-vref-mv = <1190>;
 			status = "disabled";
 			#io-channel-cells = <1>;
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x2000>;
 		};
 
 		mspi0: spi@40060000 {
@@ -315,7 +330,6 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x4000>;
 		};
 
 		mspi1: spi@40061000 {
@@ -325,7 +339,6 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x8000>;
 		};
 
 		mspi2: spi@40062000 {
@@ -335,7 +348,6 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x10000>;
 		};
 
 		rtc0: rtc@40004800 {
@@ -346,6 +358,17 @@
 			status = "disabled";
 		};
 
+		sdio0: sdio@40070000 {
+			compatible = "ambiq,sdio";
+			reg = <0x40070000 0x100>;
+			interrupts = <26 0>;
+			max-bus-freq = <96000000>;
+			min-bus-freq = <375000>;
+			power-delay-ms = <50>;
+			status = "disabled";
+			zephyr,pm-device-runtime-auto;
+		};
+
 		usb: usb@400b0000 {
 			compatible = "ambiq,usb";
 			reg = <0x400B0000 0x4100>;
@@ -353,7 +376,6 @@
 			num-bidir-endpoints = <6>;
 			maximum-speed = "full-speed";
 			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x400000>;
 		};
 
 		pinctrl: pin-controller@40010000 {
diff --git a/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi b/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi
index 421e0dcb587..677638ab8c3 100644
--- a/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi
+++ b/dts/arm/ambiq/ambiq_apollo4p_blue.dtsi
@@ -73,12 +73,6 @@
 			};
 		};
 
-		pwrcfg: pwrcfg@40021000 {
-			compatible = "ambiq,pwrctrl";
-			reg = <0x40021000 0x400>;
-			#pwrcfg-cells = <2>;
-		};
-
 		stimer0: stimer@40008800 {
 			compatible = "ambiq,stimer";
 			reg = <0x40008800 0x80>;
@@ -102,7 +96,6 @@
 			interrupt-names = "UART0";
 			status = "disabled";
 			clocks = <&uartclk>;
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
 		};
 		uart1: uart@4001d000 {
 			compatible = "ambiq,uart", "arm,pl011";
@@ -111,7 +104,6 @@
 			interrupt-names = "UART1";
 			status = "disabled";
 			clocks = <&uartclk>;
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
 		};
 
 		uart2: uart@4001e000 {
@@ -121,7 +113,6 @@
 			interrupt-names = "UART2";
 			status = "disabled";
 			clocks = <&uartclk>;
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
 		};
 
 		uart3: uart@4001f000 {
@@ -131,164 +122,178 @@
 			interrupt-names = "UART3";
 			status = "disabled";
 			clocks = <&uartclk>;
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
 		};
 
-		spi0: spi@40050000 {
+		iom0: iom@40050000 {
+			compatible = "ambiq,iom";
 			reg = <0x40050000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <6 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
-		};
-
-		spi1: spi@40051000 {
-			reg = <0x40051000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <7 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
-		};
 
-		spi2: spi@40052000 {
-			reg = <0x40052000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <8 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
-		};
-
-		spi3: spi@40053000 {
-			reg = <0x40053000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <9 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
-		};
-
-		spi4: spi@40054000 {
-			/* IOM4 works as SPI and is wired internally for BLE HCI. */
-			compatible = "ambiq,spi";
-			reg = <0x40054000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <10 0>;
-			cs-gpios = <&gpio32_63 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
-			clock-frequency = <DT_FREQ_M(24)>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
-
-			bt_hci_apollo: bt-hci@0 {
-				compatible = "ambiq,bt-hci-spi";
-				reg = <0>;
-				spi-max-frequency = <DT_FREQ_M(24)>;
-				irq-gpios = <&gpio32_63 21 GPIO_ACTIVE_HIGH>;
-				reset-gpios = <&gpio32_63 23 GPIO_ACTIVE_LOW>;
-				clkreq-gpios = <&gpio32_63 20 GPIO_ACTIVE_HIGH>;
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
 			};
 		};
 
-		spi5: spi@40055000 {
-			reg = <0x40055000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <11 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
-		};
-
-		spi6: spi@40056000 {
-			reg = <0x40056000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <12 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
-		};
-
-		spi7: spi@40057000 {
-			reg = <0x40057000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <13 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
-		};
-
-		i2c0: i2c@40050000 {
-			reg = <0x40050000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			interrupts = <6 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x2>;
-		};
-
-		i2c1: i2c@40051000 {
+		iom1: iom@40051000 {
+			compatible = "ambiq,iom";
 			reg = <0x40051000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <7 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x4>;
+
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		i2c2: i2c@40052000 {
+		iom2: iom@40052000 {
+			compatible = "ambiq,iom";
 			reg = <0x40052000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <8 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x8>;
+
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		i2c3: i2c@40053000 {
+		iom3: iom@40053000 {
+			compatible = "ambiq,iom";
 			reg = <0x40053000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <9 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x10>;
+
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		i2c4: i2c@40054000 {
+		iom4: iom@40054000 {
+			compatible = "ambiq,iom";
 			reg = <0x40054000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <10 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x20>;
+			/* IOM4 works as SPI and is wired internally for BLE HCI. */
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				cs-gpios = <&gpio32_63 22 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
+				clock-frequency = <DT_FREQ_M(24)>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+
+				bt_hci_apollo: bt-hci@0 {
+					compatible = "ambiq,bt-hci-spi";
+					reg = <0>;
+					spi-max-frequency = <DT_FREQ_M(24)>;
+					irq-gpios = <&gpio32_63 21 GPIO_ACTIVE_HIGH>;
+					reset-gpios = <&gpio32_63 23 GPIO_ACTIVE_LOW>;
+					clkreq-gpios = <&gpio32_63 20 GPIO_ACTIVE_HIGH>;
+				};
+			};
 		};
 
-		i2c5: i2c@40055000 {
+		iom5: iom@40055000 {
+			compatible = "ambiq,iom";
 			reg = <0x40055000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <11 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x40>;
+
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		i2c6: i2c@40056000 {
+		iom6: iom@40056000 {
+			compatible = "ambiq,iom";
 			reg = <0x40056000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <12 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x80>;
+
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
-		i2c7: i2c@40057000 {
+		iom7: iom@40057000 {
+			compatible = "ambiq,iom";
 			reg = <0x40057000 0x1000>;
-			#address-cells = <1>;
-			#size-cells = <0>;
 			interrupts = <13 0>;
-			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x100>;
+
+			spi {
+				compatible = "ambiq,spi";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
+			i2c {
+				compatible = "ambiq,i2c";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+				zephyr,pm-device-runtime-auto;
+			};
 		};
 
 		mspi0: spi@40060000 {
@@ -298,7 +303,6 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x4000>;
 		};
 
 		mspi1: spi@40061000 {
@@ -308,7 +312,6 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x8000>;
 		};
 
 		mspi2: spi@40062000 {
@@ -318,7 +321,6 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x10000>;
 		};
 
 		usb: usb@400b0000 {
@@ -328,7 +330,6 @@
 			num-bidir-endpoints = <6>;
 			maximum-speed = "full-speed";
 			status = "disabled";
-			ambiq,pwrcfg = <&pwrcfg 0x4 0x400000>;
 		};
 
 		rtc0: rtc@40004800 {
diff --git a/dts/arm/ambiq/ambiq_apollo510.dtsi b/dts/arm/ambiq/ambiq_apollo510.dtsi
new file mode 100644
index 00000000000..6cbbbb22921
--- /dev/null
+++ b/dts/arm/ambiq/ambiq_apollo510.dtsi
@@ -0,0 +1,266 @@
+/* Copyright (c) 2025 Ambiq Micro Inc. */
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <arm/armv8.1-m.dtsi>
+#include <mem.h>
+#include <freq.h>
+#include <apollo510/am_apollo510.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	clocks {
+		uartclk: apb-pclk {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(24)>;
+			#clock-cells = <0>;
+		};
+
+		xo32m_xtal: xo32m_xtal {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(32)>;
+			#clock-cells = <0>;
+		};
+
+		xo32m_ext: xo32m_ext {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(32)>;
+			#clock-cells = <0>;
+		};
+
+		xo32k_xtal: xo32k_xtal {
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+		};
+
+		xo32k_ext: xo32k_ext {
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+		};
+
+		extrefclk: extrefclk {
+			compatible = "fixed-clock";
+			clock-frequency = <0>;
+			#clock-cells = <0>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m55";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			cpu-power-states = <&idle &suspend_to_ram>;
+
+			itm: itm@e0000000 {
+				compatible = "arm,armv8m-itm";
+				reg = <0xe0000000 0x1000>;
+				swo-ref-frequency = <DT_FREQ_M(48)>;
+			};
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8m.1-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+
+		power-states {
+			idle: idle {
+				compatible = "zephyr,power-state";
+				power-state-name = "suspend-to-idle";
+				min-residency-us = <2000>;
+				exit-latency-us = <5>;
+			};
+
+			suspend_to_ram: suspend_to_ram {
+				compatible = "zephyr,power-state";
+				power-state-name = "suspend-to-ram";
+				min-residency-us = <5000>;
+				exit-latency-us = <125>;
+			};
+		};
+	};
+
+	/* MRAM region */
+	flash0: flash@MRAM_BASE_NAME {
+		compatible = "soc-nv-flash";
+		reg = <MRAM_BASE_ADDR MRAM_MAX_SIZE>;
+	};
+
+	/* TCM */
+	itcm: itcm@ITCM_BASE_NAME {
+		compatible = "zephyr,memory-region";
+		reg = <ITCM_BASE_ADDR ITCM_MAX_SIZE>;
+		zephyr,memory-region = "ITCM";
+	};
+
+	dtcm: dtcm@DTCM_BASE_NAME {
+		compatible = "zephyr,memory-region";
+		reg = <DTCM_BASE_ADDR DTCM_MAX_SIZE>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	/* SRAM */
+	sram: memory@SSRAM_BASE_NAME {
+		compatible = "mmio-sram";
+		reg = <SSRAM_BASE_ADDR SSRAM_MAX_SIZE>;
+	};
+
+	soc {
+		compatible = "ambiq,apollo510", "ambiq,apollo5x", "simple-bus";
+
+		stimer0: stimer@STIMER_BASE_NAME {
+			compatible = "ambiq,stimer";
+			reg = <STIMER_REG_BASE STIMER_REG_SIZE>;
+			interrupts = <32 0>;
+			status = "okay";
+		};
+
+		wdt0: watchdog@WDT_BASE_NAME {
+			compatible = "ambiq,watchdog";
+			reg = <WDT_REG_BASE WDT_REG_SIZE>;
+			interrupts = <1 0>;
+			clock-frequency = <16>;
+			status = "disabled";
+		};
+
+		uart0: uart@UART0_BASE_NAME {
+			compatible = "ambiq,uart", "arm,pl011";
+			reg = <UART0_REG_BASE UART0_REG_SIZE>;
+			interrupts = <15 0>;
+			interrupt-names = "UART0";
+			status = "disabled";
+			clocks = <&uartclk>;
+		};
+
+		uart1: uart@UART1_BASE_NAME {
+			compatible = "ambiq,uart", "arm,pl011";
+			reg = <UART1_REG_BASE UART1_REG_SIZE>;
+			interrupts = <16 0>;
+			interrupt-names = "UART1";
+			status = "disabled";
+			clocks = <&uartclk>;
+		};
+
+		uart2: uart@UART2_BASE_NAME {
+			compatible = "ambiq,uart", "arm,pl011";
+			reg = <UART2_REG_BASE UART2_REG_SIZE>;
+			interrupts = <17 0>;
+			interrupt-names = "UART2";
+			status = "disabled";
+			clocks = <&uartclk>;
+		};
+
+		uart3: uart@UART3_BASE_NAME {
+			compatible = "ambiq,uart", "arm,pl011";
+			reg = <UART3_REG_BASE UART3_REG_SIZE>;
+			interrupts = <18 0>;
+			interrupt-names = "UART3";
+			status = "disabled";
+			clocks = <&uartclk>;
+		};
+
+		pinctrl: pin-controller@GPIO_BASE_NAME {
+			compatible = "ambiq,apollo5-pinctrl";
+			reg = <GPIO_REG_BASE GPIO_REG_SIZE>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio: gpio@GPIO_BASE_NAME {
+				compatible = "ambiq,gpio";
+				gpio-map-mask = <0xffffffe0 0xffffffc0>;
+				gpio-map-pass-thru = <0x1f 0x3f>;
+				gpio-map = <
+					0x00 0x0 &gpio0_31 0x0 0x0
+					0x20 0x0 &gpio32_63 0x0 0x0
+					0x40 0x0 &gpio64_95 0x0 0x0
+					0x60 0x0 &gpio96_127 0x0 0x0
+					0x80 0x0 &gpio128_159 0x0 0x0
+					0xA0 0x0 &gpio160_191 0x0 0x0
+					0xC0 0x0 &gpio192_223 0x0 0x0
+				>;
+				reg = <GPIO_REG_BASE>;
+				#gpio-cells = <2>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				ranges;
+
+				gpio0_31: gpio0_31@0 {
+					compatible = "ambiq,gpio-bank";
+					gpio-controller;
+					#gpio-cells = <2>;
+					reg = <0>;
+					interrupts = <56 0>;
+					status = "disabled";
+				};
+
+				gpio32_63: gpio32_63@80 {
+					compatible = "ambiq,gpio-bank";
+					gpio-controller;
+					#gpio-cells = <2>;
+					reg = <0x80>;
+					interrupts = <57 0>;
+					status = "disabled";
+				};
+
+				gpio64_95: gpio64_95@100 {
+					compatible = "ambiq,gpio-bank";
+					gpio-controller;
+					#gpio-cells = <2>;
+					reg = <0x100>;
+					interrupts = <58 0>;
+					status = "disabled";
+				};
+
+				gpio96_127: gpio96_127@180 {
+					compatible = "ambiq,gpio-bank";
+					gpio-controller;
+					#gpio-cells = <2>;
+					reg = <0x180>;
+					interrupts = <59 0>;
+					status = "disabled";
+				};
+
+				gpio128_159: gpio128_159@200 {
+					compatible = "ambiq,gpio-bank";
+					gpio-controller;
+					#gpio-cells = <2>;
+					reg = <0x200>;
+					interrupts = <60 0>;
+					status = "disabled";
+				};
+
+				gpio160_191: gpio160_191@280 {
+					compatible = "ambiq,gpio-bank";
+					gpio-controller;
+					#gpio-cells = <2>;
+					reg = <0x280>;
+					interrupts = <61 0>;
+					status = "disabled";
+				};
+
+				gpio192_223: gpio192_223@300 {
+					compatible = "ambiq,gpio-bank";
+					gpio-controller;
+					#gpio-cells = <2>;
+					reg = <0x300>;
+					interrupts = <62 0>;
+					status = "disabled";
+				};
+			};
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/antmicro/myra.dtsi b/dts/arm/antmicro/myra.dtsi
new file mode 100644
index 00000000000..b47778ed4b4
--- /dev/null
+++ b/dts/arm/antmicro/myra.dtsi
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/g4/stm32g491Xe.dtsi>
+#include <st/g4/stm32g491r(c-e)tx-pinctrl.dtsi>
+#include <mem.h>
+#include <freq.h>
+
+&spi2 {
+	pinctrl-0 = <&spi2_nss_pb12 &spi2_sck_pb13
+		     &spi2_miso_pb14 &spi2_mosi_pb15>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	mb85rs1mt: mb85rs1mt@0 {
+		status = "okay";
+		compatible = "fujitsu,mb85rsxx";
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_M(25)>;
+		size = <DT_SIZE_K(128)>;
+	};
+};
diff --git a/dts/arm/atmel/dma_atmel_same70.h b/dts/arm/atmel/dma_atmel_same70.h
deleted file mode 100644
index debe04256d1..00000000000
--- a/dts/arm/atmel/dma_atmel_same70.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright (c) 2020 Linaro Limited
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef DMA_ATMEL_SAME70_H_
-#define DMA_ATMEL_SAME70_H_
-
-/** Peripheral Hardware Request Line Identifier */
-#define DMA_PERID_HSMCI_TX_RX 0
-#define DMA_PERID_SPI0_TX     1
-#define DMA_PERID_SPI0_RX     2
-#define DMA_PERID_SPI1_TX     3
-#define DMA_PERID_SPI1_RX     4
-#define DMA_PERID_QSPI_TX     5
-#define DMA_PERID_QSPI_RX     6
-#define DMA_PERID_USART0_TX   7
-#define DMA_PERID_USART0_RX   8
-#define DMA_PERID_USART1_TX   9
-#define DMA_PERID_USART1_RX   10
-#define DMA_PERID_USART2_TX   11
-#define DMA_PERID_USART2_RX   12
-#define DMA_PERID_PWM0_TX     13
-#define DMA_PERID_TWIHS0_TX   14
-#define DMA_PERID_TWIHS0_RX   15
-#define DMA_PERID_TWIHS1_TX   16
-#define DMA_PERID_TWIHS1_RX   17
-#define DMA_PERID_TWIHS2_TX   18
-#define DMA_PERID_TWIHS2_RX   19
-#define DMA_PERID_UART0_TX    20
-#define DMA_PERID_UART0_RX    21
-#define DMA_PERID_UART1_TX    22
-#define DMA_PERID_UART1_RX    23
-#define DMA_PERID_UART2_TX    24
-#define DMA_PERID_UART2_RX    25
-#define DMA_PERID_UART3_TX    26
-#define DMA_PERID_UART3_RX    27
-#define DMA_PERID_UART4_TX    28
-#define DMA_PERID_UART4_RX    29
-#define DMA_PERID_DACC_TX     30
-#define DMA_PERID_SSC_TX      32
-#define DMA_PERID_SSC_RX      33
-#define DMA_PERID_PIOA_RX     34
-#define DMA_PERID_AFEC0_RX    35
-#define DMA_PERID_AFEC1_RX    36
-#define DMA_PERID_AES_TX      37
-#define DMA_PERID_AES_RX      38
-#define DMA_PERID_PWM1_TX     39
-#define DMA_PERID_TC0_RX      40
-#define DMA_PERID_TC1_RX      41
-#define DMA_PERID_TC2_RX      42
-#define DMA_PERID_TC3_RX      43
-
-#endif /* DMA_ATMEL_SAME70_H_ */
diff --git a/dts/arm/atmel/dma_atmel_samv71.h b/dts/arm/atmel/dma_atmel_samv71.h
deleted file mode 100644
index af346081fa4..00000000000
--- a/dts/arm/atmel/dma_atmel_samv71.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * Copyright (c) 2020 Linaro Limited
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef DMA_ATMEL_SAMV71_H_
-#define DMA_ATMEL_SAMV71_H_
-
-/** Peripheral Hardware Request Line Identifier */
-#define DMA_PERID_HSMCI_TX_RX 0
-#define DMA_PERID_SPI0_TX     1
-#define DMA_PERID_SPI0_RX     2
-#define DMA_PERID_SPI1_TX     3
-#define DMA_PERID_SPI1_RX     4
-#define DMA_PERID_QSPI_TX     5
-#define DMA_PERID_QSPI_RX     6
-#define DMA_PERID_USART0_TX   7
-#define DMA_PERID_USART0_RX   8
-#define DMA_PERID_USART1_TX   9
-#define DMA_PERID_USART1_RX   10
-#define DMA_PERID_USART2_TX   11
-#define DMA_PERID_USART2_RX   12
-#define DMA_PERID_PWM0_TX     13
-#define DMA_PERID_TWIHS0_TX   14
-#define DMA_PERID_TWIHS0_RX   15
-#define DMA_PERID_TWIHS1_TX   16
-#define DMA_PERID_TWIHS1_RX   17
-#define DMA_PERID_TWIHS2_TX   18
-#define DMA_PERID_TWIHS2_RX   19
-#define DMA_PERID_UART0_TX    20
-#define DMA_PERID_UART0_RX    21
-#define DMA_PERID_UART1_TX    22
-#define DMA_PERID_UART1_RX    23
-#define DMA_PERID_UART2_TX    24
-#define DMA_PERID_UART2_RX    25
-#define DMA_PERID_UART3_TX    26
-#define DMA_PERID_UART3_RX    27
-#define DMA_PERID_UART4_TX    28
-#define DMA_PERID_UART4_RX    29
-#define DMA_PERID_DACC0_TX    30
-#define DMA_PERID_DACC1_TX    31
-#define DMA_PERID_SSC_TX      32
-#define DMA_PERID_SSC_RX      33
-#define DMA_PERID_PIOA_RX     34
-#define DMA_PERID_AFEC0_RX    35
-#define DMA_PERID_AFEC1_RX    36
-#define DMA_PERID_AES_TX      37
-#define DMA_PERID_AES_RX      38
-#define DMA_PERID_PWM1_TX     39
-#define DMA_PERID_TC0_RX      40
-#define DMA_PERID_TC3_RX      41
-#define DMA_PERID_TC6_RX      42
-#define DMA_PERID_TC9_RX      43
-#define DMA_PERID_I2SC0_TX_L  44
-#define DMA_PERID_I2SC0_RX_L  45
-#define DMA_PERID_I2SC1_TX_L  46
-#define DMA_PERID_I2SC1_RX_L  47
-#define DMA_PERID_I2SC0_TX_R  48
-#define DMA_PERID_I2SC0_RX_R  49
-#define DMA_PERID_I2SC1_TX_R  50
-#define DMA_PERID_I2SC1_RX_R  51
-
-#endif /* DMA_ATMEL_SAMV71_H_ */
diff --git a/dts/arm/atmel/sam3x.dtsi b/dts/arm/atmel/sam3x.dtsi
index 67d99418fd2..981b5548da3 100644
--- a/dts/arm/atmel/sam3x.dtsi
+++ b/dts/arm/atmel/sam3x.dtsi
@@ -5,7 +5,9 @@
  */
 
 #include <arm/armv7-m.dtsi>
+#include <zephyr/dt-bindings/adc/adc.h>
 #include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
 #include <zephyr/dt-bindings/clock/atmel_sam_pmc.h>
 
 / {
@@ -49,6 +51,26 @@
 			reg = <0x20070000 0x18000>;
 		};
 
+		spi0: spi@40008000 {
+			compatible = "atmel,sam-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40008000 0x4000>;
+			interrupts = <24 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
+			status = "disabled";
+		};
+
+		spi1: spi@4000c000 {
+			compatible = "atmel,sam-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x4000c000 0x4000>;
+			interrupts = <25 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
+			status = "disabled";
+		};
+
 		/* Only used for HWINFO device ID */
 		eefc: flash-controller@400e0a00 {
 			compatible = "atmel,sam-flash-controller";
@@ -237,6 +259,17 @@
 			status = "disabled";
 		};
 
+		adc0: adc@400c0000 {
+			compatible = "atmel,sam-adc";
+			reg = <0x400c0000 0x4000>;
+			interrupts = <37 1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#io-channel-cells = <1>;
+			status = "disabled";
+		};
+
 		pwm0: pwm@40094000 {
 			compatible = "atmel,sam-pwm";
 			reg = <0x40094000 0x4000>;
diff --git a/dts/arm/atmel/sam4l.dtsi b/dts/arm/atmel/sam4l.dtsi
index 7f19f8d21a4..a15dc81d39c 100644
--- a/dts/arm/atmel/sam4l.dtsi
+++ b/dts/arm/atmel/sam4l.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
+ * Copyright (c) 2020-2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,6 +10,10 @@
 #include <zephyr/dt-bindings/clock/atmel_sam_pmc.h>
 
 / {
+	aliases {
+		watchdog0 = &wdt;
+	};
+
 	chosen {
 		zephyr,flash-controller = &flashcalw;
 		zephyr,entropy = &trng;
@@ -237,6 +241,14 @@
 			reg = <0x80020c 0xf>;
 			status = "okay";
 		};
+
+		wdt: watchdog@400f0c00 {
+			compatible = "atmel,sam4l-watchdog";
+			reg = <0x400f0c00 0x400>;
+			interrupts = <44 1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 99>;
+			status = "okay";
+		};
 	};
 };
 
diff --git a/dts/arm/atmel/sam4s.dtsi b/dts/arm/atmel/sam4s.dtsi
index 64828f3a7d5..3e2dcb21726 100644
--- a/dts/arm/atmel/sam4s.dtsi
+++ b/dts/arm/atmel/sam4s.dtsi
@@ -55,7 +55,7 @@
 			status = "okay";
 		};
 
-		sram0: memory@20100000 {
+		sram0: memory@20000000 {
 			compatible = "mmio-sram";
 		};
 
@@ -232,6 +232,15 @@
 			status = "disabled";
 		};
 
+		dacc: dacc@4003c000 {
+			compatible = "atmel,sam-dac";
+			reg = <0x4003c000 0x4000>;
+			interrupts = <30 1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
 		rstc: rstc@400e1400 {
 			compatible = "atmel,sam-rstc";
 			reg = <0x400e1400 0x10>;
diff --git a/dts/arm/atmel/sam4s16b.dtsi b/dts/arm/atmel/sam4s16b.dtsi
index f671f6fccc4..ca158cfd915 100644
--- a/dts/arm/atmel/sam4s16b.dtsi
+++ b/dts/arm/atmel/sam4s16b.dtsi
@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(128)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(128)>;
 		};
 	};
 };
diff --git a/dts/arm/atmel/sam4s16c.dtsi b/dts/arm/atmel/sam4s16c.dtsi
index f671f6fccc4..ca158cfd915 100644
--- a/dts/arm/atmel/sam4s16c.dtsi
+++ b/dts/arm/atmel/sam4s16c.dtsi
@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(128)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(128)>;
 		};
 	};
 };
diff --git a/dts/arm/atmel/sam4s2a.dtsi b/dts/arm/atmel/sam4s2a.dtsi
index b57ddb0cec6..3855a903a45 100644
--- a/dts/arm/atmel/sam4s2a.dtsi
+++ b/dts/arm/atmel/sam4s2a.dtsi
@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(64)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(64)>;
 		};
 	};
 };
diff --git a/dts/arm/atmel/sam4s2b.dtsi b/dts/arm/atmel/sam4s2b.dtsi
index b57ddb0cec6..3855a903a45 100644
--- a/dts/arm/atmel/sam4s2b.dtsi
+++ b/dts/arm/atmel/sam4s2b.dtsi
@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(64)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(64)>;
 		};
 	};
 };
diff --git a/dts/arm/atmel/sam4s2c.dtsi b/dts/arm/atmel/sam4s2c.dtsi
index b57ddb0cec6..3855a903a45 100644
--- a/dts/arm/atmel/sam4s2c.dtsi
+++ b/dts/arm/atmel/sam4s2c.dtsi
@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(64)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(64)>;
 		};
 	};
 };
diff --git a/dts/arm/atmel/sam4s4a.dtsi b/dts/arm/atmel/sam4s4a.dtsi
index 1ea079b054c..16d6a850f83 100644
--- a/dts/arm/atmel/sam4s4a.dtsi
+++ b/dts/arm/atmel/sam4s4a.dtsi
@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(64)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(64)>;
 		};
 	};
 };
diff --git a/dts/arm/atmel/sam4s4b.dtsi b/dts/arm/atmel/sam4s4b.dtsi
index 959c4d591e2..b265de356ea 100644
--- a/dts/arm/atmel/sam4s4b.dtsi
+++ b/dts/arm/atmel/sam4s4b.dtsi
@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(64)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(64)>;
 		};
 	};
 };
diff --git a/dts/arm/atmel/sam4s4c.dtsi b/dts/arm/atmel/sam4s4c.dtsi
index 1ea079b054c..16d6a850f83 100644
--- a/dts/arm/atmel/sam4s4c.dtsi
+++ b/dts/arm/atmel/sam4s4c.dtsi
@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(64)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(64)>;
 		};
 	};
 };
diff --git a/dts/arm/atmel/sam4s8b.dtsi b/dts/arm/atmel/sam4s8b.dtsi
index 2e00a78b4d6..44f37602009 100644
--- a/dts/arm/atmel/sam4s8b.dtsi
+++ b/dts/arm/atmel/sam4s8b.dtsi
@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(128)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(128)>;
 		};
 	};
 };
diff --git a/dts/arm/atmel/sam4s8c.dtsi b/dts/arm/atmel/sam4s8c.dtsi
index 2e00a78b4d6..44f37602009 100644
--- a/dts/arm/atmel/sam4s8c.dtsi
+++ b/dts/arm/atmel/sam4s8c.dtsi
@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(128)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(128)>;
 		};
 	};
 };
diff --git a/dts/arm/atmel/sam4sa16c.dtsi b/dts/arm/atmel/sam4sa16c.dtsi
index 789e482b0f6..a413672ba1b 100644
--- a/dts/arm/atmel/sam4sa16c.dtsi
+++ b/dts/arm/atmel/sam4sa16c.dtsi
@@ -16,8 +16,8 @@
 			};
 		};
 
-		sram0: memory@20100000 {
-			reg = <0x20100000 DT_SIZE_K(160)>;
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(160)>;
 		};
 	};
 };
diff --git a/dts/arm/atmel/samc21.dtsi b/dts/arm/atmel/samc21.dtsi
index f54b5672e75..0e91f58e341 100644
--- a/dts/arm/atmel/samc21.dtsi
+++ b/dts/arm/atmel/samc21.dtsi
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2022 Kamil Serwus
+ * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,11 +23,12 @@
 			interrupt-names = "resrdy";
 			clocks = <&gclk 34>, <&mclk 0x1c 18>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			#io-channel-cells = <1>;
 
-			gclk = <0>;
 			prescaler = <4>;
 		};
 
@@ -36,6 +38,8 @@
 			interrupts = <13 0>;
 			clocks = <&gclk 23>, <&mclk 0x1c 5>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -45,6 +49,8 @@
 			interrupts = <14 0>;
 			clocks = <&gclk 25>, <&mclk 0x1c 6>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -55,6 +61,8 @@
 			interrupt-names = "int0";
 			clocks = <&gclk 26>, <&mclk 0x10 8>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
@@ -68,6 +76,8 @@
 			interrupt-names = "int0";
 			clocks = <&gclk 27>, <&mclk 0x10 9>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
diff --git a/dts/arm/atmel/samc2x.dtsi b/dts/arm/atmel/samc2x.dtsi
index a1a78112487..d6ba356b3de 100644
--- a/dts/arm/atmel/samc2x.dtsi
+++ b/dts/arm/atmel/samc2x.dtsi
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2022 Kamil Serwus
+ * Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,6 +20,8 @@
 		port-b = &portb;
 		port-c = &portc;
 
+		rtc = &rtc;
+
 		sercom-0 = &sercom0;
 		sercom-1 = &sercom1;
 		sercom-2 = &sercom2;
@@ -64,7 +67,6 @@
 			compatible = "atmel,sam0-nvmctrl";
 			reg = <0x41004000 0x22>;
 			interrupts = <6 0>;
-
 			#address-cells = <1>;
 			#size-cells = <1>;
 
@@ -78,17 +80,25 @@
 		};
 
 		mclk: mclk@40000800 {
-			compatible = "atmel,samc2x-mclk";
+			compatible = "atmel,sam0-mclk";
 			reg = <0x40000800 0x400>;
 
 			#clock-cells = <2>;
 		};
 
+		osc32kctrl: osc32kctrl@40001400 {
+			compatible = "atmel,sam0-osc32kctrl";
+			reg = <0x40001400 0x400>;
+			#clock-cells = <0>;
+			#atmel,assigned-clock-cells = <1>;
+		};
+
 		gclk: gclk@40001c00 {
-			compatible = "atmel,samc2x-gclk";
+			compatible = "atmel,sam0-gclk";
 			reg = <0x40001c00 0x400>;
 
 			#clock-cells = <1>;
+			#atmel,assigned-clock-cells = <1>;
 		};
 
 		eic: eic@40002800 {
@@ -124,11 +134,12 @@
 			interrupt-names = "resrdy";
 			clocks = <&gclk 33>, <&mclk 0x1c 17>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			#io-channel-cells = <1>;
 
-			gclk = <0>;
 			prescaler = <4>;
 		};
 
@@ -138,6 +149,8 @@
 			interrupts = <9 0>;
 			clocks = <&gclk 19>, <&mclk 0x1c 1>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -147,6 +160,8 @@
 			interrupts = <10 0>;
 			clocks = <&gclk 20>, <&mclk 0x1c 2>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -156,6 +171,8 @@
 			interrupts = <11 0>;
 			clocks = <&gclk 21>, <&mclk 0x1c 3>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -165,6 +182,8 @@
 			interrupts = <12 0>;
 			clocks = <&gclk 22>, <&mclk 0x1c 4>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -174,6 +193,8 @@
 			interrupts = <17 0>;
 			clocks = <&gclk 28>, <&mclk 0x1c 9>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			channels = <4>;
@@ -186,6 +207,8 @@
 			interrupts = <18 0>;
 			clocks = <&gclk 28>, <&mclk 0x1c 10>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			channels = <4>;
@@ -198,6 +221,8 @@
 			interrupts = <19 0>;
 			clocks = <&gclk 29>, <&mclk 0x1c 11>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			channels = <2>;
@@ -244,11 +269,16 @@
 
 		rtc: rtc@40002400 {
 			compatible = "atmel,sam0-rtc";
-			reg = <0x40002400 0x1C>;
-			interrupts = <3 0>;
+			reg = <0x40002400 0x24>;
+			interrupts = <2 0>;
+			clocks = <&osc32kctrl>, <&mclk 0x14 9>;
+			clock-names = "OSC32KCTRL", "MCLK";
+			atmel,assigned-clocks = <&osc32kctrl 0>;
+			atmel,assigned-clock-names = "OSC32KCTRL";
 			status = "disabled";
 
-			clock-generator = <0>;
+			alarms-count = <1>;
+			cal-constant = <(4096 * 240)>;
 		};
 	};
 };
diff --git a/dts/arm/atmel/samd20.dtsi b/dts/arm/atmel/samd20.dtsi
index 8e367d9fd9a..26c16e36e2d 100644
--- a/dts/arm/atmel/samd20.dtsi
+++ b/dts/arm/atmel/samd20.dtsi
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018 Sean Nyekjaer
+ * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,6 +21,8 @@
 			interrupts = <13 0>;
 			clocks = <&gclk 0x13>, <&pm 0x20 8>;
 			clock-names = "GCLK", "PM";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -29,6 +32,8 @@
 			interrupts = <15 0>;
 			clocks = <&gclk 0x14>, <&pm 0x20 10>;
 			clock-names = "GCLK", "PM";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -38,6 +43,8 @@
 			interrupts = <19 0>;
 			clocks = <&gclk 0x16>, <&pm 0x20 14>;
 			clock-names = "GCLK", "PM";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 	};
@@ -47,48 +54,71 @@
 	interrupts = <23 0>;
 	clocks = <&gclk 26>, <&pm 0x20 18>;
 	clock-names = "GCLK", "PM";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
+};
+
+&rtc {
+	clocks = <&gclk 2>, <&pm 0x18 5>;
+	clock-names = "GCLK", "PM";
+	atmel,assigned-clocks = <&gclk 4>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &sercom0 {
 	interrupts = <7 0>;
 	clocks = <&gclk 0xd>, <&pm 0x20 2>;
 	clock-names = "GCLK", "PM";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &sercom1 {
 	interrupts = <8 0>;
 	clocks = <&gclk 0xe>, <&pm 0x20 3>;
 	clock-names = "GCLK", "PM";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &sercom2 {
 	interrupts = <9 0>;
 	clocks = <&gclk 0xf>, <&pm 0x20 4>;
 	clock-names = "GCLK", "PM";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &sercom3 {
 	interrupts = <10 0>;
 	clocks = <&gclk 0x10>, <&pm 0x20 5>;
 	clock-names = "GCLK", "PM";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &sercom4 {
 	interrupts = <11 0>;
 	clocks = <&gclk 0x11>, <&pm 0x20 6>;
 	clock-names = "GCLK", "PM";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &sercom5 {
 	interrupts = <12 0>;
 	clocks = <&gclk 0x12>, <&pm 0x20 7>;
 	clock-names = "GCLK", "PM";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &tc4 {
 	interrupts = <17 0>;
 	clocks = <&gclk 0x15>, <&pm 0x20 12>;
 	clock-names = "GCLK", "PM";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &adc {
@@ -96,4 +126,11 @@
 	interrupt-names = "resrdy";
 	clocks = <&gclk 0x17>, <&pm 0x20 16>;
 	clock-names = "GCLK", "PM";
+	/*
+	 * 2.1 MHz is ADC max clock
+	 * 8 MHz GCLK / 4 = 2 MHz
+	 * Generator 3: DFLL48M / 8MHz
+	 */
+	atmel,assigned-clocks = <&gclk 3>;
+	atmel,assigned-clock-names = "GCLK";
 };
diff --git a/dts/arm/atmel/samd21.dtsi b/dts/arm/atmel/samd21.dtsi
index c4692ffa9e5..790bfe007a6 100644
--- a/dts/arm/atmel/samd21.dtsi
+++ b/dts/arm/atmel/samd21.dtsi
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2017 Google LLC.
+ * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -40,6 +41,8 @@
 			interrupts = <21 0>;
 			clocks = <&gclk 0x1d>, <&pm 0x20 14>;
 			clock-names = "GCLK", "PM";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -49,6 +52,8 @@
 			interrupts = <15 0>;
 			clocks = <&gclk 26>, <&pm 0x20 8>;
 			clock-names = "GCLK", "PM";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			channels = <4>;
@@ -61,6 +66,8 @@
 			interrupts = <16 0>;
 			clocks = <&gclk 26>, <&pm 0x20 9>;
 			clock-names = "GCLK", "PM";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			channels = <2>;
@@ -73,6 +80,8 @@
 			interrupts = <17 0>;
 			clocks = <&gclk 27>, <&pm 0x20 10>;
 			clock-names = "GCLK", "PM";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			channels = <2>;
@@ -85,53 +94,83 @@
 	interrupts = <25 0>;
 	clocks = <&gclk 33>, <&pm 0x20 18>;
 	clock-names = "GCLK", "PM";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
+};
+
+&rtc {
+	clocks = <&gclk 4>, <&pm 0x18 5>;
+	clock-names = "GCLK", "PM";
+	atmel,assigned-clocks = <&gclk 4>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &sercom0 {
 	interrupts = <9 0>;
 	clocks = <&gclk 0x14>, <&pm 0x20 2>;
 	clock-names = "GCLK", "PM";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &sercom1 {
 	interrupts = <10 0>;
 	clocks = <&gclk 0x15>, <&pm 0x20 3>;
 	clock-names = "GCLK", "PM";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &sercom2 {
 	interrupts = <11 0>;
 	clocks = <&gclk 0x16>, <&pm 0x20 4>;
 	clock-names = "GCLK", "PM";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &sercom3 {
 	interrupts = <12 0>;
 	clocks = <&gclk 0x17>, <&pm 0x20 5>;
 	clock-names = "GCLK", "PM";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &sercom4 {
 	interrupts = <13 0>;
 	clocks = <&gclk 0x18>, <&pm 0x20 6>;
 	clock-names = "GCLK", "PM";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &sercom5 {
 	interrupts = <14 0>;
 	clocks = <&gclk 0x19>, <&pm 0x20 7>;
 	clock-names = "GCLK", "PM";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &tc4 {
 	interrupts = <19 0>;
 	clocks = <&gclk 0x1c>, <&pm 0x20 12>;
 	clock-names = "GCLK", "PM";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &adc {
-	clocks = <&gclk 0x1e>, <&pm 0x20 16>;
-	clock-names = "GCLK", "PM";
 	interrupts = <23 0>;
 	interrupt-names = "resrdy";
+	clocks = <&gclk 0x1e>, <&pm 0x20 16>;
+	clock-names = "GCLK", "PM";
+	/*
+	 * 2.1 MHz is ADC max clock
+	 * 8 MHz GCLK / 4 = 2 MHz
+	 * Generator 3: DFLL48M / 8MHz
+	 */
+	atmel,assigned-clocks = <&gclk 3>;
+	atmel,assigned-clock-names = "GCLK";
 };
diff --git a/dts/arm/atmel/samd2x.dtsi b/dts/arm/atmel/samd2x.dtsi
index d40e558f732..b889c1a6cdd 100644
--- a/dts/arm/atmel/samd2x.dtsi
+++ b/dts/arm/atmel/samd2x.dtsi
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2017 Google LLC.
+ * Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -18,6 +19,8 @@
 		port-a = &porta;
 		port-b = &portb;
 
+		rtc = &rtc;
+
 		sercom-0 = &sercom0;
 		sercom-1 = &sercom1;
 		sercom-2 = &sercom2;
@@ -77,7 +80,7 @@
 		};
 
 		pm: pm@40000400 {
-			compatible = "atmel,samd2x-pm";
+			compatible = "atmel,sam0-mclk";
 			reg = <0x40000400 0x400>;
 			interrupts = <0 0>;
 
@@ -85,10 +88,11 @@
 		};
 
 		gclk: gclk@40000c00 {
-			compatible = "atmel,samd2x-gclk";
+			compatible = "atmel,sam0-gclk";
 			reg = <0x40000c00 0x400>;
 
 			#clock-cells = <1>;
+			#atmel,assigned-clock-cells = <1>;
 		};
 
 		eic: eic@40001800 {
@@ -187,9 +191,12 @@
 			compatible = "atmel,sam0-rtc";
 			reg = <0x40001400 0x1C>;
 			interrupts = <3 0>;
+			clocks = <&gclk 4 4>, <&pm 0x18 5>;
+			clock-names = "GCLK", "PM";
 			status = "disabled";
 
-			clock-generator = <0>;
+			alarms-count = <1>;
+			cal-constant = <(1024 * 976)>;
 		};
 
 		adc: adc@42004000 {
@@ -199,11 +206,6 @@
 
 			#io-channel-cells = <1>;
 
-			/*
-			 * 2.1 MHz max, so clock it with the
-			 * 8 MHz GCLK / 4 = 2 MHz
-			 */
-			gclk = <3>;
 			prescaler = <4>;
 		};
 
diff --git a/dts/arm/atmel/samd5x.dtsi b/dts/arm/atmel/samd5x.dtsi
index 12593682eae..65123ef0e1d 100644
--- a/dts/arm/atmel/samd5x.dtsi
+++ b/dts/arm/atmel/samd5x.dtsi
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2019 ML!PA Consulting GmbH
+ * Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,6 +21,8 @@
 		port-c = &portc;
 		port-d = &portd;
 
+		rtc = &rtc;
+
 		sercom-0 = &sercom0;
 		sercom-1 = &sercom1;
 		sercom-2 = &sercom2;
@@ -44,6 +47,7 @@
 	};
 
 	chosen {
+		zephyr,flash-controller = &nvmctrl;
 		zephyr,entropy = &trng;
 		zephyr,flash-controller = &nvmctrl;
 	};
@@ -88,17 +92,25 @@
 		};
 
 		mclk: mclk@40000800 {
-			compatible = "atmel,samd5x-mclk";
+			compatible = "atmel,sam0-mclk";
 			reg = <0x40000800 0x400>;
 
 			#clock-cells = <2>;
 		};
 
+		osc32kctrl: osc32kctrl@40001400 {
+			compatible = "atmel,sam0-osc32kctrl";
+			reg = <0x40001400 0x400>;
+			#clock-cells = <0>;
+			#atmel,assigned-clock-cells = <1>;
+		};
+
 		gclk: gclk@40001c00 {
-			compatible = "atmel,samd5x-gclk";
+			compatible = "atmel,sam0-gclk";
 			reg = <0x40001c00 0x400>;
 
 			#clock-cells = <1>;
+			#atmel,assigned-clock-cells = <1>;
 		};
 
 		nvmctrl: nvmctrl@41004000  {
@@ -168,6 +180,8 @@
 			interrupts = <46 0>, <47 0>, <48 0>, <49 0>;
 			clocks = <&gclk 7>, <&mclk 0x14 12>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -177,6 +191,8 @@
 			interrupts = <50 0>, <51 0>, <52 0>, <53 0>;
 			clocks = <&gclk 8>, <&mclk 0x14 13>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -186,6 +202,8 @@
 			interrupts = <54 0>, <55 0>, <56 0>, <57 0>;
 			clocks = <&gclk 23>, <&mclk 0x18 9>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -195,6 +213,8 @@
 			interrupts = <58 0>, <59 0>, <60 0>, <61 0>;
 			clocks = <&gclk 24>, <&mclk 0x18 10>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -204,6 +224,8 @@
 			interrupts = <62 0>, <63 0>, <64 0>, <65 0>;
 			clocks = <&gclk 34>, <&mclk 0x20 0>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -213,6 +235,8 @@
 			interrupts = <66 0>, <67 0>, <68 0>, <69 0>;
 			clocks = <&gclk 35>, <&mclk 0x20 1>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -222,6 +246,8 @@
 			interrupts = <70 0>, <71 0>, <72 0>, <73 0>;
 			clocks = <&gclk 36>, <&mclk 0x20 2>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -231,6 +257,8 @@
 			interrupts = <74 0>, <75 0>, <76 0>, <77 0>;
 			clocks = <&gclk 37>, <&mclk 0x20 3>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -299,11 +327,16 @@
 
 		rtc: rtc@40002400 {
 			compatible = "atmel,sam0-rtc";
-			reg = <0x40002400 0x1C>;
+			reg = <0x40002400 0x40>;
 			interrupts = <11 0>;
+			clocks = <&osc32kctrl>, <&mclk 0x14 9>;
+			clock-names = "OSC32KCTRL", "MCLK";
+			atmel,assigned-clocks = <&osc32kctrl 0>;
+			atmel,assigned-clock-names = "OSC32KCTRL";
 			status = "disabled";
 
-			clock-generator = <0>;
+			alarms-count = <2>;
+			cal-constant = <(8192 * 128)>;
 		};
 
 		adc0: adc@43001c00 {
@@ -313,17 +346,20 @@
 			interrupt-names = "overrun", "resrdy";
 			clocks = <&gclk 40>, <&mclk 0x20 7>;
 			clock-names = "GCLK", "MCLK";
-			status = "disabled";
-
-			#io-channel-cells = <1>;
-
 			/*
-			 * 16 MHz max, source clock must not exceed 100 MHz.
+			 * 16 MHz is ADC max clock, source clock must not exceed 100 MHz.
 			 *	- table 54-8, section 54.6, page 2020
 			 *	- table 54-24, section 54.10.4, page 2031
-			 * -> 48 MHz GCLK(2) / 4 = 12 MHz
+			 * 48 MHz GCLK / 4 = 12 MHz
+			 * Generator 2: DFLL48M / 4
 			 */
-			gclk = <2>;
+			atmel,assigned-clocks = <&gclk 2>;
+			atmel,assigned-clock-names = "GCLK";
+
+			status = "disabled";
+
+			#io-channel-cells = <1>;
+
 			prescaler = <4>;
 			calib-offset = <0>;
 		};
@@ -335,17 +371,19 @@
 			interrupt-names = "overrun", "resrdy";
 			clocks = <&gclk 41>, <&mclk 0x20 8>;
 			clock-names = "GCLK", "MCLK";
-			status = "disabled";
-
-			#io-channel-cells = <1>;
-
 			/*
-			 * 16 MHz max, source clock must not exceed 100 MHz.
+			 * 16 MHz is ADC max clock, source clock must not exceed 100 MHz.
 			 *	- table 54-8, section 54.6, page 2020
 			 *	- table 54-24, section 54.10.4, page 2031
-			 * -> 48 MHz GCLK(2) / 4 = 12 MHz
+			 * 48 MHz GCLK / 4 = 12 MHz
+			 * Generator 2: DFLL48M / 4
 			 */
-			gclk = <2>;
+			atmel,assigned-clocks = <&gclk 2>;
+			atmel,assigned-clock-names = "GCLK";
+			status = "disabled";
+
+			#io-channel-cells = <1>;
+
 			prescaler = <4>;
 			calib-offset = <14>;
 		};
@@ -356,6 +394,8 @@
 			interrupts = <107 0>;
 			clocks = <&gclk 9>, <&mclk 0x14 14>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -365,6 +405,8 @@
 			interrupts = <109 0>;
 			clocks = <&gclk 26>, <&mclk 0x18 13>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -374,6 +416,8 @@
 			interrupts = <111 0>;
 			clocks = <&gclk 30>, <&mclk 0x1c 5>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -383,6 +427,8 @@
 			interrupts = <113 0>;
 			clocks = <&gclk 39>, <&mclk 0x20 5>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 		};
 
@@ -393,6 +439,8 @@
 				     <90 0>, <91 0>;
 			clocks = <&gclk 25>, <&mclk 0x18 11>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			channels = <6>;
@@ -405,6 +453,8 @@
 			interrupts = <92 0>, <93 0>, <94 0>, <95 0>, <96 0>;
 			clocks = <&gclk 25>, <&mclk 0x18 12>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			channels = <4>;
@@ -417,6 +467,8 @@
 			interrupts = <97 0>, <98 0>, <99 0>, <100 0>;
 			clocks = <&gclk 29>, <&mclk 0x1c 3>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			channels = <3>;
@@ -429,6 +481,8 @@
 			interrupts = <101 0>, <102 0>, <103 0>;
 			clocks = <&gclk 29>, <&mclk 0x1c 4>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			channels = <2>;
@@ -441,6 +495,8 @@
 			interrupts = <104 0>, <105 0>, <106 0>;
 			clocks = <&gclk 38>, <&mclk 0x20 4>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			channels = <2>;
diff --git a/dts/arm/atmel/same5x.dtsi b/dts/arm/atmel/same5x.dtsi
index 9df4876736a..f7b0418c4c1 100644
--- a/dts/arm/atmel/same5x.dtsi
+++ b/dts/arm/atmel/same5x.dtsi
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
  * Copyright (c) 2023 Sebastian Schlupp
+ * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -36,6 +37,8 @@
 			interrupt-names = "int0", "int1";
 			clocks = <&gclk 27>, <&mclk 0x10 17>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
@@ -49,6 +52,8 @@
 			interrupt-names = "int0", "int1";
 			clocks = <&gclk 28>, <&mclk 0x10 18>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
diff --git a/dts/arm/atmel/same70.dtsi b/dts/arm/atmel/same70.dtsi
index cf6a2e0a003..3896a1cacba 100644
--- a/dts/arm/atmel/same70.dtsi
+++ b/dts/arm/atmel/same70.dtsi
@@ -6,4 +6,3 @@
  */
 
 #include <atmel/samx7x.dtsi>
-#include "dma_atmel_same70.h"
diff --git a/dts/arm/atmel/same70b.dtsi b/dts/arm/atmel/same70b.dtsi
index 43bef4ee89b..7e250e2c250 100644
--- a/dts/arm/atmel/same70b.dtsi
+++ b/dts/arm/atmel/same70b.dtsi
@@ -5,4 +5,3 @@
  */
 
 #include <atmel/samx7xb.dtsi>
-#include "dma_atmel_same70.h"
diff --git a/dts/arm/atmel/saml21.dtsi b/dts/arm/atmel/saml21.dtsi
index 6e015b5772c..de2f456e200 100644
--- a/dts/arm/atmel/saml21.dtsi
+++ b/dts/arm/atmel/saml21.dtsi
@@ -21,6 +21,8 @@
 			interrupts = <14 0>;
 			clocks = <&gclk 25>, <&mclk 0x1c 5>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			channels = <4>;
@@ -33,6 +35,8 @@
 			interrupts = <15 0>;
 			clocks = <&gclk 25>, <&mclk 0x1c 6>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			channels = <4>;
@@ -45,6 +49,8 @@
 			interrupts = <16 0>;
 			clocks = <&gclk 26>, <&mclk 0x1c 7>;
 			clock-names = "GCLK", "MCLK";
+			atmel,assigned-clocks = <&gclk 0>;
+			atmel,assigned-clock-names = "GCLK";
 			status = "disabled";
 
 			channels = <2>;
@@ -57,48 +63,64 @@
 	interrupts = <24 0>;
 	clocks = <&gclk 32>, <&mclk 0x1c 12>;
 	clock-names = "GCLK", "MCLK";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &sercom0 {
 	interrupts = <8 0>;
 	clocks = <&gclk 18>, <&mclk 0x1c 0>;
 	clock-names = "GCLK", "MCLK";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &sercom1 {
 	interrupts = <9 0>;
 	clocks = <&gclk 19>, <&mclk 0x1c 1>;
 	clock-names = "GCLK", "MCLK";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &sercom2 {
 	interrupts = <10 0>;
 	clocks = <&gclk 20>, <&mclk 0x1c 2>;
 	clock-names = "GCLK", "MCLK";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &sercom3 {
 	interrupts = <11 0>;
 	clocks = <&gclk 21>, <&mclk 0x1c 3>;
 	clock-names = "GCLK", "MCLK";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &sercom4 {
 	interrupts = <12 0>;
 	clocks = <&gclk 22>, <&mclk 0x1c 4>;
 	clock-names = "GCLK", "MCLK";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &sercom5 {
 	interrupts = <13 0>;
 	clocks = <&gclk 24>, <&mclk 0x20 1>;
 	clock-names = "GCLK", "MCLK";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &tc4 {
 	interrupts = <21 0>;
 	clocks = <&gclk 29>, <&mclk 0x20 2>;
 	clock-names = "GCLK", "MCLK";
+	atmel,assigned-clocks = <&gclk 0>;
+	atmel,assigned-clock-names = "GCLK";
 };
 
 &adc {
@@ -106,4 +128,11 @@
 	interrupt-names = "resrdy";
 	clocks = <&gclk 30>, <&mclk 0x20 3>;
 	clock-names = "GCLK", "MCLK";
+	/*
+	 * 16 MHz is ADC max clock
+	 * 48 MHz DFLL / 2 / 2 = 12 MHz
+	 * Generator 3: 48MHz
+	 */
+	atmel,assigned-clocks = <&gclk 3>;
+	atmel,assigned-clock-names = "GCLK";
 };
diff --git a/dts/arm/atmel/saml2x.dtsi b/dts/arm/atmel/saml2x.dtsi
index d9191c03a13..f682ac0126a 100644
--- a/dts/arm/atmel/saml2x.dtsi
+++ b/dts/arm/atmel/saml2x.dtsi
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2021 Argentum Systems Ltd.
- * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
+ * Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -26,14 +26,16 @@
 		sercom-4 = &sercom4;
 		sercom-5 = &sercom5;
 
+		rtc = &rtc;
+
 		tc-4 = &tc4;
 
 		watchdog0 = &wdog;
 	};
 
 	chosen {
-		zephyr,flash-controller = &nvmctrl;
 		zephyr,entropy = &trng;
+		zephyr,flash-controller = &nvmctrl;
 	};
 
 	cpus {
@@ -80,26 +82,27 @@
 			};
 		};
 
-		pm: pm@40000400 {
-			compatible = "atmel,saml2x-pm";
+		mclk: mclk@40000400 {
+			compatible = "atmel,sam0-mclk";
 			reg = <0x40000400 0x400>;
-			interrupts = <0 0>;
 
 			#clock-cells = <2>;
 		};
 
-		mclk: mclk@40000400 {
-			compatible = "atmel,saml2x-mclk";
-			reg = <0x40000400 0x400>;
+		osc32kctrl: osc32kctrl@40001000 {
+			compatible = "atmel,sam0-osc32kctrl";
+			reg = <0x40001000 0x400>;
 
-			#clock-cells = <2>;
+			#clock-cells = <0>;
+			#atmel,assigned-clock-cells = <1>;
 		};
 
 		gclk: gclk@40001800 {
-			compatible = "atmel,saml2x-gclk";
+			compatible = "atmel,sam0-gclk";
 			reg = <0x40001800 0x400>;
 
 			#clock-cells = <1>;
+			#atmel,assigned-clock-cells = <1>;
 		};
 
 		dmac: dmac@44000400 {
@@ -195,11 +198,16 @@
 
 		rtc: rtc@40002000 {
 			compatible = "atmel,sam0-rtc";
-			reg = <0x40002000 0x1c>;
+			reg = <0x40002000 0x44>;
 			interrupts = <2 0>;
+			clocks = <&osc32kctrl>, <&mclk 0x14 8>;
+			clock-names = "OSC32KCTRL", "MCLK";
+			atmel,assigned-clocks = <&osc32kctrl 0>;
+			atmel,assigned-clock-names = "OSC32KCTRL";
 			status = "disabled";
 
-			clock-generator = <0>;
+			alarms-count = <1>;
+			cal-constant = <(8192 * 128)>;
 		};
 
 		adc: adc@43000c00 {
@@ -209,11 +217,6 @@
 
 			#io-channel-cells = <1>;
 
-			/*
-			 * 16 MHz max, so clock it with the
-			 * 48 MHz DFLL / 2 / 2 = 12 MHz
-			 */
-			gclk = <3>;
 			prescaler = <2>;
 		};
 
diff --git a/dts/arm/atmel/samr34.dtsi b/dts/arm/atmel/samr34.dtsi
index 351e02bb1e1..c14a08b28cf 100644
--- a/dts/arm/atmel/samr34.dtsi
+++ b/dts/arm/atmel/samr34.dtsi
@@ -28,6 +28,7 @@
 
 				#atmel,pin-cells = <2>;
 				#gpio-cells = <2>;
+
 				gpio-controller;
 			};
 		};
diff --git a/dts/arm/atmel/samv71.dtsi b/dts/arm/atmel/samv71.dtsi
index 29d52abcca3..a1a20fd8e07 100644
--- a/dts/arm/atmel/samv71.dtsi
+++ b/dts/arm/atmel/samv71.dtsi
@@ -5,4 +5,3 @@
  */
 
 #include <atmel/samx7x.dtsi>
-#include "dma_atmel_samv71.h"
diff --git a/dts/arm/atmel/samv71b.dtsi b/dts/arm/atmel/samv71b.dtsi
index cca7ebb3368..7e250e2c250 100644
--- a/dts/arm/atmel/samv71b.dtsi
+++ b/dts/arm/atmel/samv71b.dtsi
@@ -5,4 +5,3 @@
  */
 
 #include <atmel/samx7xb.dtsi>
-#include "dma_atmel_samv71.h"
diff --git a/dts/arm/atmel/samx7x.dtsi b/dts/arm/atmel/samx7x.dtsi
index 65ffc3cff78..23f43b92926 100644
--- a/dts/arm/atmel/samx7x.dtsi
+++ b/dts/arm/atmel/samx7x.dtsi
@@ -11,6 +11,7 @@
 #include <zephyr/dt-bindings/gpio/gpio.h>
 #include <zephyr/dt-bindings/pwm/pwm.h>
 #include <zephyr/dt-bindings/clock/atmel_sam_pmc.h>
+#include <zephyr/dt-bindings/dma/atmel_samx7x_dma.h>
 
 / {
 	aliases {
@@ -45,44 +46,73 @@
 	};
 
 	soc {
-		pmc: pmc@400e0600 {
-			compatible = "atmel,sam-pmc";
-			reg = <0x400e0600 0x200>;
-			interrupts = <5 0>;
-			#clock-cells = <2>;
-			status = "okay";
+		ssc: ssc@40004000 {
+			compatible = "atmel,sam-ssc";
+			reg = <0x40004000 0x4000>;
+			interrupts = <22 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
+			status = "disabled";
 		};
 
-		supc: supc@400e1810 {
-			compatible = "atmel,sam-supc";
-			reg = <0x400e1810 0x20>;
-			#wakeup-source-id-cells = <1>;
-			status = "okay";
+		spi0: spi@40008000 {
+			compatible = "atmel,sam-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40008000 0x4000>;
+			interrupts = <21 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
+			status = "disabled";
 		};
 
-		eefc: flash-controller@400e0c00 {
-			compatible = "atmel,sam-flash-controller";
-			reg = <0x400e0c00 0x200>;
-			interrupts = <6 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+		tc0: tc@4000c000 {
+			compatible = "atmel,sam-tc";
+			reg = <0x4000c000 0x100>;
+			interrupts = <23 0
+				      24 0
+				      25 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 23>,
+				 <&pmc PMC_TYPE_PERIPHERAL 24>,
+				 <&pmc PMC_TYPE_PERIPHERAL 25>;
+			status = "disabled";
 
-			#address-cells = <1>;
-			#size-cells = <1>;
-			#erase-block-cells = <2>;
+			qdec {
+				compatible = "atmel,sam-tc-qdec";
+				status = "disabled";
+			};
+		};
 
-			flash0: flash@400000 {
-				compatible = "atmel,sam-flash", "soc-nv-flash";
-				write-block-size = <16>;
-				erase-block-size = <8192>;
+		tc1: tc@40010000 {
+			compatible = "atmel,sam-tc";
+			reg = <0x40010000 0x100>;
+			interrupts = <26 0
+				      27 0
+				      28 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>,
+				 <&pmc PMC_TYPE_PERIPHERAL 27>,
+				 <&pmc PMC_TYPE_PERIPHERAL 28>;
+			status = "disabled";
+
+			qdec {
+				compatible = "atmel,sam-tc-qdec";
+				status = "disabled";
 			};
 		};
 
-		wdt: watchdog@400e1850 {
-			compatible = "atmel,sam-watchdog";
-			reg = <0x400e1850 0xc>;
-			interrupts = <4 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
+		tc2: tc@40014000 {
+			compatible = "atmel,sam-tc";
+			reg = <0x40014000 0x100>;
+			interrupts = <47 0
+				      48 0
+				      49 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 47>,
+				 <&pmc PMC_TYPE_PERIPHERAL 48>,
+				 <&pmc PMC_TYPE_PERIPHERAL 49>;
 			status = "disabled";
+
+			qdec {
+				compatible = "atmel,sam-tc-qdec";
+				status = "disabled";
+			};
 		};
 
 		twihs0: i2c@40018000 {
@@ -107,25 +137,129 @@
 			status = "disabled";
 		};
 
-		twihs2: i2c@40060000 {
-			compatible = "atmel,sam-i2c-twihs";
-			clock-frequency = <I2C_BITRATE_STANDARD>;
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x40060000 0x12B>;
-			interrupts = <41 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
+		pwm0: pwm0@40020000 {
+			compatible = "atmel,sam-pwm";
+			reg = <0x40020000 0x4000>;
+			interrupts = <31 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 31>;
 			status = "disabled";
+			prescaler = <10>;
+			divider = <1>;
+			#pwm-cells = <3>;
 		};
 
-		spi0: spi@40008000 {
-			compatible = "atmel,sam-spi";
+		usart0: usart@40024000 {
+			compatible = "atmel,sam-usart";
+			reg = <0x40024000 0x100>;
+			interrupts = <13 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+			status = "disabled";
+		};
+
+		usart1: usart@40028000 {
+			compatible = "atmel,sam-usart";
+			reg = <0x40028000 0x100>;
+			interrupts = <14 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+			status = "disabled";
+		};
+
+		usart2: usart@4002c000 {
+			compatible = "atmel,sam-usart";
+			reg = <0x4002c000 0x100>;
+			interrupts = <15 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
+			status = "disabled";
+		};
+
+		can0: can@40030000 {
+			compatible = "atmel,sam-can";
+			reg = <0x40030000 0x100>, <0x40088110 0x04>;
+			reg-names = "m_can", "dma_base";
+			interrupts = <35 0>, <36 0>;
+			interrupt-names = "int0", "int1";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 35>;
+			divider = <6>;
+			bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
+			status = "disabled";
+		};
+
+		can1: can@40034000 {
+			compatible = "atmel,sam-can";
+			reg = <0x40034000 0x100>, <0x40088114 0x4>;
+			reg-names = "m_can", "dma_base";
+			interrupts = <37 0>, <38 0>;
+			interrupt-names = "int0", "int1";
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
+			divider = <6>;
+			bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
+			status = "disabled";
+		};
+
+		usbhs: usbd@40038000 {
+			compatible = "atmel,sam-usbhs";
+			reg = <0x40038000 0x4000>;
+			interrupts = <34 0>;
+			interrupt-names = "usbhs";
+			maximum-speed = "high-speed";
+			num-bidir-endpoints = <10>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
+			status = "disabled";
+		};
+
+		afec0: adc@4003c000 {
+			compatible = "atmel,sam-afec";
+			reg = <0x4003c000 0x100>;
+			interrupts = <29 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
+		dacc: dacc@40040000 {
+			compatible = "atmel,sam-dac";
+			reg = <0x40040000 0x100>;
+			interrupts = <30 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
+		gmac: ethernet@40050000 {
+			compatible = "atmel,sam-gmac";
+			reg = <0x40050000 0x4000>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
+			interrupts = <39 0>, <66 0>, <67 0>;
+			interrupt-names = "gmac", "q1", "q2";
+			num-queues = <3>;
+			local-mac-address = [00 00 00 00 00 00];
+			status = "disabled";
+		};
+
+		mdio: mdio@40050000 {
+			compatible = "atmel,sam-mdio";
+			reg = <0x40050000 0x4000>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
+			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			reg = <0x40008000 0x4000>;
-			interrupts = <21 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
+		};
+
+		tc3: tc@40054000 {
+			compatible = "atmel,sam-tc";
+			reg = <0x40054000 0x100>;
+			interrupts = <50 0
+				      51 0
+				      52 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 50>,
+				 <&pmc PMC_TYPE_PERIPHERAL 51>,
+				 <&pmc PMC_TYPE_PERIPHERAL 52>;
 			status = "disabled";
+
+			qdec {
+				compatible = "atmel,sam-tc-qdec";
+				status = "disabled";
+			};
 		};
 
 		spi1: spi@40058000 {
@@ -138,95 +272,93 @@
 			status = "disabled";
 		};
 
-		uart0: uart@400e0800 {
-			compatible = "atmel,sam-uart";
-			reg = <0x400e0800 0x100>;
-			interrupts = <7 1>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
-			status = "disabled";
-		};
-
-		uart1: uart@400e0a00 {
-			compatible = "atmel,sam-uart";
-			reg = <0x400e0a00 0x100>;
-			interrupts = <8 1>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
-			status = "disabled";
-		};
-
-		uart2: uart@400e1a00 {
-			compatible = "atmel,sam-uart";
-			reg = <0x400e1a00 0x100>;
-			interrupts = <44 1>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
+		pwm1: pwm1@4005c000 {
+			compatible = "atmel,sam-pwm";
+			reg = <0x4005c000 0x4000>;
+			interrupts = <60 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 60>;
 			status = "disabled";
+			prescaler = <10>;
+			divider = <1>;
+			#pwm-cells = <3>;
 		};
 
-		uart3: uart@400e1c00 {
-			compatible = "atmel,sam-uart";
-			reg = <0x400e1c00 0x100>;
-			interrupts = <45 1>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
+		twihs2: i2c@40060000 {
+			compatible = "atmel,sam-i2c-twihs";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40060000 0x12B>;
+			interrupts = <41 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 41>;
 			status = "disabled";
 		};
 
-		uart4: uart@400e1e00 {
-			compatible = "atmel,sam-uart";
-			reg = <0x400e1e00 0x100>;
-			interrupts = <46 1>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
+		afec1: adc@40064000 {
+			compatible = "atmel,sam-afec";
+			reg = <0x40064000 0x100>;
+			interrupts = <40 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
 			status = "disabled";
+			#io-channel-cells = <1>;
 		};
 
-		usart0: usart@40024000 {
-			compatible = "atmel,sam-usart";
-			reg = <0x40024000 0x100>;
-			interrupts = <13 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
-			status = "disabled";
+		trng: random@40070000 {
+			compatible = "atmel,sam-trng";
+			reg = <0x40070000 0x4000>;
+			interrupts = <57 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 57>;
+			status = "okay";
 		};
 
-		usart1: usart@40028000 {
-			compatible = "atmel,sam-usart";
-			reg = <0x40028000 0x100>;
-			interrupts = <14 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+		xdmac: dma0: dma-controller@40078000 {
+			compatible = "atmel,sam-xdmac";
+			reg = <0x40078000 0x400>;
+			interrupts = <58 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 58>;
+			#dma-cells = <2>;
 			status = "disabled";
 		};
 
-		usart2: usart@4002c000 {
-			compatible = "atmel,sam-usart";
-			reg = <0x4002c000 0x100>;
-			interrupts = <15 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 15>;
-			status = "disabled";
+		pmc: pmc@400e0600 {
+			compatible = "atmel,sam-pmc";
+			reg = <0x400e0600 0x200>;
+			interrupts = <5 0>;
+			#clock-cells = <2>;
+			status = "okay";
 		};
 
-		afec0: adc@4003c000 {
-			compatible = "atmel,sam-afec";
-			reg = <0x4003c000 0x100>;
-			interrupts = <29 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
+		uart0: uart@400e0800 {
+			compatible = "atmel,sam-uart";
+			reg = <0x400e0800 0x100>;
+			interrupts = <7 1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
 			status = "disabled";
-			#io-channel-cells = <1>;
 		};
 
-		afec1: adc@40064000 {
-			compatible = "atmel,sam-afec";
-			reg = <0x40064000 0x100>;
-			interrupts = <40 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
+		uart1: uart@400e0a00 {
+			compatible = "atmel,sam-uart";
+			reg = <0x400e0a00 0x100>;
+			interrupts = <8 1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
 			status = "disabled";
-			#io-channel-cells = <1>;
 		};
 
-		dacc: dacc@40040000 {
-			compatible = "atmel,sam-dac";
-			reg = <0x40040000 0x100>;
-			interrupts = <30 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
-			status = "disabled";
-			#io-channel-cells = <1>;
+		eefc: flash-controller@400e0c00 {
+			compatible = "atmel,sam-flash-controller";
+			reg = <0x400e0c00 0x200>;
+			interrupts = <6 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#erase-block-cells = <2>;
+
+			flash0: flash@400000 {
+				compatible = "atmel,sam-flash", "soc-nv-flash";
+				write-block-size = <16>;
+				erase-block-size = <8192>;
+			};
 		};
 
 		pinctrl: pinctrl@400e0e00 {
@@ -286,189 +418,58 @@
 			};
 		};
 
-		pwm0: pwm0@40020000 {
-			compatible = "atmel,sam-pwm";
-			reg = <0x40020000 0x4000>;
-			interrupts = <31 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 31>;
-			status = "disabled";
-			prescaler = <10>;
-			divider = <1>;
-			#pwm-cells = <3>;
-		};
-
-		pwm1: pwm1@4005c000 {
-			compatible = "atmel,sam-pwm";
-			reg = <0x4005c000 0x4000>;
-			interrupts = <60 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 60>;
-			status = "disabled";
-			prescaler = <10>;
-			divider = <1>;
-			#pwm-cells = <3>;
-		};
-
-		usbhs: usbd@40038000 {
-			compatible = "atmel,sam-usbhs";
-			reg = <0x40038000 0x4000>;
-			interrupts = <34 0>;
-			interrupt-names = "usbhs";
-			maximum-speed = "high-speed";
-			num-bidir-endpoints = <10>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
-			status = "disabled";
-		};
-
-		gmac: ethernet@40050000 {
-			compatible = "atmel,sam-gmac";
-			reg = <0x40050000 0x4000>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
-			interrupts = <39 0>, <66 0>, <67 0>;
-			interrupt-names = "gmac", "q1", "q2";
-			num-queues = <3>;
-			local-mac-address = [00 00 00 00 00 00];
-			status = "disabled";
-		};
-
-		mdio: mdio@40050000 {
-			compatible = "atmel,sam-mdio";
-			reg = <0x40050000 0x4000>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 39>;
-			status = "disabled";
-			#address-cells = <1>;
-			#size-cells = <0>;
-		};
-
-		tc0: tc@4000c000 {
-			compatible = "atmel,sam-tc";
-			reg = <0x4000c000 0x100>;
-			interrupts = <23 0
-				      24 0
-				      25 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 23>,
-				 <&pmc PMC_TYPE_PERIPHERAL 24>,
-				 <&pmc PMC_TYPE_PERIPHERAL 25>;
-			status = "disabled";
-
-			qdec {
-				compatible = "atmel,sam-tc-qdec";
-				status = "disabled";
-			};
-		};
-
-		tc1: tc@40010000 {
-			compatible = "atmel,sam-tc";
-			reg = <0x40010000 0x100>;
-			interrupts = <26 0
-				      27 0
-				      28 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 26>,
-				 <&pmc PMC_TYPE_PERIPHERAL 27>,
-				 <&pmc PMC_TYPE_PERIPHERAL 28>;
-			status = "disabled";
-
-			qdec {
-				compatible = "atmel,sam-tc-qdec";
-				status = "disabled";
-			};
-		};
-
-		tc2: tc@40014000 {
-			compatible = "atmel,sam-tc";
-			reg = <0x40014000 0x100>;
-			interrupts = <47 0
-				      48 0
-				      49 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 47>,
-				 <&pmc PMC_TYPE_PERIPHERAL 48>,
-				 <&pmc PMC_TYPE_PERIPHERAL 49>;
-			status = "disabled";
-
-			qdec {
-				compatible = "atmel,sam-tc-qdec";
-				status = "disabled";
-			};
-		};
-
-		tc3: tc@40054000 {
-			compatible = "atmel,sam-tc";
-			reg = <0x40054000 0x100>;
-			interrupts = <50 0
-				      51 0
-				      52 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 50>,
-				 <&pmc PMC_TYPE_PERIPHERAL 51>,
-				 <&pmc PMC_TYPE_PERIPHERAL 52>;
-			status = "disabled";
-
-			qdec {
-				compatible = "atmel,sam-tc-qdec";
-				status = "disabled";
-			};
+		rstc: rstc@400e1800 {
+			compatible = "atmel,sam-rstc";
+			reg = <0x400e1800 0x10>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 1>;
+			user-nrst;
 		};
 
-		trng: random@40070000 {
-			compatible = "atmel,sam-trng";
-			reg = <0x40070000 0x4000>;
-			interrupts = <57 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 57>;
+		supc: supc@400e1810 {
+			compatible = "atmel,sam-supc";
+			reg = <0x400e1810 0x20>;
+			#wakeup-source-id-cells = <1>;
 			status = "okay";
 		};
 
-		xdmac: dma0: dma-controller@40078000 {
-			compatible = "atmel,sam-xdmac";
-			reg = <0x40078000 0x400>;
-			interrupts = <58 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 58>;
-			#dma-cells = <2>;
+		wdt: watchog@400e1850 {
+			compatible = "atmel,sam-watchdog";
+			reg = <0x400e1850 0xc>;
+			interrupts = <4 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
 			status = "disabled";
 		};
 
-		ssc: ssc@40004000 {
-			compatible = "atmel,sam-ssc";
-			reg = <0x40004000 0x4000>;
-			interrupts = <22 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
+		rtc: rtc@400e1860 {
+			compatible = "atmel,sam-rtc";
+			reg = <0x400e1860 0x100>;
+			interrupts = <2 0>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+			alarms-count = <1>;
 			status = "disabled";
 		};
 
-		can0: can@40030000 {
-			compatible = "atmel,sam-can";
-			reg = <0x40030000 0x100>, <0x40088110 0x04>;
-			reg-names = "m_can", "dma_base";
-			interrupts = <35 0>, <36 0>;
-			interrupt-names = "int0", "int1";
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 35>;
-			divider = <6>;
-			bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
+		uart2: uart@400e1a00 {
+			compatible = "atmel,sam-uart";
+			reg = <0x400e1a00 0x100>;
+			interrupts = <44 1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 44>;
 			status = "disabled";
 		};
 
-		can1: can@40034000 {
-			compatible = "atmel,sam-can";
-			reg = <0x40034000 0x100>, <0x40088114 0x4>;
-			reg-names = "m_can", "dma_base";
-			interrupts = <37 0>, <38 0>;
-			interrupt-names = "int0", "int1";
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 37>;
-			divider = <6>;
-			bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
+		uart3: uart@400e1c00 {
+			compatible = "atmel,sam-uart";
+			reg = <0x400e1c00 0x100>;
+			interrupts = <45 1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 45>;
 			status = "disabled";
 		};
 
-		rstc: rstc@400e1800 {
-			compatible = "atmel,sam-rstc";
-			reg = <0x400e1800 0x10>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 1>;
-			user-nrst;
-		};
-
-		rtc: rtc@400e1860 {
-			compatible = "atmel,sam-rtc";
-			reg = <0x400e1860 0x100>;
-			interrupts = <2 0>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
-			alarms-count = <1>;
+		uart4: uart@400e1e00 {
+			compatible = "atmel,sam-uart";
+			reg = <0x400e1e00 0x100>;
+			interrupts = <46 1>;
+			clocks = <&pmc PMC_TYPE_PERIPHERAL 46>;
 			status = "disabled";
 		};
 	};
diff --git a/dts/arm/atmel/samx7xx21.dtsi b/dts/arm/atmel/samx7xx21.dtsi
index 9433e3063aa..608672b4129 100644
--- a/dts/arm/atmel/samx7xx21.dtsi
+++ b/dts/arm/atmel/samx7xx21.dtsi
@@ -16,7 +16,7 @@
 		flash-controller@400e0c00 {
 			flash0: flash@400000 {
 				reg = <0x00400000 DT_SIZE_K(2048)>;
-				erase-blocks = <&eefc 8 2048>, <&eefc 252 8192>;
+				erase-blocks = <&eefc 8 2048>, <&eefc 254 8192>;
 			};
 		};
 	};
diff --git a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.dtsi b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.dtsi
index 56957dddab0..59f462ee85f 100644
--- a/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.dtsi
+++ b/dts/arm/infineon/cat1a/psoc6_01/psoc6_01.dtsi
@@ -544,5 +544,29 @@
 			interrupts = <164 6>;
 			status = "disabled";
 		};
+
+		dma0: dw@40280000 {
+			#dma-cells = <1>;
+			compatible = "infineon,cat1-dma";
+			reg = <0x40280000 0x8700>;
+			dma-channels = <16>;
+			interrupts = <50 6>, /* CH0 */
+					<51 6>, /* CH1 */
+					<52 6>, /* CH2 */
+					<53 6>, /* CH3 */
+					<54 6>, /* CH4 */
+					<55 6>, /* CH5 */
+					<56 6>, /* CH6 */
+					<57 6>, /* CH7 */
+					<58 6>, /* CH8 */
+					<59 6>, /* CH9 */
+					<60 6>, /* CH10 */
+					<61 6>, /* CH11 */
+					<62 6>, /* CH12 */
+					<63 6>, /* CH13 */
+					<64 6>, /* CH14 */
+					<65 6>;  /* CH15 */
+			status = "disabled";
+		};
 	};
 };
diff --git a/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.dtsi b/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.dtsi
index c61ba9e0ca4..8a54c3be4b8 100644
--- a/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.dtsi
+++ b/dts/arm/infineon/cat1a/psoc6_02/psoc6_02.dtsi
@@ -548,5 +548,80 @@
 			interrupts = <164 6>;
 			status = "disabled";
 		};
+
+		dma0: dw@40280000 {
+			#dma-cells = <1>;
+			compatible = "infineon,cat1-dma";
+			reg = <0x40280000 0x8700>;
+			dma-channels = <29>;
+			interrupts = <56 6>,  /* CH0 */
+				     <57 6>,  /* CH1 */
+				     <58 6>,  /* CH2 */
+				     <59 6>,  /* CH3 */
+				     <60 6>,  /* CH4 */
+				     <61 6>,  /* CH5 */
+				     <62 6>,  /* CH6 */
+				     <63 6>,  /* CH7 */
+				     <64 6>,  /* CH8 */
+				     <65 6>,  /* CH9 */
+				     <66 6>,  /* CH10 */
+				     <67 6>,  /* CH11 */
+				     <68 6>,  /* CH12 */
+				     <69 6>,  /* CH13 */
+				     <70 6>,  /* CH14 */
+				     <71 6>,  /* CH15 */
+				     <72 6>,  /* CH16 */
+				     <73 6>,  /* CH17 */
+				     <74 6>,  /* CH18 */
+				     <75 6>,  /* CH19 */
+				     <76 6>,  /* CH20 */
+				     <77 6>,  /* CH21 */
+				     <78 6>,  /* CH22 */
+				     <79 6>,  /* CH23 */
+				     <80 6>,  /* CH24 */
+				     <81 6>,  /* CH25 */
+				     <82 6>,  /* CH26 */
+				     <83 6>,  /* CH27 */
+				     <84 6>;  /* CH28 */
+			status = "disabled";
+		};
+
+		dma1: dw@40290000 {
+			#dma-cells = <1>;
+			compatible = "infineon,cat1-dma";
+			reg = <0x40290000 0x8700>;
+			dma-channels = <29>;
+			interrupts = <85 6>,  /* CH0 */
+				     <86 6>,  /* CH1 */
+				     <87 6>,  /* CH2 */
+				     <88 6>,  /* CH3 */
+				     <89 6>,  /* CH4 */
+				     <90 6>,  /* CH5 */
+				     <91 6>,  /* CH6 */
+				     <92 6>,  /* CH7 */
+				     <93 6>,  /* CH8 */
+				     <94 6>,  /* CH9 */
+				     <95 6>,  /* CH10 */
+				     <96 6>,  /* CH11 */
+				     <97 6>,  /* CH12 */
+				     <98 6>,  /* CH13 */
+				     <99 6>,  /* CH14 */
+				     <100 6>,  /* CH15 */
+				     <101 6>,  /* CH16 */
+				     <102 6>,  /* CH17 */
+				     <103 6>,  /* CH18 */
+				     <104 6>,  /* CH19 */
+				     <105 6>,  /* CH20 */
+				     <106 6>,  /* CH21 */
+				     <107 6>,  /* CH22 */
+				     <108 6>,  /* CH23 */
+				     <109 6>,  /* CH24 */
+				     <110 6>,  /* CH25 */
+				     <111 6>,  /* CH26 */
+				     <112 6>,  /* CH27 */
+				     <113 6>;  /* CH28 */
+			status = "disabled";
+		};
+
 	};
 };
diff --git a/dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi b/dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi
index 763eca835d2..69ef3d0fbf6 100644
--- a/dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi
+++ b/dts/arm/infineon/cat1b/cyw20829/cyw20829.dtsi
@@ -113,6 +113,14 @@
 			#gpio-cells = <2>;
 		};
 
+		adc0: adc@40520000 {
+			compatible = "infineon,cat1-adc";
+			reg = <0x40520000 0x10000>;
+			interrupts = <67 6>;
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
 		ipc0: ipc@401d0000 {
 			compatible = "infineon,cat1-ipc";
 			reg = <0x401d0000 0x10000>;
diff --git a/dts/arm/infineon/cat3/xmc/xmc4500_F100x1024.dtsi b/dts/arm/infineon/cat3/xmc/xmc4500_F100x1024.dtsi
index ff64b9bd9c1..01756ff766e 100644
--- a/dts/arm/infineon/cat3/xmc/xmc4500_F100x1024.dtsi
+++ b/dts/arm/infineon/cat3/xmc/xmc4500_F100x1024.dtsi
@@ -26,7 +26,7 @@
 };
 
 &flash0 {
-	reg = <0xc000000 DT_SIZE_M(1)>;
+	reg = <0x8000000 DT_SIZE_M(1)>;
 	pages_layout: pages_layout {
 		pages_layout_16k: pages_layout_16k {
 			pages-count = <8>;
diff --git a/dts/arm/infineon/cat3/xmc/xmc4700_F144x2048.dtsi b/dts/arm/infineon/cat3/xmc/xmc4700_F144x2048.dtsi
index 7a1d6f4db6e..069b841d7f6 100644
--- a/dts/arm/infineon/cat3/xmc/xmc4700_F144x2048.dtsi
+++ b/dts/arm/infineon/cat3/xmc/xmc4700_F144x2048.dtsi
@@ -20,7 +20,7 @@
 };
 
 &flash0 {
-	reg = <0xc000000 DT_SIZE_M(2)>;
+	reg = <0x8000000 DT_SIZE_M(2)>;
 	pages_layout: pages_layout {
 		pages_layout_16k: pages_layout_16k {
 			pages-count = <8>;
diff --git a/dts/arm/infineon/cat3/xmc/xmc4xxx.dtsi b/dts/arm/infineon/cat3/xmc/xmc4xxx.dtsi
index d2ea0e1314e..f757dd8328e 100644
--- a/dts/arm/infineon/cat3/xmc/xmc4xxx.dtsi
+++ b/dts/arm/infineon/cat3/xmc/xmc4xxx.dtsi
@@ -26,7 +26,7 @@
 		reg = <0x58001000 0x1400>;
 		#address-cells = <1>;
 		#size-cells = <1>;
-		flash0: flash@c000000 {
+		flash0: flash@8000000 {
 			compatible = "infineon,xmc4xxx-nv-flash","soc-nv-flash";
 			write-block-size = <256>;
 		};
diff --git a/dts/arm/microchip/mec1501hsz.dtsi b/dts/arm/microchip/mec1501hsz.dtsi
index af434217933..794b07ac4da 100644
--- a/dts/arm/microchip/mec1501hsz.dtsi
+++ b/dts/arm/microchip/mec1501hsz.dtsi
@@ -20,6 +20,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-m4";
 			reg = <0>;
+			clock-frequency = <48000000>;
 			cpu-power-states = <&idle &suspend_to_ram>;
 		};
 
@@ -160,6 +161,7 @@
 			compatible = "microchip,xec-rtos-timer";
 			reg = <0x40007400 0x10>;
 			interrupts = <111 0>;
+			clock-frequency = <32768>;
 			girqs = <23 10>;
 		};
 		bbram: bb-ram@4000a800 {
diff --git a/dts/arm/microchip/mec172x_common.dtsi b/dts/arm/microchip/mec172x_common.dtsi
index 9462c1b47c2..45f673809ec 100644
--- a/dts/arm/microchip/mec172x_common.dtsi
+++ b/dts/arm/microchip/mec172x_common.dtsi
@@ -290,6 +290,7 @@ rtimer: timer@40007400 {
 	compatible = "microchip,xec-rtos-timer";
 	reg = <0x40007400 0x10>;
 	interrupts = <111 0>;
+	clock-frequency = <32768>;
 	girqs = <23 10>;
 };
 timer0: timer@40000c00 {
diff --git a/dts/arm/microchip/mec172xnlj.dtsi b/dts/arm/microchip/mec172xnlj.dtsi
index 00d27b422c0..a0943723dc4 100644
--- a/dts/arm/microchip/mec172xnlj.dtsi
+++ b/dts/arm/microchip/mec172xnlj.dtsi
@@ -26,6 +26,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-m4";
 			reg = <0>;
+			clock-frequency = <96000000>;
 			cpu-power-states = <&idle &suspend_to_ram>;
 		};
 
diff --git a/dts/arm/microchip/mec172xnsz.dtsi b/dts/arm/microchip/mec172xnsz.dtsi
index 54103e9bcde..817e22361b8 100644
--- a/dts/arm/microchip/mec172xnsz.dtsi
+++ b/dts/arm/microchip/mec172xnsz.dtsi
@@ -26,6 +26,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-m4";
 			reg = <0>;
+			clock-frequency = <96000000>;
 			cpu-power-states = <&idle &suspend_to_ram>;
 		};
 
diff --git a/dts/arm/microchip/mec5.dtsi b/dts/arm/microchip/mec5.dtsi
index ad79ca5ecda..e37e86343d1 100644
--- a/dts/arm/microchip/mec5.dtsi
+++ b/dts/arm/microchip/mec5.dtsi
@@ -7,6 +7,7 @@
 #include <arm/armv7-m.dtsi>
 #include <zephyr/dt-bindings/gpio/gpio.h>
 #include <zephyr/dt-bindings/gpio/microchip-xec-gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
 #include <freq.h>
 #include <mem.h>
 
@@ -19,6 +20,7 @@
 			device_type = "cpu";
 			compatible = "arm,cortex-m4";
 			reg = <0>;
+			clock-frequency = <96000000>;
 		};
 	};
 
@@ -202,7 +204,7 @@
 			interrupts = <41 1>;
 			status = "disabled";
 		};
-		wdog: watchdog@40000400 {
+		watchdog0: watchdog@40000400 {
 			reg = <0x40000400 0x400>;
 			interrupts = <171 0>;
 			status = "disabled";
@@ -311,7 +313,7 @@
 			status = "disabled";
 		};
 		bbram: bb-ram@4000a800 {
-			reg = <0x4000a800 0x100>;
+			reg = <0x4000a800 0x80>;
 			reg-names = "memory";
 			status = "disabled";
 		};
diff --git a/dts/arm/microchip/mec5/mec5_i3c.dtsi b/dts/arm/microchip/mec5/mec5_i3c.dtsi
new file mode 100644
index 00000000000..23e55177b62
--- /dev/null
+++ b/dts/arm/microchip/mec5/mec5_i3c.dtsi
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2024 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Microchip MEC5 SoC's Improved I2C(I3C).
+ * Include this file in the soc {} section in the relevant chip DTSI files.
+ */
+i3c0: i3c@40010800 {
+	compatible = "microchip,mec5-i3c";
+	#address-cells = <3>;
+	#size-cells = <0>;
+	reg = <0x40010800 0x800>;
+	interrupts = <181 2>;
+	input-clock-frequency = <192000000>;
+	i3c-scl-hz = <12500000>;
+	i2c-scl-hz = <400000>;
+	status = "disabled";
+};
+
+i3c1: i3c@40010000 {
+	compatible = "microchip,mec5-i3c";
+	#address-cells = <3>;
+	#size-cells = <0>;
+	reg = <0x40010000 0x800>;
+	interrupts = <182 2>;
+	input-clock-frequency = <192000000>;
+	i3c-scl-hz = <12500000>;
+	i2c-scl-hz = <400000>;
+	status = "disabled";
+};
diff --git a/dts/arm/microchip/mec5_mec1753qsz.dtsi b/dts/arm/microchip/mec5_mec1753qsz.dtsi
index 79b14172a64..df308514457 100644
--- a/dts/arm/microchip/mec5_mec1753qsz.dtsi
+++ b/dts/arm/microchip/mec5_mec1753qsz.dtsi
@@ -7,7 +7,6 @@
 #include <arm/armv7-m.dtsi>
 
 #include "mec5.dtsi"
-#include "mec5/mec5_mec175xsz-espi-host-dev.dtsi"
 
 / {
 	flash0: flash@b0000 {
diff --git a/dts/arm/nordic/nrf54h20_cpuapp.dtsi b/dts/arm/nordic/nrf54h20_cpuapp.dtsi
index c56df42ddd5..15eac9c5d19 100644
--- a/dts/arm/nordic/nrf54h20_cpuapp.dtsi
+++ b/dts/arm/nordic/nrf54h20_cpuapp.dtsi
@@ -59,3 +59,7 @@ wdt011: &cpuapp_wdt011 {};
 &grtc {
 	interrupts = <109 NRF_DEFAULT_IRQ_PRIORITY>;
 };
+
+&nfct {
+	compatible = "nordic,nrf-nfct-v2";
+};
diff --git a/dts/arm/nordic/nrf54l_05_10_15_cpuapp.dtsi b/dts/arm/nordic/nrf54l_05_10_15_cpuapp.dtsi
index e5ec7785589..80875058f5f 100644
--- a/dts/arm/nordic/nrf54l_05_10_15_cpuapp.dtsi
+++ b/dts/arm/nordic/nrf54l_05_10_15_cpuapp.dtsi
@@ -25,6 +25,11 @@ nvic: &cpuapp_nvic {};
 		ranges;
 	};
 
+	rng: rng {
+		status = "okay";
+		compatible = "nordic,nrf-cracen-ctrdrbg";
+	};
+
 	psa_rng: psa-rng {
 		compatible = "zephyr,psa-crypto-rng";
 		status = "okay";
diff --git a/dts/arm/nuvoton/m55m1h2l.dtsi b/dts/arm/nuvoton/m55m1h2l.dtsi
new file mode 100644
index 00000000000..a7148b25cdf
--- /dev/null
+++ b/dts/arm/nuvoton/m55m1h2l.dtsi
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2025 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <nuvoton/m55m1x.dtsi>
+
+/ {
+	sram0: memory@20100000 {
+		compatible = "mmio-sram";
+		reg = <0x20100000 DT_SIZE_K(1344)>;
+	};
+
+	dtcm: memory@20000000 {
+		compatible = "zephyr,memory-region", "arm,dtcm";
+		reg = <0x20000000 DT_SIZE_K(128)>;
+		zephyr,memory-region = "DTCM";
+	};
+
+	itcm: memory@0 {
+		compatible = "zephyr,memory-region", "arm,itcm";
+		reg = <0x00000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "ITCM";
+	};
+
+	soc {
+		fmc: flash-controller@40044000 {
+			flash0: flash@100000 {
+				reg = <0x100000 DT_SIZE_K(2048)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/nuvoton/m55m1x.dtsi b/dts/arm/nuvoton/m55m1x.dtsi
new file mode 100644
index 00000000000..d0d17060552
--- /dev/null
+++ b/dts/arm/nuvoton/m55m1x.dtsi
@@ -0,0 +1,353 @@
+/*
+ * Copyright (c) 2025 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv8.1-m.dtsi>
+#include <mem.h>
+#include <freq.h>
+#include <zephyr/dt-bindings/clock/numaker_m55m1x_clock.h>
+#include <zephyr/dt-bindings/reset/numaker_m55m1x_reset.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	chosen {
+		zephyr,flash-controller = &fmc;
+	};
+
+	aliases {
+		rtc = &rtc;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m55";
+			reg = <0>;
+		};
+	};
+
+	sysclk: system-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <DT_FREQ_M(220)>;
+		#clock-cells = <0>;
+	};
+
+	soc {
+		scc: system-clock-controller@40001000 {
+			compatible = "nuvoton,numaker-scc";
+			reg = <0x40001000 0x100>;
+			#clock-cells = <0>;
+			lxt = "enable";
+			clk-pclkdiv = <(NUMAKER_CLK_PCLKDIV_PCLK0DIV(2) |
+					NUMAKER_CLK_PCLKDIV_PCLK1DIV(2) |
+					NUMAKER_CLK_PCLKDIV_PCLK2DIV(2) |
+					NUMAKER_CLK_PCLKDIV_PCLK3DIV(2) |
+					NUMAKER_CLK_PCLKDIV_PCLK4DIV(2))>;
+			core-clock = <DT_FREQ_M(220)>;
+			powerdown-mode = <NUMAKER_PMC_SPD0>;
+
+			pcc: peripheral-clock-controller {
+				compatible = "nuvoton,numaker-pcc";
+				#clock-cells = <3>;
+			};
+		};
+
+		rst: reset-controller@40000000 {
+			compatible = "nuvoton,numaker-rst";
+			reg = <0x40000000 0x2e0>;
+			#reset-cells = <1>;
+		};
+
+		fmc: flash-controller@40044000 {
+			compatible = "nuvoton,numaker-fmc";
+			reg = <0x40044000 0x120>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@100000 {
+				compatible = "soc-nv-flash";
+				erase-block-size = <8192>;
+				write-block-size = <4>;
+			};
+		};
+
+		uart0: serial@4024d000 {
+			compatible = "nuvoton,numaker-uart";
+			reg = <0x4024d000 0x1000>;
+			interrupts = <75 0>;
+			resets = <&rst NUMAKER_SYS_UART0RST>;
+			clocks = <&pcc NUMAKER_UART0_MODULE NUMAKER_CLK_UARTSEL0_UART0SEL_HIRC
+				  NUMAKER_CLK_UARTDIV0_UART0DIV(1)>;
+			status = "disabled";
+		};
+
+		uart1: serial@4028d000 {
+			compatible = "nuvoton,numaker-uart";
+			reg = <0x4028d000 0x1000>;
+			interrupts = <76 0>;
+			resets = <&rst NUMAKER_SYS_UART1RST>;
+			clocks = <&pcc NUMAKER_UART1_MODULE NUMAKER_CLK_UARTSEL0_UART1SEL_HIRC
+				  NUMAKER_CLK_UARTDIV0_UART1DIV(1)>;
+			status = "disabled";
+		};
+
+		uart2: serial@4024e000 {
+			compatible = "nuvoton,numaker-uart";
+			reg = <0x4024e000 0x1000>;
+			interrupts = <77 0>;
+			resets = <&rst NUMAKER_SYS_UART2RST>;
+			clocks = <&pcc NUMAKER_UART2_MODULE NUMAKER_CLK_UARTSEL0_UART2SEL_HIRC
+				  NUMAKER_CLK_UARTDIV0_UART2DIV(1)>;
+			status = "disabled";
+		};
+
+		uart3: serial@4028e000 {
+			compatible = "nuvoton,numaker-uart";
+			reg = <0x4028e000 0x1000>;
+			interrupts = <78 0>;
+			resets = <&rst NUMAKER_SYS_UART3RST>;
+			clocks = <&pcc NUMAKER_UART3_MODULE NUMAKER_CLK_UARTSEL0_UART3SEL_HIRC
+				  NUMAKER_CLK_UARTDIV0_UART3DIV(1)>;
+			status = "disabled";
+		};
+
+		uart4: serial@4024f000 {
+			compatible = "nuvoton,numaker-uart";
+			reg = <0x4024f000 0x1000>;
+			interrupts = <79 0>;
+			resets = <&rst NUMAKER_SYS_UART4RST>;
+			clocks = <&pcc NUMAKER_UART4_MODULE NUMAKER_CLK_UARTSEL0_UART4SEL_HIRC
+				  NUMAKER_CLK_UARTDIV0_UART4DIV(1)>;
+			status = "disabled";
+		};
+
+		uart5: serial@4028f000 {
+			compatible = "nuvoton,numaker-uart";
+			reg = <0x4028f000 0x1000>;
+			interrupts = <80 0>;
+			resets = <&rst NUMAKER_SYS_UART5RST>;
+			clocks = <&pcc NUMAKER_UART5_MODULE NUMAKER_CLK_UARTSEL0_UART5SEL_HIRC
+				  NUMAKER_CLK_UARTDIV0_UART5DIV(1)>;
+			status = "disabled";
+		};
+
+		uart6: serial@40250000 {
+			compatible = "nuvoton,numaker-uart";
+			reg = <0x40250000 0x1000>;
+			interrupts = <81 0>;
+			resets = <&rst NUMAKER_SYS_UART6RST>;
+			clocks = <&pcc NUMAKER_UART6_MODULE NUMAKER_CLK_UARTSEL0_UART6SEL_HIRC
+				  NUMAKER_CLK_UARTDIV0_UART6DIV(1)>;
+			status = "disabled";
+		};
+
+		uart7: serial@40290000 {
+			compatible = "nuvoton,numaker-uart";
+			reg = <0x40290000 0x1000>;
+			interrupts = <82 0>;
+			resets = <&rst NUMAKER_SYS_UART7RST>;
+			clocks = <&pcc NUMAKER_UART7_MODULE NUMAKER_CLK_UARTSEL0_UART7SEL_HIRC
+				  NUMAKER_CLK_UARTDIV0_UART7DIV(1)>;
+			status = "disabled";
+		};
+
+		uart8: serial@40251000 {
+			compatible = "nuvoton,numaker-uart";
+			reg = <0x40251000 0x1000>;
+			interrupts = <83 0>;
+			resets = <&rst NUMAKER_SYS_UART8RST>;
+			clocks = <&pcc NUMAKER_UART8_MODULE NUMAKER_CLK_UARTSEL1_UART8SEL_HIRC
+				  NUMAKER_CLK_UARTDIV1_UART8DIV(1)>;
+			status = "disabled";
+		};
+
+		uart9: serial@40291000 {
+			compatible = "nuvoton,numaker-uart";
+			reg = <0x40291000 0x1000>;
+			interrupts = <84 0>;
+			resets = <&rst NUMAKER_SYS_UART9RST>;
+			clocks = <&pcc NUMAKER_UART9_MODULE NUMAKER_CLK_UARTSEL1_UART9SEL_HIRC
+				  NUMAKER_CLK_UARTDIV1_UART9DIV(1)>;
+			status = "disabled";
+		};
+
+		pinctrl: pin-controller@40000080 {
+			compatible = "nuvoton,numaker-pinctrl";
+			reg = <0x40000080 0x30
+			       0x40000300 0x100>;
+			reg-names = "mfos", "mfp";
+		};
+
+		gpioa: gpio@40229000 {
+			compatible = "nuvoton,numaker-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x40229000 0x40>;
+			clocks = <&pcc NUMAKER_GPIOA_MODULE 0 0>;
+			status = "disabled";
+			interrupts = <20 2>;
+		};
+
+		gpiob: gpio@40229040 {
+			compatible = "nuvoton,numaker-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x40229040 0x40>;
+			clocks = <&pcc NUMAKER_GPIOB_MODULE 0 0>;
+			status = "disabled";
+			interrupts = <21 2>;
+		};
+
+		gpioc: gpio@40229080 {
+			compatible = "nuvoton,numaker-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x40229080 0x40>;
+			clocks = <&pcc NUMAKER_GPIOC_MODULE 0 0>;
+			status = "disabled";
+			interrupts = <22 2>;
+		};
+
+		gpiod: gpio@402290c0 {
+			compatible = "nuvoton,numaker-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x402290c0 0x40>;
+			clocks = <&pcc NUMAKER_GPIOD_MODULE 0 0>;
+			status = "disabled";
+			interrupts = <23 2>;
+		};
+
+		gpioe: gpio@40229100 {
+			compatible = "nuvoton,numaker-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x40229100 0x40>;
+			clocks = <&pcc NUMAKER_GPIOE_MODULE 0 0>;
+			status = "disabled";
+			interrupts = <24 2>;
+		};
+
+		gpiof: gpio@40229140 {
+			compatible = "nuvoton,numaker-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x40229140 0x40>;
+			clocks = <&pcc NUMAKER_GPIOF_MODULE 0 0>;
+			status = "disabled";
+			interrupts = <25 2>;
+		};
+
+		gpiog: gpio@40229180 {
+			compatible = "nuvoton,numaker-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x40229180 0x40>;
+			clocks = <&pcc NUMAKER_GPIOG_MODULE 0 0>;
+			status = "disabled";
+			interrupts = <26 2>;
+		};
+
+		gpioh: gpio@402291c0 {
+			compatible = "nuvoton,numaker-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x402291c0 0x40>;
+			clocks = <&pcc NUMAKER_GPIOH_MODULE 0 0>;
+			status = "disabled";
+			interrupts = <27 2>;
+		};
+
+		gpioi: gpio@40229200 {
+			compatible = "nuvoton,numaker-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x40229200 0x40>;
+			clocks = <&pcc NUMAKER_GPIOI_MODULE 0 0>;
+			status = "disabled";
+			interrupts = <28 2>;
+		};
+
+		gpioj: gpio@40229240 {
+			compatible = "nuvoton,numaker-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x40229240 0x40>;
+			clocks = <&pcc NUMAKER_GPIOJ_MODULE 0 0>;
+			status = "disabled";
+			interrupts = <29 2>;
+		};
+
+		rtc: rtc@40297000 {
+			compatible = "nuvoton,numaker-rtc";
+			reg = <0x40297000 0x1000>;
+			interrupts = <6 0>;
+			oscillator = "lxt";
+			clocks = <&pcc NUMAKER_RTC0_MODULE 0 0>;
+			alarms-count = <1>;
+		};
+
+		spi0: spi@4024b000 {
+			compatible = "nuvoton,numaker-spi";
+			reg = <0x4024b000 0x1000>;
+			interrupts = <66 0>;
+			resets = <&rst NUMAKER_SYS_SPI0RST>;
+			clocks = <&pcc NUMAKER_SPI0_MODULE NUMAKER_CLK_SPISEL_SPI0SEL_HIRC 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi1: spi@4028b000 {
+			compatible = "nuvoton,numaker-spi";
+			reg = <0x4028b000 0x1000>;
+			interrupts = <67 0>;
+			resets = <&rst NUMAKER_SYS_SPI1RST>;
+			clocks = <&pcc NUMAKER_SPI1_MODULE NUMAKER_CLK_SPISEL_SPI1SEL_HIRC 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi2: spi@4024c000 {
+			compatible = "nuvoton,numaker-spi";
+			reg = <0x4024c000 0x1000>;
+			interrupts = <68 0>;
+			resets = <&rst NUMAKER_SYS_SPI2RST>;
+			clocks = <&pcc NUMAKER_SPI2_MODULE NUMAKER_CLK_SPISEL_SPI2SEL_HIRC 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi3: spi@4028c000 {
+			compatible = "nuvoton,numaker-spi";
+			reg = <0x4028c000 0x1000>;
+			interrupts = <69 0>;
+			resets = <&rst NUMAKER_SYS_SPI3RST>;
+			clocks = <&pcc NUMAKER_SPI3_MODULE NUMAKER_CLK_SPISEL_SPI3SEL_HIRC 0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		emac: ethernet@40208000 {
+			compatible = "nuvoton,numaker-ethernet";
+			reg = <0x40208000 0x2000>;
+			interrupts = <63 0>;
+			resets = <&rst NUMAKER_SYS_EMAC0RST>;
+			phy-addr = <0>;
+			clocks = <&pcc NUMAKER_EMAC0_MODULE 0 0>;
+			status = "disabled";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};
diff --git a/dts/arm/nuvoton/npcx/npcx-miwus-wui-map.dtsi b/dts/arm/nuvoton/npcx/npcx-miwus-wui-map.dtsi
index ec82dd71a86..200f765026c 100644
--- a/dts/arm/nuvoton/npcx/npcx-miwus-wui-map.dtsi
+++ b/dts/arm/nuvoton/npcx/npcx-miwus-wui-map.dtsi
@@ -89,12 +89,6 @@
 		wui_iob0: wui0-4-2 {
 			miwus = <&miwu0 3 2>; /* GPIOB0 */
 		};
-		wui_smb0_2: wui0-4-3 {
-			miwus = <&miwu0 3 3>; /* SMB0/2 */
-		};
-		wui_smb1_3: wui0-4-4 {
-			miwus = <&miwu0 3 4>; /* SMB1/3 */
-		};
 		wui_iob1: wui0-4-5 {
 			miwus = <&miwu0 3 5>; /* GPIOB1 */
 		};
diff --git a/dts/arm/nuvoton/npcx/npcx.dtsi b/dts/arm/nuvoton/npcx/npcx.dtsi
index 125ebb65633..aaaca78d026 100644
--- a/dts/arm/nuvoton/npcx/npcx.dtsi
+++ b/dts/arm/nuvoton/npcx/npcx.dtsi
@@ -12,6 +12,7 @@
 #include <zephyr/dt-bindings/flash_controller/npcx_fiu_qspi.h>
 #include <zephyr/dt-bindings/gpio/gpio.h>
 #include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/i2c/npcx-i2c.h>
 #include <zephyr/dt-bindings/pinctrl/npcx-pinctrl.h>
 #include <zephyr/dt-bindings/pwm/pwm.h>
 #include <zephyr/dt-bindings/sensor/npcx_tach.h>
@@ -384,71 +385,6 @@
 				<&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 7>;
 		};
 
-		/* I2c Controllers - Do not use them as i2c node directly */
-		i2c_ctrl0: i2c@40009000 {
-			compatible = "nuvoton,npcx-i2c-ctrl";
-			reg = <0x40009000 0x1000>;
-			interrupts = <13 3>;
-			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 0>;
-			status = "disabled";
-		};
-
-		i2c_ctrl1: i2c@4000b000 {
-			compatible = "nuvoton,npcx-i2c-ctrl";
-			reg = <0x4000b000 0x1000>;
-			interrupts = <14 3>;
-			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 1>;
-			status = "disabled";
-		};
-
-		i2c_ctrl2: i2c@400c0000 {
-			compatible = "nuvoton,npcx-i2c-ctrl";
-			reg = <0x400c0000 0x1000>;
-			interrupts = <36 3>;
-			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 2>;
-			status = "disabled";
-		};
-
-		i2c_ctrl3: i2c@400c2000 {
-			compatible = "nuvoton,npcx-i2c-ctrl";
-			reg = <0x400c2000 0x1000>;
-			interrupts = <37 3>;
-			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 3>;
-			status = "disabled";
-		};
-
-		i2c_ctrl4: i2c@40008000 {
-			compatible = "nuvoton,npcx-i2c-ctrl";
-			reg = <0x40008000 0x1000>;
-			interrupts = <19 3>;
-			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 4>;
-			status = "disabled";
-		};
-
-		i2c_ctrl5: i2c@40017000 {
-			compatible = "nuvoton,npcx-i2c-ctrl";
-			reg = <0x40017000 0x1000>;
-			interrupts = <20 3>;
-			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 0>;
-			status = "disabled";
-		};
-
-		i2c_ctrl6: i2c@40018000 {
-			compatible = "nuvoton,npcx-i2c-ctrl";
-			reg = <0x40018000 0x1000>;
-			interrupts = <16 3>;
-			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 1>;
-			status = "disabled";
-		};
-
-		i2c_ctrl7: i2c@40019000 {
-			compatible = "nuvoton,npcx-i2c-ctrl";
-			reg = <0x40019000 0x1000>;
-			interrupts = <8 3>;
-			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 2>;
-			status = "disabled";
-		};
-
 		tach1: tach@400e1000 {
 			compatible = "nuvoton,npcx-tach";
 			reg = <0x400e1000 0x2000>;
@@ -549,7 +485,7 @@
 			compatible = "nuvoton,npcx-i2c-port";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			port = <0x00>;
+			port = <NPCX_I2C_CTRL_PORT(0, 0)>;
 			controller = <&i2c_ctrl0>;
 			status = "disabled";
 		};
@@ -558,7 +494,7 @@
 			compatible = "nuvoton,npcx-i2c-port";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			port = <0x10>;
+			port = <NPCX_I2C_CTRL_PORT(1, 0)>;
 			controller = <&i2c_ctrl1>;
 			status = "disabled";
 		};
@@ -567,7 +503,7 @@
 			compatible = "nuvoton,npcx-i2c-port";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			port = <0x20>;
+			port = <NPCX_I2C_CTRL_PORT(2, 0)>;
 			controller = <&i2c_ctrl2>;
 			status = "disabled";
 		};
@@ -576,7 +512,7 @@
 			compatible = "nuvoton,npcx-i2c-port";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			port = <0x30>;
+			port = <NPCX_I2C_CTRL_PORT(3, 0)>;
 			controller = <&i2c_ctrl3>;
 			status = "disabled";
 		};
@@ -585,7 +521,7 @@
 			compatible = "nuvoton,npcx-i2c-port";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			port = <0x41>;
+			port = <NPCX_I2C_CTRL_PORT(4, 1)>;
 			controller = <&i2c_ctrl4>;
 			status = "disabled";
 		};
@@ -594,7 +530,7 @@
 			compatible = "nuvoton,npcx-i2c-port";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			port = <0x50>;
+			port = <NPCX_I2C_CTRL_PORT(5, 0)>;
 			controller = <&i2c_ctrl5>;
 			status = "disabled";
 		};
@@ -603,7 +539,7 @@
 			compatible = "nuvoton,npcx-i2c-port";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			port = <0x51>;
+			port = <NPCX_I2C_CTRL_PORT(5, 1)>;
 			controller = <&i2c_ctrl5>;
 			status = "disabled";
 		};
@@ -612,7 +548,7 @@
 			compatible = "nuvoton,npcx-i2c-port";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			port = <0x60>;
+			port = <NPCX_I2C_CTRL_PORT(6, 0)>;
 			controller = <&i2c_ctrl6>;
 			status = "disabled";
 		};
@@ -621,7 +557,7 @@
 			compatible = "nuvoton,npcx-i2c-port";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			port = <0x61>;
+			port = <NPCX_I2C_CTRL_PORT(6, 1)>;
 			controller = <&i2c_ctrl6>;
 			status = "disabled";
 		};
@@ -630,7 +566,7 @@
 			compatible = "nuvoton,npcx-i2c-port";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			port = <0x70>;
+			port = <NPCX_I2C_CTRL_PORT(7, 0)>;
 			controller = <&i2c_ctrl7>;
 			status = "disabled";
 		};
diff --git a/dts/arm/nuvoton/npcx/npcx4.dtsi b/dts/arm/nuvoton/npcx/npcx4.dtsi
index 6bc44daae1d..ab83adda792 100644
--- a/dts/arm/nuvoton/npcx/npcx4.dtsi
+++ b/dts/arm/nuvoton/npcx/npcx4.dtsi
@@ -296,6 +296,79 @@
 				     &lvol_iof4 &lvol_iof5 &lvol_none &lvol_none>;
 		};
 
+		/* I2c Controllers - Do not use them as i2c node directly */
+		i2c_ctrl0: i2c@40009000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x40009000 0x1000>;
+			interrupts = <13 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 0>;
+			smb-wui = <&wui_smb0>;
+			status = "disabled";
+		};
+
+		i2c_ctrl1: i2c@4000b000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x4000b000 0x1000>;
+			interrupts = <14 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 1>;
+			smb-wui = <&wui_smb1>;
+			status = "disabled";
+		};
+
+		i2c_ctrl2: i2c@400c0000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x400c0000 0x1000>;
+			interrupts = <36 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 2>;
+			smb-wui = <&wui_smb2>;
+			status = "disabled";
+		};
+
+		i2c_ctrl3: i2c@400c2000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x400c2000 0x1000>;
+			interrupts = <37 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 3>;
+			smb-wui = <&wui_smb3>;
+			status = "disabled";
+		};
+
+		i2c_ctrl4: i2c@40008000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x40008000 0x1000>;
+			interrupts = <19 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 4>;
+			smb-wui = <&wui_smb4>;
+			status = "disabled";
+		};
+
+		i2c_ctrl5: i2c@40017000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x40017000 0x1000>;
+			interrupts = <20 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 0>;
+			smb-wui = <&wui_smb5>;
+			status = "disabled";
+		};
+
+		i2c_ctrl6: i2c@40018000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x40018000 0x1000>;
+			interrupts = <16 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 1>;
+			smb-wui = <&wui_smb6>;
+			status = "disabled";
+		};
+
+		i2c_ctrl7: i2c@40019000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x40019000 0x1000>;
+			interrupts = <8 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 2>;
+			smb-wui = <&wui_smb7>;
+			status = "disabled";
+		};
+
 		/* ADC0 comparator configuration in npcx4 series */
 		adc0: adc@400d1000 {
 			channel-count = <26>;
@@ -449,7 +522,7 @@
 			compatible = "nuvoton,npcx-i2c-port";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			port = <0x40>;
+			port = <NPCX_I2C_CTRL_PORT(4, 0)>;
 			controller = <&i2c_ctrl4>;
 			status = "disabled";
 		};
@@ -458,7 +531,7 @@
 			compatible = "nuvoton,npcx-i2c-port";
 			#address-cells = <1>;
 			#size-cells = <0>;
-			port = <0x71>;
+			port = <NPCX_I2C_CTRL_PORT(7, 1)>;
 			controller = <&i2c_ctrl7>;
 			status = "disabled";
 		};
diff --git a/dts/arm/nuvoton/npcx/npcx4/npcx4-miwus-wui-map.dtsi b/dts/arm/nuvoton/npcx/npcx4/npcx4-miwus-wui-map.dtsi
index ace5d4b1562..4faef5898c2 100644
--- a/dts/arm/nuvoton/npcx/npcx4/npcx4-miwus-wui-map.dtsi
+++ b/dts/arm/nuvoton/npcx/npcx4/npcx4-miwus-wui-map.dtsi
@@ -19,6 +19,14 @@
 			miwus = <&miwu0 7 7>; /* GPIOE7 */
 		};
 
+		/* MIWU group D */
+		wui_smb0: wui0-4-3 {
+			miwus = <&miwu0 3 3>; /* SMB0 */
+		};
+		wui_smb1: wui0-4-4 {
+			miwus = <&miwu0 3 4>; /* SMB1 */
+		};
+
 		/* MIWU table 1 */
 		/* MIWU group B */
 		wui_io13: wui1-2-3 {
@@ -82,7 +90,7 @@
 			miwus = <&miwu2 6 7>; /* I3C1_RSTW */
 		};
 
-		/* MIWU group G */
+		/* MIWU group H */
 		wui_i3c2_addrw: wui2-8-0 {
 			miwus = <&miwu2 7 0>; /* I3C2_ADDRW */
 		};
diff --git a/dts/arm/nuvoton/npcx/npcx7.dtsi b/dts/arm/nuvoton/npcx/npcx7.dtsi
index 5b5b033a54c..3496e454d8b 100644
--- a/dts/arm/nuvoton/npcx/npcx7.dtsi
+++ b/dts/arm/nuvoton/npcx/npcx7.dtsi
@@ -263,6 +263,79 @@
 				     &lvol_iof4 &lvol_iof5 &lvol_none &lvol_none>;
 		};
 
+		/* I2c Controllers - Do not use them as i2c node directly */
+		i2c_ctrl0: i2c@40009000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x40009000 0x1000>;
+			interrupts = <13 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 0>;
+			smb-wui = <&wui_smb0_2>;
+			status = "disabled";
+		};
+
+		i2c_ctrl1: i2c@4000b000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x4000b000 0x1000>;
+			interrupts = <14 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 1>;
+			smb-wui = <&wui_smb1_3>;
+			status = "disabled";
+		};
+
+		i2c_ctrl2: i2c@400c0000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x400c0000 0x1000>;
+			interrupts = <36 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 2>;
+			smb-wui = <&wui_smb0_2>;
+			status = "disabled";
+		};
+
+		i2c_ctrl3: i2c@400c2000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x400c2000 0x1000>;
+			interrupts = <37 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 3>;
+			smb-wui = <&wui_smb1_3>;
+			status = "disabled";
+		};
+
+		i2c_ctrl4: i2c@40008000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x40008000 0x1000>;
+			interrupts = <19 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 4>;
+			smb-wui = <&wui_smb4>;
+			status = "disabled";
+		};
+
+		i2c_ctrl5: i2c@40017000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x40017000 0x1000>;
+			interrupts = <20 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 0>;
+			smb-wui = <&wui_smb5>;
+			status = "disabled";
+		};
+
+		i2c_ctrl6: i2c@40018000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x40018000 0x1000>;
+			interrupts = <16 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 1>;
+			smb-wui = <&wui_smb6>;
+			status = "disabled";
+		};
+
+		i2c_ctrl7: i2c@40019000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x40019000 0x1000>;
+			interrupts = <8 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 2>;
+			smb-wui = <&wui_smb7>;
+			status = "disabled";
+		};
+
 		/* ADC0 comparator configuration in npcx7 series */
 		adc0: adc@400d1000 {
 			channel-count = <10>;
diff --git a/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-wui-map.dtsi b/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-wui-map.dtsi
index 700cfd0ce4c..3a0e4153dbb 100644
--- a/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-wui-map.dtsi
+++ b/dts/arm/nuvoton/npcx/npcx7/npcx7-miwus-wui-map.dtsi
@@ -18,12 +18,18 @@
 		wui_cr_sin2: wui0-1-6-2 {
 			miwus = <&miwu0 0 6>; /* CR_SIN2 */
 		};
-
-		/* MIWU group A */
 		wui_io86: wui0-1-6 {
 			miwus = <&miwu0 0 6>; /* GPIO86 */
 		};
 
+		/* MIWU group D */
+		wui_smb0_2: wui0-4-3 {
+			miwus = <&miwu0 3 3>; /* SMB0/2 */
+		};
+		wui_smb1_3: wui0-4-4 {
+			miwus = <&miwu0 3 4>; /* SMB1/3 */
+		};
+
 		/* MIWU group G */
 		wui_iod7: wui0-7-6 {
 			miwus = <&miwu0 6 6>; /* GPIOD7 */
diff --git a/dts/arm/nuvoton/npcx/npcx9.dtsi b/dts/arm/nuvoton/npcx/npcx9.dtsi
index dd991f8fd57..c6cde81c38d 100644
--- a/dts/arm/nuvoton/npcx/npcx9.dtsi
+++ b/dts/arm/nuvoton/npcx/npcx9.dtsi
@@ -296,6 +296,79 @@
 				     &lvol_iof4 &lvol_iof5 &lvol_none &lvol_none>;
 		};
 
+		/* I2c Controllers - Do not use them as i2c node directly */
+		i2c_ctrl0: i2c@40009000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x40009000 0x1000>;
+			interrupts = <13 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 0>;
+			smb-wui = <&wui_smb0_2>;
+			status = "disabled";
+		};
+
+		i2c_ctrl1: i2c@4000b000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x4000b000 0x1000>;
+			interrupts = <14 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 1>;
+			smb-wui = <&wui_smb1_3>;
+			status = "disabled";
+		};
+
+		i2c_ctrl2: i2c@400c0000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x400c0000 0x1000>;
+			interrupts = <36 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 2>;
+			smb-wui = <&wui_smb0_2>;
+			status = "disabled";
+		};
+
+		i2c_ctrl3: i2c@400c2000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x400c2000 0x1000>;
+			interrupts = <37 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB2 NPCX_PWDWN_CTL3 3>;
+			smb-wui = <&wui_smb1_3>;
+			status = "disabled";
+		};
+
+		i2c_ctrl4: i2c@40008000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x40008000 0x1000>;
+			interrupts = <19 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL3 4>;
+			smb-wui = <&wui_smb4>;
+			status = "disabled";
+		};
+
+		i2c_ctrl5: i2c@40017000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x40017000 0x1000>;
+			interrupts = <20 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 0>;
+			smb-wui = <&wui_smb5>;
+			status = "disabled";
+		};
+
+		i2c_ctrl6: i2c@40018000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x40018000 0x1000>;
+			interrupts = <16 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 1>;
+			smb-wui = <&wui_smb6>;
+			status = "disabled";
+		};
+
+		i2c_ctrl7: i2c@40019000 {
+			compatible = "nuvoton,npcx-i2c-ctrl";
+			reg = <0x40019000 0x1000>;
+			interrupts = <8 3>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL7 2>;
+			smb-wui = <&wui_smb7>;
+			status = "disabled";
+		};
+
 		/* ADC0 comparator configuration in npcx9 series */
 		adc0: adc@400d1000 {
 			channel-count = <12>;
diff --git a/dts/arm/nuvoton/npcx/npcx9/npcx9-miwus-wui-map.dtsi b/dts/arm/nuvoton/npcx/npcx9/npcx9-miwus-wui-map.dtsi
index 6d280e75cb0..a1b711a1da4 100644
--- a/dts/arm/nuvoton/npcx/npcx9/npcx9-miwus-wui-map.dtsi
+++ b/dts/arm/nuvoton/npcx/npcx9/npcx9-miwus-wui-map.dtsi
@@ -13,12 +13,21 @@
 	npcx-miwus-wui-map {
 		compatible = "nuvoton,npcx-miwu-wui-map";
 
-		/* MIWU table 1 */
+		/* MIWU table 0 */
 		/* MIWU group A */
 		wui_cr_sin2: wui0-1-6-2 {
 			miwus = <&miwu0 0 6>; /* CR_SIN2 */
 		};
 
+		/* MIWU group D */
+		wui_smb0_2: wui0-4-3 {
+			miwus = <&miwu0 3 3>; /* SMB0/2 */
+		};
+		wui_smb1_3: wui0-4-4 {
+			miwus = <&miwu0 3 4>; /* SMB1/3 */
+		};
+
+		/* MIWU table 1 */
 		/* MIWU group G */
 		wui_io66: wui1-7-6 {
 			miwus = <&miwu1 6 6>; /* GPIO66 */
diff --git a/dts/arm/nuvoton/npcx9m7fb.dtsi b/dts/arm/nuvoton/npcx9m7fb.dtsi
index 7c17ff09934..176bf52b7d1 100644
--- a/dts/arm/nuvoton/npcx9m7fb.dtsi
+++ b/dts/arm/nuvoton/npcx9m7fb.dtsi
@@ -16,13 +16,14 @@
 		reg = <0x64000000 DT_SIZE_K(512)>;
 	};
 
-	sram0: memory@200c0000 {
+	sram0: memory@200b0000 {
 		compatible = "mmio-sram";
 		reg = <0x200B0000 DT_SIZE_K(128)>;
 	};
 
 	soc-id {
 		device-id = <0x62>;
+		revision-reg = <0x00017FFC 4>;
 	};
 };
 
diff --git a/dts/arm/nxp/nxp_imx95_m7.dtsi b/dts/arm/nxp/nxp_imx95_m7.dtsi
index 6006c2e905e..1597a9b83b1 100644
--- a/dts/arm/nxp/nxp_imx95_m7.dtsi
+++ b/dts/arm/nxp/nxp_imx95_m7.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,6 +7,7 @@
 #include <arm/armv7-m.dtsi>
 #include <zephyr/dt-bindings/clock/imx95_clock.h>
 #include <dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
 #include <mem.h>
 
 / {
@@ -49,6 +50,12 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 
+			scmi_devpd: protocol@11 {
+				compatible = "arm,scmi-power";
+				reg = <0x11>;
+				#power-domain-cells = <1>;
+			};
+
 			scmi_clk: protocol@14 {
 				compatible = "arm,scmi-clock";
 				reg = <0x14>;
@@ -63,6 +70,11 @@
 					compatible = "nxp,imx95-pinctrl", "nxp,imx93-pinctrl";
 				};
 			};
+
+			scmi_cpu: protocol@82 {
+				compatible = "nxp,scmi-cpu";
+				reg = <0x82>;
+			};
 		};
 	};
 
@@ -77,6 +89,51 @@
 			reg = <0x20000000 DT_SIZE_K(256)>;
 		};
 
+		gpio1: gpio@47400000 {
+			compatible = "nxp,imx-rgpio";
+			reg = <0x47400000 DT_SIZE_K(64)>;
+			interrupts = <10 0>, <11 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+		};
+
+		gpio2: gpio@43810000 {
+			compatible = "nxp,imx-rgpio";
+			reg = <0x43810000 DT_SIZE_K(64)>;
+			interrupts = <49 0>, <50 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <32>;
+		};
+
+		gpio3: gpio@43820000 {
+			compatible = "nxp,imx-rgpio";
+			reg = <0x43820000 DT_SIZE_K(64)>;
+			interrupts = <51 0>, <52 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <32>;
+		};
+
+		gpio4: gpio@43840000 {
+			compatible = "nxp,imx-rgpio";
+			reg = <0x43840000 DT_SIZE_K(64)>;
+			interrupts = <53 0>, <54 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <30>;
+		};
+
+		gpio5: gpio@43850000 {
+			compatible = "nxp,imx-rgpio";
+			reg = <0x43850000 DT_SIZE_K(64)>;
+			interrupts = <55 0>, <56 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <18>;
+		};
+
 		edma2: dma@42000000 {
 			compatible = "nxp,edma";
 			reg = <0x42000000 (DT_SIZE_K(64) * 33)>;
@@ -148,6 +205,30 @@
 			status = "disabled";
 		};
 
+		lpspi3: spi@42550000 {
+			compatible = "nxp,lpspi";
+			reg = <0x42550000 0x4000>;
+			interrupts = <61 3>;
+			clocks = <&scmi_clk IMX95_CLK_LPSPI3>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <16>;
+			rx-fifo-size = <16>;
+		};
+
+		lpspi4: spi@42560000 {
+			compatible = "nxp,lpspi";
+			reg = <0x42560000 0x4000>;
+			interrupts = <62 3>;
+			clocks = <&scmi_clk IMX95_CLK_LPSPI4>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <16>;
+			rx-fifo-size = <16>;
+		};
+
 		lpuart3: serial@42570000 {
 			compatible = "nxp,imx-lpuart", "nxp,lpuart";
 			reg = <0x42570000 DT_SIZE_K(64)>;
@@ -253,6 +334,54 @@
 			status = "disabled";
 		};
 
+		lpspi5: spi@426f0000 {
+			compatible = "nxp,lpspi";
+			reg = <0x426f0000 0x4000>;
+			interrupts = <177 3>;
+			clocks = <&scmi_clk IMX95_CLK_LPSPI5>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <16>;
+			rx-fifo-size = <16>;
+		};
+
+		lpspi6: spi@42700000 {
+			compatible = "nxp,lpspi";
+			reg = <0x42700000 0x4000>;
+			interrupts = <178 3>;
+			clocks = <&scmi_clk IMX95_CLK_LPSPI6>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <16>;
+			rx-fifo-size = <16>;
+		};
+
+		lpspi7: spi@42710000 {
+			compatible = "nxp,lpspi";
+			reg = <0x42710000 0x4000>;
+			interrupts = <179 3>;
+			clocks = <&scmi_clk IMX95_CLK_LPSPI7>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <16>;
+			rx-fifo-size = <16>;
+		};
+
+		lpspi8: spi@42720000 {
+			compatible = "nxp,lpspi";
+			reg = <0x42720000 0x4000>;
+			interrupts = <180 3>;
+			clocks = <&scmi_clk IMX95_CLK_LPSPI8>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <16>;
+			rx-fifo-size = <16>;
+		};
+
 		tpm1: pwm@44310000 {
 			compatible = "nxp,kinetis-tpm";
 			reg = <0x44310000 0x88>;
@@ -295,6 +424,30 @@
 			status = "disabled";
 		};
 
+		lpspi1: spi@44360000 {
+			compatible = "nxp,lpspi";
+			reg = <0x44360000 0x4000>;
+			interrupts = <16 3>;
+			clocks = <&scmi_clk IMX95_CLK_LPSPI1>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <16>;
+			rx-fifo-size = <16>;
+		};
+
+		lpspi2: spi@44370000 {
+			compatible = "nxp,lpspi";
+			reg = <0x44370000 0x4000>;
+			interrupts = <17 3>;
+			clocks = <&scmi_clk IMX95_CLK_LPSPI2>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <16>;
+			rx-fifo-size = <16>;
+		};
+
 		lpuart1: serial@44380000 {
 			compatible = "nxp,imx-lpuart", "nxp,lpuart";
 			reg = <0x44380000 DT_SIZE_K(64)>;
@@ -317,9 +470,218 @@
 			interrupts = <205 0>;
 			#mbox-cells = <1>;
 		};
+
+		mu7: mailbox@42440000 {
+			compatible = "nxp,mbox-imx-mu";
+			reg = <0x42440000 DT_SIZE_K(4)>;
+			interrupts = <207 0>;
+			#mbox-cells = <1>;
+			status = "disabled";
+		};
+
+		irqsteer: interrupt-controller@44680000 {
+			compatible = "nxp,irqsteer-intc";
+			reg = <0x44680000 DT_SIZE_K(64)>;
+
+			#size-cells = <0>;
+			#address-cells = <1>;
+
+			irqsteer_master0: interrupt-controller@0 {
+				compatible = "nxp,irqsteer-master";
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				interrupts-extended = <&nvic 224 0>;
+			};
+		};
+
+		netc: ethernet@4ca00000 {
+			reg = <0x4ca00000 0x1000000>;
+			interrupt-parent = <&irqsteer_master0>;
+			interrupts = <13 0 0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges;
+
+			emdio: mdio@4cce0000 {
+				compatible = "nxp,imx-netc-emdio";
+				reg = <0x4cce0000 0x1c44>;
+				clocks = <&scmi_clk IMX95_CLK_ENET>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+
+			enetc_psi0: ethernet@4cc00000 {
+				compatible = "nxp,imx-netc-psi";
+				reg = <0x4cc00000 0x10000>;
+				mac-index = <0>;
+				si-index = <0>;
+				status = "disabled";
+			};
+
+			enetc_psi1: ethernet@4cc40000 {
+				compatible = "nxp,imx-netc-psi";
+				reg = <0x4cc40000 0x10000>;
+				mac-index = <1>;
+				si-index = <1>;
+				status = "disabled";
+			};
+
+			enetc_psi2: ethernet@4cc80000 {
+				compatible = "nxp,imx-netc-psi";
+				reg = <0x4cc80000 0x10000>;
+				mac-index = <2>;
+				si-index = <2>;
+				status = "disabled";
+			};
+		};
 	};
 };
 
 &nvic {
 	arm,num-irq-priority-bits = <4>;
 };
+
+&gpio1 {
+	pinmux = <&iomuxc_i2c1_scl_gpio_io_bit_gpio1_io_bit0>,
+		<&iomuxc_i2c1_sda_gpio_io_bit_gpio1_io_bit1>,
+		<&iomuxc_i2c2_scl_gpio_io_bit_gpio1_io_bit2>,
+		<&iomuxc_i2c2_sda_gpio_io_bit_gpio1_io_bit3>,
+		<&iomuxc_uart1_rxd_gpio_io_bit_gpio1_io_bit4>,
+		<&iomuxc_uart1_txd_gpio_io_bit_gpio1_io_bit5>,
+		<&iomuxc_uart2_rxd_gpio_io_bit_gpio1_io_bit6>,
+		<&iomuxc_uart2_txd_gpio_io_bit_gpio1_io_bit7>,
+		<&iomuxc_pdm_clk_gpio_io_bit_gpio1_io_bit8>,
+		<&iomuxc_pdm_bit_stream0_gpio_io_bit_gpio1_io_bit9>,
+		<&iomuxc_pdm_bit_stream1_gpio_io_bit_gpio1_io_bit10>,
+		<&iomuxc_sai1_txfs_gpio_io_bit_gpio1_io_bit11>,
+		<&iomuxc_sai1_txc_gpio_io_bit_gpio1_io_bit12>,
+		<&iomuxc_sai1_txd0_gpio_io_bit_gpio1_io_bit13>,
+		<&iomuxc_sai1_rxd0_gpio_io_bit_gpio1_io_bit14>,
+		<&iomuxc_wdog_any_gpio_io_bit_gpio1_io_bit15>;
+};
+
+&gpio2 {
+	pinmux = <&iomuxc_gpio_io00_gpio_io_bit_gpio2_io_bit0>,
+		<&iomuxc_gpio_io01_gpio_io_bit_gpio2_io_bit1>,
+		<&iomuxc_gpio_io02_gpio_io_bit_gpio2_io_bit2>,
+		<&iomuxc_gpio_io03_gpio_io_bit_gpio2_io_bit3>,
+		<&iomuxc_gpio_io04_gpio_io_bit_gpio2_io_bit4>,
+		<&iomuxc_gpio_io05_gpio_io_bit_gpio2_io_bit5>,
+		<&iomuxc_gpio_io06_gpio_io_bit_gpio2_io_bit6>,
+		<&iomuxc_gpio_io07_gpio_io_bit_gpio2_io_bit7>,
+		<&iomuxc_gpio_io08_gpio_io_bit_gpio2_io_bit8>,
+		<&iomuxc_gpio_io09_gpio_io_bit_gpio2_io_bit9>,
+		<&iomuxc_gpio_io10_gpio_io_bit_gpio2_io_bit10>,
+		<&iomuxc_gpio_io11_gpio_io_bit_gpio2_io_bit11>,
+		<&iomuxc_gpio_io12_gpio_io_bit_gpio2_io_bit12>,
+		<&iomuxc_gpio_io13_gpio_io_bit_gpio2_io_bit13>,
+		<&iomuxc_gpio_io14_gpio_io_bit_gpio2_io_bit14>,
+		<&iomuxc_gpio_io15_gpio_io_bit_gpio2_io_bit15>,
+		<&iomuxc_gpio_io16_gpio_io_bit_gpio2_io_bit16>,
+		<&iomuxc_gpio_io17_gpio_io_bit_gpio2_io_bit17>,
+		<&iomuxc_gpio_io18_gpio_io_bit_gpio2_io_bit18>,
+		<&iomuxc_gpio_io19_gpio_io_bit_gpio2_io_bit19>,
+		<&iomuxc_gpio_io20_gpio_io_bit_gpio2_io_bit20>,
+		<&iomuxc_gpio_io21_gpio_io_bit_gpio2_io_bit21>,
+		<&iomuxc_gpio_io22_gpio_io_bit_gpio2_io_bit22>,
+		<&iomuxc_gpio_io23_gpio_io_bit_gpio2_io_bit23>,
+		<&iomuxc_gpio_io24_gpio_io_bit_gpio2_io_bit24>,
+		<&iomuxc_gpio_io25_gpio_io_bit_gpio2_io_bit25>,
+		<&iomuxc_gpio_io26_gpio_io_bit_gpio2_io_bit26>,
+		<&iomuxc_gpio_io27_gpio_io_bit_gpio2_io_bit27>,
+		<&iomuxc_gpio_io28_gpio_io_bit_gpio2_io_bit28>,
+		<&iomuxc_gpio_io29_gpio_io_bit_gpio2_io_bit29>,
+		<&iomuxc_gpio_io30_gpio_io_bit_gpio2_io_bit30>,
+		<&iomuxc_gpio_io31_gpio_io_bit_gpio2_io_bit31>;
+};
+
+&gpio3 {
+	pinmux = <&iomuxc_sd2_cd_b_gpio_io_bit_gpio3_io_bit0>,
+		<&iomuxc_sd2_clk_gpio_io_bit_gpio3_io_bit1>,
+		<&iomuxc_sd2_cmd_gpio_io_bit_gpio3_io_bit2>,
+		<&iomuxc_sd2_data0_gpio_io_bit_gpio3_io_bit3>,
+		<&iomuxc_sd2_data1_gpio_io_bit_gpio3_io_bit4>,
+		<&iomuxc_sd2_data2_gpio_io_bit_gpio3_io_bit5>,
+		<&iomuxc_sd2_data3_gpio_io_bit_gpio3_io_bit6>,
+		<&iomuxc_sd2_reset_b_gpio_io_bit_gpio3_io_bit7>,
+		<&iomuxc_sd1_clk_gpio_io_bit_gpio3_io_bit8>,
+		<&iomuxc_sd1_cmd_gpio_io_bit_gpio3_io_bit9>,
+		<&iomuxc_sd1_data0_gpio_io_bit_gpio3_io_bit10>,
+		<&iomuxc_sd1_data1_gpio_io_bit_gpio3_io_bit11>,
+		<&iomuxc_sd1_data2_gpio_io_bit_gpio3_io_bit12>,
+		<&iomuxc_sd1_data3_gpio_io_bit_gpio3_io_bit13>,
+		<&iomuxc_sd1_data4_gpio_io_bit_gpio3_io_bit14>,
+		<&iomuxc_sd1_data5_gpio_io_bit_gpio3_io_bit15>,
+		<&iomuxc_sd1_data6_gpio_io_bit_gpio3_io_bit16>,
+		<&iomuxc_sd1_data7_gpio_io_bit_gpio3_io_bit17>,
+		<&iomuxc_sd1_strobe_gpio_io_bit_gpio3_io_bit18>,
+		<&iomuxc_sd2_vselect_gpio_io_bit_gpio3_io_bit19>,
+		<&iomuxc_sd3_clk_gpio_io_bit_gpio3_io_bit20>,
+		<&iomuxc_sd3_cmd_gpio_io_bit_gpio3_io_bit21>,
+		<&iomuxc_sd3_data0_gpio_io_bit_gpio3_io_bit22>,
+		<&iomuxc_sd3_data1_gpio_io_bit_gpio3_io_bit23>,
+		<&iomuxc_sd3_data2_gpio_io_bit_gpio3_io_bit24>,
+		<&iomuxc_sd3_data3_gpio_io_bit_gpio3_io_bit25>,
+		<&iomuxc_ccm_clko1_gpio_io_bit_gpio3_io_bit26>,
+		<&iomuxc_ccm_clko2_gpio_io_bit_gpio3_io_bit27>,
+		<&iomuxc_dap_tdi_gpio_io_bit_gpio3_io_bit28>,
+		<&iomuxc_dap_tms_swdio_gpio_io_bit_gpio3_io_bit29>,
+		<&iomuxc_dap_tclk_swclk_gpio_io_bit_gpio3_io_bit30>,
+		<&iomuxc_dap_tdo_traceswo_gpio_io_bit_gpio3_io_bit31>;
+};
+
+&gpio4 {
+	pinmux = <&iomuxc_enet1_mdc_gpio_io_bit_gpio4_io_bit0>,
+		<&iomuxc_enet1_mdio_gpio_io_bit_gpio4_io_bit1>,
+		<&iomuxc_enet1_td3_gpio_io_bit_gpio4_io_bit2>,
+		<&iomuxc_enet1_td2_gpio_io_bit_gpio4_io_bit3>,
+		<&iomuxc_enet1_td1_gpio_io_bit_gpio4_io_bit4>,
+		<&iomuxc_enet1_td0_gpio_io_bit_gpio4_io_bit5>,
+		<&iomuxc_enet1_tx_ctl_gpio_io_bit_gpio4_io_bit6>,
+		<&iomuxc_enet1_txc_gpio_io_bit_gpio4_io_bit7>,
+		<&iomuxc_enet1_rx_ctl_gpio_io_bit_gpio4_io_bit8>,
+		<&iomuxc_enet1_rxc_gpio_io_bit_gpio4_io_bit9>,
+		<&iomuxc_enet1_rd0_gpio_io_bit_gpio4_io_bit10>,
+		<&iomuxc_enet1_rd1_gpio_io_bit_gpio4_io_bit11>,
+		<&iomuxc_enet1_rd2_gpio_io_bit_gpio4_io_bit12>,
+		<&iomuxc_enet1_rd3_gpio_io_bit_gpio4_io_bit13>,
+		<&iomuxc_enet2_mdc_gpio_io_bit_gpio4_io_bit14>,
+		<&iomuxc_enet2_mdio_gpio_io_bit_gpio4_io_bit15>,
+		<&iomuxc_enet2_td3_gpio_io_bit_gpio4_io_bit16>,
+		<&iomuxc_enet2_td2_gpio_io_bit_gpio4_io_bit17>,
+		<&iomuxc_enet2_td1_gpio_io_bit_gpio4_io_bit18>,
+		<&iomuxc_enet2_td0_gpio_io_bit_gpio4_io_bit19>,
+		<&iomuxc_enet2_tx_ctl_gpio_io_bit_gpio4_io_bit20>,
+		<&iomuxc_enet2_txc_gpio_io_bit_gpio4_io_bit21>,
+		<&iomuxc_enet2_rx_ctl_gpio_io_bit_gpio4_io_bit22>,
+		<&iomuxc_enet2_rxc_gpio_io_bit_gpio4_io_bit23>,
+		<&iomuxc_enet2_rd0_gpio_io_bit_gpio4_io_bit24>,
+		<&iomuxc_enet2_rd1_gpio_io_bit_gpio4_io_bit25>,
+		<&iomuxc_enet2_rd2_gpio_io_bit_gpio4_io_bit26>,
+		<&iomuxc_enet2_rd3_gpio_io_bit_gpio4_io_bit27>,
+		<&iomuxc_ccm_clko3_gpio_io_bit_gpio4_io_bit28>,
+		<&iomuxc_ccm_clko4_gpio_io_bit_gpio4_io_bit29>;
+};
+
+&gpio5 {
+	pinmux = <&iomuxc_xspi1_data0_gpio_io_bit_gpio5_io_bit0>,
+		<&iomuxc_xspi1_data1_gpio_io_bit_gpio5_io_bit1>,
+		<&iomuxc_xspi1_data2_gpio_io_bit_gpio5_io_bit2>,
+		<&iomuxc_xspi1_data3_gpio_io_bit_gpio5_io_bit3>,
+		<&iomuxc_xspi1_data4_gpio_io_bit_gpio5_io_bit4>,
+		<&iomuxc_xspi1_data5_gpio_io_bit_gpio5_io_bit5>,
+		<&iomuxc_xspi1_data6_gpio_io_bit_gpio5_io_bit6>,
+		<&iomuxc_xspi1_data7_gpio_io_bit_gpio5_io_bit7>,
+		<&iomuxc_xspi1_dqs_gpio_io_bit_gpio5_io_bit8>,
+		<&iomuxc_xspi1_sclk_gpio_io_bit_gpio5_io_bit9>,
+		<&iomuxc_xspi1_ss0_b_gpio_io_bit_gpio5_io_bit10>,
+		<&iomuxc_xspi1_ss1_b_gpio_io_bit_gpio5_io_bit11>,
+		<&iomuxc_gpio_io32_gpio_io_bit_gpio5_io_bit12>,
+		<&iomuxc_gpio_io33_gpio_io_bit_gpio5_io_bit13>,
+		<&iomuxc_gpio_io34_gpio_io_bit_gpio5_io_bit14>,
+		<&iomuxc_gpio_io35_gpio_io_bit_gpio5_io_bit15>,
+		<&iomuxc_gpio_io36_gpio_io_bit_gpio5_io_bit16>,
+		<&iomuxc_gpio_io37_gpio_io_bit_gpio5_io_bit17>;
+};
diff --git a/dts/arm/nxp/nxp_ke1xf.dtsi b/dts/arm/nxp/nxp_ke1xf.dtsi
index 848d1e53198..db596879032 100644
--- a/dts/arm/nxp/nxp_ke1xf.dtsi
+++ b/dts/arm/nxp/nxp_ke1xf.dtsi
@@ -387,6 +387,8 @@
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <4>;
+			rx-fifo-size = <4>;
 		};
 
 		lpspi1: spi@4002d000 {
@@ -397,6 +399,8 @@
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <4>;
+			rx-fifo-size = <4>;
 		};
 
 		flexcan0: can@40024000 {
diff --git a/dts/arm/nxp/nxp_ke1xz.dtsi b/dts/arm/nxp/nxp_ke1xz.dtsi
index 7aea4135ebb..fe6b93c2876 100644
--- a/dts/arm/nxp/nxp_ke1xz.dtsi
+++ b/dts/arm/nxp/nxp_ke1xz.dtsi
@@ -429,6 +429,8 @@
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <4>;
+			rx-fifo-size = <4>;
 		};
 
 		lpspi1: spi@4002d000 {
@@ -439,6 +441,8 @@
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <4>;
+			rx-fifo-size = <4>;
 		};
 
 		edma: dma-controller@40008000 {
diff --git a/dts/arm/nxp/nxp_lpc55S2x.dtsi b/dts/arm/nxp/nxp_lpc55S2x.dtsi
index 22177cfe8e5..d7525a4ef2a 100644
--- a/dts/arm/nxp/nxp_lpc55S2x.dtsi
+++ b/dts/arm/nxp/nxp_lpc55S2x.dtsi
@@ -34,3 +34,12 @@
 &iap {
 	status = "okay";
 };
+
+/*
+ * lpc55S_2x:
+ * Combine SRAM0, SRAM1, SRAM2 for total of 192K RAM
+ */
+&sram0 {
+	compatible = "mmio-sram";
+	reg = <0x20000000 DT_SIZE_K(192)>;
+};
diff --git a/dts/arm/nxp/nxp_lpc55S2x_common.dtsi b/dts/arm/nxp/nxp_lpc55S2x_common.dtsi
index 184c2feeadd..ca2670dbef8 100644
--- a/dts/arm/nxp/nxp_lpc55S2x_common.dtsi
+++ b/dts/arm/nxp/nxp_lpc55S2x_common.dtsi
@@ -46,8 +46,9 @@
 	#size-cells = <1>;
 
 	sramx: memory@4000000 {
-		compatible = "mmio-sram";
+		compatible = "zephyr,memory-region", "mmio-sram";
 		reg = <0x4000000 DT_SIZE_K(32)>;
+		zephyr,memory-region = "SRAMX";
 	};
 
 	sram0: memory@20000000 {
@@ -56,17 +57,16 @@
 	};
 
 	sram1: memory@20010000 {
-		compatible = "zephyr,memory-region", "mmio-sram";
+		compatible = "mmio-sram";
 		reg = <0x20010000 DT_SIZE_K(64)>;
-		zephyr,memory-region = "SRAM1";
 	};
 
 	sram2: memory@20020000 {
-		compatible = "zephyr,memory-region", "mmio-sram";
+		compatible = "mmio-sram";
 		reg = <0x20020000 DT_SIZE_K(64)>;
-		zephyr,memory-region = "SRAM2";
 	};
 
+	/* SRAM 4 is used by PowerQuad when enabled */
 	sram4: memory@20040000 {
 		compatible = "zephyr,memory-region", "mmio-sram";
 		reg = <0x20040000 DT_SIZE_K(16)>;
diff --git a/dts/arm/nxp/nxp_lpc55S3x_common.dtsi b/dts/arm/nxp/nxp_lpc55S3x_common.dtsi
index 5fc7eeeaed1..ef68f22b390 100644
--- a/dts/arm/nxp/nxp_lpc55S3x_common.dtsi
+++ b/dts/arm/nxp/nxp_lpc55S3x_common.dtsi
@@ -41,8 +41,9 @@
 	 * LPC55x36: RAMX: 16K, SRAM0: 16K, SRAM1: 16K, SRAM2: 32K, SRAM3: 32K, SRAM4: 16K
 	 */
 	sramx: memory@4000000 {
-		compatible = "mmio-sram";
+		compatible = "zephyr,memory-region", "mmio-sram";
 		reg = <0x04000000 DT_SIZE_K(16)>;
+		zephyr,memory-region = "SRAMX";
 	};
 	sram0: memory@20000000 {
 		compatible = "mmio-sram";
diff --git a/dts/arm/nxp/nxp_mcxa153.dtsi b/dts/arm/nxp/nxp_mcxa153.dtsi
new file mode 100644
index 00000000000..d1d2c42f0fa
--- /dev/null
+++ b/dts/arm/nxp/nxp_mcxa153.dtsi
@@ -0,0 +1,222 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-m.dtsi>
+#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-m33f";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+	};
+
+	/* Dummy pinctrl node, filled with pin mux options at board level */
+	pinctrl: pinctrl {
+		compatible = "nxp,port-pinctrl";
+		status = "okay";
+	};
+
+	soc {
+		edma0: dma-controller@40080000 {
+			#dma-cells = <2>;
+			compatible = "nxp,mcux-edma";
+			nxp,version = <4>;
+			dma-channels = <4>;
+			dma-requests = <66>;
+
+			reg = <0x40080000 0x1000>;
+			interrupts = <2 0>, <3 0>, <4 0>, <5 0>;
+			no-error-irq;
+			status = "disabled";
+		};
+
+		flexpwm0: flexpwm@400a9000 {
+			compatible = "nxp,flexpwm";
+			reg = <0x400a9000 0x1000>;
+			interrupt-names = "RELOAD-ERROR", "FAULT";
+			interrupts = <44 0>, <45 0>;
+			flexpwm0_pwm0: pwm0 {
+				compatible = "nxp,imx-pwm";
+				index = <0>;
+				interrupts = <46 0>;
+				#pwm-cells = <3>;
+				clocks = <&syscon MCUX_BUS_CLK>;
+				nxp,prescaler = <128>;
+				status = "disabled";
+				run-in-wait;
+			};
+
+			flexpwm0_pwm1: pwm1 {
+				compatible = "nxp,imx-pwm";
+				index = <1>;
+				interrupts = <47 0>;
+				#pwm-cells = <3>;
+				clocks = <&syscon MCUX_BUS_CLK>;
+				nxp,prescaler = <128>;
+				status = "disabled";
+				run-in-wait;
+			};
+
+			flexpwm0_pwm2: pwm2 {
+				compatible = "nxp,imx-pwm";
+				index = <2>;
+				interrupts = <48 0>;
+				#pwm-cells = <3>;
+				clocks = <&syscon MCUX_BUS_CLK>;
+				nxp,prescaler = <128>;
+				status = "disabled";
+				run-in-wait;
+			};
+		};
+
+		fmu: flash-controller@40095000 {
+			compatible = "nxp,msf1";
+			reg = <0x40095000 0x1000>;
+			interrupts = <12 0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash: flash@0 {
+				compatible = "soc-nv-flash";
+				reg = <0 DT_SIZE_K(128)>;
+				erase-block-size = <8192>;
+				write-block-size = <128>;
+			};
+		};
+
+		gpio0: gpio@40102000 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x40102000 0x1000>;
+			interrupts = <71 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&porta>;
+		};
+
+		gpio1: gpio@40103000 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x40103000 0x1000>;
+			interrupts = <72 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&portb>;
+		};
+
+		gpio2: gpio@40104000 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x40104000 0x1000>;
+			interrupts = <73 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&portc>;
+		};
+
+		gpio3: gpio@40105000 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x40105000 0x1000>;
+			interrupts = <74 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&portd>;
+		};
+
+		lpuart0: lpuart@4009f000 {
+			compatible = "nxp,lpuart";
+			status = "disabled";
+			reg = <0x4009f000 0x1000>;
+			interrupts = <31 0>;
+			clocks = <&syscon MCUX_LPUART0_CLK>;
+			/* DMA channels 0 and 1, muxed to LPUART0 RX and TX */
+			dmas = <&edma0 0 21>, <&edma0 1 22>;
+			dma-names = "rx", "tx";
+		};
+
+		lpuart1: lpuart@400a0000 {
+			compatible = "nxp,lpuart";
+			status = "disabled";
+			reg = <0x400a0000 0x1000>;
+			interrupts = <32 0>;
+			clocks = <&syscon MCUX_LPUART1_CLK>;
+			/* DMA channels 2 and 3, muxed to LPUART1 RX and TX */
+			dmas = <&edma0 2 23>, <&edma0 3 24>;
+			dma-names = "rx", "tx";
+		};
+
+		lpuart2: lpuart@400a1000 {
+			compatible = "nxp,lpuart";
+			status = "disabled";
+			reg = <0x400a1000 0x1000>;
+			interrupts = <33 0>;
+			clocks = <&syscon MCUX_LPUART2_CLK>;
+			/* DMA channels 2 and 3, muxed to LPUART2 RX and TX */
+			dmas = <&edma0 2 25>, <&edma0 3 26>;
+			dma-names = "rx", "tx";
+		};
+
+		porta: pinmux@400bc000 {
+			compatible = "nxp,port-pinmux";
+			reg = <0x400bc000 0x1000>;
+			clocks = <&syscon MCUX_PORT0_CLK>;
+		};
+
+		portb: pinmux@400bd000 {
+			compatible = "nxp,port-pinmux";
+			reg = <0x400bd000 0x1000>;
+			clocks = <&syscon MCUX_PORT1_CLK>;
+		};
+
+		portc: pinmux@400be000 {
+			compatible = "nxp,port-pinmux";
+			reg = <0x400be000 0x1000>;
+			clocks = <&syscon MCUX_PORT2_CLK>;
+		};
+
+		portd: pinmux@400bf000 {
+			compatible = "nxp,port-pinmux";
+			reg = <0x400bf000 0x1000>;
+			clocks = <&syscon MCUX_PORT3_CLK>;
+		};
+
+		sramx: memory@4000000 {
+			compatible = "mmio-sram";
+			reg = <0x4000000 DT_SIZE_K(8)>;
+		};
+
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(24)>;
+		};
+
+		syscon: syscon@40091000 {
+			compatible = "nxp,lpc-syscon";
+			reg = <0x40091000 0x4000>;
+			#clock-cells = <1>;
+
+			reset: reset {
+				compatible = "nxp,lpc-syscon-reset";
+				#reset-cells = <1>;
+			};
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};
diff --git a/dts/arm/nxp/nxp_mcxa156.dtsi b/dts/arm/nxp/nxp_mcxa156.dtsi
index 946433c2b7e..248adc0379d 100644
--- a/dts/arm/nxp/nxp_mcxa156.dtsi
+++ b/dts/arm/nxp/nxp_mcxa156.dtsi
@@ -309,9 +309,9 @@
 			};
 		};
 
-		flexpwm1: flexpwm@d0000 {
+		flexpwm1: flexpwm@400aa000 {
 			compatible = "nxp,flexpwm";
-			reg = <0xd0000 0x1000>;
+			reg = <0x400aa000 0x1000>;
 			interrupt-names = "RELOAD-ERROR", "FAULT";
 			interrupts = <79 0>, <80 0>;
 			flexpwm1_pwm0: pwm0 {
@@ -348,6 +348,19 @@
 			};
 		};
 
+		i3c0: i3c@40002000 {
+			compatible = "nxp,mcux-i3c";
+			reg = <0x40002000 0x1000>;
+			interrupts = <24 0>;
+			clocks = <&syscon MCUX_I3C_CLK>;
+			clk-divider = <4>;
+			clk-divider-slow = <1>;
+			clk-divider-tc = <1>;
+			status = "disabled";
+			#address-cells = <3>;
+			#size-cells = <0>;
+		};
+
 		lpadc0: lpadc@400af000 {
 			compatible = "nxp,lpc-lpadc";
 			reg = <0x400af000 0x1000>;
@@ -440,6 +453,30 @@
 			status = "disabled";
 		};
 
+		lpspi0: spi@4009c000 {
+			compatible = "nxp,lpspi";
+			reg = <0x4009c000 0x1000>;
+			interrupts = <28 0>;
+			clocks = <&syscon MCUX_LPSPI0_CLK>;
+			tx-fifo-size = <4>;
+			rx-fifo-size = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		lpspi1: spi@4009d000 {
+			compatible = "nxp,lpspi";
+			reg = <0x4009d000 0x1000>;
+			interrupts = <29 0>;
+			clocks = <&syscon MCUX_LPSPI1_CLK>;
+			tx-fifo-size = <4>;
+			rx-fifo-size = <4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		lptmr0: lptmr@400ab000 {
 			compatible = "nxp,lptmr";
 			reg = <0x400ab000 0x1000>;
diff --git a/dts/arm/nxp/nxp_mcxa166.dtsi b/dts/arm/nxp/nxp_mcxa166.dtsi
new file mode 100644
index 00000000000..11c1618991e
--- /dev/null
+++ b/dts/arm/nxp/nxp_mcxa166.dtsi
@@ -0,0 +1,230 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-m.dtsi>
+#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-m33f";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+	};
+
+	/* Dummy pinctrl node, filled with pin mux options at board level */
+	pinctrl: pinctrl {
+		compatible = "nxp,port-pinctrl";
+		status = "okay";
+	};
+
+	soc {
+		syscon: syscon@40091000 {
+			compatible = "nxp,lpc-syscon";
+			reg = <0x40091000 0x4000>;
+			#clock-cells = <1>;
+
+			reset: reset {
+				compatible = "nxp,lpc-syscon-reset";
+				#reset-cells = <1>;
+			};
+		};
+
+		sramx: memory@4000000 {
+			compatible = "mmio-sram";
+			reg = <0x4000000 DT_SIZE_K(8)>;
+		};
+
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(240)>;
+		};
+
+		porta: pinmux@400bc000 {
+			compatible = "nxp,port-pinmux";
+			reg = <0x400bc000 0x1000>;
+			clocks = <&syscon MCUX_PORT0_CLK>;
+		};
+
+		portb: pinmux@400bd000 {
+			compatible = "nxp,port-pinmux";
+			reg = <0x400bd000 0x1000>;
+			clocks = <&syscon MCUX_PORT1_CLK>;
+		};
+
+		portc: pinmux@400be000 {
+			compatible = "nxp,port-pinmux";
+			reg = <0x400be000 0x1000>;
+			clocks = <&syscon MCUX_PORT2_CLK>;
+		};
+
+		portd: pinmux@400bf000 {
+			compatible = "nxp,port-pinmux";
+			reg = <0x400bf000 0x1000>;
+			clocks = <&syscon MCUX_PORT3_CLK>;
+		};
+
+		porte: pinmux@400c0000 {
+			compatible = "nxp,port-pinmux";
+			reg = <0x400c0000 0x1000>;
+			clocks = <&syscon MCUX_PORT4_CLK>;
+		};
+
+		gpio0: gpio@40102000 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x40102000 0x1000>;
+			interrupts = <71 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&porta>;
+		};
+
+		gpio1: gpio@40103000 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x40103000 0x1000>;
+			interrupts = <72 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&portb>;
+		};
+
+		gpio2: gpio@40104000 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x40104000 0x1000>;
+			interrupts = <73 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&portc>;
+		};
+
+		gpio3: gpio@40105000 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x40105000 0x1000>;
+			interrupts = <74 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&portd>;
+		};
+
+		gpio4: gpio@40106000 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x40106000 0x1000>;
+			interrupts = <75 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&porte>;
+		};
+
+		lpuart0: lpuart@4009f000 {
+			compatible = "nxp,lpuart";
+			status = "disabled";
+			reg = <0x4009f000 0x1000>;
+			interrupts = <31 0>;
+			clocks = <&syscon MCUX_LPUART0_CLK>;
+			/* DMA channels 0 and 1 muxed to LPUART0 RX and TX */
+			dmas = <&edma0 0 21>, <&edma0 1 22>;
+			dma-names = "rx", "tx";
+		};
+
+		lpuart1: lpuart@4009a000 {
+			compatible = "nxp,lpuart";
+			status = "disabled";
+			reg = <0x4009a000 0x1000>;
+			interrupts = <32 0>;
+			clocks = <&syscon MCUX_LPUART1_CLK>;
+			/* DMA channels 2 and 3 muxed to LPUART1 RX and TX */
+			dmas = <&edma0 2 23>, <&edma0 3 24>;
+			dma-names = "rx", "tx";
+		};
+
+		lpuart2: lpuart@400a1000 {
+			compatible = "nxp,lpuart";
+			status = "disabled";
+			reg = <0x400a1000 0x1000>;
+			interrupts = <33 0>;
+			clocks = <&syscon MCUX_LPUART2_CLK>;
+			/* DMA channels 4 and 5, muxed to LPUART2 RX and TX */
+			dmas = <&edma0 4 25>, <&edma0 5 26>;
+			dma-names = "rx", "tx";
+		};
+
+		lpuart3: lpuart@400a2000 {
+			compatible = "nxp,lpuart";
+			status = "disabled";
+			reg = <0x400a2000 0x1000>;
+			interrupts = <34 0>;
+			clocks = <&syscon MCUX_LPUART3_CLK>;
+			/* DMA channels 2 and 3, muxed to LPUART3 RX and TX */
+			dmas = <&edma0 6 27>, <&edma0 7 28>;
+			dma-names = "rx", "tx";
+		};
+
+		lpuart4: lpuart@400a3000 {
+			compatible = "nxp,lpuart";
+			status = "disabled";
+			reg = <0x400a3000 0x1000>;
+			interrupts = <34 0>;
+			clocks = <&syscon MCUX_LPUART4_CLK>;
+			/* DMA channels 0 and 1 muxed to LPUART4 RX and TX */
+			dmas = <&edma0 0 29>, <&edma0 1 30>;
+			dma-names = "rx", "tx";
+		};
+
+		fmu: flash-controller@40095000 {
+			compatible = "nxp,msf1";
+			reg = <0x40095000 0x1000>;
+			interrupts = <12 0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash: flash@0 {
+				compatible = "soc-nv-flash";
+				reg = <0 DT_SIZE_M(1)>;
+				erase-block-size = <8192>;
+				write-block-size = <128>;
+			};
+		};
+
+		edma0: dma-controller@40080000 {
+			#dma-cells = <2>;
+			compatible = "nxp,mcux-edma";
+			nxp,version = <4>;
+			dma-channels = <8>;
+			dma-requests = <131>;
+
+			reg = <0x40080000 0x1000>;
+			interrupts = <2 0>, <3 0>, <4 0>, <5 0>,
+				<6 0>, <7 0>, <8 0>, <9 0>;
+			no-error-irq;
+			status = "disabled";
+		};
+
+		wwdt0: watchdog@4000c000 {
+			compatible = "nxp,lpc-wwdt";
+			reg = <0x4000c000 0x1000>;
+			interrupts = <60 0>;
+			status = "disabled";
+			clk-divider = <1>;
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};
diff --git a/dts/arm/nxp/nxp_mcxa276.dtsi b/dts/arm/nxp/nxp_mcxa276.dtsi
new file mode 100644
index 00000000000..11c1618991e
--- /dev/null
+++ b/dts/arm/nxp/nxp_mcxa276.dtsi
@@ -0,0 +1,230 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-m.dtsi>
+#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-m33f";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+		};
+	};
+
+	/* Dummy pinctrl node, filled with pin mux options at board level */
+	pinctrl: pinctrl {
+		compatible = "nxp,port-pinctrl";
+		status = "okay";
+	};
+
+	soc {
+		syscon: syscon@40091000 {
+			compatible = "nxp,lpc-syscon";
+			reg = <0x40091000 0x4000>;
+			#clock-cells = <1>;
+
+			reset: reset {
+				compatible = "nxp,lpc-syscon-reset";
+				#reset-cells = <1>;
+			};
+		};
+
+		sramx: memory@4000000 {
+			compatible = "mmio-sram";
+			reg = <0x4000000 DT_SIZE_K(8)>;
+		};
+
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(240)>;
+		};
+
+		porta: pinmux@400bc000 {
+			compatible = "nxp,port-pinmux";
+			reg = <0x400bc000 0x1000>;
+			clocks = <&syscon MCUX_PORT0_CLK>;
+		};
+
+		portb: pinmux@400bd000 {
+			compatible = "nxp,port-pinmux";
+			reg = <0x400bd000 0x1000>;
+			clocks = <&syscon MCUX_PORT1_CLK>;
+		};
+
+		portc: pinmux@400be000 {
+			compatible = "nxp,port-pinmux";
+			reg = <0x400be000 0x1000>;
+			clocks = <&syscon MCUX_PORT2_CLK>;
+		};
+
+		portd: pinmux@400bf000 {
+			compatible = "nxp,port-pinmux";
+			reg = <0x400bf000 0x1000>;
+			clocks = <&syscon MCUX_PORT3_CLK>;
+		};
+
+		porte: pinmux@400c0000 {
+			compatible = "nxp,port-pinmux";
+			reg = <0x400c0000 0x1000>;
+			clocks = <&syscon MCUX_PORT4_CLK>;
+		};
+
+		gpio0: gpio@40102000 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x40102000 0x1000>;
+			interrupts = <71 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&porta>;
+		};
+
+		gpio1: gpio@40103000 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x40103000 0x1000>;
+			interrupts = <72 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&portb>;
+		};
+
+		gpio2: gpio@40104000 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x40104000 0x1000>;
+			interrupts = <73 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&portc>;
+		};
+
+		gpio3: gpio@40105000 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x40105000 0x1000>;
+			interrupts = <74 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&portd>;
+		};
+
+		gpio4: gpio@40106000 {
+			compatible = "nxp,kinetis-gpio";
+			status = "disabled";
+			reg = <0x40106000 0x1000>;
+			interrupts = <75 0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			nxp,kinetis-port = <&porte>;
+		};
+
+		lpuart0: lpuart@4009f000 {
+			compatible = "nxp,lpuart";
+			status = "disabled";
+			reg = <0x4009f000 0x1000>;
+			interrupts = <31 0>;
+			clocks = <&syscon MCUX_LPUART0_CLK>;
+			/* DMA channels 0 and 1 muxed to LPUART0 RX and TX */
+			dmas = <&edma0 0 21>, <&edma0 1 22>;
+			dma-names = "rx", "tx";
+		};
+
+		lpuart1: lpuart@4009a000 {
+			compatible = "nxp,lpuart";
+			status = "disabled";
+			reg = <0x4009a000 0x1000>;
+			interrupts = <32 0>;
+			clocks = <&syscon MCUX_LPUART1_CLK>;
+			/* DMA channels 2 and 3 muxed to LPUART1 RX and TX */
+			dmas = <&edma0 2 23>, <&edma0 3 24>;
+			dma-names = "rx", "tx";
+		};
+
+		lpuart2: lpuart@400a1000 {
+			compatible = "nxp,lpuart";
+			status = "disabled";
+			reg = <0x400a1000 0x1000>;
+			interrupts = <33 0>;
+			clocks = <&syscon MCUX_LPUART2_CLK>;
+			/* DMA channels 4 and 5, muxed to LPUART2 RX and TX */
+			dmas = <&edma0 4 25>, <&edma0 5 26>;
+			dma-names = "rx", "tx";
+		};
+
+		lpuart3: lpuart@400a2000 {
+			compatible = "nxp,lpuart";
+			status = "disabled";
+			reg = <0x400a2000 0x1000>;
+			interrupts = <34 0>;
+			clocks = <&syscon MCUX_LPUART3_CLK>;
+			/* DMA channels 2 and 3, muxed to LPUART3 RX and TX */
+			dmas = <&edma0 6 27>, <&edma0 7 28>;
+			dma-names = "rx", "tx";
+		};
+
+		lpuart4: lpuart@400a3000 {
+			compatible = "nxp,lpuart";
+			status = "disabled";
+			reg = <0x400a3000 0x1000>;
+			interrupts = <34 0>;
+			clocks = <&syscon MCUX_LPUART4_CLK>;
+			/* DMA channels 0 and 1 muxed to LPUART4 RX and TX */
+			dmas = <&edma0 0 29>, <&edma0 1 30>;
+			dma-names = "rx", "tx";
+		};
+
+		fmu: flash-controller@40095000 {
+			compatible = "nxp,msf1";
+			reg = <0x40095000 0x1000>;
+			interrupts = <12 0>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash: flash@0 {
+				compatible = "soc-nv-flash";
+				reg = <0 DT_SIZE_M(1)>;
+				erase-block-size = <8192>;
+				write-block-size = <128>;
+			};
+		};
+
+		edma0: dma-controller@40080000 {
+			#dma-cells = <2>;
+			compatible = "nxp,mcux-edma";
+			nxp,version = <4>;
+			dma-channels = <8>;
+			dma-requests = <131>;
+
+			reg = <0x40080000 0x1000>;
+			interrupts = <2 0>, <3 0>, <4 0>, <5 0>,
+				<6 0>, <7 0>, <8 0>, <9 0>;
+			no-error-irq;
+			status = "disabled";
+		};
+
+		wwdt0: watchdog@4000c000 {
+			compatible = "nxp,lpc-wwdt";
+			reg = <0x4000c000 0x1000>;
+			interrupts = <60 0>;
+			status = "disabled";
+			clk-divider = <1>;
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};
diff --git a/dts/arm/nxp/nxp_mcxc141.dtsi b/dts/arm/nxp/nxp_mcxc141.dtsi
index a8918a521e7..7518beaa471 100644
--- a/dts/arm/nxp/nxp_mcxc141.dtsi
+++ b/dts/arm/nxp/nxp_mcxc141.dtsi
@@ -7,7 +7,7 @@
 #include <nxp/nxp_mcxc_common.dtsi>
 
 &sram0 {
-	reg = <0x1FFFF000 DT_SIZE_K(8)>;
+	reg = <0x1FFFF800 DT_SIZE_K(8)>;
 };
 
 &flash0 {
diff --git a/dts/arm/nxp/nxp_mcxn23x_common.dtsi b/dts/arm/nxp/nxp_mcxn23x_common.dtsi
index c892dd567ec..69732818ddb 100644
--- a/dts/arm/nxp/nxp_mcxn23x_common.dtsi
+++ b/dts/arm/nxp/nxp_mcxn23x_common.dtsi
@@ -192,6 +192,8 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			status = "disabled";
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
 		};
 		flexcomm0_lpi2c0: lpi2c@92800 {
 			compatible = "nxp,lpi2c";
@@ -231,6 +233,8 @@
 			/* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */
 			dmas = <&edma0 0 71>, <&edma0 1 72>;
 			dma-names = "rx", "tx";
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
 			status = "disabled";
 		};
 		flexcomm1_lpi2c1: lpi2c@93800 {
@@ -271,6 +275,8 @@
 			/* DMA channels 4 and 5, muxed to LPSPI2 RX and TX */
 			dmas = <&edma0 4 73>, <&edma0 5 74>;
 			dma-names = "rx", "tx";
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
 			status = "disabled";
 		};
 		flexcomm2_lpi2c2: lpi2c@94800 {
@@ -305,6 +311,8 @@
 			clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
 			status = "disabled";
 		};
 		flexcomm3_lpi2c3: lpi2c@95800 {
@@ -345,6 +353,8 @@
 			/* DMA channels 2 and 3, muxed to LPSPI4 RX and TX */
 			dmas = <&edma0 2 77>, <&edma0 3 78>;
 			dma-names = "rx", "tx";
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
 			status = "disabled";
 		};
 		flexcomm4_lpi2c4: lpi2c@b4800 {
@@ -379,6 +389,8 @@
 			clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
 			status = "disabled";
 		};
 		flexcomm5_lpi2c5: lpi2c@b5800 {
@@ -413,6 +425,8 @@
 			clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
 			status = "disabled";
 		};
 		flexcomm6_lpi2c6: lpi2c@b6800 {
@@ -447,6 +461,8 @@
 			clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
 			status = "disabled";
 		};
 		flexcomm7_lpi2c7: lpi2c@b7800 {
diff --git a/dts/arm/nxp/nxp_mcxn94x_common.dtsi b/dts/arm/nxp/nxp_mcxn94x_common.dtsi
index 587efc88993..c4c1a1ec3be 100644
--- a/dts/arm/nxp/nxp_mcxn94x_common.dtsi
+++ b/dts/arm/nxp/nxp_mcxn94x_common.dtsi
@@ -47,13 +47,13 @@
 	sramx: memory@4000000 {
 		compatible =  "zephyr,memory-region", "mmio-sram";
 		reg = <0x4000000 DT_SIZE_K(96)>;
-		zephyr,memory-region = "SRAM1";
+		zephyr,memory-region = "SRAMX";
 		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
 	};
 
 	/* mcxn94x Memory configurations:
 	 *
-	 * RAM blocks RAMA through SRAM4 are contiguous address ranges
+	 * RAM blocks RAMA through RAMH are contiguous address ranges
 	 *
 	 * MCXN94X: 512KB RAM, RAMX: 96K, RAMA: 32K, RAMB: 32K,
 	 *                     RAMC: 64K, RAMD: 64K, RAME: 64K
@@ -198,6 +198,8 @@
 			clocks = <&syscon MCUX_FLEXCOMM0_CLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
 			status = "disabled";
 		};
 		flexcomm0_lpi2c0: lpi2c@92800 {
@@ -238,6 +240,8 @@
 			/* DMA channels 0 and 1, muxed to LPSPI1 RX and TX */
 			dmas = <&edma0 0 71>, <&edma0 1 72>;
 			dma-names = "rx", "tx";
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
 			status = "disabled";
 		};
 		flexcomm1_lpi2c1: lpi2c@93800 {
@@ -278,6 +282,8 @@
 			/* DMA channels 4 and 5, muxed to LPSPI2 RX and TX */
 			dmas = <&edma0 4 73>, <&edma0 5 74>;
 			dma-names = "rx", "tx";
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
 			status = "disabled";
 		};
 		flexcomm2_lpi2c2: lpi2c@94800 {
@@ -312,6 +318,8 @@
 			clocks = <&syscon MCUX_FLEXCOMM3_CLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
 			status = "disabled";
 		};
 		flexcomm3_lpi2c3: lpi2c@95800 {
@@ -352,6 +360,8 @@
 			/* DMA channels 2 and 3, muxed to LPSPI4 RX and TX */
 			dmas = <&edma0 2 77>, <&edma0 3 78>;
 			dma-names = "rx", "tx";
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
 			status = "disabled";
 		};
 		flexcomm4_lpi2c4: lpi2c@b4800 {
@@ -386,6 +396,8 @@
 			clocks = <&syscon MCUX_FLEXCOMM5_CLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
 			status = "disabled";
 		};
 		flexcomm5_lpi2c5: lpi2c@b5800 {
@@ -420,6 +432,8 @@
 			clocks = <&syscon MCUX_FLEXCOMM6_CLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
 			status = "disabled";
 		};
 		flexcomm6_lpi2c6: lpi2c@b6800 {
@@ -454,6 +468,8 @@
 			clocks = <&syscon MCUX_FLEXCOMM7_CLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
 			status = "disabled";
 		};
 		flexcomm7_lpi2c7: lpi2c@b7800 {
@@ -488,6 +504,8 @@
 			clocks = <&syscon MCUX_FLEXCOMM8_CLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
 			status = "disabled";
 		};
 		flexcomm8_lpi2c8: lpi2c@b8800 {
@@ -522,6 +540,8 @@
 			clocks = <&syscon MCUX_FLEXCOMM9_CLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
 			status = "disabled";
 		};
 		flexcomm9_lpi2c9: lpi2c@b9800 {
@@ -534,6 +554,15 @@
 		};
 	};
 
+	mbox: mbox@b2000 {
+		compatible = "nxp,mbox-mailbox";
+		reg = <0xb2000 0xec>;
+		interrupts = <54 0>;
+		rx-channels = <4>;
+		#mbox-cells = <1>;
+		status = "disabled";
+	};
+
 	edma0: dma-controller@80000 {
 		#dma-cells = <2>;
 		compatible = "nxp,mcux-edma";
@@ -871,6 +900,16 @@
 		clocks = <&syscon MCUX_LPADC2_CLK>;
 	};
 
+	usb0: usbd@dd000 {
+		compatible = "nxp,kinetis-usbd";
+		reg = <0xdd000 0x1000>;
+		interrupts = <50 1>;
+		interrupt-names = "usbfs0";
+		num-bidir-endpoints = <16>;
+		no-voltage-regulator;
+		status = "disabled";
+	};
+
 	usb1: usbd@10b000 {
 		compatible = "nxp,ehci";
 		reg = <0x10b000 0x1000>;
@@ -1031,6 +1070,39 @@
 		clock-src = <0>;
 		alarms-count = <1>;
 	};
+
+	sai0: sai@106000 {
+		compatible = "nxp,mcux-i2s";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#pinmux-cells = <2>;
+		reg = < 0x106000 0x1000>;
+		clocks = <&syscon MCUX_SAI0_CLK>;
+		pinmuxes = <&sai0 0x100 0x40000000>;
+		interrupts = <59 0>;
+		dmas = <&edma0 0 99>, <&edma0 0 100>;
+		dma-names = "rx", "tx";
+		nxp,tx-channel = <1>;
+		nxp,tx-dma-channel = <0>;
+		nxp,rx-dma-channel = <1>;
+		status = "disabled";
+	};
+	sai1: sai@107000 {
+		compatible = "nxp,mcux-i2s";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#pinmux-cells = <2>;
+		reg = < 0x107000 0x1000>;
+		clocks = <&syscon MCUX_SAI1_CLK>;
+		pinmuxes = <&sai1 0x100 0x40000000>;
+		interrupts = <60 0>;
+		dmas = <&edma0 0 101>, <&edma0 0 102>;
+		dma-names = "rx", "tx";
+		nxp,tx-channel = <1>;
+		nxp,tx-dma-channel = <2>;
+		nxp,rx-dma-channel = <3>;
+		status = "disabled";
+	};
 };
 
 &systick {
diff --git a/dts/arm/nxp/nxp_mcxw71.dtsi b/dts/arm/nxp/nxp_mcxw71.dtsi
index 590f5cd6ca0..ba0d6e263b7 100644
--- a/dts/arm/nxp/nxp_mcxw71.dtsi
+++ b/dts/arm/nxp/nxp_mcxw71.dtsi
@@ -1,389 +1,66 @@
 /*
- * Copyright 2023-2024 NXP
+ * Copyright 2023-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <mem.h>
-#include <arm/armv8-m.dtsi>
-#include <zephyr/dt-bindings/clock/scg_k4.h>
-#include <zephyr/dt-bindings/gpio/gpio.h>
-#include <zephyr/dt-bindings/pwm/pwm.h>
-#include <zephyr/dt-bindings/i2c/i2c.h>
-#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#include "nxp_mcxw7x_common.dtsi"
 
-/ {
-	aliases {
-		watchdog0 = &wdog0;
-	};
-
-	chosen {
-		zephyr,bt-hci = &hci;
-		zephyr,nbu = &nbu;
-	};
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu0: cpu@0 {
-			compatible = "arm,cortex-m33f";
-			reg = <0>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			mpu: mpu@e000ed90 {
-				compatible = "arm,armv8m-mpu";
-				reg = <0xe000ed90 0x40>;
-			};
-		};
-	};
-
-	soc {
-		fmu: memory-controller@50020000 {
-			ranges = <0x0 0x10000000 DT_SIZE_M(1)>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			compatible = "nxp,msf1";
-			reg = <0x50020000 0x1000>;
-			interrupts = <27 0>;
-			status = "disabled";
-
-			flash: flash@0 {
-				reg = <0x0 DT_SIZE_M(1)>;
-				compatible = "soc-nv-flash";
-				write-block-size = <16>;
-				erase-block-size = <8192>;
-			};
-		};
-
-		ctcm: sram@14000000 {
-			ranges = <0x0 0x14000000 DT_SIZE_K(16)>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			ctcm0: code_memory@0 {
-				compatible = "mmio-sram";
-				reg = <0x0 DT_SIZE_K(16)>;
-			};
-		};
-
-		stcm: sram@30000000 {
-			ranges = <0x0 0x30000000 DT_SIZE_K(112)>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			stcm0: system_memory@0 {
-				compatible = "mmio-sram";
-				/* With only the first 64KB having ECC */
-				reg = <0x0 DT_SIZE_K(104)>;
-			};
-
-			stcm1: system_memory@1a000 {
-				compatible = "zephyr,memory-region","mmio-sram";
-				reg = <0x1a000 DT_SIZE_K(8)>;
-				zephyr,memory-region = "RetainedMem";
-			};
-		};
-
-		smu2: sram@489c0000 {
-			ranges = <0x0 0x489c0000 DT_SIZE_K(40)>;
-		};
-
-		peripheral: peripheral@50000000 {
-			ranges = <0x0 0x50000000 0x10000000>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			pbridge2: pbridge2@0 {
-				ranges = <>;
-				reg = <0x0 0x4b000>;
-				#address-cells = <1>;
-				#size-cells = <1>;
-			};
-
-			fast_peripheral0: fast_peripherals0@8000000 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				ranges = <0x0 0x8000000 0x40000>;
-			};
+&fmu {
+	ranges = <0x0 0x10000000 DT_SIZE_M(1)>;
+};
 
-			fast_peripheral1: fast_peripherals1@8800000 {
-				#address-cells = <1>;
-				#size-cells = <1>;
-				ranges = <0x0 0x8800000 0x210000>;
-			};
-		};
-	};
+&flash {
+	reg = <0x0 DT_SIZE_M(1)>;
+};
 
-	pinctrl: pinctrl {
-		compatible = "nxp,port-pinctrl";
-	};
+&ctcm {
+	ranges = <0x0 0x14000000 DT_SIZE_K(16)>;
 };
 
-&nvic {
-	arm,num-irq-priority-bits = <3>;
+&ctcm0 {
+	reg = <0x0 DT_SIZE_K(16)>;
 };
 
-&smu2 {
-	#address-cells = <1>;
-	#size-cells = <1>;
+&stcm {
+	ranges = <0x0 0x30000000 DT_SIZE_K(112)>;
 
-	rpmsgmem: memory@8800 {
+	stcm1: system_memory@1a000 {
 		compatible = "zephyr,memory-region","mmio-sram";
-		reg = <0x8800 DT_SIZE_K(6)>;
-		zephyr,memory-region = "rpmsg_sh_mem";
-		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
+		reg = <0x1a000 DT_SIZE_K(8)>;
+		zephyr,memory-region = "RetainedMem";
 	};
 };
 
-&pbridge2 {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	scg: clock-controller@1e000 {
-		compatible = "nxp,scg-k4";
-		reg = <0x1e000 0x404>;
-		#clock-cells = <2>;
-	};
-
-	porta: pinctrl@42000 {
-		compatible = "nxp,port-pinmux";
-		reg = <0x42000 0xe0>;
-		clocks = <&scg SCG_K4_SLOW_CLK 0x108>;
-	};
-
-	portb: pinctrl@43000 {
-		compatible = "nxp,port-pinmux";
-		reg = <0x43000 0xe0>;
-		clocks = <&scg SCG_K4_SLOW_CLK 0x10c>;
-	};
-
-	portc: pinctrl@44000 {
-		compatible = "nxp,port-pinmux";
-		reg = <0x44000 0xe0>;
-		clocks = <&scg SCG_K4_SLOW_CLK 0x110>;
-	};
-
-	portd: pinctrl@45000 {
-		compatible = "nxp,port-pinmux";
-		reg = <0x45000 0xe0>;
-		clocks = <&scg SCG_K4_SLOW_CLK 0>;
-	};
-
-	lpuart0: serial@38000 {
-		compatible = "nxp,lpuart";
-		reg = <0x38000 0x34>;
-		interrupts = <44 0>;
-		clocks = <&scg SCG_K4_FIRC_CLK 0xe0>;
-		status = "disabled";
-	};
-
-	lpuart1: serial@39000 {
-		compatible = "nxp,lpuart";
-		reg = <0x39000 0x34>;
-		interrupts = <45 0>;
-		clocks = <&scg SCG_K4_FIRC_CLK 0xe4>;
-		status = "disabled";
-	};
-
-	lpi2c0: i2c@33000 {
-		compatible = "nxp,lpi2c";
-		clock-frequency = <I2C_BITRATE_STANDARD>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x33000 0x200>;
-		interrupts = <39 0>;
-		clocks = <&scg SCG_K4_FIRC_CLK 0xe0>;
-		status = "disabled";
-	};
-
-	lpi2c1: i2c@34000 {
-		compatible = "nxp,lpi2c";
-		clock-frequency = <I2C_BITRATE_STANDARD>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		reg = <0x34000 0x200>;
-		interrupts = <40 0>;
-		clocks = <&scg SCG_K4_FIRC_CLK 0xe4>;
-		status = "disabled";
-	};
-
-	lpspi0: spi@36000 {
-		compatible = "nxp,lpspi";
-		reg = <0x36000 0x800>;
-		interrupts = <42 0>;
-		clocks = <&scg SCG_K4_FIRC_CLK 0xd8>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	lpspi1: spi@37000 {
-		compatible = "nxp,lpspi";
-		reg = <0x37000 0x800>;
-		interrupts = <43 0>;
-		clocks = <&scg SCG_K4_FIRC_CLK 0xdc>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-		status = "disabled";
-	};
-
-	gpiod: gpio@46000{
-		compatible = "nxp,kinetis-gpio";
-		status = "disabled";
-		gpio-controller;
-		#gpio-cells = <2>;
-		nxp,kinetis-port = <&portd>;
-		reg = <0x46000 0x128>;
-		interrupts = <65 0>, <66 0>;
-	};
-
-	vbat: vbat@2b000 {
-		reg = <0x2b000 0x400>;
-		interrupts = <74 0>;
-	};
-
-	tpm0: pwm@31000 {
-		compatible = "nxp,kinetis-tpm";
-		reg = <0x31000 0x100>;
-		interrupts = <37 0>;
-		clocks = <&scg SCG_K4_FIRC_CLK 0xc4>;
-		prescaler = <16>;
-		status = "disabled";
-		#pwm-cells = <3>;
-	};
-
-	tpm1: pwm@32000 {
-		compatible = "nxp,kinetis-tpm";
-		reg = <0x32000 0x100>;
-		interrupts = <38 0>;
-		clocks = <&scg SCG_K4_FIRC_CLK 0xc8>;
-		prescaler = <16>;
-		status = "disabled";
-		#pwm-cells = <3>;
-	};
-
-	wdog0: watchdog@1a000 {
-		compatible = "nxp,wdog32";
-		reg = <0x1a000 16>;
-		interrupts = <23 0>;
-		clocks = <&scg SCG_K4_SYSOSC_CLK 0x68>;
-		clk-source = <1>;
-		clk-divider = <256>;
-		status = "okay";
-	};
-
-	wdog1: watchdog@1b000 {
-		compatible = "nxp,wdog32";
-		reg = <0x1b000 16>;
-		interrupts = <24 0>;
-		clocks = <&scg SCG_K4_SYSOSC_CLK 0x6c>;
-		clk-source = <1>;
-		clk-divider = <256>;
-		status = "disabled";
-	};
-
-	lptmr0: timer@2d000 {
-		compatible = "nxp,lptmr";
-		reg = <0x2d000 0x10>;
-		interrupts = <34 0>;
-		clock-frequency = <32000>;
-		clk-source = <2>;
-		prescaler = <1>;
-		resolution = <32>;
-		status = "disabled";
-	};
-
-	lptmr1: timer@2e000 {
-		compatible = "nxp,lptmr";
-		reg = <0x2e000 0x10>;
-		interrupts = <35 0>;
-		clock-frequency = <32000>;
-		clk-source = <2>;
-		prescaler = <1>;
-		resolution = <32>;
-		status = "disabled";
-	};
-
-	nbu: nbu {
-		compatible = "nxp,nbu";
-		interrupts = <48 2>;
-		interrupt-names = "nbu_rx_int";
-	};
+&stcm0 {
+	/* With only the first 64KB having ECC */
+	reg = <0x0 DT_SIZE_K(104)>;
+};
 
-	hci: hci_ble {
-		compatible = "nxp,hci-ble";
-	};
+&pbridge2 {
+	reg = <0x0 0x4b000>;
+};
 
-	flexcan0: can@3b000 {
-		compatible = "nxp,flexcan";
-		reg = <0x3b000 0x3080>;
-		interrupts = <47 0>;
-		interrupt-names = "common";
-		clocks = <&scg SCG_K4_FIRC_CLK 0xec>;
-		clk-source = <2>;
-		status = "disabled";
-	};
+&porta {
+	reg = <0x42000 0xdc>;
+};
 
-	adc0: adc@47000 {
-		compatible = "nxp,lpc-lpadc";
-		reg = <0x47000 0x1000>;
-		interrupts = <71 0>;
-		clocks = <&scg SCG_K4_FIRC_CLK 0x11c>;
-		voltage-ref= <1>;
-		calibration-average = <128>;
-		/* pwrlvl 0 is slow speed low power, 1 is opposite */
-		power-level = <0>;
-		offset-value-a = <0>;
-		offset-value-b = <0>;
-		#io-channel-cells = <1>;
-		nxp,references = <&vref 1800>;
-		status = "disabled";
-	};
+&portb {
+	reg = <0x43000 0xdc>;
+};
 
-	vref: regulator@4a000 {
-		compatible = "nxp,vref";
-		regulator-name = "mcxw71-vref";
-		reg = <0x4a000 0x20>;
-		#nxp,reference-cells = <1>;
-		nxp,buffer-startup-delay-us = <400>;
-		nxp,bandgap-startup-time-us = <20>;
-		regulator-min-microvolt = <1000000>;
-		regulator-max-microvolt = <2100000>;
-		nxp,current-compensation-en;
-		status = "disabled";
-	};
+&portc {
+	reg = <0x44000 0xdc>;
 };
 
-&fast_peripheral0 {
-	gpioa: gpio@10000{
-		compatible = "nxp,kinetis-gpio";
-		status = "disabled";
-		gpio-controller;
-		#gpio-cells = <2>;
-		nxp,kinetis-port = <&porta>;
-		reg = <0x10000 0x128>;
-		interrupts = <59 0>, <60 0>;
-	};
+&portd {
+	reg = <0x45000 0xdc>;
+};
 
-	gpiob: gpio@20000{
-		compatible = "nxp,kinetis-gpio";
-		status = "disabled";
-		gpio-controller;
-		#gpio-cells = <2>;
-		nxp,kinetis-port = <&portb>;
-		reg = <0x20000 0x128>;
-		interrupts = <61 0>, <62 0>;
-	};
+&smu2 {
+	ranges = <0x0 0x1c0000 DT_SIZE_K(40)>;
+};
 
-	gpioc: gpio@30000{
-		compatible = "nxp,kinetis-gpio";
-		status = "disabled";
-		gpio-controller;
-		#gpio-cells = <2>;
-		nxp,kinetis-port = <&portc>;
-		reg = <0x30000 0x128>;
-		interrupts = <63 0>, <64 0>;
-	};
+&rtc {
+	reg = <0x4002c000 0x50>;
 };
diff --git a/dts/arm/nxp/nxp_mcxw72.dtsi b/dts/arm/nxp/nxp_mcxw72.dtsi
new file mode 100644
index 00000000000..80c0fe13788
--- /dev/null
+++ b/dts/arm/nxp/nxp_mcxw72.dtsi
@@ -0,0 +1,59 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "nxp_mcxw7x_common.dtsi"
+
+&fmu {
+	ranges = <0x0 0x10000000 DT_SIZE_M(2)>;
+};
+
+&flash {
+	reg = <0x0 DT_SIZE_M(2)>;
+};
+
+&ctcm {
+	ranges = <0x0 0x14000000 DT_SIZE_K(32)>;
+};
+
+&ctcm0 {
+	reg = <0x0 DT_SIZE_K(32)>;
+};
+
+&stcm {
+	ranges = <0x0 0x30000000 DT_SIZE_K(232)>;
+};
+
+&stcm0 {
+	reg = <0x0 DT_SIZE_K(232)>;
+};
+
+&pbridge2 {
+	reg = <0x0 0x54000>;
+};
+
+&porta {
+	reg = <0x42000 0xF0>;
+};
+
+&portb {
+	reg = <0x43000 0xF0>;
+};
+
+&portc {
+	reg = <0x44000 0xF0>;
+};
+
+&portd {
+	reg = <0x45000 0xF0>;
+};
+
+&smu2 {
+	ranges = <0x0 0x1c0000 DT_SIZE_K(80)>;
+};
+
+&rtc {
+	reg = <0x4002c000 0x60>;
+};
diff --git a/dts/arm/nxp/nxp_mcxw7x_common.dtsi b/dts/arm/nxp/nxp_mcxw7x_common.dtsi
new file mode 100644
index 00000000000..7e0a42c4057
--- /dev/null
+++ b/dts/arm/nxp/nxp_mcxw7x_common.dtsi
@@ -0,0 +1,392 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-m.dtsi>
+#include <zephyr/dt-bindings/clock/scg_k4.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/pwm/pwm.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	aliases {
+		watchdog0 = &wdog0;
+	};
+
+	chosen {
+		zephyr,bt-hci = &hci;
+		zephyr,ieee802154 = &ieee802154;
+		zephyr,entropy = &trng;
+		zephyr,nbu = &nbu;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-m33f";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	soc {
+		fmu: memory-controller@50020000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "nxp,msf1";
+			reg = <0x50020000 0x30>;
+			interrupts = <27 0>;
+			status = "disabled";
+
+			flash: flash@0 {
+				compatible = "soc-nv-flash";
+				write-block-size = <16>;
+				erase-block-size = <8192>;
+			};
+		};
+
+		ctcm: sram@14000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			ctcm0: code_memory@0 {
+				compatible = "mmio-sram";
+			};
+		};
+
+		stcm: sram@30000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			stcm0: system_memory@0 {
+				compatible = "mmio-sram";
+			};
+		};
+
+		peripheral: peripheral@50000000 {
+			ranges = <0x0 0x50000000 0x10000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			pbridge2: pbridge2@0 {
+				ranges = <>;
+				#address-cells = <1>;
+				#size-cells = <1>;
+			};
+
+			fast_peripheral0: fast_peripherals0@8000000 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0x8000000 0x40000>;
+			};
+
+			fast_peripheral1: fast_peripherals1@8800000 {
+				#address-cells = <1>;
+				#size-cells = <1>;
+				ranges = <0x0 0x8800000 0x20a000>;
+			};
+		};
+	};
+
+	pinctrl: pinctrl {
+		compatible = "nxp,port-pinctrl";
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};
+
+&pbridge2 {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	scg: clock-controller@1e000 {
+		compatible = "nxp,scg-k4";
+		reg = <0x1e000 0x404>;
+		#clock-cells = <2>;
+	};
+
+	porta: pinctrl@42000 {
+		compatible = "nxp,port-pinmux";
+		clocks = <&scg SCG_K4_SLOW_CLK 0x108>;
+	};
+
+	portb: pinctrl@43000 {
+		compatible = "nxp,port-pinmux";
+		clocks = <&scg SCG_K4_SLOW_CLK 0x10c>;
+	};
+
+	portc: pinctrl@44000 {
+		compatible = "nxp,port-pinmux";
+		clocks = <&scg SCG_K4_SLOW_CLK 0x110>;
+	};
+
+	portd: pinctrl@45000 {
+		compatible = "nxp,port-pinmux";
+		clocks = <&scg SCG_K4_SLOW_CLK 0>;
+	};
+
+	lpuart0: serial@38000 {
+		compatible = "nxp,lpuart";
+		reg = <0x38000 0x34>;
+		interrupts = <44 0>;
+		clocks = <&scg SCG_K4_FIRC_CLK 0xe0>;
+		status = "disabled";
+	};
+
+	lpuart1: serial@39000 {
+		compatible = "nxp,lpuart";
+		reg = <0x39000 0x34>;
+		interrupts = <45 0>;
+		clocks = <&scg SCG_K4_FIRC_CLK 0xe4>;
+		status = "disabled";
+	};
+
+	lpi2c0: i2c@33000 {
+		compatible = "nxp,lpi2c";
+		reg = <0x33000 0x17c>;
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <39 0>;
+		clocks = <&scg SCG_K4_FIRC_CLK 0xe0>;
+		status = "disabled";
+	};
+
+	lpi2c1: i2c@34000 {
+		compatible = "nxp,lpi2c";
+		reg = <0x34000 0x17c>;
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <40 0>;
+		clocks = <&scg SCG_K4_FIRC_CLK 0xe4>;
+		status = "disabled";
+	};
+
+	lpspi0: spi@36000 {
+		compatible = "nxp,lpspi";
+		reg = <0x36000 0x800>;
+		interrupts = <42 0>;
+		clocks = <&scg SCG_K4_FIRC_CLK 0xd8>;
+		tx-fifo-size = <8>;
+		rx-fifo-size = <8>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	lpspi1: spi@37000 {
+		compatible = "nxp,lpspi";
+		reg = <0x37000 0x800>;
+		interrupts = <43 0>;
+		clocks = <&scg SCG_K4_FIRC_CLK 0xdc>;
+		tx-fifo-size = <8>;
+		rx-fifo-size = <8>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	gpiod: gpio@46000{
+		compatible = "nxp,kinetis-gpio";
+		reg = <0x46000 0x128>;
+		interrupts = <65 0>, <66 0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		nxp,kinetis-port = <&portd>;
+		status = "disabled";
+	};
+
+	vbat: vbat@2b000 {
+		reg = <0x2b000 0x33c>;
+		interrupts = <74 0>;
+	};
+
+	tpm0: pwm@31000 {
+		compatible = "nxp,kinetis-tpm";
+		reg = <0x31000 0x88>;
+		interrupts = <37 0>;
+		clocks = <&scg SCG_K4_FIRC_CLK 0xc4>;
+		prescaler = <16>;
+		status = "disabled";
+		#pwm-cells = <3>;
+	};
+
+	tpm1: pwm@32000 {
+		compatible = "nxp,kinetis-tpm";
+		reg = <0x32000 0x88>;
+		interrupts = <38 0>;
+		clocks = <&scg SCG_K4_FIRC_CLK 0xc8>;
+		prescaler = <16>;
+		status = "disabled";
+		#pwm-cells = <3>;
+	};
+
+	wdog0: watchdog@1a000 {
+		compatible = "nxp,wdog32";
+		reg = <0x1a000 10>;
+		interrupts = <23 0>;
+		clocks = <&scg SCG_K4_SYSOSC_CLK 0x68>;
+		clk-source = <1>;
+		clk-divider = <256>;
+		status = "okay";
+	};
+
+	wdog1: watchdog@1b000 {
+		compatible = "nxp,wdog32";
+		reg = <0x1b000 10>;
+		interrupts = <24 0>;
+		clocks = <&scg SCG_K4_SYSOSC_CLK 0x6c>;
+		clk-source = <1>;
+		clk-divider = <256>;
+		status = "disabled";
+	};
+
+	lptmr0: timer@2d000 {
+		compatible = "nxp,lptmr";
+		reg = <0x2d000 0x10>;
+		interrupts = <34 0>;
+		clock-frequency = <32000>;
+		clk-source = <2>;
+		prescaler = <1>;
+		resolution = <32>;
+		status = "disabled";
+	};
+
+	lptmr1: timer@2e000 {
+		compatible = "nxp,lptmr";
+		reg = <0x2e000 0x10>;
+		interrupts = <35 0>;
+		clock-frequency = <32000>;
+		clk-source = <2>;
+		prescaler = <1>;
+		resolution = <32>;
+		status = "disabled";
+	};
+
+	nbu: nbu {
+		compatible = "nxp,nbu";
+		interrupts = <48 2>;
+		interrupt-names = "nbu_rx_int";
+	};
+
+	hci: hci_ble {
+		compatible = "nxp,hci-ble";
+	};
+
+	ieee802154: ieee802154 {
+		compatible = "nxp,mcxw-ieee802154";
+	};
+
+	trng: trng {
+		compatible = "nxp,ele-trng";
+	};
+
+	flexcan0: can@3b000 {
+		compatible = "nxp,flexcan";
+		reg = <0x3b000 0x3080>;
+		interrupts = <47 0>;
+		interrupt-names = "common";
+		clocks = <&scg SCG_K4_FIRC_CLK 0xec>;
+		clk-source = <2>;
+		status = "disabled";
+	};
+
+	adc0: adc@47000 {
+		compatible = "nxp,lpc-lpadc";
+		reg = <0x47000 0x584>;
+		interrupts = <71 0>;
+		clocks = <&scg SCG_K4_FIRC_CLK 0x11c>;
+		voltage-ref= <1>;
+		calibration-average = <128>;
+		/* pwrlvl 0 is slow speed low power, 1 is opposite */
+		power-level = <0>;
+		offset-value-a = <0>;
+		offset-value-b = <0>;
+		#io-channel-cells = <1>;
+		nxp,references = <&vref 1800>;
+		status = "disabled";
+	};
+
+	vref: regulator@4a000 {
+		compatible = "nxp,vref";
+		reg = <0x4a000 0x14>;
+		regulator-name = "mcxw71-vref";
+		#nxp,reference-cells = <1>;
+		nxp,buffer-startup-delay-us = <400>;
+		nxp,bandgap-startup-time-us = <20>;
+		regulator-min-microvolt = <1000000>;
+		regulator-max-microvolt = <2100000>;
+		nxp,current-compensation-en;
+		status = "disabled";
+	};
+
+	rtc: rtc@4002c000 {
+		compatible = "nxp,rtc";
+		status = "disabled";
+		interrupts = <32 0>, <33 0>;
+		interrupt-names = "alarm", "seconds";
+		clock-frequency = <32768>;
+		prescaler = <32768>;
+	};
+};
+
+&fast_peripheral0 {
+	gpioa: gpio@10000{
+		compatible = "nxp,kinetis-gpio";
+		status = "disabled";
+		gpio-controller;
+		#gpio-cells = <2>;
+		nxp,kinetis-port = <&porta>;
+		reg = <0x10000 0x128>;
+		interrupts = <59 0>, <60 0>;
+	};
+
+	gpiob: gpio@20000{
+		compatible = "nxp,kinetis-gpio";
+		status = "disabled";
+		gpio-controller;
+		#gpio-cells = <2>;
+		nxp,kinetis-port = <&portb>;
+		reg = <0x20000 0x128>;
+		interrupts = <61 0>, <62 0>;
+	};
+
+	gpioc: gpio@30000{
+		compatible = "nxp,kinetis-gpio";
+		status = "disabled";
+		gpio-controller;
+		#gpio-cells = <2>;
+		nxp,kinetis-port = <&portc>;
+		reg = <0x30000 0x128>;
+		interrupts = <63 0>, <64 0>;
+	};
+};
+
+&fast_peripheral1 {
+	smu2: smu2@1c0000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		rpmsgmem: memory@8800 {
+			compatible = "zephyr,memory-region","mmio-sram";
+			reg = <0x8800 DT_SIZE_K(6)>;
+			zephyr,memory-region = "rpmsg_sh_mem";
+			zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM) )>;
+		};
+	};
+};
diff --git a/dts/arm/nxp/nxp_rt1010.dtsi b/dts/arm/nxp/nxp_rt1010.dtsi
index 8433d92a7e2..9698024c209 100644
--- a/dts/arm/nxp/nxp_rt1010.dtsi
+++ b/dts/arm/nxp/nxp_rt1010.dtsi
@@ -8,11 +8,6 @@
 
 &flexram {
 	flexram,num-ram-banks = <4>;
-	/* default fuse */
-	flexram,bank-spec = <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_ITCM>;
 };
 
 &sysclk {
@@ -164,6 +159,8 @@
 			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <16>;
+			rx-fifo-size = <16>;
 		};
 
 		lpspi2: spi@40198000 {
@@ -174,6 +171,8 @@
 			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 2>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <16>;
+			rx-fifo-size = <16>;
 		};
 
 		/* Remove LPUART5-8, they don't exist on RT1010 */
diff --git a/dts/arm/nxp/nxp_rt1015.dtsi b/dts/arm/nxp/nxp_rt1015.dtsi
index c6bd1f59689..85087e0ea5a 100644
--- a/dts/arm/nxp/nxp_rt1015.dtsi
+++ b/dts/arm/nxp/nxp_rt1015.dtsi
@@ -12,11 +12,6 @@
 	/* Note: RT1015 has five flexram banks, but only 4 of the 5 can
 	 * be used at the same time, for a total of 128KB of RAM.
 	 */
-	flexram,bank-spec = <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_ITCM>;
 };
 
 &sysclk {
diff --git a/dts/arm/nxp/nxp_rt1020.dtsi b/dts/arm/nxp/nxp_rt1020.dtsi
index b42a17960fa..08f790cc426 100644
--- a/dts/arm/nxp/nxp_rt1020.dtsi
+++ b/dts/arm/nxp/nxp_rt1020.dtsi
@@ -9,15 +9,6 @@
 
 &flexram {
 	flexram,num-ram-banks = <8>;
-	/* default fuse */
-	flexram,bank-spec = <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_ITCM>,
-			     <FLEXRAM_ITCM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>;
 };
 
 &sysclk {
diff --git a/dts/arm/nxp/nxp_rt1024.dtsi b/dts/arm/nxp/nxp_rt1024.dtsi
index 62262bb2118..dfb20d9c72e 100644
--- a/dts/arm/nxp/nxp_rt1024.dtsi
+++ b/dts/arm/nxp/nxp_rt1024.dtsi
@@ -9,15 +9,6 @@
 
 &flexram {
 	flexram,num-ram-banks = <8>;
-	/* default fuse */
-	flexram,bank-spec = <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_ITCM>,
-			     <FLEXRAM_ITCM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>;
 };
 
 &sysclk {
diff --git a/dts/arm/nxp/nxp_rt1050.dtsi b/dts/arm/nxp/nxp_rt1050.dtsi
index 12e1c623bce..0751617f373 100644
--- a/dts/arm/nxp/nxp_rt1050.dtsi
+++ b/dts/arm/nxp/nxp_rt1050.dtsi
@@ -7,23 +7,6 @@
 
 &flexram {
 	flexram,num-ram-banks = <16>;
-	/* default fuse */
-	flexram,bank-spec = <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_ITCM>,
-			     <FLEXRAM_ITCM>,
-			     <FLEXRAM_ITCM>,
-			     <FLEXRAM_ITCM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>;
 };
 
 &ccm {
diff --git a/dts/arm/nxp/nxp_rt1060.dtsi b/dts/arm/nxp/nxp_rt1060.dtsi
index 8d308a27509..1e66b01614a 100644
--- a/dts/arm/nxp/nxp_rt1060.dtsi
+++ b/dts/arm/nxp/nxp_rt1060.dtsi
@@ -16,23 +16,6 @@
 	};
 
 	flexram,num-ram-banks = <16>;
-	/* default fuse */
-	flexram,bank-spec = <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_ITCM>,
-			     <FLEXRAM_ITCM>,
-			     <FLEXRAM_ITCM>,
-			     <FLEXRAM_ITCM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>;
 };
 
 &ccm {
@@ -57,7 +40,7 @@
 				interrupts = <152 0>;
 				interrupt-names = "COMMON";
 				nxp,mdio = <&enet2_mdio>;
-				nxp,ptp-clock = <&enet_ptp_clock>;
+				nxp,ptp-clock = <&enet2_ptp_clock>;
 				status = "disabled";
 			};
 			enet2_mdio: mdio {
diff --git a/dts/arm/nxp/nxp_rt1064.dtsi b/dts/arm/nxp/nxp_rt1064.dtsi
index 02ea70d40f9..fb3fccb01b4 100644
--- a/dts/arm/nxp/nxp_rt1064.dtsi
+++ b/dts/arm/nxp/nxp_rt1064.dtsi
@@ -9,23 +9,6 @@
 
 &flexram {
 	flexram,num-ram-banks = <16>;
-	/* default fuse */
-	flexram,bank-spec = <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_ITCM>,
-			     <FLEXRAM_ITCM>,
-			     <FLEXRAM_ITCM>,
-			     <FLEXRAM_ITCM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_DTCM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>,
-			     <FLEXRAM_OCRAM>;
 };
 
 &flexspi2 {
diff --git a/dts/arm/nxp/nxp_rt10xx.dtsi b/dts/arm/nxp/nxp_rt10xx.dtsi
index 849bbedcd64..80e5a1e7863 100644
--- a/dts/arm/nxp/nxp_rt10xx.dtsi
+++ b/dts/arm/nxp/nxp_rt10xx.dtsi
@@ -14,9 +14,12 @@
 #include <zephyr/dt-bindings/memory-controller/nxp,flexram.h>
 
 / {
+	aliases {
+		die-temp0 = &tempmon;
+	};
+
 	chosen {
 		zephyr,entropy = &trng;
-		die-temp0 = &tempmon;
 	};
 
 	cpus {
@@ -458,6 +461,8 @@
 			interrupts = <32 3>;
 			status = "disabled";
 			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 0>;
+			rx-fifo-size = <16>;
+			tx-fifo-size = <16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
@@ -468,6 +473,8 @@
 			interrupts = <33 3>;
 			status = "disabled";
 			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 2>;
+			rx-fifo-size = <16>;
+			tx-fifo-size = <16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
@@ -478,6 +485,8 @@
 			interrupts = <34 3>;
 			status = "disabled";
 			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 4>;
+			rx-fifo-size = <16>;
+			tx-fifo-size = <16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
@@ -488,6 +497,8 @@
 			interrupts = <35 3>;
 			status = "disabled";
 			clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 6>;
+			rx-fifo-size = <16>;
+			tx-fifo-size = <16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
@@ -885,14 +896,13 @@
 			dma-channels = <32>;
 			dma-requests = <128>;
 			nxp,mem2mem;
-			nxp,a_on;
+			nxp,a-on;
 			reg = <0x400E8000 0x4000>,
 				<0x400EC000 0x4000>;
 			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
 				<4 0>, <5 0>, <6 0>, <7 0>,
 				<8 0>, <9 0>, <10 0>, <11 0>,
-				<12 0>, <13 0>, <14 0>, <15 0>,
-				<16 0>;
+				<12 0>, <13 0>, <14 0>, <15 0>;
 			irq-shared-offset = <16>;
 			clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
 			status = "disabled";
diff --git a/dts/arm/nxp/nxp_rt118x.dtsi b/dts/arm/nxp/nxp_rt118x.dtsi
index ff536a4ce03..dc25cfb24ec 100644
--- a/dts/arm/nxp/nxp_rt118x.dtsi
+++ b/dts/arm/nxp/nxp_rt118x.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -11,6 +11,10 @@
 #include <zephyr/dt-bindings/pwm/pwm.h>
 
 / {
+	aliases {
+		watchdog0 = &rtwdog0;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -22,6 +26,7 @@
 
 			#address-cells = <1>;
 			#size-cells = <1>;
+			d-cache-line-size = <32>;
 
 			mpu: mpu@e000ed90 {
 				compatible = "arm,armv8m-mpu";
@@ -35,8 +40,21 @@
 
 			#address-cells = <1>;
 			#size-cells = <1>;
+			d-cache-line-size = <32>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv7m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
 		};
 	};
+
+	/* USB PLL */
+	usbclk: usbpll-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		#clock-cells = <0>;
+	};
 };
 
 &peripheral {
@@ -67,6 +85,12 @@
 		compatible = "nxp,imx-ccm-rev2";
 		reg = <0x4450000 0x4000>;
 		#clock-cells = <3>;
+
+		lpo: lpo32k {
+			compatible = "fixed-clock";
+			clock-frequency = <32000>;
+			#clock-cells = <0>;
+		};
 	};
 
 	lpuart1: uart@4380000 {
@@ -74,6 +98,8 @@
 		reg = <0x4380000 0x4000>;
 		interrupts = <19 0>;
 		clocks = <&ccm IMX_CCM_LPUART0102_CLK 0x7c 24>;
+		dmas = <&edma3 0 16>, <&edma3 1 17>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -82,6 +108,8 @@
 		reg = <0x4390000 0x4000>;
 		interrupts = <20 0>;
 		clocks = <&ccm IMX_CCM_LPUART0102_CLK 0x68 28>;
+		dmas = <&edma3 2 18>, <&edma3 3 19>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -90,6 +118,8 @@
 		reg = <0x2570000 0x4000>;
 		interrupts = <68 0>;
 		clocks = <&ccm IMX_CCM_LPUART0304_CLK 0x68 12>;
+		dmas = <&edma4 0 17>, <&edma4 1 18>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -98,6 +128,8 @@
 		reg = <0x2580000 0x4000>;
 		interrupts = <69 0>;
 		clocks = <&ccm IMX_CCM_LPUART0304_CLK 0x6c 24>;
+		dmas = <&edma4 2 19>, <&edma4 3 20>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -106,6 +138,8 @@
 		reg = <0x2590000 0x4000>;
 		interrupts = <70 0>;
 		clocks = <&ccm IMX_CCM_LPUART0506_CLK 0x74 2>;
+		dmas = <&edma4 4 21>, <&edma4 5 22>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -114,6 +148,8 @@
 		reg = <0x25A0000 0x4000>;
 		interrupts = <71 0>;
 		clocks = <&ccm IMX_CCM_LPUART0506_CLK 0x74 6>;
+		dmas = <&edma4 6 23>, <&edma4 7 24>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -122,6 +158,8 @@
 		reg = <0x4570000 0x4000>;
 		interrupts = <196 0>;
 		clocks = <&ccm IMX_CCM_LPUART0708_CLK 0x7c 26>;
+		dmas = <&edma3 4 29>, <&edma3 5 30>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -130,6 +168,8 @@
 		reg = <0x2DA0000 0x4000>;
 		interrupts = <197 0>;
 		clocks = <&ccm IMX_CCM_LPUART0708_CLK 0x80 14>;
+		dmas = <&edma4 8 178>, <&edma4 9 179>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -138,6 +178,8 @@
 		reg = <0x2D70000 0x4000>;
 		interrupts = <156 0>;
 		clocks = <&ccm IMX_CCM_LPUART0910_CLK 0x80 14>;
+		dmas = <&edma4 10 172>, <&edma4 11 173>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -146,6 +188,8 @@
 		reg = <0x2D80000 0x4000>;
 		interrupts = <157 0>;
 		clocks = <&ccm IMX_CCM_LPUART0910_CLK 0x80 14>;
+		dmas = <&edma4 12 174>, <&edma4 13 175>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -154,6 +198,8 @@
 		reg = <0x2D90000 0x4000>;
 		interrupts = <158 0>;
 		clocks = <&ccm IMX_CCM_LPUART1112_CLK 0x80 14>;
+		dmas = <&edma4 14 176>, <&edma4 15 177>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -162,6 +208,8 @@
 		reg = <0x4580000 0x4000>;
 		interrupts = <159 0>;
 		clocks = <&ccm IMX_CCM_LPUART1112_CLK 0x80 14>;
+		dmas = <&edma3 6 31>, <&edma3 7 32>;
+		dma-names = "tx", "rx";
 		status = "disabled";
 	};
 
@@ -589,6 +637,7 @@
 			reg = <0x60b40000 0x10000>;
 			mac-index = <1>;
 			si-index = <1>;
+			phy-connection-type = "internal";
 			status = "disabled";
 		};
 
@@ -600,6 +649,41 @@
 			#size-cells = <0>;
 			status = "disabled";
 		};
+
+		switch: dsa {
+			compatible = "nxp,netc-switch";
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			switch_port0: switch_port@0 {
+				reg = <0>;
+				status = "disabled";
+			};
+
+			switch_port1: switch_port@1 {
+				reg = <1>;
+				status = "disabled";
+			};
+
+			switch_port2: switch_port@2 {
+				reg = <2>;
+				status = "disabled";
+			};
+
+			switch_port3: switch_port@3 {
+				reg = <3>;
+				status = "disabled";
+			};
+
+			/* Internal port */
+			switch_port4: switch_port@4 {
+				reg = <4>;
+				ethernet = <&enetc_psi1>;
+				phy-connection-type = "internal";
+				status = "disabled";
+			};
+		};
 	};
 
 	flexcan1: can@43a0000 {
@@ -934,15 +1018,238 @@
 		#address-cells = <3>;
 		#size-cells = <0>;
 	};
-};
 
-&flexspi {
-		compatible = "nxp,imx-flexspi";
-		interrupts = <55 0>;
+	usdhc1: usdhc@2850000 {
+		compatible = "nxp,imx-usdhc";
+		reg = <0x2850000 0x4000>;
+		status = "disabled";
+		interrupts = <86 0>;
+		clocks = <&ccm IMX_CCM_USDHC1_CLK 0 0>;
+		max-current-330 = <1020>;
+		max-current-180 = <1020>;
+		max-bus-freq = <208000000>;
+		min-bus-freq = <400000>;
+	};
+
+	usdhc2: usdhc@2860000 {
+		compatible = "nxp,imx-usdhc";
+		reg = <0x2860000 0x4000>;
+		status = "disabled";
+		interrupts = <87 0>;
+		clocks = <&ccm IMX_CCM_USDHC2_CLK 0 0>;
+		max-current-330 = <1020>;
+		max-current-180 = <1020>;
+		max-bus-freq = <208000000>;
+		min-bus-freq = <400000>;
+	};
+
+	edma3: dma-controller@4000000 {
+		#dma-cells = <2>;
+		compatible = "nxp,mcux-edma";
+		nxp,version = <4>;
+		reg = <0x4000000 0x210000>;
+		dma-channels = <32>;
+		dma-requests = <39>;
+		no-error-irq;
+		interrupts = <95 0>, <96 0>, <97 0>,
+			<98 0>, <99 0>, <100 0>, <101 0>,
+			<102 0>, <103 0>, <104 0>, <105 0>,
+			<106 0>, <107 0>, <108 0>, <109 0>,
+			<110 0>, <111 0>, <112 0>, <113 0>,
+			<114 0>, <115 0>, <116 0>, <117 0>,
+			<118 0>, <119 0>, <120 0>, <121 0>,
+			<122 0>, <123 0>, <124 0>, <125 0>,
+			<126 0>, <94 0>;
+		status = "disabled";
+	};
+
+	edma4: dma-controller@2000000 {
+		#dma-cells = <2>;
+		compatible = "nxp,mcux-edma";
+		nxp,version = <4>;
+		dma-channels = <64>;
+		dma-requests = <222>;
+		reg = <0x2000000 0x4000>;
+		no-error-irq;
+		interrupts = <128 0>, <129 0>, <130 0>,
+			<131 0>, <132 0>, <133 0>, <134 0>,
+			<135 0>, <136 0>, <137 0>, <138 0>,
+			<139 0>, <140 0>, <141 0>, <142 0>,
+			<143 0>, <127 0>;
+		channels-shared-irq-mask = <0x00000003 0x00000003
+			 0x0000000C 0x0000000C 0x00000030 0x00000030
+			 0x000000C0 0x000000C0 0x00000300 0x00000300
+			 0x00000C00 0x00000C00 0x00003000 0x00003000
+			 0x0000C000 0x0000C000 0x00030000 0x00030000
+			 0x000C0000 0x000C0000 0x00300000 0x00300000
+			 0x00C00000 0x00C00000 0x03000000 0x03000000
+			 0x0C000000 0x0C000000 0x30000000 0x30000000
+			 0xC0000000 0xC0000000>;
+		status = "disabled";
+	};
+
+	lpspi1: spi@4360000 {
+		compatible = "nxp,lpspi";
+		reg = <0x4360000 0x4000>;
+		interrupts = <16 3>;
+		status = "disabled";
+		clocks = <&ccm IMX_CCM_LPSPI0102_CLK 0x6c 0>;
+		tx-fifo-size = <16>;
+		rx-fifo-size = <16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	lpspi2: spi@4370000 {
+		compatible = "nxp,lpspi";
+		reg = <0x4370000 0x4000>;
+		interrupts = <17 3>;
+		status = "disabled";
+		clocks = <&ccm IMX_CCM_LPSPI0102_CLK 0x6c 2>;
+		tx-fifo-size = <16>;
+		rx-fifo-size = <16>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+	};
+
+	lpspi3: spi@2550000 {
+		compatible = "nxp,lpspi";
+		reg = <0x2550000 0x4000>;
+		interrupts = <65 3>;
 		status = "disabled";
-		clocks = <&ccm IMX_CCM_FLEXSPI_CLK 0x0 0>;
+		clocks = <&ccm IMX_CCM_LPSPI0304_CLK 0x6c 4>;
+		tx-fifo-size = <16>;
+		rx-fifo-size = <16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	lpspi4: spi@2560000 {
+		compatible = "nxp,lpspi";
+		reg = <0x2560000 0x4000>;
+		interrupts = <66 3>;
+		status = "disabled";
+		clocks = <&ccm IMX_CCM_LPSPI0304_CLK 0x6c 6>;
+		tx-fifo-size = <16>;
+		rx-fifo-size = <16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	lpspi5: spi@2d50000 {
+		compatible = "nxp,lpspi";
+		reg = <0x2d50000 0x4000>;
+		interrupts = <194 3>;
+		status = "disabled";
+		clocks = <&ccm IMX_CCM_LPSPI0506_CLK 0x6c 6>;
+		tx-fifo-size = <16>;
+		rx-fifo-size = <16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	lpspi6: spi@2d60000 {
+		compatible = "nxp,lpspi";
+		reg = <0x2d60000 0x4000>;
+		interrupts = <195 3>;
+		status = "disabled";
+		clocks = <&ccm IMX_CCM_LPSPI0506_CLK 0x6c 6>;
+		tx-fifo-size = <16>;
+		rx-fifo-size = <16>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+
+	rtwdog0: wdog@42d0000 {
+		compatible = "nxp,rtwdog";
+		reg = <0x42d0000 0x10>;
+		status = "okay";
+		interrupts = <38 0>;
+		clocks = <&lpo>;
+		clk-source = <1>;
+		clk-divider = <1>;
+	};
+
+	rtwdog1: wdog@42e0000 {
+		compatible = "nxp,rtwdog";
+		reg = <0x42e0000 0x10>;
+		status = "disabled";
+		interrupts = <39 0>;
+		clocks = <&lpo>;
+		clk-source = <1>;
+		clk-divider = <1>;
+	};
+
+	rtwdog2: wdog@2490000 {
+		compatible = "nxp,rtwdog";
+		reg = <0x2490000 0x10>;
+		status = "disabled";
+		interrupts = <79 0>;
+		clocks = <&lpo>;
+		clk-source = <1>;
+		clk-divider = <1>;
+	};
+
+	rtwdog3: wdog@24a0000 {
+		compatible = "nxp,rtwdog";
+		reg = <0x24a0000 0x10>;
+		status = "disabled";
+		interrupts = <80 0>;
+		clocks = <&lpo>;
+		clk-source = <1>;
+		clk-divider = <1>;
+	};
+
+	rtwdog4: wdog@24b0000 {
+		compatible = "nxp,rtwdog";
+		reg = <0x24b0000 0x10>;
+		status = "disabled";
+		interrupts = <81 0>;
+		clocks = <&lpo>;
+		clk-source = <1>;
+		clk-divider = <1>;
+	};
+
+	usb1: usbd@2c80000 {
+		compatible = "nxp,ehci";
+		reg = <0x2c80000 0x1000>;
+		interrupts = <215 0>;
+		interrupt-names = "usb_otg";
+		clocks = <&usbclk>;
+		num-bidir-endpoints = <8>;
+		status = "disabled";
+	};
+
+	usb2: usbd@2c90000 {
+		compatible = "nxp,ehci";
+		reg = <0x2c90000 0x1000>;
+		interrupts = <214 0>;
+		interrupt-names = "usb_otg";
+		clocks = <&usbclk>;
+		num-bidir-endpoints = <8>;
+		status = "disabled";
+	};
+
+	usbphy1: usbphy@2ca0000 {
+		compatible = "nxp,usbphy";
+		reg = <0x2ca0000 0x1000>;
+		status = "disabled";
+	};
+
+	usbphy2: usbphy@2cb0000 {
+		compatible = "nxp,usbphy";
+		reg = <0x2cb0000 0x1000>;
+		status = "disabled";
+	};
+};
+
+&flexspi {
+	compatible = "nxp,imx-flexspi";
+	interrupts = <55 0>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "disabled";
+	clocks = <&ccm IMX_CCM_FLEXSPI_CLK 0x0 0>;
 };
 
 &flexspi2 {
diff --git a/dts/arm/nxp/nxp_rt118x_cm33.dtsi b/dts/arm/nxp/nxp_rt118x_cm33.dtsi
index 83892d17028..b77431936d9 100644
--- a/dts/arm/nxp/nxp_rt118x_cm33.dtsi
+++ b/dts/arm/nxp/nxp_rt118x_cm33.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -26,6 +26,12 @@
 			ranges = <0x0 0x30484000 0x10000000>;
 		};
 
+		m7_itcm: itcm@303c0000 {
+			compatible = "zephyr,memory-region", "mmio-sram";
+			zephyr,memory-region = "M7_ITCM";
+			reg = <0x303c0000 DT_SIZE_K(256)>;
+		};
+
 		peripheral: peripheral@50000000 {
 			ranges = <0x0 0x50000000 0x10000000>;
 		};
@@ -48,6 +54,26 @@
 	};
 };
 
+&peripheral {
+	mbox1_a: mbox@4220000 {
+		compatible = "nxp,mbox-imx-mu";
+		reg = <0x4220000 0x4000>;
+		interrupts = <21 0>;
+		rx-channels = <4>;
+		#mbox-cells = <1>;
+		status = "okay";
+	};
+
+	mbox2_a: mbox@2430000 {
+		compatible = "nxp,mbox-imx-mu";
+		reg = <0x2430000 0x4000>;
+		interrupts = <22 0>;
+		rx-channels = <4>;
+		#mbox-cells = <1>;
+		status = "okay";
+	};
+};
+
 &nvic {
 	arm,num-irq-priority-bits = <3>;
 };
@@ -60,7 +86,7 @@
 
 &gpio1{
 	pinmux = <&iomuxc_aon_gpio_aon_00_gpio1_io00>,
-	    <&iomuxc_aon_gpio_aon_01_gpio1_io01>,
+		<&iomuxc_aon_gpio_aon_01_gpio1_io01>,
 		<&iomuxc_aon_gpio_aon_02_gpio1_io02>,
 		<&iomuxc_aon_gpio_aon_03_gpio1_io03>,
 		<&iomuxc_aon_gpio_aon_04_gpio1_io04>,
@@ -91,7 +117,7 @@
 
 &gpio2{
 	pinmux = <&iomuxc_gpio_emc_b1_00_gpio2_io00>,
-	    <&iomuxc_gpio_emc_b1_01_gpio2_io01>,
+		<&iomuxc_gpio_emc_b1_01_gpio2_io01>,
 		<&iomuxc_gpio_emc_b1_02_gpio2_io02>,
 		<&iomuxc_gpio_emc_b1_03_gpio2_io03>,
 		<&iomuxc_gpio_emc_b1_04_gpio2_io04>,
@@ -126,7 +152,7 @@
 
 &gpio3{
 	pinmux = <&iomuxc_gpio_emc_b1_32_gpio3_io00>,
-	    <&iomuxc_gpio_emc_b1_33_gpio3_io01>,
+		<&iomuxc_gpio_emc_b1_33_gpio3_io01>,
 		<&iomuxc_gpio_emc_b1_34_gpio3_io02>,
 		<&iomuxc_gpio_emc_b1_35_gpio3_io03>,
 		<&iomuxc_gpio_emc_b1_36_gpio3_io04>,
diff --git a/dts/arm/nxp/nxp_rt118x_cm33_ns.dtsi b/dts/arm/nxp/nxp_rt118x_cm33_ns.dtsi
index 1b082a90fe6..5bd64f0ea60 100644
--- a/dts/arm/nxp/nxp_rt118x_cm33_ns.dtsi
+++ b/dts/arm/nxp/nxp_rt118x_cm33_ns.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -26,6 +26,12 @@
 			ranges = <0x0 0x20484000 0x10000000>;
 		};
 
+		m7_itcm: itcm@203c0000 {
+			compatible = "zephyr,memory-region", "mmio-sram";
+			zephyr,memory-region = "M7_ITCM";
+			reg = <0x203c0000 DT_SIZE_K(256)>;
+		};
+
 		peripheral: peripheral@40000000 {
 			ranges = <0x0 0x40000000 0x10000000>;
 		};
@@ -48,6 +54,26 @@
 	};
 };
 
+&peripheral {
+	mbox1_a: mbox@4220000 {
+		compatible = "nxp,mbox-imx-mu";
+		reg = <0x4220000 0x4000>;
+		interrupts = <21 0>;
+		rx-channels = <4>;
+		#mbox-cells = <1>;
+		status = "okay";
+	};
+
+	mbox2_a: mbox@2430000 {
+		compatible = "nxp,mbox-imx-mu";
+		reg = <0x2430000 0x4000>;
+		interrupts = <22 0>;
+		rx-channels = <4>;
+		#mbox-cells = <1>;
+		status = "okay";
+	};
+};
+
 &nvic {
 	arm,num-irq-priority-bits = <3>;
 };
@@ -60,7 +86,7 @@
 
 &gpio1{
 	pinmux = <&iomuxc_aon_gpio_aon_00_gpio1_io00>,
-	    <&iomuxc_aon_gpio_aon_01_gpio1_io01>,
+		<&iomuxc_aon_gpio_aon_01_gpio1_io01>,
 		<&iomuxc_aon_gpio_aon_02_gpio1_io02>,
 		<&iomuxc_aon_gpio_aon_03_gpio1_io03>,
 		<&iomuxc_aon_gpio_aon_04_gpio1_io04>,
@@ -91,7 +117,7 @@
 
 &gpio2{
 	pinmux = <&iomuxc_gpio_emc_b1_00_gpio2_io00>,
-	    <&iomuxc_gpio_emc_b1_01_gpio2_io01>,
+		<&iomuxc_gpio_emc_b1_01_gpio2_io01>,
 		<&iomuxc_gpio_emc_b1_02_gpio2_io02>,
 		<&iomuxc_gpio_emc_b1_03_gpio2_io03>,
 		<&iomuxc_gpio_emc_b1_04_gpio2_io04>,
@@ -126,7 +152,7 @@
 
 &gpio3{
 	pinmux = <&iomuxc_gpio_emc_b1_32_gpio3_io00>,
-	    <&iomuxc_gpio_emc_b1_33_gpio3_io01>,
+		<&iomuxc_gpio_emc_b1_33_gpio3_io01>,
 		<&iomuxc_gpio_emc_b1_34_gpio3_io02>,
 		<&iomuxc_gpio_emc_b1_35_gpio3_io03>,
 		<&iomuxc_gpio_emc_b1_36_gpio3_io04>,
diff --git a/dts/arm/nxp/nxp_rt118x_cm7.dtsi b/dts/arm/nxp/nxp_rt118x_cm7.dtsi
index 50aa4aa7c4a..1b9cde67f4c 100644
--- a/dts/arm/nxp/nxp_rt118x_cm7.dtsi
+++ b/dts/arm/nxp/nxp_rt118x_cm7.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,13 +10,15 @@
 / {
 	soc {
 		itcm: itcm@0{
-			compatible = "nxp,imx-itcm";
+			compatible = "zephyr,memory-region", "nxp,imx-itcm";
 			reg = <0x00000000 DT_SIZE_K(256)>;
+			zephyr,memory-region = "ITCM";
 		};
 
 		dtcm: dtcm@20000000 {
-			compatible = "nxp,imx-dtcm";
+			compatible = "zephyr,memory-region", "nxp,imx-dtcm";
 			reg = <0x20000000 DT_SIZE_K(256)>;
+			zephyr,memory-region = "DTCM";
 		};
 
 		memory: memory@20484000 {
@@ -45,6 +47,26 @@
 	};
 };
 
+&peripheral {
+	mbox1_b: mbox@4230000 {
+		compatible = "nxp,mbox-imx-mu";
+		reg = <0x4230000 0x4000>;
+		interrupts = <21 0>;
+		rx-channels = <4>;
+		#mbox-cells = <1>;
+		status = "okay";
+	};
+
+	mbox2_b: mbox@2440000 {
+		compatible = "nxp,mbox-imx-mu";
+		reg = <0x2440000 0x4000>;
+		interrupts = <22 0>;
+		rx-channels = <4>;
+		#mbox-cells = <1>;
+		status = "okay";
+	};
+};
+
 &nvic {
 	arm,num-irq-priority-bits = <4>;
 };
@@ -57,7 +79,7 @@
 
 &gpio1{
 	pinmux = <&iomuxc_aon_gpio_aon_00_gpio1_io00>,
-	    <&iomuxc_aon_gpio_aon_01_gpio1_io01>,
+		<&iomuxc_aon_gpio_aon_01_gpio1_io01>,
 		<&iomuxc_aon_gpio_aon_02_gpio1_io02>,
 		<&iomuxc_aon_gpio_aon_03_gpio1_io03>,
 		<&iomuxc_aon_gpio_aon_04_gpio1_io04>,
@@ -88,7 +110,7 @@
 
 &gpio2{
 	pinmux = <&iomuxc_gpio_emc_b1_00_gpio2_io00>,
-	    <&iomuxc_gpio_emc_b1_01_gpio2_io01>,
+		<&iomuxc_gpio_emc_b1_01_gpio2_io01>,
 		<&iomuxc_gpio_emc_b1_02_gpio2_io02>,
 		<&iomuxc_gpio_emc_b1_03_gpio2_io03>,
 		<&iomuxc_gpio_emc_b1_04_gpio2_io04>,
@@ -123,7 +145,7 @@
 
 &gpio3{
 	pinmux = <&iomuxc_gpio_emc_b1_32_gpio3_io00>,
-	    <&iomuxc_gpio_emc_b1_33_gpio3_io01>,
+		<&iomuxc_gpio_emc_b1_33_gpio3_io01>,
 		<&iomuxc_gpio_emc_b1_34_gpio3_io02>,
 		<&iomuxc_gpio_emc_b1_35_gpio3_io03>,
 		<&iomuxc_gpio_emc_b1_36_gpio3_io04>,
diff --git a/dts/arm/nxp/nxp_rt11xx.dtsi b/dts/arm/nxp/nxp_rt11xx.dtsi
index d83c2c833f2..6ef0fd76eb3 100644
--- a/dts/arm/nxp/nxp_rt11xx.dtsi
+++ b/dts/arm/nxp/nxp_rt11xx.dtsi
@@ -416,6 +416,8 @@
 			interrupts = <38 3>;
 			status = "disabled";
 			clocks = <&ccm IMX_CCM_LPSPI1_CLK 0x6c 0>;
+			rx-fifo-size = <16>;
+			tx-fifo-size = <16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
@@ -426,6 +428,8 @@
 			interrupts = <39 3>;
 			status = "disabled";
 			clocks = <&ccm IMX_CCM_LPSPI2_CLK 0x6c 2>;
+			rx-fifo-size = <16>;
+			tx-fifo-size = <16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
@@ -436,6 +440,8 @@
 			interrupts = <40 3>;
 			status = "disabled";
 			clocks = <&ccm IMX_CCM_LPSPI3_CLK 0x6c 4>;
+			rx-fifo-size = <16>;
+			tx-fifo-size = <16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
@@ -446,6 +452,8 @@
 			interrupts = <41 3>;
 			status = "disabled";
 			clocks = <&ccm IMX_CCM_LPSPI4_CLK 0x6c 6>;
+			rx-fifo-size = <16>;
+			tx-fifo-size = <16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
@@ -456,6 +464,8 @@
 			interrupts = <42 3>;
 			status = "disabled";
 			clocks = <&ccm IMX_CCM_LPSPI5_CLK 0x6c 6>;
+			rx-fifo-size = <16>;
+			tx-fifo-size = <16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
@@ -466,6 +476,8 @@
 			interrupts = <43 3>;
 			status = "disabled";
 			clocks = <&ccm IMX_CCM_LPSPI6_CLK 0x6c 6>;
+			rx-fifo-size = <16>;
+			tx-fifo-size = <16>;
 			#address-cells = <1>;
 			#size-cells = <0>;
 		};
@@ -1048,7 +1060,7 @@
 			dma-channels = <32>;
 			dma-requests = <208>;
 			nxp,mem2mem;
-			nxp,a_on;
+			nxp,a-on;
 			reg = <0x40070000 0x4000>,
 				<0x40074000 0x4000>;
 			clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
@@ -1056,8 +1068,7 @@
 			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
 				<4 0>, <5 0>, <6 0>, <7 0>,
 				<8 0>, <9 0>, <10 0>, <11 0>,
-				<12 0>, <13 0>, <14 0>, <15 0>,
-				<16 0>;
+				<12 0>, <13 0>, <14 0>, <15 0>;
 			irq-shared-offset = <16>;
 		};
 
@@ -1068,7 +1079,7 @@
 			dma-channels = <32>;
 			dma-requests = <208>;
 			nxp,mem2mem;
-			nxp,a_on;
+			nxp,a-on;
 			reg = <0x40c14000 0x4000>,
 				<0x40c18000 0x4000>;
 			clocks = <&ccm IMX_CCM_EDMA_LPSR_CLK 0x7C 0x000000C0>;
@@ -1076,8 +1087,7 @@
 			interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
 				<4 0>, <5 0>, <6 0>, <7 0>,
 				<8 0>, <9 0>, <10 0>, <11 0>,
-				<12 0>, <13 0>, <14 0>, <15 0>,
-				<16 0>;
+				<12 0>, <13 0>, <14 0>, <15 0>;
 			irq-shared-offset = <16>;
 		};
 
diff --git a/dts/arm/nxp/nxp_rt11xx_cm7.dtsi b/dts/arm/nxp/nxp_rt11xx_cm7.dtsi
index 88d1035ddc3..9de83c4cf41 100644
--- a/dts/arm/nxp/nxp_rt11xx_cm7.dtsi
+++ b/dts/arm/nxp/nxp_rt11xx_cm7.dtsi
@@ -34,23 +34,6 @@
 			flexram,bank-size = <32>;
 			flexram,num-ram-banks = <16>;
 			flexram,has-magic-addr;
-			/* same as default fuse value */
-			flexram,bank-spec = <FLEXRAM_DTCM>,
-					     <FLEXRAM_DTCM>,
-					     <FLEXRAM_DTCM>,
-					     <FLEXRAM_DTCM>,
-					     <FLEXRAM_ITCM>,
-					     <FLEXRAM_ITCM>,
-					     <FLEXRAM_ITCM>,
-					     <FLEXRAM_ITCM>,
-					     <FLEXRAM_DTCM>,
-					     <FLEXRAM_DTCM>,
-					     <FLEXRAM_DTCM>,
-					     <FLEXRAM_DTCM>,
-					     <FLEXRAM_ITCM>,
-					     <FLEXRAM_ITCM>,
-					     <FLEXRAM_ITCM>,
-					     <FLEXRAM_ITCM>;
 
 			itcm: itcm@0 {
 				compatible = "zephyr,memory-region", "nxp,imx-itcm";
diff --git a/dts/arm/nxp/nxp_rt5xx_common.dtsi b/dts/arm/nxp/nxp_rt5xx_common.dtsi
index aa9db51f125..3d988f26011 100644
--- a/dts/arm/nxp/nxp_rt5xx_common.dtsi
+++ b/dts/arm/nxp/nxp_rt5xx_common.dtsi
@@ -438,56 +438,48 @@
 		clocks = <&clkctl0 MCUX_DMIC_CLK>;
 
 		pdmc0: dmic-channel@0 {
-			compatible = "nxp,dmic-channel";
 			reg = <0>;
 			dmas = <&dma0 16>;
 			status = "disabled";
 		};
 
 		pdmc1: dmic-channel@1 {
-			compatible = "nxp,dmic-channel";
 			reg = <1>;
 			dmas = <&dma0 17>;
 			status = "disabled";
 		};
 
 		pdmc2: dmic-channel@2 {
-			compatible = "nxp,dmic-channel";
 			reg = <2>;
 			dmas = <&dma0 18>;
 			status = "disabled";
 		};
 
 		pdmc3: dmic-channel@3 {
-			compatible = "nxp,dmic-channel";
 			reg = <3>;
 			dmas = <&dma0 19>;
 			status = "disabled";
 		};
 
 		pdmc4: dmic-channel@4 {
-			compatible = "nxp,dmic-channel";
 			reg = <4>;
 			dmas = <&dma0 20>;
 			status = "disabled";
 		};
 
 		pdmc5: dmic-channel@5 {
-			compatible = "nxp,dmic-channel";
 			reg = <5>;
 			dmas = <&dma0 21>;
 			status = "disabled";
 		};
 
 		pdmc6: dmic-channel@6 {
-			compatible = "nxp,dmic-channel";
 			reg = <6>;
 			dmas = <&dma0 22>;
 			status = "disabled";
 		};
 
 		pdmc7: dmic-channel@7 {
-			compatible = "nxp,dmic-channel";
 			reg = <7>;
 			dmas = <&dma0 23>;
 			status = "disabled";
diff --git a/dts/arm/nxp/nxp_rt6xx_common.dtsi b/dts/arm/nxp/nxp_rt6xx_common.dtsi
index bf2dc2daccd..bca82a2a6f4 100644
--- a/dts/arm/nxp/nxp_rt6xx_common.dtsi
+++ b/dts/arm/nxp/nxp_rt6xx_common.dtsi
@@ -345,56 +345,48 @@
 		clocks = <&clkctl0 MCUX_DMIC_CLK>;
 
 		pdmc0: dmic-channel@0 {
-			compatible = "nxp,dmic-channel";
 			reg = <0>;
 			dmas = <&dma0 16>;
 			status = "disabled";
 		};
 
 		pdmc1: dmic-channel@1 {
-			compatible = "nxp,dmic-channel";
 			reg = <1>;
 			dmas = <&dma0 17>;
 			status = "disabled";
 		};
 
 		pdmc2: dmic-channel@2 {
-			compatible = "nxp,dmic-channel";
 			reg = <2>;
 			dmas = <&dma0 18>;
 			status = "disabled";
 		};
 
 		pdmc3: dmic-channel@3 {
-			compatible = "nxp,dmic-channel";
 			reg = <3>;
 			dmas = <&dma0 19>;
 			status = "disabled";
 		};
 
 		pdmc4: dmic-channel@4 {
-			compatible = "nxp,dmic-channel";
 			reg = <4>;
 			dmas = <&dma0 20>;
 			status = "disabled";
 		};
 
 		pdmc5: dmic-channel@5 {
-			compatible = "nxp,dmic-channel";
 			reg = <5>;
 			dmas = <&dma0 21>;
 			status = "disabled";
 		};
 
 		pdmc6: dmic-channel@6 {
-			compatible = "nxp,dmic-channel";
 			reg = <6>;
 			dmas = <&dma0 22>;
 			status = "disabled";
 		};
 
 		pdmc7: dmic-channel@7 {
-			compatible = "nxp,dmic-channel";
 			reg = <7>;
 			dmas = <&dma0 23>;
 			status = "disabled";
diff --git a/dts/arm/nxp/nxp_rt7xx_cm33_cpu0.dtsi b/dts/arm/nxp/nxp_rt7xx_cm33_cpu0.dtsi
new file mode 100644
index 00000000000..427d819ec21
--- /dev/null
+++ b/dts/arm/nxp/nxp_rt7xx_cm33_cpu0.dtsi
@@ -0,0 +1,1123 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-m.dtsi>
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/mipi_dsi/mipi_dsi.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-m33f";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	soc {
+		sram: sram@10000000 {
+			ranges = <0x0 0x10000000 0x780000
+				0x20000000 0x30000000 0x780000>;
+		};
+
+		peripheral: peripheral@50000000 {
+			ranges = <0x0 0x50000000 0x10000000>;
+		};
+
+		xspi0: spi@50184000 {
+			reg = <0x50184000 0x1000>, <0x38000000 DT_SIZE_M(128)>;
+		};
+
+		xspi1: spi@50185000 {
+			reg = <0x50185000 0x1000>, <0x18000000 DT_SIZE_M(128)>;
+		};
+
+		xspi2: spi@50411000 {
+			reg = <0x50411000 0x1000>, <0x70000000 DT_SIZE_M(128)>;
+		};
+
+	};
+
+	pinctrl: pinctrl {
+		compatible = "nxp,rt-iocon-pinctrl";
+	};
+
+	/* USB PLL */
+	usbclk: usbpll-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <24000000>;
+		#clock-cells = <0>;
+	};
+};
+
+
+&sram {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	/* RT7XX SRAM partitions are shared between code and data. Boards can override
+	 *  the reg properties of either sram0 or sram_code nodes to change the balance
+	 *  of SRAM allocation.
+	 *
+	 * The SRAM region [0x000000-0x017FFF] is reserved for ROM bootloader execution.
+	 * Can be reused after boot.
+	 * The SRAM region [0x018000-0x17FFFF] is reserved for Non-cached shared memory
+	 * or application data.
+	 * The SRAM region [0x180000-0x1FFFFF] is reserved for CPU0 application, last
+	 * 2MB non-cacheable data for NPU/GPU/Display etc.
+	 * The SRAM region [0x200000-0x400000] is reserved for HiFi4 application.
+	 */
+
+	sram4rom: memory@20000000{
+		compatible = "mmio-sram";
+		reg = <0x20000000 DT_SIZE_K(96)>;
+	};
+
+	/* This partition is shared with code in RAM */
+	sram_shared_code: memory@20018000{
+		compatible = "mmio-sram";
+		reg = <0x20018000 DT_SIZE_K(1024+512-96)>;
+	};
+
+	sram0: memory@20180000 {
+		compatible = "mmio-sram";
+		reg = <0x20180000 DT_SIZE_K(512)>;
+	};
+
+	sram1: memory@20200000 {
+		compatible =  "mmio-sram";
+		reg = <0x20200000 DT_SIZE_K(2048)>;
+	};
+};
+
+&peripheral {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	/*
+	 * Note that the offsets here are relative to the base address.
+	 * The base addresses differ between non-secure (0x40000000)
+	 * and secure modes (0x50000000).
+	 */
+
+	lpadc0: adc@20c000 {
+		compatible = "nxp,lpc-lpadc";
+		reg = <0x20c000 0x304>;
+		interrupts = <15 0>;
+		status = "disabled";
+		clk-divider = <1>;
+		clk-source = <0>;
+		voltage-ref= <1>;
+		calibration-average = <128>;
+		power-level = <0>;
+		offset-value-a = <10>;
+		offset-value-b = <10>;
+		#io-channel-cells = <1>;
+		clocks = <&clkctl3 MCUX_LPADC1_CLK>;
+	};
+
+	rstctl0: reset@0 {
+		compatible = "nxp,rstctl";
+		reg = <0x0 0x1000>;
+		#reset-cells = <1>;
+	};
+
+	rstctl2: reset@67000 {
+		compatible = "nxp,rstctl";
+		reg = <0x67000 0x1000>;
+		#reset-cells = <1>;
+	};
+
+	rstctl3: reset@60000 {
+		compatible = "nxp,rstctl";
+		reg = <0x60000 0x1000>;
+		#reset-cells = <1>;
+	};
+
+	rstctl4: reset@a0000 {
+		compatible = "nxp,rstctl";
+		reg = <0xa0000 0x1000>;
+		#reset-cells = <1>;
+	};
+
+	clkctl0: clkctl@1000 {
+		compatible = "nxp,lpc-syscon";
+		reg = <0x1000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	clkctl2: clkctl@65000 {
+		compatible = "nxp,lpc-syscon";
+		reg = <0x65000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	clkctl3: clkctl@61000 {
+		compatible = "nxp,lpc-syscon";
+		reg = <0x61000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	clkctl4: clkctl@a1000 {
+		compatible = "nxp,lpc-syscon";
+		reg = <0xa1000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	ctimer0: ctimer@28000 {
+		compatible = "nxp,lpc-ctimer";
+		reg = <0x28000 0x1000>;
+		interrupts = <3 0>;
+		status = "disabled";
+		clk-source = <1>;
+		clocks = <&clkctl0 MCUX_CTIMER0_CLK>;
+		mode = <0>;
+		input = <0>;
+		prescale = <0>;
+	};
+
+	ctimer1: ctimer@29000 {
+		compatible = "nxp,lpc-ctimer";
+		reg = <0x29000 0x1000>;
+		interrupts = <4 0>;
+		status = "disabled";
+		clk-source = <1>;
+		clocks = <&clkctl0 MCUX_CTIMER1_CLK>;
+		mode = <0>;
+		input = <0>;
+		prescale = <0>;
+	};
+
+	ctimer2: ctimer@2a000 {
+		compatible = "nxp,lpc-ctimer";
+		reg = <0x2a000 0x1000>;
+		interrupts = <32 0>;
+		status = "disabled";
+		clk-source = <1>;
+		clocks = <&clkctl0 MCUX_CTIMER2_CLK>;
+		mode = <0>;
+		input = <0>;
+		prescale = <0>;
+	};
+
+	ctimer3: ctimer@2b000 {
+		compatible = "nxp,lpc-ctimer";
+		reg = <0x2b000 0x1000>;
+		interrupts = <6 0>;
+		status = "disabled";
+		clk-source = <1>;
+		clocks = <&clkctl0 MCUX_CTIMER3_CLK>;
+		mode = <0>;
+		input = <0>;
+		prescale = <0>;
+	};
+
+	ctimer4: ctimer@2c000 {
+		compatible = "nxp,lpc-ctimer";
+		reg = <0x2c000 0x1000>;
+		interrupts = <33 0>;
+		status = "disabled";
+		clk-source = <1>;
+		clocks = <&clkctl0 MCUX_CTIMER4_CLK>;
+		mode = <0>;
+		input = <0>;
+		prescale = <0>;
+	};
+
+	edma0: dma-controller@140000 {
+		#dma-cells = <2>;
+		compatible = "nxp,mcux-edma";
+		nxp,version = <4>;
+		dma-channels = <16>;
+		dma-requests = <105>;
+		reg = <0x140000 0x1000>;
+		interrupts = <59 0>, <60 0>, <61 0>, <62 0>,
+			<63 0>, <64 0>, <65 0>, <66 0>,
+			<67 0>, <68 0>, <69 0>, <70 0>,
+			<71 0>, <72 0>, <73 0>, <74 0>;
+		no-error-irq;
+		status = "disabled";
+	};
+
+	edma1: dma-controller@160000 {
+		#dma-cells = <2>;
+		compatible = "nxp,mcux-edma";
+		nxp,version = <4>;
+		dma-channels = <16>;
+		dma-requests = <105>;
+		reg = <0x160000 0x1000>;
+		interrupts = <75 0>, <76 0>, <77 0>, <78 0>,
+			<79 0>, <80 0>, <81 0>, <82 0>,
+			<83 0>, <84 0>, <85 0>, <86 0>,
+			<87 0>, <88 0>, <89 0>, <90 0>;
+		no-error-irq;
+		status = "disabled";
+	};
+
+	syscon0: syscon@2000 {
+		compatible = "nxp,lpc-syscon";
+		reg = <0x2000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	syscon2: syscon@66000 {
+		compatible = "nxp,lpc-syscon";
+		reg = <0x66000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	syscon3: syscon@62000 {
+		compatible = "nxp,lpc-syscon";
+		reg = <0x62000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	syscon4: syscon@a2000 {
+		compatible = "nxp,lpc-syscon";
+		reg = <0xa2000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	iocon: iocon@4000 {
+		compatible = "nxp,lpc-iocon";
+		reg = <0x4000 0x1000>;
+		status = "okay";
+	};
+
+	iocon1: iocon@64000 {
+		compatible = "nxp,lpc-iocon";
+		reg = <0x64000 0x1000>;
+		status = "okay";
+	};
+
+	iocon2: iocon@a5000 {
+		compatible = "nxp,lpc-iocon";
+		reg = <0xa5000 0x1000>;
+		status = "okay";
+	};
+
+	gpio0: gpio@100000 {
+		compatible = "nxp,kinetis-gpio";
+		status = "disabled";
+		reg = <0x100000 0x1000>;
+		interrupts = <91 0>,<92 0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		nxp,kinetis-port = <&gpio0>;
+	};
+
+	gpio1: gpio@102000 {
+		compatible = "nxp,kinetis-gpio";
+		status = "disabled";
+		reg = <0x102000 0x1000>;
+		interrupts = <93 0>,<94 0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		nxp,kinetis-port = <&gpio1>;
+	};
+
+	gpio2: gpio@104000 {
+		compatible = "nxp,kinetis-gpio";
+		status = "disabled";
+		reg = <0x104000 0x1000>;
+		interrupts = <95 0>,<96 0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		nxp,kinetis-port = <&gpio2>;
+	};
+
+	gpio3: gpio@106000 {
+		compatible = "nxp,kinetis-gpio";
+		status = "disabled";
+		reg = <0x106000 0x1000>;
+		interrupts = <97 0>,<98 0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		nxp,kinetis-port = <&gpio3>;
+	};
+
+	gpio4: gpio@108000 {
+		compatible = "nxp,kinetis-gpio";
+		status = "disabled";
+		reg = <0x108000 0x1000>;
+		interrupts = <99 0>,<100 0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		nxp,kinetis-port = <&gpio4>;
+	};
+
+	gpio5: gpio@10a000 {
+		compatible = "nxp,kinetis-gpio";
+		status = "disabled";
+		reg = <0x10a000 0x1000>;
+		interrupts = <101 0>,<102 0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		nxp,kinetis-port = <&gpio5>;
+	};
+
+	gpio6: gpio@10c000 {
+		compatible = "nxp,kinetis-gpio";
+		status = "disabled";
+		reg = <0x10c000 0x1000>;
+		interrupts = <103 0>,<104 0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		nxp,kinetis-port = <&gpio6>;
+	};
+
+	gpio7: gpio@10e000 {
+		compatible = "nxp,kinetis-gpio";
+		status = "disabled";
+		reg = <0x10e000 0x1000>;
+		interrupts = <105 0>,<106 0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		nxp,kinetis-port = <&gpio7>;
+	};
+
+	flexcomm0: flexcomm@110000 {
+		compatible = "nxp,lp-flexcomm";
+		reg = <0x110000 0x1000>;
+		interrupts = <7 0>;
+		status = "disabled";
+
+		/* Empty ranges property implies parent and child address space is identical */
+		ranges = <>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flexcomm0_lpuart0: uart@110000 {
+			compatible = "nxp,lpuart";
+			reg = <0x110000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM0_CLK>;
+			status = "disabled";
+		};
+
+		flexcomm0_lpspi0: spi@110000 {
+			compatible = "nxp,lpspi";
+			reg = <0x110000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM0_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
+			status = "disabled";
+		};
+
+		flexcomm0_lpi2c0: lpi2c@110800 {
+			compatible = "nxp,lpi2c";
+			reg = <0x110800 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM0_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	flexcomm1: flexcomm@111000 {
+		compatible = "nxp,lp-flexcomm";
+		reg = <0x111000 0x1000>;
+		interrupts = <8 0>;
+		status = "disabled";
+
+		/* Empty ranges property implies parent and child address space is identical */
+		ranges = <>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flexcomm1_lpuart1: uart@111000 {
+			compatible = "nxp,lpuart";
+			reg = <0x111000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM1_CLK>;
+			status = "disabled";
+		};
+
+		flexcomm1_lpspi1: spi@111000 {
+			compatible = "nxp,lpspi";
+			reg = <0x111000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM1_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
+			status = "disabled";
+		};
+
+		flexcomm1_lpi2c1: lpi2c@111800 {
+			compatible = "nxp,lpi2c";
+			reg = <0x111800 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM1_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	flexcomm2: flexcomm@112000 {
+		compatible = "nxp,lp-flexcomm";
+		reg = <0x112000 0x1000>;
+		interrupts = <9 0>;
+		status = "disabled";
+
+		/* Empty ranges property implies parent and child address space is identical */
+		ranges = <>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flexcomm2_lpuart2: uart@112000 {
+			compatible = "nxp,lpuart";
+			reg = <0x112000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM2_CLK>;
+			status = "disabled";
+		};
+
+		flexcomm2_lpspi2: spi@112000 {
+			compatible = "nxp,lpspi";
+			reg = <0x112000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM2_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
+			status = "disabled";
+		};
+
+		flexcomm2_lpi2c2: lpi2c@112800 {
+			compatible = "nxp,lpi2c";
+			reg = <0x112800 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM2_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	flexcomm3: flexcomm@113000 {
+		compatible = "nxp,lp-flexcomm";
+		reg = <0x113000 0x1000>;
+		interrupts = <10 0>;
+		status = "disabled";
+
+		/* Empty ranges property implies parent and child address space is identical */
+		ranges = <>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flexcomm3_lpuart3: uart@113000 {
+			compatible = "nxp,lpuart";
+			reg = <0x113000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM3_CLK>;
+			status = "disabled";
+		};
+
+		flexcomm3_lpspi3: spi@113000 {
+			compatible = "nxp,lpspi";
+			reg = <0x113000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM3_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
+			status = "disabled";
+		};
+
+		flexcomm3_lpi2c3: lpi2c@113800 {
+			compatible = "nxp,lpi2c";
+			reg = <0x113800 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM3_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	flexcomm4: flexcomm@171000 {
+		compatible = "nxp,lp-flexcomm";
+		reg = <0x171000 0x1000>;
+		interrupts = <11 0>;
+		status = "disabled";
+
+		/* Empty ranges property implies parent and child address space is identical */
+		ranges = <>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flexcomm4_lpuart4: uart@171000 {
+			compatible = "nxp,lpuart";
+			reg = <0x171000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM4_CLK>;
+			status = "disabled";
+		};
+
+		flexcomm4_lpspi4: spi@171000 {
+			compatible = "nxp,lpspi";
+			reg = <0x171000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM4_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
+			status = "disabled";
+		};
+
+		flexcomm4_lpi2c4: lpi2c@171800 {
+			compatible = "nxp,lpi2c";
+			reg = <0x171800 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM4_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	flexcomm5: flexcomm@172000 {
+		compatible = "nxp,lp-flexcomm";
+		reg = <0x172000 0x1000>;
+		interrupts = <12 0>;
+		status = "disabled";
+
+		/* Empty ranges property implies parent and child address space is identical */
+		ranges = <>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flexcomm5_lpuart5: uart@172000 {
+			compatible = "nxp,lpuart";
+			reg = <0x172000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM5_CLK>;
+			status = "disabled";
+		};
+
+		flexcomm5_lpspi5: spi@172000 {
+			compatible = "nxp,lpspi";
+			reg = <0x172000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM5_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
+			status = "disabled";
+		};
+
+		flexcomm5_lpi2c5: lpi2c@172800 {
+			compatible = "nxp,lpi2c";
+			reg = <0x172800 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM5_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	flexcomm6: flexcomm@173000 {
+		compatible = "nxp,lp-flexcomm";
+		reg = <0x173000 0x1000>;
+		interrupts = <35 0>;
+		status = "disabled";
+
+		/* Empty ranges property implies parent and child address space is identical */
+		ranges = <>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flexcomm6_lpuart6: uart@173000 {
+			compatible = "nxp,lpuart";
+			reg = <0x173000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM6_CLK>;
+			status = "disabled";
+		};
+
+		flexcomm6_lpspi6: spi@173000 {
+			compatible = "nxp,lpspi";
+			reg = <0x173000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM6_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
+			status = "disabled";
+		};
+
+		flexcomm6_lpi2c6: lpi2c@173800 {
+			compatible = "nxp,lpi2c";
+			reg = <0x173800 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM6_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	flexcomm7: flexcomm@174000 {
+		compatible = "nxp,lp-flexcomm";
+		reg = <0x174000 0x1000>;
+		interrupts = <36 0>;
+		status = "disabled";
+
+		/* Empty ranges property implies parent and child address space is identical */
+		ranges = <>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flexcomm7_lpuart7: uart@174000 {
+			compatible = "nxp,lpuart";
+			reg = <0x174000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM7_CLK>;
+			status = "disabled";
+		};
+
+		flexcomm7_lpspi7: spi@174000 {
+			compatible = "nxp,lpspi";
+			reg = <0x174000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM7_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
+			status = "disabled";
+		};
+
+		flexcomm7_lpi2c7: lpi2c@174800 {
+			compatible = "nxp,lpi2c";
+			reg = <0x174800 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM7_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	flexcomm8: flexcomm@199000 {
+		compatible = "nxp,lp-flexcomm";
+		reg = <0x199000 0x1000>;
+		interrupts = <47 0>;
+		status = "disabled";
+
+		/* Empty ranges property implies parent and child address space is identical */
+		ranges = <>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flexcomm8_lpuart8: uart@199000 {
+			compatible = "nxp,lpuart";
+			reg = <0x199000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM8_CLK>;
+			status = "disabled";
+		};
+
+		flexcomm8_lpspi8: spi@199000 {
+			compatible = "nxp,lpspi";
+			reg = <0x199000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM8_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
+			status = "disabled";
+		};
+
+		flexcomm8_lpi2c8: lpi2c@199800 {
+			compatible = "nxp,lpi2c";
+			reg = <0x199800 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM8_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	flexcomm9: flexcomm@19a000 {
+		compatible = "nxp,lp-flexcomm";
+		reg = <0x19a000 0x1000>;
+		interrupts = <48 0>;
+		status = "disabled";
+
+		/* Empty ranges property implies parent and child address space is identical */
+		ranges = <>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flexcomm9_lpuart9: uart@19a000 {
+			compatible = "nxp,lpuart";
+			reg = <0x19a000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM9_CLK>;
+			status = "disabled";
+		};
+
+		flexcomm9_lpspi9: spi@19a000 {
+			compatible = "nxp,lpspi";
+			reg = <0x19a000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM9_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
+			status = "disabled";
+		};
+
+		flexcomm9_lpi2c9: lpi2c@19a800 {
+			compatible = "nxp,lpi2c";
+			reg = <0x19a800 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM9_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	flexcomm10: flexcomm@19b000 {
+		compatible = "nxp,lp-flexcomm";
+		reg = <0x19b000 0x1000>;
+		interrupts = <49 0>;
+		status = "disabled";
+
+		/* Empty ranges property implies parent and child address space is identical */
+		ranges = <>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flexcomm10_lpuart10: uart@19b000 {
+			compatible = "nxp,lpuart";
+			reg = <0x19b000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM10_CLK>;
+			status = "disabled";
+		};
+
+		flexcomm10_lpspi10: spi@19b000 {
+			compatible = "nxp,lpspi";
+			reg = <0x19b000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM10_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
+			status = "disabled";
+		};
+
+		flexcomm10_lpi2c10: lpi2c@19b800 {
+			compatible = "nxp,lpi2c";
+			reg = <0x19b800 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM10_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	flexcomm11: flexcomm@19c000 {
+		compatible = "nxp,lp-flexcomm";
+		reg = <0x19c000 0x1000>;
+		interrupts = <50 0>;
+		status = "disabled";
+
+		/* Empty ranges property implies parent and child address space is identical */
+		ranges = <>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flexcomm11_lpuart11: uart@19c000 {
+			compatible = "nxp,lpuart";
+			reg = <0x19c000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM11_CLK>;
+			status = "disabled";
+		};
+
+		flexcomm11_lpspi11: spi@19c000 {
+			compatible = "nxp,lpspi";
+			reg = <0x19c000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM11_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
+			status = "disabled";
+		};
+
+		flexcomm11_lpi2c11: lpi2c@19c800 {
+			compatible = "nxp,lpi2c";
+			reg = <0x19c800 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM11_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	flexcomm12: flexcomm@19d000 {
+		compatible = "nxp,lp-flexcomm";
+		reg = <0x19d000 0x1000>;
+		interrupts = <51 0>;
+		status = "disabled";
+
+		/* Empty ranges property implies parent and child address space is identical */
+		ranges = <>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flexcomm12_lpuart12: uart@19d000 {
+			compatible = "nxp,lpuart";
+			reg = <0x19d000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM12_CLK>;
+			status = "disabled";
+		};
+
+		flexcomm12_lpspi12: spi@19d000 {
+			compatible = "nxp,lpspi";
+			reg = <0x19d000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM12_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
+			status = "disabled";
+		};
+
+		flexcomm12_lpi2c12: lpi2c@19d800 {
+			compatible = "nxp,lpi2c";
+			reg = <0x19d800 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM12_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	flexcomm13: flexcomm@19e000 {
+		compatible = "nxp,lp-flexcomm";
+		reg = <0x19e000 0x1000>;
+		interrupts = <52 0>;
+		status = "disabled";
+
+		/* Empty ranges property implies parent and child address space is identical */
+		ranges = <>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flexcomm13_lpuart13: uart@19e000 {
+			compatible = "nxp,lpuart";
+			reg = <0x19e000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM13_CLK>;
+			status = "disabled";
+		};
+
+		flexcomm13_lpspi13: spi@19e000 {
+			compatible = "nxp,lpspi";
+			reg = <0x19e000 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM13_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
+			status = "disabled";
+		};
+
+		flexcomm13_lpi2c13: lpi2c@19e800 {
+			compatible = "nxp,lpi2c";
+			reg = <0x19e800 0x1000>;
+			clocks = <&clkctl0 MCUX_FLEXCOMM13_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	/* LPFlexcomm14/16 only support LPSPI function  */
+	lpspi14: spi@484000 {
+		compatible = "nxp,lpspi";
+		reg = <0x484000 0x1000>;
+		interrupts = <13 0>;
+		clocks = <&clkctl4 MCUX_LPSPI14_CLK>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		tx-fifo-size = <8>;
+		rx-fifo-size = <8>;
+		status = "disabled";
+	};
+
+
+	/* LPFlexcomm15 only support LPI2C function. */
+	lpi2c15: i2c@213000 {
+		compatible = "nxp,lpi2c";
+		reg = <0x213000 0x1000>;
+		interrupts = <14 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&clkctl4 MCUX_LPI2C15_CLK>;
+		status = "disabled";
+	};
+
+	/* LPFlexcomm14/16 only support LPSPI function  */
+	lpspi16: spi@405000 {
+		compatible = "nxp,lpspi";
+		reg = <0x405000 0x1000>;
+		interrupts = <53 0>;
+		clocks = <&clkctl4 MCUX_LPSPI16_CLK>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		tx-fifo-size = <8>;
+		rx-fifo-size = <8>;
+		status = "disabled";
+	};
+
+	usb0: usbd@418000 {
+		compatible = "nxp,ehci";
+		reg = <0x418000 0x1000>;
+		interrupts = <40 0>;
+		interrupt-names = "usb_otg";
+		clocks = <&usbclk>;
+		num-bidir-endpoints = <8>;
+		status = "disabled";
+	};
+
+	usb1: usbd@419000 {
+		compatible = "nxp,ehci";
+		reg = <0x419000 0x1000>;
+		interrupts = <41 0>;
+		interrupt-names = "usb_otg";
+		clocks = <&usbclk>;
+		num-bidir-endpoints = <8>;
+		status = "disabled";
+	};
+
+	usbphy: usbphy@414000 {
+		compatible = "nxp,usbphy";
+		reg = <0x414000 0x1000>;
+		status = "disabled";
+	};
+
+	mrt0: mrt@2d000 {
+		compatible = "nxp,mrt";
+		reg = <0x2d000 0x100>;
+		interrupts = <2 0>;
+		num-channels = <4>;
+		num-bits = <24>;
+		clocks = <&clkctl2 MCUX_MRT_CLK>;
+		resets = <&rstctl0 NXP_SYSCON_RESET(3, 26)>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		mrt0_channel0: mrt_channel@0 {
+			compatible = "nxp,mrt-channel";
+			reg = <0>;
+			status = "disabled";
+		};
+
+		mrt0_channel1: mrt_channel@1 {
+			compatible = "nxp,mrt-channel";
+			reg = <1>;
+			status = "disabled";
+		};
+
+		mrt0_channel2: mrt_channel@2 {
+			compatible = "nxp,mrt-channel";
+			reg = <2>;
+			status = "disabled";
+		};
+
+		mrt0_channel3: mrt_channel@3 {
+			compatible = "nxp,mrt-channel";
+			reg = <3>;
+			status = "disabled";
+		};
+	};
+
+	flexio: flexio@416000 {
+		compatible = "nxp,flexio";
+		reg = <0x416000 0x1000>;
+		status = "disabled";
+		interrupts = <55 0>;
+		clocks = <&clkctl4 MCUX_FLEXIO0_CLK>;
+	};
+
+	os_timer_cpu0: timers@207000 {
+		compatible = "nxp,os-timer";
+		reg = <0x207000 0x1000>;
+		interrupts = <34 0>;
+		status = "disabled";
+	};
+
+	wwdt0: watchdog@e000 {
+		compatible = "nxp,lpc-wwdt";
+		reg = <0xe000 0x1000>;
+		interrupts = <42 0>;
+		status = "disabled";
+		clk-divider = <1>;
+	};
+
+	wwdt1: watchdog@2e000 {
+		compatible = "nxp,lpc-wwdt";
+		reg = <0x2e000 0x1000>;
+		interrupts = <43 0>;
+		status = "disabled";
+		clk-divider = <1>;
+	};
+
+	sc_timer: pwm@114000 {
+		compatible = "nxp,sctimer-pwm";
+		reg = <0x114000 0x1000>;
+		interrupts = <5 0>;
+		status = "disabled";
+		clocks = <&clkctl0 MCUX_SCTIMER_CLK>;
+		prescaler = <8>;
+		#pwm-cells = <3>;
+	};
+
+	lcdif: lcdif@480000 {
+		compatible = "nxp,mipi-dbi-dcnano-lcdif";
+		reg = <0x480000 0x1000>;
+		interrupts = <56 0>;
+		status = "disabled";
+	};
+
+	mipi_dsi: mipi_dsi@417000 {
+		compatible = "nxp,mipi-dsi-2l";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x417000 0x1000>;
+		interrupts = <58 0>;
+		clocks = <&clkctl4 MCUX_MIPI_DSI_DPHY_CLK>,
+				 <&clkctl4 MCUX_MIPI_DSI_ESC_CLK>,
+				 <&clkctl4 MCUX_LCDIF_PIXEL_CLK>;
+		clock-names = "dphy", "esc", "pixel";
+		ulps-control;
+		status = "disabled";
+	};
+};
+
+&systick {
+	/*
+	 * RT700 cm33_cpu0 relies by default on the OS Timer for system
+	 * clock implementation, so the SysTick node is not to be enabled.
+	 */
+	status = "disabled";
+};
+
+&xspi0 {
+	compatible = "nxp,xspi";
+	status = "disabled";
+	interrupts = <42 0>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+	clocks = <&clkctl0 MCUX_XSPI_CLK>;
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};
diff --git a/dts/arm/nxp/nxp_rt7xx_cm33_cpu1.dtsi b/dts/arm/nxp/nxp_rt7xx_cm33_cpu1.dtsi
new file mode 100644
index 00000000000..23baca895d4
--- /dev/null
+++ b/dts/arm/nxp/nxp_rt7xx_cm33_cpu1.dtsi
@@ -0,0 +1,440 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-m.dtsi>
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu1: cpu@0 {
+			compatible = "arm,cortex-m33f";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	soc {
+		sram: sram@10000000 {
+			ranges = <0x0 0x10000000 0x780000
+				0x20000000 0x30000000 0x780000>;
+		};
+
+		peripheral: peripheral@50000000 {
+			ranges = <0x0 0x50000000 0x10000000>;
+		};
+
+		xspi2: spi@50411000 {
+			reg = <0x50411000 0x1000>, <0x70000000 DT_SIZE_M(128)>;
+		};
+
+	};
+
+	pinctrl: pinctrl {
+		compatible = "nxp,rt-iocon-pinctrl";
+	};
+};
+
+&sram {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	/* RT7XX SRAM partitions are shared between code and data. Boards can
+	 *  override the reg properties of either sram0 or sram_code nodes to
+	 *  change the balance of SRAM allocation.
+	 *
+	 * The SRAM region [0x580000-0x5BFFFF] is reserved for shared memory or application data.
+	 * The SRAM region [0x5C0000-0x67FFFF] is reserved for CPU1 application.
+	 * The SRAM region [0x680000-0x77FFFF] is reserved for HiFi1 application.
+	 */
+
+	sram_code: memory@600000{
+		compatible = "mmio-sram";
+		reg = <0x600000 DT_SIZE_K(512)>;
+	};
+
+	/* This partition is shared with code in RAM */
+	sram_shared_code: memory@20058000{
+		compatible = "mmio-sram";
+		reg = <0x20058000 DT_SIZE_K(256)>;
+	};
+
+	sram0: memory@205C0000 {
+		compatible = "mmio-sram";
+		/* Only use 256K, align with SDK */
+		reg = <0x205C0000 DT_SIZE_K(256)>;
+	};
+};
+
+&peripheral {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	/*
+	 * Note that the offsets here are relative to the base address.
+	 * The base addresses differ between non-secure (0x40000000)
+	 * and secure modes (0x50000000).
+	 */
+
+	lpadc0: adc@20c000 {
+		compatible = "nxp,lpc-lpadc";
+		reg = <0x20c000 0x304>;
+		interrupts = <15 0>;
+		status = "disabled";
+		clk-divider = <1>;
+		clk-source = <0>;
+		voltage-ref= <1>;
+		calibration-average = <128>;
+		power-level = <0>;
+		offset-value-a = <10>;
+		offset-value-b = <10>;
+		#io-channel-cells = <1>;
+		clocks = <&clkctl3 MCUX_LPADC1_CLK>;
+	};
+
+	rstctl1: reset@40000 {
+		compatible = "nxp,rstctl";
+		reg = <0x40000 0x1000>;
+		#reset-cells = <1>;
+	};
+
+	rstctl2: reset@67000 {
+		compatible = "nxp,rstctl";
+		reg = <0x67000 0x1000>;
+		#reset-cells = <1>;
+	};
+
+	rstctl3: reset@60000 {
+		compatible = "nxp,rstctl";
+		reg = <0x60000 0x1000>;
+		#reset-cells = <1>;
+	};
+
+	rstctl4: reset@a0000 {
+		compatible = "nxp,rstctl";
+		reg = <0xa0000 0x1000>;
+		#reset-cells = <1>;
+	};
+
+	clkctl1: clkctl@41000 {
+		compatible = "nxp,lpc-syscon";
+		reg = <0x41000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	clkctl2: clkctl@65000 {
+		compatible = "nxp,lpc-syscon";
+		reg = <0x65000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	clkctl3: clkctl@61000 {
+		compatible = "nxp,lpc-syscon";
+		reg = <0x61000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	clkctl4: clkctl@a1000 {
+		compatible = "nxp,lpc-syscon";
+		reg = <0xa1000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	ctimer5: ctimer@48000 {
+		compatible = "nxp,lpc-ctimer";
+		reg = <0x48000 0x1000>;
+		interrupts = <7 0>;
+		status = "disabled";
+		clk-source = <1>;
+		clocks = <&clkctl1 MCUX_CTIMER5_CLK>;
+		mode = <0>;
+		input = <0>;
+		prescale = <0>;
+	};
+
+	ctimer6: ctimer@49000 {
+		compatible = "nxp,lpc-ctimer";
+		reg = <0x49000 0x1000>;
+		interrupts = <8 0>;
+		status = "disabled";
+		clk-source = <1>;
+		clocks = <&clkctl1 MCUX_CTIMER6_CLK>;
+		mode = <0>;
+		input = <0>;
+		prescale = <0>;
+	};
+
+	ctimer7: ctimer@4a000 {
+		compatible = "nxp,lpc-ctimer";
+		reg = <0x4a000 0x1000>;
+		interrupts = <9 0>;
+		status = "disabled";
+		clk-source = <1>;
+		clocks = <&clkctl1 MCUX_CTIMER7_CLK>;
+		mode = <0>;
+		input = <0>;
+		prescale = <0>;
+	};
+
+	syscon1: syscon@42000 {
+		compatible = "nxp,lpc-syscon";
+		reg = <0x42000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	syscon2: syscon@66000 {
+		compatible = "nxp,lpc-syscon";
+		reg = <0x66000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	syscon3: syscon@62000 {
+		compatible = "nxp,lpc-syscon";
+		reg = <0x62000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	syscon4: syscon@a2000 {
+		compatible = "nxp,lpc-syscon";
+		reg = <0xa2000 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	iocon1: iocon@64000 {
+		compatible = "nxp,lpc-iocon";
+		reg = <0x64000 0x1000>;
+		status = "okay";
+	};
+
+	iocon2: iocon@a5000 {
+		compatible = "nxp,lpc-iocon";
+		reg = <0xa5000 0x1000>;
+		status = "okay";
+	};
+
+	gpio8: gpio@320000 {
+		compatible = "nxp,kinetis-gpio";
+		status = "disabled";
+		reg = <0x320000 0x1000>;
+		interrupts = <61 0>,<62 0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		nxp,kinetis-port = <&gpio8>;
+		gpio-port-offest = <8>;
+	};
+
+	gpio9: gpio@322000 {
+		compatible = "nxp,kinetis-gpio";
+		status = "disabled";
+		reg = <0x322000 0x1000>;
+		interrupts = <63 0>,<64 0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		nxp,kinetis-port = <&gpio9>;
+		gpio-port-offest = <8>;
+	};
+
+	gpio10: gpio@324000 {
+		compatible = "nxp,kinetis-gpio";
+		status = "disabled";
+		reg = <0x324000 0x1000>;
+		interrupts = <65 0>,<66 0>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		nxp,kinetis-port = <&gpio10>;
+		gpio-port-offest = <8>;
+	};
+
+	flexcomm17: flexcomm@326000 {
+		compatible = "nxp,lp-flexcomm";
+		reg = <0x326000 0x1000>;
+		interrupts = <11 0>;
+		status = "disabled";
+
+		/* Empty ranges property implies parent and child address space is identical */
+		ranges = <>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flexcomm17_lpuart17: uart@326000 {
+			compatible = "nxp,lpuart";
+			reg = <0x326000 0x1000>;
+			clocks = <&clkctl1 MCUX_FLEXCOMM17_CLK>;
+			status = "disabled";
+		};
+		flexcomm17_lpspi17: lpspi@326000 {
+			compatible = "nxp,lpspi";
+			reg = <0x326000 0x1000>;
+			clocks = <&clkctl1 MCUX_FLEXCOMM17_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
+			status = "disabled";
+		};
+		flexcomm17_lpi2c17: lpi2c@326800 {
+			compatible = "nxp,lpi2c";
+			reg = <0x326800 0x1000>;
+			clocks = <&clkctl1 MCUX_FLEXCOMM17_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	flexcomm18: flexcomm@327000 {
+		compatible = "nxp,lp-flexcomm";
+		reg = <0x327000 0x1000>;
+		interrupts = <12 0>;
+		status = "disabled";
+
+		/* Empty ranges property implies parent and child address space is identical */
+		ranges = <>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flexcomm18_lpuart18: uart@327000 {
+			compatible = "nxp,lpuart";
+			reg = <0x327000 0x1000>;
+			clocks = <&clkctl1 MCUX_FLEXCOMM18_CLK>;
+			status = "disabled";
+		};
+		flexcomm18_lpspi18: lpspi@327000 {
+			compatible = "nxp,lpspi";
+			reg = <0x327000 0x1000>;
+			clocks = <&clkctl1 MCUX_FLEXCOMM18_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
+			status = "disabled";
+		};
+		flexcomm18_lpi2c18: lpi2c@327800 {
+			compatible = "nxp,lpi2c";
+			reg = <0x327800 0x1000>;
+			clocks = <&clkctl1 MCUX_FLEXCOMM18_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	flexcomm19: flexcomm@328000 {
+		compatible = "nxp,lp-flexcomm";
+		reg = <0x328000 0x1000>;
+		interrupts = <13 0>;
+		status = "disabled";
+
+		/* Empty ranges property implies parent and child address space is identical */
+		ranges = <>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flexcomm19_lpuart19: uart@328000 {
+			compatible = "nxp,lpuart";
+			reg = <0x328000 0x1000>;
+			clocks = <&clkctl1 MCUX_FLEXCOMM19_CLK>;
+			status = "disabled";
+		};
+		flexcomm19_lpspi19: lpspi@328000 {
+			compatible = "nxp,lpspi";
+			reg = <0x328000 0x1000>;
+			clocks = <&clkctl1 MCUX_FLEXCOMM19_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
+			status = "disabled";
+		};
+		flexcomm19_lpi2c19: lpi2c@328800 {
+			compatible = "nxp,lpi2c";
+			reg = <0x328800 0x1000>;
+			clocks = <&clkctl1 MCUX_FLEXCOMM19_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	flexcomm20: flexcomm@329000 {
+		compatible = "nxp,lp-flexcomm";
+		reg = <0x329000 0x1000>;
+		interrupts = <14 0>;
+		status = "disabled";
+
+		/* Empty ranges property implies parent and child address space is identical */
+		ranges = <>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		flexcomm20_lpuart20: uart@329000 {
+			compatible = "nxp,lpuart";
+			reg = <0x329000 0x1000>;
+			clocks = <&clkctl1 MCUX_FLEXCOMM20_CLK>;
+			status = "disabled";
+		};
+		flexcomm20_lpspi20: lpspi@329000 {
+			compatible = "nxp,lpspi";
+			reg = <0x329000 0x1000>;
+			clocks = <&clkctl1 MCUX_FLEXCOMM20_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			tx-fifo-size = <8>;
+			rx-fifo-size = <8>;
+			status = "disabled";
+		};
+		flexcomm20_lpi2c20: lpi2c@329800 {
+			compatible = "nxp,lpi2c";
+			reg = <0x329800 0x1000>;
+			clocks = <&clkctl1 MCUX_FLEXCOMM20_CLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	/* LPFlexcomm15 only support LPI2C function. */
+	lpi2c15: i2c@213000 {
+		compatible = "nxp,lpi2c";
+		reg = <0x213000 0x1000>;
+		interrupts = <14 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&clkctl4 MCUX_LPI2C15_CLK>;
+		status = "disabled";
+	};
+
+	os_timer_cpu1: timers@209000 {
+		compatible = "nxp,os-timer";
+		reg = <0x209000 0x1000>;
+		interrupts = <30 0>;
+		status = "disabled";
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};
+
+&systick {
+	/*
+	 * RT700 cm33_cpu1 relies by default on the OS Timer for system
+	 * clock implementation, so the SysTick node is not to be enabled.
+	 */
+	status = "disabled";
+};
diff --git a/dts/arm/nxp/nxp_rw6xx_common.dtsi b/dts/arm/nxp/nxp_rw6xx_common.dtsi
index 61f8fff8d11..7777fd81439 100644
--- a/dts/arm/nxp/nxp_rw6xx_common.dtsi
+++ b/dts/arm/nxp/nxp_rw6xx_common.dtsi
@@ -30,7 +30,7 @@
 			reg = <0>;
 			#address-cells = <1>;
 			#size-cells = <1>;
-			cpu-power-states = <&idle &suspend>;
+			cpu-power-states = <&idle &suspend &standby>;
 
 			mpu: mpu@e000ed90 {
 				compatible = "arm,armv8m-mpu";
@@ -58,6 +58,20 @@
 							<0x100>,
 							<0x0>;
 			};
+			/* This is the setting for Sleep Mode */
+			standby: standby {
+				compatible = "nxp,pdcfg-power", "zephyr,power-state";
+				power-state-name = "standby";
+				/* TODO: Revisit latency numbers */
+				min-residency-us = <5000>;
+				exit-latency-us = <1000>;
+				deep-sleep-config = <0x180000>,
+							<0x0>,
+							<0x4>,
+							<0x100>,
+							<0x0>;
+				status = "disabled";
+			};
 		};
 	};
 
@@ -69,12 +83,22 @@
 		ranges = <0x0 0x443C0000 DT_SIZE_K(140)>;
 	};
 
+	power_mode3_domain: power_mode3_domain {
+		compatible = "power-domain-soc-state-change";
+		onoff-power-states = <&standby>;
+		#power-domain-cells = <0>;
+	};
 };
 
 &sram {
 	#address-cells = <1>;
 	#size-cells = <1>;
 
+	/* RW6XX SRAM can be access by either code or data bus, determined
+	 * by the address used to access the memory.
+	 * Applications can override the reg properties of either
+	 * sram_data or sram_code nodes to change the balance of SRAM access partitioning.
+	 */
 	sram_data: memory@40000 {
 		compatible = "mmio-sram";
 		reg = <0x40000 DT_SIZE_K(960)>;
@@ -170,6 +194,7 @@
 		reg = <0x14000 0x1000>;
 		status = "okay";
 		interrupts = <123 0>;
+		power-domains = <&power_mode3_domain>;
 	};
 
 	wwdt: watchdog@e000 {
@@ -192,6 +217,7 @@
 			#gpio-cells = <2>;
 			reg = <0>;
 			int-source = "pint";
+			power-domains = <&power_mode3_domain>;
 		};
 
 		hsgpio1: gpio@1 {
@@ -200,6 +226,7 @@
 			#gpio-cells = <2>;
 			reg = <1>;
 			int-source = "pint";
+			power-domains = <&power_mode3_domain>;
 		};
 	};
 
@@ -209,6 +236,7 @@
 		interrupts = <50 1>;
 		interrupt-names = "usb_otg";
 		num-bidir-endpoints = <8>;
+		power-domains = <&power_mode3_domain>;
 		status = "disabled";
 	};
 
@@ -220,6 +248,8 @@
 		resets = <&rstctl1 NXP_SYSCON_RESET(0, 8)>;
 		dmas = <&dma0 0>, <&dma0 1>;
 		dma-names = "rx", "tx";
+		zephyr,disabling-power-states = <&suspend &standby>;
+		power-domains = <&power_mode3_domain>;
 		status = "disabled";
 	};
 
@@ -231,6 +261,8 @@
 		resets = <&rstctl1 NXP_SYSCON_RESET(0, 9)>;
 		dmas = <&dma0 2>, <&dma0 3>;
 		dma-names = "rx", "tx";
+		zephyr,disabling-power-states = <&suspend &standby>;
+		power-domains = <&power_mode3_domain>;
 		status = "disabled";
 	};
 
@@ -242,6 +274,8 @@
 		resets = <&rstctl1 NXP_SYSCON_RESET(0, 10)>;
 		dmas = <&dma0 4>, <&dma0 5>;
 		dma-names = "rx", "tx";
+		zephyr,disabling-power-states = <&suspend &standby>;
+		power-domains = <&power_mode3_domain>;
 		status = "disabled";
 	};
 
@@ -253,6 +287,8 @@
 		resets = <&rstctl1 NXP_SYSCON_RESET(0, 11)>;
 		dmas = <&dma0 6>, <&dma0 7>;
 		dma-names = "rx", "tx";
+		zephyr,disabling-power-states = <&suspend &standby>;
+		power-domains = <&power_mode3_domain>;
 		status = "disabled";
 	};
 
@@ -264,6 +300,8 @@
 		resets = <&rstctl1 NXP_SYSCON_RESET(0, 22)>;
 		dmas = <&dma0 26>, <&dma0 27>;
 		dma-names = "rx", "tx";
+		zephyr,disabling-power-states = <&suspend &standby>;
+		power-domains = <&power_mode3_domain>;
 		status = "disabled";
 	};
 
@@ -295,6 +333,7 @@
 		compatible = "nxp,wifi";
 		/* first index is the imu interrupt, the second is the wakeup done interrupt */
 		interrupts = <72 2>, <64 2>;
+		power-domains = <&power_mode3_domain>;
 	};
 
 	dma0: dma-controller@104000 {
@@ -304,6 +343,7 @@
 		status = "disabled";
 		#dma-cells = <1>;
 		dma-channels = <33>;
+		power-domains = <&power_mode3_domain>;
 	};
 
 	lcdic: lcdic@128000 {
@@ -315,6 +355,18 @@
 		#size-cells = <0>;
 		clocks = <&clkctl1 MCUX_LCDIC_CLK>;
 		dmas = <&dma0 0>;
+		power-domains = <&power_mode3_domain>;
+	};
+
+	rtc: rtc@30000 {
+		compatible = "nxp,lpc-rtc";
+		reg = <0x30000 0x1000>;
+		interrupts = <32 0>;
+		status = "disabled";
+		rtc_highres: rtc_highres {
+			compatible = "nxp,lpc-rtc-highres";
+			status = "disabled";
+		};
 	};
 
 	ctimer0: ctimer@28000 {
@@ -327,6 +379,7 @@
 		mode = <0>;
 		input = <0>;
 		prescale = <0>;
+		power-domains = <&power_mode3_domain>;
 	};
 
 	ctimer1: ctimer@29000 {
@@ -339,6 +392,7 @@
 		mode = <0>;
 		input = <0>;
 		prescale = <0>;
+		power-domains = <&power_mode3_domain>;
 	};
 
 	ctimer2: ctimer@2a000 {
@@ -351,6 +405,7 @@
 		mode = <0>;
 		input = <0>;
 		prescale = <0>;
+		power-domains = <&power_mode3_domain>;
 	};
 
 	ctimer3: ctimer@2b000 {
@@ -363,6 +418,7 @@
 		mode = <0>;
 		input = <0>;
 		prescale = <0>;
+		power-domains = <&power_mode3_domain>;
 	};
 
 	sctimer: pwm@146000 {
@@ -373,6 +429,7 @@
 		status = "disabled";
 		prescaler = <8>;
 		#pwm-cells = <3>;
+		power-domains = <&power_mode3_domain>;
 	};
 
 	mrt0: mrt@2d000 {
@@ -385,6 +442,7 @@
 		resets = <&rstctl1 NXP_SYSCON_RESET(2, 8)>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		power-domains = <&power_mode3_domain>;
 
 		mrt0_channel0: mrt0_channel@0 {
 			compatible = "nxp,mrt-channel";
@@ -418,6 +476,7 @@
 		resets = <&rstctl0 NXP_SYSCON_RESET(2, 26)>;
 		#address-cells = <1>;
 		#size-cells = <0>;
+		power-domains = <&power_mode3_domain>;
 
 		mrt1_channel0: mrt1_channel@0 {
 			compatible = "nxp,mrt-channel";
@@ -449,31 +508,28 @@
 		interrupts = <25 0>;
 		status = "disabled";
 		clocks = <&clkctl1 MCUX_DMIC_CLK>;
+		power-domains = <&power_mode3_domain>;
 
 		pdmc0: dmic-channel@0 {
 			reg = <0>;
-			compatible = "nxp,dmic-channel";
 			dmas = <&dma0 16>;
 			status = "disabled";
 		};
 
 		pdmc1: dmic-channel@1 {
 			reg = <1>;
-			compatible = "nxp,dmic-channel";
 			dmas = <&dma0 17>;
 			status = "disabled";
 		};
 
 		pdmc2: dmic-channel@2 {
 			reg = <2>;
-			compatible = "nxp,dmic-channel";
 			dmas = <&dma0 18>;
 			status = "disabled";
 		};
 
 		pdmc3: dmic-channel@3 {
 			reg = <3>;
-			compatible = "nxp,dmic-channel";
 			dmas = <&dma0 19>;
 			status = "disabled";
 		};
@@ -490,6 +546,7 @@
 			interrupts = <112 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
+			power-domains = <&power_mode3_domain>;
 		};
 
 		adc1: gau_adc1@38100 {
@@ -498,6 +555,7 @@
 			interrupts = <111 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
+			power-domains = <&power_mode3_domain>;
 		};
 
 		dac0: dac@38200 {
@@ -506,6 +564,7 @@
 			interrupts = <108 0>;
 			status = "disabled";
 			#io-channel-cells = <0>;
+			power-domains = <&power_mode3_domain>;
 		};
 	};
 
@@ -524,12 +583,14 @@
 
 	hci: hci_ble {
 		compatible = "nxp,hci-ble";
+		power-domains = <&power_mode3_domain>;
 	};
 
 	hdlc_rcp_if: hdlc_rcp_if {
 		compatible = "nxp,hdlc-rcp-if";
 		interrupts = <90 2>, <82 2>;
 		interrupt-names = "hdlc_rcp_if_int", "wakeup_int";
+		power-domains = <&power_mode3_domain>;
 	};
 
 	enet: enet@138000 {
@@ -543,18 +604,21 @@
 			nxp,mdio = <&enet_mdio>;
 			nxp,ptp-clock = <&enet_ptp_clock>;
 			status = "disabled";
+			power-domains = <&power_mode3_domain>;
 		};
 		enet_mdio: mdio {
 			compatible = "nxp,enet-mdio";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
+			power-domains = <&power_mode3_domain>;
 		};
 		enet_ptp_clock: ptp-clock {
 			compatible = "nxp,enet-ptp-clock";
 			interrupts = <116 0>;
 			status = "disabled";
 			clocks = <&clkctl1 MCUX_ENET_PLL>;
+			power-domains = <&power_mode3_domain>;
 		};
 	};
 };
diff --git a/dts/arm/nxp/nxp_s32k1xx.dtsi b/dts/arm/nxp/nxp_s32k1xx.dtsi
index 7173394c436..093914b3553 100644
--- a/dts/arm/nxp/nxp_s32k1xx.dtsi
+++ b/dts/arm/nxp/nxp_s32k1xx.dtsi
@@ -77,6 +77,8 @@
 			clocks = <&clock NXP_S32_LPSPI0_CLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <4>;
+			rx-fifo-size = <4>;
 			status = "disabled";
 		};
 
@@ -86,6 +88,8 @@
 			interrupts = <27 0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <4>;
+			rx-fifo-size = <4>;
 			status = "disabled";
 		};
 
@@ -95,6 +99,8 @@
 			interrupts = <28 0>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <4>;
+			rx-fifo-size = <4>;
 			status = "disabled";
 		};
 
diff --git a/dts/arm/nxp/nxp_s32k344_m7.dtsi b/dts/arm/nxp/nxp_s32k344_m7.dtsi
index 0020324b2a2..91628a3dad4 100644
--- a/dts/arm/nxp/nxp_s32k344_m7.dtsi
+++ b/dts/arm/nxp/nxp_s32k344_m7.dtsi
@@ -90,6 +90,7 @@
 			eirq0: eirq@40290010 {
 				compatible = "nxp,s32-siul2-eirq";
 				reg = <0x40290010 0xb4>;
+				#address-cells = <0>;
 				interrupts = <53 0>, <54 0>, <55 0>, <56 0>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
@@ -570,6 +571,8 @@
 			clocks = <&clock NXP_S32_LPSPI0_CLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <4>;
+			rx-fifo-size = <4>;
 			status = "disabled";
 		};
 
@@ -580,6 +583,8 @@
 			clocks = <&clock NXP_S32_LPSPI1_CLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <4>;
+			rx-fifo-size = <4>;
 			status = "disabled";
 		};
 
@@ -590,6 +595,8 @@
 			clocks = <&clock NXP_S32_LPSPI2_CLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <4>;
+			rx-fifo-size = <4>;
 			status = "disabled";
 		};
 
@@ -600,6 +607,8 @@
 			clocks = <&clock NXP_S32_LPSPI3_CLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <4>;
+			rx-fifo-size = <4>;
 			status = "disabled";
 		};
 
@@ -610,6 +619,8 @@
 			clocks = <&clock NXP_S32_LPSPI4_CLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <4>;
+			rx-fifo-size = <4>;
 			status = "disabled";
 		};
 
@@ -620,6 +631,8 @@
 			clocks = <&clock NXP_S32_LPSPI5_CLK>;
 			#address-cells = <1>;
 			#size-cells = <0>;
+			tx-fifo-size = <4>;
+			rx-fifo-size = <4>;
 			status = "disabled";
 		};
 
diff --git a/dts/arm/nxp/nxp_s32z27x_r52.dtsi b/dts/arm/nxp/nxp_s32z27x_r52.dtsi
index 013c80c87ea..0c976a30418 100644
--- a/dts/arm/nxp/nxp_s32z27x_r52.dtsi
+++ b/dts/arm/nxp/nxp_s32z27x_r52.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022-2024 NXP
+ * Copyright 2022-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -105,6 +105,7 @@
 			compatible = "arm,gic-v3", "arm,gic";
 			reg = <0x47800000 0x10000>,
 				<0x47900000 0x80000>;
+			#address-cells = <0>;
 			interrupt-controller;
 			#interrupt-cells = <4>;
 			status = "okay";
@@ -124,6 +125,7 @@
 			compatible = "nxp,s32-linflexd";
 			reg = <0x40170000 0x1000>;
 			interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN0_CLK>;
 			status = "disabled";
 		};
 
@@ -131,6 +133,7 @@
 			compatible = "nxp,s32-linflexd";
 			reg = <0x40180000 0x1000>;
 			interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN1_CLK>;
 			status = "disabled";
 		};
 
@@ -138,6 +141,7 @@
 			compatible = "nxp,s32-linflexd";
 			reg = <0x40190000 0x1000>;
 			interrupts = <GIC_SPI 214 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN2_CLK>;
 			status = "disabled";
 		};
 
@@ -145,6 +149,7 @@
 			compatible = "nxp,s32-linflexd";
 			reg = <0x40970000 0x1000>;
 			interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN3_CLK>;
 			status = "disabled";
 		};
 
@@ -152,6 +157,7 @@
 			compatible = "nxp,s32-linflexd";
 			reg = <0x40980000 0x1000>;
 			interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN4_CLK>;
 			status = "disabled";
 		};
 
@@ -159,6 +165,7 @@
 			compatible = "nxp,s32-linflexd";
 			reg = <0x40990000 0x1000>;
 			interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN5_CLK>;
 			status = "disabled";
 		};
 
@@ -166,6 +173,7 @@
 			compatible = "nxp,s32-linflexd";
 			reg = <0x42170000 0x1000>;
 			interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN6_CLK>;
 			status = "disabled";
 		};
 
@@ -173,6 +181,7 @@
 			compatible = "nxp,s32-linflexd";
 			reg = <0x42180000 0x1000>;
 			interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN7_CLK>;
 			status = "disabled";
 		};
 
@@ -180,6 +189,7 @@
 			compatible = "nxp,s32-linflexd";
 			reg = <0x42190000 0x1000>;
 			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN8_CLK>;
 			status = "disabled";
 		};
 
@@ -187,6 +197,7 @@
 			compatible = "nxp,s32-linflexd";
 			reg = <0x42980000 0x1000>;
 			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN9_CLK>;
 			status = "disabled";
 		};
 
@@ -194,6 +205,7 @@
 			compatible = "nxp,s32-linflexd";
 			reg = <0x42990000 0x1000>;
 			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN10_CLK>;
 			status = "disabled";
 		};
 
@@ -201,6 +213,7 @@
 			compatible = "nxp,s32-linflexd";
 			reg = <0x429a0000 0x1000>;
 			interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_LIN11_CLK>;
 			status = "disabled";
 		};
 
@@ -208,6 +221,7 @@
 			compatible = "nxp,s32-linflexd";
 			reg = <0x40330000 0x1000>;
 			interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			clocks = <&clock NXP_S32_MSCLIN_CLK>;
 			status = "disabled";
 		};
 
@@ -219,6 +233,7 @@
 			eirq0: eirq0@40520010 {
 				compatible = "nxp,s32-siul2-eirq";
 				reg = <0x40520010 0xb4>;
+				#address-cells = <0>;
 				interrupts = <GIC_SPI 514 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
@@ -270,6 +285,7 @@
 			eirq1: eirq1@40d20010 {
 				compatible = "nxp,s32-siul2-eirq";
 				reg = <0x40d20010 0xb4>;
+				#address-cells = <0>;
 				interrupts = <GIC_SPI 515 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
@@ -345,6 +361,7 @@
 			eirq4: eirq4@42520010 {
 				compatible = "nxp,s32-siul2-eirq";
 				reg = <0x42520010 0xb4>;
+				#address-cells = <0>;
 				interrupts = <GIC_SPI 516 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
@@ -418,6 +435,7 @@
 			eirq5: eirq5@42d20010 {
 				compatible = "nxp,s32-siul2-eirq";
 				reg = <0x42d20010 0xb4>;
+				#address-cells = <0>;
 				interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
 				interrupt-controller;
 				#interrupt-cells = <2>;
@@ -1259,5 +1277,193 @@
 			status = "disabled";
 		};
 
+		emios0: emios@420b0000 {
+			compatible = "nxp,s32-emios";
+			reg = <0x420b0000 0x4000>;
+			clocks = <&clock NXP_S32_P4_REG_INTF_CLK>;
+			internal-cnt = <0xFFFFFFFF>;
+			interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 285 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 286 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 287 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 288 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 289 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 290 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 291 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 292 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 293 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 294 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 295 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 296 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 297 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 298 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 299 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 300 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 301 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 302 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 303 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 304 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 305 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 306 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 307 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 308 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 309 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 310 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 311 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 312 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "0_CH0", "0_CH1", "0_CH2", "0_CH3", "0_CH4",
+					"0_CH5", "0_CH6", "0_CH7", "0_CH8", "0_CH9",
+					"0_CH10", "0_CH12", "0_CH14", "0_CH16",
+					"0_CH17", "0_CH18", "0_CH19", "0_CH20",
+					"0_CH21", "0_CH22", "0_CH23", "0_CH24",
+					"0_CH25", "0_CH26", "0_CH27", "0_CH28",
+					"0_CH29", "0_CH30", "0_CH31";
+			status = "disabled";
+
+			master_bus {
+				emios0_bus_a: emios0_bus_a {
+					channel = <23>;
+					bus-type = "BUS_A";
+					channel-mask = <0xFF7FFFFF>;
+					status = "disabled";
+				};
+
+				emios0_bus_b: emios0_bus_b {
+					channel = <0>;
+					bus-type = "BUS_B";
+					channel-mask = <0x000000FE>;
+					status = "disabled";
+				};
+
+				emios0_bus_c: emios0_bus_c {
+					channel = <8>;
+					bus-type = "BUS_C";
+					channel-mask = <0x0000FE00>;
+					status = "disabled";
+				};
+
+				emios0_bus_d: emios0_bus_d {
+					channel = <16>;
+					bus-type = "BUS_D";
+					channel-mask = <0x00FE0000>;
+					status = "disabled";
+				};
+
+				emios0_bus_e: emios0_bus_e {
+					channel = <24>;
+					bus-type = "BUS_E";
+					channel-mask = <0xFE000000>;
+					status = "disabled";
+				};
+			};
+
+			pwm {
+				compatible = "nxp,s32-emios-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+		};
+
+		emios1: emios@400b0000 {
+			compatible = "nxp,s32-emios";
+			reg = <0x400b0000 0x4000>;
+			clocks = <&clock NXP_S32_P0_REG_INTF_CLK>;
+			internal-cnt = <0xFFFFFFFF>;
+			interrupts = <GIC_SPI 314 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 315 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 316 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 317 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 318 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 319 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 320 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 321 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 322 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 323 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 324 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 325 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 326 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 327 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 328 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 329 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 330 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 331 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 332 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 333 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 334 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 335 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 336 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 337 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 338 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 339 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 340 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 341 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "1_CH0", "1_CH1", "1_CH2", "1_CH3", "1_CH4",
+					"1_CH5", "1_CH6", "1_CH7", "1_CH8", "1_CH10",
+					"1_CH12", "1_CH14", "1_CH16", "1_CH17",
+					"1_CH18", "1_CH19", "1_CH20", "1_CH21",
+					"1_CH22", "1_CH23", "1_CH24", "1_CH25",
+					"1_CH26", "1_CH27", "1_CH28", "1_CH29",
+					"1_CH30", "1_CH31";
+			status = "disabled";
+
+			master_bus {
+				emios1_bus_a: emios1_bus_a {
+					channel = <23>;
+					bus-type = "BUS_A";
+					channel-mask = <0xFF7FFFFF>;
+					status = "disabled";
+				};
+
+				emios1_bus_b: emios1_bus_b {
+					channel = <0>;
+					bus-type = "BUS_B";
+					channel-mask = <0x000000FE>;
+					status = "disabled";
+				};
+
+				emios1_bus_c: emios1_bus_c {
+					channel = <8>;
+					bus-type = "BUS_C";
+					channel-mask = <0x0000FE00>;
+					status = "disabled";
+				};
+
+				emios1_bus_d: emios1_bus_d {
+					channel = <16>;
+					bus-type = "BUS_D";
+					channel-mask = <0x00FE0000>;
+					status = "disabled";
+				};
+
+				emios1_bus_e: emios1_bus_e {
+					channel = <24>;
+					channel-mask = <0xFE000000>;
+					bus-type = "BUS_E";
+					status = "disabled";
+				};
+			};
+
+			pwm {
+				compatible = "nxp,s32-emios-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+		};
+
+		qspi0: qspi@42320000 {
+			compatible = "nxp,s32-qspi";
+			reg = <0x42320000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		qspi1: qspi@42340000 {
+			compatible = "nxp,s32-qspi";
+			reg = <0x42340000 0x4000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/dts/arm/oct/osd32mp15x.dtsi b/dts/arm/oct/osd32mp15x.dtsi
new file mode 100644
index 00000000000..d69ca3b0aa4
--- /dev/null
+++ b/dts/arm/oct/osd32mp15x.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024 Antmicro <www.antmicro.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/mp1/stm32mp157.dtsi>
+#include <st/mp1/stm32mp157facx-pinctrl.dtsi>
+
+&mailbox {
+	status = "okay";
+};
+
+&rcc {
+	clock-frequency = <DT_FREQ_M(209)>;
+};
+
+&spi4 {
+	pinctrl-0 = <&spi4_nss_pe11 &spi4_sck_pe12
+		     &spi4_miso_pe13 &spi4_mosi_pe14>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi b/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi
index 6398674e0e0..9c20584c710 100644
--- a/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi
+++ b/dts/arm/raspberrypi/rpi_pico/rp2040.dtsi
@@ -238,14 +238,27 @@
 				 "gpin0", "gpin1";
 		};
 
-		gpio0: gpio@40014000 {
+		gpio0_map: gpio@40014000 {
 			compatible = "raspberrypi,pico-gpio";
 			reg = <0x40014000 DT_SIZE_K(4)>;
 			interrupts = <13 RPI_PICO_DEFAULT_IRQ_PRIORITY>;
-			gpio-controller;
+
+			gpio-map-mask = <0xffffffe0 0xffffffc0>;
+			gpio-map-pass-thru = <0x1f 0x3f>;
+			gpio-map = <0x0 0x0 &gpio0 0x0 0x0>;
+
 			#gpio-cells = <2>;
-			status = "disabled";
-			ngpios = <30>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio0: gpio-port@0 {
+				compatible = "raspberrypi,pico-gpio-port";
+				reg = <0x0>;
+				status = "disabled";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <30>;
+			};
 		};
 
 		uart0: uart@40034000 {
diff --git a/dts/arm/raspberrypi/rpi_pico/rp2350.dtsi b/dts/arm/raspberrypi/rpi_pico/rp2350.dtsi
index 687cafc19aa..62da179b667 100644
--- a/dts/arm/raspberrypi/rpi_pico/rp2350.dtsi
+++ b/dts/arm/raspberrypi/rpi_pico/rp2350.dtsi
@@ -235,13 +235,36 @@
 				 "gpin0", "gpin1";
 		};
 
-		gpio0: gpio@40028000 {
+		gpio0_map: gpio@40028000 {
 			compatible = "raspberrypi,pico-gpio";
 			reg = <0x40028000 DT_SIZE_K(4)>;
 			interrupts = <21 RPI_PICO_DEFAULT_IRQ_PRIORITY>;
-			gpio-controller;
+
+			gpio-map-mask = <0xffffffe0 0xffffffc0>;
+			gpio-map-pass-thru = <0x1f 0x3f>;
+			gpio-map = <0x00 0x0 &gpio0 0x0 0x0
+				    0x20 0x0 &gpio0_hi 0x0 0x0>;
 			#gpio-cells = <2>;
-			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio0: gpio-port@0 {
+				compatible = "raspberrypi,pico-gpio-port";
+				reg = <0x0>;
+				status = "disabled";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+			};
+
+			gpio0_hi: gpio-port@1 {
+				compatible = "raspberrypi,pico-gpio-port";
+				reg = <0x1>;
+				status = "disabled";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <32>;
+			};
 		};
 
 		uart0: uart@40070000 {
@@ -390,9 +413,9 @@
 			#dma-cells = <3>;
 		};
 
-		usbd: usbd@50100000 {
+		usbd: usbd@50110000 {
 			compatible = "raspberrypi,pico-usbd";
-			reg = <0x50100000 0x10000>;
+			reg = <0x50110000 0x10000>;
 			resets = <&reset RPI_PICO_RESETS_RESET_USBCTRL>;
 			clocks = <&clocks RPI_PICO_CLKID_CLK_USB>;
 			interrupts = <14 RPI_PICO_DEFAULT_IRQ_PRIORITY>;
diff --git a/dts/arm/raspberrypi/rpi_pico/rp2350b.dtsi b/dts/arm/raspberrypi/rpi_pico/rp2350b.dtsi
new file mode 100644
index 00000000000..55b67427237
--- /dev/null
+++ b/dts/arm/raspberrypi/rpi_pico/rp2350b.dtsi
@@ -0,0 +1,13 @@
+#include <arm/raspberrypi/rpi_pico/rp2350.dtsi>
+
+&gpio0 {
+	ngpios = <32>;
+};
+
+&gpio0_hi {
+	ngpios = <16>;
+};
+
+&die_temp {
+	io-channels = <&adc 8>;
+};
diff --git a/dts/arm/realtek/ec/rts5912-pinctrl.dtsi b/dts/arm/realtek/ec/rts5912-pinctrl.dtsi
index 3ac81a34862..ce08a65be52 100644
--- a/dts/arm/realtek/ec/rts5912-pinctrl.dtsi
+++ b/dts/arm/realtek/ec/rts5912-pinctrl.dtsi
@@ -266,105 +266,145 @@
 			pinmux = <REALTEK_RTS5912_PINMUX(41, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ kso1_gpio042: kso1_gpio042 {
 			pinmux = <REALTEK_RTS5912_PINMUX(42, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ kso2_gpio043: kso2_gpio043 {
 			pinmux = <REALTEK_RTS5912_PINMUX(43, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ kso3_gpio044: kso3_gpio044 {
 			pinmux = <REALTEK_RTS5912_PINMUX(44, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 
 	/omit-if-no-ref/ kso4_gpio045: kso4_gpio045 {
 			pinmux = <REALTEK_RTS5912_PINMUX(45, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ kso5_gpio046: kso5_gpio046 {
 			pinmux = <REALTEK_RTS5912_PINMUX(46, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ kso6_gpio047: kso6_gpio047 {
 			pinmux = <REALTEK_RTS5912_PINMUX(47, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ kso7_gpio048: kso7_gpio048 {
 			pinmux = <REALTEK_RTS5912_PINMUX(48, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 
 	/omit-if-no-ref/ kso8_gpio049: kso8_gpio049 {
 			pinmux = <REALTEK_RTS5912_PINMUX(49, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ kso9_gpio050: kso9_gpio050 {
 			pinmux = <REALTEK_RTS5912_PINMUX(50, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ kso10_gpio051: kso10_gpio051 {
 			pinmux = <REALTEK_RTS5912_PINMUX(51, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ kso11_gpio055: kso11_gpio055 {
 			pinmux = <REALTEK_RTS5912_PINMUX(55, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 
 	/omit-if-no-ref/ kso12_gpio056: kso12_gpio056 {
 			pinmux = <REALTEK_RTS5912_PINMUX(56, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ kso13_gpio057: kso13_gpio057 {
 			pinmux = <REALTEK_RTS5912_PINMUX(57, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ kso14_gpio058: kso14_gpio058 {
 			pinmux = <REALTEK_RTS5912_PINMUX(58, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ kso15_gpio059: kso15_gpio059 {
 			pinmux = <REALTEK_RTS5912_PINMUX(59, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 
 	/omit-if-no-ref/ kso16_gpio060: kso16_gpio060 {
 			pinmux = <REALTEK_RTS5912_PINMUX(60, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ kso17_gpio061: kso17_gpio061 {
 			pinmux = <REALTEK_RTS5912_PINMUX(61, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ kso18_gpio092: kso18_gpio092 {
 			pinmux = <REALTEK_RTS5912_PINMUX(92, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ kso19_gpio093: kso19_gpio093 {
 			pinmux = <REALTEK_RTS5912_PINMUX(93, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/* KSO PINCTRL SETTING END */
 	/* KSI PINCTRL SETTING START */
@@ -372,53 +412,73 @@
 			pinmux = <REALTEK_RTS5912_PINMUX(64, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ ksi1_gpio065: ksi1_gpio065 {
 			pinmux = <REALTEK_RTS5912_PINMUX(65, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ ksi2_gpio066: ksi2_gpio066 {
 			pinmux = <REALTEK_RTS5912_PINMUX(66, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ ksi3_gpio067: ksi3_gpio067 {
 			pinmux = <REALTEK_RTS5912_PINMUX(67, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 
 	/omit-if-no-ref/ ksi4_gpio068: ksi4_gpio068 {
 			pinmux = <REALTEK_RTS5912_PINMUX(68, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ ksi5_gpio069: ksi5_gpio069 {
 			pinmux = <REALTEK_RTS5912_PINMUX(69, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ ksi6_gpio070: ksi6_gpio070 {
 			pinmux = <REALTEK_RTS5912_PINMUX(70, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ ksi7_gpio071: ksi7_gpio071 {
 			pinmux = <REALTEK_RTS5912_PINMUX(71, FUNC1)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 
 	/omit-if-no-ref/ ksi8_gpio054: ksi8_gpio054 {
 			pinmux = <REALTEK_RTS5912_PINMUX(54, FUNC3)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/omit-if-no-ref/ ksi9_gpio098: ksi9_gpio098 {
 			pinmux = <REALTEK_RTS5912_PINMUX(98, FUNC2)>;
 			input-enable;
 			input-schmitt-enable;
+			bias-pull-up;
+			drive-open-drain;
 	};
 	/* KSO PINCTRL SETTING END */
 	/* KSM PINCTRL SETTING END */
diff --git a/dts/arm/realtek/ec/rts5912.dtsi b/dts/arm/realtek/ec/rts5912.dtsi
index aa994898109..0231ce9ea79 100644
--- a/dts/arm/realtek/ec/rts5912.dtsi
+++ b/dts/arm/realtek/ec/rts5912.dtsi
@@ -6,6 +6,7 @@
  */
 
 #include <arm/armv8-m.dtsi>
+#include <zephyr/dt-bindings/adc/adc.h>
 #include <zephyr/dt-bindings/clock/rts5912_clock.h>
 #include <zephyr/dt-bindings/gpio/realtek-gpio.h>
 
@@ -65,6 +66,12 @@
 		interrupt-parent = <&nvic>;
 		ranges;
 
+		bbram: bb-ram@40005000 {
+			compatible = "realtek,rts5912-bbram";
+			reg = <0x40005000 0x100>;
+			status = "okay";
+		};
+
 		sccon: clock-controller@40020000 {
 			compatible = "realtek,rts5912-sccon";
 			reg = <0x40020000 0xf0>;
@@ -73,6 +80,92 @@
 			clock-names = "rc25m", "pll";
 		};
 
+		rtc: rtc@4000c100 {
+			compatible = "realtek,rts5912-rtc";
+			reg = <0x4000c100 0x20>;
+			clocks = <&sccon RTS5912_SCCON_PERIPH_GRP2 PERIPH_GRP2_RTC_CLKPWR>;
+			clock-names = "rtc";
+			status = "disabled";
+		};
+
+		timer0: timer@4000c300 {
+			compatible = "realtek,rts5912-timer";
+			reg = < 0x4000c300 0x14 >;
+			interrupt-parent = <&nvic>;
+			interrupts = <196 0>;
+			clocks = <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_TMR0_CLKPWR>;
+			clock-names = "tmr32";
+			max-value = <0xFFFFFFFF>;
+			clock-frequency = <25000000>;
+			prescaler = <0>;
+			status = "disabled";
+		};
+
+		timer1: timer@4000c314 {
+			compatible = "realtek,rts5912-timer";
+			reg = < 0x4000c314 0x14 >;
+			interrupt-parent = <&nvic>;
+			interrupts = <197 0>;
+			clocks = <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_TMR1_CLKPWR>;
+			clock-names = "tmr32";
+			max-value = <0xFFFFFFFF>;
+			clock-frequency = <25000000>;
+			prescaler = <0>;
+			status = "disabled";
+		};
+
+		timer2: timer@4000c328 {
+			compatible = "realtek,rts5912-timer";
+			reg = < 0x4000c328 0x14 >;
+			interrupt-parent = <&nvic>;
+			interrupts = <198 0>;
+			clocks = <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_TMR2_CLKPWR>;
+			clock-names = "tmr32";
+			max-value = <0xFFFFFFFF>;
+			clock-frequency = <25000000>;
+			prescaler = <0>;
+			status = "disabled";
+		};
+
+		timer3: timer@4000c33c {
+			compatible = "realtek,rts5912-timer";
+			reg = < 0x4000c33c 0x14 >;
+			interrupt-parent = <&nvic>;
+			interrupts = <199 0>;
+			clocks = <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_TMR3_CLKPWR>;
+			clock-names = "tmr32";
+			max-value = <0xFFFFFFFF>;
+			clock-frequency = <25000000>;
+			prescaler = <0>;
+			status = "disabled";
+		};
+
+		timer4: timer@4000c350 {
+			compatible = "realtek,rts5912-timer";
+			reg = < 0x4000c350 0x14 >;
+			interrupt-parent = <&nvic>;
+			interrupts = <200 0>;
+			clocks = <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_TMR4_CLKPWR>;
+			clock-names = "tmr32";
+			max-value = <0xFFFFFFFF>;
+			clock-frequency = <25000000>;
+			prescaler = <0>;
+			status = "disabled";
+		};
+
+		timer5: timer@4000c364 {
+			compatible = "realtek,rts5912-timer";
+			reg = < 0x4000c364 0x14 >;
+			interrupt-parent = <&nvic>;
+			interrupts = <201 0>;
+			clocks = <&sccon RTS5912_SCCON_PERIPH_GRP1 PERIPH_GRP1_TMR5_CLKPWR>;
+			clock-names = "tmr32";
+			max-value = <0xFFFFFFFF>;
+			clock-frequency = <25000000>;
+			prescaler = <0>;
+			status = "disabled";
+		};
+
 		slwtmr0: slwtmr0@4000c200 {
 			compatible = "realtek,rts5912-slwtimer";
 			reg = <0x4000c200 0x10>;
@@ -82,7 +175,7 @@
 			max-value = <0xFFFFFFFF>;
 			clock-frequency = <1000000>;
 			prescaler = <0>;
-			status = "okay";
+			status = "disabled";
 		};
 
 		rtmr: rtmr@4000c500 {
@@ -92,6 +185,15 @@
 			status = "okay";
 		};
 
+		adc0: adc@4000fe00 {
+			compatible = "realtek,rts5912-adc";
+			reg = <0x4000fe00 0x38>;
+			clocks = <&sccon RTS5912_SCCON_ADC ADC0_CLKPWR>;
+			interrupts = <221 0>;
+			#io-channel-cells = <1>;
+			status = "disabled";
+		};
+
 		uart0: uart@40010100 {
 			compatible = "ns16550";
 			reg = <0x40010100 0x100>;
@@ -233,6 +335,35 @@
 					      140 0 141 0 142 0 143 0>;
 			};
 		};
+
+		wdog: watchdog@4000c000 {
+			compatible = "realtek,rts5912-watchdog";
+			reg = <0x4000c000 0x14>;
+			interrupt-parent = <&nvic>;
+			interrupts = <209 0>;
+			clocks = <&sccon RTS5912_SCCON_PERIPH_GRP2 PERIPH_GRP2_WDT_CLKPWR>;
+			clock-names = "watchdog";
+			clk-divider = <33>;
+			status = "disabled";
+		};
+
+		kbd: kbd@40010000 {
+			compatible = "realtek,rts5912-kbd";
+			reg = <0x40010000 0x10>;
+			clocks = <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_KBM_CLKPWR>;
+			interrupts = <210 0>;
+			interrupt-parent = <&nvic>;
+			status = "disabled";
+		};
+
+		tach0: tach@4000fd00 {
+			compatible = "realtek,rts5912-tach";
+			reg = <0x4000fd00 0x40>;
+			clocks = <&sccon RTS5912_SCCON_PERIPH_GRP0 PERIPH_GRP0_TACH0_CLKPWR>;
+			clock-names = "tacho";
+			interrupts = <192 0>;
+			status = "disabled";
+		};
 	};
 
 	swj_port: swj-port {
@@ -241,6 +372,45 @@
 			     &jtag_clk_gpio90 &jtag_tms_gpio91>;
 		pinctrl-names = "default";
 	};
+
+	ulpm: ulpm {
+		compatible = "realtek,rts5912-ulpm";
+		wkup-pins-max = <6>; /* 6 system wake-up pins */
+		status = "disabled";
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		wkup-pin@0 {
+			reg = <0x0>;
+			wkup-pin-mode = "gpio";
+		};
+
+		wkup-pin@1 {
+			reg = <0x1>;
+			wkup-pin-mode = "gpio";
+		};
+
+		wkup-pin@2 {
+			reg = <0x2>;
+			wkup-pin-mode = "gpio";
+		};
+
+		wkup-pin@3 {
+			reg = <0x3>;
+			wkup-pin-mode = "gpio";
+		};
+
+		wkup-pin@4 {
+			reg = <0x4>;
+			wkup-pin-mode = "gpio";
+		};
+
+		wkup-pin@5 {
+			reg = <0x5>;
+			wkup-pin-mode = "gpio";
+		};
+	};
 };
 
 &nvic {
diff --git a/dts/arm/renesas/ra/r7fa4m1ab3cfm.dtsi b/dts/arm/renesas/ra/r7fa4m1ab3cfm.dtsi
deleted file mode 100644
index 8a1702d785a..00000000000
--- a/dts/arm/renesas/ra/r7fa4m1ab3cfm.dtsi
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#define RA_SOC_PINS 64
-#define RA_SOC_HAS_MSTPCRE 1
-#define RA_SOC_MSTPD5_CHANNELS 1
-
-#include <renesas/ra/ra4-cm4-common.dtsi>
diff --git a/dts/arm/renesas/ra/ra-cm4-common.dtsi b/dts/arm/renesas/ra/ra-cm4-common.dtsi
deleted file mode 100644
index 5930631e5ea..00000000000
--- a/dts/arm/renesas/ra/ra-cm4-common.dtsi
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <mem.h>
-#include <freq.h>
-#include <arm/armv7-m.dtsi>
-#include <zephyr/dt-bindings/interrupt-controller/renesas-ra-icu.h>
-#include <zephyr/dt-bindings/clock/ra_clock.h>
-
-/ {
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-m4";
-			reg = <0>;
-		};
-	};
-
-	clocks: clocks {
-		xtal: clock-main-osc {
-			compatible = "renesas,ra-cgc-external-clock";
-			clock-frequency = <1200000>;
-			status = "disabled";
-			#clock-cells = <0>;
-		};
-
-		subclk: clock-subclk {
-			compatible = "renesas,ra-cgc-subclk";
-			clock-frequency = <32768>;
-			status = "disabled";
-			#clock-cells = <0>;
-		};
-
-		hoco: clock-hoco {
-			compatible = "fixed-clock";
-			clock-frequency = <24000000>;
-			status = "okay";
-			#clock-cells = <0>;
-		};
-
-		moco: clock-moco {
-			compatible = "fixed-clock";
-			clock-frequency = <8000000>;
-			status = "okay";
-			#clock-cells = <0>;
-		};
-
-		loco: clock-loco {
-			compatible = "fixed-clock";
-			clock-frequency = <32768>;
-			status = "okay";
-			#clock-cells = <0>;
-		};
-
-		pll: pll {
-			compatible = "renesas,ra-cgc-pll";
-			#clock-cells = <0>;
-
-			/* PLL */
-			clocks = <&xtal>;
-			div = <2>;
-			mul = <8 0>;
-			status = "disabled";
-		};
-	};
-
-	sram0: memory0@20000000 {
-		compatible = "mmio-sram";
-		reg = <0x20000000 DT_SIZE_K(32)>;
-	};
-
-	soc {
-		interrupt-parent = <&icu>;
-		icu: interrupt-controller@40006000 {
-			compatible = "renesas,ra-interrupt-controller-unit";
-			reg = <0x40006000 0x40>;
-			reg-names = "icu";
-			interrupt-controller;
-			#interrupt-cells = <3>;
-		};
-
-		pclkblock: pclkblock@4001e01c {
-			compatible = "renesas,ra-cgc-pclk-block";
-			reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>,
-			      <0x40047008 4>;
-			reg-names = "MSTPA", "MSTPB","MSTPC",
-				    "MSTPD";
-			compatible = "renesas,ra-cgc-pclk-block";
-			#clock-cells = <0>;
-			clocks = <&moco>;
-			status = "okay";
-
-			iclk: iclk {
-				compatible = "renesas,ra-cgc-pclk";
-				div = <16>;
-				#clock-cells = <2>;
-				status = "okay";
-			};
-
-			pclka: pclka {
-				compatible = "renesas,ra-cgc-pclk";
-				div = <16>;
-				#clock-cells = <2>;
-				status = "okay";
-			};
-
-			pclkb: pclkb {
-				compatible = "renesas,ra-cgc-pclk";
-				div = <16>;
-				#clock-cells = <2>;
-				status = "okay";
-			};
-
-			pclkc: pclkc {
-				compatible = "renesas,ra-cgc-pclk";
-				div = <1>;
-				#clock-cells = <2>;
-				status = "okay";
-			};
-
-			pclkd: pclkd {
-				compatible = "renesas,ra-cgc-pclk";
-				div = <16>;
-				#clock-cells = <2>;
-				status = "okay";
-			};
-
-			fclk: fclk {
-				compatible = "renesas,ra-cgc-pclk";
-				div = <16>;
-				#clock-cells = <2>;
-				status = "okay";
-			};
-
-			clkout: clkout {
-				compatible = "renesas,ra-cgc-pclk";
-				#clock-cells = <2>;
-				status = "disabled";
-			};
-		};
-
-		fcu: flash-controller@4001c000 {
-			compatible = "renesas,ra-flash-controller";
-			reg = <0x4001c000 0x44>;
-			reg-names = "fcache";
-
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			flash0: flash0@0 {
-				compatible = "soc-nv-flash";
-				reg = <0x00000000 DT_SIZE_K(256)>;
-			};
-
-			flash1: flash1@40100000 {
-				compatible = "soc-nv-flash";
-				reg = <0x40100000 DT_SIZE_K(8)>;
-			};
-		};
-
-		ioport0: gpio@40040000 {
-			compatible = "renesas,ra-gpio";
-			reg = <0x40040000 0x20>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <16>;
-			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ2>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ3>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ6>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ7>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ10>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ15>;
-			interrupt-names = "port-irq2", "port-irq3", "port-irq6",
-					  "port-irq7", "port-irq10", "port-irq15";
-			port-irq2-pins = <2>;
-			port-irq3-pins = <4>;
-			port-irq6-pins = <0>;
-			port-irq7-pins = <1 15>;
-			port-irq10-pins = <5>;
-			port-irq15-pins = <11>;
-			status = "disabled";
-		};
-
-		ioport1: gpio@40040020 {
-			compatible = "renesas,ra-gpio";
-			reg = <0x40040020 0x20>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ0>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ1>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ2>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ3>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ4>;
-			interrupt-names = "port-irq0", "port-irq1", "port-irq2",
-					  "port-irq3", "port-irq4";
-			port-irq0-pins = <5>;
-			port-irq1-pins = <1>;
-			port-irq2-pins = <0>;
-			port-irq3-pins = <10>;
-			port-irq4-pins = <11>;
-			ngpios = <16>;
-			status = "disabled";
-		};
-
-		ioport2: gpio@40040040 {
-			compatible = "renesas,ra-gpio";
-			reg = <0x40040040 0x20>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <16>;
-			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ0>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ1>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ2>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ3>;
-			interrupt-names = "port-irq0", "port-irq1", "port-irq2",
-					  "port-irq3";
-			port-irq0-pins = <6>;
-			port-irq1-pins = <5>;
-			port-irq2-pins = <13>;
-			port-irq3-pins = <12>;
-			status = "disabled";
-		};
-
-		ioport3: gpio@40040060 {
-			compatible = "renesas,ra-gpio";
-			reg = <0x40040060 0x20>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <16>;
-			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ5>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ6>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ8>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ9>;
-			interrupt-names = "port-irq5", "port-irq6", "port-irq8", "port-irq9";
-			port-irq5-pins = <2>;
-			port-irq6-pins = <1>;
-			port-irq8-pins = <5>;
-			port-irq9-pins = <4>;
-			status = "disabled";
-		};
-
-		ioport4: gpio@40040080 {
-			compatible = "renesas,ra-gpio";
-			reg = <0x40040080 0x20>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <16>;
-			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ0>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ4>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ5>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ6>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ7>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ8>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ9>;
-			interrupt-names = "port-irq0", "port-irq4", "port-irq5", "port-irq6",
-					  "port-irq7", "port-irq8", "port-irq9";
-			port-irq0-pins = <0>;
-			port-irq4-pins = <2 11>;
-			port-irq5-pins = <1 10>;
-			port-irq6-pins = <9>;
-			port-irq7-pins = <8>;
-			port-irq8-pins = <15>;
-			port-irq9-pins = <14>;
-			status = "disabled";
-		};
-
-		ioport5: gpio@400400a0 {
-			compatible = "renesas,ra-gpio";
-			reg = <0x400400a0 0x20>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <16>;
-			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ11>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ12>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_PORT_IRQ14>;
-			interrupt-names = "port-irq11", "port-irq12", "port-irq14";
-			port-irq11-pins = <1>;
-			port-irq12-pins = <2>;
-			port-irq14-pins = <5>;
-			status = "disabled";
-		};
-
-		pinctrl: pinctrl@40040800 {
-			compatible = "renesas,ra-pinctrl-pfs";
-			reg = <0x40040800 0x500 0x40040d03 0x1>;
-			reg-names = "pfs", "pmisc_pwpr";
-			status = "okay";
-		};
-
-		sci0: sci@40070000 {
-			compatible = "renesas,ra-sci";
-			reg = <0x40070000 0x20>;
-			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_RXI>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_TXI>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_TEI>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_ERI>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_AM>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI0_RXI_OR_ERI>;
-			interrupt-names = "rxi", "txi", "tei", "eri", "am", "rxi-or-eri";
-			clocks = <&pclka MSTPB 31>;
-			#clock-cells = <1>;
-			status = "disabled";
-			uart {
-				compatible = "renesas,ra-uart-sci";
-				status = "disabled";
-			};
-		};
-
-		sci1: sci@40070020 {
-			compatible = "renesas,ra-sci";
-			reg = <0x40070020 0x20>;
-			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_RXI>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_TXI>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_TEI>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_ERI>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI1_AM>;
-			interrupt-names = "rxi", "txi", "tei", "eri", "am";
-			clocks = <&pclka MSTPB 30>;
-			#clock-cells = <1>;
-			status = "disabled";
-			uart {
-				compatible = "renesas,ra-uart-sci";
-				status = "disabled";
-			};
-		};
-
-		sci9: sci@40070120 {
-			compatible = "renesas,ra-sci";
-			reg = <0x40070120 0x20>;
-			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_RXI>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_TXI>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_TEI>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_ERI>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI9_AM>;
-			interrupt-names = "rxi", "txi", "tei", "eri", "am";
-			clocks = <&pclka MSTPB 22>;
-			#clock-cells = <1>;
-			status = "disabled";
-			uart {
-				compatible = "renesas,ra-uart-sci";
-				status = "disabled";
-			};
-		};
-	};
-};
-
-&nvic {
-	arm,num-irq-priority-bits = <4>;
-};
diff --git a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi
index f06f9e9965e..d6e38b79bc3 100644
--- a/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi
+++ b/dts/arm/renesas/ra/ra2/r7fa2a1xh.dtsi
@@ -91,6 +91,13 @@
 			compatible = "renesas,ra-trng";
 			status = "disabled";
 		};
+
+		wdt: wdt@40044200 {
+			compatible = "renesas,ra-wdt";
+			reg = <0x40044200 0x200>;
+			clocks = <&pclkb 0 0>;
+			status = "disabled";
+		};
 	};
 
 	clocks: clocks {
@@ -141,6 +148,7 @@
 
 			iclk: iclk {
 				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <48000000>;
 				div = <1>;
 				#clock-cells = <2>;
 				status = "okay";
@@ -173,12 +181,17 @@
 				status = "disabled";
 			};
 
-
 			sdadcclk: sdadcclk {
 				compatible = "renesas,ra-cgc-pclk";
 				#clock-cells = <2>;
 				status = "disabled";
 			};
+
+			uclk: uclk {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
 		};
 	};
 };
@@ -251,3 +264,8 @@
 	port-irq2-pins = <1>;
 	port-irq3-pins = <0>;
 };
+
+&dac_global {
+	has-chargepump;
+	has-davrefcr;
+};
diff --git a/dts/arm/renesas/ra/ra2/r7fa2l1x9.dtsi b/dts/arm/renesas/ra/ra2/r7fa2l1x9.dtsi
new file mode 100644
index 00000000000..e20c0501335
--- /dev/null
+++ b/dts/arm/renesas/ra/ra2/r7fa2l1x9.dtsi
@@ -0,0 +1,12 @@
+/**
+ * Copyright (c) 2024 MUNIC SA
+ *
+ * Renesas R7FA2AL1x9 MCU device tree
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+&flash0 {
+	reg = <0x0 DT_SIZE_K(128)>;
+};
diff --git a/dts/arm/renesas/ra/ra2/r7fa2l1xb.dtsi b/dts/arm/renesas/ra/ra2/r7fa2l1xb.dtsi
new file mode 100644
index 00000000000..b148a4337eb
--- /dev/null
+++ b/dts/arm/renesas/ra/ra2/r7fa2l1xb.dtsi
@@ -0,0 +1,11 @@
+/**
+ * Copyright (c) 2024 MUNIC SA
+ *
+ * Renesas R7FA2AL1AB MCU device tree
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&flash0 {
+	reg = <0x0 DT_SIZE_K(256)>;
+};
diff --git a/dts/arm/renesas/ra/ra2/r7fa2l1xxxxfp.dtsi b/dts/arm/renesas/ra/ra2/r7fa2l1xxxxfp.dtsi
new file mode 100644
index 00000000000..a55ae8fa6f9
--- /dev/null
+++ b/dts/arm/renesas/ra/ra2/r7fa2l1xxxxfp.dtsi
@@ -0,0 +1,88 @@
+/**
+ * Copyright (c) 2024 MUNIC SA
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
+ *
+ * Renesas R7FA2AL1AxxxFP MCU device tree for 100 pins socket
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+/ {
+	clocks: clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		xtal: clock-main-osc {
+			compatible = "renesas,ra-cgc-external-clock";
+			clock-frequency = <DT_FREQ_M(20)>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		hoco: clock-hoco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(48)>;
+			#clock-cells = <0>;
+		};
+
+		moco: clock-moco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(8)>;
+			#clock-cells = <0>;
+		};
+
+		loco: clock-loco {
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+		};
+
+		subclk: clock-subclk {
+			compatible = "renesas,ra-cgc-subclk";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		pclkblock: pclkblock@4001e01c {
+			compatible = "renesas,ra-cgc-pclk-block";
+			reg = <0x4001e01c 4>, <0x40047000 4>, <0x40047004 4>,
+			      <0x40047008 4>;
+			reg-names = "MSTPA", "MSTPB","MSTPC",
+				    "MSTPD";
+			#clock-cells = <0>;
+			clocks = <&hoco>;
+			status = "okay";
+
+			iclk: iclk {
+				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <48000000>;
+				div = <1>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkb: pclkb {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkd: pclkd {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <1>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			clkout: clkout {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+		};
+	};
+};
diff --git a/dts/arm/renesas/ra/ra2/ra2l1.dtsi b/dts/arm/renesas/ra/ra2/ra2l1.dtsi
new file mode 100644
index 00000000000..ea317d55921
--- /dev/null
+++ b/dts/arm/renesas/ra/ra2/ra2l1.dtsi
@@ -0,0 +1,241 @@
+/**
+ * Copyright (c) 2021-2024 MUNIC SA
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * Renesas RA2L1 MCU series device tree
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <freq.h>
+#include <mem.h>
+#include <arm/armv8-m.dtsi>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m23";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	soc {
+		interrupt-parent = <&nvic>;
+
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 0x8000>;
+		};
+
+		system: system@4001e000 {
+			compatible = "renesas,ra-system";
+			reg = <0x4001e000 0x1000>;
+			status = "okay";
+		};
+
+		flcn: flash-controller@407ec000 {
+			reg = <0x407ec000 0x10000>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: code@0 {
+				compatible = "soc-nv-flash";
+				/* "reg" property should be defined in the
+				 * chip specific .dtsi file
+				 */
+			};
+
+			flash1: data@40100000 {
+				compatible = "soc-nv-flash";
+				reg = <0x40100000 DT_SIZE_K(8)>;
+			};
+		};
+
+		ioport0: gpio@40040000 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x40040000 0x20>;
+			port = <0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport1: gpio@40040020 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x40040020 0x20>;
+			port = <1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport2: gpio@40040040 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x40040040 0x20>;
+			port = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport3: gpio@40040060 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x40040060 0x20>;
+			port = <3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport4: gpio@40040080 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x40040080 0x20>;
+			port = <4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport5: gpio@400400a0 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x400400a0 0x20>;
+			port = <5>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport6: gpio@400400c0 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x400400c0 0x20>;
+			port = <6>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport7: gpio@400400e0 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x400400e0 0x20>;
+			port = <7>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		pinctrl: pin-controller@40040800 {
+			compatible = "renesas,ra-pinctrl-pfs";
+			reg = <0x40040800 0x3c0>;
+			status = "okay";
+		};
+
+		sci0: sci0@40070000 {
+			compatible = "renesas,ra-sci";
+			interrupts = <0 1>, <1 1>, <2 1>, <3 1>;
+			interrupt-names = "rxi", "txi", "tei", "eri";
+			reg = <0x40070000 0x100>;
+			clocks = <&pclkb MSTPB 31>;
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <0>;
+				status = "disabled";
+			};
+		};
+
+		sci1: sci1@40070020 {
+			compatible = "renesas,ra-sci";
+			reg = <0x40070020 0x100>;
+			clocks = <&pclkb MSTPB 30>;
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <1>;
+				status = "disabled";
+			};
+		};
+
+		sci2: sci2@40070040 {
+			compatible = "renesas,ra-sci";
+			reg = <0x40070040 0x100>;
+			clocks = <&pclkb MSTPB 29>;
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <2>;
+				status = "disabled";
+			};
+		};
+
+		sci3: sci3@40070060 {
+			compatible = "renesas,ra-sci";
+			reg = <0x40070060 0x100>;
+			clocks = <&pclkb MSTPB 28>;
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <3>;
+				status = "disabled";
+			};
+		};
+
+		sci9: sci9@40070120 {
+			compatible = "renesas,ra-sci";
+			interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
+			interrupt-names = "rxi", "txi", "tei", "eri";
+			reg = <0x40070120 0x100>;
+			clocks = <&pclkb MSTPB 22>;
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <9>;
+				status = "disabled";
+			};
+		};
+
+		id_code: id_code@1010018 {
+			compatible = "zephyr,memory-region";
+			reg = <0x01010018 0x20>;
+			zephyr,memory-region = "ID_CODE";
+			status = "okay";
+		};
+
+		wdt: wdt@40044200 {
+			compatible = "renesas,ra-wdt";
+			reg = <0x40044200 0x200>;
+			clocks = <&pclkb 0 0>;
+			status = "disabled";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <2>;
+};
diff --git a/dts/arm/renesas/ra/ra2/ra2xx.dtsi b/dts/arm/renesas/ra/ra2/ra2xx.dtsi
index 13111985dfe..2d9807c2787 100644
--- a/dts/arm/renesas/ra/ra2/ra2xx.dtsi
+++ b/dts/arm/renesas/ra/ra2/ra2xx.dtsi
@@ -364,6 +364,20 @@
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
+
+		dac_global: dac_global@4005e000 {
+			compatible = "renesas,ra-dac-global";
+			reg = <0x4005e000 0x10c4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			dac0: dac@0 {
+				compatible = "renesas,ra-dac";
+				#io-channel-cells = <1>;
+				reg = <0>;
+				status = "disabled";
+			};
+		};
 	};
 };
 
diff --git a/dts/arm/renesas/ra/ra4-cm4-common.dtsi b/dts/arm/renesas/ra/ra4-cm4-common.dtsi
deleted file mode 100644
index e49b9bc766e..00000000000
--- a/dts/arm/renesas/ra/ra4-cm4-common.dtsi
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <renesas/ra/ra-cm4-common.dtsi>
-
-/ {
-	soc {
-		ioport6: gpio@400400c0 {
-			compatible = "renesas,ra-gpio";
-			reg = <0x400400c0 0x20>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <16>;
-			status = "disabled";
-		};
-
-		ioport7: gpio@400400e0 {
-			compatible = "renesas,ra-gpio";
-			reg = <0x400400e0 0x20>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <16>;
-			status = "disabled";
-		};
-
-		ioport8: gpio@40040100 {
-			compatible = "renesas,ra-gpio";
-			reg = <0x40040100 0x20>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <16>;
-			status = "disabled";
-		};
-
-		ioport9: gpio@40040120 {
-			compatible = "renesas,ra-gpio";
-			reg = <0x40040120 0x20>;
-			gpio-controller;
-			#gpio-cells = <2>;
-			ngpios = <16>;
-			status = "disabled";
-		};
-
-		sci2: sci@40070040 {
-			compatible = "renesas,ra-sci";
-			reg = <0x40070040 0x20>;
-			interrupts = <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI2_RXI>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI2_TXI>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI2_TEI>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI2_ERI>,
-				     <RA_ICU_IRQ_UNSPECIFIED 0 RA_ICU_SCI2_AM>;
-			interrupt-names = "rxi", "txi", "tei", "eri", "am";
-			clocks = <&pclka MSTPB 29>;
-			#clock-cells = <1>;
-			status = "disabled";
-			uart {
-				compatible = "renesas,ra-uart-sci";
-				status = "disabled";
-			};
-		};
-	};
-};
diff --git a/dts/arm/renesas/ra/ra4/r7fa4e10d2cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e10d2cfm.dtsi
new file mode 100644
index 00000000000..becb0cf5baf
--- /dev/null
+++ b/dts/arm/renesas/ra/ra4/r7fa4e10d2cfm.dtsi
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <arm/renesas/ra/ra4/r7fa4e10x.dtsi>
+
+/ {
+	soc {
+		flash-controller@407e0000 {
+			block-32kb-linear-end = <21>;
+
+			flash0: flash@0 {
+				compatible = "renesas,ra-nv-flash";
+				reg = <0x0 DT_SIZE_K(512)>;
+				write-block-size = <128>;
+				erase-block-size = <8192>;
+				renesas,programming-enable;
+			};
+
+			flash1: flash@8000000 {
+				compatible = "renesas,ra-nv-flash";
+				reg = <0x8000000 DT_SIZE_K(8)>;
+				write-block-size = <4>;
+				erase-block-size = <64>;
+				renesas,programming-enable;
+			};
+		};
+	};
+};
diff --git a/dts/arm/renesas/ra/ra4/r7fa4e10d2cne.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e10d2cne.dtsi
new file mode 100644
index 00000000000..becb0cf5baf
--- /dev/null
+++ b/dts/arm/renesas/ra/ra4/r7fa4e10d2cne.dtsi
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <arm/renesas/ra/ra4/r7fa4e10x.dtsi>
+
+/ {
+	soc {
+		flash-controller@407e0000 {
+			block-32kb-linear-end = <21>;
+
+			flash0: flash@0 {
+				compatible = "renesas,ra-nv-flash";
+				reg = <0x0 DT_SIZE_K(512)>;
+				write-block-size = <128>;
+				erase-block-size = <8192>;
+				renesas,programming-enable;
+			};
+
+			flash1: flash@8000000 {
+				compatible = "renesas,ra-nv-flash";
+				reg = <0x8000000 DT_SIZE_K(8)>;
+				write-block-size = <4>;
+				erase-block-size = <64>;
+				renesas,programming-enable;
+			};
+		};
+	};
+};
diff --git a/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi
new file mode 100644
index 00000000000..33baec96894
--- /dev/null
+++ b/dts/arm/renesas/ra/ra4/r7fa4e10x.dtsi
@@ -0,0 +1,266 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra4/ra4-cm33-common.dtsi>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <zephyr/dt-bindings/pwm/ra_pwm.h>
+
+/delete-node/ &spi1;
+/delete-node/ &agt4;
+/delete-node/ &adc1;
+/delete-node/ &dac1;
+/delete-node/ &iic1;
+/delete-node/ &pwm0;
+
+/ {
+	soc {
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(128)>;
+		};
+
+		sci3: sci3@40118300 {
+			compatible = "renesas,ra-sci";
+			reg = <0x40118300 0x100>;
+			clocks = <&pclka MSTPB 28>;
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <3>;
+				status = "disabled";
+			};
+		};
+
+		sci4: sci4@40118400 {
+			compatible = "renesas,ra-sci";
+			reg = <0x40118400 0x100>;
+			clocks = <&pclka MSTPB 27>;
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <4>;
+				status = "disabled";
+			};
+		};
+
+		adc@40170000 {
+			channel-available-mask = <0x1381f>;
+		};
+
+		pwm2: pwm2@40169200 {
+			compatible = "renesas,ra-pwm";
+			divider = <RA_PWM_SOURCE_DIV_1>;
+			channel = <RA_PWM_CHANNEL_2>;
+			clocks = <&pclkd MSTPE 29>;
+			reg = <0x40169200 0x100>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
+		trng: trng {
+			compatible = "renesas,ra-sce9-rng";
+			status = "disabled";
+		};
+	};
+
+	clocks: clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		xtal: clock-main-osc {
+			compatible = "renesas,ra-cgc-external-clock";
+			clock-frequency = <DT_FREQ_M(24)>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		hoco: clock-hoco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(20)>;
+			#clock-cells = <0>;
+		};
+
+		moco: clock-moco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(8)>;
+			#clock-cells = <0>;
+		};
+
+		loco: clock-loco {
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+		};
+
+		subclk: clock-subclk {
+			compatible = "renesas,ra-cgc-subclk";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			compatible = "renesas,ra-cgc-pll";
+			#clock-cells = <0>;
+
+			/* PLL */
+			clocks = <&hoco>;
+			div = <2>;
+			mul = <20 0>;
+			status = "disabled";
+		};
+
+		pll2: pll2 {
+			compatible = "renesas,ra-cgc-pll";
+			#clock-cells = <0>;
+
+			/* PLL2 */
+			div = <2>;
+			mul = <20 0>;
+			status = "disabled";
+		};
+
+		pclkblock: pclkblock@40084000 {
+			compatible = "renesas,ra-cgc-pclk-block";
+			reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>,
+			      <0x4008400c 4>, <0x40084010 4>;
+			reg-names = "MSTPA", "MSTPB", "MSTPC",
+				    "MSTPD", "MSTPE";
+			#clock-cells = <0>;
+			clocks = <&pll>;
+			status = "okay";
+
+			iclk: iclk {
+				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <100000000>;
+				div = <2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclka: pclka {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkb: pclkb {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkc: pclkc {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkd: pclkd {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			fclk: fclk {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			clkout: clkout {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			uclk: uclk {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+		};
+	};
+};
+
+&ioport0 {
+	port-irqs = <&port_irq6 &port_irq7 &port_irq8
+	&port_irq9 &port_irq13>;
+	port-irq-names = "port-irq6",
+			 "port-irq7",
+			 "port-irq8",
+			 "port-irq9",
+			 "port-irq13";
+	port-irq6-pins = <0>;
+	port-irq7-pins = <1>;
+	port-irq8-pins = <2>;
+	port-irq9-pins = <4>;
+	port-irq13-pins = <15>;
+};
+
+&ioport1 {
+	port-irqs = <&port_irq0 &port_irq1 &port_irq2
+	&port_irq3 &port_irq4>;
+	port-irq-names = "port-irq0",
+			 "port-irq1",
+			 "port-irq2",
+			 "port-irq3",
+			 "port-irq4";
+	port-irq0-pins = <5>;
+	port-irq1-pins = <1 4>;
+	port-irq2-pins = <0>;
+	port-irq3-pins = <10>;
+	port-irq4-pins = <11>;
+};
+
+&ioport2 {
+	port-irqs = <&port_irq0 &port_irq1 &port_irq2
+	&port_irq3>;
+	port-irq-names = "port-irq0",
+			 "port-irq1",
+			 "port-irq2",
+			 "port-irq3";
+	port-irq0-pins = <6>;
+	port-irq1-pins = <5>;
+	port-irq2-pins = <13>;
+	port-irq3-pins = <12>;
+};
+
+&ioport3 {
+	port-irqs = <&port_irq5 &port_irq6 &port_irq9>;
+	port-irq-names = "port-irq5",
+			 "port-irq6",
+			 "port-irq9";
+	port-irq5-pins = <2>;
+	port-irq6-pins = <1>;
+	port-irq9-pins = <4>;
+};
+
+&ioport4 {
+	port-irqs = <&port_irq0 &port_irq4 &port_irq5
+	&port_irq6 &port_irq7>;
+	port-irq-names = "port-irq0",
+			 "port-irq4",
+			 "port-irq5",
+			 "port-irq6",
+			 "port-irq7";
+	port-irq0-pins = <0>;
+	port-irq4-pins = <2 11>;
+	port-irq5-pins = <1 10>;
+	port-irq6-pins = <9>;
+	port-irq7-pins = <8>;
+};
+
+&dac_global {
+	has-output-amplifier;
+};
diff --git a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi
index e886e1f0af0..3a25a1a2589 100644
--- a/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi
+++ b/dts/arm/renesas/ra/ra4/r7fa4e2b93cfm.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,8 +15,11 @@
 /delete-node/ &agt5;
 /delete-node/ &iic0;
 /delete-node/ &iic1;
+/delete-node/ &usbfs;
+/delete-node/ &usbfs_phy;
 
 /delete-node/ &adc1;
+/delete-node/ &dac1;
 
 / {
 	soc {
@@ -55,7 +58,6 @@
 		};
 
 		adc@40170000 {
-			channel-count = <12>;
 			channel-available-mask = <0x139f7>;
 		};
 
@@ -72,6 +74,7 @@
 			interrupt-names = "rxf", "glerr";
 			clocks = <&pclkb 0 0>, <&pclka 0 0>;
 			clock-names = "opclk", "ramclk";
+			dll-max-freq = <DT_FREQ_M(40)>;
 			reg = <0x400b0000 0x2000>;
 			status = "disabled";
 
@@ -151,6 +154,7 @@
 
 			iclk: iclk {
 				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <100000000>;
 				div = <2>;
 				#clock-cells = <2>;
 				status = "okay";
@@ -306,3 +310,7 @@
 	port-irq-names = "port-irq11";
 	port-irq11-pins = <14>;
 };
+
+&dac_global {
+	has-output-amplifier;
+};
diff --git a/dts/arm/renesas/ra/ra4/r7fa4l1bd4cfp.dtsi b/dts/arm/renesas/ra/ra4/r7fa4l1bd4cfp.dtsi
new file mode 100644
index 00000000000..af5aa03a53d
--- /dev/null
+++ b/dts/arm/renesas/ra/ra4/r7fa4l1bd4cfp.dtsi
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/ra/ra4/r7fa4l1bx.dtsi>
+
+/ {
+	soc {
+		flash-controller@407e0000 {
+			reg = <0x407e0000 0x10000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@0 {
+				compatible = "renesas,ra-nv-flash";
+				reg = <0x0 DT_SIZE_K(512)>;
+				write-block-size = <8>;
+				erase-block-size = <2048>;
+				renesas,programming-enable;
+			};
+
+			flash1: flash@8000000 {
+				compatible = "renesas,ra-nv-flash";
+				reg = <0x8000000 DT_SIZE_K(8)>;
+				write-block-size = <1>;
+				erase-block-size = <256>;
+				renesas,programming-enable;
+			};
+		};
+	};
+};
diff --git a/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi b/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi
new file mode 100644
index 00000000000..996df8f7be7
--- /dev/null
+++ b/dts/arm/renesas/ra/ra4/r7fa4l1bx.dtsi
@@ -0,0 +1,766 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-m.dtsi>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <zephyr/dt-bindings/pwm/ra_pwm.h>
+#include <freq.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m33";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	soc {
+		interrupt-parent = <&nvic>;
+
+		system: system@4001e000 {
+			compatible = "renesas,ra-system";
+			reg = <0x4001e000 0x1000>;
+			status = "okay";
+		};
+
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(64)>;
+		};
+
+		ioport0: gpio@4001f000 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x4001f000 0x20>;
+			port = <0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport1: gpio@4001f020 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x4001f020 0x20>;
+			port = <1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport2: gpio@4001f040 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x4001f040 0x20>;
+			port = <2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport3: gpio@4001f060 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x4001f060 0x20>;
+			port = <3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport4: gpio@4001f080 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x4001f080 0x20>;
+			port = <4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport5: gpio@4001f0a0 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x4001f0a0 0x20>;
+			port = <5>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport6: gpio@4001f0c0 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x4001f0c0 0x20>;
+			port = <6>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport7: gpio@4001f0e0 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x4001f0e0 0x20>;
+			port = <7>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport8: gpio@4001f100 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x4001f100 0x20>;
+			port = <8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		pinctrl: pin-controller@4001F800 {
+			compatible = "renesas,ra-pinctrl-pfs";
+			reg = <0x4001F800 0x3c0>;
+			status = "okay";
+		};
+
+		sci0: sci@40118000 {
+			compatible = "renesas,ra-sci";
+			reg = <0x40118000 0x100>;
+			clocks = <&pclka MSTPB 31>;
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <0>;
+				status = "disabled";
+			};
+		};
+
+		sci1: sci@40118100 {
+			compatible = "renesas,ra-sci";
+			reg = <0x40118100 0x100>;
+			clocks = <&pclka MSTPB 30>;
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <1>;
+				status = "disabled";
+			};
+		};
+
+		sci3: sci@40118300 {
+			compatible = "renesas,ra-sci";
+			reg = <0x40118300 0x100>;
+			clocks = <&pclka MSTPB 38>;
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <3>;
+				status = "disabled";
+			};
+		};
+
+		sci4: sci@40118400 {
+			compatible = "renesas,ra-sci";
+			reg = <0x40118400 0x100>;
+			clocks = <&pclka MSTPB 27>;
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <4>;
+				status = "disabled";
+			};
+		};
+
+		sci5: sci@40118500 {
+			compatible = "renesas,ra-sci";
+			interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
+			interrupt-names = "rxi", "txi", "tei", "eri";
+			reg = <0x40118500 0x100>;
+			clocks = <&pclka MSTPB 26>;
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <5>;
+				status = "disabled";
+			};
+		};
+
+		sci9: sci@40118900 {
+			compatible = "renesas,ra-sci";
+			interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
+			interrupt-names = "rxi", "txi", "tei", "eri";
+			reg = <0x40118900 0x100>;
+			clocks = <&pclka MSTPB 22>;
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <9>;
+				status = "disabled";
+			};
+		};
+
+		spi0: spi@4011a000 {
+			compatible = "renesas,ra-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			channel = <0>;
+			interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
+			interrupt-names = "rxi", "txi", "tei", "eri";
+			reg = <0x4011a000 0x100>;
+			status = "disabled";
+		};
+
+		adc0: adc@40170000 {
+			compatible = "renesas,ra-adc";
+			interrupts = <38 1>;
+			interrupt-names = "scanend";
+			reg = <0x40170000 0x100>;
+			#io-channel-cells = <1>;
+			vref-mv = <3300>;
+			channel-available-mask = <0x3fe007f>;
+			status = "disabled";
+		};
+
+		dac_global: dac_global@40171000 {
+			compatible = "renesas,ra-dac-global";
+			reg = <0x40171000 0x10c4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			has-davrefcr;
+
+			dac0: dac@0 {
+				compatible = "renesas,ra-dac";
+				#io-channel-cells = <1>;
+				reg = <0>;
+				status = "disabled";
+			};
+		};
+
+		iic0: iic0@4009f000 {
+			compatible = "renesas,ra-iic";
+			channel = <0>;
+			reg = <0x4009f000 0x100>;
+			status = "disabled";
+		};
+
+		pwm0: pwm0@40169000 {
+			compatible = "renesas,ra-pwm";
+			divider = <RA_PWM_SOURCE_DIV_1>;
+			channel = <RA_PWM_CHANNEL_0>;
+			clocks = <&pclkd MSTPE 31>;
+			reg = <0x40169000 0x100>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
+		pwm1: pwm1@40169100 {
+			compatible = "renesas,ra-pwm";
+			divider = <RA_PWM_SOURCE_DIV_1>;
+			channel = <RA_PWM_CHANNEL_1>;
+			clocks = <&pclkd MSTPE 30>;
+			reg = <0x40169100 0x100>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
+		pwm2: pwm2@40169200 {
+			compatible = "renesas,ra-pwm";
+			divider = <RA_PWM_SOURCE_DIV_1>;
+			channel = <RA_PWM_CHANNEL_2>;
+			clocks = <&pclkd MSTPE 29>;
+			reg = <0x40169200 0x100>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
+		pwm3: pwm3@40169300 {
+			compatible = "renesas,ra-pwm";
+			divider = <RA_PWM_SOURCE_DIV_1>;
+			channel = <RA_PWM_CHANNEL_3>;
+			clocks = <&pclkd MSTPE 28>;
+			reg = <0x40169300 0x100>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
+		pwm4: pwm4@40169400 {
+			compatible = "renesas,ra-pwm";
+			divider = <RA_PWM_SOURCE_DIV_1>;
+			channel = <RA_PWM_CHANNEL_4>;
+			clocks = <&pclkd MSTPE 27>;
+			reg = <0x40169400 0x100>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
+		pwm5: pwm5@40169500 {
+			compatible = "renesas,ra-pwm";
+			divider = <RA_PWM_SOURCE_DIV_1>;
+			channel = <RA_PWM_CHANNEL_5>;
+			clocks = <&pclkd MSTPE 26>;
+			reg = <0x40169500 0x100>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
+		canfd_global: canfd_global@400b0000 {
+			compatible = "renesas,ra-canfd-global";
+			interrupts = <40 1>, <41 1>;
+			interrupt-names = "rxf", "glerr";
+			clocks = <&pclkb 0 0>, <&pclka 0 0>;
+			clock-names = "opclk", "ramclk";
+			reg = <0x400b0000 0x2000>;
+			status = "disabled";
+
+			canfd0: canfd0 {
+				compatible = "renesas,ra-canfd";
+				channel = <0>;
+				interrupts = <43 12>, <44 12>, <45 12>;
+				interrupt-names = "err", "tx", "rx";
+				clocks = <&canfdclk MSTPC 27>;
+				clock-names = "dllclk";
+				status = "disabled";
+			};
+		};
+
+		option_setting_ofs: option_setting_ofs@100a100 {
+			compatible = "zephyr,memory-region";
+			reg = <0x0100a100 0x18>;
+			zephyr,memory-region = "OPTION_SETTING_OFS";
+			status = "okay";
+		};
+
+		option_setting_sas: option_setting_sas@100a134 {
+			compatible = "zephyr,memory-region";
+			reg = <0x0100a134 0xcc>;
+			zephyr,memory-region = "OPTION_SETTING_SAS";
+			status = "okay";
+		};
+
+		option_setting_s: option_setting_s@100a200 {
+			compatible = "zephyr,memory-region";
+			reg = <0x0100a200 0x100>;
+			zephyr,memory-region = "OPTION_SETTING_S";
+			status = "okay";
+		};
+
+		port_irq0: external-interrupt@40006000 {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x40006000 0x1>;
+			channel = <0>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		port_irq1: external-interrupt@40006001 {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x40006001 0x1>;
+			channel = <1>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		port_irq2: external-interrupt@40006002 {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x40006002 0x1>;
+			channel = <2>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		port_irq3: external-interrupt@40006003 {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x40006003 0x1>;
+			channel = <3>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		port_irq4: external-interrupt@40006004 {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x40006004 0x1>;
+			channel = <4>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		port_irq5: external-interrupt@40006005 {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x40006005 0x1>;
+			channel = <5>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		port_irq6: external-interrupt@40006006 {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x40006006 0x1>;
+			channel = <6>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		port_irq7: external-interrupt@40006007 {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x40006007 0x1>;
+			channel = <7>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		port_irq8: external-interrupt@40006008 {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x40006008 0x1>;
+			channel = <8>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		port_irq9: external-interrupt@40006009 {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x40006009 0x1>;
+			channel = <9>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		port_irq10: external-interrupt@4000600a {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x4000600a 0x1>;
+			channel = <10>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		port_irq11: external-interrupt@4000600b {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x4000600b 0x1>;
+			channel = <11>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		port_irq12: external-interrupt@4000600c {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x4000600c 0x1>;
+			channel = <12>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		port_irq13: external-interrupt@4000600d {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x4000600d 0x1>;
+			channel = <13>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		port_irq14: external-interrupt@4000600e {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x4000600e 0x1>;
+			channel = <14>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		port_irq15: external-interrupt@4000600f {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x4000600f 0x1>;
+			channel = <15>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		wdt: wdt@40083400 {
+			compatible = "renesas,ra-wdt";
+			reg = <0x40083400 0x200>;
+			clocks = <&pclkb 0 0>;
+			status = "disabled";
+		};
+	};
+
+	clocks: clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		xtal: clock-main-osc {
+			compatible = "renesas,ra-cgc-external-clock";
+			clock-frequency = <DT_FREQ_M(8)>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		hoco: clock-hoco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(48)>;
+			#clock-cells = <0>;
+		};
+
+		loco: clock-loco {
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+		};
+
+		moco: clock-moco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(8)>;
+			#clock-cells = <0>;
+		};
+
+		subclk: clock-subclk {
+			compatible = "renesas,ra-cgc-subclk";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			compatible = "renesas,ra-cgc-pll";
+			#clock-cells = <0>;
+
+			/* PLL */
+			clocks = <&xtal>;
+			div = <1>;
+			mul = <10 0>;
+			status = "disabled";
+		};
+
+		pclkblock: pclkblock@40084000 {
+			compatible = "renesas,ra-cgc-pclk-block";
+			reg = <0x40084000 4>, <0x40084004 4>, <0x40084008 4>,
+			      <0x4008400c 4>, <0x40084010 4>;
+			reg-names = "MSTPA", "MSTPB","MSTPC",
+				    "MSTPD", "MSTPE";
+			#clock-cells = <0>;
+			clocks = <&pll>;
+			status = "okay";
+
+			iclk: iclk {
+				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <80000000>;
+				div = <1>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclka: pclka {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <1>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkb: pclkb {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkc: pclkc {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkd: pclkd {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <1>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			fclk: fclk {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			clkout: clkout {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			uclk: uclk {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			canfdclk: canfdclk {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			i3cclk: i3cclk {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			uarta0: uarta0 {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			uarta1: uarta1 {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
+
+&ioport0 {
+	port-irqs = <&port_irq6 &port_irq7 &port_irq8
+	&port_irq9 &port_irq10 &port_irq11>;
+	port-irq-names = "port-irq6",
+			 "port-irq7",
+			 "port-irq8",
+			 "port-irq9",
+			 "port-irq10",
+			 "port-irq11";
+	port-irq6-pins = <0>;
+	port-irq7-pins = <1>;
+	port-irq8-pins = <2>;
+	port-irq9-pins = <4>;
+	port-irq10-pins = <10>;
+	port-irq11-pins = <11>;
+};
+
+&ioport1 {
+	port-irqs = <&port_irq0 &port_irq1 &port_irq2
+	&port_irq3 &port_irq4>;
+	port-irq-names = "port-irq0",
+			 "port-irq1",
+			 "port-irq2",
+			 "port-irq3",
+			 "port-irq4";
+	port-irq0-pins = <5>;
+	port-irq1-pins = <1 4>;
+	port-irq2-pins = <0>;
+	port-irq3-pins = <10>;
+	port-irq4-pins = <11>;
+};
+
+&ioport2 {
+	port-irqs = <&port_irq0 &port_irq1 &port_irq2
+	&port_irq3 &port_irq12>;
+	port-irq-names = "port-irq0",
+			 "port-irq1",
+			 "port-irq2",
+			 "port-irq3",
+			 "port-irq12";
+	port-irq0-pins = <6>;
+	port-irq1-pins = <5>;
+	port-irq2-pins = <13>;
+	port-irq3-pins = <12>;
+	port-irq12-pins = <8>;
+};
+
+&ioport3 {
+	port-irqs = <&port_irq5 &port_irq6
+	&port_irq8 &port_irq9>;
+	port-irq-names = "port-irq5",
+			 "port-irq6",
+			 "port-irq8",
+			 "port-irq9";
+	port-irq5-pins = <2>;
+	port-irq6-pins = <1>;
+	port-irq8-pins = <5>;
+	port-irq9-pins = <4>;
+};
+
+&ioport4 {
+	port-irqs = <&port_irq0 &port_irq4 &port_irq5
+	&port_irq6 &port_irq7 &port_irq8
+	&port_irq9 &port_irq14 &port_irq15>;
+	port-irq-names = "port-irq0",
+			 "port-irq4",
+			 "port-irq5",
+			 "port-irq6",
+			 "port-irq7",
+			 "port-irq8",
+			 "port-irq9",
+			 "port-irq14",
+			 "port-irq15";
+	port-irq0-pins = <0>;
+	port-irq4-pins = <2 11>;
+	port-irq5-pins = <1 10>;
+	port-irq6-pins = <9>;
+	port-irq7-pins = <8>;
+	port-irq8-pins = <15>;
+	port-irq9-pins = <14>;
+	port-irq14-pins = <3>;
+	port-irq15-pins = <4>;
+};
+
+&ioport5 {
+	port-irqs = <&port_irq11 &port_irq12 &port_irq13
+	&port_irq14>;
+	port-irq-names = "port-irq11",
+			 "port-irq12",
+			 "port-irq13",
+			 "port-irq14";
+	port-irq11-pins = <1>;
+	port-irq12-pins = <2>;
+	port-irq13-pins = <6>;
+	port-irq14-pins = <5>;
+};
+
+&ioport7 {
+	port-irqs = <&port_irq11>;
+	port-irq-names = "port-irq11";
+	port-irq11-pins = <8>;
+};
diff --git a/dts/arm/renesas/ra/ra4/r7fa4m1ab3cfm.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m1ab3cfm.dtsi
new file mode 100644
index 00000000000..c00d5a9f699
--- /dev/null
+++ b/dts/arm/renesas/ra/ra4/r7fa4m1ab3cfm.dtsi
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <arm/renesas/ra/ra4/r7fa4m1ax.dtsi>
+
+/delete-node/ &ioport5;
+/delete-node/ &ioport6;
+/delete-node/ &ioport7;
+/delete-node/ &ioport8;
+
+/ {
+	soc {
+		flash-controller@407e0000 {
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				reg = <0x0 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/renesas/ra/ra4/r7fa4m1ab3cfp.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m1ab3cfp.dtsi
new file mode 100644
index 00000000000..16bf28fd8b6
--- /dev/null
+++ b/dts/arm/renesas/ra/ra4/r7fa4m1ab3cfp.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <arm/renesas/ra/ra4/r7fa4m1ax.dtsi>
+
+/ {
+	soc {
+		 flash-controller@407e0000 {
+			  flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				reg = <0x0 DT_SIZE_K(256)>;
+			  };
+		 };
+	};
+};
diff --git a/dts/arm/renesas/ra/ra4/r7fa4m1ab3cne.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m1ab3cne.dtsi
new file mode 100644
index 00000000000..9f379f43524
--- /dev/null
+++ b/dts/arm/renesas/ra/ra4/r7fa4m1ab3cne.dtsi
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025 Pete Johanson
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <arm/renesas/ra/ra4/r7fa4m1ax.dtsi>
+
+/delete-node/ &ioport5;
+/delete-node/ &ioport6;
+/delete-node/ &ioport7;
+/delete-node/ &ioport8;
+
+/ {
+	soc {
+		flash-controller@407e0000 {
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				reg = <0x0 DT_SIZE_K(256)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/renesas/ra/ra4/r7fa4m1ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m1ax.dtsi
new file mode 100644
index 00000000000..1a0570dc064
--- /dev/null
+++ b/dts/arm/renesas/ra/ra4/r7fa4m1ax.dtsi
@@ -0,0 +1,341 @@
+/*
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <arm/renesas/ra/ra4/ra4-cm4-common.dtsi>
+
+/ {
+	soc {
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(32)>;
+		};
+
+		ioport6: gpio@400400c0 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x400400c0 0x20>;
+			port = <6>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport7: gpio@400400e0 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x400400e0 0x20>;
+			port = <7>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		ioport8: gpio@40040100 {
+			compatible = "renesas,ra-gpio-ioport";
+			reg = <0x40040100 0x20>;
+			port = <8>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <16>;
+			status = "disabled";
+		};
+
+		sci2: sci2@40070040 {
+			compatible = "renesas,ra-sci";
+			reg = <0x40070040 0x20>;
+			interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
+			interrupt-names = "rxi", "txi", "tei", "eri";
+			clocks = <&pclka MSTPB 29>;
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,ra-sci-uart";
+				channel = <2>;
+				status = "disabled";
+			};
+		};
+
+		adc@4005c000 {
+			interrupts = <20 1>;
+			channel-available-mask = <0x3ff7fff>;
+		};
+
+		port_irq5: external-interrupt@40006005 {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x40006005 0x1>;
+			channel = <5>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		port_irq8: external-interrupt@40006008 {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x40006008 0x1>;
+			channel = <8>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		port_irq10: external-interrupt@4000600a {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x4000600a 0x1>;
+			channel = <10>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		port_irq12: external-interrupt@4000600c {
+			compatible = "renesas,ra-external-interrupt";
+			reg = <0x4000600c 0x1>;
+			channel = <12>;
+			renesas,sample-clock-div = <64>;
+			#port-irq-cells = <0>;
+			status = "disabled";
+		};
+
+		trng: trng {
+			compatible = "renesas,ra-sce5-rng";
+			status = "disabled";
+		};
+
+		pwm6: pwm6@40078600 {
+			compatible = "renesas,ra-pwm";
+			divider = <RA_PWM_SOURCE_DIV_1>;
+			channel = <RA_PWM_CHANNEL_6>;
+			clocks = <&pclkd MSTPD 6>;
+			reg = <0x40078600 0x100>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+
+		pwm7: pwm7@40078700 {
+			compatible = "renesas,ra-pwm";
+			divider = <RA_PWM_SOURCE_DIV_1>;
+			channel = <RA_PWM_CHANNEL_7>;
+			clocks = <&pclkd MSTPD 6>;
+			reg = <0x40078700 0x100>;
+			#pwm-cells = <3>;
+			status = "disabled";
+		};
+	};
+
+	clocks: clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		xtal: clock-main-osc {
+			compatible = "renesas,ra-cgc-external-clock";
+			clock-frequency = <DT_FREQ_M(12)>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		hoco: clock-hoco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(24)>;
+			#clock-cells = <0>;
+		};
+
+		moco: clock-moco {
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_M(8)>;
+			#clock-cells = <0>;
+		};
+
+		loco: clock-loco {
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+		};
+
+		subclk: clock-subclk {
+			compatible = "renesas,ra-cgc-subclk";
+			clock-frequency = <32768>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			compatible = "renesas,ra-cgc-pll";
+			#clock-cells = <0>;
+
+			clocks = <&xtal>;
+			div = <2>;
+			mul = <8 0>;
+			status = "disabled";
+		};
+
+		pclkblock: pclkblock@40047000 {
+			compatible = "renesas,ra-cgc-pclk-block";
+			reg = <0x40047000 4>,
+				  <0x40047004 4>,
+				  <0x40047008 4>;
+			reg-names = "MSTPB", "MSTPC", "MSTPD";
+			#clock-cells = <0>;
+			clocks = <&pll>;
+			status = "okay";
+
+			iclk: iclk {
+				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <48000000>;
+				div = <1>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclka: pclka {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <1>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkb: pclkb {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkc: pclkc {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <1>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkd: pclkd {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <1>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			fclk: fclk {
+				compatible = "renesas,ra-cgc-pclk";
+				div = <2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			clkout: clkout {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+
+			uclk: uclk {
+				compatible = "renesas,ra-cgc-pclk";
+				#clock-cells = <2>;
+				status = "disabled";
+			};
+		};
+	};
+};
+
+&ioport0 {
+	port-irqs = <&port_irq2 &port_irq3 &port_irq6
+	&port_irq7 &port_irq10 &port_irq15>;
+	port-irq-names = "port-irq2",
+			 "port-irq3",
+			 "port-irq6",
+			 "port-irq7",
+			 "port-irq10",
+			 "port-irq15";
+	port-irq2-pins = <2>;
+	port-irq3-pins = <4>;
+	port-irq6-pins = <0>;
+	port-irq7-pins = <1 15>;
+	port-irq10-pins = <5>;
+	port-irq15-pins = <11>;
+};
+
+&ioport1 {
+	port-irqs = <&port_irq0 &port_irq1 &port_irq2
+	&port_irq3 &port_irq4>;
+	port-irq-names = "port-irq0",
+			 "port-irq1",
+			 "port-irq2",
+			 "port-irq3",
+			 "port-irq4";
+	port-irq0-pins = <5>;
+	port-irq1-pins = <1 4>;
+	port-irq2-pins = <0>;
+	port-irq3-pins = <10>;
+	port-irq4-pins = <11>;
+};
+
+&ioport2 {
+	port-irqs = <&port_irq0 &port_irq1 &port_irq2
+	&port_irq3>;
+	port-irq-names = "port-irq0",
+			 "port-irq1",
+			 "port-irq2",
+			 "port-irq3";
+	port-irq0-pins = <6>;
+	port-irq1-pins = <5>;
+	port-irq2-pins = <13>;
+	port-irq3-pins = <12>;
+};
+
+&ioport3 {
+	port-irqs = <&port_irq5 &port_irq6 &port_irq8
+	&port_irq9>;
+	port-irq-names = "port-irq5",
+			 "port-irq6",
+			 "port-irq8",
+			 "port-irq9";
+	port-irq5-pins = <2>;
+	port-irq6-pins = <1>;
+	port-irq8-pins = <5>;
+	port-irq9-pins = <4>;
+};
+
+&ioport4 {
+	port-irqs = <&port_irq0 &port_irq4 &port_irq5
+	&port_irq6 &port_irq7 &port_irq8
+	&port_irq9>;
+	port-irq-names = "port-irq0",
+			 "port-irq4",
+			 "port-irq5",
+			 "port-irq6",
+			 "port-irq7",
+			 "port-irq8",
+			 "port-irq9";
+	port-irq0-pins = <0>;
+	port-irq4-pins = <2 11>;
+	port-irq5-pins = <1 10>;
+	port-irq6-pins = <9>;
+	port-irq7-pins = <8>;
+	port-irq8-pins = <15>;
+	port-irq9-pins = <14>;
+};
+
+&ioport5 {
+	port-irqs = <&port_irq11 &port_irq12 &port_irq14>;
+	port-irq-names = "port-irq11",
+			 "port-irq12",
+			 "port-irq14";
+	port-irq11-pins = <1>;
+	port-irq12-pins = <2>;
+	port-irq14-pins = <5>;
+};
+
+&pwm2 {
+	clocks = <&pclkd MSTPD 6>;
+};
+
+&pwm3 {
+	clocks = <&pclkd MSTPD 6>;
+};
+
+&dac_global {
+	has-davrefcr;
+};
diff --git a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi
index 90fe1a61dc8..fcbf52a9b12 100644
--- a/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi
+++ b/dts/arm/renesas/ra/ra4/r7fa4m2ax.dtsi
@@ -96,7 +96,6 @@
 		};
 
 		adc@40170000 {
-			channel-count = <13>;
 			channel-available-mask = <0x139ff>;
 		};
 
@@ -139,6 +138,11 @@
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
+
+		trng: trng {
+			compatible = "renesas,ra-sce9-rng";
+			status = "disabled";
+		};
 	};
 
 	clocks: clocks {
@@ -210,6 +214,7 @@
 
 			iclk: iclk {
 				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <100000000>;
 				div = <2>;
 				#clock-cells = <2>;
 				status = "okay";
@@ -367,3 +372,7 @@
 	port-irq-names = "port-irq11";
 	port-irq11-pins = <8>;
 };
+
+&dac_global {
+	has-output-amplifier;
+};
diff --git a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi
index d2405af2e7a..019a3947d21 100644
--- a/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi
+++ b/dts/arm/renesas/ra/ra4/r7fa4m3ax.dtsi
@@ -104,12 +104,10 @@
 		};
 
 		adc@40170000 {
-			channel-count = <12>;
 			channel-available-mask = <0x33ff>;
 		};
 
 		adc@40170200 {
-			channel-count = <10>;
 			channel-available-mask = <0x7f0007>;
 		};
 
@@ -152,6 +150,11 @@
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
+
+		trng: trng {
+			compatible = "renesas,ra-sce9-rng";
+			status = "disabled";
+		};
 	};
 
 	clocks: clocks {
@@ -221,6 +224,7 @@
 
 			iclk: iclk {
 				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <100000000>;
 				div = <2>;
 				#clock-cells = <2>;
 				status = "okay";
@@ -383,3 +387,7 @@
 	port-irq10-pins = <9>;
 	port-irq11-pins = <8>;
 };
+
+&dac_global {
+	has-output-amplifier;
+};
diff --git a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi
index 7338fd01068..44af76cf559 100644
--- a/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi
+++ b/dts/arm/renesas/ra/ra4/r7fa4w1ad2cng.dtsi
@@ -8,8 +8,6 @@
 #include <arm/renesas/ra/ra4/ra4-cm4-common.dtsi>
 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
 
-/delete-node/ &adc1;
-
 / {
 	soc {
 		sram0: memory@20000000 {
@@ -38,12 +36,6 @@
 			};
 		};
 
-		spi1: spi@40072100 {
-			compatible = "renesas,ra-spi";
-			interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
-			interrupt-names = "rxi", "txi", "tei", "eri";
-		};
-
 		trng: trng {
 			compatible = "renesas,ra-sce5-rng";
 			status = "disabled";
@@ -51,16 +43,15 @@
 
 		adc@4005c000 {
 			interrupts = <20 1>;
-			channel-count = <8>;
 			channel-available-mask = <0x1a0670>;
 		};
 
-		pwm8: pwm8@40169800 {
+		pwm8: pwm8@40078800 {
 			compatible = "renesas,ra-pwm";
 			divider = <RA_PWM_SOURCE_DIV_1>;
 			channel = <RA_PWM_CHANNEL_8>;
 			clocks = <&pclkd MSTPD 6>;
-			reg = <0x40169800 0x100>;
+			reg = <0x40078800 0x100>;
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
@@ -125,6 +116,7 @@
 
 			iclk: iclk {
 				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <48000000>;
 				div = <1>;
 				#clock-cells = <2>;
 				status = "okay";
@@ -237,3 +229,15 @@
 	port-irq-names = "port-irq11";
 	port-irq11-pins = <1>;
 };
+
+&pwm2 {
+	clocks = <&pclkd MSTPD 5>;
+};
+
+&pwm3 {
+	clocks = <&pclkd MSTPD 5>;
+};
+
+&dac_global {
+	has-davrefcr;
+};
diff --git a/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi b/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi
index c847542129b..aa88f96a304 100644
--- a/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi
+++ b/dts/arm/renesas/ra/ra4/ra4-cm33-common.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -129,7 +129,7 @@
 
 		sci9: sci9@40118900 {
 			compatible = "renesas,ra-sci";
-			interrupts = <36 1>, <37 1>, <38 1>, <39 1>;
+			interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
 			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x40118900 0x100>;
 			clocks = <&pclka MSTPB 22>;
@@ -253,7 +253,7 @@
 
 		adc0: adc@40170000 {
 			compatible = "renesas,ra-adc";
-			interrupts = <40 1>;
+			interrupts = <38 1>;
 			interrupt-names = "scanend";
 			reg = <0x40170000 0x100>;
 			#io-channel-cells = <1>;
@@ -263,7 +263,7 @@
 
 		adc1: adc@40170200 {
 			compatible = "renesas,ra-adc";
-			interrupts = <41 1>;
+			interrupts = <39 1>;
 			interrupt-names = "scanend";
 			reg = <0x40170200 0x100>;
 			#io-channel-cells = <1>;
@@ -271,6 +271,27 @@
 			status = "disabled";
 		};
 
+		dac_global: dac_global@40171000 {
+			compatible = "renesas,ra-dac-global";
+			reg = <0x40171000 0x10c4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			dac0: dac@0 {
+				compatible = "renesas,ra-dac";
+				#io-channel-cells = <1>;
+				reg = <0>;
+				status = "disabled";
+			};
+
+			dac1: dac@1 {
+				compatible = "renesas,ra-dac";
+				#io-channel-cells = <1>;
+				reg = <1>;
+				status = "disabled";
+			};
+		};
+
 		iic0: iic0@4009f000 {
 			compatible = "renesas,ra-iic";
 			channel = <0>;
@@ -285,6 +306,22 @@
 			status = "disabled";
 		};
 
+		usbfs: usbfs@40090000 {
+			compatible = "renesas,ra-usbfs";
+			reg = <0x40090000 0x2000>;
+			interrupts = <32 1>, <33 1>;
+			interrupt-names = "usbfs-i", "usbfs-r";
+			num-bidir-endpoints = <10>;
+			phys = <&usbfs_phy>;
+			phys-clock = <&uclk>;
+			status = "disabled";
+
+			udc {
+				compatible = "renesas,ra-udc";
+				status = "disabled";
+			};
+		};
+
 		option_setting_ofs: option_setting_ofs@100a100 {
 			compatible = "zephyr,memory-region";
 			reg = <0x0100a100 0x18>;
@@ -489,6 +526,18 @@
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
+
+		wdt: wdt@40083400 {
+			compatible = "renesas,ra-wdt";
+			reg = <0x40083400 0x200>;
+			clocks = <&pclkb 0 0>;
+			status = "disabled";
+		};
+	};
+
+	usbfs_phy: usbfs-phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
 	};
 };
 
diff --git a/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi b/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi
index aaaff96cd3b..5234212dd28 100644
--- a/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi
+++ b/dts/arm/renesas/ra/ra4/ra4-cm4-common.dtsi
@@ -149,8 +149,6 @@
 
 		sci9: sci9@40070120  {
 			compatible = "renesas,ra-sci";
-			interrupts = <36 1>, <37 1>, <38 1>, <39 1>;
-			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x40070120 0x20>;
 			clocks = <&pclka MSTPB 22>;
 			status = "disabled";
@@ -175,7 +173,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			channel = <1>;
-			interrupts = <32 1>, <33 1>, <34 1>, <35 1>;
+			interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
 			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x40072100 0x100>;
 			status = "disabled";
@@ -220,13 +218,19 @@
 			status = "disabled";
 		};
 
-		adc1: adc@4005c200 {
-			compatible = "renesas,ra-adc";
-			interrupt-names = "scanend";
-			reg = <0x4005c200 0x100>;
-			#io-channel-cells = <1>;
-			vref-mv = <3300>;
-			status = "disabled";
+		dac_global: dac_global@4005e000 {
+			compatible = "renesas,ra-dac-global";
+			reg = <0x4005e000 0x10c4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "okay";
+
+			dac0: dac@0 {
+				compatible = "renesas,ra-dac";
+				#io-channel-cells = <1>;
+				reg = <0>;
+				status = "disabled";
+			};
 		};
 
 		iic0: iic0@40053000 {
@@ -243,6 +247,22 @@
 			status = "disabled";
 		};
 
+		usbfs: usbfs@40090000 {
+			compatible = "renesas,ra-usbfs";
+			reg = <0x40090000 0x2000>;
+			num-bidir-endpoints = <10>;
+			interrupts = <12 1>, <13 1>;
+			interrupt-names = "usbfs-i", "usbfs-r";
+			phys = <&usbfs_phy>;
+			phys-clock = <&uclk>;
+			status = "disabled";
+
+			udc {
+				compatible = "renesas,ra-udc";
+				status = "disabled";
+			};
+		};
+
 		id_code: id_code@1010018 {
 			compatible = "zephyr,memory-region";
 			reg = <0x01010018 0x20>;
@@ -349,65 +369,75 @@
 			status = "disabled";
 		};
 
-		pwm0: pwm0@40169000 {
+		pwm0: pwm0@40078000 {
 			compatible = "renesas,ra-pwm";
 			divider = <RA_PWM_SOURCE_DIV_1>;
 			channel = <RA_PWM_CHANNEL_0>;
 			clocks = <&pclkd MSTPD 5>;
-			reg = <0x40169000 0x100>;
+			reg = <0x40078000 0x100>;
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
 
-		pwm1: pwm1@40169100 {
+		pwm1: pwm1@40078100 {
 			compatible = "renesas,ra-pwm";
 			divider = <RA_PWM_SOURCE_DIV_1>;
 			channel = <RA_PWM_CHANNEL_1>;
 			clocks = <&pclkd MSTPD 5>;
-			reg = <0x40169100 0x100>;
+			reg = <0x40078100 0x100>;
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
 
-		pwm2: pwm2@40169200 {
+		pwm2: pwm2@40078200 {
 			compatible = "renesas,ra-pwm";
 			divider = <RA_PWM_SOURCE_DIV_1>;
 			channel = <RA_PWM_CHANNEL_2>;
-			clocks = <&pclkd MSTPD 5>;
-			reg = <0x40169200 0x100>;
+			reg = <0x40078200 0x100>;
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
 
-		pwm3: pwm3@40169300 {
+		pwm3: pwm3@40078300 {
 			compatible = "renesas,ra-pwm";
 			divider = <RA_PWM_SOURCE_DIV_1>;
 			channel = <RA_PWM_CHANNEL_3>;
-			clocks = <&pclkd MSTPD 5>;
-			reg = <0x40169300 0x100>;
+			reg = <0x40078300 0x100>;
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
 
-		pwm4: pwm4@40169400 {
+		pwm4: pwm4@40078400 {
 			compatible = "renesas,ra-pwm";
 			divider = <RA_PWM_SOURCE_DIV_1>;
 			channel = <RA_PWM_CHANNEL_4>;
-			clocks = <&pclkd MSTPD 5>;
-			reg = <0x40169400 0x100>;
+			clocks = <&pclkd MSTPD 6>;
+			reg = <0x40078400 0x100>;
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
 
-		pwm5: pwm5@40169500 {
+		pwm5: pwm5@40078500 {
 			compatible = "renesas,ra-pwm";
 			divider = <RA_PWM_SOURCE_DIV_1>;
 			channel = <RA_PWM_CHANNEL_5>;
 			clocks = <&pclkd MSTPD 6>;
-			reg = <0x40169500 0x100>;
+			reg = <0x40078500 0x100>;
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
+
+		wdt: wdt@40044200 {
+			compatible = "renesas,ra-wdt";
+			reg = <0x40044200 0x200>;
+			clocks = <&pclkb 0 0>;
+			status = "disabled";
+		};
+	};
+
+	usbfs_phy: usbfs-phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
 	};
 };
 
diff --git a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi
index df0b97c857a..7eb89905448 100644
--- a/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi
+++ b/dts/arm/renesas/ra/ra6/r7fa6e10x.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,6 +9,7 @@
 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
 
 /delete-node/ &adc1;
+/delete-node/ &dac1;
 
 / {
 	soc {
@@ -94,7 +95,6 @@
 		};
 
 		adc@40170000 {
-			channel-count = <11>;
 			channel-available-mask = <0x31ff>;
 		};
 
@@ -117,6 +117,11 @@
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
+
+		trng: trng {
+			compatible = "renesas,ra-sce9-rng";
+			status = "disabled";
+		};
 	};
 
 	clocks: clocks {
@@ -188,6 +193,7 @@
 
 			iclk: iclk {
 				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <200000000>;
 				div = <1>;
 				#clock-cells = <2>;
 				status = "okay";
@@ -345,3 +351,7 @@
 	port-irq-names = "port-irq11";
 	port-irq11-pins = <8>;
 };
+
+&dac_global {
+	has-output-amplifier;
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi
index 30577ae1103..bc4ad08abcd 100644
--- a/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi
+++ b/dts/arm/renesas/ra/ra6/r7fa6e2bx.dtsi
@@ -6,6 +6,7 @@
 
 #include <arm/renesas/ra/ra6/ra6-cm33-common.dtsi>
 #include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <zephyr/dt-bindings/pwm/ra_pwm.h>
 
 /delete-node/ &agt0;
 /delete-node/ &agt1;
@@ -13,9 +14,11 @@
 /delete-node/ &agt3;
 /delete-node/ &agt4;
 /delete-node/ &agt5;
-#include <zephyr/dt-bindings/pwm/ra_pwm.h>
-
 /delete-node/ &adc1;
+/delete-node/ &usbfs;
+/delete-node/ &usbfs_phy;
+/delete-node/ &eth;
+/delete-node/ &mdio;
 
 / {
 	soc {
@@ -35,7 +38,6 @@
 		};
 
 		adc@40170000 {
-			channel-count = <12>;
 			channel-available-mask = <0x139f7>;
 		};
 
@@ -52,6 +54,7 @@
 			interrupt-names = "rxf", "glerr";
 			clocks = <&pclkb 0 0>, <&pclka 0 0>;
 			clock-names = "opclk", "ramclk";
+			dll-max-freq = <DT_FREQ_M(40)>;
 			reg = <0x400b0000 0x2000>;
 			status = "disabled";
 
@@ -151,6 +154,7 @@
 
 			iclk: iclk {
 				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <200000000>;
 				div = <1>;
 				#clock-cells = <2>;
 				status = "okay";
@@ -306,3 +310,7 @@
 	port-irq-names = "port-irq11";
 	port-irq11-pins = <14>;
 };
+
+&dac_global {
+	has-output-amplifier;
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi
index 1bbe008e765..596fcc5b520 100644
--- a/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi
+++ b/dts/arm/renesas/ra/ra6/r7fa6m1ad3cfp.dtsi
@@ -7,6 +7,9 @@
 #include <zephyr/dt-bindings/clock/ra_clock.h>
 #include <arm/renesas/ra/ra6/ra6-cm4-common.dtsi>
 
+/delete-node/ &eth;
+/delete-node/ &mdio;
+
 / {
 	soc {
 		sram0: memory@1ffe0000 {
@@ -39,12 +42,10 @@
 		};
 
 		adc@4005c000 {
-			channel-count = <11>;
 			channel-available-mask = <0x1700ef>;
 		};
 
 		adc@4005c200 {
-			channel-count = <8>;
 			channel-available-mask = <0x300e7>;
 		};
 	};
@@ -108,6 +109,7 @@
 
 			iclk: iclk {
 				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <120000000>;
 				div = <2>;
 				#clock-cells = <2>;
 				status = "okay";
@@ -273,3 +275,7 @@
 	port-irq-names = "port-irq11";
 	port-irq11-pins = <8>;
 };
+
+&dac_global {
+	has-output-amplifier;
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi
index 5424d4d6ec8..5a07efd2800 100644
--- a/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi
+++ b/dts/arm/renesas/ra/ra6/r7fa6m2ax.dtsi
@@ -8,6 +8,9 @@
 #include <zephyr/dt-bindings/clock/ra_clock.h>
 #include <zephyr/dt-bindings/pwm/ra_pwm.h>
 
+/delete-node/ &eth;
+/delete-node/ &mdio;
+
 / {
 	soc {
 		sram0: memory@1ffe0000 {
@@ -17,8 +20,6 @@
 
 		sci5: sci5@400700a0 {
 			compatible = "renesas,ra-sci";
-			interrupts = <20 1>, <21 1>, <22 1>, <23 1>;
-			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x400700a0 0x20>;
 			clocks = <&pclka MSTPB 26>;
 			status = "disabled";
@@ -31,8 +32,6 @@
 
 		sci6: sci6@400700c0 {
 			compatible = "renesas,ra-sci";
-			interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
-			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x400700c0 0x20>;
 			clocks = <&pclka MSTPB 25>;
 			status = "disabled";
@@ -45,7 +44,7 @@
 
 		sci7: sci7@400700e0 {
 			compatible = "renesas,ra-sci";
-			interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
+			interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
 			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x400700e0 0x20>;
 			clocks = <&pclka MSTPB 24>;
@@ -65,12 +64,10 @@
 		};
 
 		adc@4005c000 {
-			channel-count = <13>;
 			channel-available-mask = <0x1f00ff>;
 		};
 
 		adc@4005c200 {
-			channel-count = <9>;
 			channel-available-mask = <0x700e7>;
 		};
 
@@ -144,6 +141,7 @@
 
 			iclk: iclk {
 				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <120000000>;
 				div = <2>;
 				#clock-cells = <2>;
 				status = "okay";
@@ -316,3 +314,7 @@
 	port-irq10-pins = <9>;
 	port-irq11-pins = <8>;
 };
+
+&dac_global {
+	has-output-amplifier;
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi
index 3962f7b3738..78e71409cc9 100644
--- a/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi
+++ b/dts/arm/renesas/ra/ra6/r7fa6m3ax.dtsi
@@ -105,12 +105,13 @@
 		};
 
 		usbhs: usbhs@40060000 {
-			compatible = "renesas,ra-usb";
+			compatible = "renesas,ra-usbhs";
 			reg = <0x40060000 0x2000>;
-			interrupts = <54 12>, <55 12>, <56 12>;
-			interrupt-names = "usbhs-ir", "usbhs-d0", "usbhs-d1";
+			interrupts = <54 12>;
+			interrupt-names = "usbhs-ir";
 			num-bidir-endpoints = <10>;
 			phys = <&usbhs_phy>;
+			phys-clock = <&uclk>;
 			status = "disabled";
 			udc {
 				compatible = "renesas,ra-udc";
@@ -119,12 +120,10 @@
 		};
 
 		adc@4005c000 {
-			channel-count = <13>;
 			channel-available-mask = <0x1f00ff>;
 		};
 
 		adc@4005c200 {
-			channel-count = <11>;
 			channel-available-mask = <0xf00ef>;
 		};
 
@@ -198,6 +197,7 @@
 
 			iclk: iclk {
 				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <120000000>;
 				div = <2>;
 				#clock-cells = <2>;
 				status = "okay";
@@ -382,3 +382,7 @@
 	port-irq10-pins = <9>;
 	port-irq11-pins = <8>;
 };
+
+&dac_global {
+	has-output-amplifier;
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi
index 9ebb32155b2..e629ed5b3fa 100644
--- a/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi
+++ b/dts/arm/renesas/ra/ra6/r7fa6m4ax.dtsi
@@ -128,12 +128,10 @@
 		};
 
 		adc@40170000 {
-			channel-count = <12>;
 			channel-available-mask = <0x33ff>;
 		};
 
 		adc@40170200 {
-			channel-count = <10>;
 			channel-available-mask = <0x7f0007>;
 		};
 
@@ -226,6 +224,11 @@
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
+
+		trng: trng {
+			compatible = "renesas,ra-sce9-rng";
+			status = "disabled";
+		};
 	};
 
 	clocks: clocks {
@@ -297,6 +300,7 @@
 
 			iclk: iclk {
 				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <200000000>;
 				div = <1>;
 				#clock-cells = <2>;
 				status = "okay";
@@ -478,3 +482,7 @@
 	port-irq10-pins = <9>;
 	port-irq11-pins = <8>;
 };
+
+&dac_global {
+	has-output-amplifier;
+};
diff --git a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi
index c51b4cf8d22..4675d23d6b2 100644
--- a/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi
+++ b/dts/arm/renesas/ra/ra6/r7fa6m5xh.dtsi
@@ -195,12 +195,13 @@
 		};
 
 		usbhs: usbhs@40111000 {
-			compatible = "renesas,ra-usb";
+			compatible = "renesas,ra-usbhs";
 			reg = <0x40111000 0x2000>;
-			interrupts = <54 12>, <55 12>, <56 12>;
-			interrupt-names = "usbhs-ir", "usbhs-d0", "usbhs-d1";
+			interrupts = <54 12>;
+			interrupt-names = "usbhs-ir";
 			num-bidir-endpoints = <10>;
 			phys = <&usbhs_phy>;
+			phys-clock = <&uclk>, <&u60clk>;
 			status = "disabled";
 			udc {
 				compatible = "renesas,ra-udc";
@@ -209,12 +210,10 @@
 		};
 
 		adc@40170000 {
-			channel-count = <13>;
 			channel-available-mask = <0x37ff>;
 		};
 
 		adc@40170200 {
-			channel-count = <16>;
 			channel-available-mask = <0x1fff0007>;
 		};
 
@@ -277,6 +276,11 @@
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
+
+		trng: trng {
+			compatible = "renesas,ra-sce9-rng";
+			status = "disabled";
+		};
 	};
 
 	clocks: clocks {
@@ -348,6 +352,7 @@
 
 			iclk: iclk {
 				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <200000000>;
 				div = <1>;
 				#clock-cells = <2>;
 				status = "okay";
@@ -601,3 +606,7 @@
 	port-irq5-pins = <9>;
 	port-irq6-pins = <8>;
 };
+
+&dac_global {
+	has-output-amplifier;
+};
diff --git a/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi b/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi
index 55ac2cf99bf..daeabd1e3f8 100644
--- a/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi
+++ b/dts/arm/renesas/ra/ra6/ra6-cm33-common.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -121,7 +121,7 @@
 
 		sci9: sci9@40118900 {
 			compatible = "renesas,ra-sci";
-			interrupts = <36 1>, <37 1>, <38 1>, <39 1>;
+			interrupts = <74 1>, <75 1>, <76 1>, <77 1>;
 			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x40118900 0x100>;
 			clocks = <&pclka MSTPB 22>;
@@ -152,7 +152,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			channel = <0>;
-			interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
+			interrupts = <78 1>, <79 1>, <80 1>, <81 1>;
 			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x4011a000 0x100>;
 			status = "disabled";
@@ -163,7 +163,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			channel = <1>;
-			interrupts = <32 1>, <33 1>, <34 1>, <35 1>;
+			interrupts = <82 1>, <83 1>, <84 1>, <85 1>;
 			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x4011a100 0x100>;
 			status = "disabled";
@@ -261,7 +261,7 @@
 
 		adc0: adc@40170000 {
 			compatible = "renesas,ra-adc";
-			interrupts = <40 1>;
+			interrupts = <38 1>;
 			interrupt-names = "scanend";
 			reg = <0x40170000 0x100>;
 			#io-channel-cells = <1>;
@@ -271,7 +271,7 @@
 
 		adc1: adc@40170200 {
 			compatible = "renesas,ra-adc";
-			interrupts = <41 1>;
+			interrupts = <39 1>;
 			interrupt-names = "scanend";
 			reg = <0x40170200 0x100>;
 			#io-channel-cells = <1>;
@@ -279,6 +279,43 @@
 			status = "disabled";
 		};
 
+		dac_global: dac_global@40171000 {
+			compatible = "renesas,ra-dac-global";
+			reg = <0x40171000 0x10c4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			dac0: dac@0 {
+				compatible = "renesas,ra-dac";
+				#io-channel-cells = <1>;
+				reg = <0>;
+				status = "disabled";
+			};
+
+			dac1: dac@1 {
+				compatible = "renesas,ra-dac";
+				#io-channel-cells = <1>;
+				reg = <1>;
+				status = "disabled";
+			};
+		};
+
+		usbfs: usbfs@40090000 {
+			compatible = "renesas,ra-usbfs";
+			reg = <0x40090000 0x2000>;
+			interrupts = <55 12>, <56 12>;
+			interrupt-names = "usbfs-i", "usbfs-r";
+			num-bidir-endpoints = <10>;
+			phys = <&usbfs_phy>;
+			phys-clock = <&uclk>;
+			status = "disabled";
+
+			udc {
+				compatible = "renesas,ra-udc";
+				status = "disabled";
+			};
+		};
+
 		option_setting_ofs: option_setting_ofs@100a100 {
 			compatible = "zephyr,memory-region";
 			reg = <0x0100a100 0x18>;
@@ -492,6 +529,34 @@
 			#pwm-cells = <3>;
 			status = "disabled";
 		};
+
+		wdt: wdt@40083400 {
+			compatible = "renesas,ra-wdt";
+			reg = <0x40083400 0x200>;
+			clocks = <&pclkb 0 0>;
+			status = "disabled";
+		};
+
+		eth: ethernet@40114100 {
+			compatible = "renesas,ra-ethernet";
+			reg = <0x40114100 0xfc>;
+			interrupts = <51 12>;
+			local-mac-address = [00 11 22 33 44 55];
+			phy-connection-type = "rmii";
+			status = "disabled";
+		};
+
+		mdio: mdio {
+			compatible = "renesas,ra-mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+	};
+
+	usbfs_phy: usbfs-phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
 	};
 };
 
diff --git a/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi b/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi
index c5fc25bc1dc..191e14252fa 100644
--- a/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi
+++ b/dts/arm/renesas/ra/ra6/ra6-cm4-common.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -140,8 +140,6 @@
 
 		sci1: sci1@40070020  {
 			compatible = "renesas,ra-sci";
-			interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
-			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x40070020 0x20>;
 			clocks = <&pclka MSTPB 30>;
 			status = "disabled";
@@ -154,8 +152,6 @@
 
 		sci2: sci2@40070040 {
 			compatible = "renesas,ra-sci";
-			interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
-			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x40070040 0x20>;
 			clocks = <&pclka MSTPB 29>;
 			status = "disabled";
@@ -168,8 +164,6 @@
 
 		sci3: sci3@40070060  {
 			compatible = "renesas,ra-sci";
-			interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
-			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x40070060 0x20>;
 			clocks = <&pclka MSTPB 27>;
 			status = "disabled";
@@ -182,8 +176,6 @@
 
 		sci4: sci4@40070080  {
 			compatible = "renesas,ra-sci";
-			interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
-			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x40070080 0x20>;
 			clocks = <&pclka MSTPB 26>;
 			status = "disabled";
@@ -196,7 +188,7 @@
 
 		sci8: sci8@40070100  {
 			compatible = "renesas,ra-sci";
-			interrupts = <32 1>, <33 1>, <34 1>, <35 1>;
+			interrupts = <20 1>, <21 1>, <22 1>, <23 1>;
 			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x40070100 0x20>;
 			clocks = <&pclka MSTPB 23>;
@@ -210,7 +202,7 @@
 
 		sci9: sci9@40070120  {
 			compatible = "renesas,ra-sci";
-			interrupts = <36 1>, <37 1>, <38 1>, <39 1>;
+			interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
 			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x40070120 0x20>;
 			clocks = <&pclka MSTPB 22>;
@@ -241,7 +233,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			channel = <0>;
-			interrupts = <40 1>, <41 1>, <42 1>, <43 1>;
+			interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
 			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x40072000 0x100>;
 			status = "disabled";
@@ -252,8 +244,6 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			channel = <1>;
-			interrupts = <44 1>, <45 1>, <46 1>, <47 1>;
-			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x40072100 0x100>;
 			status = "disabled";
 		};
@@ -290,7 +280,7 @@
 
 		adc0: adc@4005c000 {
 			compatible = "renesas,ra-adc";
-			interrupts = <40 1>;
+			interrupts = <38 1>;
 			interrupt-names = "scanend";
 			reg = <0x4005c000 0x100>;
 			#io-channel-cells = <1>;
@@ -300,7 +290,7 @@
 
 		adc1: adc@4005c200 {
 			compatible = "renesas,ra-adc";
-			interrupts = <41 1>;
+			interrupts = <39 1>;
 			interrupt-names = "scanend";
 			reg = <0x4005c200 0x100>;
 			#io-channel-cells = <1>;
@@ -308,6 +298,43 @@
 			status = "disabled";
 		};
 
+		dac_global: dac_global@4005e000 {
+			compatible = "renesas,ra-dac-global";
+			reg = <0x4005e000 0x10c4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			dac0: dac@0 {
+				compatible = "renesas,ra-dac";
+				#io-channel-cells = <1>;
+				reg = <0>;
+				status = "disabled";
+			};
+
+			dac1: dac@1 {
+				compatible = "renesas,ra-dac";
+				#io-channel-cells = <1>;
+				reg = <1>;
+				status = "disabled";
+			};
+		};
+
+		usbfs: usbfs@40090000 {
+			compatible = "renesas,ra-usbfs";
+			reg = <0x40090000 0x2000>;
+			interrupts = <55 12>, <56 12>;
+			interrupt-names = "usbfs-i", "usbfs-r";
+			num-bidir-endpoints = <10>;
+			phys = <&usbfs_phy>;
+			phys-clock = <&uclk>;
+			status = "disabled";
+
+			udc {
+				compatible = "renesas,ra-udc";
+				status = "disabled";
+			};
+		};
+
 		id_code: id_code@100a150 {
 			compatible = "zephyr,memory-region";
 			reg = <0x0100a150 0x10>;
@@ -589,6 +616,22 @@
 			status = "disabled";
 		};
 
+		eth: ethernet@40064100 {
+			compatible = "renesas,ra-ethernet";
+			reg = <0x40064100 0xfc>;
+			interrupts = <51 0>;
+			local-mac-address = [00 11 22 33 44 55];
+			phy-connection-type = "rmii";
+			status = "disabled";
+		};
+
+		mdio: mdio {
+			compatible = "renesas,ra-mdio";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		flash: flash-controller@407e0000 {
 			compatible = "renesas,ra-flash-hp-controller";
 			reg = <0x407e0000 0x10000>;
@@ -597,6 +640,18 @@
 			interrupts = <49 1>, <50 1>;
 			interrupt-names = "frdyi", "fiferr";
 		};
+
+		wdt: wdt@40044200 {
+			compatible = "renesas,ra-wdt";
+			reg = <0x40044200 0x200>;
+			clocks = <&pclkb 0 0>;
+			status = "disabled";
+		};
+	};
+
+	usbfs_phy: usbfs-phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
 	};
 };
 
diff --git a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi
index 6afc6e3f0ce..629908e00e4 100644
--- a/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi
+++ b/dts/arm/renesas/ra/ra8/r7fa8d1xh.dtsi
@@ -155,6 +155,7 @@
 
 			cpuclk: cpuclk {
 				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <480000000>;
 				div = <1>;
 				#clock-cells = <2>;
 				status = "okay";
@@ -280,12 +281,13 @@
 
 	soc {
 		usbhs: usbhs@40351000 {
-			compatible = "renesas,ra-usb";
+			compatible = "renesas,ra-usbhs";
 			reg = <0x40351000 0x2000>;
-			interrupts = <54 12>, <55 12>, <56 12>;
-			interrupt-names = "usbhs-ir", "usbhs-d0", "usbhs-d1";
+			interrupts = <54 12>;
+			interrupt-names = "usbhs-ir";
 			num-bidir-endpoints = <10>;
 			phys = <&usbhs_phy>;
+			phys-clock = <&uclk>, <&u60clk>;
 			status = "disabled";
 			udc {
 				compatible = "renesas,ra-udc";
@@ -457,3 +459,8 @@
 	port-irq5-pins = <9>;
 	port-irq6-pins = <8>;
 };
+
+&dac_global {
+	has-internal-output;
+	has-output-amplifier;
+};
diff --git a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi
index ec801213b8f..88661e3abfe 100644
--- a/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi
+++ b/dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi
@@ -125,6 +125,7 @@
 
 			cpuclk: cpuclk {
 				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <480000000>;
 				div = <1>;
 				#clock-cells = <2>;
 				status = "okay";
@@ -244,12 +245,13 @@
 
 	soc {
 		usbhs: usbhs@40351000 {
-			compatible = "renesas,ra-usb";
+			compatible = "renesas,ra-usbhs";
 			reg = <0x40351000 0x2000>;
-			interrupts = <54 12>, <55 12>, <56 12>;
-			interrupt-names = "usbhs-ir", "usbhs-d0", "usbhs-d1";
+			interrupts = <54 12>;
+			interrupt-names = "usbhs-ir";
 			num-bidir-endpoints = <10>;
 			phys = <&usbhs_phy>;
+			phys-clock = <&uclk>, <&u60clk>;
 			status = "disabled";
 			udc {
 				compatible = "renesas,ra-udc";
@@ -421,3 +423,8 @@
 	port-irq5-pins = <9>;
 	port-irq6-pins = <8>;
 };
+
+&dac_global {
+	has-internal-output;
+	has-output-amplifier;
+};
diff --git a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi
index a575c4b9827..9c45b770951 100644
--- a/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi
+++ b/dts/arm/renesas/ra/ra8/r7fa8t1xh.dtsi
@@ -122,6 +122,7 @@
 
 			cpuclk: cpuclk {
 				compatible = "renesas,ra-cgc-pclk";
+				clock-frequency = <480000000>;
 				div = <1>;
 				#clock-cells = <2>;
 				status = "okay";
@@ -403,3 +404,8 @@
 	port-irq5-pins = <9>;
 	port-irq6-pins = <8>;
 };
+
+&dac_global {
+	has-internal-output;
+	has-output-amplifier;
+};
diff --git a/dts/arm/renesas/ra/ra8/ra8x1.dtsi b/dts/arm/renesas/ra/ra8/ra8x1.dtsi
index dd177c7f5ec..1155a02793f 100644
--- a/dts/arm/renesas/ra/ra8/ra8x1.dtsi
+++ b/dts/arm/renesas/ra/ra8/ra8x1.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,12 +22,28 @@
 			reg = <0>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+			cpu-power-states = <&stop0 &stop1>;
 
 			mpu: mpu@e000ed90 {
 				compatible = "arm,armv8.1m-mpu";
 				reg = <0xe000ed90 0x40>;
 			};
 		};
+
+		power-states {
+			stop0: state0 {
+				compatible = "zephyr,power-state";
+				power-state-name = "runtime-idle";
+				min-residency-us = <450>;
+			};
+
+			stop1: state1 {
+				compatible = "zephyr,power-state";
+				power-state-name = "standby";
+				min-residency-us = <5000>;
+				exit-latency-us = <3000>;
+			};
+		};
 	};
 
 	soc {
@@ -97,7 +113,7 @@
 			gpio-controller;
 			#gpio-cells = <2>;
 			ngpios = <16>;
-			vbatts_pins = <2 3 4>;
+			vbatts-pins = <2 3 4>;
 			status = "disabled";
 		};
 
@@ -198,6 +214,14 @@
 				channel = <0>;
 				status = "disabled";
 			};
+
+			i2c {
+				compatible = "renesas,ra-i2c-sci-b";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				channel = <0>;
+				status = "disabled";
+			};
 		};
 
 		sci1: sci1@40358100 {
@@ -212,6 +236,14 @@
 				channel = <1>;
 				status = "disabled";
 			};
+
+			i2c {
+				compatible = "renesas,ra-i2c-sci-b";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				channel = <1>;
+				status = "disabled";
+			};
 		};
 
 		sci2: sci2@40358200 {
@@ -226,6 +258,14 @@
 				channel = <2>;
 				status = "disabled";
 			};
+
+			i2c {
+				compatible = "renesas,ra-i2c-sci-b";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				channel = <2>;
+				status = "disabled";
+			};
 		};
 
 		sci3: sci3@40358300 {
@@ -240,6 +280,14 @@
 				channel = <3>;
 				status = "disabled";
 			};
+
+			i2c {
+				compatible = "renesas,ra-i2c-sci-b";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				channel = <3>;
+				status = "disabled";
+			};
 		};
 
 		sci4: sci4@40358400 {
@@ -254,6 +302,14 @@
 				channel = <4>;
 				status = "disabled";
 			};
+
+			i2c {
+				compatible = "renesas,ra-i2c-sci-b";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				channel = <4>;
+				status = "disabled";
+			};
 		};
 
 		sci9: sci9@40358900 {
@@ -268,6 +324,14 @@
 				channel = <9>;
 				status = "disabled";
 			};
+
+			i2c {
+				compatible = "renesas,ra-i2c-sci-b";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				channel = <9>;
+				status = "disabled";
+			};
 		};
 
 		flash: flash-controller@40100000 {
@@ -290,7 +354,6 @@
 			reg = <0x40332000 0x100>;
 			#io-channel-cells = <1>;
 			vref-mv = <3300>;
-			channel-count = <12>;
 			channel-available-mask = <0xf01f7>;
 			status = "disabled";
 		};
@@ -302,11 +365,31 @@
 			reg = <0x40332200 0x100>;
 			#io-channel-cells = <1>;
 			vref-mv = <3300>;
-			channel-count = <13>;
 			channel-available-mask = <0x7f0077>;
 			status = "disabled";
 		};
 
+		dac_global: dac_global@40333000 {
+			compatible = "renesas,ra-dac-global";
+			reg = <0x40333000 0x10c4>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			dac0: dac@0 {
+				compatible = "renesas,ra-dac";
+				#io-channel-cells = <1>;
+				reg = <0>;
+				status = "disabled";
+			};
+
+			dac1: dac@1 {
+				compatible = "renesas,ra-dac";
+				#io-channel-cells = <1>;
+				reg = <1>;
+				status = "disabled";
+			};
+		};
+
 		trng: trng {
 			compatible = "renesas,ra-rsip-e51a-trng";
 		};
@@ -477,6 +560,32 @@
 			status = "disabled";
 		};
 
+		ulpt0: ulpt@40220000 {
+			compatible = "renesas,ra-ulpt";
+			reg = <0x40220000 0x100>;
+			channel = <0>;
+			interrupt-names = "ulpti";
+			interrupts = <36 1>;
+			status = "disabled";
+
+			timer {
+				compatible = "renesas,ra-ulpt-timer";
+				status = "disabled";
+			};
+		};
+
+		ulpt1: ulpt@40220100 {
+			compatible = "renesas,ra-ulpt";
+			reg = <0x40220100 0x100>;
+			channel = <1>;
+			status = "disabled";
+
+			timer {
+				compatible = "renesas,ra-ulpt-timer";
+				status = "disabled";
+			};
+		};
+
 		option_setting_ofs: option_setting_ofs@300a100 {
 			compatible = "zephyr,memory-region";
 			reg = <0x0300a100 0x18>;
@@ -538,6 +647,8 @@
 			interrupt-names = "rxf", "glerr";
 			clocks = <&pclka 0 0>, <&pclke 0 0>;
 			clock-names = "opclk", "ramclk";
+			dll-min-freq = <DT_FREQ_M(8)>;
+			dll-max-freq = <DT_FREQ_M(80)>;
 			reg = <0x40380000 0x4000>;
 			status = "disabled";
 
@@ -749,6 +860,52 @@
 			reg = <0x40252400 0x0400>;
 			status = "disabled";
 		};
+
+		wdt: wdt@40083400 {
+			compatible = "renesas,ra-wdt";
+			reg = <0x40083400 0x200>;
+			clocks = <&pclkb 0 0>;
+			status = "disabled";
+		};
+
+		usbfs: usbfs@40250000 {
+			compatible = "renesas,ra-usbfs";
+			reg = <0x40250000 0x2000>;
+			interrupts = <55 12>, <56 12>;
+			interrupt-names = "usbfs-i", "usbfs-r";
+			num-bidir-endpoints = <10>;
+			phys = <&usbfs_phy>;
+			phys-clock = <&uclk>;
+			status = "disabled";
+
+			udc {
+				compatible = "renesas,ra-udc";
+				status = "disabled";
+			};
+		};
+
+		acmphs_global: acmphs_global@40236000 {
+			compatible = "renesas,ra-acmphs-global";
+			reg = <0x40236000 0x200>;
+			status = "disabled";
+
+			acmphs0: acmphs0 {
+				compatible = "renesas,ra-acmphs";
+				channel = <0>;
+				status = "disabled";
+			};
+
+			acmphs1: acmphs1 {
+				compatible = "renesas,ra-acmphs";
+				channel = <1>;
+				status = "disabled";
+			};
+		};
+	};
+
+	usbfs_phy: usbfs-phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
 	};
 };
 
diff --git a/dts/arm/renesas/rz/rza/r7s9210.dtsi b/dts/arm/renesas/rz/rza/r7s9210.dtsi
new file mode 100644
index 00000000000..16b0399a0b9
--- /dev/null
+++ b/dts/arm/renesas/rz/rza/r7s9210.dtsi
@@ -0,0 +1,392 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv7-a.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+#include <zephyr/dt-bindings/clock/renesas_rza2m_clock.h>
+
+/ {
+	compatible = "renesas,r7s9210";
+	interrupt-parent = <&gic>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a9";
+			reg = <0>;
+		};
+	};
+
+	osc: osc {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&gic>;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		gic: interrupt-controller@e8221000 {
+			compatible = "arm,gic-400", "arm,gic-v2", "arm,gic";
+			#interrupt-cells = <4>;
+			#address-cells = <0>;
+			interrupt-controller;
+			reg = <0xe8221000 0x1000>,
+			      <0xe8222000 0x1000>;
+		};
+
+		ram: memory@80020000 {
+			compatible = "mmio-sram";
+			reg = <0x80020000 (DT_SIZE_M(4) - 0x20000)>;
+		};
+
+		cpg: clock-controller@fcfe0010 {
+			compatible = "renesas,rza2m-cpg";
+			reg = <0xfcfe0010 0x455>;
+			#clock-cells = <1>;
+			clocks = <&osc>;
+
+			iclk: iclk {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+			};
+
+			bclk: bclk {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+			};
+
+			p1clk: p1clk {
+				compatible = "fixed-clock";
+				#clock-cells = <0>;
+			};
+		};
+
+		ostm0: timer@e803b000 {
+			compatible = "renesas,rza2m-ostm";
+			reg = <0xe803b000 0x30>;
+			interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+			clocks = <&cpg RZA2M_CLOCK(RZA2M_MODULE_OSTM0, RZA2M_CLK_P1C)>;
+			status = "disabled";
+		};
+
+		ostm1: timer@e803c000 {
+			compatible = "renesas,rza2m-ostm";
+			reg = <0xe803c000 0x30>;
+			interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+			clocks = <&cpg RZA2M_CLOCK(RZA2M_MODULE_OSTM1, RZA2M_CLK_P1C)>;
+			status = "disabled";
+		};
+
+		ostm2: timer@e803d000 {
+			compatible = "renesas,rza2m-ostm";
+			reg = <0xe803d000 0x30>;
+			interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+			clocks = <&cpg RZA2M_CLOCK(RZA2M_MODULE_OSTM2, RZA2M_CLK_P1C)>;
+			status = "disabled";
+		};
+
+		pinctrl: pin-controller@fcffe000 {
+			compatible = "renesas,rza2m-pinctrl";
+			reg = <0xfcffe000 0x1000>;
+
+			gpio: gpio-common {
+				compatible = "renesas,rza2m-gpio-int";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "okay";
+
+				interrupts = <GIC_SPI 511 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 510 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 509 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 508 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 507 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 506 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 505 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 504 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 503 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 502 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 501 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 500 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 499 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 498 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 497 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 496 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 495 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 494 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 493 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 492 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 491 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 490 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 489 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 488 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 487 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 486 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 485 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 484 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 483 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 482 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 481 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					     <GIC_SPI 480 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+
+				gpio0: gpio@0 {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0x0>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <7>;
+				};
+
+				gpio1: gpio@1 {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0x1>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <5>;
+				};
+
+				gpio2: gpio@2 {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0x2>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <4>;
+				};
+
+				gpio3: gpio@3 {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0x3>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <6>;
+				};
+
+				gpio4: gpio@4 {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0x4>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <8>;
+				};
+
+				gpio5: gpio@5 {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0x5>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <8>;
+				};
+
+				gpio6: gpio@6 {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0x6>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <8>;
+				};
+
+				gpio7: gpio@7 {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0x7>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <8>;
+				};
+
+				gpio8: gpio@8 {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0x8>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <8>;
+				};
+
+				gpio9: gpio@9 {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0x9>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <8>;
+				};
+
+				gpioa: gpio@a {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0xa>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <8>;
+				};
+
+				gpiob: gpio@b {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0xb>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <6>;
+				};
+
+				gpioc: gpio@c {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0xc>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <8>;
+				};
+
+				gpiod: gpio@d {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0xd>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <8>;
+				};
+
+				gpioe: gpio@e {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0xe>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <7>;
+				};
+
+				gpiof: gpio@f {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0xf>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <8>;
+				};
+
+				gpiog: gpio@10 {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0x10>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <8>;
+				};
+
+				gpioh: gpio@11 {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0x11>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <7>;
+				};
+
+				gpioj: gpio@12 {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0x12>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <8>;
+				};
+
+				gpiok: gpio@13 {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0x13>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <6>;
+				};
+
+				gpiol: gpio@14 {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0x14>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <5>;
+				};
+
+				gpiom: gpio@15 {
+					compatible = "renesas,rza2m-gpio";
+					reg = <0x15>;
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+				};
+			};
+		};
+
+		scif0: serial@e8007000 {
+			compatible = "renesas,rza2m-scif-uart";
+			channel = <0>;
+			reg = <0xe8007000 0x18>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 298 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 299 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 300 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg RZA2M_CLOCK(RZA2M_MODULE_SCIFA0, RZA2M_CLK_P1C)>;
+			status = "disabled";
+		};
+
+		scif1: serial@e8007800 {
+			compatible = "renesas,rza2m-scif-uart";
+			channel = <1>;
+			reg = <0xe8007800 0x18>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 304 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 305 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 306 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg RZA2M_CLOCK(RZA2M_MODULE_SCIFA1, RZA2M_CLK_P1C)>;
+			status = "disabled";
+		};
+
+		scif2: serial@e8008000 {
+			compatible = "renesas,rza2m-scif-uart";
+			channel = <2>;
+			reg = <0xe8008000 0x18>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 310 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 311 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 312 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg RZA2M_CLOCK(RZA2M_MODULE_SCIFA2, RZA2M_CLK_P1C)>;
+			status = "disabled";
+		};
+
+		scif3: serial@e8008800 {
+			compatible = "renesas,rza2m-scif-uart";
+			channel = <3>;
+			reg = <0xe8008800 0x18>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 316 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 317 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 318 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg RZA2M_CLOCK(RZA2M_MODULE_SCIFA3, RZA2M_CLK_P1C)>;
+			status = "disabled";
+		};
+
+		scif4: serial@e8009000 {
+			compatible = "renesas,rza2m-scif-uart";
+			channel = <4>;
+			reg = <0xe8009000 0x18>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 322 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 323 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 324 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			clocks = <&cpg RZA2M_CLOCK(RZA2M_MODULE_SCIFA4, RZA2M_CLK_P1C)>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/dts/arm/renesas/rz/rzg/r9a07g044.dtsi b/dts/arm/renesas/rz/rzg/r9a07g044.dtsi
new file mode 100644
index 00000000000..e34913b34dd
--- /dev/null
+++ b/dts/arm/renesas/rz/rzg/r9a07g044.dtsi
@@ -0,0 +1,545 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv8-m.dtsi>
+#include <mem.h>
+#include <freq.h>
+
+/ {
+	compatible = "renesas,r9a07g044";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m33";
+			reg = <0>;
+			clock-frequency = <DT_FREQ_M(200)>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	soc {
+		pinctrl: pin-controller@41030000 {
+			compatible = "renesas,rzg-pinctrl";
+			reg = <0x41030000 DT_SIZE_K(64)>;
+			reg-names = "pinctrl";
+
+			gpio: gpio-common {
+				compatible = "renesas,rz-gpio-int";
+				interrupts =
+					<444 10>, <445 10>, <446 10>, <447 10>,
+					<448 10>, <449 10>, <450 10>, <451 10>,
+					<452 10>, <453 10>, <454 10>, <455 10>,
+					<456 10>, <457 10>, <458 10>, <459 10>,
+					<460 10>, <461 10>, <462 10>, <463 10>,
+					<464 10>, <465 10>, <466 10>, <467 10>,
+					<468 10>, <469 10>, <470 10>, <471 10>,
+					<472 10>, <473 10>, <474 10>, <475 10>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+
+				gpio0: gpio@0 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x0>;
+					status = "disabled";
+				};
+
+				gpio1: gpio@100 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <2>;
+					reg = <0x100>;
+					status = "disabled";
+				};
+
+				gpio2: gpio@200 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <2>;
+					reg = <0x200>;
+					status = "disabled";
+				};
+
+				gpio3: gpio@300 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <2>;
+					reg = <0x300>;
+					status = "disabled";
+				};
+
+				gpio4: gpio@400 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <2>;
+					reg = <0x400>;
+					status = "disabled";
+				};
+
+				gpio5: gpio@500 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <3>;
+					reg = <0x500>;
+					status = "disabled";
+				};
+
+				gpio6: gpio@600 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <2>;
+					reg = <0x600>;
+					status = "disabled";
+				};
+
+				gpio7: gpio@700 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <3>;
+					reg = <0x700>;
+					status = "disabled";
+				};
+
+				gpio8: gpio@800 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <2>;
+					reg = <0x800>;
+					status = "disabled";
+				};
+
+				gpio9: gpio@900 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <2>;
+					reg = <0x900>;
+					status = "disabled";
+				};
+
+				gpio10: gpio@a00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <2>;
+					reg = <0xa00>;
+					status = "disabled";
+				};
+
+				gpio11: gpio@b00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <2>;
+					reg = <0xb00>;
+					status = "disabled";
+				};
+
+				gpio12: gpio@c00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <2>;
+					reg = <0xc00>;
+					status = "disabled";
+				};
+
+				gpio13: gpio@d00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <3>;
+					reg = <0xd00>;
+					status = "disabled";
+				};
+
+				gpio14: gpio@e00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <2>;
+					reg = <0xe00>;
+					status = "disabled";
+				};
+
+				gpio15: gpio@f00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <2>;
+					reg = <0xf00>;
+					status = "disabled";
+				};
+
+				gpio16: gpio@1000 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <2>;
+					reg = <0x1000>;
+					status = "disabled";
+				};
+
+				gpio17: gpio@1100 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <3>;
+					reg = <0x1100>;
+					status = "disabled";
+				};
+
+				gpio18: gpio@1200 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x1200>;
+					status = "disabled";
+				};
+
+				gpio19: gpio@1300 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x1300>;
+					status = "disabled";
+				};
+
+				gpio20: gpio@1400 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <3>;
+					reg = <0x1400>;
+					status = "disabled";
+				};
+
+				gpio21: gpio@1500 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x1500>;
+					status = "disabled";
+				};
+
+				gpio22: gpio@1600 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x1600>;
+					status = "disabled";
+				};
+
+				gpio23: gpio@1700 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x1700>;
+					status = "disabled";
+				};
+
+				gpio24: gpio@1800 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x1800>;
+					status = "disabled";
+				};
+
+				gpio25: gpio@1900 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x1900>;
+					status = "disabled";
+				};
+
+				gpio26: gpio@1a00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x1a00>;
+					status = "disabled";
+				};
+
+				gpio27: gpio@1b00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x1b00>;
+					status = "disabled";
+				};
+
+				gpio28: gpio@1c00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x1c00>;
+					status = "disabled";
+				};
+
+				gpio29: gpio@1d00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x1d00>;
+					status = "disabled";
+				};
+
+				gpio30: gpio@1e00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x1e00>;
+					status = "disabled";
+				};
+
+				gpio31: gpio@1f00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x1f00>;
+					status = "disabled";
+				};
+
+				gpio32: gpio@2000 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x2000>;
+					status = "disabled";
+				};
+
+				gpio33: gpio@2100 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x2100>;
+					status = "disabled";
+				};
+				gpio34: gpio@2200 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x2200>;
+					status = "disabled";
+				};
+
+				gpio35: gpio@2300 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x2300>;
+					status = "disabled";
+				};
+
+				gpio36: gpio@2400 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x2400>;
+					status = "disabled";
+				};
+
+				gpio37: gpio@2500 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <3>;
+					reg = <0x2500>;
+					status = "disabled";
+				};
+
+				gpio38: gpio@2600 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <3>;
+					reg = <0x2600>;
+					status = "disabled";
+				};
+
+				gpio39: gpio@2700 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x2700>;
+					status = "disabled";
+				};
+
+				gpio40: gpio@2800 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x2800>;
+					status = "disabled";
+				};
+
+				gpio41: gpio@2900 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x2900>;
+					status = "disabled";
+				};
+
+				gpio42: gpio@2a00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <2>;
+					reg = <0x2a00>;
+					status = "disabled";
+				};
+
+				gpio43: gpio@2b00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <5>;
+					reg = <0x2b00>;
+					status = "disabled";
+				};
+
+				gpio44: gpio@2c00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <3>;
+					reg = <0x2c00>;
+					status = "disabled";
+				};
+				gpio45: gpio@2d00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <4>;
+					reg = <0x2d00>;
+					status = "disabled";
+				};
+
+				gpio46: gpio@2e00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <4>;
+					reg = <0x2e00>;
+					status = "disabled";
+				};
+
+				gpio47: gpio@2f00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <4>;
+					reg = <0x2f00>;
+					status = "disabled";
+				};
+
+				gpio48: gpio@3000 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <4>;
+					reg = <0x3000>;
+					status = "disabled";
+				};
+			};
+		};
+
+		scif0: serial@4004b800 {
+			compatible = "renesas,rz-scif-uart";
+			channel = <0>;
+			reg = <0x4004b800 DT_SIZE_K(1)>;
+			interrupts = <380 1>, <381 1>, <382 1>, <383 1>, <384 1>;
+			interrupt-names = "eri", "bri", "rxi", "txi", "tei";
+			status = "disabled";
+		};
+
+		scif1: serial@4004bc00 {
+			compatible = "renesas,rz-scif-uart";
+			channel = <1>;
+			reg = <0x4004bc00 DT_SIZE_K(1)>;
+			interrupts = <385 1>, <386 1>, <387 1>, <388 1>, <389 1>;
+			interrupt-names = "eri", "bri", "rxi", "txi", "tei";
+			status = "disabled";
+		};
+
+		scif2: serial@4004c000 {
+			compatible = "renesas,rz-scif-uart";
+			channel = <2>;
+			reg = <0x4004c000 DT_SIZE_K(1)>;
+			interrupts = <390 1>, <391 1>, <392 1>, <393 1>, <394 1>;
+			interrupt-names = "eri", "bri", "rxi", "txi", "tei";
+			status = "disabled";
+		};
+
+		scif3: serial@4004c400 {
+			compatible = "renesas,rz-scif-uart";
+			channel = <3>;
+			reg = <0x4004c400 DT_SIZE_K(1)>;
+			interrupts = <395 1>, <396 1>, <397 1>, <398 1>, <399 1>;
+			interrupt-names = "eri", "bri", "rxi", "txi", "tei";
+			status = "disabled";
+		};
+
+		scif4: serial@4004c800 {
+			compatible = "renesas,rz-scif-uart";
+			channel = <4>;
+			reg = <0x4004c800 DT_SIZE_K(1)>;
+			interrupts = <400 1>, <401 1>, <402 1>, <403 1>, <404 1>;
+			interrupt-names = "eri", "bri", "rxi", "txi", "tei";
+			status = "disabled";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <7>;
+};
diff --git a/dts/arm/renesas/rz/rzg/r9a07g044c.dtsi b/dts/arm/renesas/rz/rzg/r9a07g044c.dtsi
new file mode 100644
index 00000000000..930faeea63e
--- /dev/null
+++ b/dts/arm/renesas/rz/rzg/r9a07g044c.dtsi
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/renesas/rz/rzg/r9a07g044.dtsi>
+
+/delete-node/ &scif4;
diff --git a/dts/arm/renesas/rz/rzg/r9a08g045.dtsi b/dts/arm/renesas/rz/rzg/r9a08g045.dtsi
index 2bbb5573b15..25a8ad3f041 100644
--- a/dts/arm/renesas/rz/rzg/r9a08g045.dtsi
+++ b/dts/arm/renesas/rz/rzg/r9a08g045.dtsi
@@ -5,7 +5,10 @@
  */
 
 #include <arm/armv8-m.dtsi>
+#include <dt-bindings/i2c/i2c.h>
 #include <mem.h>
+#include <freq.h>
+#include <zephyr/dt-bindings/adc/adc.h>
 
 / {
 	compatible = "renesas,r9a08g045";
@@ -31,7 +34,176 @@
 		};
 	};
 
+	osc: osc {
+		compatible = "fixed-clock";
+		clock-frequency = <DT_FREQ_M(24)>;
+		#clock-cells = <0>;
+	};
+
 	soc {
+		cpg: clock-controller@41010000 {
+			compatible = "renesas,rz-cpg";
+			reg = <0x41010000 0x10000>;
+			clocks = <&osc>;
+			#clock-cells = <1>;
+			status = "okay";
+
+			iclk: iclk {
+				compatible = "fixed-clock";
+				clock-frequency = <DT_FREQ_M(1100)>;
+				#clock-cells = <0>;
+			};
+
+			p0clk: p0clk {
+				compatible = "fixed-clock";
+				clock-frequency = <DT_FREQ_M(100)>;
+				#clock-cells = <0>;
+			};
+
+			p4clk: p4clk {
+				compatible = "fixed-clock";
+				clock-frequency = <DT_FREQ_M(160)>;
+				#clock-cells = <0>;
+			};
+
+			p5clk: p5clk {
+				compatible = "fixed-clock";
+				clock-frequency = <DT_FREQ_M(200)>;
+				#clock-cells = <0>;
+			};
+
+			tsuclk: tsuclk {
+				compatible = "fixed-clock";
+				clock-frequency = <DT_FREQ_M(100)>;
+				#clock-cells = <0>;
+			};
+
+			sd0clk: sd0clk {
+				compatible = "fixed-clock";
+				clock-frequency = <133333333>;
+				#clock-cells = <0>;
+			};
+
+			sd1clk: sd1clk {
+				compatible = "fixed-clock";
+				clock-frequency = <133333333>;
+				#clock-cells = <0>;
+			};
+
+			sd2clk: sd2clk {
+				compatible = "fixed-clock";
+				clock-frequency = <133333333>;
+				#clock-cells = <0>;
+			};
+
+			m0clk: m0clk {
+				compatible = "fixed-clock";
+				clock-frequency = <DT_FREQ_M(200)>;
+				#clock-cells = <0>;
+			};
+
+			p1clk: p1clk {
+				compatible = "fixed-clock";
+				clock-frequency = <DT_FREQ_M(200)>;
+				#clock-cells = <0>;
+			};
+
+			p2clk: p2clk {
+				compatible = "fixed-clock";
+				clock-frequency = <DT_FREQ_M(100)>;
+				#clock-cells = <0>;
+			};
+
+			p3clk: p3clk {
+				compatible = "fixed-clock";
+				clock-frequency = <DT_FREQ_M(200)>;
+				#clock-cells = <0>;
+			};
+
+			atclk: atclk {
+				compatible = "fixed-clock";
+				clock-frequency = <DT_FREQ_M(400)>;
+				#clock-cells = <0>;
+			};
+
+			ztclk: ztclk {
+				compatible = "fixed-clock";
+				clock-frequency = <DT_FREQ_M(100)>;
+				#clock-cells = <0>;
+			};
+
+			oc0clk: oc0clk {
+				compatible = "fixed-clock";
+				clock-frequency = <33333333>;
+				#clock-cells = <0>;
+			};
+
+			oc1clk: oc1clk {
+				compatible = "fixed-clock";
+				clock-frequency = <16666666>;
+				#clock-cells = <0>;
+			};
+
+			spi0clk: spi0clk {
+				compatible = "fixed-clock";
+				clock-frequency = <33333333>;
+				#clock-cells = <0>;
+			};
+
+			spi1clk: spi1clk {
+				compatible = "fixed-clock";
+				clock-frequency = <16666666>;
+				#clock-cells = <0>;
+			};
+
+			s0clk: s0clk {
+				compatible = "fixed-clock";
+				clock-frequency = <DT_FREQ_M(400)>;
+				#clock-cells = <0>;
+			};
+
+			i2clk: i2clk {
+				compatible = "fixed-clock";
+				clock-frequency = <DT_FREQ_M(250)>;
+				#clock-cells = <0>;
+			};
+
+			i3clk: i3clk {
+				compatible = "fixed-clock";
+				clock-frequency = <DT_FREQ_M(250)>;
+				#clock-cells = <0>;
+			};
+
+			hpclk: hpclk {
+				compatible = "fixed-clock";
+				clock-frequency = <DT_FREQ_M(250)>;
+				#clock-cells = <0>;
+			};
+
+			oscclk: oscclk {
+				compatible = "fixed-clock";
+				clock-frequency = <DT_FREQ_M(24)>;
+				#clock-cells = <0>;
+			};
+
+			osc2clk: osc2clk {
+				compatible = "fixed-clock";
+				clock-frequency = <DT_FREQ_M(8)>;
+				#clock-cells = <0>;
+			};
+		};
+
+		adc: adc@40058000 {
+			compatible = "renesas,rz-adc";
+			reg = <0x40058000 0x80>;
+			interrupts = <312 3>;
+			interrupt-names = "scanend";
+			#io-channel-cells = <1>;
+			vref-mv = <1800>;
+			channel-available-mask = <0x01FF>;
+			status = "disabled";
+		};
+
 		pinctrl: pin-controller@41030000 {
 			compatible = "renesas,rzg-pinctrl";
 			reg = <0x41030000 DT_SIZE_K(64)>;
@@ -225,6 +397,26 @@
 			};
 		};
 
+		dma0: dma@41800000 { /* Secure DMA */
+			compatible = "renesas,rz-dma";
+			reg = <0x41800000 0x800>, <0x41810000 0x20>;
+			reg-names = "reg_main", "ext";
+			interrupts =  <95 1>,  <96 1>,  <97 1>,  <98 1>,
+				      <99 1>, <100 1>, <101 1>, <102 1>,
+				     <103 1>, <104 1>, <105 1>, <106 1>,
+				     <107 1>, <108 1>, <109 1>, <110 1>,
+				      <94 1>; /* DMAERR1 */
+			interrupt-names = "ch0",   "ch1",  "ch2",  "ch3",
+					  "ch4",   "ch5",  "ch6",  "ch7",
+					  "ch8",   "ch9", "ch10", "ch11",
+					  "ch12", "ch13", "ch14", "ch15",
+					  "err1";
+			dma-channels = <16>;
+			#dma-cells = <2>;
+			dma-buf-addr-alignment = <4>;
+			status = "disabled";
+		};
+
 		scif0: serial@4004b800 {
 			compatible = "renesas,rz-scif-uart";
 			channel = <0>;
@@ -273,6 +465,424 @@
 			interrupt-names = "eri", "bri", "rxi", "txi", "tei";
 			status = "disabled";
 		};
+
+		i2c0: i2c@40090000 {
+			compatible = "renesas,rz-riic";
+			channel = <0>;
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40090000 0x15>;
+			interrupts = <257 1>, <258 1>, <259 1>, <260 1>,
+				     <261 1>, <262 1>, <263 1>, <264 1>;
+			interrupt-names = "tei", "naki", "spi", "sti", "ali", "tmoi", "rxi", "txi";
+			status = "disabled";
+		};
+		i2c1: i2c@40090400 {
+			compatible = "renesas,rz-riic";
+			channel = <1>;
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40090400 0x15>;
+			interrupts = <265 1>, <266 1>, <267 1>, <268 1>,
+				     <269 1>, <270 1>, <271 1>, <272 1>;
+			interrupt-names = "tei", "naki", "spi", "sti", "ali", "tmoi", "rxi", "txi";
+			status = "disabled";
+		};
+		i2c2: i2c@40090800 {
+			compatible = "renesas,rz-riic";
+			channel = <2>;
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40090800 0x15>;
+			interrupts = <273 1>, <274 1>, <275 1>, <276 1>,
+				     <277 1>, <278 1>, <279 1>, <280 1>;
+			interrupt-names = "tei", "naki", "spi", "sti", "ali", "tmoi", "rxi", "txi";
+			status = "disabled";
+		};
+		i2c3: i2c@40090c00 {
+			compatible = "renesas,rz-riic";
+			channel = <3>;
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40090c00 0x15>;
+			interrupts = <281 1>, <282 1>, <283 1>, <284 1>,
+				     <285 1>, <286 1>, <287 1>, <288 1>;
+			interrupt-names = "tei", "naki", "spi", "sti", "ali", "tmoi", "rxi", "txi";
+			status = "disabled";
+		};
+
+		gtm0: gtm@42801000 {
+			compatible = "renesas,rz-gtm";
+			reg = <0x42801000 0x30>;
+			channel = <0>;
+			interrupts = <44 1>;
+			interrupt-names = "overflow";
+			status = "disabled";
+
+			counter {
+				compatible = "renesas,rz-gtm-counter";
+				status = "disabled";
+			};
+		};
+		gtm1: gtm@42801400 {
+			compatible = "renesas,rz-gtm";
+			reg = <0x42801400 0x30>;
+			channel = <1>;
+			interrupts = <45 1>;
+			interrupt-names = "overflow";
+			status = "disabled";
+
+			counter {
+				compatible = "renesas,rz-gtm-counter";
+				status = "disabled";
+			};
+		};
+		gtm2: gtm@42801800 {
+			compatible = "renesas,rz-gtm";
+			reg = <0x42801800 0x30>;
+			channel = <2>;
+			interrupts = <46 1>;
+			interrupt-names = "overflow";
+			status = "disabled";
+
+			counter {
+				compatible = "renesas,rz-gtm-counter";
+				status = "disabled";
+			};
+		};
+		gtm3: gtm@42801c00 {
+			compatible = "renesas,rz-gtm";
+			reg = <0x42801c00 0x30>;
+			channel = <3>;
+			interrupts = <47 1>;
+			interrupt-names = "overflow";
+			status = "disabled";
+
+			counter {
+				compatible = "renesas,rz-gtm-counter";
+				status = "disabled";
+			};
+		};
+		gtm4: gtm@42802000 {
+			compatible = "renesas,rz-gtm";
+			reg = <0x42802000 0x30>;
+			channel = <4>;
+			interrupts = <48 1>;
+			interrupt-names = "overflow";
+			status = "disabled";
+
+			counter {
+				compatible = "renesas,rz-gtm-counter";
+				status = "disabled";
+			};
+		};
+		gtm5: gtm@42802400 {
+			compatible = "renesas,rz-gtm";
+			reg = <0x42802400 0x30>;
+			channel = <5>;
+			interrupts = <49 1>;
+			interrupt-names = "overflow";
+			status = "disabled";
+
+			counter {
+				compatible = "renesas,rz-gtm-counter";
+				status = "disabled";
+			};
+		};
+		gtm6: gtm@42802800 {
+			compatible = "renesas,rz-gtm";
+			reg = <0x42802800 0x30>;
+			channel = <6>;
+			interrupts = <50 1>;
+			interrupt-names = "overflow";
+			status = "disabled";
+
+			counter {
+				compatible = "renesas,rz-gtm-counter";
+				status = "disabled";
+			};
+		};
+		gtm7: gtm@42802c00 {
+			compatible = "renesas,rz-gtm";
+			reg = <0x42802c00 0x30>;
+			channel = <7>;
+			interrupts = <51 1>;
+			interrupt-names = "overflow";
+			status = "disabled";
+
+			counter {
+				compatible = "renesas,rz-gtm-counter";
+				status = "disabled";
+			};
+		};
+
+		gpt32e0: gpt32e@50048000 {
+			compatible = "renesas,rz-gpt";
+			reg = <0x50048000 0xa4>;
+			channel = <0>;
+			interrupts = <128 1>, <129 1>, <130 1>, <131 1>, <132 1>,
+				     <133 1>, <134 1>, <135 1>, <136 1>, <137 1>;
+			interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe",
+					  "cmpf", "adtrga", "adtrgb", "ovf", "unf";
+			prescaler = <1>;
+			status = "disabled";
+
+			pwm {
+				compatible = "renesas,rz-gpt-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+		};
+		gpt32e1: gpt32e@50048100 {
+			compatible = "renesas,rz-gpt";
+			reg = <0x50048100 0xa4>;
+			channel = <1>;
+			interrupts = <141 1>, <142 1>, <143 1>, <144 1>, <145 1>,
+				     <146 1>, <147 1>, <148 1>, <149 1>, <150 1>;
+			interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe",
+					  "cmpf", "adtrga", "adtrgb", "ovf", "unf";
+			prescaler = <1>;
+			status = "disabled";
+
+			pwm {
+				compatible = "renesas,rz-gpt-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+		};
+		gpt32e2: gpt32e@50048200 {
+			compatible = "renesas,rz-gpt";
+			reg = <0x50048200 0xa4>;
+			channel = <2>;
+			interrupts = <154 1>, <155 1>, <156 1>, <157 1>, <158 1>,
+				     <159 1>, <160 1>, <161 1>, <162 1>, <163 1>;
+			interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe",
+					  "cmpf", "adtrga", "adtrgb", "ovf", "unf";
+			prescaler = <1>;
+			status = "disabled";
+
+			pwm {
+				compatible = "renesas,rz-gpt-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+		};
+		gpt32e3: gpt32e@50048300 {
+			compatible = "renesas,rz-gpt";
+			reg = <0x50048300 0xa4>;
+			channel = <3>;
+			interrupts = <167 1>, <168 1>, <169 1>, <170 1>, <171 1>,
+				     <172 1>, <173 1>, <174 1>, <175 1>, <176 1>;
+			interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe",
+					  "cmpf", "adtrga", "adtrgb", "ovf", "unf";
+			prescaler = <1>;
+			status = "disabled";
+
+			pwm {
+				compatible = "renesas,rz-gpt-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+		};
+		gpt32e4: gpt32e@50048400 {
+			compatible = "renesas,rz-gpt";
+			reg = <0x50048400 0xa4>;
+			channel = <4>;
+			interrupts = <180 1>, <181 1>, <182 1>, <183 1>, <184 1>,
+				     <185 1>, <186 1>, <187 1>, <188 1>, <189 1>;
+			interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe",
+					  "cmpf", "adtrga", "adtrgb", "ovf", "unf";
+			prescaler = <1>;
+			status = "disabled";
+
+			pwm {
+				compatible = "renesas,rz-gpt-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+		};
+		gpt32e5: gpt32e@50048500 {
+			compatible = "renesas,rz-gpt";
+			reg = <0x50048500 0xa4>;
+			channel = <5>;
+			interrupts = <193 1>, <194 1>, <195 1>, <196 1>, <197 1>,
+				     <198 1>, <199 1>, <200 1>, <201 1>, <202 1>;
+			interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe",
+					  "cmpf", "adtrga", "adtrgb", "ovf", "unf";
+			prescaler = <1>;
+			status = "disabled";
+
+			pwm {
+				compatible = "renesas,rz-gpt-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+		};
+		gpt32e6: gpt32e@50048600 {
+			compatible = "renesas,rz-gpt";
+			reg = <0x50048600 0xa4>;
+			channel = <6>;
+			interrupts = <206 1>, <207 1>, <208 1>, <209 1>, <210 1>,
+				     <211 1>, <212 1>, <213 1>, <214 1>, <215 1>;
+			interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe",
+					  "cmpf", "adtrga", "adtrgb", "ovf", "unf";
+			prescaler = <1>;
+			status = "disabled";
+
+			pwm {
+				compatible = "renesas,rz-gpt-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+		};
+		gpt32e7: gpt32e@50048700 {
+			compatible = "renesas,rz-gpt";
+			reg = <0x50048700 0xa4>;
+			channel = <7>;
+			interrupts = <219 1>, <220 1>, <221 1>, <222 1>, <223 1>,
+				     <224 1>, <225 1>, <226 1>, <227 1>, <228 1>;
+			interrupt-names = "ccmpa", "ccmpb", "cmpc", "cmpd", "cmpe",
+					  "cmpf", "adtrga", "adtrgb", "ovf", "unf";
+			prescaler = <1>;
+			status = "disabled";
+
+			pwm {
+				compatible = "renesas,rz-gpt-pwm";
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+		};
+
+		intc: interrupt-controller@41060000 {
+			reg = <0x41060000 0x18>;
+			#address-cells = <0>;
+			interrupt-parent = <&nvic>;
+
+			nmi: nmi {
+				compatible = "renesas,rz-ext-irq";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <0 1>; //NMI
+				status = "disabled";
+			};
+
+			irq0: irq0 {
+				compatible = "renesas,rz-ext-irq";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <1 1>;
+				status = "disabled";
+			};
+			irq1: irq1 {
+				compatible = "renesas,rz-ext-irq";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <2 1>;
+				status = "disabled";
+			};
+			irq2: irq2 {
+				compatible = "renesas,rz-ext-irq";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <3 1>;
+				status = "disabled";
+			};
+			irq3: irq3 {
+				compatible = "renesas,rz-ext-irq";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <4 1>;
+				status = "disabled";
+			};
+			irq4: irq4 {
+				compatible = "renesas,rz-ext-irq";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <5 1>;
+				status = "disabled";
+			};
+			irq5: irq5 {
+				compatible = "renesas,rz-ext-irq";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <6 1>;
+				status = "disabled";
+			};
+			irq6: irq6 {
+				compatible = "renesas,rz-ext-irq";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <7 1>;
+				status = "disabled";
+			};
+			irq7: irq7 {
+				compatible = "renesas,rz-ext-irq";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts = <8 1>;
+				status = "disabled";
+			};
+		};
+
+		/* CM33 <-> CA55 */
+		mbox1: mhu@50400020 {
+			compatible = "renesas,rz-mhu-mbox";
+			channel = <1>;
+			reg = <0x50400020 0x20>;
+			tx-mask = <0x00000002>; /* Channel 1 is for TX */
+			rx-mask = <0x00000001>; /* Channel 0 is for RX */
+			channels-count = <2>;
+			interrupts = <58 2>;
+			interrupt-names = "mhuns";
+			#mbox-cells = <1>;
+			status = "disabled";
+		};
+
+		/* CM33 <-> CM33_FPU */
+		mbox3: mhu@50400060 {
+			compatible = "renesas,rz-mhu-mbox";
+			channel = <3>;
+			reg = <0x50400060 0x20>;
+			tx-mask = <0x00000002>; /* Channel 1 is for TX */
+			rx-mask = <0x00000001>; /* Channel 0 is for RX */
+			channels-count = <2>;
+			interrupts = <59 2>;
+			interrupt-names = "mhuns";
+			#mbox-cells = <1>;
+			status = "disabled";
+		};
+
+		/* CM33 <-> CA55 */
+		mbox4: mhu@50400080 {
+			compatible = "renesas,rz-mhu-mbox";
+			channel = <4>;
+			reg = <0x50400080 0x20>;
+			tx-mask = <0x00000002>; /* Channel 1 is for TX */
+			rx-mask = <0x00000001>; /* Channel 0 is for RX */
+			channels-count = <2>;
+			interrupts = <60 2>;
+			interrupt-names = "mhuns";
+			#mbox-cells = <1>;
+			status = "disabled";
+		};
+
+		/* CM33 <-> CM33_FPU */
+		mbox5: mhu@504000a0 {
+			compatible = "renesas,rz-mhu-mbox";
+			channel = <5>;
+			reg = <0x504000a0 0x20>;
+			tx-mask = <0x00000002>; /* Channel 1 is for TX */
+			rx-mask = <0x00000001>; /* Channel 0 is for RX */
+			channels-count = <2>;
+			interrupts = <61 2>;
+			interrupt-names = "mhuns";
+			#mbox-cells = <1>;
+			status = "disabled";
+		};
 	};
 };
 
diff --git a/dts/arm/renesas/rz/rzn/r9a07g084.dtsi b/dts/arm/renesas/rz/rzn/r9a07g084.dtsi
new file mode 100644
index 00000000000..91330455337
--- /dev/null
+++ b/dts/arm/renesas/rz/rzn/r9a07g084.dtsi
@@ -0,0 +1,592 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-r.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "renesas,r9a07g084";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <0>;
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+	};
+
+	soc {
+		interrupt-parent = <&gic>;
+
+		gic: interrupt-controller@94000000 {
+			compatible = "arm,gic-v3", "arm,gic";
+			reg = <0x94000000 0x10000>,
+				<0x94100000 0x80000>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			status = "okay";
+		};
+
+		atcm: memory@0 {
+			compatible = "mmio-sram";
+			reg = <0x00000000 DT_SIZE_K(128)>;
+		};
+
+		btcm: memory@100000 {
+			compatible = "mmio-sram";
+			reg = <0x00100000 DT_SIZE_K(128)>;
+		};
+
+		sram: memory@10000000 {
+			compatible = "mmio-sram";
+			reg = <0x10000000 (DT_SIZE_M(1) + DT_SIZE_K(512))>;
+		};
+
+		xspi0_cs0: memory@60000000 {
+			compatible = "mmio-sram";
+			reg = <0x60000000 DT_SIZE_M(64)>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				loader_param: partition@0 {
+					label = "loader-param";
+					reg = <0x00000000 0x4C>;
+					read-only;
+				};
+
+				loader_program: partition@4C {
+					label = "loader-program";
+					reg = <0x0000004C (DT_SIZE_K(56) - 0x4C)>;
+					read-only;
+				};
+
+				slot0_partition: partition@E000 {
+					label = "image-0";
+					reg = <0x0000E000 (DT_SIZE_M(64) - DT_SIZE_K(56))>;
+					read-only;
+				};
+			};
+		};
+
+		icu: icu@81048000 {
+			reg = <0x81048000 0x1000>;
+			interrupt-parent = <&gic>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			irq0: irq0@0 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x0>;
+				interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq1: irq@1 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x1>;
+				interrupts = <GIC_SPI 7 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq2: irq@2 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x2>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq3: irq@3 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x3>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq4: irq@4 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x4>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq5: irq@5 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x5>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq6: irq@6 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x6>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq7: irq@7 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x7>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq8: irq@8 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x8>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq9: irq@9 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x9>;
+				interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq10: irq@a {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0xa>;
+				interrupts = <GIC_SPI 16 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq11: irq@b {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0xb>;
+				interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq12: irq@c {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0xc>;
+				interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq13: irq@d {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0xd>;
+				interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq14: irq@e {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0xe>;
+				interrupts = <GIC_SPI 394 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq15: irq@f {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0xf>;
+				interrupts = <GIC_SPI 395 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+		};
+
+		pinctrl: pinctrl@800a0000 {
+			compatible = "renesas,rzn-pinctrl";
+			reg = <0x800a0000 0x1000 0x81030c00 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio0: gpio@0 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				reg = <0x0>;
+				status = "disabled";
+			};
+
+			gpio1: gpio@100 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0100>;
+				status = "disabled";
+			};
+
+			gpio2: gpio@200 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0200>;
+				status = "disabled";
+			};
+
+			gpio3: gpio@300 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				gpio-reserved-ranges = <1 4>;
+				reg = <0x0300>;
+				status = "disabled";
+			};
+
+			gpio4: gpio@400 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				gpio-reserved-ranges = <2 2>;
+				reg = <0x0400>;
+				status = "disabled";
+			};
+
+			gpio5: gpio@500 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0500>;
+				status = "disabled";
+			};
+
+			gpio6: gpio@600 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0600>;
+				status = "disabled";
+			};
+
+			gpio7: gpio@700 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <5>;
+				reg = <0x0700>;
+				status = "disabled";
+			};
+
+			gpio8: gpio@800 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				gpio-reserved-ranges = <0 4>;
+				reg = <0x0800>;
+				status = "disabled";
+			};
+
+			gpio9: gpio@900 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0900>;
+				status = "disabled";
+			};
+
+			gpio10: gpio@a00 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <5>;
+				reg = <0x0a00>;
+				status = "disabled";
+			};
+
+			gpio11: gpio@b00 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <0>;
+				reg = <0x0b00>;
+				status = "disabled";
+			};
+
+			gpio12: gpio@c00 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <5>;
+				gpio-reserved-ranges = <0 4>;
+				reg = <0x0c00>;
+				status = "disabled";
+			};
+
+			gpio13: gpio@d00 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				gpio-reserved-ranges = <0 2>;
+				reg = <0x0d00>;
+				status = "disabled";
+			};
+
+			gpio14: gpio@e00 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0e00>;
+				status = "disabled";
+			};
+
+			gpio15: gpio@f00 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0f00>;
+				status = "disabled";
+			};
+
+			gpio16: gpio@1000 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				gpio-reserved-ranges = <4 1>;
+				reg = <0x1000>;
+				status = "disabled";
+			};
+
+			gpio17: gpio@1100 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				gpio-reserved-ranges = <1 2>;
+				reg = <0x1100>;
+				status = "disabled";
+			};
+
+			gpio18: gpio@1200 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <7>;
+				reg = <0x1200>;
+				status = "disabled";
+			};
+
+			gpio19: gpio@1300 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <1>;
+				reg = <0x1300>;
+				status = "disabled";
+			};
+
+			gpio20: gpio@1400 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <5>;
+				gpio-reserved-ranges = <0 1>;
+				reg = <0x1400>;
+				status = "disabled";
+			};
+
+			gpio21: gpio@1500 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				gpio-reserved-ranges = <0 1>;
+				reg = <0x1500>;
+				status = "disabled";
+			};
+
+			gpio22: gpio@1600 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <4>;
+				reg = <0x1600>;
+				status = "disabled";
+			};
+
+			gpio23: gpio@1700 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				gpio-reserved-ranges = <0 7>;
+				reg = <0x1700>;
+				status = "disabled";
+			};
+
+			gpio24: gpio@1800 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <3>;
+				reg = <0x1800>;
+				status = "disabled";
+			};
+		};
+
+		sci0: sci0@80001000 {
+			compatible = "renesas,rz-sci";
+			reg = <0x80001000 0x400>;
+			channel = <0>;
+			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 289 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 290 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 291 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,rz-sci-uart";
+				current-speed = <115200>;
+				status = "disabled";
+			};
+		};
+
+		sci1: sci1@80001400 {
+			compatible = "renesas,rz-sci";
+			reg = <0x80001400 0x400>;
+			channel = <1>;
+			interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 293 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 294 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 295 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,rz-sci-uart";
+				current-speed = <115200>;
+				status = "disabled";
+			};
+		};
+
+		sci2: sci2@80001800 {
+			compatible = "renesas,rz-sci";
+			reg = <0x80001800 0x400>;
+			channel = <2>;
+			interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 297 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 298 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 299 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,rz-sci-uart";
+				current-speed = <115200>;
+				status = "disabled";
+			};
+		};
+
+		sci3: sci3@80001c00 {
+			compatible = "renesas,rz-sci";
+			reg = <0x80001c00 0x400>;
+			channel = <3>;
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 301 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 302 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 303 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,rz-sci-uart";
+				current-speed = <115200>;
+				status = "disabled";
+			};
+		};
+
+		sci4: sci4@80002000 {
+			compatible = "renesas,rz-sci";
+			reg = <0x80002000 0x400>;
+			channel = <4>;
+			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 305 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 306 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 307 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,rz-sci-uart";
+				current-speed = <115200>;
+				status = "disabled";
+			};
+		};
+
+		sci5: sci5@81001000 {
+			compatible = "renesas,rz-sci";
+			reg = <0x81001000 0x400>;
+			channel = <5>;
+			interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 436 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 437 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 438 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,rz-sci-uart";
+				current-speed = <115200>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/dts/arm/renesas/rz/rzt/r9a07g074.dtsi b/dts/arm/renesas/rz/rzt/r9a07g074.dtsi
new file mode 100644
index 00000000000..33c52551c5f
--- /dev/null
+++ b/dts/arm/renesas/rz/rzt/r9a07g074.dtsi
@@ -0,0 +1,592 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-r.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r9a07g074";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <0>;
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+	};
+
+	soc {
+		interrupt-parent = <&gic>;
+
+		gic: interrupt-controller@94000000 {
+			compatible = "arm,gic-v3", "arm,gic";
+			reg = <0x94000000 0x10000>,
+			       <0x94100000 0x80000>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			status = "okay";
+		};
+
+		atcm: memory@0 {
+			compatible = "mmio-sram";
+			reg = <0x00000000 DT_SIZE_K(512)>;
+		};
+
+		btcm: memory@100000 {
+			compatible = "mmio-sram";
+			reg = <0x00100000 DT_SIZE_K(64)>;
+		};
+
+		sram: memory@10000000 {
+			compatible = "mmio-sram";
+			reg = <0x10000000 DT_SIZE_M(1)>;
+		};
+
+		xspi1_cs0: memory@68000000 {
+			compatible = "mmio-sram";
+			reg = <0x68000000 DT_SIZE_M(16)>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+
+				loader_param: partition@0 {
+					label = "loader-param";
+					reg = <0x00000000 0x4C>;
+					read-only;
+				};
+
+				loader_program: partition@4C {
+					label = "loader-program";
+					reg = <0x0000004C (DT_SIZE_K(56) - 0x4C)>;
+					read-only;
+				};
+
+				slot0_partition: partition@E000 {
+					label = "image-0";
+					reg = <0x0000E000 (DT_SIZE_M(16) - DT_SIZE_K(56))>;
+					read-only;
+				};
+			};
+		};
+
+		icu: icu@81048000 {
+			reg = <0x81048000 0x1000>;
+			interrupt-parent = <&gic>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			irq0: irq0@0 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x0>;
+				interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq1: irq@1 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x1>;
+				interrupts = <GIC_SPI 7 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq2: irq@2 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x2>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq3: irq@3 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x3>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq4: irq@4 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x4>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq5: irq@5 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x5>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq6: irq@6 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x6>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq7: irq@7 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x7>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq8: irq@8 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x8>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq9: irq@9 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x9>;
+				interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq10: irq@a {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0xa>;
+				interrupts = <GIC_SPI 16 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq11: irq@b {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0xb>;
+				interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq12: irq@c {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0xc>;
+				interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq13: irq@d {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0xd>;
+				interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq14: irq@e {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0xe>;
+				interrupts = <GIC_SPI 394 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq15: irq@f {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0xf>;
+				interrupts = <GIC_SPI 395 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+		};
+
+		pinctrl: pinctrl@800a0000 {
+			compatible = "renesas,rzt-pinctrl";
+			reg = <0x800a0000 0x1000 0x81030c00 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio0: gpio@0 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <7>;
+				gpio-reserved-ranges = <4 2>;
+				reg = <0x0>;
+				status = "disabled";
+			};
+
+			gpio1: gpio@100 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				reg = <0x0100>;
+				status = "disabled";
+			};
+
+			gpio2: gpio@200 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				reg = <0x0200>;
+				status = "disabled";
+			};
+
+			gpio3: gpio@300 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <0>;
+				reg = <0x0300>;
+				status = "disabled";
+			};
+
+			gpio4: gpio@400 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <2>;
+				gpio-reserved-ranges = <0 1>;
+				reg = <0x0400>;
+				status = "disabled";
+			};
+
+			gpio5: gpio@500 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				gpio-reserved-ranges = <0 5>;
+				reg = <0x0500>;
+				status = "disabled";
+			};
+
+			gpio6: gpio@600 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				reg = <0x0600>;
+				status = "disabled";
+			};
+
+			gpio7: gpio@700 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <5>;
+				reg = <0x0700>;
+				status = "disabled";
+			};
+
+			gpio8: gpio@800 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				gpio-reserved-ranges = <0 4>;
+				reg = <0x0800>;
+				status = "disabled";
+			};
+
+			gpio9: gpio@900 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				reg = <0x0900>;
+				status = "disabled";
+			};
+
+			gpio10: gpio@a00 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <5>;
+				reg = <0x0a00>;
+				status = "disabled";
+			};
+
+			gpio11: gpio@b00 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <0>;
+				reg = <0x0b00>;
+				status = "disabled";
+			};
+
+			gpio12: gpio@c00 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <0>;
+				reg = <0x0c00>;
+				status = "disabled";
+			};
+
+			gpio13: gpio@d00 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				gpio-reserved-ranges = <0 2>;
+				reg = <0x0d00>;
+				status = "disabled";
+			};
+
+			gpio14: gpio@e00 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				reg = <0x0e00>;
+				status = "disabled";
+			};
+
+			gpio15: gpio@f00 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				reg = <0x0f00>;
+				status = "disabled";
+			};
+
+			gpio16: gpio@1000 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <4>;
+				reg = <0x1000>;
+				status = "disabled";
+			};
+
+			gpio17: gpio@1100 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				gpio-reserved-ranges = <1 2>;
+				reg = <0x1100>;
+				status = "disabled";
+			};
+
+			gpio18: gpio@1200 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <7>;
+				reg = <0x1200>;
+				status = "disabled";
+			};
+
+			gpio19: gpio@1300 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <0>;
+				reg = <0x1300>;
+				status = "disabled";
+			};
+
+			gpio20: gpio@1400 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <5>;
+				gpio-reserved-ranges = <0 3>;
+				reg = <0x1400>;
+				status = "disabled";
+			};
+
+			gpio21: gpio@1500 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				gpio-reserved-ranges = <0 1>;
+				reg = <0x1500>;
+				status = "disabled";
+			};
+
+			gpio22: gpio@1600 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <4>;
+				reg = <0x1600>;
+				status = "disabled";
+			};
+
+			gpio23: gpio@1700 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				gpio-reserved-ranges = <0 7>;
+				reg = <0x1700>;
+				status = "disabled";
+			};
+
+			gpio24: gpio@1800 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <3>;
+				reg = <0x1800>;
+				status = "disabled";
+			};
+		};
+
+		sci0: sci0@80001000 {
+			compatible = "renesas,rz-sci";
+			reg = <0x80001000 0x400>;
+			channel = <0>;
+			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 289 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 290 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 291 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,rz-sci-uart";
+				current-speed = <115200>;
+				status = "disabled";
+			};
+		};
+
+		sci1: sci1@80001400 {
+			compatible = "renesas,rz-sci";
+			reg = <0x80001400 0x400>;
+			channel = <1>;
+			interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 293 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 294 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 295 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,rz-sci-uart";
+				current-speed = <115200>;
+				status = "disabled";
+			};
+		};
+
+		sci2: sci2@80001800 {
+			compatible = "renesas,rz-sci";
+			reg = <0x80001800 0x400>;
+			channel = <2>;
+			interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 297 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 298 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 299 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,rz-sci-uart";
+				current-speed = <115200>;
+				status = "disabled";
+			};
+		};
+
+		sci3: sci3@80001c00 {
+			compatible = "renesas,rz-sci";
+			reg = <0x80001c00 0x400>;
+			channel = <3>;
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 301 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 302 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 303 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,rz-sci-uart";
+				current-speed = <115200>;
+				status = "disabled";
+			};
+		};
+
+		sci4: sci4@80002000 {
+			compatible = "renesas,rz-sci";
+			reg = <0x80002000 0x400>;
+			channel = <4>;
+			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 305 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 306 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 307 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,rz-sci-uart";
+				current-speed = <115200>;
+				status = "disabled";
+			};
+		};
+
+		sci5: sci5@81001000 {
+			compatible = "renesas,rz-sci";
+			reg = <0x81001000 0x400>;
+			channel = <5>;
+			interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 436 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 437 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 438 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,rz-sci-uart";
+				current-speed = <115200>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/dts/arm/renesas/rz/rzt/r9a07g075.dtsi b/dts/arm/renesas/rz/rzt/r9a07g075.dtsi
new file mode 100644
index 00000000000..209238629d0
--- /dev/null
+++ b/dts/arm/renesas/rz/rzt/r9a07g075.dtsi
@@ -0,0 +1,590 @@
+/*
+ * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <arm/armv8-r.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	compatible = "renesas,r9a07g075";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <1>;
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+	};
+
+	soc {
+		interrupt-parent = <&gic>;
+
+		gic: interrupt-controller@94000000 {
+			compatible = "arm,gic-v3", "arm,gic";
+			reg = <0x94000000 0x10000>,
+				<0x94100000 0x80000>;
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			status = "okay";
+		};
+
+		cpu0_atcm: memory@0 {
+			compatible = "mmio-sram";
+			reg = <0x00000000 DT_SIZE_K(512)>;
+		};
+
+		cpu0_btcm: memory@100000 {
+			compatible = "mmio-sram";
+			reg = <0x00100000 DT_SIZE_K(64)>;
+		};
+
+		sram: memory@10000000 {
+			compatible = "mmio-sram";
+			reg = <0x10000000 DT_SIZE_M(2)>;
+		};
+
+		xspi0_cs0: memory@60000000 {
+			compatible = "mmio-sram";
+			reg = <0x60000000 DT_SIZE_M(64)>;
+
+			partitions {
+				compatible = "fixed-partitions";
+				#address-cells = <1>;
+				#size-cells = <1>;
+				loader_param: partition@0 {
+					label = "loader-param";
+					reg = <0x00000000 0x4C>;
+					read-only;
+				};
+
+				loader_program: partition@4C {
+					label = "loader-program";
+					reg = <0x0000004C (DT_SIZE_K(56) - 0x4C)>;
+					read-only;
+				};
+
+				slot0_partition: partition@E000 {
+					label = "image-0";
+					reg = <0x0000E000 (DT_SIZE_M(64) - DT_SIZE_K(56))>;
+					read-only;
+				};
+			};
+		};
+
+		icu: icu@81048000 {
+			reg = <0x81048000 0x1000>;
+			interrupt-parent = <&gic>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			irq0: irq0@0 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x0>;
+				interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq1: irq@1 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x1>;
+				interrupts = <GIC_SPI 7 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq2: irq@2 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x2>;
+				interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq3: irq@3 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x3>;
+				interrupts = <GIC_SPI 9 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq4: irq@4 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x4>;
+				interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq5: irq@5 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x5>;
+				interrupts = <GIC_SPI 11 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq6: irq@6 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x6>;
+				interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq7: irq@7 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x7>;
+				interrupts = <GIC_SPI 13 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq8: irq@8 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x8>;
+				interrupts = <GIC_SPI 14 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq9: irq@9 {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0x9>;
+				interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq10: irq@a {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0xa>;
+				interrupts = <GIC_SPI 16 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq11: irq@b {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0xb>;
+				interrupts = <GIC_SPI 17 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq12: irq@c {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0xc>;
+				interrupts = <GIC_SPI 18 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq13: irq@d {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0xd>;
+				interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq14: irq@e {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0xe>;
+				interrupts = <GIC_SPI 394 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+
+			irq15: irq@f {
+				compatible = "renesas,rz-ext-irq";
+				reg = <0xf>;
+				interrupts = <GIC_SPI 395 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				status = "disabled";
+			};
+		};
+
+		pinctrl: pinctrl@800a0000 {
+			compatible = "renesas,rzt-pinctrl";
+			reg = <0x800a0000 0x1000 0x81030c00 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpio0: gpio@0 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				reg = <0x0>;
+				status = "disabled";
+			};
+
+			gpio1: gpio@100 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0100>;
+				status = "disabled";
+			};
+
+			gpio2: gpio@200 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0200>;
+				status = "disabled";
+			};
+
+			gpio3: gpio@300 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				gpio-reserved-ranges= <1 1>;
+				reg = <0x0300>;
+				status = "disabled";
+			};
+
+			gpio4: gpio@400 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0400>;
+				status = "disabled";
+			};
+
+			gpio5: gpio@500 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0500>;
+				status = "disabled";
+			};
+
+			gpio6: gpio@600 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0600>;
+				status = "disabled";
+			};
+
+			gpio7: gpio@700 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0700>;
+				status = "disabled";
+			};
+
+			gpio8: gpio@800 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0800>;
+				status = "disabled";
+			};
+
+			gpio9: gpio@900 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0900>;
+				status = "disabled";
+			};
+
+			gpio10: gpio@a00 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0a00>;
+				status = "disabled";
+			};
+
+			gpio11: gpio@b00 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0b00>;
+				status = "disabled";
+			};
+
+			gpio12: gpio@c00 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0c00>;
+				status = "disabled";
+			};
+
+			gpio13: gpio@d00 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0d00>;
+				status = "disabled";
+			};
+
+			gpio14: gpio@e00 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0e00>;
+				status = "disabled";
+			};
+
+			gpio15: gpio@f00 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x0f00>;
+				status = "disabled";
+			};
+
+			gpio16: gpio@1000 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x1000>;
+				status = "disabled";
+			};
+
+			gpio17: gpio@1100 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x1100>;
+				status = "disabled";
+			};
+
+			gpio18: gpio@1200 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x1200>;
+				status = "disabled";
+			};
+
+			gpio19: gpio@1300 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x1300>;
+				status = "disabled";
+			};
+
+			gpio20: gpio@1400 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x1400>;
+				status = "disabled";
+			};
+
+			gpio21: gpio@1500 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x1500>;
+				status = "disabled";
+			};
+
+			gpio22: gpio@1600 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x1600>;
+				status = "disabled";
+			};
+
+			gpio23: gpio@1700 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <8>;
+				reg = <0x1700>;
+				status = "disabled";
+			};
+
+			gpio24: gpio@1800 {
+				compatible = "renesas,rz-gpio";
+				gpio-controller;
+				#gpio-cells= <2>;
+				ngpios = <3>;
+				reg = <0x1800>;
+				status = "disabled";
+			};
+		};
+
+		sci0: sci0@80001000 {
+			compatible = "renesas,rz-sci";
+			reg = <0x80001000 0x400>;
+			channel = <0>;
+			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 289 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 290 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 291 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,rz-sci-uart";
+				current-speed = <115200>;
+				status = "disabled";
+			};
+		};
+
+		sci1: sci1@80001400 {
+			compatible = "renesas,rz-sci";
+			reg = <0x80001400 0x400>;
+			channel = <1>;
+			interrupts = <GIC_SPI 292 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 293 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 294 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 295 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,rz-sci-uart";
+				current-speed = <115200>;
+				status = "disabled";
+			};
+		};
+
+		sci2: sci2@80001800 {
+			compatible = "renesas,rz-sci";
+			reg = <0x80001800 0x400>;
+			channel = <2>;
+			interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 297 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 298 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 299 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,rz-sci-uart";
+				current-speed = <115200>;
+				status = "disabled";
+			};
+		};
+
+		sci3: sci3@80001c00 {
+			compatible = "renesas,rz-sci";
+			reg = <0x80001c00 0x400>;
+			channel = <3>;
+			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 301 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 302 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 303 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,rz-sci-uart";
+				current-speed = <115200>;
+				status = "disabled";
+			};
+		};
+
+		sci4: sci4@80002000 {
+			compatible = "renesas,rz-sci";
+			reg = <0x80002000 0x400>;
+			channel = <4>;
+			interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 305 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 306 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 307 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,rz-sci-uart";
+				current-speed = <115200>;
+				status = "disabled";
+			};
+		};
+
+		sci5: sci5@81001000 {
+			compatible = "renesas,rz-sci";
+			reg = <0x81001000 0x400>;
+			channel = <5>;
+			interrupts = <GIC_SPI 435 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 436 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 437 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 438 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "rxi", "txi", "tei";
+			status = "disabled";
+
+			uart {
+				compatible = "renesas,rz-sci-uart";
+				current-speed = <115200>;
+				status = "disabled";
+			};
+		};
+	};
+};
diff --git a/dts/arm/renesas/rz/rzt2m.dtsi b/dts/arm/renesas/rz/rzt2m.dtsi
deleted file mode 100644
index a50cdc7e9b3..00000000000
--- a/dts/arm/renesas/rz/rzt2m.dtsi
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * Copyright (c) 2023 Antmicro <www.antmicro.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <mem.h>
-#include <arm/armv8-r.dtsi>
-#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-	compatible = "renesas,rzt2m-dev";
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu@0 {
-			device_type = "cpu";
-			compatible = "arm,cortex-r52";
-			reg = <0>;
-		};
-
-		cpu@1 {
-			device_type = "cpu";
-			compatible = "arm,cortex-r52";
-			reg = <1>;
-		};
-	};
-
-	arch_timer: timer {
-		compatible = "arm,armv8-timer";
-		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
-				<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
-				<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
-				<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
-		interrupt-parent = <&gic>;
-	};
-
-	soc {
-		compatible = "renesas,rzt2m-soc";
-
-		interrupt-parent = <&gic>;
-
-		gic: interrupt-controller@94000000 {
-			compatible = "arm,gic-v3", "arm,gic";
-			reg = <0x94000000 0x10000>,
-				<0x94100000 0x80000>;
-			interrupt-controller;
-			#interrupt-cells = <4>;
-			status = "okay";
-		};
-
-		cpu0_atcm: memory@0 {
-			compatible = "mmio-sram";
-			reg = <0x00000000 DT_SIZE_K(512)>;
-		};
-
-		cpu0_btcm: memory@100000 {
-			compatible = "mmio-sram";
-			reg = <0x00100000 DT_SIZE_K(64)>;
-		};
-
-		sram0: memory@10000000 {
-			compatible = "mmio-sram";
-			reg = <0x10000000 DT_SIZE_M(2)>;
-		};
-
-		gsc: gsc@c0060000 {
-			/* Global System Counter */
-			compatible = "syscon";
-			reg = <0xc0060000 0x30>;
-			reg-io-width = <4>;
-		};
-
-		prcrn: prcrn@80281a10 {
-			/* Non-safety area */
-			compatible = "syscon";
-			reg = <0x80281a10 0x10>;
-			reg-io-width = <4>;
-		};
-
-		prcrs: prcrs@81281a00 {
-			/* Safety area */
-			compatible = "syscon";
-			reg = <0x81281a00 0x10>;
-			reg-io-width = <4>;
-		};
-
-		sckcr: sckcr@80280000 {
-			/* System Clock Control Register*/
-			compatible = "syscon";
-			reg = <0x80280000 0x20>;
-			reg-io-width = <4>;
-		};
-
-		sckcr2: sckcr2@81280004 {
-			/* System Clock Control Register 2 */
-			compatible = "syscon";
-			reg = <0x81280004 0x1a>;
-			reg-io-width = <4>;
-		};
-
-		ns_portnf_md: ns_portnf_md@8009000c {
-			/* Interrupt edge detection setting */
-			compatible = "syscon";
-			reg = <0x8009000c 0x4>;
-			reg-io-width = <4>;
-		};
-
-		uart0: serial@80001000 {
-			compatible = "renesas,rzt2m-uart";
-			reg = <0x80001000 0x1000>;
-			current-speed = <115200>;
-			interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 289 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 290 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 291 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
-			interrupt-names = "rx_err", "rx", "tx", "tx_end";
-			status = "disabled";
-		};
-
-		uart3: serial@80001c00 {
-			compatible = "renesas,rzt2m-uart";
-			reg = <0x80001c00 0x1000>;
-			current-speed = <115200>;
-			interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 301 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 302 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 303 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
-			interrupt-names = "rx_err", "rx", "tx", "tx_end";
-			status = "disabled";
-		};
-
-		pinctrl: pinctrl@800a0000 {
-			compatible = "renesas,rzt2m-pinctrl";
-			reg = <0x800a0000 0x1000 0x81030c00 0x1000>;
-			reg-names = "port_nsr", "ptadr";
-
-			gpio_common: gpio_common {
-				compatible = "renesas,rzt2m-gpio-common";
-				interrupts = <GIC_SPI 6 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 7 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 8 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 9 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 10 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 11 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 12 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 13 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 14 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 15 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 16 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 17 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 18 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>,
-					<GIC_SPI 19 IRQ_TYPE_EDGE IRQ_DEFAULT_PRIORITY>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-
-				gpio10: gpio@a {
-					compatible = "renesas,rzt2m-gpio";
-					gpio-controller;
-					#gpio-cells = <2>;
-					ngpios = <8>;
-					reg = <0xa>;
-					irqs = <4 11>, <5 2>;
-				};
-
-				gpio16: gpio@10 {
-					compatible = "renesas,rzt2m-gpio";
-					gpio-controller;
-					#gpio-cells = <2>;
-					ngpios = <8>;
-					reg = <0x10>;
-					irqs = <3 7>, <6 8>;
-				};
-
-				gpio19: gpio@13 {
-					compatible = "renesas,rzt2m-gpio";
-					gpio-controller;
-					#gpio-cells = <2>;
-					ngpios = <8>;
-					reg = <0x13>;
-					irqs = <2 3>;
-				};
-
-				gpio20: gpio@14 {
-					compatible = "renesas,rzt2m-gpio";
-					gpio-controller;
-					#gpio-cells = <2>;
-					ngpios = <8>;
-					reg = <0x14>;
-				};
-
-				gpio23: gpio@17 {
-					compatible = "renesas,rzt2m-gpio";
-					gpio-controller;
-					#gpio-cells = <2>;
-					ngpios = <8>;
-					reg = <0x17>;
-					irqs = <0 5>, <2 8>;
-				};
-
-			};
-		};
-	};
-};
diff --git a/dts/arm/renesas/rz/rzv/r9a07g054.dtsi b/dts/arm/renesas/rz/rzv/r9a07g054.dtsi
new file mode 100644
index 00000000000..fc98bcf74f8
--- /dev/null
+++ b/dts/arm/renesas/rz/rzv/r9a07g054.dtsi
@@ -0,0 +1,547 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv8-m.dtsi>
+#include <mem.h>
+#include <freq.h>
+
+/ {
+	compatible = "renesas,r9a07g054";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m33";
+			reg = <0>;
+			clock-frequency = <DT_FREQ_M(200)>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	soc {
+		pinctrl: pin-controller@41030000 {
+			compatible = "renesas,rzv-pinctrl";
+			reg = <0x41030000 DT_SIZE_K(64)>;
+			reg-names = "pinctrl";
+
+			gpio: gpio-common {
+				compatible = "renesas,rz-gpio-int";
+				interrupts =
+					<444 10>, <445 10>, <446 10>, <447 10>,
+					<448 10>, <449 10>, <450 10>, <451 10>,
+					<452 10>, <453 10>, <454 10>, <455 10>,
+					<456 10>, <457 10>, <458 10>, <459 10>,
+					<460 10>, <461 10>, <462 10>, <463 10>,
+					<464 10>, <465 10>, <466 10>, <467 10>,
+					<468 10>, <469 10>, <470 10>, <471 10>,
+					<472 10>, <473 10>, <474 10>, <475 10>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+
+				gpio0: gpio@0 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x0>;
+					status = "disabled";
+				};
+
+				gpio1: gpio@100 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x100>;
+					status = "disabled";
+				};
+
+				gpio2: gpio@200 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x200>;
+					status = "disabled";
+				};
+
+				gpio3: gpio@300 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x300>;
+					status = "disabled";
+				};
+
+				gpio4: gpio@400 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x400>;
+					status = "disabled";
+				};
+
+				gpio5: gpio@500 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <3>;
+					reg = <0x500>;
+					status = "disabled";
+				};
+
+				gpio6: gpio@600 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x600>;
+					status = "disabled";
+				};
+
+				gpio7: gpio@700 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <3>;
+					reg = <0x700>;
+					status = "disabled";
+				};
+
+				gpio8: gpio@800 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <3>;
+					reg = <0x800>;
+					status = "disabled";
+				};
+
+				gpio9: gpio@900 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x900>;
+					status = "disabled";
+				};
+
+				gpio10: gpio@a00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0xa00>;
+					status = "disabled";
+				};
+
+				gpio11: gpio@b00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0xb00>;
+					status = "disabled";
+				};
+
+				gpio12: gpio@c00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0xc00>;
+					status = "disabled";
+				};
+
+				gpio13: gpio@d00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <3>;
+					reg = <0xd00>;
+					status = "disabled";
+				};
+
+				gpio14: gpio@e00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0xe00>;
+					status = "disabled";
+				};
+
+				gpio15: gpio@f00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0xf00>;
+					status = "disabled";
+				};
+
+				gpio16: gpio@1000 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x1000>;
+					status = "disabled";
+				};
+
+				gpio17: gpio@1100 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <3>;
+					reg = <0x1100>;
+					status = "disabled";
+				};
+
+				gpio18: gpio@1200 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x1200>;
+					status = "disabled";
+				};
+
+				gpio19: gpio@1300 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x1300>;
+					status = "disabled";
+				};
+
+				gpio20: gpio@1400 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <3>;
+					reg = <0x1400>;
+					status = "disabled";
+				};
+
+				gpio21: gpio@1500 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x1500>;
+					status = "disabled";
+				};
+
+				gpio22: gpio@1600 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x1600>;
+					status = "disabled";
+				};
+
+				gpio23: gpio@1700 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x1700>;
+					status = "disabled";
+				};
+
+				gpio24: gpio@1800 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x1800>;
+					status = "disabled";
+				};
+
+				gpio25: gpio@1900 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x1900>;
+					status = "disabled";
+				};
+
+				gpio26: gpio@1a00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x1a00>;
+					status = "disabled";
+				};
+
+				gpio27: gpio@1b00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x1b00>;
+					status = "disabled";
+				};
+
+				gpio28: gpio@1c00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x1c00>;
+					status = "disabled";
+				};
+
+				gpio29: gpio@1d00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x1d00>;
+					status = "disabled";
+				};
+
+				gpio30: gpio@1e00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x1e00>;
+					status = "disabled";
+				};
+
+				gpio31: gpio@1f00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x1f00>;
+					status = "disabled";
+				};
+
+				gpio32: gpio@2000 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x2000>;
+					status = "disabled";
+				};
+
+				gpio33: gpio@2100 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x2100>;
+					status = "disabled";
+				};
+
+				gpio34: gpio@2200 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x2200>;
+					status = "disabled";
+				};
+
+				gpio35: gpio@2300 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x2300>;
+					status = "disabled";
+				};
+
+				gpio36: gpio@2400 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x2400>;
+					status = "disabled";
+				};
+
+				gpio37: gpio@2500 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <3>;
+					reg = <0x2500>;
+					status = "disabled";
+				};
+
+				gpio38: gpio@2600 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x2600>;
+					status = "disabled";
+				};
+
+				gpio39: gpio@2700 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <3>;
+					reg = <0x2700>;
+					status = "disabled";
+				};
+
+				gpio40: gpio@2800 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <3>;
+					reg = <0x2800>;
+					status = "disabled";
+				};
+
+				gpio41: gpio@2900 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <2>;
+					reg = <0x2900>;
+					status = "disabled";
+				};
+
+				gpio42: gpio@2a00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <5>;
+					reg = <0x2a00>;
+					status = "disabled";
+				};
+
+				gpio43: gpio@2b00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <4>;
+					reg = <0x2b00>;
+					status = "disabled";
+				};
+
+				gpio44: gpio@2c00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <4>;
+					reg = <0x2c00>;
+					status = "disabled";
+				};
+
+				gpio45: gpio@2d00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <4>;
+					reg = <0x2d00>;
+					status = "disabled";
+				};
+
+				gpio46: gpio@2e00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <4>;
+					reg = <0x2e00>;
+					status = "disabled";
+				};
+
+				gpio47: gpio@2f00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <4>;
+					reg = <0x2f00>;
+					status = "disabled";
+				};
+
+				gpio48: gpio@3000 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <5>;
+					reg = <0x3000>;
+					status = "disabled";
+				};
+			};
+		};
+
+		scif0: serial@4004b800 {
+			compatible = "renesas,rz-scif-uart";
+			channel = <0>;
+			reg = <0x4004b800 0x18>;
+			interrupts = <380 1>, <381 1>, <382 1>, <383 1>, <384 1>;
+			interrupt-names = "eri", "bri", "rxi", "txi", "tei";
+			status = "disabled";
+		};
+
+		scif1: serial@4004bc00 {
+			compatible = "renesas,rz-scif-uart";
+			channel = <1>;
+			reg = <0x4004bc00 0x18>;
+			interrupts = <385 1>, <386 1>, <387 1>, <388 1>, <389 1>;
+			interrupt-names = "eri", "bri", "rxi", "txi", "tei";
+			status = "disabled";
+		};
+
+		scif2: serial@4004c000 {
+			compatible = "renesas,rz-scif-uart";
+			channel = <2>;
+			reg = <0x4004c000 0x18>;
+			interrupts = <390 1>, <391 1>, <392 1>, <393 1>, <394 1>;
+			interrupt-names = "eri", "bri", "rxi", "txi", "tei";
+			status = "disabled";
+		};
+
+		scif3: serial@4004c400 {
+			compatible = "renesas,rz-scif-uart";
+			channel = <3>;
+			reg = <0x4004c400 0x18>;
+			interrupts = <395 1>, <396 1>, <397 1>, <398 1>, <399 1>;
+			interrupt-names = "eri", "bri", "rxi", "txi", "tei";
+			status = "disabled";
+		};
+
+		scif4: serial@4004c800 {
+			compatible = "renesas,rz-scif-uart";
+			channel = <4>;
+			reg = <0x4004c800 0x18>;
+			interrupts = <400 1>, <401 1>, <402 1>, <403 1>, <404 1>;
+			interrupt-names = "eri", "bri", "rxi", "txi", "tei";
+			status = "disabled";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <7>;
+};
diff --git a/dts/arm/renesas/smartbond/da14697.dtsi b/dts/arm/renesas/smartbond/da14697.dtsi
new file mode 100644
index 00000000000..3b362194ee0
--- /dev/null
+++ b/dts/arm/renesas/smartbond/da14697.dtsi
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include "da1469x.dtsi"
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(512)>;
+};
diff --git a/dts/arm/silabs/efr32bg22.dtsi b/dts/arm/silabs/efr32bg22.dtsi
index 9d0bd14c6b9..0bbd09491bf 100644
--- a/dts/arm/silabs/efr32bg22.dtsi
+++ b/dts/arm/silabs/efr32bg22.dtsi
@@ -6,6 +6,7 @@
 
 #include "efr32bg2x.dtsi"
 #include <dt-bindings/clock/silabs/xg22-clock.h>
+#include <dt-bindings/dma/silabs/xg22-dma.h>
 #include <mem.h>
 
 / {
@@ -28,7 +29,7 @@
 };
 
 &cmu {
-	interrupts = <46 0>;
+	interrupts = <46 2>;
 };
 
 &hfxo {
@@ -50,8 +51,41 @@
 };
 
 &gpio {
-	interrupts = <10 2 18 2>;
+	interrupts = <25 2>, <26 2>;
+	interrupt-names = "gpio_odd", "gpio_even";
 	clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>;
+
+	gpioa: gpio@5003c000 {
+		compatible = "silabs,gecko-gpio-port";
+		reg = <0x5003C000 0x30>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		status = "disabled";
+	};
+
+	gpiob: gpio@5003c030 {
+		compatible = "silabs,gecko-gpio-port";
+		reg = <0x5003C030 0x30>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		status = "disabled";
+	};
+
+	gpioc: gpio@5003c060 {
+		compatible = "silabs,gecko-gpio-port";
+		reg = <0x5003C060 0x30>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		status = "disabled";
+	};
+
+	gpiod: gpio@5003c090 {
+		compatible = "silabs,gecko-gpio-port";
+		reg = <0x5003C090 0x30>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		status = "disabled";
+	};
 };
 
 &dma0 {
@@ -59,36 +93,54 @@
 };
 
 &i2c0 {
-	interrupts = <27 0>;
+	interrupts = <27 2>;
 	clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
 };
 
 &i2c1 {
-	interrupts = <28 0>;
+	interrupts = <28 2>;
 	clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>;
 };
 
 &usart0 {
-	interrupts = <13 0>, <14 0>;
+	interrupts = <13 2>, <14 2>;
 	clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
 };
 
 &usart1 {
-	interrupts = <15 0>, <16 0>;
+	interrupts = <15 2>, <16 2>;
 	clocks = <&cmu CLOCK_USART1 CLOCK_BRANCH_PCLK>;
 };
 
 &burtc0 {
-	interrupts = <18 0>;
+	interrupts = <18 2>;
 	clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
 };
 
 &rtcc0 {
-	interrupts = <12 0>;
+	interrupts = <12 2>;
 	interrupt-names = "rtcc";
 	clocks = <&cmu CLOCK_RTCC CLOCK_BRANCH_RTCCCLK>;
 };
 
 &dcdc {
-	interrupts = <61 0>;
+	interrupts = <61 2>;
+};
+
+&adc0 {
+	interrupts = <48 2>;
+	clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>;
+};
+
+&wdog0 {
+	interrupts = <43 2>;
+	clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>;
+};
+
+&radio {
+	interrupts = <31 1>, <32 1>, <33 1>, <34 1>, <35 1>, <36 1>,
+		     <37 1>, <38 1>, <39 1>, <40 1>, <41 1>, <42 1>;
+	interrupt-names = "agc", "bufc", "frc_pri", "frc", "modem", "protimer",
+		     "rac_rsm", "rac_seq", "rdmailbox", "rfsense", "prortc",
+		     "synth";
 };
diff --git a/dts/arm/silabs/efr32bg27.dtsi b/dts/arm/silabs/efr32bg27.dtsi
index 1a39b55a975..ec7546459b5 100644
--- a/dts/arm/silabs/efr32bg27.dtsi
+++ b/dts/arm/silabs/efr32bg27.dtsi
@@ -6,6 +6,7 @@
 
 #include "efr32bg2x.dtsi"
 #include <dt-bindings/clock/silabs/xg27-clock.h>
+#include <dt-bindings/dma/silabs/xg27-dma.h>
 #include <mem.h>
 
 / {
@@ -34,15 +35,22 @@
 			reg = <0x5003c460 0x4>;
 			clock-frequency = <DT_FREQ_M(38)>;
 		};
+		acmp0: acmp@5a008000 {
+			compatible = "silabs,acmp";
+			reg = <0x5a008000 0x4000>;
+			interrupts = <48 2>;
+			clocks = <&cmu CLOCK_ACMP0 CLOCK_BRANCH_EM01GRPACLK>;
+			status = "disabled";
+		};
 	};
 };
 
 &cmu {
-	interrupts = <52 0>;
+	interrupts = <52 2>;
 };
 
 &hfxo {
-	interrupts = <50 0>;
+	interrupts = <50 2>;
 	interrupt-names = "hfxo";
 };
 
@@ -60,50 +68,96 @@
 };
 
 &gpio {
-	interrupts = <30 2 31 2>;
+	interrupts = <30 2>, <31 2>;
+	interrupt-names = "gpio_odd", "gpio_even";
 	clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>;
+
+	gpioa: gpio@5003c030 {
+		compatible = "silabs,gecko-gpio-port";
+		reg = <0x5003C030 0x30>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		status = "disabled";
+	};
+
+	gpiob: gpio@5003c060 {
+		compatible = "silabs,gecko-gpio-port";
+		reg = <0x5003C060 0x30>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		status = "disabled";
+	};
+
+	gpioc: gpio@5003c090 {
+		compatible = "silabs,gecko-gpio-port";
+		reg = <0x5003C090 0x30>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		status = "disabled";
+	};
+
+	gpiod: gpio@5003c0c0 {
+		compatible = "silabs,gecko-gpio-port";
+		reg = <0x5003C0C0 0x30>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		status = "disabled";
+	};
 };
 
 &i2c0 {
-	interrupts = <32 0>;
+	interrupts = <32 2>;
 	clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
 };
 
 &i2c1 {
-	interrupts = <33 0>;
+	interrupts = <33 2>;
 	clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>;
 };
 
 &usart0 {
-	interrupts = <16 0>, <17 0>;
+	interrupts = <16 2>, <17 2>;
 	clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
 };
 
 &usart1 {
-	interrupts = <18 0>, <19 0>;
+	interrupts = <18 2>, <19 2>;
 	clocks = <&cmu CLOCK_USART1 CLOCK_BRANCH_PCLK>;
 };
 
 &burtc0 {
-	interrupts = <23 0>;
+	interrupts = <23 2>;
 	clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
 };
 
 &rtcc0 {
-	interrupts = <15 0>;
+	interrupts = <15 2>;
 	interrupt-names = "rtcc";
 	clocks = <&cmu CLOCK_RTCC CLOCK_BRANCH_RTCCCLK>;
 };
 
 &adc0 {
-	interrupts = <54 0>;
+	interrupts = <54 2>;
 	clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>;
 };
 
 &dcdc {
-	interrupts = <8 0>;
+	interrupts = <8 2>;
 };
 
 &dma0 {
 	interrupts = <26 0>;
 };
+
+&wdog0 {
+	interrupts = <49 2>;
+	clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>;
+};
+
+&radio {
+	interrupts = <36 1>, <37 1>, <38 1>, <39 1>, <40 1>, <41 1>,
+		     <42 1>, <43 1>, <44 1>, <45 1>, <46 1>, <47 1>;
+	interrupt-names = "agc", "bufc", "frc_pri", "frc", "modem", "protimer",
+		     "rac_rsm", "rac_seq", "rdmailbox", "rfsense", "synth",
+		     "prortc";
+};
diff --git a/dts/arm/silabs/efr32bg2x.dtsi b/dts/arm/silabs/efr32bg2x.dtsi
index fb88bb9555f..300adc8fffd 100644
--- a/dts/arm/silabs/efr32bg2x.dtsi
+++ b/dts/arm/silabs/efr32bg2x.dtsi
@@ -118,8 +118,18 @@
 			 * Using BURTC as sys_clock instead of SysTick
 			 * has implications on system performance. Read
 			 * KConfig documentation entry before enabling it.
+			 *
+			 * The minimum residency and exit latency is
+			 * managed by sl_power_manager on S2 devices.
 			 */
 			cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em3>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			itm: itm@e0000000 {
+				compatible = "arm,armv8m-itm";
+				reg = <0xe0000000 0x1000>;
+			};
 		};
 
 		power-states {
@@ -130,9 +140,7 @@
 			pstate_em1: em1 {
 				compatible = "zephyr,power-state";
 				power-state-name = "runtime-idle";
-				min-residency-us = <4>;
 				/* HFXO remains active */
-				exit-latency-us = <2>;
 			};
 
 			/*
@@ -142,8 +150,6 @@
 			pstate_em2: em2 {
 				compatible = "zephyr,power-state";
 				power-state-name = "suspend-to-idle";
-				min-residency-us = <260>;
-				exit-latency-us = <250>;
 			};
 
 			/*
@@ -155,8 +161,6 @@
 			pstate_em3: em3 {
 				compatible = "zephyr,power-state";
 				power-state-name = "standby";
-				min-residency-us = <20000>;
-				exit-latency-us = <2000>;
 			};
 		};
 	};
@@ -224,16 +228,16 @@
 		};
 
 		msc: flash-controller@50030000 {
-			compatible = "silabs,gecko-flash-controller";
+			compatible = "silabs,series2-flash-controller";
 			reg = <0x50030000 0xC69>;
-			interrupts = <49 0>;
+			interrupts = <49 2>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
 		};
 
 		usart0: usart@5005c000 {
-			compatible = "silabs,gecko-spi-usart";
+			compatible = "silabs,usart-spi";
 			reg = <0x5005C000 0x400>;
 			interrupt-names = "rx", "tx";
 			#address-cells = <1>;
@@ -242,7 +246,7 @@
 		};
 
 		usart1: usart@50060000 {
-			compatible = "silabs,gecko-usart";
+			compatible = "silabs,usart-uart";
 			reg = <0x50060000 0x400>;
 			interrupt-names = "rx", "tx";
 			status = "disabled";
@@ -266,7 +270,7 @@
 			compatible = "silabs,gecko-trng";
 			reg = <0x4C021000 0x1000>;
 			status = "disabled";
-			interrupts = <0x1 0x0>;
+			interrupts = <0x1 0x2>;
 		};
 
 		i2c0: i2c@5a010000 {
@@ -290,64 +294,22 @@
 		gpio: gpio@5003c000 {
 			compatible = "silabs,gecko-gpio";
 			reg = <0x5003C000 0x440>;
-			interrupt-names = "GPIO_EVEN", "GPIO_ODD";
-
 			ranges;
 			#address-cells = <1>;
 			#size-cells = <1>;
-
-			gpioa: gpio@5003c000 {
-				compatible = "silabs,gecko-gpio-port";
-				reg = <0x5003C000 0x30>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				status = "disabled";
-			};
-
-			gpiob: gpio@5003c030 {
-				compatible = "silabs,gecko-gpio-port";
-				reg = <0x5003C030 0x30>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				status = "disabled";
-			};
-
-			gpioc: gpio@5003c060 {
-				compatible = "silabs,gecko-gpio-port";
-				reg = <0x5003C060 0x30>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				status = "disabled";
-			};
-
-			gpiod: gpio@5003c090 {
-				compatible = "silabs,gecko-gpio-port";
-				reg = <0x5003C090 0x30>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				status = "disabled";
-			};
-
-			gpiof: gpio@5003c0c0 {
-				compatible = "silabs,gecko-gpio-port";
-				reg = <0x5003C0C0 0x30>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				status = "disabled";
-			};
-
 		};
 
 		pinctrl: pin-controller@5003c440 {
 			compatible = "silabs,dbus-pinctrl";
-			reg = <0x5003c440 0xbc0>;
+			reg = <0x5003c440 0xbc0>, <0x5003c320 0x40>;
+			reg-names = "dbus", "abus";
 		};
 
 		dma0: dma@40040000{
 			compatible = "silabs,ldma";
 			reg = <0x40040000 0x4000>;
-			#dma-cells = <3>;
-			dma_channels = <8>;
+			#dma-cells = <1>;
+			dma-channels = <8>;
 			status = "disabled";
 		};
 
@@ -355,14 +317,12 @@
 			compatible = "silabs,gecko-wdog";
 			reg = <0x4A018000 0x3028>;
 			peripheral-id = <0>;
-			interrupts = <43 0>;
 			status = "disabled";
 		};
 
 		adc0: adc@5a004000 {
 			compatible = "silabs,gecko-iadc";
 			reg = <0x5a004000 0x4000>;
-			interrupts = <48 0>;
 			status = "disabled";
 			#io-channel-cells = <1>;
 		};
@@ -372,11 +332,20 @@
 			reg = <0x50094000 0x4000>;
 			status = "disabled";
 		};
-	};
 
-	bt_hci_silabs: bt_hci_silabs {
-		compatible = "silabs,bt-hci-efr32";
-		status = "disabled";
+		radio: radio@b0000000 {
+			compatible = "silabs,series2-radio";
+			reg = <0xb0000000 0x1000000>;
+			pa-initial-power-dbm = <10>;
+			pa-ramp-time-us = <2>;
+			pa-voltage-mv = <3300>;
+			pa-2p4ghz = "highest";
+
+			bt_hci_silabs: bt_hci_silabs {
+				compatible = "silabs,bt-hci-efr32";
+				status = "disabled";
+			};
+		};
 	};
 };
 
diff --git a/dts/arm/silabs/efr32mg21.dtsi b/dts/arm/silabs/efr32mg21.dtsi
index 925969d7dfc..03d9be44694 100644
--- a/dts/arm/silabs/efr32mg21.dtsi
+++ b/dts/arm/silabs/efr32mg21.dtsi
@@ -9,6 +9,7 @@
 #include <zephyr/dt-bindings/gpio/gpio.h>
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <dt-bindings/clock/silabs/xg21-clock.h>
+#include <dt-bindings/dma/silabs/xg21-dma.h>
 #include <freq.h>
 
 / {
@@ -108,6 +109,11 @@
 				compatible = "arm,armv8m-mpu";
 				reg = <0xe000ed90 0x40>;
 			};
+
+			itm: itm@e0000000 {
+				compatible = "arm,armv8m-itm";
+				reg = <0xe0000000 0x1000>;
+			};
 		};
 	};
 
@@ -120,7 +126,7 @@
 		cmu: clock@50008000 {
 			compatible = "silabs,series-clock";
 			reg = <0x50008000 0x4000>;
-			interrupts = <48 0>;
+			interrupts = <48 2>;
 			interrupt-names = "cmu";
 			status = "okay";
 			#clock-cells = <2>;
@@ -191,7 +197,7 @@
 		};
 
 		msc: flash-controller@50030000 {
-			compatible = "silabs,gecko-flash-controller";
+			compatible = "silabs,series2-flash-controller";
 			reg = <0x50030000 0x31a4>;
 			interrupts = <51 0>;
 
@@ -206,31 +212,28 @@
 		};
 
 		usart0: usart@50058000 { /* USART0 */
-			compatible = "silabs,gecko-usart";
+			compatible = "silabs,usart-uart";
 			reg = <0x50058000 0x400>;
 			interrupts = <11 0>, <12 0>;
 			interrupt-names = "rx", "tx";
-			peripheral-id = <0>;
 			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>;
 			status = "disabled";
 		};
 
 		usart1: usart@5005c000 { /* USART1 */
-			compatible = "silabs,gecko-usart";
+			compatible = "silabs,usart-uart";
 			reg = <0x5005c000 0x400>;
-			interrupts = <13 0>, <14 0>;
+			interrupts = <13 2>, <14 2>;
 			interrupt-names = "rx", "tx";
-			peripheral-id = <1>;
 			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>;
 			status = "disabled";
 		};
 
 		usart2: usart@50060000 { /* USART2 */
-			compatible = "silabs,gecko-usart";
+			compatible = "silabs,usart-uart";
 			reg = <0x50060000 0x400>;
-			interrupts = <15 0>, <16 0>;
+			interrupts = <15 2>, <16 2>;
 			interrupt-names = "rx", "tx";
-			peripheral-id = <2>;
 			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>;
 			status = "disabled";
 		};
@@ -241,7 +244,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x5a010000 0x400>;
-			interrupts = <27 0>;
+			interrupts = <27 2>;
 			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_LSPCLK>;
 			status = "disabled";
 		};
@@ -252,7 +255,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x50068000 0x400>;
-			interrupts = <28 0>;
+			interrupts = <28 2>;
 			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_PCLK>;
 			status = "disabled";
 		};
@@ -260,7 +263,7 @@
 		rtcc0: rtcc@58000000 {
 			compatible = "silabs,gecko-stimer";
 			reg = <0x58000000 0x400>;
-			interrupts = <10 0>;
+			interrupts = <10 2>;
 			interrupt-names = "rtcc";
 			clock-frequency = <32768>;
 			prescaler = <1>;
@@ -318,7 +321,8 @@
 
 		pinctrl: pin-controller@5003c440 {
 			compatible = "silabs,dbus-pinctrl";
-			reg = <0x5003c440 0xbc0>;
+			reg = <0x5003c440 0xbc0>, <0x5003c320 0x40>;
+			reg-names = "dbus", "abus";
 		};
 
 		se: semailbox@5c000000 {
@@ -333,8 +337,8 @@
 			compatible = "silabs,ldma";
 			reg = <0x40040000 0x4000>;
 			interrupts = <21 0>;
-			#dma-cells = <3>;
-			dma_channels = <8>;
+			#dma-cells = <1>;
+			dma-channels = <8>;
 			status = "disabled";
 		};
 
@@ -342,7 +346,7 @@
 			compatible = "silabs,gecko-wdog";
 			reg = <0x5a018000 0x2C>;
 			peripheral-id = <0>;
-			interrupts = <43 0>;
+			interrupts = <43 2>;
 			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_WDOG0CLK>;
 			status = "disabled";
 		};
@@ -351,10 +355,31 @@
 			compatible = "silabs,gecko-wdog";
 			reg = <0x5a01c000 0x2C>;
 			peripheral-id = <1>;
-			interrupts = <44 0>;
+			interrupts = <44 2>;
 			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_WDOG1CLK>;
 			status = "disabled";
 		};
+
+		acmp0: acmp@5a008000 {
+			compatible = "silabs,acmp";
+			reg = <0x5a008000 0x4000>;
+			interrupts = <41 0>;
+			clocks = <&cmu CLOCK_AUTO CLOCK_BRANCH_EM01GRPACLK>;
+			status = "disabled";
+		};
+
+		radio: radio@b0000000 {
+			compatible = "silabs,series2-radio";
+			reg = <0xb0000000 0x1000000>;
+			interrupts = <31 1>, <32 1>, <33 1>, <34 1>, <35 1>, <36 1>,
+				     <37 1>, <38 1>, <39 1>, <40 1>;
+			interrupt-names = "agc", "bufc", "frc_pri", "frc", "modem", "protimer",
+					  "rac_rsm", "rac_seq", "prortc", "synth";
+			pa-initial-power-dbm = <10>;
+			pa-ramp-time-us = <10>;
+			pa-voltage-mv = <3300>;
+			pa-2p4ghz = "highest";
+		};
 	};
 };
 
diff --git a/dts/arm/silabs/efr32mg24.dtsi b/dts/arm/silabs/efr32mg24.dtsi
index cffa3d7b1d3..0f233403477 100644
--- a/dts/arm/silabs/efr32mg24.dtsi
+++ b/dts/arm/silabs/efr32mg24.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/i2c/i2c.h>
 #include <dt-bindings/adc/adc.h>
 #include <dt-bindings/clock/silabs/xg24-clock.h>
+#include <dt-bindings/dma/silabs/xg24-dma.h>
 #include <freq.h>
 
 / {
@@ -139,6 +140,17 @@
 			compatible = "arm,cortex-m33";
 			reg = <0>;
 			cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em3>;
+			/*
+			 * The minimum residency and exit latency is
+			 * managed by sl_power_manager on S2 devices.
+			 */
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			itm: itm@e0000000 {
+				compatible = "arm,armv8m-itm";
+				reg = <0xe0000000 0x1000>;
+			};
 		};
 
 		power-states {
@@ -149,9 +161,7 @@
 			pstate_em1: em1 {
 				compatible = "zephyr,power-state";
 				power-state-name = "runtime-idle";
-				min-residency-us = <4>;
 				/* HFXO remains active */
-				exit-latency-us = <2>;
 			};
 
 			/*
@@ -161,8 +171,6 @@
 			pstate_em2: em2 {
 				compatible = "zephyr,power-state";
 				power-state-name = "suspend-to-idle";
-				min-residency-us = <260>;
-				exit-latency-us = <250>;
 			};
 
 			/*
@@ -174,8 +182,6 @@
 			pstate_em3: em3 {
 				compatible = "zephyr,power-state";
 				power-state-name = "standby";
-				min-residency-us = <20000>;
-				exit-latency-us = <2000>;
 			};
 		};
 	};
@@ -189,7 +195,7 @@
 		cmu: clock@50008000 {
 			compatible = "silabs,series-clock";
 			reg = <0x50008000 0x4000>;
-			interrupts = <47 0>;
+			interrupts = <47 2>;
 			interrupt-names = "cmu";
 			status = "okay";
 			#clock-cells = <2>;
@@ -261,9 +267,9 @@
 		};
 
 		msc: flash-controller@50030000 {
-			compatible = "silabs,gecko-flash-controller";
+			compatible = "silabs,series2-flash-controller";
 			reg = <0x50030000 0x3148>;
-			interrupts = <50 0>;
+			interrupts = <50 2>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -276,28 +282,27 @@
 		};
 
 		usart0: usart@5005c000 {
-			compatible = "silabs,gecko-usart";
+			compatible = "silabs,usart-uart";
 			reg = <0x5005C000 0x306c>;
-			interrupts = <9 0>, <10 0>;
+			interrupts = <9 2>, <10 2>;
 			interrupt-names = "rx", "tx";
-			peripheral-id = <0>;
 			clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
 			status = "disabled";
 		};
 
 		eusart0: eusart@5b010000 {
-			compatible = "silabs,gecko-spi-eusart";
+			compatible = "silabs,eusart-spi";
 			reg = <0x5B010000 0x4000>;
-			interrupts = <11 0>, <12 0>;
+			interrupts = <11 2>, <12 2>;
 			interrupt-names = "rx", "tx";
 			clocks = <&cmu CLOCK_EUSART0 CLOCK_BRANCH_EUSART0CLK>;
 			status = "disabled";
 		};
 
 		eusart1: eusart@500a0000 {
-			compatible = "silabs,gecko-spi-eusart";
+			compatible = "silabs,eusart-spi";
 			reg = <0x500A0000 0x4000>;
-			interrupts = <13 0>, <14 0>;
+			interrupts = <13 2>, <14 2>;
 			interrupt-names = "rx", "tx";
 			clocks = <&cmu CLOCK_EUSART1 CLOCK_BRANCH_EM01GRPCCLK>;
 			status = "disabled";
@@ -306,7 +311,7 @@
 		burtc0: burtc@50064000 {
 			compatible = "silabs,gecko-burtc";
 			reg = <0x50064000 0x3034>;
-			interrupts = <17 0>;
+			interrupts = <17 2>;
 			clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
 			status = "disabled";
 		};
@@ -325,7 +330,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x5b000000 0x3044>;
-			interrupts = <27 0>;
+			interrupts = <27 2>;
 			clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
 			status = "disabled";
 		};
@@ -333,7 +338,7 @@
 		sysrtc0: stimer0: sysrtc@500a8000 {
 			compatible = "silabs,gecko-stimer";
 			reg = <0x500a8000 0x3054>;
-			interrupts = <67 0>, <68 0>;
+			interrupts = <67 2>, <68 2>;
 			interrupt-names = "sysrtc_app", "sysrtc_seq";
 			clock-frequency = <32768>;
 			prescaler = <1>;
@@ -391,15 +396,16 @@
 
 		pinctrl: pin-controller@5003c440 {
 			compatible = "silabs,dbus-pinctrl";
-			reg = <0x5003c440 0xbc0>;
+			reg = <0x5003c440 0xbc0>, <0x5003c320 0x40>;
+			reg-names = "dbus", "abus";
 		};
 
 		dma0: dma@40040000 {
 			compatible = "silabs,ldma";
 			reg = <0x40040000 0x4000>;
 			interrupts = <21 0>;
-			#dma-cells = <3>;
-			dma_channels = <8>;
+			#dma-cells = <1>;
+			dma-channels = <8>;
 			status = "disabled";
 		};
 
@@ -407,7 +413,7 @@
 			compatible = "silabs,gecko-wdog";
 			reg = <0x5b004000 0x2C>;
 			peripheral-id = <0>;
-			interrupts = <42 0>;
+			interrupts = <42 2>;
 			clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>;
 			status = "disabled";
 		};
@@ -416,7 +422,7 @@
 			compatible = "silabs,gecko-wdog";
 			reg = <0x5b008000 0x2C>;
 			peripheral-id = <1>;
-			interrupts = <43 0>;
+			interrupts = <43 2>;
 			clocks = <&cmu CLOCK_WDOG1 CLOCK_BRANCH_WDOG1CLK>;
 			status = "disabled";
 		};
@@ -424,7 +430,7 @@
 		adc0: adc@59004000 {
 			compatible = "silabs,gecko-iadc";
 			reg = <0x59004000 0x4000>;
-			interrupts = <49 0>;
+			interrupts = <49 2>;
 			clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -433,15 +439,36 @@
 		dcdc: dcdc@50094000 {
 			compatible = "silabs,series2-dcdc";
 			reg = <0x50094000 0x4000>;
-			interrupts = <53 0>;
+			interrupts = <53 2>;
 			status = "disabled";
 		};
-	};
 
+		acmp0: acmp@59008000 {
+			compatible = "silabs,acmp";
+			reg = <0x59008000 0x4000>;
+			interrupts = <40 2>;
+			clocks = <&cmu CLOCK_ACMP0 CLOCK_BRANCH_EM01GRPACLK>;
+			status = "disabled";
+		};
 
-	bt_hci_silabs: bt_hci_silabs {
-		compatible = "silabs,bt-hci-efr32";
-		status = "disabled";
+		radio: radio@b0000000 {
+			compatible = "silabs,series2-radio";
+			reg = <0xb0000000 0x1000000>;
+			interrupts = <30 1>, <31 1>, <32 1>, <33 1>, <34 1>, <35 1>,
+				     <36 1>, <37 1>, <38 1>, <39 1>, <70 1>, <71 1>;
+			interrupt-names = "agc", "bufc", "frc_pri", "frc", "modem", "protimer",
+					  "rac_rsm", "rac_seq", "hostmailbox", "synth",
+					  "rfeca0", "rfeca1";
+			pa-initial-power-dbm = <10>;
+			pa-ramp-time-us = <10>;
+			pa-voltage-mv = <3300>;
+			pa-2p4ghz = "highest";
+
+			bt_hci_silabs: bt_hci_silabs {
+				compatible = "silabs,bt-hci-efr32";
+				status = "disabled";
+			};
+		};
 	};
 };
 
diff --git a/dts/arm/silabs/efr32xg23.dtsi b/dts/arm/silabs/efr32xg23.dtsi
index 9a76b47b867..81c8005c65f 100644
--- a/dts/arm/silabs/efr32xg23.dtsi
+++ b/dts/arm/silabs/efr32xg23.dtsi
@@ -9,6 +9,7 @@
 #include <dt-bindings/i2c/i2c.h>
 #include <dt-bindings/adc/adc.h>
 #include <dt-bindings/clock/silabs/xg23-clock.h>
+#include <dt-bindings/dma/silabs/xg23-dma.h>
 #include <freq.h>
 
 / {
@@ -149,6 +150,17 @@
 			compatible = "arm,cortex-m33";
 			reg = <0>;
 			cpu-power-states = <&pstate_em1 &pstate_em2 &pstate_em3>;
+			/*
+			 * The minimum residency and exit latency is
+			 * managed by sl_power_manager on S2 devices.
+			 */
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			itm: itm@e0000000 {
+				compatible = "arm,armv8m-itm";
+				reg = <0xe0000000 0x1000>;
+			};
 		};
 
 		power-states {
@@ -159,9 +171,7 @@
 			pstate_em1: em1 {
 				compatible = "zephyr,power-state";
 				power-state-name = "runtime-idle";
-				min-residency-us = <4>;
 				/* HFXO remains active */
-				exit-latency-us = <2>;
 			};
 
 			/*
@@ -171,8 +181,6 @@
 			pstate_em2: em2 {
 				compatible = "zephyr,power-state";
 				power-state-name = "suspend-to-idle";
-				min-residency-us = <260>;
-				exit-latency-us = <250>;
 			};
 
 			/*
@@ -184,8 +192,6 @@
 			pstate_em3: em3 {
 				compatible = "zephyr,power-state";
 				power-state-name = "standby";
-				min-residency-us = <20000>;
-				exit-latency-us = <2000>;
 			};
 		};
 	};
@@ -199,7 +205,7 @@
 		cmu: clock@50008000 {
 			compatible = "silabs,series-clock";
 			reg = <0x50008000 0x4000>;
-			interrupts = <48 0>;
+			interrupts = <48 2>;
 			interrupt-names = "cmu";
 			status = "okay";
 			#clock-cells = <2>;
@@ -271,9 +277,9 @@
 		};
 
 		msc: flash-controller@50030000 {
-			compatible = "silabs,gecko-flash-controller";
+			compatible = "silabs,series2-flash-controller";
 			reg = <0x50030000 0x4000>;
-			interrupts = <51 0>;
+			interrupts = <51 2>;
 
 			#address-cells = <1>;
 			#size-cells = <1>;
@@ -286,37 +292,36 @@
 		};
 
 		usart0: usart@5005c000 {
-			compatible = "silabs,gecko-usart";
+			compatible = "silabs,usart-uart";
 			reg = <0x5005C000 0x4000>;
-			interrupts = <9 0>, <10 0>;
+			interrupts = <9 2>, <10 2>;
 			interrupt-names = "rx", "tx";
-			peripheral-id = <0>;
 			clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
 			status = "disabled";
 		};
 
 		eusart0: eusart@5b010000 {
-			compatible = "silabs,gecko-spi-eusart";
+			compatible = "silabs,eusart-spi";
 			reg = <0x5B010000 0x4000>;
-			interrupts = <11 0>, <12 0>;
+			interrupts = <11 2>, <12 2>;
 			interrupt-names = "rx", "tx";
 			clocks = <&cmu CLOCK_EUSART0 CLOCK_BRANCH_EUSART0CLK>;
 			status = "disabled";
 		};
 
 		eusart1: eusart@500a0000 {
-			compatible = "silabs,gecko-spi-eusart";
+			compatible = "silabs,eusart-spi";
 			reg = <0x500A0000 0x4000>;
-			interrupts = <13 0>, <14 0>;
+			interrupts = <13 2>, <14 2>;
 			interrupt-names = "rx", "tx";
 			clocks = <&cmu CLOCK_EUSART1 CLOCK_BRANCH_EM01GRPCCLK>;
 			status = "disabled";
 		};
 
 		eusart2: eusart@500a4000 {
-			compatible = "silabs,gecko-spi-eusart";
+			compatible = "silabs,eusart-spi";
 			reg = <0x500A4000 0x4000>;
-			interrupts = <15 0>, <16 0>;
+			interrupts = <15 2>, <16 2>;
 			interrupt-names = "rx", "tx";
 			clocks = <&cmu CLOCK_EUSART2 CLOCK_BRANCH_EM01GRPCCLK>;
 			status = "disabled";
@@ -325,7 +330,7 @@
 		burtc0: burtc@50064000 {
 			compatible = "silabs,gecko-burtc";
 			reg = <0x50064000 0x4000>;
-			interrupts = <18 0>;
+			interrupts = <18 2>;
 			clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
 			status = "disabled";
 		};
@@ -344,7 +349,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x5b000000 0x4000>;
-			interrupts = <28 0>;
+			interrupts = <28 2>;
 			clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
 			status = "disabled";
 		};
@@ -355,7 +360,7 @@
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x50068000 0x4000>;
-			interrupts = <29 0>;
+			interrupts = <29 2>;
 			clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>;
 			status = "disabled";
 		};
@@ -363,7 +368,7 @@
 		sysrtc0: stimer0: sysrtc@500a8000 {
 			compatible = "silabs,gecko-stimer";
 			reg = <0x500a8000 0x4000>;
-			interrupts = <70 0>, <71 0>;
+			interrupts = <70 2>, <71 2>;
 			interrupt-names = "sysrtc_app", "sysrtc_seq";
 			clock-frequency = <32768>;
 			prescaler = <1>;
@@ -421,15 +426,16 @@
 
 		pinctrl: pin-controller@5003c440 {
 			compatible = "silabs,dbus-pinctrl";
-			reg = <0x5003c440 0xbc0>;
+			reg = <0x5003c440 0xbc0>, <0x5003c320 0x40>;
+			reg-names = "dbus", "abus";
 		};
 
 		dma0: dma@50040000{
 			compatible = "silabs,ldma";
 			reg = <0x50040000 0x4000>;
 			interrupts = <22 0>;
-			#dma-cells = <3>;
-			dma_channels = <8>;
+			#dma-cells = <1>;
+			dma-channels = <8>;
 			status = "disabled";
 		};
 
@@ -437,7 +443,7 @@
 			compatible = "silabs,gecko-wdog";
 			reg = <0x5b004000 0x4000>;
 			peripheral-id = <0>;
-			interrupts = <43 0>;
+			interrupts = <43 2>;
 			clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>;
 			status = "disabled";
 		};
@@ -446,7 +452,7 @@
 			compatible = "silabs,gecko-wdog";
 			reg = <0x5b008000 0x4000>;
 			peripheral-id = <1>;
-			interrupts = <44 0>;
+			interrupts = <44 2>;
 			clocks = <&cmu CLOCK_WDOG1 CLOCK_BRANCH_WDOG1CLK>;
 			status = "disabled";
 		};
@@ -454,7 +460,7 @@
 		adc0: adc@59004000 {
 			compatible = "silabs,gecko-iadc";
 			reg = <0x59004000 0x4000>;
-			interrupts = <50 0>;
+			interrupts = <50 2>;
 			clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>;
 			status = "disabled";
 			#io-channel-cells = <1>;
@@ -463,9 +469,31 @@
 		dcdc: dcdc@50094000 {
 			compatible = "silabs,series2-dcdc";
 			reg = <0x50094000 0x4000>;
-			interrupts = <54 0>;
+			interrupts = <54 2>;
+			status = "disabled";
+		};
+
+		acmp0: acmp@59008000 {
+			compatible = "silabs,acmp";
+			reg = <0x59008000 0x4000>;
+			interrupts = <41 2>;
+			clocks = <&cmu CLOCK_ACMP0 CLOCK_BRANCH_EM01GRPACLK>;
 			status = "disabled";
 		};
+
+		radio: radio@b0000000 {
+			compatible = "silabs,series2-radio";
+			reg = <0xb0000000 0x1000000>;
+			interrupts = <31 1>, <32 1>, <33 1>, <34 1>, <35 1>, <36 1>,
+				     <37 1>, <38 1>, <39 1>, <40 1>, <74 1>, <75 1>;
+			interrupt-names = "agc", "bufc", "frc_pri", "frc", "modem", "protimer",
+					  "rac_rsm", "rac_seq", "hostmailbox", "synth",
+					  "rfeca0", "rfeca1";
+			pa-initial-power-dbm = <10>;
+			pa-ramp-time-us = <10>;
+			pa-voltage-mv = <3300>;
+			pa-subghz = "highest";
+		};
 	};
 
 	hwinfo: hwinfo {
diff --git a/dts/arm/silabs/siwg917.dtsi b/dts/arm/silabs/siwg917.dtsi
new file mode 100644
index 00000000000..17e69a04725
--- /dev/null
+++ b/dts/arm/silabs/siwg917.dtsi
@@ -0,0 +1,322 @@
+/*
+ * Copyright (c) 2024-2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <zephyr/dt-bindings/clock/silabs/siwx91x-clock.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,entropy = &rng0;
+		zephyr,flash = &flash0;
+		zephyr,flash-controller = &flashctrl0;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@0 {
+		compatible = "mmio-sram";
+		/* siwx91x has 672kB of SRAM shared between the Cortex-M4
+		 * (Zephyr) and the NWP (Network Processor). 3 memory
+		 * configurations are
+		 * possible:
+		 *  - 196kB
+		 *  - 256kB
+		 *  - 320kB
+		 * Less memory is allocated to Zephyr, more memory is allocated
+		 * to NWP, better are the WiFi and BLE performances.
+		 */
+		reg = <0x00000000 DT_SIZE_K(256)>;
+	};
+
+	sram_dma1: memory-dma@24061c00 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x24061c00 DT_SIZE_K(1)>;
+		zephyr,memory-region = "dma1";
+		zephyr,memory-attr = <DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)>;
+	};
+
+	bt_hci0: bt_hci {
+		compatible = "silabs,siwx91x-bt-hci";
+		status = "disabled";
+	};
+
+	wifi0: wifi {
+		compatible = "silabs,siwx91x-wifi";
+		status = "disabled";
+	};
+
+	soc {
+		clock0: clock@46000000 {
+			compatible = "silabs,siwx91x-clock";
+			reg = <0x46000000 0x100>,
+			      <0x46000800 0x100>,
+			      <0x24041400 0x100>,
+			      <0x24048000 0x200>;
+			#clock-cells = <1>;
+			status = "okay";
+		};
+
+		pinctrl0: pinctrl@46130000 {
+			compatible = "silabs,siwx91x-pinctrl";
+			reg = <0x46130000 0x1000>;
+		};
+
+		flashctrl0: flash-controller@12000000 {
+			compatible = "silabs,siwx91x-flash-controller";
+			reg = <0x12000000 0x200>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8202000 {
+				compatible = "soc-nv-flash";
+				write-block-size = <1>;
+				erase-block-size = <4096>;
+			};
+		};
+
+		ulpuart: uart@24041800 {
+			compatible = "ns16550";
+			reg = <0x24041800 0x1000>;
+			interrupts = <12 0>;
+			reg-shift = <2>;
+			clocks = <&clock0 SIWX91X_CLK_ULP_UART>;
+			current-speed = <115200>;
+			status = "disabled";
+		};
+
+		uart0: uart@44000000 {
+			compatible = "ns16550";
+			reg = <0x44000000 0x1000>;
+			interrupts = <38 0>;
+			reg-shift = <2>;
+			clocks = <&clock0 SIWX91X_CLK_UART0>;
+			current-speed = <115200>;
+			status = "disabled";
+		};
+
+		uart1: uart@45020000 {
+			compatible = "ns16550";
+			reg = <0x45020000 0x1000>;
+			interrupts = <39 0>;
+			reg-shift = <2>;
+			clocks = <&clock0 SIWX91X_CLK_UART1>;
+			current-speed = <115200>;
+			status = "disabled";
+		};
+
+		rng0: rng@45090000 {
+			compatible = "silabs,siwx91x-rng";
+			reg = <0x45090000 0x8>;
+		};
+
+		egpio0: egpio@46130000 {
+			compatible = "silabs,siwx91x-gpio";
+			reg = <0x46130000 0x1260>;
+			interrupts = <52 0>, <53 0>, <54 0>, <55 0>,
+				     <56 0>, <57 0>, <58 0>, <59 0>;
+			interrupt-names = "PIN0", "PIN1", "PIN2", "PIN3",
+					  "PIN4", "PIN5", "PIN6", "PIN7";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			gpioa: gpio@0 {
+				compatible = "silabs,siwx91x-gpio-port";
+				reg = <0>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <16>;
+				gpio-reserved-ranges = <0 6>;
+				silabs,pads = [
+					ff ff ff ff  ff ff 01 02  03 04 05 06  07 ff ff 08
+				];
+				status = "okay";
+			};
+
+			gpiob: gpio@1 {
+				compatible = "silabs,siwx91x-gpio-port";
+				reg = <1>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <16>;
+				silabs,pads = [
+					ff ff ff ff  ff ff ff ff  ff 00 00 00  00 00 00 09
+				];
+				status = "okay";
+			};
+
+			gpioc: gpio@2 {
+				compatible = "silabs,siwx91x-gpio-port";
+				reg = <2>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <16>;
+				silabs,pads = [
+					09 09 09 ff  ff ff ff ff  ff ff ff ff  ff ff 0a 0b
+				];
+				status = "okay";
+			};
+
+			gpiod: gpio@3 {
+				compatible = "silabs,siwx91x-gpio-port";
+				reg = <3>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <10>;
+				silabs,pads = [
+					0c 0d 0e 0f  10 11 12 13  14 15 ff ff  ff ff ff ff
+				];
+				status = "okay";
+			};
+		};
+
+		egpio1: egpio@2404c000 {
+			compatible = "silabs,siwx91x-gpio";
+			reg = <0x2404C000 0x1260>;
+			interrupts = <18 0>;
+			interrupt-names = "ULP";
+			silabs,ulp;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			ulpgpio: ulpgpio@0 {
+				compatible = "silabs,siwx91x-gpio-port";
+				reg = <0>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <12>;
+				gpio-reserved-ranges = <3 1>;
+				silabs,pads = [
+					16 17 18 19  1a 1b 1c 1d  1e 1f 20 21  ff ff ff ff
+				];
+				status = "okay";
+			};
+		};
+
+		uulpgpio: uulpgpio@24048600 {
+			compatible = "silabs,siwx91x-gpio-uulp";
+			reg = <0x24048600 0x30>, <0x12080000 0x18>;
+			reg-names = "ret", "int";
+			interrupts = <21 0>;
+			interrupt-names = "UULP";
+
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <5>;
+			status = "okay";
+		};
+
+		ulpi2c: i2c@24040000 {
+			compatible = "snps,designware-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x24040000 0x100>;
+			interrupts = <13 0>;
+			interrupt-names = "i2c2";
+			clocks = <&clock0 SIWX91X_CLK_ULP_I2C>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@44010000 {
+			compatible = "snps,designware-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x44010000 0x100>;
+			interrupts = <42 0>;
+			interrupt-names = "i2c0";
+			clocks = <&clock0 SIWX91X_CLK_I2C0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@47040000 {
+			compatible = "snps,designware-i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x47040000 0x100>;
+			interrupts = <61 0>;
+			interrupt-names = "i2c1";
+			clocks = <&clock0 SIWX91X_CLK_I2C1>;
+			status = "disabled";
+		};
+
+		dma0: dma@44030000 {
+			compatible = "silabs,siwx91x-dma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x44030000 0x82C>;
+			interrupts = <33 0>;
+			interrupt-names = "dma0";
+			clocks = <&clock0 SIWX91X_CLK_DMA0>;
+			#dma-cells = < 1>;
+			dma-channels = <32>;
+			status = "disabled";
+		};
+
+		ulpdma: dma@24078000 {
+			compatible = "silabs,siwx91x-dma";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x24078000 0x82C>;
+			interrupts = <10 0>;
+			interrupt-names = "ulpdma";
+			clocks = <&clock0 SIWX91X_CLK_ULP_DMA>;
+			silabs,sram-region = <&sram_dma1>;
+			#dma-cells = < 1>;
+			dma-channels = <12>;
+			status = "disabled";
+		};
+
+		pwm: pwm@47070000 {
+			compatible = "silabs,siwx91x-pwm";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x47070000 0x14C>;
+			interrupts = <48 0>;
+			interrupt-names = "pwm";
+			clocks = <&clock0 SIWX91X_CLK_PWM>;
+			#pwm-cells = <2>;
+			silabs,ch_prescaler = <64 64 64 64>;
+			status = "disabled";
+		};
+
+		watchdog: wdt@24048300 {
+			compatible = "silabs,siwx91x-wdt";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x24048300 0x1C>;
+			interrupts = <20 0>;
+			interrupt-names = "watchdog";
+			clocks = <&clock0 SIWX91X_CLK_WATCHDOG>;
+			status = "disabled";
+		};
+
+		sysrtc0: sysrtc@24048c00 {
+			compatible = "silabs,gecko-stimer";
+			reg = <0x24048c00 0x78>;
+			interrupts = <22 0>;
+			interrupt-names = "sysrtc";
+			clock-frequency = <DT_FREQ_K(32)>;
+			prescaler = <1>;
+			status = "disabled";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <6>;
+};
diff --git a/dts/arm/silabs/siwg917m111mgtba.dtsi b/dts/arm/silabs/siwg917m111mgtba.dtsi
new file mode 100644
index 00000000000..b2c7d3a1b5c
--- /dev/null
+++ b/dts/arm/silabs/siwg917m111mgtba.dtsi
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2023 Antmicro
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <silabs/siwg917.dtsi>
+
+/ {
+	soc {
+		compatible = "silabs,siwg917m111mgtba", "silabs,siwg917",
+			     "silabs,siwx91x", "simple-bus";
+	};
+};
+
+&flash0 {
+	reg = <0x08202000 DT_SIZE_K(2048-8)>;
+};
diff --git a/dts/arm/silabs/xg29/efr32bg29b140f1024im40.dtsi b/dts/arm/silabs/xg29/efr32bg29b140f1024im40.dtsi
new file mode 100644
index 00000000000..fd458ea3c4e
--- /dev/null
+++ b/dts/arm/silabs/xg29/efr32bg29b140f1024im40.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <silabs/xg29/xg29.dtsi>
+
+/ {
+	soc {
+		compatible = "silabs,efr32bg29b140f1024im40", "silabs,efr32bg29", "silabs,xg29",
+			     "silabs,efr32", "simple-bus";
+	};
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(256)>;
+};
+
+&flash0 {
+	reg = <0x08000000 DT_SIZE_K(1024)>;
+};
diff --git a/dts/arm/silabs/xg29/efr32bg29b220f1024cj45.dtsi b/dts/arm/silabs/xg29/efr32bg29b220f1024cj45.dtsi
new file mode 100644
index 00000000000..ec744a27f35
--- /dev/null
+++ b/dts/arm/silabs/xg29/efr32bg29b220f1024cj45.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <silabs/xg29/xg29.dtsi>
+#include <zephyr/dt-bindings/regulator/silabs_dcdc.h>
+
+/ {
+	soc {
+		compatible = "silabs,efr32bg29b220f1024cj45", "silabs,efr32bg29", "silabs,xg29",
+			     "silabs,efr32", "simple-bus";
+	};
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(256)>;
+};
+
+&flash0 {
+	reg = <0x08000000 DT_SIZE_K(1024)>;
+};
+
+&dcdc {
+	regulator-boot-on;
+	regulator-initial-mode = <SILABS_DCDC_MODE_BOOST>;
+	regulator-init-microvolt = <1800000>;
+	status = "okay";
+};
diff --git a/dts/arm/silabs/xg29/efr32bg29b221f1024cj45.dtsi b/dts/arm/silabs/xg29/efr32bg29b221f1024cj45.dtsi
new file mode 100644
index 00000000000..b3fea2edd79
--- /dev/null
+++ b/dts/arm/silabs/xg29/efr32bg29b221f1024cj45.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <silabs/xg29/xg29.dtsi>
+#include <zephyr/dt-bindings/regulator/silabs_dcdc.h>
+
+/ {
+	soc {
+		compatible = "silabs,efr32bg29b221f1024cj45", "silabs,efr32bg29", "silabs,xg29",
+			     "silabs,efr32", "simple-bus";
+	};
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(192)>;
+};
+
+&flash0 {
+	reg = <0x08000000 DT_SIZE_K(1024)>;
+};
+
+&dcdc {
+	regulator-boot-on;
+	regulator-initial-mode = <SILABS_DCDC_MODE_BOOST>;
+	regulator-init-microvolt = <1800000>;
+	status = "okay";
+};
diff --git a/dts/arm/silabs/xg29/efr32bg29b230f1024cm40.dtsi b/dts/arm/silabs/xg29/efr32bg29b230f1024cm40.dtsi
new file mode 100644
index 00000000000..0acadabcbdc
--- /dev/null
+++ b/dts/arm/silabs/xg29/efr32bg29b230f1024cm40.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <silabs/xg29/xg29.dtsi>
+#include <zephyr/dt-bindings/regulator/silabs_dcdc.h>
+
+/ {
+	soc {
+		compatible = "silabs,efr32bg29b230f1024cm40", "silabs,efr32bg29", "silabs,xg29",
+			     "silabs,efr32", "simple-bus";
+	};
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(256)>;
+};
+
+&flash0 {
+	reg = <0x08000000 DT_SIZE_K(1024)>;
+};
+
+&dcdc {
+	regulator-boot-on;
+	regulator-initial-mode = <SILABS_DCDC_MODE_BOOST>;
+	regulator-init-microvolt = <1800000>;
+	status = "okay";
+};
diff --git a/dts/arm/silabs/xg29/efr32mg29b140f1024im40.dtsi b/dts/arm/silabs/xg29/efr32mg29b140f1024im40.dtsi
new file mode 100644
index 00000000000..84fdecb94b2
--- /dev/null
+++ b/dts/arm/silabs/xg29/efr32mg29b140f1024im40.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <silabs/xg29/xg29.dtsi>
+
+/ {
+	soc {
+		compatible = "silabs,efr32mg29b140f1024im40", "silabs,efr32mg29", "silabs,xg29",
+			     "silabs,efr32", "simple-bus";
+	};
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(256)>;
+};
+
+&flash0 {
+	reg = <0x08000000 DT_SIZE_K(1024)>;
+};
diff --git a/dts/arm/silabs/xg29/efr32mg29b230f1024cm40.dtsi b/dts/arm/silabs/xg29/efr32mg29b230f1024cm40.dtsi
new file mode 100644
index 00000000000..60e2d9f7465
--- /dev/null
+++ b/dts/arm/silabs/xg29/efr32mg29b230f1024cm40.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <silabs/xg29/xg29.dtsi>
+#include <zephyr/dt-bindings/regulator/silabs_dcdc.h>
+
+/ {
+	soc {
+		compatible = "silabs,efr32mg29b230f1024cm40", "silabs,efr32mg29", "silabs,xg29",
+			     "silabs,efr32", "simple-bus";
+	};
+};
+
+&sram0 {
+	reg = <0x20000000 DT_SIZE_K(256)>;
+};
+
+&flash0 {
+	reg = <0x08000000 DT_SIZE_K(1024)>;
+};
+
+&dcdc {
+	regulator-boot-on;
+	regulator-initial-mode = <SILABS_DCDC_MODE_BOOST>;
+	regulator-init-microvolt = <1800000>;
+	status = "okay";
+};
diff --git a/dts/arm/silabs/xg29/xg29.dtsi b/dts/arm/silabs/xg29/xg29.dtsi
new file mode 100644
index 00000000000..621a6a4fa06
--- /dev/null
+++ b/dts/arm/silabs/xg29/xg29.dtsi
@@ -0,0 +1,492 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv8-m.dtsi>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/i2c/i2c.h>
+#include <dt-bindings/adc/adc.h>
+#include <dt-bindings/clock/silabs/xg29-clock.h>
+#include <dt-bindings/dma/silabs/xg29-dma.h>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,flash-controller = &msc;
+		zephyr,entropy = &se;
+	};
+
+	clocks {
+		hfxort: hfxort {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&hfxo>;
+		};
+
+		hfrcodpllrt: hfrcodpllrt {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&hfrcodpll>;
+		};
+
+		sysclk: sysclk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&hfrcodpll>;
+		};
+
+		hclk: hclk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&sysclk>;
+			/* Divisors 1, 2, 4, 8, 16 allowed */
+			clock-div = <1>;
+		};
+
+		pclk: pclk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&hclk>;
+			/* Divisors 1, 2 allowed */
+			clock-div = <2>;
+		};
+
+		lspclk: lspclk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&pclk>;
+			/* Fixed divisor of 2 */
+			clock-div = <2>;
+		};
+
+		hclkdiv1024: hclkdiv1024 {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&hclk>;
+			/* Fixed divisor of 1024 */
+			clock-div = <1024>;
+		};
+
+		traceclk: traceclk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&sysclk>;
+			/* Divisors 1, 2, 3, 4 allowed */
+			clock-div = <1>;
+		};
+
+		em01grpaclk: em01grpaclk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&hfrcodpll>;
+		};
+
+		em01grpbclk: em01grpbclk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&hfrcodpll>;
+		};
+
+		em01grpcclk: em01grpcclk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&hfrcodpll>;
+		};
+
+		iadcclk: iadcclk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&em01grpaclk>;
+		};
+
+		em23grpaclk: em23grpaclk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&lfrco>;
+		};
+
+		em4grpaclk: em4grpaclk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&lfrco>;
+		};
+
+		rtccclk: rtccclk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&lfrco>;
+		};
+
+		wdog0clk: wdog0clk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&lfrco>;
+		};
+
+		systickclk: systickclk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&hclk>;
+		};
+
+		eusart0clk: eusart0clk {
+			#clock-cells = <0>;
+			compatible = "fixed-factor-clock";
+			clocks = <&em01grpaclk>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m33";
+			reg = <0>;
+			cpu-power-states = <&pstate_em1 &pstate_em2>;
+			/*
+			 * The minimum residency and exit latency is
+			 * managed by sl_power_manager on S2 devices.
+			 */
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			itm: itm@e0000000 {
+				compatible = "arm,armv8m-itm";
+				reg = <0xe0000000 0x1000>;
+			};
+		};
+
+		power-states {
+			/*
+			 * EM1 is a basic "CPU WFI idle", all high-freq clocks remain
+			 * enabled.
+			 */
+			pstate_em1: em1 {
+				compatible = "zephyr,power-state";
+				power-state-name = "runtime-idle";
+				/* HFXO remains active */
+			};
+
+			/*
+			 * EM2 is a deepsleep with HF clocks disabled by HW, voltages
+			 * scaled down, etc.
+			 */
+			pstate_em2: em2 {
+				compatible = "zephyr,power-state";
+				power-state-name = "suspend-to-idle";
+			};
+		};
+	};
+
+	sram0: memory@20000000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+	};
+
+	soc {
+		cmu: clock@50008000 {
+			compatible = "silabs,series-clock";
+			reg = <0x50008000 0x4000>;
+			interrupts = <52 2>;
+			interrupt-names = "cmu";
+			status = "okay";
+			#clock-cells = <2>;
+		};
+
+		hfxo: hfxo@5000c000 {
+			#clock-cells = <0>;
+			compatible = "silabs,hfxo";
+			reg = <0x5000c000 0x4000>;
+			interrupts = <50 0>;
+			interrupt-names = "hfxo0";
+			clock-frequency = <DT_FREQ_K(38400)>;
+			ctune = <140>;
+			precision = <50>;
+			status = "disabled";
+		};
+
+		hfrcodpll: hfrcodpll@50010000 {
+			#clock-cells = <0>;
+			compatible = "silabs,series2-hfrcodpll";
+			reg = <0x50010000 0x4000>;
+			interrupts = <51 0>, <56 0>;
+			interrupt-names = "hfrco0", "dpll0";
+			clock-frequency = <DT_FREQ_M(19)>;
+		};
+
+		fsrco: fsrco@50018000 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			reg = <0x50018000 0x4000>;
+			clock-frequency = <DT_FREQ_M(20)>;
+		};
+
+		lfxo: lfxo@50020000 {
+			#clock-cells = <0>;
+			compatible = "silabs,series2-lfxo";
+			reg = <0x50020000 0x4000>;
+			interrupts = <27 2>;
+			interrupt-names = "lfxo";
+			clock-frequency = <32768>;
+			ctune = <63>;
+			precision = <50>;
+			timeout = <4096>;
+			status = "disabled";
+		};
+
+		lfrco: lfrco@50024000 {
+			#clock-cells = <0>;
+			compatible = "silabs,series2-lfrco";
+			reg = <0x50024000 0x4000>;
+			interrupts = <28 2>;
+			interrupt-names = "lfrco";
+			clock-frequency = <32768>;
+		};
+
+		ulfrco: ulfrco@50028000 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			reg = <0x50028000 0x4000>;
+			interrupts = <29 2>;
+			interrupt-names = "ulfrco";
+			clock-frequency = <1000>;
+		};
+
+		clkin0: clkin0@5003c460 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			reg = <0x5003c460 0x4>;
+			clock-frequency = <DT_FREQ_M(38)>;
+		};
+
+		msc: flash-controller@50030000 {
+			compatible = "silabs,series2-flash-controller";
+			reg = <0x50030000 0x4000>;
+			interrupts = <55 2>;
+			interrupt-names = "msc";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "soc-nv-flash";
+				write-block-size = <4>;
+				erase-block-size = <8192>;
+			};
+		};
+
+		gpio: gpio@5003c000 {
+			compatible = "silabs,gecko-gpio";
+			reg = <0x5003C000 0x440>;
+			interrupts = <31 2>, <30 2>;
+			interrupt-names = "GPIO_EVEN", "GPIO_ODD";
+			clocks = <&cmu CLOCK_GPIO CLOCK_BRANCH_PCLK>;
+			ranges;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			gpioa: gpio@5003c030 {
+				compatible = "silabs,gecko-gpio-port";
+				reg = <0x5003C030 0x30>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				status = "disabled";
+			};
+
+			gpiob: gpio@5003c060 {
+				compatible = "silabs,gecko-gpio-port";
+				reg = <0x5003C060 0x30>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				status = "disabled";
+			};
+
+			gpioc: gpio@5003c090 {
+				compatible = "silabs,gecko-gpio-port";
+				reg = <0x5003C090 0x30>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				status = "disabled";
+			};
+
+			gpiod: gpio@5003c0c0 {
+				compatible = "silabs,gecko-gpio-port";
+				reg = <0x5003C0C0 0x30>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				status = "disabled";
+			};
+		};
+
+		pinctrl: pin-controller@5003c440 {
+			compatible = "silabs,dbus-pinctrl";
+			reg = <0x5003c440 0xbc0>, <0x5003c320 0x40>;
+			reg-names = "dbus", "abus";
+		};
+
+		dma0: dma@40040000{
+			compatible = "silabs,ldma";
+			reg = <0x40040000 0x4000>;
+			interrupts = <26 0>;
+			interrupt-names = "ldma";
+			#dma-cells = <1>;
+			dma-channels = <8>;
+			status = "disabled";
+		};
+
+		usart0: usart@5005c000 {
+			compatible = "silabs,usart-uart";
+			reg = <0x5005C000 0x400>;
+			interrupts = <16 2>, <17 2>;
+			interrupt-names = "rx", "tx";
+			clocks = <&cmu CLOCK_USART0 CLOCK_BRANCH_PCLK>;
+			status = "disabled";
+		};
+
+		usart1: usart@50060000 {
+			compatible = "silabs,usart-uart";
+			reg = <0x50060000 0x400>;
+			interrupts = <18 2>, <19 2>;
+			interrupt-names = "rx", "tx";
+			clocks = <&cmu CLOCK_USART1 CLOCK_BRANCH_PCLK>;
+			status = "disabled";
+		};
+
+		burtc0: burtc@50064000 {
+			compatible = "silabs,gecko-burtc";
+			reg = <0x50064000 0x4000>;
+			interrupts = <23 2>;
+			interrupt-names = "burtc";
+			clocks = <&cmu CLOCK_BURTC CLOCK_BRANCH_EM4GRPACLK>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@5a010000 {
+			compatible = "silabs,gecko-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			reg = <0x5a010000 0x4000>;
+			interrupts = <32 2>;
+			interrupt-names = "i2c0";
+			clocks = <&cmu CLOCK_I2C0 CLOCK_BRANCH_LSPCLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@50068000 {
+			compatible = "silabs,gecko-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			reg = <0x50068000 0x4000>;
+			interrupts = <33 2>;
+			interrupt-names = "i2c1";
+			clocks = <&cmu CLOCK_I2C1 CLOCK_BRANCH_PCLK>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		dcdc: dcdc@50094000 {
+			compatible = "silabs,series2-dcdc";
+			reg = <0x50094000 0x4000>;
+			interrupts = <8 2>;
+			interrupt-names = "dcdc";
+			status = "disabled";
+		};
+
+		eusart0: eusart@5a040000 {
+			compatible = "silabs,eusart-spi";
+			reg = <0x5A040000 0x4000>;
+			interrupts = <20 2>, <21 2>;
+			interrupt-names = "rx", "tx";
+			clocks = <&cmu CLOCK_EUSART0 CLOCK_BRANCH_EUSART0CLK>;
+			status = "disabled";
+		};
+
+		eusart1: eusart@500b4000 {
+			compatible = "silabs,eusart-spi";
+			reg = <0x500B4000 0x4000>;
+			interrupts = <68 2>, <69 2>;
+			interrupt-names = "rx", "tx";
+			clocks = <&cmu CLOCK_EUSART1 CLOCK_BRANCH_EM01GRPCCLK>;
+			status = "disabled";
+		};
+
+		rtcc0: rtcc@58000000 {
+			compatible = "silabs,gecko-stimer";
+			reg = <0x58000000 0x4000>;
+			interrupts = <15 2>;
+			interrupt-names = "rtcc";
+			clocks = <&cmu CLOCK_RTCC CLOCK_BRANCH_RTCCCLK>;
+			clock-frequency = <32768>;
+			prescaler = <1>;
+			status = "disabled";
+		};
+
+		wdog0: wdog@58018000 {
+			compatible = "silabs,gecko-wdog";
+			reg = <0x58018000 0x4000>;
+			peripheral-id = <0>;
+			interrupts = <49 2>;
+			interrupt-names = "wdog0";
+			clocks = <&cmu CLOCK_WDOG0 CLOCK_BRANCH_WDOG0CLK>;
+			status = "disabled";
+		};
+
+		adc0: adc@5a004000 {
+			compatible = "silabs,gecko-iadc";
+			reg = <0x5a004000 0x4000>;
+			interrupts = <54 2>;
+			interrupt-names = "iadc0";
+			clocks = <&cmu CLOCK_IADC0 CLOCK_BRANCH_IADCCLK>;
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
+		acmp0: acmp@5a008000 {
+			compatible = "silabs,acmp";
+			reg = <0x5a008000 0x4000>;
+			interrupts = <48 2>;
+			clocks = <&cmu CLOCK_ACMP0 CLOCK_BRANCH_EM01GRPACLK>;
+			status = "disabled";
+		};
+
+		se: semailbox@4c000000 {
+			compatible = "silabs,gecko-semailbox";
+			reg = <0x4c000000 0x1000>;
+			interrupts = <0 3>, <1 3>, <2 3>;
+			interrupt-names = "SETAMPERHOST", "SEMBRX", "SEMBTX";
+			status = "disabled";
+		};
+
+		radio: radio@b0000000 {
+			compatible = "silabs,series2-radio";
+			reg = <0xb0000000 0x1000000>;
+			interrupts = <36 1>, <37 1>, <38 1>, <39 1>, <40 1>, <41 1>,
+				     <42 1>, <43 1>, <44 1>, <45 1>, <46 1>, <47 1>;
+			interrupt-names = "agc", "bufc", "frc_pri", "frc", "modem", "protimer",
+					  "rac_rsm", "rac_seq", "rdmailbox", "rfsense", "synth",
+					  "prortc";
+			pa-initial-power-dbm = <10>;
+			pa-ramp-time-us = <2>;
+			pa-voltage-mv = <3300>;
+			pa-2p4ghz = "highest";
+
+			bt_hci_silabs: bt_hci_silabs {
+				compatible = "silabs,bt-hci-efr32";
+				status = "disabled";
+			};
+		};
+	};
+
+	hwinfo: hwinfo {
+		compatible = "silabs,series2-hwinfo";
+		status = "disabled";
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/st/c0/stm32c0.dtsi b/dts/arm/st/c0/stm32c0.dtsi
index 3014abd7b5f..e5545e8b05f 100644
--- a/dts/arm/st/c0/stm32c0.dtsi
+++ b/dts/arm/st/c0/stm32c0.dtsi
@@ -3,6 +3,58 @@
  * Copyright (c) 2024 STMicroelectronics
  *
  * SPDX-License-Identifier: Apache-2.0
+ *
+ * The mapping of wake-up line WKUP2, WKUP5 and WKUP6 to GPIO pins depends on
+ * the pin count of the SoC installed on a given board. Board DTS files are
+ * responsible for configuring these lines using the following snippet
+ * (which must be adapted depending on the board's SoC):
+ *
+ *   &pwr {
+ *       wkup-pin@2 {
+ *           wkup-gpios = <&gpioX YY STM32_PWR_WKUP_PIN_NOT_MUXED>;
+ *       };
+ *       wkup-pin@5 {
+ *           wkup-gpios = <&gpioX YY STM32_PWR_WKUP_PIN_NOT_MUXED>;
+ *       };
+ *       wkup-pin@6 {
+ *           wkup-gpios = <&gpioX YY STM32_PWR_WKUP_PIN_NOT_MUXED>;
+ *       };
+ *   };
+ *
+ * Refer to product Datasheet §4 "Pinouts, pin description and alternate functions"
+ * for information about which GPIO pin (if any) is connected to wake-up lines WKUP2,
+ * WKUP5 and WKUP6. The following table provides a summary:
+ *
+ * Part Number |- WKUP2 -|- WKUP5 -|- WKUP6 -|
+ * ------------|---------|---------|---------|
+ * STM32C011Jx |   N/A   |   N/A   |   N/A   |
+ * STM32C011Dx |   PA4   |   N/A   |   N/A   |
+ * STM32C011Fx |   PA4   |   N/A   |   N/A   |
+ * ------------|---------|---------|---------|
+ * STM32C031Fx |   PA4   |   N/A   |   N/A   |
+ * STM32C031Gx |   PA4   |   N/A   |   PB5   |
+ * STM32C031Kx |   PA4   |   N/A   |   PB5   |
+ * STM32C031Cx |   PC13  |   N/A   |   PB5   |
+ * ------------|---------|---------|---------|
+ * STM32C051Dx |   PA4   |   N/A   |   PB5   |
+ * STM32C051Fx |   PA4   |   N/A   |   PB5   |
+ * STM32C051Gx |   PA4   |   N/A   |   PB5   |
+ * STM32C051Kx |   PA4   |   N/A   |   PB5   |
+ * STM32C051Cx |   PC13  |   N/A   |   PB5   |
+ * ------------|---------|---------|---------|
+ * STM32C071Fx |   PA4   |   N/A   |   PB5   |
+ * STM32C071Gx |   PA4   |   N/A   |   PB5   |
+ * STM32C071Kx |   PA4   |   N/A   |   PB5   |
+ * STM32C071Cx |   PC13  |   N/A   |   PB5   |
+ * STM32C071Rx |   PC13  |   PC5   |   PB5   |
+ * ------------|---------|---------|---------|
+ * STM32C09xFx |   PA4   |   N/A   |   PB5   |
+ * STM32C09xEx |   PA4   |   N/A   |   PB5   |
+ * STM32C09xGx |   PA4   |   N/A   |   PB5   |
+ * STM32C09xKx |   PA4   |   N/A   |   PB5   |
+ * STM32C09xCx |   PC13  |   N/A   |   PB5   |
+ * STM32C09xRx |   PC13  |   PC5   |   PB5   |
+ * ------------|---------|---------|---------|
  */
 
 #include <arm/armv6-m.dtsi>
@@ -15,6 +67,7 @@
 #include <zephyr/dt-bindings/pwm/stm32_pwm.h>
 #include <zephyr/dt-bindings/adc/stm32l4_adc.h>
 #include <zephyr/dt-bindings/reset/stm32c0_reset.h>
+#include <zephyr/dt-bindings/power/stm32_pwr.h>
 #include <freq.h>
 
 / {
@@ -162,6 +215,46 @@
 			};
 		};
 
+		pwr: power@40007000 {
+			compatible = "st,stm32-pwr";
+			reg = <0x40007000 0x400>; /* PWR register bank */
+			status = "disabled";
+
+			wkup-pins-nb = <6>; /* 6 system wake-up pins */
+			wkup-pins-pol;
+			wkup-pins-pupd;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			wkup-pin@1 {
+				reg = <0x1>;
+				wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_NOT_MUXED>;
+			};
+
+			wkup-pin@2 {
+				reg = <0x2>;
+			};
+
+			wkup-pin@3 {
+				reg = <0x3>;
+				wkup-gpios = <&gpiob 6 STM32_PWR_WKUP_PIN_NOT_MUXED>;
+			};
+
+			wkup-pin@4 {
+				reg = <0x4>;
+				wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_NOT_MUXED>;
+			};
+
+			wkup-pin@5 {
+				reg = <0x5>;
+			};
+
+			wkup-pin@6 {
+				reg = <0x6>;
+			};
+		};
+
 		rtc: rtc@40002800 {
 			compatible = "st,stm32-rtc";
 			reg = <0x40002800 0x400>;
diff --git a/dts/arm/st/f0/stm32f042.dtsi b/dts/arm/st/f0/stm32f042.dtsi
index 2dc48d49e7c..c855e3b0c2c 100644
--- a/dts/arm/st/f0/stm32f042.dtsi
+++ b/dts/arm/st/f0/stm32f042.dtsi
@@ -72,6 +72,7 @@
 			interrupt-names = "usb";
 			num-bidir-endpoints = <8>;
 			ram-size = <1024>;
+			maximum-speed = "full-speed";
 			phys = <&usb_fs_phy>;
 			clocks = <&rcc STM32_CLOCK(APB1, 23U)>,
 				 <&rcc STM32_SRC_PLLCLK USB_SEL(1)>;
diff --git a/dts/arm/st/f0/stm32f070.dtsi b/dts/arm/st/f0/stm32f070.dtsi
index 98f2de5aa33..295e5739dfc 100644
--- a/dts/arm/st/f0/stm32f070.dtsi
+++ b/dts/arm/st/f0/stm32f070.dtsi
@@ -43,6 +43,7 @@
 			interrupt-names = "usb";
 			num-bidir-endpoints = <8>;
 			ram-size = <1024>;
+			maximum-speed = "full-speed";
 			phys = <&usb_fs_phy>;
 			clocks = <&rcc STM32_CLOCK(APB1, 23U)>,
 				 <&rcc STM32_SRC_PLLCLK USB_SEL(1)>;
diff --git a/dts/arm/st/f0/stm32f072.dtsi b/dts/arm/st/f0/stm32f072.dtsi
index 734b44ad346..3bb264c10b9 100644
--- a/dts/arm/st/f0/stm32f072.dtsi
+++ b/dts/arm/st/f0/stm32f072.dtsi
@@ -25,6 +25,7 @@
 			interrupt-names = "usb";
 			num-bidir-endpoints = <8>;
 			ram-size = <1024>;
+			maximum-speed = "full-speed";
 			phys = <&usb_fs_phy>;
 			clocks = <&rcc STM32_CLOCK(APB1, 23U)>,
 				 <&rcc STM32_SRC_PLLCLK USB_SEL(1)>;
diff --git a/dts/arm/st/f1/stm32f103X8.dtsi b/dts/arm/st/f1/stm32f103X8.dtsi
index 19ea073904e..67b32d576a4 100644
--- a/dts/arm/st/f1/stm32f103X8.dtsi
+++ b/dts/arm/st/f1/stm32f103X8.dtsi
@@ -42,6 +42,7 @@
 			interrupt-names = "usb";
 			num-bidir-endpoints = <8>;
 			ram-size = <512>;
+			maximum-speed = "full-speed";
 			status = "disabled";
 			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
 			phys = <&usb_fs_phy>;
diff --git a/dts/arm/st/f1/stm32f105.dtsi b/dts/arm/st/f1/stm32f105.dtsi
index d4f05930a80..323941552cb 100644
--- a/dts/arm/st/f1/stm32f105.dtsi
+++ b/dts/arm/st/f1/stm32f105.dtsi
@@ -49,7 +49,7 @@
 			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
 			/* also enabling clock for can1 (master instance) */
-			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
 			status = "disabled";
 		};
 
@@ -146,6 +146,7 @@
 			num-bidir-endpoints = <4>;
 			ram-size = <1280>;
 			clocks = <&rcc STM32_CLOCK(AHB1, 12U)>;
+			maximum-speed = "full-speed";
 			phys = <&otgfs_phy>;
 			status = "disabled";
 		};
diff --git a/dts/arm/st/f1/stm32f107.dtsi b/dts/arm/st/f1/stm32f107.dtsi
index 1ba41fff760..8f4b2d6b991 100644
--- a/dts/arm/st/f1/stm32f107.dtsi
+++ b/dts/arm/st/f1/stm32f107.dtsi
@@ -19,16 +19,26 @@
 			status = "disabled";
 		};
 
-		mac: ethernet@40028000 {
-			compatible = "st,stm32-ethernet";
+		ethernet@40028000 {
 			reg = <0x40028000 0x2000>;
-			interrupts = <61 0>;
-			clock-names = "stmmaceth", "mac-clk-tx",
-				      "mac-clk-rx";
-			clocks = <&rcc STM32_CLOCK(AHB1, 14U)>,
-				 <&rcc STM32_CLOCK(AHB1, 15U)>,
-				 <&rcc STM32_CLOCK(AHB1, 16U)>;
-			status = "disabled";
+			clock-names = "stm-eth";
+			clocks = <&rcc STM32_CLOCK(AHB1, 14)>;
+
+			mac: ethernet {
+				compatible = "st,stm32-ethernet";
+				interrupts = <61 0>;
+				clock-names = "mac-clk-tx", "mac-clk-rx";
+				clocks = <&rcc STM32_CLOCK(AHB1, 15)>,
+					 <&rcc STM32_CLOCK(AHB1, 16)>;
+				status = "disabled";
+			};
+
+			mdio: mdio {
+				compatible = "st,stm32-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 	};
 };
diff --git a/dts/arm/st/f2/stm32f207.dtsi b/dts/arm/st/f2/stm32f207.dtsi
index a3d8ce18bb7..53bd1a77ebe 100644
--- a/dts/arm/st/f2/stm32f207.dtsi
+++ b/dts/arm/st/f2/stm32f207.dtsi
@@ -10,17 +10,29 @@
 	soc {
 		compatible = "st,stm32f207", "st,stm32f2", "simple-bus";
 
-		mac: ethernet@40028000 {
-			compatible = "st,stm32-ethernet";
+		ethernet@40028000 {
 			reg = <0x40028000 0x8000>;
-			interrupts = <61 0>;
-			clock-names = "stmmaceth", "mac-clk-tx",
-				      "mac-clk-rx", "mac-clk-ptp";
-			clocks = <&rcc STM32_CLOCK(AHB1, 25U)>,
-				 <&rcc STM32_CLOCK(AHB1, 26U)>,
-				 <&rcc STM32_CLOCK(AHB1, 27U)>,
-				 <&rcc STM32_CLOCK(AHB1, 28U)>;
-			status = "disabled";
+			compatible = "st,stm32-ethernet-controller";
+			clock-names = "stm-eth";
+			clocks = <&rcc STM32_CLOCK(AHB1, 25)>;
+
+			mac: ethernet {
+				compatible = "st,stm32-ethernet";
+				interrupts = <61 0>;
+				clock-names = "mac-clk-tx", "mac-clk-rx",
+					      "mac-clk-ptp";
+				clocks = <&rcc STM32_CLOCK(AHB1, 26)>,
+					 <&rcc STM32_CLOCK(AHB1, 27)>,
+					 <&rcc STM32_CLOCK(AHB1, 28)>;
+				status = "disabled";
+			};
+
+			mdio: mdio {
+				compatible = "st,stm32-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 	};
 };
diff --git a/dts/arm/st/f3/stm32f3.dtsi b/dts/arm/st/f3/stm32f3.dtsi
index 435877e136e..2cdfebaf03f 100644
--- a/dts/arm/st/f3/stm32f3.dtsi
+++ b/dts/arm/st/f3/stm32f3.dtsi
@@ -258,6 +258,7 @@
 			interrupt-names = "usb";
 			num-bidir-endpoints = <8>;
 			ram-size = <512>;
+			maximum-speed = "full-speed";
 			phys = <&usb_fs_phy>;
 			clocks = <&rcc STM32_CLOCK(APB1, 23U)>;
 			status = "disabled";
diff --git a/dts/arm/st/f3/stm32f303Xe.dtsi b/dts/arm/st/f3/stm32f303Xe.dtsi
index bb04ee099ae..b997e0fb4ff 100644
--- a/dts/arm/st/f3/stm32f303Xe.dtsi
+++ b/dts/arm/st/f3/stm32f303Xe.dtsi
@@ -41,5 +41,21 @@
 				status = "disabled";
 			};
 		};
+
+		i2c3: i2c@4007800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40007800 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 30)>,
+				 /* I2C clock source should always be defined,
+				  * even for the default value
+				  */
+				 <&rcc STM32_SRC_SYSCLK I2C3_SEL(1)>;
+			interrupts = <72 0>, <73 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+		};
 	};
 };
diff --git a/dts/arm/st/f4/stm32f4.dtsi b/dts/arm/st/f4/stm32f4.dtsi
index e05aaf7b090..e20a50dcbec 100644
--- a/dts/arm/st/f4/stm32f4.dtsi
+++ b/dts/arm/st/f4/stm32f4.dtsi
@@ -18,6 +18,7 @@
 #include <zephyr/dt-bindings/adc/stm32f4_adc.h>
 #include <zephyr/dt-bindings/reset/stm32f2_4_7_reset.h>
 #include <zephyr/dt-bindings/sensor/qdec_stm32.h>
+#include <zephyr/dt-bindings/power/stm32_pwr.h>
 #include <freq.h>
 
 / {
@@ -586,6 +587,22 @@
 		};
 	};
 
+	pwr: power@40007000 {
+		compatible = "st,stm32-pwr";
+		reg = <0x40007000 0x400>; /* PWR register bank */
+		status = "disabled";
+
+		wkup-pins-nb = <1>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		wkup-pin@1 {
+			reg = <0x1>;
+			wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_NOT_MUXED>;
+		};
+	};
+
 	die_temp: dietemp {
 		compatible = "st,stm32-temp-cal";
 		ts-cal1-addr = <0x1FFF7A2C>;
diff --git a/dts/arm/st/f4/stm32f401.dtsi b/dts/arm/st/f4/stm32f401.dtsi
index eda9b1e4a98..e113144d2e1 100644
--- a/dts/arm/st/f4/stm32f401.dtsi
+++ b/dts/arm/st/f4/stm32f401.dtsi
@@ -55,8 +55,8 @@
 			reg = <0x40003800 0x400>;
 			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <36 5>;
-			dmas = <&dma1 4 0 0x400 0x3
-				&dma1 3 0 0x400 0x3>;
+			dmas = <&dma1 4 0 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL
+				&dma1 3 0 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>;
 			dma-names = "tx", "rx";
 			status = "disabled";
 		};
@@ -68,8 +68,8 @@
 			reg = <0x40003c00 0x400>;
 			clocks = <&rcc STM32_CLOCK(APB1, 15U)>;
 			interrupts = <51 5>;
-			dmas = <&dma1 5 0 0x400 0x3
-				&dma1 0 0 0x400 0x3>;
+			dmas = <&dma1 5 0 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL
+				&dma1 0 0 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>;
 			dma-names = "tx", "rx";
 			status = "disabled";
 		};
diff --git a/dts/arm/st/f4/stm32f401Xd.dtsi b/dts/arm/st/f4/stm32f401Xd.dtsi
new file mode 100644
index 00000000000..b15480221f4
--- /dev/null
+++ b/dts/arm/st/f4/stm32f401Xd.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025 Cirrus Logic, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f401.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(96)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(384)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f405.dtsi b/dts/arm/st/f4/stm32f405.dtsi
index 9ae59cb70e2..76a19b808da 100644
--- a/dts/arm/st/f4/stm32f405.dtsi
+++ b/dts/arm/st/f4/stm32f405.dtsi
@@ -220,7 +220,7 @@
 			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
 			/* also enabling clock for can1 (master instance) */
-			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
 			master-can-reg = <0x40006400>;
 			status = "disabled";
 		};
diff --git a/dts/arm/st/f4/stm32f407.dtsi b/dts/arm/st/f4/stm32f407.dtsi
index 8ced67aaf26..f4ec4a6a128 100644
--- a/dts/arm/st/f4/stm32f407.dtsi
+++ b/dts/arm/st/f4/stm32f407.dtsi
@@ -10,17 +10,29 @@
 	soc {
 		compatible = "st,stm32f407", "st,stm32f4", "simple-bus";
 
-		mac: ethernet@40028000 {
-			compatible = "st,stm32-ethernet";
+		ethernet@40028000 {
 			reg = <0x40028000 0x8000>;
-			interrupts = <61 0>;
-			clock-names = "stmmaceth", "mac-clk-tx",
-				      "mac-clk-rx", "mac-clk-ptp";
-			clocks = <&rcc STM32_CLOCK(AHB1, 25U)>,
-				 <&rcc STM32_CLOCK(AHB1, 26U)>,
-				 <&rcc STM32_CLOCK(AHB1, 27U)>,
-				 <&rcc STM32_CLOCK(AHB1, 28U)>;
-			status = "disabled";
+			compatible = "st,stm32-ethernet-controller";
+			clock-names = "stm-eth";
+			clocks = <&rcc STM32_CLOCK(AHB1, 25)>;
+
+			mac: ethernet {
+				compatible = "st,stm32-ethernet";
+				interrupts = <61 0>;
+				clock-names = "mac-clk-tx", "mac-clk-rx",
+					      "mac-clk-ptp";
+				clocks = <&rcc STM32_CLOCK(AHB1, 26)>,
+					 <&rcc STM32_CLOCK(AHB1, 27)>,
+					 <&rcc STM32_CLOCK(AHB1, 28)>;
+				status = "disabled";
+			};
+
+			mdio: mdio {
+				compatible = "st,stm32-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 	};
 };
diff --git a/dts/arm/st/f4/stm32f410.dtsi b/dts/arm/st/f4/stm32f410.dtsi
index cd98599212a..0f149a98e8c 100644
--- a/dts/arm/st/f4/stm32f410.dtsi
+++ b/dts/arm/st/f4/stm32f410.dtsi
@@ -42,8 +42,8 @@
 			reg = <0x40013000 0x400>;
 			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
 			interrupts = <35 5>;
-			dmas = <&dma2 3 3 0x400 0x3
-				&dma2 2 3 0x400 0x3>;
+			dmas = <&dma2 3 3 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL
+				&dma2 2 3 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>;
 			dma-names = "tx", "rx";
 			status = "disabled";
 		};
@@ -55,8 +55,8 @@
 			reg = <0x40003800 0x400>;
 			clocks = <&rcc STM32_CLOCK(APB1, 14U)>;
 			interrupts = <36 5>;
-			dmas = <&dma1 4 0 0x400 0x3
-				&dma1 3 0 0x400 0x3>;
+			dmas = <&dma1 4 0 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL
+				&dma1 3 0 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>;
 			dma-names = "tx", "rx";
 			status = "disabled";
 		};
@@ -68,8 +68,8 @@
 			reg = <0x40015000 0x400>;
 			clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
 			interrupts = <85 5>;
-			dmas = <&dma2 6 7 0x400 0x3
-				&dma2 5 7 0x400 0x3>;
+			dmas = <&dma2 6 7 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL
+				&dma2 5 7 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>;
 			dma-names = "tx", "rx";
 			status = "disabled";
 		};
diff --git a/dts/arm/st/f4/stm32f411.dtsi b/dts/arm/st/f4/stm32f411.dtsi
index 8b1cec90893..b0dfddd40ef 100644
--- a/dts/arm/st/f4/stm32f411.dtsi
+++ b/dts/arm/st/f4/stm32f411.dtsi
@@ -35,8 +35,8 @@
 			reg = <0x40013000 0x400>;
 			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
 			interrupts = <35 5>;
-			dmas = <&dma2 3 3 0x400 0x3
-				&dma2 2 3 0x400 0x3>;
+			dmas = <&dma2 3 3 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL
+				&dma2 2 3 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>;
 			dma-names = "tx", "rx";
 			status = "disabled";
 		};
@@ -48,8 +48,8 @@
 			reg = <0x40013400 0x400>;
 			clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
 			interrupts = <84 5>;
-			dmas = <&dma2 1 4 0x400 0x3
-				&dma2 0 4 0x400 0x3>;
+			dmas = <&dma2 1 4 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL
+				&dma2 0 4 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>;
 			dma-names = "tx", "rx";
 			status = "disabled";
 		};
@@ -61,8 +61,8 @@
 			reg = <0x40015000 0x400>;
 			clocks = <&rcc STM32_CLOCK(APB2, 20U)>;
 			interrupts = <85 5>;
-			dmas = <&dma2 6 7 0x400 0x3
-				&dma2 5 7 0x400 0x3>;
+			dmas = <&dma2 6 7 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL
+				&dma2 5 7 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>;
 			dma-names = "tx", "rx";
 			status = "disabled";
 		};
diff --git a/dts/arm/st/f4/stm32f412.dtsi b/dts/arm/st/f4/stm32f412.dtsi
index b823ed9c717..73ba2591d41 100644
--- a/dts/arm/st/f4/stm32f412.dtsi
+++ b/dts/arm/st/f4/stm32f412.dtsi
@@ -84,8 +84,8 @@
 			reg = <0x40013400 0x400>;
 			clocks = <&rcc STM32_CLOCK(APB2, 13U)>;
 			interrupts = <84 5>;
-			dmas = <&dma2 1 4 0x400 0x3
-				&dma2 0 4 0x400 0x3>;
+			dmas = <&dma2 1 4 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL
+				&dma2 0 4 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>;
 			dma-names = "tx", "rx";
 			status = "disabled";
 		};
@@ -212,10 +212,10 @@
 				 <&rcc STM32_SRC_CK48 SDIO_SEL(0)>;
 		};
 
-		quadspi: quadspi@a0001000 {
+		quadspi: spi@a0001000 {
 			compatible = "st,stm32-qspi";
 			#address-cells = <0x1>;
-			#size-cells = <0x0>;
+			#size-cells = <0x1>;
 			reg = <0xa0001000 0x400>;
 			interrupts = <92 0>;
 			clocks = <&rcc STM32_CLOCK(AHB3, 1U)>;
@@ -237,7 +237,7 @@
 			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
 			/* also enabling clock for can1 (master instance) */
-			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
 			master-can-reg = <0x40006400>;
 			status = "disabled";
 		};
diff --git a/dts/arm/st/f4/stm32f439.dtsi b/dts/arm/st/f4/stm32f439.dtsi
new file mode 100644
index 00000000000..2144fb55ec5
--- /dev/null
+++ b/dts/arm/st/f4/stm32f439.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025, Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f429.dtsi>
+
+/ {
+	soc {
+		compatible = "st,stm32f439", "st,stm32f4", "simple-bus";
+
+		cryp: cryp@50060000 {
+			compatible = "st,stm32-cryp";
+			reg = <0x50060000 0x400>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 4U)>;
+			resets = <&rctl STM32_RESET(AHB2, 4U)>;
+			interrupts = <79 0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f439Xi.dtsi b/dts/arm/st/f4/stm32f439Xi.dtsi
new file mode 100644
index 00000000000..cc1c6a1276d
--- /dev/null
+++ b/dts/arm/st/f4/stm32f439Xi.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2025 Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f439.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "zephyr,memory-region", "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(192)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(2048)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f439vX.dtsi b/dts/arm/st/f4/stm32f439vX.dtsi
new file mode 100644
index 00000000000..ce43b8a80ff
--- /dev/null
+++ b/dts/arm/st/f4/stm32f439vX.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2025 Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f439.dtsi>
+
+/*
+ * spi5 and spi6 are present on all STM32F439XX SoCs except
+ * STM32F439vX SoCs, so they are defined in stm32f439.dtsi and deleted
+ * here.
+ */
+
+/delete-node/ &spi5;
+
+/delete-node/ &spi6;
diff --git a/dts/arm/st/f4/stm32f439vi.dtsi b/dts/arm/st/f4/stm32f439vi.dtsi
new file mode 100644
index 00000000000..837a6cac9d9
--- /dev/null
+++ b/dts/arm/st/f4/stm32f439vi.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2025 Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f439vX.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "zephyr,memory-region", "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(192)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(2048)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f446.dtsi b/dts/arm/st/f4/stm32f446.dtsi
index f2d3002324c..a015b1d87b4 100644
--- a/dts/arm/st/f4/stm32f446.dtsi
+++ b/dts/arm/st/f4/stm32f446.dtsi
@@ -25,8 +25,8 @@
 			reg = <0x40013000 0x400>;
 			clocks = <&rcc STM32_CLOCK(APB2, 12U)>;
 			interrupts = <35 5>;
-			dmas = <&dma2 3 3 0x400 0x3
-				&dma2 2 3 0x400 0x3>;
+			dmas = <&dma2 3 3 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL
+				&dma2 2 3 STM32_DMA_MEM_INC STM32_DMA_FIFO_FULL>;
 			dma-names = "tx", "rx";
 			status = "disabled";
 		};
@@ -73,7 +73,7 @@
 			interrupts = <63 0>, <64 0>, <65 0>, <66 0>;
 			interrupt-names = "TX", "RX0", "RX1", "SCE";
 			/* also enabling clock for can1 (master instance) */
-			clocks = <&rcc STM32_CLOCK(APB1, 26U)>;
+			clocks = <&rcc STM32_CLOCK_BUS_APB1 0x06000000>;
 			master-can-reg = <0x40006400>;
 			status = "disabled";
 		};
diff --git a/dts/arm/st/f4/stm32f479.dtsi b/dts/arm/st/f4/stm32f479.dtsi
new file mode 100644
index 00000000000..ca6b023b085
--- /dev/null
+++ b/dts/arm/st/f4/stm32f479.dtsi
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2025 Christopher Cichiwskyj
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/f4/stm32f469.dtsi>
+
+/ {
+	soc {
+		compatible = "st,stm32f479", "st,stm32f4", "simple-bus";
+
+		cryp: cryp@50060000 {
+			compatible = "st,stm32-cryp";
+			reg = <0x50060000 0x400>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 4)>;
+			interrupts = <79 0>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/dts/arm/st/f4/stm32f479Xi.dtsi b/dts/arm/st/f4/stm32f479Xi.dtsi
new file mode 100644
index 00000000000..42eb8c07afe
--- /dev/null
+++ b/dts/arm/st/f4/stm32f479Xi.dtsi
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2025 Christopher Cichiwskyj
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/f4/stm32f479.dtsi>
+
+/ {
+	ccm0: memory@10000000 {
+		compatible = "zephyr,memory-region", "st,stm32-ccm";
+		reg = <0x10000000 DT_SIZE_K(64)>;
+		zephyr,memory-region = "CCM";
+	};
+
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(320)>;
+	};
+
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(2048)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/f7/stm32f7.dtsi b/dts/arm/st/f7/stm32f7.dtsi
index 888433bbadf..5a3ec7d46cd 100644
--- a/dts/arm/st/f7/stm32f7.dtsi
+++ b/dts/arm/st/f7/stm32f7.dtsi
@@ -854,10 +854,10 @@
 			status = "disabled";
 		};
 
-		quadspi: quadspi@a0001000 {
+		quadspi: spi@a0001000 {
 			compatible = "st,stm32-qspi";
 			#address-cells = <0x1>;
-			#size-cells = <0x0>;
+			#size-cells = <0x1>;
 			reg = <0xa0001000 0x34>;
 			interrupts = <92 0>;
 			clocks = <&rcc STM32_CLOCK(AHB3, 1U)>;
diff --git a/dts/arm/st/f7/stm32f745.dtsi b/dts/arm/st/f7/stm32f745.dtsi
index 40f2b103629..999da8e962c 100644
--- a/dts/arm/st/f7/stm32f745.dtsi
+++ b/dts/arm/st/f7/stm32f745.dtsi
@@ -75,17 +75,29 @@
 			status = "disabled";
 		};
 
-		mac: ethernet@40028000 {
-			compatible = "st,stm32-ethernet";
+		ethernet@40028000 {
 			reg = <0x40028000 0x8000>;
-			interrupts = <61 0>;
-			clock-names = "stmmaceth", "mac-clk-tx",
-				      "mac-clk-rx", "mac-clk-ptp";
-			clocks = <&rcc STM32_CLOCK(AHB1, 25U)>,
-				 <&rcc STM32_CLOCK(AHB1, 26U)>,
-				 <&rcc STM32_CLOCK(AHB1, 27U)>,
-				 <&rcc STM32_CLOCK(AHB1, 28U)>;
-			status = "disabled";
+			compatible = "st,stm32-ethernet-controller";
+			clock-names = "stm-eth";
+			clocks = <&rcc STM32_CLOCK(AHB1, 25)>;
+
+			mac: ethernet {
+				compatible = "st,stm32-ethernet";
+				interrupts = <61 0>;
+				clock-names = "mac-clk-tx", "mac-clk-rx",
+					      "mac-clk-ptp";
+				clocks = <&rcc STM32_CLOCK(AHB1, 26)>,
+					 <&rcc STM32_CLOCK(AHB1, 27)>,
+					 <&rcc STM32_CLOCK(AHB1, 28)>;
+				status = "disabled";
+			};
+
+			mdio: mdio {
+				compatible = "st,stm32-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 	};
 
diff --git a/dts/arm/st/f7/stm32f765.dtsi b/dts/arm/st/f7/stm32f765.dtsi
index d8c62d3bf27..a1148f110ca 100644
--- a/dts/arm/st/f7/stm32f765.dtsi
+++ b/dts/arm/st/f7/stm32f765.dtsi
@@ -68,17 +68,29 @@
 			status = "disabled";
 		};
 
-		mac: ethernet@40028000 {
-			compatible = "st,stm32-ethernet";
+		ethernet@40028000 {
 			reg = <0x40028000 0x8000>;
-			interrupts = <61 0>;
-			clock-names = "stmmaceth", "mac-clk-tx",
-				      "mac-clk-rx", "mac-clk-ptp";
-			clocks = <&rcc STM32_CLOCK(AHB1, 25U)>,
-				 <&rcc STM32_CLOCK(AHB1, 26U)>,
-				 <&rcc STM32_CLOCK(AHB1, 27U)>,
-				 <&rcc STM32_CLOCK(AHB1, 28U)>;
-			status = "disabled";
+			compatible = "st,stm32-ethernet-controller";
+			clock-names = "stm-eth";
+			clocks = <&rcc STM32_CLOCK(AHB1, 25)>;
+
+			mac: ethernet {
+				compatible = "st,stm32-ethernet";
+				interrupts = <61 0>;
+				clock-names = "mac-clk-tx", "mac-clk-rx",
+					      "mac-clk-ptp";
+				clocks = <&rcc STM32_CLOCK(AHB1, 26)>,
+					 <&rcc STM32_CLOCK(AHB1, 27)>,
+					 <&rcc STM32_CLOCK(AHB1, 28)>;
+				status = "disabled";
+			};
+
+			mdio: mdio {
+				compatible = "st,stm32-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
 		};
 
 		sdmmc2: sdmmc@40011c00 {
diff --git a/dts/arm/st/g0/stm32g0b0.dtsi b/dts/arm/st/g0/stm32g0b0.dtsi
index b0afe8d1ed9..9e8477c33ad 100644
--- a/dts/arm/st/g0/stm32g0b0.dtsi
+++ b/dts/arm/st/g0/stm32g0b0.dtsi
@@ -99,6 +99,7 @@
 			interrupt-names = "usb";
 			num-bidir-endpoints = <8>;
 			ram-size = <2048>;
+			maximum-speed = "full-speed";
 			phys = <&usb_fs_phy>;
 			clocks = <&rcc STM32_CLOCK(APB1, 13U)>,
 				 <&rcc STM32_SRC_HSI48 USB_SEL(0)>;
diff --git a/dts/arm/st/g0/stm32g0b1.dtsi b/dts/arm/st/g0/stm32g0b1.dtsi
index bc621076b31..4a1bb1065f4 100644
--- a/dts/arm/st/g0/stm32g0b1.dtsi
+++ b/dts/arm/st/g0/stm32g0b1.dtsi
@@ -143,6 +143,7 @@
 			interrupt-names = "usb";
 			num-bidir-endpoints = <8>;
 			ram-size = <2048>;
+			maximum-speed = "full-speed";
 			phys = <&usb_fs_phy>;
 			clocks = <&rcc STM32_CLOCK(APB1, 13U)>,
 				 <&rcc STM32_SRC_HSI48 USB_SEL(0)>;
diff --git a/dts/arm/st/g4/stm32g4.dtsi b/dts/arm/st/g4/stm32g4.dtsi
index 20d3d38df39..7e94481d9a5 100644
--- a/dts/arm/st/g4/stm32g4.dtsi
+++ b/dts/arm/st/g4/stm32g4.dtsi
@@ -621,6 +621,7 @@
 			interrupt-names = "usb", "usbhp";
 			num-bidir-endpoints = <8>;
 			ram-size = <1024>;
+			maximum-speed = "full-speed";
 			phys = <&usb_fs_phy>;
 			clocks = <&rcc STM32_CLOCK(APB1, 23U)>,
 				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
diff --git a/dts/arm/st/h5/stm32h5.dtsi b/dts/arm/st/h5/stm32h5.dtsi
index 534551943f7..3fcd51acff0 100644
--- a/dts/arm/st/h5/stm32h5.dtsi
+++ b/dts/arm/st/h5/stm32h5.dtsi
@@ -39,6 +39,15 @@
 				reg = <0xe000ed90 0x40>;
 			};
 		};
+
+		power-states {
+			stop: state0 {
+				compatible = "zephyr,power-state";
+				power-state-name = "suspend-to-idle";
+				substate-id = <1>;
+				min-residency-us = <20>;
+			};
+		};
 	};
 
 	clocks {
@@ -137,15 +146,6 @@
 			status = "disabled";
 		};
 
-		power-states {
-			stop: state0 {
-				compatible = "zephyr,power-state";
-				power-state-name = "suspend-to-idle";
-				substate-id = <1>;
-				min-residency-us = <20>;
-			};
-		};
-
 		rcc: rcc@44020c00 {
 			compatible = "st,stm32u5-rcc";
 			clocks-controller;
@@ -538,15 +538,20 @@
 			status = "disabled";
 		};
 
-		mac: ethernet@40028000 {
-			compatible = "st,stm32h7-ethernet", "st,stm32-ethernet";
+		ethernet@40028000 {
 			reg = <0x40028000 0x8000>;
-			interrupts = <106 0>;
-			clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
-			clocks = <&rcc STM32_CLOCK(AHB1, 19U)>,
-				 <&rcc STM32_CLOCK(AHB1, 20U)>,
-				 <&rcc STM32_CLOCK(AHB1, 21U)>;
-			status = "disabled";
+			compatible = "st,stm32-ethernet-controller";
+			clock-names = "stm-eth";
+			clocks = <&rcc STM32_CLOCK(AHB1, 19)>;
+
+			mac: ethernet {
+				compatible = "st,stm32h7-ethernet", "st,stm32-ethernet";
+				interrupts = <106 0>;
+				clock-names = "mac-clk-tx", "mac-clk-rx";
+				clocks = <&rcc STM32_CLOCK(AHB1, 20)>,
+					 <&rcc STM32_CLOCK(AHB1, 21)>;
+				status = "disabled";
+			};
 
 			mdio: mdio {
 				compatible = "st,stm32-mdio";
@@ -635,6 +640,7 @@
 			interrupt-names = "usb";
 			num-bidir-endpoints = <8>;
 			ram-size = <2048>;
+			maximum-speed = "full-speed";
 			phys = <&usb_fs_phy>;
 			clocks = <&rcc STM32_CLOCK(APB2, 24U)>,
 				 <&rcc STM32_SRC_HSI48 USB_SEL(3)>;
diff --git a/dts/arm/st/h5/stm32h562.dtsi b/dts/arm/st/h5/stm32h562.dtsi
index 4b9bc9acf09..a8fe1bce5e2 100644
--- a/dts/arm/st/h5/stm32h562.dtsi
+++ b/dts/arm/st/h5/stm32h562.dtsi
@@ -258,7 +258,7 @@
 			status = "disabled";
 		};
 
-		xspi1: xspi@47001400 {
+		xspi1: spi@47001400 {
 			compatible = "st,stm32-xspi";
 			reg = <0x47001400 0x400>;
 			interrupts = <78 0>;
@@ -266,7 +266,7 @@
 			clocks = <&rcc STM32_CLOCK(AHB4, 20U)>,
 				<&rcc STM32_SRC_PLL1_Q OCTOSPI1_SEL(1)>;
 			#address-cells = <1>;
-			#size-cells = <0>;
+			#size-cells = <1>;
 			status = "disabled";
 		};
 
@@ -329,6 +329,22 @@
 			};
 		};
 
+		timers8: timers@40013400 {
+			compatible = "st,stm32-timers";
+			reg = <0x40013400 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB2, 13)>;
+			resets = <&rctl STM32_RESET(APB2, 13)>;
+			interrupts = <65 0>, <66 0>, <67 0>, <68 0>;
+			interrupt-names = "brk", "up", "trgcom", "cc";
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				#pwm-cells = <3>;
+			};
+		};
+
 		timers12: timers@40001800 {
 			compatible = "st,stm32-timers";
 			reg = <0x40001800 0x400>;
diff --git a/dts/arm/st/h5/stm32h562Xg.dtsi b/dts/arm/st/h5/stm32h562Xg.dtsi
new file mode 100644
index 00000000000..969c61d5d9c
--- /dev/null
+++ b/dts/arm/st/h5/stm32h562Xg.dtsi
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2025 Kacper Brzostowski
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/h5/stm32h562.dtsi>
+
+/ {
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_M(1)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/h7/stm32h7.dtsi b/dts/arm/st/h7/stm32h7.dtsi
index 57faa3db133..409d0bb1edf 100644
--- a/dts/arm/st/h7/stm32h7.dtsi
+++ b/dts/arm/st/h7/stm32h7.dtsi
@@ -1025,15 +1025,20 @@
 			status = "disabled";
 		};
 
-		mac: ethernet@40028000 {
-			compatible = "st,stm32h7-ethernet", "st,stm32-ethernet";
+		ethernet@40028000 {
 			reg = <0x40028000 0x8000>;
-			interrupts = <61 0>;
-			clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
-			clocks = <&rcc STM32_CLOCK(AHB1, 15U)>,
-				 <&rcc STM32_CLOCK(AHB1, 16U)>,
-				 <&rcc STM32_CLOCK(AHB1, 17U)>;
-			status = "disabled";
+			compatible = "st,stm32-ethernet-controller";
+			clock-names = "stm-eth";
+			clocks = <&rcc STM32_CLOCK(AHB1, 15)>;
+
+			mac: ethernet {
+				compatible = "st,stm32h7-ethernet", "st,stm32-ethernet";
+				interrupts = <61 0>;
+				clock-names = "mac-clk-tx", "mac-clk-rx";
+				clocks = <&rcc STM32_CLOCK(AHB1, 16)>,
+					 <&rcc STM32_CLOCK(AHB1, 17)>;
+				status = "disabled";
+			};
 
 			mdio: mdio {
 				compatible = "st,stm32-mdio";
@@ -1065,10 +1070,10 @@
 			status = "disabled";
 		};
 
-		quadspi: quadspi@52005000 {
+		quadspi: spi@52005000 {
 			compatible = "st,stm32-qspi";
 			#address-cells = <0x1>;
-			#size-cells = <0x0>;
+			#size-cells = <0x1>;
 			reg = <0x52005000 0x34>;
 			interrupts = <92 0>;
 			clocks = <&rcc STM32_CLOCK(AHB3, 14U)>;
diff --git a/dts/arm/st/h7/stm32h723.dtsi b/dts/arm/st/h7/stm32h723.dtsi
index 43209add1b5..a7fee953973 100644
--- a/dts/arm/st/h7/stm32h723.dtsi
+++ b/dts/arm/st/h7/stm32h723.dtsi
@@ -89,11 +89,11 @@
 			interrupts = <88 0>, <89 0>;
 			interrupt-names = "ltdc", "ltdc_er";
 			clocks = <&rcc STM32_CLOCK(APB3, 3U)>;
-			resets = <&rctl STM32_RESET(APB3, 4U)>;
+			resets = <&rctl STM32_RESET(APB3, 3U)>;
 			status = "disabled";
 		};
 
-		octospi1: octospi@52005000 {
+		octospi1: spi@52005000 {
 			compatible = "st,stm32-ospi";
 			reg = <0x52005000 0x1000>;
 			interrupts = <92 0>;
@@ -101,11 +101,11 @@
 			clocks = <&rcc STM32_CLOCK(AHB3, 14U)>,
 				<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
 			#address-cells = <1>;
-			#size-cells = <0>;
+			#size-cells = <1>;
 			status = "disabled";
 		};
 
-		octospi2: octospi@5200a000 {
+		octospi2: spi@5200a000 {
 			compatible = "st,stm32-ospi";
 			reg = <0x5200a000 0x1000>;
 			interrupts = <150 0>;
@@ -113,7 +113,7 @@
 			clocks = <&rcc STM32_CLOCK(AHB3, 19U)>,
 				<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
 			#address-cells = <1>;
-			#size-cells = <0>;
+			#size-cells = <1>;
 			status = "disabled";
 		};
 
diff --git a/dts/arm/st/h7/stm32h743.dtsi b/dts/arm/st/h7/stm32h743.dtsi
index 114db6e7c1e..f6b285dd18a 100644
--- a/dts/arm/st/h7/stm32h743.dtsi
+++ b/dts/arm/st/h7/stm32h743.dtsi
@@ -49,7 +49,7 @@
 			interrupts = <88 0>, <89 0>;
 			interrupt-names = "ltdc", "ltdc_er";
 			clocks = <&rcc STM32_CLOCK(APB3, 3U)>;
-			resets = <&rctl STM32_RESET(APB3, 4U)>;
+			resets = <&rctl STM32_RESET(APB3, 3U)>;
 			status = "disabled";
 		};
 
diff --git a/dts/arm/st/h7/stm32h745.dtsi b/dts/arm/st/h7/stm32h745.dtsi
index 294fd02c502..0eb82817506 100644
--- a/dts/arm/st/h7/stm32h745.dtsi
+++ b/dts/arm/st/h7/stm32h745.dtsi
@@ -42,7 +42,7 @@
 			interrupts = <88 0>, <89 0>;
 			interrupt-names = "ltdc", "ltdc_er";
 			clocks = <&rcc STM32_CLOCK(APB3, 3U)>;
-			resets = <&rctl STM32_RESET(APB3, 4U)>;
+			resets = <&rctl STM32_RESET(APB3, 3U)>;
 			status = "disabled";
 		};
 
diff --git a/dts/arm/st/h7/stm32h7a3.dtsi b/dts/arm/st/h7/stm32h7a3.dtsi
index 4721872a3b1..2ce9681c0b7 100644
--- a/dts/arm/st/h7/stm32h7a3.dtsi
+++ b/dts/arm/st/h7/stm32h7a3.dtsi
@@ -52,11 +52,11 @@
 			interrupts = <88 0>, <89 0>;
 			interrupt-names = "ltdc", "ltdc_er";
 			clocks = <&rcc STM32_CLOCK(APB3, 3U)>;
-			resets = <&rctl STM32_RESET(APB3, 4U)>;
+			resets = <&rctl STM32_RESET(APB3, 3U)>;
 			status = "disabled";
 		};
 
-		octospi1: octospi@52005000 {
+		octospi1: spi@52005000 {
 			compatible = "st,stm32-ospi";
 			reg = <0x52005000 0x1000>;
 			interrupts = <92 0>;
@@ -64,11 +64,11 @@
 			clocks = <&rcc STM32_CLOCK(AHB3, 14U)>,
 				<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
 			#address-cells = <1>;
-			#size-cells = <0>;
+			#size-cells = <1>;
 			status = "disabled";
 		};
 
-		octospi2: octospi@5200a000 {
+		octospi2: spi@5200a000 {
 			compatible = "st,stm32-ospi";
 			reg = <0x5200a000 0x1000>;
 			interrupts = <150 0>;
@@ -76,7 +76,7 @@
 			clocks = <&rcc STM32_CLOCK(AHB3, 19U)>,
 				<&rcc STM32_SRC_PLL1_Q OSPI_SEL(1)>;
 			#address-cells = <1>;
-			#size-cells = <0>;
+			#size-cells = <1>;
 			status = "disabled";
 		};
 
@@ -87,7 +87,8 @@
 			reg = <0x58001400 0x400>;
 			clocks = <&rcc STM32_CLOCK(APB4, 5U)>,
 				 <&rcc STM32_SRC_PLL1_Q SPI6_SEL(0)>;
-			dmas = <&dmamux2 0 12 0x20440 &dmamux2 1 11 0x20480>;
+			dmas = <&dmamux2 0 12 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)
+				&dmamux2 1 11 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
 			dma-names = "tx", "rx";
 			interrupts = <86 0>;
 			status = "disabled";
diff --git a/dts/arm/st/h7rs/stm32h7rs.dtsi b/dts/arm/st/h7rs/stm32h7rs.dtsi
index 25ba574d5b1..e41e465c7eb 100644
--- a/dts/arm/st/h7rs/stm32h7rs.dtsi
+++ b/dts/arm/st/h7rs/stm32h7rs.dtsi
@@ -776,6 +776,25 @@
 			interrupts = <37 0>;
 			status = "disabled";
 		};
+
+		usbotg_fs: usb@40080000 {
+			compatible = "st,stm32-otgfs";
+			reg = <0x40080000 0x40000>;
+			interrupts = <112 0>;
+			interrupt-names = "otgfs";
+			num-bidir-endpoints = <6>;
+			ram-size = <1280>;
+			maximum-speed = "full-speed";
+			phys = <&otgfs_phy>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 27U)>,
+				 <&rcc STM32_SRC_HSI48 OTGFS_SEL(0)>;
+			status = "disabled";
+		};
+	};
+
+	otgfs_phy: otgfs_phy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
 	};
 
 	die_temp: dietemp {
diff --git a/dts/arm/st/l0/stm32l071X8.dtsi b/dts/arm/st/l0/stm32l071X8.dtsi
new file mode 100644
index 00000000000..4f0fe482c0f
--- /dev/null
+++ b/dts/arm/st/l0/stm32l071X8.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025 Vixay Phimmasane
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l0/stm32l071.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(20)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(64)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l0/stm32l071Xz.dtsi b/dts/arm/st/l0/stm32l071Xz.dtsi
new file mode 100644
index 00000000000..78566a5d62b
--- /dev/null
+++ b/dts/arm/st/l0/stm32l071Xz.dtsi
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025 Vixay Phimmasane
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/l0/stm32l071.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(20)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(192)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/l4/stm32l4.dtsi b/dts/arm/st/l4/stm32l4.dtsi
index 6ddcbd1da9e..f127a5deb31 100644
--- a/dts/arm/st/l4/stm32l4.dtsi
+++ b/dts/arm/st/l4/stm32l4.dtsi
@@ -263,10 +263,10 @@
 			status = "disabled";
 		};
 
-		quadspi: quadspi@a0001000 {
+		quadspi: spi@a0001000 {
 			compatible = "st,stm32-qspi";
 			#address-cells = <1>;
-			#size-cells = <0>;
+			#size-cells = <1>;
 			reg = <0xa0001000 0x400>;
 			interrupts = <71 0>;
 			clocks = <&rcc STM32_CLOCK(AHB3, 8U)>;
diff --git a/dts/arm/st/l4/stm32l4p5.dtsi b/dts/arm/st/l4/stm32l4p5.dtsi
index 3746f46eceb..2636de3abd5 100644
--- a/dts/arm/st/l4/stm32l4p5.dtsi
+++ b/dts/arm/st/l4/stm32l4p5.dtsi
@@ -363,7 +363,7 @@
 			#io-channel-cells = <1>;
 		};
 
-		octospi1: octospi@a0001000 {
+		octospi1: spi@a0001000 {
 			compatible = "st,stm32-ospi";
 			reg = <0xa0001000 0x400>;
 			interrupts = <71 0>;
@@ -373,11 +373,11 @@
 				<&rcc STM32_CLOCK(AHB2, 20U)>;
 
 			#address-cells = <1>;
-			#size-cells = <0>;
+			#size-cells = <1>;
 			status = "disabled";
 		};
 
-		octospi2: octospi@a0001400 {
+		octospi2: spi@a0001400 {
 			compatible = "st,stm32-ospi";
 			reg = <0xa0001400 0x400>;
 			interrupts = <76 0>;
@@ -387,7 +387,7 @@
 				<&rcc STM32_CLOCK(AHB2, 20U)>;
 
 			#address-cells = <1>;
-			#size-cells = <0>;
+			#size-cells = <1>;
 			status = "disabled";
 		};
 	};
diff --git a/dts/arm/st/l4/stm32l4r5Xi.dtsi b/dts/arm/st/l4/stm32l4r5Xi.dtsi
index 5da6f035e76..b5318d1e40d 100644
--- a/dts/arm/st/l4/stm32l4r5Xi.dtsi
+++ b/dts/arm/st/l4/stm32l4r5Xi.dtsi
@@ -20,22 +20,22 @@
 
 &pwr {
 	wkup-pin@1 {
-		wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>;
+		wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_NOT_MUXED>;
 	};
 
 	wkup-pin@2 {
-		wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_SRC_0>;
+		wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_NOT_MUXED>;
 	};
 
 	wkup-pin@3 {
-		wkup-gpios = <&gpioe 6 STM32_PWR_WKUP_PIN_SRC_0>;
+		wkup-gpios = <&gpioe 6 STM32_PWR_WKUP_PIN_NOT_MUXED>;
 	};
 
 	wkup-pin@4 {
-		wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_SRC_0>;
+		wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_NOT_MUXED>;
 	};
 
 	wkup-pin@5 {
-		wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_SRC_0>;
+		wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_NOT_MUXED>;
 	};
 };
diff --git a/dts/arm/st/l5/stm32l5.dtsi b/dts/arm/st/l5/stm32l5.dtsi
index fc13e030c7a..176a6e23e8b 100644
--- a/dts/arm/st/l5/stm32l5.dtsi
+++ b/dts/arm/st/l5/stm32l5.dtsi
@@ -432,7 +432,7 @@
 			status = "disabled";
 		};
 
-		octospi1: octospi@44021000 {
+		octospi1: spi@44021000 {
 			compatible = "st,stm32-ospi";
 			reg = <0x44021000 0x400>;
 			interrupts = <76 0>;
@@ -440,7 +440,7 @@
 			clocks = <&rcc STM32_CLOCK(AHB3, 8U)>,
 					<&rcc STM32_SRC_SYSCLK OSPI_SEL(0)>;
 			#address-cells = <1>;
-			#size-cells = <0>;
+			#size-cells = <1>;
 			status = "disabled";
 		};
 
@@ -693,6 +693,7 @@
 			interrupt-names = "usb";
 			num-bidir-endpoints = <8>;
 			ram-size = <1024>;
+			maximum-speed = "full-speed";
 			status = "disabled";
 			clocks = <&rcc STM32_CLOCK(APB1_2, 21U)>,
 				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
diff --git a/dts/arm/st/mp13/stm32mp13.dtsi b/dts/arm/st/mp13/stm32mp13.dtsi
new file mode 100644
index 00000000000..d781890d1b5
--- /dev/null
+++ b/dts/arm/st/mp13/stm32mp13.dtsi
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-a.dtsi>
+
+#include <freq.h>
+#include <mem.h>
+
+#include <zephyr/dt-bindings/clock/stm32mp13_clock.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+#include <zephyr/dt-bindings/reset/stm32mp13_reset.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+		};
+	};
+
+	soc {
+		interrupt-parent = <&gic>;
+
+		sysram: memory@2ffe0000  {
+			compatible = "mmio-sram";
+			reg = <0x2FFE0000 DT_SIZE_K(128)>;
+		};
+
+		uart4: serial@40010000 {
+			compatible = "st,stm32-uart";
+			reg = <0x40010000 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 16)>;
+			resets = <&rctl STM32_RESET(APB1, 16)>;
+			interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			status = "disabled";
+		};
+
+		rcc: rcc@50000000 {
+			compatible = "st,stm32-rcc";
+			reg = <0x50000000 0x1000>;
+			#clock-cells = <2>;
+
+			rctl: reset-controller {
+				compatible = "st,stm32-rcc-rctl";
+				#reset-cells = <1>;
+				set-bit-to-deassert;
+			};
+		};
+
+		pinctrl: pin-controller@50002000 {
+			compatible = "st,stm32-pinctrl";
+			reg = <0x50002000 0x9000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			gpioa: gpio@50002000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50002000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 0)>;
+			};
+
+			gpiob: gpio@50003000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50003000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 1)>;
+			};
+
+			gpioc: gpio@50004000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50004000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 2)>;
+			};
+
+			gpiod: gpio@50005000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50005000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 3)>;
+			};
+
+			gpioe: gpio@50006000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50006000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 4)>;
+			};
+
+			gpiof: gpio@50007000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50007000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 5)>;
+			};
+
+			gpiog: gpio@50008000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50008000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 6)>;
+			};
+
+			gpioh: gpio@50009000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x50009000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 7)>;
+			};
+
+			gpioi: gpio@5000a000 {
+				compatible = "st,stm32-gpio";
+				reg = <0x5000a000 0x400>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 8)>;
+			};
+		};
+
+		exti: interrupt-controller@5000d000 {
+			compatible =  "st,stm32g0-exti","st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			#address-cells = <1>;
+			reg = <0x5000D000 0x400>;
+			num-lines = <16>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 7 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 8 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 9 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 24 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 65 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 66 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 67 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 68 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 43 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 77 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 78 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 106 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				     <GIC_SPI 109 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "line0", "line1", "line2", "line3",
+					  "line4", "line5", "line6", "line7",
+					  "line8", "line9", "line10", "line11",
+					  "line12", "line13", "line14", "line15";
+			line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
+				      <4 1>, <5 1>, <6 1>, <7 1>,
+				      <8 1>, <9 1>, <10 1>, <11 1>,
+				      <12 1>, <13 1>, <14 1>, <15 1>;
+		};
+	};
+
+	gic: gic@A0021000 {
+		compatible = "arm,gic-v2", "arm,gic";
+		reg = <0xA0021000 0x1000>,
+		      <0xA0022000 0x2000>;
+		interrupt-controller;
+		#interrupt-cells = <4>;
+		status = "okay";
+	};
+
+	ddr_code: memory@C0000000 {
+		compatible = "mmio-sram";
+		reg = <0xC0000000 0x10000000>;
+	};
+
+	ddr_data: memory@D0000000 {
+		compatible = "mmio-sram";
+		reg = <0xD0000000 0x10000000>;
+	};
+
+	clocks {
+
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			status = "disabled";
+		};
+
+		cpusw: cpusw {
+			#clock-cells = <0>;
+			compatible = "st,stm32mp13-cpu-clock-mux";
+			status = "disabled";
+		};
+
+		pll1: pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32mp13-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+	};
+};
diff --git a/dts/arm/st/mp13/stm32mp135.dtsi b/dts/arm/st/mp13/stm32mp135.dtsi
new file mode 100644
index 00000000000..4b754a69d58
--- /dev/null
+++ b/dts/arm/st/mp13/stm32mp135.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/mp13/stm32mp13.dtsi>
+
+/ {
+	soc {
+		compatible = "st,stm32mp135", "st,stm32mp13", "simple-bus";
+	};
+};
diff --git a/dts/arm/st/n6/stm32n6.dtsi b/dts/arm/st/n6/stm32n6.dtsi
new file mode 100644
index 00000000000..698acda6c2d
--- /dev/null
+++ b/dts/arm/st/n6/stm32n6.dtsi
@@ -0,0 +1,750 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv8.1-m.dtsi>
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/adc/stm32l4_adc.h>
+#include <zephyr/dt-bindings/clock/stm32n6_clock.h>
+#include <zephyr/dt-bindings/dma/stm32_dma.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/reset/stm32n6_reset.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+#include <zephyr/dt-bindings/memory-controller/stm32-fmc-nor-psram.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <freq.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m55";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8.1m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	axisram1: memory@34000000 {
+		compatible = "mmio-sram";
+	};
+
+	axisram2: memory@34180400 {
+		compatible = "mmio-sram";
+	};
+
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-hse-clock";
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "st,stm32h7-hsi-clock";
+			clock-frequency = <DT_FREQ_M(64)>;
+			status = "disabled";
+		};
+
+		clk_lse: clk-lse {
+			#clock-cells = <0>;
+			compatible = "st,stm32-lse-clock";
+			clock-frequency = <32768>;
+			driving-capability = <2>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(32)>;
+			status = "disabled";
+		};
+
+		pll1: pll: pll {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-pll-clock";
+			status = "disabled";
+		};
+
+		pll2: pll2 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-pll-clock";
+			status = "disabled";
+		};
+
+		pll3: pll3 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-pll-clock";
+			status = "disabled";
+		};
+
+		pll4: pll4 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-pll-clock";
+			status = "disabled";
+		};
+
+		cpusw: cpusw {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-cpu-clock-mux", "st,stm32-clock-mux";
+			status = "disabled";
+		};
+
+		perck: perck {
+			#clock-cells = <0>;
+			compatible = "st,stm32-clock-mux";
+			status = "disabled";
+		};
+
+		ic1: ic1 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic2: ic2 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic3: ic3 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic4: ic4 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic5: ic5 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic6: ic6 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic7: ic7 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic8: ic8 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic9: ic9 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic10: ic10 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic11: ic11 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic12: ic12 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic13: ic13 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic14: ic14 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic15: ic15 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic16: ic16 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic17: ic17 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic18: ic18 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic19: ic19 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+
+		ic20: ic20 {
+			#clock-cells = <0>;
+			compatible = "st,stm32n6-ic-clock-mux";
+			status = "disabled";
+		};
+	};
+
+	soc {
+		rcc: rcc@56028000 {
+			compatible = "st,stm32n6-rcc";
+			clocks-controller;
+			#clock-cells = <2>;
+			reg = <0x56028000 0x2000>;
+
+			rctl: reset-controller {
+				compatible = "st,stm32-rcc-rctl";
+				#reset-cells = <1>;
+			};
+		};
+
+		exti: interrupt-controller@56025000 {
+			compatible = "st,stm32g0-exti", "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			#address-cells = <1>;
+			reg = <0x56025000 0x400>;
+			num-lines = <16>;
+			interrupts = <20 0>, <21 0>, <22 0>, <23 0>,
+				     <24 0>, <25 0>, <26 0>, <27 0>,
+				     <28 0>, <29 0>, <30 0>, <31 0>,
+				     <32 0>, <33 0>, <34 0>, <35 0>;
+			interrupt-names = "line0", "line1", "line2", "line3",
+					  "line4", "line5", "line6", "line7",
+					  "line8", "line9", "line10", "line11",
+					  "line12", "line13", "line14", "line15";
+			line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
+				      <4 1>, <5 1>, <6 1>, <7 1>,
+				      <8 1>, <9 1>, <10 1>, <11 1>,
+				      <12 1>, <13 1>, <14 1>, <15 1>;
+		};
+
+		pinctrl: pin-controller@56020000 {
+			compatible = "st,stm32-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			reg = <0x56020000 0x2000>;
+
+			gpioa: gpio@56020000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x56020000 0x400>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 0)>;
+			};
+
+			gpiob: gpio@56020400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x56020400 0x400>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 1)>;
+			};
+
+			gpioc: gpio@56020800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x56020800 0x400>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 2)>;
+			};
+
+			gpiod: gpio@56020c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x56020c00 0x400>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 3)>;
+			};
+
+			gpioe: gpio@56021000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x56021000 0x400>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 4)>;
+			};
+
+			gpiof: gpio@56021400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x56021400 0x400>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 5)>;
+			};
+
+			gpiog: gpio@56021800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x56021800 0x400>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 6)>;
+			};
+
+			gpioh: gpio@56021c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x56021c00 0x400>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 7)>;
+			};
+
+			gpion: gpio@56023400 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x56023400 0x400>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 13)>;
+			};
+
+			gpioo: gpio@56023800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x56023800 0x400>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 14)>;
+			};
+
+			gpiop: gpio@56023c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x56023C00 0x400>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 15)>;
+			};
+
+			gpioq: gpio@56024000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x56024000 0x400>;
+				clocks = <&rcc STM32_CLOCK(AHB4, 16)>;
+			};
+		};
+
+		adc1: adc@50022000 {
+			compatible = "st,stm32n6-adc", "st,stm32-adc";
+			reg = <0x50022000 0x400>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 5)>;
+			interrupts = <46 0>;
+			status = "disabled";
+			#io-channel-cells = <1>;
+			resolutions = <STM32_ADC_RES(12, 0x00)
+				       STM32_ADC_RES(10, 0x01)
+				       STM32_ADC_RES(8, 0x02)
+				       STM32_ADC_RES(6, 0x03)>;
+			sampling-times = <2 3 7 12 14 47 247 1500>;
+			st,adc-sequencer = "FULLY_CONFIGURABLE";
+			st,adc-oversampler = "OVERSAMPLER_EXTENDED";
+		};
+
+		adc2: adc@50022100 {
+			compatible = "st,stm32n6-adc", "st,stm32-adc";
+			reg = <0x50022100 0x300>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 5)>;
+			interrupts = <46 0>;
+			status = "disabled";
+			#io-channel-cells = <1>;
+			resolutions = <STM32_ADC_RES(12, 0x00)
+				       STM32_ADC_RES(10, 0x01)
+				       STM32_ADC_RES(8, 0x02)
+				       STM32_ADC_RES(6, 0x03)>;
+			sampling-times = <2 3 7 12 14 47 247 1500>;
+			st,adc-sequencer = "FULLY_CONFIGURABLE";
+			st,adc-oversampler = "OVERSAMPLER_EXTENDED";
+		};
+
+		fdcan1: can@5000a000 {
+			compatible = "st,stm32h7-fdcan";
+			reg = <0x5000A000 0x400>, <0x5000C000 0xd54>;
+			reg-names = "m_can", "message_ram";
+			clocks = <&rcc STM32_CLOCK(APB1_2, 8)>;
+			interrupts = <180 0>, <181 0>, <186 0>;
+			interrupt-names = "int0", "int1", "calib";
+			bosch,mram-cfg = <0x0 28 8 3 3 0 3 3>;
+			status = "disabled";
+		};
+
+		fdcan2: can@5000a400 {
+			compatible = "st,stm32h7-fdcan";
+			reg = <0x5000A400 0x400>, <0x5000C000 0x1aa8>;
+			reg-names = "m_can", "message_ram";
+			clocks = <&rcc STM32_CLOCK(APB1_2, 8)>;
+			interrupts = <182 0>, <183 0>;
+			interrupt-names = "int0", "int1";
+			bosch,mram-cfg = <0xd54 28 8 3 3 0 3 3>;
+			status = "disabled";
+		};
+
+		fdcan3: can@5000e800 {
+			compatible = "st,stm32h7-fdcan";
+			reg = <0x5000E800 0x400>, <0x5000C000 0x2800>;
+			reg-names = "m_can", "message_ram";
+			clocks = <&rcc STM32_CLOCK(APB1_2, 8)>;
+			interrupts = <184 0>, <185 0>;
+			interrupt-names = "int0", "int1";
+			bosch,mram-cfg = <0x1aa8 28 8 3 3 0 3 3>;
+			status = "disabled";
+		};
+
+		usart1: serial@52001000 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x52001000 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB2, 4)>;
+			resets = <&rctl STM32_RESET(APB2, 4)>;
+			interrupts = <159 0>;
+			status = "disabled";
+		};
+
+		usart2: serial@50004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x50004400 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 17)>;
+			resets = <&rctl STM32_RESET(APB1L, 17)>;
+			interrupts = <160 0>;
+			status = "disabled";
+		};
+
+		usart3: serial@50004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x50004800 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18)>;
+			resets = <&rctl STM32_RESET(APB1L, 18)>;
+			interrupts = <161 0>;
+			status = "disabled";
+		};
+
+		uart4: serial@50004c00 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x50004C00 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19)>;
+			resets = <&rctl STM32_RESET(APB1L, 19)>;
+			interrupts = <162 0>;
+			status = "disabled";
+		};
+
+		uart5: serial@50005000 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x50005000 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 20)>;
+			resets = <&rctl STM32_RESET(APB1L, 20)>;
+			interrupts = <163 0>;
+			status = "disabled";
+		};
+
+		usart6: serial@52001400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x52001400 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB2, 5)>;
+			resets = <&rctl STM32_RESET(APB2, 5)>;
+			interrupts = <164 0>;
+			status = "disabled";
+		};
+
+		uart7: serial@50007800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x50007800 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 30)>;
+			resets = <&rctl STM32_RESET(APB1L, 30)>;
+			interrupts = <165 0>;
+			status = "disabled";
+		};
+
+		uart8: serial@50007c00 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x50007C00 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 31)>;
+			resets = <&rctl STM32_RESET(APB1L, 31)>;
+			interrupts = <166 0>;
+			status = "disabled";
+		};
+
+		uart9: serial@52001800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x52001800 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB2, 6)>;
+			resets = <&rctl STM32_RESET(APB2, 6)>;
+			interrupts = <167 0>;
+			status = "disabled";
+		};
+
+		usart10: serial@52001c00 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x52001C00 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB2, 7)>;
+			resets = <&rctl STM32_RESET(APB2, 7)>;
+			interrupts = <168 0>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@50005400 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x50005400 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 21)>;
+			interrupts = <100 0>, <101 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+		};
+
+		i2c2: i2c@50005800 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x50005800 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 22)>;
+			interrupts = <102 0>, <103 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+		};
+
+		i2c3: i2c@50005c00 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x50005C00 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 23)>;
+			interrupts = <104 0>, <105 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+		};
+
+		i2c4: i2c@56001c00 {
+			compatible = "st,stm32-i2c-v2";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x56001C00 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB4, 7)>;
+			interrupts = <106 0>, <107 0>;
+			interrupt-names = "event", "error";
+			status = "disabled";
+		};
+
+		spi1: spi@52003000 {
+			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x52003000 0x400>;
+			interrupts = <153 0>;
+			clocks = <&rcc STM32_CLOCK(APB2, 12)>;
+			status = "disabled";
+		};
+
+		spi2: spi@50003800 {
+			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x50003800 0x400>;
+			interrupts = <154 0>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14)>;
+			status = "disabled";
+		};
+
+		spi3: spi@50003c00 {
+			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x50003C00 0x400>;
+			interrupts = <155 0>;
+			clocks = <&rcc STM32_CLOCK(APB1, 15)>;
+			status = "disabled";
+		};
+
+		spi4: spi@52003400 {
+			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x52003400 0x400>;
+			interrupts = <156 0>;
+			clocks = <&rcc STM32_CLOCK(APB2, 13)>;
+			status = "disabled";
+		};
+
+		spi5: spi@52005000 {
+			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x52005000 0x400>;
+			interrupts = <157 0>;
+			clocks = <&rcc STM32_CLOCK(APB2, 20)>;
+			status = "disabled";
+		};
+
+		spi6: spi@56001400 {
+			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x56001400 0x400>;
+			interrupts = <158 0>;
+			clocks = <&rcc STM32_CLOCK(APB4, 5)>;
+			status = "disabled";
+		};
+
+		gpdma1: dma@50021000 {
+			compatible = "st,stm32u5-dma";
+			#dma-cells = <3>;
+			reg = <0x50021000 0x1000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 4)>;
+			interrupts = <84 0 85 0 86 0 87 0 88 0 89 0 90 0 91 0
+				      92 0 93 0 94 0 95 0 96 0 97 0 98 0 99 0>;
+			dma-channels = <16>;
+			dma-requests = <144>;
+			dma-offset = <0>;
+			status = "disabled";
+		};
+
+		ethernet@58036000 {
+			reg = <0x58036000 0x8000>;
+			compatible = "st,stm32-ethernet-controller";
+			clock-names = "stm-eth";
+			clocks = <&rcc STM32_CLOCK(AHB5, 22)>;
+
+			mac: ethernet {
+				compatible = "st,stm32n6-ethernet", "st,stm32h7-ethernet",
+					"st,stm32-ethernet";
+				interrupts = <179 0>;
+				clock-names = "mac-clk-tx", "mac-clk-rx";
+				clocks = <&rcc STM32_CLOCK(AHB5, 23)>,
+					 <&rcc STM32_CLOCK(AHB5, 24)>;
+				status = "disabled";
+			};
+
+			mdio: mdio {
+				compatible = "st,stm32-mdio";
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+			};
+		};
+
+		sdmmc1: sdmmc@58027000 {
+			compatible = "st,stm32-sdmmc";
+			reg = <0x58027000 0x1000>;
+			clocks = <&rcc STM32_CLOCK(AHB5, 8)>;
+			resets = <&rctl STM32_RESET(AHB5, 8)>;
+			interrupts = <174 0>;
+			status = "disabled";
+		};
+
+		sdmmc2: sdmmc@58026800 {
+			compatible = "st,stm32-sdmmc";
+			reg = <0x58026800 0x400>;
+			clocks = <&rcc STM32_CLOCK(AHB5, 7)>;
+			resets = <&rctl STM32_RESET(AHB5, 7)>;
+			interrupts = <175 0>;
+			status = "disabled";
+		};
+
+		xspi1: xspi@58025000 {
+			compatible = "st,stm32-xspi";
+			reg = <0x58025000 0x1000>;
+			interrupts = <170 0>;
+			clock-names = "xspix", "xspi-ker", "xspi-mgr";
+			clocks = <&rcc STM32_CLOCK(AHB5, 5)>,
+				 <&rcc STM32_SRC_HCLK5 XSPI1_SEL(0)>,
+				 <&rcc STM32_CLOCK(AHB5, 13)>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+		};
+
+		xspi2: spi@5802a000 {
+			compatible = "st,stm32-xspi";
+			reg = <0x5802A000 0x1000>;
+			interrupts = <171 0>;
+			clock-names = "xspix", "xspi-ker", "xspi-mgr";
+			clocks = <&rcc STM32_CLOCK(AHB5, 12)>,
+				 <&rcc STM32_SRC_HCLK5 XSPI2_SEL(0)>,
+				 <&rcc STM32_CLOCK(AHB5, 13)>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "disabled";
+		};
+
+		usbotg_hs1: otghs@58040000 {
+			compatible = "st,stm32n6-otghs", "st,stm32-otghs";
+			reg = <0x58040000 0x2000>;
+			interrupts = <177 0>;
+			interrupt-names = "otghs";
+			num-bidir-endpoints = <9>;
+			ram-size = <4096>;
+			maximum-speed = "high-speed";
+			clocks = <&rcc STM32_CLOCK(AHB5, 26)>,
+				 <&rcc STM32_SRC_HSE OTGPHY1CKREF_SEL(1)>;
+			phys = <&usbphyc1>;
+			status = "disabled";
+		};
+
+		usbphyc1: usbphyc@5803fc00 {
+			compatible = "st,stm32-usbphyc";
+			reg = <0x5803FC00 0x400>;
+			clocks = <&rcc STM32_CLOCK(AHB5, 27)>;
+			#phy-cells = <0>;
+		};
+
+		ltdc: ltdc@58001000 {
+			compatible = "st,stm32-ltdc";
+			reg = <0x58001000 0x1000>;
+			interrupts = <193 0>, <194 0>;
+			interrupt-names = "ltdc", "ltdc_er";
+			clocks = <&rcc STM32_CLOCK(APB5, 1)>,
+				 <&rcc STM32_SRC_PCLK5 LTDC_SEL(0)>;
+			resets = <&rctl STM32_RESET(APB5, 1)>;
+			status = "disabled";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};
diff --git a/dts/arm/st/n6/stm32n657.dtsi b/dts/arm/st/n6/stm32n657.dtsi
new file mode 100644
index 00000000000..7cc6f02b170
--- /dev/null
+++ b/dts/arm/st/n6/stm32n657.dtsi
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/n6/stm32n6.dtsi>
+
+
+/ {
+	soc {
+		compatible = "st,stm32n657", "st,stm32n6", "simple-bus";
+	};
+};
diff --git a/dts/arm/st/n6/stm32n657X0.dtsi b/dts/arm/st/n6/stm32n657X0.dtsi
new file mode 100644
index 00000000000..b503ffed905
--- /dev/null
+++ b/dts/arm/st/n6/stm32n657X0.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/n6/stm32n657.dtsi>
+
+/ {
+	axisram1: memory@34000000 {
+		/* 400 kB of FLEXRAM followed by 624 kB of AXISRAM1 */
+		reg = <0x34000000 (DT_SIZE_K(400) + DT_SIZE_K(624))>;
+	};
+
+	axisram2: memory@34180400 {
+		reg = <0x34180400 DT_SIZE_K(511)>;
+	};
+};
diff --git a/dts/arm/st/u0/stm32u0.dtsi b/dts/arm/st/u0/stm32u0.dtsi
index 904a61ab417..612747dfc4c 100644
--- a/dts/arm/st/u0/stm32u0.dtsi
+++ b/dts/arm/st/u0/stm32u0.dtsi
@@ -215,6 +215,15 @@
 			status = "disabled";
 		};
 
+		usart4: serial@40004c00 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 19U)>;
+			resets = <&rctl STM32_RESET(APB1L, 19U)>;
+			interrupts = <30 0>;
+			status = "disabled";
+		};
+
 		lpuart1: serial@40008000 {
 			compatible = "st,stm32-lpuart", "st,stm32-uart";
 			reg = <0x40008000 0x400>;
@@ -541,6 +550,15 @@
 			reg = <0x40009400 0x400>;
 			interrupts = <18 1>;
 			interrupt-names = "combined";
+		};
+
+		tsc: tsc@40024000 {
+			compatible = "st,stm32-tsc";
+			reg = <0x40024000 0x400>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 24U)>;
+			resets = <&rctl STM32_RESET(AHB1, 24U)>;
+			interrupts = <21 0>;
+			interrupt-names = "global";
 			status = "disabled";
 		};
 	};
diff --git a/dts/arm/st/u0/stm32u073.dtsi b/dts/arm/st/u0/stm32u073.dtsi
index dbc1f366cc8..52d53239acc 100644
--- a/dts/arm/st/u0/stm32u073.dtsi
+++ b/dts/arm/st/u0/stm32u073.dtsi
@@ -55,15 +55,11 @@
 			interrupt-names = "usb";
 			num-bidir-endpoints = <8>;
 			ram-size = <1024>;
+			maximum-speed = "full-speed";
 			phys = <&usb_fs_phy>;
 			clocks = <&rcc STM32_CLOCK(APB1, 13U)>;
 			status = "disabled";
 		};
-
-		usb_fs_phy: usbphy {
-			compatible = "usb-nop-xceiv";
-			#phy-cells = <0>;
-		};
 	};
 
 	sram1: memory@20000000 {
@@ -75,4 +71,9 @@
 		compatible = "zephyr,memory-region", "mmio-sram";
 		zephyr,memory-region = "SRAM2";
 	};
+
+	usb_fs_phy: usbphy {
+		compatible = "usb-nop-xceiv";
+		#phy-cells = <0>;
+	};
 };
diff --git a/dts/arm/st/u5/stm32u5.dtsi b/dts/arm/st/u5/stm32u5.dtsi
index 9c002c555dd..da2d4eceb64 100644
--- a/dts/arm/st/u5/stm32u5.dtsi
+++ b/dts/arm/st/u5/stm32u5.dtsi
@@ -304,7 +304,7 @@
 			compatible = "zephyr,memory-region", "st,stm32-backup-sram";
 			reg = <0x40036400 DT_SIZE_K(2)>;
 			/* BKPSRAMEN and RAMCFGEN clock enable */
-			clocks = <&rcc STM32_CLOCK(AHB1, 28U)>;
+			clocks = <&rcc STM32_CLOCK_BUS_AHB1 ((1 << 28) | (1 << 17))>;
 			zephyr,memory-region = "BACKUP_SRAM";
 			status = "disabled";
 		};
@@ -696,7 +696,7 @@
 			};
 		};
 
-		octospi1: octospi@420d1400 {
+		octospi1: spi@420d1400 {
 			compatible = "st,stm32-ospi";
 			reg = <0x420d1400 0x400>;
 			interrupts = <76 0>;
@@ -705,11 +705,11 @@
 				<&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>,
 				<&rcc STM32_CLOCK(AHB2, 21U)>;
 			#address-cells = <1>;
-			#size-cells = <0>;
+			#size-cells = <1>;
 			status = "disabled";
 		};
 
-		octospi2: octospi@420d2400 {
+		octospi2: spi@420d2400 {
 			compatible = "st,stm32-ospi";
 			reg = <0x420d2400 0x400>;
 			interrupts = <120 0>;
@@ -718,7 +718,7 @@
 				<&rcc STM32_SRC_SYSCLK OCTOSPI_SEL(0)>,
 				<&rcc STM32_CLOCK(AHB2, 21U)>;
 			#address-cells = <1>;
-			#size-cells = <0>;
+			#size-cells = <1>;
 			status = "disabled";
 		};
 
@@ -876,58 +876,58 @@
 
 			wkup-pin@1 {
 				reg = <0x1>;
-				wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>,
-					     <&gpiob 2 STM32_PWR_WKUP_PIN_SRC_1>,
-					     <&gpioe 4 STM32_PWR_WKUP_PIN_SRC_2>;
+				wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_EVT_SRC_0>,
+					     <&gpiob 2 STM32_PWR_WKUP_EVT_SRC_1>,
+					     <&gpioe 4 STM32_PWR_WKUP_EVT_SRC_2>;
 			};
 
 			wkup-pin@2 {
 				reg = <0x2>;
-				wkup-gpios = <&gpioa 4 STM32_PWR_WKUP_PIN_SRC_0>,
-					     <&gpioc 13 STM32_PWR_WKUP_PIN_SRC_1>,
-					     <&gpioe 5 STM32_PWR_WKUP_PIN_SRC_2>;
+				wkup-gpios = <&gpioa 4 STM32_PWR_WKUP_EVT_SRC_0>,
+					     <&gpioc 13 STM32_PWR_WKUP_EVT_SRC_1>,
+					     <&gpioe 5 STM32_PWR_WKUP_EVT_SRC_2>;
 			};
 
 			wkup-pin@3 {
 				reg = <0x3>;
-				wkup-gpios = <&gpioe 6 STM32_PWR_WKUP_PIN_SRC_0>,
-					     <&gpioa 1 STM32_PWR_WKUP_PIN_SRC_1>,
-					     <&gpiob 6 STM32_PWR_WKUP_PIN_SRC_2>;
+				wkup-gpios = <&gpioe 6 STM32_PWR_WKUP_EVT_SRC_0>,
+					     <&gpioa 1 STM32_PWR_WKUP_EVT_SRC_1>,
+					     <&gpiob 6 STM32_PWR_WKUP_EVT_SRC_2>;
 			};
 
 			wkup-pin@4 {
 				reg = <0x4>;
-				wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_SRC_0>,
-					     <&gpiob 1 STM32_PWR_WKUP_PIN_SRC_1>,
-					     <&gpiob 7 STM32_PWR_WKUP_PIN_SRC_2>;
+				wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_EVT_SRC_0>,
+					     <&gpiob 1 STM32_PWR_WKUP_EVT_SRC_1>,
+					     <&gpiob 7 STM32_PWR_WKUP_EVT_SRC_2>;
 			};
 
 			wkup-pin@5 {
 				reg = <0x5>;
-				wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_SRC_0>,
-					     <&gpioa 3 STM32_PWR_WKUP_PIN_SRC_1>,
-					     <&gpiob 8 STM32_PWR_WKUP_PIN_SRC_2>;
+				wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_EVT_SRC_0>,
+					     <&gpioa 3 STM32_PWR_WKUP_EVT_SRC_1>,
+					     <&gpiob 8 STM32_PWR_WKUP_EVT_SRC_2>;
 			};
 
 			wkup-pin@6 {
 				reg = <0x6>;
-				wkup-gpios = <&gpiob 5 STM32_PWR_WKUP_PIN_SRC_0>,
-					     <&gpioa 5 STM32_PWR_WKUP_PIN_SRC_1>,
-					     <&gpioe 7 STM32_PWR_WKUP_PIN_SRC_2>;
+				wkup-gpios = <&gpiob 5 STM32_PWR_WKUP_EVT_SRC_0>,
+					     <&gpioa 5 STM32_PWR_WKUP_EVT_SRC_1>,
+					     <&gpioe 7 STM32_PWR_WKUP_EVT_SRC_2>;
 			};
 
 			wkup-pin@7 {
 				reg = <0x7>;
-				wkup-gpios = <&gpiob 15 STM32_PWR_WKUP_PIN_SRC_0>,
-					     <&gpioa 6 STM32_PWR_WKUP_PIN_SRC_1>,
-					     <&gpioe 8 STM32_PWR_WKUP_PIN_SRC_2>;
+				wkup-gpios = <&gpiob 15 STM32_PWR_WKUP_EVT_SRC_0>,
+					     <&gpioa 6 STM32_PWR_WKUP_EVT_SRC_1>,
+					     <&gpioe 8 STM32_PWR_WKUP_EVT_SRC_2>;
 			};
 
 			wkup-pin@8 {
 				reg = <0x8>;
-				wkup-gpios = <&gpiof 2 STM32_PWR_WKUP_PIN_SRC_0>,
-					     <&gpioa 7 STM32_PWR_WKUP_PIN_SRC_1>,
-					     <&gpiob 10 STM32_PWR_WKUP_PIN_SRC_2>;
+				wkup-gpios = <&gpiof 2 STM32_PWR_WKUP_EVT_SRC_0>,
+					     <&gpioa 7 STM32_PWR_WKUP_EVT_SRC_1>,
+					     <&gpiob 10 STM32_PWR_WKUP_EVT_SRC_2>;
 			};
 		};
 
diff --git a/dts/arm/st/u5/stm32u545.dtsi b/dts/arm/st/u5/stm32u545.dtsi
index b7c7b6c0c64..c034e6a2727 100644
--- a/dts/arm/st/u5/stm32u545.dtsi
+++ b/dts/arm/st/u5/stm32u545.dtsi
@@ -21,6 +21,7 @@
 			interrupt-names = "usb";
 			num-bidir-endpoints = <8>;
 			ram-size = <1024>;
+			maximum-speed = "full-speed";
 			status = "disabled";
 			clocks = <&rcc STM32_CLOCK(APB2, 24U)>,
 				 <&rcc STM32_SRC_HSI48 ICKLK_SEL(0)>;
diff --git a/dts/arm/st/u5/stm32u595.dtsi b/dts/arm/st/u5/stm32u595.dtsi
index 5ca3f66d7d5..f3fc9985967 100644
--- a/dts/arm/st/u5/stm32u595.dtsi
+++ b/dts/arm/st/u5/stm32u595.dtsi
@@ -108,7 +108,7 @@
 			num-bidir-endpoints = <9>;
 			ram-size = <4096>;
 			maximum-speed = "high-speed";
-			clocks = <&rcc STM32_CLOCK(AHB2, 14U)>;
+			clocks = <&rcc STM32_CLOCK(AHB2, 14)>;
 			phys = <&otghs_phy>;
 			status = "disabled";
 		};
diff --git a/dts/arm/st/u5/stm32u5g9.dtsi b/dts/arm/st/u5/stm32u5g9.dtsi
new file mode 100644
index 00000000000..f9eadbb65e0
--- /dev/null
+++ b/dts/arm/st/u5/stm32u5g9.dtsi
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Charles Dias
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/u5/stm32u595.dtsi>
+
+/ {
+	soc {
+		compatible = "st,stm32u5g9", "st,stm32u5", "simple-bus";
+	};
+};
diff --git a/dts/arm/st/u5/stm32u5g9Xj.dtsi b/dts/arm/st/u5/stm32u5g9Xj.dtsi
new file mode 100644
index 00000000000..10e4793f9d1
--- /dev/null
+++ b/dts/arm/st/u5/stm32u5g9Xj.dtsi
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2025 Charles Dias
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <st/u5/stm32u5g9.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		/* SRAM1 + SRAM2 + SRAM3 + SRAM5 + SRAM6 */
+		/* 768K + 64K + 832K + 832K + 512 */
+		reg = <0x20000000 DT_SIZE_K(3008)>;
+	};
+
+	sram4: memory@28000000 {
+		/* SRAM4, low-power background autonomous mode */
+		reg = <0x28000000 DT_SIZE_K(16)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_M(4)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/wb/stm32wb.dtsi b/dts/arm/st/wb/stm32wb.dtsi
index b3825cf380a..a9652addf3f 100644
--- a/dts/arm/st/wb/stm32wb.dtsi
+++ b/dts/arm/st/wb/stm32wb.dtsi
@@ -487,16 +487,17 @@
 			interrupt-names = "usb", "usbhp";
 			num-bidir-endpoints = <8>;
 			ram-size = <1024>;
+			maximum-speed = "full-speed";
 			phys = <&usb_fs_phy>;
 			clocks = <&rcc STM32_CLOCK(APB1, 26U)>,
 				 <&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
 			status = "disabled";
 		};
 
-		quadspi: quadspi@a0001000 {
+		quadspi: spi@a0001000 {
 			compatible = "st,stm32-qspi";
 			#address-cells = <0x1>;
-			#size-cells = <0x0>;
+			#size-cells = <0x1>;
 			reg = <0xa0001000 0x400>;
 			interrupts = <0x32 0x0>;
 			clocks = <&rcc STM32_CLOCK(AHB3, 8U)>;
@@ -534,12 +535,12 @@
 
 			wkup-pin@1 {
 				reg = <0x1>;
-				wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>;
+				wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_NOT_MUXED>;
 			};
 
 			wkup-pin@4 {
 				reg = <0x4>;
-				wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_SRC_0>;
+				wkup-gpios = <&gpioa 2 STM32_PWR_WKUP_PIN_NOT_MUXED>;
 			};
 		};
 	};
diff --git a/dts/arm/st/wb/stm32wb55Xg.dtsi b/dts/arm/st/wb/stm32wb55Xg.dtsi
index c3a7d391e77..0e4a2220038 100644
--- a/dts/arm/st/wb/stm32wb55Xg.dtsi
+++ b/dts/arm/st/wb/stm32wb55Xg.dtsi
@@ -24,16 +24,16 @@
 &pwr {
 	wkup-pin@2 {
 		reg = <0x2>;
-		wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_SRC_0>;
+		wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_NOT_MUXED>;
 	};
 
 	wkup-pin@3 {
 		reg = <0x3>;
-		wkup-gpios = <&gpioc 12 STM32_PWR_WKUP_PIN_SRC_0>;
+		wkup-gpios = <&gpioc 12 STM32_PWR_WKUP_PIN_NOT_MUXED>;
 	};
 
 	wkup-pin@5 {
 		reg = <0x5>;
-		wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_SRC_0>;
+		wkup-gpios = <&gpioc 5 STM32_PWR_WKUP_PIN_NOT_MUXED>;
 	};
 };
diff --git a/dts/arm/st/wb0/stm32wb0.dtsi b/dts/arm/st/wb0/stm32wb0.dtsi
index c1dcd6ef68c..0900f8f02a0 100644
--- a/dts/arm/st/wb0/stm32wb0.dtsi
+++ b/dts/arm/st/wb0/stm32wb0.dtsi
@@ -178,6 +178,14 @@
 			};
 		};
 
+		rtc: rtc@40004000 {
+			compatible = "st,stm32-rtc";
+			reg = <0x40004000 DT_SIZE_K(1)>;
+			interrupts = <11 0>;
+			clocks = <&rcc STM32_CLOCK(APB0, 12)>;
+			status = "disabled";
+		};
+
 		usart1: serial@41004000 {
 			compatible = "st,stm32-usart", "st,stm32-uart";
 			reg = <0x41004000 DT_SIZE_K(1)>;
@@ -259,6 +267,29 @@
 			dma-requests= <25>;
 			status = "disabled";
 		};
+
+		/**
+		 * This node is valid for STM32WB05, STM32WB06 and
+		 * STM32WB07, all equipped with the same IRQ-less
+		 * TRNG instance. Since all those properties are
+		 * also valid on STM32SWB09, except "compatible",
+		 * we pretend this node is valid for all SoCs of
+		 * the series and clean up in `stm32wb09.dtsi`.
+		 */
+		rng: rng@48600000 {
+			compatible = "st,stm32-rng-noirq";
+			reg = <0x48600000 DT_SIZE_K(4)>;
+			clocks = <&rcc STM32_CLOCK(AHB0, 18)>;
+			generation-delay-ns = <1250>; /* 1.25us */
+			status = "disabled";
+		};
+
+		iwdg: watchdog@40003000 {
+			compatible = "st,stm32-watchdog";
+			reg = <0x40003000 DT_SIZE_K(1)>;
+			clocks = <&rcc STM32_CLOCK(APB0, 14)>;
+			status = "disabled";
+		};
 	};
 
 	bt_hci_wb0: bt_hci_wb0 {
diff --git a/dts/arm/st/wb0/stm32wb05.dtsi b/dts/arm/st/wb0/stm32wb05.dtsi
index 15dfabf83b9..e44aad6770a 100644
--- a/dts/arm/st/wb0/stm32wb05.dtsi
+++ b/dts/arm/st/wb0/stm32wb05.dtsi
@@ -9,5 +9,71 @@
 / {
 	soc {
 		compatible = "st,stm32wb05", "st,stm32wb0", "simple-bus";
+
+		timers2: timers@40002000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40002000 DT_SIZE_K(1)>;
+			clocks = <&rcc STM32_CLOCK(APB0, 0)>;
+			resets = <&rctl STM32_RESET(APB0, 0)>;
+			interrupts = <10 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+			};
+		};
+
+		timers16: timers@40005000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40005000 DT_SIZE_K(1)>;
+			clocks = <&rcc STM32_CLOCK(APB0, 1)>;
+			resets = <&rctl STM32_RESET(APB0, 1)>;
+			interrupts = <26 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+			};
+		};
+
+		timers17: timers@40006000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40006000 DT_SIZE_K(1)>;
+			clocks = <&rcc STM32_CLOCK(APB0, 2)>;
+			resets = <&rctl STM32_RESET(APB0, 2)>;
+			interrupts = <27 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+			};
+		};
 	};
 };
diff --git a/dts/arm/st/wb0/stm32wb07.dtsi b/dts/arm/st/wb0/stm32wb07.dtsi
index dec050b680e..5e8e2ed2fa0 100644
--- a/dts/arm/st/wb0/stm32wb07.dtsi
+++ b/dts/arm/st/wb0/stm32wb07.dtsi
@@ -47,5 +47,27 @@
 			interrupts = <6 0>;
 			status = "disabled";
 		};
+
+		timers1: timers@40002000 {
+			compatible = "st,stm32-timers";
+			reg = <0x40002000 DT_SIZE_K(1)>;
+			clocks = <&rcc STM32_CLOCK(APB0, 0)>;
+			resets = <&rctl STM32_RESET(APB0, 0)>;
+			interrupts = <10 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				#pwm-cells = <3>;
+			};
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+			};
+		};
 	};
 };
diff --git a/dts/arm/st/wb0/stm32wb09.dtsi b/dts/arm/st/wb0/stm32wb09.dtsi
index 604ac43322b..9b3c54e27a7 100644
--- a/dts/arm/st/wb0/stm32wb09.dtsi
+++ b/dts/arm/st/wb0/stm32wb09.dtsi
@@ -14,5 +14,17 @@
 / {
 	soc {
 		compatible = "st,stm32wb09", "st,stm32wb0", "simple-bus";
+
+		rng: rng@48600000 {
+			/**
+			 * STM32WB09 TRNG has an interrupt line.
+			 * Switch to proper compatible, delete property
+			 * that doesn't apply to it, and add the interrupt
+			 * line as property.
+			 */
+			/delete-property/ generation-delay-ns;
+			compatible = "st,stm32-rng";
+			interrupts = <28 0>;
+		};
 	};
 };
diff --git a/dts/arm/st/wba/stm32wba.dtsi b/dts/arm/st/wba/stm32wba.dtsi
index 713c913da5e..5385e7f7ff5 100644
--- a/dts/arm/st/wba/stm32wba.dtsi
+++ b/dts/arm/st/wba/stm32wba.dtsi
@@ -118,6 +118,13 @@
 		};
 	};
 
+	mcos {
+		mco1: mco1 {
+			compatible = "st,stm32-clock-mco";
+			status = "disabled";
+		};
+	};
+
 	soc {
 		flash: flash-controller@40022000 {
 			compatible = "st,stm32-flash-controller", "st,stm32wba-flash-controller";
@@ -495,7 +502,7 @@
 		compatible = "swj-connector";
 		pinctrl-0 = <&debug_jtms_swdio_pa13 &debug_jtck_swclk_pa14
 			     &debug_jtdi_pa15 &debug_jtdo_swo_pb3
-			     &debug_jtrst_pb4>;
+			     &debug_njtrst_pb4>;
 		pinctrl-1 = <&analog_pa13 &analog_pa14 &analog_pa15
 			     &analog_pb3 &analog_pb4>;
 		pinctrl-names = "default", "sleep";
diff --git a/dts/arm/st/wba/stm32wba65.dtsi b/dts/arm/st/wba/stm32wba65.dtsi
new file mode 100644
index 00000000000..6f6e0eaa14f
--- /dev/null
+++ b/dts/arm/st/wba/stm32wba65.dtsi
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <st/wba/stm32wba55.dtsi>
+
+/ {
+	soc {
+		compatible = "st,stm32wba65", "st,stm32wba", "simple-bus";
+
+		pinctrl: pin-controller@42020000 {
+			gpiod: gpio@42020c00 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42020c00 0x400>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 3)>;
+			};
+
+			gpioe: gpio@42021000 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				reg = <0x42021000 0x400>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 4)>;
+			};
+
+			gpiog: gpio@42021800 {
+				compatible = "st,stm32-gpio";
+				gpio-controller;
+				#gpio-cells = <2>;
+				/* GPIOG has an independent IO supply VDDIO2 */
+				reg = <0x42021800 0x400>;
+				clocks = <&rcc STM32_CLOCK(AHB2, 6)>;
+			};
+		};
+
+		usart3: serial@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 18)>;
+			resets = <&rctl STM32_RESET(APB1L, 18U)>;
+			interrupts = <79 0>;
+			status = "disabled";
+		};
+
+		spi2: spi@40003800 {
+			compatible = "st,stm32h7-spi", "st,stm32-spi-fifo", "st,stm32-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40003800 0x400>;
+			interrupts = <75 5>;
+			clocks = <&rcc STM32_CLOCK(APB1, 14)>;
+			status = "disabled";
+		};
+
+		timers4: timers@40000800 {
+			compatible = "st,stm32-timers";
+			reg = <0x40000800 0x400>;
+			clocks = <&rcc STM32_CLOCK(APB1, 2)>;
+			resets = <&rctl STM32_RESET(APB1L, 2U)>;
+			interrupts = <72 0>;
+			interrupt-names = "global";
+			st,prescaler = <0>;
+			status = "disabled";
+
+			counter {
+				compatible = "st,stm32-counter";
+				status = "disabled";
+			};
+
+			pwm {
+				compatible = "st,stm32-pwm";
+				status = "disabled";
+				#pwm-cells = <3>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/wba/stm32wba65Xi.dtsi b/dts/arm/st/wba/stm32wba65Xi.dtsi
new file mode 100644
index 00000000000..422ae59aa3b
--- /dev/null
+++ b/dts/arm/st/wba/stm32wba65Xi.dtsi
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <st/wba/stm32wba65.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(448)>;
+	};
+
+	sram1: memory@20070000 {
+		compatible = "mmio-sram";
+		reg = <0x20070000 DT_SIZE_K(64)>;
+	};
+
+	soc {
+		flash-controller@40022000 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_M(2)>;
+			};
+		};
+	};
+};
diff --git a/dts/arm/st/wl/stm32wl.dtsi b/dts/arm/st/wl/stm32wl.dtsi
index 6c0e71876f3..3c7c477c472 100644
--- a/dts/arm/st/wl/stm32wl.dtsi
+++ b/dts/arm/st/wl/stm32wl.dtsi
@@ -106,6 +106,13 @@
 		};
 	};
 
+	mcos {
+		mco1: mco1 {
+			compatible = "st,stm32-clock-mco";
+			status = "disabled";
+		};
+	};
+
 	soc {
 		flash: flash-controller@58004000 {
 			compatible = "st,stm32-flash-controller", "st,stm32l4-flash-controller";
@@ -516,17 +523,17 @@
 
 			wkup-pin@1 {
 				reg = <0x1>;
-				wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_SRC_0>;
+				wkup-gpios = <&gpioa 0 STM32_PWR_WKUP_PIN_NOT_MUXED>;
 			};
 
 			wkup-pin@2 {
 				reg = <0x2>;
-				wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_SRC_0>;
+				wkup-gpios = <&gpioc 13 STM32_PWR_WKUP_PIN_NOT_MUXED>;
 			};
 
 			wkup-pin@3 {
 				reg = <0x3>;
-				wkup-gpios = <&gpiob 3 STM32_PWR_WKUP_PIN_SRC_0>;
+				wkup-gpios = <&gpiob 3 STM32_PWR_WKUP_PIN_NOT_MUXED>;
 			};
 		};
 	};
diff --git a/dts/arm/ti/am62x_m4.dtsi b/dts/arm/ti/am62x_m4.dtsi
index b310c19b170..1d43602463d 100644
--- a/dts/arm/ti/am62x_m4.dtsi
+++ b/dts/arm/ti/am62x_m4.dtsi
@@ -9,6 +9,7 @@
 #include <arm/armv7-m.dtsi>
 #include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
 #include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
 
 / {
 
@@ -39,6 +40,15 @@
 		#clock-cells = <0>;
 	};
 
+	mbox0: mailbox@29000000 {
+		compatible = "ti,omap-mailbox";
+		reg = <0x29000000 0x200>;
+		interrupts = <50 4>;
+		interrupt-parent = <&nvic>;
+		usr-id = <2>;
+		#mbox-cells = <1>;
+	};
+
 	pinctrl: pinctrl@4084000 {
 		compatible = "ti,k3-pinctrl";
 		reg = <0x04084000 0x88>;
@@ -56,6 +66,16 @@
 		status = "disabled";
 	};
 
+	i2c0: i2c@4900000 {
+		compatible = "ti,omap-i2c";
+		reg = <0x04900000 0x100>;
+		interrupts = <17 4>;
+		interrupt-parent = <&nvic>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	gpio0: gpio@4201010 {
 		compatible = "ti,davinci-gpio";
 		reg = <0x4201010 0x100>;
diff --git a/dts/arm/ti/am64x_m4.dtsi b/dts/arm/ti/am64x_m4.dtsi
index d95fe49a90e..b7e040ef76d 100644
--- a/dts/arm/ti/am64x_m4.dtsi
+++ b/dts/arm/ti/am64x_m4.dtsi
@@ -9,6 +9,7 @@
 #include <arm/armv7-m.dtsi>
 #include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
 #include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
 
 / {
 
@@ -39,6 +40,15 @@
 		#clock-cells = <0>;
 	};
 
+	mbox6: mailbox@29060000 {
+		compatible = "ti,omap-mailbox";
+		reg = <0x29060000 0x200>;
+		interrupts = <56 4>;
+		interrupt-parent = <&nvic>;
+		usr-id = <3>;
+		#mbox-cells = <1>;
+	};
+
 	pinctrl: pinctrl@4084000 {
 		compatible = "ti,k3-pinctrl";
 		reg = <0x04084000 0x88>;
@@ -67,6 +77,26 @@
 		status = "disabled";
 	};
 
+	i2c0: i2c@4900000 {
+		compatible = "ti,omap-i2c";
+		reg = <0x04900000 0x100>;
+		interrupts = <17 4>;
+		interrupt-parent = <&nvic>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c1: i2c@4910000 {
+		compatible = "ti,omap-i2c";
+		reg = <0x04910000 0x100>;
+		interrupts = <18 4>;
+		interrupt-parent = <&nvic>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	gpio0: gpio@4201010 {
 		compatible = "ti,davinci-gpio";
 		reg = <0x4201010 0x100>;
diff --git a/dts/arm/ti/cc2340r5.dtsi b/dts/arm/ti/cc2340r5.dtsi
new file mode 100644
index 00000000000..c275b2e1de8
--- /dev/null
+++ b/dts/arm/ti/cc2340r5.dtsi
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <ti/cc23x0.dtsi>
+
+/ {
+	sram0: memory@20000000 {
+		reg = <0x20000000 DT_SIZE_K(36)>;
+	};
+};
+
+/* Main flash */
+&flash0 {
+	reg = <0x0 DT_SIZE_K(512)>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	slot0_partition: partition@0 {
+		label = "image-0";
+		reg = <0x0 DT_SIZE_K(512)>;
+	};
+};
+
+/* CCFG */
+&flash1 {
+	reg = <0x4e020000 DT_SIZE_K(2)>;
+	ti,bldr-vtor-flash = <0>;
+	ti,serial-io-cfg-index = <0>;
+	ti,debug-port;
+	ti,energy-trace;
+	ti,flash-verify;
+	ti,flash-program;
+	ti,chip-erase;
+	ti,ret-to-factory;
+	ti,wr-er-prot-sect0-31 = <0xffffffff>;
+	ti,wr-er-prot-sect32-255 = <0xffffffff>;
+	ti,wr-er-prot-ccfg-sect = <0>;
+	ti,wr-er-prot-fcfg-sect = <0>;
+	ti,wr-er-prot-engr-sect = <0>;
+	ti,chip-er-retain-sect0-31 = <0>;
+	ti,chip-er-retain-sect32-255 = <0>;
+
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		ti_ccfg_partition: partition@4e020000 {
+			compatible = "zephyr,memory-region";
+			reg = <0x4e020000 0x800>;
+			zephyr,memory-region = "FLASH_CCFG";
+		};
+	};
+};
diff --git a/dts/arm/ti/cc23x0.dtsi b/dts/arm/ti/cc23x0.dtsi
new file mode 100644
index 00000000000..ec2e773ec0d
--- /dev/null
+++ b/dts/arm/ti/cc23x0.dtsi
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv6-m.dtsi>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,flash-controller = &flash_controller;
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m0+";
+			clock-frequency = <DT_FREQ_M(48)>;
+			reg = <0>;
+		};
+	};
+
+	sram0: memory@20000000 {
+		compatible = "mmio-sram";
+	};
+
+	sysclk: system-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <DT_FREQ_M(48)>;
+		#clock-cells = <0>;
+	};
+
+	soc {
+		flash_controller: flash-controller@40021000 {
+			compatible = "ti,cc23x0-flash-controller";
+			reg = <0x40021000 0x408>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			/* Main flash sector */
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				erase-block-size = <DT_SIZE_K(2)>;
+				write-block-size = <0x10>;
+			};
+
+			/* CCFG flash sector */
+			flash1: flash@4e020000 {
+				compatible = "ti,cc23x0-ccfg-flash", "soc-nv-flash";
+				erase-block-size = <DT_SIZE_K(2)>;
+				write-block-size = <0x10>;
+			};
+		};
+
+		pinctrl: pinctrl@40003000 {
+			compatible = "ti,cc23x0-pinctrl";
+			reg = <0x40003000 0xc14>;
+		};
+
+		gpio0: gpio@40023000 {
+			compatible = "ti,cc23x0-gpio";
+			reg = <0x40023000 0x804>;
+			interrupts = <5 0>;	/* GPIO combined on CPUIRQ5 */
+			status = "disabled";
+			gpio-controller;
+			#gpio-cells = <2>;	/* Pin (ID), and flags */
+			ngpios = <26>;		/* Only [DIO0, DIO25] are available */
+		};
+
+		uart0: uart@40034000 {
+			compatible = "ti,cc23x0-uart";
+			reg = <0x40034000 0x52>;
+			interrupts = <11 0>;
+			clocks = <&sysclk>;
+			status = "disabled";
+		};
+
+		aes: aes@400c0000 {
+			compatible = "ti,cc23x0-aes";
+			reg = <0x400c0000 0x120>;
+			interrupts = <9 0>;
+			status = "disabled";
+		};
+
+		dma: dma@40026000 {
+			compatible = "ti,cc23x0-dma";
+			reg = <0x40026000 0x524>;
+			interrupts = <8 0>;
+			#dma-cells = <2>;
+			status = "disabled";
+		};
+
+		spi0: spi@40030000 {
+			compatible = "ti,cc23x0-spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40030000 0x164>;
+			interrupts = <10 0>;
+			status = "disabled";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <2>; /* Interrupt levels are 0-192 in steps of 64 */
+};
+
+&systick {
+	status = "disabled";
+};
diff --git a/dts/arm/ti/j721e_main_r5.dtsi b/dts/arm/ti/j721e_main_r5.dtsi
index 7b8f72ba5ae..e088321e966 100644
--- a/dts/arm/ti/j721e_main_r5.dtsi
+++ b/dts/arm/ti/j721e_main_r5.dtsi
@@ -55,6 +55,83 @@
 		status = "okay";
 	};
 
+	i2c0: i2c0@2000000 {
+		compatible = "ti,omap-i2c";
+		reg = <0x02000000 0x1000>;
+		interrupts = <0 150 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		clock-frequency = <100000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c1: i2c1@2010000 {
+		compatible = "ti,omap-i2c";
+		reg = <0x02010000 0x1000>;
+		interrupts = <0 151 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		clock-frequency = <100000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c2: i2c2@2020000 {
+		compatible = "ti,omap-i2c";
+		reg = <0x02020000 0x1000>;
+		interrupts = <0 183 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		clock-frequency = <100000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c3: i2c3@2030000 {
+		compatible = "ti,omap-i2c";
+		reg = <0x02030000 0x1000>;
+		interrupts = <0 184 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		clock-frequency = <100000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c4: i2c4@2040000 {
+		compatible = "ti,omap-i2c";
+		reg = <0x02040000 0x1000>;
+		interrupts = <0 185 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		clock-frequency = <100000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c5: i2c5@2050000 {
+		compatible = "ti,omap-i2c";
+		reg = <0x02050000 0x1000>;
+		interrupts = <0 186 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		clock-frequency = <100000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
+	i2c6: i2c@2060000 {
+		compatible = "ti,omap-i2c";
+		reg = <0x02060000 0x1000>;
+		interrupts = <0 187 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		clock-frequency = <100000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "disabled";
+	};
+
 	uart1: uart@2810000 {
 		compatible = "ns16550";
 		reg = <0x02810000 0x100>;
diff --git a/dts/arm/ti/j722s_main.dtsi b/dts/arm/ti/j722s_main.dtsi
new file mode 100644
index 00000000000..4ed66cde145
--- /dev/null
+++ b/dts/arm/ti/j722s_main.dtsi
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ *	Andrew Davis <afd@ti.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <freq.h>
+#include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	pinctrl: pinctrl@f4000 {
+		compatible = "ti,k3-pinctrl";
+		reg = <0x000f4000 0x2ac>;
+		status = "okay";
+	};
+
+	gpio0: gpio@600010 {
+		compatible = "ti,davinci-gpio";
+		reg = <0x00600010 0x100>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <92>;
+		status = "disabled";
+	};
+
+	gpio1: gpio@601010 {
+		compatible = "ti,davinci-gpio";
+		reg = <0x00601010 0x100>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <52>;
+		status = "disabled";
+	};
+
+	uart0: uart@2800000 {
+		compatible = "ns16550";
+		reg = <0x02800000 0x100>;
+		clock-frequency = <48000000>;
+		interrupts = <0 210 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart1: uart@2810000 {
+		compatible = "ns16550";
+		reg = <0x02810000 0x100>;
+		clock-frequency = <48000000>;
+		interrupts = <0 211 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart2: uart@2820000 {
+		compatible = "ns16550";
+		reg = <0x02820000 0x100>;
+		clock-frequency = <48000000>;
+		interrupts = <0 212 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart3: uart@2830000 {
+		compatible = "ns16550";
+		reg = <0x02830000 0x100>;
+		clock-frequency = <48000000>;
+		interrupts = <0 213 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart4: uart@2840000 {
+		compatible = "ns16550";
+		reg = <0x02840000 0x100>;
+		clock-frequency = <48000000>;
+		interrupts = <0 214 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart5: uart@2850000 {
+		compatible = "ns16550";
+		reg = <0x02850000 0x100>;
+		clock-frequency = <48000000>;
+		interrupts = <0 215 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	uart6: uart@2860000 {
+		compatible = "ns16550";
+		reg = <0x02860000 0x100>;
+		clock-frequency = <48000000>;
+		interrupts = <0 216 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+};
diff --git a/dts/arm/ti/j722s_main_r5.dtsi b/dts/arm/ti/j722s_main_r5.dtsi
new file mode 100644
index 00000000000..fe1457780de
--- /dev/null
+++ b/dts/arm/ti/j722s_main_r5.dtsi
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ *	Andrew Davis <afd@ti.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <freq.h>
+#include <arm/armv7-r.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>
+
+#include "j722s_mcu.dtsi"
+#include "j722s_main.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r5";
+			reg = <0>;
+		};
+	};
+
+	atcm: memory@0 {
+		device_type = "memory";
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x00000000 DT_SIZE_K(32)>;
+		zephyr,memory-region = "ATCM";
+	};
+
+	btcm: memory@41010000 {
+		device_type = "memory";
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x41010000 DT_SIZE_K(32)>;
+		zephyr,memory-region = "BTCM";
+	};
+
+	vim: interrupt-controller@2fff0000 {
+		#address-cells = <1>;
+		compatible = "ti,vim";
+		reg = <0x2fff0000 0x2800>;
+		interrupt-controller;
+		#interrupt-cells = <4>; /* {IRQ/FIQ, IRQ_NUM, IRQ_TYPE, IRQ_PRIO} */
+		status = "okay";
+	};
+
+	systick_timer: timer@2470000 {
+		compatible = "ti,am654-timer";
+		reg = <0x02470000 0x70>;
+		interrupts = <0 35 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		status = "disabled";
+	};
+};
diff --git a/dts/arm/ti/j722s_mcu.dtsi b/dts/arm/ti/j722s_mcu.dtsi
new file mode 100644
index 00000000000..df67bb8b279
--- /dev/null
+++ b/dts/arm/ti/j722s_mcu.dtsi
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ *	Andrew Davis <afd@ti.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <freq.h>
+#include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	mcu_gpio0: gpio@4201010 {
+		compatible = "ti,davinci-gpio";
+		reg = <0x4201010 0x100>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		ngpios = <24>;
+		status = "disabled";
+	};
+
+	mcu_uart0: uart@4a00000 {
+		compatible = "ns16550";
+		reg = <0x04a00000 0x100>;
+		clock-frequency = <48000000>;
+		interrupts = <0 217 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+};
diff --git a/dts/arm/ti/j722s_mcu_r5.dtsi b/dts/arm/ti/j722s_mcu_r5.dtsi
new file mode 100644
index 00000000000..a348c2dc43d
--- /dev/null
+++ b/dts/arm/ti/j722s_mcu_r5.dtsi
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ *	Andrew Davis <afd@ti.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <freq.h>
+#include <arm/armv7-r.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>
+
+#include "j722s_mcu.dtsi"
+#include "j722s_main.dtsi"
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r5";
+			reg = <0>;
+		};
+	};
+
+	atcm: memory@0 {
+		device_type = "memory";
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x00000000 DT_SIZE_K(32)>;
+		zephyr,memory-region = "ATCM";
+	};
+
+	btcm: memory@41010000 {
+		device_type = "memory";
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x41010000 DT_SIZE_K(32)>;
+		zephyr,memory-region = "BTCM";
+	};
+
+	vim: interrupt-controller@7ff0000 {
+		#address-cells = <1>;
+		compatible = "ti,vim";
+		reg = <0x07ff0000 0x2800>;
+		interrupt-controller;
+		#interrupt-cells = <4>; /* {IRQ/FIQ, IRQ_NUM, IRQ_TYPE, IRQ_PRIO} */
+		status = "okay";
+	};
+
+	systick_timer: timer@4800000 {
+		compatible = "ti,am654-timer";
+		reg = <0x04800000 0x70>;
+		interrupts = <0 28 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		status = "disabled";
+	};
+};
diff --git a/dts/arm/we/oceanus1.dtsi b/dts/arm/we/oceanus1.dtsi
new file mode 100644
index 00000000000..e7b5d1e4c38
--- /dev/null
+++ b/dts/arm/we/oceanus1.dtsi
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2024 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <st/wl/stm32wle5Xc.dtsi>
+#include <st/wl/stm32wle5ccux-pinctrl.dtsi>
+
+&clk_lse {
+	clock-frequency = <32768>;
+	driving-capability = <1>;
+	status = "okay";
+};
+
+&clk_hsi {
+	status = "okay";
+};
+
+&clk_hse {
+	clock-frequency = <DT_FREQ_M(32)>;
+	hse-tcxo;
+	status = "okay";
+};
+
+&subghzspi {
+	status = "okay";
+	lora: radio@0 {
+		status = "okay";
+		antenna-enable-gpios = <&gpiob 12 GPIO_ACTIVE_HIGH>; /* RF_SW_VCC */
+		tx-enable-gpios = <&gpioc 13 GPIO_ACTIVE_HIGH>; /* RF_SW_CTRL1 */
+		rx-enable-gpios = <&gpioc 13 GPIO_ACTIVE_LOW>; /* RF_SW_CTRL1 */
+		dio3-tcxo-voltage = <SX126X_DIO3_TCXO_1V8>;
+		tcxo-power-startup-delay-ms = <1>;
+		power-amplifier-output = "rfo-lp";
+		rfo-lp-max-power = <14>;
+	};
+};
diff --git a/dts/arm/xilinx/versalnet_r52.dtsi b/dts/arm/xilinx/versalnet_r52.dtsi
new file mode 100644
index 00000000000..d4a96434781
--- /dev/null
+++ b/dts/arm/xilinx/versalnet_r52.dtsi
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2025, Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <mem.h>
+#include <arm/armv8-r.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+#include <amd/versalnet.dtsi>
+
+/ {
+	model = "Versal NET RPU";
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r52";
+			reg = <0>;
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+		status = "okay";
+	};
+};
+
+&soc {
+	interrupt-parent = <&gic>;
+
+	gic: interrupt-controller@e2000000 {
+		compatible = "arm,gic-v3", "arm,gic";
+		reg = <0xe2000000 0x10000>,
+					<0xe2100000 0x80000>;
+		interrupt-controller;
+		#interrupt-cells = <4>;
+		status = "okay";
+	};
+};
diff --git a/dts/arm/xilinx/zynqmp.dtsi b/dts/arm/xilinx/zynqmp.dtsi
index 65abc450543..ecadbdfda53 100644
--- a/dts/arm/xilinx/zynqmp.dtsi
+++ b/dts/arm/xilinx/zynqmp.dtsi
@@ -274,6 +274,28 @@
 				status = "okay";
 			};
 		};
+
+		i2c0: i2c@ff020000 {
+			compatible = "cdns,i2c";
+			reg = <0xff020000 0x1000>;
+			status = "disabled";
+			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL
+					IRQ_DEFAULT_PRIORITY>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			fifo-depth = <16>;
+		};
+
+		i2c1: i2c@ff030000 {
+			compatible = "cdns,i2c";
+			reg = <0xff030000 0x1000>;
+			status = "disabled";
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL
+					IRQ_DEFAULT_PRIORITY>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			fifo-depth = <16>;
+		};
 	};
 
 };
diff --git a/dts/arm64/broadcom/bcm2712.dtsi b/dts/arm64/broadcom/bcm2712.dtsi
index 07084ffe75d..e99a640eb2e 100644
--- a/dts/arm64/broadcom/bcm2712.dtsi
+++ b/dts/arm64/broadcom/bcm2712.dtsi
@@ -92,6 +92,20 @@
 		#address-cells = <2>;
 		#size-cells = <1>;
 
+		pcie1: pcie@1000110000 {
+			compatible = "brcm,brcmstb-pcie";
+			reg = <0x10 0x110000 0x9310>,
+			      <0x0 0x0 0x8000000>,
+			      <0x0 0x8000000 0x10000>,
+			      <0x0 0x0 0x10>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			status = "okay";
+			ranges = <0x02000000 0x0 0x0 0x1b 0x0 0x00 0xfffffffc>,
+				 <0x43000000 0x4 0x0 0x18 0x0 0x03 0x00000000>,
+				 <0x03000000 0x0 0x0 0x10 0x0 0x10 0x00000000>;
+		};
+
 		pcie2: pcie@1000120000 {
 			compatible = "brcm,brcmstb-pcie";
 			reg = <0x10 0x120000 0x9310>,
diff --git a/dts/arm64/intel/intel_socfpga_agilex5.dtsi b/dts/arm64/intel/intel_socfpga_agilex5.dtsi
index c7c9b53ebfc..ed62369c926 100644
--- a/dts/arm64/intel/intel_socfpga_agilex5.dtsi
+++ b/dts/arm64/intel/intel_socfpga_agilex5.dtsi
@@ -128,7 +128,7 @@
 			<0x10B92000 0x1000>;
 		reg-names = "reg_base", "combo_phy";
 		clock-frequency = <200000000>;
-		power_delay_ms = <1000>;
+		power-delay-ms = <1000>;
 		resets = <&reset RSTMGR_SDMMC_RSTLINE>,
 			<&reset RSTMGR_SDMMCECC_RSTLINE>,
 			<&reset RSTMGR_SOFTPHY_RSTLINE>;
diff --git a/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi b/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi
index a3334299537..7d53dc6a6bd 100644
--- a/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi
+++ b/dts/arm64/nxp/nxp_mimx8mm_a53.dtsi
@@ -209,6 +209,54 @@
 		status = "disabled";
 	};
 
+	i2c1: i2c@30a20000 {
+		compatible = "nxp,ii2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x30a20000 0x10000>;
+		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+		clocks = <&ccm IMX_CCM_I2C1_CLK 0 0>;
+		rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@30a30000 {
+		compatible = "nxp,ii2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x30a30000 0x10000>;
+		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+		clocks = <&ccm IMX_CCM_I2C2_CLK 0 0>;
+		rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+		status = "disabled";
+	};
+
+	i2c3: i2c@30a40000 {
+		compatible = "nxp,ii2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x30a40000 0x10000>;
+		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+		clocks = <&ccm IMX_CCM_I2C3_CLK 0 0>;
+		rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+		status = "disabled";
+	};
+
+	i2c4: i2c@30a50000 {
+		compatible = "nxp,ii2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x30a50000 0x10000>;
+		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+		clocks = <&ccm IMX_CCM_I2C4_CLK 0 0>;
+		rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+		status = "disabled";
+	};
+
 	rdc: rdc@303d0000 {
 		compatible = "nxp,rdc";
 		reg = <0x303d0000 DT_SIZE_K(64)>;
diff --git a/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi b/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi
index 969e7b312da..a734b9912ab 100644
--- a/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi
+++ b/dts/arm64/nxp/nxp_mimx8mn_a53.dtsi
@@ -210,6 +210,54 @@
 		status = "disabled";
 	};
 
+	i2c1: i2c@30a20000 {
+		compatible = "nxp,ii2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x30a20000 0x10000>;
+		interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+		clocks = <&ccm IMX_CCM_I2C1_CLK 0 0>;
+		rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+		status = "disabled";
+	};
+
+	i2c2: i2c@30a30000 {
+		compatible = "nxp,ii2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x30a30000 0x10000>;
+		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+		clocks = <&ccm IMX_CCM_I2C2_CLK 0 0>;
+		rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+		status = "disabled";
+	};
+
+	i2c3: i2c@30a40000 {
+		compatible = "nxp,ii2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x30a40000 0x10000>;
+		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+		clocks = <&ccm IMX_CCM_I2C3_CLK 0 0>;
+		rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+		status = "disabled";
+	};
+
+	i2c4: i2c@30a50000 {
+		compatible = "nxp,ii2c";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x30a50000 0x10000>;
+		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+		clocks = <&ccm IMX_CCM_I2C4_CLK 0 0>;
+		rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+		status = "disabled";
+	};
+
 	rdc: rdc@303d0000 {
 		compatible = "nxp,rdc";
 		reg = <0x303d0000 DT_SIZE_K(64)>;
diff --git a/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi b/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi
index 191497e17c8..b61daa87010 100644
--- a/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi
+++ b/dts/arm64/nxp/nxp_mimx8mp_a53.dtsi
@@ -189,6 +189,78 @@
 			status = "disabled";
 		};
 
+		i2c1: i2c@30a20000 {
+			compatible = "nxp,ii2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x30a20000 0x10000>;
+			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-parent = <&gic>;
+			clocks = <&ccm IMX_CCM_I2C1_CLK 0 0>;
+			rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+			status = "disabled";
+		};
+
+		i2c2: i2c@30a30000 {
+			compatible = "nxp,ii2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x30a30000 0x10000>;
+			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-parent = <&gic>;
+			clocks = <&ccm IMX_CCM_I2C2_CLK 0 0>;
+			rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+			status = "disabled";
+		};
+
+		i2c3: i2c@30a40000 {
+			compatible = "nxp,ii2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x30a40000 0x10000>;
+			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-parent = <&gic>;
+			clocks = <&ccm IMX_CCM_I2C3_CLK 0 0>;
+			rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+			status = "disabled";
+		};
+
+		i2c4: i2c@30a50000 {
+			compatible = "nxp,ii2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x30a50000 0x10000>;
+			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-parent = <&gic>;
+			clocks = <&ccm IMX_CCM_I2C4_CLK 0 0>;
+			rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+			status = "disabled";
+		};
+
+		i2c5: i2c@30ad0000 {
+			compatible = "nxp,ii2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x30ad0000 0x10000>;
+			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-parent = <&gic>;
+			clocks = <&ccm IMX_CCM_I2C5_CLK 0 0>;
+			rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+			status = "disabled";
+		};
+
+		i2c6: i2c@30ae0000 {
+			compatible = "nxp,ii2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x30ae0000 0x10000>;
+			interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-parent = <&gic>;
+			clocks = <&ccm IMX_CCM_I2C6_CLK 0 0>;
+			rdc = <RDC_DOMAIN_PERM(A53_DOMAIN_ID, RDC_DOMAIN_PERM_RW)>;
+			status = "disabled";
+		};
+
 		enet: enet@30be0000 {
 			compatible = "nxp,enet1g";
 			reg = <0x30be0000 DT_SIZE_K(64)>;
diff --git a/dts/arm64/nxp/nxp_mimx91.dtsi b/dts/arm64/nxp/nxp_mimx91.dtsi
new file mode 100644
index 00000000000..872205719bf
--- /dev/null
+++ b/dts/arm64/nxp/nxp_mimx91.dtsi
@@ -0,0 +1,95 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <freq.h>
+#include <arm64/armv8-a.dtsi>
+#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0>;
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+	};
+
+	psci: psci {
+		compatible = "arm,psci-1.1";
+		method = "smc";
+	};
+
+	gic: interrupt-controller@48000000 {
+		compatible = "arm,gic-v3", "arm,gic";
+		reg = <0x48000000 0x10000>, /* GIC Dist */
+		      <0x48040000 0xc0000>; /* GICR (RD_base + SGI_base) */
+		interrupt-controller;
+		#interrupt-cells = <4>;
+		status = "okay";
+	};
+
+	iomuxc: iomuxc@443c0000 {
+		compatible = "nxp,imx-iomuxc";
+		reg = <0x443c0000 DT_SIZE_K(64)>;
+		status = "okay";
+		pinctrl: pinctrl {
+			status = "okay";
+			compatible = "nxp,imx93-pinctrl";
+		};
+	};
+
+	ana_pll: ana_pll@44480000 {
+		compatible = "nxp,imx-ana";
+		reg = <0x44480000 DT_SIZE_K(64)>;
+	};
+
+	ccm: ccm@44450000 {
+		compatible = "nxp,imx-ccm-rev2";
+		reg = <0x44450000 DT_SIZE_K(64)>;
+		#clock-cells = <3>;
+	};
+
+	lpuart1: serial@44380000 {
+		compatible = "nxp,imx-lpuart", "nxp,lpuart";
+		reg = <0x44380000 DT_SIZE_K(64)>;
+		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "irq_0";
+		interrupt-parent = <&gic>;
+		clocks = <&ccm IMX_CCM_LPUART1_CLK 0x6c 24>;
+		status = "disabled";
+	};
+
+	lpuart2: serial@44390000 {
+		compatible = "nxp,imx-lpuart", "nxp,lpuart";
+		reg = <0x44390000 DT_SIZE_K(64)>;
+		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "irq_0";
+		interrupt-parent = <&gic>;
+		clocks = <&ccm IMX_CCM_LPUART2_CLK 0x6c 24>;
+		status = "disabled";
+	};
+};
diff --git a/dts/arm64/nxp/nxp_mimx93_a55.dtsi b/dts/arm64/nxp/nxp_mimx93_a55.dtsi
index 5fa07dbf991..6af6bdfffc9 100644
--- a/dts/arm64/nxp/nxp_mimx93_a55.dtsi
+++ b/dts/arm64/nxp/nxp_mimx93_a55.dtsi
@@ -345,7 +345,7 @@
 		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
 					<GIC_SPI 52 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
 		interrupt-names = "common", "error";
-		clocks = <&ccm IMX_CCM_CAN1_CLK 0x68 14>;
+		clocks = <&ccm IMX_CCM_CAN2_CLK 0x68 14>;
 		clk-source = <0>;
 		status = "disabled";
 	};
diff --git a/dts/arm64/nxp/nxp_mimx95_a55.dtsi b/dts/arm64/nxp/nxp_mimx95_a55.dtsi
index 728539e2205..e10622fac8d 100644
--- a/dts/arm64/nxp/nxp_mimx95_a55.dtsi
+++ b/dts/arm64/nxp/nxp_mimx95_a55.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,6 +7,7 @@
 #include <mem.h>
 #include <freq.h>
 #include <arm64/armv8-a.dtsi>
+#include <dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/clock/imx95_clock.h>
 #include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
 
@@ -115,6 +116,102 @@
 		};
 	};
 
+	lpi2c1: i2c@44340000 {
+		compatible = "nxp,lpi2c";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x44340000 0x4000>;
+		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "irq_0";
+		clocks = <&scmi_clk IMX95_CLK_LPI2C1>;
+		status = "disabled";
+	};
+
+	lpi2c2: i2c@44350000 {
+		compatible = "nxp,lpi2c";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x44350000 0x4000>;
+		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "irq_0";
+		clocks = <&scmi_clk IMX95_CLK_LPI2C2>;
+		status = "disabled";
+	};
+
+	lpi2c3: i2c@42530000 {
+		compatible = "nxp,lpi2c";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x42530000 0x4000>;
+		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "irq_0";
+		clocks = <&scmi_clk IMX95_CLK_LPI2C3>;
+		status = "disabled";
+	};
+
+	lpi2c4: i2c@42540000 {
+		compatible = "nxp,lpi2c";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x42540000 0x4000>;
+		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "irq_0";
+		clocks = <&scmi_clk IMX95_CLK_LPI2C4>;
+		status = "disabled";
+	};
+
+	lpi2c5: i2c@426b0000 {
+		compatible = "nxp,lpi2c";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x426b0000 0x4000>;
+		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "irq_0";
+		clocks = <&scmi_clk IMX95_CLK_LPI2C5>;
+		status = "disabled";
+	};
+
+	lpi2c6: i2c@426c0000 {
+		compatible = "nxp,lpi2c";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x426c0000 0x4000>;
+		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "irq_0";
+		clocks = <&scmi_clk IMX95_CLK_LPI2C6>;
+		status = "disabled";
+	};
+
+	lpi2c7: i2c@426d0000 {
+		compatible = "nxp,lpi2c";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x426d0000 0x4000>;
+		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "irq_0";
+		clocks = <&scmi_clk IMX95_CLK_LPI2C7>;
+		status = "disabled";
+	};
+
+	lpi2c8: i2c@426e0000 {
+		compatible = "nxp,lpi2c";
+		clock-frequency = <I2C_BITRATE_STANDARD>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x426e0000 0x4000>;
+		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "irq_0";
+		clocks = <&scmi_clk IMX95_CLK_LPI2C8>;
+		status = "disabled";
+	};
+
 	lpuart3: serial@42570000 {
 		compatible = "nxp,imx-lpuart", "nxp,lpuart";
 		reg = <0x42570000 DT_SIZE_K(64)>;
@@ -239,4 +336,70 @@
 		#mbox-cells = <1>;
 		status = "disabled";
 	};
+
+	tpm1: tpm@44310000 {
+		compatible = "nxp,tpm-timer";
+		reg = <0x44310000 DT_SIZE_K(64)>;
+		interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "irq_0";
+		interrupt-parent = <&gic>;
+		clocks = <&scmi_clk IMX95_CLK_BUSAON>;
+		prescaler = <1>;
+		status = "disabled";
+	};
+
+	tpm2: tpm@44320000 {
+		compatible = "nxp,tpm-timer";
+		reg = <0x44320000 DT_SIZE_K(64)>;
+		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "irq_0";
+		interrupt-parent = <&gic>;
+		clocks = <&scmi_clk IMX95_CLK_TPM2>;
+		prescaler = <1>;
+		status = "disabled";
+	};
+
+	tpm3: tpm@424e0000 {
+		compatible = "nxp,tpm-timer";
+		reg = <0x424e0000 DT_SIZE_K(64)>;
+		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "irq_0";
+		interrupt-parent = <&gic>;
+		clocks = <&scmi_clk IMX95_CLK_BUSWAKEUP>;
+		prescaler = <1>;
+		status = "disabled";
+	};
+
+	tpm4: tpm@424f0000 {
+		compatible = "nxp,tpm-timer";
+		reg = <0x424f0000 DT_SIZE_K(64)>;
+		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "irq_0";
+		interrupt-parent = <&gic>;
+		clocks = <&scmi_clk IMX95_CLK_TPM4>;
+		prescaler = <1>;
+		status = "disabled";
+	};
+
+	tpm5: tpm@42500000 {
+		compatible = "nxp,tpm-timer";
+		reg = <0x42500000 DT_SIZE_K(64)>;
+		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "irq_0";
+		interrupt-parent = <&gic>;
+		clocks = <&scmi_clk IMX95_CLK_TPM5>;
+		prescaler = <1>;
+		status = "disabled";
+	};
+
+	tpm6: tpm@42510000 {
+		compatible = "nxp,tpm-timer";
+		reg = <0x42510000 DT_SIZE_K(64)>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-names = "irq_0";
+		interrupt-parent = <&gic>;
+		clocks = <&scmi_clk IMX95_CLK_TPM6>;
+		prescaler = <1>;
+		status = "disabled";
+	};
 };
diff --git a/dts/arm64/renesas/rz/rza/r9a07g063.dtsi b/dts/arm64/renesas/rz/rza/r9a07g063.dtsi
new file mode 100644
index 00000000000..fd75543def8
--- /dev/null
+++ b/dts/arm64/renesas/rz/rza/r9a07g063.dtsi
@@ -0,0 +1,333 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <freq.h>
+#include <arm64/armv8-a.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	compatible = "renesas,r9a07g063";
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			clock-frequency = <DT_FREQ_M(1000)>;
+			reg = <0>;
+		};
+	};
+
+	arch_timer: timer {
+		compatible = "arm,armv8-timer";
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 14 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 11 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+				<GIC_PPI 10 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+	};
+
+	soc {
+		interrupt-parent = <&gic>;
+
+		gic: interrupt-controller@11900000 {
+			compatible = "arm,gic-v3", "arm,gic";
+			reg = <0x11900000 0x10000>, /* GICD */
+				<0x11940000 0x20000>; /* GICR */
+			interrupt-controller;
+			#interrupt-cells = <4>;
+			status = "okay";
+		};
+
+		pinctrl: pin-controller@11030000 {
+			compatible = "renesas,rza-pinctrl";
+			reg = <0x11030000 DT_SIZE_K(64)>;
+			reg-names = "pinctrl";
+
+			gpio: gpio-common {
+				compatible = "renesas,rz-gpio-int";
+				interrupts =
+					<GIC_SPI 444 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 445 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 446 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 447 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 448 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 449 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 450 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 451 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 452 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 453 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 454 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 455 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 456 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 457 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 458 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 459 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 460 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 461 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 462 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 463 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 464 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 465 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 466 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 467 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 468 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 469 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 470 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 471 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 472 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 473 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 474 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 475 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				status = "disabled";
+
+				gpio0: gpio@0 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells = <2>;
+					ngpios = <4>;
+					reg = <0x0>;
+					status = "disabled";
+				};
+
+				gpio1: gpio@100 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <5>;
+					reg = <0x100>;
+					status = "disabled";
+				};
+
+				gpio2: gpio@200 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <4>;
+					reg = <0x200>;
+					status = "disabled";
+				};
+
+				gpio3: gpio@300 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <4>;
+					reg = <0x300>;
+					status = "disabled";
+				};
+
+				gpio4: gpio@400 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <6>;
+					reg = <0x400>;
+					status = "disabled";
+				};
+
+				gpio5: gpio@500 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <5>;
+					reg = <0x500>;
+					status = "disabled";
+				};
+
+				gpio6: gpio@600 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <5>;
+					reg = <0x600>;
+					status = "disabled";
+				};
+
+				gpio7: gpio@700 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <5>;
+					reg = <0x700>;
+					status = "disabled";
+				};
+
+				gpio8: gpio@800 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <5>;
+					reg = <0x800>;
+					status = "disabled";
+				};
+
+				gpio9: gpio@900 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <4>;
+					reg = <0x900>;
+					status = "disabled";
+				};
+
+				gpio10: gpio@a00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <5>;
+					reg = <0xa00>;
+					status = "disabled";
+				};
+
+				gpio11: gpio@b00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <4>;
+					reg = <0xb00>;
+					status = "disabled";
+				};
+
+				gpio12: gpio@c00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <2>;
+					reg = <0xc00>;
+					status = "disabled";
+				};
+
+				gpio13: gpio@d00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <5>;
+					reg = <0xd00>;
+					status = "disabled";
+				};
+
+				gpio14: gpio@e00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <3>;
+					reg = <0xe00>;
+					status = "disabled";
+				};
+
+				gpio15: gpio@f00 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <4>;
+					reg = <0xf00>;
+					status = "disabled";
+				};
+
+				gpio16: gpio@1000 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <2>;
+					reg = <0x1000>;
+					status = "disabled";
+				};
+
+				gpio17: gpio@1100 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells= <2>;
+					ngpios = <4>;
+					reg = <0x1100>;
+					status = "disabled";
+				};
+
+				gpio18: gpio@1200 {
+					compatible = "renesas,rz-gpio";
+					gpio-controller;
+					#gpio-cells=<2>;
+					ngpios = <6>;
+					reg = <0x1200>;
+					status = "disabled";
+				};
+			};
+		};
+
+		scif0: serial@1004b800 {
+			compatible = "renesas,rz-scif-uart";
+			channel = <0>;
+			reg = <0x1004b800 0x400>;
+			interrupts = <GIC_SPI 380 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 381 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 382 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 383 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 384 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "bri", "rxi", "txi", "tei";
+			status = "disabled";
+		};
+
+		scif1: serial@1004bc00 {
+			compatible = "renesas,rz-scif-uart";
+			channel = <1>;
+			reg = <0x1004bc00 0x400>;
+			interrupts = <GIC_SPI 385 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 386 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 387 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 388 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 389 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "bri", "rxi", "txi", "tei";
+			status = "disabled";
+		};
+
+		scif2: serial@1004c000 {
+			compatible = "renesas,rz-scif-uart";
+			channel = <2>;
+			reg = <0x1004c000 0x400>;
+			interrupts = <GIC_SPI 390 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 391 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 392 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 393 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 394 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "bri", "rxi", "txi", "tei";
+			status = "disabled";
+		};
+
+		scif3: serial@1004c400 {
+			compatible = "renesas,rz-scif-uart";
+			channel = <3>;
+			reg = <0x1004c400 0x400>;
+			interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 396 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 397 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 399 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 399 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "bri", "rxi", "txi", "tei";
+			status = "disabled";
+		};
+
+		scif4: serial@1004c800 {
+			compatible = "renesas,rz-scif-uart";
+			channel = <4>;
+			reg = <0x1004c800 0x400>;
+			interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 401 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 402 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 403 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
+					<GIC_SPI 404 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+			interrupt-names = "eri", "bri", "rxi", "txi", "tei";
+			status = "disabled";
+		};
+	};
+};
diff --git a/dts/arm64/rockchip/rk3588s.dtsi b/dts/arm64/rockchip/rk3588s.dtsi
new file mode 100644
index 00000000000..4fb37a3113c
--- /dev/null
+++ b/dts/arm64/rockchip/rk3588s.dtsi
@@ -0,0 +1,103 @@
+/*
+ * Copyright 2024 Université Gustave Eiffel
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm64/armv8-a.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
+#include <mem.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x0>;
+		};
+
+		cpu@1 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x100>;
+		};
+
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x200>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a55";
+			reg = <0x300>;
+		};
+
+		cpu@4 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x400>;
+		};
+
+		cpu@5 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x500>;
+		};
+
+		cpu@6 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x600>;
+		};
+
+		cpu@7 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a76";
+			reg = <0x700>;
+		};
+	};
+
+	gic: interrupt-controller@fe600000  {
+		#address-cells = <1>;
+		compatible = "arm,gic-v3", "arm,gic";
+		reg = <0xfe600000 0x10000>, /* GICD */
+		      <0xfe680000 0x100000>; /* GICR */
+		interrupt-controller;
+		#interrupt-cells = <4>;
+		status = "okay";
+	};
+
+	sram0: memory@10000000 {
+		reg = <0x10000000 DT_SIZE_M(128)>;
+	};
+
+	timer {
+		compatible = "arm,armv8-timer";
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 14 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 11 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>,
+			     <GIC_PPI 10 IRQ_TYPE_LEVEL
+			      IRQ_DEFAULT_PRIORITY>;
+	};
+
+	uart2: serial@feb50000  {
+		compatible = "rockchip,rk3588s-uart", "ns16550";
+		reg = <0xfeb50000 0x1000>;
+		interrupt-parent = <&gic>;
+		interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		status = "disabled";
+		reg-shift = <2>;
+		clock-frequency = <350000000>;
+	};
+};
diff --git a/dts/arm64/ti/ti_am62x_a53.dtsi b/dts/arm64/ti/ti_am62x_a53.dtsi
index 183095dd8d0..0050c4a9370 100644
--- a/dts/arm64/ti/ti_am62x_a53.dtsi
+++ b/dts/arm64/ti/ti_am62x_a53.dtsi
@@ -133,4 +133,13 @@
 		reg-shift = <2>;
 		status = "disabled";
 	};
+
+	mbox0: mailbox0@29000000 {
+		compatible = "ti,omap-mailbox";
+		reg = <0x29000000 0x200>;
+		interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&gic>;
+		usr-id = <0>;
+		#mbox-cells = <1>;
+	};
 };
diff --git a/dts/bindings/adc/adi,ad4050-adc.yaml b/dts/bindings/adc/adi,ad4050-adc.yaml
new file mode 100644
index 00000000000..6954bc50a46
--- /dev/null
+++ b/dts/bindings/adc/adi,ad4050-adc.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ADL4050 ADC Controller
+
+compatible: "adi,ad4050-adc"
+
+include: adi,ad405x-adc-base.yaml
diff --git a/dts/bindings/adc/adi,ad4052-adc.yaml b/dts/bindings/adc/adi,ad4052-adc.yaml
new file mode 100644
index 00000000000..647298c8af5
--- /dev/null
+++ b/dts/bindings/adc/adi,ad4052-adc.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ADL4052 ADC Controller
+
+compatible: "adi,ad4052-adc"
+
+include: adi,ad405x-adc-base.yaml
diff --git a/dts/bindings/adc/adi,ad405x-adc-base.yaml b/dts/bindings/adc/adi,ad405x-adc-base.yaml
new file mode 100644
index 00000000000..7a6fc10a039
--- /dev/null
+++ b/dts/bindings/adc/adi,ad405x-adc-base.yaml
@@ -0,0 +1,39 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ADL4050 ADC Controller
+
+compatible: "adi,ad4050-adc"
+
+include: [adc-controller.yaml, spi-device.yaml]
+
+properties:
+  gp1-gpios:
+    type: phandle-array
+    description: |
+      The GP1 signal defaults to DEV_RDY as produced by the
+      adc. The property value should ensure the flags properly
+      describe the signal that is presented to the driver.
+  gp0-gpios:
+    type: phandle-array
+    description: |
+      The GP0 signal defaults to Disabled as produced by the
+      adc. The property value should ensure the flags properly
+      describe the signal that is presented to the driver.
+  conversion-gpios:
+    type: phandle-array
+    description: |
+      The CONV signal.
+    required: true
+  "#io-channel-cells":
+    const: 1
+
+  double-input-range:
+    type: boolean
+    description: |
+      Default ADC input range is 0V to Vref.
+      This option increases the range from 0V to 2 x Vref. Note that this
+      requires VDD >= 2 x Vref.
+
+io-channel-cells:
+  - input
diff --git a/dts/bindings/adc/adi,ad4114-adc.yaml b/dts/bindings/adc/adi,ad4114-adc.yaml
new file mode 100644
index 00000000000..3c9f6aa58ef
--- /dev/null
+++ b/dts/bindings/adc/adi,ad4114-adc.yaml
@@ -0,0 +1,12 @@
+include: [adc-controller.yaml, spi-device.yaml]
+
+compatible: "adi,ad4114-adc"
+
+description: Binding for the ADI AD4114 ADC.
+
+properties:
+  map-inputs:
+    type: array
+    required: true
+    description: |
+      Array of 16 values corresponding to CHANNEL REGISTER 0 TO CHANNEL REGISTER 15.
diff --git a/dts/bindings/adc/adi,ad4130-adc.yaml b/dts/bindings/adc/adi,ad4130-adc.yaml
new file mode 100644
index 00000000000..421aca8f7d9
--- /dev/null
+++ b/dts/bindings/adc/adi,ad4130-adc.yaml
@@ -0,0 +1,100 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Bindings for the ADI AD4130 Analog-to-Digital Converter.
+
+  This device is controlled over SPI and exposes one or more ADC input channels.
+  Each child node corresponds to a channel and supports standard ADC properties
+  such as gain, reference, resolution, and input configuration.
+
+  Sample binding
+
+  &spi0 {
+      status = "okay";
+
+      spi_ad4130: ad4130@0 {
+          compatible = "adi,ad4130-adc";
+          reg = <0x0>;
+          spi-max-frequency = <2700000>;
+          status = "okay";
+
+          #address-cells = <1>;
+          #size-cells = <0>;
+          #io-channel-cells = <1>;
+
+          channel@1 {
+              reg = <1>;
+              zephyr,gain = "ADC_GAIN_1";
+              zephyr,reference = "ADC_REF_INTERNAL";
+              zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+              zephyr,resolution = <24>;
+              zephyr,input-positive = <AD4130_ADC_AIN8>;
+              zephyr,input-negative = <AD4130_ADC_AIN9>;
+          };
+
+          channel@2 {
+              reg = <2>;
+              zephyr,gain = "ADC_GAIN_1";
+              zephyr,reference = "ADC_REF_INTERNAL";
+              zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+              zephyr,resolution = <24>;
+              zephyr,input-positive = <AD4130_ADC_AIN10>;
+              zephyr,input-negative = <AD4130_ADC_AIN11>;
+          };
+      };
+  };
+
+  For input constants such as `AD4130_ADC_AIN8`, refer to the binding header:
+  `include/zephyr/dt-bindings/adc/ad4130-adc.h`
+
+compatible: adi,ad4130-adc
+
+include: [adc-controller.yaml, spi-device.yaml]
+
+properties:
+  bipolar:
+    type: boolean
+    description: |
+      Bipolar configuration for AD4130
+  internal-reference-value:
+    type: int
+    enum: [0, 1]
+    default: 0
+    description: |
+      Internal reference value selection:
+      - AD4130_INTREF_2_5V
+      - AD4130_INTREF_1_25V
+      The default value is set to 0 to provide a higher full-scale range
+      for ADC measurements, which is suitable for a wider variety of
+      general-purpose applications.
+  adc-mode:
+    type: int
+    enum: [0, 1, 2, 3, 4]
+    default: 0
+    description: |
+      ADC operating mode for AD4130
+      - 0 AD4130_CONTINUOUS
+      - 1 AD4130_SINGLE
+      - 2 AD4130_STANDBY
+      - 3 AD4130_POWER_DOWN
+      - 4 AD4130_IDLE
+      The default is set to 0 because the continuous conversion mode
+      is enabled for control setup upon power-up or after reset.
+  clock-type:
+    type: int
+    enum: [0, 1, 2, 3]
+    default: 0
+    description: |
+      Clock selection:
+      - AD4130_INT_76_8_KHZ_OUT_OFF
+      - AD4130_INT_76_8_KHZ_OUT_ON
+      - AD4130_EXT_76_8KHZ
+      - AD4130_EXT_153_6_KHZ_DIV_2
+      The default value is 0, which selects the internal clock without
+      enabling the clock output.
+  "#io-channel-cells":
+    const: 1
+
+io-channel-cells:
+  - input
diff --git a/dts/bindings/adc/adi,ad7124-adc.yaml b/dts/bindings/adc/adi,ad7124-adc.yaml
new file mode 100644
index 00000000000..fa79018db3c
--- /dev/null
+++ b/dts/bindings/adc/adi,ad7124-adc.yaml
@@ -0,0 +1,119 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Bindings for the ADI AD7124 Analog-to-Digital Converter.
+
+compatible: adi,ad7124-adc
+
+include: [adc-controller.yaml, spi-device.yaml]
+
+properties:
+
+  reference-enable:
+    type: boolean
+    description: |
+      Enable internal reference for AD7124
+      - true: Enable internal reference
+      - false: Disable internal reference
+
+  filter-type-mask:
+    type: int
+    default: 0
+    description: |
+      Filter type for AD7124:
+      Each bit set in this mask enables the filter type,
+      with the 0th bit corresponding to the 0th channel,
+      the 1st bit to the 1st channel, and so on.
+      - 0 means AD7124_FILTER_SINC4
+      - 1 means AD7124_FILTER_SINC3
+      The default is set to 0 because the filter type is set to SINC4
+      for all filter setups upon power-up or after reset.
+      Therefore, this setting is considered the default for all channels.
+
+  bipolar-mask:
+    type: int
+    default: 0xFFFF
+    description: |
+      Bipolar configuration for AD7124
+      Each bit set in this mask enables the polarity,
+      with the 0th bit corresponding to the 0th channel,
+      the 1st bit to the 1st channel, and so on.
+      - 0 Unipolar operation selection
+      - 1 Bipolar operation selection
+      The default is set to 0xFFFF because the bipolar configuration
+      is activated for all configuration setups upon power-up or after reset.
+      Therefore, this setting is considered the default for all channels.
+
+  inbuf-enable-mask:
+    type: int
+    default: 0xFFFF
+    description: |
+      Input buffer configuration for AD7124
+      Each bit set in this mask enables the input buffer,
+      with the 0th bit corresponding to the 0th channel,
+      the 1st bit to the 1st channel, and so on.
+      - 0 Analog input pin is unbuffered
+      - 1 Analog input pin is buffered
+      The default is set to 0xFFFF because the analog input buffer
+      is enabled for all configuration setups upon power-up or after reset.
+      Therefore, this setting is considered the default for all channels.
+
+  refbuf-enable-mask:
+    type: int
+    default: 0
+    description: |
+      Reference buffer configuration for AD7124
+      Each bit set in this mask enables the reference buffer,
+      with the 0th bit corresponding to the 0th channel,
+      the 1st bit to the 1st channel, and so on.
+      - 0 Reference input pin is unbuffered
+      - 1 Reference input pin is buffered
+      The default is set to 0 because the reference input buffer
+      is enabled for all configuration setups upon power-up or after reset.
+      Therefore, this setting is considered the default for all channels.
+
+  adc-mode:
+    type: int
+    enum: [0, 1, 2, 3, 4, 5, 6, 7, 8]
+    default: 0
+    description: |
+      ADC operating mode for AD7124
+      - 0 AD7124_CONTINUOUS
+      - 1 AD7124_SINGLE
+      - 2 AD7124_STANDBY
+      - 3 AD7124_POWER_DOWN
+      - 4 AD7124_IDLE
+      - 5 AD7124_IN_ZERO_SCALE_OFF
+      - 6 AD7124_IN_FULL_SCALE_GAIN
+      - 7 AD7124_SYS_ZERO_SCALE_OFF
+      - 8 AD7124_SYS_ZERO_SCALE_GAIN
+      The default is set to 0 because the continuous conversion mode
+      is enabled for control setup upon power-up or after reset.
+
+  power-mode:
+    type: int
+    enum: [0, 1, 2]
+    default: 0
+    description: |
+      Power mode of the ADC for AD7124
+      - 0 AD7124_LOW_POWER_MODE
+      - 1 AD7124_MID_POWER_MODE
+      - 2 AD7124_HIGH_POWER_MODE
+      The default is set to 0 because the low power mode
+      is enabled for control setup upon power-up or after reset.
+
+  active-device:
+    type: int
+    enum: [0, 1]
+    required: true
+    description: |
+      Active device for AD7124
+      - 0 ID_AD7124_4
+      - 1 ID_AD7124_8
+
+  "#io-channel-cells":
+    const: 1
+
+io-channel-cells:
+  - input
diff --git a/dts/bindings/adc/ambiq,adc.yaml b/dts/bindings/adc/ambiq,adc.yaml
index 034eadf6c5d..73f138178e5 100644
--- a/dts/bindings/adc/ambiq,adc.yaml
+++ b/dts/bindings/adc/ambiq,adc.yaml
@@ -5,7 +5,7 @@ description: Ambiq ADC node
 
 compatible: "ambiq,adc"
 
-include: [adc-controller.yaml, pinctrl-device.yaml, ambiq-pwrcfg.yaml]
+include: [adc-controller.yaml, pinctrl-device.yaml]
 properties:
   reg:
     required: true
diff --git a/dts/bindings/adc/atmel,sam0-adc.yaml b/dts/bindings/adc/atmel,sam0-adc.yaml
index e403b2316b6..71c7941bcba 100644
--- a/dts/bindings/adc/atmel,sam0-adc.yaml
+++ b/dts/bindings/adc/atmel,sam0-adc.yaml
@@ -1,4 +1,5 @@
 # Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
+# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
 description: Atmel SAM0 family ADC
@@ -8,6 +9,7 @@ compatible: "atmel,sam0-adc"
 include:
   - name: adc-controller.yaml
   - name: pinctrl-device.yaml
+  - name: atmel,assigned-clocks.yaml
 
 properties:
   reg:
@@ -22,10 +24,11 @@ properties:
   clock-names:
     required: true
 
-  gclk:
-    type: int
+  atmel,assigned-clocks:
+    required: true
+
+  atmel,assigned-clock-names:
     required: true
-    description: generic clock generator source
 
   prescaler:
     type: int
diff --git a/dts/bindings/adc/espressif,esp32-adc.yaml b/dts/bindings/adc/espressif,esp32-adc.yaml
index d3907dba640..9e49bbad83f 100644
--- a/dts/bindings/adc/espressif,esp32-adc.yaml
+++ b/dts/bindings/adc/espressif,esp32-adc.yaml
@@ -3,7 +3,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Espressif ESP32 ADC
+  ESP32 ADC.
+
   Possible available resolutions depends on the used chip.
     - ESP32     < 9,10,11,12 >
     - ESP32-S2  < 12 >
diff --git a/dts/bindings/adc/ite,it51xxx-adc.yaml b/dts/bindings/adc/ite,it51xxx-adc.yaml
new file mode 100644
index 00000000000..851821d26fd
--- /dev/null
+++ b/dts/bindings/adc/ite,it51xxx-adc.yaml
@@ -0,0 +1,29 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE it51xxx ADC
+
+compatible: "ite,it51xxx-adc"
+
+include: [adc-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  interrupts:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  "#io-channel-cells":
+    const: 1
+
+  channel-count:
+    type: int
+    required: true
+    description: the number of ADC channels
+
+io-channel-cells:
+  - input
diff --git a/dts/bindings/adc/raspberrypi,pico-adc.yaml b/dts/bindings/adc/raspberrypi,pico-adc.yaml
index 3fc9236cbb1..741f97e7cc1 100644
--- a/dts/bindings/adc/raspberrypi,pico-adc.yaml
+++ b/dts/bindings/adc/raspberrypi,pico-adc.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 TOKTIA Hrioshi <tokita.hiroshi@fujitsu.com>
 # SPDX-License-Identifier: Apache-2.0
 
-description: RaspberryPi Pico ADC
+description: Raspberry Pi Pico ADC
 
 compatible: "raspberrypi,pico-adc"
 
diff --git a/dts/bindings/adc/realtek,rts5912-adc.yaml b/dts/bindings/adc/realtek,rts5912-adc.yaml
new file mode 100644
index 00000000000..473a5c8acec
--- /dev/null
+++ b/dts/bindings/adc/realtek,rts5912-adc.yaml
@@ -0,0 +1,23 @@
+description: Realtek rts5912 ADC
+
+compatible: "realtek,rts5912-adc"
+
+include: [adc-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  interrupts:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  vref-mv:
+    type: int
+    default: 3300
+    description: The reference voltage of the ADC in mV.
+
+io-channel-cells:
+  - input
diff --git a/dts/bindings/adc/renesas,ra-adc.yaml b/dts/bindings/adc/renesas,ra-adc.yaml
index 1e5f4315ab0..0ce2649529a 100644
--- a/dts/bindings/adc/renesas,ra-adc.yaml
+++ b/dts/bindings/adc/renesas,ra-adc.yaml
@@ -16,11 +16,6 @@ properties:
     required: true
     description: ADC reference voltage (Unit:mV)
 
-  channel-count:
-    type: int
-    required: true
-    description: The number of ADC channels
-
   "#io-channel-cells":
     const: 1
 
diff --git a/dts/bindings/adc/renesas,rz-adc.yaml b/dts/bindings/adc/renesas,rz-adc.yaml
new file mode 100644
index 00000000000..a76d034716d
--- /dev/null
+++ b/dts/bindings/adc/renesas,rz-adc.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: "Renesas RZ ADC"
+
+compatible: "renesas,rz-adc"
+
+include: [adc-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  vref-mv:
+    type: int
+    required: true
+    description: Indicates the reference voltage of the ADC in mV.
+
+  channel-available-mask:
+    type: int
+    required: true
+    description: Mask for ADC channels existed in each board
+
+  "#io-channel-cells":
+    const: 1
+
+io-channel-cells:
+  - input
diff --git a/dts/bindings/adc/silabs,gecko-iadc.yaml b/dts/bindings/adc/silabs,gecko-iadc.yaml
index ac0f66847cd..73b24f8583d 100644
--- a/dts/bindings/adc/silabs,gecko-iadc.yaml
+++ b/dts/bindings/adc/silabs,gecko-iadc.yaml
@@ -5,7 +5,7 @@ description: Silicon Labs Gecko Family IADC
 
 compatible: "silabs,gecko-iadc"
 
-include: adc-controller.yaml
+include: [adc-controller.yaml, pinctrl-device.yaml]
 
 properties:
   reg:
diff --git a/dts/bindings/adc/st,stm32-adc.yaml b/dts/bindings/adc/st,stm32-adc.yaml
index 7df14029cc5..ab4af9663d2 100644
--- a/dts/bindings/adc/st,stm32-adc.yaml
+++ b/dts/bindings/adc/st,stm32-adc.yaml
@@ -2,7 +2,7 @@
 # Copyright (c) 2018, Song Qiang <songqiang1304521@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
-description: ST STM32 family ADC
+description: STM32 ADC
 
 compatible: "st,stm32-adc"
 
diff --git a/dts/bindings/adc/st,stm32f1-adc.yaml b/dts/bindings/adc/st,stm32f1-adc.yaml
index a8c99d677ab..7541591bff9 100644
--- a/dts/bindings/adc/st,stm32f1-adc.yaml
+++ b/dts/bindings/adc/st,stm32f1-adc.yaml
@@ -3,7 +3,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-        ST STM32F1 family ADC
+        STM32F1 ADC
+
         This compatible stands for all ADC blocks similar to the one on STM32F1,
         like STM32F37x.
         Remove the st,adc-clock-source and st,adc-prescaler property.
diff --git a/dts/bindings/adc/st,stm32f4-adc.yaml b/dts/bindings/adc/st,stm32f4-adc.yaml
index a24769e1200..607c8d4fa51 100644
--- a/dts/bindings/adc/st,stm32f4-adc.yaml
+++ b/dts/bindings/adc/st,stm32f4-adc.yaml
@@ -3,7 +3,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-        ST STM32F4 family ADC
+        STM32F4 ADC
+
         This compatible stands for all ADC blocks similar to the one on STM32F4,
         like F2, F7 or L1.
 
diff --git a/dts/bindings/adc/st,stm32n6-adc.yaml b/dts/bindings/adc/st,stm32n6-adc.yaml
new file mode 100644
index 00000000000..da83fd1b9ba
--- /dev/null
+++ b/dts/bindings/adc/st,stm32n6-adc.yaml
@@ -0,0 +1,16 @@
+# Copyright (c) 2024 STMicroelectronics
+
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+        STM32N6 ADC
+
+        This compatible stands for STM32N6 ADC.
+
+compatible: "st,stm32n6-adc"
+
+include:
+  - name: st,stm32-adc.yaml
+    property-blocklist:
+      - st,adc-clock-source
+      - st,adc-prescaler
diff --git a/dts/bindings/adc/st,stm32wb0-adc.yaml b/dts/bindings/adc/st,stm32wb0-adc.yaml
index b2b6599c834..b8b166a49f0 100644
--- a/dts/bindings/adc/st,stm32wb0-adc.yaml
+++ b/dts/bindings/adc/st,stm32wb0-adc.yaml
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
-description: STM32WB0 series Analog-to-Digital Converter
+description: STM32WB0 Analog-to-Digital Converter
 
 compatible: "st,stm32wb0-adc"
 
diff --git a/dts/bindings/adc/ti,ads114s06.yaml b/dts/bindings/adc/ti,ads114s06.yaml
new file mode 100644
index 00000000000..7a9d65e1269
--- /dev/null
+++ b/dts/bindings/adc/ti,ads114s06.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instrument 6 channels 16 bit SPI ADC
+
+compatible: "ti,ads114s06"
+
+include: ti,ads1x4s0x-base.yaml
diff --git a/dts/bindings/adc/ti,ads114s08.yaml b/dts/bindings/adc/ti,ads114s08.yaml
index cf91c11652b..45a376e50e3 100644
--- a/dts/bindings/adc/ti,ads114s08.yaml
+++ b/dts/bindings/adc/ti,ads114s08.yaml
@@ -5,54 +5,4 @@ description: Texas Instrument 12 channels 16 bit SPI ADC
 
 compatible: "ti,ads114s08"
 
-include: [adc-controller.yaml, spi-device.yaml]
-
-bus: ads114s0x
-
-properties:
-  "#io-channel-cells":
-    const: 1
-
-  reset-gpios:
-    type: phandle-array
-    description: "GPIO for reset"
-
-  drdy-gpios:
-    type: phandle-array
-    required: true
-    description: |
-      GPIO for data ready, becomes active when a conversion result is ready
-
-  start-sync-gpios:
-    type: phandle-array
-    description: |
-      GPIO for start/sync, used to signal the ADC that a conversion should be started
-
-  idac-current:
-    type: int
-    enum:
-      - 0
-      - 10
-      - 50
-      - 100
-      - 250
-      - 500
-      - 750
-      - 1000
-      - 1500
-      - 2000
-    default: 0
-    description: |
-      IDAC current in microampere, the default value turns the current source off
-
-  vbias-level:
-    type: int
-    enum:
-      - 0
-      - 1
-    default: 0
-    description: |
-      bias voltage level: 0 - (AVDD+AVSS)/2, 1 - (AVDD+AVSS)/12
-
-io-channel-cells:
-  - input
+include: ti,ads1x4s0x-base.yaml
diff --git a/dts/bindings/adc/ti,ads124s06.yaml b/dts/bindings/adc/ti,ads124s06.yaml
new file mode 100644
index 00000000000..ca113e74626
--- /dev/null
+++ b/dts/bindings/adc/ti,ads124s06.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instrument 6 channels 24 bit SPI ADC
+
+compatible: "ti,ads124s06"
+
+include: ti,ads1x4s0x-base.yaml
diff --git a/dts/bindings/adc/ti,ads124s08.yaml b/dts/bindings/adc/ti,ads124s08.yaml
new file mode 100644
index 00000000000..ab38b3f8925
--- /dev/null
+++ b/dts/bindings/adc/ti,ads124s08.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instrument 12 channels 24 bit SPI ADC
+
+compatible: "ti,ads124s08"
+
+include: ti,ads1x4s0x-base.yaml
diff --git a/dts/bindings/adc/ti,ads1x4s0x-base.yaml b/dts/bindings/adc/ti,ads1x4s0x-base.yaml
new file mode 100644
index 00000000000..be1070a76ee
--- /dev/null
+++ b/dts/bindings/adc/ti,ads1x4s0x-base.yaml
@@ -0,0 +1,54 @@
+# Copyright (c) 2023 SILA Embedded Solutions GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+include: [adc-controller.yaml, spi-device.yaml]
+
+bus: ads1x4s0x
+
+properties:
+  "#io-channel-cells":
+    const: 1
+
+  reset-gpios:
+    type: phandle-array
+    description: "GPIO for reset"
+
+  drdy-gpios:
+    type: phandle-array
+    required: true
+    description: |
+      GPIO for data ready, becomes active when a conversion result is ready
+
+  start-sync-gpios:
+    type: phandle-array
+    description: |
+      GPIO for start/sync, used to signal the ADC that a conversion should be started
+
+  idac-current:
+    type: int
+    enum:
+      - 0
+      - 10
+      - 50
+      - 100
+      - 250
+      - 500
+      - 750
+      - 1000
+      - 1500
+      - 2000
+    default: 0
+    description: |
+      IDAC current in microampere, the default value turns the current source off
+
+  vbias-level:
+    type: int
+    enum:
+      - 0
+      - 1
+    default: 0
+    description: |
+      bias voltage level: 0 - (AVDD+AVSS)/2, 1 - (AVDD+AVSS)/12
+
+io-channel-cells:
+  - input
diff --git a/dts/bindings/arm/atmel,sam0-sercom.yaml b/dts/bindings/arm/atmel,sam0-sercom.yaml
index 30fb3b59176..f3aa21cc281 100644
--- a/dts/bindings/arm/atmel,sam0-sercom.yaml
+++ b/dts/bindings/arm/atmel,sam0-sercom.yaml
@@ -1,8 +1,13 @@
+# Copyright (c) 2024, Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
 description: Atmel SAM0 multi-protocol (UART, SPI, I2C) SERCOM unit
 
 compatible: "atmel,sam0-sercom"
 
-include: base.yaml
+include:
+  - name: base.yaml
+  - name: atmel,assigned-clocks.yaml
 
 properties:
   reg:
diff --git a/dts/bindings/arm/atmel,samd2x-pm.yaml b/dts/bindings/arm/atmel,samd2x-pm.yaml
deleted file mode 100644
index 7fa232b815d..00000000000
--- a/dts/bindings/arm/atmel,samd2x-pm.yaml
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright (c) 2020, Linaro Limited
-# SPDX-License-Identifier: Apache-2.0
-
-description: Atmel SAMD2x Power Manager (PM)
-
-compatible: "atmel,samd2x-pm"
-
-include: [clock-controller.yaml, base.yaml]
-
-properties:
-  reg:
-    required: true
-
-  "#clock-cells":
-    const: 2
-
-clock-cells:
-  - offset
-  - bit
diff --git a/dts/bindings/audio/cirrus,c43l22.yaml b/dts/bindings/audio/cirrus,c43l22.yaml
new file mode 100644
index 00000000000..59c57958565
--- /dev/null
+++ b/dts/bindings/audio/cirrus,c43l22.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2025 Titouan Christophe
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cirrus CS43L22 audio DAC
+
+include: [i2c-device.yaml]
+
+compatible: "cirrus,cs43l22"
+
+properties:
+  reg:
+    required: true
+
+  reset-gpios:
+    required: true
+    type: phandle-array
+    description: |
+      RESET pin
diff --git a/dts/bindings/audio/intel,mic-privacy.yaml b/dts/bindings/audio/intel,mic-privacy.yaml
new file mode 100644
index 00000000000..1747479ffef
--- /dev/null
+++ b/dts/bindings/audio/intel,mic-privacy.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel ADSP Microphone Privacy
+
+compatible: "intel,adsp-mic-privacy"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
diff --git a/dts/bindings/audio/nxp,dmic.yaml b/dts/bindings/audio/nxp,dmic.yaml
index 77f1d0e74a7..eae9bf61c12 100644
--- a/dts/bindings/audio/nxp,dmic.yaml
+++ b/dts/bindings/audio/nxp,dmic.yaml
@@ -32,8 +32,11 @@ child-binding:
   description: |
     NXP DMIC channel. Can be used to configure filtering and gain attributes
     of each channel
-  include: base.yaml
-  compatible: "nxp,dmic-channel"
+  include:
+    - name: base.yaml
+      property-allowlist:
+        - reg
+        - dmas
   properties:
     reg:
       required: true
diff --git a/dts/bindings/audio/ti,tlv320aic3110.yaml b/dts/bindings/audio/ti,tlv320aic3110.yaml
new file mode 100644
index 00000000000..b27a1f2ecaa
--- /dev/null
+++ b/dts/bindings/audio/ti,tlv320aic3110.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 PHYTEC America LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instruments TLV320AIC3110 Audio DAC
+
+compatible: "ti,tlv320aic3110"
+
+include: i2c-device.yaml
diff --git a/dts/bindings/base/base.yaml b/dts/bindings/base/base.yaml
index 485c4dfe7d1..dbc2feb1483 100644
--- a/dts/bindings/base/base.yaml
+++ b/dts/bindings/base/base.yaml
@@ -5,7 +5,16 @@ include: [pm.yaml]
 properties:
   status:
     type: string
-    description: indicates the operational status of a device
+    description: |
+      Indicates the operational status of the hardware or other
+      resource that the node represents. In particular:
+
+        - "okay" means the resource is operational and, for example,
+          can be used by device drivers
+        - "disabled" means the resource is not operational and the system
+          should treat it as if it is not present
+
+      For details, see "2.3.4 status" in Devicetree Specification v0.4.
     enum:
       - "ok" # Deprecated form
       - "okay"
@@ -17,93 +26,189 @@ properties:
   compatible:
     type: string-array
     required: true
-    description: compatible strings
+    description: |
+      This property is a list of strings that essentially define what
+      type of hardware or other resource this devicetree node
+      represents. Each device driver checks for specific compatible
+      property values to find the devicetree nodes that represent
+      resources that the driver should manage.
+
+      The recommended format is "vendor,device", The "vendor" part is
+      an abbreviated name of the vendor. The "device" is usually from
+      the datasheet.
+
+      The compatible property can have multiple values, ordered from
+      most- to least-specific. Having additional values is useful when the
+      device is a specific instance of a more general family, to allow the
+      system to match the most specific driver available.
+
+      For details, see "2.3.1 compatible" in Devicetree Specification v0.4.
 
   reg:
     type: array
-    description: register space
+    description: |
+      Information used to address the device. The value is specific to
+      the device (i.e. is different depending on the compatible
+      property).
+
+      The "reg" property is typically a sequence of (address, length) pairs.
+      Each pair is called a "register block". Values are
+      conventionally written in hex.
+
+      For details, see "2.3.6 reg" in Devicetree Specification v0.4.
 
   reg-names:
     type: string-array
-    description: name of each register space
+    description: |
+      Optional names given to each register block in the "reg" property.
+      For example:
+
+        / {
+             soc {
+                 #address-cells = <1>;
+                 #size-cells = <1>;
+
+                 uart@1000 {
+                     reg = <0x1000 0x2000>, <0x3000 0x4000>;
+                     reg-names = "foo", "bar";
+                 };
+             };
+        };
+
+      The uart@1000 node has two register blocks:
+
+        - one with base address 0x1000, size 0x2000, and name "foo"
+        - another with base address 0x3000, size 0x4000, and name "bar"
 
   interrupts:
     type: array
-    description: interrupts for device
+    description: |
+      Information about interrupts generated by the device, encoded as an array
+      of one or more interrupt specifiers. The format of the data in this property
+      varies by where the device appears in the interrupt tree. Devices with the same
+      "interrupt-parent" will use the same format in their interrupts properties.
+
+      For details, see "2.4 Interrupts and Interrupt Mapping" in
+      Devicetree Specification v0.4.
 
   # Does not follow the 'type: phandle-array' scheme, but gets type-checked
   # by the code. Declare it here just so that other bindings can make it
   # 'required: true' easily if they want to.
   interrupts-extended:
     type: compound
-    description: extended interrupt specifier for device
+    description: |
+      Extended interrupt specifier for device, used as an alternative to
+      the "interrupts" property.
+
+      For details, see "2.4 Interrupts and Interrupt Mapping" in
+      Devicetree Specification v0.4.
 
   interrupt-names:
     type: string-array
-    description: name of each interrupt
+    description: |
+      Optional names given to each interrupt generated by a device.
+      The interrupts themselves are defined in either "interrupts" or
+      "interrupts-extended" properties.
+
+      For details, see "2.4 Interrupts and Interrupt Mapping" in
+      Devicetree Specification v0.4.
 
   interrupt-parent:
     type: phandle
-    description: phandle to interrupt controller node
+    description: |
+      If present, this refers to the node which handles interrupts generated
+      by this device.
+
+      For details, see "2.4 Interrupts and Interrupt Mapping" in
+      Devicetree Specification v0.4.
 
   # description of label should be given in bindings inheriting base.yaml
   # label property is included here to help enforce its type being string
   label:
     type: string
-    description: No description provided for this label
+    description: |
+      Human readable string describing the device. Use of this property is
+      deprecated except as needed on a case-by-case basis.
+
+      For details, see "4.1.2 Miscellaneous Properties" in Devicetree
+      Specification v0.4.
 
   clocks:
     type: phandle-array
-    description: Clock gate information
+    description: |
+      Information about the device's clock providers. In general, this property
+      should follow conventions established in the dt-schema binding:
+
+        https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml
 
   clock-names:
     type: string-array
-    description: name of each clock
+    description: |
+      Optional names given to each clock provider in the "clocks" property.
 
   "#address-cells":
     type: int
-    description: number of address cells in reg property
+    description: |
+      This property encodes the number of <u32> cells used by address fields
+      in "reg" properties in this node's children.
+
+      For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
+      Specification v0.4.
 
   "#size-cells":
     type: int
-    description: number of size cells in reg property
+    description: |
+      This property encodes the number of <u32> cells used by size fields in
+      "reg" properties in this node's children.
+
+      For details, see "2.3.5 #address-cells and #size-cells" in Devicetree
+      Specification v0.4.
 
   dmas:
     type: phandle-array
-    description: DMA channels specifiers
+    description: |
+      DMA channel specifiers relevant to the device.
 
   dma-names:
     type: string-array
-    description: Provided names of DMA channel specifiers
+    description: |
+      Optional names given to the DMA channel specifiers in the "dmas" property.
 
   io-channels:
     type: phandle-array
-    description: IO channels specifiers
+    description: |
+      IO channel specifiers relevant to the device.
 
   io-channel-names:
     type: string-array
-    description: Provided names of IO channel specifiers
+    description: |
+      Optional names given to the IO channel specifiers in the "io-channels" property.
 
   mboxes:
     type: phandle-array
-    description: mailbox / IPM channels specifiers
+    description: |
+      Mailbox / IPM channel specifiers relevant to the device.
     specifier-space: mbox
 
   mbox-names:
     type: string-array
-    description: Provided names of mailbox / IPM channel specifiers
+    description: |
+      Optional names given to the mbox specifiers in the "mboxes" property.
 
   power-domains:
     type: phandle-array
-    description: Power domain specifiers
+    description: |
+      Power domain specifiers relevant to the device.
 
   power-domain-names:
     type: string-array
-    description: Provided names of power domain specifiers
+    description: |
+      Optional names given to the power domain specifiers in the "power-domains" property.
 
   "#power-domain-cells":
     type: int
-    description: Number of cells in power-domains property
+    description: |
+      Number of cells in power-domains property
 
   zephyr,deferred-init:
     type: boolean
diff --git a/dts/bindings/binding-types.txt b/dts/bindings/binding-types.txt
new file mode 100644
index 00000000000..ee2b0c9f5cd
--- /dev/null
+++ b/dts/bindings/binding-types.txt
@@ -0,0 +1,135 @@
+# SPDX-FileCopyrightText: Copyright (c) 2025 The Linux Foundation
+# SPDX-License-Identifier: Apache-2.0
+#
+# Devicetree binding types registry.
+#
+# This file contains the mapping of binding types (folders directly under this
+# file) to their descriptions and provides a definition for each acronym used.
+#
+# The contents of this file are parsed during documentation generation.
+#
+# Anything that starts with a '#' is treated as a comment and ignored.
+# Non-empty lines should be in this format:
+#
+# <binding-type><TAB><Description>
+
+# zephyr-keep-sorted-start
+acpi	ACPI (Advanced Configuration and Power Interface)
+adc	ADC (Analog to Digital Converter)
+alh	ALH (Audio Link Hub)
+arc	ARC architecture
+arm	ARM architecture
+audio	Audio
+auxdisplay	Auxiliary Display
+base	Base
+battery	Battery
+bluetooth	Bluetooth
+cache	Cache
+can	CAN (Controller Area Network)
+charger	Charger
+clock	Clock control
+comparator	Comparator
+coredump	Core dump
+counter	Counter
+cpu	CPU (Central Processing Unit)
+crypto	Cryptographic accelerator
+dac	DAC (Digital to Analog Converter)
+dai	DAI (Digital Audio Interface)
+debug	Debug
+dfpmcch	DFPMCCH
+dfpmccu	DFPMCCU
+disk	Disk
+display	Display
+dma	DMA (Direct Memory Access)
+dsa	DSA (Distributed Switch Architecture)
+edac	EDAC (Error Detection and Correction)
+espi	ESPI (Enhanced Serial Peripheral Interface)
+ethernet	Ethernet
+firmware	Firmware
+flash_controller	Flash controller
+fpga	FPGA (Field Programmable Gate Array)
+fs	File system
+fuel-gauge	Fuel gauge
+gnss	GNSS (Global Navigation Satellite System)
+gpio	GPIO (General Purpose Input/Output) & Headers
+haptics	Haptics
+hda	HDA (High Definition Audio)
+hdlc_rcp_if	IEEE 802.15.4 HDLC RCP interface
+hwinfo	Hardware information
+hwspinlock	Hardware spinlock
+i2c	I2C (Inter-Integrated Circuit)
+i2s	I2S (Inter-Integrated Circuit Sound)
+i3c	I3C (Improved Inter-Integrated Circuit)
+ieee802154	IEEE 802.15.4
+iio	IIO (Industrial I/O)
+input	Input
+interrupt-controller	Interrupt controller
+ipc	IPC (Inter-Processor Communication)
+ipm	IPM (Inter-Processor Mailbox)
+led	LED (Light Emitting Diode)
+led_strip	LED (Light Emitting Diode) strip
+lora	LoRa
+mbox	Mailbox
+mdio	MDIO (Management Data Input/Output)
+memory-controllers	Memory controller
+memory-window	Memory window
+mfd	Multi-Function Device
+mhu	Mailbox Handling Unit
+mipi-dbi	MIPI-DBI (Mobile Industry Processor Interface Display Bus Interface)
+mipi-dsi	MIPI-DSI (Mobile Industry Processor Interface Display Serial Interface)
+misc	Miscellaneous
+mm	Memory management
+mmc	MMC (MultiMedia Card)
+mmu_mpu	MMU (Memory Management Unit) / MPU (Memory Protection Unit)
+modem	Modem
+mspi	Multi-bit SPI (Serial Peripheral Interface)
+mtd	MTD (Memory Technology Device)
+net	Networking
+options	Options
+ospi	OCTOSPI (Octal Serial Peripheral Interface)
+pcie	PCIe (Peripheral Component Interconnect Express)
+peci	PECI (Platform Environment Control Interface)
+phy	PHY
+pinctrl	Pin control
+pm_cpu_ops	Power management CPU operations
+power	Power management
+power-domain	Power domain
+ppc	PPC architecture
+ps2	PS/2 (Personal System/2)
+pwm	PWM (Pulse Width Modulation)
+qspi	QSPI (Quad Serial Peripheral Interface)
+regulator	Regulator
+reserved-memory	Reserved memory
+reset	Reset controller
+retained_mem	Retained memory
+retention	Retention
+riscv	RISC-V architecture
+rng	RNG (Random Number Generator)
+rtc	RTC (Real Time Clock)
+sd	SD (Secure Digital)
+sdhc	SDHC (Secure Digital High Capacity)
+sensor	Sensors
+serial	Serial controller
+shi	SHI (Serial Host Interface)
+sip_svc	Service in Platform
+smbus	SMbus (System Management Bus)
+sound	Sound
+spi	SPI (Serial Peripheral Interface)
+sram	SRAM (Static Random Access Memory)
+stepper	Stepper
+syscon	System controller
+tach	Tachometer
+tcpc	USB Type-C Port Controller
+test	Test
+timer	Timer
+timestamp	Timestamp
+usb	USB (Universal Serial Bus)
+usb-c	USB (Universal Serial Bus) Type-C
+video	Video
+virtualization	Virtualization
+w1	1-Wire
+watchdog	Watchdog
+wifi	Wi-Fi
+xen	Xen
+xspi	xSPI (Expanded Serial Peripheral Interface)
+# zephyr-keep-sorted-stop
diff --git a/dts/bindings/bluetooth/infineon,cyw43xxx-bt-hci.yaml b/dts/bindings/bluetooth/infineon,cyw43xxx-bt-hci.yaml
index 4dcc1f41873..9f447f89e6f 100644
--- a/dts/bindings/bluetooth/infineon,cyw43xxx-bt-hci.yaml
+++ b/dts/bindings/bluetooth/infineon,cyw43xxx-bt-hci.yaml
@@ -21,12 +21,17 @@ description: |
         /* HW Flow control must be enabled for HCI H4 */
         hw-flow-control;
 
-        bt-hci {
+        bt_hci_uart: bt_hci_uart {
+          compatible = "zephyr,bt-hci-uart";
           status = "okay";
-          compatible = "infineon,cyw43xxx-bt-hci";
-          bt-reg-on-gpios = <&gpio_prt3 4 (GPIO_ACTIVE_HIGH)>;
 
-          fw-download-speed = <3000000>;
+          bt-hci {
+            status = "okay";
+            compatible = "infineon,cyw43xxx-bt-hci";
+            bt-reg-on-gpios = <&gpio_prt3 4 (GPIO_ACTIVE_HIGH)>;
+
+            fw-download-speed = <3000000>;
+          };
         };
       };
 
diff --git a/dts/bindings/bluetooth/silabs,siwx91x-bt-hci.yaml b/dts/bindings/bluetooth/silabs,siwx91x-bt-hci.yaml
new file mode 100644
index 00000000000..082005e9188
--- /dev/null
+++ b/dts/bindings/bluetooth/silabs,siwx91x-bt-hci.yaml
@@ -0,0 +1,13 @@
+description: Bluetooth HCI on Silabs boards
+
+compatible: "silabs,siwx91x-bt-hci"
+
+include: bt-hci.yaml
+
+properties:
+  bt-hci-name:
+    default: "sl:bt:siwx91x"
+  bt-hci-bus:
+    default: "virtual"
+  bt-hci-quirks:
+    default: ["no-reset"]
diff --git a/dts/bindings/cache/andestech,l2c.yaml b/dts/bindings/cache/andestech,l2c.yaml
index 6d9344ad7cd..43f990a9658 100644
--- a/dts/bindings/cache/andestech,l2c.yaml
+++ b/dts/bindings/cache/andestech,l2c.yaml
@@ -4,8 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-description:
-  This is a representation of AndesTech L2 cache node
+description: AndesTech L2 cache
 
 compatible: "andestech,l2c"
 
diff --git a/dts/bindings/can/atmel,sam0-can.yaml b/dts/bindings/can/atmel,sam0-can.yaml
index 7002386c922..25e8eede707 100644
--- a/dts/bindings/can/atmel,sam0-can.yaml
+++ b/dts/bindings/can/atmel,sam0-can.yaml
@@ -1,3 +1,6 @@
+# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
 description: Specialization of Bosch m_can CAN FD controller for Atmel SAM0
 
 compatible: "atmel,sam0-can"
@@ -5,6 +8,7 @@ compatible: "atmel,sam0-can"
 include:
   - name: bosch,m_can-base.yaml
   - name: pinctrl-device.yaml
+  - name: atmel,assigned-clocks.yaml
 
 properties:
   reg:
@@ -22,6 +26,12 @@ properties:
   clock-names:
     required: true
 
+  atmel,assigned-clocks:
+    required: true
+
+  atmel,assigned-clock-names:
+    required: true
+
   divider:
     type: int
     required: true
diff --git a/dts/bindings/can/espressif,esp32-twai.yaml b/dts/bindings/can/espressif,esp32-twai.yaml
index cf0d19c23ae..cc77536a701 100644
--- a/dts/bindings/can/espressif,esp32-twai.yaml
+++ b/dts/bindings/can/espressif,esp32-twai.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 Henrik Brix Andersen <henrik@brixandersen.dk>
 # SPDX-License-Identifier: Apache-2.0
 
-description: Espressif ESP32 Two-Wire Automotive Interface (TWAI)
+description: ESP32 Two-Wire Automotive Interface (TWAI)
 
 compatible: "espressif,esp32-twai"
 
diff --git a/dts/bindings/can/infineon,xmc4xxx-can-node.yaml b/dts/bindings/can/infineon,xmc4xxx-can-node.yaml
index 8fa50922ace..82286874657 100644
--- a/dts/bindings/can/infineon,xmc4xxx-can-node.yaml
+++ b/dts/bindings/can/infineon,xmc4xxx-can-node.yaml
@@ -16,7 +16,7 @@ properties:
   interrupts:
     required: true
 
-  clock_div8:
+  clock-div8:
     description: Option enables clock divide by a factor of 8.
     type: boolean
 
diff --git a/dts/bindings/can/microchip,mcp251xfd.yaml b/dts/bindings/can/microchip,mcp251xfd.yaml
index 168314547ef..ed63da20b4f 100644
--- a/dts/bindings/can/microchip,mcp251xfd.yaml
+++ b/dts/bindings/can/microchip,mcp251xfd.yaml
@@ -65,6 +65,10 @@ properties:
       is not set, then an internal clock (typically 40MHz or 20MHz) will be
       output on CLKO pin instead.
 
+  xstby-enable:
+    type: boolean
+    description: Enables standby pin control on GPIO0.
+
   clko-div:
     type: int
     description: The factor to divide the system clock for CLKO pin.
diff --git a/dts/bindings/can/nordic,nrf-can.yaml b/dts/bindings/can/nordic,nrf-can.yaml
index 3834b6763f5..805ddf3320c 100644
--- a/dts/bindings/can/nordic,nrf-can.yaml
+++ b/dts/bindings/can/nordic,nrf-can.yaml
@@ -17,6 +17,9 @@ properties:
   clocks:
     required: true
 
+  clock-names:
+    required: true
+
   pinctrl-0:
     required: true
 
diff --git a/dts/bindings/can/renesas,ra-canfd-global.yaml b/dts/bindings/can/renesas,ra-canfd-global.yaml
index a737b571ee2..c22688eac29 100644
--- a/dts/bindings/can/renesas,ra-canfd-global.yaml
+++ b/dts/bindings/can/renesas,ra-canfd-global.yaml
@@ -13,3 +13,13 @@ properties:
 
   clocks:
     required: true
+
+  dll-min-freq:
+    type: int
+    description: |
+      Specifies the Data Link Layer clock limit on this device: DLL clock frequency > dll-min-freq.
+
+  dll-max-freq:
+    type: int
+    description: |
+      Specifies the Data Link Layer clock limit on this device: DLL clock frequency < dll-max-freq.
diff --git a/dts/bindings/can/st,stm32-fdcan.yaml b/dts/bindings/can/st,stm32-fdcan.yaml
index f4cfb310dac..7df1123ace9 100644
--- a/dts/bindings/can/st,stm32-fdcan.yaml
+++ b/dts/bindings/can/st,stm32-fdcan.yaml
@@ -1,4 +1,4 @@
-description: ST STM32 FDCAN CAN FD controller
+description: STM32 FDCAN CAN FD controller
 
 compatible: "st,stm32-fdcan"
 
diff --git a/dts/bindings/can/st,stm32h7-fdcan.yaml b/dts/bindings/can/st,stm32h7-fdcan.yaml
index 14f6fad61c5..ca42621d649 100644
--- a/dts/bindings/can/st,stm32h7-fdcan.yaml
+++ b/dts/bindings/can/st,stm32h7-fdcan.yaml
@@ -1,4 +1,4 @@
-description: ST STM32H7 series FDCAN CAN FD controller
+description: STM32H7 series FDCAN CAN FD controller
 
 compatible: "st,stm32h7-fdcan"
 
diff --git a/dts/bindings/charger/nxp,pf1550-charger.yaml b/dts/bindings/charger/nxp,pf1550-charger.yaml
new file mode 100644
index 00000000000..c1492211438
--- /dev/null
+++ b/dts/bindings/charger/nxp,pf1550-charger.yaml
@@ -0,0 +1,58 @@
+# Copyright (c), 2024 Arduino SA
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP PF1550 battery charger
+
+include: battery.yaml
+
+compatible: "nxp,pf1550-charger"
+
+properties:
+  constant-charge-voltage-max-microvolt:
+    required: true
+
+  constant-charge-current-max-microamp:
+    required: true
+
+  pf1550,vbus-current-limit-microamp:
+    type: int
+    required: true
+    description: |
+      VBUS current limit in microamperes.
+
+  pf1550,system-voltage-min-threshold-microvolt:
+    type: int
+    required: true
+    enum:
+      - 3500000
+      - 3700000
+      - 4300000
+    description: |
+      System voltage minimum threshold.
+
+  pf1550,thermistor-monitoring-mode:
+    type: string
+    required: true
+    enum:
+      - "disabled"
+      - "thermistor"
+      - "JEITA-1"
+      - "JEITA-2"
+    description: |
+      Thermistor monitoring mode.
+      Refer to ThrmCfg register description and Table 2 for details.
+
+  pf1550,int-gpios:
+    type: phandle-array
+    required: true
+    description: Interrupt pin
+
+  pf1550,led-behaviour:
+    type: string
+    required: true
+    enum:
+      - "on-in-charging-flash-in-fault"
+      - "flash-in-charging-on-in-fault"
+      - "manual-off"
+    description: |
+      Behaviour for charger LED.
diff --git a/dts/bindings/charger/ti,bq24190.yaml b/dts/bindings/charger/ti,bq24190.yaml
index 1b1ad9e97ca..78aa7654b57 100644
--- a/dts/bindings/charger/ti,bq24190.yaml
+++ b/dts/bindings/charger/ti,bq24190.yaml
@@ -1,7 +1,23 @@
 # Copyright 2023 Cirrus Logic, Inc.
+# Copyright 2025 Palta Tech, S.A
 # SPDX-License-Identifier: Apache-2.0
 
-description: Texas Instruments family of BQ24190 of charging ICs
+description: |
+  BQ2419x family of charging ICs.
+
+  BQ2419x I2C controlled, 1-Cell, 4.5-A, USB/Adapter Charger with Narrow VDC Power Path Management
+  and USB OTG
+
+  This charger is represented by device tree child node, e.g:
+
+  charger: bq24190@6b {
+      compatible = "ti,bq24190";
+      reg = <0x6b>;
+      status = "okay";
+
+      constant-charge-current-max-microamp = <1000000>;
+      constant-charge-voltage-max-microvolt = <3800000>;
+  };
 
 include: [battery.yaml, i2c-device.yaml]
 
@@ -10,9 +26,17 @@ compatible: "ti,bq24190"
 properties:
   constant-charge-current-max-microamp:
     required: true
+    description: |
+      The charge current target for the constant current phase of the charge profile.
+      This value will be set at initialization time. Range: 512 mA to 4.544 A.
+      The value specified will be rounded down to the closest implemented value.
 
   constant-charge-voltage-max-microvolt:
     required: true
+    description: |
+      The voltage regulation target for the constant voltage phase of the battery charging profile.
+      This value will be set at initialization time. Range: 3.504 V to 4.400 V.
+      The value specified will be rounded down to the closest implemented value.
 
   ce-gpios:
     type: phandle-array
diff --git a/dts/bindings/charger/ti,bq25713.yaml b/dts/bindings/charger/ti,bq25713.yaml
new file mode 100644
index 00000000000..1eda1664f35
--- /dev/null
+++ b/dts/bindings/charger/ti,bq25713.yaml
@@ -0,0 +1,48 @@
+# Copyright 2025 Palta Tech, S.A
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  BQ25713 I2C battery charge controller IC.
+
+  BQ25713 targets 1s to 4s Cell, USB Power Delivery/Adapter Charger with
+  Narrow VDC Power Path Management and Processor Hot Monitor
+
+  This charger is represented by device tree child node, e.g:
+
+  charger: bq25713@6b {
+      compatible = "ti,bq25713";
+      reg = <0x6b>;
+      status = "okay";
+
+      constant-charge-current-max-microamp = <1000000>;
+      constant-charge-voltage-max-microvolt = <3800000>;
+      system-voltage-min-threshold-microvolt = <3328000>;
+  };
+
+include: [battery.yaml, i2c-device.yaml]
+
+compatible: "ti,bq25713"
+
+properties:
+  constant-charge-current-max-microamp:
+    required: true
+    description: |
+      The charge current target for the constant current phase of the charge profile.
+      This value will be set at initialization time. Range: 0 mA to 8.128 A.
+      The value specified will be rounded down to the closest implemented value.
+
+  constant-charge-voltage-max-microvolt:
+    required: true
+    description: |
+      The voltage regulation target for the constant voltage phase of the battery charging profile.
+      This value will be set at initialization time. Range: 4.2 V 1S to 16.8 V 4S.
+      The value specified will be rounded down to the closest implemented value.
+
+  system-voltage-min-threshold-microvolt:
+    type: int
+    required: true
+    description: |
+      Minimum system voltage.
+      Voltage that will be set above when the system voltage drops this level.
+      This value will be set at initialization time. Range: 1.024 V to 16.128 V.
+      The value specified will be rounded down to the closest implemented value.
diff --git a/dts/bindings/charger/x-powers,axp2101-charger.yaml b/dts/bindings/charger/x-powers,axp2101-charger.yaml
new file mode 100644
index 00000000000..d1970411f87
--- /dev/null
+++ b/dts/bindings/charger/x-powers,axp2101-charger.yaml
@@ -0,0 +1,77 @@
+# Copyright 2025 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Charger part of the AXP2101 PMU MFD device.
+
+  This charger should be instantiated as child of the AXP2101 MFD device, i.e.
+
+  axp2101@34 {
+    compatible = "x-powers,axp2101";
+    reg = <0x34>;
+
+    charger {
+      compatible = "x-powers,axp2101-charger";
+      constant-charge-current-max-microamp = <300000>;
+      constant-charge-voltage-max-microvolt = <4200000>;
+    };
+
+    regulators {
+    ...
+    }
+  }
+
+compatible: "x-powers,axp2101-charger"
+
+on-bus: axp2101
+
+include:
+  - base.yaml
+  - battery.yaml
+
+properties:
+  # Extending the definition from battery.yaml
+  constant-charge-current-max-microamp:
+    required: true
+    enum:
+      - 100000
+      - 125000
+      - 150000
+      - 175000
+      - 200000
+      - 300000
+      - 400000
+      - 500000
+      - 600000
+      - 700000
+      - 800000
+      - 900000
+      - 1000000
+
+  # Extending the definition from battery.yaml
+  constant-charge-voltage-max-microvolt:
+    required: true
+    enum:
+      - 4000000
+      - 4100000
+      - 4200000
+      - 4350000
+      - 4400000
+
+  # Extending the definition from battery.yaml
+  charge-term-current-microamp:
+    enum:
+      - 0
+      - 25000
+      - 50000
+      - 75000
+      - 100000
+      - 125000
+      - 150000
+      - 200000
+
+  vbackup-enable:
+    type: boolean
+    description:
+      Enable Vbackup on boot. This is normally used to charge a button battery
+      that is used by some RTC IC.
diff --git a/dts/bindings/clock/atmel,assigned-clocks.yaml b/dts/bindings/clock/atmel,assigned-clocks.yaml
new file mode 100644
index 00000000000..be8c01779be
--- /dev/null
+++ b/dts/bindings/clock/atmel,assigned-clocks.yaml
@@ -0,0 +1,11 @@
+# Copyright (c) 2024, Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+properties:
+  atmel,assigned-clocks:
+    type: phandle-array
+    description: Assigned-clock information
+
+  atmel,assigned-clock-names:
+    type: string-array
+    description: Name of each assigned-clock
diff --git a/dts/bindings/clock/atmel,sam0-gclk.yaml b/dts/bindings/clock/atmel,sam0-gclk.yaml
new file mode 100644
index 00000000000..9d1059e50c6
--- /dev/null
+++ b/dts/bindings/clock/atmel,sam0-gclk.yaml
@@ -0,0 +1,66 @@
+# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAMD0 Generic Clock Controller (GCLK)
+
+compatible: "atmel,sam0-gclk"
+
+include:
+  - base.yaml
+  - clock-controller.yaml
+  - atmel,assigned-clocks.yaml
+
+properties:
+  reg:
+    required: true
+
+  "#clock-cells":
+    const: 1
+    description: |
+      - The ID cell is the peripheral identification.
+
+      These information are used on GCLK->CLKCTRL register to select the
+      clock for an specific peripheral.
+
+      Example 1: Connect the XOSC32K to RTC on SAMD2x
+        Assuming that generator 2 have the following configuration:
+          GLKC->GENCTRL:
+            SRC: 5 (XOSC32K)
+            ID:  2 (Generator 2)
+
+        Then to enable the clock to the peripheral
+        Generator:     2
+        Identificator: 4 (GCLK_RTC)
+
+          &rtc {
+            /* The peripheral is fixed and it is defined at soc devictree
+             * clocks property
+             */
+            clocks = <&gclk 4>, <&pm 0x18 5>;
+            clock-names = "GCLK", "PM";
+
+            /* The generator is user selectable and because of that it is
+             * defined at board
+             */
+            atmel,assigned-clocks = <&gclk 2>;
+            atmel,assigned-clock-names = "GCLK";
+          };
+
+      Example 2: Connect the XOSC32K to RTC on SAMD5x
+        In the SAMD5x the RTC is direct connected on the OSC32KCTRL and no
+        generator is used. See atmel,sam0-osc32kctrl.yaml for reference.
+
+  "#atmel,assigned-clock-cells":
+    required: true
+    type: int
+    const: 1
+    description: |
+      - The GEN cell is an integer number that represents the index of
+      the generic clock generator. It is usually a number between 0~8
+      but could be more depending of the SoC.
+
+clock-cells:
+  - id
+
+atmel,assigned-clock-cells:
+  - gen
diff --git a/dts/bindings/clock/atmel,sam0-mclk.yaml b/dts/bindings/clock/atmel,sam0-mclk.yaml
new file mode 100644
index 00000000000..b71d81baa3e
--- /dev/null
+++ b/dts/bindings/clock/atmel,sam0-mclk.yaml
@@ -0,0 +1,48 @@
+# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM0 Main Clock Controller (MCLK)
+
+compatible: "atmel,sam0-mclk"
+
+include:
+  - base.yaml
+  - clock-controller.yaml
+
+properties:
+  reg:
+    required: true
+
+  "#clock-cells":
+    const: 2
+    description: |
+      - The OFFSET cell is an address of a bus mask. The buses can be
+      AHB and APB[A-D]. Each bus mask can enable a paripheral clock
+      selecting the BIT position in the mask.
+      - The BIT cell is the peripheral bit mask.
+
+      These information are used on PM and MCLK register to select the
+      clock for an specific peripheral. The generator 2 is used on this
+      example and can be defined by the user at board.
+
+      Example: Enable SERCOM0 on SAMD21
+        &sercom0 {
+          clocks = <&gclk 0x14>, <&pm 0x20 2>;
+          clock-names = "GCLK", "PM";
+
+          atmel,assigned-clocks = <&gclk 2>;
+          atmel,assigned-clock-names = "GCLK";
+        };
+
+      Example: Enable SERCOM0 on SAME54
+        &sercom0 {
+          clocks = <&gclk 7>, <&mclk 0x14 12>;
+          clock-names = "GCLK", "MCLK";
+
+          atmel,assigned-clocks = <&gclk 2>;
+          atmel,assigned-clock-names = "GCLK";
+        };
+
+clock-cells:
+  - offset
+  - bit
diff --git a/dts/bindings/clock/atmel,sam0-osc32kctrl.yaml b/dts/bindings/clock/atmel,sam0-osc32kctrl.yaml
new file mode 100644
index 00000000000..e2f25565d91
--- /dev/null
+++ b/dts/bindings/clock/atmel,sam0-osc32kctrl.yaml
@@ -0,0 +1,38 @@
+# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Atmel SAM0 32kHz Oscillator Controller (OSC32KCTRL)
+
+compatible: "atmel,sam0-osc32kctrl"
+
+include:
+  - base.yaml
+  - clock-controller.yaml
+  - atmel,assigned-clocks.yaml
+
+properties:
+  reg:
+    required: true
+
+  "#clock-cells":
+    const: 0
+
+  "#atmel,assigned-clock-cells":
+    required: true
+    type: int
+    const: 1
+    description: |
+      It selects the OSC32CTRL clock to be routed to RTC peripheral
+
+      Example: Connect the XOSC32K to RTC on SAMD5x
+
+        &rtc {
+          clocks = <&mclk 0x14 9 &osc32kctrl>;
+          clock-names = "MCLK", "OSC32KCTRL";
+
+          atmel,assigned-clocks = <&osc32kctrl 4>;
+          atmel,assigned-clock-names = "OSC32KCTRL";
+        };
+
+atmel,assigned-clock-cells:
+  - src
diff --git a/dts/bindings/clock/atmel,samc2x-gclk.yaml b/dts/bindings/clock/atmel,samc2x-gclk.yaml
deleted file mode 100644
index d1e97272df7..00000000000
--- a/dts/bindings/clock/atmel,samc2x-gclk.yaml
+++ /dev/null
@@ -1,18 +0,0 @@
-# Copyright (c) 2022 Kamil Serwus
-# SPDX-License-Identifier: Apache-2.0
-
-description: Atmel SAMC2x Generic Clock Controller (GCLK)
-
-compatible: "atmel,samc2x-gclk"
-
-include: [clock-controller.yaml, base.yaml]
-
-properties:
-  reg:
-    required: true
-
-  "#clock-cells":
-    const: 1
-
-clock-cells:
-  - periph_ch
diff --git a/dts/bindings/clock/atmel,samc2x-mclk.yaml b/dts/bindings/clock/atmel,samc2x-mclk.yaml
deleted file mode 100644
index 227fa5246c0..00000000000
--- a/dts/bindings/clock/atmel,samc2x-mclk.yaml
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright (c) 2022, Kamil Serwus
-# SPDX-License-Identifier: Apache-2.0
-
-description: Atmel SAMC2x Generic Clock Controller (MCLK)
-
-compatible: "atmel,samc2x-mclk"
-
-include: [clock-controller.yaml, base.yaml]
-
-properties:
-  reg:
-    required: true
-
-  "#clock-cells":
-    const: 2
-
-clock-cells:
-  - offset
-  - bit
diff --git a/dts/bindings/clock/atmel,samd2x-gclk.yaml b/dts/bindings/clock/atmel,samd2x-gclk.yaml
deleted file mode 100644
index f5188aef05f..00000000000
--- a/dts/bindings/clock/atmel,samd2x-gclk.yaml
+++ /dev/null
@@ -1,18 +0,0 @@
-# Copyright (c) 2020, Linaro Limited
-# SPDX-License-Identifier: Apache-2.0
-
-description: Atmel SAMD2x Generic Clock Controller (GCLK)
-
-compatible: "atmel,samd2x-gclk"
-
-include: [clock-controller.yaml, base.yaml]
-
-properties:
-  reg:
-    required: true
-
-  "#clock-cells":
-    const: 1
-
-clock-cells:
-  - clkctrl_id
diff --git a/dts/bindings/clock/atmel,samd5x-gclk.yaml b/dts/bindings/clock/atmel,samd5x-gclk.yaml
deleted file mode 100644
index 68fd94b44eb..00000000000
--- a/dts/bindings/clock/atmel,samd5x-gclk.yaml
+++ /dev/null
@@ -1,18 +0,0 @@
-# Copyright (c) 2020, Linaro Limited
-# SPDX-License-Identifier: Apache-2.0
-
-description: Atmel SAMD5x Generic Clock Controller (GCLK)
-
-compatible: "atmel,samd5x-gclk"
-
-include: [clock-controller.yaml, base.yaml]
-
-properties:
-  reg:
-    required: true
-
-  "#clock-cells":
-    const: 1
-
-clock-cells:
-  - periph_ch
diff --git a/dts/bindings/clock/atmel,samd5x-mclk.yaml b/dts/bindings/clock/atmel,samd5x-mclk.yaml
deleted file mode 100644
index 603196570da..00000000000
--- a/dts/bindings/clock/atmel,samd5x-mclk.yaml
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright (c) 2020, Linaro Limited
-# SPDX-License-Identifier: Apache-2.0
-
-description: Atmel SAMD5x Generic Clock Controller (MCLK)
-
-compatible: "atmel,samd5x-mclk"
-
-include: [clock-controller.yaml, base.yaml]
-
-properties:
-  reg:
-    required: true
-
-  "#clock-cells":
-    const: 2
-
-clock-cells:
-  - offset
-  - bit
diff --git a/dts/bindings/clock/atmel,saml2x-gclk.yaml b/dts/bindings/clock/atmel,saml2x-gclk.yaml
deleted file mode 100644
index 3c9020d5052..00000000000
--- a/dts/bindings/clock/atmel,saml2x-gclk.yaml
+++ /dev/null
@@ -1,18 +0,0 @@
-# Copyright (c) 2021 Argentum Systems Ltd.
-# SPDX-License-Identifier: Apache-2.0
-
-description: Atmel SAML2x Generic Clock Controller (GCLK)
-
-compatible: "atmel,saml2x-gclk"
-
-include: [clock-controller.yaml, base.yaml]
-
-properties:
-  reg:
-    required: true
-
-  "#clock-cells":
-    const: 1
-
-clock-cells:
-  - periph_ch
diff --git a/dts/bindings/clock/atmel,saml2x-mclk.yaml b/dts/bindings/clock/atmel,saml2x-mclk.yaml
deleted file mode 100644
index ed89ba36f12..00000000000
--- a/dts/bindings/clock/atmel,saml2x-mclk.yaml
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright (c) 2021 Argentum Systems Ltd.
-# SPDX-License-Identifier: Apache-2.0
-
-description: Atmel SAML2x Generic Clock Controller (MCLK)
-
-compatible: "atmel,saml2x-mclk"
-
-include: [clock-controller.yaml, base.yaml]
-
-properties:
-  reg:
-    required: true
-
-  "#clock-cells":
-    const: 2
-
-clock-cells:
-  - offset
-  - bit
diff --git a/dts/bindings/clock/ite,it51xxx-ecpm.yaml b/dts/bindings/clock/ite,it51xxx-ecpm.yaml
new file mode 100644
index 00000000000..460828acdd1
--- /dev/null
+++ b/dts/bindings/clock/ite,it51xxx-ecpm.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE it51xxx ECPM (EC Clock and Power Management Controller) node
+
+compatible: "ite,it51xxx-ecpm"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  pll-frequency:
+    type: int
+    required: true
+    enum:
+      - 0
+      - 1
+      - 2
+      - 3
+    description: |
+      0 = PLL_18400_KHZ,
+      1 = PLL_32300_KHZ,
+      2 = PLL_64500_KHZ,
+      3 = PLL_48000_KHZ,
+
+  "#clock-cells":
+    const: 2
+
+clock-cells:
+  - ctrl
+  - bits
diff --git a/dts/bindings/clock/mediatek,mt8195_cpuclk.yaml b/dts/bindings/clock/mediatek,mt8195_cpuclk.yaml
index ea85d99580a..75d4cb1ed3e 100644
--- a/dts/bindings/clock/mediatek,mt8195_cpuclk.yaml
+++ b/dts/bindings/clock/mediatek,mt8195_cpuclk.yaml
@@ -4,13 +4,13 @@
 description: MediaTek Audio DSP CPU Frequency Control
 compatible: "mediatek,mt8195_cpuclk"
 properties:
-  freqs_mhz:
+  freqs-mhz:
     type: array
     description: Available frequencies in ascending order
     required: true
   reg:
     type: array
-  cg_reg:
+  cg-reg:
     type: int
-  pll_ctrl_reg:
+  pll-ctrl-reg:
     type: int
diff --git a/dts/bindings/clock/renesas,ra-cgc-pclk.yaml b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml
index 798b1d3569f..c36589d19e1 100644
--- a/dts/bindings/clock/renesas,ra-cgc-pclk.yaml
+++ b/dts/bindings/clock/renesas,ra-cgc-pclk.yaml
@@ -8,6 +8,10 @@ compatible: "renesas,ra-cgc-pclk"
 include: [clock-controller.yaml, base.yaml]
 
 properties:
+  clock-frequency:
+    type: int
+    description: clock frequency (Hz)
+
   div:
     type: int
     required: true
diff --git a/dts/bindings/clock/renesas,rz-cpg.yml b/dts/bindings/clock/renesas,rz-cpg.yml
new file mode 100644
index 00000000000..5124cd3cb12
--- /dev/null
+++ b/dts/bindings/clock/renesas,rz-cpg.yml
@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Renesas Electronics Corporation24
+# SPDX-License-Identifier: Apache-2.0
+
+description: RZ Clock Pulse Generator
+compatible: "renesas,rz-cpg"
+
+include: [base.yaml, clock-controller.yaml]
+
+properties:
+
+  "#clock-cells":
+    const: 1
+
+clock-cells:
+  - clk-id
diff --git a/dts/bindings/clock/renesas,rza2m-cpg.yaml b/dts/bindings/clock/renesas,rza2m-cpg.yaml
new file mode 100644
index 00000000000..7aba111b15d
--- /dev/null
+++ b/dts/bindings/clock/renesas,rza2m-cpg.yaml
@@ -0,0 +1,7 @@
+# Copyright (c) 2025 Renesas Electronics Corporation24
+# SPDX-License-Identifier: Apache-2.0
+
+description: RZ/A2M Clock Pulse Generator
+compatible: "renesas,rza2m-cpg"
+
+include: renesas,rz-cpg.yml
diff --git a/dts/bindings/clock/silabs,siwx91x-clock.yaml b/dts/bindings/clock/silabs,siwx91x-clock.yaml
new file mode 100644
index 00000000000..80bf83aadb0
--- /dev/null
+++ b/dts/bindings/clock/silabs,siwx91x-clock.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Clocks embedded on Silabs SiWx91x chips
+
+compatible: "silabs,siwx91x-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  "#clock-cells":
+    const: 1
+
+clock-cells:
+  - clkid
diff --git a/dts/bindings/clock/st,stm32-clock-mux.yaml b/dts/bindings/clock/st,stm32-clock-mux.yaml
index 1798ee686d2..afa7c9e643e 100644
--- a/dts/bindings/clock/st,stm32-clock-mux.yaml
+++ b/dts/bindings/clock/st,stm32-clock-mux.yaml
@@ -3,8 +3,9 @@
 
 description: |
         STM32 Clock multiplexer
+
         Describes a clock multiplexer, such as per_ck on STM32H7 or
-        CLK48 on STM32L5.
+        CLK48 on STM32WB.
         The only property of this node is to select a clock input.
         For instance:
                 &perck {
@@ -20,3 +21,8 @@ include:
       - status
       - compatible
       - clocks
+
+properties:
+
+  clocks:
+    required: true
diff --git a/dts/bindings/clock/st,stm32-rcc.yaml b/dts/bindings/clock/st,stm32-rcc.yaml
index 4d7aa666cc3..6199eae4a9c 100644
--- a/dts/bindings/clock/st,stm32-rcc.yaml
+++ b/dts/bindings/clock/st,stm32-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32 Reset and Clock controller node.
+  STM32 RCC (Reset and Clock controller).
+
   This node is in charge of system clock ('SYSCLK') source selection and controlling
   clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
 
diff --git a/dts/bindings/clock/st,stm32c0-hsi-clock.yaml b/dts/bindings/clock/st,stm32c0-hsi-clock.yaml
index a19fd6f605d..55c91808818 100644
--- a/dts/bindings/clock/st,stm32c0-hsi-clock.yaml
+++ b/dts/bindings/clock/st,stm32c0-hsi-clock.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32 HSI Clock node description for STM32C0 devices
+  STM32C0 HSI Clock.
+
   On STM32C0, HSI is a 48MHz fixed clock.
 
   It also produces a HSISYS secondary clk which can be used as system clock
diff --git a/dts/bindings/clock/st,stm32f0-pll-clock.yaml b/dts/bindings/clock/st,stm32f0-pll-clock.yaml
index f35804b9a54..92e6c54242b 100644
--- a/dts/bindings/clock/st,stm32f0-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32f0-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Main PLL node binding for STM32F0 and STM32F3 devices.
+  STM32F0/F3 Main PLL.
 
   Takes one of clk_hse or clk_hsi as input clock.
 
diff --git a/dts/bindings/clock/st,stm32f0-rcc.yaml b/dts/bindings/clock/st,stm32f0-rcc.yaml
index c85205ab8fd..3e278b774f0 100644
--- a/dts/bindings/clock/st,stm32f0-rcc.yaml
+++ b/dts/bindings/clock/st,stm32f0-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32F0 and G0 Reset and Clock controller node.
+  STM32F0/G0 RCC (Reset and Clock controller).
+
   For more description confere st,stm32-rcc.yaml
 
 compatible: "st,stm32f0-rcc"
diff --git a/dts/bindings/clock/st,stm32f1-clock-mco.yaml b/dts/bindings/clock/st,stm32f1-clock-mco.yaml
index 5024a816602..dc3670c76b7 100644
--- a/dts/bindings/clock/st,stm32f1-clock-mco.yaml
+++ b/dts/bindings/clock/st,stm32f1-clock-mco.yaml
@@ -7,7 +7,7 @@
 compatible: "st,stm32f1-clock-mco"
 
 description: |
-        STM32 F1 series Microcontroller Clock Output (MCO)
+        STM32F1 Microcontroller Clock Output (MCO)
 
         The STM32F1 MCO is similar to other series but has no configurable
         prescaler before the output. However, note that certain inputs of
diff --git a/dts/bindings/clock/st,stm32f1-pll-clock.yaml b/dts/bindings/clock/st,stm32f1-pll-clock.yaml
index 04c9a8e2954..5102a362e7c 100644
--- a/dts/bindings/clock/st,stm32f1-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32f1-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Main PLL node binding for low-, medium-, high- and XL-density STM32F1 devices.
+  STM32F1 Main PLL for low-, medium-, high- and XL-density devices.
 
   Takes one of 'clk_hse', 'clk_hse / 2' (when 'xtpre' is set) or 'clk_hsi / 2'
   as input clock.
diff --git a/dts/bindings/clock/st,stm32f1-rcc.yaml b/dts/bindings/clock/st,stm32f1-rcc.yaml
index 00f54374335..f013d8daa09 100644
--- a/dts/bindings/clock/st,stm32f1-rcc.yaml
+++ b/dts/bindings/clock/st,stm32f1-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32F1 and STM32F37x Reset and Clock controller node.
+  STM32F1/F3/7x RCC (Reset and Clock controller).
+
   Adds the ADC prescaler to the standard generic STM32 RCC.
   For more description confere st,stm32-rcc.yaml
 
diff --git a/dts/bindings/clock/st,stm32f100-pll-clock.yaml b/dts/bindings/clock/st,stm32f100-pll-clock.yaml
index a861a445fef..e1898b57ef7 100644
--- a/dts/bindings/clock/st,stm32f100-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32f100-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Main PLL node binding for STM32F100 devices
+  STM32F100 Main PLL.
 
   Takes one of clk_hse or clk_hsi as input clock.
   When clk_hsi is used a fixed prescaler is applied. When input clock is hse or
diff --git a/dts/bindings/clock/st,stm32f105-pll-clock.yaml b/dts/bindings/clock/st,stm32f105-pll-clock.yaml
index d2f01e8989b..d294a438a76 100644
--- a/dts/bindings/clock/st,stm32f105-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32f105-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Main PLL node binding for Connectivity line devices (STM32F105/STM32F107)
+  STM32F105/F107 Main PLL.
 
   Takes one of clk_hse, pll2 or clk_hsi as input clock.
   When clk_hsi is used a fixed prescaler is applied. When input clock is hse or
diff --git a/dts/bindings/clock/st,stm32f105-pll2-clock.yaml b/dts/bindings/clock/st,stm32f105-pll2-clock.yaml
index b9b881d4f10..3292ab5babc 100644
--- a/dts/bindings/clock/st,stm32f105-pll2-clock.yaml
+++ b/dts/bindings/clock/st,stm32f105-pll2-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  PLL2 node binding for Connectivity line devices (STM32F105/STM32F107)
+  STM32F105/F107 PLL2.
 
   Takes clk_hse as input clock, using prediv as prescaler.
 
diff --git a/dts/bindings/clock/st,stm32f2-pll-clock.yaml b/dts/bindings/clock/st,stm32f2-pll-clock.yaml
index eda981c3e07..917b64768b8 100644
--- a/dts/bindings/clock/st,stm32f2-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32f2-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32F2 Main PLL node binding:
+  STM32F2 Main PLL.
 
   Takes one of clk_hse or clk_hsi as input clock.
 
diff --git a/dts/bindings/clock/st,stm32f3-rcc.yaml b/dts/bindings/clock/st,stm32f3-rcc.yaml
index 64851cdaf59..6db97343e98 100644
--- a/dts/bindings/clock/st,stm32f3-rcc.yaml
+++ b/dts/bindings/clock/st,stm32f3-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32F3 Reset and Clock controller node.
+  STM32F3 RCC (Reset and Clock controller).
+
   Adds the STM32F3 ADC prescaler to the standard generic STM32 RCC.
   For more description confere st,stm32-rcc.yaml
 
diff --git a/dts/bindings/clock/st,stm32f4-pll-clock.yaml b/dts/bindings/clock/st,stm32f4-pll-clock.yaml
index 1346ec8a55f..81ccb5182da 100644
--- a/dts/bindings/clock/st,stm32f4-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32f4-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32F4 Main PLL node binding:
+  STM32F4 Main PLL.
 
   Takes one of clk_hse or clk_hsi as input clock, with an
   input frequency from 1 to 2 MHz. PLLM factor is used to set the input clock
diff --git a/dts/bindings/clock/st,stm32f4-plli2s-clock.yaml b/dts/bindings/clock/st,stm32f4-plli2s-clock.yaml
index b5e6e9cc4a3..aff08c75788 100644
--- a/dts/bindings/clock/st,stm32f4-plli2s-clock.yaml
+++ b/dts/bindings/clock/st,stm32f4-plli2s-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32F4 PLL I2S node binding:
+  STM32F4 PLL I2S.
 
   Takes same input as Main PLL. PLLM factor and PLL source are common with Main PLL
 
diff --git a/dts/bindings/clock/st,stm32f411-plli2s-clock.yaml b/dts/bindings/clock/st,stm32f411-plli2s-clock.yaml
index 459e990422d..ed9b235d327 100644
--- a/dts/bindings/clock/st,stm32f411-plli2s-clock.yaml
+++ b/dts/bindings/clock/st,stm32f411-plli2s-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32F411 PLL I2S node binding:
+  STM32F411 PLL I2S.
 
   Fully configurable I2S dedicated PLL.
 
diff --git a/dts/bindings/clock/st,stm32f7-pll-clock.yaml b/dts/bindings/clock/st,stm32f7-pll-clock.yaml
index 163426ef7bd..fc1a29fca29 100644
--- a/dts/bindings/clock/st,stm32f7-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32f7-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32F7 Main PLL node binding:
+  STM32F7 Main PLL.
 
   Takes one of clk_hse or clk_hsi as input clock.
 
diff --git a/dts/bindings/clock/st,stm32g0-hsi-clock.yaml b/dts/bindings/clock/st,stm32g0-hsi-clock.yaml
index a2d523fb0eb..bf2df7d5f02 100644
--- a/dts/bindings/clock/st,stm32g0-hsi-clock.yaml
+++ b/dts/bindings/clock/st,stm32g0-hsi-clock.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32 HSI Clock node description for STM32G0 devices
+  STM32G0 HSI Clock.
+
   On STM32G0, HSI is a 16MHz fixed clock.
 
   It also produces a HSISYS secondary clk which can be used as system clock
diff --git a/dts/bindings/clock/st,stm32g0-pll-clock.yaml b/dts/bindings/clock/st,stm32g0-pll-clock.yaml
index c397b3c708b..7468425de9b 100644
--- a/dts/bindings/clock/st,stm32g0-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32g0-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  PLL node binding for STM32G0 devices
+  STM32G0 main PLL.
 
   It can take one of clk_hse or clk_hsi as input clock, with
   an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
diff --git a/dts/bindings/clock/st,stm32g4-pll-clock.yaml b/dts/bindings/clock/st,stm32g4-pll-clock.yaml
index 735895258ab..fb23b621701 100644
--- a/dts/bindings/clock/st,stm32g4-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32g4-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  PLL node binding for STM32G4 devices
+  STM32G4 main PLL.
 
   It can take one of clk_hse or clk_hsi as input clock, with
   an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
diff --git a/dts/bindings/clock/st,stm32h7-pll-clock.yaml b/dts/bindings/clock/st,stm32h7-pll-clock.yaml
index 2e441876116..a62cd19aadb 100644
--- a/dts/bindings/clock/st,stm32h7-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32h7-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  PLL node binding for STM32H7 devices
+  STM32H7 main PLL.
 
   It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
   Only PLL1 and PLL3 are supported for now.
diff --git a/dts/bindings/clock/st,stm32h7-rcc.yaml b/dts/bindings/clock/st,stm32h7-rcc.yaml
index b0e6622e6d3..f2246e75708 100644
--- a/dts/bindings/clock/st,stm32h7-rcc.yaml
+++ b/dts/bindings/clock/st,stm32h7-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32 Reset and Clock controller node for STM32H7 devices
+  STM32H7 RCC (Reset and Clock controller).
+
   This node is in charge of system clock ('SYSCLK') source selection and
   System Clock Generation.
 
diff --git a/dts/bindings/clock/st,stm32h7rs-pll-clock.yaml b/dts/bindings/clock/st,stm32h7rs-pll-clock.yaml
index cb2980dd39c..6ff7100f347 100644
--- a/dts/bindings/clock/st,stm32h7rs-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32h7rs-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  PLL node binding for STM32H7RS devices
+  STM32H7RS main PLL.
 
   It can be used to describe 3 different PLLs: PLL1 (Main PLL), PLL2 and PLL3.
 
diff --git a/dts/bindings/clock/st,stm32h7rs-rcc.yaml b/dts/bindings/clock/st,stm32h7rs-rcc.yaml
index 780c84564f4..5eb4ad2f6bf 100644
--- a/dts/bindings/clock/st,stm32h7rs-rcc.yaml
+++ b/dts/bindings/clock/st,stm32h7rs-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32 Reset and Clock controller node for STM32H7RS devices
+  STM32H7RS RCC (Reset and Clock controller).
+
   This node is in charge of system clock ('SYSCLK') source selection and
   System Clock Generation.
 
diff --git a/dts/bindings/clock/st,stm32l0-msi-clock.yaml b/dts/bindings/clock/st,stm32l0-msi-clock.yaml
index 29d8d1cdcb9..07bf13cd1a3 100644
--- a/dts/bindings/clock/st,stm32l0-msi-clock.yaml
+++ b/dts/bindings/clock/st,stm32l0-msi-clock.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021, Linaro ltd
 # SPDX-License-Identifier: Apache-2.0
 
-description: STM32L0 and STM32L1 Multi Speed Internal Clock
+description: STM32L0/L1 Multi Speed Internal Clock
 
 compatible: "st,stm32l0-msi-clock"
 
diff --git a/dts/bindings/clock/st,stm32l0-pll-clock.yaml b/dts/bindings/clock/st,stm32l0-pll-clock.yaml
index a62df8ffeae..23a79b50d85 100644
--- a/dts/bindings/clock/st,stm32l0-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32l0-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32L0 and STM32L1 Main PLL node binding:
+  STM32L0/L1 Main PLL.
 
   Takes one of clk_hse, clk_hsi or clk_msi as input clock, with an
   input frequency from 2 to 24 MHz.
diff --git a/dts/bindings/clock/st,stm32l4-pll-clock.yaml b/dts/bindings/clock/st,stm32l4-pll-clock.yaml
index 32ed2c4ae13..b4fc59949c3 100644
--- a/dts/bindings/clock/st,stm32l4-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32l4-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  PLL node binding for STM32L4 and STM32L5 devices
+  STM32L4/L5 main PLL.
 
   It can be used to describe 3 different PLLs: PLL, PLLSAI1 and PLLSAI2.
   Only main PLL is supported for now.
diff --git a/dts/bindings/clock/st,stm32mp1-rcc.yaml b/dts/bindings/clock/st,stm32mp1-rcc.yaml
index 8282b46d112..14af40db531 100644
--- a/dts/bindings/clock/st,stm32mp1-rcc.yaml
+++ b/dts/bindings/clock/st,stm32mp1-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32MP1 Reset and Clock controller node.
+  STM32MP1 RCC (Reset and Clock controller).
+
   On STM32MP1 platforms, clock control configuration is performed on A9 side.
   As a consequence, the only property to be set in devicetree node is the
   clock-frequency (mlhclk_ck).
diff --git a/dts/bindings/clock/st,stm32mp13-cpu-clock-mux.yaml b/dts/bindings/clock/st,stm32mp13-cpu-clock-mux.yaml
new file mode 100644
index 00000000000..529d9ef8259
--- /dev/null
+++ b/dts/bindings/clock/st,stm32mp13-cpu-clock-mux.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2025, STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32MP13 CPU Clock
+  Describes the STM32MP13 CPU armv7 timer multiplexer.
+  For the STM32MP13 the CPU armv7 timer input can either be the HSI or the HSE.
+  For instance:
+  cpusw: cpusw {
+    #clock-cells = <0>;
+    clocks = <&clk_hsi>;
+    clock-frequency = <DT_FREQ_M(64)>;
+    compatible = "st,stm32mp13-cpu-clock-mux", "st,stm32-clock-mux";
+    status = "okay";
+  };
+
+compatible: "st,stm32mp13-cpu-clock-mux"
+
+include:
+  - name: base.yaml
+    property-allowlist:
+      - status
+      - compatible
+      - clocks
+
+properties:
+  clock-frequency:
+    required: true
+    type: int
+    description: |
+      default frequency in Hz for the timer
diff --git a/dts/bindings/clock/st,stm32mp13-pll-clock.yaml b/dts/bindings/clock/st,stm32mp13-pll-clock.yaml
new file mode 100644
index 00000000000..5128ea05f0d
--- /dev/null
+++ b/dts/bindings/clock/st,stm32mp13-pll-clock.yaml
@@ -0,0 +1,68 @@
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  PLL node binding for STM32MP13 devices
+
+  It can be used to describe 4 different PLLs: PLL1, PLL2, PLL3 and PLL4.
+
+  These PLLs can take one of hse_ck, hsi_ck or csi_ck as input clock.
+  PLLM factor is used to set the input clock in this acceptable range.
+
+  Each PLL has one output clock whose frequency can be computed with the
+  following formula:
+
+    f(PLL_P) = f(VCO clock) / (DIVP × DIVR × DIVQ)
+
+      with f(VCO clock) = f(PLL clock input) × 2 × (((DIVN + 1) + (FRACV / 8192)) / DIVM1)
+
+  Note: To reduce the power consumption, it is recommended to configure the VCOx
+        clock output to the lowest frequency.
+
+  The PLL1 output frequency must not exceed 2000 MHz.
+  The PLL2 output frequency must not exceed 1600 MHz.
+  The PLL3 output frequency must not exceed 800 MHz.
+  The PLL4 output frequency must not exceed 800 MHz.
+
+  Note: The CPU clock should not exceed 1Ghz so avoid configuring the PLL1 to more
+  than 1000 MHz or program the mpuss_ck mux to use the MPUDIV
+  (refer to the stm32mp13 reference manual for details)
+
+compatible: "st,stm32mp13-pll-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+
+  "#clock-cells":
+    const: 0
+
+  clocks:
+    required: true
+
+  div-m:
+    type: int
+    required: true
+    description: |
+        Prescaler for PLLx
+        input clock
+        Valid range: 1 - 64
+
+  mul-n:
+    type: int
+    required: true
+    description: |
+        PLLx multiplication factor for VCO
+        Valid range: 31 - 125
+
+  div-p:
+    type: int
+    description: |
+        PLLx DIVP division factor
+        Valid range: 1 - 128
+
+  frac-v:
+    type: int
+    description: |
+        PLLx FRACV fractional latch
+        Valid range: 1 - 8192
diff --git a/dts/bindings/clock/st,stm32n6-cpu-clock-mux.yaml b/dts/bindings/clock/st,stm32n6-cpu-clock-mux.yaml
new file mode 100644
index 00000000000..c37cfa4c082
--- /dev/null
+++ b/dts/bindings/clock/st,stm32n6-cpu-clock-mux.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2025, STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32N6 CPU Clock.
+
+  Describes the STM32N6 CPU clock multiplexer. On STM32N6, this is the CPU
+  clock that feeds the SysTick.
+
+  For instance:
+  &cpusw {
+    clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;
+    clock-frequency = <DT_FREQ_M(600)>;
+    status = "okay";
+  };
+
+compatible: "st,stm32n6-cpu-clock-mux"
+
+include:
+  - name: base.yaml
+    property-allowlist:
+      - status
+      - compatible
+      - clocks
+
+properties:
+  clock-frequency:
+    required: true
+    type: int
+    description: |
+      default frequency in Hz for CPU clock (sysa_ck/sys_cpu_ck)
diff --git a/dts/bindings/clock/st,stm32n6-hse-clock.yaml b/dts/bindings/clock/st,stm32n6-hse-clock.yaml
new file mode 100644
index 00000000000..36234050230
--- /dev/null
+++ b/dts/bindings/clock/st,stm32n6-hse-clock.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32N6 HSE Clock
+
+compatible: "st,stm32n6-hse-clock"
+
+include: [fixed-clock.yaml]
+
+properties:
+  hse-bypass:
+    type: boolean
+    description: |
+      HSE crystal oscillator bypass
+      Set to the property to by-pass the oscillator with an external clock.
+
+  hse-div2:
+    type: boolean
+    description: |
+      When set HSE output clock is divided by 2.
+      Otherwise, no prescaler is used.
diff --git a/dts/bindings/clock/st,stm32n6-ic-clock-mux.yaml b/dts/bindings/clock/st,stm32n6-ic-clock-mux.yaml
new file mode 100644
index 00000000000..fcfdc8b7a25
--- /dev/null
+++ b/dts/bindings/clock/st,stm32n6-ic-clock-mux.yaml
@@ -0,0 +1,35 @@
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32N6 Divider IC multiplexer.
+
+  This node selects a clock input and a divider.
+
+  For instance:
+    &ic6 {
+      pll-src = <2>;
+      div = <16>;
+      status = "okay";
+    };
+
+compatible: "st,stm32n6-ic-clock-mux"
+
+properties:
+  pll-src:
+    type: int
+    required: true
+    description: |
+        PLL clock source
+    enum:
+      - 1
+      - 2
+      - 3
+      - 4
+
+  ic-div:
+    type: int
+    description: |
+        ICx integer division factor
+        The input ICx frequency is divided by the specified value
+        Valid range: 1 - 256
diff --git a/dts/bindings/clock/st,stm32n6-pll-clock.yaml b/dts/bindings/clock/st,stm32n6-pll-clock.yaml
new file mode 100644
index 00000000000..ec14ab02b7f
--- /dev/null
+++ b/dts/bindings/clock/st,stm32n6-pll-clock.yaml
@@ -0,0 +1,62 @@
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32N6 main PLL.
+
+  It can be used to describe 4 different PLLs: PLL1, PLL2, PLL3 and PLL4.
+
+  These PLLs can take one of clk_hse, clk_hsi or clk_msi as input clock, with
+  an input frequency from 5 to 50 MHz. PLLM factor is used to set the input
+  clock in this acceptable range.
+
+  Each PLL has one output clock whose frequency can be computed with the
+  following formula:
+
+    f(PLL_P) = f(VCO clock) / (PLLP1 × PLLP2)
+
+      with f(VCO clock) = f(PLL clock input) × (PLLN / PLLM)
+
+  Note: To reduce the power consumption, it is recommended to configure the VCOx
+        clock output to the lowest frequency.
+
+  The PLL output frequency must not exceed 3200 MHz.
+
+compatible: "st,stm32n6-pll-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+
+  "#clock-cells":
+    const: 0
+
+  clocks:
+    required: true
+
+  div-m:
+    type: int
+    required: true
+    description: |
+        Prescaler for PLLx
+        input clock
+        Valid range: 1 - 63
+
+  mul-n:
+    type: int
+    required: true
+    description: |
+        PLLx multiplication factor for VCO
+        Valid range: 16 - 2500
+
+  div-p1:
+    type: int
+    description: |
+        PLLx DIVP1 division factor
+        Valid range: 1 - 7
+
+  div-p2:
+    type: int
+    description: |
+        PLLx DIVP2 division factor
+        Valid range: 1 - 7
diff --git a/dts/bindings/clock/st,stm32n6-rcc.yaml b/dts/bindings/clock/st,stm32n6-rcc.yaml
new file mode 100644
index 00000000000..5bac045ec57
--- /dev/null
+++ b/dts/bindings/clock/st,stm32n6-rcc.yaml
@@ -0,0 +1,109 @@
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32N6 RCC (Reset and Clock controller).
+
+  This node is in charge of system clock ('SYSCLK') source selection and
+  System Clock Generation.
+
+  Configuring STM32 Reset and Clock controller node:
+
+  System clock source should be selected amongst the clock nodes available in "clocks"
+  node (typically 'clk_hse, clk_csi', 'pll', ...).
+  As part of this node configuration, SYSCLK frequency should also be defined, using
+  "clock-frequency" property.
+  Last, bus clocks (typically HCLK, PCLK1, PCLK2) should be configured using matching
+  prescaler properties.
+  Here is an example of correctly configured rcc node:
+  &rcc {
+    clocks = <&ic2>;
+    clock-frequency = <DT_FREQ_M(400)>;
+    ahb-prescaler = <2>;
+    apb1-prescaler = <1>;
+    apb2-prescaler = <1>;
+    apb4-prescaler = <1>;
+    apb5-prescaler = <1>;
+  }
+
+  Confere st,stm32-rcc binding for information about domain clocks configuration.
+
+compatible: "st,stm32n6-rcc"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  "#clock-cells":
+    const: 2
+
+  clock-frequency:
+    required: true
+    type: int
+    description: |
+      default frequency in Hz for clock output
+
+  ahb-prescaler:
+    type: int
+    required: true
+    description: |
+        AHB clock prescaler
+    enum:
+      - 1
+      - 2
+      - 4
+      - 8
+      - 16
+      - 32
+      - 64
+      - 128
+
+  apb1-prescaler:
+    type: int
+    default: 1
+    const: 1
+    description: |
+        CPU domain APB1 prescaler
+        Fixed to 1 as APB prescalers cannot be modified (See Errata sheet ES0620 §2.2.1)
+
+  apb2-prescaler:
+    type: int
+    default: 1
+    const: 1
+    description: |
+        CPU domain APB2 prescaler
+        Fixed to 1 as APB prescalers cannot be modified (See Errata sheet ES0620 §2.2.1)
+
+  apb4-prescaler:
+    type: int
+    default: 1
+    const: 1
+    description: |
+        CPU domain APB4 prescaler
+        Fixed to 1 as APB prescalers cannot be modified (See Errata sheet ES0620 §2.2.1)
+
+  apb5-prescaler:
+    type: int
+    default: 1
+    const: 1
+    description: |
+        CPU domain APB5 prescaler
+        Fixed to 1 as APB prescalers cannot be modified (See Errata sheet ES0620 §2.2.1)
+
+  timg-prescaler:
+    type: int
+    default: 1
+    description: |
+        TIMG timer group domain prescaler divider, default reset value is 'not divided'.
+    enum:
+      - 1
+      - 2
+      - 4
+      - 8
+
+
+clock-cells:
+  - bus
+  - bits
diff --git a/dts/bindings/clock/st,stm32u0-pll-clock.yaml b/dts/bindings/clock/st,stm32u0-pll-clock.yaml
index 73d9d6f7324..5e56fc8ffe4 100644
--- a/dts/bindings/clock/st,stm32u0-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32u0-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32U0 Main PLL node binding:
+  STM32U0 Main PLL.
 
   Takes one of clk_hse, clk_hsi or clk_msi as input clock, with
   an input frequency from 2.66 to 16 MHz. PLLM factor is used to set the input
diff --git a/dts/bindings/clock/st,stm32u5-pll-clock.yaml b/dts/bindings/clock/st,stm32u5-pll-clock.yaml
index 241c8acb841..a83d6c22dfa 100644
--- a/dts/bindings/clock/st,stm32u5-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32u5-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  PLL node binding for STM32U5 devices
+  STM32U5 PLL.
 
   It can be used to describe 3 different PLLs: PLL1, PLL2 and PLL3.
 
diff --git a/dts/bindings/clock/st,stm32u5-rcc.yaml b/dts/bindings/clock/st,stm32u5-rcc.yaml
index 3cf2aa064a3..505acf4bf4a 100644
--- a/dts/bindings/clock/st,stm32u5-rcc.yaml
+++ b/dts/bindings/clock/st,stm32u5-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32U5 Reset and Clock controller node.
+  STM32U5 RCC (Reset and Clock controller).
+
   For more description confere st,stm32-rcc.yaml
 
 compatible: "st,stm32u5-rcc"
diff --git a/dts/bindings/clock/st,stm32wb-rcc.yaml b/dts/bindings/clock/st,stm32wb-rcc.yaml
index 6867f97fd00..fa0aea63bbc 100644
--- a/dts/bindings/clock/st,stm32wb-rcc.yaml
+++ b/dts/bindings/clock/st,stm32wb-rcc.yaml
@@ -3,6 +3,7 @@
 
 description: |
   STM32WB Reset and Clock controller node.
+
   For more description confere st,stm32-rcc.yaml
 
 compatible: "st,stm32wb-rcc"
diff --git a/dts/bindings/clock/st,stm32wb0-rcc.yaml b/dts/bindings/clock/st,stm32wb0-rcc.yaml
index bfebe71de2b..272889ada71 100644
--- a/dts/bindings/clock/st,stm32wb0-rcc.yaml
+++ b/dts/bindings/clock/st,stm32wb0-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32WB0 Reset and Clock controller node for STM32WB0 devices
+  STM32WB0 RCC (Reset and Clock controller).
+
   This node is in charge of the system clock ('SYSCLK') source
   selection and generation.
 
diff --git a/dts/bindings/clock/st,stm32wba-pll-clock.yaml b/dts/bindings/clock/st,stm32wba-pll-clock.yaml
index 03a755f0ee3..a47b61183f5 100644
--- a/dts/bindings/clock/st,stm32wba-pll-clock.yaml
+++ b/dts/bindings/clock/st,stm32wba-pll-clock.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  PLL node binding for STM32WBA devices
+  STM32WBA PLL.
 
   It can be used to describe PLL1
 
diff --git a/dts/bindings/clock/st,stm32wba-rcc.yaml b/dts/bindings/clock/st,stm32wba-rcc.yaml
index 797c366da11..ea6bd32e741 100644
--- a/dts/bindings/clock/st,stm32wba-rcc.yaml
+++ b/dts/bindings/clock/st,stm32wba-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32 Reset and Clock controller node.
+  STM32WBA RCC (Reset and Clock controller).
+
   This node is in charge of system clock ('SYSCLK') source selection and controlling
   clocks for AHB (Advanced High Performance) and APB (Advanced Peripheral) bus domains.
 
diff --git a/dts/bindings/clock/st,stm32wl-rcc.yaml b/dts/bindings/clock/st,stm32wl-rcc.yaml
index 882493ea8ea..5d0ac82bbf4 100644
--- a/dts/bindings/clock/st,stm32wl-rcc.yaml
+++ b/dts/bindings/clock/st,stm32wl-rcc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32WL Reset and Clock controller node.
+  STM32WL RCC (Reset and Clock controller).
+
   For more description confere st,stm32-rcc.yaml
 
 compatible: "st,stm32wl-rcc"
diff --git a/dts/bindings/clock/wch,ch32v20x_30x-pll-clock.yaml b/dts/bindings/clock/wch,ch32v20x_30x-pll-clock.yaml
new file mode 100644
index 00000000000..83d1ac89d49
--- /dev/null
+++ b/dts/bindings/clock/wch,ch32v20x_30x-pll-clock.yaml
@@ -0,0 +1,39 @@
+# Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
+# SPDX-License-Identifier: Apache-2.0
+
+description: WCH CH32V20x/30x PLL
+
+compatible: "wch,ch32v20x_30x-pll-clock"
+
+include: [clock-controller.yaml, base.yaml]
+
+properties:
+  "#clock-cells":
+    const: 0
+
+  clocks:
+    type: phandle-array
+    required: true
+
+  mul:
+    type: int
+    required: true
+    description: |
+        Main PLL multiplication factor
+    enum:
+      - 2   # x2
+      - 3   # x3
+      - 4   # x4
+      - 5   # x5
+      - 6   # x6
+      - 7   # x7
+      - 8   # x8
+      - 9   # x2
+      - 10  # x10
+      - 11  # x11
+      - 12  # x12
+      - 13  # x13
+      - 14  # x14
+      - 15  # x15
+      - 16  # x16
+      - 18  # x18
diff --git a/dts/bindings/comparator/renesas,ra-acmphs-global.yaml b/dts/bindings/comparator/renesas,ra-acmphs-global.yaml
new file mode 100644
index 00000000000..900d3b52597
--- /dev/null
+++ b/dts/bindings/comparator/renesas,ra-acmphs-global.yaml
@@ -0,0 +1,49 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Renesas RA ACMPHS (High-Speed Analog COMParator) Global
+
+  The following example displays the minimum node layout:
+
+    acmphs_global: acmphs_global@deadbeef {
+            compatible = "renesas,ra-acmphs-global";
+            reg = <0xdeadbeef 0x200>;
+            status = "disabled";
+
+            acmphs0: acmphs0 {
+                    ...
+            };
+    };
+
+  If the pin-output-enable is selected in the comparator controller node,
+  this global node needs to define the VCOUT pin to enable output on that pin.
+
+  Note: The VCOUT pinctrl for the comparator global node is already defined
+  on each board that supported comparator. Please check the board’s pinctrl
+  before defining it.
+
+    acmphs_vcout: acmphs_vcout {
+            group1 {
+                    /* VCOUT */
+                    psels = <RA_PSEL(RA_PSEL_ACMPHS_VCOUT, ..., ...)>;
+            };
+    };
+
+    &acmphs_global {
+            pinctrl-0 = <&acmphs_vcout>;
+            pinctrl-names = "default";
+            status = "okay";
+
+            acmphs0 {
+                    ...
+            };
+    };
+
+  Note: There is only one VCOUT shared across all comparator controller nodes.
+  Therefore, the VCOUT value is the logical OR of the output signals from all
+  comparator controllers that have pin-output-enable enabled.
+
+compatible: "renesas,ra-acmphs-global"
+
+include: [base.yaml, pinctrl-device.yaml]
diff --git a/dts/bindings/comparator/renesas,ra-acmphs.yaml b/dts/bindings/comparator/renesas,ra-acmphs.yaml
new file mode 100644
index 00000000000..252d161bdec
--- /dev/null
+++ b/dts/bindings/comparator/renesas,ra-acmphs.yaml
@@ -0,0 +1,119 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Renesas RA ACMPHS (High-Speed Analog COMParator) Controller
+
+  The following example displays the minimum node layout:
+
+    acmphs_global: acmphs_global@deadbeef {
+            ...
+
+            acmphs0: acmphs0 {
+                    compatible = "renesas,ra-acmphs";
+                    channel = <0>;
+                    status = "disabled";
+            };
+    };
+
+  Enabling the comparator controller node requires setting the minimum
+  default configuration of the comparator. This includes selecting the
+  positive and negative inputs, and routing them using pinctrl:
+
+  Note: A set of pinctrl for the default comparator controller node is
+  already defined on each board that supported comparator. Please check
+  the board’s pinctrl before defining it.
+
+  &pinctrl {
+          acmphs_ivref0: acmphs_ivref0 {
+                  group1 {
+                          /* IVREF0 */
+                          psels = <RA_PSEL(RA_PSEL_ACMPHS, ..., ...)>;
+                          renesas,analog-enable;
+                  };
+          };
+
+          acmphs0_ivcmp0: acmphs0_ivcmp0 {
+                  group1 {
+                          /* CH0 IVCMP0 */
+                          psels = <RA_PSEL(RA_PSEL_ACMPHS, ..., ...)>;
+                          renesas,analog-enable;
+                  };
+          };
+  };
+
+  &acmphs_global {
+          status = "okay";
+
+          acmphs0 {
+                  pinctrl-0 = <&acmphs_ivref0 &acmphs0_ivcmp0>;
+                  pinctrl-names = "default";
+                  interrupts = <90 12>;
+                  interrupt-names = "hs";
+                  reference-input-source = "ivref0";
+                  compare-input-source = "ivcmp0";
+                  status = "okay";
+          };
+  };
+
+compatible: "renesas,ra-acmphs"
+
+include: [base.yaml, pinctrl-device.yaml]
+
+properties:
+  channel:
+    type: int
+    required: true
+
+  interrupts:
+    description: |
+      IRQ number and priority to use for interrupt Comparator:
+      - "hs": generated on valid edge detection from comparison result
+      Note: when this interrupts property is not defined, none of the trigger APIs
+            can be used (set_trigger, set_trigger_callback, trigger_is_pending).
+
+  reference-input-source:
+    type: string
+    required: true
+    enum:
+      - "ivref0"
+      - "ivref1"
+      - "ivref2"
+      - "ivref3"
+    description: |
+      Select the Analog reference voltage source.
+      Note: ivref2 is connected to Vref
+            ivref3 is connected to DA0 (DAC)
+            If either of these is selected, there is no need to configure pinsel for pinctrl.
+
+  compare-input-source:
+    type: string
+    required: true
+    enum:
+      - "ivcmp0"
+      - "ivcmp1"
+      - "ivcmp2"
+      - "ivcmp3"
+    description: |
+      Select the Analog compare voltage source.
+      Note: ivcmp1 is connected to DA0 (DAC)
+            If ivcmp1 is selected, there is no need to configure pinsel for pinctrl.
+
+  noise-filter:
+    type: int
+    enum: [1, 8, 16, 32]
+    default: 32
+    description: |
+      Select the PCLK divisor for the hardware digital debounce filter.
+      Larger divisors provide a longer debounce and take longer for the output to update.
+
+  output-invert-polarity:
+    type: boolean
+    description: |
+      When enabled comparator output is inverted.
+
+  pin-output-enable:
+    type: boolean
+    description: |
+      Turn this on to enable the CMPOUTn signal for this channel.
+      The CMPOUTn signal for each channel is OR'd together and the result is output to VCOUT.
diff --git a/dts/bindings/comparator/silabs,acmp.yaml b/dts/bindings/comparator/silabs,acmp.yaml
new file mode 100644
index 00000000000..ccd63b5053b
--- /dev/null
+++ b/dts/bindings/comparator/silabs,acmp.yaml
@@ -0,0 +1,124 @@
+# Copyright (c) 2025 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+description: |
+  Silabs ACMP (Analog Comparator)
+
+  The minimal default configuration for the silabs acmp node is as follows:
+
+    #include <zephyr/dt-bindings/comparator/silabs-acmp.h>
+
+    &acmp0 {
+           status = "okay";
+
+           input-positive = <ACMP_INPUT_VSENSE01DIV4>;
+           input-negative = <ACMP_INPUT_VREFDIVAVDD>;
+    };
+
+  Note that there are bindings to retrieve the values for `input-positive` and
+  `input-negative` properties. See the included bindings in the example above.
+
+  When using the minimal default configuration in the snippet above, some
+  properties will be implicitly configured with default values. An equivalent
+  device tree node is therefore as follows:
+
+    #include <zephyr/dt-bindings/comparator/silabs-acmp.h>
+
+    &acmp0 {
+            status = "okay";
+
+            bias = <0>;
+            hysteresis-mode = "disabled";
+            accuracy-mode = "low";
+            input-range = "full";
+            input-positive = <ACMP_INPUT_VSENSE01DIV4>;
+            input-negative = <ACMP_INPUT_VREFDIVAVDD>;
+            vref-divider = <63>;
+    };
+
+  It is also possible to select a GPIO pin for either/both of the
+  `input-positive` or `input-negative` properties. In those cases, the
+  `pinctrl` driver must be configured to allocate an analog bus corresponding
+  to the port and pin of each GPIO input selected. The following is an example
+  of how that can be configured:
+
+    #include <zephyr/dt-bindings/comparator/silabs-acmp.h>
+    #include <zephyr/dt-bindings/pinctrl/silabs/xg24-pinctrl.h>
+
+    &pinctrl {
+            acmp0_default: acmp0_default {
+                    group0 {
+                            silabs,analog-bus = <ABUS_CDODD0_ACMP0>;
+                    };
+            };
+    };
+
+    &acmp0 {
+            pinctrl-0 = <&acmp0_default>;
+            pinctrl-names = "default";
+            status = "okay";
+
+            bias = <0>;
+            hysteresis-mode = "disabled";
+            accuracy-mode = "low";
+            input-range = "full";
+            input-positive = <ACMP_INPUT_PC3>;
+            input-negative = <ACMP_INPUT_VREFDIV1V25>;
+            vref-divider = <63>;
+    };
+
+  In the above example, note that the device specific bindings for pinctrl
+  were included. This header defines the set of analog bus allocations possible
+  for xg24 parts, and similar headers exist for other parts.
+
+
+compatible: "silabs,acmp"
+
+include:
+  - base.yaml
+  - pinctrl-device.yaml
+
+properties:
+  bias:
+    type: int
+    default: 0
+
+  hysteresis-mode:
+    type: string
+    enum:
+      - "disabled"
+      - "sym10mv"
+      - "sym20mv"
+      - "sym30mv"
+      - "pos10mv"
+      - "pos20mv"
+      - "pos30mv"
+      - "neg10mv"
+      - "neg20mv"
+      - "neg30mv"
+    default: "disabled"
+
+  accuracy-mode:
+    type: string
+    enum:
+      - "low"
+      - "high"
+    default: "low"
+
+  input-range:
+    type: string
+    enum:
+      - "full"
+      - "reduced"
+    default: "full"
+
+  input-positive:
+    type: int
+    required: true
+
+  input-negative:
+    type: int
+    required: true
+
+  vref-divider:
+    type: int
+    default: 63
diff --git a/dts/bindings/counter/atmel,sam0-tc32.yaml b/dts/bindings/counter/atmel,sam0-tc32.yaml
index c523e6e4104..3a9b49f2f3f 100644
--- a/dts/bindings/counter/atmel,sam0-tc32.yaml
+++ b/dts/bindings/counter/atmel,sam0-tc32.yaml
@@ -1,4 +1,5 @@
 # Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
+# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
 description: Atmel SAM0 basic timer counter (TC) operating in 32-bit wide mode
@@ -8,6 +9,7 @@ compatible: "atmel,sam0-tc32"
 include:
   - name: base.yaml
   - name: pinctrl-device.yaml
+  - name: atmel,assigned-clocks.yaml
 
 properties:
   reg:
@@ -22,6 +24,12 @@ properties:
   clock-names:
     required: true
 
+  atmel,assigned-clocks:
+    required: true
+
+  atmel,assigned-clock-names:
+    required: true
+
   prescaler:
     type: int
     description: Timer prescaler
diff --git a/dts/bindings/counter/espressif,esp32-rtc-timer.yaml b/dts/bindings/counter/espressif,esp32-rtc-timer.yaml
index a8bc1c1165f..9e07c064166 100644
--- a/dts/bindings/counter/espressif,esp32-rtc-timer.yaml
+++ b/dts/bindings/counter/espressif,esp32-rtc-timer.yaml
@@ -3,7 +3,7 @@
 
 description: |
 
-        Espressif's Counter Driver based on RTC Main Timer.
+        ESP32 Counter Driver based on RTC Main Timer.
 
         Any reset/sleep mode, except for the power-up reset, will not
         stop or reset the RTC Timer. This behavior may be handy when
diff --git a/dts/bindings/counter/espressif,esp32-timer.yaml b/dts/bindings/counter/espressif,esp32-timer.yaml
index 6b0056e8f34..af425a36524 100644
--- a/dts/bindings/counter/espressif,esp32-timer.yaml
+++ b/dts/bindings/counter/espressif,esp32-timer.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-        Espressif's general-purpose Timers.
+        ESP32 general-purpose timers.
+
         Each Timer is part of a Timer Group and the number of available Timers
         is SoC-dependent.
 
diff --git a/dts/bindings/counter/ite,it8xxx2-counter.yaml b/dts/bindings/counter/ite,it8xxx2-counter.yaml
new file mode 100644
index 00000000000..84c4be93156
--- /dev/null
+++ b/dts/bindings/counter/ite,it8xxx2-counter.yaml
@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2025 ITE Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: ITE IT8XXX2 counter
+
+compatible: "ite,it8xxx2-counter"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
diff --git a/dts/bindings/counter/nordic,nrf-timer.yaml b/dts/bindings/counter/nordic,nrf-timer.yaml
index 9f8395003a8..8a961f34f88 100644
--- a/dts/bindings/counter/nordic,nrf-timer.yaml
+++ b/dts/bindings/counter/nordic,nrf-timer.yaml
@@ -24,20 +24,10 @@ properties:
   interrupts:
     required: true
 
-  max-frequency:
-    type: int
-    default: 16000000
-    description: |
-        Maximum timer frequency in Hz.
-
-        The default value is 16MHz which was the maximum frequency for all nRF TIMER peripherals
-        up to the nRF54 series, and still remains the most typical maximum frequency for nRF54
-        TIMERs.
-
   prescaler:
     type: int
     required: true
-    description: Prescaler value determines frequency (max-frequency/2^prescaler)
+    description: Prescaler value determines frequency (base_frequency/2^prescaler)
 
   zli:
     type: boolean
diff --git a/dts/bindings/counter/nxp,imx-tmr.yaml b/dts/bindings/counter/nxp,imx-tmr.yaml
index b61fe6766a4..27c7ae76b29 100644
--- a/dts/bindings/counter/nxp,imx-tmr.yaml
+++ b/dts/bindings/counter/nxp,imx-tmr.yaml
@@ -33,7 +33,7 @@ properties:
       - "kQTMR_SecSrcTrigPriCnt"
       - "kQTMR_CascadeCount"
 
-  primary_source:
+  primary-source:
     type: string
     required: true
     description: Primary source of the timer, see qtmr_primary_count_source_t enumerator type
@@ -56,7 +56,7 @@ properties:
       - "kQTMR_ClockDivide_64"
       - "kQTMR_ClockDivide_128"
 
-  secondary_source:
+  secondary-source:
     type: string
     description: Secondary source of the timer, see qtmr_input_source_t enumerator type
       of the MCUXpresso SDK
@@ -66,11 +66,11 @@ properties:
       - "kQTMR_Counter2InputPin"
       - "kQTMR_Counter3InputPin"
 
-  filter_count:
+  filter-count:
     type: int
     description: Fault filter count (0-255).
 
-  filter_period:
+  filter-period:
     type: int
     description: Fault filter period (0-255).
 
diff --git a/dts/bindings/counter/nxp,kinetis-lptmr.yaml b/dts/bindings/counter/nxp,kinetis-lptmr.yaml
deleted file mode 100644
index 0188b103b1c..00000000000
--- a/dts/bindings/counter/nxp,kinetis-lptmr.yaml
+++ /dev/null
@@ -1,8 +0,0 @@
-# Copyright 2024 NXP
-# SPDX-License-Identifier: Apache-2.0
-
-description: Deprecated compatible for NXP LPTMR
-
-compatible: "nxp,kinetis-lptmr"
-
-include: nxp,lptmr.yaml
diff --git a/dts/bindings/counter/raspberrypi,pico-timer.yaml b/dts/bindings/counter/raspberrypi,pico-timer.yaml
index 98afd1b9659..b7fb7075129 100644
--- a/dts/bindings/counter/raspberrypi,pico-timer.yaml
+++ b/dts/bindings/counter/raspberrypi,pico-timer.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2023 TOKITA Hiroshi
 # SPDX-License-Identifier: Apache-2.0
 
-description: RaspberryPi Pico timer
+description: Raspberry Pi Pico timer
 
 compatible: "raspberrypi,pico-timer"
 
diff --git a/dts/bindings/timer/realtek,rts5912-slwtimer.yaml b/dts/bindings/counter/realtek,rts5912-slwtimer.yaml
similarity index 84%
rename from dts/bindings/timer/realtek,rts5912-slwtimer.yaml
rename to dts/bindings/counter/realtek,rts5912-slwtimer.yaml
index aa8a3f40510..b27eb33ba14 100644
--- a/dts/bindings/timer/realtek,rts5912-slwtimer.yaml
+++ b/dts/bindings/counter/realtek,rts5912-slwtimer.yaml
@@ -7,7 +7,7 @@ description: Realtek RTS5912 32-bit slow timer
 
 compatible: "realtek,rts5912-slwtimer"
 
-include: rtc.yaml
+include: base.yaml
 
 properties:
   reg:
@@ -22,7 +22,9 @@ properties:
     description: Maximum counter value the instance can handle
 
   clock-frequency:
+    type: int
     required: true
+    description: Clock frequency information for timer operation
 
   prescaler:
     type: int
diff --git a/dts/bindings/counter/realtek,rts5912-timer.yaml b/dts/bindings/counter/realtek,rts5912-timer.yaml
new file mode 100644
index 00000000000..c18ef866761
--- /dev/null
+++ b/dts/bindings/counter/realtek,rts5912-timer.yaml
@@ -0,0 +1,30 @@
+# Copyright (c) 2025, Realtek Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Realtek RTS5912 32bit timer
+
+compatible: "realtek,rts5912-timer"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  max-value:
+    type: int
+    required: true
+    description: Maximum counter value the instance can handle
+
+  clock-frequency:
+    type: int
+    required: true
+    description: Clock frequency information for timer operation
+
+  prescaler:
+    type: int
+    required: true
+    description: Timer frequency equals clock-frequency divided by the prescaler value
diff --git a/dts/bindings/counter/renesas,rz-gtm-counter.yaml b/dts/bindings/counter/renesas,rz-gtm-counter.yaml
new file mode 100644
index 00000000000..99c885db5f0
--- /dev/null
+++ b/dts/bindings/counter/renesas,rz-gtm-counter.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RZ GTM Counter
+
+compatible: "renesas,rz-gtm-counter"
+
+include: [base.yaml]
diff --git a/dts/bindings/counter/zephyr,native-sim-counter.yaml b/dts/bindings/counter/zephyr,native-sim-counter.yaml
new file mode 100644
index 00000000000..0c6749f37b1
--- /dev/null
+++ b/dts/bindings/counter/zephyr,native-sim-counter.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2022, Kumar Gala <galak@kernel.org>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Native_sim Counter
+
+compatible: "zephyr,native-sim-counter"
+
+include: base.yaml
diff --git a/dts/bindings/cpu/arm,cortex-a53.yaml b/dts/bindings/cpu/arm,cortex-a53.yaml
index ef47d271550..977440ab13e 100644
--- a/dts/bindings/cpu/arm,cortex-a53.yaml
+++ b/dts/bindings/cpu/arm,cortex-a53.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
 # SPDX-License-Identifier: Apache-2.0
 
-description: This is a representation of ARM Cortex-A53 CPU.
+description: ARM Cortex-A53 CPU
 
 compatible: "arm,cortex-a53"
 
diff --git a/dts/bindings/cpu/arm,cortex-a55.yaml b/dts/bindings/cpu/arm,cortex-a55.yaml
index f56db8367d5..3d2ff73fcf2 100644
--- a/dts/bindings/cpu/arm,cortex-a55.yaml
+++ b/dts/bindings/cpu/arm,cortex-a55.yaml
@@ -1,7 +1,7 @@
 # Copyright 2022 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-description: This is a representation of ARM Cortex-A55 CPU.
+description: ARM Cortex-A55 CPU
 
 compatible: "arm,cortex-a55"
 
diff --git a/dts/bindings/cpu/arm,cortex-a72.yaml b/dts/bindings/cpu/arm,cortex-a72.yaml
index 7d3bf52fbed..07b2438172a 100644
--- a/dts/bindings/cpu/arm,cortex-a72.yaml
+++ b/dts/bindings/cpu/arm,cortex-a72.yaml
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
-description: This is a representation of ARM Cortex-A72 CPU.
+description: ARM Cortex-A72 CPU
 
 compatible: "arm,cortex-a72"
 
diff --git a/dts/bindings/cpu/arm,cortex-a76.yaml b/dts/bindings/cpu/arm,cortex-a76.yaml
index bd51fa6e8f8..1f2419c603a 100644
--- a/dts/bindings/cpu/arm,cortex-a76.yaml
+++ b/dts/bindings/cpu/arm,cortex-a76.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 Intel Corp.
 # SPDX-License-Identifier: Apache-2.0
 
-description: This is a representation of ARM Cortex-A76 CPU.
+description: ARM Cortex-A76 CPU
 
 compatible: "arm,cortex-a76"
 
diff --git a/dts/bindings/cpu/arm,cortex-r52.yaml b/dts/bindings/cpu/arm,cortex-r52.yaml
index 3c7ca1ef5a3..09aa75deb90 100644
--- a/dts/bindings/cpu/arm,cortex-r52.yaml
+++ b/dts/bindings/cpu/arm,cortex-r52.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-description: This is a representation of ARM Cortex-R52 CPU.
+description: ARM Cortex-R52 CPU
 
 compatible: "arm,cortex-r52"
 
diff --git a/dts/bindings/cpu/arm,cortex-r82.yaml b/dts/bindings/cpu/arm,cortex-r82.yaml
index 2bcf3027bbd..517fcb53745 100644
--- a/dts/bindings/cpu/arm,cortex-r82.yaml
+++ b/dts/bindings/cpu/arm,cortex-r82.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021 Arm Limited (or its affiliates). All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-description: This is a representation of ARM Cortex-R82 CPU.
+description: ARM Cortex-R82 CPU
 
 compatible: "arm,cortex-r82"
 
diff --git a/dts/bindings/cpu/espressif,xtensa-lx6.yaml b/dts/bindings/cpu/espressif,xtensa-lx6.yaml
index 24dd830cb01..898a5e7cb26 100644
--- a/dts/bindings/cpu/espressif,xtensa-lx6.yaml
+++ b/dts/bindings/cpu/espressif,xtensa-lx6.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Espressif Xtensa CPU
+description: Espressif Xtensa LX6 CPU
 
 compatible: "espressif,xtensa-lx6"
 
@@ -32,3 +32,4 @@ properties:
     enum:
       - 40000000
       - 32000000
+      - 26000000
diff --git a/dts/bindings/cpu/espressif,xtensa-lx7.yaml b/dts/bindings/cpu/espressif,xtensa-lx7.yaml
index 33c6503122b..a91cd037ac9 100644
--- a/dts/bindings/cpu/espressif,xtensa-lx7.yaml
+++ b/dts/bindings/cpu/espressif,xtensa-lx7.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Espressif Xtensa CPU
+description: Espressif Xtensa LX7 CPU
 
 compatible: "espressif,xtensa-lx7"
 
@@ -31,4 +31,3 @@ properties:
     description: Value of the external XTAL connected to ESP32.
     enum:
       - 40000000
-      - 32000000
diff --git a/dts/bindings/cpu/gaisler,leon3.yaml b/dts/bindings/cpu/gaisler,leon3.yaml
index 6db8519e166..8d53fab1c10 100644
--- a/dts/bindings/cpu/gaisler,leon3.yaml
+++ b/dts/bindings/cpu/gaisler,leon3.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-description: A representation for Gaisler LEON3 CPU.
+description: Gaisler LEON3 CPU
 
 compatible: "gaisler,leon3"
 
diff --git a/dts/bindings/cpu/intel,bartlett-lake.yaml b/dts/bindings/cpu/intel,bartlett-lake.yaml
new file mode 100644
index 00000000000..1e1c1880e5b
--- /dev/null
+++ b/dts/bindings/cpu/intel,bartlett-lake.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Intel Corp.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Intel Bartlett Lake CPU
+
+compatible: "intel,bartlett-lake"
+
+include: cpu.yaml
diff --git a/dts/bindings/cpu/neorv32,cpu.yaml b/dts/bindings/cpu/neorv32,cpu.yaml
new file mode 100644
index 00000000000..fe37ce7a6eb
--- /dev/null
+++ b/dts/bindings/cpu/neorv32,cpu.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+description: NEORV32 RISC-V CPU
+
+compatible: "neorv32,cpu"
+
+include: riscv,cpus.yaml
diff --git a/dts/bindings/cpu/neorv32-cpu.yaml b/dts/bindings/cpu/neorv32-cpu.yaml
deleted file mode 100644
index b0983771e92..00000000000
--- a/dts/bindings/cpu/neorv32-cpu.yaml
+++ /dev/null
@@ -1,8 +0,0 @@
-# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
-# SPDX-License-Identifier: Apache-2.0
-
-description: NEORV32 RISC-V CPU
-
-compatible: "neorv32-cpu"
-
-include: riscv,cpus.yaml
diff --git a/dts/bindings/cpu/openhwgroup,cva6.yaml b/dts/bindings/cpu/openhwgroup,cva6.yaml
new file mode 100644
index 00000000000..e81428bfde3
--- /dev/null
+++ b/dts/bindings/cpu/openhwgroup,cva6.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2025 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: OpenHW Group CVA6 CPU
+
+compatible: "openhwgroup,cva6"
+
+include: riscv,cpus.yaml
+
+properties:
+  timebase-frequency:
+    required: true
+    type: int
+    description: Clock speed at which the core-local machine timer operates.
diff --git a/dts/bindings/cpu/qemu,riscv-virt.yaml b/dts/bindings/cpu/qemu,riscv-virt.yaml
index c4c5a8b174e..9f4f7406a26 100644
--- a/dts/bindings/cpu/qemu,riscv-virt.yaml
+++ b/dts/bindings/cpu/qemu,riscv-virt.yaml
@@ -2,7 +2,7 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-description: QEMU RISC-V virt machine CPU node
+description: QEMU RISC-V virt machine CPU
 
 compatible: "qemu,riscv-virt"
 
diff --git a/dts/bindings/cpu/wch,qingke-v2.yaml b/dts/bindings/cpu/wch,qingke-v2.yaml
index 0386a78fb8c..da04a18e29b 100644
--- a/dts/bindings/cpu/wch,qingke-v2.yaml
+++ b/dts/bindings/cpu/wch,qingke-v2.yaml
@@ -5,4 +5,4 @@ description: WCH QingKe V2 RISC-V MCU
 
 compatible: "wch,qingke-v2"
 
-include: cpu.yaml
+include: riscv,cpus.yaml
diff --git a/dts/bindings/cpu/wch,qingke-v4c.yaml b/dts/bindings/cpu/wch,qingke-v4c.yaml
new file mode 100644
index 00000000000..2fd160474c2
--- /dev/null
+++ b/dts/bindings/cpu/wch,qingke-v4c.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
+# SPDX-License-Identifier: Apache-2.0
+
+description: WCH QingKe V4C RISC-V MCU
+
+compatible: "wch,qingke-v4c"
+
+include: riscv,cpus.yaml
diff --git a/dts/bindings/cpu/zephyr,native-posix-cpu.yaml b/dts/bindings/cpu/zephyr,native-posix-cpu.yaml
index d5cc2a4ecc4..50a54ab6eb6 100644
--- a/dts/bindings/cpu/zephyr,native-posix-cpu.yaml
+++ b/dts/bindings/cpu/zephyr,native-posix-cpu.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-description: A representation for native_posix CPU.
+description: native_posix CPU
 
 compatible: "zephyr,native-posix-cpu"
 
diff --git a/dts/bindings/cpu/zephyr,native-sim-cpu.yaml b/dts/bindings/cpu/zephyr,native-sim-cpu.yaml
new file mode 100644
index 00000000000..804bf61fb23
--- /dev/null
+++ b/dts/bindings/cpu/zephyr,native-sim-cpu.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2021 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: native_sim CPU
+
+compatible: "zephyr,native-sim-cpu"
+
+include: cpu.yaml
diff --git a/dts/bindings/crypto/ti,cc23x0-aes.yaml b/dts/bindings/crypto/ti,cc23x0-aes.yaml
new file mode 100644
index 00000000000..6a1348dcea5
--- /dev/null
+++ b/dts/bindings/crypto/ti,cc23x0-aes.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) Copyright (c) 2024 BayLibre, SAS
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI CC23X0 AES accelerator.
+
+compatible: "ti,cc23x0-aes"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
diff --git a/dts/bindings/dac/adi,max22017-dac.yaml b/dts/bindings/dac/adi,max22017-dac.yaml
new file mode 100644
index 00000000000..3497791c079
--- /dev/null
+++ b/dts/bindings/dac/adi,max22017-dac.yaml
@@ -0,0 +1,74 @@
+# Copyright (c) 2024 Analog Devices Inc.
+# Copyright (c) 2024 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+include: dac-controller.yaml
+
+description: Analog Devices MAX22017 16bit DAC
+
+properties:
+  "#io-channel-cells":
+    const: 2
+
+  num-channels:
+    type: int
+    description: Number of DAC output channels.
+    default: 2
+
+  resolution:
+    type: int
+    description: DAC resolution.
+    default: 16
+
+  busy-gpios:
+    description: Busy line indicating the DAC is calculating next sample.
+    type: phandle-array
+
+  ldac-gpios:
+    description: Load both DAC latches at the same time.
+    type: phandle-array
+
+  polarity-mode:
+    description: |
+      Unipolar/bipolar mode selection for channels.
+      0 Indicates bipolar mode and 1 unipolar mode.
+      The default settings to bipolar here align with the default mode of the device.
+    default: [0, 0]
+    type: uint8-array
+
+  dac-mode:
+    description: |
+      Voltage/current mode selection for channels.
+      0 indicates voltage mode and 1 indicates current mode.
+      The default settings to voltage mode here align with the default mode of the device.
+    default: [0, 0]
+    type: uint8-array
+
+  latch-mode:
+    description: |
+      Latch mode selection for channels.
+      0 means the channel is not latched, 1 means latched.
+      The default settings to non latched should be more straightforward to use than the latched
+      mode. The latch mode can be used eitheir with the ldac-gpios to load both channels at the
+      same time or if no ldac-gpios property is set, latching will be done per channel with a
+      register write.
+    default: [0, 0]
+    type: uint8-array
+
+  overcurrent-mode:
+    description: |
+      Overcurrent mode selection for channels.
+      0 for current limiting mode
+      1 for short circuit protection auto power up mode
+      2 for short circuit protection shutdown mode
+      The default setting to current limiting mode here aligns with the default mode of the device.
+    default: [0, 0]
+    type: uint8-array
+
+  timeout:
+    description: |
+      Timeout in ms.
+      The value should be between 100 and 1600ms in increments of 100ms.
+    type: int
+
+compatible: "adi,max22017-dac"
diff --git a/dts/bindings/dac/atmel,sam0-dac.yaml b/dts/bindings/dac/atmel,sam0-dac.yaml
index 05ffd62d337..8a0f92f0fe5 100644
--- a/dts/bindings/dac/atmel,sam0-dac.yaml
+++ b/dts/bindings/dac/atmel,sam0-dac.yaml
@@ -1,4 +1,5 @@
 # Copyright (c) 2020 Google LLC.
+# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
 description: Atmel SAM0 family DAC
@@ -8,6 +9,7 @@ compatible: "atmel,sam0-dac"
 include:
   - name: dac-controller.yaml
   - name: pinctrl-device.yaml
+  - name: atmel,assigned-clocks.yaml
 
 properties:
   reg:
@@ -19,6 +21,12 @@ properties:
   clock-names:
     required: true
 
+  atmel,assigned-clocks:
+    required: true
+
+  atmel,assigned-clock-names:
+    required: true
+
   reference:
     type: string
     description: Reference voltage source
diff --git a/dts/bindings/dac/espressif,esp32-dac.yaml b/dts/bindings/dac/espressif,esp32-dac.yaml
index 39c63d7642e..18f24c1f209 100644
--- a/dts/bindings/dac/espressif,esp32-dac.yaml
+++ b/dts/bindings/dac/espressif,esp32-dac.yaml
@@ -2,8 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    Espressif Digital to Analog converter (DAC) control node
-    is part of the RTC low-power domain and belongs to the SENSE
+    ESP32 Digital to Analog converter (DAC)
+
+    Part of the RTC low-power domain and belongs to the SENSE
     peripherals set. RTC peripherals has GPIOs controlled by the
     RTCIO mux, which is separated from the main IO mux.
 
diff --git a/dts/bindings/dac/microchip,mcp4728.yaml b/dts/bindings/dac/microchip,mcp4728.yaml
index 0a0d8d291c7..f3fb95a3379 100644
--- a/dts/bindings/dac/microchip,mcp4728.yaml
+++ b/dts/bindings/dac/microchip,mcp4728.yaml
@@ -8,7 +8,7 @@ properties:
   "#io-channel-cells":
     const: 1
 
-  voltage_reference:
+  voltage-reference:
     type: array
     required: true
     description: |
@@ -17,7 +17,7 @@ properties:
       1 - Internal voltage reference (2.048V)
       Note: array entries correspond to the successive channels
 
-  power_down_mode:
+  power-down-mode:
     type: array
     required: true
     description: |
diff --git a/dts/bindings/dac/renesas,ra-dac-global.yaml b/dts/bindings/dac/renesas,ra-dac-global.yaml
new file mode 100644
index 00000000000..c9b8b6e790d
--- /dev/null
+++ b/dts/bindings/dac/renesas,ra-dac-global.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA DAC Controller Global
+
+compatible: "renesas,ra-dac-global"
+
+include: [base.yaml]
+
+properties:
+  has-internal-output:
+    type: boolean
+    description: |
+      True if the SoC supports the "internal output" feature in the DAC HWIP.
+      Note: If the SoC doesn't support this "internal output" features,
+            it cannot support the "internal" feature.
+
+  has-output-amplifier:
+    type: boolean
+    description: |
+      True if the SoC supports the "output amplifier" feature in the DAC HWIP.
+
+  has-chargepump:
+    type: boolean
+    description: |
+      True if the SoC supports the "chargepump" feature in the DAC HWIP.
+      Note: If the SoC doesn't support the "output amplifier" and "charge pump" features,
+            it cannot support the "buffer" feature.
+
+  has-davrefcr:
+    type: boolean
+    description: |
+      True if the SoC supports the D/A VREF configuration in the DAC HWIP.
diff --git a/dts/bindings/dac/renesas,ra-dac.yaml b/dts/bindings/dac/renesas,ra-dac.yaml
new file mode 100644
index 00000000000..aabb8a976c9
--- /dev/null
+++ b/dts/bindings/dac/renesas,ra-dac.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA DAC Controller
+
+compatible: "renesas,ra-dac"
+
+include: [dac-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  "#io-channel-cells":
+    const: 1
+
+io-channel-cells:
+  - output
diff --git a/dts/bindings/dac/st,stm32-dac.yaml b/dts/bindings/dac/st,stm32-dac.yaml
index 5b142d528bc..325ac2495a1 100644
--- a/dts/bindings/dac/st,stm32-dac.yaml
+++ b/dts/bindings/dac/st,stm32-dac.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2020 Libre Solar Technologies GmbH
 # SPDX-License-Identifier: Apache-2.0
 
-description: ST STM32 family DAC
+description: STM32 family DAC
 
 compatible: "st,stm32-dac"
 
diff --git a/dts/bindings/dac/ti,dac161s997.yaml b/dts/bindings/dac/ti,dac161s997.yaml
new file mode 100644
index 00000000000..f932643ff24
--- /dev/null
+++ b/dts/bindings/dac/ti,dac161s997.yaml
@@ -0,0 +1,14 @@
+# Copyright (C) 2025 Vitrolife A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI DAC161S997 16-bit 1 channel SPI DAC for 4-20 mA loops
+
+compatible: "ti,dac161s997"
+
+include: [dac-controller.yaml, spi-device.yaml]
+
+properties:
+  errb-gpios:
+    type: phandle-array
+    description: |
+      DAC error signal output. If set a callback can be set to read what caused the error.
diff --git a/dts/bindings/dai/intel,adsp-dmic-vss.yaml b/dts/bindings/dai/intel,adsp-dmic-vss.yaml
index 6994e3baf6f..72ae40f1d6a 100644
--- a/dts/bindings/dai/intel,adsp-dmic-vss.yaml
+++ b/dts/bindings/dai/intel,adsp-dmic-vss.yaml
@@ -2,7 +2,7 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-description: Intel DMIC Vendor SHIM controller
+description: Intel DMIC Vendor SHIM Controller
 
 compatible: "intel,adsp-dmic-vss"
 
diff --git a/dts/bindings/dai/intel,dai-dmic.yaml b/dts/bindings/dai/intel,dai-dmic.yaml
index 44c886b0d6a..9e0b4ecec8f 100644
--- a/dts/bindings/dai/intel,dai-dmic.yaml
+++ b/dts/bindings/dai/intel,dai-dmic.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-description: Intel Digital PDM Microphone (DMIC) node
+description: Intel Digital PDM Microphone (DMIC)
 
 compatible: "intel,dai-dmic"
 
diff --git a/dts/bindings/dai/mediatek,afe.yaml b/dts/bindings/dai/mediatek,afe.yaml
new file mode 100644
index 00000000000..18f5165fba6
--- /dev/null
+++ b/dts/bindings/dai/mediatek,afe.yaml
@@ -0,0 +1,63 @@
+description: Mediatek Audio Front End
+
+compatible: "mediatek,afe"
+
+include: base.yaml
+
+properties:
+  dai-id:
+    type: int
+    required: true
+    description: Host-defined SOF DAI index.  Must match the Linux kernel driver.
+  afe-name:
+    type: string
+    required: true
+  downlink:
+    type: boolean
+    description: True/present for downlink (capture) channels
+
+  # These three are two-register arrays defining the DSP registers
+  # that store the hi and low words of a 64 bit bus/host address.
+  #
+  base:
+    type: array
+  end:
+    type: array
+  cur:
+    type: array
+
+  # The remaining registers below are three-cell arrays describing a
+  # bit field as <addr lshift width>.  Most of them are defaultable by
+  # the driver and can be eliminated from DTS for hardware that does
+  # not support the feature.  See the driver source for details.
+  #
+  enable:
+    type: array
+    description: Channel enable flag
+  agent-disable:
+    type: array
+    description: Channel disable flag
+  fs:
+    type: array
+    description: Sample rate register
+  hd:
+    type: array
+    description: Sample format register
+  ch-num:
+    type: array
+    description: Channel count register
+  mono:
+    type: array
+    description: Mono flag register
+  mono-invert:
+    type: boolean
+    description: Sense/meaning of mono flag
+  quad-ch:
+    type: array
+    description: Quad channel flag register
+  int-odd:
+    type: array
+  msb:
+    type: array
+  msb2:
+    type: array
diff --git a/dts/bindings/dai/nxp,dai-esai.yaml b/dts/bindings/dai/nxp,dai-esai.yaml
index b179a8c6b9b..925e527ef70 100644
--- a/dts/bindings/dai/nxp,dai-esai.yaml
+++ b/dts/bindings/dai/nxp,dai-esai.yaml
@@ -1,7 +1,7 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-description: NXP Enhanced Serial Audio Interface (ESAI) node
+description: NXP Enhanced Serial Audio Interface (ESAI)
 
 compatible: "nxp,dai-esai"
 
diff --git a/dts/bindings/dai/nxp,dai-micfil.yaml b/dts/bindings/dai/nxp,dai-micfil.yaml
new file mode 100644
index 00000000000..870484dcfd2
--- /dev/null
+++ b/dts/bindings/dai/nxp,dai-micfil.yaml
@@ -0,0 +1,25 @@
+# Copyright 2023 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP PDM MICFIL
+
+compatible: "nxp,dai-micfil"
+
+include: [base.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+  dai-index:
+    type: int
+    description: |
+      Use this property to specify the index of the DAI. At the
+      moment, this is only used by SOF to fetch the "struct device"
+      associated with the DAI whose index Linux passes to SOF
+      through an IPC. If this property is not specified, the DAI
+      index will be considered 0.
+  fifo-depth:
+    type: int
+    required: true
+    description: |
+      Depth (in words) for each channel's FIFO.
diff --git a/dts/bindings/dai/nxp,dai-sai.yaml b/dts/bindings/dai/nxp,dai-sai.yaml
index 2d9f7e34997..3b0f7a5929e 100644
--- a/dts/bindings/dai/nxp,dai-sai.yaml
+++ b/dts/bindings/dai/nxp,dai-sai.yaml
@@ -1,7 +1,47 @@
 # Copyright 2023 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-description: NXP Synchronous Audio Interface (SAI) node
+description: |
+  NXP Synchronous Audio Interface (SAI)
+
+  Below you may find some configuration examples:
+
+  1) Configuring SAI1 for i.MX8QM MEK board
+
+  #include <zephyr/dt-bindings/clock/imx_ccm.h>
+
+  dai@59050000 {
+    compatible = "nxp,dai-sai";
+    reg = <0x59050000 DT_SIZE_K(64)>;
+    interrupt-parent = <&master5>;
+    interrupts = <28>;
+    clocks = <&ccm IMX_CCM_SAI1_CLK 0x0 0x0>;
+    clock-names = "bus";
+    dai-index = <1>;
+    dmas = <&edma0 15 0>, <&edma0 14 0>;
+    dma-names = "tx", "rx";
+    rx-fifo-watermark = <48>;
+    tx-fifo-watermark = <2>;
+    fifo-depth = <48>;
+    rx-sync-mode = <1>;
+  };
+
+  2) Configuring SAI6 for i.MX8ULP EVK9 board
+
+  dai@2da90000 {
+    compatible = "nxp,dai-sai";
+    reg = <0x2da90000 DT_SIZE_K(4)>;
+    interrupt-parent = <&clic>;
+    interrupts = <24 0 0>;
+    dmas = <&edma2 0 72>, <&edma2 1 71>;
+    dma-names = "tx", "rx";
+    dai-index = <6>;
+    rx-fifo-watermark = <8>;
+    tx-fifo-watermark = <1>;
+    fifo-depth = <8>;
+    rx-sync-mode = <1>;
+    tx-dataline = <2>;
+  };
 
 compatible: "nxp,dai-sai"
 
@@ -12,100 +52,46 @@ properties:
     required: true
   mclk-is-output:
     type: boolean
-    description: |
-      Use this property to set the SAI MCLK as output or as input.
-      By default, if this property is not specified, MCLK will be
-      set as input. Setting the MCLK as output for SAIs which don't
-      support MCLK configuration will result in a BUILD_ASSERT()
-      failure.
+    description: MCLK is configured as output.
   rx-fifo-watermark:
     type: int
-    description: |
-      Use this property to specify the watermark value for the TX
-      FIFO. This value needs to be in FIFO words (NOT BYTES). This
-      value needs to be in the following interval: (0, DEFAULT_FIFO_DEPTH],
-      otherwise a BUILD_ASSERT() failure will be raised.
+    description: Watermark value (in FIFO words) of RX FIFO.
   tx-fifo-watermark:
     type: int
-    description: |
-      Use this property to specify the watermark value for the RX
-      FIFO. This value needs to be in FIFO words (NOT BYTES). This
-      value needs to be in the following interval: (0, DEFAULT_FIFO_DEPTH],
-      otherwise a BUILD_ASSERT() failure will be raised.
+    description: Watermark value (in FIFO words) of TX FIFO.
   interrupts:
     required: true
   fifo-depth:
     type: int
-    description: |
-      Use this property to set the FIFO depth that will be reported
-      to other applications calling dai_get_properties(). This value
-      should be in the following interval: (0, DEFAULT_FIFO_DEPTH],
-      otherwise a BUILD_ASSERT() failure will be raised.
-      By DEFAULT_FIFO_DEPTH we mean the actual (hardware) value of
-      the FIFO depth. This is needed because some applications (e.g: SOF)
-      use this value to compute the DMA burst size, in which case
-      DEFAULT_FIFO_DEPTH cannot be used. Generally, reporting a false
-      FIFO depth should be avoided. Please note that the sanity check
-      for tx/rx-fifo-watermark uses DEFAULT_FIFO_DEPTH instead of this
-      value so use with caution. If unsure, it's better to simply not
-      use this property, in which case the reported value will be
-      DEFAULT_FIFO_DEPTH.
+    description: Size (in FIFO words) of the TX/RX FIFO.
   dai-index:
     type: int
-    description: |
-      Use this property to specify the index of the DAI. At the
-      moment, this is only used by SOF to fetch the "struct device"
-      associated with the DAI whose index Linux passes to SOF
-      through an IPC. If this property is not specified, the DAI
-      index will be considered 0.
+    description: Index of the DAI instance. Must match Linux side.
   tx-sync-mode:
     type: int
     enum:
       - 0
       - 1
     description: |
-      Use this property to specify which synchronization mode to use
-      for the transmitter. At the moment, the only supported modes are:
-        1) The transmitter is ASYNC (0)
-        2) The transmitter is in SYNC with the receiver (1)
-      If this property is not specified, the transmitter will be set to ASYNC.
-      If one side is SYNC then the other MUST be ASYNC. Failing to meet this
-      condition will result in a failed BUILD_ASSERT().
+      Transmitter synchronization mode.
+
+      0: transmitter is ASYNC to receiver
+      1: transmitter is SYNC with receiver
   rx-sync-mode:
     type: int
     enum:
       - 0
       - 1
     description: |
-      Use this property to specify which synchronization mode to use
-      for the receiver. At the moment, the only supported modes are:
-        1) The receiver is ASYNC (0)
-        2) The receiver is in SYNC with the transmitter (1)
-      If this property is not specified, the receiver will be set to ASYNC.
-      If one side is SYNC then the other MUST be ASYNC. Failing to meet this
-      condition will result in a failed BUILD_ASSERT().
+      Receiver synchronization mode.
+
+      0: receiver is ASYNC to transmitter
+      1: receiver is SYNC with transmitter
   tx-dataline:
     type: int
     description: |
-      Use this property to specify which transmission data line the SAI should
-      use. To find out which transmission line you should use you can:
-        1) Check the TRM and see if your SAI instance is multiline. If not then
-        you're going to use transmission line 0.
-        2) If your SAI is multiline then you need to check the datasheet and see
-        the index of the transmission line that's connected to your consumer
-        (e.g: the codec).
-      The indexing of the data line starts at 0. If this property is not specified
-      then the index of the transmission data line will be 0.
-      Please note that "channel" and "data line" are synnonyms in this context.
+      Index of the data line to transmit data on in multiline SAI instances.
   rx-dataline:
     type: int
     description: |
-      Use this property to specify which receive transmission data line the SAI should
-      use. To find out which receive line you should use you can:
-        1) Check the TRM and see if your SAI instance is multiline. If not then
-        you're going to use receive line 0.
-        2) If your SAI is multiline then you need to check the datasheet and see
-        the index of the receive line that's connected to your consumer (e.g: the codec).
-      The indexing of the data line starts at 0. If this property is not specified
-      then the index of the receive data line will be 0.
-      Please note that "channel" and "data line" are synnonyms in this context.
+      Index of the data line to receive data on in multiline SAI instances.
diff --git a/dts/bindings/display/ftdi,ft800.yaml b/dts/bindings/display/ftdi,ft800.yaml
index a0753bef98c..d09b24e1fc7 100644
--- a/dts/bindings/display/ftdi,ft800.yaml
+++ b/dts/bindings/display/ftdi,ft800.yaml
@@ -20,7 +20,7 @@ properties:
       typical main clock was 48MHz and this value is 5, the PCLK
       will be 9.6 MHz. Must be positive value to enable the screen
 
-  pclk_pol:
+  pclk-pol:
     type: int
     required: true
     description: |
diff --git a/dts/bindings/display/nxp,dcnano-lcdif.yaml b/dts/bindings/display/nxp,dcnano-lcdif.yaml
index 154ea323f9a..376b61855ef 100644
--- a/dts/bindings/display/nxp,dcnano-lcdif.yaml
+++ b/dts/bindings/display/nxp,dcnano-lcdif.yaml
@@ -1,4 +1,4 @@
-# Copyright 2023 NXP
+# Copyright 2023,2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 description: NXP DCNano LCDIF (LCD Interface) controller
@@ -32,3 +32,11 @@ properties:
       - "24-bit" # 24 Bit
     description:
       LCD data bus width. The default is set to the reset value of 24-bit
+
+  version:
+    type: string
+    description:
+      The version of the ip
+    enum:
+      - "DCnano"
+      - "DC8000"
diff --git a/dts/bindings/display/nxp,imx-elcdif.yaml b/dts/bindings/display/nxp,imx-elcdif.yaml
index a5ef4f13ded..cc568f20f57 100644
--- a/dts/bindings/display/nxp,imx-elcdif.yaml
+++ b/dts/bindings/display/nxp,imx-elcdif.yaml
@@ -27,7 +27,6 @@ properties:
 
   backlight-gpios:
     type: phandle-array
-    required: true
     description:
       LCB backlight control gpio. Driver will initialize this GPIO to active high
 
diff --git a/dts/bindings/display/renesas,ra-glcdc.yaml b/dts/bindings/display/renesas,ra-glcdc.yaml
index c57816709c1..c4186d1b761 100644
--- a/dts/bindings/display/renesas,ra-glcdc.yaml
+++ b/dts/bindings/display/renesas,ra-glcdc.yaml
@@ -1,4 +1,4 @@
-# Copyright (c) 2024 Renesas Electronics Corporation
+# Copyright (c) 2024-2025 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 description: Renesas Graphic LCD controller
@@ -15,10 +15,9 @@ properties:
     required: true
 
   pinctrl-0:
-    required: true
-
-  pinctrl-names:
-    required: true
+    description: |
+      Provide a pin configuration for using parallel pixel output. In combination with DSI HOST
+      the pin configuration is not necessary due to dedicated (MIPI D-PHY) pins.
 
   interrupts:
     required: true
@@ -30,11 +29,74 @@ properties:
 
   backlight-gpios:
     type: phandle-array
-    required: true
     description: |
       The BLn pin is asserted to control the backlight of the panel.
       The sensor receives this as an active-high signal.
 
+  output-pin-hsync:
+    type: string
+    enum:
+      - "TCON_PIN_NONE"
+      - "TCON_PIN_0"
+      - "TCON_PIN_1"
+      - "TCON_PIN_2"
+      - "TCON_PIN_3"
+    description: Select the Parallel LCD HSYNC pin. Please do not select if using DSI Display.
+
+  output-pin-vsync:
+    type: string
+    enum:
+      - "TCON_PIN_NONE"
+      - "TCON_PIN_0"
+      - "TCON_PIN_1"
+      - "TCON_PIN_2"
+      - "TCON_PIN_3"
+    description: Select the Parallel LCD VSYNC pin. Please do not select if using DSI Display.
+
+  output-pin-de:
+    type: string
+    enum:
+      - "TCON_PIN_NONE"
+      - "TCON_PIN_0"
+      - "TCON_PIN_1"
+      - "TCON_PIN_2"
+      - "TCON_PIN_3"
+    description: Select the Parallel LCD DE pin. Please do not select if using DSI Display.
+
+  output-clock-divisor:
+    type: int
+    enum: [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 16, 24, 32]
+    description: |
+      Select the GLCDC clock frequency division ratio to output for panel.
+
+  output-endian:
+    type: string
+    enum:
+      - "LITTLE"
+      - "BIG"
+    description: Select the output data bit order. Default is little endian.
+
+  output-color-oder:
+    type: string
+    enum:
+      - "RGB"
+      - "GBR"
+    description: Select the output color order in pixel. Default is RGB.
+
+  output-data-signal-polarity:
+    type: string
+    enum:
+      - "LOACTIVE"
+      - "HIACTIVE"
+    description: Select the output data enable signal polarity. Default is high active.
+
+  output-signal-sync-edge:
+    type: string
+    enum:
+      - "FALLING"
+      - "RISING"
+    description: Select the output signal synchronization edge. Default is falling edge.
+
   input-pixel-format:
     type: int
     required: true
@@ -46,3 +108,19 @@ properties:
     required: true
     description: |
       Initial output Pixel format for Graphic LCD controller.
+
+  def-back-color-alpha:
+    type: int
+    description: Default display background color - alpha
+
+  def-back-color-red:
+    type: int
+    description: Default display background color - red
+
+  def-back-color-green:
+    type: int
+    description: Default display background color - green
+
+  def-back-color-blue:
+    type: int
+    description: Default display background color - blue
diff --git a/dts/bindings/display/sinowealth,sh1106-spi.yaml b/dts/bindings/display/sinowealth,sh1106-spi.yaml
index 5fe3a2cf0f5..5bb843c365d 100644
--- a/dts/bindings/display/sinowealth,sh1106-spi.yaml
+++ b/dts/bindings/display/sinowealth,sh1106-spi.yaml
@@ -8,7 +8,7 @@ compatible: "sinowealth,sh1106"
 include: ["solomon,ssd1306fb-common.yaml", "spi-device.yaml"]
 
 properties:
-  data_cmd-gpios:
+  data-cmd-gpios:
     type: phandle-array
     required: true
     description: D/C# pin.
diff --git a/dts/bindings/display/sitronix,st7567-common.yaml b/dts/bindings/display/sitronix,st7567-common.yaml
new file mode 100644
index 00000000000..1152a781759
--- /dev/null
+++ b/dts/bindings/display/sitronix,st7567-common.yaml
@@ -0,0 +1,44 @@
+# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+# SPDX-License-Identifier: Apache-2.0
+
+include: display-controller.yaml
+
+properties:
+  column-offset:
+    type: int
+    required: true
+    description: 8-bits start column address
+
+  line-offset:
+    type: int
+    required: true
+    description: 6-bits start line offset
+
+  regulation-ratio:
+    type: int
+    required: true
+    description: Regulation resistor ratio (3-bits RR2 RR1 RR0)
+
+  segment-invdir:
+    type: boolean
+    description: Scan direction is from last SEG output to first SEG output
+
+  com-invdir:
+    type: boolean
+    description: Scan direction is from last COM output to first COM output
+
+  inversion-on:
+    type: boolean
+    description: Invert display
+
+  bias:
+    type: boolean
+    description: Bias setting (0 for 1/9, or 1 for 1/7)
+
+  reset-gpios:
+    type: phandle-array
+    description: RESET pin.
+
+      The RESET pin of ST7567 is active low.
+      If connected directly, the MCU pin should be configured
+      as active low.
diff --git a/dts/bindings/display/sitronix,st7567-i2c.yaml b/dts/bindings/display/sitronix,st7567-i2c.yaml
new file mode 100644
index 00000000000..a0554d902a6
--- /dev/null
+++ b/dts/bindings/display/sitronix,st7567-i2c.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+# SPDX-License-Identifier: Apache-2.0
+
+description: ST7567 132x65 dot-matrix LCD controller on I2C bus
+
+compatible: "sitronix,st7567"
+
+include: ["sitronix,st7567-common.yaml", "i2c-device.yaml"]
diff --git a/dts/bindings/display/sitronix,st7567-spi.yaml b/dts/bindings/display/sitronix,st7567-spi.yaml
new file mode 100644
index 00000000000..e90722e38ef
--- /dev/null
+++ b/dts/bindings/display/sitronix,st7567-spi.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+# SPDX-License-Identifier: Apache-2.0
+
+description: ST7567 132x65 dot-matrix LCD controller on SPI bus
+
+compatible: "sitronix,st7567"
+
+include: ["sitronix,st7567-common.yaml", "spi-device.yaml"]
+
+properties:
+  data-cmd-gpios:
+    type: phandle-array
+    required: true
+    description: D/C# pin.
diff --git a/dts/bindings/display/sitronix,st7701.yaml b/dts/bindings/display/sitronix,st7701.yaml
new file mode 100644
index 00000000000..d17aff0dcf4
--- /dev/null
+++ b/dts/bindings/display/sitronix,st7701.yaml
@@ -0,0 +1,88 @@
+# Copyright (c) 2025 Arduino SA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Sitronix ST7701 Panel
+
+compatible: "sitronix,st7701"
+
+include: [mipi-dsi-device.yaml, display-controller.yaml]
+
+properties:
+  reset-gpios:
+    type: phandle-array
+    description: |
+      The RESETn pin is asserted to disable the sensor causing a hard
+      reset.  The sensor receives this as an active-low signal.
+
+  bl-gpios:
+    type: phandle-array
+    description: |
+      The BLn pin is asserted to control the backlight of the panel.
+      The sensor receives this as an active-high signal.
+
+  rotation:
+    type: int
+    default: 0
+    enum:
+      - 0
+      - 90
+      - 180
+      - 270
+    description: |
+      Display rotation (CW) in degrees. Defaults to 0, display default.
+
+  gip-e0:
+    type: uint8-array
+    description: GIP setting at address 0xE0.
+
+  gip-e1:
+    type: uint8-array
+    description: GIP setting at address 0xE1.
+
+  gip-e2:
+    type: uint8-array
+    description: GIP setting at address 0xE2.
+
+  gip-e3:
+    type: uint8-array
+    description: GIP setting at address 0xE3.
+
+  gip-e4:
+    type: uint8-array
+    description: GIP setting at address 0xE4.
+
+  gip-e5:
+    type: uint8-array
+    description: GIP setting at address 0xE5.
+
+  gip-e6:
+    type: uint8-array
+    description: GIP setting at address 0xE6.
+
+  gip-e7:
+    type: uint8-array
+    description: GIP setting at address 0xE7.
+
+  gip-e8:
+    type: uint8-array
+    description: GIP setting at address 0xE8.
+
+  gip-eb:
+    type: uint8-array
+    description: GIP setting at address 0xEB.
+
+  gip-ec:
+    type: uint8-array
+    description: GIP setting at address 0xEC.
+
+  gip-ed:
+    type: uint8-array
+    description: GIP setting at address 0xED.
+
+  pvgamctrl:
+    type: uint8-array
+    description: Positive voltage gamma control.
+
+  nvgamctrl:
+    type: uint8-array
+    description: Negative voltage gamma control.
diff --git a/dts/bindings/display/sitronix,st7789v.yaml b/dts/bindings/display/sitronix,st7789v.yaml
index 9b503eb86ba..7230eb92a2e 100644
--- a/dts/bindings/display/sitronix,st7789v.yaml
+++ b/dts/bindings/display/sitronix,st7789v.yaml
@@ -96,5 +96,13 @@ properties:
     required: true
     description: RGB Interface Control Parameter
 
+  ready-time-ms:
+    type: int
+    default: 40
+    description: |
+      Time it takes for the device from power up to become responsive and
+      accepting commands. Defaults to 40ms (found by trial and error) if not
+      provided.
+
   mipi-mode:
     required: true
diff --git a/dts/bindings/display/solomon,ssd1306fb-spi.yaml b/dts/bindings/display/solomon,ssd1306fb-spi.yaml
index e382a1a5319..3d3d5ecde2a 100644
--- a/dts/bindings/display/solomon,ssd1306fb-spi.yaml
+++ b/dts/bindings/display/solomon,ssd1306fb-spi.yaml
@@ -8,7 +8,7 @@ compatible: "solomon,ssd1306fb"
 include: ["solomon,ssd1306fb-common.yaml", "spi-device.yaml"]
 
 properties:
-  data_cmd-gpios:
+  data-cmd-gpios:
     type: phandle-array
     required: true
     description: D/C# pin.
diff --git a/dts/bindings/display/solomon,ssd1309fb-i2c.yaml b/dts/bindings/display/solomon,ssd1309fb-i2c.yaml
new file mode 100644
index 00000000000..ee953a07cc4
--- /dev/null
+++ b/dts/bindings/display/solomon,ssd1309fb-i2c.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2025, Marcio Ribeiro
+# SPDX-License-Identifier: Apache-2.0
+
+description: SSD1309 128x64 dot-matrix display controller on I2C bus
+
+compatible: "solomon,ssd1309fb"
+
+include: ["solomon,ssd1306fb-common.yaml", "i2c-device.yaml"]
diff --git a/dts/bindings/display/solomon,ssd1309fb-spi.yaml b/dts/bindings/display/solomon,ssd1309fb-spi.yaml
new file mode 100644
index 00000000000..4a24a35d7cd
--- /dev/null
+++ b/dts/bindings/display/solomon,ssd1309fb-spi.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2025, Marcio Ribeiro
+# SPDX-License-Identifier: Apache-2.0
+
+description: SSD1309 128x64 dot-matrix display controller on SPI bus
+
+compatible: "solomon,ssd1309fb"
+
+include: ["solomon,ssd1306fb-common.yaml", "spi-device.yaml"]
+
+properties:
+  data_cmd-gpios:
+    type: phandle-array
+    required: true
+    description: D/C# pin.
diff --git a/dts/bindings/dma/espressif,esp32-gdma.yaml b/dts/bindings/dma/espressif,esp32-gdma.yaml
index f50745dd842..ecbdc58057c 100644
--- a/dts/bindings/dma/espressif,esp32-gdma.yaml
+++ b/dts/bindings/dma/espressif,esp32-gdma.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Espressif's GDMA (General Direct Memory Access) Node
+  ESP32 GDMA (General Direct Memory Access)
 
   General Direct Memory Access (GDMA) is a feature that allows
   peripheral-to-memory, memory-to-peripheral, and memory-to-memory
@@ -16,7 +16,7 @@ description: |
   ESP32C3's Peripherals with GDMA:
   * SPI2
   * UHCI0 (UART0/UART1)
-  * I2S (Not Supported yet)
+  * I2S
   * AES (Not Supported yet)
   * SHA (Not Supported yet)
   * ADC
@@ -29,12 +29,12 @@ description: |
   * SPI2
   * SPI3
   * UHCI0
-  * I2S0 (Not Supported yet)
-  * I2S1 (Not Supported yet)
-  * LCD/CAM (Not Supported yet)
+  * I2S0
+  * I2S1
+  * LCD/CAM
   * AES (Not Supported yet)
   * SHA (Not Supported yet)
-  * ADC (Not Supported yet)
+  * ADC
   * RMT (Not Supported yet)
 
 compatible: "espressif,esp32-gdma"
diff --git a/dts/bindings/dma/infineon,cat1-dma.yaml b/dts/bindings/dma/infineon,cat1-dma.yaml
new file mode 100644
index 00000000000..015c7be5524
--- /dev/null
+++ b/dts/bindings/dma/infineon,cat1-dma.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
+# an affiliate of Cypress Semiconductor Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+description: Infineon CAT1 DMA
+
+compatible: "infineon,cat1-dma"
+
+include: dma-controller.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  "#dma-cells":
+    const: 1
+
+dma-cells:
+  - channel
diff --git a/dts/bindings/dma/intel,adsp-gpdma.yaml b/dts/bindings/dma/intel,adsp-gpdma.yaml
index e71f05604eb..db929a8b8a8 100644
--- a/dts/bindings/dma/intel,adsp-gpdma.yaml
+++ b/dts/bindings/dma/intel,adsp-gpdma.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Intel ADSP Designware based General Purpose DMA Controller node
+description: Intel ADSP Designware based General Purpose DMA Controller
 
 compatible: "intel,adsp-gpdma"
 
diff --git a/dts/bindings/dma/intel,lpss.yaml b/dts/bindings/dma/intel,lpss.yaml
index d9fc4a60f11..733adf33762 100644
--- a/dts/bindings/dma/intel,lpss.yaml
+++ b/dts/bindings/dma/intel,lpss.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2019 Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-description: LPSS DMA Controller node
+description: LPSS DMA Controller
 
 compatible: "intel,lpss"
 
diff --git a/dts/bindings/dma/nxp,edma.yaml b/dts/bindings/dma/nxp,edma.yaml
index d5c58f624ad..0521ffd689b 100644
--- a/dts/bindings/dma/nxp,edma.yaml
+++ b/dts/bindings/dma/nxp,edma.yaml
@@ -1,7 +1,7 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-description: NXP enhanced Direct Memory Access (eDMA) node
+description: NXP enhanced Direct Memory Access (eDMA)
 
 compatible: "nxp,edma"
 
diff --git a/dts/bindings/dma/nxp,mcux-edma.yaml b/dts/bindings/dma/nxp,mcux-edma.yaml
index 57e79378c04..9027390c1a5 100644
--- a/dts/bindings/dma/nxp,mcux-edma.yaml
+++ b/dts/bindings/dma/nxp,mcux-edma.yaml
@@ -1,4 +1,4 @@
-# Copyright (c) 2020, NXP
+# Copyright (c) 2020,2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 description: NXP MCUX EDMA controller
@@ -40,7 +40,7 @@ properties:
     type: boolean
     description: If the DMA controller supports memory to memory transfer
 
-  nxp,a_on:
+  nxp,a-on:
     type: boolean
     description: If the DMA controller supports always on
 
@@ -65,6 +65,19 @@ properties:
     description: |
       eDMA IP revision number.
 
+  channels-shared-irq-mask:
+    type: array
+    description: |
+      Describes channel enabled mask value on every IRQ.
+      The channel number is mapped to the bit value of array element value.
+      If the interrupt is shared on one channel number, the correspongding
+      bit is set to 1.
+      Please note each element of the array must be 32-bit. If there are more
+      than 32 channels, add one or more 32-bit elements in array(elements
+      should be contiguous). The software will determine the mask value of
+      several elements corresponding to the same interrupt according to the
+      number of channels.
+
   "#dma-cells":
     type: int
     required: true
diff --git a/dts/bindings/dma/nxp,sdma.yaml b/dts/bindings/dma/nxp,sdma.yaml
index 817e9528a49..02e96914009 100644
--- a/dts/bindings/dma/nxp,sdma.yaml
+++ b/dts/bindings/dma/nxp,sdma.yaml
@@ -1,7 +1,7 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-description: NXP SDMA node
+description: NXP SDMA
 
 compatible: "nxp,sdma"
 
diff --git a/dts/bindings/dma/nxp,sof-host-dma.yaml b/dts/bindings/dma/nxp,sof-host-dma.yaml
index ebb03c46d8b..fb979a5f32b 100644
--- a/dts/bindings/dma/nxp,sof-host-dma.yaml
+++ b/dts/bindings/dma/nxp,sof-host-dma.yaml
@@ -1,7 +1,7 @@
 # Copyright 2023 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-description: NXP SOF host DMA node
+description: NXP SOF host DMA
 
 compatible: "nxp,sof-host-dma"
 
diff --git a/dts/bindings/dma/renesas,rz-dma.yaml b/dts/bindings/dma/renesas,rz-dma.yaml
new file mode 100644
index 00000000000..8934f2253d1
--- /dev/null
+++ b/dts/bindings/dma/renesas,rz-dma.yaml
@@ -0,0 +1,39 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  RZ DMA controller
+
+  channel: Select channel for data transmitting
+
+  config: A 32bit mask specifying the DMA channel configuration
+
+   Example of devicetree configuration
+
+   &ssi0 {
+        status = "okay";
+
+        dmas = <&dma0 0 RZ_DMA_PERIPH_TO_MEM>, <&dma0 5 RZ_DMA_MEM_TO_PERIPH>
+        dma-names = "rx", "tx";
+   };
+
+compatible: "renesas,rz-dma"
+
+include: [dma-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  dma-channels:
+    required: true
+
+  "#dma-cells":
+    const: 2
+
+dma-cells:
+  - channel
+  - config
diff --git a/dts/bindings/dma/silabs,ldma.yaml b/dts/bindings/dma/silabs,ldma.yaml
index b27f9ada0ef..606468e4a21 100644
--- a/dts/bindings/dma/silabs,ldma.yaml
+++ b/dts/bindings/dma/silabs,ldma.yaml
@@ -21,6 +21,12 @@ properties:
   interrupts:
     required: true
 
-  dma_channels:
+  dma-channels:
     type: int
     required: true
+
+  "#dma-cells":
+    const: 1
+
+dma-cells:
+  - slot
diff --git a/dts/bindings/dma/silabs,siwx91x-dma.yaml b/dts/bindings/dma/silabs,siwx91x-dma.yaml
new file mode 100644
index 00000000000..c6ff3b01da3
--- /dev/null
+++ b/dts/bindings/dma/silabs,siwx91x-dma.yaml
@@ -0,0 +1,24 @@
+description: Silabs SiWx91x DMA
+
+compatible: "silabs,siwx91x-dma"
+
+include: dma-controller.yaml
+
+properties:
+  reg:
+    required: true
+
+  silabs,sram-region:
+    type: phandle
+    description: |
+        SRAM Address for UDMA Descriptor Storage. Some instance require this
+        buffer to be placed in a specific area. If the instance doesn't have
+        this requirement, this attribute is not required and the memory will
+        will be automatically allocated.
+
+  "#dma-cells":
+    const: 1
+
+# Parameter syntax
+dma-cells:
+  - channel
diff --git a/dts/bindings/dma/snps,designware-dma-axi.yaml b/dts/bindings/dma/snps,designware-dma-axi.yaml
index baf27c45787..57f4c588c1d 100644
--- a/dts/bindings/dma/snps,designware-dma-axi.yaml
+++ b/dts/bindings/dma/snps,designware-dma-axi.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2023 Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Synopsys Designware axi DMA Controller node
+description: Synopsys Designware axi DMA Controller
 
 compatible: "snps,designware-dma-axi"
 
diff --git a/dts/bindings/dma/snps,designware-dma.yaml b/dts/bindings/dma/snps,designware-dma.yaml
index bcc85ffcc76..0f24c71327f 100644
--- a/dts/bindings/dma/snps,designware-dma.yaml
+++ b/dts/bindings/dma/snps,designware-dma.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2019 Intel Corporation. All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Synopsys Designware DMA Controller node
+description: Synopsys Designware DMA Controller
 
 compatible: "snps,designware-dma"
 
diff --git a/dts/bindings/dma/st,stm32-bdma.yaml b/dts/bindings/dma/st,stm32-bdma.yaml
index f8ae5bc68f5..0e6bf40c7f7 100644
--- a/dts/bindings/dma/st,stm32-bdma.yaml
+++ b/dts/bindings/dma/st,stm32-bdma.yaml
@@ -90,7 +90,7 @@ properties:
 
 # Parameter syntax of stm32 follows the dma client dts syntax
 # in the Linux kernel declared in
-# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dma.yaml
+# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/stm32/st,stm32-dma.yaml
 
 dma-cells:
   - channel
diff --git a/dts/bindings/dma/st,stm32-dma-v1.yaml b/dts/bindings/dma/st,stm32-dma-v1.yaml
index 22e1d862ea5..9d5c9b40a95 100644
--- a/dts/bindings/dma/st,stm32-dma-v1.yaml
+++ b/dts/bindings/dma/st,stm32-dma-v1.yaml
@@ -84,7 +84,7 @@ properties:
 
 # Parameter syntax of stm32 follows the dma client dts syntax
 # in the Linux kernel declared in
-# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dma.yaml
+# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/stm32/st,stm32-dma.yaml
 
 dma-cells:
   - channel
diff --git a/dts/bindings/dma/st,stm32-dma-v2.yaml b/dts/bindings/dma/st,stm32-dma-v2.yaml
index 632ff53a90b..ed753b8b3df 100644
--- a/dts/bindings/dma/st,stm32-dma-v2.yaml
+++ b/dts/bindings/dma/st,stm32-dma-v2.yaml
@@ -83,7 +83,7 @@ properties:
 
 # Parameter syntax of stm32 follows the dma client dts syntax
 # in the Linux kernel declared in
-# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dma.yaml
+# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/stm32/st,stm32-dma.yaml
 
 dma-cells:
   - channel
diff --git a/dts/bindings/dma/st,stm32-dma-v2bis.yaml b/dts/bindings/dma/st,stm32-dma-v2bis.yaml
index eeda4e94fb6..9245c918835 100644
--- a/dts/bindings/dma/st,stm32-dma-v2bis.yaml
+++ b/dts/bindings/dma/st,stm32-dma-v2bis.yaml
@@ -78,7 +78,7 @@ properties:
 
 # Parameter syntax of stm32 follows the dma client dts syntax
 # in the Linux kernel declared in
-# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dma.yaml
+# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/stm32/st,stm32-dma.yaml
 
 dma-cells:
   - channel
diff --git a/dts/bindings/dma/st,stm32-dmamux.yaml b/dts/bindings/dma/st,stm32-dmamux.yaml
index 8fa07a9c053..047f925f1e6 100644
--- a/dts/bindings/dma/st,stm32-dmamux.yaml
+++ b/dts/bindings/dma/st,stm32-dmamux.yaml
@@ -71,7 +71,7 @@ properties:
 
 # Parameter syntax of stm32 follows the dma client dts syntax
 # in the Linux kernel declared in
-# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/st,stm32-dmamux.yaml
+# https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/plain/Bindings/dma/stm32/st,stm32-dmamux.yaml
 
 dma-cells:
   - channel
diff --git a/dts/bindings/dma/st,stm32u5-dma.yaml b/dts/bindings/dma/st,stm32u5-dma.yaml
index 57b0ce0138e..b9d6f8a041d 100644
--- a/dts/bindings/dma/st,stm32u5-dma.yaml
+++ b/dts/bindings/dma/st,stm32u5-dma.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32 DMA controller for the stm32U5 soc family
+  STM32U5 DMA controller.
 
   It is present on stm32U5 devices as a GP DMA
   This controller includes several channels with different requests.
diff --git a/dts/bindings/dma/ti,cc23x0-dma.yaml b/dts/bindings/dma/ti,cc23x0-dma.yaml
new file mode 100644
index 00000000000..5c7ddb206b7
--- /dev/null
+++ b/dts/bindings/dma/ti,cc23x0-dma.yaml
@@ -0,0 +1,38 @@
+# Copyright (c) 2024 BayLibre, SAS
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI CC23X0 DMA controller
+
+compatible: "ti,cc23x0-dma"
+
+include: dma-controller.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  "#dma-cells":
+    const: 2
+    description: |
+      The 1st cell specifies the DMA channel to be used for the data transfer.
+      This channel should be unique between all peripherals that are using the
+      DMA instance.
+      The 2nd cell defines the peripheral trigger which is the source of the transfer.
+      See the SoC's reference manual for all the supported request sources.
+
+      Example of devicetree DMA channel configuration for the client part:
+
+      &uart0 {
+          dmas = <&dma 0 7>, <&dma 1 6>;
+          dma-names = "rx", "tx";
+      };
+
+      Above, fragment 0 and 1 represent the different channels used to transfer
+      data between peripheral and RAM. The numbers 7/6 are uart0 rx/tx triggers.
+
+dma-cells:
+  - channel
+  - trigsrc
diff --git a/dts/bindings/dma/wch,wch-dma.yaml b/dts/bindings/dma/wch,wch-dma.yaml
new file mode 100644
index 00000000000..157edfe01ea
--- /dev/null
+++ b/dts/bindings/dma/wch,wch-dma.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2024 Paul Wedeck <paulwedeck@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  WCH DMA controller
+
+  The WCH DMA controller is a general-purpose direct memory access controller
+  featuring between 7 and 11 independent channels.
+  Every channel is capable of memory-to-memory, memory-to-peripheral, and
+  peripheral-to-memory access.
+
+  Mapping of peripheral requests to DMA channels is limited and SoC specific.
+  Commonly, each peripheral request maps to just a single DMA channel.
+  The controller supports 8, 16, and 32 bit width memory access.
+
+  It is present on WCH CH32V and CH32X series SoCs.
+
+compatible: "wch,wch-dma"
+
+include: dma-controller.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  "#dma-cells":
+    const: 1
+
+dma-cells:
+  - channel
diff --git a/dts/bindings/dsa/dsa.yaml b/dts/bindings/dsa/dsa.yaml
new file mode 100644
index 00000000000..eca0b1d6d2c
--- /dev/null
+++ b/dts/bindings/dsa/dsa.yaml
@@ -0,0 +1,27 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: DSA Device
+
+child-binding:
+  description: Properties of slave port
+
+  include:
+    - name: pinctrl-device.yaml
+    - name: ethernet-controller.yaml
+      property-allowlist:
+        - zephyr,random-mac-address
+        - local-mac-address
+        - phy-handle
+        - phy-connection-type
+
+  properties:
+    reg:
+      type: array
+      required: true
+      description: Port number
+    ethernet:
+      type: phandle
+      description:
+        A phandle to a valid Ethernet device node. This host
+        device is what the switch port is connected to.
diff --git a/dts/bindings/dsa/microchip,ksz8463.yaml b/dts/bindings/dsa/microchip,ksz8463.yaml
new file mode 100644
index 00000000000..06df462ad4c
--- /dev/null
+++ b/dts/bindings/dsa/microchip,ksz8463.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2023 Aleksandr Senin <al@meshium.net>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    KSZ8463 ethernet switch
+
+compatible: "microchip,ksz8463"
+
+include: [microchip_dsa.yaml]
diff --git a/dts/bindings/dsa/nxp,netc-switch.yaml b/dts/bindings/dsa/nxp,netc-switch.yaml
new file mode 100644
index 00000000000..33842d60761
--- /dev/null
+++ b/dts/bindings/dsa/nxp,netc-switch.yaml
@@ -0,0 +1,8 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP NETC ethernet switch
+
+compatible: "nxp,netc-switch"
+
+include: [dsa.yaml]
diff --git a/dts/bindings/espi/microchip,xec-espi-saf.yaml b/dts/bindings/espi/microchip,xec-espi-saf.yaml
index 995052bbf69..e74ee0a29ed 100644
--- a/dts/bindings/espi/microchip,xec-espi-saf.yaml
+++ b/dts/bindings/espi/microchip,xec-espi-saf.yaml
@@ -13,26 +13,26 @@ properties:
     description: mmio register space
     required: true
 
-  io_girq:
+  io-girq:
     type: int
     description: soc group irq index for eSPI I/O
 
-  poll_timeout:
+  poll-timeout:
     type: int
     description: poll flash busy timeout in 32KHz periods
 
-  poll_interval:
+  poll-interval:
     type: int
     description: interval between flash busy poll in 20 ns units
 
-  consec_rd_timeout:
+  consec-rd-timeout:
     type: int
     description: timeout after last read to resume supended operations in 20 ns units
 
-  sus_chk_delay:
+  sus-chk-delay:
     type: int
     description: hold off poll after suspend in 20 ns units
 
-  sus_rsm_interval:
+  sus-rsm-interval:
     type: int
     description: force suspended erase or program to resume in 32KHz periods
diff --git a/dts/bindings/espi/microchip,xec-espi.yaml b/dts/bindings/espi/microchip,xec-espi.yaml
index b3fb2474a04..df03c6f1932 100644
--- a/dts/bindings/espi/microchip,xec-espi.yaml
+++ b/dts/bindings/espi/microchip,xec-espi.yaml
@@ -12,17 +12,17 @@ properties:
     description: mmio register space
     required: true
 
-  io_girq:
+  io-girq:
     type: int
     description: soc group irq index for eSPI I/O
     required: true
 
-  vw_girqs:
+  vw-girqs:
     type: array
     description: soc group irq indexes for eSPI virtual wires channel
     required: true
 
-  pc_girq:
+  pc-girq:
     type: int
     description: soc group irq index for eSPI peripheral channel
     required: true
diff --git a/dts/bindings/ethernet/davicom,dm8806-phy.yaml b/dts/bindings/ethernet/davicom,dm8806-phy.yaml
index 13fe82c1e93..c4196bfe334 100644
--- a/dts/bindings/ethernet/davicom,dm8806-phy.yaml
+++ b/dts/bindings/ethernet/davicom,dm8806-phy.yaml
@@ -29,6 +29,7 @@ properties:
       Absolute address is the address of the concrete register in MAC PHY0
       which is responsible for Ethernet Port0 in Davicom DM8806
   reg-switch:
+    type: int
     required: true
     description: |
       5-bit PHY address for Switch Per-Port Registers group of Davicom DM8806
@@ -48,9 +49,11 @@ properties:
       which is responsible for Ethernet Port0 in Davicom DM8806
   reset-gpios:
     type: phandle-array
+    required: true
     description: GPIO connected to MAC PHY reset signal pin. Reset is active low.
   int-gpios:
     type: phandle-array
+    required: true
     description: GPIO for   upt signal indicating MAC PHY state change.
   davicom,interface-type:
     type: string
diff --git a/dts/bindings/ethernet/ethernet-controller.yaml b/dts/bindings/ethernet/ethernet-controller.yaml
index bb4fa794152..ea19d106fe2 100644
--- a/dts/bindings/ethernet/ethernet-controller.yaml
+++ b/dts/bindings/ethernet/ethernet-controller.yaml
@@ -37,3 +37,4 @@ properties:
       - "rmii"
       - "gmii"
       - "rgmii"
+      - "internal"
diff --git a/dts/bindings/ethernet/microchip,lan865x.yaml b/dts/bindings/ethernet/microchip,lan865x.yaml
index 699bfca7dc6..b0852fd30a2 100644
--- a/dts/bindings/ethernet/microchip,lan865x.yaml
+++ b/dts/bindings/ethernet/microchip,lan865x.yaml
@@ -15,24 +15,6 @@ properties:
   rx-cut-through-mode:
     type: boolean
     description: Enable RX cut through mode
-  plca-enable:
-    type: boolean
-    description: Enable or disable PLCA support
-  plca-node-id:
-    type: int
-    description: Specify the PLCA node ID number
-  plca-node-count:
-    type: int
-    description: Specify the PLCA node count
-  plca-burst-count:
-    type: int
-    description: Specify the PLCA burst count
-  plca-burst-timer:
-    type: int
-    description: Specify the PLCA burst timer value
-  plca-to-timer:
-    type: int
-    description: Specify the PLCA to timer value
   int-gpios:
     type: phandle-array
     required: true
diff --git a/dts/bindings/ethernet/microchip,t1s-phy.yaml b/dts/bindings/ethernet/microchip,t1s-phy.yaml
new file mode 100644
index 00000000000..eba95092f10
--- /dev/null
+++ b/dts/bindings/ethernet/microchip,t1s-phy.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2024 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip's 10BASE-T1S PHYs support
+
+compatible: "microchip,t1s-phy"
+
+include: phy.yaml
+
+properties:
+  reg:
+    required: true
+    description: PHY address
+  plca-enable:
+    type: boolean
+    description: Enable or disable PLCA support
+  plca-node-id:
+    type: int
+    description: Specify the PLCA node ID number
+  plca-node-count:
+    type: int
+    description: Specify the PLCA node count
+  plca-burst-count:
+    type: int
+    description: Specify the PLCA burst count
+  plca-burst-timer:
+    type: int
+    description: Specify the PLCA burst timer value
+  plca-to-timer:
+    type: int
+    description: Specify the PLCA to timer value
diff --git a/dts/bindings/ethernet/microchip,vsc8541-phy.yaml b/dts/bindings/ethernet/microchip,vsc8541-phy.yaml
new file mode 100644
index 00000000000..b283884bd27
--- /dev/null
+++ b/dts/bindings/ethernet/microchip,vsc8541-phy.yaml
@@ -0,0 +1,30 @@
+# Copyright (c) 2024 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+description: Single Port Gigabit Ethernet Copper PHY with GMII/RGMII/MII/RMII Interfaces
+
+compatible: "microchip,vsc8541"
+
+include: [ethernet-phy.yaml]
+
+on-bus: mdio
+
+properties:
+  reg:
+    required: true
+    description: |
+      5-bit MDIO PHY address for the attached PHY.
+
+  reset-gpios:
+    type: phandle-array
+    description: GPIO connected to MAC PHY reset signal pin. Reset is active low.
+
+  microchip,interface-type:
+    type: string
+    required: true
+    description: Which type of phy connection the phy is set up for
+    enum:
+      - "mii"
+      - "rmii"
+      - "gmii"
+      - "rgmii"
diff --git a/dts/bindings/ethernet/nxp,imx-netc-psi.yaml b/dts/bindings/ethernet/nxp,imx-netc-psi.yaml
index 913df707d2b..7aba10df1e3 100644
--- a/dts/bindings/ethernet/nxp,imx-netc-psi.yaml
+++ b/dts/bindings/ethernet/nxp,imx-netc-psi.yaml
@@ -1,4 +1,4 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 description: NXP i.MX NETC Physical Station Interface (PSI)
@@ -11,9 +11,6 @@ properties:
   reg:
     required: true
 
-  phy-handle:
-    required: true
-
   mac-index:
     required: true
     type: int
diff --git a/dts/bindings/ethernet/sensry,sy1xx-mac.yaml b/dts/bindings/ethernet/sensry,sy1xx-mac.yaml
new file mode 100644
index 00000000000..412c405bcce
--- /dev/null
+++ b/dts/bindings/ethernet/sensry,sy1xx-mac.yaml
@@ -0,0 +1,28 @@
+# Copyright (c) 2024 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+compatible: "sensry,sy1xx-mac"
+
+include: [ethernet-controller.yaml, pinctrl-device.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  reg-names:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  phy-handle:
+    required: true
+
+  promiscuous-mode:
+    type: boolean
+    description: |
+      Optional feature flag - Enable promiscuous mode. When set, all valid
+      frames will be accepted.
diff --git a/dts/bindings/ethernet/silabs,gecko-ethernet.yaml b/dts/bindings/ethernet/silabs,gecko-ethernet.yaml
index 136e4cc6280..6a1328962d5 100644
--- a/dts/bindings/ethernet/silabs,gecko-ethernet.yaml
+++ b/dts/bindings/ethernet/silabs,gecko-ethernet.yaml
@@ -36,66 +36,66 @@ properties:
     description: location of MDC and MDIO pins, configuration defined as <location>
 
   # PHY management pins
-  location-phy_mdc:
+  location-phy-mdc:
     type: array
     required: true
     description: PHY MDC individual pin configuration defined as <location port pin>
 
-  location-phy_mdio:
+  location-phy-mdio:
     type: array
     required: true
     description: PHY MDIO individual pin configuration defined as <location port pin>
 
   # RMII interface pins
-  location-rmii_refclk:
+  location-rmii-refclk:
     type: array
     required: true
     description: Reference clock individual pin configuration defined as <location port pin>
 
-  location-rmii_crs_dv:
+  location-rmii-crs-dv:
     type: array
     required: true
     description: Receive data valid individual pin configuration defined as <location port pin>
 
-  location-rmii_txd0:
+  location-rmii-txd0:
     type: array
     required: true
     description: Transmit data 0 individual pin configuration defined as <location port pin>
 
-  location-rmii_txd1:
+  location-rmii-txd1:
     type: array
     required: true
     description: Transmit data 1 individual pin configuration defined as <location port pin>
 
-  location-rmii_tx_en:
+  location-rmii-tx-en:
     type: array
     required: true
     description: Transmit enable individual pin configuration defined as <location port pin>
 
-  location-rmii_rxd0:
+  location-rmii-rxd0:
     type: array
     required: true
     description: Receive data 0 individual pin configuration defined as <location port pin>
 
-  location-rmii_rxd1:
+  location-rmii-rxd1:
     type: array
     required: true
     description: Receive data 1 individual pin configuration defined as <location port pin>
 
-  location-rmii_rx_er:
+  location-rmii-rx-er:
     type: array
     required: true
     description: Receive error individual pin configuration defined as <location port pin>
 
   # PHY control pins
-  location-phy_pwr_enable:
+  location-phy-pwr-enable:
     type: array
     description: PHY power enable individual pin configuration defined as <port pin>
 
-  location-phy_reset:
+  location-phy-reset:
     type: array
     description: PHY reset individual pin configuration defined as <port pin>
 
-  location-phy_interrupt:
+  location-phy-interrupt:
     type: array
     description: PHY interrupt individual pin configuration defined as <port pin>
diff --git a/dts/bindings/ethernet/st,stm32-ethernet-common.yaml b/dts/bindings/ethernet/st,stm32-ethernet-common.yaml
index 4b3707d0610..2ebaae6a481 100644
--- a/dts/bindings/ethernet/st,stm32-ethernet-common.yaml
+++ b/dts/bindings/ethernet/st,stm32-ethernet-common.yaml
@@ -6,8 +6,6 @@
 include: [ethernet-controller.yaml, pinctrl-device.yaml]
 
 properties:
-  reg:
-    required: true
   interrupts:
     required: true
   clocks:
@@ -18,3 +16,7 @@ properties:
     required: true
   pinctrl-names:
     required: true
+  phy-connection-type:
+    required: true
+  phy-handle:
+    required: true
diff --git a/dts/bindings/ethernet/st,stm32-ethernet-controller.yaml b/dts/bindings/ethernet/st,stm32-ethernet-controller.yaml
new file mode 100644
index 00000000000..eedc3f2ada0
--- /dev/null
+++ b/dts/bindings/ethernet/st,stm32-ethernet-controller.yaml
@@ -0,0 +1,18 @@
+# Copyright The Zephyr Project Contributors
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  ST STM32 Ethernet controller, contains the Ethernet MAC
+  and the MDIO as a child nodes.
+
+compatible: "st,stm32-ethernet-controller"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+  clocks:
+    required: true
+  clock-names:
+    required: true
diff --git a/dts/bindings/ethernet/st,stm32-ethernet.yaml b/dts/bindings/ethernet/st,stm32-ethernet.yaml
index 67f211194dc..154729490ee 100644
--- a/dts/bindings/ethernet/st,stm32-ethernet.yaml
+++ b/dts/bindings/ethernet/st,stm32-ethernet.yaml
@@ -2,7 +2,8 @@
 # Copyright (c) 2024, STMicroelectronics
 # SPDX-License-Identifier: Apache-2.0
 
-description: ST STM32 Ethernet
+description: |
+  ST STM32 Ethernet MAC, a child node of the Ethernet controller.
 
 compatible: "st,stm32-ethernet"
 
diff --git a/dts/bindings/ethernet/st,stm32h7-ethernet.yaml b/dts/bindings/ethernet/st,stm32h7-ethernet.yaml
index 00f2addd21c..7878817c4fd 100644
--- a/dts/bindings/ethernet/st,stm32h7-ethernet.yaml
+++ b/dts/bindings/ethernet/st,stm32h7-ethernet.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  ST STM32H7 Ethernet
+  STM32H7 Ethernet
 
   This binding file describes the device tree properties required to configure
   and use the Ethernet controller on STM32H7 and STM32H5 series microcontrollers.
diff --git a/dts/bindings/ethernet/st,stm32n6-ethernet.yaml b/dts/bindings/ethernet/st,stm32n6-ethernet.yaml
new file mode 100644
index 00000000000..a423c4f324f
--- /dev/null
+++ b/dts/bindings/ethernet/st,stm32n6-ethernet.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2025, STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  ST STM32N6 Ethernet
+
+  This binding file describes the device tree properties required to configure
+  and use the Ethernet controller on STM32N6 series microcontrollers.
+
+compatible: "st,stm32n6-ethernet"
+
+include: st,stm32-ethernet-common.yaml
diff --git a/dts/bindings/ethernet/ti,dp83867.yaml b/dts/bindings/ethernet/ti,dp83867.yaml
new file mode 100644
index 00000000000..b08dfbb605f
--- /dev/null
+++ b/dts/bindings/ethernet/ti,dp83867.yaml
@@ -0,0 +1,16 @@
+# Copyright 2024, PHYTEC America, LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI DP83867 Ethernet PHY device
+
+compatible: "ti,dp83867"
+
+include: ethernet-phy.yaml
+
+properties:
+  reset-gpios:
+    type: phandle-array
+    description: GPIO connected to PHY reset signal pin. Reset is active low.
+  int-gpios:
+    type: phandle-array
+    description: GPIO for interrupt signal indicating PHY state change.
diff --git a/dts/bindings/ethernet/xlnx,axi-ethernet-1.00.a.yaml b/dts/bindings/ethernet/xlnx,axi-ethernet-1.00.a.yaml
new file mode 100644
index 00000000000..6e0670a8d58
--- /dev/null
+++ b/dts/bindings/ethernet/xlnx,axi-ethernet-1.00.a.yaml
@@ -0,0 +1,48 @@
+# Copyright (c) 2024 CISPA Helmholtz Center for Information Security
+# SPDX-License-Identifier: Apache-2.0
+
+description: Xilinx AXI 1G/2.5G Ethernet Subsystem base bindings.
+
+include: [ethernet-controller.yaml]
+
+compatible: "xlnx,axi-ethernet-1.00.a"
+
+properties:
+  interrupts:
+    description: Xilinx AXI Ethernet has an optional interrupt for updating statistics.
+
+  reg:
+    description:
+      Control registers of the MDIO device are also used for the Ethernet MAC controller.
+      Thus, both devices should have a parent node with compatible "xlnx,axi-ethernet-subsystem-7.2"
+      which defines the reg property, and MAC and MDIO should NOT have a reg property.
+
+  clock-frequency:
+    type: int
+
+  axistream-connected:
+    type: phandle
+    required: true
+    description: Xilinx AXI DMA that is connected to the data streams.
+
+  axistream-control-connected:
+    type: phandle
+    description:
+      Xilinx AXI DMA that is connected to the control streams.
+      Automatically generated by Xilinx' device tree generator.
+      Included in the schema to prevent spurious warnings for such autogenerated device trees.
+
+  xlnx,rxcsum:
+    type: int
+    default: 0
+    description: RX checksum offloading. 0 = none, 2 = full. 1 = partial is not supported.
+    enum:
+      - 0
+      - 2
+  xlnx,txcsum:
+    type: int
+    default: 0
+    description: TX checksum offloading. 0 = none, 2 = full. 1 = partial is not supported.
+    enum:
+      - 0
+      - 2
diff --git a/dts/bindings/firmware/arm,scmi-power.yaml b/dts/bindings/firmware/arm,scmi-power.yaml
new file mode 100644
index 00000000000..41ad234681d
--- /dev/null
+++ b/dts/bindings/firmware/arm,scmi-power.yaml
@@ -0,0 +1,21 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: System Control and Management Interface (SCMI) power domain protocol
+
+compatible: "arm,scmi-power"
+
+include: [base.yaml]
+
+properties:
+  reg:
+    required: true
+    const: [0x11]
+
+  "#power-domain-cells":
+    type: int
+    required: true
+    const: 1
+
+power-domain-cells:
+  - name
diff --git a/dts/bindings/firmware/nxp,scmi-cpu.yaml b/dts/bindings/firmware/nxp,scmi-cpu.yaml
new file mode 100644
index 00000000000..7032df08d98
--- /dev/null
+++ b/dts/bindings/firmware/nxp,scmi-cpu.yaml
@@ -0,0 +1,13 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: System Control and Management Interface (SCMI) cpu domain protocol
+
+compatible: "nxp,scmi-cpu"
+
+include: [base.yaml]
+
+properties:
+  reg:
+    required: true
+    const: [0x82]
diff --git a/dts/bindings/flash_controller/espressif,esp32-flash-controller.yaml b/dts/bindings/flash_controller/espressif,esp32-flash-controller.yaml
index c1bfa3bf696..0416405e0f7 100644
--- a/dts/bindings/flash_controller/espressif,esp32-flash-controller.yaml
+++ b/dts/bindings/flash_controller/espressif,esp32-flash-controller.yaml
@@ -1,4 +1,4 @@
-description: ESP32 Family flash controller
+description: ESP32 flash controller
 
 compatible: "espressif,esp32-flash-controller"
 
diff --git a/dts/bindings/flash_controller/nuvoton,npcx-fiu-nor.yaml b/dts/bindings/flash_controller/nuvoton,npcx-fiu-nor.yaml
index 86c8e57a362..48be99535c0 100644
--- a/dts/bindings/flash_controller/nuvoton,npcx-fiu-nor.yaml
+++ b/dts/bindings/flash_controller/nuvoton,npcx-fiu-nor.yaml
@@ -47,3 +47,17 @@ properties:
       - "NPCX_RD_MODE_NORMAL" # Direct read access by command code 03h
       - "NPCX_RD_MODE_FAST" # Direct read access by command code 0bh
       - "NPCX_RD_MODE_FAST_DUAL" # Direct read access by command code bbh
+  spi-dev-size:
+    type: string
+    description: |
+      Select the size of the address space allocated for SPI device. This affects
+      the address space for any direct flash access.
+    enum:
+      - "NPCX_SPI_DEV_SIZE_1M"
+      - "NPCX_SPI_DEV_SIZE_2M"
+      - "NPCX_SPI_DEV_SIZE_4M"
+      - "NPCX_SPI_DEV_SIZE_8M"
+      - "NPCX_SPI_DEV_SIZE_16M"
+      - "NPCX_SPI_DEV_SIZE_32M"
+      - "NPCX_SPI_DEV_SIZE_64M"
+      - "NPCX_SPI_DEV_SIZE_128M"
diff --git a/dts/bindings/flash_controller/nuvoton,npcx-fiu-qspi.yaml b/dts/bindings/flash_controller/nuvoton,npcx-fiu-qspi.yaml
index 3e8627faf23..23504268e1a 100644
--- a/dts/bindings/flash_controller/nuvoton,npcx-fiu-qspi.yaml
+++ b/dts/bindings/flash_controller/nuvoton,npcx-fiu-qspi.yaml
@@ -38,3 +38,7 @@ properties:
     type: boolean
     description: |
       Two external SPI devices are supported for Direct Read Access (DRA) on QSPI bus.
+  flash-dev-inv:
+    type: boolean
+    description: |
+      Inverse the device connected to the base address.
diff --git a/dts/bindings/flash_controller/silabs,series2-flash-controller.yaml b/dts/bindings/flash_controller/silabs,series2-flash-controller.yaml
new file mode 100644
index 00000000000..fa22525e481
--- /dev/null
+++ b/dts/bindings/flash_controller/silabs,series2-flash-controller.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2025 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Silicon Labs Series 2 flash controller
+
+compatible: "silabs,series2-flash-controller"
+
+include: flash-controller.yaml
+
+properties:
+  low-power-write:
+    type: boolean
+    description: |
+      Reduce current consumption during write, doubling write time
diff --git a/dts/bindings/flash_controller/silabs,siwx91x-flash-controller.yaml b/dts/bindings/flash_controller/silabs,siwx91x-flash-controller.yaml
new file mode 100644
index 00000000000..c12753253a0
--- /dev/null
+++ b/dts/bindings/flash_controller/silabs,siwx91x-flash-controller.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Silicon Labs SiWx91x flash controller
+
+compatible: "silabs,siwx91x-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/flash_controller/st,stm32f1-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32f1-flash-controller.yaml
index 1ba1208d90a..27bf78323ca 100644
--- a/dts/bindings/flash_controller/st,stm32f1-flash-controller.yaml
+++ b/dts/bindings/flash_controller/st,stm32f1-flash-controller.yaml
@@ -1,4 +1,4 @@
-description: STM32 F1 flash controller
+description: STM32F1 flash controller
 
 compatible: "st,stm32f1-flash-controller"
 
diff --git a/dts/bindings/flash_controller/st,stm32f2-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32f2-flash-controller.yaml
index 65ab19a0714..5e3f9cef4e9 100644
--- a/dts/bindings/flash_controller/st,stm32f2-flash-controller.yaml
+++ b/dts/bindings/flash_controller/st,stm32f2-flash-controller.yaml
@@ -1,4 +1,4 @@
-description: STM32 F2 flash controller
+description: STM32F2 flash controller
 
 compatible: "st,stm32f2-flash-controller"
 
diff --git a/dts/bindings/flash_controller/st,stm32f4-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32f4-flash-controller.yaml
index cea824302ab..c7ee38f5a66 100644
--- a/dts/bindings/flash_controller/st,stm32f4-flash-controller.yaml
+++ b/dts/bindings/flash_controller/st,stm32f4-flash-controller.yaml
@@ -1,4 +1,4 @@
-description: STM32 F4 flash controller
+description: STM32F4 flash controller
 
 compatible: "st,stm32f4-flash-controller"
 
diff --git a/dts/bindings/flash_controller/st,stm32f7-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32f7-flash-controller.yaml
index cdeaa308df8..e03bca31c98 100644
--- a/dts/bindings/flash_controller/st,stm32f7-flash-controller.yaml
+++ b/dts/bindings/flash_controller/st,stm32f7-flash-controller.yaml
@@ -1,4 +1,4 @@
-description: STM32 F7 flash controller
+description: STM32F7 flash controller
 
 compatible: "st,stm32f7-flash-controller"
 
diff --git a/dts/bindings/flash_controller/st,stm32g0-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32g0-flash-controller.yaml
index 226858e3e5b..40a32902f0c 100644
--- a/dts/bindings/flash_controller/st,stm32g0-flash-controller.yaml
+++ b/dts/bindings/flash_controller/st,stm32g0-flash-controller.yaml
@@ -1,4 +1,4 @@
-description: STM32 G0 flash controller
+description: STM32G0 flash controller
 
 compatible: "st,stm32g0-flash-controller"
 
diff --git a/dts/bindings/flash_controller/st,stm32g4-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32g4-flash-controller.yaml
index 71df716072e..e3debe1f720 100644
--- a/dts/bindings/flash_controller/st,stm32g4-flash-controller.yaml
+++ b/dts/bindings/flash_controller/st,stm32g4-flash-controller.yaml
@@ -1,4 +1,4 @@
-description: STM32 G4 flash controller
+description: STM32G4 flash controller
 
 compatible: "st,stm32g4-flash-controller"
 
diff --git a/dts/bindings/flash_controller/st,stm32h7-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32h7-flash-controller.yaml
index 305107cc1ca..fff76143d1b 100644
--- a/dts/bindings/flash_controller/st,stm32h7-flash-controller.yaml
+++ b/dts/bindings/flash_controller/st,stm32h7-flash-controller.yaml
@@ -1,4 +1,4 @@
-description: STM32 H7 flash controller
+description: STM32H7 flash controller
 
 compatible: "st,stm32h7-flash-controller"
 
diff --git a/dts/bindings/flash_controller/st,stm32l4-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32l4-flash-controller.yaml
index 17e3e76fbaf..cb5f50b1ad8 100644
--- a/dts/bindings/flash_controller/st,stm32l4-flash-controller.yaml
+++ b/dts/bindings/flash_controller/st,stm32l4-flash-controller.yaml
@@ -1,4 +1,4 @@
-description: STM32 L4 flash controller
+description: STM32L4 flash controller
 
 compatible: "st,stm32l4-flash-controller"
 
diff --git a/dts/bindings/flash_controller/st,stm32l5-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32l5-flash-controller.yaml
index 0f6edba9d92..bfb7938ab78 100644
--- a/dts/bindings/flash_controller/st,stm32l5-flash-controller.yaml
+++ b/dts/bindings/flash_controller/st,stm32l5-flash-controller.yaml
@@ -1,4 +1,4 @@
-description: STM32 L5 flash controller
+description: STM32L5 flash controller
 
 compatible: "st,stm32l5-flash-controller"
 
diff --git a/dts/bindings/flash_controller/st,stm32wb-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32wb-flash-controller.yaml
index 3234a34d861..d72cd171e92 100644
--- a/dts/bindings/flash_controller/st,stm32wb-flash-controller.yaml
+++ b/dts/bindings/flash_controller/st,stm32wb-flash-controller.yaml
@@ -1,4 +1,4 @@
-description: STM32 WB flash controller
+description: STM32WB flash controller
 
 compatible: "st,stm32wb-flash-controller"
 
diff --git a/dts/bindings/flash_controller/st,stm32wba-flash-controller.yaml b/dts/bindings/flash_controller/st,stm32wba-flash-controller.yaml
index 5ef97c10ece..9b34765d65d 100644
--- a/dts/bindings/flash_controller/st,stm32wba-flash-controller.yaml
+++ b/dts/bindings/flash_controller/st,stm32wba-flash-controller.yaml
@@ -1,4 +1,4 @@
-description: STM32 WBA flash controller
+description: STM32WBA flash controller
 
 compatible: "st,stm32wba-flash-controller"
 
diff --git a/dts/bindings/flash_controller/ti,cc23x0-flash-controller.yaml b/dts/bindings/flash_controller/ti,cc23x0-flash-controller.yaml
new file mode 100644
index 00000000000..538e75aa16d
--- /dev/null
+++ b/dts/bindings/flash_controller/ti,cc23x0-flash-controller.yaml
@@ -0,0 +1,5 @@
+description: Texas Instruments CC23X0 flash controller
+
+compatible: "ti,cc23x0-flash-controller"
+
+include: flash-controller.yaml
diff --git a/dts/bindings/fs/zephyr,fstab,fatfs.yaml b/dts/bindings/fs/zephyr,fstab,fatfs.yaml
new file mode 100644
index 00000000000..ba11faef956
--- /dev/null
+++ b/dts/bindings/fs/zephyr,fstab,fatfs.yaml
@@ -0,0 +1,9 @@
+# Copyright (C) 2025 Endress+Hauser AG
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Description of pre-defined fatfs file systems.
+
+compatible: "zephyr,fstab,fatfs"
+
+include: zephyr,fstab-common.yaml
diff --git a/dts/bindings/fs/zephyr,fstab,littlefs.yaml b/dts/bindings/fs/zephyr,fstab,littlefs.yaml
index 92e667712b1..8703c512e33 100644
--- a/dts/bindings/fs/zephyr,fstab,littlefs.yaml
+++ b/dts/bindings/fs/zephyr,fstab,littlefs.yaml
@@ -11,6 +11,12 @@ include: "zephyr,fstab-common.yaml"
 properties:
   # num-files and num-dirs are not filesystem-specific.
 
+  partition:
+    type: phandle
+    required: true
+    description: |
+      A reference to the file system's partition.
+
   read-size:
     type: int
     required: true
diff --git a/dts/bindings/fs/zephyr,fstab-common.yaml b/dts/bindings/fs/zephyr,fstab-common.yaml
index e7e9fa3fe9a..054098e7c00 100644
--- a/dts/bindings/fs/zephyr,fstab-common.yaml
+++ b/dts/bindings/fs/zephyr,fstab-common.yaml
@@ -12,12 +12,6 @@ properties:
     description: |
       The absolute path used as the file system mount point.
 
-  partition:
-    type: phandle
-    required: true
-    description: |
-      A reference to the file system's partition.
-
   automount:
     type: boolean
     description: |
diff --git a/dts/bindings/gpio/adi,max14915-gpio.yaml b/dts/bindings/gpio/adi,max14915-gpio.yaml
new file mode 100644
index 00000000000..a2d4b421eb3
--- /dev/null
+++ b/dts/bindings/gpio/adi,max14915-gpio.yaml
@@ -0,0 +1,64 @@
+# Copyright (c) 2025 Analog Devices Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  ADI MAX14915 compact industrial octal high-side switch with
+  diagnostics
+
+  https://www.analog.com/media/en/technical-documentation/data-sheets/MAX14915.pdf
+
+  Example:
+
+  max14915: max14915@0 {
+      compatible = "adi,max14915-gpio";
+      status = "okay";
+      reg = <0x00>;
+      fault-gpios = <&gpiof 13 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+      sync-gpios = <&gpioc 7 GPIO_ACTIVE_LOW>;
+      en-gpios = <&gpiob 5 GPIO_ACTIVE_LOW>;
+      drdy-gpios = <&gpioa 15 GPIO_ACTIVE_LOW>;
+      spi-max-frequency = <10000000>;
+      gpio-controller;
+      #gpio-cells = <2>;
+      ngpios = <8>;
+      crc-en;
+      spi-addr = <0>;
+      ow-on-en = <0 0 0 0 0 0 0 0>;
+      ow-off-en = <0 0 0 0 0 0 0 0>;
+      sh-vdd-en = <0 0 0 0 0 0 0 0>;
+      /* Config Reg 1 */
+      fled-set;
+      sled-set;
+      fled-stretch = <3>;
+      ffilter-en;
+      filter-long;
+      flatch-en;
+      led-cur-lim;
+      /* Config Reg 2 */
+      vdd-on-thr;
+      synch-wd-en;
+      sht-vdd-thr = <3>;
+      ow-off-cs = <3>;
+      wd-to = <0>;
+    };
+
+compatible: "adi,max14915-gpio"
+
+properties:
+  wd-to:
+    type: int
+    default: 0
+    enum:
+      - 0
+      - 1
+      - 2
+      - 3
+    description: |
+      Default value according to documentation.
+      Set SPI and SYNCH Watchdog Timeout
+      0: Disable SPI Watchdog and set SYNCH Watchdog Timeout to 600ms (typ)
+      1: Set SPI and SYNCH Watchdog Timeout to 200ms (typ)
+      2: Set SPI and SYNCH Watchdog Timeout to 600ms (typ)
+      3: Set SPI and SYNCH Watchdog Timeout to 1.2s (typ)
+
+include: adi,max14916-gpio.yaml
diff --git a/dts/bindings/gpio/adi,max14917-gpio.yaml b/dts/bindings/gpio/adi,max14917-gpio.yaml
new file mode 100644
index 00000000000..d94b486e7c7
--- /dev/null
+++ b/dts/bindings/gpio/adi,max14917-gpio.yaml
@@ -0,0 +1,59 @@
+# Copyright (c) 2025 Analog Devices Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ADI  MAX14917 is octal industrial output
+
+compatible: "adi,max14917-gpio"
+
+properties:
+  "#gpio-cells":
+    const: 2
+  ngpios:
+    type: int
+    required: true
+    const: 8
+    description: Number of gpios supported
+  vddok-gpios:
+    description: |
+      High-Side Open-Drain Output. VDDOK is passive low when the internal
+      logic supply is higher than the UVLO threshold, indicating that the
+      registers have adequate supply voltage.
+    type: phandle-array
+  ready-gpios:
+    description: |
+      Ready pin indicates when the device is ready to be used.
+    type: phandle-array
+  comerr-gpios:
+    description: |
+      Communication Error pin indicates when there is a communication error
+      on the SPI bus.
+    type: phandle-array
+  fault-gpios:
+    description: |
+      Fault pin indicates cases of overload or undervoltage conditions
+    type: phandle-array
+  en-gpios:
+    description: |
+      Enable Pin. Drive the EN pin high to enable the outputs.
+      Drive EN low to disable/three-state all outputs.
+    type: phandle-array
+  sync-gpios:
+    description: |
+      All eight output switches are updated simultaneously on the rising edge
+      of SYNCH, as determined by the content of the SPI command
+    type: phandle-array
+  crcen-gpios:
+    description: |
+      Drive CRCEN high to enable CRC generation and error detection on the
+      serial data.
+    type: phandle-array
+  crc-en:
+    description: |
+      Notify driver if crc pin is enabled.
+    type: boolean
+
+gpio-cells:
+  - pin
+  - flags
+
+include: [gpio-controller.yaml, spi-device.yaml]
diff --git a/dts/bindings/gpio/adi,max22017-gpio.yaml b/dts/bindings/gpio/adi,max22017-gpio.yaml
new file mode 100644
index 00000000000..81a243ea7af
--- /dev/null
+++ b/dts/bindings/gpio/adi,max22017-gpio.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2024 Analog Devices Inc.
+# Copyright (c) 2024 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+description: MAX22017 GPIO
+
+compatible: "adi,max22017-gpio"
+
+include: gpio-controller.yaml
+
+properties:
+  "#gpio-cells":
+    const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/adi,max22190-gpio.yaml b/dts/bindings/gpio/adi,max22190-gpio.yaml
index 29e263fbd92..4739b30e325 100644
--- a/dts/bindings/gpio/adi,max22190-gpio.yaml
+++ b/dts/bindings/gpio/adi,max22190-gpio.yaml
@@ -41,44 +41,6 @@ description: |
 compatible: "adi,max22190-gpio"
 
 properties:
-  "#gpio-cells":
-    const: 2
-  ngpios:
-    type: int
-    required: true
-    const: 8
-    description: Number of gpios supported
-  drdy-gpios:
-    description: Ready pin which show when chip is ready
-    type: phandle-array
-  fault-gpios:
-    description: |
-      Fault pin indicates when there is Fault state in either FAULT1 or FAULT2
-      bothe of which are cleaned on read once problem is not persistent
-    type: phandle-array
-  latch-gpios:
-    description: |
-      Latch the data so it could be read (partially duplicate CS)
-    type: phandle-array
-  max22190-mode:
-    type: int
-    required: true
-    enum:
-      - 0
-      - 1
-      - 2
-      - 3
-    description: |
-      Default mode set to 1, because in MAX22190PMB devkit this is hardwired
-      mode set by manufacturer.
-      max22190 mode is configured from M0 and M1 pins with
-      pull up or down resistors.
-      MODE| M1| M0| FRAME  | CRC | DAISY CHAIN
-      ----+---+---+--------+-----+------------
-        0 | 0 | 0 | 24-bit | yes | no
-        1 | 0 | 1 | 16-bit | no  | no
-        2 | 1 | 0 | 24-bit | yes | yes
-        3 | 1 | 1 | 16-bit | no  | yes
   filter-wbes:
     type: array
     default: [0, 0, 0, 0, 0, 0, 0, 0]
@@ -92,27 +54,9 @@ properties:
       - 1 wire break enable
       - 0 wire break disable
       channels indentation start from CH0...CH7
-  filter-fbps:
-    type: array
-    default: [1, 1, 1, 1, 1, 1, 1, 1]
-    description: |
-      The default value corresponds to the default value of the hardware.
-      All channels are in bypass.
-      Enable or disable filter
-      - 1 mean bypass
-      - 0 mean filter is used
-      channels indentation start from CH0...CH7
-  filter-delays:
-    type: array
-    default: [50, 50, 50, 50, 50, 50, 50, 50]
-    description: |
-      The default value corresponds to the default value of the hardware.
-      Used to setup filter delay. Values are set in us. Default value is 50 = 50 us.
-      Value : 50, 100, 400, 800, 1600, 3200, 12800, 20000
-      channels indentation start from CH0...CH7
 
 gpio-cells:
   - pin
   - flags
 
-include: [gpio-controller.yaml, spi-device.yaml]
+include: adi,max2219x-base-gpio.yaml
diff --git a/dts/bindings/gpio/adi,max22199-gpio.yaml b/dts/bindings/gpio/adi,max22199-gpio.yaml
new file mode 100644
index 00000000000..6f6403ac05e
--- /dev/null
+++ b/dts/bindings/gpio/adi,max22199-gpio.yaml
@@ -0,0 +1,47 @@
+# Copyright (c) 2024 Analog Devices Inc.
+# Copyright (c) 2024 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  The MAX22199 is an IEC 61131-2 compliant industrial digital input device.
+  The MAX22199 translates eight 24V current-sinking industrial inputs to a
+  serialized SPI-compatible output that interfaces with 3V to 5.5V logic.
+  It can operate as eight Type 1/Type 3 digital inputs or four Type 2 digital
+  inputs. The device provides diagnostic functions, including thermal shutdown,
+  24V under voltage alarm, 24V missing voltage alarm, and SPI and CRC
+  communication error detection.
+
+  Sample binding
+  &sdp_spi {
+    status = "okay";
+    pinctrl-names = "default";
+    max22199_gpio0: max22199_gpio@0 {
+      compatible = "adi,max22199-gpio";
+      reg = <0>;
+
+      spi-max-frequency = <1000000>;
+      status = "okay";
+
+      gpio-controller;
+      #gpio-cells = <2>;
+      ngpios = <8>;
+      status = "okay";
+
+      max22199-mode = <1>; // modes range from 0-4
+
+      drdy-gpios = <&gpioj 12 GPIO_ACTIVE_LOW>; /* SDP-GPIO5 - PMOD-PIN8 */
+      fault-gpios = <&gpioc 11 GPIO_ACTIVE_LOW>; /* SDP-SERIAL_INT - PMOD-PIN7 */
+      latch-gpios = <&gpioj 13 GPIO_ACTIVE_LOW>; /* SDP-GPIO6 - PMOD-PIN9 */
+
+      filter-fbps = <0 0 0 0  0 0 0 0>; // programmable filter INx
+      filter-delays = <50 100 400 800 1600 3200 12800 20000>; // 1000 us == 1ms
+    };
+  };
+
+compatible: "adi,max22199-gpio"
+
+gpio-cells:
+  - pin
+  - flags
+
+include: adi,max2219x-base-gpio.yaml
diff --git a/dts/bindings/gpio/adi,max2219x-base-gpio.yaml b/dts/bindings/gpio/adi,max2219x-base-gpio.yaml
new file mode 100644
index 00000000000..41354456e2c
--- /dev/null
+++ b/dts/bindings/gpio/adi,max2219x-base-gpio.yaml
@@ -0,0 +1,76 @@
+# Copyright (c) 2024 Analog Devices Inc.
+# Copyright (c) 2024 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+include: [gpio-controller.yaml, spi-device.yaml]
+
+properties:
+  "#gpio-cells":
+    const: 2
+  ngpios:
+    type: int
+    required: true
+    const: 8
+    description: Number of gpios supported
+  drdy-gpios:
+    description: Ready pin which show when chip is ready
+    type: phandle-array
+  fault-gpios:
+    description: |
+      Fault pin indicates when there is Fault state in either FAULT1 or FAULT2
+      bothe of which are cleaned on read once problem is not persistent
+    type: phandle-array
+  latch-gpios:
+    description: |
+      Latch the data so it could be read (partially duplicate CS)
+    type: phandle-array
+  max22190-mode:
+    type: int
+    required: true
+    enum:
+      - 0
+      - 1
+      - 2
+      - 3
+    description: |
+      Default mode set to 1, because in MAX22190PMB devkit this is hardwired
+      mode set by manufacturer.
+      max22190 mode is configured from M0 and M1 pins with
+      pull up or down resistors.
+      MODE| M1| M0| FRAME  | CRC | DAISY CHAIN
+      ----+---+---+--------+-----+------------
+        0 | 0 | 0 | 24-bit | yes | no
+        1 | 0 | 1 | 16-bit | no  | no
+        2 | 1 | 0 | 24-bit | yes | yes
+        3 | 1 | 1 | 16-bit | no  | yes
+  filter-wbes:
+    type: array
+    default: [0, 0, 0, 0, 0, 0, 0, 0]
+    description: |
+      The default value corresponds to the default value of the hardware.
+      Wire break is disabled in all channels.
+      WBE bit in all Filter registers stand for wire break enable on each
+      channel, so to enable WB functionality set 1.
+      If WB on specific channel is disabled , FAULT will not be rised in case
+      wire is cut.
+      - 1 wire break enable
+      - 0 wire break disable
+      channels indentation start from CH0...CH7
+  filter-fbps:
+    type: array
+    default: [1, 1, 1, 1, 1, 1, 1, 1]
+    description: |
+      The default value corresponds to the default value of the hardware.
+      All channels are in bypass.
+      Enable or disable filter
+      - 1 mean bypass
+      - 0 mean filter is used
+      channels indentation start from CH0...CH7
+  filter-delays:
+    type: array
+    default: [50, 50, 50, 50, 50, 50, 50, 50]
+    description: |
+      The default value corresponds to the default value of the hardware.
+      Used to setup filter delay. Values are set in us. Default value is 50 = 50 us.
+      Value : 50, 100, 400, 800, 1600, 3200, 12800, 20000
+      channels indentation start from CH0...CH7
diff --git a/dts/bindings/gpio/altr,pio-1.0.yaml b/dts/bindings/gpio/altr,pio-1.0.yaml
index d9711130e7c..b272ce80b7c 100644
--- a/dts/bindings/gpio/altr,pio-1.0.yaml
+++ b/dts/bindings/gpio/altr,pio-1.0.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2023 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-description: Altera PIO node
+description: Altera PIO
 
 compatible: "altr,pio-1.0"
 
diff --git a/dts/bindings/gpio/ambiq,gpio-bank.yaml b/dts/bindings/gpio/ambiq,gpio-bank.yaml
index 8d9114acc5b..4cdcb5b8551 100644
--- a/dts/bindings/gpio/ambiq,gpio-bank.yaml
+++ b/dts/bindings/gpio/ambiq,gpio-bank.yaml
@@ -2,7 +2,7 @@
 # Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
 # SPDX-License-Identifier: Apache-2.0
 
-description: Ambiq GPIO bank node
+description: Ambiq GPIO bank
 
 compatible: "ambiq,gpio-bank"
 
diff --git a/dts/bindings/gpio/andestech,atcgpio100.yaml b/dts/bindings/gpio/andestech,atcgpio100.yaml
index 88a7d990a39..22d289069fd 100644
--- a/dts/bindings/gpio/andestech,atcgpio100.yaml
+++ b/dts/bindings/gpio/andestech,atcgpio100.yaml
@@ -1,8 +1,7 @@
 # Copyright (c) 2021, Andes Technology Corporation.
 # SPDX-License-Identifier: Apache-2.0
 
-description:
-  This is a representation of Andes Technology atcgpio100 GPIO node
+description: Andes Technology ATCGPIO100 GPIO Controller.
 
 compatible: "andestech,atcgpio100"
 
diff --git a/dts/bindings/gpio/arduino-mkr-header.yaml b/dts/bindings/gpio/arduino-mkr-header.yaml
index 2b3c15bbe8f..03fb39d053c 100644
--- a/dts/bindings/gpio/arduino-mkr-header.yaml
+++ b/dts/bindings/gpio/arduino-mkr-header.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    GPIO pins exposing on Arduino MKR headers.
+    GPIO pins exposed on Arduino MKR headers.
 
     The Arduino MKR layout provides two headers on both edges of the board.
 
diff --git a/dts/bindings/gpio/arm,mmio32-gpio.yaml b/dts/bindings/gpio/arm,mmio32-gpio.yaml
new file mode 100644
index 00000000000..0a8692adef4
--- /dev/null
+++ b/dts/bindings/gpio/arm,mmio32-gpio.yaml
@@ -0,0 +1,22 @@
+description: ARM MMIO32 GPIO
+
+compatible: "arm,mmio32-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  ngpios:
+    required: true
+
+  "#gpio-cells":
+    const: 1
+
+  direction-input:
+    type: boolean
+    description: Marks this pin set as all input pins.
+
+gpio-cells:
+  - pin
diff --git a/dts/bindings/gpio/arm,mps2-fpgaio-gpio.yaml b/dts/bindings/gpio/arm,mps2-fpgaio-gpio.yaml
deleted file mode 100644
index 1c91ef9ca2a..00000000000
--- a/dts/bindings/gpio/arm,mps2-fpgaio-gpio.yaml
+++ /dev/null
@@ -1,18 +0,0 @@
-description: GPIO controller on ARM MPS2 FPGA
-
-compatible: "arm,mps2-fpgaio-gpio"
-
-include: [gpio-controller.yaml, base.yaml]
-
-properties:
-  reg:
-    required: true
-
-  ngpios:
-    required: true
-
-  "#gpio-cells":
-    const: 1
-
-gpio-cells:
-  - pin
diff --git a/dts/bindings/gpio/arm,mps3-fpgaio-gpio.yaml b/dts/bindings/gpio/arm,mps3-fpgaio-gpio.yaml
deleted file mode 100644
index 8d93742f9ed..00000000000
--- a/dts/bindings/gpio/arm,mps3-fpgaio-gpio.yaml
+++ /dev/null
@@ -1,18 +0,0 @@
-description: GPIO controller on ARM MPS3 FPGA
-
-compatible: "arm,mps3-fpgaio-gpio"
-
-include: [gpio-controller.yaml, base.yaml]
-
-properties:
-  reg:
-    required: true
-
-  ngpios:
-    required: true
-
-  "#gpio-cells":
-    const: 1
-
-gpio-cells:
-  - pin
diff --git a/dts/bindings/gpio/atmel,sam-gpio.yaml b/dts/bindings/gpio/atmel,sam-gpio.yaml
index b212915086e..694c4c03cc0 100644
--- a/dts/bindings/gpio/atmel,sam-gpio.yaml
+++ b/dts/bindings/gpio/atmel,sam-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021-2023, Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
-description: SAM GPIO PORT node
+description: SAM GPIO Port
 
 compatible: "atmel,sam-gpio"
 
diff --git a/dts/bindings/gpio/atmel,sam4l-gpio.yaml b/dts/bindings/gpio/atmel,sam4l-gpio.yaml
index 9b7d03883ff..2868ea220cf 100644
--- a/dts/bindings/gpio/atmel,sam4l-gpio.yaml
+++ b/dts/bindings/gpio/atmel,sam4l-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021-2023, Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
-description: SAM4L GPIO PORT node
+description: SAM4L GPIO Port
 
 compatible: "atmel,sam4l-gpio"
 
diff --git a/dts/bindings/gpio/bflb,gpio.yaml b/dts/bindings/gpio/bflb,gpio.yaml
new file mode 100644
index 00000000000..8692999ddc7
--- /dev/null
+++ b/dts/bindings/gpio/bflb,gpio.yaml
@@ -0,0 +1,35 @@
+# Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+description: Bouffalo Lab GPIO node
+
+compatible: "bflb,gpio"
+
+include:
+  - name: base.yaml
+  - name: gpio-controller.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  "#gpio-cells":
+    const: 2
+
+  "#bflb,pin-cells":
+    type: int
+    required: true
+    const: 2
+    description: Number of items to expect in a bflb,pins specifier
+
+gpio-cells:
+  - pin
+  - flags
+
+bflb,pin-cells:
+  - pin
+  - peripheral
diff --git a/dts/bindings/gpio/cypress,cy8c95xx-gpio-port.yaml b/dts/bindings/gpio/cypress,cy8c95xx-gpio-port.yaml
index 544621f74e4..0ea3a6d7adf 100644
--- a/dts/bindings/gpio/cypress,cy8c95xx-gpio-port.yaml
+++ b/dts/bindings/gpio/cypress,cy8c95xx-gpio-port.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021 Synopsys
 # SPDX-License-Identifier: Apache-2.0
 
-description: Cypress cy8c95xx GPIO port node
+description: Cypress cy8c95xx GPIO Port
 
 compatible: "cypress,cy8c95xx-gpio-port"
 
diff --git a/dts/bindings/gpio/cypress,cy8c95xx-gpio.yaml b/dts/bindings/gpio/cypress,cy8c95xx-gpio.yaml
index 1f97f9a141f..6634e866603 100644
--- a/dts/bindings/gpio/cypress,cy8c95xx-gpio.yaml
+++ b/dts/bindings/gpio/cypress,cy8c95xx-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021 Synopsys
 # SPDX-License-Identifier: Apache-2.0
 
-description: Cypress cy8c95xx GPIO node
+description: Cypress cy8c95xx GPIO
 
 compatible: "cypress,cy8c95xx-gpio"
 
diff --git a/dts/bindings/gpio/cypress,psoc6-gpio.yaml b/dts/bindings/gpio/cypress,psoc6-gpio.yaml
index ac16d9341a3..1c8ff76ce84 100644
--- a/dts/bindings/gpio/cypress,psoc6-gpio.yaml
+++ b/dts/bindings/gpio/cypress,psoc6-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2020-2021 ATL Electronics
 # SPDX-License-Identifier: Apache-2.0
 
-description: Cypress GPIO PORT node
+description: Cypress GPIO Port
 
 compatible: "cypress,psoc6-gpio"
 
diff --git a/dts/bindings/gpio/ene,kb1200-gpio.yaml b/dts/bindings/gpio/ene,kb1200-gpio.yaml
index a87d33138db..95f7dd66681 100644
--- a/dts/bindings/gpio/ene,kb1200-gpio.yaml
+++ b/dts/bindings/gpio/ene,kb1200-gpio.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    ENE KB1200 GPIO(General purpose IO) Port node
+    ENE KB1200 GPIO Port
 
     The GPIO controller provides group control of GPIO functions. Each port
     group contains 32 pins. GPIO_00~GPIO_1F belong to the Port0 group,
diff --git a/dts/bindings/gpio/gd,gd32-gpio.yaml b/dts/bindings/gpio/gd,gd32-gpio.yaml
index c2b8c918204..9705ee34c40 100644
--- a/dts/bindings/gpio/gd,gd32-gpio.yaml
+++ b/dts/bindings/gpio/gd,gd32-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021 Teslabs Engineering S.L.
 # SPDX-License-Identifier: Apache-2.0
 
-description: GD32 GPIO node
+description: GD32 GPIO
 
 compatible: "gd,gd32-gpio"
 
diff --git a/dts/bindings/gpio/grove-header.yaml b/dts/bindings/gpio/grove-header.yaml
index eaaec78baff..f4cb051442c 100644
--- a/dts/bindings/gpio/grove-header.yaml
+++ b/dts/bindings/gpio/grove-header.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    GPIO pins exposing on Grove 4 pins headers.
+    GPIO pins exposed on Grove 4 pins headers.
 
     This binding provides a nexus mapping for 2 pins as depicted below.
 
diff --git a/dts/bindings/gpio/infineon,cat1-gpio.yaml b/dts/bindings/gpio/infineon,cat1-gpio.yaml
index 3bcfe65473d..54c4777315c 100644
--- a/dts/bindings/gpio/infineon,cat1-gpio.yaml
+++ b/dts/bindings/gpio/infineon,cat1-gpio.yaml
@@ -4,7 +4,7 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-description: Infineon CAT1 GPIO PORT node
+description: Infineon CAT1 GPIO Port
 
 compatible: "infineon,cat1-gpio"
 
diff --git a/dts/bindings/gpio/infineon,xmc4xxx-gpio.yaml b/dts/bindings/gpio/infineon,xmc4xxx-gpio.yaml
index a6b28c3af89..2001dffb7ad 100644
--- a/dts/bindings/gpio/infineon,xmc4xxx-gpio.yaml
+++ b/dts/bindings/gpio/infineon,xmc4xxx-gpio.yaml
@@ -1,4 +1,4 @@
-description: INFINEON XMC4XXX GPIO PORT node
+description: INFINEON XMC4XXX GPIO Port
 
 compatible: "infineon,xmc4xxx-gpio"
 
diff --git a/dts/bindings/gpio/intel,gpio.yaml b/dts/bindings/gpio/intel,gpio.yaml
index f8c434cd0d2..c9c843ef519 100644
--- a/dts/bindings/gpio/intel,gpio.yaml
+++ b/dts/bindings/gpio/intel,gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2018-2019 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-description: Intel GPIO node
+description: Intel GPIO
 
 compatible: "intel,gpio"
 
diff --git a/dts/bindings/gpio/ite,it51xxx-gpio.yaml b/dts/bindings/gpio/ite,it51xxx-gpio.yaml
new file mode 100644
index 00000000000..c95941cb6bd
--- /dev/null
+++ b/dts/bindings/gpio/ite,it51xxx-gpio.yaml
@@ -0,0 +1,28 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: This binding gives a base representation of the it51xxx series gpio
+
+compatible: "ite,it51xxx-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  has-volt-sel:
+    type: array
+    description: |
+      Selection of support input voltage 3.3V or 1.8V.
+
+  wucctrl:
+    type: phandles
+    description: |
+      WUC groups internal and external inputs, and asserts wake-up
+      signals to INTC that allows the CPU to exit a Doze/Deep
+      Doze/Sleep mode.
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/ite,it8801-gpio.yaml b/dts/bindings/gpio/ite,it8801-gpio.yaml
index 2e78fa9917a..56f29eab3a6 100644
--- a/dts/bindings/gpio/ite,it8801-gpio.yaml
+++ b/dts/bindings/gpio/ite,it8801-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 ITE Corporation. All Rights Reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-description: ITE IT8801 I2C-based GPIO device driver
+description: ITE IT8801 I2C-based GPIO
 
 compatible: "ite,it8801-gpio"
 
diff --git a/dts/bindings/gpio/ite,it8xxx2-gpio-v2.yaml b/dts/bindings/gpio/ite,it8xxx2-gpio-v2.yaml
index 744365cc5a3..dbadba5713e 100644
--- a/dts/bindings/gpio/ite,it8xxx2-gpio-v2.yaml
+++ b/dts/bindings/gpio/ite,it8xxx2-gpio-v2.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2023 ITE Corporation. All Rights Reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-description: This binding gives a base representation of the ITE gpio
+description: ITE IT8xxx2 GPIO V2
 
 compatible: "ite,it8xxx2-gpio-v2"
 
diff --git a/dts/bindings/gpio/ite,it8xxx2-gpio.yaml b/dts/bindings/gpio/ite,it8xxx2-gpio.yaml
index 366c72f12f5..e6e6a5e48e6 100644
--- a/dts/bindings/gpio/ite,it8xxx2-gpio.yaml
+++ b/dts/bindings/gpio/ite,it8xxx2-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2020 ITE Corporation. All Rights Reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-description: This binding gives a base representation of the ITE gpio
+description: ITE IT8xxx2 GPIO
 
 compatible: "ite,it8xxx2-gpio"
 
diff --git a/dts/bindings/gpio/ite,it8xxx2-gpiokscan.yaml b/dts/bindings/gpio/ite,it8xxx2-gpiokscan.yaml
index bca75c534aa..489616c297a 100644
--- a/dts/bindings/gpio/ite,it8xxx2-gpiokscan.yaml
+++ b/dts/bindings/gpio/ite,it8xxx2-gpiokscan.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 ITE Corporation. All Rights Reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-description: This binding gives a base representation of the ITE kscan pins as gpio
+description: ITE IT8xxx2 Kscan Pins as GPIO
 
 compatible: "ite,it8xxx2-gpiokscan"
 
diff --git a/dts/bindings/gpio/linaro,96b-lscon-1v8.yaml b/dts/bindings/gpio/linaro,96b-lscon-1v8.yaml
index 56e43a95870..61872ba6116 100644
--- a/dts/bindings/gpio/linaro,96b-lscon-1v8.yaml
+++ b/dts/bindings/gpio/linaro,96b-lscon-1v8.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2019 Linaro Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Represents GPIO pin nodes exposed on the 96Boards 1.8v low-speed header
+description: GPIO Pin exposed on the 96Boards 1.8v low-speed header
 
 compatible: "linaro,96b-lscon-1v8"
 
diff --git a/dts/bindings/gpio/linaro,96b-lscon-3v3.yaml b/dts/bindings/gpio/linaro,96b-lscon-3v3.yaml
index 2fe7a499881..0441eecd2d4 100644
--- a/dts/bindings/gpio/linaro,96b-lscon-3v3.yaml
+++ b/dts/bindings/gpio/linaro,96b-lscon-3v3.yaml
@@ -1,8 +1,7 @@
 # Copyright (c) 2019 Linaro Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
-description: |
-    Represents GPIO pin nodes exposed on the 96Boards 3.3v low-speed header
+description: GPIO Pin exposed on the 96Boards 3.3v low-speed header
 
 compatible: "linaro,96b-lscon-3v3"
 
diff --git a/dts/bindings/gpio/microchip,mcp23008.yaml b/dts/bindings/gpio/microchip,mcp23008.yaml
index 5a5497249fd..cf5896c6e94 100644
--- a/dts/bindings/gpio/microchip,mcp23008.yaml
+++ b/dts/bindings/gpio/microchip,mcp23008.yaml
@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-description: This is a representation of the Microchip MCP23008 I2C GPIO Expander.
+description: Microchip MCP23008 I2C GPIO Expander.
 
 compatible: "microchip,mcp23008"
 
diff --git a/dts/bindings/gpio/microchip,mcp23009.yaml b/dts/bindings/gpio/microchip,mcp23009.yaml
index 5e8a50f8fd0..114753d1665 100644
--- a/dts/bindings/gpio/microchip,mcp23009.yaml
+++ b/dts/bindings/gpio/microchip,mcp23009.yaml
@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-description: This is a representation of the Microchip MCP23009 I2C GPIO Expander.
+description: Microchip MCP23009 I2C GPIO Expander.
 
 compatible: "microchip,mcp23009"
 
diff --git a/dts/bindings/gpio/microchip,mcp23016.yaml b/dts/bindings/gpio/microchip,mcp23016.yaml
index b2735030218..028d4e47718 100644
--- a/dts/bindings/gpio/microchip,mcp23016.yaml
+++ b/dts/bindings/gpio/microchip,mcp23016.yaml
@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-description: This is a representation of the Microchip MCP23016 I2C GPIO Expander.
+description: Microchip MCP23016 I2C GPIO Expander.
 
 compatible: "microchip,mcp23016"
 
diff --git a/dts/bindings/gpio/microchip,mcp23017.yaml b/dts/bindings/gpio/microchip,mcp23017.yaml
index 63bd108d401..c7fce77905c 100644
--- a/dts/bindings/gpio/microchip,mcp23017.yaml
+++ b/dts/bindings/gpio/microchip,mcp23017.yaml
@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-description: This is a representation of the Microchip MCP23017 I2C GPIO Expander.
+description: Microchip MCP23017 I2C GPIO Expander.
 
 compatible: "microchip,mcp23017"
 
diff --git a/dts/bindings/gpio/microchip,mcp23018.yaml b/dts/bindings/gpio/microchip,mcp23018.yaml
index 9af5bbe2575..45a28bc11dc 100644
--- a/dts/bindings/gpio/microchip,mcp23018.yaml
+++ b/dts/bindings/gpio/microchip,mcp23018.yaml
@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-description: This is a representation of the Microchip MCP23018 I2C GPIO Expander.
+description: Microchip MCP23018 I2C GPIO Expander.
 
 compatible: "microchip,mcp23018"
 
diff --git a/dts/bindings/gpio/microchip,mcp23s08.yaml b/dts/bindings/gpio/microchip,mcp23s08.yaml
index f9b8a663830..1dc9dfa702f 100644
--- a/dts/bindings/gpio/microchip,mcp23s08.yaml
+++ b/dts/bindings/gpio/microchip,mcp23s08.yaml
@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-description: This is a representation of the Microchip MCP23S08 SPI GPIO Expander.
+description: Microchip MCP23S08 SPI GPIO Expander.
 
 compatible: "microchip,mcp23s08"
 
diff --git a/dts/bindings/gpio/microchip,mcp23s09.yaml b/dts/bindings/gpio/microchip,mcp23s09.yaml
index c81ec0a87e8..c0cd223237d 100644
--- a/dts/bindings/gpio/microchip,mcp23s09.yaml
+++ b/dts/bindings/gpio/microchip,mcp23s09.yaml
@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-description: This is a representation of the Microchip MCP23S09 SPI GPIO Expander.
+description: Microchip MCP23S09 SPI GPIO Expander.
 
 compatible: "microchip,mcp23s09"
 
diff --git a/dts/bindings/gpio/microchip,mcp23s17.yaml b/dts/bindings/gpio/microchip,mcp23s17.yaml
index 7a2d7b84d84..1d109ad8a88 100644
--- a/dts/bindings/gpio/microchip,mcp23s17.yaml
+++ b/dts/bindings/gpio/microchip,mcp23s17.yaml
@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-description: This is a representation of the Microchip MCP23S17 SPI GPIO Expander.
+description: Microchip MCP23S17 SPI GPIO Expander.
 
 compatible: "microchip,mcp23s17"
 
diff --git a/dts/bindings/gpio/microchip,mcp23s18.yaml b/dts/bindings/gpio/microchip,mcp23s18.yaml
index a308572c23c..5a2d14560d2 100644
--- a/dts/bindings/gpio/microchip,mcp23s18.yaml
+++ b/dts/bindings/gpio/microchip,mcp23s18.yaml
@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-description: This is a representation of the Microchip MCP23S18 SPI GPIO Expander.
+description: Microchip MCP23S18 SPI GPIO Expander.
 
 compatible: "microchip,mcp23s18"
 
diff --git a/dts/bindings/gpio/microchip,mec5-gpio.yaml b/dts/bindings/gpio/microchip,mec5-gpio.yaml
index c29ecb3466a..d9ae269a5d7 100644
--- a/dts/bindings/gpio/microchip,mec5-gpio.yaml
+++ b/dts/bindings/gpio/microchip,mec5-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024, Microchip Technology Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Microchip MEC5 GPIO node
+description: Microchip MEC5 GPIO
 
 compatible: "microchip,mec5-gpio"
 
diff --git a/dts/bindings/gpio/microchip,mpfs-gpio.yaml b/dts/bindings/gpio/microchip,mpfs-gpio.yaml
index f5381133dc1..826e23aed89 100644
--- a/dts/bindings/gpio/microchip,mpfs-gpio.yaml
+++ b/dts/bindings/gpio/microchip,mpfs-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 Microchip Technology Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Microchip PolarFire SoC GPIO node
+description: Microchip PolarFire SoC GPIO
 
 compatible: "microchip,mpfs-gpio"
 
diff --git a/dts/bindings/gpio/microchip,xec-gpio-v2.yaml b/dts/bindings/gpio/microchip,xec-gpio-v2.yaml
index 22af68ce120..501172e30fe 100644
--- a/dts/bindings/gpio/microchip,xec-gpio-v2.yaml
+++ b/dts/bindings/gpio/microchip,xec-gpio-v2.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2019, Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-description: Microchip CEC/MEC GPIO V2 node
+description: Microchip CEC/MEC GPIO V2
 
 compatible: "microchip,xec-gpio-v2"
 
diff --git a/dts/bindings/gpio/microchip,xec-gpio.yaml b/dts/bindings/gpio/microchip,xec-gpio.yaml
index 21bbabf12a5..02e873a43e0 100644
--- a/dts/bindings/gpio/microchip,xec-gpio.yaml
+++ b/dts/bindings/gpio/microchip,xec-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2019, Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-description: Microchip CEC/MEC GPIO node
+description: Microchip CEC/MEC GPIO
 
 compatible: "microchip,xec-gpio"
 
diff --git a/dts/bindings/gpio/mikro-bus.yaml b/dts/bindings/gpio/mikro-bus.yaml
index 806961f39ee..8c123def1c3 100644
--- a/dts/bindings/gpio/mikro-bus.yaml
+++ b/dts/bindings/gpio/mikro-bus.yaml
@@ -12,7 +12,7 @@ description: |
     https://download.mikroe.com/documents/standards/mikrobus/mikrobus-standard-specification-v200.pdf
 
     This binding provides a nexus mapping for 10 pins, left side pins are
-    numbered 0 - 5 (AN - MOSI), the right side pins are numbered 6 - 10
+    numbered 0 - 5 (AN - MOSI), the right side pins are numbered 6 - 11
     (PWM - SDA). The bottom 2 pins on each side are used for input voltage
     and ground, they are not mapped in the nexus.
 
diff --git a/dts/bindings/gpio/neorv32,gpio.yaml b/dts/bindings/gpio/neorv32,gpio.yaml
new file mode 100644
index 00000000000..5417b92e50f
--- /dev/null
+++ b/dts/bindings/gpio/neorv32,gpio.yaml
@@ -0,0 +1,22 @@
+description: NEORV32 GPIO
+
+compatible: "neorv32,gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  syscon:
+    type: phandle
+    required: true
+    description: |
+      phandle to syscon (NEORV32 SYSINFO) node.
+
+  "#gpio-cells":
+    const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/neorv32-gpio.yaml b/dts/bindings/gpio/neorv32-gpio.yaml
deleted file mode 100644
index a357cd5eea9..00000000000
--- a/dts/bindings/gpio/neorv32-gpio.yaml
+++ /dev/null
@@ -1,25 +0,0 @@
-description: NEORV32 GPIO
-
-compatible: "neorv32-gpio"
-
-include: [gpio-controller.yaml, base.yaml]
-
-properties:
-  reg:
-    required: true
-
-  reg-names:
-    required: true
-
-  syscon:
-    type: phandle
-    required: true
-    description: |
-      phandle to syscon (NEORV32 SYSINFO) node.
-
-  "#gpio-cells":
-    const: 2
-
-gpio-cells:
-  - pin
-  - flags
diff --git a/dts/bindings/gpio/nordic,nrf-gpio.yaml b/dts/bindings/gpio/nordic,nrf-gpio.yaml
index 097a99d8fa9..6bde10bad07 100644
--- a/dts/bindings/gpio/nordic,nrf-gpio.yaml
+++ b/dts/bindings/gpio/nordic,nrf-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2018, marc-cpdesign
 # SPDX-License-Identifier: Apache-2.0
 
-description: NRF5 GPIO node
+description: NRF5 GPIO
 
 compatible: "nordic,nrf-gpio"
 
diff --git a/dts/bindings/gpio/nordic,nrf-gpiote.yaml b/dts/bindings/gpio/nordic,nrf-gpiote.yaml
index 4bb09574e9b..b9180857e44 100644
--- a/dts/bindings/gpio/nordic,nrf-gpiote.yaml
+++ b/dts/bindings/gpio/nordic,nrf-gpiote.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2018, marc-cpdesign
 # SPDX-License-Identifier: Apache-2.0
 
-description: NRF5 GPIOTE node
+description: NRF5 GPIOTE
 
 compatible: "nordic,nrf-gpiote"
 
diff --git a/dts/bindings/gpio/nuvoton,nct38xx-gpio-port.yaml b/dts/bindings/gpio/nuvoton,nct38xx-gpio-port.yaml
index af2d5eff200..d1158b75927 100644
--- a/dts/bindings/gpio/nuvoton,nct38xx-gpio-port.yaml
+++ b/dts/bindings/gpio/nuvoton,nct38xx-gpio-port.yaml
@@ -11,7 +11,7 @@ properties:
   reg:
     required: true
 
-  pin_mask:
+  pin-mask:
     type: int
     required: true
     description: |
@@ -21,7 +21,7 @@ properties:
       NCT3808: <0xdc>
       others: <0xff>
 
-  pinmux_mask:
+  pinmux-mask:
     type: int
     description: |
       NCT38XX series port 0 has Pin Multiplexing functionality. However, not
diff --git a/dts/bindings/gpio/nuvoton,nct38xx-gpio.yaml b/dts/bindings/gpio/nuvoton,nct38xx-gpio.yaml
index 5b9afbbc892..8f10d4b98ed 100644
--- a/dts/bindings/gpio/nuvoton,nct38xx-gpio.yaml
+++ b/dts/bindings/gpio/nuvoton,nct38xx-gpio.yaml
@@ -23,8 +23,8 @@ description: |
               gpio-controller;
               #gpio-cells = <2>;
               ngpios = <8>;
-              pin_mask = <0xff>;
-              pinmux_mask = <0xf7>;
+              pin-mask = <0xff>;
+              pinmux-mask = <0xf7>;
             };
 
             gpio@1 {
@@ -33,7 +33,7 @@ description: |
               gpio-controller;
               #gpio-cells = <2>;
               ngpios = <8>;
-              pin_mask = <0xff>;
+              pin-mask = <0xff>;
             };
           };
         };
@@ -53,8 +53,8 @@ description: |
               gpio-controller;
               #gpio-cells = <2>;
               ngpios = <8>;
-              pin_mask = <0xdc>;
-              pinmux_mask = <0xff>;
+              pin-mask = <0xdc>;
+              pinmux-mask = <0xff>;
             };
           };
         };
@@ -74,8 +74,8 @@ description: |
               gpio-controller;
               #gpio-cells = <2>;
               ngpios = <8>;
-              pin_mask = <0xdc>;
-              pinmux_mask = <0xff>;
+              pin-mask = <0xdc>;
+              pinmux-mask = <0xff>;
             };
           };
         };
diff --git a/dts/bindings/gpio/nuvoton,npcx-gpio.yaml b/dts/bindings/gpio/nuvoton,npcx-gpio.yaml
index b1e307e237c..4e60b2c1b9b 100644
--- a/dts/bindings/gpio/nuvoton,npcx-gpio.yaml
+++ b/dts/bindings/gpio/nuvoton,npcx-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2020 Nuvoton Technology Corporation.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Nuvoton, NPCX-GPIO node
+description: Nuvoton, NPCX-GPIO
 
 compatible: "nuvoton,npcx-gpio"
 
diff --git a/dts/bindings/gpio/nuvoton,numaker-gpio.yaml b/dts/bindings/gpio/nuvoton,numaker-gpio.yaml
index 29463aae271..40c216cbbf2 100644
--- a/dts/bindings/gpio/nuvoton,numaker-gpio.yaml
+++ b/dts/bindings/gpio/nuvoton,numaker-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2023 Nuvoton Technology Corporation.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Nuvoton, Numaker-GPIO node
+description: Nuvoton Numaker GPIO
 
 compatible: "nuvoton,numaker-gpio"
 
diff --git a/dts/bindings/gpio/nuvoton,numicro-gpio.yaml b/dts/bindings/gpio/nuvoton,numicro-gpio.yaml
index 173dcb3d7eb..10688372479 100644
--- a/dts/bindings/gpio/nuvoton,numicro-gpio.yaml
+++ b/dts/bindings/gpio/nuvoton,numicro-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 SEAL AG
 # SPDX-License-Identifier: Apache-2.0
 
-description: Nuvoton NuMicro GPIO node
+description: Nuvoton NuMicro GPIO
 
 compatible: "nuvoton,numicro-gpio"
 
diff --git a/dts/bindings/gpio/nxp,imx-gpio.yaml b/dts/bindings/gpio/nxp,imx-gpio.yaml
index d13db06b672..83471175d12 100644
--- a/dts/bindings/gpio/nxp,imx-gpio.yaml
+++ b/dts/bindings/gpio/nxp,imx-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright 2017, 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-description: i.MX GPIO node
+description: i.MX GPIO
 
 compatible: "nxp,imx-gpio"
 
diff --git a/dts/bindings/gpio/nxp,imx-rgpio.yaml b/dts/bindings/gpio/nxp,imx-rgpio.yaml
index 14aef8a9b30..9b032c1350c 100644
--- a/dts/bindings/gpio/nxp,imx-rgpio.yaml
+++ b/dts/bindings/gpio/nxp,imx-rgpio.yaml
@@ -1,7 +1,7 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-description: i.MX RGPIO node
+description: i.MX RGPIO
 
 compatible: "nxp,imx-rgpio"
 
diff --git a/dts/bindings/gpio/nxp,kinetis-gpio.yaml b/dts/bindings/gpio/nxp,kinetis-gpio.yaml
index 845a13714e0..2f4bed4a55d 100644
--- a/dts/bindings/gpio/nxp,kinetis-gpio.yaml
+++ b/dts/bindings/gpio/nxp,kinetis-gpio.yaml
@@ -1,4 +1,4 @@
-description: Kinetis GPIO node
+description: Kinetis GPIO
 
 compatible: "nxp,kinetis-gpio"
 
@@ -18,6 +18,12 @@ properties:
       A phandle reference to the device tree node that contains the pinmux
       port associated with this GPIO controller.
 
+  gpio-port-offest:
+    type: int
+    default: 0
+    description: |
+      Describes an offset between inst index and actual GPIO port number.
+
 gpio-cells:
   - pin
   - flags
diff --git a/dts/bindings/gpio/nxp,lcd-pmod.yaml b/dts/bindings/gpio/nxp,lcd-pmod.yaml
new file mode 100644
index 00000000000..ca1ca168006
--- /dev/null
+++ b/dts/bindings/gpio/nxp,lcd-pmod.yaml
@@ -0,0 +1,26 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+
+compatible: "nxp,lcd-pmod"
+
+description: |
+    GPIO pins exposed on NXP LCD pmod interface (e.g., used on LCD-PAR-035 panel).
+    These pins are exposed on a 12 pin connector. The pins have the
+    following assignments:
+
+      Pin Number    Usage
+      1             VCC
+      2             VCC
+      3             GND
+      4             GND
+      5             LCD PMOD interface WR pin
+      6             LCD touch controller I2C SCL
+      7             LCD PMOD interface D/C pin
+      8             LCD touch controller I2C SDA
+      9             LCD PMOD interface MOSI pin
+      10            LCD and touch reset
+      11            LCD PMOD interface CS pin
+      12            LCD touch interrupt
+
+include: [gpio-nexus.yaml, base.yaml]
diff --git a/dts/bindings/gpio/nxp,lpc-gpio.yaml b/dts/bindings/gpio/nxp,lpc-gpio.yaml
index 19b31bc284c..f0790306eeb 100644
--- a/dts/bindings/gpio/nxp,lpc-gpio.yaml
+++ b/dts/bindings/gpio/nxp,lpc-gpio.yaml
@@ -6,7 +6,7 @@
 # base address. It is the ports that are
 # functionally gpio devices.
 
-description: LPC GPIO node
+description: LPC GPIO
 
 compatible: "nxp,lpc-gpio"
 
diff --git a/dts/bindings/gpio/nxp,lpc11u6x-gpio.yaml b/dts/bindings/gpio/nxp,lpc11u6x-gpio.yaml
index 612d6f83d19..d39580668de 100644
--- a/dts/bindings/gpio/nxp,lpc11u6x-gpio.yaml
+++ b/dts/bindings/gpio/nxp,lpc11u6x-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2020 Seagate Technology LLC
 # SPDX-License-Identifier: Apache-2.0
 
-description: NXP LPC11U6X GPIO node
+description: NXP LPC11U6X GPIO
 
 compatible: "nxp,lpc11u6x-gpio"
 
diff --git a/dts/bindings/gpio/nxp,pca6416.yaml b/dts/bindings/gpio/nxp,pca6416.yaml
new file mode 100644
index 00000000000..b6e1a6e6b82
--- /dev/null
+++ b/dts/bindings/gpio/nxp,pca6416.yaml
@@ -0,0 +1,23 @@
+# Copyright 2024-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: PCA6416 I2C-based GPIO expander
+
+compatible: "nxp,pca6416"
+
+include: [gpio-controller.yaml, i2c-device.yaml]
+
+properties:
+  interrupt-gpios:
+    type: phandle-array
+    description:
+      Interrupt GPIO pin (active-low open-drain)
+      Left blank if the pin is not connected in your
+      application.
+
+  "#gpio-cells":
+    const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/nxp,pca9538.yaml b/dts/bindings/gpio/nxp,pca9538.yaml
index 5933b2841d3..07925f6d863 100644
--- a/dts/bindings/gpio/nxp,pca9538.yaml
+++ b/dts/bindings/gpio/nxp,pca9538.yaml
@@ -1,7 +1,9 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
-description: NXP PCA9538 I2C GPIO expander node
-compatible: nxp,pca9538
+description: NXP PCA9538 I2C GPIO expander
+
+compatible: "nxp,pca9538"
+
 include: nxp,pca_series.yaml
 
 properties:
diff --git a/dts/bindings/gpio/nxp,pca9539.yaml b/dts/bindings/gpio/nxp,pca9539.yaml
index 42101ba30f0..73468b694d2 100644
--- a/dts/bindings/gpio/nxp,pca9539.yaml
+++ b/dts/bindings/gpio/nxp,pca9539.yaml
@@ -1,7 +1,9 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
-description: NXP PCA9539 I2C GPIO expander node
-compatible: nxp,pca9539
+description: NXP PCA9539 I2C GPIO expander
+
+compatible: "nxp,pca9539"
+
 include: nxp,pca_series.yaml
 
 properties:
diff --git a/dts/bindings/gpio/nxp,pca9554.yaml b/dts/bindings/gpio/nxp,pca9554.yaml
index aa4ff0c65dc..c0298f62169 100644
--- a/dts/bindings/gpio/nxp,pca9554.yaml
+++ b/dts/bindings/gpio/nxp,pca9554.yaml
@@ -1,7 +1,9 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
-description: NXP PCA9554 I2C GPIO expander node
-compatible: nxp,pca9554
+description: NXP PCA9554 I2C GPIO expander
+
+compatible: "nxp,pca9554"
+
 include: nxp,pca_series.yaml
 
 properties:
diff --git a/dts/bindings/gpio/nxp,pca9555.yaml b/dts/bindings/gpio/nxp,pca9555.yaml
index 5902b2bacf7..3686ca3bf2b 100644
--- a/dts/bindings/gpio/nxp,pca9555.yaml
+++ b/dts/bindings/gpio/nxp,pca9555.yaml
@@ -1,7 +1,9 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
-description: NXP PCA9555 I2C GPIO expander node
-compatible: nxp,pca9555
+description: NXP PCA9555 I2C GPIO expander
+
+compatible: "nxp,pca9555"
+
 include: nxp,pca_series.yaml
 
 properties:
diff --git a/dts/bindings/gpio/nxp,pca_series.yaml b/dts/bindings/gpio/nxp,pca_series.yaml
index a37fa281e3b..84d56a5981b 100644
--- a/dts/bindings/gpio/nxp,pca_series.yaml
+++ b/dts/bindings/gpio/nxp,pca_series.yaml
@@ -1,7 +1,7 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-description: Base binding for PCA series I2C-based GPIO expander
+description: PCA series I2C-based GPIO expander
 
 include: [gpio-controller.yaml, i2c-device.yaml]
 
diff --git a/dts/bindings/gpio/nxp,pcal6524.yaml b/dts/bindings/gpio/nxp,pcal6524.yaml
index 8721cb6413f..96500e63684 100644
--- a/dts/bindings/gpio/nxp,pcal6524.yaml
+++ b/dts/bindings/gpio/nxp,pcal6524.yaml
@@ -1,7 +1,9 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
-description: NXP PCAL6524 I2C GPIO expander node
-compatible: nxp,pcal6524
+description: NXP PCAL6524 I2C GPIO expander
+
+compatible: "nxp,pcal6524"
+
 include: nxp,pca_series.yaml
 
 properties:
diff --git a/dts/bindings/gpio/nxp,pcal6534.yaml b/dts/bindings/gpio/nxp,pcal6534.yaml
index ea1ffd3e57e..8037483408a 100644
--- a/dts/bindings/gpio/nxp,pcal6534.yaml
+++ b/dts/bindings/gpio/nxp,pcal6534.yaml
@@ -1,7 +1,9 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
-description: NXP PCAL6534 I2C GPIO expander node
-compatible: nxp,pcal6534
+description: NXP PCAL6534 I2C GPIO expander
+
+compatible: "nxp,pcal6534"
+
 include: nxp,pca_series.yaml
 
 properties:
diff --git a/dts/bindings/gpio/openisa,rv32m1-gpio.yaml b/dts/bindings/gpio/openisa,rv32m1-gpio.yaml
index 369e25508d3..e5df0acfdb0 100644
--- a/dts/bindings/gpio/openisa,rv32m1-gpio.yaml
+++ b/dts/bindings/gpio/openisa,rv32m1-gpio.yaml
@@ -1,4 +1,4 @@
-description: OpenISA GPIO node
+description: OpenISA GPIO
 
 compatible: "openisa,rv32m1-gpio"
 
diff --git a/dts/bindings/gpio/quicklogic,eos-s3-gpio.yaml b/dts/bindings/gpio/quicklogic,eos-s3-gpio.yaml
index 182a820db39..7f32d1b17ab 100644
--- a/dts/bindings/gpio/quicklogic,eos-s3-gpio.yaml
+++ b/dts/bindings/gpio/quicklogic,eos-s3-gpio.yaml
@@ -1,4 +1,4 @@
-description: EOS S3 GPIO node
+description: EOS S3 GPIO
 
 compatible: "quicklogic,eos-s3-gpio"
 
diff --git a/dts/bindings/gpio/raspberrypi,pico-gpio-port.yaml b/dts/bindings/gpio/raspberrypi,pico-gpio-port.yaml
new file mode 100644
index 00000000000..fb4c9e4e737
--- /dev/null
+++ b/dts/bindings/gpio/raspberrypi,pico-gpio-port.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2021, Yonatan Schachter
+# SPDX-License-Identifier: Apache-2.0
+
+description: Raspberry Pi Pico GPIO Port
+
+compatible: "raspberrypi,pico-gpio-port"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  "#gpio-cells":
+    const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/raspberrypi,pico-gpio.yaml b/dts/bindings/gpio/raspberrypi,pico-gpio.yaml
index 89afb5084b5..dc441964a7b 100644
--- a/dts/bindings/gpio/raspberrypi,pico-gpio.yaml
+++ b/dts/bindings/gpio/raspberrypi,pico-gpio.yaml
@@ -1,19 +1,8 @@
-# Copyright (c) 2021, Yonatan Schachter
+# Copyright (c) 2024 TOKITA Hiroshi
 # SPDX-License-Identifier: Apache-2.0
 
 description: Raspberry Pi Pico GPIO
 
 compatible: "raspberrypi,pico-gpio"
 
-include: [gpio-controller.yaml, base.yaml]
-
-properties:
-  reg:
-    required: true
-
-  "#gpio-cells":
-    const: 2
-
-gpio-cells:
-  - pin
-  - flags
+include: [gpio-nexus.yaml, base.yaml]
diff --git a/dts/bindings/gpio/renesas,ra-gpio-ioport.yaml b/dts/bindings/gpio/renesas,ra-gpio-ioport.yaml
index 11c8ebf7944..1524a426686 100644
--- a/dts/bindings/gpio/renesas,ra-gpio-ioport.yaml
+++ b/dts/bindings/gpio/renesas,ra-gpio-ioport.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-description: Renesas RA GPIO IO port
+description: Renesas RA GPIO I/O Port
 
 compatible: "renesas,ra-gpio-ioport"
 
@@ -15,7 +15,7 @@ properties:
     type: int
     required: true
 
-  vbatts_pins:
+  vbatts-pins:
     type: array
     description: Array of vbatt pin on port
 
diff --git a/dts/bindings/gpio/renesas,ra-gpio.yaml b/dts/bindings/gpio/renesas,ra-gpio.yaml
deleted file mode 100644
index ad18a0d45da..00000000000
--- a/dts/bindings/gpio/renesas,ra-gpio.yaml
+++ /dev/null
@@ -1,83 +0,0 @@
-# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
-# SPDX-License-Identifier: Apache-2.0
-
-description: Renesas RA series GPIO
-
-compatible: "renesas,ra-gpio"
-
-include: [gpio-controller.yaml, base.yaml]
-
-properties:
-  reg:
-    required: true
-
-  port-irq0-pins:
-    type: array
-    description: Pins allow to assign port-irq0
-
-  port-irq1-pins:
-    type: array
-    description: Pins allow to assign port-irq1
-
-  port-irq2-pins:
-    type: array
-    description: Pins allow to assign port-irq2
-
-  port-irq3-pins:
-    type: array
-    description: Pins allow to assign port-irq3
-
-  port-irq4-pins:
-    type: array
-    description: Pins allow to assign port-irq4
-
-  port-irq5-pins:
-    type: array
-    description: Pins allow to assign port-irq5
-
-  port-irq6-pins:
-    type: array
-    description: Pins allow to assign port-irq6
-
-  port-irq7-pins:
-    type: array
-    description: Pins allow to assign port-irq7
-
-  port-irq8-pins:
-    type: array
-    description: Pins allow to assign port-irq8
-
-  port-irq9-pins:
-    type: array
-    description: Pins allow to assign port-irq9
-
-  port-irq10-pins:
-    type: array
-    description: Pins allow to assign port-irq10
-
-  port-irq11-pins:
-    type: array
-    description: Pins allow to assign port-irq11
-
-  port-irq12-pins:
-    type: array
-    description: Pins allow to assign port-irq12
-
-  port-irq13-pins:
-    type: array
-    description: Pins allow to assign port-irq13
-
-  port-irq14-pins:
-    type: array
-    description: Pins allow to assign port-irq14
-
-  port-irq15-pins:
-    type: array
-    description: Pins allow to assign port-irq15
-
-  "#gpio-cells":
-    const: 2
-
-gpio-cells:
-  - pin
-  - flags
diff --git a/dts/bindings/gpio/renesas,ra-parallel-graphics-header.yaml b/dts/bindings/gpio/renesas,ra-parallel-graphics-header.yaml
new file mode 100644
index 00000000000..106d61e05da
--- /dev/null
+++ b/dts/bindings/gpio/renesas,ra-parallel-graphics-header.yaml
@@ -0,0 +1,35 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  GPIO pins exposed on Renesas Parallel Graphics Expansion Header.
+
+  The Renesas Parallel Graphics Expansion Header consists of 2 rows of 20 pins each (40 pins total),
+
+  Pin mapping:
+
+    ------------------      --------------------
+    1   DISP_BLEN           2   IIC_SDA
+    3   DISP_INT            4   IIC_SCL
+    5   3V3                 6   DISP_RST
+    7   3V3                 8   5V0
+    9   LCDC_TCON0          10  LCDC_CLK
+    11  LCDC_TCON2          12  LCDC_TCON1
+    13  LCDC_EXTCLK         14  LCDC_TCON3
+    15  LCDC_DATA01         16  LCDC_DATA00
+    17  LCDC_DATA03         18  LCDC_DATA02
+    19  LCDC_DATA05         20  LCDC_DATA04
+    21  LCDC_DATA07         22  LCDC_DATA16
+    23  LCDC_DATA09         24  LCDC_DATA08
+    25  LCDC_DATA11         26  LCDC_DATA10
+    27  LCDC_DATA13         28  LCDC_DATA12
+    29  LCDC_DATA15         30  LCDC_DATA14
+    31  LCDC_DATA17         32  LCDC_DATA16
+    33  LCDC_DATA19         34  LCDC_DATA18
+    35  LCDC_DATA21         36  LCDC_DATA20
+    37  LCDC_DATA23         38  LCDC_DATA22
+    39  GND                 40  GND
+
+compatible: "renesas,ra-parallel-graphics-header"
+
+include: [gpio-nexus.yaml, base.yaml]
diff --git a/dts/bindings/gpio/renesas,rz-gpio.yaml b/dts/bindings/gpio/renesas,rz-gpio.yaml
index 9b4a37e6c17..ecf3808f487 100644
--- a/dts/bindings/gpio/renesas,rz-gpio.yaml
+++ b/dts/bindings/gpio/renesas,rz-gpio.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Reneses RZ  GPIO controller node.
+  Renesas RZ GPIO controller.
   Sample of usage:
     gpio-consumer{
           out-gpio = <&gpio8 2 (GPIO_PULL_UP);
diff --git a/dts/bindings/gpio/renesas,rza2m-gpio-int.yaml b/dts/bindings/gpio/renesas,rza2m-gpio-int.yaml
new file mode 100644
index 00000000000..3c4c5842e52
--- /dev/null
+++ b/dts/bindings/gpio/renesas,rza2m-gpio-int.yaml
@@ -0,0 +1,13 @@
+description: Renesas RZ/A2M GPIO Interrupt
+
+compatible: "renesas,rza2m-gpio-int"
+
+include: base.yaml
+
+properties:
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
diff --git a/dts/bindings/gpio/renesas,rza2m-gpio.yaml b/dts/bindings/gpio/renesas,rza2m-gpio.yaml
new file mode 100644
index 00000000000..fa859ff11fc
--- /dev/null
+++ b/dts/bindings/gpio/renesas,rza2m-gpio.yaml
@@ -0,0 +1,19 @@
+description: Renesas RZ/A2M GPIO Controller
+
+compatible: "renesas,rza2m-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+    description: |
+      GPIO port number. RZ/A2M board has a number of ports that
+      are used to calculate correct pin number.
+
+  "#gpio-cells":
+    const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/renesas,smartbond-gpio.yaml b/dts/bindings/gpio/renesas,smartbond-gpio.yaml
index 36cb1537cde..ee79e2cbd14 100644
--- a/dts/bindings/gpio/renesas,smartbond-gpio.yaml
+++ b/dts/bindings/gpio/renesas,smartbond-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-description: Renesas SmartBond(tm) GPIO node
+description: Renesas SmartBond(tm) GPIO
 
 compatible: "renesas,smartbond-gpio"
 
diff --git a/dts/bindings/gpio/richtek,rt1718s-gpio-port.yaml b/dts/bindings/gpio/richtek,rt1718s-gpio-port.yaml
index 6a95853ac81..d73d3bc671e 100644
--- a/dts/bindings/gpio/richtek,rt1718s-gpio-port.yaml
+++ b/dts/bindings/gpio/richtek,rt1718s-gpio-port.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    Richtek RT1718S TCPC chip GPIO port
+    Richtek RT1718S TCPC chip GPIO Port
 
     "richtek,rt1718s-gpio-port" node handles GPIO feature of the RT1718S TCPC
     chip.
diff --git a/dts/bindings/gpio/rohm,bd8lb600fs-gpio.yaml b/dts/bindings/gpio/rohm,bd8lb600fs-gpio.yaml
index 96c2d2832e9..155472ba8fc 100644
--- a/dts/bindings/gpio/rohm,bd8lb600fs-gpio.yaml
+++ b/dts/bindings/gpio/rohm,bd8lb600fs-gpio.yaml
@@ -6,7 +6,7 @@
 #
 
 description: |
-    This is a representation of the Rohm BD8LB600FS SPI Gpio Expander.
+    Rohm BD8LB600FS SPI GPIO Expander.
     Multiple instances may be daisy chained, which can be configured
     via the number of supported GPIOs.
 
diff --git a/dts/bindings/gpio/semtech,sx1509b.yaml b/dts/bindings/gpio/semtech,sx1509b.yaml
index b7e04843ef0..318e02a6c2f 100644
--- a/dts/bindings/gpio/semtech,sx1509b.yaml
+++ b/dts/bindings/gpio/semtech,sx1509b.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2018, Aapo Vienamo
 # SPDX-License-Identifier: Apache-2.0
 
-description: SX1509B GPIO node
+description: SX1509B GPIO
 
 compatible: "semtech,sx1509b"
 
diff --git a/dts/bindings/gpio/sensry,sy1xx-gpio.yaml b/dts/bindings/gpio/sensry,sy1xx-gpio.yaml
new file mode 100644
index 00000000000..f2fbadfc9e7
--- /dev/null
+++ b/dts/bindings/gpio/sensry,sy1xx-gpio.yaml
@@ -0,0 +1,25 @@
+# Copyright (c) 2024 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+description: Sensry SY1XX GPIO Port
+
+compatible: "sensry,sy1xx-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+    description: Base address for the gpio configuration.
+
+  "#gpio-cells":
+    const: 2
+
+  pad-cfg:
+    type: int
+    required: true
+    description: Offset for gpio pad ctrl registers.
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/sifive,gpio0.yaml b/dts/bindings/gpio/sifive,gpio0.yaml
index 41e7d2ae8a9..e80246db071 100644
--- a/dts/bindings/gpio/sifive,gpio0.yaml
+++ b/dts/bindings/gpio/sifive,gpio0.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2018, SiFive Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-description: SiFive GPIO node
+description: SiFive GPIO
 
 compatible: "sifive,gpio0"
 
diff --git a/dts/bindings/gpio/silabs,gecko-gpio-port.yaml b/dts/bindings/gpio/silabs,gecko-gpio-port.yaml
index 3551f4df1ff..09b7757f77a 100644
--- a/dts/bindings/gpio/silabs,gecko-gpio-port.yaml
+++ b/dts/bindings/gpio/silabs,gecko-gpio-port.yaml
@@ -1,4 +1,4 @@
-description: SiLabs Gecko GPIO port node
+description: SiLabs Gecko GPIO Port
 
 compatible: "silabs,gecko-gpio-port"
 
diff --git a/dts/bindings/gpio/silabs,gecko-gpio.yaml b/dts/bindings/gpio/silabs,gecko-gpio.yaml
index 0e923fd72f8..a1101849fe8 100644
--- a/dts/bindings/gpio/silabs,gecko-gpio.yaml
+++ b/dts/bindings/gpio/silabs,gecko-gpio.yaml
@@ -1,4 +1,4 @@
-description: SiLabs Gecko GPIO node
+description: SiLabs Gecko GPIO
 
 compatible: "silabs,gecko-gpio"
 
diff --git a/dts/bindings/gpio/silabs,si32-gpio.yaml b/dts/bindings/gpio/silabs,si32-gpio.yaml
index e317f916acd..99817cb5081 100644
--- a/dts/bindings/gpio/silabs,si32-gpio.yaml
+++ b/dts/bindings/gpio/silabs,si32-gpio.yaml
@@ -2,7 +2,7 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-description: Si32 GPIO node
+description: Si32 GPIO
 
 compatible: "silabs,si32-gpio"
 
diff --git a/dts/bindings/gpio/silabs,siwx91x-gpio-port.yaml b/dts/bindings/gpio/silabs,siwx91x-gpio-port.yaml
new file mode 100644
index 00000000000..c797e78ca3f
--- /dev/null
+++ b/dts/bindings/gpio/silabs,siwx91x-gpio-port.yaml
@@ -0,0 +1,25 @@
+description: Silabs SiWx91x GPIO Port
+
+compatible: "silabs,siwx91x-gpio-port"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+
+  reg:
+    required: true
+
+  "#gpio-cells":
+    const: 2
+
+  silabs,pads:
+    type: uint8-array
+    required: true
+    description: |
+      Contains the map of what pad number is used for each GPIO.
+      0xFF if a GPIO has no pad.
+      0 if the pad is directly configured using port and pin number.
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/silabs,siwx91x-gpio-uulp.yaml b/dts/bindings/gpio/silabs,siwx91x-gpio-uulp.yaml
new file mode 100644
index 00000000000..d527099de39
--- /dev/null
+++ b/dts/bindings/gpio/silabs,siwx91x-gpio-uulp.yaml
@@ -0,0 +1,17 @@
+description: Silabs SiWx91x UULP (ultra ultra low power) GPIO Port
+
+compatible: "silabs,siwx91x-gpio-uulp"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+
+  reg:
+    required: true
+
+  "#gpio-cells":
+    const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/silabs,siwx91x-gpio.yaml b/dts/bindings/gpio/silabs,siwx91x-gpio.yaml
new file mode 100644
index 00000000000..095d2573400
--- /dev/null
+++ b/dts/bindings/gpio/silabs,siwx91x-gpio.yaml
@@ -0,0 +1,17 @@
+description: Silabs SiWx91x GPIO
+
+compatible: "silabs,siwx91x-gpio"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  silabs,ulp:
+    type: boolean
+    description: |
+      If this property is set, the GPIO controller uses ULP (ultra low power) pads.
diff --git a/dts/bindings/gpio/snps,creg-gpio.yaml b/dts/bindings/gpio/snps,creg-gpio.yaml
index 954a9ae10d7..5f8897b66ee 100644
--- a/dts/bindings/gpio/snps,creg-gpio.yaml
+++ b/dts/bindings/gpio/snps,creg-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021 Synopsys, Inc. All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Synopsys CREG GPIO node
+description: Synopsys CREG GPIO
 
 compatible: "snps,creg-gpio"
 
@@ -11,15 +11,15 @@ properties:
   reg:
     required: true
 
-  bit_per_gpio:
+  bit-per-gpio:
     type: int
     required: true
 
-  off_val:
+  off-val:
     type: int
     required: true
 
-  on_val:
+  on-val:
     type: int
     required: true
 
diff --git a/dts/bindings/gpio/snps,designware-gpio.yaml b/dts/bindings/gpio/snps,designware-gpio.yaml
index 12b81c0455a..96629dfe0c1 100644
--- a/dts/bindings/gpio/snps,designware-gpio.yaml
+++ b/dts/bindings/gpio/snps,designware-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2018 Synopsys, Inc. All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Synopsys DesignWare GPIO node
+description: Synopsys DesignWare GPIO
 
 compatible: "snps,designware-gpio"
 
diff --git a/dts/bindings/gpio/st,dcmi-camera-fpu-330zh.yaml b/dts/bindings/gpio/st,dcmi-camera-fpu-330zh.yaml
new file mode 100644
index 00000000000..e6b74dfd3d5
--- /dev/null
+++ b/dts/bindings/gpio/st,dcmi-camera-fpu-330zh.yaml
@@ -0,0 +1,40 @@
+# Copyright (c) 2025 Charles Dias
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  GPIO pins exposed on the 30-pin ZIF connector (CN5) of the B-CAMS-OMV.
+  Connector layout:
+    (1)   3V3
+    (2)   GND
+    (3)   I2C_SCL
+    (4)   I2C_SDA
+    (5)   RESET#
+    (6)   PWR_EN / LED1
+    (7)   SHUTTER
+    (8)   GND
+    (9)   PULLDOWN / LED2
+    (10)  Camera_CLK
+    (11)  3V3
+    (12)  DCMI_VSYNC
+    (13)  5V (RSU)
+    (14)  DCMI_HSYNC
+    (15)  GND
+    (16)  DCMI_PIXCK
+    (17)  GND
+    (18)  SPI_MISO
+    (19)  SPI_CS
+    (20)  DCMI_D7
+    (21)  DCMI_D6
+    (22)  DCMI_D5
+    (23)  DCMI_D4
+    (24)  DCMI_D3
+    (25)  DCMI_D2
+    (26)  DCMI_D1
+    (27)  DCMI_D0
+    (28)  SPI_MOSI
+    (29)  SPI_CLK
+    (30)  GND
+
+compatible: "st,dcmi-camera-fpu-330zh"
+
+include: [gpio-nexus.yaml, base.yaml]
diff --git a/dts/bindings/gpio/st,mfxstm32l152.yaml b/dts/bindings/gpio/st,mfxstm32l152.yaml
new file mode 100644
index 00000000000..b01137043c3
--- /dev/null
+++ b/dts/bindings/gpio/st,mfxstm32l152.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: MFXSTM32L152 I2C-based GPIO expander
+
+compatible: "st,mfxstm32l152"
+
+include: [gpio-controller.yaml, i2c-device.yaml]
+
+properties:
+  int-gpios:
+    type: phandle-array
+    description: |
+        GPIO connected to the controller INT pin. This pin is active-low
+        and open-drain.
+
+  "#gpio-cells":
+    const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/st,stm32-gpio.yaml b/dts/bindings/gpio/st,stm32-gpio.yaml
index be1061ac085..ca99957f9fb 100644
--- a/dts/bindings/gpio/st,stm32-gpio.yaml
+++ b/dts/bindings/gpio/st,stm32-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2018, Linaro Limited
 # SPDX-License-Identifier: Apache-2.0
 
-description: STM32 GPIO node
+description: STM32 GPIO Controller
 
 compatible: "st,stm32-gpio"
 
diff --git a/dts/bindings/gpio/telink,b91-gpio.yaml b/dts/bindings/gpio/telink,b91-gpio.yaml
index 511b61208c4..427b6f77a35 100644
--- a/dts/bindings/gpio/telink,b91-gpio.yaml
+++ b/dts/bindings/gpio/telink,b91-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021, Telink Semiconductor
 # SPDX-License-Identifier: Apache-2.0
 
-description: Telink B91 GPIO node
+description: Telink B91 GPIO
 
 compatible: "telink,b91-gpio"
 
diff --git a/dts/bindings/gpio/ti,ads114s0x-gpio.yaml b/dts/bindings/gpio/ti,ads114s0x-gpio.yaml
deleted file mode 100644
index 62a7a483aa1..00000000000
--- a/dts/bindings/gpio/ti,ads114s0x-gpio.yaml
+++ /dev/null
@@ -1,27 +0,0 @@
-#
-# Copyright (c) 2022 SILA Embedded Solutions GmbH
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-
-description: TI ADS114S0x GPIO controller binding
-
-compatible: "ti,ads114s0x-gpio"
-
-include: [gpio-controller.yaml, base.yaml]
-
-on-bus: ads114s0x
-
-properties:
-  "#gpio-cells":
-    const: 2
-
-  ngpios:
-    type: int
-    required: true
-    const: 4
-    description: Number of gpios supported
-
-gpio-cells:
-  - pin
-  - flags
diff --git a/dts/bindings/gpio/ti,ads1x4s0x-gpio.yaml b/dts/bindings/gpio/ti,ads1x4s0x-gpio.yaml
new file mode 100644
index 00000000000..47423eb0251
--- /dev/null
+++ b/dts/bindings/gpio/ti,ads1x4s0x-gpio.yaml
@@ -0,0 +1,27 @@
+#
+# Copyright (c) 2022 SILA Embedded Solutions GmbH
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: TI ADS114S0x GPIO Controller
+
+compatible: "ti,ads1x4s0x-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+on-bus: ads1x4s0x
+
+properties:
+  "#gpio-cells":
+    const: 2
+
+  ngpios:
+    type: int
+    required: true
+    const: 4
+    description: Number of gpios supported
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/ti,cc13xx-cc26xx-gpio.yaml b/dts/bindings/gpio/ti,cc13xx-cc26xx-gpio.yaml
index 284c90d376a..c480ea77ae5 100644
--- a/dts/bindings/gpio/ti,cc13xx-cc26xx-gpio.yaml
+++ b/dts/bindings/gpio/ti,cc13xx-cc26xx-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2019 Brett Witherspoon
 # SPDX-License-Identifier: Apache-2.0
 
-description: TI SimpleLink CC13xx / CC26xx GPIO node
+description: TI SimpleLink CC13xx / CC26xx GPIO
 
 compatible: "ti,cc13xx-cc26xx-gpio"
 
diff --git a/dts/bindings/gpio/ti,cc23x0-gpio.yaml b/dts/bindings/gpio/ti,cc23x0-gpio.yaml
new file mode 100644
index 00000000000..9f2728b69b6
--- /dev/null
+++ b/dts/bindings/gpio/ti,cc23x0-gpio.yaml
@@ -0,0 +1,24 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+# Copyright (c) 2024 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI SimpleLink CC23X0 GPIO
+
+compatible: "ti,cc23x0-gpio"
+
+include: [gpio-controller.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  "#gpio-cells":
+    const: 2
+
+gpio-cells:
+  - pin
+  - flags
diff --git a/dts/bindings/gpio/ti,cc32xx-gpio.yaml b/dts/bindings/gpio/ti,cc32xx-gpio.yaml
index 1673df89153..55ac87e1006 100644
--- a/dts/bindings/gpio/ti,cc32xx-gpio.yaml
+++ b/dts/bindings/gpio/ti,cc32xx-gpio.yaml
@@ -1,5 +1,5 @@
 # SPDX-License-Identifier: Apache-2.0
-description: TI CC32XX GPIO node
+description: TI CC32XX GPIO
 
 compatible: "ti,cc32xx-gpio"
 
diff --git a/dts/bindings/gpio/ti,davinci-gpio-nexus.yaml b/dts/bindings/gpio/ti,davinci-gpio-nexus.yaml
index 1b38fe927ca..d3ed0f4374e 100644
--- a/dts/bindings/gpio/ti,davinci-gpio-nexus.yaml
+++ b/dts/bindings/gpio/ti,davinci-gpio-nexus.yaml
@@ -3,7 +3,7 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-description: GPIO controller for Davinci and Keystone devices
+description: GPIO Controller for Davinci and Keystone devices
 
 compatible: "ti,davinci-gpio-nexus"
 
diff --git a/dts/bindings/gpio/ti,davinci-gpio.yaml b/dts/bindings/gpio/ti,davinci-gpio.yaml
index 64c0bbd5db5..4b5360f224a 100644
--- a/dts/bindings/gpio/ti,davinci-gpio.yaml
+++ b/dts/bindings/gpio/ti,davinci-gpio.yaml
@@ -3,7 +3,7 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-description: GPIO controller for Davinci and Keystone devices.
+description: GPIO Controller for Davinci and Keystone devices.
 
 compatible: "ti,davinci-gpio"
 
diff --git a/dts/bindings/gpio/ti,lmp90xxx-gpio.yaml b/dts/bindings/gpio/ti,lmp90xxx-gpio.yaml
index 536b24be5c5..6fc960c2a37 100644
--- a/dts/bindings/gpio/ti,lmp90xxx-gpio.yaml
+++ b/dts/bindings/gpio/ti,lmp90xxx-gpio.yaml
@@ -1,4 +1,4 @@
-description: TI LMP90xxx GPIO controller binding
+description: TI LMP90xxx GPIO Controller
 
 compatible: "ti,lmp90xxx-gpio"
 
diff --git a/dts/bindings/gpio/ti,stellaris-gpio.yaml b/dts/bindings/gpio/ti,stellaris-gpio.yaml
index ecdfddd4a8d..a1486cf4d5e 100644
--- a/dts/bindings/gpio/ti,stellaris-gpio.yaml
+++ b/dts/bindings/gpio/ti,stellaris-gpio.yaml
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
-description: TI Stellaris GPIO node
+description: TI Stellaris GPIO
 
 compatible: "ti,stellaris-gpio"
 
diff --git a/dts/bindings/gpio/ti,tca9538.yaml b/dts/bindings/gpio/ti,tca9538.yaml
index 9200a9a1606..2b4f0098868 100644
--- a/dts/bindings/gpio/ti,tca9538.yaml
+++ b/dts/bindings/gpio/ti,tca9538.yaml
@@ -2,7 +2,7 @@
 # Copyright (c) 2021, Laird Connectivity
 # SPDX-License-Identifier: Apache-2.0
 
-description: TCA9538 GPIO node
+description: TCA9538 GPIO
 
 compatible: "ti,tca9538"
 
diff --git a/dts/bindings/gpio/x-powers,axp192-gpio.yaml b/dts/bindings/gpio/x-powers,axp192-gpio.yaml
index 5a56f60c121..5b54c0725f8 100644
--- a/dts/bindings/gpio/x-powers,axp192-gpio.yaml
+++ b/dts/bindings/gpio/x-powers,axp192-gpio.yaml
@@ -18,6 +18,8 @@ compatible: "x-powers,axp192-gpio"
 
 include: gpio-controller.yaml
 
+on-bus: axp192
+
 properties:
   "#gpio-cells":
     const: 2
diff --git a/dts/bindings/gpio/xlnx,ps-gpio-bank.yaml b/dts/bindings/gpio/xlnx,ps-gpio-bank.yaml
index 43e8f457421..78653046189 100644
--- a/dts/bindings/gpio/xlnx,ps-gpio-bank.yaml
+++ b/dts/bindings/gpio/xlnx,ps-gpio-bank.yaml
@@ -4,7 +4,7 @@
 #
 
 description: |
-  Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller bank node.
+  Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO Controller bank.
 
   Each node of this type specified in the devicetree represents
   a bank of the MIO/EMIO GPIO controller integrated in the Processor
diff --git a/dts/bindings/gpio/xlnx,ps-gpio.yaml b/dts/bindings/gpio/xlnx,ps-gpio.yaml
index 9271adda4e4..c13e2f84b73 100644
--- a/dts/bindings/gpio/xlnx,ps-gpio.yaml
+++ b/dts/bindings/gpio/xlnx,ps-gpio.yaml
@@ -4,7 +4,7 @@
 #
 
 description: |
-  Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO controller node.
+  Xilinx Zynq-7000/ZynqMP MIO/EMIO GPIO Controller.
 
   This GPIO controller is contained in both the Xilinx Zynq-7000 and
   ZynqMP (UltraScale) SoCs. It interfaces both I/O pins of the SoC,
diff --git a/dts/bindings/gpio/xlnx,xps-gpio-1.00.a-gpio2.yaml b/dts/bindings/gpio/xlnx,xps-gpio-1.00.a-gpio2.yaml
index b2c44c43659..9960076b54e 100644
--- a/dts/bindings/gpio/xlnx,xps-gpio-1.00.a-gpio2.yaml
+++ b/dts/bindings/gpio/xlnx,xps-gpio-1.00.a-gpio2.yaml
@@ -1,4 +1,4 @@
-description: Xilinx AXI GPIO IP GPIO2 node
+description: Xilinx AXI GPIO IP GPIO2
 
 compatible: "xlnx,xps-gpio-1.00.a-gpio2"
 
diff --git a/dts/bindings/gpio/xlnx,xps-gpio-1.00.a.yaml b/dts/bindings/gpio/xlnx,xps-gpio-1.00.a.yaml
index 673f47291ca..ead2829454d 100644
--- a/dts/bindings/gpio/xlnx,xps-gpio-1.00.a.yaml
+++ b/dts/bindings/gpio/xlnx,xps-gpio-1.00.a.yaml
@@ -1,4 +1,4 @@
-description: Xilinx AXI GPIO IP node
+description: Xilinx AXI GPIO IP
 
 compatible: "xlnx,xps-gpio-1.00.a"
 
diff --git a/dts/bindings/hwspinlock/sqn,hwspinlock.yaml b/dts/bindings/hwspinlock/sqn,hwspinlock.yaml
index 179d3d4449c..c4c7b3056c7 100644
--- a/dts/bindings/hwspinlock/sqn,hwspinlock.yaml
+++ b/dts/bindings/hwspinlock/sqn,hwspinlock.yaml
@@ -11,6 +11,6 @@ properties:
   reg:
     required: true
 
-  num_locks:
+  num-locks:
     type: int
     required: true
diff --git a/dts/bindings/i2c/ambiq,i2c.yaml b/dts/bindings/i2c/ambiq,i2c.yaml
index 7d7a87617dc..556dc792c47 100644
--- a/dts/bindings/i2c/ambiq,i2c.yaml
+++ b/dts/bindings/i2c/ambiq,i2c.yaml
@@ -5,18 +5,9 @@ description: Ambiq I2C
 
 compatible: "ambiq,i2c"
 
-include: [i2c-controller.yaml, pinctrl-device.yaml, ambiq-pwrcfg.yaml]
+include: [i2c-controller.yaml, pinctrl-device.yaml]
 
 properties:
-  reg:
-    required: true
-
-  interrupts:
-    required: true
-
-  ambiq,pwrcfg:
-    required: true
-
   scl-gpios:
     type: phandle-array
     description: |
diff --git a/dts/bindings/i2c/andestech,atciic100.yaml b/dts/bindings/i2c/andestech,atciic100.yaml
index 1af3b04c181..e54303eb4e7 100644
--- a/dts/bindings/i2c/andestech,atciic100.yaml
+++ b/dts/bindings/i2c/andestech,atciic100.yaml
@@ -4,8 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-description:
-  This is a representation of AndesTech atciic100 I2C node
+description: AndesTech ATCIIC100 I2C
 
 compatible: "andestech,atciic100"
 
diff --git a/dts/bindings/i2c/arm,versatile-i2c.yaml b/dts/bindings/i2c/arm,versatile-i2c.yaml
index c88d87002e5..b8b0ae52a3b 100644
--- a/dts/bindings/i2c/arm,versatile-i2c.yaml
+++ b/dts/bindings/i2c/arm,versatile-i2c.yaml
@@ -1,11 +1,12 @@
 # Copyright (c) 2018, Linaro Limited
+# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 description: ARM SBCon two-wire serial bus interface
 
 compatible: "arm,versatile-i2c"
 
-include: i2c-controller.yaml
+include: [i2c-controller.yaml, pinctrl-device.yaml]
 
 properties:
   reg:
diff --git a/dts/bindings/i2c/atmel,sam-i2c-twi.yaml b/dts/bindings/i2c/atmel,sam-i2c-twi.yaml
index c22646160d5..4acaa564155 100644
--- a/dts/bindings/i2c/atmel,sam-i2c-twi.yaml
+++ b/dts/bindings/i2c/atmel,sam-i2c-twi.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2017 Piotr Mienkowski
 # SPDX-License-Identifier: Apache-2.0
 
-description: Atmel SAM Family I2C (TWI) node
+description: Atmel SAM Family I2C (TWI)
 
 compatible: "atmel,sam-i2c-twi"
 
diff --git a/dts/bindings/i2c/atmel,sam-i2c-twihs.yaml b/dts/bindings/i2c/atmel,sam-i2c-twihs.yaml
index abaad2cf27c..1eeeb4ab2bd 100644
--- a/dts/bindings/i2c/atmel,sam-i2c-twihs.yaml
+++ b/dts/bindings/i2c/atmel,sam-i2c-twihs.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2017 Piotr Mienkowski
 # SPDX-License-Identifier: Apache-2.0
 
-description: Atmel SAM Family I2C (TWIHS) node
+description: Atmel SAM Family I2C (TWIHS)
 
 compatible: "atmel,sam-i2c-twihs"
 
diff --git a/dts/bindings/i2c/atmel,sam-i2c-twim.yaml b/dts/bindings/i2c/atmel,sam-i2c-twim.yaml
index 90c5c6e8388..dc06d32a9be 100644
--- a/dts/bindings/i2c/atmel,sam-i2c-twim.yaml
+++ b/dts/bindings/i2c/atmel,sam-i2c-twim.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Atmel SAM4L Family I2C (TWIM) node
+  Atmel SAM4L Family I2C (TWIM)
 
   The Atmel Two-wire Master Interface (TWIM) interconnects components on a
   unique two-wire bus, made up of one clock line and one data line with speeds
diff --git a/dts/bindings/i2c/atmel,sam0-i2c.yaml b/dts/bindings/i2c/atmel,sam0-i2c.yaml
index 9f8d34e95f9..134657fa553 100644
--- a/dts/bindings/i2c/atmel,sam0-i2c.yaml
+++ b/dts/bindings/i2c/atmel,sam0-i2c.yaml
@@ -1,13 +1,15 @@
 # Copyright (c) 2019 Derek Hageman <hageman@inthat.cloud>
+# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
-description: Atmel SAM0 series SERCOM I2C node
+description: Atmel SAM0 series SERCOM I2C
 
 compatible: "atmel,sam0-i2c"
 
 include:
   - name: i2c-controller.yaml
   - name: pinctrl-device.yaml
+  - name: atmel,assigned-clocks.yaml
 
 properties:
   reg:
@@ -22,6 +24,12 @@ properties:
   clock-names:
     required: true
 
+  atmel,assigned-clocks:
+    required: true
+
+  atmel,assigned-clock-names:
+    required: true
+
   dmas:
     description: |
       Optional TX & RX dma specifiers.  Each specifier will have a phandle
diff --git a/dts/bindings/i2c/cdns,i2c.yaml b/dts/bindings/i2c/cdns,i2c.yaml
new file mode 100644
index 00000000000..e03925cad29
--- /dev/null
+++ b/dts/bindings/i2c/cdns,i2c.yaml
@@ -0,0 +1,42 @@
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Cadence I2C controller.
+
+  Example I2C device tree node:
+    i2c@e0004000 {
+        compatible = "cdns,i2c";
+        clocks = <&clkc 38>;
+        interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+        reg = <0xe0004000 0x1000>;
+        clock-frequency = <400000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+        fifo-depth = <8>;
+    };
+
+compatible: "cdns,i2c"
+
+include: [i2c-controller.yaml, reset-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  clocks:
+    required: true
+    description: Reference Input clock for I2C core.
+
+  interrupts:
+    required: true
+
+  clock-frequency:
+    required: true
+    description: Desired I2C bus clock frequency in Hz.
+
+  fifo-depth:
+    type: int
+    required: true
+    description: Size of the data FIFO in bytes.
diff --git a/dts/bindings/i2c/fsl,imx21-i2c.yaml b/dts/bindings/i2c/fsl,imx21-i2c.yaml
index 7a8fcaabc52..a9fb34cbb5e 100644
--- a/dts/bindings/i2c/fsl,imx21-i2c.yaml
+++ b/dts/bindings/i2c/fsl,imx21-i2c.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2018 Linaro Limited
 # SPDX-License-Identifier: Apache-2.0
 
-description: i.MX I2C node
+description: i.MX I2C
 
 compatible: "fsl,imx21-i2c"
 
diff --git a/dts/bindings/i2c/litex,litei2c.yaml b/dts/bindings/i2c/litex,litei2c.yaml
new file mode 100644
index 00000000000..d85bd410f02
--- /dev/null
+++ b/dts/bindings/i2c/litex,litei2c.yaml
@@ -0,0 +1,18 @@
+#
+# Copyright (c) 2024 Vogl Electronic GmbH
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+description: LiteX LiteI2C I2C controller
+
+compatible: "litex,litei2c"
+
+include: i2c-controller.yaml
+
+properties:
+  reg:
+    required: true
+
+  clock-frequency:
+    required: true
diff --git a/dts/bindings/i2c/microchip,mpfs-i2c.yaml b/dts/bindings/i2c/microchip,mpfs-i2c.yaml
index 36d0b00b7d8..3da7cc07547 100644
--- a/dts/bindings/i2c/microchip,mpfs-i2c.yaml
+++ b/dts/bindings/i2c/microchip,mpfs-i2c.yaml
@@ -4,8 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-description:
-  Microchip MPFS I2C Controller Device Tree Bindings
+description: Microchip MPFS I2C Controller
 
 compatible: "microchip,mpfs-i2c"
 
diff --git a/dts/bindings/i2c/microchip,xec-i2c-v2.yaml b/dts/bindings/i2c/microchip,xec-i2c-v2.yaml
index 619e8e86231..b1f686a2905 100644
--- a/dts/bindings/i2c/microchip,xec-i2c-v2.yaml
+++ b/dts/bindings/i2c/microchip,xec-i2c-v2.yaml
@@ -11,7 +11,7 @@ properties:
   reg:
     required: true
 
-  port_sel:
+  port-sel:
     type: int
     description: soc block mapping to pin
     required: true
diff --git a/dts/bindings/i2c/microchip,xec-i2c.yaml b/dts/bindings/i2c/microchip,xec-i2c.yaml
index 3cb2d0fc7a0..5fd56979694 100644
--- a/dts/bindings/i2c/microchip,xec-i2c.yaml
+++ b/dts/bindings/i2c/microchip,xec-i2c.yaml
@@ -11,7 +11,7 @@ properties:
   reg:
     required: true
 
-  port_sel:
+  port-sel:
     type: int
     description: soc block mapping to pin
     required: true
diff --git a/dts/bindings/i2c/nuvoton,npcx-i2c-ctrl.yaml b/dts/bindings/i2c/nuvoton,npcx-i2c-ctrl.yaml
index e14ce0ae236..6e1b8e77bd5 100644
--- a/dts/bindings/i2c/nuvoton,npcx-i2c-ctrl.yaml
+++ b/dts/bindings/i2c/nuvoton,npcx-i2c-ctrl.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2020 Nuvoton Technology Corporation.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Nuvoton, NPCX-I2C controller node
+description: Nuvoton NPCX-I2C controller
 
 compatible: "nuvoton,npcx-i2c-ctrl"
 
@@ -12,3 +12,11 @@ properties:
     required: true
   clocks:
     required: true
+  smb-wui:
+    type: phandle
+    required: true
+    description: |
+        Mapping table between Wake-Up Input (WUI) and SMB module.
+
+        For example the WUI mapping on SMB 4 module would be
+           smb-wui = <&wui_smb4>;
diff --git a/dts/bindings/i2c/nuvoton,npcx-i2c-port.yaml b/dts/bindings/i2c/nuvoton,npcx-i2c-port.yaml
index 8f5f288705e..339c33cf203 100644
--- a/dts/bindings/i2c/nuvoton,npcx-i2c-port.yaml
+++ b/dts/bindings/i2c/nuvoton,npcx-i2c-port.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2020 Nuvoton Technology Corporation.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Nuvoton, NPCX-I2C port pads node
+description: Nuvoton NPCX-I2C port pads
 
 compatible: "nuvoton,npcx-i2c-port"
 
@@ -11,7 +11,13 @@ properties:
   port:
     type: int
     required: true
-    description: index of i2c port
+    description: |
+      Index of i2c port
+      This property is used to differentiate between multiple I2C ports controlled by the same
+      or different I2C controllers.
+      Bit[7:4] module id (controller).
+      Bit[3:0] port id.
+      Use the macro NPCX_I2C_CTRL_PORT(ctrl, port) to set this property.
 
   controller:
     type: phandle
diff --git a/dts/bindings/i2c/nxp,ii2c.yaml b/dts/bindings/i2c/nxp,ii2c.yaml
new file mode 100644
index 00000000000..1c3e0d39f85
--- /dev/null
+++ b/dts/bindings/i2c/nxp,ii2c.yaml
@@ -0,0 +1,15 @@
+# Copyright 2024-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP II2C
+
+compatible: "nxp,ii2c"
+
+include: [i2c-controller.yaml, pinctrl-device.yaml, "nxp,rdc-policy.yaml"]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
diff --git a/dts/bindings/i2c/nxp,kinetis-i2c.yaml b/dts/bindings/i2c/nxp,kinetis-i2c.yaml
index 32c41632140..b7616f6efe6 100644
--- a/dts/bindings/i2c/nxp,kinetis-i2c.yaml
+++ b/dts/bindings/i2c/nxp,kinetis-i2c.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2017 Linaro Limited
 # SPDX-License-Identifier: Apache-2.0
 
-description: Kinetis I2C node
+description: Kinetis I2C
 
 compatible: "nxp,kinetis-i2c"
 
diff --git a/dts/bindings/i2c/nxp,lpc-i2c.yaml b/dts/bindings/i2c/nxp,lpc-i2c.yaml
index 54aa4b7fb58..c4fdd88a428 100644
--- a/dts/bindings/i2c/nxp,lpc-i2c.yaml
+++ b/dts/bindings/i2c/nxp,lpc-i2c.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2019 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-description: LPC I2C node
+description: LPC I2C
 
 compatible: "nxp,lpc-i2c"
 
diff --git a/dts/bindings/i2c/raspberrypi,pico-i2c.yaml b/dts/bindings/i2c/raspberrypi,pico-i2c.yaml
index ac055dcfd59..331c5762b89 100644
--- a/dts/bindings/i2c/raspberrypi,pico-i2c.yaml
+++ b/dts/bindings/i2c/raspberrypi,pico-i2c.yaml
@@ -2,4 +2,4 @@ description: Raspberry Pi Pico I2C
 
 compatible: "raspberrypi,pico-i2c"
 
-include: ["snps,designware-i2c.yaml", "reset-device.yaml"]
+include: "snps,designware-i2c.yaml"
diff --git a/dts/bindings/i2c/renesas,ra-i2c-sci-b.yaml b/dts/bindings/i2c/renesas,ra-i2c-sci-b.yaml
new file mode 100644
index 00000000000..75beaa59ef1
--- /dev/null
+++ b/dts/bindings/i2c/renesas,ra-i2c-sci-b.yaml
@@ -0,0 +1,34 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA SCI-B I2C controller
+
+compatible: "renesas,ra-i2c-sci-b"
+
+include: [i2c-controller.yaml, pinctrl-device.yaml]
+
+properties:
+
+  channel:
+    required: true
+    type: int
+
+  sda-output-delay:
+    type: int
+    default: 300
+    description: |
+      SDA Output Delay in nano seconds.
+
+  noise-filter-clock-select:
+    type: int
+    default: 1
+    enum: [1, 2, 3, 4]
+    description: |
+      Select the on-chip baud rate generator source clock
+      division setting for the digital noise filter.
+
+  bit-rate-modulation:
+    type: boolean
+    description: |
+      Enabling bitrate modulation reduces the percent error
+      of the actual bitrate with respect to the requested baud rate.
diff --git a/dts/bindings/i2c/renesas,rz-riic.yaml b/dts/bindings/i2c/renesas,rz-riic.yaml
new file mode 100644
index 00000000000..42b7fdc5d96
--- /dev/null
+++ b/dts/bindings/i2c/renesas,rz-riic.yaml
@@ -0,0 +1,44 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RZ/G3S I2C controller
+
+compatible: "renesas,rz-riic"
+
+include: [i2c-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  channel:
+    required: true
+    type: int
+
+  interrupts:
+    required: true
+
+  rise-time-ns:
+    type: int
+    default: 120
+    description: |
+      Number of nanoseconds the SCL signal takes to rise; t(r) in the I2C specification.
+
+  fall-time-ns:
+    type: int
+    default: 120
+    description: |
+      Number of nanoseconds the SCL signal takes to fall; t(f) in the I2C specification.
+
+  duty-cycle-percent:
+    type: int
+    default: 50
+
+  noise-filter-stages:
+    type: int
+    default: 1
+    enum:
+      - 1
+      - 2
+      - 3
+      - 4
diff --git a/dts/bindings/i2c/sensry,sy1xxx-i2c.yaml b/dts/bindings/i2c/sensry,sy1xxx-i2c.yaml
new file mode 100644
index 00000000000..124b2d98709
--- /dev/null
+++ b/dts/bindings/i2c/sensry,sy1xxx-i2c.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2024 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+description: Sensry SY1XX I2C Driver node
+
+compatible: "sensry,sy1xx-i2c"
+
+include: [i2c-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  instance:
+    type: int
+    required: true
diff --git a/dts/bindings/i2c/silabs,gecko-i2c.yaml b/dts/bindings/i2c/silabs,gecko-i2c.yaml
index ef694376ac9..c3ab3258fc9 100644
--- a/dts/bindings/i2c/silabs,gecko-i2c.yaml
+++ b/dts/bindings/i2c/silabs,gecko-i2c.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2018 Diego Sueiro <diego.sueiro@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
-description: Silabs Gecko I2C node
+description: Silabs Gecko I2C
 
 compatible: "silabs,gecko-i2c"
 
diff --git a/dts/bindings/i2c/snps,designware-i2c.yaml b/dts/bindings/i2c/snps,designware-i2c.yaml
index 770ff98b5fc..cc02989d927 100644
--- a/dts/bindings/i2c/snps,designware-i2c.yaml
+++ b/dts/bindings/i2c/snps,designware-i2c.yaml
@@ -1,11 +1,11 @@
 # Copyright (c) 2018 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-description: Synopsys DesignWare I2C node
+description: Synopsys DesignWare I2C
 
 compatible: "snps,designware-i2c"
 
-include: [i2c-controller.yaml, pinctrl-device.yaml, pcie-device.yaml]
+include: [i2c-controller.yaml, pinctrl-device.yaml, pcie-device.yaml, reset-device.yaml]
 
 properties:
   interrupts:
diff --git a/dts/bindings/i2c/st,stm32-i2c-v2.yaml b/dts/bindings/i2c/st,stm32-i2c-v2.yaml
index bc859873ac0..80283d518b1 100644
--- a/dts/bindings/i2c/st,stm32-i2c-v2.yaml
+++ b/dts/bindings/i2c/st,stm32-i2c-v2.yaml
@@ -55,3 +55,15 @@ properties:
     description: |
       GPIO to which the I2C SDA signal is routed. This is only needed for
       I2C bus recovery support.
+
+  dmas:
+    type: phandle-array
+    description: |
+      Optional DMA channels used by the I2C peripheral. If specified, these
+      channels can be used to handle RX and TX transactions over DMA.
+
+  dma-names:
+    type: string-array
+    description: |
+      Names of the optional DMA channels. Expected values are "tx" for
+      the TX channel and "rx" for the RX channel.
diff --git a/dts/bindings/i2c/ti,cc13xx-cc26xx-i2c.yaml b/dts/bindings/i2c/ti,cc13xx-cc26xx-i2c.yaml
index f9e55a09a77..0e3581760f9 100644
--- a/dts/bindings/i2c/ti,cc13xx-cc26xx-i2c.yaml
+++ b/dts/bindings/i2c/ti,cc13xx-cc26xx-i2c.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2019 Brett Witherspoon
 # SPDX-License-Identifier: Apache-2.0
 
-description: TI CC13xx / CC26xx I2C node
+description: TI CC13xx / CC26xx I2C
 
 compatible: "ti,cc13xx-cc26xx-i2c"
 
diff --git a/dts/bindings/i2c/ti,omap-i2c.yaml b/dts/bindings/i2c/ti,omap-i2c.yaml
new file mode 100644
index 00000000000..b9c976d0881
--- /dev/null
+++ b/dts/bindings/i2c/ti,omap-i2c.yaml
@@ -0,0 +1,20 @@
+description: TI OMAP I2C Controller
+compatible: "ti,omap-i2c"
+include: [i2c-controller.yaml, pinctrl-device.yaml]
+properties:
+  reg:
+    description: Base address and size of the I2C registers.
+    required: true
+  interrupts:
+    description: Interrupt specifier for the I2C controller.
+    required: true
+  pinctrl-0:
+    description: Pin control groups for this I2C instance.
+    required: true
+  pinctrl-names:
+    description: Names for the pin control groups.
+    required: true
+  clock-frequency:
+    description: The frequency of the I2C bus.
+    default: 100000
+    required: true
diff --git a/dts/bindings/i2c/ti,tca9544a.yaml b/dts/bindings/i2c/ti,tca9544a.yaml
index 16c00b90784..b110c8084af 100644
--- a/dts/bindings/i2c/ti,tca9544a.yaml
+++ b/dts/bindings/i2c/ti,tca9544a.yaml
@@ -1,6 +1,6 @@
 # Binding for TI TCA9544A, compatible with NXP PCA9544A
 
-description: Texas Instruments TCA9544A binding
+description: Texas Instruments TCA9544A
 
 compatible: "ti,tca9544a"
 
diff --git a/dts/bindings/i2c/ti,tca9546a.yaml b/dts/bindings/i2c/ti,tca9546a.yaml
index 95741cd72c3..7687318ac7b 100644
--- a/dts/bindings/i2c/ti,tca9546a.yaml
+++ b/dts/bindings/i2c/ti,tca9546a.yaml
@@ -1,6 +1,6 @@
 # Binding for TI TCA9546A, compatible with NXP PCA9546A
 
-description: Texas Instruments TCA9546A binding
+description: Texas Instruments TCA9546A
 
 compatible: "ti,tca9546a"
 
diff --git a/dts/bindings/i2c/ti,tca9548a.yaml b/dts/bindings/i2c/ti,tca9548a.yaml
index bddf59e120a..8afa76e039b 100644
--- a/dts/bindings/i2c/ti,tca9548a.yaml
+++ b/dts/bindings/i2c/ti,tca9548a.yaml
@@ -1,6 +1,6 @@
 # Binding for TI TCA9548A, compatible with NXP PCA9548A
 
-description: Texas Instruments TCA9548A binding
+description: Texas Instruments TCA9548A
 
 compatible: "ti,tca9548a"
 
diff --git a/dts/bindings/i2c/ti,tca954x-base.yaml b/dts/bindings/i2c/ti,tca954x-base.yaml
index 2ce07e0fb6a..3a13f50f79c 100644
--- a/dts/bindings/i2c/ti,tca954x-base.yaml
+++ b/dts/bindings/i2c/ti,tca954x-base.yaml
@@ -20,25 +20,25 @@ description: |
           reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>;
 
           mux_i2c@0 {
-              compatible: "ti,tca9546a-channel"
+              compatible = "ti,tca9546a-channel";
               reg = <0>;
               #address-cells = <1>;
               #size-cells = <0>;
 
-              temp_sens_0: tmp116@49 {
-                  compatible = "ti,tmp116";
+              temp_sens_0: tmp11x@49 {
+                  compatible = "ti,tmp11x";
                   reg = <0x49>;
               };
           };
 
           mux_i2c@1 {
-            compatible: "ti,tca9546a-channel"
+              compatible = "ti,tca9546a-channel";
               reg = <1>;
               #address-cells = <1>;
               #size-cells = <0>;
 
-              temp_sens_1: tmp116@49 {
-                  compatible = "ti,tmp116";
+              temp_sens_1: tmp11x@49 {
+                  compatible = "ti,tmp11x";
                   reg = <0x49>;
               };
           };
@@ -52,6 +52,13 @@ properties:
     description: |
       GPIO connected to the controller RESET pin. This pin is active-low.
 
+  i2c-mux-idle-disconnect:
+    type: boolean
+    description: |
+      Forces mux to disconnect all children in idle state. This is
+      necessary for example, if there are several multiplexers on the bus and
+      the devices behind them use same I2C addresses.
+
 child-binding:
   description: TCA954x I2C switch channel node
   include: [i2c-controller.yaml]
diff --git a/dts/bindings/i2c/wch,i2c.yaml b/dts/bindings/i2c/wch,i2c.yaml
new file mode 100644
index 00000000000..416ab38c4d4
--- /dev/null
+++ b/dts/bindings/i2c/wch,i2c.yaml
@@ -0,0 +1,24 @@
+# Copyright (c) 2025 Andrei-Edward Popa
+# SPDX-License-Identifier: Apache-2.0
+
+description: WCH I2C controller
+
+compatible: "wch,i2c"
+
+include: [i2c-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  clocks:
+    required: true
+
+  interrupts:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
diff --git a/dts/bindings/i2s/espressif,esp32-i2s.yaml b/dts/bindings/i2s/espressif,esp32-i2s.yaml
index aded3488636..16e32b90a43 100644
--- a/dts/bindings/i2s/espressif,esp32-i2s.yaml
+++ b/dts/bindings/i2s/espressif,esp32-i2s.yaml
@@ -23,12 +23,6 @@ properties:
   interrupt-parent:
     required: true
 
-  dmas:
-    required: true
-
-  dma-names:
-    required: true
-
   unit:
     type: int
     required: true
diff --git a/dts/bindings/i2s/litex,i2s.yaml b/dts/bindings/i2s/litex,i2s.yaml
index 9259e02250a..60031781e03 100644
--- a/dts/bindings/i2s/litex,i2s.yaml
+++ b/dts/bindings/i2s/litex,i2s.yaml
@@ -13,6 +13,6 @@ properties:
   reg:
     required: true
 
-  fifo_depth:
+  fifo-depth:
     type: int
     required: true
diff --git a/dts/bindings/i2s/nxp,mcux-i2s.yaml b/dts/bindings/i2s/nxp,mcux-i2s.yaml
index 25295432874..7fbd85f53a3 100644
--- a/dts/bindings/i2s/nxp,mcux-i2s.yaml
+++ b/dts/bindings/i2s/nxp,mcux-i2s.yaml
@@ -1,4 +1,4 @@
-# Copyright 2021,2023 NXP
+# Copyright 2021,2023-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 description: NXP mcux SAI-I2S controller
@@ -62,6 +62,14 @@ properties:
     description: tx channel the maximum number is SOC dependent
 
   clock-mux:
-    required: true
     type: int
     description: Clock mux source for SAI root clock
+
+  mclk-output:
+    type: boolean
+    description: |
+      Set if MCLK signal is an output.  Hardware default sets MCLK signal as input.
+
+pinmux-cells:
+  - offset
+  - mask
diff --git a/dts/bindings/i3c/i3c-controller.yaml b/dts/bindings/i3c/i3c-controller.yaml
index 50472604b5e..c6ac5eacccd 100644
--- a/dts/bindings/i3c/i3c-controller.yaml
+++ b/dts/bindings/i3c/i3c-controller.yaml
@@ -30,3 +30,11 @@ properties:
       and there are I2C devices attached to the bus, look at the Legacy
       Virtual Register (LVR) of all connected I2C devices to determine
       the maximum allowed frequency.
+
+  primary-controller-da:
+    type: int
+    description: |
+      This is the self assigned dynamic address of the I3C controller. This
+      is the address is used to communicate with itself after a handoff by
+      a secondary controller. This is only used if the controller is a primary
+      controller.
diff --git a/dts/bindings/i3c/i3c-device.yaml b/dts/bindings/i3c/i3c-device.yaml
index 297e28e6325..76e4dafa630 100644
--- a/dts/bindings/i3c/i3c-device.yaml
+++ b/dts/bindings/i3c/i3c-device.yaml
@@ -67,3 +67,8 @@ properties:
     description: |
       Indicates if the device supports the CCC SETAASA. If true, it will
       be used as an optimization for bus initialization.
+
+  v1p0-support:
+    type: boolean
+    description: |
+      Indicates if the device compiles to I3C v1.0.
diff --git a/dts/bindings/i3c/snps,designware-i3c.yaml b/dts/bindings/i3c/snps,designware-i3c.yaml
new file mode 100644
index 00000000000..b323ebd5e6b
--- /dev/null
+++ b/dts/bindings/i3c/snps,designware-i3c.yaml
@@ -0,0 +1,30 @@
+# Copyright (C) 2020 Samsung Electronics Co., Ltd.
+# Copyright (C) 2023 Meta Platforms
+# SPDX-License-Identifier: Apache-2.0
+
+description: >
+    This is a binding for the Synopsys I3C interface
+
+compatible: "snps,designware-i3c"
+
+include: i3c-controller.yaml
+
+properties:
+  clocks:
+    required: true
+
+  od-thigh-max-ns:
+    type: int
+    default: 41
+    description: |
+      Maximum high clock pulse length (ns) in Open-Drain mode.
+      The default is value from Section 6.2 of the I3C
+      Specifiction.
+
+  od-tlow-min-ns:
+    type: int
+    default: 200
+    description: |
+      Minimum low clock pulse length (ns) in Open-Drain mode.
+      The default is value from Section 6.2 of the I3C
+      Specifiction.
diff --git a/dts/bindings/ieee802154/nxp,mcxw-ieee802154.yaml b/dts/bindings/ieee802154/nxp,mcxw-ieee802154.yaml
new file mode 100644
index 00000000000..cb76bf63ac8
--- /dev/null
+++ b/dts/bindings/ieee802154/nxp,mcxw-ieee802154.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2025, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP MCXW71 IEEE 802.15.4 node
+
+compatible: "nxp,mcxw-ieee802154"
+
+include: base.yaml
diff --git a/dts/bindings/iio/afe/current-sense-amplifier.yaml b/dts/bindings/iio/afe/current-sense-amplifier.yaml
index 11eda97323c..d12a07fabb4 100644
--- a/dts/bindings/iio/afe/current-sense-amplifier.yaml
+++ b/dts/bindings/iio/afe/current-sense-amplifier.yaml
@@ -45,3 +45,16 @@ properties:
 
       If present the corresponding GPIO must be set to an active level
       to enable the current amplifier.
+
+  enable-calibration:
+    type: boolean
+    description: |
+      Enable calibration of the current sense amplifier.
+      This is used to calibrate the ADC prior to taking measurements.
+
+  zephyr,noise-threshold:
+    type: int
+    default: 0
+    description: |
+     Raw ADC readings below this threshold are treated as noise and
+     reported as 0 uA. The default value of 0 disables the threshold.
diff --git a/dts/bindings/input/cypress,cy8cmbr3xxx.yaml b/dts/bindings/input/cypress,cy8cmbr3xxx.yaml
new file mode 100644
index 00000000000..3b62b5b043f
--- /dev/null
+++ b/dts/bindings/input/cypress,cy8cmbr3xxx.yaml
@@ -0,0 +1,35 @@
+# Copyright (c) 2025 Basalte bv
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Cypress CY8CMBR3002/3102/3106S/3108/3110/3116 capacitive touch sensor
+
+compatible: "cypress,cy8cmbr3xxx"
+
+include: i2c-device.yaml
+
+properties:
+  int-gpios:
+    type: phandle-array
+    required: true
+    description: |
+      The interrupt pin generates an active low pulse signal on
+      any change in the CapSense sensor's status.
+
+  rst-gpios:
+    type: phandle-array
+    required: true
+    description: |
+      The reset pin resets the capsense controller with an active
+      low reset pulse.
+
+  input-codes:
+    type: array
+    required: true
+    description: |
+      Array of input event key codes (INPUT_KEY_* or INPUT_BTN_*).
+
+  proximity-codes:
+    type: array
+    description: |
+      Array of input event key codes (INPUT_KEY_* or INPUT_BTN_*).
diff --git a/dts/bindings/input/espressif,esp32-touch-sensor.yaml b/dts/bindings/input/espressif,esp32-touch-sensor.yaml
index 5bea6081b97..f646563b856 100644
--- a/dts/bindings/input/espressif,esp32-touch-sensor.yaml
+++ b/dts/bindings/input/espressif,esp32-touch-sensor.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Zephyr input touch sensor parent node
+  ESP32 touch sensor input
 
   This defines a group of touch sensors that can generate input events. Each touch
   sensor is defined in a child node of the touch-sensor node and defines a specific key
diff --git a/dts/bindings/input/gpio-keys.yaml b/dts/bindings/input/gpio-keys.yaml
index a04806086fb..884e2542d50 100644
--- a/dts/bindings/input/gpio-keys.yaml
+++ b/dts/bindings/input/gpio-keys.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Zephyr Input GPIO KEYS parent node
+  Group of GPIO-bound input keys.
 
   This defines a group of buttons that can generate input events. Each button
   is defined in a child node of the gpio-keys node and defines a specific key
diff --git a/dts/bindings/input/ite,it51xxx-kbd.yaml b/dts/bindings/input/ite,it51xxx-kbd.yaml
new file mode 100644
index 00000000000..5a334069de0
--- /dev/null
+++ b/dts/bindings/input/ite,it51xxx-kbd.yaml
@@ -0,0 +1,56 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE it51xxx keyboard matrix controller
+
+compatible: "ite,it51xxx-kbd"
+
+include: [kbd-matrix-common.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  wucctrl:
+    type: phandles
+    description: |
+      Configure wakeup controller, this controller is used to set that
+      when the interrupt is triggered in EC low power mode, it can wakeup
+      EC or not. Via this controller, we set the wakeup trigger edge,
+      enable, disable, and clear wakeup status for the specific pin which
+      may be gpio pins or alternate pins.
+
+  kso16-gpios:
+    type: phandle-array
+    required: true
+    description: |
+      The KSO16 pin for the selected port.
+
+  kso17-gpios:
+    type: phandle-array
+    required: true
+    description: |
+      The KSO17 pin for the selected port.
+
+  kso-ignore-mask:
+    type: int
+    default: 0
+    description: |
+      Bitmask of KSO signals to ignore, this can be used to instruct the driver
+      to skip KSO signals between 0 and (col-size - 1) that are used as GPIOs.
+      Default to 0 (no signals masked).
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  row-size:
+    required: true
+
+  col-size:
+    required: true
diff --git a/dts/bindings/input/realtek,rts5912-kbd.yaml b/dts/bindings/input/realtek,rts5912-kbd.yaml
new file mode 100644
index 00000000000..8429ddfa851
--- /dev/null
+++ b/dts/bindings/input/realtek,rts5912-kbd.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2025 Realtek Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Realtek RTS5912 keyboard matrix controller
+
+compatible: "realtek,rts5912-kbd"
+
+include: [kbd-matrix-common.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  row-size:
+    required: true
+
+  col-size:
+    required: true
+
+  kso-ignore-mask:
+    type: int
+    default: 0
diff --git a/dts/bindings/input/st,stm32-tsc.yaml b/dts/bindings/input/st,stm32-tsc.yaml
new file mode 100644
index 00000000000..5e2c1ccfc32
--- /dev/null
+++ b/dts/bindings/input/st,stm32-tsc.yaml
@@ -0,0 +1,121 @@
+# Copyright (c) 2024 Arif Balik <arifbalik@outlook.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 Tocuh Sensing Controller (TSC) driver
+
+compatible: "st,stm32-tsc"
+
+include: [base.yaml, pinctrl-device.yaml, reset-device.yaml]
+
+properties:
+  reg:
+    required: true
+  clocks:
+    required: true
+  resets:
+    required: true
+  interrupts:
+    required: true
+  pinctrl-0:
+    required: true
+  pinctrl-names:
+    required: true
+
+  st,pulse-generator-prescaler:
+    type: int
+    required: true
+    description: |
+      Prescaler for the pulse generator clock (t_pgclk=f_hclk/prescaler).
+      The prescaler is used to generate the charge transfer pulse. The final
+      prescaled value is 2^N where N is the value of this property.
+    enum: [1, 2, 4, 8, 16, 32, 64, 128]
+
+  st,charge-transfer-pulse-high:
+    type: int
+    required: true
+    description: |
+      Number of cycles for the high state of the
+      charge transfer pulse (1 to 16 cycles of t_pgclk).
+    enum: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
+
+  st,charge-transfer-pulse-low:
+    type: int
+    required: true
+    description: |
+      Number of cycles for the low state of the
+      charge transfer pulse (1 to 16 cycles of t_pgclk).
+    enum: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
+
+  st,spread-spectrum:
+    type: boolean
+    description: Spread spectrum enable
+
+  st,spread-spectrum-prescaler:
+    type: int
+    required: true
+    description: Spread spectrum clock prescaler (t_ssclk)
+    enum:
+      - 1
+      - 2
+
+  st,spread-spectrum-deviation:
+    type: int
+    required: true
+    description: Spread spectrum deviation (1 to 128 cycles of t_ssclk)
+
+  st,max-count-value:
+    type: int
+    required: true
+    description: |
+      Max number of charge transfer pulses before max count error is generated.
+      The value of the counter is calculated as 256 * 2^max_count_value.
+    enum: [255, 511, 1023, 2047, 4095, 8191, 16383, 32767]
+
+  st,synced-acquisition:
+    type: boolean
+    description: |
+      Synchronized acquisition enable.
+      Acquisition starts when START bit and signal on sync pin.
+      You have to provide a pinctrl for the sync pin.
+
+  st,syncpol-rising:
+    type: boolean
+    description: Rising synchronization pin polarity, instead of falling
+
+  st,iodef-float:
+    type: boolean
+    description: |
+      Set default state (not acqusition) of all channel I/Os to floating.
+      push-pull down by default.
+
+child-binding:
+  description: STM32 TSC group configuration
+  properties:
+    group:
+      type: int
+      required: true
+      description: Group number (0 to 7)
+      enum: [0, 1, 2, 3, 4, 5, 6, 7]
+
+    channel-ios:
+      type: int
+      required: true
+      description: Channel I/Os to be enabled
+      enum: [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]
+
+    sampling-io:
+      type: int
+      required: true
+      description: Channel to be selected for sampling
+      enum:
+        - 1
+        - 2
+        - 4
+        - 8
+
+    st,use-as-shield:
+      type: boolean
+      description: |
+        Use channel as shield. This configures group but
+        does not enable it for acqusition. channel-io is used
+        as shield pin and can only have values 1, 2, 4 or 8.
diff --git a/dts/bindings/input/tsc-keys.yaml b/dts/bindings/input/tsc-keys.yaml
new file mode 100644
index 00000000000..d3b4cb06c18
--- /dev/null
+++ b/dts/bindings/input/tsc-keys.yaml
@@ -0,0 +1,71 @@
+# Copyright (c) 2024 Arif Balik <arifbalik@outlook.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Input driver for STM32 Tocuh Sensing Controller (TSC).
+
+  This node is a st,stm32-tsc grandchild node and applies filters and
+  calculations to detect an input event on a group which is the child of
+  st,stm32-tsc. For more information see drivers/misc/st,stm32-tsc.yaml
+
+  Example:
+
+  #include <dt-bindings/input/input-event-codes.h>
+
+  &tsc {
+    compatible = "st,stm32-tsc";
+
+    tsc_group6: g6 {
+      ...
+      ts1 {
+        compatible = "tsc-keys";
+        sampling-interval-ms = <10>;
+        oversampling = <10>;
+        noise-threshold = <50>;
+        zephyr,code = <INPUT_KEY_0>;
+      };
+    };
+  };
+
+compatible: "tsc-keys"
+
+include:
+  - name: base.yaml
+    property-allowlist:
+      - compatible
+      - zephyr,deferred-init
+      - label
+      - status
+
+properties:
+  sampling-interval-ms:
+    type: int
+    required: true
+    description: |
+      Sampling interval in milliseconds.
+  oversampling:
+    type: int
+    required: true
+    description: |
+      Over sampling factor. The driver will take the average of the samples
+      taken in the sampling interval and compare it with the previous sample.
+      Larger values will reduce the noise but will increase the latency. The
+      default value is 10 so the slope will be calculated every
+      10 * sampling-interval-ms milliseconds.
+  noise-threshold:
+    type: int
+    required: true
+    description: |
+      This value will be used to reject the noise for both
+      directions of the slope.
+  sticky-key-timeout-ms:
+    type: int
+    required: true
+    description: |
+      Time in milliseconds to wait before releasing a key. By default a release
+      event will be generated after 10 seconds of the last press event if
+      the key is still pressed.
+  zephyr,code:
+    type: int
+    required: true
+    description: Key code to emit.
diff --git a/dts/bindings/input/zephyr,input-sdl-touch.yaml b/dts/bindings/input/zephyr,input-sdl-touch.yaml
index 8248334e4f7..cd0a6f50f81 100644
--- a/dts/bindings/input/zephyr,input-sdl-touch.yaml
+++ b/dts/bindings/input/zephyr,input-sdl-touch.yaml
@@ -4,3 +4,8 @@
 description: SDL based emulated touch panel
 
 compatible: "zephyr,input-sdl-touch"
+
+properties:
+  display:
+    type: phandle
+    description: Handle to the display that the input events are raised for
diff --git a/dts/bindings/interrupt-controller/arm,gic-v3.yaml b/dts/bindings/interrupt-controller/arm,gic-v3.yaml
index 8fc5851d62c..fed263f6273 100644
--- a/dts/bindings/interrupt-controller/arm,gic-v3.yaml
+++ b/dts/bindings/interrupt-controller/arm,gic-v3.yaml
@@ -1,7 +1,53 @@
+#
+# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+#
 # SPDX-License-Identifier: Apache-2.0
+#
 
-description: ARM Generic Interrupt Controller v3
+description: |
+  ARM Generic Interrupt Controller v3
+
+  Examples for GICv3 devicetree nodes:
+
+    gic: interrupt-controller@2cf00000 {
+      compatible = "arm,gic-v3", "arm,gic";
+      reg = <0x2f000000 0x10000>,  /* GICD */
+            <0x2f100000 0x200000>;  /* GICR */
+      interrupt-controller;
+      #interrupt-cells = <3>;
+      status = "okay";
+    };
+
+    gic: interrupt-controller@2c010000 {
+      compatible = "arm,gic-v3", "arm,gic";
+      redistributor-stride = <0x40000>;  /* 256kB stride */
+      redistributor-regions = <2>;
+      reg = <0x2c010000 0x10000>,  /* GICD */
+            <0x2d000000 0x800000>,  /* GICR 1: CPUs 0-31 */
+            <0x2e000000 0x800000>;  /* GICR 2: CPUs 32-63 */
+      interrupt-controller;
+      #interrupt-cells = <4>;
+      status = "okay";
+    };
 
 compatible: arm,gic-v3
 
 include: arm,gic.yaml
+
+properties:
+  redistributor-stride:
+    type: int
+    description:
+      If using padding pages, specifies the stride of consecutive
+      redistributors which is the distance between consecutive redistributors in
+      memory. Must be a multiple of 64kB. Required if the distance between
+      redistributors is not the default 128kB.
+
+  redistributor-regions:
+    type: int
+    description:
+      The number of independent contiguous regions occupied by the redistributors.
+      The term "regions" refers to distinct memory segments or areas allocated
+      for redistributors within the system memory. The number of redistributor
+      regions and their sizes are hardware-specific. Required if more than one
+      such region is present.
diff --git a/dts/bindings/interrupt-controller/ite,it51xxx-intc.yaml b/dts/bindings/interrupt-controller/ite,it51xxx-intc.yaml
new file mode 100644
index 00000000000..3b22729b1b4
--- /dev/null
+++ b/dts/bindings/interrupt-controller/ite,it51xxx-intc.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE Interrupt controller
+compatible: "ite,it51xxx-intc"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+
+interrupt-cells:
+  - irq
+  - flags
diff --git a/dts/bindings/interrupt-controller/ite,it51xxx-wuc-map.yaml b/dts/bindings/interrupt-controller/ite,it51xxx-wuc-map.yaml
new file mode 100644
index 00000000000..4d32305e609
--- /dev/null
+++ b/dts/bindings/interrupt-controller/ite,it51xxx-wuc-map.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE Wake-Up Controller (WUC) mapping child node
+
+compatible: "ite,it51xxx-wuc-map"
+
+child-binding:
+  description: Child node to present the mapping between input of WUC and its source device
+  properties:
+    wucs:
+      type: phandle-array
+      required: true
diff --git a/dts/bindings/interrupt-controller/ite,it51xxx-wuc.yaml b/dts/bindings/interrupt-controller/ite,it51xxx-wuc.yaml
new file mode 100644
index 00000000000..fa32f96b85b
--- /dev/null
+++ b/dts/bindings/interrupt-controller/ite,it51xxx-wuc.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE Wake-Up Controller (WUC)
+compatible: "ite,it51xxx-wuc"
+
+include: [base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  wakeup-controller:
+    type: boolean
+    description: |
+      conveys that this node is a wakeup controller
+
+  both-edge-trigger:
+    type: boolean
+    description: |
+      Rising-edge or falling-edge triggered is selected.
+
+  "#wuc-cells":
+    type: int
+    required: true
+    description: |
+      number of items to expect in a wakeup controller specifier
+    const: 1
+
+wuc-cells:
+  - mask
diff --git a/dts/bindings/interrupt-controller/renesas,ra-interrupt-controller-unit.yaml b/dts/bindings/interrupt-controller/renesas,ra-interrupt-controller-unit.yaml
deleted file mode 100644
index dd13f876cdc..00000000000
--- a/dts/bindings/interrupt-controller/renesas,ra-interrupt-controller-unit.yaml
+++ /dev/null
@@ -1,20 +0,0 @@
-# Copyright (c) 2023, TOKITA Hiroshi
-# SPDX-License-Identifier: Apache-2.0
-
-description: Renesas RA series interrupt controller unit
-
-compatible: "renesas,ra-interrupt-controller-unit"
-
-include: [interrupt-controller.yaml, base.yaml]
-
-properties:
-  reg:
-    required: true
-
-  "#interrupt-cells":
-    const: 3
-
-interrupt-cells:
-  - irq
-  - priority
-  - flags
diff --git a/dts/bindings/interrupt-controller/renesas,rz-ext-irq.yaml b/dts/bindings/interrupt-controller/renesas,rz-ext-irq.yaml
new file mode 100644
index 00000000000..2777e3bc65e
--- /dev/null
+++ b/dts/bindings/interrupt-controller/renesas,rz-ext-irq.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RZ external interrupt controller
+
+compatible: "renesas,rz-ext-irq"
+
+include: [interrupt-controller.yaml, base.yaml, pinctrl-device.yaml]
+
+properties:
+  "#interrupt-cells":
+    const: 2
+
+  trigger-type:
+    required: true
+    type: string
+    description: |
+      Indicates the condition that will trigger an interrupt when detected.
+    enum:
+      - "falling"
+      - "rising"
+      - "both_edges"
+      - "low_level"
diff --git a/dts/bindings/interrupt-controller/riscv,clic.yaml b/dts/bindings/interrupt-controller/riscv,clic.yaml
new file mode 100644
index 00000000000..73d95625db0
--- /dev/null
+++ b/dts/bindings/interrupt-controller/riscv,clic.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2025 Andes Technology Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: RISC-V core local interrupt controller
+
+compatible: "riscv,clic"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  "#interrupt-cells":
+    const: 2
+
+interrupt-cells:
+  - irq
+  - priority
diff --git a/dts/bindings/timer/sifive,clint0.yaml b/dts/bindings/interrupt-controller/sifive,clint0.yaml
similarity index 100%
rename from dts/bindings/timer/sifive,clint0.yaml
rename to dts/bindings/interrupt-controller/sifive,clint0.yaml
diff --git a/dts/bindings/interrupt-controller/st,stm32-exti.yaml b/dts/bindings/interrupt-controller/st,stm32-exti.yaml
index c25e1bf6001..3cb8b758682 100644
--- a/dts/bindings/interrupt-controller/st,stm32-exti.yaml
+++ b/dts/bindings/interrupt-controller/st,stm32-exti.yaml
@@ -1,4 +1,4 @@
-description: STMicroelectronics STM32 family External Interrupt Controller
+description: STM32 External Interrupt Controller
 
 compatible: "st,stm32-exti"
 
diff --git a/dts/bindings/interrupt-controller/st,stm32g0-exti.yaml b/dts/bindings/interrupt-controller/st,stm32g0-exti.yaml
index 6f8704416dd..06b778a7371 100644
--- a/dts/bindings/interrupt-controller/st,stm32g0-exti.yaml
+++ b/dts/bindings/interrupt-controller/st,stm32g0-exti.yaml
@@ -3,7 +3,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-        STM32 controller
+        STM32G0 External Interrupt Controller
+
         This compatible stands for all interrupt-controller blocks with two
         dedicated Rising and Falling interrupt pending registers.
 
diff --git a/dts/bindings/interrupt-controller/st,stm32h7rs-exti.yaml b/dts/bindings/interrupt-controller/st,stm32h7rs-exti.yaml
index 1e441fb47b8..ad981acae46 100644
--- a/dts/bindings/interrupt-controller/st,stm32h7rs-exti.yaml
+++ b/dts/bindings/interrupt-controller/st,stm32h7rs-exti.yaml
@@ -3,7 +3,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-        STM32 controller
+        STM32H7RS External Interrupt Controller
+
         This compatible stands for the stm32H7RS interrupt-controller block
         with two dedicated Rising and Falling interrupt pending registers
 
diff --git a/dts/bindings/ipc/zephyr,ipc-icmsg.yaml b/dts/bindings/ipc/zephyr,ipc-icmsg.yaml
index 13a9e2b84b6..d1730dddb0f 100644
--- a/dts/bindings/ipc/zephyr,ipc-icmsg.yaml
+++ b/dts/bindings/ipc/zephyr,ipc-icmsg.yaml
@@ -21,6 +21,21 @@ properties:
     required: true
     type: phandle
 
+  unbound:
+    type: string
+    enum:
+      - disable
+      - enable
+      - detect
+    default: disable
+    description: |
+      Select unbound() callback mode. The callback can be enabled or disabled with the
+      "enable" and "disable" option respectively. This functionality requires session
+      number handshake procedure on both sides, so you cannot set "enable" on one side
+      and "disable" on the other. The "detect" mode detects if the remote side
+      supports handshake procedure and adjusts its behavior accordingly. The
+      "detect" mode is possible only if "dcache-alignment" is at least 8 bytes.
+
   dcache-alignment:
     type: int
     description: |
diff --git a/dts/bindings/kscan/kscan.yaml b/dts/bindings/kscan/kscan.yaml
deleted file mode 100644
index e30042d935e..00000000000
--- a/dts/bindings/kscan/kscan.yaml
+++ /dev/null
@@ -1,8 +0,0 @@
-# Copyright (c) 2019, Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-# Common properties for keyboard matrix devices
-
-include: base.yaml
-
-bus: kscan
diff --git a/dts/bindings/kscan/zephyr,kscan-input.yaml b/dts/bindings/kscan/zephyr,kscan-input.yaml
deleted file mode 100644
index b8880df6d00..00000000000
--- a/dts/bindings/kscan/zephyr,kscan-input.yaml
+++ /dev/null
@@ -1,23 +0,0 @@
-# Copyright 2023 Google LLC
-# SPDX-License-Identifier: Apache-2.0
-
-description: |
-  Input to kscan adapter.
-
-  Allows using an input device with the kscan API. Define as a child node of
-  the input device, for example
-
-  chosen {
-    zephyr,keyboard-scan = &kscan_input;
-  };
-
-  ft5336@38 {
-    ...
-    kscan_input: kscan-input {
-      compatible = "zephyr,kscan-input";
-    };
-  };
-
-compatible: "zephyr,kscan-input"
-
-include: kscan.yaml
diff --git a/dts/bindings/led/gpio-leds.yaml b/dts/bindings/led/gpio-leds.yaml
index 6a5d37b929a..3589b394c8c 100644
--- a/dts/bindings/led/gpio-leds.yaml
+++ b/dts/bindings/led/gpio-leds.yaml
@@ -2,9 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  This allows you to define a group of LEDs. Each LED in the group is
-  controlled by a GPIO. Each LED is defined in a child node of the
-  gpio-leds node.
+  Group of GPIO-controlled LEDs.
+
+  Each LED is defined in a child node of the gpio-leds node.
 
   Here is an example which defines three LEDs in the node /leds:
 
diff --git a/dts/bindings/led/pwm-leds.yaml b/dts/bindings/led/pwm-leds.yaml
index e9e9d131ee6..c5619e03883 100644
--- a/dts/bindings/led/pwm-leds.yaml
+++ b/dts/bindings/led/pwm-leds.yaml
@@ -1,7 +1,10 @@
 # Copyright (c) 2018, Linaro Limited
 # SPDX-License-Identifier: Apache-2.0
 
-description: PWM LEDs parent node
+description: |
+  Group of PWM-controlled LEDs.
+
+  Each LED is defined in a child node of the pwm-leds node.
 
 compatible: "pwm-leds"
 
diff --git a/dts/bindings/led/ti,lp50xx.yaml b/dts/bindings/led/ti,lp50xx.yaml
index fb06d59f7f9..91511dbd303 100644
--- a/dts/bindings/led/ti,lp50xx.yaml
+++ b/dts/bindings/led/ti,lp50xx.yaml
@@ -8,7 +8,7 @@ properties:
     type: phandle-array
     description: |
       GPIO to use to enable/disable the controller.
-  max_curr_opt:
+  max-curr-opt:
     type: boolean
     description: |
       If enabled the maximum current output is set to 35 mA (25.5 mA else).
diff --git a/dts/bindings/led/x-powers,axp192-led.yaml b/dts/bindings/led/x-powers,axp192-led.yaml
new file mode 100644
index 00000000000..b31012f8793
--- /dev/null
+++ b/dts/bindings/led/x-powers,axp192-led.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2024 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  AXP192 LED controller
+
+  The AXP192 has one LED can automatically display error or charging status,
+  or be controlled by software.
+
+compatible: "x-powers,axp192-led"
+
+on-bus: axp192
+
+properties:
+  x-powers,mode:
+    type: string
+    enum:
+      - "by-reg"
+      - "by-charge"
+    description:
+      Select the LED control method.
+      If you select "by-reg", you can control it from software.
+      Please refer to the datasheet for details on "by-charge".
diff --git a/dts/bindings/led/x-powers,axp2101-led.yaml b/dts/bindings/led/x-powers,axp2101-led.yaml
new file mode 100644
index 00000000000..75e1d181680
--- /dev/null
+++ b/dts/bindings/led/x-powers,axp2101-led.yaml
@@ -0,0 +1,24 @@
+# Copyright (c) 2024 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  AXP2101 LED controller
+
+  The AXP2101 has one LED can automatically display error or charging status,
+  or be controlled by software.
+
+compatible: "x-powers,axp2101-led"
+
+on-bus: axp2101
+
+properties:
+  x-powers,mode:
+    type: string
+    enum:
+      - "type-a"
+      - "type-b"
+      - "by-reg"
+    description:
+      Select the LED control method.
+      If you select "by-reg", you can control it from software.
+      Please refer to the datasheet for details on "type-a" and "type-b".
diff --git a/dts/bindings/led_strip/worldsemi,ws2812-rpi_pico-pio.yaml b/dts/bindings/led_strip/worldsemi,ws2812-rpi_pico-pio.yaml
index d0c8d38e63c..c87296acf05 100644
--- a/dts/bindings/led_strip/worldsemi,ws2812-rpi_pico-pio.yaml
+++ b/dts/bindings/led_strip/worldsemi,ws2812-rpi_pico-pio.yaml
@@ -44,7 +44,7 @@ properties:
 
 child-binding:
   description: |
-    Worldsemi WS2812 or compatible LED strip driver based on RaspberryPi Pico's PIO
+    Worldsemi WS2812 or compatible LED strip driver based on Raspberry Pi Pico's PIO
     The LED strip node can put up to 4 instances under a single PIO node.
 
   include: ws2812-gpio.yaml
diff --git a/dts/bindings/lora/st,stm32wl-subghz-radio.yaml b/dts/bindings/lora/st,stm32wl-subghz-radio.yaml
index 4066c1bcb2c..1eaa264cf28 100644
--- a/dts/bindings/lora/st,stm32wl-subghz-radio.yaml
+++ b/dts/bindings/lora/st,stm32wl-subghz-radio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021 Fabio Baltieri
 # SPDX-License-Identifier: Apache-2.0
 
-description: STM32WL SUBGHZ Radio
+description: STM32WL Sub-GHz Radio
 
 compatible: "st,stm32wl-subghz-radio"
 
diff --git a/dts/bindings/mbox/andestech,mbox-plic-sw.yaml b/dts/bindings/mbox/andestech,mbox-plic-sw.yaml
index 3aa45bfd3b6..0352f6a8e93 100644
--- a/dts/bindings/mbox/andestech,mbox-plic-sw.yaml
+++ b/dts/bindings/mbox/andestech,mbox-plic-sw.yaml
@@ -4,8 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-description: |
-  This is a representation of AndesTech MBOX PLIC-SW node
+description: AndesTech MBOX PLIC-SW
 
 compatible: "andestech,mbox-plic-sw"
 
diff --git a/dts/bindings/mbox/arm,mhuv3.yaml b/dts/bindings/mbox/arm,mhuv3.yaml
new file mode 100644
index 00000000000..7b6ceee1736
--- /dev/null
+++ b/dts/bindings/mbox/arm,mhuv3.yaml
@@ -0,0 +1,23 @@
+# SPDX-FileCopyrightText: <text>Copyright 2024 Arm Limited and/or its
+# affiliates <open-source-office@arm.com></text>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+description: ARM MHUv3 (Message Handling Unit v3)
+
+compatible: "arm,mhuv3"
+
+include: [base.yaml, mailbox-controller.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  interrupt-names:
+    required: true
+
+mbox-cells:
+  - channel
diff --git a/dts/bindings/mbox/espressif,mbox-esp32.yaml b/dts/bindings/mbox/espressif,mbox-esp32.yaml
index 7b2065db554..31020d23c1d 100644
--- a/dts/bindings/mbox/espressif,mbox-esp32.yaml
+++ b/dts/bindings/mbox/espressif,mbox-esp32.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 Felipe Neves
 # SPDX-License-Identifier: Apache-2.0
 
-description: ESP32 soft mailbox bindings
+description: ESP32 soft mailbox
 
 compatible: "espressif,mbox-esp32"
 
diff --git a/dts/bindings/mbox/linaro,ivshmem-mbox.yaml b/dts/bindings/mbox/linaro,ivshmem-mbox.yaml
index d3b42c597db..977fd515d85 100644
--- a/dts/bindings/mbox/linaro,ivshmem-mbox.yaml
+++ b/dts/bindings/mbox/linaro,ivshmem-mbox.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 Felipe Neves
 # SPDX-License-Identifier: Apache-2.0
 
-description: Inter VM shared memory based mailbox binding
+description: Inter VM shared memory based mailbox
 
 compatible: "linaro,ivshmem-mbox"
 
diff --git a/dts/bindings/mbox/renesas,rz-mhu-mbox.yaml b/dts/bindings/mbox/renesas,rz-mhu-mbox.yaml
new file mode 100644
index 00000000000..da4e6cf00a3
--- /dev/null
+++ b/dts/bindings/mbox/renesas,rz-mhu-mbox.yaml
@@ -0,0 +1,45 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas MHU MBOX
+
+compatible: "renesas,rz-mhu-mbox"
+
+include: [base.yaml, mailbox-controller.yaml]
+
+properties:
+  channel:
+    type: int
+    required: true
+    description: the channel number of the underlying MHU unit used for MBOX.
+
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  tx-mask:
+    type: int
+    required: true
+    description: TX supported channels mask
+
+  rx-mask:
+    type: int
+    required: true
+    description: RX supported channels mask
+
+  channels-count:
+    type: int
+    required: true
+    description: number of channels supported for a MBOX instance.
+
+  shared-memory:
+    type: phandle
+    description: |
+      Reference to the shared memory region that is going
+      to be used for the buffer communication between
+      MHU units. No data will be transmitted if not set.
+
+mbox-cells:
+  - channel
diff --git a/dts/bindings/mbox/ti,omap-mailbox.yaml b/dts/bindings/mbox/ti,omap-mailbox.yaml
new file mode 100644
index 00000000000..1dd6d64b552
--- /dev/null
+++ b/dts/bindings/mbox/ti,omap-mailbox.yaml
@@ -0,0 +1,23 @@
+# Copyright 2024 Texas Instruments Incorporated.
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI OMAP MAILBOX
+
+compatible: "ti,omap-mailbox"
+
+include: [base.yaml, mailbox-controller.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  usr-id:
+    type: int
+    required: true
+    description: User ID for processor
+
+mbox-cells:
+  - channel
diff --git a/dts/bindings/mdio/espressif,esp32-mdio.yaml b/dts/bindings/mdio/espressif,esp32-mdio.yaml
index d869d656da5..f181a7810b7 100644
--- a/dts/bindings/mdio/espressif,esp32-mdio.yaml
+++ b/dts/bindings/mdio/espressif,esp32-mdio.yaml
@@ -1,10 +1,16 @@
 # Copyright (c) 2022 Grant Ramsay <grant.ramsay@hotmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
-description: ESP32 MDIO Driver node
+description: ESP32 MDIO controller
 
 compatible: "espressif,esp32-mdio"
 
 include:
   - name: mdio-controller.yaml
   - name: pinctrl-device.yaml
+
+properties:
+  ref-clk-output-gpios:
+    type: phandle-array
+    description: |
+      GPIO to output RMII Clock.
diff --git a/dts/bindings/mdio/microchip,lan865x-mdio.yaml b/dts/bindings/mdio/microchip,lan865x-mdio.yaml
new file mode 100644
index 00000000000..9940354b1e1
--- /dev/null
+++ b/dts/bindings/mdio/microchip,lan865x-mdio.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: LAN865X MDIO Driver node
+
+compatible: "microchip,lan865x-mdio"
+
+include: mdio-controller.yaml
+
+on-bus: lan865x
diff --git a/dts/bindings/mdio/sensry,sy1xx-mdio.yaml b/dts/bindings/mdio/sensry,sy1xx-mdio.yaml
new file mode 100644
index 00000000000..978d6b167c9
--- /dev/null
+++ b/dts/bindings/mdio/sensry,sy1xx-mdio.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+description: Sensry SY1XX MDIO Driver node
+
+compatible: "sensry,sy1xx-mdio"
+
+include: [base.yaml, mdio-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
diff --git a/dts/bindings/mdio/st,stm32-mdio.yaml b/dts/bindings/mdio/st,stm32-mdio.yaml
index e536ed1c23a..5a302d6b65e 100644
--- a/dts/bindings/mdio/st,stm32-mdio.yaml
+++ b/dts/bindings/mdio/st,stm32-mdio.yaml
@@ -2,7 +2,7 @@
 # Copyright (c) 2024 Analog Devices Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-description: ST MDIO Features
+description: STM32 MDIO Controller
 
 compatible: "st,stm32-mdio"
 
diff --git a/dts/bindings/mdio/xilinx,axi-ethernet-1.00.a-mdio.yaml b/dts/bindings/mdio/xilinx,axi-ethernet-1.00.a-mdio.yaml
new file mode 100644
index 00000000000..632cae74af0
--- /dev/null
+++ b/dts/bindings/mdio/xilinx,axi-ethernet-1.00.a-mdio.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 CISPA Helmholtz Center for Information Security
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for MDIO controllers
+
+include: mdio-controller.yaml
+
+compatible: xlnx,axi-ethernet-1.00.a-mdio
+
+description: MDIO interface of Xilinx AXI 1G/2.5G Ethernet Subsystem.
+
+properties:
+  reg:
+    type: array
+    description: |
+      Control registers of the MDIO device are also used for the Ethernet MAC controller.
+      Thus, both devices should have a parent node with compatible "xlnx,axi-ethernet-subsystem-7.2"
+      which defines the reg property, and MAC and MDIO should NOT have a reg property.
diff --git a/dts/bindings/memory-controllers/espressif,esp32-psram.yaml b/dts/bindings/memory-controllers/espressif,esp32-psram.yaml
new file mode 100644
index 00000000000..cdfede604dd
--- /dev/null
+++ b/dts/bindings/memory-controllers/espressif,esp32-psram.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ESP32 pseudo-static RAM controller
+
+compatible: "espressif,esp32-psram"
+
+include: base.yaml
+
+properties:
+  size:
+    type: int
+    required: true
diff --git a/dts/bindings/memory-controllers/nxp,flexram.yaml b/dts/bindings/memory-controllers/nxp,flexram.yaml
index 76248c06394..5482b26d8ea 100644
--- a/dts/bindings/memory-controllers/nxp,flexram.yaml
+++ b/dts/bindings/memory-controllers/nxp,flexram.yaml
@@ -1,7 +1,44 @@
 # Copyright 2023 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-description: NXP FlexRAM on-chip ram controller
+description: |
+  NXP FlexRAM on-chip ram controller
+  If the flexram,bank-spec property is specified, then the flexram will be
+  dynamically reconfigured to the configuration specified at runtime. An
+  example to configure the flexram dynamically using the
+  flexram,bank-spec property for rt1060 is as follows:
+
+  &itcm {
+          reg = < 0x0 DT_SIZE_K(64) >;
+  };
+  &dtcm {
+          reg = < 0x20000000 DT_SIZE_K(384) >;
+  };
+  &ocram {
+          reg = < 0x20280000 DT_SIZE_K(64) >;
+  };
+  &flexram {
+          flexram,bank-spec = <FLEXRAM_OCRAM>,
+                              <FLEXRAM_OCRAM>,
+                              <FLEXRAM_DTCM>,
+                              <FLEXRAM_DTCM>,
+                              <FLEXRAM_DTCM>,
+                              <FLEXRAM_DTCM>,
+                              <FLEXRAM_DTCM>,
+                              <FLEXRAM_DTCM>,
+                              <FLEXRAM_ITCM>,
+                              <FLEXRAM_ITCM>,
+                              <FLEXRAM_DTCM>,
+                              <FLEXRAM_DTCM>,
+                              <FLEXRAM_DTCM>,
+                              <FLEXRAM_DTCM>,
+                              <FLEXRAM_DTCM>,
+                              <FLEXRAM_DTCM>;
+  };
+
+  This will configure the flexram for 384K of DTCM, 64K of ITCM,
+  and 64K of OCRAM.
+
 
 include: base.yaml
 
diff --git a/dts/bindings/memory-controllers/realtek,rts5912-bbram.yaml b/dts/bindings/memory-controllers/realtek,rts5912-bbram.yaml
new file mode 100644
index 00000000000..324b56b195e
--- /dev/null
+++ b/dts/bindings/memory-controllers/realtek,rts5912-bbram.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2025, Realtek, SIBG-SD7
+# SPDX-License-Identifier: Apache-2.0
+
+description: Realtek, RTS5912 Battery Backed RAM node
+
+compatible: "realtek,rts5912-bbram"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
diff --git a/dts/bindings/memory-controllers/st,stm32-xspi-psram.yaml b/dts/bindings/memory-controllers/st,stm32-xspi-psram.yaml
new file mode 100644
index 00000000000..a4514e536bc
--- /dev/null
+++ b/dts/bindings/memory-controllers/st,stm32-xspi-psram.yaml
@@ -0,0 +1,138 @@
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32 XSPI PSRAM.
+
+compatible: "st,stm32-xspi-psram"
+
+include: [base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  fixed-latency:
+    type: boolean
+    description: |
+      Read latency type: variable if not set, fixed if set.
+
+  read-latency:
+    type: int
+    default: 2
+    description: |
+      Read latency code
+      - 0: LCx2 3 / Fmax 66 MHz
+      - 1: LCx2 4 / Fmax 109 MHz
+      - 2: LCx2 5 / Fmax 133 MHz
+      - 3: LCx2 6 / Fmax 166 MHz
+      - 4: LCx2 7 / Fmax 200 MHz
+    enum:
+      - 0
+      - 1
+      - 2
+      - 3
+      - 4
+
+  drive-strength:
+    type: int
+    default: 0
+    description: |
+      Drive strength code:
+      - 0: Full
+      - 1: Half
+      - 2: 1/4
+      - 3: 1/8
+    enum:
+      - 0
+      - 1
+      - 2
+      - 3
+
+  write-latency:
+    type: int
+    default: 2
+    description: |
+      Write latency code:
+      - 0: WLC 3 / Fmax 66 MHz
+      - 4: WLC 4 / Fmax 109 MHz
+      - 2: WLC 5 / Fmax 133 MHz
+      - 5: WLC 6 / Fmax 166 MHz
+      - 1: WLC 7 / Fmax 200 MHz
+    enum:
+      - 0
+      - 1
+      - 2
+      - 4
+      - 5
+
+  refresh-rate:
+    type: int
+    default: 0
+    description: |
+      - 0: Always 4x refresh
+      - 1: Enables 1x refesh when temperature allows
+      - 3: Enables 0.5x refresh when temperature allows
+    enum:
+      - 0
+      - 1
+      - 3
+
+  pasr:
+    type: int
+    default: 0
+    description: |
+      Refresh coverage:
+      - 0: Full array
+      - 1: Bottom 1/2 array
+      - 2: Bottom 1/4 array
+      - 3: Bottom 1/8 array
+      - 4: None
+      - 5: Top 1/2 array
+      - 6: Top 1/4 array
+      - 7: Top 1/8 array
+    enum:
+      - 0
+      - 1
+      - 2
+      - 3
+      - 4
+      - 5
+      - 6
+      - 7
+
+  io-x16-mode:
+    type: boolean
+    description: |
+      Mode is x8 if not set, and x16 if set.
+
+  rbx:
+    type: boolean
+    description: |
+      If not enabled, reads stay within page (row) boundary.
+      If enabled, allows reads cross page (row) boundary.
+
+  burst-length:
+    type: int
+    default: 1
+    description: |
+      Burst length:
+      0: 16 Byte/Word Wrap
+      1: 32 Byte/Word Wrap
+      2: 64 Byte/Word Wrap
+      3: 2K Byte/1K Word Wrap
+    enum:
+      - 0
+      - 1
+      - 2
+      - 3
+
+  burst-type-hybrid-wrap:
+    type: boolean
+    description: |
+      If not enabled, burst-length sets the burst address space in which the
+      device will continually wrap within.
+      If enabled, the device will burst through the initial wrapped burst length
+      once, then continue to burst incrementally up to maximum column address
+      (2K in X8 mode/1K in X16 mode) before wrapping around within the entire
+      column address space
diff --git a/dts/bindings/memory-controllers/st,stm32h7-fmc.yaml b/dts/bindings/memory-controllers/st,stm32h7-fmc.yaml
index 89fa3bf2a47..a0d27b01bca 100644
--- a/dts/bindings/memory-controllers/st,stm32h7-fmc.yaml
+++ b/dts/bindings/memory-controllers/st,stm32h7-fmc.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32 Flexible Memory Controller (FMC).
+  STM32H7 Flexible Memory Controller (FMC).
 
   The FMC allows to interface with static-memory mapped external devices such as
   SRAM, NOR Flash, NAND Flash, SDRAM...
diff --git a/dts/bindings/mfd/adi,max22017.yaml b/dts/bindings/mfd/adi,max22017.yaml
new file mode 100644
index 00000000000..06bf2d8a639
--- /dev/null
+++ b/dts/bindings/mfd/adi,max22017.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2024 Analog Devices Inc.
+# Copyright (c) 2024 BayLibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+include: spi-device.yaml
+
+description: Analog MAX22017 DAC/GPIO chip common properties
+
+properties:
+  rst-gpios:
+    description: Reset pin for max22017.
+    type: phandle-array
+
+  crc-mode:
+    description: Enables CRC over SPI.
+    type: boolean
+
+  int-gpios:
+    description: Interrupt gpio
+    type: phandle-array
+
+compatible: "adi,max22017"
diff --git a/dts/bindings/mfd/adi,maxq10xx.yaml b/dts/bindings/mfd/adi,maxq10xx.yaml
new file mode 100644
index 00000000000..2db03be3dae
--- /dev/null
+++ b/dts/bindings/mfd/adi,maxq10xx.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Vogl Electronic GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: ADI MAXQ10XX
+
+compatible: "adi,maxq10xx"
+
+include: spi-device.yaml
diff --git a/dts/bindings/mfd/ambiq,iom.yaml b/dts/bindings/mfd/ambiq,iom.yaml
new file mode 100644
index 00000000000..a0d011bc89f
--- /dev/null
+++ b/dts/bindings/mfd/ambiq,iom.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2025 Ambiq Micro Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Ambiq SPI/I2C controller common properties
+
+compatible: "ambiq,iom"
+
+include: [base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
diff --git a/dts/bindings/mfd/ite,it8801-mfd.yaml b/dts/bindings/mfd/ite,it8801-mfd.yaml
index e16c1474f82..fd69ec5a350 100644
--- a/dts/bindings/mfd/ite,it8801-mfd.yaml
+++ b/dts/bindings/mfd/ite,it8801-mfd.yaml
@@ -51,6 +51,7 @@ properties:
 
   irq-gpios:
     type: phandle-array
+    required: true
     description: |
       An interrupt can be asserted on SMB_INT# pin to notify
       the host-side since an effective interrupt occurs.
diff --git a/dts/bindings/mfd/nxp,pf1550.yaml b/dts/bindings/mfd/nxp,pf1550.yaml
new file mode 100644
index 00000000000..53f6cdf2e23
--- /dev/null
+++ b/dts/bindings/mfd/nxp,pf1550.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Arduino SA
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP PF1550
+
+compatible: "nxp,pf1550"
+
+include: i2c-device.yaml
+
+properties:
+  reg:
+    required: true
diff --git a/dts/bindings/mfd/x-powers,axp192.yaml b/dts/bindings/mfd/x-powers,axp192.yaml
index 44fdbac3024..ec68f71bcd1 100644
--- a/dts/bindings/mfd/x-powers,axp192.yaml
+++ b/dts/bindings/mfd/x-powers,axp192.yaml
@@ -7,6 +7,8 @@ compatible: "x-powers,axp192"
 
 include: i2c-device.yaml
 
+bus: axp192
+
 properties:
   reg:
     required: true
diff --git a/dts/bindings/mfd/x-powers,axp2101.yaml b/dts/bindings/mfd/x-powers,axp2101.yaml
new file mode 100644
index 00000000000..de51277ba3a
--- /dev/null
+++ b/dts/bindings/mfd/x-powers,axp2101.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2024 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+description: X-Powers AXP2101
+
+compatible: "x-powers,axp2101"
+
+include: i2c-device.yaml
+
+bus: axp2101
+
+properties:
+  reg:
+    required: true
diff --git a/dts/bindings/mipi-dbi/nxp,mipi-dbi-dcnano-lcdif.yaml b/dts/bindings/mipi-dbi/nxp,mipi-dbi-dcnano-lcdif.yaml
new file mode 100644
index 00000000000..4600e88000a
--- /dev/null
+++ b/dts/bindings/mipi-dbi/nxp,mipi-dbi-dcnano-lcdif.yaml
@@ -0,0 +1,85 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  DBI settings for NXP DCnano LCD controller. DCNano is used in DPI mode by default,
+  when used in DBI mode the compatible need to change in example overlay. For example:
+
+  &lcdif {
+      compatible = "nxp,mipi-dbi-dcnano-lcdif";
+      clock-frequency = <279000000>;
+      wr-period = <14>;
+      wr-assert = <6>;
+      wr-deassert = <13>;
+      cs-assert = <1>;
+      cs-deassert = <4>;
+  };
+
+compatible: "nxp,mipi-dbi-dcnano-lcdif"
+
+include: [base.yaml]
+
+properties:
+  clock-frequency:
+    type: int
+    required: true
+    description: |
+      The DBI clock source frequency.
+
+  reset-gpios:
+    type: phandle-array
+    description: |
+      Reset GPIO pin.
+
+  divider:
+    type: int
+    description: |
+      Divider of the DBI clock source frequency, the final DBI frequency is
+      clock-frequency / divider.
+
+  wr-period:
+    type: int
+    required: true
+    description: |
+      How many clock cycles does one write cycle take.
+
+  wr-assert:
+    type: int
+    required: true
+    description: |
+      At which clock cycle to assert E signal for TypeA_ClockedE, or WRX signal for TypeB.
+
+  wr-deassert:
+    type: int
+    required: true
+    description: |
+      At which clock cycle to deassert E signal for TypeA_ClockedE, or WRX signal for TypeB.
+
+  cs-assert:
+    type: int
+    required: true
+    description: |
+      At which clock cycle to assert CSX signal for TypeA_FixedE or TypeB.
+
+  cs-deassert:
+    type: int
+    required: true
+    description: |
+      At which clock cycle to deassert CSX signal for TypeA_FixedE or TypeB.
+
+  endian:
+    type: string
+    description: |
+      Input data endian mode.
+    enum:
+      - "no-swap"
+      - "half-word"
+      - "word"
+
+  swizzle:
+    type: string
+    description: |
+      Bus data output order.
+    enum:
+      - "RGB"
+      - "BGR"
diff --git a/dts/bindings/mipi-dbi/zephyr,mipi-dbi-spi.yaml b/dts/bindings/mipi-dbi/zephyr,mipi-dbi-spi.yaml
index 31b9abccc5f..e3e292fefa5 100644
--- a/dts/bindings/mipi-dbi/zephyr,mipi-dbi-spi.yaml
+++ b/dts/bindings/mipi-dbi/zephyr,mipi-dbi-spi.yaml
@@ -28,20 +28,16 @@ properties:
       Reset GPIO pin. Set high to reset the display
 
   xfr-min-bits:
-    type: int
-    default: 8
+    type: string
+    default: "MIPI_DBI_SPI_XFR_8BIT"
     description:
       On rare types of SPI interfaces, discrete shift registers can be found
       whose task is to convert the serial SPI bit stream to the parallel MCU
       interface with clock and bit accuracy. Typically, these are 16 bits wide.
-
-      Use the macros, not the actual enum value. Here is the concordance list
-      (see dt-bindings/mipi_dbi/mipi_dbi.h)
-         8     MIPI_DBI_SPI_XFR_8BIT
-        16     MIPI_DBI_SPI_XFR_16BIT
+      These definitions should match those in dt-bindings/mipi_dbi/mipi_dbi.h
     enum:
-      - 8
-      - 16
+      - "MIPI_DBI_SPI_XFR_8BIT"
+      - "MIPI_DBI_SPI_XFR_16BIT"
 
   write-only:
     type: boolean
diff --git a/dts/bindings/mipi-dsi/nxp,mipi-dsi-2l.yaml b/dts/bindings/mipi-dsi/nxp,mipi-dsi-2l.yaml
index 02871f29641..1e5458c5701 100644
--- a/dts/bindings/mipi-dsi/nxp,mipi-dsi-2l.yaml
+++ b/dts/bindings/mipi-dsi/nxp,mipi-dsi-2l.yaml
@@ -76,3 +76,8 @@ properties:
     description:
       Enable non-contiuous high speed clock. Saves power but introduces latency
       when transitioning to high speed mode.
+
+  ulps-control:
+    type: boolean
+    description:
+      The IP supports ULPS between transfer.
diff --git a/dts/bindings/mipi-dsi/renesas,ra-mipi-dsi.yaml b/dts/bindings/mipi-dsi/renesas,ra-mipi-dsi.yaml
index 6f0f572aced..dbcbb47c8e2 100644
--- a/dts/bindings/mipi-dsi/renesas,ra-mipi-dsi.yaml
+++ b/dts/bindings/mipi-dsi/renesas,ra-mipi-dsi.yaml
@@ -18,3 +18,81 @@ properties:
     type: string-array
     required: true
     description: name of each interrupt
+
+  pll-div:
+    type: int
+    enum: [1, 2, 3, 4]
+    description:
+      PHY PLL divisor.
+
+  pll-mul-int:
+    type: int
+    description:
+      PHY PLL integer multiplier.
+
+  pll-mul-frac:
+    type: string
+    enum: ["0.00", "0.33", "0.66", "0.50"]
+    description:
+      PHY PLL fractional multiplier.
+
+  lp-divisor:
+    type: int
+    description:
+      PHY PLL LP speed divisor.
+
+  ulps-wakeup-period:
+    type: int
+    description: ULPS wakeup period.
+
+  video-mode-delay:
+    type: int
+    description: |
+      Set the delay value inside DSI Host until the transfer begins.
+
+  timing:
+    type: array
+    description: |
+      MIPI DSI timing parameter: <CLKSTPT CLKBFHT CLKKPT GOLPBKT>
+
+child-binding:
+  description: |
+    MIPI PHY timing configuration. The child node must be named "phys-timing".
+    Refer to '57. MIPI PHY - RA8D1 MCU group HWM' for detail parameter description.
+
+  properties:
+    t-init:
+      type: int
+      required: true
+      description: |
+        Minimum duration of the TINIT state (Units: operation clock cycles).
+
+    t-clk-prep:
+      type: int
+      required: true
+      description: |
+        Duration of the clock lane LP-00 state (immediately before entry to the HS-0 state).
+
+    t-hs-prep:
+      type: int
+      required: true
+      description: |
+        Duration of the data lane LP-00 state (immediately before entry to the HS-0 state).
+
+    t-lp-exit:
+      type: int
+      required: true
+      description:
+        Low-power transition time to High-Speed mode.
+
+    dphytim4:
+      type: array
+      required: true
+      description: |
+        Clock lane pre and post data timing parameter: <TCLKZERO TCLKPRE TCLKPOST TCLKTRL>
+
+    dphytim5:
+      type: array
+      required: true
+      description: |
+        High-Speed data lane timing parameter: <THSZERO THSTRL THSEXIT>
diff --git a/dts/bindings/misc/ene,kb1200-gcfg.yaml b/dts/bindings/misc/ene,kb1200-gcfg.yaml
index a8700fe02f1..e08d2332f67 100644
--- a/dts/bindings/misc/ene,kb1200-gcfg.yaml
+++ b/dts/bindings/misc/ene,kb1200-gcfg.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 ENE Technology Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-description: ENE, General Configuration node
+description: ENE, General Configuration
 
 compatible: "ene,kb1200-gcfg"
 
diff --git a/dts/bindings/misc/ene,kb1200-pmu.yaml b/dts/bindings/misc/ene,kb1200-pmu.yaml
index d6516a4e42f..ee0a0d655a5 100644
--- a/dts/bindings/misc/ene,kb1200-pmu.yaml
+++ b/dts/bindings/misc/ene,kb1200-pmu.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 ENE Technology Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-description: ENE, Power Manager node
+description: ENE, Power Manager
 
 compatible: "ene,kb1200-pmu"
 
diff --git a/dts/bindings/misc/intel,timeaware-gpio.yaml b/dts/bindings/misc/intel,timeaware-gpio.yaml
index 149e95bbb6a..4a05d3d5641 100644
--- a/dts/bindings/misc/intel,timeaware-gpio.yaml
+++ b/dts/bindings/misc/intel,timeaware-gpio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-description: Intel TGPIO node
+description: Intel TGPIO
 
 compatible: "intel,timeaware-gpio"
 
diff --git a/dts/bindings/misc/nuvoton,npcx-soc-id.yaml b/dts/bindings/misc/nuvoton,npcx-soc-id.yaml
index 2f44d469902..5efeaa43cd5 100644
--- a/dts/bindings/misc/nuvoton,npcx-soc-id.yaml
+++ b/dts/bindings/misc/nuvoton,npcx-soc-id.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021 Nuvoton Technology Corporation.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Nuvoton, NPCX soc ID node
+description: Nuvoton, NPCX soc ID
 
 compatible: "nuvoton,npcx-soc-id"
 
diff --git a/dts/bindings/misc/nxp,rdc.yaml b/dts/bindings/misc/nxp,rdc.yaml
index 08431f94bfc..9682bcbed47 100644
--- a/dts/bindings/misc/nxp,rdc.yaml
+++ b/dts/bindings/misc/nxp,rdc.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  NXP i.MX Resource Domain Controller (RDC) node.
+  NXP i.MX Resource Domain Controller (RDC).
   The RDC provides robust support for the isolation of destination
   memory mapped locations such as peripherals and memory to a single
   core, a bus master, or set of cores and bus masters.
diff --git a/dts/bindings/misc/nxp,s32-emios.yaml b/dts/bindings/misc/nxp,s32-emios.yaml
index 61c831a01a0..9747dd9000f 100644
--- a/dts/bindings/misc/nxp,s32-emios.yaml
+++ b/dts/bindings/misc/nxp,s32-emios.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  NXP S32 Enhanced Modular IO SubSystem (eMIOS) node for S32 SoCs.
+  Enhanced Modular IO SubSystem (eMIOS) for NXP S32 SoCs.
   eMIOS provides independent unified channels (UCs), some of channels
   have internal counter that either can be used independently or used
   as a reference timebase (master bus) for other channels.
@@ -52,7 +52,6 @@ child-binding:
             bus-type = "BUS_A";
             channel-mask = <0x07FFFFF>;
             prescaler = <1>;
-            period = <65535>;
             mode = <MCB_UP_COUNTER>;
             freeze;
             status = "okay";
@@ -104,13 +103,6 @@ child-binding:
           - "MCB_UP_COUNTER"
           - "MCB_UP_DOWN_COUNTER"
 
-      period:
-        type: int
-        required: true
-        description: |
-          Default period (in ticks) for master bus at boot time. This determines PWM period
-          for channels use this bus as reference timebase. Could be in range [2 ... 65535]
-
       freeze:
         type: boolean
         description: Freeze internal counter when the chip enters Debug mode.
diff --git a/dts/bindings/misc/nxp,s32-lcu.yaml b/dts/bindings/misc/nxp,s32-lcu.yaml
index 51707de20e8..b3bbdb7a6fd 100644
--- a/dts/bindings/misc/nxp,s32-lcu.yaml
+++ b/dts/bindings/misc/nxp,s32-lcu.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  NXP S32 Logic control Unit node for S32 SoCs.
+  Logic control Unit for NXP S32 SoCs.
   LCU selects multiple inputs from timers, Pulse Width Modulation
   signals, and Input/Output (I/O) pads, and combines them
   using a programmable logic function to create output waveforms
diff --git a/dts/bindings/misc/nxp,s32-trgmux.yaml b/dts/bindings/misc/nxp,s32-trgmux.yaml
index 55a589d6836..58507c4034d 100644
--- a/dts/bindings/misc/nxp,s32-trgmux.yaml
+++ b/dts/bindings/misc/nxp,s32-trgmux.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  NXP S32 Trigger Multiplexing Control node for S32 SoCs.
+  Trigger Multiplexing Control for NXP S32 SoCs.
   The device supports the triggering scheme between peripherals.
   The supported trigger sources and destination can be found in
   the device Ref Manual
diff --git a/dts/bindings/misc/renesas,ra-ulpt.yaml b/dts/bindings/misc/renesas,ra-ulpt.yaml
new file mode 100644
index 00000000000..3b38f1f6ec2
--- /dev/null
+++ b/dts/bindings/misc/renesas,ra-ulpt.yaml
@@ -0,0 +1,30 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA ULPT
+
+compatible: "renesas,ra-ulpt"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  channel:
+    type: int
+    required: true
+    description: |
+      ULPT channel number.
+
+  interrupts:
+    description: |
+      IRQ number and priority to use for ULPT.
+
+  interrupt-names:
+    enum:
+      - "ulpti"
+      - "ulptcmai"
+      - "ulptcmbi"
+    description: |
+      Interrupts must be given corresponding names so that the timer driver can recognize them.
diff --git a/dts/bindings/misc/renesas,rz-sci.yaml b/dts/bindings/misc/renesas,rz-sci.yaml
new file mode 100644
index 00000000000..4f685a3ee66
--- /dev/null
+++ b/dts/bindings/misc/renesas,rz-sci.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RZ SCI controller
+
+compatible: "renesas,rz-sci"
+
+include: [base.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  channel:
+    type: int
+    required: true
+
+  interrupts:
+    required: true
diff --git a/dts/bindings/misc/zephyr,swdp-gpio.yaml b/dts/bindings/misc/zephyr,swdp-gpio.yaml
index c6d6aa55e7f..b4b3585e2fc 100644
--- a/dts/bindings/misc/zephyr,swdp-gpio.yaml
+++ b/dts/bindings/misc/zephyr,swdp-gpio.yaml
@@ -3,8 +3,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  This is a representation of the Serial Wire Debug Port interface
-  implementation by GPIO bit-banging.
+  Serial Wire Debug Port interface implementation by GPIO bit-banging.
 
   Schematic using dual-supply bus transceiver and separate dout and dnoe pins
 
diff --git a/dts/bindings/mmc/st,stm32-sdmmc.yaml b/dts/bindings/mmc/st,stm32-sdmmc.yaml
index 7071b44be16..f8c77f992ad 100644
--- a/dts/bindings/mmc/st,stm32-sdmmc.yaml
+++ b/dts/bindings/mmc/st,stm32-sdmmc.yaml
@@ -1,10 +1,15 @@
-description: stm32 sdmmc disk access
+description: STM32 SDMMC Disk Access
 
 compatible: "st,stm32-sdmmc"
 
 include: [mmc.yaml, pinctrl-device.yaml, reset-device.yaml]
 
 properties:
+  disk-name:
+    type: string
+    description: |
+      Disk name.
+
   clocks:
     required: true
 
diff --git a/dts/bindings/modem/sqn,gm02s.yaml b/dts/bindings/modem/sqn,gm02s.yaml
index 223b8c102a3..584fc878e18 100644
--- a/dts/bindings/modem/sqn,gm02s.yaml
+++ b/dts/bindings/modem/sqn,gm02s.yaml
@@ -11,3 +11,6 @@ properties:
   mdm-reset-gpios:
     type: phandle-array
     required: true
+
+  mdm-wake-gpios:
+    type: phandle-array
diff --git a/dts/bindings/mspi/ambiq,mspi-controller.yaml b/dts/bindings/mspi/ambiq,mspi-controller.yaml
index 44b5cad2a2e..380bcf4fe42 100644
--- a/dts/bindings/mspi/ambiq,mspi-controller.yaml
+++ b/dts/bindings/mspi/ambiq,mspi-controller.yaml
@@ -5,7 +5,7 @@ description: Ambiq MSPI controller
 
 compatible: "ambiq,mspi-controller"
 
-include: [mspi-controller.yaml, pinctrl-device.yaml, ambiq-pwrcfg.yaml]
+include: [mspi-controller.yaml, pinctrl-device.yaml]
 
 properties:
   reg:
@@ -14,9 +14,6 @@ properties:
   interrupts:
     required: true
 
-  ambiq,pwrcfg:
-    required: true
-
   ce-gpios:
     required: true
 
diff --git a/dts/bindings/mtd/fixed-partitions.yaml b/dts/bindings/mtd/fixed-partitions.yaml
index 90989a56697..365762bf8df 100644
--- a/dts/bindings/mtd/fixed-partitions.yaml
+++ b/dts/bindings/mtd/fixed-partitions.yaml
@@ -1,6 +1,5 @@
 description: |
-  This binding is used to describe fixed partitions of a flash (or
-  other nonvolatile storage) memory.
+  Fixed partitions of a flash (or other non-volatile storage) memory.
 
   Here is an example:
 
diff --git a/dts/bindings/mtd/nxp,s32-qspi-device.yaml b/dts/bindings/mtd/nxp,s32-qspi-device.yaml
index 23de077121e..889c3995f01 100644
--- a/dts/bindings/mtd/nxp,s32-qspi-device.yaml
+++ b/dts/bindings/mtd/nxp,s32-qspi-device.yaml
@@ -1,4 +1,4 @@
-# Copyright 2023 NXP
+# Copyright 2023-2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
@@ -14,9 +14,15 @@ properties:
   reg:
     required: true
 
-  memory-alignment:
+  max-program-buffer-size:
     type: int
+    required: true
+    description: |
+      The maximum of programming page buffer size of the flash memory device,
+      as specified in the flash memory device datasheet.
+
+  write-block-size:
+    type: int
+    required: true
     description: |
-      Memory alignment in bytes, used to calculate padding when performing
-      unaligned accesses.
-      If not provided, 1 byte alignment will be selected.
+      The number of bytes used in write operations.
diff --git a/dts/bindings/mtd/nxp,s32-qspi-hyperflash.yaml b/dts/bindings/mtd/nxp,s32-qspi-hyperflash.yaml
new file mode 100644
index 00000000000..3fe64dd9aba
--- /dev/null
+++ b/dts/bindings/mtd/nxp,s32-qspi-hyperflash.yaml
@@ -0,0 +1,99 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  QSPI hyperflash connected to the NXP S32 QSPI bus.
+
+compatible: "nxp,s32-qspi-hyperflash"
+
+include: "nxp,s32-qspi-device.yaml"
+
+properties:
+  device-id-word-addr:
+    required: true
+    type: int
+    description: |
+      The word address of the device ID in ASO (Application-Specific Object).
+      This address specifies the exact location within the memory where the device ID is stored.
+
+  rwds-low-dual-error:
+    type: boolean
+    description: |
+      Enable Read-Write Data Strobe (RWDS) dual error detect.
+
+  secure-region-locked:
+    type: boolean
+    description: |
+      The secure region is locked and cannot be accessed or modified.
+      This is particularly useful in scenarios where sensitive data needs protection from
+      unauthorized access, such as in financial applications or secure communication systems.
+      If it is disable, having access to all memory regions is beneficial during development
+      or debugging phases.
+
+  vcc-mv:
+    type: int
+    required: true
+    enum:
+      - 1800
+      - 3000
+    description: |
+      The memory operating voltage supply in mV.
+
+  drive-strength-ohm:
+    type: int
+    required: true
+    enum:
+      - 12
+      - 14
+      - 16
+      - 20
+      - 24
+      - 27
+      - 34
+      - 40
+      - 45
+      - 68
+      - 71
+      - 117
+    description: |
+      Specifies the output drive strength in ohm, which based on the operating device VCC.
+      The supported typical impedance settings:
+        For 1.8V: 117 Ohm, 68 Ohm, 45 Ohm, 34 Ohm, 27 Ohm, 24 Ohm, 20 Ohm
+        For 3V: 71 Ohm, 40 Ohm, 27 Ohm, 20 Ohm, 16 Ohm, 14 Ohm, 12 Ohm
+      See the xVCR[14:12] field in VCR configuration register in the memory device datasheet.
+
+  read-latency-cycles:
+    type: int
+    required: true
+    enum:
+      - 5
+      - 6
+      - 7
+      - 8
+      - 9
+      - 10
+      - 11
+      - 12
+      - 13
+      - 14
+      - 15
+      - 16
+    description: |
+      Specifies the read latency in cycles, which is determined based on the operating frequency
+      as specified in the memory device datasheet.
+
+  support-only-uniform-sectors:
+    type: boolean
+    description: |
+      The memory device supports only uniform (256KB) sectors.
+
+  ppw-sectors-addr-mapping:
+    type: string
+    required: true
+    enum:
+      - LOW
+      - HIGH
+    description: |
+      The mapping of the parameter and read password sectors:
+        - LOW: Parameter and read password sectors mapped into lowest addresses
+        - HIGH: Parameter and read password sectors mapped into highest addresses
diff --git a/dts/bindings/mtd/nxp,xspi-device.yaml b/dts/bindings/mtd/nxp,xspi-device.yaml
new file mode 100644
index 00000000000..d067b878c93
--- /dev/null
+++ b/dts/bindings/mtd/nxp,xspi-device.yaml
@@ -0,0 +1,6 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP XSPI device
+
+include: [spi-device.yaml, "jedec,jesd216.yaml"]
diff --git a/dts/bindings/mtd/nxp,xspi-mx25um51345g.yaml b/dts/bindings/mtd/nxp,xspi-mx25um51345g.yaml
new file mode 100644
index 00000000000..6554d5d61af
--- /dev/null
+++ b/dts/bindings/mtd/nxp,xspi-mx25um51345g.yaml
@@ -0,0 +1,8 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP XSPI MX25UM51345G
+
+compatible: "nxp,xspi-mx25um51345g"
+
+include: ["nxp,xspi-device.yaml", soc-nv-flash.yaml]
diff --git a/dts/bindings/mtd/st,stm32-nv-flash.yaml b/dts/bindings/mtd/st,stm32-nv-flash.yaml
index 518c12ab450..81a5a944793 100644
--- a/dts/bindings/mtd/st,stm32-nv-flash.yaml
+++ b/dts/bindings/mtd/st,stm32-nv-flash.yaml
@@ -1,7 +1,8 @@
 description: |
-  STM32 flash memory. This binding is for the flash memory itself, not
-  the flash controller peripheral. For that, see the
-  "st,stm32-flash-controller" binding.
+  STM32 flash memory.
+
+  This binding is for the flash memory itself, not the flash controller peripheral.
+  For that, see the "st,stm32-flash-controller" binding.
 
 include: soc-nv-flash.yaml
 
diff --git a/dts/bindings/mtd/st,stm32f4-nv-flash.yaml b/dts/bindings/mtd/st,stm32f4-nv-flash.yaml
index 258e2c209a7..c56dbb9b065 100644
--- a/dts/bindings/mtd/st,stm32f4-nv-flash.yaml
+++ b/dts/bindings/mtd/st,stm32f4-nv-flash.yaml
@@ -1,5 +1,5 @@
 description: |
-  ST STM32F4 family flash memory.
+  STM32F4 flash memory.
 
 include: st,stm32-nv-flash.yaml
 
diff --git a/dts/bindings/mtd/st,stm32l0-nv-flash.yaml b/dts/bindings/mtd/st,stm32l0-nv-flash.yaml
index 682ee48a601..1c5ea5ecebb 100644
--- a/dts/bindings/mtd/st,stm32l0-nv-flash.yaml
+++ b/dts/bindings/mtd/st,stm32l0-nv-flash.yaml
@@ -1,5 +1,5 @@
 description: |
-  ST STM32L0 family flash memory.
+  STM32L0 flash memory.
 
 include: st,stm32-nv-flash.yaml
 
diff --git a/dts/bindings/mtd/ti,cc23x0-ccfg-flash.yaml b/dts/bindings/mtd/ti,cc23x0-ccfg-flash.yaml
new file mode 100644
index 00000000000..0786ec7c478
--- /dev/null
+++ b/dts/bindings/mtd/ti,cc23x0-ccfg-flash.yaml
@@ -0,0 +1,161 @@
+# Copyright (c) 2024 BayLibre, SAS
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  This binding describes the TI CC23X0 flash CCFG (custom configuration)
+  area content.
+
+  Notes:
+    The flash CCFG sector node (e.g. flash1) should have both
+    "ti,cc23x0-ccfg-flash" and the "soc-nv-flash" compatibles.
+    The latter is used from mcuboot and other modules to identify
+    the flash area.
+
+compatible: "ti,cc23x0-ccfg-flash"
+
+include: soc-nv-flash.yaml
+
+properties:
+  ti,bldr-vtor-flash:
+    type: int
+    description: |
+      Bootloader entry point when a boot from flash is selected.
+      Valid range: 0 - 0x0effffff
+      Default is 0, which is the standard initial configuration.
+    default: 0
+
+  ti,serial-io-cfg-index:
+    type: int
+    description: |
+      Index of which I/O mapping to use for UART/SPI.
+      Valid range: 0 - 2
+      Default is 0, which is the standard initial configuration. Other values can be
+      used depending on I/O availability.
+    default: 0
+
+  ti,pin-trigger:
+    type: boolean
+    description: |
+      If not present, then bootloader unconditionally triggers.
+      Else normal pin trigger check is performed.
+
+  ti,pin-trigger-dio:
+    type: int
+    description: |
+      Index of DIO pin to use for pin trigger check.
+      Valid range: 0 - 25
+      Default is 0, which is the standard initial configuration. Other values can be
+      used depending on DIO availability.
+    default: 0
+
+  ti,pin-trigger-level-hi:
+    type: boolean
+    description: |
+      If not present, then the level on trigger pin that triggers bootloader is low.
+      Else level that triggers bootloader is high.
+
+  ti,debug-port:
+    type: boolean
+    description: |
+      If not present, then the SWD port is disabled altogether at a certain point in boot
+      before invoking either bootloader or application.
+
+  ti,energy-trace:
+    type: boolean
+    description: |
+      Allows using EnergyTrace power analyzer tool.
+      EnergyTrace software is an energy-based code analysis tool that measures
+      and displays the energy profile of an application and helps optimize it for
+      ultra-low-power consumption.
+
+  ti,flash-verify:
+    type: boolean
+    description: |
+      Determines whether flash verifying SACI commands are allowed. These commands only check
+      integrity against a provided CRC32 value, never return any flash contents. Flash verify
+      commands are always allowed after a chip erase and until the first reset after the CCFG
+      sector has been programmed.
+
+  ti,flash-program:
+    type: boolean
+    description: |
+      Determines whether flash programming SACI commands are allowed.
+      Reset to allowed after a chip erase.
+
+  ti,chip-erase:
+    type: boolean
+    description: |
+      Determines whether chip erasing SACI commands are allowed.
+
+  ti,ret-to-factory:
+    type: boolean
+    description: |
+      Allows return-to-factory procedure by SACI.
+      To do full failure analysis including flash, a return to factory procedure is supported.
+
+  ti,wr-er-prot-sect0-31:
+    type: int
+    description: |
+      Bitmask for write/erase protection of individual sectors in sector range [0, 31].
+      Controls whether flash programming is allowed through SACI. The same mechanism
+      controls whether the application is allowed to program these sectors.
+      0 = protected.
+      Valid range: 0 - 0xffffffff
+      Default is 0xffffffff to allow programming these sectors.
+    default: 0xffffffff
+
+  ti,wr-er-prot-sect32-255:
+    type: int
+    description: |
+      Bitmask for write/erase protection of groups of 8 sectors, in sector range [32, 255].
+      Bit i protects sectors [32 + 8i, 39 + 8i].
+      0 = protected.
+      Valid range: 0 - 0xffffffff
+      Default is 0xffffffff to allow programming these sectors.
+    default: 0xffffffff
+
+  ti,wr-er-prot-ccfg-sect:
+    type: int
+    description: |
+      Bitmask for write/erase protection of CCFG sectors.
+      Valid range: 0 - 0xffffffff
+      Default is 0 to prevent from mistakenly programming these sectors.
+    default: 0
+
+  ti,wr-er-prot-fcfg-sect:
+    type: int
+    description: |
+      Bitmask for write/erase protection of FCFG sectors.
+      Valid range: 0 - 0xffffffff
+      Default is 0 to prevent from mistakenly programming these sectors.
+    default: 0
+
+  ti,wr-er-prot-engr-sect:
+    type: int
+    description: |
+      Bitmask for write/erase protection of ENGR sectors.
+      Valid range: 0 - 0xffffffff
+      Default is 0 to prevent from mistakenly programming these sectors.
+    default: 0
+
+  ti,chip-er-retain-sect0-31:
+    type: int
+    description: |
+      Bitmask for chip erase protection of individual sectors in sector range [0, 31].
+      Controls whether a chip erase affects a sector or not. The mechanism is intended
+      to allow flash sectors devoted to logging or runtime state/configuration to survive
+      the chip erase during a FW update.
+      0 = protected.
+      Valid range: 0 - 0xffffffff
+      Default is 0 to prevent from mistakenly programming these sectors.
+    default: 0
+
+  ti,chip-er-retain-sect32-255:
+    type: int
+    description: |
+      Bitmask for chip erase protection of groups of 8 sectors, in sector range [32, 255].
+      Bit i protects sectors [32 + 8i, 39 + 8i].
+      0 = protected.
+      Valid range: 0 - 0xffffffff
+      Default is 0 to prevent from mistakenly programming these sectors.
+    default: 0
diff --git a/dts/bindings/mtd/ti,tmp116-eeprom.yaml b/dts/bindings/mtd/ti,tmp116-eeprom.yaml
deleted file mode 100644
index 4c4188b0c70..00000000000
--- a/dts/bindings/mtd/ti,tmp116-eeprom.yaml
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright (c) 2020 Innoseis B.V
-# SPDX-License-Identifier: Apache-2.0
-
-description: TI TMP116 EEPROM controller binding
-
-compatible: "ti,tmp116-eeprom"
-
-include: eeprom-base.yaml
-
-on-bus: tmp116
diff --git a/dts/bindings/mtd/ti,tmp11x-eeprom.yaml b/dts/bindings/mtd/ti,tmp11x-eeprom.yaml
new file mode 100644
index 00000000000..e4d5a24dd5d
--- /dev/null
+++ b/dts/bindings/mtd/ti,tmp11x-eeprom.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2020 Innoseis B.V
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI TMP11X EEPROM controller
+
+compatible: "ti,tmp11x-eeprom"
+
+include: eeprom-base.yaml
+
+on-bus: tmp11x
diff --git a/dts/bindings/net/wireless/generic-fem-two-ctrl-pins.yaml b/dts/bindings/net/wireless/generic-fem-two-ctrl-pins.yaml
index a7202f1294d..edf3a632caf 100644
--- a/dts/bindings/net/wireless/generic-fem-two-ctrl-pins.yaml
+++ b/dts/bindings/net/wireless/generic-fem-two-ctrl-pins.yaml
@@ -2,8 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    This is a representation of generic radio Front-End Module (FEM)
-    that has a two-pin control interface (CTX, CRX).
+    Generic radio Front-End Module (FEM) with a two-pin
+    control interface (CTX, CRX).
 
     The CTX control pin is used to enable the Power Amplifier (PA) in
     the transmit path. This is therefore sometimes referred to as
diff --git a/dts/bindings/net/wireless/nordic,nrf-nfct-v2.yaml b/dts/bindings/net/wireless/nordic,nrf-nfct-v2.yaml
new file mode 100644
index 00000000000..e6b34aff3ec
--- /dev/null
+++ b/dts/bindings/net/wireless/nordic,nrf-nfct-v2.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Nordic nRF family NFCT (Near Field Communication Tag)
+
+compatible: "nordic,nrf-nfct-v2"
+
+include: nordic,nrf-nfct.yaml
+
+properties:
+  nfct-pins-as-gpios:
+    type: boolean
+    description: |
+      When enabled this property will configure pins dedicated to NFCT
+      peripheral as regular GPIOs. This property must be applied in cpuapp
+      if NFCT pins are intended to be used as regular GPIOs by any core.
+
+      NFC pins in nRF54H series: P2.10 and P2.11
diff --git a/dts/bindings/net/wireless/nordic,nrf21540-fem.yaml b/dts/bindings/net/wireless/nordic,nrf21540-fem.yaml
index 706fe8dd9e6..aedd22bcf79 100644
--- a/dts/bindings/net/wireless/nordic,nrf21540-fem.yaml
+++ b/dts/bindings/net/wireless/nordic,nrf21540-fem.yaml
@@ -3,7 +3,7 @@
 
 
 description: |
-    This is a representation of the nRF21540 Radio Front-End module.
+    nRF21540 Radio Front-End module.
 
     See the "nordic,nrf21540-fem-spi" binding to configure the SPI
     interface. The SPI interface should be configured as a child node
diff --git a/dts/bindings/net/wireless/silabs,series2-radio.yaml b/dts/bindings/net/wireless/silabs,series2-radio.yaml
new file mode 100644
index 00000000000..7d2d1606406
--- /dev/null
+++ b/dts/bindings/net/wireless/silabs,series2-radio.yaml
@@ -0,0 +1,59 @@
+# Copyright (c) 2025 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Silicon Labs Series 2 radio interface.
+
+    This controls the radio transceiver on Silicon Labs Series 2
+    SoCs.
+
+compatible: "silabs,series2-radio"
+
+include: [base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  pa-initial-power-dbm:
+    type: int
+    required: true
+    description: |
+      Initial Power Amplifier power in dBm.
+
+  pa-ramp-time-us:
+    type: int
+    required: true
+    description: |
+      Power Amplifier ramp time in microseconds.
+
+  pa-voltage-mv:
+    type: int
+    required: true
+    description: |
+      Voltage on PAVDD supply pin in millivolts.
+
+  pa-2p4ghz:
+    type: string
+    description: |
+      Power Amplifier selection for 2.4 GHz. A value of 'highest' selects the highest
+      available PA on the given device. Other values explicitly select a specific PA.
+      Not all PAs are available on all devices, check device specific documentation.
+      If this property is not set, no 2.4 GHz PA is enabled.
+    enum:
+      - highest
+      - hp
+      - mp
+      - lp
+
+  pa-subghz:
+    type: string
+    description: |
+      Power Amplifier selection for sub-GHz. A value of 'highest' selects the highest
+      available PA on the given device. This is the only available option. If this
+      property is not set, no sub-GHz PA is enabled.
+    enum:
+      - highest
diff --git a/dts/bindings/net/wireless/ti,cc13xx-cc26xx-radio.yaml b/dts/bindings/net/wireless/ti,cc13xx-cc26xx-radio.yaml
index 3c7f8079ff3..f5145f8c4d1 100644
--- a/dts/bindings/net/wireless/ti,cc13xx-cc26xx-radio.yaml
+++ b/dts/bindings/net/wireless/ti,cc13xx-cc26xx-radio.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-description: TI SimpleLink CC13xx / CC26xx radio node
+description: TI SimpleLink CC13xx / CC26xx radio
 
 compatible: "ti,cc13xx-cc26xx-radio"
 
diff --git a/dts/bindings/ospi/st,stm32-ospi.yaml b/dts/bindings/ospi/st,stm32-ospi.yaml
index b1666d67d91..f28abdbb1e1 100644
--- a/dts/bindings/ospi/st,stm32-ospi.yaml
+++ b/dts/bindings/ospi/st,stm32-ospi.yaml
@@ -2,8 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    STM32 OSPI device representation. Enabling a stm32 octospi node in a board
-    description would typically requires this:
+    STM32 OSPI Controller.
+
+    Enabling a stm32 octospi node in a board description would typically requires this:
 
         &octospi {
             pinctrl-0 = <&octospi_clk_pe9 &octospi_ncs_pe10 &octospi_dqs_pe11
diff --git a/dts/bindings/pcie/controller/brcm,brcmstb-pcie.yaml b/dts/bindings/pcie/controller/brcm,brcmstb-pcie.yaml
new file mode 100644
index 00000000000..850260c09e6
--- /dev/null
+++ b/dts/bindings/pcie/controller/brcm,brcmstb-pcie.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Junho Lee <junho@tsnlab.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: BRCMSTB PCIe controller
+
+compatible: "brcm,brcmstb-pcie"
+
+include: [base.yaml, pcie-controller.yaml]
+
+properties:
+  reg:
+    required: true
diff --git a/dts/bindings/phy/st,stm32u5-otghs-phy.yaml b/dts/bindings/phy/st,stm32u5-otghs-phy.yaml
index f844d813a99..38e9a36f3e7 100644
--- a/dts/bindings/phy/st,stm32u5-otghs-phy.yaml
+++ b/dts/bindings/phy/st,stm32u5-otghs-phy.yaml
@@ -3,6 +3,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
+    STM32U5 OTG HS PHY.
+
     This binding is to be used by the STM32U5xx transceivers which are built-in
     with USB HS PHY IP and a configurable HSE clock source.
 
diff --git a/dts/bindings/pinctrl/adi,max32-pinctrl.yaml b/dts/bindings/pinctrl/adi,max32-pinctrl.yaml
index d40926ca772..414983eb1a9 100644
--- a/dts/bindings/pinctrl/adi,max32-pinctrl.yaml
+++ b/dts/bindings/pinctrl/adi,max32-pinctrl.yaml
@@ -2,9 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  MAX32 Pin controller Node
-  Based on pincfg-node.yaml binding.
+  MAX32 Pin Controller
 
+  Based on pincfg-node.yaml binding.
   Note: `bias-disable`  are default pin configurations.
 
 compatible: "adi,max32-pinctrl"
diff --git a/dts/bindings/pinctrl/ambiq,apollo3-pinctrl.yaml b/dts/bindings/pinctrl/ambiq,apollo3-pinctrl.yaml
index 6035955af50..f1d362b0472 100644
--- a/dts/bindings/pinctrl/ambiq,apollo3-pinctrl.yaml
+++ b/dts/bindings/pinctrl/ambiq,apollo3-pinctrl.yaml
@@ -98,7 +98,7 @@ child-binding:
           For Apollo3 these pins are 0-1,5-6,8-9,25,27,39-40,42-43,48-49.
           The default value is 1500 ohms, which is the reset value of
           register PADREGx.PADxRSEL.
-      ambiq,iom-nce-module:
+      ambiq,nce-src:
         type: int
         default: 0
         description: |
@@ -125,3 +125,10 @@ child-binding:
           information and config the pins accordingly, we give a default value
           0 here to make it be consistent with AM_HAL_GPIO_PINCFG_DEFAULT in
           ambiq hal. If the pin is not a CE, this descriptor will be ignored.
+      ambiq,nce-pol:
+        type: int
+        default: 0
+        description: |
+          Polarity select for NCE
+          LOW = 0x0 - Polarity is active low
+          HIGH = 0x1 - Polarity is active high
diff --git a/dts/bindings/pinctrl/ambiq,apollo4-pinctrl.yaml b/dts/bindings/pinctrl/ambiq,apollo4-pinctrl.yaml
index 9e5feecc808..cfb7cbd7a4e 100644
--- a/dts/bindings/pinctrl/ambiq,apollo4-pinctrl.yaml
+++ b/dts/bindings/pinctrl/ambiq,apollo4-pinctrl.yaml
@@ -104,7 +104,7 @@ child-binding:
         default: 1500
         description: |
           The pullup resistor value. The default value is 1500 ohms.
-      ambiq,iom-nce-module:
+      ambiq,nce-src:
         type: int
         default: 0
         description: |
@@ -154,24 +154,18 @@ child-binding:
             42,    DC_RESX : DC module RESX
           If the pin is not a CE, this descriptor will be ignored.
           Default value 0, which is the reset value.
-      ambiq,iom-mspi:
+      ambiq,nce-pol:
         type: int
         default: 0
         description: |
-          Indicates the module which uses specific CE pin, 1 if CE is IOM, 0 if MSPI.
-          Default value 0, which is the reset value.
-          If the pin is not a CE, this descriptor will be ignored.
-      ambiq,iom-num:
-        type: int
-        default: 0
-        description: |
-          Indicates the instance which uses specific CE pin.
-          IOM number (0-7) or MSPI (0-2).
-          Default value 0, which is the reset value.
-          If the pin is not a CE, this descriptor will be ignored.
-      ambiq,interrupt-direction:
+          Polarity select for NCE
+          LOW = 0x0 - Polarity is active low
+          HIGH = 0x1 - Polarity is active high
+      ambiq,sdif-cdwp:
         type: int
         default: 0
         description: |
-          Indicates the pininterrupt direction.
-          Default value 0, which is the reset value.
+          Configure SD Card Detection and Write Protection pin
+          0x0 - Not SDIF pin
+          0x1 - SDIFCD
+          0x2 - SDIFWP
diff --git a/dts/bindings/pinctrl/ambiq,apollo5-pinctrl.yaml b/dts/bindings/pinctrl/ambiq,apollo5-pinctrl.yaml
new file mode 100644
index 00000000000..006c7339a09
--- /dev/null
+++ b/dts/bindings/pinctrl/ambiq,apollo5-pinctrl.yaml
@@ -0,0 +1,156 @@
+# Copyright (c) 2025 Ambiq Micro Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    The Ambiq Apollo5 pin controller is a node responsible for controlling
+    pin function selection and pin properties, such as routing a UART0 TX
+    to pin 60 and enabling the pullup resistor on that pin.
+
+    The node has the 'pinctrl' node label set in your SoC's devicetree,
+    so you can modify it like this:
+
+      &pinctrl {
+              /* your modifications go here */
+      };
+
+    All device pin configurations should be placed in child nodes of the
+    'pinctrl' node, as shown in this example:
+
+      /* You can put this in places like a board-pinctrl.dtsi file in
+       * your board directory, or a devicetree overlay in your application.
+       */
+
+      /* include pre-defined combinations for the SoC variant used by the board */
+      #include <dt-bindings/pinctrl/ambiq-apollo5-pinctrl.h>
+
+      &pinctrl {
+        uart0_default: uart0_default {
+          group1 {
+            pinmux = <UART0TX_P60>;
+          };
+          group2 {
+            pinmux = <UART0RX_P47>;
+            input-enable;
+          };
+        };
+      };
+
+    The 'uart0_default' child node encodes the pin configurations for a
+    particular state of a device; in this case, the default (that is, active)
+    state.
+
+    As shown, pin configurations are organized in groups within each child node.
+    Each group can specify a list of pin function selections in the 'pinmux'
+    property.
+
+    A group can also specify shared pin properties common to all the specified
+    pins, such as the 'input-enable' property in group 2.
+
+compatible: "ambiq,apollo5-pinctrl"
+
+include: base.yaml
+
+child-binding:
+  description: |
+    Definitions for a pinctrl state.
+  child-binding:
+
+    include:
+      - name: pincfg-node.yaml
+        property-allowlist:
+          - input-enable
+          - drive-push-pull
+          - drive-open-drain
+          - bias-high-impedance
+          - bias-pull-up
+          - bias-pull-down
+
+    properties:
+      pinmux:
+        required: true
+        type: array
+        description: |
+          An array of pins sharing the same group properties. Each
+          element of the array is an integer constructed from the
+          pin number and the alternative function of the pin.
+      drive-strength:
+        type: string
+        enum:
+          - "0.1"
+          - "0.5"
+          - "0.75"
+          - "1.0"
+        default: "0.1"
+        description: |
+          The drive strength of a pin, relative to full-driver strength.
+          The default value is 0.1, which is the reset value.
+      ambiq,pull-up-ohms:
+        type: int
+        enum:
+          - 1500
+          - 6000
+          - 12000
+          - 24000
+          - 50000
+          - 100000
+        default: 1500
+        description: |
+          The pullup resistor value. The default value is 1500 ohms.
+      ambiq,nce-src:
+        type: int
+        default: 0
+        description: |
+          IOM0CE0 = 0x0 - IOM 0 NCE 0 module
+          IOM0CE1 = 0x1 - IOM 0 NCE 1 module
+          IOM0CE2 = 0x2 - IOM 0 NCE 2 module
+          IOM0CE3 = 0x3 - IOM 0 NCE 3 module
+          IOM1CE0 = 0x4 - IOM 1 NCE 0 module
+          IOM1CE1 = 0x5 - IOM 1 NCE 1 module
+          IOM1CE2 = 0x6 - IOM 1 NCE 2 module
+          IOM1CE3 = 0x7 - IOM 1 NCE 3 module
+          IOM2CE0 = 0x8 - IOM 2 NCE 0 module
+          IOM2CE1 = 0x9 - IOM 2 NCE 1 module
+          IOM2CE2 = 0xA - IOM 2 NCE 2 module
+          IOM2CE3 = 0xB - IOM 2 NCE 3 module
+          IOM3CE0 = 0xC - IOM 3 NCE 0 module
+          IOM3CE1 = 0xD - IOM 3 NCE 1 module
+          IOM3CE2 = 0xE - IOM 3 NCE 2 module
+          IOM3CE3 = 0xF - IOM 3 NCE 3 module
+          IOM4CE0 = 0x10 - IOM 4 NCE 0 module
+          IOM4CE1 = 0x11 - IOM 4 NCE 1 module
+          IOM4CE2 = 0x12 - IOM 4 NCE 2 module
+          IOM4CE3 = 0x13 - IOM 4 NCE 3 module
+          IOM5CE0 = 0x14 - IOM 5 NCE 0 module
+          IOM5CE1 = 0x15 - IOM 5 NCE 1 module
+          IOM5CE2 = 0x16 - IOM 5 NCE 2 module
+          IOM5CE3 = 0x17 - IOM 5 NCE 3 module
+          IOM6CE0 = 0x18 - IOM 6 NCE 0 module
+          IOM6CE1 = 0x19 - IOM 6 NCE 1 module
+          IOM6CE2 = 0x1A - IOM 6 NCE 2 module
+          IOM6CE3 = 0x1B - IOM 6 NCE 3 module
+          IOM7CE0 = 0x1C - IOM 7 NCE 0 module
+          IOM7CE1 = 0x1D - IOM 7 NCE 1 module
+          IOM7CE2 = 0x1E - IOM 7 NCE 2 module
+          IOM7CE3 = 0x1F - IOM 7 NCE 3 module
+          DC_DPI_DE = 0x30 - DC DPI DE module
+          DISP_CONT_CSX = 0x31 - DISP CONT CSX module
+          DC_SPI_CS_N = 0x32 - DC SPI CS_N module
+          DC_QSPI_CS_N = 0x33 - DC QSPI CS_N module
+          DC_RESX = 0x34 - DC module RESX
+      ambiq,nce-pol:
+        type: int
+        default: 0
+        description: |
+          Polarity select for NCE
+          LOW = 0x0 - Polarity is active low
+          HIGH = 0x1 - Polarity is active high
+      ambiq,sdif-cdwp:
+        type: int
+        default: 0
+        description: |
+          Configure SD Card Detection and Write Protection pin
+          0x0 - Not SDIF pin
+          0x1 - SDIF0CD
+          0x2 - SDIF0WP
+          0x3 - SDIF1CD
+          0x4 - SDIF1WP
diff --git a/dts/bindings/pinctrl/arm,mps2-pinctrl.yaml b/dts/bindings/pinctrl/arm,mps2-pinctrl.yaml
new file mode 100644
index 00000000000..314da3b7e5b
--- /dev/null
+++ b/dts/bindings/pinctrl/arm,mps2-pinctrl.yaml
@@ -0,0 +1,81 @@
+# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    The Arm Mps2 pin controller is a node responsible for controlling
+    pin function selection and pin properties, such as routing a UART3 TX
+    to pin 1.
+
+    The node has the 'pinctrl' node label set in your SoC's devicetree,
+    so you can modify it like this:
+
+      &pinctrl {
+              /* your modifications go here */
+      };
+
+    All device pin configurations should be placed in child nodes of the
+    'pinctrl' node, as shown in this example:
+
+      &pinctrl {
+        /* configuration for the usart0 "default" state */
+        uart3_default: uart3_default {
+          /* group 1 */
+          group1 {
+            /* configure P1 as UART3 TX */
+            pinmux = <UART3_TXD_EXP>;
+          };
+          /* group 2 */
+          group2 {
+            /* configure P0 as UART3 RX */
+            pinmux = <UART3_RXD_EXP>;
+            /* enable input on pin 1 */
+            input-enable;
+          };
+        };
+      };
+
+    The 'uart3_default' child node encodes the pin configurations for a
+    particular state of a device; in this case, the default (that is, active)
+    state.
+
+    As shown, pin configurations are organized in groups within each child node.
+    Each group can specify a list of pin function selections in the 'pinmux'
+    property. Here is a list of supported standard pin properties:
+    - input-enable
+
+    A group can also specify shared pin properties common to all the specified
+    pins, such as the 'input-enable' property in group 2.
+
+    To link pin configurations with a device, use a pinctrl-N property for some
+    number N, like this example you could place in your board's DTS file:
+
+       #include "board-pinctrl.dtsi"
+
+       &uart3 {
+             pinctrl-0 = <&uart3_default>;
+             pinctrl-1 = <&uart3_sleep>;
+             pinctrl-names = "default", "sleep";
+       };
+
+compatible: "arm,mps2-pinctrl"
+
+include: base.yaml
+
+child-binding:
+  description: |
+    Definitions for a pinctrl state.
+  child-binding:
+
+    include:
+      - name: pincfg-node.yaml
+        property-allowlist:
+          - input-enable
+
+    properties:
+      pinmux:
+        required: true
+        type: array
+        description: |
+          An array of pins sharing the same group properties. Each
+          element of the array is an integer constructed from the
+          pin number and the alternative function of the pin.
diff --git a/dts/bindings/pinctrl/arm,mps3-pinctrl.yaml b/dts/bindings/pinctrl/arm,mps3-pinctrl.yaml
new file mode 100644
index 00000000000..68dcde4b17f
--- /dev/null
+++ b/dts/bindings/pinctrl/arm,mps3-pinctrl.yaml
@@ -0,0 +1,82 @@
+# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    The Arm Mps3 pin controller is a node responsible for controlling
+    pin function selection and pin properties, such as routing a UART3 TX
+    to pin 1.
+
+    The node has the 'pinctrl' node label set in your SoC's devicetree,
+    so you can modify it like this:
+
+      &pinctrl {
+              /* your modifications go here */
+      };
+
+    All device pin configurations should be placed in child nodes of the
+    'pinctrl' node, as shown in this example:
+
+      &pinctrl {
+        /* configuration for the usart0 "default" state */
+        uart3_default: uart3_default {
+          /* group 1 */
+          group1 {
+            /* configure P1 as UART3 TX */
+            pinmux = <UART3_TXD_EXP>;
+          };
+          /* group 2 */
+          group2 {
+            /* configure P0 as UART3 RX */
+            pinmux = <UART3_TXD_EXP>;
+            /* enable input on pin 1 */
+            input-enable;
+          };
+        };
+      };
+
+    The 'uart3_default' child node encodes the pin configurations for a
+    particular state of a device; in this case, the default (that is, active)
+    state.
+
+    As shown, pin configurations are organized in groups within each child node.
+    Each group can specify a list of pin function selections in the 'pinmux'
+    property. Here is a list of supported standard pin properties:
+    - input-enable
+
+    A group can also specify shared pin properties common to all the specified
+    pins, such as the 'input-enable' property in group 2.
+
+    To link pin configurations with a device, use a pinctrl-N property for some
+    number N, like this example you could place in your board's DTS file:
+
+       #include "board-pinctrl.dtsi"
+
+       &uart3 {
+             pinctrl-0 = <&uart3_default>;
+             pinctrl-1 = <&uart3_sleep>;
+             pinctrl-names = "default", "sleep";
+       };
+
+
+compatible: "arm,mps3-pinctrl"
+
+include: base.yaml
+
+child-binding:
+  description: |
+    Definitions for a pinctrl state.
+  child-binding:
+
+    include:
+      - name: pincfg-node.yaml
+        property-allowlist:
+          - input-enable
+
+    properties:
+      pinmux:
+        required: true
+        type: array
+        description: |
+          An array of pins sharing the same group properties. Each
+          element of the array is an integer constructed from the
+          pin number and the alternative function of the pin.
diff --git a/dts/bindings/pinctrl/arm,v2m_beetle-pinctrl.yaml b/dts/bindings/pinctrl/arm,v2m_beetle-pinctrl.yaml
new file mode 100644
index 00000000000..0581c6f9693
--- /dev/null
+++ b/dts/bindings/pinctrl/arm,v2m_beetle-pinctrl.yaml
@@ -0,0 +1,40 @@
+# Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    The node has the 'pinctrl' node label set in your SoC's devicetree,
+    so you can modify it like this:
+
+      &pinctrl {
+              /* your modifications go here */
+      };
+
+    All device pin configurations should be placed in child nodes of the
+    'pinctrl' node, as shown in this example:
+
+      /* You can put this in places like a board-pinctrl.dtsi file in
+       * your board directory, or a devicetree overlay in your application.
+       */
+
+compatible: "arm,v2m_beetle-pinctrl"
+
+include: base.yaml
+
+child-binding:
+  description: |
+    Definitions for a pinctrl state.
+  child-binding:
+
+    include:
+      - name: pincfg-node.yaml
+        property-allowlist:
+          - input-enable
+
+    properties:
+      pinmux:
+        required: true
+        type: array
+        description: |
+          An array of pins sharing the same group properties. Each
+          element of the array is an integer constructed from the
+          pin number and the alternative function of the pin.
diff --git a/dts/bindings/pinctrl/atmel,sam-pinctrl.yaml b/dts/bindings/pinctrl/atmel,sam-pinctrl.yaml
index 63ac1082755..a2bef2f529e 100644
--- a/dts/bindings/pinctrl/atmel,sam-pinctrl.yaml
+++ b/dts/bindings/pinctrl/atmel,sam-pinctrl.yaml
@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Atmel SAM Pinctrl container node
+  Atmel SAM Pinctrl Container
 
   The Atmel SAM pin controller is a singleton node responsible for controlling
   pin function selection and pin properties. For example, you can use this node
diff --git a/dts/bindings/pinctrl/atmel,sam0-pinctrl.yaml b/dts/bindings/pinctrl/atmel,sam0-pinctrl.yaml
index 7557c5e52e9..2616182b61e 100644
--- a/dts/bindings/pinctrl/atmel,sam0-pinctrl.yaml
+++ b/dts/bindings/pinctrl/atmel,sam0-pinctrl.yaml
@@ -3,7 +3,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Atmel SAM0 Pinctrl container node
+  Atmel SAM0 Pinctrl Container
 
   The Atmel SAM0 pin controller is a singleton node responsible for controlling
   pin function selection and pin properties. For example, you can use this node
diff --git a/dts/bindings/pinctrl/bflb,pinctrl.yaml b/dts/bindings/pinctrl/bflb,pinctrl.yaml
new file mode 100644
index 00000000000..b67404dc85d
--- /dev/null
+++ b/dts/bindings/pinctrl/bflb,pinctrl.yaml
@@ -0,0 +1,91 @@
+# Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+description: Bouffalo Lab Pinctrl node
+
+compatible: "bflb,pinctrl"
+
+include: base.yaml
+
+properties:
+  "#address-cells":
+    required: true
+    const: 1
+  "#size-cells":
+    required: true
+    const: 1
+
+child-binding:
+  description: |
+    Bouffalo Lab pin controller pin configuration nodes. Each node is composed
+    by one or more groups, each defining the configuration for a set of pins.
+
+  child-binding:
+    description: |
+      Bouffalo Lab pin controller pin configuration group. Each group contains
+      a list of pins sharing the same set of properties. Example:
+
+      uart0_default: uart0_default {
+        /* group 1 (name is arbitrary) */
+        group1 {
+          /* configure to uart0 function plus modem interrupt, pin 7 as UART_RX
+             pin 16 as UART_TX and finally pin 18 as gpio */
+          pinmux = <GPIO7_UART0_RX>,
+                   <GPIO16_UART0_TX>;
+          bias-pull-up;
+          input-schmitt-enable;
+        };
+      };
+
+      uart0_sleep: uart0_sleep {
+        group1 {
+          pinmux = <GPIO7_UART0_RX>,
+                   <GPIO16_UART0_TX>;
+          bias-high-impedance;
+        };
+      };
+
+      The list of supported standard properties:
+      - bias-high-impedance: Disable pull-up/down (default behavior, not
+        required).
+      - bias-pull-up: Enable pull-up resistor.
+      - bias-pull-down: Enable pull-down resistor.
+      - input-enable: Enable GPIO as input (default behavior, not required).
+      - input-schmitt-enable: Enable Schimitt Trigger when GPIO is Input.
+      - output-enable: Enable GPIO as output.
+
+      Note that bias options are mutually exclusive. It is the same with GPIO
+      input/output enable options.
+
+    include:
+      - name: pincfg-node.yaml
+        property-allowlist:
+          - bias-high-impedance
+          - bias-pull-down
+          - bias-pull-up
+          - input-enable
+          - input-schmitt-enable
+          - output-enable
+
+    properties:
+      pinmux:
+        required: true
+        type: array
+        description: |
+          An array of pins sharing the same group properties. The pins should be
+          defined using the BFLB_PINMUX utility macro that encode all the pin
+          route matrix.
+      drive-strength:
+        type: int
+        default: 0
+        enum:
+          - 0     # Default value, lower strength, 8mA
+          - 1     # 9.6mA
+          - 2     # 11.2mA
+          - 3     # highest strength, 12.8mA
+        description: |
+          Pin drive strength. It tunes pin max current where 0 means lower
+          value, which is the default, and 3 represents max drive strength.
+          The driver will automatically apply the default value (8mA) to all
+          pins to save power.
diff --git a/dts/bindings/pinctrl/espressif,esp32-pinctrl.yaml b/dts/bindings/pinctrl/espressif,esp32-pinctrl.yaml
index c55372094ae..5fe2c5e8f42 100644
--- a/dts/bindings/pinctrl/espressif,esp32-pinctrl.yaml
+++ b/dts/bindings/pinctrl/espressif,esp32-pinctrl.yaml
@@ -2,6 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
+    ESP32 pin controller
+
     Espressif's pin controller is in charge of controlling pin configurations, pin
     functionalities and pin properties as defined by pin states. In its turn, pin
     states are composed by groups of pre-defined pin muxing definitions and user
diff --git a/dts/bindings/pinctrl/infineon,cat1-pinctrl.yaml b/dts/bindings/pinctrl/infineon,cat1-pinctrl.yaml
index 2335a08b098..d2345bdd677 100644
--- a/dts/bindings/pinctrl/infineon,cat1-pinctrl.yaml
+++ b/dts/bindings/pinctrl/infineon,cat1-pinctrl.yaml
@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Infineon CAT1 Pinctrl container node
+  Infineon CAT1 Pinctrl Container
 
   This is a singleton node responsible for controlling the pin function selection
   and pin properties. For example, you can use this node to route
diff --git a/dts/bindings/pinctrl/ite,it8xxx2-pinctrl-func.yaml b/dts/bindings/pinctrl/ite,it8xxx2-pinctrl-func.yaml
index 4fe47c5ba03..ccc59972f28 100644
--- a/dts/bindings/pinctrl/ite,it8xxx2-pinctrl-func.yaml
+++ b/dts/bindings/pinctrl/ite,it8xxx2-pinctrl-func.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 ITE Corporation. All Rights Reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-description: ITE IT8XXX2 pin controller function node
+description: ITE IT8XXX2 Pin Controller
 
 compatible: "ite,it8xxx2-pinctrl-func"
 
diff --git a/dts/bindings/pinctrl/microchip,mec5-pinctrl.yaml b/dts/bindings/pinctrl/microchip,mec5-pinctrl.yaml
index b469aa41a03..c27defda8a7 100644
--- a/dts/bindings/pinctrl/microchip,mec5-pinctrl.yaml
+++ b/dts/bindings/pinctrl/microchip,mec5-pinctrl.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    Microchip XEC Pin controller Node
+    Microchip XEC Pin controller
+
     Based on pincfg-node.yaml binding.
     The MCHP XEC pin controller is a singleton node responsible for controlling
     pin function selection and pin properties. For example, you can use this
diff --git a/dts/bindings/pinctrl/microchip,xec-pinctrl.yaml b/dts/bindings/pinctrl/microchip,xec-pinctrl.yaml
index 40bdc1a3e33..186db1c39f0 100644
--- a/dts/bindings/pinctrl/microchip,xec-pinctrl.yaml
+++ b/dts/bindings/pinctrl/microchip,xec-pinctrl.yaml
@@ -3,7 +3,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    Microchip XEC Pin controller Node
+    Microchip XEC Pin Controller
+
     Based on pincfg-node.yaml binding.
     The MCHP XEC pin controller is a singleton node responsible for controlling
     pin function selection and pin properties. For example, you can use this
diff --git a/dts/bindings/pinctrl/nuvoton,npcx-scfg.yaml b/dts/bindings/pinctrl/nuvoton,npcx-scfg.yaml
index b8c881fbffa..02912e0935d 100644
--- a/dts/bindings/pinctrl/nuvoton,npcx-scfg.yaml
+++ b/dts/bindings/pinctrl/nuvoton,npcx-scfg.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2020 Nuvoton Technology Corporation.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Nuvoton, NPCX System Configuration (Pinmux, 1.8V support and so on) node
+description: Nuvoton NPCX System Configuration (Pinmux, 1.8V support and so on)
 
 compatible: "nuvoton,npcx-scfg"
 
diff --git a/dts/bindings/pinctrl/nxp,imx-gpr.yaml b/dts/bindings/pinctrl/nxp,imx-gpr.yaml
index f6944de8860..7e4b1328d4c 100644
--- a/dts/bindings/pinctrl/nxp,imx-gpr.yaml
+++ b/dts/bindings/pinctrl/nxp,imx-gpr.yaml
@@ -1,7 +1,14 @@
 # Copyright (c) 2021, NXP
 # SPDX-License-Identifier: Apache-2.0
 
-description: i.MX IOMUXC node
+description: |
+  i.MX IOMUXC
+
+  The specifier space "pinmux" of this binding should have two cells describing
+  the resources needed from the GPR registers.
+  For each specifier, the first cell should be the offset of the GPR register in bytes
+  from the base address of the GPR device base address. The second cell should be a
+  bitmask indicating which bits in the specified register are relevant to the referencing device.
 
 compatible: "nxp,imx-gpr"
 
@@ -12,5 +19,5 @@ properties:
     required: true
 
 pinmux-cells:
-  - pin
-  - function
+  - offset
+  - mask
diff --git a/dts/bindings/pinctrl/nxp,mci-io-mux.yaml b/dts/bindings/pinctrl/nxp,mci-io-mux.yaml
index d717c0374e1..94b9e747df3 100644
--- a/dts/bindings/pinctrl/nxp,mci-io-mux.yaml
+++ b/dts/bindings/pinctrl/nxp,mci-io-mux.yaml
@@ -2,7 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  MCI IO MUX pin control node. This node defines pin configurations in pin
+  MCI IO MUX Pin Controller
+
+  This node defines pin configurations in pin
   groups, and has the 'pinctrl' node identifier in the SOC's devicetree. Each
   group within the pin configuration defines a peripheral's pin configuration.
   Each numbered subgroup represents pins with shared configuration for that
diff --git a/dts/bindings/pinctrl/nxp,port-pinctrl.yaml b/dts/bindings/pinctrl/nxp,port-pinctrl.yaml
index ec096802250..02bd6f9f573 100644
--- a/dts/bindings/pinctrl/nxp,port-pinctrl.yaml
+++ b/dts/bindings/pinctrl/nxp,port-pinctrl.yaml
@@ -2,7 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  NXP PORT pinctrl node. This node will define pin configurations in pin
+  NXP PORT Pin Controller
+
+  This node will define pin configurations in pin
   groups, and has the 'pinctrl' node identifier in the SOC's devicetree. Each
   group within the pin configuration defines the pin configuration for a
   peripheral, and each numbered subgroup in the pin group defines all the pins
diff --git a/dts/bindings/pinctrl/nxp,port-pinmux.yaml b/dts/bindings/pinctrl/nxp,port-pinmux.yaml
index 7bdb56b2b5e..c0dbda759f4 100644
--- a/dts/bindings/pinctrl/nxp,port-pinmux.yaml
+++ b/dts/bindings/pinctrl/nxp,port-pinmux.yaml
@@ -1,4 +1,4 @@
-description: NXP PORT pinmux node
+description: NXP PORT Pin Controller
 
 compatible: "nxp,port-pinmux"
 
diff --git a/dts/bindings/pinctrl/nxp,rt-iocon-pinctrl.yaml b/dts/bindings/pinctrl/nxp,rt-iocon-pinctrl.yaml
index e98eeaea420..916f6b4ee48 100644
--- a/dts/bindings/pinctrl/nxp,rt-iocon-pinctrl.yaml
+++ b/dts/bindings/pinctrl/nxp,rt-iocon-pinctrl.yaml
@@ -2,7 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  RT600/RT500 pin control node. This node defines pin configurations in pin
+  RT600/RT500 Pin Controller
+
+  This node defines pin configurations in pin
   groups, and has the 'pinctrl' node identifier in the SOC's devicetree. Each
   group within the pin configuration defines a peripheral's pin configuration.
   Each numbered subgroup represents pins with shared configuration for that
diff --git a/dts/bindings/pinctrl/nxp,s32k3-pinctrl.yaml b/dts/bindings/pinctrl/nxp,s32k3-pinctrl.yaml
index d4e8ddd99f2..b4cfd4e5784 100644
--- a/dts/bindings/pinctrl/nxp,s32k3-pinctrl.yaml
+++ b/dts/bindings/pinctrl/nxp,s32k3-pinctrl.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  NXP S32 pinctrl node for S32K3 SoCs.
+  NXP S32 Pin Controller for S32K3 SoCs
 
   The NXP S32 pin controller is a singleton node responsible for controlling
   the pin function selection and pin properties. This node, labeled 'pinctrl' in
diff --git a/dts/bindings/pinctrl/nxp,s32ze-pinctrl.yaml b/dts/bindings/pinctrl/nxp,s32ze-pinctrl.yaml
index 0826fce73ac..aa5567a0826 100644
--- a/dts/bindings/pinctrl/nxp,s32ze-pinctrl.yaml
+++ b/dts/bindings/pinctrl/nxp,s32ze-pinctrl.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  NXP S32 pinctrl node for S32Z/E SoCs.
+  NXP S32 Pin Controller for S32Z/E SoCs
 
   The NXP S32 pin controller is a singleton node responsible for controlling
   the pin function selection and pin properties. This node, labeled 'pinctrl' in
diff --git a/dts/bindings/pinctrl/openisa,rv32m1-pinctrl.yaml b/dts/bindings/pinctrl/openisa,rv32m1-pinctrl.yaml
index d53d1233ebc..77df30fc9b0 100644
--- a/dts/bindings/pinctrl/openisa,rv32m1-pinctrl.yaml
+++ b/dts/bindings/pinctrl/openisa,rv32m1-pinctrl.yaml
@@ -3,7 +3,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  OpenISA RV32M1 pinctrl node. This node will define pin configurations in pin groups,
+  OpenISA RV32M1 Pin Controller
+
+  This node will define pin configurations in pin groups,
   and has the 'pinctrl' node identifier in the SOC's devicetree. Each group
   within the pin configuration defines the pin configuration for a peripheral,
   and each numbered subgroup in the pin group defines all the pins for that
diff --git a/dts/bindings/pinctrl/openisa,rv32m1-pinmux.yaml b/dts/bindings/pinctrl/openisa,rv32m1-pinmux.yaml
index 436531c8db0..1cb37db5a98 100644
--- a/dts/bindings/pinctrl/openisa,rv32m1-pinmux.yaml
+++ b/dts/bindings/pinctrl/openisa,rv32m1-pinmux.yaml
@@ -1,4 +1,4 @@
-description: RV32M1 pinmux node
+description: RV32M1 pinmux
 
 compatible: "openisa,rv32m1-pinmux"
 
diff --git a/dts/bindings/pinctrl/realtek,rts5912-pinctrl.yaml b/dts/bindings/pinctrl/realtek,rts5912-pinctrl.yaml
index c5b00ae822a..17180cf00c5 100644
--- a/dts/bindings/pinctrl/realtek,rts5912-pinctrl.yaml
+++ b/dts/bindings/pinctrl/realtek,rts5912-pinctrl.yaml
@@ -3,8 +3,7 @@
 # Copyright (c) 2024 Realtek Semiconductor Corporation, SIBG-SD7
 #
 
-description: |
-     This binding gives a base representation of the pins configuration
+description: Realtek RTS5912 Pin Controller
 
 compatible: "realtek,rts5912-pinctrl"
 
diff --git a/dts/bindings/pinctrl/renesas,rcar-pfc.yaml b/dts/bindings/pinctrl/renesas,rcar-pfc.yaml
index 1743f213193..80c990251e5 100644
--- a/dts/bindings/pinctrl/renesas,rcar-pfc.yaml
+++ b/dts/bindings/pinctrl/renesas,rcar-pfc.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    Renesas R-Car Pin Function Controller node
+    Renesas R-Car Pin Function Controller
+
     This binding gives a base representation of the R-Car pins configuration.
     The R-Car pin controller is a singleton node responsible for controlling
     pin function selection and pin properties. For example, you can use this
diff --git a/dts/bindings/pinctrl/renesas,rza-pinctrl.yaml b/dts/bindings/pinctrl/renesas,rza-pinctrl.yaml
new file mode 100644
index 00000000000..7b2da83da1f
--- /dev/null
+++ b/dts/bindings/pinctrl/renesas,rza-pinctrl.yaml
@@ -0,0 +1,105 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Below generic example shows of supported pinctrl definitions:
+
+    #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza-common.h>
+    example_pins: device_pin {
+        device-pinmux {
+          pinmux = <RZA_PINMUX(PORT_08, 1, 5)>,
+                   <RZA_PINMUX(PORT_08, 2, 5)>;
+          bias_pull_up;
+          renesas,filter = RZA_FILTER_SET(RZA_FILNUM_8_STAGE,RZA_FILCLKSEL_DIV_18000);
+          drive-strength = <1>;
+          slew-rate = "fast";
+        };
+
+        device-spins {
+          pins = <BSP_IO_XSPI_IO0>, <BSP_IO_XSPI_IO4>;
+          input-enable;
+          renesas,filter = RZA_FILTER_SET(RZA_FILNUM_8_STAGE,RZA_FILCLKSEL_DIV_18000);
+          drive-strength = <2>;
+          slew-rate = "fast";
+        };
+      };
+
+
+compatible: renesas,rza-pinctrl
+
+include: base.yaml
+properties:
+  reg:
+    required: true
+
+  reg-names:
+    required: true
+
+child-binding:
+  description: |
+    This RZA pins mux/cfg nodes description.
+
+  child-binding:
+    description: |
+      The RZA pinmux/pincfg configuration nodes description.
+
+    include:
+    - name: pincfg-node.yaml
+      property-allowlist:
+      - bias-disable
+      - bias-high-impedance
+      - bias-pull-down
+      - bias-pull-up
+      - bias-pull-pin-default
+      - drive-strength
+      - input-enable
+      - input-disable
+      - output-enable
+      - power-source
+      - low-power-enable
+      - low-power-disable
+
+    properties:
+      pinmux:
+        type: array
+        description: |
+          Pinmux configuration node.
+          Values are constructed from GPIO port number, pin number, and
+          alternate function configuration number using the RZA_PINMUX()
+          helper macro in pinctrl_rza.h
+
+      pins:
+        type: array
+        description: |
+          Special Purpose pins configuration node.
+          Values are define in pinctrl_rza.h.
+          Ex: BSP_IO_XSPI_IO0,BSP_IO_I3C_SCL,...
+
+      drive-strength:
+        type: int
+        default: 0
+        description: |
+          Maximum sink or source current in mA for pin which shall be selected
+          depending on device and pin group.
+
+      renesas,filter:
+        type: int
+        default: 0
+        description: |
+          Digital Noise Filter configuration for a pin which shall be defined
+          using RZA_FILTER_SET() helper macro in pinctrl_rza.h to specify
+          FILNUM and FILCLKSEL. With 24Mhz external clock:
+          - min debounce time will be 166.666ns for FILNUM=0 and FILCLKSEL=0
+          - max debounce time will be 24ms for FILNUM=3 and FILCLKSEL=3.
+          This property intentionally redefined to avoid unnecessary conversation from usec to
+          FILNUM and FILCLKSEL values depending on external clock value as this configuration
+          is static.
+
+      slew-rate:
+        type: string
+        default: "fast"
+        enum:
+        - "slow"
+        - "fast"
+        description: |
+          Select slew rate for pin.
diff --git a/dts/bindings/pinctrl/renesas,rza2m-pinctrl.yaml b/dts/bindings/pinctrl/renesas,rza2m-pinctrl.yaml
new file mode 100644
index 00000000000..a9fb8aeebb2
--- /dev/null
+++ b/dts/bindings/pinctrl/renesas,rza2m-pinctrl.yaml
@@ -0,0 +1,59 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Renesas RZ/A2M pin controller
+
+    The Renesas RZ/A2M pin controller is a node responsible for controlling
+    pin function selection and pin properties, such as routing the TX and RX of UART4
+    to pin 0 and pin 1 of port 9.
+
+    #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza2m.h>
+    example_pins: device_pin {
+        device-pinmux {
+          pinmux = <RZA2M_PINMUX(PORT_09, 0, 4)>, /* TXD */
+                   <RZA2M_PINMUX(PORT_09, 1, 4)>; /* RXD */
+        };
+    };
+
+compatible: "renesas,rza2m-pinctrl"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+child-binding:
+  description: |
+    This RZA2M pins mux/cfg nodes description.
+
+  child-binding:
+    description: |
+      The RZA2M pinmux/pincfg configuration nodes description.
+
+    include:
+      - name: pincfg-node.yaml
+
+    properties:
+      pinmux:
+        type: array
+        required: true
+        description: |
+          Pinmux configuration node.
+          Values are constructed from GPIO port number, pin number, and
+          alternate function configuration number using the RZA2M_PINMUX()
+          helper macro in pinctrl-rza2m.h
+
+      drive-strength:
+        type: int
+        enum:
+          - 0 # 2 mA
+          - 1 # 8 mA
+          - 2 # 12 mA
+        description: |
+          The DSCR register controls driving ability of the ports.
+          The PCKIO register controls driving ability of the CKIO pin.
+          The PSDMMC(0/1/2) registers specify the driving ability of the pins of the SD/MMC.
+          The PSPIBSC register specifies the driving ability of the pins
+            of the SPI multi I/O bus controller.
diff --git a/dts/bindings/pinctrl/renesas,rzg-pinctrl.yaml b/dts/bindings/pinctrl/renesas,rzg-pinctrl.yaml
index 2b17a67857c..10aca130db4 100644
--- a/dts/bindings/pinctrl/renesas,rzg-pinctrl.yaml
+++ b/dts/bindings/pinctrl/renesas,rzg-pinctrl.yaml
@@ -1,11 +1,18 @@
 # Copyright (c) 2024 Epam Systems
-# Copyright (c) 2024 Renesas Electronics Corporation
+# Copyright (c) 2024-2025 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Below generic example shows of supported pinctrl definitions:
+    Renesas RZ/G pin controller
 
-    #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl_rzg3s.h>
+    The Renesas RZ/G pin controller is a node responsible for controlling
+    pin function selection and pin properties.
+
+    The pre-defined combinations for the RZ/G variants are defined in the below headers
+    - pinctrl-rzg-common.h for RZ/G3S
+    - pinctrl-rzg2-common.h for RZ/G2L, RZ/G2LC
+
+    #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg(2)-common.h>
     example_pins: device_pin {
         device-pinmux {
           pinmux = <RZG_PINMUX(PORT_08, 1, 5)>,
@@ -65,13 +72,13 @@ child-binding:
           Pinmux configuration node.
           Values are constructed from GPIO port number, pin number, and
           alternate function configuration number using the RZG_PINMUX()
-          helper macro in pinctrl_rzg.h
+          helper macro in pinctrl-rzg(2)-common.h.
 
       pins:
         type: array
         description: |
           Special Purpose pins configuration node.
-          Values are define in pinctrl_rzg.h.
+          Values are define in pinctrl-rzg(2)-common.h.
           Ex: BSP_IO_XSPI_IO0,BSP_IO_I3C_SCL,...
 
       drive-strength:
diff --git a/dts/bindings/pinctrl/renesas,rzn-pinctrl.yaml b/dts/bindings/pinctrl/renesas,rzn-pinctrl.yaml
new file mode 100644
index 00000000000..feafa4a650a
--- /dev/null
+++ b/dts/bindings/pinctrl/renesas,rzn-pinctrl.yaml
@@ -0,0 +1,95 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+
+description: |
+    The Renesas RZ/N2L pin controller is a node responsible for controlling
+    pin function selection and pin properties, such as routing the TX and RX of UART0
+    to pin 5 and pin 6 of port 16.
+
+    The node has the 'pinctrl' node label set in your SoC's devicetree,
+    so you can modify it like this:
+
+      &pinctrl {
+              /* your modifications go here */
+      };
+
+    All device pin configurations should be placed in child nodes of the
+    'pinctrl' node, as shown in this example:
+
+      /* You can put this in places like a board-pinctrl.dtsi file in
+       * your board directory, or a devicetree overlay in your application.
+       */
+
+      /* include pre-defined combinations for the SoC variant used by the board */
+      #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzn-common.h>
+
+      &pinctrl {
+        uart0_pins: uart0 {
+          group1 {
+            pinmux = <RZN_PINMUX(PORT_16, 5, 1)>; /* TXD */
+          };
+          group2 {
+            pinmux = <RZN_PINMUX(PORT_16, 6, 2)>; /* RXD */
+            input-enable;
+          };
+        };
+      };
+
+    The 'uart0_pins' child node encodes the pin configurations for a
+    particular state of a device; in this case, the default (that is, active)
+    state.
+
+    As shown, pin configurations are organized in groups within each child node.
+    Each group can specify a list of pin function selections in the 'pinmux'
+    property.
+
+    A group can also specify shared pin properties common to all the specified
+    pins, such as the 'input-enable' property in group 2.
+
+compatible: "renesas,rzn-pinctrl"
+
+include: base.yaml
+
+child-binding:
+  description: |
+    Definitions for a pinctrl state.
+  child-binding:
+
+    include:
+      - name: pincfg-node.yaml
+        property-allowlist:
+          - input-enable
+          - output-enable
+          - output-high
+          - bias-pull-up
+          - bias-pull-down
+          - input-schmitt-enable
+
+    properties:
+      pinmux:
+        required: true
+        type: array
+        description: |
+          An array of pins sharing the same group properties. Each
+          element of the array is an integer constructed from the
+          pin number and the alternative function of the pin.
+      drive-strength:
+        type: string
+        enum:
+          - "low"
+          - "middle"
+          - "high"
+          - "ultrahigh"
+        default: "low"
+        description: |
+          The drive strength of a pin, relative to full-driver strength.
+          The default value is "low", which is the reset value.
+      slew-rate:
+        type: string
+        enum:
+          - "slow"
+          - "fast"
+        default: "slow"
+        description: |
+          Select slew rate for a pin. The default is slow, which is the reset value.
diff --git a/dts/bindings/pinctrl/renesas,rzt-pinctrl.yaml b/dts/bindings/pinctrl/renesas,rzt-pinctrl.yaml
new file mode 100644
index 00000000000..e8df2996b7f
--- /dev/null
+++ b/dts/bindings/pinctrl/renesas,rzt-pinctrl.yaml
@@ -0,0 +1,96 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Renesas RZ/T pin controller
+
+    The Renesas RZ/T pin controller is a node responsible for controlling
+    pin function selection and pin properties, such as routing the TX and RX of UART0
+    to pin 5 and pin 6 of port 16.
+
+    The node has the 'pinctrl' node label set in your SoC's devicetree,
+    so you can modify it like this:
+
+      &pinctrl {
+              /* your modifications go here */
+      };
+
+    All device pin configurations should be placed in child nodes of the
+    'pinctrl' node, as shown in this example:
+
+      /* You can put this in places like a board-pinctrl.dtsi file in
+       * your board directory, or a devicetree overlay in your application.
+       */
+
+      /* include pre-defined combinations for the SoC variant used by the board */
+      #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzt-common.h>
+
+      &pinctrl {
+        uart0_default: uart0_default {
+          group1 {
+            pinmux = <RZT_PINMUX(PORT_16, 5, 1)>;
+          };
+          group2 {
+            pinmux = <RZT_PINMUX(PORT_16, 6, 2)>;
+            input-enable;
+          };
+        };
+      };
+
+    The 'uart0_default' child node encodes the pin configurations for a
+    particular state of a device; in this case, the default (that is, active)
+    state.
+
+    As shown, pin configurations are organized in groups within each child node.
+    Each group can specify a list of pin function selections in the 'pinmux'
+    property.
+
+    A group can also specify shared pin properties common to all the specified
+    pins, such as the 'input-enable' property in group 2.
+
+compatible: "renesas,rzt-pinctrl"
+
+include: base.yaml
+
+child-binding:
+  description: |
+    Definitions for a pinctrl state.
+  child-binding:
+
+    include:
+      - name: pincfg-node.yaml
+        property-allowlist:
+          - input-enable
+          - output-enable
+          - output-high
+          - bias-pull-up
+          - bias-pull-down
+          - input-schmitt-enable
+
+    properties:
+      pinmux:
+        required: true
+        type: array
+        description: |
+          An array of pins sharing the same group properties. Each
+          element of the array is an integer constructed from the
+          pin number and the alternative function of the pin.
+      drive-strength:
+        type: string
+        enum:
+          - "low"
+          - "middle"
+          - "high"
+          - "ultrahigh"
+        default: "low"
+        description: |
+          The drive strength of a pin, relative to full-driver strength.
+          The default value is "low", which is the reset value.
+      slew-rate:
+        type: string
+        enum:
+          - "slow"
+          - "fast"
+        default: "slow"
+        description: |
+          Select slew rate for a pin. The default is slow, which is the reset value.
diff --git a/dts/bindings/pinctrl/renesas,rzv-pinctrl.yaml b/dts/bindings/pinctrl/renesas,rzv-pinctrl.yaml
new file mode 100644
index 00000000000..acf28285029
--- /dev/null
+++ b/dts/bindings/pinctrl/renesas,rzv-pinctrl.yaml
@@ -0,0 +1,101 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Renesas RZ/V pin controller
+
+    The Renesas RZ/V pin controller is a node responsible for controlling
+    pin function selection and pin properties, such as routing the TX and RX of UART2
+    to pin 0 and pin 1 of port 48.
+
+    #include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzv-common.h>
+    example_pins: device_pin {
+        device-pinmux {
+          pinmux = <RZV_PINMUX(PORT_04, 0, 2)>,
+                   <RZV_PINMUX(PORT_04, 1, 2);
+          bias_pull_up;
+          renesas,filter = RZV_FILTER_SET(RZV_FILNUM_8_STAGE,RZV_FILCLKSEL_DIV_18000);
+          drive-strength = <1>;
+          slew-rate = <fast>;
+        };
+
+        device-spins {
+          pins = <BSP_IO_QSPI0_IO0>, <BSP_IO_QSPI0_IO3>;
+          input-enable;
+          renesas,filter = RZV_FILTER_SET(RZV_FILNUM_8_STAGE,RZV_FILCLKSEL_DIV_18000);
+          drive-strength = <2>;
+          slew-rate = "fast";
+        };
+      };
+
+
+compatible: renesas,rzv-pinctrl
+
+include: base.yaml
+properties:
+  reg:
+    required: true
+
+  reg-names:
+    required: true
+
+child-binding:
+  description: |
+    This RZV pins mux/cfg nodes description.
+
+  child-binding:
+    description: |
+      The RZV pinmux/pincfg configuration nodes description.
+
+    include:
+    - name: pincfg-node.yaml
+      property-allowlist:
+      - bias-pull-down
+      - bias-pull-up
+      - drive-strength
+      - input-enable
+
+    properties:
+      pinmux:
+        type: array
+        description: |
+          Pinmux configuration node.
+          Values are constructed from GPIO port number, pin number, and
+          alternate function configuration number using the RZV_PINMUX()
+          helper macro in pinctrl-rzv-common.h
+
+      pins:
+        type: array
+        description: |
+          Special Purpose pins configuration node.
+          Values are define in pinctrl-rzv-common.h.
+          Ex: BSP_IO_QSPI0_IO0,BSP_IO_RIIC1_SCL,...
+
+      drive-strength:
+        type: int
+        default: 0
+        description: |
+          Maximum sink or source current in mA for pin which shell be selected
+          depending on device and pin group.
+
+      renesas,filter:
+        type: int
+        default: 0
+        description: |
+          Digital Noise Filter configuration for a pin which shell be defined
+          using RZV_FILTER_SET() helper macro in pinctrl-rzv-common.h to specify
+          FILNUM and FILCLKSEL. With 24Mhz external clock:
+          - min debounce time will be 166.666ns for FILNUM=0 and FILCLKSEL=0
+          - max debounce time will be 24ms for FILNUM=3 and FILCLKSEL=3.
+          This property intentionally redefined to avoid unnecessary conversation from usec to
+          FILNUM and FILCLKSEL values depending on external clock value as this configuration
+          is static.
+
+      slew-rate:
+        type: string
+        default: "fast"
+        enum:
+        - "slow"
+        - "fast"
+        description: |
+          Select slew rate for pin.
diff --git a/dts/bindings/pinctrl/silabs,dbus-pinctrl.yaml b/dts/bindings/pinctrl/silabs,dbus-pinctrl.yaml
index 410edd4cf5e..d0229c72a33 100644
--- a/dts/bindings/pinctrl/silabs,dbus-pinctrl.yaml
+++ b/dts/bindings/pinctrl/silabs,dbus-pinctrl.yaml
@@ -6,7 +6,8 @@ description: |
     pin function selection and pin properties. For example, you can use this
     node to route USART0 RX to pin PA1 and enable the pull-up resistor on the
     pin. This pin controller is used for devices that use DBUS (Digital Bus)
-    for alternate function configuration, including Series 2 devices.
+    for alternate function configuration, including Series 2 devices. It is
+    also capable of ABUS (Analog Bus) allocation.
 
     The pinctrl settings are referenced in a device tree peripheral node. For
     example when configuring a USART:
@@ -81,6 +82,24 @@ description: |
                                      Allowed in drive-push-pull and
                                      drive-open-drain modes.
 
+    ABUS allocation is performed using the 'silabs,analog-bus' property. This
+    property takes an array of buses to allocate. Example:
+
+      &pinctrl {
+        iadc0_default: iadc0_default {
+          group0 {
+            /* Allocate even bus 0 and odd bus 1 from GPIO port A for ADC use */
+            silabs,analog-bus = <ABUS_AEVEN0_IADC0>, <ABUS_AODD1_IADC0>;
+          }
+        };
+      };
+
+    A given group may contain a mix of analog bus allocations and digital pin
+    selections. Digital pin properties only apply to digital pins. Analog input
+    selection is not done through the pin controller, this is done in the devicetree
+    node for the respective peripheral using properties such as 'zephyr,input-positive'
+    for ADC.
+
 compatible: "silabs,dbus-pinctrl"
 
 include: base.yaml
@@ -107,7 +126,6 @@ child-binding:
 
     properties:
       pins:
-        required: true
         type: array
         description: |
           An array of pins sharing the same group properties. The pins should be
@@ -126,3 +144,10 @@ child-binding:
           for this pin. May be used in drive-push-pull and drive-open-drain
           modes.
         type: boolean
+
+      silabs,analog-bus:
+        type: array
+        description: |
+          Assign one or more analog buses to the given GPIO port. The bus should
+          be defined using the ABUS_<bus>_<peripheral> macros available from the
+          SoC DeviceTree files.
diff --git a/dts/bindings/pinctrl/silabs,si32-pinctrl.yaml b/dts/bindings/pinctrl/silabs,si32-pinctrl.yaml
index 183146d6990..5e205163489 100644
--- a/dts/bindings/pinctrl/silabs,si32-pinctrl.yaml
+++ b/dts/bindings/pinctrl/silabs,si32-pinctrl.yaml
@@ -2,8 +2,7 @@
 #
 # SPDX-License-Identifier: Apache-2.0
 
-description: |
-  Silabs Si32 pinctrl node
+description: Silabs Si32 Pin Controller
 
 compatible: "silabs,si32-pinctrl"
 
diff --git a/dts/bindings/pinctrl/silabs,siwx91x-pinctrl.yaml b/dts/bindings/pinctrl/silabs,siwx91x-pinctrl.yaml
new file mode 100644
index 00000000000..8dc8a9305ac
--- /dev/null
+++ b/dts/bindings/pinctrl/silabs,siwx91x-pinctrl.yaml
@@ -0,0 +1,63 @@
+# Copyright (c) 2023 Antmicro
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  The Silabs SiWx91x pin controller is a devicetree node tasked with selecting
+  the proper IO function for a given pin.
+
+  The pinctrl settings are referenced in a device tree peripheral node. For
+  example when configuring a UART:
+
+    &ulpuart {
+      pinctrl-0 = <&ulpuart_default>;
+      pinctrl-names = "default";
+    }
+
+  pinctrl-0 is a phandle that stores the pin settings for the peripheral, in
+  this example &ulpuart_default. This phandle is defined as a child node of the
+  'pinctrl' node, typically in a board-pinctrl.dtsi file in the board directory
+  or a device tree overlay in the application:
+
+    &pinctrl {
+      ulpuart_default: ulpuart_default {
+        out {
+          pinmux = <ULPUART_TX_ULP11>; /* Configure ULP pin 11 as ULPUART TX */
+        };
+        in {
+          pinmux = <ULPUART_RX_ULP9>; /* Configure ULP pin 9 as ULPUART RX */
+        };
+      };
+    };
+
+  The 'ulpuart_default' child node encodes the pin configurations for a
+  particular state of the device, the default (active) state.
+
+  Pin configurations are organized in groups within each child node. The name
+  given to groups is arbitrary. Each group can specify a list of pin function
+  selections in the `pinmux` property, as well as a selection of pin properties
+  as given by the rest of the properties on the group.
+
+compatible: "silabs,siwx91x-pinctrl"
+
+include: base.yaml
+
+child-binding:
+  description: |
+    Silabs SiWx91x pin configuration. Each child node defines
+    the configuration for a particular group of pins.
+  child-binding:
+    description: |
+      Silabs SiWx91x pin configuration group.
+    include:
+      - name: pincfg-node.yaml
+        property-allowlist: []
+
+    properties:
+      pinmux:
+        required: true
+        type: array
+        description: |
+          An array of pins sharing the same group properties. The pins should be
+          defined using the <peripheral>_<signal>_<pin> macros available from
+          the SoC DeviceTree files.
diff --git a/dts/bindings/pinctrl/st,stm32-pinctrl.yaml b/dts/bindings/pinctrl/st,stm32-pinctrl.yaml
index a9f41602643..0be9533919e 100644
--- a/dts/bindings/pinctrl/st,stm32-pinctrl.yaml
+++ b/dts/bindings/pinctrl/st,stm32-pinctrl.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    STM32 Pin controller Node
+    STM32 Pin controller.
+
     Based on pincfg-node.yaml binding.
 
     Note: `bias-disable` and `drive-push-pull` are default pin configurations.
@@ -54,8 +55,8 @@ child-binding:
       description: |
         Reused from
         https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
-        Integer array, represents gpio pin number and mux setting.
-        These defines are calculated as: ((port * 16 + line) << 8) | function
+        Integer represents gpio pin number and mux setting.
+        Each integer encodes a port, line and alternate function.
         With:
         - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
         - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
@@ -74,7 +75,7 @@ child-binding:
 
         To simplify the usage, macro is available to generate "pinmux" field.
         This macro is available here:
-          -include/zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h
+          -include/zephyr/dt-bindings/pinctrl/stm32-pinctrl.h
         Some examples of macro usage:
            GPIO A9 set as alternate function 2
         ... {
diff --git a/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml b/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml
index 77efa78c064..6de98d27058 100644
--- a/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml
+++ b/dts/bindings/pinctrl/st,stm32f1-pinctrl.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    STM32F1 Pin controller Node
+    STM32F1 Pin controller.
+
     Based on pincfg-node.yaml binding.
 
     Note: `bias-disable` and `drive-push-pull` are default pin configurations.
@@ -61,8 +62,8 @@ child-binding:
       description: |
         Adapted from
         https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
-        Integer array, represents gpio pin number and mux setting.
-        These defines are calculated as: ((port * 16 + line) << 8) | (function << 6) | remap)
+        Integer represents gpio pin number and mux setting.
+        Each integer encodes a port, line, alternate function and remap.
         With:
         - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
         - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
diff --git a/dts/bindings/pinctrl/ti,cc13xx-cc26xx-pinctrl.yaml b/dts/bindings/pinctrl/ti,cc13xx-cc26xx-pinctrl.yaml
index 307cb7c0090..063c65e568c 100644
--- a/dts/bindings/pinctrl/ti,cc13xx-cc26xx-pinctrl.yaml
+++ b/dts/bindings/pinctrl/ti,cc13xx-cc26xx-pinctrl.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    TI SimpleLink CC13xx / CC26xx pinctrl node.
+    TI SimpleLink CC13xx / CC26xx Pin Controller
 
     Device pin configuration should be placed in the child nodes of this node.
     Populate the 'pinmux' field with a pair consisting of a pin number and its IO
diff --git a/dts/bindings/pinctrl/ti,cc23x0-pinctrl.yaml b/dts/bindings/pinctrl/ti,cc23x0-pinctrl.yaml
new file mode 100644
index 00000000000..ce23e6b9035
--- /dev/null
+++ b/dts/bindings/pinctrl/ti,cc23x0-pinctrl.yaml
@@ -0,0 +1,62 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+# Copyright (c) 2024 BayLibre, SAS
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    TI SimpleLink CC23X0 Pin Controller
+
+    Device pin configuration should be placed in the child nodes of this node.
+    Populate the 'pinmux' field with a pair consisting of a pin number and its IO
+    functions.
+
+    The node has the 'pinctrl' node label set in your SoC's devicetree,
+    so you can modify it like this:
+
+      &pinctrl {
+              /* your modifications go here */
+      };
+
+    All device pin configurations should be placed in child nodes of the
+    'pinctrl' node, as in the i2c0 example shown at the end.
+
+    Here is a list of
+    supported standard pin properties:
+
+    - bias-disable: Disable pull-up/down.
+    - bias-pull-down: Enable pull-down resistor.
+    - bias-pull-up: Enable pull-up resistor.
+    - drive-open-drain: Output driver is open-drain.
+    - drive-open-source: Output driver is open-source.
+    - input-enable: enable input.
+    - input-schmitt-enable: enable input schmitt circuit.
+
+compatible: "ti,cc23x0-pinctrl"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+child-binding:
+  description: |
+    This binding gives a base representation of the CC23X0
+    pins configuration.
+
+  include:
+    - name: pincfg-node.yaml
+      property-allowlist:
+        - bias-disable
+        - bias-pull-down
+        - bias-pull-up
+        - drive-open-drain
+        - drive-open-source
+        - input-enable
+        - input-schmitt-enable
+
+  properties:
+    pinmux:
+      required: true
+      type: array
+      description: |
+        CC23X0 pin's configuration (IO pin, IO function).
diff --git a/dts/bindings/pinctrl/ti,k3-pinctrl.yaml b/dts/bindings/pinctrl/ti,k3-pinctrl.yaml
index 600baa3292f..65abd04f597 100644
--- a/dts/bindings/pinctrl/ti,k3-pinctrl.yaml
+++ b/dts/bindings/pinctrl/ti,k3-pinctrl.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  TI K3 pinctrl node.
+  TI K3 Pin Controller
 
   Pins can be configured using the following macro "K3_PINMUX(offset, value, mux_mode)".
   offset - the pin attribute register offset from the base address.
diff --git a/dts/bindings/pinctrl/wch,20x_30x-afio.yaml b/dts/bindings/pinctrl/wch,20x_30x-afio.yaml
new file mode 100644
index 00000000000..7e7ccf6670c
--- /dev/null
+++ b/dts/bindings/pinctrl/wch,20x_30x-afio.yaml
@@ -0,0 +1,52 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+description: WCH CH32V20x/30x AFIO
+
+compatible: "wch,20x_30x-afio"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+  "#address-cells":
+    required: true
+    const: 1
+  "#size-cells":
+    required: true
+    const: 1
+
+child-binding:
+  description: |
+    Each child node defines the configuration for a particular state.
+  child-binding:
+    description: |
+      The grandchild nodes group pins that share the same pin configuration.
+
+    include:
+      - name: pincfg-node.yaml
+        property-allowlist:
+          - bias-high-impedance
+          - bias-pull-up
+          - bias-pull-down
+          - drive-open-drain
+          - drive-push-pull
+          - output-high
+          - output-low
+
+    properties:
+      slew-rate:
+        type: string
+        default: "max-speed-2mhz"
+        enum:
+          - "max-speed-10mhz"
+          - "max-speed-2mhz"
+          - "max-speed-50mhz"
+
+      pinmux:
+        required: true
+        type: array
+        description: |
+          An array of pins sharing the same group properties. The pins should
+          be defined using pre-defined macros.
diff --git a/dts/bindings/pinctrl/xlnx,pinctrl-zynqmp.yaml b/dts/bindings/pinctrl/xlnx,pinctrl-zynqmp.yaml
index 7a5af3a2b7d..c3b16f0a0ad 100644
--- a/dts/bindings/pinctrl/xlnx,pinctrl-zynqmp.yaml
+++ b/dts/bindings/pinctrl/xlnx,pinctrl-zynqmp.yaml
@@ -2,8 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  Xilinx ZynqMP SoC pinctrl node. It allows configuration of pin assignments
-  for the supported peripherals.
+  Xilinx ZynqMP SoC Pin Controller
+
+  It allows configuration of pin assignments for the supported peripherals.
 
   See Zynq UltraScale+ Devices Register Reference (UG1087) for details regarding
   valid pin assignments
diff --git a/dts/bindings/power-domain/power-domain-soc-state-change.yaml b/dts/bindings/power-domain/power-domain-soc-state-change.yaml
new file mode 100644
index 00000000000..6f5955241d1
--- /dev/null
+++ b/dts/bindings/power-domain/power-domain-soc-state-change.yaml
@@ -0,0 +1,23 @@
+# Copyright 2024-25 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  This power domain will Turn On and Off devices when transitioning
+  in and out a specified Power State. Power States that trigger this
+  action is specified via the onoff-power-states property.
+
+compatible: "power-domain-soc-state-change"
+
+include: power-domain.yaml
+
+properties:
+  onoff-power-states:
+    type: phandles
+    description: |
+      List of power management states.
+      The registered devices will be turned off before the PM subsystem
+      enters these PM states. The devices will be turned on after the
+      PM subsystem exits these PM states.
+
+  "#power-domain-cells":
+    const: 0
diff --git a/dts/bindings/power/ambiq,pwrctrl.yaml b/dts/bindings/power/ambiq,pwrctrl.yaml
deleted file mode 100644
index 701d65c9f9e..00000000000
--- a/dts/bindings/power/ambiq,pwrctrl.yaml
+++ /dev/null
@@ -1,22 +0,0 @@
-# Copyright (c) 2023 Antmicro <www.antmicro.com>
-# SPDX-License-Identifier: Apache-2.0
-
-description: Ambiq power control
-
-compatible: "ambiq,pwrctrl"
-
-include: base.yaml
-
-properties:
-  reg:
-    required: true
-
-  "#pwrcfg-cells":
-    type: int
-    required: true
-    const: 2
-    description: Number of items to expect in a power configuration
-
-pwrcfg-cells:
-  - offset
-  - mask
diff --git a/dts/bindings/power/ambiq-pwrcfg.yaml b/dts/bindings/power/ambiq-pwrcfg.yaml
deleted file mode 100644
index bd629c4bd01..00000000000
--- a/dts/bindings/power/ambiq-pwrcfg.yaml
+++ /dev/null
@@ -1,11 +0,0 @@
-# Copyright (c) 2023 Antmicro <www.antmicro.com>
-# SPDX-License-Identifier: Apache-2.0
-
-description: Ambiq peripheral power configuration
-
-properties:
-
-  ambiq,pwrcfg:
-    type: phandle-array
-    specifier-space: pwrcfg
-    description: Power configuration
diff --git a/dts/bindings/power/realtek,rts5912-ulpm.yaml b/dts/bindings/power/realtek,rts5912-ulpm.yaml
new file mode 100644
index 00000000000..32c5f492346
--- /dev/null
+++ b/dts/bindings/power/realtek,rts5912-ulpm.yaml
@@ -0,0 +1,45 @@
+# Copyright (c) 2025 Realtek Semiconductor Corporation, SIBG-SD7
+# SPDX-License-Identifier: Apache-2.0
+
+description: RTS5912 ULPM power controller
+
+compatible: "realtek,rts5912-ulpm"
+
+include: base.yaml
+
+properties:
+  wkup-pins-max:
+    type: int
+    description: |
+      Max nbr of system wake-up pins.
+      For example wkup-pins-nb = <5>; on the rts5912
+
+child-binding:
+  description: |
+    RTS5912 wake-up pin node.
+
+    All nodes using this binding must be named "wkup-pin@[index]"
+    index starts from 0
+
+  properties:
+    reg:
+      type: array
+      required: true
+      description: Wake-up pin identifier, same as "index" in node name
+
+    wkup-pin-pol:
+      type: string
+      default: rising
+      description: indicates a wakeup polarity
+      enum:
+        - rising
+        - falling
+
+    wkup-pin-mode:
+      type: string
+      default: vin
+      required: true
+      description: indicates a wakeup pin mode selection
+      enum:
+        - vin
+        - gpio
diff --git a/dts/bindings/power/st,stm32-pwr.yaml b/dts/bindings/power/st,stm32-pwr.yaml
index 84b67104dac..0eaccb39c1b 100644
--- a/dts/bindings/power/st,stm32-pwr.yaml
+++ b/dts/bindings/power/st,stm32-pwr.yaml
@@ -62,6 +62,6 @@ child-binding:
       description: |
         Specifies the GPIOs, if any, that are associated with the wake-up pin.
 
-        For example, for GPIO B2 associated with wakeup source 1 on wake-up
-        pin 1 on STM32U5 SoCs:
-        wkup-gpios = <&gpiob 2 STM32_PWR_WKUP_PIN_SRC_1>, <...>;
+        For example, for GPIO PB2 associated with wakeup source 1 on wake-up
+        event 1 on STM32U5 SoCs:
+        wkup-gpios = <&gpiob 2 STM32_PWR_WKUP_EVT_SRC_1>, <...>;
diff --git a/dts/bindings/pwm/arduino-header-pwm.yaml b/dts/bindings/pwm/arduino-header-pwm.yaml
new file mode 100644
index 00000000000..28f145e2bb9
--- /dev/null
+++ b/dts/bindings/pwm/arduino-header-pwm.yaml
@@ -0,0 +1,14 @@
+# Copyright (C) 2025 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  PWM channels exposed on Arduino headers.
+
+  Arduino's PWM pin names shares the same definition as Digital pins one.
+  That is, the mapping of PWM output on pin D3 on Arduino UNO R3 header is
+
+    pwm-map = <9 0 0 &pwm0 1 0 0>;
+
+compatible: "arduino-header-pwm"
+
+include: [base.yaml, pwm-nexus.yaml]
diff --git a/dts/bindings/pwm/atmel,sam0-tc-pwm.yaml b/dts/bindings/pwm/atmel,sam0-tc-pwm.yaml
index f13dfa448c9..bb486bdbff0 100644
--- a/dts/bindings/pwm/atmel,sam0-tc-pwm.yaml
+++ b/dts/bindings/pwm/atmel,sam0-tc-pwm.yaml
@@ -1,4 +1,5 @@
 # Copyright (c) 2020 Google LLC.
+# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
 description: Atmel SAM0 TC in PWM mode
@@ -9,6 +10,7 @@ include:
   - name: base.yaml
   - name: pwm-controller.yaml
   - name: pinctrl-device.yaml
+  - name: atmel,assigned-clocks.yaml
 
 properties:
   reg:
@@ -23,6 +25,12 @@ properties:
   clock-names:
     required: true
 
+  atmel,assigned-clocks:
+    required: true
+
+  atmel,assigned-clock-names:
+    required: true
+
   channels:
     type: int
     required: true
diff --git a/dts/bindings/pwm/atmel,sam0-tcc-pwm.yaml b/dts/bindings/pwm/atmel,sam0-tcc-pwm.yaml
index 358528f47ef..75f4c2abd00 100644
--- a/dts/bindings/pwm/atmel,sam0-tcc-pwm.yaml
+++ b/dts/bindings/pwm/atmel,sam0-tcc-pwm.yaml
@@ -1,4 +1,5 @@
 # Copyright (c) 2020 Google LLC.
+# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
 description: Atmel SAM0 TCC in PWM mode
@@ -9,6 +10,7 @@ include:
   - name: base.yaml
   - name: pwm-controller.yaml
   - name: pinctrl-device.yaml
+  - name: atmel,assigned-clocks.yaml
 
 properties:
   reg:
@@ -23,6 +25,12 @@ properties:
   clock-names:
     required: true
 
+  atmel,assigned-clocks:
+    required: true
+
+  atmel,assigned-clock-names:
+    required: true
+
   channels:
     type: int
     required: true
diff --git a/dts/bindings/pwm/espressif,esp32-ledc.yaml b/dts/bindings/pwm/espressif,esp32-ledc.yaml
index 39d4c3c59fe..c41efc3cfb7 100644
--- a/dts/bindings/pwm/espressif,esp32-ledc.yaml
+++ b/dts/bindings/pwm/espressif,esp32-ledc.yaml
@@ -1,9 +1,9 @@
-# Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
+# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
 
-  Espressif's LEDC controller Node
+  ESP32 LED Control (LEDC)
 
   The LEDC controller is primarily designed to control the intensity of LEDs, although it can be
   used to generate PWM signals for other purposes as well.
@@ -64,6 +64,7 @@ description: |
       channel9@9 {
         reg = <0x9>;
         timer = <0>;
+        inverted;
       };
       channel10@a {
         reg = <0xa>;
@@ -71,6 +72,9 @@ description: |
       };
     };
 
+    For the channel to be initially inverted after the driver's init, the flag 'inverted' can
+    be declared, as shown above for channel 9.
+
     Note: The channel's 'reg' property defines the ID of the channel. It must match the channel used
       in the 'pinmux'.
 
@@ -130,6 +134,14 @@ child-binding:
         For maximum flexibility, the high-speed as well as the low-speed channels can be driven from
         one of four high-speed/low-speed timers.
 
+    inverted:
+      type: boolean
+      description: |
+        Initial channel output level.
+        This flag defines if the channel will remain initially inverted after driver init,
+        as any pwm_set() operation will re-evaluate if the output is inverted or not
+        according to the flag passed as parameter.
+
 pwm-cells:
 - channel
 - period
diff --git a/dts/bindings/pwm/espressif,esp32-mcpwm.yaml b/dts/bindings/pwm/espressif,esp32-mcpwm.yaml
index d39e4ff95ea..fe2697deeed 100644
--- a/dts/bindings/pwm/espressif,esp32-mcpwm.yaml
+++ b/dts/bindings/pwm/espressif,esp32-mcpwm.yaml
@@ -3,7 +3,7 @@
 
 description: |
 
-  Espressif's Motor Control Pulse Width Modulator (MCPWM) controller Node
+  ESP32 Motor Control Pulse Width Modulator (MCPWM)
 
   The MCPWM peripheral is intended for motor and power control.
   It provides six PWM outputs that can be set up to operate in several topologies
diff --git a/dts/bindings/pwm/nxp,s32-emios-pwm.yaml b/dts/bindings/pwm/nxp,s32-emios-pwm.yaml
index 0b8a2ffc674..c8c4a64b27d 100644
--- a/dts/bindings/pwm/nxp,s32-emios-pwm.yaml
+++ b/dts/bindings/pwm/nxp,s32-emios-pwm.yaml
@@ -18,27 +18,20 @@ description: |
         channel = <0>;
         pwm-mode = "OPWFMB";
         prescaler = <8>;
-        period = <65534>;
-        duty-cycle = <32768>;
-        polarity = "ACTIVE_HIGH";
       };
 
       pwm_1 {
         channel = <1>;
         master-bus = <&emios1_bus_a>;
         pwm-mode = "OPWMB";
-        duty-cycle = <32768>;
         phase-shift = <100>;
-        polarity = "ACTIVE_LOW";
       };
 
       pwm_2 {
         channel = <2>;
         master-bus = <&emios1_bus_b>;
         pwm-mode = "OPWMCB_LEAD_EDGE";
-        duty-cycle = <32768>;
         dead-time = <100>;
-        polarity = "ACTIVE_LOW";
       };
 
       pwm_3 {
@@ -50,10 +43,8 @@ description: |
     };
 
   OPWMB and OPWMCB modes use reference timebase, the master bus is chosen over
-  phandle 'master-bus'. For OPWMB mode, PWM's period is master bus's period and
-  is 2 * master bus's period - 2 for OPWMCB mode. Please notice that the devicetree
-  node for master bus should be enabled and configured for using, please see
-  'nxp,s32-emios' bindings.
+  phandle 'master-bus'. Please notice that the devicetree node for master bus
+  should be enabled and configured for using, please see 'nxp,s32-emios' bindings.
 
 compatible: "nxp,s32-emios-pwm"
 
@@ -124,25 +115,6 @@ child-binding:
         - "OPWMCB_LEAD_EDGE"
         - "SAIC"
 
-    polarity:
-      type: string
-      description: |
-        Output polarity for PWM channel.
-      enum:
-        - "ACTIVE_LOW"
-        - "ACTIVE_HIGH"
-
-    duty-cycle:
-      type: int
-      description: |
-        Duty-cycle (in ticks) for PWM channel at boot time.
-
-    period:
-      type: int
-      description: |
-        Period (in ticks) for OPWFMB at boot time. Period for the rest
-        of PWM mode depends on period's master bus. Must be in range [2 ... 65535].
-
     freeze:
       type: boolean
       description: Freeze individual internal counter when the chip enters Debug mode.
diff --git a/dts/bindings/pwm/pwm-nexus.yaml b/dts/bindings/pwm/pwm-nexus.yaml
new file mode 100644
index 00000000000..17901d23ced
--- /dev/null
+++ b/dts/bindings/pwm/pwm-nexus.yaml
@@ -0,0 +1,20 @@
+# Copyright (c) 2025 TOKITA Hiroshi
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for PWM nexus nodes
+
+properties:
+  pwm-map:
+    type: compound
+    required: true
+
+  pwm-map-mask:
+    type: array
+
+  pwm-map-pass-thru:
+    type: array
+
+  "#pwm-cells":
+    type: int
+    required: true
+    description: Number of items to expect in a PWM specifier
diff --git a/dts/bindings/pwm/renesas,rz-gpt-pwm.yaml b/dts/bindings/pwm/renesas,rz-gpt-pwm.yaml
new file mode 100644
index 00000000000..b89bdb0511e
--- /dev/null
+++ b/dts/bindings/pwm/renesas,rz-gpt-pwm.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RZ GPT PWM
+
+compatible: "renesas,rz-gpt-pwm"
+
+include: [pwm-controller.yaml, base.yaml, pinctrl-device.yaml]
+
+properties:
+  "#pwm-cells":
+    const: 3
+
+pwm-cells:
+  - channel
+  - period
+  - flags
diff --git a/dts/bindings/pwm/silabs,siwx91x-pwm.yaml b/dts/bindings/pwm/silabs,siwx91x-pwm.yaml
new file mode 100644
index 00000000000..b8a01f2027b
--- /dev/null
+++ b/dts/bindings/pwm/silabs,siwx91x-pwm.yaml
@@ -0,0 +1,39 @@
+description: |
+  Silabs siwx91x PWM Controller
+
+  The siwx91x PWM controller is designed to generate PWM signals. The mapping
+  between PWM channels and GPIO pins is configured through pinctrl settings.
+
+compatible: "silabs,siwx91x-pwm"
+
+include: [base.yaml, pinctrl-device.yaml, pwm-controller.yaml]
+
+properties:
+  "#pwm-cells":
+    const: 2
+
+  silabs,ch_prescaler:
+    type: array
+    required: true
+    description: |
+      Contains the prescaler values for all the 4 channels
+    enum:
+      - 1
+      - 2
+      - 4
+      - 8
+      - 16
+      - 32
+      - 64
+
+  silabs,pwm_polarity:
+    type: int
+    required: true
+    description: |
+        Common PWM polarity for all the channels
+        0 - Normal polarity
+        1 - Inverted polarity
+
+pwm-cells:
+  - channel
+  - period
diff --git a/dts/bindings/qspi/nxp,s32-qspi-sfp-frad.yaml b/dts/bindings/qspi/nxp,s32-qspi-sfp-frad.yaml
new file mode 100644
index 00000000000..368fb7f88ca
--- /dev/null
+++ b/dts/bindings/qspi/nxp,s32-qspi-sfp-frad.yaml
@@ -0,0 +1,53 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP S32 Quad Serial Peripheral Interface (QSPI) Secure Flash Protection SFP FRAD.
+
+  The SFP FRAD performs second-level checks on input flash write and erase transactions,
+  based on the address range of each transaction.
+
+compatible: "nxp,s32-qspi-sfp-frad"
+
+child-binding:
+
+  properties:
+    reg:
+      type: array
+      required: true
+
+    master-domain-acp-policy:
+      type: int
+      required: true
+      description: |
+        Selects the master domain access control policy, defined in dt-bindings/qspi/nxp-s32-qspi.h:
+        - NXP_S32_QSPI_NON_SECURE: Selects the non-secure access control policy.
+        - NXP_S32_QSPI_SECURE: Selects the secure access control policy.
+        - NXP_S32_QSPI_PRIVILEGE: Selects the privilege access control policy.
+        Allowed combinations:
+        - NXP_S32_QSPI_SECURE
+        - NXP_S32_QSPI_SECURE | NXP_S32_QSPI_PRIVILEGE
+        - NXP_S32_QSPI_NON_SECURE | NXP_S32_QSPI_PRIVILEGE
+        - NXP_S32_QSPI_NON_SECURE | NXP_S32_QSPI_SECURE | NXP_S32_QSPI_PRIVILEGE
+
+    exclusive-access-lock:
+      type: string
+      enum:
+        - DISABLED
+        - OWNER
+        - NONE
+      default: DISABLED
+      description: |
+        Selects the exclusive access lock:
+        - DISABLED: The exclusive access lock disabled, granting write permissions for all masters
+        - ENABLED: The exclusive access lock enabled, granting write permissions only to the
+          exclusive access owner master and disabling write permissions for other masters.
+        - NONE: This configuration should not be used
+        The default corresponds to the reset value of the register field.
+
+    exclusive-access-owner:
+      type: int
+      default: 0
+      description: |
+        The domain master ID that owns the exclusive access lock.
+        Valid range: 0 - 63. The default corresponds to the reset
+        value of the register field.
diff --git a/dts/bindings/qspi/nxp,s32-qspi-sfp-mdad.yaml b/dts/bindings/qspi/nxp,s32-qspi-sfp-mdad.yaml
new file mode 100644
index 00000000000..7a40f0f3cb6
--- /dev/null
+++ b/dts/bindings/qspi/nxp,s32-qspi-sfp-mdad.yaml
@@ -0,0 +1,51 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP S32 Quad Serial Peripheral Interface (QSPI) Secure Flash Protection SFP MDAD.
+
+  The SFP MDAD performs first-level checks on input transactions, based on the secure attribute
+  and MGID associated with each transaction.
+
+compatible: "nxp,s32-qspi-sfp-mdad"
+
+child-binding:
+
+  properties:
+    secure-attribute:
+      type: int
+      required: true
+      description: |
+        Selects the secure attribute, defined in dt-bindings/qspi/nxp-s32-qspi.h:
+        - NXP_S32_QSPI_NON_SECURE: Allow the bus attribute for this master to non-secure
+        - NXP_S32_QSPI_SECURE: Allow the bus attribute for this master to secure
+        Allowed combinations:
+        - NXP_S32_QSPI_NON_SECURE
+        - NXP_S32_QSPI_SECURE
+        - NXP_S32_QSPI_NON_SECURE | NXP_S32_QSPI_SECURE
+
+    mask-type:
+      type: string
+      enum:
+        - AND
+        - OR
+      default: AND
+      description: |
+        Selects the mask type:
+        - AND: AND-ed mask
+        - OR: OR-ed mask
+        The default corresponds to the reset value of the register field.
+
+    mask:
+      type: int
+      default: 0
+      description: |
+        Defines the mask value for the ID-Match comparison.
+        Valid range: 0 - 63. The default corresponds to the
+        reset value of the register field.
+
+    domain-id:
+      type: int
+      required: true
+      description: |
+        Domain ID Reference value of the Domain-ID (MID) for MID-comparison.
+        Valid range: 0 - 63.
diff --git a/dts/bindings/qspi/st,stm32-qspi.yaml b/dts/bindings/qspi/st,stm32-qspi.yaml
index f656bd90586..5cbdd93d9c2 100644
--- a/dts/bindings/qspi/st,stm32-qspi.yaml
+++ b/dts/bindings/qspi/st,stm32-qspi.yaml
@@ -2,8 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    STM32 QSPI device representation. A stm32 quadspi node would typically
-    looks to this:
+    STM32 QSPI Controller.
+
+    An stm32 quadspi node would typically look like this:
 
         &quadspi {
             pinctrl-0 = <&quadspi_clk_pe10 &quadspi_ncs_pe11
diff --git a/dts/bindings/regulator/nxp,pf1550-regulator.yaml b/dts/bindings/regulator/nxp,pf1550-regulator.yaml
new file mode 100644
index 00000000000..8964b1857ef
--- /dev/null
+++ b/dts/bindings/regulator/nxp,pf1550-regulator.yaml
@@ -0,0 +1,54 @@
+# Copyright (c), 2024 Arduino SA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  NXP PF1550 PMIC
+
+  The PMIC has two buck converters and three LDOs. All need to be defined as
+  children nodes, strictly following the BUCK1..3, LDO1..3 node names. For
+  example:
+
+  pmic@8 {
+    reg = <0x8>;
+    ...
+    regulators {
+      compatible = nxp,pf1550-regulator";
+
+      BUCK1 {
+        /* all properties for BUCK1 */
+      };
+      BUCK2 {
+        /* all properties for BUCK2 */
+      };
+      BUCK3 {
+        /* all properties for BUCK3 */
+      };
+      LDO1 {
+        /* all properties for LDO1 */
+      };
+      LDO2 {
+        /* all properties for LDO2 */
+      };
+      LDO3 {
+        /* all properties for LDO3 */
+      };
+    };
+  };
+
+compatible: "nxp,pf1550-regulator"
+
+include: base.yaml
+
+child-binding:
+  include:
+    - name: regulator.yaml
+      property-allowlist:
+        - regulator-init-microvolt
+        - regulator-min-microvolt
+        - regulator-max-microvolt
+        - regulator-init-microamp
+        - regulator-max-microamp
+        - regulator-always-on
+        - regulator-boot-on
+        - regulator-initial-mode
+        - regulator-allowed-modes
diff --git a/dts/bindings/regulator/raspberrypi,core-supply-regulator.yaml b/dts/bindings/regulator/raspberrypi,core-supply-regulator.yaml
index 2dc1c7d0e89..c0f95e77351 100644
--- a/dts/bindings/regulator/raspberrypi,core-supply-regulator.yaml
+++ b/dts/bindings/regulator/raspberrypi,core-supply-regulator.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  RaspberryPi Pico core supply regurator
+  Raspberry Pi Pico core supply regurator
 
 compatible: "raspberrypi,core-supply-regulator"
 
diff --git a/dts/bindings/regulator/x-powers,axp192-regulator.yaml b/dts/bindings/regulator/x-powers,axp192-regulator.yaml
index 5fcbda2c847..091cb69cd95 100644
--- a/dts/bindings/regulator/x-powers,axp192-regulator.yaml
+++ b/dts/bindings/regulator/x-powers,axp192-regulator.yaml
@@ -40,6 +40,8 @@ description: |
 
 compatible: "x-powers,axp192-regulator"
 
+on-bus: axp192
+
 include: base.yaml
 
 child-binding:
diff --git a/dts/bindings/regulator/x-powers,axp2101-regulator.yaml b/dts/bindings/regulator/x-powers,axp2101-regulator.yaml
new file mode 100644
index 00000000000..d8ead994729
--- /dev/null
+++ b/dts/bindings/regulator/x-powers,axp2101-regulator.yaml
@@ -0,0 +1,93 @@
+# Copyright (c), 2021 NXP
+# Copyright (c), 2024 Lothar Felten <lothar.felten@gmail.com>
+# SPDX -License-Identifier: Apache-2.0
+
+description: |
+  AXP2101 PMIC
+
+  The PMIC has five DCDC converters and nine LDOs.
+  All need to be defined as children nodes.
+  For example:
+
+  i2c {
+    axp2101@34 {
+      compatible = "x-powers,axp2101";
+      reg = <0x34>;
+      ...
+      regulators {
+        compatible = "x-powers,axp2101-regulator";
+
+        DCDC1 {
+          /* all properties for DCDC1 */
+        };
+        DCDC2 {
+          /* all properties for DCDC2 */
+        };
+        DCDC3 {
+          /* all properties for DCDC3 */
+        };
+        DCDC4 {
+          /* all properties for DCDC4 */
+        };
+        DCDC5 {
+          /* all properties for DCDC5 */
+        };
+        LDOA1 {
+          /* all properties for LDOA1 */
+        };
+        LDOA2 {
+          /* all properties for LDOA2 */
+        };
+        LDOA3 {
+          /* all properties for LDOA3 */
+        };
+        LDOA4 {
+          /* all properties for LDOA4 */
+        };
+        LDOB1 {
+          /* all properties for LDOB1 */
+        };
+        LDOB2 {
+          /* all properties for LDOB2 */
+        };
+        LDOC {
+          /* all properties for LDOC */
+        };
+        LDOD1 {
+          /* all properties for LDOD1 */
+        };
+        LDOD2 {
+          /* all properties for LDOD2 */
+        };
+      };
+    };
+  };
+
+compatible: "x-powers,axp2101-regulator"
+
+include: base.yaml
+
+on-bus: axp2101
+
+child-binding:
+  include:
+    - name: regulator.yaml
+      property-allowlist:
+        - regulator-init-microvolt
+        - regulator-min-microvolt
+        - regulator-max-microvolt
+        - regulator-always-on
+        - regulator-boot-on
+        - regulator-boot-off
+        - regulator-initial-mode
+        - regulator-allowed-modes
+
+  properties:
+    regulator-initial-mode:
+      type: int
+      default: 0
+      enum: [0, 1]
+      description: |
+        Initial operating mode. AXP2101 supports 2 different power modes:
+        AXP2101_DCDC_MODE_AUTO: Auto (0, default)
+        AXP2101_DCDC_MODE_PWM:  PWM
diff --git a/dts/bindings/reset/reset-mmio.yaml b/dts/bindings/reset/reset-mmio.yaml
new file mode 100644
index 00000000000..ab368839482
--- /dev/null
+++ b/dts/bindings/reset/reset-mmio.yaml
@@ -0,0 +1,23 @@
+# Copyright (c) 2025 Google, LLC
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Generic MMIO Reset driver for devices with a single memory mapped reset bit
+  required to take them out of reset.
+
+compatible: "reset-mmio"
+
+include: [base.yaml]
+
+properties:
+  reg:
+    required: true
+  num-resets:
+    type: int
+    required: true
+    description: |
+      Number of resets controlled by the register.
+      Can be in the range [1, 31].
+  active-low:
+    description: Reset is active in low state.
+    type: boolean
diff --git a/dts/bindings/reset/st,stm32-rcc-rctl.yaml b/dts/bindings/reset/st,stm32-rcc-rctl.yaml
index 3629db3813a..69b0746add1 100644
--- a/dts/bindings/reset/st,stm32-rcc-rctl.yaml
+++ b/dts/bindings/reset/st,stm32-rcc-rctl.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32 Reset and Clock Control (RCC) node.
+  STM32 Reset and Clock Control (RCC) Controller.
+
   This node is in charge of reset control for AHB (Advanced High Performance)
   and APB (Advanced Peripheral) bus domains.
 
diff --git a/dts/bindings/riscv/openisa,rv32m1-pcc.yaml b/dts/bindings/riscv/openisa,rv32m1-pcc.yaml
index 15e9f6fcea0..39f61d55178 100644
--- a/dts/bindings/riscv/openisa,rv32m1-pcc.yaml
+++ b/dts/bindings/riscv/openisa,rv32m1-pcc.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2018 Foundries.io
 # SPDX-License-Identifier: Apache-2.0
 
-description: RV32M1 PCC (Peripheral Clock Control) IP node
+description: RV32M1 PCC (Peripheral Clock Control)
 
 compatible: "openisa,rv32m1-pcc"
 
diff --git a/dts/bindings/rng/adi,maxq10xx-trng.yaml b/dts/bindings/rng/adi,maxq10xx-trng.yaml
new file mode 100644
index 00000000000..5d18d467d75
--- /dev/null
+++ b/dts/bindings/rng/adi,maxq10xx-trng.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Vogl Electronic GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: ADI MAXQ10XX RNG
+
+compatible: "adi,maxq10xx-trng"
+
+include: base.yaml
diff --git a/dts/bindings/rng/espressif,esp32-trng.yaml b/dts/bindings/rng/espressif,esp32-trng.yaml
index 78c3fd1e1ec..45f13d42e82 100644
--- a/dts/bindings/rng/espressif,esp32-trng.yaml
+++ b/dts/bindings/rng/espressif,esp32-trng.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    Espressif ESP32 TRNG (True Random Number Generator).
+    ESP32 TRNG (True Random Number Generator).
 
     The TRNG uses the noise in the Wi-Fi/BT RF system. When Wi-Fi and BT are
     disabled, the random number generator will give out pseudo-random numbers.
diff --git a/dts/bindings/rng/neorv32,trng.yaml b/dts/bindings/rng/neorv32,trng.yaml
new file mode 100644
index 00000000000..3d4a1aba3b8
--- /dev/null
+++ b/dts/bindings/rng/neorv32,trng.yaml
@@ -0,0 +1,15 @@
+description: NEORV32 True Random Number Generator (TRNG)
+
+compatible: "neorv32,trng"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  syscon:
+    type: phandle
+    required: true
+    description: |
+      phandle to syscon (NEORV32 SYSINFO) node.
diff --git a/dts/bindings/rng/neorv32-trng.yaml b/dts/bindings/rng/neorv32-trng.yaml
deleted file mode 100644
index 2514944481b..00000000000
--- a/dts/bindings/rng/neorv32-trng.yaml
+++ /dev/null
@@ -1,15 +0,0 @@
-description: NEORV32 True Random Number Generator (TRNG)
-
-compatible: "neorv32-trng"
-
-include: base.yaml
-
-properties:
-  reg:
-    required: true
-
-  syscon:
-    type: phandle
-    required: true
-    description: |
-      phandle to syscon (NEORV32 SYSINFO) node.
diff --git a/dts/bindings/rng/nordic,nrf-cracen-ctrdrbg.yaml b/dts/bindings/rng/nordic,nrf-cracen-ctrdrbg.yaml
new file mode 100644
index 00000000000..820178b975a
--- /dev/null
+++ b/dts/bindings/rng/nordic,nrf-cracen-ctrdrbg.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2025, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Nordic nRF CRACEN CTR_DRBG based (Random Number Generator)
+
+    This driver is only compatible with 54L devices, and may only be used from one processor
+    core. This driver cannot be used in conjunction with the nRF security PSA solution, as both
+    would attempt to use the CRACEN HW exclusively; When that is enabled, zephyr,psa-crypto-rng
+    should be selected instead.
+
+compatible: "nordic,nrf-cracen-ctrdrbg"
+
+include: base.yaml
diff --git a/dts/bindings/rng/nxp,ele-trng.yaml b/dts/bindings/rng/nxp,ele-trng.yaml
new file mode 100644
index 00000000000..c501461da76
--- /dev/null
+++ b/dts/bindings/rng/nxp,ele-trng.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2025, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP ELE (EdgeLock secure enclave) TRNG (True Random Number Generator)
+
+compatible: "nxp,ele-trng"
+
+include: base.yaml
diff --git a/dts/bindings/rng/renesas,ra-sce9-rng.yaml b/dts/bindings/rng/renesas,ra-sce9-rng.yaml
new file mode 100644
index 00000000000..652ffbf8319
--- /dev/null
+++ b/dts/bindings/rng/renesas,ra-sce9-rng.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA SCE9 TRNG
+
+compatible: "renesas,ra-sce9-rng"
+
+include: base.yaml
diff --git a/dts/bindings/rng/sensry,sy1xx-trng.yaml b/dts/bindings/rng/sensry,sy1xx-trng.yaml
new file mode 100644
index 00000000000..d484b9a27e3
--- /dev/null
+++ b/dts/bindings/rng/sensry,sy1xx-trng.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2025 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+description: Sensry SY1XX TRNG
+
+compatible: "sensry,sy1xx-trng"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
diff --git a/dts/bindings/rng/silabs,siwx91x-rng.yaml b/dts/bindings/rng/silabs,siwx91x-rng.yaml
new file mode 100644
index 00000000000..8174a76b912
--- /dev/null
+++ b/dts/bindings/rng/silabs,siwx91x-rng.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Hardware Random Number Generator embedded on Silabs SiWx91x chips
+
+compatible: "silabs,siwx91x-rng"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
diff --git a/dts/bindings/rng/st,stm32-rng-noirq.yaml b/dts/bindings/rng/st,stm32-rng-noirq.yaml
new file mode 100644
index 00000000000..d0cfe9622fb
--- /dev/null
+++ b/dts/bindings/rng/st,stm32-rng-noirq.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: STM32 Random Number Generator without interrupt line
+
+compatible: "st,stm32-rng-noirq"
+
+include:
+  - name: st,stm32-rng.yaml
+    property-blocklist:
+      - interrupts
+
+properties:
+  generation-delay-ns:
+    type: int
+    description: |
+      Delay between the generation of two random samples, in nanoseconds.
diff --git a/dts/bindings/rng/zephyr,native-posix-rng.yaml b/dts/bindings/rng/zephyr,native-posix-rng.yaml
index 4b1d82613aa..9043a3e8901 100644
--- a/dts/bindings/rng/zephyr,native-posix-rng.yaml
+++ b/dts/bindings/rng/zephyr,native-posix-rng.yaml
@@ -6,3 +6,5 @@ description: Native POSIX RNG/Entropy
 compatible: "zephyr,native-posix-rng"
 
 include: base.yaml
+
+# This binding is deprecated in favor of zephyr,native-sim-rng
diff --git a/dts/bindings/rng/zephyr,native-sim-rng.yaml b/dts/bindings/rng/zephyr,native-sim-rng.yaml
new file mode 100644
index 00000000000..a5e40a75584
--- /dev/null
+++ b/dts/bindings/rng/zephyr,native-sim-rng.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2025, Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+description: Native simulator RNG/Entropy
+
+compatible: "zephyr,native-sim-rng"
+
+include: base.yaml
diff --git a/dts/bindings/rtc/atmel,sam0-rtc.yaml b/dts/bindings/rtc/atmel,sam0-rtc.yaml
index f2210e8bfb4..db3ed230884 100644
--- a/dts/bindings/rtc/atmel,sam0-rtc.yaml
+++ b/dts/bindings/rtc/atmel,sam0-rtc.yaml
@@ -1,4 +1,5 @@
 # Copyright (c) 2018 omSquare s.r.o.
+# Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
 description: Atmel SAM0 RTC
@@ -6,14 +7,124 @@ description: Atmel SAM0 RTC
 compatible: "atmel,sam0-rtc"
 
 include:
-  - name: rtc.yaml
+  - name: rtc-device.yaml
   - name: pinctrl-device.yaml
+  - name: atmel,assigned-clocks.yaml
 
 properties:
   reg:
     required: true
 
-  clock-generator:
+  clocks:
+    required: true
+
+  clock-names:
+    required: true
+
+  atmel,assigned-clocks:
+    required: true
+
+  atmel,assigned-clock-names:
+    required: true
+
+  systimer:
+    type: boolean
+    description: |
+      Selects RTC peripheral to be used as a system timer and replace
+      the ARM systick. When this option is selected the normal RTC
+      functionality is in exclusive mode and the normal RTC functions
+      will not be available.
+
+      The systimer exclusive functionality can be enabled using the
+      following devicetree entry:
+
+        &rtc {
+          status = "okay";
+          systimer;
+        };
+
+  cal-constant:
     type: int
-    description: clock generator index
     required: true
+    description: |
+      Define the constant used to calculate the calibration. More
+      information can be found in the datasheet of each SoC series
+      at RTC Frequency Correction topic.
+
+      Example:
+        Correction in ppm = (FREQCORR.VALUE * 1e6 ppm) / (8192 * 128)
+
+        &rtc {
+          cal-constant = <8192 * 128>;
+        };
+
+  counter-mode:
+    type: string
+    enum:
+      - "count-32"
+      - "count-16"
+      - "clock"
+    description: |
+      Configure the RTC counter operating mode. In mode 0, the counter
+      register is configured as a 32-bit counter. In mode 1, simmilar
+      to mode 0, the counter register is only 16-bit counter. In mode
+      2 the counter register is configured as a clock/calendar.
+
+        &rtc {
+          status = "okay";
+          counter-mode = "clock";
+          prescaler = <1024>;
+        };
+
+  prescaler:
+    type: int
+    enum:
+      - 1
+      - 2
+      - 4
+      - 8
+      - 16
+      - 32
+      - 64
+      - 128
+      - 256
+      - 512
+      - 1024
+    description: |
+      Enable CLKOUT at given frequency. When disabled, CLKOUT pin is LOW.
+      The default is 0 and corresponds to the disable the CLKOUT signal.
+
+        &rtc {
+          status = "okay";
+          counter-mode = "clock";
+          prescaler = <1024>;
+        };
+
+  event-control-msk:
+    type: int
+    default: 0
+    description: |
+      Enable peripheral event sources by bitmask. By default all the channels
+      are always disabled.
+
+      Event Table:
+
+        bit   Event Source
+         0    Periodic Interval 0 Event Output
+         1    Periodic Interval 1 Event Output
+         2    Periodic Interval 2 Event Output
+         3    Periodic Interval 3 Event Output
+         4    Periodic Interval 4 Event Output
+         5    Periodic Interval 5 Event Output
+         6    Periodic Interval 6 Event Output
+         7    Periodic Interval 7 Event Output
+         8    Compare/Alarm 0 Event Output
+         9    Compare/Alarm 1 Event Output
+        14    Tamper Event Output
+        15    Overflow Event Output
+        16    Tamper Event Input
+
+      Example how to enable Compare/Alarm 0 Event Output:
+        &rtc {
+          event-control-msk = <100>;
+        };
diff --git a/dts/bindings/rtc/epson,rx8130ce.yaml b/dts/bindings/rtc/epson,rx8130ce.yaml
new file mode 100644
index 00000000000..04ba5282650
--- /dev/null
+++ b/dts/bindings/rtc/epson,rx8130ce.yaml
@@ -0,0 +1,32 @@
+# Copyright (c) 2025 Måns Ansgariusson <mansgariusson@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: RX8130CE RTC
+
+compatible: "epson,rx8130ce-rtc"
+include: [i2c-device.yaml, rtc-device.yaml]
+
+properties:
+  irq-gpios:
+    type: phandle-array
+
+  clockout-frequency:
+    type: int
+    description: |
+      Specify the ociillator frequency in Hz, if not specified the clockout will be disabled.
+      - 1 # 1 Hz oscillator
+      - 1024 # 1 kHz oscillator
+      - 32768 # 32 kHz oscillator
+    enum: [1, 1024, 32768]
+
+  battery-switchover:
+    type: int
+    description: |
+      Enable the battery backup feature and specify the switchover mode.
+      If not specified the battery backup feature will be disabled.
+
+      - 1 # Non-rechargeable battery backup i2c & FOUT are disabled when VDD is below Vdet1
+      - 2 # Non-rechargeable battery backup i2c & FOUT are always on
+      - 3 # Rechargeable battery backup i2c & FOUT are disabled when VDD is below Vdet1
+      - 4 # Rechargeable battery backup i2c & FOUT are always on
+    enum: [1, 2, 3, 4]
diff --git a/dts/bindings/rtc/maxim,ds1307.yaml b/dts/bindings/rtc/maxim,ds1307.yaml
index fc81e803cb4..25815a2262a 100644
--- a/dts/bindings/rtc/maxim,ds1307.yaml
+++ b/dts/bindings/rtc/maxim,ds1307.yaml
@@ -1,6 +1,9 @@
 # SPDX-License-Identifier: Apache-2.0
+#
 # Copyright (c) 2023 Arunmani Alagarsamy
 # Author: Arunmani Alagarsamy <arunmani27100@gmail.com>
+#
+# Copyright (c) 2025 Marcin Lyda <elektromarcin@gmail.com>
 
 description: Maxim DS1307 RTC
 
@@ -9,3 +12,16 @@ compatible: "maxim,ds1307"
 include:
   - name: rtc-device.yaml
   - name: i2c-device.yaml
+
+properties:
+  sqw-frequency:
+    type: int
+    description: |
+      SQW frequency value [Hz]
+      This field enables to select output frequency on
+      SQW pin.
+    enum:
+      - 1
+      - 4096
+      - 8192
+      - 32768
diff --git a/dts/bindings/rtc/maxim,ds1337.yaml b/dts/bindings/rtc/maxim,ds1337.yaml
new file mode 100644
index 00000000000..ac874fed276
--- /dev/null
+++ b/dts/bindings/rtc/maxim,ds1337.yaml
@@ -0,0 +1,30 @@
+# Copyright (c) 2025 Marcin Lyda <elektromarcin@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Maxim DS1337 RTC
+
+compatible: "maxim,ds1337"
+
+include:
+  - name: rtc-device.yaml
+  - name: i2c-device.yaml
+
+properties:
+  int-gpios:
+    type: phandle-array
+    description: |
+      INTA interrupt output
+      GPIO pin to handle chip's INTA interrupt output,
+      used to notify about alarm events.
+
+  sqw-frequency:
+    type: int
+    description: |
+      SQW/INTB frequency value [Hz]
+      This field enables to select output frequency at
+      SQW/INTB pin.
+    enum:
+      - 1
+      - 4096
+      - 8192
+      - 32768
diff --git a/dts/bindings/rtc/microcrystal,rv8803.yaml b/dts/bindings/rtc/microcrystal,rv8803.yaml
new file mode 100644
index 00000000000..06bf6923cd6
--- /dev/null
+++ b/dts/bindings/rtc/microcrystal,rv8803.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2024 Marcin Lyda <elektromarcin@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Micro Crystal RV8803 Extreme Low Power Real-Time Clock Module
+
+compatible: "microcrystal,rv8803"
+
+include:
+  - name: rtc-device.yaml
+  - name: i2c-device.yaml
+
+properties:
+  reg:
+    required: true
+
+  int-gpios:
+    type: phandle-array
+    description: |
+      Interrupt output
+      Interrupt output used by the chip to notify various
+      events, such as alarm event, update event, external
+      events etc.
+
+  clkout-frequency:
+    type: int
+    description: |
+      CLKOUT value [Hz]
+      This field enables to select output frequency on
+      CLKOUT pin.
+    enum:
+      - 1
+      - 1024
+      - 32768
diff --git a/dts/bindings/rtc/nxp,pcf2123.yaml b/dts/bindings/rtc/nxp,pcf2123.yaml
new file mode 100644
index 00000000000..4adad0126be
--- /dev/null
+++ b/dts/bindings/rtc/nxp,pcf2123.yaml
@@ -0,0 +1,30 @@
+# Copyright (c) 2025 Lukas Gunnarsson <lukasgunnarsson@protonmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP PCF2123 RTC
+
+compatible: "nxp,pcf2123"
+
+include:
+  - name: rtc-device.yaml
+  - name: spi-device.yaml
+
+properties:
+  clkout-frequency:
+    type: int
+    default: 32768
+    enum:
+      - 32768
+      - 16384
+      - 8192
+      - 4096
+      - 2048
+      - 1024
+      - 1
+    description: |
+      Frequency of the CLKOUT signal in Hertz (Hz). Default is 32768 Hz.
+
+  int1-gpios:
+    type: phandle-array
+    description: |
+      GPIO connected to the PCF2123 INT output, interrupts are unused if none is provided.
diff --git a/dts/bindings/rtc/raspberrypi,pico-rtc.yaml b/dts/bindings/rtc/raspberrypi,pico-rtc.yaml
index cba7a708af8..a91398bc635 100644
--- a/dts/bindings/rtc/raspberrypi,pico-rtc.yaml
+++ b/dts/bindings/rtc/raspberrypi,pico-rtc.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 Andrew Featherstone <andrew.featherstone@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
-description: RaspberryPi Pico RTC
+description: Raspberry Pi Pico RTC
 
 compatible: "raspberrypi,pico-rtc"
 
diff --git a/dts/bindings/rtc/realtek,rts5912-rtc.yaml b/dts/bindings/rtc/realtek,rts5912-rtc.yaml
new file mode 100644
index 00000000000..39c49f824cb
--- /dev/null
+++ b/dts/bindings/rtc/realtek,rts5912-rtc.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2025 Realtek, SIBG-SD7
+# SPDX-License-Identifier: Apache-2.0
+
+description: RTC on Realtek RTS5912 EC
+
+compatible: "realtek,rts5912-rtc"
+
+include: rtc-device.yaml
+
+properties:
+  reg:
+    required: true
diff --git a/dts/bindings/rtc/renesas,smartbond-rtc.yaml b/dts/bindings/rtc/renesas,smartbond-rtc.yaml
index afe21aef79b..c852a9abcb0 100644
--- a/dts/bindings/rtc/renesas,smartbond-rtc.yaml
+++ b/dts/bindings/rtc/renesas,smartbond-rtc.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2023 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-description: Renesas SmartBond(tm) RTC node
+description: Renesas SmartBond(tm) RTC
 
 compatible: "renesas,smartbond-rtc"
 
diff --git a/dts/bindings/rtc/rtc-device.yaml b/dts/bindings/rtc/rtc-device.yaml
index cb231a8795b..d4d81959f61 100644
--- a/dts/bindings/rtc/rtc-device.yaml
+++ b/dts/bindings/rtc/rtc-device.yaml
@@ -3,7 +3,7 @@
 
 include: base.yaml
 
-description: RTC (real-time clock) device common bindings
+description: RTC (real-time clock) device
 
 properties:
   alarms-count:
diff --git a/dts/bindings/rtc/ti,bq32002.yaml b/dts/bindings/rtc/ti,bq32002.yaml
new file mode 100644
index 00000000000..ea55c59995e
--- /dev/null
+++ b/dts/bindings/rtc/ti,bq32002.yaml
@@ -0,0 +1,24 @@
+# Copyright (c) 2025 Marcin Lyda <elektromarcin@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instruments BQ32002 Real-Time Clock
+
+compatible: "ti,bq32002"
+
+include:
+  - name: rtc-device.yaml
+  - name: i2c-device.yaml
+
+properties:
+  irq-frequency:
+    type: int
+    description: |
+      IRQ pin frequency
+
+      This field enables to select output frequency on IRQ pin.
+      1Hz frequency is periodically corrected by the configured calibration value,
+      while the 512Hz frequency is derived directly from the oscillator.
+
+    enum:
+      - 1
+      - 512
diff --git a/dts/bindings/rtc/xlnx,xps-timer-1.00.a.yaml b/dts/bindings/rtc/xlnx,xps-timer-1.00.a.yaml
index b0b5fb3cc07..0d429f45ad4 100644
--- a/dts/bindings/rtc/xlnx,xps-timer-1.00.a.yaml
+++ b/dts/bindings/rtc/xlnx,xps-timer-1.00.a.yaml
@@ -1,4 +1,4 @@
-description: Xilinx AXI Timer IP node
+description: Xilinx AXI Timer IP
 
 compatible: "xlnx,xps-timer-1.00.a"
 
diff --git a/dts/bindings/rtc/zephyr,fake-rtc.yaml b/dts/bindings/rtc/zephyr,fake-rtc.yaml
index 733de7bb07a..62f6cb993f1 100644
--- a/dts/bindings/rtc/zephyr,fake-rtc.yaml
+++ b/dts/bindings/rtc/zephyr,fake-rtc.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    This binding provides a fake RTC controller for use as either a stub or a mock in Zephyr
+    A Fake RTC controller for use as either a stub or a mock in Zephyr
     testing.
 
 compatible: "zephyr,fake-rtc"
diff --git a/dts/bindings/sd/zephyr,mmc-disk.yaml b/dts/bindings/sd/zephyr,mmc-disk.yaml
index 4246a994e2e..164af1159a4 100644
--- a/dts/bindings/sd/zephyr,mmc-disk.yaml
+++ b/dts/bindings/sd/zephyr,mmc-disk.yaml
@@ -1,5 +1,7 @@
 description: |
-  Zephyr MMC disk node. A binding with this compatible present within an SD
+  Zephyr MMC disk.
+
+  A binding with this compatible present within an SD
   host controller device node indicates that an MMC chip is attached to that
   SD bus. This binding will enable that to be used with the disk driver
   API and any subsystems that utilize it.
diff --git a/dts/bindings/sd/zephyr,sdmmc-disk.yaml b/dts/bindings/sd/zephyr,sdmmc-disk.yaml
index 866e99da7c9..bd55fa8a966 100644
--- a/dts/bindings/sd/zephyr,sdmmc-disk.yaml
+++ b/dts/bindings/sd/zephyr,sdmmc-disk.yaml
@@ -1,5 +1,7 @@
 description: |
-  Zephyr SDMMC disk node. A binding with this compatible present within an SD
+  Zephyr SDMMC disk.
+
+  A binding with this compatible present within an SD
   host controller device node indicates that an SDMMC disk is attached to that
   SD bus. This binding will enable that disk to be used with the disk driver
   API and any subsystems that utilize it.
diff --git a/dts/bindings/sdhc/adi,max32-sdhc.yaml b/dts/bindings/sdhc/adi,max32-sdhc.yaml
new file mode 100644
index 00000000000..86d0e99d5cc
--- /dev/null
+++ b/dts/bindings/sdhc/adi,max32-sdhc.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ADI MAX32 SDHC
+
+compatible: "adi,max32-sdhc"
+
+include: [sdhc.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
diff --git a/dts/bindings/sdhc/ambiq,sdhc.yaml b/dts/bindings/sdhc/ambiq,sdhc.yaml
new file mode 100644
index 00000000000..32dd3b4147d
--- /dev/null
+++ b/dts/bindings/sdhc/ambiq,sdhc.yaml
@@ -0,0 +1,28 @@
+# Copyright 2025, Ambiq Micro Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Ambiq SDIO host controller
+
+compatible: "ambiq,sdio"
+
+include: [sdhc.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  txdelay:
+    type: int
+    required: true
+    description: SDIO TX delay tap setting. Range 0 - 15.
+
+  rxdelay:
+    type: int
+    required: true
+    description: SDIO RX delay tap setting. Range 0 - 31.
diff --git a/dts/bindings/sdhc/cdns,sdhc.yaml b/dts/bindings/sdhc/cdns,sdhc.yaml
index 536b9c4bd58..20dc723b484 100644
--- a/dts/bindings/sdhc/cdns,sdhc.yaml
+++ b/dts/bindings/sdhc/cdns,sdhc.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2023 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-description: Cadence SDHC Controller node
+description: Cadence SDHC Controller
 
 compatible: "cdns,sdhc"
 
@@ -14,7 +14,7 @@ properties:
   reg:
     required: true
     description: register space
-  power_delay_ms:
+  power-delay-ms:
     type: int
     required: true
     description: delay required to switch on the SDHC
diff --git a/dts/bindings/sdhc/espressif,esp32-sdhc-slot.yaml b/dts/bindings/sdhc/espressif,esp32-sdhc-slot.yaml
index ff743a2ad2c..284ed1f929f 100644
--- a/dts/bindings/sdhc/espressif,esp32-sdhc-slot.yaml
+++ b/dts/bindings/sdhc/espressif,esp32-sdhc-slot.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Espressif ESP32 SDHC controller slot
+description: ESP32 SDHC controller slot
 
 compatible: "espressif,esp32-sdhc-slot"
 
diff --git a/dts/bindings/sdhc/espressif,esp32-sdhc.yaml b/dts/bindings/sdhc/espressif,esp32-sdhc.yaml
index b7cfabcdbbb..335ab6bf82b 100644
--- a/dts/bindings/sdhc/espressif,esp32-sdhc.yaml
+++ b/dts/bindings/sdhc/espressif,esp32-sdhc.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Espressif ESP32 SDHC controller
+description: ESP32 SDHC controller
 
 compatible: "espressif,esp32-sdhc"
 
diff --git a/dts/bindings/sdhc/nxp,imx-usdhc.yaml b/dts/bindings/sdhc/nxp,imx-usdhc.yaml
index bccdf51d723..4e217d0c7db 100644
--- a/dts/bindings/sdhc/nxp,imx-usdhc.yaml
+++ b/dts/bindings/sdhc/nxp,imx-usdhc.yaml
@@ -29,7 +29,7 @@ properties:
     description: |
       Number of words used as write watermark level in FIFO queue for USDHC
 
-  max_current_330:
+  max-current-330:
     type: int
     default: 0
     description: |
diff --git a/dts/bindings/sensor/ams,as6212.yaml b/dts/bindings/sensor/ams,as6212.yaml
index 4604e9b50cb..163e2fb0e7c 100644
--- a/dts/bindings/sensor/ams,as6212.yaml
+++ b/dts/bindings/sensor/ams,as6212.yaml
@@ -7,7 +7,7 @@ description: |
 
 compatible: "ams,as6212"
 
-include: i2c-device.yaml
+include: [sensor-device.yaml, i2c-device.yaml]
 
 properties:
   alert-gpios:
diff --git a/dts/bindings/sensor/espressif,esp32-pcnt.yaml b/dts/bindings/sensor/espressif,esp32-pcnt.yaml
index f022206f0c4..78a7384d150 100644
--- a/dts/bindings/sensor/espressif,esp32-pcnt.yaml
+++ b/dts/bindings/sensor/espressif,esp32-pcnt.yaml
@@ -3,7 +3,7 @@
 
 description: |
 
-  Espressif's Pulse Counter Mode (PCNT) controller Node
+  ESP32 Pulse Counter (PCNT)
 
   The pulse counter module is designed to count the number of
   rising and/or falling edges of an input signal.
diff --git a/dts/bindings/sensor/espressif,esp32-temp.yaml b/dts/bindings/sensor/espressif,esp32-temp.yaml
index 31509f40251..3d61c4eb929 100644
--- a/dts/bindings/sensor/espressif,esp32-temp.yaml
+++ b/dts/bindings/sensor/espressif,esp32-temp.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
-description: ESP32 family temperature sensor node
+description: ESP32 temperature sensor
 
 compatible: "espressif,esp32-temp"
 
@@ -11,7 +11,7 @@ properties:
   range:
     type: int
     description: |
-      The temperature sensor is available on the ESP32-S2, ESP32-S3, ESP32-C3.
+      The temperature sensor is available on the ESP32-S2, ESP32-S3, ESP32-C3, ESP32-C6.
       Note that it is unavailable on the ESP32 due to missing offset calibration.
       Temperature range is defined by the temperature offset which is used during
       calculation of the output temperature from the measured value.
diff --git a/dts/bindings/sensor/everlight,als-pt19.yaml b/dts/bindings/sensor/everlight,als-pt19.yaml
new file mode 100644
index 00000000000..f41facba771
--- /dev/null
+++ b/dts/bindings/sensor/everlight,als-pt19.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2025 Dipak Shetty <shetty.dipak@gmx.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Everlight ALS-PT19 Ambient Light Sensor
+
+compatible: "everlight,als-pt19"
+
+include: sensor-device.yaml
+
+properties:
+  load-resistor:
+    type: int
+    required: true
+    description: |
+      Load resistor value in ohms
+
+  io-channels:
+    type: phandle-array
+    required: true
+    description: |
+      ADC IO channel to use.
diff --git a/dts/bindings/sensor/invensense,icm42370p-i2c.yaml b/dts/bindings/sensor/invensense,icm42370p-i2c.yaml
new file mode 100644
index 00000000000..6ae7b24ce50
--- /dev/null
+++ b/dts/bindings/sensor/invensense,icm42370p-i2c.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ICM-42370-P motion tracking device
+
+compatible: "invensense,icm42370p"
+
+include: [i2c-device.yaml, "invensense,icm42x70.yaml"]
diff --git a/dts/bindings/sensor/invensense,icm42370p-spi.yaml b/dts/bindings/sensor/invensense,icm42370p-spi.yaml
new file mode 100644
index 00000000000..4f7b0ddc134
--- /dev/null
+++ b/dts/bindings/sensor/invensense,icm42370p-spi.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2022 Esco Medical ApS
+# Copyright (c) 2020 TDK Invensense
+# SPDX-License-Identifier: Apache-2.0
+
+description: ICM-42370-P motion tracking device
+
+compatible: "invensense,icm42370p"
+
+include: [spi-device.yaml, "invensense,icm42x70.yaml"]
diff --git a/dts/bindings/sensor/invensense,icm42670.yaml b/dts/bindings/sensor/invensense,icm42670.yaml
index 6b79dcb3034..01654f1f6f8 100644
--- a/dts/bindings/sensor/invensense,icm42670.yaml
+++ b/dts/bindings/sensor/invensense,icm42670.yaml
@@ -5,37 +5,9 @@
 
 description: ICM-42670 motion tracking device
 
-include: [sensor-device.yaml]
+include: invensense,icm42x70.yaml
 
 properties:
-  int-gpios:
-    type: phandle-array
-    description: |
-      The INT signal default configuration is active-high. The
-      property value should ensure the flags properly describe the
-      signal that is presented to the driver.
-
-  accel-hz:
-    type: int
-    required: true
-    description: |
-      Default frequency of accelerometer. (Unit - Hz)
-      Maps to ACCEL_ODR field in ACCEL_CONFIG0 setting
-      Power-on reset value is 800.
-    enum:
-      - 0
-      - 1600
-      - 800
-      - 400
-      - 200
-      - 100
-      - 50
-      - 25
-      - 12
-      - 6
-      - 3
-      - 1
-
   gyro-hz:
     type: int
     required: true
@@ -54,67 +26,6 @@ properties:
       - 25
       - 12
 
-  power-mode:
-    type: string
-    default: "low-noise"
-    description: |
-      Power mode.
-      Low power mode is allowed for accelerometer sensor only from
-      1.5625Hz to 400Hz.
-      The default is chosen to support both accelerometer and
-      gyroscope sensors.
-    enum:
-      - "low-noise"
-      - "low-power"
-
-
-  accel-fs:
-    type: int
-    required: true
-    description: |
-      Default full scale of accelerometer. (Unit - g)
-      Maps to ACCEL_FS_SEL field in ACCEL_CONFIG0 setting
-      Power-on reset value is 16
-    enum:
-      - 16
-      - 8
-      - 4
-      - 2
-
-  accel-avg:
-    type: int
-    default: 32
-    description: |
-      Averaging filter setting to create accelerometer output
-      in accelerometer low power mode.
-      Maps to ACCEL_UI_AVG field in ACCEL_CONFIG1 setting.
-      The default corresponds to the reset value of the register field.
-    enum:
-      - 2
-      - 4
-      - 8
-      - 16
-      - 32
-      - 64
-
-  accel-filt-bw-hz:
-    type: int
-    default: 180
-    description: |
-      Accelerometer low pass filter bandwidth frequency (Unit - Hz).
-      Maps to ACCEL_UI_FILT_BW field in ACCEL_CONFIG1 setting.
-      The default corresponds to the reset value of the register field.
-    enum:
-      - 0
-      - 180
-      - 121
-      - 73
-      - 53
-      - 34
-      - 25
-      - 16
-
-
   gyro-fs:
     type: int
     required: true
@@ -144,21 +55,3 @@ properties:
       - 34
       - 25
       - 16
-
-  apex:
-    type: string
-    default: "none"
-    description: |
-      APEX (Advanced Pedometer and Event Detection) features. It consists of:
-      * Pedometer: Tracks step count, and provide details such as the cadence and
-                   the estimated activity type (Walk, Run, Unknown).
-      * Tilt Detection: Detects the Tilt when tilting the board with an angle of
-                        30 degrees or more held for 4 seconds.
-      * Wake on Motion (WoM): Detects motion per axis exceeding 195 mg threshold.
-      * Significant Motion Detector (SMD): Detects when the user has moved significantly.
-    enum:
-      - "none"
-      - "pedometer"
-      - "tilt"
-      - "smd"
-      - "wom"
diff --git a/dts/bindings/sensor/invensense,icm42688.yaml b/dts/bindings/sensor/invensense,icm42688.yaml
index c3c628e9597..d9e532b64a5 100644
--- a/dts/bindings/sensor/invensense,icm42688.yaml
+++ b/dts/bindings/sensor/invensense,icm42688.yaml
@@ -4,7 +4,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    ICM-42688 motion tracking device
+    ICM-42688 motion tracking device.
+
     When setting the accel-pm, accel-range, accel-odr, gyro-pm, gyro-range,
     gyro-odr properties in a .dts or .dtsi file you may include icm42688.h
     and use the macros defined there.
@@ -15,12 +16,12 @@ description: |
     icm42688: icm42688@0 {
       ...
 
-      accel-pwr-mode = <ICM42688_ACCEL_LN>;
-      accel-fs = <ICM42688_ACCEL_FS_16G>;
-      accel-odr = <ICM42688_ACCEL_ODR_2000>;
-      gyro-pwr-mode= <ICM42688_GYRO_LN>;
-      gyro-fs = <ICM42688_GYRO_FS_2000>;
-      gyro-odr = <ICM42688_GYRO_ODR_2000>;
+      accel-pwr-mode = <ICM42688_DT_ACCEL_LN>;
+      accel-fs = <ICM42688_DT_ACCEL_FS_16>;
+      accel-odr = <ICM42688_DT_ACCEL_ODR_2000>;
+      gyro-pwr-mode= <ICM42688_DT_GYRO_LN>;
+      gyro-fs = <ICM42688_DT_GYRO_FS_2000>;
+      gyro-odr = <ICM42688_DT_GYRO_ODR_2000>;
     };
 compatible: "invensense,icm42688"
 include: [sensor-device.yaml, spi-device.yaml]
diff --git a/dts/bindings/sensor/invensense,icm42x70.yaml b/dts/bindings/sensor/invensense,icm42x70.yaml
new file mode 100644
index 00000000000..169b5145965
--- /dev/null
+++ b/dts/bindings/sensor/invensense,icm42x70.yaml
@@ -0,0 +1,114 @@
+# Copyright (c) 2024 TDK Invensense
+# Copyright (c) 2022 Esco Medical ApS
+# Copyright (c) 2020 TDK Invensense
+# SPDX-License-Identifier: Apache-2.0
+
+description: ICM-42670 motion tracking device
+
+include: sensor-device.yaml
+
+properties:
+  int-gpios:
+    type: phandle-array
+    description: |
+      The INT signal default configuration is active-high. The
+      property value should ensure the flags properly describe the
+      signal that is presented to the driver.
+
+  accel-hz:
+    type: int
+    required: true
+    description: |
+      Default frequency of accelerometer. (Unit - Hz)
+      Maps to ACCEL_ODR field in ACCEL_CONFIG0 setting
+      Power-on reset value is 800.
+    enum:
+      - 0
+      - 1600
+      - 800
+      - 400
+      - 200
+      - 100
+      - 50
+      - 25
+      - 12
+      - 6
+      - 3
+      - 1
+
+  power-mode:
+    type: string
+    default: "low-noise"
+    description: |
+      Power mode.
+      Low power mode is allowed for accelerometer sensor only from
+      1.5625Hz to 400Hz.
+      The default is chosen to support both accelerometer and
+      gyroscope sensors.
+    enum:
+      - "low-noise"
+      - "low-power"
+
+  accel-fs:
+    type: int
+    required: true
+    description: |
+      Default full scale of accelerometer. (Unit - g)
+      Maps to ACCEL_FS_SEL field in ACCEL_CONFIG0 setting
+      Power-on reset value is 16
+    enum:
+      - 16
+      - 8
+      - 4
+      - 2
+
+  accel-avg:
+    type: int
+    default: 32
+    description: |
+      Averaging filter setting to create accelerometer output
+      in accelerometer low power mode.
+      Maps to ACCEL_UI_AVG field in ACCEL_CONFIG1 setting.
+      The default corresponds to the reset value of the register field.
+    enum:
+      - 2
+      - 4
+      - 8
+      - 16
+      - 32
+      - 64
+
+  accel-filt-bw-hz:
+    type: int
+    default: 180
+    description: |
+      Accelerometer low pass filter bandwidth frequency (Unit - Hz).
+      Maps to ACCEL_UI_FILT_BW field in ACCEL_CONFIG1 setting.
+      The default corresponds to the reset value of the register field.
+    enum:
+      - 0
+      - 180
+      - 121
+      - 73
+      - 53
+      - 34
+      - 25
+      - 16
+
+  apex:
+    type: string
+    default: "none"
+    description: |
+      APEX (Advanced Pedometer and Event Detection) features. It consists of:
+      * Pedometer: Tracks step count, and provide details such as the cadence and
+                   the estimated activity type (Walk, Run, Unknown).
+      * Tilt Detection: Detects the Tilt when tilting the board with an angle of
+                        30 degrees or more held for 4 seconds.
+      * Wake on Motion (WoM): Detects motion per axis exceeding 195 mg threshold.
+      * Significant Motion Detector (SMD): Detects when the user has moved significantly.
+    enum:
+      - "none"
+      - "pedometer"
+      - "tilt"
+      - "smd"
+      - "wom"
diff --git a/dts/bindings/sensor/invensense,icm45686-common.yaml b/dts/bindings/sensor/invensense,icm45686-common.yaml
new file mode 100644
index 00000000000..e89e94c019a
--- /dev/null
+++ b/dts/bindings/sensor/invensense,icm45686-common.yaml
@@ -0,0 +1,149 @@
+# Copyright (c) 2024 Intel Corporation
+# Copyright (c) 2025 Croxel Inc.
+# Copyright (c) 2025 CogniPilot Foundation
+# SPDX-License-Identifier: Apache-2.0
+
+include: sensor-device.yaml
+
+properties:
+  int-gpios:
+    type: phandle-array
+    description: |
+      The INT signal default configuration is active-high. The
+      property value should ensure the flags properly describe the
+      signal that is presented to the driver.
+
+  accel-pwr-mode:
+    type: int
+    default: 0
+    description: |
+      Specify the default accelerometer power mode.
+      Default is power-up configuration.
+    enum:
+      - 0 # ICM45686_DT_ACCEL_OFF
+      - 2 # ICM45686_DT_ACCEL_LP
+      - 3 # ICM45686_DT_ACCEL_LN
+
+  accel-odr:
+    type: int
+    default: 6
+    description: |
+      Specify the default accelerometer output data rate expressed in samples per second (Hz).
+      Default is power-up configuration.
+    enum:
+      - 3 # ICM45686_DT_ACCEL_ODR_6400 (LN-mode only)
+      - 4 # ICM45686_DT_ACCEL_ODR_3200 (LN-mode only)
+      - 5 # ICM45686_DT_ACCEL_ODR_1600 (LN-mode only)
+      - 6 # ICM45686_DT_ACCEL_ODR_800 (LN-mode only)
+      - 7 # ICM45686_DT_ACCEL_ODR_400
+      - 8 # ICM45686_DT_ACCEL_ODR_200
+      - 9 # ICM45686_DT_ACCEL_ODR_100
+      - 10 # ICM45686_DT_ACCEL_ODR_50
+      - 11 # ICM45686_DT_ACCEL_ODR_25
+      - 12 # ICM45686_DT_ACCEL_ODR_12_5
+      - 13 # ICM45686_DT_ACCEL_ODR_6_25 (LP-mode only)
+      - 14 # ICM45686_DT_ACCEL_ODR_3_125 (LP-mode only)
+      - 15 # ICM45686_DT_ACCEL_ODR_1_5625 (LP-mode only)
+
+  accel-fs:
+    type: int
+    default: 0
+    description: |
+      Specify the accelerometer range in g.
+      Default is power-up configuration.
+    enum:
+      - 0 # ICM45686_DT_ACCEL_FS_32
+      - 1 # ICM45686_DT_ACCEL_FS_16
+      - 2 # ICM45686_DT_ACCEL_FS_8
+      - 3 # ICM45686_DT_ACCEL_FS_4
+      - 4 # ICM45686_DT_ACCEL_FS_2
+
+  accel-lpf:
+    type: int
+    default: 0
+    description: |
+      Specify the accelerometer low pass filter cut-off frequency
+      as a fraction of the output data rate.
+      Default is power-up configuration.
+    enum:
+      - 0 # ICM45686_DT_ACCEL_LPF_BW_OFF
+      - 1 # ICM45686_DT_ACCEL_LPF_BW_1_4
+      - 2 # ICM45686_DT_ACCEL_LPF_BW_1_8
+      - 3 # ICM45686_DT_ACCEL_LPF_BW_1_16
+      - 4 # ICM45686_DT_ACCEL_LPF_BW_1_32
+      - 5 # ICM45686_DT_ACCEL_LPF_BW_1_64
+      - 6 # ICM45686_DT_ACCEL_LPF_BW_1_128
+
+  gyro-pwr-mode:
+    type: int
+    default: 0
+    description: |
+      Specify the default gyro power mode.
+      Default is power-up configuration.
+    enum:
+      - 0 # ICM42688_DT_GYRO_OFF
+      - 1 # ICM42688_DT_GYRO_STANDBY
+      - 2 # ICM42688_DT_GYRO_LP
+      - 3 # ICM42688_DT_GYRO_LN
+
+  gyro-odr:
+    type: int
+    default: 6
+    description: |
+      Specify the default gyro output data rate expressed in samples per second (Hz).
+      Default is power-up configuration.
+    enum:
+      - 3 # ICM45686_DT_GYRO_ODR_6400 (LN-mode only)
+      - 4 # ICM45686_DT_GYRO_ODR_3200 (LN-mode only)
+      - 5 # ICM45686_DT_GYRO_ODR_1600 (LN-mode only)
+      - 6 # ICM45686_DT_GYRO_ODR_800 (LN-mode only)
+      - 7 # ICM45686_DT_GYRO_ODR_400
+      - 8 # ICM45686_DT_GYRO_ODR_200
+      - 9 # ICM45686_DT_GYRO_ODR_100
+      - 10 # ICM45686_DT_GYRO_ODR_50
+      - 11 # ICM45686_DT_GYRO_ODR_25
+      - 12 # ICM45686_DT_GYRO_ODR_12_5
+      - 13 # ICM45686_DT_GYRO_ODR_6_25 (LP-mode only)
+      - 14 # ICM45686_DT_GYRO_ODR_3_125 (LP-mode only)
+      - 15 # ICM45686_DT_GYRO_ODR_1_5625 (LP-mode only)
+
+  gyro-fs:
+    type: int
+    default: 0
+    description: |
+      Specify the gyro range in degrees per second.
+      Default is power-up configuration.
+    enum:
+      - 0 # ICM45686_DT_GYRO_FS_4000
+      - 1 # ICM45686_DT_GYRO_FS_2000
+      - 2 # ICM45686_DT_GYRO_FS_1000
+      - 3 # ICM45686_DT_GYRO_FS_500
+      - 4 # ICM45686_DT_GYRO_FS_250
+      - 5 # ICM45686_DT_GYRO_FS_125
+      - 6 # ICM45686_DT_GYRO_FS_62_5
+      - 7 # ICM45686_DT_GYRO_FS_31_25
+      - 8 # ICM45686_DT_GYRO_FS_15_625
+
+  gyro-lpf:
+    type: int
+    default: 0
+    description: |
+      Specify the gyro low pass filter cut-off frequency
+      as a fraction of the output data rate.
+      Default is power-up configuration.
+    enum:
+      - 0 # ICM45686_DT_GYRO_LPF_BW_OFF
+      - 1 # ICM45686_DT_GYRO_LPF_BW_1_4
+      - 2 # ICM45686_DT_GYRO_LPF_BW_1_8
+      - 3 # ICM45686_DT_GYRO_LPF_BW_1_16
+      - 4 # ICM45686_DT_GYRO_LPF_BW_1_32
+      - 5 # ICM45686_DT_GYRO_LPF_BW_1_64
+      - 6 # ICM45686_DT_GYRO_LPF_BW_1_128
+
+  fifo-watermark:
+    type: int
+    default: 0
+    description: |
+      Specify the FIFO watermark level in frame count.
+      Default is power-up configuration (disabled).
+      Valid range: 0 - 104
diff --git a/dts/bindings/sensor/invensense,icm45686-i2c.yaml b/dts/bindings/sensor/invensense,icm45686-i2c.yaml
new file mode 100644
index 00000000000..778e4a47c09
--- /dev/null
+++ b/dts/bindings/sensor/invensense,icm45686-i2c.yaml
@@ -0,0 +1,30 @@
+# Copyright (c) 2025 Croxel Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    ICM45686 High-precision 6-axis motion tracking device
+    When setting the accel-pm, accel-range, accel-odr, gyro-pm, gyro-range,
+    gyro-odr properties in a .dts or .dtsi file you may include icm45686.h
+    and use the macros defined there.
+
+    Example:
+    #include <zephyr/dt-bindings/sensor/icm45686.h>
+
+    &i2c0 {
+      ...
+
+      icm42688: icm45686@68 {
+        ...
+
+        accel-pwr-mode = <ICM45686_DT_ACCEL_LN>;
+        accel-fs = <ICM45686_DT_ACCEL_FS_32>;
+        accel-odr = <ICM45686_DT_ACCEL_ODR_800>;
+        gyro-pwr-mode= <ICM45686_DT_GYRO_LN>;
+        gyro-fs = <ICM45686_DT_GYRO_FS_4000>;
+        gyro-odr = <ICM45686_DT_GYRO_ODR_800>;
+      };
+    };
+
+compatible: "invensense,icm45686"
+
+include: ["i2c-device.yaml", "invensense,icm45686-common.yaml"]
diff --git a/dts/bindings/sensor/invensense,icm45686-i3c.yaml b/dts/bindings/sensor/invensense,icm45686-i3c.yaml
new file mode 100644
index 00000000000..488ad3dd3d1
--- /dev/null
+++ b/dts/bindings/sensor/invensense,icm45686-i3c.yaml
@@ -0,0 +1,30 @@
+# # Copyright (c) 2025 Croxel Inc.
+# # SPDX-License-Identifier: Apache-2.0
+
+description: |
+    ICM45686 High-precision 6-axis motion tracking device
+    When setting the accel-pm, accel-range, accel-odr, gyro-pm, gyro-range,
+    gyro-odr properties in a .dts or .dtsi file you may include icm45686.h
+    and use the macros defined there.
+
+    Example:
+    #include <zephyr/dt-bindings/sensor/icm45686.h>
+
+    &i3c1 {
+      ...
+
+      icm42688: icm45686@680000046a00000011 {
+        ...
+
+        accel-pwr-mode = <ICM45686_DT_ACCEL_LN>;
+        accel-fs = <ICM45686_DT_ACCEL_FS_32>;
+        accel-odr = <ICM45686_DT_ACCEL_ODR_800>;
+        gyro-pwr-mode= <ICM45686_DT_GYRO_LN>;
+        gyro-fs = <ICM45686_DT_GYRO_FS_4000>;
+        gyro-odr = <ICM45686_DT_GYRO_ODR_800>;
+      };
+    };
+
+compatible: "invensense,icm45686"
+
+include: ["i3c-device.yaml", "invensense,icm45686-common.yaml"]
diff --git a/dts/bindings/sensor/invensense,icm45686-spi.yaml b/dts/bindings/sensor/invensense,icm45686-spi.yaml
new file mode 100644
index 00000000000..1f0ce9eb895
--- /dev/null
+++ b/dts/bindings/sensor/invensense,icm45686-spi.yaml
@@ -0,0 +1,30 @@
+# Copyright (c) 2025 Croxel Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    ICM45686 High-precision 6-axis motion tracking device
+    When setting the accel-pm, accel-range, accel-odr, gyro-pm, gyro-range,
+    gyro-odr properties in a .dts or .dtsi file you may include icm45686.h
+    and use the macros defined there.
+
+    Example:
+    #include <zephyr/dt-bindings/sensor/icm45686.h>
+
+    &spi0 {
+      ...
+
+      icm42688: icm45686@0 {
+        ...
+
+        accel-pwr-mode = <ICM45686_DT_ACCEL_LN>;
+        accel-fs = <ICM45686_DT_ACCEL_FS_32>;
+        accel-odr = <ICM45686_DT_ACCEL_ODR_800>;
+        gyro-pwr-mode= <ICM45686_DT_GYRO_LN>;
+        gyro-fs = <ICM45686_DT_GYRO_FS_4000>;
+        gyro-odr = <ICM45686_DT_GYRO_ODR_800>;
+      };
+    };
+
+compatible: "invensense,icm45686"
+
+include: ["spi-device.yaml", "invensense,icm45686-common.yaml"]
diff --git a/dts/bindings/sensor/invensense,icp10125.yaml b/dts/bindings/sensor/invensense,icp10125.yaml
deleted file mode 100644
index 78fa69d7851..00000000000
--- a/dts/bindings/sensor/invensense,icp10125.yaml
+++ /dev/null
@@ -1,29 +0,0 @@
-# Copyright (c) 2022, Mizuki Agawa  <agawa.mizuki@fujitsu.com>
-# SPDX-License-Identifier: Apache-2.0
-
-description: ICP10125 barometric pressure/temperature sensor
-
-compatible: "invensense,icp10125"
-
-include: [sensor-device.yaml, i2c-device.yaml]
-
-properties:
-  temperature-measurement-mode:
-    type: string
-    required: true
-    description: Mode of ambient temperature measurement
-    enum:
-      - "low-power"
-      - "normal"
-      - "low-noise"
-      - "ultra-low-noise"
-
-  pressure-measurement-mode:
-    type: string
-    required: true
-    description: Mode of barometric pressure measurement
-    enum:
-      - "low-power"
-      - "normal"
-      - "low-noise"
-      - "ultra-low-noise"
diff --git a/dts/bindings/sensor/invensense,icp101xx.yaml b/dts/bindings/sensor/invensense,icp101xx.yaml
new file mode 100644
index 00000000000..c723187a792
--- /dev/null
+++ b/dts/bindings/sensor/invensense,icp101xx.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2024 TDK Invensense
+# SPDX-License-Identifier: Apache-2.0
+
+description: ICP101xx High Accuracy, Low Power, Barometric Pressure and Temperature Sensors IC
+
+compatible: "invensense,icp101xx"
+
+include: [sensor-device.yaml, i2c-device.yaml]
+
+properties:
+  mode:
+    type: string
+    default: "normal"
+    description: Mode of pressure and temperature measurement
+    enum:
+      - "low-power"
+      - "normal"
+      - "low-noise"
+      - "ultra-low-noise"
diff --git a/dts/bindings/sensor/invensense,icp201xx-i2c.yaml b/dts/bindings/sensor/invensense,icp201xx-i2c.yaml
new file mode 100644
index 00000000000..cd973ef5375
--- /dev/null
+++ b/dts/bindings/sensor/invensense,icp201xx-i2c.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 TDK Invensense
+# SPDX-License-Identifier: Apache-2.0
+
+description: ICP201xx High Accuracy, Low Power, Barometric Pressure and Temperature Sensor IC
+
+compatible: "invensense,icp201xx"
+
+include: [i2c-device.yaml, "invensense,icp201xx.yaml"]
diff --git a/dts/bindings/sensor/invensense,icp201xx-spi.yaml b/dts/bindings/sensor/invensense,icp201xx-spi.yaml
new file mode 100644
index 00000000000..d404c2931b0
--- /dev/null
+++ b/dts/bindings/sensor/invensense,icp201xx-spi.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 TDK Invensense
+# SPDX-License-Identifier: Apache-2.0
+
+description: ICP201xx High Accuracy, Low Power, Barometric Pressure and Temperature Sensor IC
+
+compatible: "invensense,icp201xx"
+
+include: [spi-device.yaml, "invensense,icp201xx.yaml"]
diff --git a/dts/bindings/sensor/invensense,icp201xx.yaml b/dts/bindings/sensor/invensense,icp201xx.yaml
new file mode 100644
index 00000000000..d618fd9d83c
--- /dev/null
+++ b/dts/bindings/sensor/invensense,icp201xx.yaml
@@ -0,0 +1,53 @@
+# Copyright (c) 2025 TDK Invensense
+# SPDX-License-Identifier: Apache-2.0
+
+description: ICP201xx High Accuracy, Low Power, Barometric Pressure and Temperature Sensor IC
+
+compatible: "invensense,icp201xx"
+
+include: [sensor-device.yaml]
+
+properties:
+  int-gpios:
+    type: phandle-array
+    description: |
+      The INT signal default configuration is active-high. The
+      property value should ensure the flags properly describe the
+      signal that is presented to the driver.
+
+  op-mode:
+    type: string
+    default: mode0
+    description: |
+      Default mode for sensor.
+      Mode selection is a trade-off between measurement time, consumption and noise.
+      Operation modes are the following:
+      - Mode0: odr=25Hz,  noise=0.5rms, current=211uA
+      - Mode1: odr=120Hz, noise=1rms,   current=222uA
+      - Mode2: odr=40Hz,  noise=2.5rms, current=49uA
+      - Mode3: odr=2Hz,   noise=0.5rms, current=23uA
+      - Mode4: odr=25Hz,  noise=0.3rms, current=250uA
+      Default set to mode0 which is the sensor default value.
+    enum:
+      - mode0
+      - mode1
+      - mode2
+      - mode3
+      - mode4
+
+  drive-strength:
+    type: string
+    default: current_12mA_1_8V
+    description: |
+      IO device strength register value.
+      Define max current when switching IO state.
+      Default set to current_12mA_1_8V which is the sensor default value.
+    enum:
+      - current_2mA_1_8V
+      - current_4mA_1_8V
+      - current_8mA_1_8V
+      - current_12mA_1_8V
+      - current_2mA_1_2V
+      - current_4mA_1_2V
+      - current_6mA_1_2V
+      - current_8mA_1_2V
diff --git a/dts/bindings/sensor/invensense,mpu6050.yaml b/dts/bindings/sensor/invensense,mpu6050.yaml
index 6e56444008e..688de846858 100644
--- a/dts/bindings/sensor/invensense,mpu6050.yaml
+++ b/dts/bindings/sensor/invensense,mpu6050.yaml
@@ -16,3 +16,39 @@ properties:
       The INT signal default configuration is active-high.  The
       property value should ensure the flags properly describe the
       signal that is presented to the driver.
+
+  accel-fs:
+    type: int
+    default: 2
+    description: |
+      Accelerometer full-scale range.
+      An X value represents a range of +/- X g.
+      The power-on reset state of the sensor matches the default value of 2.
+    enum:
+      - 2
+      - 4
+      - 8
+      - 16
+
+  gyro-fs:
+    type: int
+    default: 250
+    description: |
+      Gyroscope full-scale range.
+      An X value represents a range of +/- X deg/s.
+      The power-on reset state of the sensor matches the default value of 250.
+    enum:
+      - 250
+      - 500
+      - 1000
+      - 2000
+
+  smplrt-div:
+    type: int
+    default: 0
+    description: |
+      The base sample rate is 8 kHz for the gyroscope and 1 kHz for
+      the accelerometer.
+      A division factor of X sets the sample rate to: baserate / (1 + X).
+      Valid values for X are 0 through 255.
+      The power-on reset state of the sensor matches the default value of 0.
diff --git a/dts/bindings/sensor/ist,tsic-xx6.yaml b/dts/bindings/sensor/ist,tsic-xx6.yaml
index d6ee88b8079..50378a3c3f7 100644
--- a/dts/bindings/sensor/ist,tsic-xx6.yaml
+++ b/dts/bindings/sensor/ist,tsic-xx6.yaml
@@ -17,6 +17,8 @@ description: |
 
 compatible: "ist,tsic-xx6"
 
+include: sensor-device.yaml
+
 properties:
   pwms:
     required: true
@@ -26,12 +28,12 @@ properties:
   lower-temperature-limit:
     required: true
     type: int
-    description: Lowest temperature supported by the device in celcius degrees.
+    description: Lowest temperature supported by the device in celsius degrees.
 
   higher-temperature-limit:
     required: true
     type: int
-    description: Highest temperature supported by the device in celcius degrees.
+    description: Highest temperature supported by the device in celsius degrees.
 
   data-bits:
     required: true
diff --git a/dts/bindings/sensor/liteon,ltr329.yaml b/dts/bindings/sensor/liteon,ltr329.yaml
new file mode 100644
index 00000000000..66db8bfe982
--- /dev/null
+++ b/dts/bindings/sensor/liteon,ltr329.yaml
@@ -0,0 +1,63 @@
+# Copyright (c) 2025 Konrad Sikora
+# SPDX-License-Identifier: Apache-2.0
+
+description: LiteOn LTR-329 Digital Ambient Light Sensor
+
+compatible: "liteon,ltr329"
+
+include: [sensor-device.yaml, i2c-device.yaml]
+
+properties:
+  gain:
+    type: int
+    default: 0
+    description: |
+      This parameter adjusts the ADC gain factor, impacting the sensor's
+      light sensitivity range. The default setting, corresponding to the
+      register reset value (1X).
+      Possible values are:
+      - 0 # Gain 1X (1 lux to 64k lux)
+      - 1 # Gain 2X (0.5 lux to 32k lux)
+      - 2 # Gain 4X (0.25 lux to 16k lux)
+      - 3 # Gain 8X (0.125 lux to 8k lux)
+      - 6 # Gain 48X (0.02 lux to 1.3k lux)
+      - 7 # Gain 96X (0.01 lux to 600 lux)
+    enum: [0, 1, 2, 3, 6, 7]
+
+  integration-time:
+    type: int
+    default: 0
+    description: |
+      ALS Integration Time is the measurement time for each ALS cycle.
+      Default value is a register reset value (100ms).
+      Possible values are:
+      - 0 # 100ms
+      - 1 # 50ms
+      - 2 # 200ms
+      - 3 # 400ms
+      - 4 # 150ms
+      - 5 # 250ms
+      - 6 # 300ms
+      - 7 # 350ms
+    enum: [0, 1, 2, 3, 4, 5, 6, 7]
+
+  measurement-rate:
+    type: int
+    default: 3
+    description: |
+      ALS Measurement Rate is the rate at which the sensor
+      takes measurements in the active mode. This is the interval
+      between ALS_DATA registers update. ALS Measurement Repeat Rate
+      must be set to be equal or larger than the Integration Time.
+      If ALS Measurement Repeat Rate  is set to be smaller than
+      ALS Integration Time, it will automatically be reset to be
+      equal to ALS Integration Time by the IC internally. Default value
+      is a register reset value (500ms).
+      Possible values are:
+      - 0 # 50ms
+      - 1 # 100ms
+      - 2 # 200ms
+      - 3 # 500ms
+      - 4 # 1000ms
+      - 5 # 2000ms
+    enum: [0, 1, 2, 3, 4, 5]
diff --git a/dts/bindings/sensor/liteon,ltrf216a.yaml b/dts/bindings/sensor/liteon,ltrf216a.yaml
new file mode 100644
index 00000000000..f509dbfcaff
--- /dev/null
+++ b/dts/bindings/sensor/liteon,ltrf216a.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2023, Trridonic
+# SPDX-License-Identifier: Apache-2.0
+
+description: LiteOn F216A ambient light sensor
+
+compatible: "liteon,ltrf216a"
+
+include: [sensor-device.yaml, i2c-device.yaml]
diff --git a/dts/bindings/sensor/ltrf216a.yaml b/dts/bindings/sensor/ltrf216a.yaml
deleted file mode 100644
index fdbd7304be0..00000000000
--- a/dts/bindings/sensor/ltrf216a.yaml
+++ /dev/null
@@ -1,8 +0,0 @@
-# Copyright (c) 2023, Trridonic
-# SPDX-License-Identifier: Apache-2.0
-
-description: LiteOn F216A ambient light sensor
-
-compatible: "ltr,f216a"
-
-include: [sensor-device.yaml, i2c-device.yaml]
diff --git a/dts/bindings/sensor/meas,ms5837-02ba.yaml b/dts/bindings/sensor/meas,ms5837-02ba.yaml
new file mode 100644
index 00000000000..61ac0b1760a
--- /dev/null
+++ b/dts/bindings/sensor/meas,ms5837-02ba.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2025, Ivan Wagner <ivan.wagner@tecinvent.ch>
+# SPDX-License-Identifier: Apache-2.0
+
+description: TE Connectivity MS5837-02BA digital pressure sensor
+
+compatible: "meas,ms5837-02ba"
+
+include: [sensor-device.yaml, i2c-device.yaml]
diff --git a/dts/bindings/sensor/meas,ms5837-30ba.yaml b/dts/bindings/sensor/meas,ms5837-30ba.yaml
new file mode 100644
index 00000000000..329537b3313
--- /dev/null
+++ b/dts/bindings/sensor/meas,ms5837-30ba.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2025, Ivan Wagner <ivan.wagner@tecinvent.ch>
+# SPDX-License-Identifier: Apache-2.0
+
+description: TE Connectivity MS5837-30BA digital pressure sensor
+
+compatible: "meas,ms5837-30ba"
+
+include: [sensor-device.yaml, i2c-device.yaml]
diff --git a/dts/bindings/sensor/meas,ms5837.yaml b/dts/bindings/sensor/meas,ms5837.yaml
deleted file mode 100644
index 7d5472c3613..00000000000
--- a/dts/bindings/sensor/meas,ms5837.yaml
+++ /dev/null
@@ -1,8 +0,0 @@
-# Copyright (c) 2018, Jan Van Winkel <jan.van_winkel@dxplore.eu>
-# SPDX-License-Identifier: Apache-2.0
-
-description: TE Connectivity MS5837 digital pressure sensor
-
-compatible: "meas,ms5837"
-
-include: [sensor-device.yaml, i2c-device.yaml]
diff --git a/dts/bindings/sensor/melexis,mlx90394.yaml b/dts/bindings/sensor/melexis,mlx90394.yaml
new file mode 100644
index 00000000000..367e4313404
--- /dev/null
+++ b/dts/bindings/sensor/melexis,mlx90394.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) Florian Weber <Florian.Weber@live.de>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Melexis MLX90394 Magnetometer. See datasheet at
+    https://media.melexis.com/-/media/files/documents/datasheets/mlx90394-datasheet-melexis.pdf
+
+compatible: "melexis,mlx90394"
+
+include: [sensor-device.yaml, i2c-device.yaml]
diff --git a/dts/bindings/sensor/nordic,nrf-temp-nrfs.yaml b/dts/bindings/sensor/nordic,nrf-temp-nrfs.yaml
index 2a77552b3bf..540f2512d10 100644
--- a/dts/bindings/sensor/nordic,nrf-temp-nrfs.yaml
+++ b/dts/bindings/sensor/nordic,nrf-temp-nrfs.yaml
@@ -6,4 +6,4 @@ description: |
 
 compatible: "nordic,nrf-temp-nrfs"
 
-include: base.yaml
+include: [base.yaml, sensor-device.yaml]
diff --git a/dts/bindings/sensor/nxp,p3t1755-common.yaml b/dts/bindings/sensor/nxp,p3t1755-common.yaml
index ff090a8349a..0f0e174fae8 100644
--- a/dts/bindings/sensor/nxp,p3t1755-common.yaml
+++ b/dts/bindings/sensor/nxp,p3t1755-common.yaml
@@ -4,6 +4,8 @@
 description: |
     NXP P3T1755 digital temperature sensor.
 
+include: sensor-device.yaml
+
 properties:
   oneshot-mode:
     type: boolean
diff --git a/dts/bindings/sensor/pixart,paa3905.yaml b/dts/bindings/sensor/pixart,paa3905.yaml
new file mode 100644
index 00000000000..dac6c5271db
--- /dev/null
+++ b/dts/bindings/sensor/pixart,paa3905.yaml
@@ -0,0 +1,42 @@
+# Copyright (c) 2025 Croxel Inc.
+# Copyright (c) 2025 CogniPilot Foundation
+# SPDX-License-Identifier: Apache-2.0
+
+description: PA3905 optical flow sensor
+
+compatible: "pixart,paa3905"
+
+include: [sensor-device.yaml, spi-device.yaml]
+
+properties:
+  resolution:
+    type: int
+    default: 42
+    description: |
+      The resolution of the sensor, which affects the counts per inch detected
+      by the sensor.
+      Default is power-on reset value.
+
+  led-control:
+    type: boolean
+    default:
+    description: |
+      Enable or disable the LED control feature, which allows the optical flow
+      sensor to drive an external LED in order to provide illuminance when needed.
+
+  int-gpios:
+    type: phandle-array
+    description: |
+      The INT signal default configuration is active-low. The
+      property value should ensure the flags properly describe the
+      signal that is presented to the driver.
+
+  backup-timer-ms:
+    type: int
+    default: 80
+    description: |
+      The back-up timer in milliseconds used to ensure sensor interaction
+      even if no motion is present, when Data-Ready streaming trigger is
+      configured. If erratic behavior is detected, a sensor recovery
+      sequence is performed.
+      Default is 10X the fastest frame rate (126 fps).
diff --git a/dts/bindings/sensor/pixart,paj7620.yaml b/dts/bindings/sensor/pixart,paj7620.yaml
new file mode 100644
index 00000000000..2fec7adb76d
--- /dev/null
+++ b/dts/bindings/sensor/pixart,paj7620.yaml
@@ -0,0 +1,17 @@
+# Copyright (c) 2025 Paul Timke <ptimkec@live.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: Pixart PAJ7620 gesture sensor
+
+compatible: "pixart,paj7620"
+
+include: [sensor-device.yaml, i2c-device.yaml]
+
+properties:
+  int-gpios:
+    type: phandle-array
+    description: |
+      INT pin
+      This pin defaults to active low when produced by the sensor.
+      The property value should ensure the flags properly describe
+      the signal that is presented to the driver.
diff --git a/dts/bindings/sensor/pixart,pat9136.yaml b/dts/bindings/sensor/pixart,pat9136.yaml
new file mode 100644
index 00000000000..1336bf3b3ff
--- /dev/null
+++ b/dts/bindings/sensor/pixart,pat9136.yaml
@@ -0,0 +1,45 @@
+# Copyright (c) 2025 Croxel Inc.
+# Copyright (c) 2025 CogniPilot Foundation
+# SPDX-License-Identifier: Apache-2.0
+
+description: PAT9136 optical flow sensor
+
+compatible: "pixart,pat9136"
+
+include: [sensor-device.yaml, spi-device.yaml]
+
+properties:
+  resolution:
+    type: int
+    default: 19
+    description: |
+      The resolution of the sensor which indirectly results in counts per inch
+      (CPI), following the formula CPI = (1 + resolution) * 100.
+      Valid range is 0 to 199.
+      Default is value set during Performance Optimization Settings.
+
+  int-gpios:
+    type: phandle-array
+    description: |
+      The INT signal default configuration is active-low. The
+      property value should ensure the flags properly describe the
+      signal that is presented to the driver.
+
+  backup-timer-ms:
+    type: int
+    default: 50
+    description: |
+      The back-up timer in milliseconds used to ensure sensor interaction
+      even if no motion is present, when Data-Ready streaming trigger is
+      configured.
+      Default is 1000X the fastest frame rate (20,000 fps).
+
+  cooldown-timer-ms:
+    type: int
+    default: 10
+    description: |
+      The cooldown timer in milliseconds used to prevent flooding the system
+      with interrupts (potentially at max 20,000 fps) while Data-Ready
+      streaming trigger is configured.
+      Default is 200X the fastest frame rate (20,000 fps).
+      Must be less than backup-timer-ms.
diff --git a/dts/bindings/sensor/raspberrrypi,pico-temp.yaml b/dts/bindings/sensor/raspberrrypi,pico-temp.yaml
index 98b1e119292..d56b15c16af 100644
--- a/dts/bindings/sensor/raspberrrypi,pico-temp.yaml
+++ b/dts/bindings/sensor/raspberrrypi,pico-temp.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2023 TOKITA Hiroshi
 # SPDX-License-Identifier: Apache-2.0
 
-description: RaspberryPi Pico family temperature sensor node
+description: Raspberry Pi Pico family temperature sensor node
 
 compatible: "raspberrypi,pico-temp"
 
diff --git a/dts/bindings/sensor/st,lsm6dsv16x-common.yaml b/dts/bindings/sensor/st,lsm6dsv16x-common.yaml
index 9746012e310..b382aa101a0 100644
--- a/dts/bindings/sensor/st,lsm6dsv16x-common.yaml
+++ b/dts/bindings/sensor/st,lsm6dsv16x-common.yaml
@@ -1,298 +1,18 @@
 # Copyright (c) 2023 STMicroelectronics
 # SPDX-License-Identifier: Apache-2.0
 
-description: |
-    When setting the accel-range, accel-odr, gyro-range, gyro-odr properties in
-    a .dts or .dtsi file you may include lsm6dsv16x.h and use the macros
-    defined there.
-
-    Example:
-    #include <zephyr/dt-bindings/sensor/lsm6dsv16x.h>
-
-    lsm6dsv16x: lsm6dsv16x@0 {
-      ...
-
-      accel-range = <LSM6DSV16X_DT_FS_8G>;
-      accel-odr = <LSM6DSV16X_DT_ODR_AT_60Hz>;
-      gyro-range = <LSM6DSV16X_DT_FS_4000DPS>;
-      gyro-odr = <LSM6DSV16X_DT_ODR_AT_60Hz>;
-    };
-
-include: sensor-device.yaml
+include: st,lsm6dsvxxx-common.yaml
 
 properties:
-  int1-gpios:
-    type: phandle-array
-    description: |
-      INT1 pin
-
-      This pin defaults to active high when produced by the sensor.
-      The property value should ensure the flags properly describe
-      the signal that is presented to the driver.
-
-  int2-gpios:
-    type: phandle-array
-    description: |
-      INT2 pin
-
-      This pin defaults to active high when produced by the sensor.
-      The property value should ensure the flags properly describe
-      the signal that is presented to the driver.
-
-  drdy-pin:
-    type: int
-    default: 1
-    enum:
-      - 1 # drdy is generated from INT1
-      - 2 # drdy is generated from INT2
-    description: |
-      Select DRDY pin number (1 or 2).
-
-      This number represents which of the two interrupt pins
-      (INT1 or INT2) the drdy line is attached to. This property is not
-      mandatory and if not present it defaults to 1 which is the
-      configuration at power-up.
-
   accel-range:
     type: int
-    default: 0
+    default: 2
     description: |
       Range in g. Default is power-up configuration.
 
-      - 0 # LSM6DSV16X_DT_FS_2G  (0.061 mg/LSB)
-      - 1 # LSM6DSV16X_DT_FS_4G  (0.122 mg/LSB)
-      - 2 # LSM6DSV16X_DT_FS_8G  (0.244 mg/LSB)
-      - 3 # LSM6DSV16X_DT_FS_16G (0.488 mg/LSB)
-
-    enum: [0, 1, 2, 3]
-
-  accel-odr:
-    type: int
-    default: 0x0
-    description: |
-      Specify the default accelerometer output data rate expressed in samples per second (Hz).
-      The values are taken in accordance to lsm6dsv16x_data_rate_t enumerative in hal/st
-      module. Please note that this values will not change the operating mode, which will remain
-      High Performance (device default)
-      Default is power-up configuration.
-
-      - 0x00 # LSM6DSV16X_DT_ODR_OFF
-      - 0x01 # LSM6DSV16X_DT_ODR_AT_1Hz875
-      - 0x02 # LSM6DSV16X_DT_ODR_AT_7Hz5
-      - 0x03 # LSM6DSV16X_DT_ODR_AT_15Hz
-      - 0x04 # LSM6DSV16X_DT_ODR_AT_30Hz
-      - 0x05 # LSM6DSV16X_DT_ODR_AT_60Hz
-      - 0x06 # LSM6DSV16X_DT_ODR_AT_120Hz
-      - 0x07 # LSM6DSV16X_DT_ODR_AT_240Hz
-      - 0x08 # LSM6DSV16X_DT_ODR_AT_480Hz
-      - 0x09 # LSM6DSV16X_DT_ODR_AT_960Hz
-      - 0x0a # LSM6DSV16X_DT_ODR_AT_1920Hz
-      - 0x0b # LSM6DSV16X_DT_ODR_AT_3840Hz
-      - 0x0c # LSM6DSV16X_DT_ODR_AT_7680Hz
-      - 0x13 # LSM6DSV16X_DT_ODR_HA01_AT_15Hz625
-      - 0x14 # LSM6DSV16X_DT_ODR_HA01_AT_31Hz25
-      - 0x15 # LSM6DSV16X_DT_ODR_HA01_AT_62Hz5
-      - 0x16 # LSM6DSV16X_DT_ODR_HA01_AT_125Hz
-      - 0x17 # LSM6DSV16X_DT_ODR_HA01_AT_250Hz
-      - 0x18 # LSM6DSV16X_DT_ODR_HA01_AT_500Hz
-      - 0x19 # LSM6DSV16X_DT_ODR_HA01_AT_1000Hz
-      - 0x1a # LSM6DSV16X_DT_ODR_HA01_AT_2000Hz
-      - 0x1b # LSM6DSV16X_DT_ODR_HA01_AT_4000Hz
-      - 0x1c # LSM6DSV16X_DT_ODR_HA01_AT_8000Hz
-      - 0x23 # LSM6DSV16X_DT_ODR_HA02_AT_12Hz5
-      - 0x24 # LSM6DSV16X_DT_ODR_HA02_AT_25Hz
-      - 0x25 # LSM6DSV16X_DT_ODR_HA02_AT_50Hz
-      - 0x26 # LSM6DSV16X_DT_ODR_HA02_AT_100Hz
-      - 0x27 # LSM6DSV16X_DT_ODR_HA02_AT_200Hz
-      - 0x28 # LSM6DSV16X_DT_ODR_HA02_AT_400Hz
-      - 0x29 # LSM6DSV16X_DT_ODR_HA02_AT_800Hz
-      - 0x2a # LSM6DSV16X_DT_ODR_HA02_AT_1600Hz
-      - 0x2b # LSM6DSV16X_DT_ODR_HA02_AT_3200Hz
-      - 0x2c # LSM6DSV16X_DT_ODR_HA02_AT_6400Hz
-
-    enum: [0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c,
-           0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c,
-           0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c]
-
-  gyro-range:
-    type: int
-    default: 0
-    description: |
-      Range in dps. Default is power-up configuration.
-
-      - 0x0 # LSM6DSV16X_DT_FS_125DPS  (4.375 mdps/LSB)
-      - 0x1 # LSM6DSV16X_DT_FS_250DPS  (8.75 mdps/LSB)
-      - 0x2 # LSM6DSV16X_DT_FS_500DPS  (17.50 mdps/LSB)
-      - 0x3 # LSM6DSV16X_DT_FS_1000DPS (35 mdps/LSB)
-      - 0x4 # LSM6DSV16X_DT_FS_2000DPS (70 mdps/LSB)
-      - 0xc # LSM6DSV16X_DT_FS_4000DPS (140 mdps/LSB)
-
-    enum: [0x0, 0x1, 0x2, 0x3, 0x4, 0xc]
-
-  gyro-odr:
-    type: int
-    default: 0x0
-    description: |
-      Specify the default gyro output data rate expressed in samples per second (Hz).
-      The values are taken in accordance to lsm6dsv16x_data_rate_t enumerative in hal/st
-      module. Please note that these values will not change the operating mode, which will remain
-      High Performance (device default). Moreover, the values here which will be selected in the
-      DT are the only way to specify the odr accuracy even at runtime with
-      SENSOR_ATTR_SAMPLING_FREQUENCY.
-      Default is power-up configuration.
-
-      - 0x00 # LSM6DSV16X_DT_ODR_OFF
-      - 0x01 # LSM6DSV16X_DT_ODR_AT_1Hz875
-      - 0x02 # LSM6DSV16X_DT_ODR_AT_7Hz5
-      - 0x03 # LSM6DSV16X_DT_ODR_AT_15Hz
-      - 0x04 # LSM6DSV16X_DT_ODR_AT_30Hz
-      - 0x05 # LSM6DSV16X_DT_ODR_AT_60Hz
-      - 0x06 # LSM6DSV16X_DT_ODR_AT_120Hz
-      - 0x07 # LSM6DSV16X_DT_ODR_AT_240Hz
-      - 0x08 # LSM6DSV16X_DT_ODR_AT_480Hz
-      - 0x09 # LSM6DSV16X_DT_ODR_AT_960Hz
-      - 0x0a # LSM6DSV16X_DT_ODR_AT_1920Hz
-      - 0x0b # LSM6DSV16X_DT_ODR_AT_3840Hz
-      - 0x0c # LSM6DSV16X_DT_ODR_AT_7680Hz
-      - 0x13 # LSM6DSV16X_DT_ODR_HA01_AT_15Hz625
-      - 0x14 # LSM6DSV16X_DT_ODR_HA01_AT_31Hz25
-      - 0x15 # LSM6DSV16X_DT_ODR_HA01_AT_62Hz5
-      - 0x16 # LSM6DSV16X_DT_ODR_HA01_AT_125Hz
-      - 0x17 # LSM6DSV16X_DT_ODR_HA01_AT_250Hz
-      - 0x18 # LSM6DSV16X_DT_ODR_HA01_AT_500Hz
-      - 0x19 # LSM6DSV16X_DT_ODR_HA01_AT_1000Hz
-      - 0x1a # LSM6DSV16X_DT_ODR_HA01_AT_2000Hz
-      - 0x1b # LSM6DSV16X_DT_ODR_HA01_AT_4000Hz
-      - 0x1c # LSM6DSV16X_DT_ODR_HA01_AT_8000Hz
-      - 0x23 # LSM6DSV16X_DT_ODR_HA02_AT_12Hz5
-      - 0x24 # LSM6DSV16X_DT_ODR_HA02_AT_25Hz
-      - 0x25 # LSM6DSV16X_DT_ODR_HA02_AT_50Hz
-      - 0x26 # LSM6DSV16X_DT_ODR_HA02_AT_100Hz
-      - 0x27 # LSM6DSV16X_DT_ODR_HA02_AT_200Hz
-      - 0x28 # LSM6DSV16X_DT_ODR_HA02_AT_400Hz
-      - 0x29 # LSM6DSV16X_DT_ODR_HA02_AT_800Hz
-      - 0x2a # LSM6DSV16X_DT_ODR_HA02_AT_1600Hz
-      - 0x2b # LSM6DSV16X_DT_ODR_HA02_AT_3200Hz
-      - 0x2c # LSM6DSV16X_DT_ODR_HA02_AT_6400Hz
-
-    enum: [0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c,
-           0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c,
-           0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c]
-
-  drdy-pulsed:
-    type: boolean
-    description: |
-      Selects the pulsed mode for data-ready interrupt when enabled,
-      and the latched mode when disabled.
-
-  fifo-watermark:
-    type: int
-    default: 32
-    description: |
-      Specify the default FIFO watermark threshold. Every unit indicates a FIFO row (1 byte of TAG +
-      6 bytes of data). (min 0; max 255)
-      A typical threshold value is 32 which is then used as default.
-
-  accel-fifo-batch-rate:
-    type: int
-    default: 0x0
-    description: |
-      Specify the default accelerometer FIFO batch data rate expressed in samples per second (Hz).
-      The values are taken in accordance to lsm6dsv16x_fifo_xl_batch_t enumerative in hal/st
-      module.
-      Default is power-up configuration.
-
-      - 0x0 # LSM6DSV16X_DT_XL_NOT_BATCHED
-      - 0x1 # LSM6DSV16X_DT_XL_BATCHED_AT_1Hz875
-      - 0x2 # LSM6DSV16X_DT_XL_BATCHED_AT_7Hz5
-      - 0x3 # LSM6DSV16X_DT_XL_BATCHED_AT_15Hz
-      - 0x4 # LSM6DSV16X_DT_XL_BATCHED_AT_30Hz
-      - 0x5 # LSM6DSV16X_DT_XL_BATCHED_AT_60Hz
-      - 0x6 # LSM6DSV16X_DT_XL_BATCHED_AT_120Hz
-      - 0x7 # LSM6DSV16X_DT_XL_BATCHED_AT_240Hz
-      - 0x8 # LSM6DSV16X_DT_XL_BATCHED_AT_480Hz
-      - 0x9 # LSM6DSV16X_DT_XL_BATCHED_AT_960Hz
-      - 0xa # LSM6DSV16X_DT_XL_BATCHED_AT_1920Hz
-      - 0xb # LSM6DSV16X_DT_XL_BATCHED_AT_3840Hz
-      - 0xc # LSM6DSV16X_DT_XL_BATCHED_AT_7680Hz
-
-    enum: [0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c]
-
-  gyro-fifo-batch-rate:
-    type: int
-    default: 0x0
-    description: |
-      Specify the default gyroscope FIFO batch data rate expressed in samples per second (Hz).
-      The values are taken in accordance to lsm6dsv16x_fifo_gy_batch_t enumerative in hal/st
-      module.
-      Default is power-up configuration.
-
-      - 0x0 # LSM6DSV16X_DT_GY_NOT_BATCHED
-      - 0x1 # LSM6DSV16X_DT_GY_BATCHED_AT_1Hz875
-      - 0x2 # LSM6DSV16X_DT_GY_BATCHED_AT_7Hz5
-      - 0x3 # LSM6DSV16X_DT_GY_BATCHED_AT_15Hz
-      - 0x4 # LSM6DSV16X_DT_GY_BATCHED_AT_30Hz
-      - 0x5 # LSM6DSV16X_DT_GY_BATCHED_AT_60Hz
-      - 0x6 # LSM6DSV16X_DT_GY_BATCHED_AT_120Hz
-      - 0x7 # LSM6DSV16X_DT_GY_BATCHED_AT_240Hz
-      - 0x8 # LSM6DSV16X_DT_GY_BATCHED_AT_480Hz
-      - 0x9 # LSM6DSV16X_DT_GY_BATCHED_AT_960Hz
-      - 0xa # LSM6DSV16X_DT_GY_BATCHED_AT_1920Hz
-      - 0xb # LSM6DSV16X_DT_GY_BATCHED_AT_3840Hz
-      - 0xc # LSM6DSV16X_DT_GY_BATCHED_AT_7680Hz
-
-    enum: [0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c]
-
-  temp-fifo-batch-rate:
-    type: int
-    default: 0x0
-    description: |
-      Specify the default temperature FIFO batch data rate expressed in samples per second (Hz).
-      The values are taken in accordance to lsm6dsv16x_fifo_temp_batch_t enumerative in hal/st
-      module.
-      Default is power-up configuration.
-
-      - 0x0 # LSM6DSV16X_DT_TEMP_NOT_BATCHED
-      - 0x1 # LSM6DSV16X_DT_TEMP_BATCHED_AT_1Hz875
-      - 0x2 # LSM6DSV16X_DT_TEMP_BATCHED_AT_15Hz
-      - 0x3 # LSM6DSV16X_DT_TEMP_BATCHED_AT_60Hz
-
-    enum: [0x00, 0x01, 0x02, 0x03]
-
-  sflp-odr:
-    type: int
-    default: 0x3
-    description: |
-      Specify the Sensor Fusion Low Power output data rate expressed in samples per second (Hz).
-      The values are taken in accordance to lsm6dsv16x_sflp_data_rate_t enumerative in hal/st
-      module.
-      Default is power-up configuration.
-
-      - 0x0 # LSM6DSV16X_DT_SFLP_ODR_AT_15Hz
-      - 0x1 # LSM6DSV16X_DT_SFLP_ODR_AT_30Hz
-      - 0x2 # LSM6DSV16X_DT_SFLP_ODR_AT_60Hz
-      - 0x3 # LSM6DSV16X_DT_SFLP_ODR_AT_120Hz
-      - 0x4 # LSM6DSV16X_DT_SFLP_ODR_AT_240Hz
-      - 0x5 # LSM6DSV16X_DT_SFLP_ODR_AT_480Hz
-
-    enum: [0x00, 0x01, 0x02, 0x03, 0x04, 0x05]
-
-  sflp-fifo-enable:
-    type: int
-    default: 0x0
-    description: |
-      Specify what Sensor Fusion Low Power component has to be batched in FIFO.
-      The values are taken in accordance to lsm6dsv16x_fifo_sflp_raw_t enumerative in hal/st
-      module.
-      Default is power-up configuration.
-
-      - 0x0 # LSM6DSV16X_DT_SFLP_FIFO_OFF
-      - 0x1 # LSM6DSV16X_DT_SFLP_FIFO_GAME_ROTATION
-      - 0x2 # LSM6DSV16X_DT_SFLP_FIFO_GRAVITY
-      - 0x3 # LSM6DSV16X_DT_SFLP_FIFO_GAME_ROTATION_GRAVITY
-      - 0x4 # LSM6DSV16X_DT_SFLP_FIFO_GBIAS
-      - 0x5 # LSM6DSV16X_DT_SFLP_FIFO_GAME_ROTATION_GBIAS
-      - 0x6 # LSM6DSV16X_DT_SFLP_FIFO_GRAVITY_GBIAS
-      - 0x7 # LSM6DSV16X_DT_SFLP_FIFO_GAME_ROTATION_GRAVITY_GBIAS
+      - 2  # LSM6DSV16X_DT_FS_2G  (0.061 mg/LSB)
+      - 4  # LSM6DSV16X_DT_FS_4G  (0.122 mg/LSB)
+      - 8  # LSM6DSV16X_DT_FS_8G  (0.244 mg/LSB)
+      - 16 # LSM6DSV16X_DT_FS_16G (0.488 mg/LSB)
 
-    enum: [0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07]
+    enum: [2, 4, 8, 16]
diff --git a/dts/bindings/sensor/st,lsm6dsv32x-common.yaml b/dts/bindings/sensor/st,lsm6dsv32x-common.yaml
new file mode 100644
index 00000000000..cad3f67e69c
--- /dev/null
+++ b/dts/bindings/sensor/st,lsm6dsv32x-common.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2025 Meta Platforms
+# SPDX-License-Identifier: Apache-2.0
+
+include: st,lsm6dsvxxx-common.yaml
+
+properties:
+  accel-range:
+    type: int
+    default: 4
+    description: |
+      Range in g. Default is power-up configuration.
+
+      - 4  # LSM6DSV32X_DT_FS_4G  (0.122 mg/LSB)
+      - 8  # LSM6DSV32X_DT_FS_8G  (0.244 mg/LSB)
+      - 16 # LSM6DSV32X_DT_FS_16G (0.488 mg/LSB)
+      - 32 # LSM6DSV32X_DT_FS_32G (0.976 mg/LSB)
+
+    enum: [4, 8, 16, 32]
diff --git a/dts/bindings/sensor/st,lsm6dsv32x-i2c.yaml b/dts/bindings/sensor/st,lsm6dsv32x-i2c.yaml
new file mode 100644
index 00000000000..2e56b97acd0
--- /dev/null
+++ b/dts/bindings/sensor/st,lsm6dsv32x-i2c.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Meta Platforms
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics LSM6DSV32X 6-axis IMU (Inertial Measurement Unit) sensor
+    accessed through I2C bus
+
+compatible: "st,lsm6dsv32x"
+
+include: ["i2c-device.yaml", "st,lsm6dsv32x-common.yaml"]
diff --git a/dts/bindings/sensor/st,lsm6dsv32x-i3c.yaml b/dts/bindings/sensor/st,lsm6dsv32x-i3c.yaml
new file mode 100644
index 00000000000..078153771d6
--- /dev/null
+++ b/dts/bindings/sensor/st,lsm6dsv32x-i3c.yaml
@@ -0,0 +1,24 @@
+# Copyright (c) 2025 Meta Platforms
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics LSM6DSV32X 6-axis IMU (Inertial Measurement Unit) sensor
+    accessed through I3C bus
+
+compatible: "st,lsm6dsv32x"
+
+include: ["i3c-device.yaml", "st,lsm6dsv32x-common.yaml"]
+
+properties:
+  int-en-i3c:
+    type: boolean
+    description: |
+      Enables INT pin when I3C is enabled
+
+  bus-act-sel-us:
+    type: int
+    default: 50
+    description: |
+      Bus available time for I3C IBI in microseconds
+
+    enum: [50, 2, 1000, 25000]
diff --git a/dts/bindings/sensor/st,lsm6dsv32x-spi.yaml b/dts/bindings/sensor/st,lsm6dsv32x-spi.yaml
new file mode 100644
index 00000000000..3bf58b10924
--- /dev/null
+++ b/dts/bindings/sensor/st,lsm6dsv32x-spi.yaml
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Meta Platforms
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    STMicroelectronics LSM6DSV32X 6-axis IMU (Inertial Measurement Unit) sensor
+    accessed through SPI bus
+
+compatible: "st,lsm6dsv32x"
+
+include: ["spi-device.yaml", "st,lsm6dsv32x-common.yaml"]
diff --git a/dts/bindings/sensor/st,lsm6dsvxxx-common.yaml b/dts/bindings/sensor/st,lsm6dsvxxx-common.yaml
new file mode 100644
index 00000000000..44b897343f7
--- /dev/null
+++ b/dts/bindings/sensor/st,lsm6dsvxxx-common.yaml
@@ -0,0 +1,285 @@
+# Copyright (c) 2023 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    When setting the accel-range, accel-odr, gyro-range, gyro-odr properties in
+    a .dts or .dtsi file you may include lsm6dsv16x.h and use the macros
+    defined there.
+
+    Example:
+    #include <zephyr/dt-bindings/sensor/lsm6dsv16x.h>
+
+    lsm6dsv16x: lsm6dsv16x@0 {
+      ...
+
+      accel-range = <LSM6DSV16X_DT_FS_8G>;
+      accel-odr = <LSM6DSV16X_DT_ODR_AT_60Hz>;
+      gyro-range = <LSM6DSV16X_DT_FS_4000DPS>;
+      gyro-odr = <LSM6DSV16X_DT_ODR_AT_60Hz>;
+    };
+
+include: sensor-device.yaml
+
+properties:
+  int1-gpios:
+    type: phandle-array
+    description: |
+      INT1 pin
+
+      This pin defaults to active high when produced by the sensor.
+      The property value should ensure the flags properly describe
+      the signal that is presented to the driver.
+
+  int2-gpios:
+    type: phandle-array
+    description: |
+      INT2 pin
+
+      This pin defaults to active high when produced by the sensor.
+      The property value should ensure the flags properly describe
+      the signal that is presented to the driver.
+
+  drdy-pin:
+    type: int
+    default: 1
+    enum:
+      - 1 # drdy is generated from INT1
+      - 2 # drdy is generated from INT2
+    description: |
+      Select DRDY pin number (1 or 2).
+
+      This number represents which of the two interrupt pins
+      (INT1 or INT2) the drdy line is attached to. This property is not
+      mandatory and if not present it defaults to 1 which is the
+      configuration at power-up.
+
+  accel-odr:
+    type: int
+    default: 0x0
+    description: |
+      Specify the default accelerometer output data rate expressed in samples per second (Hz).
+      The values are taken in accordance to lsm6dsv16x_data_rate_t enumerative in hal/st
+      module. Please note that this values will not change the operating mode, which will remain
+      High Performance (device default)
+      Default is power-up configuration.
+
+      - 0x00 # LSM6DSV16X_DT_ODR_OFF
+      - 0x01 # LSM6DSV16X_DT_ODR_AT_1Hz875
+      - 0x02 # LSM6DSV16X_DT_ODR_AT_7Hz5
+      - 0x03 # LSM6DSV16X_DT_ODR_AT_15Hz
+      - 0x04 # LSM6DSV16X_DT_ODR_AT_30Hz
+      - 0x05 # LSM6DSV16X_DT_ODR_AT_60Hz
+      - 0x06 # LSM6DSV16X_DT_ODR_AT_120Hz
+      - 0x07 # LSM6DSV16X_DT_ODR_AT_240Hz
+      - 0x08 # LSM6DSV16X_DT_ODR_AT_480Hz
+      - 0x09 # LSM6DSV16X_DT_ODR_AT_960Hz
+      - 0x0a # LSM6DSV16X_DT_ODR_AT_1920Hz
+      - 0x0b # LSM6DSV16X_DT_ODR_AT_3840Hz
+      - 0x0c # LSM6DSV16X_DT_ODR_AT_7680Hz
+      - 0x13 # LSM6DSV16X_DT_ODR_HA01_AT_15Hz625
+      - 0x14 # LSM6DSV16X_DT_ODR_HA01_AT_31Hz25
+      - 0x15 # LSM6DSV16X_DT_ODR_HA01_AT_62Hz5
+      - 0x16 # LSM6DSV16X_DT_ODR_HA01_AT_125Hz
+      - 0x17 # LSM6DSV16X_DT_ODR_HA01_AT_250Hz
+      - 0x18 # LSM6DSV16X_DT_ODR_HA01_AT_500Hz
+      - 0x19 # LSM6DSV16X_DT_ODR_HA01_AT_1000Hz
+      - 0x1a # LSM6DSV16X_DT_ODR_HA01_AT_2000Hz
+      - 0x1b # LSM6DSV16X_DT_ODR_HA01_AT_4000Hz
+      - 0x1c # LSM6DSV16X_DT_ODR_HA01_AT_8000Hz
+      - 0x23 # LSM6DSV16X_DT_ODR_HA02_AT_12Hz5
+      - 0x24 # LSM6DSV16X_DT_ODR_HA02_AT_25Hz
+      - 0x25 # LSM6DSV16X_DT_ODR_HA02_AT_50Hz
+      - 0x26 # LSM6DSV16X_DT_ODR_HA02_AT_100Hz
+      - 0x27 # LSM6DSV16X_DT_ODR_HA02_AT_200Hz
+      - 0x28 # LSM6DSV16X_DT_ODR_HA02_AT_400Hz
+      - 0x29 # LSM6DSV16X_DT_ODR_HA02_AT_800Hz
+      - 0x2a # LSM6DSV16X_DT_ODR_HA02_AT_1600Hz
+      - 0x2b # LSM6DSV16X_DT_ODR_HA02_AT_3200Hz
+      - 0x2c # LSM6DSV16X_DT_ODR_HA02_AT_6400Hz
+
+    enum: [0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c,
+           0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c,
+           0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c]
+
+  gyro-range:
+    type: int
+    default: 0
+    description: |
+      Range in dps. Default is power-up configuration.
+
+      - 0x0 # LSM6DSV16X_DT_FS_125DPS  (4.375 mdps/LSB)
+      - 0x1 # LSM6DSV16X_DT_FS_250DPS  (8.75 mdps/LSB)
+      - 0x2 # LSM6DSV16X_DT_FS_500DPS  (17.50 mdps/LSB)
+      - 0x3 # LSM6DSV16X_DT_FS_1000DPS (35 mdps/LSB)
+      - 0x4 # LSM6DSV16X_DT_FS_2000DPS (70 mdps/LSB)
+      - 0xc # LSM6DSV16X_DT_FS_4000DPS (140 mdps/LSB)
+
+    enum: [0x0, 0x1, 0x2, 0x3, 0x4, 0xc]
+
+  gyro-odr:
+    type: int
+    default: 0x0
+    description: |
+      Specify the default gyro output data rate expressed in samples per second (Hz).
+      The values are taken in accordance to lsm6dsv16x_data_rate_t enumerative in hal/st
+      module. Please note that these values will not change the operating mode, which will remain
+      High Performance (device default). Moreover, the values here which will be selected in the
+      DT are the only way to specify the odr accuracy even at runtime with
+      SENSOR_ATTR_SAMPLING_FREQUENCY.
+      Default is power-up configuration.
+
+      - 0x00 # LSM6DSV16X_DT_ODR_OFF
+      - 0x01 # LSM6DSV16X_DT_ODR_AT_1Hz875
+      - 0x02 # LSM6DSV16X_DT_ODR_AT_7Hz5
+      - 0x03 # LSM6DSV16X_DT_ODR_AT_15Hz
+      - 0x04 # LSM6DSV16X_DT_ODR_AT_30Hz
+      - 0x05 # LSM6DSV16X_DT_ODR_AT_60Hz
+      - 0x06 # LSM6DSV16X_DT_ODR_AT_120Hz
+      - 0x07 # LSM6DSV16X_DT_ODR_AT_240Hz
+      - 0x08 # LSM6DSV16X_DT_ODR_AT_480Hz
+      - 0x09 # LSM6DSV16X_DT_ODR_AT_960Hz
+      - 0x0a # LSM6DSV16X_DT_ODR_AT_1920Hz
+      - 0x0b # LSM6DSV16X_DT_ODR_AT_3840Hz
+      - 0x0c # LSM6DSV16X_DT_ODR_AT_7680Hz
+      - 0x13 # LSM6DSV16X_DT_ODR_HA01_AT_15Hz625
+      - 0x14 # LSM6DSV16X_DT_ODR_HA01_AT_31Hz25
+      - 0x15 # LSM6DSV16X_DT_ODR_HA01_AT_62Hz5
+      - 0x16 # LSM6DSV16X_DT_ODR_HA01_AT_125Hz
+      - 0x17 # LSM6DSV16X_DT_ODR_HA01_AT_250Hz
+      - 0x18 # LSM6DSV16X_DT_ODR_HA01_AT_500Hz
+      - 0x19 # LSM6DSV16X_DT_ODR_HA01_AT_1000Hz
+      - 0x1a # LSM6DSV16X_DT_ODR_HA01_AT_2000Hz
+      - 0x1b # LSM6DSV16X_DT_ODR_HA01_AT_4000Hz
+      - 0x1c # LSM6DSV16X_DT_ODR_HA01_AT_8000Hz
+      - 0x23 # LSM6DSV16X_DT_ODR_HA02_AT_12Hz5
+      - 0x24 # LSM6DSV16X_DT_ODR_HA02_AT_25Hz
+      - 0x25 # LSM6DSV16X_DT_ODR_HA02_AT_50Hz
+      - 0x26 # LSM6DSV16X_DT_ODR_HA02_AT_100Hz
+      - 0x27 # LSM6DSV16X_DT_ODR_HA02_AT_200Hz
+      - 0x28 # LSM6DSV16X_DT_ODR_HA02_AT_400Hz
+      - 0x29 # LSM6DSV16X_DT_ODR_HA02_AT_800Hz
+      - 0x2a # LSM6DSV16X_DT_ODR_HA02_AT_1600Hz
+      - 0x2b # LSM6DSV16X_DT_ODR_HA02_AT_3200Hz
+      - 0x2c # LSM6DSV16X_DT_ODR_HA02_AT_6400Hz
+
+    enum: [0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c,
+           0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c,
+           0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c]
+
+  drdy-pulsed:
+    type: boolean
+    description: |
+      Selects the pulsed mode for data-ready interrupt when enabled,
+      and the latched mode when disabled.
+
+  fifo-watermark:
+    type: int
+    default: 32
+    description: |
+      Specify the default FIFO watermark threshold. Every unit indicates a FIFO row (1 byte of TAG +
+      6 bytes of data). (min 0; max 255)
+      A typical threshold value is 32 which is then used as default.
+
+  accel-fifo-batch-rate:
+    type: int
+    default: 0x0
+    description: |
+      Specify the default accelerometer FIFO batch data rate expressed in samples per second (Hz).
+      The values are taken in accordance to lsm6dsv16x_fifo_xl_batch_t enumerative in hal/st
+      module.
+      Default is power-up configuration.
+
+      - 0x0 # LSM6DSV16X_DT_XL_NOT_BATCHED
+      - 0x1 # LSM6DSV16X_DT_XL_BATCHED_AT_1Hz875
+      - 0x2 # LSM6DSV16X_DT_XL_BATCHED_AT_7Hz5
+      - 0x3 # LSM6DSV16X_DT_XL_BATCHED_AT_15Hz
+      - 0x4 # LSM6DSV16X_DT_XL_BATCHED_AT_30Hz
+      - 0x5 # LSM6DSV16X_DT_XL_BATCHED_AT_60Hz
+      - 0x6 # LSM6DSV16X_DT_XL_BATCHED_AT_120Hz
+      - 0x7 # LSM6DSV16X_DT_XL_BATCHED_AT_240Hz
+      - 0x8 # LSM6DSV16X_DT_XL_BATCHED_AT_480Hz
+      - 0x9 # LSM6DSV16X_DT_XL_BATCHED_AT_960Hz
+      - 0xa # LSM6DSV16X_DT_XL_BATCHED_AT_1920Hz
+      - 0xb # LSM6DSV16X_DT_XL_BATCHED_AT_3840Hz
+      - 0xc # LSM6DSV16X_DT_XL_BATCHED_AT_7680Hz
+
+    enum: [0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c]
+
+  gyro-fifo-batch-rate:
+    type: int
+    default: 0x0
+    description: |
+      Specify the default gyroscope FIFO batch data rate expressed in samples per second (Hz).
+      The values are taken in accordance to lsm6dsv16x_fifo_gy_batch_t enumerative in hal/st
+      module.
+      Default is power-up configuration.
+
+      - 0x0 # LSM6DSV16X_DT_GY_NOT_BATCHED
+      - 0x1 # LSM6DSV16X_DT_GY_BATCHED_AT_1Hz875
+      - 0x2 # LSM6DSV16X_DT_GY_BATCHED_AT_7Hz5
+      - 0x3 # LSM6DSV16X_DT_GY_BATCHED_AT_15Hz
+      - 0x4 # LSM6DSV16X_DT_GY_BATCHED_AT_30Hz
+      - 0x5 # LSM6DSV16X_DT_GY_BATCHED_AT_60Hz
+      - 0x6 # LSM6DSV16X_DT_GY_BATCHED_AT_120Hz
+      - 0x7 # LSM6DSV16X_DT_GY_BATCHED_AT_240Hz
+      - 0x8 # LSM6DSV16X_DT_GY_BATCHED_AT_480Hz
+      - 0x9 # LSM6DSV16X_DT_GY_BATCHED_AT_960Hz
+      - 0xa # LSM6DSV16X_DT_GY_BATCHED_AT_1920Hz
+      - 0xb # LSM6DSV16X_DT_GY_BATCHED_AT_3840Hz
+      - 0xc # LSM6DSV16X_DT_GY_BATCHED_AT_7680Hz
+
+    enum: [0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b, 0x0c]
+
+  temp-fifo-batch-rate:
+    type: int
+    default: 0x0
+    description: |
+      Specify the default temperature FIFO batch data rate expressed in samples per second (Hz).
+      The values are taken in accordance to lsm6dsv16x_fifo_temp_batch_t enumerative in hal/st
+      module.
+      Default is power-up configuration.
+
+      - 0x0 # LSM6DSV16X_DT_TEMP_NOT_BATCHED
+      - 0x1 # LSM6DSV16X_DT_TEMP_BATCHED_AT_1Hz875
+      - 0x2 # LSM6DSV16X_DT_TEMP_BATCHED_AT_15Hz
+      - 0x3 # LSM6DSV16X_DT_TEMP_BATCHED_AT_60Hz
+
+    enum: [0x00, 0x01, 0x02, 0x03]
+
+  sflp-odr:
+    type: int
+    default: 0x3
+    description: |
+      Specify the Sensor Fusion Low Power output data rate expressed in samples per second (Hz).
+      The values are taken in accordance to lsm6dsv16x_sflp_data_rate_t enumerative in hal/st
+      module.
+      Default is power-up configuration.
+
+      - 0x0 # LSM6DSV16X_DT_SFLP_ODR_AT_15Hz
+      - 0x1 # LSM6DSV16X_DT_SFLP_ODR_AT_30Hz
+      - 0x2 # LSM6DSV16X_DT_SFLP_ODR_AT_60Hz
+      - 0x3 # LSM6DSV16X_DT_SFLP_ODR_AT_120Hz
+      - 0x4 # LSM6DSV16X_DT_SFLP_ODR_AT_240Hz
+      - 0x5 # LSM6DSV16X_DT_SFLP_ODR_AT_480Hz
+
+    enum: [0x00, 0x01, 0x02, 0x03, 0x04, 0x05]
+
+  sflp-fifo-enable:
+    type: int
+    default: 0x0
+    description: |
+      Specify what Sensor Fusion Low Power component has to be batched in FIFO.
+      The values are taken in accordance to lsm6dsv16x_fifo_sflp_raw_t enumerative in hal/st
+      module.
+      Default is power-up configuration.
+
+      - 0x0 # LSM6DSV16X_DT_SFLP_FIFO_OFF
+      - 0x1 # LSM6DSV16X_DT_SFLP_FIFO_GAME_ROTATION
+      - 0x2 # LSM6DSV16X_DT_SFLP_FIFO_GRAVITY
+      - 0x3 # LSM6DSV16X_DT_SFLP_FIFO_GAME_ROTATION_GRAVITY
+      - 0x4 # LSM6DSV16X_DT_SFLP_FIFO_GBIAS
+      - 0x5 # LSM6DSV16X_DT_SFLP_FIFO_GAME_ROTATION_GBIAS
+      - 0x6 # LSM6DSV16X_DT_SFLP_FIFO_GRAVITY_GBIAS
+      - 0x7 # LSM6DSV16X_DT_SFLP_FIFO_GAME_ROTATION_GRAVITY_GBIAS
+
+    enum: [0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07]
diff --git a/dts/bindings/sensor/st,stm32-digi-temp.yaml b/dts/bindings/sensor/st,stm32-digi-temp.yaml
index 4faba85246d..4c97be88fc8 100644
--- a/dts/bindings/sensor/st,stm32-digi-temp.yaml
+++ b/dts/bindings/sensor/st,stm32-digi-temp.yaml
@@ -1,11 +1,11 @@
 # Copyright (c) 2024, Aurelien Jarno
 # SPDX-License-Identifier: Apache-2.0
 
-description: STM32 family Digital Temperature Sensor node
+description: STM32 Digital Temperature Sensor.
 
 compatible: "st,stm32-digi-temp"
 
-include: base.yaml
+include: [sensor-device.yaml, base.yaml]
 
 properties:
   reg:
diff --git a/dts/bindings/sensor/st,stm32-qdec.yaml b/dts/bindings/sensor/st,stm32-qdec.yaml
index c8deae1bb91..4429e0416ea 100644
--- a/dts/bindings/sensor/st,stm32-qdec.yaml
+++ b/dts/bindings/sensor/st,stm32-qdec.yaml
@@ -8,6 +8,7 @@ compatible: "st,stm32-qdec"
 include:
   - name: base.yaml
   - name: pinctrl-device.yaml
+  - name: sensor-device.yaml
 
 properties:
   pinctrl-0:
diff --git a/dts/bindings/sensor/st,stm32-temp.yaml b/dts/bindings/sensor/st,stm32-temp.yaml
index 1a53f33b43a..118c19d7412 100644
--- a/dts/bindings/sensor/st,stm32-temp.yaml
+++ b/dts/bindings/sensor/st,stm32-temp.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021, Eug Krashtan
 # SPDX-License-Identifier: Apache-2.0
 
-description: STM32 family TEMP node
+description: STM32 Internal Temperature Sensor.
 
 compatible: "st,stm32-temp"
 
diff --git a/dts/bindings/sensor/st,stm32-vbat.yaml b/dts/bindings/sensor/st,stm32-vbat.yaml
index c23b8f84a35..04616485ecb 100644
--- a/dts/bindings/sensor/st,stm32-vbat.yaml
+++ b/dts/bindings/sensor/st,stm32-vbat.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 STMicroelectronics
 # SPDX-License-Identifier: Apache-2.0
 
-description: STM32 family VBAT node
+description: STM32 VBAT
 
 include: sensor-device.yaml
 
diff --git a/dts/bindings/sensor/st,stm32-vref.yaml b/dts/bindings/sensor/st,stm32-vref.yaml
index 7a2987871a5..1e9a8b0de2a 100644
--- a/dts/bindings/sensor/st,stm32-vref.yaml
+++ b/dts/bindings/sensor/st,stm32-vref.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2023 Kenneth J. Miller <ken@miller.ec>
 # SPDX-License-Identifier: Apache-2.0
 
-description: STM32 family VREF+ node
+description: STM32 VREF+.
 
 compatible: "st,stm32-vref"
 
diff --git a/dts/bindings/sensor/st,stm32c0-temp-cal.yaml b/dts/bindings/sensor/st,stm32c0-temp-cal.yaml
index d217782cade..82dcd09821c 100644
--- a/dts/bindings/sensor/st,stm32c0-temp-cal.yaml
+++ b/dts/bindings/sensor/st,stm32c0-temp-cal.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    STM32 family TEMP node for production calibrated sensors with a single calibration temperature.
+  STM32 TEMP for production calibrated sensors with a single calibration temperature.
 
 compatible: "st,stm32c0-temp-cal"
 
diff --git a/dts/bindings/sensor/ti,opt3001.yaml b/dts/bindings/sensor/ti,opt3001.yaml
index 4c5fd7e5c35..89d102e3ac7 100644
--- a/dts/bindings/sensor/ti,opt3001.yaml
+++ b/dts/bindings/sensor/ti,opt3001.yaml
@@ -6,3 +6,9 @@ description: Texas Instruments OPT3001 ambient light sensor
 compatible: "ti,opt3001"
 
 include: [sensor-device.yaml, i2c-device.yaml]
+
+properties:
+  int-gpios:
+    type: phandle-array
+    description: |
+      Interrupt pin on the opt3001 where the default polarity is active low.
diff --git a/dts/bindings/sensor/ti,tmp112.yaml b/dts/bindings/sensor/ti,tmp112.yaml
index 8708dbd39eb..36346e6c234 100644
--- a/dts/bindings/sensor/ti,tmp112.yaml
+++ b/dts/bindings/sensor/ti,tmp112.yaml
@@ -19,6 +19,21 @@ properties:
       - 1000
       - 4000
       - 8000
+
   extended-mode:
-    description: When true use 13-bit data format allowing measuring temperature up to 128°C
+    description: When true use 13-bit data format allowing measuring temperature up to 150°C
     type: boolean
+
+  t-low-micro-c:
+    description: |
+      Sets the default tLow threshold in micro-Celsius. The default value is the chip reset
+      value.
+    type: int
+    default: 75000000
+
+  t-high-micro-c:
+    description: |
+      Sets the default tHigh threshold in micro-Celsius. The default value is the chip reset
+      value.
+    type: int
+    default: 85000000
diff --git a/dts/bindings/sensor/ti,tmp114.yaml b/dts/bindings/sensor/ti,tmp114.yaml
index 494df181098..e62d2f2e3b8 100644
--- a/dts/bindings/sensor/ti,tmp114.yaml
+++ b/dts/bindings/sensor/ti,tmp114.yaml
@@ -6,3 +6,26 @@ description: Texas Instruments TMP114 temperature sensor
 compatible: "ti,tmp114"
 
 include: [sensor-device.yaml, i2c-device.yaml]
+
+properties:
+  odr:
+    type: int
+    default: 4
+    enum: [0, 1, 2, 3, 4, 5, 6, 7]
+    description: |
+      Specify the default temperature output data rate in milliseconds (ms).
+      Default is power-up configuration (250ms).
+
+      - 0    # TMP114_DT_ODR_6_4_MS
+      - 1    # TMP114_DT_ODR_32_25_MS
+      - 2    # TMP114_DT_ODR_62_5_MS
+      - 3    # TMP114_DT_ODR_125_MS
+      - 4    # TMP114_DT_ODR_250_MS
+      - 5    # TMP114_DT_ODR_500_MS
+      - 6    # TMP114_DT_ODR_1000_MS
+      - 7    # TMP114_DT_ODR_2000_MS
+
+  oversampling:
+    type: boolean
+    description: |
+      Set averaging of samples.
diff --git a/dts/bindings/sensor/ti,tmp116.yaml b/dts/bindings/sensor/ti,tmp116.yaml
deleted file mode 100644
index 338b2595885..00000000000
--- a/dts/bindings/sensor/ti,tmp116.yaml
+++ /dev/null
@@ -1,27 +0,0 @@
-# Copyright (c) 2019 Centaur Analytics, Inc
-# SPDX-License-Identifier: Apache-2.0
-
-description: Texas Instruments TMP116 temperature sensor
-
-compatible: "ti,tmp116"
-
-bus: tmp116
-
-include: [sensor-device.yaml, i2c-device.yaml]
-
-properties:
-  odr:
-    type: int
-    default: 0x200
-    description: |
-      Specify the default temperature output data rate in milliseconds (ms).
-      Default is power-up configuration.
-    enum:
-      - 0     # TMP116_DT_ODR_15_5_MS
-      - 0x80  # TMP116_DT_ODR_125_MS
-      - 0x100 # TMP116_DT_ODR_250_MS
-      - 0x180 # TMP116_DT_ODR_500_MS
-      - 0x200 # TMP116_DT_ODR_1000_MS
-      - 0x280 # TMP116_DT_ODR_4000_MS
-      - 0x300 # TMP116_DT_ODR_8000_MS
-      - 0x380 # TMP116_DT_ODR_16000_MS
diff --git a/dts/bindings/sensor/ti,tmp11x.yaml b/dts/bindings/sensor/ti,tmp11x.yaml
new file mode 100644
index 00000000000..a6207360db7
--- /dev/null
+++ b/dts/bindings/sensor/ti,tmp11x.yaml
@@ -0,0 +1,40 @@
+# Copyright (c) 2019 Centaur Analytics, Inc
+# SPDX-License-Identifier: Apache-2.0
+
+description: Texas Instruments TMP11X temperature sensor
+
+compatible: "ti,tmp11x"
+
+bus: tmp11x
+
+include: [sensor-device.yaml, i2c-device.yaml]
+
+properties:
+  odr:
+    type: int
+    default: 0x200
+    enum: [0, 0x80, 0x100, 0x180, 0x200, 0x280, 0x300, 0x380]
+    description: |
+      Specify the default temperature output data rate in milliseconds (ms).
+      Default is power-up configuration.
+
+      - 0     # TMP11X_DT_ODR_15_5_MS
+      - 0x80  # TMP11X_DT_ODR_125_MS
+      - 0x100 # TMP11X_DT_ODR_250_MS
+      - 0x180 # TMP11X_DT_ODR_500_MS
+      - 0x200 # TMP11X_DT_ODR_1000_MS
+      - 0x280 # TMP11X_DT_ODR_4000_MS
+      - 0x300 # TMP11X_DT_ODR_8000_MS
+      - 0x380 # TMP11X_DT_ODR_16000_MS
+  oversampling:
+    type: int
+    default: 0x20
+    enum: [0, 0x20, 0x40, 0x60]
+    description: |
+      Set number of sample to averaging in one readout.
+      Default is power-up configuration (8 samples).
+
+      - 0    # TMP11X_DT_OVERSAMPLING_1
+      - 0x20 # TMP11X_DT_OVERSAMPLING_8
+      - 0x40 # TMP11X_DT_OVERSAMPLING_32
+      - 0x60 # TMP11X_DT_OVERSAMPLING_64
diff --git a/dts/bindings/sensor/we,wsen-pads-2511020213301-common.yaml b/dts/bindings/sensor/we,wsen-pads-2511020213301-common.yaml
new file mode 100644
index 00000000000..9a6553b595e
--- /dev/null
+++ b/dts/bindings/sensor/we,wsen-pads-2511020213301-common.yaml
@@ -0,0 +1,59 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+include: sensor-device.yaml
+
+properties:
+  interrupt-gpios:
+    type: phandle-array
+    description: |
+      Interrupt pin.
+      Interrupt is active high by default.
+
+  odr:
+    type: int
+    required: true
+    enum:
+    - 0
+    - 1
+    - 10
+    - 25
+    - 50
+    - 75
+    - 100
+    - 200
+    description: |
+      Sensor output data rate expressed in samples per second.
+      Data rates supported by the chip are 0 (power down), 1,
+      10, 25, 50, 75, 100 and 200.
+
+  configuration:
+    type: string
+    default: "Low_Power"
+    enum:
+    - "Low_Power"
+    - "Low_Noise"
+    description: |
+      Configuration of sensor to either be low power or low noise.
+      Maximum ODR in Low Noise configuration is 75Hz.
+      Defaults to Low_Power, which is the configuration at power-up.
+
+  additional-low-pass-filter:
+    type: boolean
+    description: |
+      Enable or disable the additional low pass filter of the sensor.
+
+  additional-low-pass-filter-configuration:
+    type: int
+    default: 0
+    enum:
+    - 0
+    - 1
+    description: |
+      Configuration of the additional low pass filter of the sensor.
+      Defaults to 0, which is the configuration at power-up.
+
+  threshold:
+    type: int
+    description: |
+      Threshold for the differential pressure interrupt in Pa.
diff --git a/dts/bindings/sensor/we,wsen-pads-2511020213301-i2c.yaml b/dts/bindings/sensor/we,wsen-pads-2511020213301-i2c.yaml
new file mode 100644
index 00000000000..3490e3498a6
--- /dev/null
+++ b/dts/bindings/sensor/we,wsen-pads-2511020213301-i2c.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Würth Elektronik WSEN-PADS-2511020213301 absolute pressure sensor (I2C bus)
+
+compatible: "we,wsen-pads-2511020213301"
+
+include: ["i2c-device.yaml", "we,wsen-pads-2511020213301-common.yaml"]
diff --git a/dts/bindings/sensor/we,wsen-pads-2511020213301-spi.yaml b/dts/bindings/sensor/we,wsen-pads-2511020213301-spi.yaml
new file mode 100644
index 00000000000..b821c32d5f8
--- /dev/null
+++ b/dts/bindings/sensor/we,wsen-pads-2511020213301-spi.yaml
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Würth Elektronik WSEN-PADS-2511020213301 absolute pressure sensor (SPI bus)
+
+compatible: "we,wsen-pads-2511020213301"
+
+include: ["spi-device.yaml", "we,wsen-pads-2511020213301-common.yaml"]
diff --git a/dts/bindings/sensor/we,wsen-pdus-25131308XXXXX.yaml b/dts/bindings/sensor/we,wsen-pdus-25131308XXXXX.yaml
new file mode 100644
index 00000000000..d6a12797bdb
--- /dev/null
+++ b/dts/bindings/sensor/we,wsen-pdus-25131308XXXXX.yaml
@@ -0,0 +1,29 @@
+# Copyright (c) 2024 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Würth Elektronik WSEN-PDUS-25131308XXXXX differential pressure sensor
+
+compatible: "we,wsen-pdus-25131308XXXXX"
+
+include: [sensor-device.yaml, i2c-device.yaml]
+
+properties:
+  sensor-type:
+    type: int
+    required: true
+    enum:
+    - 0
+    - 1
+    - 2
+    - 3
+    - 4
+    - 5
+    description: |
+      PDUS sensor product variant (pressure measurement range).
+      0 - order code 2513130810001, range = -0.1 to +0.1 kPa
+      1 - order code 2513130810101 (5V VCC) + 2513130810102 (3.3V VCC), range = -1 to +1 kPa
+      2 - order code 2513130810201, range = -10 to +10 kPa
+      3 - order code 2513130810301, range =  0 to 100 kPa
+      4 - order code 2513130810401 (5V VCC) + 2513130810402 (3.3V VCC), range = -100 to +1000 kPa
+      5 - order code 2513130815401, range = 0 to +1500 kPa
diff --git a/dts/bindings/sensor/we,wsen-tids-2521020222501.yaml b/dts/bindings/sensor/we,wsen-tids-2521020222501.yaml
new file mode 100644
index 00000000000..489c8ba3c76
--- /dev/null
+++ b/dts/bindings/sensor/we,wsen-tids-2521020222501.yaml
@@ -0,0 +1,42 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    Würth Elektronik WSEN-TIDS-2521020222501 temperature sensor
+
+compatible: "we,wsen-tids-2521020222501"
+
+include: [sensor-device.yaml, i2c-device.yaml]
+
+properties:
+  interrupt-gpios:
+    type: phandle-array
+    description: Threshold interrupt pin.
+      Interrupt is active low by default.
+
+  odr:
+    type: int
+    required: true
+    enum:
+      - 0
+      - 25
+      - 50
+      - 100
+      - 200
+    description: |
+      Sensor output data rate expressed in samples per second.
+      Data rates supported by the chip are 0 (power down), 25, 50, 100 and 200.
+
+  temp-high-threshold:
+    type: int
+    default: -40320
+    description: |
+      Threshold for temperature high limit interrupt event in millidegree Celsius.
+      Defaults to -40320, which is the configuration at power-up.
+
+  temp-low-threshold:
+    type: int
+    default: -40320
+    description: |
+      Threshold for temperature low limit interrupt event in millidegree Celsius.
+      Defaults to -40320, which is the configuration at power-up.
diff --git a/dts/bindings/serial/adi,max32-uart.yaml b/dts/bindings/serial/adi,max32-uart.yaml
index c79543cf6b8..07ebaffc80b 100644
--- a/dts/bindings/serial/adi,max32-uart.yaml
+++ b/dts/bindings/serial/adi,max32-uart.yaml
@@ -34,3 +34,34 @@ properties:
       - 5: "ADI_MAX32_PRPH_CLK_SRC_INRO" Internal Ring Oscillator
       The target device might not support all option please take a look on
       target device user guide
+
+  current-speed:
+    description: |
+      Initial baud rate setting for UART. Defaults to standard baudrate of 115200 if not specified.
+    default: 115200
+
+  stop-bits:
+    description: |
+      Sets the number of stop bits. Defaults to standard of 1 if not specified.
+    default: "1"
+
+  data-bits:
+    description: |
+      Sets the number of data bits. Defaults to standard of 8 if not specified.
+    default: 8
+
+  dmas:
+    description: |
+      DMA configuration used by asynchronous UART. Consists of a DMA instance,
+      channel number and a matching DMA slot.
+
+      For example dmas for TX, RX on UART2
+         dmas = <&dma0 1 MAX32_DMA_SLOT_UART2_TX>, <&dma0 2 MAX32_DMA_SLOT_UART2_RX>;
+
+  dma-names:
+    description: |
+      Required if the dmas property exists.  This should be "tx" and "rx"
+      to match the dmas property.
+
+      For example
+         dma-names = "tx", "rx";
diff --git a/dts/bindings/serial/altr,uart.yaml b/dts/bindings/serial/altr,uart.yaml
index 69c9ed1a94c..c009bedd88b 100644
--- a/dts/bindings/serial/altr,uart.yaml
+++ b/dts/bindings/serial/altr,uart.yaml
@@ -13,6 +13,16 @@ properties:
     required: true
     description: Default baudrate of the uart controller.
 
+  stop-bits:
+    description: |
+      Sets the number of stop bits. Defaults to standard of 1 if not specified.
+    default: "1"
+
+  data-bits:
+    description: |
+      Sets the number of data bits. Defaults to standard of 8 if not specified.
+    default: 8
+
   fixed-baudrate:
     type: boolean
     description: |
diff --git a/dts/bindings/serial/ambiq,uart.yaml b/dts/bindings/serial/ambiq,uart.yaml
index bc2611c3bd2..f87be27f419 100644
--- a/dts/bindings/serial/ambiq,uart.yaml
+++ b/dts/bindings/serial/ambiq,uart.yaml
@@ -5,7 +5,7 @@ description: Ambiq UART controller (PL011 compatible)
 
 compatible: "ambiq,uart"
 
-include: ["arm,pl011.yaml", pinctrl-device.yaml, ambiq-pwrcfg.yaml]
+include: ["arm,pl011.yaml", pinctrl-device.yaml]
 
 properties:
   pinctrl-0:
@@ -13,6 +13,3 @@ properties:
 
   pinctrl-names:
     required: true
-
-  ambiq,pwrcfg:
-    required: true
diff --git a/dts/bindings/serial/arm,cmsdk-uart.yaml b/dts/bindings/serial/arm,cmsdk-uart.yaml
index 88288c15169..efb690c65fc 100644
--- a/dts/bindings/serial/arm,cmsdk-uart.yaml
+++ b/dts/bindings/serial/arm,cmsdk-uart.yaml
@@ -2,7 +2,7 @@ description: ARM CMSDK UART
 
 compatible: "arm,cmsdk-uart"
 
-include: uart-controller.yaml
+include: [uart-controller.yaml, pinctrl-device.yaml]
 
 properties:
   reg:
diff --git a/dts/bindings/serial/arm,pl011.yaml b/dts/bindings/serial/arm,pl011.yaml
index 6029b28fd40..add76a7ca0a 100644
--- a/dts/bindings/serial/arm,pl011.yaml
+++ b/dts/bindings/serial/arm,pl011.yaml
@@ -10,3 +10,7 @@ properties:
 
   interrupts:
     required: true
+
+  fifo-disable:
+    type: boolean
+    description: Disable the UART FIFO
diff --git a/dts/bindings/serial/atmel,sam0-uart.yaml b/dts/bindings/serial/atmel,sam0-uart.yaml
index f817137d7b6..19dd2c35461 100644
--- a/dts/bindings/serial/atmel,sam0-uart.yaml
+++ b/dts/bindings/serial/atmel,sam0-uart.yaml
@@ -1,3 +1,6 @@
+# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
 description: Atmel SAM0 SERCOM UART driver
 
 compatible: "atmel,sam0-uart"
@@ -5,6 +8,7 @@ compatible: "atmel,sam0-uart"
 include:
   - name: uart-controller.yaml
   - name: pinctrl-device.yaml
+  - name: atmel,assigned-clocks.yaml
 
 properties:
   reg:
@@ -19,6 +23,12 @@ properties:
   clock-names:
     required: true
 
+  atmel,assigned-clocks:
+    required: true
+
+  atmel,assigned-clock-names:
+    required: true
+
   rxpo:
     type: int
     required: true
diff --git a/dts/bindings/serial/bflb,uart.yaml b/dts/bindings/serial/bflb,uart.yaml
new file mode 100644
index 00000000000..d844435568f
--- /dev/null
+++ b/dts/bindings/serial/bflb,uart.yaml
@@ -0,0 +1,20 @@
+# Copyright (c) 2021-2025 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+description: Bouffalo Lab UART
+
+compatible: "bflb,uart"
+
+include:
+  - name: uart-controller.yaml
+  - name: pinctrl-device.yaml
+
+properties:
+  reg:
+    required: true
+
+  peripheral-id:
+    type: int
+    description: peripheral ID
+    required: true
diff --git a/dts/bindings/serial/espressif,esp32-lpuart.yaml b/dts/bindings/serial/espressif,esp32-lpuart.yaml
new file mode 100644
index 00000000000..c6802374571
--- /dev/null
+++ b/dts/bindings/serial/espressif,esp32-lpuart.yaml
@@ -0,0 +1,40 @@
+description: ESP32 Low Power UART
+
+compatible: "espressif,esp32-lpuart"
+
+include: uart-controller.yaml
+
+properties:
+  reg:
+    required: true
+
+  tx-pin:
+    type: int
+    default: 5
+    enum:
+      - 5
+    description: In ESP32-C6, TX pin is fixed to GPIO5
+
+  rx-pin:
+    type: int
+    default: 4
+    enum:
+      - 4
+    description: In ESP32-C6, RX pin is fixed to GPIO4
+
+  rts-pin:
+    type: int
+    default: 2
+    enum:
+      - 2
+    description: In ESP32-C6, RTS pin is fixed to GPIO2
+
+  cts-pin:
+    type: int
+    default: 3
+    enum:
+      - 3
+    description: In ESP32-C6, CTS pin is fixed to GPIO3
+
+  current-speed:
+    type: int
diff --git a/dts/bindings/serial/espressif,esp32-uart.yaml b/dts/bindings/serial/espressif,esp32-uart.yaml
index 49026309f34..f1f6abdfa37 100644
--- a/dts/bindings/serial/espressif,esp32-uart.yaml
+++ b/dts/bindings/serial/espressif,esp32-uart.yaml
@@ -14,6 +14,16 @@ properties:
   pinctrl-names:
     required: true
 
+  stop-bits:
+    description: |
+      Sets the number of stop bits. Defaults to standard of 1 if not specified.
+    default: "1"
+
+  data-bits:
+    description: |
+      Sets the number of data bits. Defaults to standard of 8 if not specified.
+    default: 8
+
   hw-rs485-hd-mode:
     type: boolean
     description: |
diff --git a/dts/bindings/serial/infineon,cat1-uart.yaml b/dts/bindings/serial/infineon,cat1-uart.yaml
index 2827e0b4e1a..32990ea6827 100644
--- a/dts/bindings/serial/infineon,cat1-uart.yaml
+++ b/dts/bindings/serial/infineon,cat1-uart.yaml
@@ -39,3 +39,13 @@ properties:
 
   pinctrl-names:
     required: true
+
+  stop-bits:
+    description: |
+      Sets the number of stop bits. Defaults to standard of 1 if not specified.
+    default: "1"
+
+  data-bits:
+    description: |
+      Sets the number of data bits. Defaults to standard of 8 if not specified.
+    default: 8
diff --git a/dts/bindings/serial/intel,lw_uart.yaml b/dts/bindings/serial/intel,lw_uart.yaml
index 798dfa53225..4687ebcfe4a 100644
--- a/dts/bindings/serial/intel,lw_uart.yaml
+++ b/dts/bindings/serial/intel,lw_uart.yaml
@@ -17,3 +17,13 @@ properties:
     type: boolean
     description: |
       Baud rate cannot be changed by software (Divisor register is not writable)
+
+  stop-bits:
+    description: |
+      Sets the number of stop bits. Defaults to standard of 1 if not specified.
+    default: "1"
+
+  data-bits:
+    description: |
+      Sets the number of data bits. Defaults to standard of 8 if not specified.
+    default: 8
diff --git a/dts/bindings/serial/ite,it51xxx-uart.yaml b/dts/bindings/serial/ite,it51xxx-uart.yaml
new file mode 100644
index 00000000000..cc6fae88b4b
--- /dev/null
+++ b/dts/bindings/serial/ite,it51xxx-uart.yaml
@@ -0,0 +1,22 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE, IT51XXX-UART node
+
+compatible: "ite,it51xxx-uart"
+
+include: [uart-controller.yaml]
+
+properties:
+  reg:
+    required: true
+
+  wucctrl:
+    type: phandles
+    description: |
+      WUC groups internal and external inputs, and asserts wake-up
+      signals to INTC that allows the CPU to exit a Doze/Deep
+      Doze/Sleep mode.
+
+  clocks:
+    required: true
diff --git a/dts/bindings/serial/microchip,mec5-uart.yaml b/dts/bindings/serial/microchip,mec5-uart.yaml
new file mode 100644
index 00000000000..d37c196d046
--- /dev/null
+++ b/dts/bindings/serial/microchip,mec5-uart.yaml
@@ -0,0 +1,55 @@
+# Copyright (c) 2024 Microchip Technology Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Microchip MEC5 UART
+
+compatible: "microchip,mec5-uart"
+
+include: [uart-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  fifo-mode-disable:
+    type: boolean
+    description: |
+      Disable 16550 FIFO mode. Both 16-byte TX and RX FIFOs will be
+      disabled. UART will revert to a one byte holding register for
+      TX and RX.
+
+  rx-fifo-trig:
+    type: string
+    default: "8"
+    description: |
+      RX FIFO byte count trigger limit. When the number of received bytes
+      reaches this level the UART will signal an interrupt if enabled.
+    enum:
+      - "1"
+      - "4"
+      - "8"
+      - "14"
+
+  use-extclk:
+    type: boolean
+    description: |
+      Optional source of an external UART clock. If present the
+      driver will use this pin as the UART input clock source.
+      The pin should have a 1.8432 MHz clock waveform for normal
+      UART BAUD rates or 48 MHz for high speed BAUD rates.
+      Refer to data sheet for the pin(s) available as external UART
+      clock input. The pin should be added to the default PINCTRL list.
+      Example using external 1.8432MHz clock on MEC5 external UART clock pin.
+
+        clock-frequency = <1843200>;
+        pinctrl-0 = < &uart1_tx_gpio170 &uart1_tx_gpio171 &uart_clk_gpio025>;
+        pinctrl-names = "default";
diff --git a/dts/bindings/serial/neorv32,uart.yaml b/dts/bindings/serial/neorv32,uart.yaml
new file mode 100644
index 00000000000..3d9eca3135c
--- /dev/null
+++ b/dts/bindings/serial/neorv32,uart.yaml
@@ -0,0 +1,24 @@
+description: NEORV32 UART
+
+compatible: "neorv32,uart"
+
+include: uart-controller.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  interrupt-names:
+    required: true
+
+  current-speed:
+    required: true
+
+  syscon:
+    type: phandle
+    required: true
+    description: |
+      phandle to syscon (NEORV32 SYSINFO) node.
diff --git a/dts/bindings/serial/neorv32-uart.yaml b/dts/bindings/serial/neorv32-uart.yaml
deleted file mode 100644
index 8c9b8334c0b..00000000000
--- a/dts/bindings/serial/neorv32-uart.yaml
+++ /dev/null
@@ -1,24 +0,0 @@
-description: NEORV32 UART
-
-compatible: "neorv32-uart"
-
-include: uart-controller.yaml
-
-properties:
-  reg:
-    required: true
-
-  interrupts:
-    required: true
-
-  interrupt-names:
-    required: true
-
-  current-speed:
-    required: true
-
-  syscon:
-    type: phandle
-    required: true
-    description: |
-      phandle to syscon (NEORV32 SYSINFO) node.
diff --git a/dts/bindings/serial/nxp,s32-linflexd.yaml b/dts/bindings/serial/nxp,s32-linflexd.yaml
index 0c4e014da8f..a5402f6bff2 100644
--- a/dts/bindings/serial/nxp,s32-linflexd.yaml
+++ b/dts/bindings/serial/nxp,s32-linflexd.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022 NXP
+# Copyright 2022, 2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 description: NXP S32 LINFlexD
@@ -19,3 +19,21 @@ properties:
 
   pinctrl-names:
     required: true
+
+  clocks:
+    required: true
+
+  current-speed:
+    description: |
+      Initial baud rate setting for UART. Defaults to standard baudrate of 115200 if not specified.
+    default: 115200
+
+  stop-bits:
+    description: |
+      Sets the number of stop bits. Defaults to standard of 1 if not specified.
+    default: "1"
+
+  data-bits:
+    description: |
+      Sets the number of data bits. Defaults to standard of 8 if not specified.
+    default: 8
diff --git a/dts/bindings/serial/renesas,ra-uart-sci.yaml b/dts/bindings/serial/renesas,ra-uart-sci.yaml
deleted file mode 100644
index 94229b06924..00000000000
--- a/dts/bindings/serial/renesas,ra-uart-sci.yaml
+++ /dev/null
@@ -1,8 +0,0 @@
-# Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
-# SPDX-License-Identifier: Apache-2.0
-
-description: Renesas RA Series SCI based UART controller
-
-compatible: "renesas,ra-uart-sci"
-
-include: [uart-controller.yaml]
diff --git a/dts/bindings/serial/renesas,rz-sci-uart.yaml b/dts/bindings/serial/renesas,rz-sci-uart.yaml
new file mode 100644
index 00000000000..cd5807f4132
--- /dev/null
+++ b/dts/bindings/serial/renesas,rz-sci-uart.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RZ SCI UART controller
+
+compatible: "renesas,rz-sci-uart"
+
+include: [uart-controller.yaml, pinctrl-device.yaml]
diff --git a/dts/bindings/serial/renesas,rz-scif-uart.yaml b/dts/bindings/serial/renesas,rz-scif-uart.yaml
index b362a09e474..1d3ae33b1b2 100644
--- a/dts/bindings/serial/renesas,rz-scif-uart.yaml
+++ b/dts/bindings/serial/renesas,rz-scif-uart.yaml
@@ -8,6 +8,21 @@ compatible: "renesas,rz-scif-uart"
 include: [uart-controller.yaml, pinctrl-device.yaml]
 
 properties:
+  current-speed:
+    description: |
+      Initial baud rate setting for UART. Defaults to standard baudrate of 115200 if not specified.
+    default: 115200
+
+  stop-bits:
+    description: |
+      Sets the number of stop bits. Defaults to standard of 1 if not specified.
+    default: "1"
+
+  data-bits:
+    description: |
+      Sets the number of data bits. Defaults to standard of 8 if not specified.
+    default: 8
+
   channel:
     type: int
     required: true
diff --git a/dts/bindings/serial/renesas,rza2m-scif-uart.yaml b/dts/bindings/serial/renesas,rza2m-scif-uart.yaml
new file mode 100644
index 00000000000..c749eb990e5
--- /dev/null
+++ b/dts/bindings/serial/renesas,rza2m-scif-uart.yaml
@@ -0,0 +1,20 @@
+description: Renesas RZ/A2M UART
+
+compatible: "renesas,rza2m-scif-uart"
+
+include: [uart-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  clocks:
+    description: |
+      Clock source for calculating BRR value
+
+  channel:
+    type: int
+    required: true
diff --git a/dts/bindings/serial/renesas,rzt2m-uart.yaml b/dts/bindings/serial/renesas,rzt2m-uart.yaml
index 967972ac7c8..9ab38e8f638 100644
--- a/dts/bindings/serial/renesas,rzt2m-uart.yaml
+++ b/dts/bindings/serial/renesas,rzt2m-uart.yaml
@@ -22,5 +22,15 @@ properties:
       - 9600
       - 115200
 
+  stop-bits:
+    description: |
+      Sets the number of stop bits. Defaults to standard of 1 if not specified.
+    default: "1"
+
+  data-bits:
+    description: |
+      Sets the number of data bits. Defaults to standard of 8 if not specified.
+    default: 8
+
   interrupts:
     required: true
diff --git a/dts/bindings/serial/sensry,sy1xx-uart.yaml b/dts/bindings/serial/sensry,sy1xx-uart.yaml
index fbb98dded3c..99007cf648d 100644
--- a/dts/bindings/serial/sensry,sy1xx-uart.yaml
+++ b/dts/bindings/serial/sensry,sy1xx-uart.yaml
@@ -5,7 +5,7 @@ description: Sensry SY1xx UART
 
 compatible: "sensry,sy1xx-uart"
 
-include: uart-controller.yaml
+include: [uart-controller.yaml, pinctrl-device.yaml]
 
 properties:
   reg:
diff --git a/dts/bindings/serial/silabs,eusart-uart.yaml b/dts/bindings/serial/silabs,eusart-uart.yaml
new file mode 100644
index 00000000000..c546abcba73
--- /dev/null
+++ b/dts/bindings/serial/silabs,eusart-uart.yaml
@@ -0,0 +1,27 @@
+description: Silabs EUSART UART
+
+compatible: "silabs,eusart-uart"
+
+include: [uart-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  current-speed:
+    description: |
+      Initial baud rate setting for UART. Defaults to standard baudrate of 115200 if not specified.
+    default: 115200
+
+  stop-bits:
+    description: |
+      Sets the number of stop bits. Defaults to standard of 1 if not specified.
+    default: "1"
+
+  data-bits:
+    description: |
+      Sets the number of data bits. Defaults to standard of 8 if not specified.
+    default: 8
diff --git a/dts/bindings/serial/silabs,gecko-uart.yaml b/dts/bindings/serial/silabs,gecko-uart.yaml
index ae22286e72b..0ed866631be 100644
--- a/dts/bindings/serial/silabs,gecko-uart.yaml
+++ b/dts/bindings/serial/silabs,gecko-uart.yaml
@@ -11,6 +11,21 @@ properties:
   interrupts:
     required: true
 
+  current-speed:
+    description: |
+      Initial baud rate setting for UART. Defaults to standard baudrate of 115200 if not specified.
+    default: 115200
+
+  stop-bits:
+    description: |
+      Sets the number of stop bits. Defaults to standard of 1 if not specified.
+    default: "1"
+
+  data-bits:
+    description: |
+      Sets the number of data bits. Defaults to standard of 8 if not specified.
+    default: 8
+
   peripheral-id:
     type: int
     required: true
diff --git a/dts/bindings/serial/silabs,gecko-usart.yaml b/dts/bindings/serial/silabs,gecko-usart.yaml
index 14d0fad61bd..adefd0fddb1 100644
--- a/dts/bindings/serial/silabs,gecko-usart.yaml
+++ b/dts/bindings/serial/silabs,gecko-usart.yaml
@@ -11,6 +11,21 @@ properties:
   interrupts:
     required: true
 
+  current-speed:
+    description: |
+      Initial baud rate setting for UART. Defaults to standard baudrate of 115200 if not specified.
+    default: 115200
+
+  stop-bits:
+    description: |
+      Sets the number of stop bits. Defaults to standard of 1 if not specified.
+    default: "1"
+
+  data-bits:
+    description: |
+      Sets the number of data bits. Defaults to standard of 8 if not specified.
+    default: 8
+
   peripheral-id:
     type: int
     description: peripheral ID
diff --git a/dts/bindings/serial/silabs,usart-uart.yaml b/dts/bindings/serial/silabs,usart-uart.yaml
new file mode 100644
index 00000000000..9d01c3b05d5
--- /dev/null
+++ b/dts/bindings/serial/silabs,usart-uart.yaml
@@ -0,0 +1,27 @@
+description: Silabs USART UART
+
+compatible: "silabs,usart-uart"
+
+include: [uart-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  current-speed:
+    description: |
+      Initial baud rate setting for UART. Defaults to standard baudrate of 115200 if not specified.
+    default: 115200
+
+  stop-bits:
+    description: |
+      Sets the number of stop bits. Defaults to standard of 1 if not specified.
+    default: "1"
+
+  data-bits:
+    description: |
+      Sets the number of data bits. Defaults to standard of 8 if not specified.
+    default: 8
diff --git a/dts/bindings/serial/st,stm32-uart-base.yaml b/dts/bindings/serial/st,stm32-uart-base.yaml
index 37b6e66762b..f8323111743 100644
--- a/dts/bindings/serial/st,stm32-uart-base.yaml
+++ b/dts/bindings/serial/st,stm32-uart-base.yaml
@@ -25,6 +25,21 @@ properties:
   interrupts:
     required: true
 
+  current-speed:
+    description: |
+      Initial baud rate setting for UART. Defaults to standard baudrate of 115200 if not specified.
+    default: 115200
+
+  stop-bits:
+    description: |
+      Sets the number of stop bits. Defaults to standard of 1 if not specified.
+    default: "1"
+
+  data-bits:
+    description: |
+      Sets the number of data bits. Defaults to standard of 8 if not specified.
+    default: 8
+
   single-wire:
     type: boolean
     description: |
diff --git a/dts/bindings/serial/ti,cc13xx-cc26xx-uart.yaml b/dts/bindings/serial/ti,cc13xx-cc26xx-uart.yaml
index 5b13c83934c..1ba0920602d 100644
--- a/dts/bindings/serial/ti,cc13xx-cc26xx-uart.yaml
+++ b/dts/bindings/serial/ti,cc13xx-cc26xx-uart.yaml
@@ -13,3 +13,16 @@ properties:
 
   interrupts:
     required: true
+
+  current-speed:
+    required: true
+
+  stop-bits:
+    description: |
+      Sets the number of stop bits. Defaults to standard of 1 if not specified.
+    default: "1"
+
+  data-bits:
+    description: |
+      Sets the number of data bits. Defaults to standard of 8 if not specified.
+    default: 8
diff --git a/dts/bindings/serial/ti,cc23x0-uart.yaml b/dts/bindings/serial/ti,cc23x0-uart.yaml
new file mode 100644
index 00000000000..f2587a0a267
--- /dev/null
+++ b/dts/bindings/serial/ti,cc23x0-uart.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+# Copyright (c) 2024 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI SimpleLink CC23X0 UART node
+
+compatible: "ti,cc23x0-uart"
+
+include: [uart-controller.yaml, pinctrl-device.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  stop-bits:
+    description: |
+      Sets the number of stop bits. Defaults to standard of 1 if not specified.
+    default: "1"
+
+  data-bits:
+    description: |
+      Sets the number of data bits. Defaults to standard of 8 if not specified.
+    default: 8
diff --git a/dts/bindings/serial/uart-controller.yaml b/dts/bindings/serial/uart-controller.yaml
index 3c4873fedef..092ca39ee8b 100644
--- a/dts/bindings/serial/uart-controller.yaml
+++ b/dts/bindings/serial/uart-controller.yaml
@@ -18,11 +18,15 @@ properties:
     type: string
     description: |
       Configures the parity of the adapter. Enumeration id 0 for none, 1 for odd
-      and 2 for even parity. Default to none if not specified.
+      and 2 for even parity, 3 for mark parity and 4 for space parity.
+      Default to none if not specified.
     enum:
       - "none"
       - "odd"
       - "even"
+      - "mark"
+      - "space"
+    default: "none"
   stop-bits:
     type: string
     description: |
diff --git a/dts/bindings/serial/zephyr,cdc-acm-uart.yaml b/dts/bindings/serial/zephyr,cdc-acm-uart.yaml
index 8e0a0030978..6b7ad36d1d1 100644
--- a/dts/bindings/serial/zephyr,cdc-acm-uart.yaml
+++ b/dts/bindings/serial/zephyr,cdc-acm-uart.yaml
@@ -21,3 +21,8 @@ properties:
     default: 1024
     description: |
       Size of the virtual CDC ACM UART RX FIFO
+
+  label:
+    description: |
+      The string defined by the label property is also used for the USB
+      interface string descriptor.
diff --git a/dts/bindings/serial/zephyr,native-posix-uart.yaml b/dts/bindings/serial/zephyr,native-posix-uart.yaml
index 7cd8d186e83..1357a199606 100644
--- a/dts/bindings/serial/zephyr,native-posix-uart.yaml
+++ b/dts/bindings/serial/zephyr,native-posix-uart.yaml
@@ -6,3 +6,5 @@ description: Native POSIX UART
 compatible: "zephyr,native-posix-uart"
 
 include: uart-controller.yaml
+
+# This binding is deprecated in favor of zephyr,native-pty-uart
diff --git a/dts/bindings/serial/zephyr,native-pty-uart.yaml b/dts/bindings/serial/zephyr,native-pty-uart.yaml
new file mode 100644
index 00000000000..56d2312b19d
--- /dev/null
+++ b/dts/bindings/serial/zephyr,native-pty-uart.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2019, Jan Van Winkel (jan.van_winkel@dxplore.eu)
+# SPDX-License-Identifier: Apache-2.0
+
+description: Native PTY UART
+
+compatible: "zephyr,native-pty-uart"
+
+include: uart-controller.yaml
diff --git a/dts/bindings/shi/ite,it8xxx2-shi.yaml b/dts/bindings/shi/ite,it8xxx2-shi.yaml
index f7cc28c0d24..1aa91357706 100644
--- a/dts/bindings/shi/ite,it8xxx2-shi.yaml
+++ b/dts/bindings/shi/ite,it8xxx2-shi.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 Google LLC
 # SPDX-License-Identifier: Apache-2.0
 
-description: ITE, IT8XXX2 Serial Host Interface (SHI) node
+description: ITE IT8XXX2 Serial Host Interface (SHI)
 
 compatible: "ite,it8xxx2-shi"
 
diff --git a/dts/bindings/shi/nuvoton,npcx-shi-enhanced.yaml b/dts/bindings/shi/nuvoton,npcx-shi-enhanced.yaml
index dc197fb6fd8..8483af14168 100644
--- a/dts/bindings/shi/nuvoton,npcx-shi-enhanced.yaml
+++ b/dts/bindings/shi/nuvoton,npcx-shi-enhanced.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 Google LLC
 # SPDX-License-Identifier: Apache-2.0
 
-description: Nuvoton, NPCX Serial Host Interface (SHI) node
+description: Nuvoton NPCX Serial Host Interface (SHI)
 
 compatible: "nuvoton,npcx-shi-enhanced"
 
diff --git a/dts/bindings/shi/nuvoton,npcx-shi.yaml b/dts/bindings/shi/nuvoton,npcx-shi.yaml
index b24e3f3100a..27a20be3106 100644
--- a/dts/bindings/shi/nuvoton,npcx-shi.yaml
+++ b/dts/bindings/shi/nuvoton,npcx-shi.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 Google LLC
 # SPDX-License-Identifier: Apache-2.0
 
-description: Nuvoton, NPCX Serial Host Interface (SHI) node
+description: Nuvoton NPCX Serial Host Interface (SHI)
 
 compatible: "nuvoton,npcx-shi"
 
diff --git a/dts/bindings/smbus/intel,pch-smbus.yaml b/dts/bindings/smbus/intel,pch-smbus.yaml
index b3475f3ae31..d1e51fcc960 100644
--- a/dts/bindings/smbus/intel,pch-smbus.yaml
+++ b/dts/bindings/smbus/intel,pch-smbus.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-description: Intel Platform Controller Hub SMBus node
+description: Intel Platform Controller Hub SMBus
 
 compatible: "intel,pch-smbus"
 
diff --git a/dts/bindings/spi/ambiq,mspi.yaml b/dts/bindings/spi/ambiq,mspi.yaml
index 0c48f6605e6..0e8caa7bc73 100644
--- a/dts/bindings/spi/ambiq,mspi.yaml
+++ b/dts/bindings/spi/ambiq,mspi.yaml
@@ -5,7 +5,7 @@ description: Ambiq MSPI
 
 compatible: "ambiq,mspi"
 
-include: [spi-controller.yaml, pinctrl-device.yaml, ambiq-pwrcfg.yaml]
+include: [spi-controller.yaml, pinctrl-device.yaml]
 
 properties:
   reg:
@@ -13,6 +13,3 @@ properties:
 
   interrupts:
     required: true
-
-  ambiq,pwrcfg:
-    required: true
diff --git a/dts/bindings/spi/ambiq,spi-bleif.yaml b/dts/bindings/spi/ambiq,spi-bleif.yaml
index 2be2ee1b9f8..3983c87195d 100644
--- a/dts/bindings/spi/ambiq,spi-bleif.yaml
+++ b/dts/bindings/spi/ambiq,spi-bleif.yaml
@@ -8,11 +8,8 @@ description: |
 
 compatible: "ambiq,spi-bleif"
 
-include: [spi-controller.yaml, pinctrl-device.yaml, ambiq-pwrcfg.yaml]
+include: [spi-controller.yaml, pinctrl-device.yaml]
 
 properties:
   reg:
     required: true
-
-  ambiq,pwrcfg:
-    required: true
diff --git a/dts/bindings/spi/ambiq,spi.yaml b/dts/bindings/spi/ambiq,spi.yaml
index 425c7fc44ee..aff02ab65a6 100644
--- a/dts/bindings/spi/ambiq,spi.yaml
+++ b/dts/bindings/spi/ambiq,spi.yaml
@@ -5,17 +5,4 @@ description: Ambiq SPI
 
 compatible: "ambiq,spi"
 
-include: [spi-controller.yaml, pinctrl-device.yaml, ambiq-pwrcfg.yaml]
-
-properties:
-  reg:
-    required: true
-
-  interrupts:
-    required: true
-
-  clock-frequency:
-    required: true
-
-  ambiq,pwrcfg:
-    required: true
+include: [spi-controller.yaml, pinctrl-device.yaml]
diff --git a/dts/bindings/spi/ambiq,spid.yaml b/dts/bindings/spi/ambiq,spid.yaml
index d6d4be55c83..c04db4ac09f 100644
--- a/dts/bindings/spi/ambiq,spid.yaml
+++ b/dts/bindings/spi/ambiq,spid.yaml
@@ -5,7 +5,7 @@ description: Ambiq SPI Device
 
 compatible: "ambiq,spid"
 
-include: [spi-controller.yaml, pinctrl-device.yaml, ambiq-pwrcfg.yaml]
+include: [spi-controller.yaml, pinctrl-device.yaml]
 
 properties:
   int-gpios:
diff --git a/dts/bindings/spi/arm,pl022.yaml b/dts/bindings/spi/arm,pl022.yaml
index 2e5094bf204..f83d1d28f58 100644
--- a/dts/bindings/spi/arm,pl022.yaml
+++ b/dts/bindings/spi/arm,pl022.yaml
@@ -5,7 +5,7 @@ description: ARM PL022 SPI
 
 compatible: "arm,pl022"
 
-include: [spi-controller.yaml, pinctrl-device.yaml]
+include: [spi-controller.yaml, pinctrl-device.yaml, reset-device.yaml]
 
 properties:
   reg:
diff --git a/dts/bindings/spi/atmel,sam0-spi.yaml b/dts/bindings/spi/atmel,sam0-spi.yaml
index 8b1c79b8220..ea5a5750111 100644
--- a/dts/bindings/spi/atmel,sam0-spi.yaml
+++ b/dts/bindings/spi/atmel,sam0-spi.yaml
@@ -1,4 +1,5 @@
 # Copyright (c) 2018, Google LLC.
+# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
 description: Atmel SAM0 SERCOM SPI controller
@@ -8,6 +9,7 @@ compatible: "atmel,sam0-spi"
 include:
   - name: spi-controller.yaml
   - name: pinctrl-device.yaml
+  - name: atmel,assigned-clocks.yaml
 
 properties:
   reg:
@@ -19,6 +21,12 @@ properties:
   clock-names:
     required: true
 
+  atmel,assigned-clocks:
+    required: true
+
+  atmel,assigned-clock-names:
+    required: true
+
   dipo:
     type: int
     required: true
diff --git a/dts/bindings/spi/cdns,spi.yaml b/dts/bindings/spi/cdns,spi.yaml
new file mode 100644
index 00000000000..e4964f7fbf9
--- /dev/null
+++ b/dts/bindings/spi/cdns,spi.yaml
@@ -0,0 +1,58 @@
+# Copyright (c) 2024, Meta Platforms
+# SPDX-License-Identifier: Apache-2.0
+
+description: Cadence SPI controller
+
+compatible: "cdns,spi"
+
+include: [spi-controller.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  clock-frequency:
+    required: true
+
+  clock-frequency-ext:
+    type: int
+
+  fifo-width:
+    type: int
+    required: true
+    enum:
+      - 8
+      - 16
+      - 24
+      - 32
+    description: |
+      The total fifo width in bits
+
+  rx-fifo-depth:
+    type: int
+    required: true
+    enum:
+      - 8
+      - 16
+      - 32
+      - 64
+      - 128
+      - 256
+    description: |
+      The depth of the rx fifo
+
+  tx-fifo-depth:
+    type: int
+    required: true
+    enum:
+      - 8
+      - 16
+      - 32
+      - 64
+      - 128
+      - 256
+    description: |
+      The depth of the tx fifo
diff --git a/dts/bindings/spi/cypress,psoc6-spi.yaml b/dts/bindings/spi/cypress,psoc6-spi.yaml
index 3a162ec2cd3..7d3b5011b7c 100644
--- a/dts/bindings/spi/cypress,psoc6-spi.yaml
+++ b/dts/bindings/spi/cypress,psoc6-spi.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021, ATL Electronics
 # SPDX-License-Identifier: Apache-2.0
 
-description: Cypress SBC[SPI]
+description: Cypress SBC SPI controller
 
 compatible: "cypress,psoc6-spi"
 
diff --git a/dts/bindings/spi/microchip,mpfs-qspi.yaml b/dts/bindings/spi/microchip,mpfs-qspi.yaml
index ab3c66809b3..c38b0e557be 100644
--- a/dts/bindings/spi/microchip,mpfs-qspi.yaml
+++ b/dts/bindings/spi/microchip,mpfs-qspi.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 Microchip Technology Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Microchip Polarfire SOC QSPI IP node
+description: Microchip Polarfire SOC QSPI controller
 
 compatible: "microchip,mpfs-qspi"
 
diff --git a/dts/bindings/spi/microchip,mpfs-spi.yaml b/dts/bindings/spi/microchip,mpfs-spi.yaml
index 7ec6536ca83..b76a643e471 100644
--- a/dts/bindings/spi/microchip,mpfs-spi.yaml
+++ b/dts/bindings/spi/microchip,mpfs-spi.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 Microchip Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Microchip Polarfire SOC SPI IP node
+description: Microchip Polarfire SOC SPI controller
 
 compatible: "microchip,mpfs-spi"
 
diff --git a/dts/bindings/spi/nxp,lpspi.yaml b/dts/bindings/spi/nxp,lpspi.yaml
index ec4e742a8dc..4064b85c703 100644
--- a/dts/bindings/spi/nxp,lpspi.yaml
+++ b/dts/bindings/spi/nxp,lpspi.yaml
@@ -18,19 +18,22 @@ properties:
     type: int
     description: |
       Delay in nanoseconds from the chip select assert to the first clock
-      edge. If not set, the minimum supported delay is used.
+      edge.
+      If not set, the minimum supported delay is used.
 
   sck-pcs-delay:
     type: int
     description: |
       Delay in nanoseconds from the last clock edge to the chip select
-      deassert. If not set, the minimum supported delay is used.
+      deassert.
+      If not set, the minimum supported delay is used.
 
   transfer-delay:
     type: int
     description: |
-      Delay in nanoseconds from the chip select deassert to the next chip
-      select assert. If not set, the minimum supported delay is used.
+      Delay in nanoseconds between last SCK edge of a transfer word and the
+      first SCK edge of the next transfer word.
+      If not set, the minimum supported delay is used.
 
   data-pin-config:
     type: string
@@ -43,3 +46,22 @@ properties:
     description: |
       Configures which pins (SDO and SDI) are used for input and output data
       during single bit transfers.
+
+  tristate-output:
+    type: boolean
+    description:
+      Configures whether or not the output data is tristated between accesses
+      (when PCS is negated). If set, the output will be tristated when PCS is negated,
+      otherwise the output line retains the last value when PCS is negated.
+
+  rx-fifo-size:
+    type: int
+    required: true
+    description: |
+      Max number of words in the RX fifo on this instance of the LPSPI.
+
+  tx-fifo-size:
+    type: int
+    required: true
+    description: |
+      Max number of words in the TX/Command fifo on this instance of the LPSPI.
diff --git a/dts/bindings/spi/nxp,xspi.yaml b/dts/bindings/spi/nxp,xspi.yaml
new file mode 100644
index 00000000000..236ad62ba48
--- /dev/null
+++ b/dts/bindings/spi/nxp,xspi.yaml
@@ -0,0 +1,20 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP XSPI controller
+
+compatible: "nxp,xspi"
+
+include: [spi-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+child-binding:
+  description: NXP XSPI port
+
+  include: nxp,xspi-device.yaml
diff --git a/dts/bindings/spi/raspberrypi,pico-spi.yaml b/dts/bindings/spi/raspberrypi,pico-spi.yaml
index e039bcf7d1f..ad5a23baaa3 100644
--- a/dts/bindings/spi/raspberrypi,pico-spi.yaml
+++ b/dts/bindings/spi/raspberrypi,pico-spi.yaml
@@ -2,4 +2,4 @@ description: Raspberry Pi Pico SPI
 
 compatible: "raspberrypi,pico-spi"
 
-include: ["arm,pl022.yaml", "reset-device.yaml"]
+include: "arm,pl022.yaml"
diff --git a/dts/bindings/spi/silabs,eusart-spi.yaml b/dts/bindings/spi/silabs,eusart-spi.yaml
new file mode 100644
index 00000000000..59a10502e70
--- /dev/null
+++ b/dts/bindings/spi/silabs,eusart-spi.yaml
@@ -0,0 +1,21 @@
+description: Silabs EUSART SPI
+
+compatible: "silabs,eusart-spi"
+
+include: [spi-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  clocks:
+    required: true
diff --git a/dts/bindings/spi/silabs,gecko-spi-eusart.yaml b/dts/bindings/spi/silabs,gecko-spi-eusart.yaml
deleted file mode 100644
index 1663c8ec8dc..00000000000
--- a/dts/bindings/spi/silabs,gecko-spi-eusart.yaml
+++ /dev/null
@@ -1,21 +0,0 @@
-description: GECKO EUSART SPI
-
-compatible: "silabs,gecko-spi-eusart"
-
-include: [spi-controller.yaml, pinctrl-device.yaml]
-
-properties:
-  reg:
-    required: true
-
-  interrupts:
-    required: true
-
-  pinctrl-0:
-    required: true
-
-  pinctrl-names:
-    required: true
-
-  clocks:
-    required: true
diff --git a/dts/bindings/spi/silabs,gecko-spi-usart.yaml b/dts/bindings/spi/silabs,gecko-spi-usart.yaml
deleted file mode 100644
index df3bcc6ccbc..00000000000
--- a/dts/bindings/spi/silabs,gecko-spi-usart.yaml
+++ /dev/null
@@ -1,31 +0,0 @@
-description: GECKO USART SPI
-
-compatible: "silabs,gecko-spi-usart"
-
-include: [spi-controller.yaml, pinctrl-device.yaml]
-
-properties:
-  reg:
-    required: true
-
-  interrupts:
-    required: true
-
-  peripheral-id:
-    type: int
-    description: peripheral ID
-
-  # Note: Not all SoC series support setting individual pin location. If this
-  # is a case all location-* properties need to have identical value.
-
-  location-rx:
-    type: array
-    description: RX pin configuration defined as <location port pin>
-
-  location-tx:
-    type: array
-    description: TX pin configuration defined as <location port pin>
-
-  location-clk:
-    type: array
-    description: CLK pin configuration defined as <location port pin>
diff --git a/dts/bindings/spi/silabs,usart-spi.yaml b/dts/bindings/spi/silabs,usart-spi.yaml
new file mode 100644
index 00000000000..1b149097412
--- /dev/null
+++ b/dts/bindings/spi/silabs,usart-spi.yaml
@@ -0,0 +1,31 @@
+description: Silabs USART SPI
+
+compatible: "silabs,usart-spi"
+
+include: [spi-controller.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  peripheral-id:
+    type: int
+    description: peripheral ID
+
+  # Note: Not all SoC series support setting individual pin location. If this
+  # is a case all location-* properties need to have identical value.
+
+  location-rx:
+    type: array
+    description: RX pin configuration defined as <location port pin>
+
+  location-tx:
+    type: array
+    description: TX pin configuration defined as <location port pin>
+
+  location-clk:
+    type: array
+    description: CLK pin configuration defined as <location port pin>
diff --git a/dts/bindings/spi/snps,designware-spi.yaml b/dts/bindings/spi/snps,designware-spi.yaml
index 01073f8d003..16badb5b8ed 100644
--- a/dts/bindings/spi/snps,designware-spi.yaml
+++ b/dts/bindings/spi/snps,designware-spi.yaml
@@ -2,7 +2,7 @@
 # Copyright (c) 2023 Meta Platforms All rights reserved.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Synopsys DesignWare SPI node
+description: Synopsys DesignWare SPI controller
 
 compatible: "snps,designware-spi"
 
diff --git a/dts/bindings/spi/st,stm32-spi-host-cmd.yaml b/dts/bindings/spi/st,stm32-spi-host-cmd.yaml
index db5cb55d5f2..944048315f6 100644
--- a/dts/bindings/spi/st,stm32-spi-host-cmd.yaml
+++ b/dts/bindings/spi/st,stm32-spi-host-cmd.yaml
@@ -3,6 +3,7 @@
 
 description: |
         Host Command version of STM32 SPI controller.
+
         All properties are the same, but a different driver is used.
 
 compatible: "st,stm32-spi-host-cmd"
diff --git a/dts/bindings/spi/st,stm32h7-spi.yaml b/dts/bindings/spi/st,stm32h7-spi.yaml
index 69f1a8c52ae..252d6b09d4a 100644
--- a/dts/bindings/spi/st,stm32h7-spi.yaml
+++ b/dts/bindings/spi/st,stm32h7-spi.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-        STM32H7 SPI controller
+        STM32H7 SPI controller.
+
         This compatible stands for all SPI hardware blocks matching the
         version available in STM32H7 SoCs.
         This version of STM32 SPI hardware block could be identified by the
diff --git a/dts/bindings/spi/ti,cc13xx-cc26xx-spi.yaml b/dts/bindings/spi/ti,cc13xx-cc26xx-spi.yaml
index b614c7f4336..57ebef93010 100644
--- a/dts/bindings/spi/ti,cc13xx-cc26xx-spi.yaml
+++ b/dts/bindings/spi/ti,cc13xx-cc26xx-spi.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2019 Brett Witherspoon
 # SPDX-License-Identifier: Apache-2.0
 
-description: TI SimpleLink CC13xx / CC26xx SPI node
+description: TI SimpleLink CC13xx / CC26xx SPI controller
 
 compatible: "ti,cc13xx-cc26xx-spi"
 
diff --git a/dts/bindings/spi/ti,cc23x0-spi.yaml b/dts/bindings/spi/ti,cc23x0-spi.yaml
new file mode 100644
index 00000000000..c58d46901f2
--- /dev/null
+++ b/dts/bindings/spi/ti,cc23x0-spi.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2024 BayLibre, SAS
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI SimpleLink CC23x0 SPI controller
+
+compatible: "ti,cc23x0-spi"
+
+include: [spi-controller.yaml, pinctrl-device.yaml, base.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
diff --git a/dts/bindings/spi/xlnx,xps-spi-2.00.a.yaml b/dts/bindings/spi/xlnx,xps-spi-2.00.a.yaml
index 092cbcb2e5b..4a26db0a076 100644
--- a/dts/bindings/spi/xlnx,xps-spi-2.00.a.yaml
+++ b/dts/bindings/spi/xlnx,xps-spi-2.00.a.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2020 Henrik Brix Andersen <henrik@brixandersen.dk>
 # SPDX-License-Identifier: Apache-2.0
 
-description: Xilinx AXI Quad SPI IP node
+description: Xilinx AXI Quad SPI controller
 
 compatible: "xlnx,xps-spi-2.00.a"
 
diff --git a/dts/bindings/sram/mmio-sram.yaml b/dts/bindings/sram/mmio-sram.yaml
index e1255e185c4..d8a282bb2e1 100644
--- a/dts/bindings/sram/mmio-sram.yaml
+++ b/dts/bindings/sram/mmio-sram.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2018, Linaro Limited
 # SPDX-License-Identifier: Apache-2.0
 
-description: Generic on-chip SRAM description
+description: Generic on-chip SRAM
 
 compatible: "mmio-sram"
 
diff --git a/dts/bindings/stepper/adi/adi,tmc2209.yaml b/dts/bindings/stepper/adi/adi,tmc2209.yaml
index 96a13bfe94d..17e44b27308 100644
--- a/dts/bindings/stepper/adi/adi,tmc2209.yaml
+++ b/dts/bindings/stepper/adi/adi,tmc2209.yaml
@@ -19,12 +19,6 @@ compatible: "adi,tmc2209"
 
 include:
   - name: stepper-controller.yaml
-    property-allowlist:
-      - micro-step-res
-      - step-gpios
-      - dir-gpios
-      - en-gpios
-      - counter
 
 properties:
   msx-gpios:
diff --git a/dts/bindings/stepper/adi/adi,tmc5041.yaml b/dts/bindings/stepper/adi/adi,tmc5041.yaml
deleted file mode 100644
index ba856b7fa65..00000000000
--- a/dts/bindings/stepper/adi/adi,tmc5041.yaml
+++ /dev/null
@@ -1,117 +0,0 @@
-# SPDX-FileCopyrightText: Copyright (c) 2024 Carl Zeiss Meditec AG
-# SPDX-License-Identifier: Apache-2.0
-
-description: |
-  Analog Devices TMC5041 Stepper Motor Controller
-
-  Example:
-
-    #include <zephyr/dt-bindings/stepper/adi/tmc5041_reg.h>
-
-    &spi0 {
-        /* SPI bus options here, not shown */
-
-        /* Dual controller/driver for up to two 2-phase bipolar stepper motors */
-        tmc5041: tmc5041@0 {
-            compatible = "adi,tmc5041";
-            reg = <0>;
-            spi-max-frequency = <DT_FREQ_M(24)>; /* Maximum SPI bus frequency */
-
-            #address-cells = <1>;
-            #size-cells = <0>;
-
-            poscmp_enable; test_mode; lock_gconf; /* ADI TMC Global configuration flags */
-            clock-frequency = <DT_FREQ_M(16)>; /* Internal/External Clock frequency */
-
-            motor: motor@0 {
-                status = "okay";
-                reg = <0>;
-
-                /* common stepper controller settings */
-                invert-direction;
-                micro-step-res = <256>;
-
-                /* ADI TMC stallguard settings specific to TMC5041 */
-                activate-stallguard2;
-                stallguard-velocity-check-interval-ms=<100>;
-                stallguard2-threshold=<9>;
-                stallguard-threshold-velocity=<500000>;
-
-                /* ADI TMC ramp generator as well as current settings */
-                vstart = <10>;
-                a1 = <20>;
-                v1 = <30>;
-                d1 = <40>;
-                vmax = <50>;
-                amax = <60>;
-                dmax = <70>;
-                tzerowait = <80>;
-                vhigh = <90>;
-                vcoolthrs = <100>;
-                ihold = <1>;
-                irun = <2>;
-                iholddelay = <3>;
-            };
-        };
-    };
-
-
-compatible: "adi,tmc5041"
-
-include:
-  - name: spi-device.yaml
-  - name: adi,trinamic-gconf.yaml
-    property-allowlist:
-      - poscmp_enable
-      - shaft1
-      - shaft2
-      - test_mode
-      - lock_gconf
-
-properties:
-  "#address-cells":
-    default: 1
-    const: 1
-
-  "#size-cells":
-    default: 0
-    const: 0
-
-  clock-frequency:
-    type: int
-    required: true
-    description: |
-      The frequency of the clock signal provided to the TMC5041.
-      This is used for real world conversion.
-
-      Hint: µstep velocity v[Hz] µsteps / s v[Hz] = v[5041] * ( fCLK[Hz]/2 / 2^23 )
-            where v[5041] is the value written to the TMC5041.
-
-child-binding:
-  include:
-    - name: stepper-controller.yaml
-    - name: base.yaml
-      property-allowlist:
-        - reg
-    - name: adi,trinamic-ramp-generator.yaml
-      property-allowlist:
-        - vstart
-        - a1
-        - v1
-        - amax
-        - vmax
-        - dmax
-        - d1
-        - vstop
-        - tzerowait
-        - vhigh
-        - vcoolthrs
-        - ihold
-        - irun
-        - iholddelay
-    - name: adi,trinamic-stallguard.yaml
-      property-allowlist:
-        - activate-stallguard2
-        - stallguard2-threshold
-        - stallguard-threshold-velocity
-        - stallguard-velocity-check-interval-ms
diff --git a/dts/bindings/stepper/adi/adi,tmc50xx.yaml b/dts/bindings/stepper/adi/adi,tmc50xx.yaml
new file mode 100644
index 00000000000..eba9cd3f664
--- /dev/null
+++ b/dts/bindings/stepper/adi/adi,tmc50xx.yaml
@@ -0,0 +1,113 @@
+# SPDX-FileCopyrightText: Copyright (c) 2024 Carl Zeiss Meditec AG
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Analog Devices TMC50XX Stepper Motor Controller
+
+  Example:
+
+    &spi0 {
+        /* SPI bus options here, not shown */
+
+        /* Dual controller/driver for up to two 2-phase bipolar stepper motors */
+        tmc50xx: tmc50xx@0 {
+            compatible = "adi,tmc50xx";
+            reg = <0>;
+            spi-max-frequency = <DT_FREQ_M(8)>; /* Maximum SPI bus frequency */
+
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            poscmp-enable; test-mode; lock-gconf; /* ADI TMC Global configuration flags */
+            clock-frequency = <DT_FREQ_M(16)>; /* Internal/External Clock frequency */
+
+            motor: motor@0 {
+                status = "okay";
+                reg = <0>;
+
+                /* common stepper controller settings */
+                invert-direction;
+                micro-step-res = <256>;
+
+                /* ADI TMC stallguard settings specific to TMC50XX */
+                activate-stallguard2;
+                stallguard-velocity-check-interval-ms=<100>;
+                stallguard2-threshold=<9>;
+                stallguard-threshold-velocity=<500000>;
+
+                /* ADI TMC ramp generator as well as current settings */
+                vstart = <10>;
+                a1 = <20>;
+                v1 = <30>;
+                d1 = <40>;
+                vmax = <50>;
+                amax = <60>;
+                dmax = <70>;
+                tzerowait = <80>;
+                vhigh = <90>;
+                vcoolthrs = <100>;
+                ihold = <1>;
+                irun = <2>;
+                iholddelay = <3>;
+            };
+        };
+    };
+
+
+compatible: "adi,tmc50xx"
+
+include:
+  - name: spi-device.yaml
+  - name: adi,trinamic-gconf.yaml
+    property-allowlist:
+      - poscmp-enable
+      - test-mode
+      - lock-gconf
+
+properties:
+  "#address-cells":
+    default: 1
+    const: 1
+
+  "#size-cells":
+    default: 0
+    const: 0
+
+  clock-frequency:
+    type: int
+    required: true
+    description: |
+      The frequency of the clock signal provided to the TMC50XX.
+      This is used for real world conversion.
+
+      Hint: µstep velocity v[Hz] µsteps / s v[Hz] = v[50xx] * ( fCLK[Hz]/2 / 2^23 )
+            where v[50xx] is the value written to the TMC50XX.
+
+child-binding:
+  include:
+    - name: stepper-controller.yaml
+    - name: base.yaml
+      property-allowlist:
+        - reg
+    - name: adi,trinamic-ramp-generator.yaml
+      property-allowlist:
+        - vstart
+        - a1
+        - v1
+        - amax
+        - vmax
+        - dmax
+        - d1
+        - vstop
+        - tzerowait
+        - vhigh
+        - vcoolthrs
+        - ihold
+        - irun
+        - iholddelay
+    - name: adi,trinamic-stallguard.yaml
+      property-allowlist:
+        - activate-stallguard2
+        - stallguard2-threshold
+        - stallguard-threshold-velocity
+        - stallguard-velocity-check-interval-ms
diff --git a/dts/bindings/stepper/adi/adi,tmc51xx.yaml b/dts/bindings/stepper/adi/adi,tmc51xx.yaml
new file mode 100644
index 00000000000..caad1785123
--- /dev/null
+++ b/dts/bindings/stepper/adi/adi,tmc51xx.yaml
@@ -0,0 +1,108 @@
+# SPDX-FileCopyrightText: Copyright (c) 2025 Prevas A/S
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Analog Devices TMC51XX Stepper Motor Controller
+
+  Example:
+
+    &spi0 {
+        /* SPI bus options here, not shown */
+
+        /* Controller/driver for one 2-phase bipolar stepper motor */
+        tmc51xx: tmc51xx@0 {
+            compatible = "adi,tmc51xx";
+            reg = <0>;
+            spi-max-frequency = <DT_FREQ_M(8)>; /* Maximum SPI bus frequency */
+
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            en-pwm-mode; test-mode; /* ADI TMC Global configuration flags */
+            clock-frequency = <DT_FREQ_M(16)>; /* Internal/External Clock frequency */
+
+            /* common stepper controller settings */
+            invert-direction;
+            micro-step-res = <256>;
+
+            /* ADI TMC stallguard settings specific to TMC51XX */
+            activate-stallguard2;
+            stallguard-velocity-check-interval-ms=<100>;
+            stallguard2-threshold=<9>;
+            stallguard-threshold-velocity=<500000>;
+
+            /* ADI TMC ramp generator as well as current settings */
+            vstart = <10>;
+            a1 = <20>;
+            v1 = <30>;
+            d1 = <40>;
+            vmax = <50>;
+            amax = <60>;
+            dmax = <70>;
+            tzerowait = <80>;
+            thigh = <90>;
+            tcoolthrs = <100>;
+            tpwmthrs = <110>;
+            tpowerdown = <120>;
+            ihold = <1>;
+            irun = <2>;
+            iholddelay = <3>;
+        };
+    };
+
+
+compatible: "adi,tmc51xx"
+
+include:
+  - name: spi-device.yaml
+  - name: adi,trinamic-gconf.yaml
+    property-allowlist:
+      - en-pwm-mode
+      - test-mode
+  - name: stepper-controller.yaml
+  - name: base.yaml
+    property-allowlist:
+      - reg
+  - name: adi,trinamic-ramp-generator.yaml
+    property-allowlist:
+      - vstart
+      - a1
+      - v1
+      - amax
+      - vmax
+      - dmax
+      - d1
+      - vstop
+      - tzerowait
+      - thigh
+      - tcoolthrs
+      - tpwmthrs
+      - tpowerdown
+      - ihold
+      - irun
+      - iholddelay
+  - name: adi,trinamic-stallguard.yaml
+    property-allowlist:
+      - activate-stallguard2
+      - stallguard2-threshold
+      - stallguard-threshold-velocity
+      - stallguard-velocity-check-interval-ms
+
+properties:
+  "#address-cells":
+    default: 1
+    const: 1
+
+  "#size-cells":
+    default: 0
+    const: 0
+
+  clock-frequency:
+    type: int
+    required: true
+    description: |
+      The frequency of the clock signal provided to the TMC51XX.
+      This is used for real world conversion.
+
+      Hint: µstep velocity v[Hz] µsteps / s v[Hz] = v[51xx] * ( fCLK[Hz]/2 / 2^23 )
+            where v[51xx] is the value written to the TMC51XX.
diff --git a/dts/bindings/stepper/adi/adi,trinamic-gconf.yaml b/dts/bindings/stepper/adi/adi,trinamic-gconf.yaml
index 404476b8ee4..be25692bb0d 100644
--- a/dts/bindings/stepper/adi/adi,trinamic-gconf.yaml
+++ b/dts/bindings/stepper/adi/adi,trinamic-gconf.yaml
@@ -1,54 +1,55 @@
 # SPDX-FileCopyrightText: Copyright (c) 2024 Carl Zeiss Meditec AG
+# SPDX-FileCopyrightText: Copyright (c) 2025 Prevas A/S
 # SPDX-License-Identifier: Apache-2.0
 
 description: Global configuration flags for Trinamic stepper controller.
 
 properties:
-  en_spreadcycle:
+  en-spreadcycle:
     type: boolean
     description: |
       A high level on the pin SPREAD inverts this flag to switch between both chopper modes.
       0: StealthChop mode
       1: SpreadCycle mode enabled
 
-  i_scale_analog:
+  i-scale-analog:
     type: boolean
     description: |
       0: Use internal reference derived from 5VOUT
       1: Use voltage supplied to VREF as current reference
 
-  internal_rsense:
+  internal-rsense:
     type: boolean
     description: |
       0: Operation with external sense resistors
       1: Internal sense resistors. Use current supplied into VREF as reference for internal
          sense resistor. VREF pin internally is driven to GND in this mode.
 
-  index_otpw:
+  index-otpw:
     type: boolean
     description: |
       0: INDEX shows the first microstep position of sequencer
       1: INDEX output shows step pulses from internal pulse generator (toggle upon each step)
 
-  index_step:
+  index-step:
     type: boolean
     description: |
-      0: INDEX output as selected by index_otpw
+      0: INDEX output as selected by index-otpw
       1: INDEX pin shows the current step position of sequencer
 
-  pdn_disable:
+  pdn-disable:
     type: boolean
     description: |
       0: Normal operation
       1: Power down mode
 
-  mstep_reg_select:
+  mstep-reg-select:
     type: boolean
     description: |
       0: Microstep resolution selected by pins MS1, MS2
       1: Microstep resolution selected by MRES register
 
-  poscmp_enable:
+  poscmp-enable:
     type: boolean
     description: |
       Enable position compare feature
@@ -56,9 +57,9 @@ properties:
       1: Position compare pulse (PP) and interrupt output (INT) are available
 
       Attention – do not leave the outputs floating in tristate condition, provide an external
-      pull-up or set poscmp_enable=1
+      pull-up or set poscmp-enable=1
 
-  test_mode:
+  test-mode:
     type: boolean
     description: |
       Enable test mode
@@ -68,7 +69,15 @@ properties:
 
       Attention: Not for user, set to 0 for normal operation!
 
-  lock_gconf:
+  lock-gconf:
     type: boolean
     description: |
       1: GCONF is locked against further write access.
+
+  en-pwm-mode:
+    type: boolean
+    description: |
+      1: StealthChop voltage PWM mode enabled
+         (depending on velocity thresholds). Switch from
+         off to on state while in stand-still and at IHOLD=
+         nominal IRUN current, only.
diff --git a/dts/bindings/stepper/adi/adi,trinamic-ramp-generator.yaml b/dts/bindings/stepper/adi/adi,trinamic-ramp-generator.yaml
index 42d9b9e41fb..381ddf9a654 100644
--- a/dts/bindings/stepper/adi/adi,trinamic-ramp-generator.yaml
+++ b/dts/bindings/stepper/adi/adi,trinamic-ramp-generator.yaml
@@ -1,4 +1,5 @@
 # SPDX-FileCopyrightText: Copyright (c) 2024 Carl Zeiss Meditec AG
+# SPDX-FileCopyrightText: Copyright (c) 2025 Prevas A/S
 # SPDX-License-Identifier: Apache-2.0
 
 description: Ramp Generator Motion Control Register-Set for Trinamic stepper controller.
@@ -131,3 +132,63 @@ properties:
           (constant off time with slow decay, only).
         - If vhighfs is set, the motor operates in fullstep mode.
         - Voltage PWM mode StealthChop is switched off, if configured
+
+  tcoolthrs:
+    type: int
+    default: 0
+    description: |
+      This is the lower threshold velocity for switching on smart
+      energy CoolStep and StallGuard feature. (unsigned)
+      Set this parameter to disable CoolStep at low speeds, where it
+      cannot work reliably. The stop on stall function (enable with
+      sg_stop when using internal motion controller) and the stall
+      output signal become enabled when exceeding this velocity. In
+      non-DcStep mode, it becomes disabled again once the velocity
+      falls below this threshold.
+      TCOOLTHRS ≥ TSTEP ≥ THIGH:
+      - CoolStep is enabled, if configured
+      - StealthChop voltage PWM mode is disabled
+      TCOOLTHRS ≥ TSTEP
+      - Stop on stall is enabled, if configured
+      - Stall output signal (DIAG0/1) is enabled, if configured
+
+  thigh:
+    type: int
+    default: 0
+    description: |
+      This velocity setting allows velocity dependent switching into
+      a different chopper mode and fullstepping to maximize torque.
+      (unsigned)
+      The stall detection feature becomes switched off for 2-3
+      electrical periods whenever passing THIGH threshold to
+      compensate for the effect of switching modes.
+      TSTEP ≤ THIGH:
+      - CoolStep is disabled (motor runs with normal current
+      scale)
+      - StealthChop voltage PWM mode is disabled
+      - If vhighchm is set, the chopper switches to chm=1
+      with TFD=0 (constant off time with slow decay, only).
+      - If vhighfs is set, the motor operates in fullstep mode,
+      and the stall detection becomes switched over to
+      DcStep stall detection.
+
+  tpwmthrs:
+    type: int
+    default: 0
+    description: |
+      This is the upper velocity for StealthChop voltage PWM mode.
+      TSTEP ≥ TPWMTHRS
+      - StealthChop PWM mode is enabled, if configured
+      - DcStep is disabled
+
+  tpowerdown:
+    type: int
+    default: 10
+    description: |
+      TPOWERDOWN sets the delay time after stand still (stst) of the
+      motor to motor current power down. Time range is about 0 to
+      4 seconds.
+      Attention: A minimum setting of 2 is required to allow
+      automatic tuning of StealthChop PWM_OFS_AUTO.
+      Reset Default = 10
+      0…((2^8)-1) * 2^18 tCLK
diff --git a/dts/bindings/stepper/allegro/allegro,a4979.yml b/dts/bindings/stepper/allegro/allegro,a4979.yml
new file mode 100644
index 00000000000..c9e53b7a066
--- /dev/null
+++ b/dts/bindings/stepper/allegro/allegro,a4979.yml
@@ -0,0 +1,43 @@
+# SPDX-FileCopyrightText: Copyright (c) 2025 Carl Zeiss Meditec AG
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  Allegro A4979 microstepping stepper motor driver.
+  A4979 is a flexible microstepping motor driver with built-in translator for easy operation.
+  It is designed to operate bipolar stepper motors in full-, half-, quarter-, and sixteenth-step
+  modes.
+
+  Example:
+  a4979: a4979 {
+      status = "okay";
+      compatible = "allegro,a4979";
+      micro-step-res = <2>;
+      reset-gpios = <&gpiod 10 GPIO_ACTIVE_HIGH>;
+      dir-gpios = <&gpiod 14 GPIO_ACTIVE_HIGH>;
+      step-gpios = <&gpiod 15 GPIO_ACTIVE_HIGH>;
+      en-gpios = <&gpiod 11 GPIO_ACTIVE_HIGH>;
+      m0-gpios = <&gpiod 13 0>;
+      m1-gpios = <&gpiod 12 0>;
+      counter = <&counter5>;
+  };
+
+compatible: "allegro,a4979"
+
+include:
+  - name: stepper-controller.yaml
+
+properties:
+  m0-gpios:
+    required: true
+    type: phandle-array
+    description: Microstep configuration pin 0.
+
+  m1-gpios:
+    required: true
+    type: phandle-array
+    description: Microstep configuration pin 1.
+
+  reset-gpios:
+    type: phandle-array
+    required: true
+    description: Reset pin
diff --git a/dts/bindings/stepper/ti/ti,drv8424.yaml b/dts/bindings/stepper/ti/ti,drv8424.yaml
deleted file mode 100644
index e02d85e5026..00000000000
--- a/dts/bindings/stepper/ti/ti,drv8424.yaml
+++ /dev/null
@@ -1,56 +0,0 @@
-# SPDX-FileCopyrightText: Copyright (c) 2024 Navimatix GmbH
-# SPDX-License-Identifier: Apache-2.0
-
-description: |
-  TI DRV8424 stepper motor driver.
-  SAFETY:
-  The counter needs to support both set_top_value functionalities: Setting a new top value and
-  attaching an ISR to the turnaround.
-  SAFETY:
-  The step gpio pin needs to be connected directly to the SOC GPIO controller, connecting the
-  pin to a controller connected via a bus such as i2c or others will lead to undefined behaviour.
-
-  Example:
-  drv8424: drv8424 {
-    status = "okay";
-    compatible = "ti,drv8424";
-
-    dir-gpios = <&arduino_header 18 0>;
-    step-gpios = <&arduino_header 19 0>;
-    sleep-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>;
-    en-gpios  = <&arduino_header 14 0>;
-    m0-gpios = <&mikroe_stepper_gpios 0 0>;
-    m1-gpios = <&mikroe_stepper_gpios 1 0>;
-    counter = <&counter2>;
-  };
-
-
-compatible: "ti,drv8424"
-
-include:
-  - name: stepper-controller.yaml
-    property-allowlist:
-      - micro-step-res
-      - step-gpios
-      - dir-gpios
-      - en-gpios
-      - counter
-
-properties:
-  fault-gpios:
-    type: phandle-array
-    description: Fault pin.
-
-  sleep-gpios:
-    type: phandle-array
-    description: Sleep pin (active low).
-
-  m0-gpios:
-    required: true
-    type: phandle-array
-    description: Microstep configuration pin 0.
-
-  m1-gpios:
-    required: true
-    type: phandle-array
-    description: Microstep configuration pin 1.
diff --git a/dts/bindings/stepper/ti/ti,drv84xx.yaml b/dts/bindings/stepper/ti/ti,drv84xx.yaml
new file mode 100644
index 00000000000..3b891d1d17c
--- /dev/null
+++ b/dts/bindings/stepper/ti/ti,drv84xx.yaml
@@ -0,0 +1,50 @@
+# SPDX-FileCopyrightText: Copyright (c) 2024 Navimatix GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  TI DRV84XX stepper motor driver.
+  Compatible with drv8424, drv8425, drv8426, drv8434 and drv8436.
+  SAFETY:
+  The counter needs to support both set_top_value functionalities: Setting a new top value and
+  attaching an ISR to the turnaround.
+  SAFETY:
+  The step gpio pin needs to be connected directly to the SOC GPIO controller, connecting the
+  pin to a controller connected via a bus such as i2c or others will lead to undefined behaviour.
+
+  Example:
+  drv8424: drv8424 {
+    status = "okay";
+    compatible = "ti,drv84xx";
+
+    dir-gpios = <&arduino_header 18 0>;
+    step-gpios = <&arduino_header 19 0>;
+    fault-gpios = <&arduino_header 16 0>;
+    sleep-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>;
+    en-gpios  = <&arduino_header 14 0>;
+    m0-gpios = <&mikroe_stepper_gpios 0 0>;
+    m1-gpios = <&mikroe_stepper_gpios 1 0>;
+    counter = <&counter2>;
+  };
+
+
+compatible: "ti,drv84xx"
+
+include:
+  - name: stepper-controller.yaml
+
+properties:
+  fault-gpios:
+    type: phandle-array
+    description: Fault pin.
+
+  sleep-gpios:
+    type: phandle-array
+    description: Sleep pin (active low).
+
+  m0-gpios:
+    type: phandle-array
+    description: Microstep configuration pin 0.
+
+  m1-gpios:
+    type: phandle-array
+    description: Microstep configuration pin 1.
diff --git a/dts/bindings/tach/ene,kb1200-tach.yaml b/dts/bindings/tach/ene,kb1200-tach.yaml
index 4f89d9a882d..d263d4659d7 100644
--- a/dts/bindings/tach/ene,kb1200-tach.yaml
+++ b/dts/bindings/tach/ene,kb1200-tach.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 ENE Technology Inc.
 # SPDX-License-Identifier: Apache-2.0
 
-description: ENE, KB1200-Tachometer node
+description: ENE KB1200 Tachometer
 
 compatible: "ene,kb1200-tach"
 
diff --git a/dts/bindings/tach/ite,it51xxx-tach.yaml b/dts/bindings/tach/ite,it51xxx-tach.yaml
new file mode 100644
index 00000000000..c46a634d23a
--- /dev/null
+++ b/dts/bindings/tach/ite,it51xxx-tach.yaml
@@ -0,0 +1,31 @@
+# Copyright (c) 2025 ITE Technology Corporation.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE, it51xxx Tachometer node
+
+compatible: "ite,it51xxx-tach"
+
+include: [tach.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  input-pin:
+    type: int
+    required: true
+    enum:
+      - 0
+      - 1
+    description: 0 = TACH_INPUT_PIN_A, 1 = TACH_INPUT_PIN_B
+
+  pulses-per-round:
+    type: int
+    required: true
+    description: number of pulses per round of tachometer's input
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
diff --git a/dts/bindings/tach/ite,it8xxx2-tach.yaml b/dts/bindings/tach/ite,it8xxx2-tach.yaml
index d00d4eca3c4..2558a66d1eb 100644
--- a/dts/bindings/tach/ite,it8xxx2-tach.yaml
+++ b/dts/bindings/tach/ite,it8xxx2-tach.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021 ITE Technology Corporation.
 # SPDX-License-Identifier: Apache-2.0
 
-description: ITE, it8xxx2 Tachometer node
+description: ITE IT8xxx2 Tachometer
 
 compatible: "ite,it8xxx2-tach"
 
diff --git a/dts/bindings/tach/nuvoton,npcx-tach.yaml b/dts/bindings/tach/nuvoton,npcx-tach.yaml
index 8a2c35ae004..48def30def0 100644
--- a/dts/bindings/tach/nuvoton,npcx-tach.yaml
+++ b/dts/bindings/tach/nuvoton,npcx-tach.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021 Nuvoton Technology Corporation.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Nuvoton, NPCX-Tachometer node
+description: Nuvoton NPCX Tachometer
 
 compatible: "nuvoton,npcx-tach"
 
diff --git a/dts/bindings/tach/realtek,rts5912-tach.yaml b/dts/bindings/tach/realtek,rts5912-tach.yaml
new file mode 100644
index 00000000000..1d72ce8bb0b
--- /dev/null
+++ b/dts/bindings/tach/realtek,rts5912-tach.yaml
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2025 Realtek Semiconductor Corporation, SIBG-SD7
+#
+
+description: Realtek rts5912 tachometer controller
+
+compatible: "realtek,rts5912-tach"
+
+include: [tach.yaml, pinctrl-device.yaml, sensor-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  pinctrl-0:
+    required: true
+
+  pinctrl-names:
+    required: true
+
+  pulses-per-round:
+    type: int
+    required: true
+    description: number of pulses per round of tachometer's input
diff --git a/dts/bindings/tcpc/richtek,rt1715.yaml b/dts/bindings/tcpc/richtek,rt1715.yaml
new file mode 100644
index 00000000000..de106484cb3
--- /dev/null
+++ b/dts/bindings/tcpc/richtek,rt1715.yaml
@@ -0,0 +1,74 @@
+# Copyright (c) 2024 Jianxiong Gu <jianxiong.gu@outlook.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+    The Richtek RT1715 is a Type-C Port Controller (TCPC) chip.
+
+    Example:
+
+    ports {
+        #address-cells = <1>;
+        #size-cells = <0>;
+        port0: usbc-port@0 {
+          compatible = "usb-c-connector";
+          reg = <0>;
+          tcpc = <&rt1715_tcpc0>;
+          vbus = <&vbus0>;
+          power-role = "sink";
+          sink-pdos = <PDO_FIXED(5000, 100, 0)>;
+        };
+    };
+
+    vbus0: vbus {
+      compatible = "zephyr,usb-c-vbus-adc";
+      status = "okay";
+      io-channels = <&adc 2>;
+      output-ohms = <10000>;
+      full-ohms = <(100000 + 10000)>;
+    };
+
+    i2c1 {
+      status = "okay";
+      clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+      rt1715_tcpc0: rt1715@4e {
+        compatible = "richtek,rt1715";
+        reg = <0x4e>;
+        irq-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>;
+        status = "okay";
+      };
+    };
+
+compatible: "richtek,rt1715"
+
+include: [base.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  irq-gpios:
+    type: phandle-array
+    required: true
+    description: |
+      Interrupt GPIO pin connected from the chip.
+
+  transmit-retries:
+    type: int
+    default: 2
+    description: |
+      Maximum number of packet retransmissions done by TCPC. Valid values are <0, 3>.
+      This value is used to fill the Retry Counter part of the TCPCI Transmit register.
+
+  vconn-ctrl-gpios:
+    type: phandle-array
+    description: |
+      GPIO pin for VCONN control. RT1715 does not have built-in VCONN power supply. If the
+      state of the VCONN power supply need to be toggled, this pin and a switchable power
+      supply are required.
+
+  vconn-disc-gpios:
+    type: phandle-array
+    description: |
+      GPIO pin for VCONN discharge control. RT1715 does not have VCONN discharge capability.
+      If VCONN discharge is not needed, this pin does not need to be defined in the device
+      tree. Otherwise, this pin and a discharge path are required.
diff --git a/dts/bindings/tcpc/st,stm32-ucpd.yaml b/dts/bindings/tcpc/st,stm32-ucpd.yaml
index 8d49b78a31a..93b72faf0a9 100644
--- a/dts/bindings/tcpc/st,stm32-ucpd.yaml
+++ b/dts/bindings/tcpc/st,stm32-ucpd.yaml
@@ -2,8 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    ST STM32 family USB Type-C / Power Delivery. The default values were
-    taken from the LL_UCPD_StructInit function defined in the HAL.
+    STM32 USB Type-C / Power Delivery.
+
+    The default values were taken from the LL_UCPD_StructInit function defined in the HAL.
 
 compatible: "st,stm32-ucpd"
 
diff --git a/dts/bindings/timer/andestech,machine-timer.yaml b/dts/bindings/timer/andestech,machine-timer.yaml
deleted file mode 100644
index 9a1c4e891d3..00000000000
--- a/dts/bindings/timer/andestech,machine-timer.yaml
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright (c) 2022 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-description: |
-  Andes Machine Timer
-
-  The Andes machine timer provides RISC-V privileged mtime and mtimecmp
-  registers.
-
-compatible: "andestech,machine-timer"
-
-include: base.yaml
-
-properties:
-  reg:
-    required: true
-
-  interrupts-extended:
-    required: true
diff --git a/dts/bindings/timer/espressif,esp32-systimer.yaml b/dts/bindings/timer/espressif,esp32-systimer.yaml
index bc08df7e39c..f9289886b4c 100644
--- a/dts/bindings/timer/espressif,esp32-systimer.yaml
+++ b/dts/bindings/timer/espressif,esp32-systimer.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Espressif ESP32 Systimer peripheral
+description: ESP32 System Timer
 
 compatible: "espressif,esp32-systimer"
 
diff --git a/dts/bindings/timer/ite,it51xxx-timer.yaml b/dts/bindings/timer/ite,it51xxx-timer.yaml
new file mode 100644
index 00000000000..825b3332b76
--- /dev/null
+++ b/dts/bindings/timer/ite,it51xxx-timer.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE it51xxx external timer
+
+compatible: "ite,it51xxx-timer"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
diff --git a/dts/bindings/timer/lowrisc,machine-timer.yaml b/dts/bindings/timer/lowrisc,machine-timer.yaml
deleted file mode 100644
index 01721e22ed4..00000000000
--- a/dts/bindings/timer/lowrisc,machine-timer.yaml
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright (c) 2023 Rivos Inc.
-# SPDX-License-Identifier: Apache-2.0
-
-description: |
-  OpenTitan Machine Timer
-
-  The OpenTitan machine timer provides RISC-V privileged mtime and mtimecmp
-  registers.
-
-compatible: "lowrisc,machine-timer"
-
-include: base.yaml
-
-properties:
-  reg:
-    required: true
-
-  interrupts:
-    required: true
diff --git a/dts/bindings/timer/microchip,xec-rtos-timer.yaml b/dts/bindings/timer/microchip,xec-rtos-timer.yaml
index 7099bca798a..509634082dd 100644
--- a/dts/bindings/timer/microchip,xec-rtos-timer.yaml
+++ b/dts/bindings/timer/microchip,xec-rtos-timer.yaml
@@ -18,3 +18,9 @@ properties:
     type: array
     required: true
     description: Array of GIRQ numbers [8:26] and bit positions [0:31].
+
+  clock-frequency:
+    type: int
+    required: true
+    const: 32768
+    description: RTOS timer runs at fixed 32 KHz.
diff --git a/dts/bindings/timer/neorv32-machine-timer.yaml b/dts/bindings/timer/neorv32-machine-timer.yaml
deleted file mode 100644
index 4c72679f6a5..00000000000
--- a/dts/bindings/timer/neorv32-machine-timer.yaml
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright (c) 2022 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-description: |
-  NEORV32 Machine Timer
-
-  The NEORV32 machine timer provides RISC-V privileged mtime and mtimecmp
-  registers.
-
-compatible: "neorv32-machine-timer"
-
-include: base.yaml
-
-properties:
-  reg:
-    required: true
-
-  interrupts:
-    required: true
diff --git a/dts/bindings/timer/niosv-machine-timer.yaml b/dts/bindings/timer/niosv-machine-timer.yaml
deleted file mode 100644
index 4b77d131e6e..00000000000
--- a/dts/bindings/timer/niosv-machine-timer.yaml
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright (C) 2023, Intel Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-description: |
-  NIOSV Machine Timer
-
-  The NIOSV machine timer provides RISC-V privileged mtime and mtimecmp
-  registers.
-
-compatible: "niosv-machine-timer"
-
-include: base.yaml
-
-properties:
-  reg:
-    required: true
-
-  interrupts:
-    required: true
diff --git a/dts/bindings/timer/nordic,nrf-grtc.yaml b/dts/bindings/timer/nordic,nrf-grtc.yaml
index 4b041d0adc1..edff2423b11 100644
--- a/dts/bindings/timer/nordic,nrf-grtc.yaml
+++ b/dts/bindings/timer/nordic,nrf-grtc.yaml
@@ -12,7 +12,7 @@ description: |
           pinctrl-0 = <&grtc_default>;
           pinctrl-1 = <&grtc_sleep>;
           pinctrl-names = "default", "sleep";
-          clkout-fast-frequency = <8000000>;
+          clkout-fast-frequency-hz = <8000000>;
           clkout-32k;
           /* In case of nRF54H20 devices: */
           nordic,clockpin-enable = <NRF_FUN_GRTC_CLKOUT_FAST>;
@@ -30,7 +30,7 @@ properties:
   reg:
     required: true
 
-  clkout-fast-frequency:
+  clkout-fast-frequency-hz:
     type: int
     description: Fast output clock frequency.
 
diff --git a/dts/bindings/timer/nuclei,systimer.yaml b/dts/bindings/timer/nuclei,systimer.yaml
index 5c8f319a7c5..265b0716b40 100644
--- a/dts/bindings/timer/nuclei,systimer.yaml
+++ b/dts/bindings/timer/nuclei,systimer.yaml
@@ -9,15 +9,9 @@ description: |
 
 compatible: "nuclei,systimer"
 
-include: base.yaml
+include: "riscv,machine-timer.yaml"
 
 properties:
-  reg:
-    required: true
-
-  interrupts:
-    required: true
-
   clk-divider:
     type: int
     description: |
diff --git a/dts/bindings/timer/nuvoton,npcx-itim-timer.yaml b/dts/bindings/timer/nuvoton,npcx-itim-timer.yaml
index 4e538507727..c12301c9bf3 100644
--- a/dts/bindings/timer/nuvoton,npcx-itim-timer.yaml
+++ b/dts/bindings/timer/nuvoton,npcx-itim-timer.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021 Nuvoton Technology Corporation.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Nuvoton, NPCX Internal Timer (ITIM) node
+description: Nuvoton NPCX Internal Timer (ITIM)
 
 compatible: "nuvoton,npcx-itim-timer"
 
diff --git a/dts/bindings/timer/renesas,ra-ulpt-timer.yaml b/dts/bindings/timer/renesas,ra-ulpt-timer.yaml
new file mode 100644
index 00000000000..7c01129b875
--- /dev/null
+++ b/dts/bindings/timer/renesas,ra-ulpt-timer.yaml
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA ULPT TIMER
+
+compatible: "renesas,ra-ulpt-timer"
+
+include: base.yaml
diff --git a/dts/bindings/timer/renesas,rz-gpt.yaml b/dts/bindings/timer/renesas,rz-gpt.yaml
new file mode 100644
index 00000000000..e70cda20361
--- /dev/null
+++ b/dts/bindings/timer/renesas,rz-gpt.yaml
@@ -0,0 +1,36 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RZ GPT
+
+compatible: "renesas,rz-gpt"
+
+include: [base.yaml]
+
+properties:
+  prescaler:
+    type: int
+    required: true
+    enum:
+      - 1
+      - 2
+      - 4
+      - 8
+      - 16
+      - 32
+      - 64
+      - 128
+      - 256
+      - 512
+      - 1024
+    description: Input clock prescaler. For RZ/G3S, only 1, 4, 16, 64, 256, 1024 are supported.
+
+  channel:
+    type: int
+    required: true
+
+  interrupts:
+    required: true
+
+  interrupt-names:
+    required: true
diff --git a/dts/bindings/timer/renesas,rz-gtm.yaml b/dts/bindings/timer/renesas,rz-gtm.yaml
new file mode 100644
index 00000000000..8d193184ff3
--- /dev/null
+++ b/dts/bindings/timer/renesas,rz-gtm.yaml
@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RZ GTM Timer
+
+compatible: "renesas,rz-gtm"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  channel:
+    type: int
+    required: true
+
+  interrupts:
+    required: true
diff --git a/dts/bindings/timer/renesas,rza2m-ostm.yaml b/dts/bindings/timer/renesas,rza2m-ostm.yaml
new file mode 100644
index 00000000000..260a18e3916
--- /dev/null
+++ b/dts/bindings/timer/renesas,rza2m-ostm.yaml
@@ -0,0 +1,15 @@
+description: Renesas RZ/A2M OS timer
+
+compatible: "renesas,rza2m-ostm"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  clocks:
+    required: true
+
+  interrupts:
+    required: true
diff --git a/dts/bindings/timer/riscv,machine-timer.yaml b/dts/bindings/timer/riscv,machine-timer.yaml
new file mode 100644
index 00000000000..e0acc601bf1
--- /dev/null
+++ b/dts/bindings/timer/riscv,machine-timer.yaml
@@ -0,0 +1,14 @@
+# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+# SPDX-License-Identifier: Apache-2.0
+
+description: RISC-V Machine Timer.
+
+compatible: "riscv,machine-timer"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+  interrupts-extended:
+    required: true
diff --git a/dts/bindings/timer/silabs,gecko-timer.yaml b/dts/bindings/timer/silabs,gecko-timer.yaml
index 7953ae2bf1c..1868be606c0 100644
--- a/dts/bindings/timer/silabs,gecko-timer.yaml
+++ b/dts/bindings/timer/silabs,gecko-timer.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021, Sun Amar
 # SPDX-License-Identifier: Apache-2.0
 
-description: Silabs gecko timer node
+description: Silabs Gecko timer
 
 compatible: "silabs,gecko-timer"
 
diff --git a/dts/bindings/timer/st,stm32-lptim.yaml b/dts/bindings/timer/st,stm32-lptim.yaml
index 159d8bdff00..31e4ea0e8ef 100644
--- a/dts/bindings/timer/st,stm32-lptim.yaml
+++ b/dts/bindings/timer/st,stm32-lptim.yaml
@@ -2,7 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  STM32 lptim : low power timer
+  STM32 low-power timer (LPTIM).
+
   The lptim node to be used for counting ticks during lowpower modes
   must be named stm32_lp_tick_source in the DTS, as follows:
   stm32_lp_tick_source: &lptim1 {
diff --git a/dts/bindings/timer/starfive,jh7100-clint.yaml b/dts/bindings/timer/starfive,jh7100-clint.yaml
deleted file mode 100644
index 0120e899308..00000000000
--- a/dts/bindings/timer/starfive,jh7100-clint.yaml
+++ /dev/null
@@ -1,8 +0,0 @@
-# Copyright (c) 2022 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-description: Starfive JH7100 RISC-V Core-Local Interruptor.
-
-compatible: "starfive,jh7100-clint"
-
-include: sifive,clint0.yaml
diff --git a/dts/bindings/timer/sy1xx,sys-timer.yaml b/dts/bindings/timer/sy1xx,sys-timer.yaml
index b87fbd77564..58b6e501b6b 100644
--- a/dts/bindings/timer/sy1xx,sys-timer.yaml
+++ b/dts/bindings/timer/sy1xx,sys-timer.yaml
@@ -14,6 +14,6 @@ properties:
   interrupts:
     required: true
 
-  ticks_us:
+  ticks-us:
     type: int
     required: true
diff --git a/dts/bindings/timer/telink,machine-timer.yaml b/dts/bindings/timer/telink,machine-timer.yaml
deleted file mode 100644
index 0ee37bd6de7..00000000000
--- a/dts/bindings/timer/telink,machine-timer.yaml
+++ /dev/null
@@ -1,19 +0,0 @@
-# Copyright (c) 2022 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-description: |
-  Telink Machine Timer
-
-  The Telink machine timer provides RISC-V privileged mtime and mtimecmp
-  registers.
-
-compatible: "telink,machine-timer"
-
-include: base.yaml
-
-properties:
-  reg:
-    required: true
-
-  interrupts:
-    required: true
diff --git a/dts/bindings/timer/ti,cc13xx-cc26xx-timer.yaml b/dts/bindings/timer/ti,cc13xx-cc26xx-timer.yaml
index 33712c4364a..fff487807bb 100644
--- a/dts/bindings/timer/ti,cc13xx-cc26xx-timer.yaml
+++ b/dts/bindings/timer/ti,cc13xx-cc26xx-timer.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2023 Zephyr Project
 # SPDX-License-Identifier: Apache-2.0
 
-description: TI SimpleLink CC13xx/CC26xx Timer Node
+description: TI SimpleLink CC13xx/CC26xx Timer
 
 compatible: "ti,cc13xx-cc26xx-timer"
 
diff --git a/dts/bindings/timer/ti,cc23x0-timer.yaml b/dts/bindings/timer/ti,cc23x0-timer.yaml
new file mode 100644
index 00000000000..e43acb09cf5
--- /dev/null
+++ b/dts/bindings/timer/ti,cc23x0-timer.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Baylibre SAS
+# SPDX-License-Identifier: Apache-2.0
+
+description: TI SimpleLink CC23x0 Timer
+
+compatible: "ti,cc23x0-systim-timer"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
diff --git a/dts/bindings/usb/adi,max32-usbhs.yaml b/dts/bindings/usb/adi,max32-usbhs.yaml
new file mode 100644
index 00000000000..74de7cd204a
--- /dev/null
+++ b/dts/bindings/usb/adi,max32-usbhs.yaml
@@ -0,0 +1,18 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ADI MAX32 USBHS
+
+compatible: "adi,max32-usbhs"
+
+include: [usb-ep.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  clocks:
+    required: true
+
+  interrupts:
+    required: true
diff --git a/dts/bindings/usb/ambiq,usb.yaml b/dts/bindings/usb/ambiq,usb.yaml
index f460e7257cf..ecff0bf6fb9 100644
--- a/dts/bindings/usb/ambiq,usb.yaml
+++ b/dts/bindings/usb/ambiq,usb.yaml
@@ -5,7 +5,7 @@ description: Ambiq USB
 
 compatible: "ambiq,usb"
 
-include: [usb-ep.yaml, pinctrl-device.yaml, ambiq-pwrcfg.yaml]
+include: [usb-ep.yaml, pinctrl-device.yaml]
 
 properties:
   reg:
@@ -14,9 +14,6 @@ properties:
   interrupts:
     required: true
 
-  ambiq,pwrcfg:
-    required: true
-
   vddusb33-gpios:
     type: phandle-array
     description: |
diff --git a/dts/bindings/usb/nxp,ehci.yaml b/dts/bindings/usb/nxp,ehci.yaml
index 8f1569e2060..de4c8f25cba 100644
--- a/dts/bindings/usb/nxp,ehci.yaml
+++ b/dts/bindings/usb/nxp,ehci.yaml
@@ -8,5 +8,5 @@ compatible: nxp,ehci
 include: "nxp,mcux-usbd.yaml"
 
 properties:
-  phy_handle:
+  phy-handle:
     type: phandle
diff --git a/dts/bindings/usb/nxp,lpcip3511.yaml b/dts/bindings/usb/nxp,lpcip3511.yaml
index 3c799e49390..b8681540d96 100644
--- a/dts/bindings/usb/nxp,lpcip3511.yaml
+++ b/dts/bindings/usb/nxp,lpcip3511.yaml
@@ -8,5 +8,5 @@ compatible: nxp,lpcip3511
 include: "nxp,mcux-usbd.yaml"
 
 properties:
-  phy_handle:
+  phy-handle:
     type: phandle
diff --git a/dts/bindings/usb/raspberrypi,pico-usbd.yaml b/dts/bindings/usb/raspberrypi,pico-usbd.yaml
index 26b763e9a7a..39caa0dddd9 100644
--- a/dts/bindings/usb/raspberrypi,pico-usbd.yaml
+++ b/dts/bindings/usb/raspberrypi,pico-usbd.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  RaspberryPi Pico USB Device Controller.
+  Raspberry Pi Pico USB Device Controller.
 
   Example of enabling the controller with vbus detection:
 
diff --git a/dts/bindings/usb/renesas/renesas,ra-usb.yaml b/dts/bindings/usb/renesas/renesas,ra-usb.yaml
deleted file mode 100644
index ec31e250eb3..00000000000
--- a/dts/bindings/usb/renesas/renesas,ra-usb.yaml
+++ /dev/null
@@ -1,16 +0,0 @@
-# Copyright (c) 2024 Renesas Electronics Corporation
-# SPDX-License-Identifier: Apache-2.0
-
-description: Renesas RA USB controller
-
-compatible: "renesas,ra-usb"
-
-include: [pinctrl-device.yaml, usb-ep.yaml]
-
-properties:
-  reg:
-    required: true
-
-  phys:
-    type: phandle
-    description: PHY provider specifier
diff --git a/dts/bindings/usb/renesas/renesas,ra-usbfs.yaml b/dts/bindings/usb/renesas/renesas,ra-usbfs.yaml
new file mode 100644
index 00000000000..58ec9aa344e
--- /dev/null
+++ b/dts/bindings/usb/renesas/renesas,ra-usbfs.yaml
@@ -0,0 +1,34 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA USB full-speed controller
+
+compatible: "renesas,ra-usbfs"
+
+include: [pinctrl-device.yaml, usb-ep.yaml]
+
+properties:
+  phys-clock:
+    type: phandles
+    required: true
+    description: USBFS physical clock.
+
+  interrupts:
+    required: true
+    description: |
+      IRQ number and priority to use for USBFS.
+
+  interrupt-names:
+    required: true
+    enum:
+      - "usbfs-i"
+      - "usbfs-r"
+    description: |
+      Interrupts must be given corresponding names so that the shim driver can recognize them.
+
+  reg:
+    required: true
+
+  phys:
+    type: phandle
+    description: PHY provider specifier
diff --git a/dts/bindings/usb/renesas/renesas,ra-usbhs.yaml b/dts/bindings/usb/renesas/renesas,ra-usbhs.yaml
new file mode 100644
index 00000000000..9428c2413bc
--- /dev/null
+++ b/dts/bindings/usb/renesas/renesas,ra-usbhs.yaml
@@ -0,0 +1,33 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA USB high-speed controller
+
+compatible: "renesas,ra-usbhs"
+
+include: [pinctrl-device.yaml, usb-ep.yaml]
+
+properties:
+  phys-clock:
+    type: phandles
+    description: |
+      USBHS physical clocks. Should be provided in case internal clock source is set in phys node.
+
+  interrupts:
+    required: true
+    description: |
+      IRQ number and priority to use for USBHS.
+
+  interrupt-names:
+    required: true
+    enum:
+      - "usbhs-ir"
+    description: |
+      Interrupts must be given corresponding names so that the shim driver can recognize them.
+
+  reg:
+    required: true
+
+  phys:
+    type: phandle
+    description: PHY provider specifier
diff --git a/dts/bindings/usb/snps,designware-usb.yaml b/dts/bindings/usb/snps,designware-usb.yaml
index 993e1f738e3..84f4deadd27 100644
--- a/dts/bindings/usb/snps,designware-usb.yaml
+++ b/dts/bindings/usb/snps,designware-usb.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2019 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-description: Synopsys Designware USB Controller node
+description: Synopsys Designware USB controller
 
 compatible: "snps,designware-usb"
 
diff --git a/dts/bindings/usb/st,stm32-otghs-common.yaml b/dts/bindings/usb/st,stm32-otghs-common.yaml
new file mode 100644
index 00000000000..d1aab33d93a
--- /dev/null
+++ b/dts/bindings/usb/st,stm32-otghs-common.yaml
@@ -0,0 +1,27 @@
+# Copyright (c) 2025, STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+# Common fields for STM32 OTGHS controller
+
+include: [usb-ep.yaml, pinctrl-device.yaml]
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  ram-size:
+    type: int
+    required: true
+    description: |
+      Size of USB dedicated RAM. STM32 SOC's reference
+      manual defines a shared FIFO size.
+
+  phys:
+    type: phandle
+    description: PHY provider specifier
+
+  clocks:
+    required: true
diff --git a/dts/bindings/usb/st,stm32-otghs.yaml b/dts/bindings/usb/st,stm32-otghs.yaml
index dfd40a9ed3d..58f4f5b5523 100644
--- a/dts/bindings/usb/st,stm32-otghs.yaml
+++ b/dts/bindings/usb/st,stm32-otghs.yaml
@@ -1,35 +1,16 @@
 # Copyright (c) 2017, I-SENSE group of ICCS
+# Copyright (c) 2025, STMicroelectronics
 # SPDX-License-Identifier: Apache-2.0
 
 description: STM32 OTGHS controller
 
 compatible: "st,stm32-otghs"
 
-include: [usb-ep.yaml, pinctrl-device.yaml]
+include: st,stm32-otghs-common.yaml
 
 properties:
-  reg:
-    required: true
-
-  interrupts:
-    required: true
-
   pinctrl-0:
     required: true
 
   pinctrl-names:
     required: true
-
-  ram-size:
-    type: int
-    required: true
-    description: |
-      Size of USB dedicated RAM. STM32 SOC's reference
-      manual defines a shared FIFO size.
-
-  phys:
-    type: phandle
-    description: PHY provider specifier
-
-  clocks:
-    required: true
diff --git a/dts/bindings/usb/st,stm32f4-fsotg.yaml b/dts/bindings/usb/st,stm32f4-fsotg.yaml
index 7b681a362c8..2d657f70099 100644
--- a/dts/bindings/usb/st,stm32f4-fsotg.yaml
+++ b/dts/bindings/usb/st,stm32f4-fsotg.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2023 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 #
-description: STM32F4 SoC series OTG_FS DWC2 compatible controller
+description: STM32F4 OTG_FS DWC2 compatible controller.
 
 compatible: "st,stm32f4-fsotg"
 
diff --git a/dts/bindings/usb/st,stm32n6-otghs.yaml b/dts/bindings/usb/st,stm32n6-otghs.yaml
new file mode 100644
index 00000000000..b7c73fb7287
--- /dev/null
+++ b/dts/bindings/usb/st,stm32n6-otghs.yaml
@@ -0,0 +1,13 @@
+# Copyright (c) 2025, STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+description: |
+  STM32N6 OTGHS controller
+
+  In the STM32N6 series, the `pinctrl-0` and `pinctrl-names` properties are not required
+  for the USB OTG HS peripheral configuration. This is because the pin multiplexing
+  for the USB OTG HS peripheral are handled automatically by the hardware.
+
+compatible: "st,stm32n6-otghs"
+
+include: st,stm32-otghs-common.yaml
diff --git a/dts/bindings/usb/zephyr,midi2-device.yaml b/dts/bindings/usb/zephyr,midi2-device.yaml
new file mode 100644
index 00000000000..851916e7e87
--- /dev/null
+++ b/dts/bindings/usb/zephyr,midi2-device.yaml
@@ -0,0 +1,51 @@
+# Copyright (c) 2024 Titouan Christophe
+# SPDX-License-Identifier: Apache-2.0
+
+description: MIDI2 device
+
+compatible: "zephyr,midi2-device"
+
+properties:
+  "#address-cells":
+    type: int
+    const: 1
+
+  "#size-cells":
+    type: int
+    const: 1
+
+child-binding:
+  description: |
+    MIDI2 Group terminal block.
+    This represent a set of contiguous MIDI2 groups through which the
+    device exchange Universal MIDI Packets with the host.
+
+  properties:
+    reg:
+      type: array
+      required: true
+      description: |
+        First MIDI2 Group number (address) and number of Group Terminals (size)
+        in this MIDI2 Group Terminal Block.
+        The MIDI2 Groups 1 to 16 corresponds to address 0x0 to 0xf. There are
+        at most 16 addressable groups (of 16 chans each) per MIDI2 interface.
+
+    protocol:
+      type: string
+      enum:
+      - "use-midi-ci"
+      - "midi1-up-to-64b"
+      - "midi1-up-to-128b"
+      - "midi2"
+      description: |
+        Default MIDI protocol of the Group Terminals in this Block.
+
+    terminal-type:
+      type: string
+      default: "bidirectional"
+      enum:
+      - "bidirectional"
+      - "input-only"
+      - "output-only"
+      description: |
+        Type (data direction) of Group Terminals in this Block.
diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt
index 1d06e4b8201..70c43fdc8b7 100644
--- a/dts/bindings/vendor-prefixes.txt
+++ b/dts/bindings/vendor-prefixes.txt
@@ -57,6 +57,7 @@ ams	AMS AG
 amstaos	AMS-Taos Inc.
 analogix	Analogix Semiconductor, Inc.
 andestech	Andes Technology Corporation
+antmicro	Antmicro
 anvo	Anvo-Systems Dresden GmbH
 aosong	Guangzhou Aosong Electronic Co., Ltd.
 ap	Angst+Pfister
@@ -100,6 +101,7 @@ bbc	BBC
 bcdevices	Blue Clover Devices
 beacon	Compass Electronics Group, LLC
 beagle	BeagleBoard.org Foundation
+bflb	Bouffalo Lab (Nanjing) Co., Ltd.
 bhf	Beckhoff Automation GmbH & Co. KG
 bitmain	Bitmain Technologies
 blues	Blues Wireless
@@ -302,6 +304,7 @@ hynitron	Hynitron
 hyundai	Hyundai Technology
 hzgrow	Hangzhou Grow Technology Co., Ltd.
 i2se	I2SE GmbH
+iar	IAR Systems AB
 ibm	International Business Machines (IBM)
 icplus	IC Plus Corp.
 idt	Integrated Device Technologies, Inc.
@@ -357,6 +360,7 @@ kontron	Kontron S&T AG
 kosagi	Sutajio Ko-Usagi PTE Ltd.
 kvaser	Kvaser
 kvg	Kverneland Group
+kws	KWS Computersysteme Gmbh
 kyo	Kyocera Corporation
 lacie	LaCie
 laird	Laird PLC
@@ -379,6 +383,7 @@ linksys	Belkin International, Inc. (Linksys)
 linutronix	Linutronix GmbH
 linux	Linux-specific binding
 linx	Linx Technologies
+liteon	LiteOn OptoElectronics
 litex	LiteX SoC builder
 lltc	Linear Technology Corporation
 logicpd	Logic PD, Inc.
@@ -388,7 +393,6 @@ lontium	Lontium Semiconductor Corporation
 loongson	Loongson Technology Corporation Limited
 lowrisc	lowRISC Community Interest Company
 lsi	LSI Corp. (LSI Logic)
-ltr	LiteOn OptoElectronics
 luatos	LuatOS Team
 lwn	Liebherr-Werk Nenzing GmbH
 lxa	Linux Automation GmbH
@@ -451,6 +455,7 @@ myir	MYIR Tech Limited
 national	National Semiconductor
 nec	NEC LCD Technologies, Ltd.
 neonode	Neonode Inc.
+neorv32	NEORV32 RISC-V Processor
 netgear	NETGEAR
 netlogic	Broadcom Corporation (formerly NetLogic Microsystems)
 netron-dy	Netron DY
@@ -485,6 +490,7 @@ onnn	ON Semiconductor Corp.
 ontat	On Tat Industrial Company
 opalkelly	Opal Kelly Incorporated
 opencores	OpenCores.org
+openhwgroup	OpenHW Group
 openisa	open-isa.org
 openrisc	OpenRISC.io
 openthread	OpenThread.io
@@ -505,12 +511,14 @@ parade	Parade Technologies Inc.
 parallax	Parallax Inc.
 particle	Particle.io
 pda	Precision Design Associates, Inc.
+peregrine	Peregrine Consultoria e Servicos
 pericom	Pericom Technology Inc.
 pervasive	Pervasive Displays, Inc.
 phicomm	PHICOMM Co., Ltd.
 phosense	Beijing Phosense Electronic Technology Co., Ltd.
 phytec	PHYTEC
 picochip	Picochip Ltd
+pimoroni	Pimoroni Ltd.
 pine64	Pine64
 pineriver	Shenzhen PineRiver Designs Co., Ltd.
 pixart	PixArt Imaging Inc.
@@ -574,6 +582,7 @@ ronbo	Ronbo Electronics
 ronoth	Ronoth
 roofull	Shenzhen Roofull Technology Co, Ltd
 roseapplepi	RoseapplePi.org
+ruiside	Shanghai Ruiside Electronic Technology Co., Ltd.
 ruuvi	Ruuvi Innovations Ltd (Oy)
 samsung	Samsung Semiconductor
 samtec	Samtec/Softing company
diff --git a/dts/bindings/video/espressif,esp32-cam.yaml b/dts/bindings/video/espressif,esp32-cam.yaml
index 309c1e954f7..2aaef707354 100644
--- a/dts/bindings/video/espressif,esp32-cam.yaml
+++ b/dts/bindings/video/espressif,esp32-cam.yaml
@@ -4,7 +4,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-description: esp32 LCD CAM Peripheral interface
+description: ESP32 LCD CAM Peripheral interface
 
 compatible: "espressif,esp32-lcd-cam"
 
diff --git a/dts/bindings/video/galaxycore,gc2145.yaml b/dts/bindings/video/galaxycore,gc2145.yaml
index d74a4b60973..a275023c371 100644
--- a/dts/bindings/video/galaxycore,gc2145.yaml
+++ b/dts/bindings/video/galaxycore,gc2145.yaml
@@ -13,3 +13,8 @@ properties:
     description: |
       The RESETn pin is asserted to disable the sensor causing a hard
       reset.  The sensor receives this as an active-low signal.
+  pwdn-gpios:
+    type: phandle-array
+    description: |
+      The PWDN pin is asserted to power down the sensor. The sensor
+      receives this as an active high signal
diff --git a/dts/bindings/video/st,stm32-dcmi.yaml b/dts/bindings/video/st,stm32-dcmi.yaml
index 8381ae0acaf..567b8d0efa8 100644
--- a/dts/bindings/video/st,stm32-dcmi.yaml
+++ b/dts/bindings/video/st,stm32-dcmi.yaml
@@ -5,7 +5,8 @@
 #
 
 description: |
-    STMicroelectronics STM32 Digital Camera Memory Interface (DCMI).
+    STM32 Digital Camera Memory Interface (DCMI).
+
     Example of node configuration at board level:
 
     &dcmi {
diff --git a/dts/bindings/watchdog/atmel,sam4l-watchdog.yaml b/dts/bindings/watchdog/atmel,sam4l-watchdog.yaml
new file mode 100644
index 00000000000..05916724474
--- /dev/null
+++ b/dts/bindings/watchdog/atmel,sam4l-watchdog.yaml
@@ -0,0 +1,37 @@
+# Copyright (c) 2024-2025, Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+description: ATMEL SAM4L watchdog
+
+compatible: "atmel,sam4l-watchdog"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  clocks:
+    required: true
+
+  clk-source:
+    type: string
+    default: "rcsys"
+    enum:
+      - "rcsys"
+      - "osc32k"
+    description: |
+      Watchdog counter clock source:
+        - rcsys:  115kHz internal System RC oscillator
+        - osc32k: 32kHz clock source
+      Defaults to "rcsys" (hardware reset value) and always enabled source
+
+  lock-mode:
+    type: boolean
+    description: |
+      Lock the watchdog when setup is executed. This provides a write protection
+      to the control register. This mechanism can only be released when a hardware
+      reset happens.
diff --git a/dts/bindings/watchdog/espressif,esp32-watchdog.yaml b/dts/bindings/watchdog/espressif,esp32-watchdog.yaml
index 87997e291ad..9f134359c3a 100644
--- a/dts/bindings/watchdog/espressif,esp32-watchdog.yaml
+++ b/dts/bindings/watchdog/espressif,esp32-watchdog.yaml
@@ -2,7 +2,9 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    ESP32 watchdog. ESP32 contains 3x Watchdog timers, 2x Main System Watchdog
+    ESP32 watchdog.
+
+    ESP32 contains 3x Watchdog timers, 2x Main System Watchdog
     Timer (MWDT), 1x RTC Watchdog Timer (RWDT). RWDT is not supported yet.
 
 compatible: "espressif,esp32-watchdog"
diff --git a/dts/bindings/watchdog/espressif,esp32-xt-wdt.yaml b/dts/bindings/watchdog/espressif,esp32-xt-wdt.yaml
index c20a4234cab..4dec4f39f57 100644
--- a/dts/bindings/watchdog/espressif,esp32-xt-wdt.yaml
+++ b/dts/bindings/watchdog/espressif,esp32-xt-wdt.yaml
@@ -2,6 +2,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
+    ESP32 XT Watchdog Timer.
+
     This watchdog timer can detect oscillation failure of the RTC_SLOW_CLK_SRC_XTAL32K.
     When such a failure is detected the hardware automatically switch to
     ESP32_RTC_SLOW_CLK_SRC_RC_SLOW.
diff --git a/dts/bindings/watchdog/intel,tco-wdt.yaml b/dts/bindings/watchdog/intel,tco-wdt.yaml
index af1f00902d7..dad010efae5 100644
--- a/dts/bindings/watchdog/intel,tco-wdt.yaml
+++ b/dts/bindings/watchdog/intel,tco-wdt.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2022 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
-description: Intel TCO Watchdog driver binding
+description: Intel TCO Watchdog
 
 compatible: "intel,tco-wdt"
 
diff --git a/dts/bindings/watchdog/ite,it51xxx-watchdog.yaml b/dts/bindings/watchdog/ite,it51xxx-watchdog.yaml
new file mode 100644
index 00000000000..1c666b9ae70
--- /dev/null
+++ b/dts/bindings/watchdog/ite,it51xxx-watchdog.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+description: ITE watchdog timer
+
+include: base.yaml
+
+compatible: "ite,it51xxx-watchdog"
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
diff --git a/dts/bindings/watchdog/nuvoton,npcx-watchdog.yaml b/dts/bindings/watchdog/nuvoton,npcx-watchdog.yaml
index 87a2abb2e62..b967d669e82 100644
--- a/dts/bindings/watchdog/nuvoton,npcx-watchdog.yaml
+++ b/dts/bindings/watchdog/nuvoton,npcx-watchdog.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2021 Nuvoton Technology Corporation.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Nuvoton, NPCX-TWD node
+description: Nuvoton, NPCX-TWD
 
 compatible: "nuvoton,npcx-watchdog"
 
diff --git a/dts/bindings/watchdog/nxp,rtwdog.yaml b/dts/bindings/watchdog/nxp,rtwdog.yaml
new file mode 100644
index 00000000000..d834dc1f4ce
--- /dev/null
+++ b/dts/bindings/watchdog/nxp,rtwdog.yaml
@@ -0,0 +1,28 @@
+# Copyright 2024, NXP
+# SPDX-License-Identifier: Apache-2.0
+
+description: NXP RT watchdog
+
+compatible: "nxp,rtwdog"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  clocks:
+    required: true
+
+  clk-source:
+    type: int
+    required: true
+    description: Watchdog counter clock source
+
+  clk-divider:
+    type: int
+    description: Watchdog counter clock divider
+    required: true
diff --git a/dts/bindings/watchdog/realtek,rts5912-watchdog.yaml b/dts/bindings/watchdog/realtek,rts5912-watchdog.yaml
new file mode 100644
index 00000000000..7edde70be1e
--- /dev/null
+++ b/dts/bindings/watchdog/realtek,rts5912-watchdog.yaml
@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Realtek, SIBG-SD7
+# SPDX-License-Identifier: Apache-2.0
+
+description: Realtek RTS5912 watchdog timer
+
+include: base.yaml
+
+compatible: "realtek,rts5912-watchdog"
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  clk-divider:
+    type: int
+    description: Watchdog clock divider
+    required: true
diff --git a/dts/bindings/watchdog/renesas,ra-wdt.yaml b/dts/bindings/watchdog/renesas,ra-wdt.yaml
new file mode 100644
index 00000000000..f50b9e4f4b2
--- /dev/null
+++ b/dts/bindings/watchdog/renesas,ra-wdt.yaml
@@ -0,0 +1,15 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+description: Renesas RA Watchdog (wdt)
+
+compatible: "renesas,ra-wdt"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  clocks:
+    required: true
diff --git a/dts/bindings/watchdog/silabs,siwx91x-wdt.yaml b/dts/bindings/watchdog/silabs,siwx91x-wdt.yaml
new file mode 100644
index 00000000000..fafa84f9e06
--- /dev/null
+++ b/dts/bindings/watchdog/silabs,siwx91x-wdt.yaml
@@ -0,0 +1,12 @@
+description: Silabs SiWx91x Watchdog
+
+compatible: "silabs,siwx91x-wdt"
+
+include: base.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
diff --git a/dts/bindings/wifi/espressif,esp-at.yaml b/dts/bindings/wifi/espressif,esp-at.yaml
index 33f9a492bfe..b1f0ea23c77 100644
--- a/dts/bindings/wifi/espressif,esp-at.yaml
+++ b/dts/bindings/wifi/espressif,esp-at.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2019 Tobias Svehagen
 # SPDX-License-Identifier: Apache-2.0
 
-description: Espressif ESP8266/ESP32 WiFi modem (AT Commands)
+description: ESP8266/ESP32 WiFi modem (AT Commands)
 
 compatible: "espressif,esp-at"
 
diff --git a/dts/bindings/wifi/espressif,esp32-wifi.yaml b/dts/bindings/wifi/espressif,esp32-wifi.yaml
index af84531812b..9a1bf691c42 100644
--- a/dts/bindings/wifi/espressif,esp32-wifi.yaml
+++ b/dts/bindings/wifi/espressif,esp32-wifi.yaml
@@ -1,6 +1,6 @@
 # Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
-description: Espressif ESP32 SoC WiFi
+description: ESP32 SoC Wi-Fi
 
 compatible: "espressif,esp32-wifi"
diff --git a/dts/bindings/wifi/nordic,nrf70-coex.yaml b/dts/bindings/wifi/nordic,nrf70-coex.yaml
index 0a9c12f587e..0ab29cd63a1 100644
--- a/dts/bindings/wifi/nordic,nrf70-coex.yaml
+++ b/dts/bindings/wifi/nordic,nrf70-coex.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  This is a representation of an external radio coexistence setup for coexistence
+  An external radio coexistence setup for coexistence
   with nRF70 WiFi chips.
 
 properties:
diff --git a/dts/bindings/wifi/nordic,nrf70-qspi.yaml b/dts/bindings/wifi/nordic,nrf70-qspi.yaml
index 87a98d5b358..e4dd79d1b00 100644
--- a/dts/bindings/wifi/nordic,nrf70-qspi.yaml
+++ b/dts/bindings/wifi/nordic,nrf70-qspi.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-description: This is a representation of the nRF70 Wi-Fi chip.
+description: nRF70 Wi-Fi chip with QSPI interface.
 
 include: ["nordic,nrf70.yaml", "base.yaml"]
 
diff --git a/dts/bindings/wifi/nordic,nrf70-spi.yaml b/dts/bindings/wifi/nordic,nrf70-spi.yaml
index a0363f1b1a4..a74458c6892 100644
--- a/dts/bindings/wifi/nordic,nrf70-spi.yaml
+++ b/dts/bindings/wifi/nordic,nrf70-spi.yaml
@@ -1,6 +1,6 @@
 # Copyright (c) 2024 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-description: This is a representation of the nRF70 Wi-Fi chip.
+description: nRF70 Wi-Fi chip with SPI interface.
 
 include: ["nordic,nrf70.yaml", "spi-device.yaml"]
diff --git a/dts/bindings/wifi/nordic,nrf70.yaml b/dts/bindings/wifi/nordic,nrf70.yaml
index abdc7ec2cb0..eacec39eefc 100644
--- a/dts/bindings/wifi/nordic,nrf70.yaml
+++ b/dts/bindings/wifi/nordic,nrf70.yaml
@@ -22,3 +22,10 @@ properties:
     description: |
       GPIO of the RF Switch to control SR RF output to either SR Antenna
       or shared Antenna with Wi-Fi
+
+  iovdd-power-up-delay-ms:
+    type: int
+    default: 1
+    description: |
+      Duration to wait after enabling IOVDD before attempting communications.
+      Default value of 1 comes from the nRF7002 DK/EK switch (TCK106AG): ~600us
diff --git a/dts/bindings/wifi/nordic,nrf7000-coex.yaml b/dts/bindings/wifi/nordic,nrf7000-coex.yaml
index 94dcc2181d3..227f10bc9c6 100644
--- a/dts/bindings/wifi/nordic,nrf7000-coex.yaml
+++ b/dts/bindings/wifi/nordic,nrf7000-coex.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-description: This is a representation of the nRF7000 Wi-Fi chip with COEX interface.
+description: nRF7000 Wi-Fi chip with COEX interface.
 
 compatible: nordic,nrf7000-coex
 
diff --git a/dts/bindings/wifi/nordic,nrf7000-qspi.yaml b/dts/bindings/wifi/nordic,nrf7000-qspi.yaml
index f25663749e8..f12c336eb1b 100644
--- a/dts/bindings/wifi/nordic,nrf7000-qspi.yaml
+++ b/dts/bindings/wifi/nordic,nrf7000-qspi.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-description: This is a representation of the nRF7002 Wi-Fi chip with QSPI interface.
+description: nRF7002 Wi-Fi chip with QSPI interface.
 
 compatible: nordic,nrf7000-qspi
 
diff --git a/dts/bindings/wifi/nordic,nrf7000-spi.yaml b/dts/bindings/wifi/nordic,nrf7000-spi.yaml
index 3c5710a38f2..5268e31769e 100644
--- a/dts/bindings/wifi/nordic,nrf7000-spi.yaml
+++ b/dts/bindings/wifi/nordic,nrf7000-spi.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-description: This is a representation of the nRF7002 Wi-Fi chip with SPI interface.
+description: nRF7002 Wi-Fi chip with SPI interface.
 
 compatible: nordic,nrf7000-spi
 
diff --git a/dts/bindings/wifi/nordic,nrf7001-coex.yaml b/dts/bindings/wifi/nordic,nrf7001-coex.yaml
index d58afe7d44c..4dee31b890f 100644
--- a/dts/bindings/wifi/nordic,nrf7001-coex.yaml
+++ b/dts/bindings/wifi/nordic,nrf7001-coex.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-description: This is a representation of the nRF7001 Wi-Fi chip with COEX interface.
+description: nRF7001 Wi-Fi chip with COEX interface.
 
 compatible: nordic,nrf7001-coex
 
diff --git a/dts/bindings/wifi/nordic,nrf7001-qspi.yaml b/dts/bindings/wifi/nordic,nrf7001-qspi.yaml
index 1961677fad2..c8d2560e22d 100644
--- a/dts/bindings/wifi/nordic,nrf7001-qspi.yaml
+++ b/dts/bindings/wifi/nordic,nrf7001-qspi.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-description: This is a representation of the nRF7002 Wi-Fi chip with QSPI interface.
+description: nRF7002 Wi-Fi chip with QSPI interface.
 
 compatible: nordic,nrf7001-qspi
 
diff --git a/dts/bindings/wifi/nordic,nrf7001-spi.yaml b/dts/bindings/wifi/nordic,nrf7001-spi.yaml
index 5c516945e44..d586b48f9b2 100644
--- a/dts/bindings/wifi/nordic,nrf7001-spi.yaml
+++ b/dts/bindings/wifi/nordic,nrf7001-spi.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-description: This is a representation of the nRF7002 Wi-Fi chip with SPI interface.
+description: nRF7002 Wi-Fi chip with SPI interface.
 
 compatible: nordic,nrf7001-spi
 
diff --git a/dts/bindings/wifi/nordic,nrf7002-coex.yaml b/dts/bindings/wifi/nordic,nrf7002-coex.yaml
index 1df61d0bf98..b41d403fc28 100644
--- a/dts/bindings/wifi/nordic,nrf7002-coex.yaml
+++ b/dts/bindings/wifi/nordic,nrf7002-coex.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-description: This is a representation of the nRF7002 Wi-Fi chip with COEX interface.
+description: nRF7002 Wi-Fi chip with COEX interface.
 
 compatible: nordic,nrf7002-coex
 
diff --git a/dts/bindings/wifi/nordic,nrf7002-qspi.yaml b/dts/bindings/wifi/nordic,nrf7002-qspi.yaml
index 101bcfce11f..9e6b617f221 100644
--- a/dts/bindings/wifi/nordic,nrf7002-qspi.yaml
+++ b/dts/bindings/wifi/nordic,nrf7002-qspi.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-description: This is a representation of the nRF7002 Wi-Fi chip with QSPI interface.
+description: nRF7002 Wi-Fi chip with QSPI interface.
 
 compatible: nordic,nrf7002-qspi
 
diff --git a/dts/bindings/wifi/nordic,nrf7002-spi.yaml b/dts/bindings/wifi/nordic,nrf7002-spi.yaml
index af12744161a..bdab20a6739 100644
--- a/dts/bindings/wifi/nordic,nrf7002-spi.yaml
+++ b/dts/bindings/wifi/nordic,nrf7002-spi.yaml
@@ -1,7 +1,7 @@
 # Copyright (c) 2024 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-description: This is a representation of the nRF7002 Wi-Fi chip with SPI interface.
+description: nRF7002 Wi-Fi chip with SPI interface.
 
 compatible: nordic,nrf7002-spi
 
diff --git a/dts/bindings/wifi/nxp,wifi.yaml b/dts/bindings/wifi/nxp,wifi.yaml
index 32d6adc5a65..416d334214c 100644
--- a/dts/bindings/wifi/nxp,wifi.yaml
+++ b/dts/bindings/wifi/nxp,wifi.yaml
@@ -3,8 +3,8 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    NXP Wifi Module
+    NXP Wi-Fi Module
 
 compatible: "nxp,wifi"
 
-include: [sd-device.yaml, pinctrl-device.yaml]
+include: [base.yaml, pinctrl-device.yaml]
diff --git a/dts/bindings/wifi/silabs,siwx91x-wifi.yaml b/dts/bindings/wifi/silabs,siwx91x-wifi.yaml
new file mode 100644
index 00000000000..fe93e4910d0
--- /dev/null
+++ b/dts/bindings/wifi/silabs,siwx91x-wifi.yaml
@@ -0,0 +1,7 @@
+# Copyright (c) 2023 Antmicro
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: Silabs SiWx91x SoC WiFi
+
+compatible: "silabs,siwx91x-wifi"
diff --git a/dts/bindings/wifi/wifi-tx-power-2g.yaml b/dts/bindings/wifi/wifi-tx-power-2g.yaml
index 967cee43981..a628af580f8 100644
--- a/dts/bindings/wifi/wifi-tx-power-2g.yaml
+++ b/dts/bindings/wifi/wifi-tx-power-2g.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  This is a representation of the Wi-Fi transmit power ceilings
+  Wi-Fi transmit power ceilings
   i.e., maximum transmit power allowed for 2.4GHz band. Based on the
   RF performance of the device, the transmit power can be limited
   for different data rates and sub-bands to get the best performance.
diff --git a/dts/bindings/wifi/wifi-tx-power-5g.yaml b/dts/bindings/wifi/wifi-tx-power-5g.yaml
index b9af40e0b9f..1f3452f28c2 100644
--- a/dts/bindings/wifi/wifi-tx-power-5g.yaml
+++ b/dts/bindings/wifi/wifi-tx-power-5g.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-  This is a representation of the Wi-Fi transmit power ceilings
+  Wi-Fi transmit power ceilings
   i.e., maximum transmit power allowed for 5GHz band. Based on the
   RF performance of the device, the transmit power can be limited
   for different data rates and sub-bands to get the best performance.
diff --git a/dts/bindings/xspi/st,stm32-xspi.yaml b/dts/bindings/xspi/st,stm32-xspi.yaml
index 388c3d20bca..873c5c8776f 100644
--- a/dts/bindings/xspi/st,stm32-xspi.yaml
+++ b/dts/bindings/xspi/st,stm32-xspi.yaml
@@ -2,7 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 description: |
-    STM32 XSPI device representation. Enabling a stm32 xspi node in a board
+    STM32 XSPI Controller.
 
 compatible: "st,stm32-xspi"
 
diff --git a/dts/common/amd/versalnet.dtsi b/dts/common/amd/versalnet.dtsi
new file mode 100644
index 00000000000..e5ab51ad59f
--- /dev/null
+++ b/dts/common/amd/versalnet.dtsi
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2025, Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	soc: soc {
+		ocm: memory@bbf00000 {
+			compatible = "zephyr,memory-region";
+			reg = <0xbbf00000 DT_SIZE_M(1)>;
+			status = "disabled";
+			zephyr,memory-region = "OCM";
+		};
+
+		uart0: uart@f1920000 {
+			compatible = "arm,sbsa-uart";
+			reg = <0xf1920000 0x4c>;
+			status = "disabled";
+			interrupt-names = "irq_0";
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		};
+
+		uart1: uart@f1930000 {
+			compatible = "arm,sbsa-uart";
+			reg = <0xf1930000 0x1000>;
+			status = "disabled";
+			interrupt-names = "irq_1";
+			interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		};
+	};
+};
diff --git a/dts/common/espressif/partitions_0x0_amp.dtsi b/dts/common/espressif/partitions_0x0_amp.dtsi
index 024e273da1f..d3424efb006 100644
--- a/dts/common/espressif/partitions_0x0_amp.dtsi
+++ b/dts/common/espressif/partitions_0x0_amp.dtsi
@@ -1,7 +1,7 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- #include <espressif/partitions_0x0_amp_4M.dtsi>
+#include <espressif/partitions_0x0_amp_4M.dtsi>
diff --git a/dts/common/espressif/partitions_0x0_amp_16M.dtsi b/dts/common/espressif/partitions_0x0_amp_16M.dtsi
index 86088c3f5fe..54eb03f738b 100644
--- a/dts/common/espressif/partitions_0x0_amp_16M.dtsi
+++ b/dts/common/espressif/partitions_0x0_amp_16M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 16MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,42 +12,56 @@
 
 		boot_partition: partition@0 {
 			label = "mcuboot";
-			reg = <0x0 DT_SIZE_K(64)>;
+			reg = <0x0 DT_SIZE_K(128)>;
 		};
 
 		slot0_partition: partition@20000 {
 			label = "image-0";
-			reg = <0x20000 DT_SIZE_K(6080)>;
+			reg = <0x20000 DT_SIZE_K(5952)>;
 		};
 
-		slot0_appcpu_partition: partition@610000 {
-			label = "image-0-appcpu";
-			reg = <0x610000 DT_SIZE_K(1920)>;
+		slot1_partition: partition@5f0000 {
+			label = "image-1";
+			reg = <0x5F0000 DT_SIZE_K(5952)>;
 		};
 
-		slot1_partition: partition@7F0000 {
-			label = "image-1";
-			reg = <0x7F0000 DT_SIZE_K(6080)>;
+		slot0_appcpu_partition: partition@bc0000 {
+			label = "image-0-appcpu";
+			reg = <0xBC0000 DT_SIZE_K(1984)>;
 		};
 
-		slot1_appcpu_partition: partition@DE0000 {
+		slot1_appcpu_partition: partition@db0000 {
 			label = "image-1-appcpu";
-			reg = <0xDE0000 DT_SIZE_K(1920)>;
+			reg = <0xDB0000 DT_SIZE_K(1984)>;
+		};
+
+		slot0_lpcore_partition: partition@fa0000 {
+			label = "image-0-lpcore";
+			reg = <0xFA0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@fa8000 {
+			label = "image-1-lpcore";
+			reg = <0xFA8000 DT_SIZE_K(32)>;
 		};
 
-		storage_partition: partition@FC0000 {
+		storage_partition: partition@fb0000 {
 			label = "storage";
-			reg = <0xFC0000 DT_SIZE_K(128)>;
+			reg = <0xFB0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@FE0000 {
-			   label = "image-scratch";
-			   reg = <0xFE0000 DT_SIZE_K(64)>;
+		scratch_partition: partition@fe0000 {
+			label = "image-scratch";
+			reg = <0xFE0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@FF0000 {
-			label = "coredump-partition";
-			reg = <0xFF0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@fff000 {
+			label = "coredump";
+			reg = <0xFFF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0xFFFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x0_amp_2M.dtsi b/dts/common/espressif/partitions_0x0_amp_2M.dtsi
index 77c8f480a56..adc496d577e 100644
--- a/dts/common/espressif/partitions_0x0_amp_2M.dtsi
+++ b/dts/common/espressif/partitions_0x0_amp_2M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 2MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,7 +12,7 @@
 
 		boot_partition: partition@0 {
 			label = "mcuboot";
-			reg = <0x0 DT_SIZE_K(64)>;
+			reg = <0x0 DT_SIZE_K(128)>;
 		};
 
 		slot0_partition: partition@20000 {
@@ -21,34 +20,48 @@
 			reg = <0x20000 DT_SIZE_K(576)>;
 		};
 
-		slot0_appcpu_partition: partition@B0000 {
-			label = "image-0-appcpu";
-			reg = <0xB0000 DT_SIZE_K(256)>;
+		slot1_partition: partition@b0000 {
+			label = "image-1";
+			reg = <0xB0000 DT_SIZE_K(576)>;
 		};
 
-		slot1_partition: partition@F0000 {
-			label = "image-1";
-			reg = <0xF0000 DT_SIZE_K(576)>;
+		slot0_appcpu_partition: partition@140000 {
+			label = "image-0-appcpu";
+			reg = <0x140000 DT_SIZE_K(192)>;
 		};
 
-		slot1_appcpu_partition: partition@180000 {
+		slot1_appcpu_partition: partition@170000 {
 			label = "image-1-appcpu";
-			reg = <0x1a0000 DT_SIZE_K(256)>;
+			reg = <0x170000 DT_SIZE_K(192)>;
+		};
+
+		slot0_lpcore_partition: partition@1a0000 {
+			label = "image-0-lpcore";
+			reg = <0x1A0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@1a8000 {
+			label = "image-1-lpcore";
+			reg = <0x1A8000 DT_SIZE_K(32)>;
 		};
 
-		storage_partition: partition@1C0000 {
+		storage_partition: partition@1b0000 {
 			label = "storage";
-			reg = <0x1C0000 DT_SIZE_K(128)>;
+			reg = <0x1B0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@1E0000 {
-			   label = "image-scratch";
-			   reg = <0x1E0000 DT_SIZE_K(64)>;
+		scratch_partition: partition@1e0000 {
+			label = "image-scratch";
+			reg = <0x1E0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@1F0000 {
-			label = "coredump-partition";
-			reg = <0x1F0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@1ff000 {
+			label = "coredump";
+			reg = <0x1FF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0x1FFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x0_amp_32M.dtsi b/dts/common/espressif/partitions_0x0_amp_32M.dtsi
index e5a95fc3bec..2d8c92d1b32 100644
--- a/dts/common/espressif/partitions_0x0_amp_32M.dtsi
+++ b/dts/common/espressif/partitions_0x0_amp_32M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 32MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,42 +12,56 @@
 
 		boot_partition: partition@0 {
 			label = "mcuboot";
-			reg = <0x0 DT_SIZE_K(64)>;
+			reg = <0x0 DT_SIZE_K(128)>;
 		};
 
 		slot0_partition: partition@20000 {
 			label = "image-0";
-			reg = <0x20000 DT_SIZE_K(12352)>;
+			reg = <0x20000 DT_SIZE_K(12096)>;
 		};
 
-		slot0_appcpu_partition: partition@C30000 {
-			label = "image-0-appcpu";
-			reg = <0xC30000 DT_SIZE_K(3840)>;
+		slot1_partition: partition@bf0000 {
+			label = "image-1";
+			reg = <0xBF0000 DT_SIZE_K(12096)>;
 		};
 
-		slot1_partition: partition@FF0000 {
-			label = "image-1";
-			reg = <0xFF0000 DT_SIZE_K(12352)>;
+		slot0_appcpu_partition: partition@17c0000 {
+			label = "image-0-appcpu";
+			reg = <0x17C0000 DT_SIZE_K(4032)>;
 		};
 
-		slot1_appcpu_partition: partition@1C00000 {
+		slot1_appcpu_partition: partition@1bb0000 {
 			label = "image-1-appcpu";
-			reg = <0x1C00000 DT_SIZE_K(3840)>;
+			reg = <0x1BB0000 DT_SIZE_K(4032)>;
+		};
+
+		slot0_lpcore_partition: partition@1fa0000 {
+			label = "image-0-lpcore";
+			reg = <0x1FA0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@1fa8000 {
+			label = "image-1-lpcore";
+			reg = <0x1FA8000 DT_SIZE_K(32)>;
 		};
 
-		storage_partition: partition@1FC0000 {
+		storage_partition: partition@1fb0000 {
 			label = "storage";
-			reg = <0x1FC0000 DT_SIZE_K(128)>;
+			reg = <0x1FB0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@1FE0000 {
-			   label = "image-scratch";
-			   reg = <0x1FE0000 DT_SIZE_K(64)>;
+		scratch_partition: partition@1fe0000 {
+			label = "image-scratch";
+			reg = <0x1FE0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@1FF0000 {
-			label = "coredump-partition";
-			reg = <0x1FF0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@1fff000 {
+			label = "coredump";
+			reg = <0x1FFF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0x1FFFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x0_amp_4M.dtsi b/dts/common/espressif/partitions_0x0_amp_4M.dtsi
index 067615de5dd..856e35326e0 100644
--- a/dts/common/espressif/partitions_0x0_amp_4M.dtsi
+++ b/dts/common/espressif/partitions_0x0_amp_4M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 4MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,7 +12,7 @@
 
 		boot_partition: partition@0 {
 			label = "mcuboot";
-			reg = <0x0 DT_SIZE_K(64)>;
+			reg = <0x0 DT_SIZE_K(128)>;
 		};
 
 		slot0_partition: partition@20000 {
@@ -21,34 +20,48 @@
 			reg = <0x20000 DT_SIZE_K(1344)>;
 		};
 
-		slot0_appcpu_partition: partition@170000 {
-			label = "image-0-appcpu";
-			reg = <0x170000 DT_SIZE_K(512)>;
+		slot1_partition: partition@170000 {
+			label = "image-1";
+			reg = <0x170000 DT_SIZE_K(1344)>;
 		};
 
-		slot1_partition: partition@1F0000 {
-			label = "image-1";
-			reg = <0x1F0000 DT_SIZE_K(1344)>;
+		slot0_appcpu_partition: partition@2c0000 {
+			label = "image-0-appcpu";
+			reg = <0x2C0000 DT_SIZE_K(448)>;
 		};
 
-		slot1_appcpu_partition: partition@340000 {
+		slot1_appcpu_partition: partition@330000 {
 			label = "image-1-appcpu";
-			reg = <0x340000 DT_SIZE_K(512)>;
+			reg = <0x330000 DT_SIZE_K(448)>;
+		};
+
+		slot0_lpcore_partition: partition@3a0000 {
+			label = "image-0-lpcore";
+			reg = <0x3A0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@3a8000 {
+			label = "image-1-lpcore";
+			reg = <0x3A8000 DT_SIZE_K(32)>;
 		};
 
-		storage_partition: partition@3C0000 {
+		storage_partition: partition@3b0000 {
 			label = "storage";
-			reg = <0x3C0000 DT_SIZE_K(128)>;
+			reg = <0x3B0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@3E0000 {
-			   label = "image-scratch";
-			   reg = <0x3E0000 DT_SIZE_K(64)>;
+		scratch_partition: partition@3e0000 {
+			label = "image-scratch";
+			reg = <0x3E0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@3F0000 {
-			label = "coredump-partition";
-			reg = <0x3F0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@3ff000 {
+			label = "coredump";
+			reg = <0x3FF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0x3FFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x0_amp_8M.dtsi b/dts/common/espressif/partitions_0x0_amp_8M.dtsi
index bbba09092e7..e854d854780 100644
--- a/dts/common/espressif/partitions_0x0_amp_8M.dtsi
+++ b/dts/common/espressif/partitions_0x0_amp_8M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 8MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,42 +12,56 @@
 
 		boot_partition: partition@0 {
 			label = "mcuboot";
-			reg = <0x0 DT_SIZE_K(64)>;
+			reg = <0x0 DT_SIZE_K(128)>;
 		};
 
 		slot0_partition: partition@20000 {
 			label = "image-0";
-			reg = <0x20000 DT_SIZE_K(3136)>;
+			reg = <0x20000 DT_SIZE_K(2880)>;
 		};
 
-		slot0_appcpu_partition: partition@330000 {
-			label = "image-0-appcpu";
-			reg = <0x330000 DT_SIZE_K(768)>;
+		slot1_partition: partition@2f0000 {
+			label = "image-1";
+			reg = <0x2F0000 DT_SIZE_K(2880)>;
 		};
 
-		slot1_partition: partition@3F0000 {
-			label = "image-1";
-			reg = <0x3F0000 DT_SIZE_K(3136)>;
+		slot0_appcpu_partition: partition@5c0000 {
+			label = "image-0-appcpu";
+			reg = <0x5C0000 DT_SIZE_K(960)>;
 		};
 
-		slot1_appcpu_partition: partition@700000 {
+		slot1_appcpu_partition: partition@6b0000 {
 			label = "image-1-appcpu";
-			reg = <0x700000 DT_SIZE_K(768)>;
+			reg = <0x6B0000 DT_SIZE_K(960)>;
+		};
+
+		slot0_lpcore_partition: partition@7a0000 {
+			label = "image-0-lpcore";
+			reg = <0x7A0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@7a8000 {
+			label = "image-1-lpcore";
+			reg = <0x7A8000 DT_SIZE_K(32)>;
 		};
 
-		storage_partition: partition@7C0000 {
+		storage_partition: partition@7b0000 {
 			label = "storage";
-			reg = <0x7C0000 DT_SIZE_K(128)>;
+			reg = <0x7B0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@7E0000 {
-			   label = "image-scratch";
-			   reg = <0x7E0000 DT_SIZE_K(64)>;
+		scratch_partition: partition@7e0000 {
+			label = "image-scratch";
+			reg = <0x7E0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@7F0000 {
-			label = "coredump-partition";
-			reg = <0x7F0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@7ff000 {
+			label = "coredump";
+			reg = <0x7FF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0x7FFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x0_default.dtsi b/dts/common/espressif/partitions_0x0_default.dtsi
index 851fffe886b..5f51a092607 100644
--- a/dts/common/espressif/partitions_0x0_default.dtsi
+++ b/dts/common/espressif/partitions_0x0_default.dtsi
@@ -1,7 +1,7 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- #include <espressif/partitions_0x0_default_4M.dtsi>
+#include <espressif/partitions_0x0_default_4M.dtsi>
diff --git a/dts/common/espressif/partitions_0x0_default_16M.dtsi b/dts/common/espressif/partitions_0x0_default_16M.dtsi
index d4b01753d0b..1f595c1a030 100644
--- a/dts/common/espressif/partitions_0x0_default_16M.dtsi
+++ b/dts/common/espressif/partitions_0x0_default_16M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 16MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,32 +12,46 @@
 
 		boot_partition: partition@0 {
 			label = "mcuboot";
-			reg = <0x0 DT_SIZE_K(64)>;
+			reg = <0x0 DT_SIZE_K(128)>;
 		};
 
 		slot0_partition: partition@20000 {
 			label = "image-0";
-			reg = <0x20000 DT_SIZE_K(8000)>;
+			reg = <0x20000 DT_SIZE_K(7936)>;
 		};
 
-		slot1_partition: partition@7F0000 {
+		slot1_partition: partition@7e0000 {
 			label = "image-1";
-			reg = <0x7F0000 DT_SIZE_K(8000)>;
+			reg = <0x7E0000 DT_SIZE_K(7936)>;
 		};
 
-		storage_partition: partition@FC0000 {
+		slot0_lpcore_partition: partition@fa0000 {
+			label = "image-0-lpcore";
+			reg = <0xFA0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@fa8000 {
+			label = "image-1-lpcore";
+			reg = <0xFA8000 DT_SIZE_K(32)>;
+		};
+
+		storage_partition: partition@fb0000 {
 			label = "storage";
-			reg = <0xFC0000 DT_SIZE_K(128)>;
+			reg = <0xFB0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@FE0000 {
-			   label = "image-scratch";
-			   reg = <0xFE0000 DT_SIZE_K(64)>;
+		scratch_partition: partition@fe0000 {
+			label = "image-scratch";
+			reg = <0xFE0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@FF0000 {
-			label = "coredump-partition";
-			reg = <0xFF0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@fff000 {
+			label = "coredump";
+			reg = <0xFFF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0xFFFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x0_default_2M.dtsi b/dts/common/espressif/partitions_0x0_default_2M.dtsi
index 56e49951c53..759a17c82f6 100644
--- a/dts/common/espressif/partitions_0x0_default_2M.dtsi
+++ b/dts/common/espressif/partitions_0x0_default_2M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 2MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,32 +12,46 @@
 
 		boot_partition: partition@0 {
 			label = "mcuboot";
-			reg = <0x0 DT_SIZE_K(64)>;
+			reg = <0x0 DT_SIZE_K(128)>;
 		};
 
 		slot0_partition: partition@20000 {
 			label = "image-0";
-			reg = <0x20000 DT_SIZE_K(832)>;
+			reg = <0x20000 DT_SIZE_K(768)>;
 		};
 
-		slot1_partition: partition@F0000 {
+		slot1_partition: partition@e0000 {
 			label = "image-1";
-			reg = <0xF0000 DT_SIZE_K(832)>;
+			reg = <0xE0000 DT_SIZE_K(768)>;
 		};
 
-		storage_partition: partition@1C0000 {
+		slot0_lpcore_partition: partition@1a0000 {
+			label = "image-0-lpcore";
+			reg = <0x1A0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@1a8000 {
+			label = "image-1-lpcore";
+			reg = <0x1A8000 DT_SIZE_K(32)>;
+		};
+
+		storage_partition: partition@1b0000 {
 			label = "storage";
-			reg = <0x1C0000 DT_SIZE_K(128)>;
+			reg = <0x1B0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@1E0000 {
-			   label = "image-scratch";
-			   reg = <0x1E0000 DT_SIZE_K(64)>;
+		scratch_partition: partition@1e0000 {
+			label = "image-scratch";
+			reg = <0x1E0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@1F0000 {
-			label = "coredump-partition";
-			reg = <0x1F0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@1ff000 {
+			label = "coredump";
+			reg = <0x1FF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0x1FFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x0_default_32M.dtsi b/dts/common/espressif/partitions_0x0_default_32M.dtsi
index 710ea747eb9..77fd4a6919e 100644
--- a/dts/common/espressif/partitions_0x0_default_32M.dtsi
+++ b/dts/common/espressif/partitions_0x0_default_32M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 32MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,32 +12,46 @@
 
 		boot_partition: partition@0 {
 			label = "mcuboot";
-			reg = <0x0 DT_SIZE_K(64)>;
+			reg = <0x0 DT_SIZE_K(128)>;
 		};
 
 		slot0_partition: partition@20000 {
 			label = "image-0";
-			reg = <0x20000 DT_SIZE_K(16192)>;
+			reg = <0x20000 DT_SIZE_K(16128)>;
 		};
 
-		slot1_partition: partition@FF0000 {
+		slot1_partition: partition@fe0000 {
 			label = "image-1";
-			reg = <0xFF0000 DT_SIZE_K(16192)>;
+			reg = <0xFE0000 DT_SIZE_K(16128)>;
 		};
 
-		storage_partition: partition@1FC0000 {
+		slot0_lpcore_partition: partition@1fa0000 {
+			label = "image-0-lpcore";
+			reg = <0x1FA0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@1fa8000 {
+			label = "image-1-lpcore";
+			reg = <0x1FA8000 DT_SIZE_K(32)>;
+		};
+
+		storage_partition: partition@1fb0000 {
 			label = "storage";
-			reg = <0x1FC0000 DT_SIZE_K(128)>;
+			reg = <0x1FB0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@1FE0000 {
-			   label = "image-scratch";
-			   reg = <0x1FE0000 DT_SIZE_K(64)>;
+		scratch_partition: partition@1fe0000 {
+			label = "image-scratch";
+			reg = <0x1FE0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@1FF0000 {
-			label = "coredump-partition";
-			reg = <0x1FF0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@1fff000 {
+			label = "coredump";
+			reg = <0x1FFF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0x1FFFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x0_default_4M.dtsi b/dts/common/espressif/partitions_0x0_default_4M.dtsi
index d72be3994c6..c82ecb50fba 100644
--- a/dts/common/espressif/partitions_0x0_default_4M.dtsi
+++ b/dts/common/espressif/partitions_0x0_default_4M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 4MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,32 +12,46 @@
 
 		boot_partition: partition@0 {
 			label = "mcuboot";
-			reg = <0x0 DT_SIZE_K(64)>;
+			reg = <0x0 DT_SIZE_K(128)>;
 		};
 
 		slot0_partition: partition@20000 {
 			label = "image-0";
-			reg = <0x20000 DT_SIZE_K(1856)>;
+			reg = <0x20000 DT_SIZE_K(1792)>;
 		};
 
-		slot1_partition: partition@1F0000 {
+		slot1_partition: partition@1e0000 {
 			label = "image-1";
-			reg = <0x1F0000 DT_SIZE_K(1856)>;
+			reg = <0x1E0000 DT_SIZE_K(1792)>;
 		};
 
-		storage_partition: partition@3C0000 {
+		slot0_lpcore_partition: partition@3a0000 {
+			label = "image-0-lpcore";
+			reg = <0x3A0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@3a8000 {
+			label = "image-1-lpcore";
+			reg = <0x3A8000 DT_SIZE_K(32)>;
+		};
+
+		storage_partition: partition@3b0000 {
 			label = "storage";
-			reg = <0x3C0000 DT_SIZE_K(128)>;
+			reg = <0x3B0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@3E0000 {
+		scratch_partition: partition@3e0000 {
 			label = "image-scratch";
-			reg = <0x3E0000 DT_SIZE_K(64)>;
+			reg = <0x3E0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@3F0000 {
-			label = "coredump-partition";
-			reg = <0x3F0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@3ff000 {
+			label = "coredump";
+			reg = <0x3FF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0x3FFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x0_default_8M.dtsi b/dts/common/espressif/partitions_0x0_default_8M.dtsi
index f9b43664b87..8087050765f 100644
--- a/dts/common/espressif/partitions_0x0_default_8M.dtsi
+++ b/dts/common/espressif/partitions_0x0_default_8M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 8MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,32 +12,46 @@
 
 		boot_partition: partition@0 {
 			label = "mcuboot";
-			reg = <0x0 DT_SIZE_K(64)>;
+			reg = <0x0 DT_SIZE_K(128)>;
 		};
 
 		slot0_partition: partition@20000 {
 			label = "image-0";
-			reg = <0x20000 DT_SIZE_K(3904)>;
+			reg = <0x20000 DT_SIZE_K(3840)>;
 		};
 
-		slot1_partition: partition@3F0000 {
+		slot1_partition: partition@3e0000 {
 			label = "image-1";
-			reg = <0x3F0000 DT_SIZE_K(3904)>;
+			reg = <0x3E0000 DT_SIZE_K(3840)>;
 		};
 
-		storage_partition: partition@7C0000 {
+		slot0_lpcore_partition: partition@7a0000 {
+			label = "image-0-lpcore";
+			reg = <0x7A0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@7a8000 {
+			label = "image-1-lpcore";
+			reg = <0x7A8000 DT_SIZE_K(32)>;
+		};
+
+		storage_partition: partition@7b0000 {
 			label = "storage";
-			reg = <0x7C0000 DT_SIZE_K(128)>;
+			reg = <0x7B0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@7E0000 {
-			   label = "image-scratch";
-			   reg = <0x7E0000 DT_SIZE_K(64)>;
+		scratch_partition: partition@7e0000 {
+			label = "image-scratch";
+			reg = <0x7E0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@7F0000 {
-			label = "coredump-partition";
-			reg = <0x7F0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@7ff000 {
+			label = "coredump";
+			reg = <0x7FF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0x7FFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x1000_amp.dtsi b/dts/common/espressif/partitions_0x1000_amp.dtsi
index 13e950cb3cd..8f51c547bf9 100644
--- a/dts/common/espressif/partitions_0x1000_amp.dtsi
+++ b/dts/common/espressif/partitions_0x1000_amp.dtsi
@@ -1,7 +1,7 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- #include <espressif/partitions_0x1000_amp_4M.dtsi>
+#include <espressif/partitions_0x1000_amp_4M.dtsi>
diff --git a/dts/common/espressif/partitions_0x1000_amp_16M.dtsi b/dts/common/espressif/partitions_0x1000_amp_16M.dtsi
index c994ddd762a..3a6e769d919 100644
--- a/dts/common/espressif/partitions_0x1000_amp_16M.dtsi
+++ b/dts/common/espressif/partitions_0x1000_amp_16M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 16MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,42 +12,56 @@
 
 		boot_partition: partition@1000 {
 			label = "mcuboot";
-			reg = <0x1000 DT_SIZE_K(60)>;
+			reg = <0x1000 DT_SIZE_K(124)>;
 		};
 
 		slot0_partition: partition@20000 {
 			label = "image-0";
-			reg = <0x20000 DT_SIZE_K(6080)>;
+			reg = <0x20000 DT_SIZE_K(5952)>;
 		};
 
-		slot0_appcpu_partition: partition@610000 {
-			label = "image-0-appcpu";
-			reg = <0x610000 DT_SIZE_K(1920)>;
+		slot1_partition: partition@5f0000 {
+			label = "image-1";
+			reg = <0x5F0000 DT_SIZE_K(5952)>;
 		};
 
-		slot1_partition: partition@7F0000 {
-			label = "image-1";
-			reg = <0x7F0000 DT_SIZE_K(6080)>;
+		slot0_appcpu_partition: partition@bc0000 {
+			label = "image-0-appcpu";
+			reg = <0xBC0000 DT_SIZE_K(1984)>;
 		};
 
-		slot1_appcpu_partition: partition@DE0000 {
+		slot1_appcpu_partition: partition@db0000 {
 			label = "image-1-appcpu";
-			reg = <0xDE0000 DT_SIZE_K(1920)>;
+			reg = <0xDB0000 DT_SIZE_K(1984)>;
+		};
+
+		slot0_lpcore_partition: partition@fa0000 {
+			label = "image-0-lpcore";
+			reg = <0xFA0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@fa8000 {
+			label = "image-1-lpcore";
+			reg = <0xFA8000 DT_SIZE_K(32)>;
 		};
 
-		storage_partition: partition@FC0000 {
+		storage_partition: partition@fb0000 {
 			label = "storage";
-			reg = <0xFC0000 DT_SIZE_K(128)>;
+			reg = <0xFB0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@FE0000 {
-			   label = "image-scratch";
-			   reg = <0xFE0000 DT_SIZE_K(64)>;
+		scratch_partition: partition@fe0000 {
+			label = "image-scratch";
+			reg = <0xFE0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@FF0000 {
-			label = "coredump-partition";
-			reg = <0xFF0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@fff000 {
+			label = "coredump";
+			reg = <0xFFF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0xFFFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x1000_amp_2M.dtsi b/dts/common/espressif/partitions_0x1000_amp_2M.dtsi
index 1c8e472cb04..aba0c5be16c 100644
--- a/dts/common/espressif/partitions_0x1000_amp_2M.dtsi
+++ b/dts/common/espressif/partitions_0x1000_amp_2M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 2MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,7 +12,7 @@
 
 		boot_partition: partition@1000 {
 			label = "mcuboot";
-			reg = <0x1000 DT_SIZE_K(60)>;
+			reg = <0x1000 DT_SIZE_K(124)>;
 		};
 
 		slot0_partition: partition@20000 {
@@ -21,34 +20,48 @@
 			reg = <0x20000 DT_SIZE_K(576)>;
 		};
 
-		slot0_appcpu_partition: partition@B0000 {
-			label = "image-0-appcpu";
-			reg = <0xB0000 DT_SIZE_K(256)>;
+		slot1_partition: partition@b0000 {
+			label = "image-1";
+			reg = <0xB0000 DT_SIZE_K(576)>;
 		};
 
-		slot1_partition: partition@F0000 {
-			label = "image-1";
-			reg = <0xF0000 DT_SIZE_K(576)>;
+		slot0_appcpu_partition: partition@140000 {
+			label = "image-0-appcpu";
+			reg = <0x140000 DT_SIZE_K(192)>;
 		};
 
-		slot1_appcpu_partition: partition@180000 {
+		slot1_appcpu_partition: partition@170000 {
 			label = "image-1-appcpu";
-			reg = <0x180000 DT_SIZE_K(256)>;
+			reg = <0x170000 DT_SIZE_K(192)>;
+		};
+
+		slot0_lpcore_partition: partition@1a0000 {
+			label = "image-0-lpcore";
+			reg = <0x1A0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@1a8000 {
+			label = "image-1-lpcore";
+			reg = <0x1A8000 DT_SIZE_K(32)>;
 		};
 
-		storage_partition: partition@1C0000 {
+		storage_partition: partition@1b0000 {
 			label = "storage";
-			reg = <0x1C0000 DT_SIZE_K(128)>;
+			reg = <0x1B0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@1E0000 {
+		scratch_partition: partition@1e0000 {
 			label = "image-scratch";
-			reg = <0x1E0000 DT_SIZE_K(64)>;
+			reg = <0x1E0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@1F0000 {
-			label = "coredump-partition";
-			reg = <0x1F0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@1ff000 {
+			label = "coredump";
+			reg = <0x1FF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0x1FFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x1000_amp_32M.dtsi b/dts/common/espressif/partitions_0x1000_amp_32M.dtsi
index 7006269f994..1863dc11bb8 100644
--- a/dts/common/espressif/partitions_0x1000_amp_32M.dtsi
+++ b/dts/common/espressif/partitions_0x1000_amp_32M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 32MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,42 +12,56 @@
 
 		boot_partition: partition@1000 {
 			label = "mcuboot";
-			reg = <0x1000 DT_SIZE_K(60)>;
+			reg = <0x1000 DT_SIZE_K(124)>;
 		};
 
 		slot0_partition: partition@20000 {
 			label = "image-0";
-			reg = <0x20000 DT_SIZE_K(12352)>;
+			reg = <0x20000 DT_SIZE_K(12096)>;
 		};
 
-		slot0_appcpu_partition: partition@C30000 {
-			label = "image-0-appcpu";
-			reg = <0xC24000 DT_SIZE_K(3840)>;
+		slot1_partition: partition@bf0000 {
+			label = "image-1";
+			reg = <0xBF0000 DT_SIZE_K(12096)>;
 		};
 
-		slot1_partition: partition@FF0000 {
-			label = "image-1";
-			reg = <0xFF0000 DT_SIZE_K(12352)>;
+		slot0_appcpu_partition: partition@17c0000 {
+			label = "image-0-appcpu";
+			reg = <0x17C0000 DT_SIZE_K(4032)>;
 		};
 
-		slot1_appcpu_partition: partition@1C00000 {
+		slot1_appcpu_partition: partition@1bb0000 {
 			label = "image-1-appcpu";
-			reg = <0x1C00000 DT_SIZE_K(3840)>;
+			reg = <0x1BB0000 DT_SIZE_K(4032)>;
+		};
+
+		slot0_lpcore_partition: partition@1fa0000 {
+			label = "image-0-lpcore";
+			reg = <0x1FA0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@1fa8000 {
+			label = "image-1-lpcore";
+			reg = <0x1FA8000 DT_SIZE_K(32)>;
 		};
 
-		storage_partition: partition@1FC0000 {
+		storage_partition: partition@1fb0000 {
 			label = "storage";
-			reg = <0x1FC0000 DT_SIZE_K(128)>;
+			reg = <0x1FB0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@1FE0000 {
-			   label = "image-scratch";
-			   reg = <0x1FE0000 DT_SIZE_K(64)>;
+		scratch_partition: partition@1fe0000 {
+			label = "image-scratch";
+			reg = <0x1FE0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@1FF0000 {
-			label = "coredump-partition";
-			reg = <0x1FF0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@1fff000 {
+			label = "coredump";
+			reg = <0x1FFF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0x1FFFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x1000_amp_4M.dtsi b/dts/common/espressif/partitions_0x1000_amp_4M.dtsi
index 1747b52d523..84bfe8d2e37 100644
--- a/dts/common/espressif/partitions_0x1000_amp_4M.dtsi
+++ b/dts/common/espressif/partitions_0x1000_amp_4M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 4MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,7 +12,7 @@
 
 		boot_partition: partition@1000 {
 			label = "mcuboot";
-			reg = <0x1000 DT_SIZE_K(60)>;
+			reg = <0x1000 DT_SIZE_K(124)>;
 		};
 
 		slot0_partition: partition@20000 {
@@ -21,34 +20,48 @@
 			reg = <0x20000 DT_SIZE_K(1344)>;
 		};
 
-		slot0_appcpu_partition: partition@170000 {
-			label = "image-0-appcpu";
-			reg = <0x170000 DT_SIZE_K(512)>;
+		slot1_partition: partition@170000 {
+			label = "image-1";
+			reg = <0x170000 DT_SIZE_K(1344)>;
 		};
 
-		slot1_partition: partition@1F0000 {
-			label = "image-1";
-			reg = <0x1F0000 DT_SIZE_K(1344)>;
+		slot0_appcpu_partition: partition@2c0000 {
+			label = "image-0-appcpu";
+			reg = <0x2C0000 DT_SIZE_K(448)>;
 		};
 
-		slot1_appcpu_partition: partition@340000 {
+		slot1_appcpu_partition: partition@330000 {
 			label = "image-1-appcpu";
-			reg = <0x340000 DT_SIZE_K(512)>;
+			reg = <0x330000 DT_SIZE_K(448)>;
+		};
+
+		slot0_lpcore_partition: partition@3a0000 {
+			label = "image-0-lpcore";
+			reg = <0x3A0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@3a8000 {
+			label = "image-1-lpcore";
+			reg = <0x3A8000 DT_SIZE_K(32)>;
 		};
 
-		storage_partition: partition@3C0000 {
+		storage_partition: partition@3b0000 {
 			label = "storage";
-			reg = <0x3C0000 DT_SIZE_K(128)>;
+			reg = <0x3B0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@3E0000 {
-			   label = "image-scratch";
-			   reg = <0x3E0000 DT_SIZE_K(64)>;
+		scratch_partition: partition@3e0000 {
+			label = "image-scratch";
+			reg = <0x3E0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@3F0000 {
-			label = "coredump-partition";
-			reg = <0x3F0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@3ff000 {
+			label = "coredump";
+			reg = <0x3FF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0x3FFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x1000_amp_8M.dtsi b/dts/common/espressif/partitions_0x1000_amp_8M.dtsi
index afdcdbc2840..87c94061d40 100644
--- a/dts/common/espressif/partitions_0x1000_amp_8M.dtsi
+++ b/dts/common/espressif/partitions_0x1000_amp_8M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 8MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,42 +12,56 @@
 
 		boot_partition: partition@1000 {
 			label = "mcuboot";
-			reg = <0x1000 DT_SIZE_K(60)>;
+			reg = <0x1000 DT_SIZE_K(124)>;
 		};
 
 		slot0_partition: partition@20000 {
 			label = "image-0";
-			reg = <0x20000 DT_SIZE_K(3136)>;
+			reg = <0x20000 DT_SIZE_K(2880)>;
 		};
 
-		slot0_appcpu_partition: partition@330000 {
-			label = "image-0-appcpu";
-			reg = <0x330000 DT_SIZE_K(768)>;
+		slot1_partition: partition@2f0000 {
+			label = "image-1";
+			reg = <0x2F0000 DT_SIZE_K(2880)>;
 		};
 
-		slot1_partition: partition@3F0000 {
-			label = "image-1";
-			reg = <0x3F0000 DT_SIZE_K(3136)>;
+		slot0_appcpu_partition: partition@5c0000 {
+			label = "image-0-appcpu";
+			reg = <0x5C0000 DT_SIZE_K(960)>;
 		};
 
-		slot1_appcpu_partition: partition@700000 {
+		slot1_appcpu_partition: partition@6b0000 {
 			label = "image-1-appcpu";
-			reg = <0x700000 DT_SIZE_K(768)>;
+			reg = <0x6B0000 DT_SIZE_K(960)>;
+		};
+
+		slot0_lpcore_partition: partition@7a0000 {
+			label = "image-0-lpcore";
+			reg = <0x7A0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@7a8000 {
+			label = "image-1-lpcore";
+			reg = <0x7A8000 DT_SIZE_K(32)>;
 		};
 
-		storage_partition: partition@7C0000 {
+		storage_partition: partition@7b0000 {
 			label = "storage";
-			reg = <0x7C0000 DT_SIZE_K(128)>;
+			reg = <0x7B0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@7E0000 {
-			   label = "image-scratch";
-			   reg = <0x7E0000 DT_SIZE_K(64)>;
+		scratch_partition: partition@7e0000 {
+			label = "image-scratch";
+			reg = <0x7E0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@7F0000 {
-			label = "coredump-partition";
-			reg = <0x7F0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@7ff000 {
+			label = "coredump";
+			reg = <0x7FF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0x7FFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x1000_default.dtsi b/dts/common/espressif/partitions_0x1000_default.dtsi
index 834bb6f7368..54fa797e6bc 100644
--- a/dts/common/espressif/partitions_0x1000_default.dtsi
+++ b/dts/common/espressif/partitions_0x1000_default.dtsi
@@ -1,7 +1,7 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- #include <espressif/partitions_0x1000_default_4M.dtsi>
+#include <espressif/partitions_0x1000_default_4M.dtsi>
diff --git a/dts/common/espressif/partitions_0x1000_default_16M.dtsi b/dts/common/espressif/partitions_0x1000_default_16M.dtsi
index 84663ecafd1..8150760ffbe 100644
--- a/dts/common/espressif/partitions_0x1000_default_16M.dtsi
+++ b/dts/common/espressif/partitions_0x1000_default_16M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 16MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,32 +12,46 @@
 
 		boot_partition: partition@1000 {
 			label = "mcuboot";
-			reg = <0x1000 DT_SIZE_K(60)>;
+			reg = <0x1000 DT_SIZE_K(124)>;
 		};
 
 		slot0_partition: partition@20000 {
 			label = "image-0";
-			reg = <0x20000 DT_SIZE_K(8000)>;
+			reg = <0x20000 DT_SIZE_K(7936)>;
 		};
 
-		slot1_partition: partition@7F0000 {
+		slot1_partition: partition@7e0000 {
 			label = "image-1";
-			reg = <0x7F0000 DT_SIZE_K(8000)>;
+			reg = <0x7E0000 DT_SIZE_K(7936)>;
 		};
 
-		storage_partition: partition@FC0000 {
+		slot0_lpcore_partition: partition@fa0000 {
+			label = "image-0-lpcore";
+			reg = <0xFA0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@fa8000 {
+			label = "image-1-lpcore";
+			reg = <0xFA8000 DT_SIZE_K(32)>;
+		};
+
+		storage_partition: partition@fb0000 {
 			label = "storage";
-			reg = <0xFC0000 DT_SIZE_K(128)>;
+			reg = <0xFB0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@FE0000 {
-			   label = "image-scratch";
-			   reg = <0xFE0000 DT_SIZE_K(64)>;
+		scratch_partition: partition@fe0000 {
+			label = "image-scratch";
+			reg = <0xFE0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@FF0000 {
-			label = "coredump-partition";
-			reg = <0xFF0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@fff000 {
+			label = "coredump";
+			reg = <0xFFF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0xFFFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x1000_default_2M.dtsi b/dts/common/espressif/partitions_0x1000_default_2M.dtsi
index 08b1caf3044..b32f686dd5b 100644
--- a/dts/common/espressif/partitions_0x1000_default_2M.dtsi
+++ b/dts/common/espressif/partitions_0x1000_default_2M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 2MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,32 +12,46 @@
 
 		boot_partition: partition@1000 {
 			label = "mcuboot";
-			reg = <0x1000 DT_SIZE_K(60)>;
+			reg = <0x1000 DT_SIZE_K(124)>;
 		};
 
 		slot0_partition: partition@20000 {
 			label = "image-0";
-			reg = <0x20000 DT_SIZE_K(832)>;
+			reg = <0x20000 DT_SIZE_K(768)>;
 		};
 
-		slot1_partition: partition@F0000 {
+		slot1_partition: partition@e0000 {
 			label = "image-1";
-			reg = <0xF0000 DT_SIZE_K(832)>;
+			reg = <0xE0000 DT_SIZE_K(768)>;
 		};
 
-		storage_partition: partition@1C0000 {
+		slot0_lpcore_partition: partition@1a0000 {
+			label = "image-0-lpcore";
+			reg = <0x1A0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@1a8000 {
+			label = "image-1-lpcore";
+			reg = <0x1A8000 DT_SIZE_K(32)>;
+		};
+
+		storage_partition: partition@1b0000 {
 			label = "storage";
-			reg = <0x1C0000 DT_SIZE_K(128)>;
+			reg = <0x1B0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@1E0000 {
-			   label = "image-scratch";
-			   reg = <0x1E0000 DT_SIZE_K(64)>;
+		scratch_partition: partition@1e0000 {
+			label = "image-scratch";
+			reg = <0x1E0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@1F0000 {
-			label = "coredump-partition";
-			reg = <0x1F0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@1ff000 {
+			label = "coredump";
+			reg = <0x1FF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0x1FFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x1000_default_32M.dtsi b/dts/common/espressif/partitions_0x1000_default_32M.dtsi
index 4e7cc4511bb..4139d18976d 100644
--- a/dts/common/espressif/partitions_0x1000_default_32M.dtsi
+++ b/dts/common/espressif/partitions_0x1000_default_32M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 32MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,32 +12,46 @@
 
 		boot_partition: partition@1000 {
 			label = "mcuboot";
-			reg = <0x1000 DT_SIZE_K(60)>;
+			reg = <0x1000 DT_SIZE_K(124)>;
 		};
 
 		slot0_partition: partition@20000 {
 			label = "image-0";
-			reg = <0x20000 DT_SIZE_K(16192)>;
+			reg = <0x20000 DT_SIZE_K(16128)>;
 		};
 
-		slot1_partition: partition@FF0000 {
+		slot1_partition: partition@fe0000 {
 			label = "image-1";
-			reg = <0xFF0000 DT_SIZE_K(16192)>;
+			reg = <0xFE0000 DT_SIZE_K(16128)>;
 		};
 
-		storage_partition: partition@1FC0000 {
+		slot0_lpcore_partition: partition@1fa0000 {
+			label = "image-0-lpcore";
+			reg = <0x1FA0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@1fa8000 {
+			label = "image-1-lpcore";
+			reg = <0x1FA8000 DT_SIZE_K(32)>;
+		};
+
+		storage_partition: partition@1fb0000 {
 			label = "storage";
-			reg = <0x1FC0000 DT_SIZE_K(128)>;
+			reg = <0x1FB0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@1FE0000 {
-			   label = "image-scratch";
-			   reg = <0x1FE0000 DT_SIZE_K(64)>;
+		scratch_partition: partition@1fe0000 {
+			label = "image-scratch";
+			reg = <0x1FE0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@1FF0000 {
-			label = "coredump-partition";
-			reg = <0x1FF0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@1fff000 {
+			label = "coredump";
+			reg = <0x1FFF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0x1FFFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x1000_default_4M.dtsi b/dts/common/espressif/partitions_0x1000_default_4M.dtsi
index bf5d09fdc48..61282f2ae09 100644
--- a/dts/common/espressif/partitions_0x1000_default_4M.dtsi
+++ b/dts/common/espressif/partitions_0x1000_default_4M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 4MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,32 +12,46 @@
 
 		boot_partition: partition@1000 {
 			label = "mcuboot";
-			reg = <0x1000 DT_SIZE_K(60)>;
+			reg = <0x1000 DT_SIZE_K(124)>;
 		};
 
 		slot0_partition: partition@20000 {
 			label = "image-0";
-			reg = <0x20000 DT_SIZE_K(1856)>;
+			reg = <0x20000 DT_SIZE_K(1792)>;
 		};
 
-		slot1_partition: partition@1F0000 {
+		slot1_partition: partition@1e0000 {
 			label = "image-1";
-			reg = <0x1F0000 DT_SIZE_K(1856)>;
+			reg = <0x1E0000 DT_SIZE_K(1792)>;
 		};
 
-		storage_partition: partition@3C0000 {
+		slot0_lpcore_partition: partition@3a0000 {
+			label = "image-0-lpcore";
+			reg = <0x3A0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@3a8000 {
+			label = "image-1-lpcore";
+			reg = <0x3A8000 DT_SIZE_K(32)>;
+		};
+
+		storage_partition: partition@3b0000 {
 			label = "storage";
-			reg = <0x3C0000 DT_SIZE_K(128)>;
+			reg = <0x3B0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@3E0000 {
-			   label = "image-scratch";
-			   reg = <0x3E0000 DT_SIZE_K(64)>;
+		scratch_partition: partition@3e0000 {
+			label = "image-scratch";
+			reg = <0x3E0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@3F0000 {
-			label = "coredump-partition";
-			reg = <0x3F0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@3ff000 {
+			label = "coredump";
+			reg = <0x3FF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0x3FFFFF
+ */
diff --git a/dts/common/espressif/partitions_0x1000_default_8M.dtsi b/dts/common/espressif/partitions_0x1000_default_8M.dtsi
index eaf0511cf27..301644b6bef 100644
--- a/dts/common/espressif/partitions_0x1000_default_8M.dtsi
+++ b/dts/common/espressif/partitions_0x1000_default_8M.dtsi
@@ -1,10 +1,9 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
- /* 8MB flash partition table */
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
@@ -13,32 +12,46 @@
 
 		boot_partition: partition@1000 {
 			label = "mcuboot";
-			reg = <0x1000 DT_SIZE_K(60)>;
+			reg = <0x1000 DT_SIZE_K(124)>;
 		};
 
 		slot0_partition: partition@20000 {
 			label = "image-0";
-			reg = <0x20000 DT_SIZE_K(3904)>;
+			reg = <0x20000 DT_SIZE_K(3840)>;
 		};
 
-		slot1_partition: partition@3F0000 {
+		slot1_partition: partition@3e0000 {
 			label = "image-1";
-			reg = <0x3F0000 DT_SIZE_K(3904)>;
+			reg = <0x3E0000 DT_SIZE_K(3840)>;
 		};
 
-		storage_partition: partition@7C0000 {
+		slot0_lpcore_partition: partition@7a0000 {
+			label = "image-0-lpcore";
+			reg = <0x7A0000 DT_SIZE_K(32)>;
+		};
+
+		slot1_lpcore_partition: partition@7a8000 {
+			label = "image-1-lpcore";
+			reg = <0x7A8000 DT_SIZE_K(32)>;
+		};
+
+		storage_partition: partition@7b0000 {
 			label = "storage";
-			reg = <0x7C0000 DT_SIZE_K(128)>;
+			reg = <0x7B0000 DT_SIZE_K(192)>;
 		};
 
-		scratch_partition: partition@7E0000 {
-			   label = "image-scratch";
-			   reg = <0x7E0000 DT_SIZE_K(64)>;
+		scratch_partition: partition@7e0000 {
+			label = "image-scratch";
+			reg = <0x7E0000 DT_SIZE_K(124)>;
 		};
 
-		coredump_partition: partition@7F0000 {
-			label = "coredump-partition";
-			reg = <0x7F0000 DT_SIZE_K(4)>;
+		coredump_partition: partition@7ff000 {
+			label = "coredump";
+			reg = <0x7FF000 DT_SIZE_K(4)>;
 		};
 	};
 };
+
+/* Remaining flash size is 0kB
+ * Last used address is 0x7FFFFF
+ */
diff --git a/dts/common/nordic/nrf52840_partition.dtsi b/dts/common/nordic/nrf52840_partition.dtsi
index 8852ab5b15a..1fa90a3ed71 100644
--- a/dts/common/nordic/nrf52840_partition.dtsi
+++ b/dts/common/nordic/nrf52840_partition.dtsi
@@ -22,13 +22,15 @@
 			label = "mcuboot";
 			reg = <0x00000000 0x0000C000>;
 		};
+
 		slot0_partition: partition@c000 {
 			label = "image-0";
-			reg = <0x0000C000 0x00077000>;
+			reg = <0x0000C000 0x00076000>;
 		};
-		slot1_partition: partition@83000 {
+
+		slot1_partition: partition@82000 {
 			label = "image-1";
-			reg = <0x00083000 0x00075000>;
+			reg = <0x00082000 0x00076000>;
 		};
 
 		/*
diff --git a/dts/common/nordic/nrf52840_partition_uf2_sdv6.dtsi b/dts/common/nordic/nrf52840_partition_uf2_sdv6.dtsi
index 37387fd782f..9c12d7f82f5 100644
--- a/dts/common/nordic/nrf52840_partition_uf2_sdv6.dtsi
+++ b/dts/common/nordic/nrf52840_partition_uf2_sdv6.dtsi
@@ -35,6 +35,7 @@
 			read-only;
 			reg = <0x00000000 0x00026000>;
 		};
+
 		code_partition: partition@26000 {
 			label = "Application";
 			reg = <0x00026000 0x000C6000>;
diff --git a/dts/common/nordic/nrf52840_partition_uf2_sdv7.dtsi b/dts/common/nordic/nrf52840_partition_uf2_sdv7.dtsi
index e6aaf73ca14..c7f5e0d5e20 100644
--- a/dts/common/nordic/nrf52840_partition_uf2_sdv7.dtsi
+++ b/dts/common/nordic/nrf52840_partition_uf2_sdv7.dtsi
@@ -33,6 +33,7 @@
 			read-only;
 			reg = <0x00000000 0x00027000>;
 		};
+
 		code_partition: partition@27000 {
 			label = "Application";
 			reg = <0x00027000 0x000C5000>;
diff --git a/dts/common/nordic/nrf5340_cpuapp_partition.dtsi b/dts/common/nordic/nrf5340_cpuapp_partition.dtsi
index b1a1095b355..621c35596e3 100644
--- a/dts/common/nordic/nrf5340_cpuapp_partition.dtsi
+++ b/dts/common/nordic/nrf5340_cpuapp_partition.dtsi
@@ -33,34 +33,42 @@
 			label = "mcuboot";
 			reg = <0x00000000 0x10000>;
 		};
+
 		slot0_partition: partition@10000 {
 			label = "image-0";
 			reg = <0x00010000 0x40000>;
 		};
+
 		slot0_ns_partition: partition@50000 {
 			label = "image-0-nonsecure";
 			reg = <0x00050000 0x30000>;
 		};
+
 		slot1_partition: partition@80000 {
 			label = "image-1";
 			reg = <0x00080000 0x40000>;
 		};
+
 		slot1_ns_partition: partition@c0000 {
 			label = "image-1-nonsecure";
 			reg = <0x000c0000 0x30000>;
 		};
+
 		tfm_ps_partition: partition@f0000 {
 			label = "tfm-ps";
 			reg = <0x000f0000 0x00004000>;
 		};
+
 		tfm_its_partition: partition@f4000 {
 			label = "tfm-its";
 			reg = <0x000f4000 0x00002000>;
 		};
+
 		tfm_otp_partition: partition@f6000 {
 			label = "tfm-otp";
 			reg = <0x000f6000 0x00002000>;
 		};
+
 		storage_partition: partition@f8000 {
 			label = "storage";
 			reg = <0x000f8000 0x00008000>;
diff --git a/dts/common/nordic/nrf54h20.dtsi b/dts/common/nordic/nrf54h20.dtsi
index 7fbfa94722d..8b7762f07e6 100644
--- a/dts/common/nordic/nrf54h20.dtsi
+++ b/dts/common/nordic/nrf54h20.dtsi
@@ -394,7 +394,6 @@
 				interrupts = <40 NRF_DEFAULT_IRQ_PRIORITY>;
 				clocks = <&hfxo>;
 				max-bit-width = <32>;
-				max-frequency = <DT_FREQ_M(32)>;
 				prescaler = <0>;
 			};
 
@@ -406,7 +405,6 @@
 				interrupts = <41 NRF_DEFAULT_IRQ_PRIORITY>;
 				clocks = <&hfxo>;
 				max-bit-width = <32>;
-				max-frequency = <DT_FREQ_M(32)>;
 				prescaler = <0>;
 			};
 
@@ -418,7 +416,6 @@
 				interrupts = <42 NRF_DEFAULT_IRQ_PRIORITY>;
 				clocks = <&hfxo>;
 				max-bit-width = <32>;
-				max-frequency = <DT_FREQ_M(32)>;
 				prescaler = <0>;
 			};
 
@@ -620,7 +617,8 @@
 				reg = <0x8d8000 0x400>, <0x2fbef800 0x800>, <0x2fbe8000 0x7800>;
 				reg-names = "wrapper", "m_can", "message_ram";
 				interrupts = <216 NRF_DEFAULT_IRQ_PRIORITY>;
-				clocks = <&canpll>;
+				clocks = <&canpll>, <&hsfll120>;
+				clock-names = "auxpll", "hsfll";
 				power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>;
 				bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
 				status = "disabled";
@@ -641,7 +639,6 @@
 				interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>;
 				power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>;
 				max-bit-width = <32>;
-				max-frequency = <DT_FREQ_M(320)>;
 				clocks = <&hsfll120>;
 				prescaler = <0>;
 			};
@@ -654,7 +651,6 @@
 				interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>;
 				power-domains = <&gpd NRF_GPD_FAST_ACTIVE1>;
 				max-bit-width = <32>;
-				max-frequency = <DT_FREQ_M(320)>;
 				clocks = <&hsfll120>;
 				prescaler = <0>;
 			};
diff --git a/dts/common/nordic/nrf54l09.dtsi b/dts/common/nordic/nrf54l09.dtsi
index a5b37fb4133..ac780378837 100644
--- a/dts/common/nordic/nrf54l09.dtsi
+++ b/dts/common/nordic/nrf54l09.dtsi
@@ -30,6 +30,7 @@
 			clocks = <&hfpll>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+
 			itm: itm@e0000000 {
 				compatible = "arm,armv8m-itm";
 				reg = <0xe0000000 0x1000>;
diff --git a/dts/common/nordic/nrf54l20.dtsi b/dts/common/nordic/nrf54l20.dtsi
index 5ac567e631f..741fe1e6b17 100644
--- a/dts/common/nordic/nrf54l20.dtsi
+++ b/dts/common/nordic/nrf54l20.dtsi
@@ -30,6 +30,7 @@
 			clocks = <&hfpll>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+
 			itm: itm@e0000000 {
 				compatible = "arm,armv8m-itm";
 				reg = <0xe0000000 0x1000>;
@@ -251,6 +252,7 @@
 				ieee802154-supported;
 				ble-2mbps-supported;
 				ble-coded-phy-supported;
+				cs-supported;
 
 				ieee802154: ieee802154 {
 					compatible = "nordic,nrf-ieee802154";
diff --git a/dts/common/nordic/nrf54l_05_10_15.dtsi b/dts/common/nordic/nrf54l_05_10_15.dtsi
index 1f2c82c08fa..6ea1a1f2976 100644
--- a/dts/common/nordic/nrf54l_05_10_15.dtsi
+++ b/dts/common/nordic/nrf54l_05_10_15.dtsi
@@ -30,6 +30,7 @@
 			clocks = <&hfpll>;
 			#address-cells = <1>;
 			#size-cells = <1>;
+
 			itm: itm@e0000000 {
 				compatible = "arm,armv8m-itm";
 				reg = <0xe0000000 0x1000>;
diff --git a/dts/common/nordic/nrf91xx_partition.dtsi b/dts/common/nordic/nrf91xx_partition.dtsi
index 27557da0498..85d878ccdb9 100644
--- a/dts/common/nordic/nrf91xx_partition.dtsi
+++ b/dts/common/nordic/nrf91xx_partition.dtsi
@@ -33,34 +33,42 @@
 			label = "mcuboot";
 			reg = <0x00000000 0x10000>;
 		};
+
 		slot0_partition: partition@10000 {
 			label = "image-0";
 			reg = <0x00010000 0x40000>;
 		};
+
 		slot0_ns_partition: partition@50000 {
 			label = "image-0-nonsecure";
 			reg = <0x00050000 0x30000>;
 		};
+
 		slot1_partition: partition@80000 {
 			label = "image-1";
 			reg = <0x00080000 0x40000>;
 		};
+
 		slot1_ns_partition: partition@c0000 {
 			label = "image-1-nonsecure";
 			reg = <0x000c0000 0x30000>;
 		};
+
 		tfm_ps_partition: partition@f0000 {
 			label = "tfm-ps";
 			reg = <0x000f0000 0x00004000>;
 		};
+
 		tfm_its_partition: partition@f4000 {
 			label = "tfm-its";
 			reg = <0x000f4000 0x00002000>;
 		};
+
 		tfm_otp_partition: partition@f6000 {
 			label = "tfm-otp";
 			reg = <0x000f6000 0x00002000>;
 		};
+
 		storage_partition: partition@f8000 {
 			label = "storage";
 			reg = <0x000f8000 0x00008000>;
diff --git a/dts/common/nordic/nrf9280.dtsi b/dts/common/nordic/nrf9280.dtsi
index ae3a59c6c0c..06e0a3a1514 100644
--- a/dts/common/nordic/nrf9280.dtsi
+++ b/dts/common/nordic/nrf9280.dtsi
@@ -445,26 +445,6 @@
 				global-domain-id = <12>;
 			};
 
-			can120: can@8d8000 {
-				compatible = "nordic,nrf-can";
-				reg = <0x8d8000 0x400>, <0x2fbef800 0x800>, <0x2fbe8000 0x7800>;
-				reg-names = "wrapper", "m_can", "message_ram";
-				interrupts = <216 NRF_DEFAULT_IRQ_PRIORITY>;
-				clocks = <&canpll>;
-				bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
-				status = "disabled";
-			};
-
-			can121: can@8db000 {
-				compatible = "nordic,nrf-can";
-				reg = <0x8db000 0x400>, <0x2fbf7800 0x800>, <0x2fbf0000 0x7800>;
-				reg-names = "wrapper", "m_can", "message_ram";
-				interrupts = <219 NRF_DEFAULT_IRQ_PRIORITY>;
-				clocks = <&canpll>;
-				bosch,mram-cfg = <0x0 28 8 3 3 0 1 1>;
-				status = "disabled";
-			};
-
 			dppic120: dppic@8e1000 {
 				compatible = "nordic,nrf-dppic-global";
 				reg = <0x8e1000 0x1000>;
diff --git a/dts/riscv/andes/andes_v5_ae350.dtsi b/dts/riscv/andes/andes_v5_ae350.dtsi
index 538de399af9..082b599dd31 100644
--- a/dts/riscv/andes/andes_v5_ae350.dtsi
+++ b/dts/riscv/andes/andes_v5_ae350.dtsi
@@ -215,8 +215,8 @@
 		};
 
 		mtimer: timer@e6000000 {
-			compatible = "andestech,machine-timer";
-			reg = <0xe6000000 0x10>;
+			compatible = "riscv,machine-timer";
+			reg = <0xe6000000 0x8 0xe6000008 0x8>;
 			interrupts-extended = <&cpu0_intc 7 &cpu1_intc 7
 					       &cpu2_intc 7 &cpu3_intc 7
 					       &cpu4_intc 7 &cpu5_intc 7
diff --git a/dts/riscv/bouffalolab/bl60x.dtsi b/dts/riscv/bouffalolab/bl60x.dtsi
new file mode 100644
index 00000000000..7ec4c90802f
--- /dev/null
+++ b/dts/riscv/bouffalolab/bl60x.dtsi
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2021-2025 ATL Electronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <freq.h>
+#include <mem.h>
+#include <dt-bindings/pinctrl/bl60x-pinctrl.h>
+#include <dt-bindings/pinctrl/bflb-common-pinctrl.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "sifive,e24", "riscv";
+			reg = <0>;
+			riscv,isa = "rv32imafcb";
+			hardware-exec-breakpoint-count = <4>;
+			status = "okay";
+
+			ictrl: interrupt-controller {
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		clic: clic@2000000 {
+			compatible = "sifive,clint0";
+			reg = <0x2000000 0x10000>;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+
+			interrupt-controller;
+			interrupts-extended = <&ictrl 3 &ictrl 7 &ictrl 11 &ictrl 12>;
+			interrupt-names = "msip", /* Machine Software Interrupt */
+					  "mtip", /* Machine Timer interrupt    */
+					  "meip", /* Machine External Interrupt */
+					  "csip"; /* CLIC Software Interrupt    */
+		};
+
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			reg = <0x200bff8 0x8 0x2004000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+
+			interrupts-extended = <&ictrl 7>;
+		};
+
+		pinctrl: pin-controller@40000000 {
+			compatible = "bflb,pinctrl";
+			reg = <0x40000000 0x1000>;
+			ranges = <0x40000000 0x40000000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "okay";
+
+			glb: gpio@40000000 {
+				compatible = "bflb,gpio";
+				reg = <0x40000000 0x1000>;
+				#gpio-cells = <2>;
+				#bflb,pin-cells = <2>;
+				status = "disabled";
+
+				gpio-controller;
+				interrupts = <1 0>;
+				interrupt-parent = <&ictrl>;
+			};
+		};
+
+		uart0: uart@4000a000 {
+			compatible = "bflb,uart";
+			reg = <0x4000a000 0x100>;
+			peripheral-id = <0>;
+			interrupts = <29 0>;
+			interrupt-parent = <&ictrl>;
+			status = "disabled";
+		};
+
+		uart1: uart@4000a100 {
+			compatible = "bflb,uart";
+			reg = <0x4000a100 0x100>;
+			peripheral-id = <1>;
+			interrupts = <30 0>;
+			interrupt-parent = <&ictrl>;
+			status = "disabled";
+		};
+
+		spi0: spi@4000a200 {
+			compatible = "bflb,spi";
+			reg = <0x4000a200 0x100>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			peripheral-id = <0>;
+			interrupts = <27 0>;
+			interrupt-parent = <&ictrl>;
+		};
+
+		spi1: spi@4000b000 {
+			compatible = "bflb,qspi";
+			reg = <0x4000b000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+
+			peripheral-id = <0>;
+			interrupts = <23 0>;
+			interrupt-parent = <&ictrl>;
+		};
+
+		retram: memory@40010000 {
+			compatible = "mmio-sram";
+			reg = <0x40010000 DT_SIZE_K(4)>;
+		};
+
+		itcm: itcm@22010000 {
+			compatible = "zephyr,memory-region", "sifive,dtim0";
+			reg = <0x22010000 DT_SIZE_K(16)>;
+			zephyr,memory-region = "ITCM";
+		};
+
+		dtcm: dtcm@42014000 {
+			compatible = "zephyr,memory-region", "sifive,dtim0";
+			reg = <0x42014000 DT_SIZE_K(48)>;
+			zephyr,memory-region = "DTCM";
+		};
+
+		sram0: memory@42020000 {
+			compatible = "mmio-sram";
+			reg = <0x42020000 DT_SIZE_K(64)>;
+		};
+
+		sram1: memory@42030000 {
+			compatible = "mmio-sram";
+			reg = <0x42030000 DT_SIZE_K(112)>;
+		};
+	};
+};
diff --git a/dts/riscv/efinix/sapphire_soc.dtsi b/dts/riscv/efinix/sapphire_soc.dtsi
index 72092a4bc93..faf60931d64 100644
--- a/dts/riscv/efinix/sapphire_soc.dtsi
+++ b/dts/riscv/efinix/sapphire_soc.dtsi
@@ -65,6 +65,13 @@
 			reg = <0xf8b00000 0x10000>;
 		};
 
+		mtimer: timer@f8b0bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&hlic 7>;
+			reg = <0xf8b0bff8 0x8 0xf8b04000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
+
 		timer0: timer@e0002800 {
 			compatible = "efinix,sapphire-timer0";
 			reg = <0xe0002800 0x40>;
diff --git a/dts/riscv/espressif/esp32c2/esp32c2_common.dtsi b/dts/riscv/espressif/esp32c2/esp32c2_common.dtsi
index 4559e87b2a8..1d8a34e471d 100644
--- a/dts/riscv/espressif/esp32c2/esp32c2_common.dtsi
+++ b/dts/riscv/espressif/esp32c2/esp32c2_common.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -215,5 +215,15 @@
 			reg = <0x60040058 0x4>;
 			status = "disabled";
 		};
+
+		adc0: adc@60040000 {
+			compatible = "espressif,esp32-adc";
+			reg = <0x60040000 4>;
+			clocks = <&rtc ESP32_SARADC_MODULE>;
+			unit = <1>;
+			channel-count = <5>;
+			#io-channel-cells = <1>;
+			status = "disabled";
+		};
 	};
 };
diff --git a/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi b/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi
index 4217777e5aa..7c8eee5e99a 100644
--- a/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi
+++ b/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi
@@ -304,21 +304,13 @@
 		adc0: adc@60040000 {
 			compatible = "espressif,esp32-adc";
 			reg = <0x60040000 4>;
+			clocks = <&rtc ESP32_SARADC_MODULE>;
 			unit = <1>;
 			channel-count = <5>;
 			#io-channel-cells = <1>;
 			status = "disabled";
 		};
 
-		adc1: adc@60040004 {
-			compatible = "espressif,esp32-adc";
-			reg = <0x60040004 4>;
-			unit = <2>;
-			channel-count = <2>;
-			#io-channel-cells = <1>;
-			status = "disabled";
-		};
-
 		dma: dma@6003f000 {
 			compatible = "espressif,esp32-gdma";
 			reg = <0x6003f000 DT_SIZE_K(4)>;
diff --git a/dts/riscv/espressif/esp32c6/esp32c6_common.dtsi b/dts/riscv/espressif/esp32c6/esp32c6_common.dtsi
index d8049584fb1..840ca3ba7b8 100644
--- a/dts/riscv/espressif/esp32c6/esp32c6_common.dtsi
+++ b/dts/riscv/espressif/esp32c6/esp32c6_common.dtsi
@@ -1,10 +1,11 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <mem.h>
 #include <freq.h>
+#include <zephyr/dt-bindings/adc/adc.h>
 #include <zephyr/dt-bindings/gpio/gpio.h>
 #include <zephyr/dt-bindings/i2c/i2c.h>
 #include <zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h>
@@ -15,6 +16,10 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 
+	aliases {
+		die-temp0 = &coretemp;
+	};
+
 	chosen {
 		zephyr,entropy = &trng0;
 		zephyr,flash-controller = &flash;
@@ -75,9 +80,15 @@
 		};
 
 		sramlp: memory@50000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
 			compatible = "zephyr,memory-region", "mmio-sram";
 			reg = <0x50000000 DT_SIZE_K(16)>;
 			zephyr,memory-region = "SRAMLP ";
+
+			shmlp: memory@0 {
+				reg = <0x0 0x10>;
+			};
 		};
 
 		intc: interrupt-controller@60010000 {
@@ -188,6 +199,23 @@
 			};
 		};
 
+		coretemp: coretemp@6000e058 {
+			compatible = "espressif,esp32-temp";
+			friendly-name = "coretemp";
+			reg = <0x6000E058 0x4>;
+			status = "disabled";
+		};
+
+		adc0: adc@6000e000 {
+			compatible = "espressif,esp32-adc";
+			reg = <0x6000E000 4>;
+			clocks = <&rtc ESP32_SARADC_MODULE>;
+			unit = <1>;
+			channel-count = <7>;
+			#io-channel-cells = <1>;
+			status = "disabled";
+		};
+
 		dma: dma@60080000 {
 			compatible = "espressif,esp32-gdma";
 			reg = <0x60080000 DT_SIZE_K(4)>;
@@ -246,6 +274,13 @@
 			current-speed = <115200>;
 		};
 
+		lp_uart: uart@600b1400 {
+			compatible = "espressif,esp32-lpuart";
+			reg = <0x600b1400 DT_SIZE_K(4)>;
+			status = "disabled";
+			current-speed = <115200>;
+		};
+
 		usb_serial: uart@6000f000 {
 			compatible = "espressif,esp32-usb-serial";
 			reg = <0x6000F000 0x1000>;
diff --git a/dts/riscv/espressif/esp32c6/esp32c6_lpcore.dtsi b/dts/riscv/espressif/esp32c6/esp32c6_lpcore.dtsi
new file mode 100644
index 00000000000..319bc571805
--- /dev/null
+++ b/dts/riscv/espressif/esp32c6/esp32c6_lpcore.dtsi
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <mem.h>
+#include <freq.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h>
+#include <zephyr/dt-bindings/clock/esp32c6_clock.h>
+#include <dt-bindings/pinctrl/esp32c6-pinctrl.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "espressif,riscv";
+			riscv,isa = "rv32imac_zicsr_zifencei";
+			reg = <0>;
+			clock-source = <ESP32_RTC_FAST_CLK_SRC_XTAL_D2>;
+			clock-frequency = <DT_FREQ_M(20)>;
+			xtal-freq = <DT_FREQ_M(40)>;
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		sramlp: memory@50000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "mmio-sram";
+			reg = <0x50000000 DT_SIZE_K(16)>;
+
+			shmlp: memory@0 {
+				reg = <0x0 0x10>;
+			};
+		};
+
+		flash: flash-controller@60002000 {
+			compatible = "espressif,esp32-flash-controller";
+			reg = <0x60002000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				erase-block-size = <4096>;
+				write-block-size = <4>;
+				/* Flash size is specified in SOC/SIP dtsi */
+			};
+		};
+
+		lp_uart: uart@600b1400 {
+			compatible = "espressif,esp32-lpuart";
+			reg = <0x600b1400 DT_SIZE_K(4)>;
+			status = "disabled";
+		};
+
+	};
+};
diff --git a/dts/riscv/espressif/esp32c6/esp32c6_lpcore_wroom_n4.dtsi b/dts/riscv/espressif/esp32c6/esp32c6_lpcore_wroom_n4.dtsi
new file mode 100644
index 00000000000..cfb4fc103dc
--- /dev/null
+++ b/dts/riscv/espressif/esp32c6/esp32c6_lpcore_wroom_n4.dtsi
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ #include "esp32c6_lpcore.dtsi"
+
+/* 4MB flash */
+&flash0 {
+	reg = <0x0 DT_SIZE_M(4)>;
+};
diff --git a/dts/riscv/gd/gd32vf103.dtsi b/dts/riscv/gd/gd32vf103.dtsi
index a631cd4ab18..95cdb1a6955 100644
--- a/dts/riscv/gd/gd32vf103.dtsi
+++ b/dts/riscv/gd/gd32vf103.dtsi
@@ -41,9 +41,9 @@
 		ranges;
 
 		systimer: timer@d1000000 {
-			compatible = "nuclei,systimer";
-			reg = <0xd1000000 0x10000>;
-			interrupts = <3 0>, <7 0>;
+			compatible = "nuclei,systimer", "riscv,machine-timer";
+			reg = <0xd1000000 0x8 0xd1000008 0x8>;
+			interrupts-extended = <&eclic 7 0>;
 			clk-divider = <NUCLEI_SYSTIMER_DIVIDER_4>;
 		};
 
@@ -52,10 +52,7 @@
 			#address-cells = <0>;
 			#interrupt-cells = <2>;
 			interrupt-controller;
-			reg =  <0xd2000000 0x0001
-				0xd2000004 0x0004
-				0xd200000b 0x0001
-				0xd2001000 0x1000>;
+			reg =  <0xd2000000 0x2000>;
 		};
 
 		rcu: reset-clock-controller@40021000 {
diff --git a/dts/riscv/ite/it51526aw.dtsi b/dts/riscv/ite/it51526aw.dtsi
new file mode 100644
index 00000000000..b03cfc22e1b
--- /dev/null
+++ b/dts/riscv/ite/it51526aw.dtsi
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	cpus {
+		cpu0: cpu@0 {
+			compatible = "ite,riscv-ite", "riscv";
+			riscv,isa = "rv32imb_zifencei";
+			device_type = "cpu";
+			reg = <0>;
+			clock-frequency = <32768>;
+			cpu-power-states = <&standby>;
+		};
+	};
+};
diff --git a/dts/riscv/ite/it51xxx-pinctrl-map.dtsi b/dts/riscv/ite/it51xxx-pinctrl-map.dtsi
new file mode 100644
index 00000000000..f5bcaf53a23
--- /dev/null
+++ b/dts/riscv/ite/it51xxx-pinctrl-map.dtsi
@@ -0,0 +1,396 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
+
+&pinctrl {
+	/* ADC alternate function */
+	adc0_ch0_gpi0_default: adc0_ch0_gpi0_default {
+		pinmuxs = <&pinctrli 0 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	adc0_ch1_gpi1_default: adc0_ch1_gpi1_default {
+		pinmuxs = <&pinctrli 1 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	adc0_ch2_gpi2_default: adc0_ch2_gpi2_default {
+		pinmuxs = <&pinctrli 2 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	adc0_ch3_gpi3_default: adc0_ch3_gpi3_default {
+		pinmuxs = <&pinctrli 3 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	adc0_ch4_gpi4_default: adc0_ch4_gpi4_default {
+		pinmuxs = <&pinctrli 4 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	adc0_ch5_gpi5_default: adc0_ch5_gpi5_default {
+		pinmuxs = <&pinctrli 5 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	adc0_ch6_gpi6_default: adc0_ch6_gpi6_default {
+		pinmuxs = <&pinctrli 6 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	adc0_ch7_gpi7_default: adc0_ch7_gpi7_default {
+		pinmuxs = <&pinctrli 7 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	/* I2C alternate function */
+	i2c0_clk_gpf2_default: i2c0_clk_gpf2_default {
+		pinmuxs = <&pinctrlf 2 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	i2c0_data_gpf3_default: i2c0_data_gpf3_default {
+		pinmuxs = <&pinctrlf 3 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	i2c1_clk_gpc1_default: i2c1_clk_gpc1_default {
+		pinmuxs = <&pinctrlc 1 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	i2c1_data_gpc2_default: i2c1_data_gpc2_default {
+		pinmuxs = <&pinctrlc 2 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	i2c2_clk_gpf6_default: i2c2_clk_gpf6_default {
+		pinmuxs = <&pinctrlf 6 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	i2c2_data_gpf7_default: i2c2_data_gpf7_default {
+		pinmuxs = <&pinctrlf 7 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	i2c3_clk_gph1_default: i2c3_clk_gph1_default {
+		pinmuxs = <&pinctrlh 1 IT8XXX2_ALT_FUNC_4>;
+	};
+
+	i2c3_data_gph2_default: i2c3_data_gph2_default {
+		pinmuxs = <&pinctrlh 2 IT8XXX2_ALT_FUNC_4>;
+	};
+
+	i2c4_clk_gpe0_default: i2c4_clk_gpe0_default {
+		pinmuxs = <&pinctrle 0 IT8XXX2_ALT_FUNC_4>;
+	};
+
+	i2c4_data_gpe7_default: i2c4_data_gpe7_default {
+		pinmuxs = <&pinctrle 7 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	i2c5_clk_gpa4_default: i2c5_clk_gpa4_default {
+		pinmuxs = <&pinctrla 4 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	i2c5_data_gpa5_default: i2c5_data_gpa5_default {
+		pinmuxs = <&pinctrla 5 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	i2c6_clk_gpd0_default: i2c6_clk_gpd0_default {
+		pinmuxs = <&pinctrld 0 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	i2c6_data_gpd1_default: i2c6_data_gpd1_default {
+		pinmuxs = <&pinctrld 1 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	i2c7_clk_gpb2_default: i2c7_clk_gpb2_default {
+		pinmuxs = <&pinctrlb 2 IT8XXX2_ALT_FUNC_4>;
+	};
+
+	i2c7_data_gph0_default: i2c7_data_gph0_default {
+		pinmuxs = <&pinctrlh 0 IT8XXX2_ALT_FUNC_4>;
+	};
+
+	i2c8_clk_gpb5_default: i2c8_clk_gpb5_default {
+		pinmuxs = <&pinctrlb 5 IT8XXX2_ALT_FUNC_4>;
+	};
+
+	i2c8_data_gpj6_default: i2c8_data_gpj6_default {
+		pinmuxs = <&pinctrlj 6 IT8XXX2_ALT_FUNC_4>;
+	};
+
+	/* I3C alternate function */
+	i3c0_clk_gpj3_default: i3c0_clk_gpj3_default {
+		pinmuxs = <&pinctrlj 3 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	i3c0_data_gpj4_default: i3c0_data_gpj4_default {
+		pinmuxs = <&pinctrlj 4 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	i3c1_clk_gpj5_default: i3c1_clk_gpj5_default {
+		pinmuxs = <&pinctrlj 5 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	i3c1_data_gpe1_default: i3c1_data_gpe1_default {
+		pinmuxs = <&pinctrle 1 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	i3c2_clk_gpe2_default: i3c2_clk_gpe2_default {
+		pinmuxs = <&pinctrle 2 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	i3c2_data_gpe3_default: i3c2_data_gpe3_default {
+		pinmuxs = <&pinctrle 3 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	i3c3_clk_gpf0_default: i3c3_clk_gpf0_default {
+		pinmuxs = <&pinctrlf 0 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	i3c3_data_gpf1_default: i3c3_data_gpf1_default {
+		pinmuxs = <&pinctrlf 1 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	/* Keyboard alternate function */
+	kso0_default: kso0_gpk0_default: kso0_gpk0_default {
+		pinmuxs = <&pinctrlk 0 IT8XXX2_ALT_FUNC_1>;
+		drive-open-drain;
+		bias-pull-up;
+	};
+
+	kso1_default: kso1_gpk1_default: kso1_gpk1_default {
+		pinmuxs = <&pinctrlk 1 IT8XXX2_ALT_FUNC_1>;
+		drive-open-drain;
+		bias-pull-up;
+	};
+
+	kso2_default: kso2_gpk2_default: kso2_gpk2_default {
+		pinmuxs = <&pinctrlk 2 IT8XXX2_ALT_FUNC_1>;
+		drive-open-drain;
+		bias-pull-up;
+	};
+
+	kso3_default: kso3_gpk3_default: kso3_gpk3_default {
+		pinmuxs = <&pinctrlk 3 IT8XXX2_ALT_FUNC_1>;
+		drive-open-drain;
+		bias-pull-up;
+	};
+
+	kso4_default: kso4_gpk4_default: kso4_gpk4_default {
+		pinmuxs = <&pinctrlk 4 IT8XXX2_ALT_FUNC_1>;
+		drive-open-drain;
+		bias-pull-up;
+	};
+
+	kso5_default: kso5_gpk5_default: kso5_gpk5_default {
+		pinmuxs = <&pinctrlk 5 IT8XXX2_ALT_FUNC_1>;
+		drive-open-drain;
+		bias-pull-up;
+	};
+
+	kso6_default: kso6_gpk6_default: kso6_gpk6_default {
+		pinmuxs = <&pinctrlk 6 IT8XXX2_ALT_FUNC_1>;
+		drive-open-drain;
+		bias-pull-up;
+	};
+
+	kso7_default: kso7_gpk7_default: kso7_gpk7_default {
+		pinmuxs = <&pinctrlk 7 IT8XXX2_ALT_FUNC_1>;
+		drive-open-drain;
+		bias-pull-up;
+	};
+
+	kso8_default: kso8_gpl0_default: kso8_gpl0_default {
+		pinmuxs = <&pinctrll 0 IT8XXX2_ALT_FUNC_1>;
+		drive-open-drain;
+		bias-pull-up;
+	};
+
+	kso9_default: kso9_gpl1_default: kso9_gpl1_default {
+		pinmuxs = <&pinctrll 1 IT8XXX2_ALT_FUNC_1>;
+		drive-open-drain;
+		bias-pull-up;
+	};
+
+	kso10_default: kso10_gpl2_default: kso10_gpl2_default {
+		pinmuxs = <&pinctrll 2 IT8XXX2_ALT_FUNC_1>;
+		drive-open-drain;
+		bias-pull-up;
+	};
+
+	kso11_default: kso11_gpl3_default: kso11_gpl3_default {
+		pinmuxs = <&pinctrll 3 IT8XXX2_ALT_FUNC_1>;
+		drive-open-drain;
+		bias-pull-up;
+	};
+
+	kso12_default: kso12_gpl4_default: kso12_gpl4_default {
+		pinmuxs = <&pinctrll 4 IT8XXX2_ALT_FUNC_1>;
+		drive-open-drain;
+		bias-pull-up;
+	};
+
+	kso13_default: kso13_gpl5_default: kso13_gpl5_default {
+		pinmuxs = <&pinctrll 5 IT8XXX2_ALT_FUNC_1>;
+		drive-open-drain;
+		bias-pull-up;
+	};
+
+	kso14_default: kso14_gpl6_default: kso14_gpl6_default {
+		pinmuxs = <&pinctrll 6 IT8XXX2_ALT_FUNC_1>;
+		drive-open-drain;
+		bias-pull-up;
+	};
+
+	kso15_default: kso15_gpl7_default: kso15_gpl7_default {
+		pinmuxs = <&pinctrll 7 IT8XXX2_ALT_FUNC_1>;
+		drive-open-drain;
+		bias-pull-up;
+	};
+
+	kso16_default: kso16_gpc3_default: kso16_gpc3_default {
+		pinmuxs = <&pinctrlc 3 IT8XXX2_ALT_FUNC_1>;
+		bias-pull-up;
+	};
+
+	kso17_default: kso17_gpc5_default: kso17_gpc5_default {
+		pinmuxs = <&pinctrlc 5 IT8XXX2_ALT_FUNC_1>;
+		bias-pull-up;
+	};
+
+	ksi0_default: ksi0_gpn0_default: ksi0_gpn0_default {
+		pinmuxs = <&pinctrln 0 IT8XXX2_ALT_FUNC_1>;
+		bias-pull-up;
+	};
+
+	ksi1_default: ksi1_gpn1_default: ksi1_gpn1_default {
+		pinmuxs = <&pinctrln 1 IT8XXX2_ALT_FUNC_1>;
+		bias-pull-up;
+	};
+
+	ksi2_default: ksi2_gpn2_default: ksi2_gpn2_default {
+		pinmuxs = <&pinctrln 2 IT8XXX2_ALT_FUNC_1>;
+		bias-pull-up;
+	};
+
+	ksi3_default: ksi3_gpn3_default: ksi3_gpn3_default {
+		pinmuxs = <&pinctrln 3 IT8XXX2_ALT_FUNC_1>;
+		bias-pull-up;
+	};
+
+	ksi4_default: ksi4_gpn4_default: ksi4_gpn4_default {
+		pinmuxs = <&pinctrln 4 IT8XXX2_ALT_FUNC_1>;
+		bias-pull-up;
+	};
+
+	ksi5_default: ksi5_gpn5_default: ksi5_gpn5_default {
+		pinmuxs = <&pinctrln 5 IT8XXX2_ALT_FUNC_1>;
+		bias-pull-up;
+	};
+
+	ksi6_default: ksi6_gpn6_default: ksi6_gpn6_default {
+		pinmuxs = <&pinctrln 6 IT8XXX2_ALT_FUNC_1>;
+		bias-pull-up;
+	};
+
+	ksi7_default: ksi7_gpn7_default: ksi7_gpn7_default {
+		pinmuxs = <&pinctrln 7 IT8XXX2_ALT_FUNC_1>;
+		bias-pull-up;
+	};
+
+	/* PECI alternate function */
+	peci_gpf6_default: peci_gpf6_default {
+		pinmuxs = <&pinctrlf 6 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	/* PWM alternate function */
+	pwm0_gpa0_default: pwm0_gpa0_default {
+		pinmuxs = <&pinctrla 0 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	pwm1_gpa1_default: pwm1_gpa1_default {
+		pinmuxs = <&pinctrla 1 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	pwm2_gpa2_default: pwm2_gpa2_default {
+		pinmuxs = <&pinctrla 2 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	pwm3_gpa3_default: pwm3_gpa3_default {
+		pinmuxs = <&pinctrla 3 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	pwm4_gpa4_default: pwm4_gpa4_default {
+		pinmuxs = <&pinctrla 4 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	pwm5_gpa5_default: pwm5_gpa5_default {
+		pinmuxs = <&pinctrla 5 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	pwm6_gpa6_default: pwm6_gpa6_default {
+		pinmuxs = <&pinctrla 6 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	pwm7_gpa7_default: pwm7_gpa7_default {
+		pinmuxs = <&pinctrla 7 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	/* SSPI alternate function */
+	ssce0_gpj7_default: ssce0_gpj7_default {
+		pinmuxs = <&pinctrlj 7 IT8XXX2_ALT_FUNC_4>;
+	};
+
+	ssce1_gph7_default: ssce1_gph7_default {
+		pinmuxs = <&pinctrlh 7 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	ssck_gpa6_default: ssck_gpa6_default {
+		pinmuxs = <&pinctrla 6 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	smosi_gpc6_default: smosi_gpc6_default {
+		pinmuxs = <&pinctrlc 6 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	smiso_gpc4_default: smiso_gpc4_default {
+		pinmuxs = <&pinctrlc 4 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	/* Tachometer alternate function */
+	tach0a_gpd6_default: tach0a_gpd6_default {
+		pinmuxs = <&pinctrld 6 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	tach1a_gpd7_default: tach1a_gpd7_default {
+		pinmuxs = <&pinctrld 7 IT8XXX2_ALT_FUNC_1>;
+	};
+
+	tach2a_gpj0_default: tach2a_gpj0_default {
+		pinmuxs = <&pinctrlj 0 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	tach0b_gpc6_default: tach0b_gpc6_default {
+		pinmuxs = <&pinctrlc 6 IT8XXX2_ALT_FUNC_4>;
+	};
+
+	tach1b_gpj6_default: tach1b_gpj6_default {
+		pinmuxs = <&pinctrlj 6 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	tach2b_gpj1_default: tach2b_gpj1_default {
+		pinmuxs = <&pinctrlj 1 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	/* UART alternate function */
+	uart1_rx_gpc7_default: uart1_rx_gpc7_default {
+		pinmuxs = <&pinctrlc 7 IT8XXX2_ALT_FUNC_4>;
+	};
+
+	uart1_tx_gpe6_default: uart1_tx_gpe6_default {
+		pinmuxs = <&pinctrle 6 IT8XXX2_ALT_FUNC_4>;
+	};
+
+	uart2_rx_gph1_default: uart2_rx_gph1_default {
+		pinmuxs = <&pinctrlh 1 IT8XXX2_ALT_FUNC_3>;
+	};
+
+	uart2_tx_gph2_default: uart2_tx_gph2_default {
+		pinmuxs = <&pinctrlh 2 IT8XXX2_ALT_FUNC_3>;
+	};
+};
diff --git a/dts/riscv/ite/it51xxx-wuc-map.dtsi b/dts/riscv/ite/it51xxx-wuc-map.dtsi
new file mode 100644
index 00000000000..248fd20b302
--- /dev/null
+++ b/dts/riscv/ite/it51xxx-wuc-map.dtsi
@@ -0,0 +1,337 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/dt-util.h>
+
+/ {
+	/* Mapping between wuc bits and source device */
+	it51xxx-wuc-map {
+		compatible = "ite,it51xxx-wuc-map";
+
+		/* WUC group 2 */
+		wuc_wu20: wu20 {
+			wucs = <&wuc2 BIT(0)>; /* GPD0 */
+		};
+		wuc_wu21: wu21 {
+			wucs = <&wuc2 BIT(1)>; /* GPD1 */
+		};
+		wuc_wu22: wu22 {
+			wucs = <&wuc2 BIT(2)>; /* GPC4 */
+		};
+		wuc_wu23: wu23 {
+			wucs = <&wuc2 BIT(3)>; /* GPC6 */
+		};
+		wuc_wu24: wu24{
+			wucs = <&wuc2 BIT(4)>; /* GPD2 */
+		};
+		wuc_wu25: wu25 {
+			wucs = <&wuc2 BIT(5)>; /* GPB3 */
+		};
+
+		/* WUC group 3 */
+		wuc_wu30: wu30 {
+			wucs = <&wuc3 BIT(0)>; /* KSI[0] */
+		};
+		wuc_wu31: wu31 {
+			wucs = <&wuc3 BIT(1)>; /* KSI[1] */
+		};
+		wuc_wu32: wu32 {
+			wucs = <&wuc3 BIT(2)>; /* KSI[2] */
+		};
+		wuc_wu33: wu33 {
+			wucs = <&wuc3 BIT(3)>; /* KSI[3] */
+		};
+		wuc_wu34: wu34{
+			wucs = <&wuc3 BIT(4)>; /* KSI[4] */
+		};
+		wuc_wu35: wu35 {
+			wucs = <&wuc3 BIT(5)>; /* KSI[5] */
+		};
+		wuc_wu36: wu36 {
+			wucs = <&wuc3 BIT(6)>; /* KSI[6] */
+		};
+		wuc_wu37: wu37 {
+			wucs = <&wuc3 BIT(7)>; /* KSI[7] */
+		};
+
+		/* WUC group 4 */
+		wuc_wu40: wu40 {
+			wucs = <&wuc4 BIT(0)>; /* GPE5 */
+		};
+		wuc_wu42: wu42 {
+			wucs = <&wuc4 BIT(2)>; /* eSPI transaction */
+		};
+		wuc_wu45: wu45 {
+			wucs = <&wuc4 BIT(5)>; /* GPE6 */
+		};
+		wuc_wu46: wu46 {
+			wucs = <&wuc4 BIT(6)>; /* GPE7 */
+		};
+
+		/* WUC group 6 */
+		wuc_wu60: wu60 {
+			wucs = <&wuc6 BIT(0)>; /* GPH0 */
+		};
+		wuc_wu61: wu61 {
+			wucs = <&wuc6 BIT(1)>; /* GPH1 */
+		};
+		wuc_wu62: wu62 {
+			wucs = <&wuc6 BIT(2)>; /* GPH2 */
+		};
+		wuc_wu63: wu63 {
+			wucs = <&wuc6 BIT(3)>; /* GPH3 */
+		};
+		wuc_wu64: wu64 {
+			wucs = <&wuc6 BIT(4)>; /* GPF4 */
+		};
+		wuc_wu65: wu65 {
+			wucs = <&wuc6 BIT(5)>; /* GPF5 */
+		};
+		wuc_wu66: wu66 {
+			wucs = <&wuc6 BIT(6)>; /* GPF6 */
+		};
+		wuc_wu67: wu67 {
+			wucs = <&wuc6 BIT(7)>; /* GPF7 */
+		};
+
+		/* WUC group 7 */
+		wuc_wu70: wu70 {
+			wucs = <&wuc7 BIT(0)>; /* GPE0 */
+		};
+		wuc_wu71: wu71 {
+			wucs = <&wuc7 BIT(1)>; /* GPE1 */
+		};
+		wuc_wu72: wu72 {
+			wucs = <&wuc7 BIT(2)>; /* GPE2 */
+		};
+		wuc_wu73: wu73 {
+			wucs = <&wuc7 BIT(3)>; /* GPE3 */
+		};
+		wuc_wu74: wu74 {
+			wucs = <&wuc7 BIT(4)>; /* GPI4 */
+		};
+		wuc_wu75: wu75 {
+			wucs = <&wuc7 BIT(5)>; /* GPI5 */
+		};
+		wuc_wu76: wu76 {
+			wucs = <&wuc7 BIT(6)>; /* GPI6 */
+		};
+		wuc_wu77: wu77 {
+			wucs = <&wuc7 BIT(7)>; /* GPI7 */
+		};
+
+		/* WUC group 8 */
+		wuc_wu80: wu80 {
+			wucs = <&wuc8 BIT(0)>; /* GPA3 */
+		};
+		wuc_wu81: wu81 {
+			wucs = <&wuc8 BIT(1)>; /* GPA4 */
+		};
+		wuc_wu82: wu82 {
+			wucs = <&wuc8 BIT(2)>; /* GPA5 */
+		};
+		wuc_wu83: wu83 {
+			wucs = <&wuc8 BIT(3)>; /* GPA6 */
+		};
+		wuc_wu84: wu84 {
+			wucs = <&wuc8 BIT(4)>; /* GPB2 */
+		};
+		wuc_wu85: wu85 {
+			wucs = <&wuc8 BIT(5)>; /* GPC0 */
+		};
+		wuc_wu86: wu86 {
+			wucs = <&wuc8 BIT(6)>; /* GPC7 */
+		};
+		wuc_wu87: wu87 {
+			wucs = <&wuc8 BIT(7)>; /* GPD7 */
+		};
+
+		/* WUC group 9 */
+		wuc_wu88: wu88 {
+			wucs = <&wuc9 BIT(0)>; /* GPH4 */
+		};
+		wuc_wu89: wu89 {
+			wucs = <&wuc9 BIT(1)>; /* GPH5 */
+		};
+		wuc_wu90: wu90 {
+			wucs = <&wuc9 BIT(2)>; /* GPH6 */
+		};
+		wuc_wu91: wu91 {
+			wucs = <&wuc9 BIT(3)>; /* GPA0 */
+		};
+		wuc_wu92: wu92 {
+			wucs = <&wuc9 BIT(4)>; /* GPA1 */
+		};
+		wuc_wu93: wu93 {
+			wucs = <&wuc9 BIT(5)>; /* GPA2 */
+		};
+		wuc_wu95: wu95 {
+			wucs = <&wuc9 BIT(7)>; /* GPC2 */
+		};
+
+		/* WUC group 10 */
+		wuc_wu96: wu96 {
+			wucs = <&wuc10 BIT(0)>; /* GPF0 */
+		};
+		wuc_wu97: wu97 {
+			wucs = <&wuc10 BIT(1)>; /* GPF1 */
+		};
+		wuc_wu98: wu98 {
+			wucs = <&wuc10 BIT(2)>; /* GPF2 */
+		};
+		wuc_wu99: wu99 {
+			wucs = <&wuc10 BIT(3)>; /* GPF3 */
+		};
+		wuc_wu100: wu100 {
+			wucs = <&wuc10 BIT(4)>; /* GPA7 */
+		};
+		wuc_wu101: wu101 {
+			wucs = <&wuc10 BIT(5)>; /* GPB0 */
+		};
+		wuc_wu102: wu102 {
+			wucs = <&wuc10 BIT(6)>; /* GPB1 */
+		};
+		wuc_wu103: wu103 {
+			wucs = <&wuc10 BIT(7)>; /* GPB3 */
+		};
+
+		/* WUC group 11 */
+		wuc_wu104: wu104 {
+			wucs = <&wuc11 BIT(0)>; /* GPB5 */
+		};
+		wuc_wu105: wu105 {
+			wucs = <&wuc11 BIT(1)>; /* GPB6 */
+		};
+		wuc_wu107: wu107 {
+			wucs = <&wuc11 BIT(3)>; /* GPC1 */
+		};
+		wuc_wu108: wu108 {
+			wucs = <&wuc11 BIT(4)>; /* GPC3 */
+		};
+		wuc_wu109: wu109 {
+			wucs = <&wuc11 BIT(5)>; /* GPC5 */
+		};
+		wuc_wu110: wu110 {
+			wucs = <&wuc11 BIT(6)>; /* GPD3 */
+		};
+		wuc_wu111: wu111 {
+			wucs = <&wuc11 BIT(7)>; /* GPD4 */
+		};
+
+		/* WUC group 12 */
+		wuc_wu112: wu112 {
+			wucs = <&wuc12 BIT(0)>; /* GPD5 */
+		};
+		wuc_wu113: wu113 {
+			wucs = <&wuc12 BIT(1)>; /* GPD6 */
+		};
+		wuc_wu114: wu114 {
+			wucs = <&wuc12 BIT(2)>; /* GPE4 */
+		};
+		wuc_wu115: wu115 {
+			wucs = <&wuc12 BIT(3)>; /* GPG0 */
+		};
+		wuc_wu116: wu116 {
+			wucs = <&wuc12 BIT(4)>; /* GPG1 */
+		};
+		wuc_wu117: wu117 {
+			wucs = <&wuc12 BIT(5)>; /* GPG2 */
+		};
+		wuc_wu118: wu118 {
+			wucs = <&wuc12 BIT(6)>; /* GPG6 */
+		};
+		wuc_wu119: wu119 {
+			wucs = <&wuc12 BIT(7)>; /* GPI0 */
+		};
+
+		/* WUC group 13 */
+		wuc_wu120: wu120 {
+			wucs = <&wuc13 BIT(0)>; /* GPI1 */
+		};
+		wuc_wu121: wu121 {
+			wucs = <&wuc13 BIT(1)>; /* GPI2 */
+		};
+		wuc_wu122: wu122 {
+			wucs = <&wuc13 BIT(2)>; /* GPI3 */
+		};
+		wuc_wu127: wu127 {
+			wucs = <&wuc13 BIT(7)>; /* GPH7 */
+		};
+
+		/* WUC group 14 */
+		wuc_wu128: wu128 {
+			wucs = <&wuc14 BIT(0)>; /* GPJ0 */
+		};
+		wuc_wu129: wu129 {
+			wucs = <&wuc14 BIT(1)>; /* GPJ1 */
+		};
+		wuc_wu131: wu131 {
+			wucs = <&wuc14 BIT(3)>; /* GPJ3 */
+		};
+		wuc_wu132: wu132 {
+			wucs = <&wuc14 BIT(4)>; /* GPJ4 */
+		};
+		wuc_wu133: wu133 {
+			wucs = <&wuc14 BIT(5)>; /* GPJ5 */
+		};
+		wuc_wu134: wu134 {
+			wucs = <&wuc14 BIT(6)>; /* GPJ6 */
+		};
+		wuc_wu135: wu135 {
+			wucs = <&wuc14 BIT(7)>; /* GPJ7 */
+		};
+
+		/* WUC group 15 */
+		wuc_wu136: wu136 {
+			wucs = <&wuc15 BIT(0)>; /* GPL0 */
+		};
+		wuc_wu137: wu137 {
+			wucs = <&wuc15 BIT(1)>; /* GPL1 */
+		};
+		wuc_wu138: wu138 {
+			wucs = <&wuc15 BIT(2)>; /* GPL2 */
+		};
+		wuc_wu139: wu139 {
+			wucs = <&wuc15 BIT(3)>; /* GPL3 */
+		};
+		wuc_wu140: wu140 {
+			wucs = <&wuc15 BIT(4)>; /* GPL4 */
+		};
+		wuc_wu141: wu141 {
+			wucs = <&wuc15 BIT(5)>; /* GPL5 */
+		};
+		wuc_wu142: wu142 {
+			wucs = <&wuc15 BIT(6)>; /* GPL6 */
+		};
+
+		/* WUC group 16 */
+		wuc_wu144: wu144 {
+			wucs = <&wuc16 BIT(0)>; /* GPM0 */
+		};
+		wuc_wu145: wu145 {
+			wucs = <&wuc16 BIT(1)>; /* GPM1 */
+		};
+		wuc_wu146: wu146 {
+			wucs = <&wuc16 BIT(2)>; /* GPM2 */
+		};
+		wuc_wu147: wu147 {
+			wucs = <&wuc16 BIT(3)>; /* GPM3 */
+		};
+		wuc_wu148: wu148 {
+			wucs = <&wuc16 BIT(4)>; /* GPM4 */
+		};
+		wuc_wu149: wu149 {
+			wucs = <&wuc16 BIT(5)>; /* GPM5 */
+		};
+		wuc_wu150: wu150 {
+			wucs = <&wuc16 BIT(6)>; /* GPM6 */
+		};
+
+		wuc_no_func: no_func {
+			wucs = <&wuc_fake 0>;
+		};
+	};
+};
diff --git a/dts/riscv/ite/it51xxx.dtsi b/dts/riscv/ite/it51xxx.dtsi
new file mode 100644
index 00000000000..3538a62be56
--- /dev/null
+++ b/dts/riscv/ite/it51xxx.dtsi
@@ -0,0 +1,1046 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <ite/it51xxx-wuc-map.dtsi>
+#include <mem.h>
+#include <zephyr/dt-bindings/clock/ite-it51xxx-clock.h>
+#include <zephyr/dt-bindings/dt-util.h>
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/interrupt-controller/ite-it51xxx-intc.h>
+#include <zephyr/dt-bindings/interrupt-controller/ite-it51xxx-wuc.h>
+#include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
+#include <zephyr/dt-bindings/sensor/it51xxx_tach.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "ite,riscv-ite", "riscv";
+			riscv,isa = "rv32imcb_zifencei";
+			device_type = "cpu";
+			reg = <0>;
+			clock-frequency = <32768>;
+			cpu-power-states = <&standby>;
+		};
+
+		power-states {
+			standby: standby {
+				compatible = "zephyr,power-state";
+				power-state-name = "standby";
+				min-residency-us = <500>;
+			};
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		flashctrl: flash-controller@f01000 {
+			compatible = "ite,it8xxx2-flash-controller";
+			reg = <0x00f01000 0x100>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				reg = <0 DT_SIZE_M(1)>;
+				erase-block-size = <4096>;
+				write-block-size = <4>;
+			};
+		};
+
+		sram0: memory@800000 {
+			compatible = "mmio-sram";
+			reg = <0x800000 DT_SIZE_K(128)>;
+		};
+
+		ilm: ilm@f01040 {
+			compatible = "ite,it8xxx2-ilm";
+			reg = <0xf01040 3>;	/* SCAR0 */
+		};
+
+		adc0: adc@f04500 {
+			compatible = "ite,it51xxx-adc";
+			reg = <0xf04500 0xc1>;
+			channel-count = <8>;
+			interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			status = "disabled";
+			#io-channel-cells = <1>;
+		};
+
+		gpiogcr: gpio-gcr@f01600 {
+			compatible = "ite,it51xxx-gpiogcr";
+			reg = <0x00f01600 0x100>;
+		};
+
+		gpioa: gpio@f01601 {
+			compatible = "ite,it51xxx-gpio";
+			reg = <0x00f01601 1   /* GPDR (set) */
+			       0x00f01661 1   /* GPDMR (get) */
+			       0x00f01671 1   /* GPOTR */
+			       0x00f016d4 1   /* P18SCR */
+			       0x00f01610 8   /* GPCR */
+			       NO_FUNC 1>;
+			ngpios = <8>;
+			gpio-controller;
+			interrupts = <IT51XXX_IRQ_WU91 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU92 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU93 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU80 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU81 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU82 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU83 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU100 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			wucctrl = <&wuc_wu91    /* GPA0 */
+				   &wuc_wu92    /* GPA1 */
+				   &wuc_wu93    /* GPA2 */
+				   &wuc_wu80    /* GPA3 */
+				   &wuc_wu81    /* GPA4 */
+				   &wuc_wu82    /* GPA5 */
+				   &wuc_wu83    /* GPA6 */
+				   &wuc_wu100>; /* GPA7 */
+			has-volt-sel = <1 1 1 1 0 0 1 1>;
+			#gpio-cells = <2>;
+		};
+
+		gpiob: gpio@f01602 {
+			compatible = "ite,it51xxx-gpio";
+			reg = <0x00f01602 1   /* GPDR (set) */
+			       0x00f01662 1   /* GPDMR (get) */
+			       0x00f01672 1   /* GPOTR */
+			       0x00f016d5 1   /* P18SCR */
+			       0x00f01618 7   /* GPCR */
+			       NO_FUNC 1>;
+			ngpios = <7>;
+			gpio-controller;
+			interrupts = <IT51XXX_IRQ_WU101 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU102 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU84 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU103 IRQ_TYPE_LEVEL_HIGH
+				      NO_FUNC 0
+				      IT51XXX_IRQ_WU104 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU105 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			wucctrl = <&wuc_wu101   /* GPB0 */
+				   &wuc_wu102   /* GPB1 */
+				   &wuc_wu84    /* GPB2 */
+				   &wuc_wu103   /* GPB3 */
+				   &wuc_no_func /* NO_FUNC */
+				   &wuc_wu104   /* GPB5 */
+				   &wuc_wu105>; /* GPB6 */
+			has-volt-sel = <0 0 1 0 0 0 0 0>;
+			#gpio-cells = <2>;
+		};
+
+		gpioc: gpio@f01603 {
+			compatible = "ite,it51xxx-gpio";
+			reg = <0x00f01603 1   /* GPDR (set) */
+			       0x00f01663 1   /* GPDMR (get) */
+			       0x00f01673 1   /* GPOTR */
+			       0x00f016d6 1   /* P18SCR */
+			       0x00f01620 8   /* GPCR */
+			       NO_FUNC 1>;
+			ngpios = <8>;
+			gpio-controller;
+			interrupts = <IT51XXX_IRQ_WU85 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU107 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU95 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU108 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU22 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU109 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU23 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU86 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			wucctrl = <&wuc_wu85   /* GPC0 */
+				   &wuc_wu107  /* GPC1 */
+				   &wuc_wu95   /* GPC2 */
+				   &wuc_wu108  /* GPC3 */
+				   &wuc_wu22   /* GPC4 */
+				   &wuc_wu109  /* GPC5 */
+				   &wuc_wu23   /* GPC6 */
+				   &wuc_wu86>; /* GPC7 */
+			has-volt-sel = <1 0 0 1 1 1 1 0>;
+			#gpio-cells = <2>;
+		};
+
+		gpiod: gpio@f01604 {
+			compatible = "ite,it51xxx-gpio";
+			reg = <0x00f01604 1   /* GPDR (set) */
+			       0x00f01664 1   /* GPDMR (get) */
+			       0x00f01674 1   /* GPOTR */
+			       0x00f016d7 1   /* P18SCR */
+			       0x00f01628 8   /* GPCR */
+			       NO_FUNC 1>;
+			ngpios = <8>;
+			gpio-controller;
+			interrupts = <IT51XXX_IRQ_WU20 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU21 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU24 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU110 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU111 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU112 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU113 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU87 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			wucctrl = <&wuc_wu20   /* GPD0 */
+				   &wuc_wu21   /* GPD1 */
+				   &wuc_wu24   /* GPD2 */
+				   &wuc_wu110  /* GPD3 */
+				   &wuc_wu111  /* GPD4 */
+				   &wuc_wu112  /* GPD5 */
+				   &wuc_wu113  /* GPD6 */
+				   &wuc_wu87>; /* GPD7 */
+			has-volt-sel = <0 0 0 0 0 1 1 1>;
+			#gpio-cells = <2>;
+		};
+
+		gpioe: gpio@f01605 {
+			compatible = "ite,it51xxx-gpio";
+			reg = <0x00f01605 1   /* GPDR (set) */
+			       0x00f01665 1   /* GPDMR (get) */
+			       0x00f01675 1   /* GPOTR */
+			       0x00f016d8 1   /* P18SCR */
+			       0x00f01630 8   /* GPCR */
+			       NO_FUNC 1>;
+			ngpios = <8>;
+			gpio-controller;
+			interrupts = <IT51XXX_IRQ_WU70 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU71 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU72 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU73 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU114 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU40 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU45 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU46 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			wucctrl = <&wuc_wu70   /* GPE0 */
+				   &wuc_wu71   /* GPE1 */
+				   &wuc_wu72   /* GPE2 */
+				   &wuc_wu73   /* GPE3 */
+				   &wuc_wu114  /* GPE4 */
+				   &wuc_wu40   /* GPE5 */
+				   &wuc_wu45   /* GPE6 */
+				   &wuc_wu46>; /* GPE7 */
+			has-volt-sel = <0 1 1 1 0 1 0 0>;
+			#gpio-cells = <2>;
+		};
+
+		gpiof: gpio@f01606 {
+			compatible = "ite,it51xxx-gpio";
+			reg = <0x00f01606 1   /* GPDR (set) */
+			       0x00f01666 1   /* GPDMR (get) */
+			       0x00f01676 1   /* GPOTR */
+			       0x00f016d9 1   /* P18SCR */
+			       0x00f01638 8   /* GPCR */
+			       NO_FUNC 1>;
+			ngpios = <8>;
+			gpio-controller;
+			interrupts = <IT51XXX_IRQ_WU96 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU97 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU98 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU99 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU64 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU65 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU66 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU67 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			wucctrl = <&wuc_wu96   /* GPF0 */
+				   &wuc_wu97   /* GPF1 */
+				   &wuc_wu98   /* GPF2 */
+				   &wuc_wu99   /* GPF3 */
+				   &wuc_wu64   /* GPF4 */
+				   &wuc_wu65   /* GPF5 */
+				   &wuc_wu66   /* GPF6 */
+				   &wuc_wu67>; /* GPF7 */
+			has-volt-sel = <1 1 0 0 0 0 0 0>;
+			#gpio-cells = <2>;
+		};
+
+		gpiog: gpio@f01607 {
+			compatible = "ite,it51xxx-gpio";
+			reg = <0x00f01607 1   /* GPDR (set) */
+			       0x00f01667 1   /* GPDMR (get) */
+			       0x00f01677 1   /* GPOTR */
+			       0x00f016da 1   /* P18SCR */
+			       0x00f01640 8   /* GPCR */
+			       NO_FUNC 1>;
+			ngpios = <8>;
+			gpio-controller;
+			interrupts = <IT51XXX_IRQ_WU115 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU116 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU117 IRQ_TYPE_LEVEL_HIGH
+				      NO_FUNC 0
+				      NO_FUNC 0
+				      NO_FUNC 0
+				      IT51XXX_IRQ_WU118 IRQ_TYPE_LEVEL_HIGH
+				      NO_FUNC 0>;
+			interrupt-parent = <&intc>;
+			wucctrl = <&wuc_wu115     /* GPG0 */
+				   &wuc_wu116     /* GPG1 */
+				   &wuc_wu117     /* GPG2 */
+				   &wuc_no_func   /* NO_FUNC */
+				   &wuc_no_func   /* NO_FUNC */
+				   &wuc_no_func   /* NO_FUNC */
+				   &wuc_wu118     /* GPG6 */
+				   &wuc_no_func>; /* NO_FUNC */
+			has-volt-sel = <1 0 1 0 0 0 0 0>;
+			#gpio-cells = <2>;
+		};
+
+		gpioh: gpio@f01608 {
+			compatible = "ite,it51xxx-gpio";
+			reg = <0x00f01608 1   /* GPDR (set) */
+			       0x00f01668 1   /* GPDMR (get) */
+			       0x00f01678 1   /* GPOTR */
+			       0x00f016db 1   /* P18SCR */
+			       0x00f01648 8   /* GPCR */
+			       NO_FUNC 1>;
+			ngpios = <8>;
+			gpio-controller;
+			interrupts = <IT51XXX_IRQ_WU60 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU61 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU62 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU63 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU88 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU89 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU90 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU127 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			wucctrl = <&wuc_wu60    /* GPH0 */
+				   &wuc_wu61    /* GPH1 */
+				   &wuc_wu62    /* GPH2 */
+				   &wuc_wu63    /* GPH3 */
+				   &wuc_wu88    /* GPH4 */
+				   &wuc_wu89    /* GPH5 */
+				   &wuc_wu90    /* GPH6 */
+				   &wuc_wu127>; /* GPH7 */
+			has-volt-sel = <0 0 0 1 1 1 1 1>;
+			#gpio-cells = <2>;
+		};
+
+		gpioi: gpio@f01609 {
+			compatible = "ite,it51xxx-gpio";
+			reg = <0x00f01609 1   /* GPDR (set) */
+			       0x00f01669 1   /* GPDMR (get) */
+			       0x00f01679 1   /* GPOTR */
+			       0x00f016dc 1   /* P18SCR */
+			       0x00f01650 8   /* GPCR */
+			       NO_FUNC 1>;
+			ngpios = <8>;
+			gpio-controller;
+			interrupts = <IT51XXX_IRQ_WU119 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU120 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU121 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU122 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU74 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU75 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU76 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU77 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			wucctrl = <&wuc_wu119  /* GPI0 */
+				   &wuc_wu120  /* GPI1 */
+				   &wuc_wu121  /* GPI2 */
+				   &wuc_wu122  /* GPI3 */
+				   &wuc_wu74   /* GPI4 */
+				   &wuc_wu75   /* GPI5 */
+				   &wuc_wu76   /* GPI6 */
+				   &wuc_wu77>; /* GPI7 */
+			has-volt-sel = <1 1 1 1 1 1 1 1>;
+			#gpio-cells = <2>;
+		};
+
+		gpioj: gpio@f0160a {
+			compatible = "ite,it51xxx-gpio";
+			reg = <0x00f0160a 1   /* GPDR (set) */
+			       0x00f0166a 1   /* GPDMR (get) */
+			       0x00f0167a 1   /* GPOTR */
+			       0x00f016dd 1   /* P18SCR */
+			       0x00f01658 8   /* GPCR */
+			       NO_FUNC 1>;
+			ngpios = <8>;
+			gpio-controller;
+			interrupts = <IT51XXX_IRQ_WU128 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU129 IRQ_TYPE_LEVEL_HIGH
+				      NO_FUNC 0
+				      IT51XXX_IRQ_WU131 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU132 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU133 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU134 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU135 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			wucctrl = <&wuc_wu128   /* GPJ0 */
+				   &wuc_wu129   /* GPJ1 */
+				   &wuc_no_func /* NO_FUNC */
+				   &wuc_wu131   /* GPJ3 */
+				   &wuc_wu132   /* GPJ4 */
+				   &wuc_wu133   /* GPJ5 */
+				   &wuc_wu134   /* GPJ6 */
+				   &wuc_wu135>; /* GPJ7 */
+			has-volt-sel = <1 1 0 1 1 1 1 1>;
+			#gpio-cells = <2>;
+		};
+
+		gpiok: gpio@f0160b {
+			compatible = "ite,it51xxx-gpio";
+			reg = <0x00f0160b 1   /* GPDR (set) */
+			       0x00f0166b 1   /* GPDMR (get) */
+			       0x00f0167b 1   /* GPOTR */
+			       NO_FUNC 1      /* P18SCR */
+			       0x00f01690 8   /* GPCR */
+			       0x00f01d2d 1>; /* KSOLFSELR */
+			ngpios = <8>;
+			gpio-controller;
+			interrupts = <NO_FUNC 0
+				      NO_FUNC 0
+				      NO_FUNC 0
+				      NO_FUNC 0
+				      NO_FUNC 0
+				      NO_FUNC 0
+				      NO_FUNC 0
+				      NO_FUNC 0>;
+			interrupt-parent = <&intc>;
+			wucctrl = <&wuc_no_func /* NO_FUNC */
+				   &wuc_no_func
+				   &wuc_no_func
+				   &wuc_no_func
+				   &wuc_no_func
+				   &wuc_no_func
+				   &wuc_no_func
+				   &wuc_no_func>;
+			#gpio-cells = <2>;
+		};
+
+		gpiol: gpio@f0160c {
+			compatible = "ite,it51xxx-gpio";
+			reg = <0x00f0160c 1   /* GPDR (set) */
+			       0x00f0166c 1   /* GPDMR (get) */
+			       0x00f0167c 1   /* GPOTR */
+			       NO_FUNC 1      /* P18SCR */
+			       0x00f01698 8   /* GPCR */
+			       0x00f01d2e 1>; /* KSOHFSELR */
+			ngpios = <8>;
+			gpio-controller;
+			interrupts = <IT51XXX_IRQ_WU136 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU137 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU138 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU139 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU140 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU141 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU142 IRQ_TYPE_LEVEL_HIGH
+				      NO_FUNC 0>;
+			interrupt-parent = <&intc>;
+			wucctrl = <&wuc_wu136     /* GPL0 */
+				   &wuc_wu137     /* GPL1 */
+				   &wuc_wu138     /* GPL2 */
+				   &wuc_wu139     /* GPL3 */
+				   &wuc_wu140     /* GPL4 */
+				   &wuc_wu141     /* GPL5 */
+				   &wuc_wu142     /* GPL6 */
+				   &wuc_no_func>; /* NO_FUNC */
+			#gpio-cells = <2>;
+		};
+
+		gpiom: gpio@f0160d {
+			compatible = "ite,it51xxx-gpio";
+			reg = <0x00f0160d 1   /* GPDR (set) */
+			       0x00f0166d 1   /* GPDMR (get) */
+			       NO_FUNC 1      /* GPOTR */
+			       NO_FUNC 1      /* P18SCR */
+			       0x00f016a0 7   /* GPCR */
+			       NO_FUNC 1>;
+			ngpios = <7>;
+			gpio-controller;
+			interrupts = <IT51XXX_IRQ_WU144 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU145 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU146 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU147 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU148 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU149 IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WU150 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			wucctrl = <&wuc_wu144   /* GPM0 */
+				   &wuc_wu145   /* GPM1 */
+				   &wuc_wu146   /* GPM2 */
+				   &wuc_wu147   /* GPM3 */
+				   &wuc_wu148   /* GPM4 */
+				   &wuc_wu149   /* GPM5 */
+				   &wuc_wu150>; /* GPM6 */
+			#gpio-cells = <2>;
+		};
+
+		gpion: gpio@f0160e {
+			compatible = "ite,it51xxx-gpio";
+			reg = <0x00f0160e 1   /* GPDR (set) */
+			       0x00f0166e 1   /* GPDMR (get) */
+			       0x00f0167e 1   /* GPOTR */
+			       NO_FUNC 1      /* P18SCR */
+			       0x00f016a8 8   /* GPCR */
+			       0x00f01d2c 1>; /* KSIFSELR */
+			ngpios = <8>;
+			gpio-controller;
+			interrupts = <IT51XXX_IRQ_WKINTC IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WKINTC IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WKINTC IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WKINTC IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WKINTC IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WKINTC IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WKINTC IRQ_TYPE_LEVEL_HIGH
+				      IT51XXX_IRQ_WKINTC IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			wucctrl = <&wuc_wu30   /* GPN0 */
+				   &wuc_wu31   /* GPN1 */
+				   &wuc_wu32   /* GPN2 */
+				   &wuc_wu33   /* GPN3 */
+				   &wuc_wu34   /* GPN4 */
+				   &wuc_wu35   /* GPN5 */
+				   &wuc_wu36   /* GPN6 */
+				   &wuc_wu37>; /* GPN7 */
+			#gpio-cells = <2>;
+		};
+
+		pinctrl: pin-controller {
+			compatible = "ite,it8xxx2-pinctrl";
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "okay";
+		};
+
+		pinctrla: pinctrl@f01610 {
+			compatible = "ite,it8xxx2-pinctrl-func";
+			reg = <0x00f01610 8     /* GPCR */
+			       NO_FUNC    1>;
+			func3-gcr =     <NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC
+					 0xf016fe 0xf016fe 0xf016f0 0xf016f0>;
+			func3-en-mask = <0        0        0        0
+					 BIT(5)   BIT(5)   BIT(4)   BIT(3)  >;
+			func4-gcr =     <NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC
+					 NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC >;
+			func4-en-mask = <0        0        0        0
+					 0        0        0        0       >;
+			volt-sel =      <0xf016d4 0xf016d4 0xf016d4 0xf016d4
+					 NO_FUNC  NO_FUNC  0xf016d4 0xf016d4>;
+			volt-sel-mask = <BIT(0)   BIT(1)   BIT(2)   BIT(3)
+					 0        0        BIT(6)   BIT(7)  >;
+			#pinmux-cells = <2>;
+			gpio-group;
+		};
+
+		pinctrlb: pinctrl@f01618 {
+			compatible = "ite,it8xxx2-pinctrl-func";
+			reg = <0x00f01618 8     /* GPCR */
+			       NO_FUNC    1>;
+			func3-gcr =     <NO_FUNC  NO_FUNC  0xf016f0 NO_FUNC
+					 NO_FUNC  0xf016f7 NO_FUNC  NO_FUNC >;
+			func3-en-mask = <0        0        BIT(1)   0
+					 0        BIT(5)   0        0       >;
+			func4-gcr =     <NO_FUNC  NO_FUNC  0xf016ed NO_FUNC
+					 NO_FUNC  0xf016ed NO_FUNC  NO_FUNC >;
+			func4-en-mask = <0        0        BIT(2)   0
+					 0        BIT(3)   0        0       >;
+			volt-sel =      <NO_FUNC  NO_FUNC  0xf016d5 NO_FUNC
+					 NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC >;
+			volt-sel-mask = <0        0        BIT(2)   0
+					 0        0        0        0       >;
+			#pinmux-cells = <2>;
+			gpio-group;
+		};
+
+		pinctrlc: pinctrl@f01620 {
+			compatible = "ite,it8xxx2-pinctrl-func";
+			reg = <0x00f01620 8     /* GPCR */
+			       NO_FUNC    1>;
+			func3-gcr =     <NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC
+					 0xf016f0 NO_FUNC  0xf016f0 0xf016f6>;
+			func3-en-mask = <0        0        0        0
+					 BIT(4)   0        BIT(4)   BIT(7)  >;
+			func4-gcr =     <NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC
+					 NO_FUNC  NO_FUNC  0xf016f4 0xf016f5>;
+			func4-en-mask = <0        0        0        0
+					 0        0        BIT(0)   BIT(0)  >;
+			volt-sel =      <0xf016d6 NO_FUNC  NO_FUNC  0xf016d6
+					 0xf016d6 0xf016d6 0xf016d6 NO_FUNC >;
+			volt-sel-mask = <BIT(0)   0        0        BIT(3)
+					 BIT(4)   BIT(5)   BIT(6)   0       >;
+			#pinmux-cells = <2>;
+			gpio-group;
+		};
+
+		pinctrld: pinctrl@f01628 {
+			compatible = "ite,it8xxx2-pinctrl-func";
+			reg = <0x00f01628 8     /* GPCR */
+			       NO_FUNC    1>;
+			func3-gcr =     <0xf016ed 0xf016ed NO_FUNC  NO_FUNC
+					 0xf03292 0xf016f0 NO_FUNC  NO_FUNC >;
+			func3-en-mask = <BIT(1)   BIT(1)   0        0
+					 BIT(5)   BIT(1)   0        0       >;
+			func4-gcr =     <NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC
+					 NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC >;
+			func4-en-mask = <0        0        0        0
+					 0        0        0        0       >;
+			volt-sel =      <NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC
+					 NO_FUNC  0xf016d7 0xf016d7 0xf016d7>;
+			volt-sel-mask = <0        0        0        0
+					 0        BIT(5)   BIT(6)   BIT(7)  >;
+			#pinmux-cells = <2>;
+			gpio-group;
+		};
+
+		pinctrle: pinctrl@f01630 {
+			compatible = "ite,it8xxx2-pinctrl-func";
+			reg = <0x00f01630 8     /* GPCR */
+			       NO_FUNC    1>;
+			func3-gcr =     <0xf016f3 NO_FUNC  NO_FUNC  NO_FUNC
+					 NO_FUNC  0xf016f0 0xf016fe 0xf016fe>;
+			func3-en-mask = <BIT(0)   0        0        0
+					 0        BIT(3)   BIT(7)   BIT(4)  >;
+			func4-gcr =     <0xf016fe NO_FUNC  NO_FUNC  NO_FUNC
+					 NO_FUNC  NO_FUNC  0xf016f5 NO_FUNC >;
+			func4-en-mask = <BIT(4)   0        0        0
+					 0        0        BIT(1)   0       >;
+			volt-sel =      <NO_FUNC  0xf016d8 0xf016d8 0xf016d8
+					 NO_FUNC  0xf016d8 NO_FUNC  NO_FUNC >;
+			volt-sel-mask = <0        BIT(1)   BIT(2)   BIT(3)
+					 0        BIT(5)   0        0       >;
+			#pinmux-cells = <2>;
+			gpio-group;
+		};
+
+		pinctrlf: pinctrl@f01638 {
+			compatible = "ite,it8xxx2-pinctrl-func";
+			reg = <0x00f01638 8     /* GPCR */
+			       NO_FUNC    1>;
+			func3-gcr =     <NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC
+					 NO_FUNC  NO_FUNC  0xf016f1 NO_FUNC>;
+			func3-en-mask = <0        0        0        0
+					 0        0        BIT(4)   0      >;
+			func4-gcr =     <NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC
+					 NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC>;
+			func4-en-mask = <0        0        0        0
+					 0        0        0        0      >;
+			volt-sel =      <0xf016d9 0xf016d9 NO_FUNC  NO_FUNC
+					 NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC>;
+			volt-sel-mask = <BIT(0)   BIT(1)   0        0
+					 0        0        0        0      >;
+			#pinmux-cells = <2>;
+			gpio-group;
+		};
+
+		pinctrlg: pinctrl@f01640 {
+			compatible = "ite,it8xxx2-pinctrl-func";
+			reg = <0x00f01640 8     /* GPCR */
+			       NO_FUNC    1>;
+			func3-gcr =     <NO_FUNC  0xf016f0 NO_FUNC  NO_FUNC
+					 NO_FUNC  NO_FUNC  0xf016f0 NO_FUNC>;
+			func3-en-mask = <0        BIT(3)   0        0
+					 0        0        BIT(1)   0      >;
+			func4-gcr =     <NO_FUNC  0xf016f0 NO_FUNC  NO_FUNC
+					 NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC>;
+			func4-en-mask = <0        BIT(6)   0        0
+					 0        0        0        0      >;
+			volt-sel =      <0xf016da NO_FUNC  0xf016da NO_FUNC
+					 NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC>;
+			volt-sel-mask = <BIT(0)   0        BIT(2)   0
+					 0        0        0        0      >;
+			#pinmux-cells = <2>;
+			gpio-group;
+		};
+
+		pinctrlh: pinctrl@f01648 {
+			compatible = "ite,it8xxx2-pinctrl-func";
+			reg = <0x00f01648 8     /* GPCR */
+			       NO_FUNC    1>;
+			func3-gcr =     <0xf016f0 0xf016f5 0xf016f5 0xf016f0
+					 0xf016f0 NO_FUNC  NO_FUNC  0xf016f0>;
+			func3-en-mask = <BIT(1)   BIT(2)   BIT(3)   BIT(1)
+					 BIT(1)   0        0        BIT(5)  >;
+			func4-gcr =     <0xf016ed 0xf016f1 0xf016f1 NO_FUNC
+					 NO_FUNC  NO_FUNC  NO_FUNC  0xf016f5>;
+			func4-en-mask = <BIT(2)   BIT(5)   BIT(5)   0
+					 0        0        0        BIT(7)  >;
+			volt-sel =      <NO_FUNC  NO_FUNC  NO_FUNC  0xf016db
+					 0xf016db 0xf016db 0xf016db 0xf016db>;
+			volt-sel-mask = <0        0        0        BIT(3)
+					 BIT(4)   BIT(5)   BIT(6)   BIT(7)  >;
+			#pinmux-cells = <2>;
+			gpio-group;
+		};
+
+		pinctrli: pinctrl@f01650 {
+			compatible = "ite,it8xxx2-pinctrl-func";
+			reg = <0x00f01650 8     /* GPCR */
+			       NO_FUNC    1>;
+			func3-gcr =     <NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC
+					 NO_FUNC  0xf016f0 0xf016f0 0xf016f0>;
+			func3-en-mask = <0        0        0        0
+					 0        BIT(3)   BIT(3)   BIT(3)  >;
+			func4-gcr =     <NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC
+					 NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC >;
+			func4-en-mask = <0        0        0        0
+					 0        0        0        0       >;
+			volt-sel =      <0xf016dc 0xf016dc 0xf016dc 0xf016dc
+					 0xf016dc 0xf016dc 0xf016dc 0xf016dc>;
+			volt-sel-mask = <BIT(0)   BIT(1)   BIT(2)   BIT(3)
+					 BIT(4)   BIT(5)   BIT(6)   BIT(7)  >;
+			#pinmux-cells = <2>;
+			gpio-group;
+		};
+
+		pinctrlj: pinctrl@f01658 {
+			compatible = "ite,it8xxx2-pinctrl-func";
+			reg = <0x00f01658 8     /* GPCR */
+			       NO_FUNC    1>;
+			func3-gcr =     <0xf016f1 0xf016fe NO_FUNC  NO_FUNC
+					 NO_FUNC  NO_FUNC  0xf016f4 0xf016d1>;
+			func3-en-mask = <BIT(7)   BIT(3)   0        0
+					 0        0        BIT(1)   BIT(3)  >;
+			func4-gcr =     <NO_FUNC  NO_FUNC  NO_FUNC  NO_FUNC
+					 NO_FUNC  NO_FUNC  0xf016ed 0xf016f0>;
+			func4-en-mask = <0        0        0        0
+					 0        0        BIT(3)   BIT(4)  >;
+			volt-sel =      <0xf016dd NO_FUNC  0xf016dd 0xf016dd
+					 0xf016dd 0xf016dd 0xf016dd 0xf016dd>;
+			volt-sel-mask = <BIT(0)   0        BIT(2)   BIT(3)
+					 BIT(4)   BIT(5)   BIT(6)   BIT(7)  >;
+			#pinmux-cells = <2>;
+			gpio-group;
+		};
+
+		pinctrlk: pinctrl@f01d2d {
+			compatible = "ite,it8xxx2-pinctrl-func";
+			reg = <0x00f01d2d 1   /* KSOLGCTRL */
+			       0x00f01d02 1>; /* KSOCTRL */
+			pp-od-mask = <BIT(0)>;
+			pullup-mask = <BIT(2)>;
+			#pinmux-cells = <2>;
+		};
+
+		pinctrll: pinctrl@f01d2e {
+			compatible = "ite,it8xxx2-pinctrl-func";
+			reg = <0x00f01d2e 1   /* KSOHGCTRL */
+			       0x00f01d02 1>; /* KSOCTRL */
+			pp-od-mask = <BIT(0)>;
+			pullup-mask = <BIT(2)>;
+			#pinmux-cells = <2>;
+		};
+
+		pinctrlm: pinctrl@f016a0 {
+			compatible = "ite,it8xxx2-pinctrl-func";
+			reg = <0x00f016a0 8     /* GPCR */
+			       NO_FUNC    1>;
+			func3-gcr =     <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
+					 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
+			func3-en-mask = <0       0       0       0
+					 0       0       0       0      >;
+			func4-gcr =     <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
+					 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
+			func4-en-mask = <0       0       0       0
+					 0       0       0       0      >;
+			volt-sel =      <NO_FUNC NO_FUNC NO_FUNC NO_FUNC
+					 NO_FUNC NO_FUNC NO_FUNC NO_FUNC>;
+			volt-sel-mask = <0       0       0       0
+					 0       0       0       0      >;
+			#pinmux-cells = <2>;
+			gpio-group;
+		};
+
+		pinctrln: pinctrl@f01d2c {
+			compatible = "ite,it8xxx2-pinctrl-func";
+			reg = <0x00f01d2c 1   /* KSIGCTRL */
+			       0x00f01d05 1>; /* KSICTRL */
+			pp-od-mask = <NO_FUNC>;
+			pullup-mask = <BIT(2)>;
+			#pinmux-cells = <2>;
+		};
+
+		wuc1: wakeup-controller@f01b00 {
+			compatible = "ite,it51xxx-wuc";
+			reg = <0x00f01b00 1   /* WUEMR1 */
+			       0x00f01b04 1   /* WUESR1 */
+			       0x00f01b08 1   /* WUENR1 */
+			       0x00f01b3c 1>; /* WUBEMR1 */
+			wakeup-controller;
+			#wuc-cells = <1>;
+		};
+
+		wuc2: wakeup-controller@f01b01 {
+			compatible = "ite,it51xxx-wuc";
+			reg = <0x00f01b01             1   /* WUEMR2 */
+			       0x00f01b05             1   /* WUESR2 */
+			       IT51XXX_WUC_UNUSED_REG 1   /* WUENR2 */
+			       0x00f01b3d             1>; /* WUBEMR2 */
+			wakeup-controller;
+			#wuc-cells = <1>;
+		};
+
+		wuc3: wakeup-controller@f01b02 {
+			compatible = "ite,it51xxx-wuc";
+			reg = <0x00f01b02 1   /* WUEMR3 */
+			       0x00f01b06 1   /* WUESR3 */
+			       0x00f01b0a 1   /* WUENR3 */
+			       0x00f01b3e 1>; /* WUBEMR3 */
+			wakeup-controller;
+			#wuc-cells = <1>;
+		};
+
+		wuc4: wakeup-controller@f01b03 {
+			compatible = "ite,it51xxx-wuc";
+			reg = <0x00f01b03 1   /* WUEMR4 */
+			       0x00f01b07 1   /* WUESR4 */
+			       0x00f01b0b 1   /* WUENR4 */
+			       0x00f01b3f 1>; /* WUBEMR4 */
+			wakeup-controller;
+			#wuc-cells = <1>;
+		};
+
+		wuc6: wakeup-controller@f01b10 {
+			compatible = "ite,it51xxx-wuc";
+			reg = <0x00f01b10             1   /* WUEMR6 */
+			       0x00f01b11             1   /* WUESR6 */
+			       IT51XXX_WUC_UNUSED_REG 1   /* WUENR6 */
+			       0x00f01b13             1>; /* WUBEMR6 */
+			wakeup-controller;
+			#wuc-cells = <1>;
+		};
+
+		wuc7: wakeup-controller@f01b14 {
+			compatible = "ite,it51xxx-wuc";
+			reg = <0x00f01b14             1   /* WUEMR7 */
+			       0x00f01b15             1   /* WUESR7 */
+			       IT51XXX_WUC_UNUSED_REG 1   /* WUENR7 */
+			       0x00f01b17             1>; /* WUBEMR7 */
+			wakeup-controller;
+			both-edge-trigger;
+			#wuc-cells = <1>;
+		};
+
+		wuc8: wakeup-controller@f01b18 {
+			compatible = "ite,it51xxx-wuc";
+			reg = <0x00f01b18             1   /* WUEMR8 */
+			       0x00f01b19             1   /* WUESR8 */
+			       IT51XXX_WUC_UNUSED_REG 1   /* WUENR8 */
+			       0x00f01b1b             1>; /* WUBEMR8 */
+			wakeup-controller;
+			#wuc-cells = <1>;
+		};
+
+		wuc9: wakeup-controller@f01b1c {
+			compatible = "ite,it51xxx-wuc";
+			reg = <0x00f01b1c             1   /* WUEMR9 */
+			       0x00f01b1d             1   /* WUESR9 */
+			       IT51XXX_WUC_UNUSED_REG 1   /* WUENR9 */
+			       0x00f01b1f             1>; /* WUBEMR9 */
+			wakeup-controller;
+			#wuc-cells = <1>;
+		};
+
+		wuc10: wakeup-controller@f01b20 {
+			compatible = "ite,it51xxx-wuc";
+			reg = <0x00f01b20             1   /* WUEMR10 */
+			       0x00f01b21             1   /* WUESR10 */
+			       IT51XXX_WUC_UNUSED_REG 1   /* WUENR10 */
+			       0x00f01b23             1>; /* WUBEMR10 */
+			wakeup-controller;
+			both-edge-trigger;
+			#wuc-cells = <1>;
+		};
+
+		wuc11: wakeup-controller@f01b24 {
+			compatible = "ite,it51xxx-wuc";
+			reg = <0x00f01b24             1   /* WUEMR11 */
+			       0x00f01b25             1   /* WUESR11 */
+			       IT51XXX_WUC_UNUSED_REG 1   /* WUENR11 */
+			       0x00f01b27             1>; /* WUBEMR11 */
+			wakeup-controller;
+			#wuc-cells = <1>;
+		};
+
+		wuc12: wakeup-controller@f01b28 {
+			compatible = "ite,it51xxx-wuc";
+			reg = <0x00f01b28             1   /* WUEMR12 */
+			       0x00f01b29             1   /* WUESR12 */
+			       IT51XXX_WUC_UNUSED_REG 1   /* WUENR12 */
+			       0x00f01b2b             1>; /* WUBEMR12 */
+			wakeup-controller;
+			both-edge-trigger;
+			#wuc-cells = <1>;
+		};
+
+		wuc13: wakeup-controller@f01b2c {
+			compatible = "ite,it51xxx-wuc";
+			reg = <0x00f01b2c             1   /* WUEMR13 */
+			       0x00f01b2d             1   /* WUESR13 */
+			       IT51XXX_WUC_UNUSED_REG 1   /* WUENR13 */
+			       0x00f01b2f             1>; /* WUBEMR13 */
+			wakeup-controller;
+			#wuc-cells = <1>;
+		};
+
+		wuc14: wakeup-controller@f01b30 {
+			compatible = "ite,it51xxx-wuc";
+			reg = <0x00f01b30             1   /* WUEMR14 */
+			       0x00f01b31             1   /* WUESR14 */
+			       IT51XXX_WUC_UNUSED_REG 1   /* WUENR14 */
+			       0x00f01b33             1>; /* WUBEMR14 */
+			wakeup-controller;
+			#wuc-cells = <1>;
+		};
+
+		wuc15: wakeup-controller@f01b34 {
+			compatible = "ite,it51xxx-wuc";
+			reg = <0x00f01b34             1   /* WUEMR15 */
+			       0x00f01b35             1   /* WUESR15 */
+			       IT51XXX_WUC_UNUSED_REG 1   /* WUENR15 */
+			       0x00f01b37             1>; /* WUBEMR15 */
+			wakeup-controller;
+			#wuc-cells = <1>;
+		};
+
+		wuc16: wakeup-controller@f01b38 {
+			compatible = "ite,it51xxx-wuc";
+			reg = <0x00f01b38             1   /* WUEMR16 */
+			       0x00f01b39             1   /* WUESR16 */
+			       IT51XXX_WUC_UNUSED_REG 1   /* WUENR16 */
+			       0x00f01b3b             1>; /* WUBEMR16 */
+			wakeup-controller;
+			#wuc-cells = <1>;
+		};
+
+		wuc_fake: wakeup-controller@0 {
+			compatible = "ite,it51xxx-wuc";
+			reg = <0 1
+			       0 1
+			       0 1
+			       0 1>;
+			#wuc-cells = <1>;
+		};
+
+		ecpm: clock-controller@f01e00 {
+			compatible = "ite,it51xxx-ecpm";
+			reg = <0x00f01e00 0x0a>;
+			pll-frequency = <PLL_48000_KHZ>;
+			#clock-cells = <2>;
+		};
+
+		gctrl: general-control@f02000 {
+			compatible = "ite,it51xxx-gctrl";
+			reg = <0x00f02000 0x100>;
+		};
+
+		uart1: uart@f02700 {
+			compatible = "ns16550";
+			reg = <0x00f02700 0x0020>;
+			status = "disabled";
+			current-speed = <115200>;
+			clock-frequency = <1843200>;
+			interrupts = <38 IRQ_TYPE_EDGE_RISING>;
+			interrupt-parent = <&intc>;
+			reg-shift = <0>;
+		};
+
+		ite_uart1_wrapper: uartwrapper@f02720 {
+			compatible = "ite,it51xxx-uart";
+			reg = <0x00f02720 0x0020>;
+			status = "disabled";
+			wucctrl = <&wuc_wu86>; /* GPC7 */
+			interrupts = <IT51XXX_IRQ_WU86 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			clocks = <&ecpm IT51XXX_ECPM_CGCTRL3R_OFF BIT(2)>;
+		};
+
+		uart2: uart@f02800 {
+			compatible = "ns16550";
+			reg = <0x00f02800 0x0020>;
+			status = "disabled";
+			current-speed = <460800>;
+			clock-frequency = <1843200>;
+			interrupts = <39 IRQ_TYPE_EDGE_RISING>;
+			interrupt-parent = <&intc>;
+			reg-shift = <0>;
+		};
+
+		ite_uart2_wrapper: uartwrapper@f02820 {
+			compatible = "ite,it51xxx-uart";
+			reg = <0x00f02820 0x0020>;
+			status = "disabled";
+			wucctrl = <&wuc_wu61>; /* GPH1 */
+			interrupts = <IT51XXX_IRQ_WU61 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-parent = <&intc>;
+			clocks = <&ecpm IT51XXX_ECPM_CGCTRL3R_OFF BIT(2)>;
+		};
+
+		intc: interrupt-controller@f04300 {
+			compatible = "ite,it51xxx-intc";
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			reg = <0x00f04300 0x0100>;
+		};
+
+		timer: timer@f04700 {
+			compatible = "ite,it51xxx-timer";
+			reg = <0x00f04700 0xff>;
+			interrupts = <IT51XXX_IRQ_TIMER3_DW IRQ_TYPE_EDGE_RISING   /* Event timer */
+				      IT51XXX_IRQ_TIMER4_DW IRQ_TYPE_EDGE_RISING   /* Free run */
+				      IT51XXX_IRQ_TIMER5_DW IRQ_TYPE_EDGE_RISING   /* Busy wait */
+				      IT51XXX_IRQ_TIMER6_DW IRQ_TYPE_EDGE_RISING   /* Busy wait */
+				      IT51XXX_IRQ_TIMER7_DW IRQ_TYPE_EDGE_RISING>;
+			interrupt-parent = <&intc>;
+		};
+
+		kbd: kbd@f01d00 {
+			compatible = "ite,it51xxx-kbd";
+			reg = <0x00f01d00 0x29>;
+			interrupt-parent = <&intc>;
+			interrupts = <IT51XXX_IRQ_WKINTC IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			wucctrl = <&wuc_wu30   /* KSI[0] */
+				   &wuc_wu31   /* KSI[1] */
+				   &wuc_wu32   /* KSI[2] */
+				   &wuc_wu33   /* KSI[3] */
+				   &wuc_wu34   /* KSI[4] */
+				   &wuc_wu35   /* KSI[5] */
+				   &wuc_wu36   /* KSI[6] */
+				   &wuc_wu37>; /* KSI[7] */
+			kso16-gpios = <&gpioc 3 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
+			kso17-gpios = <&gpioc 5 (GPIO_OPEN_DRAIN | GPIO_PULL_UP)>;
+		};
+
+		twd0: watchdog@f04780 {
+			compatible = "ite,it51xxx-watchdog";
+			reg = <0x00f04780 0x20>;
+			interrupts = <IT51XXX_IRQ_TIMER1_DW IRQ_TYPE_EDGE_RISING>; /* Warn timer */
+			interrupt-parent = <&intc>;
+		};
+
+		tach0: tach@f046c0 {
+			compatible = "ite,it51xxx-tach";
+			reg = <0x00f046c0 0xf>;
+			status = "disabled";
+		};
+
+		tach1: tach@f046d0 {
+			compatible = "ite,it51xxx-tach";
+			reg = <0x00f046d0 0xf>;
+			status = "disabled";
+		};
+
+		tach2: tach@f046e0 {
+			compatible = "ite,it51xxx-tach";
+			reg = <0x00f046e0 0xf>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/dts/riscv/ite/it8xxx2-pinctrl-map.dtsi b/dts/riscv/ite/it8xxx2-pinctrl-map.dtsi
index 5492f19610a..73ec8462d4a 100644
--- a/dts/riscv/ite/it8xxx2-pinctrl-map.dtsi
+++ b/dts/riscv/ite/it8xxx2-pinctrl-map.dtsi
@@ -222,11 +222,11 @@
 		drive-open-drain;
 		bias-pull-up;
 	};
-	kso16_gpc3_default: kso16_gpc3_default {
+	kso16_default: kso16_gpc3_default: kso16_default {
 		pinmuxs = <&pinctrlc 3 IT8XXX2_ALT_FUNC_1>;
 		bias-pull-up;
 	};
-	kso17_gpc5_default: kso17_gpc5_default {
+	kso17_default: kso17_gpc5_default: kso17_default {
 		pinmuxs = <&pinctrlc 5 IT8XXX2_ALT_FUNC_1>;
 		bias-pull-up;
 	};
@@ -304,10 +304,10 @@
 	kso15_sleep: kso15_sleep {
 		pinmuxs = <&pinctrlksoh 7 IT8XXX2_ALT_DEFAULT>;
 	};
-	kso16_gpc3_sleep: kso16_gpc3_sleep {
+	kso16_sleep: kso16_gpc3_sleep: kso16_sleep {
 		pinmuxs = <&pinctrlc 3 IT8XXX2_ALT_DEFAULT>;
 	};
-	kso17_gpc5_sleep: kso17_gpc5_sleep {
+	kso17_sleep: kso17_gpc5_sleep: kso17_sleep {
 		pinmuxs = <&pinctrlc 5 IT8XXX2_ALT_DEFAULT>;
 	};
 
diff --git a/dts/riscv/ite/it8xxx2.dtsi b/dts/riscv/ite/it8xxx2.dtsi
index dfbebc7d615..05610ce9843 100644
--- a/dts/riscv/ite/it8xxx2.dtsi
+++ b/dts/riscv/ite/it8xxx2.dtsi
@@ -153,6 +153,15 @@
 			interrupt-parent = <&intc>;
 		};
 
+		counter0: counter@f01f30 {
+			compatible = "ite,it8xxx2-counter";
+			reg = <0xf01f30 0x10>;
+			interrupts = <IT8XXX2_IRQ_TIMER7 IRQ_TYPE_EDGE_RISING   /* Alarm timer */
+				      IT8XXX2_IRQ_TIMER8 IRQ_TYPE_EDGE_RISING>; /* Top timer */
+			interrupt-parent = <&intc>;
+			status = "disabled";
+		};
+
 		gpioa: gpio@f01601 {
 			compatible = "ite,it8xxx2-gpio";
 			reg = <0x00f01601 1   /* GPDR (set) */
diff --git a/dts/riscv/lowrisc/opentitan_earlgrey.dtsi b/dts/riscv/lowrisc/opentitan_earlgrey.dtsi
index e3b79bbaf06..11c1f784a73 100644
--- a/dts/riscv/lowrisc/opentitan_earlgrey.dtsi
+++ b/dts/riscv/lowrisc/opentitan_earlgrey.dtsi
@@ -44,12 +44,11 @@
 			reg = <0x10000000 0x10000>;
 		};
 
-		mtimer: timer@40100000 {
-			compatible = "lowrisc,machine-timer";
-			reg = <0x40100000 0x200>;
-			interrupts = <7 0>;
-			interrupt-parent = <&hlic>;
-			status = "disabled";
+		mtimer: timer@40100110 {
+			compatible = "riscv,machine-timer";
+			reg = <0x40100110 0x8 0x40100118 0x8>;
+			reg-names = "mtime", "mtimecmp";
+			interrupts-extended = <&hlic 7>;
 		};
 
 		aontimer: aontimer@40470000 {
diff --git a/dts/riscv/microchip/microchip-miv.dtsi b/dts/riscv/microchip/microchip-miv.dtsi
index 305145b7e44..aa42d989c7a 100644
--- a/dts/riscv/microchip/microchip-miv.dtsi
+++ b/dts/riscv/microchip/microchip-miv.dtsi
@@ -48,6 +48,13 @@
 			reg = <0x44000000 0x10000>;
 		};
 
+		mtimer: timer@4400bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&hlic 7>;
+			reg = <0x4400bff8 0x8 0x44004000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
+
 		plic: interrupt-controller@40000000 {
 			compatible = "sifive,plic-1.0.0";
 			#address-cells = <0>;
diff --git a/dts/riscv/microchip/mpfs.dtsi b/dts/riscv/microchip/mpfs.dtsi
index f22c7604bb3..e3ff65dd577 100644
--- a/dts/riscv/microchip/mpfs.dtsi
+++ b/dts/riscv/microchip/mpfs.dtsi
@@ -114,6 +114,17 @@
 			reg = <0x2000000 0x10000>;
 		};
 
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&hlic0 7
+						&hlic1 7
+						&hlic2 7
+						&hlic3 7
+						&hlic4 7>;
+			reg = <0x200bff8 0x8 0x2004000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
+
 		plic: interrupt-controller@c000000 {
 			compatible = "sifive,plic-1.0.0";
 			#interrupt-cells = <2>;
diff --git a/dts/riscv/neorv32.dtsi b/dts/riscv/neorv32.dtsi
index 31fb06b1c49..34c9088faee 100644
--- a/dts/riscv/neorv32.dtsi
+++ b/dts/riscv/neorv32.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
+ * Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,8 +19,7 @@
 		#size-cells = <0>;
 
 		cpu0: cpu@0 {
-			compatible = "neorv32-cpu", "riscv";
-			riscv,isa = "rv32imc_zicsr";
+			compatible = "neorv32,cpu", "riscv";
 			reg = <0>;
 			device_type = "cpu";
 
@@ -64,77 +63,76 @@
 		#size-cells = <1>;
 		ranges;
 
-		mtimer: timer@ffffff90 {
-			compatible = "neorv32-machine-timer";
-			reg = <0xffffff90 0x10>;
-			interrupts = <7>;
+		imem: memory@0 {
+			compatible = "soc-nv-flash", "mmio-sram";
+			status = "disabled";
+		};
+
+		dmem: memory@80000000 {
+			compatible = "mmio-sram";
+			status = "disabled";
+		};
+
+		bootrom: rom@ffe00000 {
+			compatible = "neorv32,bootrom", "mmio-sram";
+			status = "disabled";
+			reg = <0xffe00000 0x10000>;
+		};
+
+		clint: clint@fff40000 {
+			compatible = "neorv32,clint", "sifive,clint0";
+			status = "disabled";
+			reg = <0xfff40000 0x10000>;
+			interrupts-extended = <&intc 3>;
+		};
+
+		mtimer: timer@fff4bff8 {
+			compatible = "riscv,machine-timer";
+			status = "disabled";
+			reg = <0xfff4bff8 0x8 0xfff44000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+			interrupts-extended = <&intc 7>;
 		};
 
-		uart0: serial@ffffffa0 {
-			compatible = "neorv32-uart";
+		uart0: serial@fff50000 {
+			compatible = "neorv32,uart";
 			status = "disabled";
-			reg = <0xffffffa0 8>;
+			reg = <0xfff50000 0x10000>;
 			interrupts = <2>, <3>;
 			interrupt-names = "RX", "TX";
 			syscon = <&sysinfo>;
 		};
 
-		trng: rng@ffffffb8 {
-			compatible = "neorv32-trng";
+		uart1: serial@fff60000 {
+			compatible = "neorv32,uart";
 			status = "disabled";
-			reg = <0xffffffb8 4>;
+			reg = <0xfff60000 0x10000>;
+			interrupts = <4>, <5>;
+			interrupt-names = "RX", "TX";
 			syscon = <&sysinfo>;
 		};
 
-		gpio: gpio {
-			compatible = "simple-bus";
-			gpio-map-mask = <0xffffffe0 0xffffffc0>;
-			gpio-map-pass-thru = <0x1f 0x3f>;
-			gpio-map = <
-				0x00 0x0 &gpio_lo 0x0 0x0
-				0x20 0x0 &gpio_hi 0x0 0x0
-			>;
-			#gpio-cells = <2>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges;
-
-			gpio_lo: gpio@ffffffc0 {
-				compatible = "neorv32-gpio";
-				status = "disabled";
-				reg = <0xffffffc0 4 0xffffffc8 4>;
-				reg-names = "input", "output";
-				gpio-controller;
-				ngpios = <32>;
-				syscon = <&sysinfo>;
-				#gpio-cells = <2>;
-			};
-
-			gpio_hi: gpio@ffffffc4 {
-				compatible = "neorv32-gpio";
-				status = "disabled";
-				reg = <0xffffffc4 4 0xffffffcc 4>;
-				reg-names = "input", "output";
-				gpio-controller;
-				ngpios = <32>;
-				syscon = <&sysinfo>;
-				#gpio-cells = <2>;
-			};
+		trng: rng@fffa0000 {
+			compatible = "neorv32,trng";
+			status = "disabled";
+			reg = <0xfffa0000 0x10000>;
+			syscon = <&sysinfo>;
 		};
 
-		uart1: serial@ffffffd0 {
-			compatible = "neorv32-uart";
+		gpio: gpio@fffc0000 {
+			compatible = "neorv32,gpio";
 			status = "disabled";
-			reg = <0xffffffd0 8>;
-			interrupts = <4>, <5>;
-			interrupt-names = "RX", "TX";
+			reg = <0xfffc0000 0x10000>;
 			syscon = <&sysinfo>;
+			gpio-controller;
+			ngpios = <32>;
+			#gpio-cells = <2>;
 		};
 
-		sysinfo: syscon@ffffffe0 {
+		sysinfo: syscon@fffe0000 {
 			compatible = "neorv-sysinfo", "syscon";
 			status = "okay";
-			reg = <0xffffffe0 32>;
+			reg = <0xfffe0000 0x10000>;
 		};
 	};
 };
diff --git a/dts/riscv/niosv/niosv-g.dtsi b/dts/riscv/niosv/niosv-g.dtsi
index 2022e984ff5..e0b1435fabe 100644
--- a/dts/riscv/niosv/niosv-g.dtsi
+++ b/dts/riscv/niosv/niosv-g.dtsi
@@ -44,9 +44,10 @@
 		};
 
 		mtimer: machine-timer@90000 {
-			compatible = "niosv-machine-timer";
-			reg = <0x90000 0x10>;
-			interrupts = <7>;
+			compatible = "riscv,machine-timer";
+			reg = <0x90000 0x8 0x90008 0x8>;
+			reg-names = "mtime", "mtimecmp";
+			interrupts-extended = <&intc 7>;
 		};
 
 		uart0: serial@90078 {
diff --git a/dts/riscv/niosv/niosv-m.dtsi b/dts/riscv/niosv/niosv-m.dtsi
index e6594a23546..f2870921e96 100644
--- a/dts/riscv/niosv/niosv-m.dtsi
+++ b/dts/riscv/niosv/niosv-m.dtsi
@@ -44,9 +44,10 @@
 		};
 
 		mtimer: machine-timer@90000 {
-			compatible = "niosv-machine-timer";
-			reg = <0x90000 0x10>;
-			interrupts = <7>;
+			compatible = "riscv,machine-timer";
+			reg = <0x90000 0x8 0x90008 0x8>;
+			reg-names = "mtime", "mtimecmp";
+			interrupts-extended = <&intc 7>;
 		};
 
 		uart0: serial@90078 {
diff --git a/dts/riscv/openhwgroup/cv32a6.dtsi b/dts/riscv/openhwgroup/cv32a6.dtsi
new file mode 100644
index 00000000000..83ac4bd70fb
--- /dev/null
+++ b/dts/riscv/openhwgroup/cv32a6.dtsi
@@ -0,0 +1,40 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright 2024 CISPA Helmholtz Center for Information Security
+ */
+
+#include <freq.h>
+#include "cva6.dtsi"
+
+/*
+ * Least common denominator of CVA6 32-bit CPUs: no FPU, no compressed instructions,
+ * no MMU, no PMP.
+ * Boards can overwrite the node if additional configurations are available.
+ */
+/ {
+	cpus_0: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu_0: cpu@0 {
+			clock-frequency = <DT_FREQ_M(50)>;
+			timebase-frequency = <DT_FREQ_M(25)>;
+			device_type = "cpu";
+			compatible = "openhwgroup,cva6";
+			riscv,isa = "rv32ima";
+			/* overwrite in board configuration if sv32 MMU is enabled */
+			mmu-type = "riscv,none";
+			reg = <0>;
+
+			status = "okay";
+
+			hlic: interrupt-controller {
+				#interrupt-cells = <0x01>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/dts/riscv/openhwgroup/cv64a6.dtsi b/dts/riscv/openhwgroup/cv64a6.dtsi
new file mode 100644
index 00000000000..ff51969c151
--- /dev/null
+++ b/dts/riscv/openhwgroup/cv64a6.dtsi
@@ -0,0 +1,38 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright 2024 CISPA Helmholtz Center for Information Security
+ */
+
+#include <freq.h>
+#include "cva6.dtsi"
+/*
+ * Application-class configuration of CVA6 64-bit CPUs:
+ * FPU for 32-bit and 64-bit floats, SV39 MMU.
+ *
+ */
+/ {
+	cpus_0: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu_0: cpu@0 {
+			clock-frequency = <DT_FREQ_M(50)>;
+			timebase-frequency = <DT_FREQ_M(25)>;
+			device_type = "cpu";
+			compatible = "openhwgroup,cva6";
+			riscv,isa = "rv64imafdc";
+			mmu-type = "riscv,sv39";
+			reg = <0>;
+
+			status = "okay";
+
+			hlic: interrupt-controller {
+				#interrupt-cells = <0x01>;
+				interrupt-controller;
+				compatible = "riscv,cpu-intc";
+				status = "okay";
+			};
+		};
+	};
+};
diff --git a/dts/riscv/openhwgroup/cva6.dtsi b/dts/riscv/openhwgroup/cva6.dtsi
new file mode 100644
index 00000000000..22dd17e6d86
--- /dev/null
+++ b/dts/riscv/openhwgroup/cva6.dtsi
@@ -0,0 +1,159 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ * Copyright 2024 CISPA Helmholtz Center for Information Security
+ */
+
+#include <freq.h>
+
+/*
+ * CVA6 SoC without CPU, which comes in 32 and 64 bit variants
+ */
+/ {
+	#address-cells = <0x01>;
+	#size-cells = <0x01>;
+
+	clocks {
+
+		clk_cpu {
+			#clock-cells = <0x00>;
+			clock-frequency = <DT_FREQ_M(50)>;
+			compatible = "fixed-clock";
+		};
+
+		clk_bus: clk_bus_0 {
+			#clock-cells = <0x00>;
+			clock-frequency = <DT_FREQ_M(50)>;
+			compatible = "fixed-clock";
+		};
+	};
+
+	soc {
+		#address-cells = <0x01>;
+		#size-cells = <0x01>;
+		ranges;
+
+		/* Xilinx MIG memory controller */
+		memory0: memory@80000000 {
+			device_type = "memory";
+			reg = <0x80000000 0x40000000>;
+			status = "okay";
+		};
+
+		/* RISC-V Platform-level interrupt controller */
+		plic: interrupt-controller@c000000 {
+			compatible = "sifive,plic-1.0.0";
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			interrupts-extended = <&hlic 11 &hlic 9>;
+			reg = <0x0c000000 0x4000000>;
+			riscv,max-priority = <7>;
+			riscv,ndev = <30>;
+			status = "okay";
+		};
+
+		/* USB UART */
+		uart0: serial@10000000 {
+			clock-frequency = <50000000>;
+			clocks = <&clk_bus>;
+			compatible = "ns16550";
+			current-speed = <115200>;
+			device_type = "serial";
+			reg = <0x10000000 0x10000>;
+			reg-shift = <0x02>;
+			parity = "none";
+			stop-bits = "1";
+			data-bits = <8>;
+			interrupt-parent = <&plic>;
+			interrupts = <1 0x04>;
+			status = "disabled";
+		};
+
+		/* SPI controller, connected to SD card */
+		spi0: axi_quad_spi@20000000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "xlnx,xps-spi-2.00.a";
+			reg = <0x20000000 0x10000>;
+			xlnx,num-ss-bits = <0x01>;
+			xlnx,num-transfer-bits = <0x8>;
+			interrupts=<2 0x2>;
+			interrupt-parent=<&plic>;
+			clocks=<&clk_bus>;
+			status = "disabled";
+		};
+
+		/*
+		 * Core-local interrupt controller according to RISC-V spec
+		 */
+		clint: clint@2000000 {
+			compatible = "sifive,clint0";
+			reg = <0x2000000 0x40000>;
+			interrupts-extended = <&hlic 3 &hlic 7>;
+			status = "disabled";
+		};
+
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&hlic 7>;
+			reg = <0x200bff8 0x8 0x2004000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+			status = "disabled";
+		};
+
+		/*
+		 * Xilinx AXI DMA.
+		 * Part of the Xilinx AXI Ethernet Subsystem.
+		 * Only on CISPA board.
+		 */
+		dma0: dma@41e00000 {
+			#dma-cells = <0x01>;
+			clock-frequency = <DT_FREQ_M(50)>;
+			clock-names = "s_axi_lite_aclk";
+			clocks = <&clk_bus>;
+			compatible = "xlnx,eth-dma";
+			reg = <0x41e00000 0x10000>;
+			xlnx,addrwidth = <0x40>;
+			xlnx,include-dre;
+			xlnx,num-queues = <0x1>;
+			interrupt-parent = <&plic>;
+			// TX - RX
+			// active-high level-triggered
+			interrupts = <8 4>, <9 4>;
+			// TX and RX
+			dma-channels = <2>;
+			status = "disabled";
+		};
+
+		/*
+		 * LowRISC ethernet subsystem.
+		 * Only on OpenHW Group board.
+		 */
+		eth: lowrisc-eth@30000000 {
+			compatible = "lowrisc-eth";
+			device_type = "network";
+			interrupt-parent = <&plic>;
+			interrupts = <3 0>;
+			reg = <0x0 0x30000000 0x0 0x8000>;
+			status = "disabled";
+		};
+
+		/* Xilinx GPIO, connected to LEDs */
+		xlnx_gpio: gpio@40000000 {
+			#gpio-cells = <2>;
+			compatible = "xlnx,xps-gpio-1.00.a";
+			gpio-controller ;
+			reg = <0x0 0x40000000 0x0 0x10000 >;
+			xlnx,all-inputs = <0x0>;
+			xlnx,all-inputs-2 = <0x0>;
+			xlnx,dout-default = <0x0>;
+			xlnx,dout-default-2 = <0x0>;
+			xlnx,gpio-width = <0x8>;
+			xlnx,gpio2-width = <0x8>;
+			xlnx,is-dual = <0x1>;
+			xlnx,tri-default = <0xffffffff>;
+			xlnx,tri-default-2 = <0xffffffff>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/dts/riscv/qemu/virt-riscv.dtsi b/dts/riscv/qemu/virt-riscv.dtsi
index b810f9fe7dc..d104f44e07d 100644
--- a/dts/riscv/qemu/virt-riscv.dtsi
+++ b/dts/riscv/qemu/virt-riscv.dtsi
@@ -193,5 +193,19 @@
 					       &hlic6 0x03 &hlic6 0x07
 					       &hlic7 0x03 &hlic7 0x07>;
 		};
+
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&hlic0 7
+						&hlic1 7
+						&hlic2 7
+						&hlic3 7
+						&hlic4 7
+						&hlic5 7
+						&hlic6 7
+						&hlic7 7>;
+			reg = <0x200bff8 0x8 0x2004000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
 	};
 };
diff --git a/dts/riscv/renode_riscv32_virt.dtsi b/dts/riscv/renode_riscv32_virt.dtsi
index a0db375501f..f819ca441b7 100644
--- a/dts/riscv/renode_riscv32_virt.dtsi
+++ b/dts/riscv/renode_riscv32_virt.dtsi
@@ -50,6 +50,13 @@
 			reg = <0x2000000 0x10000>;
 		};
 
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&hlic 7>;
+			reg = <0x200bff8 0x8 0x2004000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
+
 		plic0: interrupt-controller@c000000 {
 			compatible = "sifive,plic-1.0.0";
 			#address-cells = <0>;
diff --git a/dts/riscv/riscv32-litex-vexriscv.dtsi b/dts/riscv/riscv32-litex-vexriscv.dtsi
index 8557d2ecb83..6d144b69aba 100644
--- a/dts/riscv/riscv32-litex-vexriscv.dtsi
+++ b/dts/riscv/riscv32-litex-vexriscv.dtsi
@@ -236,6 +236,25 @@
 			#size-cells = <0>;
 			status = "disabled";
 		};
+		i2c1: i2c@e000d800 {
+			compatible = "litex,litei2c";
+			reg = <0xe000d800 0x4>,
+				<0xe000d804 0x4>,
+				<0xe000d808 0x4>,
+				<0xe000d80c 0x4>,
+				<0xe000d810 0x4>,
+				<0xe000d814 0x4>;
+			reg-names = "phy_speed_mode",
+				"master_active",
+				"master_settings",
+				"master_addr",
+				"master_rxtx",
+				"master_status";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
 		gpio_out: gpio@e0005800 {
 			compatible = "litex,gpio";
 			reg = <0xe0005800 0x4>;
@@ -298,7 +317,7 @@
 				"rx_stat",
 				"rx_conf",
 				"fifo";
-			fifo_depth = <256>;
+			fifo-depth = <256>;
 			status = "disabled";
 		};
 		i2s_tx: i2s_tx@e000b000 {
@@ -321,7 +340,7 @@
 				"tx_stat",
 				"tx_conf",
 				"fifo";
-			fifo_depth = <256>;
+			fifo-depth = <256>;
 			status = "disabled";
 		};
 		clock-outputs {
diff --git a/dts/riscv/sensry/ganymed-sy1xx.dtsi b/dts/riscv/sensry/ganymed-sy1xx.dtsi
index 5e652c56a15..a8dcb76f4f9 100644
--- a/dts/riscv/sensry/ganymed-sy1xx.dtsi
+++ b/dts/riscv/sensry/ganymed-sy1xx.dtsi
@@ -3,10 +3,16 @@
 
 /dts-v1/;
 
+#include <zephyr/dt-bindings/pinctrl/sy1xx-pinctrl.h>
+
 / {
 	#address-cells = <1>;
 	#size-cells = <0>;
 
+	chosen {
+		zephyr,entropy = &trng;
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -52,7 +58,7 @@
 			reg = <0x1a10b040 0x04>;
 			interrupt-parent = <&event0>;
 			interrupts = <10 0>;
-			ticks_us = <1000>;
+			ticks-us = <1000>;
 		};
 
 		timer1: timer@1a10b044 {
@@ -60,7 +66,7 @@
 			reg = <0x1a10b044 0x04>;
 			interrupt-parent = <&event0>;
 			interrupts = <11 0>;
-			ticks_us = <1000>;
+			ticks-us = <1000>;
 		};
 
 		uart0: uart@1a102000 {
@@ -87,11 +93,88 @@
 			status = "okay";
 		};
 
+		i2c0: i2c@1a102500 {
+			compatible = "sensry,sy1xx-i2c";
+			reg = <0x1a102500 0x80>;
+			instance = <0>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+		};
+
+		i2c1: i2c@1a102580 {
+			compatible = "sensry,sy1xx-i2c";
+			reg = <0x1a102580 0x80>;
+			instance = <1>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+		};
+
+		i2c2: i2c@1a102600 {
+			compatible = "sensry,sy1xx-i2c";
+			reg = <0x1a102600 0x80>;
+			instance = <2>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+		};
+
+		i2c3: i2c@1a102680 {
+			compatible = "sensry,sy1xx-i2c";
+			reg = <0x1a102680 0x80>;
+			instance = <3>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+		};
+
+		trng: random@1d030100 {
+			compatible = "sensry,sy1xx-trng";
+			reg = <0x1d030100 0x100>;
+			status = "okay";
+		};
+
+		gpio0: gpio@1a101000 {
+			compatible = "sensry,sy1xx-gpio";
+			gpio-controller;
+			#gpio-cells = <2>;
+			reg = <0x1a101000 0x20>;
+			pad-cfg = <SY1XX_GPIO0_PAD_CFG0>;
+			status = "okay";
+			ngpios = <32>;
+		};
+
 		pinctrl: pinctrl@1a104000 {
 			compatible = "sensry,sy1xx-pinctrl";
 			reg = <0x1a104000 0x1000>;
 			status = "okay";
 		};
 
+		mdio0: mdio@1a120020 {
+			compatible = "sensry,sy1xx-mdio";
+			reg = <0x1a120020 0x20>;
+			status = "disabled";
+
+			clock-frequency = <450000>;
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		eth0: ethernet@1a120000 {
+			compatible = "sensry,sy1xx-mac";
+			reg = <0x1a120000 0x1000>, <0x1a102a00 0x100>;
+			reg-names = "ctrl", "data";
+			status = "disabled";
+		};
 	};
 };
diff --git a/dts/riscv/sifive/riscv32-fe310.dtsi b/dts/riscv/sifive/riscv32-fe310.dtsi
index f2128e1d37b..9bcd00c9007 100644
--- a/dts/riscv/sifive/riscv32-fe310.dtsi
+++ b/dts/riscv/sifive/riscv32-fe310.dtsi
@@ -65,6 +65,12 @@
 			interrupts-extended = <&hlic 3 &hlic 7>;
 			reg = <0x2000000 0x10000>;
 		};
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&hlic 7>;
+			reg = <0x200bff8 0x8 0x2004000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
 		debug: debug-controller@0 {
 			compatible = "sifive,debug-013", "riscv,debug-013";
 			interrupts-extended = <&hlic 65535>;
diff --git a/dts/riscv/sifive/riscv64-fu540.dtsi b/dts/riscv/sifive/riscv64-fu540.dtsi
index 065870fac61..a730157bcec 100644
--- a/dts/riscv/sifive/riscv64-fu540.dtsi
+++ b/dts/riscv/sifive/riscv64-fu540.dtsi
@@ -182,6 +182,17 @@
 			reg = <0x2000000 0x10000>;
 		};
 
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&hlic0 7
+						&hlic1 7
+						&hlic2 7
+						&hlic3 7
+						&hlic4 7>;
+			reg = <0x200bff8 0x8 0x2004000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
+
 		l2lim: l2lim@8000000 {
 			compatible = "sifive,l2lim0";
 			reg = <0x8000000 0x2000000>;
diff --git a/dts/riscv/sifive/riscv64-fu740.dtsi b/dts/riscv/sifive/riscv64-fu740.dtsi
index 4b82d6338bc..db9a60e970a 100644
--- a/dts/riscv/sifive/riscv64-fu740.dtsi
+++ b/dts/riscv/sifive/riscv64-fu740.dtsi
@@ -137,13 +137,23 @@
 			reg = <0x0 0x2000000 0x0 0x10000>;
 		};
 
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&hlic0 7
+						&hlic1 7
+						&hlic2 7
+						&hlic3 7
+						&hlic4 7>;
+			reg = <0x0 0x200bff8 0x0 0x8 0x0 0x2004000 0x0 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
+
 		l2lim: l2lim@8000000 {
 			compatible = "sifive,l2lim0";
 			reg = <0x0 0x8000000 0x0 0x200000>;
 			reg-names = "mem";
 		};
 
-
 		plic: interrupt-controller@c000000 {
 			compatible = "sifive,plic-1.0.0";
 			#address-cells = <0>;
diff --git a/dts/riscv/starfive/jh7110-visionfive-v2.dtsi b/dts/riscv/starfive/jh7110-visionfive-v2.dtsi
index c3382bca86f..49c231f7887 100644
--- a/dts/riscv/starfive/jh7110-visionfive-v2.dtsi
+++ b/dts/riscv/starfive/jh7110-visionfive-v2.dtsi
@@ -145,8 +145,8 @@
 		compatible = "starfive,jh7110", "simple-bus";
 		ranges;
 
-		clint: timer@2000000 {
-			compatible = "starfive,jh7110-clint", "sifive,clint0";
+		clint: clint@2000000 {
+			compatible = "sifive,clint0";
 			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
 						&cpu1_intc 3 &cpu1_intc 7
 						&cpu2_intc 3 &cpu2_intc 7
@@ -155,6 +155,17 @@
 			reg = <0x0 0x2000000 0x0 0x10000>;
 		};
 
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&cpu0_intc 7
+						&cpu1_intc 7
+						&cpu2_intc 7
+						&cpu3_intc 7
+						&cpu4_intc 7>;
+			reg = <0x0 0x200bff8 0x0 0x8 0x0 0x2004000 0x0 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
+
 		ccache: cache-controller@2010000 {
 			cache-block-size = <64>;
 			cache-level = <2>;
diff --git a/dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi b/dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi
index c36ea625b02..fec2afc9f3f 100644
--- a/dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi
+++ b/dts/riscv/starfive/starfive_jh7100_beagle_v.dtsi
@@ -115,12 +115,19 @@
 		};
 
 		clint: clint@2000000 {
-			compatible = "starfive,jh7100-clint", "sifive,clint0";
+			compatible = "sifive,clint0";
 			interrupts-extended = <&cpu0intctrl 3 &cpu0intctrl 7
 					       &cpu1intctrl 3 &cpu1intctrl 7>;
 			reg = <0x0 0x2000000 0x0 0x10000>;
 		};
 
+		mtimer: timer@200bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&cpu0intctrl 7 &cpu1intctrl 7>;
+			reg = <0x0 0x200bff8 0x0 0x8 0x0 0x2004000 0x0 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
+
 		plic: plic@c000000 {
 			compatible = "sifive,plic-1.0.0";
 			#address-cells = <0>;
diff --git a/dts/riscv/telink/telink_b91.dtsi b/dts/riscv/telink/telink_b91.dtsi
index a75929f2814..e6f7079d45a 100644
--- a/dts/riscv/telink/telink_b91.dtsi
+++ b/dts/riscv/telink/telink_b91.dtsi
@@ -48,10 +48,10 @@
 		};
 
 		mtimer: timer@e6000000 {
-			compatible = "telink,machine-timer";
-			reg = <0xe6000000 0x10000>;
-			interrupts = <7 0>;
-			interrupt-parent = <&plic0>;
+			compatible = "riscv,machine-timer";
+			reg = <0xe6000000 0x8 0xe6000008 0x8>;
+			reg-names = "mtime", "mtimecmp";
+			interrupts-extended = <&plic0 7 0>;
 		};
 
 		flash_mspi: flash-controller@80140100 {
diff --git a/dts/riscv/wch/ch32v0/ch32v003.dtsi b/dts/riscv/wch/ch32v0/ch32v003.dtsi
new file mode 100644
index 00000000000..e2de8a5ad27
--- /dev/null
+++ b/dts/riscv/wch/ch32v0/ch32v003.dtsi
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2024 Michael Hope
+ * Copyright (c) 2024 Paul Wedeck <paulwedeck@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <freq.h>
+#include <mem.h>
+#include <wch/qingke-v2.dtsi>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/clock/ch32v00x-clocks.h>
+#include <zephyr/dt-bindings/dma/ch32v003-dma.h>
+
+/ {
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "wch,ch32v00x-hse-clock";
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "wch,ch32v00x-hsi-clock";
+			clock-frequency = <DT_FREQ_M(24)>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(128)>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "wch,ch32v00x-pll-clock";
+			status = "disabled";
+		};
+	};
+
+	soc {
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(2)>;
+		};
+
+		flash: flash-controller@40022000 {
+			compatible = "wch,ch32v00x-flash-controller";
+			reg = <0x40022000 0x400>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				reg = <0 DT_SIZE_K(16)>;
+			};
+		};
+
+		pwr: pwr@40007000 {
+			compatible = "wch,pwr";
+			reg = <0x40007000 0x10>;
+		};
+
+		pinctrl: pin-controller@40010000 {
+			compatible = "wch,afio";
+			reg = <0x40010000 0x10>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			status = "okay";
+
+			gpioa: gpio@40010800 {
+				compatible = "wch,gpio";
+				reg = <0x40010800 0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				gpio-reserved-ranges = <0 1>, <3 5>;
+				clocks = <&rcc CH32V00X_CLOCK_IOPA>;
+			};
+
+			gpioc: gpio@40011000 {
+				compatible = "wch,gpio";
+				reg = <0x40011000 0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				clocks = <&rcc CH32V00X_CLOCK_IOPC>;
+			};
+
+			gpiod: gpio@40011400 {
+				compatible = "wch,gpio";
+				reg = <0x40011400 0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				clocks = <&rcc CH32V00X_CLOCK_IOPD>;
+			};
+		};
+
+		i2c1: i2c@40005400 {
+			compatible = "wch,i2c";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x40005400 0x400>;
+			clocks = <&rcc CH32V00X_CLOCK_I2C1>;
+			interrupt-parent = <&pfic>;
+			interrupts = <30>, <31>;
+		};
+
+		usart1: uart@40013800 {
+			compatible = "wch,usart";
+			reg = <0x40013800 0x10>;
+			clocks = <&rcc CH32V00X_CLOCK_USART1>;
+			interrupt-parent = <&pfic>;
+			interrupts = <32>;
+		};
+
+		rcc: rcc@40021000 {
+			compatible = "wch,rcc";
+			reg = <0x40021000 0x10>;
+			#clock-cells = <1>;
+			status = "okay";
+		};
+
+		dma1: dma@40020000 {
+			compatible = "wch,wch-dma";
+			reg = <0x40020000 0x90>;
+			clocks = <&rcc CH32V00X_CLOCK_DMA1>;
+			#dma-cells = <1>;
+			interrupt-parent = <&pfic>;
+			interrupts = <22>, <23>, <24>, <25>, <26>, <27>, <28>;
+			dma-channels = <7>;
+		};
+	};
+};
+
+&cpu0 {
+	clock-frequency = <DT_FREQ_M(48)>;
+};
diff --git a/dts/riscv/wch/ch32v0/ch32v003a4m.dtsi b/dts/riscv/wch/ch32v0/ch32v003a4m.dtsi
new file mode 100644
index 00000000000..62e16a8f0ab
--- /dev/null
+++ b/dts/riscv/wch/ch32v0/ch32v003a4m.dtsi
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2024 Michael Hope
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <wch/ch32v0/ch32v003.dtsi>
+
+&gpioc {
+	gpio-reserved-ranges = <5 1>;
+};
+
+&gpiod {
+	gpio-reserved-ranges = <0 1>, <2 2>;
+};
diff --git a/dts/riscv/wch/ch32v0/ch32v003f4p.dtsi b/dts/riscv/wch/ch32v0/ch32v003f4p.dtsi
new file mode 100644
index 00000000000..005a5e9257d
--- /dev/null
+++ b/dts/riscv/wch/ch32v0/ch32v003f4p.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2024 Michael Hope
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <wch/ch32v0/ch32v003.dtsi>
diff --git a/dts/riscv/wch/ch32v0/ch32v003f4u.dtsi b/dts/riscv/wch/ch32v0/ch32v003f4u.dtsi
new file mode 100644
index 00000000000..005a5e9257d
--- /dev/null
+++ b/dts/riscv/wch/ch32v0/ch32v003f4u.dtsi
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2024 Michael Hope
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <wch/ch32v0/ch32v003.dtsi>
diff --git a/dts/riscv/wch/ch32v0/ch32v003j4m.dtsi b/dts/riscv/wch/ch32v0/ch32v003j4m.dtsi
new file mode 100644
index 00000000000..573a8632473
--- /dev/null
+++ b/dts/riscv/wch/ch32v0/ch32v003j4m.dtsi
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2024 Michael Hope
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <wch/ch32v0/ch32v003.dtsi>
+
+&gpioc {
+	gpio-reserved-ranges = <0 1>, <3 1>, <5 3>;
+};
+
+&gpiod {
+	gpio-reserved-ranges = <0 1>, <2 2>, <7 1>;
+};
diff --git a/dts/riscv/wch/ch32v00x.dtsi b/dts/riscv/wch/ch32v00x.dtsi
deleted file mode 100644
index 0066dc1992d..00000000000
--- a/dts/riscv/wch/ch32v00x.dtsi
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * Copyright (c) 2024 Michael Hope
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <freq.h>
-#include <mem.h>
-#include <zephyr/dt-bindings/gpio/gpio.h>
-#include <zephyr/dt-bindings/i2c/i2c.h>
-#include <zephyr/dt-bindings/clock/ch32v00x-clocks.h>
-
-/ {
-	#address-cells = <1>;
-	#size-cells = <1>;
-
-	cpus {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		cpu0: cpu@0 {
-			device_type = "cpu";
-			compatible = "wch,qingke-v2";
-			reg = <0>;
-			clock-frequency = <DT_FREQ_M(48)>;
-		};
-	};
-
-	clocks {
-		clk_hse: clk-hse {
-			#clock-cells = <0>;
-			compatible = "wch,ch32v00x-hse-clock";
-			status = "disabled";
-		};
-
-		clk_hsi: clk-hsi {
-			#clock-cells = <0>;
-			compatible = "wch,ch32v00x-hsi-clock";
-			clock-frequency = <DT_FREQ_M(24)>;
-			status = "disabled";
-		};
-
-		clk_lsi: clk-lsi {
-			#clock-cells = <0>;
-			compatible = "fixed-clock";
-			clock-frequency = <DT_FREQ_K(128)>;
-			status = "disabled";
-		};
-
-		pll: pll {
-			#clock-cells = <0>;
-			compatible = "wch,ch32v00x-pll-clock";
-			status = "disabled";
-		};
-	};
-
-	soc {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "simple-bus";
-		ranges;
-
-		sram0: memory@20000000 {
-			compatible = "mmio-sram";
-			reg = <0x20000000 0x800>;
-		};
-
-		flash: flash-controller@40022000 {
-			compatible = "wch,ch32v00x-flash-controller";
-			reg = <0x40022000 0x400>;
-
-			#address-cells = <1>;
-			#size-cells = <1>;
-
-			flash0: flash@0 {
-				compatible = "soc-nv-flash";
-				reg = <0 0x4000>;
-			};
-		};
-
-		pfic: interrupt-controller@e000e000 {
-			compatible = "wch,pfic";
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-			interrupt-controller;
-			reg = <0xe000e000 16>;
-			status = "okay";
-		};
-
-		systick: systimer@e000f000 {
-			compatible = "wch,systick";
-			reg = <0xe000f000 16>;
-			status = "okay";
-			interrupt-parent = <&pfic>;
-			interrupts = <12>;
-		};
-
-		pwr: pwr@40007000 {
-			compatible = "wch,pwr";
-			reg = <0x40007000 16>;
-		};
-
-		pinctrl: pin-controller@40010000 {
-			compatible = "wch,afio";
-			reg = <0x40010000 16>;
-			#address-cells = <1>;
-			#size-cells = <1>;
-			status = "okay";
-
-			gpioa: gpio@40010800 {
-				compatible = "wch,gpio";
-				reg = <0x40010800 32>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				ngpios = <8>;
-				clocks = <&rcc CH32V00X_CLOCK_IOPA>;
-			};
-
-			gpioc: gpio@40011000 {
-				compatible = "wch,gpio";
-				reg = <0x40011000 32>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				ngpios = <8>;
-				clocks = <&rcc CH32V00X_CLOCK_IOPC>;
-			};
-
-			gpiod: gpio@40011400 {
-				compatible = "wch,gpio";
-				reg = <0x40011400 32>;
-				gpio-controller;
-				#gpio-cells = <2>;
-				ngpios = <8>;
-				clocks = <&rcc CH32V00X_CLOCK_IOPD>;
-			};
-		};
-
-		usart1: uart@40013800 {
-			compatible = "wch,usart";
-			reg = <0x40013800 16>;
-			clocks = <&rcc CH32V00X_CLOCK_USART1>;
-			interrupt-parent = <&pfic>;
-			interrupts = <32>;
-		};
-
-		rcc: rcc@40021000 {
-			compatible = "wch,rcc";
-			reg = <0x40021000 16>;
-			#clock-cells = <1>;
-			status = "okay";
-		};
-	};
-};
diff --git a/dts/riscv/wch/ch32v208/ch32v208.dtsi b/dts/riscv/wch/ch32v208/ch32v208.dtsi
new file mode 100644
index 00000000000..c92324dad64
--- /dev/null
+++ b/dts/riscv/wch/ch32v208/ch32v208.dtsi
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <freq.h>
+#include <mem.h>
+#include <wch/qingke-v4c.dtsi>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/clock/ch32v20x_30x-clocks.h>
+
+/ {
+	clocks {
+		clk_hse: clk-hse {
+			#clock-cells = <0>;
+			compatible = "wch,ch32v00x-hse-clock";
+			clock-frequency = <DT_FREQ_M(32)>;
+			status = "disabled";
+		};
+
+		clk_hsi: clk-hsi {
+			#clock-cells = <0>;
+			compatible = "wch,ch32v00x-hsi-clock";
+			clock-frequency = <DT_FREQ_M(8)>;
+			status = "disabled";
+		};
+
+		clk_lsi: clk-lsi {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <DT_FREQ_K(32)>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			#clock-cells = <0>;
+			compatible = "wch,ch32v20x_30x-pll-clock";
+			mul = <18>;
+			status = "disabled";
+		};
+	};
+
+	soc {
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+			reg = <0x20000000 DT_SIZE_K(64)>;
+		};
+
+		flash: flash-controller@40022000 {
+			compatible = "wch,ch32v20x_30x-flash-controller";
+			reg = <0x40022000 0x400>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@0 {
+				compatible = "soc-nv-flash";
+				reg = <0 DT_SIZE_K(128)>;
+			};
+		};
+
+		pwr: pwr@40007000 {
+			compatible = "wch,pwr";
+			reg = <0x40007000 16>;
+		};
+
+		pinctrl: pin-controller@40010000 {
+			compatible = "wch,20x_30x-afio";
+			reg = <0x40010000 16>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			gpioa: gpio@40010800 {
+				compatible = "wch,gpio";
+				reg = <0x40010800 0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				clocks = <&rcc CH32V20X_V30X_CLOCK_IOPA>;
+			};
+
+			gpiob: gpio@40010C00 {
+				compatible = "wch,gpio";
+				reg = <0x40010C00 0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				clocks = <&rcc CH32V20X_V30X_CLOCK_IOPB>;
+			};
+
+			gpioc: gpio@40011000 {
+				compatible = "wch,gpio";
+				reg = <0x40011000 0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				clocks = <&rcc CH32V20X_V30X_CLOCK_IOPC>;
+			};
+
+			gpiod: gpio@40011400 {
+				compatible = "wch,gpio";
+				reg = <0x40011400 0x20>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				clocks = <&rcc CH32V20X_V30X_CLOCK_IOPD>;
+			};
+		};
+
+		usart1: uart@40013800 {
+			compatible = "wch,usart";
+			reg = <0x40013800 0x20>;
+			clocks = <&rcc CH32V20X_V30X_CLOCK_USART1>;
+			interrupt-parent = <&pfic>;
+			interrupts = <53>;
+			status = "disabled";
+		};
+
+		usart2: uart@40004400 {
+			compatible = "wch,usart";
+			reg = <0x40004400 0x20>;
+			clocks = <&rcc CH32V20X_V30X_CLOCK_USART2>;
+			interrupt-parent = <&pfic>;
+			interrupts = <54>;
+			status = "disabled";
+		};
+
+		usart3: uart@40004800 {
+			compatible = "wch,usart";
+			reg = <0x40004800 0x20>;
+			clocks = <&rcc CH32V20X_V30X_CLOCK_USART3>;
+			interrupt-parent = <&pfic>;
+			interrupts = <55>;
+			status = "disabled";
+		};
+
+		usart4: uart@40004c00 {
+			compatible = "wch,usart";
+			reg = <0x40004C00 0x20>;
+			clocks = <&rcc CH32V20X_V30X_CLOCK_USART4>;
+			interrupt-parent = <&pfic>;
+			interrupts = <68>;
+			status = "disabled";
+		};
+
+		rcc: rcc@40021000 {
+			compatible = "wch,rcc";
+			reg = <0x40021000 16>;
+			#clock-cells = <1>;
+		};
+	};
+};
+
+&cpu0 {
+	clock-frequency = <DT_FREQ_M(144)>;
+};
diff --git a/dts/riscv/wch/ch32v208/ch32v208cbu.dtsi b/dts/riscv/wch/ch32v208/ch32v208cbu.dtsi
new file mode 100644
index 00000000000..e4f958ca2c8
--- /dev/null
+++ b/dts/riscv/wch/ch32v208/ch32v208cbu.dtsi
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <wch/ch32v208/ch32v208.dtsi>
+
+&gpioc {
+	gpio-reserved-ranges = <0 13>;
+};
+
+&gpiod {
+	gpio-reserved-ranges = <0 16>;
+};
diff --git a/dts/riscv/wch/ch32v208/ch32v208gbu.dtsi b/dts/riscv/wch/ch32v208/ch32v208gbu.dtsi
new file mode 100644
index 00000000000..3241b148c93
--- /dev/null
+++ b/dts/riscv/wch/ch32v208/ch32v208gbu.dtsi
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <wch/ch32v208/ch32v208.dtsi>
+
+&gpioa {
+	gpio-reserved-ranges = <8 3>, <15 1>;
+};
+
+&gpiob {
+	gpio-reserved-ranges = <0 6>, <9 7>;
+};
+
+&gpioc {
+	gpio-reserved-ranges = <0 7>, <10 4>;
+};
+
+&gpiod {
+	gpio-reserved-ranges = <0 16>;
+};
diff --git a/dts/riscv/wch/ch32v208/ch32v208rbt.dtsi b/dts/riscv/wch/ch32v208/ch32v208rbt.dtsi
new file mode 100644
index 00000000000..7507be1f731
--- /dev/null
+++ b/dts/riscv/wch/ch32v208/ch32v208rbt.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <wch/ch32v208/ch32v208.dtsi>
+
+&gpiod {
+	gpio-reserved-ranges = <0 2>, <3 12>;
+};
diff --git a/dts/riscv/wch/ch32v208/ch32v208wbu.dtsi b/dts/riscv/wch/ch32v208/ch32v208wbu.dtsi
new file mode 100644
index 00000000000..d2e72c30a8f
--- /dev/null
+++ b/dts/riscv/wch/ch32v208/ch32v208wbu.dtsi
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <wch/ch32v208/ch32v208.dtsi>
+
+&gpiod {
+	gpio-reserved-ranges = <0 2>, <7 8>;
+};
diff --git a/dts/riscv/wch/qingke-v2.dtsi b/dts/riscv/wch/qingke-v2.dtsi
new file mode 100644
index 00000000000..a82ce935a53
--- /dev/null
+++ b/dts/riscv/wch/qingke-v2.dtsi
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2024 Michael Hope
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "wch,qingke-v2";
+			reg = <0>;
+			riscv,isa = "rv32ec_zicsr_zifencei";
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		pfic: interrupt-controller@e000e000 {
+			compatible = "wch,pfic";
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			reg = <0xe000e000 0x10>;
+			status = "okay";
+		};
+
+		systick: systimer@e000f000 {
+			compatible = "wch,systick";
+			reg = <0xe000f000 0x10>;
+			status = "okay";
+			interrupt-parent = <&pfic>;
+			interrupts = <12>;
+		};
+	};
+};
diff --git a/dts/riscv/wch/qingke-v4c.dtsi b/dts/riscv/wch/qingke-v4c.dtsi
new file mode 100644
index 00000000000..c4b00b5fdd7
--- /dev/null
+++ b/dts/riscv/wch/qingke-v4c.dtsi
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "wch,qingke-v4c";
+			reg = <0>;
+			riscv,isa = "rv32imac_zicsr_zifencei";
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		pfic: interrupt-controller@e000e000 {
+			compatible = "wch,pfic";
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+			interrupt-controller;
+			reg = <0xe000e000 0x10>;
+			status = "okay";
+		};
+
+		systick: systimer@e000f000 {
+			compatible = "wch,systick";
+			reg = <0xe000f000 0x10>;
+			status = "okay";
+			interrupt-parent = <&pfic>;
+			interrupts = <12>;
+		};
+	};
+};
diff --git a/dts/x86/intel/alder_lake.dtsi b/dts/x86/intel/alder_lake.dtsi
index 78df9c3cc52..110cc238729 100644
--- a/dts/x86/intel/alder_lake.dtsi
+++ b/dts/x86/intel/alder_lake.dtsi
@@ -25,7 +25,7 @@
 
 		cpu@1 {
 			device_type = "cpu";
-			compatible = "intel,alder-lake";
+			compatible = "intel,alder-lake", "intel,x86_64";
 			d-cache-line-size = <64>;
 			reg = <1>;
 		};
diff --git a/dts/x86/intel/bartlett_lake_s.dtsi b/dts/x86/intel/bartlett_lake_s.dtsi
new file mode 100644
index 00000000000..70f4df31e28
--- /dev/null
+++ b/dts/x86/intel/bartlett_lake_s.dtsi
@@ -0,0 +1,598 @@
+/*
+ * Copyright (c) 2025 Intel Corporation.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "skeleton.dtsi"
+#include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
+#include <zephyr/dt-bindings/i2c/i2c.h>
+#include <zephyr/dt-bindings/pcie/pcie.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "intel,bartlett-lake";
+			d-cache-line-size = <64>;
+			reg = <0>;
+		};
+	};
+
+	dram0: memory@0 {
+		device_type = "memory";
+		reg = <0x0 DT_DRAM_SIZE>;
+	};
+
+	intc: ioapic@fec00000  {
+		compatible = "intel,ioapic";
+		#address-cells = <1>;
+		#interrupt-cells = <3>;
+		reg = <0xfec00000 0x1000>;
+		interrupt-controller;
+	};
+
+	intc_loapic: loapic@fee00000  {
+		compatible = "intel,loapic";
+		reg = <0xfee00000 0x1000>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		#address-cells = <1>;
+	};
+
+	pcie0: pcie0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "pcie-controller";
+		acpi-hid = "PNP0A08";
+		ranges;
+
+		smbus0: smbus0 {
+			compatible = "intel,pch-smbus";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7aa3>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			status = "disabled";
+		};
+
+		i2c0_dma: i2c0_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		i2c0: i2c0 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7acc>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c0_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c1_dma: i2c1_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		i2c1: i2c1 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7acd>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c1_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c2_dma: i2c2_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		i2c2: i2c2 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7ace>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c2_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c3_dma: i2c3_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		i2c3: i2c3 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7acf>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c3_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c4_dma: i2c4_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		i2c4: i2c4 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7afc>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c4_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c5_dma: i2c5_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		i2c5: i2c5 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7afd>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c5_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c6_dma: i2c6_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		i2c6: i2c6 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7ada>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c6_dma 0>;
+
+			status = "disabled";
+		};
+
+		i2c7_dma: i2c7_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		i2c7: i2c7 {
+			compatible = "snps,designware-i2c";
+			clock-frequency = <I2C_BITRATE_STANDARD>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			vendor-id = <0x8086>;
+			device-id = <0x7adb>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			dmas = <&i2c7_dma 0>;
+
+			status = "disabled";
+		};
+
+		spi0: spi0 {
+			compatible = "intel,penwell-spi";
+			vendor-id = <0x8086>;
+			device-id = <0x7aaa>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pw,cs-mode = <0>;
+			pw,cs-output = <0>;
+			pw,fifo-depth = <64>;
+			cs-gpios = <&gpio_0_i 15 GPIO_ACTIVE_LOW>;
+			clock-frequency = <100000000>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			status = "disabled";
+		};
+
+		spi1: spi1 {
+			compatible = "intel,penwell-spi";
+			vendor-id = <0x8086>;
+			device-id = <0x7aab>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pw,cs-mode = <0>;
+			pw,cs-output = <0>;
+			pw,fifo-depth = <64>;
+			cs-gpios = <&gpio_0_i 19 GPIO_ACTIVE_LOW>;
+			clock-frequency = <100000000>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			status = "disabled";
+		};
+
+		spi2: spi2 {
+			compatible = "intel,penwell-spi";
+			vendor-id = <0x8086>;
+			device-id = <0x7afb>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			pw,cs-mode = <0>;
+			pw,cs-output = <0>;
+			pw,fifo-depth = <64>;
+			cs-gpios = <&gpio_0_r 12 GPIO_ACTIVE_LOW>;
+			clock-frequency = <100000000>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+
+			status = "disabled";
+		};
+
+		uart0_dma: uart0_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		uart0: uart0 {
+			compatible = "ns16550";
+			vendor-id = <0x8086>;
+			device-id = <0x7aa8>;
+			reg-shift = <2>;
+			clock-frequency = <1843200>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			current-speed = <115200>;
+			dmas = <&uart0_dma 0>, <&uart0_dma 1>;
+			dma-names = "tx", "rx";
+
+			status = "disabled";
+		};
+
+		uart1_dma: uart1_dma {
+			compatible = "intel,lpss";
+			#dma-cells = <1>;
+
+			status = "disabled";
+		};
+
+		uart1: uart1 {
+			compatible = "ns16550";
+			vendor-id = <0x8086>;
+			device-id = <0x7aa9>;
+			reg-shift = <2>;
+			clock-frequency = <1843200>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			current-speed = <115200>;
+			dmas = <&uart1_dma 0>, <&uart1_dma 1>;
+			dma-names = "tx", "rx";
+
+			status = "disabled";
+		};
+
+		uart2: uart2 {
+			compatible = "ns16550";
+			vendor-id = <0x8086>;
+			device-id = <0x7afe>;
+			reg-shift = <2>;
+			clock-frequency = <1843200>;
+			interrupts = <PCIE_IRQ_DETECT IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			current-speed = <115200>;
+
+			status = "disabled";
+		};
+	};
+
+	soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "simple-bus";
+		ranges;
+
+		vtd: vtd@fed91000 {
+			compatible = "intel,vt-d";
+			reg = <0xfed91000 0x1000>;
+
+			status = "okay";
+		};
+
+		uart_ec_0: uart@3f8 {
+			compatible = "ns16550";
+			reg = <0x000003f8 0x100>;
+			io-mapped;
+			clock-frequency = <1843200>;
+			interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
+			interrupt-parent = <&intc>;
+			reg-shift = <0>;
+			io-mapped;
+
+			status = "disabled";
+		};
+
+		gpio_0_i: gpio@e06e0700 {
+			compatible = "intel,gpio";
+			reg = <0xe06e0700 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <23>;
+			pin-offset = <0>;
+
+			status = "disabled";
+		};
+
+		gpio_0_r: gpio@e06e0890 {
+			compatible = "intel,gpio";
+			reg = <0xe06e0890 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <22>;
+			pin-offset = <26>;
+
+			status = "disabled";
+		};
+
+		gpio_0_j: gpio@e06e0a00 {
+			compatible = "intel,gpio";
+			reg = <0xe06e0a00 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <12>;
+			pin-offset = <49>;
+
+			status = "disabled";
+		};
+
+		gpio_1_b: gpio@e06d0700 {
+			compatible = "intel,gpio";
+			reg = <0xe06d0700 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <24>;
+			pin-offset = <0>;
+
+			status = "disabled";
+		};
+
+		gpio_1_g: gpio@e06d0880 {
+			compatible = "intel,gpio";
+			reg = <0xe06d0880 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin-offset = <24>;
+
+			status = "disabled";
+		};
+
+		gpio_1_h: gpio@e06d0900 {
+			compatible = "intel,gpio";
+			reg = <0xe06d0900 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <24>;
+			pin-offset = <32>;
+
+			status = "disabled";
+		};
+
+		gpio_3_a: gpio@e06b0790 {
+			compatible = "intel,gpio";
+			reg = <0xe06b0790 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <15>;
+			pin-offset = <9>;
+
+			status = "disabled";
+		};
+
+		gpio_3_c: gpio@e06b0890 {
+			compatible = "intel,gpio";
+			reg = <0xe06b0890 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <24>;
+			pin-offset = <25>;
+
+			status = "disabled";
+		};
+
+		gpio_4_s: gpio@e06a0700 {
+			compatible = "intel,gpio";
+			reg = <0xe06a0700 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <8>;
+			pin-offset = <0>;
+
+			status = "disabled";
+		};
+
+		gpio_4_e: gpio@e06a0780 {
+			compatible = "intel,gpio";
+			reg = <0xe06a0780 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <22>;
+			pin-offset = <8>;
+
+			status = "disabled";
+		};
+
+		gpio_4_k: gpio@e06a08f0 {
+			compatible = "intel,gpio";
+			reg = <0xe06a08f0 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x2>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <12>;
+			pin-offset = <25>;
+
+			status = "disabled";
+		};
+
+		gpio_4_f: gpio@e06a09e0 {
+			compatible = "intel,gpio";
+			reg = <0xe06a09e0 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x3>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <24>;
+			pin-offset = <41>;
+
+			status = "disabled";
+		};
+
+		gpio_5_d: gpio@e0690700 {
+			compatible = "intel,gpio";
+			reg = <0xe0690700 0x1000>;
+			interrupts = <14 IRQ_TYPE_LOWEST_LEVEL_LOW 3>;
+			interrupt-parent = <&intc>;
+			group-index = <0x0>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <24>;
+			pin-offset = <0>;
+
+			status = "disabled";
+		};
+
+		pwm0: pwm@e06a0000 {
+			compatible = "intel,blinky-pwm";
+			reg = <0xe06a0000 0x400>;
+			reg-offset = <0x304>;
+			clock-frequency = <32768>;
+			max-pins = <1>;
+			#pwm-cells = <2>;
+
+			status = "disabled";
+		};
+
+		rtc: counter: rtc@70 {
+			compatible = "motorola,mc146818";
+			reg = <0x70 0x0D 0x71 0x0D>;
+			interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>;
+			interrupt-parent = <&intc>;
+			alarms-count = <1>;
+
+			status = "disabled";
+		};
+
+		tgpio: tgpio@fe001200 {
+			compatible = "intel,timeaware-gpio";
+			reg = <0xfe001200 0x100>;
+			timer-clock = <19200000>;
+			max-pins = <2>;
+
+			status = "disabled";
+		};
+
+		hpet: hpet@fed00000 {
+			compatible = "intel,hpet";
+			reg = <0xfed00000 0x400>;
+			interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>;
+			interrupt-parent = <&intc>;
+
+			status = "disabled";
+		};
+
+		tco_wdt: tco_wdt@400 {
+			compatible = "intel,tco-wdt";
+			reg = <0x0400 0x20>;
+
+			status = "disabled";
+		};
+	};
+};
diff --git a/dts/xtensa/espressif/esp32/esp32_common.dtsi b/dts/xtensa/espressif/esp32/esp32_common.dtsi
index 403a4b97fd8..0842e7e1170 100644
--- a/dts/xtensa/espressif/esp32/esp32_common.dtsi
+++ b/dts/xtensa/espressif/esp32/esp32_common.dtsi
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2019 Intel Corporation.
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -112,6 +113,29 @@
 			zephyr,memory-region = "SRAM2";
 		};
 
+		dcache0: dcache0@3f400000 {
+			compatible = "zephyr,memory-region", "mmio-sram";
+			reg = <0x3f400000 DT_SIZE_M(4)>;
+			zephyr,memory-region = "DCACHE0";
+		};
+
+		dcache1: dcache1@3f800000 {
+			compatible = "zephyr,memory-region", "mmio-sram";
+			reg = <0x3f800000 DT_SIZE_M(4)>;
+			zephyr,memory-region = "DCACHE1";
+
+			psram0: psram0 {
+				compatible = "espressif,esp32-psram";
+				size = <0x0>;
+			};
+		};
+
+		icache0: icache0@400d0000 {
+			compatible = "zephyr,memory-region", "mmio-sram";
+			reg = <0x400d0000 DT_SIZE_K(11456)>;
+			zephyr,memory-region = "ICACHE0";
+		};
+
 		ipmmem0: memory@3ffe5230 {
 			compatible = "mmio-sram";
 			reg = <0x3ffe5230 0x400>;
@@ -189,14 +213,6 @@
 			};
 		};
 
-		psram0: psram@3f800000 {
-			device_type = "memory";
-			compatible = "mmio-sram";
-			/* PSRAM size is specified in SOC/SIP dtsi */
-			reg = <0x3f800000 DT_SIZE_M(2)>;
-			status = "disabled";
-		};
-
 		ipi0: ipi@3f4c0058 {
 			compatible = "espressif,crosscore-interrupt";
 			reg = <0x3f4c0058 0x4>;
@@ -344,6 +360,34 @@
 			status = "disabled";
 		};
 
+		i2s0: i2s@3ff4f000 {
+			compatible = "espressif,esp32-i2s";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3ff4f000 0x1000>;
+			interrupts = <I2S0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>,
+				     <I2S0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
+			interrupt-names = "rx", "tx";
+			interrupt-parent = <&intc>;
+			clocks = <&rtc ESP32_I2S0_MODULE>;
+			unit = <0>;
+			status = "disabled";
+		};
+
+		i2s1: i2s@3ff6d000 {
+			compatible = "espressif,esp32-i2s";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3ff6d000 0x1000>;
+			interrupts = <I2S1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>,
+				     <I2S1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
+			interrupt-names = "rx", "tx";
+			interrupt-parent = <&intc>;
+			clocks = <&rtc ESP32_I2S1_MODULE>;
+			unit = <1>;
+			status = "disabled";
+		};
+
 		trng0: trng@3ff75144 {
 			compatible = "espressif,esp32-trng";
 			reg = <0x3FF75144 0x4>;
@@ -456,6 +500,7 @@
 		adc0: adc@3ff48800 {
 			compatible = "espressif,esp32-adc";
 			reg = <0x3ff48800 10>;
+			clocks = <&rtc ESP32_SARADC_MODULE>;
 			unit = <1>;
 			channel-count = <8>;
 			#io-channel-cells = <1>;
@@ -465,6 +510,7 @@
 		adc1: adc@3ff48890 {
 			compatible = "espressif,esp32-adc";
 			reg = <0x3ff48890 10>;
+			clocks = <&rtc ESP32_SARADC_MODULE>;
 			unit = <2>;
 			channel-count = <10>;
 			#io-channel-cells = <1>;
diff --git a/dts/xtensa/espressif/esp32/esp32_d0wdr2_v3.dtsi b/dts/xtensa/espressif/esp32/esp32_d0wdr2_v3.dtsi
index 2703231b821..c7180dd467d 100644
--- a/dts/xtensa/espressif/esp32/esp32_d0wdr2_v3.dtsi
+++ b/dts/xtensa/espressif/esp32/esp32_d0wdr2_v3.dtsi
@@ -15,6 +15,5 @@
 
 /* 2MB psram */
 &psram0 {
-	reg = <0x3f800000 DT_SIZE_M(2)>;
-	status = "okay";
+	size = <DT_SIZE_M(2)>;
 };
diff --git a/dts/xtensa/espressif/esp32/esp32_pico_v3_02.dtsi b/dts/xtensa/espressif/esp32/esp32_pico_v3_02.dtsi
index 9d108bd4e57..03acd73f59e 100644
--- a/dts/xtensa/espressif/esp32/esp32_pico_v3_02.dtsi
+++ b/dts/xtensa/espressif/esp32/esp32_pico_v3_02.dtsi
@@ -19,6 +19,5 @@
 
 /* 2MB psram */
 &psram0 {
-	reg = <0x3f800000 DT_SIZE_M(2)>;
-	status = "okay";
+	size = <DT_SIZE_M(2)>;
 };
diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r2.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r2.dtsi
index 4aa681336ac..2476afcacbd 100644
--- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r2.dtsi
+++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r2.dtsi
@@ -23,6 +23,5 @@
 
 /* 2MB psram */
 &psram0 {
-	reg = <0x3f800000 DT_SIZE_M(2)>;
-	status = "okay";
+	size = <DT_SIZE_M(2)>;
 };
diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r4.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r4.dtsi
index 37e2b62a004..1018cb453b0 100644
--- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r4.dtsi
+++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r4.dtsi
@@ -23,6 +23,5 @@
 
 /* 4MB psram */
 &psram0 {
-	reg = <0x3f800000 DT_SIZE_M(4)>;
-	status = "okay";
+	size = <DT_SIZE_M(4)>;
 };
diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r8.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r8.dtsi
index 73ec91dca44..d6484cadb50 100644
--- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r8.dtsi
+++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n16r8.dtsi
@@ -23,6 +23,5 @@
 
 /* 8MB psram */
 &psram0 {
-	reg = <0x3f800000 DT_SIZE_M(8)>;
-	status = "okay";
+	size = <DT_SIZE_M(8)>;
 };
diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r2.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r2.dtsi
index b0ab013feb3..9057bae18d3 100644
--- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r2.dtsi
+++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r2.dtsi
@@ -23,6 +23,5 @@
 
 /* 2MB psram */
 &psram0 {
-	reg = <0x3f800000 DT_SIZE_M(2)>;
-	status = "okay";
+	size = <DT_SIZE_M(2)>;
 };
diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r8.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r8.dtsi
index 87a2f8930ec..1171dc69882 100644
--- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r8.dtsi
+++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n4r8.dtsi
@@ -23,6 +23,5 @@
 
 /* 8MB psram */
 &psram0 {
-	reg = <0x3f800000 DT_SIZE_M(8)>;
-	status = "okay";
+	size = <DT_SIZE_M(8)>;
 };
diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r2.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r2.dtsi
index 6b74a725ed4..281ebd835a5 100644
--- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r2.dtsi
+++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r2.dtsi
@@ -23,6 +23,5 @@
 
 /* 2MB psram */
 &psram0 {
-	reg = <0x3f800000 DT_SIZE_M(2)>;
-	status = "okay";
+	size = <DT_SIZE_M(2)>;
 };
diff --git a/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r8.dtsi b/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r8.dtsi
index e5a12caae0c..19cf746989f 100644
--- a/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r8.dtsi
+++ b/dts/xtensa/espressif/esp32/esp32_wrover_e_n8r8.dtsi
@@ -24,6 +24,5 @@
 
 /* 8MB flash */
 &psram0 {
-	reg = <0x3f800000 DT_SIZE_M(8)>;
-	status = "okay";
+	size = <DT_SIZE_M(8)>;
 };
diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi
index dac9ce903ea..4c3fcbc3c38 100644
--- a/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi
+++ b/dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi
@@ -91,6 +91,29 @@
 			zephyr,memory-region = "SRAM1";
 		};
 
+		dcache0: dcache0@3f000000 {
+			compatible = "zephyr,memory-region";
+			reg = <0x3f000000 DT_SIZE_M(4)>;
+			zephyr,memory-region = "DCACHE0";
+		};
+
+		dcache1: dcache1@3f500000 {
+			compatible = "zephyr,memory-region";
+			reg = <0x3f500000 DT_SIZE_K(10752)>;
+			zephyr,memory-region = "DCACHE1";
+
+			psram0: psram0 {
+				compatible = "espressif,esp32-psram";
+				size = <0x0>;
+			};
+		};
+
+		icache0: icache0@40080000 {
+			compatible = "zephyr,memory-region";
+			reg = <0x40080000 DT_SIZE_K(7680)>;
+			zephyr,memory-region = "ICACHE0";
+		};
+
 		intc: interrupt-controller@3f4c2000 {
 			#interrupt-cells = <3>;
 			#address-cells = <0>;
@@ -142,14 +165,6 @@
 			};
 		};
 
-		psram0: psram@3f500000 {
-			device_type = "memory";
-			compatible = "mmio-sram";
-			/* PSRAM size is specified in SOC/SIP dtsi */
-			reg = <0x3f500000 DT_SIZE_M(2)>;
-			status = "disabled";
-		};
-
 		uart0: uart@3f400000 {
 			compatible = "espressif,esp32-uart";
 			reg = <0x3f400000 0x400>;
@@ -242,6 +257,20 @@
 			status = "disabled";
 		};
 
+		i2s0: i2s@3f40f000 {
+			compatible = "espressif,esp32-i2s";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x3f40f000 0x1000>;
+			interrupts = <I2S0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>,
+				     <I2S0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
+			interrupt-names = "rx", "tx";
+			interrupt-parent = <&intc>;
+			clocks = <&rtc ESP32_I2S0_MODULE>;
+			unit = <0>;
+			status = "disabled";
+		};
+
 		timer0: counter@3f41f000 {
 			compatible = "espressif,esp32-timer";
 			reg = <0x3f41f000 DT_SIZE_K(4)>;
@@ -350,6 +379,7 @@
 		adc0: adc@3f440018 {
 			compatible = "espressif,esp32-adc";
 			reg = <0x3f440018 100>;
+			clocks = <&rtc ESP32_PERIPH_SARADC_MODULE>;
 			unit = <1>;
 			channel-count = <10>;
 			#io-channel-cells = <1>;
@@ -359,6 +389,7 @@
 		adc1: adc@3f440028 {
 			compatible = "espressif,esp32-adc";
 			reg = <0x3f440028 100>;
+			clocks = <&rtc ESP32_PERIPH_SARADC_MODULE>;
 			unit = <2>;
 			channel-count = <10>;
 			#io-channel-cells = <1>;
diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_fn4r2.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_fn4r2.dtsi
index f3175a99233..fd8686b2334 100644
--- a/dts/xtensa/espressif/esp32s2/esp32s2_fn4r2.dtsi
+++ b/dts/xtensa/espressif/esp32s2/esp32s2_fn4r2.dtsi
@@ -13,6 +13,5 @@
 
 /* 2MB psram */
 &psram0 {
-	reg = <0x3f500000 DT_SIZE_M(2)>;
-	status = "okay";
+	size = <DT_SIZE_M(2)>;
 };
diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_mini_n4r2.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_mini_n4r2.dtsi
index 84e3b16cc39..fd8686b2334 100644
--- a/dts/xtensa/espressif/esp32s2/esp32s2_mini_n4r2.dtsi
+++ b/dts/xtensa/espressif/esp32s2/esp32s2_mini_n4r2.dtsi
@@ -13,6 +13,5 @@
 
 /* 2MB psram */
 &psram0 {
-	status = "okay";
-	reg = <0x3f500000 DT_SIZE_M(2)>;
+	size = <DT_SIZE_M(2)>;
 };
diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_r2.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_r2.dtsi
index db004992e70..66d624e4e5c 100644
--- a/dts/xtensa/espressif/esp32s2/esp32s2_r2.dtsi
+++ b/dts/xtensa/espressif/esp32s2/esp32s2_r2.dtsi
@@ -8,6 +8,5 @@
 
 /* 2MB psram */
 &psram0 {
-	status = "okay";
-	reg = <0x3f500000 DT_SIZE_M(2)>;
+	size = <DT_SIZE_M(2)>;
 };
diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_solo_n4r2.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_solo_n4r2.dtsi
index 84e3b16cc39..fd8686b2334 100644
--- a/dts/xtensa/espressif/esp32s2/esp32s2_solo_n4r2.dtsi
+++ b/dts/xtensa/espressif/esp32s2/esp32s2_solo_n4r2.dtsi
@@ -13,6 +13,5 @@
 
 /* 2MB psram */
 &psram0 {
-	status = "okay";
-	reg = <0x3f500000 DT_SIZE_M(2)>;
+	size = <DT_SIZE_M(2)>;
 };
diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n16r2.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n16r2.dtsi
index 77645a3c2e0..053b0d6ee4a 100644
--- a/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n16r2.dtsi
+++ b/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n16r2.dtsi
@@ -13,6 +13,5 @@
 
 /* 2MB psram */
 &psram0 {
-	status = "okay";
-	reg = <0x3f500000 DT_SIZE_M(2)>;
+	size = <DT_SIZE_M(2)>;
 };
diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n4r2.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n4r2.dtsi
index 84e3b16cc39..fd8686b2334 100644
--- a/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n4r2.dtsi
+++ b/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n4r2.dtsi
@@ -13,6 +13,5 @@
 
 /* 2MB psram */
 &psram0 {
-	status = "okay";
-	reg = <0x3f500000 DT_SIZE_M(2)>;
+	size = <DT_SIZE_M(2)>;
 };
diff --git a/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n8r2.dtsi b/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n8r2.dtsi
index 92d8775368e..5f3e9ecd713 100644
--- a/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n8r2.dtsi
+++ b/dts/xtensa/espressif/esp32s2/esp32s2_wrover_n8r2.dtsi
@@ -13,6 +13,5 @@
 
 /* 2MB psram */
 &psram0 {
-	status = "okay";
-	reg = <0x3f500000 DT_SIZE_M(2)>;
+	size = <DT_SIZE_M(2)>;
 };
diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi
index 46d74df4e3a..1f4f046df4d 100644
--- a/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi
+++ b/dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi
@@ -86,6 +86,23 @@
 		compatible = "simple-bus";
 		ranges;
 
+		icache0: memory@42000000 {
+			compatible = "zephyr,memory-region";
+			reg = <0x42000000 DT_SIZE_M(32)>;
+			zephyr,memory-region = "ICACHE0";
+		};
+
+		dcache0: memory@3c000000 {
+			compatible = "zephyr,memory-region";
+			reg = <0x3c000000 DT_SIZE_M(32)>;
+			zephyr,memory-region = "DCACHE0";
+
+			psram0: psram0 {
+				compatible = "espressif,esp32-psram";
+				size = <0x0>;
+			};
+		};
+
 		sram0: memory@40370000 {
 			compatible = "zephyr,memory-region", "mmio-sram";
 			reg = <0x40370000 DT_SIZE_K(32)>;
@@ -189,14 +206,6 @@
 			};
 		};
 
-		psram0: psram@3c000000 {
-			device_type = "memory";
-			compatible = "mmio-sram";
-			/* PSRAM size is specified in SOC/SIP dtsi */
-			reg = <0x3c000000 DT_SIZE_M(2)>;
-			status = "disabled";
-		};
-
 		uart0: uart@60000000 {
 			compatible = "espressif,esp32-uart";
 			reg = <0x60000000 0x1000>;
@@ -353,6 +362,7 @@
 		adc0: adc@60040000 {
 			compatible = "espressif,esp32-adc";
 			reg = <0x60040000 4>;
+			clocks = <&rtc ESP32_SARADC_MODULE>;
 			unit = <1>;
 			channel-count = <10>;
 			#io-channel-cells = <1>;
@@ -362,6 +372,7 @@
 		adc1: adc@60040004 {
 			compatible = "espressif,esp32-adc";
 			reg = <0x60040004 4>;
+			clocks = <&rtc ESP32_SARADC_MODULE>;
 			unit = <2>;
 			channel-count = <10>;
 			#io-channel-cells = <1>;
diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_mini_n4r2.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_mini_n4r2.dtsi
index b8f733a3c54..843c999f525 100644
--- a/dts/xtensa/espressif/esp32s3/esp32s3_mini_n4r2.dtsi
+++ b/dts/xtensa/espressif/esp32s3/esp32s3_mini_n4r2.dtsi
@@ -13,6 +13,5 @@
 
 /* 2MB psram */
 &psram0 {
-	reg = <0x3c000000 DT_SIZE_M(2)>;
-	status = "okay";
+	size = <DT_SIZE_M(2)>;
 };
diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_mini_n8.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_mini_n8.dtsi
index 4b2e7404282..5639f2bd921 100644
--- a/dts/xtensa/espressif/esp32s3/esp32s3_mini_n8.dtsi
+++ b/dts/xtensa/espressif/esp32s3/esp32s3_mini_n8.dtsi
@@ -10,3 +10,7 @@
 &flash0 {
 	reg = <0x0 DT_SIZE_M(8)>;
 };
+
+&psram0 {
+	size = <DT_SIZE_M(8)>;
+};
diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_pico_n8r2.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_pico_n8r2.dtsi
index b77169f172b..31c631bbde0 100644
--- a/dts/xtensa/espressif/esp32s3/esp32s3_pico_n8r2.dtsi
+++ b/dts/xtensa/espressif/esp32s3/esp32s3_pico_n8r2.dtsi
@@ -13,6 +13,5 @@
 
 /* 2MB psram */
 &psram0 {
-	reg = <0x3c000000 DT_SIZE_M(2)>;
-	status = "okay";
+	size = <DT_SIZE_M(2)>;
 };
diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_pico_n8r8.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_pico_n8r8.dtsi
index 34ec0ec5ac1..a3de8d6faa6 100644
--- a/dts/xtensa/espressif/esp32s3/esp32s3_pico_n8r8.dtsi
+++ b/dts/xtensa/espressif/esp32s3/esp32s3_pico_n8r8.dtsi
@@ -13,6 +13,5 @@
 
 /* 8MB psram */
 &psram0 {
-	reg = <0x3c000000 DT_SIZE_M(8)>;
-	status = "okay";
+	size = <DT_SIZE_M(8)>;
 };
diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_r2.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_r2.dtsi
index 187a214078f..df68b4852cb 100644
--- a/dts/xtensa/espressif/esp32s3/esp32s3_r2.dtsi
+++ b/dts/xtensa/espressif/esp32s3/esp32s3_r2.dtsi
@@ -8,6 +8,5 @@
 
 /* 2MB psram */
 &psram0 {
-	reg = <0x3c000000 DT_SIZE_M(2)>;
-	status = "okay";
+	size = <DT_SIZE_M(2)>;
 };
diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_r8.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_r8.dtsi
index 29a21140630..3b192040f04 100644
--- a/dts/xtensa/espressif/esp32s3/esp32s3_r8.dtsi
+++ b/dts/xtensa/espressif/esp32s3/esp32s3_r8.dtsi
@@ -8,6 +8,5 @@
 
 /* 8MB psram */
 &psram0 {
-	reg = <0x3c000000 DT_SIZE_M(8)>;
-	status = "okay";
+	size = <DT_SIZE_M(8)>;
 };
diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_r8v.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_r8v.dtsi
index 29a21140630..3b192040f04 100644
--- a/dts/xtensa/espressif/esp32s3/esp32s3_r8v.dtsi
+++ b/dts/xtensa/espressif/esp32s3/esp32s3_r8v.dtsi
@@ -8,6 +8,5 @@
 
 /* 8MB psram */
 &psram0 {
-	reg = <0x3c000000 DT_SIZE_M(8)>;
-	status = "okay";
+	size = <DT_SIZE_M(8)>;
 };
diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n16r2.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n16r2.dtsi
index c4c0929063d..e3a4bf89b90 100644
--- a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n16r2.dtsi
+++ b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n16r2.dtsi
@@ -13,6 +13,5 @@
 
 /* 2MB psram */
 &psram0 {
-	reg = <0x3c000000 DT_SIZE_M(2)>;
-	status = "okay";
+	size = <DT_SIZE_M(2)>;
 };
diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n16r8.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n16r8.dtsi
index 102fd94ec12..45cbd4cf0b1 100644
--- a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n16r8.dtsi
+++ b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n16r8.dtsi
@@ -13,6 +13,5 @@
 
 /* 8MB psram */
 &psram0 {
-	reg = <0x3c000000 DT_SIZE_M(8)>;
-	status = "okay";
+	size = <DT_SIZE_M(8)>;
 };
diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n4r2.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n4r2.dtsi
index b8f733a3c54..843c999f525 100644
--- a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n4r2.dtsi
+++ b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n4r2.dtsi
@@ -13,6 +13,5 @@
 
 /* 2MB psram */
 &psram0 {
-	reg = <0x3c000000 DT_SIZE_M(2)>;
-	status = "okay";
+	size = <DT_SIZE_M(2)>;
 };
diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n4r8.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n4r8.dtsi
index b17d9f9223b..429044da2b1 100644
--- a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n4r8.dtsi
+++ b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n4r8.dtsi
@@ -13,6 +13,5 @@
 
 /* 8MB psram */
 &psram0 {
-	reg = <0x3c000000 DT_SIZE_M(8)>;
-	status = "okay";
+	size = <DT_SIZE_M(8)>;
 };
diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n8r2.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n8r2.dtsi
index b77169f172b..31c631bbde0 100644
--- a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n8r2.dtsi
+++ b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n8r2.dtsi
@@ -13,6 +13,5 @@
 
 /* 2MB psram */
 &psram0 {
-	reg = <0x3c000000 DT_SIZE_M(2)>;
-	status = "okay";
+	size = <DT_SIZE_M(2)>;
 };
diff --git a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n8r8.dtsi b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n8r8.dtsi
index 34ec0ec5ac1..a3de8d6faa6 100644
--- a/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n8r8.dtsi
+++ b/dts/xtensa/espressif/esp32s3/esp32s3_wroom_n8r8.dtsi
@@ -13,6 +13,5 @@
 
 /* 8MB psram */
 &psram0 {
-	reg = <0x3c000000 DT_SIZE_M(8)>;
-	status = "okay";
+	size = <DT_SIZE_M(8)>;
 };
diff --git a/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi b/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi
index 47e5895b1f1..d28ef58ec4d 100644
--- a/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi
+++ b/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi
@@ -446,6 +446,14 @@
 			};
 		};
 
+		mic_privacy: mic-prv@71a40  {
+			compatible = "intel,adsp-mic-privacy";
+			reg = <0x71a40  0x8000>;
+			interrupts = <29 0 0>;
+			interrupt-parent = <&ace_intc>;
+			status = "okay";
+		};
+
 		mem_window0: mem_window@70200 {
 			compatible = "intel,adsp-mem-window";
 			reg = <0x70200 0x8>;
@@ -623,7 +631,7 @@
 			interrupt-controller;
 			#interrupt-cells = <3>;
 			interrupts = <4 0 0>;
-			num-irqs = <28>;
+			num-irqs = <30>;
 			interrupt-parent = <&core_intc>;
 		};
 
diff --git a/dts/xtensa/nxp/nxp_imx8m.dtsi b/dts/xtensa/nxp/nxp_imx8m.dtsi
index a18b63bf49e..036d1ef07e3 100644
--- a/dts/xtensa/nxp/nxp_imx8m.dtsi
+++ b/dts/xtensa/nxp/nxp_imx8m.dtsi
@@ -113,6 +113,15 @@
 			status = "disabled";
 		};
 
+		micfil: micfil@30ca0000 {
+			compatible = "nxp,dai-micfil";
+			reg = <0x30ca0000 DT_SIZE_K(64)>;
+			dai-index = <2>;
+			dmas = <&sdma3 24 6>;
+			fifo-depth = <32>;
+			status = "disabled";
+		};
+
 		iomuxc: iomuxc@30330000 {
 			compatible = "nxp,imx-iomuxc";
 			reg = <0x30330000 DT_SIZE_K(64)>;
diff --git a/dts/xtensa/nxp/nxp_imx8ulp.dtsi b/dts/xtensa/nxp/nxp_imx8ulp.dtsi
index 816a72f9cc1..f10d6a87c58 100644
--- a/dts/xtensa/nxp/nxp_imx8ulp.dtsi
+++ b/dts/xtensa/nxp/nxp_imx8ulp.dtsi
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023 NXP
+ * Copyright 2023-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -17,16 +17,16 @@
 			device_type = "cpu";
 			compatible = "cdns,tensilica-xtensa-lx7";
 			reg = <0>;
-		};
 
-		#address-cells = <1>;
-		#size-cells = <0>;
+			#address-cells = <1>;
+			#size-cells = <0>;
 
-		clic: interrupt-controller@0 {
-			compatible = "cdns,xtensa-core-intc";
-			reg = <0>;
-			interrupt-controller;
-			#interrupt-cells = <3>;
+			clic: interrupt-controller@0 {
+				compatible = "cdns,xtensa-core-intc";
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <3>;
+			};
 		};
 	};
 
@@ -98,4 +98,14 @@
 		dai-index = <6>;
 		status = "disabled";
 	};
+
+	mu3: mbox@2da20000 {
+		compatible = "nxp,mbox-imx-mu";
+		reg = <0x2da20000 DT_SIZE_K(64)>;
+		interrupt-parent = <&clic>;
+		interrupts = <15 0 0>;
+		rx-channels = <4>;
+		#mbox-cells = <1>;
+		status = "disabled";
+	};
 };
diff --git a/dts/xtensa/nxp/nxp_imxrt700_hifi1.dtsi b/dts/xtensa/nxp/nxp_imxrt700_hifi1.dtsi
new file mode 100644
index 00000000000..808857164c3
--- /dev/null
+++ b/dts/xtensa/nxp/nxp_imxrt700_hifi1.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <xtensa/xtensa.dtsi>
+#include <freq.h>
+#include <mem.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "cdns,tensilica-xtensa-lx7";
+			clock-frequency = <DT_FREQ_M(250)>;
+			reg = <0>;
+		};
+	};
+
+	itcm0: memory@580000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x580000 DT_SIZE_K(32)>;
+	};
+
+	itcm1: memory@680000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x680000 DT_SIZE_K(512)>;
+	};
+
+	dtcm: memory@20700000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x20700000 DT_SIZE_K(512)>;
+	};
+};
diff --git a/dts/xtensa/nxp/nxp_imxrt700_hifi4.dtsi b/dts/xtensa/nxp/nxp_imxrt700_hifi4.dtsi
new file mode 100644
index 00000000000..2a37cd5f2dc
--- /dev/null
+++ b/dts/xtensa/nxp/nxp_imxrt700_hifi4.dtsi
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <xtensa/xtensa.dtsi>
+#include <freq.h>
+#include <mem.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "cdns,tensilica-xtensa-lx7";
+			clock-frequency = <DT_FREQ_M(325)>;
+			reg = <0>;
+		};
+	};
+
+	itcm: memory@24020000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x24020000 DT_SIZE_K(64)>;
+	};
+
+	dtcm: memory@24000000 {
+		device_type = "memory";
+		compatible = "mmio-sram";
+		reg = <0x24000000 DT_SIZE_K(64)>;
+	};
+};
diff --git a/include/zephyr/app_memory/mem_domain.h b/include/zephyr/app_memory/mem_domain.h
index b950235fc0d..1b97ab4d333 100644
--- a/include/zephyr/app_memory/mem_domain.h
+++ b/include/zephyr/app_memory/mem_domain.h
@@ -89,6 +89,8 @@ struct k_mem_domain {
 	uint8_t num_partitions;
 };
 
+typedef struct k_mem_domain k_mem_domain_t;
+
 /**
  * Default memory domain
  *
diff --git a/include/zephyr/arch/arc/v2/linker.ld b/include/zephyr/arch/arc/v2/linker.ld
index 3a9ae9803e6..22926769ac6 100644
--- a/include/zephyr/arch/arc/v2/linker.ld
+++ b/include/zephyr/arch/arc/v2/linker.ld
@@ -142,13 +142,6 @@ SECTIONS {
 #include <snippets-rodata.ld>
 #include <zephyr/linker/kobject-rom.ld>
 
-#if defined(CONFIG_CPP) && !defined(CONFIG_STATIC_INIT_GNU) && defined(__MWDT_LINKER_CMD__)
-		. = ALIGN(4);
-		_fctors = .;
-		KEEP(*(.ctors*))
-		_ectors = .;
-#endif /* CONFIG_CPP && !CONFIG_STATIC_INIT_GNU && __MWDT_LINKER_CMD__ */
-
 /* This extra MPU alignment of RAMABLE_REGION is only required if we put ROMABLE_REGION and
  * RAMABLE_REGION into the same (continuous) memory - otherwise we can get beginning of the
  * RAMABLE_REGION in the end of ROMABLE_REGION MPU aperture.
@@ -317,11 +310,9 @@ SECTIONS {
 #endif
 
 	/DISCARD/ : {
-#if defined(CONFIG_CPP) && !defined(CONFIG_STATIC_INIT_GNU) && defined(__MWDT_LINKER_CMD__)
+		/* Discard all destructors */
 		*(.dtors*)
 		*(.fini*)
-		*(.eh_frame*)
-#endif /* CONFIG_CPP && !CONFIG_STATIC_INIT_GNU && __MWDT_LINKER_CMD__ */
 		*(.note.GNU-stack)
 		*(.got.plt)
 		*(.igot.plt)
diff --git a/include/zephyr/arch/arch_interface.h b/include/zephyr/arch/arch_interface.h
index 6721cec1171..395a36fb5f2 100644
--- a/include/zephyr/arch/arch_interface.h
+++ b/include/zephyr/arch/arch_interface.h
@@ -47,8 +47,6 @@ typedef struct z_thread_stack_element k_thread_stack_t;
 
 typedef void (*k_thread_entry_t)(void *p1, void *p2, void *p3);
 
-__deprecated typedef struct arch_esf z_arch_esf_t;
-
 /**
  * @defgroup arch-timing Architecture timing APIs
  * @ingroup arch-interface
@@ -1261,6 +1259,7 @@ void arch_spin_relax(void);
 /**
  * @defgroup arch-stackwalk Architecture-specific Stack Walk APIs
  * @ingroup arch-interface
+ * @brief Architecture-specific Stack Walk APIs
  *
  * To add API support to an architecture, `arch_stack_walk()` should be implemented and a non-user
  * configurable Kconfig `ARCH_HAS_STACKWALK` that is default to `y` should be created in the
diff --git a/include/zephyr/arch/arm/arch.h b/include/zephyr/arch/arm/arch.h
index 9bbcc2375f1..1a33196b15e 100644
--- a/include/zephyr/arch/arm/arch.h
+++ b/include/zephyr/arch/arm/arch.h
@@ -40,9 +40,9 @@
 #elif defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
 #include <zephyr/arch/arm/cortex_a_r/cpu.h>
 #include <zephyr/arch/arm/cortex_a_r/sys_io.h>
-#if defined(CONFIG_AARCH32_ARMV8_R)
+#if defined(CONFIG_AARCH32_ARMV8_R) || defined(CONFIG_CPU_CORTEX_A7)
 #include <zephyr/arch/arm/cortex_a_r/lib_helpers.h>
-#include <zephyr/arch/arm/cortex_a_r/armv8_timer.h>
+#include <zephyr/arch/arm/cortex_a_r/armv7_v8_timer.h>
 #else
 #include <zephyr/arch/arm/cortex_a_r/timer.h>
 #endif
@@ -99,13 +99,25 @@ enum k_fatal_error_reason_arch {
 	K_ERR_ARM_ALIGNMENT_FAULT,
 	K_ERR_ARM_BACKGROUND_FAULT,
 	K_ERR_ARM_PERMISSION_FAULT,
+	K_ERR_ARM_PERMISSION_FAULT_2ND_LEVEL,
 	K_ERR_ARM_SYNC_EXTERNAL_ABORT,
 	K_ERR_ARM_ASYNC_EXTERNAL_ABORT,
 	K_ERR_ARM_SYNC_PARITY_ERROR,
 	K_ERR_ARM_ASYNC_PARITY_ERROR,
 	K_ERR_ARM_DEBUG_EVENT,
 	K_ERR_ARM_TRANSLATION_FAULT,
-	K_ERR_ARM_UNSUPPORTED_EXCLUSIVE_ACCESS_FAULT
+	K_ERR_ARM_TRANSLATION_FAULT_2ND_LEVEL,
+	K_ERR_ARM_UNSUPPORTED_EXCLUSIVE_ACCESS_FAULT,
+	K_ERR_ARM_ACCESS_FLAG_FAULT_1ST_LEVEL,
+	K_ERR_ARM_ACCESS_FLAG_FAULT_2ND_LEVEL,
+	K_ERR_ARM_CACHE_MAINTENANCE_INSTRUCTION_FAULT,
+	K_ERR_ARM_DOMAIN_FAULT_1ST_LEVEL,
+	K_ERR_ARM_DOMAIN_FAULT_2ND_LEVEL,
+	K_ERR_ARM_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_1ST_LEVEL,
+	K_ERR_ARM_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_2ND_LEVEL,
+	K_ERR_ARM_TLB_CONFLICT_FAULT,
+	K_ERR_ARM_SYNC_PARITY_ERROR_TRANSLATION_TABLE_1ST_LEVEL,
+	K_ERR_ARM_SYNC_PARITY_ERROR_TRANSLATION_TABLE_2ND_LEVEL,
 };
 
 #endif /* _ASMLANGUAGE */
diff --git a/include/zephyr/arch/arm/asm_inline.h b/include/zephyr/arch/arm/asm_inline.h
index fe36fb2d0e1..54bf2a6f459 100644
--- a/include/zephyr/arch/arm/asm_inline.h
+++ b/include/zephyr/arch/arm/asm_inline.h
@@ -14,10 +14,10 @@
  * Include kernel.h instead
  */
 
-#if defined(__GNUC__)
+#if defined(__GNUC__) || defined(__ICCARM__)
 #include <zephyr/arch/arm/asm_inline_gcc.h>
 #else
-#include <arch/arm/asm_inline_other.h>
+#error Unknown toolchain in asm_inline.h
 #endif
 
 #endif /* ZEPHYR_INCLUDE_ARCH_ARM_ASM_INLINE_H_ */
diff --git a/include/zephyr/arch/arm/cortex_a_r/armv7_v8_timer.h b/include/zephyr/arch/arm/cortex_a_r/armv7_v8_timer.h
new file mode 100644
index 00000000000..911bed910f0
--- /dev/null
+++ b/include/zephyr/arch/arm/cortex_a_r/armv7_v8_timer.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
+ * Copyright (c) 2022 IoT.bzh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_ARMV7_V8_TIMER_H_
+#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_ARMV7_V8_TIMER_H_
+
+#ifndef _ASMLANGUAGE
+
+#include <zephyr/drivers/timer/arm_arch_timer.h>
+#include <zephyr/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ARM_ARCH_TIMER_IRQ	ARM_TIMER_VIRTUAL_IRQ
+#define ARM_ARCH_TIMER_PRIO	ARM_TIMER_VIRTUAL_PRIO
+#define ARM_ARCH_TIMER_FLAGS	ARM_TIMER_VIRTUAL_FLAGS
+
+static ALWAYS_INLINE void arm_arch_timer_init(void)
+{
+}
+
+static ALWAYS_INLINE void arm_arch_timer_set_compare(uint64_t val)
+{
+	write_cntv_cval(val);
+}
+
+static ALWAYS_INLINE void arm_arch_timer_enable(unsigned char enable)
+{
+	uint64_t cntv_ctl;
+
+	cntv_ctl = read_cntv_ctl();
+
+	if (enable) {
+		cntv_ctl |= CNTV_CTL_ENABLE_BIT;
+	} else {
+		cntv_ctl &= ~CNTV_CTL_ENABLE_BIT;
+	}
+
+	write_cntv_ctl(cntv_ctl);
+}
+
+static ALWAYS_INLINE void arm_arch_timer_set_irq_mask(bool mask)
+{
+	uint64_t cntv_ctl;
+
+	cntv_ctl = read_cntv_ctl();
+
+	if (mask) {
+		cntv_ctl |= CNTV_CTL_IMASK_BIT;
+	} else {
+		cntv_ctl &= ~CNTV_CTL_IMASK_BIT;
+	}
+
+	write_cntv_ctl(cntv_ctl);
+}
+
+static ALWAYS_INLINE uint64_t arm_arch_timer_count(void)
+{
+	return read_cntvct();
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ASMLANGUAGE */
+
+#endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_ARMV7_V8_TIMER_H_ */
diff --git a/include/zephyr/arch/arm/cortex_a_r/armv8_timer.h b/include/zephyr/arch/arm/cortex_a_r/armv8_timer.h
deleted file mode 100644
index 3950397f71a..00000000000
--- a/include/zephyr/arch/arm/cortex_a_r/armv8_timer.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright (c) 2019 Carlo Caione <ccaione@baylibre.com>
- * Copyright (c) 2022 IoT.bzh
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_ARMV8_TIMER_H_
-#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_ARMV8_TIMER_H_
-
-#ifndef _ASMLANGUAGE
-
-#include <zephyr/drivers/timer/arm_arch_timer.h>
-#include <zephyr/types.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ARM_ARCH_TIMER_IRQ	ARM_TIMER_VIRTUAL_IRQ
-#define ARM_ARCH_TIMER_PRIO	ARM_TIMER_VIRTUAL_PRIO
-#define ARM_ARCH_TIMER_FLAGS	ARM_TIMER_VIRTUAL_FLAGS
-
-static ALWAYS_INLINE void arm_arch_timer_init(void)
-{
-}
-
-static ALWAYS_INLINE void arm_arch_timer_set_compare(uint64_t val)
-{
-	write_cntv_cval(val);
-}
-
-static ALWAYS_INLINE void arm_arch_timer_enable(unsigned char enable)
-{
-	uint64_t cntv_ctl;
-
-	cntv_ctl = read_cntv_ctl();
-
-	if (enable) {
-		cntv_ctl |= CNTV_CTL_ENABLE_BIT;
-	} else {
-		cntv_ctl &= ~CNTV_CTL_ENABLE_BIT;
-	}
-
-	write_cntv_ctl(cntv_ctl);
-}
-
-static ALWAYS_INLINE void arm_arch_timer_set_irq_mask(bool mask)
-{
-	uint64_t cntv_ctl;
-
-	cntv_ctl = read_cntv_ctl();
-
-	if (mask) {
-		cntv_ctl |= CNTV_CTL_IMASK_BIT;
-	} else {
-		cntv_ctl &= ~CNTV_CTL_IMASK_BIT;
-	}
-
-	write_cntv_ctl(cntv_ctl);
-}
-
-static ALWAYS_INLINE uint64_t arm_arch_timer_count(void)
-{
-	return read_cntvct();
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _ASMLANGUAGE */
-
-#endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_ARMV8_TIMER_H_ */
diff --git a/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld b/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld
index 1d2744e253b..dbc2ff1e94e 100644
--- a/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld
+++ b/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld
@@ -257,7 +257,10 @@ SECTIONS
 
     GROUP_START(RAMABLE_REGION)
 
+#if ROM_ADDR != RAM_ADDR
     . = RAM_ADDR;
+#endif
+
     /* Align the start of image RAM with the
      * minimum granularity required by MPU.
      */
diff --git a/include/zephyr/arch/arm/cortex_m/cpu.h b/include/zephyr/arch/arm/cortex_m/cpu.h
index 064d8f92d56..096f5aabba8 100644
--- a/include/zephyr/arch/arm/cortex_m/cpu.h
+++ b/include/zephyr/arch/arm/cortex_m/cpu.h
@@ -12,9 +12,9 @@
 #define _SCS_BASE_ADDR _PPB_INT_SCS
 
 /* ICSR defines */
-#define _SCS_ICSR (_SCS_BASE_ADDR + 0xd04)
-#define _SCS_ICSR_PENDSV (1 << 28)
-#define _SCS_ICSR_UNPENDSV (1 << 27)
+#define _SCS_ICSR           (_SCS_BASE_ADDR + 0xd04)
+#define _SCS_ICSR_PENDSV    (1 << 28)
+#define _SCS_ICSR_UNPENDSV  (1 << 27)
 #define _SCS_ICSR_RETTOBASE (1 << 11)
 
 #define _SCS_MPU_CTRL (_SCS_BASE_ADDR + 0xd94)
@@ -34,20 +34,20 @@ extern "C" {
 #endif
 
 /* CP10 Access Bits */
-#define CPACR_CP10_Pos          20U
-#define CPACR_CP10_Msk          (3UL << CPACR_CP10_Pos)
-#define CPACR_CP10_NO_ACCESS    (0UL << CPACR_CP10_Pos)
-#define CPACR_CP10_PRIV_ACCESS  (1UL << CPACR_CP10_Pos)
-#define CPACR_CP10_RESERVED     (2UL << CPACR_CP10_Pos)
-#define CPACR_CP10_FULL_ACCESS  (3UL << CPACR_CP10_Pos)
+#define CPACR_CP10_Pos         20U
+#define CPACR_CP10_Msk         (3UL << CPACR_CP10_Pos)
+#define CPACR_CP10_NO_ACCESS   (0UL << CPACR_CP10_Pos)
+#define CPACR_CP10_PRIV_ACCESS (1UL << CPACR_CP10_Pos)
+#define CPACR_CP10_RESERVED    (2UL << CPACR_CP10_Pos)
+#define CPACR_CP10_FULL_ACCESS (3UL << CPACR_CP10_Pos)
 
 /* CP11 Access Bits */
-#define CPACR_CP11_Pos          22U
-#define CPACR_CP11_Msk          (3UL << CPACR_CP11_Pos)
-#define CPACR_CP11_NO_ACCESS    (0UL << CPACR_CP11_Pos)
-#define CPACR_CP11_PRIV_ACCESS  (1UL << CPACR_CP11_Pos)
-#define CPACR_CP11_RESERVED     (2UL << CPACR_CP11_Pos)
-#define CPACR_CP11_FULL_ACCESS  (3UL << CPACR_CP11_Pos)
+#define CPACR_CP11_Pos         22U
+#define CPACR_CP11_Msk         (3UL << CPACR_CP11_Pos)
+#define CPACR_CP11_NO_ACCESS   (0UL << CPACR_CP11_Pos)
+#define CPACR_CP11_PRIV_ACCESS (1UL << CPACR_CP11_Pos)
+#define CPACR_CP11_RESERVED    (2UL << CPACR_CP11_Pos)
+#define CPACR_CP11_FULL_ACCESS (3UL << CPACR_CP11_Pos)
 
 #ifdef CONFIG_PM_S2RAM
 
diff --git a/include/zephyr/arch/arm/cortex_m/exception.h b/include/zephyr/arch/arm/cortex_m/exception.h
index 6f60317891d..d675efa1549 100644
--- a/include/zephyr/arch/arm/cortex_m/exception.h
+++ b/include/zephyr/arch/arm/cortex_m/exception.h
@@ -43,17 +43,17 @@
 #define _EXCEPTION_RESERVED_PRIO 0
 #endif
 
-#define _EXC_FAULT_PRIO 0
+#define _EXC_FAULT_PRIO             0
 #define _EXC_ZERO_LATENCY_IRQS_PRIO 0
-#define _EXC_SVC_PRIO COND_CODE_1(CONFIG_ZERO_LATENCY_IRQS,		\
+#define _EXC_SVC_PRIO               COND_CODE_1(CONFIG_ZERO_LATENCY_IRQS,		\
 				  (CONFIG_ZERO_LATENCY_LEVELS), (0))
-#define _IRQ_PRIO_OFFSET (_EXCEPTION_RESERVED_PRIO + _EXC_SVC_PRIO)
-#define IRQ_PRIO_LOWEST (BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET) - 1)
+#define _IRQ_PRIO_OFFSET            (_EXCEPTION_RESERVED_PRIO + _EXC_SVC_PRIO)
+#define IRQ_PRIO_LOWEST             (BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET) - 1)
 
 #define _EXC_IRQ_DEFAULT_PRIO Z_EXC_PRIO(_IRQ_PRIO_OFFSET)
 
 /* Use lowest possible priority level for PendSV */
-#define _EXC_PENDSV_PRIO 0xff
+#define _EXC_PENDSV_PRIO      0xff
 #define _EXC_PENDSV_PRIO_MASK Z_EXC_PRIO(_EXC_PENDSV_PRIO)
 
 #ifdef _ASMLANGUAGE
@@ -99,7 +99,10 @@ struct __extra_esf_info {
 #endif /* CONFIG_EXTRA_EXCEPTION_INFO */
 
 /* ARM GPRs are often designated by two different names */
-#define sys_define_gpr_with_alias(name1, name2) union { uint32_t name1, name2; }
+#define sys_define_gpr_with_alias(name1, name2)                                                    \
+	union {                                                                                    \
+		uint32_t name1, name2;                                                             \
+	}
 
 struct arch_esf {
 	struct __basic_sf {
diff --git a/include/zephyr/arch/arm/cortex_m/memory_map.h b/include/zephyr/arch/arm/cortex_m/memory_map.h
index 1fbec9d19d7..30e800daf37 100644
--- a/include/zephyr/arch/arm/cortex_m/memory_map.h
+++ b/include/zephyr/arch/arm/cortex_m/memory_map.h
@@ -18,8 +18,8 @@
 #include <zephyr/sys/util.h>
 
 /* 0x00000000 -> 0x1fffffff: Code in ROM [0.5 GB] */
-#define _CODE_BASE_ADDR           0x00000000
-#define _CODE_END_ADDR            0x1FFFFFFF
+#define _CODE_BASE_ADDR 0x00000000
+#define _CODE_END_ADDR  0x1FFFFFFF
 
 /* 0x20000000 -> 0x3fffffff: SRAM [0.5GB] */
 #define _SRAM_BASE_ADDR           0x20000000
@@ -38,78 +38,77 @@
 #define _PERI_END_ADDR            0x5FFFFFFF
 
 /* 0x60000000 -> 0x9fffffff: external RAM [1GB] */
-#define _ERAM_BASE_ADDR           0x60000000
-#define _ERAM_END_ADDR            0x9FFFFFFF
+#define _ERAM_BASE_ADDR 0x60000000
+#define _ERAM_END_ADDR  0x9FFFFFFF
 
 /* 0xa0000000 -> 0xdfffffff: external devices [1GB] */
-#define _EDEV_BASE_ADDR           0xA0000000
-#define _EDEV_END_ADDR            0xDFFFFFFF
+#define _EDEV_BASE_ADDR 0xA0000000
+#define _EDEV_END_ADDR  0xDFFFFFFF
 
 /* 0xe0000000 -> 0xffffffff: varies by processor (see below) */
 
 /* 0xe0000000 -> 0xe00fffff: private peripheral bus */
 /* 0xe0000000 -> 0xe003ffff: internal [256KB] */
-#define _PPB_INT_BASE_ADDR        0xE0000000
-#if defined(CONFIG_CPU_CORTEX_M0) || defined(CONFIG_CPU_CORTEX_M0PLUS) || \
+#define _PPB_INT_BASE_ADDR 0xE0000000
+#if defined(CONFIG_CPU_CORTEX_M0) || defined(CONFIG_CPU_CORTEX_M0PLUS) ||                          \
 	defined(CONFIG_CPU_CORTEX_M1)
-#define _PPB_INT_RSVD_0           0xE0000000
-#define _PPB_INT_DWT              0xE0001000
-#define _PPB_INT_BPU              0xE0002000
-#define _PPB_INT_RSVD_1           0xE0003000
-#define _PPB_INT_SCS              0xE000E000
-#define _PPB_INT_RSVD_2           0xE000F000
-#elif defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4) || defined(CONFIG_CPU_CORTEX_M7)
-#define _PPB_INT_ITM              0xE0000000
-#define _PPB_INT_DWT              0xE0001000
-#define _PPB_INT_FPB              0xE0002000
-#define _PPB_INT_RSVD_1           0xE0003000
-#define _PPB_INT_SCS              0xE000E000
-#define _PPB_INT_RSVD_2           0xE000F000
-#elif defined(CONFIG_CPU_CORTEX_M23) || \
-	defined(CONFIG_CPU_CORTEX_M33) || \
-	defined(CONFIG_CPU_CORTEX_M55) || \
-	defined(CONFIG_CPU_CORTEX_M85)
-#define _PPB_INT_RSVD_0           0xE0000000
-#define _PPB_INT_SCS              0xE000E000
-#define _PPB_INT_SCB              0xE000ED00
-#define _PPB_INT_RSVD_1           0xE002E000
+#define _PPB_INT_RSVD_0 0xE0000000
+#define _PPB_INT_DWT    0xE0001000
+#define _PPB_INT_BPU    0xE0002000
+#define _PPB_INT_RSVD_1 0xE0003000
+#define _PPB_INT_SCS    0xE000E000
+#define _PPB_INT_RSVD_2 0xE000F000
+#elif defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4) ||                            \
+	defined(CONFIG_CPU_CORTEX_M7)
+#define _PPB_INT_ITM    0xE0000000
+#define _PPB_INT_DWT    0xE0001000
+#define _PPB_INT_FPB    0xE0002000
+#define _PPB_INT_RSVD_1 0xE0003000
+#define _PPB_INT_SCS    0xE000E000
+#define _PPB_INT_RSVD_2 0xE000F000
+#elif defined(CONFIG_CPU_CORTEX_M23) || defined(CONFIG_CPU_CORTEX_M33) ||                          \
+	defined(CONFIG_CPU_CORTEX_M55) || defined(CONFIG_CPU_CORTEX_M85)
+#define _PPB_INT_RSVD_0 0xE0000000
+#define _PPB_INT_SCS    0xE000E000
+#define _PPB_INT_SCB    0xE000ED00
+#define _PPB_INT_RSVD_1 0xE002E000
 #else
 #error Unknown CPU
 #endif
-#define _PPB_INT_END_ADDR         0xE003FFFF
+#define _PPB_INT_END_ADDR 0xE003FFFF
 
 /* 0xe0000000 -> 0xe00fffff: private peripheral bus */
 /* 0xe0040000 -> 0xe00fffff: external [768K] */
-#define _PPB_EXT_BASE_ADDR        0xE0040000
-#if defined(CONFIG_CPU_CORTEX_M0) || defined(CONFIG_CPU_CORTEX_M0PLUS) \
-	|| defined(CONFIG_CPU_CORTEX_M1) || defined(CONFIG_CPU_CORTEX_M23)
+#define _PPB_EXT_BASE_ADDR 0xE0040000
+#if defined(CONFIG_CPU_CORTEX_M0) || defined(CONFIG_CPU_CORTEX_M0PLUS) ||                          \
+	defined(CONFIG_CPU_CORTEX_M1) || defined(CONFIG_CPU_CORTEX_M23)
 #elif defined(CONFIG_CPU_CORTEX_M3) || defined(CONFIG_CPU_CORTEX_M4)
-#define _PPB_EXT_TPIU             0xE0040000
-#define _PPB_EXT_ETM              0xE0041000
-#define _PPB_EXT_PPB              0xE0042000
-#define _PPB_EXT_ROM_TABLE        0xE00FF000
-#define _PPB_EXT_END_ADDR         0xE00FFFFF
-#elif defined(CONFIG_CPU_CORTEX_M33) || defined(CONFIG_CPU_CORTEX_M55) \
-	|| defined(CONFIG_CPU_CORTEX_M85)
-#undef  _PPB_EXT_BASE_ADDR
-#define _PPB_EXT_BASE_ADDR        0xE0044000
-#define _PPB_EXT_ROM_TABLE        0xE00FF000
-#define _PPB_EXT_END_ADDR         0xE00FFFFF
+#define _PPB_EXT_TPIU      0xE0040000
+#define _PPB_EXT_ETM       0xE0041000
+#define _PPB_EXT_PPB       0xE0042000
+#define _PPB_EXT_ROM_TABLE 0xE00FF000
+#define _PPB_EXT_END_ADDR  0xE00FFFFF
+#elif defined(CONFIG_CPU_CORTEX_M33) || defined(CONFIG_CPU_CORTEX_M55) ||                          \
+	defined(CONFIG_CPU_CORTEX_M85)
+#undef _PPB_EXT_BASE_ADDR
+#define _PPB_EXT_BASE_ADDR 0xE0044000
+#define _PPB_EXT_ROM_TABLE 0xE00FF000
+#define _PPB_EXT_END_ADDR  0xE00FFFFF
 #elif defined(CONFIG_CPU_CORTEX_M7)
-#define _PPB_EXT_BASE_ADDR        0xE0040000
-#define _PPB_EXT_RSVD_TPIU        0xE0040000
-#define _PPB_EXT_ETM              0xE0041000
-#define _PPB_EXT_CTI              0xE0042000
-#define _PPB_EXT_PPB              0xE0043000
-#define _PPB_EXT_PROC_ROM_TABLE   0xE00FE000
-#define _PPB_EXT_PPB_ROM_TABLE    0xE00FF000
+#define _PPB_EXT_BASE_ADDR      0xE0040000
+#define _PPB_EXT_RSVD_TPIU      0xE0040000
+#define _PPB_EXT_ETM            0xE0041000
+#define _PPB_EXT_CTI            0xE0042000
+#define _PPB_EXT_PPB            0xE0043000
+#define _PPB_EXT_PROC_ROM_TABLE 0xE00FE000
+#define _PPB_EXT_PPB_ROM_TABLE  0xE00FF000
 #else
 #error Unknown CPU
 #endif
-#define _PPB_EXT_END_ADDR         0xE00FFFFF
+#define _PPB_EXT_END_ADDR 0xE00FFFFF
 
 /* 0xe0100000 -> 0xffffffff: vendor-specific [0.5GB-1MB or 511MB]  */
-#define _VENDOR_BASE_ADDR         0xE0100000
-#define _VENDOR_END_ADDR          0xFFFFFFFF
+#define _VENDOR_BASE_ADDR 0xE0100000
+#define _VENDOR_END_ADDR  0xFFFFFFFF
 
 #endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_MEMORY_MAP_H_ */
diff --git a/include/zephyr/arch/arm/cortex_m/scripts/linker.ld b/include/zephyr/arch/arm/cortex_m/scripts/linker.ld
index 6a1e91b66ed..7edfc1b7e41 100644
--- a/include/zephyr/arch/arm/cortex_m/scripts/linker.ld
+++ b/include/zephyr/arch/arm/cortex_m/scripts/linker.ld
@@ -307,7 +307,10 @@ SECTIONS
 
     GROUP_START(RAMABLE_REGION)
 
+#if ROM_ADDR != RAM_ADDR
 	. = RAM_ADDR;
+#endif
+
 	/* Align the start of image RAM with the
 	 * minimum granularity required by MPU.
 	 */
@@ -327,35 +330,6 @@ SECTIONS
 
 	_app_smem_size = _app_smem_end - _app_smem_start;
 	_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
-
-    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
-	{
-        /*
-         * For performance, BSS section is assumed to be 4 byte aligned and
-         * a multiple of 4 bytes
-         */
-        . = ALIGN(4);
-	__bss_start = .;
-	__kernel_ram_start = .;
-
-	*(.bss)
-	*(".bss.*")
-	*(COMMON)
-	*(".kernel_bss.*")
-
-#ifdef CONFIG_CODE_DATA_RELOCATION
-#include <linker_sram_bss_relocate.ld>
-#endif
-
-        /*
-         * As memory is cleared in words only, it is simpler to ensure the BSS
-         * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
-		 */
-	__bss_end = ALIGN(4);
-	} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
-
-#include <zephyr/linker/common-noinit.ld>
-
 #endif  /* CONFIG_USERSPACE */
 
     GROUP_START(DATA_REGION)
@@ -499,8 +473,7 @@ SECTION_PROLOGUE(.last_section,,)
  * calculate this value here. */
 _flash_used = LOADADDR(.last_section) + SIZEOF(.last_section) - __rom_region_start;
 
-#ifndef CONFIG_USERSPACE
-   SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
+    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
 	{
         /*
          * For performance, BSS section is assumed to be 4 byte aligned and
@@ -526,23 +499,7 @@ _flash_used = LOADADDR(.last_section) + SIZEOF(.last_section) - __rom_region_sta
 	__bss_end = ALIGN(4);
 	} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
 
-    SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)
-        {
-        /*
-         * This section is used for non-initialized objects that
-         * will not be cleared during the boot process.
-         */
-        *(.noinit)
-        *(".noinit.*")
-	*(".kernel_noinit.*")
-
-/* Located in generated directory. This file is populated by the
- * zephyr_linker_sources() Cmake function.
- */
-#include <snippets-noinit.ld>
-
-        } GROUP_NOLOAD_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
-#endif /* CONFIG_USERSPACE */
+#include <zephyr/linker/common-noinit.ld>
 
     /* Define linker symbols */
 
diff --git a/include/zephyr/arch/arm/irq.h b/include/zephyr/arch/arm/irq.h
index efb6abf90f1..1fbc2ab3045 100644
--- a/include/zephyr/arch/arm/irq.h
+++ b/include/zephyr/arch/arm/irq.h
@@ -35,20 +35,23 @@ GTEXT(z_soc_irq_eoi)
 #else
 
 #if !defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
+extern void arm_irq_enable(unsigned int irq);
+extern void arm_irq_disable(unsigned int irq);
+extern int arm_irq_is_enabled(unsigned int irq);
+extern void arm_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags);
+#if !defined(CONFIG_MULTI_LEVEL_INTERRUPTS)
+#define arch_irq_enable(irq)                     arm_irq_enable(irq)
+#define arch_irq_disable(irq)                    arm_irq_disable(irq)
+#define arch_irq_is_enabled(irq)                 arm_irq_is_enabled(irq)
+#define z_arm_irq_priority_set(irq, prio, flags) arm_irq_priority_set(irq, prio, flags)
+#endif
+#endif
 
-extern void arch_irq_enable(unsigned int irq);
-extern void arch_irq_disable(unsigned int irq);
-extern int arch_irq_is_enabled(unsigned int irq);
-
-/* internal routine documented in C file, needed by IRQ_CONNECT() macro */
-extern void z_arm_irq_priority_set(unsigned int irq, unsigned int prio,
-				   uint32_t flags);
-
-#else
-
+#if defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER) || defined(CONFIG_MULTI_LEVEL_INTERRUPTS)
 /*
- * When a custom interrupt controller is specified, map the architecture
- * interrupt control functions to the SoC layer interrupt control functions.
+ * When a custom interrupt controller or multi-level interrupts is specified,
+ * map the architecture interrupt control functions to the SoC layer interrupt
+ * control functions.
  */
 
 void z_soc_irq_init(void);
@@ -69,7 +72,7 @@ void z_soc_irq_eoi(unsigned int irq);
 #define z_arm_irq_priority_set(irq, prio, flags)	\
 	z_soc_irq_priority_set(irq, prio, flags)
 
-#endif /* !CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER */
+#endif
 
 extern void z_arm_int_exit(void);
 
@@ -166,20 +169,12 @@ static inline void arch_isr_direct_footer(int maybe_swap)
 	}
 }
 
-#if defined(__clang__)
-#define ARCH_ISR_DIAG_OFF \
-	_Pragma("clang diagnostic push") \
-	_Pragma("clang diagnostic ignored \"-Wextra\"")
-#define ARCH_ISR_DIAG_ON _Pragma("clang diagnostic pop")
-#elif defined(__GNUC__)
 #define ARCH_ISR_DIAG_OFF \
-	_Pragma("GCC diagnostic push") \
-	_Pragma("GCC diagnostic ignored \"-Wattributes\"")
-#define ARCH_ISR_DIAG_ON _Pragma("GCC diagnostic pop")
-#else
-#define ARCH_ISR_DIAG_OFF
-#define ARCH_ISR_DIAG_ON
-#endif
+	TOOLCHAIN_DISABLE_CLANG_WARNING(TOOLCHAIN_WARNING_EXTRA) \
+	TOOLCHAIN_DISABLE_GCC_WARNING(TOOLCHAIN_WARNING_ATTRIBUTES)
+#define ARCH_ISR_DIAG_ON \
+	TOOLCHAIN_ENABLE_CLANG_WARNING(TOOLCHAIN_WARNING_EXTRA) \
+	TOOLCHAIN_ENABLE_GCC_WARNING(TOOLCHAIN_WARNING_ATTRIBUTES)
 
 #define ARCH_ISR_DIRECT_DECLARE(name) \
 	static inline int name##_body(void); \
diff --git a/include/zephyr/arch/arm/mmu/arm_mmu.h b/include/zephyr/arch/arm/mmu/arm_mmu.h
index 4179436615d..76b8ec9b97d 100644
--- a/include/zephyr/arch/arm/mmu/arm_mmu.h
+++ b/include/zephyr/arch/arm/mmu/arm_mmu.h
@@ -10,6 +10,9 @@
 
 #ifndef _ASMLANGUAGE
 
+#include <stdint.h>
+#include <stdlib.h>
+
 /*
  * Comp.:
  * ARM Architecture Reference Manual, ARMv7-A and ARMv7-R edition,
diff --git a/include/zephyr/arch/arm/mpu/arm_mpu.h b/include/zephyr/arch/arm/mpu/arm_mpu.h
index e47883f1849..2aee4dd7efe 100644
--- a/include/zephyr/arch/arm/mpu/arm_mpu.h
+++ b/include/zephyr/arch/arm/mpu/arm_mpu.h
@@ -6,16 +6,11 @@
 #ifndef ZEPHYR_INCLUDE_ARCH_ARM_MPU_ARM_MPU_H_
 #define ZEPHYR_INCLUDE_ARCH_ARM_MPU_ARM_MPU_H_
 
-#if defined(CONFIG_CPU_CORTEX_M0PLUS) || \
-	defined(CONFIG_CPU_CORTEX_M3) || \
-	defined(CONFIG_CPU_CORTEX_M4) || \
-	defined(CONFIG_CPU_CORTEX_M7) || \
-	defined(CONFIG_ARMV7_R)
+#if defined(CONFIG_CPU_CORTEX_M0PLUS) || defined(CONFIG_CPU_CORTEX_M3) ||                          \
+	defined(CONFIG_CPU_CORTEX_M4) || defined(CONFIG_CPU_CORTEX_M7) || defined(CONFIG_ARMV7_R)
 #include <zephyr/arch/arm/mpu/arm_mpu_v7m.h>
-#elif defined(CONFIG_CPU_CORTEX_M23) || \
-	defined(CONFIG_CPU_CORTEX_M33) || \
-	defined(CONFIG_CPU_CORTEX_M55) || \
-	defined(CONFIG_CPU_CORTEX_M85) || \
+#elif defined(CONFIG_CPU_CORTEX_M23) || defined(CONFIG_CPU_CORTEX_M33) ||                          \
+	defined(CONFIG_CPU_CORTEX_M55) || defined(CONFIG_CPU_CORTEX_M85) ||                        \
 	defined(CONFIG_AARCH32_ARMV8_R)
 #include <zephyr/arch/arm/mpu/arm_mpu_v8.h>
 #else
@@ -47,19 +42,19 @@ struct arm_mpu_config {
 };
 
 #if defined(CONFIG_ARMV7_R)
-#define MPU_REGION_ENTRY(_name, _base, _size, _attr) \
-	{\
-		.name = _name, \
-		.base = _base, \
-		.size = _size, \
-		.attr = _attr, \
+#define MPU_REGION_ENTRY(_name, _base, _size, _attr)                                               \
+	{                                                                                          \
+		.name = _name,                                                                     \
+		.base = _base,                                                                     \
+		.size = _size,                                                                     \
+		.attr = _attr,                                                                     \
 	}
 #else
-#define MPU_REGION_ENTRY(_name, _base, _attr) \
-	{\
-		.name = _name, \
-		.base = _base, \
-		.attr = _attr, \
+#define MPU_REGION_ENTRY(_name, _base, _attr)                                                      \
+	{                                                                                          \
+		.name = _name,                                                                     \
+		.base = _base,                                                                     \
+		.attr = _attr,                                                                     \
 	}
 #endif
 
diff --git a/include/zephyr/arch/arm/mpu/arm_mpu_v7m.h b/include/zephyr/arch/arm/mpu/arm_mpu_v7m.h
index 1ed8636ec50..02c7d13be58 100644
--- a/include/zephyr/arch/arm/mpu/arm_mpu_v7m.h
+++ b/include/zephyr/arch/arm/mpu/arm_mpu_v7m.h
@@ -46,73 +46,69 @@
 #define NOT_EXEC MPU_RASR_XN_Msk
 
 /* The following definitions are for internal use in arm_mpu.h. */
-#define STRONGLY_ORDERED_SHAREABLE      MPU_RASR_S_Msk
-#define DEVICE_SHAREABLE                (MPU_RASR_B_Msk | MPU_RASR_S_Msk)
-#define NORMAL_OUTER_INNER_WRITE_THROUGH_SHAREABLE \
-		(MPU_RASR_C_Msk | MPU_RASR_S_Msk)
-#define NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE	MPU_RASR_C_Msk
-#define NORMAL_OUTER_INNER_WRITE_BACK_SHAREABLE	\
-		(MPU_RASR_C_Msk | MPU_RASR_B_Msk | MPU_RASR_S_Msk)
-#define NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE \
-		(MPU_RASR_C_Msk | MPU_RASR_B_Msk)
-#define NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE \
-		((1 << MPU_RASR_TEX_Pos) | MPU_RASR_S_Msk)
-#define NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE \
-		(1 << MPU_RASR_TEX_Pos)
-#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_SHAREABLE \
-	((1 << MPU_RASR_TEX_Pos) |\
-	 MPU_RASR_C_Msk | MPU_RASR_B_Msk | MPU_RASR_S_Msk)
-#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE \
+#define STRONGLY_ORDERED_SHAREABLE                     MPU_RASR_S_Msk
+#define DEVICE_SHAREABLE                               (MPU_RASR_B_Msk | MPU_RASR_S_Msk)
+#define NORMAL_OUTER_INNER_WRITE_THROUGH_SHAREABLE     (MPU_RASR_C_Msk | MPU_RASR_S_Msk)
+#define NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE MPU_RASR_C_Msk
+/* clang-format off */
+#define NORMAL_OUTER_INNER_WRITE_BACK_SHAREABLE                                                    \
+	(MPU_RASR_C_Msk | MPU_RASR_B_Msk | MPU_RASR_S_Msk)
+/* clang-format on */
+#define NORMAL_OUTER_INNER_WRITE_BACK_NON_SHAREABLE    (MPU_RASR_C_Msk | MPU_RASR_B_Msk)
+#define NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE     ((1 << MPU_RASR_TEX_Pos) | MPU_RASR_S_Msk)
+#define NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE (1 << MPU_RASR_TEX_Pos)
+#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_SHAREABLE                                \
+	((1 << MPU_RASR_TEX_Pos) | MPU_RASR_C_Msk | MPU_RASR_B_Msk | MPU_RASR_S_Msk)
+#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE                            \
 	((1 << MPU_RASR_TEX_Pos) | MPU_RASR_C_Msk | MPU_RASR_B_Msk)
-#define DEVICE_NON_SHAREABLE            (2 << MPU_RASR_TEX_Pos)
+#define DEVICE_NON_SHAREABLE (2 << MPU_RASR_TEX_Pos)
 
 /* Bit-masks to disable sub-regions. */
-#define SUB_REGION_0_DISABLED	((0x01 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
-#define SUB_REGION_1_DISABLED	((0x02 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
-#define SUB_REGION_2_DISABLED	((0x04 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
-#define SUB_REGION_3_DISABLED	((0x08 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
-#define SUB_REGION_4_DISABLED	((0x10 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
-#define SUB_REGION_5_DISABLED	((0x20 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
-#define SUB_REGION_6_DISABLED	((0x40 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
-#define SUB_REGION_7_DISABLED	((0x80 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
+#define SUB_REGION_0_DISABLED ((0x01 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
+#define SUB_REGION_1_DISABLED ((0x02 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
+#define SUB_REGION_2_DISABLED ((0x04 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
+#define SUB_REGION_3_DISABLED ((0x08 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
+#define SUB_REGION_4_DISABLED ((0x10 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
+#define SUB_REGION_5_DISABLED ((0x20 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
+#define SUB_REGION_6_DISABLED ((0x40 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
+#define SUB_REGION_7_DISABLED ((0x80 << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk)
 
+#define REGION_SIZE(size) ((ARM_MPU_REGION_SIZE_##size << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)
 
-#define REGION_SIZE(size) ((ARM_MPU_REGION_SIZE_ ## size \
-	<< MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)
+#define REGION_32B  REGION_SIZE(32B)
+#define REGION_64B  REGION_SIZE(64B)
+#define REGION_128B REGION_SIZE(128B)
+#define REGION_256B REGION_SIZE(256B)
+#define REGION_512B REGION_SIZE(512B)
+#define REGION_1K   REGION_SIZE(1KB)
+#define REGION_2K   REGION_SIZE(2KB)
+#define REGION_4K   REGION_SIZE(4KB)
+#define REGION_8K   REGION_SIZE(8KB)
+#define REGION_16K  REGION_SIZE(16KB)
+#define REGION_32K  REGION_SIZE(32KB)
+#define REGION_64K  REGION_SIZE(64KB)
+#define REGION_128K REGION_SIZE(128KB)
+#define REGION_256K REGION_SIZE(256KB)
+#define REGION_512K REGION_SIZE(512KB)
+#define REGION_1M   REGION_SIZE(1MB)
+#define REGION_2M   REGION_SIZE(2MB)
+#define REGION_4M   REGION_SIZE(4MB)
+#define REGION_8M   REGION_SIZE(8MB)
+#define REGION_16M  REGION_SIZE(16MB)
+#define REGION_32M  REGION_SIZE(32MB)
+#define REGION_64M  REGION_SIZE(64MB)
+#define REGION_128M REGION_SIZE(128MB)
+#define REGION_256M REGION_SIZE(256MB)
+#define REGION_512M REGION_SIZE(512MB)
+#define REGION_1G   REGION_SIZE(1GB)
+#define REGION_2G   REGION_SIZE(2GB)
+#define REGION_4G   REGION_SIZE(4GB)
 
-#define REGION_32B      REGION_SIZE(32B)
-#define REGION_64B      REGION_SIZE(64B)
-#define REGION_128B     REGION_SIZE(128B)
-#define REGION_256B     REGION_SIZE(256B)
-#define REGION_512B     REGION_SIZE(512B)
-#define REGION_1K       REGION_SIZE(1KB)
-#define REGION_2K       REGION_SIZE(2KB)
-#define REGION_4K       REGION_SIZE(4KB)
-#define REGION_8K       REGION_SIZE(8KB)
-#define REGION_16K      REGION_SIZE(16KB)
-#define REGION_32K      REGION_SIZE(32KB)
-#define REGION_64K      REGION_SIZE(64KB)
-#define REGION_128K     REGION_SIZE(128KB)
-#define REGION_256K     REGION_SIZE(256KB)
-#define REGION_512K     REGION_SIZE(512KB)
-#define REGION_1M       REGION_SIZE(1MB)
-#define REGION_2M       REGION_SIZE(2MB)
-#define REGION_4M       REGION_SIZE(4MB)
-#define REGION_8M       REGION_SIZE(8MB)
-#define REGION_16M      REGION_SIZE(16MB)
-#define REGION_32M      REGION_SIZE(32MB)
-#define REGION_64M      REGION_SIZE(64MB)
-#define REGION_128M     REGION_SIZE(128MB)
-#define REGION_256M     REGION_SIZE(256MB)
-#define REGION_512M     REGION_SIZE(512MB)
-#define REGION_1G       REGION_SIZE(1GB)
-#define REGION_2G       REGION_SIZE(2GB)
-#define REGION_4G       REGION_SIZE(4GB)
-
-#define ARM_MPU_REGION_INIT(p_name, p_base, p_size, p_attr)	\
-	{ .name = p_name,					\
-	  .base = p_base,					\
-	  .attr = p_attr(size_to_mpu_rasr_size(p_size)),	\
+#define ARM_MPU_REGION_INIT(p_name, p_base, p_size, p_attr)                                        \
+	{                                                                                          \
+		.name = p_name,                                                                    \
+		.base = p_base,                                                                    \
+		.attr = p_attr(size_to_mpu_rasr_size(p_size)),                                     \
 	}
 
 /* Some helper defines for common regions */
@@ -121,33 +117,20 @@
  * CONFIG_XIP=n, the entire image will be linked to SRAM, so we need to keep
  * the SRAM region XN bit clear or the application code will not be executable.
  */
-#define REGION_RAM_ATTR(size) \
-{ \
-	(NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE | \
-	 IF_ENABLED(CONFIG_XIP, (MPU_RASR_XN_Msk |)) size | P_RW_U_NA_Msk) \
-}
-#define REGION_RAM_NOCACHE_ATTR(size) \
-{ \
-	(NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | \
-	 MPU_RASR_XN_Msk | size | P_RW_U_NA_Msk) \
-}
+#define REGION_RAM_ATTR(size)                                                                      \
+	{(NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE |                        \
+	  IF_ENABLED(CONFIG_XIP, (MPU_RASR_XN_Msk |)) size | P_RW_U_NA_Msk)}
+#define REGION_RAM_NOCACHE_ATTR(size)                                                              \
+	{(NORMAL_OUTER_INNER_NON_CACHEABLE_NON_SHAREABLE | MPU_RASR_XN_Msk | size | P_RW_U_NA_Msk)}
 #if defined(CONFIG_MPU_ALLOW_FLASH_WRITE)
-#define REGION_FLASH_ATTR(size) \
-{ \
-	(NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE | size | \
-		P_RW_U_RO_Msk) \
-}
+#define REGION_FLASH_ATTR(size)                                                                    \
+	{(NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE | size | P_RW_U_RO_Msk)}
 #else
-#define REGION_FLASH_ATTR(size) \
-{ \
-	(NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE | size | RO_Msk) \
-}
+#define REGION_FLASH_ATTR(size) {(NORMAL_OUTER_INNER_WRITE_THROUGH_NON_SHAREABLE | size | RO_Msk)}
 #endif
-#define REGION_PPB_ATTR(size) { (STRONGLY_ORDERED_SHAREABLE | size | \
-		P_RW_U_NA_Msk) }
-#define REGION_IO_ATTR(size) { (DEVICE_NON_SHAREABLE | size | P_RW_U_NA_Msk) }
-#define REGION_EXTMEM_ATTR(size) { (STRONGLY_ORDERED_SHAREABLE | size | \
-		NO_ACCESS_Msk) }
+#define REGION_PPB_ATTR(size)    {(STRONGLY_ORDERED_SHAREABLE | size | P_RW_U_NA_Msk)}
+#define REGION_IO_ATTR(size)     {(DEVICE_NON_SHAREABLE | size | P_RW_U_NA_Msk)}
+#define REGION_EXTMEM_ATTR(size) {(STRONGLY_ORDERED_SHAREABLE | size | NO_ACCESS_Msk)}
 
 struct arm_mpu_region_attr {
 	/* Attributes belonging to RASR (including the encoded region size) */
@@ -162,12 +145,12 @@ typedef struct {
 } k_mem_partition_attr_t;
 
 /* Read-Write access permission attributes */
-#define _K_MEM_PARTITION_P_NA_U_NA	(NO_ACCESS_Msk | NOT_EXEC)
-#define _K_MEM_PARTITION_P_RW_U_RW	(P_RW_U_RW_Msk | NOT_EXEC)
-#define _K_MEM_PARTITION_P_RW_U_RO	(P_RW_U_RO_Msk | NOT_EXEC)
-#define _K_MEM_PARTITION_P_RW_U_NA	(P_RW_U_NA_Msk | NOT_EXEC)
-#define _K_MEM_PARTITION_P_RO_U_RO	(P_RO_U_RO_Msk | NOT_EXEC)
-#define _K_MEM_PARTITION_P_RO_U_NA	(P_RO_U_NA_Msk | NOT_EXEC)
+#define _K_MEM_PARTITION_P_NA_U_NA (NO_ACCESS_Msk | NOT_EXEC)
+#define _K_MEM_PARTITION_P_RW_U_RW (P_RW_U_RW_Msk | NOT_EXEC)
+#define _K_MEM_PARTITION_P_RW_U_RO (P_RW_U_RO_Msk | NOT_EXEC)
+#define _K_MEM_PARTITION_P_RW_U_NA (P_RW_U_NA_Msk | NOT_EXEC)
+#define _K_MEM_PARTITION_P_RO_U_RO (P_RO_U_RO_Msk | NOT_EXEC)
+#define _K_MEM_PARTITION_P_RO_U_NA (P_RO_U_NA_Msk | NOT_EXEC)
 
 /* Execution-allowed attributes */
 #define _K_MEM_PARTITION_P_RWX_U_RWX (P_RW_U_RW_Msk)
@@ -184,35 +167,44 @@ typedef struct {
  */
 
 /* Read-Write access permission attributes (default cache-ability) */
-#define K_MEM_PARTITION_P_NA_U_NA	((k_mem_partition_attr_t) \
-	{ _K_MEM_PARTITION_P_NA_U_NA | \
-	  NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
-#define K_MEM_PARTITION_P_RW_U_RW	((k_mem_partition_attr_t) \
-	{ _K_MEM_PARTITION_P_RW_U_RW | \
-	  NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
-#define K_MEM_PARTITION_P_RW_U_RO	((k_mem_partition_attr_t) \
-	{ _K_MEM_PARTITION_P_RW_U_RO | \
-	  NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
-#define K_MEM_PARTITION_P_RW_U_NA	((k_mem_partition_attr_t) \
-	{ _K_MEM_PARTITION_P_RW_U_NA | \
-	  NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
-#define K_MEM_PARTITION_P_RO_U_RO	((k_mem_partition_attr_t) \
-	{ _K_MEM_PARTITION_P_RO_U_RO | \
-	  NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
-#define K_MEM_PARTITION_P_RO_U_NA	((k_mem_partition_attr_t) \
-	{ _K_MEM_PARTITION_P_RO_U_NA | \
-	  NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
+#define K_MEM_PARTITION_P_NA_U_NA                                                                  \
+	((k_mem_partition_attr_t){                                                                 \
+		_K_MEM_PARTITION_P_NA_U_NA |                                                       \
+		NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
+#define K_MEM_PARTITION_P_RW_U_RW                                                                  \
+	((k_mem_partition_attr_t){                                                                 \
+		_K_MEM_PARTITION_P_RW_U_RW |                                                       \
+		NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
+#define K_MEM_PARTITION_P_RW_U_RO                                                                  \
+	((k_mem_partition_attr_t){                                                                 \
+		_K_MEM_PARTITION_P_RW_U_RO |                                                       \
+		NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
+#define K_MEM_PARTITION_P_RW_U_NA                                                                  \
+	((k_mem_partition_attr_t){                                                                 \
+		_K_MEM_PARTITION_P_RW_U_NA |                                                       \
+		NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
+#define K_MEM_PARTITION_P_RO_U_RO                                                                  \
+	((k_mem_partition_attr_t){                                                                 \
+		_K_MEM_PARTITION_P_RO_U_RO |                                                       \
+		NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
+#define K_MEM_PARTITION_P_RO_U_NA                                                                  \
+	((k_mem_partition_attr_t){                                                                 \
+		_K_MEM_PARTITION_P_RO_U_NA |                                                       \
+		NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
 
 /* Execution-allowed attributes (default-cacheability) */
-#define K_MEM_PARTITION_P_RWX_U_RWX	((k_mem_partition_attr_t) \
-	{ _K_MEM_PARTITION_P_RWX_U_RWX | \
-	  NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
-#define K_MEM_PARTITION_P_RWX_U_RX	((k_mem_partition_attr_t) \
-	{ _K_MEM_PARTITION_P_RWX_U_RX | \
-	  NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
-#define K_MEM_PARTITION_P_RX_U_RX	((k_mem_partition_attr_t) \
-	{ _K_MEM_PARTITION_P_RX_U_RX | \
-	  NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
+#define K_MEM_PARTITION_P_RWX_U_RWX                                                                \
+	((k_mem_partition_attr_t){                                                                 \
+		_K_MEM_PARTITION_P_RWX_U_RWX |                                                     \
+		NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
+#define K_MEM_PARTITION_P_RWX_U_RX                                                                 \
+	((k_mem_partition_attr_t){                                                                 \
+		_K_MEM_PARTITION_P_RWX_U_RX |                                                      \
+		NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
+#define K_MEM_PARTITION_P_RX_U_RX                                                                  \
+	((k_mem_partition_attr_t){                                                                 \
+		_K_MEM_PARTITION_P_RX_U_RX |                                                       \
+		NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_SHAREABLE})
 
 /*
  * @brief Evaluate Write-ability
@@ -222,19 +214,19 @@ typedef struct {
  * @param attr The k_mem_partition_attr_t object holding the
  *             MPU attributes to be checked against write-ability.
  */
-#define K_MEM_PARTITION_IS_WRITABLE(attr) \
-	({ \
-		int __is_writable__; \
-		switch (attr.rasr_attr & MPU_RASR_AP_Msk) { \
-		case P_RW_U_RW_Msk: \
-		case P_RW_U_RO_Msk: \
-		case P_RW_U_NA_Msk: \
-			__is_writable__ = 1; \
-			break; \
-		default: \
-			__is_writable__ = 0; \
-		} \
-		__is_writable__; \
+#define K_MEM_PARTITION_IS_WRITABLE(attr)                                                          \
+	({                                                                                         \
+		int __is_writable__;                                                               \
+		switch (attr.rasr_attr & MPU_RASR_AP_Msk) {                                        \
+		case P_RW_U_RW_Msk:                                                                \
+		case P_RW_U_RO_Msk:                                                                \
+		case P_RW_U_NA_Msk:                                                                \
+			__is_writable__ = 1;                                                       \
+			break;                                                                     \
+		default:                                                                           \
+			__is_writable__ = 0;                                                       \
+		}                                                                                  \
+		__is_writable__;                                                                   \
 	})
 
 /*
@@ -246,46 +238,56 @@ typedef struct {
  *             MPU attributes to be checked against execution
  *             allowance.
  */
-#define K_MEM_PARTITION_IS_EXECUTABLE(attr) \
-	(!((attr.rasr_attr) & (NOT_EXEC)))
+#define K_MEM_PARTITION_IS_EXECUTABLE(attr) (!((attr.rasr_attr) & (NOT_EXEC)))
 
 /* Attributes for no-cache enabling (share-ability is selected by default) */
 
-#define K_MEM_PARTITION_P_NA_U_NA_NOCACHE ((k_mem_partition_attr_t) \
-	{(_K_MEM_PARTITION_P_NA_U_NA \
-	| NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
-#define K_MEM_PARTITION_P_RW_U_RW_NOCACHE ((k_mem_partition_attr_t) \
-	{(_K_MEM_PARTITION_P_RW_U_RW \
-	| NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
-#define K_MEM_PARTITION_P_RW_U_RO_NOCACHE ((k_mem_partition_attr_t) \
-	{(_K_MEM_PARTITION_P_RW_U_RO \
-	| NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
-#define K_MEM_PARTITION_P_RW_U_NA_NOCACHE ((k_mem_partition_attr_t) \
-	{(_K_MEM_PARTITION_P_RW_U_NA \
-	| NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
-#define K_MEM_PARTITION_P_RO_U_RO_NOCACHE ((k_mem_partition_attr_t) \
-	{(_K_MEM_PARTITION_P_RO_U_RO \
-	| NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
-#define K_MEM_PARTITION_P_RO_U_NA_NOCACHE ((k_mem_partition_attr_t) \
-	{(_K_MEM_PARTITION_P_RO_U_NA \
-	| NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
+#define K_MEM_PARTITION_P_NA_U_NA_NOCACHE                                                          \
+	((k_mem_partition_attr_t){                                                                 \
+		(_K_MEM_PARTITION_P_NA_U_NA | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
+#define K_MEM_PARTITION_P_RW_U_RW_NOCACHE                                                          \
+	((k_mem_partition_attr_t){                                                                 \
+		(_K_MEM_PARTITION_P_RW_U_RW | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
+#define K_MEM_PARTITION_P_RW_U_RO_NOCACHE                                                          \
+	((k_mem_partition_attr_t){                                                                 \
+		(_K_MEM_PARTITION_P_RW_U_RO | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
+#define K_MEM_PARTITION_P_RW_U_NA_NOCACHE                                                          \
+	((k_mem_partition_attr_t){                                                                 \
+		(_K_MEM_PARTITION_P_RW_U_NA | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
+#define K_MEM_PARTITION_P_RO_U_RO_NOCACHE                                                          \
+	((k_mem_partition_attr_t){                                                                 \
+		(_K_MEM_PARTITION_P_RO_U_RO | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
+#define K_MEM_PARTITION_P_RO_U_NA_NOCACHE                                                          \
+	((k_mem_partition_attr_t){                                                                 \
+		(_K_MEM_PARTITION_P_RO_U_NA | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
 
-#define K_MEM_PARTITION_P_RWX_U_RWX_NOCACHE ((k_mem_partition_attr_t) \
-	{(_K_MEM_PARTITION_P_RWX_U_RWX \
-	| NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
-#define K_MEM_PARTITION_P_RWX_U_RX_NOCACHE  ((k_mem_partition_attr_t) \
-	{(_K_MEM_PARTITION_P_RWX_U_RX  \
-	| NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
-#define K_MEM_PARTITION_P_RX_U_RX_NOCACHE   ((k_mem_partition_attr_t) \
-	{(_K_MEM_PARTITION_P_RX_U_RX   \
-	| NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
+#define K_MEM_PARTITION_P_RWX_U_RWX_NOCACHE                                                        \
+	((k_mem_partition_attr_t){                                                                 \
+		(_K_MEM_PARTITION_P_RWX_U_RWX | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
+#define K_MEM_PARTITION_P_RWX_U_RX_NOCACHE                                                         \
+	((k_mem_partition_attr_t){                                                                 \
+		(_K_MEM_PARTITION_P_RWX_U_RX | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
+#define K_MEM_PARTITION_P_RX_U_RX_NOCACHE                                                          \
+	((k_mem_partition_attr_t){                                                                 \
+		(_K_MEM_PARTITION_P_RX_U_RX | NORMAL_OUTER_INNER_NON_CACHEABLE_SHAREABLE)})
 
 #endif /* _ASMLANGUAGE */
 
-#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
-	BUILD_ASSERT(!(((size) & ((size) - 1))) && \
-		(size) >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE && \
-		!((uint32_t)(start) & ((size) - 1)), \
-		"the size of the partition must be power of 2" \
-		" and greater than or equal to the minimum MPU region size." \
-		"start address of the partition must align with size.")
+#define _ARCH_MEM_PARTITION_ALIGN_CHECK_SIZE(size)                                                 \
+	BUILD_ASSERT(!(((size) & ((size) - 1))) &&                                                 \
+		     (size) >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE,                           \
+		     "The size of the partition must be power of 2 and greater than or equal to "  \
+		     "the minimum MPU region size.\n")
+
+/* Some compilers do not handle BUILD_ASSERT on the values of pointers.*/
+#if defined(__IAR_SYSTEMS_ICC__)
+#define _ARCH_MEM_PARTITION_ALIGN_CHECK_START(start, size)
+#else
+#define _ARCH_MEM_PARTITION_ALIGN_CHECK_START(start, size)                                         \
+	BUILD_ASSERT(!((uint32_t)(start) & ((size) - 1)),                                          \
+		     "The start address of the partition must align with size.")
+#endif
+
+#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size)                                               \
+	_ARCH_MEM_PARTITION_ALIGN_CHECK_SIZE(size);                                                \
+	_ARCH_MEM_PARTITION_ALIGN_CHECK_START(start, size)
diff --git a/include/zephyr/arch/arm/mpu/arm_mpu_v8.h b/include/zephyr/arch/arm/mpu/arm_mpu_v8.h
index 77deb64beed..25ec225fc6b 100644
--- a/include/zephyr/arch/arm/mpu/arm_mpu_v8.h
+++ b/include/zephyr/arch/arm/mpu/arm_mpu_v8.h
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2018 Linaro Limited.
  * Copyright (c) 2018 Nordic Semiconductor ASA.
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,25 +13,25 @@
  * cache-ability attribution.
  */
 #if defined(CONFIG_AARCH32_ARMV8_R)
-#define MPU_IR_REGION_Msk       (0xFFU)
-#define MPU_IR_REGION_Pos       8U
+#define MPU_IR_REGION_Msk (0xFFU)
+#define MPU_IR_REGION_Pos 8U
 /* MPU RBAR Register attribute msk Definitions */
-#define MPU_RBAR_BASE_Pos       6U
-#define MPU_RBAR_BASE_Msk       (0x3FFFFFFFFFFFFFFUL << MPU_RBAR_BASE_Pos)
-#define MPU_RBAR_SH_Pos         3U
-#define MPU_RBAR_SH_Msk         (0x3UL << MPU_RBAR_SH_Pos)
-#define MPU_RBAR_AP_Pos         1U
-#define MPU_RBAR_AP_Msk         (0x3UL << MPU_RBAR_AP_Pos)
+#define MPU_RBAR_BASE_Pos 6U
+#define MPU_RBAR_BASE_Msk (0x3FFFFFFFFFFFFFFUL << MPU_RBAR_BASE_Pos)
+#define MPU_RBAR_SH_Pos   3U
+#define MPU_RBAR_SH_Msk   (0x3UL << MPU_RBAR_SH_Pos)
+#define MPU_RBAR_AP_Pos   1U
+#define MPU_RBAR_AP_Msk   (0x3UL << MPU_RBAR_AP_Pos)
 /* RBAR XN */
-#define MPU_RBAR_XN_Pos         0U
-#define MPU_RBAR_XN_Msk         (0x1UL << MPU_RBAR_XN_Pos)
+#define MPU_RBAR_XN_Pos   0U
+#define MPU_RBAR_XN_Msk   (0x1UL << MPU_RBAR_XN_Pos)
 
 /* MPU PLBAR Register Definitions */
-#define MPU_RLAR_LIMIT_Pos      6U
-#define MPU_RLAR_LIMIT_Msk      (0x3FFFFFFFFFFFFFFUL << MPU_RLAR_LIMIT_Pos)
-#define MPU_RLAR_AttrIndx_Pos   1U
-#define MPU_RLAR_AttrIndx_Msk   (0x7UL << MPU_RLAR_AttrIndx_Pos)
-#define MPU_RLAR_EN_Msk         (0x1UL)
+#define MPU_RLAR_LIMIT_Pos    6U
+#define MPU_RLAR_LIMIT_Msk    (0x3FFFFFFFFFFFFFFUL << MPU_RLAR_LIMIT_Pos)
+#define MPU_RLAR_AttrIndx_Pos 1U
+#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos)
+#define MPU_RLAR_EN_Msk       (0x1UL)
 #else
 #include <cmsis_core.h>
 #endif
@@ -66,20 +67,19 @@
 /* Attribute flag for not-allowing execution (eXecute Never) */
 #define NOT_EXEC MPU_RBAR_XN_Msk
 
+/* To prevent execution of MPU region in privileged mode */
+#define PRIV_EXEC_NEVER (1)
+
 /* Attribute flags for share-ability */
 #define NON_SHAREABLE       0x0
-#define NON_SHAREABLE_Msk \
-	((NON_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
-#define OUTER_SHAREABLE 0x2
-#define OUTER_SHAREABLE_Msk \
-	((OUTER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
-#define INNER_SHAREABLE 0x3
-#define INNER_SHAREABLE_Msk \
-	((INNER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
+#define NON_SHAREABLE_Msk   ((NON_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
+#define OUTER_SHAREABLE     0x2
+#define OUTER_SHAREABLE_Msk ((OUTER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
+#define INNER_SHAREABLE     0x3
+#define INNER_SHAREABLE_Msk ((INNER_SHAREABLE << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk)
 
 /* Helper define to calculate the region limit address. */
-#define REGION_LIMIT_ADDR(base, size) \
-	(((base & MPU_RBAR_BASE_Msk) + size - 1) & MPU_RLAR_LIMIT_Msk)
+#define REGION_LIMIT_ADDR(base, size) (((base & MPU_RBAR_BASE_Msk) + size - 1) & MPU_RLAR_LIMIT_Msk)
 
 /* Attribute flags for cache-ability */
 
@@ -101,10 +101,10 @@
  *   nE: The response should come from the end slave, not buffering in
  *   the interconnect.
  */
-#define DEVICE_nGnRnE	0x0U
-#define DEVICE_nGnRE	0x4U
-#define DEVICE_nGRE	0x8U
-#define DEVICE_GRE	0xCU
+#define DEVICE_nGnRnE 0x0U
+#define DEVICE_nGnRE  0x4U
+#define DEVICE_nGRE   0x8U
+#define DEVICE_GRE    0xCU
 
 /* Read/Write Allocation Configurations for Cacheable Memory */
 #define R_NON_W_NON     0x0 /* Do not allocate Read/Write */
@@ -113,36 +113,30 @@
 #define R_ALLOC_W_ALLOC 0x3 /* Allocate Read/Write */
 
 /* Memory Attributes for Normal Memory */
-#define NORMAL_O_WT_NT  0x80 /* Normal, Outer Write-through non-transient */
-#define NORMAL_O_WB_NT  0xC0 /* Normal, Outer Write-back non-transient */
-#define NORMAL_O_NON_C  0x40 /* Normal, Outer Non-Cacheable  */
+#define NORMAL_O_WT_NT 0x80 /* Normal, Outer Write-through non-transient */
+#define NORMAL_O_WB_NT 0xC0 /* Normal, Outer Write-back non-transient */
+#define NORMAL_O_NON_C 0x40 /* Normal, Outer Non-Cacheable  */
 
-#define NORMAL_I_WT_NT  0x08 /* Normal, Inner Write-through non-transient */
-#define NORMAL_I_WB_NT  0x0C /* Normal, Inner Write-back non-transient */
-#define NORMAL_I_NON_C  0x04 /* Normal, Inner Non-Cacheable  */
+#define NORMAL_I_WT_NT 0x08 /* Normal, Inner Write-through non-transient */
+#define NORMAL_I_WB_NT 0x0C /* Normal, Inner Write-back non-transient */
+#define NORMAL_I_NON_C 0x04 /* Normal, Inner Non-Cacheable  */
 
-#define NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS \
-	((NORMAL_O_WT_NT | (R_ALLOC_W_NON << 4)) \
-	 | \
-	 (NORMAL_I_WT_NT | R_ALLOC_W_NON)) \
+#define NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS                                   \
+	((NORMAL_O_WT_NT | (R_ALLOC_W_NON << 4)) | (NORMAL_I_WT_NT | R_ALLOC_W_NON))
 
-#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS \
-	((NORMAL_O_WB_NT | (R_ALLOC_W_ALLOC << 4)) \
-	 | \
-	 (NORMAL_I_WB_NT | R_ALLOC_W_ALLOC))
+#define NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS                                \
+	((NORMAL_O_WB_NT | (R_ALLOC_W_ALLOC << 4)) | (NORMAL_I_WB_NT | R_ALLOC_W_ALLOC))
 
-#define NORMAL_OUTER_INNER_NON_CACHEABLE \
-	((NORMAL_O_NON_C | (R_NON_W_NON << 4)) \
-	 | \
-	 (NORMAL_I_NON_C | R_NON_W_NON))
+#define NORMAL_OUTER_INNER_NON_CACHEABLE                                                           \
+	((NORMAL_O_NON_C | (R_NON_W_NON << 4)) | (NORMAL_I_NON_C | R_NON_W_NON))
 
 /* Common cache-ability configuration for Flash, SRAM regions */
-#define MPU_CACHE_ATTRIBUTES_FLASH \
-	NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS
-#define MPU_CACHE_ATTRIBUTES_SRAM \
+#define MPU_CACHE_ATTRIBUTES_FLASH        NORMAL_OUTER_INNER_WRITE_THROUGH_READ_ALLOCATE_NON_TRANS
+/* clang-format off */
+#define MPU_CACHE_ATTRIBUTES_SRAM                                                                  \
 	NORMAL_OUTER_INNER_WRITE_BACK_WRITE_READ_ALLOCATE_NON_TRANS
-#define MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE \
-	NORMAL_OUTER_INNER_NON_CACHEABLE
+/* clang-format on */
+#define MPU_CACHE_ATTRIBUTES_SRAM_NOCACHE NORMAL_OUTER_INNER_NON_CACHEABLE
 
 /* Global MAIR configurations */
 #define MPU_MAIR_ATTR_FLASH         MPU_CACHE_ATTRIBUTES_FLASH
@@ -158,10 +152,10 @@
  * SRAM no cache-able regions(s): Attribute-2
  * DEVICE no cache-able regions(s): Attribute-3
  */
-#define MPU_MAIR_ATTRS							     \
-	((MPU_MAIR_ATTR_FLASH << (MPU_MAIR_INDEX_FLASH * 8)) |		     \
-	 (MPU_MAIR_ATTR_SRAM << (MPU_MAIR_INDEX_SRAM * 8)) |		     \
-	 (MPU_MAIR_ATTR_SRAM_NOCACHE << (MPU_MAIR_INDEX_SRAM_NOCACHE * 8)) | \
+#define MPU_MAIR_ATTRS                                                                             \
+	((MPU_MAIR_ATTR_FLASH << (MPU_MAIR_INDEX_FLASH * 8)) |                                     \
+	 (MPU_MAIR_ATTR_SRAM << (MPU_MAIR_INDEX_SRAM * 8)) |                                       \
+	 (MPU_MAIR_ATTR_SRAM_NOCACHE << (MPU_MAIR_INDEX_SRAM_NOCACHE * 8)) |                       \
 	 (MPU_MAIR_ATTR_DEVICE << (MPU_MAIR_INDEX_DEVICE * 8)))
 
 /* Some helper defines for common regions.
@@ -175,133 +169,140 @@
  */
 #if defined(CONFIG_AARCH32_ARMV8_R)
 
-#define ARM_MPU_REGION_INIT(p_name, p_base, p_size, p_attr)	\
-	{ .name = p_name,					\
-	  .base = p_base,					\
-	  .attr = p_attr(p_base + p_size),			\
+#define ARM_MPU_REGION_INIT(p_name, p_base, p_size, p_attr)                                        \
+	{                                                                                          \
+		.name = p_name,                                                                    \
+		.base = p_base,                                                                    \
+		.attr = p_attr(p_base + p_size),                                                   \
 	}
 
-#define REGION_RAM_ATTR(limit)						    \
-	{								    \
-		.rbar = NOT_EXEC |					    \
-			P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
-		/* Cache-ability */					    \
-		.mair_idx = MPU_MAIR_INDEX_SRAM,			    \
-		.r_limit = limit - 1,  /* Region Limit */		    \
+#define REGION_RAM_ATTR(limit)                                                                     \
+	{                                                                                          \
+		.rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */             \
+		.mair_idx = MPU_MAIR_INDEX_SRAM,                      /* Cache-ability */          \
+		.r_limit = limit - 1,                                 /* Region Limit */           \
 	}
 
-#define REGION_RAM_TEXT_ATTR(limit)					    \
-	{								    \
-		.rbar = P_RO_U_RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
-		/* Cache-ability */					    \
-		.mair_idx = MPU_MAIR_INDEX_SRAM,			    \
-		.r_limit = limit - 1,  /* Region Limit */		    \
+#define REGION_RAM_TEXT_ATTR(limit)                                                                \
+	{                                                                                          \
+		.rbar = P_RO_U_RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */                        \
+		.mair_idx = MPU_MAIR_INDEX_SRAM,           /* Cache-ability */                     \
+		.r_limit = limit - 1,                      /* Region Limit */                      \
 	}
 
-#define REGION_RAM_RO_ATTR(limit)					    \
-	{								    \
-		.rbar = NOT_EXEC |					    \
-			P_RO_U_RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
-		/* Cache-ability */					    \
-		.mair_idx = MPU_MAIR_INDEX_SRAM,			    \
-		.r_limit = limit - 1,  /* Region Limit */		    \
+#define REGION_RAM_RO_ATTR(limit)                                                                  \
+	{                                                                                          \
+		.rbar = NOT_EXEC | P_RO_U_RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */             \
+		.mair_idx = MPU_MAIR_INDEX_SRAM,                      /* Cache-ability */          \
+		.r_limit = limit - 1,                                 /* Region Limit */           \
 	}
-#define REGION_RAM_NOCACHE_ATTR(limit)					    \
-	{								    \
-		.rbar = NOT_EXEC |					    \
-			P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
-		/* Cache-ability */					    \
-		.mair_idx = MPU_MAIR_INDEX_SRAM_NOCACHE,		    \
-		.r_limit = limit - 1,  /* Region Limit */		    \
+#define REGION_RAM_NOCACHE_ATTR(limit)                                                             \
+	{                                                                                          \
+		.rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */             \
+		.mair_idx = MPU_MAIR_INDEX_SRAM_NOCACHE,              /* Cache-ability */          \
+		.r_limit = limit - 1,                                 /* Region Limit */           \
 	}
 #if defined(CONFIG_MPU_ALLOW_FLASH_WRITE)
 /* Note that the access permissions allow for un-privileged writes, contrary
  * to ARMv7-M where un-privileged code has Read-Only permissions.
  */
-#define REGION_FLASH_ATTR(limit)					    \
-	{								    \
-		.rbar = P_RW_U_RW_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
-		/* Cache-ability */					    \
-		.mair_idx = MPU_MAIR_INDEX_FLASH,			    \
-		.r_limit = limit - 1,  /* Region Limit */		    \
+#define REGION_FLASH_ATTR(limit)                                                                   \
+	{                                                                                          \
+		.rbar = P_RW_U_RW_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */                        \
+		.mair_idx = MPU_MAIR_INDEX_FLASH,          /* Cache-ability */                     \
+		.r_limit = limit - 1,                      /* Region Limit */                      \
 	}
 #else /* CONFIG_MPU_ALLOW_FLASH_WRITE */
-#define REGION_FLASH_ATTR(limit)				     \
-	{							     \
-		.rbar = RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
-		/* Cache-ability */				     \
-		.mair_idx = MPU_MAIR_INDEX_FLASH,		     \
-		.r_limit = limit - 1,  /* Region Limit */	     \
+#define REGION_FLASH_ATTR(limit)                                                                   \
+	{                                                                                          \
+		.rbar = RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */                               \
+		.mair_idx = MPU_MAIR_INDEX_FLASH,   /* Cache-ability */                            \
+		.r_limit = limit - 1,               /* Region Limit */                             \
 	}
 #endif /* CONFIG_MPU_ALLOW_FLASH_WRITE */
 
-#define REGION_DEVICE_ATTR(limit)				      \
-	{							      \
-		/* AP, XN, SH */				      \
-		.rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, \
-		/* Cache-ability */				      \
-		.mair_idx = MPU_MAIR_INDEX_DEVICE,		      \
-		/* Region Limit */				      \
-		.r_limit = limit - 1,				      \
+#define REGION_DEVICE_ATTR(limit)                                                                  \
+	{                                                                                          \
+		.rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */             \
+		.mair_idx = MPU_MAIR_INDEX_DEVICE,                    /* Cache-ability */          \
+		.r_limit = limit - 1,                                 /* Region Limit */           \
 	}
 #else
 
-#define ARM_MPU_REGION_INIT(p_name, p_base, p_size, p_attr)	\
-	{ .name = p_name,					\
-	  .base = p_base,					\
-	  .attr = p_attr(p_base, p_size),			\
+#define ARM_MPU_REGION_INIT(p_name, p_base, p_size, p_attr)                                        \
+	{                                                                                          \
+		.name = p_name,                                                                    \
+		.base = p_base,                                                                    \
+		.attr = p_attr(p_base, p_size),                                                    \
 	}
 
 /* On Cortex-M, we can only set the XN bit when CONFIG_XIP=y. When
  * CONFIG_XIP=n, the entire image will be linked to SRAM, so we need to keep
  * the SRAM region XN bit clear or the application code will not be executable.
  */
-#define REGION_RAM_ATTR(base, size) \
-	{\
-		.rbar = IF_ENABLED(CONFIG_XIP, (NOT_EXEC |)) \
-			P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
-		/* Cache-ability */ \
-		.mair_idx = MPU_MAIR_INDEX_SRAM, \
-		.r_limit = REGION_LIMIT_ADDR(base, size),  /* Region Limit */ \
+/* clang-format off */
+#define REGION_RAM_ATTR(base, size)                                                                \
+	{                                                                                          \
+		.rbar = IF_ENABLED(CONFIG_XIP, (NOT_EXEC |)) P_RW_U_NA_Msk |                       \
+			NON_SHAREABLE_Msk,                /* AP, XN, SH */                         \
+		.mair_idx = MPU_MAIR_INDEX_SRAM,          /* Cache-ability */                      \
+		.r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */                       \
+		IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = !PRIV_EXEC_NEVER,))			   \
+	}
+
+#if defined(CONFIG_ARM_MPU_PXN)
+/* Use this attr to define an MPU region in RAM that has code intended to be executed in
+ * un-privileged mode but not in privileged mode.
+ */
+#define REGION_RAM_ATTR_PXN(base, size)                                                            \
+	{                                                                                          \
+		.rbar = P_RO_U_RO_Msk | NON_SHAREABLE_Msk,/* AP, XN, SH */			   \
+		.mair_idx = MPU_MAIR_INDEX_SRAM,          /* Cache-ability */                      \
+		.r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */                       \
+		.pxn = PRIV_EXEC_NEVER,								   \
 	}
+#endif
 
-#define REGION_RAM_NOCACHE_ATTR(base, size) \
-	{\
-		.rbar = NOT_EXEC | \
-			P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
-		/* Cache-ability */ \
-		.mair_idx = MPU_MAIR_INDEX_SRAM_NOCACHE, \
-		.r_limit = REGION_LIMIT_ADDR(base, size),  /* Region Limit */ \
+#define REGION_RAM_NOCACHE_ATTR(base, size)                                                        \
+	{                                                                                          \
+		.rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */             \
+		.mair_idx = MPU_MAIR_INDEX_SRAM_NOCACHE,              /* Cache-ability */          \
+		.r_limit = REGION_LIMIT_ADDR(base, size),             /* Region Limit */           \
+		IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = PRIV_EXEC_NEVER,))			   \
 	}
 
 #if defined(CONFIG_MPU_ALLOW_FLASH_WRITE)
 /* Note that the access permissions allow for un-privileged writes, contrary
  * to ARMv7-M where un-privileged code has Read-Only permissions.
  */
-#define REGION_FLASH_ATTR(base, size) \
-	{\
-		.rbar = P_RW_U_RW_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
-		/* Cache-ability */ \
-		.mair_idx = MPU_MAIR_INDEX_FLASH, \
-		.r_limit = REGION_LIMIT_ADDR(base, size),  /* Region Limit */ \
+#define REGION_FLASH_ATTR(base, size)                                                              \
+	{                                                                                          \
+		.rbar = P_RW_U_RW_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */                        \
+		.mair_idx = MPU_MAIR_INDEX_FLASH,          /* Cache-ability */                     \
+		.r_limit = REGION_LIMIT_ADDR(base, size),  /* Region Limit */                      \
+		IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = !PRIV_EXEC_NEVER,))			   \
 	}
+
 #else /* CONFIG_MPU_ALLOW_FLASH_WRITE */
-#define REGION_FLASH_ATTR(base, size) \
-	{\
-		.rbar = RO_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */ \
-		/* Cache-ability */ \
-		.mair_idx = MPU_MAIR_INDEX_FLASH, \
-		.r_limit = REGION_LIMIT_ADDR(base, size),  /* Region Limit */ \
+#define REGION_FLASH_ATTR(base, size)                                                              \
+	{                                                                                          \
+		.rbar = RO_Msk | NON_SHAREABLE_Msk,       /* AP, XN, SH */                         \
+		.mair_idx = MPU_MAIR_INDEX_FLASH,         /* Cache-ability */                      \
+		.r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */                       \
+		IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = !PRIV_EXEC_NEVER,))			   \
 	}
+
 #endif /* CONFIG_MPU_ALLOW_FLASH_WRITE */
 
 #define REGION_DEVICE_ATTR(base, size)                                                             \
 	{                                                                                          \
-		/* AP, XN, SH */                                                                   \
-		.rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* Cache-ability */          \
-		.mair_idx = MPU_MAIR_INDEX_DEVICE,                                                 \
-		.r_limit = REGION_LIMIT_ADDR(base, size), /* Region Limit */                       \
+		.rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk, /* AP, XN, SH */             \
+		.mair_idx = MPU_MAIR_INDEX_DEVICE,                    /* Cache-ability */          \
+		.r_limit = REGION_LIMIT_ADDR(base, size),             /* Region Limit */           \
+		IF_ENABLED(CONFIG_ARM_MPU_PXN, (.pxn = PRIV_EXEC_NEVER,))			   \
 	}
+
+/* clang-format on */
 #endif
 
 struct arm_mpu_region_attr {
@@ -311,6 +312,10 @@ struct arm_mpu_region_attr {
 	uint8_t mair_idx: 3;
 	/* Region Limit Address value to be written to the RLAR register. */
 	uint32_t r_limit;
+#ifdef CONFIG_ARM_MPU_PXN
+	/* To prevent execution of MPU region in privileged mode (Privileged Execute Never) */
+	uint8_t pxn;
+#endif
 };
 
 typedef struct arm_mpu_region_attr arm_mpu_region_attr_t;
@@ -319,6 +324,10 @@ typedef struct arm_mpu_region_attr arm_mpu_region_attr_t;
 typedef struct {
 	uint16_t rbar;
 	uint16_t mair_idx;
+#ifdef CONFIG_ARM_MPU_PXN
+	/* To prevent execution of MPU region in privileged mode (Privileged Execute Never) */
+	uint8_t pxn;
+#endif
 } k_mem_partition_attr_t;
 
 /* Kernel macros for memory attribution
@@ -333,20 +342,23 @@ typedef struct {
  */
 
 /* Read-Write access permission attributes */
-#define K_MEM_PARTITION_P_RW_U_RW ((k_mem_partition_attr_t) \
-	{(P_RW_U_RW_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
-#define K_MEM_PARTITION_P_RW_U_NA ((k_mem_partition_attr_t) \
-	{(P_RW_U_NA_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
-#define K_MEM_PARTITION_P_RO_U_RO ((k_mem_partition_attr_t) \
-	{(P_RO_U_RO_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
-#define K_MEM_PARTITION_P_RO_U_NA ((k_mem_partition_attr_t) \
-	{(P_RO_U_NA_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
+#define K_MEM_PARTITION_P_RW_U_RW                                                                  \
+	((k_mem_partition_attr_t){(P_RW_U_RW_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
+#define K_MEM_PARTITION_P_RW_U_NA                                                                  \
+	((k_mem_partition_attr_t){(P_RW_U_NA_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
+#define K_MEM_PARTITION_P_RO_U_RO                                                                  \
+	((k_mem_partition_attr_t){(P_RO_U_RO_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
+#define K_MEM_PARTITION_P_RO_U_NA                                                                  \
+	((k_mem_partition_attr_t){(P_RO_U_NA_Msk | NOT_EXEC), MPU_MAIR_INDEX_SRAM})
 
 /* Execution-allowed attributes */
-#define K_MEM_PARTITION_P_RWX_U_RWX ((k_mem_partition_attr_t) \
-	{(P_RW_U_RW_Msk), MPU_MAIR_INDEX_SRAM})
-#define K_MEM_PARTITION_P_RX_U_RX ((k_mem_partition_attr_t) \
-	{(P_RO_U_RO_Msk), MPU_MAIR_INDEX_SRAM})
+#define K_MEM_PARTITION_P_RWX_U_RWX ((k_mem_partition_attr_t){(P_RW_U_RW_Msk), MPU_MAIR_INDEX_SRAM})
+#define K_MEM_PARTITION_P_RX_U_RX   ((k_mem_partition_attr_t){(P_RO_U_RO_Msk), MPU_MAIR_INDEX_SRAM})
+
+#ifdef CONFIG_ARM_MPU_PXN
+#define K_MEM_PARTITION_P_R_U_RX                                                                   \
+	((k_mem_partition_attr_t){(P_RO_U_RO_Msk), MPU_MAIR_INDEX_SRAM, PRIV_EXEC_NEVER})
+#endif
 
 /*
  * @brief Evaluate Write-ability
@@ -356,18 +368,18 @@ typedef struct {
  * @param attr The k_mem_partition_attr_t object holding the
  *             MPU attributes to be checked against write-ability.
  */
-#define K_MEM_PARTITION_IS_WRITABLE(attr) \
-	({ \
-		int __is_writable__; \
-		switch (attr.rbar & MPU_RBAR_AP_Msk) { \
-		case P_RW_U_RW_Msk: \
-		case P_RW_U_NA_Msk: \
-			__is_writable__ = 1; \
-			break; \
-		default: \
-			__is_writable__ = 0; \
-		} \
-		__is_writable__; \
+#define K_MEM_PARTITION_IS_WRITABLE(attr)                                                          \
+	({                                                                                         \
+		int __is_writable__;                                                               \
+		switch (attr.rbar & MPU_RBAR_AP_Msk) {                                             \
+		case P_RW_U_RW_Msk:                                                                \
+		case P_RW_U_NA_Msk:                                                                \
+			__is_writable__ = 1;                                                       \
+			break;                                                                     \
+		default:                                                                           \
+			__is_writable__ = 0;                                                       \
+		}                                                                                  \
+		__is_writable__;                                                                   \
 	})
 
 /*
@@ -379,36 +391,37 @@ typedef struct {
  *             MPU attributes to be checked against execution
  *             allowance.
  */
-#define K_MEM_PARTITION_IS_EXECUTABLE(attr) \
-	(!((attr.rbar) & (NOT_EXEC)))
+#define K_MEM_PARTITION_IS_EXECUTABLE(attr) (!((attr.rbar) & (NOT_EXEC)))
 
 /* Attributes for no-cache enabling (share-ability is selected by default) */
 
 /* Read-Write access permission attributes */
-#define K_MEM_PARTITION_P_RW_U_RW_NOCACHE ((k_mem_partition_attr_t) \
-	{(P_RW_U_RW_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \
-		MPU_MAIR_INDEX_SRAM_NOCACHE})
-#define K_MEM_PARTITION_P_RW_U_NA_NOCACHE ((k_mem_partition_attr_t) \
-	{(P_RW_U_NA_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \
-		MPU_MAIR_INDEX_SRAM_NOCACHE})
-#define K_MEM_PARTITION_P_RO_U_RO_NOCACHE ((k_mem_partition_attr_t) \
-	{(P_RO_U_RO_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \
-		MPU_MAIR_INDEX_SRAM_NOCACHE})
-#define K_MEM_PARTITION_P_RO_U_NA_NOCACHE ((k_mem_partition_attr_t) \
-	{(P_RO_U_NA_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk), \
-		MPU_MAIR_INDEX_SRAM_NOCACHE})
+#define K_MEM_PARTITION_P_RW_U_RW_NOCACHE                                                          \
+	((k_mem_partition_attr_t){(P_RW_U_RW_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk),                \
+				  MPU_MAIR_INDEX_SRAM_NOCACHE})
+#define K_MEM_PARTITION_P_RW_U_NA_NOCACHE                                                          \
+	((k_mem_partition_attr_t){(P_RW_U_NA_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk),                \
+				  MPU_MAIR_INDEX_SRAM_NOCACHE})
+#define K_MEM_PARTITION_P_RO_U_RO_NOCACHE                                                          \
+	((k_mem_partition_attr_t){(P_RO_U_RO_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk),                \
+				  MPU_MAIR_INDEX_SRAM_NOCACHE})
+#define K_MEM_PARTITION_P_RO_U_NA_NOCACHE                                                          \
+	((k_mem_partition_attr_t){(P_RO_U_NA_Msk | NOT_EXEC | OUTER_SHAREABLE_Msk),                \
+				  MPU_MAIR_INDEX_SRAM_NOCACHE})
 
 /* Execution-allowed attributes */
-#define K_MEM_PARTITION_P_RWX_U_RWX_NOCACHE ((k_mem_partition_attr_t) \
-	{(P_RW_U_RW_Msk | OUTER_SHAREABLE_Msk), MPU_MAIR_INDEX_SRAM_NOCACHE})
-#define K_MEM_PARTITION_P_RX_U_RX_NOCACHE ((k_mem_partition_attr_t) \
-	{(P_RO_U_RO_Msk | OUTER_SHAREABLE_Msk), MPU_MAIR_INDEX_SRAM_NOCACHE})
+#define K_MEM_PARTITION_P_RWX_U_RWX_NOCACHE                                                        \
+	((k_mem_partition_attr_t){(P_RW_U_RW_Msk | OUTER_SHAREABLE_Msk),                           \
+				  MPU_MAIR_INDEX_SRAM_NOCACHE})
+#define K_MEM_PARTITION_P_RX_U_RX_NOCACHE                                                          \
+	((k_mem_partition_attr_t){(P_RO_U_RO_Msk | OUTER_SHAREABLE_Msk),                           \
+				  MPU_MAIR_INDEX_SRAM_NOCACHE})
 
 #endif /* _ASMLANGUAGE */
 
-#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
-	BUILD_ASSERT((size > 0) && ((uint32_t)start % \
-			CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0U) && \
-		((size) % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0), \
-		" the start and size of the partition must align " \
-		"with the minimum MPU region size.")
+#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size)                                               \
+	BUILD_ASSERT((size > 0) &&                                                                 \
+			     ((uint32_t)start % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0U) && \
+			     ((size) % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0),             \
+		     "The start and size of the partition must align with the minimum MPU "        \
+		     "region size.")
diff --git a/include/zephyr/arch/arm/mpu/nxp_mpu.h b/include/zephyr/arch/arm/mpu/nxp_mpu.h
index b9556565802..b1bc9c2e451 100644
--- a/include/zephyr/arch/arm/mpu/nxp_mpu.h
+++ b/include/zephyr/arch/arm/mpu/nxp_mpu.h
@@ -11,119 +11,102 @@
 #define NXP_MPU_REGION_NUMBER 12
 
 /* Bus Master User Mode Access */
-#define UM_READ		4
-#define UM_WRITE	2
-#define UM_EXEC		1
+#define UM_READ  4
+#define UM_WRITE 2
+#define UM_EXEC  1
 
-#define BM0_UM_SHIFT	0
-#define BM1_UM_SHIFT	6
-#define BM2_UM_SHIFT	12
-#define BM3_UM_SHIFT	18
+#define BM0_UM_SHIFT 0
+#define BM1_UM_SHIFT 6
+#define BM2_UM_SHIFT 12
+#define BM3_UM_SHIFT 18
 
 /* Bus Master Supervisor Mode Access */
-#define SM_RWX_ALLOW	0
-#define SM_RX_ALLOW	1
-#define SM_RW_ALLOW	2
-#define SM_SAME_AS_UM	3
+#define SM_RWX_ALLOW  0
+#define SM_RX_ALLOW   1
+#define SM_RW_ALLOW   2
+#define SM_SAME_AS_UM 3
 
-#define BM0_SM_SHIFT	3
-#define BM1_SM_SHIFT	9
-#define BM2_SM_SHIFT	15
-#define BM3_SM_SHIFT	21
+#define BM0_SM_SHIFT 3
+#define BM1_SM_SHIFT 9
+#define BM2_SM_SHIFT 15
+#define BM3_SM_SHIFT 21
 
-#define BM4_WE_SHIFT	24
-#define BM4_RE_SHIFT	25
+#define BM4_WE_SHIFT 24
+#define BM4_RE_SHIFT 25
 
 #if CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS
-#define BM4_PERMISSIONS	((1 << BM4_RE_SHIFT) | (1 << BM4_WE_SHIFT))
+#define BM4_PERMISSIONS ((1 << BM4_RE_SHIFT) | (1 << BM4_WE_SHIFT))
 #else
-#define BM4_PERMISSIONS	0
+#define BM4_PERMISSIONS 0
 #endif
 
 /* Read Attribute */
-#define MPU_REGION_READ  ((UM_READ << BM0_UM_SHIFT) | \
-			  (UM_READ << BM1_UM_SHIFT) | \
-			  (UM_READ << BM2_UM_SHIFT) | \
-			  (UM_READ << BM3_UM_SHIFT))
+#define MPU_REGION_READ                                                                            \
+	((UM_READ << BM0_UM_SHIFT) | (UM_READ << BM1_UM_SHIFT) | (UM_READ << BM2_UM_SHIFT) |       \
+	 (UM_READ << BM3_UM_SHIFT))
 
 /* Write Attribute */
-#define MPU_REGION_WRITE ((UM_WRITE << BM0_UM_SHIFT) | \
-			  (UM_WRITE << BM1_UM_SHIFT) | \
-			  (UM_WRITE << BM2_UM_SHIFT) | \
-			  (UM_WRITE << BM3_UM_SHIFT))
+#define MPU_REGION_WRITE                                                                           \
+	((UM_WRITE << BM0_UM_SHIFT) | (UM_WRITE << BM1_UM_SHIFT) | (UM_WRITE << BM2_UM_SHIFT) |    \
+	 (UM_WRITE << BM3_UM_SHIFT))
 
 /* Execute Attribute */
-#define MPU_REGION_EXEC  ((UM_EXEC << BM0_UM_SHIFT) | \
-			  (UM_EXEC << BM1_UM_SHIFT) | \
-			  (UM_EXEC << BM2_UM_SHIFT) | \
-			  (UM_EXEC << BM3_UM_SHIFT))
+#define MPU_REGION_EXEC                                                                            \
+	((UM_EXEC << BM0_UM_SHIFT) | (UM_EXEC << BM1_UM_SHIFT) | (UM_EXEC << BM2_UM_SHIFT) |       \
+	 (UM_EXEC << BM3_UM_SHIFT))
 
 /* Super User Attributes */
-#define MPU_REGION_SU	 ((SM_SAME_AS_UM << BM0_SM_SHIFT) | \
-			  (SM_SAME_AS_UM << BM1_SM_SHIFT) | \
-			  (SM_SAME_AS_UM << BM2_SM_SHIFT) | \
-			  (SM_SAME_AS_UM << BM3_SM_SHIFT))
-
-#define MPU_REGION_SU_RX ((SM_RX_ALLOW << BM0_SM_SHIFT) | \
-			  (SM_RX_ALLOW << BM1_SM_SHIFT) | \
-			  (SM_RX_ALLOW << BM2_SM_SHIFT) | \
-			  (SM_RX_ALLOW << BM3_SM_SHIFT))
-
-#define MPU_REGION_SU_RW ((SM_RW_ALLOW << BM0_SM_SHIFT) | \
-			  (SM_RW_ALLOW << BM1_SM_SHIFT) | \
-			  (SM_RW_ALLOW << BM2_SM_SHIFT) | \
-			  (SM_RW_ALLOW << BM3_SM_SHIFT))
-
-#define MPU_REGION_SU_RWX ((SM_RWX_ALLOW << BM0_SM_SHIFT) | \
-			   (SM_RWX_ALLOW << BM1_SM_SHIFT) | \
-			   (SM_RWX_ALLOW << BM2_SM_SHIFT) | \
-			   (SM_RWX_ALLOW << BM3_SM_SHIFT))
+#define MPU_REGION_SU                                                                              \
+	((SM_SAME_AS_UM << BM0_SM_SHIFT) | (SM_SAME_AS_UM << BM1_SM_SHIFT) |                       \
+	 (SM_SAME_AS_UM << BM2_SM_SHIFT) | (SM_SAME_AS_UM << BM3_SM_SHIFT))
+
+#define MPU_REGION_SU_RX                                                                           \
+	((SM_RX_ALLOW << BM0_SM_SHIFT) | (SM_RX_ALLOW << BM1_SM_SHIFT) |                           \
+	 (SM_RX_ALLOW << BM2_SM_SHIFT) | (SM_RX_ALLOW << BM3_SM_SHIFT))
+
+#define MPU_REGION_SU_RW                                                                           \
+	((SM_RW_ALLOW << BM0_SM_SHIFT) | (SM_RW_ALLOW << BM1_SM_SHIFT) |                           \
+	 (SM_RW_ALLOW << BM2_SM_SHIFT) | (SM_RW_ALLOW << BM3_SM_SHIFT))
+
+#define MPU_REGION_SU_RWX                                                                          \
+	((SM_RWX_ALLOW << BM0_SM_SHIFT) | (SM_RWX_ALLOW << BM1_SM_SHIFT) |                         \
+	 (SM_RWX_ALLOW << BM2_SM_SHIFT) | (SM_RWX_ALLOW << BM3_SM_SHIFT))
 
 /* The ENDADDR field has the last 5 bit reserved and set to 1 */
 #define ENDADDR_ROUND(x) (x - 0x1F)
 
-#define REGION_USER_MODE_ATTR {(MPU_REGION_READ | \
-				MPU_REGION_WRITE | \
-				MPU_REGION_SU)}
+#define REGION_USER_MODE_ATTR {(MPU_REGION_READ | MPU_REGION_WRITE | MPU_REGION_SU)}
 
 /* Some helper defines for common regions */
 #if defined(CONFIG_MPU_ALLOW_FLASH_WRITE)
-#define REGION_RAM_ATTR	  {((MPU_REGION_SU_RWX) | \
-			   ((UM_READ | UM_WRITE | UM_EXEC) << BM3_UM_SHIFT) | \
-			   (BM4_PERMISSIONS))}
+#define REGION_RAM_ATTR                                                                            \
+	{((MPU_REGION_SU_RWX) | ((UM_READ | UM_WRITE | UM_EXEC) << BM3_UM_SHIFT) |                 \
+	  (BM4_PERMISSIONS))}
 
 #define REGION_FLASH_ATTR {(MPU_REGION_SU_RWX)}
 
 #else
-#define REGION_RAM_ATTR	  {((MPU_REGION_SU_RW) | \
-			   ((UM_READ | UM_WRITE) << BM3_UM_SHIFT) | \
-			   (BM4_PERMISSIONS))}
+#define REGION_RAM_ATTR                                                                            \
+	{((MPU_REGION_SU_RW) | ((UM_READ | UM_WRITE) << BM3_UM_SHIFT) | (BM4_PERMISSIONS))}
 
-#define REGION_FLASH_ATTR {(MPU_REGION_READ | \
-			   MPU_REGION_EXEC | \
-			   MPU_REGION_SU)}
+#define REGION_FLASH_ATTR {(MPU_REGION_READ | MPU_REGION_EXEC | MPU_REGION_SU)}
 #endif
 
-#define REGION_IO_ATTR	  {(MPU_REGION_READ | \
-			   MPU_REGION_WRITE | \
-			   MPU_REGION_EXEC | \
-			   MPU_REGION_SU)}
+#define REGION_IO_ATTR {(MPU_REGION_READ | MPU_REGION_WRITE | MPU_REGION_EXEC | MPU_REGION_SU)}
 
-#define REGION_RO_ATTR	  {(MPU_REGION_READ | MPU_REGION_SU)}
+#define REGION_RO_ATTR {(MPU_REGION_READ | MPU_REGION_SU)}
 
-#define REGION_USER_RO_ATTR {(MPU_REGION_READ | \
-			     MPU_REGION_SU)}
+#define REGION_USER_RO_ATTR {(MPU_REGION_READ | MPU_REGION_SU)}
 
 /* ENET (Master 3) and USB (Master 4) devices will not be able
 to access RAM when the region is dynamically disabled in NXP MPU.
 DEBUGGER (Master 1) can't be disabled in Region 0. */
-#define REGION_DEBUGGER_AND_DEVICE_ATTR  {((MPU_REGION_SU) | \
-				((UM_READ | UM_WRITE) << BM3_UM_SHIFT) | \
-				(BM4_PERMISSIONS))}
+#define REGION_DEBUGGER_AND_DEVICE_ATTR                                                            \
+	{((MPU_REGION_SU) | ((UM_READ | UM_WRITE) << BM3_UM_SHIFT) | (BM4_PERMISSIONS))}
 
-#define REGION_DEBUG_ATTR  {MPU_REGION_SU}
+#define REGION_DEBUG_ATTR {MPU_REGION_SU}
 
-#define REGION_BACKGROUND_ATTR	{MPU_REGION_SU_RW}
+#define REGION_BACKGROUND_ATTR {MPU_REGION_SU_RW}
 
 struct nxp_mpu_region_attr {
 	/* NXP MPU region access permission attributes */
@@ -145,27 +128,22 @@ typedef struct {
  */
 
 /* Read-Write access permission attributes */
-#define K_MEM_PARTITION_P_NA_U_NA	((k_mem_partition_attr_t) \
-	{(MPU_REGION_SU)})
-#define K_MEM_PARTITION_P_RW_U_RW	((k_mem_partition_attr_t) \
-	{(MPU_REGION_READ | MPU_REGION_WRITE | MPU_REGION_SU)})
-#define K_MEM_PARTITION_P_RW_U_RO	((k_mem_partition_attr_t) \
-	{(MPU_REGION_READ | MPU_REGION_SU_RW)})
-#define K_MEM_PARTITION_P_RW_U_NA	((k_mem_partition_attr_t) \
-	{(MPU_REGION_SU_RW)})
-#define K_MEM_PARTITION_P_RO_U_RO	((k_mem_partition_attr_t) \
-	{(MPU_REGION_READ | MPU_REGION_SU)})
-#define K_MEM_PARTITION_P_RO_U_NA	((k_mem_partition_attr_t) \
-	{(MPU_REGION_SU_RX)})
+#define K_MEM_PARTITION_P_NA_U_NA ((k_mem_partition_attr_t){(MPU_REGION_SU)})
+#define K_MEM_PARTITION_P_RW_U_RW                                                                  \
+	((k_mem_partition_attr_t){(MPU_REGION_READ | MPU_REGION_WRITE | MPU_REGION_SU)})
+#define K_MEM_PARTITION_P_RW_U_RO ((k_mem_partition_attr_t){(MPU_REGION_READ | MPU_REGION_SU_RW)})
+#define K_MEM_PARTITION_P_RW_U_NA ((k_mem_partition_attr_t){(MPU_REGION_SU_RW)})
+#define K_MEM_PARTITION_P_RO_U_RO ((k_mem_partition_attr_t){(MPU_REGION_READ | MPU_REGION_SU)})
+#define K_MEM_PARTITION_P_RO_U_NA ((k_mem_partition_attr_t){(MPU_REGION_SU_RX)})
 
 /* Execution-allowed attributes */
-#define K_MEM_PARTITION_P_RWX_U_RWX	((k_mem_partition_attr_t) \
-	{(MPU_REGION_READ | MPU_REGION_WRITE | \
-	  MPU_REGION_EXEC | MPU_REGION_SU)})
-#define K_MEM_PARTITION_P_RWX_U_RX	((k_mem_partition_attr_t) \
-	{(MPU_REGION_READ | MPU_REGION_EXEC | MPU_REGION_SU_RWX)})
-#define K_MEM_PARTITION_P_RX_U_RX	((k_mem_partition_attr_t) \
-	{(MPU_REGION_READ | MPU_REGION_EXEC | MPU_REGION_SU)})
+#define K_MEM_PARTITION_P_RWX_U_RWX                                                                \
+	((k_mem_partition_attr_t){                                                                 \
+		(MPU_REGION_READ | MPU_REGION_WRITE | MPU_REGION_EXEC | MPU_REGION_SU)})
+#define K_MEM_PARTITION_P_RWX_U_RX                                                                 \
+	((k_mem_partition_attr_t){(MPU_REGION_READ | MPU_REGION_EXEC | MPU_REGION_SU_RWX)})
+#define K_MEM_PARTITION_P_RX_U_RX                                                                  \
+	((k_mem_partition_attr_t){(MPU_REGION_READ | MPU_REGION_EXEC | MPU_REGION_SU)})
 
 /*
  * @brief Evaluate Write-ability
@@ -175,18 +153,18 @@ typedef struct {
  * @param attr The k_mem_partition_attr_t object holding the
  *             MPU attributes to be checked against write-ability.
  */
-#define K_MEM_PARTITION_IS_WRITABLE(attr) \
-	({ \
-		int __is_writable__; \
-		switch (attr.ap_attr) { \
-		case MPU_REGION_WRITE: \
-		case MPU_REGION_SU_RW: \
-			__is_writable__ = 1; \
-			break; \
-		default: \
-			__is_writable__ = 0; \
-		} \
-		__is_writable__; \
+#define K_MEM_PARTITION_IS_WRITABLE(attr)                                                          \
+	({                                                                                         \
+		int __is_writable__;                                                               \
+		switch (attr.ap_attr) {                                                            \
+		case MPU_REGION_WRITE:                                                             \
+		case MPU_REGION_SU_RW:                                                             \
+			__is_writable__ = 1;                                                       \
+			break;                                                                     \
+		default:                                                                           \
+			__is_writable__ = 0;                                                       \
+		}                                                                                  \
+		__is_writable__;                                                                   \
 	})
 
 /*
@@ -198,21 +176,20 @@ typedef struct {
  *             MPU attributes to be checked against execution
  *             allowance.
  */
-#define K_MEM_PARTITION_IS_EXECUTABLE(attr) \
-	({ \
-		int __is_executable__; \
-		switch (attr.ap_attr) { \
-		case MPU_REGION_SU_RX: \
-		case MPU_REGION_EXEC: \
-			__is_executable__ = 1; \
-			break; \
-		default: \
-			__is_executable__ = 0; \
-		} \
-		__is_executable__; \
+#define K_MEM_PARTITION_IS_EXECUTABLE(attr)                                                        \
+	({                                                                                         \
+		int __is_executable__;                                                             \
+		switch (attr.ap_attr) {                                                            \
+		case MPU_REGION_SU_RX:                                                             \
+		case MPU_REGION_EXEC:                                                              \
+			__is_executable__ = 1;                                                     \
+			break;                                                                     \
+		default:                                                                           \
+			__is_executable__ = 0;                                                     \
+		}                                                                                  \
+		__is_executable__;                                                                 \
 	})
 
-
 /* Region definition data structure */
 struct nxp_mpu_region {
 	/* Region Base Address */
@@ -225,12 +202,12 @@ struct nxp_mpu_region {
 	nxp_mpu_region_attr_t attr;
 };
 
-#define MPU_REGION_ENTRY(_name, _base, _end, _attr) \
-	{\
-		.name = _name, \
-		.base = _base, \
-		.end = _end, \
-		.attr = _attr, \
+#define MPU_REGION_ENTRY(_name, _base, _end, _attr)                                                \
+	{                                                                                          \
+		.name = _name,                                                                     \
+		.base = _base,                                                                     \
+		.end = _end,                                                                       \
+		.attr = _attr,                                                                     \
 	}
 
 /* MPU configuration data structure */
@@ -255,15 +232,13 @@ extern const struct nxp_mpu_config mpu_config;
 
 #endif /* _ASMLANGUAGE */
 
-#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size) \
-	BUILD_ASSERT((size) % \
-		CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0 && \
-		(size) >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE && \
-		(uint32_t)(start) % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0, \
-		"the size of the partition must align with minimum MPU \
-		 region size" \
-		" and greater than or equal to minimum MPU region size." \
-		"start address of the partition must align with minimum MPU \
-		 region size.")
+#define _ARCH_MEM_PARTITION_ALIGN_CHECK(start, size)                                               \
+	BUILD_ASSERT(                                                                              \
+		(size) % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0 &&                          \
+			(size) >= CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE &&                      \
+			(uint32_t)(start) % CONFIG_ARM_MPU_REGION_MIN_ALIGN_AND_SIZE == 0,         \
+		"The size of the partition must align with minimum MPU region size"                \
+		" and greater than or equal to minimum MPU region size.\n"                         \
+		"The start address of the partition must align with minimum MPU region size.")
 
 #endif /* ZEPHYR_INCLUDE_ARCH_ARM_MPU_NXP_MPU_H_ */
diff --git a/include/zephyr/arch/arm/nmi.h b/include/zephyr/arch/arm/nmi.h
index 33f46084248..1f92456fe12 100644
--- a/include/zephyr/arch/arm/nmi.h
+++ b/include/zephyr/arch/arm/nmi.h
@@ -13,8 +13,16 @@
 #ifndef ZEPHYR_INCLUDE_ARCH_ARM_NMI_H_
 #define ZEPHYR_INCLUDE_ARCH_ARM_NMI_H_
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 #if !defined(_ASMLANGUAGE) && defined(CONFIG_RUNTIME_NMI)
 extern void z_arm_nmi_set_handler(void (*pHandler)(void));
 #endif
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* ZEPHYR_INCLUDE_ARCH_ARM_NMI_H_ */
diff --git a/include/zephyr/arch/arm64/timer.h b/include/zephyr/arch/arm64/timer.h
index d8abba1c0e4..0973e327dfc 100644
--- a/include/zephyr/arch/arm64/timer.h
+++ b/include/zephyr/arch/arm64/timer.h
@@ -26,11 +26,11 @@ extern "C" {
 static ALWAYS_INLINE void arm_arch_timer_init(void)
 {
 #ifdef CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
-	extern int z_clock_hw_cycles_per_sec;
+	extern unsigned int z_clock_hw_cycles_per_sec;
 	uint64_t cntfrq_el0 = read_cntfrq_el0();
 
-	__ASSERT(cntfrq_el0 < INT_MAX, "cntfrq_el0 cannot fit in system 'int'");
-	z_clock_hw_cycles_per_sec = (int) cntfrq_el0;
+	__ASSERT(cntfrq_el0 < UINT_MAX, "cntfrq_el0 cannot fit in system 'unsigned int'");
+	z_clock_hw_cycles_per_sec = (unsigned int) cntfrq_el0;
 #endif
 }
 
diff --git a/include/zephyr/arch/common/ffs.h b/include/zephyr/arch/common/ffs.h
index 2660faa2e3f..2fd912cd5e0 100644
--- a/include/zephyr/arch/common/ffs.h
+++ b/include/zephyr/arch/common/ffs.h
@@ -11,6 +11,7 @@
 #ifndef _ASMLANGUAGE
 
 #include <zephyr/types.h>
+#include <zephyr/toolchain/common.h>
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/include/zephyr/arch/mips/exception.h b/include/zephyr/arch/mips/exception.h
index f33af4c4387..352ef887a51 100644
--- a/include/zephyr/arch/mips/exception.h
+++ b/include/zephyr/arch/mips/exception.h
@@ -6,8 +6,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_INCLUDE_ARCH_MIPS_EXPCEPTION_H_
-#define ZEPHYR_INCLUDE_ARCH_MIPS_EXPCEPTION_H_
+#ifndef ZEPHYR_INCLUDE_ARCH_MIPS_EXCEPTION_H_
+#define ZEPHYR_INCLUDE_ARCH_MIPS_EXCEPTION_H_
 
 #ifndef _ASMLANGUAGE
 #include <zephyr/types.h>
@@ -56,4 +56,4 @@ struct arch_esf {
 
 #endif /* _ASMLANGUAGE */
 
-#endif /* ZEPHYR_INCLUDE_ARCH_MIPS_EXPCEPTION_H_ */
+#endif /* ZEPHYR_INCLUDE_ARCH_MIPS_EXCEPTION_H_ */
diff --git a/include/zephyr/arch/nios2/exception.h b/include/zephyr/arch/nios2/exception.h
index 223fa583114..c2c614ae88f 100644
--- a/include/zephyr/arch/nios2/exception.h
+++ b/include/zephyr/arch/nios2/exception.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_INCLUDE_ARCH_NIOS2_EXPCEPTION_H_
-#define ZEPHYR_INCLUDE_ARCH_NIOS2_EXPCEPTION_H_
+#ifndef ZEPHYR_INCLUDE_ARCH_NIOS2_EXCEPTION_H_
+#define ZEPHYR_INCLUDE_ARCH_NIOS2_EXCEPTION_H_
 
 #ifndef _ASMLANGUAGE
 #include <zephyr/types.h>
@@ -41,4 +41,4 @@ struct arch_esf {
 
 #endif /* _ASMLANGUAGE */
 
-#endif /* ZEPHYR_INCLUDE_ARCH_NIOS2_EXPCEPTION_H_ */
+#endif /* ZEPHYR_INCLUDE_ARCH_NIOS2_EXCEPTION_H_ */
diff --git a/include/zephyr/arch/posix/exception.h b/include/zephyr/arch/posix/exception.h
index 6c7962aa057..4387a5547ee 100644
--- a/include/zephyr/arch/posix/exception.h
+++ b/include/zephyr/arch/posix/exception.h
@@ -5,8 +5,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_INCLUDE_ARCH_POSIX_EXPCEPTION_H_
-#define ZEPHYR_INCLUDE_ARCH_POSIX_EXPCEPTION_H_
+#ifndef ZEPHYR_INCLUDE_ARCH_POSIX_EXCEPTION_H_
+#define ZEPHYR_INCLUDE_ARCH_POSIX_EXCEPTION_H_
 
 #ifndef _ASMLANGUAGE
 #include <zephyr/types.h>
@@ -25,4 +25,4 @@ struct arch_esf {
 
 #endif /* _ASMLANGUAGE */
 
-#endif /* ZEPHYR_INCLUDE_ARCH_POSIX_EXPCEPTION_H_ */
+#endif /* ZEPHYR_INCLUDE_ARCH_POSIX_EXCEPTION_H_ */
diff --git a/include/zephyr/arch/riscv/exception.h b/include/zephyr/arch/riscv/exception.h
index 4e46417048c..eb3cabebd41 100644
--- a/include/zephyr/arch/riscv/exception.h
+++ b/include/zephyr/arch/riscv/exception.h
@@ -78,6 +78,10 @@ struct arch_esf {
 	unsigned long a7;		/* function argument */
 #endif /* !CONFIG_RISCV_ISA_RV32E */
 
+#ifdef CONFIG_CLIC_SUPPORT_INTERRUPT_LEVEL
+	unsigned long mcause;		/* machine cause register */
+#endif /* CONFIG_CLIC_SUPPORT_INTERRUPT_LEVEL */
+
 	unsigned long mepc;		/* machine exception program counter */
 	unsigned long mstatus;	/* machine status register */
 
diff --git a/include/zephyr/arch/sparc/exception.h b/include/zephyr/arch/sparc/exception.h
index a2d3fae52e2..9d6181a2947 100644
--- a/include/zephyr/arch/sparc/exception.h
+++ b/include/zephyr/arch/sparc/exception.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_INCLUDE_ARCH_SPARC_EXPCEPTION_H_
-#define ZEPHYR_INCLUDE_ARCH_SPARC_EXPCEPTION_H_
+#ifndef ZEPHYR_INCLUDE_ARCH_SPARC_EXCEPTION_H_
+#define ZEPHYR_INCLUDE_ARCH_SPARC_EXCEPTION_H_
 
 #ifndef _ASMLANGUAGE
 #include <zephyr/types.h>
@@ -31,4 +31,4 @@ struct arch_esf {
 
 #endif /* _ASMLANGUAGE */
 
-#endif /* ZEPHYR_INCLUDE_ARCH_SPARC_EXPCEPTION_H_ */
+#endif /* ZEPHYR_INCLUDE_ARCH_SPARC_EXCEPTION_H_ */
diff --git a/include/zephyr/arch/structs.h b/include/zephyr/arch/structs.h
index 703ec81f889..dcd4406c1d8 100644
--- a/include/zephyr/arch/structs.h
+++ b/include/zephyr/arch/structs.h
@@ -29,6 +29,8 @@
 #include <zephyr/arch/riscv/structs.h>
 #elif defined(CONFIG_ARM)
 #include <zephyr/arch/arm/structs.h>
+#elif defined(CONFIG_X86) && !defined(CONFIG_X86_64)
+#include <zephyr/arch/x86/ia32/structs.h>
 #else
 
 /* Default definitions when no architecture specific definitions exist. */
diff --git a/include/zephyr/arch/x86/ia32/exception.h b/include/zephyr/arch/x86/ia32/exception.h
index de618f4e01d..d1acafb3fd3 100644
--- a/include/zephyr/arch/x86/ia32/exception.h
+++ b/include/zephyr/arch/x86/ia32/exception.h
@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_INCLUDE_ARCH_X86_IA32_EXPCEPTION_H_
-#define ZEPHYR_INCLUDE_ARCH_X86_IA32_EXPCEPTION_H_
+#ifndef ZEPHYR_INCLUDE_ARCH_X86_IA32_EXCEPTION_H_
+#define ZEPHYR_INCLUDE_ARCH_X86_IA32_EXCEPTION_H_
 
 #ifndef _ASMLANGUAGE
 #include <zephyr/types.h>
@@ -67,4 +67,4 @@ struct _x86_syscall_stack_frame {
 
 #endif /* _ASMLANGUAGE */
 
-#endif /* ZEPHYR_INCLUDE_ARCH_X86_IA32_EXPCEPTION_H_ */
+#endif /* ZEPHYR_INCLUDE_ARCH_X86_IA32_EXCEPTION_H_ */
diff --git a/include/zephyr/arch/x86/ia32/structs.h b/include/zephyr/arch/x86/ia32/structs.h
new file mode 100644
index 00000000000..91112a8578c
--- /dev/null
+++ b/include/zephyr/arch/x86/ia32/structs.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2025 Intel
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_X86_STRUCTS_H_
+#define ZEPHYR_INCLUDE_X86_STRUCTS_H_
+
+#include <stdint.h>
+
+struct k_thread;
+
+/* Per CPU architecture specifics (empty) */
+struct _cpu_arch {
+
+#if defined(CONFIG_FPU_SHARING)
+	/*
+	 * A 'sse_owner' field does not exist in addition to the 'fpu_owner'
+	 * field since it's not possible to divide the IA-32 non-integer
+	 * registers into 2 distinct blocks owned by differing threads.  In
+	 * other words, given that the 'fxnsave/fxrstor' instructions
+	 * save/restore both the X87 FPU and XMM registers, it's not possible
+	 * for a thread to only "own" the XMM registers.
+	 */
+
+	struct k_thread *fpu_owner;
+#elif defined(__cplusplus)
+	/* Ensure this struct does not have a size of 0 which is not allowed in C++. */
+	uint8_t dummy;
+#endif
+};
+
+#endif /* ZEPHYR_INCLUDE_X86_STRUCTS_H_ */
diff --git a/include/zephyr/arch/x86/intel64/exception.h b/include/zephyr/arch/x86/intel64/exception.h
index 55c7cc2b4ee..7a78950334e 100644
--- a/include/zephyr/arch/x86/intel64/exception.h
+++ b/include/zephyr/arch/x86/intel64/exception.h
@@ -3,8 +3,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef ZEPHYR_INCLUDE_ARCH_X86_INTEL64_EXPCEPTION_H_
-#define ZEPHYR_INCLUDE_ARCH_X86_INTEL64_EXPCEPTION_H_
+#ifndef ZEPHYR_INCLUDE_ARCH_X86_INTEL64_EXCEPTION_H_
+#define ZEPHYR_INCLUDE_ARCH_X86_INTEL64_EXCEPTION_H_
 
 #ifndef _ASMLANGUAGE
 #include <zephyr/arch/x86/intel64/thread.h>
@@ -72,4 +72,4 @@ struct x86_ssf {
 
 #endif /* _ASMLANGUAGE */
 
-#endif /* ZEPHYR_INCLUDE_ARCH_X86_INTEL64_EXPCEPTION_H_ */
+#endif /* ZEPHYR_INCLUDE_ARCH_X86_INTEL64_EXCEPTION_H_ */
diff --git a/include/zephyr/arch/x86/thread_stack.h b/include/zephyr/arch/x86/thread_stack.h
index f22bf4d6853..fb5572055da 100644
--- a/include/zephyr/arch/x86/thread_stack.h
+++ b/include/zephyr/arch/x86/thread_stack.h
@@ -107,7 +107,6 @@ struct z_x86_thread_stack_header {
 #define ARCH_KERNEL_STACK_RESERVED	CONFIG_MMU_PAGE_SIZE
 #define ARCH_KERNEL_STACK_OBJ_ALIGN	CONFIG_MMU_PAGE_SIZE
 #else
-#define ARCH_KERNEL_STACK_RESERVED	0
 #define ARCH_KERNEL_STACK_OBJ_ALIGN	ARCH_STACK_PTR_ALIGN
 #endif
 
diff --git a/include/zephyr/arch/xtensa/arch.h b/include/zephyr/arch/xtensa/arch.h
index 794bd1b5d70..6255249f8e7 100644
--- a/include/zephyr/arch/xtensa/arch.h
+++ b/include/zephyr/arch/xtensa/arch.h
@@ -66,6 +66,14 @@ struct arch_mem_domain {
 	uint32_t *ptables;
 	uint8_t asid;
 	bool dirty;
+
+	/* Following are used to program registers when changing page tables. */
+	uint32_t reg_asid;
+	uint32_t reg_ptevaddr;
+	uint32_t reg_ptepin_as;
+	uint32_t reg_ptepin_at;
+	uint32_t reg_vecpin_as;
+	uint32_t reg_vecpin_at;
 #endif
 #ifdef CONFIG_XTENSA_MPU
 	struct xtensa_mpu_map mpu_map;
@@ -73,6 +81,8 @@ struct arch_mem_domain {
 	sys_snode_t node;
 };
 
+typedef struct arch_mem_domain arch_mem_domain_t;
+
 /**
  * @brief Generate hardware exception.
  *
diff --git a/include/zephyr/arch/xtensa/syscall.h b/include/zephyr/arch/xtensa/syscall.h
index 9fdbe2b0977..34f49437e2a 100644
--- a/include/zephyr/arch/xtensa/syscall.h
+++ b/include/zephyr/arch/xtensa/syscall.h
@@ -30,6 +30,26 @@
 extern "C" {
 #endif
 
+/* When syscall assembly is executed, the EPC points to the syscall
+ * instruction, and we have to manually advance it so we will
+ * return to the instruction after syscall to continue execution.
+ * However, with zero-overhead loops and the syscall instruction is
+ * the last instruction, this simple addition does not work as it
+ * would point past the loop and would have skipped the loop.
+ * Because of this, syscall entrance would need to look at the loop
+ * registers and set the PC back to the beginning of loop if we are
+ * still looping. Assuming most of the syscalls are not inside
+ * loops, the extra handling code consumes quite a few cycles.
+ * To workaround this, simply adds a nop after syscall so we no
+ * longer have to deal with loops at syscall entrance, and that
+ * a nop is faster than all the code to manipulate loop registers.
+ */
+#ifdef XCHAL_HAVE_LOOPS
+#define XTENSA_SYSCALL_ASM		"syscall; nop;"
+#else
+#define XTENSA_SYSCALL_ASM		"syscall"
+#endif
+
 #ifdef CONFIG_XTENSA_SYSCALL_USE_HELPER
 uintptr_t xtensa_syscall_helper_args_6(uintptr_t arg1, uintptr_t arg2,
 				       uintptr_t arg3, uintptr_t arg4,
@@ -75,7 +95,7 @@ static SYSINL uintptr_t arch_syscall_invoke6(uintptr_t arg1, uintptr_t arg2,
 	register uintptr_t a8 __asm__("%a8") = arg5;
 	register uintptr_t a9 __asm__("%a9") = arg6;
 
-	__asm__ volatile("syscall\n\t"
+	__asm__ volatile(XTENSA_SYSCALL_ASM
 			 : "=r" (a2)
 			 : "r" (a2), "r" (a6), "r" (a3), "r" (a4),
 			   "r" (a5), "r" (a8), "r" (a9)
@@ -99,7 +119,7 @@ static SYSINL uintptr_t arch_syscall_invoke5(uintptr_t arg1, uintptr_t arg2,
 	register uintptr_t a5 __asm__("%a5") = arg4;
 	register uintptr_t a8 __asm__("%a8") = arg5;
 
-	__asm__ volatile("syscall\n\t"
+	__asm__ volatile(XTENSA_SYSCALL_ASM
 			 : "=r" (a2)
 			 : "r" (a2), "r" (a6), "r" (a3), "r" (a4),
 			   "r" (a5), "r" (a8)
@@ -122,7 +142,7 @@ static SYSINL uintptr_t arch_syscall_invoke4(uintptr_t arg1, uintptr_t arg2,
 	register uintptr_t a4 __asm__("%a4") = arg3;
 	register uintptr_t a5 __asm__("%a5") = arg4;
 
-	__asm__ volatile("syscall\n\t"
+	__asm__ volatile(XTENSA_SYSCALL_ASM
 			 : "=r" (a2)
 			 : "r" (a2), "r" (a6), "r" (a3), "r" (a4),
 			   "r" (a5)
@@ -140,7 +160,7 @@ static inline uintptr_t arch_syscall_invoke3(uintptr_t arg1, uintptr_t arg2,
 	register uintptr_t a3 __asm__("%a3") = arg2;
 	register uintptr_t a4 __asm__("%a4") = arg3;
 
-	__asm__ volatile("syscall\n\t"
+	__asm__ volatile(XTENSA_SYSCALL_ASM
 			 : "=r" (a2)
 			 : "r" (a2), "r" (a6), "r" (a3), "r" (a4)
 			 : "memory");
@@ -155,7 +175,7 @@ static inline uintptr_t arch_syscall_invoke2(uintptr_t arg1, uintptr_t arg2,
 	register uintptr_t a6 __asm__("%a6") = arg1;
 	register uintptr_t a3 __asm__("%a3") = arg2;
 
-	__asm__ volatile("syscall\n\t"
+	__asm__ volatile(XTENSA_SYSCALL_ASM
 			 : "=r" (a2)
 			 : "r" (a2), "r" (a6), "r" (a3)
 			 : "memory");
@@ -168,7 +188,7 @@ static inline uintptr_t arch_syscall_invoke1(uintptr_t arg1, uintptr_t call_id)
 	register uintptr_t a2 __asm__("%a2") = call_id;
 	register uintptr_t a6 __asm__("%a6") = arg1;
 
-	__asm__ volatile("syscall\n\t"
+	__asm__ volatile(XTENSA_SYSCALL_ASM
 			 : "=r" (a2)
 			 : "r" (a2), "r" (a6)
 			 : "memory");
@@ -180,7 +200,7 @@ static inline uintptr_t arch_syscall_invoke0(uintptr_t call_id)
 {
 	register uintptr_t a2 __asm__("%a2") = call_id;
 
-	__asm__ volatile("syscall\n\t"
+	__asm__ volatile(XTENSA_SYSCALL_ASM
 			 : "=r" (a2)
 			 : "r" (a2)
 			 : "memory");
diff --git a/include/zephyr/arch/xtensa/thread.h b/include/zephyr/arch/xtensa/thread.h
index 73f8a95e595..0b5112fb6d9 100644
--- a/include/zephyr/arch/xtensa/thread.h
+++ b/include/zephyr/arch/xtensa/thread.h
@@ -42,6 +42,11 @@ struct _thread_arch {
 	 * Un-set for surpervisor threads.
 	 */
 	uint8_t *psp;
+
+	/* Stashed PS value used to restore PS when restoring from
+	 * context switching or returning from non-nested interrupts.
+	 */
+	uint32_t return_ps;
 #endif
 };
 
diff --git a/include/zephyr/arch/xtensa/thread_stack.h b/include/zephyr/arch/xtensa/thread_stack.h
index 816eaf3b97c..6155f0dfe0e 100644
--- a/include/zephyr/arch/xtensa/thread_stack.h
+++ b/include/zephyr/arch/xtensa/thread_stack.h
@@ -68,7 +68,6 @@ struct xtensa_thread_stack_header {
 	ROUND_UP((size), XTENSA_STACK_SIZE_ALIGN)
 
 /* kernel stack */
-#define ARCH_KERNEL_STACK_RESERVED		0
 #define ARCH_KERNEL_STACK_OBJ_ALIGN		ARCH_STACK_PTR_ALIGN
 
 #endif /* _ASMLANGUAGE */
diff --git a/include/zephyr/arch/xtensa/xtensa_mmu.h b/include/zephyr/arch/xtensa/xtensa_mmu.h
index 91da6a4f656..13dc2385331 100644
--- a/include/zephyr/arch/xtensa/xtensa_mmu.h
+++ b/include/zephyr/arch/xtensa/xtensa_mmu.h
@@ -63,8 +63,10 @@ typedef uint32_t k_mem_partition_attr_t;
 	((k_mem_partition_attr_t) {0})
 
 /* Execution-allowed attributes */
-#define K_MEM_PARTITION_P_RX_U_RX \
+#define K_MEM_PARTITION_P_RX_U_NA \
 	((k_mem_partition_attr_t) {XTENSA_MMU_PERM_X})
+#define K_MEM_PARTITION_P_RX_U_RX \
+	((k_mem_partition_attr_t) {XTENSA_MMU_PERM_X | XTENSA_MMU_MAP_USER})
 
 /**
  * @}
diff --git a/include/zephyr/audio/midi.h b/include/zephyr/audio/midi.h
new file mode 100644
index 00000000000..d564531ecad
--- /dev/null
+++ b/include/zephyr/audio/midi.h
@@ -0,0 +1,204 @@
+/*
+ * Copyright (c) 2024 Titouan Christophe
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_AUDIO_MIDI_H_
+#define ZEPHYR_INCLUDE_AUDIO_MIDI_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+/**
+ * @brief Universal MIDI Packet definitions
+ * @defgroup midi_ump MIDI2 Universal MIDI Packet definitions
+ * @ingroup audio_interface
+ * @since 4.1
+ * @version 0.1.0
+ * @see ump112: "Universal MIDI Packet (UMP) Format and MIDI 2.0 Protocol"
+ *              Document version 1.1.2
+ * @{
+ */
+
+/**
+ * @brief      Universal MIDI Packet container
+ */
+struct midi_ump {
+	uint32_t data[4]; /**< Raw content, in the CPU native endianness */
+};
+
+/**
+ * @defgroup midi_ump_mt Message types
+ * @ingroup midi_ump
+ * @see ump112: 2.1.4 Message Type (MT) Allocation
+ * @{
+ */
+
+/** Utility Messages */
+#define UMP_MT_UTILITY             0x00
+/** System Real Time and System Common Messages (except System Exclusive) */
+#define UMP_MT_SYS_RT_COMMON       0x01
+/** MIDI 1.0 Channel Voice Messages */
+#define UMP_MT_MIDI1_CHANNEL_VOICE 0x02
+/** 64 bits Data Messages (including System Exclusive) */
+#define UMP_MT_DATA_64             0x03
+/** MIDI 2.0 Channel Voice Messages */
+#define UMP_MT_MIDI2_CHANNEL_VOICE 0x04
+/** 128 bits Data Messages */
+#define UMP_MT_DATA_128            0x05
+/** Flex Data Messages */
+#define UMP_MT_FLEX_DATA           0x0d
+/** UMP Stream Message */
+#define UMP_MT_UMP_STREAM          0x0f
+/** @} */
+
+/**
+ * @brief      Message Type field of a Universal MIDI Packet
+ * @param[in]  ump    Universal MIDI Packet
+ */
+#define UMP_MT(ump) \
+	((ump).data[0] >> 28)
+
+/**
+ * There are 16 UMP message types, each of which can be 1 to 4 uint32 long.
+ * Hence this packed representation of 16x2b array as an uint32 lookup table
+ */
+#define UMP_NUM_WORDS_LOOKUP_TABLE \
+	((0U << 0) | (0U << 2) | (0U << 4) | (1U << 6) | \
+	(1U << 8) | (3U << 10) | (0U << 12) | (0U << 14) | \
+	(1U << 16) | (1U << 18) | (1U << 20) | (2U << 22) | \
+	(2U << 24) | (3U << 26) | (3U << 28) | (3U << 30))
+
+/**
+ * @brief      Size of a Universal MIDI Packet, in 32bit words
+ * @param[in]  ump    Universal MIDI Packet
+ * @see ump112: 2.1.4 Message Type (MT) Allocation
+ */
+#define UMP_NUM_WORDS(ump) \
+	(1 + ((UMP_NUM_WORDS_LOOKUP_TABLE >> (2 * UMP_MT(ump))) & 3))
+
+/**
+ * @brief      MIDI group field of a Universal MIDI Packet
+ * @param[in]  ump    Universal MIDI Packet
+ */
+#define UMP_GROUP(ump) \
+	(((ump).data[0] >> 24) & 0x0f)
+
+/**
+ * @brief      Status byte of a MIDI channel voice or system message
+ * @param[in]  ump    Universal MIDI Packet (containing a MIDI1 event)
+ */
+#define UMP_MIDI_STATUS(ump) \
+	(((ump).data[0] >> 16) & 0xff)
+/**
+ * @brief      Command of a MIDI channel voice message
+ * @param[in]  ump    Universal MIDI Packet (containing a MIDI event)
+ * @see midi_ump_cmd
+ */
+#define UMP_MIDI_COMMAND(ump) \
+	(UMP_MIDI_STATUS(ump) >> 4)
+/**
+ * @brief      Channel of a MIDI channel voice message
+ * @param[in]  ump    Universal MIDI Packet (containing a MIDI event)
+ */
+#define UMP_MIDI_CHANNEL(ump) \
+	(UMP_MIDI_STATUS(ump) & 0x0f)
+/**
+ * @brief      First parameter of a MIDI1 channel voice or system message
+ * @param[in]  ump     Universal MIDI Packet (containing a MIDI1 message)
+ */
+#define UMP_MIDI1_P1(ump) \
+	(((ump).data[0] >> 8) & 0x7f)
+/**
+ * @brief      Second parameter of a MIDI1 channel voice or system message
+ * @param[in]  ump     Universal MIDI Packet (containing a MIDI1 message)
+ */
+#define UMP_MIDI1_P2(ump) \
+	((ump).data[0] & 0x7f)
+
+/**
+ * @brief      Initialize a UMP with a MIDI1 channel voice message
+ * @remark     For messages that take a single parameter, p2 is ignored by the receiver.
+ * @param      group    The UMP group
+ * @param      command  The MIDI1 command
+ * @param      channel  The MIDI1 channel number
+ * @param      p1       The 1st MIDI1 parameter
+ * @param      p2       The 2nd MIDI1 parameter
+ */
+#define UMP_MIDI1_CHANNEL_VOICE(group, command, channel, p1, p2) \
+	(struct midi_ump) {.data = {                             \
+		(UMP_MT_MIDI1_CHANNEL_VOICE << 28)               \
+		| (((group) & 0x0f) << 24)                       \
+		| (((command) & 0x0f) << 20)                     \
+		| (((channel) & 0x0f) << 16)                     \
+		| (((p1) & 0x7f) << 8)                           \
+		| ((p2) & 0x7f)                                  \
+	}}
+
+/**
+ * @defgroup midi_ump_cmd MIDI commands
+ * @ingroup midi_ump
+ * @see ump112: 7.3 MIDI 1.0 Channel Voice Messages
+ *
+ * When UMP_MT(x)=UMP_MT_MIDI1_CHANNEL_VOICE or UMP_MT_MIDI2_CHANNEL_VOICE, then
+ * UMP_MIDI_COMMAND(x) may be one of:
+ * @{
+ */
+#define UMP_MIDI_NOTE_OFF        0x8 /**< Note Off (p1=note number, p2=velocity) */
+#define UMP_MIDI_NOTE_ON         0x9 /**< Note On (p1=note number, p2=velocity) */
+#define UMP_MIDI_AFTERTOUCH      0xa /**< Polyphonic aftertouch (p1=note number, p2=data) */
+#define UMP_MIDI_CONTROL_CHANGE  0xb /**< Control Change (p1=index, p2=data) */
+#define UMP_MIDI_PROGRAM_CHANGE  0xc /**< Control Change (p1=program) */
+#define UMP_MIDI_CHAN_AFTERTOUCH 0xd /**< Channel aftertouch (p1=data) */
+#define UMP_MIDI_PITCH_BEND      0xe /**< Pitch bend (p1=lsb, p2=msb) */
+/** @} */
+
+/**
+ * @brief      Initialize a UMP with a System Real Time and System Common Message
+ * @remark     For messages that take only one (or no) parameter, p2 (and p1)
+ *             are ignored by the receiver.
+ * @param      group    The UMP group
+ * @param      status   The status byte
+ * @param      p1       The 1st parameter
+ * @param      p2       The 2nd parameter
+ */
+#define UMP_SYS_RT_COMMON(group, status, p1, p2) \
+	(struct midi_ump) {.data = {             \
+		(UMP_MT_SYS_RT_COMMON << 28)     \
+		| (((group) & 0x0f) << 24)       \
+		| ((status) << 16)               \
+		| (((p1) & 0x7f) << 8)           \
+		| ((p2) & 0x7f)                  \
+	}}
+
+/**
+ * @defgroup midi_ump_sys System common and System Real Time message status
+ * @ingroup midi_ump
+ * @see ump112: 7.6 System Common and System Real Time Messages
+ *
+ * When UMP_MT(x)=UMP_MT_SYS_RT_COMMON, UMP_MIDI_STATUS(x) may be one of:
+ * @{
+ */
+#define UMP_SYS_MIDI_TIME_CODE 0xf1 /**< MIDI Time Code (no param) */
+#define UMP_SYS_SONG_POSITION  0xf2 /**< Song Position Pointer (p1=lsb, p2=msb) */
+#define UMP_SYS_SONG_SELECT    0xf3 /**< Song Select (p1=song number) */
+#define UMP_SYS_TUNE_REQUEST   0xf6 /**< Tune Request (no param) */
+#define UMP_SYS_TIMING_CLOCK   0xf8 /**< Timing Clock (no param) */
+#define UMP_SYS_START          0xfa /**< Start (no param) */
+#define UMP_SYS_CONTINUE       0xfb /**< Continue (no param) */
+#define UMP_SYS_STOP           0xfc /**< Stop (no param) */
+#define UMP_SYS_ACTIVE_SENSING 0xfe /**< Active sensing (no param) */
+#define UMP_SYS_RESET          0xff /**< Reset (no param) */
+/** @} */
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/zephyr/bluetooth/att.h b/include/zephyr/bluetooth/att.h
index 9550848cb7d..21a971a96ec 100644
--- a/include/zephyr/bluetooth/att.h
+++ b/include/zephyr/bluetooth/att.h
@@ -17,8 +17,12 @@
  * @{
  */
 
-#include <zephyr/sys/slist.h>
+#include <stdint.h>
+#include <stddef.h>
+
 #include <zephyr/bluetooth/conn.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/sys/util_macro.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -118,6 +122,8 @@ extern "C" {
 #if defined(CONFIG_BT_ATT_ERR_TO_STR)
 const char *bt_att_err_to_str(uint8_t att_err);
 #else
+#include <zephyr/toolchain.h>
+
 static inline const char *bt_att_err_to_str(uint8_t att_err)
 {
 	ARG_UNUSED(att_err);
@@ -143,7 +149,7 @@ int bt_eatt_reconfigure(struct bt_conn *conn, uint16_t mtu);
  * may be created.
  *
  * @param conn The connection to send the request on
- * @param num_channels The number of Enhanced ATT beares to request.
+ * @param num_channels The number of Enhanced ATT bearers to request.
  * Must be in the range 1 - @kconfig{CONFIG_BT_EATT_MAX}, inclusive.
  *
  * @return 0 in case of success or negative value in case of error.
diff --git a/include/zephyr/bluetooth/audio/bap.h b/include/zephyr/bluetooth/audio/bap.h
index 0c530f93bd8..ad452bf9188 100644
--- a/include/zephyr/bluetooth/audio/bap.h
+++ b/include/zephyr/bluetooth/audio/bap.h
@@ -42,11 +42,12 @@
 extern "C" {
 #endif
 
-#if defined(CONFIG_BT_BAP_BASS_MAX_SUBGROUPS)
-#define BT_BAP_BASS_MAX_SUBGROUPS CONFIG_BT_BAP_BASS_MAX_SUBGROUPS
-#else
-#define BT_BAP_BASS_MAX_SUBGROUPS 0
-#endif /* CONFIG_BT_BAP_BASS_MAX_SUBGROUPS*/
+/** Maximum number of subgroups supported in the BAP Scan Delegator API */
+#define BT_BAP_BASS_MAX_SUBGROUPS                                                                  \
+	COND_CODE_1(CONFIG_BT_AUDIO, (CONFIG_BT_BAP_BASS_MAX_SUBGROUPS), (0))
+
+/** Maximum size of BASE excluding service data header */
+#define BT_BASE_MAX_SIZE (UINT8_MAX - 1 /* type */ - BT_UUID_SIZE_16)
 
 /** An invalid Broadcast ID */
 #define BT_BAP_INVALID_BROADCAST_ID 0xFFFFFFFFU
@@ -148,7 +149,7 @@ extern "C" {
 /**
  * @brief Check if a BAP BASS BIS_Sync bitfield is valid
  *
- * Valid options are eiter a bitmask of valid BIS indices, including none (0x00000000)
+ * Valid options are either a bitmask of valid BIS indices, including none (0x00000000)
  * or @ref BT_BAP_BIS_SYNC_NO_PREF (0xFFFFFFFF).
  *
  * @param _bis_bitfield BIS_Sync bitfield (uint32)
@@ -854,28 +855,30 @@ struct bt_bap_stream {
 	/** Audio stream operations */
 	struct bt_bap_stream_ops *ops;
 
+	/** Stream user data */
+	void *user_data;
+
 #if defined(CONFIG_BT_BAP_UNICAST_CLIENT) || defined(__DOXYGEN__)
+	/** @cond INTERNAL_HIDDEN */
 	/**
-	 * @internal Audio ISO reference
+	 * @brief Audio ISO reference
 	 *
 	 * This is only used for Unicast Client streams, and is handled internally.
 	 */
 	struct bt_bap_iso *bap_iso;
 #endif /* CONFIG_BT_BAP_UNICAST_CLIENT */
 
-	/** @internal Unicast or Broadcast group - Used internally */
+	/** Unicast or Broadcast group - Used internally */
 	void *group;
 
-	/** Stream user data */
-	void *user_data;
-
 #if defined(CONFIG_BT_BAP_DEBUG_STREAM_SEQ_NUM) || defined(__DOXYGEN__)
-	/** @internal Previously sent sequence number */
+	/** Previously sent sequence number */
 	uint16_t _prev_seq_num;
 #endif /* CONFIG_BT_BAP_DEBUG_STREAM_SEQ_NUM */
 
-	/** @internal Internally used list node */
+	/** Internally used list node */
 	sys_snode_t _node;
+	/** @endcond */
 };
 
 /** @brief Stream operation. */
@@ -2117,8 +2120,10 @@ struct bt_bap_broadcast_source_cb {
 	 */
 	void (*stopped)(struct bt_bap_broadcast_source *source, uint8_t reason);
 
-	/** @internal Internally used field for list handling */
+	/** @cond INTERNAL_HIDDEN */
+	/** Internally used field for list handling */
 	sys_snode_t _node;
+	/** @endcond */
 };
 
 /**
@@ -2403,8 +2408,10 @@ struct bt_bap_broadcast_sink_cb {
 	 */
 	void (*stopped)(struct bt_bap_broadcast_sink *sink, uint8_t reason);
 
-	/** @internal Internally used list node */
+	/** @cond INTERNAL_HIDDEN */
+	/** Internally used list node */
 	sys_snode_t _node;
+	/** @endcond */
 };
 
 /**
@@ -2776,8 +2783,10 @@ struct bt_bap_broadcast_assistant_cb {
 	 */
 	void (*rem_src)(struct bt_conn *conn, int err);
 
-	/** @internal Internally used list node */
+	/** @cond INTERNAL_HIDDEN */
+	/** Internally used list node */
 	sys_snode_t _node;
+	/** @endcond */
 };
 
 /**
diff --git a/include/zephyr/bluetooth/audio/cap.h b/include/zephyr/bluetooth/audio/cap.h
index b539a463c26..cfa841afb85 100644
--- a/include/zephyr/bluetooth/audio/cap.h
+++ b/include/zephyr/bluetooth/audio/cap.h
@@ -974,7 +974,7 @@ struct bt_cap_commander_broadcast_reception_start_param {
 int bt_cap_commander_broadcast_reception_start(
 	const struct bt_cap_commander_broadcast_reception_start_param *param);
 
-/** Parameters for stopping broadcast reception  */
+/** Member parameters for stopping broadcast reception  */
 struct bt_cap_commander_broadcast_reception_stop_member_param {
 	/** Coordinated or ad-hoc set member. */
 	union bt_cap_set_member member;
@@ -986,6 +986,7 @@ struct bt_cap_commander_broadcast_reception_stop_member_param {
 	size_t num_subgroups;
 };
 
+/** Parameters for stopping broadcast reception */
 struct bt_cap_commander_broadcast_reception_stop_param {
 	/** The type of the set. */
 	enum bt_cap_set_type type;
@@ -1008,7 +1009,7 @@ struct bt_cap_commander_broadcast_reception_stop_param {
 int bt_cap_commander_broadcast_reception_stop(
 	const struct bt_cap_commander_broadcast_reception_stop_param *param);
 
-/** Parameters for distributing broadcast code */
+/** Member parameters for distributing broadcast code */
 struct bt_cap_commander_distribute_broadcast_code_member_param {
 	/** Coordinated or ad-hoc set member. */
 	union bt_cap_set_member member;
@@ -1017,6 +1018,7 @@ struct bt_cap_commander_distribute_broadcast_code_member_param {
 	uint8_t src_id;
 };
 
+/** Parameters for distributing broadcast code */
 struct bt_cap_commander_distribute_broadcast_code_param {
 	/** The type of the set. */
 	enum bt_cap_set_type type;
diff --git a/include/zephyr/bluetooth/audio/ccp.h b/include/zephyr/bluetooth/audio/ccp.h
index 4bd8b53fd8c..0b74ad46767 100644
--- a/include/zephyr/bluetooth/audio/ccp.h
+++ b/include/zephyr/bluetooth/audio/ccp.h
@@ -31,8 +31,12 @@
  * The profile is not limited to carrier phone calls and can be used with common applications like
  * Discord and Teams.
  */
+#include <stdint.h>
 
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/audio/tbs.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/sys/slist.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -90,6 +94,115 @@ int bt_ccp_call_control_server_unregister_bearer(struct bt_ccp_call_control_serv
 
 /** @} */ /* End of group bt_ccp_call_control_server */
 
+/**
+ * @defgroup bt_ccp_call_control_client CCP Call Control Client APIs
+ * @ingroup bt_ccp
+ * @{
+ */
+/** Abstract Call Control Client structure. */
+struct bt_ccp_call_control_client;
+
+/** Abstract Call Control Client bearer structure. */
+struct bt_ccp_call_control_client_bearer;
+
+/** Struct with information about bearers of a client */
+struct bt_ccp_call_control_client_bearers {
+#if defined(CONFIG_BT_TBS_CLIENT_GTBS)
+	/** The GTBS bearer. */
+	struct bt_ccp_call_control_client_bearer *gtbs_bearer;
+#endif /* CONFIG_BT_TBS_CLIENT_GTBS */
+
+#if defined(CONFIG_BT_TBS_CLIENT_TBS)
+	/** Number of TBS bearers in @p tbs_bearers */
+	size_t tbs_count;
+
+	/** Array of pointers of TBS bearers */
+	struct bt_ccp_call_control_client_bearer
+		*tbs_bearers[CONFIG_BT_CCP_CALL_CONTROL_CLIENT_BEARER_COUNT];
+#endif /* CONFIG_BT_TBS_CLIENT_TBS */
+};
+
+/**
+ * @brief Struct to hold the Telephone Bearer Service client callbacks
+ *
+ * These can be registered for usage with bt_tbs_client_register_cb().
+ */
+struct bt_ccp_call_control_client_cb {
+	/**
+	 * @brief Callback function for bt_ccp_call_control_client_discover().
+	 *
+	 * This callback is called once the discovery procedure is completed.
+	 *
+	 * @param client       Call Control Client pointer.
+	 * @param err          Error value. 0 on success, GATT error on positive
+	 *                     value or errno on negative value.
+	 * @param bearers      The bearers found.
+	 */
+	void (*discover)(struct bt_ccp_call_control_client *client, int err,
+			 struct bt_ccp_call_control_client_bearers *bearers);
+
+	/** @cond INTERNAL_HIDDEN */
+	/** Internally used field for list handling */
+	sys_snode_t _node;
+	/** @endcond */
+};
+
+/**
+ * @brief Discovers the Telephone Bearer Service (TBS) support on a remote device.
+ *
+ * This will discover the Telephone Bearer Service (TBS) and Generic Telephone Bearer Service (GTBS)
+ * on the remote device.
+ *
+ * @kconfig_dep{CONFIG_BT_CCP_CALL_CONTROL_CLIENT}.
+ *
+ * @param conn Connection to a remote server.
+ * @param out_client Pointer to client instance on success
+ *
+ * @retval 0 Success
+ * @retval -EINVAL @p conn or @p out_client is NULL
+ * @retval -ENOTCONN @p conn is not connected
+ * @retval -ENOMEM Could not allocated memory for the request
+ * @retval -EBUSY Already doing discovery for @p conn
+ * @retval -ENOEXEC Rejected by the GATT layer
+ */
+int bt_ccp_call_control_client_discover(struct bt_conn *conn,
+					struct bt_ccp_call_control_client **out_client);
+
+/**
+ * @brief Register callbacks for the Call Control Client
+ *
+ * @param cb The callback struct
+ *
+ * @retval 0 Success
+ * @retval -EINVAL @p cb is NULL
+ * @retval -EEXISTS @p cb is already registered
+ */
+int bt_ccp_call_control_client_register_cb(struct bt_ccp_call_control_client_cb *cb);
+
+/**
+ * @brief Unregister callbacks for the Call Control Client
+ *
+ * @param cb The callback struct
+ *
+ * @retval 0 Success
+ * @retval -EINVAL @p cb is NULL
+ * @retval -EALREADY @p cb is not registered
+ */
+int bt_ccp_call_control_client_unregister_cb(struct bt_ccp_call_control_client_cb *cb);
+
+/**
+ * @brief Get the bearers of a client instance
+ *
+ * @param[in]  client  The client to get the bearers of.
+ * @param[out] bearers The bearers struct that will be populated with the bearers of @p client.
+
+ * @retval 0 Success
+ * @retval -EINVAL @p client or @p bearers is NULL
+ */
+int bt_ccp_call_control_client_get_bearers(struct bt_ccp_call_control_client *client,
+					   struct bt_ccp_call_control_client_bearers *bearers);
+
+/** @} */ /* End of group bt_ccp_call_control_client */
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/zephyr/bluetooth/audio/csip.h b/include/zephyr/bluetooth/audio/csip.h
index 48540c6f5ee..312eaaee14f 100644
--- a/include/zephyr/bluetooth/audio/csip.h
+++ b/include/zephyr/bluetooth/audio/csip.h
@@ -505,8 +505,10 @@ struct bt_csip_set_coordinator_cb {
 	/** Callback for the ordered access procedure */
 	bt_csip_set_coordinator_ordered_access_cb_t ordered_access;
 
-	/** @internal Internally used field for list handling */
+	/** @cond INTERNAL_HIDDEN */
+	/** Internally used field for list handling */
 	sys_snode_t _node;
+	/** @endcond */
 };
 
 /**
diff --git a/include/zephyr/bluetooth/audio/gmap_lc3_preset.h b/include/zephyr/bluetooth/audio/gmap_lc3_preset.h
index 73217d9d18d..f1fab5d74bf 100644
--- a/include/zephyr/bluetooth/audio/gmap_lc3_preset.h
+++ b/include/zephyr/bluetooth/audio/gmap_lc3_preset.h
@@ -26,6 +26,7 @@
  */
 
 #include <zephyr/bluetooth/audio/audio.h>
+#include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/audio/bap_lc3_preset.h>
 #include <zephyr/bluetooth/audio/lc3.h>
 
diff --git a/include/zephyr/bluetooth/audio/micp.h b/include/zephyr/bluetooth/audio/micp.h
index 45d75c515d8..7bc33f86fd9 100644
--- a/include/zephyr/bluetooth/audio/micp.h
+++ b/include/zephyr/bluetooth/audio/micp.h
@@ -219,8 +219,10 @@ struct bt_micp_mic_ctlr_cb {
 	struct bt_aics_cb               aics_cb;
 #endif /* CONFIG_BT_MICP_MIC_CTLR_AICS */
 
-	/** @internal Internally used field for list handling */
+	/** @cond INTERNAL_HIDDEN */
+	/** Internally used field for list handling */
 	sys_snode_t _node;
+	/** @endcond */
 };
 
 /**
diff --git a/include/zephyr/bluetooth/audio/pacs.h b/include/zephyr/bluetooth/audio/pacs.h
index e956e0da7f4..d9b6ced9c0a 100644
--- a/include/zephyr/bluetooth/audio/pacs.h
+++ b/include/zephyr/bluetooth/audio/pacs.h
@@ -41,8 +41,47 @@ struct bt_pacs_cap {
 	/** Codec capability reference */
 	const struct bt_audio_codec_cap *codec_cap;
 
-	/** @internal Internally used list node */
+	/** @cond INTERNAL_HIDDEN */
+	/** Internally used field for list handling */
 	sys_snode_t _node;
+	/** @endcond */
+};
+
+/** Structure for registering PACS */
+struct bt_pacs_register_param {
+#if defined(CONFIG_BT_PAC_SNK) || defined(__DOXYGEN__)
+	/**
+	 * @brief Enables or disables registration of Sink PAC Characteristic.
+	 */
+	bool snk_pac;
+#endif /* CONFIG_BT_PAC_SNK */
+
+#if defined(CONFIG_BT_PAC_SNK_LOC) || defined(__DOXYGEN__)
+	/**
+	 * @brief Enables or disables registration of Sink Location Characteristic.
+	 *
+	 * Registration of Sink Location is dependent on @ref bt_pacs_register_param.snk_pac
+	 * also being set.
+	 */
+	bool snk_loc;
+#endif /* CONFIG_BT_PAC_SNK_LOC */
+
+#if defined(CONFIG_BT_PAC_SRC) || defined(__DOXYGEN__)
+	/**
+	 * @brief Enables or disables registration of Source PAC Characteristic.
+	 */
+	bool src_pac;
+#endif /* CONFIG_BT_PAC_SRC */
+
+#if defined(CONFIG_BT_PAC_SRC_LOC) || defined(__DOXYGEN__)
+	/**
+	 * @brief Enables or disables registration of Source Location Characteristic.
+	 *
+	 * Registration of Source Location is dependent on @ref bt_pacs_register_param.src_pac
+	 * also being set.
+	 */
+	bool src_loc;
+#endif /* CONFIG_BT_PAC_SRC_LOC */
 };
 
 /**
@@ -71,6 +110,25 @@ void bt_pacs_cap_foreach(enum bt_audio_dir dir,
 			 bt_pacs_cap_foreach_func_t func,
 			 void *user_data);
 
+/**
+ * @brief Register the Published Audio Capability Service instance.
+ *
+ * @param param PACS register parameters.
+ *
+ * @retval 0 Success
+ * @retval -EINVAL @p param is NULL or bad combination of values in @p param
+ * @retval -EALREADY Already registered
+ * @retval -ENOEXEC Request was rejected by GATT
+ */
+int bt_pacs_register(const struct bt_pacs_register_param *param);
+
+/**
+ * @brief Unregister the Published Audio Capability Service instance.
+ *
+ * @return 0 in case of success or negative value in case of error.
+ */
+int bt_pacs_unregister(void);
+
 /**
  * @brief Register Published Audio Capability.
  *
diff --git a/include/zephyr/bluetooth/audio/pbp.h b/include/zephyr/bluetooth/audio/pbp.h
index db649e523ab..3391a52a28d 100644
--- a/include/zephyr/bluetooth/audio/pbp.h
+++ b/include/zephyr/bluetooth/audio/pbp.h
@@ -26,6 +26,8 @@
  * The Public Broadcast Profile (PBP) is used for public broadcasts by providing additional
  * information in the advertising data.
  */
+#include <stddef.h>
+#include <stdint.h>
 
 #include <zephyr/bluetooth/audio/audio.h>
 #include <zephyr/bluetooth/bluetooth.h>
diff --git a/include/zephyr/bluetooth/audio/tbs.h b/include/zephyr/bluetooth/audio/tbs.h
index 6f408ff8174..895949cbfc2 100644
--- a/include/zephyr/bluetooth/audio/tbs.h
+++ b/include/zephyr/bluetooth/audio/tbs.h
@@ -462,6 +462,7 @@ int bt_tbs_set_uri_scheme_list(uint8_t bearer_index, const char **uri_list,
  */
 void bt_tbs_register_cb(struct bt_tbs_cb *cbs);
 
+/** Parameters for registering a Telephone Bearer Service */
 struct bt_tbs_register_param {
 	/** The name of the provider, for example a cellular service provider */
 	char *provider_name;
@@ -774,8 +775,10 @@ struct bt_tbs_client_cb {
 	bt_tbs_client_read_string_cb         friendly_name;
 #endif /* defined(CONFIG_BT_TBS_CLIENT_CALL_FRIENDLY_NAME) */
 
-	/** @internal Internally used field for list handling */
+	/** @cond INTERNAL_HIDDEN */
+	/** Internally used field for list handling */
 	sys_snode_t _node;
+	/** @endcond */
 };
 
 /**
diff --git a/include/zephyr/bluetooth/audio/vcp.h b/include/zephyr/bluetooth/audio/vcp.h
index 29662ffec44..a7de11733de 100644
--- a/include/zephyr/bluetooth/audio/vcp.h
+++ b/include/zephyr/bluetooth/audio/vcp.h
@@ -405,8 +405,10 @@ struct bt_vcp_vol_ctlr_cb {
 	/** Audio Input Control Service callbacks */
 	struct bt_aics_cb             aics_cb;
 
-	/** @internal Internally used field for list handling */
+	/** @cond INTERNAL_HIDDEN */
+	/** Internally used field for list handling */
 	sys_snode_t _node;
+	/** @endcond */
 };
 
 /**
diff --git a/include/zephyr/bluetooth/bluetooth.h b/include/zephyr/bluetooth/bluetooth.h
index d04dbfdd7c8..425d9a7a1b9 100644
--- a/include/zephyr/bluetooth/bluetooth.h
+++ b/include/zephyr/bluetooth/bluetooth.h
@@ -1,5 +1,6 @@
-/** @file
- *  @brief Bluetooth subsystem core APIs.
+/**
+ * @file
+ * @brief Bluetooth subsystem core APIs.
  */
 
 /*
@@ -13,12 +14,14 @@
 
 /**
  * @brief Bluetooth APIs
+ *
  * @details The Bluetooth Subsystem Core APIs provide essential functionalities
  *          to use and manage Bluetooth based communication. These APIs include
  *          APIs for Bluetooth stack initialization, device discovery,
  *          connection management, data transmission, profiles and services.
  *          These APIs support both classic Bluetooth and Bluetooth Low Energy
  *          (LE) operations.
+ *
  * @defgroup bluetooth Bluetooth APIs
  * @ingroup connectivity
  * @{
@@ -28,12 +31,15 @@
 #include <stdint.h>
 #include <string.h>
 
-#include <zephyr/sys/util.h>
-#include <zephyr/net_buf.h>
 #include <zephyr/bluetooth/gap.h>
 #include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/crypto.h>
 #include <zephyr/bluetooth/classic/classic.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/toolchain.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -41,6 +47,7 @@ extern "C" {
 
 /**
  * @brief Generic Access Profile (GAP)
+ *
  * @details The Generic Access Profile (GAP) defines fundamental Bluetooth
  *          operations, including device discovery, pairing, and connection
  *          management. Zephyr's GAP implementation supports both classic
@@ -48,6 +55,7 @@ extern "C" {
  *          roles such as Broadcaster, Observer, Peripheral, and Central. These
  *          roles define the device's behavior in advertising, scanning, and
  *          establishing connections within Bluetooth networks.
+ *
  * @defgroup bt_gap Generic Access Profile (GAP)
  * @since 1.0
  * @version 1.0.0
@@ -56,9 +64,9 @@ extern "C" {
  */
 
 /**
- * Convenience macro for specifying the default identity. This helps
- * make the code more readable, especially when only one identity is
- * supported.
+ * Identity handle referring to the first identity address. This is a convenience macro for
+ * specifying the default identity address. This helps make the code more readable, especially when
+ * only one identity address is supported.
  */
 #define BT_ID_DEFAULT 0
 
@@ -84,21 +92,50 @@ struct bt_iso_biginfo;
 /* Don't require everyone to include direction.h */
 struct bt_df_per_adv_sync_iq_samples_report;
 
+/**
+ * @brief Info of the advertising sent event.
+ *
+ * @note Used in @ref bt_le_ext_adv_cb.
+ */
 struct bt_le_ext_adv_sent_info {
-	/** The number of advertising events completed. */
+	/**
+	 * If the advertising set was started with a non-zero
+	 * @ref bt_le_ext_adv_start_param.num_events, this field
+	 * contains the number of times this advertising set has
+	 * been sent since it was enabled.
+	 */
 	uint8_t num_sent;
 };
 
+/**
+ * @brief Info of the advertising connected event.
+ *
+ * @note Used in @ref bt_le_ext_adv_cb.
+ */
 struct bt_le_ext_adv_connected_info {
 	/** Connection object of the new connection */
 	struct bt_conn *conn;
 };
 
+/**
+ * @brief Info of the advertising scanned event.
+ *
+ * @note Used in @ref bt_le_ext_adv_cb.
+ */
 struct bt_le_ext_adv_scanned_info {
 	/** Active scanner LE address and type */
 	bt_addr_le_t *addr;
 };
 
+/**
+ * @brief Info of the PAwR subevents.
+ *
+ * @details When the Controller indicates it is ready to transmit one or more PAwR subevents,
+ * @ref bt_le_per_adv_data_request holds the information about the first subevent data and the
+ * number of subevents data can be set for.
+ *
+ * @note Used in @ref bt_le_ext_adv_cb.
+ */
 struct bt_le_per_adv_data_request {
 	/** The first subevent data can be set for */
 	uint8_t start;
@@ -107,6 +144,16 @@ struct bt_le_per_adv_data_request {
 	uint8_t count;
 };
 
+/**
+ * @brief Info about the PAwR responses received.
+ *
+ * @details When the Controller indicates that one or more synced devices have responded to a
+ * periodic advertising subevent indication, @ref bt_le_per_adv_response_info holds the information
+ * about the subevent in question, its status, TX power, RSSI of the response, the Constant Tone
+ * Extension of the advertisement, and the slot the response was received in.
+ *
+ * @note Used in @ref bt_le_ext_adv_cb.
+ */
 struct bt_le_per_adv_response_info {
 	/** The subevent the response was received in */
 	uint8_t subevent;
@@ -132,14 +179,33 @@ struct bt_le_per_adv_response_info {
 	uint8_t response_slot;
 };
 
+/**
+ * @brief Callback struct to notify about advertiser activity.
+ *
+ * @details The @ref bt_le_ext_adv_cb struct contains callback functions that are invoked in
+ * response to various events related to the advertising set. These events include:
+ *     - Completion of advertising data transmission
+ *     - Acceptance of a new connection
+ *     - Transmission of scan response data
+ *     - If privacy is enabled:
+ *         - Expiration of the advertising set's validity
+ *     - If PAwR (Periodic Advertising with Response) is enabled:
+ *         - Readiness to send one or more PAwR subevents, namely the LE Periodic Advertising
+ *           Subevent Data Request event
+ *         - Response of synced devices to a periodic advertising subevent indication has been
+ *           received, namely the LE Periodic Advertising Response Report event
+ *
+ * @note Must point to valid memory during the lifetime of the advertising set.
+ *
+ * @note Used in @ref bt_le_ext_adv_create.
+ */
 struct bt_le_ext_adv_cb {
 	/**
-	 * @brief The advertising set has finished sending adv data.
+	 * @brief The advertising set was disabled after reaching limit
 	 *
-	 * This callback notifies the application that the advertising set has
-	 * finished sending advertising data.
-	 * The advertising set can either have been stopped by a timeout or
-	 * because the specified number of advertising events has been reached.
+	 * This callback is invoked when the limit set in
+	 * @ref bt_le_ext_adv_start_param.timeout or
+	 * @ref bt_le_ext_adv_start_param.num_events is reached.
 	 *
 	 * @param adv  The advertising set object.
 	 * @param info Information about the sent event.
@@ -167,7 +233,7 @@ struct bt_le_ext_adv_cb {
 	 * packet.
 	 *
 	 * @param adv  The advertising set object.
-	 * @param addr Information about the scanned event.
+	 * @param info Information about the scanned event, namely the address.
 	 */
 	void (*scanned)(struct bt_le_ext_adv *adv,
 			struct bt_le_ext_adv_scanned_info *info);
@@ -176,13 +242,13 @@ struct bt_le_ext_adv_cb {
 	/**
 	 * @brief The RPA validity of the advertising set has expired.
 	 *
-	 * This callback notifies the application that the RPA validity of
-	 * the advertising set has expired. The user can use this callback
-	 * to synchronize the advertising payload update with the RPA rotation.
+	 * This callback notifies the application that the RPA validity of the advertising set has
+	 * expired. The user can use this callback to synchronize the advertising payload update
+	 * with the RPA rotation by for example invoking @ref bt_le_ext_adv_set_data upon callback.
 	 *
-	 * If rpa sharing is enabled and rpa expired cb of any adv-sets belonging
-	 * to same adv id returns false, then adv-sets will continue with old rpa
-	 * through out the rpa rotations.
+	 * If RPA sharing is enabled (see @kconfig{CONFIG_BT_RPA_SHARING}) and this RPA expired
+	 * callback of any adv-sets belonging to same adv id returns false, then adv-sets will
+	 * continue with the old RPA throughout the RPA rotations.
 	 *
 	 * @param adv  The advertising set object.
 	 *
@@ -194,7 +260,7 @@ struct bt_le_ext_adv_cb {
 
 #if defined(CONFIG_BT_PER_ADV_RSP)
 	/**
-	 * @brief The Controller indicates it is ready to transmit one or more subevent.
+	 * @brief The Controller indicates it is ready to transmit one or more PAwR subevents.
 	 *
 	 * This callback notifies the application that the controller has requested
 	 * data for upcoming subevents.
@@ -253,7 +319,7 @@ int bt_enable(bt_ready_cb_t cb);
  *
  * Disable Bluetooth. Can't be called before bt_enable has completed.
  *
- * This API will clear all configured identities and keys that are not persistently
+ * This API will clear all configured identity addresses and keys that are not persistently
  * stored with @kconfig{CONFIG_BT_SETTINGS}. These can be restored
  * with settings_load() before reenabling the stack.
  *
@@ -333,36 +399,35 @@ uint16_t bt_get_appearance(void);
 int bt_set_appearance(uint16_t new_appearance);
 
 /**
- * @brief Get the currently configured identities.
+ * @brief Get the currently configured identity addresses.
  *
  * Returns an array of the currently configured identity addresses. To
- * make sure all available identities can be retrieved, the number of
+ * make sure all available identity addresses can be retrieved, the number of
  * elements in the @a addrs array should be CONFIG_BT_ID_MAX. The identity
- * identifier that some APIs expect (such as advertising parameters) is
- * simply the index of the identity in the @a addrs array.
+ * handle that some APIs expect (such as @ref bt_le_adv_param) is
+ * simply the index of the identity address in the @a addrs array.
  *
- * If @a addrs is passed as NULL, then returned @a count contains the
- * count of all available identities that can be retrieved with a
+ * If @a addrs is passed as NULL, then the returned @a count contains the
+ * count of all available identity addresses that can be retrieved with a
  * subsequent call to this function with non-NULL @a addrs parameter.
  *
- * @note Deleted identities may show up as @ref BT_ADDR_LE_ANY in the returned
- * array.
+ * @note Deleted identity addresses may show up as @ref BT_ADDR_LE_ANY in the returned array.
  *
- * @param addrs Array where to store the configured identities.
- * @param count Should be initialized to the array size. Once the function
- *              returns it will contain the number of returned identities.
+ * @param addrs Array where to store the configured identity addresses.
+ * @param count Should be initialized to the array size. Once the function returns
+ *              it will contain the number of returned identity addresses.
  */
 void bt_id_get(bt_addr_le_t *addrs, size_t *count);
 
 /**
- * @brief Create a new identity.
+ * @brief Create a new identity address.
  *
- * Create a new identity using the given address and IRK. This function can be
- * called before calling bt_enable(). However, the new identity will only be
+ * Create a new identity address using the given address and IRK. This function can be
+ * called before calling bt_enable(). However, the new identity address will only be
  * stored persistently in flash when this API is used after bt_enable(). The
  * reason is that the persistent settings are loaded after bt_enable() and would
  * therefore cause potential conflicts with the stack blindly overwriting what's
- * stored in flash. The identity will also not be written to flash in case a
+ * stored in flash. The identity address will also not be written to flash in case a
  * pre-defined address is provided, since in such a situation the app clearly
  * has some place it got the address from and will be able to repeat the
  * procedure on every power cycle, i.e. it would be redundant to also store the
@@ -371,11 +436,11 @@ void bt_id_get(bt_addr_le_t *addrs, size_t *count);
  * Generating random static address or random IRK is not supported when calling
  * this function before bt_enable().
  *
- * If the application wants to have the stack randomly generate identities
+ * If the application wants to have the stack randomly generate identity addresses
  * and store them in flash for later recovery, the way to do it would be
  * to first initialize the stack (using bt_enable), then call settings_load(),
- * and after that check with bt_id_get() how many identities were recovered.
- * If an insufficient amount of identities were recovered the app may then
+ * and after that check with bt_id_get() how many identity addresses were recovered.
+ * If an insufficient amount of identity addresses were recovered the app may then
  * call bt_id_create() to create new ones.
  *
  * If supported by the HCI driver (indicated by setting
@@ -384,71 +449,66 @@ void bt_id_get(bt_addr_le_t *addrs, size_t *count);
  * before calling bt_enable(). Subsequent calls always add/generate random
  * static addresses.
  *
- * @param addr Address to use for the new identity. If NULL or initialized
- *             to BT_ADDR_LE_ANY the stack will generate a new random
- *             static address for the identity and copy it to the given
- *             parameter upon return from this function (in case the
- *             parameter was non-NULL).
+ * @param addr Address to use for the new identity address. If NULL or initialized
+ *             to BT_ADDR_LE_ANY the stack will generate a new random static address
+ *             for the identity address and copy it to the given parameter upon return
+ *             from this function (in case the parameter was non-NULL).
  * @param irk  Identity Resolving Key (16 bytes) to be used with this
- *             identity. If set to all zeroes or NULL, the stack will
- *             generate a random IRK for the identity and copy it back
+ *             identity address. If set to all zeroes or NULL, the stack will
+ *             generate a random IRK for the identity address and copy it back
  *             to the parameter upon return from this function (in case
  *             the parameter was non-NULL). If privacy
  *             @kconfig{CONFIG_BT_PRIVACY} is not enabled this parameter must
  *             be NULL.
  *
- * @return Identity identifier (>= 0) in case of success, or a negative
- *         error code on failure.
+ * @return Identity handle (>= 0) in case of success, or a negative error code on failure.
  */
 int bt_id_create(bt_addr_le_t *addr, uint8_t *irk);
 
 /**
- * @brief Reset/reclaim an identity for reuse.
+ * @brief Reset/reclaim an identity address for reuse.
  *
  * The semantics of the @a addr and @a irk parameters of this function
  * are the same as with bt_id_create(). The difference is the first
- * @a id parameter that needs to be an existing identity (if it doesn't
- * exist this function will return an error). When given an existing
- * identity this function will disconnect any connections created using it,
- * remove any pairing keys or other data associated with it, and then create
- * a new identity in the same slot, based on the @a addr and @a irk
- * parameters.
- *
- * @note the default identity (BT_ID_DEFAULT) cannot be reset, i.e. this
+ * @a id parameter that needs to be an existing identity handle (if it doesn't
+ * exist this function will return an error). When given an existing identity handle
+ * this function will disconnect any connections (to the corresponding identity address)
+ * created using it, remove any pairing keys or other data associated with it, and then
+ * create a new identity address in the same slot, based on the @a addr and @a irk parameters.
+ *
+ * @note The default identity address (corresponding to BT_ID_DEFAULT) cannot be reset, and this
  * API will return an error if asked to do that.
  *
- * @param id   Existing identity identifier.
- * @param addr Address to use for the new identity. If NULL or initialized
- *             to BT_ADDR_LE_ANY the stack will generate a new static
- *             random address for the identity and copy it to the given
- *             parameter upon return from this function (in case the
- *             parameter was non-NULL).
+ * @param id   Existing identity handle.
+ * @param addr Address to use for the new identity address. If NULL or initialized
+ *             to BT_ADDR_LE_ANY the stack will generate a new static random
+ *             address for the identity address and copy it to the given
+ *             parameter upon return from this function.
  * @param irk  Identity Resolving Key (16 bytes) to be used with this
- *             identity. If set to all zeroes or NULL, the stack will
- *             generate a random IRK for the identity and copy it back
+ *             identity address. If set to all zeroes or NULL, the stack will
+ *             generate a random IRK for the identity address and copy it back
  *             to the parameter upon return from this function (in case
  *             the parameter was non-NULL). If privacy
  *             @kconfig{CONFIG_BT_PRIVACY} is not enabled this parameter must
  *             be NULL.
  *
- * @return Identity identifier (>= 0) in case of success, or a negative
- *         error code on failure.
+ * @return Identity handle (>= 0) in case of success, or a negative error code on failure.
  */
 int bt_id_reset(uint8_t id, bt_addr_le_t *addr, uint8_t *irk);
 
 /**
- * @brief Delete an identity.
+ * @brief Delete an identity address.
  *
- * When given a valid identity this function will disconnect any connections
- * created using it, remove any pairing keys or other data associated with
- * it, and then flag is as deleted, so that it can not be used for any
- * operations. To take back into use the slot the identity was occupying the
- * bt_id_reset() API needs to be used.
+ * When given a valid identity handle this function will disconnect any connections
+ * (to the corresponding identity address) created using it, remove any pairing keys
+ * or other data associated with it, and then flag is as deleted, so that it can not
+ * be used for any operations. To take back into use the slot the identity address was
+ * occupying, the bt_id_reset() API needs to be used.
  *
- * @note the default identity (BT_ID_DEFAULT) cannot be deleted, i.e. this
+ * @note The default identity address (corresponding to BT_ID_DEFAULT) cannot be deleted, and this
  * API will return an error if asked to do that.
  *
- * @param id   Existing identity identifier.
+ * @param id   Existing identity handle.
  *
  * @return 0 in case of success, or a negative error code on failure.
  */
@@ -470,13 +530,16 @@ int bt_id_delete(uint8_t id);
 /**
  * @brief Bluetooth data.
  *
- * Description of different data types that can be encoded into
- * advertising data. Used to form arrays that are passed to the
- * bt_le_adv_start() function.
+ * @details Description of different AD Types that can be encoded into advertising data. Used to
+ * form arrays that are passed to the @ref bt_le_adv_start function. The @ref BT_DATA define can
+ * be used as a helpter to declare the elements of an @ref bt_data array.
  */
 struct bt_data {
+	/** Type of scan response data or advertisement data. */
 	uint8_t type;
+	/** Length of scan response data or advertisement data. */
 	uint8_t data_len;
+	/** Pointer to Scan response or advertisement data. */
 	const uint8_t *data;
 };
 
@@ -484,7 +547,7 @@ struct bt_data {
  * @brief Helper to declare elements of bt_data arrays
  *
  * This macro is mainly for creating an array of struct bt_data
- * elements which is then passed to e.g. @ref bt_le_adv_start().
+ * elements which is then passed to e.g. @ref bt_le_adv_start function.
  *
  * @param _type Type of advertising data field
  * @param _data Pointer to the data field payload
@@ -501,7 +564,7 @@ struct bt_data {
  * @brief Helper to declare elements of bt_data arrays
  *
  * This macro is mainly for creating an array of struct bt_data
- * elements which is then passed to e.g. @ref bt_le_adv_start().
+ * elements which is then passed to e.g. @ref bt_le_adv_start function.
  *
  * @param _type Type of advertising data field
  * @param _bytes Variable number of single-byte parameters
@@ -538,6 +601,17 @@ size_t bt_data_get_len(const struct bt_data data[], size_t data_count);
  */
 size_t bt_data_serialize(const struct bt_data *input, uint8_t *output);
 
+/**
+ * @brief Local Bluetooth LE controller features and capabilities.
+ *
+ * @details This struct provides details about the Bluetooth LE controller's supported features,
+ * states, and various other capabilities. It includes information on ACL and ISO data packet
+ * lengths, the controller's resolving list size, and the maximum advertising data length. This
+ * information can be obtained after enabling the Bluetooth stack with @ref bt_enable function.
+ *
+ * Refer to the Bluetooth Core Specification, Volume 6, Part B and Volume 4, Part E for detailed
+ * sections about each field's significance and values.
+ */
 struct bt_le_local_features {
 	/**
 	 * @brief Local LE controller supported features.
@@ -611,7 +685,7 @@ struct bt_le_local_features {
 int bt_le_get_local_features(struct bt_le_local_features *local_features);
 
 /** Advertising options */
-enum {
+enum bt_le_adv_opt {
 	/** Convenience value when no options are specified. */
 	BT_LE_ADV_OPT_NONE = 0,
 
@@ -812,7 +886,8 @@ enum {
 	 *
 	 * @note Cannot be set if BT_LE_ADV_OPT_CODED is set.
 	 *
-	 * @note Requires @ref BT_LE_ADV_OPT_EXT_ADV.
+	 * @note Requires @ref BT_LE_ADV_OPT_EXT_ADV bit (see @ref bt_le_adv_opt field)  to be
+	 * set as @ref bt_le_adv_param.options.
 	 */
 	BT_LE_ADV_OPT_NO_2M = BIT(11),
 
@@ -824,21 +899,24 @@ enum {
 	 * the trade-off of lower data rate and higher power consumption.
 	 * Connections will be established on LE Coded PHY.
 	 *
-	 * @note Requires @ref BT_LE_ADV_OPT_EXT_ADV
+	 * @note Requires @ref BT_LE_ADV_OPT_EXT_ADV bit (see @ref bt_le_adv_opt field)  to be
+	 * set as @ref bt_le_adv_param.options.
 	 */
 	BT_LE_ADV_OPT_CODED = BIT(12),
 
 	/**
-	 * @brief Advertise without a device address (identity or RPA).
+	 * @brief Advertise without a device address (identity address or RPA).
 	 *
-	 * @note Requires @ref BT_LE_ADV_OPT_EXT_ADV
+	 * @note Requires @ref BT_LE_ADV_OPT_EXT_ADV bit (see @ref bt_le_adv_opt field)  to be
+	 * set as @ref bt_le_adv_param.options.
 	 */
 	BT_LE_ADV_OPT_ANONYMOUS = BIT(13),
 
 	/**
 	 * @brief Advertise with transmit power.
 	 *
-	 * @note Requires @ref BT_LE_ADV_OPT_EXT_ADV
+	 * @note Requires @ref BT_LE_ADV_OPT_EXT_ADV bit (see @ref bt_le_adv_opt field)  to be
+	 * set as @ref bt_le_adv_param.options.
 	 */
 	BT_LE_ADV_OPT_USE_TX_POWER = BIT(14),
 
@@ -916,7 +994,9 @@ enum {
 /** LE Advertising Parameters. */
 struct bt_le_adv_param {
 	/**
-	 * @brief Local identity.
+	 * @brief Local identity handle.
+	 *
+	 * The index of the identity address in the local Bluetooth controller.
 	 *
 	 * @note When extended advertising @kconfig{CONFIG_BT_EXT_ADV} is not
 	 *       enabled or not supported by the controller it is not possible
@@ -928,7 +1008,8 @@ struct bt_le_adv_param {
 	/**
 	 * @brief Advertising Set Identifier, valid range 0x00 - 0x0f.
 	 *
-	 * @note Requires @ref BT_LE_ADV_OPT_EXT_ADV
+	 * @note Requires @ref BT_LE_ADV_OPT_EXT_ADV bit (see @ref bt_le_adv_opt field)  to be
+	 *set as @ref bt_le_adv_param.options.
 	 **/
 	uint8_t  sid;
 
@@ -938,27 +1019,34 @@ struct bt_le_adv_param {
 	 * Maximum advertising events the advertiser can skip before it must
 	 * send advertising data on the secondary advertising channel.
 	 *
-	 * @note Requires @ref BT_LE_ADV_OPT_EXT_ADV
+	 * @note Requires @ref BT_LE_ADV_OPT_EXT_ADV bit (see @ref bt_le_adv_opt field)  to be
+	 * set as @ref bt_le_adv_param.options.
 	 */
 	uint8_t  secondary_max_skip;
 
-	/** Bit-field of advertising options */
+	/** @brief Bit-field of advertising options, see the @ref bt_le_adv_opt field. */
 	uint32_t options;
 
-	/** Minimum Advertising Interval (N * 0.625 milliseconds)
-	 * Minimum Advertising Interval shall be less than or equal to the
-	 * Maximum Advertising Interval. The Minimum Advertising Interval and
-	 * Maximum Advertising Interval should not be the same value (as stated
-	 * in Bluetooth Core Spec 5.2, section 7.8.5)
+	/**
+	 * @brief Minimum Advertising Interval (N * 0.625 milliseconds)
+	 *
+	 * @details The Minimum Advertising Interval shall be less than or equal to the Maximum
+	 * Advertising Interval. The Minimum Advertising Interval and Maximum Advertising Interval
+	 * aren't recommended to be the same value to enable the Controller to determine the best
+	 * advertising interval given other activities.
+	 * (See Bluetooth Core Spec 6.0, Vol 4, Part E, section 7.8.5)
 	 * Range: 0x0020 to 0x4000
 	 */
 	uint32_t interval_min;
 
-	/** Maximum Advertising Interval (N * 0.625 milliseconds)
-	 * Minimum Advertising Interval shall be less than or equal to the
-	 * Maximum Advertising Interval. The Minimum Advertising Interval and
-	 * Maximum Advertising Interval should not be the same value (as stated
-	 * in Bluetooth Core Spec 5.2, section 7.8.5)
+	/**
+	 * @brief Maximum Advertising Interval (N * 0.625 milliseconds)
+	 *
+	 * @details The Maximum Advertising Interval shall be more than or equal to the Minimum
+	 * Advertising Interval. The Minimum Advertising Interval and Maximum Advertising Interval
+	 * aren't recommended to be the same value to enable the Controller to determine the best
+	 * advertising interval given other activities.
+	 * (See Bluetooth Core Spec 6.0, Vol 4, Part E, section 7.8.5)
 	 * Range: 0x0020 to 0x4000
 	 */
 	uint32_t interval_max;
@@ -983,25 +1071,40 @@ struct bt_le_adv_param {
 
 
 /** Periodic Advertising options */
-enum {
+enum bt_le_per_adv_opt {
 	/** Convenience value when no options are specified. */
 	BT_LE_PER_ADV_OPT_NONE = 0,
 
 	/**
 	 * @brief Advertise with transmit power.
 	 *
-	 * @note Requires @ref BT_LE_ADV_OPT_EXT_ADV
+	 * @note Requires @ref BT_LE_ADV_OPT_EXT_ADV bit (see @ref bt_le_adv_opt field)  to be
+	 * set as @ref bt_le_adv_param.options.
 	 */
 	BT_LE_PER_ADV_OPT_USE_TX_POWER = BIT(1),
 
 	/**
 	 * @brief Advertise with included AdvDataInfo (ADI).
 	 *
-	 * @note Requires @ref BT_LE_ADV_OPT_EXT_ADV
+	 * @note Requires @ref BT_LE_ADV_OPT_EXT_ADV bit (see @ref bt_le_adv_opt field)  to be
+	 * set as @ref bt_le_adv_param.options.
 	 */
 	BT_LE_PER_ADV_OPT_INCLUDE_ADI = BIT(2),
 };
 
+/**
+ * @brief Parameters for configuring periodic advertising.
+ *
+ * @details This struct is used to configure the parameters for periodic advertising, including the
+ * minimum and maximum advertising intervals, options, and settings for subevents if periodic
+ * advertising responses are supported. The intervals are specified in units of 1.25 ms, and the
+ * options field can be used to modify other advertising behaviors. For extended advertisers, the
+ * periodic advertising parameters can be set or updated using this structure. Some parameters are
+ * conditional based on whether the device supports periodic advertising responses (configured via
+ * @kconfig{CONFIG_BT_PER_ADV_RSP}).
+ *
+ * @note Used in @ref bt_le_per_adv_set_param function.
+ */
 struct bt_le_per_adv_param {
 	/**
 	 * @brief Minimum Periodic Advertising Interval (N * 1.25 ms)
@@ -1019,7 +1122,7 @@ struct bt_le_per_adv_param {
 	 */
 	uint16_t interval_max;
 
-	/** Bit-field of periodic advertising options */
+	/** Bit-field of periodic advertising options, see the @ref bt_le_adv_opt field. */
 	uint32_t options;
 
 #if defined(CONFIG_BT_PER_ADV_RSP)
@@ -1107,42 +1210,57 @@ struct bt_le_per_adv_param {
 			BT_GAP_ADV_FAST_INT_MAX_2, NULL)                                           \
 	__DEPRECATED_MACRO
 
-/** @brief GAP recommended connectable advertising
+/**
+ * @brief GAP recommended connectable advertising parameters user-initiated
+ *
+ * @details This define sets the recommended default for when an application is likely waiting for
+ * the device to be connected or discovered.
  *
- * This is the recommended default for when a person is likely
- * to be waiting the device to connect or be discovered.
+ * GAP recommends advertisers use the advertising parameters set by @ref BT_LE_ADV_CONN_FAST_1 for
+ * user-initiated advertisements. This might mean any time a user interacts with a device, a press
+ * on a dedicated Bluetooth wakeup button, or anything in-between. Interpretation is left to the
+ * application developer.
  *
- * Use a longer interval to conserve battery at the cost of
- * responsiveness. Consider entering a lower power state with
- * longer intervals after a timeout.
+ * Following modes are considered in these parameter settings:
+ * - Undirected Connectable Mode
+ * - Limited Discoverable Mode and sending connectable undirected advertising events
+ * - General Discoverable Mode and sending connectable undirected advertising events
+ * - Directed Connectable Mode and sending low duty cycle directed advertising events
  *
- * GAP recommends advertisers use this "when user-initiated".
- * The application developer decides what this means. It can by
- * any time the user interacts with the device, a press on a
- * dedicated Bluetooth wakeup button, or anything in-between.
+ * @note These parameters are merely a recommendation. For example the application might use a
+ * longer interval to conserve battery, which would be at the cost of responsiveness and it should
+ * be considered to enter a lower power state with longer intervals only after a timeout.
  *
- * This is the recommended setting for limited discoverable
- * mode.
+ * @note This is the recommended setting for limited discoverable mode.
  *
  * See Bluetooth Core Specification:
- * - 3.C.A "Timers and Constants", T_GAP(adv_fast_interval1)
- * - 3.C.9.3.11 "Connection Establishment Timing parameters"
+ * - 6.0 Vol 3, Part C, Appendix A "Timers and Constants", T_GAP(adv_fast_interval1)
+ * - 6.0 Vol 3, Part C, Section 9.3.11 "Connection Establishment Timing parameters"
  */
+
 #define BT_LE_ADV_CONN_FAST_1                                                                      \
 	BT_LE_ADV_PARAM(BT_LE_ADV_OPT_CONN, BT_GAP_ADV_FAST_INT_MIN_1, BT_GAP_ADV_FAST_INT_MAX_1,  \
 			NULL)
 
-/** @brief Connectable advertising with
- * T_GAP(adv_fast_interval2)
+/**
+ * @brief GAP recommended connectable advertising parameters non-connectable advertising events
+ *
+ * @details This define sets the recommended default for user-initiated advertisements or sending
+ * non-connectable advertising events.
  *
- * The advertising interval corresponds to what was offered as
- * `BT_LE_ADV_CONN` in Zephyr 3.6 and earlier, but unlike
- * `BT_LE_ADV_CONN`, the host does not automatically resume the
- * advertiser after it results in a connection.
+ * Following modes are considered in these parameter settings:
+ * - Non-Discoverable Mode
+ * - Non-Connectable Mode
+ * - Limited Discoverable Mode
+ * - General Discoverable Mode
+ *
+ * The advertising interval corresponds to what was offered as @ref BT_LE_ADV_CONN in Zephyr 3.6 and
+ * earlier, but unlike @ref BT_LE_ADV_CONN, the host does not automatically resume the advertiser
+ * after it results in a connection.
  *
  * See Bluetooth Core Specification:
- * - 3.C.A "Timers and Constants", T_GAP(adv_fast_interval1)
- * - 3.C.9.3.11 "Connection Establishment Timing parameters"
+ * - 6.0 Vol 3, Part C, Appendix A "Timers and Constants", T_GAP(adv_fast_interval2)
+ * - 6.0 Vol 3, Part C, Section 9.3.11 "Connection Establishment Timing parameters"
  */
 #define BT_LE_ADV_CONN_FAST_2                                                                      \
 	BT_LE_ADV_PARAM(BT_LE_ADV_OPT_CONN, BT_GAP_ADV_FAST_INT_MIN_2, BT_GAP_ADV_FAST_INT_MAX_2,  \
@@ -1319,9 +1437,10 @@ struct bt_le_per_adv_param {
 /**
  * Helper to declare periodic advertising parameters inline
  *
- * @param _int_min     Minimum periodic advertising interval
- * @param _int_max     Maximum periodic advertising interval
- * @param _options     Periodic advertising properties bitfield.
+ * @param _int_min     Minimum periodic advertising interval, N * 0.625 milliseconds
+ * @param _int_max     Maximum periodic advertising interval, N * 0.625 milliseconds
+ * @param _options     Periodic advertising properties bitfield, see @ref bt_le_adv_opt
+ *                     field.
  */
 #define BT_LE_PER_ADV_PARAM_INIT(_int_min, _int_max, _options) \
 { \
@@ -1333,9 +1452,10 @@ struct bt_le_per_adv_param {
 /**
  * Helper to declare periodic advertising parameters inline
  *
- * @param _int_min     Minimum periodic advertising interval
- * @param _int_max     Maximum periodic advertising interval
- * @param _options     Periodic advertising properties bitfield.
+ * @param _int_min     Minimum periodic advertising interval, N * 0.625 milliseconds
+ * @param _int_max     Maximum periodic advertising interval, N * 0.625 milliseconds
+ * @param _options     Periodic advertising properties bitfield, see @ref bt_le_adv_opt
+ *                     field.
  */
 #define BT_LE_PER_ADV_PARAM(_int_min, _int_max, _options) \
 	((struct bt_le_per_adv_param[]) { \
@@ -1422,26 +1542,63 @@ int bt_le_ext_adv_create(const struct bt_le_adv_param *param,
 			 const struct bt_le_ext_adv_cb *cb,
 			 struct bt_le_ext_adv **adv);
 
+/**
+ * @brief Parameters for starting an extended advertising session.
+ *
+ * @details This struct provides the parameters to control the behavior of an extended advertising
+ * session, including the timeout and the number of advertising events to send. The timeout is
+ * specified in units of 10 ms, and the number of events determines how many times the advertising
+ * will be sent before stopping. If either the timeout or number of events is reached, the
+ * advertising session will be stopped, and the application will be notified via the advertiser sent
+ * callback. If both parameters are provided, the advertising session will stop when either limit is
+ * reached.
+ *
+ * @note Used in @ref bt_le_ext_adv_start function.
+ */
 struct bt_le_ext_adv_start_param {
 	/**
-	 * @brief Advertiser timeout (N * 10 ms).
+	 * @brief Maximum advertising set duration (N * 10 ms)
 	 *
-	 * Application will be notified by the advertiser sent callback.
-	 * Set to zero for no timeout.
+	 * The advertising set can be automatically disabled after a
+	 * certain amount of time has passed since it first appeared on
+	 * air.
 	 *
-	 * When using high duty cycle directed connectable advertising then
-	 * this parameters must be set to a non-zero value less than or equal
-	 * to the maximum of @ref BT_GAP_ADV_HIGH_DUTY_CYCLE_MAX_TIMEOUT.
+	 * Set to zero for no limit. Set in units of 10 ms.
 	 *
-	 * If privacy @kconfig{CONFIG_BT_PRIVACY} is enabled then the timeout
-	 * must be less than @kconfig{CONFIG_BT_RPA_TIMEOUT}.
+	 * When the advertising set is automatically disabled because of
+	 * this limit, @ref bt_le_ext_adv_cb.sent will be called.
+	 *
+	 * When using high duty cycle directed connectable advertising
+	 * then this parameters must be set to a non-zero value less
+	 * than or equal to the maximum of
+	 * @ref BT_GAP_ADV_HIGH_DUTY_CYCLE_MAX_TIMEOUT.
+	 *
+	 * If privacy @kconfig{CONFIG_BT_PRIVACY} is enabled then the
+	 * timeout must be less than @kconfig{CONFIG_BT_RPA_TIMEOUT}.
+	 *
+	 * For background information, see parameter "Duration" in
+	 * Bluetooth Core Specification Version 6.0 Vol. 4 Part E,
+	 * Section 7.8.56.
 	 */
 	uint16_t timeout;
+
 	/**
-	 * @brief Number of advertising events.
+	 * @brief Maximum number of extended advertising events to be
+	 * sent
+	 *
+	 * The advertiser can be automatically disabled once the whole
+	 * advertisement (i.e. extended advertising event) has been sent
+	 * a certain number of times. The number of advertising PDUs
+	 * sent may be higher and is not relevant.
 	 *
-	 * Application will be notified by the advertiser sent callback.
 	 * Set to zero for no limit.
+	 *
+	 * When the advertising set is automatically disabled because of
+	 * this limit, @ref bt_le_ext_adv_cb.sent will be called.
+	 *
+	 * For background information, see parameter
+	 * "Max_Extended_Advertising_Events" in Bluetooth Core
+	 * Specification Version 6.0 Vol. 4 Part E, Section 7.8.56.
 	 */
 	uint8_t  num_events;
 };
@@ -1556,7 +1713,7 @@ uint8_t bt_le_ext_adv_get_index(struct bt_le_ext_adv *adv);
 
 /** @brief Advertising set info structure. */
 struct bt_le_ext_adv_info {
-	/* Local identity */
+	/** Local identity handle. */
 	uint8_t                    id;
 
 	/** Currently selected Transmit Power (dBM). */
@@ -1587,7 +1744,7 @@ int bt_le_ext_adv_get_info(const struct bt_le_ext_adv *adv,
  * @param addr Advertiser LE address and type.
  * @param rssi Strength of advertiser signal.
  * @param adv_type Type of advertising response from advertiser.
- *                 Uses the BT_GAP_ADV_TYPE_* values.
+ *                 Uses the @ref bt_gap_adv_type values.
  * @param buf Buffer containing advertiser data.
  */
 typedef void bt_le_scan_cb_t(const bt_addr_le_t *addr, int8_t rssi,
@@ -1624,6 +1781,16 @@ int bt_le_per_adv_set_param(struct bt_le_ext_adv *adv,
 int bt_le_per_adv_set_data(const struct bt_le_ext_adv *adv,
 			   const struct bt_data *ad, size_t ad_len);
 
+/**
+ * @brief Parameters for setting data for a specific periodic advertising with response subevent.
+ *
+ * @details This struct provides the necessary information to set the data for a specific subevent
+ * in a Periodic Advertising with Response (PAwR) scenario. It specifies the subevent number, the
+ * range of response slots to listen to, and the actual data to send. This is used to respond to
+ * data request from an advertiser by sending back the data in the specified subevent.
+ *
+ * @note Used in @ref bt_le_per_adv_set_subevent_data function.
+ */
 struct bt_le_per_adv_subevent_data_params {
 	/** The subevent to set data for */
 	uint8_t subevent;
@@ -1665,8 +1832,8 @@ int bt_le_per_adv_set_subevent_data(const struct bt_le_ext_adv *adv, uint8_t num
  * periodic advertising and extended advertising can be enabled in any order.
  *
  * Once periodic advertising has been enabled, it will continue advertising
- * until @ref bt_le_per_adv_stop() has been called, or if the advertising set
- * is deleted by @ref bt_le_ext_adv_delete(). Calling @ref bt_le_ext_adv_stop()
+ * until @ref bt_le_per_adv_stop function has been called, or if the advertising set
+ * is deleted by @ref bt_le_ext_adv_delete function. Calling @ref bt_le_ext_adv_stop function
  * will not stop the periodic advertising.
  *
  * @param adv      Advertising set object.
@@ -1688,6 +1855,18 @@ int bt_le_per_adv_start(struct bt_le_ext_adv *adv);
  */
 int bt_le_per_adv_stop(struct bt_le_ext_adv *adv);
 
+/**
+ * @brief Information about the successful synchronization with periodic advertising.
+ *
+ * @details This struct provides information about the periodic advertising sync once it has been
+ * successfully established. It includes the advertiser's address, SID, the advertising interval,
+ * PHY, and the synchronization state. It also contains details about the sync, such as service data
+ * and the peer device that transferred the sync.
+ * When using periodic advertising response (configured via @kconfig{CONFIG_BT_PER_ADV_SYNC_RSP}),
+ * additional details such as subevent information and response timings are provided.
+ *
+ * @note Used in @ref bt_le_per_adv_sync_cb structure.
+ */
 struct bt_le_per_adv_sync_synced_info {
 	/** Advertiser LE address and type. */
 	const bt_addr_le_t *addr;
@@ -1734,6 +1913,16 @@ struct bt_le_per_adv_sync_synced_info {
 #endif /* CONFIG_BT_PER_ADV_SYNC_RSP */
 };
 
+/**
+ * @brief Information about the termination of a periodic advertising sync.
+ *
+ * @details This struct provides information about the termination of a periodic advertising sync.
+ * It includes the advertiser’s address and SID, along with the reason for the sync termination.
+ * This information is provided in the callback when the sync is terminated, either due to a
+ * local or remote request, or due to missing data (e.g., out of range or lost sync).
+ *
+ * @note Used in @ref bt_le_per_adv_sync_cb structure.
+ */
 struct bt_le_per_adv_sync_term_info {
 	/** Advertiser LE address and type. */
 	const bt_addr_le_t *addr;
@@ -1745,6 +1934,17 @@ struct bt_le_per_adv_sync_term_info {
 	uint8_t reason;
 };
 
+/**
+ * @brief Information about a received periodic advertising report.
+ *
+ * @details This struct holds information about a periodic advertising event that has been received.
+ * It contains details such as the advertiser’s address, SID, transmit power, RSSI, CTE type, and
+ * additional information depending on the configuration (e.g., event counter and subevent in case
+ * of a subevent indication). This information is provided in the callback when periodic advertising
+ * data is received.
+ *
+ * @note Used in @ref bt_le_per_adv_sync_cb structure.
+ */
 struct bt_le_per_adv_sync_recv_info {
 	/** Advertiser LE address and type. */
 	const bt_addr_le_t *addr;
@@ -1769,12 +1969,29 @@ struct bt_le_per_adv_sync_recv_info {
 #endif /* CONFIG_BT_PER_ADV_SYNC_RSP */
 };
 
-
+/**
+ * @brief Information about the state of periodic advertising sync.
+ *
+ * @details This struct provides information about the current state of a periodic advertising sync.
+ * It indicates whether periodic advertising reception is enabled or not. It is typically used to
+ * report the state change via callbacks in the @ref bt_le_per_adv_sync_cb structure.
+ */
 struct bt_le_per_adv_sync_state_info {
 	/** True if receiving periodic advertisements, false otherwise. */
 	bool recv_enabled;
 };
 
+/**
+ * @brief Callback struct for periodic advertising sync events.
+ *
+ * @details This struct defines the callback functions that are invoked for various periodic
+ * advertising sync events. These include when the sync is successfully established, terminated,
+ * when data is received, state changes, BIG info reports, and IQ samples from the periodic
+ * advertising.
+ *
+ * @note Used in @ref bt_le_per_adv_sync_cb_register function.
+ */
+
 struct bt_le_per_adv_sync_cb {
 	/**
 	 * @brief The periodic advertising has been successfully synced.
@@ -1857,7 +2074,7 @@ struct bt_le_per_adv_sync_cb {
 };
 
 /** Periodic advertising sync options */
-enum {
+enum bt_le_per_adv_sync_opt {
 	/** Convenience value when no options are specified. */
 	BT_LE_PER_ADV_SYNC_OPT_NONE = 0,
 
@@ -1892,6 +2109,17 @@ enum {
 	BT_LE_PER_ADV_SYNC_OPT_SYNC_ONLY_CONST_TONE_EXT = BIT(6),
 };
 
+/**
+ * @brief Parameters for creating a periodic advertising sync object.
+ *
+ * @details This struct contains the parameters required to create a periodic advertising sync
+ * object, which allows the system to synchronize with periodic advertising reports from an
+ * advertiser. It includes the advertiser's address, SID, sync options, event skip, and
+ * synchronization timeout.
+ *
+ * @note bt_le_per_adv_sync_param is used as a parameter in the @ref bt_le_per_adv_sync_create
+ * function to configure synchronization behavior.
+ */
 struct bt_le_per_adv_sync_param {
 	/**
 	 * @brief Periodic Advertiser Address
@@ -2070,7 +2298,7 @@ int bt_le_per_adv_sync_recv_enable(struct bt_le_per_adv_sync *per_adv_sync);
 int bt_le_per_adv_sync_recv_disable(struct bt_le_per_adv_sync *per_adv_sync);
 
 /** Periodic Advertising Sync Transfer options */
-enum {
+enum bt_le_per_adv_sync_transfer_opt {
 	/** Convenience value when no options are specified. */
 	BT_LE_PER_ADV_SYNC_TRANSFER_OPT_NONE = 0,
 
@@ -2117,6 +2345,16 @@ enum {
 	BT_LE_PER_ADV_SYNC_TRANSFER_OPT_FILTER_DUPLICATES = BIT(5),
 };
 
+/**
+ * @brief Parameters for periodic advertising sync transfer.
+ *
+ * @details This struct defines the parameters for configuring periodic advertising sync transfers
+ * (PASTs). It includes settings for the maximum event skip, synchronization timeout, and options
+ * for sync transfer.
+ *
+ * @note Used in the @ref bt_le_per_adv_sync_transfer_subscribe function to configure sync transfer
+ * settings.
+ */
 struct bt_le_per_adv_sync_transfer_param {
 	/**
 	 * @brief Maximum event skip
@@ -2241,7 +2479,7 @@ int bt_le_per_adv_list_remove(const bt_addr_le_t *addr, uint8_t sid);
 int bt_le_per_adv_list_clear(void);
 
 
-enum {
+enum bt_le_scan_opt {
 	/** Convenience value when no options are specified. */
 	BT_LE_SCAN_OPT_NONE = 0,
 
@@ -2262,7 +2500,7 @@ enum {
 	BT_LE_SCAN_OPT_NO_1M = BIT(3),
 };
 
-enum {
+enum bt_le_scan_type {
 	/** Scan without requesting additional information from advertisers. */
 	BT_LE_SCAN_TYPE_PASSIVE = 0x00,
 
@@ -2278,7 +2516,7 @@ enum {
 
 /** LE scan parameters */
 struct bt_le_scan_param {
-	/** Scan type (BT_LE_SCAN_TYPE_ACTIVE or BT_LE_SCAN_TYPE_PASSIVE) */
+	/** Scan type. @ref BT_LE_SCAN_TYPE_ACTIVE or @ref BT_LE_SCAN_TYPE_PASSIVE. */
 	uint8_t  type;
 
 	/** Bit-field of scanning options. */
@@ -2349,7 +2587,7 @@ struct bt_le_scan_recv_info {
 	/**
 	 * @brief Advertising packet type.
 	 *
-	 * Uses the BT_GAP_ADV_TYPE_* value.
+	 * Uses the @ref bt_gap_adv_type value.
 	 *
 	 * May indicate that this is a scan response if the type is
 	 * @ref BT_GAP_ADV_TYPE_SCAN_RSP.
@@ -2359,7 +2597,7 @@ struct bt_le_scan_recv_info {
 	/**
 	 * @brief Advertising packet properties bitfield.
 	 *
-	 * Uses the BT_GAP_ADV_PROP_* values.
+	 * Uses the @ref bt_gap_adv_prop values.
 	 * May indicate that this is a scan response if the value contains the
 	 * @ref BT_GAP_ADV_PROP_SCAN_RESPONSE bit.
 	 *
@@ -2401,8 +2639,7 @@ struct bt_le_scan_cb {
 /**
  * @brief Initialize scan parameters
  *
- * @param _type     Scan Type, BT_LE_SCAN_TYPE_ACTIVE or
- *                  BT_LE_SCAN_TYPE_PASSIVE.
+ * @param _type     Scan Type, @ref BT_LE_SCAN_TYPE_ACTIVE or @ref BT_LE_SCAN_TYPE_PASSIVE.
  * @param _options  Scan options
  * @param _interval Scan Interval (N * 0.625 ms)
  * @param _window   Scan Window (N * 0.625 ms)
@@ -2421,8 +2658,7 @@ struct bt_le_scan_cb {
 /**
  * @brief Helper to declare scan parameters inline
  *
- * @param _type     Scan Type, BT_LE_SCAN_TYPE_ACTIVE or
- *                  BT_LE_SCAN_TYPE_PASSIVE.
+ * @param _type     Scan Type, @ref BT_LE_SCAN_TYPE_ACTIVE or @ref BT_LE_SCAN_TYPE_PASSIVE.
  * @param _options  Scan options
  * @param _interval Scan Interval (N * 0.625 ms)
  * @param _window   Scan Window (N * 0.625 ms)
@@ -2509,7 +2745,7 @@ BUILD_ASSERT(BT_GAP_SCAN_FAST_WINDOW == BT_GAP_SCAN_FAST_INTERVAL_MIN,
  *
  * @note The LE scanner by default does not use the Identity Address of the
  *       local device when @kconfig{CONFIG_BT_PRIVACY} is disabled. This is to
- *       prevent the active scanner from disclosing the identity information
+ *       prevent the active scanner from disclosing the identity address information
  *       when requesting additional information from advertisers.
  *       In order to enable directed advertiser reports then
  *       @kconfig{CONFIG_BT_SCAN_WITH_IDENTITY} must be enabled.
@@ -2643,7 +2879,7 @@ int bt_le_set_rpa_timeout(uint16_t new_rpa_timeout);
 /**
  * @brief Helper for parsing advertising (or EIR or OOB) data.
  *
- * A helper for parsing the basic data types used for Extended Inquiry
+ * A helper for parsing the basic AD Types used for Extended Inquiry
  * Response (EIR), Advertising Data (AD), and OOB data blocks. The most
  * common scenario is to call this helper on the advertising data
  * received in the callback that was given to bt_le_scan_start().
@@ -2698,12 +2934,12 @@ struct bt_le_oob {
  *       - Creating a connection in progress, wait for the connected callback.
  *      In addition when extended advertising @kconfig{CONFIG_BT_EXT_ADV} is
  *      not enabled or not supported by the controller:
- *       - Advertiser is enabled using a Random Static Identity Address for a
- *         different local identity.
- *       - The local identity conflicts with the local identity used by other
+ *       - Advertiser is enabled using a Random Static Identity Address as a
+ *         different local identity address.
+ *       - The local identity address conflicts with the local identity address used by other
  *         roles.
  *
- * @param[in]  id  Local identity, in most cases BT_ID_DEFAULT.
+ * @param[in]  id  Local identity handle, in most cases BT_ID_DEFAULT.
  * @param[out] oob LE OOB information
  *
  * @return Zero on success or error code otherwise, positive in case of
@@ -2741,7 +2977,7 @@ int bt_le_ext_adv_oob_get_local(struct bt_le_ext_adv *adv,
 /**
  * @brief Clear pairing information.
  *
- * @param id    Local identity (mostly just BT_ID_DEFAULT).
+ * @param id    Local identity handle (mostly just BT_ID_DEFAULT).
  * @param addr  Remote address, NULL or BT_ADDR_LE_ANY to clear all remote
  *              devices.
  *
@@ -2758,7 +2994,7 @@ struct bt_bond_info {
 /**
  * @brief Iterate through all existing bonds.
  *
- * @param id         Local identity (mostly just BT_ID_DEFAULT).
+ * @param id         Local identity handle (mostly just BT_ID_DEFAULT).
  * @param func       Function to call for each bond.
  * @param user_data  Data to pass to the callback function.
  */
@@ -2766,23 +3002,33 @@ void bt_foreach_bond(uint8_t id, void (*func)(const struct bt_bond_info *info,
 					   void *user_data),
 		     void *user_data);
 
-/** @brief Configure vendor data path
+/**
+ * @brief Configure vendor data path
  *
- *  Request the Controller to configure the data transport path in a given direction between
- *  the Controller and the Host.
+ * @details Request the Controller to configure the data transport path in a given direction between
+ * the Controller and the Host.
  *
- *  @param dir            Direction to be configured, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR or
+ * @param dir            Direction to be configured, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR or
  *                        BT_HCI_DATAPATH_DIR_CTLR_TO_HOST
- *  @param id             Vendor specific logical transport channel ID, range
+ * @param id             Vendor specific logical transport channel ID, range
  *                        [BT_HCI_DATAPATH_ID_VS..BT_HCI_DATAPATH_ID_VS_END]
- *  @param vs_config_len  Length of additional vendor specific configuration data
- *  @param vs_config      Pointer to additional vendor specific configuration data
+ * @param vs_config_len  Length of additional vendor specific configuration data
+ * @param vs_config      Pointer to additional vendor specific configuration data
  *
- *  @return 0 in case of success or negative value in case of error.
+ * @return 0 in case of success or negative value in case of error.
  */
 int bt_configure_data_path(uint8_t dir, uint8_t id, uint8_t vs_config_len,
 			   const uint8_t *vs_config);
 
+/**
+ * @brief Parameters for synchronizing with specific periodic advertising subevents.
+ *
+ * @details This struct contains the parameters used to synchronize with a subset of subevents in
+ * periodic advertising. It includes the periodic advertising properties, the number of subevents
+ * to sync to, and the list of subevents that the controller should synchronize with.
+ *
+ * @note Used in @ref bt_le_per_adv_sync_subevent function to control synchronization.
+ */
 struct bt_le_per_adv_sync_subevent_params {
 	/** @brief Periodic Advertising Properties.
 	 *
@@ -2815,8 +3061,17 @@ struct bt_le_per_adv_sync_subevent_params {
 int bt_le_per_adv_sync_subevent(struct bt_le_per_adv_sync *per_adv_sync,
 				struct bt_le_per_adv_sync_subevent_params *params);
 
+/**
+ * @brief Parameters for sending a periodic advertising response.
+ *
+ * @details This struct contains the parameters used when sending a response to a periodic
+ * advertising request (see @ref bt_le_per_adv_set_response_data function). The response is sent
+ * in the specified subevent and response slot, and includes event and subevent counters
+ * to track the request the response corresponds to.
+ */
 struct bt_le_per_adv_response_params {
-	/** @brief The periodic event counter of the request the response is sent to.
+	/**
+	 * @brief The periodic event counter of the request the response is sent to.
 	 *
 	 * @ref bt_le_per_adv_sync_recv_info
 	 *
@@ -2826,7 +3081,8 @@ struct bt_le_per_adv_response_params {
 	 */
 	uint16_t request_event;
 
-	/** @brief The subevent counter of the request the response is sent to.
+	/**
+	 * @brief The subevent counter of the request the response is sent to.
 	 *
 	 * @ref bt_le_per_adv_sync_recv_info
 	 *
@@ -2856,6 +3112,19 @@ int bt_le_per_adv_set_response_data(struct bt_le_per_adv_sync *per_adv_sync,
 				    const struct bt_le_per_adv_response_params *params,
 				    const struct net_buf_simple *data);
 
+/**
+ * @brief Check if a device identified by a Bluetooth LE address is bonded.
+ *
+ * @details Valid Bluetooth LE identity addresses are either public address or random static
+ * address.
+ *
+ * @param id   Local identity handle (typically @ref BT_ID_DEFAULT).
+ * @param addr Bluetooth LE device address.
+ *
+ * @return true if @p addr is bonded with local @p id
+ */
+bool bt_le_bond_exists(uint8_t id, const bt_addr_le_t *addr);
+
 /**
  * @}
  */
diff --git a/include/zephyr/bluetooth/buf.h b/include/zephyr/bluetooth/buf.h
index dd452342ef7..a5d0ec4fe8e 100644
--- a/include/zephyr/bluetooth/buf.h
+++ b/include/zephyr/bluetooth/buf.h
@@ -18,11 +18,17 @@
  * @{
  */
 
+#include <stddef.h>
 #include <stdint.h>
 
-#include <zephyr/net_buf.h>
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/net_buf.h>
 #include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/toolchain.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -97,13 +103,13 @@ struct bt_buf_data {
   * available for the HCI driver to allocate from.
   *
   * TODO: When CONFIG_BT_BUF_ACL_RX_COUNT is removed,
-  *       remove the MAX and only keep (CONFIG_BT_MAX_CONN + 1)
+  *       remove the MAX and only keep the 1.
   */
-#define BT_BUF_ACL_RX_COUNT                                                                        \
-	(MAX(CONFIG_BT_BUF_ACL_RX_COUNT, (CONFIG_BT_MAX_CONN + 1)) +                               \
-	 CONFIG_BT_BUF_ACL_RX_COUNT_EXTRA)
+#define BT_BUF_ACL_RX_COUNT_EXTRA CONFIG_BT_BUF_ACL_RX_COUNT_EXTRA
+#define BT_BUF_ACL_RX_COUNT       (MAX(CONFIG_BT_BUF_ACL_RX_COUNT, 1) + BT_BUF_ACL_RX_COUNT_EXTRA)
 #else
-#define BT_BUF_ACL_RX_COUNT 0
+#define BT_BUF_ACL_RX_COUNT_EXTRA 0
+#define BT_BUF_ACL_RX_COUNT       0
 #endif /* CONFIG_BT_CONN && CONFIG_BT_HCI_HOST */
 
 #if defined(CONFIG_BT_BUF_ACL_RX_COUNT) && CONFIG_BT_BUF_ACL_RX_COUNT > 0
@@ -117,10 +123,15 @@ BUILD_ASSERT(BT_BUF_ACL_RX_COUNT <= BT_BUF_ACL_RX_COUNT_MAX,
 #define BT_BUF_RX_SIZE (MAX(MAX(BT_BUF_ACL_RX_SIZE, BT_BUF_EVT_RX_SIZE), \
 			    BT_BUF_ISO_RX_SIZE))
 
-/** Buffer count needed for HCI ACL, HCI ISO or Event RX buffers */
-#define BT_BUF_RX_COUNT (MAX(MAX(CONFIG_BT_BUF_EVT_RX_COUNT, \
-				 BT_BUF_ACL_RX_COUNT), \
-			     BT_BUF_ISO_RX_COUNT))
+/* Controller can generate up to CONFIG_BT_BUF_ACL_TX_COUNT number of unique HCI Number of Completed
+ * Packets events.
+ */
+BUILD_ASSERT(CONFIG_BT_BUF_EVT_RX_COUNT > CONFIG_BT_BUF_ACL_TX_COUNT,
+	     "Increase Event RX buffer count to be greater than ACL TX buffer count");
+
+/** Buffer count needed for HCI ACL or HCI ISO plus Event RX buffers */
+#define BT_BUF_RX_COUNT (CONFIG_BT_BUF_EVT_RX_COUNT + \
+			 MAX(BT_BUF_ACL_RX_COUNT, BT_BUF_ISO_RX_COUNT))
 
 /** Data size needed for HCI Command buffers. */
 #define BT_BUF_CMD_TX_SIZE BT_BUF_CMD_SIZE(CONFIG_BT_BUF_CMD_TX_SIZE)
diff --git a/include/zephyr/bluetooth/classic/a2dp.h b/include/zephyr/bluetooth/classic/a2dp.h
index 95b1899cebc..32329b61453 100644
--- a/include/zephyr/bluetooth/classic/a2dp.h
+++ b/include/zephyr/bluetooth/classic/a2dp.h
@@ -341,7 +341,7 @@ struct bt_a2dp_ep_info {
 	/** Codec capabilities, if SBC, use function of a2dp_codec_sbc.h to parse it */
 	struct bt_a2dp_codec_ie codec_cap;
 	/** Stream End Point Information */
-	struct bt_avdtp_sep_info sep_info;
+	struct bt_avdtp_sep_info *sep_info;
 };
 
 /** @brief Helper enum to be used as return value of bt_a2dp_discover_ep_cb.
diff --git a/include/zephyr/bluetooth/classic/avrcp.h b/include/zephyr/bluetooth/classic/avrcp.h
index 4c422570fb6..dff804970c5 100644
--- a/include/zephyr/bluetooth/classic/avrcp.h
+++ b/include/zephyr/bluetooth/classic/avrcp.h
@@ -16,6 +16,125 @@
 extern "C" {
 #endif
 
+#define BT_AVRCP_COMPANY_ID_SIZE          (3)
+#define BT_AVRCP_COMPANY_ID_BLUETOOTH_SIG (0x001958)
+
+/** @brief AVRCP Capability ID */
+typedef enum __packed {
+	BT_AVRCP_CAP_COMPANY_ID = 0x2,
+	BT_AVRCP_CAP_EVENTS_SUPPORTED = 0x3,
+} bt_avrcp_cap_t;
+
+/** @brief AVRCP Notification Events */
+typedef enum __packed {
+	BT_AVRCP_EVT_PLAYBACK_STATUS_CHANGED = 0x01,
+	BT_AVRCP_EVT_TRACK_CHANGED = 0x02,
+	BT_AVRCP_EVT_TRACK_REACHED_END = 0x03,
+	BT_AVRCP_EVT_TRACK_REACHED_START = 0x04,
+	BT_AVRCP_EVT_PLAYBACK_POS_CHANGED = 0x05,
+	BT_AVRCP_EVT_BATT_STATUS_CHANGED = 0x06,
+	BT_AVRCP_EVT_SYSTEM_STATUS_CHANGED = 0x07,
+	BT_AVRCP_EVT_PLAYER_APP_SETTING_CHANGED = 0x08,
+	BT_AVRCP_EVT_NOW_PLAYING_CONTENT_CHANGED = 0x09,
+	BT_AVRCP_EVT_AVAILABLE_PLAYERS_CHANGED = 0x0a,
+	BT_AVRCP_EVT_ADDRESSED_PLAYER_CHANGED = 0x0b,
+	BT_AVRCP_EVT_UIDS_CHANGED = 0x0c,
+	BT_AVRCP_EVT_VOLUME_CHANGED = 0x0d,
+} bt_avrcp_evt_t;
+
+/** @brief AV/C command types */
+typedef enum __packed {
+	BT_AVRCP_CTYPE_CONTROL = 0x0,
+	BT_AVRCP_CTYPE_STATUS = 0x1,
+	BT_AVRCP_CTYPE_SPECIFIC_INQUIRY = 0x2,
+	BT_AVRCP_CTYPE_NOTIFY = 0x3,
+	BT_AVRCP_CTYPE_GENERAL_INQUIRY = 0x4,
+} bt_avrcp_ctype_t;
+
+/** @brief AV/C response codes */
+typedef enum __packed {
+	BT_AVRCP_RSP_NOT_IMPLEMENTED = 0x8,
+	BT_AVRCP_RSP_ACCEPTED = 0x9,
+	BT_AVRCP_RSP_REJECTED = 0xa,
+	BT_AVRCP_RSP_IN_TRANSITION = 0xb,
+	BT_AVRCP_RSP_IMPLEMENTED = 0xc, /**< For SPECIFIC_INQUIRY and GENERAL_INQUIRY commands */
+	BT_AVRCP_RSP_STABLE = 0xc,      /**< For STATUS commands */
+	BT_AVRCP_RSP_CHANGED = 0xd,
+	BT_AVRCP_RSP_INTERIM = 0xf,
+} bt_avrcp_rsp_t;
+
+/** @brief AV/C operation ids used in AVRCP passthrough commands */
+typedef enum __packed {
+	BT_AVRCP_OPID_SELECT = 0x00,
+	BT_AVRCP_OPID_UP = 0x01,
+	BT_AVRCP_OPID_DOWN = 0x02,
+	BT_AVRCP_OPID_LEFT = 0x03,
+	BT_AVRCP_OPID_RIGHT = 0x04,
+	BT_AVRCP_OPID_RIGHT_UP = 0x05,
+	BT_AVRCP_OPID_RIGHT_DOWN = 0x06,
+	BT_AVRCP_OPID_LEFT_UP = 0x07,
+	BT_AVRCP_OPID_LEFT_DOWN = 0x08,
+	BT_AVRCP_OPID_ROOT_MENU = 0x09,
+	BT_AVRCP_OPID_SETUP_MENU = 0x0a,
+	BT_AVRCP_OPID_CONTENTS_MENU = 0x0b,
+	BT_AVRCP_OPID_FAVORITE_MENU = 0x0c,
+	BT_AVRCP_OPID_EXIT = 0x0d,
+
+	BT_AVRCP_OPID_0 = 0x20,
+	BT_AVRCP_OPID_1 = 0x21,
+	BT_AVRCP_OPID_2 = 0x22,
+	BT_AVRCP_OPID_3 = 0x23,
+	BT_AVRCP_OPID_4 = 0x24,
+	BT_AVRCP_OPID_5 = 0x25,
+	BT_AVRCP_OPID_6 = 0x26,
+	BT_AVRCP_OPID_7 = 0x27,
+	BT_AVRCP_OPID_8 = 0x28,
+	BT_AVRCP_OPID_9 = 0x29,
+	BT_AVRCP_OPID_DOT = 0x2a,
+	BT_AVRCP_OPID_ENTER = 0x2b,
+	BT_AVRCP_OPID_CLEAR = 0x2c,
+
+	BT_AVRCP_OPID_CHANNEL_UP = 0x30,
+	BT_AVRCP_OPID_CHANNEL_DOWN = 0x31,
+	BT_AVRCP_OPID_PREVIOUS_CHANNEL = 0x32,
+	BT_AVRCP_OPID_SOUND_SELECT = 0x33,
+	BT_AVRCP_OPID_INPUT_SELECT = 0x34,
+	BT_AVRCP_OPID_DISPLAY_INFORMATION = 0x35,
+	BT_AVRCP_OPID_HELP = 0x36,
+	BT_AVRCP_OPID_PAGE_UP = 0x37,
+	BT_AVRCP_OPID_PAGE_DOWN = 0x38,
+
+	BT_AVRCP_OPID_POWER = 0x40,
+	BT_AVRCP_OPID_VOLUME_UP = 0x41,
+	BT_AVRCP_OPID_VOLUME_DOWN = 0x42,
+	BT_AVRCP_OPID_MUTE = 0x43,
+	BT_AVRCP_OPID_PLAY = 0x44,
+	BT_AVRCP_OPID_STOP = 0x45,
+	BT_AVRCP_OPID_PAUSE = 0x46,
+	BT_AVRCP_OPID_RECORD = 0x47,
+	BT_AVRCP_OPID_REWIND = 0x48,
+	BT_AVRCP_OPID_FAST_FORWARD = 0x49,
+	BT_AVRCP_OPID_EJECT = 0x4a,
+	BT_AVRCP_OPID_FORWARD = 0x4b,
+	BT_AVRCP_OPID_BACKWARD = 0x4c,
+
+	BT_AVRCP_OPID_ANGLE = 0x50,
+	BT_AVRCP_OPID_SUBPICTURE = 0x51,
+
+	BT_AVRCP_OPID_F1 = 0x71,
+	BT_AVRCP_OPID_F2 = 0x72,
+	BT_AVRCP_OPID_F3 = 0x73,
+	BT_AVRCP_OPID_F4 = 0x74,
+	BT_AVRCP_OPID_F5 = 0x75,
+	BT_AVRCP_OPID_VENDOR_UNIQUE = 0x7e,
+} bt_avrcp_opid_t;
+
+/** @brief AVRCP button state flag */
+typedef enum __packed {
+	BT_AVRCP_BUTTON_PRESSED = 0,
+	BT_AVRCP_BUTTON_RELEASED = 1,
+} bt_avrcp_button_state_t;
+
 /** @brief AVRCP structure */
 struct bt_avrcp;
 
@@ -28,7 +147,24 @@ struct bt_avrcp_subunit_info_rsp {
 	uint8_t subunit_type;
 	uint8_t max_subunit_id;
 	const uint8_t *extended_subunit_type; /**< contains max_subunit_id items */
-	const uint8_t *extended_subunit_id; /**< contains max_subunit_id items */
+	const uint8_t *extended_subunit_id;   /**< contains max_subunit_id items */
+};
+
+#define BT_AVRCP_PASSTHROUGH_GET_STATE(payload)                                                    \
+	((bt_avrcp_button_state_t)(FIELD_GET(BIT(7), ((payload)->byte0))))
+#define BT_AVRCP_PASSTHROUGH_GET_OPID(payload)                                                     \
+	((bt_avrcp_opid_t)(FIELD_GET(GENMASK(6, 0), ((payload)->byte0))))
+
+struct bt_avrcp_passthrough_rsp {
+	uint8_t byte0; /**< [7]: state_flag, [6:0]: opid */
+	uint8_t data_len;
+	uint8_t data[];
+};
+
+struct bt_avrcp_get_cap_rsp {
+	uint8_t cap_id;  /**< bt_avrcp_cap_t */
+	uint8_t cap_cnt; /**< number of items contained in *cap */
+	uint8_t cap[];   /**< 1 or 3 octets each depends on cap_id */
 };
 
 struct bt_avrcp_cb {
@@ -40,6 +176,7 @@ struct bt_avrcp_cb {
 	 *  @param avrcp AVRCP connection object.
 	 */
 	void (*connected)(struct bt_avrcp *avrcp);
+
 	/** @brief An AVRCP connection has been disconnected.
 	 *
 	 *  This callback notifies the application that an avrcp connection
@@ -48,22 +185,51 @@ struct bt_avrcp_cb {
 	 *  @param avrcp AVRCP connection object.
 	 */
 	void (*disconnected)(struct bt_avrcp *avrcp);
+
+	/** @brief Callback function for bt_avrcp_get_cap().
+	 *
+	 *  Called when the get capabilities process is completed.
+	 *
+	 *  @param avrcp AVRCP connection object.
+	 *  @param tid The transaction label of the response.
+	 *  @param rsp The response for Get Capabilities command.
+	 */
+	void (*get_cap_rsp)(struct bt_avrcp *avrcp, uint8_t tid,
+			    const struct bt_avrcp_get_cap_rsp *rsp);
+
 	/** @brief Callback function for bt_avrcp_get_unit_info().
 	 *
 	 *  Called when the get unit info process is completed.
 	 *
 	 *  @param avrcp AVRCP connection object.
+	 *  @param tid The transaction label of the response.
 	 *  @param rsp The response for UNIT INFO command.
 	 */
-	void (*unit_info_rsp)(struct bt_avrcp *avrcp, struct bt_avrcp_unit_info_rsp *rsp);
+	void (*unit_info_rsp)(struct bt_avrcp *avrcp, uint8_t tid,
+			      struct bt_avrcp_unit_info_rsp *rsp);
+
 	/** @brief Callback function for bt_avrcp_get_subunit_info().
 	 *
 	 *  Called when the get subunit info process is completed.
 	 *
 	 *  @param avrcp AVRCP connection object.
+	 *  @param tid The transaction label of the response.
 	 *  @param rsp The response for SUBUNIT INFO command.
 	 */
-	void (*subunit_info_rsp)(struct bt_avrcp *avrcp, struct bt_avrcp_subunit_info_rsp *rsp);
+	void (*subunit_info_rsp)(struct bt_avrcp *avrcp, uint8_t tid,
+				 struct bt_avrcp_subunit_info_rsp *rsp);
+
+	/** @brief Callback function for bt_avrcp_passthrough().
+	 *
+	 *  Called when a passthrough response is received.
+	 *
+	 *  @param avrcp AVRCP connection object.
+	 *  @param tid The transaction label of the response.
+	 *  @param result The result of the operation.
+	 *  @param rsp The response for PASS THROUGH command.
+	 */
+	void (*passthrough_rsp)(struct bt_avrcp *avrcp, uint8_t tid, bt_avrcp_rsp_t result,
+				const struct bt_avrcp_passthrough_rsp *rsp);
 };
 
 /** @brief Connect AVRCP.
@@ -99,15 +265,28 @@ int bt_avrcp_disconnect(struct bt_avrcp *avrcp);
  */
 int bt_avrcp_register_cb(const struct bt_avrcp_cb *cb);
 
+/** @brief Get AVRCP Capabilities.
+ *
+ *  This function gets the capabilities supported by remote device.
+ *
+ *  @param avrcp The AVRCP instance.
+ *  @param tid The transaction label of the response, valid from 0 to 15.
+ *  @param cap_id Specific capability requested, see @ref bt_avrcp_cap_t.
+ *
+ *  @return 0 in case of success or error code in case of error.
+ */
+int bt_avrcp_get_cap(struct bt_avrcp *avrcp, uint8_t tid, uint8_t cap_id);
+
 /** @brief Get AVRCP Unit Info.
  *
  *  This function obtains information that pertains to the AV/C unit as a whole.
  *
  *  @param avrcp The AVRCP instance.
+ *  @param tid The transaction label of the response, valid from 0 to 15.
  *
  *  @return 0 in case of success or error code in case of error.
  */
-int bt_avrcp_get_unit_info(struct bt_avrcp *avrcp);
+int bt_avrcp_get_unit_info(struct bt_avrcp *avrcp, uint8_t tid);
 
 /** @brief Get AVRCP Subunit Info.
  *
@@ -115,10 +294,28 @@ int bt_avrcp_get_unit_info(struct bt_avrcp *avrcp);
  *  may support other subunits than the panel subunit if other profiles co-exist in the device.
  *
  *  @param avrcp The AVRCP instance.
+ *  @param tid The transaction label of the response, valid from 0 to 15.
+ *
+ *  @return 0 in case of success or error code in case of error.
+ */
+int bt_avrcp_get_subunit_info(struct bt_avrcp *avrcp, uint8_t tid);
+
+/** @brief Send AVRCP Pass Through command.
+ *
+ *  This function send a pass through command to the remote device. Passsthhrough command is used
+ *  to transfer user operation information from a CT to Panel subunit of TG.
+ *
+ *  @param avrcp The AVRCP instance.
+ *  @param tid The transaction label of the response, valid from 0 to 15.
+ *  @param opid The user operation id, see @ref bt_avrcp_opid_t.
+ *  @param state The button state, see @ref bt_avrcp_button_state_t.
+ *  @param payload The payload of the pass through command. Should not be NULL if len is not zero.
+ *  @param len The length of the payload.
  *
  *  @return 0 in case of success or error code in case of error.
  */
-int bt_avrcp_get_subunit_info(struct bt_avrcp *avrcp);
+int bt_avrcp_passthrough(struct bt_avrcp *avrcp, uint8_t tid, uint8_t opid, uint8_t state,
+			 const uint8_t *payload, uint8_t len);
 
 #ifdef __cplusplus
 }
diff --git a/include/zephyr/bluetooth/classic/classic.h b/include/zephyr/bluetooth/classic/classic.h
index be7cf8dc404..0aeec12d3b2 100644
--- a/include/zephyr/bluetooth/classic/classic.h
+++ b/include/zephyr/bluetooth/classic/classic.h
@@ -48,9 +48,12 @@ struct bt_br_discovery_priv {
 	/** Page scan repetition mode */
 	uint8_t pscan_rep_mode;
 	/** Resolving remote name*/
-	bool resolving;
+	uint8_t resolve_state;
 };
 
+/** Maximum size of Extended Inquiry Response */
+#define BT_BR_EIR_SIZE_MAX 240
+
 /** @brief BR/EDR discovery result structure */
 struct bt_br_discovery_result {
 	/** Private data */
@@ -66,7 +69,7 @@ struct bt_br_discovery_result {
 	uint8_t cod[3];
 
 	/** Extended Inquiry Response */
-	uint8_t eir[240];
+	uint8_t eir[BT_BR_EIR_SIZE_MAX];
 };
 
 /** BR/EDR discovery parameters */
@@ -175,12 +178,17 @@ int bt_br_oob_get_local(struct bt_br_oob *oob);
  * to devices making general inquiry. To enable this state it's mandatory
  * to first be in connectable state.
  *
+ * If the device enters limited discoverable mode, the controller will leave from discoverable
+ * mode after the duration of @kconfig{BT_LIMITED_DISCOVERABLE_DURATION} seconds in the limited
+ * discoverable mode.
+ *
  * @param enable Value allowing/disallowing controller to become discoverable.
+ * @param limited Value allowing/disallowing controller to enter limited discoverable mode.
  *
  * @return Negative if fail set to requested state or requested state has been
  *         already set. Zero if done successfully.
  */
-int bt_br_set_discoverable(bool enable);
+int bt_br_set_discoverable(bool enable, bool limited);
 
 /**
  * @brief Enable/disable set controller in connectable state.
@@ -196,6 +204,38 @@ int bt_br_set_discoverable(bool enable);
  */
 int bt_br_set_connectable(bool enable);
 
+/** @brief Check if a Bluetooth classic device address is bonded.
+ *
+ *  @param addr Bluetooth classic device address.
+ *
+ *  @return true if @p addr is bonded
+ */
+bool bt_br_bond_exists(const bt_addr_t *addr);
+
+/**
+ * @brief Clear classic pairing information .
+ *
+ * @param addr  Remote address, NULL or BT_ADDR_ANY to clear all remote devices.
+ *
+ * @return 0 on success or negative error value on failure.
+ */
+int bt_br_unpair(const bt_addr_t *addr);
+
+/** Information about a bond with a remote device. */
+struct bt_br_bond_info {
+	/** Address of the remote device. */
+	bt_addr_t addr;
+};
+
+/**
+ * @brief Iterate through all existing bonds of Classic.
+ *
+ * @param func       Function to call for each bond.
+ * @param user_data  Data to pass to the callback function.
+ */
+void bt_br_foreach_bond(void (*func)(const struct bt_br_bond_info *info, void *user_data),
+			void *user_data);
+
 /**
  * @}
  */
diff --git a/include/zephyr/bluetooth/classic/hfp_ag.h b/include/zephyr/bluetooth/classic/hfp_ag.h
index 6e5173d9fa4..9f936bef923 100644
--- a/include/zephyr/bluetooth/classic/hfp_ag.h
+++ b/include/zephyr/bluetooth/classic/hfp_ag.h
@@ -42,6 +42,40 @@ enum bt_hfp_ag_indicator {
 #define BT_HFP_AG_CODEC_LC3_SWB 0x03
 
 struct bt_hfp_ag;
+struct bt_hfp_ag_call;
+
+/** @typedef bt_hfp_ag_query_subscriber_func_t
+ *  @brief Query subscriber number callback function
+ *
+ *  When AG wants to send subscriber number information, all information
+ *  will be passed through the callback. And the subscriber number
+ *  information will be sent out in this function.
+ *
+ *  @param ag HFP AG object.
+ *  @param number Subscriber number.
+ *  @param type Type of subscriber number specifies the format of the phone number provided,
+ *              and can be one of the following values:
+ *              - values 128-143: The phone number format may be a national or international
+ *                format, and may contain prefix and/or escape digits. No changes on the number
+ *                presentation are required.
+ *              - values 144-159: The phone number format is an international number, including
+ *                the country code prefix. If the plus sign ("+") is not included as part of the
+ *                number and shall be added by the AG as needed.
+ *              - values 160-175: National number. No prefix nor escape digits included.
+ *  @param service Service of subscriber number indicates which service this phone number relates
+ *                 to. Shall be either 4 (voice) or 5 (fax).
+ *
+ *  @return 0 if should continue to the next subscriber number information.
+ *  @return negative value to stop.
+ */
+typedef int (*bt_hfp_ag_query_subscriber_func_t)(struct bt_hfp_ag *ag, char *number, uint8_t type,
+						 uint8_t service);
+
+/* HF indicators */
+enum hfp_ag_hf_indicators {
+	HFP_AG_ENHANCED_SAFETY_IND = 1, /* Enhanced Safety */
+	HFP_AG_BATTERY_LEVEL_IND = 2,   /* Remaining level of Battery */
+};
 
 /** @brief HFP profile AG application callback */
 struct bt_hfp_ag_cb {
@@ -50,9 +84,10 @@ struct bt_hfp_ag_cb {
 	 *  If this callback is provided it will be called whenever the
 	 *  AG connection completes.
 	 *
+	 *  @param conn Connection object.
 	 *  @param ag HFP AG object.
 	 */
-	void (*connected)(struct bt_hfp_ag *ag);
+	void (*connected)(struct bt_conn *conn, struct bt_hfp_ag *ag);
 	/** HF disconnected callback to application
 	 *
 	 *  If this callback is provided it will be called whenever the
@@ -76,34 +111,51 @@ struct bt_hfp_ag_cb {
 	 *  If this callback is provided it will be called whenever the
 	 *  SCO/eSCO connection gets disconnected.
 	 *
-	 *  @param ag HFP AG object.
-	 *  @param sco_conn SCO/eSCO Connection object.
+	 *  @param conn SCO/eSCO Connection object.
+	 *  @param reason BT_HCI_ERR_* reason for the disconnection.
 	 */
-	void (*sco_disconnected)(struct bt_hfp_ag *ag);
+	void (*sco_disconnected)(struct bt_conn *sco_conn, uint8_t reason);
 
 	/** HF memory dialing request Callback
 	 *
 	 *  If this callback is provided it will be called whenever a
-	 *  new call is requested with memory dialing from HFP unit.
+	 *  new call is requested with memory dialing from HF.
 	 *  Get the phone number according to the given AG memory location.
 	 *
 	 *  @param ag HFP AG object.
 	 *  @param location AG memory location
-	 *  @param number Dailing number
+	 *  @param number Dialing number
 	 *
 	 *  @return 0 in case of success or negative value in case of error.
 	 */
 	int (*memory_dial)(struct bt_hfp_ag *ag, const char *location, char **number);
 
+	/** HF phone number calling request Callback
+	 *
+	 *  If this callback is provided it will be called whenever a
+	 *  new call is requested with specific phone number from HF.
+	 *  When the callback is triggered, the application needs to start
+	 *  dialing the number with the passed phone number.
+	 *  If the callback is invalid, the phone number dialing from HF
+	 *  cannot be supported.
+	 *
+	 *  @param ag HFP AG object.
+	 *  @param number Dialing number
+	 *
+	 *  @return 0 in case of success or negative value in case of error.
+	 */
+	int (*number_call)(struct bt_hfp_ag *ag, const char *number);
+
 	/** HF outgoing Callback
 	 *
 	 *  If this callback is provided it will be called whenever a
 	 *  new call is outgoing.
 	 *
 	 *  @param ag HFP AG object.
-	 *  @param number Dailing number
+	 *  @param call HFP AG call object.
+	 *  @param number Dialing number
 	 */
-	void (*outgoing)(struct bt_hfp_ag *ag, const char *number);
+	void (*outgoing)(struct bt_hfp_ag *ag, struct bt_hfp_ag_call *call, const char *number);
 
 	/** HF incoming Callback
 	 *
@@ -111,46 +163,74 @@ struct bt_hfp_ag_cb {
 	 *  new call is incoming.
 	 *
 	 *  @param ag HFP AG object.
+	 *  @param call HFP AG call object.
 	 *  @param number Incoming number
 	 */
-	void (*incoming)(struct bt_hfp_ag *ag, const char *number);
+	void (*incoming)(struct bt_hfp_ag *ag, struct bt_hfp_ag_call *call, const char *number);
+
+	/** HF incoming call is held Callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  incoming call is held but not accepted.
+	 *
+	 *  @param call HFP AG call object.
+	 */
+	void (*incoming_held)(struct bt_hfp_ag_call *call);
 
 	/** HF ringing Callback
 	 *
 	 *  If this callback is provided it will be called whenever the
 	 *  call is in the ringing
 	 *
-	 *  @param ag HFP AG object.
+	 *  @param call HFP AG call object.
 	 *  @param in_bond true - in-bond ringing, false - No in-bond ringing
 	 */
-	void (*ringing)(struct bt_hfp_ag *ag, bool in_band);
+	void (*ringing)(struct bt_hfp_ag_call *call, bool in_band);
 
 	/** HF call accept Callback
 	 *
 	 *  If this callback is provided it will be called whenever the
 	 *  call is accepted.
 	 *
-	 *  @param ag HFP AG object.
+	 *  @param call HFP AG call object.
+	 */
+	void (*accept)(struct bt_hfp_ag_call *call);
+
+	/** HF call held Callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  call is held.
+	 *
+	 *  @param call HFP AG call object.
 	 */
-	void (*accept)(struct bt_hfp_ag *ag);
+	void (*held)(struct bt_hfp_ag_call *call);
+
+	/** HF call retrieve Callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  call is retrieved.
+	 *
+	 *  @param call HFP AG call object.
+	 */
+	void (*retrieve)(struct bt_hfp_ag_call *call);
 
 	/** HF call reject Callback
 	 *
 	 *  If this callback is provided it will be called whenever the
 	 *  call is rejected.
 	 *
-	 *  @param ag HFP AG object.
+	 *  @param call HFP AG call object.
 	 */
-	void (*reject)(struct bt_hfp_ag *ag);
+	void (*reject)(struct bt_hfp_ag_call *call);
 
 	/** HF call terminate Callback
 	 *
 	 *  If this callback is provided it will be called whenever the
 	 *  call is terminated.
 	 *
-	 *  @param ag HFP AG object.
+	 *  @param call HFP AG call object.
 	 */
-	void (*terminate)(struct bt_hfp_ag *ag);
+	void (*terminate)(struct bt_hfp_ag_call *call);
 
 	/** Supported codec Ids callback
 	 *
@@ -160,6 +240,175 @@ struct bt_hfp_ag_cb {
 	 *  @param ag HFP AG object.
 	 */
 	void (*codec)(struct bt_hfp_ag *ag, uint32_t ids);
+
+	/** Codec negotiate callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  codec negotiation succeeded or failed.
+	 *
+	 *  @param ag HFP AG object.
+	 *  @param err Result of codec negotiation.
+	 */
+	void (*codec_negotiate)(struct bt_hfp_ag *ag, int err);
+
+	/** Audio connection request callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  audio conenction request is triggered by HF.
+	 *  When AT+BCC AT command received, it means the procedure of
+	 *  establishment of audio connection is triggered by HF.
+	 *  If the callback is provided by application, AG needs to
+	 *  start the codec connection procedure by calling
+	 *  function `bt_hfp_ag_audio_connect` in application layer.
+	 *  Or, the codec conenction procedure will be started with
+	 *  default codec id `BT_HFP_AG_CODEC_CVSD`.
+	 *
+	 *  @param ag HFP AG object.
+	 *  @param err Result of codec negotiation.
+	 */
+	void (*audio_connect_req)(struct bt_hfp_ag *ag);
+
+	/** HF VGM setting callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  VGM gain setting is informed from HF.
+	 *
+	 *  @param ag HFP AG object.
+	 *  @param gain HF microphone gain value.
+	 */
+	void (*vgm)(struct bt_hfp_ag *ag, uint8_t gain);
+
+	/** HF VGS setting callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  VGS gain setting is informed from HF.
+	 *
+	 *  @param ag HFP AG object.
+	 *  @param gain HF speaker gain value.
+	 */
+	void (*vgs)(struct bt_hfp_ag *ag, uint8_t gain);
+
+	/** HF ECNR turns off callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  ECNR turning off request is received from HF.
+	 *  If the callback is NULL or @kconfig{CONFIG_BT_HFP_AG_ECNR}
+	 *  is not enabled, the response result code of AT command
+	 *  will be an AT ERROR.
+	 *
+	 *  @param ag HFP AG object.
+	 */
+	void (*ecnr_turn_off)(struct bt_hfp_ag *ag);
+
+	/** HF explicit call transfer callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  AT+CHLD=4 is sent from HF.
+	 *  When the callback is notified, the application should connect
+	 *  the two calls and disconnects the subscriber from both calls
+	 *  (Explicit Call Transfer).
+	 *  After the callback returned, the call objects will be invalid.
+	 *  If the callback is NULL, the response result code of AT command
+	 *  will be an AT ERROR.
+	 *  If @kconfig{CONFIG_BT_HFP_AG_3WAY_CALL} is not enabled, the
+	 *  callback will not be notified.
+	 *
+	 *  @param ag HFP AG object.
+	 */
+	void (*explicit_call_transfer)(struct bt_hfp_ag *ag);
+
+	/** Voice recognition activation/deactivation callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  voice recognition activation is changed.
+	 *  If voice recognition is activated, the upper layer should
+	 *  call `bt_hfp_ag_audio_connect` with appropriate codec ID to
+	 *  setup audio connection.
+	 *  If the callback is not provided by upper layer, the function
+	 *  `bt_hfp_ag_audio_connect` will be called with default codec
+	 *  ID `BT_HFP_AG_CODEC_CVSD`.
+	 *  If @kconfig{CONFIG_BT_HFP_AG_VOICE_RECG} is not enabled,
+	 *  the callback will not be notified.
+	 *
+	 *  @param ag HFP AG object.
+	 *  @param activate Voice recognition activation/deactivation.
+	 */
+	void (*voice_recognition)(struct bt_hfp_ag *ag, bool activate);
+
+	/** Ready to accept audio callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  HF is ready to accept audio.
+	 *  If the feature `Enhanced Voice Recognition Status` is supported
+	 *  by HF, the callback will be notified if the AT command `AT+BVRA=2`
+	 *  is received. The HF may send this value during an ongoing VR
+	 *  (Voice Recognition) session to terminate audio output from the
+	 *  AG (if there is any) and prepare the AG for new audio input.
+	 *  Or, the callback will be notified after the voice recognition
+	 *  is activated.
+	 *  If @kconfig{CONFIG_BT_HFP_AG_ENH_VOICE_RECG} is not enabled,
+	 *  the callback will not be notified.
+	 *
+	 *  @param ag HFP AG object.
+	 */
+	void (*ready_to_accept_audio)(struct bt_hfp_ag *ag);
+
+	/** Request phone number callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  AT command `AT+BINP=1` is received.
+	 *  If the upper layer accepts the request, it shall obtain a
+	 *  phone number.
+	 *  If the upper layer rejects the request, it shall return a
+	 *  an error.
+	 *  If @kconfig{CONFIG_BT_HFP_AG_VOICE_TAG} is not enabled,
+	 *  the callback will not be notified.
+	 *
+	 *  @param ag HFP AG object.
+	 *  @param number Phone number of voice tag.
+	 *
+	 *  @return 0 in case of success or negative value in case of error.
+	 */
+	int (*request_phone_number)(struct bt_hfp_ag *ag, char **number);
+
+	/** Transmit a DTMF Code callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  AT command `AT+VTS=<code>` is received.
+	 *  During an ongoing call, the HF transmits the AT+VTS command
+	 *  to instruct the AG to transmit a specific DTMF code to its
+	 *  network connection.
+	 *
+	 *  @param ag HFP AG object.
+	 *  @param code A specific DTMF code.
+	 */
+	void (*transmit_dtmf_code)(struct bt_hfp_ag *ag, char code);
+
+	/** Get subscriber number callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  AT command `AT+CNUM` is received.
+	 *
+	 *  @param ag HFP AG object.
+	 *  @param func Query subscriber number callback.
+	 *
+	 *  @return 0 in case of success or negative value in case of error.
+	 */
+	int (*subscriber_number)(struct bt_hfp_ag *ag, bt_hfp_ag_query_subscriber_func_t func);
+
+	/** HF indicator value callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  AT command `AT+BIEV` is received.
+	 *  If @kconfig{CONFIG_BT_HFP_AG_HF_INDICATORS} is not enabled,
+	 *  the callback will not be notified.
+	 *
+	 *  @param ag HFP AG object.
+	 *  @param indicator HF indicator
+	 *  @param value The value of specific indicator
+	 */
+	void (*hf_indicator_value)(struct bt_hfp_ag *ag, enum hfp_ag_hf_indicators indicator,
+				   uint32_t value);
 };
 
 /** @brief Register HFP AG profile
@@ -200,48 +449,78 @@ int bt_hfp_ag_disconnect(struct bt_hfp_ag *ag);
  *  Notify HFP Unit of an incoming call.
  *
  *  @param ag HFP AG object.
- *  @param number Dailing number.
+ *  @param number Dialing number.
  *
  *  @return 0 in case of success or negative value in case of error.
  */
 int bt_hfp_ag_remote_incoming(struct bt_hfp_ag *ag, const char *number);
 
+/** @brief Put the incoming call on hold
+ *
+ *  Put the incoming call on hold.
+ *
+ *  @param call HFP AG call object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_ag_hold_incoming(struct bt_hfp_ag_call *call);
+
 /** @brief Reject the incoming call
  *
  *  Reject the incoming call.
  *
- *  @param ag HFP AG object.
+ *  @param call HFP AG call object.
  *
  *  @return 0 in case of success or negative value in case of error.
  */
-int bt_hfp_ag_reject(struct bt_hfp_ag *ag);
+int bt_hfp_ag_reject(struct bt_hfp_ag_call *call);
 
 /** @brief Accept the incoming call
  *
  *  Accept the incoming call.
  *
- *  @param ag HFP AG object.
+ *  @param call HFP AG call object.
  *
  *  @return 0 in case of success or negative value in case of error.
  */
-int bt_hfp_ag_accept(struct bt_hfp_ag *ag);
+int bt_hfp_ag_accept(struct bt_hfp_ag_call *call);
 
 /** @brief Terminate the active/hold call
  *
  *  Terminate the active/hold call.
  *
- *  @param ag HFP AG object.
+ *  @param call HFP AG call object.
  *
  *  @return 0 in case of success or negative value in case of error.
  */
-int bt_hfp_ag_terminate(struct bt_hfp_ag *ag);
+int bt_hfp_ag_terminate(struct bt_hfp_ag_call *call);
+
+/** @brief Retrieve the held call
+ *
+ *  Retrieve the held call.
+ *
+ *  @param call HFP AG call object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_ag_retrieve(struct bt_hfp_ag_call *call);
+
+/** @brief Hold the active call
+ *
+ *  Hold the active call.
+ *
+ *  @param call HFP AG call object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_ag_hold(struct bt_hfp_ag_call *call);
 
 /** @brief Dial a call
  *
  *  Dial a call.
  *
  *  @param ag HFP AG object.
- *  @param number Dailing number.
+ *  @param number Dialing number.
  *
  *  @return 0 in case of success or negative value in case of error.
  */
@@ -251,41 +530,266 @@ int bt_hfp_ag_outgoing(struct bt_hfp_ag *ag, const char *number);
  *
  *  Notify HFP Unit that the remote starts ringing.
  *
- *  @param ag HFP AG object.
+ *  @param call HFP AG call object.
  *
  *  @return 0 in case of success or negative value in case of error.
  */
-int bt_hfp_ag_remote_ringing(struct bt_hfp_ag *ag);
+int bt_hfp_ag_remote_ringing(struct bt_hfp_ag_call *call);
 
 /** @brief Notify HFP Unit that the remote rejects the call
  *
  *  Notify HFP Unit that the remote rejects the call.
  *
- *  @param ag HFP AG object.
+ *  @param call HFP AG call object.
  *
  *  @return 0 in case of success or negative value in case of error.
  */
-int bt_hfp_ag_remote_reject(struct bt_hfp_ag *ag);
+int bt_hfp_ag_remote_reject(struct bt_hfp_ag_call *call);
 
 /** @brief Notify HFP Unit that the remote accepts the call
  *
  *  Notify HFP Unit that the remote accepts the call.
  *
- *  @param ag HFP AG object.
+ *  @param call HFP AG call object.
  *
  *  @return 0 in case of success or negative value in case of error.
  */
-int bt_hfp_ag_remote_accept(struct bt_hfp_ag *ag);
+int bt_hfp_ag_remote_accept(struct bt_hfp_ag_call *call);
 
 /** @brief Notify HFP Unit that the remote terminates the active/hold call
  *
  *  Notify HFP Unit that the remote terminates the active/hold call.
  *
+ *  @param call HFP AG call object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_ag_remote_terminate(struct bt_hfp_ag_call *call);
+
+/** @brief explicit call transfer
+ *
+ *  Connects the two calls and disconnects the subscriber from
+ *  both calls (Explicit Call Transfer).
+ *  If @kconfig{CONFIG_BT_HFP_AG_3WAY_CALL} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param ag HFP AG object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_ag_explicit_call_transfer(struct bt_hfp_ag *ag);
+
+/** @brief Set the HF microphone gain
+ *
+ *  Set the HF microphone gain
+ *
+ *  @param ag HFP AG object.
+ *  @param vgm Microphone gain value.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_ag_vgm(struct bt_hfp_ag *ag, uint8_t vgm);
+
+/** @brief Set the HF speaker gain
+ *
+ *  Set the HF speaker gain
+ *
+ *  @param ag HFP AG object.
+ *  @param vgs Speaker gain value.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_ag_vgs(struct bt_hfp_ag *ag, uint8_t vgs);
+
+/** @brief Set currently network operator
+ *
+ *  Set currently network operator.
+ *
+ *  @param ag HFP AG object.
+ *  @param mode Current mode and provides no information with regard
+ *              to the name of the operator.
+ *  @param name A string in alphanumeric format representing the
+ *                  name of the network operator. This string shall
+ *                  not exceed 16 characters.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_ag_set_operator(struct bt_hfp_ag *ag, uint8_t mode, char *name);
+
+/** @brief Create audio connection
+ *
+ *  Create audio conenction by HFP AG. There are two setups included,
+ *  Codec connection and audio connection.
+ *  The codec connection will be established firstly if the codec
+ *  negotiation are supported by both side. If the passed codec id
+ *  is not same as the last codec connection, the codec connection
+ *  procedure will be triggered.
+ *  After the codec conenction is established, the audio conenction
+ *  will be started.
+ *  The passed codec id could be one of BT_HFP_AG_CODEC_XXX. If the
+ *  codec negotiation feature is supported by both side, the codec id
+ *  could be one of the bitmaps of `ids` notified by callback `codec`.
+ *  Or, the `id` should be BT_HFP_AG_CODEC_CVSD.
+ *
+ *  @param ag HFP AG object.
+ *  @param id Codec Id.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_ag_audio_connect(struct bt_hfp_ag *ag, uint8_t id);
+
+/** @brief Set In-Band Ring Tone
+ *
+ *  Set In-Band Ring Tone.
+ *
+ *  @param ag HFP AG object.
+ *  @param inband In-band or no in-band.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_ag_inband_ringtone(struct bt_hfp_ag *ag, bool inband);
+
+/** @brief Enable/disable the voice recognition function
+ *
+ *  Enables/disables the voice recognition function.
+ *  If @kconfig{CONFIG_BT_HFP_AG_VOICE_RECG} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param ag HFP AG object.
+ *  @param activate Activate/deactivate the voice recognition function.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_ag_voice_recognition(struct bt_hfp_ag *ag, bool activate);
+
+/** @brief set voice recognition engine state
+ *
+ *  It is used to set the voice recognition engine state.
+ *  The unsolicited result code `+BVRA: 1,<vrecstate>` will be sent.
+ *  `<vrecstate>`: Bitmask that reflects the current state of the voice
+ *  recognition engine on the AG.
+ *  Bit 0 - If it is 1, the AG is ready to accept audio input
+ *  Bit 1 - If it is 1, the AG is sending audio to the HF
+ *  Bit 2 - If it is 1, the AG is processing the audio input
+ *  If @kconfig{CONFIG_BT_HFP_AG_ENH_VOICE_RECG} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param ag HFP AG object.
+ *  @param state The value of `<vrecstate>`.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_ag_vre_state(struct bt_hfp_ag *ag, uint8_t state);
+
+/** @brief set voice recognition engine state and textual representation
+ *
+ *  It is used to set the voice recognition engine state with
+ *  textual representation.
+ *  unsolicited result code `+BVRA: 1,<vrecstate>,
+ *  <textualRepresentation>` will be sent.
+ *  `<vrecstate>` is same as parameter `state` of function
+ *  `bt_hfp_ag_vre_state`.
+ *  `<textualRepresentation>: <textID>,<textType>,<textOperation>,
+ *  <string>`.
+ *  `<textID>`: Unique ID of the current text as a hexadecimal string
+ *  (a maximum of 4 characters in length, but less than 4 characters
+ *  in length is valid).
+ *  `<textType>`: ID of the textType from the following list:
+ *  0 - Text recognized by the AG from the audio input provided by the HF
+ *  1 - Text of the audio output from the AG
+ *  2 - Text of the audio output from the AG that contains a question
+ *  3 - Text of the audio output from the AG that contains an error
+ *      description
+ *  `<textOperation>`: ID of the operation of the text
+ *  1 - NewText: Indicates that a new text started. Shall be used when the
+ *               `<textID>` changes
+ *  2 - Replace: Replace any existing text with the same `<textID>` and
+ *               same `<textType>`
+ *  3 - Append: Attach new text to existing text and keep the same
+ *              `<textID>` and same `<textType>`
+ *  `<string>`: The `<string>` parameter shall be a UTF-8 text string and
+ *  shall always be contained within double quotes.
+ *  If @kconfig{CONFIG_BT_HFP_AG_VOICE_RECG_TEXT} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param ag HFP AG object.
+ *  @param state The value of `<vrecstate>`.
+ *  @param id Value of `<textID>`.
+ *  @param type Value of `<textType>`.
+ *  @param operation Value of `<textOperation>`.
+ *  @param text Value of `<string>`.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_ag_vre_textual_representation(struct bt_hfp_ag *ag, uint8_t state, const char *id,
+					 uint8_t type, uint8_t operation, const char *text);
+
+/** @brief Set signal strength
+ *
+ *  Set signal strength.
+ *
+ *  @param ag HFP AG object.
+ *  @param strength Signal strength.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_ag_signal_strength(struct bt_hfp_ag *ag, uint8_t strength);
+
+/** @brief Set roaming status
+ *
+ *  Set roaming status.
+ *
+ *  @param ag HFP AG object.
+ *  @param status Roaming status.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_ag_roaming_status(struct bt_hfp_ag *ag, uint8_t status);
+
+/** @brief Set battery level
+ *
+ *  Set battery level.
+ *
+ *  @param ag HFP AG object.
+ *  @param level battery level.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_ag_battery_level(struct bt_hfp_ag *ag, uint8_t level);
+
+/** @brief Set service availability
+ *
+ *  Set service availability.
+ *
+ *  @param ag HFP AG object.
+ *  @param available service availability
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_ag_service_availability(struct bt_hfp_ag *ag, bool available);
+
+/** @brief Activate/deactivate HF indicator
+ *
+ *  It allows HF to issue the +BIND unsolicited result code to
+ *  activate/deactivate of the AG’s supported HF Indicators.
+ *  The indicator of supported indicators can be activated/deactivated
+ *  are defined in `enum hfp_ag_hf_indicators`.
+ *  `BT_HFP_AG_HF_INDICATOR_ENH_SAFETY` is used to support
+ *  `Enhanced Safety`. Only the configuration has been enabled, the
+ *  `indicator` can be HFP_AG_ENHANCED_SAFETY_IND.
+ *  `BT_HFP_AG_HF_INDICATOR_BATTERY` is used to support
+ *  `Remaining level of Battery`. Only the configuration has been
+ *  enabled, the `indicator` can be HFP_AG_BATTERY_LEVEL_IND.
+ *  If @kconfig{CONFIG_BT_HFP_HF_HF_INDICATORS} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
  *  @param ag HFP AG object.
+ *  @param indicator The indicator of the AG’s supported HF Indicators.
+ *  @param enable enable/disable specific HF Indicator.
  *
  *  @return 0 in case of success or negative value in case of error.
  */
-int bt_hfp_ag_remote_terminate(struct bt_hfp_ag *ag);
+int bt_hfp_ag_hf_indicator(struct bt_hfp_ag *ag, enum hfp_ag_hf_indicators indicator, bool enable);
 
 #ifdef __cplusplus
 }
diff --git a/include/zephyr/bluetooth/classic/hfp_hf.h b/include/zephyr/bluetooth/classic/hfp_hf.h
index ded881351ca..3a6dd4fc8f5 100644
--- a/include/zephyr/bluetooth/classic/hfp_hf.h
+++ b/include/zephyr/bluetooth/classic/hfp_hf.h
@@ -23,27 +23,14 @@
 extern "C" {
 #endif
 
-/* AT Commands */
-enum bt_hfp_hf_at_cmd {
-	BT_HFP_HF_ATA,
-	BT_HFP_HF_AT_CHUP,
-};
+/* HFP CODEC IDs */
+#define BT_HFP_HF_CODEC_CVSD    0x01
+#define BT_HFP_HF_CODEC_MSBC    0x02
+#define BT_HFP_HF_CODEC_LC3_SWB 0x03
 
-/*
- * Command complete types for the application
- */
-#define HFP_HF_CMD_OK             0
-#define HFP_HF_CMD_ERROR          1
-#define HFP_HF_CMD_CME_ERROR      2
-#define HFP_HF_CMD_UNKNOWN_ERROR  4
-
-/** @brief HFP HF Command completion field */
-struct bt_hfp_hf_cmd_complete {
-	/* Command complete status */
-	uint8_t type;
-	/* CME error number to be added */
-	uint8_t cme;
-};
+struct bt_hfp_hf;
+
+struct bt_hfp_hf_call;
 
 /** @brief HFP profile application callback */
 struct bt_hfp_hf_cb {
@@ -53,32 +40,35 @@ struct bt_hfp_hf_cb {
 	 *  connection completes.
 	 *
 	 *  @param conn Connection object.
+	 *  @param hf HFP HF object.
 	 */
-	void (*connected)(struct bt_conn *conn);
+	void (*connected)(struct bt_conn *conn, struct bt_hfp_hf *hf);
 	/** HF disconnected callback to application
 	 *
 	 *  If this callback is provided it will be called whenever the
 	 *  connection gets disconnected, including when a connection gets
 	 *  rejected or cancelled or any error in SLC establishment.
+	 *  And the HFP HF object will be freed after the registered
+	 *  callback `disconnected` returned.
 	 *
-	 *  @param conn Connection object.
+	 *  @param hf HFP HF object.
 	 */
-	void (*disconnected)(struct bt_conn *conn);
+	void (*disconnected)(struct bt_hfp_hf *hf);
 	/** HF SCO/eSCO connected Callback
 	 *
 	 *  If this callback is provided it will be called whenever the
 	 *  SCO/eSCO connection completes.
 	 *
-	 *  @param conn Connection object.
+	 *  @param hf HFP HF object.
 	 *  @param sco_conn SCO/eSCO Connection object.
 	 */
-	void (*sco_connected)(struct bt_conn *conn, struct bt_conn *sco_conn);
+	void (*sco_connected)(struct bt_hfp_hf *hf, struct bt_conn *sco_conn);
 	/** HF SCO/eSCO disconnected Callback
 	 *
 	 *  If this callback is provided it will be called whenever the
 	 *  SCO/eSCO connection gets disconnected.
 	 *
-	 *  @param conn Connection object.
+	 *  @param conn SCO/eSCO Connection object.
 	 *  @param reason BT_HCI_ERR_* reason for the disconnection.
 	 */
 	void (*sco_disconnected)(struct bt_conn *sco_conn, uint8_t reason);
@@ -86,75 +76,346 @@ struct bt_hfp_hf_cb {
 	 *
 	 *  This callback provides service indicator value to the application
 	 *
-	 *  @param conn Connection object.
+	 *  @param hf HFP HF object.
 	 *  @param value service indicator value received from the AG.
 	 */
-	void (*service)(struct bt_conn *conn, uint32_t value);
-	/** HF indicator Callback
+	void (*service)(struct bt_hfp_hf *hf, uint32_t value);
+	/** HF call outgoing Callback
 	 *
-	 *  This callback provides call indicator value to the application
+	 *  This callback provides the outgoing call status to
+	 *  the application.
 	 *
-	 *  @param conn Connection object.
-	 *  @param value call indicator value received from the AG.
+	 *  @param hf HFP HF object.
+	 *  @param call HFP HF call object.
 	 */
-	void (*call)(struct bt_conn *conn, uint32_t value);
-	/** HF indicator Callback
+	void (*outgoing)(struct bt_hfp_hf *hf, struct bt_hfp_hf_call *call);
+	/** HF call outgoing call is ringing Callback
 	 *
-	 *  This callback provides call setup indicator value to the application
+	 *  This callback provides the outgoing call is ringing
+	 *  status to the application.
 	 *
-	 *  @param conn Connection object.
-	 *  @param value call setup indicator value received from the AG.
+	 *  @param call HFP HF call object.
 	 */
-	void (*call_setup)(struct bt_conn *conn, uint32_t value);
-	/** HF indicator Callback
+	void (*remote_ringing)(struct bt_hfp_hf_call *call);
+	/** HF call incoming Callback
 	 *
-	 *  This callback provides call held indicator value to the application
+	 *  This callback provides the incoming call status to
+	 *  the application.
 	 *
-	 *  @param conn Connection object.
-	 *  @param value call held indicator value received from the AG.
+	 *  @param hf HFP HF object.
+	 *  @param call HFP HF call object.
+	 */
+	void (*incoming)(struct bt_hfp_hf *hf, struct bt_hfp_hf_call *call);
+	/** HF incoming call on hold Callback
+	 *
+	 *  This callback provides the incoming call on hold status to
+	 *  the application.
+	 *
+	 *  @param call HFP HF call object.
+	 */
+	void (*incoming_held)(struct bt_hfp_hf_call *call);
+	/** HF call accept Callback
+	 *
+	 *  This callback provides the incoming/outgoing call active
+	 *  status to the application.
+	 *
+	 *  @param call HFP HF call object.
 	 */
-	void (*call_held)(struct bt_conn *conn, uint32_t value);
+	void (*accept)(struct bt_hfp_hf_call *call);
+	/** HF call reject Callback
+	 *
+	 *  This callback provides the incoming/outgoing call reject
+	 *  status to the application.
+	 *
+	 *  @param call HFP HF call object.
+	 */
+	void (*reject)(struct bt_hfp_hf_call *call);
+	/** HF call terminate Callback
+	 *
+	 *  This callback provides the incoming/outgoing call terminate
+	 *  status to the application.
+	 *
+	 *  @param call HFP HF call object.
+	 */
+	void (*terminate)(struct bt_hfp_hf_call *call);
+	/** HF call held Callback
+	 *
+	 *  This callback provides call held to the application
+	 *
+	 *  @param call HFP HF call object.
+	 */
+	void (*held)(struct bt_hfp_hf_call *call);
+	/** HF call retrieve Callback
+	 *
+	 *  This callback provides call retrieved to the application
+	 *
+	 *  @param call HFP HF call object.
+	 */
+	void (*retrieve)(struct bt_hfp_hf_call *call);
 	/** HF indicator Callback
 	 *
 	 *  This callback provides signal indicator value to the application
 	 *
-	 *  @param conn Connection object.
+	 *  @param hf HFP HF object.
 	 *  @param value signal indicator value received from the AG.
 	 */
-	void (*signal)(struct bt_conn *conn, uint32_t value);
+	void (*signal)(struct bt_hfp_hf *hf, uint32_t value);
 	/** HF indicator Callback
 	 *
 	 *  This callback provides roaming indicator value to the application
 	 *
-	 *  @param conn Connection object.
+	 *  @param hf HFP HF object.
 	 *  @param value roaming indicator value received from the AG.
 	 */
-	void (*roam)(struct bt_conn *conn, uint32_t value);
+	void (*roam)(struct bt_hfp_hf *hf, uint32_t value);
 	/** HF indicator Callback
 	 *
 	 *  This callback battery service indicator value to the application
 	 *
-	 *  @param conn Connection object.
+	 *  @param hf HFP HF object.
 	 *  @param value battery indicator value received from the AG.
 	 */
-	void (*battery)(struct bt_conn *conn, uint32_t value);
+	void (*battery)(struct bt_hfp_hf *hf, uint32_t value);
 	/** HF incoming call Ring indication callback to application
 	 *
 	 *  If this callback is provided it will be called whenever there
 	 *  is an incoming call.
 	 *
-	 *  @param conn Connection object.
+	 *  @param call HFP HF call object.
 	 */
-	void (*ring_indication)(struct bt_conn *conn);
-	/** HF notify command completed callback to application
+	void (*ring_indication)(struct bt_hfp_hf_call *call);
+	/** HF call dialing Callback
 	 *
-	 *  The command sent from the application is notified about its status
+	 *  This callback provides call dialing result to the application.
 	 *
-	 *  @param conn Connection object.
-	 *  @param cmd structure contains status of the command including cme.
+	 *  @param hf HFP HF object.
+	 *  @param err Result of calling dialing.
+	 */
+	void (*dialing)(struct bt_hfp_hf *hf, int err);
+	/** HF calling line identification notification callback to application
+	 *
+	 *  If this callback is provided it will be called whenever there
+	 *  is a unsolicited result code +CLIP.
+	 *  If @kconfig{CONFIG_BT_HFP_HF_CLI} is not enabled, the unsolicited
+	 *  result code +CLIP will be ignored. And the callback will not be
+	 *  notified.
+	 *
+	 *  @param call HFP HF call object.
+	 *  @param number Notified phone number.
+	 *  @param type Specify the format of the phone number.
+	 */
+	void (*clip)(struct bt_hfp_hf_call *call, char *number, uint8_t type);
+	/** HF microphone gain notification callback to application
+	 *
+	 *  If this callback is provided it will be called whenever there
+	 *  is a unsolicited result code +VGM.
+	 *  If @kconfig{CONFIG_BT_HFP_HF_VOLUME} is not enabled, the unsolicited
+	 *  result code +VGM will be ignored. And the callback will not be
+	 *  notified.
+	 *
+	 *  @param hf HFP HF object.
+	 *  @param gain Microphone gain.
+	 */
+	void (*vgm)(struct bt_hfp_hf *hf, uint8_t gain);
+	/** HF speaker gain notification callback to application
+	 *
+	 *  If this callback is provided it will be called whenever there
+	 *  is a unsolicited result code +VGS.
+	 *  If @kconfig{CONFIG_BT_HFP_HF_VOLUME} is not enabled, the unsolicited
+	 *  result code +VGS will be ignored. And the callback will not be
+	 *  notified.
+	 *
+	 *  @param hf HFP HF object.
+	 *  @param gain Speaker gain.
+	 */
+	void (*vgs)(struct bt_hfp_hf *hf, uint8_t gain);
+	/** HF in-band ring tone notification callback to application
+	 *
+	 *  If this callback is provided it will be called whenever there
+	 *  is a unsolicited result code +BSIR issued by the AG to
+	 *  indicate to the HF that the in-band ring tone setting
+	 *  has been locally changed.
+	 *
+	 *  @param hf HFP HF object.
+	 *  @param inband In-band ring tone status from the AG.
+	 */
+	void (*inband_ring)(struct bt_hfp_hf *hf, bool inband);
+	/** HF network operator notification callback to application
+	 *
+	 *  If this callback is provided it will be called whenever there
+	 *  is a response code +COPS issued by the AG to
+	 *  response the AT+COPS? command issued by the HF by calling
+	 *  function `bt_hfp_hf_get_operator`.
+	 *
+	 *  @param hf HFP HF object.
+	 *  @param mode Current mode.
+	 *  @param format Format of the `operator` parameter string.
+	 *                It should be zero.
+	 *  @param operator A string in alphanumeric format
+	 *                  representing the name of the network
+	 *                  operator.
+	 */
+	void (*operator)(struct bt_hfp_hf *hf, uint8_t mode, uint8_t format, char *operator);
+	/** Codec negotiate callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  unsolicited codec negotiation response received.
+	 *  There are two cases when the callback triggered,
+	 *  Case 1, the codec id can be accepted, the function
+	 *  `bt_hfp_hf_select_codec` should be called to accept the codec
+	 *  id.
+	 *  Case 2, the codec id can not be accepted, the function
+	 *  `bt_hfp_hf_set_codecs` should be called to trigger codec ID
+	 *  to be re-selected.
+	 *  If the callback is not provided by application, the function
+	 *  `bt_hfp_hf_select_codec` will be called to accept the codec
+	 *  id.
+	 *  Refers to BT_HFP_HF_CODEC_XXX for codec id value.
+	 *  If @kconfig{CONFIG_BT_HFP_HF_CODEC_NEG} is not enabled, the
+	 *  unsolicited result code +BCS will be ignored. And the callback
+	 *  will not be notified.
+	 *
+	 *  @param hf HFP HF object.
+	 *  @param id Negotiated Codec ID.
+	 */
+	void (*codec_negotiate)(struct bt_hfp_hf *hf, uint8_t id);
+	/** HF ECNR turns off callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  response of ECNR turning off is received from AG.
+	 *  If @kconfig{CONFIG_BT_HFP_HF_ECNR} is not enabled, the
+	 *  callback will not be notified.
+	 *
+	 *  @param hf HFP HF object.
+	 *  @param err The result of request.
+	 */
+	void (*ecnr_turn_off)(struct bt_hfp_hf *hf, int err);
+	/** HF call waiting notification callback to application
+	 *
+	 *  If this callback is provided it will be called whenever there
+	 *  is a unsolicited result code +CCWA.
+	 *  This notification can be enabled/disabled by calling function
+	 *  `bt_hfp_hf_call_waiting_notify`.
+	 *  If @kconfig{CONFIG_BT_HFP_HF_3WAY_CALL} is not enabled, the
+	 *  unsolicited result code +CCWA will be ignored. And the callback
+	 *  will not be notified.
+	 *
+	 *  @param call HFP HF call object.
+	 *  @param number Notified phone number.
+	 *  @param type Specify the format of the phone number.
+	 */
+	void (*call_waiting)(struct bt_hfp_hf_call *call, char *number, uint8_t type);
+	/** Voice recognition activation/deactivation callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  unsolicited result code +BVRA is notified the HF when the
+	 *  voice recognition function in the AG is activated/deactivated
+	 *  autonomously from the AG.
+	 *  If @kconfig{CONFIG_BT_HFP_HF_VOICE_RECG} is not enabled, the
+	 *  unsolicited result code +BVRA will be ignored. And the callback
+	 *  will not be notified.
+	 *
+	 *  @param hf HFP HF object.
+	 *  @param activate Voice recognition activation/deactivation.
+	 */
+	void (*voice_recognition)(struct bt_hfp_hf *hf, bool activate);
+	/** Voice recognition engine state callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  unsolicited result code `+BVRA: 1,<vrecstate>` is received from AG.
+	 *  `<vrecstate>`: Bitmask that reflects the current state of the voice
+	 *  recognition engine on the AG.
+	 *  Bit 0 - If it is 1, the AG is ready to accept audio input
+	 *  Bit 1 - If it is 1, the AG is sending audio to the HF
+	 *  Bit 2 - If it is 1, the AG is processing the audio input
+	 *  If @kconfig{CONFIG_BT_HFP_HF_ENH_VOICE_RECG} is not enabled, the
+	 *  unsolicited result code +BVRA will be ignored. And the callback
+	 *  will not be notified.
+	 *
+	 *  @param hf HFP HF object.
+	 *  @param state Value of `<vrecstate>`.
 	 */
-	void (*cmd_complete_cb)(struct bt_conn *conn,
-			      struct bt_hfp_hf_cmd_complete *cmd);
+	void (*vre_state)(struct bt_hfp_hf *hf, uint8_t state);
+	/** Textual representation callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  unsolicited result code `+BVRA: 1,<vrecstate>,
+	 *  <textualRepresentation>` is received from AG.
+	 *  `<textualRepresentation>: <textID>,<textType>,<textOperation>,
+	 *  <string>`.
+	 *  `<textID>`: Unique ID of the current text as a hexadecimal string
+	 *  (a maximum of 4 characters in length, but less than 4 characters
+	 *  in length is valid).
+	 *  `<textType>`: ID of the textType from the following list:
+	 *  0 - Text recognized by the AG from the audio input provided by the HF
+	 *  1 - Text of the audio output from the AG
+	 *  2 - Text of the audio output from the AG that contains a question
+	 *  3 - Text of the audio output from the AG that contains an error
+	 *      description
+	 *  `<textOperation>`: ID of the operation of the text
+	 *  1 - NewText: Indicates that a new text started. Shall be used when the
+	 *               `<textID>` changes
+	 *  2 - Replace: Replace any existing text with the same `<textID>` and
+	 *               same `<textType>`
+	 *  3 - Append: Attach new text to existing text and keep the same
+	 *              `<textID>` and same `<textType>`
+	 *  `<string>`: The `<string>` parameter shall be a UTF-8 text string and
+	 *  shall always be contained within double quotes.
+	 *  If @kconfig{CONFIG_BT_HFP_HF_VOICE_RECG_TEXT} is not enabled, the
+	 *  unsolicited result code +BVRA will be ignored. And the callback
+	 *  will not be notified.
+	 *
+	 *  @param hf HFP HF object.
+	 *  @param id Value of `<textID>`.
+	 *  @param type Value of `<textType>`.
+	 *  @param operation Value of `<textOperation>`.
+	 *  @param text Value of `<string>`.
+	 */
+	void (*textual_representation)(struct bt_hfp_hf *hf, char *id, uint8_t type,
+				       uint8_t operation, char *text);
+	/** Request phone number callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  result code `+BINP: <Phone number>` is received from AG.
+	 *  If the request is failed, the `number` will be NULL.
+	 *
+	 *  @param hf HFP HF object.
+	 *  @param number Value of `<Phone number>`.
+	 */
+	void (*request_phone_number)(struct bt_hfp_hf *hf, const char *number);
+
+	/** Query subscriber number callback
+	 *
+	 *  If this callback is provided it will be called whenever the
+	 *  result code `+CUNM: [<alpha>],<number>, <type>,[<speed> ,<service>]`
+	 *  is received from AG.
+	 *  `<alpha>`: This optional field is not supported, and shall be left
+	 *  blank.
+	 *  `<number>`: Quoted string containing the phone number in the format
+	 *  specified by `<type>`.
+	 *  `<type>` field specifies the format of the phone number provided,
+	 *  and can be one of the following values:
+	 *  - values 128-143: The phone number format may be a national or
+	 *  international format, and may contain prefix and/or escape digits.
+	 *  No changes on the number presentation are required.
+	 *  - values 144-159: The phone number format is an international
+	 *  number, including the country code prefix. If the plus sign ("+")
+	 *  is not included as part of the number and shall be added by the AG
+	 *  as needed.
+	 *  - values 160-175: National number. No prefix nor escape digits
+	 *  included.
+	 *  `<speed>`: This optional field is not supported, and shall be left
+	 *  blank.
+	 *  `<service>`: Indicates which service this phone number relates to.
+	 *  Shall be either 4 (voice) or 5 (fax).
+	 *
+	 *  @param hf HFP HF object.
+	 *  @param number Value of `<number>` without quotes.
+	 *  @param type Value of `<type>`.
+	 *  @param service Value of `<service>`.
+	 */
+	void (*subscriber_number)(struct bt_hfp_hf *hf, const char *number, uint8_t type,
+				  uint8_t service);
 };
 
 /** @brief Register HFP HF profile
@@ -168,16 +429,528 @@ struct bt_hfp_hf_cb {
  */
 int bt_hfp_hf_register(struct bt_hfp_hf_cb *cb);
 
-/** @brief Handsfree client Send AT
+/** @brief Initiate the service level connection establishment procedure
+ *
+ *  Initiate the service level connection establishment procedure on the
+ *  ACL connection specified by the parameter `conn` using the specific
+ *  RFCOMM channel discovered by the function `bt_br_discovery_start`.
+ *
+ *  The parameter `hf` is a output parameter. When the service level
+ *  connection establishment procedure is initiated without any error,
+ *  the HFP HF object is allocated and it will be returned via the parameter
+ *  `hf` if the parameter `hf` is not a NULL pointer.
+ *
+ *  When service level conenction is established, the registered callback
+ *  `connected` will be triggered to notify the application that the service
+ *  level connection establishment procedure is done. And the HFP HF object
+ *  is valid at this time. It means after the function is called without
+ *  any error, all interfaces provided by HFP HF can only be called after
+ *  the registered callback `connected` is triggered.
+ *
+ *  @param conn ACL connection object.
+ *  @param hf Created HFP HF object.
+ *  @param channel Peer RFCOMM channel to be connected.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_connect(struct bt_conn *conn, struct bt_hfp_hf **hf, uint8_t channel);
+
+/** @brief Release the service level connection
+ *
+ *  Release the service level connection from the peer device.
+ *
+ *  The function can only be called after the registered callback `connected`
+ *  is triggered.
+ *
+ *  If the function is called without any error, the HFP HF object is
+ *  invalid at this time. All interfaces provided by HFP HF should not
+ *  be called anymore.
+ *
+ *  If the service level connection is released, the registered callback
+ *  `disconnected` will be triggered to notify the application that the
+ *  service level connection release procedure is done. And the HFP HF
+ *  object will be freed after the registered callback `disconnected`
+ *  returned.
+ *
+ *  @param hf HFP HF object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_disconnect(struct bt_hfp_hf *hf);
+
+/** @brief Handsfree HF enable/disable Calling Line Identification (CLI) Notification
+ *
+ *  Enable/disable Calling Line Identification (CLI) Notification.
+ *  The AT command `AT+CLIP` will be sent to the AG to enable/disable the CLI
+ *  unsolicited result code +CLIP when calling the function.
+ *  If @kconfig{CONFIG_BT_HFP_HF_CLI} is not enabled, the error `-ENOTSUP` will
+ *  be returned if the function called.
+ *
+ *  @param hf HFP HF object.
+ *  @param enable Enable/disable CLI.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_cli(struct bt_hfp_hf *hf, bool enable);
+
+/** @brief Handsfree HF report Gain of Microphone (VGM)
+ *
+ *  Report Gain of Microphone (VGM).
+ *  The AT command `AT+VGM=<gain>` will be sent to the AG to report its
+ *  current microphone gain level setting to the AG.
+ *  `<gain>` is a decimal numeric constant, relating to a particular
+ *  (implementation dependent) volume level controlled by the HF.
+ *  This command does not change the microphone gain of the AG; it simply
+ *  indicates the current value of the microphone gain in the HF.
+ *  If @kconfig{CONFIG_BT_HFP_HF_VOLUME} is not enabled, the error `-ENOTSUP`
+ *  will be returned if the function called.
+ *  For "Volume Level Synchronization", the HF application could call
+ *  the function to set VGM gain value in HF connection callback
+ *  function. Then after the HF connection callback returned, VGM gain
+ *  will be sent to HFP AG.
+ *
+ *  @param hf HFP HF object.
+ *  @param gain Gain of microphone.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_vgm(struct bt_hfp_hf *hf, uint8_t gain);
+
+/** @brief Handsfree HF report Gain of Speaker (VGS)
+ *
+ *  Report Gain of Speaker (VGS).
+ *  The AT command `AT+VGS=<gain>` will be sent to the AG to report its
+ *  current speaker gain level setting to the AG.
+ *  `<gain>` is a decimal numeric constant, relating to a particular
+ *  (implementation dependent) volume level controlled by the HF.
+ *  This command does not change the speaker gain of the AG; it simply
+ *  indicates the current value of the speaker gain in the HF.
+ *  If @kconfig{CONFIG_BT_HFP_HF_VOLUME} is not enabled, the error `-ENOTSUP`
+ *  will be returned if the function called.
+ *  For "Volume Level Synchronization", the HF application could call
+ *  the function to set VGS gain value in HF connection callback
+ *  function. Then after the HF connection callback returned, VGS gain
+ *  will be sent to HFP AG.
+ *
+ *  @param hf HFP HF object.
+ *  @param gain Gain of speaker.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_vgs(struct bt_hfp_hf *hf, uint8_t gain);
+
+/** @brief Handsfree HF requests currently selected operator
+ *
+ *  Send the AT+COPS? (Read) command to find the currently
+ *  selected operator.
+ *
+ *  @param hf HFP HF object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_get_operator(struct bt_hfp_hf *hf);
+
+/** @brief Handsfree HF accept the incoming call
+ *
+ *  Send the ATA command to accept the incoming call.
+ *  OR, send the AT+BTRH=1 command to accept a held incoming
+ *  call.
+ *
+ *  @note It cannot be used when multiple calls are ongoing.
+ *
+ *  @param call HFP HF call object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_accept(struct bt_hfp_hf_call *call);
+
+/** @brief Handsfree HF reject the incoming call
+ *
+ *  Send the AT+CHUP command to reject the incoming call.
+ *  OR, send the AT+BTRH=2 command to reject a held incoming
+ *  call.
+ *
+ *  @note It cannot be used when multiple calls are ongoing.
+ *
+ *  @param call HFP HF call object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_reject(struct bt_hfp_hf_call *call);
+
+/** @brief Handsfree HF terminate the incoming call
+ *
+ *  Send the AT+CHUP command to terminate the incoming call.
+ *
+ *  @note It cannot be used when multiple calls are ongoing.
+ *
+ *  @param call HFP HF call object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_terminate(struct bt_hfp_hf_call *call);
+
+/** @brief Handsfree HF put the incoming call on hold
+ *
+ *  Send the AT+BTRH=0 command to put the incoming call on hold.
+ *  If the incoming call has been held, the callback `on_hold` will
+ *  be triggered.
+ *
+ *  @note It cannot be used when multiple calls are ongoing.
+ *
+ *  @param call HFP HF call object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_hold_incoming(struct bt_hfp_hf_call *call);
+
+/** @brief Handsfree HF query respond and hold status of AG
+ *
+ *  Send the AT+BTRH? command to query respond and hold status of AG.
+ *  The status respond and hold will be notified through callback
+ *  `on_hold`.
+ *
+ *  @param hf HFP HF object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_query_respond_hold_status(struct bt_hfp_hf *hf);
+
+/** @brief Handsfree HF phone number call
+ *
+ *  Initiate outgoing voice calls by providing the destination phone
+ *  number to the AG.
+ *  Send the ATDdd…dd command to start phone number call.
+ *  The result of the command will be notified through the callback
+ *  `dialing`.
+ *
+ *  @param hf HFP HF object.
+ *  @param number Phone number.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_number_call(struct bt_hfp_hf *hf, const char *number);
+
+/** @brief Handsfree HF memory dialing call
+ *
+ *  Initiate outgoing voice calls using the memory dialing feature
+ *  of the AG.
+ *  Send the ATD>Nan... command to start memory dialing.
+ *  The result of the command will be notified through the callback
+ *  `dialing`.
+ *
+ *  @param hf HFP HF object.
+ *  @param location Memory location.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_memory_dial(struct bt_hfp_hf *hf, const char *location);
+
+/** @brief Handsfree HF redial last number
+ *
+ *  Initiate outgoing voice calls by recalling the last number
+ *  dialed by the AG.
+ *  Send the AT+BLDN command to recall the last number.
+ *  The result of the command will be notified through the callback
+ *  `dialing`.
+ *
+ *  @param hf HFP HF object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_redial(struct bt_hfp_hf *hf);
+
+/** @brief Handsfree HF setup audio connection
+ *
+ *  Setup audio conenction by sending AT+BCC.
+ *  If @kconfig{CONFIG_BT_HFP_HF_CODEC_NEG} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param hf HFP HF object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_audio_connect(struct bt_hfp_hf *hf);
+
+/** @brief Handsfree HF set selected codec id
+ *
+ *  Set selected codec id by sending AT+BCS. The function is used to
+ *  response the codec negotiation request notified by callback
+ *  `codec_negotiate`. The parameter `codec_id` should be same as
+ *  `id` of callback `codec_negotiate` if the id could be supported.
+ *  Or, call `bt_hfp_hf_set_codecs` to notify the AG Codec IDs supported
+ *  by HFP HF.
+ *  If @kconfig{CONFIG_BT_HFP_HF_CODEC_NEG} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param hf HFP HF object.
+ *  @param codec_id Selected codec id.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_select_codec(struct bt_hfp_hf *hf, uint8_t codec_id);
+
+/** @brief Handsfree HF set supported codec ids
+ *
+ *  Set supported codec ids by sending AT+BAC. This function is used
+ *  to notify AG the supported Codec IDs of HF.
+ *  If @kconfig{CONFIG_BT_HFP_HF_CODEC_NEG} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param hf HFP HF object.
+ *  @param codec_ids Supported codec IDs.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_set_codecs(struct bt_hfp_hf *hf, uint8_t codec_ids);
+
+/** @brief Handsfree HF turns off AG's EC and NR
+ *
+ *  Turn off the AG's EC and NR by sending `AT+NREC=0`.
+ *  The result of the command is notified through the callback
+ *  `ecnr_turn_off`.
+ *  If @kconfig{CONFIG_BT_HFP_HF_ECNR} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param hf HFP HF object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_turn_off_ecnr(struct bt_hfp_hf *hf);
+
+/** @brief Handsfree HF enable/disable call waiting notification
+ *
+ *  Enable call waiting notification by sending `AT+CCWA=1`.
+ *  Disable call waiting notification by sending `AT+CCWA=0`.
+ *  If @kconfig{CONFIG_BT_HFP_HF_3WAY_CALL} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param hf HFP HF object.
+ *  @param enable Enable/disable.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_call_waiting_notify(struct bt_hfp_hf *hf, bool enable);
+
+/** @brief Handsfree HF release all held calls
+ *
+ *  Release all held calls by sending `AT+CHLD=0`.
+ *  If @kconfig{CONFIG_BT_HFP_HF_3WAY_CALL} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param hf HFP HF object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_release_all_held(struct bt_hfp_hf *hf);
+
+/** @brief Handsfree HF set User Determined User Busy (UDUB) for a waiting call
+ *
+ *  Set User Determined User Busy (UDUB) for a waiting call
+ *  by sending `AT+CHLD=0`.
+ *  If @kconfig{CONFIG_BT_HFP_HF_3WAY_CALL} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param hf HFP HF object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_set_udub(struct bt_hfp_hf *hf);
+
+/** @brief Handsfree HF release all active calls and accept other call
+ *
+ *  Release all active calls (if any exist) and accepts the other
+ *  (held or waiting) call by sending `AT+CHLD=1`.
+ *  If @kconfig{CONFIG_BT_HFP_HF_3WAY_CALL} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param hf HFP HF object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_release_active_accept_other(struct bt_hfp_hf *hf);
+
+/** @brief Handsfree HF hold all active calls and accept other call
+ *
+ *  Hold all active calls (if any exist) and accepts the other
+ *  (held or waiting) call by sending `AT+CHLD=2`.
+ *  If @kconfig{CONFIG_BT_HFP_HF_3WAY_CALL} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param hf HFP HF object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_hold_active_accept_other(struct bt_hfp_hf *hf);
+
+/** @brief Handsfree HF add a held call to the conversation
+ *
+ *  Add a held call to the conversation by sending `AT+CHLD=3`.
+ *  If @kconfig{CONFIG_BT_HFP_HF_3WAY_CALL} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param hf HFP HF object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_join_conversation(struct bt_hfp_hf *hf);
+
+/** @brief Handsfree HF explicit call transfer
+ *
+ *  Connects the two calls and disconnects the subscriber from
+ *  both calls (Explicit Call Transfer) by sending `AT+CHLD=4`.
+ *  If @kconfig{CONFIG_BT_HFP_HF_3WAY_CALL} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param hf HFP HF object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_explicit_call_transfer(struct bt_hfp_hf *hf);
+
+/** @brief Handsfree HF release call with specified index
+ *
+ *  Release call with specified index by sending `AT+CHLD=1<idx>`.
+ *  `<idx>` is index of specified call.
+ *  If @kconfig{CONFIG_BT_HFP_HF_ECC} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param call HFP HF call object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_release_specified_call(struct bt_hfp_hf_call *call);
+
+/** @brief Handsfree HF request private consultation mode with specified call
+ *
+ *  Request private consultation mode with specified call (Place all calls
+ *  on hold EXCEPT the call indicated by `<idx>`.) by sending
+ *  `AT+CHLD=2<idx>`.
+ *  `<idx>` is index of specified call.
+ *  If @kconfig{CONFIG_BT_HFP_HF_ECC} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param call HFP HF call object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_private_consultation_mode(struct bt_hfp_hf_call *call);
+
+/** @brief Handsfree HF enable/disable the voice recognition function
+ *
+ *  Enables/disables the voice recognition function in the AG.
+ *  If @kconfig{CONFIG_BT_HFP_HF_VOICE_RECG} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param hf HFP HF object.
+ *  @param activate Activate/deactivate the voice recognition function.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_voice_recognition(struct bt_hfp_hf *hf, bool activate);
+
+/** @brief Handsfree HF indicate that the HF is ready to accept audio
+ *
+ *  This value indicates that the HF is ready to accept audio when
+ *  the Audio Connection is first established. The HF shall only send
+ *  this value if the eSCO link has been established.
+ *  If @kconfig{CONFIG_BT_HFP_HF_ENH_VOICE_RECG} is not enabled, the error
+ *  `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param hf HFP HF object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_ready_to_accept_audio(struct bt_hfp_hf *hf);
+
+/** @brief Handsfree HF attach a phone number for a voice tag
+ *
+ *  Send AT command "AT+BINP=1" to request phone number to the AG.
+ *
+ *  @param hf HFP HF object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_request_phone_number(struct bt_hfp_hf *hf);
+
+/** @brief Handsfree HF Transmit A specific DTMF Code
+ *
+ *  During an ongoing call, the HF transmits the AT+VTS command to
+ *  instruct the AG to transmit a specific DTMF code to its network
+ *  connection.
+ *  The set of the code is "0-9,#,*,A-D".
+ *
+ *  @param call HFP HF call object.
+ *  @param code A specific DTMF code.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_transmit_dtmf_code(struct bt_hfp_hf_call *call, char code);
+
+/** @brief Handsfree HF Query Subscriber Number Information
+ *
+ *  It allows HF to query the AG subscriber number by sending `AT+CNUM`.
+ *
+ *  @param hf HFP HF object.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_query_subscriber(struct bt_hfp_hf *hf);
+
+/* HFP HF Indicators */
+enum hfp_hf_ag_indicators {
+	HF_SERVICE_IND = 0, /* AG service indicator */
+	HF_CALL_IND,        /* AG call indicator */
+	HF_CALL_SETUP_IND,  /* AG call setup indicator */
+	HF_CALL_HELD_IND,   /* AG call held indicator */
+	HF_SIGNAL_IND,      /* AG signal indicator */
+	HF_ROAM_IND,        /* AG roaming indicator */
+	HF_BATTERY_IND      /* AG battery indicator */
+};
+
+/** @brief Handsfree HF set AG indicator activated/deactivated status
+ *
+ *  It allows HF to issue the AT+BIA command if it needs to change the
+ *  activated/deactivated status of indicators in the AG.
+ *  The index of all indicators can be activated/deactivated are
+ *  defined in `enum hfp_hf_ag_indicators`.
+ *  The each bit of parameter `status` represents the indicator status
+ *  corresponding to the index. Such as, value 0b111110 of `status`
+ *  means the AG indicator `service` is required to be deactivated.
+ *  Others are required to be activated.
+ *
+ *  @param hf HFP HF object.
+ *  @param status The activated/deactivated bitmap status of AG indicators.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_indicator_status(struct bt_hfp_hf *hf, uint8_t status);
+
+/** @brief Handsfree HF enable/disable enhanced safety
+ *
+ *  It allows HF to transfer of HF indicator enhanced safety value.
+ *  If @kconfig{CONFIG_BT_HFP_HF_HF_INDICATOR_ENH_SAFETY} is not enabled,
+ *  the error `-ENOTSUP` will be returned if the function called.
+ *
+ *  @param hf HFP HF object.
+ *  @param enable The enhanced safety is enabled/disabled.
+ *
+ *  @return 0 in case of success or negative value in case of error.
+ */
+int bt_hfp_hf_enhanced_safety(struct bt_hfp_hf *hf, bool enable);
+
+/** @brief Handsfree HF remaining battery level
  *
- *  Send specific AT commands to handsfree client profile.
+ *  It allows HF to transfer of HF indicator remaining battery level value.
+ *  If @kconfig{CONFIG_BT_HFP_HF_HF_INDICATOR_BATTERY} is not enabled,
+ *  the error `-ENOTSUP` will be returned if the function called.
  *
- *  @param conn Connection object.
- *  @param cmd AT command to be sent.
+ *  @param hf HFP HF object.
+ *  @param level The remaining battery level.
  *
  *  @return 0 in case of success or negative value in case of error.
  */
-int bt_hfp_hf_send_cmd(struct bt_conn *conn, enum bt_hfp_hf_at_cmd cmd);
+int bt_hfp_hf_battery(struct bt_hfp_hf *hf, uint8_t level);
 
 #ifdef __cplusplus
 }
diff --git a/include/zephyr/bluetooth/classic/rfcomm.h b/include/zephyr/bluetooth/classic/rfcomm.h
index 1d3056643bd..be2cf02b419 100644
--- a/include/zephyr/bluetooth/classic/rfcomm.h
+++ b/include/zephyr/bluetooth/classic/rfcomm.h
@@ -19,11 +19,27 @@
 
 #include <zephyr/bluetooth/buf.h>
 #include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/l2cap.h>
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+/** RFCOMM Maximum Header Size. The length could be 2 bytes, it depends on information length. */
+#define BT_RFCOMM_HDR_MAX_SIZE 4
+/** RFCOMM FCS Size */
+#define BT_RFCOMM_FCS_SIZE     1
+
+/** @brief Helper to calculate needed buffer size for RFCOMM PDUs.
+ *         Useful for creating buffer pools.
+ *
+ *  @param mtu Needed RFCOMM PDU MTU.
+ *
+ *  @return Needed buffer size to match the requested RFCOMM PDU MTU.
+ */
+#define BT_RFCOMM_BUF_SIZE(mtu)                                                                    \
+	BT_L2CAP_BUF_SIZE(BT_RFCOMM_HDR_MAX_SIZE + BT_RFCOMM_FCS_SIZE + (mtu))
+
 /* RFCOMM channels (1-30): pre-allocated for profiles to avoid conflicts */
 enum {
 	BT_RFCOMM_CHAN_HFP_HF = 1,
@@ -31,6 +47,7 @@ enum {
 	BT_RFCOMM_CHAN_HSP_AG,
 	BT_RFCOMM_CHAN_HSP_HS,
 	BT_RFCOMM_CHAN_SPP,
+	BT_RFCOMM_CHAN_DYNAMIC_START,
 };
 
 struct bt_rfcomm_dlc;
@@ -109,7 +126,16 @@ struct bt_rfcomm_dlc {
 };
 
 struct bt_rfcomm_server {
-	/** Server Channel */
+	/** Server Channel
+	 *
+	 *  Possible values:
+	 *  0           A dynamic value will be auto-allocated when bt_rfcomm_server_register() is
+	 *              called.
+	 *
+	 *  0x01 - 0x1e Dynamically allocated. May be pre-set by the application before server
+	 *              registration (not recommended however), or auto-allocated by the stack
+	 *              if the 0 is passed.
+	 */
 	uint8_t channel;
 
 	/** Server accept callback
@@ -118,11 +144,13 @@ struct bt_rfcomm_server {
 	 *  authorization.
 	 *
 	 *  @param conn The connection that is requesting authorization
+	 *  @param server Pointer to the server structure this callback relates to
 	 *  @param dlc Pointer to received the allocated dlc
 	 *
 	 *  @return 0 in case of success or negative value in case of error.
 	 */
-	int (*accept)(struct bt_conn *conn, struct bt_rfcomm_dlc **dlc);
+	int (*accept)(struct bt_conn *conn, struct bt_rfcomm_server *server,
+		      struct bt_rfcomm_dlc **dlc);
 
 	struct bt_rfcomm_server	*_next;
 };
diff --git a/include/zephyr/bluetooth/conn.h b/include/zephyr/bluetooth/conn.h
index dc088068645..82f6a8d2770 100644
--- a/include/zephyr/bluetooth/conn.h
+++ b/include/zephyr/bluetooth/conn.h
@@ -4,6 +4,7 @@
 
 /*
  * Copyright (c) 2015-2016 Intel Corporation
+ * Copyright (c) 2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,12 +21,16 @@
 #include <stdbool.h>
 #include <stdint.h>
 
-#include <zephyr/bluetooth/bluetooth.h>
-#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/addr.h>
-#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/direction.h>
+#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/net_buf.h>
 #include <zephyr/sys/iterable_sections.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/toolchain.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -722,7 +727,7 @@ struct bt_conn *bt_conn_lookup_addr_le(uint8_t id, const bt_addr_le_t *peer);
  *
  *  @param conn Connection object.
  *
- *  @return Destination address.
+ *  @return Destination address if @p conn is a valid @ref BT_CONN_TYPE_LE connection
  */
 const bt_addr_le_t *bt_conn_get_dst(const struct bt_conn *conn);
 
@@ -1041,9 +1046,20 @@ enum bt_conn_auth_keypress {
  */
 int bt_conn_get_info(const struct bt_conn *conn, struct bt_conn_info *info);
 
+/** @brief Function to determine the type of a connection
+ *
+ *  @param conn The connection object
+ *  @param type The types to check against. It is possible to supply multiple types,
+ *              e.g. BT_CONN_TYPE_LE | BT_CONN_TYPE_SCO.
+ *
+ *  @retval true @p conn is of type @p type
+ *  @retval false @p conn is either NULL or not of type @p type
+ */
+bool bt_conn_is_type(const struct bt_conn *conn, enum bt_conn_type type);
+
 /** @brief Get connection info for the remote device.
  *
- *  @param conn Connection object.
+ *  @param conn @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection object.
  *  @param remote_info Connection remote info object.
  *
  *  @note In order to retrieve the remote version (version, manufacturer
@@ -1055,51 +1071,55 @@ int bt_conn_get_info(const struct bt_conn *conn, struct bt_conn_info *info);
  *
  *  @return Zero on success or (negative) error code on failure.
  *  @return -EBUSY The remote information is not yet available.
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection.
  */
-int bt_conn_get_remote_info(struct bt_conn *conn,
-			    struct bt_conn_remote_info *remote_info);
+int bt_conn_get_remote_info(const struct bt_conn *conn, struct bt_conn_remote_info *remote_info);
 
 /** @brief Get connection transmit power level.
  *
- *  @param conn           Connection object.
+ *  @param conn           @ref BT_CONN_TYPE_LE connection object.
  *  @param tx_power_level Transmit power level descriptor.
  *
  *  @return Zero on success or (negative) error code on failure.
  *  @return -ENOBUFS HCI command buffer is not available.
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE connection.
  */
 int bt_conn_le_get_tx_power_level(struct bt_conn *conn,
 				  struct bt_conn_le_tx_power *tx_power_level);
 
 /** @brief Get local enhanced connection transmit power level.
  *
- *  @param conn           Connection object.
+ *  @param conn           @ref BT_CONN_TYPE_LE connection object.
  *  @param tx_power       Transmit power level descriptor.
  *
  *  @return Zero on success or (negative) error code on failure.
  *  @retval -ENOBUFS HCI command buffer is not available.
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE connection.
  */
 int bt_conn_le_enhanced_get_tx_power_level(struct bt_conn *conn,
 					   struct bt_conn_le_tx_power *tx_power);
 
 /** @brief Get remote (peer) transmit power level.
  *
- *  @param conn           Connection object.
+ *  @param conn           @ref BT_CONN_TYPE_LE connection object.
  *  @param phy            PHY information.
  *
  *  @return Zero on success or (negative) error code on failure.
  *  @retval -ENOBUFS HCI command buffer is not available.
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE connection.
  */
 int bt_conn_le_get_remote_tx_power_level(struct bt_conn *conn,
 					 enum bt_conn_le_tx_power_phy phy);
 
 /** @brief Enable transmit power reporting.
  *
- *  @param conn           Connection object.
+ *  @param conn           @ref BT_CONN_TYPE_LE connection object.
  *  @param local_enable   Enable/disable reporting for local.
  *  @param remote_enable  Enable/disable reporting for remote.
  *
  *  @return Zero on success or (negative) error code on failure.
  *  @retval -ENOBUFS HCI command buffer is not available.
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE connection.
  */
 int bt_conn_le_set_tx_power_report_enable(struct bt_conn *conn,
 					  bool local_enable,
@@ -1111,10 +1131,11 @@ int bt_conn_le_set_tx_power_report_enable(struct bt_conn *conn,
  *
  *  @note To use this API @kconfig{CONFIG_BT_PATH_LOSS_MONITORING} must be set.
  *
- *  @param conn  Connection object.
+ *  @param conn  @ref BT_CONN_TYPE_LE connection object.
  *  @param param Path Loss Monitoring parameters
  *
  *  @return Zero on success or (negative) error code on failure.
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE connection.
  */
 int bt_conn_le_set_path_loss_mon_param(struct bt_conn *conn,
 				       const struct bt_conn_le_path_loss_reporting_param *param);
@@ -1126,10 +1147,11 @@ int bt_conn_le_set_path_loss_mon_param(struct bt_conn *conn,
  *
  * @note To use this API @kconfig{CONFIG_BT_PATH_LOSS_MONITORING} must be set.
  *
- * @param conn   Connection Object.
+ * @param conn  @ref BT_CONN_TYPE_LE connection object.
  * @param enable Enable/disable path loss reporting.
  *
  * @return Zero on success or (negative) error code on failure.
+ * @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE connection.
  */
 int bt_conn_le_set_path_loss_mon_enable(struct bt_conn *conn, bool enable);
 
@@ -1155,10 +1177,11 @@ int bt_conn_le_subrate_set_defaults(const struct bt_conn_le_subrate_param *param
  *
  *  @note To use this API @kconfig{CONFIG_BT_SUBRATING} must be set.
  *
- *  @param conn   Connection object.
+ *  @param conn   @ref BT_CONN_TYPE_LE connection object.
  *  @param params Subrating parameters.
  *
  *  @return Zero on success or (negative) error code on failure.
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE connection.
  */
 int bt_conn_le_subrate_request(struct bt_conn *conn,
 			       const struct bt_conn_le_subrate_param *params);
@@ -1169,20 +1192,22 @@ int bt_conn_le_subrate_request(struct bt_conn *conn,
  *  parameters will be delayed. This delay can be configured by through the
  *  @kconfig{CONFIG_BT_CONN_PARAM_UPDATE_TIMEOUT} option.
  *
- *  @param conn Connection object.
+ *  @param conn  @ref BT_CONN_TYPE_LE connection object.
  *  @param param Updated connection parameters.
  *
  *  @return Zero on success or (negative) error code on failure.
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE connection.
  */
 int bt_conn_le_param_update(struct bt_conn *conn,
 			    const struct bt_le_conn_param *param);
 
 /** @brief Update the connection transmit data length parameters.
  *
- *  @param conn  Connection object.
+ *  @param conn  @ref BT_CONN_TYPE_LE connection object.
  *  @param param Updated data length parameters.
  *
  *  @return Zero on success or (negative) error code on failure.
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE connection.
  */
 int bt_conn_le_data_len_update(struct bt_conn *conn,
 			       const struct bt_conn_le_data_len_param *param);
@@ -1192,10 +1217,11 @@ int bt_conn_le_data_len_update(struct bt_conn *conn,
  *  Update the preferred transmit and receive PHYs of the connection.
  *  Use @ref BT_GAP_LE_PHY_NONE to indicate no preference.
  *
- *  @param conn Connection object.
+ *  @param conn  @ref BT_CONN_TYPE_LE connection object.
  *  @param param Updated connection parameters.
  *
  *  @return Zero on success or (negative) error code on failure.
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE connection.
  */
 int bt_conn_le_phy_update(struct bt_conn *conn,
 			  const struct bt_conn_le_phy_param *param);
@@ -1469,16 +1495,22 @@ __deprecated int bt_le_set_auto_conn(const bt_addr_le_t *addr,
  *  @note When @ref BT_SECURITY_FORCE_PAIR within @p sec is enabled then the pairing
  *        procedure will always be initiated.
  *
- *  @param conn Connection object.
+ *  @param conn @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection object.
  *  @param sec Requested minimum security level.
  *
  *  @return 0 on success or negative error
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection.
  */
 int bt_conn_set_security(struct bt_conn *conn, bt_security_t sec);
 
 /** @brief Get security level for a connection.
  *
- *  @return Connection security level
+ *  @param conn @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection object.
+ *
+ *  @return Connection security level if @kconfig{CONFIG_BT_SMP} or @kconfig{CONFIG_BT_CLASSIC} is
+ *          enabled, else @ref BT_SECURITY_L1
+ *  @return @ref BT_SECURITY_L0 @p conn is not a valid @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR
+ *          connection.
  */
 bt_security_t bt_conn_get_security(const struct bt_conn *conn);
 
@@ -1487,9 +1519,10 @@ bt_security_t bt_conn_get_security(const struct bt_conn *conn);
  *  This function gets encryption key size.
  *  If there is no security (encryption) enabled 0 will be returned.
  *
- *  @param conn Existing connection object.
+ *  @param conn @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection object.
  *
  *  @return Encryption key size.
+ *  @return 0 @p conn is not a valid @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection.
  */
 uint8_t bt_conn_enc_key_size(const struct bt_conn *conn);
 
@@ -1530,7 +1563,7 @@ enum bt_conn_le_cs_procedure_enable_state {
 	BT_CONN_LE_CS_PROCEDURES_ENABLED = BT_HCI_OP_LE_CS_PROCEDURES_ENABLED,
 };
 
-/** CS Test Tone Antennna Config Selection.
+/** CS Test Tone Antenna Config Selection.
  *
  *  These enum values are indices in the following table, where N_AP is the maximum
  *  number of antenna paths (in the range [1, 4]).
@@ -2035,8 +2068,13 @@ bool bt_get_bondable(void);
  *  The default value of the global configuration is defined using
  *  CONFIG_BT_BONDABLE Kconfig option.
  *
- *  @param conn Connection object.
+ *  @param conn @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection object.
  *  @param enable Value allowing/disallowing to be bondable.
+ *
+ *  @retval 0 Success
+ *  @retval -EALREADY Already in the requested state
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection
+ *  @return -EINVAL @p conn is a valid @ref BT_CONN_TYPE_LE but could not get SMP context
  */
 int bt_conn_set_bondable(struct bt_conn *conn, bool enable);
 
@@ -2062,10 +2100,12 @@ void bt_le_oob_set_legacy_flag(bool enable);
  *  The function should only be called in response to the oob_data_request()
  *  callback provided that the legacy method is user pairing.
  *
- *  @param conn Connection object
+ *  @param conn  @ref BT_CONN_TYPE_LE connection object.
  *  @param tk Pointer to 16 byte long TK array
  *
- *  @return Zero on success or -EINVAL if NULL
+ *  @retval 0 Success
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE connection.
+ *  @return -EINVAL @p tk is NULL.
  */
 int bt_le_oob_set_legacy_tk(struct bt_conn *conn, const uint8_t *tk);
 
@@ -2080,12 +2120,13 @@ int bt_le_oob_set_legacy_tk(struct bt_conn *conn, const uint8_t *tk);
  *  data present, with only remote OOB data present or with both local and
  *  remote OOB data present.
  *
- *  @param conn Connection object
+ *  @param conn  @ref BT_CONN_TYPE_LE connection object.
  *  @param oobd_local Local OOB data or NULL if not present
  *  @param oobd_remote Remote OOB data or NULL if not present
  *
  *  @return Zero on success or error code otherwise, positive in case of
  *          protocol error or negative (POSIX) in case of stack internal error.
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE connection.
  */
 int bt_le_oob_set_sc_data(struct bt_conn *conn,
 			  const struct bt_le_oob_sc_data *oobd_local,
@@ -2099,12 +2140,13 @@ int bt_le_oob_set_sc_data(struct bt_conn *conn,
  *  @note The OOB data will only be available as long as the connection object
  *  associated with it is valid.
  *
- *  @param conn Connection object
+ *  @param conn  @ref BT_CONN_TYPE_LE connection object.
  *  @param oobd_local Local OOB data or NULL if not set
  *  @param oobd_remote Remote OOB data or NULL if not set
  *
  *  @return Zero on success or error code otherwise, positive in case of
  *          protocol error or negative (POSIX) in case of stack internal error.
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE connection.
  */
 int bt_le_oob_get_sc_data(struct bt_conn *conn,
 			  const struct bt_le_oob_sc_data **oobd_local,
@@ -2426,6 +2468,17 @@ struct bt_conn_auth_info_cb {
 	 */
 	void (*bond_deleted)(uint8_t id, const bt_addr_le_t *peer);
 
+#if defined(CONFIG_BT_CLASSIC)
+	/** @brief Notify that bond of classic has been deleted.
+	 *
+	 *  This callback notifies the application that the bond information of classic
+	 *  for the remote peer has been deleted
+	 *
+	 *  @param peer Remote address.
+	 */
+	void (*br_bond_deleted)(const bt_addr_t *peer);
+#endif /* CONFIG_BT_CLASSIC */
+
 	/** Internally used field for list handling */
 	sys_snode_t node;
 };
@@ -2450,10 +2503,11 @@ int bt_conn_auth_cb_register(const struct bt_conn_auth_cb *cb);
  *  security procedures in the SMP module have already started. This function
  *  can be called only once per connection.
  *
- *  @param conn	Connection object.
+ *  @param conn @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection object.
  *  @param cb	Callback struct.
  *
  *  @return Zero on success or negative error code otherwise
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection
  */
 int bt_conn_auth_cb_overlay(struct bt_conn *conn, const struct bt_conn_auth_cb *cb);
 
@@ -2483,10 +2537,11 @@ int bt_conn_auth_info_cb_unregister(struct bt_conn_auth_info_cb *cb);
  *  This function should be called only after passkey_entry callback from
  *  bt_conn_auth_cb structure was called.
  *
- *  @param conn Connection object.
+ *  @param conn @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection object.
  *  @param passkey Entered passkey.
  *
  *  @return Zero on success or negative error code otherwise
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection
  */
 int bt_conn_auth_passkey_entry(struct bt_conn *conn, unsigned int passkey);
 
@@ -2497,13 +2552,14 @@ int bt_conn_auth_passkey_entry(struct bt_conn *conn, unsigned int passkey);
  *
  *  Requires @kconfig{CONFIG_BT_PASSKEY_KEYPRESS}.
  *
- *  @param conn Destination for the notification.
+ *  @param conn @ref BT_CONN_TYPE_LE destination connection for the notification.
  *  @param type What keypress event type to send. @see bt_conn_auth_keypress.
  *
  *  @retval 0 Success
  *  @retval -EINVAL Improper use of the API.
  *  @retval -ENOMEM Failed to allocate.
  *  @retval -ENOBUFS Failed to allocate.
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE connection
  */
 int bt_conn_auth_keypress_notify(struct bt_conn *conn, enum bt_conn_auth_keypress type);
 
@@ -2511,9 +2567,10 @@ int bt_conn_auth_keypress_notify(struct bt_conn *conn, enum bt_conn_auth_keypres
  *
  *  This function allows to cancel ongoing authenticated pairing.
  *
- *  @param conn Connection object.
+ *  @param conn @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection object.
  *
  *  @return Zero on success or negative error code otherwise
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection
  */
 int bt_conn_auth_cancel(struct bt_conn *conn);
 
@@ -2522,9 +2579,10 @@ int bt_conn_auth_cancel(struct bt_conn *conn);
  *  This function should be called only after passkey_confirm callback from
  *  bt_conn_auth_cb structure was called.
  *
- *  @param conn Connection object.
+ *  @param conn @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection object.
  *
  *  @return Zero on success or negative error code otherwise
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection
  */
 int bt_conn_auth_passkey_confirm(struct bt_conn *conn);
 
@@ -2533,9 +2591,10 @@ int bt_conn_auth_passkey_confirm(struct bt_conn *conn);
  *  This function should be called only after pairing_confirm callback from
  *  bt_conn_auth_cb structure was called if user confirmed incoming pairing.
  *
- *  @param conn Connection object.
+ *  @param conn @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection object.
  *
  *  @return Zero on success or negative error code otherwise
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_LE or @ref BT_CONN_TYPE_BR connection
  */
 int bt_conn_auth_pairing_confirm(struct bt_conn *conn);
 
@@ -2544,10 +2603,11 @@ int bt_conn_auth_pairing_confirm(struct bt_conn *conn);
  *  This function should be called only after PIN code callback from
  *  bt_conn_auth_cb structure was called. It's for legacy 2.0 devices.
  *
- *  @param conn Connection object.
+ *  @param conn @ref BT_CONN_TYPE_BR connection object.
  *  @param pin Entered PIN code.
  *
  *  @return Zero on success or negative error code otherwise
+ *  @return -EINVAL @p conn is not a valid @ref BT_CONN_TYPE_BR connection
  */
 int bt_conn_auth_pincode_entry(struct bt_conn *conn, const char *pin);
 
@@ -2595,6 +2655,27 @@ struct bt_br_conn_param {
 struct bt_conn *bt_conn_create_br(const bt_addr_t *peer,
 				  const struct bt_br_conn_param *param);
 
+/** @brief Look up an existing BR connection by address.
+ *
+ *  Look up an existing BR connection based on the remote address.
+ *
+ *  The caller gets a new reference to the connection object which must be
+ *  released with bt_conn_unref() once done using the object.
+ *
+ *  @param peer Remote address.
+ *
+ *  @return Connection object or NULL if not found.
+ */
+struct bt_conn *bt_conn_lookup_addr_br(const bt_addr_t *peer);
+
+/** @brief Get destination (peer) address of a connection.
+ *
+ *  @param conn Connection object.
+ *
+ *  @return Destination address if @p conn is a valid @ref BT_CONN_TYPE_BR connection
+ */
+const bt_addr_t *bt_conn_get_dst_br(const struct bt_conn *conn);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/zephyr/bluetooth/crypto.h b/include/zephyr/bluetooth/crypto.h
index c5cbfd8a0e5..804e496e0e4 100644
--- a/include/zephyr/bluetooth/crypto.h
+++ b/include/zephyr/bluetooth/crypto.h
@@ -19,6 +19,7 @@
  */
 
 #include <stdbool.h>
+#include <stddef.h>
 #include <stdint.h>
 
 #ifdef __cplusplus
diff --git a/include/zephyr/bluetooth/cs.h b/include/zephyr/bluetooth/cs.h
index dfb744bdbcd..be7918da8ba 100644
--- a/include/zephyr/bluetooth/cs.h
+++ b/include/zephyr/bluetooth/cs.h
@@ -22,6 +22,8 @@
 
 #include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/conn.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/util_macro.h>
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/include/zephyr/bluetooth/direction.h b/include/zephyr/bluetooth/direction.h
index 59407bc25d8..dc77a2933c1 100644
--- a/include/zephyr/bluetooth/direction.h
+++ b/include/zephyr/bluetooth/direction.h
@@ -9,6 +9,9 @@
 
 #include <stdint.h>
 
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/sys/util_macro.h>
+
 /** Constant Tone Extension (CTE) types. */
 enum bt_df_cte_type {
 	/** Convenience value for purposes where non of CTE types is allowed. */
diff --git a/include/zephyr/bluetooth/ead.h b/include/zephyr/bluetooth/ead.h
index 8aaee2e4136..5a9ae1e1ecf 100644
--- a/include/zephyr/bluetooth/ead.h
+++ b/include/zephyr/bluetooth/ead.h
@@ -8,8 +8,8 @@
 #ifndef ZEPHYR_INCLUDE_BLUETOOTH_EAD_H_
 #define ZEPHYR_INCLUDE_BLUETOOTH_EAD_H_
 
-#include <zephyr/kernel.h>
 #include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/kernel.h>
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/include/zephyr/bluetooth/gap.h b/include/zephyr/bluetooth/gap.h
index 2582d9fb96c..225f0ecc3cc 100644
--- a/include/zephyr/bluetooth/gap.h
+++ b/include/zephyr/bluetooth/gap.h
@@ -11,8 +11,8 @@
 #ifndef ZEPHYR_INCLUDE_BLUETOOTH_GAP_H_
 #define ZEPHYR_INCLUDE_BLUETOOTH_GAP_H_
 
-#include <zephyr/sys/util_macro.h>
 #include <zephyr/bluetooth/byteorder.h>
+#include <zephyr/sys/util_macro.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -740,7 +740,7 @@ extern "C" {
  */
 
 /** LE PHY types */
-enum {
+enum bt_gap_le_phy {
 	/** Convenience macro for when no PHY is set. */
 	BT_GAP_LE_PHY_NONE                    = 0,
 	/** LE 1M PHY */
@@ -760,7 +760,7 @@ enum {
 };
 
 /** Advertising PDU types */
-enum {
+enum bt_gap_adv_type {
 	/** Scannable and connectable advertising. */
 	BT_GAP_ADV_TYPE_ADV_IND               = 0x00,
 	/** Directed connectable advertising. */
@@ -776,7 +776,7 @@ enum {
 };
 
 /** Advertising PDU properties */
-enum {
+enum bt_gap_adv_prop {
 	/** Connectable advertising. */
 	BT_GAP_ADV_PROP_CONNECTABLE           = BIT(0),
 	/** Scannable advertising. */
@@ -1054,7 +1054,7 @@ enum {
 	(BT_GAP_US_TO_CONN_EVENT_LEN((_event_len) * USEC_PER_MSEC))
 
 /** Constant Tone Extension (CTE) types */
-enum {
+enum bt_gap_cte {
 	/** Angle of Arrival */
 	BT_GAP_CTE_AOA = 0x00,
 	/** Angle of Departure with 1 us slots */
@@ -1066,7 +1066,7 @@ enum {
 };
 
 /** @brief Peripheral sleep clock accuracy (SCA) in ppm (parts per million) */
-enum {
+enum bt_gap_sca {
 	BT_GAP_SCA_UNKNOWN = 0,   /**< Unknown */
 	BT_GAP_SCA_251_500 = 0,   /**< 251 ppm to 500 ppm */
 	BT_GAP_SCA_151_250 = 1,   /**< 151 ppm to 250 ppm */
diff --git a/include/zephyr/bluetooth/gatt.h b/include/zephyr/bluetooth/gatt.h
index 64df43e3c8f..e149ea577c7 100644
--- a/include/zephyr/bluetooth/gatt.h
+++ b/include/zephyr/bluetooth/gatt.h
@@ -22,15 +22,21 @@
 
 #include <stdint.h>
 #include <stddef.h>
+#include <string.h>
 
 #include <sys/types.h>
 
-#include <zephyr/sys/slist.h>
-#include <zephyr/sys/util.h>
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/uuid.h>
 #include <zephyr/bluetooth/att.h>
+#include <zephyr/sys/atomic.h>
 #include <zephyr/sys/iterable_sections.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/toolchain.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -229,7 +235,7 @@ struct bt_gatt_attr {
 	 *  GATT Characteristic Presentation Format descriptor as
 	 *  specified in Core Specification 3.G.3.3.3.5.
 	 *
-	 *  You can define a new Attirubute Type for your application specific
+	 *  You can define a new Attribute Type for your application specific
 	 *  use by generating a new UUID for it.
 	 */
 	const struct bt_uuid *uuid;
@@ -683,7 +689,7 @@ bool bt_gatt_service_is_registered(const struct bt_gatt_service *svc);
 /** @brief to be used as return values for @ref bt_gatt_attr_func_t and @ref bt_gatt_read_func_t
  *  type callbacks.
  */
-enum {
+enum bt_gatt_iter {
 	BT_GATT_ITER_STOP = 0,
 	BT_GATT_ITER_CONTINUE,
 };
@@ -706,8 +712,8 @@ typedef uint8_t (*bt_gatt_attr_func_t)(const struct bt_gatt_attr *attr,
  *
  *  Iterate attributes in the given range matching given UUID and/or data.
  *
- *  @param start_handle Start handle.
- *  @param end_handle End handle. Often set to start_handle + attr_count or
+ *  @param start_handle Start attribute handle.
+ *  @param end_handle End attribute handle. Often set to start_handle + attr_count or
  *  BT_ATT_LAST_ATTRIBUTE_HANDLE.
  *  @param uuid UUID to match, passing NULL skips UUID matching.
  *  @param attr_data Attribute data to match, passing NULL skips data matching.
@@ -725,8 +731,8 @@ void bt_gatt_foreach_attr_type(uint16_t start_handle, uint16_t end_handle,
  *
  *  Iterate attributes in the given range.
  *
- *  @param start_handle Start handle.
- *  @param end_handle End handle.
+ *  @param start_handle Starting attribute handle.
+ *  @param end_handle Ending attribute handle.
  *  @param func Callback function.
  *  @param user_data Data to pass to the callback.
  */
@@ -956,7 +962,7 @@ ssize_t bt_gatt_attr_read_chrc(struct bt_conn *conn,
 			       const struct bt_gatt_attr *attr, void *buf,
 			       uint16_t len, uint16_t offset);
 
-/** @brief Gatt Characterisitc Initialization Macro.
+/** @brief Gatt Characteristic Initialization Macro.
  *
  *  Helper macro used within the @ref BT_GATT_CHARACTERISTIC macro in the GATT attribute declaration
  *  to set the attribute user data.
@@ -1035,8 +1041,14 @@ struct bt_gatt_ccc_cfg {
 	uint16_t value;
 };
 
-/** Internal representation of CCC value */
-struct _bt_gatt_ccc {
+/** Macro to keep old name for deprecation period. */
+#define _bt_gatt_ccc bt_gatt_ccc_managed_user_data __DEPRECATED_MACRO
+
+/** @brief Internal representation of CCC value.
+ *
+ * @note Only use this as an argument for @ref BT_GATT_CCC_MANAGED
+ */
+struct bt_gatt_ccc_managed_user_data {
 	/** Configuration for each connection */
 	struct bt_gatt_ccc_cfg cfg[BT_GATT_CCC_MAX];
 
@@ -1092,8 +1104,8 @@ struct _bt_gatt_ccc {
  *          case of error.
  */
 /** @cond INTERNAL_HIDDEN
- *  @note Only use this with attributes which user_data is a _bt_gatt_ccc.
- *  _bt_gatt_ccc being the internal representation of CCC value.
+ *  @note Only use this with attributes which user_data is a bt_gatt_ccc_managed_user_data.
+ *        @ref bt_gatt_ccc_managed_user_data being the internal representation of CCC value.
  */
  /** @endcond */
 ssize_t bt_gatt_attr_read_ccc(struct bt_conn *conn,
@@ -1115,14 +1127,17 @@ ssize_t bt_gatt_attr_read_ccc(struct bt_conn *conn,
  *          case of error.
  */
 /** @cond INTERNAL_HIDDEN
- *  @note Only use this with attributes which user_data is a _bt_gatt_ccc.
- *  _bt_gatt_ccc being the internal representation of CCC value.
+ *  @note Only use this with attributes which user_data is a bt_gatt_ccc_managed_user_data.
+ *        @ref bt_gatt_ccc_managed_user_data being the internal representation of CCC value.
  */
 /** @endcond */
 ssize_t bt_gatt_attr_write_ccc(struct bt_conn *conn,
 			       const struct bt_gatt_attr *attr, const void *buf,
 			       uint16_t len, uint16_t offset, uint8_t flags);
 
+/** Macro to keep old name for deprecation period. */
+#define BT_GATT_CCC_INITIALIZER BT_GATT_CCC_MANAGED_USER_DATA_INIT __DEPRECATED_MACRO
+
 /**
  *  @brief Initialize Client Characteristic Configuration Declaration Macro.
  *
@@ -1132,12 +1147,12 @@ ssize_t bt_gatt_attr_write_ccc(struct bt_conn *conn,
  *  @param _write Configuration write callback.
  *  @param _match Configuration match callback.
  */
-#define BT_GATT_CCC_INITIALIZER(_changed, _write, _match) \
-	{                                            \
-		.cfg = {},                           \
-		.cfg_changed = _changed,             \
-		.cfg_write = _write,                 \
-		.cfg_match = _match,                 \
+#define BT_GATT_CCC_MANAGED_USER_DATA_INIT(_changed, _write, _match)                               \
+	{                                                                                          \
+		.cfg = {},                                                                         \
+		.cfg_changed = _changed,                                                           \
+		.cfg_write = _write,                                                               \
+		.cfg_match = _match,                                                               \
 	}
 
 /**
@@ -1145,7 +1160,10 @@ ssize_t bt_gatt_attr_write_ccc(struct bt_conn *conn,
  *
  *  Helper macro to declare a Managed CCC attribute.
  *
- *  @param _ccc CCC attribute user data, shall point to a _bt_gatt_ccc.
+ *  @param _ccc A new @ref bt_gatt_ccc_managed_user_data object with the same lifetime
+ *              as the results of the call to BT_GATT_CCC_MANAGED.
+ *              See the documentation of @ref bt_gatt_ccc_managed_user_data on how
+ *              to initialize it.
  *  @param _perm CCC access permissions,
  *               a bitmap of @ref bt_gatt_perm values.
  */
@@ -1163,9 +1181,10 @@ ssize_t bt_gatt_attr_write_ccc(struct bt_conn *conn,
  *  @param _perm CCC access permissions,
  *               a bitmap of @ref bt_gatt_perm values.
  */
-#define BT_GATT_CCC(_changed, _perm)				\
-	BT_GATT_CCC_MANAGED(((struct _bt_gatt_ccc[])			\
-		{BT_GATT_CCC_INITIALIZER(_changed, NULL, NULL)}), _perm)
+#define BT_GATT_CCC(_changed, _perm)                                                               \
+	BT_GATT_CCC_MANAGED(((struct bt_gatt_ccc_managed_user_data[]){                             \
+				    BT_GATT_CCC_MANAGED_USER_DATA_INIT(_changed, NULL, NULL)}),    \
+			    _perm)
 
 /**
  *  @brief Client Characteristic Configuration Declaration Macro with write callback.
@@ -1177,9 +1196,10 @@ ssize_t bt_gatt_attr_write_ccc(struct bt_conn *conn,
  *  @param _perm CCC access permissions,
  *               a bitmap of @ref bt_gatt_perm values.
  */
-#define BT_GATT_CCC_WITH_WRITE_CB(_changed, _write, _perm)		\
-	BT_GATT_CCC_MANAGED(((struct _bt_gatt_ccc[])			\
-		{BT_GATT_CCC_INITIALIZER(_changed, _write, NULL) }), _perm)
+#define BT_GATT_CCC_WITH_WRITE_CB(_changed, _write, _perm)                                         \
+	BT_GATT_CCC_MANAGED(((struct bt_gatt_ccc_managed_user_data[]){                             \
+				    BT_GATT_CCC_MANAGED_USER_DATA_INIT(_changed, _write, NULL)}),  \
+			    _perm)
 
 /** @brief Read Characteristic Extended Properties Attribute helper
  *
@@ -1655,7 +1675,7 @@ uint16_t bt_gatt_get_uatt_mtu(struct bt_conn *conn);
 
 /** @brief GATT Exchange MTU parameters
  *
- *  Used with @ref bt_gatt_exchange_mtu() to initiate an MTU exchange. The
+ *  Used with @ref bt_gatt_exchange_mtu function to initiate an MTU exchange. The
  *  response is handled in the callback @p func, which is called upon
  *  completion from the 'config BT_RECV_CONTEXT' context.
  *
@@ -1710,7 +1730,7 @@ struct bt_gatt_discover_params;
  *  The attribute object as well as its UUID and value objects are temporary and
  *  must be copied to in order to cache its information.
  *
- *  @note @ref bt_gatt_attr is given as an argument to bt_gatt_discover(), but
+ *  @note @ref bt_gatt_attr is given as an argument to @ref bt_gatt_discover function, but
  *  it's not a proper object of this type. @ref bt_gatt_attr.perm, and methods
  *  bt_gatt_attr.read() and bt_gatt_attr.write() are not available, and it's
  *  unsound to pass the pointer to GATT server APIs.
@@ -1807,15 +1827,20 @@ struct bt_gatt_discover_params {
 		struct {
 			/** Include service attribute declaration handle */
 			uint16_t attr_handle;
-			/** Included service start handle */
+			/** Starting attribute handle for included service */
 			uint16_t start_handle;
-			/** Included service end handle */
+			/** Ending attribute handle for included service */
 			uint16_t end_handle;
 		} _included;
-		/** Discover start handle */
+		/** Starting attribute handle to begin discovery */
 		uint16_t start_handle;
 	};
-	/** Discover end handle */
+	/** @brief Ending attribute handle to stop discovery at
+	 *
+	 * @note When discovery begins this can be set to
+	 * @ref BT_ATT_LAST_ATTRIBUTE_HANDLE to discover all attributes
+	 * in the service.
+	 */
 	uint16_t end_handle;
 	/** Discover type */
 	uint8_t type;
@@ -1920,9 +1945,27 @@ struct bt_gatt_read_params {
 			bool variable;
 		} multiple;
 		struct {
-			/** Attribute handle to start reading from. */
+			/** @brief Requested start attribute handle number.
+			 *
+			 * @details The starting handle is set to the starting point of the range
+			 * over which this read should be performed. For example, this could be
+			 * set to @ref BT_ATT_FIRST_ATTRIBUTE_HANDLE to set the starting point of
+			 * the range at the beginning of the GATT database, or to the starting
+			 * handle of a service after discovery.
+			 *
+			 * This value is automatically incremented by the stack after
+			 * processing each matching handle-value pair returned by the server.
+			 */
 			uint16_t start_handle;
-			/** Attribute handle to stop reading at. */
+			/** @brief Requested end attribute handle number.
+			 *
+			 * @details The end handle is set to the ending point of the range over
+			 * which this read should be performed. For example, this could be set to
+			 * @ref BT_ATT_LAST_ATTRIBUTE_HANDLE to set the ending point of the range
+			 * at the end of the GATT database, or to the end handle for service after
+			 * discovery, where the end_handle is available in the
+			 * @ref bt_gatt_service_val.
+			 */
 			uint16_t end_handle;
 			/** 2 or 16 octet UUID. */
 			const struct bt_uuid *uuid;
diff --git a/include/zephyr/bluetooth/hci.h b/include/zephyr/bluetooth/hci.h
index 7687abdb631..590ea55a84a 100644
--- a/include/zephyr/bluetooth/hci.h
+++ b/include/zephyr/bluetooth/hci.h
@@ -9,8 +9,10 @@
 #define ZEPHYR_INCLUDE_BLUETOOTH_HCI_H_
 
 #include <stdbool.h>
+#include <stddef.h>
 #include <stdint.h>
 
+#include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/net_buf.h>
 #include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/conn.h>
@@ -37,6 +39,8 @@ extern "C" {
 #if defined(CONFIG_BT_HCI_ERR_TO_STR)
 const char *bt_hci_err_to_str(uint8_t hci_err);
 #else
+#include <zephyr/toolchain.h>
+
 static inline const char *bt_hci_err_to_str(uint8_t hci_err)
 {
 	ARG_UNUSED(hci_err);
diff --git a/include/zephyr/bluetooth/hci_raw.h b/include/zephyr/bluetooth/hci_raw.h
index 8a0b4a37680..3671d1bcb54 100644
--- a/include/zephyr/bluetooth/hci_raw.h
+++ b/include/zephyr/bluetooth/hci_raw.h
@@ -18,6 +18,10 @@
  */
 
 #include <stdint.h>
+#include <stddef.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/net_buf.h>
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/include/zephyr/bluetooth/hci_types.h b/include/zephyr/bluetooth/hci_types.h
index 580385b4127..94693b94757 100644
--- a/include/zephyr/bluetooth/hci_types.h
+++ b/include/zephyr/bluetooth/hci_types.h
@@ -11,12 +11,12 @@
 
 #include <stdbool.h>
 #include <stdint.h>
-#include <string.h>
 
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
 #include <zephyr/toolchain.h>
 #include <zephyr/types.h>
-#include <zephyr/sys/util.h>
-#include <zephyr/bluetooth/addr.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -592,6 +592,12 @@ struct bt_hci_rp_write_conn_accept_timeout {
 #define BT_BREDR_SCAN_INQUIRY                   0x01
 #define BT_BREDR_SCAN_PAGE                      0x02
 
+#define BT_HCI_OP_READ_CLASS_OF_DEVICE          BT_OP(BT_OGF_BASEBAND, 0x0023) /* 0x0c23 */
+struct bt_hci_rp_read_class_of_device {
+	uint8_t  status;
+	uint8_t  class_of_device[3];
+} __packed;
+
 #define BT_COD(major_service, major_device, minor_device)                         \
 	(((uint32_t)major_service << 13) | ((uint32_t)major_device << 8) |            \
 	 ((uint32_t)minor_device << 2))
@@ -766,6 +772,16 @@ struct bt_hci_cp_host_num_completed_packets {
 	struct bt_hci_handle_count h[0];
 } __packed;
 
+#define BT_HCI_OP_WRITE_CURRENT_IAC_LAP         BT_OP(BT_OGF_BASEBAND, 0x003a) /* 0x0c3a */
+struct bt_hci_iac_lap {
+	uint8_t iac[3];
+} __packed;
+
+struct bt_hci_cp_write_current_iac_lap {
+	uint8_t  num_current_iac;
+	struct bt_hci_iac_lap lap[0];
+} __packed;
+
 #define BT_HCI_OP_WRITE_INQUIRY_MODE            BT_OP(BT_OGF_BASEBAND, 0x0045) /* 0x0c45 */
 struct bt_hci_cp_write_inquiry_mode {
 	uint8_t  mode;
@@ -2788,6 +2804,12 @@ struct bt_hci_evt_remote_name_req_complete {
 	uint8_t   name[248];
 } __packed;
 
+/* Encryption Value */
+#define BT_HCI_ENCRYPTION_OFF           0x00
+#define BT_HCI_ENCRYPTION_ON_LE_AES_CCM 0x01
+#define BT_HCI_ENCRYPTION_ON_BR_E0      0x01
+#define BT_HCI_ENCRYPTION_ON_BR_AES_CCM 0x02
+
 #define BT_HCI_EVT_ENCRYPT_CHANGE               0x08
 struct bt_hci_evt_encrypt_change {
 	uint8_t  status;
diff --git a/include/zephyr/bluetooth/hci_vs.h b/include/zephyr/bluetooth/hci_vs.h
index dabbe2902ea..1170c41474a 100644
--- a/include/zephyr/bluetooth/hci_vs.h
+++ b/include/zephyr/bluetooth/hci_vs.h
@@ -11,7 +11,10 @@
 
 #include <stdint.h>
 
+#include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/net_buf.h>
 
 #ifdef __cplusplus
 extern "C" {
diff --git a/include/zephyr/bluetooth/iso.h b/include/zephyr/bluetooth/iso.h
index ff62661b9e8..3237a3b9bc3 100644
--- a/include/zephyr/bluetooth/iso.h
+++ b/include/zephyr/bluetooth/iso.h
@@ -5,7 +5,7 @@
 
 /*
  * Copyright (c) 2020 Intel Corporation
- * Copyright (c) 2021-2024 Nordic Semiconductor ASA
+ * Copyright (c) 2021-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -24,6 +24,7 @@
  */
 
 #include <stdint.h>
+#include <stddef.h>
 
 #include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/bluetooth.h>
@@ -70,6 +71,14 @@ extern "C" {
 
 /** Unknown SDU interval */
 #define BT_ISO_SDU_INTERVAL_UNKNOWN 0x000000U
+/** The minimum value for vendor specific data path ID */
+#define BT_ISO_DATA_PATH_VS_ID_MIN  0x01
+/** The maximum value for vendor specific data path ID */
+#define BT_ISO_DATA_PATH_VS_ID_MAX  0xFE
+/** Minimum controller delay in microseconds (0 s) */
+#define BT_ISO_CONTROLLER_DELAY_MIN 0x000000
+/** Maximum controller delay in microseconds (4 s) */
+#define BT_ISO_CONTROLLER_DELAY_MAX 0x3D0900
 /** Minimum interval value in microseconds */
 #define BT_ISO_SDU_INTERVAL_MIN     0x0000FFU
 /** Maximum interval value in microseconds */
@@ -178,7 +187,8 @@ enum bt_iso_state {
  */
 enum bt_iso_chan_type {
 	BT_ISO_CHAN_TYPE_NONE,		/**< No channel type */
-	BT_ISO_CHAN_TYPE_CONNECTED,	/**< Connected */
+	BT_ISO_CHAN_TYPE_CENTRAL,       /**< Connected as central */
+	BT_ISO_CHAN_TYPE_PERIPHERAL,    /**< Connected as peripheral */
 	BT_ISO_CHAN_TYPE_BROADCASTER,	/**< Isochronous broadcaster */
 	BT_ISO_CHAN_TYPE_SYNC_RECEIVER	/**< Synchronized receiver */
 };
@@ -219,7 +229,7 @@ struct bt_iso_chan_io_qos {
 	 */
 	uint16_t			sdu;
 	/**
-	 * @brief Channel PHY - See the BT_GAP_LE_PHY_* values.
+	 * @brief Channel PHY - See the @ref bt_gap_le_phy values.
 	 *
 	 * Setting @ref BT_GAP_LE_PHY_NONE is invalid.
 	 */
@@ -230,13 +240,6 @@ struct bt_iso_chan_io_qos {
 	 * This value is ignored if any advanced ISO parameters are set.
 	 */
 	uint8_t				rtn;
-	/**
-	 * @brief Channel data path reference
-	 *
-	 * Setting to NULL default to HCI data path (same as setting path.pid
-	 * to @ref BT_ISO_DATA_PATH_HCI).
-	 */
-	struct bt_iso_chan_path		*path;
 
 #if defined(CONFIG_BT_ISO_TEST_PARAMS) || defined(__DOXYGEN__)
 	/**
@@ -293,20 +296,37 @@ struct bt_iso_chan_qos {
 
 /** @brief ISO Channel Data Path structure. */
 struct bt_iso_chan_path {
-	/** Default path ID */
-	uint8_t				pid;
-	/** Coding Format */
-	uint8_t				format;
+	/**
+	 * @brief Default path ID
+	 *
+	 * @ref BT_ISO_DATA_PATH_HCI to use ISO over  HCI or between @ref BT_ISO_DATA_PATH_VS_ID_MIN
+	 * and @ref BT_ISO_DATA_PATH_VS_ID_MAX for vendor specific data paths.
+	 */
+	uint8_t pid;
+	/**
+	 * @brief Coding Format
+	 *
+	 * See the BT_HCI_CODING_FORMAT_* values for valid values.
+	 */
+	uint8_t format;
 	/** Company ID */
-	uint16_t			cid;
+	uint16_t cid;
 	/** Vendor-defined Codec ID */
-	uint16_t			vid;
-	/** Controller Delay */
-	uint32_t			delay;
-	/** Codec Configuration length*/
-	uint8_t				cc_len;
-	/** Pointer to an array containing the Codec Configuration */
-	uint8_t				*cc;
+	uint16_t vid;
+	/**
+	 * @brief Controller Delay in microseconds
+	 *
+	 * Value range from @ref BT_ISO_CONTROLLER_DELAY_MIN to @ref BT_ISO_CONTROLLER_DELAY_MAX.
+	 */
+	uint32_t delay;
+	/** Codec Configuration length */
+	uint8_t cc_len;
+	/**
+	 * @brief Pointer to an array containing the Codec Configuration
+	 *
+	 * Shall not be NULL if bt_iso_chan_path.cc_len is non-zero.
+	 */
+	uint8_t *cc;
 };
 
 /** ISO packet status flag bits */
@@ -413,7 +433,7 @@ struct bt_iso_cig_param {
 	 * @brief Channel peripherals sleep clock accuracy Only for CIS
 	 *
 	 * Shall be worst case sleep clock accuracy of all the peripherals.
-	 * For possible values see the BT_GAP_SCA_* values.
+	 * For possible values, see @ref bt_gap_sca.
 	 * If unknown for the peripherals, this should be set to @ref BT_GAP_SCA_UNKNOWN.
 	 */
 	uint8_t sca;
@@ -691,6 +711,14 @@ struct bt_iso_chan_ops {
 	 * channel is disconnected, including when a connection gets
 	 * rejected or when setting security fails.
 	 *
+	 * If the channel was established (i.e. @ref bt_iso_chan_ops.connected has been called
+	 * for this channel), then the channel object is still valid and the memory of the channel
+	 * shall not be memset to 0 or otherwise free'd.
+	 * To avoid any issues it is recommended to use a @ref k_work_submit or similar to not
+	 * overwrite any data while in the callback.
+	 *
+	 * For the above reason it is still possible to use bt_iso_chan_get_info() on the @p chan.
+	 *
 	 * @param chan   The channel that has been Disconnected
 	 * @param reason BT_HCI_ERR_* reason for the disconnection.
 	 */
@@ -957,6 +985,70 @@ int bt_iso_chan_send(struct bt_iso_chan *chan, struct net_buf *buf, uint16_t seq
 int bt_iso_chan_send_ts(struct bt_iso_chan *chan, struct net_buf *buf, uint16_t seq_num,
 			uint32_t ts);
 
+/**
+ * @brief Sets up the ISO data path for a ISO channel
+ *
+ * The channel must be associated with a BIS or CIS handle first which it is when the
+ * bt_iso_chan_ops.connected() callback is called.
+ *
+ * @param chan The channel to setup the ISO data path for
+ * @param dir The direction to setup, either @ref BT_HCI_DATAPATH_DIR_CTLR_TO_HOST or
+ *            @ref BT_HCI_DATAPATH_DIR_HOST_TO_CTLR. For ISO broadcast channels this can only be
+ *            @ref BT_HCI_DATAPATH_DIR_HOST_TO_CTLR, and for ISO sync receiver channels this can
+ *            only be @ref BT_HCI_DATAPATH_DIR_CTLR_TO_HOST.
+ * @param path The data path
+ *
+ * @retval 0 Success
+ * @retval -EINVAL Invalid parameters
+ * @retval -ENOBUFS No HCI command buffer could be allocated
+ * @retval -EIO The controller rejected the request or response contains invalid data
+ * @retval -ENODEV @p chan is not associated with a CIS or BIS handle
+ * @retval -EACCES The controller rejected the request as disallowed
+ * @retval -ENOEXEC Unexpected error occurred
+ */
+int bt_iso_setup_data_path(const struct bt_iso_chan *chan, uint8_t dir,
+			   const struct bt_iso_chan_path *path);
+
+/**
+ * @brief Removes the ISO data path for a ISO channel
+ *
+ * Removes the ISO data path configured by bt_iso_setup_data_path() for the provided @p dir.
+ *
+ * The data paths of CIS for Peripherals are deleted by the controller,
+ * and thus it is not necessary (or possible) to remove
+ * data paths of CIS after they have disconnected for a Peripheral,
+ * as per Bluetooth Core specification 6.0, Vol 4, Part E, Section 7.7.5.
+ * The data paths for CIS for a Central remain valid, even after a disconnection, and thus a Central
+ * device should call bt_iso_remove_data_path() on disconnect if it no longer wants to use that CIS.
+ * All data paths created by a Central are removed when the CIG is removed with
+ * bt_iso_cig_terminate().
+ *
+ * Any data paths associated with an ISO Sync Receiver BIG are removed by the controller
+ * when the BIG sync is lost or terminated, and thus it is not necessary (or possible) to remove
+ * data paths of ISO channels associated with a BIG for a Sync Receiver,
+ * as per Bluetooth Core specification 6.0, Vol 4, Part E, Section 7.7.65.30
+ *
+ * All data paths associated with an ISO Broadcaster BIG are removed when the BIG is terminated by
+ * bt_iso_big_terminate(), and thus it is not necessary (or possible) to remove data paths of ISO
+ * channels associated with a BIG for a Broadcaster,
+ * as per Bluetooth Core specification 6.0, Vol 4, Part E, Section 7.8.105
+ *
+ * @param chan The channel to setup the ISO data path for
+ * @param dir The direction to setup, either @ref BT_HCI_DATAPATH_DIR_CTLR_TO_HOST or
+ *            @ref BT_HCI_DATAPATH_DIR_HOST_TO_CTLR. For ISO broadcast channels this can only be
+ *            @ref BT_HCI_DATAPATH_DIR_HOST_TO_CTLR, and for ISO sync receiver channels this can
+ *            only be @ref BT_HCI_DATAPATH_DIR_CTLR_TO_HOST.
+
+ * @retval 0 Success
+ * @retval -EINVAL Invalid parameters
+ * @retval -ENOBUFS No HCI command buffer could be allocated
+ * @retval -EIO The controller rejected the request or response contains invalid data
+ * @retval -ENODEV @p chan is not associated with a CIS or BIS handle
+ * @retval -EACCES The controller rejected the request as disallowed
+ * @retval -ENOEXEC Unexpected error occurred
+ */
+int bt_iso_remove_data_path(const struct bt_iso_chan *chan, uint8_t dir);
+
 /** @brief ISO Unicast TX Info Structure */
 struct bt_iso_unicast_tx_info {
 	/** The transport latency in us */
@@ -1082,20 +1174,30 @@ struct bt_iso_info {
 	/** Connection Type specific Info.*/
 	union {
 #if defined(CONFIG_BT_ISO_UNICAST) || defined(__DOXYGEN__)
-		/** Unicast specific Info.
+		/**
+		 * @brief Unicast specific Info.
+		 *
 		 * Only available when @kconfig{CONFIG_BT_ISO_UNICAST} is enabled.
+		 * Use this when the @ref bt_iso_info.type is @ref BT_ISO_CHAN_TYPE_CENTRAL or
+		 * @ref BT_ISO_CHAN_TYPE_PERIPHERAL.
 		 */
 		struct bt_iso_unicast_info unicast;
 #endif /* CONFIG_BT_ISO_UNICAST */
 #if defined(CONFIG_BT_ISO_BROADCASTER) || defined(__DOXYGEN__)
-		/** Broadcaster specific Info.
+		/**
+		 * @brief Broadcaster specific Info.
+		 *
 		 * Only available when @kconfig{CONFIG_BT_ISO_BROADCASTER} is enabled.
+		 * Use this when the @ref bt_iso_info.type is @ref BT_ISO_CHAN_TYPE_BROADCASTER.
 		 */
 		struct bt_iso_broadcaster_info broadcaster;
 #endif /* CONFIG_BT_ISO_BROADCASTER */
 #if defined(CONFIG_BT_ISO_SYNC_RECEIVER) || defined(__DOXYGEN__)
-		/** Sync receiver specific Info.
+		/**
+		 * @brief Sync receiver specific Info.
+		 *
 		 * Only available when @kconfig{CONFIG_BT_ISO_SYNC_RECEIVER} is enabled.
+		 * Use this when the @ref bt_iso_info.type is @ref BT_ISO_CHAN_TYPE_SYNC_RECEIVER.
 		 */
 		struct bt_iso_sync_receiver_info sync_receiver;
 #endif /* CONFIG_BT_ISO_SYNC_RECEIVER */
diff --git a/include/zephyr/bluetooth/l2cap.h b/include/zephyr/bluetooth/l2cap.h
index 8358d62c309..f8781d791f0 100644
--- a/include/zephyr/bluetooth/l2cap.h
+++ b/include/zephyr/bluetooth/l2cap.h
@@ -18,13 +18,18 @@
  * @{
  */
 
+#include <stddef.h>
 #include <stdint.h>
-#include <sys/types.h>
 
-#include <zephyr/sys/atomic.h>
 #include <zephyr/bluetooth/buf.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/hci.h>
+#include <zephyr/kernel.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/sys/util.h>
+#include <sys/types.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -271,42 +276,219 @@ struct bt_l2cap_le_chan {
  */
 #define BT_L2CAP_LE_CHAN(_ch) CONTAINER_OF(_ch, struct bt_l2cap_le_chan, chan)
 
+/** L2CAP Endpoint Link Mode. Basic mode. */
+#define BT_L2CAP_BR_LINK_MODE_BASIC  0x00
+/** L2CAP Endpoint Link Mode. Retransmission mode. */
+#define BT_L2CAP_BR_LINK_MODE_RET    0x01
+/** L2CAP Endpoint Link Mode. Flow control mode. */
+#define BT_L2CAP_BR_LINK_MODE_FC     0x02
+/** L2CAP Endpoint Link Mode. Enhance retransmission mode. */
+#define BT_L2CAP_BR_LINK_MODE_ERET   0x03
+/** L2CAP Endpoint Link Mode. Streaming mode. */
+#define BT_L2CAP_BR_LINK_MODE_STREAM 0x04
+
+/** Frame Check Sequence type. No FCS. */
+#define BT_L2CAP_BR_FCS_NO    0x00
+/** Frame Check Sequence type. 16-bit FCS. */
+#define BT_L2CAP_BR_FCS_16BIT 0x01
+
 /** @brief BREDR L2CAP Endpoint structure. */
 struct bt_l2cap_br_endpoint {
 	/** Endpoint Channel Identifier (CID) */
-	uint16_t				cid;
+	uint16_t                                cid;
 	/** Endpoint Maximum Transmission Unit */
-	uint16_t				mtu;
+	uint16_t                                mtu;
+#if defined(CONFIG_BT_L2CAP_RET_FC) || defined(__DOXYGEN__)
+	/** Endpoint Link Mode.
+	 *  The value is defined as BT_L2CAP_BR_LINK_MODE_*
+	 */
+	uint8_t                                 mode;
+	/** Whether Endpoint Link Mode is optional
+	 * If the `optional` is true, the `mode` could be
+	 * changed according to the extended feature and
+	 * peer configuration from L2CAP configuration
+	 * response and request.
+	 * Otherwise, if the channel configuration process
+	 * does not meet the set mode, the L2CAP channel
+	 * will be disconnected.
+	 */
+	bool                                    optional;
+	/** Endpoint Maximum Transmit
+	 * The field is used to set the max retransmission
+	 * count.
+	 * For `RET`, `FC`, and `ERET`, it should be not
+	 * less 1.
+	 * For `STREAM`, it should be 0.
+	 */
+	uint8_t                                 max_transmit;
+	/** Endpoint Retransmission Timeout
+	 * The field is configured by
+	 * `@kconfig{BT_L2CAP_BR_RET_TIMEOUT}`
+	 * The field should be no more than the field
+	 * `monitor_timeout`.
+	 */
+	uint16_t                                ret_timeout;
+	/** Endpoint Monitor Timeout
+	 * The field is configured by
+	 * `@kconfig{BT_L2CAP_BR_MONITOR_TIMEOUT}`
+	 */
+	uint16_t                                monitor_timeout;
+	/** Endpoint Maximum PDU payload Size */
+	uint16_t                                mps;
+	/** Endpoint Maximum Window Size
+	 * MAX supported window size is configured by
+	 * `@kconfig{BT_L2CAP_MAX_WINDOW_SIZE}`. The field
+	 * should be no more then `CONFIG_BT_L2CAP_MAX_WINDOW_SIZE`.
+	 */
+	uint16_t                                max_window;
+	/** Endpoint FCS Type
+	 * The value is defined as BT_L2CAP_BR_FCS_*
+	 * The default setting should be BT_L2CAP_BR_FCS_16BIT.
+	 * For FC and RET, the FCS type should be
+	 * BT_L2CAP_BR_FCS_16BIT.
+	 * For ERET and STREAM, the FCS type is optional. If
+	 * the field is not default value, the local will include
+	 * FCS option in configuration request packet if both side
+	 * support `FCS Option`.
+	 */
+	uint8_t                                 fcs;
+	/** Endpoint Extended Control.
+	 * If this field is true, and both side support
+	 * `Extended Window size feature`, the local will
+	 * include `extended window size` option in configuration
+	 * request packet.
+	 */
+	bool                                    extended_control;
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+};
+
+/** I-Frame transmission window for none `BASIC` mode L2cap connected channel. */
+struct bt_l2cap_br_window {
+	sys_snode_t node;
+
+	/** tx seq */
+	uint16_t tx_seq;
+	/** data len */
+	uint16_t len;
+	/** data address */
+	uint8_t *data;
+	/** Transmit Counter */
+	uint8_t transmit_counter;
+	/** SAR flag */
+	uint8_t sar;
+	/** srej flag */
+	bool srej;
+	/* Save PDU state */
+	struct net_buf_simple_state sdu_state;
+	/** @internal Holds the sending buffer. */
+	struct net_buf *sdu;
+	/** @internal Total length of TX SDU */
+	uint16_t sdu_total_len;
 };
 
 /** @brief BREDR L2CAP Channel structure. */
 struct bt_l2cap_br_chan {
 	/** Common L2CAP channel reference object */
-	struct bt_l2cap_chan		chan;
+	struct bt_l2cap_chan            chan;
 	/** Channel Receiving Endpoint */
-	struct bt_l2cap_br_endpoint	rx;
+	struct bt_l2cap_br_endpoint     rx;
 	/** Channel Transmission Endpoint */
-	struct bt_l2cap_br_endpoint	tx;
+	struct bt_l2cap_br_endpoint     tx;
 	/* For internal use only */
-	atomic_t			flags[1];
+	atomic_t                        flags[1];
 
-	bt_l2cap_chan_state_t		state;
+	bt_l2cap_chan_state_t           state;
 	/** Remote PSM to be connected */
-	uint16_t			psm;
+	uint16_t                        psm;
 	/** Helps match request context during CoC */
-	uint8_t				ident;
-	bt_security_t			required_sec_level;
+	uint8_t                         ident;
+	bt_security_t                   required_sec_level;
 
 	/* Response Timeout eXpired (RTX) timer */
-	struct k_work_delayable		rtx_work;
-	struct k_work_sync		rtx_sync;
+	struct k_work_delayable	        rtx_work;
+	struct k_work_sync              rtx_sync;
 
 	/** @internal To be used with @ref bt_conn.upper_data_ready */
-	sys_snode_t			_pdu_ready;
+	sys_snode_t                     _pdu_ready;
 	/** @internal To be used with @ref bt_conn.upper_data_ready */
-	atomic_t			_pdu_ready_lock;
-	/** @internal Queue of net bufs not yet sent to lower layer */
-	struct k_fifo			_pdu_tx_queue;
+	atomic_t                        _pdu_ready_lock;
+	/** @internal List of net bufs not yet sent to lower layer */
+	sys_slist_t                     _pdu_tx_queue;
+
+#if defined(CONFIG_BT_L2CAP_RET_FC) || defined(__DOXYGEN__)
+	/** @internal Total length of TX SDU */
+	uint16_t                        _sdu_total_len;
+
+	/** @internal Holds the remaining length of current sending buffer */
+	size_t                          _pdu_remaining;
+
+	/** @internal Holds the sending buffer. */
+	struct net_buf                  *_pdu_buf;
+
+	/** @internal TX windows for outstanding frame */
+	sys_slist_t                     _pdu_outstanding;
+
+	/** @internal PDU restore state */
+	struct net_buf_simple_state     _pdu_state;
+
+	/** @internal Free TX windows */
+	struct k_fifo                   _free_tx_win;
+
+	/** @internal TX windows */
+	struct bt_l2cap_br_window       tx_win[CONFIG_BT_L2CAP_MAX_WINDOW_SIZE];
+
+	/** Segment SDU packet from upper layer */
+	struct net_buf                  *_sdu;
+	/** @internal RX SDU */
+	uint16_t                        _sdu_len;
+#if defined(CONFIG_BT_L2CAP_SEG_RECV) || defined(__DOXYGEN__)
+	uint16_t                        _sdu_len_done;
+#endif /* CONFIG_BT_L2CAP_SEG_RECV */
+	/** @internal variables and sequence numbers */
+	/** @internal The sending peer uses the following variables and sequence
+	 * numbers.
+	 */
+	/** @internal The send sequence number used to sequentially number each
+	 * new I-frame transmitted.
+	 */
+	uint16_t                        tx_seq;
+	/** @internal The sequence number to be used in the next new I-frame
+	 * transmitted.
+	 */
+	uint16_t                        next_tx_seq;
+	/** @internal The sequence number of the next I-frame expected to be
+	 * acknowledged by the receiving peer.
+	 */
+	uint16_t                        expected_ack_seq;
+	/** @internal The receiving peer uses the following variables and sequence
+	 * numbers.
+	 */
+	/** @internal The sequence number sent in an acknowledgment frame to
+	 * request transmission of I-frame with TxSeq = ReqSeq and acknowledge
+	 * receipt of I-frames up to and including (ReqSeq-1).
+	 */
+	uint16_t                        req_seq;
+	/** @internal The value of TxSeq expected in the next I-frame.
+	 */
+	uint16_t                        expected_tx_seq;
+	/** @internal When segmented I-frames are buffered this is used to delay
+	 * acknowledgment of received I-frame so that new I-frame transmissions do
+	 * not cause buffer overflow.
+	 */
+	uint16_t                        buffer_seq;
+
+	/** @internal States of Enhanced Retransmission Mode */
+	/** @internal Holds the number of times an S-frame operation is retried
+	 */
+	uint16_t                        retry_count;
+	/** @internal save the ReqSeq of a SREJ frame */
+	uint16_t                        srej_save_req_seq;
+
+	/** @internal Retransmission Timer */
+	struct k_work_delayable         ret_work;
+	/** @internal Monitor Timer */
+	struct k_work_delayable         monitor_work;
+#endif /* CONFIG_BT_L2CAP_RET_FC */
 };
 
 /** @brief L2CAP Channel operations structure.
@@ -490,7 +672,7 @@ struct bt_l2cap_chan_ops {
 struct bt_l2cap_server {
 	/** @brief Server PSM.
 	 *
-	 *  Possible values:
+	 *  For LE, possible values:
 	 *  0               A dynamic value will be auto-allocated when
 	 *                  bt_l2cap_server_register() is called.
 	 *
@@ -500,6 +682,22 @@ struct bt_l2cap_server {
 	 *                  application before server registration (not
 	 *                  recommended however), or auto-allocated by the
 	 *                  stack if the app gave 0 as the value.
+	 *
+	 *  For BR, possible values:
+	 *
+	 *  The PSM field is at least two octets in length. All PSM values shall have the least
+	 *  significant bit of the most significant octet equal to 0 and the least significant bit
+	 *  of all other octets equal to 1.
+	 *
+	 *  0               A dynamic value will be auto-allocated when
+	 *                  bt_l2cap_br_server_register() is called.
+	 *
+	 *  0x0001-0x0eff   Standard, Bluetooth SIG-assigned fixed values.
+	 *
+	 *  > 0x1000        Dynamically allocated. May be pre-set by the
+	 *                  application before server registration (not
+	 *                  recommended however), or auto-allocated by the
+	 *                  stack if the app gave 0 as the value.
 	 */
 	uint16_t			psm;
 
@@ -556,6 +754,15 @@ int bt_l2cap_server_register(struct bt_l2cap_server *server);
  *  the accept() callback which in case of success shall allocate the channel
  *  structure to be used by the new connection.
  *
+ *  For fixed, SIG-assigned PSMs (in the range 0x0001-0x0eff) the PSM should
+ *  be assigned to server->psm before calling this API. For dynamic PSMs
+ *  (in the range 0x1000-0xffff) server->psm may be pre-set to a given value
+ *  (this is however not recommended) or be left as 0, in which case upon
+ *  return a newly allocated value will have been assigned to it. For
+ *  dynamically allocated values the expectation is that it's exposed through
+ *  a SDP record, and that's how L2CAP clients discover how to connect to
+ *  the server.
+ *
  *  @param server Server structure.
  *
  *  @return 0 in case of success or negative value in case of error.
diff --git a/include/zephyr/bluetooth/uuid.h b/include/zephyr/bluetooth/uuid.h
index aa0413dc13a..37b061c2ed6 100644
--- a/include/zephyr/bluetooth/uuid.h
+++ b/include/zephyr/bluetooth/uuid.h
@@ -17,6 +17,7 @@
  * @{
  */
 
+#include <stddef.h>
 #include <stdint.h>
 
 #include <zephyr/sys/util.h>
diff --git a/include/zephyr/data/cobs.h b/include/zephyr/data/cobs.h
new file mode 100644
index 00000000000..e22f1d2aaaf
--- /dev/null
+++ b/include/zephyr/data/cobs.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2024 Kelly Helmut Lord
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DATA_COBS_H_
+#define ZEPHYR_INCLUDE_DATA_COBS_H_
+
+#include <stddef.h>
+#include <sys/types.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/net_buf.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define COBS_DEFAULT_DELIMITER 0x00
+
+/**
+ * Flag indicating that encode and decode should include an implicit end delimiter
+ */
+#define COBS_FLAG_TRAILING_DELIMITER BIT(8)
+
+/**
+ * Macro for extracting delimiter from flags. 8 LSB of "flags" is used for the delimiter
+ * Example usage:
+ * cobs_encode(src_buf, dst_buf, COBS_FLAG_TRAILING_DELIMITER | COBS_FLAG_CUSTOM_DELIMITER(0x7F));
+ */
+#define COBS_FLAG_CUSTOM_DELIMITER(x) ((x) & 0xff)
+
+/**
+ * @defgroup cobs COBS (Consistent Overhead Byte Stuffing)
+ * @ingroup utilities
+ * @{
+ *
+ * @brief COBS encoding and decoding functions with custom delimiter support
+ *
+ * Provides functions for COBS encoding/decoding with configurable delimiters.
+ * The implementation handles both standard zero-delimited COBS and custom
+ * delimiter variants.
+ */
+
+/**
+ * @brief Calculate maximum encoded buffer size
+ *
+ * @param decoded_size  Size of input data to be encoded
+ * @param flags         COBS_FLAG_TRAILING_DELIMITER to include termination byte in calculation
+ *
+ * @return Required buffer size for worst-case encoding scenario
+ */
+static inline size_t cobs_max_encoded_len(size_t decoded_size, uint32_t flags)
+{
+	if (flags & COBS_FLAG_TRAILING_DELIMITER) {
+		return decoded_size + decoded_size / 254 + 1 + 1;
+	} else {
+		return decoded_size + decoded_size / 254 + 1;
+	}
+}
+
+/**
+ * @brief Standard COBS encoding
+ *
+ * @param src        Source buffer to decode
+ * @param dst        Destination buffer for decoded data
+ * @param flags      Decoding flags (reserved)
+ *
+ * @retval 0        Success
+ * @retval -ENOMEM  Insufficient destination space
+ * @retval -EINVAL  Invalid COBS structure or parameters
+ */
+
+int cobs_encode(struct net_buf *src, struct net_buf *dst, uint32_t flags);
+
+/**
+ * @brief Standard COBS decoding
+ *
+ * @param src        Source buffer to decode
+ * @param dst        Destination buffer for decoded data
+ * @param flags      Decoding flags (reserved)
+ *
+ * @retval 0        Success
+ * @retval -ENOMEM  Insufficient destination space
+ * @retval -EINVAL  Invalid COBS structure or parameters
+ */
+int cobs_decode(struct net_buf *src, struct net_buf *dst, uint32_t flags);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_INCLUDE_DATA_COBS_H_ */
diff --git a/include/zephyr/data/json.h b/include/zephyr/data/json.h
index 2e8182fd088..699cd139007 100644
--- a/include/zephyr/data/json.h
+++ b/include/zephyr/data/json.h
@@ -35,6 +35,7 @@ enum json_tokens {
 	JSON_TOK_ARRAY_START = '[',
 	JSON_TOK_ARRAY_END = ']',
 	JSON_TOK_STRING = '"',
+	JSON_TOK_STRING_BUF = 's',
 	JSON_TOK_COLON = ':',
 	JSON_TOK_COMMA = ',',
 	JSON_TOK_NUMBER = '0',
@@ -44,6 +45,10 @@ enum json_tokens {
 	JSON_TOK_ENCODED_OBJ = '4',
 	JSON_TOK_INT64 = '5',
 	JSON_TOK_UINT64 = '6',
+	JSON_TOK_FLOAT_FP = '7',
+	JSON_TOK_DOUBLE_FP = '8',
+	JSON_TOK_INT = 'i',
+	JSON_TOK_UINT = 'u',
 	JSON_TOK_TRUE = 't',
 	JSON_TOK_FALSE = 'f',
 	JSON_TOK_NULL = 'n',
@@ -108,6 +113,9 @@ struct json_obj_descr {
 			const struct json_obj_descr *element_descr;
 			size_t n_elements;
 		} array;
+		struct {
+			size_t size;
+		} field;
 	};
 };
 
@@ -157,6 +165,9 @@ typedef int (*json_append_bytes_t)(const char *bytes, size_t len,
 		.field_name_len = sizeof(#field_name_) - 1, \
 		.type = type_, \
 		.offset = offsetof(struct_, field_name_), \
+		.field = { \
+			.size = SIZEOF_FIELD(struct_, field_name_) \
+		}, \
 	}
 
 /**
@@ -237,11 +248,22 @@ typedef int (*json_append_bytes_t)(const char *bytes, size_t len,
  * @param elem_descr_len_ Number of elements in elem_descr_
  */
 #define Z_JSON_DESCR_OBJ(elem_descr_, elem_descr_len_) \
-	{ \
 		.object = { \
 			.sub_descr = elem_descr_, \
 			.sub_descr_len = elem_descr_len_, \
 		}, \
+
+/**
+ * @internal @brief Helper macro to declare a field descriptor
+ *
+ * @param struct_ Struct packing the values
+ * @param field_name_ Field name in the struct
+ */
+#define Z_JSON_DESCR_FIELD(struct_, field_name_) \
+	{ \
+		.field = { \
+			.size = SIZEOF_FIELD(struct_, field_name_), \
+		}, \
 	}
 
 /**
@@ -276,7 +298,8 @@ typedef int (*json_append_bytes_t)(const char *bytes, size_t len,
 		.offset = offsetof(struct_, field_name_), \
 		.array = { \
 			.element_descr = Z_JSON_ELEMENT_DESCR(struct_, len_field_, \
-				elem_type_,), \
+				elem_type_, \
+				Z_JSON_DESCR_FIELD(struct_, field_name_[0])), \
 			.n_elements = (max_len_), \
 		}, \
 	}
@@ -449,6 +472,9 @@ typedef int (*json_append_bytes_t)(const char *bytes, size_t len,
 		.field_name_len = sizeof(json_field_name_) - 1, \
 		.type = type_, \
 		.offset = offsetof(struct_, struct_field_name_), \
+		.field = { \
+			.size = SIZEOF_FIELD(struct_, struct_field_name_) \
+		}, \
 	}
 
 /**
@@ -504,8 +530,9 @@ typedef int (*json_append_bytes_t)(const char *bytes, size_t len,
 		.type = JSON_TOK_ARRAY_START, \
 		.offset = offsetof(struct_, struct_field_name_), \
 		.array = { \
-			.element_descr = \
-				Z_JSON_ELEMENT_DESCR(struct_, len_field_, elem_type_,), \
+			.element_descr = Z_JSON_ELEMENT_DESCR(struct_, len_field_, \
+				elem_type_, \
+				Z_JSON_DESCR_FIELD(struct_, struct_field_name_[0])), \
 			.n_elements = (max_len_), \
 		}, \
 	}
diff --git a/include/zephyr/data/navigation.h b/include/zephyr/data/navigation.h
index 0759df984ea..a0915280942 100644
--- a/include/zephyr/data/navigation.h
+++ b/include/zephyr/data/navigation.h
@@ -31,7 +31,7 @@ struct navigation_data {
 	uint32_t bearing;
 	/** Speed in millimeters per second */
 	uint32_t speed;
-	/** Altitude in millimeters */
+	/** Altitude above MSL in millimeters */
 	int32_t altitude;
 };
 
diff --git a/include/zephyr/debug/coredump.h b/include/zephyr/debug/coredump.h
index 5ebdca5fc1e..bf045763c45 100644
--- a/include/zephyr/debug/coredump.h
+++ b/include/zephyr/debug/coredump.h
@@ -29,7 +29,7 @@
  * @file
  *
  * @defgroup coredump_apis Coredump APIs
- * @ingroup os_services
+ * @ingroup debug
  * @brief Coredump APIs
  * @{
  */
@@ -235,7 +235,7 @@ struct coredump_backend_api {
 	coredump_backend_start_t		start;
 
 	/* Signal to backend of the end of coredump. */
-	coredump_backend_end_t		end;
+	coredump_backend_end_t			end;
 
 	/* Raw buffer output */
 	coredump_backend_buffer_output_t	buffer_output;
diff --git a/include/zephyr/debug/coresight/cs_trace_defmt.h b/include/zephyr/debug/coresight/cs_trace_defmt.h
index b9920672681..b106586ca2b 100644
--- a/include/zephyr/debug/coresight/cs_trace_defmt.h
+++ b/include/zephyr/debug/coresight/cs_trace_defmt.h
@@ -14,6 +14,7 @@ extern "C" {
 
 /**
  * @defgroup coresight_apis Coresight APIs
+ * @ingroup debug
  * @{
  * @}
  * @defgroup cs_trace_defmt Coresight Trace Deformatter
diff --git a/include/zephyr/debug/cpu_load.h b/include/zephyr/debug/cpu_load.h
new file mode 100644
index 00000000000..dbc816fd227
--- /dev/null
+++ b/include/zephyr/debug/cpu_load.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2024, Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DEBUG_CPU_LOAD_H_
+#define ZEPHYR_INCLUDE_DEBUG_CPU_LOAD_H_
+
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup cpu_load CPU load monitor
+ *  @ingroup debug
+ *  @brief Module for monitoring CPU Load
+ *
+ *  This module allow monitoring of the CPU load.
+ *  @{
+ */
+
+/** @brief Hook called by the application specific hook on entering CPU idle. */
+void cpu_load_on_enter_idle(void);
+
+/** @brief Hook called by the application specific hook on exiting CPU idle. */
+void cpu_load_on_exit_idle(void);
+
+/** @brief Get CPU load.
+ *
+ * CPU load is measured using a timer which tracks amount of time spent in the
+ * CPU idle. Since it is a software tracking there is some small overhead.
+ * Precision depends on the frequency of the timer in relation to the CPU frequency.
+ *
+ * @param reset Reset the measurement after reading.
+ *
+ * @retval Positive number - CPU load in per mille.
+ * @retval Negative number - error code.
+ */
+int cpu_load_get(bool reset);
+
+/** @brief Control periodic CPU statistics report.
+ *
+ * Report logging is by default enabled.
+ *
+ * @param enable true to enable report logging and false to disable.
+ */
+void cpu_load_log_control(bool enable);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* ZEPHYR_INCLUDE_DEBUG_CPU_LOAD_H_ */
diff --git a/include/zephyr/debug/mipi_stp_decoder.h b/include/zephyr/debug/mipi_stp_decoder.h
index c3a87e7a2ff..a28ecff83db 100644
--- a/include/zephyr/debug/mipi_stp_decoder.h
+++ b/include/zephyr/debug/mipi_stp_decoder.h
@@ -15,7 +15,7 @@ extern "C" {
 
 /**
  * @defgroup mipi_stp_decoder_apis STP Decoder API
- * @ingroup os_services
+ * @ingroup debug
  * @{
  */
 
diff --git a/include/zephyr/debug/stack.h b/include/zephyr/debug/stack.h
index 365560a0624..64dd547f059 100644
--- a/include/zephyr/debug/stack.h
+++ b/include/zephyr/debug/stack.h
@@ -21,9 +21,9 @@ static inline void log_stack_usage(const struct k_thread *thread)
 #if defined(CONFIG_INIT_STACKS) && defined(CONFIG_THREAD_STACK_INFO)
 	size_t unused, size = thread->stack_info.size;
 
-	TOOLCHAIN_IGNORE_WSHADOW_BEGIN;
+	TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_SHADOW);
 	LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
-	TOOLCHAIN_IGNORE_WSHADOW_END;
+	TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_SHADOW);
 
 	if (k_thread_stack_space_get(thread, &unused) == 0) {
 		unsigned int pcnt = ((size - unused) * 100U) / size;
diff --git a/include/zephyr/debug/symtab.h b/include/zephyr/debug/symtab.h
index 19afb5947b8..c83d2ba1948 100644
--- a/include/zephyr/debug/symtab.h
+++ b/include/zephyr/debug/symtab.h
@@ -15,7 +15,7 @@ extern "C" {
 
 /**
  * @defgroup symtab_apis Symbol Table API
- * @ingroup os_services
+ * @ingroup debug
  * @{
  */
 
diff --git a/include/zephyr/debug/thread_analyzer.h b/include/zephyr/debug/thread_analyzer.h
index d3d419bd8b6..c89607ab6a2 100644
--- a/include/zephyr/debug/thread_analyzer.h
+++ b/include/zephyr/debug/thread_analyzer.h
@@ -15,7 +15,7 @@ extern "C" {
 #endif
 
 /** @defgroup thread_analyzer Thread analyzer
- *  @ingroup os_services
+ *  @ingroup debug
  *  @brief Module for analyzing threads
  *
  *  This module implements functions and the configuration that simplifies
diff --git a/include/zephyr/device.h b/include/zephyr/device.h
index 00e7da354f9..df2d47250c7 100644
--- a/include/zephyr/device.h
+++ b/include/zephyr/device.h
@@ -101,21 +101,48 @@ typedef int16_t device_handle_t;
  * The ordinal used in this name can be mapped to the path by
  * examining zephyr/include/generated/zephyr/devicetree_generated.h.
  */
-#define Z_DEVICE_DT_DEV_ID(node_id) _CONCAT(dts_ord_, DT_DEP_ORD(node_id))
+#define Z_DEVICE_DT_DEP_ORD(node_id) _CONCAT(dts_ord_, DT_DEP_ORD(node_id))
 
-#if defined(CONFIG_LLEXT_EXPORT_DEVICES)
+/* Same as above, but uses the hash of the node path instead of the ordinal.
+ *
+ * The hash used in this name can be mapped to the path by
+ * examining zephyr/include/generated/zephyr/devicetree_generated.h.
+ */
+#define Z_DEVICE_DT_HASH(node_id) _CONCAT(dts_, DT_NODE_HASH(node_id))
+
+/* By default, device identifiers are obtained using the dependency ordinal.
+ * When LLEXT_EXPORT_DEV_IDS_BY_HASH is defined, the main Zephyr binary exports
+ * DT identifiers via EXPORT_SYMBOL_NAMED as hashed versions of their paths.
+ * When matching extensions are built, that is what they need to look for.
+ *
+ * The ordinal or hash used in this name can be mapped to the path by
+ * examining zephyr/include/generated/zephyr/devicetree_generated.h.
+ */
+#if defined(LL_EXTENSION_BUILD) && defined(CONFIG_LLEXT_EXPORT_DEV_IDS_BY_HASH)
+#define Z_DEVICE_DT_DEV_ID(node_id) Z_DEVICE_DT_HASH(node_id)
+#else
+#define Z_DEVICE_DT_DEV_ID(node_id) Z_DEVICE_DT_DEP_ORD(node_id)
+#endif
+
+#if defined(CONFIG_LLEXT_EXPORT_DEV_IDS_BY_HASH)
+/* Export device identifiers by hash */
+#define Z_DEVICE_EXPORT(node_id)					       \
+	EXPORT_SYMBOL_NAMED(DEVICE_DT_NAME_GET(node_id),		       \
+			    DEVICE_NAME_GET(Z_DEVICE_DT_HASH(node_id)))
+#elif defined(CONFIG_LLEXT_EXPORT_DEVICES)
 /* Export device identifiers using the builtin name */
 #define Z_DEVICE_EXPORT(node_id) EXPORT_SYMBOL(DEVICE_DT_NAME_GET(node_id))
 #endif
 
 /**
- * @brief Create a device object and set it up for boot time initialization.
+ * @brief Create a device object and set it up for boot time initialization,
+ * with de-init capabilities.
  *
  * This macro defines a @ref device that is automatically configured by the
  * kernel during system initialization. This macro should only be used when the
  * device is not being allocated from a devicetree node. If you are allocating a
- * device from a devicetree node, use DEVICE_DT_DEFINE() or
- * DEVICE_DT_INST_DEFINE() instead.
+ * device from a devicetree node, use DEVICE_DT_DEINIT_DEFINE() or
+ * DEVICE_DT_INST_DEINIT_DEFINE() instead.
  *
  * @param dev_id A unique token which is used in the name of the global device
  * structure as a C identifier.
@@ -125,6 +152,9 @@ typedef int16_t device_handle_t;
  * (including terminating `NULL`) in order to be looked up from user mode.
  * @param init_fn Pointer to the device's initialization function, which will be
  * run by the kernel during system initialization. Can be `NULL`.
+ * @param deinit_fn Pointer to the device's de-initialization function. Can be
+ * `NULL`. It must release any acquired resources (e.g. pins, bus, clock...) and
+ * leave the device in its reset state.
  * @param pm Pointer to the device's power management resources, a
  * @ref pm_device, which will be stored in @ref device.pm field. Use `NULL` if
  * the device does not use PM.
@@ -138,13 +168,23 @@ typedef int16_t device_handle_t;
  * SYS_INIT() for details.
  * @param api Pointer to the device's API structure. Can be `NULL`.
  */
-#define DEVICE_DEFINE(dev_id, name, init_fn, pm, data, config, level, prio,    \
-		      api)                                                     \
+#define DEVICE_DEINIT_DEFINE(dev_id, name, init_fn, deinit_fn, pm, data,       \
+			     config, level, prio, api)                         \
 	Z_DEVICE_STATE_DEFINE(dev_id);                                         \
-	Z_DEVICE_DEFINE(DT_INVALID_NODE, dev_id, name, init_fn, pm, data,      \
-			config, level, prio, api,                              \
+	Z_DEVICE_DEFINE(DT_INVALID_NODE, dev_id, name, init_fn, deinit_fn, 0U, \
+			pm, data, config, level, prio, api,                    \
 			&Z_DEVICE_STATE_NAME(dev_id))
 
+/**
+ * @brief Create a device object and set it up for boot time initialization.
+ *
+ * @see DEVICE_DEINIT_DEFINE()
+ */
+#define DEVICE_DEFINE(dev_id, name, init_fn, pm, data, config, level, prio,    \
+		      api)                                                     \
+	DEVICE_DEINIT_DEFINE(dev_id, name, init_fn, NULL, pm, data, config,    \
+			     level, prio, api)
+
 /**
  * @brief Return a string name for a devicetree node.
  *
@@ -159,24 +199,14 @@ typedef int16_t device_handle_t;
 #define DEVICE_DT_NAME(node_id)                                                \
 	DT_PROP_OR(node_id, label, DT_NODE_FULL_NAME(node_id))
 
-/**
- * @brief Determine if a devicetree node initialization should be deferred.
- *
- * @param node_id The devicetree node identifier.
- *
- * @return Boolean stating if node initialization should be deferred.
- */
-#define DEVICE_DT_DEFER(node_id)                                               \
-	DT_PROP(node_id, zephyr_deferred_init)
-
 /**
  * @brief Create a device object from a devicetree node identifier and set it up
  * for boot time initialization.
  *
  * This macro defines a @ref device that is automatically configured by the
  * kernel during system initialization. The global device object's name as a C
- * identifier is derived from the node's dependency ordinal. @ref device.name is
- * set to `DEVICE_DT_NAME(node_id)`.
+ * identifier is derived from the node's dependency ordinal or hash.
+ * @ref device.name is set to `DEVICE_DT_NAME(node_id)`.
  *
  * The device is declared with extern visibility, so a pointer to a global
  * device object can be obtained with `DEVICE_DT_GET(node_id)` from any source
@@ -187,6 +217,9 @@ typedef int16_t device_handle_t;
  * @param node_id The devicetree node identifier.
  * @param init_fn Pointer to the device's initialization function, which will be
  * run by the kernel during system initialization. Can be `NULL`.
+ * @param deinit_fn Pointer to the device's de-initialization function. Can be
+ * `NULL`. It must release any acquired resources (e.g. pins, bus, clock...) and
+ * leave the device in its reset state.
  * @param pm Pointer to the device's power management resources, a
  * @ref pm_device, which will be stored in @ref device.pm. Use `NULL` if the
  * device does not use PM.
@@ -200,15 +233,38 @@ typedef int16_t device_handle_t;
  * SYS_INIT() for details.
  * @param api Pointer to the device's API structure. Can be `NULL`.
  */
-#define DEVICE_DT_DEFINE(node_id, init_fn, pm, data, config, level, prio, api, \
-			 ...)                                                  \
+#define DEVICE_DT_DEINIT_DEFINE(node_id, init_fn, deinit_fn, pm, data, config, \
+				level, prio, api, ...)                         \
 	Z_DEVICE_STATE_DEFINE(Z_DEVICE_DT_DEV_ID(node_id));                    \
 	Z_DEVICE_DEFINE(node_id, Z_DEVICE_DT_DEV_ID(node_id),                  \
-			DEVICE_DT_NAME(node_id), init_fn, pm, data, config,    \
-			level, prio, api,                                      \
+			DEVICE_DT_NAME(node_id), init_fn, deinit_fn,           \
+			Z_DEVICE_DT_FLAGS(node_id), pm, data, config, level,   \
+			prio, api,                                             \
 			&Z_DEVICE_STATE_NAME(Z_DEVICE_DT_DEV_ID(node_id)),     \
 			__VA_ARGS__)
 
+/**
+ * @brief Create a device object from a devicetree node identifier and set it up
+ * for boot time initialization.
+ *
+ * @see DEVICE_DT_DEINIT_DEFINE()
+ */
+#define DEVICE_DT_DEFINE(node_id, init_fn, pm, data, config, level, prio, api, \
+			 ...)                                                  \
+	DEVICE_DT_DEINIT_DEFINE(node_id, init_fn, NULL, pm, data, config,      \
+				level, prio, api, __VA_ARGS__)
+
+/**
+ * @brief Like DEVICE_DT_DEINIT_DEFINE(), but uses an instance of a
+ * `DT_DRV_COMPAT` compatible instead of a node identifier.
+ *
+ * @param inst Instance number. The `node_id` argument to DEVICE_DT_DEFINE() is
+ * set to `DT_DRV_INST(inst)`.
+ * @param ... Other parameters as expected by DEVICE_DT_DEFINE().
+ */
+#define DEVICE_DT_INST_DEINIT_DEFINE(inst, ...)                                \
+	DEVICE_DT_DEINIT_DEFINE(DT_DRV_INST(inst), __VA_ARGS__)
+
 /**
  * @brief Like DEVICE_DT_DEFINE(), but uses an instance of a `DT_DRV_COMPAT`
  * compatible instead of a node identifier.
@@ -320,6 +376,22 @@ typedef int16_t device_handle_t;
 	COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(node_id),                          \
 		    (DEVICE_DT_GET(node_id)), (NULL))
 
+/**
+ * @brief Get a @ref device reference from a devicetree phandles by idx.
+ *
+ * Returns a pointer to a device object referenced by a phandles property, by idx.
+ *
+ * @param node_id A devicetree node identifier
+ * @param prop lowercase-and-underscores property with type `phandle`,
+ *            `phandles`, or `phandle-array`
+ * @param idx logical index into @p phs, which must be zero if @p phs
+ *            has type `phandle`
+ *
+ * @return A pointer to the device object created for that node
+ */
+#define DEVICE_DT_GET_BY_IDX(node_id, prop, idx) \
+	DEVICE_DT_GET(DT_PHANDLE_BY_IDX(node_id, prop, idx))
+
 /**
  * @brief Obtain a pointer to a device object by name
  *
@@ -405,6 +477,27 @@ struct device_dt_metadata;
 #define Z_DEVICE_DEPS_CONST const
 #endif
 
+/** Device flags */
+typedef uint8_t device_flags_t;
+
+/**
+ * @name Device flags
+ * @{
+ */
+
+/** Device initialization is deferred */
+#define DEVICE_FLAG_INIT_DEFERRED BIT(0)
+
+/** @} */
+
+/** Device operations */
+struct device_ops {
+	/** Initialization function */
+	int (*init)(const struct device *dev);
+	/** De-initialization function */
+	int (*deinit)(const struct device *dev);
+};
+
 /**
  * @brief Runtime device structure (in ROM) per driver instance
  */
@@ -419,6 +512,10 @@ struct device {
 	struct device_state *state;
 	/** Address of the device instance private data */
 	void *data;
+	/** Device operations */
+	struct device_ops ops;
+	/** Device flags */
+	device_flags_t flags;
 #if defined(CONFIG_DEVICE_DEPS) || defined(__DOXYGEN__)
 	/**
 	 * Optional pointer to dependencies associated with the device.
@@ -767,17 +864,35 @@ __syscall bool device_is_ready(const struct device *dev);
  *
  * A device whose initialization was deferred (by marking it as
  * ``zephyr,deferred-init`` on devicetree) needs to be initialized manually via
- * this call. Note that only devices whose initialization was deferred can be
- * initialized via this call - one can not try to initialize a non
- * initialization deferred device that failed initialization with this call.
+ * this call. De-initialized devices can also be initialized again via this
+ * call.
  *
  * @param dev device to be initialized.
  *
- * @retval -ENOENT If device was not found - or isn't a deferred one.
+ * @retval -EALREADY Device is already initialized.
  * @retval -errno For other errors.
  */
 __syscall int device_init(const struct device *dev);
 
+/**
+ * @brief De-initialize a device.
+ *
+ * When a device is de-initialized, it will release any resources it has
+ * acquired (e.g. pins, memory, clocks, DMA channels, etc.) and its status will
+ * be left as in its reset state.
+ *
+ * @warning It is the responsibility of the caller to ensure that the device is
+ * ready to be de-initialized.
+ *
+ * @param dev device to be de-initialized.
+ *
+ * @retval 0 If successful
+ * @retval -EPERM If device has not been initialized.
+ * @retval -ENOTSUP If device does not support de-initialization.
+ * @retval -errno For any other errors.
+ */
+__syscall int device_deinit(const struct device *dev);
+
 /**
  * @}
  */
@@ -799,6 +914,14 @@ __syscall int device_init(const struct device *dev);
 	static Z_DECL_ALIGN(struct device_state) Z_DEVICE_STATE_NAME(dev_id)   \
 		__attribute__((__section__(".z_devstate")))
 
+/**
+ * @brief Device flags obtained from DT.
+ *
+ * @param node_id Devicetree node identifier.
+ */
+#define Z_DEVICE_DT_FLAGS(node_id)                                             \
+	(DT_PROP_OR(node_id, zephyr_deferred_init, 0U) * DEVICE_FLAG_INIT_DEFERRED)
+
 #if defined(CONFIG_DEVICE_DEPS) || defined(__DOXYGEN__)
 
 /**
@@ -1013,6 +1136,9 @@ device_get_dt_nodelabels(const struct device *dev)
  * @brief Initializer for @ref device.
  *
  * @param name_ Name of the device.
+ * @param init_fn_ Init function (optional).
+ * @param deinit_fn_ De-init function (optional).
+ * @param flags_ Device flags.
  * @param pm_ Reference to @ref pm_device_base (optional).
  * @param data_ Reference to device data.
  * @param config_ Reference to device config.
@@ -1022,14 +1148,16 @@ device_get_dt_nodelabels(const struct device *dev)
  * @param node_id_ Devicetree node identifier
  * @param dev_id_ Device identifier token, as passed to Z_DEVICE_BASE_DEFINE
  */
-#define Z_DEVICE_INIT(name_, pm_, data_, config_, api_, state_, deps_, node_id_,	\
-		      dev_id_)								\
+#define Z_DEVICE_INIT(name_, init_fn_, deinit_fn_, flags_, pm_, data_, config_, api_,   \
+		      state_, deps_, node_id_, dev_id_)					\
 	{										\
 		.name = name_,								\
 		.config = (config_),							\
 		.api = (api_),								\
 		.state = (state_),							\
 		.data = (data_),							\
+		.ops = { .init = (init_fn_), .deinit = (deinit_fn_) },			\
+		.flags = (flags_),							\
 		IF_ENABLED(CONFIG_DEVICE_DEPS, (.deps = (deps_),)) /**/			\
 		IF_ENABLED(CONFIG_PM_DEVICE, Z_DEVICE_INIT_PM_BASE(pm_)) /**/		\
 		IF_ENABLED(CONFIG_DEVICE_DT_METADATA,					\
@@ -1065,6 +1193,9 @@ device_get_dt_nodelabels(const struct device *dev)
  * software device).
  * @param dev_id Device identifier (used to name the defined @ref device).
  * @param name Name of the device.
+ * @param init_fn Init function.
+ * @param deinit_fn De-init function.
+ * @param flags Device flags.
  * @param pm Reference to @ref pm_device_base associated with the device.
  * (optional).
  * @param data Reference to device data.
@@ -1074,14 +1205,15 @@ device_get_dt_nodelabels(const struct device *dev)
  * @param api Reference to device API.
  * @param ... Optional dependencies, manually specified.
  */
-#define Z_DEVICE_BASE_DEFINE(node_id, dev_id, name, pm, data, config, level, prio, api, state,     \
-			     deps)                                                    \
+#define Z_DEVICE_BASE_DEFINE(node_id, dev_id, name, init_fn, deinit_fn, flags, pm, data, config,   \
+			     level, prio, api, state, deps)                                        \
 	COND_CODE_1(DT_NODE_EXISTS(node_id), (), (static))                                         \
 	COND_CODE_1(Z_DEVICE_IS_MUTABLE(node_id), (), (const))                                     \
 	STRUCT_SECTION_ITERABLE_NAMED_ALTERNATE(                                                   \
 		device, COND_CODE_1(Z_DEVICE_IS_MUTABLE(node_id), (device_mutable), (device)),     \
 		Z_DEVICE_SECTION_NAME(level, prio), DEVICE_NAME_GET(dev_id)) =                     \
-		Z_DEVICE_INIT(name, pm, data, config, api, state, deps, node_id, dev_id)
+		Z_DEVICE_INIT(name, init_fn, deinit_fn, flags, pm, data, config, api, state, deps, \
+			      node_id, dev_id)
 
 /**
  * @brief Issue an error if the given init level is not supported.
@@ -1100,43 +1232,18 @@ device_get_dt_nodelabels(const struct device *dev)
  * @param node_id Devicetree node id for the device (DT_INVALID_NODE if a
  * software device).
  * @param dev_id Device identifier.
- * @param init_fn_ Device init function.
  * @param level Initialization level.
  * @param prio Initialization priority.
  */
-#define Z_DEVICE_INIT_ENTRY_DEFINE(node_id, dev_id, init_fn_, level, prio)                         \
+#define Z_DEVICE_INIT_ENTRY_DEFINE(node_id, dev_id, level, prio)                                   \
 	Z_DEVICE_CHECK_INIT_LEVEL(level)                                                           \
                                                                                                    \
 	static const Z_DECL_ALIGN(struct init_entry) __used __noasan Z_INIT_ENTRY_SECTION(         \
 		level, prio, Z_DEVICE_INIT_SUB_PRIO(node_id))                                      \
 		Z_INIT_ENTRY_NAME(DEVICE_NAME_GET(dev_id)) = {                                     \
-			.init_fn = {COND_CODE_1(Z_DEVICE_IS_MUTABLE(node_id), (.dev_rw), (.dev)) = \
-					    (init_fn_)},                                           \
-			Z_DEVICE_INIT_ENTRY_DEV(node_id, dev_id),                                  \
-	}
-
-#define Z_DEFER_DEVICE_INIT_ENTRY_DEFINE(node_id, dev_id, init_fn_)                                \
-	static const Z_DECL_ALIGN(struct init_entry) __used __noasan                               \
-		__attribute__((__section__(".z_deferred_init")))                                   \
-		Z_INIT_ENTRY_NAME(DEVICE_NAME_GET(dev_id)) = {                                     \
-			.init_fn = {COND_CODE_1(Z_DEVICE_IS_MUTABLE(node_id), (.dev_rw), (.dev)) = \
-					    (init_fn_)},                                           \
-			Z_DEVICE_INIT_ENTRY_DEV(node_id, dev_id),                                  \
-	}
-
-/*
- * Anonymous unions require C11. Some pre-C11 gcc versions have early support for anonymous
- * unions but they require these braces when combined with C99 designated initializers. For
- * more details see https://docs.zephyrproject.org/latest/develop/languages/cpp/
- */
-#if defined(__STDC_VERSION__) && (__STDC_VERSION__) < 201100
-#  define Z_DEVICE_INIT_ENTRY_DEV(node_id, dev_id) { Z_DEV_ENTRY_DEV(node_id, dev_id) }
-#else
-#  define Z_DEVICE_INIT_ENTRY_DEV(node_id, dev_id)   Z_DEV_ENTRY_DEV(node_id, dev_id)
-#endif
-
-#define Z_DEV_ENTRY_DEV(node_id, dev_id)                                                           \
-	COND_CODE_1(Z_DEVICE_IS_MUTABLE(node_id), (.dev_rw), (.dev)) =  &DEVICE_NAME_GET(dev_id)
+			.init_fn = NULL,                                                           \
+			.dev = (const struct device *)&DEVICE_NAME_GET(dev_id),                    \
+		}
 
 /**
  * @brief Define a @ref device and all other required objects.
@@ -1149,6 +1256,7 @@ device_get_dt_nodelabels(const struct device *dev)
  * @param dev_id Device identifier (used to name the defined @ref device).
  * @param name Name of the device.
  * @param init_fn Device init function.
+ * @param flags Device flags.
  * @param pm Reference to @ref pm_device_base associated with the device.
  * (optional).
  * @param data Reference to device data.
@@ -1159,8 +1267,8 @@ device_get_dt_nodelabels(const struct device *dev)
  * @param state Reference to device state.
  * @param ... Optional dependencies, manually specified.
  */
-#define Z_DEVICE_DEFINE(node_id, dev_id, name, init_fn, pm, data, config,       \
-			level, prio, api, state, ...)                           \
+#define Z_DEVICE_DEFINE(node_id, dev_id, name, init_fn, deinit_fn, flags, pm,   \
+			data, config, level, prio, api, state, ...)             \
 	Z_DEVICE_NAME_CHECK(name);                                              \
                                                                                 \
 	IF_ENABLED(CONFIG_DEVICE_DEPS,                                          \
@@ -1170,13 +1278,12 @@ device_get_dt_nodelabels(const struct device *dev)
 		   (IF_ENABLED(DT_NODE_EXISTS(node_id),                         \
 			      (Z_DEVICE_DT_METADATA_DEFINE(node_id, dev_id);))))\
                                                                                 \
-	Z_DEVICE_BASE_DEFINE(node_id, dev_id, name, pm, data, config, level,    \
-		prio, api, state, Z_DEVICE_DEPS_NAME(dev_id));                  \
-	COND_CODE_1(DEVICE_DT_DEFER(node_id),                                   \
-		    (Z_DEFER_DEVICE_INIT_ENTRY_DEFINE(node_id, dev_id,          \
-						      init_fn)),                \
-		    (Z_DEVICE_INIT_ENTRY_DEFINE(node_id, dev_id, init_fn,       \
-						level, prio)));                 \
+	Z_DEVICE_BASE_DEFINE(node_id, dev_id, name, init_fn, deinit_fn, flags,  \
+			     pm, data, config, level, prio, api, state,         \
+			     Z_DEVICE_DEPS_NAME(dev_id));                       \
+                                                                                \
+	Z_DEVICE_INIT_ENTRY_DEFINE(node_id, dev_id, level, prio);               \
+                                                                                \
 	IF_ENABLED(CONFIG_LLEXT_EXPORT_DEVICES,                                 \
 		(IF_ENABLED(DT_NODE_EXISTS(node_id),                            \
 				(Z_DEVICE_EXPORT(node_id);))))
diff --git a/include/zephyr/devicetree.h b/include/zephyr/devicetree.h
index de4903471cb..2b10eaf8d48 100644
--- a/include/zephyr/devicetree.h
+++ b/include/zephyr/devicetree.h
@@ -242,6 +242,16 @@
  */
 #define DT_HAS_ALIAS(alias_name) DT_NODE_EXISTS(DT_ALIAS(alias_name))
 
+/**
+ * @brief Get the hash associated with a DT node
+ *
+ * Get the hash for the specified node_id. The hash is calculated on the
+ * full devicetree path of the node.
+ * @param node_id node identifier
+ * @return hash value as a preprocessor token
+ */
+#define DT_NODE_HASH(node_id) DT_CAT(node_id, _HASH)
+
 /**
  * @brief Get a node identifier for an instance of a compatible
  *
@@ -2919,6 +2929,36 @@
  * @defgroup devicetree-generic-foreach "For-each" macros
  * @ingroup devicetree
  * @{
+ *
+ * IMPORTANT: you can't use the DT for-each macros in their own expansions.
+ *
+ * For example, something like this won't work the way you might expect:
+ *
+ * @code{.c}
+ * #define FOO(node_id) [...] DT_FOREACH_NODE(...) [...]
+ * DT_FOREACH_NODE(FOO)
+ * @endcode
+ *
+ * In this example, the C preprocessor won't expand the
+ * DT_FOREACH_NODE() macro inside of FOO() while it's already
+ * expanding DT_FOREACH_NODE() at the top level of the file.
+ *
+ * This is true of any macro, not just DT_FOREACH_NODE(). The C
+ * language works this way to avoid infinite recursions inside of
+ * macro expansions.
+ *
+ * If you need to "nest" calls to one of these macros, you can work
+ * around this preprocessor limitation by using a different, related
+ * macro instead, like this:
+ *
+ * @code{.c}
+ * #define BAR(node_id) [...] DT_FOREACH_NODE_VARGS(...) [...]
+ * DT_FOREACH_NODE(BAR)
+ * @endcode
+ *
+ * Here, we use DT_FOREACH_NODE_VARGS() "inside" BAR() "inside"
+ * DT_FOREACH_NODE(). Because of this, the preprocessor will expand
+ * both DT_FOREACH_NODE_VARGS() and DT_FOREACH_NODE() as expected.
  */
 
 /**
@@ -4665,7 +4705,7 @@
 #define DT_INST_STRING_UNQUOTED_OR(inst, name, default_value) \
 	DT_STRING_UNQUOTED_OR(DT_DRV_INST(inst), name, default_value)
 
-/*
+/**
  * @brief Test if any enabled node with the given compatible is on
  *        the given bus type
  *
diff --git a/include/zephyr/dfu/flash_img.h b/include/zephyr/dfu/flash_img.h
index 00446852609..8ae5fe52e47 100644
--- a/include/zephyr/dfu/flash_img.h
+++ b/include/zephyr/dfu/flash_img.h
@@ -111,6 +111,13 @@ int flash_img_check(struct flash_img_context *ctx,
 		    const struct flash_img_check *fic,
 		    uint8_t area_id);
 
+/**
+ * @brief Get the flash area id for the image upload slot.
+ *
+ * @return flash area id for the image upload slot
+ */
+uint8_t flash_img_get_upload_slot(void);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/zephyr/dfu/mcuboot.h b/include/zephyr/dfu/mcuboot.h
index fe15f769f98..efd8c83b26b 100644
--- a/include/zephyr/dfu/mcuboot.h
+++ b/include/zephyr/dfu/mcuboot.h
@@ -81,6 +81,8 @@ extern "C" {
 
 #define BOOT_IMG_VER_STRLEN_MAX 25  /* 255.255.65535.4294967295\0 */
 
+/** Sector at which firmware update should be placed by application in swap using offset mode */
+#define SWAP_USING_OFFSET_SECTOR_UPDATE_BEGIN 1
 
 /**
  * @brief MCUboot image header representation for image version
@@ -159,6 +161,13 @@ int boot_read_bank_header(uint8_t area_id,
 			  struct mcuboot_img_header *header,
 			  size_t header_size);
 
+/**
+ * @brief Get the flash area id for the active image slot.
+ *
+ * @return flash area id for the active image slot
+ */
+uint8_t boot_fetch_active_slot(void);
+
 /**
  * @brief Check if the currently running image is confirmed as OK.
  *
@@ -280,6 +289,20 @@ ssize_t boot_get_area_trailer_status_offset(uint8_t area_id);
  */
 ssize_t boot_get_trailer_status_offset(size_t area_size);
 
+#if defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_USING_OFFSET) || defined(__DOXYGEN__)
+/**
+ * @brief Get the offset of the image header, this should be used in swap using offset mode to
+ *	  account for the secondary slot data starting in the first or second sector, depending
+ *	  upon the current state
+ *
+ * @param area_id flash_area ID of image bank to get the status offset
+ * @return offset of the image header
+ */
+size_t boot_get_image_start_offset(uint8_t area_id);
+#else
+#define boot_get_image_start_offset(...) 0
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/zephyr/display/cfb.h b/include/zephyr/display/cfb.h
index 9cdf81e259a..ea00b8aa2fd 100644
--- a/include/zephyr/display/cfb.h
+++ b/include/zephyr/display/cfb.h
@@ -28,7 +28,7 @@ extern "C" {
  */
 
 enum cfb_display_param {
-	CFB_DISPLAY_HEIGH		= 0,
+	CFB_DISPLAY_HEIGHT		= 0,
 	CFB_DISPLAY_WIDTH,
 	CFB_DISPLAY_PPT,
 	CFB_DISPLAY_ROWS,
diff --git a/include/zephyr/drivers/adc/ads114s0x.h b/include/zephyr/drivers/adc/ads114s0x.h
deleted file mode 100644
index af8cae7a96a..00000000000
--- a/include/zephyr/drivers/adc/ads114s0x.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright (c) 2023 SILA Embedded Solutions GmbH
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_INCLUDE_DRIVERS_ADC_ADS114S0X_H_
-#define ZEPHYR_INCLUDE_DRIVERS_ADC_ADS114S0X_H_
-
-#include <zephyr/device.h>
-#include <zephyr/drivers/gpio.h>
-
-int ads114s0x_gpio_set_output(const struct device *dev, uint8_t pin, bool initial_value);
-
-int ads114s0x_gpio_set_input(const struct device *dev, uint8_t pin);
-
-int ads114s0x_gpio_deconfigure(const struct device *dev, uint8_t pin);
-
-int ads114s0x_gpio_set_pin_value(const struct device *dev, uint8_t pin,
-				bool value);
-
-int ads114s0x_gpio_get_pin_value(const struct device *dev, uint8_t pin,
-				bool *value);
-
-int ads114s0x_gpio_port_get_raw(const struct device *dev,
-			       gpio_port_value_t *value);
-
-int ads114s0x_gpio_port_set_masked_raw(const struct device *dev,
-				      gpio_port_pins_t mask,
-				      gpio_port_value_t value);
-
-int ads114s0x_gpio_port_toggle_bits(const struct device *dev,
-				   gpio_port_pins_t pins);
-
-#endif /* ZEPHYR_INCLUDE_DRIVERS_ADC_ADS114S0X_H_ */
diff --git a/include/zephyr/drivers/adc/ads1x4s0x.h b/include/zephyr/drivers/adc/ads1x4s0x.h
new file mode 100644
index 00000000000..2f4c7a14829
--- /dev/null
+++ b/include/zephyr/drivers/adc/ads1x4s0x.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2023 SILA Embedded Solutions GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_ADC_ADS1X4S0X_H_
+#define ZEPHYR_INCLUDE_DRIVERS_ADC_ADS1X4S0X_H_
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+
+int ads1x4s0x_gpio_set_output(const struct device *dev, uint8_t pin, bool initial_value);
+
+int ads1x4s0x_gpio_set_input(const struct device *dev, uint8_t pin);
+
+int ads1x4s0x_gpio_deconfigure(const struct device *dev, uint8_t pin);
+
+int ads1x4s0x_gpio_set_pin_value(const struct device *dev, uint8_t pin,
+				bool value);
+
+int ads1x4s0x_gpio_get_pin_value(const struct device *dev, uint8_t pin,
+				bool *value);
+
+int ads1x4s0x_gpio_port_get_raw(const struct device *dev,
+			       gpio_port_value_t *value);
+
+int ads1x4s0x_gpio_port_set_masked_raw(const struct device *dev,
+				      gpio_port_pins_t mask,
+				      gpio_port_value_t value);
+
+int ads1x4s0x_gpio_port_toggle_bits(const struct device *dev,
+				   gpio_port_pins_t pins);
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_ADC_ADS1X4S0X_H_ */
diff --git a/include/zephyr/drivers/adc/current_sense_amplifier.h b/include/zephyr/drivers/adc/current_sense_amplifier.h
index 05c9a98d158..59d091706d4 100644
--- a/include/zephyr/drivers/adc/current_sense_amplifier.h
+++ b/include/zephyr/drivers/adc/current_sense_amplifier.h
@@ -11,11 +11,13 @@
 #include <zephyr/drivers/gpio.h>
 
 struct current_sense_amplifier_dt_spec {
-	const struct adc_dt_spec port;
+	struct adc_dt_spec port;
+	struct gpio_dt_spec power_gpio;
 	uint32_t sense_milli_ohms;
 	uint16_t sense_gain_mult;
 	uint16_t sense_gain_div;
-	struct gpio_dt_spec power_gpio;
+	uint16_t noise_threshold;
+	bool enable_calibration;
 };
 
 /**
@@ -31,10 +33,12 @@ struct current_sense_amplifier_dt_spec {
 #define CURRENT_SENSE_AMPLIFIER_DT_SPEC_GET(node_id)                                               \
 	{                                                                                          \
 		.port = ADC_DT_SPEC_GET(node_id),                                                  \
+		.power_gpio = GPIO_DT_SPEC_GET_OR(node_id, power_gpios, {0}),                      \
 		.sense_milli_ohms = DT_PROP(node_id, sense_resistor_milli_ohms),                   \
 		.sense_gain_mult = DT_PROP(node_id, sense_gain_mult),                              \
 		.sense_gain_div = DT_PROP(node_id, sense_gain_div),                                \
-		.power_gpio = GPIO_DT_SPEC_GET_OR(node_id, power_gpios, {0}),                      \
+		.noise_threshold = DT_PROP(node_id, zephyr_noise_threshold),                       \
+		.enable_calibration = DT_PROP_OR(node_id, enable_calibration, false),              \
 	}
 
 /**
diff --git a/include/zephyr/drivers/can.h b/include/zephyr/drivers/can.h
index 5f32b8c3b48..edebeed3fff 100644
--- a/include/zephyr/drivers/can.h
+++ b/include/zephyr/drivers/can.h
@@ -761,7 +761,8 @@ struct can_device_state {
 	Z_DEVICE_DEFINE(node_id, Z_DEVICE_DT_DEV_ID(node_id),		\
 			DEVICE_DT_NAME(node_id),			\
 			&UTIL_CAT(Z_DEVICE_DT_DEV_ID(node_id), _init),	\
-			pm, data, config, level, prio, api,		\
+			NULL, Z_DEVICE_DT_FLAGS(node_id), pm, data,	\
+			config,	level, prio, api,			\
 			&(Z_DEVICE_STATE_NAME(Z_DEVICE_DT_DEV_ID(node_id)).devstate), \
 			__VA_ARGS__)
 
diff --git a/include/zephyr/drivers/clock_control.h b/include/zephyr/drivers/clock_control.h
index 27d65fe3079..6e322a8b07a 100644
--- a/include/zephyr/drivers/clock_control.h
+++ b/include/zephyr/drivers/clock_control.h
@@ -128,6 +128,10 @@ static inline int clock_control_on(const struct device *dev,
 	const struct clock_control_driver_api *api =
 		(const struct clock_control_driver_api *)dev->api;
 
+	if (api->on == NULL) {
+		return -ENOSYS;
+	}
+
 	return api->on(dev, sys);
 }
 
@@ -147,6 +151,10 @@ static inline int clock_control_off(const struct device *dev,
 	const struct clock_control_driver_api *api =
 		(const struct clock_control_driver_api *)dev->api;
 
+	if (api->off == NULL) {
+		return -ENOSYS;
+	}
+
 	return api->off(dev, sys);
 }
 
diff --git a/include/zephyr/drivers/clock_control/adi_max32_clock_control.h b/include/zephyr/drivers/clock_control/adi_max32_clock_control.h
index cd889d370b2..0f1e7b12882 100644
--- a/include/zephyr/drivers/clock_control/adi_max32_clock_control.h
+++ b/include/zephyr/drivers/clock_control/adi_max32_clock_control.h
@@ -41,7 +41,7 @@ struct max32_perclk {
 
 #define ADI_MAX32_CLK_IPO_FREQ    DT_PROP(DT_NODELABEL(clk_ipo), clock_frequency)
 #define ADI_MAX32_CLK_ERFO_FREQ   DT_PROP_OR(DT_NODELABEL(clk_erfo), clock_frequency, 0)
-#define ADI_MAX32_CLK_IBRO_FREQ   DT_PROP(DT_NODELABEL(clk_ibro), clock_frequency)
+#define ADI_MAX32_CLK_IBRO_FREQ   DT_PROP_OR(DT_NODELABEL(clk_ibro), clock_frequency, 0)
 #define ADI_MAX32_CLK_ISO_FREQ    DT_PROP_OR(DT_NODELABEL(clk_iso), clock_frequency, 0)
 #define ADI_MAX32_CLK_INRO_FREQ   DT_PROP(DT_NODELABEL(clk_inro), clock_frequency)
 #define ADI_MAX32_CLK_ERTCO_FREQ  DT_PROP(DT_NODELABEL(clk_ertco), clock_frequency)
diff --git a/include/zephyr/drivers/clock_control/clock_control_silabs.h b/include/zephyr/drivers/clock_control/clock_control_silabs.h
index ebabe6cbd83..b893c82aa56 100644
--- a/include/zephyr/drivers/clock_control/clock_control_silabs.h
+++ b/include/zephyr/drivers/clock_control/clock_control_silabs.h
@@ -19,6 +19,8 @@
 #include <zephyr/dt-bindings/clock/silabs/xg24-clock.h>
 #elif defined(CONFIG_SOC_SERIES_EFR32BG27)
 #include <zephyr/dt-bindings/clock/silabs/xg27-clock.h>
+#elif defined(CONFIG_SOC_SERIES_EFR32BG29) || defined(CONFIG_SOC_SERIES_EFR32MG29)
+#include <zephyr/dt-bindings/clock/silabs/xg29-clock.h>
 #endif
 
 struct silabs_clock_control_cmu_config {
diff --git a/include/zephyr/drivers/clock_control/nrf_clock_control.h b/include/zephyr/drivers/clock_control/nrf_clock_control.h
index acc74a85357..f94667700d2 100644
--- a/include/zephyr/drivers/clock_control/nrf_clock_control.h
+++ b/include/zephyr/drivers/clock_control/nrf_clock_control.h
@@ -8,7 +8,7 @@
 #define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_NRF_CLOCK_CONTROL_H_
 
 #include <zephyr/device.h>
-#if defined(NRF_CLOCK) && !defined(NRF_LFRC)
+#ifdef NRF_CLOCK
 #include <hal/nrf_clock.h>
 #endif
 #include <zephyr/sys/onoff.h>
diff --git a/include/zephyr/drivers/clock_control/stm32_clock_control.h b/include/zephyr/drivers/clock_control/stm32_clock_control.h
index a7974467d2e..49c74d1922b 100644
--- a/include/zephyr/drivers/clock_control/stm32_clock_control.h
+++ b/include/zephyr/drivers/clock_control/stm32_clock_control.h
@@ -53,6 +53,10 @@
 #include <zephyr/dt-bindings/clock/stm32h7_clock.h>
 #elif defined(CONFIG_SOC_SERIES_STM32H7RSX)
 #include <zephyr/dt-bindings/clock/stm32h7rs_clock.h>
+#elif defined(CONFIG_SOC_SERIES_STM32MP13X)
+#include <zephyr/dt-bindings/clock/stm32mp13_clock.h>
+#elif defined(CONFIG_SOC_SERIES_STM32N6X)
+#include <zephyr/dt-bindings/clock/stm32n6_clock.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U0X)
 #include <zephyr/dt-bindings/clock/stm32u0_clock.h>
 #elif defined(CONFIG_SOC_SERIES_STM32U5X)
@@ -72,6 +76,7 @@
 #define STM32_APB1_PRESCALER	DT_PROP(DT_NODELABEL(rcc), apb1_prescaler)
 #define STM32_APB2_PRESCALER	DT_PROP(DT_NODELABEL(rcc), apb2_prescaler)
 #define STM32_APB3_PRESCALER	DT_PROP(DT_NODELABEL(rcc), apb3_prescaler)
+#define STM32_APB4_PRESCALER	DT_PROP(DT_NODELABEL(rcc), apb4_prescaler)
 #define STM32_APB5_PRESCALER	DT_PROP(DT_NODELABEL(rcc), apb5_prescaler)
 #define STM32_APB7_PRESCALER	DT_PROP(DT_NODELABEL(rcc), apb7_prescaler)
 #define STM32_AHB3_PRESCALER	DT_PROP(DT_NODELABEL(rcc), ahb3_prescaler)
@@ -141,7 +146,25 @@
 #if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(clk_csi))
 #define STM32_SYSCLK_SRC_CSI	1
 #endif
+#if DT_SAME_NODE(DT_RCC_CLOCKS_CTRL, DT_NODELABEL(ic2))
+#define STM32_SYSCLK_SRC_IC2	1
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rcc), st_stm32n6_rcc, okay)
+#if (DT_SAME_NODE(DT_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(cpusw), 0), DT_NODELABEL(rcc)))
+#if (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_HSI)
+#define STM32_CPUCLK_SRC_HSI	1
+#elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_MSI)
+#define STM32_CPUCLK_SRC_MSI	1
+#elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_HSE)
+#define STM32_CPUCLK_SRC_HSE	1
+#elif (DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(cpusw), 0, bus) == STM32_SRC_IC1)
+#define STM32_CPUCLK_SRC_IC1	1
+#endif
+#endif /* cpusw clk source is rcc */
 
+#define STM32_TIMG_PRESCALER	DT_PROP(DT_NODELABEL(rcc), timg_prescaler)
+#endif /* rcc node compatible st_stm32n6_rcc and okay */
 
 /** PLL node related symbols */
 
@@ -180,7 +203,7 @@
 #define STM32_PLLI2S_R_DIVISOR		DT_PROP_OR(DT_NODELABEL(plli2s), div_r, 1)
 #endif
 
-#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f412_plli2s_clock, okay)
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(plli2s), st_stm32f411_plli2s_clock, okay)
 #define STM32_PLLI2S_ENABLED	1
 #define STM32_PLLI2S_M_DIVISOR		DT_PROP(DT_NODELABEL(plli2s), div_m)
 #define STM32_PLLI2S_N_MULTIPLIER	DT_PROP(DT_NODELABEL(plli2s), mul_n)
@@ -252,6 +275,38 @@
 #define STM32_PLL2_PREDIV	DT_PROP(DT_NODELABEL(pll2), prediv)
 #endif
 
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll1), st_stm32n6_pll_clock, okay)
+#define STM32_PLL1_ENABLED	1
+#define STM32_PLL1_M_DIVISOR	DT_PROP(DT_NODELABEL(pll1), div_m)
+#define STM32_PLL1_N_MULTIPLIER	DT_PROP(DT_NODELABEL(pll1), mul_n)
+#define STM32_PLL1_P1_DIVISOR	DT_PROP(DT_NODELABEL(pll1), div_p1)
+#define STM32_PLL1_P2_DIVISOR	DT_PROP(DT_NODELABEL(pll1), div_p2)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll2), st_stm32n6_pll_clock, okay)
+#define STM32_PLL2_ENABLED	1
+#define STM32_PLL2_M_DIVISOR	DT_PROP(DT_NODELABEL(pll2), div_m)
+#define STM32_PLL2_N_MULTIPLIER	DT_PROP(DT_NODELABEL(pll2), mul_n)
+#define STM32_PLL2_P1_DIVISOR	DT_PROP(DT_NODELABEL(pll2), div_p1)
+#define STM32_PLL2_P2_DIVISOR	DT_PROP(DT_NODELABEL(pll2), div_p2)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll3), st_stm32n6_pll_clock, okay)
+#define STM32_PLL3_ENABLED	1
+#define STM32_PLL3_M_DIVISOR	DT_PROP(DT_NODELABEL(pll3), div_m)
+#define STM32_PLL3_N_MULTIPLIER	DT_PROP(DT_NODELABEL(pll3), mul_n)
+#define STM32_PLL3_P1_DIVISOR	DT_PROP(DT_NODELABEL(pll3), div_p1)
+#define STM32_PLL3_P2_DIVISOR	DT_PROP(DT_NODELABEL(pll3), div_p2)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(pll4), st_stm32n6_pll_clock, okay)
+#define STM32_PLL4_ENABLED	1
+#define STM32_PLL4_M_DIVISOR	DT_PROP(DT_NODELABEL(pll4), div_m)
+#define STM32_PLL4_N_MULTIPLIER	DT_PROP(DT_NODELABEL(pll4), mul_n)
+#define STM32_PLL4_P1_DIVISOR	DT_PROP(DT_NODELABEL(pll4), div_p1)
+#define STM32_PLL4_P2_DIVISOR	DT_PROP(DT_NODELABEL(pll4), div_p2)
+#endif
+
 /** PLL/PLL1 clock source */
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll)) && \
 	DT_NODE_HAS_PROP(DT_NODELABEL(pll), clocks)
@@ -281,6 +336,9 @@
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll2)) && \
 	DT_NODE_HAS_PROP(DT_NODELABEL(pll2), clocks)
 #define DT_PLL2_CLOCKS_CTRL	DT_CLOCKS_CTLR(DT_NODELABEL(pll2))
+#if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
+#define STM32_PLL2_SRC_MSI	1
+#endif
 #if DT_SAME_NODE(DT_PLL2_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
 #define STM32_PLL2_SRC_MSIS	1
 #endif
@@ -297,6 +355,9 @@
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pll3)) && \
 	DT_NODE_HAS_PROP(DT_NODELABEL(pll3), clocks)
 #define DT_PLL3_CLOCKS_CTRL	DT_CLOCKS_CTLR(DT_NODELABEL(pll3))
+#if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
+#define STM32_PLL3_SRC_MSI	1
+#endif
 #if DT_SAME_NODE(DT_PLL3_CLOCKS_CTRL, DT_NODELABEL(clk_msis))
 #define STM32_PLL3_SRC_MSIS	1
 #endif
@@ -309,6 +370,22 @@
 
 #endif
 
+/** PLL4 clock source */
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(pll4), okay) && \
+	DT_NODE_HAS_PROP(DT_NODELABEL(pll4), clocks)
+#define DT_PLL4_CLOCKS_CTRL	DT_CLOCKS_CTLR(DT_NODELABEL(pll4))
+#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_msi))
+#define STM32_PLL4_SRC_MSI	1
+#endif
+#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_hsi))
+#define STM32_PLL4_SRC_HSI	1
+#endif
+#if DT_SAME_NODE(DT_PLL4_CLOCKS_CTRL, DT_NODELABEL(clk_hse))
+#define STM32_PLL4_SRC_HSE	1
+#endif
+
+#endif
+
 
 /** Fixed clocks related symbols */
 
@@ -386,7 +463,8 @@
 #define STM32_HSI_FREQ		DT_PROP(DT_NODELABEL(clk_hsi), clock_frequency)
 #elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32h7_hsi_clock, okay) \
 	|| DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32g0_hsi_clock, okay) \
-	|| DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32c0_hsi_clock, okay)
+	|| DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32c0_hsi_clock, okay) \
+	|| DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hsi), st_stm32n6_hsi_clock, okay)
 #define STM32_HSI_DIV_ENABLED	1
 #define STM32_HSI_ENABLED	1
 #define STM32_HSI_DIVISOR	DT_PROP(DT_NODELABEL(clk_hsi), hsi_div)
@@ -414,6 +492,11 @@
 #define STM32_HSE_ENABLED	1
 #define STM32_HSE_DIV2		DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
 #define STM32_HSE_FREQ		DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
+#elif DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(clk_hse), st_stm32n6_hse_clock, okay)
+#define STM32_HSE_ENABLED	1
+#define STM32_HSE_BYPASS	DT_PROP(DT_NODELABEL(clk_hse), hse_bypass)
+#define STM32_HSE_DIV2		DT_PROP(DT_NODELABEL(clk_hse), hse_div2)
+#define STM32_HSE_FREQ		DT_PROP(DT_NODELABEL(clk_hse), clock_frequency)
 #else
 #define STM32_HSE_FREQ		0
 #endif
@@ -431,6 +514,130 @@
 #define STM32_CKPER_ENABLED	1
 #endif
 
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(cpusw), st_stm32_clock_mux, okay)
+#define STM32_CPUSW_ENABLED	1
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic1), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC1_ENABLED	1
+#define STM32_IC1_PLL_SRC	DT_PROP(DT_NODELABEL(ic1), pll_src)
+#define STM32_IC1_DIV		DT_PROP(DT_NODELABEL(ic1), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic2), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC2_ENABLED	1
+#define STM32_IC2_PLL_SRC	DT_PROP(DT_NODELABEL(ic2), pll_src)
+#define STM32_IC2_DIV		DT_PROP(DT_NODELABEL(ic2), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic3), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC3_ENABLED	1
+#define STM32_IC3_PLL_SRC	DT_PROP(DT_NODELABEL(ic3), pll_src)
+#define STM32_IC3_DIV		DT_PROP(DT_NODELABEL(ic3), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic4), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC4_ENABLED	1
+#define STM32_IC4_PLL_SRC	DT_PROP(DT_NODELABEL(ic4), pll_src)
+#define STM32_IC4_DIV		DT_PROP(DT_NODELABEL(ic4), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic5), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC5_ENABLED	1
+#define STM32_IC5_PLL_SRC	DT_PROP(DT_NODELABEL(ic5), pll_src)
+#define STM32_IC5_DIV		DT_PROP(DT_NODELABEL(ic5), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic6), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC6_ENABLED	1
+#define STM32_IC6_PLL_SRC	DT_PROP(DT_NODELABEL(ic6), pll_src)
+#define STM32_IC6_DIV		DT_PROP(DT_NODELABEL(ic6), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic7), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC7_ENABLED	1
+#define STM32_IC7_PLL_SRC	DT_PROP(DT_NODELABEL(ic7), pll_src)
+#define STM32_IC7_DIV		DT_PROP(DT_NODELABEL(ic7), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic8), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC8_ENABLED	1
+#define STM32_IC8_PLL_SRC	DT_PROP(DT_NODELABEL(ic8), pll_src)
+#define STM32_IC8_DIV		DT_PROP(DT_NODELABEL(ic8), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic9), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC9_ENABLED	1
+#define STM32_IC9_PLL_SRC	DT_PROP(DT_NODELABEL(ic9), pll_src)
+#define STM32_IC9_DIV		DT_PROP(DT_NODELABEL(ic9), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic10), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC10_ENABLED	1
+#define STM32_IC10_PLL_SRC	DT_PROP(DT_NODELABEL(ic10), pll_src)
+#define STM32_IC10_DIV		DT_PROP(DT_NODELABEL(ic10), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic11), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC11_ENABLED	1
+#define STM32_IC11_PLL_SRC	DT_PROP(DT_NODELABEL(ic11), pll_src)
+#define STM32_IC11_DIV		DT_PROP(DT_NODELABEL(ic11), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic12), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC12_ENABLED	1
+#define STM32_IC12_PLL_SRC	DT_PROP(DT_NODELABEL(ic12), pll_src)
+#define STM32_IC12_DIV		DT_PROP(DT_NODELABEL(ic12), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic13), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC13_ENABLED	1
+#define STM32_IC13_PLL_SRC	DT_PROP(DT_NODELABEL(ic13), pll_src)
+#define STM32_IC13_DIV		DT_PROP(DT_NODELABEL(ic13), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic14), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC14_ENABLED	1
+#define STM32_IC14_PLL_SRC	DT_PROP(DT_NODELABEL(ic14), pll_src)
+#define STM32_IC14_DIV		DT_PROP(DT_NODELABEL(ic14), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic15), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC15_ENABLED	1
+#define STM32_IC15_PLL_SRC	DT_PROP(DT_NODELABEL(ic15), pll_src)
+#define STM32_IC15_DIV		DT_PROP(DT_NODELABEL(ic15), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic16), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC16_ENABLED	1
+#define STM32_IC16_PLL_SRC	DT_PROP(DT_NODELABEL(ic16), pll_src)
+#define STM32_IC16_DIV		DT_PROP(DT_NODELABEL(ic16), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic17), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC17_ENABLED	1
+#define STM32_IC17_PLL_SRC	DT_PROP(DT_NODELABEL(ic17), pll_src)
+#define STM32_IC17_DIV		DT_PROP(DT_NODELABEL(ic17), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic18), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC18_ENABLED	1
+#define STM32_IC18_PLL_SRC	DT_PROP(DT_NODELABEL(ic18), pll_src)
+#define STM32_IC18_DIV		DT_PROP(DT_NODELABEL(ic18), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic19), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC19_ENABLED	1
+#define STM32_IC19_PLL_SRC	DT_PROP(DT_NODELABEL(ic19), pll_src)
+#define STM32_IC19_DIV		DT_PROP(DT_NODELABEL(ic19), ic_div)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(ic20), st_stm32n6_ic_clock_mux, okay)
+#define STM32_IC20_ENABLED	1
+#define STM32_IC20_PLL_SRC	DT_PROP(DT_NODELABEL(ic20), pll_src)
+#define STM32_IC20_DIV		DT_PROP(DT_NODELABEL(ic20), ic_div)
+#endif
+
 /** Driver structure definition */
 
 struct stm32_pclken {
@@ -469,68 +676,36 @@ struct stm32_pclken {
 /** Clock source binding accessors */
 
 /**
- * @brief Obtain register field from clock configuration.
+ * @brief Obtain register field from clock source selection configuration.
  *
  * @param clock clock bit field value.
  */
-#define STM32_CLOCK_REG_GET(clock) \
-	(((clock) >> STM32_CLOCK_REG_SHIFT) & STM32_CLOCK_REG_MASK)
+#define STM32_DT_CLKSEL_REG_GET(clock) \
+	(((clock) >> STM32_DT_CLKSEL_REG_SHIFT) & STM32_DT_CLKSEL_REG_MASK)
 
 /**
- * @brief Obtain position field from clock configuration.
+ * @brief Obtain position field from clock source selection configuration.
  *
  * @param clock Clock bit field value.
  */
-#define STM32_CLOCK_SHIFT_GET(clock) \
-	(((clock) >> STM32_CLOCK_SHIFT_SHIFT) & STM32_CLOCK_SHIFT_MASK)
+#define STM32_DT_CLKSEL_SHIFT_GET(clock) \
+	(((clock) >> STM32_DT_CLKSEL_SHIFT_SHIFT) & STM32_DT_CLKSEL_SHIFT_MASK)
 
 /**
- * @brief Obtain mask field from clock configuration.
+ * @brief Obtain mask field from clock source selection configuration.
  *
  * @param clock Clock bit field value.
  */
-#define STM32_CLOCK_MASK_GET(clock) \
-	(((clock) >> STM32_CLOCK_MASK_SHIFT) & STM32_CLOCK_MASK_MASK)
+#define STM32_DT_CLKSEL_MASK_GET(clock) \
+	(((clock) >> STM32_DT_CLKSEL_MASK_SHIFT) & STM32_DT_CLKSEL_MASK_MASK)
 
 /**
- * @brief Obtain value field from clock configuration.
+ * @brief Obtain value field from clock source selection configuration.
  *
  * @param clock Clock bit field value.
  */
-#define STM32_CLOCK_VAL_GET(clock) \
-	(((clock) >> STM32_CLOCK_VAL_SHIFT) & STM32_CLOCK_VAL_MASK)
-
-/**
- * @brief Obtain register field from MCO configuration.
- *
- * @param mco_cfgr MCO configuration bit field value.
- */
-#define STM32_MCO_CFGR_REG_GET(mco_cfgr) \
-	(((mco_cfgr) >> STM32_MCO_CFGR_REG_SHIFT) & STM32_MCO_CFGR_REG_MASK)
-
-/**
- * @brief Obtain position field from MCO configuration.
- *
- * @param mco_cfgr MCO configuration bit field value.
- */
-#define STM32_MCO_CFGR_SHIFT_GET(mco_cfgr) \
-	(((mco_cfgr) >> STM32_MCO_CFGR_SHIFT_SHIFT) & STM32_MCO_CFGR_SHIFT_MASK)
-
-/**
- * @brief Obtain mask field from MCO configuration.
- *
- * @param mco_cfgr MCO configuration bit field value.
- */
-#define STM32_MCO_CFGR_MASK_GET(mco_cfgr) \
-	(((mco_cfgr) >> STM32_MCO_CFGR_MASK_SHIFT) & STM32_MCO_CFGR_MASK_MASK)
-
-/**
- * @brief Obtain value field from MCO configuration.
- *
- * @param mco_cfgr MCO configuration bit field value.
- */
-#define STM32_MCO_CFGR_VAL_GET(mco_cfgr) \
-	(((mco_cfgr) >> STM32_MCO_CFGR_VAL_SHIFT) & STM32_MCO_CFGR_VAL_MASK)
+#define STM32_DT_CLKSEL_VAL_GET(clock) \
+	(((clock) >> STM32_DT_CLKSEL_VAL_SHIFT) & STM32_DT_CLKSEL_VAL_MASK)
 
 #if defined(STM32_HSE_CSS)
 /**
diff --git a/include/zephyr/drivers/console/native_posix_console.h b/include/zephyr/drivers/console/native_posix_console.h
index 6a4429ab830..c68f1328742 100644
--- a/include/zephyr/drivers/console/native_posix_console.h
+++ b/include/zephyr/drivers/console/native_posix_console.h
@@ -7,6 +7,9 @@
 #ifndef ZEPHYR_INCLUDE_DRIVERS_CONSOLE_NATIVE_POSIX_CONSOLE_H_
 #define ZEPHYR_INCLUDE_DRIVERS_CONSOLE_NATIVE_POSIX_CONSOLE_H_
 
+#warning "This header is now deprecated and will be removed by v4.4. "\
+	 "Use posix_arch_console.h instead."
+
 /*
  * This header is left for compatibility with old applications
  * The console for native_posix is now provided by the posix_arch_console driver
diff --git a/include/zephyr/drivers/counter.h b/include/zephyr/drivers/counter.h
index 0e14ade3b51..d929c0d8332 100644
--- a/include/zephyr/drivers/counter.h
+++ b/include/zephyr/drivers/counter.h
@@ -215,6 +215,7 @@ typedef int (*counter_api_get_value)(const struct device *dev,
 				     uint32_t *ticks);
 typedef int (*counter_api_get_value_64)(const struct device *dev,
 			uint64_t *ticks);
+typedef int (*counter_api_reset)(const struct device *dev);
 typedef int (*counter_api_set_alarm)(const struct device *dev,
 				     uint8_t chan_id,
 				     const struct counter_alarm_cfg *alarm_cfg);
@@ -236,6 +237,7 @@ __subsystem struct counter_driver_api {
 	counter_api_stop stop;
 	counter_api_get_value get_value;
 	counter_api_get_value_64 get_value_64;
+	counter_api_reset reset;
 	counter_api_set_alarm set_alarm;
 	counter_api_cancel_alarm cancel_alarm;
 	counter_api_set_top_value set_top_value;
@@ -425,12 +427,33 @@ static inline int z_impl_counter_get_value_64(const struct device *dev,
 				(struct counter_driver_api *)dev->api;
 
 	if (!api->get_value_64) {
-		return -ENOTSUP;
+		return -ENOSYS;
 	}
 
 	return api->get_value_64(dev, ticks);
 }
 
+/**
+ * @brief Reset the counter to the initial value.
+ * @param dev Pointer to the device structure for the driver instance.
+ *
+ * @retval 0 If successful.
+ * @retval -errno Negative error code on failure resetting the counter value.
+ */
+__syscall int counter_reset(const struct device *dev);
+
+static inline int z_impl_counter_reset(const struct device *dev)
+{
+	const struct counter_driver_api *api =
+				(struct counter_driver_api *)dev->api;
+
+	if (!api->reset) {
+		return -ENOSYS;
+	}
+
+	return api->reset(dev);
+}
+
 /**
  * @brief Set a single shot alarm on a channel.
  *
@@ -627,7 +650,7 @@ static inline uint32_t z_impl_counter_get_top_value(const struct device *dev)
  * @param flags		See @ref COUNTER_GUARD_PERIOD_FLAGS.
  *
  * @retval 0 if successful.
- * @retval -ENOTSUP if function or flags are not supported.
+ * @retval -ENOSYS if function or flags are not supported.
  * @retval -EINVAL if ticks value is invalid.
  */
 __syscall int counter_set_guard_period(const struct device *dev,
@@ -641,7 +664,7 @@ static inline int z_impl_counter_set_guard_period(const struct device *dev,
 				(struct counter_driver_api *)dev->api;
 
 	if (!api->set_guard_period) {
-		return -ENOTSUP;
+		return -ENOSYS;
 	}
 
 	return api->set_guard_period(dev, ticks, flags);
diff --git a/include/zephyr/drivers/dac/dac161s997.h b/include/zephyr/drivers/dac/dac161s997.h
new file mode 100644
index 00000000000..2ffe5d44e57
--- /dev/null
+++ b/include/zephyr/drivers/dac/dac161s997.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright 2025 Vitrolife A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_DAC_DAC161S997_H_
+#define ZEPHYR_INCLUDE_DRIVERS_DAC_DAC161S997_H_
+
+#include <stdint.h>
+#include <zephyr/device.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+union dac161s997_status {
+	uint8_t raw;
+	struct {
+		/**
+		 * True if the DAC161S997 is unable to maintain the output current.
+		 */
+		bool current_loop_status: 1;
+		/**
+		 * Identical to current_loop_status except this bit is sticky.
+		 */
+		bool loop_status: 1;
+		/**
+		 * True if a SPI command has not been received within SPI timeout period (default
+		 * 100 ms). If this error occurs, it is cleared with a properly formatted write
+		 * command to a valid address.
+		 */
+		bool spi_timeout_error: 1;
+		/**
+		 * A frame error is caused by an incorrect number of clocks during a register write.
+		 * A register write without an integer multiple of 24 clock cycles will cause a
+		 * Frame error.
+		 */
+		bool frame_status: 1;
+		/**
+		 * Returns the state of the ERR_LVL pin.
+		 */
+		bool error_level_pin_state: 1;
+		/**
+		 * DAC resolution register. Always returns 0x7.
+		 */
+		uint8_t dac_resolution: 3;
+	} __packed;
+};
+
+/**
+ * @typedef dac161s997_error_callback_t
+ * @brief Callback to invoke when an error is triggered
+ *
+ * @param dev Pointer to the device
+ * @param status NULL if read was not possible otherwise pointer to status.
+ */
+typedef void (*dac161s997_error_callback_t)(const struct device *dev,
+					    const union dac161s997_status *status);
+
+/**
+ * @brief Set callback to invoke when an error is triggered
+ *
+ * The callback runs in a work queue context and the device is locked while it runs.
+ *
+ * @param dev Pointer to the device
+ * @param cb Callback to invoke when an error is triggered
+ *
+ * @returns 0 on success and -errno otherwise.
+ */
+int dac161s997_set_error_callback(const struct device *dev, dac161s997_error_callback_t cb);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_DAC_DAC161S997_H_ */
diff --git a/include/zephyr/drivers/dai.h b/include/zephyr/drivers/dai.h
index 7af4157d442..6ae17110567 100644
--- a/include/zephyr/drivers/dai.h
+++ b/include/zephyr/drivers/dai.h
@@ -115,6 +115,7 @@ enum dai_type {
 	DAI_INTEL_DMIC_NHLT,	/**< nhlt ssp */
 	DAI_INTEL_HDA_NHLT,	/**< nhlt Intel HD/A */
 	DAI_INTEL_ALH_NHLT,	/**< nhlt Intel ALH */
+	DAI_IMX_MICFIL,		/**< i.MX PDM MICFIL */
 };
 
 /**
diff --git a/include/zephyr/drivers/display.h b/include/zephyr/drivers/display.h
index 8fd26978bea..c458050b27d 100644
--- a/include/zephyr/drivers/display.h
+++ b/include/zephyr/drivers/display.h
@@ -46,6 +46,8 @@ enum display_pixel_format {
 	PIXEL_FORMAT_ARGB_8888		= BIT(3), /**< 32-bit ARGB */
 	PIXEL_FORMAT_RGB_565		= BIT(4), /**< 16-bit RGB */
 	PIXEL_FORMAT_BGR_565		= BIT(5), /**< 16-bit BGR */
+	PIXEL_FORMAT_L_8		= BIT(6), /**< 8-bit Grayscale/Luminance, equivalent to */
+						  /**< GRAY, GREY, GRAY8, Y8, R8, etc...        */
 };
 
 /**
@@ -61,7 +63,8 @@ enum display_pixel_format {
 	(((fmt & PIXEL_FORMAT_MONO10) >> 2) * 1U) +				\
 	(((fmt & PIXEL_FORMAT_ARGB_8888) >> 3) * 32U) +				\
 	(((fmt & PIXEL_FORMAT_RGB_565) >> 4) * 16U) +				\
-	(((fmt & PIXEL_FORMAT_BGR_565) >> 5) * 16U))
+	(((fmt & PIXEL_FORMAT_BGR_565) >> 5) * 16U) +				\
+	(((fmt & PIXEL_FORMAT_L_8) >> 6) * 8U))
 
 /**
  * @brief Display screen information
@@ -165,6 +168,13 @@ typedef int (*display_read_api)(const struct device *dev, const uint16_t x,
 				const struct display_buffer_descriptor *desc,
 				void *buf);
 
+/**
+ * @typedef display_clear
+ * @brief Callback API for clearing the screen of the display
+ * See display_clear() for argument description
+ */
+typedef int (*display_clear_api)(const struct device *dev);
+
 /**
  * @typedef display_get_framebuffer_api
  * @brief Callback API to get framebuffer pointer
@@ -224,6 +234,7 @@ __subsystem struct display_driver_api {
 	display_blanking_off_api blanking_off;
 	display_write_api write;
 	display_read_api read;
+	display_clear_api clear;
 	display_get_framebuffer_api get_framebuffer;
 	display_set_brightness_api set_brightness;
 	display_set_contrast_api set_contrast;
@@ -281,6 +292,26 @@ static inline int display_read(const struct device *dev, const uint16_t x,
 	return api->read(dev, x, y, desc, buf);
 }
 
+/**
+ * @brief Clear the screen of the display device
+ *
+ * @param dev Pointer to device structure
+ *
+ * @retval 0 on success else negative errno code.
+ * @retval -ENOSYS if not implemented.
+ */
+static inline int display_clear(const struct device *dev)
+{
+	struct display_driver_api *api =
+		(struct display_driver_api *)dev->api;
+
+	if (api->clear == NULL) {
+		return -ENOSYS;
+	}
+
+	return api->clear(dev);
+}
+
 /**
  * @brief Get pointer to framebuffer for direct access
  *
diff --git a/include/zephyr/drivers/dma/dma_silabs_ldma.h b/include/zephyr/drivers/dma/dma_silabs_ldma.h
new file mode 100644
index 00000000000..3a99a122e5b
--- /dev/null
+++ b/include/zephyr/drivers/dma/dma_silabs_ldma.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_DMA_SILABS_LDMA_H_
+#define ZEPHYR_INCLUDE_DRIVERS_DMA_SILABS_LDMA_H_
+
+#include <zephyr/drivers/dma.h>
+
+#define SILABS_LDMA_SOURCE_MASK  GENMASK(21, 16)
+#define SILABS_LDMA_SIG_MASK     GENMASK(3, 0)
+
+#define SILABS_DMA_SLOT_SOURCE_MASK  GENMASK(7, 3)
+#define SILABS_DMA_SLOT_SIG_MASK     GENMASK(2, 0)
+
+#define SILABS_LDMA_REQSEL_TO_SLOT(signal)             \
+	FIELD_PREP(SILABS_DMA_SLOT_SOURCE_MASK, FIELD_GET(SILABS_LDMA_SOURCE_MASK, signal)) | \
+	FIELD_PREP(SILABS_DMA_SLOT_SIG_MASK, FIELD_GET(SILABS_LDMA_SIG_MASK, signal))
+
+#define SILABS_LDMA_SLOT_TO_REQSEL(slot)     \
+	FIELD_PREP(SILABS_LDMA_SOURCE_MASK, FIELD_GET(SILABS_DMA_SLOT_SOURCE_MASK, slot)) | \
+	FIELD_PREP(SILABS_LDMA_SIG_MASK, FIELD_GET(SILABS_DMA_SLOT_SIG_MASK, slot))
+
+/**
+ * @brief Append a new block to the current channel
+ *
+ * This function allows to append a block to the current DMA transfer. It allows a user/driver
+ * to register the next DMA transfer while a transfer in being held without stopping or restarting
+ * DMA engine. It is very suitable for Zephyr Uart API where user gives buffers while the DMA engine
+ * is running. Because this function changes dynamically the link to the block that DMA engine would
+ * load as the next transfer, it is only working with channel that didn't have linked block list.
+ *
+ * In the case that the DMA engine naturally stopped because the previous transfer is finished, this
+ * function simply restart the DMA engine with the given block. If the DMA engine stopped while
+ * reconfiguring the next transfer, the DMA engine will restart too.
+ *
+ * @param dev: dma device
+ * @param channel: channel
+ * @param config: configuration of the channel with the block to append as the head_block.
+ */
+int silabs_ldma_append_block(const struct device *dev, uint32_t channel,
+					struct dma_config *config);
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_DMA_SILABS_LDMA_H_*/
diff --git a/include/zephyr/drivers/dma/dma_stm32.h b/include/zephyr/drivers/dma/dma_stm32.h
index cd661f20965..38f395b0108 100644
--- a/include/zephyr/drivers/dma/dma_stm32.h
+++ b/include/zephyr/drivers/dma/dma_stm32.h
@@ -56,6 +56,8 @@
 		DT_INST_DMAS_CELL_BY_IDX(id, idx, channel_config)
 
 /* macros for channel-config */
+/* enable circular buffer */
+#define STM32_DMA_CONFIG_CYCLIC(config)                 ((config >> 5) & 0x1)
 /* direction defined on bits 6-7 */
 /* 0 -> MEM_TO_MEM, 1 -> MEM_TO_PERIPH, 2 -> PERIPH_TO_MEM */
 #define STM32_DMA_CONFIG_DIRECTION(config)		((config >> 6) & 0x3)
diff --git a/include/zephyr/drivers/espi.h b/include/zephyr/drivers/espi.h
index 62e4ce5e28b..d3c39d1e0d9 100644
--- a/include/zephyr/drivers/espi.h
+++ b/include/zephyr/drivers/espi.h
@@ -728,6 +728,8 @@ static inline int z_impl_espi_write_lpc_request(const struct device *dev,
  *
  * @retval 0 If successful.
  * @retval -EIO General input / output error, failed to send over the bus.
+ * @retval -EINVAL invalid signal.
+ * @retval -ETIMEDOUT timeout waiting for eSPI controller to process the VW.
  */
 __syscall int espi_send_vwire(const struct device *dev,
 			      enum espi_vwire_signal signal,
diff --git a/include/zephyr/drivers/ethernet/eth_lan865x.h b/include/zephyr/drivers/ethernet/eth_lan865x.h
new file mode 100644
index 00000000000..4a7e7f11556
--- /dev/null
+++ b/include/zephyr/drivers/ethernet/eth_lan865x.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2024 Microchip Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_ETH_LAN865X_H__
+#define ZEPHYR_INCLUDE_DRIVERS_ETH_LAN865X_H__
+
+#include <stdint.h>
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+
+/**
+ * @brief      Read C22 registers using LAN865X MDIO Bus
+ *
+ * This routine provides an interface to perform a C22 register read on the
+ * LAN865X MDIO bus.
+ *
+ * @param[in]  dev         Pointer to the device structure for the controller
+ * @param[in]  prtad       Port address
+ * @param[in]  regad       Register address
+ * @param      data        Pointer to receive read data
+ *
+ * @retval 0 If successful.
+ * @retval -EIO General input / output error.
+ * @retval -ETIMEDOUT If transaction timedout on the bus
+ * @retval -ENOSYS if read is not supported
+ */
+int eth_lan865x_mdio_c22_read(const struct device *dev, uint8_t prtad, uint8_t regad,
+			      uint16_t *data);
+
+/**
+ * @brief      Write C22 registers using LAN865X MDIO Bus
+ *
+ * This routine provides an interface to perform a C22 register write on the
+ * LAN865X MDIO bus.
+ *
+ * @param[in]  dev         Pointer to the device structure for the controller
+ * @param[in]  prtad       Port address
+ * @param[in]  regad       Register address
+ * @param[in]  data        Write data
+ *
+ * @retval 0 If successful.
+ * @retval -EIO General input / output error.
+ * @retval -ETIMEDOUT If transaction timedout on the bus
+ * @retval -ENOSYS if read is not supported
+ */
+int eth_lan865x_mdio_c22_write(const struct device *dev, uint8_t prtad, uint8_t regad,
+			       uint16_t data);
+
+/**
+ * @brief      Read C45 registers using LAN865X MDIO Bus
+ *
+ * This routine provides an interface to perform a C45 register read on the
+ * LAN865X MDIO bus.
+ *
+ * @param[in]  dev         Pointer to the device structure for the controller
+ * @param[in]  prtad       Port address
+ * @param[in]  devad       MMD device address
+ * @param[in]  regad       Register address
+ * @param      data        Pointer to receive read data
+ *
+ * @retval 0 If successful.
+ * @retval -EIO General input / output error.
+ * @retval -ETIMEDOUT If transaction timedout on the bus
+ * @retval -ENOSYS if read is not supported
+ */
+int eth_lan865x_mdio_c45_read(const struct device *dev, uint8_t prtad, uint8_t devad,
+			      uint16_t regad, uint16_t *data);
+
+/**
+ * @brief      Write C45 registers using LAN865X MDIO Bus
+ *
+ * This routine provides an interface to perform a C45 register write on the
+ * LAN865X MDIO bus.
+ *
+ * @param[in]  dev         Pointer to the device structure for the controller
+ * @param[in]  prtad       Port address
+ * @param[in]  devad       MMD device address
+ * @param[in]  regad       Register address
+ * @param[in]  data        Write data
+ *
+ * @retval 0 If successful.
+ * @retval -EIO General input / output error.
+ * @retval -ETIMEDOUT If transaction timedout on the bus
+ * @retval -ENOSYS if read is not supported
+ */
+int eth_lan865x_mdio_c45_write(const struct device *dev, uint8_t prtad, uint8_t devad,
+			       uint16_t regad, uint16_t data);
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_ETH_LAN865X_H__ */
diff --git a/include/zephyr/drivers/firmware/scmi/clk.h b/include/zephyr/drivers/firmware/scmi/clk.h
index e56fc9df244..d13cfd13679 100644
--- a/include/zephyr/drivers/firmware/scmi/clk.h
+++ b/include/zephyr/drivers/firmware/scmi/clk.h
@@ -20,6 +20,11 @@
 
 #define SCMI_CLK_ATTRIBUTES_CLK_NUM(x) ((x) & GENMASK(15, 0))
 
+#define SCMI_CLK_RATE_SET_FLAGS_ASYNC                BIT(0)
+#define SCMI_CLK_RATE_SET_FLAGS_IGNORE_DELEAYED_RESP BIT(1)
+#define SCMI_CLK_RATE_SET_FLAGS_ROUNDS_UP_DOWN       BIT(2)
+#define SCMI_CLK_RATE_SET_FLAGS_ROUNDS_AUTO          BIT(3)
+
 /**
  * @struct scmi_clock_config
  *
@@ -32,6 +37,18 @@ struct scmi_clock_config {
 	uint32_t extended_cfg_val;
 };
 
+/**
+ * @struct scmi_clock_rate_config
+ *
+ * @brief Describes the parameters for the CLOCK_RATE_SET
+ * command
+ */
+struct scmi_clock_rate_config {
+	uint32_t flags;
+	uint32_t clk_id;
+	uint32_t rate[2];
+};
+
 /**
  * @brief Clock protocol command message IDs
  */
@@ -93,4 +110,41 @@ int scmi_clock_config_set(struct scmi_protocol *proto,
 int scmi_clock_rate_get(struct scmi_protocol *proto,
 			uint32_t clk_id, uint32_t *rate);
 
+/**
+ * @brief Send the CLOCK_RATE_SET command and get its reply
+ *
+ * @param proto pointer to SCMI clock protocol data
+ * @param cfg pointer to structure containing configuration
+ * to be set
+ *
+ * @retval 0 if successful
+ * @retval negative errno if failure
+ */
+int scmi_clock_rate_set(struct scmi_protocol *proto, struct scmi_clock_rate_config *cfg);
+
+/**
+ * @brief Query the parent of a clock
+ *
+ * @param proto pointer to SCMI clock protocol data
+ * @param clk_id ID of the clock for which the query is done
+ * @param parent_id pointer to be set via this command
+ *
+ * @retval 0 if successful
+ * @retval negative errno if failure
+ */
+int scmi_clock_parent_get(struct scmi_protocol *proto, uint32_t clk_id, uint32_t *parent_id);
+
+/**
+ * @brief Send the CLOCK_PARENT_SET command and get its reply
+ *
+ * @param proto pointer to SCMI clock protocol data
+ * @param clk_id ID of the clock for which the query is done
+ * @param parent_id to be set via this command
+ * to be set
+ *
+ * @retval 0 if successful
+ * @retval negative errno if failure
+ */
+int scmi_clock_parent_set(struct scmi_protocol *proto, uint32_t clk_id, uint32_t parent_id);
+
 #endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CLK_H_ */
diff --git a/include/zephyr/drivers/firmware/scmi/nxp/cpu.h b/include/zephyr/drivers/firmware/scmi/nxp/cpu.h
new file mode 100644
index 00000000000..687175912ec
--- /dev/null
+++ b/include/zephyr/drivers/firmware/scmi/nxp/cpu.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief SCMI power domain protocol helpers
+ */
+
+#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CPU_H_
+#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CPU_H_
+
+#include <zephyr/drivers/firmware/scmi/protocol.h>
+#if __has_include("scmi_cpu_soc.h")
+#include <scmi_cpu_soc.h>
+#endif
+
+#define SCMI_CPU_SLEEP_FLAG_IRQ_MUX 0x1U
+
+#define SCMI_PROTOCOL_CPU_DOMAIN 130
+
+/**
+ * @struct scmi_cpu_sleep_mode_config
+ *
+ * @brief Describes the parameters for the CPU_STATE_SET
+ * command
+ */
+struct scmi_cpu_sleep_mode_config {
+	uint32_t cpu_id;
+	uint32_t flags;
+	uint32_t sleep_mode;
+};
+
+/**
+ * @brief CPU domain protocol command message IDs
+ */
+enum scmi_cpu_domain_message {
+	SCMI_CPU_DOMAIN_MSG_PROTOCOL_VERSION = 0x0,
+	SCMI_CPU_DOMAIN_MSG_PROTOCOL_ATTRIBUTES = 0x1,
+	SCMI_CPU_DOMAIN_MSG_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2,
+	SCMI_CPU_DOMAIN_MSG_CPU_DOMAIN_ATTRIBUTES = 0x3,
+	SCMI_CPU_DOMAIN_MSG_CPU_START = 0x4,
+	SCMI_CPU_DOMAIN_MSG_CPU_STOP = 0x5,
+	SCMI_CPU_DOMAIN_MSG_CPU_RESET_VECTOR_SET = 0x6,
+	SCMI_CPU_DOMAIN_MSG_CPU_SLEEP_MODE_SET = 0x7,
+	SCMI_CPU_DOMAIN_MSG_CPU_IRQ_WAKE_SET = 0x8,
+	SCMI_CPU_DOMAIN_MSG_CPU_NON_IRQ_WAKE_SET = 0x9,
+	SCMI_CPU_DOMAIN_MSG_CPU_PD_LPM_CONFIG_SET = 0xA,
+	SCMI_CPU_DOMAIN_MSG_CPU_PER_LPM_CONFIG_SET = 0xB,
+	SCMI_CPU_DOMAIN_MSG_CPU_INFO_GET = 0xC,
+	SCMI_CPU_DOMAIN_MSG_NEGOTIATE_PROTOCOL_VERSION = 0x10,
+};
+
+/**
+ * @brief Send the CPU_SLEEP_MODE_SET command and get its reply
+ *
+ * @param cfg pointer to structure containing configuration
+ * to be set
+ *
+ * @retval 0 if successful
+ * @retval negative errno if failure
+ */
+int scmi_cpu_sleep_mode_set(struct scmi_cpu_sleep_mode_config *cfg);
+
+#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CPU_H_ */
diff --git a/include/zephyr/drivers/firmware/scmi/power.h b/include/zephyr/drivers/firmware/scmi/power.h
new file mode 100644
index 00000000000..649209c7469
--- /dev/null
+++ b/include/zephyr/drivers/firmware/scmi/power.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief SCMI power domain protocol helpers
+ */
+
+#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_POWER_H_
+#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_POWER_H_
+
+#include <zephyr/drivers/firmware/scmi/protocol.h>
+
+#define SCMI_POWER_STATE_SET_FLAGS_ASYNC BIT(0)
+
+/**
+ * @struct scmi_power_state_config
+ *
+ * @brief Describes the parameters for the POWER_STATE_SET
+ * command
+ */
+struct scmi_power_state_config {
+	uint32_t flags;
+	uint32_t domain_id;
+	uint32_t power_state;
+};
+
+/**
+ * @brief Power domain protocol command message IDs
+ */
+enum scmi_power_domain_message {
+	SCMI_POWER_DOMAIN_MSG_PROTOCOL_VERSION = 0x0,
+	SCMI_POWER_DOMAIN_MSG_PROTOCOL_ATTRIBUTES = 0x1,
+	SCMI_POWER_DOMAIN_MSG_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2,
+	SCMI_POWER_DOMAIN_MSG_POWER_DOMAIN_ATTRIBUTES = 0x3,
+	SCMI_POWER_DOMAIN_MSG_POWER_STATE_SET = 0x4,
+	SCMI_POWER_DOMAIN_MSG_POWER_STATE_GET = 0x5,
+	SCMI_POWER_DOMAIN_MSG_POWER_STATE_NOTIFY = 0x6,
+	SCMI_POWER_DOMAIN_MSG_POWER_STATE_CHANGE_REQEUSTED_NOTIFY = 0x7,
+	SCMI_POWER_DOMAIN_MSG_POWER_DOMAIN_NAME_GET = 0x8,
+	SCMI_POWER_DOMAIN_MSG_NEGOTIATE_PROTOCOL_VERSION = 0x10,
+};
+
+/**
+ * @brief Send the POWER_STATE_SET command and get its reply
+ *
+ * @param cfg pointer to structure containing configuration
+ * to be set
+ *
+ * @retval 0 if successful
+ * @retval negative errno if failure
+ */
+int scmi_power_state_set(struct scmi_power_state_config *cfg);
+/**
+ * @brief Query the power domain state
+ *
+ * @param domain_id ID of the power domain for which the query is done
+ * @param power_state pointer to be set via this command
+ *
+ * @retval 0 if successful
+ * @retval negative errno if failure
+ */
+int scmi_power_state_get(uint32_t domain_id, uint32_t *power_state);
+
+#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_POWER_H_ */
diff --git a/include/zephyr/drivers/firmware/scmi/shmem.h b/include/zephyr/drivers/firmware/scmi/shmem.h
index a655a361e69..662bf793373 100644
--- a/include/zephyr/drivers/firmware/scmi/shmem.h
+++ b/include/zephyr/drivers/firmware/scmi/shmem.h
@@ -19,6 +19,15 @@
 #define SCMI_SHMEM_CHAN_STATUS_BUSY_BIT BIT(0)
 #define SCMI_SHMEM_CHAN_FLAG_IRQ_BIT BIT(0)
 
+struct scmi_shmem_layout {
+	volatile uint32_t res0;
+	volatile uint32_t chan_status;
+	volatile uint32_t res1[2];
+	volatile uint32_t chan_flags;
+	volatile uint32_t len;
+	volatile uint32_t msg_hdr;
+};
+
 struct scmi_message;
 
 /**
@@ -64,4 +73,24 @@ void scmi_shmem_update_flags(const struct device *shmem,
  */
 uint32_t scmi_shmem_channel_status(const struct device *shmem);
 
+/**
+ * @brief Process vendor specific features when writing message
+ *
+ * @param layout layout of the message
+ *
+ * @retval 0 if successful
+ * @retval negative errno if failure
+ */
+int scmi_shmem_vendor_write_message(struct scmi_shmem_layout *layout);
+
+/**
+ * @brief Process vendor specific features when reading message
+ *
+ * @param layout layout of the message
+ *
+ * @retval 0 if successful
+ * @retval negative errno if failure
+ */
+int scmi_shmem_vendor_read_message(const struct scmi_shmem_layout *layout);
+
 #endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_SHMEM_H_ */
diff --git a/include/zephyr/drivers/gnss.h b/include/zephyr/drivers/gnss.h
index c5d2b9174cc..3a0ba8ba1b6 100644
--- a/include/zephyr/drivers/gnss.h
+++ b/include/zephyr/drivers/gnss.h
@@ -140,6 +140,8 @@ struct gnss_info {
 	uint16_t satellites_cnt;
 	/** Horizontal dilution of precision in 1/1000 */
 	uint32_t hdop;
+	/** Geoid separation in millimeters */
+	int32_t geoid_separation;
 	/** The fix status */
 	enum gnss_fix_status fix_status;
 	/** The fix quality */
diff --git a/include/zephyr/drivers/gpio.h b/include/zephyr/drivers/gpio.h
index c1c0c261c4f..3eed8194726 100644
--- a/include/zephyr/drivers/gpio.h
+++ b/include/zephyr/drivers/gpio.h
@@ -810,7 +810,8 @@ __subsystem struct gpio_driver_api {
 				gpio_port_pins_t pins);
 	int (*pin_interrupt_configure)(const struct device *port,
 				       gpio_pin_t pin,
-				       enum gpio_int_mode, enum gpio_int_trig);
+				       enum gpio_int_mode mode,
+				       enum gpio_int_trig trig);
 	int (*manage_callback)(const struct device *port,
 			       struct gpio_callback *cb,
 			       bool set);
diff --git a/include/zephyr/drivers/gpio/gpio_ambiq.h b/include/zephyr/drivers/gpio/gpio_ambiq.h
new file mode 100644
index 00000000000..eec0e34fe0c
--- /dev/null
+++ b/include/zephyr/drivers/gpio/gpio_ambiq.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 Ambiq Micro Inc. <www.ambiq.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_GPIO_GPIO_AMBIQ_H_
+#define ZEPHYR_DRIVERS_GPIO_GPIO_AMBIQ_H_
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Get the actual gpio pin number.
+ *
+ * @param dev Pointer to the device structure for the driver instance.
+ * @param pin Pin number of the select gpio group.
+ *
+ * @retval pin number.
+ */
+gpio_pin_t ambiq_gpio_get_pinnum(const struct device *dev, gpio_pin_t pin);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_DRIVERS_GPIO_GPIO_AMBIQ_H_ */
diff --git a/include/zephyr/drivers/gpio/gpio_cmsdk_ahb.h b/include/zephyr/drivers/gpio/gpio_cmsdk_ahb.h
index 46ba451c0e7..de65f7a4c6a 100644
--- a/include/zephyr/drivers/gpio/gpio_cmsdk_ahb.h
+++ b/include/zephyr/drivers/gpio/gpio_cmsdk_ahb.h
@@ -52,6 +52,8 @@ struct gpio_cmsdk_ahb {
 	volatile uint32_t ub_masked[256];
 };
 
+int cmsdk_ahb_gpio_config(const struct device *dev, uint32_t mask, gpio_flags_t flags);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/zephyr/drivers/gpio/gpio_mcux_lpc.h b/include/zephyr/drivers/gpio/gpio_mcux_lpc.h
new file mode 100644
index 00000000000..74101a0ab9e
--- /dev/null
+++ b/include/zephyr/drivers/gpio/gpio_mcux_lpc.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_GPIO_MCUX_LPC_H_
+#define ZEPHYR_INCLUDE_DRIVERS_GPIO_MCUX_LPC_H_
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+
+/**
+ * @brief Trigger a callback for a given pin.
+ *
+ * This allows other drivers to fire callbacks for the pin.
+ *
+ * @param dev  Pointer to the device structure for the driver instance.
+ * @param pins The actual pin mask that triggered the interrupt.
+ *
+ */
+void gpio_mcux_lpc_trigger_cb(const struct device *dev, uint32_t pins);
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_MCUX_LPC_H_ */
diff --git a/include/zephyr/drivers/gpio/gpio_mmio32.h b/include/zephyr/drivers/gpio/gpio_mmio32.h
deleted file mode 100644
index 005f7205293..00000000000
--- a/include/zephyr/drivers/gpio/gpio_mmio32.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright (c) 2016 Linaro Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_MMIO32_H_
-#define ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_MMIO32_H_
-
-#include <zephyr/device.h>
-#include <zephyr/drivers/gpio.h>
-#include <zephyr/types.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-extern const struct gpio_driver_api gpio_mmio32_api;
-
-struct gpio_mmio32_config {
-	/* gpio_driver_config needs to be first */
-	struct gpio_driver_config common;
-	volatile uint32_t *reg;
-	uint32_t mask;
-};
-
-struct gpio_mmio32_context {
-	/* gpio_driver_data needs to be first */
-	struct gpio_driver_data common;
-	const struct gpio_mmio32_config *config;
-};
-
-int gpio_mmio32_init(const struct device *dev);
-
-#ifdef CONFIG_GPIO_MMIO32
-
-/**
- * Create a device object for accessing a simple 32-bit i/o register using the
- * same APIs as GPIO drivers.
- *
- * @param node_id   The devicetree node identifier.
- * @param _address  The address of the 32-bit i/o register the device will
- *		    provide access to.
- * @param _mask     Mask of bits in the register that it is valid to access.
- *		    E.g. 0xffffffffu to allow access to all of them.
- *
- */
-#define GPIO_MMIO32_INIT(node_id, _address, _mask)					\
-static struct gpio_mmio32_context _CONCAT(Z_DEVICE_DT_DEV_ID(node_id), _ctx);		\
-											\
-static const struct gpio_mmio32_config _CONCAT(Z_DEVICE_DT_DEV_ID(node_id), _cfg) = {	\
-	.common = {									\
-		 .port_pin_mask = _mask,						\
-	},										\
-	.reg	= (volatile uint32_t *)_address,					\
-	.mask	= _mask,								\
-};											\
-											\
-DEVICE_DT_DEFINE(node_id,								\
-		    &gpio_mmio32_init,							\
-		    NULL,								\
-		    &_CONCAT(Z_DEVICE_DT_DEV_ID(node_id), _ctx),			\
-		    &_CONCAT(Z_DEVICE_DT_DEV_ID(node_id), _cfg),			\
-		    PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,			\
-		    &gpio_mmio32_api)
-
-
-#else /* CONFIG_GPIO_MMIO32 */
-
-/* Null definition for when support not configured into kernel */
-#define GPIO_MMIO32_INIT(node_id, _address, _mask)
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ZEPHYR_INCLUDE_DRIVERS_GPIO_GPIO_MMIO32_H_ */
diff --git a/include/zephyr/drivers/haptics/drv2605.h b/include/zephyr/drivers/haptics/drv2605.h
index ada27d096df..0d4a8c671a7 100644
--- a/include/zephyr/drivers/haptics/drv2605.h
+++ b/include/zephyr/drivers/haptics/drv2605.h
@@ -9,6 +9,10 @@
 #include <zephyr/drivers/haptics.h>
 #include <zephyr/types.h>
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 #define DRV2605_WAVEFORM_SEQUENCER_MAX 8
 
 enum drv2605_library {
@@ -83,4 +87,8 @@ union drv2605_config_data {
 int drv2605_haptic_config(const struct device *dev, enum drv2605_haptics_source source,
 			  const union drv2605_config_data *config_data);
 
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
 #endif
diff --git a/include/zephyr/drivers/i2c.h b/include/zephyr/drivers/i2c.h
index 5f1c3fbe8ae..09640e3275d 100644
--- a/include/zephyr/drivers/i2c.h
+++ b/include/zephyr/drivers/i2c.h
@@ -668,7 +668,8 @@ static inline void i2c_xfer_stats(const struct device *dev, struct i2c_msg *msgs
 	Z_DEVICE_DEFINE(node_id, Z_DEVICE_DT_DEV_ID(node_id),		\
 			DEVICE_DT_NAME(node_id),			\
 			&UTIL_CAT(Z_DEVICE_DT_DEV_ID(node_id), _init),	\
-			pm, data, config, level, prio, api,	\
+			NULL, Z_DEVICE_DT_FLAGS(node_id), pm, data,	\
+			config,	level, prio, api,			\
 			&(Z_DEVICE_STATE_NAME(Z_DEVICE_DT_DEV_ID(node_id)).devstate), \
 			__VA_ARGS__)
 
@@ -722,6 +723,25 @@ static inline int z_impl_i2c_configure(const struct device *dev,
 	return api->configure(dev, dev_config);
 }
 
+/**
+ * @brief Configure operation of a host controller.
+ *
+ * This is equivalent to:
+ *
+ *     i2c_configure(spec->bus, dev_config);
+ *
+ * @param spec I2C specification from devicetree.
+ * @param dev_config Bit-packed 32-bit value to the device runtime configuration
+ * for the I2C controller.
+ *
+ * @return a value from i2c_configure()
+ */
+static inline int i2c_configure_dt(const struct i2c_dt_spec *spec,
+						uint32_t dev_config)
+{
+	return i2c_configure(spec->bus, dev_config);
+}
+
 /**
  * @brief Get configuration of a host controller.
  *
@@ -1076,6 +1096,21 @@ extern const struct rtio_iodev_api i2c_iodev_api;
 	};                                                                      \
 	RTIO_IODEV_DEFINE(name, &i2c_iodev_api, (void *)&_i2c_dt_spec_##name)
 
+/**
+ * @brief Validate that I2C bus is ready.
+ *
+ * @param i2c_iodev I2C iodev defined with I2C_DT_IODEV_DEFINE
+ *
+ * @retval true if the I2C bus is ready for use.
+ * @retval false if the I2C bus is not ready for use.
+ */
+static inline bool i2c_is_ready_iodev(const struct rtio_iodev *i2c_iodev)
+{
+	struct i2c_dt_spec *spec = (struct i2c_dt_spec *)i2c_iodev->data;
+
+	return i2c_is_ready_dt(spec);
+}
+
 /**
  * @brief Copy the i2c_msgs into a set of RTIO requests
  *
@@ -1092,6 +1127,35 @@ struct rtio_sqe *i2c_rtio_copy(struct rtio *r,
 			       const struct i2c_msg *msgs,
 			       uint8_t num_msgs);
 
+/**
+ * @brief Copy the register address and data to a SQE
+ *
+ * @param r RTIO context
+ * @param iodev RTIO IODev to target for the submissions
+ * @param reg_addr target register address
+ * @param data data to be written
+ *
+ * @retval sqe Last submission in the queue added
+ * @retval NULL Not enough memory in the context to copy the requests
+ */
+struct rtio_sqe *i2c_rtio_copy_reg_write_byte(struct rtio *r, struct rtio_iodev *iodev,
+					      uint8_t reg_addr, uint8_t data);
+
+/**
+ * @brief acquire and configure a i2c burst read transmission
+ *
+ * @param r RTIO context
+ * @param iodev RTIO IODev to target for the submissions
+ * @param start_addr target register address
+ * @param buf Memory pool that stores the retrieved data.
+ * @param num_bytes Number of bytes to read.
+ *
+ * @retval sqe Last submission in the queue added
+ * @retval NULL Not enough memory in the context to copy the requests
+ */
+struct rtio_sqe *i2c_rtio_copy_reg_burst_read(struct rtio *r, struct rtio_iodev *iodev,
+					      uint8_t start_addr, void *buf, size_t num_bytes);
+
 #endif /* CONFIG_I2C_RTIO */
 
 /**
diff --git a/include/zephyr/drivers/i3c.h b/include/zephyr/drivers/i3c.h
index a80d1830340..5d48a360999 100644
--- a/include/zephyr/drivers/i3c.h
+++ b/include/zephyr/drivers/i3c.h
@@ -503,6 +503,7 @@ struct i3c_device_desc;
 struct i3c_device_id;
 struct i3c_i2c_device_desc;
 struct i3c_target_config;
+struct i3c_config_target;
 
 __subsystem struct i3c_driver_api {
 	/**
@@ -545,7 +546,7 @@ __subsystem struct i3c_driver_api {
 	 */
 	int (*config_get)(const struct device *dev,
 			  enum i3c_config_type type, void *config);
-
+#if defined(CONFIG_I3C_CONTROLLER) || defined(__DOXYGEN__)
 	/**
 	 * Perform bus recovery
 	 *
@@ -572,7 +573,7 @@ __subsystem struct i3c_driver_api {
 	 * @return See i3c_attach_i3c_device()
 	 */
 	int (*attach_i3c_device)(const struct device *dev,
-			struct i3c_device_desc *target);
+				 struct i3c_device_desc *target);
 
 	/**
 	 * I3C Address Update
@@ -588,8 +589,8 @@ __subsystem struct i3c_driver_api {
 	 * @return See i3c_reattach_i3c_device()
 	 */
 	int (*reattach_i3c_device)(const struct device *dev,
-			struct i3c_device_desc *target,
-			uint8_t old_dyn_addr);
+				   struct i3c_device_desc *target,
+				   uint8_t old_dyn_addr);
 
 	/**
 	 * I3C Device Detach
@@ -604,7 +605,7 @@ __subsystem struct i3c_driver_api {
 	 * @return See i3c_detach_i3c_device()
 	 */
 	int (*detach_i3c_device)(const struct device *dev,
-			struct i3c_device_desc *target);
+				 struct i3c_device_desc *target);
 
 	/**
 	 * I2C Device Attach
@@ -619,7 +620,7 @@ __subsystem struct i3c_driver_api {
 	 * @return See i3c_attach_i2c_device()
 	 */
 	int (*attach_i2c_device)(const struct device *dev,
-			struct i3c_i2c_device_desc *target);
+				 struct i3c_i2c_device_desc *target);
 
 	/**
 	 * I2C Device Detach
@@ -634,7 +635,7 @@ __subsystem struct i3c_driver_api {
 	 * @return See i3c_detach_i2c_device()
 	 */
 	int (*detach_i2c_device)(const struct device *dev,
-			struct i3c_i2c_device_desc *target);
+				 struct i3c_i2c_device_desc *target);
 
 	/**
 	 * Perform Dynamic Address Assignment via ENTDAA.
@@ -696,20 +697,9 @@ __subsystem struct i3c_driver_api {
 	 */
 	struct i3c_device_desc *(*i3c_device_find)(const struct device *dev,
 						   const struct i3c_device_id *id);
-
-	/**
-	 * ACK or NACK IBI HJ Requests
-	 *
-	 * @see ibi_hj_response()
-	 *
-	 * @param dev Pointer to controller device driver instance.
-	 * @param ack True to ack, False to nack
-	 *
-	 * @return See ibi_hj_response()
-	 */
-	int (*ibi_hj_response)(const struct device *dev,
-			       bool ack);
-
+#endif /* CONFIG_I3C_CONTROLLER */
+#ifdef CONFIG_I3C_USE_IBI
+#if defined(CONFIG_I3C_TARGET) || defined(__DOXYGEN__)
 	/**
 	 * Raise In-Band Interrupt (IBI).
 	 *
@@ -724,6 +714,20 @@ __subsystem struct i3c_driver_api {
 	 */
 	int (*ibi_raise)(const struct device *dev,
 			 struct i3c_ibi *request);
+#endif /* CONFIG_I3C_TARGET */
+#if defined(CONFIG_I3C_CONTROLLER) || defined(__DOXYGEN__)
+	/**
+	 * ACK or NACK IBI HJ Requests
+	 *
+	 * @see ibi_hj_response()
+	 *
+	 * @param dev Pointer to controller device driver instance.
+	 * @param ack True to ack, False to nack
+	 *
+	 * @return See ibi_hj_response()
+	 */
+	int (*ibi_hj_response)(const struct device *dev,
+			       bool ack);
 
 	/**
 	 * Enable receiving IBI from a target.
@@ -754,7 +758,9 @@ __subsystem struct i3c_driver_api {
 	 */
 	int (*ibi_disable)(const struct device *dev,
 			   struct i3c_device_desc *target);
-
+#endif /* CONFIG_I3C_CONTROLLER */
+#endif /* CONFIG_I3C_USE_IBI */
+#if defined(CONFIG_I3C_TARGET) || defined(__DOXYGEN__)
 	/**
 	 * Register config as target device of a controller.
 	 *
@@ -808,9 +814,27 @@ __subsystem struct i3c_driver_api {
 	 * @return See i3c_target_tx_write()
 	 */
 	int (*target_tx_write)(const struct device *dev,
-				 uint8_t *buf, uint16_t len, uint8_t hdr_mode);
+			       uint8_t *buf, uint16_t len, uint8_t hdr_mode);
 
-#ifdef CONFIG_I3C_RTIO
+	/**
+	 * ACK or NACK controller handoffs
+	 *
+	 * This will tell the target to ACK or NACK controller handoffs
+	 * from the CCC GETACCCR
+	 *
+	 * Target device only API.
+	 *
+	 * @see i3c_target_controller_handoff()
+	 *
+	 * @param dev Pointer to the controller device driver instance.
+	 * @param accept True to ACK controller handoffs, False to NACK.
+	 *
+	 * @return See i3c_target_controller_handoff()
+	 */
+	int (*target_controller_handoff)(const struct device *dev,
+					 bool accept);
+#endif /* CONFIG_I3C_TARGET */
+#if defined(CONFIG_I3C_RTIO) || defined(__DOXYGEN__)
 	/**
 	 * RTIO
 	 *
@@ -822,8 +846,8 @@ __subsystem struct i3c_driver_api {
 	 * @return See i3c_iodev_submit()
 	 */
 	void (*iodev_submit)(const struct device *dev,
-				 struct rtio_iodev_sqe *iodev_sqe);
-#endif
+			     struct rtio_iodev_sqe *iodev_sqe);
+#endif /* CONFIG_I3C_RTIO */
 };
 
 /**
@@ -835,7 +859,7 @@ __subsystem struct i3c_driver_api {
  */
 struct i3c_device_id {
 	/** Device Provisioned ID */
-	const uint64_t pid:48;
+	uint64_t pid:48;
 };
 
 /**
@@ -871,13 +895,13 @@ struct i3c_device_desc {
 	sys_snode_t node;
 
 	/** I3C bus to which this target device is attached */
-	const struct device * const bus;
+	const struct device *bus;
 
 	/** Device driver instance of the I3C device */
-	const struct device * const dev;
+	const struct device *dev;
 
 	/** Device Provisioned ID */
-	const uint64_t pid:48;
+	uint64_t pid;
 
 	/**
 	 * Static address for this target device.
@@ -891,7 +915,7 @@ struct i3c_device_desc {
 	 * device (as both are to tell target device to use static
 	 * address as dynamic address).
 	 */
-	const uint8_t static_addr;
+	uint8_t static_addr;
 
 	/**
 	 * Initial dynamic address.
@@ -905,12 +929,13 @@ struct i3c_device_desc {
 	const uint8_t init_dynamic_addr;
 
 	/**
-	 * Device support for SETAASA
+	 * Device Flags
 	 *
-	 * This will be used as an optimization for bus initializtion if the
+	 * BIT[0]: This shall be used as an optimization for bus initializtion if the
 	 * device supports SETAASA.
+	 * BIT[1]: This shall be used to indicate if the device is a I3C v1.0 device
 	 */
-	const bool supports_setaasa;
+	const uint8_t flags;
 
 	/**
 	 * Dynamic Address for this target device used for communication.
@@ -927,18 +952,6 @@ struct i3c_device_desc {
 	 */
 	uint8_t dynamic_addr;
 
-#if defined(CONFIG_I3C_USE_GROUP_ADDR) || defined(__DOXYGEN__)
-	/**
-	 * Group address for this target device. Set during:
-	 * - Reset Group Address(es) (RSTGRPA)
-	 * - Set Group Address (SETGRPA)
-	 *
-	 * 0 if group address has not been assigned.
-	 * Only available if @kconfig{CONFIG_I3C_USE_GROUP_ADDR} is set.
-	 */
-	uint8_t group_addr;
-#endif /* CONFIG_I3C_USE_GROUP_ADDR */
-
 	/**
 	 * Bus Characteristic Register (BCR)
 	 * @see @ref I3C_BCR
@@ -975,6 +988,9 @@ struct i3c_device_desc {
 		uint8_t max_ibi;
 	} data_length;
 
+	/** Controller Handoff Delay Parameters */
+	uint8_t crhdly1;
+
 	/** Describes advanced (Target) capabilities and features */
 	struct {
 		union {
@@ -1027,6 +1043,28 @@ struct i3c_device_desc {
 		uint8_t getcap4;
 	} getcaps;
 
+	/* Describes Controller Feature Capabilities */
+	struct {
+		/**
+		 * CRCAPS1
+		 * - Bit[0]: Hot-Join Support
+		 * - Bit[1]: Group Management Support
+		 * - Bit[2]: Multi-Lane Support
+		 * - Bit[7:3]: Reserved
+		 */
+		uint8_t crcaps1;
+
+		/**
+		 * CRCAPS2
+		 * - Bit[0]: In-Band Interrupt Support
+		 * - Bit[1]: Controller Pass-Back
+		 * - Bit[2]: Deep Sleep Capable
+		 * - Bit[3]: Delayed Controller Handoff
+		 * - Bit[7:4]: Reserved
+		 */
+		uint8_t crcaps2;
+	} crcaps;
+
 	/** @cond INTERNAL_HIDDEN */
 	/**
 	 * Private data by the controller to aid in transactions. Do not modify.
@@ -1063,13 +1101,13 @@ struct i3c_i2c_device_desc {
 	const struct device *bus;
 
 	/** Static address for this I2C device. */
-	const uint16_t addr;
+	uint16_t addr;
 
 	/**
 	 * Legacy Virtual Register (LVR)
 	 * @see @ref I3C_LVR
 	 */
-	const uint8_t lvr;
+	uint8_t lvr;
 
 	/** @cond INTERNAL_HIDDEN */
 	/**
@@ -1145,10 +1183,22 @@ struct i3c_dev_list {
  * in the device structure.
  */
 struct i3c_driver_config {
+#if defined(CONFIG_I3C_CONTROLLER) || defined(__DOXYGEN__)
 	/** I3C/I2C device list struct. */
 	struct i3c_dev_list dev_list;
+
+	/** I3C Primary Controller Dynamic Address */
+	uint8_t primary_controller_da;
+#elif defined(CONFIG_CPP)
+       /* Empty struct has size 0 in C, size 1 in C++. Force them to be the same. */
+	uint8_t unused_cpp_size_compatibility;
+#endif
 };
 
+#if defined(CONFIG_CPP)
+BUILD_ASSERT(sizeof(struct i3c_driver_config) >= 1);
+#endif
+
 /**
  * This structure is common to all I3C drivers and is expected to be the first
  * element in the driver's struct driver_data declaration.
@@ -1156,11 +1206,19 @@ struct i3c_driver_config {
 struct i3c_driver_data {
 	/** Controller Configuration */
 	struct i3c_config_controller ctrl_config;
-
+#if defined(CONFIG_I3C_CONTROLLER) || defined(__DOXYGEN__)
 	/** Attached I3C/I2C devices and addresses */
 	struct i3c_dev_attached_list attached_dev;
+#if defined(CONFIG_I3C_TARGET) || defined(__DOXYGEN__)
+	/** Received DEFTGTS Pointer */
+	struct i3c_ccc_deftgts *deftgts;
+
+	/** DEFTGTS refreshed */
+	bool deftgts_refreshed;
+#endif /* CONFIG_I3C_TARGET */
+#endif /* CONFIG_I3C_CONTROLLER */
 };
-
+#if defined(CONFIG_I3C_CONTROLLER) || defined(__DOXYGEN__)
 /**
  * @brief iterate over all I3C devices present on the bus
  *
@@ -1213,6 +1271,21 @@ struct i3c_device_desc *i3c_dev_list_find(const struct i3c_dev_list *dev_list,
 struct i3c_device_desc *i3c_dev_list_i3c_addr_find(const struct device *dev,
 						   uint8_t addr);
 
+/**
+ * @brief Find a I3C target device descriptor by static address.
+ *
+ * This finds the I3C target device descriptor in the attached
+ * device list matching the static address (@p addr)
+ *
+ * @param dev Pointer to controller device driver instance.
+ * @param addr static address to be matched.
+ *
+ * @return Pointer to the I3C target device descriptor, or
+ *         `NULL` if none is found.
+ */
+struct i3c_device_desc *i3c_dev_list_i3c_static_addr_find(const struct device *dev,
+							  uint8_t addr);
+
 /**
  * @brief Find a I2C target device descriptor by address.
  *
@@ -1226,7 +1299,7 @@ struct i3c_device_desc *i3c_dev_list_i3c_addr_find(const struct device *dev,
  *         `NULL` if none is found.
  */
 struct i3c_i2c_device_desc *i3c_dev_list_i2c_addr_find(const struct device *dev,
-							   uint16_t addr);
+						       uint16_t addr);
 
 /**
  * @brief Helper function to find a usable address during ENTDAA.
@@ -1285,7 +1358,7 @@ int i3c_dev_list_daa_addr_helper(struct i3c_addr_slots *addr_slots,
 				 bool assigned_okay,
 				 struct i3c_device_desc **target,
 				 uint8_t *addr);
-
+#endif /* CONFIG_I3C_CONTROLLER */
 /**
  * @brief Configure the I3C hardware.
  *
@@ -1311,7 +1384,50 @@ static inline int i3c_configure(const struct device *dev,
 
 	return api->configure(dev, type, config);
 }
-
+#if defined(CONFIG_I3C_CONTROLLER) || defined(__DOXYGEN__)
+/**
+ * @brief Get the controller device configuration for an I3C device.
+ *
+ * This function retrieves the configuration parameters specific to an
+ * I3C controller device. It is a type-safe wrapper around @ref i3c_config_get
+ * that ensures the correct structure type is passed.
+ *
+ * @param dev Pointer to the I3C controller device instance.
+ * @param config Pointer to a @ref i3c_config_controller structure
+ *               where the configuration will be stored.
+ *
+ * @retval 0 If successful.
+ * @retval -EIO General Input/Output errors.
+ * @retval -ENOSYS If not implemented.
+ */
+static inline int i3c_configure_controller(const struct device *dev,
+					   struct i3c_config_controller *config)
+{
+	return i3c_configure(dev, I3C_CONFIG_CONTROLLER, config);
+}
+#endif /* CONFIG_I3C_CONTROLLER */
+#if defined(CONFIG_I3C_TARGET) || defined(__DOXYGEN__)
+/**
+ * @brief Get the target device configuration for an I3C device.
+ *
+ * This function retrieves the configuration parameters specific to an
+ * I3C target device. It is a type-safe wrapper around @ref i3c_config_get
+ * that ensures the correct structure type is passed.
+ *
+ * @param dev Pointer to the I3C controller device instance.
+ * @param config Pointer to a @ref i3c_config_target structure
+ *                    where the configuration will be stored.
+ *
+ * @retval 0 If successful.
+ * @retval -EIO General Input/Output errors.
+ * @retval -ENOSYS If not implemented.
+ */
+static inline int i3c_configure_target(const struct device *dev,
+				       struct i3c_config_target *config)
+{
+	return i3c_configure(dev, I3C_CONFIG_TARGET, config);
+}
+#endif /* CONFIG_I3C_TARGET */
 /**
  * @brief Get configuration of the I3C hardware.
  *
@@ -1344,7 +1460,51 @@ static inline int i3c_config_get(const struct device *dev,
 
 	return api->config_get(dev, type, config);
 }
-
+#if defined(CONFIG_I3C_CONTROLLER) || defined(__DOXYGEN__)
+/**
+ * @brief Get the controller device configuration for an I3C device.
+ *
+ * This function sets the configuration parameters specific to an
+ * I3C controller device. It is a type-safe wrapper around @ref i3c_config_get
+ * that ensures the correct structure type is passed.
+ *
+ * @param[in] dev Pointer to the I3C controller device instance.
+ * @param[out] config Pointer to a @ref i3c_config_controller structure
+ *                    where the configuration will be used.
+ *
+ * @retval 0 If successful.
+ * @retval -EIO General Input/Output errors.
+ * @retval -ENOSYS If not implemented.
+ */
+static inline int i3c_config_get_controller(const struct device *dev,
+					    struct i3c_config_controller *config)
+{
+	return i3c_config_get(dev, I3C_CONFIG_CONTROLLER, config);
+}
+#endif /* CONFIG_I3C_CONTROLLER */
+#if defined(CONFIG_I3C_TARGET) || defined(__DOXYGEN__)
+/**
+ * @brief Get the target device configuration for an I3C device.
+ *
+ * This function sets the configuration parameters specific to an
+ * I3C target device. It is a type-safe wrapper around @ref i3c_config_get
+ * that ensures the correct structure type is passed.
+ *
+ * @param[in] dev Pointer to the I3C controller device instance.
+ * @param[out] config Pointer to a @ref i3c_config_target structure
+ *                    where the configuration will be used.
+ *
+ * @retval 0 If successful.
+ * @retval -EIO General Input/Output errors.
+ * @retval -ENOSYS If not implemented.
+ */
+static inline int i3c_config_get_target(const struct device *dev,
+					struct i3c_config_target *config)
+{
+	return i3c_config_get(dev, I3C_CONFIG_TARGET, config);
+}
+#endif /* CONFIG_I3C_TARGET */
+#if defined(CONFIG_I3C_CONTROLLER) || defined(__DOXYGEN__)
 /**
  * @brief Attempt bus recovery on the I3C bus.
  *
@@ -1610,12 +1770,14 @@ struct i3c_device_desc *i3c_device_find(const struct device *dev,
 
 	return api->i3c_device_find(dev, id);
 }
-
+#endif /* CONFIG_I3C_CONTROLLER */
+#if defined(CONFIG_I3C_USE_IBI) || defined(__DOXYGEN__)
 /**
  * @addtogroup i3c_ibi
  * @{
  */
 
+#if defined(CONFIG_I3C_CONTROLLER) || defined(__DOXYGEN__)
 /**
  * @brief ACK or NACK IBI HJ Requests
  *
@@ -1640,7 +1802,8 @@ static inline int i3c_ibi_hj_response(const struct device *dev,
 
 	return api->ibi_hj_response(dev, ack);
 }
-
+#endif /* CONFIG_I3C_CONTROLLER */
+#if defined(CONFIG_I3C_TARGET) || defined(__DOXYGEN__)
 /**
  * @brief Raise an In-Band Interrupt (IBI).
  *
@@ -1664,7 +1827,8 @@ static inline int i3c_ibi_raise(const struct device *dev,
 
 	return api->ibi_raise(dev, request);
 }
-
+#endif /* CONFIG_I3C_TARGET */
+#if defined(CONFIG_I3C_CONTROLLER) || defined(__DOXYGEN__)
 /**
  * @brief Enable IBI of a target device.
  *
@@ -1714,7 +1878,8 @@ static inline int i3c_ibi_disable(struct i3c_device_desc *target)
 
 	return api->ibi_disable(target->bus, target);
 }
-
+#endif /* CONFIG_I3C_CONTROLLER */
+#endif /* CONFIG_I3C_USE_IBI */
 /**
  * @brief Check if target's IBI has payload.
  *
@@ -1767,7 +1932,7 @@ static inline int i3c_device_is_controller_capable(struct i3c_device_desc *targe
 }
 
 /** @} */
-
+#if defined(CONFIG_I3C_CONTROLLER) || defined(__DOXYGEN__)
 /**
  * @addtogroup i3c_transfer_api
  * @{
@@ -2167,6 +2332,157 @@ bool i3c_bus_has_sec_controller(const struct device *dev);
  */
 int i3c_bus_deftgts(const struct device *dev);
 
+/**
+ * @brief Calculate odd parity
+ *
+ * Calculate the Odd Parity of a Target Address.
+ *
+ * @param p The 7b target dynamic address
+ *
+ * @return The odd parity bit
+ */
+uint8_t i3c_odd_parity(uint8_t p);
+
+/**
+ * @brief Perform Controller Handoff
+ *
+ * This performs the controller handoff according to 5.1.7.1 of
+ * I3C v1.1.1 Specification.
+ *
+ * @param target I3C target device descriptor.
+ * @param requested True if the target requested the Handoff, False if
+ * the active controller is passing it to a secondary controller
+ *
+ * @retval 0 if successful.
+ * @retval -EIO General Input/Output error.
+ * @retval -EBUSY Target cannot accept Controller Handoff
+ */
+int i3c_device_controller_handoff(const struct i3c_device_desc *target, bool requested);
+#endif /* CONFIG_I3C_CONTROLLER */
+
+#if defined(CONFIG_I3C_USE_IBI) || defined(__DOXYGEN__)
+#if (defined(CONFIG_I3C_CONTROLLER) && defined(CONFIG_I3C_TARGET)) || defined(__DOXYGEN__)
+/**
+ * @brief Call back for when Controllership is Handoffed to itself
+ *
+ * This reads the DEFTGTS it received earlier and processes it by reading
+ * the PIDs of all the devices with GETPID and then matching it with known
+ * PIDS. If it does not match, then it will attempt to grab a mem slab
+ * for i3c_device_desc. It will then obtain the standard I3C information
+ * from the device.
+ *
+ * @param work pointer to the work item.
+ */
+void i3c_sec_handoffed(struct k_work *work);
+#endif /* CONFIG_I3C_CONTROLLER && CONFIG_I3C_TARGET */
+#endif /* CONFIG_I3C_USE_IBI */
+
+#if (defined(CONFIG_I3C_NUM_OF_DESC_MEM_SLABS) && CONFIG_I3C_NUM_OF_DESC_MEM_SLABS > 0) ||         \
+	defined(__DOXYGEN__)
+
+/**
+ * @brief Allocate memory for a i3c device descriptor
+ *
+ * This allocates memory from a mem slab for a i3c_device_desc
+ *
+ * @retval Pointer to allocated i3c_device_desc
+ * @retval NULL if no mem slabs available
+ */
+struct i3c_device_desc *i3c_device_desc_alloc(void);
+
+/**
+ * @brief Free memory from a i3c device descriptor
+ *
+ * This frees memory from a mem slab of a i3c_device_desc
+ *
+ * @param desc Pointer to allocated i3c_device_desc
+ */
+void i3c_device_desc_free(struct i3c_device_desc *desc);
+
+/**
+ * @brief Report if the i3c device descriptor was from a mem slab
+ *
+ * This reports if the i3c_device_desc was from a memory slab
+ *
+ * @param desc Pointer to a i3c_device_desc
+ *
+ * @return True if from a memory slab, False if not
+ */
+bool i3c_device_desc_in_pool(struct i3c_device_desc *desc);
+
+#else
+
+static inline struct i3c_device_desc *i3c_device_desc_alloc(void)
+{
+	return NULL;
+}
+
+static inline void i3c_device_desc_free(struct i3c_device_desc *desc)
+{
+	ARG_UNUSED(desc);
+}
+
+static inline bool i3c_device_desc_in_pool(struct i3c_device_desc *desc)
+{
+	ARG_UNUSED(desc);
+	return false;
+}
+
+#endif /* CONFIG_I3C_NUM_OF_DESC_MEM_SLABS > 0 */
+
+#if (defined(CONFIG_I3C_I2C_NUM_OF_DESC_MEM_SLABS) && CONFIG_I3C_I2C_NUM_OF_DESC_MEM_SLABS > 0) || \
+	defined(__DOXYGEN__)
+
+/**
+ * @brief Allocate memory for a i3c i2c device descriptor
+ *
+ * This allocates memory from a mem slab for a i3c_i2c_device_desc
+ *
+ * @return Pointer to allocated i3c_i2c_device_desc, NULL if none
+ *         available
+ */
+struct i3c_i2c_device_desc *i3c_i2c_device_desc_alloc(void);
+
+/**
+ * @brief Free memory from a i3c i2c device descriptor
+ *
+ * This frees memory from a mem slab of a i3c_i2c_device_desc
+ *
+ * @param desc Pointer to allocated i3c_i2c_device_desc
+ */
+void i3c_i2c_device_desc_free(struct i3c_i2c_device_desc *desc);
+
+/**
+ * @brief Report if the i3c i2c device descriptor was from a mem slab
+ *
+ * This reports if the i3c_i2c_device_desc was from a memory slab
+ *
+ * @param desc Pointer to a i3c_i2c_device_desc
+ *
+ * @return True if from a memory slab, False if not
+ */
+bool i3c_i2c_device_desc_in_pool(struct i3c_i2c_device_desc *desc);
+
+#else
+
+static inline struct i3c_i2c_device_desc *i3c_i2c_device_desc_alloc(void)
+{
+	return NULL;
+}
+
+static inline void i3c_i2c_device_desc_free(struct i3c_i2c_device_desc *desc)
+{
+	ARG_UNUSED(desc);
+}
+
+static inline bool i3c_i2c_device_desc_in_pool(struct i3c_i2c_device_desc *desc)
+{
+	ARG_UNUSED(desc);
+	return false;
+}
+
+#endif /* CONFIG_I3C_I2C_NUM_OF_DESC_MEM_SLABS > 0 */
+
 #if defined(CONFIG_I3C_RTIO) || defined(__DOXYGEN__)
 
 struct i3c_iodev_data {
@@ -2241,17 +2557,21 @@ struct rtio_sqe *i3c_rtio_copy(struct rtio *r,
 
 #endif /* CONFIG_I3C_RTIO */
 
+#if defined(CONFIG_I3C_TARGET) || defined(__DOXYGEN__)
 /*
  * This needs to be after declaration of struct i3c_driver_api,
  * or else compiler complains about undefined type inside
  * the static inline API wrappers.
  */
 #include <zephyr/drivers/i3c/target_device.h>
+#endif /* CONFIG_I3C_TARGET */
 
+#if defined(CONFIG_I3C_CONTROLLER) || defined(__DOXYGEN__)
 /*
  * Include High-Data-Rate (HDR) inline helper functions
  */
 #include <zephyr/drivers/i3c/hdr_ddr.h>
+#endif /* CONFIG_I3C_CONTROLLER */
 
 #ifdef __cplusplus
 }
diff --git a/include/zephyr/drivers/i3c/ccc.h b/include/zephyr/drivers/i3c/ccc.h
index 4318896a269..651930e7442 100644
--- a/include/zephyr/drivers/i3c/ccc.h
+++ b/include/zephyr/drivers/i3c/ccc.h
@@ -179,6 +179,14 @@ extern "C" {
  */
 #define I3C_CCC_VENDOR(broadcast, id)		((id) + ((broadcast) ? 0x61U : 0xE0U))
 
+/**
+ * Reset Dynamic Address (Direct)
+ *
+ * @note This should not be used by devices that support I3C v1.0 and this
+ * shall not be used for devices that support I3C v1.1 or later.
+ */
+#define I3C_CCC_RSTDAA_DC			0x86U
+
 /** Set Dynamic Address from Static Address (Direct) */
 #define I3C_CCC_SETDASA				0x87U
 
@@ -515,7 +523,7 @@ struct i3c_ccc_address {
 	 * @note For SETDATA, SETNEWDA and SETGRPA,
 	 * the address is left-shift by 1, and bit[0] is always 0.
 	 *
-	 * @note Fpr SET GETACCCR, the address is left-shift by 1,
+	 * @note For SET GETACCCR, the address is left-shift by 1,
 	 * and bit[0] is the calculated odd parity bit.
 	 */
 	uint8_t addr;
@@ -639,6 +647,9 @@ union i3c_ccc_getstatus {
 #define I3C_CCC_GETSTATUS_ACTIVITY_MODE(status)			\
 	FIELD_GET(I3C_CCC_GETSTATUS_ACTIVITY_MODE_MASK, (status))
 
+/** GETSTATUS Format 1 - Activity Mode Unable to participate in Controller Handoff */
+#define I3C_CCC_GETSTATUS_ACTIVITY_MODE_NCH			0x3
+
 /** GETSTATUS Format 1 - Number of Pending Interrupts bitmask. */
 #define I3C_CCC_GETSTATUS_NUM_INT_MASK				GENMASK(3U, 0U)
 
@@ -869,7 +880,7 @@ union i3c_ccc_getmxds {
  * @param crhdly1 GETMXDS value.
  */
 #define I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE(crhdly1)	\
-	FIELD_GET(I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_MASK, (chrdly1))
+	FIELD_GET(I3C_CCC_GETMXDS_CRDHLY1_CTRL_HANDOFF_ACT_STATE_MASK, (crhdly1))
 
 /**
  * @brief Indicate which format of GETCAPS to use.
@@ -1499,6 +1510,21 @@ static inline int i3c_ccc_do_rstact_fmt3(const struct i3c_device_desc *target,
 	return i3c_ccc_do_rstact(target, action, true, data);
 }
 
+/**
+ * @brief Reset dynamic addresses for a targets.
+ *
+ * Helper function to reset a dynamic addresses of a targets.
+ *
+ * @note This should not be used by devices that support I3C v1.0 and this
+ * shall not be used for devices that support I3C v1.1 or later.
+ *
+ * @param[in] target Pointer to the target device descriptor where
+ *                   the device is configured with a dynamic address.
+ *
+ * @return @see i3c_do_ccc
+ */
+int i3c_ccc_do_rstdaa(struct i3c_device_desc *target);
+
 /**
  * @brief Broadcast RSTDAA to reset dynamic addresses for all targets.
  *
@@ -1535,7 +1561,7 @@ int i3c_ccc_do_setdasa(const struct i3c_device_desc *target,
  * Note this does not update @p target with the new dynamic address.
  *
  * @param[in] target Pointer to the target device descriptor where
- *                   the device is configured with a static address.
+ *                   the device is configured with a dynamic address.
  * @param[in] new_da Struct of the Dynamic address
  *
  * @return @see i3c_do_ccc
@@ -2135,6 +2161,24 @@ int i3c_ccc_do_deftgts_all(const struct device *controller,
 int i3c_ccc_do_setbuscon(const struct device *controller,
 				uint8_t *context, uint16_t length);
 
+/**
+ * @brief Direct GETACCCR for Controller Handoff
+ *
+ * Helper function to allow for the Active Controller to pass the
+ * Controller Role to a Secondary Controller. The returned address
+ * should match it's dynamic address along with odd parity.
+ *
+ * Note it is up to the caller to verify the correct returned address
+ *
+ * @param[in] target Pointer to the target device descriptor.
+ * @param[out] handoff_address Pointer to the address returned by the secondary
+ * controller.
+ *
+ * @return @see i3c_do_ccc
+ */
+int i3c_ccc_do_getacccr(const struct i3c_device_desc *target,
+			   struct i3c_ccc_address *handoff_address);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/zephyr/drivers/i3c/devicetree.h b/include/zephyr/drivers/i3c/devicetree.h
index 803f17d5517..2ab0749b01e 100644
--- a/include/zephyr/drivers/i3c/devicetree.h
+++ b/include/zephyr/drivers/i3c/devicetree.h
@@ -52,6 +52,19 @@ extern "C" {
 #define I3C_DEVICE_ID_DT_INST(inst)					\
 	I3C_DEVICE_ID_DT(DT_DRV_INST(inst))
 
+/**
+ * @name I3C device flags.
+ * @anchor I3C_DEVICE_FLAGS
+ * @{
+ */
+
+/** Device supports SETAASA CCC */
+#define I3C_SUPPORTS_SETAASA		BIT(0)
+/** Device supports I3C v1.0 */
+#define I3C_V1P0_SUPPORT		BIT(1)
+
+/** @} */
+
 /**
  * @brief Structure initializer for i3c_device_desc from devicetree
  *
@@ -62,16 +75,16 @@ extern "C" {
  * @param node_id Devicetree node identifier for the I3C device whose
  *                struct i3c_device_desc to create an initializer for
  */
-#define I3C_DEVICE_DESC_DT(node_id)					\
-	{								\
-		.bus = DEVICE_DT_GET(DT_BUS(node_id)),			\
-		.dev = DEVICE_DT_GET(node_id),				\
-		.static_addr = DT_PROP_BY_IDX(node_id, reg, 0),		\
-		.pid = ((uint64_t)DT_PROP_BY_IDX(node_id, reg, 1) << 32)\
-		       | DT_PROP_BY_IDX(node_id, reg, 2),		\
-		.init_dynamic_addr =					\
-			DT_PROP_OR(node_id, assigned_address, 0),	\
-		.supports_setaasa = DT_PROP(node_id, supports_setaasa), \
+#define I3C_DEVICE_DESC_DT(node_id)                                                                \
+	{                                                                                          \
+		.bus = DEVICE_DT_GET(DT_BUS(node_id)),                                             \
+		.dev = DEVICE_DT_GET(node_id),                                                     \
+		.static_addr = DT_PROP_BY_IDX(node_id, reg, 0),                                    \
+		.pid = ((uint64_t)DT_PROP_BY_IDX(node_id, reg, 1) << 32) |                         \
+		       DT_PROP_BY_IDX(node_id, reg, 2),                                            \
+		.init_dynamic_addr = DT_PROP_OR(node_id, assigned_address, 0),                     \
+		.flags = FIELD_PREP(I3C_SUPPORTS_SETAASA, DT_PROP(node_id, supports_setaasa)) |    \
+			 FIELD_PREP(I3C_V1P0_SUPPORT, DT_PROP(node_id, v1p0_support)),             \
 	},
 
 /**
diff --git a/include/zephyr/drivers/i3c/hdr_ddr.h b/include/zephyr/drivers/i3c/hdr_ddr.h
index 6aaff610532..ad7f6d38f9f 100644
--- a/include/zephyr/drivers/i3c/hdr_ddr.h
+++ b/include/zephyr/drivers/i3c/hdr_ddr.h
@@ -38,8 +38,8 @@ extern "C" {
  * @retval -EBUSY Bus is busy.
  * @retval -EIO General input / output error.
  */
-static inline int i3c_hdr_ddr_write(struct i3c_device_desc *target, uint8_t cmd,
-				uint8_t *buf, uint32_t num_bytes)
+static inline int i3c_hdr_ddr_write(struct i3c_device_desc *target, uint8_t cmd, uint8_t *buf,
+				    uint32_t num_bytes)
 {
 	struct i3c_msg msg;
 
@@ -66,14 +66,14 @@ static inline int i3c_hdr_ddr_write(struct i3c_device_desc *target, uint8_t cmd,
  * @retval -EBUSY Bus is busy.
  * @retval -EIO General input / output error.
  */
-static inline int i3c_hdr_ddr_read(struct i3c_device_desc *target, uint8_t cmd,
-				uint8_t *buf, uint32_t num_bytes)
+static inline int i3c_hdr_ddr_read(struct i3c_device_desc *target, uint8_t cmd, uint8_t *buf,
+				   uint32_t num_bytes)
 {
 	struct i3c_msg msg;
 
 	msg.buf = buf;
 	msg.len = num_bytes;
-	msg.flags = I3C_MSG_STOP | I3C_MSG_HDR;
+	msg.flags = I3C_MSG_READ | I3C_MSG_STOP | I3C_MSG_HDR;
 	msg.hdr_mode = I3C_MSG_HDR_DDR;
 	msg.hdr_cmd_code = cmd;
 
@@ -90,18 +90,18 @@ static inline int i3c_hdr_ddr_read(struct i3c_device_desc *target, uint8_t cmd,
  * @param target I3C target device descriptor.
  * @param write_buf Pointer to the data to be written
  * @param num_write Number of bytes to write
- * @param write_cmd 7-bit command code for write
+ * @param read_cmd 7-bit command code for read
  * @param read_buf Pointer to storage for read data
  * @param num_read Number of bytes to read
- * @param read_cmd 7-bit command code for read
+ * @param write_cmd 7-bit command code for write
  *
  * @retval 0 if successful
  * @retval -EBUSY Bus is busy.
  * @retval -EIO General input / output error.
  */
-static inline int i3c_hdr_ddr_write_read(struct i3c_device_desc *target,
-				 const void *write_buf, size_t num_write, uint8_t read_cmd,
-				 void *read_buf, size_t num_read, uint8_t write_cmd)
+static inline int i3c_hdr_ddr_write_read(struct i3c_device_desc *target, const void *write_buf,
+					 size_t num_write, uint8_t read_cmd, void *read_buf,
+					 size_t num_read, uint8_t write_cmd)
 {
 	struct i3c_msg msg[2];
 
diff --git a/include/zephyr/drivers/i3c/ibi.h b/include/zephyr/drivers/i3c/ibi.h
index 6020609b500..443d43ecb15 100644
--- a/include/zephyr/drivers/i3c/ibi.h
+++ b/include/zephyr/drivers/i3c/ibi.h
@@ -184,6 +184,21 @@ int i3c_ibi_work_enqueue(struct i3c_ibi_work *ibi_work);
 int i3c_ibi_work_enqueue_target_irq(struct i3c_device_desc *target,
 				    uint8_t *payload, size_t payload_len);
 
+/**
+ * @brief Queue a controllership request IBI for future processing.
+ *
+ * This queues up a controllership request IBI in the IBI workqueue
+ * for future processing.
+ *
+ * @param target Pointer to target device descriptor.
+ *
+ * @retval 0 If work item is successfully queued.
+ * @retval -ENOMEM If no more free internal node to
+ *                 store IBI work item.
+ * @retval Others @see k_work_submit_to_queue
+ */
+int i3c_ibi_work_enqueue_controller_request(struct i3c_device_desc *target);
+
 /**
  * @brief Queue a hot join IBI for future processing.
  *
diff --git a/include/zephyr/drivers/i3c/target_device.h b/include/zephyr/drivers/i3c/target_device.h
index 7d85e03b001..621fc3f6e98 100644
--- a/include/zephyr/drivers/i3c/target_device.h
+++ b/include/zephyr/drivers/i3c/target_device.h
@@ -31,27 +31,30 @@ struct i3c_driver_api;
  * @brief Configuration parameters for I3C hardware to act as target device.
  *
  * This can also be used to configure the controller if it is to act as
- * a secondary controller on the bus.
+ * a target on the bus.
  */
 struct i3c_config_target {
 	/**
-	 * If the hardware is to act as a target device
+	 * If the hardware is currently acting as a target device
 	 * on the bus.
 	 */
-	bool enable;
+	bool enabled;
 
 	/**
 	 * I3C target dynamic address.
 	 *
-	 * Used when operates as secondary controller
-	 * or as a target device.
+	 * Currently assigned dynamic address. 0 if no address
+	 * assigned.
+	 *
+	 * @note Only writeable if the hardware acts as a primary
+	 *       controller
 	 */
 	uint8_t dynamic_addr;
 
 	/**
 	 * I3C target static address.
 	 *
-	 * Used used when operates as secondary controller
+	 * Used used when operating as a secondary controller
 	 * or as a target device.
 	 */
 	uint8_t static_addr;
@@ -81,9 +84,6 @@ struct i3c_config_target {
 
 	/**
 	 * Bit mask of supported HDR modes (0 - 7).
-	 *
-	 * This can be used to enable or disable HDR mode
-	 * supported by the hardware at runtime.
 	 */
 	uint8_t supported_hdr;
 };
@@ -261,6 +261,22 @@ struct i3c_target_callbacks {
 	 * @return Ignored.
 	 */
 	int (*stop_cb)(struct i3c_target_config *config);
+
+	/**
+	 * @brief Function called when an active controller handoffs controlership
+	 * to this target.
+	 *
+	 * This function is invoked by the active controller when it handoffs
+	 * controllership to this target. This can happen wither the target has
+	 * requested it or if the active controller chooses to handoff to the
+	 * controller capable target.
+	 *
+	 * @param config Configuration structure associated with the
+	 *               device to which the operation is addressed.
+	 *
+	 * @return Ignored.
+	 */
+	int (*controller_handoff_cb)(struct i3c_target_config *config);
 };
 
 __subsystem struct i3c_target_driver_api {
@@ -268,6 +284,31 @@ __subsystem struct i3c_target_driver_api {
 	int (*driver_unregister)(const struct device *dev);
 };
 
+/**
+ * @brief Accept or Decline Controller Handoffs
+ *
+ * This sets the target to ACK or NACK handoffs from the active
+ * controller from the CCC GETACCCR.
+ *
+ * @param dev Pointer to the device structure for an I3C controller
+ *            driver configured in target mode.
+ * @param accept True to ACK controller handoffs, False to NACK
+ *
+ * @retval 0 Is successful
+ */
+static inline int i3c_target_controller_handoff(const struct device *dev,
+				      bool accept)
+{
+	const struct i3c_driver_api *api =
+		(const struct i3c_driver_api *)dev->api;
+
+	if (api->target_controller_handoff == NULL) {
+		return -ENOSYS;
+	}
+
+	return api->target_controller_handoff(dev, accept);
+}
+
 /**
  * @brief Writes to the target's TX FIFO
  *
diff --git a/include/zephyr/drivers/interrupt_controller/gic.h b/include/zephyr/drivers/interrupt_controller/gic.h
index ab6aeffe3d2..463aa7203cc 100644
--- a/include/zephyr/drivers/interrupt_controller/gic.h
+++ b/include/zephyr/drivers/interrupt_controller/gic.h
@@ -20,8 +20,8 @@
  * GIC Register Interface Base Addresses
  */
 
-#define GIC_DIST_BASE	DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0)
-#define GIC_CPU_BASE	DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1)
+#define GIC_DIST_BASE DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0)
+#define GIC_CPU_BASE  DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1)
 
 /*
  * GIC Distributor Interface
@@ -32,70 +32,112 @@
  * v1		ICDDCR
  * v2/v3	GICD_CTLR
  */
-#define	GICD_CTLR		(GIC_DIST_BASE +   0x0)
+#define GICD_CTLR (GIC_DIST_BASE + 0x0)
 
 /*
  * 0x004  Interrupt Controller Type Register
  * v1		ICDICTR
  * v2/v3	GICD_TYPER
  */
-#define	GICD_TYPER		(GIC_DIST_BASE +   0x4)
+#define GICD_TYPER (GIC_DIST_BASE + 0x4)
 
 /*
  * 0x008  Distributor Implementer Identification Register
  * v1		ICDIIDR
  * v2/v3	GICD_IIDR
  */
-#define	GICD_IIDR		(GIC_DIST_BASE +   0x8)
+#define GICD_IIDR (GIC_DIST_BASE + 0x8)
 
 /*
  * 0x080  Interrupt Group Registers
  * v1		ICDISRn
  * v2/v3	GICD_IGROUPRn
  */
-#define	GICD_IGROUPRn		(GIC_DIST_BASE +  0x80)
+#define GICD_IGROUPRn (GIC_DIST_BASE + 0x80)
+
+/*
+ * 0x1000  Interrupt Group Registers for Extended SPI Range
+ * v3.1		GICD_IGROUPRnE
+ */
+#define GICD_IGROUPRnE (GIC_DIST_BASE + 0x1000)
 
 /*
  * 0x100  Interrupt Set-Enable Registers
  * v1		ICDISERn
  * v2/v3	GICD_ISENABLERn
  */
-#define	GICD_ISENABLERn		(GIC_DIST_BASE + 0x100)
+#define GICD_ISENABLERn (GIC_DIST_BASE + 0x100)
+
+/*
+ * 0x1200  Interrupt Set-Enable Registers for Extended SPI Range
+ * v3.1		GICD_ISENABLERnE
+ */
+#define GICD_ISENABLERnE (GIC_DIST_BASE + 0x1200)
 
 /*
  * 0x180  Interrupt Clear-Enable Registers
  * v1		ICDICERn
  * v2/v3	GICD_ICENABLERn
  */
-#define	GICD_ICENABLERn		(GIC_DIST_BASE + 0x180)
+#define GICD_ICENABLERn (GIC_DIST_BASE + 0x180)
+
+/*
+ * 0x1400  Interrupt Clear-Enable Registers for Extended SPI Range
+ * v3.1		GICD_ICENABLERnE
+ */
+#define GICD_ICENABLERnE (GIC_DIST_BASE + 0x1400)
 
 /*
  * 0x200  Interrupt Set-Pending Registers
  * v1		ICDISPRn
  * v2/v3	GICD_ISPENDRn
  */
-#define	GICD_ISPENDRn		(GIC_DIST_BASE + 0x200)
+#define GICD_ISPENDRn (GIC_DIST_BASE + 0x200)
+
+/*
+ * 1600  Interrupt Set-Pending Registers for Extended SPI Range
+ * v3.1		GICD_ISPENDRnE
+ */
+#define GICD_ISPENDRnE (GIC_DIST_BASE + 0x1600)
 
 /*
  * 0x280  Interrupt Clear-Pending Registers
  * v1		ICDICPRn
  * v2/v3	GICD_ICPENDRn
  */
-#define	GICD_ICPENDRn		(GIC_DIST_BASE + 0x280)
+#define GICD_ICPENDRn (GIC_DIST_BASE + 0x280)
+
+/*
+ * 0x1800  Interrupt Clear-Pending Registers for Extended SPI Range
+ * v3.1		GICD_ICPENDRnE
+ */
+#define GICD_ICPENDRnE (GIC_DIST_BASE + 0x1800)
 
 /*
  * 0x300  Interrupt Set-Active Registers
  * v1		ICDABRn
  * v2/v3	GICD_ISACTIVERn
  */
-#define	GICD_ISACTIVERn		(GIC_DIST_BASE + 0x300)
+#define GICD_ISACTIVERn (GIC_DIST_BASE + 0x300)
+
+/*
+ * 0x1A00  Interrupt Set-Active Registers for Extended SPI Range
+ * v3.1		GICD_ISACTIVERnE
+ */
+#define GICD_ISACTIVERnE (GIC_DIST_BASE + 0x1A00)
 
 #if CONFIG_GIC_VER >= 2
 /*
  * 0x380  Interrupt Clear-Active Registers
  * v2/v3	GICD_ICACTIVERn
  */
-#define	GICD_ICACTIVERn		(GIC_DIST_BASE + 0x380)
+#define GICD_ICACTIVERn (GIC_DIST_BASE + 0x380)
+
+/*
+ * 0x1C00  Interrupt Clear-Active Registers for Extended SPI Range
+ * v3.1		GICD_ICACTIVERnE
+ */
+#define GICD_ICACTIVERnE (GIC_DIST_BASE + 0x1C00)
 #endif
 
 /*
@@ -103,28 +145,40 @@
  * v1		ICDIPRn
  * v2/v3	GICD_IPRIORITYRn
  */
-#define	GICD_IPRIORITYRn	(GIC_DIST_BASE + 0x400)
+#define GICD_IPRIORITYRn (GIC_DIST_BASE + 0x400)
+
+/*
+ * 0x2000  Interrupt Priority Registers for Extended SPI Range
+ * v3.1		GICD_IPRIORITYRnE
+ */
+#define GICD_IPRIORITYRnE (GIC_DIST_BASE + 0x2000)
 
 /*
  * 0x800  Interrupt Processor Targets Registers
  * v1		ICDIPTRn
  * v2/v3	GICD_ITARGETSRn
  */
-#define	GICD_ITARGETSRn		(GIC_DIST_BASE + 0x800)
+#define GICD_ITARGETSRn (GIC_DIST_BASE + 0x800)
 
 /*
  * 0xC00  Interrupt Configuration Registers
  * v1		ICDICRn
  * v2/v3	GICD_ICFGRn
  */
-#define	GICD_ICFGRn		(GIC_DIST_BASE + 0xc00)
+#define GICD_ICFGRn (GIC_DIST_BASE + 0xc00)
+
+/*
+ * 0x3000  Interrupt Configuration Registers for Extended SPI Range
+ * v3.1		GICD_ICFGRnE
+ */
+#define GICD_ICFGRnE (GIC_DIST_BASE + 0x3000)
 
 /*
  * 0xF00  Software Generated Interrupt Register
  * v1		ICDSGIR
  * v2/v3	GICD_SGIR
  */
-#define	GICD_SGIR		(GIC_DIST_BASE + 0xf00)
+#define GICD_SGIR (GIC_DIST_BASE + 0xf00)
 
 /*
  * GIC CPU Interface
@@ -137,116 +191,113 @@
  * v1		ICCICR
  * v2/v3	GICC_CTLR
  */
-#define GICC_CTLR		(GIC_CPU_BASE +    0x0)
+#define GICC_CTLR (GIC_CPU_BASE + 0x0)
 
 /*
  * 0x0004  Interrupt Priority Mask Register
  * v1		ICCPMR
  * v2/v3	GICC_PMR
  */
-#define GICC_PMR		(GIC_CPU_BASE +    0x4)
+#define GICC_PMR (GIC_CPU_BASE + 0x4)
 
 /*
  * 0x0008  Binary Point Register
  * v1		ICCBPR
  * v2/v3	GICC_BPR
  */
-#define GICC_BPR		(GIC_CPU_BASE +    0x8)
+#define GICC_BPR (GIC_CPU_BASE + 0x8)
 
 /*
  * 0x000C  Interrupt Acknowledge Register
  * v1		ICCIAR
  * v2/v3	GICC_IAR
  */
-#define GICC_IAR		(GIC_CPU_BASE +    0xc)
+#define GICC_IAR (GIC_CPU_BASE + 0xc)
 
 /*
  * 0x0010  End of Interrupt Register
  * v1		ICCEOIR
  * v2/v3	GICC_EOIR
  */
-#define GICC_EOIR		(GIC_CPU_BASE +   0x10)
-
+#define GICC_EOIR (GIC_CPU_BASE + 0x10)
 
 /*
  * Helper Constants
  */
 
 /* GICC_CTLR */
-#define GICC_CTLR_ENABLEGRP0	BIT(0)
-#define GICC_CTLR_ENABLEGRP1	BIT(1)
+#define GICC_CTLR_ENABLEGRP0 BIT(0)
+#define GICC_CTLR_ENABLEGRP1 BIT(1)
 
-#define GICC_CTLR_ENABLE_MASK	(GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1)
+#define GICC_CTLR_ENABLE_MASK (GICC_CTLR_ENABLEGRP0 | GICC_CTLR_ENABLEGRP1)
 
 #if defined(CONFIG_GIC_V2)
 
-#define GICC_CTLR_FIQBYPDISGRP0	BIT(5)
-#define GICC_CTLR_IRQBYPDISGRP0	BIT(6)
-#define GICC_CTLR_FIQBYPDISGRP1	BIT(7)
-#define GICC_CTLR_IRQBYPDISGRP1	BIT(8)
+#define GICC_CTLR_FIQBYPDISGRP0 BIT(5)
+#define GICC_CTLR_IRQBYPDISGRP0 BIT(6)
+#define GICC_CTLR_FIQBYPDISGRP1 BIT(7)
+#define GICC_CTLR_IRQBYPDISGRP1 BIT(8)
 
-#define GICC_CTLR_BYPASS_MASK	(GICC_CTLR_FIQBYPDISGRP0 | \
-				 GICC_CTLR_IRQBYPDISGRP1 | \
-				 GICC_CTLR_FIQBYPDISGRP1 | \
-				 GICC_CTLR_IRQBYPDISGRP1)
+#define GICC_CTLR_BYPASS_MASK                                                                      \
+	(GICC_CTLR_FIQBYPDISGRP0 | GICC_CTLR_IRQBYPDISGRP1 | GICC_CTLR_FIQBYPDISGRP1 |             \
+	 GICC_CTLR_IRQBYPDISGRP1)
 
 #endif /* CONFIG_GIC_V2 */
 
 /* GICD_SGIR */
-#define GICD_SGIR_TGTFILT(x)		((x) << 24)
-#define GICD_SGIR_TGTFILT_CPULIST	GICD_SGIR_TGTFILT(0b00)
-#define GICD_SGIR_TGTFILT_ALLBUTREQ	GICD_SGIR_TGTFILT(0b01)
-#define GICD_SGIR_TGTFILT_REQONLY	GICD_SGIR_TGTFILT(0b10)
+#define GICD_SGIR_TGTFILT(x)        ((x) << 24)
+#define GICD_SGIR_TGTFILT_CPULIST   GICD_SGIR_TGTFILT(0b00)
+#define GICD_SGIR_TGTFILT_ALLBUTREQ GICD_SGIR_TGTFILT(0b01)
+#define GICD_SGIR_TGTFILT_REQONLY   GICD_SGIR_TGTFILT(0b10)
 
-#define GICD_SGIR_CPULIST(x)		((x) << 16)
-#define GICD_SGIR_CPULIST_CPU(n)	GICD_SGIR_CPULIST(BIT(n))
-#define GICD_SGIR_CPULIST_MASK		0xff
+#define GICD_SGIR_CPULIST(x)     ((x) << 16)
+#define GICD_SGIR_CPULIST_CPU(n) GICD_SGIR_CPULIST(BIT(n))
+#define GICD_SGIR_CPULIST_MASK   0xff
 
-#define GICD_SGIR_NSATT			BIT(15)
+#define GICD_SGIR_NSATT BIT(15)
 
-#define GICD_SGIR_SGIINTID(x)		(x)
+#define GICD_SGIR_SGIINTID(x) (x)
 
 #endif /* CONFIG_GIC_VER <= 2 */
 
-
 /* GICD_ICFGR */
-#define GICD_ICFGR_MASK			BIT_MASK(2)
-#define GICD_ICFGR_TYPE			BIT(1)
+#define GICD_ICFGR_MASK BIT_MASK(2)
+#define GICD_ICFGR_TYPE BIT(1)
 
 /* GICD_TYPER.ITLinesNumber 0:4 */
-#define GICD_TYPER_ITLINESNUM_MASK	0x1f
+#define GICD_TYPER_ITLINESNUM_MASK 0x1f
+
+/* GICD_TYPER.ESPI [8] */
+#define GICD_TYPER_ESPI_MASK BIT(8)
 
 /* GICD_TYPER.IDbits */
-#define GICD_TYPER_IDBITS(typer)	((((typer) >> 19) & 0x1f) + 1)
+#define GICD_TYPER_IDBITS(typer) ((((typer) >> 19) & 0x1f) + 1)
 
 /*
  * Common Helper Constants
  */
-#define GIC_SGI_INT_BASE		0
-#define GIC_PPI_INT_BASE		16
-
-#define GIC_IS_SGI(intid)		(((intid) >= GIC_SGI_INT_BASE) && \
-					 ((intid) < GIC_PPI_INT_BASE))
+#define GIC_SGI_INT_BASE 0
+#define GIC_PPI_INT_BASE 16
 
+#define GIC_IS_SGI(intid) (((intid) >= GIC_SGI_INT_BASE) && ((intid) < GIC_PPI_INT_BASE))
 
-#define GIC_SPI_INT_BASE		32
+#define GIC_SPI_INT_BASE 32
 
-#define GIC_SPI_MAX_INTID		1019
+#define GIC_SPI_MAX_INTID 1019
 
-#define GIC_IS_SPI(intid)		(((intid) >= GIC_SPI_INT_BASE) && \
-					((intid) <= GIC_SPI_MAX_INTID))
+#define GIC_IS_SPI(intid) (((intid) >= GIC_SPI_INT_BASE) && ((intid) <= GIC_SPI_MAX_INTID))
 
-#define GIC_NUM_INTR_PER_REG		32
+#define GIC_NUM_INTR_PER_REG 32
 
-#define GIC_NUM_CFG_PER_REG		16
+#define GIC_NUM_CFG_PER_REG 16
 
-#define GIC_NUM_PRI_PER_REG		4
+#define GIC_NUM_PRI_PER_REG 4
 
 /* GIC idle priority : value '0xff' will allow all interrupts */
-#define GIC_IDLE_PRIO			0xff
+#define GIC_IDLE_PRIO 0xff
 
 /* Priority levels 0:255 */
-#define GIC_PRI_MASK			0xff
+#define GIC_PRI_MASK 0xff
 
 /*
  * '0xa0'is used to initialize each interrupt default priority.
@@ -255,13 +306,13 @@
  * The values of individual interrupt and default has to be chosen
  * carefully if PMR and BPR based nesting and preemption has to be done.
  */
-#define GIC_INT_DEF_PRI_X4		0xa0a0a0a0
+#define GIC_INT_DEF_PRI_X4 0xa0a0a0a0
 
 /* GIC special interrupt id */
-#define GIC_INTID_SPURIOUS		1023
+#define GIC_INTID_SPURIOUS 1023
 
 /* Fixme: update from platform specific define or dt */
-#define GIC_NUM_CPU_IF			CONFIG_MP_MAX_NUM_CPUS
+#define GIC_NUM_CPU_IF CONFIG_MP_MAX_NUM_CPUS
 
 #ifndef _ASMLANGUAGE
 
@@ -323,8 +374,7 @@ void arm_gic_irq_clear_pending(unsigned int irq);
  * @param prio interrupt priority
  * @param flags interrupt flags
  */
-void arm_gic_irq_set_priority(
-	unsigned int irq, unsigned int prio, unsigned int flags);
+void arm_gic_irq_set_priority(unsigned int irq, unsigned int prio, unsigned int flags);
 
 /**
  * @brief Get active interrupt ID
@@ -355,8 +405,7 @@ void arm_gic_secondary_init(void);
  *                    Aff level 1 2 3 will be extracted by api.
  * @param target_list bitmask of target cores
  */
-void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff,
-		   uint16_t target_list);
+void gic_raise_sgi(unsigned int sgi_id, uint64_t target_aff, uint16_t target_list);
 
 #endif /* !_ASMLANGUAGE */
 
diff --git a/include/zephyr/drivers/interrupt_controller/intc_esp32.h b/include/zephyr/drivers/interrupt_controller/intc_esp32.h
index 5b5ce8d94bb..91083528e37 100644
--- a/include/zephyr/drivers/interrupt_controller/intc_esp32.h
+++ b/include/zephyr/drivers/interrupt_controller/intc_esp32.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2021-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,9 +10,6 @@
 #include <stdint.h>
 #include <stdbool.h>
 
-/* number of possible interrupts per core */
-#define ESP_INTC_INTS_NUM		(32)
-
 /*
  * Interrupt allocation flags - These flags can be used to specify
  * which interrupt qualities the code calling esp_intr_alloc* needs.
@@ -71,6 +68,12 @@
 /* Function prototype for interrupt handler function */
 typedef void (*intr_handler_t)(void *arg);
 
+/* Interrupt handler associated data structure */
+typedef struct intr_handle_data_t intr_handle_data_t;
+
+/* Handle to an interrupt handler */
+typedef intr_handle_data_t *intr_handle_t;
+
 struct shared_vector_desc_t {
 	int disabled : 1;
 	int source : 8;
@@ -97,11 +100,6 @@ struct intr_handle_data_t {
 	struct shared_vector_desc_t *shared_vector_desc;
 };
 
-/**
- * @brief Initializes interrupt table to its defaults
- */
-void esp_intr_initialize(void);
-
 /**
  * @brief Mark an interrupt as a shared interrupt
  *
@@ -158,7 +156,7 @@ int esp_intr_reserve(int intno, int cpu);
  * @param handler The interrupt handler. Must be NULL when an interrupt of level >3
  *               is requested, because these types of interrupts aren't C-callable.
  * @param arg    Optional argument for passed to the interrupt handler
- * @param ret_handle Pointer to a struct intr_handle_data_t pointer to store a handle that can
+ * @param ret_handle Pointer to an intr_handle_t pointer to store a handle that can
  *               later be used to request details or free the interrupt. Can be NULL if no handle
  *               is required.
  *
@@ -170,7 +168,7 @@ int esp_intr_alloc(int source,
 		int flags,
 		intr_handler_t handler,
 		void *arg,
-		struct intr_handle_data_t **ret_handle);
+		intr_handle_t *ret_handle);
 
 
 /**
@@ -200,7 +198,7 @@ int esp_intr_alloc(int source,
  * @param handler The interrupt handler. Must be NULL when an interrupt of level >3
  *               is requested, because these types of interrupts aren't C-callable.
  * @param arg    Optional argument for passed to the interrupt handler
- * @param ret_handle Pointer to a struct intr_handle_data_t pointer to store a handle that can
+ * @param ret_handle Pointer to an intr_handle_t pointer to store a handle that can
  *               later be used to request details or free the interrupt. Can be NULL if no handle
  *               is required.
  *
@@ -214,7 +212,7 @@ int esp_intr_alloc_intrstatus(int source,
 		uint32_t intrstatusmask,
 		intr_handler_t handler,
 		void *arg,
-		struct intr_handle_data_t **ret_handle);
+		intr_handle_t *ret_handle);
 
 
 /**
@@ -235,7 +233,7 @@ int esp_intr_alloc_intrstatus(int source,
  * @return -EINVAL the handle is NULL
  *         0 otherwise
  */
-int esp_intr_free(struct intr_handle_data_t *handle);
+int esp_intr_free(intr_handle_t handle);
 
 
 /**
@@ -245,7 +243,7 @@ int esp_intr_free(struct intr_handle_data_t *handle);
  *
  * @return The core number where the interrupt is allocated
  */
-int esp_intr_get_cpu(struct intr_handle_data_t *handle);
+int esp_intr_get_cpu(intr_handle_t handle);
 
 /**
  * @brief Get the allocated interrupt for a certain handle
@@ -254,7 +252,7 @@ int esp_intr_get_cpu(struct intr_handle_data_t *handle);
  *
  * @return The interrupt number
  */
-int esp_intr_get_intno(struct intr_handle_data_t *handle);
+int esp_intr_get_intno(intr_handle_t handle);
 
 /**
  * @brief Disable the interrupt associated with the handle
@@ -272,7 +270,7 @@ int esp_intr_get_intno(struct intr_handle_data_t *handle);
  * @return -EINVAL if the combination of arguments is invalid.
  *         0 otherwise
  */
-int esp_intr_disable(struct intr_handle_data_t *handle);
+int esp_intr_disable(intr_handle_t handle);
 
 /**
  * @brief Enable the interrupt associated with the handle
@@ -285,7 +283,7 @@ int esp_intr_disable(struct intr_handle_data_t *handle);
  * @return -EINVAL if the combination of arguments is invalid.
  *         0 otherwise
  */
-int esp_intr_enable(struct intr_handle_data_t *handle);
+int esp_intr_enable(intr_handle_t handle);
 
 /**
  * @brief Set the "in IRAM" status of the handler.
@@ -299,7 +297,7 @@ int esp_intr_enable(struct intr_handle_data_t *handle);
  * @return -EINVAL if the combination of arguments is invalid.
  *         0 otherwise
  */
-int esp_intr_set_in_iram(struct intr_handle_data_t *handle, bool is_in_iram);
+int esp_intr_set_in_iram(intr_handle_t handle, bool is_in_iram);
 
 /**
  * @brief Disable interrupts that aren't specifically marked as running from IRAM
diff --git a/include/zephyr/drivers/interrupt_controller/intc_esp32c3.h b/include/zephyr/drivers/interrupt_controller/intc_esp32c3.h
deleted file mode 100644
index a30dc16ed0f..00000000000
--- a/include/zephyr/drivers/interrupt_controller/intc_esp32c3.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32C3_H_
-#define ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32C3_H_
-
-#include <stdint.h>
-#include <stdbool.h>
-#include <soc.h>
-/*
- * Interrupt allocation flags - These flags can be used to specify
- * which interrupt qualities the code calling esp_intr_alloc* needs.
- */
-
-/* Keep the LEVELx values as they are here; they match up with (1<<level) */
-#define ESP_INTR_FLAG_LEVEL1		(1<<1)	/* Accept a Level 1 int vector, lowest priority */
-#define ESP_INTR_FLAG_LEVEL2		(1<<2)	/* Accept a Level 2 int vector */
-#define ESP_INTR_FLAG_LEVEL3		(1<<3)	/* Accept a Level 3 int vector */
-#define ESP_INTR_FLAG_LEVEL4		(1<<4)	/* Accept a Level 4 int vector */
-#define ESP_INTR_FLAG_LEVEL5		(1<<5)	/* Accept a Level 5 int vector */
-#define ESP_INTR_FLAG_LEVEL6		(1<<6)	/* Accept a Level 6 int vector */
-#define ESP_INTR_FLAG_NMI		(1<<7)	/* Accept a Level 7 int vector, highest priority */
-#define ESP_INTR_FLAG_SHARED		(1<<8)	/* Interrupt can be shared between ISRs */
-#define ESP_INTR_FLAG_EDGE		(1<<9)	/* Edge-triggered interrupt */
-#define ESP_INTR_FLAG_IRAM		(1<<10)	/* ISR can be called if cache is disabled */
-#define ESP_INTR_FLAG_INTRDISABLED	(1<<11)	/* Return with this interrupt disabled */
-
-/* Low and medium prio interrupts. These can be handled in C. */
-#define ESP_INTR_FLAG_LOWMED	(ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3)
-
-/* High level interrupts. Need to be handled in assembly. */
-#define ESP_INTR_FLAG_HIGH	(ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \
-				 ESP_INTR_FLAG_NMI)
-
-/* Mask for all level flags */
-#define ESP_INTR_FLAG_LEVELMASK	(ESP_INTR_FLAG_LEVEL1|ESP_INTR_FLAG_LEVEL2|ESP_INTR_FLAG_LEVEL3| \
-				 ESP_INTR_FLAG_LEVEL4|ESP_INTR_FLAG_LEVEL5|ESP_INTR_FLAG_LEVEL6| \
-				 ESP_INTR_FLAG_NMI)
-
-/*
- * Get the interrupt flags from the supplied priority.
- */
-#define ESP_PRIO_TO_FLAGS(priority) \
-	((priority) > 0 ? ((1 << (priority)) & ESP_INTR_FLAG_LEVELMASK) : 0)
-
-/*
- * Check interrupt flags from input and filter unallowed values.
- */
-#define ESP_INT_FLAGS_CHECK(int_flags) ((int_flags) & ESP_INTR_FLAG_SHARED)
-
-
-/* Function prototype for interrupt handler function */
-typedef void (*isr_handler_t)(const void *arg);
-
-/**
- * @brief Initializes interrupt table to its defaults
- */
-void esp_intr_initialize(void);
-
-/**
- * @brief Allocate an interrupt with the given parameters.
- *
- * This finds an interrupt that matches the restrictions as given in the flags
- * parameter, maps the given interrupt source to it and hooks up the given
- * interrupt handler (with optional argument) as well. If needed, it can return
- * a handle for the interrupt as well.
- *
- * @param source The interrupt source.
- * @param flags An ORred mask of the ESP_INTR_FLAG_* defines. These restrict the
- *               choice of interrupts that this routine can choose from. If this value
- *               is 0, it will default to allocating a non-shared interrupt of level
- *               1, 2 or 3. If this is ESP_INTR_FLAG_SHARED, it will allocate a shared
- *               interrupt of level 1. Setting ESP_INTR_FLAG_INTRDISABLED will return
- *               from this function with the interrupt disabled.
- * @param handler The interrupt handler.
- * @param arg    Optional argument for passed to the interrupt handler
- * @param ret_handle Pointer to a struct intr_handle_data_t pointer to store a handle that can
- *               later be used to request details or free the interrupt. Can be NULL if no handle
- *               is required.
- *
- * @return -EINVAL if the combination of arguments is invalid.
- *         -ENODEV No free interrupt found with the specified flags
- *         0 otherwise
- */
-int esp_intr_alloc(int source,
-		int flags,
-		isr_handler_t handler,
-		void *arg,
-		void **ret_handle);
-
-/**
- * @brief Disable the interrupt associated with the source
- *
- * @param source The interrupt source
- *
- * @return -EINVAL if the combination of arguments is invalid.
- *         0 otherwise
- */
-int esp_intr_disable(int source);
-
-/**
- * @brief Enable the interrupt associated with the source
- *
- * @param source The interrupt source
- * @return -EINVAL if the combination of arguments is invalid.
- *         0 otherwise
- */
-int esp_intr_enable(int source);
-
-/**
- * @brief Gets the current enabled interrupts
- *
- * @param status_mask_number the status mask can be 0 or 1
- * @return bitmask of enabled interrupt sources
- */
-uint32_t esp_intr_get_enabled_intmask(int status_mask_number);
-
-#endif /* ZEPHYR_INCLUDE_DRIVERS_INTERRUPT_CONTROLLER_INTC_ESP32C3_H_ */
diff --git a/include/zephyr/drivers/interrupt_controller/intc_ra_icu.h b/include/zephyr/drivers/interrupt_controller/intc_ra_icu.h
deleted file mode 100644
index d347d81cad8..00000000000
--- a/include/zephyr/drivers/interrupt_controller/intc_ra_icu.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/dt-bindings/interrupt-controller/renesas-ra-icu.h>
-
-#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_RA_ICU_H_
-#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_RA_ICU_H_
-
-#define RA_ICU_FLAG_EVENT_OFFSET  8
-#define RA_ICU_FLAG_EVENT_MASK    (BIT_MASK(8) << RA_ICU_FLAG_EVENT_OFFSET)
-#define RA_ICU_FLAG_INTCFG_OFFSET 16
-#define RA_ICU_FLAG_INTCFG_MASK   (BIT_MASK(8) << RA_ICU_FLAG_INTCFG_OFFSET)
-
-enum icu_irq_mode {
-	ICU_FALLING,
-	ICU_RISING,
-	ICU_BOTH_EDGE,
-	ICU_LOW_LEVEL,
-};
-
-typedef void (*ra_isr_handler)(const void *);
-
-extern void ra_icu_clear_int_flag(unsigned int irqn);
-
-extern int ra_icu_query_available_irq(uint32_t event);
-extern int ra_icu_query_exists_irq(uint32_t event);
-
-extern void ra_icu_query_irq_config(unsigned int irq, uint32_t *intcfg, ra_isr_handler *pisr,
-				    const void **cbarg);
-
-extern int ra_icu_irq_connect_dynamic(unsigned int irq, unsigned int priority,
-				      void (*routine)(const void *parameter), const void *parameter,
-				      uint32_t flags);
-
-extern int ra_icu_irq_disconnect_dynamic(unsigned int irq, unsigned int priority,
-					 void (*routine)(const void *parameter),
-					 const void *parameter, uint32_t flags);
-
-#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_RA_ICU_H_ */
diff --git a/include/zephyr/drivers/interrupt_controller/intc_rz_ext_irq.h b/include/zephyr/drivers/interrupt_controller/intc_rz_ext_irq.h
new file mode 100644
index 00000000000..b9865c91c87
--- /dev/null
+++ b/include/zephyr/drivers/interrupt_controller/intc_rz_ext_irq.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_RZ_EXT_IRQ_H_
+#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_RZ_EXT_IRQ_H_
+
+#define RZ_EXT_IRQ_TRIG_FALLING   0
+#define RZ_EXT_IRQ_TRIG_RISING    1
+#define RZ_EXT_IRQ_TRIG_BOTH_EDGE 2
+#define RZ_EXT_IRQ_TRIG_LEVEL_LOW 3
+
+/** RZ external interrupt callback */
+typedef void (*intc_rz_ext_irq_callback_t)(void *arg);
+
+/**
+ * @brief Enable external interrupt for specified channel.
+ *
+ * @param dev: pointer to interrupt controller instance
+ * @return 0 on success, or negative value on error
+ */
+int intc_rz_ext_irq_enable(const struct device *dev);
+
+/**
+ * @brief Disable external interrupt for specified channel.
+ *
+ * @param dev: pointer to interrupt controller instance
+ * @return 0 on success, or negative value on error
+ */
+int intc_rz_ext_irq_disable(const struct device *dev);
+
+/**
+ * @brief Updates the user callback
+ *
+ * @param dev: pointer to interrupt controller instance
+ * @param cb: callback to set
+ * @param arg: user data passed to callback
+ * @return 0 on success, or negative value on error
+ */
+int intc_rz_ext_irq_set_callback(const struct device *dev, intc_rz_ext_irq_callback_t cb,
+				 void *arg);
+
+/**
+ * @brief Change trigger external interrupt type for specified channel.
+ *
+ * @param dev: pointer to interrupt controller instance
+ * @param trig: trigger type to be changed
+ * @return 0 on success, or negative value on error
+ */
+int intc_rz_ext_irq_set_type(const struct device *dev, uint8_t trig);
+
+#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_RZ_EXT_IRQ_H_ */
diff --git a/include/zephyr/drivers/interrupt_controller/loapic.h b/include/zephyr/drivers/interrupt_controller/loapic.h
index 75a47955bc6..f0e58ff95e0 100644
--- a/include/zephyr/drivers/interrupt_controller/loapic.h
+++ b/include/zephyr/drivers/interrupt_controller/loapic.h
@@ -43,6 +43,7 @@
 
 #define LOAPIC_ICR_BUSY		0x00001000	/* delivery status: 1 = busy */
 
+#define LOAPIC_ICR_IPI_SPECIFIC 0x00004000U     /* target IPI to specific CPU */
 #define LOAPIC_ICR_IPI_OTHERS	0x000C4000U	/* normal IPI to other CPUs */
 #define LOAPIC_ICR_IPI_INIT	0x00004500U
 #define LOAPIC_ICR_IPI_STARTUP	0x00004600U
diff --git a/include/zephyr/drivers/interrupt_controller/wuc_ite_it51xxx.h b/include/zephyr/drivers/interrupt_controller/wuc_ite_it51xxx.h
new file mode 100644
index 00000000000..f039381af75
--- /dev/null
+++ b/include/zephyr/drivers/interrupt_controller/wuc_ite_it51xxx.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_IT51XXX_WUC_H_
+#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_IT51XXX_WUC_H_
+
+#include <zephyr/device.h>
+
+/**
+ * @name wakeup controller flags
+ * @{
+ */
+/** WUC rising edge trigger mode */
+#define WUC_TYPE_EDGE_RISING  BIT(0)
+/** WUC falling edge trigger mode */
+#define WUC_TYPE_EDGE_FALLING BIT(1)
+/** WUC both edge trigger mode */
+#define WUC_TYPE_EDGE_BOTH    (WUC_TYPE_EDGE_RISING | WUC_TYPE_EDGE_FALLING)
+
+#define WUC_TYPE_LEVEL_TRIG BIT(2)
+/** WUC level high trigger mode */
+#define WUC_TYPE_LEVEL_HIGH BIT(3)
+/** WUC level low trigger mode */
+#define WUC_TYPE_LEVEL_LOW  BIT(4)
+
+/** @} */
+
+/**
+ * @brief A trigger condition on the corresponding input generates
+ *        a wake-up signal to the power management control of EC
+ *
+ * @param dev Pointer to the device structure for the driver instance
+ * @param mask Pin mask of WUC group
+ */
+void it51xxx_wuc_enable(const struct device *dev, uint8_t mask);
+
+/**
+ * @brief A trigger condition on the corresponding input doesn't
+ *        assert the wake-up signal (canceled not pending)
+ *
+ * @param dev Pointer to the device structure for the driver instance
+ * @param mask Pin mask of WUC group
+ */
+void it51xxx_wuc_disable(const struct device *dev, uint8_t mask);
+
+/**
+ * @brief Write-1-clear a trigger condition that occurs on the
+ *        corresponding input
+ *
+ * @param dev Pointer to the device structure for the driver instance
+ * @param mask Pin mask of WUC group
+ */
+void it51xxx_wuc_clear_status(const struct device *dev, uint8_t mask);
+
+/**
+ * @brief Select the trigger edge mode on the corresponding input
+ *
+ * @param dev Pointer to the device structure for the driver instance
+ * @param mask Pin mask of WUC group
+ * @param flags Select the trigger edge mode
+ */
+void it51xxx_wuc_set_polarity(const struct device *dev, uint8_t mask, uint32_t flags);
+
+#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_IT51XXX_WUC_H_ */
diff --git a/include/zephyr/drivers/kscan.h b/include/zephyr/drivers/kscan.h
deleted file mode 100644
index f12e2809062..00000000000
--- a/include/zephyr/drivers/kscan.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * Copyright (c) 2019 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief Public API for Keyboard scan matrix devices.
- * The scope of this API is simply to report which key event was triggered
- * and users can later decode keys using their desired scan code tables in
- * their application. In addition, typematic rate and delay can easily be
- * implemented using a timer if desired.
- */
-
-#ifndef ZEPHYR_INCLUDE_DRIVERS_KB_SCAN_H_
-#define ZEPHYR_INCLUDE_DRIVERS_KB_SCAN_H_
-
-#include <errno.h>
-#include <zephyr/types.h>
-#include <stddef.h>
-#include <zephyr/device.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief KSCAN APIs
- * @defgroup kscan_interface Keyboard Scan Driver APIs
- * @since 2.1
- * @version 1.0.0
- * @deprecated
- * @ingroup io_interfaces
- * @{
- */
-
-/**
- * @deprecated
- * @brief Keyboard scan callback called when user press/release
- * a key on a matrix keyboard.
- *
- * @param dev Pointer to the device structure for the driver instance.
- * @param row Describes row change.
- * @param column Describes column change.
- * @param pressed Describes the kind of key event.
- */
-typedef void (*kscan_callback_t)(const struct device *dev, uint32_t row,
-				 uint32_t column,
-				 bool pressed);
-
-/**
- * @deprecated
- * @cond INTERNAL_HIDDEN
- *
- * Keyboard scan driver API definition and system call entry points.
- *
- * (Internal use only.)
- */
-typedef int (*kscan_config_t)(const struct device *dev,
-			      kscan_callback_t callback);
-typedef int (*kscan_disable_callback_t)(const struct device *dev);
-typedef int (*kscan_enable_callback_t)(const struct device *dev);
-
-__subsystem struct kscan_driver_api {
-	kscan_config_t config;
-	kscan_disable_callback_t disable_callback;
-	kscan_enable_callback_t enable_callback;
-};
-/**
- * @endcond
- */
-
-/**
- * @deprecated
- * @brief Configure a Keyboard scan instance.
- *
- * @param dev Pointer to the device structure for the driver instance.
- * @param callback called when keyboard devices reply to a keyboard
- * event such as key pressed/released.
- *
- * @retval 0 If successful.
- * @retval Negative errno code if failure.
- */
-__syscall int kscan_config(const struct device *dev,
-			     kscan_callback_t callback);
-
-static inline int z_impl_kscan_config(const struct device *dev,
-					kscan_callback_t callback)
-{
-	const struct kscan_driver_api *api =
-				(struct kscan_driver_api *)dev->api;
-
-	return api->config(dev, callback);
-}
-/**
- * @deprecated
- * @brief Enables callback.
- * @param dev Pointer to the device structure for the driver instance.
- *
- * @retval 0 If successful.
- * @retval Negative errno code if failure.
- */
-__syscall int kscan_enable_callback(const struct device *dev);
-
-static inline int z_impl_kscan_enable_callback(const struct device *dev)
-{
-	const struct kscan_driver_api *api =
-			(const struct kscan_driver_api *)dev->api;
-
-	if (api->enable_callback == NULL) {
-		return -ENOSYS;
-	}
-
-	return api->enable_callback(dev);
-}
-
-/**
- * @deprecated
- * @brief Disables callback.
- * @param dev Pointer to the device structure for the driver instance.
- *
- * @retval 0 If successful.
- * @retval Negative errno code if failure.
- */
-__syscall int kscan_disable_callback(const struct device *dev);
-
-static inline int z_impl_kscan_disable_callback(const struct device *dev)
-{
-	const struct kscan_driver_api *api =
-			(const struct kscan_driver_api *)dev->api;
-
-	if (api->disable_callback == NULL) {
-		return -ENOSYS;
-	}
-
-	return api->disable_callback(dev);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-/**
- * @}
- */
-
-#include <zephyr/syscalls/kscan.h>
-
-#endif /* ZEPHYR_INCLUDE_DRIVERS_KB_SCAN_H_ */
diff --git a/include/zephyr/drivers/mfd/max22017.h b/include/zephyr/drivers/mfd/max22017.h
new file mode 100644
index 00000000000..a8f837020ab
--- /dev/null
+++ b/include/zephyr/drivers/mfd/max22017.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2024 Analog Devices Inc.
+ * Copyright (c) 2024 Baylibre SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_MAX22017_H_
+#define ZEPHYR_INCLUDE_DRIVERS_MFD_MAX22017_H_
+
+#include <zephyr/device.h>
+
+#define MAX22017_LDAC_TOGGLE_TIME 200
+#define MAX22017_MAX_CHANNEL      2
+#define MAX22017_CRC_POLY         0x8c /* reversed 0x31 poly for crc8-maxim */
+
+#define MAX22017_GEN_ID_OFF     0x00
+#define MAX22017_GEN_ID_PROD_ID GENMASK(15, 8)
+#define MAX22017_GEN_ID_REV_ID  GENMASK(7, 0)
+
+#define MAX22017_GEN_SERIAL_MSB_OFF        0x01
+#define MAX22017_GEN_SERIAL_MSB_SERIAL_MSB GENMASK(15, 0)
+
+#define MAX22017_GEN_SERIAL_LSB_OFF        0x02
+#define MAX22017_GEN_SERIAL_LSB_SERIAL_LSB GENMASK(15, 0)
+
+#define MAX22017_GEN_CNFG_OFF                0x03
+#define MAX22017_GEN_CNFG_OPENWIRE_DTCT_CNFG GENMASK(15, 14)
+#define MAX22017_GEN_CNFG_TMOUT_SEL          GENMASK(13, 10)
+#define MAX22017_GEN_CNFG_TMOUT_CNFG         BIT(9)
+#define MAX22017_GEN_CNFG_TMOUT_EN           BIT(8)
+#define MAX22017_GEN_CNFG_THSHDN_CNFG        GENMASK(7, 6)
+#define MAX22017_GEN_CNFG_OVC_SHDN_CNFG      GENMASK(5, 4)
+#define MAX22017_GEN_CNFG_OVC_CNFG           GENMASK(3, 2)
+#define MAX22017_GEN_CNFG_CRC_EN             BIT(1)
+#define MAX22017_GEN_CNFG_DACREF_SEL         BIT(0)
+
+#define MAX22017_GEN_GPIO_CTRL_OFF      0x04
+#define MAX22017_GEN_GPIO_CTRL_GPIO_EN  GENMASK(13, 8)
+#define MAX22017_GEN_GPIO_CTRL_GPIO_DIR GENMASK(5, 0)
+
+#define MAX22017_GEN_GPIO_DATA_OFF      0x05
+#define MAX22017_GEN_GPIO_DATA_GPO_DATA GENMASK(13, 8)
+#define MAX22017_GEN_GPIO_DATA_GPI_DATA GENMASK(5, 0)
+
+#define MAX22017_GEN_GPI_INT_OFF              0x06
+#define MAX22017_GEN_GPI_INT_GPI_POS_EDGE_INT GENMASK(13, 8)
+#define MAX22017_GEN_GPI_INT_GPI_NEG_EDGE_INT GENMASK(5, 0)
+
+#define MAX22017_GEN_GPI_INT_STA_OFF                  0x07
+#define MAX22017_GEN_GPI_INT_STA_GPI_POS_EDGE_INT_STA GENMASK(13, 8)
+#define MAX22017_GEN_GPI_INT_STA_GPI_NEG_EDGE_INT_STA GENMASK(5, 0)
+
+#define MAX22017_GEN_INT_OFF               0x08
+#define MAX22017_GEN_INT_FAIL_INT          BIT(15)
+#define MAX22017_GEN_INT_CONV_OVF_INT      GENMASK(13, 12)
+#define MAX22017_GEN_INT_OPENWIRE_DTCT_INT GENMASK(11, 10)
+#define MAX22017_GEN_INT_HVDD_INT          BIT(9)
+#define MAX22017_GEN_INT_TMOUT_INT         BIT(8)
+#define MAX22017_GEN_INT_THSHDN_INT        GENMASK(7, 6)
+#define MAX22017_GEN_INT_THWRNG_INT        GENMASK(5, 4)
+#define MAX22017_GEN_INT_OVC_INT           GENMASK(3, 2)
+#define MAX22017_GEN_INT_CRC_INT           BIT(1)
+#define MAX22017_GEN_INT_GPI_INT           BIT(0)
+
+#define MAX22017_GEN_INTEN_OFF                 0x09
+#define MAX22017_GEN_INTEN_CONV_OVF_INTEN      GENMASK(13, 12)
+#define MAX22017_GEN_INTEN_OPENWIRE_DTCT_INTEN GENMASK(11, 10)
+#define MAX22017_GEN_INTEN_HVDD_INTEN          BIT(9)
+#define MAX22017_GEN_INTEN_TMOUT_INTEN         BIT(8)
+#define MAX22017_GEN_INTEN_THSHDN_INTEN        GENMASK(7, 6)
+#define MAX22017_GEN_INTEN_THWRNG_INTEN        GENMASK(5, 4)
+#define MAX22017_GEN_INTEN_OVC_INTEN           GENMASK(3, 2)
+#define MAX22017_GEN_INTEN_CRC_INTEN           BIT(1)
+#define MAX22017_GEN_INTEN_GPI_INTEN           BIT(0)
+
+#define MAX22017_GEN_RST_CTRL_OFF             0x0A
+#define MAX22017_GEN_RST_CTRL_AO_COEFF_RELOAD GENMASK(15, 14)
+#define MAX22017_GEN_RST_CTRL_GEN_RST         BIT(9)
+
+#define MAX22017_AO_CMD_OFF        0x40
+#define MAX22017_AO_CMD_AO_LD_CTRL GENMASK(15, 14)
+
+#define MAX22017_AO_STA_OFF      0x41
+#define MAX22017_AO_STA_BUSY_STA GENMASK(15, 14)
+#define MAX22017_AO_STA_SLEW_STA GENMASK(13, 12)
+#define MAX22017_AO_STA_FAIL_STA BIT(0)
+
+#define MAX22017_AO_CNFG_OFF                  0x42
+#define MAX22017_AO_CNFG_AO_LD_CNFG           GENMASK(15, 14)
+#define MAX22017_AO_CNFG_AO_CM_SENSE          GENMASK(13, 12)
+#define MAX22017_AO_CNFG_AO_UNI               GENMASK(11, 10)
+#define MAX22017_AO_CNFG_AO_MODE              GENMASK(9, 8)
+#define MAX22017_AO_CNFG_AO_OPENWIRE_DTCT_LMT GENMASK(5, 4)
+#define MAX22017_AO_CNFG_AI_EN                GENMASK(3, 2)
+#define MAX22017_AO_CNFG_AO_EN                GENMASK(1, 0)
+
+#define MAX22017_AO_SLEW_RATE_CHn_OFF(n)                (0x43 + n)
+#define MAX22017_AO_SLEW_RATE_CHn_AO_SR_EN_CHn          BIT(5)
+#define MAX22017_AO_SLEW_RATE_CHn_AO_SR_SEL_CHn         BIT(4)
+#define MAX22017_AO_SLEW_RATE_CHn_AO_SR_STEP_SIZE_CHn   GENMASK(3, 2)
+#define MAX22017_AO_SLEW_RATE_CHn_AO_SR_UPDATE_RATE_CHn GENMASK(1, 0)
+
+#define MAX22017_AO_DATA_CHn_OFF(n)     (0x45 + n)
+#define MAX22017_AO_DATA_CHn_AO_DATA_CH GENMASK(15, 0)
+
+#define MAX22017_AO_OFFSET_CORR_CHn_OFF(n)       (0x47 + (2 * n))
+#define MAX22017_AO_OFFSET_CORR_CHn_AO_OFFSET_CH GENMASK(15, 0)
+
+#define MAX22017_AO_GAIN_CORR_CHn_OFF(n)     (0x48 + (2 * n))
+#define MAX22017_AO_GAIN_CORR_CHn_AO_GAIN_CH GENMASK(15, 0)
+
+#define MAX22017_SPI_TRANS_ADDR    GENMASK(7, 1)
+#define MAX22017_SPI_TRANS_DIR     BIT(0)
+#define MAX22017_SPI_TRANS_PAYLOAD GENMASK(15, 0)
+
+/**
+ * @defgroup mdf_interface_max22017 MFD MAX22017 interface
+ * @ingroup mfd_interfaces
+ * @{
+ */
+
+/**
+ * @brief Read register from max22017
+ *
+ * @param dev max22017 mfd device
+ * @param addr register address to read from
+ * @param value pointer to buffer for received data
+ * @retval 0 If successful
+ * @retval -errno In case of any error (see spi_transceive_dt())
+ */
+int max22017_reg_read(const struct device *dev, uint8_t addr, uint16_t *value);
+
+/**
+ * @brief Write register to max22017
+ *
+ * @param dev max22017 mfd device
+ * @param addr register address to write to
+ * @param value content to write
+ * @retval 0 If successful
+ * @retval -errno In case of any error (see spi_write_dt())
+ */
+int max22017_reg_write(const struct device *dev, uint8_t addr, uint16_t value);
+
+/**
+ * @}
+ */
+
+struct max22017_data {
+	const struct device *dev;
+	struct k_mutex lock;
+	struct k_work int_work;
+	struct gpio_callback callback_int;
+	bool crc_enabled;
+#ifdef CONFIG_GPIO_MAX22017
+	sys_slist_t callbacks_gpi;
+#endif
+};
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_MAX22017_H_ */
diff --git a/include/zephyr/drivers/mfd/mfd_maxq10xx.h b/include/zephyr/drivers/mfd/mfd_maxq10xx.h
new file mode 100644
index 00000000000..35baa9bb79e
--- /dev/null
+++ b/include/zephyr/drivers/mfd/mfd_maxq10xx.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 Vogl Electronic GmbH
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_MFD_MAXQ10XX_H_
+#define ZEPHYR_INCLUDE_DRIVERS_MFD_MAXQ10XX_H_
+
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Get the semaphore reference for a MAXQ1xx instance. Callers
+ * should pass the return value to k_sem_take/k_sem_give
+ *
+ * @param[in] dev     Pointer to device struct of the driver instance
+ *
+ * @return Address of the semaphore
+ */
+struct k_sem *mfd_maxq10xx_get_lock(const struct device *dev);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_MFD_MAXQ10XX_H_ */
diff --git a/include/zephyr/drivers/mic_privacy/intel/mic_privacy.h b/include/zephyr/drivers/mic_privacy/intel/mic_privacy.h
new file mode 100644
index 00000000000..950add9bab3
--- /dev/null
+++ b/include/zephyr/drivers/mic_privacy/intel/mic_privacy.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __ZEPHYR_INCLUDE_MIC_PRIVACY_H__
+#define __ZEPHYR_INCLUDE_MIC_PRIVACY_H__
+
+#include <stdint.h>
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <zephyr/kernel.h>
+#include <zephyr/spinlock.h>
+#include <zephyr/devicetree.h>
+
+enum mic_privacy_policy {
+	MIC_PRIVACY_DISABLED = 0,
+	MIC_PRIVACY_HW_MANAGED = 1,
+	MIC_PRIVACY_FW_MANAGED = 2,
+	MIC_PRIVACY_FORCE_MIC_DISABLED = 3,
+};
+
+/* has to match HW register definition
+ * (DZLS bit field in DFMICPVCP register)
+ */
+union mic_privacy_mask {
+	uint32_t value;
+	struct {
+		uint32_t sndw:7;
+		uint32_t dmic:1;
+	};
+};
+
+struct intel_adsp_mic_priv_data {
+	uint8_t rsvd;
+};
+
+struct intel_adsp_mic_priv_cfg {
+	uint32_t base;
+	uint32_t regblock_size;
+};
+
+struct mic_privacy_api_funcs {
+	void (*enable_fw_managed_irq)(bool enable_irq, const void *fn);
+	void (*clear_fw_managed_irq)();
+	void (*enable_dmic_irq)(bool enable_irq, const void *fn);
+	bool (*get_dmic_irq_status)(void);
+	void (*clear_dmic_irq_status)(void);
+	enum mic_privacy_policy (*get_policy)();
+	uint32_t (*get_privacy_policy_register_raw_value)();
+	uint32_t (*get_dma_data_zeroing_wait_time)();
+	uint32_t (*get_dma_data_zeroing_link_select)();
+	uint32_t (*get_dmic_mic_disable_status)(void);
+	uint32_t (*get_fw_managed_mic_disable_status)();
+	void (*set_fw_managed_mode)(bool is_fw_managed_enabled);
+	void (*set_fw_mic_disable_status)(bool fw_mic_disable_status);
+	uint32_t (*get_fw_mic_disable_status)();
+};
+
+#endif
diff --git a/include/zephyr/drivers/mipi_dsi/mipi_dsi_mcux_2l.h b/include/zephyr/drivers/mipi_dsi/mipi_dsi_mcux_2l.h
index 927fcba5e55..fae9db5eb0e 100644
--- a/include/zephyr/drivers/mipi_dsi/mipi_dsi_mcux_2l.h
+++ b/include/zephyr/drivers/mipi_dsi/mipi_dsi_mcux_2l.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2023 NXP
+ * Copyright 2023,2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,4 +13,10 @@
  */
 #define MCUX_DSI_2L_FB_DATA BIT(0x1)
 
+/*
+ * HW specific flag - user set this bit in message flag and after the
+ * transfer bus will enter ULPS.
+ */
+#define MCUX_DSI_2L_ULPS BIT(0x2)
+
 #endif /* ZEPHYR_INCLUDE_DRIVERS_MIPI_DSI_MCUX_2L_ */
diff --git a/include/zephyr/drivers/misc/ft8xx/ft8xx.h b/include/zephyr/drivers/misc/ft8xx/ft8xx.h
index 5b9dc589fbd..65f42e6fbb3 100644
--- a/include/zephyr/drivers/misc/ft8xx/ft8xx.h
+++ b/include/zephyr/drivers/misc/ft8xx/ft8xx.h
@@ -13,6 +13,7 @@
 #define ZEPHYR_DRIVERS_MISC_FT8XX_FT8XX_H_
 
 #include <stdint.h>
+#include <zephyr/device.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -45,8 +46,11 @@ struct ft8xx_touch_transform {
  * @brief Callback API to inform API user that FT8xx triggered interrupt
  *
  * This callback is called from IRQ context.
+ *
+ * @param dev Pointer to the device structure for the driver instance
+ * @param user_data Pointer to user data provided during callback registration
  */
-typedef void (*ft8xx_int_callback)(void);
+typedef void (*ft8xx_int_callback)(const struct device *dev, void *user_data);
 
 /**
  * @brief Calibrate touchscreen
@@ -59,9 +63,11 @@ typedef void (*ft8xx_int_callback)(void);
  * ft8xx_touch_transform_set() to avoid calibrating touchscreen after each
  * device reset.
  *
+ * @param dev  Pointer to the device structure for the driver instance
  * @param data Pointer to touchscreen transform structure to populate
  */
-void ft8xx_calibrate(struct ft8xx_touch_transform *data);
+void ft8xx_calibrate(const struct device *dev,
+		     struct ft8xx_touch_transform *data);
 
 /**
  * @brief Set touchscreen calibration data
@@ -70,16 +76,20 @@ void ft8xx_calibrate(struct ft8xx_touch_transform *data);
  * Data is to be obtained from calibration procedure started with
  * ft8xx_calibrate().
  *
+ * @param dev  Pointer to the device structure for the driver instance
  * @param data Pointer to touchscreen transform structure to apply
  */
-void ft8xx_touch_transform_set(const struct ft8xx_touch_transform *data);
+void ft8xx_touch_transform_set(const struct device *dev,
+			       const struct ft8xx_touch_transform *data);
 
 /**
  * @brief Get tag of recently touched element
  *
+ * @param dev Pointer to the device structure for the driver instance
+ *
  * @return Tag value 0-255 of recently touched element
  */
-int ft8xx_get_touch_tag(void);
+int ft8xx_get_touch_tag(const struct device *dev);
 
 /**
  * @brief Set callback executed when FT8xx triggers interrupt
@@ -91,9 +101,13 @@ int ft8xx_get_touch_tag(void);
  * kept active until ft8xx_get_touch_tag() is called. It results in single
  * execution of @p callback until ft8xx_get_touch_tag() is called.
  *
- * @param callback Pointer to function called when FT8xx triggers interrupt
+ * @param dev       Pointer to the device structure for the driver instance
+ * @param callback  Pointer to function called when FT8xx triggers interrupt
+ * @param user_data Pointer to user data to be passed to the @p callback
  */
-void ft8xx_register_int(ft8xx_int_callback callback);
+void ft8xx_register_int(const struct device *dev,
+			ft8xx_int_callback callback,
+			void *user_data);
 
 /**
  * @}
diff --git a/include/zephyr/drivers/misc/ft8xx/ft8xx_common.h b/include/zephyr/drivers/misc/ft8xx/ft8xx_common.h
index 2fde40e740a..64874d8b801 100644
--- a/include/zephyr/drivers/misc/ft8xx/ft8xx_common.h
+++ b/include/zephyr/drivers/misc/ft8xx/ft8xx_common.h
@@ -13,6 +13,7 @@
 #define ZEPHYR_DRIVERS_MISC_FT8XX_FT8XX_COMMON_H_
 
 #include <stdint.h>
+#include <zephyr/device.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -28,53 +29,59 @@ extern "C" {
 /**
  * @brief Write 1 byte (8 bits) to FT8xx memory
  *
+ * @param dev Pointer to the device structure for the driver instance
  * @param address Memory address to write to
  * @param data Byte to write
  */
-void ft8xx_wr8(uint32_t address, uint8_t data);
+void ft8xx_wr8(const struct device *dev, uint32_t address, uint8_t data);
 
 /**
  * @brief Write 2 bytes (16 bits) to FT8xx memory
  *
+ * @param dev Pointer to the device structure for the driver instance
  * @param address Memory address to write to
  * @param data Value to write
  */
-void ft8xx_wr16(uint32_t address, uint16_t data);
+void ft8xx_wr16(const struct device *dev, uint32_t address, uint16_t data);
 
 /**
  * @brief Write 4 bytes (32 bits) to FT8xx memory
  *
+ * @param dev Pointer to the device structure for the driver instance
  * @param address Memory address to write to
  * @param data Value to write
  */
-void ft8xx_wr32(uint32_t address, uint32_t data);
+void ft8xx_wr32(const struct device *dev, uint32_t address, uint32_t data);
 
 /**
  * @brief Read 1 byte (8 bits) from FT8xx memory
  *
+ * @param dev Pointer to the device structure for the driver instance
  * @param address Memory address to read from
  *
  * @return Value read from memory
  */
-uint8_t ft8xx_rd8(uint32_t address);
+uint8_t ft8xx_rd8(const struct device *dev, uint32_t address);
 
 /**
  * @brief Read 2 bytes (16 bits) from FT8xx memory
  *
+ * @param dev Pointer to the device structure for the driver instance
  * @param address Memory address to read from
  *
  * @return Value read from memory
  */
-uint16_t ft8xx_rd16(uint32_t address);
+uint16_t ft8xx_rd16(const struct device *dev, uint32_t address);
 
 /**
  * @brief Read 4 bytes (32 bits) from FT8xx memory
  *
+ * @param dev Pointer to the device structure for the driver instance
  * @param address Memory address to read from
  *
  * @return Value read from memory
  */
-uint32_t ft8xx_rd32(uint32_t address);
+uint32_t ft8xx_rd32(const struct device *dev, uint32_t address);
 
 /**
  * @}
diff --git a/include/zephyr/drivers/misc/ft8xx/ft8xx_copro.h b/include/zephyr/drivers/misc/ft8xx/ft8xx_copro.h
index 0913656ffde..1985f1c23d4 100644
--- a/include/zephyr/drivers/misc/ft8xx/ft8xx_copro.h
+++ b/include/zephyr/drivers/misc/ft8xx/ft8xx_copro.h
@@ -13,6 +13,7 @@
 #define ZEPHYR_DRIVERS_MISC_FT8XX_FT8XX_COPRO_H_
 
 #include <stdint.h>
+#include <zephyr/device.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -65,19 +66,24 @@ extern "C" {
 /**
  * @brief Execute a display list command by co-processor engine
  *
+ * @param dev Device structure
  * @param cmd Display list command to execute
  */
-void ft8xx_copro_cmd(uint32_t cmd);
+void ft8xx_copro_cmd(const struct device *dev, uint32_t cmd);
 
 /**
  * @brief Start a new display list
+ *
+ * @param dev Device structure
  */
-void ft8xx_copro_cmd_dlstart(void);
+void ft8xx_copro_cmd_dlstart(const struct device *dev);
 
 /**
  * @brief Swap the current display list
+ *
+ * @param dev Device structure
  */
-void ft8xx_copro_cmd_swap(void);
+void ft8xx_copro_cmd_swap(const struct device *dev);
 
 /**
  * @brief Draw text
@@ -88,17 +94,19 @@ void ft8xx_copro_cmd_swap(void);
  * the text in both directions. @ref FT8XX_OPT_RIGHTX right-justifies the text,
  * so that the @p x is the rightmost pixel.
  *
+ * @param dev Device structure
  * @param x x-coordinate of text base, in pixels
  * @param y y-coordinate of text base, in pixels
  * @param font Font to use for text, 0-31. 16-31 are ROM fonts
  * @param options Options to apply
- * @param s Character string to display, terminated with a null character
+ * @param string Character string to display, terminated with a null character
  */
-void ft8xx_copro_cmd_text(int16_t x,
-			   int16_t y,
-			   int16_t font,
-			   uint16_t options,
-			   const char *s);
+void ft8xx_copro_cmd_text(const struct device *dev,
+			  int16_t x,
+			  int16_t y,
+			  int16_t font,
+			  uint16_t options,
+			  const char *string);
 
 /**
  * @brief Draw a decimal number
@@ -113,17 +121,19 @@ void ft8xx_copro_cmd_text(int16_t x,
  * If @ref FT8XX_OPT_SIGNED is given, the number is treated as signed, and
  * prefixed by a minus sign if negative.
  *
+ * @param dev Device structure
  * @param x x-coordinate of text base, in pixels
  * @param y y-coordinate of text base, in pixels
  * @param font Font to use for text, 0-31. 16-31 are ROM fonts
  * @param options Options to apply
- * @param n The number to display.
+ * @param number The number to display.
  */
-void ft8xx_copro_cmd_number(int16_t x,
-			     int16_t y,
-			     int16_t font,
-			     uint16_t options,
-			     int32_t n);
+void ft8xx_copro_cmd_number(const struct device *dev,
+			    int16_t x,
+			    int16_t y,
+			    int16_t font,
+			    uint16_t options,
+			    int32_t number);
 
 /**
  * @brief Execute the touch screen calibration routine
@@ -134,9 +144,10 @@ void ft8xx_copro_cmd_number(int16_t x,
  * engine overlays the touch targets on the current display list, gathers the
  * calibration input and updates REG_TOUCH_TRANSFORM_A-F.
  *
+ * @param dev Device structure
  * @param result Calibration result, written with 0 on failure of calibration
  */
-void ft8xx_copro_cmd_calibrate(uint32_t *result);
+void ft8xx_copro_cmd_calibrate(const struct device *dev, uint32_t *result);
 
 /**
  * @}
diff --git a/include/zephyr/drivers/misc/ft8xx/ft8xx_reference_api.h b/include/zephyr/drivers/misc/ft8xx/ft8xx_reference_api.h
index c54dcdfc1b3..3fb17077608 100644
--- a/include/zephyr/drivers/misc/ft8xx/ft8xx_reference_api.h
+++ b/include/zephyr/drivers/misc/ft8xx/ft8xx_reference_api.h
@@ -46,7 +46,7 @@ extern "C" {
  */
 static inline void wr8(uint32_t address, uint8_t data)
 {
-	ft8xx_wr8(address, data);
+	ft8xx_wr8(DEVICE_DT_GET_ONE(ftdi_ft800), address, data);
 }
 
 /**
@@ -57,7 +57,7 @@ static inline void wr8(uint32_t address, uint8_t data)
  */
 static inline void wr16(uint32_t address, uint16_t data)
 {
-	ft8xx_wr16(address, data);
+	ft8xx_wr16(DEVICE_DT_GET_ONE(ftdi_ft800), address, data);
 }
 
 /**
@@ -68,7 +68,7 @@ static inline void wr16(uint32_t address, uint16_t data)
  */
 static inline void wr32(uint32_t address, uint32_t data)
 {
-	ft8xx_wr32(address, data);
+	ft8xx_wr32(DEVICE_DT_GET_ONE(ftdi_ft800), address, data);
 }
 
 /**
@@ -80,7 +80,7 @@ static inline void wr32(uint32_t address, uint32_t data)
  */
 static inline uint8_t rd8(uint32_t address)
 {
-	return ft8xx_rd8(address);
+	return ft8xx_rd8(DEVICE_DT_GET_ONE(ftdi_ft800), address);
 }
 
 /**
@@ -92,7 +92,7 @@ static inline uint8_t rd8(uint32_t address)
  */
 static inline uint16_t rd16(uint32_t address)
 {
-	return ft8xx_rd16(address);
+	return ft8xx_rd16(DEVICE_DT_GET_ONE(ftdi_ft800), address);
 }
 
 /**
@@ -104,7 +104,7 @@ static inline uint16_t rd16(uint32_t address)
  */
 static inline uint32_t rd32(uint32_t address)
 {
-	return ft8xx_rd32(address);
+	return ft8xx_rd32(DEVICE_DT_GET_ONE(ftdi_ft800), address);
 }
 
 
@@ -152,7 +152,7 @@ static inline uint32_t rd32(uint32_t address)
  */
 static inline void cmd(uint32_t command)
 {
-	ft8xx_copro_cmd(command);
+	ft8xx_copro_cmd(DEVICE_DT_GET_ONE(ftdi_ft800), command);
 }
 
 /**
@@ -160,7 +160,7 @@ static inline void cmd(uint32_t command)
  */
 static inline void cmd_dlstart(void)
 {
-	ft8xx_copro_cmd_dlstart();
+	ft8xx_copro_cmd_dlstart(DEVICE_DT_GET_ONE(ftdi_ft800));
 }
 
 /**
@@ -168,7 +168,7 @@ static inline void cmd_dlstart(void)
  */
 static inline void cmd_swap(void)
 {
-	ft8xx_copro_cmd_swap();
+	ft8xx_copro_cmd_swap(DEVICE_DT_GET_ONE(ftdi_ft800));
 }
 
 /**
@@ -191,7 +191,7 @@ static inline void cmd_text(int16_t x,
 			   uint16_t options,
 			   const char *s)
 {
-	ft8xx_copro_cmd_text(x, y, font, options, s);
+	ft8xx_copro_cmd_text(DEVICE_DT_GET_ONE(ftdi_ft800), x, y, font, options, s);
 }
 
 /**
@@ -218,7 +218,7 @@ static inline void cmd_number(int16_t x,
 			     uint16_t options,
 			     int32_t n)
 {
-	ft8xx_copro_cmd_number(x, y, font, options, n);
+	ft8xx_copro_cmd_number(DEVICE_DT_GET_ONE(ftdi_ft800), x, y, font, options, n);
 }
 
 /**
@@ -234,7 +234,7 @@ static inline void cmd_number(int16_t x,
  */
 static inline void cmd_calibrate(uint32_t *result)
 {
-	ft8xx_copro_cmd_calibrate(result);
+	ft8xx_copro_cmd_calibrate(DEVICE_DT_GET_ONE(ftdi_ft800), result);
 }
 
 
diff --git a/include/zephyr/drivers/mm/rat.h b/include/zephyr/drivers/mm/rat.h
index 216142a2680..a3e82292109 100644
--- a/include/zephyr/drivers/mm/rat.h
+++ b/include/zephyr/drivers/mm/rat.h
@@ -14,13 +14,6 @@ extern "C" {
 
 #include <stdint.h>
 
-#define ADDR_TRANSLATE_MAX_REGIONS (16u)
-#define RAT_CTRL(base_addr, i)     (base_addr + 0x20 + 0x10 * (i))
-#define RAT_BASE(base_addr, i)     (base_addr + 0x24 + 0x10 * (i))
-#define RAT_TRANS_L(base_addr, i)  (base_addr + 0x28 + 0x10 * (i))
-#define RAT_TRANS_H(base_addr, i)  (base_addr + 0x2C + 0x10 * (i))
-#define RAT_CTRL_W(enable, size)   (((enable & 0x1) << 31u) | (size & 0x3F))
-
 /**
  * @brief Enum's to represent different possible region size for the address translate module
  */
@@ -69,16 +62,8 @@ struct address_trans_region_config {
 	uint32_t size;
 };
 
-/**
- * @brief Parameters for address_trans_init
- */
-struct address_trans_params {
-	uint32_t num_regions;
-	uint32_t rat_base_addr;
-	struct address_trans_region_config *region_config;
-};
-
-void sys_mm_drv_ti_rat_init(void *region_config, uint64_t rat_base_addr, uint8_t translate_regions);
+void sys_mm_drv_ti_rat_init(struct address_trans_region_config *region_config,
+			    uint64_t rat_base_addr, uint8_t translate_regions);
 
 #ifdef __cplusplus
 }
diff --git a/include/zephyr/drivers/modem/hl7800.h b/include/zephyr/drivers/modem/hl7800.h
index 6cb880e6142..c784a789529 100644
--- a/include/zephyr/drivers/modem/hl7800.h
+++ b/include/zephyr/drivers/modem/hl7800.h
@@ -111,6 +111,12 @@ enum mdm_hl7800_event {
 	HL7800_EVENT_POLTE_LOCATE_STATUS,
 	HL7800_EVENT_POLTE,
 	HL7800_EVENT_SITE_SURVEY,
+	HL7800_EVENT_STATE,
+};
+
+enum mdm_hl7800_state {
+	HL7800_STATE_NOT_READY = 0,
+	HL7800_STATE_INITIALIZED,
 };
 
 enum mdm_hl7800_startup_state {
@@ -227,25 +233,26 @@ struct mdm_hl7800_polte_location_data {
 
 /**
  * event - The type of event
- * event_data - Pointer to event specific data structure
- * HL7800_EVENT_NETWORK_STATE_CHANGE - compound event
+ * event_data - Pointer to event specific data structure:
+ * HL7800_EVENT_NETWORK_STATE_CHANGE - mdm_hl7800_compound_event
  * HL7800_EVENT_APN_UPDATE - struct mdm_hl7800_apn
  * HL7800_EVENT_RSSI - int
  * HL7800_EVENT_SINR - int
- * HL7800_EVENT_STARTUP_STATE_CHANGE - compound event
- * HL7800_EVENT_SLEEP_STATE_CHANGE - compound event
+ * HL7800_EVENT_STARTUP_STATE_CHANGE - mdm_hl7800_compound_event
+ * HL7800_EVENT_SLEEP_STATE_CHANGE - mdm_hl7800_compound_event
  * HL7800_EVENT_RAT - int
  * HL7800_EVENT_BANDS - string
  * HL7800_EVENT_ACTIVE_BANDS - string
- * HL7800_EVENT_FOTA_STATE - compound event
+ * HL7800_EVENT_FOTA_STATE - mdm_hl7800_compound_event
  * HL7800_EVENT_FOTA_COUNT - uint32_t
  * HL7800_EVENT_REVISION - string
- * HL7800_EVENT_GPS - compound event
+ * HL7800_EVENT_GPS - mdm_hl7800_compound_event
  * HL7800_EVENT_GPS_POSITION_STATUS int
  * HL7800_EVENT_POLTE_REGISTRATION mdm_hl7800_polte_registration_event_data
  * HL7800_EVENT_POLTE mdm_hl7800_polte_location_data
  * HL7800_EVENT_POLTE_LOCATE_STATUS int
  * HL7800_EVENT_SITE_SURVEY mdm_hl7800_site_survey
+ * HL7800_EVENT_STATE mdm_hl7800_compound_event
  */
 typedef void (*mdm_hl7800_event_callback_t)(enum mdm_hl7800_event event,
 					    void *event_data);
@@ -265,7 +272,7 @@ int32_t mdm_hl7800_power_off(void);
 /**
  * @brief Reset the HL7800 (and allow it to reconfigure).
  *
- * @return int32_t 0 for success
+ * @return int32_t >= 0 for success, < 0 for failure
  */
 int32_t mdm_hl7800_reset(void);
 
@@ -279,12 +286,18 @@ void mdm_hl7800_wakeup(bool awake);
 
 /**
  * @brief Send an AT command to the HL7800.
- * @note this API should only be used for debug purposes.
+ * @note This API should only be used for debug purposes.
+ *   It is possible to break the driver using this API.
  *
  * @param data AT command string
+ * @param resp_timeout Timeout in seconds to wait for the response
+ * @param resp Pointer to the response buffer. This can be NULL to ignore the response.
+ * @param resp_len Input: length of the response buffer, Output: length of the response.
+ *   This can be NULL.
  * @return int32_t 0 for success
  */
-int32_t mdm_hl7800_send_at_cmd(const uint8_t *data);
+int32_t mdm_hl7800_send_at_cmd(const uint8_t *data, uint8_t resp_timeout, char *resp,
+			       uint16_t *resp_len);
 
 /**
  * @brief Get the signal quality of the HL7800.
diff --git a/include/zephyr/drivers/pinctrl/pinctrl_soc_bflb_common.h b/include/zephyr/drivers/pinctrl/pinctrl_soc_bflb_common.h
new file mode 100644
index 00000000000..7d7404ff75e
--- /dev/null
+++ b/include/zephyr/drivers/pinctrl/pinctrl_soc_bflb_common.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * Bouffalo Lab SoC specific helpers for pinctrl driver
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_BFLB_COMMON_H_
+#define ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_BFLB_COMMON_H_
+
+#include <zephyr/devicetree.h>
+#include <zephyr/types.h>
+
+/* clang-format off */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @cond INTERNAL_HIDDEN */
+
+/**
+ * @brief BFLB pincfg bit field.
+ * @anchor BFLB_PINMUX
+ *
+ * Fields:
+ *
+ * - 24..31: pin
+ * - 20..23: signal
+ * - 18..19: mode
+ * - 16..17: instance
+ * -  8..15: function
+ * -      7: reserved
+ * -      6: GPIO Output Enable
+ * -      5: Pull Down
+ * -      4: Pull Up
+ * -   2..3: Driver Strength
+ * -      1: Schmitt trigger (SMT)
+ * -      0: reserved
+ */
+typedef uint32_t pinctrl_soc_pin_t;
+
+/**
+ * @brief Utility macro to initialize each pin.
+ *
+ * @param node_id Node identifier.
+ * @param prop Property name.
+ * @param idx Property entry index.
+ */
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx)						\
+	((DT_PROP_BY_IDX(node_id, prop, idx))							\
+	 | (DT_PROP(node_id, bias_pull_up)              << BFLB_PINMUX_PULL_UP_POS)		\
+	 | (DT_PROP(node_id, bias_pull_down)            << BFLB_PINMUX_PULL_DOWN_POS)		\
+	 | (DT_PROP(node_id, output_enable)             << BFLB_PINMUX_OE_POS)			\
+	 | (DT_PROP(node_id, input_schmitt_enable)      << BFLB_PINMUX_SMT_POS)			\
+	 | (DT_ENUM_IDX(node_id, drive_strength)        << BFLB_PINMUX_DRIVER_STRENGTH_POS)	\
+	),
+
+/**
+ * @brief Utility macro to initialize state pins contained in a given property.
+ *
+ * @param node_id Node identifier.
+ * @param prop Property name describing state pins.
+ */
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)			       \
+	{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop),		       \
+				DT_FOREACH_PROP_ELEM, pinmux,	               \
+				Z_PINCTRL_STATE_PIN_INIT)}
+
+/** @endcond */
+
+#ifdef __cplusplus
+}
+#endif
+
+/* clang-format on */
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_PINCTRL_PINCTRL_SOC_BFLB_COMMON_H_ */
diff --git a/include/zephyr/drivers/regulator/fake.h b/include/zephyr/drivers/regulator/fake.h
index d91161dbc7a..c52d35a56e7 100644
--- a/include/zephyr/drivers/regulator/fake.h
+++ b/include/zephyr/drivers/regulator/fake.h
@@ -23,6 +23,9 @@ DECLARE_FAKE_VALUE_FUNC(int, regulator_fake_set_voltage, const struct device *,
 			int32_t, int32_t);
 DECLARE_FAKE_VALUE_FUNC(int, regulator_fake_get_voltage, const struct device *,
 			int32_t *);
+DECLARE_FAKE_VALUE_FUNC(unsigned int, regulator_fake_count_current_limits, const struct device *);
+DECLARE_FAKE_VALUE_FUNC(int, regulator_fake_list_current_limit, const struct device *, unsigned int,
+			int32_t *);
 DECLARE_FAKE_VALUE_FUNC(int, regulator_fake_set_current_limit,
 			const struct device *, int32_t, int32_t);
 DECLARE_FAKE_VALUE_FUNC(int, regulator_fake_get_current_limit,
diff --git a/include/zephyr/drivers/sensor.h b/include/zephyr/drivers/sensor.h
index cf1f2961731..af8651886d0 100644
--- a/include/zephyr/drivers/sensor.h
+++ b/include/zephyr/drivers/sensor.h
@@ -156,6 +156,9 @@ enum sensor_channel {
 	/** Revolutions per minute, in RPM. */
 	SENSOR_CHAN_RPM,
 
+	/** Frequency, in Hz. */
+	SENSOR_CHAN_FREQUENCY,
+
 	/** Voltage, in volts **/
 	SENSOR_CHAN_GAUGE_VOLTAGE,
 	/** Average current, in amps **/
@@ -1205,6 +1208,25 @@ static inline void sensor_g_to_ms2(int32_t g, struct sensor_value *ms2)
 	ms2->val2 = ((int64_t)g * SENSOR_G) % 1000000LL;
 }
 
+/**
+ * @brief Helper function to convert acceleration from m/s^2 to milli Gs
+ *
+ * @param ms2 A pointer to a sensor_value struct holding the acceleration,
+ *            in m/s^2.
+ *
+ * @return The converted value, in milli Gs.
+ */
+static inline int32_t sensor_ms2_to_mg(const struct sensor_value *ms2)
+{
+	int64_t nano_ms2 = (ms2->val1 * 1000000LL + ms2->val2) * 1000LL;
+
+	if (nano_ms2 > 0) {
+		return (nano_ms2 + SENSOR_G / 2) / SENSOR_G;
+	} else {
+		return (nano_ms2 - SENSOR_G / 2) / SENSOR_G;
+	}
+}
+
 /**
  * @brief Helper function to convert acceleration from m/s^2 to micro Gs
  *
@@ -1446,6 +1468,28 @@ struct sensor_info {
 #define SENSOR_DEVICE_DT_INST_DEFINE(inst, ...)				\
 	SENSOR_DEVICE_DT_DEFINE(DT_DRV_INST(inst), __VA_ARGS__)
 
+/**
+ * @brief Helper function for converting struct sensor_value to integer deci units.
+ *
+ * @param val A pointer to a sensor_value struct.
+ * @return The converted value.
+ */
+static inline int64_t sensor_value_to_deci(const struct sensor_value *val)
+{
+	return ((int64_t)val->val1 * 10) + val->val2 / 100000;
+}
+
+/**
+ * @brief Helper function for converting struct sensor_value to integer centi units.
+ *
+ * @param val A pointer to a sensor_value struct.
+ * @return The converted value.
+ */
+static inline int64_t sensor_value_to_centi(const struct sensor_value *val)
+{
+	return ((int64_t)val->val1 * 100) + val->val2 / 10000;
+}
+
 /**
  * @brief Helper function for converting struct sensor_value to integer milli units.
  *
diff --git a/include/zephyr/drivers/sensor/adltc2990.h b/include/zephyr/drivers/sensor/adltc2990.h
new file mode 100644
index 00000000000..a13fe5c5d51
--- /dev/null
+++ b/include/zephyr/drivers/sensor/adltc2990.h
@@ -0,0 +1,41 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2024 Jilay Sandeep Pandya
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_ADLTC2990_H_
+#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_ADLTC2990_H_
+
+#include <stdbool.h>
+
+#include <zephyr/device.h>
+
+enum adltc2990_acquisition_format {
+	ADLTC2990_REPEATED_ACQUISITION,
+	ADLTC2990_SINGLE_SHOT_ACQUISITION,
+};
+
+/**
+ * @brief check if adtlc2990 is busy doing conversion
+ *
+ * @param dev Pointer to the adltc2990 device
+ * @param is_busy Pointer to the variable to store the busy status
+ *
+ * @retval 0 if successful
+ * @retval -EIO General input / output error.
+ */
+int adltc2990_is_busy(const struct device *dev, bool *is_busy);
+
+/**
+ * @brief Trigger the adltc2990 to start a measurement
+ *
+ * @param dev Pointer to the adltc2990 device
+ * @param format The acquisition format to be used
+ *
+ * @retval 0 if successful
+ * @retval -EIO General input / output error.
+ */
+int adltc2990_trigger_measurement(const struct device *dev,
+				  enum adltc2990_acquisition_format format);
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_ADLTC2990_H_ */
diff --git a/include/zephyr/drivers/sensor/battery.h b/include/zephyr/drivers/sensor/battery.h
index 6158141922c..e221651895c 100644
--- a/include/zephyr/drivers/sensor/battery.h
+++ b/include/zephyr/drivers/sensor/battery.h
@@ -19,8 +19,9 @@ extern "C" {
 #endif
 
 /**
- * @brief battery API
- * @defgroup battery_apis battery APIs
+ * @brief Battery API
+ * @defgroup battery_apis Battery APIs
+ * @ingroup sensor_interface
  * @{
  */
 
diff --git a/include/zephyr/drivers/sensor/icm42670.h b/include/zephyr/drivers/sensor/icm42670.h
deleted file mode 100644
index 9894109fd75..00000000000
--- a/include/zephyr/drivers/sensor/icm42670.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Copyright (c) 2024 TDK Invensense
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_ICM42670_H_
-#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_ICM42670_H_
-
-#include <zephyr/drivers/sensor.h>
-
-/**
- * @file
- * @brief Extended public API for ICM42670 6-axis MEMS sensor
- *
- * Some capabilities and operational requirements for this sensor
- * cannot be expressed within the sensor driver abstraction.
- */
-
-/** ICM42670 power mode */
-#define ICM42670_LOW_NOISE_MODE (0)
-#define ICM42670_LOW_POWER_MODE (1)
-
-/**
- * @brief Extended sensor attributes for ICM42670 6-axis MEMS sensor
- *
- * This exposes attributes for the ICM42670 which can be used for
- * setting the signal path filtering parameters.
- *
- * The signal path starts with ADCs for the gyroscope and accelerometer.
- * Low-Noise Mode and Low-Power Mode options are available for the
- * accelerometer. Only Low-Noise Mode is available for gyroscope.
- * In Low-Noise Mode, the ADC output is sent through an Anti-Alias Filter
- * (AAF). The AAF is a filter with fixed coefficients (not user configurable),
- * also the AAF cannot be bypassed. The AAF is followed by a 1st Order Low Pass
- * Filter (LPF) with user selectable filter bandwidth options.
- * In Low-Power Mode, the accelerometer ADC output is sent through an Average
- * filter, with user configurable average filter setting.
- * The output of 1st Order LPF in Low-Noise Mode, or Average filter in Low-Power
- * Mode is subject to ODR selection, with user selectable ODR.
- */
-enum sensor_attribute_icm42670 {
-	/** BW filtering */
-
-	/** Low-pass filter configuration */
-	SENSOR_ATTR_BW_FILTER_LPF = SENSOR_ATTR_PRIV_START,
-	/** Averaging configuration */
-	SENSOR_ATTR_AVERAGING,
-};
-#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_ICM42670_H_ */
diff --git a/include/zephyr/drivers/sensor/icm42x70.h b/include/zephyr/drivers/sensor/icm42x70.h
new file mode 100644
index 00000000000..06c2c1ae396
--- /dev/null
+++ b/include/zephyr/drivers/sensor/icm42x70.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2024 TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_ICM42X70_H_
+#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_ICM42X70_H_
+
+#include <zephyr/drivers/sensor.h>
+
+/**
+ * @file
+ * @brief Extended public API for ICM42X70 MEMS sensor
+ *
+ * Some capabilities and operational requirements for this sensor
+ * cannot be expressed within the sensor driver abstraction.
+ */
+
+/** ICM42X70 power mode */
+#define ICM42X70_LOW_NOISE_MODE (0)
+#define ICM42X70_LOW_POWER_MODE (1)
+
+/**
+ * @brief Extended sensor attributes for ICM42X70 MEMS sensor
+ *
+ * This exposes attributes for the ICM42X70 which can be used for
+ * setting the signal path filtering parameters.
+ *
+ * The signal path starts with ADCs for the gyroscope and accelerometer.
+ * Low-Noise Mode and Low-Power Mode options are available for the
+ * accelerometer. Only Low-Noise Mode is available for gyroscope.
+ * In Low-Noise Mode, the ADC output is sent through an Anti-Alias Filter
+ * (AAF). The AAF is a filter with fixed coefficients (not user configurable),
+ * also the AAF cannot be bypassed. The AAF is followed by a 1st Order Low Pass
+ * Filter (LPF) with user selectable filter bandwidth options.
+ * In Low-Power Mode, the accelerometer ADC output is sent through an Average
+ * filter, with user configurable average filter setting.
+ * The output of 1st Order LPF in Low-Noise Mode, or Average filter in Low-Power
+ * Mode is subject to ODR selection, with user selectable ODR.
+ */
+enum sensor_attribute_icm42x70 {
+	/** BW filtering */
+
+	/** Low-pass filter configuration */
+	SENSOR_ATTR_BW_FILTER_LPF = SENSOR_ATTR_PRIV_START,
+	/** Averaging configuration */
+	SENSOR_ATTR_AVERAGING,
+};
+#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_ICM42X70_H_ */
diff --git a/include/zephyr/drivers/sensor/mlx90394.h b/include/zephyr/drivers/sensor/mlx90394.h
new file mode 100644
index 00000000000..ea545bfa450
--- /dev/null
+++ b/include/zephyr/drivers/sensor/mlx90394.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2024 Florian Weber <Florian.Weber@live.de>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Extended public API for Melexis mlx90394 Sensor
+ *
+ * Some capabilities and operational requirements for this sensor
+ * cannot be expressed within the sensor driver abstraction.
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_MLX90394_H_
+#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_MLX90394_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <zephyr/drivers/sensor.h>
+
+enum mlx90394_sensor_attribute {
+	MLX90394_SENSOR_ATTR_MAGN_LOW_NOISE = SENSOR_ATTR_PRIV_START,
+	MLX90394_SENSOR_ATTR_MAGN_FILTER_XY,
+	MLX90394_SENSOR_ATTR_MAGN_FILTER_Z,
+	MLX90394_SENSOR_ATTR_MAGN_OSR,
+	MLX90394_SENSOR_ATTR_TEMP_FILTER,
+	MLX90394_SENSOR_ATTR_TEMP_OSR
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_MLX90394_H_ */
diff --git a/include/zephyr/drivers/sensor/paj7620.h b/include/zephyr/drivers/sensor/paj7620.h
new file mode 100644
index 00000000000..125d77d58dd
--- /dev/null
+++ b/include/zephyr/drivers/sensor/paj7620.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2025 Paul Timke <ptimkec@live.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Extended Public API for PAJ7620 sensor
+ *
+ * Some capabilities of the sensor cannot be expressed
+ * within the sensor driver abstraction
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_PAJ7620_H_
+#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_PAJ7620_H_
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+#include <zephyr/drivers/sensor.h>
+
+#define PAJ7620_FLAG_GES_UP               BIT(0)
+#define PAJ7620_FLAG_GES_DOWN             BIT(1)
+#define PAJ7620_FLAG_GES_LEFT             BIT(2)
+#define PAJ7620_FLAG_GES_RIGHT            BIT(3)
+#define PAJ7620_FLAG_GES_FORWARD          BIT(4)
+#define PAJ7620_FLAG_GES_BACKWARD         BIT(5)
+#define PAJ7620_FLAG_GES_CLOCKWISE        BIT(6)
+#define PAJ7620_FLAG_GES_COUNTERCLOCKWISE BIT(7)
+#define PAJ7620_FLAG_GES_WAVE             BIT(8)
+
+enum sensor_channel_paj7620 {
+	/**
+	 * This channel will contain gesture data as a bitmask where each
+	 * set bit represents a detected gesture. The possible gestures
+	 * that can be detected along with their corresponding bit are given
+	 * by the PAJ7620_FLAG_GES_X macros
+	 */
+	SENSOR_CHAN_PAJ7620_GESTURES = SENSOR_CHAN_PRIV_START
+};
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_PAJ7620_H_ */
diff --git a/include/zephyr/drivers/sensor/pat9136.h b/include/zephyr/drivers/sensor/pat9136.h
new file mode 100644
index 00000000000..a88de369d76
--- /dev/null
+++ b/include/zephyr/drivers/sensor/pat9136.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_PAT9136_H_
+#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_PAT9136_H_
+
+#include <zephyr/drivers/sensor.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** This sensor does have the ability to provide DXY in meaningful units, and
+ * since the standard channels' unit is in points (SENSOR_CHAN_POS_DX,
+ * SENSOR_CHAN_POS_DY, SENSOR_CHAN_POS_DXYZ), we've captured the following
+ * channels to provide an alternative for this sensor.
+ */
+enum sensor_channel_pat9136 {
+	/** Position change on the X axis, in millimeters. */
+	SENSOR_CHAN_POS_DX_MM = SENSOR_CHAN_PRIV_START + 1,
+	/** Position change on the Y axis, in millimeters. */
+	SENSOR_CHAN_POS_DY_MM,
+	/** Position change on the X, Y and Z axis, in millimeters.
+	 * Added additional offset so the channels X and Y can be accessed
+	 * relative to XYZ in spite of not supporting DZ.
+	 */
+	SENSOR_CHAN_POS_DXYZ_MM = SENSOR_CHAN_POS_DY_MM + 2,
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_PAT9136_H_ */
diff --git a/include/zephyr/drivers/sensor/tmp116.h b/include/zephyr/drivers/sensor/tmp116.h
deleted file mode 100644
index 5efb4ad252a..00000000000
--- a/include/zephyr/drivers/sensor/tmp116.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (c) 2021 Innoseis B.V
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_TMP116_H_
-#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_TMP116_H_
-
-#include <zephyr/device.h>
-#include <zephyr/drivers/sensor.h>
-#include <sys/types.h>
-
-enum sensor_attribute_tmp_116 {
-	/** Turn on power saving/one shot mode */
-	SENSOR_ATTR_TMP116_ONE_SHOT_MODE = SENSOR_ATTR_PRIV_START,
-	/** Shutdown the sensor */
-	SENSOR_ATTR_TMP116_SHUTDOWN_MODE,
-	/** Turn on continuous conversion */
-	SENSOR_ATTR_TMP116_CONTINUOUS_CONVERSION_MODE,
-};
-
-#define EEPROM_TMP116_SIZE (4 * sizeof(uint16_t))
-
-int tmp116_eeprom_read(const struct device *dev, off_t offset, void *data,
-		       size_t len);
-
-int tmp116_eeprom_write(const struct device *dev, off_t offset,
-			const void *data, size_t len);
-
-#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_TMP116_H_ */
diff --git a/include/zephyr/drivers/sensor/tmp11x.h b/include/zephyr/drivers/sensor/tmp11x.h
new file mode 100644
index 00000000000..10d0b24865d
--- /dev/null
+++ b/include/zephyr/drivers/sensor/tmp11x.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2021 Innoseis B.V
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_TMP11X_H_
+#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_TMP11X_H_
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/sensor.h>
+#include <sys/types.h>
+
+enum sensor_attribute_tmp_11x {
+	/** Turn on power saving/one shot mode */
+	SENSOR_ATTR_TMP11X_ONE_SHOT_MODE = SENSOR_ATTR_PRIV_START,
+	/** Shutdown the sensor */
+	SENSOR_ATTR_TMP11X_SHUTDOWN_MODE,
+	/** Turn on continuous conversion */
+	SENSOR_ATTR_TMP11X_CONTINUOUS_CONVERSION_MODE,
+};
+
+#define EEPROM_TMP11X_SIZE (4 * sizeof(uint16_t))
+
+int tmp11x_eeprom_read(const struct device *dev, off_t offset, void *data,
+		       size_t len);
+
+int tmp11x_eeprom_write(const struct device *dev, off_t offset,
+			const void *data, size_t len);
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_TMP11X_H_ */
diff --git a/include/zephyr/drivers/sensor/vl53l0x.h b/include/zephyr/drivers/sensor/vl53l0x.h
new file mode 100644
index 00000000000..98613f16f31
--- /dev/null
+++ b/include/zephyr/drivers/sensor/vl53l0x.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2024 Michal Piekos
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Custom channels and values for VL53L0X ToF Sensor
+ *
+ * These channels provide additional sensor data not covered by the standard
+ * Zephyr sensor channels. Application must include vl53l0x.h file to gain
+ * access to these channels.
+ *
+ * Example usage:
+ * @code{c}
+ * #include <zephyr/drivers/sensor/vl53l0x.h>
+ *
+ * if (sensor_channel_get(dev, SENSOR_CHAN_VL53L0X_RANGE_STATUS, &value)) {
+ *	printk("Status: %d\n", value.val1);
+ * }
+ * @endcode
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_VL53L0X_H_
+#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_VL53L0X_H_
+
+#include <zephyr/drivers/sensor.h>
+
+/* VL53L0x specific channels */
+enum sensor_channel_vl53l0x {
+	SENSOR_CHAN_VL53L0X_RANGE_DMAX = SENSOR_CHAN_PRIV_START,
+	SENSOR_CHAN_VL53L0X_SIGNAL_RATE_RTN_CPS,
+	SENSOR_CHAN_VL53L0X_AMBIENT_RATE_RTN_CPS,
+	SENSOR_CHAN_VL53L0X_EFFECTIVE_SPAD_RTN_COUNT,
+	SENSOR_CHAN_VL53L0X_RANGE_STATUS,
+};
+
+/* VL53L0x meas status values */
+#define VL53L0X_RANGE_STATUS_RANGE_VALID    (0)
+#define VL53L0X_RANGE_STATUS_SIGMA_FAIL	    (1)
+#define VL53L0X_RANGE_STATUS_SIGNAL_FAIL    (2)
+#define VL53L0X_RANGE_STATUS_MIN_RANGE_FAIL (3)
+#define VL53L0X_RANGE_STATUS_PHASE_FAIL	    (4)
+#define VL53L0X_RANGE_STATUS_HARDWARE_FAIL  (5)
+#define VL53L0X_RANGE_STATUS_NO_UPDATE      (255)
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_VL53L0X_H_ */
diff --git a/include/zephyr/drivers/sensor/wsen_pads_2511020213301.h b/include/zephyr/drivers/sensor/wsen_pads_2511020213301.h
new file mode 100644
index 00000000000..44c08e6e1a7
--- /dev/null
+++ b/include/zephyr/drivers/sensor/wsen_pads_2511020213301.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Extended public API for WSEN-PADS-2511020213301 Sensor
+ *
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_WSEN_PADS_2511020213301_H_
+#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_WSEN_PADS_2511020213301_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <zephyr/drivers/sensor.h>
+
+enum sensor_attribute_wsen_pads_2511020213301 {
+	SENSOR_ATTR_WSEN_PADS_2511020213301_REFERENCE_POINT = SENSOR_ATTR_PRIV_START,
+};
+
+#ifdef CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD
+enum sensor_trigger_wsen_pads_2511020213301 {
+	SENSOR_TRIG_WSEN_PADS_2511020213301_THRESHOLD_UPPER = SENSOR_TRIG_PRIV_START,
+	SENSOR_TRIG_WSEN_PADS_2511020213301_THRESHOLD_LOWER,
+};
+#endif /* CONFIG_WSEN_PADS_2511020213301_PRESSURE_THRESHOLD */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_WSEN_PADS_2511020213301_H_ */
diff --git a/include/zephyr/drivers/sensor/wsen_tids_2521020222501.h b/include/zephyr/drivers/sensor/wsen_tids_2521020222501.h
new file mode 100644
index 00000000000..64eb1f48fa0
--- /dev/null
+++ b/include/zephyr/drivers/sensor/wsen_tids_2521020222501.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Extended public API for WSEN-TIDS-2521020222501 Sensor
+ *
+ */
+
+#ifndef ZEPHYR_INCLUDE_DRIVERS_SENSOR_WSEN_TIDS_2521020222501_H_
+#define ZEPHYR_INCLUDE_DRIVERS_SENSOR_WSEN_TIDS_2521020222501_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <zephyr/drivers/sensor.h>
+
+enum sensor_trigger_wsen_tids_2521020222501 {
+	SENSOR_TRIG_WSEN_TIDS_2521020222501_THRESHOLD_UPPER = SENSOR_TRIG_PRIV_START,
+	SENSOR_TRIG_WSEN_TIDS_2521020222501_THRESHOLD_LOWER,
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_SENSOR_WSEN_TIDS_2521020222501_H_ */
diff --git a/include/zephyr/drivers/sensor_clock.h b/include/zephyr/drivers/sensor_clock.h
new file mode 100644
index 00000000000..8a67ce0a3c9
--- /dev/null
+++ b/include/zephyr/drivers/sensor_clock.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2024 Cienet
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_DRIVERS_SENSOR_CLOCK_H_
+#define ZEPHYR_DRIVERS_SENSOR_CLOCK_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Retrieve the current sensor clock cycles.
+ *
+ * This function obtains the current cycle count from the selected
+ * sensor clock source. The clock source may be the system clock or
+ * an external clock, depending on the configuration.
+ *
+ * @param[out] cycles Pointer to a 64-bit unsigned integer where the
+ *                    current clock cycle count will be stored.
+ *
+ * @return 0 on success, or an error code on failure.
+ */
+int sensor_clock_get_cycles(uint64_t *cycles);
+
+/**
+ * @brief Convert clock cycles to nanoseconds.
+ *
+ * This function converts clock cycles into nanoseconds based on the
+ * clock frequency.
+ *
+ * @param cycles Clock cycles to convert.
+ * @return Time in nanoseconds.
+ */
+uint64_t sensor_clock_cycles_to_ns(uint64_t cycles);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_DRIVERS_SENSOR_CLOCK_H_ */
diff --git a/include/zephyr/drivers/smbus.h b/include/zephyr/drivers/smbus.h
index f0642d6d837..de197becbc2 100644
--- a/include/zephyr/drivers/smbus.h
+++ b/include/zephyr/drivers/smbus.h
@@ -510,7 +510,7 @@ static inline void smbus_xfer_stats(const struct device *dev, uint8_t sent,
 	Z_DEVICE_DEFINE(node_id, Z_DEVICE_DT_DEV_NAME(node_id),		\
 			DEVICE_DT_NAME(node_id),			\
 			&UTIL_CAT(Z_DEVICE_DT_DEV_NAME(node_id), _init),\
-			pm_device,					\
+			NULL, Z_DEVICE_DT_FLAGS(node_id), pm_device,	\
 			data_ptr, cfg_ptr, level, prio,			\
 			api_ptr,					\
 			&(Z_DEVICE_STATE_NAME(Z_DEVICE_DT_DEV_NAME	\
diff --git a/include/zephyr/drivers/spi.h b/include/zephyr/drivers/spi.h
index c9aaf38c720..8e8cdb5a994 100644
--- a/include/zephyr/drivers/spi.h
+++ b/include/zephyr/drivers/spi.h
@@ -39,98 +39,176 @@ extern "C" {
  * @name SPI operational mode
  * @{
  */
-#define SPI_OP_MODE_MASTER	0U      /**< Master mode. */
+
+/**
+ * @brief Master (controller) mode.
+ *
+ * In this case the device used with the API will function as a controller,
+ * meaning it will control the CLK line on the SPI bus and the chip select,
+ * and therefore have full control over the timing of the transaction.
+ */
+#define SPI_OP_MODE_MASTER	0U
+
+/**
+ * @brief Slave (peripheral) mode.
+ *
+ * With this mode, the device will function as a peripheral,
+ * meaning it will need to wait for it's select line to be asserted,
+ * and will be need to be subject to pacing by a controller's clock in order to
+ * send and receive data during a transaction.
+ */
 #define SPI_OP_MODE_SLAVE	BIT(0)  /**< Slave mode. */
+
 /** @cond INTERNAL_HIDDEN */
 #define SPI_OP_MODE_MASK	0x1U
 /** @endcond */
-/** Get SPI operational mode. */
+
+/**
+ * @brief Get SPI Operational mode bitmask from a @ref spi_operation_t
+ */
 #define SPI_OP_MODE_GET(_operation_) ((_operation_) & SPI_OP_MODE_MASK)
 /** @} */
 
+
 /**
- * @name SPI Polarity & Phase Modes
+ * @name SPI Clock Modes
  * @{
  */
 
 /**
- * Clock Polarity: if set, clock idle state will be 1
- * and active state will be 0. If untouched, the inverse will be true
- * which is the default.
+ * @brief Clock Polarity (Clock Idle State)
+ *
+ * @details
+ * Used in @ref spi_operation_t definition.
+ * If set, clock idle state will be 1 and active state will be 0.
+ * If unset, clock idle state will be 0 and active state will be 1.
+ * Unset is the default.
  */
 #define SPI_MODE_CPOL		BIT(1)
 
 /**
- * Clock Phase: this dictates when is the data captured, and depends
- * clock's polarity. When SPI_MODE_CPOL is set and this bit as well,
- * capture will occur on low to high transition and high to low if
- * this bit is not set (default). This is fully reversed if CPOL is
- * not set.
+ * @brief Clock Phase (Clock data capture edge)
+ *
+ * @details
+ * Used in @ref spi_operation_t definition.
+ * If set, data is captured on transition from active to idle CLK state.
+ * If unset, data is captured on transition from idle to active state.
+ * Unset is the default.
  */
 #define SPI_MODE_CPHA		BIT(2)
 
 /**
- * Whatever data is transmitted is looped-back to the receiving buffer of
- * the controller. This is fully controller dependent as some may not
- * support this, and can be used for testing purposes only.
+ * @brief Controller loopback mode
+ *
+ * @details
+ * For testing purposes, enable hardware loopback,
+ * which means that transmit data is fed back to the receiver of the same controller.
+ *
+ * Not all controllers support this feature.
  */
 #define SPI_MODE_LOOP		BIT(3)
+
 /** @cond INTERNAL_HIDDEN */
 #define SPI_MODE_MASK		(0xEU)
 /** @endcond */
-/** Get SPI polarity and phase mode bits. */
+
+/**
+ * @brief Get SPI clock polarity and phase mode bitmask from a @ref spi_operation_t
+ */
 #define SPI_MODE_GET(_mode_)			\
 	((_mode_) & SPI_MODE_MASK)
 
 /** @} */
 
-/**
- * @name SPI Transfer modes (host controller dependent)
- * @{
- */
-#define SPI_TRANSFER_MSB	(0U)    /**< Most significant bit first. */
-#define SPI_TRANSFER_LSB	BIT(4)  /**< Least significant bit first. */
-/** @} */
 
 /**
- * @name SPI word size
+ * @name SPI Data Word Configurations
+ *
+ * A SPI Data word is a value that is shifted in/out of the controller's hardware FIFO
+ * and is the atomic unit of communication on the spi bus.
+ * A word is also called a "data frame" in this API.
+ * A transfer is made up of an arbitrary number of words.
+ * The following options specify configurations of the SPI word for the operation.
+ *
  * @{
  */
+
+/** Words are most significant bit first, used for @ref spi_operation_t */
+#define SPI_TRANSFER_MSB	(0U)
+/** Words are least significant bit first, used for @ref spi_operation_t */
+#define SPI_TRANSFER_LSB	BIT(4)
+
 /** @cond INTERNAL_HIDDEN */
 #define SPI_WORD_SIZE_SHIFT	(5U)
 #define SPI_WORD_SIZE_MASK	(0x3FU << SPI_WORD_SIZE_SHIFT)
 /** @endcond */
-/** Get SPI word size (data frame size) in bits. */
-#define SPI_WORD_SIZE_GET(_operation_)					\
-	(((_operation_) & SPI_WORD_SIZE_MASK) >> SPI_WORD_SIZE_SHIFT)
-/** Set SPI word size (data frame size) in bits. */
-#define SPI_WORD_SET(_word_size_)		\
-	((_word_size_) << SPI_WORD_SIZE_SHIFT)
+
+/**
+ * @brief Get SPI word size in bits from a @ref spi_operation_t
+ *
+ * @param operation A @ref spi_operation_t from which to get the configured word size.
+ * @retval The size (in bits) of a spi word for the operation.
+ */
+#define SPI_WORD_SIZE_GET(operation)					\
+	(((operation) & SPI_WORD_SIZE_MASK) >> SPI_WORD_SIZE_SHIFT)
+
+/**
+ * @brief Get a bitmask to set the word size in a @ref spi_operation_t
+ *
+ * @param word_size The size of a SPI data frame in bits.
+ * @retval A bitmask to apply to a @ref spi_operation_t
+ */
+#define SPI_WORD_SET(word_size)			\
+	((word_size) << SPI_WORD_SIZE_SHIFT)
+
 /** @} */
 
+
 /**
- * @name Specific SPI devices control bits
+ * @name SPI Transfer control flags
  * @{
  */
-/** Requests - if possible - to keep CS asserted after the transaction */
+
+/**
+ * @brief Keep chip select active after transaction
+ *
+ * After one of the spi transceive calls described in this API,
+ * if this flag is set in the spi config operation, then
+ * attempt to keep the CS active after the call, if supported and possible.
+ */
 #define SPI_HOLD_ON_CS		BIT(12)
-/** Keep the device locked after the transaction for the current config.
- * Use this with extreme caution (see spi_release() below) as it will
- * prevent other callers to access the SPI device until spi_release() is
- * properly called.
+
+/**
+ * @brief Retain ownership of the spi device
+ *
+ * This is a software control parameter that will prevent the spi device
+ * from being accessed by other API callers after the transaction,
+ * and therefore should be used with caution.
+ *
+ * The identifying piece of information for who "locks" the device
+ * is the spi_config pointer given to the transaction API, so this same
+ * config should be re-used to do another transaction or release the lock.
+ *
+ * See @ref spi_release for how to release the  lock.
  */
 #define SPI_LOCK_ON		BIT(13)
 
-/** Active high logic on CS. Usually, and by default, CS logic is active
- * low. However, some devices may require the reverse logic: active high.
- * This bit will request the controller to use that logic. Note that not
- * all controllers are able to handle that natively. In this case deferring
- * the CS control to a gpio line through struct spi_cs_control would be
- * the solution.
+/**
+ * @brief Chip select active state configuration
+ *
+ * If this flag is set, the CS will be active high.
+ * If this flag is unset, the CS will be active low.
+ *
+ * Default is active low (unset) as that is most common for spi peripherals.
+ *
+ * Not all controllers are able to handle this natively, in which case a
+ * gpio can still be used to control the CS through software with a @ref spi_cs_control
  */
 #define SPI_CS_ACTIVE_HIGH	BIT(14)
+
 /** @} */
 
+
 /**
  * @name SPI MISO lines
  * @{
@@ -149,11 +227,16 @@ extern "C" {
 
 /** @} */
 
+/**
+ * @name SPI GPIO Chip Select control
+ * @{
+ */
+
 /**
  * @brief SPI Chip Select control structure
  *
  * This can be used to control a CS line via a GPIO line, instead of
- * using the controller inner CS logic.
+ * using the controller internal CS logic.
  *
  */
 struct spi_cs_control {
@@ -285,6 +368,8 @@ struct spi_cs_control {
 #define SPI_CS_CONTROL_INIT_INST(inst, delay_)		\
 	SPI_CS_CONTROL_INIT(DT_DRV_INST(inst), delay_)
 
+/** @} */
+
 /**
  * @typedef spi_operation_t
  * Opaque type to hold the SPI operation flags.
@@ -297,6 +382,10 @@ typedef uint16_t spi_operation_t;
 
 /**
  * @brief SPI controller configuration structure
+ *
+ * @warning Most drivers use pointer comparison to determine whether a passed
+ * configuration is different from one used in a previous transaction.
+ * Changes to fields in the structure may not be detected.
  */
 struct spi_config {
 	/** @brief Bus frequency in Hertz. */
@@ -307,7 +396,7 @@ struct spi_config {
 	 * It is a bit field with the following parts:
 	 *
 	 * - 0:      Master or slave.
-	 * - 1..3:   Polarity, phase and loop mode.
+	 * - 1..3:   Clock polarity, phase and loop mode.
 	 * - 4:      LSB or MSB first.
 	 * - 5..10:  Size of a data frame (word) in bits.
 	 * - 11:     Full/half duplex.
@@ -454,27 +543,41 @@ struct spi_dt_spec {
 
 /**
  * @brief SPI buffer structure
+ *
+ * A SPI buffer describes either a real data buffer or an indication of NOP
+ * For a NOP indicator:
+ *   If buffer is used for TX, only 0's will be sent for the length on the bus
+ *   If buffer is used for RX, that length of data received by bus will be ignored/skipped
  */
 struct spi_buf {
-	/** Valid pointer to a data buffer, or NULL otherwise */
+	/** Valid pointer to a data buffer, or NULL for NOP indication */
 	void *buf;
-	/** Length of the buffer @a buf in bytes.
-	 * If @a buf is NULL, length which as to be sent as dummy bytes (as TX
-	 * buffer) or the length of bytes that should be skipped (as RX buffer).
-	 */
+	/** Length of the buffer @a buf in bytes, or length of NOP */
 	size_t len;
 };
 
 /**
- * @brief SPI buffer array structure
+ * @brief SPI scatter-gather buffer array structure
+ *
+ * A spi_buf_set is a flexible description of a whole single SPI bus transfer.
+ *
+ * Since the set is an array of pointers to buffers, it means that pieces of a spi transfer
+ * definition can be re-used across different transfers, without having to redefine or allocate
+ * new memory for them each time.
+ * This accomplishes what is called "scatter-gather" buffer management at the driver level with
+ * user-provided buffers.
  */
 struct spi_buf_set {
 	/** Pointer to an array of spi_buf, or NULL */
 	const struct spi_buf *buffers;
-	/** Length of the array (number of buffers) pointed by @a buffers */
+	/** Number of buffers in the array pointed to: by @a buffers */
 	size_t count;
 };
 
+/**
+ * @name SPI Stats
+ * @{
+ */
 #if defined(CONFIG_SPI_STATS)
 STATS_SECT_START(spi)
 STATS_SECT_ENTRY32(rx_bytes)
@@ -528,6 +631,7 @@ struct spi_device_state {
 #define SPI_STATS_TRANSFER_ERROR_INC(dev_)			\
 	STATS_INC(Z_SPI_GET_STATS(dev_), transfer_error)
 
+/** @cond INTERNAL_HIDDEN */
 /**
  * @brief Define a statically allocated and section assigned SPI device state
  */
@@ -551,26 +655,8 @@ struct spi_device_state {
 		stats_register(dev->name, &(state->stats.s_hdr));	\
 		return init_fn(dev);					\
 	}
+/** @endcond */
 
-/**
- * @brief Like DEVICE_DT_DEFINE() with SPI specifics.
- *
- * @details Defines a device which implements the SPI API. May
- * generate a custom device_state container struct and init_fn
- * wrapper when needed depending on SPI @kconfig{CONFIG_SPI_STATS}.
- *
- * @param node_id The devicetree node identifier.
- * @param init_fn Name of the init function of the driver.
- * @param pm_device PM device resources reference (NULL if device does not use PM).
- * @param data_ptr Pointer to the device's private data.
- * @param cfg_ptr The address to the structure containing the configuration
- *                information for this instance of the driver.
- * @param level The initialization level. See SYS_INIT() for details.
- * @param prio Priority within the selected initialization level. See SYS_INIT()
- *             for details.
- * @param api_ptr Provides an initial pointer to the API function struct used by
- *                the driver. Can be NULL.
- */
 #define SPI_DEVICE_DT_DEFINE(node_id, init_fn, pm_device,		\
 			     data_ptr, cfg_ptr, level, prio,		\
 			     api_ptr, ...)				\
@@ -579,7 +665,7 @@ struct spi_device_state {
 	Z_DEVICE_DEFINE(node_id, Z_DEVICE_DT_DEV_ID(node_id),		\
 			DEVICE_DT_NAME(node_id),			\
 			&UTIL_CAT(Z_DEVICE_DT_DEV_ID(node_id), _init),	\
-			pm_device,					\
+			NULL, Z_DEVICE_DT_FLAGS(node_id), pm_device,	\
 			data_ptr, cfg_ptr, level, prio,			\
 			api_ptr,					\
 			&(Z_DEVICE_STATE_NAME(Z_DEVICE_DT_DEV_ID(node_id)).devstate), \
@@ -606,18 +692,44 @@ static inline void spi_transceive_stats(const struct device *dev, int error,
 		SPI_STATS_RX_BYTES_INCN(dev, rx_bytes);
 	}
 }
+/** @} */
 
 #else /*CONFIG_SPI_STATS*/
 
+/**
+ * @name SPI DT Device Macros
+ * @{
+ */
+/**
+ * @brief Like DEVICE_DT_DEFINE() with SPI specifics.
+ *
+ * @details Defines a device which implements the SPI API. May
+ * generate a custom device_state container struct and init_fn
+ * wrapper when needed depending on SPI @kconfig{CONFIG_SPI_STATS}.
+ *
+ * @param node_id The devicetree node identifier.
+ * @param init_fn Name of the init function of the driver.
+ * @param pm PM device resources reference (NULL if device does not use PM).
+ * @param data Pointer to the device's private data.
+ * @param config The address to the structure containing the configuration
+ *                information for this instance of the driver.
+ * @param level The initialization level. See SYS_INIT() for details.
+ * @param prio Priority within the selected initialization level. See SYS_INIT()
+ *             for details.
+ * @param api Provides an initial pointer to the API function struct used by
+ *                the driver. Can be NULL.
+ */
 #define SPI_DEVICE_DT_DEFINE(node_id, init_fn, pm,		\
 				data, config, level, prio,	\
 				api, ...)			\
 	Z_DEVICE_STATE_DEFINE(Z_DEVICE_DT_DEV_ID(node_id));			\
 	Z_DEVICE_DEFINE(node_id, Z_DEVICE_DT_DEV_ID(node_id),			\
-			DEVICE_DT_NAME(node_id), init_fn, pm, data, config,	\
+			DEVICE_DT_NAME(node_id), init_fn, NULL,			\
+			Z_DEVICE_DT_FLAGS(node_id), pm, data, config,		\
 			level, prio, api,					\
 			&Z_DEVICE_STATE_NAME(Z_DEVICE_DT_DEV_ID(node_id)),	\
 			__VA_ARGS__)
+/** @} */
 
 #define SPI_STATS_RX_BYTES_INC(dev_)
 #define SPI_STATS_TX_BYTES_INC(dev_)
@@ -627,6 +739,7 @@ static inline void spi_transceive_stats(const struct device *dev, int error,
 
 #endif /*CONFIG_SPI_STATS*/
 
+
 /**
  * @brief Like SPI_DEVICE_DT_DEFINE(), but uses an instance of a `DT_DRV_COMPAT`
  * compatible instead of a node identifier.
@@ -749,11 +862,28 @@ static inline bool spi_is_ready_dt(const struct spi_dt_spec *spec)
 	return true;
 }
 
+/**
+ * @name SPI Synchronous Transfer Functions
+ *
+ * These functions will not return until transfer is complete
+ *
+ * @{
+ */
+
 /**
  * @brief Read/write the specified amount of data from the SPI driver.
  *
  * @note This function is synchronous.
  *
+ * @note In master mode, the chip select line will remain asserted (active) for
+ *       the entire duration of the transfer of all buffers in the provided buf sets.
+ *       Only after all buffers have been transferred will CS be deasserted.
+ *
+ * @note In peripheral mode, data transfer happens when the master asserts CS and
+ *       provides the clock. The function will wait for the master to complete
+ *       the transfer before returning. The CS is controlled by master
+ *       and therefore may not be continuously asserted for the whole transfer.
+ *
  * @param dev Pointer to the device structure for the driver instance
  * @param config Pointer to a valid spi_config structure instance.
  *        Pointer-comparison may be used to detect changes from
@@ -765,6 +895,9 @@ static inline bool spi_is_ready_dt(const struct spi_dt_spec *spec)
  *
  * @retval frames Positive number of frames received in slave mode.
  * @retval 0 If successful in master mode.
+ * @retval -ENOTSUP means some part of the spi config is not supported either by the
+ *	   device hardware or the driver software.
+ * @retval -EINVAL means that some parameter of the spi_config is invalid.
  * @retval -errno Negative errno code on failure.
  */
 __syscall int spi_transceive(const struct device *dev,
@@ -824,6 +957,9 @@ static inline int spi_transceive_dt(const struct spi_dt_spec *spec,
  *
  * @retval frames Positive number of frames received in slave mode.
  * @retval 0 If successful.
+ * @retval -ENOTSUP means some part of the spi config is not supported either by the
+ *	   device hardware or the driver software.
+ * @retval -EINVAL means that some parameter of the spi_config is invalid.
  * @retval -errno Negative errno code on failure.
  */
 static inline int spi_read(const struct device *dev,
@@ -865,6 +1001,9 @@ static inline int spi_read_dt(const struct spi_dt_spec *spec,
  * @param tx_bufs Buffer array where data to be sent originates from.
  *
  * @retval 0 If successful.
+ * @retval -ENOTSUP means some part of the spi config is not supported either by the
+ *	   device hardware or the driver software.
+ * @retval -EINVAL means that some parameter of the spi_config is invalid.
  * @retval -errno Negative errno code on failure.
  */
 static inline int spi_write(const struct device *dev,
@@ -891,8 +1030,20 @@ static inline int spi_write_dt(const struct spi_dt_spec *spec,
 {
 	return spi_write(spec->bus, &spec->config, tx_bufs);
 }
+/** @} */
 
 #if defined(CONFIG_SPI_ASYNC) || defined(__DOXYGEN__)
+/**
+ * @name SPI Asynchronous Transfer Functions
+ *
+ * With this API the transfer function will return after the transfer is started and
+ * report completion through a notification mechanism: callback or signal.
+ *
+ * @note Note that asynchronous API calls can still be blocking if the bus is already busy.
+ *       The functions will block until the bus is available to start the requested transfer.
+ *
+ * @{
+ */
 
 /**
  * @brief Read/write the specified amount of data from the SPI driver.
@@ -902,6 +1053,9 @@ static inline int spi_write_dt(const struct spi_dt_spec *spec,
  * @note This function is available only if @kconfig{CONFIG_SPI_ASYNC}
  * is selected.
  *
+ * @note The chip select behavior as described by @ref spi_transceive and
+ *       the function of controller/peripheral modes is the same.
+ *
  * @param dev Pointer to the device structure for the driver instance
  * @param config Pointer to a valid spi_config structure instance.
  *        Pointer-comparison may be used to detect changes from
@@ -918,6 +1072,9 @@ static inline int spi_write_dt(const struct spi_dt_spec *spec,
  *
  * @retval frames Positive number of frames received in slave mode.
  * @retval 0 If successful in master mode.
+ * @retval -ENOTSUP means some part of the spi config is not supported either by the
+ *	   device hardware or the driver software.
+ * @retval -EINVAL means that some parameter of the spi_config is invalid.
  * @retval -errno Negative errno code on failure.
  */
 static inline int spi_transceive_cb(const struct device *dev,
@@ -944,6 +1101,9 @@ void z_spi_transfer_signal_cb(const struct device *dev, int result, void *userda
  *
  * @note This function is asynchronous.
  *
+ * @note The chip select behavior as described by @ref spi_transceive and
+ *       the function of controller/peripheral modes is the same.
+ *
  * @note This function is available only if @kconfig{CONFIG_SPI_ASYNC}
  * and @kconfig{CONFIG_POLL} are selected.
  *
@@ -962,6 +1122,9 @@ void z_spi_transfer_signal_cb(const struct device *dev, int result, void *userda
  *
  * @retval frames Positive number of frames received in slave mode.
  * @retval 0 If successful in master mode.
+ * @retval -ENOTSUP means some part of the spi config is not supported either by the
+ *	   device hardware or the driver software.
+ * @retval -EINVAL means that some parameter of the spi_config is invalid.
  * @retval -errno Negative errno code on failure.
  */
 static inline int spi_transceive_signal(const struct device *dev,
@@ -999,6 +1162,9 @@ static inline int spi_transceive_signal(const struct device *dev,
  *
  * @retval frames Positive number of frames received in slave mode.
  * @retval 0 If successful
+ * @retval -ENOTSUP means some part of the spi config is not supported either by the
+ *	   device hardware or the driver software.
+ * @retval -EINVAL means that some parameter of the spi_config is invalid.
  * @retval -errno Negative errno code on failure.
  */
 static inline int spi_read_signal(const struct device *dev,
@@ -1030,6 +1196,9 @@ static inline int spi_read_signal(const struct device *dev,
  *        successfully or not).
  *
  * @retval 0 If successful.
+ * @retval -ENOTSUP means some part of the spi config is not supported either by the
+ *	   device hardware or the driver software.
+ * @retval -EINVAL means that some parameter of the spi_config is invalid.
  * @retval -errno Negative errno code on failure.
  */
 static inline int spi_write_signal(const struct device *dev,
@@ -1042,11 +1211,19 @@ static inline int spi_write_signal(const struct device *dev,
 
 #endif /* CONFIG_POLL */
 
+/** @} */
 #endif /* CONFIG_SPI_ASYNC */
 
 
 #if defined(CONFIG_SPI_RTIO) || defined(__DOXYGEN__)
 
+/**
+ * @name SPI RTIO API
+ *
+ * Theses functions are for using the SPI driver class through an RTIO-based API
+ *
+ * @{
+ */
 /**
  * @brief Submit a SPI device with a request
  *
@@ -1063,7 +1240,9 @@ static inline void spi_iodev_submit(struct rtio_iodev_sqe *iodev_sqe)
 	api->iodev_submit(dt_spec->bus, iodev_sqe);
 }
 
+/** @cond INTERNAL_HIDDEN */
 extern const struct rtio_iodev_api spi_iodev_api;
+/** @endcond */
 
 /**
  * @brief Define an iodev for a given dt node on the bus
@@ -1095,6 +1274,7 @@ static inline bool spi_is_ready_iodev(const struct rtio_iodev *spi_iodev)
 
 	return spi_is_ready_dt(spec);
 }
+/** @} */
 
 #endif /* CONFIG_SPI_RTIO */
 
@@ -1156,4 +1336,7 @@ static inline int spi_release_dt(const struct spi_dt_spec *spec)
 
 #include <zephyr/syscalls/spi.h>
 
+/**
+ * @}
+ */
 #endif /* ZEPHYR_INCLUDE_DRIVERS_SPI_H_ */
diff --git a/include/zephyr/drivers/stepper.h b/include/zephyr/drivers/stepper.h
index 31200cd0302..16632e2579f 100644
--- a/include/zephyr/drivers/stepper.h
+++ b/include/zephyr/drivers/stepper.h
@@ -1,22 +1,22 @@
-/**
- * @file drivers/stepper.h
- *
- * @brief Public API for Stepper Driver
- *
- */
-
 /*
  * SPDX-FileCopyrightText: Copyright (c) 2024 Carl Zeiss Meditec AG
  * SPDX-FileCopyrightText: Copyright (c) 2024 Jilay Sandeep Pandya
  * SPDX-License-Identifier: Apache-2.0
  */
 
+/**
+ * @file drivers/stepper.h
+ * @brief Public API for Stepper Driver
+ */
+
 #ifndef ZEPHYR_INCLUDE_DRIVERS_STEPPER_H_
 #define ZEPHYR_INCLUDE_DRIVERS_STEPPER_H_
 
 /**
- * @brief Stepper Controller Interface
- * @defgroup stepper_interface Stepper Controller Interface
+ * @brief Stepper Driver Interface
+ * @defgroup stepper_interface Stepper Driver Interface
+ * @since 4.0
+ * @version 0.1.0
  * @ingroup io_interfaces
  * @{
  */
@@ -30,35 +30,42 @@ extern "C" {
 #endif
 
 /**
- * @brief Macro to calculate the index of the microstep resolution
- * @param res Microstep resolution
- */
-#define MICRO_STEP_RES_INDEX(res) LOG2(res)
-
-/**
- * @brief Stepper Motor microstep resolution options
+ * @brief Stepper Motor micro-step resolution options
  */
 enum stepper_micro_step_resolution {
 	/** Full step resolution */
 	STEPPER_MICRO_STEP_1 = 1,
-	/** 2 microsteps per full step */
+	/** 2 micro-steps per full step */
 	STEPPER_MICRO_STEP_2 = 2,
-	/** 4 microsteps per full step */
+	/** 4 micro-steps per full step */
 	STEPPER_MICRO_STEP_4 = 4,
-	/** 8 microsteps per full step */
+	/** 8 micro-steps per full step */
 	STEPPER_MICRO_STEP_8 = 8,
-	/** 16 microsteps per full step */
+	/** 16 micro-steps per full step */
 	STEPPER_MICRO_STEP_16 = 16,
-	/** 32 microsteps per full step */
+	/** 32 micro-steps per full step */
 	STEPPER_MICRO_STEP_32 = 32,
-	/** 64 microsteps per full step */
+	/** 64 micro-steps per full step */
 	STEPPER_MICRO_STEP_64 = 64,
-	/** 128 microsteps per full step */
+	/** 128 micro-steps per full step */
 	STEPPER_MICRO_STEP_128 = 128,
-	/** 256 microsteps per full step */
+	/** 256 micro-steps per full step */
 	STEPPER_MICRO_STEP_256 = 256,
 };
 
+/**
+ * @brief Macro to calculate the index of the microstep resolution
+ * @param res Microstep resolution
+ */
+#define MICRO_STEP_RES_INDEX(res) LOG2(res)
+
+#define VALID_MICRO_STEP_RES(res)                                                                  \
+	((res) == STEPPER_MICRO_STEP_1 || (res) == STEPPER_MICRO_STEP_2 ||                         \
+	 (res) == STEPPER_MICRO_STEP_4 || (res) == STEPPER_MICRO_STEP_8 ||                         \
+	 (res) == STEPPER_MICRO_STEP_16 || (res) == STEPPER_MICRO_STEP_32 ||                       \
+	 (res) == STEPPER_MICRO_STEP_64 || (res) == STEPPER_MICRO_STEP_128 ||                      \
+	 (res) == STEPPER_MICRO_STEP_256)
+
 /**
  * @brief Stepper Motor direction options
  */
@@ -93,36 +100,32 @@ enum stepper_event {
 	STEPPER_EVENT_LEFT_END_STOP_DETECTED = 2,
 	/** Right end switch status changes to pressed */
 	STEPPER_EVENT_RIGHT_END_STOP_DETECTED = 3,
+	/** Stepper has stopped */
+	STEPPER_EVENT_STOPPED = 4,
+	/** Fault with the stepper controller detected */
+	STEPPER_EVENT_FAULT_DETECTED = 5,
 };
 
 /**
  * @cond INTERNAL_HIDDEN
  *
- * Stepper motor controller driver API definition and system call entry points.
+ * Stepper driver API definition and system call entry points.
  *
  */
 
 /**
- * @brief enable or disable the stepper motor controller.
+ * @brief Enable the stepper driver.
  *
  * @see stepper_enable() for details.
  */
-typedef int (*stepper_enable_t)(const struct device *dev, const bool enable);
-
-/**
- * @brief Move the stepper motor relatively by a given number of microsteps.
- *
- * @see stepper_move_by() for details.
- */
-typedef int (*stepper_move_by_t)(const struct device *dev, const int32_t micro_steps);
+typedef int (*stepper_enable_t)(const struct device *dev);
 
 /**
- * @brief Set the max velocity in microsteps per seconds.
+ * @brief Disable the stepper driver.
  *
- * @see stepper_set_max_velocity() for details.
+ * @see stepper_disable() for details.
  */
-typedef int (*stepper_set_max_velocity_t)(const struct device *dev,
-					  const uint32_t micro_steps_per_second);
+typedef int (*stepper_disable_t)(const struct device *dev);
 
 /**
  * @brief Set the micro-step resolution
@@ -154,56 +157,77 @@ typedef int (*stepper_set_reference_position_t)(const struct device *dev, const
 typedef int (*stepper_get_actual_position_t)(const struct device *dev, int32_t *value);
 
 /**
- * @brief Move the stepper motor to an absolute position in microsteps.
+ * @brief Callback function for stepper events
+ */
+typedef void (*stepper_event_callback_t)(const struct device *dev, const enum stepper_event event,
+					 void *user_data);
+
+/**
+ * @brief Set the callback function to be called when a stepper event occurs
  *
- * @see stepper_move_to() for details.
+ * @see stepper_set_event_callback() for details.
  */
-typedef int (*stepper_move_to_t)(const struct device *dev, const int32_t micro_steps);
+typedef int (*stepper_set_event_callback_t)(const struct device *dev,
+					    stepper_event_callback_t callback, void *user_data);
+/**
+ * @brief Set the time interval between steps in nanoseconds.
+ *
+ * @see stepper_set_microstep_interval() for details.
+ */
+typedef int (*stepper_set_microstep_interval_t)(const struct device *dev,
+						const uint64_t microstep_interval_ns);
+/**
+ * @brief Move the stepper relatively by a given number of micro-steps.
+ *
+ * @see stepper_move_by() for details.
+ */
+typedef int (*stepper_move_by_t)(const struct device *dev, const int32_t micro_steps);
 
 /**
- * @brief Is the target position fo the stepper reached
+ * @brief Move the stepper to an absolute position in micro-steps.
  *
- * @see stepper_is_moving() for details.
+ * @see stepper_move_to() for details.
  */
-typedef int (*stepper_is_moving_t)(const struct device *dev, bool *is_moving);
+typedef int (*stepper_move_to_t)(const struct device *dev, const int32_t micro_steps);
 
 /**
- * @brief Run the stepper with a given velocity in a given direction
+ * @brief Run the stepper with a given step interval in a given direction
  *
  * @see stepper_run() for details.
  */
-typedef int (*stepper_run_t)(const struct device *dev, const enum stepper_direction direction,
-			     const uint32_t value);
+typedef int (*stepper_run_t)(const struct device *dev, const enum stepper_direction direction);
 
 /**
- * @brief Callback function for stepper events
+ * @brief Stop the stepper
+ *
+ * @see stepper_stop() for details.
  */
-typedef void (*stepper_event_callback_t)(const struct device *dev, const enum stepper_event event,
-					 void *user_data);
+typedef int (*stepper_stop_t)(const struct device *dev);
 
 /**
- * @brief Set the callback function to be called when a stepper event occurs
+ * @brief Is the target position fo the stepper reached
  *
- * @see stepper_set_event_callback() for details.
+ * @see stepper_is_moving() for details.
  */
-typedef int (*stepper_set_event_callback_t)(const struct device *dev,
-					    stepper_event_callback_t callback, void *user_data);
+typedef int (*stepper_is_moving_t)(const struct device *dev, bool *is_moving);
 
 /**
- * @brief Stepper Motor Controller API
+ * @brief Stepper Driver API
  */
 __subsystem struct stepper_driver_api {
 	stepper_enable_t enable;
-	stepper_move_by_t move_by;
-	stepper_set_max_velocity_t set_max_velocity;
+	stepper_disable_t disable;
 	stepper_set_micro_step_res_t set_micro_step_res;
 	stepper_get_micro_step_res_t get_micro_step_res;
 	stepper_set_reference_position_t set_reference_position;
 	stepper_get_actual_position_t get_actual_position;
+	stepper_set_event_callback_t set_event_callback;
+	stepper_set_microstep_interval_t set_microstep_interval;
+	stepper_move_by_t move_by;
 	stepper_move_to_t move_to;
-	stepper_is_moving_t is_moving;
 	stepper_run_t run;
-	stepper_set_event_callback_t set_event_callback;
+	stepper_stop_t stop;
+	stepper_is_moving_t is_moving;
 };
 
 /**
@@ -211,76 +235,48 @@ __subsystem struct stepper_driver_api {
  */
 
 /**
- * @brief Enable or disable motor controller
+ * @brief Enable stepper driver
+ *
+ * @details Enabling the driver will energize the coils, however not set the stepper in motion.
  *
- * @param dev pointer to the stepper motor controller instance
- * @param enable Input enable or disable motor controller
+ * @param dev pointer to the stepper driver instance
  *
  * @retval -EIO Error during Enabling
  * @retval 0 Success
  */
-__syscall int stepper_enable(const struct device *dev, const bool enable);
-
-static inline int z_impl_stepper_enable(const struct device *dev, const bool enable)
-{
-	const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api;
-
-	return api->enable(dev, enable);
-}
-
-/**
- * @brief Set the microsteps to be moved from the current position i.e. relative movement
- *
- * @details The motor will move by the given number of microsteps from the current position.
- * This function is non-blocking.
- *
- * @param dev pointer to the stepper motor controller instance
- * @param micro_steps target microsteps to be moved from the current position
- *
- * @retval -ECANCELED If the stepper is disabled
- * @retval -EIO General input / output error
- * @retval	0 Success
- */
-__syscall int stepper_move_by(const struct device *dev, int32_t micro_steps);
+__syscall int stepper_enable(const struct device *dev);
 
-static inline int z_impl_stepper_move_by(const struct device *dev, const int32_t micro_steps)
+static inline int z_impl_stepper_enable(const struct device *dev)
 {
 	const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api;
 
-	return api->move_by(dev, micro_steps);
+	return api->enable(dev);
 }
 
 /**
- * @brief Set the target velocity to be reached by the motor
+ * @brief Disable stepper driver
  *
- * @details For controllers such as DRV8825 where you
- * toggle the STEP Pin, the pulse_length would have to be calculated based on this parameter in the
- * driver. For controllers where velocity can be set, this parameter corresponds to max_velocity
- * @note Setting max velocity does not set the motor into motion, a combination of set_max_velocity
- * and move is required to set the motor into motion.
+ * @details Disabling the driver shall cancel all active movements and de-energize the coils.
  *
- * @param dev pointer to the stepper motor controller instance
- * @param micro_steps_per_second speed in microsteps per second
+ * @param dev pointer to the stepper driver instance
  *
- * @retval -EIO General input / output error
- * @retval -EINVAL If the requested velocity is not supported
+ * @retval -EIO Error during Disabling
  * @retval 0 Success
  */
-__syscall int stepper_set_max_velocity(const struct device *dev, uint32_t micro_steps_per_second);
+__syscall int stepper_disable(const struct device *dev);
 
-static inline int z_impl_stepper_set_max_velocity(const struct device *dev,
-						  const uint32_t micro_steps_per_second)
+static inline int z_impl_stepper_disable(const struct device *dev)
 {
 	const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api;
 
-	return api->set_max_velocity(dev, micro_steps_per_second);
+	return api->disable(dev);
 }
 
 /**
- * @brief Set the microstep resolution in stepper motor controller
+ * @brief Set the micro-step resolution in stepper driver
  *
- * @param dev pointer to the stepper motor controller instance
- * @param resolution microstep resolution
+ * @param dev pointer to the stepper driver instance
+ * @param resolution micro-step resolution
  *
  * @retval -EIO General input / output error
  * @retval -ENOSYS If not implemented by device driver
@@ -302,10 +298,10 @@ static inline int z_impl_stepper_set_micro_step_res(const struct device *dev,
 }
 
 /**
- * @brief Get the microstep resolution in stepper motor controller
+ * @brief Get the micro-step resolution in stepper driver
  *
- * @param dev pointer to the stepper motor controller instance
- * @param resolution microstep resolution
+ * @param dev pointer to the stepper driver instance
+ * @param resolution micro-step resolution
  *
  * @retval -EIO General input / output error
  * @retval -ENOSYS If not implemented by device driver
@@ -328,7 +324,7 @@ static inline int z_impl_stepper_get_micro_step_res(const struct device *dev,
 /**
  * @brief Set the reference position of the stepper
  *
- * @param dev Pointer to the stepper motor controller instance.
+ * @param dev Pointer to the stepper driver instance.
  * @param value The reference position to set in micro-steps.
  *
  * @retval -EIO General input / output error
@@ -351,8 +347,8 @@ static inline int z_impl_stepper_set_reference_position(const struct device *dev
 /**
  * @brief Get the actual a.k.a reference position of the stepper
  *
- * @param dev pointer to the stepper motor controller instance
- * @param value The actual position to get in microsteps
+ * @param dev pointer to the stepper driver instance
+ * @param value The actual position to get in micro-steps
  *
  * @retval -EIO General input / output error
  * @retval -ENOSYS If not implemented by device driver
@@ -370,14 +366,90 @@ static inline int z_impl_stepper_get_actual_position(const struct device *dev, i
 	return api->get_actual_position(dev, value);
 }
 
+/**
+ * @brief Set the callback function to be called when a stepper event occurs
+ *
+ * @param dev pointer to the stepper driver instance
+ * @param callback Callback function to be called when a stepper event occurs
+ * passing NULL will disable the callback
+ * @param user_data User data to be passed to the callback function
+ *
+ * @retval -ENOSYS If not implemented by device driver
+ * @retval 0 Success
+ */
+__syscall int stepper_set_event_callback(const struct device *dev,
+					 stepper_event_callback_t callback, void *user_data);
+
+static inline int z_impl_stepper_set_event_callback(const struct device *dev,
+						    stepper_event_callback_t callback,
+						    void *user_data)
+{
+	const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api;
+
+	if (api->set_event_callback == NULL) {
+		return -ENOSYS;
+	}
+	return api->set_event_callback(dev, callback, user_data);
+}
+
+/**
+ * @brief Set the time interval between steps in nanoseconds with immediate effect.
+ *
+ * @note Setting step interval does not set the stepper into motion, a combination of
+ * set_microstep_interval and move is required to set the stepper into motion.
+ *
+ * @param dev pointer to the stepper driver instance
+ * @param microstep_interval_ns time interval between steps in nanoseconds
+ *
+ * @retval -EIO General input / output error
+ * @retval -EINVAL If the requested step interval is not supported
+ * @retval -ENOSYS If not implemented by device driver
+ * @retval 0 Success
+ */
+__syscall int stepper_set_microstep_interval(const struct device *dev,
+					     uint64_t microstep_interval_ns);
+
+static inline int z_impl_stepper_set_microstep_interval(const struct device *dev,
+							const uint64_t microstep_interval_ns)
+{
+	const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api;
+
+	if (api->set_microstep_interval == NULL) {
+		return -ENOSYS;
+	}
+	return api->set_microstep_interval(dev, microstep_interval_ns);
+}
+
+/**
+ * @brief Set the micro-steps to be moved from the current position i.e. relative movement
+ *
+ * @details The stepper will move by the given number of micro-steps from the current position.
+ * This function is non-blocking.
+ *
+ * @param dev pointer to the stepper driver instance
+ * @param micro_steps target micro-steps to be moved from the current position
+ *
+ * @retval -ECANCELED If the stepper is disabled
+ * @retval -EIO General input / output error
+ * @retval 0 Success
+ */
+__syscall int stepper_move_by(const struct device *dev, int32_t micro_steps);
+
+static inline int z_impl_stepper_move_by(const struct device *dev, const int32_t micro_steps)
+{
+	const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api;
+
+	return api->move_by(dev, micro_steps);
+}
+
 /**
  * @brief Set the absolute target position of the stepper
  *
- * @details The motor will move to the given microsteps position from the reference position.
+ * @details The stepper will move to the given micro-steps position from the reference position.
  * This function is non-blocking.
  *
- * @param dev pointer to the stepper motor controller instance
- * @param micro_steps target position to set in microsteps
+ * @param dev pointer to the stepper driver instance
+ * @param micro_steps target position to set in micro-steps
  *
  * @retval -ECANCELED If the stepper is disabled
  * @retval -EIO General input / output error
@@ -397,84 +469,75 @@ static inline int z_impl_stepper_move_to(const struct device *dev, const int32_t
 }
 
 /**
- * @brief Check if the stepper motor is currently moving
+ * @brief Run the stepper with a given step interval in a given direction
+ *
+ * @details The stepper shall be set into motion and run continuously until
+ * stalled or stopped using some other command, for instance, stepper_enable(false). This
+ * function is non-blocking.
  *
- * @param dev pointer to the stepper motor controller instance
- * @param is_moving Pointer to a boolean to store the moving status of the stepper motor
+ * @param dev pointer to the stepper driver instance
+ * @param direction The direction to set
  *
+ * @retval -ECANCELED If the stepper is disabled
  * @retval -EIO General input / output error
  * @retval -ENOSYS If not implemented by device driver
  * @retval 0 Success
  */
-__syscall int stepper_is_moving(const struct device *dev, bool *is_moving);
+__syscall int stepper_run(const struct device *dev, enum stepper_direction direction);
 
-static inline int z_impl_stepper_is_moving(const struct device *dev, bool *is_moving)
+static inline int z_impl_stepper_run(const struct device *dev,
+				     const enum stepper_direction direction)
 {
 	const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api;
 
-	if (api->is_moving == NULL) {
+	if (api->run == NULL) {
 		return -ENOSYS;
 	}
-	return api->is_moving(dev, is_moving);
+	return api->run(dev, direction);
 }
 
 /**
- * @brief Run the stepper with a given velocity in a given direction
+ * @brief Stop the stepper
+ * @details Cancel all active movements, however keep the coils energized.
  *
- * @details If velocity > 0, motor shall be set into motion and run incessantly until and unless
- * stalled or stopped using some other command, for instance, motor_enable(false).
- * This function is non-blocking.
- *
- * @param dev pointer to the stepper motor controller instance
- * @param direction The direction to set
- * @param velocity The velocity to set in microsteps per second
- *                 - > 0: Run the stepper with the given velocity in a given direction
- *                 - 0: Stop the stepper
+ * @param dev pointer to the stepper driver instance
  *
- * @retval -ECANCELED If the stepper is disabled
  * @retval -EIO General input / output error
  * @retval -ENOSYS If not implemented by device driver
  * @retval 0 Success
  */
-__syscall int stepper_run(const struct device *dev, enum stepper_direction direction,
-			  uint32_t velocity);
+__syscall int stepper_stop(const struct device *dev);
 
-static inline int z_impl_stepper_run(const struct device *dev,
-				     const enum stepper_direction direction,
-				     const uint32_t velocity)
+static inline int z_impl_stepper_stop(const struct device *dev)
 {
 	const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api;
 
-	if (api->run == NULL) {
+	if (api->stop == NULL) {
 		return -ENOSYS;
 	}
-	return api->run(dev, direction, velocity);
+	return api->stop(dev);
 }
 
 /**
- * @brief Set the callback function to be called when a stepper event occurs
+ * @brief Check if the stepper is currently moving
  *
- * @param dev pointer to the stepper motor controller instance
- * @param callback Callback function to be called when a stepper event occurs
- * passing NULL will disable the callback
- * @param user_data User data to be passed to the callback function
+ * @param dev pointer to the stepper driver instance
+ * @param is_moving Pointer to a boolean to store the moving status of the stepper
  *
+ * @retval -EIO General input / output error
  * @retval -ENOSYS If not implemented by device driver
  * @retval 0 Success
  */
-__syscall int stepper_set_event_callback(const struct device *dev,
-					 stepper_event_callback_t callback, void *user_data);
+__syscall int stepper_is_moving(const struct device *dev, bool *is_moving);
 
-static inline int z_impl_stepper_set_event_callback(const struct device *dev,
-						    stepper_event_callback_t callback,
-						    void *user_data)
+static inline int z_impl_stepper_is_moving(const struct device *dev, bool *is_moving)
 {
 	const struct stepper_driver_api *api = (const struct stepper_driver_api *)dev->api;
 
-	if (api->set_event_callback == NULL) {
+	if (api->is_moving == NULL) {
 		return -ENOSYS;
 	}
-	return api->set_event_callback(dev, callback, user_data);
+	return api->is_moving(dev, is_moving);
 }
 
 /**
diff --git a/include/zephyr/drivers/stepper/stepper_drv8424.h b/include/zephyr/drivers/stepper/stepper_drv8424.h
deleted file mode 100644
index 6f20774d856..00000000000
--- a/include/zephyr/drivers/stepper/stepper_drv8424.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/**
- * @file drivers/stepper/stepper_drv8424.h
- *
- * @brief Public API for DRV8424 Stepper Controller Specific Functions
- *
- */
-
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2024 Navimatix GmbH
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <stdint.h>
-#include <zephyr/drivers/stepper.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief After microstep setter fails, attempt to recover into previous state.
- *
- * @param dev Pointer to the stepper motor controller instance
- *
- * @retval 0 Success
- * @retval <0 Error code dependent on the gpio controller of the microstep pins
- */
-int drv8424_microstep_recovery(const struct device *dev);
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/include/zephyr/drivers/stepper/stepper_drv84xx.h b/include/zephyr/drivers/stepper/stepper_drv84xx.h
new file mode 100644
index 00000000000..6454fa52069
--- /dev/null
+++ b/include/zephyr/drivers/stepper/stepper_drv84xx.h
@@ -0,0 +1,33 @@
+/**
+ * @file drivers/stepper/stepper_drv84xx.h
+ *
+ * @brief Public API for DRV84XX Stepper Controller Specific Functions
+ *
+ */
+
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2024 Navimatix GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <zephyr/drivers/stepper.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief After microstep setter fails, attempt to recover into previous state.
+ *
+ * @param dev Pointer to the stepper motor controller instance
+ *
+ * @retval 0 Success
+ * @retval <0 Error code dependent on the gpio controller of the microstep pins
+ */
+int drv84xx_microstep_recovery(const struct device *dev);
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/include/zephyr/drivers/stepper/stepper_fake.h b/include/zephyr/drivers/stepper/stepper_fake.h
index 292fdbc0e80..0dad709dc61 100644
--- a/include/zephyr/drivers/stepper/stepper_fake.h
+++ b/include/zephyr/drivers/stepper/stepper_fake.h
@@ -14,11 +14,13 @@
 extern "C" {
 #endif
 
-DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_enable, const struct device *, bool);
+DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_enable, const struct device *);
+
+DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_disable, const struct device *);
 
 DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_move_by, const struct device *, int32_t);
 
-DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_set_max_velocity, const struct device *, uint32_t);
+DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_set_microstep_interval, const struct device *, uint64_t);
 
 DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_set_micro_step_res, const struct device *,
 			enum stepper_micro_step_resolution);
@@ -34,8 +36,9 @@ DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_move_to, const struct device *, int32_
 
 DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_is_moving, const struct device *, bool *);
 
-DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_run, const struct device *, enum stepper_direction,
-			uint32_t);
+DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_run, const struct device *, enum stepper_direction);
+
+DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_stop, const struct device *);
 
 DECLARE_FAKE_VALUE_FUNC(int, fake_stepper_set_event_callback, const struct device *,
 			stepper_event_callback_t, void *);
diff --git a/include/zephyr/drivers/stepper/stepper_trinamic.h b/include/zephyr/drivers/stepper/stepper_trinamic.h
index 6afe8c9292f..691eac73be6 100644
--- a/include/zephyr/drivers/stepper/stepper_trinamic.h
+++ b/include/zephyr/drivers/stepper/stepper_trinamic.h
@@ -7,6 +7,7 @@
 
 /*
  * SPDX-FileCopyrightText: Copyright (c) 2024 Carl Zeiss Meditec AG
+ * SPDX-FileCopyrightText: Copyright (c) 2025 Prevas A/S
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -49,16 +50,28 @@ extern "C" {
 #define TMC_RAMP_VSTOP_MIN      1
 #define TMC_RAMP_TZEROWAIT_MAX  (GENMASK(15, 0) - 512)
 #define TMC_RAMP_TZEROWAIT_MIN  0
-#define TMC_RAMP_VCOOLTHRS_MAX  GENMASK(22, 0)
-#define TMC_RAMP_VCOOLTHRS_MIN  0
-#define TMC_RAMP_VHIGH_MAX      GENMASK(22, 0)
-#define TMC_RAMP_VHIGH_MIN      0
 #define TMC_RAMP_IHOLD_IRUN_MAX GENMASK(4, 0)
 #define TMC_RAMP_IHOLD_IRUN_MIN 0
 #define TMC_RAMP_IHOLDDELAY_MAX GENMASK(3, 0)
 #define TMC_RAMP_IHOLDDELAY_MIN 0
 #define TMC_RAMP_VACTUAL_SHIFT  22
 
+/* TMC50XX specific */
+#define TMC_RAMP_VCOOLTHRS_MAX  GENMASK(22, 0)
+#define TMC_RAMP_VCOOLTHRS_MIN  0
+#define TMC_RAMP_VHIGH_MAX      GENMASK(22, 0)
+#define TMC_RAMP_VHIGH_MIN      0
+
+/* TMC51XX specific */
+#define TMC_RAMP_TPOWERDOWN_MAX	GENMASK(7, 0)
+#define TMC_RAMP_TPOWERDOWN_MIN	0
+#define TMC_RAMP_TPWMTHRS_MAX	GENMASK(19, 0)
+#define TMC_RAMP_TPWMTHRS_MIN	0
+#define TMC_RAMP_TCOOLTHRS_MAX	GENMASK(19, 0)
+#define TMC_RAMP_TCOOLTHRS_MIN	0
+#define TMC_RAMP_THIGH_MAX	GENMASK(19, 0)
+#define TMC_RAMP_THIGH_MIN	0
+
 /**
  * @brief Trinamic Stepper Ramp Generator data
  */
@@ -72,9 +85,21 @@ struct tmc_ramp_generator_data {
 	uint16_t dmax;
 	uint32_t vstop;
 	uint16_t tzerowait;
-	uint32_t vcoolthrs;
-	uint32_t vhigh;
 	uint32_t iholdrun;
+	union {
+		/* TMC50XX specific */
+		struct {
+			uint32_t vcoolthrs;
+			uint32_t vhigh;
+		};
+		/* TMC51XX specific */
+		struct {
+			uint32_t tpowerdown;
+			uint32_t tpwmthrs;
+			uint32_t tcoolthrs;
+			uint32_t thigh;
+		};
+	};
 };
 
 /**
@@ -108,12 +133,6 @@ struct tmc_ramp_generator_data {
 	COND_CODE_1(DT_PROP_EXISTS(node, tzerowait),					\
 	BUILD_ASSERT(IN_RANGE(DT_PROP(node, tzerowait), TMC_RAMP_TZEROWAIT_MIN,		\
 			      TMC_RAMP_TZEROWAIT_MAX), "tzerowait out of range"), ());	\
-	COND_CODE_1(DT_PROP_EXISTS(node, vcoolthrs),					\
-	BUILD_ASSERT(IN_RANGE(DT_PROP(node, vcoolthrs), TMC_RAMP_VCOOLTHRS_MIN,		\
-			      TMC_RAMP_VCOOLTHRS_MAX), "vcoolthrs out of range"), ());	\
-	COND_CODE_1(DT_PROP_EXISTS(node, vhigh),					\
-	BUILD_ASSERT(IN_RANGE(DT_PROP(node, vhigh), TMC_RAMP_VHIGH_MIN,			\
-			      TMC_RAMP_VHIGH_MAX), "vhigh out of range"), ());		\
 	COND_CODE_1(DT_PROP_EXISTS(node, ihold),					\
 	BUILD_ASSERT(IN_RANGE(DT_PROP(node, ihold), TMC_RAMP_IHOLD_IRUN_MIN,		\
 			      TMC_RAMP_IHOLD_IRUN_MAX), "ihold out of range"), ());	\
@@ -122,7 +141,27 @@ struct tmc_ramp_generator_data {
 			      TMC_RAMP_IHOLD_IRUN_MAX), "irun out of range"), ());	\
 	COND_CODE_1(DT_PROP_EXISTS(node, iholddelay),					\
 	BUILD_ASSERT(IN_RANGE(DT_PROP(node, iholddelay), TMC_RAMP_IHOLDDELAY_MIN,	\
-			      TMC_RAMP_IHOLDDELAY_MAX), "iholddelay out of range"), ());
+			      TMC_RAMP_IHOLDDELAY_MAX), "iholddelay out of range"), ());\
+	/* TMC50XX specific */								\
+	COND_CODE_1(DT_PROP_EXISTS(node, vcoolthrs),					\
+	BUILD_ASSERT(IN_RANGE(DT_PROP(node, vcoolthrs), TMC_RAMP_VCOOLTHRS_MIN,		\
+			      TMC_RAMP_VCOOLTHRS_MAX), "vcoolthrs out of range"), ());	\
+	COND_CODE_1(DT_PROP_EXISTS(node, vhigh),					\
+	BUILD_ASSERT(IN_RANGE(DT_PROP(node, vhigh), TMC_RAMP_VHIGH_MIN,			\
+			      TMC_RAMP_VHIGH_MAX), "vhigh out of range"), ());		\
+	/* TMC51XX specific */								\
+	COND_CODE_1(DT_PROP_EXISTS(node, tpowerdown),					\
+	BUILD_ASSERT(IN_RANGE(DT_PROP(node, tpowerdown), TMC_RAMP_TPOWERDOWN_MIN,	\
+			      TMC_RAMP_TPOWERDOWN_MAX), "tpowerdown out of range"), ());\
+	COND_CODE_1(DT_PROP_EXISTS(node, tpwmthrs),					\
+	BUILD_ASSERT(IN_RANGE(DT_PROP(node, tpwmthrs), TMC_RAMP_TPWMTHRS_MIN,		\
+			      TMC_RAMP_TPWMTHRS_MAX), "tpwmthrs out of range"), ());	\
+	COND_CODE_1(DT_PROP_EXISTS(node, tcoolthrs),					\
+	BUILD_ASSERT(IN_RANGE(DT_PROP(node, tcoolthrs), TMC_RAMP_TCOOLTHRS_MIN,		\
+			      TMC_RAMP_TCOOLTHRS_MAX), "tcoolthrs out of range"), ());	\
+	COND_CODE_1(DT_PROP_EXISTS(node, thigh),					\
+	BUILD_ASSERT(IN_RANGE(DT_PROP(node, thigh), TMC_RAMP_THIGH_MIN,			\
+			      TMC_RAMP_THIGH_MAX), "thigh out of range"), ());
 
 /**
  * @brief Get Trinamic Stepper Ramp Generator data from DT
@@ -131,8 +170,7 @@ struct tmc_ramp_generator_data {
  *
  * @return struct tmc_ramp_generator_data
  */
-#define TMC_RAMP_DT_SPEC_GET(node)						\
-	{									\
+#define TMC_RAMP_DT_SPEC_GET_COMMON(node)					\
 		.vstart = DT_PROP(node, vstart),				\
 		.v1 = DT_PROP(node, v1),					\
 		.vmax = DT_PROP(node, vmax),					\
@@ -142,11 +180,24 @@ struct tmc_ramp_generator_data {
 		.dmax = DT_PROP(node, dmax),					\
 		.vstop = DT_PROP(node, vstop),					\
 		.tzerowait = DT_PROP(node, tzerowait),				\
-		.vcoolthrs = DT_PROP(node, vcoolthrs),				\
-		.vhigh = DT_PROP(node, vhigh),					\
 		.iholdrun = (TMC5XXX_IRUN(DT_PROP(node, irun)) |		\
 			     TMC5XXX_IHOLD(DT_PROP(node, ihold)) |		\
-			     TMC5XXX_IHOLDDELAY(DT_PROP(node, iholddelay))),	\
+			     TMC5XXX_IHOLDDELAY(DT_PROP(node, iholddelay))),
+
+#define TMC_RAMP_DT_SPEC_GET_TMC50XX(node)					\
+	{									\
+		TMC_RAMP_DT_SPEC_GET_COMMON(node)				\
+		.vhigh = DT_PROP(node, vhigh),					\
+		.vcoolthrs = DT_PROP(node, vcoolthrs),				\
+	}
+
+#define TMC_RAMP_DT_SPEC_GET_TMC51XX(node)					\
+	{									\
+		TMC_RAMP_DT_SPEC_GET_COMMON(DT_DRV_INST(node))			\
+		.tpowerdown = DT_INST_PROP(node, tpowerdown),			\
+		.tpwmthrs = DT_INST_PROP(node, tpwmthrs),			\
+		.tcoolthrs = DT_INST_PROP(node, tcoolthrs),			\
+		.thigh = DT_INST_PROP(node, thigh),				\
 	}
 
 /**
@@ -159,9 +210,20 @@ struct tmc_ramp_generator_data {
  * @retval -ENOSYS If not implemented by device driver
  * @retval 0 Success
  */
-int tmc5041_stepper_set_ramp(const struct device *dev,
+int tmc50xx_stepper_set_ramp(const struct device *dev,
 			     const struct tmc_ramp_generator_data *ramp_data);
 
+/**
+ * @brief Set the maximum velocity of the stepper motor
+ *
+ * @param dev Pointer to the stepper motor controller instance
+ * @param velocity Maximum velocity in microsteps per second.
+ *
+ * @retval -EIO General input / output error
+ * @retval 0 Success
+ */
+int tmc50xx_stepper_set_max_velocity(const struct device *dev, uint32_t velocity);
+
 /**
  * @}
  */
diff --git a/include/zephyr/drivers/usb/udc.h b/include/zephyr/drivers/usb/udc.h
index 7e9d66bc638..197cfe60e55 100644
--- a/include/zephyr/drivers/usb/udc.h
+++ b/include/zephyr/drivers/usb/udc.h
@@ -311,7 +311,7 @@ struct udc_data {
  */
 static inline bool udc_is_initialized(const struct device *dev)
 {
-	struct udc_data *data = dev->data;
+	struct udc_data *data = (struct udc_data *)dev->data;
 
 	return atomic_test_bit(&data->status, UDC_STATUS_INITIALIZED);
 }
@@ -325,7 +325,7 @@ static inline bool udc_is_initialized(const struct device *dev)
  */
 static inline bool udc_is_enabled(const struct device *dev)
 {
-	struct udc_data *data = dev->data;
+	struct udc_data *data = (struct udc_data *)dev->data;
 
 	return atomic_test_bit(&data->status, UDC_STATUS_ENABLED);
 }
@@ -339,7 +339,7 @@ static inline bool udc_is_enabled(const struct device *dev)
  */
 static inline bool udc_is_suspended(const struct device *dev)
 {
-	struct udc_data *data = dev->data;
+	struct udc_data *data = (struct udc_data *)dev->data;
 
 	return atomic_test_bit(&data->status, UDC_STATUS_SUSPENDED);
 }
@@ -415,7 +415,7 @@ int udc_shutdown(const struct device *dev);
  */
 static inline struct udc_device_caps udc_caps(const struct device *dev)
 {
-	struct udc_data *data = dev->data;
+	struct udc_data *data = (struct udc_data *)dev->data;
 
 	return data->caps;
 }
@@ -445,7 +445,7 @@ enum udc_bus_speed udc_device_speed(const struct device *dev);
  */
 static inline int udc_set_address(const struct device *dev, const uint8_t addr)
 {
-	const struct udc_api *api = dev->api;
+	const struct udc_api *api = (const struct udc_api *)dev->api;
 	int ret;
 
 	if (!udc_is_enabled(dev)) {
@@ -477,7 +477,7 @@ static inline int udc_set_address(const struct device *dev, const uint8_t addr)
 static inline int udc_test_mode(const struct device *dev,
 				const uint8_t mode, const bool dryrun)
 {
-	const struct udc_api *api = dev->api;
+	const struct udc_api *api = (const struct udc_api *)dev->api;
 	int ret;
 
 	if (!udc_is_enabled(dev)) {
@@ -507,7 +507,7 @@ static inline int udc_test_mode(const struct device *dev,
  */
 static inline int udc_host_wakeup(const struct device *dev)
 {
-	const struct udc_api *api = dev->api;
+	const struct udc_api *api = (const struct udc_api *)dev->api;
 	int ret;
 
 	if (!udc_is_enabled(dev)) {
@@ -724,7 +724,7 @@ static inline struct udc_buf_info *udc_get_buf_info(const struct net_buf *const
  */
 static inline const void *udc_get_event_ctx(const struct device *dev)
 {
-	struct udc_data *data = dev->data;
+	struct udc_data *data = (struct udc_data *)dev->data;
 
 	return data->event_ctx;
 }
diff --git a/include/zephyr/drivers/usb/udc_buf.h b/include/zephyr/drivers/usb/udc_buf.h
index 6e1ca15e1c3..5975c6d6a35 100644
--- a/include/zephyr/drivers/usb/udc_buf.h
+++ b/include/zephyr/drivers/usb/udc_buf.h
@@ -34,6 +34,16 @@
 #define Z_UDC_BUF_GRANULARITY	sizeof(void *)
 #endif
 
+
+#if defined(CONFIG_UDC_BUF_FORCE_NOCACHE)
+/*
+ * The usb transfer buffer needs to be in __nocache section
+ */
+#define Z_UDC_BUF_SECTION	__nocache
+#else
+#define Z_UDC_BUF_SECTION
+#endif
+
 /**
  * @brief Buffer macros and definitions used in USB device support
  * @defgroup udc_buf Buffer macros and definitions used in USB device support
@@ -59,7 +69,8 @@
  * @param size Buffer size
  */
 #define UDC_STATIC_BUF_DEFINE(name, size)					\
-	static uint8_t __aligned(UDC_BUF_ALIGN) name[ROUND_UP(size, UDC_BUF_GRANULARITY)];
+	static uint8_t Z_UDC_BUF_SECTION __aligned(UDC_BUF_ALIGN)		\
+	name[ROUND_UP(size, UDC_BUF_GRANULARITY)];
 
 /**
  * @brief Verify that the buffer is aligned as required by the UDC driver
@@ -136,7 +147,7 @@ extern const struct net_buf_data_cb net_buf_dma_cb;
 	_NET_BUF_ARRAY_DEFINE(pname, count, ud_size);				\
 	BUILD_ASSERT((UDC_BUF_GRANULARITY) % (UDC_BUF_ALIGN) == 0,		\
 		     "Code assumes granurality is multiple of alignment");	\
-	static uint8_t __nocache __aligned(UDC_BUF_ALIGN)			\
+	static uint8_t Z_UDC_BUF_SECTION __aligned(UDC_BUF_ALIGN)		\
 		net_buf_data_##pname[count][ROUND_UP(size, UDC_BUF_GRANULARITY)];\
 	static const struct net_buf_pool_fixed net_buf_fixed_##pname = {	\
 		.data_pool = (uint8_t *)net_buf_data_##pname,			\
diff --git a/include/zephyr/drivers/usb/uhc.h b/include/zephyr/drivers/usb/uhc.h
index a2224d24669..f7e357854e8 100644
--- a/include/zephyr/drivers/usb/uhc.h
+++ b/include/zephyr/drivers/usb/uhc.h
@@ -23,10 +23,75 @@
  * @defgroup uhc_api USB host controller driver API
  * @ingroup io_interfaces
  * @since 3.3
- * @version 0.1.0
+ * @version 0.1.1
  * @{
  */
 
+/** USB device state */
+enum usb_device_state {
+	USB_STATE_NOTCONNECTED,
+	USB_STATE_DEFAULT,
+	USB_STATE_ADDRESSED,
+	USB_STATE_CONFIGURED,
+};
+
+/**
+ * @brief USB device operating speed
+ */
+enum usb_device_speed {
+	/** Device is probably not connected */
+	USB_SPEED_UNKNOWN,
+	/** Low speed */
+	USB_SPEED_SPEED_LS,
+	/** Full speed */
+	USB_SPEED_SPEED_FS,
+	/** High speed */
+	USB_SPEED_SPEED_HS,
+	/** Super speed */
+	USB_SPEED_SPEED_SS,
+};
+
+#define UHC_INTERFACES_MAX 32
+
+struct usb_host_interface {
+	struct usb_desc_header *dhp;
+	uint8_t alternate;
+};
+
+struct usb_host_ep {
+	struct usb_ep_descriptor *desc;
+};
+
+/**
+ * Host representation of a USB device
+ */
+struct usb_device {
+	/** dlist node */
+	sys_dnode_t node;
+	/** An opaque pointer to the host context to which this device belongs */
+	void *ctx;
+	/** Device mutex */
+	struct k_mutex mutex;
+	/** USB device descriptor */
+	struct usb_device_descriptor dev_desc;
+	/** Device state */
+	enum usb_device_state state;
+	/** Device speed */
+	enum usb_device_speed speed;
+	/** Actual active device configuration */
+	uint8_t actual_cfg;
+	/** Device address */
+	uint8_t addr;
+	/** Pointer to actual device configuration descriptor */
+	void *cfg_desc;
+	/** Pointers to device interfaces */
+	struct usb_host_interface ifaces[UHC_INTERFACES_MAX + 1];
+	/** Pointers to device OUT endpoints */
+	struct usb_host_ep ep_out[16];
+	/** Pointers to device IN endpoints */
+	struct usb_host_ep ep_in[16];
+};
+
 /**
  * @brief USB control transfer stage
  */
@@ -53,24 +118,24 @@ struct uhc_transfer {
 	uint8_t setup_pkt[8];
 	/** Transfer data buffer */
 	struct net_buf *buf;
-	/** Device (peripheral) address */
-	uint8_t addr;
 	/** Endpoint to which request is associated */
 	uint8_t ep;
-	/** Endpoint attributes (TBD) */
-	uint8_t attrib;
 	/** Maximum packet size */
 	uint16_t mps;
-	/** Timeout in number of frames */
-	uint16_t timeout;
+	/** Interval, used for periodic transfers only */
+	uint16_t interval;
+	/** Start frame, used for periodic transfers only */
+	uint16_t start_frame;
 	/** Flag marks request buffer is queued */
 	unsigned int queued : 1;
 	/** Control stage status, up to the driver to use it or not */
 	unsigned int stage : 2;
-	/** Pointer to USB device (opaque for the UHC) */
-	void *udev;
+	/** Pointer to USB device */
+	struct usb_device *udev;
 	/** Pointer to transfer completion callback (opaque for the UHC) */
 	void *cb;
+	/** Pointer to completion callback private data */
+	void *priv;
 	/** Transfer result, 0 on success, other values on error */
 	int err;
 };
@@ -177,6 +242,8 @@ struct uhc_data {
 	sys_dlist_t bulk_xfers;
 	/** Callback to submit an UHC event to upper layer */
 	uhc_event_cb_t event_cb;
+	/** Opaque pointer to store higher layer context */
+	const void *event_ctx;
 	/** USB host controller status */
 	atomic_t status;
 	/** Driver private data */
@@ -336,24 +403,18 @@ static inline int uhc_bus_resume(const struct device *dev)
  * and added from different pools.
  *
  * @param[in] dev     Pointer to device struct of the driver instance
- * @param[in] addr    Device (peripheral) address
  * @param[in] ep      Endpoint address
- * @param[in] attrib  Endpoint attributes
- * @param[in] mps     Maximum packet size of the endpoint
- * @param[in] timeout Timeout in number of frames
- * @param[in] udev    Opaque pointer to USB device
+ * @param[in] udev    Pointer to USB device
  * @param[in] cb      Transfer completion callback
+ * @param[in] cb_priv Completion callback callback private data
  *
  * @return pointer to allocated transfer or NULL on error.
  */
 struct uhc_transfer *uhc_xfer_alloc(const struct device *dev,
-				    const uint8_t addr,
 				    const uint8_t ep,
-				    const uint8_t attrib,
-				    const uint16_t mps,
-				    const uint16_t timeout,
-				    void *const udev,
-				    void *const cb);
+				    struct usb_device *const udev,
+				    void *const cb,
+				    void *const cb_priv);
 
 /**
  * @brief Allocate UHC transfer with buffer
@@ -361,25 +422,19 @@ struct uhc_transfer *uhc_xfer_alloc(const struct device *dev,
  * Allocate a new transfer from common transfer pool with buffer.
  *
  * @param[in] dev     Pointer to device struct of the driver instance
- * @param[in] addr    Device (peripheral) address
  * @param[in] ep      Endpoint address
- * @param[in] attrib  Endpoint attributes
- * @param[in] mps     Maximum packet size of the endpoint
- * @param[in] timeout Timeout in number of frames
- * @param[in] udev    Opaque pointer to USB device
+ * @param[in] udev    Pointer to USB device
  * @param[in] cb      Transfer completion callback
+ * @param[in] cb_priv Completion callback callback private data
  * @param[in] size    Size of the buffer
  *
  * @return pointer to allocated transfer or NULL on error.
  */
 struct uhc_transfer *uhc_xfer_alloc_with_buf(const struct device *dev,
-					     const uint8_t addr,
 					     const uint8_t ep,
-					     const uint8_t attrib,
-					     const uint16_t mps,
-					     const uint16_t timeout,
-					     void *const udev,
+					     struct usb_device *const udev,
 					     void *const cb,
+					     void *const cb_priv,
 					     size_t size);
 
 /**
@@ -467,12 +522,14 @@ int uhc_ep_dequeue(const struct device *dev, struct uhc_transfer *const xfer);
  *
  * @param[in] dev      Pointer to device struct of the driver instance
  * @param[in] event_cb Event callback from the higher layer (USB host stack)
+ * @param[in] event_ctx Opaque pointer to higher layer context
  *
  * @return 0 on success, all other values should be treated as error.
  * @retval -EINVAL on parameter error (no callback is passed)
  * @retval -EALREADY already initialized
  */
-int uhc_init(const struct device *dev, uhc_event_cb_t event_cb);
+int uhc_init(const struct device *dev,
+	     uhc_event_cb_t event_cb, const void *const event_ctx);
 
 /**
  * @brief Enable USB host controller
@@ -530,6 +587,23 @@ static inline struct uhc_device_caps uhc_caps(const struct device *dev)
 	return data->caps;
 }
 
+/**
+ * @brief Get pointer to higher layer context
+ *
+ * The address of the context is passed as an argument to the uhc_init()
+ * function and is stored in the uhc data.
+ *
+ * @param[in] dev Pointer to device struct of the driver instance
+ *
+ * @return Opaque pointer to higher layer context
+ */
+static inline const void *uhc_get_event_ctx(const struct device *dev)
+{
+	struct uhc_data *data = dev->data;
+
+	return data->event_ctx;
+}
+
 /**
  * @}
  */
diff --git a/include/zephyr/drivers/usb_c/tcpci_priv.h b/include/zephyr/drivers/usb_c/tcpci_priv.h
index 8c5d67f59e3..aad4fb80bbe 100644
--- a/include/zephyr/drivers/usb_c/tcpci_priv.h
+++ b/include/zephyr/drivers/usb_c/tcpci_priv.h
@@ -108,12 +108,158 @@ enum tcpc_alert tcpci_alert_reg_to_enum(uint16_t reg);
  * representing voltages state and partner detection status.
  *
  * @param bus I2C bus
- * @param cc1 pointer to variable where detected CC1 voltage state will be stored
- * @param cc2 pointer to variable where detected CC2 voltage state will be stored
+ * @param cc1 Pointer to variable where detected CC1 voltage state will be stored
+ * @param cc2 Pointer to variable where detected CC2 voltage state will be stored
  * @return -EINVAL if cc1 or cc2 pointer is NULL
  * @return int Status of I2C operation, 0 in case of success
  */
 int tcpci_tcpm_get_cc(const struct i2c_dt_spec *bus, enum tc_cc_voltage_state *cc1,
 		      enum tc_cc_voltage_state *cc2);
 
+/**
+ * @brief Function to retrieve information about the TCPCI chip.
+ *
+ * @param bus I2C bus
+ * @param chip_info Pointer to the structure where the chip information will be stored
+ * @return int Status of I2C operation, 0 in case of success
+ */
+int tcpci_tcpm_get_chip_info(const struct i2c_dt_spec *bus, struct tcpc_chip_info *chip_info);
+
+/**
+ * @brief Function to dump the standard TCPCI registers.
+ *
+ * @param bus I2C bus
+ * @return int Status of I2C operation, 0 in case of success
+ */
+int tcpci_tcpm_dump_std_reg(const struct i2c_dt_spec *bus);
+
+/**
+ * @brief Function to enable or disable the BIST (Built-In Self-Test) mode.
+ *
+ * @param bus I2C bus
+ * @param enable Boolean flag to enable (true) or disable (false) BIST mode
+ * @return int Status of I2C operation, 0 in case of success
+ */
+int tcpci_tcpm_set_bist_test_mode(const struct i2c_dt_spec *bus, bool enable);
+
+/**
+ * @brief Function to transmit a PD (Power Delivery) message. The message is transmitted
+ * with a specified number of retries in case of failure.
+ *
+ * @param bus I2C bus
+ * @param msg Pointer to the PD message structure to be transmitted
+ * @param retries Number of retries in case of transmission failure
+ * @return int Status of I2C operation, 0 in case of success
+ */
+int tcpci_tcpm_transmit_data(const struct i2c_dt_spec *bus, struct pd_msg *msg,
+			     const uint8_t retries);
+
+/**
+ * @brief Function to select the Rp (Pull-up Resistor) value.
+ *
+ * @param bus I2C bus
+ * @param rp Enum representing the Rp value to be set
+ * @return int Status of I2C operation, 0 in case of success
+ */
+int tcpci_tcpm_select_rp_value(const struct i2c_dt_spec *bus, enum tc_rp_value rp);
+
+/**
+ * @brief Function to get the currently selected Rp value.
+ *
+ * @param bus I2C bus
+ * @param rp Pointer to the variable where the Rp value will be stored
+ * @return int Status of I2C operation, 0 in case of success
+ */
+int tcpci_tcpm_get_rp_value(const struct i2c_dt_spec *bus, enum tc_rp_value *rp);
+
+/**
+ * @brief Function to set the CC pull resistor and set the role as either Source or Sink.
+ *
+ * @param bus I2C bus
+ * @param pull Enum representing the CC pull resistor to be set
+ * @return int Status of I2C operation, 0 in case of success
+ */
+int tcpci_tcpm_set_cc(const struct i2c_dt_spec *bus, enum tc_cc_pull pull);
+
+/**
+ * @brief Function to enable or disable TCPC auto dual role toggle.
+ *
+ * @param bus I2C bus
+ * @param enable Boolean flag to enable (true) or disable (false) DRP toggle mode
+ * @return int Status of I2C operation, 0 in case of success
+ */
+int tcpci_tcpm_set_drp_toggle(const struct i2c_dt_spec *bus, bool enable);
+
+/**
+ * @brief Function to set the power and data role of the PD message header.
+ *
+ * @param bus I2C bus
+ * @param pd_rev Enum representing the USB−PD Specification Revision to be set
+ * @param power_role Enum representing the power role to be set
+ * @param data_role Enum representing the data role to be set
+ * @return int Status of I2C operation, 0 in case of success
+ */
+int tcpci_tcpm_set_roles(const struct i2c_dt_spec *bus, enum pd_rev_type pd_rev,
+			 enum tc_power_role power_role, enum tc_data_role data_role);
+
+/**
+ * @brief Function to set the RX type.
+ *
+ * @param bus I2C bus
+ * @param type Value representing the RX type to be set
+ * @return int Status of I2C operation, 0 in case of success
+ */
+int tcpci_tcpm_set_rx_type(const struct i2c_dt_spec *bus, uint8_t type);
+
+/**
+ * @brief Function to set the polarity of the CC lines.
+ *
+ * @param bus I2C bus
+ * @param polarity Enum representing the CC polarity to be set
+ * @return int Status of I2C operation, 0 in case of success
+ */
+int tcpci_tcpm_set_cc_polarity(const struct i2c_dt_spec *bus, enum tc_cc_polarity polarity);
+
+/**
+ * @brief Function to enable or disable VCONN.
+ *
+ * @param bus I2C bus
+ * @param enable Boolean flag to enable (true) or disable (false) VCONN
+ * @return int Status of I2C operation, 0 in case of success
+ */
+int tcpci_tcpm_set_vconn(const struct i2c_dt_spec *bus, bool enable);
+
+/**
+ * @brief Function to get the status of a specific TCPCI status register.
+ *
+ * @param bus I2C bus
+ * @param reg Enum representing the status register to be read
+ * @param status Pointer to the variable where the status will be stored
+ * @return int Status of I2C operation, 0 in case of success
+ */
+int tcpci_tcpm_get_status_register(const struct i2c_dt_spec *bus, enum tcpc_status_reg reg,
+				   uint16_t *status);
+
+/**
+ * @brief Function to clear specific bits in a TCPCI status register.
+ *
+ * @param bus I2C bus
+ * @param reg Enum representing the status register to be cleared
+ * @param mask Bitmask specifying which bits to clear
+ * @return int Status of I2C operation, 0 in case of success
+ */
+int tcpci_tcpm_clear_status_register(const struct i2c_dt_spec *bus, enum tcpc_status_reg reg,
+				     uint16_t mask);
+
+/**
+ * @brief Function to set the mask of a TCPCI status register.
+ *
+ * @param bus I2C bus
+ * @param reg Enum representing the status register to be masked
+ * @param mask Bitmask specifying which bits to mask
+ * @return int Status of I2C operation, 0 in case of success
+ */
+int tcpci_tcpm_mask_status_register(const struct i2c_dt_spec *bus, enum tcpc_status_reg reg,
+				    uint16_t mask);
+
 #endif /* ZEPHYR_INCLUDE_DRIVERS_USBC_TCPCI_PRIV_H_ */
diff --git a/include/zephyr/drivers/usb_c/usbc_tcpc.h b/include/zephyr/drivers/usb_c/usbc_tcpc.h
index 33daa31415c..81ed04fb5bf 100644
--- a/include/zephyr/drivers/usb_c/usbc_tcpc.h
+++ b/include/zephyr/drivers/usb_c/usbc_tcpc.h
@@ -83,6 +83,8 @@ enum tcpc_alert {
  * @brief TCPC Status register
  */
 enum tcpc_status_reg {
+	/** The Altert register */
+	TCPC_ALERT_STATUS,
 	/** The CC Status register */
 	TCPC_CC_STATUS,
 	/** The Power Status register */
@@ -837,10 +839,11 @@ static inline int tcpc_set_low_power_mode(const struct device *dev, bool enable)
 }
 
 /**
- * @brief Enables the reception of SOP Prime messages
+ * @brief Enables the reception of SOP Prime and optionally SOP Double Prime messages
  *
  * @param dev     Runtime device structure
- * @param enable  Can receive SOP Prime messages when true, else it can not
+ * @param enable  Can receive SOP Prime messages and SOP Double Prime messages when true,
+ *		  else it can not
  *
  * @retval 0 on success
  * @retval -EIO on failure
diff --git a/include/zephyr/drivers/video-controls.h b/include/zephyr/drivers/video-controls.h
index b67e5a8771a..4304316c181 100644
--- a/include/zephyr/drivers/video-controls.h
+++ b/include/zephyr/drivers/video-controls.h
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2019 Linaro Limited.
  * Copyright (c) 2024 tinyVision.ai Inc.
+ * Copyright 2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -29,6 +30,8 @@
  * @{
  */
 
+#include <stdint.h>
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -54,7 +57,13 @@ extern "C" {
 /** Amount of time an image sensor is exposed to light, affecting the brightness */
 #define VIDEO_CID_EXPOSURE (VIDEO_CID_BASE + 17)
 
-/** Amount of amplification performed to each pixel electrical signal, affecting the brightness */
+/** Automatic gain control */
+#define VIDEO_CID_AUTOGAIN (VIDEO_CID_BASE + 18)
+
+/** Gain control. Most devices control only digital gain with this control.
+ * Devices that recognise the difference between digital and analogue gain use
+ * VIDEO_CID_DIGITAL_GAIN and VIDEO_CID_ANALOGUE_GAIN.
+ */
 #define VIDEO_CID_GAIN (VIDEO_CID_BASE + 19)
 
 /** Flip the image horizontally: the left side becomes the right side */
@@ -75,6 +84,9 @@ enum video_power_line_frequency {
 /** Balance of colors in direction of blue (cold) or red (warm) */
 #define VIDEO_CID_WHITE_BALANCE_TEMPERATURE (VIDEO_CID_BASE + 26)
 
+/** Last base CID + 1 */
+#define VIDEO_CID_LASTP1 (VIDEO_CID_BASE + 44)
+
 /**
  * @}
  */
@@ -95,6 +107,15 @@ enum video_power_line_frequency {
  */
 #define VIDEO_CID_CAMERA_CLASS_BASE 0x009a0900
 
+/** Adjustments of exposure time and/or iris aperture. */
+#define VIDEO_CID_EXPOSURE_AUTO (VIDEO_CID_CAMERA_CLASS_BASE + 1)
+enum video_exposure_auto_type {
+	VIDEO_EXPOSURE_AUTO = 0,
+	VIDEO_EXPOSURE_MANUAL = 1,
+	VIDEO_EXPOSURE_SHUTTER_PRIORITY = 2,
+	VIDEO_EXPOSURE_APERTURE_PRIORITY = 3
+};
+
 /** Amount of optical zoom applied through to the camera optics */
 #define VIDEO_CID_ZOOM_ABSOLUTE (VIDEO_CID_CAMERA_CLASS_BASE + 13)
 
@@ -131,6 +152,9 @@ enum video_power_line_frequency {
  */
 #define VIDEO_CID_IMAGE_SOURCE_CLASS_BASE 0x009e0900
 
+/** Analogue gain control. */
+#define VIDEO_CID_ANALOGUE_GAIN (VIDEO_CID_IMAGE_SOURCE_CLASS_BASE + 3)
+
 /**
  * @}
  */
@@ -157,6 +181,94 @@ enum video_power_line_frequency {
  */
 #define VIDEO_CID_PRIVATE_BASE 0x08000000
 
+/**
+ * @}
+ */
+
+/**
+ * @name Query flags, to be ORed with the control ID
+ * @{
+ */
+#define VIDEO_CTRL_FLAG_NEXT_CTRL 0x80000000
+
+/**
+ * @}
+ */
+
+/**
+ * @name Public video control structures
+ * @{
+ */
+
+/**
+ * @struct video_control
+ * @brief Video control structure
+ *
+ * Used to get/set a video control.
+ * @see video_ctrl for the struct used in the driver implementation
+ */
+struct video_control {
+	/** control id */
+	uint32_t id;
+	/** control value */
+	union {
+		int32_t val;
+		int64_t val64;
+	};
+};
+
+/**
+ * @struct video_control_range
+ * @brief Video control range structure
+ *
+ * Describe range of a control including min, max, step and default values
+ */
+struct video_ctrl_range {
+	/** control minimum value, inclusive */
+	union {
+		int32_t min;
+		int64_t min64;
+	};
+	/** control maximum value, inclusive */
+	union {
+		int32_t max;
+		int64_t max64;
+	};
+	/** control value step */
+	union {
+		int32_t step;
+		int64_t step64;
+	};
+	/** control default value for VIDEO_CTRL_TYPE_INTEGER, _BOOLEAN, _MENU or
+	 * _INTEGER_MENU, not valid for other types
+	 */
+	union {
+		int32_t def;
+		int64_t def64;
+	};
+};
+
+/**
+ * @struct video_control_query
+ * @brief Video control query structure
+ *
+ * Used to query information about a control.
+ */
+struct video_ctrl_query {
+	/** control id */
+	uint32_t id;
+	/** control type */
+	uint32_t type;
+	/** control name */
+	const char *name;
+	/** control flags */
+	uint32_t flags;
+	/** control range */
+	struct video_ctrl_range range;
+	/** menu if control is of menu type */
+	const char *const *menu;
+};
+
 /**
  * @}
  */
diff --git a/include/zephyr/drivers/video.h b/include/zephyr/drivers/video.h
index 959083a411a..c0b814932f7 100644
--- a/include/zephyr/drivers/video.h
+++ b/include/zephyr/drivers/video.h
@@ -6,6 +6,7 @@
 
 /*
  * Copyright (c) 2019 Linaro Limited.
+ * Copyright 2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -37,6 +38,8 @@ extern "C" {
  */
 #define LINE_COUNT_HEIGHT (-1)
 
+struct video_control;
+
 /**
  * @struct video_format
  * @brief Video format structure
@@ -302,36 +305,26 @@ typedef int (*video_api_dequeue_t)(const struct device *dev, enum video_endpoint
 typedef int (*video_api_flush_t)(const struct device *dev, enum video_endpoint_id ep, bool cancel);
 
 /**
- * @typedef video_api_stream_start_t
- * @brief Start the capture or output process.
+ * @typedef video_api_set_stream_t
+ * @brief Start or stop streaming on the video device.
  *
- * See video_stream_start() for argument descriptions.
- */
-typedef int (*video_api_stream_start_t)(const struct device *dev);
-
-/**
- * @typedef video_api_stream_stop_t
- * @brief Stop the capture or output process.
+ * Start (enable == true) or stop (enable == false) streaming on the video device.
  *
- * See video_stream_stop() for argument descriptions.
- */
-typedef int (*video_api_stream_stop_t)(const struct device *dev);
-
-/**
- * @typedef video_api_set_ctrl_t
- * @brief Set a video control value.
+ * @param dev Pointer to the device structure.
+ * @param enable If true, start streaming, otherwise stop streaming.
  *
- * See video_set_ctrl() for argument descriptions.
+ * @retval 0 on success, otherwise a negative errno code.
  */
-typedef int (*video_api_set_ctrl_t)(const struct device *dev, unsigned int cid, void *value);
+typedef int (*video_api_set_stream_t)(const struct device *dev, bool enable);
 
 /**
- * @typedef video_api_get_ctrl_t
- * @brief Get a video control value.
+ * @typedef video_api_ctrl_t
+ * @brief Set/Get a video control value.
  *
- * See video_get_ctrl() for argument descriptions.
+ * @param dev Pointer to the device structure.
+ * @param cid Id of the control to set/get its value.
  */
-typedef int (*video_api_get_ctrl_t)(const struct device *dev, unsigned int cid, void *value);
+typedef int (*video_api_ctrl_t)(const struct device *dev, uint32_t cid);
 
 /**
  * @typedef video_api_get_caps_t
@@ -355,15 +348,14 @@ __subsystem struct video_driver_api {
 	/* mandatory callbacks */
 	video_api_set_format_t set_format;
 	video_api_get_format_t get_format;
-	video_api_stream_start_t stream_start;
-	video_api_stream_stop_t stream_stop;
+	video_api_set_stream_t set_stream;
 	video_api_get_caps_t get_caps;
 	/* optional callbacks */
 	video_api_enqueue_t enqueue;
 	video_api_dequeue_t dequeue;
 	video_api_flush_t flush;
-	video_api_set_ctrl_t set_ctrl;
-	video_api_get_ctrl_t get_ctrl;
+	video_api_ctrl_t set_ctrl;
+	video_api_ctrl_t get_volatile_ctrl;
 	video_api_set_signal_t set_signal;
 	video_api_set_frmival_t set_frmival;
 	video_api_get_frmival_t get_frmival;
@@ -598,11 +590,11 @@ static inline int video_stream_start(const struct device *dev)
 {
 	const struct video_driver_api *api = (const struct video_driver_api *)dev->api;
 
-	if (api->stream_start == NULL) {
+	if (api->set_stream == NULL) {
 		return -ENOSYS;
 	}
 
-	return api->stream_start(dev);
+	return api->set_stream(dev, true);
 }
 
 /**
@@ -619,11 +611,11 @@ static inline int video_stream_stop(const struct device *dev)
 	const struct video_driver_api *api = (const struct video_driver_api *)dev->api;
 	int ret;
 
-	if (api->stream_stop == NULL) {
+	if (api->set_stream == NULL) {
 		return -ENOSYS;
 	}
 
-	ret = api->stream_stop(dev);
+	ret = api->set_stream(dev, false);
 	video_flush(dev, VIDEO_EP_ALL, true);
 
 	return ret;
@@ -657,24 +649,14 @@ static inline int video_get_caps(const struct device *dev, enum video_endpoint_i
  * must be interpreted accordingly.
  *
  * @param dev Pointer to the device structure for the driver instance.
- * @param cid Control ID.
- * @param value Pointer to the control value.
+ * @param control Pointer to the video control struct.
  *
  * @retval 0 Is successful.
  * @retval -EINVAL If parameters are invalid.
  * @retval -ENOTSUP If format is not supported.
  * @retval -EIO General input / output error.
  */
-static inline int video_set_ctrl(const struct device *dev, unsigned int cid, void *value)
-{
-	const struct video_driver_api *api = (const struct video_driver_api *)dev->api;
-
-	if (api->set_ctrl == NULL) {
-		return -ENOSYS;
-	}
-
-	return api->set_ctrl(dev, cid, value);
-}
+int video_set_ctrl(const struct device *dev, struct video_control *control);
 
 /**
  * @brief Get the current value of a control.
@@ -682,25 +664,50 @@ static inline int video_set_ctrl(const struct device *dev, unsigned int cid, voi
  * This retrieve the value of a video control, value type depends on control ID,
  * and must be interpreted accordingly.
  *
- * @param dev Pointer to the device structure for the driver instance.
- * @param cid Control ID.
- * @param value Pointer to the control value.
+ * @param dev Pointer to the device structure.
+ * @param control Pointer to the video control struct.
  *
  * @retval 0 Is successful.
  * @retval -EINVAL If parameters are invalid.
  * @retval -ENOTSUP If format is not supported.
  * @retval -EIO General input / output error.
  */
-static inline int video_get_ctrl(const struct device *dev, unsigned int cid, void *value)
-{
-	const struct video_driver_api *api = (const struct video_driver_api *)dev->api;
+int video_get_ctrl(const struct device *dev, struct video_control *control);
 
-	if (api->get_ctrl == NULL) {
-		return -ENOSYS;
-	}
+struct video_ctrl_query;
 
-	return api->get_ctrl(dev, cid, value);
-}
+/**
+ * @brief Query information about a control.
+ *
+ * Applications set the id field of the query structure, the function fills the rest of this
+ * structure. It is possible to enumerate base class controls (i.e., VIDEO_CID_BASE + x) by calling
+ * this function with successive id values starting from VIDEO_CID_BASE up to and exclusive
+ * VIDEO_CID_LASTP1. The function may return -ENOTSUP if a control in this range is not supported.
+ * Applications can also enumerate private controls by starting at VIDEO_CID_PRIVATE_BASE and
+ * incrementing the id until the driver returns -ENOTSUP. For other control classes, it's a bit more
+ * difficult. Hence, the best way to enumerate all kinds of device's supported controls is to
+ * iterate with VIDEO_CTRL_FLAG_NEXT_CTRL.
+ *
+ * @param dev Pointer to the device structure.
+ * @param cq Pointer to the control query struct.
+ *
+ * @retval 0 If successful.
+ * @retval -EINVAL If the control id is invalid.
+ * @retval -ENOTSUP If the control id is not supported.
+ */
+int video_query_ctrl(const struct device *dev, struct video_ctrl_query *cq);
+
+/**
+ * @brief Print all the information of a control.
+ *
+ * Print all the information of a control including its name, type, flag, range,
+ * menu (if any) and current value, i.e. by invoking the video_get_ctrl(), in a
+ * human readble format.
+ *
+ * @param dev Pointer to the device structure.
+ * @param cq Pointer to the control query struct.
+ */
+void video_print_ctrl(const struct device *const dev, const struct video_ctrl_query *const cq);
 
 /**
  * @brief Register/Unregister k_poll signal for a video endpoint.
@@ -812,104 +819,399 @@ void video_closest_frmival_stepwise(const struct video_frmival_stepwise *stepwis
 void video_closest_frmival(const struct device *dev, enum video_endpoint_id ep,
 			   struct video_frmival_enum *match);
 
-/* fourcc - four-character-code */
-#define video_fourcc(a, b, c, d)                                                                   \
-	((uint32_t)(a) | ((uint32_t)(b) << 8) | ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
-
 /**
  * @defgroup video_pixel_formats Video pixel formats
+ * The '|' characters separate the pixels or logical blocks, and spaces separate the bytes.
+ * The uppercase letter represents the most significant bit.
+ * The lowercase letters represent the rest of the bits.
  * @{
  */
 
 /**
- * @name Bayer formats
+ * @brief Four-character-code uniquely identifying the pixel format
+ */
+#define VIDEO_FOURCC(a, b, c, d)                                                                   \
+	((uint32_t)(a) | ((uint32_t)(b) << 8) | ((uint32_t)(c) << 16) | ((uint32_t)(d) << 24))
+
+/**
+ * @brief Convert a four-character-string to a four-character-code
+ *
+ * Convert a string literal or variable into a four-character-code
+ * as defined by @ref VIDEO_FOURCC.
+ *
+ * @param str String to be converted
+ * @return Four-character-code.
+ */
+#define VIDEO_FOURCC_FROM_STR(str) VIDEO_FOURCC((str)[0], (str)[1], (str)[2], (str)[3])
+
+/**
+ * @brief Convert a four-character-code to a four-character-string
+ *
+ * Convert a four-character code as defined by @ref VIDEO_FOURCC into a string that can be used
+ * anywhere, such as in debug logs with the %s print formatter.
+ *
+ * @param fourcc The 32-bit four-character-code integer to be converted, in CPU-native endinaness.
+ * @return Four-character-string built out of it.
+ */
+#define VIDEO_FOURCC_TO_STR(fourcc)                                                                \
+	((char[]){                                                                                 \
+		(char)((fourcc) & 0xFF),                                                           \
+		(char)(((fourcc) >> 8) & 0xFF),                                                    \
+		(char)(((fourcc) >> 16) & 0xFF),                                                   \
+		(char)(((fourcc) >> 24) & 0xFF),                                                   \
+		'\0'                                                                               \
+	})
+
+/**
+ * @name Bayer formats (R, G, B channels).
+ *
+ * The full color information is spread over multiple pixels.
+ *
+ * When the format includes more than 8-bit per pixel, a strategy becomes needed to pack
+ * the bits over multiple bytes, as illustrated for each format.
+ *
+ * The number above the 'R', 'r', 'G', 'g', 'B', 'b' are hints about which pixel number the
+ * following bits belong to.
+ *
  * @{
  */
 
-/** BGGR8 pixel format */
-#define VIDEO_PIX_FMT_BGGR8 video_fourcc('B', 'G', 'G', 'R') /*  8  BGBG.. GRGR.. */
-/** GBRG8 pixel format */
-#define VIDEO_PIX_FMT_GBRG8 video_fourcc('G', 'B', 'R', 'G') /*  8  GBGB.. RGRG.. */
-/** GRBG8 pixel format */
-#define VIDEO_PIX_FMT_GRBG8 video_fourcc('G', 'R', 'B', 'G') /*  8  GRGR.. BGBG.. */
-/** RGGB8 pixel format */
-#define VIDEO_PIX_FMT_RGGB8 video_fourcc('R', 'G', 'G', 'B') /*  8  RGRG.. GBGB.. */
+/**
+ * @code{.unparsed}
+ *   0          1          2          3
+ * | Bbbbbbbb | Gggggggg | Bbbbbbbb | Gggggggg | ...
+ * | Gggggggg | Rrrrrrrr | Gggggggg | Rrrrrrrr | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_BGGR8 VIDEO_FOURCC('B', 'A', '8', '1')
+
+/**
+ * @code{.unparsed}
+ *   0          1          2          3
+ * | Gggggggg | Bbbbbbbb | Gggggggg | Bbbbbbbb | ...
+ * | Rrrrrrrr | Gggggggg | Rrrrrrrr | Gggggggg | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_GBRG8 VIDEO_FOURCC('G', 'B', 'R', 'G')
+
+/**
+ * @code{.unparsed}
+ *   0          1          2          3
+ * | Gggggggg | Rrrrrrrr | Gggggggg | Rrrrrrrr | ...
+ * | Bbbbbbbb | Gggggggg | Bbbbbbbb | Gggggggg | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_GRBG8 VIDEO_FOURCC('G', 'R', 'B', 'G')
+
+/**
+ * @code{.unparsed}
+ *   0          1          2          3
+ * | Rrrrrrrr | Gggggggg | Rrrrrrrr | Gggggggg | ...
+ * | Gggggggg | Bbbbbbbb | Gggggggg | Bbbbbbbb | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_RGGB8 VIDEO_FOURCC('R', 'G', 'G', 'B')
+
+/**
+ * @code{.unparsed}
+ *   0          1          2          3          3 2 1 0
+ * | Bbbbbbbb | Gggggggg | Bbbbbbbb | Gggggggg | ggbbggbb | ...
+ * | Gggggggg | Rrrrrrrr | Gggggggg | Rrrrrrrr | rrggrrgg | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_SBGGR10P VIDEO_FOURCC('p', 'B', 'A', 'A')
+
+/**
+ * @code{.unparsed}
+ *   0          1          2          3          3 2 1 0
+ * | Gggggggg | Bbbbbbbb | Gggggggg | Bbbbbbbb | bbggbbgg | ...
+ * | Rrrrrrrr | Gggggggg | Rrrrrrrr | Gggggggg | ggrrggrr | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_SGBRG10P VIDEO_FOURCC('p', 'G', 'A', 'A')
+
+/**
+ * @code{.unparsed}
+ *   0          1          2          3          3 2 1 0
+ * | Gggggggg | Rrrrrrrr | Gggggggg | Rrrrrrrr | rrggrrgg | ...
+ * | Bbbbbbbb | Gggggggg | Bbbbbbbb | Gggggggg | ggbbggbb | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_SGRBG10P VIDEO_FOURCC('p', 'g', 'A', 'A')
+
+/**
+ * @code{.unparsed}
+ *   0          1          2          3          3 2 1 0
+ * | Rrrrrrrr | Gggggggg | Rrrrrrrr | Gggggggg | ggrrggrr | ...
+ * | Gggggggg | Bbbbbbbb | Gggggggg | Bbbbbbbb | bbggbbgg | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_SRGGB10P VIDEO_FOURCC('p', 'R', 'A', 'A')
+
+/**
+ * @code{.unparsed}
+ *   0          1          1   0      2          3          3   2
+ * | Bbbbbbbb | Gggggggg | ggggbbbb | Bbbbbbbb | Gggggggg | ggggbbbb | ...
+ * | Gggggggg | Rrrrrrrr | rrrrgggg | Gggggggg | Rrrrrrrr | rrrrgggg | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_SBGGR12P VIDEO_FOURCC('p', 'B', 'C', 'C')
+
+/**
+ * @code{.unparsed}
+ *   0          1          1   0      2          3          3   2
+ * | Gggggggg | Bbbbbbbb | bbbbgggg | Gggggggg | Bbbbbbbb | bbbbgggg | ...
+ * | Rrrrrrrr | Gggggggg | ggggrrrr | Rrrrrrrr | Gggggggg | ggggrrrr | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_SGBRG12P VIDEO_FOURCC('p', 'G', 'C', 'C')
+
+/**
+ * @code{.unparsed}
+ *   0          1          1   0      2          3          3   2
+ * | Gggggggg | Rrrrrrrr | rrrrgggg | Gggggggg | Rrrrrrrr | rrrrgggg | ...
+ * | Bbbbbbbb | Gggggggg | ggggbbbb | Bbbbbbbb | Gggggggg | ggggbbbb | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_SGRBG12P VIDEO_FOURCC('p', 'g', 'C', 'C')
+
+/**
+ * @code{.unparsed}
+ *   0          1          1   0      2          3          3   2
+ * | Rrrrrrrr | Gggggggg | ggggrrrr | Rrrrrrrr | Gggggggg | ggggrrrr | ...
+ * | Gggggggg | Bbbbbbbb | bbbbgggg | Gggggggg | Bbbbbbbb | bbbbgggg | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_SRGGB12P VIDEO_FOURCC('p', 'R', 'C', 'C')
+
+/**
+ * @code{.unparsed}
+ *   0          1          2          3          1 0      2   1    3     2
+ * | Bbbbbbbb | Gggggggg | Bbbbbbbb | Gggggggg | ggbbbbbb bbbbgggg ggggggbb | ...
+ * | Gggggggg | Rrrrrrrr | Gggggggg | Rrrrrrrr | rrgggggg ggggrrrr rrrrrrgg | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_SBGGR14P VIDEO_FOURCC('p', 'B', 'E', 'E')
+
+/**
+ * @code{.unparsed}
+ *   0          1          2          3          1 0      2   1    3     2
+ * | Gggggggg | Bbbbbbbb | Gggggggg | Bbbbbbbb | bbgggggg ggggbbbb bbbbbbgg | ...
+ * | Rrrrrrrr | Gggggggg | Rrrrrrrr | Gggggggg | ggrrrrrr rrrrgggg ggggggrr | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_SGBRG14P VIDEO_FOURCC('p', 'G', 'E', 'E')
+
+/**
+ * @code{.unparsed}
+ *   0          1          2          3          1 0      2   1    3     2
+ * | Gggggggg | Rrrrrrrr | Gggggggg | Rrrrrrrr | rrgggggg ggggrrrr rrrrrrgg | ...
+ * | Bbbbbbbb | Gggggggg | Bbbbbbbb | Gggggggg | ggbbbbbb bbbbgggg ggggggbb | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_SGRBG14P VIDEO_FOURCC('p', 'g', 'E', 'E')
+
+/**
+ * @code{.unparsed}
+ *   0          1          2          3          1 0      2   1    3     2
+ * | Rrrrrrrr | Gggggggg | Rrrrrrrr | Gggggggg | ggrrrrrr rrrrgggg ggggggrr | ...
+ * | Gggggggg | Bbbbbbbb | Gggggggg | Bbbbbbbb | bbgggggg ggggbbbb bbbbbbgg | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_SRGGB14P VIDEO_FOURCC('p', 'R', 'E', 'E')
 
 /**
  * @}
  */
 
 /**
- * @name RGB formats
+ * @name Grayscale formats
+ * Luminance (Y) channel only, in various bit depth and packing.
+ *
+ * When the format includes more than 8-bit per pixel, a strategy becomes needed to pack
+ * the bits over multiple bytes, as illustrated for each format.
+ *
+ * The number above the 'Y', 'y' are hints about which pixel number the following bits belong to.
+ *
  * @{
  */
 
-/** RGB565 pixel format */
-#define VIDEO_PIX_FMT_RGB565 video_fourcc('R', 'G', 'B', 'P') /* 16  RGB-5-6-5 */
+/**
+ * Same as Y8 (8-bit luma-only) following the standard FOURCC naming,
+ * or L8 in some graphics libraries.
+ *
+ * @code{.unparsed}
+ *   0          1          2          3
+ * | Yyyyyyyy | Yyyyyyyy | Yyyyyyyy | Yyyyyyyy | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_GREY VIDEO_FOURCC('G', 'R', 'E', 'Y')
+
+/**
+ * @code{.unparsed}
+ *   0          1          2          3          3 2 1 0
+ * | Yyyyyyyy | Yyyyyyyy | Yyyyyyyy | Yyyyyyyy | yyyyyyyy | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_Y10P VIDEO_FOURCC('Y', '1', '0', 'P')
+
+/**
+ * @code{.unparsed}
+ *   0          1          1   0      2          3          3   2
+ * | Yyyyyyyy | Yyyyyyyy | yyyyyyyy | Yyyyyyyy | Yyyyyyyy | yyyyyyyy | ...
+ * | Yyyyyyyy | Yyyyyyyy | yyyyyyyy | Yyyyyyyy | Yyyyyyyy | yyyyyyyy | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_Y12P VIDEO_FOURCC('Y', '1', '2', 'P')
 
-/** XRGB32 pixel format */
-#define VIDEO_PIX_FMT_XRGB32 video_fourcc('B', 'X', '2', '4') /* 32  XRGB-8-8-8-8 */
+/**
+ * @code{.unparsed}
+ *   0          1          2          3          1 0      2   1    3     2
+ * | Yyyyyyyy | Yyyyyyyy | Yyyyyyyy | Yyyyyyyy | yyyyyyyy yyyyyyyy yyyyyyyy | ...
+ * | Yyyyyyyy | Yyyyyyyy | Yyyyyyyy | Yyyyyyyy | yyyyyyyy yyyyyyyy yyyyyyyy | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_Y14P VIDEO_FOURCC('Y', '1', '4', 'P')
 
 /**
  * @}
  */
 
 /**
- * @name YUV formats
+ * @name RGB formats
+ * Per-color (R, G, B) channels.
  * @{
  */
 
-/** YUYV pixel format */
-#define VIDEO_PIX_FMT_YUYV video_fourcc('Y', 'U', 'Y', 'V') /* 16  Y0-Cb0 Y1-Cr0 */
+/**
+ * 5 red bits [15:11], 6 green bits [10:5], 5 blue bits [4:0].
+ * This 16-bit integer is then packed in big endian format over two bytes:
+ *
+ * @code{.unparsed}
+ *   15.....8 7......0
+ * | RrrrrGgg gggBbbbb | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_RGB565X VIDEO_FOURCC('R', 'G', 'B', 'R')
 
-/** XYUV32 pixel format */
-#define VIDEO_PIX_FMT_XYUV32 video_fourcc('X', 'Y', 'U', 'V') /* 32  XYUV-8-8-8-8 */
+/**
+ * 5 red bits [15:11], 6 green bits [10:5], 5 blue bits [4:0].
+ * This 16-bit integer is then packed in little endian format over two bytes:
+ *
+ * @code{.unparsed}
+ *   7......0 15.....8
+ * | gggBbbbb RrrrrGgg | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_RGB565 VIDEO_FOURCC('R', 'G', 'B', 'P')
 
 /**
+ * The first byte is empty (X) for each pixel.
  *
+ * @code{.unparsed}
+ * | Xxxxxxxx Rrrrrrrr Gggggggg Bbbbbbbb | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_XRGB32 VIDEO_FOURCC('B', 'X', '2', '4')
+
+/**
  * @}
  */
 
 /**
- * @name JPEG formats
+ * @name YUV formats
+ * Luminance (Y) and chrominance (U, V) channels.
  * @{
  */
 
-/** JPEG pixel format */
-#define VIDEO_PIX_FMT_JPEG video_fourcc('J', 'P', 'E', 'G') /*  8  JPEG */
+/**
+ * There is either a missing channel per pixel, U or V.
+ * The value is to be averaged over 2 pixels to get the value of individual pixel.
+ *
+ * @code{.unparsed}
+ * | Yyyyyyyy Uuuuuuuu | Yyyyyyyy Vvvvvvvv | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_YUYV VIDEO_FOURCC('Y', 'U', 'Y', 'V')
+
+/**
+ * The first byte is empty (X) for each pixel.
+ *
+ * @code{.unparsed}
+ * | Xxxxxxxx Yyyyyyyy Uuuuuuuu Vvvvvvvv | ...
+ * @endcode
+ */
+#define VIDEO_PIX_FMT_XYUV32 VIDEO_FOURCC('X', 'Y', 'U', 'V')
 
 /**
  * @}
  */
 
+/**
+ * @name Compressed formats
+ * @{
+ */
+
+/**
+ * Both JPEG (single frame) and Motion-JPEG (MJPEG, multiple JPEG frames concatenated)
+ */
+#define VIDEO_PIX_FMT_JPEG VIDEO_FOURCC('J', 'P', 'E', 'G')
+
 /**
  * @}
  */
 
 /**
- * @brief Get number of bytes per pixel of a pixel format
+ * @brief Get number of bits per pixel of a pixel format
+ *
+ * @param pixfmt FourCC pixel format value (@ref video_pixel_formats).
  *
- * @param pixfmt FourCC pixel format value (\ref video_pixel_formats).
+ * @retval 0 if the format is unhandled or if it is variable number of bits
+ * @retval bit size of one pixel for this format
  */
-static inline unsigned int video_pix_fmt_bpp(uint32_t pixfmt)
+static inline unsigned int video_bits_per_pixel(uint32_t pixfmt)
 {
 	switch (pixfmt) {
 	case VIDEO_PIX_FMT_BGGR8:
 	case VIDEO_PIX_FMT_GBRG8:
 	case VIDEO_PIX_FMT_GRBG8:
 	case VIDEO_PIX_FMT_RGGB8:
-		return 1;
+	case VIDEO_PIX_FMT_GREY:
+		return 8;
+	case VIDEO_PIX_FMT_SBGGR10P:
+	case VIDEO_PIX_FMT_SGBRG10P:
+	case VIDEO_PIX_FMT_SGRBG10P:
+	case VIDEO_PIX_FMT_SRGGB10P:
+	case VIDEO_PIX_FMT_Y10P:
+		return 10;
+	case VIDEO_PIX_FMT_SBGGR12P:
+	case VIDEO_PIX_FMT_SGBRG12P:
+	case VIDEO_PIX_FMT_SGRBG12P:
+	case VIDEO_PIX_FMT_SRGGB12P:
+	case VIDEO_PIX_FMT_Y12P:
+		return 12;
+	case VIDEO_PIX_FMT_SBGGR14P:
+	case VIDEO_PIX_FMT_SGBRG14P:
+	case VIDEO_PIX_FMT_SGRBG14P:
+	case VIDEO_PIX_FMT_SRGGB14P:
+	case VIDEO_PIX_FMT_Y14P:
+		return 14;
 	case VIDEO_PIX_FMT_RGB565:
 	case VIDEO_PIX_FMT_YUYV:
-		return 2;
+		return 16;
 	case VIDEO_PIX_FMT_XRGB32:
 	case VIDEO_PIX_FMT_XYUV32:
-		return 4;
+		return 32;
 	default:
+		/* Variable number of bits per pixel or unknown format */
 		return 0;
 	}
 }
 
+/**
+ * @}
+ */
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/zephyr/dt-bindings/adc/ad4130-adc.h b/include/zephyr/dt-bindings/adc/ad4130-adc.h
new file mode 100644
index 00000000000..6bc744dc65b
--- /dev/null
+++ b/include/zephyr/dt-bindings/adc/ad4130-adc.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_AD4130_ADC_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_AD4130_ADC_H_
+
+#include <zephyr/dt-bindings/dt-util.h>
+
+#define AD4130_ADC_AIN0                  0
+#define AD4130_ADC_AIN1                  1
+#define AD4130_ADC_AIN2                  2
+#define AD4130_ADC_AIN3                  3
+#define AD4130_ADC_AIN4                  4
+#define AD4130_ADC_AIN5                  5
+#define AD4130_ADC_AIN6                  6
+#define AD4130_ADC_AIN7                  7
+#define AD4130_ADC_AIN8                  8
+#define AD4130_ADC_AIN9                  9
+#define AD4130_ADC_AIN10                 10
+#define AD4130_ADC_AIN11                 11
+#define AD4130_ADC_AIN12                 12
+#define AD4130_ADC_AIN13                 13
+#define AD4130_ADC_AIN14                 14
+#define AD4130_ADC_AIN15                 15
+#define AD4130_ADC_TEMP_SENSOR           16
+#define AD4130_ADC_AVSS                  17
+#define AD4130_ADC_INTERNAL_REF          18
+#define AD4130_ADC_DGND                  19
+#define AD4130_ADC_AVDD_AVSS_DIV6_PLUS   20
+#define AD4130_ADC_AVDD_AVSS_DIV6_MINUS  21
+#define AD4130_ADC_IOVDD_DGND_DIV6_PLUS  22
+#define AD4130_ADC_IOVDD_DGND_DIV6_MINUS 23
+#define AD4130_ADC_ALDO_AVSS_DIV6_PLUS   24
+#define AD4130_ADC_ALDO_AVSS_DIV6_MINUS  25
+#define AD4130_ADC_DLDO_DGND_DIV6_PLUS   26
+#define AD4130_ADC_DLDO_DGND_DIV6_MINUS  27
+#define AD4130_ADC_V_MV_P                28
+#define AD4130_ADC_V_MV_M                29
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_AD4130_ADC_H_ */
diff --git a/include/zephyr/dt-bindings/adc/ad7124-adc.h b/include/zephyr/dt-bindings/adc/ad7124-adc.h
new file mode 100644
index 00000000000..d35234a409e
--- /dev/null
+++ b/include/zephyr/dt-bindings/adc/ad7124-adc.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_AD7124_ADC_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_AD7124_ADC_H_
+
+#include <zephyr/dt-bindings/dt-util.h>
+
+#define AD7124_ADC_AIN0                  0
+#define AD7124_ADC_AIN1                  1
+#define AD7124_ADC_AIN2                  2
+#define AD7124_ADC_AIN3                  3
+#define AD7124_ADC_AIN4                  4
+#define AD7124_ADC_AIN5                  5
+#define AD7124_ADC_AIN6                  6
+#define AD7124_ADC_AIN7                  7
+#define AD7124_ADC_AIN8                  8
+#define AD7124_ADC_AIN9                  9
+#define AD7124_ADC_AIN10                 10
+#define AD7124_ADC_AIN11                 11
+#define AD7124_ADC_AIN12                 12
+#define AD7124_ADC_AIN13                 13
+#define AD7124_ADC_AIN14                 14
+#define AD7124_ADC_AIN15                 15
+#define AD7124_ADC_TEMP_SENSOR           16
+#define AD7124_ADC_AVSS                  17
+#define AD7124_ADC_INTERNAL_REF          18
+#define AD7124_ADC_DGND                  19
+#define AD7124_ADC_AVDD_AVSS_DIV6_PLUS   20
+#define AD7124_ADC_AVDD_AVSS_DIV6_MINUS  21
+#define AD7124_ADC_IOVDD_DGND_DIV6_PLUS  22
+#define AD7124_ADC_IOVDD_DGND_DIV6_MINUS 23
+#define AD7124_ADC_ALDO_AVSS_DIV6_PLUS   24
+#define AD7124_ADC_ALDO_AVSS_DIV6_MINUS  25
+#define AD7124_ADC_DLDO_DGND_DIV6_PLUS   26
+#define AD7124_ADC_DLDO_DGND_DIV6_MINUS  27
+#define AD7124_ADC_V_20MV_P              28
+#define AD7124_ADC_V_20MV_M              29
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_AD7124_ADC_H_ */
diff --git a/include/zephyr/dt-bindings/adc/ads114s0x_adc.h b/include/zephyr/dt-bindings/adc/ads114s0x_adc.h
deleted file mode 100644
index c54b1c4c07b..00000000000
--- a/include/zephyr/dt-bindings/adc/ads114s0x_adc.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright (c) 2023 SILA Embedded Solutions GmbH
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_ADS114S0X_ADC_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_ADS114S0X_ADC_H_
-
-/*
- * These are the available data rates described as samples per second. They
- * can be used with the time unit ticks for the acquisition time.
- */
-#define ADS114S0X_CONFIG_DR_2_5		0
-#define ADS114S0X_CONFIG_DR_5		1
-#define ADS114S0X_CONFIG_DR_10		2
-#define ADS114S0X_CONFIG_DR_16_6	3
-#define ADS114S0X_CONFIG_DR_20		4
-#define ADS114S0X_CONFIG_DR_50		5
-#define ADS114S0X_CONFIG_DR_60		6
-#define ADS114S0X_CONFIG_DR_100		7
-#define ADS114S0X_CONFIG_DR_200		8
-#define ADS114S0X_CONFIG_DR_400		9
-#define ADS114S0X_CONFIG_DR_800		10
-#define ADS114S0X_CONFIG_DR_1000	11
-#define ADS114S0X_CONFIG_DR_2000	12
-#define ADS114S0X_CONFIG_DR_4000	13
-
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_ADS114S0X_ADC_H_ */
diff --git a/include/zephyr/dt-bindings/adc/ads1x4s0x_adc.h b/include/zephyr/dt-bindings/adc/ads1x4s0x_adc.h
new file mode 100644
index 00000000000..51367aa0447
--- /dev/null
+++ b/include/zephyr/dt-bindings/adc/ads1x4s0x_adc.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2023 SILA Embedded Solutions GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_ADS1X4S0X_ADC_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_ADS1X4S0X_ADC_H_
+
+/*
+ * These are the available data rates described as samples per second. They
+ * can be used with the time unit ticks for the acquisition time.
+ */
+#define ADS1X4S0X_CONFIG_DR_2_5		0
+#define ADS1X4S0X_CONFIG_DR_5		1
+#define ADS1X4S0X_CONFIG_DR_10		2
+#define ADS1X4S0X_CONFIG_DR_16_6	3
+#define ADS1X4S0X_CONFIG_DR_20		4
+#define ADS1X4S0X_CONFIG_DR_50		5
+#define ADS1X4S0X_CONFIG_DR_60		6
+#define ADS1X4S0X_CONFIG_DR_100		7
+#define ADS1X4S0X_CONFIG_DR_200		8
+#define ADS1X4S0X_CONFIG_DR_400		9
+#define ADS1X4S0X_CONFIG_DR_800		10
+#define ADS1X4S0X_CONFIG_DR_1000	11
+#define ADS1X4S0X_CONFIG_DR_2000	12
+#define ADS1X4S0X_CONFIG_DR_4000	13
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_ADS1X4S0X_ADC_H_ */
diff --git a/include/zephyr/dt-bindings/adc/silabs-adc.h b/include/zephyr/dt-bindings/adc/silabs-adc.h
new file mode 100644
index 00000000000..367ed2627ad
--- /dev/null
+++ b/include/zephyr/dt-bindings/adc/silabs-adc.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * This file was generated by the script gen_adc.py in the hal_silabs module.
+ * Do not manually edit.
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ADC_SILABS_ADC_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_ADC_SILABS_ADC_H_
+
+#define IADC_INPUT_GND      0x0
+#define IADC_INPUT_AVDD     0x10
+#define IADC_INPUT_IOVDD    0x11
+#define IADC_INPUT_VBAT     0x12
+#define IADC_INPUT_DVDD     0x14
+#define IADC_INPUT_DECOUPLE 0x17
+#define IADC_INPUT_DAC0     0x20
+#define IADC_INPUT_DAC1     0x20
+#define IADC_INPUT_AIN0     0x40
+#define IADC_INPUT_AIN1     0x40
+#define IADC_INPUT_AIN2     0x50
+#define IADC_INPUT_AIN3     0x50
+#define IADC_INPUT_PA0      0x80
+#define IADC_INPUT_PA1      0x81
+#define IADC_INPUT_PA2      0x82
+#define IADC_INPUT_PA3      0x83
+#define IADC_INPUT_PA4      0x84
+#define IADC_INPUT_PA5      0x85
+#define IADC_INPUT_PA6      0x86
+#define IADC_INPUT_PA7      0x87
+#define IADC_INPUT_PA8      0x88
+#define IADC_INPUT_PA9      0x89
+#define IADC_INPUT_PA10     0x8a
+#define IADC_INPUT_PA11     0x8b
+#define IADC_INPUT_PA12     0x8c
+#define IADC_INPUT_PA13     0x8d
+#define IADC_INPUT_PA14     0x8e
+#define IADC_INPUT_PA15     0x8f
+#define IADC_INPUT_PB0      0x90
+#define IADC_INPUT_PB1      0x91
+#define IADC_INPUT_PB2      0x92
+#define IADC_INPUT_PB3      0x93
+#define IADC_INPUT_PB4      0x94
+#define IADC_INPUT_PB5      0x95
+#define IADC_INPUT_PB6      0x96
+#define IADC_INPUT_PB7      0x97
+#define IADC_INPUT_PB8      0x98
+#define IADC_INPUT_PB9      0x99
+#define IADC_INPUT_PB10     0x9a
+#define IADC_INPUT_PB11     0x9b
+#define IADC_INPUT_PB12     0x9c
+#define IADC_INPUT_PB13     0x9d
+#define IADC_INPUT_PB14     0x9e
+#define IADC_INPUT_PB15     0x9f
+#define IADC_INPUT_PC0      0xa0
+#define IADC_INPUT_PC1      0xa1
+#define IADC_INPUT_PC2      0xa2
+#define IADC_INPUT_PC3      0xa3
+#define IADC_INPUT_PC4      0xa4
+#define IADC_INPUT_PC5      0xa5
+#define IADC_INPUT_PC6      0xa6
+#define IADC_INPUT_PC7      0xa7
+#define IADC_INPUT_PC8      0xa8
+#define IADC_INPUT_PC9      0xa9
+#define IADC_INPUT_PC10     0xaa
+#define IADC_INPUT_PC11     0xab
+#define IADC_INPUT_PC12     0xac
+#define IADC_INPUT_PC13     0xad
+#define IADC_INPUT_PC14     0xae
+#define IADC_INPUT_PC15     0xaf
+#define IADC_INPUT_PD0      0xb0
+#define IADC_INPUT_PD1      0xb1
+#define IADC_INPUT_PD2      0xb2
+#define IADC_INPUT_PD3      0xb3
+#define IADC_INPUT_PD4      0xb4
+#define IADC_INPUT_PD5      0xb5
+#define IADC_INPUT_PD6      0xb6
+#define IADC_INPUT_PD7      0xb7
+#define IADC_INPUT_PD8      0xb8
+#define IADC_INPUT_PD9      0xb9
+#define IADC_INPUT_PD10     0xba
+#define IADC_INPUT_PD11     0xbb
+#define IADC_INPUT_PD12     0xbc
+#define IADC_INPUT_PD13     0xbd
+#define IADC_INPUT_PD14     0xbe
+#define IADC_INPUT_PD15     0xbf
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ADC_SILABS_ADC_H_ */
diff --git a/include/zephyr/dt-bindings/clock/ch32v20x_30x-clocks.h b/include/zephyr/dt-bindings/clock/ch32v20x_30x-clocks.h
new file mode 100644
index 00000000000..e600f9c9966
--- /dev/null
+++ b/include/zephyr/dt-bindings/clock/ch32v20x_30x-clocks.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __CH32V20X_V30X_CLOCKS_H__
+#define __CH32V20X_V30X_CLOCKS_H__
+
+#define CH32V20X_V30X_AHB_PCENR_OFFSET  0
+#define CH32V20X_V30X_APB2_PCENR_OFFSET 1
+#define CH32V20X_V30X_APB1_PCENR_OFFSET 2
+
+#define CH32V20X_V30X_CLOCK_CONFIG(bus, bit) (((CH32V20X_V30X_##bus##_PCENR_OFFSET) << 5) | (bit))
+
+#define CH32V20X_V30X_CLOCK_DMA1     CH32V20X_V30X_CLOCK_CONFIG(AHB, 0)
+#define CH32V20X_V30X_CLOCK_DMA2     CH32V20X_V30X_CLOCK_CONFIG(AHB, 1)
+#define CH32V20X_V30X_CLOCK_SRAM     CH32V20X_V30X_CLOCK_CONFIG(AHB, 2)
+#define CH32V20X_V30X_CLOCK_FLITF    CH32V20X_V30X_CLOCK_CONFIG(AHB, 4)
+#define CH32V20X_V30X_CLOCK_CRC      CH32V20X_V30X_CLOCK_CONFIG(AHB, 6)
+#define CH32V20X_V30X_CLOCK_FSMC     CH32V20X_V30X_CLOCK_CONFIG(AHB, 8)
+#define CH32V20X_V30X_CLOCK_RNG      CH32V20X_V30X_CLOCK_CONFIG(AHB, 9)
+#define CH32V20X_V30X_CLOCK_SDIO     CH32V20X_V30X_CLOCK_CONFIG(AHB, 10)
+#define CH32V20X_V30X_CLOCK_USBHS    CH32V20X_V30X_CLOCK_CONFIG(AHB, 11)
+#define CH32V20X_V30X_CLOCK_OTG_FS   CH32V20X_V30X_CLOCK_CONFIG(AHB, 12)
+#define CH32V20X_V30X_CLOCK_DVP      CH32V20X_V30X_CLOCK_CONFIG(AHB, 13)
+#define CH32V20X_V30X_CLOCK_ETHMAC   CH32V20X_V30X_CLOCK_CONFIG(AHB, 14)
+#define CH32V20X_V30X_CLOCK_ETHMACTX CH32V20X_V30X_CLOCK_CONFIG(AHB, 15)
+#define CH32V20X_V30X_CLOCK_ETHMACRX CH32V20X_V30X_CLOCK_CONFIG(AHB, 16)
+#define CH32V20X_V30X_CLOCK_BLEC     CH32V20X_V30X_CLOCK_CONFIG(AHB, 16)
+#define CH32V20X_V30X_CLOCK_BLES     CH32V20X_V30X_CLOCK_CONFIG(AHB, 17)
+
+#define CH32V20X_V30X_CLOCK_AFIO   CH32V20X_V30X_CLOCK_CONFIG(APB2, 0)
+#define CH32V20X_V30X_CLOCK_IOPA   CH32V20X_V30X_CLOCK_CONFIG(APB2, 2)
+#define CH32V20X_V30X_CLOCK_IOPB   CH32V20X_V30X_CLOCK_CONFIG(APB2, 3)
+#define CH32V20X_V30X_CLOCK_IOPC   CH32V20X_V30X_CLOCK_CONFIG(APB2, 4)
+#define CH32V20X_V30X_CLOCK_IOPD   CH32V20X_V30X_CLOCK_CONFIG(APB2, 5)
+#define CH32V20X_V30X_CLOCK_IOPE   CH32V20X_V30X_CLOCK_CONFIG(APB2, 6)
+#define CH32V20X_V30X_CLOCK_ADC1   CH32V20X_V30X_CLOCK_CONFIG(APB2, 9)
+#define CH32V20X_V30X_CLOCK_ADC2   CH32V20X_V30X_CLOCK_CONFIG(APB2, 10)
+#define CH32V20X_V30X_CLOCK_TIM1   CH32V20X_V30X_CLOCK_CONFIG(APB2, 11)
+#define CH32V20X_V30X_CLOCK_SPI1   CH32V20X_V30X_CLOCK_CONFIG(APB2, 12)
+#define CH32V20X_V30X_CLOCK_TIM8   CH32V20X_V30X_CLOCK_CONFIG(APB2, 13)
+#define CH32V20X_V30X_CLOCK_USART1 CH32V20X_V30X_CLOCK_CONFIG(APB2, 14)
+#define CH32V20X_V30X_CLOCK_TIM9   CH32V20X_V30X_CLOCK_CONFIG(APB2, 19)
+#define CH32V20X_V30X_CLOCK_TIM10  CH32V20X_V30X_CLOCK_CONFIG(APB2, 20)
+
+#define CH32V20X_V30X_CLOCK_TIM2   CH32V20X_V30X_CLOCK_CONFIG(APB1, 0)
+#define CH32V20X_V30X_CLOCK_TIM3   CH32V20X_V30X_CLOCK_CONFIG(APB1, 1)
+#define CH32V20X_V30X_CLOCK_TIM4   CH32V20X_V30X_CLOCK_CONFIG(APB1, 2)
+#define CH32V20X_V30X_CLOCK_TIM5   CH32V20X_V30X_CLOCK_CONFIG(APB1, 3)
+#define CH32V20X_V30X_CLOCK_TIM6   CH32V20X_V30X_CLOCK_CONFIG(APB1, 4)
+#define CH32V20X_V30X_CLOCK_TIM7   CH32V20X_V30X_CLOCK_CONFIG(APB1, 5)
+#define CH32V20X_V30X_CLOCK_USART6 CH32V20X_V30X_CLOCK_CONFIG(APB1, 6)
+#define CH32V20X_V30X_CLOCK_USART7 CH32V20X_V30X_CLOCK_CONFIG(APB1, 7)
+#define CH32V20X_V30X_CLOCK_USART8 CH32V20X_V30X_CLOCK_CONFIG(APB1, 8)
+#define CH32V20X_V30X_CLOCK_WWDG   CH32V20X_V30X_CLOCK_CONFIG(APB1, 11)
+#define CH32V20X_V30X_CLOCK_SPI2   CH32V20X_V30X_CLOCK_CONFIG(APB1, 14)
+#define CH32V20X_V30X_CLOCK_SPI3   CH32V20X_V30X_CLOCK_CONFIG(APB1, 15)
+#define CH32V20X_V30X_CLOCK_USART2 CH32V20X_V30X_CLOCK_CONFIG(APB1, 17)
+#define CH32V20X_V30X_CLOCK_USART3 CH32V20X_V30X_CLOCK_CONFIG(APB1, 18)
+#define CH32V20X_V30X_CLOCK_USART4 CH32V20X_V30X_CLOCK_CONFIG(APB1, 19)
+#define CH32V20X_V30X_CLOCK_USART5 CH32V20X_V30X_CLOCK_CONFIG(APB1, 20)
+#define CH32V20X_V30X_CLOCK_I2C1   CH32V20X_V30X_CLOCK_CONFIG(APB1, 21)
+#define CH32V20X_V30X_CLOCK_I2C2   CH32V20X_V30X_CLOCK_CONFIG(APB1, 22)
+#define CH32V20X_V30X_CLOCK_USBD   CH32V20X_V30X_CLOCK_CONFIG(APB1, 23)
+#define CH32V20X_V30X_CLOCK_CAN1   CH32V20X_V30X_CLOCK_CONFIG(APB1, 25)
+#define CH32V20X_V30X_CLOCK_CAN2   CH32V20X_V30X_CLOCK_CONFIG(APB1, 26)
+#define CH32V20X_V30X_CLOCK_BKP    CH32V20X_V30X_CLOCK_CONFIG(APB1, 27)
+#define CH32V20X_V30X_CLOCK_PWR    CH32V20X_V30X_CLOCK_CONFIG(APB1, 28)
+#define CH32V20X_V30X_CLOCK_DAC    CH32V20X_V30X_CLOCK_CONFIG(APB1, 29)
+
+#endif
diff --git a/include/zephyr/dt-bindings/clock/esp32c6_clock.h b/include/zephyr/dt-bindings/clock/esp32c6_clock.h
index 9aa39b2c51e..b3264125790 100644
--- a/include/zephyr/dt-bindings/clock/esp32c6_clock.h
+++ b/include/zephyr/dt-bindings/clock/esp32c6_clock.h
@@ -13,28 +13,28 @@
 #define ESP32_CLK_SRC_RC_FAST  2U
 
 /* Supported CPU frequencies */
-#define ESP32_CLK_CPU_PLL_80M     80000000
-#define ESP32_CLK_CPU_PLL_160M    160000000
+#define ESP32_CLK_CPU_PLL_80M      80000000
+#define ESP32_CLK_CPU_PLL_160M     160000000
 #define ESP32_CLK_CPU_RC_FAST_FREQ 17500000
 
 /* Supported XTAL Frequencies */
-#define ESP32_CLK_XTAL_32M             32000000
-#define ESP32_CLK_XTAL_40M             40000000
+#define ESP32_CLK_XTAL_32M 32000000
+#define ESP32_CLK_XTAL_40M 40000000
 
 /* Supported RTC fast clock sources */
 #define ESP32_RTC_FAST_CLK_SRC_RC_FAST 0
 #define ESP32_RTC_FAST_CLK_SRC_XTAL_D2 1
 
 /* Supported RTC slow clock frequencies */
-#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW      0
-#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K      1
-#define ESP32_RTC_SLOW_CLK_SRC_RC32K        2
-#define ESP32_RTC_SLOW_CLK_32K_EXT_OSC      9
+#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW 0
+#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K 1
+#define ESP32_RTC_SLOW_CLK_SRC_RC32K   2
+#define ESP32_RTC_SLOW_CLK_32K_EXT_OSC 9
 
 /* RTC slow clock frequencies */
-#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ      136000
-#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ      32768
-#define ESP32_RTC_SLOW_CLK_SRC_RC32K_FREQ        32768
+#define ESP32_RTC_SLOW_CLK_SRC_RC_SLOW_FREQ 136000
+#define ESP32_RTC_SLOW_CLK_SRC_XTAL32K_FREQ 32768
+#define ESP32_RTC_SLOW_CLK_SRC_RC32K_FREQ   32768
 
 /* Modules IDs
  * These IDs are actually offsets in CLK and RST Control registers.
@@ -44,44 +44,49 @@
  * Basic Modules
  * Registers: DPORT_PERIP_CLK_EN_REG, DPORT_PERIP_RST_EN_REG
  */
-#define ESP32_LEDC_MODULE              0
-#define ESP32_UART0_MODULE             1
-#define ESP32_UART1_MODULE             2
-#define ESP32_USB_MODULE               3
-#define ESP32_I2C0_MODULE              4
-#define ESP32_I2S1_MODULE              5
-#define ESP32_TIMG0_MODULE             6
-#define ESP32_TIMG1_MODULE             7
-#define ESP32_UHCI0_MODULE             8
-#define ESP32_RMT_MODULE               9
-#define ESP32_PCNT_MODULE             10
-#define ESP32_SPI_MODULE              11
-#define ESP32_SPI2_MODULE             12
-#define ESP32_TWAI0_MODULE            13
-#define ESP32_TWAI1_MODULE            14
-#define ESP32_RNG_MODULE              15
-#define ESP32_RSA_MODULE              16
-#define ESP32_AES_MODULE              17
-#define ESP32_SHA_MODULE              18
-#define ESP32_ECC_MODULE              19
-#define ESP32_HMAC_MODULE             20
-#define ESP32_DS_MODULE               21
-#define ESP32_SDIO_SLAVE_MODULE       22
-#define ESP32_GDMA_MODULE             23
-#define ESP32_MCPWM0_MODULE           24
-#define ESP32_ETM_MODULE              25
-#define ESP32_PARLIO_MODULE           26
-#define ESP32_SYSTIMER_MODULE         27
-#define ESP32_SARADC_MODULE           28
-#define ESP32_TEMPSENSOR_MODULE       29
-#define ESP32_REGDMA_MODULE           30
-#define ESP32_LP_I2C0_MODULE          31
+#define ESP32_LEDC_MODULE                0
+#define ESP32_UART0_MODULE               1
+#define ESP32_UART1_MODULE               2
+#define ESP32_USB_MODULE                 3
+#define ESP32_I2C0_MODULE                4
+#define ESP32_I2S1_MODULE                5
+#define ESP32_TIMG0_MODULE               6
+#define ESP32_TIMG1_MODULE               7
+#define ESP32_UHCI0_MODULE               8
+#define ESP32_RMT_MODULE                 9
+#define ESP32_PCNT_MODULE                10
+#define ESP32_SPI_MODULE                 11
+#define ESP32_SPI2_MODULE                12
+#define ESP32_TWAI0_MODULE               13
+#define ESP32_TWAI1_MODULE               14
+#define ESP32_RNG_MODULE                 15
+#define ESP32_RSA_MODULE                 16
+#define ESP32_AES_MODULE                 17
+#define ESP32_SHA_MODULE                 18
+#define ESP32_ECC_MODULE                 19
+#define ESP32_HMAC_MODULE                20
+#define ESP32_DS_MODULE                  21
+#define ESP32_SDIO_SLAVE_MODULE          22
+#define ESP32_GDMA_MODULE                23
+#define ESP32_MCPWM0_MODULE              24
+#define ESP32_ETM_MODULE                 25
+#define ESP32_PARLIO_MODULE              26
+#define ESP32_SYSTIMER_MODULE            27
+#define ESP32_SARADC_MODULE              28
+#define ESP32_TEMPSENSOR_MODULE          29
+#define ESP32_ASSIST_DEBUG_MODULE        30
+/* LP peripherals */
+#define ESP32_LP_I2C0_MODULE             31
+#define ESP32_LP_UART0_MODULE            32
 /* Peripherals clock managed by the modem_clock driver must be listed last */
-#define ESP32_WIFI_MODULE             32
-#define ESP32_BT_MODULE               33
-#define ESP32_IEEE802154_MODULE       34
-#define ESP32_COEX_MODULE             35
-#define ESP32_PHY_MODULE              36
-#define ESP32_MODULE_MAX              37
+#define ESP32_WIFI_MODULE                33
+#define ESP32_BT_MODULE                  34
+#define ESP32_IEEE802154_MODULE          35
+#define ESP32_COEX_MODULE                36
+#define ESP32_PHY_MODULE                 37
+#define ESP32_ANA_I2C_MASTER_MODULE      38
+#define ESP32_MODEM_ETM_MODULE           39
+#define ESP32_MODEM_ADC_COMMON_FE_MODULE 40
+#define ESP32_MODULE_MAX                 41
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_ESP32C6_H_ */
diff --git a/include/zephyr/dt-bindings/clock/imx_ccm.h b/include/zephyr/dt-bindings/clock/imx_ccm.h
index 7a4876cc43f..4f2f1bb0952 100644
--- a/include/zephyr/dt-bindings/clock/imx_ccm.h
+++ b/include/zephyr/dt-bindings/clock/imx_ccm.h
@@ -72,4 +72,11 @@
 
 #define IMX_CCM_GPT_IPG_CLK		0x1300UL
 
+#define IMX_CCM_I2C1_CLK		0x1400UL
+#define IMX_CCM_I2C2_CLK		0x1401UL
+#define IMX_CCM_I2C3_CLK		0x1402UL
+#define IMX_CCM_I2C4_CLK		0x1403UL
+#define IMX_CCM_I2C5_CLK		0x1404UL
+#define IMX_CCM_I2C6_CLK		0x1405UL
+
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_H_ */
diff --git a/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h b/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h
index 89a43c734e2..e5035584cbe 100644
--- a/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h
+++ b/include/zephyr/dt-bindings/clock/imx_ccm_rev2.h
@@ -58,10 +58,13 @@
 
 /* LPSPI */
 #define IMX_CCM_LPSPI_CLK              0x500UL
+#define IMX_CCM_LPSPI0102_CLK          0x500UL
 #define IMX_CCM_LPSPI1_CLK             0x500UL
 #define IMX_CCM_LPSPI2_CLK             0x501UL
+#define IMX_CCM_LPSPI0304_CLK          0x501UL
 #define IMX_CCM_LPSPI3_CLK             0x502UL
 #define IMX_CCM_LPSPI4_CLK             0x503UL
+#define IMX_CCM_LPSPI0506_CLK          0x502UL
 #define IMX_CCM_LPSPI5_CLK             0x504UL
 #define IMX_CCM_LPSPI6_CLK             0x505UL
 #define IMX_CCM_LPSPI7_CLK             0x506UL
@@ -74,6 +77,8 @@
 /* DMA  */
 #define IMX_CCM_EDMA_CLK               0x700UL
 #define IMX_CCM_EDMA_LPSR_CLK          0x701UL
+#define IMX_CCM_EDMA3_CLK              0x700UL
+#define IMX_CCM_EDMA4_CLK              0x701UL
 
 /* PWM */
 #define IMX_CCM_PWM_CLK                0x800UL
diff --git a/include/zephyr/dt-bindings/clock/ite-it51xxx-clock.h b/include/zephyr/dt-bindings/clock/ite-it51xxx-clock.h
new file mode 100644
index 00000000000..d2e2a7dd58d
--- /dev/null
+++ b/include/zephyr/dt-bindings/clock/ite-it51xxx-clock.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IT51XXX_CLOCK_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IT51XXX_CLOCK_H_
+
+/* Clock control */
+#define IT51XXX_ECPM_CGCTRL2R_OFF 0x02
+#define IT51XXX_ECPM_CGCTRL3R_OFF 0x05
+#define IT51XXX_ECPM_CGCTRL4R_OFF 0x09
+
+/* Clock PLL frequency */
+#define PLL_18400_KHZ 0
+#define PLL_32300_KHZ 1
+#define PLL_64500_KHZ 2
+#define PLL_48000_KHZ 3
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IT51XXX_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h
index 77b5741b23d..b98f2a1079e 100644
--- a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h
+++ b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h
@@ -21,6 +21,9 @@
 #define MCUX_CTIMER2_CLK 2
 #define MCUX_CTIMER3_CLK 3
 #define MCUX_CTIMER4_CLK 4
+#define MCUX_CTIMER5_CLK 5
+#define MCUX_CTIMER6_CLK 6
+#define MCUX_CTIMER7_CLK 7
 
 #define MCUX_FLEXCOMM0_CLK  MCUX_LPC_CLK_ID(0x01, 0x00)
 #define MCUX_FLEXCOMM1_CLK  MCUX_LPC_CLK_ID(0x01, 0x01)
@@ -40,9 +43,16 @@
 #define MCUX_FLEXCOMM14_CLK MCUX_HS_SPI_CLK
 #define MCUX_PMIC_I2C_CLK   MCUX_LPC_CLK_ID(0x01, 0x0F)
 #define MCUX_HS_SPI1_CLK    MCUX_LPC_CLK_ID(0x01, 0x10)
-
-#define MCUX_USDHC1_CLK MCUX_LPC_CLK_ID(0x02, 0x00)
-#define MCUX_USDHC2_CLK MCUX_LPC_CLK_ID(0x02, 0x01)
+#define MCUX_FLEXCOMM17_CLK MCUX_LPC_CLK_ID(0x01, 0x11)
+#define MCUX_FLEXCOMM18_CLK MCUX_LPC_CLK_ID(0x01, 0x12)
+#define MCUX_FLEXCOMM19_CLK MCUX_LPC_CLK_ID(0x01, 0x13)
+#define MCUX_FLEXCOMM20_CLK MCUX_LPC_CLK_ID(0x01, 0x14)
+/* On RT7xx, flexcomm14 and 16 only can be LPSPI, flexcomm15 only can be I2C. */
+#define MCUX_LPSPI14_CLK    MCUX_LPC_CLK_ID(0x01, 0x24)
+#define MCUX_LPI2C15_CLK    MCUX_LPC_CLK_ID(0x01, 0x25)
+#define MCUX_LPSPI16_CLK    MCUX_LPC_CLK_ID(0x01, 0x26)
+#define MCUX_USDHC1_CLK     MCUX_LPC_CLK_ID(0x02, 0x00)
+#define MCUX_USDHC2_CLK     MCUX_LPC_CLK_ID(0x02, 0x01)
 
 #define MCUX_MCAN_CLK MCUX_LPC_CLK_ID(0x03, 0x00)
 
@@ -103,4 +113,15 @@
 #define MCUX_LPI2C2_CLK MCUX_LPC_CLK_ID(0x14, 0x02)
 #define MCUX_LPI2C3_CLK MCUX_LPC_CLK_ID(0x14, 0x03)
 
+#define MCUX_XSPI_CLK  MCUX_LPC_CLK_ID(0x15, 0x00)
+#define MCUX_XSPI0_CLK MCUX_LPC_CLK_ID(0x15, 0x00)
+#define MCUX_XSPI1_CLK MCUX_LPC_CLK_ID(0x15, 0x01)
+#define MCUX_XSPI2_CLK MCUX_LPC_CLK_ID(0x15, 0x02)
+
+#define MCUX_SAI0_CLK MCUX_LPC_CLK_ID(0x16, 0x00)
+#define MCUX_SAI1_CLK MCUX_LPC_CLK_ID(0x16, 0x01)
+
+#define MCUX_LPSPI0_CLK MCUX_LPC_CLK_ID(0x17, 0x00)
+#define MCUX_LPSPI1_CLK MCUX_LPC_CLK_ID(0x17, 0x01)
+
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */
diff --git a/include/zephyr/dt-bindings/clock/numaker_m55m1x_clock.h b/include/zephyr/dt-bindings/clock/numaker_m55m1x_clock.h
new file mode 100644
index 00000000000..6cc231a7fe4
--- /dev/null
+++ b/include/zephyr/dt-bindings/clock/numaker_m55m1x_clock.h
@@ -0,0 +1,436 @@
+/*
+ * Copyright (c) 2025 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M55M1X_CLOCK_H
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_NUMAKER_M55M1X_CLOCK_H
+
+#define NUMAKER_CLK_SCLKSEL_SCLKSEL_HIRC 0x00000000
+#define NUMAKER_CLK_SCLKSEL_SCLKSEL_MIRC 0x00000001
+#define NUMAKER_CLK_SCLKSEL_SCLKSEL_HIRC48M 0x00000002
+#define NUMAKER_CLK_SCLKSEL_SCLKSEL_HXT 0x00000003
+#define NUMAKER_CLK_SCLKSEL_SCLKSEL_APLL0 0x00000004
+#define NUMAKER_CLK_BPWMSEL_BPWM0SEL_PCLK0 0x00000000
+#define NUMAKER_CLK_BPWMSEL_BPWM0SEL_HCLK0 0x00000001
+#define NUMAKER_CLK_BPWMSEL_BPWM1SEL_PCLK2 0x00000000
+#define NUMAKER_CLK_BPWMSEL_BPWM1SEL_HCLK0 0x00000010
+#define NUMAKER_CLK_CANFDSEL_CANFD0SEL_HXT 0x00000000
+#define NUMAKER_CLK_CANFDSEL_CANFD0SEL_APLL0_DIV2 0x00000001
+#define NUMAKER_CLK_CANFDSEL_CANFD0SEL_HCLK0 0x00000002
+#define NUMAKER_CLK_CANFDSEL_CANFD0SEL_HIRC 0x00000003
+#define NUMAKER_CLK_CANFDSEL_CANFD0SEL_HIRC48M_DIV4 0x00000004
+#define NUMAKER_CLK_CANFDSEL_CANFD1SEL_HXT 0x00000000
+#define NUMAKER_CLK_CANFDSEL_CANFD1SEL_APLL0_DIV2 0x00000010
+#define NUMAKER_CLK_CANFDSEL_CANFD1SEL_HCLK0 0x00000020
+#define NUMAKER_CLK_CANFDSEL_CANFD1SEL_HIRC 0x00000030
+#define NUMAKER_CLK_CANFDSEL_CANFD1SEL_HIRC48M_DIV4 0x00000040
+#define NUMAKER_CLK_CCAPSEL_CCAP0SEL_MIRC 0x00000000
+#define NUMAKER_CLK_CCAPSEL_CCAP0SEL_HCLK2 0x00000001
+#define NUMAKER_CLK_CCAPSEL_CCAP0SEL_HIRC 0x00000002
+#define NUMAKER_CLK_CCAPSEL_CCAP0SEL_APLL0_DIV2 0x00000003
+#define NUMAKER_CLK_CCAPSEL_CCAP0SEL_HXT 0x00000004
+#define NUMAKER_CLK_CLKOSEL_CLKOSEL_SYSCLK 0x00000000
+#define NUMAKER_CLK_CLKOSEL_CLKOSEL_ACLK 0x00000001
+#define NUMAKER_CLK_CLKOSEL_CLKOSEL_HCLK0 0x00000002
+#define NUMAKER_CLK_CLKOSEL_CLKOSEL_HCLK1 0x00000003
+#define NUMAKER_CLK_CLKOSEL_CLKOSEL_HCLK2 0x00000004
+#define NUMAKER_CLK_CLKOSEL_CLKOSEL_APLL0_DIV2 0x00000005
+#define NUMAKER_CLK_CLKOSEL_CLKOSEL_APLL1_DIV2 0x00000006
+#define NUMAKER_CLK_CLKOSEL_CLKOSEL_HIRC48M 0x00000007
+#define NUMAKER_CLK_CLKOSEL_CLKOSEL_HXT 0x00000008
+#define NUMAKER_CLK_CLKOSEL_CLKOSEL_HIRC 0x00000009
+#define NUMAKER_CLK_CLKOSEL_CLKOSEL_MIRC 0x0000000A
+#define NUMAKER_CLK_CLKOSEL_CLKOSEL_LXT 0x0000000B
+#define NUMAKER_CLK_CLKOSEL_CLKOSEL_LIRC 0x0000000C
+#define NUMAKER_CLK_DMICSEL_DMIC0SEL_HXT 0x00000000
+#define NUMAKER_CLK_DMICSEL_DMIC0SEL_APLL1_DIV2 0x00000001
+#define NUMAKER_CLK_DMICSEL_DMIC0SEL_MIRC 0x00000002
+#define NUMAKER_CLK_DMICSEL_DMIC0SEL_HIRC 0x00000003
+#define NUMAKER_CLK_DMICSEL_DMIC0SEL_HIRC48M 0x00000004
+#define NUMAKER_CLK_DMICSEL_DMIC0SEL_PCLK4 0x00000005
+#define NUMAKER_CLK_DMICSEL_VAD0SEL_PCLK4 0x00000000
+#define NUMAKER_CLK_DMICSEL_VAD0SEL_MIRC 0x00000010
+#define NUMAKER_CLK_DMICSEL_VAD0SEL_HIRC 0x00000020
+#define NUMAKER_CLK_EADCSEL_EADC0SEL_APLL1_DIV2 0x00000000
+#define NUMAKER_CLK_EADCSEL_EADC0SEL_APLL0_DIV2 0x00000001
+#define NUMAKER_CLK_EADCSEL_EADC0SEL_PCLK0 0x00000002
+#define NUMAKER_CLK_EPWMSEL_EPWM0SEL_PCLK0 0x00000000
+#define NUMAKER_CLK_EPWMSEL_EPWM0SEL_HCLK0 0x00000001
+#define NUMAKER_CLK_EPWMSEL_EPWM1SEL_PCLK2 0x00000000
+#define NUMAKER_CLK_EPWMSEL_EPWM1SEL_HCLK0 0x00000010
+#define NUMAKER_CLK_FMCSEL_FMC0SEL_HIRC 0x00000000
+#define NUMAKER_CLK_FMCSEL_FMC0SEL_HIRC48M_DIV4 0x00000001
+#define NUMAKER_CLK_I2SSEL_I2S0SEL_HXT 0x00000000
+#define NUMAKER_CLK_I2SSEL_I2S0SEL_APLL1_DIV2 0x00000001
+#define NUMAKER_CLK_I2SSEL_I2S0SEL_APLL0_DIV2 0x00000002
+#define NUMAKER_CLK_I2SSEL_I2S0SEL_PCLK1 0x00000003
+#define NUMAKER_CLK_I2SSEL_I2S0SEL_HIRC 0x00000004
+#define NUMAKER_CLK_I2SSEL_I2S0SEL_HIRC48M 0x00000005
+#define NUMAKER_CLK_I2SSEL_I2S1SEL_HXT 0x00000000
+#define NUMAKER_CLK_I2SSEL_I2S1SEL_APLL1_DIV2 0x00000010
+#define NUMAKER_CLK_I2SSEL_I2S1SEL_APLL0_DIV2 0x00000020
+#define NUMAKER_CLK_I2SSEL_I2S1SEL_PCLK3 0x00000030
+#define NUMAKER_CLK_I2SSEL_I2S1SEL_HIRC 0x00000040
+#define NUMAKER_CLK_I2SSEL_I2S1SEL_HIRC48M 0x00000050
+#define NUMAKER_CLK_I3CSEL_I3C0SEL_HCLK0 0x00000000
+#define NUMAKER_CLK_I3CSEL_I3C0SEL_APLL1 0x00000001
+#define NUMAKER_CLK_KPISEL_KPI0SEL_HIRC48M_DIV4 0x00000000
+#define NUMAKER_CLK_KPISEL_KPI0SEL_HIRC 0x00000001
+#define NUMAKER_CLK_KPISEL_KPI0SEL_LIRC 0x00000002
+#define NUMAKER_CLK_KPISEL_KPI0SEL_HXT 0x00000003
+#define NUMAKER_CLK_LPADCSEL_LPADC0SEL_PCLK4 0x00000000
+#define NUMAKER_CLK_LPADCSEL_LPADC0SEL_LXT 0x00000001
+#define NUMAKER_CLK_LPADCSEL_LPADC0SEL_MIRC 0x00000002
+#define NUMAKER_CLK_LPADCSEL_LPADC0SEL_HIRC 0x00000003
+#define NUMAKER_CLK_LPSPISEL_LPSPI0SEL_PCLK4 0x00000000
+#define NUMAKER_CLK_LPSPISEL_LPSPI0SEL_MIRC 0x00000001
+#define NUMAKER_CLK_LPSPISEL_LPSPI0SEL_HIRC 0x00000002
+#define NUMAKER_CLK_LPTMRSEL_LPTMR0SEL_PCLK4 0x00000000
+#define NUMAKER_CLK_LPTMRSEL_LPTMR0SEL_LXT 0x00000001
+#define NUMAKER_CLK_LPTMRSEL_LPTMR0SEL_LIRC 0x00000002
+#define NUMAKER_CLK_LPTMRSEL_LPTMR0SEL_MIRC 0x00000003
+#define NUMAKER_CLK_LPTMRSEL_LPTMR0SEL_HIRC 0x00000004
+#define NUMAKER_CLK_LPTMRSEL_LPTMR0SEL_EXT 0x00000005
+#define NUMAKER_CLK_LPTMRSEL_LPTMR1SEL_PCLK4 0x00000000
+#define NUMAKER_CLK_LPTMRSEL_LPTMR1SEL_LXT 0x00000010
+#define NUMAKER_CLK_LPTMRSEL_LPTMR1SEL_LIRC 0x00000020
+#define NUMAKER_CLK_LPTMRSEL_LPTMR1SEL_MIRC 0x00000030
+#define NUMAKER_CLK_LPTMRSEL_LPTMR1SEL_HIRC 0x00000040
+#define NUMAKER_CLK_LPTMRSEL_LPTMR1SEL_EXT 0x00000050
+#define NUMAKER_CLK_LPUARTSEL_LPUART0SEL_PCLK4 0x00000000
+#define NUMAKER_CLK_LPUARTSEL_LPUART0SEL_LXT 0x00000001
+#define NUMAKER_CLK_LPUARTSEL_LPUART0SEL_MIRC 0x00000002
+#define NUMAKER_CLK_LPUARTSEL_LPUART0SEL_HIRC 0x00000003
+#define NUMAKER_CLK_PSIOSEL_PSIO0SEL_LXT 0x00000000
+#define NUMAKER_CLK_PSIOSEL_PSIO0SEL_HXT 0x00000001
+#define NUMAKER_CLK_PSIOSEL_PSIO0SEL_LIRC 0x00000002
+#define NUMAKER_CLK_PSIOSEL_PSIO0SEL_HIRC 0x00000003
+#define NUMAKER_CLK_PSIOSEL_PSIO0SEL_HIRC48M_DIV4 0x00000004
+#define NUMAKER_CLK_PSIOSEL_PSIO0SEL_PCLK1 0x00000005
+#define NUMAKER_CLK_PSIOSEL_PSIO0SEL_APLL0_DIV2 0x00000006
+#define NUMAKER_CLK_QSPISEL_QSPI0SEL_HXT 0x00000000
+#define NUMAKER_CLK_QSPISEL_QSPI0SEL_APLL0_DIV2 0x00000001
+#define NUMAKER_CLK_QSPISEL_QSPI0SEL_PCLK0 0x00000002
+#define NUMAKER_CLK_QSPISEL_QSPI0SEL_HIRC 0x00000003
+#define NUMAKER_CLK_QSPISEL_QSPI0SEL_HIRC48M_DIV4 0x00000004
+#define NUMAKER_CLK_QSPISEL_QSPI1SEL_HXT 0x00000000
+#define NUMAKER_CLK_QSPISEL_QSPI1SEL_APLL0_DIV2 0x00000010
+#define NUMAKER_CLK_QSPISEL_QSPI1SEL_PCLK2 0x00000020
+#define NUMAKER_CLK_QSPISEL_QSPI1SEL_HIRC 0x00000030
+#define NUMAKER_CLK_QSPISEL_QSPI1SEL_HIRC48M_DIV4 0x00000040
+#define NUMAKER_CLK_SCSEL_SC0SEL_HXT 0x00000000
+#define NUMAKER_CLK_SCSEL_SC0SEL_APLL0_DIV2 0x00000001
+#define NUMAKER_CLK_SCSEL_SC0SEL_PCLK1 0x00000002
+#define NUMAKER_CLK_SCSEL_SC0SEL_HIRC 0x00000003
+#define NUMAKER_CLK_SCSEL_SC0SEL_HIRC48M_DIV4 0x00000004
+#define NUMAKER_CLK_SCSEL_SC1SEL_HXT 0x00000000
+#define NUMAKER_CLK_SCSEL_SC1SEL_APLL0_DIV2 0x00000010
+#define NUMAKER_CLK_SCSEL_SC1SEL_PCLK3 0x00000020
+#define NUMAKER_CLK_SCSEL_SC1SEL_HIRC 0x00000030
+#define NUMAKER_CLK_SCSEL_SC1SEL_HIRC48M_DIV4 0x00000040
+#define NUMAKER_CLK_SCSEL_SC2SEL_HXT 0x00000000
+#define NUMAKER_CLK_SCSEL_SC2SEL_APLL0_DIV2 0x00000100
+#define NUMAKER_CLK_SCSEL_SC2SEL_PCLK1 0x00000200
+#define NUMAKER_CLK_SCSEL_SC2SEL_HIRC 0x00000300
+#define NUMAKER_CLK_SCSEL_SC2SEL_HIRC48M_DIV4 0x00000400
+#define NUMAKER_CLK_SDHSEL_SDH0SEL_HXT 0x00000000
+#define NUMAKER_CLK_SDHSEL_SDH0SEL_APLL1_DIV2 0x00000001
+#define NUMAKER_CLK_SDHSEL_SDH0SEL_HCLK0 0x00000002
+#define NUMAKER_CLK_SDHSEL_SDH0SEL_HIRC 0x00000003
+#define NUMAKER_CLK_SDHSEL_SDH0SEL_HIRC48M_DIV4 0x00000004
+#define NUMAKER_CLK_SDHSEL_SDH1SEL_HXT 0x00000000
+#define NUMAKER_CLK_SDHSEL_SDH1SEL_APLL1_DIV2 0x00000010
+#define NUMAKER_CLK_SDHSEL_SDH1SEL_HCLK0 0x00000020
+#define NUMAKER_CLK_SDHSEL_SDH1SEL_HIRC 0x00000030
+#define NUMAKER_CLK_SDHSEL_SDH1SEL_HIRC48M_DIV4 0x00000040
+#define NUMAKER_CLK_SPISEL_SPI0SEL_HXT 0x00000000
+#define NUMAKER_CLK_SPISEL_SPI0SEL_APLL1_DIV2 0x00000001
+#define NUMAKER_CLK_SPISEL_SPI0SEL_APLL0_DIV2 0x00000002
+#define NUMAKER_CLK_SPISEL_SPI0SEL_PCLK0 0x00000003
+#define NUMAKER_CLK_SPISEL_SPI0SEL_HIRC 0x00000004
+#define NUMAKER_CLK_SPISEL_SPI0SEL_HIRC48M 0x00000005
+#define NUMAKER_CLK_SPISEL_SPI1SEL_HXT 0x00000000
+#define NUMAKER_CLK_SPISEL_SPI1SEL_APLL1_DIV2 0x00000010
+#define NUMAKER_CLK_SPISEL_SPI1SEL_APLL0_DIV2 0x00000020
+#define NUMAKER_CLK_SPISEL_SPI1SEL_PCLK2 0x00000030
+#define NUMAKER_CLK_SPISEL_SPI1SEL_HIRC 0x00000040
+#define NUMAKER_CLK_SPISEL_SPI1SEL_HIRC48M 0x00000050
+#define NUMAKER_CLK_SPISEL_SPI2SEL_HXT 0x00000000
+#define NUMAKER_CLK_SPISEL_SPI2SEL_APLL1_DIV2 0x00000100
+#define NUMAKER_CLK_SPISEL_SPI2SEL_APLL0_DIV2 0x00000200
+#define NUMAKER_CLK_SPISEL_SPI2SEL_PCLK0 0x00000300
+#define NUMAKER_CLK_SPISEL_SPI2SEL_HIRC 0x00000400
+#define NUMAKER_CLK_SPISEL_SPI2SEL_HIRC48M 0x00000500
+#define NUMAKER_CLK_SPISEL_SPI3SEL_HXT 0x00000000
+#define NUMAKER_CLK_SPISEL_SPI3SEL_APLL1_DIV2 0x00001000
+#define NUMAKER_CLK_SPISEL_SPI3SEL_APLL0_DIV2 0x00002000
+#define NUMAKER_CLK_SPISEL_SPI3SEL_PCLK2 0x00003000
+#define NUMAKER_CLK_SPISEL_SPI3SEL_HIRC 0x00004000
+#define NUMAKER_CLK_SPISEL_SPI3SEL_HIRC48M 0x00005000
+#define NUMAKER_CLK_STSEL_ST0SEL_HXT 0x00000000
+#define NUMAKER_CLK_STSEL_ST0SEL_HXT_DIV2 0x00000001
+#define NUMAKER_CLK_STSEL_ST0SEL_ACLK_DIV2 0x00000002
+#define NUMAKER_CLK_STSEL_ST0SEL_HIRC_DIV2 0x00000003
+#define NUMAKER_CLK_STSEL_ACLK 0x00000008
+#define NUMAKER_CLK_TMRSEL_TMR0SEL_HXT 0x00000000
+#define NUMAKER_CLK_TMRSEL_TMR0SEL_LXT 0x00000001
+#define NUMAKER_CLK_TMRSEL_TMR0SEL_PCLK1 0x00000002
+#define NUMAKER_CLK_TMRSEL_TMR0SEL_EXT 0x00000003
+#define NUMAKER_CLK_TMRSEL_TMR0SEL_LIRC 0x00000004
+#define NUMAKER_CLK_TMRSEL_TMR0SEL_HIRC 0x00000005
+#define NUMAKER_CLK_TMRSEL_TMR0SEL_HIRC48M_DIV4 0x00000006
+#define NUMAKER_CLK_TMRSEL_TMR1SEL_HXT 0x00000000
+#define NUMAKER_CLK_TMRSEL_TMR1SEL_LXT 0x00000010
+#define NUMAKER_CLK_TMRSEL_TMR1SEL_PCLK1 0x00000020
+#define NUMAKER_CLK_TMRSEL_TMR1SEL_EXT 0x00000030
+#define NUMAKER_CLK_TMRSEL_TMR1SEL_LIRC 0x00000040
+#define NUMAKER_CLK_TMRSEL_TMR1SEL_HIRC 0x00000050
+#define NUMAKER_CLK_TMRSEL_TMR1SEL_HIRC48M_DIV4 0x00000060
+#define NUMAKER_CLK_TMRSEL_TMR2SEL_HXT 0x00000000
+#define NUMAKER_CLK_TMRSEL_TMR2SEL_LXT 0x00000100
+#define NUMAKER_CLK_TMRSEL_TMR2SEL_PCLK3 0x00000200
+#define NUMAKER_CLK_TMRSEL_TMR2SEL_EXT 0x00000300
+#define NUMAKER_CLK_TMRSEL_TMR2SEL_LIRC 0x00000400
+#define NUMAKER_CLK_TMRSEL_TMR2SEL_HIRC 0x00000500
+#define NUMAKER_CLK_TMRSEL_TMR2SEL_HIRC48M_DIV4 0x00000600
+#define NUMAKER_CLK_TMRSEL_TMR3SEL_HXT 0x00000000
+#define NUMAKER_CLK_TMRSEL_TMR3SEL_LXT 0x00001000
+#define NUMAKER_CLK_TMRSEL_TMR3SEL_PCLK3 0x00002000
+#define NUMAKER_CLK_TMRSEL_TMR3SEL_EXT 0x00003000
+#define NUMAKER_CLK_TMRSEL_TMR3SEL_LIRC 0x00004000
+#define NUMAKER_CLK_TMRSEL_TMR3SEL_HIRC 0x00005000
+#define NUMAKER_CLK_TMRSEL_TMR3SEL_HIRC48M_DIV4 0x00006000
+#define NUMAKER_CLK_TTMRSEL_TTMR0SEL_PCLK4 0x00000000
+#define NUMAKER_CLK_TTMRSEL_TTMR0SEL_LXT 0x00000001
+#define NUMAKER_CLK_TTMRSEL_TTMR0SEL_LIRC 0x00000002
+#define NUMAKER_CLK_TTMRSEL_TTMR0SEL_MIRC 0x00000003
+#define NUMAKER_CLK_TTMRSEL_TTMR0SEL_HIRC 0x00000004
+#define NUMAKER_CLK_TTMRSEL_TTMR1SEL_PCLK4 0x00000000
+#define NUMAKER_CLK_TTMRSEL_TTMR1SEL_LXT 0x00000010
+#define NUMAKER_CLK_TTMRSEL_TTMR1SEL_LIRC 0x00000020
+#define NUMAKER_CLK_TTMRSEL_TTMR1SEL_MIRC 0x00000030
+#define NUMAKER_CLK_TTMRSEL_TTMR1SEL_HIRC 0x00000040
+#define NUMAKER_CLK_UARTSEL0_UART0SEL_HXT 0x00000000
+#define NUMAKER_CLK_UARTSEL0_UART0SEL_HIRC 0x00000001
+#define NUMAKER_CLK_UARTSEL0_UART0SEL_LXT 0x00000002
+#define NUMAKER_CLK_UARTSEL0_UART0SEL_APLL0_DIV2 0x00000003
+#define NUMAKER_CLK_UARTSEL0_UART0SEL_HIRC48M 0x00000004
+#define NUMAKER_CLK_UARTSEL0_UART1SEL_HXT 0x00000000
+#define NUMAKER_CLK_UARTSEL0_UART1SEL_HIRC 0x00000010
+#define NUMAKER_CLK_UARTSEL0_UART1SEL_LXT 0x00000020
+#define NUMAKER_CLK_UARTSEL0_UART1SEL_APLL0_DIV2 0x00000030
+#define NUMAKER_CLK_UARTSEL0_UART1SEL_HIRC48M 0x00000040
+#define NUMAKER_CLK_UARTSEL0_UART2SEL_HXT 0x00000000
+#define NUMAKER_CLK_UARTSEL0_UART2SEL_HIRC 0x00000100
+#define NUMAKER_CLK_UARTSEL0_UART2SEL_LXT 0x00000200
+#define NUMAKER_CLK_UARTSEL0_UART2SEL_APLL0_DIV2 0x00000300
+#define NUMAKER_CLK_UARTSEL0_UART2SEL_HIRC48M 0x00000400
+#define NUMAKER_CLK_UARTSEL0_UART3SEL_HXT 0x00000000
+#define NUMAKER_CLK_UARTSEL0_UART3SEL_HIRC 0x00001000
+#define NUMAKER_CLK_UARTSEL0_UART3SEL_LXT 0x00002000
+#define NUMAKER_CLK_UARTSEL0_UART3SEL_APLL0_DIV2 0x00003000
+#define NUMAKER_CLK_UARTSEL0_UART3SEL_HIRC48M 0x00004000
+#define NUMAKER_CLK_UARTSEL0_UART4SEL_HXT 0x00000000
+#define NUMAKER_CLK_UARTSEL0_UART4SEL_HIRC 0x00010000
+#define NUMAKER_CLK_UARTSEL0_UART4SEL_LXT 0x00020000
+#define NUMAKER_CLK_UARTSEL0_UART4SEL_APLL0_DIV2 0x00030000
+#define NUMAKER_CLK_UARTSEL0_UART4SEL_HIRC48M 0x00040000
+#define NUMAKER_CLK_UARTSEL0_UART5SEL_HXT 0x00000000
+#define NUMAKER_CLK_UARTSEL0_UART5SEL_HIRC 0x00100000
+#define NUMAKER_CLK_UARTSEL0_UART5SEL_LXT 0x00200000
+#define NUMAKER_CLK_UARTSEL0_UART5SEL_APLL0_DIV2 0x00300000
+#define NUMAKER_CLK_UARTSEL0_UART5SEL_HIRC48M 0x00400000
+#define NUMAKER_CLK_UARTSEL0_UART6SEL_HXT 0x00000000
+#define NUMAKER_CLK_UARTSEL0_UART6SEL_HIRC 0x01000000
+#define NUMAKER_CLK_UARTSEL0_UART6SEL_LXT 0x02000000
+#define NUMAKER_CLK_UARTSEL0_UART6SEL_APLL0_DIV2 0x03000000
+#define NUMAKER_CLK_UARTSEL0_UART6SEL_HIRC48M 0x04000000
+#define NUMAKER_CLK_UARTSEL0_UART7SEL_HXT 0x00000000
+#define NUMAKER_CLK_UARTSEL0_UART7SEL_HIRC 0x10000000
+#define NUMAKER_CLK_UARTSEL0_UART7SEL_LXT 0x20000000
+#define NUMAKER_CLK_UARTSEL0_UART7SEL_APLL0_DIV2 0x30000000
+#define NUMAKER_CLK_UARTSEL0_UART7SEL_HIRC48M 0x40000000
+#define NUMAKER_CLK_UARTSEL1_UART8SEL_HXT 0x00000000
+#define NUMAKER_CLK_UARTSEL1_UART8SEL_HIRC 0x00000001
+#define NUMAKER_CLK_UARTSEL1_UART8SEL_LXT 0x00000002
+#define NUMAKER_CLK_UARTSEL1_UART8SEL_APLL0_DIV2 0x00000003
+#define NUMAKER_CLK_UARTSEL1_UART8SEL_HIRC48M 0x00000004
+#define NUMAKER_CLK_UARTSEL1_UART9SEL_HXT 0x00000000
+#define NUMAKER_CLK_UARTSEL1_UART9SEL_HIRC 0x00000010
+#define NUMAKER_CLK_UARTSEL1_UART9SEL_LXT 0x00000020
+#define NUMAKER_CLK_UARTSEL1_UART9SEL_APLL0_DIV2 0x00000030
+#define NUMAKER_CLK_UARTSEL1_UART9SEL_HIRC48M 0x00000040
+#define NUMAKER_CLK_USBSEL_USBSEL_HIRC48M 0x00000000
+#define NUMAKER_CLK_USBSEL_USBSEL_APLL1_DIV2 0x00000001
+#define NUMAKER_CLK_WDTSEL_WDT0SEL_LXT 0x00000000
+#define NUMAKER_CLK_WDTSEL_WDT0SEL_LIRC 0x00000001
+#define NUMAKER_CLK_WDTSEL_WDT1SEL_LXT 0x00000000
+#define NUMAKER_CLK_WDTSEL_WDT1SEL_LIRC 0x00000010
+#define NUMAKER_CLK_WWDTSEL_WWDT0SEL_LIRC 0x00000000
+#define NUMAKER_CLK_WWDTSEL_WWDT0SEL_LXT 0x00000001
+#define NUMAKER_CLK_WWDTSEL_WWDT1SEL_LIRC 0x00000000
+#define NUMAKER_CLK_WWDTSEL_WWDT1SEL_LXT 0x00000010
+#define NUMAKER_CLK_SCLKDIV_SCLKDIV(x) (((x) - 1UL) << (0))
+#define NUMAKER_CLK_HCLKDIV_HCLK2DIV(x) (((x) - 1UL) << (8))
+#define NUMAKER_CLK_PCLKDIV_PCLK0DIV(x) (((x) - 1UL) << (0))
+#define NUMAKER_CLK_PCLKDIV_PCLK1DIV(x) (((x) - 1UL) << (4))
+#define NUMAKER_CLK_PCLKDIV_PCLK2DIV(x) (((x) - 1UL) << (8))
+#define NUMAKER_CLK_PCLKDIV_PCLK3DIV(x) (((x) - 1UL) << (12))
+#define NUMAKER_CLK_PCLKDIV_PCLK4DIV(x) (((x) - 1UL) << (16))
+#define NUMAKER_CLK_STDIV_ST0DIV(x) (((x) - 1UL) << (0))
+#define NUMAKER_CLK_CANFDDIV_CANFD0DIV(x) (((x) - 1UL) << (0))
+#define NUMAKER_CLK_CANFDDIV_CANFD1DIV(x) (((x) - 1UL) << (8))
+#define NUMAKER_CLK_DMICDIV_DMIC0DIV(x) (((x) - 1UL) << (0))
+#define NUMAKER_CLK_EADCDIV_EADC0DIV(x) (((x) - 1UL) << (0))
+#define NUMAKER_CLK_I2SDIV_I2S0DIV(x) (((x) - 1UL) << (0))
+#define NUMAKER_CLK_I2SDIV_I2S1DIV(x) (((x) - 1UL) << (8))
+#define NUMAKER_CLK_KPIDIV_KPI0DIV(x) (((x) - 1UL) << (0))
+#define NUMAKER_CLK_LPADCDIV_LPADC0DIV(x) (((x) - 1UL) << (0))
+#define NUMAKER_CLK_LPUARTDIV_LPUART0DIV(x) (((x) - 1UL) << (0))
+#define NUMAKER_CLK_PSIODIV_PSIO0DIV(x) (((x) - 1UL) << (0))
+#define NUMAKER_CLK_SCDIV_SC0DIV(x) (((x) - 1UL) << (0))
+#define NUMAKER_CLK_SCDIV_SC1DIV(x) (((x) - 1UL) << (8))
+#define NUMAKER_CLK_SCDIV_SC2DIV(x) (((x) - 1UL) << (16))
+#define NUMAKER_CLK_SDHDIV_SDH0DIV(x) (((x) - 1UL) << (0))
+#define NUMAKER_CLK_SDHDIV_SDH1DIV(x) (((x) - 1UL) << (8))
+#define NUMAKER_CLK_UARTDIV0_UART0DIV(x) (((x) - 1UL) << (0))
+#define NUMAKER_CLK_UARTDIV0_UART1DIV(x) (((x) - 1UL) << (4))
+#define NUMAKER_CLK_UARTDIV0_UART2DIV(x) (((x) - 1UL) << (8))
+#define NUMAKER_CLK_UARTDIV0_UART3DIV(x) (((x) - 1UL) << (12))
+#define NUMAKER_CLK_UARTDIV0_UART4DIV(x) (((x) - 1UL) << (16))
+#define NUMAKER_CLK_UARTDIV0_UART5DIV(x) (((x) - 1UL) << (20))
+#define NUMAKER_CLK_UARTDIV0_UART6DIV(x) (((x) - 1UL) << (24))
+#define NUMAKER_CLK_UARTDIV0_UART7DIV(x) (((x) - 1UL) << (28))
+#define NUMAKER_CLK_UARTDIV1_UART8DIV(x) (((x) - 1UL) << (0))
+#define NUMAKER_CLK_UARTDIV1_UART9DIV(x) (((x) - 1UL) << (4))
+#define NUMAKER_CLK_USBDIV_USBDIV(x) (((x) - 1UL) << (0))
+#define NUMAKER_CLK_VSENSEDIV_VSENSEDIV(x) (((x) - 1UL) << (0))
+#define NUMAKER_CLK_APLL0_SELECT 0x00000000
+#define NUMAKER_CLK_APLL1_SELECT 0x00000001
+#define NUMAKER_CLK_APLLCTL_APLLSRC_HXT 0x00000000
+#define NUMAKER_CLK_APLLCTL_APLLSRC_HXT_DIV2 0x00000001
+#define NUMAKER_CLK_APLLCTL_APLLSRC_HIRC 0x00000002
+#define NUMAKER_CLK_APLLCTL_APLLSRC_HIRC48_DIV4 0x00000003
+#define NUMAKER_ACMP01_MODULE 0
+#define NUMAKER_ACMP23_MODULE 1
+#define NUMAKER_AWF0_MODULE 2
+#define NUMAKER_BPWM0_MODULE 3
+#define NUMAKER_BPWM1_MODULE 4
+#define NUMAKER_CANFD0_MODULE 5
+#define NUMAKER_CANFD1_MODULE 6
+#define NUMAKER_CCAP0_MODULE 7
+#define NUMAKER_CRC0_MODULE 8
+#define NUMAKER_CRYPTO0_MODULE 9
+#define NUMAKER_DAC01_MODULE 10
+#define NUMAKER_DMIC0_MODULE 11
+#define NUMAKER_VAD0SEL_MODULE 12
+#define NUMAKER_EADC0_MODULE 13
+#define NUMAKER_EBI0_MODULE 14
+#define NUMAKER_ECAP0_MODULE 15
+#define NUMAKER_ECAP1_MODULE 16
+#define NUMAKER_ECAP2_MODULE 17
+#define NUMAKER_ECAP3_MODULE 18
+#define NUMAKER_EMAC0_MODULE 19
+#define NUMAKER_EPWM0_MODULE 20
+#define NUMAKER_EPWM1_MODULE 21
+#define NUMAKER_EQEI0_MODULE 22
+#define NUMAKER_EQEI1_MODULE 23
+#define NUMAKER_EQEI2_MODULE 24
+#define NUMAKER_EQEI3_MODULE 25
+#define NUMAKER_FMC0_MODULE 26
+#define NUMAKER_ISP0_MODULE 27
+#define NUMAKER_GDMA0_MODULE 28
+#define NUMAKER_GPIOA_MODULE 29
+#define NUMAKER_GPIOB_MODULE 30
+#define NUMAKER_GPIOC_MODULE 31
+#define NUMAKER_GPIOD_MODULE 32
+#define NUMAKER_GPIOE_MODULE 33
+#define NUMAKER_GPIOF_MODULE 34
+#define NUMAKER_GPIOG_MODULE 35
+#define NUMAKER_GPIOH_MODULE 36
+#define NUMAKER_GPIOI_MODULE 37
+#define NUMAKER_GPIOJ_MODULE 38
+#define NUMAKER_HSOTG0_MODULE 39
+#define NUMAKER_HSUSBD0_MODULE 40
+#define NUMAKER_HSUSBH0_MODULE 41
+#define NUMAKER_I2C0_MODULE 42
+#define NUMAKER_I2C1_MODULE 43
+#define NUMAKER_I2C2_MODULE 44
+#define NUMAKER_I2C3_MODULE 45
+#define NUMAKER_I2S0_MODULE 46
+#define NUMAKER_I2S1_MODULE 47
+#define NUMAKER_I3C0_MODULE 48
+#define NUMAKER_KDF0_MODULE 49
+#define NUMAKER_KPI0_MODULE 50
+#define NUMAKER_KS0_MODULE 51
+#define NUMAKER_LPADC0_MODULE 52
+#define NUMAKER_LPPDMA0_MODULE 53
+#define NUMAKER_LPGPIO0_MODULE 54
+#define NUMAKER_LPI2C0_MODULE 55
+#define NUMAKER_LPSPI0_MODULE 56
+#define NUMAKER_LPSRAM0_MODULE 57
+#define NUMAKER_LPTMR0_MODULE 58
+#define NUMAKER_LPTMR1_MODULE 59
+#define NUMAKER_LPUART0_MODULE 60
+#define NUMAKER_NPU0_MODULE 61
+#define NUMAKER_OTFC0_MODULE 62
+#define NUMAKER_OTG0_MODULE 63
+#define NUMAKER_PDMA0_MODULE 64
+#define NUMAKER_PDMA1_MODULE 65
+#define NUMAKER_PSIO0_MODULE 66
+#define NUMAKER_QSPI0_MODULE 67
+#define NUMAKER_QSPI1_MODULE 68
+#define NUMAKER_RTC0_MODULE 69
+#define NUMAKER_SC0_MODULE 70
+#define NUMAKER_SC1_MODULE 71
+#define NUMAKER_SC2_MODULE 72
+#define NUMAKER_SCU0_MODULE 73
+#define NUMAKER_SDH0_MODULE 74
+#define NUMAKER_SDH1_MODULE 75
+#define NUMAKER_SPI0_MODULE 76
+#define NUMAKER_SPI1_MODULE 77
+#define NUMAKER_SPI2_MODULE 78
+#define NUMAKER_SPI3_MODULE 79
+#define NUMAKER_SPIM0_MODULE 80
+#define NUMAKER_SRAM0_MODULE 81
+#define NUMAKER_SRAM1_MODULE 82
+#define NUMAKER_SRAM2_MODULE 83
+#define NUMAKER_SRAM3_MODULE 84
+#define NUMAKER_ST0_MODULE 85
+#define NUMAKER_TMR0_MODULE 86
+#define NUMAKER_TMR1_MODULE 87
+#define NUMAKER_TMR2_MODULE 88
+#define NUMAKER_TMR3_MODULE 89
+#define NUMAKER_TRNG0_MODULE 90
+#define NUMAKER_TTMR0_MODULE 91
+#define NUMAKER_TTMR1_MODULE 92
+#define NUMAKER_UART0_MODULE 93
+#define NUMAKER_UART1_MODULE 94
+#define NUMAKER_UART2_MODULE 95
+#define NUMAKER_UART3_MODULE 96
+#define NUMAKER_UART4_MODULE 97
+#define NUMAKER_UART5_MODULE 98
+#define NUMAKER_UART6_MODULE 99
+#define NUMAKER_UART7_MODULE 100
+#define NUMAKER_UART8_MODULE 101
+#define NUMAKER_UART9_MODULE 102
+#define NUMAKER_USBD0_MODULE 103
+#define NUMAKER_USBH0_MODULE 104
+#define NUMAKER_USCI0_MODULE 105
+#define NUMAKER_UTCPD0_MODULE 106
+#define NUMAKER_WDT0_MODULE 107
+#define NUMAKER_WDT1_MODULE 108
+#define NUMAKER_WWDT0_MODULE 109
+#define NUMAKER_WWDT1_MODULE 110
+#define NUMAKER_PMC_NPD0 0x00000000
+#define NUMAKER_PMC_NPD1 0x00000001
+#define NUMAKER_PMC_NPD2 0x00000002
+#define NUMAKER_PMC_NPD3 0x00000003
+#define NUMAKER_PMC_NPD4 0x00000004
+#define NUMAKER_PMC_SPD0 0x00000005
+#define NUMAKER_PMC_SPD1 0x00000006
+#define NUMAKER_PMC_DPD 0x00000007
+
+#endif
diff --git a/include/zephyr/dt-bindings/clock/r7fa4m1xxxxxx-clock.h b/include/zephyr/dt-bindings/clock/r7fa4m1xxxxxx-clock.h
deleted file mode 100644
index 355c4982a3d..00000000000
--- a/include/zephyr/dt-bindings/clock/r7fa4m1xxxxxx-clock.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_DT_BINDINGS_CLOCK_R7FA4M1XXXXXX_CLOCK_H_
-#define ZEPHYR_DT_BINDINGS_CLOCK_R7FA4M1XXXXXX_CLOCK_H_
-
-#include <zephyr/dt-bindings/clock/renesas-ra-cgc.h>
-
-#endif /* ZEPHYR_DT_BINDINGS_CLOCK_R7FA4M1XXXXXX_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/renesas_rza2m_clock.h b/include/zephyr/dt-bindings/clock/renesas_rza2m_clock.h
new file mode 100644
index 00000000000..76fa3994fa6
--- /dev/null
+++ b/include/zephyr/dt-bindings/clock/renesas_rza2m_clock.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZA2M_CLOCK_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZA2M_CLOCK_H_
+
+#define RZA2M_MODULE_CORESIGHT 1UL
+#define RZA2M_MODULE_OSTM0     2UL
+#define RZA2M_MODULE_OSTM1     3UL
+#define RZA2M_MODULE_OSTM2     4UL
+#define RZA2M_MODULE_MTU3      5UL
+#define RZA2M_MODULE_CANFD     6UL
+#define RZA2M_MODULE_ADC       7UL
+#define RZA2M_MODULE_GPT       8UL
+#define RZA2M_MODULE_SCIFA0    9UL
+#define RZA2M_MODULE_SCIFA1    10UL
+#define RZA2M_MODULE_SCIFA2    11UL
+#define RZA2M_MODULE_SCIFA3    12UL
+#define RZA2M_MODULE_SCIFA4    13UL
+#define RZA2M_MODULE_SCI0      14UL
+#define RZA2M_MODULE_SCI1      15UL
+#define RZA2M_MODULE_IrDA      16UL
+#define RZA2M_MODULE_CEU       17UL
+#define RZA2M_MODULE_RTC0      18UL
+#define RZA2M_MODULE_RTC1      19UL
+#define RZA2M_MODULE_JCU       20UL
+#define RZA2M_MODULE_VIN       21UL
+#define RZA2M_MODULE_ETHER     22UL
+#define RZA2M_MODULE_USB0      23UL
+#define RZA2M_MODULE_USB1      24UL
+#define RZA2M_MODULE_IMR2      25UL
+#define RZA2M_MODULE_DRW       26UL
+#define RZA2M_MODULE_MIPI      27UL
+#define RZA2M_MODULE_SSIF0     28UL
+#define RZA2M_MODULE_SSIF1     29UL
+#define RZA2M_MODULE_SSIF2     30UL
+#define RZA2M_MODULE_SSIF3     31UL
+#define RZA2M_MODULE_I2C0      32UL
+#define RZA2M_MODULE_I2C1      33UL
+#define RZA2M_MODULE_I2C2      34UL
+#define RZA2M_MODULE_I2C3      35UL
+#define RZA2M_MODULE_SPIBSC    36UL
+#define RZA2M_MODULE_VDC6      37UL
+#define RZA2M_MODULE_RSPI0     38UL
+#define RZA2M_MODULE_RSPI1     39UL
+#define RZA2M_MODULE_RSPI2     40UL
+#define RZA2M_MODULE_HYPERBUS  41UL
+#define RZA2M_MODULE_OCTAMEM   42UL
+#define RZA2M_MODULE_RSPDIF    43UL
+#define RZA2M_MODULE_DRP       44UL
+#define RZA2M_MODULE_TSIP      45UL
+#define RZA2M_MODULE_NAND      46UL
+#define RZA2M_MODULE_SDMMC0    47UL
+#define RZA2M_MODULE_SDMMC1    48UL
+
+/** RZ/A2M clock configuration values */
+#define RZA2M_MODULE_SHIFT    8UL
+#define RZA2M_CLOCK_SRC_SHIFT 0UL
+
+#define RZA2M_CLK_EXTAL 0UL
+#define RZA2M_CLK_I     1UL
+#define RZA2M_CLK_G     2UL
+#define RZA2M_CLK_B     3UL
+#define RZA2M_CLK_P1    4UL
+#define RZA2M_CLK_P1C   4UL
+#define RZA2M_CLK_P0    5UL
+
+#define RZA2M_CLOCK(module, clk)                                                                   \
+	(((module) << RZA2M_MODULE_SHIFT) | ((clk) << RZA2M_CLOCK_SRC_SHIFT))
+
+/*
+ * Example: RZA2M_CLOCK(MODULE_SCIFA4, RZA2M_CLK_P1C) // SCIFA4
+ */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZA2M_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/renesas_rzg_clock.h b/include/zephyr/dt-bindings/clock/renesas_rzg_clock.h
new file mode 100644
index 00000000000..af94425e533
--- /dev/null
+++ b/include/zephyr/dt-bindings/clock/renesas_rzg_clock.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZG_CLOCK_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZG_CLOCK_H_
+
+/** RZ clock configuration values */
+#define RZ_IP_MASK         0xFF000000UL
+#define RZ_IP_SHIFT        24UL
+#define RZ_IP_CH_MASK      0xFF0000UL
+#define RZ_IP_CH_SHIFT     16UL
+#define RZ_CLOCK_MASK      0xFF00UL
+#define RZ_CLOCK_SHIFT     8UL
+#define RZ_CLOCK_DIV_MASK  0xFFUL
+#define RZ_CLOCK_DIV_SHIFT 0UL
+
+#define RZ_IP_GTM   0UL /* General Timer */
+#define RZ_IP_GPT   1UL /* General PWM Timer */
+#define RZ_IP_SCIF  2UL /* Serial Communications Interface with FIFO */
+#define RZ_IP_RIIC  3UL /* I2C Bus Interface */
+#define RZ_IP_RSPI  4UL /* Renesas Serial Peripheral Interface */
+#define RZ_IP_MHU   5UL /* Message Handling Unit */
+#define RZ_IP_DMAC  6UL /* Direct Memory Access Controller */
+#define RZ_IP_CANFD 7UL /* CANFD Interface (RS-CANFD) */
+#define RZ_IP_ADC   8UL /* A/D Converter */
+
+#define RZ_CLOCK_ICLK    0UL  /* Cortex-A55 Clock */
+#define RZ_CLOCK_I2CLK   1UL  /* Cortex-M33 Clock */
+#define RZ_CLOCK_I3CLK   2UL  /* Cortex-M33 FPU Clock */
+#define RZ_CLOCK_S0CLK   3UL  /* DDR-PHY Clock */
+#define RZ_CLOCK_OC0CLK  4UL  /* OCTA0 Clock */
+#define RZ_CLOCK_OC1CLK  5UL  /* OCTA1 Clock */
+#define RZ_CLOCK_SPI0CLK 6UL  /* SPI0 Clock */
+#define RZ_CLOCK_SPI1CLK 7UL  /* SPI1 Clock */
+#define RZ_CLOCK_SD0CLK  8UL  /* SDH0 Clock */
+#define RZ_CLOCK_SD1CLK  9UL  /* SDH1 Clock */
+#define RZ_CLOCK_SD2CLK  10UL /* SDH2 Clock */
+#define RZ_CLOCK_M0CLK   11UL /* VCP LCDC Clock */
+#define RZ_CLOCK_HPCLK   12UL /* Ethernet Clock */
+#define RZ_CLOCK_TSUCLK  13UL /* TSU Clock */
+#define RZ_CLOCK_ZTCLK   14UL /* JAUTH Clock */
+#define RZ_CLOCK_P0CLK   15UL /* APB-BUS Clock */
+#define RZ_CLOCK_P1CLK   16UL /* AXI-BUS Clock */
+#define RZ_CLOCK_P2CLK   17UL /* P2CLK */
+#define RZ_CLOCK_P3CLK   18UL /* P3CLK */
+#define RZ_CLOCK_P4CLK   19UL /* P4CLK */
+#define RZ_CLOCK_P5CLK   20UL /* P5CLK */
+#define RZ_CLOCK_ATCLK   21UL /* ATCLK */
+#define RZ_CLOCK_OSCCLK  22UL /* OSC Clock */
+#define RZ_CLOCK_OSCCLK2 23UL /* OSC2 Clock */
+
+#define RZ_CLOCK(IP, ch, clk, div)                                                                 \
+	((RZ_IP_##IP << RZ_IP_SHIFT) | ((ch) << RZ_IP_CH_SHIFT) | ((clk) << RZ_CLOCK_SHIFT) |      \
+	 ((div) << RZ_CLOCK_DIV_SHIFT))
+
+/**
+ * Pack clock configurations in a 32-bit value
+ * as expected for the Device Tree `clocks` property on Renesas RZ/G.
+ *
+ * @param ch Peripheral channel/unit
+ */
+
+/* SCIF */
+#define RZ_CLOCK_SCIF(ch) RZ_CLOCK(SCIF, ch, RZ_CLOCK_P0CLK, 1)
+
+/* GPT */
+#define RZ_CLOCK_GPT(ch) RZ_CLOCK(GPT, ch, RZ_CLOCK_P0CLK, 1)
+
+/* MHU */
+#define RZ_CLOCK_MHU(ch) RZ_CLOCK(MHU, ch, RZ_CLOCK_P1CLK, 2)
+
+/* ADC */
+#define RZ_CLOCK_ADC(ch) RZ_CLOCK(ADC, ch, RZ_CLOCK_TSUCLK, 1)
+
+/* RIIC */
+#define RZ_CLOCK_RIIC(ch) RZ_CLOCK(RIIC, ch, RZ_CLOCK_P0CLK, 1)
+
+/* GTM */
+#define RZ_CLOCK_GTM(ch) RZ_CLOCK(GTM, ch, RZ_CLOCK_P0CLK, 1)
+
+/* CAN */
+#define RZ_CLOCK_CANFD(ch) RZ_CLOCK(CANFD, ch, RZ_CLOCK_P4CLK, 2)
+
+/* RSPI */
+#define RZ_CLOCK_RSPI(ch) RZ_CLOCK(RSPI, ch, RZ_CLOCK_P0CLK, 1)
+
+/* DMAC */
+#define RZ_CLOCK_DMAC(ch) RZ_CLOCK(DMAC, ch, RZ_CLOCK_P3CLK, 1)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RENESAS_RZG_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/silabs/siwx91x-clock.h b/include/zephyr/dt-bindings/clock/silabs/siwx91x-clock.h
new file mode 100644
index 00000000000..b133d2775ab
--- /dev/null
+++ b/include/zephyr/dt-bindings/clock/silabs/siwx91x-clock.h
@@ -0,0 +1,18 @@
+/* Copyright (c) 2024 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_SIWX91X_CLOCK_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_SIWX91X_CLOCK_H_
+
+#define SIWX91X_CLK_ULP_UART      0
+#define SIWX91X_CLK_ULP_I2C       1
+#define SIWX91X_CLK_ULP_DMA       2
+#define SIWX91X_CLK_UART0         3
+#define SIWX91X_CLK_UART1         4
+#define SIWX91X_CLK_I2C0          5
+#define SIWX91X_CLK_I2C1          6
+#define SIWX91X_CLK_DMA0          7
+#define SIWX91X_CLK_WATCHDOG      8
+#define SIWX91X_CLK_PWM           9
+
+#endif
diff --git a/include/zephyr/dt-bindings/clock/silabs/xg29-clock.h b/include/zephyr/dt-bindings/clock/silabs/xg29-clock.h
new file mode 100644
index 00000000000..20a9eb4b783
--- /dev/null
+++ b/include/zephyr/dt-bindings/clock/silabs/xg29-clock.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * This file was generated by the script gen_clock_control.py in the hal_silabs module.
+ * Do not manually edit.
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG29_CLOCK_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG29_CLOCK_H_
+
+#include <zephyr/dt-bindings/dt-util.h>
+#include "common-clock.h"
+
+/*
+ * DT macros for clock tree nodes.
+ * Defined as:
+ *  0..5 - Bit within CLKEN register
+ *  6..8 - CLKEN register number
+ * Must stay in sync with equivalent SL_BUS_*_VALUE constants in the Silicon Labs HAL to be
+ * interpreted correctly by the clock control driver.
+ */
+#define CLOCK_ACMP0         (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 19))
+#define CLOCK_AGC           (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 0))
+#define CLOCK_AMUXCP0       (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 11))
+#define CLOCK_BUFC          (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 11))
+#define CLOCK_BURAM         (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 28))
+#define CLOCK_BURTC         (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 29))
+#define CLOCK_SEMAILBOX     (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 21))
+#define CLOCK_DMEM          (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 22))
+#define CLOCK_DCDC          (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 31))
+#define CLOCK_DPLL0         (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 17))
+#define CLOCK_ETAMPDET      (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 28))
+#define CLOCK_EUSART0       (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 20))
+#define CLOCK_EUSART1       (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 23))
+#define CLOCK_FRC           (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 3))
+#define CLOCK_FSRCO         (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 20))
+#define CLOCK_GPCRC0        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 3))
+#define CLOCK_GPIO          (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 26))
+#define CLOCK_HFRCO0        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 18))
+#define CLOCK_HFXO0         (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 19))
+#define CLOCK_I2C0          (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 14))
+#define CLOCK_I2C1          (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 15))
+#define CLOCK_IADC0         (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 10))
+#define CLOCK_ICACHE0       (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 16))
+#define CLOCK_IFADCDEBUG    (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 12))
+#define CLOCK_LDMA0         (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 0))
+#define CLOCK_LDMAXBAR0     (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 1))
+#define CLOCK_LETIMER0      (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 12))
+#define CLOCK_LFRCO         (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 21))
+#define CLOCK_LFXO          (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 22))
+#define CLOCK_MODEM         (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 1))
+#define CLOCK_MSC           (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 17))
+#define CLOCK_PDM           (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 25))
+#define CLOCK_PRORTC        (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 10))
+#define CLOCK_PROTIMER      (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 4))
+#define CLOCK_PRS           (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 27))
+#define CLOCK_RAC           (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 5))
+#define CLOCK_RADIOAES      (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 2))
+#define CLOCK_RDMAILBOX0    (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 8))
+#define CLOCK_RDMAILBOX1    (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 9))
+#define CLOCK_RDSCRATCHPAD  (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 7))
+#define CLOCK_RFCRC         (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 2))
+#define CLOCK_RFSENSE       (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 14))
+#define CLOCK_RTCC          (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 30))
+#define CLOCK_SMU           (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 15))
+#define CLOCK_SYNTH         (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 6))
+#define CLOCK_SYSCFG        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 16))
+#define CLOCK_TIMER0        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 4))
+#define CLOCK_TIMER1        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 5))
+#define CLOCK_TIMER2        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 6))
+#define CLOCK_TIMER3        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 7))
+#define CLOCK_TIMER4        (FIELD_PREP(CLOCK_REG_MASK, 1) | FIELD_PREP(CLOCK_BIT_MASK, 18))
+#define CLOCK_ULFRCO        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 23))
+#define CLOCK_USART0        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 8))
+#define CLOCK_USART1        (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 9))
+#define CLOCK_WDOG0         (FIELD_PREP(CLOCK_REG_MASK, 0) | FIELD_PREP(CLOCK_BIT_MASK, 13))
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_SILABS_XG29_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32_clock.h b/include/zephyr/dt-bindings/clock/stm32_clock.h
index 37241a26c46..0564c3084b1 100644
--- a/include/zephyr/dt-bindings/clock/stm32_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32_clock.h
@@ -22,6 +22,7 @@
 #define STM32_CLOCK_BUS_APB5    12
 #define STM32_CLOCK_BUS_AXI     13
 #define STM32_CLOCK_BUS_MLAHB   14
+#define STM32_CLOCK_BUS_APB4_2  15
 
 #define STM32_CLOCK_DIV_SHIFT	12
 
diff --git a/include/zephyr/dt-bindings/clock/stm32_common_clocks.h b/include/zephyr/dt-bindings/clock/stm32_common_clocks.h
index 5c1015471dd..5992fee999b 100644
--- a/include/zephyr/dt-bindings/clock/stm32_common_clocks.h
+++ b/include/zephyr/dt-bindings/clock/stm32_common_clocks.h
@@ -20,35 +20,34 @@
 /** Clock divider */
 #define STM32_CLOCK_DIV(div)	(((div) - 1) << STM32_CLOCK_DIV_SHIFT)
 
-/** STM32 MCO configuration values */
-#define STM32_MCO_CFGR_REG_MASK     0xFFFFU
-#define STM32_MCO_CFGR_REG_SHIFT    0U
-#define STM32_MCO_CFGR_SHIFT_MASK   0x3FU
-#define STM32_MCO_CFGR_SHIFT_SHIFT  16U
-#define STM32_MCO_CFGR_MASK_MASK    0x1FU
-#define STM32_MCO_CFGR_MASK_SHIFT   22U
-#define STM32_MCO_CFGR_VAL_MASK     0x1FU
-#define STM32_MCO_CFGR_VAL_SHIFT    27U
+/** Helper macros to pack RCC clock source selection register info in the DT */
+#define STM32_DT_CLKSEL_REG_MASK	0xFFFFU
+#define STM32_DT_CLKSEL_REG_SHIFT	0U
+#define STM32_DT_CLKSEL_SHIFT_MASK	0x3FU
+#define STM32_DT_CLKSEL_SHIFT_SHIFT	16U
+#define STM32_DT_CLKSEL_MASK_MASK	0x1FU
+#define STM32_DT_CLKSEL_MASK_SHIFT	22U
+#define STM32_DT_CLKSEL_VAL_MASK	0x1FU
+#define STM32_DT_CLKSEL_VAL_SHIFT	27U
 
 /**
- * @brief STM32 MCO configuration register bit field
+ * @brief Pack STM32 source clock selection RCC register bit fields for the DT
  *
- * @param reg    Offset to RCC register holding MCO configuration
- * @param shift    Position of field within RCC register (= field LSB's index)
- * @param mask    Mask of register field in RCC register
- * @param val    Clock configuration field value (0~0x1F)
+ * @param val    Clock configuration field value
+ * @param mask   Mask of register field in RCC register
+ * @param shift  Position of field within RCC register (= field LSB's index)
+ * @param reg    Offset to target clock configuration register in RCC
  *
- * @note 'reg' range:    0x0~0xFFFF    [ 00 : 15 ]
- * @note 'shift' range:    0~63        [ 16 : 21 ]
- * @note 'mask' range:    0x00~0x1F    [ 22 : 26 ]
+ * @note 'reg' range:    0x0~0xFFFF   [ 00 : 15 ]
+ * @note 'shift' range:  0~63         [ 16 : 21 ]
+ * @note 'mask' range:   0x00~0x1F    [ 22 : 26 ]
  * @note 'val' range:    0x00~0x1F    [ 27 : 31 ]
- *
  */
-#define STM32_MCO_CFGR(val, mask, shift, reg)                        \
-	((((reg) & STM32_MCO_CFGR_REG_MASK) << STM32_MCO_CFGR_REG_SHIFT) |        \
-	 (((shift) & STM32_MCO_CFGR_SHIFT_MASK) << STM32_MCO_CFGR_SHIFT_SHIFT) |    \
-	 (((mask) & STM32_MCO_CFGR_MASK_MASK) << STM32_MCO_CFGR_MASK_SHIFT) |        \
-	 (((val) & STM32_MCO_CFGR_VAL_MASK) << STM32_MCO_CFGR_VAL_SHIFT))
+#define STM32_DT_CLOCK_SELECT(val, mask, shift, reg)					\
+	((((reg) & STM32_DT_CLKSEL_REG_MASK) << STM32_DT_CLKSEL_REG_SHIFT) |		\
+	 (((shift) & STM32_DT_CLKSEL_SHIFT_MASK) << STM32_DT_CLKSEL_SHIFT_SHIFT) |	\
+	 (((mask) & STM32_DT_CLKSEL_MASK_MASK) << STM32_DT_CLKSEL_MASK_SHIFT) |		\
+	 (((val) & STM32_DT_CLKSEL_VAL_MASK) << STM32_DT_CLKSEL_VAL_SHIFT))
 
 /**
  * Pack RCC clock register offset and bit in two 32-bit values
diff --git a/include/zephyr/dt-bindings/clock/stm32c0_clock.h b/include/zephyr/dt-bindings/clock/stm32c0_clock.h
index 9564f4113f2..00b5078ac16 100644
--- a/include/zephyr/dt-bindings/clock/stm32c0_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32c0_clock.h
@@ -24,39 +24,11 @@
 /* defined in stm32_common_clocks.h */
 /** Fixed clocks  */
 /* Low speed clocks defined in stm32_common_clocks.h */
-#define STM32_SRC_HSI48		(STM32_SRC_LSI + 1)
-#define STM32_SRC_HSE		(STM32_SRC_HSI48 + 1)
+#define STM32_SRC_HSI		(STM32_SRC_LSI + 1)
+#define STM32_SRC_HSE		(STM32_SRC_HSI + 1)
 /** Peripheral bus clock */
 #define STM32_SRC_PCLK		(STM32_SRC_HSE + 1)
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CCIPRx register offset
- * @param shift Position within RCC_CCIPRx.
- * @param mask Mask for the RCC_CCIPRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CCIPR register offset */
 #define CCIPR_REG		0x54
 
@@ -68,18 +40,18 @@
 
 /** @brief Device domain clocks selection helpers */
 /** CCIPR devices */
-#define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
-#define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
-#define I2C2_I2S1_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
-#define ADC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)
+#define USART1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
+#define I2C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
+#define I2C2_I2S1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG)
+#define ADC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG)
 /** CSR1 devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, CSR1_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, CSR1_REG)
 
 /** CFGR1 devices */
-#define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG)
-#define MCO1_PRE(val)           STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG)
-#define MCO2_SEL(val)           STM32_MCO_CFGR(val, 0x7, 16, CFGR1_REG)
-#define MCO2_PRE(val)           STM32_MCO_CFGR(val, 0x7, 20, CFGR1_REG)
+#define MCO1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR1_REG)
+#define MCO1_PRE(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG)
+#define MCO2_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 16, CFGR1_REG)
+#define MCO2_PRE(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 20, CFGR1_REG)
 
 /* MCO prescaler : division factor */
 #define MCO_PRE_DIV_1   0
diff --git a/include/zephyr/dt-bindings/clock/stm32f0_clock.h b/include/zephyr/dt-bindings/clock/stm32f0_clock.h
index 7572c1c422f..56b87128e71 100644
--- a/include/zephyr/dt-bindings/clock/stm32f0_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32f0_clock.h
@@ -30,34 +30,6 @@
 /** PLL clock */
 #define STM32_SRC_PLLCLK	(STM32_SRC_PCLK + 1)
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CFGRx register offset
- * @param shift Position within RCC_CFGRx.
- * @param mask Mask for the RCC_CFGRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CFGRx register offset */
 #define CFGR1_REG               0x04
 #define CFGR3_REG		0x30
@@ -67,17 +39,17 @@
 
 /** @brief Device domain clocks selection helpers */
 /** CFGR3 devices */
-#define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG)
-#define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG)
-#define CEC_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG)
-#define USB_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 7, CFGR3_REG)
-#define USART2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 16, CFGR3_REG)
-#define USART3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 18, CFGR3_REG)
+#define USART1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CFGR3_REG)
+#define I2C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 4, CFGR3_REG)
+#define CEC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 6, CFGR3_REG)
+#define USB_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 7, CFGR3_REG)
+#define USART2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 16, CFGR3_REG)
+#define USART3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 18, CFGR3_REG)
 /** BDCR devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
 
 /** CFGR1 devices */
-#define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG)
-#define MCO1_PRE(val)           STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG)
+#define MCO1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG)
+#define MCO1_PRE(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG)
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F0_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32f10x_clock.h b/include/zephyr/dt-bindings/clock/stm32f10x_clock.h
index 05f2b598a05..7fe99485219 100644
--- a/include/zephyr/dt-bindings/clock/stm32f10x_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32f10x_clock.h
@@ -19,7 +19,7 @@
 
 /** CFGR1 devices */
 #undef MCO1_SEL /* Need to redefine generic F1 MCO_SEL for connectivity line devices. */
-#define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG)
+#define MCO1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG)
 /* No MCO prescaler support on STM32F1 series. */
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F10X_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32f1_clock.h b/include/zephyr/dt-bindings/clock/stm32f1_clock.h
index f6777932c77..83f1a0f748e 100644
--- a/include/zephyr/dt-bindings/clock/stm32f1_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32f1_clock.h
@@ -28,34 +28,6 @@
 #define STM32_SRC_EXT_HSE       (STM32_SRC_HSE + 1)
 #define STM32_SRC_PLLCLK        (STM32_SRC_EXT_HSE + 1)
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CFGRx register offset
- * @param shift Position within RCC_CFGRx.
- * @param mask Mask for the RCC_CFGRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CFGRx register offset */
 #define CFGR1_REG               0x04
 #define CFGR2_REG		0x2C
@@ -65,13 +37,13 @@
 
 /** @brief Device domain clocks selection helpers */
 /** CFGR2 devices */
-#define I2S2_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 17, CFGR2_REG)
-#define I2S3_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 18, CFGR2_REG)
+#define I2S2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 17, CFGR2_REG)
+#define I2S3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 18, CFGR2_REG)
 /** BDCR devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
 
 /** CFGR1 devices */
-#define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0x7, 24, CFGR1_REG)
+#define MCO1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR1_REG)
 /* No MCO prescaler support on STM32F1 series. */
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F1_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32f3_clock.h b/include/zephyr/dt-bindings/clock/stm32f3_clock.h
index c00d1dd59c3..4617d6727c2 100644
--- a/include/zephyr/dt-bindings/clock/stm32f3_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32f3_clock.h
@@ -31,34 +31,6 @@
 /** PLL clock */
 #define STM32_SRC_PLLCLK	(STM32_SRC_PCLK + 1)
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CFGRx register offset
- * @param shift Position within RCC_CFGRx.
- * @param mask Mask for the RCC_CFGRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CFGRx register offset */
 #define CFGR_REG		0x04
 #define CFGR3_REG		0x30
@@ -68,27 +40,27 @@
 
 /** @brief Device domain clocks selection helpers) */
 /** CFGR devices */
-#define I2S_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)
-#define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG)
-#define MCO1_PRE(val)           STM32_MCO_CFGR(val, 0x7, 28, CFGR_REG)
+#define I2S_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 23, CFGR_REG)
+#define MCO1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR_REG)
+#define MCO1_PRE(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR_REG)
 /** CFGR3 devices */
-#define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CFGR3_REG)
-#define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 4, CFGR3_REG)
-#define I2C2_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 5, CFGR3_REG)
-#define I2C3_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 6, CFGR3_REG)
-#define TIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 8, CFGR3_REG)
-#define TIM8_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 9, CFGR3_REG)
-#define TIM15_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 10, CFGR3_REG)
-#define TIM16_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 11, CFGR3_REG)
-#define TIM17_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 13, CFGR3_REG)
-#define TIM20_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 15, CFGR3_REG)
-#define USART2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 16, CFGR3_REG)
-#define USART3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 18, CFGR3_REG)
-#define USART4_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, CFGR3_REG)
-#define USART5_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 22, CFGR3_REG)
-#define TIM2_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 24, CFGR3_REG)
-#define TIM3_4_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 25, CFGR3_REG)
+#define USART1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CFGR3_REG)
+#define I2C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 4, CFGR3_REG)
+#define I2C2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 5, CFGR3_REG)
+#define I2C3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 6, CFGR3_REG)
+#define TIM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 8, CFGR3_REG)
+#define TIM8_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 9, CFGR3_REG)
+#define TIM15_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 10, CFGR3_REG)
+#define TIM16_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 11, CFGR3_REG)
+#define TIM17_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 13, CFGR3_REG)
+#define TIM20_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 15, CFGR3_REG)
+#define USART2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 16, CFGR3_REG)
+#define USART3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 18, CFGR3_REG)
+#define USART4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, CFGR3_REG)
+#define USART5_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 22, CFGR3_REG)
+#define TIM2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 24, CFGR3_REG)
+#define TIM3_4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 25, CFGR3_REG)
 /** BDCR devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F3_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32f410_clock.h b/include/zephyr/dt-bindings/clock/stm32f410_clock.h
index fffd47321f6..eb7a39c3fb7 100644
--- a/include/zephyr/dt-bindings/clock/stm32f410_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32f410_clock.h
@@ -6,25 +6,27 @@
 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_
 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F410_CLOCK_H_
 
+#include "stm32f4_clock.h"
+
 /** @brief RCC_DCKCFGR register offset */
 #define DCKCFGR_REG		0x8C
 #define DCKCFGR2_REG		0x94
 
 /** @brief Device domain clocks selection helpers */
 /** DCKCFGR devices */
-#define CKDFSDM2A_SEL(val)	STM32_DOMAIN_CLOCK(val, 1, 14, DCKCFGR_REG)
-#define CKDFSDM1A_SEL(val)	STM32_DOMAIN_CLOCK(val, 1, 15, DCKCFGR_REG)
-#define SAI1A_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR_REG)
-#define SAI1B_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR_REG)
-#define I2S1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 25, DCKCFGR_REG)
-#define I2S2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 27, DCKCFGR_REG)
-#define CKDFSDM_SEL(val)	STM32_DOMAIN_CLOCK(val, 1, 31, DCKCFGR_REG)
+#define CKDFSDM2A_SEL(val)	STM32_DT_CLOCK_SELECT((val), 1, 14, DCKCFGR_REG)
+#define CKDFSDM1A_SEL(val)	STM32_DT_CLOCK_SELECT((val), 1, 15, DCKCFGR_REG)
+#define SAI1A_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, DCKCFGR_REG)
+#define SAI1B_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 22, DCKCFGR_REG)
+#define I2S1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 25, DCKCFGR_REG)
+#define I2S2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 27, DCKCFGR_REG)
+#define CKDFSDM_SEL(val)	STM32_DT_CLOCK_SELECT((val), 1, 31, DCKCFGR_REG)
 
 /** DCKCFGR2 devices */
-#define I2CFMP1_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR2_REG)
-#define CK48M_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG)
-#define SDIO_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR2_REG)
-#define LPTIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 30, DCKCFGR2_REG)
+#define I2CFMP1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 22, DCKCFGR2_REG)
+#define CK48M_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 27, DCKCFGR2_REG)
+#define SDIO_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 28, DCKCFGR2_REG)
+#define LPTIM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 30, DCKCFGR2_REG)
 
 /* F4 generic I2S_SEL is not compatible with F410 devices */
 #ifdef I2S_SEL
diff --git a/include/zephyr/dt-bindings/clock/stm32f427_clock.h b/include/zephyr/dt-bindings/clock/stm32f427_clock.h
index 97d22836be5..4fb2f72325f 100644
--- a/include/zephyr/dt-bindings/clock/stm32f427_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32f427_clock.h
@@ -6,17 +6,19 @@
 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_
 #define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_
 
+#include "stm32f4_clock.h"
+
 /** @brief RCC_DCKCFGR register offset */
 #define DCKCFGR_REG		0x8C
 
 /** @brief Device domain clocks selection helpers */
 /** DCKCFGR devices */
-#define CKDFSDM2A_SEL(val)	STM32_DOMAIN_CLOCK(val, 1, 14, DCKCFGR_REG)
-#define CKDFSDM1A_SEL(val)	STM32_DOMAIN_CLOCK(val, 1, 15, DCKCFGR_REG)
-#define SAI1A_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR_REG)
-#define SAI1B_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR_REG)
-#define CLK48M_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR_REG)
-#define SDMMC_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR_REG)
-#define DSI_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 29, DCKCFGR_REG)
+#define CKDFSDM2A_SEL(val)	STM32_DT_CLOCK_SELECT((val), 1, 14, DCKCFGR_REG)
+#define CKDFSDM1A_SEL(val)	STM32_DT_CLOCK_SELECT((val), 1, 15, DCKCFGR_REG)
+#define SAI1A_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, DCKCFGR_REG)
+#define SAI1B_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 22, DCKCFGR_REG)
+#define CLK48M_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 27, DCKCFGR_REG)
+#define SDMMC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 28, DCKCFGR_REG)
+#define DSI_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 29, DCKCFGR_REG)
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F427_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32f4_clock.h b/include/zephyr/dt-bindings/clock/stm32f4_clock.h
index 02290fc1051..98e635c4a2b 100644
--- a/include/zephyr/dt-bindings/clock/stm32f4_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32f4_clock.h
@@ -43,34 +43,6 @@
 /* I2S_CKIN not supported yet */
 /* #define STM32_SRC_I2S_CKIN	TBD */
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CFGRx register offset
- * @param shift Position within RCC_CFGRx.
- * @param mask Mask for the RCC_CFGRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)                                                  \
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |                               \
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |                         \
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |                            \
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CFGRx register offset */
 #define CFGR_REG 0x08
 /** @brief RCC_BDCR register offset */
@@ -78,13 +50,13 @@
 
 /** @brief Device domain clocks selection helpers */
 /** CFGR devices */
-#define I2S_SEL(val)  STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)
-#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG)
-#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG)
-#define MCO2_SEL(val) STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG)
-#define MCO2_PRE(val) STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG)
+#define I2S_SEL(val)  STM32_DT_CLOCK_SELECT((val), 1, 23, CFGR_REG)
+#define MCO1_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 21, CFGR_REG)
+#define MCO1_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR_REG)
+#define MCO2_SEL(val) STM32_DT_CLOCK_SELECT((val), 0x3, 30, CFGR_REG)
+#define MCO2_PRE(val) STM32_DT_CLOCK_SELECT((val), 0x7, 27, CFGR_REG)
 /** BDCR devices */
-#define RTC_SEL(val)  STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
+#define RTC_SEL(val)  STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
 
 /* MCO prescaler : division factor */
 #define MCO_PRE_DIV_1 0
diff --git a/include/zephyr/dt-bindings/clock/stm32f7_clock.h b/include/zephyr/dt-bindings/clock/stm32f7_clock.h
index a729aea88f1..4bfcfdf7386 100644
--- a/include/zephyr/dt-bindings/clock/stm32f7_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32f7_clock.h
@@ -40,35 +40,6 @@
 
 #define STM32_SRC_PLLI2S_R      (STM32_SRC_PCLK + 1)
 
-
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CFGRx register offset
- * @param shift Position within RCC_CFGRx.
- * @param mask Mask for the RCC_CFGRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CFGRx register offset */
 #define CFGR_REG		0x08
 
@@ -77,11 +48,11 @@
 
 /** @brief Device domain clocks selection helpers */
 /** CFGR devices */
-#define I2S_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 23, CFGR_REG)
-#define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0x3, 21, CFGR_REG)
-#define MCO1_PRE(val)           STM32_MCO_CFGR(val, 0x7, 24, CFGR_REG)
-#define MCO2_SEL(val)           STM32_MCO_CFGR(val, 0x3, 30, CFGR_REG)
-#define MCO2_PRE(val)           STM32_MCO_CFGR(val, 0x7, 27, CFGR_REG)
+#define I2S_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 23, CFGR_REG)
+#define MCO1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0x3, 21, CFGR_REG)
+#define MCO1_PRE(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 24, CFGR_REG)
+#define MCO2_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0x3, 30, CFGR_REG)
+#define MCO2_PRE(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 27, CFGR_REG)
 
 /* MCO prescaler : division factor */
 #define MCO_PRE_DIV_1 0
@@ -91,7 +62,7 @@
 #define MCO_PRE_DIV_5 7
 
 /** BDCR devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
 
 /** @brief RCC_DKCFGR register offset */
 #define DCKCFGR1_REG		0x8C
@@ -99,23 +70,23 @@
 
 /** @brief Dedicated clocks configuration register selection helpers */
 /** DKCFGR2 devices */
-#define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, DCKCFGR2_REG)
-#define USART2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 2, DCKCFGR2_REG)
-#define USART3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 4, DCKCFGR2_REG)
-#define USART4_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 6, DCKCFGR2_REG)
-#define USART5_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, DCKCFGR2_REG)
-#define USART6_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 10, DCKCFGR2_REG)
-#define USART7_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, DCKCFGR2_REG)
-#define USART8_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 14, DCKCFGR2_REG)
-#define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 16, DCKCFGR2_REG)
-#define I2C2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 18, DCKCFGR2_REG)
-#define I2C3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, DCKCFGR2_REG)
-#define I2C4_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 22, DCKCFGR2_REG)
-#define LPTIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 24, DCKCFGR2_REG)
-#define CEC_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 26, DCKCFGR2_REG)
-#define CK48M_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 27, DCKCFGR2_REG)
-#define SDMMC1_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 28, DCKCFGR2_REG)
-#define SDMMC2_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 29, DCKCFGR2_REG)
-#define DSI_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 30, DCKCFGR2_REG)
+#define USART1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, DCKCFGR2_REG)
+#define USART2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 2, DCKCFGR2_REG)
+#define USART3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 4, DCKCFGR2_REG)
+#define USART4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 6, DCKCFGR2_REG)
+#define USART5_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, DCKCFGR2_REG)
+#define USART6_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 10, DCKCFGR2_REG)
+#define USART7_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 12, DCKCFGR2_REG)
+#define USART8_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 14, DCKCFGR2_REG)
+#define I2C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 16, DCKCFGR2_REG)
+#define I2C2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 18, DCKCFGR2_REG)
+#define I2C3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, DCKCFGR2_REG)
+#define I2C4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 22, DCKCFGR2_REG)
+#define LPTIM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 24, DCKCFGR2_REG)
+#define CEC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 26, DCKCFGR2_REG)
+#define CK48M_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 27, DCKCFGR2_REG)
+#define SDMMC1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 28, DCKCFGR2_REG)
+#define SDMMC2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 29, DCKCFGR2_REG)
+#define DSI_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 30, DCKCFGR2_REG)
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32F7_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32g0_clock.h b/include/zephyr/dt-bindings/clock/stm32g0_clock.h
index b7d7714b1b1..944f3c022ef 100644
--- a/include/zephyr/dt-bindings/clock/stm32g0_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32g0_clock.h
@@ -35,34 +35,6 @@
 #define STM32_SRC_PLL_Q		(STM32_SRC_PLL_P + 1)
 #define STM32_SRC_PLL_R		(STM32_SRC_PLL_Q + 1)
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CCIPRx register offset
- * @param shift Position within RCC_CCIPRx.
- * @param mask Mask for the RCC_CCIPRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CCIPR register offset */
 #define CCIPR_REG		0x54
 #define CCIPR2_REG		0x58
@@ -72,26 +44,26 @@
 
 /** @brief Device domain clocks selection helpers */
 /** CCIPR devices */
-#define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
-#define USART2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)
-#define USART3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG)
-#define CEC_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 6, CCIPR_REG)
-#define LPUART2_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG)
-#define LPUART1_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
-#define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
-#define I2C2_I2S1_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
-#define LPTIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
-#define LPTIM2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)
-#define TIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 22, CCIPR_REG)
-#define TIM15_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 24, CCIPR_REG)
-#define RNG_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG)
-#define ADC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)
+#define USART1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
+#define USART2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
+#define USART3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG)
+#define CEC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 6, CCIPR_REG)
+#define LPUART2_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)
+#define LPUART1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
+#define I2C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
+#define I2C2_I2S1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG)
+#define LPTIM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
+#define LPTIM2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)
+#define TIM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 22, CCIPR_REG)
+#define TIM15_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR_REG)
+#define RNG_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG)
+#define ADC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG)
 /** CCIPR2 devices */
-#define I2S1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR2_REG)
-#define I2S2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR2_REG)
-#define FDCAN_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR2_REG)
-#define USB_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR2_REG)
+#define I2S1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
+#define I2S2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR2_REG)
+#define FDCAN_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR2_REG)
+#define USB_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
 /** BDCR devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G0_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32g4_clock.h b/include/zephyr/dt-bindings/clock/stm32g4_clock.h
index a7d928c801f..f66d0313a33 100644
--- a/include/zephyr/dt-bindings/clock/stm32g4_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32g4_clock.h
@@ -39,34 +39,6 @@
 #define STM32_SRC_PLL_R		(STM32_SRC_PLL_Q + 1)
 /* TODO: PLLSAI clocks */
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CCIPRx register offset
- * @param shift Position within RCC_CCIPRx.
- * @param mask Mask for the RCC_CCIPRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CCIPR register offset */
 #define CCIPR_REG		0x88
 #define CCIPR2_REG		0x9C
@@ -76,26 +48,26 @@
 
 /** @brief Device domain clocks selection helpers */
 /** CCIPR devices */
-#define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
-#define USART2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)
-#define USART3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG)
-#define USART4_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR_REG)
-#define USART5_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG)
-#define LPUART1_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
-#define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
-#define I2C2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
-#define I2C3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)
-#define LPTIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
-#define SAI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)
-#define I2S23_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG)
-#define FDCAN_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR_REG)
-#define CLK48_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG)
-#define ADC12_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG)
-#define ADC34_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)
+#define USART1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
+#define USART2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
+#define USART3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG)
+#define USART4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR_REG)
+#define USART5_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)
+#define LPUART1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
+#define I2C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
+#define I2C2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG)
+#define I2C3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG)
+#define LPTIM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
+#define SAI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)
+#define I2S23_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG)
+#define FDCAN_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR_REG)
+#define CLK48_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG)
+#define ADC12_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG)
+#define ADC34_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG)
 /** CCIPR2 devices */
-#define I2C4_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR2_REG)
-#define QSPI_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR2_REG)
+#define I2C4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
+#define QSPI_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR2_REG)
 /** BDCR devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32G4_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32h5_clock.h b/include/zephyr/dt-bindings/clock/stm32h5_clock.h
index cbac2d66743..f3ed8289ea7 100644
--- a/include/zephyr/dt-bindings/clock/stm32h5_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32h5_clock.h
@@ -51,34 +51,6 @@
 #define STM32_PERIPH_BUS_MIN	STM32_CLOCK_BUS_AHB1
 #define STM32_PERIPH_BUS_MAX	STM32_CLOCK_BUS_APB3
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32H5 clock configuration bit field.
- *
- * - reg   (1/2/3/4/5)     [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CCIPRx register offset
- * @param shift Position within RCC_CCIPRx.
- * @param mask Mask for the RCC_CCIPRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |	\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |	\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CCIPRx register offset (RM0456.pdf) */
 #define CCIPR1_REG		0xD8
 #define CCIPR2_REG		0xDC
@@ -94,67 +66,67 @@
 
 /** @brief Device domain clocks selection helpers */
 /** CCIPR1 devices */
-#define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR1_REG)
-#define USART2_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 3, CCIPR1_REG)
-#define USART3_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 6, CCIPR1_REG)
-#define USART4_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 9, CCIPR1_REG)
-#define USART5_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR1_REG)
-#define USART6_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 15, CCIPR1_REG)
-#define USART7_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 18, CCIPR1_REG)
-#define USART8_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 21, CCIPR1_REG)
-#define USART9_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 24, CCIPR1_REG)
-#define USART10_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 27, CCIPR1_REG)
-#define TIMIC_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 31, CCIPR1_REG)
+#define USART1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR1_REG)
+#define USART2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 3, CCIPR1_REG)
+#define USART3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR1_REG)
+#define USART4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 9, CCIPR1_REG)
+#define USART5_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR1_REG)
+#define USART6_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 15, CCIPR1_REG)
+#define USART7_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 18, CCIPR1_REG)
+#define USART8_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 21, CCIPR1_REG)
+#define USART9_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR1_REG)
+#define USART10_SEL(val)	STM32_DT_CLOCK_SELECT((val), 7, 27, CCIPR1_REG)
+#define TIMIC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 31, CCIPR1_REG)
 
 /** CCIPR2 devices */
-#define USART11_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR2_REG)
-#define USART12_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 4, CCIPR2_REG)
-#define LPTIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 8, CCIPR2_REG)
-#define LPTIM2_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR2_REG)
-#define LPTIM3_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 16, CCIPR2_REG)
-#define LPTIM4_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 20, CCIPR2_REG)
-#define LPTIM5_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 24, CCIPR2_REG)
-#define LPTIM6_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 28, CCIPR2_REG)
+#define USART11_SEL(val)	STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR2_REG)
+#define USART12_SEL(val)	STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR2_REG)
+#define LPTIM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR2_REG)
+#define LPTIM2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR2_REG)
+#define LPTIM3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR2_REG)
+#define LPTIM4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR2_REG)
+#define LPTIM5_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR2_REG)
+#define LPTIM6_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 28, CCIPR2_REG)
 
 /** CCIPR3 devices */
-#define SPI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR3_REG)
-#define SPI2_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 3, CCIPR3_REG)
-#define SPI3_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 6, CCIPR3_REG)
-#define SPI4_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 9, CCIPR3_REG)
-#define SPI5_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR3_REG)
-#define SPI6_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 15, CCIPR2_REG)
-#define LPUART1_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 24, CCIPR3_REG)
+#define SPI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR3_REG)
+#define SPI2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 3, CCIPR3_REG)
+#define SPI3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 6, CCIPR3_REG)
+#define SPI4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 9, CCIPR3_REG)
+#define SPI5_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR3_REG)
+#define SPI6_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 15, CCIPR2_REG)
+#define LPUART1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR3_REG)
 
 /** CCIPR4 devices */
-#define OCTOSPI1_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR4_REG)
-#define SYSTICK_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR4_REG)
-#define USB_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR4_REG)
-#define SDMMC1_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 6, CCIPR4_REG)
-#define SDMMC2_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 7, CCIPR4_REG)
-#define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR4_REG)
-#define I2C2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR4_REG)
-#define I2C3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR4_REG)
-#define I2C4_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR4_REG)
-#define I3C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR4_REG)
+#define OCTOSPI1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR4_REG)
+#define SYSTICK_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR4_REG)
+#define USB_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR4_REG)
+#define SDMMC1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 6, CCIPR4_REG)
+#define SDMMC2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 7, CCIPR4_REG)
+#define I2C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR4_REG)
+#define I2C2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR4_REG)
+#define I2C3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR4_REG)
+#define I2C4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR4_REG)
+#define I3C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR4_REG)
 
 /** CCIPR5 devices */
-#define ADCDAC_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR5_REG)
-#define DAC_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 3, CCIPR5_REG)
-#define RNG_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR5_REG)
-#define CEC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR5_REG)
-#define FDCAN_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR5_REG)
-#define SAI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 16, CCIPR5_REG)
-#define SAI2_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 19, CCIPR5_REG)
-#define CKPER_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR5_REG)
+#define ADCDAC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR5_REG)
+#define DAC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 3, CCIPR5_REG)
+#define RNG_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR5_REG)
+#define CEC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR5_REG)
+#define FDCAN_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR5_REG)
+#define SAI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR5_REG)
+#define SAI2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 19, CCIPR5_REG)
+#define CKPER_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR5_REG)
 
 /** BDCR devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
 
 /** CFGR1 devices */
-#define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0x7, 22, CFGR1_REG)
-#define MCO1_PRE(val)           STM32_MCO_CFGR(val, 0xF, 18, CFGR1_REG)
-#define MCO2_SEL(val)           STM32_MCO_CFGR(val, 0x7, 25, CFGR1_REG)
-#define MCO2_PRE(val)           STM32_MCO_CFGR(val, 0xF, 29, CFGR1_REG)
+#define MCO1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 22, CFGR1_REG)
+#define MCO1_PRE(val)           STM32_DT_CLOCK_SELECT((val), 0xF, 18, CFGR1_REG)
+#define MCO2_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 25, CFGR1_REG)
+#define MCO2_PRE(val)           STM32_DT_CLOCK_SELECT((val), 0xF, 29, CFGR1_REG)
 
 /* MCO prescaler : division factor */
 #define MCO_PRE_DIV_1 1
diff --git a/include/zephyr/dt-bindings/clock/stm32h7_clock.h b/include/zephyr/dt-bindings/clock/stm32h7_clock.h
index 92c954cdc86..aec5ffc33b9 100644
--- a/include/zephyr/dt-bindings/clock/stm32h7_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32h7_clock.h
@@ -58,34 +58,6 @@
 #define STM32_PERIPH_BUS_MIN	STM32_CLOCK_BUS_AHB3
 #define STM32_PERIPH_BUS_MAX	STM32_CLOCK_BUS_APB4
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32H7 clock configuration bit field.
- *
- * - reg   (0/1)           [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..3)          [ 16 : 18 ]
- *
- * @param reg RCC_DxCCIP register offset
- * @param shift Position within RCC_DxCCIP.
- * @param mask Mask for the RCC_DxCCIP field.
- * @param val Clock value (0, 1, 2 or 3).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |	\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |	\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_DxCCIP register offset (RM0399.pdf) */
 #define D1CCIPR_REG		0x4C
 #define D2CCIP1R_REG		0x50
@@ -100,46 +72,46 @@
 
 /** @brief Device domain clocks selection helpers (RM0399.pdf) */
 /** D1CCIPR devices */
-#define FMC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, D1CCIPR_REG)
-#define QSPI_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG)
-#define DSI_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 8, D1CCIPR_REG)
-#define SDMMC_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 16, D1CCIPR_REG)
-#define CKPER_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 28, D1CCIPR_REG)
+#define FMC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, D1CCIPR_REG)
+#define QSPI_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 4, D1CCIPR_REG)
+#define DSI_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 8, D1CCIPR_REG)
+#define SDMMC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 16, D1CCIPR_REG)
+#define CKPER_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 28, D1CCIPR_REG)
 /* Device domain clocks selection helpers (RM0468.pdf) */
-#define OSPI_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG)
+#define OSPI_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 4, D1CCIPR_REG)
 /** D2CCIP1R devices */
-#define SAI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIP1R_REG)
-#define SAI23_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 6, D2CCIP1R_REG)
-#define SPI123_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 12, D2CCIP1R_REG)
-#define SPI45_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 16, D2CCIP1R_REG)
-#define SPDIF_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, D2CCIP1R_REG)
-#define DFSDM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 24, D2CCIP1R_REG)
-#define FDCAN_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 28, D2CCIP1R_REG)
-#define SWP_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 31, D2CCIP1R_REG)
+#define SAI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 0, D2CCIP1R_REG)
+#define SAI23_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 6, D2CCIP1R_REG)
+#define SPI123_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 12, D2CCIP1R_REG)
+#define SPI45_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 16, D2CCIP1R_REG)
+#define SPDIF_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, D2CCIP1R_REG)
+#define DFSDM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 24, D2CCIP1R_REG)
+#define FDCAN_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 28, D2CCIP1R_REG)
+#define SWP_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 31, D2CCIP1R_REG)
 /** D2CCIP2R devices */
-#define USART2345678_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIP2R_REG)
-#define USART16_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 3, D2CCIP2R_REG)
-#define RNG_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, D2CCIP2R_REG)
-#define I2C123_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, D2CCIP2R_REG)
-#define USB_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, D2CCIP2R_REG)
-#define CEC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 22, D2CCIP2R_REG)
-#define LPTIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 28, D2CCIP2R_REG)
+#define USART2345678_SEL(val)	STM32_DT_CLOCK_SELECT((val), 7, 0, D2CCIP2R_REG)
+#define USART16_SEL(val)	STM32_DT_CLOCK_SELECT((val), 7, 3, D2CCIP2R_REG)
+#define RNG_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, D2CCIP2R_REG)
+#define I2C123_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 12, D2CCIP2R_REG)
+#define USB_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, D2CCIP2R_REG)
+#define CEC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 22, D2CCIP2R_REG)
+#define LPTIM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 28, D2CCIP2R_REG)
 /** D3CCIPR devices */
-#define LPUART1_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 0, D3CCIPR_REG)
-#define I2C4_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, D3CCIPR_REG)
-#define LPTIM2_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 10, D3CCIPR_REG)
-#define LPTIM345_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 13, D3CCIPR_REG)
-#define ADC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 16, D3CCIPR_REG)
-#define SAI4A_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 21, D3CCIPR_REG)
-#define SAI4B_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 24, D3CCIPR_REG)
-#define SPI6_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 28, D3CCIPR_REG)
+#define LPUART1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 7, 0, D3CCIPR_REG)
+#define I2C4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, D3CCIPR_REG)
+#define LPTIM2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 10, D3CCIPR_REG)
+#define LPTIM345_SEL(val)	STM32_DT_CLOCK_SELECT((val), 7, 13, D3CCIPR_REG)
+#define ADC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 16, D3CCIPR_REG)
+#define SAI4A_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 21, D3CCIPR_REG)
+#define SAI4B_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 24, D3CCIPR_REG)
+#define SPI6_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 28, D3CCIPR_REG)
 /** BDCR devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
 /** CFGR devices */
-#define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0xF, 22, CFGR_REG)
-#define MCO1_PRE(val)           STM32_MCO_CFGR(val, 0x7, 18, CFGR_REG)
-#define MCO2_SEL(val)           STM32_MCO_CFGR(val, 0xF, 29, CFGR_REG)
-#define MCO2_PRE(val)           STM32_MCO_CFGR(val, 0x7, 25, CFGR_REG)
+#define MCO1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0xF, 22, CFGR_REG)
+#define MCO1_PRE(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 18, CFGR_REG)
+#define MCO2_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0xF, 29, CFGR_REG)
+#define MCO2_PRE(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 25, CFGR_REG)
 
 /* MCO prescaler : division factor */
 #define MCO_PRE_DIV_1 1
diff --git a/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h b/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h
index e2c1ed81289..d7943dbe73b 100644
--- a/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32h7rs_clock.h
@@ -54,34 +54,6 @@
 #define STM32_PERIPH_BUS_MIN	STM32_CLOCK_BUS_AHB5
 #define STM32_PERIPH_BUS_MAX	STM32_CLOCK_BUS_AHB3
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32H7RS clock configuration bit field.
- *
- * - reg   (0/1)           [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..3)          [ 16 : 18 ]
- *
- * @param reg RCC_DxCCIP register offset
- * @param shift Position within RCC_DxCCIP.
- * @param mask Mask for the RCC_DxCCIP field.
- * @param val Clock value (0, 1, 2 or 3).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |	\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |	\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_DxCCIP register offset (RM0477.pdf) */
 #define D1CCIPR_REG		0x4C
 #define D2CCIPR_REG		0x50
@@ -99,43 +71,44 @@
 /* TODO to be completed */
 
 /** D1CCIPR devices */
-#define FMC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, D1CCIPR_REG)
-#define SDMMC_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 2, D1CCIPR_REG)
-#define XSPI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 4, D1CCIPR_REG)
-#define XSPI2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 6, D1CCIPR_REG)
-#define ADC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 24, D1CCIPR_REG)
-#define CKPER_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 28, D1CCIPR_REG)
+#define FMC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, D1CCIPR_REG)
+#define SDMMC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 2, D1CCIPR_REG)
+#define XSPI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 4, D1CCIPR_REG)
+#define XSPI2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 6, D1CCIPR_REG)
+#define OTGFS_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 14, D1CCIPR_REG)
+#define ADC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 24, D1CCIPR_REG)
+#define CKPER_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 28, D1CCIPR_REG)
 
 /** D2CCIPR devices */
-#define USART234578_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 0, D2CCIPR_REG)
-#define SPI23_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 4, D2CCIPR_REG)
-#define I2C23_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, D2CCIPR_REG)
-#define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, D2CCIPR_REG)
-#define I3C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, D2CCIPR_REG)
-#define LPTIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 16, D2CCIPR_REG)
-#define FDCAN_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 22, D2CCIPR_REG)
+#define USART234578_SEL(val)	STM32_DT_CLOCK_SELECT((val), 7, 0, D2CCIPR_REG)
+#define SPI23_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 4, D2CCIPR_REG)
+#define I2C23_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, D2CCIPR_REG)
+#define I2C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 12, D2CCIPR_REG)
+#define I3C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 12, D2CCIPR_REG)
+#define LPTIM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 16, D2CCIPR_REG)
+#define FDCAN_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 22, D2CCIPR_REG)
 
 /** D3CCIPR devices */
-#define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 0, D3CCIPR_REG)
-#define SPI45_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 4, D3CCIPR_REG)
-#define SPI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 8, D3CCIPR_REG)
-#define SAI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 16, D3CCIPR_REG)
-#define SAI2_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 20, D3CCIPR_REG)
+#define USART1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 0, D3CCIPR_REG)
+#define SPI45_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 4, D3CCIPR_REG)
+#define SPI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 8, D3CCIPR_REG)
+#define SAI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 16, D3CCIPR_REG)
+#define SAI2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 20, D3CCIPR_REG)
 
 /** D4CCIPR devices */
-#define LPUART1_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 0, D4CCIPR_REG)
-#define SPI6_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 4, D4CCIPR_REG)
-#define LPTIM23_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 8, D4CCIPR_REG)
-#define LPTIM45_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 12, D4CCIPR_REG)
+#define LPUART1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 7, 0, D4CCIPR_REG)
+#define SPI6_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 4, D4CCIPR_REG)
+#define LPTIM23_SEL(val)	STM32_DT_CLOCK_SELECT((val), 7, 8, D4CCIPR_REG)
+#define LPTIM45_SEL(val)	STM32_DT_CLOCK_SELECT((val), 7, 12, D4CCIPR_REG)
 
 /** BDCR devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
 
 /** CFGR devices */
-#define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0x7, 22, CFGR_REG)
-#define MCO1_PRE(val)           STM32_MCO_CFGR(val, 0xF, 18, CFGR_REG)
-#define MCO2_SEL(val)           STM32_MCO_CFGR(val, 0x7, 29, CFGR_REG)
-#define MCO2_PRE(val)           STM32_MCO_CFGR(val, 0xF, 25, CFGR_REG)
+#define MCO1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 22, CFGR_REG)
+#define MCO1_PRE(val)           STM32_DT_CLOCK_SELECT((val), 0xF, 18, CFGR_REG)
+#define MCO2_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 29, CFGR_REG)
+#define MCO2_PRE(val)           STM32_DT_CLOCK_SELECT((val), 0xF, 25, CFGR_REG)
 
 /* MCO prescaler : division factor */
 #define MCO_PRE_DIV_1 1
diff --git a/include/zephyr/dt-bindings/clock/stm32l0_clock.h b/include/zephyr/dt-bindings/clock/stm32l0_clock.h
index c16e367a94e..44709e79962 100644
--- a/include/zephyr/dt-bindings/clock/stm32l0_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32l0_clock.h
@@ -31,34 +31,6 @@
 /** Bus clock */
 #define STM32_SRC_PCLK		(STM32_SRC_HSI48 + 1)
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CCIPRx register offset
- * @param shift Position within RCC_CCIPRx.
- * @param mask Mask for the RCC_CCIPRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CCIPR register offset */
 #define CCIPR_REG		0x4C
 
@@ -67,14 +39,14 @@
 
 /** @brief Device domain clocks selection helpers */
 /** CCIPR devices */
-#define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
-#define USART2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)
-#define LPUART1_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
-#define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
-#define I2C3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)
-#define LPTIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
-#define HSI48_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 26, CCIPR_REG)
+#define USART1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
+#define USART2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
+#define LPUART1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
+#define I2C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
+#define I2C3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG)
+#define LPTIM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
+#define HSI48_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 26, CCIPR_REG)
 /** CSR devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 16, CSR_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 16, CSR_REG)
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L0_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32l1_clock.h b/include/zephyr/dt-bindings/clock/stm32l1_clock.h
index f958f7b6bb8..9f94a18b8ff 100644
--- a/include/zephyr/dt-bindings/clock/stm32l1_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32l1_clock.h
@@ -26,37 +26,9 @@
 #define STM32_SRC_HSE		(STM32_SRC_LSI + 1)
 #define STM32_SRC_HSI		(STM32_SRC_HSE + 1)
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CCIPRx register offset
- * @param shift Position within RCC_CCIPRx.
- * @param mask Mask for the RCC_CCIPRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CSR register offset */
 #define CSR_REG		0x34
 
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 16, CSR_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 16, CSR_REG)
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L1_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32l4_clock.h b/include/zephyr/dt-bindings/clock/stm32l4_clock.h
index 3e865f9a880..eabfffc9ed2 100644
--- a/include/zephyr/dt-bindings/clock/stm32l4_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32l4_clock.h
@@ -37,34 +37,6 @@
 #define STM32_SRC_PLL_R		(STM32_SRC_PLL_Q + 1)
 /* TODO: PLLSAI clocks */
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CCIPRx register offset
- * @param shift Position within RCC_CCIPRx.
- * @param mask Mask for the RCC_CCIPRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CCIPR register offset */
 #define CCIPR_REG		0x88
 #define CCIPR2_REG		0x9C
@@ -77,36 +49,36 @@
 
 /** @brief Device domain clocks selection helpers */
 /** CCIPR devices */
-#define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
-#define USART2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)
-#define USART3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR_REG)
-#define UART4_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR_REG)
-#define UART5_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG)
-#define LPUART1_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
-#define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
-#define I2C2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
-#define I2C3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)
-#define LPTIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
-#define LPTIM2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)
-#define SAI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG)
-#define SAI2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR_REG)
-#define CLK48_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG)
-#define ADC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG)
-#define SWPMI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 30, CCIPR_REG)
-#define DFSDM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 31, CCIPR_REG)
+#define USART1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
+#define USART2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
+#define USART3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR_REG)
+#define UART4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR_REG)
+#define UART5_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)
+#define LPUART1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
+#define I2C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
+#define I2C2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG)
+#define I2C3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG)
+#define LPTIM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
+#define LPTIM2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)
+#define SAI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG)
+#define SAI2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR_REG)
+#define CLK48_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG)
+#define ADC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG)
+#define SWPMI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 30, CCIPR_REG)
+#define DFSDM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 31, CCIPR_REG)
 /** CCIPR2 devices */
-#define I2C4_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR2_REG)
-#define DFSDM_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 2, CCIPR2_REG)
-#define ADFSDM_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 3, CCIPR2_REG)
-/* #define SAI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 5, CCIPR2_REG) */
-/* #define SAI2_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 8, CCIPR2_REG) */
-#define DSI_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 12, CCIPR2_REG)
-#define SDMMC_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 14, CCIPR2_REG)
-#define OSPI_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR2_REG)
+#define I2C4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
+#define DFSDM_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 2, CCIPR2_REG)
+#define ADFSDM_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR2_REG)
+/* #define SAI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 5, CCIPR2_REG) */
+/* #define SAI2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR2_REG) */
+#define DSI_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 12, CCIPR2_REG)
+#define SDMMC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 14, CCIPR2_REG)
+#define OSPI_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR2_REG)
 /** BDCR devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
 /** CFGR devices */
-#define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0xF, 24, CFGR_REG)
-#define MCO1_PRE(val)           STM32_MCO_CFGR(val, 0x7, 28, CFGR_REG)
+#define MCO1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR_REG)
+#define MCO1_PRE(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR_REG)
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32L4_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32mp13_clock.h b/include/zephyr/dt-bindings/clock/stm32mp13_clock.h
new file mode 100644
index 00000000000..daf2d8ca2cd
--- /dev/null
+++ b/include/zephyr/dt-bindings/clock/stm32mp13_clock.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP13_CLOCK_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP13_CLOCK_H_
+
+#include "stm32_common_clocks.h"
+
+/** Bus clocks */
+#define STM32_CLOCK_BUS_APB1    0x700
+#define STM32_CLOCK_BUS_APB2    0x708
+#define STM32_CLOCK_BUS_APB3    0x710
+#define STM32_CLOCK_BUS_APB4    0x728
+#define STM32_CLOCK_BUS_APB5    0x740
+#define STM32_CLOCK_BUS_APB6    0x748
+#define STM32_CLOCK_BUS_AHB2    0x750
+#define STM32_CLOCK_BUS_AHB4    0x768
+#define STM32_CLOCK_BUS_AHB5    0x778
+#define STM32_CLOCK_BUS_AHB6    0x780
+
+#define STM32_PERIPH_BUS_MIN	STM32_CLOCK_BUS_APB1
+#define STM32_PERIPH_BUS_MAX	STM32_CLOCK_BUS_AHB6
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32MP13_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32n6_clock.h b/include/zephyr/dt-bindings/clock/stm32n6_clock.h
new file mode 100644
index 00000000000..85a8c3ec0b0
--- /dev/null
+++ b/include/zephyr/dt-bindings/clock/stm32n6_clock.h
@@ -0,0 +1,179 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32N6_CLOCK_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32N6_CLOCK_H_
+
+#include "stm32_common_clocks.h"
+
+/** Domain clocks */
+
+/* RM0486, Figures 37 and 45 on clock distribution description */
+
+/** System clock */
+/* defined in stm32_common_clocks.h */
+/** Fixed clocks  */
+#define STM32_SRC_HSE		(STM32_SRC_LSI + 1)
+#define STM32_SRC_HSI		(STM32_SRC_HSE + 1)
+#define STM32_SRC_MSI		(STM32_SRC_HSI + 1)
+/** PLL outputs */
+#define STM32_SRC_PLL1		(STM32_SRC_MSI + 1)
+#define STM32_SRC_PLL2		(STM32_SRC_PLL1 + 1)
+#define STM32_SRC_PLL3		(STM32_SRC_PLL2 + 1)
+#define STM32_SRC_PLL4		(STM32_SRC_PLL3 + 1)
+/** Clock muxes */
+#define STM32_SRC_CKPER		(STM32_SRC_PLL4 + 1)
+#define STM32_SRC_IC1		(STM32_SRC_CKPER + 1)
+#define STM32_SRC_IC2		(STM32_SRC_IC1 + 1)
+#define STM32_SRC_IC3		(STM32_SRC_IC2 + 1)
+#define STM32_SRC_IC4		(STM32_SRC_IC3 + 1)
+#define STM32_SRC_IC5		(STM32_SRC_IC4 + 1)
+#define STM32_SRC_IC6		(STM32_SRC_IC5 + 1)
+#define STM32_SRC_IC7		(STM32_SRC_IC6 + 1)
+#define STM32_SRC_IC8		(STM32_SRC_IC7 + 1)
+#define STM32_SRC_IC9		(STM32_SRC_IC8 + 1)
+#define STM32_SRC_IC10		(STM32_SRC_IC9 + 1)
+#define STM32_SRC_IC11		(STM32_SRC_IC10 + 1)
+#define STM32_SRC_IC12		(STM32_SRC_IC11 + 1)
+#define STM32_SRC_IC13		(STM32_SRC_IC12 + 1)
+#define STM32_SRC_IC14		(STM32_SRC_IC13 + 1)
+#define STM32_SRC_IC15		(STM32_SRC_IC14 + 1)
+#define STM32_SRC_IC16		(STM32_SRC_IC15 + 1)
+#define STM32_SRC_IC17		(STM32_SRC_IC16 + 1)
+#define STM32_SRC_IC18		(STM32_SRC_IC17 + 1)
+#define STM32_SRC_IC19		(STM32_SRC_IC18 + 1)
+#define STM32_SRC_IC20		(STM32_SRC_IC19 + 1)
+#define STM32_SRC_HSI_DIV	(STM32_SRC_IC20 + 1)
+#define STM32_SRC_TIMG		(STM32_SRC_HSI_DIV + 1)
+#define STM32_SRC_HCLK1		(STM32_SRC_TIMG + 1)
+#define STM32_SRC_HCLK2		(STM32_SRC_HCLK1 + 1)
+#define STM32_SRC_HCLK3		(STM32_SRC_HCLK2 + 1)
+#define STM32_SRC_HCLK4		(STM32_SRC_HCLK3 + 1)
+#define STM32_SRC_HCLK5		(STM32_SRC_HCLK4 + 1)
+#define STM32_SRC_PCLK1		(STM32_SRC_HCLK5 + 1)
+#define STM32_SRC_PCLK2		(STM32_SRC_PCLK1 + 1)
+#define STM32_SRC_PCLK4		(STM32_SRC_PCLK2 + 1)
+#define STM32_SRC_PCLK5		(STM32_SRC_PCLK4 + 1)
+
+/** Others: Not yet supported */
+/* #define STM32_SRC_I2SCKIN	TBD */
+
+/** Bus clocks */
+#define STM32_CLOCK_BUS_AHB1	0x250
+#define STM32_CLOCK_BUS_AHB2	0x254
+#define STM32_CLOCK_BUS_AHB3	0x258
+#define STM32_CLOCK_BUS_AHB4	0x25C
+#define STM32_CLOCK_BUS_AHB5	0x260
+#define STM32_CLOCK_BUS_APB1	0x264
+#define STM32_CLOCK_BUS_APB1_2	0x268
+#define STM32_CLOCK_BUS_APB2	0x26C
+#define STM32_CLOCK_BUS_APB3	0x270
+#define STM32_CLOCK_BUS_APB4	0x274
+#define STM32_CLOCK_BUS_APB4_2	0x278
+#define STM32_CLOCK_BUS_APB5	0x27C
+
+#define STM32_CLOCK_LP_BUS_SHIFT	0x40
+
+#define STM32_PERIPH_BUS_MIN	STM32_CLOCK_BUS_AHB1
+#define STM32_PERIPH_BUS_MAX	STM32_CLOCK_BUS_APB5
+
+/** @brief RCC_CCIPRx register offset (RM0486.pdf) */
+#define CCIPR1_REG		0x144
+#define CCIPR2_REG		0x148
+#define CCIPR3_REG		0x14C
+#define CCIPR4_REG		0x150
+#define CCIPR5_REG		0x154
+#define CCIPR6_REG		0x158
+#define CCIPR7_REG		0x15C
+#define CCIPR8_REG		0x160
+#define CCIPR9_REG		0x164
+#define CCIPR12_REG		0x170
+#define CCIPR13_REG		0x174
+#define CCIPR14_REG		0x178
+
+/** @brief Device domain clocks selection helpers */
+/** CCIPR1 devices */
+#define ADF1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR1_REG)
+#define ADC12_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR1_REG)
+#define DCMIPP_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR1_REG)
+/** CCIPR2 devices */
+#define ETH1PTP_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR2_REG)
+#define ETH1CLK_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
+#define ETH1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR2_REG)
+#define ETH1REFCLK_SEL(val)	STM32_DT_CLOCK_SELECT((val), 1, 20, CCIPR2_REG)
+#define ETH1GTXCLK_SEL(val)	STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR2_REG)
+/** CCIPR3 devices */
+#define FDCAN_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR3_REG)
+#define FMC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR3_REG)
+/** CCIPR4 devices */
+#define I2C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR4_REG)
+#define I2C2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR4_REG)
+#define I2C3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR4_REG)
+#define I2C4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR4_REG)
+#define I3C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR4_REG)
+#define I3C2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR4_REG)
+#define LTDC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR4_REG)
+/** CCIPR5 devices */
+#define MCO1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR5_REG)
+#define MCO2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR5_REG)
+#define MDF1SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR5_REG)
+/** CCIPR6 devices */
+#define XSPI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR6_REG)
+#define XSPI2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR6_REG)
+#define XSPI3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR6_REG)
+#define OTGPHY1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR6_REG)
+#define OTGPHY1CKREF_SEL(val)	STM32_DT_CLOCK_SELECT((val), 1, 16, CCIPR6_REG)
+#define OTGPHY2_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR6_REG)
+#define OTGPHY2CKREF_SEL(val)	STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR6_REG)
+/** CCIPR7 devices */
+#define PER_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR7_REG)
+#define PSSI_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR7_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR7_REG)
+#define SAI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR7_REG)
+#define SAI2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR7_REG)
+/** CCIPR8 devices */
+#define SDMMC1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR8_REG)
+#define SDMMC2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR8_REG)
+/** CCIPR9 devices */
+#define SPDIFRX1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR9_REG)
+#define SPI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR9_REG)
+#define SPI2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR9_REG)
+#define SPI3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR9_REG)
+#define SPI4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR9_REG)
+#define SPI5_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR9_REG)
+#define SPI6_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR9_REG)
+/** CCIPR12 devices */
+#define LPTIM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR12_REG)
+#define LPTIM2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR12_REG)
+#define LPTIM3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR12_REG)
+#define LPTIM4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR12_REG)
+#define LPTIM5_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR12_REG)
+/** CCIPR13 devices */
+#define USART1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR13_REG)
+#define USART2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR13_REG)
+#define USART3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR13_REG)
+#define UART4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR13_REG)
+#define UART5_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR13_REG)
+#define USART6_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 20, CCIPR13_REG)
+#define UART7_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 24, CCIPR13_REG)
+#define UART8_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 28, CCIPR13_REG)
+/** CCIPR14 devices */
+#define UART9_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR14_REG)
+#define USART10_SEL(val)	STM32_DT_CLOCK_SELECT((val), 7, 4, CCIPR14_REG)
+#define LPUART1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR14_REG)
+
+/** @brief RCC_ICxCFGR register offset (RM0486.pdf) */
+#define ICxCFGR_REG(ic)		(0xC4 + ((ic) - 1) * 4)
+
+/** @brief Divider ICx source selection */
+#define ICx_PLLy_SEL(ic, pll)	STM32_DT_CLOCK_SELECT((pll) - 1, 3, 28, ICxCFGR_REG(ic))
+
+/** @brief RCC_CFGR1 register offset (RM0486.pdf) */
+#define CFGR1_REG		0x20
+
+/** @brief CPU clock switch selection */
+#define CPU_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 16, CFGR1_REG)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32N6_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32u0_clock.h b/include/zephyr/dt-bindings/clock/stm32u0_clock.h
index 476c4236082..50e76c573d7 100644
--- a/include/zephyr/dt-bindings/clock/stm32u0_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32u0_clock.h
@@ -36,34 +36,6 @@
 #define STM32_SRC_PLL_Q		(STM32_SRC_PLL_P + 1)
 #define STM32_SRC_PLL_R		(STM32_SRC_PLL_Q + 1)
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CCIPRx register offset
- * @param shift Position within RCC_CCIPRx.
- * @param mask Mask for the RCC_CCIPRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CCIPR register offset */
 #define CCIPR_REG		0x88
 
@@ -72,21 +44,21 @@
 
 /** @brief Device domain clocks selection helpers */
 /** CCIPR devices */
-#define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
-#define USART2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)
-#define LPUART3_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR_REG)
-#define LPUART2_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG)
-#define LPUART1_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
-#define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
-#define I2C3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)
-#define LPTIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
-#define LPTIM2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)
-#define LPTIM3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG)
-#define TIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 24, CCIPR_REG)
-#define TIM15_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 25, CCIPR_REG)
-#define CLK48_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG)
-#define ADC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG)
+#define USART1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
+#define USART2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
+#define LPUART3_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR_REG)
+#define LPUART2_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)
+#define LPUART1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
+#define I2C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
+#define I2C3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG)
+#define LPTIM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
+#define LPTIM2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)
+#define LPTIM3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG)
+#define TIM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 24, CCIPR_REG)
+#define TIM15_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 25, CCIPR_REG)
+#define CLK48_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG)
+#define ADC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG)
 /** BDCR devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32U0_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32u5_clock.h b/include/zephyr/dt-bindings/clock/stm32u5_clock.h
index 4bb1f349cdd..e1d131b70cb 100644
--- a/include/zephyr/dt-bindings/clock/stm32u5_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32u5_clock.h
@@ -11,7 +11,7 @@
 
 /** Domain clocks */
 
-/* RM0468, Table 56 Kernel clock distribution summary */
+/* RM0456, Figure 36 Clock tree for STM32U5 Series */
 
 /** System clock */
 /* defined in stm32_common_clocks.h */
@@ -52,34 +52,6 @@
 #define STM32_PERIPH_BUS_MIN	STM32_CLOCK_BUS_AHB1
 #define STM32_PERIPH_BUS_MAX	STM32_CLOCK_BUS_APB3
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32U5 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CCIPRx register offset
- * @param shift Position within RCC_CCIPRx.
- * @param mask Mask for the RCC_CCIPRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |	\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |	\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CCIPRx register offset (RM0456.pdf) */
 #define CCIPR1_REG		0xE0
 #define CCIPR2_REG		0xE4
@@ -93,51 +65,51 @@
 
 /** @brief Device domain clocks selection helpers */
 /** CCIPR1 devices */
-#define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR1_REG)
-#define USART2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR1_REG)
-#define USART3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 4, CCIPR1_REG)
-#define UART4_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR1_REG)
-#define UART5_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR1_REG)
-#define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR1_REG)
-#define I2C2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR1_REG)
-#define I2C4_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR1_REG)
-#define SPI2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR1_REG)
-#define LPTIM2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR1_REG)
-#define SPI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR1_REG)
-#define SYSTICK_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR1_REG)
-#define FDCAN1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR1_REG)
-#define ICKLK_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR1_REG)
-#define TIMIC_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 29, CCIPR1_REG)
+#define USART1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR1_REG)
+#define USART2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR1_REG)
+#define USART3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR1_REG)
+#define UART4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR1_REG)
+#define UART5_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR1_REG)
+#define I2C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR1_REG)
+#define I2C2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR1_REG)
+#define I2C4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR1_REG)
+#define SPI2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR1_REG)
+#define LPTIM2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR1_REG)
+#define SPI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR1_REG)
+#define SYSTICK_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR1_REG)
+#define FDCAN1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR1_REG)
+#define ICKLK_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR1_REG)
+#define TIMIC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 29, CCIPR1_REG)
 /** CCIPR2 devices */
-#define MDF1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR2_REG)
-#define SAI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 5, CCIPR2_REG)
-#define SAI2_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 8, CCIPR2_REG)
-#define SAE_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 11, CCIPR2_REG)
-#define RNG_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR2_REG)
-#define SDMMC_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 14, CCIPR2_REG)
-#define DSIHOST_SEL(val)	STM32_DOMAIN_CLOCK(val, 1, 15, CCIPR2_REG)
-#define USART6_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 16, CCIPR2_REG)
-#define LTDC_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 18, CCIPR2_REG)
-#define OCTOSPI_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR2_REG)
-#define HSPI_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR2_REG)
-#define I2C5_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 24, CCIPR2_REG)
-#define I2C6_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR2_REG)
-#define OTGHS_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR2_REG)
+#define MDF1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR2_REG)
+#define SAI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 5, CCIPR2_REG)
+#define SAI2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 8, CCIPR2_REG)
+#define SAE_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 11, CCIPR2_REG)
+#define RNG_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
+#define SDMMC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 14, CCIPR2_REG)
+#define DSIHOST_SEL(val)	STM32_DT_CLOCK_SELECT((val), 1, 15, CCIPR2_REG)
+#define USART6_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 16, CCIPR2_REG)
+#define LTDC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 18, CCIPR2_REG)
+#define OCTOSPI_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR2_REG)
+#define HSPI_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR2_REG)
+#define I2C5_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 24, CCIPR2_REG)
+#define I2C6_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR2_REG)
+#define OTGHS_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR2_REG)
 /** CCIPR3 devices */
-#define LPUART1_SEL(val)	STM32_DOMAIN_CLOCK(val, 7, 0, CCIPR3_REG)
-#define SPI3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 3, CCIPR3_REG)
-#define I2C3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR3_REG)
-#define LPTIM34_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR3_REG)
-#define LPTIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR3_REG)
-#define ADCDAC_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR3_REG)
-#define DAC1_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 15, CCIPR3_REG)
-#define ADF1_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 16, CCIPR3_REG)
+#define LPUART1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 7, 0, CCIPR3_REG)
+#define SPI3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR3_REG)
+#define I2C3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR3_REG)
+#define LPTIM34_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR3_REG)
+#define LPTIM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR3_REG)
+#define ADCDAC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR3_REG)
+#define DAC1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 15, CCIPR3_REG)
+#define ADF1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 16, CCIPR3_REG)
 /** BDCR devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
 
 /** CFGR1 devices */
-#define MCO1_SEL(val)           STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG)
-#define MCO1_PRE(val)           STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG)
+#define MCO1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG)
+#define MCO1_PRE(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG)
 
 /* MCO prescaler : division factor */
 #define MCO_PRE_DIV_1  0
diff --git a/include/zephyr/dt-bindings/clock/stm32wb0_clock.h b/include/zephyr/dt-bindings/clock/stm32wb0_clock.h
index 23ba8e99608..d3b96b49ca4 100644
--- a/include/zephyr/dt-bindings/clock/stm32wb0_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32wb0_clock.h
@@ -27,34 +27,6 @@
 #define STM32_PERIPH_BUS_MIN	STM32_CLOCK_BUS_AHB0
 #define STM32_PERIPH_BUS_MAX	STM32_CLOCK_BUS_APB2
 
-#define STM32_CLOCK_REG_MASK	(0xFFFFU)
-#define STM32_CLOCK_REG_SHIFT	(0U)
-#define STM32_CLOCK_SHIFT_MASK  (0x3FU)
-#define STM32_CLOCK_SHIFT_SHIFT (16U)
-#define STM32_CLOCK_MASK_MASK   (0x1FU)
-#define STM32_CLOCK_MASK_SHIFT  (22U)
-#define STM32_CLOCK_VAL_MASK    STM32_CLOCK_MASK_MASK
-#define STM32_CLOCK_VAL_SHIFT   (27U)
-
-/**
- * @brief STM32 clock configuration bit field
- *
- * @param reg	Offset to target configuration register in RCC
- * @param shift	Position of field within RCC register (= field LSB's index)
- * @param mask	Mask of field in RCC register
- * @param val	Field value
- *
- * @note 'reg' range:	0x0~0xFFFF	[ 00 : 15 ]
- * @note 'shift' range:	0~63		[ 16 : 21 ]
- * @note 'mask' range:	0x00~0x1F	[ 22 : 26 ]
- * @note 'val' range:	0x00~0x1F	[ 27 : 31 ]
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)				\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CFGR register offset */
 #define CFGR_REG	0x08
 
@@ -62,9 +34,12 @@
 #define APB2ENR_REG	0x60
 
 /** @brief Device clk sources selection helpers */
-#define LPUART1_SEL(val)	STM32_DOMAIN_CLOCK(val, 1, 13, CFGR_REG)	/* WB05/WB09 only */
-#define SPI2_I2S2_SEL(val)	STM32_DOMAIN_CLOCK(val, 1, 22, CFGR_REG)	/* WB06/WB07 only */
+
+/* WB05/WB09 only */
+#define LPUART1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 1, 13, CFGR_REG)
+/* WB06/WB07 only */
+#define SPI2_I2S2_SEL(val)	STM32_DT_CLOCK_SELECT((val), 1, 22, CFGR_REG)
 /* `mask` is only 0x1 for WB06/WB07, but a single definition with mask=0x3 is acceptable */
-#define SPI3_I2S3_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 22, CFGR_REG)
+#define SPI3_I2S3_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 22, CFGR_REG)
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB0_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32wb_clock.h b/include/zephyr/dt-bindings/clock/stm32wb_clock.h
index 31786c8675d..f56e70e54b9 100644
--- a/include/zephyr/dt-bindings/clock/stm32wb_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32wb_clock.h
@@ -38,34 +38,6 @@
 #define STM32_SRC_PLL_R		(STM32_SRC_PLL_Q + 1)
 /* TODO: PLLSAI clocks */
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CCIPRx register offset
- * @param shift Position within RCC_CCIPRx.
- * @param mask Mask for the RCC_CCIPRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CCIPR register offset */
 #define CCIPR_REG		0x88
 
@@ -77,19 +49,19 @@
 
 /** @brief Device domain clocks selection helpers */
 /** CCIPR devices */
-#define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
-#define LPUART1_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
-#define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
-#define I2C3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)
-#define LPTIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
-#define LPTIM2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)
-#define SAI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG)
-#define CLK48_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 26, CCIPR_REG)
-#define ADC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG)
-#define RNG_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)
+#define USART1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
+#define LPUART1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
+#define I2C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
+#define I2C3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG)
+#define LPTIM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
+#define LPTIM2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)
+#define SAI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG)
+#define CLK48_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 26, CCIPR_REG)
+#define ADC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG)
+#define RNG_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG)
 /** BDCR devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
 /** CSR devices */
-#define RFWKP_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 14, CSR_REG)
+#define RFWKP_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 14, CSR_REG)
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WB_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32wba_clock.h b/include/zephyr/dt-bindings/clock/stm32wba_clock.h
index b8baaada6be..d77dfba5cbe 100644
--- a/include/zephyr/dt-bindings/clock/stm32wba_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32wba_clock.h
@@ -10,7 +10,8 @@
 
 /** Peripheral clock sources */
 
-/* RM0493, Figure 30, clock tree */
+/* RM0493, Figure 34, clock tree */
+/* RM0515, Figure 36, clock tree */
 
 /** System clock */
 /* defined in stm32_common_clocks.h */
@@ -45,35 +46,6 @@
 #define STM32_PERIPH_BUS_MIN	STM32_CLOCK_BUS_AHB1
 #define STM32_PERIPH_BUS_MAX	STM32_CLOCK_BUS_APB7
 
-/**
- * @brief STM32WBA clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CCIPRx register offset
- * @param shift Position within RCC_CCIPRx.
- * @param mask Mask for the RCC_CCIPRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |	\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |	\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CCIPRx register offset (RM0493.pdf) */
 #define CCIPR1_REG		0xE0
 #define CCIPR2_REG		0xE4
@@ -83,22 +55,50 @@
 
 /** @brief Device clk sources selection helpers */
 /** CCIPR1 devices */
-#define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR1_REG)
-#define USART2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR1_REG)
-#define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR1_REG)
-#define LPTIM2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR1_REG)
-#define SPI1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR1_REG)
-#define SYSTICK_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR1_REG)
-#define TIMIC_SEL(val)		STM32_DOMAIN_CLOCK(val, 1, 31, CCIPR1_REG)
+#define USART1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR1_REG)
+#define USART2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR1_REG)
+#define USART3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 4, CCIPR1_REG)
+#define I2C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR1_REG)
+#define I2C2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR1_REG)
+#define I2C4_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR1_REG)
+#define SPI2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR1_REG)
+#define LPTIM2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR1_REG)
+#define SPI1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR1_REG)
+#define SYSTICK_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR1_REG)
+#define TIMIC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 1, 31, CCIPR1_REG)
 /** CCIPR2 devices */
-#define RNG_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR2_REG)
+#define RNG_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR2_REG)
 /** CCIPR3 devices */
-#define LPUART1_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR3_REG)
-#define SPI3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 3, CCIPR3_REG)
-#define I2C3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 6, CCIPR3_REG)
-#define LPTIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR3_REG)
-#define ADC_SEL(val)		STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR3_REG)
+#define LPUART1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR3_REG)
+#define SPI3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 3, CCIPR3_REG)
+#define I2C3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 6, CCIPR3_REG)
+#define LPTIM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR3_REG)
+#define ADC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 7, 12, CCIPR3_REG)
 /** BCDR1 devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BCDR1_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, BCDR1_REG)
+/** @brief RCC_CFGRx register offset */
+#define CFGR1_REG               0x1C
+/** CFGR1 devices */
+#define MCO1_SEL(val)           STM32_DT_CLOCK_SELECT((val), 0xF, 24, CFGR1_REG)
+#define MCO1_PRE(val)           STM32_DT_CLOCK_SELECT((val), 0x7, 28, CFGR1_REG)
+
+/* MCO prescaler : division factor */
+#define MCO_PRE_DIV_1 0
+#define MCO_PRE_DIV_2 1
+#define MCO_PRE_DIV_4 2
+#define MCO_PRE_DIV_8 3
+#define MCO_PRE_DIV_16 4
+
+/* MCO clock output */
+#define MCO_SEL_SYSCLKPRE 1
+#define MCO_SEL_HSI16 3
+#define MCO_SEL_HSE32 4
+#define MCO_SEL_PLL1RCLK 5
+#define MCO_SEL_LSI 6
+#define MCO_SEL_LSE 7
+#define MCO_SEL_PLL1PCLK 8
+#define MCO_SEL_PLL1QCLK 9
+#define MCO_SEL_HCLK5 10
+
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/clock/stm32wl_clock.h b/include/zephyr/dt-bindings/clock/stm32wl_clock.h
index 7384703267e..adcfd164777 100644
--- a/include/zephyr/dt-bindings/clock/stm32wl_clock.h
+++ b/include/zephyr/dt-bindings/clock/stm32wl_clock.h
@@ -38,55 +38,52 @@
 #define STM32_SRC_PLL_Q		(STM32_SRC_PLL_P + 1)
 #define STM32_SRC_PLL_R		(STM32_SRC_PLL_Q + 1)
 
-#define STM32_CLOCK_REG_MASK    0xFFU
-#define STM32_CLOCK_REG_SHIFT   0U
-#define STM32_CLOCK_SHIFT_MASK  0x1FU
-#define STM32_CLOCK_SHIFT_SHIFT 8U
-#define STM32_CLOCK_MASK_MASK   0x7U
-#define STM32_CLOCK_MASK_SHIFT  13U
-#define STM32_CLOCK_VAL_MASK    0x7U
-#define STM32_CLOCK_VAL_SHIFT   16U
-
-/**
- * @brief STM32 clock configuration bit field.
- *
- * - reg   (1/2/3)         [ 0 : 7 ]
- * - shift (0..31)         [ 8 : 12 ]
- * - mask  (0x1, 0x3, 0x7) [ 13 : 15 ]
- * - val   (0..7)          [ 16 : 18 ]
- *
- * @param reg RCC_CCIPRx register offset
- * @param shift Position within RCC_CCIPRx.
- * @param mask Mask for the RCC_CCIPRx field.
- * @param val Clock value (0, 1, ... 7).
- */
-#define STM32_DOMAIN_CLOCK(val, mask, shift, reg)					\
-	((((reg) & STM32_CLOCK_REG_MASK) << STM32_CLOCK_REG_SHIFT) |		\
-	 (((shift) & STM32_CLOCK_SHIFT_MASK) << STM32_CLOCK_SHIFT_SHIFT) |	\
-	 (((mask) & STM32_CLOCK_MASK_MASK) << STM32_CLOCK_MASK_SHIFT) |		\
-	 (((val) & STM32_CLOCK_VAL_MASK) << STM32_CLOCK_VAL_SHIFT))
-
 /** @brief RCC_CCIPR register offset */
 #define CCIPR_REG		0x88
 
 /** @brief RCC_BDCR register offset */
 #define BDCR_REG		0x90
 
+/** @brief RCC_CFGRx register offset */
+#define CFGR1_REG        0x08
+
 /** @brief Device domain clocks selection helpers */
 /** CCIPR devices */
-#define USART1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 0, CCIPR_REG)
-#define USART2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 2, CCIPR_REG)
-#define SPI2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, CCIPR_REG)
-#define LPUART1_SEL(val)	STM32_DOMAIN_CLOCK(val, 3, 10, CCIPR_REG)
-#define I2C1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 12, CCIPR_REG)
-#define I2C2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 14, CCIPR_REG)
-#define I2C3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 16, CCIPR_REG)
-#define LPTIM1_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 18, CCIPR_REG)
-#define LPTIM2_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 20, CCIPR_REG)
-#define LPTIM3_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 22, CCIPR_REG)
-#define ADC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 28, CCIPR_REG)
-#define RNG_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 30, CCIPR_REG)
+#define USART1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 0, CCIPR_REG)
+#define USART2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 2, CCIPR_REG)
+#define SPI2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, CCIPR_REG)
+#define LPUART1_SEL(val)	STM32_DT_CLOCK_SELECT((val), 3, 10, CCIPR_REG)
+#define I2C1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 12, CCIPR_REG)
+#define I2C2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 14, CCIPR_REG)
+#define I2C3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 16, CCIPR_REG)
+#define LPTIM1_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 18, CCIPR_REG)
+#define LPTIM2_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 20, CCIPR_REG)
+#define LPTIM3_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 22, CCIPR_REG)
+#define ADC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 28, CCIPR_REG)
+#define RNG_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 30, CCIPR_REG)
 /** BDCR devices */
-#define RTC_SEL(val)		STM32_DOMAIN_CLOCK(val, 3, 8, BDCR_REG)
+#define RTC_SEL(val)		STM32_DT_CLOCK_SELECT((val), 3, 8, BDCR_REG)
+/** CFGR1 devices */
+#define MCO1_SEL(val)       STM32_DT_CLOCK_SELECT(val, 0xF, 24, CFGR1_REG)
+#define MCO1_PRE(val)       STM32_DT_CLOCK_SELECT(val, 0x7, 28, CFGR1_REG)
+
+/* MCO prescaler : division factor */
+#define MCO_PRE_DIV_1  0
+#define MCO_PRE_DIV_2  1
+#define MCO_PRE_DIV_4  2
+#define MCO_PRE_DIV_8  3
+#define MCO_PRE_DIV_16 4
+
+/* MCO clock output */
+#define MCO_SEL_NOCLK     0
+#define MCO_SEL_SYSCLKPRE 1
+#define MCO_SEL_MSI       2
+#define MCO_SEL_HSI16     3
+#define MCO_SEL_HSE32     4
+#define MCO_SEL_PLL1RCLK  5
+#define MCO_SEL_LSI       6
+#define MCO_SEL_LSE       8
+#define MCO_SEL_PLL1PCLK  13
+#define MCO_SEL_PLL1QCLK  14
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WL_CLOCK_H_ */
diff --git a/include/zephyr/dt-bindings/comparator/silabs-acmp.h b/include/zephyr/dt-bindings/comparator/silabs-acmp.h
new file mode 100644
index 00000000000..e326c2b3ebe
--- /dev/null
+++ b/include/zephyr/dt-bindings/comparator/silabs-acmp.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * This file was generated by the script gen_acmp.py in the hal_silabs module.
+ * Do not manually edit.
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_COMPARATOR_SILABS_ACMP_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_COMPARATOR_SILABS_ACMP_H_
+
+/* ACMP Input Aliases */
+#define ACMP_INPUT_VDACOUT0 ACMP_INPUT_VDAC0OUT0
+#define ACMP_INPUT_VDACOUT1 ACMP_INPUT_VDAC0OUT1
+
+/* ACMP Input Definitions */
+#define ACMP_INPUT_VSS               0x0
+#define ACMP_INPUT_VREFDIVAVDD       0x10
+#define ACMP_INPUT_VREFDIVAVDDLP     0x11
+#define ACMP_INPUT_VREFDIV1V25       0x12
+#define ACMP_INPUT_VREFDIV1V25LP     0x13
+#define ACMP_INPUT_VREFDIV2V5        0x14
+#define ACMP_INPUT_VREFDIV2V5LP      0x15
+#define ACMP_INPUT_VSENSE01DIV4      0x20
+#define ACMP_INPUT_VSENSE01DIV4LP    0x21
+#define ACMP_INPUT_VSENSE11DIV4      0x22
+#define ACMP_INPUT_VSENSE11DIV4LP    0x23
+#define ACMP_INPUT_CAPSENSE          0x30
+#define ACMP_INPUT_VDAC0OUT0         0x40
+#define ACMP_INPUT_VDAC0OUT1         0x41
+#define ACMP_INPUT_VDAC1OUT0         0x42
+#define ACMP_INPUT_VDAC1OUT1         0x43
+#define ACMP_INPUT_EXTPA             0x50
+#define ACMP_INPUT_EXTPB             0x51
+#define ACMP_INPUT_EXTPC             0x52
+#define ACMP_INPUT_EXTPD             0x53
+#define ACMP_INPUT_PA0               0x80
+#define ACMP_INPUT_PA1               0x81
+#define ACMP_INPUT_PA2               0x82
+#define ACMP_INPUT_PA3               0x83
+#define ACMP_INPUT_PA4               0x84
+#define ACMP_INPUT_PA5               0x85
+#define ACMP_INPUT_PA6               0x86
+#define ACMP_INPUT_PA7               0x87
+#define ACMP_INPUT_PA8               0x88
+#define ACMP_INPUT_PA9               0x89
+#define ACMP_INPUT_PA10              0x8a
+#define ACMP_INPUT_PA11              0x8b
+#define ACMP_INPUT_PA12              0x8c
+#define ACMP_INPUT_PA13              0x8d
+#define ACMP_INPUT_PA14              0x8e
+#define ACMP_INPUT_PA15              0x8f
+#define ACMP_INPUT_PB0               0x90
+#define ACMP_INPUT_PB1               0x91
+#define ACMP_INPUT_PB2               0x92
+#define ACMP_INPUT_PB3               0x93
+#define ACMP_INPUT_PB4               0x94
+#define ACMP_INPUT_PB5               0x95
+#define ACMP_INPUT_PB6               0x96
+#define ACMP_INPUT_PB7               0x97
+#define ACMP_INPUT_PB8               0x98
+#define ACMP_INPUT_PB9               0x99
+#define ACMP_INPUT_PB10              0x9a
+#define ACMP_INPUT_PB11              0x9b
+#define ACMP_INPUT_PB12              0x9c
+#define ACMP_INPUT_PB13              0x9d
+#define ACMP_INPUT_PB14              0x9e
+#define ACMP_INPUT_PB15              0x9f
+#define ACMP_INPUT_PC0               0xa0
+#define ACMP_INPUT_PC1               0xa1
+#define ACMP_INPUT_PC2               0xa2
+#define ACMP_INPUT_PC3               0xa3
+#define ACMP_INPUT_PC4               0xa4
+#define ACMP_INPUT_PC5               0xa5
+#define ACMP_INPUT_PC6               0xa6
+#define ACMP_INPUT_PC7               0xa7
+#define ACMP_INPUT_PC8               0xa8
+#define ACMP_INPUT_PC9               0xa9
+#define ACMP_INPUT_PC10              0xaa
+#define ACMP_INPUT_PC11              0xab
+#define ACMP_INPUT_PC12              0xac
+#define ACMP_INPUT_PC13              0xad
+#define ACMP_INPUT_PC14              0xae
+#define ACMP_INPUT_PC15              0xaf
+#define ACMP_INPUT_PD0               0xb0
+#define ACMP_INPUT_PD1               0xb1
+#define ACMP_INPUT_PD2               0xb2
+#define ACMP_INPUT_PD3               0xb3
+#define ACMP_INPUT_PD4               0xb4
+#define ACMP_INPUT_PD5               0xb5
+#define ACMP_INPUT_PD6               0xb6
+#define ACMP_INPUT_PD7               0xb7
+#define ACMP_INPUT_PD8               0xb8
+#define ACMP_INPUT_PD9               0xb9
+#define ACMP_INPUT_PD10              0xba
+#define ACMP_INPUT_PD11              0xbb
+#define ACMP_INPUT_PD12              0xbc
+#define ACMP_INPUT_PD13              0xbd
+#define ACMP_INPUT_PD14              0xbe
+#define ACMP_INPUT_PD15              0xbf
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_COMPARATOR_SILABS_ACMP_H_ */
diff --git a/include/zephyr/dt-bindings/display/panel.h b/include/zephyr/dt-bindings/display/panel.h
index e1957e9a66b..c2e26e508be 100644
--- a/include/zephyr/dt-bindings/display/panel.h
+++ b/include/zephyr/dt-bindings/display/panel.h
@@ -23,12 +23,13 @@
  * since enum definitions are not supported by devicetree tooling.
  */
 
-#define PANEL_PIXEL_FORMAT_RGB_888		(0x1 << 0)
-#define PANEL_PIXEL_FORMAT_MONO01		(0x1 << 1) /* 0=Black 1=White */
-#define PANEL_PIXEL_FORMAT_MONO10		(0x1 << 2) /* 1=Black 0=White */
-#define PANEL_PIXEL_FORMAT_ARGB_8888		(0x1 << 3)
-#define PANEL_PIXEL_FORMAT_RGB_565		(0x1 << 4)
-#define PANEL_PIXEL_FORMAT_BGR_565		(0x1 << 5)
+#define PANEL_PIXEL_FORMAT_RGB_888   (0x1 << 0)
+#define PANEL_PIXEL_FORMAT_MONO01    (0x1 << 1) /* 0=Black 1=White */
+#define PANEL_PIXEL_FORMAT_MONO10    (0x1 << 2) /* 1=Black 0=White */
+#define PANEL_PIXEL_FORMAT_ARGB_8888 (0x1 << 3)
+#define PANEL_PIXEL_FORMAT_RGB_565   (0x1 << 4)
+#define PANEL_PIXEL_FORMAT_BGR_565   (0x1 << 5)
+#define PANEL_PIXEL_FORMAT_L_8       (0x1 << 6)
 
 /**
  * @}
diff --git a/include/zephyr/dt-bindings/dma/atmel_samx7x_dma.h b/include/zephyr/dt-bindings/dma/atmel_samx7x_dma.h
new file mode 100644
index 00000000000..e0914d454ba
--- /dev/null
+++ b/include/zephyr/dt-bindings/dma/atmel_samx7x_dma.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2020 Linaro Limited
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_ATMEL_SAMX7X_DMA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_ATMEL_SAMX7X_DMA_H_
+
+/**
+ * Atmel SAMx7x Peripheral Hardware Request HW Interface Number (XDMAC_CC.PERID).
+ *
+ * See table Table 35-1. Peripheral Hardware Requests in the SAM E70/S70/V70/V71 datasheet.
+ */
+#define DMA_PERID_HSMCI_TX_RX 0
+#define DMA_PERID_SPI0_TX     1
+#define DMA_PERID_SPI0_RX     2
+#define DMA_PERID_SPI1_TX     3
+#define DMA_PERID_SPI1_RX     4
+#define DMA_PERID_QSPI_TX     5
+#define DMA_PERID_QSPI_RX     6
+#define DMA_PERID_USART0_TX   7
+#define DMA_PERID_USART0_RX   8
+#define DMA_PERID_USART1_TX   9
+#define DMA_PERID_USART1_RX   10
+#define DMA_PERID_USART2_TX   11
+#define DMA_PERID_USART2_RX   12
+#define DMA_PERID_PWM0_TX     13
+#define DMA_PERID_TWIHS0_TX   14
+#define DMA_PERID_TWIHS0_RX   15
+#define DMA_PERID_TWIHS1_TX   16
+#define DMA_PERID_TWIHS1_RX   17
+#define DMA_PERID_TWIHS2_TX   18
+#define DMA_PERID_TWIHS2_RX   19
+#define DMA_PERID_UART0_TX    20
+#define DMA_PERID_UART0_RX    21
+#define DMA_PERID_UART1_TX    22
+#define DMA_PERID_UART1_RX    23
+#define DMA_PERID_UART2_TX    24
+#define DMA_PERID_UART2_RX    25
+#define DMA_PERID_UART3_TX    26
+#define DMA_PERID_UART3_RX    27
+#define DMA_PERID_UART4_TX    28
+#define DMA_PERID_UART4_RX    29
+#define DMA_PERID_DACC0_TX    30
+#define DMA_PERID_DACC1_TX    31
+#define DMA_PERID_SSC_TX      32
+#define DMA_PERID_SSC_RX      33
+#define DMA_PERID_PIOA_RX     34
+#define DMA_PERID_AFEC0_RX    35
+#define DMA_PERID_AFEC1_RX    36
+#define DMA_PERID_AES_TX      37
+#define DMA_PERID_AES_RX      38
+#define DMA_PERID_PWM1_TX     39
+#define DMA_PERID_TC0_RX      40
+#define DMA_PERID_TC1_RX      41
+#define DMA_PERID_TC2_RX      42
+#define DMA_PERID_TC3_RX      43
+#define DMA_PERID_I2SC0_TX_L  44
+#define DMA_PERID_I2SC0_RX_L  45
+#define DMA_PERID_I2SC1_TX_L  46
+#define DMA_PERID_I2SC1_RX_L  47
+#define DMA_PERID_I2SC0_TX_R  48
+#define DMA_PERID_I2SC0_RX_R  49
+#define DMA_PERID_I2SC1_TX_R  50
+#define DMA_PERID_I2SC1_RX_R  51
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_ATMEL_SAMX7X_DMA_H_ */
diff --git a/include/zephyr/dt-bindings/dma/ch32v003-dma.h b/include/zephyr/dt-bindings/dma/ch32v003-dma.h
new file mode 100644
index 00000000000..0860afcb65a
--- /dev/null
+++ b/include/zephyr/dt-bindings/dma/ch32v003-dma.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025 Paul Wedeck
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_CH32V003_DMA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_CH32V003_DMA_H_
+
+#define CH32V003_ADC1_DMA 0
+
+#define CH32V003_SPI1_RX_DMA 1
+#define CH32V003_SPI1_TX_DMA 2
+
+#define CH32V003_USART1_RX_DMA 4
+#define CH32V003_USART1_TX_DMA 3
+
+#define CH32V003_I2C1_RX_DMA 6
+#define CH32V003_I2C1_TX_DMA 5
+
+#define CH32V003_TIM1_CH1_DMA 1
+#define CH32V003_TIM1_CH2_DMA 2
+#define CH32V003_TIM1_CH3_DMA 5
+#define CH32V003_TIM1_CH4_DMA 3
+#define CH32V003_TIM1_TRIG 3
+#define CH32V003_TIM1_COM 3
+#define CH32V003_TIM1_UP 4
+
+#define CH32V003_TIM2_CH1_DMA 4
+#define CH32V003_TIM2_CH2_DMA 6
+#define CH32V003_TIM2_CH3_DMA 0
+#define CH32V003_TIM2_CH4_DMA 6
+#define CH32V003_TIM2_UP 1
+
+#endif /*ZEPHYR_INCLUDE_DT_BINDINGS_CH32V003_DMA_H_*/
diff --git a/include/zephyr/dt-bindings/dma/max32660_dma.h b/include/zephyr/dt-bindings/dma/max32660_dma.h
new file mode 100644
index 00000000000..e52805e1ab6
--- /dev/null
+++ b/include/zephyr/dt-bindings/dma/max32660_dma.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32660_DMA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32660_DMA_H_
+
+#define MAX32_DMA_SLOT_MEMTOMEM  0x00U
+#define MAX32_DMA_SLOT_SPI0_RX   0x01U
+#define MAX32_DMA_SLOT_SPI1_RX   0x02U
+#define MAX32_DMA_SLOT_UART0_RX  0x04U
+#define MAX32_DMA_SLOT_UART1_RX  0x05U
+#define MAX32_DMA_SLOT_I2C0_RX   0x07U
+#define MAX32_DMA_SLOT_I2C1_RX   0x08U
+#define MAX32_DMA_SLOT_SPI0_TX   0x21U
+#define MAX32_DMA_SLOT_SPI1_TX   0x22U
+#define MAX32_DMA_SLOT_UART0_TX  0x24U
+#define MAX32_DMA_SLOT_UART1_TX  0x25U
+#define MAX32_DMA_SLOT_I2C0_TX   0x27U
+#define MAX32_DMA_SLOT_I2C1_TX   0x28U
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX32660_DMA_H_ */
diff --git a/include/zephyr/dt-bindings/dma/max78000_dma.h b/include/zephyr/dt-bindings/dma/max78000_dma.h
new file mode 100644
index 00000000000..b899748e46d
--- /dev/null
+++ b/include/zephyr/dt-bindings/dma/max78000_dma.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX78000_DMA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX78000_DMA_H_
+
+#define MAX78_DMA_SLOT_MEMTOMEM 0x00U
+#define MAX78_DMA_SLOT_SPI1_RX  0x01U
+#define MAX78_DMA_SLOT_UART0_RX 0x04U
+#define MAX78_DMA_SLOT_UART1_RX 0x05U
+#define MAX78_DMA_SLOT_I2C0_RX  0x07U
+#define MAX78_DMA_SLOT_I2C1_RX  0x08U
+#define MAX78_DMA_SLOT_ADC      0x09U
+#define MAX78_DMA_SLOT_I2C2_RX  0x0AU
+#define MAX78_DMA_SLOT_PCIF_RX  0x0DU
+#define MAX78_DMA_SLOT_UART2_RX 0x0EU
+#define MAX78_DMA_SLOT_SPI0_RX  0x0FU
+#define MAX78_DMA_SLOT_UART3_RX 0x1CU
+#define MAX78_DMA_SLOT_I2S_RX   0x1EU
+#define MAX78_DMA_SLOT_SPI1_TX  0x21U
+#define MAX78_DMA_SLOT_UART0_TX 0x24U
+#define MAX78_DMA_SLOT_UART1_TX 0x25U
+#define MAX78_DMA_SLOT_I2C0_TX  0x27U
+#define MAX78_DMA_SLOT_I2C1_TX  0x28U
+#define MAX78_DMA_SLOT_I2C2_TX  0x2AU
+#define MAX78_DMA_SLOT_CRC      0x2CU
+#define MAX78_DMA_SLOT_PCIF_TX  0x2DU
+#define MAX78_DMA_SLOT_UART2_TX 0x2EU
+#define MAX78_DMA_SLOT_SPI0_TX  0x2FU
+#define MAX78_DMA_SLOT_UART3_TX 0x3CU
+#define MAX78_DMA_SLOT_I2S_TX   0x3EU
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_MAX78000_DMA_H_ */
diff --git a/include/zephyr/dt-bindings/dma/renesas_rz_dma.h b/include/zephyr/dt-bindings/dma/renesas_rz_dma.h
new file mode 100644
index 00000000000..a21506f9bb5
--- /dev/null
+++ b/include/zephyr/dt-bindings/dma/renesas_rz_dma.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_RENESAS_RZ_DMA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_RENESAS_RZ_DMA_H_
+
+/* mode:                bit 0 (0: Normal, 1: Block) */
+/* source data size:    bit 1, 2, 3 (0b000 -> 0b111) */
+/* dest data size:      bit 4, 5, 6 (0b000 -> 0b111) */
+/* source addr mode:    bit 7 (0: incremented, 1: fixed) */
+/* dest addr mode:      bit 8 (0: incremented, 1: fixed) */
+
+#define RZ_DMA_MODE_NORMAL (0U)
+#define RZ_DMA_MODE_BLOCK  (1U)
+
+/* DMA source data size config on bits 1, 2, 3 */
+#define RZ_DMA_CFG_SRC_DATA_SIZE(val) ((val & 0x7) << 1)
+#define RZ_DMA_SRC_1_BYTE             RZ_DMA_CFG_SRC_DATA_SIZE(0)
+#define RZ_DMA_SRC_2_BYTE             RZ_DMA_CFG_SRC_DATA_SIZE(1)
+#define RZ_DMA_SRC_4_BYTE             RZ_DMA_CFG_SRC_DATA_SIZE(2)
+#define RZ_DMA_SRC_8_BYTE             RZ_DMA_CFG_SRC_DATA_SIZE(3)
+#define RZ_DMA_SRC_16_BYTE            RZ_DMA_CFG_SRC_DATA_SIZE(4)
+#define RZ_DMA_SRC_32_BYTE            RZ_DMA_CFG_SRC_DATA_SIZE(5)
+#define RZ_DMA_SRC_64_BYTE            RZ_DMA_CFG_SRC_DATA_SIZE(6)
+#define RZ_DMA_SRC_128_BYTE           RZ_DMA_CFG_SRC_DATA_SIZE(7)
+
+/* DMA destination data size config on bits 4, 5, 6 */
+#define RZ_DMA_CFG_DEST_DATA_SIZE(val) ((val & 0x7) << 4)
+#define RZ_DMA_DEST_1_BYTE             RZ_DMA_CFG_DEST_DATA_SIZE(0)
+#define RZ_DMA_DEST_2_BYTE             RZ_DMA_CFG_DEST_DATA_SIZE(1)
+#define RZ_DMA_DEST_4_BYTE             RZ_DMA_CFG_DEST_DATA_SIZE(2)
+#define RZ_DMA_DEST_8_BYTE             RZ_DMA_CFG_DEST_DATA_SIZE(3)
+#define RZ_DMA_DEST_16_BYTE            RZ_DMA_CFG_DEST_DATA_SIZE(4)
+#define RZ_DMA_DEST_32_BYTE            RZ_DMA_CFG_DEST_DATA_SIZE(5)
+#define RZ_DMA_DEST_64_BYTE            RZ_DMA_CFG_DEST_DATA_SIZE(6)
+#define RZ_DMA_DEST_128_BYTE           RZ_DMA_CFG_DEST_DATA_SIZE(7)
+
+/* DMA source address mode config on bit 7 */
+#define RZ_DMA_CFG_SRC_ADDR_MODE(val) ((val & 0x1) << 7)
+#define RZ_DMA_SRC_INCREMENTED        RZ_DMA_CFG_SRC_ADDR_MODE(0)
+#define RZ_DMA_SRC_FIXED              RZ_DMA_CFG_SRC_ADDR_MODE(1)
+
+/* DMA source address mode config on bit 8 */
+#define RZ_DMA_CFG_DEST_ADDR_MODE(val) ((val & 0x1) << 8)
+#define RZ_DMA_DEST_INCREMENTED        RZ_DMA_CFG_DEST_ADDR_MODE(0)
+#define RZ_DMA_DEST_FIXED              RZ_DMA_CFG_DEST_ADDR_MODE(1)
+
+/* DMA usual combination for peripheral transfer */
+#define RZ_DMA_MEM_TO_PERIPH                                                                       \
+	(RZ_DMA_MODE_NORMAL | RZ_DMA_SRC_INCREMENTED | RZ_DMA_DEST_FIXED | RZ_DMA_SRC_1_BYTE |     \
+	 RZ_DMA_DEST_1_BYTE)
+#define RZ_DMA_PERIPH_TO_MEM                                                                       \
+	(RZ_DMA_MODE_NORMAL | RZ_DMA_SRC_FIXED | RZ_DMA_DEST_INCREMENTED | RZ_DMA_SRC_1_BYTE |     \
+	 RZ_DMA_DEST_1_BYTE)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_RENESAS_RZ_DMA_H_ */
diff --git a/include/zephyr/dt-bindings/dma/silabs/common-dma.h b/include/zephyr/dt-bindings/dma/silabs/common-dma.h
new file mode 100644
index 00000000000..ac4c7b75f13
--- /dev/null
+++ b/include/zephyr/dt-bindings/dma/silabs/common-dma.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_DMA_SILABS_COMMON_DMA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_DMA_SILABS_COMMON_DMA_H_
+
+#define DMA_SRC_MASK 0x1F0000
+#define DMA_SIG_MASK 0x7
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_DMA_SILABS_COMMON_DMA_H_ */
diff --git a/include/zephyr/dt-bindings/dma/silabs/xg21-dma.h b/include/zephyr/dt-bindings/dma/silabs/xg21-dma.h
new file mode 100644
index 00000000000..a1077a9594a
--- /dev/null
+++ b/include/zephyr/dt-bindings/dma/silabs/xg21-dma.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_XG21_DMA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_XG21_DMA_H_
+
+#include <zephyr/dt-bindings/dt-util.h>
+#include "common-dma.h"
+
+/**
+ *  Definition of Silabs LDMA request signal
+ */
+#define DMA_REQSEL_NONE               (FIELD_PREP(DMA_SRC_MASK, 0) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_LDMAXBARPRSREQ0    (FIELD_PREP(DMA_SRC_MASK, 1) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_LDMAXBARPRSREQ1    (FIELD_PREP(DMA_SRC_MASK, 1) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER0CC0          (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER0CC1          (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER0CC2          (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER0UFOF         (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_TIMER1CC0          (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER1CC1          (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER1CC2          (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER1UFOF         (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_USART0RXDATAV      (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_USART0RXDATAVRIGHT (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_USART0TXBL         (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_USART0TXBLRIGHT    (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_USART0TXEMPTY      (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 4))
+#define DMA_REQSEL_USART1RXDATAV      (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_USART1RXDATAVRIGHT (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_USART1TXBL         (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_USART1TXBLRIGHT    (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_USART1TXEMPTY      (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 4))
+#define DMA_REQSEL_USART2RXDATAV      (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_USART2RXDATAVRIGHT (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_USART2TXBL         (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_USART2TXBLRIGHT    (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_USART2TXEMPTY      (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 4))
+#define DMA_REQSEL_I2C0RXDATAV        (FIELD_PREP(DMA_SRC_MASK, 7) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_I2C0TXBL           (FIELD_PREP(DMA_SRC_MASK, 7) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_I2C1RXDATAV        (FIELD_PREP(DMA_SRC_MASK, 8) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_I2C1TXBL           (FIELD_PREP(DMA_SRC_MASK, 8) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_IADC0IADC_SCAN     (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_IADC0IADC_SINGLE   (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_MSCWDATA           (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER2CC0          (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER2CC1          (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER2CC2          (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER2UFOF         (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_TIMER3CC0          (FIELD_PREP(DMA_SRC_MASK, 15) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER3CC1          (FIELD_PREP(DMA_SRC_MASK, 15) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER3CC2          (FIELD_PREP(DMA_SRC_MASK, 15) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER3UFOF         (FIELD_PREP(DMA_SRC_MASK, 15) | FIELD_PREP(DMA_SIG_MASK, 3))
+
+#endif ZEPHYR_INCLUDE_DT_BINDINGS_XG21_DMA_H_
diff --git a/include/zephyr/dt-bindings/dma/silabs/xg22-dma.h b/include/zephyr/dt-bindings/dma/silabs/xg22-dma.h
new file mode 100644
index 00000000000..8cba1cc20aa
--- /dev/null
+++ b/include/zephyr/dt-bindings/dma/silabs/xg22-dma.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_XG22_DMA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_XG22_DMA_H_
+
+#include <zephyr/dt-bindings/dt-util.h>
+#include "common-dma.h"
+
+/**
+ *  Definition of Silabs LDMA request signal
+ */
+#define DMA_REQSEL_NONE               (FIELD_PREP(DMA_SRC_MASK, 0) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_LDMAXBARPRSREQ0    (FIELD_PREP(DMA_SRC_MASK, 1) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_LDMAXBARPRSREQ1    (FIELD_PREP(DMA_SRC_MASK, 1) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER0CC0          (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER0CC1          (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER0CC2          (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER0UFOF         (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_TIMER1CC0          (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER1CC1          (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER1CC2          (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER1UFOF         (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_USART0RXDATAV      (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_USART0RXDATAVRIGHT (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_USART0TXBL         (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_USART0TXBLRIGHT    (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_USART0TXEMPTY      (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 4))
+#define DMA_REQSEL_USART1RXDATAV      (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_USART1RXDATAVRIGHT (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_USART1TXBL         (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_USART1TXBLRIGHT    (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_USART1TXEMPTY      (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 4))
+#define DMA_REQSEL_I2C0RXDATAV        (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_I2C0TXBL           (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_I2C1RXDATAV        (FIELD_PREP(DMA_SRC_MASK, 7) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_I2C1TXBL           (FIELD_PREP(DMA_SRC_MASK, 7) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_IADC0IADC_SCAN     (FIELD_PREP(DMA_SRC_MASK, 11) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_IADC0IADC_SINGLE   (FIELD_PREP(DMA_SRC_MASK, 11) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_MSCWDATA           (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER2CC0          (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER2CC1          (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER2CC2          (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER2UFOF         (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_TIMER3CC0          (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER3CC1          (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER3CC2          (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER3UFOF         (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_PDMRXDATAV         (FIELD_PREP(DMA_SRC_MASK, 15) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_EUART0RXFL         (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_EUART0TXFL         (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER4CC0          (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER4CC1          (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER4CC2          (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER4UFOF         (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 3))
+
+#endif ZEPHYR_INCLUDE_DT_BINDINGS_XG22_DMA_H_
diff --git a/include/zephyr/dt-bindings/dma/silabs/xg23-dma.h b/include/zephyr/dt-bindings/dma/silabs/xg23-dma.h
new file mode 100644
index 00000000000..b3e04176147
--- /dev/null
+++ b/include/zephyr/dt-bindings/dma/silabs/xg23-dma.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_XG23_DMA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_XG23_DMA_H_
+
+#include <zephyr/dt-bindings/dt-util.h>
+#include "common-dma.h"
+
+/**
+ *  Definition of Silabs LDMA request signal
+ */
+#define DMA_REQSEL_NONE               (FIELD_PREP(DMA_SRC_MASK, 0) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_LDMAXBARPRSREQ0    (FIELD_PREP(DMA_SRC_MASK, 1) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_LDMAXBARPRSREQ1    (FIELD_PREP(DMA_SRC_MASK, 1) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER0CC0          (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER0CC1          (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER0CC2          (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER0UFOF         (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_TIMER1CC0          (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER1CC1          (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER1CC2          (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER1UFOF         (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_USART0RXDATAV      (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_USART0RXDATAVRIGHT (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_USART0TXBL         (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_USART0TXBLRIGHT    (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_USART0TXEMPTY      (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 4))
+#define DMA_REQSEL_I2C0RXDATAV        (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_I2C0TXBL           (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_I2C1RXDATAV        (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_I2C1TXBL           (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_IADC0IADC_SCAN     (FIELD_PREP(DMA_SRC_MASK, 10) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_IADC0IADC_SINGLE   (FIELD_PREP(DMA_SRC_MASK, 10) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_MSCWDATA           (FIELD_PREP(DMA_SRC_MASK, 11) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER2CC0          (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER2CC1          (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER2CC2          (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER2UFOF         (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_TIMER3CC0          (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER3CC1          (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER3CC2          (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER3UFOF         (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_TIMER4CC0          (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER4CC1          (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER4CC2          (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER4UFOF         (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_VDAC0CH0_REQ       (FIELD_PREP(DMA_SRC_MASK, 15) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_VDAC0CH1_REQ       (FIELD_PREP(DMA_SRC_MASK, 15) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_EUSART0RXFL        (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_EUSART0TXFL        (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_EUSART1RXFL        (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_EUSART1TXFL        (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_EUSART2RXFL        (FIELD_PREP(DMA_SRC_MASK, 18) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_EUSART2TXFL        (FIELD_PREP(DMA_SRC_MASK, 18) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_LESENSEFIFO        (FIELD_PREP(DMA_SRC_MASK, 19) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_LCD                (FIELD_PREP(DMA_SRC_MASK, 20) | FIELD_PREP(DMA_SIG_MASK, 0))
+
+#endif ZEPHYR_INCLUDE_DT_BINDINGS_XG23_DMA_H_
diff --git a/include/zephyr/dt-bindings/dma/silabs/xg24-dma.h b/include/zephyr/dt-bindings/dma/silabs/xg24-dma.h
new file mode 100644
index 00000000000..a4067f79711
--- /dev/null
+++ b/include/zephyr/dt-bindings/dma/silabs/xg24-dma.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_XG24_DMA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_XG24_DMA_H_
+
+#include <zephyr/dt-bindings/dt-util.h>
+#include "common-dma.h"
+
+/**
+ *  Definition of Silabs LDMA request signal
+ */
+#define DMA_REQSEL_NONE               (FIELD_PREP(DMA_SRC_MASK, 0) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_LDMAXBARPRSREQ0    (FIELD_PREP(DMA_SRC_MASK, 1) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_LDMAXBARPRSREQ1    (FIELD_PREP(DMA_SRC_MASK, 1) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER0CC0          (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER0CC1          (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER0CC2          (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER0UFOF         (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_TIMER1CC0          (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER1CC1          (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER1CC2          (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER1UFOF         (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_USART0RXDATAV      (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_USART0RXDATAVRIGHT (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_USART0TXBL         (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_USART0TXBLRIGHT    (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_USART0TXEMPTY      (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 4))
+#define DMA_REQSEL_I2C0RXDATAV        (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_I2C0TXBL           (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_I2C1RXDATAV        (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_I2C1TXBL           (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_IADC0IADC_SCAN     (FIELD_PREP(DMA_SRC_MASK, 10) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_IADC0IADC_SINGLE   (FIELD_PREP(DMA_SRC_MASK, 10) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_MSCWDATA           (FIELD_PREP(DMA_SRC_MASK, 11) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER2CC0          (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER2CC1          (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER2CC2          (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER2UFOF         (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_TIMER3CC0          (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER3CC1          (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER3CC2          (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER3UFOF         (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_TIMER4CC0          (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER4CC1          (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER4CC2          (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER4UFOF         (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_EUSART0RXFL        (FIELD_PREP(DMA_SRC_MASK, 15) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_EUSART0TXFL        (FIELD_PREP(DMA_SRC_MASK, 15) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_EUSART1RXFL        (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_EUSART1TXFL        (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_VDAC0CH0_REQ       (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_VDAC0CH1_REQ       (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_VDAC1CH0_REQ       (FIELD_PREP(DMA_SRC_MASK, 18) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_VDAC1CH1_REQ       (FIELD_PREP(DMA_SRC_MASK, 18) | FIELD_PREP(DMA_SIG_MASK, 1))
+
+#endif ZEPHYR_INCLUDE_DT_BINDINGS_XG24_DMA_H_
diff --git a/include/zephyr/dt-bindings/dma/silabs/xg27-dma.h b/include/zephyr/dt-bindings/dma/silabs/xg27-dma.h
new file mode 100644
index 00000000000..1da99664edf
--- /dev/null
+++ b/include/zephyr/dt-bindings/dma/silabs/xg27-dma.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_XG27_DMA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_XG27_DMA_H_
+
+#include <zephyr/dt-bindings/dt-util.h>
+#include "common-dma.h"
+
+/**
+ *  Definition of Silabs LDMA request signal
+ */
+#define DMA_REQSEL_NONE               (FIELD_PREP(DMA_SRC_MASK, 0) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_LDMAXBARPRSREQ0    (FIELD_PREP(DMA_SRC_MASK, 1) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_LDMAXBARPRSREQ1    (FIELD_PREP(DMA_SRC_MASK, 1) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER0CC0          (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER0CC1          (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER0CC2          (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER0UFOF         (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_TIMER1CC0          (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER1CC1          (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER1CC2          (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER1UFOF         (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_USART0RXDATAV      (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_USART0RXDATAVRIGHT (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_USART0TXBL         (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_USART0TXBLRIGHT    (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_USART0TXEMPTY      (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 4))
+#define DMA_REQSEL_USART1RXDATAV      (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_USART1RXDATAVRIGHT (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_USART1TXBL         (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_USART1TXBLRIGHT    (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_USART1TXEMPTY      (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 4))
+#define DMA_REQSEL_I2C0RXDATAV        (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_I2C0TXBL           (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_I2C1RXDATAV        (FIELD_PREP(DMA_SRC_MASK, 7) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_I2C1TXBL           (FIELD_PREP(DMA_SRC_MASK, 7) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_IADC0IADC_SCAN     (FIELD_PREP(DMA_SRC_MASK, 11) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_IADC0IADC_SINGLE   (FIELD_PREP(DMA_SRC_MASK, 11) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_MSCWDATA           (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER2CC0          (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER2CC1          (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER2CC2          (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER2UFOF         (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_TIMER3CC0          (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER3CC1          (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER3CC2          (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER3UFOF         (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_PDMRXDATAV         (FIELD_PREP(DMA_SRC_MASK, 15) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER4CC0          (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER4CC1          (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER4CC2          (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER4UFOF         (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_EUSART0RXFL        (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_EUSART0TXFL        (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 1))
+
+#endif ZEPHYR_INCLUDE_DT_BINDINGS_XG27_DMA_H_
diff --git a/include/zephyr/dt-bindings/dma/silabs/xg29-dma.h b/include/zephyr/dt-bindings/dma/silabs/xg29-dma.h
new file mode 100644
index 00000000000..2622b211ca5
--- /dev/null
+++ b/include/zephyr/dt-bindings/dma/silabs/xg29-dma.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_XG29_DMA_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_XG29_DMA_H_
+
+#include <zephyr/dt-bindings/dt-util.h>
+#include "common-dma.h"
+
+/**
+ *  Definition of Silabs LDMA request signal
+ */
+#define DMA_REQSEL_NONE               (FIELD_PREP(DMA_SRC_MASK, 0) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_LDMAXBARPRSREQ0    (FIELD_PREP(DMA_SRC_MASK, 1) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_LDMAXBARPRSREQ1    (FIELD_PREP(DMA_SRC_MASK, 1) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER0CC0          (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER0CC1          (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER0CC2          (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER0UFOF         (FIELD_PREP(DMA_SRC_MASK, 2) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_TIMER1CC0          (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER1CC1          (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER1CC2          (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER1UFOF         (FIELD_PREP(DMA_SRC_MASK, 3) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_USART0RXDATAV      (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_USART0RXDATAVRIGHT (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_USART0TXBL         (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_USART0TXBLRIGHT    (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_USART0TXEMPTY      (FIELD_PREP(DMA_SRC_MASK, 4) | FIELD_PREP(DMA_SIG_MASK, 4))
+#define DMA_REQSEL_USART1RXDATAV      (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_USART1RXDATAVRIGHT (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_USART1TXBL         (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_USART1TXBLRIGHT    (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_USART1TXEMPTY      (FIELD_PREP(DMA_SRC_MASK, 5) | FIELD_PREP(DMA_SIG_MASK, 4))
+#define DMA_REQSEL_I2C0RXDATAV        (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_I2C0TXBL           (FIELD_PREP(DMA_SRC_MASK, 6) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_I2C1RXDATAV        (FIELD_PREP(DMA_SRC_MASK, 7) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_I2C1TXBL           (FIELD_PREP(DMA_SRC_MASK, 7) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_IADC0IADC_SCAN     (FIELD_PREP(DMA_SRC_MASK, 11) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_IADC0IADC_SINGLE   (FIELD_PREP(DMA_SRC_MASK, 11) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_MSCWDATA           (FIELD_PREP(DMA_SRC_MASK, 12) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER2CC0          (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER2CC1          (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER2CC2          (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER2UFOF         (FIELD_PREP(DMA_SRC_MASK, 13) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_TIMER3CC0          (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER3CC1          (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER3CC2          (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER3UFOF         (FIELD_PREP(DMA_SRC_MASK, 14) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_PDMRXDATAV         (FIELD_PREP(DMA_SRC_MASK, 15) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER4CC0          (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_TIMER4CC1          (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_TIMER4CC2          (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 2))
+#define DMA_REQSEL_TIMER4UFOF         (FIELD_PREP(DMA_SRC_MASK, 16) | FIELD_PREP(DMA_SIG_MASK, 3))
+#define DMA_REQSEL_EUSART0RXFL        (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_EUSART0TXFL        (FIELD_PREP(DMA_SRC_MASK, 17) | FIELD_PREP(DMA_SIG_MASK, 1))
+#define DMA_REQSEL_EUSART1RXFL        (FIELD_PREP(DMA_SRC_MASK, 18) | FIELD_PREP(DMA_SIG_MASK, 0))
+#define DMA_REQSEL_EUSART1TXFL        (FIELD_PREP(DMA_SRC_MASK, 18) | FIELD_PREP(DMA_SIG_MASK, 1))
+
+#endif ZEPHYR_INCLUDE_DT_BINDINGS_XG29_DMA_H_
diff --git a/include/zephyr/dt-bindings/gpio/arduino-header-r3.h b/include/zephyr/dt-bindings/gpio/arduino-header-r3.h
new file mode 100644
index 00000000000..d54913ba9af
--- /dev/null
+++ b/include/zephyr/dt-bindings/gpio/arduino-header-r3.h
@@ -0,0 +1,33 @@
+/**
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ARDUINO_HEADER_R3_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ARDUINO_HEADER_R3_H_
+
+#define ARDUINO_HEADER_R3_A0  0
+#define ARDUINO_HEADER_R3_A1  1
+#define ARDUINO_HEADER_R3_A2  2
+#define ARDUINO_HEADER_R3_A3  3
+#define ARDUINO_HEADER_R3_A4  4
+#define ARDUINO_HEADER_R3_A5  5
+#define ARDUINO_HEADER_R3_D0  6
+#define ARDUINO_HEADER_R3_D1  7
+#define ARDUINO_HEADER_R3_D2  8
+#define ARDUINO_HEADER_R3_D3  9
+#define ARDUINO_HEADER_R3_D4  10
+#define ARDUINO_HEADER_R3_D5  11
+#define ARDUINO_HEADER_R3_D6  12
+#define ARDUINO_HEADER_R3_D7  13
+#define ARDUINO_HEADER_R3_D8  14
+#define ARDUINO_HEADER_R3_D9  15
+#define ARDUINO_HEADER_R3_D10 16
+#define ARDUINO_HEADER_R3_D11 17
+#define ARDUINO_HEADER_R3_D12 18
+#define ARDUINO_HEADER_R3_D13 19
+#define ARDUINO_HEADER_R3_D14 20
+#define ARDUINO_HEADER_R3_D15 21
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ARDUINO_HEADER_R3_H_ */
diff --git a/include/zephyr/dt-bindings/gpio/ene-kb1200-gpio.h b/include/zephyr/dt-bindings/gpio/ene-kb1200-gpio.h
new file mode 100644
index 00000000000..f6ca127081f
--- /dev/null
+++ b/include/zephyr/dt-bindings/gpio/ene-kb1200-gpio.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2024 ENE Technology Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ENE_KB1200_GPIO_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ENE_KB1200_GPIO_H_
+
+/**
+ * @name GPIO pin voltage flags
+ *
+ * The voltage and driving flags are a Zephyr specific extension of the standard GPIO flags
+ * specified by the Linux GPIO binding for use with the ENE KB1200 SoC.
+ *
+ * @{
+ *  Note: Bits 15 down to 8 are reserved for SoC specific flags.
+ */
+
+/** @cond INTERNAL_HIDDEN */
+#define KB1200_GPIO_VOLTAGE_POS         8
+#define KB1200_GPIO_VOLTAGE_MASK        (1U << KB1200_GPIO_VOLTAGE_POS)
+
+#define KB1200_GPIO_DRIVING_POS         9
+#define KB1200_GPIO_DRIVING_MASK        (1U << KB1200_GPIO_DRIVING_POS)
+/** @endcond */
+
+/** Set pin at the default voltage level (3.3V) */
+#define KB1200_GPIO_VOLTAGE_DEFAULT     (0U << KB1200_GPIO_VOLTAGE_POS)
+/** Set pin voltage level at 1.8 V */
+#define KB1200_GPIO_VOLTAGE_1P8	        (1U << KB1200_GPIO_VOLTAGE_POS)
+
+/** Set pin at the default driving current (4mA) */
+#define KB1200_GPIO_DRIVING_DEFAULT     (0U << KB1200_GPIO_DRIVING_POS)
+/** Set pin driving current at 16mA */
+#define KB1200_GPIO_DRIVING_16MA        (1U << KB1200_GPIO_DRIVING_POS)
+
+
+/** @} */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_ENE_KB1200_GPIO_H_ */
diff --git a/include/zephyr/dt-bindings/gpio/nxp-imx-igpio.h b/include/zephyr/dt-bindings/gpio/nxp-imx-igpio.h
new file mode 100644
index 00000000000..29eebc1451b
--- /dev/null
+++ b/include/zephyr/dt-bindings/gpio/nxp-imx-igpio.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2025 Feniex Industries Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NXP_IMX_IGPIO_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NXP_IMX_IGPIO_H_
+
+/**
+ * @name GPIO pull strength flags
+ *
+ * The pull strength flags are a Zephyr specific extension of the standard GPIO
+ * flags specified by the Linux GPIO binding. Only applicable for NXP IMX
+ * SoCs.
+ *
+ * The interface supports two different pull strengths:
+ * `WEAK` - The lowest pull strength supported by the HW
+ * `STRONG` - The highest pull strength supported by the HW
+ *
+ * @{
+ */
+/** @cond INTERNAL_HIDDEN */
+#define NXP_IGPIO_PULL_STRENGTH_POS 8
+#define NXP_IGPIO_PULL_STRENGTH_MASK (0x1U << NXP_IGPIO_PULL_STRENGTH_POS)
+/** @endcond */
+
+/** pull up/down strengths (only applies to CONFIG_SOC_SERIES_IMXRT10XX) */
+#define NXP_IGPIO_PULL_WEAK (0x0U << NXP_IGPIO_PULL_STRENGTH_POS)
+#define NXP_IGPIO_PULL_STRONG (0x1U << NXP_IGPIO_PULL_STRENGTH_POS)
+
+/** @} */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_NXP_IMX_IGPIO_H_ */
diff --git a/include/zephyr/dt-bindings/gpio/renesas-rz-gpio.h b/include/zephyr/dt-bindings/gpio/renesas-rz-gpio.h
index 30729af98bd..d78aa1c8225 100644
--- a/include/zephyr/dt-bindings/gpio/renesas-rz-gpio.h
+++ b/include/zephyr/dt-bindings/gpio/renesas-rz-gpio.h
@@ -1,42 +1,42 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZ_GPIO_H_
 #define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZ_GPIO_H_
 
-/*********************************RZG3S*****************************************/
+/*********************************RZ/A,G,V**************************************/
 
 /**
- * @brief RZ G3S specific GPIO Flags
+ * @brief RZ/A,G,V-specific GPIO Flags
  * The pin driving ability flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
  * follows:
- * - Bit 9..8: Pin driving ability value
- * - Bit 11..10: Digital Noise Filter Clock Selection value
- * - Bit 13..12: Digital Noise Filter Number value
- * - Bit 14: Digital Noise Filter ON/OFF
+ * - Bit 8..9: Pin driving ability value
+ * - Bit 10: Digital Noise Filter ON/OFF
+ * - Bit 11..12: Digital Noise Filter Number value
+ * - Bit 13..14: Digital Noise Filter Clock Selection value
  * example:
  * gpio-consumer {
- *	out-gpios = <&port8 2 (GPIO_PULL_UP | RZG3S_GPIO_FILTER_SET(1, 3, 3))>;
+ *	out-gpios = <&port8 2 (GPIO_PULL_UP | RZ_GPIO_FILTER_SET(1, 3, 3))>;
  * };
  * gpio-consumer {
- *	out-gpios = <&port8 2 (GPIO_PULL_UP | RZG3S_GPIO_IOLH_SET(2))>;
+ *	out-gpios = <&port8 2 (GPIO_PULL_UP | RZ_GPIO_IOLH_SET(2))>;
  * };
  */
 
 /* GPIO drive IOLH */
-#define RZG3S_GPIO_IOLH_SHIFT         7U
-#define RZG3S_GPIO_IOLH_SET(iolh_val) (iolh_val << RZG3S_GPIO_IOLH_SHIFT)
+#define RZ_GPIO_IOLH_SHIFT         8U
+#define RZ_GPIO_IOLH_SET(iolh_val) (iolh_val << RZ_GPIO_IOLH_SHIFT)
 
 /* GPIO filter */
-#define RZG3S_GPIO_FILTER_SHIFT    9U
-#define RZG3S_GPIO_FILNUM_SHIFT    1U
-#define RZG3S_GPIO_FILCLKSEL_SHIFT 3U
-#define RZG3S_GPIO_FILTER_SET(fillonoff, filnum, filclksel)                                        \
-	(((fillonoff) | ((filnum) << RZG3S_GPIO_FILNUM_SHIFT) |                                    \
-	  ((filclksel) << RZG3S_GPIO_FILCLKSEL_SHIFT))                                             \
-	 << RZG3S_GPIO_FILTER_SHIFT)
+#define RZ_GPIO_FILTER_SHIFT    10U
+#define RZ_GPIO_FILNUM_SHIFT    1U
+#define RZ_GPIO_FILCLKSEL_SHIFT 3U
+#define RZ_GPIO_FILTER_SET(fillonoff, filnum, filclksel)                                           \
+	(((fillonoff) | ((filnum) << RZ_GPIO_FILNUM_SHIFT) |                                       \
+	  ((filclksel) << RZ_GPIO_FILCLKSEL_SHIFT))                                                \
+	 << RZ_GPIO_FILTER_SHIFT)
 
 /*******************************************************************************/
 
diff --git a/include/zephyr/dt-bindings/gpio/renesas-rza2m-gpio.h b/include/zephyr/dt-bindings/gpio/renesas-rza2m-gpio.h
new file mode 100644
index 00000000000..e8ba24fd38e
--- /dev/null
+++ b/include/zephyr/dt-bindings/gpio/renesas-rza2m-gpio.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZA2M_GPIO_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZA2M_GPIO_H_
+
+/**
+ * @brief RZ/A2M specific GPIO Flags
+ *
+ * The drive flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
+ * follows:
+ *
+ * - Bit 8: Drive strength
+ */
+
+/** Normal drive */
+#define RZA2M_GPIO_DRIVE_NORMAL (0U << 8U)
+/** High drive */
+#define RZA2M_GPIO_DRIVE_HIGH   (1U << 8U)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZA2M_GPIO_H_ */
diff --git a/include/zephyr/dt-bindings/gpio/renesas-rztn-gpio.h b/include/zephyr/dt-bindings/gpio/renesas-rztn-gpio.h
new file mode 100644
index 00000000000..22d4d3ea301
--- /dev/null
+++ b/include/zephyr/dt-bindings/gpio/renesas-rztn-gpio.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZTN_GPIO_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZTN_GPIO_H_
+
+/*********************************RZTN*****************************************/
+
+/**
+ * @brief RZTN specific GPIO Flags
+ * The pin driving ability flags are encoded in the 8 upper bits of @ref gpio_dt_flags_t as
+ * follows:
+ * - Bit 9..8: Driving ability control
+ * - Bit 12: Schmitt trigger control
+ * - Bit 13: Slew rate control
+ * Example:
+ * Driving ability control: Middle
+ * Schmitt trigger control: Enabled
+ * Slew rate control: Slow
+ * gpio-consumer {
+ *	out-gpios = <&port8 2 (GPIO_PULL_UP | RZTN_GPIO_CFG_SET(1, 1, 0))>;
+ * };
+ */
+
+/* GPIO DRCTL register */
+#define RZTN_GPIO_DRCTL_SHIFT        8U
+#define RZTN_GPIO_SCHMITT_TRIG_SHIFT 4U
+#define RZTN_GPIO_SLEW_RATE_SHIFT    5U
+#define RZTN_GPIO_DRCTL_SET(drive_ability, schmitt_trig, slew_rate)                                \
+	(((drive_ability) | ((schmitt_trig) << RZTN_GPIO_SCHMITT_TRIG_SHIFT) |                     \
+	  ((slew_rate) << RZTN_GPIO_SLEW_RATE_SHIFT))                                              \
+	 << RZTN_GPIO_DRCTL_SHIFT)
+
+/*******************************************************************************/
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_GPIO_RENESAS_RZTN_GPIO_H_ */
diff --git a/include/zephyr/dt-bindings/gpio/stm32-gpio.h b/include/zephyr/dt-bindings/gpio/stm32-gpio.h
index f9a3a4b60af..3a31bbc60e0 100644
--- a/include/zephyr/dt-bindings/gpio/stm32-gpio.h
+++ b/include/zephyr/dt-bindings/gpio/stm32-gpio.h
@@ -14,6 +14,7 @@
  * follows:
  *
  * - Bit 8: Configure a GPIO pin to power on the system after Poweroff.
+ * - Bit 10..9: Configure the output speed of a GPIO pin.
  *
  * @ingroup gpio_interface
  * @{
@@ -24,7 +25,24 @@
  * This flag is reserved to GPIO pins that are associated with wake-up pins
  * in STM32 PWR devicetree node, through the property "wkup-gpios".
  */
-#define STM32_GPIO_WKUP		(1 << 8)
+#define STM32_GPIO_WKUP (1 << 8)
+
+/** @cond INTERNAL_HIDDEN */
+#define STM32_GPIO_SPEED_SHIFT 9
+#define STM32_GPIO_SPEED_MASK  0x3
+/** @endcond */
+
+/** Configure the GPIO pin output speed to be low */
+#define STM32_GPIO_LOW_SPEED (0x0 << STM32_GPIO_SPEED_SHIFT)
+
+/** Configure the GPIO pin output speed to be medium */
+#define STM32_GPIO_MEDIUM_SPEED (0x1 << STM32_GPIO_SPEED_SHIFT)
+
+/** Configure the GPIO pin output speed to be high */
+#define STM32_GPIO_HIGH_SPEED (0x2 << STM32_GPIO_SPEED_SHIFT)
+
+/** Configure the GPIO pin output speed to be very high */
+#define STM32_GPIO_VERY_HIGH_SPEED (0x3 << STM32_GPIO_SPEED_SHIFT)
 
 /** @} */
 
diff --git a/include/zephyr/dt-bindings/i2c/npcx-i2c.h b/include/zephyr/dt-bindings/i2c/npcx-i2c.h
new file mode 100644
index 00000000000..fc46fbf55fd
--- /dev/null
+++ b/include/zephyr/dt-bindings/i2c/npcx-i2c.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_I2C_NPCX_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_I2C_NPCX_H_
+
+
+#define NPCX_I2C_CTRL_PORT(ctrl, port) (((ctrl & 0xf) << 4) | (port & 0xf))
+
+#endif	/* ZEPHYR_INCLUDE_DT_BINDINGS_I2C_NPCX_H_ */
diff --git a/include/zephyr/dt-bindings/input/stm32-tsc-defines.h b/include/zephyr/dt-bindings/input/stm32-tsc-defines.h
new file mode 100644
index 00000000000..5153e985c95
--- /dev/null
+++ b/include/zephyr/dt-bindings/input/stm32-tsc-defines.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 Arif Balik <arifbalik@outlook.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_STM32_TSC_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_STM32_TSC_H_
+
+#define TSC_IO1 0x1UL
+#define TSC_IO2 0x2UL
+#define TSC_IO3 0x4UL
+#define TSC_IO4 0x8UL
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_STM32_TSC_H_ */
diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h
index 5f4cd793f18..cf0e9c5eee5 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c2-intmux.h
@@ -51,11 +51,8 @@
 #define CORE0_PIF_PMS_SIZE_INTR_SOURCE         41
 #define CACHE_CORE0_ACS_INTR_SOURCE            42
 
-/* RISC-V supports priority values from 1 (lowest) to 15.
- * As interrupt controller for Xtensa and RISC-V is shared, this is
- * set to an intermediate and compatible value.
- */
-#define IRQ_DEFAULT_PRIORITY	3
+/* Zero will allocate low/medium levels of priority (ESP_INTR_FLAG_LOWMED) */
+#define IRQ_DEFAULT_PRIORITY	0
 
 #define ESP_INTR_FLAG_SHARED	(1<<8)	/* Interrupt can be shared between ISRs */
 
diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h
index f6059000505..4f4df11455d 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h
@@ -70,11 +70,8 @@
 #define BAK_PMS_VIOLATE_INTR_SOURCE         60
 #define CACHE_CORE0_ACS_INTR_SOURCE         61
 
-/* RISC-V supports priority values from 1 (lowest) to 15.
- * As interrupt controller for Xtensa and RISC-V is shared, this is
- * set to an intermediate and compatible value.
- */
-#define IRQ_DEFAULT_PRIORITY	3
+/* Zero will allocate low/medium levels of priority (ESP_INTR_FLAG_LOWMED) */
+#define IRQ_DEFAULT_PRIORITY	0
 
 #define ESP_INTR_FLAG_SHARED	(1<<8)	/* Interrupt can be shared between ISRs */
 
diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h
index 24b55504016..fc89526d7bd 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/esp-esp32c6-intmux.h
@@ -86,11 +86,8 @@
 #define ECC_INTR_SOURCE                    76  /* interrupt of ECC accelerator, level*/
 #define MAX_INTR_SOURCE                    77
 
-/* RISC-V supports priority values from 1 (lowest) to 15.
- * As interrupt controller for Xtensa and RISC-V is shared, this is
- * set to an intermediate and compatible value.
- */
-#define IRQ_DEFAULT_PRIORITY	3
+/* Zero will allocate low/medium levels of priority (ESP_INTR_FLAG_LOWMED) */
+#define IRQ_DEFAULT_PRIORITY	0
 
 #define ESP_INTR_FLAG_SHARED	(1<<8)	/* Interrupt can be shared between ISRs */
 
diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h
index 32194e69a48..4d644af20bb 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/esp-xtensa-intmux.h
@@ -79,9 +79,7 @@
 #define CACHE_IA_INTR_SOURCE                68  /* Cache Invalid Access, LEVEL */
 #define MAX_INTR_SOURCE                     69  /* total number of interrupt sources */
 
-/* For Xtensa architecture, zero will allocate low/medium
- * levels of priority (ESP_INTR_FLAG_LOWMED)
- */
+/* Zero will allocate low/medium levels of priority (ESP_INTR_FLAG_LOWMED) */
 #define IRQ_DEFAULT_PRIORITY	0
 
 #define ESP_INTR_FLAG_SHARED	(1<<8)	/* Interrupt can be shared between ISRs */
diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h
index 383f9a62306..34bb3429cbb 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h
@@ -106,9 +106,7 @@
 #define ICACHE_SYNC_INTR_SOURCE             94  /* instruction cache sync done, level */
 #define MAX_INTR_SOURCE                     95  /* total number of interrupt sources */
 
-/* For Xtensa architecture, zero will allocate low/medium
- * levels of priority (ESP_INTR_FLAG_LOWMED)
- */
+/* Zero will allocate low/medium levels of priority (ESP_INTR_FLAG_LOWMED) */
 #define IRQ_DEFAULT_PRIORITY	0
 
 #define ESP_INTR_FLAG_SHARED	(1<<8)	/* Interrupt can be shared between ISRs */
diff --git a/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h b/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h
index 87c690606f6..ae6f7760e58 100644
--- a/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h
+++ b/include/zephyr/dt-bindings/interrupt-controller/esp32s3-xtensa-intmux.h
@@ -104,9 +104,7 @@
 #define DMA_EXTMEM_REJECT_SOURCE              98
 #define MAX_INTR_SOURCE                       99 /* number of interrupt sources */
 
-/* For Xtensa architecture, zero will allocate low/medium
- * levels of priority (ESP_INTR_FLAG_LOWMED)
- */
+/* Zero will allocate low/medium levels of priority (ESP_INTR_FLAG_LOWMED) */
 #define IRQ_DEFAULT_PRIORITY	0
 
 #define ESP_INTR_FLAG_SHARED	(1<<8)	/* Interrupt can be shared between ISRs */
diff --git a/include/zephyr/dt-bindings/interrupt-controller/ite-it51xxx-intc.h b/include/zephyr/dt-bindings/interrupt-controller/ite-it51xxx-intc.h
new file mode 100644
index 00000000000..c6e2c7c8f78
--- /dev/null
+++ b/include/zephyr/dt-bindings/interrupt-controller/ite-it51xxx-intc.h
@@ -0,0 +1,186 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_
+
+#define IRQ_TYPE_NONE         0
+#define IRQ_TYPE_EDGE_RISING  1
+#define IRQ_TYPE_EDGE_FALLING 2
+#define IRQ_TYPE_EDGE_BOTH    (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)
+#define IRQ_TYPE_LEVEL_HIGH   4
+#define IRQ_TYPE_LEVEL_LOW    8
+
+/* IRQ numbers of WUC */
+/* Group 0 of INTC */
+#define IT51XXX_IRQ_WU20       1
+#define IT51XXX_IRQ_KBC_OBE    2
+#define IT51XXX_IRQ_SMB_D      4
+#define IT51XXX_IRQ_WKINTD     5
+#define IT51XXX_IRQ_WU23       6
+/* Group 1 */
+#define IT51XXX_IRQ_SMB_A      9
+#define IT51XXX_IRQ_SMB_B      10
+#define IT51XXX_IRQ_WU26       12
+#define IT51XXX_IRQ_WKINTC     13
+#define IT51XXX_IRQ_WU25       14
+/* Group 2 */
+#define IT51XXX_IRQ_SMB_C      16
+#define IT51XXX_IRQ_WU24       17
+#define IT51XXX_IRQ_WU22       21
+/* Group 3 */
+#define IT51XXX_IRQ_KBC_IBF    24
+#define IT51XXX_IRQ_PMC1_IBF   25
+#define IT51XXX_IRQ_PMC2_IBF   27
+#define IT51XXX_IRQ_TIMER1     30
+#define IT51XXX_IRQ_WU21       31
+/* Group 5 */
+#define IT51XXX_IRQ_WU50       40
+#define IT51XXX_IRQ_WU51       41
+#define IT51XXX_IRQ_WU52       42
+#define IT51XXX_IRQ_WU53       43
+#define IT51XXX_IRQ_WU54       44
+#define IT51XXX_IRQ_WU55       45
+#define IT51XXX_IRQ_WU56       46
+#define IT51XXX_IRQ_WU57       47
+/* Group 6 */
+#define IT51XXX_IRQ_WU60       48
+#define IT51XXX_IRQ_WU61       49
+#define IT51XXX_IRQ_WU62       50
+#define IT51XXX_IRQ_WU63       51
+#define IT51XXX_IRQ_WU64       52
+#define IT51XXX_IRQ_WU65       53
+#define IT51XXX_IRQ_WU66       54
+#define IT51XXX_IRQ_WU67       55
+/* Group 7 */
+#define IT51XXX_IRQ_TIMER2     58
+/* Group 9 */
+#define IT51XXX_IRQ_WU70       72
+#define IT51XXX_IRQ_WU71       73
+#define IT51XXX_IRQ_WU72       74
+#define IT51XXX_IRQ_WU73       75
+#define IT51XXX_IRQ_WU74       76
+#define IT51XXX_IRQ_WU75       77
+#define IT51XXX_IRQ_WU76       78
+#define IT51XXX_IRQ_WU77       79
+/* Group 10 */
+#define IT51XXX_IRQ_WU88       85
+#define IT51XXX_IRQ_WU89       86
+#define IT51XXX_IRQ_WU90       87
+/* Group 11 */
+#define IT51XXX_IRQ_WU80       88
+#define IT51XXX_IRQ_WU81       89
+#define IT51XXX_IRQ_WU82       90
+#define IT51XXX_IRQ_WU83       91
+#define IT51XXX_IRQ_WU84       92
+#define IT51XXX_IRQ_WU85       93
+#define IT51XXX_IRQ_WU86       94
+#define IT51XXX_IRQ_WU87       95
+/* Group 12 */
+#define IT51XXX_IRQ_WU91       96
+#define IT51XXX_IRQ_WU92       97
+#define IT51XXX_IRQ_WU93       98
+#define IT51XXX_IRQ_WU95       100
+#define IT51XXX_IRQ_WU96       101
+#define IT51XXX_IRQ_WU97       102
+#define IT51XXX_IRQ_WU98       103
+/* Group 13 */
+#define IT51XXX_IRQ_WU99       104
+#define IT51XXX_IRQ_WU100      105
+#define IT51XXX_IRQ_WU101      106
+#define IT51XXX_IRQ_WU102      107
+#define IT51XXX_IRQ_WU103      108
+#define IT51XXX_IRQ_WU104      109
+#define IT51XXX_IRQ_WU105      110
+#define IT51XXX_IRQ_WU106      111
+/* Group 14 */
+#define IT51XXX_IRQ_WU107      112
+#define IT51XXX_IRQ_WU108      113
+#define IT51XXX_IRQ_WU109      114
+#define IT51XXX_IRQ_WU110      115
+#define IT51XXX_IRQ_WU111      116
+#define IT51XXX_IRQ_WU112      117
+#define IT51XXX_IRQ_WU113      118
+#define IT51XXX_IRQ_WU114      119
+/* Group 15 */
+#define IT51XXX_IRQ_WU115      120
+#define IT51XXX_IRQ_WU116      121
+#define IT51XXX_IRQ_WU117      122
+#define IT51XXX_IRQ_WU118      123
+#define IT51XXX_IRQ_WU119      124
+#define IT51XXX_IRQ_WU120      125
+#define IT51XXX_IRQ_WU121      126
+#define IT51XXX_IRQ_WU122      127
+/* Group 16 */
+#define IT51XXX_IRQ_WU128      128
+#define IT51XXX_IRQ_WU129      129
+#define IT51XXX_IRQ_WU131      131
+#define IT51XXX_IRQ_WU132      132
+#define IT51XXX_IRQ_WU133      133
+#define IT51XXX_IRQ_WU134      134
+#define IT51XXX_IRQ_WU135      135
+/* Group 17 */
+#define IT51XXX_IRQ_WU136      136
+#define IT51XXX_IRQ_WU137      137
+#define IT51XXX_IRQ_WU138      138
+#define IT51XXX_IRQ_WU139      139
+#define IT51XXX_IRQ_WU140      140
+#define IT51XXX_IRQ_WU141      141
+#define IT51XXX_IRQ_WU142      142
+/* Group 18 */
+#define IT51XXX_IRQ_WU127      148
+#define IT51XXX_IRQ_V_CMP      151
+/* Group 19 */
+#define IT51XXX_IRQ_PECI       152
+#define IT51XXX_IRQ_ESPI       153
+#define IT51XXX_IRQ_ESPI_VW    154
+#define IT51XXX_IRQ_PCH_P80    155
+#define IT51XXX_IRQ_TIMER3     157
+#define IT51XXX_IRQ_PLL_CHANGE 159
+/* Group 20 */
+#define IT51XXX_IRQ_SMB_E      160
+#define IT51XXX_IRQ_SMB_F      161
+#define IT51XXX_IRQ_WU40       163
+#define IT51XXX_IRQ_WU45       166
+/* Group 21 */
+#define IT51XXX_IRQ_WU46       168
+#define IT51XXX_IRQ_WU144      170
+#define IT51XXX_IRQ_WU145      171
+#define IT51XXX_IRQ_WU146      172
+#define IT51XXX_IRQ_WU147      173
+#define IT51XXX_IRQ_TIMER4     175
+/* Group 22 */
+#define IT51XXX_IRQ_WU148      176
+#define IT51XXX_IRQ_WU149      177
+#define IT51XXX_IRQ_WU150      178
+#define IT51XXX_IRQ_WU151      179
+#define IT51XXX_IRQ_I3C_M0     180
+#define IT51XXX_IRQ_I3C_M1     181
+#define IT51XXX_IRQ_I3C_S0     182
+#define IT51XXX_IRQ_I3C_S1     183
+/* Group 25 */
+#define IT51XXX_IRQ_SMB_SC     203
+#define IT51XXX_IRQ_SMB_SB     204
+#define IT51XXX_IRQ_SMB_SA     205
+#define IT51XXX_IRQ_TIMER1_DW  207
+/* Group 26 */
+#define IT51XXX_IRQ_TIMER2_DW  208
+#define IT51XXX_IRQ_TIMER3_DW  209
+#define IT51XXX_IRQ_TIMER4_DW  210
+#define IT51XXX_IRQ_TIMER5_DW  211
+#define IT51XXX_IRQ_TIMER6_DW  212
+#define IT51XXX_IRQ_TIMER7_DW  213
+#define IT51XXX_IRQ_TIMER8_DW  214
+/* Group 27 */
+#define IT51XXX_IRQ_PWM_TACH0  219
+#define IT51XXX_IRQ_PWM_TACH1  220
+#define IT51XXX_IRQ_PWM_TACH2  221
+#define IT51XXX_IRQ_SMB_G      222
+#define IT51XXX_IRQ_SMB_H      223
+/* Group 28 */
+#define IT51XXX_IRQ_SMB_I      224
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_ITE_INTC_H_ */
diff --git a/include/zephyr/dt-bindings/interrupt-controller/ite-it51xxx-wuc.h b/include/zephyr/dt-bindings/interrupt-controller/ite-it51xxx-wuc.h
new file mode 100644
index 00000000000..99e2b9708c3
--- /dev/null
+++ b/include/zephyr/dt-bindings/interrupt-controller/ite-it51xxx-wuc.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_IT51XXX_WUC_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_IT51XXX_WUC_H_
+
+/** WUC reserved register of reg property */
+#define IT51XXX_WUC_UNUSED_REG 0
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_INTERRUPT_CONTROLLER_IT51XXX_WUC_H_ */
diff --git a/include/zephyr/dt-bindings/interrupt-controller/renesas-ra-icu.h b/include/zephyr/dt-bindings/interrupt-controller/renesas-ra-icu.h
deleted file mode 100644
index 4df6bfeae52..00000000000
--- a/include/zephyr/dt-bindings/interrupt-controller/renesas-ra-icu.h
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_DT_BINDINGS_INTERRUPT_CONTROLLER_RENESAS_RA_ICU_H_
-#define ZEPHYR_DT_BINDINGS_INTERRUPT_CONTROLLER_RENESAS_RA_ICU_H_
-
-#define RA_ICU_IRQ_UNSPECIFIED (-1)
-
-#define RA_ICU_PORT_IRQ0       (1 << 8)
-#define RA_ICU_PORT_IRQ1       (2 << 8)
-#define RA_ICU_PORT_IRQ2       (3 << 8)
-#define RA_ICU_PORT_IRQ3       (4 << 8)
-#define RA_ICU_PORT_IRQ4       (5 << 8)
-#define RA_ICU_PORT_IRQ5       (6 << 8)
-#define RA_ICU_PORT_IRQ6       (7 << 8)
-#define RA_ICU_PORT_IRQ7       (8 << 8)
-#define RA_ICU_PORT_IRQ8       (9 << 8)
-#define RA_ICU_PORT_IRQ9       (10 << 8)
-#define RA_ICU_PORT_IRQ10      (11 << 8)
-#define RA_ICU_PORT_IRQ11      (12 << 8)
-#define RA_ICU_PORT_IRQ12      (13 << 8)
-#define RA_ICU_PORT_IRQ14      (15 << 8)
-#define RA_ICU_PORT_IRQ15      (16 << 8)
-#define RA_ICU_DMAC0_INT       (17 << 8)
-#define RA_ICU_DMAC1_INT       (18 << 8)
-#define RA_ICU_DMAC2_INT       (19 << 8)
-#define RA_ICU_DMAC3_INT       (20 << 8)
-#define RA_ICU_DTC_COMPLETE    (21 << 8)
-#define RA_ICU_ICU_SNZCANCEL   (23 << 8)
-#define RA_ICU_FCU_FRDYI       (24 << 8)
-#define RA_ICU_LVD_LVD1        (25 << 8)
-#define RA_ICU_LVD_LVD2        (26 << 8)
-#define RA_ICU_VBATT_LVD       (27 << 8)
-#define RA_ICU_MOSC_STOP       (28 << 8)
-#define RA_ICU_SYSTEM_SNZREQ   (29 << 8)
-#define RA_ICU_AGT0_AGTI       (30 << 8)
-#define RA_ICU_AGT0_AGTCMAI    (31 << 8)
-#define RA_ICU_AGT0_AGTCMBI    (32 << 8)
-#define RA_ICU_AGT1_AGTI       (33 << 8)
-#define RA_ICU_AGT1_AGTCMAI    (34 << 8)
-#define RA_ICU_AGT1_AGTCMBI    (35 << 8)
-#define RA_ICU_IWDT_NMIUNDF    (36 << 8)
-#define RA_ICU_WDT_NMIUNDF     (37 << 8)
-#define RA_ICU_RTC_ALM         (38 << 8)
-#define RA_ICU_RTC_PRD         (39 << 8)
-#define RA_ICU_RTC_CUP         (40 << 8)
-#define RA_ICU_ADC140_ADI      (41 << 8)
-#define RA_ICU_ADC140_GBADI    (42 << 8)
-#define RA_ICU_ADC140_CMPAI    (43 << 8)
-#define RA_ICU_ADC140_CMPBI    (44 << 8)
-#define RA_ICU_ADC140_WCMPM    (45 << 8)
-#define RA_ICU_ADC140_WCMPUM   (46 << 8)
-#define RA_ICU_ACMP_LP0        (47 << 8)
-#define RA_ICU_ACMP_LP1        (48 << 8)
-#define RA_ICU_USBFS_D0FIFO    (49 << 8)
-#define RA_ICU_USBFS_D1FIFO    (50 << 8)
-#define RA_ICU_USBFS_USBI      (51 << 8)
-#define RA_ICU_USBFS_USBR      (52 << 8)
-#define RA_ICU_IIC0_RXI        (53 << 8)
-#define RA_ICU_IIC0_TXI        (54 << 8)
-#define RA_ICU_IIC0_TEI        (55 << 8)
-#define RA_ICU_IIC0_EEI        (56 << 8)
-#define RA_ICU_IIC0_WUI        (57 << 8)
-#define RA_ICU_IIC1_RXI        (58 << 8)
-#define RA_ICU_IIC1_TXI        (59 << 8)
-#define RA_ICU_IIC1_TEI        (60 << 8)
-#define RA_ICU_IIC1_EEI        (61 << 8)
-#define RA_ICU_SSIE0_SSITXI    (62 << 8)
-#define RA_ICU_SSIE0_SSIRXI    (63 << 8)
-
-#define RA_ICU_SSIE0_SSIF      (65 << 8)
-#define RA_ICU_CTSU_CTSUWR     (66 << 8)
-#define RA_ICU_CTSU_CTSURD     (67 << 8)
-#define RA_ICU_CTSU_CTSUFN     (68 << 8)
-#define RA_ICU_KEY_INTKR       (69 << 8)
-#define RA_ICU_DOC_DOPCI       (70 << 8)
-#define RA_ICU_CAC_FERRI       (71 << 8)
-#define RA_ICU_CAC_MENDI       (72 << 8)
-#define RA_ICU_CAC_OVFI        (73 << 8)
-#define RA_ICU_CAN0_ERS        (74 << 8)
-#define RA_ICU_CAN0_RXF        (75 << 8)
-#define RA_ICU_CAN0_TXF        (76 << 8)
-#define RA_ICU_CAN0_RXM        (77 << 8)
-#define RA_ICU_CAN0_TXM        (78 << 8)
-#define RA_ICU_IOPORT_GROUP1   (70 << 8)
-#define RA_ICU_IOPORT_GROUP2   (80 << 8)
-#define RA_ICU_IOPORT_GROUP3   (81 << 8)
-#define RA_ICU_IOPORT_GROUP4   (82 << 8)
-#define RA_ICU_ELC_SWEVT0      (83 << 8)
-#define RA_ICU_ELC_SWEVT1      (84 << 8)
-#define RA_ICU_POEG_GROUP0     (85 << 8)
-#define RA_ICU_POEG_GROUP1     (86 << 8)
-#define RA_ICU_GPT0_CCMPA      (87 << 8)
-#define RA_ICU_GPT0_CCMPB      (88 << 8)
-#define RA_ICU_GPT0_CMPC       (89 << 8)
-#define RA_ICU_GPT0_CMPD       (90 << 8)
-#define RA_ICU_GPT0_CMPE       (91 << 8)
-#define RA_ICU_GPT0_CMPF       (92 << 8)
-#define RA_ICU_GPT0_OVF        (93 << 8)
-#define RA_ICU_GPT0_UDF        (94 << 8)
-#define RA_ICU_GPT1_CCMPA      (95 << 8)
-#define RA_ICU_GPT1_CCMPB      (96 << 8)
-#define RA_ICU_GPT1_CMPC       (97 << 8)
-#define RA_ICU_GPT1_CMPD       (98 << 8)
-#define RA_ICU_GPT1_CMPE       (99 << 8)
-#define RA_ICU_GPT1_CMPF       (100 << 8)
-#define RA_ICU_GPT1_OVF        (101 << 8)
-#define RA_ICU_GPT1_UDF        (102 << 8)
-#define RA_ICU_GPT2_CCMPA      (103 << 8)
-#define RA_ICU_GPT2_CCMPB      (104 << 8)
-#define RA_ICU_GPT2_CMPC       (105 << 8)
-#define RA_ICU_GPT2_CMPD       (106 << 8)
-#define RA_ICU_GPT2_CMPE       (107 << 8)
-#define RA_ICU_GPT2_CMPF       (108 << 8)
-#define RA_ICU_GPT2_OVF        (109 << 8)
-#define RA_ICU_GPT2_UDF        (110 << 8)
-#define RA_ICU_GPT3_CCMPA      (111 << 8)
-#define RA_ICU_GPT3_CCMPB      (112 << 8)
-#define RA_ICU_GPT3_CMPC       (113 << 8)
-#define RA_ICU_GPT3_CMPD       (114 << 8)
-#define RA_ICU_GPT3_CMPE       (115 << 8)
-#define RA_ICU_GPT3_CMPF       (116 << 8)
-#define RA_ICU_GPT3_OVF        (117 << 8)
-#define RA_ICU_GPT3_UDF        (118 << 8)
-#define RA_ICU_GPT4_CCMPA      (119 << 8)
-#define RA_ICU_GPT4_CCMPB      (120 << 8)
-#define RA_ICU_GPT4_CMPC       (121 << 8)
-#define RA_ICU_GPT4_CMPD       (122 << 8)
-#define RA_ICU_GPT4_CMPE       (123 << 8)
-#define RA_ICU_GPT4_CMPF       (124 << 8)
-#define RA_ICU_GPT4_OVF        (125 << 8)
-#define RA_ICU_GPT4_UDF        (126 << 8)
-#define RA_ICU_GPT5_CCMPA      (127 << 8)
-#define RA_ICU_GPT5_CCMPB      (128 << 8)
-#define RA_ICU_GPT5_CMPC       (129 << 8)
-#define RA_ICU_GPT5_CMPD       (130 << 8)
-#define RA_ICU_GPT5_CMPE       (131 << 8)
-#define RA_ICU_GPT5_CMPF       (132 << 8)
-#define RA_ICU_GPT5_OVF        (133 << 8)
-#define RA_ICU_GPT5_UDF        (134 << 8)
-#define RA_ICU_GPT6_CCMPA      (135 << 8)
-#define RA_ICU_GPT6_CCMPB      (136 << 8)
-#define RA_ICU_GPT6_CMPC       (137 << 8)
-#define RA_ICU_GPT6_CMPD       (138 << 8)
-#define RA_ICU_GPT6_CMPE       (139 << 8)
-#define RA_ICU_GPT6_CMPF       (140 << 8)
-#define RA_ICU_GPT6_OVF        (141 << 8)
-#define RA_ICU_GPT6_UDF        (142 << 8)
-#define RA_ICU_GPT7_CCMPA      (143 << 8)
-#define RA_ICU_GPT7_CCMPB      (144 << 8)
-#define RA_ICU_GPT7_CMPC       (145 << 8)
-#define RA_ICU_GPT7_CMPD       (146 << 8)
-#define RA_ICU_GPT7_CMPE       (147 << 8)
-#define RA_ICU_GPT7_CMPF       (148 << 8)
-#define RA_ICU_GPT7_OVF        (149 << 8)
-#define RA_ICU_GPT7_UDF        (150 << 8)
-#define RA_ICU_GPT_UVWEDGE     (151 << 8)
-#define RA_ICU_SCI0_RXI        (152 << 8)
-#define RA_ICU_SCI0_TXI        (153 << 8)
-#define RA_ICU_SCI0_TEI        (154 << 8)
-#define RA_ICU_SCI0_ERI        (155 << 8)
-#define RA_ICU_SCI0_AM         (156 << 8)
-#define RA_ICU_SCI0_RXI_OR_ERI (157 << 8)
-#define RA_ICU_SCI1_RXI        (158 << 8)
-#define RA_ICU_SCI1_TXI        (159 << 8)
-#define RA_ICU_SCI1_TEI        (160 << 8)
-#define RA_ICU_SCI1_ERI        (161 << 8)
-#define RA_ICU_SCI1_AM         (162 << 8)
-#define RA_ICU_SCI2_RXI        (163 << 8)
-#define RA_ICU_SCI2_TXI        (164 << 8)
-#define RA_ICU_SCI2_TEI        (165 << 8)
-#define RA_ICU_SCI2_ERI        (166 << 8)
-#define RA_ICU_SCI2_AM         (167 << 8)
-#define RA_ICU_SCI9_RXI        (168 << 8)
-#define RA_ICU_SCI9_TXI        (169 << 8)
-#define RA_ICU_SCI9_TEI        (170 << 8)
-#define RA_ICU_SCI9_ERI        (171 << 8)
-#define RA_ICU_SCI9_AM         (172 << 8)
-#define RA_ICU_SPI0_SPRI       (173 << 8)
-#define RA_ICU_SPI0_SPTI       (174 << 8)
-#define RA_ICU_SPI0_SPII       (175 << 8)
-#define RA_ICU_SPI0_SPEI       (176 << 8)
-#define RA_ICU_SPI0_SPTEND     (177 << 8)
-#define RA_ICU_SPI1_SPRI       (178 << 8)
-#define RA_ICU_SPI1_SPTI       (179 << 8)
-#define RA_ICU_SPI1_SPII       (180 << 8)
-#define RA_ICU_SPI1_SPEI       (181 << 8)
-#define RA_ICU_SPI1_SPTEND     (182 << 8)
-
-#endif /* ZEPHYR_DT_BINDINGS_INTERRUPT_CONTROLLER_RENESAS_RA_ICU_H_ */
diff --git a/include/zephyr/dt-bindings/memory-attr/memory-attr-arm.h b/include/zephyr/dt-bindings/memory-attr/memory-attr-arm.h
index 473c43fc781..607907d6d5d 100644
--- a/include/zephyr/dt-bindings/memory-attr/memory-attr-arm.h
+++ b/include/zephyr/dt-bindings/memory-attr/memory-attr-arm.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2023 Carlo Caione <ccaione@baylibre.com>
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -18,23 +19,25 @@
  * This is legacy and it should NOT be extended further. If new MPU region
  * types must be added, these must rely on the generic memory attributes.
  */
-#define DT_MEM_ARM_MASK			DT_MEM_ARCH_ATTR_MASK
-#define DT_MEM_ARM_GET(x)		((x) & DT_MEM_ARM_MASK)
-#define DT_MEM_ARM(x)			((x) << DT_MEM_ARCH_ATTR_SHIFT)
+#define DT_MEM_ARM_MASK   DT_MEM_ARCH_ATTR_MASK
+#define DT_MEM_ARM_GET(x) ((x) & DT_MEM_ARM_MASK)
+#define DT_MEM_ARM(x)     ((x) << DT_MEM_ARCH_ATTR_SHIFT)
 
-#define  ATTR_MPU_RAM			BIT(0)
-#define  ATTR_MPU_RAM_NOCACHE		BIT(1)
-#define  ATTR_MPU_FLASH			BIT(2)
-#define  ATTR_MPU_PPB			BIT(3)
-#define  ATTR_MPU_IO			BIT(4)
-#define  ATTR_MPU_EXTMEM		BIT(5)
+#define ATTR_MPU_RAM         BIT(0)
+#define ATTR_MPU_RAM_NOCACHE BIT(1)
+#define ATTR_MPU_FLASH       BIT(2)
+#define ATTR_MPU_PPB         BIT(3)
+#define ATTR_MPU_IO          BIT(4)
+#define ATTR_MPU_EXTMEM      BIT(5)
+#define ATTR_MPU_RAM_PXN     BIT(6)
 
-#define DT_MEM_ARM_MPU_RAM		DT_MEM_ARM(ATTR_MPU_RAM)
-#define DT_MEM_ARM_MPU_RAM_NOCACHE	DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)
-#define DT_MEM_ARM_MPU_FLASH		DT_MEM_ARM(ATTR_MPU_FLASH)
-#define DT_MEM_ARM_MPU_PPB		DT_MEM_ARM(ATTR_MPU_PPB)
-#define DT_MEM_ARM_MPU_IO		DT_MEM_ARM(ATTR_MPU_IO)
-#define DT_MEM_ARM_MPU_EXTMEM		DT_MEM_ARM(ATTR_MPU_EXTMEM)
-#define DT_MEM_ARM_MPU_UNKNOWN		DT_MEM_ARCH_ATTR_UNKNOWN
+#define DT_MEM_ARM_MPU_RAM         DT_MEM_ARM(ATTR_MPU_RAM)
+#define DT_MEM_ARM_MPU_RAM_NOCACHE DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE)
+#define DT_MEM_ARM_MPU_FLASH       DT_MEM_ARM(ATTR_MPU_FLASH)
+#define DT_MEM_ARM_MPU_PPB         DT_MEM_ARM(ATTR_MPU_PPB)
+#define DT_MEM_ARM_MPU_IO          DT_MEM_ARM(ATTR_MPU_IO)
+#define DT_MEM_ARM_MPU_EXTMEM      DT_MEM_ARM(ATTR_MPU_EXTMEM)
+#define DT_MEM_ARM_MPU_RAM_PXN     DT_MEM_ARM(ATTR_MPU_RAM_PXN)
+#define DT_MEM_ARM_MPU_UNKNOWN     DT_MEM_ARCH_ATTR_UNKNOWN
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_MEM_ATTR_ARM_H_ */
diff --git a/include/zephyr/dt-bindings/mipi_dbi/mipi_dbi.h b/include/zephyr/dt-bindings/mipi_dbi/mipi_dbi.h
index cb3eae16512..b767b1804d2 100644
--- a/include/zephyr/dt-bindings/mipi_dbi/mipi_dbi.h
+++ b/include/zephyr/dt-bindings/mipi_dbi/mipi_dbi.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024,2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -110,6 +110,54 @@
 #define MIPI_DBI_MODE_8080_BUS_9_BIT 0x7
 #define MIPI_DBI_MODE_8080_BUS_8_BIT 0x8
 
+/** Color coding for MIPI DBI Type A or Type B interface. */
+/**
+ * For 8-bit data bus width, 1 pixel is sent in 1 cycle. For 16-bit data bus width,
+ * 2 pixels are sent in 1 cycle.
+ */
+#define MIPI_DBI_MODE_RGB332 (0x1 << 4U)
+/**
+ * For 8-bit data bus width, 2 pixels are sent in 3 cycles. For 16-bit data bus width,
+ * 1 pixel is sent in 1 cycle, the high 4 bits are not used.
+ */
+#define MIPI_DBI_MODE_RGB444 (0x2 << 4U)
+/**
+ * For 8-bit data bus width, 1 pixel is sent in 2 cycles. For 16-bit data bus width,
+ * 1 pixel is sent in 1 cycle.
+ */
+#define MIPI_DBI_MODE_RGB565 (0x3 << 4U)
+/**
+ * For 8-bit data bus width, MIPI_DBI_MODE_RGB666_1 and MIPI_DBI_MODE_RGB666_2
+ * are the same. 1 pixel is sent in 3 cycles, R component first, and the low 2
+ * bits are not used.
+ * For 9-bit data bus width, MIPI_DBI_MODE_RGB666_1 and MIPI_DBI_MODE_RGB666_2
+ * are the same. 1 pixel is sent in 2 cycles.
+ * For 16-bit data bus width, MIPI_DBI_MODE_RGB666_1 is option 1,
+ * 2 pixels are sent in 3 cycles. The first pixel's R/G/B components are sent in
+ * cycle 1 bits 10-15, cycle 1 bits 2-7 and cycle 2 bits 10-15.
+ * The second pixel's R/G/B components are sent in cycle 2 bits 2-7, cycle 3 bits
+ * 10-15 and cycle 3 bits 2-7.
+ * MIPI_DBI_MODE_RGB666_2 is option 2, 1 pixel is sent in 2 cycles. The pixel's
+ * R/G/B components are sent in cycle 1 bits 2-7, cycle 2 bits 10-15 and cycle 2
+ * bits 2-7.
+ */
+#define MIPI_DBI_MODE_RGB666_1 (0x4 << 4U)
+#define MIPI_DBI_MODE_RGB666_2 (0x5 << 4U)
+/**
+ * For 8-bit data bus width, MIPI_DBI_MODE_RGB666_1 and MIPI_DBI_MODE_RGB666_2
+ * are the same. 1 pixel is sent in 3 cycles, R component first.
+ * For 16-bit data bus width, MIPI_DBI_MODE_RGB666_1 is option 1,
+ * 2 pixels are sent in 3 cycles. The first pixel's R/G/B components are sent in
+ * cycle 1 bits 8-15, cycle 1 bits 0-7 and cycle 2 bits 0-15.
+ * The second pixel's R/G/B components are sent in cycle 2 bits 0-7, cycle 3 bits
+ * 8-15 and cycle 3 bits 0-7.
+ * MIPI_DBI_MODE_RGB666_2 is option 2, 1 pixel is sent in 2 cycles. The pixel's
+ * R/G/B components are sent in cycle 1 bits 0-7, cycle 2 bits 8-15 and cycle 2
+ * bits 0-7.
+ */
+#define MIPI_DBI_MODE_RGB888_1 (0x6 << 4U)
+#define MIPI_DBI_MODE_RGB888_2 (0x7 << 4U)
+
 /** MIPI DBI tearing enable synchronization is disabled. */
 #define MIPI_DBI_TE_NO_EDGE 0x0
 
diff --git a/include/zephyr/dt-bindings/pinctrl/ambiq-apollo5-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/ambiq-apollo5-pinctrl.h
new file mode 100644
index 00000000000..083386a5bf2
--- /dev/null
+++ b/include/zephyr/dt-bindings/pinctrl/ambiq-apollo5-pinctrl.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025 Ambiq Micro Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __APOLLO5_PINCTRL_H__
+#define __APOLLO5_PINCTRL_H__
+
+#define APOLLO5_ALT_FUNC_POS 0
+#define APOLLO5_ALT_FUNC_MASK 0xf
+
+#define APOLLO5_PIN_NUM_POS 4
+#define APOLLO5_PIN_NUM_MASK 0xff
+
+#define APOLLO5_PINMUX(pin_num, alt_func)       \
+        (pin_num << APOLLO5_PIN_NUM_POS |       \
+         alt_func << APOLLO5_ALT_FUNC_POS)
+
+#endif /* __APOLLO5_PINCTRL_H__ */
diff --git a/include/zephyr/dt-bindings/pinctrl/arm-mps2-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/arm-mps2-pinctrl.h
new file mode 100644
index 00000000000..dfb1dc9dfec
--- /dev/null
+++ b/include/zephyr/dt-bindings/pinctrl/arm-mps2-pinctrl.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define MPS2_ALT_FUNC_POS 0
+#define MPS2_ALT_FUNC_MASK 0x3
+
+#define MPS2_EXP_NUM_POS 2
+#define MPS2_EXP_NUM_MASK 0x3F
+
+#define MPS2_PINCTRL_FUNC_UART 0
+#define MPS2_PINCTRL_FUNC_GPIO 1
+#define MPS2_PINCTRL_FUNC_I2C 2
+#define MPS2_PINCTRL_FUNC_SPI 3
+
+
+#define MPS2_PINMUX(alt_func, exp_num) (exp_num << MPS2_EXP_NUM_POS | \
+	alt_func << MPS2_ALT_FUNC_POS)
+
+
+
+/*
+ * This is the mapping from the ARM MPS2 Board pins to GPIO
+ * controllers.
+ *
+ * D0 : EXT_0
+ * D1 : EXT_4
+ * D2 : EXT_2
+ * D3 : EXT_3
+ * D4 : EXT_1
+ * D5 : EXT_6
+ * D6 : EXT_7
+ * D7 : EXT_8
+ * D8 : EXT_9
+ * D9 : EXT_10
+ * D10 : EXT_12
+ * D11 : EXT_13
+ * D12 : EXT_14
+ * D13 : EXT_11
+ * D14 : EXT_15
+ * D15 : EXT_5
+ * D16 : EXT_16
+ * D17 : EXT_17
+ * D18 : EXT_18
+ * D19 : EXT_19
+ * D20 : EXT_20
+ * D21 : EXT_21
+ * D22 : EXT_22
+ * D23 : EXT_23
+ * D24 : EXT_24
+ * D25 : EXT_25
+ * D26 : EXT_26
+ * D27 : EXT_30
+ * D28 : EXT_28
+ * D29 : EXT_29
+ * D30 : EXT_27
+ * D31 : EXT_32
+ * D32 : EXT_33
+ * D33 : EXT_34
+ * D34 : EXT_35
+ * D35 : EXT_36
+ * D36 : EXT_38
+ * D37 : EXT_39
+ * D38 : EXT_40
+ * D39 : EXT_44
+ * D40 : EXT_41
+ * D41 : EXT_31
+ * D42 : EXT_37
+ * D43 : EXT_42
+ * D44 : EXT_43
+ * D45 : EXT_45
+ * D46 : EXT_46
+ * D47 : EXT_47
+ * D48 : EXT_48
+ * D49 : EXT_49
+ * D50 : EXT_50
+ * D51 : EXT_51
+ *
+ * UART_3_RX : D0
+ * UART_3_TX : D1
+ * SPI_3_CS : D10
+ * SPI_3_MOSI : D11
+ * SPI_3_MISO : D12
+ * SPI_3_SCLK : D13
+ * I2C_3_SDA : D14
+ * I2C_3_SCL : D15
+ * UART_4_RX : D26
+ * UART_4_TX : D30
+ * SPI_4_CS : D36
+ * SPI_4_MOSI : D37
+ * SPI_4_MISO : D38
+ * SPI_4_SCK : D39
+ * I2C_4_SDA : D40
+ * I2C_4_SCL : D41
+ *
+ */
+
+/* GPIO 0 */
+#define UART3_RXD_EXP MPS2_PINMUX(MPS2_PINCTRL_FUNC_UART, 0)
+#define UART3_TXD_EXP MPS2_PINMUX(MPS2_PINCTRL_FUNC_UART, 4)
+#define SBCON2_SCL_EXP MPS2_PINMUX(MPS2_PINCTRL_FUNC_I2C, 5)
+#define SBCON2_SDA_EXP MPS2_PINMUX(MPS2_PINCTRL_FUNC_I2C, 15)
+#define SPI3_SCK_EXP MPS2_PINMUX(MPS2_PINCTRL_FUNC_SPI, 11)
+#define SPI3_SS_EXP MPS2_PINMUX(MPS2_PINCTRL_FUNC_SPI, 12)
+#define SPI3_MOSI_EXP MPS2_PINMUX(MPS2_PINCTRL_FUNC_SPI, 13)
+#define SPI3_MISO_EXP MPS2_PINMUX(MPS2_PINCTRL_FUNC_SPI, 14)
+
+/* GPIO 1 */
+#define SPI2_SS_EXP  MPS2_PINMUX(MPS2_PINCTRL_FUNC_SPI, 16)
+#define SPI2_MISO_EXP  MPS2_PINMUX(MPS2_PINCTRL_FUNC_SPI, 17)
+#define SPI2_MOSI_EXP  MPS2_PINMUX(MPS2_PINCTRL_FUNC_SPI, 18)
+#define SPI2_SCK_EXP  MPS2_PINMUX(MPS2_PINCTRL_FUNC_SPI, 19)
+#define UART4_RXD_EXP MPS2_PINMUX(MPS2_PINCTRL_FUNC_UART, 26)
+#define UART4_TXD_EXP MPS2_PINMUX(MPS2_PINCTRL_FUNC_UART, 30)
+#define SBCON3_SCL_EXP MPS2_PINMUX(MPS2_PINCTRL_FUNC_I2C, 31)
+
+/* GPIO 2 */
+#define SBCON3_SDA_EXP MPS2_PINMUX(MPS2_PINCTRL_FUNC_I2C, 41)
+#define SPI4_SS_EXP MPS2_PINMUX(MPS2_PINCTRL_FUNC_SPI, 38)
+#define SPI4_MOSI_EXP MPS2_PINMUX(MPS2_PINCTRL_FUNC_SPI, 39)
+#define SPI4_MISO_EXP MPS2_PINMUX(MPS2_PINCTRL_FUNC_SPI, 40)
+#define SPI4_SCK_EXP MPS2_PINMUX(MPS2_PINCTRL_FUNC_SPI, 44)
diff --git a/include/zephyr/dt-bindings/pinctrl/arm-mps3-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/arm-mps3-pinctrl.h
new file mode 100644
index 00000000000..3c873dd155f
--- /dev/null
+++ b/include/zephyr/dt-bindings/pinctrl/arm-mps3-pinctrl.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define MPS3_ALT_FUNC_POS 0
+#define MPS3_ALT_FUNC_MASK 0x7
+
+#define MPS3_EXP_NUM_POS 3
+#define MPS3_EXP_NUM_MASK 0x1F8
+
+#define MPS3_PINCTRL_FUNC_UART 0
+#define MPS3_PINCTRL_FUNC_GPIO 1
+#define MPS3_PINCTRL_FUNC_I2C 2
+#define MPS3_PINCTRL_FUNC_SPI 3
+#define MPS3_PINCTRL_FUNC_PMOD 4
+
+#define MPS3_PINMUX(alt_func, exp_num) (exp_num << MPS3_EXP_NUM_POS | \
+	alt_func << MPS3_ALT_FUNC_POS)
+
+/* GPIO 0 */
+#define PMOD1_IO1_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_PMOD, 0)
+#define PMOD1_IO0_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_PMOD, 1)
+#define PMOD1_SS_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_PMOD, 3)
+#define PMOD0_IO2_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_PMOD, 7)
+#define PMOD0_IO3_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_PMOD, 8)
+#define PMOD1_SCK_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_PMOD, 9)
+#define PMOD0_SS_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_PMOD, 10)
+#define PMOD0_IO0_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_PMOD, 11)
+#define PMOD0_IO1_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_PMOD, 12)
+#define PMOD0_SCK_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_PMOD, 13)
+#define PMOD1_IO3_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_PMOD, 14)
+#define PMOD1_IO2_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_PMOD, 15)
+
+#define UART3_RXD_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_UART, 0)
+#define UART3_TXD_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_UART, 1)
+#define SPI3_SS_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_SPI, 10)
+#define SPI3_MOSI_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_SPI, 11)
+#define SPI3_MISO_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_SPI, 12)
+#define SPI3_SCK_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_SPI, 13)
+#define SBCON2_SDA_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_I2C, 14)
+#define SBCON2_SCL_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_I2C, 15)
+
+
+/* GPIO 1 */
+#define UART4_RXD_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_UART, 16)
+#define UART4_TXD_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_UART, 17)
+#define SPI4_SS_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_SPI, 26)
+#define SPI4_MOSI_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_SPI, 27)
+#define SPI4_MISO_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_SPI, 28)
+#define SPI4_SCK_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_SPI, 29)
+#define SBCON3_SDA_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_I2C, 30)
+#define SBCON3_SCL_EXP MPS3_PINMUX(MPS3_PINCTRL_FUNC_I2C, 31)
diff --git a/include/zephyr/dt-bindings/pinctrl/arm-v2m_beetle-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/arm-v2m_beetle-pinctrl.h
new file mode 100644
index 00000000000..0dcf30b9f20
--- /dev/null
+++ b/include/zephyr/dt-bindings/pinctrl/arm-v2m_beetle-pinctrl.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define V2M_BEETLE_ALT_FUNC_POS 0
+#define V2M_BEETLE_ALT_FUNC_MASK 0x7
+
+#define V2M_BEETLE_EXP_NUM_POS 3
+#define V2M_BEETLE_EXP_NUM_MASK 0x1F8
+
+#define V2M_BEETLE_PINCTRL_FUNC_UART 0
+#define V2M_BEETLE_PINCTRL_FUNC_GPIO 1
+#define V2M_BEETLE_PINCTRL_FUNC_I2C 2
+#define V2M_BEETLE_PINCTRL_FUNC_SPI 3
+#define V2M_BEETLE_PINCTRL_FUNC_QSPI 4
+
+#define V2M_BEETLE_PINMUX(alt_func, exp_num) (exp_num << V2M_BEETLE_EXP_NUM_POS | \
+	alt_func << V2M_BEETLE_ALT_FUNC_POS)
+
+
+
+/* GPIO 0 */
+#define UART0_RXD_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_UART, 0)
+#define UART0_TXD_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_UART, 1)
+#define SPI0_SS_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_SPI, 10)
+#define SPI0_MOSI_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_SPI, 11)
+#define SPI0_MISO_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_SPI, 12)
+#define SPI0_SCK_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_SPI, 13)
+#define SBCON0_SDA_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_I2C, 14)
+#define SBCON0_SCL_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_I2C, 15)
+
+/* GPIO 1 */
+#define UART1_RXD_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_UART, 16)
+#define UART1_TXD_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_UART, 17)
+#define SPI1_SS_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_SPI, 18)
+#define SPI1_MOSI_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_SPI, 19)
+#define SPI1_MISO_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_SPI, 20)
+#define SPI1_SCK_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_SPI, 21)
+#define SBCON1_SDA_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_I2C, 22)
+#define SBCON1_SCL_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_I2C, 23)
+#define QSPI_CS2_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_QSPI, 24)
+#define QSPI_CS1_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_QSPI, 25)
+#define QSPI_IOF0_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_QSPI, 26)
+#define QSPI_IOF1_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_QSPI, 27)
+#define QSPI_IOF2_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_QSPI, 28)
+#define QSPI_IOF3_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_QSPI, 29)
+#define QSPI_SCK_EXP V2M_BEETLE_PINMUX(V2M_BEETLE_PINCTRL_FUNC_QSPI, 30)
diff --git a/include/zephyr/dt-bindings/pinctrl/cc23x0-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/cc23x0-pinctrl.h
new file mode 100644
index 00000000000..1c365965c9d
--- /dev/null
+++ b/include/zephyr/dt-bindings/pinctrl/cc23x0-pinctrl.h
@@ -0,0 +1,227 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef CC23X0_PINCTRL_COMMON_H_
+#define CC23X0_PINCTRL_COMMON_H_
+
+/*
+ * The whole TI CC23X0 pin configuration information is encoded in a 32-bit
+ * bitfield organized as follow:
+ *
+ * - 31:     Reserved
+ * - 30:     Input hysteresis
+ * - 29:     Input capability of IO
+ * - 28..27: Reserved
+ * - 26..24: IO mode
+ * - 23..22: Reserved
+ * - 21..20: Wakeup configuration from shutdown
+ * - 19:     Reserved
+ * - 18:     Wakeup capability from standby
+ * - 17..16: Edge detection configuration
+ * - 15:     Reserved
+ * - 14..13: Pull control
+ * - 12..3:  Reserved
+ * - 2..0:   Function configuration
+ */
+
+/* TI CC23X0 function configuration */
+
+#define IOC_PORTCFG_BASE   0U
+#define IOC_PORTCFG_PFUNC1 1U
+#define IOC_PORTCFG_PFUNC2 2U
+#define IOC_PORTCFG_PFUNC3 3U
+#define IOC_PORTCFG_PFUNC4 4U
+#define IOC_PORTCFG_PFUNC5 5U
+#define IOC_PORTCFG_ANA    6U
+#define IOC_PORTCFG_DTB    7U
+
+/* TI CC23X0 peripheral pin mapping */
+
+#define DIO0_GPIO0    IOC_PORTCFG_BASE
+#define DIO0_SPI0_CSN IOC_PORTCFG_PFUNC1
+#define DIO0_I2C0_SDA IOC_PORTCFG_PFUNC2
+#define DIO0_T3_C2    IOC_PORTCFG_PFUNC3
+#define DIO0_ADC5     IOC_PORTCFG_ANA
+
+#define DIO1_GPIO1     IOC_PORTCFG_BASE
+#define DIO1_T3_C1     IOC_PORTCFG_PFUNC1
+#define DIO1_LRFD7     IOC_PORTCFG_PFUNC2
+#define DIO1_T1_F      IOC_PORTCFG_PFUNC3
+#define DIO1_UART0_RTS IOC_PORTCFG_PFUNC4
+#define DIO1_ADC4      IOC_PORTCFG_ANA
+#define DIO1_DTB2      IOC_PORTCFG_DTB
+
+#define DIO2_GPIO2     IOC_PORTCFG_BASE
+#define DIO2_T0_PE     IOC_PORTCFG_PFUNC1
+#define DIO2_T2_C1N    IOC_PORTCFG_PFUNC2
+#define DIO2_UART0_CTS IOC_PORTCFG_PFUNC3
+#define DIO2_ADC3      IOC_PORTCFG_ANA
+
+#define DIO3_GPIO3  IOC_PORTCFG_BASE
+#define DIO3_LFCI   IOC_PORTCFG_PFUNC1
+#define DIO3_T0_C1N IOC_PORTCFG_PFUNC2
+#define DIO3_LRFD0  IOC_PORTCFG_PFUNC3
+#define DIO3_T3_C1  IOC_PORTCFG_PFUNC4
+#define DIO3_T1_C2  IOC_PORTCFG_PFUNC5
+#define DIO3_LFXT_P IOC_PORTCFG_ANA
+#define DIO3_DTB7   IOC_PORTCFG_DTB
+
+#define DIO4_GPIO4     IOC_PORTCFG_BASE
+#define DIO4_T0_C2N    IOC_PORTCFG_PFUNC1
+#define DIO4_UART0_TXD IOC_PORTCFG_PFUNC2
+#define DIO4_LRFD1     IOC_PORTCFG_PFUNC3
+#define DIO4_SPI0_MOSI IOC_PORTCFG_PFUNC4
+#define DIO4_T0_C2     IOC_PORTCFG_PFUNC5
+#define DIO4_LFXT_N    IOC_PORTCFG_ANA
+#define DIO4_DTB8      IOC_PORTCFG_DTB
+
+#define DIO5_GPIO5 IOC_PORTCFG_BASE
+#define DIO5_T2_C2 IOC_PORTCFG_PFUNC1
+#define DIO5_LRFD6 IOC_PORTCFG_PFUNC3
+#define DIO5_ADC2  IOC_PORTCFG_ANA
+
+#define DIO6_GPIO6      IOC_PORTCFG_BASE
+#define DIO6_SPI0_CSN   IOC_PORTCFG_PFUNC1
+#define DIO6_I2C0_SCL   IOC_PORTCFG_PFUNC2
+#define DIO6_T1_C2      IOC_PORTCFG_PFUNC3
+#define DIO6_LRFD2      IOC_PORTCFG_PFUNC4
+#define DIO6_UART0_TXD  IOC_PORTCFG_PFUNC5
+#define DIO6_ADC1_AREFP IOC_PORTCFG_ANA
+#define DIO6_DTB6       IOC_PORTCFG_DTB
+
+#define DIO7_GPIO7      IOC_PORTCFG_BASE
+#define DIO7_T3_C1      IOC_PORTCFG_PFUNC1
+#define DIO7_LRFD4      IOC_PORTCFG_PFUNC3
+#define DIO7_ADC0_AREFM IOC_PORTCFG_ANA
+
+#define DIO8_GPIO8     IOC_PORTCFG_BASE
+#define DIO8_SPI0_SCLK IOC_PORTCFG_PFUNC1
+#define DIO8_UART0_RTS IOC_PORTCFG_PFUNC2
+#define DIO8_T1_C0N    IOC_PORTCFG_PFUNC3
+#define DIO8_I2C0_SDA  IOC_PORTCFG_PFUNC4
+#define DIO8_T0_C0N    IOC_PORTCFG_PFUNC5
+#define DIO8_DTB3      IOC_PORTCFG_DTB
+
+#define DIO9_GPIO9 IOC_PORTCFG_BASE
+#define DIO9_T3_C0 IOC_PORTCFG_PFUNC1
+#define DIO9_LRFD3 IOC_PORTCFG_PFUNC3
+
+#define DIO10_GPIO10 IOC_PORTCFG_BASE
+#define DIO10_LPC0   IOC_PORTCFG_PFUNC1
+#define DIO10_T2_PE  IOC_PORTCFG_PFUNC2
+#define DIO10_T3_C0N IOC_PORTCFG_PFUNC3
+
+#define DIO11_GPIO11    IOC_PORTCFG_BASE
+#define DIO11_SPI0_CSN  IOC_PORTCFG_PFUNC1
+#define DIO11_T1_C2N    IOC_PORTCFG_PFUNC2
+#define DIO11_T0_C0     IOC_PORTCFG_PFUNC3
+#define DIO11_LRFD0     IOC_PORTCFG_PFUNC4
+#define DIO11_SPI0_MISO IOC_PORTCFG_PFUNC5
+#define DIO11_DTB9      IOC_PORTCFG_DTB
+
+#define DIO12_GPIO12    IOC_PORTCFG_BASE
+#define DIO12_SPI0_MISO IOC_PORTCFG_PFUNC1
+#define DIO12_SPI0_MOSI IOC_PORTCFG_PFUNC2
+#define DIO12_UART0_RXD IOC_PORTCFG_PFUNC3
+#define DIO12_T1_C1     IOC_PORTCFG_PFUNC4
+#define DIO12_I2C0_SDA  IOC_PORTCFG_PFUNC5
+#define DIO12_DTB13     IOC_PORTCFG_DTB
+
+#define DIO13_GPIO13    IOC_PORTCFG_BASE
+#define DIO13_SPI0_MISO IOC_PORTCFG_PFUNC1
+#define DIO13_SPI0_MOSI IOC_PORTCFG_PFUNC2
+#define DIO13_UART0_TXD IOC_PORTCFG_PFUNC3
+#define DIO13_T0_C0N    IOC_PORTCFG_PFUNC4
+#define DIO13_T1_F      IOC_PORTCFG_PFUNC5
+#define DIO13_DTB4      IOC_PORTCFG_DTB
+
+#define DIO14_GPIO14 IOC_PORTCFG_BASE
+#define DIO14_T3_C2  IOC_PORTCFG_PFUNC1
+#define DIO14_T1_C2N IOC_PORTCFG_PFUNC2
+#define DIO14_LRFD5  IOC_PORTCFG_PFUNC3
+#define DIO14_T1_F   IOC_PORTCFG_PFUNC4
+
+#define DIO15_GPIO15    IOC_PORTCFG_BASE
+#define DIO15_UART0_RXD IOC_PORTCFG_PFUNC1
+#define DIO15_T2_C0N    IOC_PORTCFG_PFUNC2
+#define DIO15_CKMIN     IOC_PORTCFG_PFUNC3
+
+#define DIO16_GPIO16    IOC_PORTCFG_BASE
+#define DIO16_SPI0_MOSI IOC_PORTCFG_PFUNC1
+#define DIO16_UART0_RXD IOC_PORTCFG_PFUNC2
+#define DIO16_I2C0_SDA  IOC_PORTCFG_PFUNC3
+#define DIO16_T1_C2     IOC_PORTCFG_PFUNC4
+#define DIO16_T1_C0N    IOC_PORTCFG_PFUNC5
+#define DIO16_DTB10     IOC_PORTCFG_DTB
+
+#define DIO17_GPIO17    IOC_PORTCFG_BASE
+#define DIO17_SPI0_SCLK IOC_PORTCFG_PFUNC1
+#define DIO17_UART0_TXD IOC_PORTCFG_PFUNC2
+#define DIO17_I2C0_SCL  IOC_PORTCFG_PFUNC3
+#define DIO17_T1_C1N    IOC_PORTCFG_PFUNC4
+#define DIO17_T0_C2     IOC_PORTCFG_PFUNC5
+#define DIO17_DTB11     IOC_PORTCFG_DTB
+
+#define DIO18_GPIO18    IOC_PORTCFG_BASE
+#define DIO18_T3_C0     IOC_PORTCFG_PFUNC1
+#define DIO18_LPC0      IOC_PORTCFG_PFUNC2
+#define DIO18_UART0_TXD IOC_PORTCFG_PFUNC3
+#define DIO18_SPI0_SCLK IOC_PORTCFG_PFUNC4
+#define DIO18_DTB12     IOC_PORTCFG_DTB
+
+#define DIO19_GPIO19    IOC_PORTCFG_BASE
+#define DIO19_T3_C1     IOC_PORTCFG_PFUNC1
+#define DIO19_T2_PE     IOC_PORTCFG_PFUNC2
+#define DIO19_SPI0_MOSI IOC_PORTCFG_PFUNC4
+#define DIO19_DTB0      IOC_PORTCFG_DTB
+
+#define DIO20_GPIO20    IOC_PORTCFG_BASE
+#define DIO20_LPC0      IOC_PORTCFG_PFUNC1
+#define DIO20_UART0_TXD IOC_PORTCFG_PFUNC2
+#define DIO20_UART0_RXD IOC_PORTCFG_PFUNC3
+#define DIO20_T1_C0     IOC_PORTCFG_PFUNC4
+#define DIO20_SPI0_MISO IOC_PORTCFG_PFUNC5
+#define DIO20_ADC11     IOC_PORTCFG_ANA
+#define DIO20_DTB14     IOC_PORTCFG_DTB
+
+#define DIO21_GPIO21     IOC_PORTCFG_BASE
+#define DIO21_UART0_CTS  IOC_PORTCFG_PFUNC1
+#define DIO21_T1_C1N     IOC_PORTCFG_PFUNC2
+#define DIO21_T0_C1      IOC_PORTCFG_PFUNC3
+#define DIO21_SPI0_MISO  IOC_PORTCFG_PFUNC4
+#define DIO21_LRFD1      IOC_PORTCFG_PFUNC5
+#define DIO21_ADC10_LPCP IOC_PORTCFG_ANA
+#define DIO21_DTB15      IOC_PORTCFG_DTB
+
+#define DIO22_GPIO22    IOC_PORTCFG_BASE
+#define DIO22_T2_C0     IOC_PORTCFG_PFUNC1
+#define DIO22_UART0_RXD IOC_PORTCFG_PFUNC2
+#define DIO22_T3_C1N    IOC_PORTCFG_PFUNC3
+#define DIO22_ADC9      IOC_PORTCFG_ANA
+#define DIO22_DTB1      IOC_PORTCFG_DTB
+
+#define DIO23_GPIO23         IOC_PORTCFG_BASE
+#define DIO23_T2_C1          IOC_PORTCFG_PFUNC1
+#define DIO23_T3_C2N         IOC_PORTCFG_PFUNC3
+#define DIO23_ADC8_LPCP_LPCM IOC_PORTCFG_ANA
+
+#define DIO24_GPIO24         IOC_PORTCFG_BASE
+#define DIO24_SPI0_SCLK      IOC_PORTCFG_PFUNC1
+#define DIO24_T1_C0          IOC_PORTCFG_PFUNC2
+#define DIO24_T3_C0          IOC_PORTCFG_PFUNC3
+#define DIO24_T0_PE          IOC_PORTCFG_PFUNC4
+#define DIO24_I2C0_SCL       IOC_PORTCFG_PFUNC5
+#define DIO24_ADC7_LPCP_LPCM IOC_PORTCFG_ANA
+#define DIO24_DTB5           IOC_PORTCFG_DTB
+
+#define DIO25_GPIO25    IOC_PORTCFG_BASE
+#define DIO25_SPI0_MISO IOC_PORTCFG_PFUNC1
+#define DIO25_I2C0_SCL  IOC_PORTCFG_PFUNC2
+#define DIO25_T2_C2N    IOC_PORTCFG_PFUNC3
+#define DIO25_ADC6      IOC_PORTCFG_ANA
+
+#endif /* CC23X0_PINCTRL_COMMON_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/ch32v20x_30x-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/ch32v20x_30x-pinctrl.h
new file mode 100644
index 00000000000..209381c616f
--- /dev/null
+++ b/include/zephyr/dt-bindings/pinctrl/ch32v20x_30x-pinctrl.h
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2024 MASSDRIVER EI (massdriver.space)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __CH32V20X_V30X_PINCTRL_H__
+#define __CH32V20X_V30X_PINCTRL_H__
+
+#define CH32V20X_V30X_PINMUX_PORT_PA 0
+#define CH32V20X_V30X_PINMUX_PORT_PB 1
+#define CH32V20X_V30X_PINMUX_PORT_PC 2
+#define CH32V20X_V30X_PINMUX_PORT_PD 3
+#define CH32V20X_V30X_PINMUX_PORT_PE 4
+
+/*
+ * Defines the starting bit for the remap field.
+ */
+#define CH32V20X_V30X_PINMUX_SPI1_RM    0
+#define CH32V20X_V30X_PINMUX_I2C1_RM    1
+#define CH32V20X_V30X_PINMUX_USART1_RM  2
+#define CH32V20X_V30X_PINMUX_USART2_RM  3
+#define CH32V20X_V30X_PINMUX_USART3_RM  4
+#define CH32V20X_V30X_PINMUX_TIM1_RM    6
+#define CH32V20X_V30X_PINMUX_TIM2_RM    8
+#define CH32V20X_V30X_PINMUX_TIM3_RM    10
+#define CH32V20X_V30X_PINMUX_TIM4_RM    12
+#define CH32V20X_V30X_PINMUX_CAN1_RM    13
+#define CH32V20X_V30X_PINMUX_PD01_RM    15
+#define CH32V20X_V30X_PINMUX_TIM5CH4_RM 16
+#define CH32V20X_V30X_PINMUX_ETH_RM     21
+#define CH32V20X_V30X_PINMUX_CAN2_RM    22
+#define CH32V20X_V30X_PINMUX_RMII_RM    23
+#define CH32V20X_V30X_PINMUX_SDI_RM     24
+#define CH32V20X_V30X_PINMUX_SPI3_RM    28
+
+#define CH32V20X_V30X_PINMUX_TIM8_RM    (32 + 2)
+#define CH32V20X_V30X_PINMUX_TIM9_RM    (32 + 3)
+#define CH32V20X_V30X_PINMUX_TIM10_RM   (32 + 5)
+#define CH32V20X_V30X_PINMUX_USART4_RM  (32 + 16)
+#define CH32V20X_V30X_PINMUX_USART5_RM  (32 + 18)
+#define CH32V20X_V30X_PINMUX_USART6_RM  (32 + 20)
+#define CH32V20X_V30X_PINMUX_USART7_RM  (32 + 22)
+#define CH32V20X_V30X_PINMUX_USART8_RM  (32 + 24)
+#define CH32V20X_V30X_PINMUX_USART1_RM1 (32 + 26)
+
+/* Port number with 0-4 */
+#define CH32V20X_V30X_PINCTRL_PORT_SHIFT    0
+#define CH32V20X_V30X_PINCTRL_PORT_MASK     GENMASK(2, 0)
+/* Pin number 0-15 */
+#define CH32V20X_V30X_PINCTRL_PIN_SHIFT     3
+#define CH32V20X_V30X_PINCTRL_PIN_MASK      GENMASK(6, 3)
+/* Base remap bit 0-31 */
+#define CH32V20X_V30X_PINCTRL_RM_BASE_SHIFT 7
+#define CH32V20X_V30X_PINCTRL_RM_BASE_MASK  GENMASK(11, 7)
+/* Remap Register ID */
+#define CH32V20X_V30X_PINCTRL_PCFR_ID_SHIFT 12
+#define CH32V20X_V30X_PINCTRL_PCFR_ID_MASK  GENMASK(12, 12)
+/* Function remapping ID 0-3 */
+#define CH32V20X_V30X_PINCTRL_RM_SHIFT      13
+#define CH32V20X_V30X_PINCTRL_RM_MASK       GENMASK(14, 13)
+
+#define CH32V20X_V30X_PINMUX_DEFINE(port, pin, rm, remapping)                                      \
+	((CH32V20X_V30X_PINMUX_PORT_##port << CH32V20X_V30X_PINCTRL_PORT_SHIFT) |                  \
+	 (pin << CH32V20X_V30X_PINCTRL_PIN_SHIFT) |                                                \
+	 (CH32V20X_V30X_PINMUX_##rm##_RM << CH32V20X_V30X_PINCTRL_RM_BASE_SHIFT) |                 \
+	 (remapping << CH32V20X_V30X_PINCTRL_RM_SHIFT))
+
+/* Pin swaps.
+ * Warning: Some of those do not apply to all packages.
+ * Verify using reference manual and use CH32V20X_V30X_PINMUX_DEFINE directly if needed.
+ */
+
+#define USART1_CK_PA8_0   CH32V20X_V30X_PINMUX_DEFINE(PA, 8, USART1, 0)
+#define USART1_CK_PA8_1   CH32V20X_V30X_PINMUX_DEFINE(PA, 8, USART1, 1)
+#define USART1_CK_PA10_2  CH32V20X_V30X_PINMUX_DEFINE(PA, 10, USART1, 2)
+#define USART1_CK_PA5_3   CH32V20X_V30X_PINMUX_DEFINE(PA, 5, USART1, 3)
+#define USART1_TX_PA9_0   CH32V20X_V30X_PINMUX_DEFINE(PA, 9, USART1, 0)
+#define USART1_TX_PB6_1   CH32V20X_V30X_PINMUX_DEFINE(PB, 6, USART1, 1)
+#define USART1_TX_PB15_2  CH32V20X_V30X_PINMUX_DEFINE(PB, 15, USART1, 2)
+#define USART1_TX_PA6_3   CH32V20X_V30X_PINMUX_DEFINE(PA, 6, USART1, 3)
+#define USART1_RX_PA10_0  CH32V20X_V30X_PINMUX_DEFINE(PA, 10, USART1, 0)
+#define USART1_RX_PB7_1   CH32V20X_V30X_PINMUX_DEFINE(PB, 7, USART1, 1)
+#define USART1_RX_PA8_2   CH32V20X_V30X_PINMUX_DEFINE(PA, 8, USART1, 2)
+#define USART1_RX_PA7_3   CH32V20X_V30X_PINMUX_DEFINE(PA, 7, USART1, 3)
+#define USART1_CTS_PA11_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 11, USART1, 0)
+#define USART1_CTS_PA11_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 11, USART1, 1)
+#define USART1_CTS_PA5_2  CH32V20X_V30X_PINMUX_DEFINE(PA, 5, USART1, 2)
+#define USART1_CTS_PC4_3  CH32V20X_V30X_PINMUX_DEFINE(PC, 4, USART1, 3)
+#define USART1_RTS_PA12_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 12, USART1, 0)
+#define USART1_RTS_PA12_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 12, USART1, 1)
+#define USART1_RTS_PA9_2  CH32V20X_V30X_PINMUX_DEFINE(PA, 9, USART1, 2)
+#define USART1_RTS_PC5_3  CH32V20X_V30X_PINMUX_DEFINE(PC, 5, USART1, 3)
+
+#define USART2_CK_PA4_0  CH32V20X_V30X_PINMUX_DEFINE(PA, 4, USART2, 0)
+#define USART2_CK_PD7_1  CH32V20X_V30X_PINMUX_DEFINE(PD, 7, USART2, 1)
+#define USART2_TX_PA2_0  CH32V20X_V30X_PINMUX_DEFINE(PA, 2, USART2, 0)
+#define USART2_TX_PD5_1  CH32V20X_V30X_PINMUX_DEFINE(PD, 5, USART2, 1)
+#define USART2_RX_PA3_0  CH32V20X_V30X_PINMUX_DEFINE(PA, 3, USART2, 0)
+#define USART2_RX_PD6_1  CH32V20X_V30X_PINMUX_DEFINE(PD, 6, USART2, 1)
+#define USART2_CTS_PA0_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 0, USART2, 0)
+#define USART2_CTS_PD3_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 3, USART2, 1)
+#define USART2_RTS_PA1_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 1, USART2, 0)
+#define USART2_RTS_PD4_1 CH32V20X_V30X_PINMUX_DEFINE(PD, 4, USART2, 1)
+
+#define USART3_CK_PB12_0  CH32V20X_V30X_PINMUX_DEFINE(PB, 12, USART3, 0)
+#define USART3_CK_PC12_1  CH32V20X_V30X_PINMUX_DEFINE(PC, 12, USART3, 1)
+#define USART3_CK_PD10_2  CH32V20X_V30X_PINMUX_DEFINE(PD, 10, USART3, 2)
+#define USART3_CK_PD10_3  CH32V20X_V30X_PINMUX_DEFINE(PD, 10, USART3, 3)
+#define USART3_TX_PB10_0  CH32V20X_V30X_PINMUX_DEFINE(PB, 10, USART3, 0)
+#define USART3_TX_PC10_1  CH32V20X_V30X_PINMUX_DEFINE(PC, 10, USART3, 1)
+#define USART3_TX_PA13_2  CH32V20X_V30X_PINMUX_DEFINE(PA, 13, USART3, 2)
+#define USART3_TX_PD8_3   CH32V20X_V30X_PINMUX_DEFINE(PD, 8, USART3, 3)
+#define USART3_RX_PB11_0  CH32V20X_V30X_PINMUX_DEFINE(PB, 11, USART3, 0)
+#define USART3_RX_PC11_1  CH32V20X_V30X_PINMUX_DEFINE(PC, 11, USART3, 1)
+#define USART3_RX_PA14_2  CH32V20X_V30X_PINMUX_DEFINE(PA, 14, USART3, 2)
+#define USART3_RX_PD9_3   CH32V20X_V30X_PINMUX_DEFINE(PD, 9, USART3, 3)
+#define USART3_CTS_PB13_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 13, USART3, 0)
+#define USART3_CTS_PB13_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 13, USART3, 1)
+#define USART3_CTS_PD11_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 11, USART3, 2)
+#define USART3_CTS_PD11_3 CH32V20X_V30X_PINMUX_DEFINE(PD, 11, USART3, 3)
+#define USART3_RTS_PB14_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 14, USART3, 0)
+#define USART3_RTS_PB14_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 14, USART3, 1)
+#define USART3_RTS_PD12_2 CH32V20X_V30X_PINMUX_DEFINE(PD, 12, USART3, 2)
+#define USART3_RTS_PD12_3 CH32V20X_V30X_PINMUX_DEFINE(PD, 12, USART3, 3)
+
+#define USART4_CK_PB2_0   CH32V20X_V30X_PINMUX_DEFINE(PB, 2, USART4, 0)
+#define USART4_CK_PA6_1   CH32V20X_V30X_PINMUX_DEFINE(PA, 6, USART4, 1)
+#define USART4_TX_PB0_0   CH32V20X_V30X_PINMUX_DEFINE(PB, 0, USART4, 0)
+#define USART4_TX_PA5_1   CH32V20X_V30X_PINMUX_DEFINE(PA, 5, USART4, 1)
+#define USART4_RX_PB1_0   CH32V20X_V30X_PINMUX_DEFINE(PB, 1, USART4, 0)
+#define USART4_RX_PB5_1   CH32V20X_V30X_PINMUX_DEFINE(PB, 5, USART4, 1)
+#define USART4_CTS_PB3_0  CH32V20X_V30X_PINMUX_DEFINE(PB, 3, USART4, 0)
+#define USART4_CTS_PA7_1  CH32V20X_V30X_PINMUX_DEFINE(PA, 7, USART4, 1)
+#define USART4_RTS_PB4_0  CH32V20X_V30X_PINMUX_DEFINE(PB, 4, USART4, 0)
+#define USART4_RTS_PA15_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, USART4, 1)
+
+#define USART5_TX_PC12_0 CH32V20X_V30X_PINMUX_DEFINE(PC, 12, USART5, 0)
+#define USART5_TX_PB4_1  CH32V20X_V30X_PINMUX_DEFINE(PB, 4, USART5, 1)
+#define USART5_TX_PE8_2  CH32V20X_V30X_PINMUX_DEFINE(PE, 8, USART5, 2)
+#define USART5_RX_PD2_0  CH32V20X_V30X_PINMUX_DEFINE(PD, 2, USART5, 0)
+#define USART5_RX_PB5_1  CH32V20X_V30X_PINMUX_DEFINE(PB, 5, USART5, 1)
+#define USART5_RX_PE9_2  CH32V20X_V30X_PINMUX_DEFINE(PE, 9, USART5, 2)
+
+#define USART6_TX_PC0_0  CH32V20X_V30X_PINMUX_DEFINE(PC, 0, USART6, 0)
+#define USART6_TX_PB8_1  CH32V20X_V30X_PINMUX_DEFINE(PB, 8, USART6, 1)
+#define USART6_TX_PE10_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 10, USART6, 2)
+#define USART6_RX_PC1_0  CH32V20X_V30X_PINMUX_DEFINE(PC, 1, USART6, 0)
+#define USART6_RX_PB9_1  CH32V20X_V30X_PINMUX_DEFINE(PB, 9, USART6, 1)
+#define USART6_RX_PE11_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 11, USART6, 2)
+
+#define USART7_TX_PC2_0  CH32V20X_V30X_PINMUX_DEFINE(PC, 2, USART7, 0)
+#define USART7_TX_PA6_1  CH32V20X_V30X_PINMUX_DEFINE(PA, 6, USART7, 1)
+#define USART7_TX_PE12_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 12, USART7, 2)
+#define USART7_RX_PC3_0  CH32V20X_V30X_PINMUX_DEFINE(PC, 3, USART7, 0)
+#define USART7_RX_PA7_1  CH32V20X_V30X_PINMUX_DEFINE(PA, 7, USART7, 1)
+#define USART7_RX_PE13_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 13, USART7, 2)
+
+#define USART8_TX_PC4_0  CH32V20X_V30X_PINMUX_DEFINE(PC, 4, USART8, 0)
+#define USART8_TX_PA14_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 14, USART8, 1)
+#define USART8_TX_PE14_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 14, USART8, 2)
+#define USART8_RX_PC5_0  CH32V20X_V30X_PINMUX_DEFINE(PC, 5, USART8, 0)
+#define USART8_RX_PA15_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, USART8, 1)
+#define USART8_RX_PE15_2 CH32V20X_V30X_PINMUX_DEFINE(PE, 15, USART8, 2)
+
+#define SPI1_NSS_PA4_0  CH32V20X_V30X_PINMUX_DEFINE(PA, 4, SPI1, 0)
+#define SPI1_NSS_PA15_1 CH32V20X_V30X_PINMUX_DEFINE(PA, 15, SPI1, 1)
+#define SPI1_SCK_PA5_0  CH32V20X_V30X_PINMUX_DEFINE(PA, 5, SPI1, 0)
+#define SPI1_SCK_PB3_1  CH32V20X_V30X_PINMUX_DEFINE(PB, 3, SPI1, 1)
+#define SPI1_MISO_PA6_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 6, SPI1, 0)
+#define SPI1_MISO_PB4_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 4, SPI1, 1)
+#define SPI1_MOSI_PA7_0 CH32V20X_V30X_PINMUX_DEFINE(PA, 7, SPI1, 0)
+#define SPI1_MOSI_PB5_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 5, SPI1, 1)
+
+#define I2C1_SCL_PB6_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 6, I2C1, 0)
+#define I2C1_SCL_PB8_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 8, I2C1, 1)
+#define I2C1_SDA_PB7_0 CH32V20X_V30X_PINMUX_DEFINE(PB, 7, I2C1, 0)
+#define I2C1_SDA_PB9_1 CH32V20X_V30X_PINMUX_DEFINE(PB, 9, I2C1, 1)
+
+#endif /* __CH32V20X_V30X_PINCTRL_H__ */
diff --git a/include/zephyr/dt-bindings/pinctrl/esp32-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/esp32-pinctrl.h
index 2728fbd06f4..88ae3c10e9c 100644
--- a/include/zephyr/dt-bindings/pinctrl/esp32-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/esp32-pinctrl.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -10,11512 +10,8544 @@
 #define INC_DT_BINDS_PINCTRL_ESP32_PINCTRL_HAL_H_
 
 /* DAC_CH1 */
-#define DAC_CH1_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_DAC1_OUT)
+#define DAC_CH1_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_DAC1_OUT)
 
 /* DAC_CH2 */
-#define DAC_CH2_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_DAC2_OUT)
+#define DAC_CH2_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_DAC2_OUT)
 
 /* I2C0_SCL */
-#define I2C0_SCL_GPIO0 \
-	ESP32_PINMUX(0, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO1 \
-	ESP32_PINMUX(1, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO1 ESP32_PINMUX(1, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO2 \
-	ESP32_PINMUX(2, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO2 ESP32_PINMUX(2, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO3 \
-	ESP32_PINMUX(3, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO3 ESP32_PINMUX(3, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO4 \
-	ESP32_PINMUX(4, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO4 ESP32_PINMUX(4, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO5 \
-	ESP32_PINMUX(5, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO5 ESP32_PINMUX(5, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO6 \
-	ESP32_PINMUX(6, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO6 ESP32_PINMUX(6, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO7 \
-	ESP32_PINMUX(7, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO7 ESP32_PINMUX(7, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO8 \
-	ESP32_PINMUX(8, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO8 ESP32_PINMUX(8, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO9 \
-	ESP32_PINMUX(9, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO9 ESP32_PINMUX(9, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO10 \
-	ESP32_PINMUX(10, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO10 ESP32_PINMUX(10, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO11 \
-	ESP32_PINMUX(11, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO11 ESP32_PINMUX(11, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO12 \
-	ESP32_PINMUX(12, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO12 ESP32_PINMUX(12, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO13 \
-	ESP32_PINMUX(13, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO13 ESP32_PINMUX(13, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO14 \
-	ESP32_PINMUX(14, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO14 ESP32_PINMUX(14, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO15 \
-	ESP32_PINMUX(15, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO15 ESP32_PINMUX(15, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO16 \
-	ESP32_PINMUX(16, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO16 ESP32_PINMUX(16, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO17 \
-	ESP32_PINMUX(17, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO17 ESP32_PINMUX(17, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO18 \
-	ESP32_PINMUX(18, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO18 ESP32_PINMUX(18, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO19 \
-	ESP32_PINMUX(19, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO19 ESP32_PINMUX(19, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO20 \
-	ESP32_PINMUX(20, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO20 ESP32_PINMUX(20, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO21 \
-	ESP32_PINMUX(21, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO21 ESP32_PINMUX(21, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO22 \
-	ESP32_PINMUX(22, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO22 ESP32_PINMUX(22, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO23 \
-	ESP32_PINMUX(23, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO23 ESP32_PINMUX(23, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO25 \
-	ESP32_PINMUX(25, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO25 ESP32_PINMUX(25, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO26 \
-	ESP32_PINMUX(26, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO26 ESP32_PINMUX(26, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO27 \
-	ESP32_PINMUX(27, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO27 ESP32_PINMUX(27, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO32 \
-	ESP32_PINMUX(32, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO32 ESP32_PINMUX(32, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO33 \
-	ESP32_PINMUX(33, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO33 ESP32_PINMUX(33, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
 /* I2C0_SDA */
-#define I2C0_SDA_GPIO0 \
-	ESP32_PINMUX(0, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO1 \
-	ESP32_PINMUX(1, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO1 ESP32_PINMUX(1, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO2 \
-	ESP32_PINMUX(2, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO2 ESP32_PINMUX(2, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO3 \
-	ESP32_PINMUX(3, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO3 ESP32_PINMUX(3, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO4 \
-	ESP32_PINMUX(4, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO4 ESP32_PINMUX(4, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO5 \
-	ESP32_PINMUX(5, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO5 ESP32_PINMUX(5, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO6 \
-	ESP32_PINMUX(6, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO6 ESP32_PINMUX(6, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO7 \
-	ESP32_PINMUX(7, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO7 ESP32_PINMUX(7, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO8 \
-	ESP32_PINMUX(8, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO8 ESP32_PINMUX(8, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO9 \
-	ESP32_PINMUX(9, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO9 ESP32_PINMUX(9, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO10 \
-	ESP32_PINMUX(10, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO10 ESP32_PINMUX(10, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO11 \
-	ESP32_PINMUX(11, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO11 ESP32_PINMUX(11, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO12 \
-	ESP32_PINMUX(12, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO12 ESP32_PINMUX(12, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO13 \
-	ESP32_PINMUX(13, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO13 ESP32_PINMUX(13, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO14 \
-	ESP32_PINMUX(14, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO14 ESP32_PINMUX(14, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO15 \
-	ESP32_PINMUX(15, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO15 ESP32_PINMUX(15, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO16 \
-	ESP32_PINMUX(16, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO16 ESP32_PINMUX(16, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO17 \
-	ESP32_PINMUX(17, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO17 ESP32_PINMUX(17, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO18 \
-	ESP32_PINMUX(18, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO18 ESP32_PINMUX(18, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO19 \
-	ESP32_PINMUX(19, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO19 ESP32_PINMUX(19, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO20 \
-	ESP32_PINMUX(20, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO20 ESP32_PINMUX(20, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO21 \
-	ESP32_PINMUX(21, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO21 ESP32_PINMUX(21, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO22 \
-	ESP32_PINMUX(22, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO22 ESP32_PINMUX(22, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO23 \
-	ESP32_PINMUX(23, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO23 ESP32_PINMUX(23, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO25 \
-	ESP32_PINMUX(25, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO25 ESP32_PINMUX(25, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO26 \
-	ESP32_PINMUX(26, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO26 ESP32_PINMUX(26, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO27 \
-	ESP32_PINMUX(27, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO27 ESP32_PINMUX(27, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO32 \
-	ESP32_PINMUX(32, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO32 ESP32_PINMUX(32, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO33 \
-	ESP32_PINMUX(33, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO33 ESP32_PINMUX(33, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
 /* I2C1_SCL */
-#define I2C1_SCL_GPIO0 \
-	ESP32_PINMUX(0, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO1 \
-	ESP32_PINMUX(1, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO1 ESP32_PINMUX(1, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO2 \
-	ESP32_PINMUX(2, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO2 ESP32_PINMUX(2, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO3 \
-	ESP32_PINMUX(3, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO3 ESP32_PINMUX(3, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO4 \
-	ESP32_PINMUX(4, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO4 ESP32_PINMUX(4, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO5 \
-	ESP32_PINMUX(5, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO5 ESP32_PINMUX(5, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO6 \
-	ESP32_PINMUX(6, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO6 ESP32_PINMUX(6, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO7 \
-	ESP32_PINMUX(7, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO7 ESP32_PINMUX(7, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO8 \
-	ESP32_PINMUX(8, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO8 ESP32_PINMUX(8, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO9 \
-	ESP32_PINMUX(9, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO9 ESP32_PINMUX(9, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO10 \
-	ESP32_PINMUX(10, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO10 ESP32_PINMUX(10, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO11 \
-	ESP32_PINMUX(11, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO11 ESP32_PINMUX(11, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO12 \
-	ESP32_PINMUX(12, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO12 ESP32_PINMUX(12, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO13 \
-	ESP32_PINMUX(13, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO13 ESP32_PINMUX(13, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO14 \
-	ESP32_PINMUX(14, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO14 ESP32_PINMUX(14, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO15 \
-	ESP32_PINMUX(15, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO15 ESP32_PINMUX(15, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO16 \
-	ESP32_PINMUX(16, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO16 ESP32_PINMUX(16, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO17 \
-	ESP32_PINMUX(17, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO17 ESP32_PINMUX(17, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO18 \
-	ESP32_PINMUX(18, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO18 ESP32_PINMUX(18, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO19 \
-	ESP32_PINMUX(19, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO19 ESP32_PINMUX(19, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO20 \
-	ESP32_PINMUX(20, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO20 ESP32_PINMUX(20, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO21 \
-	ESP32_PINMUX(21, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO21 ESP32_PINMUX(21, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO22 \
-	ESP32_PINMUX(22, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO22 ESP32_PINMUX(22, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO23 \
-	ESP32_PINMUX(23, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO23 ESP32_PINMUX(23, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO25 \
-	ESP32_PINMUX(25, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO25 ESP32_PINMUX(25, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO26 \
-	ESP32_PINMUX(26, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO26 ESP32_PINMUX(26, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO27 \
-	ESP32_PINMUX(27, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO27 ESP32_PINMUX(27, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO32 \
-	ESP32_PINMUX(32, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO32 ESP32_PINMUX(32, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO33 \
-	ESP32_PINMUX(33, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO33 ESP32_PINMUX(33, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
 /* I2C1_SDA */
-#define I2C1_SDA_GPIO0 \
-	ESP32_PINMUX(0, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO1 \
-	ESP32_PINMUX(1, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO1 ESP32_PINMUX(1, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO2 \
-	ESP32_PINMUX(2, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO2 ESP32_PINMUX(2, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO3 \
-	ESP32_PINMUX(3, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO3 ESP32_PINMUX(3, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO4 \
-	ESP32_PINMUX(4, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO4 ESP32_PINMUX(4, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO5 \
-	ESP32_PINMUX(5, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO5 ESP32_PINMUX(5, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO6 \
-	ESP32_PINMUX(6, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO6 ESP32_PINMUX(6, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO7 \
-	ESP32_PINMUX(7, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO7 ESP32_PINMUX(7, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO8 \
-	ESP32_PINMUX(8, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO8 ESP32_PINMUX(8, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO9 \
-	ESP32_PINMUX(9, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO9 ESP32_PINMUX(9, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO10 \
-	ESP32_PINMUX(10, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO10 ESP32_PINMUX(10, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO11 \
-	ESP32_PINMUX(11, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO11 ESP32_PINMUX(11, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO12 \
-	ESP32_PINMUX(12, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO12 ESP32_PINMUX(12, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO13 \
-	ESP32_PINMUX(13, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO13 ESP32_PINMUX(13, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO14 \
-	ESP32_PINMUX(14, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO14 ESP32_PINMUX(14, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO15 \
-	ESP32_PINMUX(15, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO15 ESP32_PINMUX(15, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO16 \
-	ESP32_PINMUX(16, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO16 ESP32_PINMUX(16, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO17 \
-	ESP32_PINMUX(17, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO17 ESP32_PINMUX(17, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO18 \
-	ESP32_PINMUX(18, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO18 ESP32_PINMUX(18, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO19 \
-	ESP32_PINMUX(19, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO19 ESP32_PINMUX(19, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO20 \
-	ESP32_PINMUX(20, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO20 ESP32_PINMUX(20, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO21 \
-	ESP32_PINMUX(21, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO21 ESP32_PINMUX(21, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO22 \
-	ESP32_PINMUX(22, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO22 ESP32_PINMUX(22, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO23 \
-	ESP32_PINMUX(23, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO23 ESP32_PINMUX(23, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO25 \
-	ESP32_PINMUX(25, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO25 ESP32_PINMUX(25, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO26 \
-	ESP32_PINMUX(26, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO26 ESP32_PINMUX(26, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO27 \
-	ESP32_PINMUX(27, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO27 ESP32_PINMUX(27, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO32 \
-	ESP32_PINMUX(32, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO32 ESP32_PINMUX(32, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO33 \
-	ESP32_PINMUX(33, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO33 ESP32_PINMUX(33, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+
+/* I2S0_I_BCK */
+#define I2S0_I_BCK_GPIO0 ESP32_PINMUX(0, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO1 ESP32_PINMUX(1, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO2 ESP32_PINMUX(2, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO3 ESP32_PINMUX(3, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO4 ESP32_PINMUX(4, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO5 ESP32_PINMUX(5, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO6 ESP32_PINMUX(6, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO7 ESP32_PINMUX(7, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO8 ESP32_PINMUX(8, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO9 ESP32_PINMUX(9, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO10 ESP32_PINMUX(10, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO11 ESP32_PINMUX(11, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO12 ESP32_PINMUX(12, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO13 ESP32_PINMUX(13, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO14 ESP32_PINMUX(14, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO15 ESP32_PINMUX(15, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO16 ESP32_PINMUX(16, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO17 ESP32_PINMUX(17, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO18 ESP32_PINMUX(18, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO19 ESP32_PINMUX(19, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO20 ESP32_PINMUX(20, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO21 ESP32_PINMUX(21, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO22 ESP32_PINMUX(22, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO23 ESP32_PINMUX(23, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO25 ESP32_PINMUX(25, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO26 ESP32_PINMUX(26, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO27 ESP32_PINMUX(27, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO32 ESP32_PINMUX(32, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO33 ESP32_PINMUX(33, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO34 ESP32_PINMUX(34, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO35 ESP32_PINMUX(35, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO36 ESP32_PINMUX(36, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO37 ESP32_PINMUX(37, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO38 ESP32_PINMUX(38, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO39 ESP32_PINMUX(39, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+/* I2S0_I_SD */
+#define I2S0_I_SD_GPIO0 ESP32_PINMUX(0, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO1 ESP32_PINMUX(1, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO2 ESP32_PINMUX(2, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO3 ESP32_PINMUX(3, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO4 ESP32_PINMUX(4, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO5 ESP32_PINMUX(5, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO6 ESP32_PINMUX(6, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO7 ESP32_PINMUX(7, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO8 ESP32_PINMUX(8, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO9 ESP32_PINMUX(9, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO10 ESP32_PINMUX(10, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO11 ESP32_PINMUX(11, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO12 ESP32_PINMUX(12, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO13 ESP32_PINMUX(13, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO14 ESP32_PINMUX(14, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO15 ESP32_PINMUX(15, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO16 ESP32_PINMUX(16, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO17 ESP32_PINMUX(17, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO18 ESP32_PINMUX(18, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO19 ESP32_PINMUX(19, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO20 ESP32_PINMUX(20, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO21 ESP32_PINMUX(21, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO22 ESP32_PINMUX(22, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO23 ESP32_PINMUX(23, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO25 ESP32_PINMUX(25, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO26 ESP32_PINMUX(26, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO27 ESP32_PINMUX(27, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO32 ESP32_PINMUX(32, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO33 ESP32_PINMUX(33, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO34 ESP32_PINMUX(34, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO35 ESP32_PINMUX(35, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO36 ESP32_PINMUX(36, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO37 ESP32_PINMUX(37, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO38 ESP32_PINMUX(38, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO39 ESP32_PINMUX(39, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+/* I2S0_I_WS */
+#define I2S0_I_WS_GPIO0 ESP32_PINMUX(0, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO1 ESP32_PINMUX(1, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO2 ESP32_PINMUX(2, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO3 ESP32_PINMUX(3, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO4 ESP32_PINMUX(4, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO5 ESP32_PINMUX(5, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO6 ESP32_PINMUX(6, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO7 ESP32_PINMUX(7, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO8 ESP32_PINMUX(8, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO9 ESP32_PINMUX(9, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO10 ESP32_PINMUX(10, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO11 ESP32_PINMUX(11, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO12 ESP32_PINMUX(12, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO13 ESP32_PINMUX(13, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO14 ESP32_PINMUX(14, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO15 ESP32_PINMUX(15, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO16 ESP32_PINMUX(16, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO17 ESP32_PINMUX(17, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO18 ESP32_PINMUX(18, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO19 ESP32_PINMUX(19, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO20 ESP32_PINMUX(20, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO21 ESP32_PINMUX(21, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO22 ESP32_PINMUX(22, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO23 ESP32_PINMUX(23, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO25 ESP32_PINMUX(25, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO26 ESP32_PINMUX(26, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO27 ESP32_PINMUX(27, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO32 ESP32_PINMUX(32, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO33 ESP32_PINMUX(33, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO34 ESP32_PINMUX(34, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO35 ESP32_PINMUX(35, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO36 ESP32_PINMUX(36, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO37 ESP32_PINMUX(37, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO38 ESP32_PINMUX(38, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO39 ESP32_PINMUX(39, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+/* I2S0_O_BCK */
+#define I2S0_O_BCK_GPIO0 ESP32_PINMUX(0, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO1 ESP32_PINMUX(1, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO2 ESP32_PINMUX(2, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO3 ESP32_PINMUX(3, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO4 ESP32_PINMUX(4, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO5 ESP32_PINMUX(5, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO6 ESP32_PINMUX(6, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO7 ESP32_PINMUX(7, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO8 ESP32_PINMUX(8, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO9 ESP32_PINMUX(9, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO10 ESP32_PINMUX(10, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO11 ESP32_PINMUX(11, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO12 ESP32_PINMUX(12, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO13 ESP32_PINMUX(13, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO14 ESP32_PINMUX(14, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO15 ESP32_PINMUX(15, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO16 ESP32_PINMUX(16, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO17 ESP32_PINMUX(17, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO18 ESP32_PINMUX(18, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO19 ESP32_PINMUX(19, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO20 ESP32_PINMUX(20, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO21 ESP32_PINMUX(21, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO22 ESP32_PINMUX(22, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO23 ESP32_PINMUX(23, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO25 ESP32_PINMUX(25, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO26 ESP32_PINMUX(26, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO27 ESP32_PINMUX(27, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO32 ESP32_PINMUX(32, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO33 ESP32_PINMUX(33, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO34 ESP32_PINMUX(34, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO35 ESP32_PINMUX(35, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO36 ESP32_PINMUX(36, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO37 ESP32_PINMUX(37, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO38 ESP32_PINMUX(38, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO39 ESP32_PINMUX(39, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+/* I2S0_O_SD */
+#define I2S0_O_SD_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+/* I2S0_O_WS */
+#define I2S0_O_WS_GPIO0 ESP32_PINMUX(0, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO1 ESP32_PINMUX(1, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO2 ESP32_PINMUX(2, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO3 ESP32_PINMUX(3, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO4 ESP32_PINMUX(4, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO5 ESP32_PINMUX(5, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO6 ESP32_PINMUX(6, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO7 ESP32_PINMUX(7, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO8 ESP32_PINMUX(8, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO9 ESP32_PINMUX(9, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO10 ESP32_PINMUX(10, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO11 ESP32_PINMUX(11, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO12 ESP32_PINMUX(12, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO13 ESP32_PINMUX(13, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO14 ESP32_PINMUX(14, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO15 ESP32_PINMUX(15, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO16 ESP32_PINMUX(16, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO17 ESP32_PINMUX(17, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO18 ESP32_PINMUX(18, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO19 ESP32_PINMUX(19, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO20 ESP32_PINMUX(20, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO21 ESP32_PINMUX(21, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO22 ESP32_PINMUX(22, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO23 ESP32_PINMUX(23, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO25 ESP32_PINMUX(25, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO26 ESP32_PINMUX(26, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO27 ESP32_PINMUX(27, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO32 ESP32_PINMUX(32, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO33 ESP32_PINMUX(33, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO34 ESP32_PINMUX(34, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO35 ESP32_PINMUX(35, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO36 ESP32_PINMUX(36, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO37 ESP32_PINMUX(37, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO38 ESP32_PINMUX(38, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO39 ESP32_PINMUX(39, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+/* I2S1_I_BCK */
+#define I2S1_I_BCK_GPIO0 ESP32_PINMUX(0, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO1 ESP32_PINMUX(1, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO2 ESP32_PINMUX(2, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO3 ESP32_PINMUX(3, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO4 ESP32_PINMUX(4, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO5 ESP32_PINMUX(5, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO6 ESP32_PINMUX(6, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO7 ESP32_PINMUX(7, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO8 ESP32_PINMUX(8, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO9 ESP32_PINMUX(9, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO10 ESP32_PINMUX(10, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO11 ESP32_PINMUX(11, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO12 ESP32_PINMUX(12, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO13 ESP32_PINMUX(13, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO14 ESP32_PINMUX(14, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO15 ESP32_PINMUX(15, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO16 ESP32_PINMUX(16, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO17 ESP32_PINMUX(17, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO18 ESP32_PINMUX(18, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO19 ESP32_PINMUX(19, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO20 ESP32_PINMUX(20, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO21 ESP32_PINMUX(21, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO22 ESP32_PINMUX(22, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO23 ESP32_PINMUX(23, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO25 ESP32_PINMUX(25, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO26 ESP32_PINMUX(26, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO27 ESP32_PINMUX(27, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO32 ESP32_PINMUX(32, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO33 ESP32_PINMUX(33, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO34 ESP32_PINMUX(34, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO35 ESP32_PINMUX(35, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO36 ESP32_PINMUX(36, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO37 ESP32_PINMUX(37, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO38 ESP32_PINMUX(38, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+#define I2S1_I_BCK_GPIO39 ESP32_PINMUX(39, ESP_I2S1I_BCK_IN, ESP_I2S1I_BCK_OUT)
+
+/* I2S1_I_SD */
+#define I2S1_I_SD_GPIO0 ESP32_PINMUX(0, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO1 ESP32_PINMUX(1, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO2 ESP32_PINMUX(2, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO3 ESP32_PINMUX(3, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO4 ESP32_PINMUX(4, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO5 ESP32_PINMUX(5, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO6 ESP32_PINMUX(6, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO7 ESP32_PINMUX(7, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO8 ESP32_PINMUX(8, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO9 ESP32_PINMUX(9, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO10 ESP32_PINMUX(10, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO11 ESP32_PINMUX(11, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO12 ESP32_PINMUX(12, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO13 ESP32_PINMUX(13, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO14 ESP32_PINMUX(14, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO15 ESP32_PINMUX(15, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO16 ESP32_PINMUX(16, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO17 ESP32_PINMUX(17, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO18 ESP32_PINMUX(18, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO19 ESP32_PINMUX(19, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO20 ESP32_PINMUX(20, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO21 ESP32_PINMUX(21, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO22 ESP32_PINMUX(22, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO23 ESP32_PINMUX(23, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO25 ESP32_PINMUX(25, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO26 ESP32_PINMUX(26, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO27 ESP32_PINMUX(27, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO32 ESP32_PINMUX(32, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO33 ESP32_PINMUX(33, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO34 ESP32_PINMUX(34, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO35 ESP32_PINMUX(35, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO36 ESP32_PINMUX(36, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO37 ESP32_PINMUX(37, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO38 ESP32_PINMUX(38, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+#define I2S1_I_SD_GPIO39 ESP32_PINMUX(39, ESP_I2S1I_DATA_IN15, ESP_NOSIG)
+
+/* I2S1_I_WS */
+#define I2S1_I_WS_GPIO0 ESP32_PINMUX(0, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO1 ESP32_PINMUX(1, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO2 ESP32_PINMUX(2, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO3 ESP32_PINMUX(3, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO4 ESP32_PINMUX(4, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO5 ESP32_PINMUX(5, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO6 ESP32_PINMUX(6, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO7 ESP32_PINMUX(7, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO8 ESP32_PINMUX(8, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO9 ESP32_PINMUX(9, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO10 ESP32_PINMUX(10, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO11 ESP32_PINMUX(11, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO12 ESP32_PINMUX(12, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO13 ESP32_PINMUX(13, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO14 ESP32_PINMUX(14, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO15 ESP32_PINMUX(15, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO16 ESP32_PINMUX(16, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO17 ESP32_PINMUX(17, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO18 ESP32_PINMUX(18, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO19 ESP32_PINMUX(19, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO20 ESP32_PINMUX(20, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO21 ESP32_PINMUX(21, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO22 ESP32_PINMUX(22, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO23 ESP32_PINMUX(23, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO25 ESP32_PINMUX(25, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO26 ESP32_PINMUX(26, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO27 ESP32_PINMUX(27, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO32 ESP32_PINMUX(32, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO33 ESP32_PINMUX(33, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO34 ESP32_PINMUX(34, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO35 ESP32_PINMUX(35, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO36 ESP32_PINMUX(36, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO37 ESP32_PINMUX(37, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO38 ESP32_PINMUX(38, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+#define I2S1_I_WS_GPIO39 ESP32_PINMUX(39, ESP_I2S1I_WS_IN, ESP_I2S1I_WS_OUT)
+
+/* I2S1_O_BCK */
+#define I2S1_O_BCK_GPIO0 ESP32_PINMUX(0, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO1 ESP32_PINMUX(1, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO2 ESP32_PINMUX(2, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO3 ESP32_PINMUX(3, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO4 ESP32_PINMUX(4, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO5 ESP32_PINMUX(5, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO6 ESP32_PINMUX(6, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO7 ESP32_PINMUX(7, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO8 ESP32_PINMUX(8, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO9 ESP32_PINMUX(9, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO10 ESP32_PINMUX(10, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO11 ESP32_PINMUX(11, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO12 ESP32_PINMUX(12, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO13 ESP32_PINMUX(13, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO14 ESP32_PINMUX(14, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO15 ESP32_PINMUX(15, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO16 ESP32_PINMUX(16, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO17 ESP32_PINMUX(17, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO18 ESP32_PINMUX(18, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO19 ESP32_PINMUX(19, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO20 ESP32_PINMUX(20, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO21 ESP32_PINMUX(21, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO22 ESP32_PINMUX(22, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO23 ESP32_PINMUX(23, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO25 ESP32_PINMUX(25, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO26 ESP32_PINMUX(26, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO27 ESP32_PINMUX(27, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO32 ESP32_PINMUX(32, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO33 ESP32_PINMUX(33, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO34 ESP32_PINMUX(34, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO35 ESP32_PINMUX(35, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO36 ESP32_PINMUX(36, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO37 ESP32_PINMUX(37, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO38 ESP32_PINMUX(38, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+#define I2S1_O_BCK_GPIO39 ESP32_PINMUX(39, ESP_I2S1O_BCK_IN, ESP_I2S1O_BCK_OUT)
+
+/* I2S1_O_SD */
+#define I2S1_O_SD_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+#define I2S1_O_SD_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_I2S1O_DATA_OUT23)
+
+/* I2S1_O_WS */
+#define I2S1_O_WS_GPIO0 ESP32_PINMUX(0, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO1 ESP32_PINMUX(1, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO2 ESP32_PINMUX(2, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO3 ESP32_PINMUX(3, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO4 ESP32_PINMUX(4, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO5 ESP32_PINMUX(5, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO6 ESP32_PINMUX(6, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO7 ESP32_PINMUX(7, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO8 ESP32_PINMUX(8, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO9 ESP32_PINMUX(9, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO10 ESP32_PINMUX(10, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO11 ESP32_PINMUX(11, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO12 ESP32_PINMUX(12, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO13 ESP32_PINMUX(13, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO14 ESP32_PINMUX(14, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO15 ESP32_PINMUX(15, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO16 ESP32_PINMUX(16, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO17 ESP32_PINMUX(17, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO18 ESP32_PINMUX(18, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO19 ESP32_PINMUX(19, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO20 ESP32_PINMUX(20, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO21 ESP32_PINMUX(21, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO22 ESP32_PINMUX(22, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO23 ESP32_PINMUX(23, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO25 ESP32_PINMUX(25, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO26 ESP32_PINMUX(26, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO27 ESP32_PINMUX(27, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO32 ESP32_PINMUX(32, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO33 ESP32_PINMUX(33, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO34 ESP32_PINMUX(34, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO35 ESP32_PINMUX(35, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO36 ESP32_PINMUX(36, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO37 ESP32_PINMUX(37, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO38 ESP32_PINMUX(38, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
+
+#define I2S1_O_WS_GPIO39 ESP32_PINMUX(39, ESP_I2S1O_WS_IN, ESP_I2S1O_WS_OUT)
 
 /* LEDC_CH0 */
-#define LEDC_CH0_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
 /* LEDC_CH1 */
-#define LEDC_CH1_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
 /* LEDC_CH10 */
-#define LEDC_CH10_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
-#define LEDC_CH10_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
+#define LEDC_CH10_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT2)
 
 /* LEDC_CH11 */
-#define LEDC_CH11_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
-#define LEDC_CH11_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
+#define LEDC_CH11_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT3)
 
 /* LEDC_CH12 */
-#define LEDC_CH12_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
-#define LEDC_CH12_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
+#define LEDC_CH12_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT4)
 
 /* LEDC_CH13 */
-#define LEDC_CH13_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
-#define LEDC_CH13_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
+#define LEDC_CH13_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT5)
 
 /* LEDC_CH14 */
-#define LEDC_CH14_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
-#define LEDC_CH14_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
+#define LEDC_CH14_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT6)
 
 /* LEDC_CH15 */
-#define LEDC_CH15_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
-#define LEDC_CH15_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
+#define LEDC_CH15_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT7)
 
 /* LEDC_CH2 */
-#define LEDC_CH2_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
 /* LEDC_CH3 */
-#define LEDC_CH3_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
 /* LEDC_CH4 */
-#define LEDC_CH4_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
 /* LEDC_CH5 */
-#define LEDC_CH5_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
 /* LEDC_CH6 */
-#define LEDC_CH6_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
 /* LEDC_CH7 */
-#define LEDC_CH7_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
 /* LEDC_CH8 */
-#define LEDC_CH8_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
-#define LEDC_CH8_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
+#define LEDC_CH8_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT0)
 
 /* LEDC_CH9 */
-#define LEDC_CH9_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
-#define LEDC_CH9_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
+#define LEDC_CH9_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_HS_SIG_OUT1)
 
 /* MCPWM0_CAP0 */
-#define MCPWM0_CAP0_GPIO0 \
-	ESP32_PINMUX(0, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO0 ESP32_PINMUX(0, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO1 \
-	ESP32_PINMUX(1, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO1 ESP32_PINMUX(1, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO2 \
-	ESP32_PINMUX(2, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO2 ESP32_PINMUX(2, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO3 \
-	ESP32_PINMUX(3, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO3 ESP32_PINMUX(3, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO4 \
-	ESP32_PINMUX(4, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO4 ESP32_PINMUX(4, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO5 \
-	ESP32_PINMUX(5, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO5 ESP32_PINMUX(5, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO6 \
-	ESP32_PINMUX(6, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO6 ESP32_PINMUX(6, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO7 \
-	ESP32_PINMUX(7, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO7 ESP32_PINMUX(7, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO8 \
-	ESP32_PINMUX(8, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO8 ESP32_PINMUX(8, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO9 \
-	ESP32_PINMUX(9, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO9 ESP32_PINMUX(9, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO10 \
-	ESP32_PINMUX(10, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO10 ESP32_PINMUX(10, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO11 \
-	ESP32_PINMUX(11, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO11 ESP32_PINMUX(11, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO12 \
-	ESP32_PINMUX(12, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO12 ESP32_PINMUX(12, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO13 \
-	ESP32_PINMUX(13, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO13 ESP32_PINMUX(13, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO14 \
-	ESP32_PINMUX(14, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO14 ESP32_PINMUX(14, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO15 \
-	ESP32_PINMUX(15, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO15 ESP32_PINMUX(15, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO16 \
-	ESP32_PINMUX(16, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO16 ESP32_PINMUX(16, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO17 \
-	ESP32_PINMUX(17, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO17 ESP32_PINMUX(17, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO18 \
-	ESP32_PINMUX(18, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO18 ESP32_PINMUX(18, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO19 \
-	ESP32_PINMUX(19, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO19 ESP32_PINMUX(19, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO20 \
-	ESP32_PINMUX(20, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO20 ESP32_PINMUX(20, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO21 \
-	ESP32_PINMUX(21, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO21 ESP32_PINMUX(21, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO22 \
-	ESP32_PINMUX(22, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO22 ESP32_PINMUX(22, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO23 \
-	ESP32_PINMUX(23, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO23 ESP32_PINMUX(23, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO25 \
-	ESP32_PINMUX(25, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO25 ESP32_PINMUX(25, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO26 \
-	ESP32_PINMUX(26, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO26 ESP32_PINMUX(26, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO27 \
-	ESP32_PINMUX(27, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO27 ESP32_PINMUX(27, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO32 \
-	ESP32_PINMUX(32, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO32 ESP32_PINMUX(32, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO33 \
-	ESP32_PINMUX(33, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO33 ESP32_PINMUX(33, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO34 \
-	ESP32_PINMUX(34, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO34 ESP32_PINMUX(34, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO35 \
-	ESP32_PINMUX(35, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO35 ESP32_PINMUX(35, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO36 \
-	ESP32_PINMUX(36, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO36 ESP32_PINMUX(36, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO37 \
-	ESP32_PINMUX(37, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO37 ESP32_PINMUX(37, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO38 \
-	ESP32_PINMUX(38, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO38 ESP32_PINMUX(38, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP0_GPIO39 \
-	ESP32_PINMUX(39, ESP_PWM0_CAP0_IN, ESP_NOSIG)
+#define MCPWM0_CAP0_GPIO39 ESP32_PINMUX(39, ESP_PWM0_CAP0_IN, ESP_NOSIG)
 
 /* MCPWM0_CAP1 */
-#define MCPWM0_CAP1_GPIO0 \
-	ESP32_PINMUX(0, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO0 ESP32_PINMUX(0, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO1 \
-	ESP32_PINMUX(1, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO1 ESP32_PINMUX(1, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO2 \
-	ESP32_PINMUX(2, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO2 ESP32_PINMUX(2, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO3 \
-	ESP32_PINMUX(3, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO3 ESP32_PINMUX(3, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO4 \
-	ESP32_PINMUX(4, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO4 ESP32_PINMUX(4, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO5 \
-	ESP32_PINMUX(5, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO5 ESP32_PINMUX(5, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO6 \
-	ESP32_PINMUX(6, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO6 ESP32_PINMUX(6, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO7 \
-	ESP32_PINMUX(7, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO7 ESP32_PINMUX(7, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO8 \
-	ESP32_PINMUX(8, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO8 ESP32_PINMUX(8, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO9 \
-	ESP32_PINMUX(9, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO9 ESP32_PINMUX(9, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO10 \
-	ESP32_PINMUX(10, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO10 ESP32_PINMUX(10, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO11 \
-	ESP32_PINMUX(11, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO11 ESP32_PINMUX(11, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO12 \
-	ESP32_PINMUX(12, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO12 ESP32_PINMUX(12, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO13 \
-	ESP32_PINMUX(13, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO13 ESP32_PINMUX(13, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO14 \
-	ESP32_PINMUX(14, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO14 ESP32_PINMUX(14, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO15 \
-	ESP32_PINMUX(15, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO15 ESP32_PINMUX(15, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO16 \
-	ESP32_PINMUX(16, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO16 ESP32_PINMUX(16, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO17 \
-	ESP32_PINMUX(17, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO17 ESP32_PINMUX(17, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO18 \
-	ESP32_PINMUX(18, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO18 ESP32_PINMUX(18, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO19 \
-	ESP32_PINMUX(19, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO19 ESP32_PINMUX(19, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO20 \
-	ESP32_PINMUX(20, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO20 ESP32_PINMUX(20, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO21 \
-	ESP32_PINMUX(21, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO21 ESP32_PINMUX(21, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO22 \
-	ESP32_PINMUX(22, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO22 ESP32_PINMUX(22, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO23 \
-	ESP32_PINMUX(23, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO23 ESP32_PINMUX(23, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO25 \
-	ESP32_PINMUX(25, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO25 ESP32_PINMUX(25, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO26 \
-	ESP32_PINMUX(26, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO26 ESP32_PINMUX(26, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO27 \
-	ESP32_PINMUX(27, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO27 ESP32_PINMUX(27, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO32 \
-	ESP32_PINMUX(32, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO32 ESP32_PINMUX(32, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO33 \
-	ESP32_PINMUX(33, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO33 ESP32_PINMUX(33, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO34 \
-	ESP32_PINMUX(34, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO34 ESP32_PINMUX(34, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO35 \
-	ESP32_PINMUX(35, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO35 ESP32_PINMUX(35, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO36 \
-	ESP32_PINMUX(36, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO36 ESP32_PINMUX(36, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO37 \
-	ESP32_PINMUX(37, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO37 ESP32_PINMUX(37, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO38 \
-	ESP32_PINMUX(38, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO38 ESP32_PINMUX(38, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP1_GPIO39 \
-	ESP32_PINMUX(39, ESP_PWM0_CAP1_IN, ESP_NOSIG)
+#define MCPWM0_CAP1_GPIO39 ESP32_PINMUX(39, ESP_PWM0_CAP1_IN, ESP_NOSIG)
 
 /* MCPWM0_CAP2 */
-#define MCPWM0_CAP2_GPIO0 \
-	ESP32_PINMUX(0, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO0 ESP32_PINMUX(0, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO1 \
-	ESP32_PINMUX(1, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO1 ESP32_PINMUX(1, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO2 \
-	ESP32_PINMUX(2, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO2 ESP32_PINMUX(2, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO3 \
-	ESP32_PINMUX(3, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO3 ESP32_PINMUX(3, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO4 \
-	ESP32_PINMUX(4, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO4 ESP32_PINMUX(4, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO5 \
-	ESP32_PINMUX(5, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO5 ESP32_PINMUX(5, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO6 \
-	ESP32_PINMUX(6, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO6 ESP32_PINMUX(6, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO7 \
-	ESP32_PINMUX(7, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO7 ESP32_PINMUX(7, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO8 \
-	ESP32_PINMUX(8, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO8 ESP32_PINMUX(8, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO9 \
-	ESP32_PINMUX(9, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO9 ESP32_PINMUX(9, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO10 \
-	ESP32_PINMUX(10, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO10 ESP32_PINMUX(10, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO11 \
-	ESP32_PINMUX(11, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO11 ESP32_PINMUX(11, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO12 \
-	ESP32_PINMUX(12, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO12 ESP32_PINMUX(12, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO13 \
-	ESP32_PINMUX(13, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO13 ESP32_PINMUX(13, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO14 \
-	ESP32_PINMUX(14, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO14 ESP32_PINMUX(14, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO15 \
-	ESP32_PINMUX(15, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO15 ESP32_PINMUX(15, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO16 \
-	ESP32_PINMUX(16, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO16 ESP32_PINMUX(16, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO17 \
-	ESP32_PINMUX(17, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO17 ESP32_PINMUX(17, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO18 \
-	ESP32_PINMUX(18, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO18 ESP32_PINMUX(18, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO19 \
-	ESP32_PINMUX(19, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO19 ESP32_PINMUX(19, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO20 \
-	ESP32_PINMUX(20, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO20 ESP32_PINMUX(20, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO21 \
-	ESP32_PINMUX(21, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO21 ESP32_PINMUX(21, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO22 \
-	ESP32_PINMUX(22, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO22 ESP32_PINMUX(22, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO23 \
-	ESP32_PINMUX(23, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO23 ESP32_PINMUX(23, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO25 \
-	ESP32_PINMUX(25, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO25 ESP32_PINMUX(25, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO26 \
-	ESP32_PINMUX(26, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO26 ESP32_PINMUX(26, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO27 \
-	ESP32_PINMUX(27, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO27 ESP32_PINMUX(27, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO32 \
-	ESP32_PINMUX(32, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO32 ESP32_PINMUX(32, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO33 \
-	ESP32_PINMUX(33, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO33 ESP32_PINMUX(33, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO34 \
-	ESP32_PINMUX(34, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO34 ESP32_PINMUX(34, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO35 \
-	ESP32_PINMUX(35, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO35 ESP32_PINMUX(35, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO36 \
-	ESP32_PINMUX(36, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO36 ESP32_PINMUX(36, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO37 \
-	ESP32_PINMUX(37, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO37 ESP32_PINMUX(37, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO38 \
-	ESP32_PINMUX(38, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO38 ESP32_PINMUX(38, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM0_CAP2_GPIO39 \
-	ESP32_PINMUX(39, ESP_PWM0_CAP2_IN, ESP_NOSIG)
+#define MCPWM0_CAP2_GPIO39 ESP32_PINMUX(39, ESP_PWM0_CAP2_IN, ESP_NOSIG)
 
 /* MCPWM0_FAULT0 */
-#define MCPWM0_FAULT0_GPIO0 \
-	ESP32_PINMUX(0, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO0 ESP32_PINMUX(0, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO1 \
-	ESP32_PINMUX(1, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO1 ESP32_PINMUX(1, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO2 \
-	ESP32_PINMUX(2, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO2 ESP32_PINMUX(2, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO3 \
-	ESP32_PINMUX(3, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO3 ESP32_PINMUX(3, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO4 \
-	ESP32_PINMUX(4, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO4 ESP32_PINMUX(4, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO5 \
-	ESP32_PINMUX(5, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO5 ESP32_PINMUX(5, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO6 \
-	ESP32_PINMUX(6, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO6 ESP32_PINMUX(6, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO7 \
-	ESP32_PINMUX(7, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO7 ESP32_PINMUX(7, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO8 \
-	ESP32_PINMUX(8, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO8 ESP32_PINMUX(8, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO9 \
-	ESP32_PINMUX(9, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO9 ESP32_PINMUX(9, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO10 \
-	ESP32_PINMUX(10, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO10 ESP32_PINMUX(10, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO11 \
-	ESP32_PINMUX(11, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO11 ESP32_PINMUX(11, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO12 \
-	ESP32_PINMUX(12, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO12 ESP32_PINMUX(12, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO13 \
-	ESP32_PINMUX(13, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO13 ESP32_PINMUX(13, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO14 \
-	ESP32_PINMUX(14, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO14 ESP32_PINMUX(14, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO15 \
-	ESP32_PINMUX(15, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO15 ESP32_PINMUX(15, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO16 \
-	ESP32_PINMUX(16, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO16 ESP32_PINMUX(16, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO17 \
-	ESP32_PINMUX(17, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO17 ESP32_PINMUX(17, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO18 \
-	ESP32_PINMUX(18, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO18 ESP32_PINMUX(18, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO19 \
-	ESP32_PINMUX(19, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO19 ESP32_PINMUX(19, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO20 \
-	ESP32_PINMUX(20, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO20 ESP32_PINMUX(20, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO21 \
-	ESP32_PINMUX(21, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO21 ESP32_PINMUX(21, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO22 \
-	ESP32_PINMUX(22, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO22 ESP32_PINMUX(22, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO23 \
-	ESP32_PINMUX(23, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO23 ESP32_PINMUX(23, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO25 \
-	ESP32_PINMUX(25, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO25 ESP32_PINMUX(25, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO26 \
-	ESP32_PINMUX(26, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO26 ESP32_PINMUX(26, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO27 \
-	ESP32_PINMUX(27, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO27 ESP32_PINMUX(27, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO32 \
-	ESP32_PINMUX(32, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO32 ESP32_PINMUX(32, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO33 \
-	ESP32_PINMUX(33, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO33 ESP32_PINMUX(33, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO34 \
-	ESP32_PINMUX(34, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO34 ESP32_PINMUX(34, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO35 \
-	ESP32_PINMUX(35, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO35 ESP32_PINMUX(35, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO36 \
-	ESP32_PINMUX(36, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO36 ESP32_PINMUX(36, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO37 \
-	ESP32_PINMUX(37, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO37 ESP32_PINMUX(37, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO38 \
-	ESP32_PINMUX(38, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO38 ESP32_PINMUX(38, ESP_PWM0_F0_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT0_GPIO39 \
-	ESP32_PINMUX(39, ESP_PWM0_F0_IN, ESP_NOSIG)
+#define MCPWM0_FAULT0_GPIO39 ESP32_PINMUX(39, ESP_PWM0_F0_IN, ESP_NOSIG)
 
 /* MCPWM0_FAULT1 */
-#define MCPWM0_FAULT1_GPIO0 \
-	ESP32_PINMUX(0, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO0 ESP32_PINMUX(0, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO1 \
-	ESP32_PINMUX(1, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO1 ESP32_PINMUX(1, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO2 \
-	ESP32_PINMUX(2, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO2 ESP32_PINMUX(2, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO3 \
-	ESP32_PINMUX(3, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO3 ESP32_PINMUX(3, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO4 \
-	ESP32_PINMUX(4, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO4 ESP32_PINMUX(4, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO5 \
-	ESP32_PINMUX(5, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO5 ESP32_PINMUX(5, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO6 \
-	ESP32_PINMUX(6, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO6 ESP32_PINMUX(6, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO7 \
-	ESP32_PINMUX(7, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO7 ESP32_PINMUX(7, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO8 \
-	ESP32_PINMUX(8, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO8 ESP32_PINMUX(8, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO9 \
-	ESP32_PINMUX(9, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO9 ESP32_PINMUX(9, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO10 \
-	ESP32_PINMUX(10, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO10 ESP32_PINMUX(10, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO11 \
-	ESP32_PINMUX(11, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO11 ESP32_PINMUX(11, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO12 \
-	ESP32_PINMUX(12, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO12 ESP32_PINMUX(12, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO13 \
-	ESP32_PINMUX(13, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO13 ESP32_PINMUX(13, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO14 \
-	ESP32_PINMUX(14, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO14 ESP32_PINMUX(14, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO15 \
-	ESP32_PINMUX(15, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO15 ESP32_PINMUX(15, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO16 \
-	ESP32_PINMUX(16, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO16 ESP32_PINMUX(16, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO17 \
-	ESP32_PINMUX(17, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO17 ESP32_PINMUX(17, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO18 \
-	ESP32_PINMUX(18, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO18 ESP32_PINMUX(18, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO19 \
-	ESP32_PINMUX(19, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO19 ESP32_PINMUX(19, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO20 \
-	ESP32_PINMUX(20, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO20 ESP32_PINMUX(20, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO21 \
-	ESP32_PINMUX(21, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO21 ESP32_PINMUX(21, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO22 \
-	ESP32_PINMUX(22, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO22 ESP32_PINMUX(22, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO23 \
-	ESP32_PINMUX(23, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO23 ESP32_PINMUX(23, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO25 \
-	ESP32_PINMUX(25, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO25 ESP32_PINMUX(25, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO26 \
-	ESP32_PINMUX(26, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO26 ESP32_PINMUX(26, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO27 \
-	ESP32_PINMUX(27, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO27 ESP32_PINMUX(27, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO32 \
-	ESP32_PINMUX(32, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO32 ESP32_PINMUX(32, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO33 \
-	ESP32_PINMUX(33, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO33 ESP32_PINMUX(33, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO34 \
-	ESP32_PINMUX(34, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO34 ESP32_PINMUX(34, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO35 \
-	ESP32_PINMUX(35, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO35 ESP32_PINMUX(35, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO36 \
-	ESP32_PINMUX(36, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO36 ESP32_PINMUX(36, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO37 \
-	ESP32_PINMUX(37, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO37 ESP32_PINMUX(37, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO38 \
-	ESP32_PINMUX(38, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO38 ESP32_PINMUX(38, ESP_PWM0_F1_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT1_GPIO39 \
-	ESP32_PINMUX(39, ESP_PWM0_F1_IN, ESP_NOSIG)
+#define MCPWM0_FAULT1_GPIO39 ESP32_PINMUX(39, ESP_PWM0_F1_IN, ESP_NOSIG)
 
 /* MCPWM0_FAULT2 */
-#define MCPWM0_FAULT2_GPIO0 \
-	ESP32_PINMUX(0, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO0 ESP32_PINMUX(0, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO1 \
-	ESP32_PINMUX(1, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO1 ESP32_PINMUX(1, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO2 \
-	ESP32_PINMUX(2, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO2 ESP32_PINMUX(2, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO3 \
-	ESP32_PINMUX(3, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO3 ESP32_PINMUX(3, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO4 \
-	ESP32_PINMUX(4, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO4 ESP32_PINMUX(4, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO5 \
-	ESP32_PINMUX(5, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO5 ESP32_PINMUX(5, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO6 \
-	ESP32_PINMUX(6, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO6 ESP32_PINMUX(6, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO7 \
-	ESP32_PINMUX(7, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO7 ESP32_PINMUX(7, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO8 \
-	ESP32_PINMUX(8, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO8 ESP32_PINMUX(8, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO9 \
-	ESP32_PINMUX(9, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO9 ESP32_PINMUX(9, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO10 \
-	ESP32_PINMUX(10, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO10 ESP32_PINMUX(10, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO11 \
-	ESP32_PINMUX(11, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO11 ESP32_PINMUX(11, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO12 \
-	ESP32_PINMUX(12, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO12 ESP32_PINMUX(12, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO13 \
-	ESP32_PINMUX(13, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO13 ESP32_PINMUX(13, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO14 \
-	ESP32_PINMUX(14, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO14 ESP32_PINMUX(14, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO15 \
-	ESP32_PINMUX(15, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO15 ESP32_PINMUX(15, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO16 \
-	ESP32_PINMUX(16, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO16 ESP32_PINMUX(16, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO17 \
-	ESP32_PINMUX(17, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO17 ESP32_PINMUX(17, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO18 \
-	ESP32_PINMUX(18, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO18 ESP32_PINMUX(18, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO19 \
-	ESP32_PINMUX(19, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO19 ESP32_PINMUX(19, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO20 \
-	ESP32_PINMUX(20, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO20 ESP32_PINMUX(20, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO21 \
-	ESP32_PINMUX(21, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO21 ESP32_PINMUX(21, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO22 \
-	ESP32_PINMUX(22, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO22 ESP32_PINMUX(22, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO23 \
-	ESP32_PINMUX(23, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO23 ESP32_PINMUX(23, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO25 \
-	ESP32_PINMUX(25, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO25 ESP32_PINMUX(25, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO26 \
-	ESP32_PINMUX(26, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO26 ESP32_PINMUX(26, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO27 \
-	ESP32_PINMUX(27, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO27 ESP32_PINMUX(27, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO32 \
-	ESP32_PINMUX(32, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO32 ESP32_PINMUX(32, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO33 \
-	ESP32_PINMUX(33, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO33 ESP32_PINMUX(33, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO34 \
-	ESP32_PINMUX(34, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO34 ESP32_PINMUX(34, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO35 \
-	ESP32_PINMUX(35, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO35 ESP32_PINMUX(35, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO36 \
-	ESP32_PINMUX(36, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO36 ESP32_PINMUX(36, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO37 \
-	ESP32_PINMUX(37, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO37 ESP32_PINMUX(37, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO38 \
-	ESP32_PINMUX(38, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO38 ESP32_PINMUX(38, ESP_PWM0_F2_IN, ESP_NOSIG)
 
-#define MCPWM0_FAULT2_GPIO39 \
-	ESP32_PINMUX(39, ESP_PWM0_F2_IN, ESP_NOSIG)
+#define MCPWM0_FAULT2_GPIO39 ESP32_PINMUX(39, ESP_PWM0_F2_IN, ESP_NOSIG)
 
 /* MCPWM0_OUT0A */
-#define MCPWM0_OUT0A_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT0A)
 
-#define MCPWM0_OUT0A_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT0A)
+#define MCPWM0_OUT0A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT0A)
 
 /* MCPWM0_OUT0B */
-#define MCPWM0_OUT0B_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT0B)
 
-#define MCPWM0_OUT0B_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT0B)
+#define MCPWM0_OUT0B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT0B)
 
 /* MCPWM0_OUT1A */
-#define MCPWM0_OUT1A_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT1A)
 
-#define MCPWM0_OUT1A_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT1A)
+#define MCPWM0_OUT1A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT1A)
 
 /* MCPWM0_OUT1B */
-#define MCPWM0_OUT1B_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT1B)
 
-#define MCPWM0_OUT1B_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT1B)
+#define MCPWM0_OUT1B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT1B)
 
 /* MCPWM0_OUT2A */
-#define MCPWM0_OUT2A_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT2A)
 
-#define MCPWM0_OUT2A_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT2A)
+#define MCPWM0_OUT2A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT2A)
 
 /* MCPWM0_OUT2B */
-#define MCPWM0_OUT2B_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM0_OUT2B)
 
-#define MCPWM0_OUT2B_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT2B)
+#define MCPWM0_OUT2B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM0_OUT2B)
 
 /* MCPWM0_SYNC0 */
-#define MCPWM0_SYNC0_GPIO0 \
-	ESP32_PINMUX(0, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO0 ESP32_PINMUX(0, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO1 \
-	ESP32_PINMUX(1, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO1 ESP32_PINMUX(1, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO2 \
-	ESP32_PINMUX(2, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO2 ESP32_PINMUX(2, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO3 \
-	ESP32_PINMUX(3, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO3 ESP32_PINMUX(3, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO4 \
-	ESP32_PINMUX(4, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO4 ESP32_PINMUX(4, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO5 \
-	ESP32_PINMUX(5, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO5 ESP32_PINMUX(5, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO6 \
-	ESP32_PINMUX(6, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO6 ESP32_PINMUX(6, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO7 \
-	ESP32_PINMUX(7, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO7 ESP32_PINMUX(7, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO8 \
-	ESP32_PINMUX(8, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO8 ESP32_PINMUX(8, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO9 \
-	ESP32_PINMUX(9, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO9 ESP32_PINMUX(9, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO10 \
-	ESP32_PINMUX(10, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO10 ESP32_PINMUX(10, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO11 \
-	ESP32_PINMUX(11, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO11 ESP32_PINMUX(11, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO12 \
-	ESP32_PINMUX(12, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO12 ESP32_PINMUX(12, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO13 \
-	ESP32_PINMUX(13, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO13 ESP32_PINMUX(13, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO14 \
-	ESP32_PINMUX(14, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO14 ESP32_PINMUX(14, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO15 \
-	ESP32_PINMUX(15, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO15 ESP32_PINMUX(15, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO16 \
-	ESP32_PINMUX(16, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO16 ESP32_PINMUX(16, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO17 \
-	ESP32_PINMUX(17, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO17 ESP32_PINMUX(17, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO18 \
-	ESP32_PINMUX(18, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO18 ESP32_PINMUX(18, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO19 \
-	ESP32_PINMUX(19, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO19 ESP32_PINMUX(19, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO20 \
-	ESP32_PINMUX(20, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO20 ESP32_PINMUX(20, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO21 \
-	ESP32_PINMUX(21, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO21 ESP32_PINMUX(21, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO22 \
-	ESP32_PINMUX(22, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO22 ESP32_PINMUX(22, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO23 \
-	ESP32_PINMUX(23, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO23 ESP32_PINMUX(23, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO25 \
-	ESP32_PINMUX(25, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO25 ESP32_PINMUX(25, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO26 \
-	ESP32_PINMUX(26, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO26 ESP32_PINMUX(26, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO27 \
-	ESP32_PINMUX(27, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO27 ESP32_PINMUX(27, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO32 \
-	ESP32_PINMUX(32, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO32 ESP32_PINMUX(32, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO33 \
-	ESP32_PINMUX(33, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO33 ESP32_PINMUX(33, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO34 \
-	ESP32_PINMUX(34, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO34 ESP32_PINMUX(34, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO35 \
-	ESP32_PINMUX(35, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO35 ESP32_PINMUX(35, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO36 \
-	ESP32_PINMUX(36, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO36 ESP32_PINMUX(36, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO37 \
-	ESP32_PINMUX(37, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO37 ESP32_PINMUX(37, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO38 \
-	ESP32_PINMUX(38, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO38 ESP32_PINMUX(38, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC0_GPIO39 \
-	ESP32_PINMUX(39, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
+#define MCPWM0_SYNC0_GPIO39 ESP32_PINMUX(39, ESP_PWM0_SYNC0_IN, ESP_NOSIG)
 
 /* MCPWM0_SYNC1 */
-#define MCPWM0_SYNC1_GPIO0 \
-	ESP32_PINMUX(0, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO0 ESP32_PINMUX(0, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO1 \
-	ESP32_PINMUX(1, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO1 ESP32_PINMUX(1, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO2 \
-	ESP32_PINMUX(2, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO2 ESP32_PINMUX(2, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO3 \
-	ESP32_PINMUX(3, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO3 ESP32_PINMUX(3, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO4 \
-	ESP32_PINMUX(4, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO4 ESP32_PINMUX(4, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO5 \
-	ESP32_PINMUX(5, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO5 ESP32_PINMUX(5, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO6 \
-	ESP32_PINMUX(6, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO6 ESP32_PINMUX(6, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO7 \
-	ESP32_PINMUX(7, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO7 ESP32_PINMUX(7, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO8 \
-	ESP32_PINMUX(8, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO8 ESP32_PINMUX(8, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO9 \
-	ESP32_PINMUX(9, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO9 ESP32_PINMUX(9, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO10 \
-	ESP32_PINMUX(10, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO10 ESP32_PINMUX(10, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO11 \
-	ESP32_PINMUX(11, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO11 ESP32_PINMUX(11, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO12 \
-	ESP32_PINMUX(12, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO12 ESP32_PINMUX(12, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO13 \
-	ESP32_PINMUX(13, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO13 ESP32_PINMUX(13, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO14 \
-	ESP32_PINMUX(14, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO14 ESP32_PINMUX(14, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO15 \
-	ESP32_PINMUX(15, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO15 ESP32_PINMUX(15, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO16 \
-	ESP32_PINMUX(16, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO16 ESP32_PINMUX(16, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO17 \
-	ESP32_PINMUX(17, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO17 ESP32_PINMUX(17, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO18 \
-	ESP32_PINMUX(18, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO18 ESP32_PINMUX(18, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO19 \
-	ESP32_PINMUX(19, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO19 ESP32_PINMUX(19, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO20 \
-	ESP32_PINMUX(20, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO20 ESP32_PINMUX(20, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO21 \
-	ESP32_PINMUX(21, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO21 ESP32_PINMUX(21, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO22 \
-	ESP32_PINMUX(22, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO22 ESP32_PINMUX(22, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO23 \
-	ESP32_PINMUX(23, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO23 ESP32_PINMUX(23, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO25 \
-	ESP32_PINMUX(25, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO25 ESP32_PINMUX(25, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO26 \
-	ESP32_PINMUX(26, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO26 ESP32_PINMUX(26, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO27 \
-	ESP32_PINMUX(27, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO27 ESP32_PINMUX(27, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO32 \
-	ESP32_PINMUX(32, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO32 ESP32_PINMUX(32, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO33 \
-	ESP32_PINMUX(33, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO33 ESP32_PINMUX(33, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO34 \
-	ESP32_PINMUX(34, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO34 ESP32_PINMUX(34, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO35 \
-	ESP32_PINMUX(35, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO35 ESP32_PINMUX(35, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO36 \
-	ESP32_PINMUX(36, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO36 ESP32_PINMUX(36, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO37 \
-	ESP32_PINMUX(37, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO37 ESP32_PINMUX(37, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO38 \
-	ESP32_PINMUX(38, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO38 ESP32_PINMUX(38, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC1_GPIO39 \
-	ESP32_PINMUX(39, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
+#define MCPWM0_SYNC1_GPIO39 ESP32_PINMUX(39, ESP_PWM0_SYNC1_IN, ESP_NOSIG)
 
 /* MCPWM0_SYNC2 */
-#define MCPWM0_SYNC2_GPIO0 \
-	ESP32_PINMUX(0, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO0 ESP32_PINMUX(0, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO1 \
-	ESP32_PINMUX(1, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO1 ESP32_PINMUX(1, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO2 \
-	ESP32_PINMUX(2, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO2 ESP32_PINMUX(2, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO3 \
-	ESP32_PINMUX(3, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO3 ESP32_PINMUX(3, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO4 \
-	ESP32_PINMUX(4, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO4 ESP32_PINMUX(4, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO5 \
-	ESP32_PINMUX(5, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO5 ESP32_PINMUX(5, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO6 \
-	ESP32_PINMUX(6, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO6 ESP32_PINMUX(6, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO7 \
-	ESP32_PINMUX(7, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO7 ESP32_PINMUX(7, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO8 \
-	ESP32_PINMUX(8, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO8 ESP32_PINMUX(8, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO9 \
-	ESP32_PINMUX(9, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO9 ESP32_PINMUX(9, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO10 \
-	ESP32_PINMUX(10, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO10 ESP32_PINMUX(10, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO11 \
-	ESP32_PINMUX(11, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO11 ESP32_PINMUX(11, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO12 \
-	ESP32_PINMUX(12, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO12 ESP32_PINMUX(12, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO13 \
-	ESP32_PINMUX(13, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO13 ESP32_PINMUX(13, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO14 \
-	ESP32_PINMUX(14, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO14 ESP32_PINMUX(14, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO15 \
-	ESP32_PINMUX(15, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO15 ESP32_PINMUX(15, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO16 \
-	ESP32_PINMUX(16, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO16 ESP32_PINMUX(16, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO17 \
-	ESP32_PINMUX(17, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO17 ESP32_PINMUX(17, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO18 \
-	ESP32_PINMUX(18, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO18 ESP32_PINMUX(18, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO19 \
-	ESP32_PINMUX(19, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO19 ESP32_PINMUX(19, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO20 \
-	ESP32_PINMUX(20, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO20 ESP32_PINMUX(20, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO21 \
-	ESP32_PINMUX(21, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO21 ESP32_PINMUX(21, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO22 \
-	ESP32_PINMUX(22, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO22 ESP32_PINMUX(22, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO23 \
-	ESP32_PINMUX(23, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO23 ESP32_PINMUX(23, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO25 \
-	ESP32_PINMUX(25, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO25 ESP32_PINMUX(25, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO26 \
-	ESP32_PINMUX(26, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO26 ESP32_PINMUX(26, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO27 \
-	ESP32_PINMUX(27, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO27 ESP32_PINMUX(27, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO32 \
-	ESP32_PINMUX(32, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO32 ESP32_PINMUX(32, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO33 \
-	ESP32_PINMUX(33, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO33 ESP32_PINMUX(33, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO34 \
-	ESP32_PINMUX(34, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO34 ESP32_PINMUX(34, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO35 \
-	ESP32_PINMUX(35, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO35 ESP32_PINMUX(35, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO36 \
-	ESP32_PINMUX(36, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO36 ESP32_PINMUX(36, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO37 \
-	ESP32_PINMUX(37, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO37 ESP32_PINMUX(37, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO38 \
-	ESP32_PINMUX(38, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO38 ESP32_PINMUX(38, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM0_SYNC2_GPIO39 \
-	ESP32_PINMUX(39, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
+#define MCPWM0_SYNC2_GPIO39 ESP32_PINMUX(39, ESP_PWM0_SYNC2_IN, ESP_NOSIG)
 
 /* MCPWM1_CAP0 */
-#define MCPWM1_CAP0_GPIO0 \
-	ESP32_PINMUX(0, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO0 ESP32_PINMUX(0, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO1 \
-	ESP32_PINMUX(1, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO1 ESP32_PINMUX(1, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO2 \
-	ESP32_PINMUX(2, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO2 ESP32_PINMUX(2, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO3 \
-	ESP32_PINMUX(3, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO3 ESP32_PINMUX(3, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO4 \
-	ESP32_PINMUX(4, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO4 ESP32_PINMUX(4, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO5 \
-	ESP32_PINMUX(5, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO5 ESP32_PINMUX(5, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO6 \
-	ESP32_PINMUX(6, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO6 ESP32_PINMUX(6, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO7 \
-	ESP32_PINMUX(7, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO7 ESP32_PINMUX(7, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO8 \
-	ESP32_PINMUX(8, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO8 ESP32_PINMUX(8, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO9 \
-	ESP32_PINMUX(9, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO9 ESP32_PINMUX(9, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO10 \
-	ESP32_PINMUX(10, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO10 ESP32_PINMUX(10, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO11 \
-	ESP32_PINMUX(11, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO11 ESP32_PINMUX(11, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO12 \
-	ESP32_PINMUX(12, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO12 ESP32_PINMUX(12, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO13 \
-	ESP32_PINMUX(13, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO13 ESP32_PINMUX(13, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO14 \
-	ESP32_PINMUX(14, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO14 ESP32_PINMUX(14, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO15 \
-	ESP32_PINMUX(15, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO15 ESP32_PINMUX(15, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO16 \
-	ESP32_PINMUX(16, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO16 ESP32_PINMUX(16, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO17 \
-	ESP32_PINMUX(17, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO17 ESP32_PINMUX(17, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO18 \
-	ESP32_PINMUX(18, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO18 ESP32_PINMUX(18, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO19 \
-	ESP32_PINMUX(19, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO19 ESP32_PINMUX(19, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO20 \
-	ESP32_PINMUX(20, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO20 ESP32_PINMUX(20, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO21 \
-	ESP32_PINMUX(21, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO21 ESP32_PINMUX(21, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO22 \
-	ESP32_PINMUX(22, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO22 ESP32_PINMUX(22, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO23 \
-	ESP32_PINMUX(23, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO23 ESP32_PINMUX(23, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO25 \
-	ESP32_PINMUX(25, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO25 ESP32_PINMUX(25, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO26 \
-	ESP32_PINMUX(26, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO26 ESP32_PINMUX(26, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO27 \
-	ESP32_PINMUX(27, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO27 ESP32_PINMUX(27, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO32 \
-	ESP32_PINMUX(32, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO32 ESP32_PINMUX(32, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO33 \
-	ESP32_PINMUX(33, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO33 ESP32_PINMUX(33, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO34 \
-	ESP32_PINMUX(34, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO34 ESP32_PINMUX(34, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO35 \
-	ESP32_PINMUX(35, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO35 ESP32_PINMUX(35, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO36 \
-	ESP32_PINMUX(36, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO36 ESP32_PINMUX(36, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO37 \
-	ESP32_PINMUX(37, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO37 ESP32_PINMUX(37, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO38 \
-	ESP32_PINMUX(38, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO38 ESP32_PINMUX(38, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP0_GPIO39 \
-	ESP32_PINMUX(39, ESP_PWM1_CAP0_IN, ESP_NOSIG)
+#define MCPWM1_CAP0_GPIO39 ESP32_PINMUX(39, ESP_PWM1_CAP0_IN, ESP_NOSIG)
 
 /* MCPWM1_CAP1 */
-#define MCPWM1_CAP1_GPIO0 \
-	ESP32_PINMUX(0, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO0 ESP32_PINMUX(0, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO1 \
-	ESP32_PINMUX(1, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO1 ESP32_PINMUX(1, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO2 \
-	ESP32_PINMUX(2, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO2 ESP32_PINMUX(2, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO3 \
-	ESP32_PINMUX(3, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO3 ESP32_PINMUX(3, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO4 \
-	ESP32_PINMUX(4, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO4 ESP32_PINMUX(4, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO5 \
-	ESP32_PINMUX(5, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO5 ESP32_PINMUX(5, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO6 \
-	ESP32_PINMUX(6, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO6 ESP32_PINMUX(6, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO7 \
-	ESP32_PINMUX(7, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO7 ESP32_PINMUX(7, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO8 \
-	ESP32_PINMUX(8, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO8 ESP32_PINMUX(8, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO9 \
-	ESP32_PINMUX(9, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO9 ESP32_PINMUX(9, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO10 \
-	ESP32_PINMUX(10, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO10 ESP32_PINMUX(10, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO11 \
-	ESP32_PINMUX(11, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO11 ESP32_PINMUX(11, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO12 \
-	ESP32_PINMUX(12, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO12 ESP32_PINMUX(12, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO13 \
-	ESP32_PINMUX(13, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO13 ESP32_PINMUX(13, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO14 \
-	ESP32_PINMUX(14, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO14 ESP32_PINMUX(14, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO15 \
-	ESP32_PINMUX(15, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO15 ESP32_PINMUX(15, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO16 \
-	ESP32_PINMUX(16, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO16 ESP32_PINMUX(16, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO17 \
-	ESP32_PINMUX(17, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO17 ESP32_PINMUX(17, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO18 \
-	ESP32_PINMUX(18, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO18 ESP32_PINMUX(18, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO19 \
-	ESP32_PINMUX(19, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO19 ESP32_PINMUX(19, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO20 \
-	ESP32_PINMUX(20, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO20 ESP32_PINMUX(20, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO21 \
-	ESP32_PINMUX(21, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO21 ESP32_PINMUX(21, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO22 \
-	ESP32_PINMUX(22, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO22 ESP32_PINMUX(22, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO23 \
-	ESP32_PINMUX(23, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO23 ESP32_PINMUX(23, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO25 \
-	ESP32_PINMUX(25, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO25 ESP32_PINMUX(25, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO26 \
-	ESP32_PINMUX(26, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO26 ESP32_PINMUX(26, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO27 \
-	ESP32_PINMUX(27, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO27 ESP32_PINMUX(27, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO32 \
-	ESP32_PINMUX(32, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO32 ESP32_PINMUX(32, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO33 \
-	ESP32_PINMUX(33, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO33 ESP32_PINMUX(33, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO34 \
-	ESP32_PINMUX(34, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO34 ESP32_PINMUX(34, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO35 \
-	ESP32_PINMUX(35, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO35 ESP32_PINMUX(35, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO36 \
-	ESP32_PINMUX(36, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO36 ESP32_PINMUX(36, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO37 \
-	ESP32_PINMUX(37, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO37 ESP32_PINMUX(37, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO38 \
-	ESP32_PINMUX(38, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO38 ESP32_PINMUX(38, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP1_GPIO39 \
-	ESP32_PINMUX(39, ESP_PWM1_CAP1_IN, ESP_NOSIG)
+#define MCPWM1_CAP1_GPIO39 ESP32_PINMUX(39, ESP_PWM1_CAP1_IN, ESP_NOSIG)
 
 /* MCPWM1_CAP2 */
-#define MCPWM1_CAP2_GPIO0 \
-	ESP32_PINMUX(0, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO0 ESP32_PINMUX(0, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO1 \
-	ESP32_PINMUX(1, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO1 ESP32_PINMUX(1, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO2 \
-	ESP32_PINMUX(2, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO2 ESP32_PINMUX(2, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO3 \
-	ESP32_PINMUX(3, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO3 ESP32_PINMUX(3, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO4 \
-	ESP32_PINMUX(4, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO4 ESP32_PINMUX(4, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO5 \
-	ESP32_PINMUX(5, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO5 ESP32_PINMUX(5, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO6 \
-	ESP32_PINMUX(6, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO6 ESP32_PINMUX(6, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO7 \
-	ESP32_PINMUX(7, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO7 ESP32_PINMUX(7, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO8 \
-	ESP32_PINMUX(8, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO8 ESP32_PINMUX(8, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO9 \
-	ESP32_PINMUX(9, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO9 ESP32_PINMUX(9, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO10 \
-	ESP32_PINMUX(10, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO10 ESP32_PINMUX(10, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO11 \
-	ESP32_PINMUX(11, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO11 ESP32_PINMUX(11, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO12 \
-	ESP32_PINMUX(12, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO12 ESP32_PINMUX(12, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO13 \
-	ESP32_PINMUX(13, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO13 ESP32_PINMUX(13, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO14 \
-	ESP32_PINMUX(14, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO14 ESP32_PINMUX(14, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO15 \
-	ESP32_PINMUX(15, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO15 ESP32_PINMUX(15, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO16 \
-	ESP32_PINMUX(16, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO16 ESP32_PINMUX(16, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO17 \
-	ESP32_PINMUX(17, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO17 ESP32_PINMUX(17, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO18 \
-	ESP32_PINMUX(18, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO18 ESP32_PINMUX(18, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO19 \
-	ESP32_PINMUX(19, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO19 ESP32_PINMUX(19, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO20 \
-	ESP32_PINMUX(20, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO20 ESP32_PINMUX(20, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO21 \
-	ESP32_PINMUX(21, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO21 ESP32_PINMUX(21, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO22 \
-	ESP32_PINMUX(22, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO22 ESP32_PINMUX(22, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO23 \
-	ESP32_PINMUX(23, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO23 ESP32_PINMUX(23, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO25 \
-	ESP32_PINMUX(25, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO25 ESP32_PINMUX(25, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO26 \
-	ESP32_PINMUX(26, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO26 ESP32_PINMUX(26, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO27 \
-	ESP32_PINMUX(27, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO27 ESP32_PINMUX(27, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO32 \
-	ESP32_PINMUX(32, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO32 ESP32_PINMUX(32, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO33 \
-	ESP32_PINMUX(33, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO33 ESP32_PINMUX(33, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO34 \
-	ESP32_PINMUX(34, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO34 ESP32_PINMUX(34, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO35 \
-	ESP32_PINMUX(35, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO35 ESP32_PINMUX(35, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO36 \
-	ESP32_PINMUX(36, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO36 ESP32_PINMUX(36, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO37 \
-	ESP32_PINMUX(37, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO37 ESP32_PINMUX(37, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO38 \
-	ESP32_PINMUX(38, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO38 ESP32_PINMUX(38, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
-#define MCPWM1_CAP2_GPIO39 \
-	ESP32_PINMUX(39, ESP_PWM1_CAP2_IN, ESP_NOSIG)
+#define MCPWM1_CAP2_GPIO39 ESP32_PINMUX(39, ESP_PWM1_CAP2_IN, ESP_NOSIG)
 
 /* MCPWM1_FAULT0 */
-#define MCPWM1_FAULT0_GPIO0 \
-	ESP32_PINMUX(0, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO0 ESP32_PINMUX(0, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO1 \
-	ESP32_PINMUX(1, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO1 ESP32_PINMUX(1, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO2 \
-	ESP32_PINMUX(2, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO2 ESP32_PINMUX(2, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO3 \
-	ESP32_PINMUX(3, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO3 ESP32_PINMUX(3, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO4 \
-	ESP32_PINMUX(4, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO4 ESP32_PINMUX(4, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO5 \
-	ESP32_PINMUX(5, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO5 ESP32_PINMUX(5, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO6 \
-	ESP32_PINMUX(6, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO6 ESP32_PINMUX(6, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO7 \
-	ESP32_PINMUX(7, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO7 ESP32_PINMUX(7, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO8 \
-	ESP32_PINMUX(8, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO8 ESP32_PINMUX(8, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO9 \
-	ESP32_PINMUX(9, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO9 ESP32_PINMUX(9, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO10 \
-	ESP32_PINMUX(10, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO10 ESP32_PINMUX(10, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO11 \
-	ESP32_PINMUX(11, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO11 ESP32_PINMUX(11, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO12 \
-	ESP32_PINMUX(12, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO12 ESP32_PINMUX(12, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO13 \
-	ESP32_PINMUX(13, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO13 ESP32_PINMUX(13, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO14 \
-	ESP32_PINMUX(14, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO14 ESP32_PINMUX(14, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO15 \
-	ESP32_PINMUX(15, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO15 ESP32_PINMUX(15, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO16 \
-	ESP32_PINMUX(16, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO16 ESP32_PINMUX(16, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO17 \
-	ESP32_PINMUX(17, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO17 ESP32_PINMUX(17, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO18 \
-	ESP32_PINMUX(18, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO18 ESP32_PINMUX(18, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO19 \
-	ESP32_PINMUX(19, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO19 ESP32_PINMUX(19, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO20 \
-	ESP32_PINMUX(20, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO20 ESP32_PINMUX(20, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO21 \
-	ESP32_PINMUX(21, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO21 ESP32_PINMUX(21, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO22 \
-	ESP32_PINMUX(22, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO22 ESP32_PINMUX(22, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO23 \
-	ESP32_PINMUX(23, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO23 ESP32_PINMUX(23, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO25 \
-	ESP32_PINMUX(25, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO25 ESP32_PINMUX(25, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO26 \
-	ESP32_PINMUX(26, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO26 ESP32_PINMUX(26, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO27 \
-	ESP32_PINMUX(27, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO27 ESP32_PINMUX(27, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO32 \
-	ESP32_PINMUX(32, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO32 ESP32_PINMUX(32, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO33 \
-	ESP32_PINMUX(33, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO33 ESP32_PINMUX(33, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO34 \
-	ESP32_PINMUX(34, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO34 ESP32_PINMUX(34, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO35 \
-	ESP32_PINMUX(35, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO35 ESP32_PINMUX(35, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO36 \
-	ESP32_PINMUX(36, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO36 ESP32_PINMUX(36, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO37 \
-	ESP32_PINMUX(37, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO37 ESP32_PINMUX(37, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO38 \
-	ESP32_PINMUX(38, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO38 ESP32_PINMUX(38, ESP_PWM1_F0_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT0_GPIO39 \
-	ESP32_PINMUX(39, ESP_PWM1_F0_IN, ESP_NOSIG)
+#define MCPWM1_FAULT0_GPIO39 ESP32_PINMUX(39, ESP_PWM1_F0_IN, ESP_NOSIG)
 
 /* MCPWM1_FAULT1 */
-#define MCPWM1_FAULT1_GPIO0 \
-	ESP32_PINMUX(0, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO0 ESP32_PINMUX(0, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO1 \
-	ESP32_PINMUX(1, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO1 ESP32_PINMUX(1, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO2 \
-	ESP32_PINMUX(2, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO2 ESP32_PINMUX(2, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO3 \
-	ESP32_PINMUX(3, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO3 ESP32_PINMUX(3, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO4 \
-	ESP32_PINMUX(4, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO4 ESP32_PINMUX(4, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO5 \
-	ESP32_PINMUX(5, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO5 ESP32_PINMUX(5, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO6 \
-	ESP32_PINMUX(6, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO6 ESP32_PINMUX(6, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO7 \
-	ESP32_PINMUX(7, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO7 ESP32_PINMUX(7, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO8 \
-	ESP32_PINMUX(8, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO8 ESP32_PINMUX(8, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO9 \
-	ESP32_PINMUX(9, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO9 ESP32_PINMUX(9, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO10 \
-	ESP32_PINMUX(10, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO10 ESP32_PINMUX(10, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO11 \
-	ESP32_PINMUX(11, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO11 ESP32_PINMUX(11, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO12 \
-	ESP32_PINMUX(12, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO12 ESP32_PINMUX(12, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO13 \
-	ESP32_PINMUX(13, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO13 ESP32_PINMUX(13, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO14 \
-	ESP32_PINMUX(14, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO14 ESP32_PINMUX(14, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO15 \
-	ESP32_PINMUX(15, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO15 ESP32_PINMUX(15, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO16 \
-	ESP32_PINMUX(16, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO16 ESP32_PINMUX(16, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO17 \
-	ESP32_PINMUX(17, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO17 ESP32_PINMUX(17, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO18 \
-	ESP32_PINMUX(18, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO18 ESP32_PINMUX(18, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO19 \
-	ESP32_PINMUX(19, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO19 ESP32_PINMUX(19, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO20 \
-	ESP32_PINMUX(20, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO20 ESP32_PINMUX(20, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO21 \
-	ESP32_PINMUX(21, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO21 ESP32_PINMUX(21, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO22 \
-	ESP32_PINMUX(22, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO22 ESP32_PINMUX(22, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO23 \
-	ESP32_PINMUX(23, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO23 ESP32_PINMUX(23, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO25 \
-	ESP32_PINMUX(25, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO25 ESP32_PINMUX(25, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO26 \
-	ESP32_PINMUX(26, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO26 ESP32_PINMUX(26, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO27 \
-	ESP32_PINMUX(27, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO27 ESP32_PINMUX(27, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO32 \
-	ESP32_PINMUX(32, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO32 ESP32_PINMUX(32, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO33 \
-	ESP32_PINMUX(33, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO33 ESP32_PINMUX(33, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO34 \
-	ESP32_PINMUX(34, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO34 ESP32_PINMUX(34, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO35 \
-	ESP32_PINMUX(35, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO35 ESP32_PINMUX(35, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO36 \
-	ESP32_PINMUX(36, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO36 ESP32_PINMUX(36, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO37 \
-	ESP32_PINMUX(37, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO37 ESP32_PINMUX(37, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO38 \
-	ESP32_PINMUX(38, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO38 ESP32_PINMUX(38, ESP_PWM1_F1_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT1_GPIO39 \
-	ESP32_PINMUX(39, ESP_PWM1_F1_IN, ESP_NOSIG)
+#define MCPWM1_FAULT1_GPIO39 ESP32_PINMUX(39, ESP_PWM1_F1_IN, ESP_NOSIG)
 
 /* MCPWM1_FAULT2 */
-#define MCPWM1_FAULT2_GPIO0 \
-	ESP32_PINMUX(0, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO0 ESP32_PINMUX(0, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO1 \
-	ESP32_PINMUX(1, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO1 ESP32_PINMUX(1, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO2 \
-	ESP32_PINMUX(2, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO2 ESP32_PINMUX(2, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO3 \
-	ESP32_PINMUX(3, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO3 ESP32_PINMUX(3, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO4 \
-	ESP32_PINMUX(4, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO4 ESP32_PINMUX(4, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO5 \
-	ESP32_PINMUX(5, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO5 ESP32_PINMUX(5, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO6 \
-	ESP32_PINMUX(6, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO6 ESP32_PINMUX(6, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO7 \
-	ESP32_PINMUX(7, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO7 ESP32_PINMUX(7, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO8 \
-	ESP32_PINMUX(8, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO8 ESP32_PINMUX(8, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO9 \
-	ESP32_PINMUX(9, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO9 ESP32_PINMUX(9, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO10 \
-	ESP32_PINMUX(10, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO10 ESP32_PINMUX(10, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO11 \
-	ESP32_PINMUX(11, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO11 ESP32_PINMUX(11, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO12 \
-	ESP32_PINMUX(12, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO12 ESP32_PINMUX(12, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO13 \
-	ESP32_PINMUX(13, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO13 ESP32_PINMUX(13, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO14 \
-	ESP32_PINMUX(14, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO14 ESP32_PINMUX(14, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO15 \
-	ESP32_PINMUX(15, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO15 ESP32_PINMUX(15, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO16 \
-	ESP32_PINMUX(16, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO16 ESP32_PINMUX(16, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO17 \
-	ESP32_PINMUX(17, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO17 ESP32_PINMUX(17, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO18 \
-	ESP32_PINMUX(18, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO18 ESP32_PINMUX(18, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO19 \
-	ESP32_PINMUX(19, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO19 ESP32_PINMUX(19, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO20 \
-	ESP32_PINMUX(20, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO20 ESP32_PINMUX(20, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO21 \
-	ESP32_PINMUX(21, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO21 ESP32_PINMUX(21, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO22 \
-	ESP32_PINMUX(22, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO22 ESP32_PINMUX(22, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO23 \
-	ESP32_PINMUX(23, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO23 ESP32_PINMUX(23, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO25 \
-	ESP32_PINMUX(25, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO25 ESP32_PINMUX(25, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO26 \
-	ESP32_PINMUX(26, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO26 ESP32_PINMUX(26, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO27 \
-	ESP32_PINMUX(27, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO27 ESP32_PINMUX(27, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO32 \
-	ESP32_PINMUX(32, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO32 ESP32_PINMUX(32, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO33 \
-	ESP32_PINMUX(33, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO33 ESP32_PINMUX(33, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO34 \
-	ESP32_PINMUX(34, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO34 ESP32_PINMUX(34, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO35 \
-	ESP32_PINMUX(35, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO35 ESP32_PINMUX(35, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO36 \
-	ESP32_PINMUX(36, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO36 ESP32_PINMUX(36, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO37 \
-	ESP32_PINMUX(37, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO37 ESP32_PINMUX(37, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO38 \
-	ESP32_PINMUX(38, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO38 ESP32_PINMUX(38, ESP_PWM1_F2_IN, ESP_NOSIG)
 
-#define MCPWM1_FAULT2_GPIO39 \
-	ESP32_PINMUX(39, ESP_PWM1_F2_IN, ESP_NOSIG)
+#define MCPWM1_FAULT2_GPIO39 ESP32_PINMUX(39, ESP_PWM1_F2_IN, ESP_NOSIG)
 
 /* MCPWM1_OUT0A */
-#define MCPWM1_OUT0A_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT0A)
 
-#define MCPWM1_OUT0A_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT0A)
+#define MCPWM1_OUT0A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT0A)
 
 /* MCPWM1_OUT0B */
-#define MCPWM1_OUT0B_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT0B)
 
-#define MCPWM1_OUT0B_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT0B)
+#define MCPWM1_OUT0B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT0B)
 
 /* MCPWM1_OUT1A */
-#define MCPWM1_OUT1A_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT1A)
 
-#define MCPWM1_OUT1A_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT1A)
+#define MCPWM1_OUT1A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT1A)
 
 /* MCPWM1_OUT1B */
-#define MCPWM1_OUT1B_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT1B)
 
-#define MCPWM1_OUT1B_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT1B)
+#define MCPWM1_OUT1B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT1B)
 
 /* MCPWM1_OUT2A */
-#define MCPWM1_OUT2A_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT2A)
 
-#define MCPWM1_OUT2A_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT2A)
+#define MCPWM1_OUT2A_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT2A)
 
 /* MCPWM1_OUT2B */
-#define MCPWM1_OUT2B_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_PWM1_OUT2B)
 
-#define MCPWM1_OUT2B_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT2B)
+#define MCPWM1_OUT2B_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_PWM1_OUT2B)
 
 /* MCPWM1_SYNC0 */
-#define MCPWM1_SYNC0_GPIO0 \
-	ESP32_PINMUX(0, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO0 ESP32_PINMUX(0, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO1 \
-	ESP32_PINMUX(1, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO1 ESP32_PINMUX(1, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO2 \
-	ESP32_PINMUX(2, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO2 ESP32_PINMUX(2, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO3 \
-	ESP32_PINMUX(3, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO3 ESP32_PINMUX(3, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO4 \
-	ESP32_PINMUX(4, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO4 ESP32_PINMUX(4, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO5 \
-	ESP32_PINMUX(5, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO5 ESP32_PINMUX(5, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO6 \
-	ESP32_PINMUX(6, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO6 ESP32_PINMUX(6, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO7 \
-	ESP32_PINMUX(7, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO7 ESP32_PINMUX(7, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO8 \
-	ESP32_PINMUX(8, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO8 ESP32_PINMUX(8, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO9 \
-	ESP32_PINMUX(9, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO9 ESP32_PINMUX(9, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO10 \
-	ESP32_PINMUX(10, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO10 ESP32_PINMUX(10, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO11 \
-	ESP32_PINMUX(11, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO11 ESP32_PINMUX(11, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO12 \
-	ESP32_PINMUX(12, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO12 ESP32_PINMUX(12, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO13 \
-	ESP32_PINMUX(13, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO13 ESP32_PINMUX(13, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO14 \
-	ESP32_PINMUX(14, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO14 ESP32_PINMUX(14, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO15 \
-	ESP32_PINMUX(15, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO15 ESP32_PINMUX(15, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO16 \
-	ESP32_PINMUX(16, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO16 ESP32_PINMUX(16, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO17 \
-	ESP32_PINMUX(17, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO17 ESP32_PINMUX(17, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO18 \
-	ESP32_PINMUX(18, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO18 ESP32_PINMUX(18, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO19 \
-	ESP32_PINMUX(19, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO19 ESP32_PINMUX(19, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO20 \
-	ESP32_PINMUX(20, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO20 ESP32_PINMUX(20, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO21 \
-	ESP32_PINMUX(21, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO21 ESP32_PINMUX(21, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO22 \
-	ESP32_PINMUX(22, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO22 ESP32_PINMUX(22, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO23 \
-	ESP32_PINMUX(23, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO23 ESP32_PINMUX(23, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO25 \
-	ESP32_PINMUX(25, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO25 ESP32_PINMUX(25, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO26 \
-	ESP32_PINMUX(26, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO26 ESP32_PINMUX(26, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO27 \
-	ESP32_PINMUX(27, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO27 ESP32_PINMUX(27, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO32 \
-	ESP32_PINMUX(32, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO32 ESP32_PINMUX(32, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO33 \
-	ESP32_PINMUX(33, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO33 ESP32_PINMUX(33, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO34 \
-	ESP32_PINMUX(34, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO34 ESP32_PINMUX(34, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO35 \
-	ESP32_PINMUX(35, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO35 ESP32_PINMUX(35, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO36 \
-	ESP32_PINMUX(36, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO36 ESP32_PINMUX(36, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO37 \
-	ESP32_PINMUX(37, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO37 ESP32_PINMUX(37, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO38 \
-	ESP32_PINMUX(38, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO38 ESP32_PINMUX(38, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC0_GPIO39 \
-	ESP32_PINMUX(39, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
+#define MCPWM1_SYNC0_GPIO39 ESP32_PINMUX(39, ESP_PWM1_SYNC0_IN, ESP_NOSIG)
 
 /* MCPWM1_SYNC1 */
-#define MCPWM1_SYNC1_GPIO0 \
-	ESP32_PINMUX(0, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO0 ESP32_PINMUX(0, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO1 \
-	ESP32_PINMUX(1, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO1 ESP32_PINMUX(1, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO2 \
-	ESP32_PINMUX(2, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO2 ESP32_PINMUX(2, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO3 \
-	ESP32_PINMUX(3, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO3 ESP32_PINMUX(3, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO4 \
-	ESP32_PINMUX(4, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO4 ESP32_PINMUX(4, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO5 \
-	ESP32_PINMUX(5, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO5 ESP32_PINMUX(5, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO6 \
-	ESP32_PINMUX(6, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO6 ESP32_PINMUX(6, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO7 \
-	ESP32_PINMUX(7, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO7 ESP32_PINMUX(7, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO8 \
-	ESP32_PINMUX(8, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO8 ESP32_PINMUX(8, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO9 \
-	ESP32_PINMUX(9, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO9 ESP32_PINMUX(9, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO10 \
-	ESP32_PINMUX(10, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO10 ESP32_PINMUX(10, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO11 \
-	ESP32_PINMUX(11, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO11 ESP32_PINMUX(11, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO12 \
-	ESP32_PINMUX(12, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO12 ESP32_PINMUX(12, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO13 \
-	ESP32_PINMUX(13, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO13 ESP32_PINMUX(13, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO14 \
-	ESP32_PINMUX(14, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO14 ESP32_PINMUX(14, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO15 \
-	ESP32_PINMUX(15, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO15 ESP32_PINMUX(15, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO16 \
-	ESP32_PINMUX(16, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO16 ESP32_PINMUX(16, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO17 \
-	ESP32_PINMUX(17, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO17 ESP32_PINMUX(17, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO18 \
-	ESP32_PINMUX(18, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO18 ESP32_PINMUX(18, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO19 \
-	ESP32_PINMUX(19, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO19 ESP32_PINMUX(19, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO20 \
-	ESP32_PINMUX(20, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO20 ESP32_PINMUX(20, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO21 \
-	ESP32_PINMUX(21, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO21 ESP32_PINMUX(21, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO22 \
-	ESP32_PINMUX(22, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO22 ESP32_PINMUX(22, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO23 \
-	ESP32_PINMUX(23, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO23 ESP32_PINMUX(23, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO25 \
-	ESP32_PINMUX(25, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO25 ESP32_PINMUX(25, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO26 \
-	ESP32_PINMUX(26, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO26 ESP32_PINMUX(26, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO27 \
-	ESP32_PINMUX(27, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO27 ESP32_PINMUX(27, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO32 \
-	ESP32_PINMUX(32, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO32 ESP32_PINMUX(32, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO33 \
-	ESP32_PINMUX(33, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO33 ESP32_PINMUX(33, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO34 \
-	ESP32_PINMUX(34, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO34 ESP32_PINMUX(34, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO35 \
-	ESP32_PINMUX(35, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO35 ESP32_PINMUX(35, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO36 \
-	ESP32_PINMUX(36, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO36 ESP32_PINMUX(36, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO37 \
-	ESP32_PINMUX(37, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO37 ESP32_PINMUX(37, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO38 \
-	ESP32_PINMUX(38, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO38 ESP32_PINMUX(38, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC1_GPIO39 \
-	ESP32_PINMUX(39, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
+#define MCPWM1_SYNC1_GPIO39 ESP32_PINMUX(39, ESP_PWM1_SYNC1_IN, ESP_NOSIG)
 
 /* MCPWM1_SYNC2 */
-#define MCPWM1_SYNC2_GPIO0 \
-	ESP32_PINMUX(0, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO0 ESP32_PINMUX(0, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO1 \
-	ESP32_PINMUX(1, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO1 ESP32_PINMUX(1, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO2 \
-	ESP32_PINMUX(2, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO2 ESP32_PINMUX(2, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO3 \
-	ESP32_PINMUX(3, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO3 ESP32_PINMUX(3, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO4 \
-	ESP32_PINMUX(4, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO4 ESP32_PINMUX(4, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO5 \
-	ESP32_PINMUX(5, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO5 ESP32_PINMUX(5, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO6 \
-	ESP32_PINMUX(6, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO6 ESP32_PINMUX(6, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO7 \
-	ESP32_PINMUX(7, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO7 ESP32_PINMUX(7, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO8 \
-	ESP32_PINMUX(8, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO8 ESP32_PINMUX(8, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO9 \
-	ESP32_PINMUX(9, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO9 ESP32_PINMUX(9, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO10 \
-	ESP32_PINMUX(10, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO10 ESP32_PINMUX(10, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO11 \
-	ESP32_PINMUX(11, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO11 ESP32_PINMUX(11, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO12 \
-	ESP32_PINMUX(12, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO12 ESP32_PINMUX(12, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO13 \
-	ESP32_PINMUX(13, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO13 ESP32_PINMUX(13, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO14 \
-	ESP32_PINMUX(14, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO14 ESP32_PINMUX(14, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO15 \
-	ESP32_PINMUX(15, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO15 ESP32_PINMUX(15, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO16 \
-	ESP32_PINMUX(16, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO16 ESP32_PINMUX(16, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO17 \
-	ESP32_PINMUX(17, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO17 ESP32_PINMUX(17, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO18 \
-	ESP32_PINMUX(18, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO18 ESP32_PINMUX(18, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO19 \
-	ESP32_PINMUX(19, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO19 ESP32_PINMUX(19, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO20 \
-	ESP32_PINMUX(20, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO20 ESP32_PINMUX(20, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO21 \
-	ESP32_PINMUX(21, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO21 ESP32_PINMUX(21, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO22 \
-	ESP32_PINMUX(22, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO22 ESP32_PINMUX(22, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO23 \
-	ESP32_PINMUX(23, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO23 ESP32_PINMUX(23, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO25 \
-	ESP32_PINMUX(25, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO25 ESP32_PINMUX(25, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO26 \
-	ESP32_PINMUX(26, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO26 ESP32_PINMUX(26, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO27 \
-	ESP32_PINMUX(27, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO27 ESP32_PINMUX(27, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO32 \
-	ESP32_PINMUX(32, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO32 ESP32_PINMUX(32, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO33 \
-	ESP32_PINMUX(33, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO33 ESP32_PINMUX(33, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO34 \
-	ESP32_PINMUX(34, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO34 ESP32_PINMUX(34, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO35 \
-	ESP32_PINMUX(35, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO35 ESP32_PINMUX(35, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO36 \
-	ESP32_PINMUX(36, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO36 ESP32_PINMUX(36, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO37 \
-	ESP32_PINMUX(37, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO37 ESP32_PINMUX(37, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO38 \
-	ESP32_PINMUX(38, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO38 ESP32_PINMUX(38, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
-#define MCPWM1_SYNC2_GPIO39 \
-	ESP32_PINMUX(39, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
+#define MCPWM1_SYNC2_GPIO39 ESP32_PINMUX(39, ESP_PWM1_SYNC2_IN, ESP_NOSIG)
 
 /* PCNT0_CH0CTRL */
-#define PCNT0_CH0CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
 /* PCNT0_CH0SIG */
-#define PCNT0_CH0SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
 /* PCNT0_CH1CTRL */
-#define PCNT0_CH1CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
 /* PCNT0_CH1SIG */
-#define PCNT0_CH1SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
 /* PCNT1_CH0CTRL */
-#define PCNT1_CH0CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
 /* PCNT1_CH0SIG */
-#define PCNT1_CH0SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
 /* PCNT1_CH1CTRL */
-#define PCNT1_CH1CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
 /* PCNT1_CH1SIG */
-#define PCNT1_CH1SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
 /* PCNT2_CH0CTRL */
-#define PCNT2_CH0CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
 /* PCNT2_CH0SIG */
-#define PCNT2_CH0SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
 /* PCNT2_CH1CTRL */
-#define PCNT2_CH1CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
 /* PCNT2_CH1SIG */
-#define PCNT2_CH1SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
 /* PCNT3_CH0CTRL */
-#define PCNT3_CH0CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
 /* PCNT3_CH0SIG */
-#define PCNT3_CH0SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
 /* PCNT3_CH1CTRL */
-#define PCNT3_CH1CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
 /* PCNT3_CH1SIG */
-#define PCNT3_CH1SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
 /* PCNT4_CH0CTRL */
-#define PCNT4_CH0CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN4, ESP_NOSIG)
 
 /* PCNT4_CH0SIG */
-#define PCNT4_CH0SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
-#define PCNT4_CH0SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
+#define PCNT4_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN4, ESP_NOSIG)
 
 /* PCNT4_CH1CTRL */
-#define PCNT4_CH1CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN4, ESP_NOSIG)
 
 /* PCNT4_CH1SIG */
-#define PCNT4_CH1SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
-#define PCNT4_CH1SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
+#define PCNT4_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN4, ESP_NOSIG)
 
 /* PCNT5_CH0CTRL */
-#define PCNT5_CH0CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN5, ESP_NOSIG)
 
 /* PCNT5_CH0SIG */
-#define PCNT5_CH0SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
-#define PCNT5_CH0SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
+#define PCNT5_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN5, ESP_NOSIG)
 
 /* PCNT5_CH1CTRL */
-#define PCNT5_CH1CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN5, ESP_NOSIG)
 
 /* PCNT5_CH1SIG */
-#define PCNT5_CH1SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
-#define PCNT5_CH1SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
+#define PCNT5_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN5, ESP_NOSIG)
 
 /* PCNT6_CH0CTRL */
-#define PCNT6_CH0CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN6, ESP_NOSIG)
 
 /* PCNT6_CH0SIG */
-#define PCNT6_CH0SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
-#define PCNT6_CH0SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
+#define PCNT6_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN6, ESP_NOSIG)
 
 /* PCNT6_CH1CTRL */
-#define PCNT6_CH1CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN6, ESP_NOSIG)
 
 /* PCNT6_CH1SIG */
-#define PCNT6_CH1SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
-#define PCNT6_CH1SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
+#define PCNT6_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN6, ESP_NOSIG)
 
 /* PCNT7_CH0CTRL */
-#define PCNT7_CH0CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN7, ESP_NOSIG)
 
 /* PCNT7_CH0SIG */
-#define PCNT7_CH0SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
-#define PCNT7_CH0SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
+#define PCNT7_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN7, ESP_NOSIG)
 
 /* PCNT7_CH1CTRL */
-#define PCNT7_CH1CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO22 ESP32_PINMUX(22, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO23 ESP32_PINMUX(23, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO25 ESP32_PINMUX(25, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN7, ESP_NOSIG)
 
 /* PCNT7_CH1SIG */
-#define PCNT7_CH1SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO22 \
-	ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO22 ESP32_PINMUX(22, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO23 \
-	ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO23 ESP32_PINMUX(23, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO25 \
-	ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO25 ESP32_PINMUX(25, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
-#define PCNT7_CH1SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
+#define PCNT7_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN7, ESP_NOSIG)
 
 /* SDHC0_CD */
-#define SDHC0_CD_GPIO5 \
-	ESP32_PINMUX(5, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO5 ESP32_PINMUX(5, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO6 \
-	ESP32_PINMUX(6, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO6 ESP32_PINMUX(6, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO7 \
-	ESP32_PINMUX(7, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO7 ESP32_PINMUX(7, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO8 \
-	ESP32_PINMUX(8, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO8 ESP32_PINMUX(8, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO9 \
-	ESP32_PINMUX(9, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO9 ESP32_PINMUX(9, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO10 \
-	ESP32_PINMUX(10, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO10 ESP32_PINMUX(10, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO11 \
-	ESP32_PINMUX(11, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO11 ESP32_PINMUX(11, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO16 \
-	ESP32_PINMUX(16, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO16 ESP32_PINMUX(16, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO17 \
-	ESP32_PINMUX(17, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO17 ESP32_PINMUX(17, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO18 \
-	ESP32_PINMUX(18, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO18 ESP32_PINMUX(18, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO19 \
-	ESP32_PINMUX(19, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO19 ESP32_PINMUX(19, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO20 \
-	ESP32_PINMUX(20, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO20 ESP32_PINMUX(20, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO21 \
-	ESP32_PINMUX(21, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO21 ESP32_PINMUX(21, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO22 \
-	ESP32_PINMUX(22, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO22 ESP32_PINMUX(22, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO23 \
-	ESP32_PINMUX(23, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO23 ESP32_PINMUX(23, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO25 \
-	ESP32_PINMUX(25, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO25 ESP32_PINMUX(25, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO26 \
-	ESP32_PINMUX(26, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO26 ESP32_PINMUX(26, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO27 \
-	ESP32_PINMUX(27, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO27 ESP32_PINMUX(27, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO32 \
-	ESP32_PINMUX(32, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO32 ESP32_PINMUX(32, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO33 \
-	ESP32_PINMUX(33, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO33 ESP32_PINMUX(33, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO34 \
-	ESP32_PINMUX(34, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO34 ESP32_PINMUX(34, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO35 \
-	ESP32_PINMUX(35, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO35 ESP32_PINMUX(35, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO36 \
-	ESP32_PINMUX(36, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO36 ESP32_PINMUX(36, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO37 \
-	ESP32_PINMUX(37, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO37 ESP32_PINMUX(37, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO38 \
-	ESP32_PINMUX(38, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO38 ESP32_PINMUX(38, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
-#define SDHC0_CD_GPIO39 \
-	ESP32_PINMUX(39, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
+#define SDHC0_CD_GPIO39 ESP32_PINMUX(39, ESP_HOST_CARD_DETECT_N_2, ESP_NOSIG)
 
 /* SDHC0_WP */
-#define SDHC0_WP_GPIO5 \
-	ESP32_PINMUX(5, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO5 ESP32_PINMUX(5, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO6 \
-	ESP32_PINMUX(6, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO6 ESP32_PINMUX(6, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO7 \
-	ESP32_PINMUX(7, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO7 ESP32_PINMUX(7, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO8 \
-	ESP32_PINMUX(8, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO8 ESP32_PINMUX(8, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO9 \
-	ESP32_PINMUX(9, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO9 ESP32_PINMUX(9, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO10 \
-	ESP32_PINMUX(10, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO10 ESP32_PINMUX(10, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO11 \
-	ESP32_PINMUX(11, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO11 ESP32_PINMUX(11, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO16 \
-	ESP32_PINMUX(16, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO16 ESP32_PINMUX(16, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO17 \
-	ESP32_PINMUX(17, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO17 ESP32_PINMUX(17, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO18 \
-	ESP32_PINMUX(18, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO18 ESP32_PINMUX(18, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO19 \
-	ESP32_PINMUX(19, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO19 ESP32_PINMUX(19, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO20 \
-	ESP32_PINMUX(20, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO20 ESP32_PINMUX(20, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO21 \
-	ESP32_PINMUX(21, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO21 ESP32_PINMUX(21, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO22 \
-	ESP32_PINMUX(22, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO22 ESP32_PINMUX(22, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO23 \
-	ESP32_PINMUX(23, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO23 ESP32_PINMUX(23, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO25 \
-	ESP32_PINMUX(25, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO25 ESP32_PINMUX(25, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO26 \
-	ESP32_PINMUX(26, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO26 ESP32_PINMUX(26, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO27 \
-	ESP32_PINMUX(27, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO27 ESP32_PINMUX(27, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO32 \
-	ESP32_PINMUX(32, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO32 ESP32_PINMUX(32, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO33 \
-	ESP32_PINMUX(33, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO33 ESP32_PINMUX(33, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO34 \
-	ESP32_PINMUX(34, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO34 ESP32_PINMUX(34, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO35 \
-	ESP32_PINMUX(35, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO35 ESP32_PINMUX(35, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO36 \
-	ESP32_PINMUX(36, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO36 ESP32_PINMUX(36, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO37 \
-	ESP32_PINMUX(37, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO37 ESP32_PINMUX(37, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO38 \
-	ESP32_PINMUX(38, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO38 ESP32_PINMUX(38, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
-#define SDHC0_WP_GPIO39 \
-	ESP32_PINMUX(39, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
+#define SDHC0_WP_GPIO39 ESP32_PINMUX(39, ESP_HOST_CARD_WRITE_PRT_2, ESP_NOSIG)
 
 /* SMI_MDC */
-#define SMI_MDC_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_EMAC_MDC_O)
 
-#define SMI_MDC_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_EMAC_MDC_O)
+#define SMI_MDC_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_EMAC_MDC_O)
 
 /* SMI_MDIO */
-#define SMI_MDIO_GPIO0 \
-	ESP32_PINMUX(0, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO0 ESP32_PINMUX(0, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO1 \
-	ESP32_PINMUX(1, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO1 ESP32_PINMUX(1, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO2 \
-	ESP32_PINMUX(2, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO2 ESP32_PINMUX(2, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO3 \
-	ESP32_PINMUX(3, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO3 ESP32_PINMUX(3, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO4 \
-	ESP32_PINMUX(4, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO4 ESP32_PINMUX(4, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO5 \
-	ESP32_PINMUX(5, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO5 ESP32_PINMUX(5, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO6 \
-	ESP32_PINMUX(6, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO6 ESP32_PINMUX(6, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO7 \
-	ESP32_PINMUX(7, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO7 ESP32_PINMUX(7, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO8 \
-	ESP32_PINMUX(8, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO8 ESP32_PINMUX(8, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO9 \
-	ESP32_PINMUX(9, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO9 ESP32_PINMUX(9, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO10 \
-	ESP32_PINMUX(10, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO10 ESP32_PINMUX(10, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO11 \
-	ESP32_PINMUX(11, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO11 ESP32_PINMUX(11, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO12 \
-	ESP32_PINMUX(12, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO12 ESP32_PINMUX(12, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO13 \
-	ESP32_PINMUX(13, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO13 ESP32_PINMUX(13, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO14 \
-	ESP32_PINMUX(14, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO14 ESP32_PINMUX(14, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO15 \
-	ESP32_PINMUX(15, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO15 ESP32_PINMUX(15, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO16 \
-	ESP32_PINMUX(16, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO16 ESP32_PINMUX(16, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO17 \
-	ESP32_PINMUX(17, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO17 ESP32_PINMUX(17, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO18 \
-	ESP32_PINMUX(18, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO18 ESP32_PINMUX(18, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO19 \
-	ESP32_PINMUX(19, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO19 ESP32_PINMUX(19, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO20 \
-	ESP32_PINMUX(20, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO20 ESP32_PINMUX(20, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO21 \
-	ESP32_PINMUX(21, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO21 ESP32_PINMUX(21, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO22 \
-	ESP32_PINMUX(22, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO22 ESP32_PINMUX(22, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO23 \
-	ESP32_PINMUX(23, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO23 ESP32_PINMUX(23, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO25 \
-	ESP32_PINMUX(25, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO25 ESP32_PINMUX(25, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO26 \
-	ESP32_PINMUX(26, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO26 ESP32_PINMUX(26, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO27 \
-	ESP32_PINMUX(27, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO27 ESP32_PINMUX(27, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO32 \
-	ESP32_PINMUX(32, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO32 ESP32_PINMUX(32, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
-#define SMI_MDIO_GPIO33 \
-	ESP32_PINMUX(33, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
+#define SMI_MDIO_GPIO33 ESP32_PINMUX(33, ESP_EMAC_MDI_I, ESP_EMAC_MDO_O)
 
 /* SPIM2_CSEL */
-#define SPIM2_CSEL_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_HSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_HSPICS0_OUT)
+#define SPIM2_CSEL_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_HSPICS0_OUT)
 
 /* SPIM2_CSEL1 */
-#define SPIM2_CSEL1_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_HSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_HSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_HSPICS1_OUT)
 
 /* SPIM2_CSEL2 */
-#define SPIM2_CSEL2_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_HSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_HSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_HSPICS2_OUT)
 
 /* SPIM2_MISO */
-#define SPIM2_MISO_GPIO0 \
-	ESP32_PINMUX(0, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO0 ESP32_PINMUX(0, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO1 \
-	ESP32_PINMUX(1, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO1 ESP32_PINMUX(1, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO2 \
-	ESP32_PINMUX(2, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO2 ESP32_PINMUX(2, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO3 \
-	ESP32_PINMUX(3, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO3 ESP32_PINMUX(3, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO4 \
-	ESP32_PINMUX(4, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO4 ESP32_PINMUX(4, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO5 \
-	ESP32_PINMUX(5, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO5 ESP32_PINMUX(5, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO6 \
-	ESP32_PINMUX(6, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO6 ESP32_PINMUX(6, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO7 \
-	ESP32_PINMUX(7, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO7 ESP32_PINMUX(7, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO8 \
-	ESP32_PINMUX(8, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO8 ESP32_PINMUX(8, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO9 \
-	ESP32_PINMUX(9, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO9 ESP32_PINMUX(9, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO10 \
-	ESP32_PINMUX(10, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO10 ESP32_PINMUX(10, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO11 \
-	ESP32_PINMUX(11, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO11 ESP32_PINMUX(11, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO12 \
-	ESP32_PINMUX(12, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO12 ESP32_PINMUX(12, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO13 \
-	ESP32_PINMUX(13, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO13 ESP32_PINMUX(13, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO14 \
-	ESP32_PINMUX(14, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO14 ESP32_PINMUX(14, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO15 \
-	ESP32_PINMUX(15, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO15 ESP32_PINMUX(15, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO16 \
-	ESP32_PINMUX(16, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO16 ESP32_PINMUX(16, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO17 \
-	ESP32_PINMUX(17, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO17 ESP32_PINMUX(17, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO18 \
-	ESP32_PINMUX(18, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO18 ESP32_PINMUX(18, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO19 \
-	ESP32_PINMUX(19, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO19 ESP32_PINMUX(19, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO20 \
-	ESP32_PINMUX(20, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO20 ESP32_PINMUX(20, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO21 \
-	ESP32_PINMUX(21, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO21 ESP32_PINMUX(21, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO22 \
-	ESP32_PINMUX(22, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO22 ESP32_PINMUX(22, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO23 \
-	ESP32_PINMUX(23, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO23 ESP32_PINMUX(23, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO25 \
-	ESP32_PINMUX(25, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO25 ESP32_PINMUX(25, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO26 \
-	ESP32_PINMUX(26, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO26 ESP32_PINMUX(26, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO27 \
-	ESP32_PINMUX(27, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO27 ESP32_PINMUX(27, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO32 \
-	ESP32_PINMUX(32, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO32 ESP32_PINMUX(32, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO33 \
-	ESP32_PINMUX(33, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO33 ESP32_PINMUX(33, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO34 \
-	ESP32_PINMUX(34, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO34 ESP32_PINMUX(34, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO35 \
-	ESP32_PINMUX(35, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO35 ESP32_PINMUX(35, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO36 \
-	ESP32_PINMUX(36, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO36 ESP32_PINMUX(36, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO37 \
-	ESP32_PINMUX(37, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO37 ESP32_PINMUX(37, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO38 \
-	ESP32_PINMUX(38, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO38 ESP32_PINMUX(38, ESP_HSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO39 \
-	ESP32_PINMUX(39, ESP_HSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO39 ESP32_PINMUX(39, ESP_HSPIQ_IN, ESP_NOSIG)
 
 /* SPIM2_MOSI */
-#define SPIM2_MOSI_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_HSPID_OUT)
 
-#define SPIM2_MOSI_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_HSPID_OUT)
+#define SPIM2_MOSI_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_HSPID_OUT)
 
 /* SPIM2_SCLK */
-#define SPIM2_SCLK_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_HSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_HSPICLK_OUT)
+#define SPIM2_SCLK_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_HSPICLK_OUT)
 
 /* SPIM3_CSEL */
-#define SPIM3_CSEL_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_VSPICS0_OUT)
 
-#define SPIM3_CSEL_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_VSPICS0_OUT)
+#define SPIM3_CSEL_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_VSPICS0_OUT)
 
 /* SPIM3_CSEL1 */
-#define SPIM3_CSEL1_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_VSPICS1_OUT)
 
-#define SPIM3_CSEL1_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_VSPICS1_OUT)
+#define SPIM3_CSEL1_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_VSPICS1_OUT)
 
 /* SPIM3_CSEL2 */
-#define SPIM3_CSEL2_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_VSPICS2_OUT)
 
-#define SPIM3_CSEL2_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_VSPICS2_OUT)
+#define SPIM3_CSEL2_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_VSPICS2_OUT)
 
 /* SPIM3_MISO */
-#define SPIM3_MISO_GPIO0 \
-	ESP32_PINMUX(0, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO0 ESP32_PINMUX(0, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO1 \
-	ESP32_PINMUX(1, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO1 ESP32_PINMUX(1, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO2 \
-	ESP32_PINMUX(2, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO2 ESP32_PINMUX(2, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO3 \
-	ESP32_PINMUX(3, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO3 ESP32_PINMUX(3, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO4 \
-	ESP32_PINMUX(4, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO4 ESP32_PINMUX(4, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO5 \
-	ESP32_PINMUX(5, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO5 ESP32_PINMUX(5, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO6 \
-	ESP32_PINMUX(6, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO6 ESP32_PINMUX(6, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO7 \
-	ESP32_PINMUX(7, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO7 ESP32_PINMUX(7, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO8 \
-	ESP32_PINMUX(8, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO8 ESP32_PINMUX(8, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO9 \
-	ESP32_PINMUX(9, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO9 ESP32_PINMUX(9, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO10 \
-	ESP32_PINMUX(10, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO10 ESP32_PINMUX(10, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO11 \
-	ESP32_PINMUX(11, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO11 ESP32_PINMUX(11, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO12 \
-	ESP32_PINMUX(12, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO12 ESP32_PINMUX(12, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO13 \
-	ESP32_PINMUX(13, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO13 ESP32_PINMUX(13, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO14 \
-	ESP32_PINMUX(14, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO14 ESP32_PINMUX(14, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO15 \
-	ESP32_PINMUX(15, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO15 ESP32_PINMUX(15, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO16 \
-	ESP32_PINMUX(16, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO16 ESP32_PINMUX(16, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO17 \
-	ESP32_PINMUX(17, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO17 ESP32_PINMUX(17, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO18 \
-	ESP32_PINMUX(18, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO18 ESP32_PINMUX(18, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO19 \
-	ESP32_PINMUX(19, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO19 ESP32_PINMUX(19, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO20 \
-	ESP32_PINMUX(20, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO20 ESP32_PINMUX(20, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO21 \
-	ESP32_PINMUX(21, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO21 ESP32_PINMUX(21, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO22 \
-	ESP32_PINMUX(22, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO22 ESP32_PINMUX(22, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO23 \
-	ESP32_PINMUX(23, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO23 ESP32_PINMUX(23, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO25 \
-	ESP32_PINMUX(25, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO25 ESP32_PINMUX(25, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO26 \
-	ESP32_PINMUX(26, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO26 ESP32_PINMUX(26, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO27 \
-	ESP32_PINMUX(27, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO27 ESP32_PINMUX(27, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO32 \
-	ESP32_PINMUX(32, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO32 ESP32_PINMUX(32, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO33 \
-	ESP32_PINMUX(33, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO33 ESP32_PINMUX(33, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO34 \
-	ESP32_PINMUX(34, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO34 ESP32_PINMUX(34, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO35 \
-	ESP32_PINMUX(35, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO35 ESP32_PINMUX(35, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO36 \
-	ESP32_PINMUX(36, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO36 ESP32_PINMUX(36, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO37 \
-	ESP32_PINMUX(37, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO37 ESP32_PINMUX(37, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO38 \
-	ESP32_PINMUX(38, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO38 ESP32_PINMUX(38, ESP_VSPIQ_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO39 \
-	ESP32_PINMUX(39, ESP_VSPIQ_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO39 ESP32_PINMUX(39, ESP_VSPIQ_IN, ESP_NOSIG)
 
 /* SPIM3_MOSI */
-#define SPIM3_MOSI_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_VSPID_OUT)
 
-#define SPIM3_MOSI_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_VSPID_OUT)
+#define SPIM3_MOSI_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_VSPID_OUT)
 
 /* SPIM3_SCLK */
-#define SPIM3_SCLK_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_VSPICLK_OUT)
 
-#define SPIM3_SCLK_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_VSPICLK_OUT)
+#define SPIM3_SCLK_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_VSPICLK_OUT)
 
 /* TWAI_BUS_OFF */
-#define TWAI_BUS_OFF_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
 /* TWAI_CLKOUT */
-#define TWAI_CLKOUT_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
 /* TWAI_RX */
-#define TWAI_RX_GPIO0 \
-	ESP32_PINMUX(0, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO0 ESP32_PINMUX(0, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO1 \
-	ESP32_PINMUX(1, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO1 ESP32_PINMUX(1, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO2 \
-	ESP32_PINMUX(2, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO2 ESP32_PINMUX(2, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO3 \
-	ESP32_PINMUX(3, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO3 ESP32_PINMUX(3, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO4 \
-	ESP32_PINMUX(4, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO4 ESP32_PINMUX(4, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO5 \
-	ESP32_PINMUX(5, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO5 ESP32_PINMUX(5, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO6 \
-	ESP32_PINMUX(6, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO6 ESP32_PINMUX(6, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO7 \
-	ESP32_PINMUX(7, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO7 ESP32_PINMUX(7, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO8 \
-	ESP32_PINMUX(8, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO8 ESP32_PINMUX(8, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO9 \
-	ESP32_PINMUX(9, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO9 ESP32_PINMUX(9, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO10 \
-	ESP32_PINMUX(10, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO10 ESP32_PINMUX(10, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO11 \
-	ESP32_PINMUX(11, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO11 ESP32_PINMUX(11, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO12 \
-	ESP32_PINMUX(12, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO12 ESP32_PINMUX(12, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO13 \
-	ESP32_PINMUX(13, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO13 ESP32_PINMUX(13, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO14 \
-	ESP32_PINMUX(14, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO14 ESP32_PINMUX(14, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO15 \
-	ESP32_PINMUX(15, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO15 ESP32_PINMUX(15, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO16 \
-	ESP32_PINMUX(16, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO16 ESP32_PINMUX(16, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO17 \
-	ESP32_PINMUX(17, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO17 ESP32_PINMUX(17, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO18 \
-	ESP32_PINMUX(18, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO18 ESP32_PINMUX(18, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO19 \
-	ESP32_PINMUX(19, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO19 ESP32_PINMUX(19, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO20 \
-	ESP32_PINMUX(20, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO20 ESP32_PINMUX(20, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO21 \
-	ESP32_PINMUX(21, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO21 ESP32_PINMUX(21, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO22 \
-	ESP32_PINMUX(22, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO22 ESP32_PINMUX(22, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO23 \
-	ESP32_PINMUX(23, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO23 ESP32_PINMUX(23, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO25 \
-	ESP32_PINMUX(25, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO25 ESP32_PINMUX(25, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO26 \
-	ESP32_PINMUX(26, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO26 ESP32_PINMUX(26, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO27 \
-	ESP32_PINMUX(27, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO27 ESP32_PINMUX(27, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO32 \
-	ESP32_PINMUX(32, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO32 ESP32_PINMUX(32, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO33 \
-	ESP32_PINMUX(33, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO33 ESP32_PINMUX(33, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO34 \
-	ESP32_PINMUX(34, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO34 ESP32_PINMUX(34, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO35 \
-	ESP32_PINMUX(35, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO35 ESP32_PINMUX(35, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO36 \
-	ESP32_PINMUX(36, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO36 ESP32_PINMUX(36, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO37 \
-	ESP32_PINMUX(37, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO37 ESP32_PINMUX(37, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO38 \
-	ESP32_PINMUX(38, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO38 ESP32_PINMUX(38, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO39 \
-	ESP32_PINMUX(39, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO39 ESP32_PINMUX(39, ESP_TWAI_RX, ESP_NOSIG)
 
 /* TWAI_TX */
-#define TWAI_TX_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_TWAI_TX)
 
 /* UART0_CTS */
-#define UART0_CTS_GPIO0 \
-	ESP32_PINMUX(0, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO0 ESP32_PINMUX(0, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO1 \
-	ESP32_PINMUX(1, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO1 ESP32_PINMUX(1, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO2 \
-	ESP32_PINMUX(2, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO2 ESP32_PINMUX(2, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO3 \
-	ESP32_PINMUX(3, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO3 ESP32_PINMUX(3, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO4 \
-	ESP32_PINMUX(4, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO4 ESP32_PINMUX(4, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO5 \
-	ESP32_PINMUX(5, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO5 ESP32_PINMUX(5, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO6 \
-	ESP32_PINMUX(6, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO6 ESP32_PINMUX(6, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO7 \
-	ESP32_PINMUX(7, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO7 ESP32_PINMUX(7, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO8 \
-	ESP32_PINMUX(8, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO8 ESP32_PINMUX(8, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO9 \
-	ESP32_PINMUX(9, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO9 ESP32_PINMUX(9, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO10 \
-	ESP32_PINMUX(10, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO10 ESP32_PINMUX(10, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO11 \
-	ESP32_PINMUX(11, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO11 ESP32_PINMUX(11, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO12 \
-	ESP32_PINMUX(12, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO12 ESP32_PINMUX(12, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO13 \
-	ESP32_PINMUX(13, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO13 ESP32_PINMUX(13, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO14 \
-	ESP32_PINMUX(14, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO14 ESP32_PINMUX(14, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO15 \
-	ESP32_PINMUX(15, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO15 ESP32_PINMUX(15, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO16 \
-	ESP32_PINMUX(16, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO16 ESP32_PINMUX(16, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO17 \
-	ESP32_PINMUX(17, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO17 ESP32_PINMUX(17, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO18 \
-	ESP32_PINMUX(18, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO18 ESP32_PINMUX(18, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO19 \
-	ESP32_PINMUX(19, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO19 ESP32_PINMUX(19, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO20 \
-	ESP32_PINMUX(20, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO20 ESP32_PINMUX(20, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO21 \
-	ESP32_PINMUX(21, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO21 ESP32_PINMUX(21, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO22 \
-	ESP32_PINMUX(22, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO22 ESP32_PINMUX(22, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO23 \
-	ESP32_PINMUX(23, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO23 ESP32_PINMUX(23, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO25 \
-	ESP32_PINMUX(25, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO25 ESP32_PINMUX(25, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO26 \
-	ESP32_PINMUX(26, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO26 ESP32_PINMUX(26, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO27 \
-	ESP32_PINMUX(27, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO27 ESP32_PINMUX(27, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO32 \
-	ESP32_PINMUX(32, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO32 ESP32_PINMUX(32, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO33 \
-	ESP32_PINMUX(33, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO33 ESP32_PINMUX(33, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO34 \
-	ESP32_PINMUX(34, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO34 ESP32_PINMUX(34, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO35 \
-	ESP32_PINMUX(35, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO35 ESP32_PINMUX(35, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO36 \
-	ESP32_PINMUX(36, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO36 ESP32_PINMUX(36, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO37 \
-	ESP32_PINMUX(37, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO37 ESP32_PINMUX(37, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO38 \
-	ESP32_PINMUX(38, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO38 ESP32_PINMUX(38, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO39 \
-	ESP32_PINMUX(39, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO39 ESP32_PINMUX(39, ESP_U0CTS_IN, ESP_NOSIG)
 
 /* UART0_DSR */
-#define UART0_DSR_GPIO0 \
-	ESP32_PINMUX(0, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO0 ESP32_PINMUX(0, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO1 \
-	ESP32_PINMUX(1, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO1 ESP32_PINMUX(1, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO2 \
-	ESP32_PINMUX(2, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO2 ESP32_PINMUX(2, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO3 \
-	ESP32_PINMUX(3, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO3 ESP32_PINMUX(3, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO4 \
-	ESP32_PINMUX(4, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO4 ESP32_PINMUX(4, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO5 \
-	ESP32_PINMUX(5, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO5 ESP32_PINMUX(5, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO6 \
-	ESP32_PINMUX(6, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO6 ESP32_PINMUX(6, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO7 \
-	ESP32_PINMUX(7, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO7 ESP32_PINMUX(7, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO8 \
-	ESP32_PINMUX(8, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO8 ESP32_PINMUX(8, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO9 \
-	ESP32_PINMUX(9, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO9 ESP32_PINMUX(9, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO10 \
-	ESP32_PINMUX(10, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO10 ESP32_PINMUX(10, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO11 \
-	ESP32_PINMUX(11, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO11 ESP32_PINMUX(11, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO12 \
-	ESP32_PINMUX(12, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO12 ESP32_PINMUX(12, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO13 \
-	ESP32_PINMUX(13, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO13 ESP32_PINMUX(13, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO14 \
-	ESP32_PINMUX(14, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO14 ESP32_PINMUX(14, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO15 \
-	ESP32_PINMUX(15, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO15 ESP32_PINMUX(15, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO16 \
-	ESP32_PINMUX(16, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO16 ESP32_PINMUX(16, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO17 \
-	ESP32_PINMUX(17, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO17 ESP32_PINMUX(17, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO18 \
-	ESP32_PINMUX(18, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO18 ESP32_PINMUX(18, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO19 \
-	ESP32_PINMUX(19, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO19 ESP32_PINMUX(19, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO20 \
-	ESP32_PINMUX(20, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO20 ESP32_PINMUX(20, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO21 \
-	ESP32_PINMUX(21, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO21 ESP32_PINMUX(21, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO22 \
-	ESP32_PINMUX(22, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO22 ESP32_PINMUX(22, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO23 \
-	ESP32_PINMUX(23, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO23 ESP32_PINMUX(23, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO25 \
-	ESP32_PINMUX(25, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO25 ESP32_PINMUX(25, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO26 \
-	ESP32_PINMUX(26, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO26 ESP32_PINMUX(26, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO27 \
-	ESP32_PINMUX(27, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO27 ESP32_PINMUX(27, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO32 \
-	ESP32_PINMUX(32, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO32 ESP32_PINMUX(32, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO33 \
-	ESP32_PINMUX(33, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO33 ESP32_PINMUX(33, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO34 \
-	ESP32_PINMUX(34, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO34 ESP32_PINMUX(34, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO35 \
-	ESP32_PINMUX(35, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO35 ESP32_PINMUX(35, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO36 \
-	ESP32_PINMUX(36, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO36 ESP32_PINMUX(36, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO37 \
-	ESP32_PINMUX(37, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO37 ESP32_PINMUX(37, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO38 \
-	ESP32_PINMUX(38, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO38 ESP32_PINMUX(38, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO39 \
-	ESP32_PINMUX(39, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO39 ESP32_PINMUX(39, ESP_U0DSR_IN, ESP_NOSIG)
 
 /* UART0_DTR */
-#define UART0_DTR_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_U0DTR_OUT)
 
 /* UART0_RTS */
-#define UART0_RTS_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U0RTS_OUT)
 
 /* UART0_RX */
-#define UART0_RX_GPIO0 \
-	ESP32_PINMUX(0, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO0 ESP32_PINMUX(0, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO1 \
-	ESP32_PINMUX(1, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO1 ESP32_PINMUX(1, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO2 \
-	ESP32_PINMUX(2, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO2 ESP32_PINMUX(2, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO3 \
-	ESP32_PINMUX(3, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO3 ESP32_PINMUX(3, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO4 \
-	ESP32_PINMUX(4, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO4 ESP32_PINMUX(4, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO5 \
-	ESP32_PINMUX(5, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO5 ESP32_PINMUX(5, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO6 \
-	ESP32_PINMUX(6, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO6 ESP32_PINMUX(6, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO7 \
-	ESP32_PINMUX(7, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO7 ESP32_PINMUX(7, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO8 \
-	ESP32_PINMUX(8, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO8 ESP32_PINMUX(8, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO9 \
-	ESP32_PINMUX(9, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO9 ESP32_PINMUX(9, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO10 \
-	ESP32_PINMUX(10, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO10 ESP32_PINMUX(10, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO11 \
-	ESP32_PINMUX(11, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO11 ESP32_PINMUX(11, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO12 \
-	ESP32_PINMUX(12, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO12 ESP32_PINMUX(12, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO13 \
-	ESP32_PINMUX(13, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO13 ESP32_PINMUX(13, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO14 \
-	ESP32_PINMUX(14, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO14 ESP32_PINMUX(14, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO15 \
-	ESP32_PINMUX(15, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO15 ESP32_PINMUX(15, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO16 \
-	ESP32_PINMUX(16, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO16 ESP32_PINMUX(16, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO17 \
-	ESP32_PINMUX(17, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO17 ESP32_PINMUX(17, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO18 \
-	ESP32_PINMUX(18, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO18 ESP32_PINMUX(18, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO19 \
-	ESP32_PINMUX(19, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO19 ESP32_PINMUX(19, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO20 \
-	ESP32_PINMUX(20, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO20 ESP32_PINMUX(20, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO21 \
-	ESP32_PINMUX(21, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO21 ESP32_PINMUX(21, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO22 \
-	ESP32_PINMUX(22, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO22 ESP32_PINMUX(22, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO23 \
-	ESP32_PINMUX(23, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO23 ESP32_PINMUX(23, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO25 \
-	ESP32_PINMUX(25, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO25 ESP32_PINMUX(25, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO26 \
-	ESP32_PINMUX(26, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO26 ESP32_PINMUX(26, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO27 \
-	ESP32_PINMUX(27, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO27 ESP32_PINMUX(27, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO32 \
-	ESP32_PINMUX(32, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO32 ESP32_PINMUX(32, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO33 \
-	ESP32_PINMUX(33, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO33 ESP32_PINMUX(33, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO34 \
-	ESP32_PINMUX(34, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO34 ESP32_PINMUX(34, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO35 \
-	ESP32_PINMUX(35, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO35 ESP32_PINMUX(35, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO36 \
-	ESP32_PINMUX(36, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO36 ESP32_PINMUX(36, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO37 \
-	ESP32_PINMUX(37, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO37 ESP32_PINMUX(37, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO38 \
-	ESP32_PINMUX(38, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO38 ESP32_PINMUX(38, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO39 \
-	ESP32_PINMUX(39, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO39 ESP32_PINMUX(39, ESP_U0RXD_IN, ESP_NOSIG)
 
 /* UART0_TX */
-#define UART0_TX_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U0TXD_OUT)
 
 /* UART1_CTS */
-#define UART1_CTS_GPIO0 \
-	ESP32_PINMUX(0, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO0 ESP32_PINMUX(0, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO1 \
-	ESP32_PINMUX(1, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO1 ESP32_PINMUX(1, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO2 \
-	ESP32_PINMUX(2, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO2 ESP32_PINMUX(2, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO3 \
-	ESP32_PINMUX(3, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO3 ESP32_PINMUX(3, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO4 \
-	ESP32_PINMUX(4, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO4 ESP32_PINMUX(4, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO5 \
-	ESP32_PINMUX(5, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO5 ESP32_PINMUX(5, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO6 \
-	ESP32_PINMUX(6, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO6 ESP32_PINMUX(6, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO7 \
-	ESP32_PINMUX(7, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO7 ESP32_PINMUX(7, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO8 \
-	ESP32_PINMUX(8, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO8 ESP32_PINMUX(8, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO9 \
-	ESP32_PINMUX(9, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO9 ESP32_PINMUX(9, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO10 \
-	ESP32_PINMUX(10, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO10 ESP32_PINMUX(10, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO11 \
-	ESP32_PINMUX(11, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO11 ESP32_PINMUX(11, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO12 \
-	ESP32_PINMUX(12, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO12 ESP32_PINMUX(12, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO13 \
-	ESP32_PINMUX(13, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO13 ESP32_PINMUX(13, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO14 \
-	ESP32_PINMUX(14, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO14 ESP32_PINMUX(14, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO15 \
-	ESP32_PINMUX(15, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO15 ESP32_PINMUX(15, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO16 \
-	ESP32_PINMUX(16, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO16 ESP32_PINMUX(16, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO17 \
-	ESP32_PINMUX(17, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO17 ESP32_PINMUX(17, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO18 \
-	ESP32_PINMUX(18, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO18 ESP32_PINMUX(18, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO19 \
-	ESP32_PINMUX(19, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO19 ESP32_PINMUX(19, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO20 \
-	ESP32_PINMUX(20, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO20 ESP32_PINMUX(20, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO21 \
-	ESP32_PINMUX(21, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO21 ESP32_PINMUX(21, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO22 \
-	ESP32_PINMUX(22, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO22 ESP32_PINMUX(22, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO23 \
-	ESP32_PINMUX(23, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO23 ESP32_PINMUX(23, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO25 \
-	ESP32_PINMUX(25, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO25 ESP32_PINMUX(25, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO26 \
-	ESP32_PINMUX(26, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO26 ESP32_PINMUX(26, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO27 \
-	ESP32_PINMUX(27, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO27 ESP32_PINMUX(27, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO32 \
-	ESP32_PINMUX(32, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO32 ESP32_PINMUX(32, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO33 \
-	ESP32_PINMUX(33, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO33 ESP32_PINMUX(33, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO34 \
-	ESP32_PINMUX(34, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO34 ESP32_PINMUX(34, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO35 \
-	ESP32_PINMUX(35, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO35 ESP32_PINMUX(35, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO36 \
-	ESP32_PINMUX(36, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO36 ESP32_PINMUX(36, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO37 \
-	ESP32_PINMUX(37, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO37 ESP32_PINMUX(37, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO38 \
-	ESP32_PINMUX(38, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO38 ESP32_PINMUX(38, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO39 \
-	ESP32_PINMUX(39, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO39 ESP32_PINMUX(39, ESP_U1CTS_IN, ESP_NOSIG)
 
 /* UART1_DSR */
-#define UART1_DSR_GPIO0 \
-	ESP32_PINMUX(0, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO0 ESP32_PINMUX(0, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO1 \
-	ESP32_PINMUX(1, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO1 ESP32_PINMUX(1, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO2 \
-	ESP32_PINMUX(2, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO2 ESP32_PINMUX(2, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO3 \
-	ESP32_PINMUX(3, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO3 ESP32_PINMUX(3, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO4 \
-	ESP32_PINMUX(4, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO4 ESP32_PINMUX(4, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO5 \
-	ESP32_PINMUX(5, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO5 ESP32_PINMUX(5, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO6 \
-	ESP32_PINMUX(6, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO6 ESP32_PINMUX(6, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO7 \
-	ESP32_PINMUX(7, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO7 ESP32_PINMUX(7, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO8 \
-	ESP32_PINMUX(8, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO8 ESP32_PINMUX(8, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO9 \
-	ESP32_PINMUX(9, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO9 ESP32_PINMUX(9, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO10 \
-	ESP32_PINMUX(10, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO10 ESP32_PINMUX(10, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO11 \
-	ESP32_PINMUX(11, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO11 ESP32_PINMUX(11, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO12 \
-	ESP32_PINMUX(12, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO12 ESP32_PINMUX(12, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO13 \
-	ESP32_PINMUX(13, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO13 ESP32_PINMUX(13, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO14 \
-	ESP32_PINMUX(14, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO14 ESP32_PINMUX(14, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO15 \
-	ESP32_PINMUX(15, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO15 ESP32_PINMUX(15, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO16 \
-	ESP32_PINMUX(16, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO16 ESP32_PINMUX(16, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO17 \
-	ESP32_PINMUX(17, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO17 ESP32_PINMUX(17, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO18 \
-	ESP32_PINMUX(18, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO18 ESP32_PINMUX(18, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO19 \
-	ESP32_PINMUX(19, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO19 ESP32_PINMUX(19, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO20 \
-	ESP32_PINMUX(20, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO20 ESP32_PINMUX(20, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO21 \
-	ESP32_PINMUX(21, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO21 ESP32_PINMUX(21, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO22 \
-	ESP32_PINMUX(22, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO22 ESP32_PINMUX(22, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO23 \
-	ESP32_PINMUX(23, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO23 ESP32_PINMUX(23, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO25 \
-	ESP32_PINMUX(25, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO25 ESP32_PINMUX(25, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO26 \
-	ESP32_PINMUX(26, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO26 ESP32_PINMUX(26, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO27 \
-	ESP32_PINMUX(27, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO27 ESP32_PINMUX(27, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO32 \
-	ESP32_PINMUX(32, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO32 ESP32_PINMUX(32, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO33 \
-	ESP32_PINMUX(33, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO33 ESP32_PINMUX(33, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO34 \
-	ESP32_PINMUX(34, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO34 ESP32_PINMUX(34, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO35 \
-	ESP32_PINMUX(35, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO35 ESP32_PINMUX(35, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO36 \
-	ESP32_PINMUX(36, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO36 ESP32_PINMUX(36, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO37 \
-	ESP32_PINMUX(37, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO37 ESP32_PINMUX(37, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO38 \
-	ESP32_PINMUX(38, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO38 ESP32_PINMUX(38, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO39 \
-	ESP32_PINMUX(39, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO39 ESP32_PINMUX(39, ESP_U1DSR_IN, ESP_NOSIG)
 
 /* UART1_DTR */
-#define UART1_DTR_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_U1DTR_OUT)
 
 /* UART1_RTS */
-#define UART1_RTS_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U1RTS_OUT)
 
 /* UART1_RX */
-#define UART1_RX_GPIO0 \
-	ESP32_PINMUX(0, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO0 ESP32_PINMUX(0, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO1 \
-	ESP32_PINMUX(1, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO1 ESP32_PINMUX(1, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO2 \
-	ESP32_PINMUX(2, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO2 ESP32_PINMUX(2, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO3 \
-	ESP32_PINMUX(3, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO3 ESP32_PINMUX(3, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO4 \
-	ESP32_PINMUX(4, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO4 ESP32_PINMUX(4, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO5 \
-	ESP32_PINMUX(5, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO5 ESP32_PINMUX(5, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO6 \
-	ESP32_PINMUX(6, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO6 ESP32_PINMUX(6, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO7 \
-	ESP32_PINMUX(7, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO7 ESP32_PINMUX(7, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO8 \
-	ESP32_PINMUX(8, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO8 ESP32_PINMUX(8, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO9 \
-	ESP32_PINMUX(9, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO9 ESP32_PINMUX(9, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO10 \
-	ESP32_PINMUX(10, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO10 ESP32_PINMUX(10, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO11 \
-	ESP32_PINMUX(11, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO11 ESP32_PINMUX(11, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO12 \
-	ESP32_PINMUX(12, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO12 ESP32_PINMUX(12, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO13 \
-	ESP32_PINMUX(13, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO13 ESP32_PINMUX(13, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO14 \
-	ESP32_PINMUX(14, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO14 ESP32_PINMUX(14, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO15 \
-	ESP32_PINMUX(15, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO15 ESP32_PINMUX(15, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO16 \
-	ESP32_PINMUX(16, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO16 ESP32_PINMUX(16, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO17 \
-	ESP32_PINMUX(17, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO17 ESP32_PINMUX(17, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO18 \
-	ESP32_PINMUX(18, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO18 ESP32_PINMUX(18, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO19 \
-	ESP32_PINMUX(19, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO19 ESP32_PINMUX(19, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO20 \
-	ESP32_PINMUX(20, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO20 ESP32_PINMUX(20, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO21 \
-	ESP32_PINMUX(21, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO21 ESP32_PINMUX(21, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO22 \
-	ESP32_PINMUX(22, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO22 ESP32_PINMUX(22, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO23 \
-	ESP32_PINMUX(23, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO23 ESP32_PINMUX(23, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO25 \
-	ESP32_PINMUX(25, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO25 ESP32_PINMUX(25, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO26 \
-	ESP32_PINMUX(26, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO26 ESP32_PINMUX(26, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO27 \
-	ESP32_PINMUX(27, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO27 ESP32_PINMUX(27, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO32 \
-	ESP32_PINMUX(32, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO32 ESP32_PINMUX(32, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO33 \
-	ESP32_PINMUX(33, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO33 ESP32_PINMUX(33, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO34 \
-	ESP32_PINMUX(34, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO34 ESP32_PINMUX(34, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO35 \
-	ESP32_PINMUX(35, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO35 ESP32_PINMUX(35, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO36 \
-	ESP32_PINMUX(36, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO36 ESP32_PINMUX(36, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO37 \
-	ESP32_PINMUX(37, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO37 ESP32_PINMUX(37, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO38 \
-	ESP32_PINMUX(38, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO38 ESP32_PINMUX(38, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO39 \
-	ESP32_PINMUX(39, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO39 ESP32_PINMUX(39, ESP_U1RXD_IN, ESP_NOSIG)
 
 /* UART1_TX */
-#define UART1_TX_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U1TXD_OUT)
 
 /* UART2_CTS */
-#define UART2_CTS_GPIO0 \
-	ESP32_PINMUX(0, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO0 ESP32_PINMUX(0, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO1 \
-	ESP32_PINMUX(1, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO1 ESP32_PINMUX(1, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO2 \
-	ESP32_PINMUX(2, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO2 ESP32_PINMUX(2, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO3 \
-	ESP32_PINMUX(3, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO3 ESP32_PINMUX(3, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO4 \
-	ESP32_PINMUX(4, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO4 ESP32_PINMUX(4, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO5 \
-	ESP32_PINMUX(5, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO5 ESP32_PINMUX(5, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO6 \
-	ESP32_PINMUX(6, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO6 ESP32_PINMUX(6, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO7 \
-	ESP32_PINMUX(7, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO7 ESP32_PINMUX(7, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO8 \
-	ESP32_PINMUX(8, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO8 ESP32_PINMUX(8, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO9 \
-	ESP32_PINMUX(9, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO9 ESP32_PINMUX(9, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO10 \
-	ESP32_PINMUX(10, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO10 ESP32_PINMUX(10, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO11 \
-	ESP32_PINMUX(11, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO11 ESP32_PINMUX(11, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO12 \
-	ESP32_PINMUX(12, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO12 ESP32_PINMUX(12, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO13 \
-	ESP32_PINMUX(13, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO13 ESP32_PINMUX(13, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO14 \
-	ESP32_PINMUX(14, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO14 ESP32_PINMUX(14, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO15 \
-	ESP32_PINMUX(15, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO15 ESP32_PINMUX(15, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO16 \
-	ESP32_PINMUX(16, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO16 ESP32_PINMUX(16, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO17 \
-	ESP32_PINMUX(17, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO17 ESP32_PINMUX(17, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO18 \
-	ESP32_PINMUX(18, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO18 ESP32_PINMUX(18, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO19 \
-	ESP32_PINMUX(19, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO19 ESP32_PINMUX(19, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO20 \
-	ESP32_PINMUX(20, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO20 ESP32_PINMUX(20, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO21 \
-	ESP32_PINMUX(21, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO21 ESP32_PINMUX(21, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO22 \
-	ESP32_PINMUX(22, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO22 ESP32_PINMUX(22, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO23 \
-	ESP32_PINMUX(23, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO23 ESP32_PINMUX(23, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO25 \
-	ESP32_PINMUX(25, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO25 ESP32_PINMUX(25, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO26 \
-	ESP32_PINMUX(26, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO26 ESP32_PINMUX(26, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO27 \
-	ESP32_PINMUX(27, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO27 ESP32_PINMUX(27, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO32 \
-	ESP32_PINMUX(32, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO32 ESP32_PINMUX(32, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO33 \
-	ESP32_PINMUX(33, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO33 ESP32_PINMUX(33, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO34 \
-	ESP32_PINMUX(34, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO34 ESP32_PINMUX(34, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO35 \
-	ESP32_PINMUX(35, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO35 ESP32_PINMUX(35, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO36 \
-	ESP32_PINMUX(36, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO36 ESP32_PINMUX(36, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO37 \
-	ESP32_PINMUX(37, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO37 ESP32_PINMUX(37, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO38 \
-	ESP32_PINMUX(38, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO38 ESP32_PINMUX(38, ESP_U2CTS_IN, ESP_NOSIG)
 
-#define UART2_CTS_GPIO39 \
-	ESP32_PINMUX(39, ESP_U2CTS_IN, ESP_NOSIG)
+#define UART2_CTS_GPIO39 ESP32_PINMUX(39, ESP_U2CTS_IN, ESP_NOSIG)
 
 /* UART2_RTS */
-#define UART2_RTS_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U2RTS_OUT)
 
-#define UART2_RTS_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_U2RTS_OUT)
+#define UART2_RTS_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U2RTS_OUT)
 
 /* UART2_RX */
-#define UART2_RX_GPIO0 \
-	ESP32_PINMUX(0, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO0 ESP32_PINMUX(0, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO1 \
-	ESP32_PINMUX(1, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO1 ESP32_PINMUX(1, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO2 \
-	ESP32_PINMUX(2, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO2 ESP32_PINMUX(2, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO3 \
-	ESP32_PINMUX(3, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO3 ESP32_PINMUX(3, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO4 \
-	ESP32_PINMUX(4, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO4 ESP32_PINMUX(4, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO5 \
-	ESP32_PINMUX(5, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO5 ESP32_PINMUX(5, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO6 \
-	ESP32_PINMUX(6, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO6 ESP32_PINMUX(6, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO7 \
-	ESP32_PINMUX(7, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO7 ESP32_PINMUX(7, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO8 \
-	ESP32_PINMUX(8, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO8 ESP32_PINMUX(8, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO9 \
-	ESP32_PINMUX(9, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO9 ESP32_PINMUX(9, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO10 \
-	ESP32_PINMUX(10, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO10 ESP32_PINMUX(10, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO11 \
-	ESP32_PINMUX(11, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO11 ESP32_PINMUX(11, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO12 \
-	ESP32_PINMUX(12, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO12 ESP32_PINMUX(12, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO13 \
-	ESP32_PINMUX(13, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO13 ESP32_PINMUX(13, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO14 \
-	ESP32_PINMUX(14, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO14 ESP32_PINMUX(14, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO15 \
-	ESP32_PINMUX(15, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO15 ESP32_PINMUX(15, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO16 \
-	ESP32_PINMUX(16, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO16 ESP32_PINMUX(16, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO17 \
-	ESP32_PINMUX(17, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO17 ESP32_PINMUX(17, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO18 \
-	ESP32_PINMUX(18, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO18 ESP32_PINMUX(18, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO19 \
-	ESP32_PINMUX(19, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO19 ESP32_PINMUX(19, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO20 \
-	ESP32_PINMUX(20, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO20 ESP32_PINMUX(20, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO21 \
-	ESP32_PINMUX(21, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO21 ESP32_PINMUX(21, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO22 \
-	ESP32_PINMUX(22, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO22 ESP32_PINMUX(22, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO23 \
-	ESP32_PINMUX(23, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO23 ESP32_PINMUX(23, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO25 \
-	ESP32_PINMUX(25, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO25 ESP32_PINMUX(25, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO26 \
-	ESP32_PINMUX(26, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO26 ESP32_PINMUX(26, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO27 \
-	ESP32_PINMUX(27, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO27 ESP32_PINMUX(27, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO32 \
-	ESP32_PINMUX(32, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO32 ESP32_PINMUX(32, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO33 \
-	ESP32_PINMUX(33, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO33 ESP32_PINMUX(33, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO34 \
-	ESP32_PINMUX(34, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO34 ESP32_PINMUX(34, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO35 \
-	ESP32_PINMUX(35, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO35 ESP32_PINMUX(35, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO36 \
-	ESP32_PINMUX(36, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO36 ESP32_PINMUX(36, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO37 \
-	ESP32_PINMUX(37, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO37 ESP32_PINMUX(37, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO38 \
-	ESP32_PINMUX(38, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO38 ESP32_PINMUX(38, ESP_U2RXD_IN, ESP_NOSIG)
 
-#define UART2_RX_GPIO39 \
-	ESP32_PINMUX(39, ESP_U2RXD_IN, ESP_NOSIG)
+#define UART2_RX_GPIO39 ESP32_PINMUX(39, ESP_U2RXD_IN, ESP_NOSIG)
 
 /* UART2_TX */
-#define UART2_TX_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO22 \
-	ESP32_PINMUX(22, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO22 ESP32_PINMUX(22, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO23 \
-	ESP32_PINMUX(23, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO23 ESP32_PINMUX(23, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO25 \
-	ESP32_PINMUX(25, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO25 ESP32_PINMUX(25, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U2TXD_OUT)
 
-#define UART2_TX_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_U2TXD_OUT)
+#define UART2_TX_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U2TXD_OUT)
 
 
 #endif /* INC_DT_BINDS_PINCTRL_ESP32_PINCTRL_HAL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/esp32s2-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/esp32s2-pinctrl.h
index 5d97a79b176..34ec1ada0b9 100644
--- a/include/zephyr/dt-bindings/pinctrl/esp32s2-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/esp32s2-pinctrl.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -10,7578 +10,5680 @@
 #define INC_DT_BINDS_PINCTRL_ESP32S2_PINCTRL_HAL_H_
 
 /* I2C0_SCL */
-#define I2C0_SCL_GPIO0 \
-	ESP32_PINMUX(0, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO1 \
-	ESP32_PINMUX(1, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO1 ESP32_PINMUX(1, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO2 \
-	ESP32_PINMUX(2, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO2 ESP32_PINMUX(2, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO3 \
-	ESP32_PINMUX(3, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO3 ESP32_PINMUX(3, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO4 \
-	ESP32_PINMUX(4, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO4 ESP32_PINMUX(4, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO5 \
-	ESP32_PINMUX(5, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO5 ESP32_PINMUX(5, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO6 \
-	ESP32_PINMUX(6, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO6 ESP32_PINMUX(6, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO7 \
-	ESP32_PINMUX(7, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO7 ESP32_PINMUX(7, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO8 \
-	ESP32_PINMUX(8, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO8 ESP32_PINMUX(8, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO9 \
-	ESP32_PINMUX(9, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO9 ESP32_PINMUX(9, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO10 \
-	ESP32_PINMUX(10, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO10 ESP32_PINMUX(10, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO11 \
-	ESP32_PINMUX(11, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO11 ESP32_PINMUX(11, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO12 \
-	ESP32_PINMUX(12, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO12 ESP32_PINMUX(12, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO13 \
-	ESP32_PINMUX(13, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO13 ESP32_PINMUX(13, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO14 \
-	ESP32_PINMUX(14, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO14 ESP32_PINMUX(14, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO15 \
-	ESP32_PINMUX(15, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO15 ESP32_PINMUX(15, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO16 \
-	ESP32_PINMUX(16, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO16 ESP32_PINMUX(16, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO17 \
-	ESP32_PINMUX(17, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO17 ESP32_PINMUX(17, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO18 \
-	ESP32_PINMUX(18, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO18 ESP32_PINMUX(18, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO19 \
-	ESP32_PINMUX(19, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO19 ESP32_PINMUX(19, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO20 \
-	ESP32_PINMUX(20, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO20 ESP32_PINMUX(20, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO21 \
-	ESP32_PINMUX(21, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO21 ESP32_PINMUX(21, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO26 \
-	ESP32_PINMUX(26, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO26 ESP32_PINMUX(26, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO27 \
-	ESP32_PINMUX(27, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO27 ESP32_PINMUX(27, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO28 \
-	ESP32_PINMUX(28, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO28 ESP32_PINMUX(28, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO29 \
-	ESP32_PINMUX(29, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO29 ESP32_PINMUX(29, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO30 \
-	ESP32_PINMUX(30, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO30 ESP32_PINMUX(30, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO31 \
-	ESP32_PINMUX(31, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO31 ESP32_PINMUX(31, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO32 \
-	ESP32_PINMUX(32, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO32 ESP32_PINMUX(32, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO33 \
-	ESP32_PINMUX(33, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO33 ESP32_PINMUX(33, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO34 \
-	ESP32_PINMUX(34, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO34 ESP32_PINMUX(34, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO35 \
-	ESP32_PINMUX(35, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO35 ESP32_PINMUX(35, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO36 \
-	ESP32_PINMUX(36, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO36 ESP32_PINMUX(36, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO37 \
-	ESP32_PINMUX(37, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO37 ESP32_PINMUX(37, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO38 \
-	ESP32_PINMUX(38, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO38 ESP32_PINMUX(38, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO39 \
-	ESP32_PINMUX(39, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO39 ESP32_PINMUX(39, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO40 \
-	ESP32_PINMUX(40, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO40 ESP32_PINMUX(40, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO41 \
-	ESP32_PINMUX(41, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO41 ESP32_PINMUX(41, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO42 \
-	ESP32_PINMUX(42, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO42 ESP32_PINMUX(42, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO43 \
-	ESP32_PINMUX(43, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO43 ESP32_PINMUX(43, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO44 \
-	ESP32_PINMUX(44, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO44 ESP32_PINMUX(44, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
-#define I2C0_SCL_GPIO45 \
-	ESP32_PINMUX(45, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
+#define I2C0_SCL_GPIO45 ESP32_PINMUX(45, ESP_I2CEXT0_SCL_IN, ESP_I2CEXT0_SCL_OUT)
 
 /* I2C0_SDA */
-#define I2C0_SDA_GPIO0 \
-	ESP32_PINMUX(0, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO1 \
-	ESP32_PINMUX(1, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO1 ESP32_PINMUX(1, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO2 \
-	ESP32_PINMUX(2, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO2 ESP32_PINMUX(2, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO3 \
-	ESP32_PINMUX(3, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO3 ESP32_PINMUX(3, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO4 \
-	ESP32_PINMUX(4, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO4 ESP32_PINMUX(4, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO5 \
-	ESP32_PINMUX(5, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO5 ESP32_PINMUX(5, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO6 \
-	ESP32_PINMUX(6, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO6 ESP32_PINMUX(6, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO7 \
-	ESP32_PINMUX(7, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO7 ESP32_PINMUX(7, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO8 \
-	ESP32_PINMUX(8, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO8 ESP32_PINMUX(8, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO9 \
-	ESP32_PINMUX(9, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO9 ESP32_PINMUX(9, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO10 \
-	ESP32_PINMUX(10, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO10 ESP32_PINMUX(10, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO11 \
-	ESP32_PINMUX(11, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO11 ESP32_PINMUX(11, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO12 \
-	ESP32_PINMUX(12, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO12 ESP32_PINMUX(12, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO13 \
-	ESP32_PINMUX(13, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO13 ESP32_PINMUX(13, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO14 \
-	ESP32_PINMUX(14, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO14 ESP32_PINMUX(14, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO15 \
-	ESP32_PINMUX(15, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO15 ESP32_PINMUX(15, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO16 \
-	ESP32_PINMUX(16, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO16 ESP32_PINMUX(16, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO17 \
-	ESP32_PINMUX(17, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO17 ESP32_PINMUX(17, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO18 \
-	ESP32_PINMUX(18, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO18 ESP32_PINMUX(18, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO19 \
-	ESP32_PINMUX(19, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO19 ESP32_PINMUX(19, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO20 \
-	ESP32_PINMUX(20, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO20 ESP32_PINMUX(20, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO21 \
-	ESP32_PINMUX(21, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO21 ESP32_PINMUX(21, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO26 \
-	ESP32_PINMUX(26, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO26 ESP32_PINMUX(26, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO27 \
-	ESP32_PINMUX(27, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO27 ESP32_PINMUX(27, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO28 \
-	ESP32_PINMUX(28, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO28 ESP32_PINMUX(28, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO29 \
-	ESP32_PINMUX(29, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO29 ESP32_PINMUX(29, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO30 \
-	ESP32_PINMUX(30, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO30 ESP32_PINMUX(30, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO31 \
-	ESP32_PINMUX(31, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO31 ESP32_PINMUX(31, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO32 \
-	ESP32_PINMUX(32, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO32 ESP32_PINMUX(32, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO33 \
-	ESP32_PINMUX(33, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO33 ESP32_PINMUX(33, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO34 \
-	ESP32_PINMUX(34, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO34 ESP32_PINMUX(34, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO35 \
-	ESP32_PINMUX(35, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO35 ESP32_PINMUX(35, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO36 \
-	ESP32_PINMUX(36, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO36 ESP32_PINMUX(36, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO37 \
-	ESP32_PINMUX(37, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO37 ESP32_PINMUX(37, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO38 \
-	ESP32_PINMUX(38, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO38 ESP32_PINMUX(38, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO39 \
-	ESP32_PINMUX(39, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO39 ESP32_PINMUX(39, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO40 \
-	ESP32_PINMUX(40, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO40 ESP32_PINMUX(40, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO41 \
-	ESP32_PINMUX(41, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO41 ESP32_PINMUX(41, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO42 \
-	ESP32_PINMUX(42, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO42 ESP32_PINMUX(42, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO43 \
-	ESP32_PINMUX(43, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO43 ESP32_PINMUX(43, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO44 \
-	ESP32_PINMUX(44, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO44 ESP32_PINMUX(44, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
-#define I2C0_SDA_GPIO45 \
-	ESP32_PINMUX(45, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
+#define I2C0_SDA_GPIO45 ESP32_PINMUX(45, ESP_I2CEXT0_SDA_IN, ESP_I2CEXT0_SDA_OUT)
 
 /* I2C1_SCL */
-#define I2C1_SCL_GPIO0 \
-	ESP32_PINMUX(0, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO1 \
-	ESP32_PINMUX(1, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO1 ESP32_PINMUX(1, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO2 \
-	ESP32_PINMUX(2, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO2 ESP32_PINMUX(2, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO3 \
-	ESP32_PINMUX(3, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO3 ESP32_PINMUX(3, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO4 \
-	ESP32_PINMUX(4, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO4 ESP32_PINMUX(4, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO5 \
-	ESP32_PINMUX(5, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO5 ESP32_PINMUX(5, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO6 \
-	ESP32_PINMUX(6, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO6 ESP32_PINMUX(6, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO7 \
-	ESP32_PINMUX(7, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO7 ESP32_PINMUX(7, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO8 \
-	ESP32_PINMUX(8, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO8 ESP32_PINMUX(8, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO9 \
-	ESP32_PINMUX(9, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO9 ESP32_PINMUX(9, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO10 \
-	ESP32_PINMUX(10, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO10 ESP32_PINMUX(10, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO11 \
-	ESP32_PINMUX(11, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO11 ESP32_PINMUX(11, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO12 \
-	ESP32_PINMUX(12, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO12 ESP32_PINMUX(12, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO13 \
-	ESP32_PINMUX(13, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO13 ESP32_PINMUX(13, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO14 \
-	ESP32_PINMUX(14, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO14 ESP32_PINMUX(14, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO15 \
-	ESP32_PINMUX(15, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO15 ESP32_PINMUX(15, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO16 \
-	ESP32_PINMUX(16, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO16 ESP32_PINMUX(16, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO17 \
-	ESP32_PINMUX(17, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO17 ESP32_PINMUX(17, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO18 \
-	ESP32_PINMUX(18, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO18 ESP32_PINMUX(18, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO19 \
-	ESP32_PINMUX(19, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO19 ESP32_PINMUX(19, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO20 \
-	ESP32_PINMUX(20, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO20 ESP32_PINMUX(20, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO21 \
-	ESP32_PINMUX(21, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO21 ESP32_PINMUX(21, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO26 \
-	ESP32_PINMUX(26, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO26 ESP32_PINMUX(26, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO27 \
-	ESP32_PINMUX(27, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO27 ESP32_PINMUX(27, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO28 \
-	ESP32_PINMUX(28, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO28 ESP32_PINMUX(28, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO29 \
-	ESP32_PINMUX(29, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO29 ESP32_PINMUX(29, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO30 \
-	ESP32_PINMUX(30, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO30 ESP32_PINMUX(30, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO31 \
-	ESP32_PINMUX(31, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO31 ESP32_PINMUX(31, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO32 \
-	ESP32_PINMUX(32, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO32 ESP32_PINMUX(32, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO33 \
-	ESP32_PINMUX(33, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO33 ESP32_PINMUX(33, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO34 \
-	ESP32_PINMUX(34, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO34 ESP32_PINMUX(34, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO35 \
-	ESP32_PINMUX(35, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO35 ESP32_PINMUX(35, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO36 \
-	ESP32_PINMUX(36, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO36 ESP32_PINMUX(36, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO37 \
-	ESP32_PINMUX(37, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO37 ESP32_PINMUX(37, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO38 \
-	ESP32_PINMUX(38, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO38 ESP32_PINMUX(38, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO39 \
-	ESP32_PINMUX(39, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO39 ESP32_PINMUX(39, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO40 \
-	ESP32_PINMUX(40, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO40 ESP32_PINMUX(40, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO41 \
-	ESP32_PINMUX(41, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO41 ESP32_PINMUX(41, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO42 \
-	ESP32_PINMUX(42, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO42 ESP32_PINMUX(42, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO43 \
-	ESP32_PINMUX(43, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO43 ESP32_PINMUX(43, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO44 \
-	ESP32_PINMUX(44, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO44 ESP32_PINMUX(44, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
-#define I2C1_SCL_GPIO45 \
-	ESP32_PINMUX(45, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
+#define I2C1_SCL_GPIO45 ESP32_PINMUX(45, ESP_I2CEXT1_SCL_IN, ESP_I2CEXT1_SCL_OUT)
 
 /* I2C1_SDA */
-#define I2C1_SDA_GPIO0 \
-	ESP32_PINMUX(0, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO0 ESP32_PINMUX(0, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO1 \
-	ESP32_PINMUX(1, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO1 ESP32_PINMUX(1, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO2 \
-	ESP32_PINMUX(2, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO2 ESP32_PINMUX(2, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO3 \
-	ESP32_PINMUX(3, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO3 ESP32_PINMUX(3, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO4 \
-	ESP32_PINMUX(4, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO4 ESP32_PINMUX(4, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO5 \
-	ESP32_PINMUX(5, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO5 ESP32_PINMUX(5, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO6 \
-	ESP32_PINMUX(6, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO6 ESP32_PINMUX(6, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO7 \
-	ESP32_PINMUX(7, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO7 ESP32_PINMUX(7, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO8 \
-	ESP32_PINMUX(8, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO8 ESP32_PINMUX(8, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO9 \
-	ESP32_PINMUX(9, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO9 ESP32_PINMUX(9, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO10 \
-	ESP32_PINMUX(10, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO10 ESP32_PINMUX(10, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO11 \
-	ESP32_PINMUX(11, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO11 ESP32_PINMUX(11, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO12 \
-	ESP32_PINMUX(12, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO12 ESP32_PINMUX(12, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO13 \
-	ESP32_PINMUX(13, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO13 ESP32_PINMUX(13, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO14 \
-	ESP32_PINMUX(14, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO14 ESP32_PINMUX(14, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO15 \
-	ESP32_PINMUX(15, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO15 ESP32_PINMUX(15, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO16 \
-	ESP32_PINMUX(16, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO16 ESP32_PINMUX(16, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO17 \
-	ESP32_PINMUX(17, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO17 ESP32_PINMUX(17, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO18 \
-	ESP32_PINMUX(18, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO18 ESP32_PINMUX(18, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO19 \
-	ESP32_PINMUX(19, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO19 ESP32_PINMUX(19, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO20 \
-	ESP32_PINMUX(20, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO20 ESP32_PINMUX(20, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO21 \
-	ESP32_PINMUX(21, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO21 ESP32_PINMUX(21, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO26 \
-	ESP32_PINMUX(26, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO26 ESP32_PINMUX(26, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO27 \
-	ESP32_PINMUX(27, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO27 ESP32_PINMUX(27, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO28 \
-	ESP32_PINMUX(28, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO28 ESP32_PINMUX(28, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO29 \
-	ESP32_PINMUX(29, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO29 ESP32_PINMUX(29, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO30 \
-	ESP32_PINMUX(30, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO30 ESP32_PINMUX(30, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO31 \
-	ESP32_PINMUX(31, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO31 ESP32_PINMUX(31, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO32 \
-	ESP32_PINMUX(32, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO32 ESP32_PINMUX(32, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO33 \
-	ESP32_PINMUX(33, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO33 ESP32_PINMUX(33, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO34 \
-	ESP32_PINMUX(34, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO34 ESP32_PINMUX(34, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO35 \
-	ESP32_PINMUX(35, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO35 ESP32_PINMUX(35, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO36 \
-	ESP32_PINMUX(36, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO36 ESP32_PINMUX(36, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO37 \
-	ESP32_PINMUX(37, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO37 ESP32_PINMUX(37, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO38 \
-	ESP32_PINMUX(38, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO38 ESP32_PINMUX(38, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO39 \
-	ESP32_PINMUX(39, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO39 ESP32_PINMUX(39, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO40 \
-	ESP32_PINMUX(40, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO40 ESP32_PINMUX(40, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO41 \
-	ESP32_PINMUX(41, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO41 ESP32_PINMUX(41, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO42 \
-	ESP32_PINMUX(42, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO42 ESP32_PINMUX(42, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO43 \
-	ESP32_PINMUX(43, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO43 ESP32_PINMUX(43, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO44 \
-	ESP32_PINMUX(44, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO44 ESP32_PINMUX(44, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
 
-#define I2C1_SDA_GPIO45 \
-	ESP32_PINMUX(45, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+#define I2C1_SDA_GPIO45 ESP32_PINMUX(45, ESP_I2CEXT1_SDA_IN, ESP_I2CEXT1_SDA_OUT)
+
+/* I2S0_I_BCK */
+#define I2S0_I_BCK_GPIO0 ESP32_PINMUX(0, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO1 ESP32_PINMUX(1, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO2 ESP32_PINMUX(2, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO3 ESP32_PINMUX(3, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO4 ESP32_PINMUX(4, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO5 ESP32_PINMUX(5, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO6 ESP32_PINMUX(6, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO7 ESP32_PINMUX(7, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO8 ESP32_PINMUX(8, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO9 ESP32_PINMUX(9, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO10 ESP32_PINMUX(10, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO11 ESP32_PINMUX(11, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO12 ESP32_PINMUX(12, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO13 ESP32_PINMUX(13, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO14 ESP32_PINMUX(14, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO15 ESP32_PINMUX(15, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO16 ESP32_PINMUX(16, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO17 ESP32_PINMUX(17, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO18 ESP32_PINMUX(18, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO19 ESP32_PINMUX(19, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO20 ESP32_PINMUX(20, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO21 ESP32_PINMUX(21, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO26 ESP32_PINMUX(26, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO27 ESP32_PINMUX(27, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO28 ESP32_PINMUX(28, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO29 ESP32_PINMUX(29, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO30 ESP32_PINMUX(30, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO31 ESP32_PINMUX(31, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO32 ESP32_PINMUX(32, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO33 ESP32_PINMUX(33, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO34 ESP32_PINMUX(34, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO35 ESP32_PINMUX(35, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO36 ESP32_PINMUX(36, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO37 ESP32_PINMUX(37, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO38 ESP32_PINMUX(38, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO39 ESP32_PINMUX(39, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO40 ESP32_PINMUX(40, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO41 ESP32_PINMUX(41, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO42 ESP32_PINMUX(42, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO43 ESP32_PINMUX(43, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO44 ESP32_PINMUX(44, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO45 ESP32_PINMUX(45, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+#define I2S0_I_BCK_GPIO46 ESP32_PINMUX(46, ESP_I2S0I_BCK_IN, ESP_I2S0I_BCK_OUT)
+
+/* I2S0_I_SD */
+#define I2S0_I_SD_GPIO0 ESP32_PINMUX(0, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO1 ESP32_PINMUX(1, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO2 ESP32_PINMUX(2, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO3 ESP32_PINMUX(3, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO4 ESP32_PINMUX(4, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO5 ESP32_PINMUX(5, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO6 ESP32_PINMUX(6, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO7 ESP32_PINMUX(7, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO8 ESP32_PINMUX(8, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO9 ESP32_PINMUX(9, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO10 ESP32_PINMUX(10, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO11 ESP32_PINMUX(11, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO12 ESP32_PINMUX(12, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO13 ESP32_PINMUX(13, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO14 ESP32_PINMUX(14, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO15 ESP32_PINMUX(15, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO16 ESP32_PINMUX(16, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO17 ESP32_PINMUX(17, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO18 ESP32_PINMUX(18, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO19 ESP32_PINMUX(19, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO20 ESP32_PINMUX(20, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO21 ESP32_PINMUX(21, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO26 ESP32_PINMUX(26, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO27 ESP32_PINMUX(27, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO28 ESP32_PINMUX(28, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO29 ESP32_PINMUX(29, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO30 ESP32_PINMUX(30, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO31 ESP32_PINMUX(31, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO32 ESP32_PINMUX(32, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO33 ESP32_PINMUX(33, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO34 ESP32_PINMUX(34, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO35 ESP32_PINMUX(35, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO36 ESP32_PINMUX(36, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO37 ESP32_PINMUX(37, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO38 ESP32_PINMUX(38, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO39 ESP32_PINMUX(39, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO40 ESP32_PINMUX(40, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO41 ESP32_PINMUX(41, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO42 ESP32_PINMUX(42, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO43 ESP32_PINMUX(43, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO44 ESP32_PINMUX(44, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO45 ESP32_PINMUX(45, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+#define I2S0_I_SD_GPIO46 ESP32_PINMUX(46, ESP_I2S0I_DATA_IN15, ESP_NOSIG)
+
+/* I2S0_I_WS */
+#define I2S0_I_WS_GPIO0 ESP32_PINMUX(0, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO1 ESP32_PINMUX(1, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO2 ESP32_PINMUX(2, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO3 ESP32_PINMUX(3, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO4 ESP32_PINMUX(4, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO5 ESP32_PINMUX(5, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO6 ESP32_PINMUX(6, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO7 ESP32_PINMUX(7, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO8 ESP32_PINMUX(8, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO9 ESP32_PINMUX(9, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO10 ESP32_PINMUX(10, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO11 ESP32_PINMUX(11, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO12 ESP32_PINMUX(12, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO13 ESP32_PINMUX(13, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO14 ESP32_PINMUX(14, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO15 ESP32_PINMUX(15, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO16 ESP32_PINMUX(16, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO17 ESP32_PINMUX(17, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO18 ESP32_PINMUX(18, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO19 ESP32_PINMUX(19, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO20 ESP32_PINMUX(20, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO21 ESP32_PINMUX(21, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO26 ESP32_PINMUX(26, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO27 ESP32_PINMUX(27, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO28 ESP32_PINMUX(28, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO29 ESP32_PINMUX(29, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO30 ESP32_PINMUX(30, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO31 ESP32_PINMUX(31, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO32 ESP32_PINMUX(32, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO33 ESP32_PINMUX(33, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO34 ESP32_PINMUX(34, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO35 ESP32_PINMUX(35, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO36 ESP32_PINMUX(36, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO37 ESP32_PINMUX(37, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO38 ESP32_PINMUX(38, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO39 ESP32_PINMUX(39, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO40 ESP32_PINMUX(40, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO41 ESP32_PINMUX(41, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO42 ESP32_PINMUX(42, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO43 ESP32_PINMUX(43, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO44 ESP32_PINMUX(44, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO45 ESP32_PINMUX(45, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+#define I2S0_I_WS_GPIO46 ESP32_PINMUX(46, ESP_I2S0I_WS_IN, ESP_I2S0I_WS_OUT)
+
+/* I2S0_MCLK */
+#define I2S0_MCLK_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_CLK_I2S)
+
+#define I2S0_MCLK_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_CLK_I2S)
+
+/* I2S0_O_BCK */
+#define I2S0_O_BCK_GPIO0 ESP32_PINMUX(0, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO1 ESP32_PINMUX(1, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO2 ESP32_PINMUX(2, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO3 ESP32_PINMUX(3, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO4 ESP32_PINMUX(4, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO5 ESP32_PINMUX(5, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO6 ESP32_PINMUX(6, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO7 ESP32_PINMUX(7, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO8 ESP32_PINMUX(8, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO9 ESP32_PINMUX(9, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO10 ESP32_PINMUX(10, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO11 ESP32_PINMUX(11, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO12 ESP32_PINMUX(12, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO13 ESP32_PINMUX(13, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO14 ESP32_PINMUX(14, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO15 ESP32_PINMUX(15, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO16 ESP32_PINMUX(16, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO17 ESP32_PINMUX(17, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO18 ESP32_PINMUX(18, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO19 ESP32_PINMUX(19, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO20 ESP32_PINMUX(20, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO21 ESP32_PINMUX(21, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO26 ESP32_PINMUX(26, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO27 ESP32_PINMUX(27, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO28 ESP32_PINMUX(28, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO29 ESP32_PINMUX(29, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO30 ESP32_PINMUX(30, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO31 ESP32_PINMUX(31, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO32 ESP32_PINMUX(32, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO33 ESP32_PINMUX(33, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO34 ESP32_PINMUX(34, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO35 ESP32_PINMUX(35, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO36 ESP32_PINMUX(36, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO37 ESP32_PINMUX(37, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO38 ESP32_PINMUX(38, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO39 ESP32_PINMUX(39, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO40 ESP32_PINMUX(40, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO41 ESP32_PINMUX(41, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO42 ESP32_PINMUX(42, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO43 ESP32_PINMUX(43, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO44 ESP32_PINMUX(44, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO45 ESP32_PINMUX(45, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+#define I2S0_O_BCK_GPIO46 ESP32_PINMUX(46, ESP_I2S0O_BCK_IN, ESP_I2S0O_BCK_OUT)
+
+/* I2S0_O_SD */
+#define I2S0_O_SD_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+#define I2S0_O_SD_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_I2S0O_DATA_OUT23)
+
+/* I2S0_O_WS */
+#define I2S0_O_WS_GPIO0 ESP32_PINMUX(0, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO1 ESP32_PINMUX(1, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO2 ESP32_PINMUX(2, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO3 ESP32_PINMUX(3, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO4 ESP32_PINMUX(4, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO5 ESP32_PINMUX(5, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO6 ESP32_PINMUX(6, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO7 ESP32_PINMUX(7, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO8 ESP32_PINMUX(8, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO9 ESP32_PINMUX(9, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO10 ESP32_PINMUX(10, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO11 ESP32_PINMUX(11, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO12 ESP32_PINMUX(12, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO13 ESP32_PINMUX(13, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO14 ESP32_PINMUX(14, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO15 ESP32_PINMUX(15, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO16 ESP32_PINMUX(16, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO17 ESP32_PINMUX(17, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO18 ESP32_PINMUX(18, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO19 ESP32_PINMUX(19, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO20 ESP32_PINMUX(20, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO21 ESP32_PINMUX(21, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO26 ESP32_PINMUX(26, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO27 ESP32_PINMUX(27, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO28 ESP32_PINMUX(28, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO29 ESP32_PINMUX(29, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO30 ESP32_PINMUX(30, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO31 ESP32_PINMUX(31, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO32 ESP32_PINMUX(32, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO33 ESP32_PINMUX(33, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO34 ESP32_PINMUX(34, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO35 ESP32_PINMUX(35, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO36 ESP32_PINMUX(36, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO37 ESP32_PINMUX(37, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO38 ESP32_PINMUX(38, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO39 ESP32_PINMUX(39, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO40 ESP32_PINMUX(40, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO41 ESP32_PINMUX(41, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO42 ESP32_PINMUX(42, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO43 ESP32_PINMUX(43, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO44 ESP32_PINMUX(44, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO45 ESP32_PINMUX(45, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
+
+#define I2S0_O_WS_GPIO46 ESP32_PINMUX(46, ESP_I2S0O_WS_IN, ESP_I2S0O_WS_OUT)
 
 /* LEDC_CH0 */
-#define LEDC_CH0_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
-#define LEDC_CH0_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
+#define LEDC_CH0_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT0)
 
 /* LEDC_CH1 */
-#define LEDC_CH1_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
-#define LEDC_CH1_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
+#define LEDC_CH1_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT1)
 
 /* LEDC_CH2 */
-#define LEDC_CH2_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
-#define LEDC_CH2_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
+#define LEDC_CH2_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT2)
 
 /* LEDC_CH3 */
-#define LEDC_CH3_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
-#define LEDC_CH3_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
+#define LEDC_CH3_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT3)
 
 /* LEDC_CH4 */
-#define LEDC_CH4_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
-#define LEDC_CH4_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
+#define LEDC_CH4_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT4)
 
 /* LEDC_CH5 */
-#define LEDC_CH5_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
-#define LEDC_CH5_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
+#define LEDC_CH5_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT5)
 
 /* LEDC_CH6 */
-#define LEDC_CH6_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
-#define LEDC_CH6_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
+#define LEDC_CH6_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT6)
 
 /* LEDC_CH7 */
-#define LEDC_CH7_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
-#define LEDC_CH7_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
+#define LEDC_CH7_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_LEDC_LS_SIG_OUT7)
 
 /* PCNT0_CH0CTRL */
-#define PCNT0_CH0CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO28 \
-	ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO29 \
-	ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO30 \
-	ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO31 \
-	ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO40 \
-	ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO41 \
-	ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO42 \
-	ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO43 \
-	ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO44 \
-	ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO45 \
-	ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0CTRL_GPIO46 \
-	ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN0, ESP_NOSIG)
 
 /* PCNT0_CH0SIG */
-#define PCNT0_CH0SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO28 \
-	ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO29 \
-	ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO30 \
-	ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO31 \
-	ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO40 \
-	ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO41 \
-	ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO42 \
-	ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO43 \
-	ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO44 \
-	ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO45 \
-	ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
-#define PCNT0_CH0SIG_GPIO46 \
-	ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
+#define PCNT0_CH0SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN0, ESP_NOSIG)
 
 /* PCNT0_CH1CTRL */
-#define PCNT0_CH1CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO28 \
-	ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO29 \
-	ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO30 \
-	ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO31 \
-	ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO40 \
-	ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO41 \
-	ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO42 \
-	ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO43 \
-	ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO44 \
-	ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO45 \
-	ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1CTRL_GPIO46 \
-	ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN0, ESP_NOSIG)
 
 /* PCNT0_CH1SIG */
-#define PCNT0_CH1SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO28 \
-	ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO29 \
-	ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO30 \
-	ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO31 \
-	ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO40 \
-	ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO41 \
-	ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO42 \
-	ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO43 \
-	ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO44 \
-	ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO45 \
-	ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
-#define PCNT0_CH1SIG_GPIO46 \
-	ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
+#define PCNT0_CH1SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN0, ESP_NOSIG)
 
 /* PCNT1_CH0CTRL */
-#define PCNT1_CH0CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO28 \
-	ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO29 \
-	ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO30 \
-	ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO31 \
-	ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO40 \
-	ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO41 \
-	ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO42 \
-	ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO43 \
-	ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO44 \
-	ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO45 \
-	ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0CTRL_GPIO46 \
-	ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN1, ESP_NOSIG)
 
 /* PCNT1_CH0SIG */
-#define PCNT1_CH0SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO28 \
-	ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO29 \
-	ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO30 \
-	ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO31 \
-	ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO40 \
-	ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO41 \
-	ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO42 \
-	ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO43 \
-	ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO44 \
-	ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO45 \
-	ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
-#define PCNT1_CH0SIG_GPIO46 \
-	ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
+#define PCNT1_CH0SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN1, ESP_NOSIG)
 
 /* PCNT1_CH1CTRL */
-#define PCNT1_CH1CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO28 \
-	ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO29 \
-	ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO30 \
-	ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO31 \
-	ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO40 \
-	ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO41 \
-	ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO42 \
-	ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO43 \
-	ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO44 \
-	ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO45 \
-	ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1CTRL_GPIO46 \
-	ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN1, ESP_NOSIG)
 
 /* PCNT1_CH1SIG */
-#define PCNT1_CH1SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO28 \
-	ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO29 \
-	ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO30 \
-	ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO31 \
-	ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO40 \
-	ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO41 \
-	ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO42 \
-	ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO43 \
-	ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO44 \
-	ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO45 \
-	ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
-#define PCNT1_CH1SIG_GPIO46 \
-	ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
+#define PCNT1_CH1SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN1, ESP_NOSIG)
 
 /* PCNT2_CH0CTRL */
-#define PCNT2_CH0CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO28 \
-	ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO29 \
-	ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO30 \
-	ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO31 \
-	ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO40 \
-	ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO41 \
-	ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO42 \
-	ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO43 \
-	ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO44 \
-	ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO45 \
-	ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
-#define PCNT2_CH0CTRL_GPIO46 \
-	ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
+#define PCNT2_CH0CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN2, ESP_NOSIG)
 
 /* PCNT2_CH0SIG */
-#define PCNT2_CH0SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO28 \
-	ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO29 \
-	ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO30 \
-	ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO31 \
-	ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO40 \
-	ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO41 \
-	ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO42 \
-	ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO43 \
-	ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO44 \
-	ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO45 \
-	ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT2_CH0SIG_GPIO46 \
-	ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT2_CH0SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
 /* PCNT2_CH1CTRL */
-#define PCNT2_CH1CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO28 \
-	ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO29 \
-	ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO30 \
-	ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO31 \
-	ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO40 \
-	ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO41 \
-	ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO42 \
-	ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO43 \
-	ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO44 \
-	ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO45 \
-	ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1CTRL_GPIO46 \
-	ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN2, ESP_NOSIG)
 
 /* PCNT2_CH1SIG */
-#define PCNT2_CH1SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO28 \
-	ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO29 \
-	ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO30 \
-	ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO31 \
-	ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO40 \
-	ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO41 \
-	ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO42 \
-	ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO43 \
-	ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO44 \
-	ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO45 \
-	ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
-#define PCNT2_CH1SIG_GPIO46 \
-	ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
+#define PCNT2_CH1SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN2, ESP_NOSIG)
 
 /* PCNT3_CH0CTRL */
-#define PCNT3_CH0CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO28 \
-	ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO29 \
-	ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO30 \
-	ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO31 \
-	ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO40 \
-	ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO41 \
-	ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO42 \
-	ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO43 \
-	ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO44 \
-	ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO45 \
-	ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0CTRL_GPIO46 \
-	ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH0_IN3, ESP_NOSIG)
 
 /* PCNT3_CH0SIG */
-#define PCNT3_CH0SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO28 \
-	ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO29 \
-	ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO30 \
-	ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO31 \
-	ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO40 \
-	ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO41 \
-	ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO42 \
-	ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO43 \
-	ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO44 \
-	ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO45 \
-	ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
-#define PCNT3_CH0SIG_GPIO46 \
-	ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
+#define PCNT3_CH0SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH0_IN3, ESP_NOSIG)
 
 /* PCNT3_CH1CTRL */
-#define PCNT3_CH1CTRL_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO0 ESP32_PINMUX(0, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO1 ESP32_PINMUX(1, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO2 ESP32_PINMUX(2, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO3 ESP32_PINMUX(3, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO4 ESP32_PINMUX(4, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO5 ESP32_PINMUX(5, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO6 ESP32_PINMUX(6, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO7 ESP32_PINMUX(7, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO8 ESP32_PINMUX(8, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO9 ESP32_PINMUX(9, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO10 ESP32_PINMUX(10, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO11 ESP32_PINMUX(11, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO12 ESP32_PINMUX(12, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO13 ESP32_PINMUX(13, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO14 ESP32_PINMUX(14, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO15 ESP32_PINMUX(15, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO16 ESP32_PINMUX(16, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO17 ESP32_PINMUX(17, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO18 ESP32_PINMUX(18, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO19 ESP32_PINMUX(19, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO20 ESP32_PINMUX(20, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO21 ESP32_PINMUX(21, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO26 ESP32_PINMUX(26, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO27 ESP32_PINMUX(27, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO28 \
-	ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO28 ESP32_PINMUX(28, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO29 \
-	ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO29 ESP32_PINMUX(29, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO30 \
-	ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO30 ESP32_PINMUX(30, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO31 \
-	ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO31 ESP32_PINMUX(31, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO32 ESP32_PINMUX(32, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO33 ESP32_PINMUX(33, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO34 ESP32_PINMUX(34, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO35 ESP32_PINMUX(35, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO36 ESP32_PINMUX(36, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO37 ESP32_PINMUX(37, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO38 ESP32_PINMUX(38, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO39 ESP32_PINMUX(39, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO40 \
-	ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO40 ESP32_PINMUX(40, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO41 \
-	ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO41 ESP32_PINMUX(41, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO42 \
-	ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO42 ESP32_PINMUX(42, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO43 \
-	ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO43 ESP32_PINMUX(43, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO44 \
-	ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO44 ESP32_PINMUX(44, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO45 \
-	ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO45 ESP32_PINMUX(45, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1CTRL_GPIO46 \
-	ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1CTRL_GPIO46 ESP32_PINMUX(46, ESP_PCNT_CTRL_CH1_IN3, ESP_NOSIG)
 
 /* PCNT3_CH1SIG */
-#define PCNT3_CH1SIG_GPIO0 \
-	ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO0 ESP32_PINMUX(0, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO1 \
-	ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO1 ESP32_PINMUX(1, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO2 \
-	ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO2 ESP32_PINMUX(2, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO3 \
-	ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO3 ESP32_PINMUX(3, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO4 \
-	ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO4 ESP32_PINMUX(4, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO5 \
-	ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO5 ESP32_PINMUX(5, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO6 \
-	ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO6 ESP32_PINMUX(6, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO7 \
-	ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO7 ESP32_PINMUX(7, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO8 \
-	ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO8 ESP32_PINMUX(8, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO9 \
-	ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO9 ESP32_PINMUX(9, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO10 \
-	ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO10 ESP32_PINMUX(10, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO11 \
-	ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO11 ESP32_PINMUX(11, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO12 \
-	ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO12 ESP32_PINMUX(12, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO13 \
-	ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO13 ESP32_PINMUX(13, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO14 \
-	ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO14 ESP32_PINMUX(14, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO15 \
-	ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO15 ESP32_PINMUX(15, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO16 \
-	ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO16 ESP32_PINMUX(16, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO17 \
-	ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO17 ESP32_PINMUX(17, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO18 \
-	ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO18 ESP32_PINMUX(18, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO19 \
-	ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO19 ESP32_PINMUX(19, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO20 \
-	ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO20 ESP32_PINMUX(20, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO21 \
-	ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO21 ESP32_PINMUX(21, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO26 \
-	ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO26 ESP32_PINMUX(26, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO27 \
-	ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO27 ESP32_PINMUX(27, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO28 \
-	ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO28 ESP32_PINMUX(28, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO29 \
-	ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO29 ESP32_PINMUX(29, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO30 \
-	ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO30 ESP32_PINMUX(30, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO31 \
-	ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO31 ESP32_PINMUX(31, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO32 \
-	ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO32 ESP32_PINMUX(32, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO33 \
-	ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO33 ESP32_PINMUX(33, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO34 \
-	ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO34 ESP32_PINMUX(34, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO35 \
-	ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO35 ESP32_PINMUX(35, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO36 \
-	ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO36 ESP32_PINMUX(36, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO37 \
-	ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO37 ESP32_PINMUX(37, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO38 \
-	ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO38 ESP32_PINMUX(38, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO39 \
-	ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO39 ESP32_PINMUX(39, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO40 \
-	ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO40 ESP32_PINMUX(40, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO41 \
-	ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO41 ESP32_PINMUX(41, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO42 \
-	ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO42 ESP32_PINMUX(42, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO43 \
-	ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO43 ESP32_PINMUX(43, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO44 \
-	ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO44 ESP32_PINMUX(44, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO45 \
-	ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO45 ESP32_PINMUX(45, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
-#define PCNT3_CH1SIG_GPIO46 \
-	ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
+#define PCNT3_CH1SIG_GPIO46 ESP32_PINMUX(46, ESP_PCNT_SIG_CH1_IN3, ESP_NOSIG)
 
 /* SPIM2_CSEL */
-#define SPIM2_CSEL_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS0_OUT)
 
-#define SPIM2_CSEL_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS0_OUT)
+#define SPIM2_CSEL_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS0_OUT)
 
 /* SPIM2_CSEL1 */
-#define SPIM2_CSEL1_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS1_OUT)
 
-#define SPIM2_CSEL1_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS1_OUT)
+#define SPIM2_CSEL1_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS1_OUT)
 
 /* SPIM2_CSEL2 */
-#define SPIM2_CSEL2_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS2_OUT)
 
-#define SPIM2_CSEL2_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS2_OUT)
+#define SPIM2_CSEL2_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS2_OUT)
 
 /* SPIM2_CSEL3 */
-#define SPIM2_CSEL3_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS3_OUT)
 
-#define SPIM2_CSEL3_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS3_OUT)
+#define SPIM2_CSEL3_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS3_OUT)
 
 /* SPIM2_CSEL4 */
-#define SPIM2_CSEL4_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS4_OUT)
 
-#define SPIM2_CSEL4_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS4_OUT)
+#define SPIM2_CSEL4_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS4_OUT)
 
 /* SPIM2_CSEL5 */
-#define SPIM2_CSEL5_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICS5_OUT)
 
-#define SPIM2_CSEL5_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS5_OUT)
+#define SPIM2_CSEL5_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICS5_OUT)
 
 /* SPIM2_MISO */
-#define SPIM2_MISO_GPIO0 \
-	ESP32_PINMUX(0, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO0 ESP32_PINMUX(0, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO1 \
-	ESP32_PINMUX(1, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO1 ESP32_PINMUX(1, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO2 \
-	ESP32_PINMUX(2, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO2 ESP32_PINMUX(2, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO3 \
-	ESP32_PINMUX(3, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO3 ESP32_PINMUX(3, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO4 \
-	ESP32_PINMUX(4, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO4 ESP32_PINMUX(4, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO5 \
-	ESP32_PINMUX(5, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO5 ESP32_PINMUX(5, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO6 \
-	ESP32_PINMUX(6, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO6 ESP32_PINMUX(6, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO7 \
-	ESP32_PINMUX(7, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO7 ESP32_PINMUX(7, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO8 \
-	ESP32_PINMUX(8, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO8 ESP32_PINMUX(8, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO9 \
-	ESP32_PINMUX(9, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO9 ESP32_PINMUX(9, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO10 \
-	ESP32_PINMUX(10, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO10 ESP32_PINMUX(10, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO11 \
-	ESP32_PINMUX(11, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO11 ESP32_PINMUX(11, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO12 \
-	ESP32_PINMUX(12, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO12 ESP32_PINMUX(12, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO13 \
-	ESP32_PINMUX(13, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO13 ESP32_PINMUX(13, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO14 \
-	ESP32_PINMUX(14, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO14 ESP32_PINMUX(14, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO15 \
-	ESP32_PINMUX(15, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO15 ESP32_PINMUX(15, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO16 \
-	ESP32_PINMUX(16, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO16 ESP32_PINMUX(16, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO17 \
-	ESP32_PINMUX(17, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO17 ESP32_PINMUX(17, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO18 \
-	ESP32_PINMUX(18, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO18 ESP32_PINMUX(18, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO19 \
-	ESP32_PINMUX(19, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO19 ESP32_PINMUX(19, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO20 \
-	ESP32_PINMUX(20, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO20 ESP32_PINMUX(20, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO21 \
-	ESP32_PINMUX(21, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO21 ESP32_PINMUX(21, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO26 \
-	ESP32_PINMUX(26, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO26 ESP32_PINMUX(26, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO27 \
-	ESP32_PINMUX(27, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO27 ESP32_PINMUX(27, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO28 \
-	ESP32_PINMUX(28, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO28 ESP32_PINMUX(28, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO29 \
-	ESP32_PINMUX(29, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO29 ESP32_PINMUX(29, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO30 \
-	ESP32_PINMUX(30, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO30 ESP32_PINMUX(30, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO31 \
-	ESP32_PINMUX(31, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO31 ESP32_PINMUX(31, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO32 \
-	ESP32_PINMUX(32, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO32 ESP32_PINMUX(32, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO33 \
-	ESP32_PINMUX(33, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO33 ESP32_PINMUX(33, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO34 \
-	ESP32_PINMUX(34, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO34 ESP32_PINMUX(34, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO35 \
-	ESP32_PINMUX(35, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO35 ESP32_PINMUX(35, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO36 \
-	ESP32_PINMUX(36, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO36 ESP32_PINMUX(36, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO37 \
-	ESP32_PINMUX(37, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO37 ESP32_PINMUX(37, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO38 \
-	ESP32_PINMUX(38, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO38 ESP32_PINMUX(38, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO39 \
-	ESP32_PINMUX(39, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO39 ESP32_PINMUX(39, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO40 \
-	ESP32_PINMUX(40, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO40 ESP32_PINMUX(40, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO41 \
-	ESP32_PINMUX(41, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO41 ESP32_PINMUX(41, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO42 \
-	ESP32_PINMUX(42, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO42 ESP32_PINMUX(42, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO43 \
-	ESP32_PINMUX(43, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO43 ESP32_PINMUX(43, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO44 \
-	ESP32_PINMUX(44, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO44 ESP32_PINMUX(44, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO45 \
-	ESP32_PINMUX(45, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO45 ESP32_PINMUX(45, ESP_FSPIQ_IN, ESP_NOSIG)
 
-#define SPIM2_MISO_GPIO46 \
-	ESP32_PINMUX(46, ESP_FSPIQ_IN, ESP_NOSIG)
+#define SPIM2_MISO_GPIO46 ESP32_PINMUX(46, ESP_FSPIQ_IN, ESP_NOSIG)
 
 /* SPIM2_MOSI */
-#define SPIM2_MOSI_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPID_OUT)
 
-#define SPIM2_MOSI_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPID_OUT)
+#define SPIM2_MOSI_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPID_OUT)
 
 /* SPIM2_SCLK */
-#define SPIM2_SCLK_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_FSPICLK_OUT)
 
-#define SPIM2_SCLK_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICLK_OUT)
+#define SPIM2_SCLK_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_FSPICLK_OUT)
 
 /* SPIM3_CSEL */
-#define SPIM3_CSEL_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
-#define SPIM3_CSEL_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_CS0_OUT)
+#define SPIM3_CSEL_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_CS0_OUT)
 
 /* SPIM3_CSEL1 */
-#define SPIM3_CSEL1_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
-#define SPIM3_CSEL1_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_CS1_OUT)
+#define SPIM3_CSEL1_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_CS1_OUT)
 
 /* SPIM3_CSEL2 */
-#define SPIM3_CSEL2_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
-#define SPIM3_CSEL2_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_CS2_OUT)
+#define SPIM3_CSEL2_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_CS2_OUT)
 
 /* SPIM3_MISO */
-#define SPIM3_MISO_GPIO0 \
-	ESP32_PINMUX(0, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO0 ESP32_PINMUX(0, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO1 \
-	ESP32_PINMUX(1, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO1 ESP32_PINMUX(1, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO2 \
-	ESP32_PINMUX(2, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO2 ESP32_PINMUX(2, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO3 \
-	ESP32_PINMUX(3, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO3 ESP32_PINMUX(3, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO4 \
-	ESP32_PINMUX(4, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO4 ESP32_PINMUX(4, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO5 \
-	ESP32_PINMUX(5, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO5 ESP32_PINMUX(5, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO6 \
-	ESP32_PINMUX(6, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO6 ESP32_PINMUX(6, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO7 \
-	ESP32_PINMUX(7, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO7 ESP32_PINMUX(7, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO8 \
-	ESP32_PINMUX(8, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO8 ESP32_PINMUX(8, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO9 \
-	ESP32_PINMUX(9, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO9 ESP32_PINMUX(9, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO10 \
-	ESP32_PINMUX(10, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO10 ESP32_PINMUX(10, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO11 \
-	ESP32_PINMUX(11, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO11 ESP32_PINMUX(11, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO12 \
-	ESP32_PINMUX(12, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO12 ESP32_PINMUX(12, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO13 \
-	ESP32_PINMUX(13, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO13 ESP32_PINMUX(13, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO14 \
-	ESP32_PINMUX(14, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO14 ESP32_PINMUX(14, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO15 \
-	ESP32_PINMUX(15, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO15 ESP32_PINMUX(15, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO16 \
-	ESP32_PINMUX(16, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO16 ESP32_PINMUX(16, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO17 \
-	ESP32_PINMUX(17, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO17 ESP32_PINMUX(17, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO18 \
-	ESP32_PINMUX(18, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO18 ESP32_PINMUX(18, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO19 \
-	ESP32_PINMUX(19, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO19 ESP32_PINMUX(19, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO20 \
-	ESP32_PINMUX(20, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO20 ESP32_PINMUX(20, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO21 \
-	ESP32_PINMUX(21, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO21 ESP32_PINMUX(21, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO26 \
-	ESP32_PINMUX(26, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO26 ESP32_PINMUX(26, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO27 \
-	ESP32_PINMUX(27, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO27 ESP32_PINMUX(27, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO28 \
-	ESP32_PINMUX(28, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO28 ESP32_PINMUX(28, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO29 \
-	ESP32_PINMUX(29, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO29 ESP32_PINMUX(29, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO30 \
-	ESP32_PINMUX(30, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO30 ESP32_PINMUX(30, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO31 \
-	ESP32_PINMUX(31, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO31 ESP32_PINMUX(31, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO32 \
-	ESP32_PINMUX(32, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO32 ESP32_PINMUX(32, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO33 \
-	ESP32_PINMUX(33, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO33 ESP32_PINMUX(33, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO34 \
-	ESP32_PINMUX(34, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO34 ESP32_PINMUX(34, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO35 \
-	ESP32_PINMUX(35, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO35 ESP32_PINMUX(35, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO36 \
-	ESP32_PINMUX(36, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO36 ESP32_PINMUX(36, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO37 \
-	ESP32_PINMUX(37, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO37 ESP32_PINMUX(37, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO38 \
-	ESP32_PINMUX(38, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO38 ESP32_PINMUX(38, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO39 \
-	ESP32_PINMUX(39, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO39 ESP32_PINMUX(39, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO40 \
-	ESP32_PINMUX(40, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO40 ESP32_PINMUX(40, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO41 \
-	ESP32_PINMUX(41, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO41 ESP32_PINMUX(41, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO42 \
-	ESP32_PINMUX(42, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO42 ESP32_PINMUX(42, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO43 \
-	ESP32_PINMUX(43, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO43 ESP32_PINMUX(43, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO44 \
-	ESP32_PINMUX(44, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO44 ESP32_PINMUX(44, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO45 \
-	ESP32_PINMUX(45, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO45 ESP32_PINMUX(45, ESP_SPI3_Q_IN, ESP_NOSIG)
 
-#define SPIM3_MISO_GPIO46 \
-	ESP32_PINMUX(46, ESP_SPI3_Q_IN, ESP_NOSIG)
+#define SPIM3_MISO_GPIO46 ESP32_PINMUX(46, ESP_SPI3_Q_IN, ESP_NOSIG)
 
 /* SPIM3_MOSI */
-#define SPIM3_MOSI_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_D_OUT)
 
-#define SPIM3_MOSI_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_D_OUT)
+#define SPIM3_MOSI_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_D_OUT)
 
 /* SPIM3_SCLK */
-#define SPIM3_SCLK_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
-#define SPIM3_SCLK_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
+#define SPIM3_SCLK_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_SPI3_CLK_OUT_MUX)
 
 /* TWAI_BUS_OFF */
-#define TWAI_BUS_OFF_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
-#define TWAI_BUS_OFF_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
+#define TWAI_BUS_OFF_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_TWAI_BUS_OFF_ON)
 
 /* TWAI_CLKOUT */
-#define TWAI_CLKOUT_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
-#define TWAI_CLKOUT_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_TWAI_CLKOUT)
+#define TWAI_CLKOUT_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_TWAI_CLKOUT)
 
 /* TWAI_RX */
-#define TWAI_RX_GPIO0 \
-	ESP32_PINMUX(0, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO0 ESP32_PINMUX(0, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO1 \
-	ESP32_PINMUX(1, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO1 ESP32_PINMUX(1, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO2 \
-	ESP32_PINMUX(2, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO2 ESP32_PINMUX(2, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO3 \
-	ESP32_PINMUX(3, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO3 ESP32_PINMUX(3, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO4 \
-	ESP32_PINMUX(4, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO4 ESP32_PINMUX(4, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO5 \
-	ESP32_PINMUX(5, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO5 ESP32_PINMUX(5, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO6 \
-	ESP32_PINMUX(6, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO6 ESP32_PINMUX(6, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO7 \
-	ESP32_PINMUX(7, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO7 ESP32_PINMUX(7, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO8 \
-	ESP32_PINMUX(8, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO8 ESP32_PINMUX(8, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO9 \
-	ESP32_PINMUX(9, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO9 ESP32_PINMUX(9, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO10 \
-	ESP32_PINMUX(10, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO10 ESP32_PINMUX(10, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO11 \
-	ESP32_PINMUX(11, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO11 ESP32_PINMUX(11, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO12 \
-	ESP32_PINMUX(12, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO12 ESP32_PINMUX(12, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO13 \
-	ESP32_PINMUX(13, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO13 ESP32_PINMUX(13, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO14 \
-	ESP32_PINMUX(14, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO14 ESP32_PINMUX(14, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO15 \
-	ESP32_PINMUX(15, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO15 ESP32_PINMUX(15, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO16 \
-	ESP32_PINMUX(16, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO16 ESP32_PINMUX(16, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO17 \
-	ESP32_PINMUX(17, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO17 ESP32_PINMUX(17, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO18 \
-	ESP32_PINMUX(18, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO18 ESP32_PINMUX(18, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO19 \
-	ESP32_PINMUX(19, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO19 ESP32_PINMUX(19, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO20 \
-	ESP32_PINMUX(20, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO20 ESP32_PINMUX(20, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO21 \
-	ESP32_PINMUX(21, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO21 ESP32_PINMUX(21, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO26 \
-	ESP32_PINMUX(26, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO26 ESP32_PINMUX(26, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO27 \
-	ESP32_PINMUX(27, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO27 ESP32_PINMUX(27, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO28 \
-	ESP32_PINMUX(28, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO28 ESP32_PINMUX(28, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO29 \
-	ESP32_PINMUX(29, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO29 ESP32_PINMUX(29, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO30 \
-	ESP32_PINMUX(30, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO30 ESP32_PINMUX(30, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO31 \
-	ESP32_PINMUX(31, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO31 ESP32_PINMUX(31, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO32 \
-	ESP32_PINMUX(32, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO32 ESP32_PINMUX(32, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO33 \
-	ESP32_PINMUX(33, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO33 ESP32_PINMUX(33, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO34 \
-	ESP32_PINMUX(34, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO34 ESP32_PINMUX(34, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO35 \
-	ESP32_PINMUX(35, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO35 ESP32_PINMUX(35, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO36 \
-	ESP32_PINMUX(36, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO36 ESP32_PINMUX(36, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO37 \
-	ESP32_PINMUX(37, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO37 ESP32_PINMUX(37, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO38 \
-	ESP32_PINMUX(38, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO38 ESP32_PINMUX(38, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO39 \
-	ESP32_PINMUX(39, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO39 ESP32_PINMUX(39, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO40 \
-	ESP32_PINMUX(40, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO40 ESP32_PINMUX(40, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO41 \
-	ESP32_PINMUX(41, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO41 ESP32_PINMUX(41, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO42 \
-	ESP32_PINMUX(42, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO42 ESP32_PINMUX(42, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO43 \
-	ESP32_PINMUX(43, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO43 ESP32_PINMUX(43, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO44 \
-	ESP32_PINMUX(44, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO44 ESP32_PINMUX(44, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO45 \
-	ESP32_PINMUX(45, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO45 ESP32_PINMUX(45, ESP_TWAI_RX, ESP_NOSIG)
 
-#define TWAI_RX_GPIO46 \
-	ESP32_PINMUX(46, ESP_TWAI_RX, ESP_NOSIG)
+#define TWAI_RX_GPIO46 ESP32_PINMUX(46, ESP_TWAI_RX, ESP_NOSIG)
 
 /* TWAI_TX */
-#define TWAI_TX_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_TWAI_TX)
 
-#define TWAI_TX_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_TWAI_TX)
+#define TWAI_TX_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_TWAI_TX)
 
 /* UART0_CTS */
-#define UART0_CTS_GPIO0 \
-	ESP32_PINMUX(0, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO0 ESP32_PINMUX(0, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO1 \
-	ESP32_PINMUX(1, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO1 ESP32_PINMUX(1, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO2 \
-	ESP32_PINMUX(2, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO2 ESP32_PINMUX(2, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO3 \
-	ESP32_PINMUX(3, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO3 ESP32_PINMUX(3, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO4 \
-	ESP32_PINMUX(4, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO4 ESP32_PINMUX(4, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO5 \
-	ESP32_PINMUX(5, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO5 ESP32_PINMUX(5, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO6 \
-	ESP32_PINMUX(6, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO6 ESP32_PINMUX(6, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO7 \
-	ESP32_PINMUX(7, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO7 ESP32_PINMUX(7, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO8 \
-	ESP32_PINMUX(8, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO8 ESP32_PINMUX(8, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO9 \
-	ESP32_PINMUX(9, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO9 ESP32_PINMUX(9, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO10 \
-	ESP32_PINMUX(10, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO10 ESP32_PINMUX(10, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO11 \
-	ESP32_PINMUX(11, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO11 ESP32_PINMUX(11, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO12 \
-	ESP32_PINMUX(12, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO12 ESP32_PINMUX(12, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO13 \
-	ESP32_PINMUX(13, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO13 ESP32_PINMUX(13, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO14 \
-	ESP32_PINMUX(14, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO14 ESP32_PINMUX(14, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO15 \
-	ESP32_PINMUX(15, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO15 ESP32_PINMUX(15, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO16 \
-	ESP32_PINMUX(16, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO16 ESP32_PINMUX(16, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO17 \
-	ESP32_PINMUX(17, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO17 ESP32_PINMUX(17, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO18 \
-	ESP32_PINMUX(18, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO18 ESP32_PINMUX(18, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO19 \
-	ESP32_PINMUX(19, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO19 ESP32_PINMUX(19, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO20 \
-	ESP32_PINMUX(20, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO20 ESP32_PINMUX(20, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO21 \
-	ESP32_PINMUX(21, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO21 ESP32_PINMUX(21, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO26 \
-	ESP32_PINMUX(26, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO26 ESP32_PINMUX(26, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO27 \
-	ESP32_PINMUX(27, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO27 ESP32_PINMUX(27, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO28 \
-	ESP32_PINMUX(28, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO28 ESP32_PINMUX(28, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO29 \
-	ESP32_PINMUX(29, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO29 ESP32_PINMUX(29, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO30 \
-	ESP32_PINMUX(30, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO30 ESP32_PINMUX(30, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO31 \
-	ESP32_PINMUX(31, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO31 ESP32_PINMUX(31, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO32 \
-	ESP32_PINMUX(32, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO32 ESP32_PINMUX(32, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO33 \
-	ESP32_PINMUX(33, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO33 ESP32_PINMUX(33, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO34 \
-	ESP32_PINMUX(34, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO34 ESP32_PINMUX(34, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO35 \
-	ESP32_PINMUX(35, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO35 ESP32_PINMUX(35, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO36 \
-	ESP32_PINMUX(36, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO36 ESP32_PINMUX(36, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO37 \
-	ESP32_PINMUX(37, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO37 ESP32_PINMUX(37, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO38 \
-	ESP32_PINMUX(38, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO38 ESP32_PINMUX(38, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO39 \
-	ESP32_PINMUX(39, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO39 ESP32_PINMUX(39, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO40 \
-	ESP32_PINMUX(40, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO40 ESP32_PINMUX(40, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO41 \
-	ESP32_PINMUX(41, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO41 ESP32_PINMUX(41, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO42 \
-	ESP32_PINMUX(42, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO42 ESP32_PINMUX(42, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO43 \
-	ESP32_PINMUX(43, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO43 ESP32_PINMUX(43, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO44 \
-	ESP32_PINMUX(44, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO44 ESP32_PINMUX(44, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO45 \
-	ESP32_PINMUX(45, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO45 ESP32_PINMUX(45, ESP_U0CTS_IN, ESP_NOSIG)
 
-#define UART0_CTS_GPIO46 \
-	ESP32_PINMUX(46, ESP_U0CTS_IN, ESP_NOSIG)
+#define UART0_CTS_GPIO46 ESP32_PINMUX(46, ESP_U0CTS_IN, ESP_NOSIG)
 
 /* UART0_DSR */
-#define UART0_DSR_GPIO0 \
-	ESP32_PINMUX(0, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO0 ESP32_PINMUX(0, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO1 \
-	ESP32_PINMUX(1, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO1 ESP32_PINMUX(1, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO2 \
-	ESP32_PINMUX(2, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO2 ESP32_PINMUX(2, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO3 \
-	ESP32_PINMUX(3, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO3 ESP32_PINMUX(3, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO4 \
-	ESP32_PINMUX(4, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO4 ESP32_PINMUX(4, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO5 \
-	ESP32_PINMUX(5, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO5 ESP32_PINMUX(5, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO6 \
-	ESP32_PINMUX(6, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO6 ESP32_PINMUX(6, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO7 \
-	ESP32_PINMUX(7, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO7 ESP32_PINMUX(7, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO8 \
-	ESP32_PINMUX(8, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO8 ESP32_PINMUX(8, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO9 \
-	ESP32_PINMUX(9, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO9 ESP32_PINMUX(9, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO10 \
-	ESP32_PINMUX(10, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO10 ESP32_PINMUX(10, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO11 \
-	ESP32_PINMUX(11, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO11 ESP32_PINMUX(11, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO12 \
-	ESP32_PINMUX(12, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO12 ESP32_PINMUX(12, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO13 \
-	ESP32_PINMUX(13, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO13 ESP32_PINMUX(13, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO14 \
-	ESP32_PINMUX(14, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO14 ESP32_PINMUX(14, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO15 \
-	ESP32_PINMUX(15, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO15 ESP32_PINMUX(15, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO16 \
-	ESP32_PINMUX(16, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO16 ESP32_PINMUX(16, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO17 \
-	ESP32_PINMUX(17, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO17 ESP32_PINMUX(17, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO18 \
-	ESP32_PINMUX(18, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO18 ESP32_PINMUX(18, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO19 \
-	ESP32_PINMUX(19, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO19 ESP32_PINMUX(19, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO20 \
-	ESP32_PINMUX(20, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO20 ESP32_PINMUX(20, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO21 \
-	ESP32_PINMUX(21, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO21 ESP32_PINMUX(21, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO26 \
-	ESP32_PINMUX(26, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO26 ESP32_PINMUX(26, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO27 \
-	ESP32_PINMUX(27, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO27 ESP32_PINMUX(27, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO28 \
-	ESP32_PINMUX(28, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO28 ESP32_PINMUX(28, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO29 \
-	ESP32_PINMUX(29, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO29 ESP32_PINMUX(29, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO30 \
-	ESP32_PINMUX(30, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO30 ESP32_PINMUX(30, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO31 \
-	ESP32_PINMUX(31, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO31 ESP32_PINMUX(31, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO32 \
-	ESP32_PINMUX(32, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO32 ESP32_PINMUX(32, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO33 \
-	ESP32_PINMUX(33, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO33 ESP32_PINMUX(33, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO34 \
-	ESP32_PINMUX(34, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO34 ESP32_PINMUX(34, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO35 \
-	ESP32_PINMUX(35, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO35 ESP32_PINMUX(35, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO36 \
-	ESP32_PINMUX(36, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO36 ESP32_PINMUX(36, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO37 \
-	ESP32_PINMUX(37, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO37 ESP32_PINMUX(37, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO38 \
-	ESP32_PINMUX(38, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO38 ESP32_PINMUX(38, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO39 \
-	ESP32_PINMUX(39, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO39 ESP32_PINMUX(39, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO40 \
-	ESP32_PINMUX(40, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO40 ESP32_PINMUX(40, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO41 \
-	ESP32_PINMUX(41, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO41 ESP32_PINMUX(41, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO42 \
-	ESP32_PINMUX(42, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO42 ESP32_PINMUX(42, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO43 \
-	ESP32_PINMUX(43, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO43 ESP32_PINMUX(43, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO44 \
-	ESP32_PINMUX(44, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO44 ESP32_PINMUX(44, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO45 \
-	ESP32_PINMUX(45, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO45 ESP32_PINMUX(45, ESP_U0DSR_IN, ESP_NOSIG)
 
-#define UART0_DSR_GPIO46 \
-	ESP32_PINMUX(46, ESP_U0DSR_IN, ESP_NOSIG)
+#define UART0_DSR_GPIO46 ESP32_PINMUX(46, ESP_U0DSR_IN, ESP_NOSIG)
 
 /* UART0_DTR */
-#define UART0_DTR_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_U0DTR_OUT)
 
-#define UART0_DTR_GPIO46 \
-	ESP32_PINMUX(46, ESP_NOSIG, ESP_U0DTR_OUT)
+#define UART0_DTR_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_U0DTR_OUT)
 
 /* UART0_RTS */
-#define UART0_RTS_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_U0RTS_OUT)
 
-#define UART0_RTS_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_U0RTS_OUT)
+#define UART0_RTS_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_U0RTS_OUT)
 
 /* UART0_RX */
-#define UART0_RX_GPIO0 \
-	ESP32_PINMUX(0, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO0 ESP32_PINMUX(0, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO1 \
-	ESP32_PINMUX(1, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO1 ESP32_PINMUX(1, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO2 \
-	ESP32_PINMUX(2, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO2 ESP32_PINMUX(2, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO3 \
-	ESP32_PINMUX(3, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO3 ESP32_PINMUX(3, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO4 \
-	ESP32_PINMUX(4, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO4 ESP32_PINMUX(4, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO5 \
-	ESP32_PINMUX(5, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO5 ESP32_PINMUX(5, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO6 \
-	ESP32_PINMUX(6, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO6 ESP32_PINMUX(6, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO7 \
-	ESP32_PINMUX(7, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO7 ESP32_PINMUX(7, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO8 \
-	ESP32_PINMUX(8, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO8 ESP32_PINMUX(8, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO9 \
-	ESP32_PINMUX(9, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO9 ESP32_PINMUX(9, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO10 \
-	ESP32_PINMUX(10, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO10 ESP32_PINMUX(10, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO11 \
-	ESP32_PINMUX(11, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO11 ESP32_PINMUX(11, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO12 \
-	ESP32_PINMUX(12, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO12 ESP32_PINMUX(12, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO13 \
-	ESP32_PINMUX(13, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO13 ESP32_PINMUX(13, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO14 \
-	ESP32_PINMUX(14, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO14 ESP32_PINMUX(14, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO15 \
-	ESP32_PINMUX(15, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO15 ESP32_PINMUX(15, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO16 \
-	ESP32_PINMUX(16, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO16 ESP32_PINMUX(16, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO17 \
-	ESP32_PINMUX(17, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO17 ESP32_PINMUX(17, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO18 \
-	ESP32_PINMUX(18, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO18 ESP32_PINMUX(18, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO19 \
-	ESP32_PINMUX(19, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO19 ESP32_PINMUX(19, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO20 \
-	ESP32_PINMUX(20, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO20 ESP32_PINMUX(20, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO21 \
-	ESP32_PINMUX(21, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO21 ESP32_PINMUX(21, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO26 \
-	ESP32_PINMUX(26, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO26 ESP32_PINMUX(26, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO27 \
-	ESP32_PINMUX(27, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO27 ESP32_PINMUX(27, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO28 \
-	ESP32_PINMUX(28, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO28 ESP32_PINMUX(28, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO29 \
-	ESP32_PINMUX(29, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO29 ESP32_PINMUX(29, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO30 \
-	ESP32_PINMUX(30, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO30 ESP32_PINMUX(30, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO31 \
-	ESP32_PINMUX(31, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO31 ESP32_PINMUX(31, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO32 \
-	ESP32_PINMUX(32, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO32 ESP32_PINMUX(32, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO33 \
-	ESP32_PINMUX(33, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO33 ESP32_PINMUX(33, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO34 \
-	ESP32_PINMUX(34, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO34 ESP32_PINMUX(34, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO35 \
-	ESP32_PINMUX(35, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO35 ESP32_PINMUX(35, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO36 \
-	ESP32_PINMUX(36, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO36 ESP32_PINMUX(36, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO37 \
-	ESP32_PINMUX(37, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO37 ESP32_PINMUX(37, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO38 \
-	ESP32_PINMUX(38, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO38 ESP32_PINMUX(38, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO39 \
-	ESP32_PINMUX(39, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO39 ESP32_PINMUX(39, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO40 \
-	ESP32_PINMUX(40, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO40 ESP32_PINMUX(40, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO41 \
-	ESP32_PINMUX(41, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO41 ESP32_PINMUX(41, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO42 \
-	ESP32_PINMUX(42, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO42 ESP32_PINMUX(42, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO43 \
-	ESP32_PINMUX(43, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO43 ESP32_PINMUX(43, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO44 \
-	ESP32_PINMUX(44, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO44 ESP32_PINMUX(44, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO45 \
-	ESP32_PINMUX(45, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO45 ESP32_PINMUX(45, ESP_U0RXD_IN, ESP_NOSIG)
 
-#define UART0_RX_GPIO46 \
-	ESP32_PINMUX(46, ESP_U0RXD_IN, ESP_NOSIG)
+#define UART0_RX_GPIO46 ESP32_PINMUX(46, ESP_U0RXD_IN, ESP_NOSIG)
 
 /* UART0_TX */
-#define UART0_TX_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_U0TXD_OUT)
 
-#define UART0_TX_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_U0TXD_OUT)
+#define UART0_TX_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_U0TXD_OUT)
 
 /* UART1_CTS */
-#define UART1_CTS_GPIO0 \
-	ESP32_PINMUX(0, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO0 ESP32_PINMUX(0, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO1 \
-	ESP32_PINMUX(1, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO1 ESP32_PINMUX(1, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO2 \
-	ESP32_PINMUX(2, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO2 ESP32_PINMUX(2, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO3 \
-	ESP32_PINMUX(3, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO3 ESP32_PINMUX(3, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO4 \
-	ESP32_PINMUX(4, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO4 ESP32_PINMUX(4, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO5 \
-	ESP32_PINMUX(5, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO5 ESP32_PINMUX(5, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO6 \
-	ESP32_PINMUX(6, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO6 ESP32_PINMUX(6, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO7 \
-	ESP32_PINMUX(7, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO7 ESP32_PINMUX(7, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO8 \
-	ESP32_PINMUX(8, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO8 ESP32_PINMUX(8, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO9 \
-	ESP32_PINMUX(9, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO9 ESP32_PINMUX(9, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO10 \
-	ESP32_PINMUX(10, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO10 ESP32_PINMUX(10, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO11 \
-	ESP32_PINMUX(11, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO11 ESP32_PINMUX(11, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO12 \
-	ESP32_PINMUX(12, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO12 ESP32_PINMUX(12, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO13 \
-	ESP32_PINMUX(13, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO13 ESP32_PINMUX(13, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO14 \
-	ESP32_PINMUX(14, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO14 ESP32_PINMUX(14, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO15 \
-	ESP32_PINMUX(15, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO15 ESP32_PINMUX(15, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO16 \
-	ESP32_PINMUX(16, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO16 ESP32_PINMUX(16, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO17 \
-	ESP32_PINMUX(17, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO17 ESP32_PINMUX(17, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO18 \
-	ESP32_PINMUX(18, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO18 ESP32_PINMUX(18, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO19 \
-	ESP32_PINMUX(19, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO19 ESP32_PINMUX(19, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO20 \
-	ESP32_PINMUX(20, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO20 ESP32_PINMUX(20, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO21 \
-	ESP32_PINMUX(21, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO21 ESP32_PINMUX(21, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO26 \
-	ESP32_PINMUX(26, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO26 ESP32_PINMUX(26, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO27 \
-	ESP32_PINMUX(27, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO27 ESP32_PINMUX(27, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO28 \
-	ESP32_PINMUX(28, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO28 ESP32_PINMUX(28, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO29 \
-	ESP32_PINMUX(29, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO29 ESP32_PINMUX(29, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO30 \
-	ESP32_PINMUX(30, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO30 ESP32_PINMUX(30, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO31 \
-	ESP32_PINMUX(31, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO31 ESP32_PINMUX(31, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO32 \
-	ESP32_PINMUX(32, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO32 ESP32_PINMUX(32, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO33 \
-	ESP32_PINMUX(33, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO33 ESP32_PINMUX(33, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO34 \
-	ESP32_PINMUX(34, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO34 ESP32_PINMUX(34, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO35 \
-	ESP32_PINMUX(35, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO35 ESP32_PINMUX(35, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO36 \
-	ESP32_PINMUX(36, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO36 ESP32_PINMUX(36, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO37 \
-	ESP32_PINMUX(37, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO37 ESP32_PINMUX(37, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO38 \
-	ESP32_PINMUX(38, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO38 ESP32_PINMUX(38, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO39 \
-	ESP32_PINMUX(39, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO39 ESP32_PINMUX(39, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO40 \
-	ESP32_PINMUX(40, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO40 ESP32_PINMUX(40, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO41 \
-	ESP32_PINMUX(41, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO41 ESP32_PINMUX(41, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO42 \
-	ESP32_PINMUX(42, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO42 ESP32_PINMUX(42, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO43 \
-	ESP32_PINMUX(43, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO43 ESP32_PINMUX(43, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO44 \
-	ESP32_PINMUX(44, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO44 ESP32_PINMUX(44, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO45 \
-	ESP32_PINMUX(45, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO45 ESP32_PINMUX(45, ESP_U1CTS_IN, ESP_NOSIG)
 
-#define UART1_CTS_GPIO46 \
-	ESP32_PINMUX(46, ESP_U1CTS_IN, ESP_NOSIG)
+#define UART1_CTS_GPIO46 ESP32_PINMUX(46, ESP_U1CTS_IN, ESP_NOSIG)
 
 /* UART1_DSR */
-#define UART1_DSR_GPIO0 \
-	ESP32_PINMUX(0, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO0 ESP32_PINMUX(0, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO1 \
-	ESP32_PINMUX(1, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO1 ESP32_PINMUX(1, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO2 \
-	ESP32_PINMUX(2, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO2 ESP32_PINMUX(2, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO3 \
-	ESP32_PINMUX(3, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO3 ESP32_PINMUX(3, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO4 \
-	ESP32_PINMUX(4, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO4 ESP32_PINMUX(4, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO5 \
-	ESP32_PINMUX(5, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO5 ESP32_PINMUX(5, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO6 \
-	ESP32_PINMUX(6, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO6 ESP32_PINMUX(6, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO7 \
-	ESP32_PINMUX(7, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO7 ESP32_PINMUX(7, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO8 \
-	ESP32_PINMUX(8, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO8 ESP32_PINMUX(8, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO9 \
-	ESP32_PINMUX(9, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO9 ESP32_PINMUX(9, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO10 \
-	ESP32_PINMUX(10, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO10 ESP32_PINMUX(10, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO11 \
-	ESP32_PINMUX(11, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO11 ESP32_PINMUX(11, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO12 \
-	ESP32_PINMUX(12, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO12 ESP32_PINMUX(12, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO13 \
-	ESP32_PINMUX(13, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO13 ESP32_PINMUX(13, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO14 \
-	ESP32_PINMUX(14, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO14 ESP32_PINMUX(14, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO15 \
-	ESP32_PINMUX(15, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO15 ESP32_PINMUX(15, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO16 \
-	ESP32_PINMUX(16, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO16 ESP32_PINMUX(16, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO17 \
-	ESP32_PINMUX(17, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO17 ESP32_PINMUX(17, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO18 \
-	ESP32_PINMUX(18, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO18 ESP32_PINMUX(18, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO19 \
-	ESP32_PINMUX(19, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO19 ESP32_PINMUX(19, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO20 \
-	ESP32_PINMUX(20, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO20 ESP32_PINMUX(20, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO21 \
-	ESP32_PINMUX(21, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO21 ESP32_PINMUX(21, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO26 \
-	ESP32_PINMUX(26, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO26 ESP32_PINMUX(26, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO27 \
-	ESP32_PINMUX(27, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO27 ESP32_PINMUX(27, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO28 \
-	ESP32_PINMUX(28, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO28 ESP32_PINMUX(28, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO29 \
-	ESP32_PINMUX(29, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO29 ESP32_PINMUX(29, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO30 \
-	ESP32_PINMUX(30, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO30 ESP32_PINMUX(30, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO31 \
-	ESP32_PINMUX(31, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO31 ESP32_PINMUX(31, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO32 \
-	ESP32_PINMUX(32, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO32 ESP32_PINMUX(32, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO33 \
-	ESP32_PINMUX(33, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO33 ESP32_PINMUX(33, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO34 \
-	ESP32_PINMUX(34, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO34 ESP32_PINMUX(34, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO35 \
-	ESP32_PINMUX(35, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO35 ESP32_PINMUX(35, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO36 \
-	ESP32_PINMUX(36, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO36 ESP32_PINMUX(36, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO37 \
-	ESP32_PINMUX(37, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO37 ESP32_PINMUX(37, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO38 \
-	ESP32_PINMUX(38, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO38 ESP32_PINMUX(38, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO39 \
-	ESP32_PINMUX(39, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO39 ESP32_PINMUX(39, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO40 \
-	ESP32_PINMUX(40, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO40 ESP32_PINMUX(40, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO41 \
-	ESP32_PINMUX(41, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO41 ESP32_PINMUX(41, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO42 \
-	ESP32_PINMUX(42, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO42 ESP32_PINMUX(42, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO43 \
-	ESP32_PINMUX(43, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO43 ESP32_PINMUX(43, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO44 \
-	ESP32_PINMUX(44, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO44 ESP32_PINMUX(44, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO45 \
-	ESP32_PINMUX(45, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO45 ESP32_PINMUX(45, ESP_U1DSR_IN, ESP_NOSIG)
 
-#define UART1_DSR_GPIO46 \
-	ESP32_PINMUX(46, ESP_U1DSR_IN, ESP_NOSIG)
+#define UART1_DSR_GPIO46 ESP32_PINMUX(46, ESP_U1DSR_IN, ESP_NOSIG)
 
 /* UART1_DTR */
-#define UART1_DTR_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_U1DTR_OUT)
 
-#define UART1_DTR_GPIO46 \
-	ESP32_PINMUX(46, ESP_NOSIG, ESP_U1DTR_OUT)
+#define UART1_DTR_GPIO46 ESP32_PINMUX(46, ESP_NOSIG, ESP_U1DTR_OUT)
 
 /* UART1_RTS */
-#define UART1_RTS_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_U1RTS_OUT)
 
-#define UART1_RTS_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_U1RTS_OUT)
+#define UART1_RTS_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_U1RTS_OUT)
 
 /* UART1_RX */
-#define UART1_RX_GPIO0 \
-	ESP32_PINMUX(0, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO0 ESP32_PINMUX(0, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO1 \
-	ESP32_PINMUX(1, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO1 ESP32_PINMUX(1, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO2 \
-	ESP32_PINMUX(2, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO2 ESP32_PINMUX(2, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO3 \
-	ESP32_PINMUX(3, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO3 ESP32_PINMUX(3, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO4 \
-	ESP32_PINMUX(4, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO4 ESP32_PINMUX(4, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO5 \
-	ESP32_PINMUX(5, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO5 ESP32_PINMUX(5, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO6 \
-	ESP32_PINMUX(6, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO6 ESP32_PINMUX(6, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO7 \
-	ESP32_PINMUX(7, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO7 ESP32_PINMUX(7, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO8 \
-	ESP32_PINMUX(8, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO8 ESP32_PINMUX(8, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO9 \
-	ESP32_PINMUX(9, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO9 ESP32_PINMUX(9, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO10 \
-	ESP32_PINMUX(10, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO10 ESP32_PINMUX(10, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO11 \
-	ESP32_PINMUX(11, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO11 ESP32_PINMUX(11, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO12 \
-	ESP32_PINMUX(12, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO12 ESP32_PINMUX(12, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO13 \
-	ESP32_PINMUX(13, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO13 ESP32_PINMUX(13, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO14 \
-	ESP32_PINMUX(14, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO14 ESP32_PINMUX(14, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO15 \
-	ESP32_PINMUX(15, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO15 ESP32_PINMUX(15, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO16 \
-	ESP32_PINMUX(16, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO16 ESP32_PINMUX(16, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO17 \
-	ESP32_PINMUX(17, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO17 ESP32_PINMUX(17, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO18 \
-	ESP32_PINMUX(18, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO18 ESP32_PINMUX(18, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO19 \
-	ESP32_PINMUX(19, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO19 ESP32_PINMUX(19, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO20 \
-	ESP32_PINMUX(20, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO20 ESP32_PINMUX(20, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO21 \
-	ESP32_PINMUX(21, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO21 ESP32_PINMUX(21, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO26 \
-	ESP32_PINMUX(26, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO26 ESP32_PINMUX(26, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO27 \
-	ESP32_PINMUX(27, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO27 ESP32_PINMUX(27, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO28 \
-	ESP32_PINMUX(28, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO28 ESP32_PINMUX(28, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO29 \
-	ESP32_PINMUX(29, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO29 ESP32_PINMUX(29, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO30 \
-	ESP32_PINMUX(30, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO30 ESP32_PINMUX(30, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO31 \
-	ESP32_PINMUX(31, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO31 ESP32_PINMUX(31, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO32 \
-	ESP32_PINMUX(32, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO32 ESP32_PINMUX(32, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO33 \
-	ESP32_PINMUX(33, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO33 ESP32_PINMUX(33, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO34 \
-	ESP32_PINMUX(34, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO34 ESP32_PINMUX(34, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO35 \
-	ESP32_PINMUX(35, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO35 ESP32_PINMUX(35, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO36 \
-	ESP32_PINMUX(36, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO36 ESP32_PINMUX(36, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO37 \
-	ESP32_PINMUX(37, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO37 ESP32_PINMUX(37, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO38 \
-	ESP32_PINMUX(38, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO38 ESP32_PINMUX(38, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO39 \
-	ESP32_PINMUX(39, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO39 ESP32_PINMUX(39, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO40 \
-	ESP32_PINMUX(40, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO40 ESP32_PINMUX(40, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO41 \
-	ESP32_PINMUX(41, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO41 ESP32_PINMUX(41, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO42 \
-	ESP32_PINMUX(42, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO42 ESP32_PINMUX(42, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO43 \
-	ESP32_PINMUX(43, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO43 ESP32_PINMUX(43, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO44 \
-	ESP32_PINMUX(44, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO44 ESP32_PINMUX(44, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO45 \
-	ESP32_PINMUX(45, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO45 ESP32_PINMUX(45, ESP_U1RXD_IN, ESP_NOSIG)
 
-#define UART1_RX_GPIO46 \
-	ESP32_PINMUX(46, ESP_U1RXD_IN, ESP_NOSIG)
+#define UART1_RX_GPIO46 ESP32_PINMUX(46, ESP_U1RXD_IN, ESP_NOSIG)
 
 /* UART1_TX */
-#define UART1_TX_GPIO0 \
-	ESP32_PINMUX(0, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO0 ESP32_PINMUX(0, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO1 \
-	ESP32_PINMUX(1, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO1 ESP32_PINMUX(1, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO2 \
-	ESP32_PINMUX(2, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO2 ESP32_PINMUX(2, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO3 \
-	ESP32_PINMUX(3, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO3 ESP32_PINMUX(3, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO4 \
-	ESP32_PINMUX(4, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO4 ESP32_PINMUX(4, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO5 \
-	ESP32_PINMUX(5, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO5 ESP32_PINMUX(5, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO6 \
-	ESP32_PINMUX(6, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO6 ESP32_PINMUX(6, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO7 \
-	ESP32_PINMUX(7, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO7 ESP32_PINMUX(7, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO8 \
-	ESP32_PINMUX(8, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO8 ESP32_PINMUX(8, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO9 \
-	ESP32_PINMUX(9, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO9 ESP32_PINMUX(9, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO10 \
-	ESP32_PINMUX(10, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO10 ESP32_PINMUX(10, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO11 \
-	ESP32_PINMUX(11, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO11 ESP32_PINMUX(11, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO12 \
-	ESP32_PINMUX(12, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO12 ESP32_PINMUX(12, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO13 \
-	ESP32_PINMUX(13, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO13 ESP32_PINMUX(13, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO14 \
-	ESP32_PINMUX(14, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO14 ESP32_PINMUX(14, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO15 \
-	ESP32_PINMUX(15, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO15 ESP32_PINMUX(15, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO16 \
-	ESP32_PINMUX(16, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO16 ESP32_PINMUX(16, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO17 \
-	ESP32_PINMUX(17, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO17 ESP32_PINMUX(17, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO18 \
-	ESP32_PINMUX(18, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO18 ESP32_PINMUX(18, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO19 \
-	ESP32_PINMUX(19, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO19 ESP32_PINMUX(19, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO20 \
-	ESP32_PINMUX(20, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO20 ESP32_PINMUX(20, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO21 \
-	ESP32_PINMUX(21, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO21 ESP32_PINMUX(21, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO26 \
-	ESP32_PINMUX(26, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO26 ESP32_PINMUX(26, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO27 \
-	ESP32_PINMUX(27, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO27 ESP32_PINMUX(27, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO28 \
-	ESP32_PINMUX(28, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO28 ESP32_PINMUX(28, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO29 \
-	ESP32_PINMUX(29, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO29 ESP32_PINMUX(29, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO30 \
-	ESP32_PINMUX(30, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO30 ESP32_PINMUX(30, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO31 \
-	ESP32_PINMUX(31, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO31 ESP32_PINMUX(31, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO32 \
-	ESP32_PINMUX(32, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO32 ESP32_PINMUX(32, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO33 \
-	ESP32_PINMUX(33, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO33 ESP32_PINMUX(33, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO34 \
-	ESP32_PINMUX(34, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO34 ESP32_PINMUX(34, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO35 \
-	ESP32_PINMUX(35, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO35 ESP32_PINMUX(35, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO36 \
-	ESP32_PINMUX(36, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO36 ESP32_PINMUX(36, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO37 \
-	ESP32_PINMUX(37, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO37 ESP32_PINMUX(37, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO38 \
-	ESP32_PINMUX(38, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO38 ESP32_PINMUX(38, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO39 \
-	ESP32_PINMUX(39, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO39 ESP32_PINMUX(39, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO40 \
-	ESP32_PINMUX(40, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO40 ESP32_PINMUX(40, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO41 \
-	ESP32_PINMUX(41, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO41 ESP32_PINMUX(41, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO42 \
-	ESP32_PINMUX(42, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO42 ESP32_PINMUX(42, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO43 \
-	ESP32_PINMUX(43, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO43 ESP32_PINMUX(43, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO44 \
-	ESP32_PINMUX(44, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO44 ESP32_PINMUX(44, ESP_NOSIG, ESP_U1TXD_OUT)
 
-#define UART1_TX_GPIO45 \
-	ESP32_PINMUX(45, ESP_NOSIG, ESP_U1TXD_OUT)
+#define UART1_TX_GPIO45 ESP32_PINMUX(45, ESP_NOSIG, ESP_U1TXD_OUT)
 
 
 #endif /* INC_DT_BINDS_PINCTRL_ESP32S2_PINCTRL_HAL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra-common.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra-common.h
deleted file mode 100644
index a7969523a93..00000000000
--- a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra-common.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RA_COMMON_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RA_COMMON_H_
-
-#define PORT4_POS  29
-#define PORT4_MASK 0x1
-#define PSEL_POS   24
-#define PSEL_MASK  0x5
-#define PORT_POS   21
-#define PORT_MASK  0x7
-#define PIN_POS    17
-#define PIN_MASK   0xF
-#define OPT_POS    0
-#define OPT_MASK   0x1B000
-
-#define RA_PINCFG_GPIO   0x00000
-#define RA_PINCFG_FUNC   0x10000
-#define RA_PINCFG_ANALOG 0x08000
-
-#define RA_PINCFG(port, pin, psel, opt)                                                            \
-	((((psel)&PSEL_MASK) << PSEL_POS) | (((pin)&PIN_MASK) << PIN_POS) |                        \
-	 (((port)&PORT_MASK) << PORT_POS) | ((((port) >> 3) & PORT4_MASK) << PORT4_POS) |          \
-	 (((opt)&OPT_MASK) << OPT_POS))
-
-#if RA_SOC_PINS >= 40
-#define RA_PINCFG__40(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt)
-#endif
-
-#if RA_SOC_PINS >= 48
-#define RA_PINCFG__48(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt)
-#endif
-
-#if RA_SOC_PINS >= 64
-#define RA_PINCFG__64(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt)
-#endif
-
-#if RA_SOC_PINS >= 100
-#define RA_PINCFG_100(port, pin, psel, opt) RA_PINCFG(port, pin, psel, opt)
-#endif
-
-#endif
diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h
index 5d88ea6eea8..cbb3dac6ffd 100644
--- a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h
+++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-ra.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -14,6 +14,9 @@
 #define RA_PIN_NUM_MASK 0xf
 
 #define RA_PSEL_HIZ_JTAG_SWD 0x0
+#define RA_PSEL_ADC          0x0
+#define RA_PSEL_DAC          0x0
+#define RA_PSEL_ACMPHS       0x0
 #define RA_PSEL_AGT          0x1
 #define RA_PSEL_GPT0         0x2
 #define RA_PSEL_GPT1         0x3
@@ -30,7 +33,9 @@
 #define RA_PSEL_SPI          0x6
 #define RA_PSEL_I2C          0x7
 #define RA_PSEL_CLKOUT_RTC   0x9
+#define RA_PSEL_ACMPHS_VCOUT 0x9
 #define RA_PSEL_CAC_ADC      0xa
+#define RA_PSEL_CAC_DAC      0xa
 #define RA_PSEL_BUS          0xb
 #define RA_PSEL_CANFD        0x10
 #define RA_PSEL_QSPI         0x11
@@ -42,7 +47,6 @@
 #define RA_PSEL_ETH_RMII     0x17
 #define RA_PSEL_GLCDC        0x19
 #define RA_PSEL_OSPI         0x1c
-#define RA_PSEL_ADC          0x00
 
 #define RA_PSEL_POS  8
 #define RA_PSEL_MASK 0x1f
diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza-common.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza-common.h
new file mode 100644
index 00000000000..38bf44752f9
--- /dev/null
+++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza-common.h
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA_COMMON_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA_COMMON_H_
+
+/* Superset list of all possible IO ports. */
+#define PORT_00 0x0000 /* IO port 0 */
+#define PORT_01 0x0100 /* IO port 1 */
+#define PORT_02 0x0200 /* IO port 2 */
+#define PORT_03 0x0300 /* IO port 3 */
+#define PORT_04 0x0400 /* IO port 4 */
+#define PORT_05 0x0500 /* IO port 5 */
+#define PORT_06 0x0600 /* IO port 6 */
+#define PORT_07 0x0700 /* IO port 7 */
+#define PORT_08 0x0800 /* IO port 8 */
+#define PORT_09 0x0900 /* IO port 9 */
+#define PORT_10 0x0A00 /* IO port 10 */
+#define PORT_11 0x0B00 /* IO port 11 */
+#define PORT_12 0x0C00 /* IO port 12 */
+#define PORT_13 0x0D00 /* IO port 13 */
+#define PORT_14 0x0E00 /* IO port 14 */
+#define PORT_15 0x0F00 /* IO port 15 */
+#define PORT_16 0x1000 /* IO port 16 */
+#define PORT_17 0x1100 /* IO port 17 */
+#define PORT_18 0x1200 /* IO port 18 */
+
+/*
+ * Create the value contain port/pin/function information
+ *
+ * port: port number BSP_IO_PORT_00..BSP_IO_PORT_18
+ * pin: pin number
+ * func: pin function
+ */
+#define RZA_PINMUX(port, pin, func) (port | pin | (func << 4))
+
+/* Special purpose port */
+#define BSP_IO_NMI 0xFFFF0100 /* NMI */
+
+#define BSP_IO_TMS_SWDIO 0xFFFF0200 /* TMS_SWDIO */
+
+#define BSP_IO_TDO 0xFFFF0300 /* TDO */
+
+#define BSP_IO_AUDIO_CLK1 0xFFFF0400 /* AUDIO_CLK1 */
+#define BSP_IO_AUDIO_CLK2 0xFFFF0401 /* AUDIO_CLK2 */
+
+#define BSP_IO_SD0_CLK   0xFFFF0600 /* CD0_CLK */
+#define BSP_IO_SD0_CMD   0xFFFF0601 /* CD0_CMD */
+#define BSP_IO_SD0_RST_N 0xFFFF0602 /* CD0_RST_N */
+
+#define BSP_IO_SD0_DATA0 0xFFFF0700 /* SD0_DATA0 */
+#define BSP_IO_SD0_DATA1 0xFFFF0701 /* SD0_DATA1 */
+#define BSP_IO_SD0_DATA2 0xFFFF0702 /* SD0_DATA2 */
+#define BSP_IO_SD0_DATA3 0xFFFF0703 /* SD0_DATA3 */
+#define BSP_IO_SD0_DATA4 0xFFFF0704 /* SD0_DATA4 */
+#define BSP_IO_SD0_DATA5 0xFFFF0705 /* SD0_DATA5 */
+#define BSP_IO_SD0_DATA6 0xFFFF0706 /* SD0_DATA6 */
+#define BSP_IO_SD0_DATA7 0xFFFF0707 /* SD0_DATA7 */
+
+#define BSP_IO_SD1_CLK 0xFFFF0800 /* SD1_CLK */
+#define BSP_IO_SD1_CMD 0xFFFF0801 /* SD1_CMD */
+
+#define BSP_IO_SD1_DATA0 0xFFFF0900 /* SD1_DATA0 */
+#define BSP_IO_SD1_DATA1 0xFFFF0901 /* SD1_DATA1 */
+#define BSP_IO_SD1_DATA2 0xFFFF0902 /* SD1_DATA2 */
+#define BSP_IO_SD1_DATA3 0xFFFF0903 /* SD1_DATA3 */
+
+#define BSP_IO_QSPI0_SPCLK 0xFFFF0A00 /* QSPI0_SPCLK */
+#define BSP_IO_QSPI0_IO0   0xFFFF0A01 /* QSPI0_IO0 */
+#define BSP_IO_QSPI0_IO1   0xFFFF0A02 /* QSPI0_IO1 */
+#define BSP_IO_QSPI0_IO2   0xFFFF0A03 /* QSPI0_IO2 */
+#define BSP_IO_QSPI0_IO3   0xFFFF0A04 /* QSPI0_IO3 */
+#define BSP_IO_QSPI0_SSL   0xFFFF0A05 /* QSPI0_SSL */
+
+#define BSP_IO_OM_CS1_N 0xFFFF0B00 /* OM_CS1_N */
+#define BSP_IO_OM_DQS   0xFFFF0B01 /* OM_DQS */
+#define BSP_IO_OM_SIO4  0xFFFF0B02 /* OM_SIO4 */
+#define BSP_IO_OM_SIO5  0xFFFF0B03 /* OM_SIO5 */
+#define BSP_IO_OM_SIO6  0xFFFF0B04 /* OM_SIO6 */
+#define BSP_IO_OM_SIO7  0xFFFF0B05 /* OM_SIO7 */
+
+#define BSP_IO_QSPI_RESET_N 0xFFFF0C00 /* QSPI_RESET_N */
+#define BSP_IO_QSPI_WP_N    0xFFFF0C01 /* QSPI_WP_N */
+
+#define BSP_IO_WDTOVF_PERROUT_N 0xFFFF0D00 /* WDTOVF_PERROUT_N */
+
+#define BSP_IO_RIIC0_SDA 0xFFFF0E00 /* RIIC0_SDA */
+#define BSP_IO_RIIC0_SCL 0xFFFF0E01 /* RIIC0_SCL */
+#define BSP_IO_RIIC1_SDA 0xFFFF0E02 /* RIIC1_SDA */
+#define BSP_IO_RIIC1_SCL 0xFFFF0E03 /* RIIC1_SCL */
+
+/* FILNUM */
+#define RZA_FILNUM_4_STAGE  0
+#define RZA_FILNUM_8_STAGE  1
+#define RZA_FILNUM_12_STAGE 2
+#define RZA_FILNUM_16_STAGE 3
+
+/* FILCLKSEL */
+#define RZA_FILCLKSEL_NOT_DIV   0
+#define RZA_FILCLKSEL_DIV_9000  1
+#define RZA_FILCLKSEL_DIV_18000 2
+#define RZA_FILCLKSEL_DIV_36000 3
+
+#define RZA_FILTER_SET(filnum, filclksel) (((filnum) & 0x3) << 0x2) | (filclksel & 0x3)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA_COMMON_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza2m.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza2m.h
new file mode 100644
index 00000000000..37468be63f0
--- /dev/null
+++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rza2m.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA2M_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA2M_H_
+
+#define RZA2M_PIN_NUM_IN_PORT 8
+
+/* Port names as labeled in the Hardware Manual */
+#define PORT_00 0
+#define PORT_01 1
+#define PORT_02 2
+#define PORT_03 3
+#define PORT_04 4
+#define PORT_05 5
+#define PORT_06 6
+#define PORT_07 7
+#define PORT_08 8
+#define PORT_09 9
+#define PORT_A  10
+#define PORT_B  11
+#define PORT_C  12
+#define PORT_D  13
+#define PORT_E  14
+#define PORT_F  15
+#define PORT_G  16
+#define PORT_H  17
+/* No I */
+#define PORT_J  18
+#define PORT_K  19
+#define PORT_L  20
+#define PORT_M  21 /* Pins PM_0/1 are labeled JP_0/1 in HW manual */
+
+#define PORT_CKIO 22
+#define PORT_PPOC 23 /* Select between 1.8V and 3.3V for SPI and SD/MMC */
+
+#define PIN_POSEL 0 /* Sets function for POSEL0 bits. 00, 01, 10 - 1.8v, 11 - 3.3v */
+#define PIN_POC2  1 /* Sets function for SSD host 0, 0 - 1.8v 1 - 3.3v */
+#define PIN_POC3  2 /* Sets function for SSD host 1, 0 - 1.8v 1 - 3.3v */
+
+/*
+ * Create the pin index from its bank and position numbers and store in
+ * the upper 16 bits the alternate function identifier
+ */
+#define RZA2M_PINMUX(b, p, f) ((b) * RZA2M_PIN_NUM_IN_PORT + (p) | (f << 16))
+
+#define CKIO_DRV RZA2M_PINMUX(PORT_CKIO, 0, 0)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZA2M_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h
index da9266ac780..2f03d21fec7 100644
--- a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h
+++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg-common.h
@@ -101,4 +101,4 @@
 
 #define RZG_FILTER_SET(filnum, filclksel) (((filnum) & 0x3) << 0x2) | (filclksel & 0x3)
 
-#endif /*ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_*/
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG_COMMON_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg2-common.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg2-common.h
new file mode 100644
index 00000000000..e73df800bad
--- /dev/null
+++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzg2-common.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG2_COMMON_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG2_COMMON_H_
+
+/* Superset list of all possible IO ports. */
+#define PORT_00 0x0000 /* IO port 0 */
+#define PORT_01 0x0100 /* IO port 1 */
+#define PORT_02 0x0200 /* IO port 2 */
+#define PORT_03 0x0300 /* IO port 3 */
+#define PORT_04 0x0400 /* IO port 4 */
+#define PORT_05 0x0500 /* IO port 5 */
+#define PORT_06 0x0600 /* IO port 6 */
+#define PORT_07 0x0700 /* IO port 7 */
+#define PORT_08 0x0800 /* IO port 8 */
+#define PORT_09 0x0900 /* IO port 9 */
+#define PORT_10 0x0A00 /* IO port 10 */
+#define PORT_11 0x0B00 /* IO port 11 */
+#define PORT_12 0x0C00 /* IO port 12 */
+#define PORT_13 0x0D00 /* IO port 13 */
+#define PORT_14 0x0E00 /* IO port 14 */
+#define PORT_15 0x0F00 /* IO port 15 */
+#define PORT_16 0x1000 /* IO port 16 */
+#define PORT_17 0x1100 /* IO port 17 */
+#define PORT_18 0x1200 /* IO port 18 */
+#define PORT_19 0x1300 /* IO port 19 */
+#define PORT_20 0x1400 /* IO port 20 */
+#define PORT_21 0x1500 /* IO port 21 */
+#define PORT_22 0x1600 /* IO port 22 */
+#define PORT_23 0x1700 /* IO port 23 */
+#define PORT_24 0x1800 /* IO port 24 */
+#define PORT_25 0x1900 /* IO port 25 */
+#define PORT_26 0x1A00 /* IO port 26 */
+#define PORT_27 0x1B00 /* IO port 27 */
+#define PORT_28 0x1C00 /* IO port 28 */
+#define PORT_29 0x1D00 /* IO port 29 */
+#define PORT_30 0x1E00 /* IO port 30 */
+#define PORT_31 0x1F00 /* IO port 31 */
+#define PORT_32 0x2000 /* IO port 32 */
+#define PORT_33 0x2100 /* IO port 33 */
+#define PORT_34 0x2200 /* IO port 34 */
+#define PORT_35 0x2300 /* IO port 35 */
+#define PORT_36 0x2400 /* IO port 36 */
+#define PORT_37 0x2500 /* IO port 37 */
+#define PORT_38 0x2600 /* IO port 38 */
+#define PORT_39 0x2700 /* IO port 39 */
+#define PORT_40 0x2800 /* IO port 40 */
+#define PORT_41 0x2900 /* IO port 41 */
+#define PORT_42 0x2A00 /* IO port 42 */
+#define PORT_43 0x2B00 /* IO port 43 */
+#define PORT_44 0x2C00 /* IO port 44 */
+#define PORT_45 0x2D00 /* IO port 45 */
+#define PORT_46 0x2E00 /* IO port 46 */
+#define PORT_47 0x2F00 /* IO port 47 */
+#define PORT_48 0x3000 /* IO port 48 */
+
+/*
+ * Create the value contain port/pin/function information
+ *
+ * port: port number BSP_IO_PORT_00..BSP_IO_PORT_48
+ * pin: pin number
+ * func: pin function
+ */
+#define RZG_PINMUX(port, pin, func) (port | pin | (func << 4))
+
+/* Special purpose port */
+#define BSP_IO_NMI 0xFFFF0100 /* NMI */
+
+#define BSP_IO_TMS_SWDIO 0xFFFF0200 /* TMS_SWDIO */
+#define BSP_IO_TDO       0xFFFF0300 /* TDO */
+
+#define BSP_IO_AUDIO_CLK1 0xFFFF0400 /* AUDIO_CLK1 */
+#define BSP_IO_AUDIO_CLK2 0xFFFF0401 /* AUDIO_CLK2 */
+
+#define BSP_IO_SD0_CLK   0xFFFF0600 /* SD0_CLK */
+#define BSP_IO_SD0_CMD   0xFFFF0601 /* SD0_CMD */
+#define BSP_IO_SD0_RST_N 0xFFFF0602 /* SD0_RST_N */
+
+#define BSP_IO_SD0_DATA0 0xFFFF0700 /* SD0_DATA0 */
+#define BSP_IO_SD0_DATA1 0xFFFF0701 /* SD0_DATA1 */
+#define BSP_IO_SD0_DATA2 0xFFFF0702 /* SD0_DATA2 */
+#define BSP_IO_SD0_DATA3 0xFFFF0703 /* SD0_DATA3 */
+#define BSP_IO_SD0_DATA4 0xFFFF0704 /* SD0_DATA4 */
+#define BSP_IO_SD0_DATA5 0xFFFF0705 /* SD0_DATA5 */
+#define BSP_IO_SD0_DATA6 0xFFFF0706 /* SD0_DATA6 */
+#define BSP_IO_SD0_DATA7 0xFFFF0707 /* SD0_DATA7 */
+
+#define BSP_IO_SD1_CLK 0xFFFF0800 /* SD1_CLK */
+#define BSP_IO_SD1_CMD 0xFFFF0801 /* SD1_CMD */
+
+#define BSP_IO_SD1_DATA0 0xFFFF0900 /* SD1_DATA0 */
+#define BSP_IO_SD1_DATA1 0xFFFF0901 /* SD1_DATA1 */
+#define BSP_IO_SD1_DATA2 0xFFFF0902 /* SD1_DATA2 */
+#define BSP_IO_SD1_DATA3 0xFFFF0903 /* SD1_DATA3 */
+
+#define BSP_IO_QSPI0_SPCLK 0xFFFF0A00 /* QSPI0_SPCLK */
+#define BSP_IO_QSPI0_IO0   0xFFFF0A01 /* QSPI0_IO0 */
+#define BSP_IO_QSPI0_IO1   0xFFFF0A02 /* QSPI0_IO1 */
+#define BSP_IO_QSPI0_IO2   0xFFFF0A03 /* QSPI0_IO2 */
+#define BSP_IO_QSPI0_IO3   0xFFFF0A04 /* QSPI0_IO3 */
+#define BSP_IO_QSPI0_SSL   0xFFFF0A05 /* QSPI0_SSL */
+
+#define BSP_IO_QSPI1_SPCLK 0xFFFF0B00 /* QSPI1_SPCLK */
+#define BSP_IO_QSPI1_IO0   0xFFFF0B01 /* QSPI1_IO0 */
+#define BSP_IO_QSPI1_IO1   0xFFFF0B02 /* QSPI1_IO1 */
+#define BSP_IO_QSPI1_IO2   0xFFFF0B03 /* QSPI1_IO2 */
+#define BSP_IO_QSPI1_IO3   0xFFFF0B04 /* QSPI1_IO3 */
+#define BSP_IO_QSPI1_SSL   0xFFFF0B05 /* QSPI1_SSL */
+
+#define BSP_IO_QSPI_RESET_N 0xFFFF0C00 /* QSPI_RESET_N */
+#define BSP_IO_QSPI_WP_N    0xFFFF0C01 /* QSPI_WP_N */
+#define BSP_IO_QSPI_INT_N   0xFFFF0C02 /* QSPI_INT_N */
+
+#define BSP_IO_WDTOVF_PERROUT_N 0xFFFF0D00 /* WDTOVF_PERROUT_N */
+
+#define BSP_IO_RIIC0_SDA 0xFFFF0E00 /* RIIC0_SDA */
+#define BSP_IO_RIIC0_SCL 0xFFFF0E01 /* RIIC0_SCL */
+#define BSP_IO_RIIC1_SDA 0xFFFF0E02 /* RIIC1_SDA */
+#define BSP_IO_RIIC1_SCL 0xFFFF0E03 /* RIIC1_SCL */
+
+/* FILNUM */
+#define RZG_FILNUM_4_STAGE  0
+#define RZG_FILNUM_8_STAGE  1
+#define RZG_FILNUM_12_STAGE 2
+#define RZG_FILNUM_16_STAGE 3
+
+/* FILCLKSEL */
+#define RZG_FILCLKSEL_NOT_DIV   0
+#define RZG_FILCLKSEL_DIV_9000  1
+#define RZG_FILCLKSEL_DIV_18000 2
+#define RZG_FILCLKSEL_DIV_36000 3
+
+#define RZG_FILTER_SET(filnum, filclksel) (((filnum) & 0x3) << 0x2) | (filclksel & 0x3)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZG2_COMMON_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzn-common.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzn-common.h
new file mode 100644
index 00000000000..36d1da14989
--- /dev/null
+++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzn-common.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZN_COMMON_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZN_COMMON_H_
+
+/* Superset list of all possible IO ports. */
+#define PORT_00 0x0000 /* IO port 0 */
+#define PORT_01 0x0100 /* IO port 1 */
+#define PORT_02 0x0200 /* IO port 2 */
+#define PORT_03 0x0300 /* IO port 3 */
+#define PORT_04 0x0400 /* IO port 4 */
+#define PORT_05 0x0500 /* IO port 5 */
+#define PORT_06 0x0600 /* IO port 6 */
+#define PORT_07 0x0700 /* IO port 7 */
+#define PORT_08 0x0800 /* IO port 8 */
+#define PORT_09 0x0900 /* IO port 9 */
+#define PORT_10 0x0A00 /* IO port 10 */
+#define PORT_11 0x0B00 /* IO port 11 */
+#define PORT_12 0x0C00 /* IO port 12 */
+#define PORT_13 0x0D00 /* IO port 13 */
+#define PORT_14 0x0E00 /* IO port 14 */
+#define PORT_15 0x0F00 /* IO port 15 */
+#define PORT_16 0x1000 /* IO port 16 */
+#define PORT_17 0x1100 /* IO port 17 */
+#define PORT_18 0x1200 /* IO port 18 */
+#define PORT_19 0x1300 /* IO port 19 */
+#define PORT_20 0x1400 /* IO port 20 */
+#define PORT_21 0x1500 /* IO port 21 */
+#define PORT_22 0x1600 /* IO port 22 */
+#define PORT_23 0x1700 /* IO port 23 */
+#define PORT_24 0x1800 /* IO port 24 */
+
+/*
+ * Create the value contain port/pin/function information
+ *
+ * port: port number BSP_IO_PORT_00..BSP_IO_PORT_34
+ * pin: pin number
+ * func: pin function
+ */
+#define RZN_PINMUX(port, pin, func) (port | pin | (func << 4))
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZN_COMMON_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzt-common.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzt-common.h
new file mode 100644
index 00000000000..52b78c38dc5
--- /dev/null
+++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzt-common.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZT_COMMON_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZT_COMMON_H_
+
+/* Superset list of all possible IO ports. */
+#define PORT_00 0x0000 /* IO port 0 */
+#define PORT_01 0x0100 /* IO port 1 */
+#define PORT_02 0x0200 /* IO port 2 */
+#define PORT_03 0x0300 /* IO port 3 */
+#define PORT_04 0x0400 /* IO port 4 */
+#define PORT_05 0x0500 /* IO port 5 */
+#define PORT_06 0x0600 /* IO port 6 */
+#define PORT_07 0x0700 /* IO port 7 */
+#define PORT_08 0x0800 /* IO port 8 */
+#define PORT_09 0x0900 /* IO port 9 */
+#define PORT_10 0x0A00 /* IO port 10 */
+#define PORT_11 0x0B00 /* IO port 11 */
+#define PORT_12 0x0C00 /* IO port 12 */
+#define PORT_13 0x0D00 /* IO port 13 */
+#define PORT_14 0x0E00 /* IO port 14 */
+#define PORT_15 0x0F00 /* IO port 15 */
+#define PORT_16 0x1000 /* IO port 16 */
+#define PORT_17 0x1100 /* IO port 17 */
+#define PORT_18 0x1200 /* IO port 18 */
+#define PORT_19 0x1300 /* IO port 19 */
+#define PORT_20 0x1400 /* IO port 20 */
+#define PORT_21 0x1500 /* IO port 21 */
+#define PORT_22 0x1600 /* IO port 22 */
+#define PORT_23 0x1700 /* IO port 23 */
+#define PORT_24 0x1800 /* IO port 24 */
+
+/*
+ * Create the value contain port/pin/function information
+ *
+ * port: port number BSP_IO_PORT_00..BSP_IO_PORT_24
+ * pin: pin number
+ * func: pin function
+ */
+#define RZT_PINMUX(port, pin, func) (port | pin | (func << 4))
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZT_COMMON_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzv-common.h b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzv-common.h
new file mode 100644
index 00000000000..2d2ae8f32b9
--- /dev/null
+++ b/include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-rzv-common.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZV_COMMON_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZV_COMMON_H_
+
+/* Superset list of all possible IO ports. */
+#define PORT_00 0x0000 /* IO port 0 */
+#define PORT_01 0x0100 /* IO port 1 */
+#define PORT_02 0x0200 /* IO port 2 */
+#define PORT_03 0x0300 /* IO port 3 */
+#define PORT_04 0x0400 /* IO port 4 */
+#define PORT_05 0x0500 /* IO port 5 */
+#define PORT_06 0x0600 /* IO port 6 */
+#define PORT_07 0x0700 /* IO port 7 */
+#define PORT_08 0x0800 /* IO port 8 */
+#define PORT_09 0x0900 /* IO port 9 */
+#define PORT_10 0x0A00 /* IO port 10 */
+#define PORT_11 0x0B00 /* IO port 11 */
+#define PORT_12 0x0C00 /* IO port 12 */
+#define PORT_13 0x0D00 /* IO port 13 */
+#define PORT_14 0x0E00 /* IO port 14 */
+#define PORT_15 0x0F00 /* IO port 15 */
+#define PORT_16 0x1000 /* IO port 16 */
+#define PORT_17 0x1100 /* IO port 17 */
+#define PORT_18 0x1200 /* IO port 18 */
+#define PORT_19 0x1300 /* IO port 19 */
+#define PORT_20 0x1400 /* IO port 20 */
+#define PORT_21 0x1500 /* IO port 21 */
+#define PORT_22 0x1600 /* IO port 22 */
+#define PORT_23 0x1700 /* IO port 23 */
+#define PORT_24 0x1800 /* IO port 24 */
+#define PORT_25 0x1900 /* IO port 25 */
+#define PORT_26 0x1A00 /* IO port 26 */
+#define PORT_27 0x1B00 /* IO port 27 */
+#define PORT_28 0x1C00 /* IO port 28 */
+#define PORT_29 0x1D00 /* IO port 29 */
+#define PORT_30 0x1E00 /* IO port 30 */
+#define PORT_31 0x1F00 /* IO port 31 */
+#define PORT_32 0x2000 /* IO port 32 */
+#define PORT_33 0x2100 /* IO port 33 */
+#define PORT_34 0x2200 /* IO port 34 */
+#define PORT_35 0x2300 /* IO port 35 */
+#define PORT_36 0x2400 /* IO port 36 */
+#define PORT_37 0x2500 /* IO port 37 */
+#define PORT_38 0x2600 /* IO port 38 */
+#define PORT_39 0x2700 /* IO port 39 */
+#define PORT_40 0x2800 /* IO port 40 */
+#define PORT_41 0x2900 /* IO port 41 */
+#define PORT_42 0x2A00 /* IO port 42 */
+#define PORT_43 0x2B00 /* IO port 43 */
+#define PORT_44 0x2C00 /* IO port 44 */
+#define PORT_45 0x2D00 /* IO port 45 */
+#define PORT_46 0x2E00 /* IO port 46 */
+#define PORT_47 0x2F00 /* IO port 47 */
+#define PORT_48 0x3000 /* IO port 48 */
+
+/*
+ * Create the value contain port/pin/function information
+ *
+ * port: port number BSP_IO_PORT_00..BSP_IO_PORT_48
+ * pin: pin number
+ * func: pin function
+ */
+#define RZV_PINMUX(port, pin, func) (port | pin | (func << 4))
+
+/* Special purpose port */
+#define BSP_IO_NMI 0xFFFF0100 /* NMI */
+
+#define BSP_IO_TMS_SWDIO 0xFFFF0200 /* TMS_SWDIO */
+
+#define BSP_IO_TDO 0xFFFF0300 /* TDO */
+
+#define BSP_IO_AUDIO_CLK1 0xFFFF0400 /* AUDIO_CLK1 */
+#define BSP_IO_AUDIO_CLK2 0xFFFF0401 /* AUDIO_CLK2 */
+
+#define BSP_IO_SD0_CLK   0xFFFF0600 /* SD0_CLK */
+#define BSP_IO_SD0_CMD   0xFFFF0601 /* SD0_CMD */
+#define BSP_IO_SD0_RST_N 0xFFFF0602 /* SD0_RST_N */
+
+#define BSP_IO_SD0_DATA0 0xFFFF0700 /* SD0_DATA0 */
+#define BSP_IO_SD0_DATA1 0xFFFF0701 /* SD0_DATA1 */
+#define BSP_IO_SD0_DATA2 0xFFFF0702 /* SD0_DATA2 */
+#define BSP_IO_SD0_DATA3 0xFFFF0703 /* SD0_DATA3 */
+#define BSP_IO_SD0_DATA4 0xFFFF0704 /* SD0_DATA4 */
+#define BSP_IO_SD0_DATA5 0xFFFF0705 /* SD0_DATA5 */
+#define BSP_IO_SD0_DATA6 0xFFFF0706 /* SD0_DATA6 */
+#define BSP_IO_SD0_DATA7 0xFFFF0707 /* SD0_DATA7 */
+
+#define BSP_IO_SD1_CLK 0xFFFF0800 /* SD1_CLK */
+#define BSP_IO_SD1_CMD 0xFFFF0801 /* SD1_CMD */
+
+#define BSP_IO_SD1_DATA0 0xFFFF0900 /* SD1_DATA0 */
+#define BSP_IO_SD1_DATA1 0xFFFF0901 /* SD1_DATA1 */
+#define BSP_IO_SD1_DATA2 0xFFFF0902 /* SD1_DATA2 */
+#define BSP_IO_SD1_DATA3 0xFFFF0903 /* SD1_DATA3 */
+
+#define BSP_IO_QSPI0_SPCLK 0xFFFF0A00 /* QSPI0_SPCLK */
+#define BSP_IO_QSPI0_IO0   0xFFFF0A01 /* QSPI0_IO0 */
+#define BSP_IO_QSPI0_IO1   0xFFFF0A02 /* QSPI0_IO1 */
+#define BSP_IO_QSPI0_IO2   0xFFFF0A03 /* QSPI0_IO2 */
+#define BSP_IO_QSPI0_IO3   0xFFFF0A04 /* QSPI0_IO3 */
+#define BSP_IO_QSPI0_SSL   0xFFFF0A05 /* QSPI0_SSL */
+
+#define BSP_IO_QSPI1_SPCLK 0xFFFF0B00 /* QSPI1_SPCLK */
+#define BSP_IO_QSPI1_IO0   0xFFFF0B01 /* QSPI1_IO0 */
+#define BSP_IO_QSPI1_IO1   0xFFFF0B02 /* QSPI1_IO1 */
+#define BSP_IO_QSPI1_IO2   0xFFFF0B03 /* QSPI1_IO2 */
+#define BSP_IO_QSPI1_IO3   0xFFFF0B04 /* QSPI1_IO3 */
+#define BSP_IO_QSPI1_SSL   0xFFFF0B05 /* QSPI1_SSL */
+
+#define BSP_IO_QSPI_RESET_N 0xFFFF0C00 /* QSPI_RESET_N */
+#define BSP_IO_QSPI_WP_N    0xFFFF0C01 /* QSPI_WP_N */
+#define BSP_IO_QSPI_INT_N   0xFFFF0C02 /* QSPI_INT_N */
+
+#define BSP_IO_WDTOVF_PERROUT_N 0xFFFF0D00 /* WDTOVF_PERROUT_N */
+
+#define BSP_IO_RIIC0_SDA 0xFFFF0E00 /* RIIC0_SDA */
+#define BSP_IO_RIIC0_SCL 0xFFFF0E01 /* RIIC0_SCL */
+#define BSP_IO_RIIC1_SDA 0xFFFF0E02 /* RIIC1_SDA */
+#define BSP_IO_RIIC1_SCL 0xFFFF0E03 /* RIIC1_SCL */
+
+/* FILNUM */
+#define RZV_FILNUM_4_STAGE  0
+#define RZV_FILNUM_8_STAGE  1
+#define RZV_FILNUM_12_STAGE 2
+#define RZV_FILNUM_16_STAGE 3
+
+/* FILCLKSEL */
+#define RZV_FILCLKSEL_NOT_DIV   0
+#define RZV_FILCLKSEL_DIV_9000  1
+#define RZV_FILCLKSEL_DIV_18000 2
+#define RZV_FILCLKSEL_DIV_36000 3
+
+#define RZV_FILTER_SET(filnum, filclksel) (((filnum) & 0x3) << 0x2) | (filclksel & 0x3)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_RZV_COMMON_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/silabs-pinctrl-dbus.h b/include/zephyr/dt-bindings/pinctrl/silabs-pinctrl-dbus.h
index 9ad02a5cd0f..c28d87432af 100644
--- a/include/zephyr/dt-bindings/pinctrl/silabs-pinctrl-dbus.h
+++ b/include/zephyr/dt-bindings/pinctrl/silabs-pinctrl-dbus.h
@@ -11,7 +11,10 @@
 /*
  * Silabs Series 2 DBUS configuration is encoded in a 32-bit bitfield organized as follows:
  *
- * 31..29: Reserved
+ * 31    : Whether the configuration represents an analog pin
+ * If digital (bit 31 == 0):
+ * 30    : Reserved
+ * 29    : Route register presence (fixed routes have no route register)
  * 28..24: Route register offset in words from peripheral config (offset of <fun>ROUTE
  *         register in GPIO_<periph>ROUTE_TypeDef)
  * 23..19: Enable bit (offset into ROUTEEN register for given function)
@@ -20,6 +23,11 @@
  *         register in GPIO_TypeDef minus offset of first route register [DBGROUTEPEN, 0x440])
  *  7..4 : GPIO pin
  *  3..0 : GPIO port
+ * If analog (bit 31 == 1):
+ * 15..14: Bus selection (A, B, CD)
+ * 13..12: Bus selection (EVEN0, EVEN1, ODD0, ODD1)
+ * 11..8 : Peripheral selection (bit in GPIO_nBUSALLOC bitfield)
+ * 7 ..0 : Reserved
  */
 
 #define SILABS_PINCTRL_GPIO_PORT_MASK   0x0000000FUL
@@ -28,6 +36,15 @@
 #define SILABS_PINCTRL_HAVE_EN_MASK     0x00040000UL
 #define SILABS_PINCTRL_EN_BIT_MASK      0x00F80000UL
 #define SILABS_PINCTRL_ROUTE_MASK       0x1F000000UL
+#define SILABS_PINCTRL_HAVE_ROUTE_MASK  0x20000000UL
+
+#define SILABS_PINCTRL_ANALOG_MASK      0x80000000UL
+#define SILABS_PINCTRL_ABUS_BUS_MASK    0x0000C000UL
+#define SILABS_PINCTRL_ABUS_PARITY_MASK 0x00003000UL
+#define SILABS_PINCTRL_ABUS_PERIPH_MASK 0x00000F00UL
+
+#define SILABS_PINCTRL_UNUSED 0xFF
+#define SILABS_PINCTRL_ANALOG 0xAA
 
 #define SILABS_DBUS(port, pin, periph_base, en_present, en_bit, route)                             \
 	(FIELD_PREP(SILABS_PINCTRL_GPIO_PORT_MASK, port) |                                         \
@@ -35,6 +52,21 @@
 	 FIELD_PREP(SILABS_PINCTRL_PERIPH_BASE_MASK, periph_base) |                                \
 	 FIELD_PREP(SILABS_PINCTRL_HAVE_EN_MASK, en_present) |                                     \
 	 FIELD_PREP(SILABS_PINCTRL_EN_BIT_MASK, en_bit) |                                          \
-	 FIELD_PREP(SILABS_PINCTRL_ROUTE_MASK, route))
+	 FIELD_PREP(SILABS_PINCTRL_ROUTE_MASK, route) |                                            \
+	 FIELD_PREP(SILABS_PINCTRL_HAVE_ROUTE_MASK, 1))
+
+#define SILABS_FIXED_ROUTE(port, pin, periph_base, en_bit)                                         \
+	(FIELD_PREP(SILABS_PINCTRL_GPIO_PORT_MASK, port) |                                         \
+	 FIELD_PREP(SILABS_PINCTRL_GPIO_PIN_MASK, pin) |                                           \
+	 FIELD_PREP(SILABS_PINCTRL_PERIPH_BASE_MASK, periph_base) |                                \
+	 FIELD_PREP(SILABS_PINCTRL_HAVE_EN_MASK, 1) |                                              \
+	 FIELD_PREP(SILABS_PINCTRL_EN_BIT_MASK, en_bit) |                                          \
+	 FIELD_PREP(SILABS_PINCTRL_HAVE_ROUTE_MASK, 0))
+
+#define SILABS_ABUS(bus, parity, peripheral)                                                       \
+	(FIELD_PREP(SILABS_PINCTRL_ANALOG_MASK, 1) |                                               \
+	 FIELD_PREP(SILABS_PINCTRL_ABUS_BUS_MASK, bus) |                                           \
+	 FIELD_PREP(SILABS_PINCTRL_ABUS_PARITY_MASK, parity) |                                     \
+	 FIELD_PREP(SILABS_PINCTRL_ABUS_PERIPH_MASK, peripheral))
 
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_DBUS_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/silabs-pinctrl-siwx91x.h b/include/zephyr/dt-bindings/pinctrl/silabs-pinctrl-siwx91x.h
new file mode 100644
index 00000000000..371dbffbaf9
--- /dev/null
+++ b/include/zephyr/dt-bindings/pinctrl/silabs-pinctrl-siwx91x.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef INCLUDE_ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_SIWX91X_H_
+#define INCLUDE_ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_SIWX91X_H_
+
+#include <zephyr/dt-bindings/dt-util.h>
+
+#if !defined(FIELD_PREP)
+/* Upstream does not make these macros available to DeviceTree */
+#define LSB_GET(value)          ((value) & -(value))
+#define FIELD_GET(mask, value)  (((value) & (mask)) / LSB_GET(mask))
+#define FIELD_PREP(mask, value) (((value) * LSB_GET(mask)) & (mask))
+#endif
+
+#define SIWX91X_PINCTRL_PORT_MASK    0x0000000FUL
+#define SIWX91X_PINCTRL_PIN_MASK     0x000000F0UL
+#define SIWX91X_PINCTRL_ULPPIN_MASK  0x00000F00UL
+#define SIWX91X_PINCTRL_MODE_MASK    0x0003F000UL
+#define SIWX91X_PINCTRL_ULPMODE_MASK 0x00FC0000UL
+#define SIWX91X_PINCTRL_PAD_MASK     0xFF000000UL
+
+/* Declare an integer representing the pinctrl/gpio state of a signal on SiWx91x.
+ * @param mode          HP GPIO mode, 0xFF if HP GPIO mux isn't used
+ * @param ulpmode       ULP GPIO mode, 0xFF if ULP GPIO mux isn't used
+ * @param pad           HP pad number, 0xFF if HP pad isn't used, 0 if host pad
+ * @param port          GPIO port number (0-4)
+ * @param pin           HP GPIO pin number, value is unused if mode is 0xFF
+ * @param ulppin        ULP GPIO pin number, value is unused if ulpmode is 0xFF
+ */
+#define SIWX91X_GPIO(mode, ulpmode, pad, port, pin, ulppin)                                        \
+	(FIELD_PREP(SIWX91X_PINCTRL_PORT_MASK, port) | FIELD_PREP(SIWX91X_PINCTRL_PIN_MASK, pin) | \
+	 FIELD_PREP(SIWX91X_PINCTRL_ULPPIN_MASK, ulppin) |                                         \
+	 FIELD_PREP(SIWX91X_PINCTRL_MODE_MASK, mode) |                                             \
+	 FIELD_PREP(SIWX91X_PINCTRL_ULPMODE_MASK, ulpmode) |                                       \
+	 FIELD_PREP(SIWX91X_PINCTRL_PAD_MASK, pad))
+
+#endif /* INCLUDE_ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_PINCTRL_SIWX91X_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/silabs/siwx91x-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/silabs/siwx91x-pinctrl.h
new file mode 100644
index 00000000000..69dfa32f755
--- /dev/null
+++ b/include/zephyr/dt-bindings/pinctrl/silabs/siwx91x-pinctrl.h
@@ -0,0 +1,620 @@
+/*
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef INCLUDE_ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_SIWX91X_PINCTRL_H_
+#define INCLUDE_ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_SIWX91X_PINCTRL_H_
+
+#include <zephyr/dt-bindings/pinctrl/silabs-pinctrl-siwx91x.h>
+
+/* clang-format off */
+
+#define AGPIO_ULP0           SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0,  0)
+#define AGPIO_ULP1           SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0,  1)
+#define AGPIO_ULP2           SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0,  2)
+#define AGPIO_ULP4           SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0,  4)
+#define AGPIO_ULP5           SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0,  5)
+#define AGPIO_ULP6           SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0,  6)
+#define AGPIO_ULP7           SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0,  7)
+#define AGPIO_ULP8           SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0,  8)
+#define AGPIO_ULP9           SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0,  9)
+#define AGPIO_ULP10          SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 10)
+#define AGPIO_ULP11          SIWX91X_GPIO(0xFF, 7, 0xFF, 4, 0, 11)
+
+#define AUXULP_TRIG0_PA11    SIWX91X_GPIO(9,     5,    6, 0, 11,  5)
+#define AUXULP_TRIG0_PB14    SIWX91X_GPIO(11,    5,    0, 1, 14, 11)
+#define AUXULP_TRIG0_PD1     SIWX91X_GPIO(9,     5,   13, 3,  1, 11)
+#define AUXULP_TRIG0_ULP5    SIWX91X_GPIO(0xFF,  5, 0xFF, 4,  0,  5)
+#define AUXULP_TRIG0_ULP6    SIWX91X_GPIO(0xFF, 10, 0xFF, 4,  0,  6)
+#define AUXULP_TRIG0_ULP11   SIWX91X_GPIO(0xFF,  5, 0xFF, 4,  0, 11)
+#define AUXULP_TRIG1_ULP4    SIWX91X_GPIO(0xFF,  5, 0xFF, 4,  0,  4)
+#define AUXULP_TRIG1_ULP7    SIWX91X_GPIO(0xFF, 10, 0xFF, 4,  0,  7)
+
+#define CLK_I2SPLL_PB11      SIWX91X_GPIO(12, 0xFF,  0, 1, 11, 0)
+#define CLK_I2SPLL_PD0       SIWX91X_GPIO(10, 0xFF, 12, 3,  0, 0)
+#define CLK_I2SPLL_PD6       SIWX91X_GPIO(10, 0xFF, 18, 3,  6, 0)
+#define CLK_INTFPLL_PB10     SIWX91X_GPIO(12, 0xFF,  0, 1, 10, 0)
+#define CLK_INTFPLL_PC15     SIWX91X_GPIO(10, 0xFF, 11, 2, 15, 0)
+#define CLK_INTFPLL_PD5      SIWX91X_GPIO(10, 0xFF, 17, 3,  5, 0)
+#define CLK_MCUOUT_PA11      SIWX91X_GPIO(12, 0xFF,  6, 0, 11, 0)
+#define CLK_MEMSREF_PD2      SIWX91X_GPIO(10, 0xFF, 14, 3,  2, 0)
+#define CLK_MEMSREF_PD8      SIWX91X_GPIO(10, 0xFF, 20, 3,  8, 0)
+#define CLK_OUT_PA12         SIWX91X_GPIO(8,  0xFF,  7, 0, 12, 0)
+#define CLK_OUT_PA15         SIWX91X_GPIO(8,  0xFF,  8, 0, 15, 0)
+#define CLK_PLLTESTMODE_PD3  SIWX91X_GPIO(10, 0xFF, 15, 3,  3, 0)
+#define CLK_SOCPLL_PB9       SIWX91X_GPIO(12, 0xFF,  0, 1,  9, 0)
+#define CLK_SOCPLL_PC14      SIWX91X_GPIO(10, 0xFF, 10, 2, 14, 0)
+#define CLK_SOCPLL_PD4       SIWX91X_GPIO(10, 0xFF, 16, 3,  4, 0)
+#define CLK_XTALONIN_PB12    SIWX91X_GPIO(12, 0xFF,  0, 1, 12, 0)
+#define CLK_XTALONIN_PD9     SIWX91X_GPIO(10, 0xFF, 21, 3,  9, 0)
+
+#define COMP1_OUT_PA8        SIWX91X_GPIO(9,    5,    3, 0,  8, 2)
+#define COMP1_OUT_PB12       SIWX91X_GPIO(11,   5,    0, 1, 12, 9)
+#define COMP1_OUT_PC15       SIWX91X_GPIO(9,    5,   11, 2, 15, 9)
+#define COMP1_OUT_ULP2       SIWX91X_GPIO(0xFF, 5, 0xFF, 4,  0, 2)
+#define COMP1_OUT_ULP6       SIWX91X_GPIO(0xFF, 9, 0xFF, 4,  0, 6)
+#define COMP2_OUT_ULP7       SIWX91X_GPIO(0xFF, 9, 0xFF, 4,  0, 7)
+
+#define GSPI_CLK_PA8         SIWX91X_GPIO(4,  0xFF,  3, 0,  8, 0)
+#define GSPI_CLK_PB9         SIWX91X_GPIO(4,  0xFF,  0, 1,  9, 0)
+#define GSPI_CLK_PC14        SIWX91X_GPIO(4,  0xFF, 10, 2, 14, 0)
+#define GSPI_CLK_PD4         SIWX91X_GPIO(4,  0xFF, 16, 3,  4, 0)
+#define GSPI_CS0_PA9         SIWX91X_GPIO(4,  0xFF,  4, 0,  9, 0)
+#define GSPI_CS0_PB12        SIWX91X_GPIO(4,  0xFF,  0, 1, 12, 0)
+#define GSPI_CS0_PD1         SIWX91X_GPIO(4,  0xFF, 13, 3,  1, 0)
+#define GSPI_CS0_PD5         SIWX91X_GPIO(4,  0xFF, 17, 3,  5, 0)
+#define GSPI_CS1_PA10        SIWX91X_GPIO(4,  0xFF,  5, 0, 10, 0)
+#define GSPI_CS1_PB13        SIWX91X_GPIO(4,  0xFF,  0, 1, 13, 0)
+#define GSPI_CS1_PD2         SIWX91X_GPIO(4,  0xFF, 14, 3,  2, 0)
+#define GSPI_CS1_PD6         SIWX91X_GPIO(4,  0xFF, 18, 3,  6, 0)
+#define GSPI_CS2_PA15        SIWX91X_GPIO(4,  0xFF,  8, 0, 15, 0)
+#define GSPI_CS2_PB14        SIWX91X_GPIO(4,  0xFF,  0, 1, 14, 0)
+#define GSPI_CS2_PD3         SIWX91X_GPIO(4,  0xFF, 15, 3,  3, 0)
+#define GSPI_CS2_PD7         SIWX91X_GPIO(4,  0xFF, 19, 3,  7, 0)
+#define GSPI_MISO_PA11       SIWX91X_GPIO(4,  0xFF,  6, 0, 11, 0)
+#define GSPI_MISO_PB10       SIWX91X_GPIO(4,  0xFF,  0, 1, 10, 0)
+#define GSPI_MISO_PC15       SIWX91X_GPIO(4,  0xFF, 11, 2, 15, 0)
+#define GSPI_MISO_PD8        SIWX91X_GPIO(4,  0xFF, 20, 3,  8, 0)
+#define GSPI_MOSI_PA6        SIWX91X_GPIO(12, 0xFF,  1, 0,  6, 0)
+#define GSPI_MOSI_PA12       SIWX91X_GPIO(4,  0xFF,  7, 0, 12, 0)
+#define GSPI_MOSI_PB11       SIWX91X_GPIO(4,  0xFF,  0, 1, 11, 0)
+#define GSPI_MOSI_PD0        SIWX91X_GPIO(4,  0xFF, 12, 3,  0, 0)
+#define GSPI_MOSI_PD9        SIWX91X_GPIO(4,  0xFF, 21, 3,  9, 0)
+
+#define I2C0_SCL_PA7         SIWX91X_GPIO(4,  0xFF,  2, 0,  7,  0)
+#define I2C0_SCL_PC0         SIWX91X_GPIO(11, 0xFF,  9, 2,  0,  0)
+#define I2C0_SCL_ULP1        SIWX91X_GPIO(4,     6, 23, 4,  1,  1)
+#define I2C0_SCL_ULP2        SIWX91X_GPIO(4,     6, 24, 4,  2,  2)
+#define I2C0_SCL_ULP11       SIWX91X_GPIO(4,     6, 33, 4, 11, 11)
+#define I2C0_SDA_PA6         SIWX91X_GPIO(4,  0xFF,  1, 0,  6,  0)
+#define I2C0_SDA_PB15        SIWX91X_GPIO(11, 0xFF,  9, 1, 15,  0)
+#define I2C0_SDA_ULP0        SIWX91X_GPIO(4,     6, 22, 4,  0,  0)
+#define I2C0_SDA_ULP3        SIWX91X_GPIO(4,     6, 25, 4,  3,  3)
+#define I2C0_SDA_ULP10       SIWX91X_GPIO(4,     6, 32, 4, 10, 10)
+
+#define I2C1_SCL_PA6         SIWX91X_GPIO(5,  0xFF,  1, 0,  6, 0)
+#define I2C1_SCL_PB13        SIWX91X_GPIO(5,  0xFF,  0, 1, 13, 0)
+#define I2C1_SCL_PC1         SIWX91X_GPIO(11, 0xFF,  9, 2,  1, 0)
+#define I2C1_SCL_PD2         SIWX91X_GPIO(5,  0xFF, 14, 3,  2, 0)
+#define I2C1_SCL_PD6         SIWX91X_GPIO(5,  0xFF, 18, 3,  6, 0)
+#define I2C1_SCL_ULP0        SIWX91X_GPIO(5,     6, 22, 4,  0, 0)
+#define I2C1_SCL_ULP2        SIWX91X_GPIO(5,     6, 24, 4,  2, 2)
+#define I2C1_SCL_ULP6        SIWX91X_GPIO(5,     6, 28, 4,  6, 6)
+#define I2C1_SDA_PA7         SIWX91X_GPIO(5,  0xFF,  2, 0,  7, 0)
+#define I2C1_SDA_PB14        SIWX91X_GPIO(5,  0xFF,  0, 1, 14, 0)
+#define I2C1_SDA_PC2         SIWX91X_GPIO(11, 0xFF,  9, 2,  2, 0)
+#define I2C1_SDA_PD3         SIWX91X_GPIO(5,  0xFF, 15, 3,  3, 0)
+#define I2C1_SDA_PD7         SIWX91X_GPIO(5,  0xFF, 19, 3,  7, 0)
+#define I2C1_SDA_ULP1        SIWX91X_GPIO(5,     6, 23, 4,  1, 1)
+#define I2C1_SDA_ULP3        SIWX91X_GPIO(5,     6, 25, 4,  3, 3)
+#define I2C1_SDA_ULP7        SIWX91X_GPIO(5,     6, 29, 4,  7, 7)
+
+#define I2S0_CLK_PA8         SIWX91X_GPIO(7, 0xFF,  3, 0,  8, 0)
+#define I2S0_CLK_PB9         SIWX91X_GPIO(7, 0xFF,  0, 1,  9, 0)
+#define I2S0_CLK_PC14        SIWX91X_GPIO(7, 0xFF, 10, 2, 14, 0)
+#define I2S0_CLK_PD4         SIWX91X_GPIO(7, 0xFF, 16, 3,  4, 0)
+#define I2S0_DIN0_PA10       SIWX91X_GPIO(7, 0xFF,  5, 0, 10, 0)
+#define I2S0_DIN0_PB11       SIWX91X_GPIO(7, 0xFF,  0, 1, 11, 0)
+#define I2S0_DIN0_PD0        SIWX91X_GPIO(7, 0xFF, 12, 3,  0, 0)
+#define I2S0_DIN0_PD8        SIWX91X_GPIO(7, 0xFF, 20, 3,  8, 0)
+#define I2S0_DIN1_PA6        SIWX91X_GPIO(7, 0xFF,  1, 0,  6, 0)
+#define I2S0_DIN1_PB13       SIWX91X_GPIO(7, 0xFF,  0, 1, 13, 0)
+#define I2S0_DIN1_PD2        SIWX91X_GPIO(7, 0xFF, 14, 3,  2, 0)
+#define I2S0_DIN1_PD6        SIWX91X_GPIO(7, 0xFF, 18, 3,  6, 0)
+#define I2S0_DOUT0_PA11      SIWX91X_GPIO(7, 0xFF,  6, 0, 11, 0)
+#define I2S0_DOUT0_PB12      SIWX91X_GPIO(7, 0xFF,  0, 1, 12, 0)
+#define I2S0_DOUT0_PD1       SIWX91X_GPIO(7, 0xFF, 13, 3,  1, 0)
+#define I2S0_DOUT0_PD9       SIWX91X_GPIO(7, 0xFF, 21, 3,  9, 0)
+#define I2S0_DOUT1_PA7       SIWX91X_GPIO(7, 0xFF,  2, 0,  7, 0)
+#define I2S0_DOUT1_PB13      SIWX91X_GPIO(7, 0xFF,  0, 1, 14, 0)
+#define I2S0_DOUT1_PD3       SIWX91X_GPIO(7, 0xFF, 15, 3,  3, 0)
+#define I2S0_DOUT1_PD7       SIWX91X_GPIO(7, 0xFF, 19, 3,  7, 0)
+#define I2S0_WS_PA9          SIWX91X_GPIO(7, 0xFF,  4, 0,  9, 0)
+#define I2S0_WS_PB10         SIWX91X_GPIO(7, 0xFF,  0, 1, 10, 0)
+#define I2S0_WS_PC15         SIWX91X_GPIO(7, 0xFF, 11, 2, 15, 0)
+#define I2S0_WS_PD5          SIWX91X_GPIO(7, 0xFF, 17, 3,  5, 0)
+
+#define IR_INPUT_PA15        SIWX91X_GPIO(9,     1,    8, 0, 15,  7)
+#define IR_INPUT_PB10        SIWX91X_GPIO(11,    1,    0, 1, 10,  7)
+#define IR_INPUT_PB13        SIWX91X_GPIO(11,    4,    0, 1, 13, 10)
+#define IR_INPUT_PD0         SIWX91X_GPIO(9,     4,   12, 3,  0, 10)
+#define IR_INPUT_ULP4        SIWX91X_GPIO(0xFF, 10, 0xFF, 4,  0,  4)
+#define IR_INPUT_ULP7        SIWX91X_GPIO(0xFF,  1, 0xFF, 4,  0,  7)
+#define IR_INPUT_ULP10       SIWX91X_GPIO(0xFF,  4, 0xFF, 4,  0, 10)
+#define IR_OUTPUT_PA11       SIWX91X_GPIO(9,     1,    6, 0, 11,  5)
+#define IR_OUTPUT_ULP5       SIWX91X_GPIO(0xFF,  1, 0xFF, 4,  0,  5)
+
+#define PMU_TEST1_PA6        SIWX91X_GPIO(8,  0xFF,  1, 0,  6,  0)
+#define PMU_TEST1_PB13       SIWX91X_GPIO(8,  0xFF,  0, 1, 13,  0)
+#define PMU_TEST1_PB14       SIWX91X_GPIO(12, 0xFF,  0, 1, 14,  0)
+#define PMU_TEST1_ULP0       SIWX91X_GPIO(13,    6, 22, 4,  0,  0)
+#define PMU_TEST1_ULP2       SIWX91X_GPIO(10,    6, 24, 4,  2,  2)
+#define PMU_TEST1_ULP6       SIWX91X_GPIO(12,    6, 28, 4,  6,  6)
+#define PMU_TEST1_ULP10      SIWX91X_GPIO(10,    6, 32, 4, 10, 10)
+#define PMU_TEST2_PA7        SIWX91X_GPIO(8,  0xFF,  2, 0,  7,  0)
+#define PMU_TEST2_PB14       SIWX91X_GPIO(8,  0xFF,  0, 1, 14,  0)
+#define PMU_TEST2_ULP1       SIWX91X_GPIO(13,    6, 23, 4,  1,  1)
+#define PMU_TEST2_ULP3       SIWX91X_GPIO(10,    6, 25, 4,  3,  3)
+#define PMU_TEST2_ULP7       SIWX91X_GPIO(12,    6, 29, 4,  7,  7)
+#define PMU_TEST2_ULP11      SIWX91X_GPIO(10,    6, 33, 4, 11, 11)
+
+#define PSRAM_CLK_PC14       SIWX91X_GPIO(11, 0xFF, 10, 2, 14, 0)
+#define PSRAM_CLK_PD4        SIWX91X_GPIO(12, 0xFF, 16, 3,  4, 0)
+#define PSRAM_CSN0_PD1       SIWX91X_GPIO(11, 0xFF, 13, 3,  1, 0)
+#define PSRAM_CSN0_PD7       SIWX91X_GPIO(12, 0xFF, 19, 3,  7, 0)
+#define PSRAM_CSN1_PD5       SIWX91X_GPIO(11, 0xFF, 17, 3,  5, 0)
+#define PSRAM_D0_PC15        SIWX91X_GPIO(11, 0xFF, 11, 2, 15, 0)
+#define PSRAM_D0_PD5         SIWX91X_GPIO(12, 0xFF, 17, 3,  5, 0)
+#define PSRAM_D1_PD0         SIWX91X_GPIO(11, 0xFF, 12, 3,  0, 0)
+#define PSRAM_D1_PD6         SIWX91X_GPIO(12, 0xFF, 18, 3,  6, 0)
+#define PSRAM_D2_PD2         SIWX91X_GPIO(11, 0xFF, 14, 3,  2, 0)
+#define PSRAM_D2_PD8         SIWX91X_GPIO(12, 0xFF, 20, 3,  8, 0)
+#define PSRAM_D3_PD3         SIWX91X_GPIO(11, 0xFF, 15, 3,  3, 0)
+#define PSRAM_D3_PD9         SIWX91X_GPIO(12, 0xFF, 21, 3,  9, 0)
+#define PSRAM_D4_PD6         SIWX91X_GPIO(11, 0xFF, 18, 3,  6, 0)
+#define PSRAM_D5_PD7         SIWX91X_GPIO(11, 0xFF, 19, 3,  7, 0)
+#define PSRAM_D6_PD8         SIWX91X_GPIO(11, 0xFF, 20, 3,  8, 0)
+#define PSRAM_D7_PD9         SIWX91X_GPIO(11, 0xFF, 21, 3,  9, 0)
+
+#define PWM_0H_PA7           SIWX91X_GPIO(10, 0xFF,  2, 0,  7,  0)
+#define PWM_0H_ULP1          SIWX91X_GPIO(12,    6, 23, 4,  1,  1)
+#define PWM_0L_PA6           SIWX91X_GPIO(10, 0xFF,  1, 0,  6,  0)
+#define PWM_0L_ULP0          SIWX91X_GPIO(12,    6, 22, 4,  0,  0)
+#define PWM_1H_PA9           SIWX91X_GPIO(10, 0xFF,  4, 0,  9,  0)
+#define PWM_1H_ULP3          SIWX91X_GPIO(8,     6, 25, 4,  3,  3)
+#define PWM_1H_ULP5          SIWX91X_GPIO(12,    6, 27, 4,  5,  5)
+#define PWM_1L_PA8           SIWX91X_GPIO(10, 0xFF,  3, 0,  8,  0)
+#define PWM_1L_ULP2          SIWX91X_GPIO(8,     6, 24, 4,  2,  2)
+#define PWM_1L_ULP4          SIWX91X_GPIO(12,    6, 26, 4,  4,  4)
+#define PWM_2H_PA11          SIWX91X_GPIO(10, 0xFF,  6, 0, 11,  0)
+#define PWM_2H_ULP5          SIWX91X_GPIO(8,     6, 27, 4,  5,  5)
+#define PWM_2L_PA10          SIWX91X_GPIO(10, 0xFF,  5, 0, 10,  0)
+#define PWM_2L_ULP4          SIWX91X_GPIO(8,     6, 26, 4,  4,  4)
+#define PWM_3H_PA15          SIWX91X_GPIO(10, 0xFF,  8, 0, 15,  0)
+#define PWM_3H_ULP7          SIWX91X_GPIO(8,     6, 29, 4,  7,  7)
+#define PWM_3L_PA12          SIWX91X_GPIO(10, 0xFF,  7, 0, 12,  0)
+#define PWM_3L_ULP6          SIWX91X_GPIO(8,     6, 28, 4,  6,  6)
+#define PWM_EXTTRIG0_PB11    SIWX91X_GPIO(10, 0xFF,  0, 1, 11,  0)
+#define PWM_EXTTRIG0_PD3     SIWX91X_GPIO(8,  0xFF, 15, 3,  3,  0)
+#define PWM_EXTTRIG0_ULP6    SIWX91X_GPIO(10,    6, 28, 4,  6,  6)
+#define PWM_EXTTRIG0_ULP11   SIWX91X_GPIO(8,     6, 33, 4, 11, 11)
+#define PWM_EXTTRIG1_PB12    SIWX91X_GPIO(10, 0xFF,  0, 1, 12,  0)
+#define PWM_EXTTRIG1_PD6     SIWX91X_GPIO(8,  0xFF, 18, 3,  6,  0)
+#define PWM_EXTTRIG1_ULP7    SIWX91X_GPIO(10,    6, 29, 4,  7,  7)
+#define PWM_EXTTRIG2_PB13    SIWX91X_GPIO(10, 0xFF,  0, 1, 13,  0)
+#define PWM_EXTTRIG2_PD7     SIWX91X_GPIO(8,  0xFF, 19, 3,  7,  0)
+#define PWM_EXTTRIG2_ULP8    SIWX91X_GPIO(10,    6, 30, 4,  8,  8)
+#define PWM_EXTTRIG3_PB14    SIWX91X_GPIO(10, 0xFF,  0, 1, 14,  0)
+#define PWM_EXTTRIG3_PD2     SIWX91X_GPIO(8,  0xFF, 14, 3,  2,  0)
+#define PWM_EXTTRIG3_ULP9    SIWX91X_GPIO(10,    6, 31, 4,  9,  9)
+#define PWM_FAULTA_PB9       SIWX91X_GPIO(10, 0xFF,  0, 1,  9,  0)
+#define PWM_FAULTA_ULP4      SIWX91X_GPIO(10,    6, 26, 4,  4,  4)
+#define PWM_FAULTA_ULP9      SIWX91X_GPIO(8,     6, 31, 4,  9,  9)
+#define PWM_FAULTB_PB10      SIWX91X_GPIO(10, 0xFF,  0, 1, 10,  0)
+#define PWM_FAULTB_ULP5      SIWX91X_GPIO(10,    6, 27, 4,  5,  5)
+#define PWM_FAULTB_ULP10     SIWX91X_GPIO(8,     6, 32, 4, 10, 10)
+#define PWM_SLEEPEVENT_ULP8  SIWX91X_GPIO(8,     6, 30, 4,  8,  8)
+
+#define QEI_DIR_PA11         SIWX91X_GPIO(5,  0xFF,  6, 0, 11,  0)
+#define QEI_DIR_PB12         SIWX91X_GPIO(5,  0xFF,  0, 1, 12,  0)
+#define QEI_DIR_PC2          SIWX91X_GPIO(13, 0xFF,  9, 2,  2,  0)
+#define QEI_DIR_PD1          SIWX91X_GPIO(3,  0xFF, 13, 3,  1,  0)
+#define QEI_DIR_PD9          SIWX91X_GPIO(5,  0xFF, 21, 3,  9,  0)
+#define QEI_DIR_ULP3         SIWX91X_GPIO(3,     6, 25, 4,  3,  3)
+#define QEI_DIR_ULP7         SIWX91X_GPIO(3,     6, 29, 4,  7,  7)
+#define QEI_DIR_ULP11        SIWX91X_GPIO(3,     6, 33, 4, 11, 11)
+#define QEI_IDX_PA8          SIWX91X_GPIO(5,  0xFF,  3, 0,  8,  0)
+#define QEI_IDX_PB15         SIWX91X_GPIO(13, 0xFF,  9, 1, 15,  0)
+#define QEI_IDX_PB9          SIWX91X_GPIO(5,  0xFF,  0, 1,  9,  0)
+#define QEI_IDX_PC14         SIWX91X_GPIO(3,  0xFF, 10, 2, 14,  0)
+#define QEI_IDX_PD4          SIWX91X_GPIO(5,  0xFF, 16, 3,  4,  0)
+#define QEI_IDX_ULP0         SIWX91X_GPIO(3,     6, 22, 4,  0,  0)
+#define QEI_IDX_ULP4         SIWX91X_GPIO(3,     6, 26, 4,  4,  4)
+#define QEI_IDX_ULP8         SIWX91X_GPIO(3,     6, 30, 4,  8,  8)
+#define QEI_PHA_PA9          SIWX91X_GPIO(5,  0xFF,  4, 0,  9,  0)
+#define QEI_PHA_PB10         SIWX91X_GPIO(5,  0xFF,  0, 1, 10,  0)
+#define QEI_PHA_PC0          SIWX91X_GPIO(13, 0xFF,  9, 2,  0,  0)
+#define QEI_PHA_PC15         SIWX91X_GPIO(3,  0xFF, 11, 2, 15,  0)
+#define QEI_PHA_PD5          SIWX91X_GPIO(5,  0xFF, 17, 3,  5,  0)
+#define QEI_PHA_ULP1         SIWX91X_GPIO(3,     6, 23, 4,  1,  1)
+#define QEI_PHA_ULP5         SIWX91X_GPIO(3,     6, 27, 4,  5,  5)
+#define QEI_PHA_ULP9         SIWX91X_GPIO(3,     6, 31, 4,  9,  9)
+#define QEI_PHB_PA10         SIWX91X_GPIO(5,  0xFF,  5, 0, 10,  0)
+#define QEI_PHB_PB11         SIWX91X_GPIO(5,  0xFF,  0, 1, 11,  0)
+#define QEI_PHB_PC1          SIWX91X_GPIO(13, 0xFF,  9, 2,  1,  0)
+#define QEI_PHB_PD0          SIWX91X_GPIO(3,  0xFF, 12, 3,  0,  0)
+#define QEI_PHB_PD8          SIWX91X_GPIO(5,  0xFF, 20, 3,  8,  0)
+#define QEI_PHB_ULP2         SIWX91X_GPIO(3,     6, 24, 4,  2,  2)
+#define QEI_PHB_ULP6         SIWX91X_GPIO(3,     6, 28, 4,  6,  6)
+#define QEI_PHB_ULP10        SIWX91X_GPIO(3,     6, 32, 4, 10, 10)
+
+#define QSPI_CLK_PA8         SIWX91X_GPIO(11, 0xFF,  3, 0,  8, 0)
+#define QSPI_CLK_PC14        SIWX91X_GPIO(1,  0xFF, 10, 2, 14, 0)
+#define QSPI_CLK_PD4         SIWX91X_GPIO(9,  0xFF, 16, 3,  4, 0)
+#define QSPI_CSN0_PA7        SIWX91X_GPIO(11, 0xFF,  2, 0,  7, 0)
+#define QSPI_CSN0_PD1        SIWX91X_GPIO(1,  0xFF, 13, 3,  1, 0)
+#define QSPI_CSN0_PD7        SIWX91X_GPIO(9,  0xFF, 19, 3,  7, 0)
+#define QSPI_CSN1_PA7        SIWX91X_GPIO(12, 0xFF,  2, 0,  7, 0)
+#define QSPI_CSN1_PD5        SIWX91X_GPIO(1,  0xFF, 17, 3,  5, 0)
+#define QSPI_CSN9_PD1        SIWX91X_GPIO(10, 0xFF, 13, 3,  1, 0)
+#define QSPI_D0_PA6          SIWX91X_GPIO(11, 0xFF,  1, 0,  6, 0)
+#define QSPI_D0_PC15         SIWX91X_GPIO(1,  0xFF, 11, 2, 15, 0)
+#define QSPI_D0_PD5          SIWX91X_GPIO(9,  0xFF, 17, 3,  5, 0)
+#define QSPI_D1_PA9          SIWX91X_GPIO(11, 0xFF,  4, 0,  9, 0)
+#define QSPI_D1_PD0          SIWX91X_GPIO(1,  0xFF, 12, 3,  0, 0)
+#define QSPI_D1_PD6          SIWX91X_GPIO(9,  0xFF, 18, 3,  6, 0)
+#define QSPI_D2_PA10         SIWX91X_GPIO(11, 0xFF,  5, 0, 10, 0)
+#define QSPI_D2_PD2          SIWX91X_GPIO(1,  0xFF, 14, 3,  2, 0)
+#define QSPI_D2_PD8          SIWX91X_GPIO(9,  0xFF, 20, 3,  8, 0)
+#define QSPI_D3_PA11         SIWX91X_GPIO(11, 0xFF,  6, 0, 11, 0)
+#define QSPI_D3_PD3          SIWX91X_GPIO(1,  0xFF, 15, 3,  3, 0)
+#define QSPI_D3_PD9          SIWX91X_GPIO(9,  0xFF, 21, 3,  9, 0)
+#define QSPI_D4_PD6          SIWX91X_GPIO(1,  0xFF, 18, 3,  6, 0)
+#define QSPI_D5_PD7          SIWX91X_GPIO(1,  0xFF, 19, 3,  7, 0)
+#define QSPI_D6_PD8          SIWX91X_GPIO(1,  0xFF, 20, 3,  8, 0)
+#define QSPI_D7_PD9          SIWX91X_GPIO(1,  0xFF, 21, 3,  9, 0)
+
+#define SCT_IN0_PB9          SIWX91X_GPIO(9,  0xFF,  0, 1,  9,  0)
+#define SCT_IN0_ULP0         SIWX91X_GPIO(7,     6, 22, 4,  0,  0)
+#define SCT_IN0_ULP4         SIWX91X_GPIO(9,     6, 26, 4,  4,  4)
+#define SCT_IN1_PB10         SIWX91X_GPIO(9,  0xFF,  0, 1, 10,  0)
+#define SCT_IN1_ULP1         SIWX91X_GPIO(7,     6, 23, 4,  1,  1)
+#define SCT_IN1_ULP5         SIWX91X_GPIO(9,     6, 27, 4,  5,  5)
+#define SCT_IN2_PB11         SIWX91X_GPIO(9,  0xFF,  0, 1, 11,  0)
+#define SCT_IN2_ULP2         SIWX91X_GPIO(7,     6, 24, 4,  2,  2)
+#define SCT_IN2_ULP6         SIWX91X_GPIO(9,     6, 28, 4,  6,  6)
+#define SCT_IN3_PB12         SIWX91X_GPIO(9,  0xFF,  0, 1, 12,  0)
+#define SCT_IN3_ULP3         SIWX91X_GPIO(7,     6, 25, 4,  3,  3)
+#define SCT_IN3_ULP7         SIWX91X_GPIO(9,     6, 29, 4,  7,  7)
+#define SCT_OUT0_PB13        SIWX91X_GPIO(9,  0xFF,  0, 1, 13,  0)
+#define SCT_OUT0_ULP4        SIWX91X_GPIO(7,     6, 26, 4,  4,  4)
+#define SCT_OUT1_PB14        SIWX91X_GPIO(9,  0xFF,  0, 1, 14,  0)
+#define SCT_OUT1_ULP5        SIWX91X_GPIO(7,     6, 27, 4,  5,  5)
+#define SCT_OUT2_PA8         SIWX91X_GPIO(12, 0xFF,  3, 0,  8,  0)
+#define SCT_OUT2_ULP6        SIWX91X_GPIO(7,     6, 28, 4,  6,  6)
+#define SCT_OUT3_PA9         SIWX91X_GPIO(12, 0xFF,  4, 0,  9,  0)
+#define SCT_OUT3_ULP7        SIWX91X_GPIO(7,     6, 29, 4,  7,  7)
+#define SCT_OUT4_ULP4        SIWX91X_GPIO(13,    6, 26, 4,  4,  4)
+#define SCT_OUT4_ULP8        SIWX91X_GPIO(7,     6, 30, 4,  8,  8)
+#define SCT_OUT5_ULP5        SIWX91X_GPIO(13,    6, 27, 4,  5,  5)
+#define SCT_OUT5_ULP9        SIWX91X_GPIO(7,     6, 31, 4,  9,  9)
+#define SCT_OUT6_ULP6        SIWX91X_GPIO(13,    6, 28, 4,  6,  6)
+#define SCT_OUT6_ULP10       SIWX91X_GPIO(7,     6, 32, 4, 10, 10)
+#define SCT_OUT7_ULP7        SIWX91X_GPIO(13,    6, 29, 4,  7,  7)
+#define SCT_OUT7_ULP11       SIWX91X_GPIO(7,     6, 33, 4, 11, 11)
+
+#define SIO_0_PA6            SIWX91X_GPIO(1, 0xFF,  1, 0,  6,  0)
+#define SIO_0_PB9            SIWX91X_GPIO(1, 0xFF,  0, 1,  9,  0)
+#define SIO_0_ULP0           SIWX91X_GPIO(1,    6, 22, 4,  0,  0)
+#define SIO_0_ULP8           SIWX91X_GPIO(1,    6, 30, 4,  8,  8)
+#define SIO_1_PA7            SIWX91X_GPIO(1, 0xFF,  2, 0,  7,  0)
+#define SIO_1_PB10           SIWX91X_GPIO(1, 0xFF,  0, 1, 10,  0)
+#define SIO_1_ULP1           SIWX91X_GPIO(1,    6, 23, 4,  1,  1)
+#define SIO_1_ULP9           SIWX91X_GPIO(1,    6, 31, 4,  9,  9)
+#define SIO_2_PA8            SIWX91X_GPIO(1, 0xFF,  3, 0,  8,  0)
+#define SIO_2_PB11           SIWX91X_GPIO(1, 0xFF,  0, 1, 11,  0)
+#define SIO_2_ULP2           SIWX91X_GPIO(1,    6, 24, 4,  2,  2)
+#define SIO_2_ULP10          SIWX91X_GPIO(1,    6, 32, 4, 10, 10)
+#define SIO_3_PA9            SIWX91X_GPIO(1, 0xFF,  4, 0,  9,  0)
+#define SIO_3_PB12           SIWX91X_GPIO(1, 0xFF,  0, 1, 12,  0)
+#define SIO_3_ULP3           SIWX91X_GPIO(1,    6, 25, 4,  3,  3)
+#define SIO_3_ULP11          SIWX91X_GPIO(1,    6, 33, 4, 11, 11)
+#define SIO_4_PA10           SIWX91X_GPIO(1, 0xFF,  5, 0, 10,  0)
+#define SIO_4_PB13           SIWX91X_GPIO(1, 0xFF,  0, 1, 13,  0)
+#define SIO_4_ULP4           SIWX91X_GPIO(1,    6, 26, 4,  4,  4)
+#define SIO_5_PA11           SIWX91X_GPIO(1, 0xFF,  6, 0, 11,  0)
+#define SIO_5_PB14           SIWX91X_GPIO(1, 0xFF,  0, 1, 14,  0)
+#define SIO_5_ULP5           SIWX91X_GPIO(1,    6, 27, 4,  5,  5)
+#define SIO_6_ULP6           SIWX91X_GPIO(1,    6, 28, 4,  6,  6)
+#define SIO_7_PA15           SIWX91X_GPIO(1, 0xFF,  8, 0, 15,  0)
+#define SIO_7_ULP7           SIWX91X_GPIO(1,    6, 29, 4,  7,  7)
+
+#define SSI_CLK_PA8          SIWX91X_GPIO(3,  0xFF,  3, 0,  8, 0)
+#define SSI_CLK_PB9          SIWX91X_GPIO(3,  0xFF,  0, 1,  9, 0)
+#define SSI_CLK_PD4          SIWX91X_GPIO(3,  0xFF, 16, 3,  4, 0)
+#define SSI_CS0_PA9          SIWX91X_GPIO(3,  0xFF,  4, 0,  9, 0)
+#define SSI_CS0_PB12         SIWX91X_GPIO(3,  0xFF,  0, 1, 12, 0)
+#define SSI_CS0_PD5          SIWX91X_GPIO(3,  0xFF, 17, 3,  5, 0)
+#define SSI_CS1_PA10         SIWX91X_GPIO(3,  0xFF,  5, 0, 10, 0)
+#define SSI_CS2_PA15         SIWX91X_GPIO(3,  0xFF,  8, 0, 15, 0)
+#define SSI_CS2_PD2          SIWX91X_GPIO(3,  0xFF, 14, 3,  2, 0)
+#define SSI_CS3_PD3          SIWX91X_GPIO(3,  0xFF, 15, 3,  3, 0)
+#define SSI_DATA0_PA11       SIWX91X_GPIO(3,  0xFF,  6, 0, 11, 0)
+#define SSI_DATA0_PB10       SIWX91X_GPIO(3,  0xFF,  0, 1, 10, 0)
+#define SSI_DATA0_PD8        SIWX91X_GPIO(3,  0xFF, 20, 3,  8, 0)
+#define SSI_DATA1_PA10       SIWX91X_GPIO(12, 0xFF,  5, 0, 10, 0)
+#define SSI_DATA1_PA12       SIWX91X_GPIO(3,  0xFF,  7, 0, 12, 0)
+#define SSI_DATA1_PB11       SIWX91X_GPIO(3,  0xFF,  0, 1, 11, 0)
+#define SSI_DATA1_PD9        SIWX91X_GPIO(3,  0xFF, 21, 3,  9, 0)
+#define SSI_DATA2_PA6        SIWX91X_GPIO(3,  0xFF,  1, 0,  6, 0)
+#define SSI_DATA2_PB13       SIWX91X_GPIO(3,  0xFF,  0, 1, 13, 0)
+#define SSI_DATA2_PD6        SIWX91X_GPIO(3,  0xFF, 18, 3,  6, 0)
+#define SSI_DATA3_PA7        SIWX91X_GPIO(3,  0xFF,  2, 0,  7, 0)
+#define SSI_DATA3_PB14       SIWX91X_GPIO(3,  0xFF,  0, 1, 14, 0)
+#define SSI_DATA3_PD7        SIWX91X_GPIO(3,  0xFF, 19, 3,  7, 0)
+
+#define SSIS_CLK_PA8         SIWX91X_GPIO(8, 0xFF,  3, 0,  8, 0)
+#define SSIS_CLK_PB10        SIWX91X_GPIO(8, 0xFF,  0, 1, 10, 0)
+#define SSIS_CLK_PC15        SIWX91X_GPIO(8, 0xFF, 11, 2, 15, 0)
+#define SSIS_CLK_PD4         SIWX91X_GPIO(8, 0xFF, 16, 3,  4, 0)
+#define SSIS_CS_PA9          SIWX91X_GPIO(8, 0xFF,  4, 0,  9, 0)
+#define SSIS_CS_PB9          SIWX91X_GPIO(8, 0xFF,  0, 1,  9, 0)
+#define SSIS_CS_PC14         SIWX91X_GPIO(8, 0xFF, 10, 2, 14, 0)
+#define SSIS_CS_PD5          SIWX91X_GPIO(8, 0xFF, 17, 3,  5, 0)
+#define SSIS_MISO_PA11       SIWX91X_GPIO(8, 0xFF,  6, 0, 11, 0)
+#define SSIS_MISO_PB12       SIWX91X_GPIO(8, 0xFF,  0, 1, 12, 0)
+#define SSIS_MISO_PD1        SIWX91X_GPIO(8, 0xFF, 13, 3,  1, 0)
+#define SSIS_MISO_PD9        SIWX91X_GPIO(8, 0xFF, 21, 3,  9, 0)
+#define SSIS_MOSI_PA10       SIWX91X_GPIO(8, 0xFF,  5, 0, 10, 0)
+#define SSIS_MOSI_PB11       SIWX91X_GPIO(8, 0xFF,  0, 1, 11, 0)
+#define SSIS_MOSI_PD0        SIWX91X_GPIO(8, 0xFF, 12, 3,  0, 0)
+#define SSIS_MOSI_PD8        SIWX91X_GPIO(8, 0xFF, 20, 3,  8, 0)
+
+#define TIMER0_PA7           SIWX91X_GPIO(9,    5,    2, 0,  7, 1)
+#define TIMER0_PB11          SIWX91X_GPIO(11,   5,    0, 1, 11, 8)
+#define TIMER0_PC14          SIWX91X_GPIO(9,    5,   10, 2, 14, 8)
+#define TIMER0_ULP4          SIWX91X_GPIO(0xFF, 9, 0xFF, 4,  0, 4)
+#define TIMER0_ULP8          SIWX91X_GPIO(0xFF, 5, 0xFF, 4,  0, 8)
+
+#define TIMER1_PA15          SIWX91X_GPIO(9,    5,    8, 0, 15, 7)
+#define TIMER1_PB10          SIWX91X_GPIO(11,   5,    0, 1, 10, 7)
+#define TIMER1_ULP5          SIWX91X_GPIO(0xFF, 9, 0xFF, 4,  0, 5)
+#define TIMER1_ULP7          SIWX91X_GPIO(0xFF, 5, 0xFF, 4,  0, 7)
+
+#define TIMER2_ULP1          SIWX91X_GPIO(0xFF, 5, 0xFF, 4, 0, 1)
+
+#define TRACE_CLK_PA7        SIWX91X_GPIO(13, 0xFF,  2, 0,  7, 0)
+#define TRACE_CLK_PC15       SIWX91X_GPIO(6,  0xFF, 11, 2, 15, 0)
+#define TRACE_CLK_PD5        SIWX91X_GPIO(6,  0xFF, 17, 3,  5, 0)
+#define TRACE_CLKIN_PA6      SIWX91X_GPIO(13, 0xFF,  1, 0,  6, 0)
+#define TRACE_CLKIN_PA15     SIWX91X_GPIO(6,  0xFF,  8, 0, 15, 0)
+#define TRACE_CLKIN_PC14     SIWX91X_GPIO(6,  0xFF, 10, 2, 14, 0)
+#define TRACE_CLKIN_PD4      SIWX91X_GPIO(6,  0xFF, 16, 3,  4, 0)
+#define TRACE_D0_PA8         SIWX91X_GPIO(13, 0xFF,  3, 0,  8, 0)
+#define TRACE_D0_PD0         SIWX91X_GPIO(6,  0xFF, 12, 3,  0, 0)
+#define TRACE_D0_PD6         SIWX91X_GPIO(6,  0xFF, 18, 3,  6, 0)
+#define TRACE_D1_PA9         SIWX91X_GPIO(13, 0xFF,  4, 0,  9, 0)
+#define TRACE_D1_PD1         SIWX91X_GPIO(6,  0xFF, 13, 3,  1, 0)
+#define TRACE_D1_PD7         SIWX91X_GPIO(6,  0xFF, 19, 3,  7, 0)
+#define TRACE_D2_PA10        SIWX91X_GPIO(13, 0xFF,  5, 0, 10, 0)
+#define TRACE_D2_PD2         SIWX91X_GPIO(6,  0xFF, 14, 3,  2, 0)
+#define TRACE_D2_PD8         SIWX91X_GPIO(6,  0xFF, 20, 3,  8, 0)
+#define TRACE_D3_PA11        SIWX91X_GPIO(13, 0xFF,  6, 0, 11, 0)
+#define TRACE_D3_PD3         SIWX91X_GPIO(6,  0xFF, 15, 3,  3, 0)
+#define TRACE_D3_PD9         SIWX91X_GPIO(6,  0xFF, 21, 3,  9, 0)
+
+#define UART0_CLK_PA8        SIWX91X_GPIO(2,  0xFF,  3, 0,  8,  0)
+#define UART0_CLK_PB9        SIWX91X_GPIO(2,  0xFF,  0, 1,  9,  0)
+#define UART0_CLK_PD4        SIWX91X_GPIO(2,  0xFF, 16, 3,  4,  0)
+#define UART0_CLK_ULP0       SIWX91X_GPIO(2,     6, 22, 4,  0,  0)
+#define UART0_CTS_PA6        SIWX91X_GPIO(2,  0xFF,  1, 0,  6,  0)
+#define UART0_CTS_PB10       SIWX91X_GPIO(2,  0xFF,  0, 1, 10,  0)
+#define UART0_CTS_PD8        SIWX91X_GPIO(2,  0xFF, 20, 3,  8,  0)
+#define UART0_CTS_ULP6       SIWX91X_GPIO(2,     6, 28, 4,  6,  6)
+#define UART0_DCD_PA12       SIWX91X_GPIO(2,  0xFF,  7, 0, 12,  0)
+#define UART0_DCD_PB13       SIWX91X_GPIO(12, 0xFF,  0, 1, 13,  0)
+#define UART0_DSR_PA11       SIWX91X_GPIO(2,  0xFF,  6, 0, 11,  0)
+#define UART0_DSR_PD9        SIWX91X_GPIO(2,  0xFF, 21, 3,  9,  0)
+#define UART0_DTR_PA7        SIWX91X_GPIO(2,  0xFF,  2, 0,  7,  0)
+#define UART0_IRRX_PB9       SIWX91X_GPIO(13, 0xFF,  0, 1,  9,  0)
+#define UART0_IRRX_PC15      SIWX91X_GPIO(2,  0xFF, 11, 2, 15,  0)
+#define UART0_IRRX_ULP0      SIWX91X_GPIO(11,    6, 22, 4,  0,  0)
+#define UART0_IRRX_ULP7      SIWX91X_GPIO(2,     6, 29, 4,  7,  7)
+#define UART0_IRTX_PB10      SIWX91X_GPIO(13, 0xFF,  0, 1, 10,  0)
+#define UART0_IRTX_PD0       SIWX91X_GPIO(2,  0xFF, 12, 3,  0,  0)
+#define UART0_IRTX_ULP1      SIWX91X_GPIO(11,    6, 23, 4,  1,  1)
+#define UART0_IRTX_ULP8      SIWX91X_GPIO(2,     6, 30, 4,  8,  8)
+#define UART0_RI_PB11        SIWX91X_GPIO(2,  0xFF,  0, 1, 11,  0)
+#define UART0_RI_PC14        SIWX91X_GPIO(2,  0xFF, 10, 2, 14,  0)
+#define UART0_RI_ULP4        SIWX91X_GPIO(11,    6, 26, 4,  4,  4)
+#define UART0_RS485DE_PB13   SIWX91X_GPIO(13, 0xFF,  0, 1, 13,  0)
+#define UART0_RS485DE_PD3    SIWX91X_GPIO(2,  0xFF, 15, 3,  3,  0)
+#define UART0_RS485DE_ULP7   SIWX91X_GPIO(11,    6, 29, 4,  7,  7)
+#define UART0_RS485DE_ULP11  SIWX91X_GPIO(2,     6, 33, 4, 11, 11)
+#define UART0_RS485EN_PB11   SIWX91X_GPIO(13, 0xFF,  0, 1, 11,  0)
+#define UART0_RS485EN_PD1    SIWX91X_GPIO(2,  0xFF, 13, 3,  1,  0)
+#define UART0_RS485EN_ULP5   SIWX91X_GPIO(11,    6, 27, 4,  5,  5)
+#define UART0_RS485EN_ULP9   SIWX91X_GPIO(2,     6, 31, 4,  9,  9)
+#define UART0_RS485RE_PB12   SIWX91X_GPIO(13, 0xFF,  0, 1, 12,  0)
+#define UART0_RS485RE_PD2    SIWX91X_GPIO(2,  0xFF, 14, 3,  2,  0)
+#define UART0_RS485RE_ULP6   SIWX91X_GPIO(11,    6, 28, 4,  6,  6)
+#define UART0_RS485RE_ULP10  SIWX91X_GPIO(2,     6, 32, 4, 10, 10)
+#define UART0_RTS_PA9        SIWX91X_GPIO(2,  0xFF,  4, 0,  9,  0)
+#define UART0_RTS_PB12       SIWX91X_GPIO(2,  0xFF,  0, 1, 12,  0)
+#define UART0_RTS_PD5        SIWX91X_GPIO(2,  0xFF, 17, 3,  5,  0)
+#define UART0_RTS_ULP5       SIWX91X_GPIO(2,     6, 27, 4,  5,  5)
+#define UART0_RX_PA10        SIWX91X_GPIO(2,  0xFF,  5, 0, 10,  0)
+#define UART0_RX_PB13        SIWX91X_GPIO(2,  0xFF,  0, 1, 13,  0)
+#define UART0_RX_PD7         SIWX91X_GPIO(2,  0xFF, 19, 3,  7,  0)
+#define UART0_RX_ULP1        SIWX91X_GPIO(2,     6, 23, 4,  1,  1)
+#define UART0_RX_ULP6        SIWX91X_GPIO(4,     6, 28, 4,  6,  6)
+#define UART0_TX_PB14        SIWX91X_GPIO(2,  0xFF,  0, 1, 14,  0)
+#define UART0_TX_PD6         SIWX91X_GPIO(2,  0xFF, 18, 3,  6,  0)
+#define UART0_TX_ULP4        SIWX91X_GPIO(2,     6, 26, 4,  4,  4)
+#define UART0_TX_ULP7        SIWX91X_GPIO(4,     6, 29, 4,  7,  7)
+
+#define UART1_CTS_PA11       SIWX91X_GPIO(6,  0xFF,  6, 0, 11,  0)
+#define UART1_CTS_PC0        SIWX91X_GPIO(12, 0xFF,  9, 2,  0,  0)
+#define UART1_CTS_PD3        SIWX91X_GPIO(9,  0xFF, 15, 3,  3,  0)
+#define UART1_CTS_ULP1       SIWX91X_GPIO(9,     6, 23, 4,  1,  1)
+#define UART1_CTS_ULP7       SIWX91X_GPIO(6,     6, 29, 4,  7,  7)
+#define UART1_CTS_ULP9       SIWX91X_GPIO(9,     6, 31, 4,  9,  9)
+#define UART1_RS485DE_PA9    SIWX91X_GPIO(6,  0xFF,  4, 0,  9,  0)
+#define UART1_RS485DE_ULP2   SIWX91X_GPIO(6,     6, 24, 4,  2,  2)
+#define UART1_RS485DE_ULP11  SIWX91X_GPIO(6,     6, 33, 4, 11, 11)
+#define UART1_RS485EN_PA12   SIWX91X_GPIO(6,  0xFF,  7, 0, 12,  0)
+#define UART1_RS485EN_PB10   SIWX91X_GPIO(6,  0xFF,  0, 1, 10,  0)
+#define UART1_RS485EN_ULP0   SIWX91X_GPIO(6,     6, 22, 4,  0,  0)
+#define UART1_RS485RE_PA8    SIWX91X_GPIO(6,  0xFF,  3, 0,  8,  0)
+#define UART1_RS485RE_ULP1   SIWX91X_GPIO(6,     6, 23, 4,  1,  1)
+#define UART1_RS485RE_ULP10  SIWX91X_GPIO(6,     6, 32, 4, 10, 10)
+#define UART1_RTS_PA10       SIWX91X_GPIO(6,  0xFF,  5, 0, 10,  0)
+#define UART1_RTS_PB11       SIWX91X_GPIO(6,  0xFF,  0, 1, 11,  0)
+#define UART1_RTS_PB12       SIWX91X_GPIO(6,  0xFF,  0, 1, 12,  0)
+#define UART1_RTS_PB15       SIWX91X_GPIO(12, 0xFF,  9, 1, 15,  0)
+#define UART1_RTS_PD2        SIWX91X_GPIO(9,  0xFF, 14, 3,  2,  0)
+#define UART1_RTS_ULP0       SIWX91X_GPIO(9,     6, 22, 4,  0,  0)
+#define UART1_RTS_ULP6       SIWX91X_GPIO(6,     6, 28, 4,  6,  6)
+#define UART1_RTS_ULP8       SIWX91X_GPIO(9,     6, 30, 4,  8,  8)
+#define UART1_RX_PA6         SIWX91X_GPIO(6,  0xFF,  1, 0,  6,  0)
+#define UART1_RX_PB13        SIWX91X_GPIO(6,  0xFF,  0, 1, 13,  0)
+#define UART1_RX_PC1         SIWX91X_GPIO(12, 0xFF,  9, 2,  1,  0)
+#define UART1_RX_ULP2        SIWX91X_GPIO(9,     6, 24, 4,  1,  1)
+#define UART1_RX_ULP4        SIWX91X_GPIO(6,     6, 26, 4,  4,  4)
+#define UART1_RX_ULP8        SIWX91X_GPIO(6,     6, 30, 4,  8,  8)
+#define UART1_RX_ULP10       SIWX91X_GPIO(9,     6, 32, 4, 10, 10)
+#define UART1_TX_PA15        SIWX91X_GPIO(2,  0xFF,  8, 0, 15,  0)
+#define UART1_TX_PA7         SIWX91X_GPIO(6,  0xFF,  2, 0,  7,  0)
+#define UART1_TX_PB14        SIWX91X_GPIO(6,  0xFF,  0, 1, 14,  0)
+#define UART1_TX_PC2         SIWX91X_GPIO(12, 0xFF,  9, 2,  2,  0)
+#define UART1_TX_ULP3        SIWX91X_GPIO(9,     6, 25, 4,  1,  1)
+#define UART1_TX_ULP5        SIWX91X_GPIO(6,     6, 27, 4,  5,  5)
+#define UART1_TX_ULP9        SIWX91X_GPIO(6,     6, 31, 4,  9,  9)
+#define UART1_TX_ULP11       SIWX91X_GPIO(9,     6, 33, 4, 11, 11)
+
+#define ULPI2C_SCL_PA11      SIWX91X_GPIO(9,    4,    6, 0, 11,  5)
+#define ULPI2C_SCL_PA15      SIWX91X_GPIO(9,    4,    8, 0, 15,  7)
+#define ULPI2C_SCL_PA7       SIWX91X_GPIO(9,    4,    2, 0,  7,  1)
+#define ULPI2C_SCL_PB10      SIWX91X_GPIO(11,   4,    0, 1, 10,  7)
+#define ULPI2C_SCL_PB11      SIWX91X_GPIO(11,   4,    0, 1, 11,  8)
+#define ULPI2C_SCL_PC14      SIWX91X_GPIO(9,    4,   10, 2, 14,  8)
+#define ULPI2C_SCL_ULP1      SIWX91X_GPIO(0xFF, 4, 0xFF, 4,  0,  1)
+#define ULPI2C_SCL_ULP5      SIWX91X_GPIO(0xFF, 4, 0xFF, 4,  0,  5)
+#define ULPI2C_SCL_ULP7      SIWX91X_GPIO(0xFF, 4, 0xFF, 4,  0,  7)
+#define ULPI2C_SCL_ULP8      SIWX91X_GPIO(0xFF, 4, 0xFF, 4,  0,  8)
+#define ULPI2C_SDA_PA6       SIWX91X_GPIO(9,    4,    1, 0,  6,  0)
+#define ULPI2C_SDA_PA10      SIWX91X_GPIO(9,    4,    5, 0, 10,  4)
+#define ULPI2C_SDA_PA12      SIWX91X_GPIO(9,    4,    7, 0, 12,  6)
+#define ULPI2C_SDA_PB9       SIWX91X_GPIO(11,   4,    0, 1,  9,  6)
+#define ULPI2C_SDA_PB12      SIWX91X_GPIO(11,   4,    0, 1, 12,  9)
+#define ULPI2C_SDA_PB14      SIWX91X_GPIO(11,   4,    0, 1, 14, 11)
+#define ULPI2C_SDA_PC15      SIWX91X_GPIO(9,    4,   11, 2, 15,  9)
+#define ULPI2C_SDA_PD1       SIWX91X_GPIO(9,    4,   13, 3,  1, 11)
+#define ULPI2C_SDA_ULP0      SIWX91X_GPIO(0xFF, 4, 0xFF, 4,  0,  0)
+#define ULPI2C_SDA_ULP4      SIWX91X_GPIO(0xFF, 4, 0xFF, 4,  0,  4)
+#define ULPI2C_SDA_ULP6      SIWX91X_GPIO(0xFF, 4, 0xFF, 4,  0,  6)
+#define ULPI2C_SDA_ULP9      SIWX91X_GPIO(0xFF, 4, 0xFF, 4,  0,  9)
+#define ULPI2C_SDA_ULP11     SIWX91X_GPIO(0xFF, 4, 0xFF, 4,  0, 11)
+
+#define ULPI2S_CLK_PA15      SIWX91X_GPIO(9,    2,    8, 0, 15,  7)
+#define ULPI2S_CLK_PB10      SIWX91X_GPIO(11,   2,    0, 1, 10,  7)
+#define ULPI2S_CLK_PB11      SIWX91X_GPIO(11,   2,    0, 1, 11,  8)
+#define ULPI2S_CLK_PC14      SIWX91X_GPIO(9,    2,   10, 2, 14,  8)
+#define ULPI2S_CLK_ULP7      SIWX91X_GPIO(0xFF, 2, 0xFF, 4,  0,  7)
+#define ULPI2S_CLK_ULP8      SIWX91X_GPIO(0xFF, 2, 0xFF, 4,  0,  8)
+#define ULPI2S_DIN_PA12      SIWX91X_GPIO(9,    2,    7, 0, 12,  6)
+#define ULPI2S_DIN_PA6       SIWX91X_GPIO(9,    2,    1, 0,  6,  0)
+#define ULPI2S_DIN_PB9       SIWX91X_GPIO(11,   2,    0, 1,  9,  6)
+#define ULPI2S_DIN_PB12      SIWX91X_GPIO(11,   2,    0, 1, 12,  9)
+#define ULPI2S_DIN_PC15      SIWX91X_GPIO(9,    2,   11, 2, 15,  9)
+#define ULPI2S_DIN_ULP0      SIWX91X_GPIO(0xFF, 2, 0xFF, 4,  0,  0)
+#define ULPI2S_DIN_ULP6      SIWX91X_GPIO(0xFF, 2, 0xFF, 4,  0,  6)
+#define ULPI2S_DIN_ULP9      SIWX91X_GPIO(0xFF, 2, 0xFF, 4,  0,  9)
+#define ULPI2S_DOUT_PA7      SIWX91X_GPIO(9,    2,    2, 0,  7,  1)
+#define ULPI2S_DOUT_PA11     SIWX91X_GPIO(9,    2,    6, 0, 11,  5)
+#define ULPI2S_DOUT_PB14     SIWX91X_GPIO(11,   2,    0, 1, 14, 11)
+#define ULPI2S_DOUT_PD1      SIWX91X_GPIO(9,    2,   13, 3,  1, 11)
+#define ULPI2S_DOUT_ULP1     SIWX91X_GPIO(0xFF, 2, 0xFF, 4,  0,  1)
+#define ULPI2S_DOUT_ULP5     SIWX91X_GPIO(0xFF, 2, 0xFF, 4,  0,  5)
+#define ULPI2S_DOUT_ULP11    SIWX91X_GPIO(0xFF, 2, 0xFF, 4,  0, 11)
+#define ULPI2S_WS_PA8        SIWX91X_GPIO(9,    2,    3, 0,  8,  2)
+#define ULPI2S_WS_PA10       SIWX91X_GPIO(9,    2,    5, 0, 10,  4)
+#define ULPI2S_WS_PB13       SIWX91X_GPIO(11,   2,    0, 1, 13, 10)
+#define ULPI2S_WS_PD0        SIWX91X_GPIO(9,    2,   12, 3,  0, 10)
+#define ULPI2S_WS_ULP2       SIWX91X_GPIO(0xFF, 2, 0xFF, 4,  0,  2)
+#define ULPI2S_WS_ULP4       SIWX91X_GPIO(0xFF, 2, 0xFF, 4,  0,  4)
+#define ULPI2S_WS_ULP10      SIWX91X_GPIO(0xFF, 2, 0xFF, 4,  0, 10)
+
+#define ULPSSI_CLK_PA6       SIWX91X_GPIO(9,    1,    1, 0,  6,  0)
+#define ULPSSI_CLK_PB11      SIWX91X_GPIO(11,   1,    0, 1, 11,  8)
+#define ULPSSI_CLK_PC14      SIWX91X_GPIO(9,    1,   10, 2, 14,  8)
+#define ULPSSI_CLK_ULP0      SIWX91X_GPIO(0xFF, 1, 0xFF, 4,  0,  0)
+#define ULPSSI_CLK_ULP4      SIWX91X_GPIO(0xFF, 8, 0xFF, 4,  0,  4)
+#define ULPSSI_CLK_ULP8      SIWX91X_GPIO(0xFF, 1, 0xFF, 4,  0,  8)
+#define ULPSSI_CS0_PB13      SIWX91X_GPIO(11,   1,    0, 1, 13, 10)
+#define ULPSSI_CS0_PD0       SIWX91X_GPIO(9,    1,   12, 3,  0, 10)
+#define ULPSSI_CS0_ULP7      SIWX91X_GPIO(0xFF, 8, 0xFF, 4,  0,  7)
+#define ULPSSI_CS0_ULP10     SIWX91X_GPIO(0xFF, 1, 0xFF, 4,  0, 10)
+#define ULPSSI_CS1_PA10      SIWX91X_GPIO(9,    1,    5, 0, 10,  4)
+#define ULPSSI_CS1_ULP4      SIWX91X_GPIO(0xFF, 1, 0xFF, 4,  0,  4)
+#define ULPSSI_CS2_PA12      SIWX91X_GPIO(9,    1,    7, 0, 12,  6)
+#define ULPSSI_CS2_PB9       SIWX91X_GPIO(11,   1,    0, 1,  9,  6)
+#define ULPSSI_CS2_ULP6      SIWX91X_GPIO(0xFF, 1, 0xFF, 4,  0,  6)
+#define ULPSSI_DIN_PA8       SIWX91X_GPIO(9,    1,    3, 0,  8,  2)
+#define ULPSSI_DIN_PB12      SIWX91X_GPIO(11,   1,    0, 1, 12,  9)
+#define ULPSSI_DIN_PC15      SIWX91X_GPIO(9,    1,   11, 2, 15,  9)
+#define ULPSSI_DIN_ULP2      SIWX91X_GPIO(0xFF, 1, 0xFF, 4,  0,  2)
+#define ULPSSI_DIN_ULP6      SIWX91X_GPIO(0xFF, 8, 0xFF, 4,  0,  6)
+#define ULPSSI_DIN_ULP9      SIWX91X_GPIO(0xFF, 1, 0xFF, 4,  0,  9)
+#define ULPSSI_DOUT_PA7      SIWX91X_GPIO(9,    1,    2, 0,  7,  1)
+#define ULPSSI_DOUT_PB14     SIWX91X_GPIO(11,   1,    0, 1, 14, 11)
+#define ULPSSI_DOUT_PD1      SIWX91X_GPIO(9,    1,   13, 3,  1, 11)
+#define ULPSSI_DOUT_ULP1     SIWX91X_GPIO(0xFF, 1, 0xFF, 4,  0,  1)
+#define ULPSSI_DOUT_ULP5     SIWX91X_GPIO(0xFF, 8, 0xFF, 4,  0,  5)
+#define ULPSSI_DOUT_ULP11    SIWX91X_GPIO(0xFF, 1, 0xFF, 4,  0, 11)
+
+#define ULPUART_CTS_PA7      SIWX91X_GPIO(9,    3,    2, 0,  7,  1)
+#define ULPUART_CTS_PA11     SIWX91X_GPIO(9,    3,    6, 0, 11,  5)
+#define ULPUART_CTS_PB11     SIWX91X_GPIO(11,   3,    0, 1, 11,  8)
+#define ULPUART_CTS_PC14     SIWX91X_GPIO(9,    3,   10, 2, 14,  8)
+#define ULPUART_CTS_ULP1     SIWX91X_GPIO(0xFF, 3, 0xFF, 4,  0,  1)
+#define ULPUART_CTS_ULP5     SIWX91X_GPIO(0xFF, 3, 0xFF, 4,  0,  5)
+#define ULPUART_CTS_ULP8     SIWX91X_GPIO(0xFF, 3, 0xFF, 4,  0,  8)
+#define ULPUART_RTS_PA6      SIWX91X_GPIO(9,    3,    1, 0,  6,  0)
+#define ULPUART_RTS_PA10     SIWX91X_GPIO(9,    3,    5, 0, 10,  4)
+#define ULPUART_RTS_PB13     SIWX91X_GPIO(11,   3,    0, 1, 13, 10)
+#define ULPUART_RTS_PD0      SIWX91X_GPIO(9,    3,   12, 3,  0, 10)
+#define ULPUART_RTS_ULP0     SIWX91X_GPIO(0xFF, 3, 0xFF, 4,  0,  0)
+#define ULPUART_RTS_ULP4     SIWX91X_GPIO(0xFF, 3, 0xFF, 4,  0,  4)
+#define ULPUART_RTS_ULP10    SIWX91X_GPIO(0xFF, 3, 0xFF, 4,  0, 10)
+#define ULPUART_RX_PA8       SIWX91X_GPIO(9,    3,    3, 0,  8,  2)
+#define ULPUART_RX_PA12      SIWX91X_GPIO(9,    3,    7, 0, 12,  6)
+#define ULPUART_RX_PB9       SIWX91X_GPIO(11,   3,    0, 1,  9,  6)
+#define ULPUART_RX_PB12      SIWX91X_GPIO(11,   3,    0, 1, 12,  9)
+#define ULPUART_RX_PC15      SIWX91X_GPIO(9,    3,   11, 2, 15,  9)
+#define ULPUART_RX_ULP2      SIWX91X_GPIO(0xFF, 3, 0xFF, 4,  0,  2)
+#define ULPUART_RX_ULP6      SIWX91X_GPIO(0xFF, 3, 0xFF, 4,  0,  6)
+#define ULPUART_RX_ULP9      SIWX91X_GPIO(0xFF, 3, 0xFF, 4,  0,  9)
+#define ULPUART_TX_PA15      SIWX91X_GPIO(9,    3,    8, 0, 15,  7)
+#define ULPUART_TX_PB10      SIWX91X_GPIO(11,   3,    0, 1, 10,  7)
+#define ULPUART_TX_PB14      SIWX91X_GPIO(11,   3,    0, 1, 14, 11)
+#define ULPUART_TX_PD1       SIWX91X_GPIO(9,    3,   13, 3,  1, 11)
+#define ULPUART_TX_ULP7      SIWX91X_GPIO(0xFF, 3, 0xFF, 4,  0,  7)
+#define ULPUART_TX_ULP11     SIWX91X_GPIO(0xFF, 3, 0xFF, 4,  0, 11)
+
+#define UULP_GPIO4_ULP2      SIWX91X_GPIO(0xFF,  4, 0xFF, 4, 0, 2)
+#define UULP_TESTMODE0_ULP7  SIWX91X_GPIO(0xFF, 11, 0xFF, 4, 0, 7)
+#define UULP_TESTMODE0_ULP9  SIWX91X_GPIO(0xFF,  5, 0xFF, 4, 0, 9)
+
+/* clang-format on */
+
+/* The following definitions are duplicates of signals that are also
+ * available on the same pins using other GPIO modes.
+ * #define IR_OUTPUT_ULP5       SIWX91X_GPIO(0xFF, 10, 0xFF, 4, 0, 5)
+ * #define PMU_TEST2_PB14       SIWX91X_GPIO(13, 0xFF, 0, 1, 14, 0)
+ * #define PWM_1H_ULP1          SIWX91X_GPIO(8, 6, 23, 4, 1, 1)
+ * #define PWM_1L_ULP0          SIWX91X_GPIO(8, 6, 22, 4, 0, 0)
+ */
+
+#endif /* INCLUDE_ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_SIWX91X_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/silabs/xg21-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/silabs/xg21-pinctrl.h
index 4ab1c6ab486..6dbaafd2576 100644
--- a/include/zephyr/dt-bindings/pinctrl/silabs/xg21-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/silabs/xg21-pinctrl.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Silicon Laboratories Inc.
+ * Copyright (c) 2025 Silicon Laboratories Inc.
  * SPDX-License-Identifier: Apache-2.0
  *
  * Pin Control for Silicon Labs XG21 devices
@@ -107,6 +107,14 @@
 #define SILABS_DBUS_USART2_TX(port, pin)  SILABS_DBUS(port, pin, 107, 1, 4, 6)
 #define SILABS_DBUS_USART2_CTS(port, pin) SILABS_DBUS(port, pin, 107, 0, 0, 2)
 
+#define GPIO_SWCLKTCK_PA1   SILABS_FIXED_ROUTE(0x0, 0x1, 0, 0)
+#define GPIO_SWDIOTMS_PA2   SILABS_FIXED_ROUTE(0x0, 0x2, 0, 1)
+#define GPIO_TDO_PA3        SILABS_FIXED_ROUTE(0x0, 0x3, 0, 2)
+#define GPIO_TDI_PA4        SILABS_FIXED_ROUTE(0x0, 0x4, 0, 3)
+#define GPIO_SWV_PA3        SILABS_FIXED_ROUTE(0x0, 0x3, 1, 0)
+#define GPIO_TRACECLK_PA4   SILABS_FIXED_ROUTE(0x0, 0x4, 1, 1)
+#define GPIO_TRACEDATA0_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 1, 2)
+
 #define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0)
 #define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1)
 #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
@@ -1185,4 +1193,41 @@
 #define USART2_CTS_PD3 SILABS_DBUS_USART2_CTS(0x3, 0x3)
 #define USART2_CTS_PD4 SILABS_DBUS_USART2_CTS(0x3, 0x4)
 
+#define ABUS_AEVEN0_IADC0  SILABS_ABUS(0x0, 0x0, 0x1)
+#define ABUS_AEVEN0_ACMP0  SILABS_ABUS(0x0, 0x0, 0x2)
+#define ABUS_AEVEN0_ACMP1  SILABS_ABUS(0x0, 0x0, 0x3)
+#define ABUS_AEVEN1_IADC0  SILABS_ABUS(0x0, 0x1, 0x1)
+#define ABUS_AEVEN1_ACMP0  SILABS_ABUS(0x0, 0x1, 0x2)
+#define ABUS_AEVEN1_ACMP1  SILABS_ABUS(0x0, 0x1, 0x3)
+#define ABUS_AODD0_IADC0   SILABS_ABUS(0x0, 0x2, 0x1)
+#define ABUS_AODD0_ACMP0   SILABS_ABUS(0x0, 0x2, 0x2)
+#define ABUS_AODD0_ACMP1   SILABS_ABUS(0x0, 0x2, 0x3)
+#define ABUS_AODD1_IADC0   SILABS_ABUS(0x0, 0x3, 0x1)
+#define ABUS_AODD1_ACMP0   SILABS_ABUS(0x0, 0x3, 0x2)
+#define ABUS_AODD1_ACMP1   SILABS_ABUS(0x0, 0x3, 0x3)
+#define ABUS_BEVEN0_IADC0  SILABS_ABUS(0x1, 0x0, 0x1)
+#define ABUS_BEVEN0_ACMP0  SILABS_ABUS(0x1, 0x0, 0x2)
+#define ABUS_BEVEN0_ACMP1  SILABS_ABUS(0x1, 0x0, 0x3)
+#define ABUS_BEVEN1_IADC0  SILABS_ABUS(0x1, 0x1, 0x1)
+#define ABUS_BEVEN1_ACMP0  SILABS_ABUS(0x1, 0x1, 0x2)
+#define ABUS_BEVEN1_ACMP1  SILABS_ABUS(0x1, 0x1, 0x3)
+#define ABUS_BODD0_IADC0   SILABS_ABUS(0x1, 0x2, 0x1)
+#define ABUS_BODD0_ACMP0   SILABS_ABUS(0x1, 0x2, 0x2)
+#define ABUS_BODD0_ACMP1   SILABS_ABUS(0x1, 0x2, 0x3)
+#define ABUS_BODD1_IADC0   SILABS_ABUS(0x1, 0x3, 0x1)
+#define ABUS_BODD1_ACMP0   SILABS_ABUS(0x1, 0x3, 0x2)
+#define ABUS_BODD1_ACMP1   SILABS_ABUS(0x1, 0x3, 0x3)
+#define ABUS_CDEVEN0_IADC0 SILABS_ABUS(0x2, 0x0, 0x1)
+#define ABUS_CDEVEN0_ACMP0 SILABS_ABUS(0x2, 0x0, 0x2)
+#define ABUS_CDEVEN0_ACMP1 SILABS_ABUS(0x2, 0x0, 0x3)
+#define ABUS_CDEVEN1_IADC0 SILABS_ABUS(0x2, 0x1, 0x1)
+#define ABUS_CDEVEN1_ACMP0 SILABS_ABUS(0x2, 0x1, 0x2)
+#define ABUS_CDEVEN1_ACMP1 SILABS_ABUS(0x2, 0x1, 0x3)
+#define ABUS_CDODD0_IADC0  SILABS_ABUS(0x2, 0x2, 0x1)
+#define ABUS_CDODD0_ACMP0  SILABS_ABUS(0x2, 0x2, 0x2)
+#define ABUS_CDODD0_ACMP1  SILABS_ABUS(0x2, 0x2, 0x3)
+#define ABUS_CDODD1_IADC0  SILABS_ABUS(0x2, 0x3, 0x1)
+#define ABUS_CDODD1_ACMP0  SILABS_ABUS(0x2, 0x3, 0x2)
+#define ABUS_CDODD1_ACMP1  SILABS_ABUS(0x2, 0x3, 0x3)
+
 #endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG21_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/silabs/xg22-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/silabs/xg22-pinctrl.h
index d276d1f5989..e4629b1c6b2 100644
--- a/include/zephyr/dt-bindings/pinctrl/silabs/xg22-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/silabs/xg22-pinctrl.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Silicon Laboratories Inc.
+ * Copyright (c) 2025 Silicon Laboratories Inc.
  * SPDX-License-Identifier: Apache-2.0
  *
  * Pin Control for Silicon Labs XG22 devices
@@ -123,6 +123,14 @@
 #define SILABS_DBUS_USART1_TX(port, pin)  SILABS_DBUS(port, pin, 127, 1, 4, 6)
 #define SILABS_DBUS_USART1_CTS(port, pin) SILABS_DBUS(port, pin, 127, 0, 0, 2)
 
+#define GPIO_SWCLKTCK_PA1   SILABS_FIXED_ROUTE(0x0, 0x1, 0, 0)
+#define GPIO_SWDIOTMS_PA2   SILABS_FIXED_ROUTE(0x0, 0x2, 0, 1)
+#define GPIO_TDO_PA3        SILABS_FIXED_ROUTE(0x0, 0x3, 0, 2)
+#define GPIO_TDI_PA4        SILABS_FIXED_ROUTE(0x0, 0x4, 0, 3)
+#define GPIO_SWV_PA3        SILABS_FIXED_ROUTE(0x0, 0x3, 1, 0)
+#define GPIO_TRACECLK_PA4   SILABS_FIXED_ROUTE(0x0, 0x4, 1, 1)
+#define GPIO_TRACEDATA0_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 1, 2)
+
 #define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0)
 #define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
 #define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2)
@@ -1789,4 +1797,17 @@
 #define USART1_CTS_PB3 SILABS_DBUS_USART1_CTS(0x1, 0x3)
 #define USART1_CTS_PB4 SILABS_DBUS_USART1_CTS(0x1, 0x4)
 
+#define ABUS_AEVEN0_IADC0  SILABS_ABUS(0x0, 0x0, 0x1)
+#define ABUS_AEVEN1_IADC0  SILABS_ABUS(0x0, 0x1, 0x1)
+#define ABUS_AODD0_IADC0   SILABS_ABUS(0x0, 0x2, 0x1)
+#define ABUS_AODD1_IADC0   SILABS_ABUS(0x0, 0x3, 0x1)
+#define ABUS_BEVEN0_IADC0  SILABS_ABUS(0x1, 0x0, 0x1)
+#define ABUS_BEVEN1_IADC0  SILABS_ABUS(0x1, 0x1, 0x1)
+#define ABUS_BODD0_IADC0   SILABS_ABUS(0x1, 0x2, 0x1)
+#define ABUS_BODD1_IADC0   SILABS_ABUS(0x1, 0x3, 0x1)
+#define ABUS_CDEVEN0_IADC0 SILABS_ABUS(0x2, 0x0, 0x1)
+#define ABUS_CDEVEN1_IADC0 SILABS_ABUS(0x2, 0x1, 0x1)
+#define ABUS_CDODD0_IADC0  SILABS_ABUS(0x2, 0x2, 0x1)
+#define ABUS_CDODD1_IADC0  SILABS_ABUS(0x2, 0x3, 0x1)
+
 #endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG22_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/silabs/xg23-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/silabs/xg23-pinctrl.h
index fb097656624..d1ec5a99b59 100644
--- a/include/zephyr/dt-bindings/pinctrl/silabs/xg23-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/silabs/xg23-pinctrl.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Silicon Laboratories Inc.
+ * Copyright (c) 2025 Silicon Laboratories Inc.
  * SPDX-License-Identifier: Apache-2.0
  *
  * Pin Control for Silicon Labs XG23 devices
@@ -169,6 +169,17 @@
 #define SILABS_DBUS_USART0_TX(port, pin)  SILABS_DBUS(port, pin, 214, 1, 4, 6)
 #define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 214, 0, 0, 2)
 
+#define GPIO_SWCLKTCK_PA1   SILABS_FIXED_ROUTE(0x0, 0x1, 0, 0)
+#define GPIO_SWDIOTMS_PA2   SILABS_FIXED_ROUTE(0x0, 0x2, 0, 1)
+#define GPIO_TDO_PA3        SILABS_FIXED_ROUTE(0x0, 0x3, 0, 2)
+#define GPIO_TDI_PA4        SILABS_FIXED_ROUTE(0x0, 0x4, 0, 3)
+#define GPIO_SWV_PA3        SILABS_FIXED_ROUTE(0x0, 0x3, 1, 0)
+#define GPIO_TRACECLK_PA4   SILABS_FIXED_ROUTE(0x0, 0x4, 1, 1)
+#define GPIO_TRACEDATA0_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 1, 2)
+#define GPIO_TRACEDATA1_PA5 SILABS_FIXED_ROUTE(0x0, 0x5, 1, 3)
+#define GPIO_TRACEDATA2_PA6 SILABS_FIXED_ROUTE(0x0, 0x6, 1, 4)
+#define GPIO_TRACEDATA3_PA7 SILABS_FIXED_ROUTE(0x0, 0x7, 1, 5)
+
 #define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0)
 #define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1)
 #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
@@ -3201,4 +3212,53 @@
 #define USART0_CTS_PD4 SILABS_DBUS_USART0_CTS(0x3, 0x4)
 #define USART0_CTS_PD5 SILABS_DBUS_USART0_CTS(0x3, 0x5)
 
+#define ABUS_AEVEN0_IADC0     SILABS_ABUS(0x0, 0x0, 0x1)
+#define ABUS_AEVEN0_ACMP0     SILABS_ABUS(0x0, 0x0, 0x2)
+#define ABUS_AEVEN0_ACMP1     SILABS_ABUS(0x0, 0x0, 0x3)
+#define ABUS_AEVEN0_VDAC0CH0  SILABS_ABUS(0x0, 0x0, 0x4)
+#define ABUS_AEVEN1_IADC0     SILABS_ABUS(0x0, 0x1, 0x1)
+#define ABUS_AEVEN1_ACMP0     SILABS_ABUS(0x0, 0x1, 0x2)
+#define ABUS_AEVEN1_ACMP1     SILABS_ABUS(0x0, 0x1, 0x3)
+#define ABUS_AEVEN1_VDAC0CH1  SILABS_ABUS(0x0, 0x1, 0x4)
+#define ABUS_AODD0_IADC0      SILABS_ABUS(0x0, 0x2, 0x1)
+#define ABUS_AODD0_ACMP0      SILABS_ABUS(0x0, 0x2, 0x2)
+#define ABUS_AODD0_ACMP1      SILABS_ABUS(0x0, 0x2, 0x3)
+#define ABUS_AODD0_VDAC0CH0   SILABS_ABUS(0x0, 0x2, 0x4)
+#define ABUS_AODD1_IADC0      SILABS_ABUS(0x0, 0x3, 0x1)
+#define ABUS_AODD1_ACMP0      SILABS_ABUS(0x0, 0x3, 0x2)
+#define ABUS_AODD1_ACMP1      SILABS_ABUS(0x0, 0x3, 0x3)
+#define ABUS_AODD1_VDAC0CH1   SILABS_ABUS(0x0, 0x3, 0x4)
+#define ABUS_BEVEN0_IADC0     SILABS_ABUS(0x1, 0x0, 0x1)
+#define ABUS_BEVEN0_ACMP0     SILABS_ABUS(0x1, 0x0, 0x2)
+#define ABUS_BEVEN0_ACMP1     SILABS_ABUS(0x1, 0x0, 0x3)
+#define ABUS_BEVEN0_VDAC0CH0  SILABS_ABUS(0x1, 0x0, 0x4)
+#define ABUS_BEVEN1_IADC0     SILABS_ABUS(0x1, 0x1, 0x1)
+#define ABUS_BEVEN1_ACMP0     SILABS_ABUS(0x1, 0x1, 0x2)
+#define ABUS_BEVEN1_ACMP1     SILABS_ABUS(0x1, 0x1, 0x3)
+#define ABUS_BEVEN1_VDAC0CH1  SILABS_ABUS(0x1, 0x1, 0x4)
+#define ABUS_BODD0_IADC0      SILABS_ABUS(0x1, 0x2, 0x1)
+#define ABUS_BODD0_ACMP0      SILABS_ABUS(0x1, 0x2, 0x2)
+#define ABUS_BODD0_ACMP1      SILABS_ABUS(0x1, 0x2, 0x3)
+#define ABUS_BODD0_VDAC0CH0   SILABS_ABUS(0x1, 0x2, 0x4)
+#define ABUS_BODD1_IADC0      SILABS_ABUS(0x1, 0x3, 0x1)
+#define ABUS_BODD1_ACMP0      SILABS_ABUS(0x1, 0x3, 0x2)
+#define ABUS_BODD1_ACMP1      SILABS_ABUS(0x1, 0x3, 0x3)
+#define ABUS_BODD1_VDAC0CH1   SILABS_ABUS(0x1, 0x3, 0x4)
+#define ABUS_CDEVEN0_IADC0    SILABS_ABUS(0x2, 0x0, 0x1)
+#define ABUS_CDEVEN0_ACMP0    SILABS_ABUS(0x2, 0x0, 0x2)
+#define ABUS_CDEVEN0_ACMP1    SILABS_ABUS(0x2, 0x0, 0x3)
+#define ABUS_CDEVEN0_VDAC0CH0 SILABS_ABUS(0x2, 0x0, 0x4)
+#define ABUS_CDEVEN1_IADC0    SILABS_ABUS(0x2, 0x1, 0x1)
+#define ABUS_CDEVEN1_ACMP0    SILABS_ABUS(0x2, 0x1, 0x2)
+#define ABUS_CDEVEN1_ACMP1    SILABS_ABUS(0x2, 0x1, 0x3)
+#define ABUS_CDEVEN1_VDAC0CH1 SILABS_ABUS(0x2, 0x1, 0x4)
+#define ABUS_CDODD0_IADC0     SILABS_ABUS(0x2, 0x2, 0x1)
+#define ABUS_CDODD0_ACMP0     SILABS_ABUS(0x2, 0x2, 0x2)
+#define ABUS_CDODD0_ACMP1     SILABS_ABUS(0x2, 0x2, 0x3)
+#define ABUS_CDODD0_VDAC0CH0  SILABS_ABUS(0x2, 0x2, 0x4)
+#define ABUS_CDODD1_IADC0     SILABS_ABUS(0x2, 0x3, 0x1)
+#define ABUS_CDODD1_ACMP0     SILABS_ABUS(0x2, 0x3, 0x2)
+#define ABUS_CDODD1_ACMP1     SILABS_ABUS(0x2, 0x3, 0x3)
+#define ABUS_CDODD1_VDAC0CH1  SILABS_ABUS(0x2, 0x3, 0x4)
+
 #endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG23_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/silabs/xg24-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/silabs/xg24-pinctrl.h
index 3bcbd132891..85eb32c8a91 100644
--- a/include/zephyr/dt-bindings/pinctrl/silabs/xg24-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/silabs/xg24-pinctrl.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Silicon Laboratories Inc.
+ * Copyright (c) 2025 Silicon Laboratories Inc.
  * SPDX-License-Identifier: Apache-2.0
  *
  * Pin Control for Silicon Labs XG24 devices
@@ -152,6 +152,17 @@
 #define SILABS_DBUS_USART0_TX(port, pin)  SILABS_DBUS(port, pin, 184, 1, 4, 6)
 #define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 184, 0, 0, 2)
 
+#define GPIO_SWCLKTCK_PA1   SILABS_FIXED_ROUTE(0x0, 0x1, 0, 0)
+#define GPIO_SWDIOTMS_PA2   SILABS_FIXED_ROUTE(0x0, 0x2, 0, 1)
+#define GPIO_TDO_PA3        SILABS_FIXED_ROUTE(0x0, 0x3, 0, 2)
+#define GPIO_TDI_PA4        SILABS_FIXED_ROUTE(0x0, 0x4, 0, 3)
+#define GPIO_SWV_PA3        SILABS_FIXED_ROUTE(0x0, 0x3, 1, 0)
+#define GPIO_TRACECLK_PA4   SILABS_FIXED_ROUTE(0x0, 0x4, 1, 1)
+#define GPIO_TRACEDATA0_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 1, 2)
+#define GPIO_TRACEDATA1_PA5 SILABS_FIXED_ROUTE(0x0, 0x5, 1, 3)
+#define GPIO_TRACEDATA2_PA6 SILABS_FIXED_ROUTE(0x0, 0x6, 1, 4)
+#define GPIO_TRACEDATA3_PA7 SILABS_FIXED_ROUTE(0x0, 0x7, 1, 5)
+
 #define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0)
 #define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1)
 #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
@@ -2700,4 +2711,65 @@
 #define USART0_CTS_PD4 SILABS_DBUS_USART0_CTS(0x3, 0x4)
 #define USART0_CTS_PD5 SILABS_DBUS_USART0_CTS(0x3, 0x5)
 
+#define ABUS_AEVEN0_IADC0     SILABS_ABUS(0x0, 0x0, 0x1)
+#define ABUS_AEVEN0_ACMP0     SILABS_ABUS(0x0, 0x0, 0x2)
+#define ABUS_AEVEN0_ACMP1     SILABS_ABUS(0x0, 0x0, 0x3)
+#define ABUS_AEVEN0_VDAC0CH0  SILABS_ABUS(0x0, 0x0, 0x4)
+#define ABUS_AEVEN0_VDAC1CH0  SILABS_ABUS(0x0, 0x0, 0x5)
+#define ABUS_AEVEN1_IADC0     SILABS_ABUS(0x0, 0x1, 0x1)
+#define ABUS_AEVEN1_ACMP0     SILABS_ABUS(0x0, 0x1, 0x2)
+#define ABUS_AEVEN1_ACMP1     SILABS_ABUS(0x0, 0x1, 0x3)
+#define ABUS_AEVEN1_VDAC0CH1  SILABS_ABUS(0x0, 0x1, 0x4)
+#define ABUS_AEVEN1_VDAC1CH1  SILABS_ABUS(0x0, 0x1, 0x5)
+#define ABUS_AODD0_IADC0      SILABS_ABUS(0x0, 0x2, 0x1)
+#define ABUS_AODD0_ACMP0      SILABS_ABUS(0x0, 0x2, 0x2)
+#define ABUS_AODD0_ACMP1      SILABS_ABUS(0x0, 0x2, 0x3)
+#define ABUS_AODD0_VDAC0CH0   SILABS_ABUS(0x0, 0x2, 0x4)
+#define ABUS_AODD0_VDAC1CH0   SILABS_ABUS(0x0, 0x2, 0x5)
+#define ABUS_AODD1_IADC0      SILABS_ABUS(0x0, 0x3, 0x1)
+#define ABUS_AODD1_ACMP0      SILABS_ABUS(0x0, 0x3, 0x2)
+#define ABUS_AODD1_ACMP1      SILABS_ABUS(0x0, 0x3, 0x3)
+#define ABUS_AODD1_VDAC0CH1   SILABS_ABUS(0x0, 0x3, 0x4)
+#define ABUS_AODD1_VDAC1CH1   SILABS_ABUS(0x0, 0x3, 0x5)
+#define ABUS_BEVEN0_IADC0     SILABS_ABUS(0x1, 0x0, 0x1)
+#define ABUS_BEVEN0_ACMP0     SILABS_ABUS(0x1, 0x0, 0x2)
+#define ABUS_BEVEN0_ACMP1     SILABS_ABUS(0x1, 0x0, 0x3)
+#define ABUS_BEVEN0_VDAC0CH0  SILABS_ABUS(0x1, 0x0, 0x4)
+#define ABUS_BEVEN0_VDAC1CH0  SILABS_ABUS(0x1, 0x0, 0x5)
+#define ABUS_BEVEN1_IADC0     SILABS_ABUS(0x1, 0x1, 0x1)
+#define ABUS_BEVEN1_ACMP0     SILABS_ABUS(0x1, 0x1, 0x2)
+#define ABUS_BEVEN1_ACMP1     SILABS_ABUS(0x1, 0x1, 0x3)
+#define ABUS_BEVEN1_VDAC0CH1  SILABS_ABUS(0x1, 0x1, 0x4)
+#define ABUS_BEVEN1_VDAC1CH1  SILABS_ABUS(0x1, 0x1, 0x5)
+#define ABUS_BODD0_IADC0      SILABS_ABUS(0x1, 0x2, 0x1)
+#define ABUS_BODD0_ACMP0      SILABS_ABUS(0x1, 0x2, 0x2)
+#define ABUS_BODD0_ACMP1      SILABS_ABUS(0x1, 0x2, 0x3)
+#define ABUS_BODD0_VDAC0CH0   SILABS_ABUS(0x1, 0x2, 0x4)
+#define ABUS_BODD0_VDAC1CH0   SILABS_ABUS(0x1, 0x2, 0x5)
+#define ABUS_BODD1_IADC0      SILABS_ABUS(0x1, 0x3, 0x1)
+#define ABUS_BODD1_ACMP0      SILABS_ABUS(0x1, 0x3, 0x2)
+#define ABUS_BODD1_ACMP1      SILABS_ABUS(0x1, 0x3, 0x3)
+#define ABUS_BODD1_VDAC0CH1   SILABS_ABUS(0x1, 0x3, 0x4)
+#define ABUS_BODD1_VDAC1CH1   SILABS_ABUS(0x1, 0x3, 0x5)
+#define ABUS_CDEVEN0_IADC0    SILABS_ABUS(0x2, 0x0, 0x1)
+#define ABUS_CDEVEN0_ACMP0    SILABS_ABUS(0x2, 0x0, 0x2)
+#define ABUS_CDEVEN0_ACMP1    SILABS_ABUS(0x2, 0x0, 0x3)
+#define ABUS_CDEVEN0_VDAC0CH0 SILABS_ABUS(0x2, 0x0, 0x4)
+#define ABUS_CDEVEN0_VDAC1CH0 SILABS_ABUS(0x2, 0x0, 0x5)
+#define ABUS_CDEVEN1_IADC0    SILABS_ABUS(0x2, 0x1, 0x1)
+#define ABUS_CDEVEN1_ACMP0    SILABS_ABUS(0x2, 0x1, 0x2)
+#define ABUS_CDEVEN1_ACMP1    SILABS_ABUS(0x2, 0x1, 0x3)
+#define ABUS_CDEVEN1_VDAC0CH1 SILABS_ABUS(0x2, 0x1, 0x4)
+#define ABUS_CDEVEN1_VDAC1CH1 SILABS_ABUS(0x2, 0x1, 0x5)
+#define ABUS_CDODD0_IADC0     SILABS_ABUS(0x2, 0x2, 0x1)
+#define ABUS_CDODD0_ACMP0     SILABS_ABUS(0x2, 0x2, 0x2)
+#define ABUS_CDODD0_ACMP1     SILABS_ABUS(0x2, 0x2, 0x3)
+#define ABUS_CDODD0_VDAC0CH0  SILABS_ABUS(0x2, 0x2, 0x4)
+#define ABUS_CDODD0_VDAC1CH0  SILABS_ABUS(0x2, 0x2, 0x5)
+#define ABUS_CDODD1_IADC0     SILABS_ABUS(0x2, 0x3, 0x1)
+#define ABUS_CDODD1_ACMP0     SILABS_ABUS(0x2, 0x3, 0x2)
+#define ABUS_CDODD1_ACMP1     SILABS_ABUS(0x2, 0x3, 0x3)
+#define ABUS_CDODD1_VDAC0CH1  SILABS_ABUS(0x2, 0x3, 0x4)
+#define ABUS_CDODD1_VDAC1CH1  SILABS_ABUS(0x2, 0x3, 0x5)
+
 #endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG24_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/silabs/xg27-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/silabs/xg27-pinctrl.h
index a111ce6cc8b..098313cadcf 100644
--- a/include/zephyr/dt-bindings/pinctrl/silabs/xg27-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/silabs/xg27-pinctrl.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Silicon Laboratories Inc.
+ * Copyright (c) 2025 Silicon Laboratories Inc.
  * SPDX-License-Identifier: Apache-2.0
  *
  * Pin Control for Silicon Labs XG27 devices
@@ -127,6 +127,17 @@
 #define SILABS_DBUS_USART1_TX(port, pin)  SILABS_DBUS(port, pin, 133, 1, 4, 6)
 #define SILABS_DBUS_USART1_CTS(port, pin) SILABS_DBUS(port, pin, 133, 0, 0, 2)
 
+#define GPIO_SWCLKTCK_PA1   SILABS_FIXED_ROUTE(0x0, 0x1, 0, 0)
+#define GPIO_SWDIOTMS_PA2   SILABS_FIXED_ROUTE(0x0, 0x2, 0, 1)
+#define GPIO_TDO_PA3        SILABS_FIXED_ROUTE(0x0, 0x3, 0, 2)
+#define GPIO_TDI_PA4        SILABS_FIXED_ROUTE(0x0, 0x4, 0, 3)
+#define GPIO_SWV_PA3        SILABS_FIXED_ROUTE(0x0, 0x3, 1, 0)
+#define GPIO_TRACECLK_PA4   SILABS_FIXED_ROUTE(0x0, 0x4, 1, 1)
+#define GPIO_TRACEDATA0_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 1, 2)
+#define GPIO_TRACEDATA1_PA5 SILABS_FIXED_ROUTE(0x0, 0x5, 1, 3)
+#define GPIO_TRACEDATA2_PA6 SILABS_FIXED_ROUTE(0x0, 0x6, 1, 4)
+#define GPIO_TRACEDATA3_PA7 SILABS_FIXED_ROUTE(0x0, 0x7, 1, 5)
+
 #define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0)
 #define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1)
 #define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
@@ -1872,4 +1883,30 @@
 #define USART1_CTS_PB3 SILABS_DBUS_USART1_CTS(0x1, 0x3)
 #define USART1_CTS_PB4 SILABS_DBUS_USART1_CTS(0x1, 0x4)
 
+#define ABUS_AEVEN0_IADC0  SILABS_ABUS(0x0, 0x0, 0x1)
+#define ABUS_AEVEN0_ACMP0  SILABS_ABUS(0x0, 0x0, 0x2)
+#define ABUS_AEVEN1_IADC0  SILABS_ABUS(0x0, 0x1, 0x1)
+#define ABUS_AEVEN1_ACMP0  SILABS_ABUS(0x0, 0x1, 0x2)
+#define ABUS_AODD0_IADC0   SILABS_ABUS(0x0, 0x2, 0x1)
+#define ABUS_AODD0_ACMP0   SILABS_ABUS(0x0, 0x2, 0x2)
+#define ABUS_AODD1_IADC0   SILABS_ABUS(0x0, 0x3, 0x1)
+#define ABUS_AODD1_ACMP0   SILABS_ABUS(0x0, 0x3, 0x2)
+#define ABUS_BEVEN0_IADC0  SILABS_ABUS(0x1, 0x0, 0x1)
+#define ABUS_BEVEN0_ACMP0  SILABS_ABUS(0x1, 0x0, 0x2)
+#define ABUS_BEVEN1_IADC0  SILABS_ABUS(0x1, 0x1, 0x1)
+#define ABUS_BEVEN1_ACMP0  SILABS_ABUS(0x1, 0x1, 0x2)
+#define ABUS_BODD0_IADC0   SILABS_ABUS(0x1, 0x2, 0x1)
+#define ABUS_BODD0_ACMP0   SILABS_ABUS(0x1, 0x2, 0x2)
+#define ABUS_BODD1_IADC0   SILABS_ABUS(0x1, 0x3, 0x1)
+#define ABUS_BODD1_ACMP0   SILABS_ABUS(0x1, 0x3, 0x2)
+#define ABUS_CDEVEN0_IADC0 SILABS_ABUS(0x2, 0x0, 0x1)
+#define ABUS_CDEVEN0_ACMP0 SILABS_ABUS(0x2, 0x0, 0x2)
+#define ABUS_CDEVEN1_IADC0 SILABS_ABUS(0x2, 0x1, 0x1)
+#define ABUS_CDEVEN1_ACMP0 SILABS_ABUS(0x2, 0x1, 0x2)
+#define ABUS_CDODD0_IADC0  SILABS_ABUS(0x2, 0x2, 0x1)
+#define ABUS_CDODD0_ACMP0  SILABS_ABUS(0x2, 0x2, 0x2)
+#define ABUS_CDODD0_PMON   SILABS_ABUS(0x2, 0x2, 0xc)
+#define ABUS_CDODD1_IADC0  SILABS_ABUS(0x2, 0x3, 0x1)
+#define ABUS_CDODD1_ACMP0  SILABS_ABUS(0x2, 0x3, 0x2)
+
 #endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG27_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/silabs/xg29-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/silabs/xg29-pinctrl.h
new file mode 100644
index 00000000000..d8a478a7b67
--- /dev/null
+++ b/include/zephyr/dt-bindings/pinctrl/silabs/xg29-pinctrl.h
@@ -0,0 +1,2075 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Pin Control for Silicon Labs XG29 devices
+ *
+ * This file was generated by the script gen_pinctrl.py in the hal_silabs module.
+ * Do not manually edit.
+ */
+
+#ifndef ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG29_PINCTRL_H_
+#define ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG29_PINCTRL_H_
+
+#include <dt-bindings/pinctrl/silabs-pinctrl-dbus.h>
+
+#define SILABS_DBUS_ACMP0_ACMPOUT(port, pin) SILABS_DBUS(port, pin, 4, 1, 0, 1)
+
+#define SILABS_DBUS_CMU_CLKOUT0(port, pin) SILABS_DBUS(port, pin, 7, 1, 0, 2)
+#define SILABS_DBUS_CMU_CLKOUT1(port, pin) SILABS_DBUS(port, pin, 7, 1, 1, 3)
+#define SILABS_DBUS_CMU_CLKOUT2(port, pin) SILABS_DBUS(port, pin, 7, 1, 2, 4)
+#define SILABS_DBUS_CMU_CLKIN0(port, pin)  SILABS_DBUS(port, pin, 7, 0, 0, 1)
+
+#define SILABS_DBUS_EUSART0_CS(port, pin)   SILABS_DBUS(port, pin, 19, 1, 0, 1)
+#define SILABS_DBUS_EUSART0_RTS(port, pin)  SILABS_DBUS(port, pin, 19, 1, 1, 3)
+#define SILABS_DBUS_EUSART0_RX(port, pin)   SILABS_DBUS(port, pin, 19, 1, 2, 4)
+#define SILABS_DBUS_EUSART0_SCLK(port, pin) SILABS_DBUS(port, pin, 19, 1, 3, 5)
+#define SILABS_DBUS_EUSART0_TX(port, pin)   SILABS_DBUS(port, pin, 19, 1, 4, 6)
+#define SILABS_DBUS_EUSART0_CTS(port, pin)  SILABS_DBUS(port, pin, 19, 0, 0, 2)
+
+#define SILABS_DBUS_EUSART1_CS(port, pin)   SILABS_DBUS(port, pin, 27, 1, 0, 1)
+#define SILABS_DBUS_EUSART1_RTS(port, pin)  SILABS_DBUS(port, pin, 27, 1, 1, 3)
+#define SILABS_DBUS_EUSART1_RX(port, pin)   SILABS_DBUS(port, pin, 27, 1, 2, 4)
+#define SILABS_DBUS_EUSART1_SCLK(port, pin) SILABS_DBUS(port, pin, 27, 1, 3, 5)
+#define SILABS_DBUS_EUSART1_TX(port, pin)   SILABS_DBUS(port, pin, 27, 1, 4, 6)
+#define SILABS_DBUS_EUSART1_CTS(port, pin)  SILABS_DBUS(port, pin, 27, 0, 0, 2)
+
+#define SILABS_DBUS_PTI_DCLK(port, pin)   SILABS_DBUS(port, pin, 35, 1, 0, 1)
+#define SILABS_DBUS_PTI_DFRAME(port, pin) SILABS_DBUS(port, pin, 35, 1, 1, 2)
+#define SILABS_DBUS_PTI_DOUT(port, pin)   SILABS_DBUS(port, pin, 35, 1, 2, 3)
+
+#define SILABS_DBUS_I2C0_SCL(port, pin) SILABS_DBUS(port, pin, 40, 1, 0, 1)
+#define SILABS_DBUS_I2C0_SDA(port, pin) SILABS_DBUS(port, pin, 40, 1, 1, 2)
+
+#define SILABS_DBUS_I2C1_SCL(port, pin) SILABS_DBUS(port, pin, 44, 1, 0, 1)
+#define SILABS_DBUS_I2C1_SDA(port, pin) SILABS_DBUS(port, pin, 44, 1, 1, 2)
+
+#define SILABS_DBUS_LETIMER0_OUT0(port, pin) SILABS_DBUS(port, pin, 48, 1, 0, 1)
+#define SILABS_DBUS_LETIMER0_OUT1(port, pin) SILABS_DBUS(port, pin, 48, 1, 1, 2)
+
+#define SILABS_DBUS_MODEM_ANT0(port, pin)        SILABS_DBUS(port, pin, 52, 1, 0, 1)
+#define SILABS_DBUS_MODEM_ANT1(port, pin)        SILABS_DBUS(port, pin, 52, 1, 1, 2)
+#define SILABS_DBUS_MODEM_ANTROLLOVER(port, pin) SILABS_DBUS(port, pin, 52, 1, 2, 3)
+#define SILABS_DBUS_MODEM_ANTRR0(port, pin)      SILABS_DBUS(port, pin, 52, 1, 3, 4)
+#define SILABS_DBUS_MODEM_ANTRR1(port, pin)      SILABS_DBUS(port, pin, 52, 1, 4, 5)
+#define SILABS_DBUS_MODEM_ANTRR2(port, pin)      SILABS_DBUS(port, pin, 52, 1, 5, 6)
+#define SILABS_DBUS_MODEM_ANTRR3(port, pin)      SILABS_DBUS(port, pin, 52, 1, 6, 7)
+#define SILABS_DBUS_MODEM_ANTRR4(port, pin)      SILABS_DBUS(port, pin, 52, 1, 7, 8)
+#define SILABS_DBUS_MODEM_ANTRR5(port, pin)      SILABS_DBUS(port, pin, 52, 1, 8, 9)
+#define SILABS_DBUS_MODEM_ANTSWEN(port, pin)     SILABS_DBUS(port, pin, 52, 1, 9, 10)
+#define SILABS_DBUS_MODEM_ANTSWUS(port, pin)     SILABS_DBUS(port, pin, 52, 1, 10, 11)
+#define SILABS_DBUS_MODEM_ANTTRIG(port, pin)     SILABS_DBUS(port, pin, 52, 1, 11, 12)
+#define SILABS_DBUS_MODEM_ANTTRIGSTOP(port, pin) SILABS_DBUS(port, pin, 52, 1, 12, 13)
+#define SILABS_DBUS_MODEM_DCLK(port, pin)        SILABS_DBUS(port, pin, 52, 1, 13, 14)
+#define SILABS_DBUS_MODEM_DOUT(port, pin)        SILABS_DBUS(port, pin, 52, 1, 14, 16)
+#define SILABS_DBUS_MODEM_DIN(port, pin)         SILABS_DBUS(port, pin, 52, 0, 0, 15)
+
+#define SILABS_DBUS_PDM_CLK(port, pin)  SILABS_DBUS(port, pin, 70, 1, 0, 1)
+#define SILABS_DBUS_PDM_DAT0(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 2)
+#define SILABS_DBUS_PDM_DAT1(port, pin) SILABS_DBUS(port, pin, 70, 0, 0, 3)
+
+#define SILABS_DBUS_PRS0_ASYNCH0(port, pin)  SILABS_DBUS(port, pin, 75, 1, 0, 1)
+#define SILABS_DBUS_PRS0_ASYNCH1(port, pin)  SILABS_DBUS(port, pin, 75, 1, 1, 2)
+#define SILABS_DBUS_PRS0_ASYNCH2(port, pin)  SILABS_DBUS(port, pin, 75, 1, 2, 3)
+#define SILABS_DBUS_PRS0_ASYNCH3(port, pin)  SILABS_DBUS(port, pin, 75, 1, 3, 4)
+#define SILABS_DBUS_PRS0_ASYNCH4(port, pin)  SILABS_DBUS(port, pin, 75, 1, 4, 5)
+#define SILABS_DBUS_PRS0_ASYNCH5(port, pin)  SILABS_DBUS(port, pin, 75, 1, 5, 6)
+#define SILABS_DBUS_PRS0_ASYNCH6(port, pin)  SILABS_DBUS(port, pin, 75, 1, 6, 7)
+#define SILABS_DBUS_PRS0_ASYNCH7(port, pin)  SILABS_DBUS(port, pin, 75, 1, 7, 8)
+#define SILABS_DBUS_PRS0_ASYNCH8(port, pin)  SILABS_DBUS(port, pin, 75, 1, 8, 9)
+#define SILABS_DBUS_PRS0_ASYNCH9(port, pin)  SILABS_DBUS(port, pin, 75, 1, 9, 10)
+#define SILABS_DBUS_PRS0_ASYNCH10(port, pin) SILABS_DBUS(port, pin, 75, 1, 10, 11)
+#define SILABS_DBUS_PRS0_ASYNCH11(port, pin) SILABS_DBUS(port, pin, 75, 1, 11, 12)
+#define SILABS_DBUS_PRS0_SYNCH0(port, pin)   SILABS_DBUS(port, pin, 75, 1, 12, 13)
+#define SILABS_DBUS_PRS0_SYNCH1(port, pin)   SILABS_DBUS(port, pin, 75, 1, 13, 14)
+#define SILABS_DBUS_PRS0_SYNCH2(port, pin)   SILABS_DBUS(port, pin, 75, 1, 14, 15)
+#define SILABS_DBUS_PRS0_SYNCH3(port, pin)   SILABS_DBUS(port, pin, 75, 1, 15, 16)
+
+#define SILABS_DBUS_TIMER0_CC0(port, pin)   SILABS_DBUS(port, pin, 93, 1, 0, 1)
+#define SILABS_DBUS_TIMER0_CC1(port, pin)   SILABS_DBUS(port, pin, 93, 1, 1, 2)
+#define SILABS_DBUS_TIMER0_CC2(port, pin)   SILABS_DBUS(port, pin, 93, 1, 2, 3)
+#define SILABS_DBUS_TIMER0_CDTI0(port, pin) SILABS_DBUS(port, pin, 93, 1, 3, 4)
+#define SILABS_DBUS_TIMER0_CDTI1(port, pin) SILABS_DBUS(port, pin, 93, 1, 4, 5)
+#define SILABS_DBUS_TIMER0_CDTI2(port, pin) SILABS_DBUS(port, pin, 93, 1, 5, 6)
+
+#define SILABS_DBUS_TIMER1_CC0(port, pin)   SILABS_DBUS(port, pin, 101, 1, 0, 1)
+#define SILABS_DBUS_TIMER1_CC1(port, pin)   SILABS_DBUS(port, pin, 101, 1, 1, 2)
+#define SILABS_DBUS_TIMER1_CC2(port, pin)   SILABS_DBUS(port, pin, 101, 1, 2, 3)
+#define SILABS_DBUS_TIMER1_CDTI0(port, pin) SILABS_DBUS(port, pin, 101, 1, 3, 4)
+#define SILABS_DBUS_TIMER1_CDTI1(port, pin) SILABS_DBUS(port, pin, 101, 1, 4, 5)
+#define SILABS_DBUS_TIMER1_CDTI2(port, pin) SILABS_DBUS(port, pin, 101, 1, 5, 6)
+
+#define SILABS_DBUS_TIMER2_CC0(port, pin)   SILABS_DBUS(port, pin, 109, 1, 0, 1)
+#define SILABS_DBUS_TIMER2_CC1(port, pin)   SILABS_DBUS(port, pin, 109, 1, 1, 2)
+#define SILABS_DBUS_TIMER2_CC2(port, pin)   SILABS_DBUS(port, pin, 109, 1, 2, 3)
+#define SILABS_DBUS_TIMER2_CDTI0(port, pin) SILABS_DBUS(port, pin, 109, 1, 3, 4)
+#define SILABS_DBUS_TIMER2_CDTI1(port, pin) SILABS_DBUS(port, pin, 109, 1, 4, 5)
+#define SILABS_DBUS_TIMER2_CDTI2(port, pin) SILABS_DBUS(port, pin, 109, 1, 5, 6)
+
+#define SILABS_DBUS_TIMER3_CC0(port, pin)   SILABS_DBUS(port, pin, 117, 1, 0, 1)
+#define SILABS_DBUS_TIMER3_CC1(port, pin)   SILABS_DBUS(port, pin, 117, 1, 1, 2)
+#define SILABS_DBUS_TIMER3_CC2(port, pin)   SILABS_DBUS(port, pin, 117, 1, 2, 3)
+#define SILABS_DBUS_TIMER3_CDTI0(port, pin) SILABS_DBUS(port, pin, 117, 1, 3, 4)
+#define SILABS_DBUS_TIMER3_CDTI1(port, pin) SILABS_DBUS(port, pin, 117, 1, 4, 5)
+#define SILABS_DBUS_TIMER3_CDTI2(port, pin) SILABS_DBUS(port, pin, 117, 1, 5, 6)
+
+#define SILABS_DBUS_TIMER4_CC0(port, pin)   SILABS_DBUS(port, pin, 125, 1, 0, 1)
+#define SILABS_DBUS_TIMER4_CC1(port, pin)   SILABS_DBUS(port, pin, 125, 1, 1, 2)
+#define SILABS_DBUS_TIMER4_CC2(port, pin)   SILABS_DBUS(port, pin, 125, 1, 2, 3)
+#define SILABS_DBUS_TIMER4_CDTI0(port, pin) SILABS_DBUS(port, pin, 125, 1, 3, 4)
+#define SILABS_DBUS_TIMER4_CDTI1(port, pin) SILABS_DBUS(port, pin, 125, 1, 4, 5)
+#define SILABS_DBUS_TIMER4_CDTI2(port, pin) SILABS_DBUS(port, pin, 125, 1, 5, 6)
+
+#define SILABS_DBUS_USART0_CS(port, pin)  SILABS_DBUS(port, pin, 133, 1, 0, 1)
+#define SILABS_DBUS_USART0_RTS(port, pin) SILABS_DBUS(port, pin, 133, 1, 1, 3)
+#define SILABS_DBUS_USART0_RX(port, pin)  SILABS_DBUS(port, pin, 133, 1, 2, 4)
+#define SILABS_DBUS_USART0_CLK(port, pin) SILABS_DBUS(port, pin, 133, 1, 3, 5)
+#define SILABS_DBUS_USART0_TX(port, pin)  SILABS_DBUS(port, pin, 133, 1, 4, 6)
+#define SILABS_DBUS_USART0_CTS(port, pin) SILABS_DBUS(port, pin, 133, 0, 0, 2)
+
+#define SILABS_DBUS_USART1_CS(port, pin)  SILABS_DBUS(port, pin, 141, 1, 0, 1)
+#define SILABS_DBUS_USART1_RTS(port, pin) SILABS_DBUS(port, pin, 141, 1, 1, 3)
+#define SILABS_DBUS_USART1_RX(port, pin)  SILABS_DBUS(port, pin, 141, 1, 2, 4)
+#define SILABS_DBUS_USART1_CLK(port, pin) SILABS_DBUS(port, pin, 141, 1, 3, 5)
+#define SILABS_DBUS_USART1_TX(port, pin)  SILABS_DBUS(port, pin, 141, 1, 4, 6)
+#define SILABS_DBUS_USART1_CTS(port, pin) SILABS_DBUS(port, pin, 141, 0, 0, 2)
+
+#define GPIO_SWCLKTCK_PA1   SILABS_FIXED_ROUTE(0x0, 0x1, 0, 0)
+#define GPIO_SWDIOTMS_PA2   SILABS_FIXED_ROUTE(0x0, 0x2, 0, 1)
+#define GPIO_TDO_PA3        SILABS_FIXED_ROUTE(0x0, 0x3, 0, 2)
+#define GPIO_TDI_PA4        SILABS_FIXED_ROUTE(0x0, 0x4, 0, 3)
+#define GPIO_SWV_PA3        SILABS_FIXED_ROUTE(0x0, 0x3, 1, 0)
+#define GPIO_TRACECLK_PA4   SILABS_FIXED_ROUTE(0x0, 0x4, 1, 1)
+#define GPIO_TRACEDATA0_PA3 SILABS_FIXED_ROUTE(0x0, 0x3, 1, 2)
+#define GPIO_TRACEDATA1_PA5 SILABS_FIXED_ROUTE(0x0, 0x5, 1, 3)
+#define GPIO_TRACEDATA2_PA6 SILABS_FIXED_ROUTE(0x0, 0x6, 1, 4)
+#define GPIO_TRACEDATA3_PA7 SILABS_FIXED_ROUTE(0x0, 0x7, 1, 5)
+
+#define ACMP0_ACMPOUT_PA0 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x0)
+#define ACMP0_ACMPOUT_PA1 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x1)
+#define ACMP0_ACMPOUT_PA2 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x2)
+#define ACMP0_ACMPOUT_PA3 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x3)
+#define ACMP0_ACMPOUT_PA4 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x4)
+#define ACMP0_ACMPOUT_PA5 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x5)
+#define ACMP0_ACMPOUT_PA6 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x6)
+#define ACMP0_ACMPOUT_PA7 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x7)
+#define ACMP0_ACMPOUT_PA8 SILABS_DBUS_ACMP0_ACMPOUT(0x0, 0x8)
+#define ACMP0_ACMPOUT_PB0 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x0)
+#define ACMP0_ACMPOUT_PB1 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x1)
+#define ACMP0_ACMPOUT_PB2 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x2)
+#define ACMP0_ACMPOUT_PB3 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x3)
+#define ACMP0_ACMPOUT_PB4 SILABS_DBUS_ACMP0_ACMPOUT(0x1, 0x4)
+#define ACMP0_ACMPOUT_PC0 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x0)
+#define ACMP0_ACMPOUT_PC1 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x1)
+#define ACMP0_ACMPOUT_PC2 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x2)
+#define ACMP0_ACMPOUT_PC3 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x3)
+#define ACMP0_ACMPOUT_PC4 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x4)
+#define ACMP0_ACMPOUT_PC5 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x5)
+#define ACMP0_ACMPOUT_PC6 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x6)
+#define ACMP0_ACMPOUT_PC7 SILABS_DBUS_ACMP0_ACMPOUT(0x2, 0x7)
+#define ACMP0_ACMPOUT_PD0 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x0)
+#define ACMP0_ACMPOUT_PD1 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x1)
+#define ACMP0_ACMPOUT_PD2 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x2)
+#define ACMP0_ACMPOUT_PD3 SILABS_DBUS_ACMP0_ACMPOUT(0x3, 0x3)
+
+#define CMU_CLKOUT0_PC0 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x0)
+#define CMU_CLKOUT0_PC1 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x1)
+#define CMU_CLKOUT0_PC2 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x2)
+#define CMU_CLKOUT0_PC3 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x3)
+#define CMU_CLKOUT0_PC4 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x4)
+#define CMU_CLKOUT0_PC5 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x5)
+#define CMU_CLKOUT0_PC6 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x6)
+#define CMU_CLKOUT0_PC7 SILABS_DBUS_CMU_CLKOUT0(0x2, 0x7)
+#define CMU_CLKOUT0_PD0 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x0)
+#define CMU_CLKOUT0_PD1 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x1)
+#define CMU_CLKOUT0_PD2 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x2)
+#define CMU_CLKOUT0_PD3 SILABS_DBUS_CMU_CLKOUT0(0x3, 0x3)
+#define CMU_CLKOUT1_PC0 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x0)
+#define CMU_CLKOUT1_PC1 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x1)
+#define CMU_CLKOUT1_PC2 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x2)
+#define CMU_CLKOUT1_PC3 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x3)
+#define CMU_CLKOUT1_PC4 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x4)
+#define CMU_CLKOUT1_PC5 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x5)
+#define CMU_CLKOUT1_PC6 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x6)
+#define CMU_CLKOUT1_PC7 SILABS_DBUS_CMU_CLKOUT1(0x2, 0x7)
+#define CMU_CLKOUT1_PD0 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x0)
+#define CMU_CLKOUT1_PD1 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x1)
+#define CMU_CLKOUT1_PD2 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x2)
+#define CMU_CLKOUT1_PD3 SILABS_DBUS_CMU_CLKOUT1(0x3, 0x3)
+#define CMU_CLKOUT2_PA0 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x0)
+#define CMU_CLKOUT2_PA1 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x1)
+#define CMU_CLKOUT2_PA2 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x2)
+#define CMU_CLKOUT2_PA3 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x3)
+#define CMU_CLKOUT2_PA4 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x4)
+#define CMU_CLKOUT2_PA5 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x5)
+#define CMU_CLKOUT2_PA6 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x6)
+#define CMU_CLKOUT2_PA7 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x7)
+#define CMU_CLKOUT2_PA8 SILABS_DBUS_CMU_CLKOUT2(0x0, 0x8)
+#define CMU_CLKOUT2_PB0 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x0)
+#define CMU_CLKOUT2_PB1 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x1)
+#define CMU_CLKOUT2_PB2 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x2)
+#define CMU_CLKOUT2_PB3 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x3)
+#define CMU_CLKOUT2_PB4 SILABS_DBUS_CMU_CLKOUT2(0x1, 0x4)
+#define CMU_CLKIN0_PC0  SILABS_DBUS_CMU_CLKIN0(0x2, 0x0)
+#define CMU_CLKIN0_PC1  SILABS_DBUS_CMU_CLKIN0(0x2, 0x1)
+#define CMU_CLKIN0_PC2  SILABS_DBUS_CMU_CLKIN0(0x2, 0x2)
+#define CMU_CLKIN0_PC3  SILABS_DBUS_CMU_CLKIN0(0x2, 0x3)
+#define CMU_CLKIN0_PC4  SILABS_DBUS_CMU_CLKIN0(0x2, 0x4)
+#define CMU_CLKIN0_PC5  SILABS_DBUS_CMU_CLKIN0(0x2, 0x5)
+#define CMU_CLKIN0_PC6  SILABS_DBUS_CMU_CLKIN0(0x2, 0x6)
+#define CMU_CLKIN0_PC7  SILABS_DBUS_CMU_CLKIN0(0x2, 0x7)
+#define CMU_CLKIN0_PD0  SILABS_DBUS_CMU_CLKIN0(0x3, 0x0)
+#define CMU_CLKIN0_PD1  SILABS_DBUS_CMU_CLKIN0(0x3, 0x1)
+#define CMU_CLKIN0_PD2  SILABS_DBUS_CMU_CLKIN0(0x3, 0x2)
+#define CMU_CLKIN0_PD3  SILABS_DBUS_CMU_CLKIN0(0x3, 0x3)
+
+#define EUSART0_CS_PA0   SILABS_DBUS_EUSART0_CS(0x0, 0x0)
+#define EUSART0_CS_PA1   SILABS_DBUS_EUSART0_CS(0x0, 0x1)
+#define EUSART0_CS_PA2   SILABS_DBUS_EUSART0_CS(0x0, 0x2)
+#define EUSART0_CS_PA3   SILABS_DBUS_EUSART0_CS(0x0, 0x3)
+#define EUSART0_CS_PA4   SILABS_DBUS_EUSART0_CS(0x0, 0x4)
+#define EUSART0_CS_PA5   SILABS_DBUS_EUSART0_CS(0x0, 0x5)
+#define EUSART0_CS_PA6   SILABS_DBUS_EUSART0_CS(0x0, 0x6)
+#define EUSART0_CS_PA7   SILABS_DBUS_EUSART0_CS(0x0, 0x7)
+#define EUSART0_CS_PA8   SILABS_DBUS_EUSART0_CS(0x0, 0x8)
+#define EUSART0_CS_PB0   SILABS_DBUS_EUSART0_CS(0x1, 0x0)
+#define EUSART0_CS_PB1   SILABS_DBUS_EUSART0_CS(0x1, 0x1)
+#define EUSART0_CS_PB2   SILABS_DBUS_EUSART0_CS(0x1, 0x2)
+#define EUSART0_CS_PB3   SILABS_DBUS_EUSART0_CS(0x1, 0x3)
+#define EUSART0_CS_PB4   SILABS_DBUS_EUSART0_CS(0x1, 0x4)
+#define EUSART0_CS_PC0   SILABS_DBUS_EUSART0_CS(0x2, 0x0)
+#define EUSART0_CS_PC1   SILABS_DBUS_EUSART0_CS(0x2, 0x1)
+#define EUSART0_CS_PC2   SILABS_DBUS_EUSART0_CS(0x2, 0x2)
+#define EUSART0_CS_PC3   SILABS_DBUS_EUSART0_CS(0x2, 0x3)
+#define EUSART0_CS_PC4   SILABS_DBUS_EUSART0_CS(0x2, 0x4)
+#define EUSART0_CS_PC5   SILABS_DBUS_EUSART0_CS(0x2, 0x5)
+#define EUSART0_CS_PC6   SILABS_DBUS_EUSART0_CS(0x2, 0x6)
+#define EUSART0_CS_PC7   SILABS_DBUS_EUSART0_CS(0x2, 0x7)
+#define EUSART0_CS_PD0   SILABS_DBUS_EUSART0_CS(0x3, 0x0)
+#define EUSART0_CS_PD1   SILABS_DBUS_EUSART0_CS(0x3, 0x1)
+#define EUSART0_CS_PD2   SILABS_DBUS_EUSART0_CS(0x3, 0x2)
+#define EUSART0_CS_PD3   SILABS_DBUS_EUSART0_CS(0x3, 0x3)
+#define EUSART0_RTS_PA0  SILABS_DBUS_EUSART0_RTS(0x0, 0x0)
+#define EUSART0_RTS_PA1  SILABS_DBUS_EUSART0_RTS(0x0, 0x1)
+#define EUSART0_RTS_PA2  SILABS_DBUS_EUSART0_RTS(0x0, 0x2)
+#define EUSART0_RTS_PA3  SILABS_DBUS_EUSART0_RTS(0x0, 0x3)
+#define EUSART0_RTS_PA4  SILABS_DBUS_EUSART0_RTS(0x0, 0x4)
+#define EUSART0_RTS_PA5  SILABS_DBUS_EUSART0_RTS(0x0, 0x5)
+#define EUSART0_RTS_PA6  SILABS_DBUS_EUSART0_RTS(0x0, 0x6)
+#define EUSART0_RTS_PA7  SILABS_DBUS_EUSART0_RTS(0x0, 0x7)
+#define EUSART0_RTS_PA8  SILABS_DBUS_EUSART0_RTS(0x0, 0x8)
+#define EUSART0_RTS_PB0  SILABS_DBUS_EUSART0_RTS(0x1, 0x0)
+#define EUSART0_RTS_PB1  SILABS_DBUS_EUSART0_RTS(0x1, 0x1)
+#define EUSART0_RTS_PB2  SILABS_DBUS_EUSART0_RTS(0x1, 0x2)
+#define EUSART0_RTS_PB3  SILABS_DBUS_EUSART0_RTS(0x1, 0x3)
+#define EUSART0_RTS_PB4  SILABS_DBUS_EUSART0_RTS(0x1, 0x4)
+#define EUSART0_RTS_PC0  SILABS_DBUS_EUSART0_RTS(0x2, 0x0)
+#define EUSART0_RTS_PC1  SILABS_DBUS_EUSART0_RTS(0x2, 0x1)
+#define EUSART0_RTS_PC2  SILABS_DBUS_EUSART0_RTS(0x2, 0x2)
+#define EUSART0_RTS_PC3  SILABS_DBUS_EUSART0_RTS(0x2, 0x3)
+#define EUSART0_RTS_PC4  SILABS_DBUS_EUSART0_RTS(0x2, 0x4)
+#define EUSART0_RTS_PC5  SILABS_DBUS_EUSART0_RTS(0x2, 0x5)
+#define EUSART0_RTS_PC6  SILABS_DBUS_EUSART0_RTS(0x2, 0x6)
+#define EUSART0_RTS_PC7  SILABS_DBUS_EUSART0_RTS(0x2, 0x7)
+#define EUSART0_RTS_PD0  SILABS_DBUS_EUSART0_RTS(0x3, 0x0)
+#define EUSART0_RTS_PD1  SILABS_DBUS_EUSART0_RTS(0x3, 0x1)
+#define EUSART0_RTS_PD2  SILABS_DBUS_EUSART0_RTS(0x3, 0x2)
+#define EUSART0_RTS_PD3  SILABS_DBUS_EUSART0_RTS(0x3, 0x3)
+#define EUSART0_RX_PA0   SILABS_DBUS_EUSART0_RX(0x0, 0x0)
+#define EUSART0_RX_PA1   SILABS_DBUS_EUSART0_RX(0x0, 0x1)
+#define EUSART0_RX_PA2   SILABS_DBUS_EUSART0_RX(0x0, 0x2)
+#define EUSART0_RX_PA3   SILABS_DBUS_EUSART0_RX(0x0, 0x3)
+#define EUSART0_RX_PA4   SILABS_DBUS_EUSART0_RX(0x0, 0x4)
+#define EUSART0_RX_PA5   SILABS_DBUS_EUSART0_RX(0x0, 0x5)
+#define EUSART0_RX_PA6   SILABS_DBUS_EUSART0_RX(0x0, 0x6)
+#define EUSART0_RX_PA7   SILABS_DBUS_EUSART0_RX(0x0, 0x7)
+#define EUSART0_RX_PA8   SILABS_DBUS_EUSART0_RX(0x0, 0x8)
+#define EUSART0_RX_PB0   SILABS_DBUS_EUSART0_RX(0x1, 0x0)
+#define EUSART0_RX_PB1   SILABS_DBUS_EUSART0_RX(0x1, 0x1)
+#define EUSART0_RX_PB2   SILABS_DBUS_EUSART0_RX(0x1, 0x2)
+#define EUSART0_RX_PB3   SILABS_DBUS_EUSART0_RX(0x1, 0x3)
+#define EUSART0_RX_PB4   SILABS_DBUS_EUSART0_RX(0x1, 0x4)
+#define EUSART0_RX_PC0   SILABS_DBUS_EUSART0_RX(0x2, 0x0)
+#define EUSART0_RX_PC1   SILABS_DBUS_EUSART0_RX(0x2, 0x1)
+#define EUSART0_RX_PC2   SILABS_DBUS_EUSART0_RX(0x2, 0x2)
+#define EUSART0_RX_PC3   SILABS_DBUS_EUSART0_RX(0x2, 0x3)
+#define EUSART0_RX_PC4   SILABS_DBUS_EUSART0_RX(0x2, 0x4)
+#define EUSART0_RX_PC5   SILABS_DBUS_EUSART0_RX(0x2, 0x5)
+#define EUSART0_RX_PC6   SILABS_DBUS_EUSART0_RX(0x2, 0x6)
+#define EUSART0_RX_PC7   SILABS_DBUS_EUSART0_RX(0x2, 0x7)
+#define EUSART0_RX_PD0   SILABS_DBUS_EUSART0_RX(0x3, 0x0)
+#define EUSART0_RX_PD1   SILABS_DBUS_EUSART0_RX(0x3, 0x1)
+#define EUSART0_RX_PD2   SILABS_DBUS_EUSART0_RX(0x3, 0x2)
+#define EUSART0_RX_PD3   SILABS_DBUS_EUSART0_RX(0x3, 0x3)
+#define EUSART0_SCLK_PA0 SILABS_DBUS_EUSART0_SCLK(0x0, 0x0)
+#define EUSART0_SCLK_PA1 SILABS_DBUS_EUSART0_SCLK(0x0, 0x1)
+#define EUSART0_SCLK_PA2 SILABS_DBUS_EUSART0_SCLK(0x0, 0x2)
+#define EUSART0_SCLK_PA3 SILABS_DBUS_EUSART0_SCLK(0x0, 0x3)
+#define EUSART0_SCLK_PA4 SILABS_DBUS_EUSART0_SCLK(0x0, 0x4)
+#define EUSART0_SCLK_PA5 SILABS_DBUS_EUSART0_SCLK(0x0, 0x5)
+#define EUSART0_SCLK_PA6 SILABS_DBUS_EUSART0_SCLK(0x0, 0x6)
+#define EUSART0_SCLK_PA7 SILABS_DBUS_EUSART0_SCLK(0x0, 0x7)
+#define EUSART0_SCLK_PA8 SILABS_DBUS_EUSART0_SCLK(0x0, 0x8)
+#define EUSART0_SCLK_PB0 SILABS_DBUS_EUSART0_SCLK(0x1, 0x0)
+#define EUSART0_SCLK_PB1 SILABS_DBUS_EUSART0_SCLK(0x1, 0x1)
+#define EUSART0_SCLK_PB2 SILABS_DBUS_EUSART0_SCLK(0x1, 0x2)
+#define EUSART0_SCLK_PB3 SILABS_DBUS_EUSART0_SCLK(0x1, 0x3)
+#define EUSART0_SCLK_PB4 SILABS_DBUS_EUSART0_SCLK(0x1, 0x4)
+#define EUSART0_SCLK_PC0 SILABS_DBUS_EUSART0_SCLK(0x2, 0x0)
+#define EUSART0_SCLK_PC1 SILABS_DBUS_EUSART0_SCLK(0x2, 0x1)
+#define EUSART0_SCLK_PC2 SILABS_DBUS_EUSART0_SCLK(0x2, 0x2)
+#define EUSART0_SCLK_PC3 SILABS_DBUS_EUSART0_SCLK(0x2, 0x3)
+#define EUSART0_SCLK_PC4 SILABS_DBUS_EUSART0_SCLK(0x2, 0x4)
+#define EUSART0_SCLK_PC5 SILABS_DBUS_EUSART0_SCLK(0x2, 0x5)
+#define EUSART0_SCLK_PC6 SILABS_DBUS_EUSART0_SCLK(0x2, 0x6)
+#define EUSART0_SCLK_PC7 SILABS_DBUS_EUSART0_SCLK(0x2, 0x7)
+#define EUSART0_SCLK_PD0 SILABS_DBUS_EUSART0_SCLK(0x3, 0x0)
+#define EUSART0_SCLK_PD1 SILABS_DBUS_EUSART0_SCLK(0x3, 0x1)
+#define EUSART0_SCLK_PD2 SILABS_DBUS_EUSART0_SCLK(0x3, 0x2)
+#define EUSART0_SCLK_PD3 SILABS_DBUS_EUSART0_SCLK(0x3, 0x3)
+#define EUSART0_TX_PA0   SILABS_DBUS_EUSART0_TX(0x0, 0x0)
+#define EUSART0_TX_PA1   SILABS_DBUS_EUSART0_TX(0x0, 0x1)
+#define EUSART0_TX_PA2   SILABS_DBUS_EUSART0_TX(0x0, 0x2)
+#define EUSART0_TX_PA3   SILABS_DBUS_EUSART0_TX(0x0, 0x3)
+#define EUSART0_TX_PA4   SILABS_DBUS_EUSART0_TX(0x0, 0x4)
+#define EUSART0_TX_PA5   SILABS_DBUS_EUSART0_TX(0x0, 0x5)
+#define EUSART0_TX_PA6   SILABS_DBUS_EUSART0_TX(0x0, 0x6)
+#define EUSART0_TX_PA7   SILABS_DBUS_EUSART0_TX(0x0, 0x7)
+#define EUSART0_TX_PA8   SILABS_DBUS_EUSART0_TX(0x0, 0x8)
+#define EUSART0_TX_PB0   SILABS_DBUS_EUSART0_TX(0x1, 0x0)
+#define EUSART0_TX_PB1   SILABS_DBUS_EUSART0_TX(0x1, 0x1)
+#define EUSART0_TX_PB2   SILABS_DBUS_EUSART0_TX(0x1, 0x2)
+#define EUSART0_TX_PB3   SILABS_DBUS_EUSART0_TX(0x1, 0x3)
+#define EUSART0_TX_PB4   SILABS_DBUS_EUSART0_TX(0x1, 0x4)
+#define EUSART0_TX_PC0   SILABS_DBUS_EUSART0_TX(0x2, 0x0)
+#define EUSART0_TX_PC1   SILABS_DBUS_EUSART0_TX(0x2, 0x1)
+#define EUSART0_TX_PC2   SILABS_DBUS_EUSART0_TX(0x2, 0x2)
+#define EUSART0_TX_PC3   SILABS_DBUS_EUSART0_TX(0x2, 0x3)
+#define EUSART0_TX_PC4   SILABS_DBUS_EUSART0_TX(0x2, 0x4)
+#define EUSART0_TX_PC5   SILABS_DBUS_EUSART0_TX(0x2, 0x5)
+#define EUSART0_TX_PC6   SILABS_DBUS_EUSART0_TX(0x2, 0x6)
+#define EUSART0_TX_PC7   SILABS_DBUS_EUSART0_TX(0x2, 0x7)
+#define EUSART0_TX_PD0   SILABS_DBUS_EUSART0_TX(0x3, 0x0)
+#define EUSART0_TX_PD1   SILABS_DBUS_EUSART0_TX(0x3, 0x1)
+#define EUSART0_TX_PD2   SILABS_DBUS_EUSART0_TX(0x3, 0x2)
+#define EUSART0_TX_PD3   SILABS_DBUS_EUSART0_TX(0x3, 0x3)
+#define EUSART0_CTS_PA0  SILABS_DBUS_EUSART0_CTS(0x0, 0x0)
+#define EUSART0_CTS_PA1  SILABS_DBUS_EUSART0_CTS(0x0, 0x1)
+#define EUSART0_CTS_PA2  SILABS_DBUS_EUSART0_CTS(0x0, 0x2)
+#define EUSART0_CTS_PA3  SILABS_DBUS_EUSART0_CTS(0x0, 0x3)
+#define EUSART0_CTS_PA4  SILABS_DBUS_EUSART0_CTS(0x0, 0x4)
+#define EUSART0_CTS_PA5  SILABS_DBUS_EUSART0_CTS(0x0, 0x5)
+#define EUSART0_CTS_PA6  SILABS_DBUS_EUSART0_CTS(0x0, 0x6)
+#define EUSART0_CTS_PA7  SILABS_DBUS_EUSART0_CTS(0x0, 0x7)
+#define EUSART0_CTS_PA8  SILABS_DBUS_EUSART0_CTS(0x0, 0x8)
+#define EUSART0_CTS_PB0  SILABS_DBUS_EUSART0_CTS(0x1, 0x0)
+#define EUSART0_CTS_PB1  SILABS_DBUS_EUSART0_CTS(0x1, 0x1)
+#define EUSART0_CTS_PB2  SILABS_DBUS_EUSART0_CTS(0x1, 0x2)
+#define EUSART0_CTS_PB3  SILABS_DBUS_EUSART0_CTS(0x1, 0x3)
+#define EUSART0_CTS_PB4  SILABS_DBUS_EUSART0_CTS(0x1, 0x4)
+#define EUSART0_CTS_PC0  SILABS_DBUS_EUSART0_CTS(0x2, 0x0)
+#define EUSART0_CTS_PC1  SILABS_DBUS_EUSART0_CTS(0x2, 0x1)
+#define EUSART0_CTS_PC2  SILABS_DBUS_EUSART0_CTS(0x2, 0x2)
+#define EUSART0_CTS_PC3  SILABS_DBUS_EUSART0_CTS(0x2, 0x3)
+#define EUSART0_CTS_PC4  SILABS_DBUS_EUSART0_CTS(0x2, 0x4)
+#define EUSART0_CTS_PC5  SILABS_DBUS_EUSART0_CTS(0x2, 0x5)
+#define EUSART0_CTS_PC6  SILABS_DBUS_EUSART0_CTS(0x2, 0x6)
+#define EUSART0_CTS_PC7  SILABS_DBUS_EUSART0_CTS(0x2, 0x7)
+#define EUSART0_CTS_PD0  SILABS_DBUS_EUSART0_CTS(0x3, 0x0)
+#define EUSART0_CTS_PD1  SILABS_DBUS_EUSART0_CTS(0x3, 0x1)
+#define EUSART0_CTS_PD2  SILABS_DBUS_EUSART0_CTS(0x3, 0x2)
+#define EUSART0_CTS_PD3  SILABS_DBUS_EUSART0_CTS(0x3, 0x3)
+
+#define EUSART1_CS_PA0   SILABS_DBUS_EUSART1_CS(0x0, 0x0)
+#define EUSART1_CS_PA1   SILABS_DBUS_EUSART1_CS(0x0, 0x1)
+#define EUSART1_CS_PA2   SILABS_DBUS_EUSART1_CS(0x0, 0x2)
+#define EUSART1_CS_PA3   SILABS_DBUS_EUSART1_CS(0x0, 0x3)
+#define EUSART1_CS_PA4   SILABS_DBUS_EUSART1_CS(0x0, 0x4)
+#define EUSART1_CS_PA5   SILABS_DBUS_EUSART1_CS(0x0, 0x5)
+#define EUSART1_CS_PA6   SILABS_DBUS_EUSART1_CS(0x0, 0x6)
+#define EUSART1_CS_PA7   SILABS_DBUS_EUSART1_CS(0x0, 0x7)
+#define EUSART1_CS_PA8   SILABS_DBUS_EUSART1_CS(0x0, 0x8)
+#define EUSART1_CS_PB0   SILABS_DBUS_EUSART1_CS(0x1, 0x0)
+#define EUSART1_CS_PB1   SILABS_DBUS_EUSART1_CS(0x1, 0x1)
+#define EUSART1_CS_PB2   SILABS_DBUS_EUSART1_CS(0x1, 0x2)
+#define EUSART1_CS_PB3   SILABS_DBUS_EUSART1_CS(0x1, 0x3)
+#define EUSART1_CS_PB4   SILABS_DBUS_EUSART1_CS(0x1, 0x4)
+#define EUSART1_CS_PC0   SILABS_DBUS_EUSART1_CS(0x2, 0x0)
+#define EUSART1_CS_PC1   SILABS_DBUS_EUSART1_CS(0x2, 0x1)
+#define EUSART1_CS_PC2   SILABS_DBUS_EUSART1_CS(0x2, 0x2)
+#define EUSART1_CS_PC3   SILABS_DBUS_EUSART1_CS(0x2, 0x3)
+#define EUSART1_CS_PC4   SILABS_DBUS_EUSART1_CS(0x2, 0x4)
+#define EUSART1_CS_PC5   SILABS_DBUS_EUSART1_CS(0x2, 0x5)
+#define EUSART1_CS_PC6   SILABS_DBUS_EUSART1_CS(0x2, 0x6)
+#define EUSART1_CS_PC7   SILABS_DBUS_EUSART1_CS(0x2, 0x7)
+#define EUSART1_CS_PD0   SILABS_DBUS_EUSART1_CS(0x3, 0x0)
+#define EUSART1_CS_PD1   SILABS_DBUS_EUSART1_CS(0x3, 0x1)
+#define EUSART1_CS_PD2   SILABS_DBUS_EUSART1_CS(0x3, 0x2)
+#define EUSART1_CS_PD3   SILABS_DBUS_EUSART1_CS(0x3, 0x3)
+#define EUSART1_RTS_PA0  SILABS_DBUS_EUSART1_RTS(0x0, 0x0)
+#define EUSART1_RTS_PA1  SILABS_DBUS_EUSART1_RTS(0x0, 0x1)
+#define EUSART1_RTS_PA2  SILABS_DBUS_EUSART1_RTS(0x0, 0x2)
+#define EUSART1_RTS_PA3  SILABS_DBUS_EUSART1_RTS(0x0, 0x3)
+#define EUSART1_RTS_PA4  SILABS_DBUS_EUSART1_RTS(0x0, 0x4)
+#define EUSART1_RTS_PA5  SILABS_DBUS_EUSART1_RTS(0x0, 0x5)
+#define EUSART1_RTS_PA6  SILABS_DBUS_EUSART1_RTS(0x0, 0x6)
+#define EUSART1_RTS_PA7  SILABS_DBUS_EUSART1_RTS(0x0, 0x7)
+#define EUSART1_RTS_PA8  SILABS_DBUS_EUSART1_RTS(0x0, 0x8)
+#define EUSART1_RTS_PB0  SILABS_DBUS_EUSART1_RTS(0x1, 0x0)
+#define EUSART1_RTS_PB1  SILABS_DBUS_EUSART1_RTS(0x1, 0x1)
+#define EUSART1_RTS_PB2  SILABS_DBUS_EUSART1_RTS(0x1, 0x2)
+#define EUSART1_RTS_PB3  SILABS_DBUS_EUSART1_RTS(0x1, 0x3)
+#define EUSART1_RTS_PB4  SILABS_DBUS_EUSART1_RTS(0x1, 0x4)
+#define EUSART1_RTS_PC0  SILABS_DBUS_EUSART1_RTS(0x2, 0x0)
+#define EUSART1_RTS_PC1  SILABS_DBUS_EUSART1_RTS(0x2, 0x1)
+#define EUSART1_RTS_PC2  SILABS_DBUS_EUSART1_RTS(0x2, 0x2)
+#define EUSART1_RTS_PC3  SILABS_DBUS_EUSART1_RTS(0x2, 0x3)
+#define EUSART1_RTS_PC4  SILABS_DBUS_EUSART1_RTS(0x2, 0x4)
+#define EUSART1_RTS_PC5  SILABS_DBUS_EUSART1_RTS(0x2, 0x5)
+#define EUSART1_RTS_PC6  SILABS_DBUS_EUSART1_RTS(0x2, 0x6)
+#define EUSART1_RTS_PC7  SILABS_DBUS_EUSART1_RTS(0x2, 0x7)
+#define EUSART1_RTS_PD0  SILABS_DBUS_EUSART1_RTS(0x3, 0x0)
+#define EUSART1_RTS_PD1  SILABS_DBUS_EUSART1_RTS(0x3, 0x1)
+#define EUSART1_RTS_PD2  SILABS_DBUS_EUSART1_RTS(0x3, 0x2)
+#define EUSART1_RTS_PD3  SILABS_DBUS_EUSART1_RTS(0x3, 0x3)
+#define EUSART1_RX_PA0   SILABS_DBUS_EUSART1_RX(0x0, 0x0)
+#define EUSART1_RX_PA1   SILABS_DBUS_EUSART1_RX(0x0, 0x1)
+#define EUSART1_RX_PA2   SILABS_DBUS_EUSART1_RX(0x0, 0x2)
+#define EUSART1_RX_PA3   SILABS_DBUS_EUSART1_RX(0x0, 0x3)
+#define EUSART1_RX_PA4   SILABS_DBUS_EUSART1_RX(0x0, 0x4)
+#define EUSART1_RX_PA5   SILABS_DBUS_EUSART1_RX(0x0, 0x5)
+#define EUSART1_RX_PA6   SILABS_DBUS_EUSART1_RX(0x0, 0x6)
+#define EUSART1_RX_PA7   SILABS_DBUS_EUSART1_RX(0x0, 0x7)
+#define EUSART1_RX_PA8   SILABS_DBUS_EUSART1_RX(0x0, 0x8)
+#define EUSART1_RX_PB0   SILABS_DBUS_EUSART1_RX(0x1, 0x0)
+#define EUSART1_RX_PB1   SILABS_DBUS_EUSART1_RX(0x1, 0x1)
+#define EUSART1_RX_PB2   SILABS_DBUS_EUSART1_RX(0x1, 0x2)
+#define EUSART1_RX_PB3   SILABS_DBUS_EUSART1_RX(0x1, 0x3)
+#define EUSART1_RX_PB4   SILABS_DBUS_EUSART1_RX(0x1, 0x4)
+#define EUSART1_RX_PC0   SILABS_DBUS_EUSART1_RX(0x2, 0x0)
+#define EUSART1_RX_PC1   SILABS_DBUS_EUSART1_RX(0x2, 0x1)
+#define EUSART1_RX_PC2   SILABS_DBUS_EUSART1_RX(0x2, 0x2)
+#define EUSART1_RX_PC3   SILABS_DBUS_EUSART1_RX(0x2, 0x3)
+#define EUSART1_RX_PC4   SILABS_DBUS_EUSART1_RX(0x2, 0x4)
+#define EUSART1_RX_PC5   SILABS_DBUS_EUSART1_RX(0x2, 0x5)
+#define EUSART1_RX_PC6   SILABS_DBUS_EUSART1_RX(0x2, 0x6)
+#define EUSART1_RX_PC7   SILABS_DBUS_EUSART1_RX(0x2, 0x7)
+#define EUSART1_RX_PD0   SILABS_DBUS_EUSART1_RX(0x3, 0x0)
+#define EUSART1_RX_PD1   SILABS_DBUS_EUSART1_RX(0x3, 0x1)
+#define EUSART1_RX_PD2   SILABS_DBUS_EUSART1_RX(0x3, 0x2)
+#define EUSART1_RX_PD3   SILABS_DBUS_EUSART1_RX(0x3, 0x3)
+#define EUSART1_SCLK_PA0 SILABS_DBUS_EUSART1_SCLK(0x0, 0x0)
+#define EUSART1_SCLK_PA1 SILABS_DBUS_EUSART1_SCLK(0x0, 0x1)
+#define EUSART1_SCLK_PA2 SILABS_DBUS_EUSART1_SCLK(0x0, 0x2)
+#define EUSART1_SCLK_PA3 SILABS_DBUS_EUSART1_SCLK(0x0, 0x3)
+#define EUSART1_SCLK_PA4 SILABS_DBUS_EUSART1_SCLK(0x0, 0x4)
+#define EUSART1_SCLK_PA5 SILABS_DBUS_EUSART1_SCLK(0x0, 0x5)
+#define EUSART1_SCLK_PA6 SILABS_DBUS_EUSART1_SCLK(0x0, 0x6)
+#define EUSART1_SCLK_PA7 SILABS_DBUS_EUSART1_SCLK(0x0, 0x7)
+#define EUSART1_SCLK_PA8 SILABS_DBUS_EUSART1_SCLK(0x0, 0x8)
+#define EUSART1_SCLK_PB0 SILABS_DBUS_EUSART1_SCLK(0x1, 0x0)
+#define EUSART1_SCLK_PB1 SILABS_DBUS_EUSART1_SCLK(0x1, 0x1)
+#define EUSART1_SCLK_PB2 SILABS_DBUS_EUSART1_SCLK(0x1, 0x2)
+#define EUSART1_SCLK_PB3 SILABS_DBUS_EUSART1_SCLK(0x1, 0x3)
+#define EUSART1_SCLK_PB4 SILABS_DBUS_EUSART1_SCLK(0x1, 0x4)
+#define EUSART1_SCLK_PC0 SILABS_DBUS_EUSART1_SCLK(0x2, 0x0)
+#define EUSART1_SCLK_PC1 SILABS_DBUS_EUSART1_SCLK(0x2, 0x1)
+#define EUSART1_SCLK_PC2 SILABS_DBUS_EUSART1_SCLK(0x2, 0x2)
+#define EUSART1_SCLK_PC3 SILABS_DBUS_EUSART1_SCLK(0x2, 0x3)
+#define EUSART1_SCLK_PC4 SILABS_DBUS_EUSART1_SCLK(0x2, 0x4)
+#define EUSART1_SCLK_PC5 SILABS_DBUS_EUSART1_SCLK(0x2, 0x5)
+#define EUSART1_SCLK_PC6 SILABS_DBUS_EUSART1_SCLK(0x2, 0x6)
+#define EUSART1_SCLK_PC7 SILABS_DBUS_EUSART1_SCLK(0x2, 0x7)
+#define EUSART1_SCLK_PD0 SILABS_DBUS_EUSART1_SCLK(0x3, 0x0)
+#define EUSART1_SCLK_PD1 SILABS_DBUS_EUSART1_SCLK(0x3, 0x1)
+#define EUSART1_SCLK_PD2 SILABS_DBUS_EUSART1_SCLK(0x3, 0x2)
+#define EUSART1_SCLK_PD3 SILABS_DBUS_EUSART1_SCLK(0x3, 0x3)
+#define EUSART1_TX_PA0   SILABS_DBUS_EUSART1_TX(0x0, 0x0)
+#define EUSART1_TX_PA1   SILABS_DBUS_EUSART1_TX(0x0, 0x1)
+#define EUSART1_TX_PA2   SILABS_DBUS_EUSART1_TX(0x0, 0x2)
+#define EUSART1_TX_PA3   SILABS_DBUS_EUSART1_TX(0x0, 0x3)
+#define EUSART1_TX_PA4   SILABS_DBUS_EUSART1_TX(0x0, 0x4)
+#define EUSART1_TX_PA5   SILABS_DBUS_EUSART1_TX(0x0, 0x5)
+#define EUSART1_TX_PA6   SILABS_DBUS_EUSART1_TX(0x0, 0x6)
+#define EUSART1_TX_PA7   SILABS_DBUS_EUSART1_TX(0x0, 0x7)
+#define EUSART1_TX_PA8   SILABS_DBUS_EUSART1_TX(0x0, 0x8)
+#define EUSART1_TX_PB0   SILABS_DBUS_EUSART1_TX(0x1, 0x0)
+#define EUSART1_TX_PB1   SILABS_DBUS_EUSART1_TX(0x1, 0x1)
+#define EUSART1_TX_PB2   SILABS_DBUS_EUSART1_TX(0x1, 0x2)
+#define EUSART1_TX_PB3   SILABS_DBUS_EUSART1_TX(0x1, 0x3)
+#define EUSART1_TX_PB4   SILABS_DBUS_EUSART1_TX(0x1, 0x4)
+#define EUSART1_TX_PC0   SILABS_DBUS_EUSART1_TX(0x2, 0x0)
+#define EUSART1_TX_PC1   SILABS_DBUS_EUSART1_TX(0x2, 0x1)
+#define EUSART1_TX_PC2   SILABS_DBUS_EUSART1_TX(0x2, 0x2)
+#define EUSART1_TX_PC3   SILABS_DBUS_EUSART1_TX(0x2, 0x3)
+#define EUSART1_TX_PC4   SILABS_DBUS_EUSART1_TX(0x2, 0x4)
+#define EUSART1_TX_PC5   SILABS_DBUS_EUSART1_TX(0x2, 0x5)
+#define EUSART1_TX_PC6   SILABS_DBUS_EUSART1_TX(0x2, 0x6)
+#define EUSART1_TX_PC7   SILABS_DBUS_EUSART1_TX(0x2, 0x7)
+#define EUSART1_TX_PD0   SILABS_DBUS_EUSART1_TX(0x3, 0x0)
+#define EUSART1_TX_PD1   SILABS_DBUS_EUSART1_TX(0x3, 0x1)
+#define EUSART1_TX_PD2   SILABS_DBUS_EUSART1_TX(0x3, 0x2)
+#define EUSART1_TX_PD3   SILABS_DBUS_EUSART1_TX(0x3, 0x3)
+#define EUSART1_CTS_PA0  SILABS_DBUS_EUSART1_CTS(0x0, 0x0)
+#define EUSART1_CTS_PA1  SILABS_DBUS_EUSART1_CTS(0x0, 0x1)
+#define EUSART1_CTS_PA2  SILABS_DBUS_EUSART1_CTS(0x0, 0x2)
+#define EUSART1_CTS_PA3  SILABS_DBUS_EUSART1_CTS(0x0, 0x3)
+#define EUSART1_CTS_PA4  SILABS_DBUS_EUSART1_CTS(0x0, 0x4)
+#define EUSART1_CTS_PA5  SILABS_DBUS_EUSART1_CTS(0x0, 0x5)
+#define EUSART1_CTS_PA6  SILABS_DBUS_EUSART1_CTS(0x0, 0x6)
+#define EUSART1_CTS_PA7  SILABS_DBUS_EUSART1_CTS(0x0, 0x7)
+#define EUSART1_CTS_PA8  SILABS_DBUS_EUSART1_CTS(0x0, 0x8)
+#define EUSART1_CTS_PB0  SILABS_DBUS_EUSART1_CTS(0x1, 0x0)
+#define EUSART1_CTS_PB1  SILABS_DBUS_EUSART1_CTS(0x1, 0x1)
+#define EUSART1_CTS_PB2  SILABS_DBUS_EUSART1_CTS(0x1, 0x2)
+#define EUSART1_CTS_PB3  SILABS_DBUS_EUSART1_CTS(0x1, 0x3)
+#define EUSART1_CTS_PB4  SILABS_DBUS_EUSART1_CTS(0x1, 0x4)
+#define EUSART1_CTS_PC0  SILABS_DBUS_EUSART1_CTS(0x2, 0x0)
+#define EUSART1_CTS_PC1  SILABS_DBUS_EUSART1_CTS(0x2, 0x1)
+#define EUSART1_CTS_PC2  SILABS_DBUS_EUSART1_CTS(0x2, 0x2)
+#define EUSART1_CTS_PC3  SILABS_DBUS_EUSART1_CTS(0x2, 0x3)
+#define EUSART1_CTS_PC4  SILABS_DBUS_EUSART1_CTS(0x2, 0x4)
+#define EUSART1_CTS_PC5  SILABS_DBUS_EUSART1_CTS(0x2, 0x5)
+#define EUSART1_CTS_PC6  SILABS_DBUS_EUSART1_CTS(0x2, 0x6)
+#define EUSART1_CTS_PC7  SILABS_DBUS_EUSART1_CTS(0x2, 0x7)
+#define EUSART1_CTS_PD0  SILABS_DBUS_EUSART1_CTS(0x3, 0x0)
+#define EUSART1_CTS_PD1  SILABS_DBUS_EUSART1_CTS(0x3, 0x1)
+#define EUSART1_CTS_PD2  SILABS_DBUS_EUSART1_CTS(0x3, 0x2)
+#define EUSART1_CTS_PD3  SILABS_DBUS_EUSART1_CTS(0x3, 0x3)
+
+#define PTI_DCLK_PC0   SILABS_DBUS_PTI_DCLK(0x2, 0x0)
+#define PTI_DCLK_PC1   SILABS_DBUS_PTI_DCLK(0x2, 0x1)
+#define PTI_DCLK_PC2   SILABS_DBUS_PTI_DCLK(0x2, 0x2)
+#define PTI_DCLK_PC3   SILABS_DBUS_PTI_DCLK(0x2, 0x3)
+#define PTI_DCLK_PC4   SILABS_DBUS_PTI_DCLK(0x2, 0x4)
+#define PTI_DCLK_PC5   SILABS_DBUS_PTI_DCLK(0x2, 0x5)
+#define PTI_DCLK_PC6   SILABS_DBUS_PTI_DCLK(0x2, 0x6)
+#define PTI_DCLK_PC7   SILABS_DBUS_PTI_DCLK(0x2, 0x7)
+#define PTI_DCLK_PD0   SILABS_DBUS_PTI_DCLK(0x3, 0x0)
+#define PTI_DCLK_PD1   SILABS_DBUS_PTI_DCLK(0x3, 0x1)
+#define PTI_DCLK_PD2   SILABS_DBUS_PTI_DCLK(0x3, 0x2)
+#define PTI_DCLK_PD3   SILABS_DBUS_PTI_DCLK(0x3, 0x3)
+#define PTI_DFRAME_PC0 SILABS_DBUS_PTI_DFRAME(0x2, 0x0)
+#define PTI_DFRAME_PC1 SILABS_DBUS_PTI_DFRAME(0x2, 0x1)
+#define PTI_DFRAME_PC2 SILABS_DBUS_PTI_DFRAME(0x2, 0x2)
+#define PTI_DFRAME_PC3 SILABS_DBUS_PTI_DFRAME(0x2, 0x3)
+#define PTI_DFRAME_PC4 SILABS_DBUS_PTI_DFRAME(0x2, 0x4)
+#define PTI_DFRAME_PC5 SILABS_DBUS_PTI_DFRAME(0x2, 0x5)
+#define PTI_DFRAME_PC6 SILABS_DBUS_PTI_DFRAME(0x2, 0x6)
+#define PTI_DFRAME_PC7 SILABS_DBUS_PTI_DFRAME(0x2, 0x7)
+#define PTI_DFRAME_PD0 SILABS_DBUS_PTI_DFRAME(0x3, 0x0)
+#define PTI_DFRAME_PD1 SILABS_DBUS_PTI_DFRAME(0x3, 0x1)
+#define PTI_DFRAME_PD2 SILABS_DBUS_PTI_DFRAME(0x3, 0x2)
+#define PTI_DFRAME_PD3 SILABS_DBUS_PTI_DFRAME(0x3, 0x3)
+#define PTI_DOUT_PC0   SILABS_DBUS_PTI_DOUT(0x2, 0x0)
+#define PTI_DOUT_PC1   SILABS_DBUS_PTI_DOUT(0x2, 0x1)
+#define PTI_DOUT_PC2   SILABS_DBUS_PTI_DOUT(0x2, 0x2)
+#define PTI_DOUT_PC3   SILABS_DBUS_PTI_DOUT(0x2, 0x3)
+#define PTI_DOUT_PC4   SILABS_DBUS_PTI_DOUT(0x2, 0x4)
+#define PTI_DOUT_PC5   SILABS_DBUS_PTI_DOUT(0x2, 0x5)
+#define PTI_DOUT_PC6   SILABS_DBUS_PTI_DOUT(0x2, 0x6)
+#define PTI_DOUT_PC7   SILABS_DBUS_PTI_DOUT(0x2, 0x7)
+#define PTI_DOUT_PD0   SILABS_DBUS_PTI_DOUT(0x3, 0x0)
+#define PTI_DOUT_PD1   SILABS_DBUS_PTI_DOUT(0x3, 0x1)
+#define PTI_DOUT_PD2   SILABS_DBUS_PTI_DOUT(0x3, 0x2)
+#define PTI_DOUT_PD3   SILABS_DBUS_PTI_DOUT(0x3, 0x3)
+
+#define I2C0_SCL_PA0 SILABS_DBUS_I2C0_SCL(0x0, 0x0)
+#define I2C0_SCL_PA1 SILABS_DBUS_I2C0_SCL(0x0, 0x1)
+#define I2C0_SCL_PA2 SILABS_DBUS_I2C0_SCL(0x0, 0x2)
+#define I2C0_SCL_PA3 SILABS_DBUS_I2C0_SCL(0x0, 0x3)
+#define I2C0_SCL_PA4 SILABS_DBUS_I2C0_SCL(0x0, 0x4)
+#define I2C0_SCL_PA5 SILABS_DBUS_I2C0_SCL(0x0, 0x5)
+#define I2C0_SCL_PA6 SILABS_DBUS_I2C0_SCL(0x0, 0x6)
+#define I2C0_SCL_PA7 SILABS_DBUS_I2C0_SCL(0x0, 0x7)
+#define I2C0_SCL_PA8 SILABS_DBUS_I2C0_SCL(0x0, 0x8)
+#define I2C0_SCL_PB0 SILABS_DBUS_I2C0_SCL(0x1, 0x0)
+#define I2C0_SCL_PB1 SILABS_DBUS_I2C0_SCL(0x1, 0x1)
+#define I2C0_SCL_PB2 SILABS_DBUS_I2C0_SCL(0x1, 0x2)
+#define I2C0_SCL_PB3 SILABS_DBUS_I2C0_SCL(0x1, 0x3)
+#define I2C0_SCL_PB4 SILABS_DBUS_I2C0_SCL(0x1, 0x4)
+#define I2C0_SCL_PC0 SILABS_DBUS_I2C0_SCL(0x2, 0x0)
+#define I2C0_SCL_PC1 SILABS_DBUS_I2C0_SCL(0x2, 0x1)
+#define I2C0_SCL_PC2 SILABS_DBUS_I2C0_SCL(0x2, 0x2)
+#define I2C0_SCL_PC3 SILABS_DBUS_I2C0_SCL(0x2, 0x3)
+#define I2C0_SCL_PC4 SILABS_DBUS_I2C0_SCL(0x2, 0x4)
+#define I2C0_SCL_PC5 SILABS_DBUS_I2C0_SCL(0x2, 0x5)
+#define I2C0_SCL_PC6 SILABS_DBUS_I2C0_SCL(0x2, 0x6)
+#define I2C0_SCL_PC7 SILABS_DBUS_I2C0_SCL(0x2, 0x7)
+#define I2C0_SCL_PD0 SILABS_DBUS_I2C0_SCL(0x3, 0x0)
+#define I2C0_SCL_PD1 SILABS_DBUS_I2C0_SCL(0x3, 0x1)
+#define I2C0_SCL_PD2 SILABS_DBUS_I2C0_SCL(0x3, 0x2)
+#define I2C0_SCL_PD3 SILABS_DBUS_I2C0_SCL(0x3, 0x3)
+#define I2C0_SDA_PA0 SILABS_DBUS_I2C0_SDA(0x0, 0x0)
+#define I2C0_SDA_PA1 SILABS_DBUS_I2C0_SDA(0x0, 0x1)
+#define I2C0_SDA_PA2 SILABS_DBUS_I2C0_SDA(0x0, 0x2)
+#define I2C0_SDA_PA3 SILABS_DBUS_I2C0_SDA(0x0, 0x3)
+#define I2C0_SDA_PA4 SILABS_DBUS_I2C0_SDA(0x0, 0x4)
+#define I2C0_SDA_PA5 SILABS_DBUS_I2C0_SDA(0x0, 0x5)
+#define I2C0_SDA_PA6 SILABS_DBUS_I2C0_SDA(0x0, 0x6)
+#define I2C0_SDA_PA7 SILABS_DBUS_I2C0_SDA(0x0, 0x7)
+#define I2C0_SDA_PA8 SILABS_DBUS_I2C0_SDA(0x0, 0x8)
+#define I2C0_SDA_PB0 SILABS_DBUS_I2C0_SDA(0x1, 0x0)
+#define I2C0_SDA_PB1 SILABS_DBUS_I2C0_SDA(0x1, 0x1)
+#define I2C0_SDA_PB2 SILABS_DBUS_I2C0_SDA(0x1, 0x2)
+#define I2C0_SDA_PB3 SILABS_DBUS_I2C0_SDA(0x1, 0x3)
+#define I2C0_SDA_PB4 SILABS_DBUS_I2C0_SDA(0x1, 0x4)
+#define I2C0_SDA_PC0 SILABS_DBUS_I2C0_SDA(0x2, 0x0)
+#define I2C0_SDA_PC1 SILABS_DBUS_I2C0_SDA(0x2, 0x1)
+#define I2C0_SDA_PC2 SILABS_DBUS_I2C0_SDA(0x2, 0x2)
+#define I2C0_SDA_PC3 SILABS_DBUS_I2C0_SDA(0x2, 0x3)
+#define I2C0_SDA_PC4 SILABS_DBUS_I2C0_SDA(0x2, 0x4)
+#define I2C0_SDA_PC5 SILABS_DBUS_I2C0_SDA(0x2, 0x5)
+#define I2C0_SDA_PC6 SILABS_DBUS_I2C0_SDA(0x2, 0x6)
+#define I2C0_SDA_PC7 SILABS_DBUS_I2C0_SDA(0x2, 0x7)
+#define I2C0_SDA_PD0 SILABS_DBUS_I2C0_SDA(0x3, 0x0)
+#define I2C0_SDA_PD1 SILABS_DBUS_I2C0_SDA(0x3, 0x1)
+#define I2C0_SDA_PD2 SILABS_DBUS_I2C0_SDA(0x3, 0x2)
+#define I2C0_SDA_PD3 SILABS_DBUS_I2C0_SDA(0x3, 0x3)
+
+#define I2C1_SCL_PC0 SILABS_DBUS_I2C1_SCL(0x2, 0x0)
+#define I2C1_SCL_PC1 SILABS_DBUS_I2C1_SCL(0x2, 0x1)
+#define I2C1_SCL_PC2 SILABS_DBUS_I2C1_SCL(0x2, 0x2)
+#define I2C1_SCL_PC3 SILABS_DBUS_I2C1_SCL(0x2, 0x3)
+#define I2C1_SCL_PC4 SILABS_DBUS_I2C1_SCL(0x2, 0x4)
+#define I2C1_SCL_PC5 SILABS_DBUS_I2C1_SCL(0x2, 0x5)
+#define I2C1_SCL_PC6 SILABS_DBUS_I2C1_SCL(0x2, 0x6)
+#define I2C1_SCL_PC7 SILABS_DBUS_I2C1_SCL(0x2, 0x7)
+#define I2C1_SCL_PD0 SILABS_DBUS_I2C1_SCL(0x3, 0x0)
+#define I2C1_SCL_PD1 SILABS_DBUS_I2C1_SCL(0x3, 0x1)
+#define I2C1_SCL_PD2 SILABS_DBUS_I2C1_SCL(0x3, 0x2)
+#define I2C1_SCL_PD3 SILABS_DBUS_I2C1_SCL(0x3, 0x3)
+#define I2C1_SDA_PC0 SILABS_DBUS_I2C1_SDA(0x2, 0x0)
+#define I2C1_SDA_PC1 SILABS_DBUS_I2C1_SDA(0x2, 0x1)
+#define I2C1_SDA_PC2 SILABS_DBUS_I2C1_SDA(0x2, 0x2)
+#define I2C1_SDA_PC3 SILABS_DBUS_I2C1_SDA(0x2, 0x3)
+#define I2C1_SDA_PC4 SILABS_DBUS_I2C1_SDA(0x2, 0x4)
+#define I2C1_SDA_PC5 SILABS_DBUS_I2C1_SDA(0x2, 0x5)
+#define I2C1_SDA_PC6 SILABS_DBUS_I2C1_SDA(0x2, 0x6)
+#define I2C1_SDA_PC7 SILABS_DBUS_I2C1_SDA(0x2, 0x7)
+#define I2C1_SDA_PD0 SILABS_DBUS_I2C1_SDA(0x3, 0x0)
+#define I2C1_SDA_PD1 SILABS_DBUS_I2C1_SDA(0x3, 0x1)
+#define I2C1_SDA_PD2 SILABS_DBUS_I2C1_SDA(0x3, 0x2)
+#define I2C1_SDA_PD3 SILABS_DBUS_I2C1_SDA(0x3, 0x3)
+
+#define LETIMER0_OUT0_PA0 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x0)
+#define LETIMER0_OUT0_PA1 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x1)
+#define LETIMER0_OUT0_PA2 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x2)
+#define LETIMER0_OUT0_PA3 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x3)
+#define LETIMER0_OUT0_PA4 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x4)
+#define LETIMER0_OUT0_PA5 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x5)
+#define LETIMER0_OUT0_PA6 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x6)
+#define LETIMER0_OUT0_PA7 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x7)
+#define LETIMER0_OUT0_PA8 SILABS_DBUS_LETIMER0_OUT0(0x0, 0x8)
+#define LETIMER0_OUT0_PB0 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x0)
+#define LETIMER0_OUT0_PB1 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x1)
+#define LETIMER0_OUT0_PB2 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x2)
+#define LETIMER0_OUT0_PB3 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x3)
+#define LETIMER0_OUT0_PB4 SILABS_DBUS_LETIMER0_OUT0(0x1, 0x4)
+#define LETIMER0_OUT1_PA0 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x0)
+#define LETIMER0_OUT1_PA1 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x1)
+#define LETIMER0_OUT1_PA2 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x2)
+#define LETIMER0_OUT1_PA3 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x3)
+#define LETIMER0_OUT1_PA4 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x4)
+#define LETIMER0_OUT1_PA5 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x5)
+#define LETIMER0_OUT1_PA6 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x6)
+#define LETIMER0_OUT1_PA7 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x7)
+#define LETIMER0_OUT1_PA8 SILABS_DBUS_LETIMER0_OUT1(0x0, 0x8)
+#define LETIMER0_OUT1_PB0 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x0)
+#define LETIMER0_OUT1_PB1 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x1)
+#define LETIMER0_OUT1_PB2 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x2)
+#define LETIMER0_OUT1_PB3 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x3)
+#define LETIMER0_OUT1_PB4 SILABS_DBUS_LETIMER0_OUT1(0x1, 0x4)
+
+#define MODEM_ANT0_PA0        SILABS_DBUS_MODEM_ANT0(0x0, 0x0)
+#define MODEM_ANT0_PA1        SILABS_DBUS_MODEM_ANT0(0x0, 0x1)
+#define MODEM_ANT0_PA2        SILABS_DBUS_MODEM_ANT0(0x0, 0x2)
+#define MODEM_ANT0_PA3        SILABS_DBUS_MODEM_ANT0(0x0, 0x3)
+#define MODEM_ANT0_PA4        SILABS_DBUS_MODEM_ANT0(0x0, 0x4)
+#define MODEM_ANT0_PA5        SILABS_DBUS_MODEM_ANT0(0x0, 0x5)
+#define MODEM_ANT0_PA6        SILABS_DBUS_MODEM_ANT0(0x0, 0x6)
+#define MODEM_ANT0_PA7        SILABS_DBUS_MODEM_ANT0(0x0, 0x7)
+#define MODEM_ANT0_PA8        SILABS_DBUS_MODEM_ANT0(0x0, 0x8)
+#define MODEM_ANT0_PB0        SILABS_DBUS_MODEM_ANT0(0x1, 0x0)
+#define MODEM_ANT0_PB1        SILABS_DBUS_MODEM_ANT0(0x1, 0x1)
+#define MODEM_ANT0_PB2        SILABS_DBUS_MODEM_ANT0(0x1, 0x2)
+#define MODEM_ANT0_PB3        SILABS_DBUS_MODEM_ANT0(0x1, 0x3)
+#define MODEM_ANT0_PB4        SILABS_DBUS_MODEM_ANT0(0x1, 0x4)
+#define MODEM_ANT0_PC0        SILABS_DBUS_MODEM_ANT0(0x2, 0x0)
+#define MODEM_ANT0_PC1        SILABS_DBUS_MODEM_ANT0(0x2, 0x1)
+#define MODEM_ANT0_PC2        SILABS_DBUS_MODEM_ANT0(0x2, 0x2)
+#define MODEM_ANT0_PC3        SILABS_DBUS_MODEM_ANT0(0x2, 0x3)
+#define MODEM_ANT0_PC4        SILABS_DBUS_MODEM_ANT0(0x2, 0x4)
+#define MODEM_ANT0_PC5        SILABS_DBUS_MODEM_ANT0(0x2, 0x5)
+#define MODEM_ANT0_PC6        SILABS_DBUS_MODEM_ANT0(0x2, 0x6)
+#define MODEM_ANT0_PC7        SILABS_DBUS_MODEM_ANT0(0x2, 0x7)
+#define MODEM_ANT0_PD0        SILABS_DBUS_MODEM_ANT0(0x3, 0x0)
+#define MODEM_ANT0_PD1        SILABS_DBUS_MODEM_ANT0(0x3, 0x1)
+#define MODEM_ANT0_PD2        SILABS_DBUS_MODEM_ANT0(0x3, 0x2)
+#define MODEM_ANT0_PD3        SILABS_DBUS_MODEM_ANT0(0x3, 0x3)
+#define MODEM_ANT1_PA0        SILABS_DBUS_MODEM_ANT1(0x0, 0x0)
+#define MODEM_ANT1_PA1        SILABS_DBUS_MODEM_ANT1(0x0, 0x1)
+#define MODEM_ANT1_PA2        SILABS_DBUS_MODEM_ANT1(0x0, 0x2)
+#define MODEM_ANT1_PA3        SILABS_DBUS_MODEM_ANT1(0x0, 0x3)
+#define MODEM_ANT1_PA4        SILABS_DBUS_MODEM_ANT1(0x0, 0x4)
+#define MODEM_ANT1_PA5        SILABS_DBUS_MODEM_ANT1(0x0, 0x5)
+#define MODEM_ANT1_PA6        SILABS_DBUS_MODEM_ANT1(0x0, 0x6)
+#define MODEM_ANT1_PA7        SILABS_DBUS_MODEM_ANT1(0x0, 0x7)
+#define MODEM_ANT1_PA8        SILABS_DBUS_MODEM_ANT1(0x0, 0x8)
+#define MODEM_ANT1_PB0        SILABS_DBUS_MODEM_ANT1(0x1, 0x0)
+#define MODEM_ANT1_PB1        SILABS_DBUS_MODEM_ANT1(0x1, 0x1)
+#define MODEM_ANT1_PB2        SILABS_DBUS_MODEM_ANT1(0x1, 0x2)
+#define MODEM_ANT1_PB3        SILABS_DBUS_MODEM_ANT1(0x1, 0x3)
+#define MODEM_ANT1_PB4        SILABS_DBUS_MODEM_ANT1(0x1, 0x4)
+#define MODEM_ANT1_PC0        SILABS_DBUS_MODEM_ANT1(0x2, 0x0)
+#define MODEM_ANT1_PC1        SILABS_DBUS_MODEM_ANT1(0x2, 0x1)
+#define MODEM_ANT1_PC2        SILABS_DBUS_MODEM_ANT1(0x2, 0x2)
+#define MODEM_ANT1_PC3        SILABS_DBUS_MODEM_ANT1(0x2, 0x3)
+#define MODEM_ANT1_PC4        SILABS_DBUS_MODEM_ANT1(0x2, 0x4)
+#define MODEM_ANT1_PC5        SILABS_DBUS_MODEM_ANT1(0x2, 0x5)
+#define MODEM_ANT1_PC6        SILABS_DBUS_MODEM_ANT1(0x2, 0x6)
+#define MODEM_ANT1_PC7        SILABS_DBUS_MODEM_ANT1(0x2, 0x7)
+#define MODEM_ANT1_PD0        SILABS_DBUS_MODEM_ANT1(0x3, 0x0)
+#define MODEM_ANT1_PD1        SILABS_DBUS_MODEM_ANT1(0x3, 0x1)
+#define MODEM_ANT1_PD2        SILABS_DBUS_MODEM_ANT1(0x3, 0x2)
+#define MODEM_ANT1_PD3        SILABS_DBUS_MODEM_ANT1(0x3, 0x3)
+#define MODEM_ANTROLLOVER_PC0 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x0)
+#define MODEM_ANTROLLOVER_PC1 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x1)
+#define MODEM_ANTROLLOVER_PC2 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x2)
+#define MODEM_ANTROLLOVER_PC3 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x3)
+#define MODEM_ANTROLLOVER_PC4 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x4)
+#define MODEM_ANTROLLOVER_PC5 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x5)
+#define MODEM_ANTROLLOVER_PC6 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x6)
+#define MODEM_ANTROLLOVER_PC7 SILABS_DBUS_MODEM_ANTROLLOVER(0x2, 0x7)
+#define MODEM_ANTROLLOVER_PD0 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x0)
+#define MODEM_ANTROLLOVER_PD1 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x1)
+#define MODEM_ANTROLLOVER_PD2 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x2)
+#define MODEM_ANTROLLOVER_PD3 SILABS_DBUS_MODEM_ANTROLLOVER(0x3, 0x3)
+#define MODEM_ANTRR0_PC0      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x0)
+#define MODEM_ANTRR0_PC1      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x1)
+#define MODEM_ANTRR0_PC2      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x2)
+#define MODEM_ANTRR0_PC3      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x3)
+#define MODEM_ANTRR0_PC4      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x4)
+#define MODEM_ANTRR0_PC5      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x5)
+#define MODEM_ANTRR0_PC6      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x6)
+#define MODEM_ANTRR0_PC7      SILABS_DBUS_MODEM_ANTRR0(0x2, 0x7)
+#define MODEM_ANTRR0_PD0      SILABS_DBUS_MODEM_ANTRR0(0x3, 0x0)
+#define MODEM_ANTRR0_PD1      SILABS_DBUS_MODEM_ANTRR0(0x3, 0x1)
+#define MODEM_ANTRR0_PD2      SILABS_DBUS_MODEM_ANTRR0(0x3, 0x2)
+#define MODEM_ANTRR0_PD3      SILABS_DBUS_MODEM_ANTRR0(0x3, 0x3)
+#define MODEM_ANTRR1_PC0      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x0)
+#define MODEM_ANTRR1_PC1      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x1)
+#define MODEM_ANTRR1_PC2      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x2)
+#define MODEM_ANTRR1_PC3      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x3)
+#define MODEM_ANTRR1_PC4      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x4)
+#define MODEM_ANTRR1_PC5      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x5)
+#define MODEM_ANTRR1_PC6      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x6)
+#define MODEM_ANTRR1_PC7      SILABS_DBUS_MODEM_ANTRR1(0x2, 0x7)
+#define MODEM_ANTRR1_PD0      SILABS_DBUS_MODEM_ANTRR1(0x3, 0x0)
+#define MODEM_ANTRR1_PD1      SILABS_DBUS_MODEM_ANTRR1(0x3, 0x1)
+#define MODEM_ANTRR1_PD2      SILABS_DBUS_MODEM_ANTRR1(0x3, 0x2)
+#define MODEM_ANTRR1_PD3      SILABS_DBUS_MODEM_ANTRR1(0x3, 0x3)
+#define MODEM_ANTRR2_PC0      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x0)
+#define MODEM_ANTRR2_PC1      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x1)
+#define MODEM_ANTRR2_PC2      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x2)
+#define MODEM_ANTRR2_PC3      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x3)
+#define MODEM_ANTRR2_PC4      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x4)
+#define MODEM_ANTRR2_PC5      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x5)
+#define MODEM_ANTRR2_PC6      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x6)
+#define MODEM_ANTRR2_PC7      SILABS_DBUS_MODEM_ANTRR2(0x2, 0x7)
+#define MODEM_ANTRR2_PD0      SILABS_DBUS_MODEM_ANTRR2(0x3, 0x0)
+#define MODEM_ANTRR2_PD1      SILABS_DBUS_MODEM_ANTRR2(0x3, 0x1)
+#define MODEM_ANTRR2_PD2      SILABS_DBUS_MODEM_ANTRR2(0x3, 0x2)
+#define MODEM_ANTRR2_PD3      SILABS_DBUS_MODEM_ANTRR2(0x3, 0x3)
+#define MODEM_ANTRR3_PC0      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x0)
+#define MODEM_ANTRR3_PC1      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x1)
+#define MODEM_ANTRR3_PC2      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x2)
+#define MODEM_ANTRR3_PC3      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x3)
+#define MODEM_ANTRR3_PC4      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x4)
+#define MODEM_ANTRR3_PC5      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x5)
+#define MODEM_ANTRR3_PC6      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x6)
+#define MODEM_ANTRR3_PC7      SILABS_DBUS_MODEM_ANTRR3(0x2, 0x7)
+#define MODEM_ANTRR3_PD0      SILABS_DBUS_MODEM_ANTRR3(0x3, 0x0)
+#define MODEM_ANTRR3_PD1      SILABS_DBUS_MODEM_ANTRR3(0x3, 0x1)
+#define MODEM_ANTRR3_PD2      SILABS_DBUS_MODEM_ANTRR3(0x3, 0x2)
+#define MODEM_ANTRR3_PD3      SILABS_DBUS_MODEM_ANTRR3(0x3, 0x3)
+#define MODEM_ANTRR4_PC0      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x0)
+#define MODEM_ANTRR4_PC1      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x1)
+#define MODEM_ANTRR4_PC2      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x2)
+#define MODEM_ANTRR4_PC3      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x3)
+#define MODEM_ANTRR4_PC4      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x4)
+#define MODEM_ANTRR4_PC5      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x5)
+#define MODEM_ANTRR4_PC6      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x6)
+#define MODEM_ANTRR4_PC7      SILABS_DBUS_MODEM_ANTRR4(0x2, 0x7)
+#define MODEM_ANTRR4_PD0      SILABS_DBUS_MODEM_ANTRR4(0x3, 0x0)
+#define MODEM_ANTRR4_PD1      SILABS_DBUS_MODEM_ANTRR4(0x3, 0x1)
+#define MODEM_ANTRR4_PD2      SILABS_DBUS_MODEM_ANTRR4(0x3, 0x2)
+#define MODEM_ANTRR4_PD3      SILABS_DBUS_MODEM_ANTRR4(0x3, 0x3)
+#define MODEM_ANTRR5_PC0      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x0)
+#define MODEM_ANTRR5_PC1      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x1)
+#define MODEM_ANTRR5_PC2      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x2)
+#define MODEM_ANTRR5_PC3      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x3)
+#define MODEM_ANTRR5_PC4      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x4)
+#define MODEM_ANTRR5_PC5      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x5)
+#define MODEM_ANTRR5_PC6      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x6)
+#define MODEM_ANTRR5_PC7      SILABS_DBUS_MODEM_ANTRR5(0x2, 0x7)
+#define MODEM_ANTRR5_PD0      SILABS_DBUS_MODEM_ANTRR5(0x3, 0x0)
+#define MODEM_ANTRR5_PD1      SILABS_DBUS_MODEM_ANTRR5(0x3, 0x1)
+#define MODEM_ANTRR5_PD2      SILABS_DBUS_MODEM_ANTRR5(0x3, 0x2)
+#define MODEM_ANTRR5_PD3      SILABS_DBUS_MODEM_ANTRR5(0x3, 0x3)
+#define MODEM_ANTSWEN_PC0     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x0)
+#define MODEM_ANTSWEN_PC1     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x1)
+#define MODEM_ANTSWEN_PC2     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x2)
+#define MODEM_ANTSWEN_PC3     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x3)
+#define MODEM_ANTSWEN_PC4     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x4)
+#define MODEM_ANTSWEN_PC5     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x5)
+#define MODEM_ANTSWEN_PC6     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x6)
+#define MODEM_ANTSWEN_PC7     SILABS_DBUS_MODEM_ANTSWEN(0x2, 0x7)
+#define MODEM_ANTSWEN_PD0     SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x0)
+#define MODEM_ANTSWEN_PD1     SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x1)
+#define MODEM_ANTSWEN_PD2     SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x2)
+#define MODEM_ANTSWEN_PD3     SILABS_DBUS_MODEM_ANTSWEN(0x3, 0x3)
+#define MODEM_ANTSWUS_PC0     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x0)
+#define MODEM_ANTSWUS_PC1     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x1)
+#define MODEM_ANTSWUS_PC2     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x2)
+#define MODEM_ANTSWUS_PC3     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x3)
+#define MODEM_ANTSWUS_PC4     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x4)
+#define MODEM_ANTSWUS_PC5     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x5)
+#define MODEM_ANTSWUS_PC6     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x6)
+#define MODEM_ANTSWUS_PC7     SILABS_DBUS_MODEM_ANTSWUS(0x2, 0x7)
+#define MODEM_ANTSWUS_PD0     SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x0)
+#define MODEM_ANTSWUS_PD1     SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x1)
+#define MODEM_ANTSWUS_PD2     SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x2)
+#define MODEM_ANTSWUS_PD3     SILABS_DBUS_MODEM_ANTSWUS(0x3, 0x3)
+#define MODEM_ANTTRIG_PC0     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x0)
+#define MODEM_ANTTRIG_PC1     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x1)
+#define MODEM_ANTTRIG_PC2     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x2)
+#define MODEM_ANTTRIG_PC3     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x3)
+#define MODEM_ANTTRIG_PC4     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x4)
+#define MODEM_ANTTRIG_PC5     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x5)
+#define MODEM_ANTTRIG_PC6     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x6)
+#define MODEM_ANTTRIG_PC7     SILABS_DBUS_MODEM_ANTTRIG(0x2, 0x7)
+#define MODEM_ANTTRIG_PD0     SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x0)
+#define MODEM_ANTTRIG_PD1     SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x1)
+#define MODEM_ANTTRIG_PD2     SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x2)
+#define MODEM_ANTTRIG_PD3     SILABS_DBUS_MODEM_ANTTRIG(0x3, 0x3)
+#define MODEM_ANTTRIGSTOP_PC0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x0)
+#define MODEM_ANTTRIGSTOP_PC1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x1)
+#define MODEM_ANTTRIGSTOP_PC2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x2)
+#define MODEM_ANTTRIGSTOP_PC3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x3)
+#define MODEM_ANTTRIGSTOP_PC4 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x4)
+#define MODEM_ANTTRIGSTOP_PC5 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x5)
+#define MODEM_ANTTRIGSTOP_PC6 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x6)
+#define MODEM_ANTTRIGSTOP_PC7 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x2, 0x7)
+#define MODEM_ANTTRIGSTOP_PD0 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x0)
+#define MODEM_ANTTRIGSTOP_PD1 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x1)
+#define MODEM_ANTTRIGSTOP_PD2 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x2)
+#define MODEM_ANTTRIGSTOP_PD3 SILABS_DBUS_MODEM_ANTTRIGSTOP(0x3, 0x3)
+#define MODEM_DCLK_PA0        SILABS_DBUS_MODEM_DCLK(0x0, 0x0)
+#define MODEM_DCLK_PA1        SILABS_DBUS_MODEM_DCLK(0x0, 0x1)
+#define MODEM_DCLK_PA2        SILABS_DBUS_MODEM_DCLK(0x0, 0x2)
+#define MODEM_DCLK_PA3        SILABS_DBUS_MODEM_DCLK(0x0, 0x3)
+#define MODEM_DCLK_PA4        SILABS_DBUS_MODEM_DCLK(0x0, 0x4)
+#define MODEM_DCLK_PA5        SILABS_DBUS_MODEM_DCLK(0x0, 0x5)
+#define MODEM_DCLK_PA6        SILABS_DBUS_MODEM_DCLK(0x0, 0x6)
+#define MODEM_DCLK_PA7        SILABS_DBUS_MODEM_DCLK(0x0, 0x7)
+#define MODEM_DCLK_PA8        SILABS_DBUS_MODEM_DCLK(0x0, 0x8)
+#define MODEM_DCLK_PB0        SILABS_DBUS_MODEM_DCLK(0x1, 0x0)
+#define MODEM_DCLK_PB1        SILABS_DBUS_MODEM_DCLK(0x1, 0x1)
+#define MODEM_DCLK_PB2        SILABS_DBUS_MODEM_DCLK(0x1, 0x2)
+#define MODEM_DCLK_PB3        SILABS_DBUS_MODEM_DCLK(0x1, 0x3)
+#define MODEM_DCLK_PB4        SILABS_DBUS_MODEM_DCLK(0x1, 0x4)
+#define MODEM_DOUT_PA0        SILABS_DBUS_MODEM_DOUT(0x0, 0x0)
+#define MODEM_DOUT_PA1        SILABS_DBUS_MODEM_DOUT(0x0, 0x1)
+#define MODEM_DOUT_PA2        SILABS_DBUS_MODEM_DOUT(0x0, 0x2)
+#define MODEM_DOUT_PA3        SILABS_DBUS_MODEM_DOUT(0x0, 0x3)
+#define MODEM_DOUT_PA4        SILABS_DBUS_MODEM_DOUT(0x0, 0x4)
+#define MODEM_DOUT_PA5        SILABS_DBUS_MODEM_DOUT(0x0, 0x5)
+#define MODEM_DOUT_PA6        SILABS_DBUS_MODEM_DOUT(0x0, 0x6)
+#define MODEM_DOUT_PA7        SILABS_DBUS_MODEM_DOUT(0x0, 0x7)
+#define MODEM_DOUT_PA8        SILABS_DBUS_MODEM_DOUT(0x0, 0x8)
+#define MODEM_DOUT_PB0        SILABS_DBUS_MODEM_DOUT(0x1, 0x0)
+#define MODEM_DOUT_PB1        SILABS_DBUS_MODEM_DOUT(0x1, 0x1)
+#define MODEM_DOUT_PB2        SILABS_DBUS_MODEM_DOUT(0x1, 0x2)
+#define MODEM_DOUT_PB3        SILABS_DBUS_MODEM_DOUT(0x1, 0x3)
+#define MODEM_DOUT_PB4        SILABS_DBUS_MODEM_DOUT(0x1, 0x4)
+#define MODEM_DIN_PA0         SILABS_DBUS_MODEM_DIN(0x0, 0x0)
+#define MODEM_DIN_PA1         SILABS_DBUS_MODEM_DIN(0x0, 0x1)
+#define MODEM_DIN_PA2         SILABS_DBUS_MODEM_DIN(0x0, 0x2)
+#define MODEM_DIN_PA3         SILABS_DBUS_MODEM_DIN(0x0, 0x3)
+#define MODEM_DIN_PA4         SILABS_DBUS_MODEM_DIN(0x0, 0x4)
+#define MODEM_DIN_PA5         SILABS_DBUS_MODEM_DIN(0x0, 0x5)
+#define MODEM_DIN_PA6         SILABS_DBUS_MODEM_DIN(0x0, 0x6)
+#define MODEM_DIN_PA7         SILABS_DBUS_MODEM_DIN(0x0, 0x7)
+#define MODEM_DIN_PA8         SILABS_DBUS_MODEM_DIN(0x0, 0x8)
+#define MODEM_DIN_PB0         SILABS_DBUS_MODEM_DIN(0x1, 0x0)
+#define MODEM_DIN_PB1         SILABS_DBUS_MODEM_DIN(0x1, 0x1)
+#define MODEM_DIN_PB2         SILABS_DBUS_MODEM_DIN(0x1, 0x2)
+#define MODEM_DIN_PB3         SILABS_DBUS_MODEM_DIN(0x1, 0x3)
+#define MODEM_DIN_PB4         SILABS_DBUS_MODEM_DIN(0x1, 0x4)
+
+#define PDM_CLK_PA0  SILABS_DBUS_PDM_CLK(0x0, 0x0)
+#define PDM_CLK_PA1  SILABS_DBUS_PDM_CLK(0x0, 0x1)
+#define PDM_CLK_PA2  SILABS_DBUS_PDM_CLK(0x0, 0x2)
+#define PDM_CLK_PA3  SILABS_DBUS_PDM_CLK(0x0, 0x3)
+#define PDM_CLK_PA4  SILABS_DBUS_PDM_CLK(0x0, 0x4)
+#define PDM_CLK_PA5  SILABS_DBUS_PDM_CLK(0x0, 0x5)
+#define PDM_CLK_PA6  SILABS_DBUS_PDM_CLK(0x0, 0x6)
+#define PDM_CLK_PA7  SILABS_DBUS_PDM_CLK(0x0, 0x7)
+#define PDM_CLK_PA8  SILABS_DBUS_PDM_CLK(0x0, 0x8)
+#define PDM_CLK_PB0  SILABS_DBUS_PDM_CLK(0x1, 0x0)
+#define PDM_CLK_PB1  SILABS_DBUS_PDM_CLK(0x1, 0x1)
+#define PDM_CLK_PB2  SILABS_DBUS_PDM_CLK(0x1, 0x2)
+#define PDM_CLK_PB3  SILABS_DBUS_PDM_CLK(0x1, 0x3)
+#define PDM_CLK_PB4  SILABS_DBUS_PDM_CLK(0x1, 0x4)
+#define PDM_CLK_PC0  SILABS_DBUS_PDM_CLK(0x2, 0x0)
+#define PDM_CLK_PC1  SILABS_DBUS_PDM_CLK(0x2, 0x1)
+#define PDM_CLK_PC2  SILABS_DBUS_PDM_CLK(0x2, 0x2)
+#define PDM_CLK_PC3  SILABS_DBUS_PDM_CLK(0x2, 0x3)
+#define PDM_CLK_PC4  SILABS_DBUS_PDM_CLK(0x2, 0x4)
+#define PDM_CLK_PC5  SILABS_DBUS_PDM_CLK(0x2, 0x5)
+#define PDM_CLK_PC6  SILABS_DBUS_PDM_CLK(0x2, 0x6)
+#define PDM_CLK_PC7  SILABS_DBUS_PDM_CLK(0x2, 0x7)
+#define PDM_CLK_PD0  SILABS_DBUS_PDM_CLK(0x3, 0x0)
+#define PDM_CLK_PD1  SILABS_DBUS_PDM_CLK(0x3, 0x1)
+#define PDM_CLK_PD2  SILABS_DBUS_PDM_CLK(0x3, 0x2)
+#define PDM_CLK_PD3  SILABS_DBUS_PDM_CLK(0x3, 0x3)
+#define PDM_DAT0_PA0 SILABS_DBUS_PDM_DAT0(0x0, 0x0)
+#define PDM_DAT0_PA1 SILABS_DBUS_PDM_DAT0(0x0, 0x1)
+#define PDM_DAT0_PA2 SILABS_DBUS_PDM_DAT0(0x0, 0x2)
+#define PDM_DAT0_PA3 SILABS_DBUS_PDM_DAT0(0x0, 0x3)
+#define PDM_DAT0_PA4 SILABS_DBUS_PDM_DAT0(0x0, 0x4)
+#define PDM_DAT0_PA5 SILABS_DBUS_PDM_DAT0(0x0, 0x5)
+#define PDM_DAT0_PA6 SILABS_DBUS_PDM_DAT0(0x0, 0x6)
+#define PDM_DAT0_PA7 SILABS_DBUS_PDM_DAT0(0x0, 0x7)
+#define PDM_DAT0_PA8 SILABS_DBUS_PDM_DAT0(0x0, 0x8)
+#define PDM_DAT0_PB0 SILABS_DBUS_PDM_DAT0(0x1, 0x0)
+#define PDM_DAT0_PB1 SILABS_DBUS_PDM_DAT0(0x1, 0x1)
+#define PDM_DAT0_PB2 SILABS_DBUS_PDM_DAT0(0x1, 0x2)
+#define PDM_DAT0_PB3 SILABS_DBUS_PDM_DAT0(0x1, 0x3)
+#define PDM_DAT0_PB4 SILABS_DBUS_PDM_DAT0(0x1, 0x4)
+#define PDM_DAT0_PC0 SILABS_DBUS_PDM_DAT0(0x2, 0x0)
+#define PDM_DAT0_PC1 SILABS_DBUS_PDM_DAT0(0x2, 0x1)
+#define PDM_DAT0_PC2 SILABS_DBUS_PDM_DAT0(0x2, 0x2)
+#define PDM_DAT0_PC3 SILABS_DBUS_PDM_DAT0(0x2, 0x3)
+#define PDM_DAT0_PC4 SILABS_DBUS_PDM_DAT0(0x2, 0x4)
+#define PDM_DAT0_PC5 SILABS_DBUS_PDM_DAT0(0x2, 0x5)
+#define PDM_DAT0_PC6 SILABS_DBUS_PDM_DAT0(0x2, 0x6)
+#define PDM_DAT0_PC7 SILABS_DBUS_PDM_DAT0(0x2, 0x7)
+#define PDM_DAT0_PD0 SILABS_DBUS_PDM_DAT0(0x3, 0x0)
+#define PDM_DAT0_PD1 SILABS_DBUS_PDM_DAT0(0x3, 0x1)
+#define PDM_DAT0_PD2 SILABS_DBUS_PDM_DAT0(0x3, 0x2)
+#define PDM_DAT0_PD3 SILABS_DBUS_PDM_DAT0(0x3, 0x3)
+#define PDM_DAT1_PA0 SILABS_DBUS_PDM_DAT1(0x0, 0x0)
+#define PDM_DAT1_PA1 SILABS_DBUS_PDM_DAT1(0x0, 0x1)
+#define PDM_DAT1_PA2 SILABS_DBUS_PDM_DAT1(0x0, 0x2)
+#define PDM_DAT1_PA3 SILABS_DBUS_PDM_DAT1(0x0, 0x3)
+#define PDM_DAT1_PA4 SILABS_DBUS_PDM_DAT1(0x0, 0x4)
+#define PDM_DAT1_PA5 SILABS_DBUS_PDM_DAT1(0x0, 0x5)
+#define PDM_DAT1_PA6 SILABS_DBUS_PDM_DAT1(0x0, 0x6)
+#define PDM_DAT1_PA7 SILABS_DBUS_PDM_DAT1(0x0, 0x7)
+#define PDM_DAT1_PA8 SILABS_DBUS_PDM_DAT1(0x0, 0x8)
+#define PDM_DAT1_PB0 SILABS_DBUS_PDM_DAT1(0x1, 0x0)
+#define PDM_DAT1_PB1 SILABS_DBUS_PDM_DAT1(0x1, 0x1)
+#define PDM_DAT1_PB2 SILABS_DBUS_PDM_DAT1(0x1, 0x2)
+#define PDM_DAT1_PB3 SILABS_DBUS_PDM_DAT1(0x1, 0x3)
+#define PDM_DAT1_PB4 SILABS_DBUS_PDM_DAT1(0x1, 0x4)
+#define PDM_DAT1_PC0 SILABS_DBUS_PDM_DAT1(0x2, 0x0)
+#define PDM_DAT1_PC1 SILABS_DBUS_PDM_DAT1(0x2, 0x1)
+#define PDM_DAT1_PC2 SILABS_DBUS_PDM_DAT1(0x2, 0x2)
+#define PDM_DAT1_PC3 SILABS_DBUS_PDM_DAT1(0x2, 0x3)
+#define PDM_DAT1_PC4 SILABS_DBUS_PDM_DAT1(0x2, 0x4)
+#define PDM_DAT1_PC5 SILABS_DBUS_PDM_DAT1(0x2, 0x5)
+#define PDM_DAT1_PC6 SILABS_DBUS_PDM_DAT1(0x2, 0x6)
+#define PDM_DAT1_PC7 SILABS_DBUS_PDM_DAT1(0x2, 0x7)
+#define PDM_DAT1_PD0 SILABS_DBUS_PDM_DAT1(0x3, 0x0)
+#define PDM_DAT1_PD1 SILABS_DBUS_PDM_DAT1(0x3, 0x1)
+#define PDM_DAT1_PD2 SILABS_DBUS_PDM_DAT1(0x3, 0x2)
+#define PDM_DAT1_PD3 SILABS_DBUS_PDM_DAT1(0x3, 0x3)
+
+#define PRS0_ASYNCH0_PA0  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x0)
+#define PRS0_ASYNCH0_PA1  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x1)
+#define PRS0_ASYNCH0_PA2  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x2)
+#define PRS0_ASYNCH0_PA3  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x3)
+#define PRS0_ASYNCH0_PA4  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x4)
+#define PRS0_ASYNCH0_PA5  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x5)
+#define PRS0_ASYNCH0_PA6  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x6)
+#define PRS0_ASYNCH0_PA7  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x7)
+#define PRS0_ASYNCH0_PA8  SILABS_DBUS_PRS0_ASYNCH0(0x0, 0x8)
+#define PRS0_ASYNCH0_PB0  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x0)
+#define PRS0_ASYNCH0_PB1  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x1)
+#define PRS0_ASYNCH0_PB2  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x2)
+#define PRS0_ASYNCH0_PB3  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x3)
+#define PRS0_ASYNCH0_PB4  SILABS_DBUS_PRS0_ASYNCH0(0x1, 0x4)
+#define PRS0_ASYNCH1_PA0  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x0)
+#define PRS0_ASYNCH1_PA1  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x1)
+#define PRS0_ASYNCH1_PA2  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x2)
+#define PRS0_ASYNCH1_PA3  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x3)
+#define PRS0_ASYNCH1_PA4  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x4)
+#define PRS0_ASYNCH1_PA5  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x5)
+#define PRS0_ASYNCH1_PA6  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x6)
+#define PRS0_ASYNCH1_PA7  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x7)
+#define PRS0_ASYNCH1_PA8  SILABS_DBUS_PRS0_ASYNCH1(0x0, 0x8)
+#define PRS0_ASYNCH1_PB0  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x0)
+#define PRS0_ASYNCH1_PB1  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x1)
+#define PRS0_ASYNCH1_PB2  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x2)
+#define PRS0_ASYNCH1_PB3  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x3)
+#define PRS0_ASYNCH1_PB4  SILABS_DBUS_PRS0_ASYNCH1(0x1, 0x4)
+#define PRS0_ASYNCH2_PA0  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x0)
+#define PRS0_ASYNCH2_PA1  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x1)
+#define PRS0_ASYNCH2_PA2  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x2)
+#define PRS0_ASYNCH2_PA3  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x3)
+#define PRS0_ASYNCH2_PA4  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x4)
+#define PRS0_ASYNCH2_PA5  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x5)
+#define PRS0_ASYNCH2_PA6  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x6)
+#define PRS0_ASYNCH2_PA7  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x7)
+#define PRS0_ASYNCH2_PA8  SILABS_DBUS_PRS0_ASYNCH2(0x0, 0x8)
+#define PRS0_ASYNCH2_PB0  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x0)
+#define PRS0_ASYNCH2_PB1  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x1)
+#define PRS0_ASYNCH2_PB2  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x2)
+#define PRS0_ASYNCH2_PB3  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x3)
+#define PRS0_ASYNCH2_PB4  SILABS_DBUS_PRS0_ASYNCH2(0x1, 0x4)
+#define PRS0_ASYNCH3_PA0  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x0)
+#define PRS0_ASYNCH3_PA1  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x1)
+#define PRS0_ASYNCH3_PA2  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x2)
+#define PRS0_ASYNCH3_PA3  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x3)
+#define PRS0_ASYNCH3_PA4  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x4)
+#define PRS0_ASYNCH3_PA5  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x5)
+#define PRS0_ASYNCH3_PA6  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x6)
+#define PRS0_ASYNCH3_PA7  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x7)
+#define PRS0_ASYNCH3_PA8  SILABS_DBUS_PRS0_ASYNCH3(0x0, 0x8)
+#define PRS0_ASYNCH3_PB0  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x0)
+#define PRS0_ASYNCH3_PB1  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x1)
+#define PRS0_ASYNCH3_PB2  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x2)
+#define PRS0_ASYNCH3_PB3  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x3)
+#define PRS0_ASYNCH3_PB4  SILABS_DBUS_PRS0_ASYNCH3(0x1, 0x4)
+#define PRS0_ASYNCH4_PA0  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x0)
+#define PRS0_ASYNCH4_PA1  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x1)
+#define PRS0_ASYNCH4_PA2  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x2)
+#define PRS0_ASYNCH4_PA3  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x3)
+#define PRS0_ASYNCH4_PA4  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x4)
+#define PRS0_ASYNCH4_PA5  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x5)
+#define PRS0_ASYNCH4_PA6  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x6)
+#define PRS0_ASYNCH4_PA7  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x7)
+#define PRS0_ASYNCH4_PA8  SILABS_DBUS_PRS0_ASYNCH4(0x0, 0x8)
+#define PRS0_ASYNCH4_PB0  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x0)
+#define PRS0_ASYNCH4_PB1  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x1)
+#define PRS0_ASYNCH4_PB2  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x2)
+#define PRS0_ASYNCH4_PB3  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x3)
+#define PRS0_ASYNCH4_PB4  SILABS_DBUS_PRS0_ASYNCH4(0x1, 0x4)
+#define PRS0_ASYNCH5_PA0  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x0)
+#define PRS0_ASYNCH5_PA1  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x1)
+#define PRS0_ASYNCH5_PA2  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x2)
+#define PRS0_ASYNCH5_PA3  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x3)
+#define PRS0_ASYNCH5_PA4  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x4)
+#define PRS0_ASYNCH5_PA5  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x5)
+#define PRS0_ASYNCH5_PA6  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x6)
+#define PRS0_ASYNCH5_PA7  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x7)
+#define PRS0_ASYNCH5_PA8  SILABS_DBUS_PRS0_ASYNCH5(0x0, 0x8)
+#define PRS0_ASYNCH5_PB0  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x0)
+#define PRS0_ASYNCH5_PB1  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x1)
+#define PRS0_ASYNCH5_PB2  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x2)
+#define PRS0_ASYNCH5_PB3  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x3)
+#define PRS0_ASYNCH5_PB4  SILABS_DBUS_PRS0_ASYNCH5(0x1, 0x4)
+#define PRS0_ASYNCH6_PC0  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x0)
+#define PRS0_ASYNCH6_PC1  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x1)
+#define PRS0_ASYNCH6_PC2  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x2)
+#define PRS0_ASYNCH6_PC3  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x3)
+#define PRS0_ASYNCH6_PC4  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x4)
+#define PRS0_ASYNCH6_PC5  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x5)
+#define PRS0_ASYNCH6_PC6  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x6)
+#define PRS0_ASYNCH6_PC7  SILABS_DBUS_PRS0_ASYNCH6(0x2, 0x7)
+#define PRS0_ASYNCH6_PD0  SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x0)
+#define PRS0_ASYNCH6_PD1  SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x1)
+#define PRS0_ASYNCH6_PD2  SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x2)
+#define PRS0_ASYNCH6_PD3  SILABS_DBUS_PRS0_ASYNCH6(0x3, 0x3)
+#define PRS0_ASYNCH7_PC0  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x0)
+#define PRS0_ASYNCH7_PC1  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x1)
+#define PRS0_ASYNCH7_PC2  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x2)
+#define PRS0_ASYNCH7_PC3  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x3)
+#define PRS0_ASYNCH7_PC4  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x4)
+#define PRS0_ASYNCH7_PC5  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x5)
+#define PRS0_ASYNCH7_PC6  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x6)
+#define PRS0_ASYNCH7_PC7  SILABS_DBUS_PRS0_ASYNCH7(0x2, 0x7)
+#define PRS0_ASYNCH7_PD0  SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x0)
+#define PRS0_ASYNCH7_PD1  SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x1)
+#define PRS0_ASYNCH7_PD2  SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x2)
+#define PRS0_ASYNCH7_PD3  SILABS_DBUS_PRS0_ASYNCH7(0x3, 0x3)
+#define PRS0_ASYNCH8_PC0  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x0)
+#define PRS0_ASYNCH8_PC1  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x1)
+#define PRS0_ASYNCH8_PC2  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x2)
+#define PRS0_ASYNCH8_PC3  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x3)
+#define PRS0_ASYNCH8_PC4  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x4)
+#define PRS0_ASYNCH8_PC5  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x5)
+#define PRS0_ASYNCH8_PC6  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x6)
+#define PRS0_ASYNCH8_PC7  SILABS_DBUS_PRS0_ASYNCH8(0x2, 0x7)
+#define PRS0_ASYNCH8_PD0  SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x0)
+#define PRS0_ASYNCH8_PD1  SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x1)
+#define PRS0_ASYNCH8_PD2  SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x2)
+#define PRS0_ASYNCH8_PD3  SILABS_DBUS_PRS0_ASYNCH8(0x3, 0x3)
+#define PRS0_ASYNCH9_PC0  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x0)
+#define PRS0_ASYNCH9_PC1  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x1)
+#define PRS0_ASYNCH9_PC2  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x2)
+#define PRS0_ASYNCH9_PC3  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x3)
+#define PRS0_ASYNCH9_PC4  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x4)
+#define PRS0_ASYNCH9_PC5  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x5)
+#define PRS0_ASYNCH9_PC6  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x6)
+#define PRS0_ASYNCH9_PC7  SILABS_DBUS_PRS0_ASYNCH9(0x2, 0x7)
+#define PRS0_ASYNCH9_PD0  SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x0)
+#define PRS0_ASYNCH9_PD1  SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x1)
+#define PRS0_ASYNCH9_PD2  SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x2)
+#define PRS0_ASYNCH9_PD3  SILABS_DBUS_PRS0_ASYNCH9(0x3, 0x3)
+#define PRS0_ASYNCH10_PC0 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x0)
+#define PRS0_ASYNCH10_PC1 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x1)
+#define PRS0_ASYNCH10_PC2 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x2)
+#define PRS0_ASYNCH10_PC3 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x3)
+#define PRS0_ASYNCH10_PC4 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x4)
+#define PRS0_ASYNCH10_PC5 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x5)
+#define PRS0_ASYNCH10_PC6 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x6)
+#define PRS0_ASYNCH10_PC7 SILABS_DBUS_PRS0_ASYNCH10(0x2, 0x7)
+#define PRS0_ASYNCH10_PD0 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x0)
+#define PRS0_ASYNCH10_PD1 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x1)
+#define PRS0_ASYNCH10_PD2 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x2)
+#define PRS0_ASYNCH10_PD3 SILABS_DBUS_PRS0_ASYNCH10(0x3, 0x3)
+#define PRS0_ASYNCH11_PC0 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x0)
+#define PRS0_ASYNCH11_PC1 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x1)
+#define PRS0_ASYNCH11_PC2 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x2)
+#define PRS0_ASYNCH11_PC3 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x3)
+#define PRS0_ASYNCH11_PC4 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x4)
+#define PRS0_ASYNCH11_PC5 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x5)
+#define PRS0_ASYNCH11_PC6 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x6)
+#define PRS0_ASYNCH11_PC7 SILABS_DBUS_PRS0_ASYNCH11(0x2, 0x7)
+#define PRS0_ASYNCH11_PD0 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x0)
+#define PRS0_ASYNCH11_PD1 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x1)
+#define PRS0_ASYNCH11_PD2 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x2)
+#define PRS0_ASYNCH11_PD3 SILABS_DBUS_PRS0_ASYNCH11(0x3, 0x3)
+#define PRS0_SYNCH0_PA0   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x0)
+#define PRS0_SYNCH0_PA1   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x1)
+#define PRS0_SYNCH0_PA2   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x2)
+#define PRS0_SYNCH0_PA3   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x3)
+#define PRS0_SYNCH0_PA4   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x4)
+#define PRS0_SYNCH0_PA5   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x5)
+#define PRS0_SYNCH0_PA6   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x6)
+#define PRS0_SYNCH0_PA7   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x7)
+#define PRS0_SYNCH0_PA8   SILABS_DBUS_PRS0_SYNCH0(0x0, 0x8)
+#define PRS0_SYNCH0_PB0   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x0)
+#define PRS0_SYNCH0_PB1   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x1)
+#define PRS0_SYNCH0_PB2   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x2)
+#define PRS0_SYNCH0_PB3   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x3)
+#define PRS0_SYNCH0_PB4   SILABS_DBUS_PRS0_SYNCH0(0x1, 0x4)
+#define PRS0_SYNCH0_PC0   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x0)
+#define PRS0_SYNCH0_PC1   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x1)
+#define PRS0_SYNCH0_PC2   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x2)
+#define PRS0_SYNCH0_PC3   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x3)
+#define PRS0_SYNCH0_PC4   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x4)
+#define PRS0_SYNCH0_PC5   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x5)
+#define PRS0_SYNCH0_PC6   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x6)
+#define PRS0_SYNCH0_PC7   SILABS_DBUS_PRS0_SYNCH0(0x2, 0x7)
+#define PRS0_SYNCH0_PD0   SILABS_DBUS_PRS0_SYNCH0(0x3, 0x0)
+#define PRS0_SYNCH0_PD1   SILABS_DBUS_PRS0_SYNCH0(0x3, 0x1)
+#define PRS0_SYNCH0_PD2   SILABS_DBUS_PRS0_SYNCH0(0x3, 0x2)
+#define PRS0_SYNCH0_PD3   SILABS_DBUS_PRS0_SYNCH0(0x3, 0x3)
+#define PRS0_SYNCH1_PA0   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x0)
+#define PRS0_SYNCH1_PA1   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x1)
+#define PRS0_SYNCH1_PA2   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x2)
+#define PRS0_SYNCH1_PA3   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x3)
+#define PRS0_SYNCH1_PA4   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x4)
+#define PRS0_SYNCH1_PA5   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x5)
+#define PRS0_SYNCH1_PA6   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x6)
+#define PRS0_SYNCH1_PA7   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x7)
+#define PRS0_SYNCH1_PA8   SILABS_DBUS_PRS0_SYNCH1(0x0, 0x8)
+#define PRS0_SYNCH1_PB0   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x0)
+#define PRS0_SYNCH1_PB1   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x1)
+#define PRS0_SYNCH1_PB2   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x2)
+#define PRS0_SYNCH1_PB3   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x3)
+#define PRS0_SYNCH1_PB4   SILABS_DBUS_PRS0_SYNCH1(0x1, 0x4)
+#define PRS0_SYNCH1_PC0   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x0)
+#define PRS0_SYNCH1_PC1   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x1)
+#define PRS0_SYNCH1_PC2   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x2)
+#define PRS0_SYNCH1_PC3   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x3)
+#define PRS0_SYNCH1_PC4   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x4)
+#define PRS0_SYNCH1_PC5   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x5)
+#define PRS0_SYNCH1_PC6   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x6)
+#define PRS0_SYNCH1_PC7   SILABS_DBUS_PRS0_SYNCH1(0x2, 0x7)
+#define PRS0_SYNCH1_PD0   SILABS_DBUS_PRS0_SYNCH1(0x3, 0x0)
+#define PRS0_SYNCH1_PD1   SILABS_DBUS_PRS0_SYNCH1(0x3, 0x1)
+#define PRS0_SYNCH1_PD2   SILABS_DBUS_PRS0_SYNCH1(0x3, 0x2)
+#define PRS0_SYNCH1_PD3   SILABS_DBUS_PRS0_SYNCH1(0x3, 0x3)
+#define PRS0_SYNCH2_PA0   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x0)
+#define PRS0_SYNCH2_PA1   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x1)
+#define PRS0_SYNCH2_PA2   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x2)
+#define PRS0_SYNCH2_PA3   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x3)
+#define PRS0_SYNCH2_PA4   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x4)
+#define PRS0_SYNCH2_PA5   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x5)
+#define PRS0_SYNCH2_PA6   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x6)
+#define PRS0_SYNCH2_PA7   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x7)
+#define PRS0_SYNCH2_PA8   SILABS_DBUS_PRS0_SYNCH2(0x0, 0x8)
+#define PRS0_SYNCH2_PB0   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x0)
+#define PRS0_SYNCH2_PB1   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x1)
+#define PRS0_SYNCH2_PB2   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x2)
+#define PRS0_SYNCH2_PB3   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x3)
+#define PRS0_SYNCH2_PB4   SILABS_DBUS_PRS0_SYNCH2(0x1, 0x4)
+#define PRS0_SYNCH2_PC0   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x0)
+#define PRS0_SYNCH2_PC1   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x1)
+#define PRS0_SYNCH2_PC2   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x2)
+#define PRS0_SYNCH2_PC3   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x3)
+#define PRS0_SYNCH2_PC4   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x4)
+#define PRS0_SYNCH2_PC5   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x5)
+#define PRS0_SYNCH2_PC6   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x6)
+#define PRS0_SYNCH2_PC7   SILABS_DBUS_PRS0_SYNCH2(0x2, 0x7)
+#define PRS0_SYNCH2_PD0   SILABS_DBUS_PRS0_SYNCH2(0x3, 0x0)
+#define PRS0_SYNCH2_PD1   SILABS_DBUS_PRS0_SYNCH2(0x3, 0x1)
+#define PRS0_SYNCH2_PD2   SILABS_DBUS_PRS0_SYNCH2(0x3, 0x2)
+#define PRS0_SYNCH2_PD3   SILABS_DBUS_PRS0_SYNCH2(0x3, 0x3)
+#define PRS0_SYNCH3_PA0   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x0)
+#define PRS0_SYNCH3_PA1   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x1)
+#define PRS0_SYNCH3_PA2   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x2)
+#define PRS0_SYNCH3_PA3   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x3)
+#define PRS0_SYNCH3_PA4   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x4)
+#define PRS0_SYNCH3_PA5   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x5)
+#define PRS0_SYNCH3_PA6   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x6)
+#define PRS0_SYNCH3_PA7   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x7)
+#define PRS0_SYNCH3_PA8   SILABS_DBUS_PRS0_SYNCH3(0x0, 0x8)
+#define PRS0_SYNCH3_PB0   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x0)
+#define PRS0_SYNCH3_PB1   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x1)
+#define PRS0_SYNCH3_PB2   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x2)
+#define PRS0_SYNCH3_PB3   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x3)
+#define PRS0_SYNCH3_PB4   SILABS_DBUS_PRS0_SYNCH3(0x1, 0x4)
+#define PRS0_SYNCH3_PC0   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x0)
+#define PRS0_SYNCH3_PC1   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x1)
+#define PRS0_SYNCH3_PC2   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x2)
+#define PRS0_SYNCH3_PC3   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x3)
+#define PRS0_SYNCH3_PC4   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x4)
+#define PRS0_SYNCH3_PC5   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x5)
+#define PRS0_SYNCH3_PC6   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x6)
+#define PRS0_SYNCH3_PC7   SILABS_DBUS_PRS0_SYNCH3(0x2, 0x7)
+#define PRS0_SYNCH3_PD0   SILABS_DBUS_PRS0_SYNCH3(0x3, 0x0)
+#define PRS0_SYNCH3_PD1   SILABS_DBUS_PRS0_SYNCH3(0x3, 0x1)
+#define PRS0_SYNCH3_PD2   SILABS_DBUS_PRS0_SYNCH3(0x3, 0x2)
+#define PRS0_SYNCH3_PD3   SILABS_DBUS_PRS0_SYNCH3(0x3, 0x3)
+
+#define TIMER0_CC0_PA0   SILABS_DBUS_TIMER0_CC0(0x0, 0x0)
+#define TIMER0_CC0_PA1   SILABS_DBUS_TIMER0_CC0(0x0, 0x1)
+#define TIMER0_CC0_PA2   SILABS_DBUS_TIMER0_CC0(0x0, 0x2)
+#define TIMER0_CC0_PA3   SILABS_DBUS_TIMER0_CC0(0x0, 0x3)
+#define TIMER0_CC0_PA4   SILABS_DBUS_TIMER0_CC0(0x0, 0x4)
+#define TIMER0_CC0_PA5   SILABS_DBUS_TIMER0_CC0(0x0, 0x5)
+#define TIMER0_CC0_PA6   SILABS_DBUS_TIMER0_CC0(0x0, 0x6)
+#define TIMER0_CC0_PA7   SILABS_DBUS_TIMER0_CC0(0x0, 0x7)
+#define TIMER0_CC0_PA8   SILABS_DBUS_TIMER0_CC0(0x0, 0x8)
+#define TIMER0_CC0_PB0   SILABS_DBUS_TIMER0_CC0(0x1, 0x0)
+#define TIMER0_CC0_PB1   SILABS_DBUS_TIMER0_CC0(0x1, 0x1)
+#define TIMER0_CC0_PB2   SILABS_DBUS_TIMER0_CC0(0x1, 0x2)
+#define TIMER0_CC0_PB3   SILABS_DBUS_TIMER0_CC0(0x1, 0x3)
+#define TIMER0_CC0_PB4   SILABS_DBUS_TIMER0_CC0(0x1, 0x4)
+#define TIMER0_CC0_PC0   SILABS_DBUS_TIMER0_CC0(0x2, 0x0)
+#define TIMER0_CC0_PC1   SILABS_DBUS_TIMER0_CC0(0x2, 0x1)
+#define TIMER0_CC0_PC2   SILABS_DBUS_TIMER0_CC0(0x2, 0x2)
+#define TIMER0_CC0_PC3   SILABS_DBUS_TIMER0_CC0(0x2, 0x3)
+#define TIMER0_CC0_PC4   SILABS_DBUS_TIMER0_CC0(0x2, 0x4)
+#define TIMER0_CC0_PC5   SILABS_DBUS_TIMER0_CC0(0x2, 0x5)
+#define TIMER0_CC0_PC6   SILABS_DBUS_TIMER0_CC0(0x2, 0x6)
+#define TIMER0_CC0_PC7   SILABS_DBUS_TIMER0_CC0(0x2, 0x7)
+#define TIMER0_CC0_PD0   SILABS_DBUS_TIMER0_CC0(0x3, 0x0)
+#define TIMER0_CC0_PD1   SILABS_DBUS_TIMER0_CC0(0x3, 0x1)
+#define TIMER0_CC0_PD2   SILABS_DBUS_TIMER0_CC0(0x3, 0x2)
+#define TIMER0_CC0_PD3   SILABS_DBUS_TIMER0_CC0(0x3, 0x3)
+#define TIMER0_CC1_PA0   SILABS_DBUS_TIMER0_CC1(0x0, 0x0)
+#define TIMER0_CC1_PA1   SILABS_DBUS_TIMER0_CC1(0x0, 0x1)
+#define TIMER0_CC1_PA2   SILABS_DBUS_TIMER0_CC1(0x0, 0x2)
+#define TIMER0_CC1_PA3   SILABS_DBUS_TIMER0_CC1(0x0, 0x3)
+#define TIMER0_CC1_PA4   SILABS_DBUS_TIMER0_CC1(0x0, 0x4)
+#define TIMER0_CC1_PA5   SILABS_DBUS_TIMER0_CC1(0x0, 0x5)
+#define TIMER0_CC1_PA6   SILABS_DBUS_TIMER0_CC1(0x0, 0x6)
+#define TIMER0_CC1_PA7   SILABS_DBUS_TIMER0_CC1(0x0, 0x7)
+#define TIMER0_CC1_PA8   SILABS_DBUS_TIMER0_CC1(0x0, 0x8)
+#define TIMER0_CC1_PB0   SILABS_DBUS_TIMER0_CC1(0x1, 0x0)
+#define TIMER0_CC1_PB1   SILABS_DBUS_TIMER0_CC1(0x1, 0x1)
+#define TIMER0_CC1_PB2   SILABS_DBUS_TIMER0_CC1(0x1, 0x2)
+#define TIMER0_CC1_PB3   SILABS_DBUS_TIMER0_CC1(0x1, 0x3)
+#define TIMER0_CC1_PB4   SILABS_DBUS_TIMER0_CC1(0x1, 0x4)
+#define TIMER0_CC1_PC0   SILABS_DBUS_TIMER0_CC1(0x2, 0x0)
+#define TIMER0_CC1_PC1   SILABS_DBUS_TIMER0_CC1(0x2, 0x1)
+#define TIMER0_CC1_PC2   SILABS_DBUS_TIMER0_CC1(0x2, 0x2)
+#define TIMER0_CC1_PC3   SILABS_DBUS_TIMER0_CC1(0x2, 0x3)
+#define TIMER0_CC1_PC4   SILABS_DBUS_TIMER0_CC1(0x2, 0x4)
+#define TIMER0_CC1_PC5   SILABS_DBUS_TIMER0_CC1(0x2, 0x5)
+#define TIMER0_CC1_PC6   SILABS_DBUS_TIMER0_CC1(0x2, 0x6)
+#define TIMER0_CC1_PC7   SILABS_DBUS_TIMER0_CC1(0x2, 0x7)
+#define TIMER0_CC1_PD0   SILABS_DBUS_TIMER0_CC1(0x3, 0x0)
+#define TIMER0_CC1_PD1   SILABS_DBUS_TIMER0_CC1(0x3, 0x1)
+#define TIMER0_CC1_PD2   SILABS_DBUS_TIMER0_CC1(0x3, 0x2)
+#define TIMER0_CC1_PD3   SILABS_DBUS_TIMER0_CC1(0x3, 0x3)
+#define TIMER0_CC2_PA0   SILABS_DBUS_TIMER0_CC2(0x0, 0x0)
+#define TIMER0_CC2_PA1   SILABS_DBUS_TIMER0_CC2(0x0, 0x1)
+#define TIMER0_CC2_PA2   SILABS_DBUS_TIMER0_CC2(0x0, 0x2)
+#define TIMER0_CC2_PA3   SILABS_DBUS_TIMER0_CC2(0x0, 0x3)
+#define TIMER0_CC2_PA4   SILABS_DBUS_TIMER0_CC2(0x0, 0x4)
+#define TIMER0_CC2_PA5   SILABS_DBUS_TIMER0_CC2(0x0, 0x5)
+#define TIMER0_CC2_PA6   SILABS_DBUS_TIMER0_CC2(0x0, 0x6)
+#define TIMER0_CC2_PA7   SILABS_DBUS_TIMER0_CC2(0x0, 0x7)
+#define TIMER0_CC2_PA8   SILABS_DBUS_TIMER0_CC2(0x0, 0x8)
+#define TIMER0_CC2_PB0   SILABS_DBUS_TIMER0_CC2(0x1, 0x0)
+#define TIMER0_CC2_PB1   SILABS_DBUS_TIMER0_CC2(0x1, 0x1)
+#define TIMER0_CC2_PB2   SILABS_DBUS_TIMER0_CC2(0x1, 0x2)
+#define TIMER0_CC2_PB3   SILABS_DBUS_TIMER0_CC2(0x1, 0x3)
+#define TIMER0_CC2_PB4   SILABS_DBUS_TIMER0_CC2(0x1, 0x4)
+#define TIMER0_CC2_PC0   SILABS_DBUS_TIMER0_CC2(0x2, 0x0)
+#define TIMER0_CC2_PC1   SILABS_DBUS_TIMER0_CC2(0x2, 0x1)
+#define TIMER0_CC2_PC2   SILABS_DBUS_TIMER0_CC2(0x2, 0x2)
+#define TIMER0_CC2_PC3   SILABS_DBUS_TIMER0_CC2(0x2, 0x3)
+#define TIMER0_CC2_PC4   SILABS_DBUS_TIMER0_CC2(0x2, 0x4)
+#define TIMER0_CC2_PC5   SILABS_DBUS_TIMER0_CC2(0x2, 0x5)
+#define TIMER0_CC2_PC6   SILABS_DBUS_TIMER0_CC2(0x2, 0x6)
+#define TIMER0_CC2_PC7   SILABS_DBUS_TIMER0_CC2(0x2, 0x7)
+#define TIMER0_CC2_PD0   SILABS_DBUS_TIMER0_CC2(0x3, 0x0)
+#define TIMER0_CC2_PD1   SILABS_DBUS_TIMER0_CC2(0x3, 0x1)
+#define TIMER0_CC2_PD2   SILABS_DBUS_TIMER0_CC2(0x3, 0x2)
+#define TIMER0_CC2_PD3   SILABS_DBUS_TIMER0_CC2(0x3, 0x3)
+#define TIMER0_CDTI0_PA0 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x0)
+#define TIMER0_CDTI0_PA1 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x1)
+#define TIMER0_CDTI0_PA2 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x2)
+#define TIMER0_CDTI0_PA3 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x3)
+#define TIMER0_CDTI0_PA4 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x4)
+#define TIMER0_CDTI0_PA5 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x5)
+#define TIMER0_CDTI0_PA6 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x6)
+#define TIMER0_CDTI0_PA7 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x7)
+#define TIMER0_CDTI0_PA8 SILABS_DBUS_TIMER0_CDTI0(0x0, 0x8)
+#define TIMER0_CDTI0_PB0 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x0)
+#define TIMER0_CDTI0_PB1 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x1)
+#define TIMER0_CDTI0_PB2 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x2)
+#define TIMER0_CDTI0_PB3 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x3)
+#define TIMER0_CDTI0_PB4 SILABS_DBUS_TIMER0_CDTI0(0x1, 0x4)
+#define TIMER0_CDTI0_PC0 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x0)
+#define TIMER0_CDTI0_PC1 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x1)
+#define TIMER0_CDTI0_PC2 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x2)
+#define TIMER0_CDTI0_PC3 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x3)
+#define TIMER0_CDTI0_PC4 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x4)
+#define TIMER0_CDTI0_PC5 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x5)
+#define TIMER0_CDTI0_PC6 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x6)
+#define TIMER0_CDTI0_PC7 SILABS_DBUS_TIMER0_CDTI0(0x2, 0x7)
+#define TIMER0_CDTI0_PD0 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x0)
+#define TIMER0_CDTI0_PD1 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x1)
+#define TIMER0_CDTI0_PD2 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x2)
+#define TIMER0_CDTI0_PD3 SILABS_DBUS_TIMER0_CDTI0(0x3, 0x3)
+#define TIMER0_CDTI1_PA0 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x0)
+#define TIMER0_CDTI1_PA1 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x1)
+#define TIMER0_CDTI1_PA2 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x2)
+#define TIMER0_CDTI1_PA3 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x3)
+#define TIMER0_CDTI1_PA4 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x4)
+#define TIMER0_CDTI1_PA5 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x5)
+#define TIMER0_CDTI1_PA6 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x6)
+#define TIMER0_CDTI1_PA7 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x7)
+#define TIMER0_CDTI1_PA8 SILABS_DBUS_TIMER0_CDTI1(0x0, 0x8)
+#define TIMER0_CDTI1_PB0 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x0)
+#define TIMER0_CDTI1_PB1 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x1)
+#define TIMER0_CDTI1_PB2 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x2)
+#define TIMER0_CDTI1_PB3 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x3)
+#define TIMER0_CDTI1_PB4 SILABS_DBUS_TIMER0_CDTI1(0x1, 0x4)
+#define TIMER0_CDTI1_PC0 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x0)
+#define TIMER0_CDTI1_PC1 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x1)
+#define TIMER0_CDTI1_PC2 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x2)
+#define TIMER0_CDTI1_PC3 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x3)
+#define TIMER0_CDTI1_PC4 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x4)
+#define TIMER0_CDTI1_PC5 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x5)
+#define TIMER0_CDTI1_PC6 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x6)
+#define TIMER0_CDTI1_PC7 SILABS_DBUS_TIMER0_CDTI1(0x2, 0x7)
+#define TIMER0_CDTI1_PD0 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x0)
+#define TIMER0_CDTI1_PD1 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x1)
+#define TIMER0_CDTI1_PD2 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x2)
+#define TIMER0_CDTI1_PD3 SILABS_DBUS_TIMER0_CDTI1(0x3, 0x3)
+#define TIMER0_CDTI2_PA0 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x0)
+#define TIMER0_CDTI2_PA1 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x1)
+#define TIMER0_CDTI2_PA2 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x2)
+#define TIMER0_CDTI2_PA3 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x3)
+#define TIMER0_CDTI2_PA4 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x4)
+#define TIMER0_CDTI2_PA5 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x5)
+#define TIMER0_CDTI2_PA6 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x6)
+#define TIMER0_CDTI2_PA7 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x7)
+#define TIMER0_CDTI2_PA8 SILABS_DBUS_TIMER0_CDTI2(0x0, 0x8)
+#define TIMER0_CDTI2_PB0 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x0)
+#define TIMER0_CDTI2_PB1 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x1)
+#define TIMER0_CDTI2_PB2 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x2)
+#define TIMER0_CDTI2_PB3 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x3)
+#define TIMER0_CDTI2_PB4 SILABS_DBUS_TIMER0_CDTI2(0x1, 0x4)
+#define TIMER0_CDTI2_PC0 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x0)
+#define TIMER0_CDTI2_PC1 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x1)
+#define TIMER0_CDTI2_PC2 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x2)
+#define TIMER0_CDTI2_PC3 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x3)
+#define TIMER0_CDTI2_PC4 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x4)
+#define TIMER0_CDTI2_PC5 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x5)
+#define TIMER0_CDTI2_PC6 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x6)
+#define TIMER0_CDTI2_PC7 SILABS_DBUS_TIMER0_CDTI2(0x2, 0x7)
+#define TIMER0_CDTI2_PD0 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x0)
+#define TIMER0_CDTI2_PD1 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x1)
+#define TIMER0_CDTI2_PD2 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x2)
+#define TIMER0_CDTI2_PD3 SILABS_DBUS_TIMER0_CDTI2(0x3, 0x3)
+
+#define TIMER1_CC0_PA0   SILABS_DBUS_TIMER1_CC0(0x0, 0x0)
+#define TIMER1_CC0_PA1   SILABS_DBUS_TIMER1_CC0(0x0, 0x1)
+#define TIMER1_CC0_PA2   SILABS_DBUS_TIMER1_CC0(0x0, 0x2)
+#define TIMER1_CC0_PA3   SILABS_DBUS_TIMER1_CC0(0x0, 0x3)
+#define TIMER1_CC0_PA4   SILABS_DBUS_TIMER1_CC0(0x0, 0x4)
+#define TIMER1_CC0_PA5   SILABS_DBUS_TIMER1_CC0(0x0, 0x5)
+#define TIMER1_CC0_PA6   SILABS_DBUS_TIMER1_CC0(0x0, 0x6)
+#define TIMER1_CC0_PA7   SILABS_DBUS_TIMER1_CC0(0x0, 0x7)
+#define TIMER1_CC0_PA8   SILABS_DBUS_TIMER1_CC0(0x0, 0x8)
+#define TIMER1_CC0_PB0   SILABS_DBUS_TIMER1_CC0(0x1, 0x0)
+#define TIMER1_CC0_PB1   SILABS_DBUS_TIMER1_CC0(0x1, 0x1)
+#define TIMER1_CC0_PB2   SILABS_DBUS_TIMER1_CC0(0x1, 0x2)
+#define TIMER1_CC0_PB3   SILABS_DBUS_TIMER1_CC0(0x1, 0x3)
+#define TIMER1_CC0_PB4   SILABS_DBUS_TIMER1_CC0(0x1, 0x4)
+#define TIMER1_CC0_PC0   SILABS_DBUS_TIMER1_CC0(0x2, 0x0)
+#define TIMER1_CC0_PC1   SILABS_DBUS_TIMER1_CC0(0x2, 0x1)
+#define TIMER1_CC0_PC2   SILABS_DBUS_TIMER1_CC0(0x2, 0x2)
+#define TIMER1_CC0_PC3   SILABS_DBUS_TIMER1_CC0(0x2, 0x3)
+#define TIMER1_CC0_PC4   SILABS_DBUS_TIMER1_CC0(0x2, 0x4)
+#define TIMER1_CC0_PC5   SILABS_DBUS_TIMER1_CC0(0x2, 0x5)
+#define TIMER1_CC0_PC6   SILABS_DBUS_TIMER1_CC0(0x2, 0x6)
+#define TIMER1_CC0_PC7   SILABS_DBUS_TIMER1_CC0(0x2, 0x7)
+#define TIMER1_CC0_PD0   SILABS_DBUS_TIMER1_CC0(0x3, 0x0)
+#define TIMER1_CC0_PD1   SILABS_DBUS_TIMER1_CC0(0x3, 0x1)
+#define TIMER1_CC0_PD2   SILABS_DBUS_TIMER1_CC0(0x3, 0x2)
+#define TIMER1_CC0_PD3   SILABS_DBUS_TIMER1_CC0(0x3, 0x3)
+#define TIMER1_CC1_PA0   SILABS_DBUS_TIMER1_CC1(0x0, 0x0)
+#define TIMER1_CC1_PA1   SILABS_DBUS_TIMER1_CC1(0x0, 0x1)
+#define TIMER1_CC1_PA2   SILABS_DBUS_TIMER1_CC1(0x0, 0x2)
+#define TIMER1_CC1_PA3   SILABS_DBUS_TIMER1_CC1(0x0, 0x3)
+#define TIMER1_CC1_PA4   SILABS_DBUS_TIMER1_CC1(0x0, 0x4)
+#define TIMER1_CC1_PA5   SILABS_DBUS_TIMER1_CC1(0x0, 0x5)
+#define TIMER1_CC1_PA6   SILABS_DBUS_TIMER1_CC1(0x0, 0x6)
+#define TIMER1_CC1_PA7   SILABS_DBUS_TIMER1_CC1(0x0, 0x7)
+#define TIMER1_CC1_PA8   SILABS_DBUS_TIMER1_CC1(0x0, 0x8)
+#define TIMER1_CC1_PB0   SILABS_DBUS_TIMER1_CC1(0x1, 0x0)
+#define TIMER1_CC1_PB1   SILABS_DBUS_TIMER1_CC1(0x1, 0x1)
+#define TIMER1_CC1_PB2   SILABS_DBUS_TIMER1_CC1(0x1, 0x2)
+#define TIMER1_CC1_PB3   SILABS_DBUS_TIMER1_CC1(0x1, 0x3)
+#define TIMER1_CC1_PB4   SILABS_DBUS_TIMER1_CC1(0x1, 0x4)
+#define TIMER1_CC1_PC0   SILABS_DBUS_TIMER1_CC1(0x2, 0x0)
+#define TIMER1_CC1_PC1   SILABS_DBUS_TIMER1_CC1(0x2, 0x1)
+#define TIMER1_CC1_PC2   SILABS_DBUS_TIMER1_CC1(0x2, 0x2)
+#define TIMER1_CC1_PC3   SILABS_DBUS_TIMER1_CC1(0x2, 0x3)
+#define TIMER1_CC1_PC4   SILABS_DBUS_TIMER1_CC1(0x2, 0x4)
+#define TIMER1_CC1_PC5   SILABS_DBUS_TIMER1_CC1(0x2, 0x5)
+#define TIMER1_CC1_PC6   SILABS_DBUS_TIMER1_CC1(0x2, 0x6)
+#define TIMER1_CC1_PC7   SILABS_DBUS_TIMER1_CC1(0x2, 0x7)
+#define TIMER1_CC1_PD0   SILABS_DBUS_TIMER1_CC1(0x3, 0x0)
+#define TIMER1_CC1_PD1   SILABS_DBUS_TIMER1_CC1(0x3, 0x1)
+#define TIMER1_CC1_PD2   SILABS_DBUS_TIMER1_CC1(0x3, 0x2)
+#define TIMER1_CC1_PD3   SILABS_DBUS_TIMER1_CC1(0x3, 0x3)
+#define TIMER1_CC2_PA0   SILABS_DBUS_TIMER1_CC2(0x0, 0x0)
+#define TIMER1_CC2_PA1   SILABS_DBUS_TIMER1_CC2(0x0, 0x1)
+#define TIMER1_CC2_PA2   SILABS_DBUS_TIMER1_CC2(0x0, 0x2)
+#define TIMER1_CC2_PA3   SILABS_DBUS_TIMER1_CC2(0x0, 0x3)
+#define TIMER1_CC2_PA4   SILABS_DBUS_TIMER1_CC2(0x0, 0x4)
+#define TIMER1_CC2_PA5   SILABS_DBUS_TIMER1_CC2(0x0, 0x5)
+#define TIMER1_CC2_PA6   SILABS_DBUS_TIMER1_CC2(0x0, 0x6)
+#define TIMER1_CC2_PA7   SILABS_DBUS_TIMER1_CC2(0x0, 0x7)
+#define TIMER1_CC2_PA8   SILABS_DBUS_TIMER1_CC2(0x0, 0x8)
+#define TIMER1_CC2_PB0   SILABS_DBUS_TIMER1_CC2(0x1, 0x0)
+#define TIMER1_CC2_PB1   SILABS_DBUS_TIMER1_CC2(0x1, 0x1)
+#define TIMER1_CC2_PB2   SILABS_DBUS_TIMER1_CC2(0x1, 0x2)
+#define TIMER1_CC2_PB3   SILABS_DBUS_TIMER1_CC2(0x1, 0x3)
+#define TIMER1_CC2_PB4   SILABS_DBUS_TIMER1_CC2(0x1, 0x4)
+#define TIMER1_CC2_PC0   SILABS_DBUS_TIMER1_CC2(0x2, 0x0)
+#define TIMER1_CC2_PC1   SILABS_DBUS_TIMER1_CC2(0x2, 0x1)
+#define TIMER1_CC2_PC2   SILABS_DBUS_TIMER1_CC2(0x2, 0x2)
+#define TIMER1_CC2_PC3   SILABS_DBUS_TIMER1_CC2(0x2, 0x3)
+#define TIMER1_CC2_PC4   SILABS_DBUS_TIMER1_CC2(0x2, 0x4)
+#define TIMER1_CC2_PC5   SILABS_DBUS_TIMER1_CC2(0x2, 0x5)
+#define TIMER1_CC2_PC6   SILABS_DBUS_TIMER1_CC2(0x2, 0x6)
+#define TIMER1_CC2_PC7   SILABS_DBUS_TIMER1_CC2(0x2, 0x7)
+#define TIMER1_CC2_PD0   SILABS_DBUS_TIMER1_CC2(0x3, 0x0)
+#define TIMER1_CC2_PD1   SILABS_DBUS_TIMER1_CC2(0x3, 0x1)
+#define TIMER1_CC2_PD2   SILABS_DBUS_TIMER1_CC2(0x3, 0x2)
+#define TIMER1_CC2_PD3   SILABS_DBUS_TIMER1_CC2(0x3, 0x3)
+#define TIMER1_CDTI0_PA0 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x0)
+#define TIMER1_CDTI0_PA1 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x1)
+#define TIMER1_CDTI0_PA2 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x2)
+#define TIMER1_CDTI0_PA3 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x3)
+#define TIMER1_CDTI0_PA4 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x4)
+#define TIMER1_CDTI0_PA5 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x5)
+#define TIMER1_CDTI0_PA6 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x6)
+#define TIMER1_CDTI0_PA7 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x7)
+#define TIMER1_CDTI0_PA8 SILABS_DBUS_TIMER1_CDTI0(0x0, 0x8)
+#define TIMER1_CDTI0_PB0 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x0)
+#define TIMER1_CDTI0_PB1 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x1)
+#define TIMER1_CDTI0_PB2 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x2)
+#define TIMER1_CDTI0_PB3 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x3)
+#define TIMER1_CDTI0_PB4 SILABS_DBUS_TIMER1_CDTI0(0x1, 0x4)
+#define TIMER1_CDTI0_PC0 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x0)
+#define TIMER1_CDTI0_PC1 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x1)
+#define TIMER1_CDTI0_PC2 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x2)
+#define TIMER1_CDTI0_PC3 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x3)
+#define TIMER1_CDTI0_PC4 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x4)
+#define TIMER1_CDTI0_PC5 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x5)
+#define TIMER1_CDTI0_PC6 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x6)
+#define TIMER1_CDTI0_PC7 SILABS_DBUS_TIMER1_CDTI0(0x2, 0x7)
+#define TIMER1_CDTI0_PD0 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x0)
+#define TIMER1_CDTI0_PD1 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x1)
+#define TIMER1_CDTI0_PD2 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x2)
+#define TIMER1_CDTI0_PD3 SILABS_DBUS_TIMER1_CDTI0(0x3, 0x3)
+#define TIMER1_CDTI1_PA0 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x0)
+#define TIMER1_CDTI1_PA1 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x1)
+#define TIMER1_CDTI1_PA2 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x2)
+#define TIMER1_CDTI1_PA3 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x3)
+#define TIMER1_CDTI1_PA4 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x4)
+#define TIMER1_CDTI1_PA5 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x5)
+#define TIMER1_CDTI1_PA6 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x6)
+#define TIMER1_CDTI1_PA7 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x7)
+#define TIMER1_CDTI1_PA8 SILABS_DBUS_TIMER1_CDTI1(0x0, 0x8)
+#define TIMER1_CDTI1_PB0 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x0)
+#define TIMER1_CDTI1_PB1 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x1)
+#define TIMER1_CDTI1_PB2 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x2)
+#define TIMER1_CDTI1_PB3 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x3)
+#define TIMER1_CDTI1_PB4 SILABS_DBUS_TIMER1_CDTI1(0x1, 0x4)
+#define TIMER1_CDTI1_PC0 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x0)
+#define TIMER1_CDTI1_PC1 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x1)
+#define TIMER1_CDTI1_PC2 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x2)
+#define TIMER1_CDTI1_PC3 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x3)
+#define TIMER1_CDTI1_PC4 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x4)
+#define TIMER1_CDTI1_PC5 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x5)
+#define TIMER1_CDTI1_PC6 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x6)
+#define TIMER1_CDTI1_PC7 SILABS_DBUS_TIMER1_CDTI1(0x2, 0x7)
+#define TIMER1_CDTI1_PD0 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x0)
+#define TIMER1_CDTI1_PD1 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x1)
+#define TIMER1_CDTI1_PD2 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x2)
+#define TIMER1_CDTI1_PD3 SILABS_DBUS_TIMER1_CDTI1(0x3, 0x3)
+#define TIMER1_CDTI2_PA0 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x0)
+#define TIMER1_CDTI2_PA1 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x1)
+#define TIMER1_CDTI2_PA2 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x2)
+#define TIMER1_CDTI2_PA3 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x3)
+#define TIMER1_CDTI2_PA4 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x4)
+#define TIMER1_CDTI2_PA5 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x5)
+#define TIMER1_CDTI2_PA6 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x6)
+#define TIMER1_CDTI2_PA7 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x7)
+#define TIMER1_CDTI2_PA8 SILABS_DBUS_TIMER1_CDTI2(0x0, 0x8)
+#define TIMER1_CDTI2_PB0 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x0)
+#define TIMER1_CDTI2_PB1 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x1)
+#define TIMER1_CDTI2_PB2 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x2)
+#define TIMER1_CDTI2_PB3 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x3)
+#define TIMER1_CDTI2_PB4 SILABS_DBUS_TIMER1_CDTI2(0x1, 0x4)
+#define TIMER1_CDTI2_PC0 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x0)
+#define TIMER1_CDTI2_PC1 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x1)
+#define TIMER1_CDTI2_PC2 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x2)
+#define TIMER1_CDTI2_PC3 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x3)
+#define TIMER1_CDTI2_PC4 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x4)
+#define TIMER1_CDTI2_PC5 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x5)
+#define TIMER1_CDTI2_PC6 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x6)
+#define TIMER1_CDTI2_PC7 SILABS_DBUS_TIMER1_CDTI2(0x2, 0x7)
+#define TIMER1_CDTI2_PD0 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x0)
+#define TIMER1_CDTI2_PD1 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x1)
+#define TIMER1_CDTI2_PD2 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x2)
+#define TIMER1_CDTI2_PD3 SILABS_DBUS_TIMER1_CDTI2(0x3, 0x3)
+
+#define TIMER2_CC0_PA0   SILABS_DBUS_TIMER2_CC0(0x0, 0x0)
+#define TIMER2_CC0_PA1   SILABS_DBUS_TIMER2_CC0(0x0, 0x1)
+#define TIMER2_CC0_PA2   SILABS_DBUS_TIMER2_CC0(0x0, 0x2)
+#define TIMER2_CC0_PA3   SILABS_DBUS_TIMER2_CC0(0x0, 0x3)
+#define TIMER2_CC0_PA4   SILABS_DBUS_TIMER2_CC0(0x0, 0x4)
+#define TIMER2_CC0_PA5   SILABS_DBUS_TIMER2_CC0(0x0, 0x5)
+#define TIMER2_CC0_PA6   SILABS_DBUS_TIMER2_CC0(0x0, 0x6)
+#define TIMER2_CC0_PA7   SILABS_DBUS_TIMER2_CC0(0x0, 0x7)
+#define TIMER2_CC0_PA8   SILABS_DBUS_TIMER2_CC0(0x0, 0x8)
+#define TIMER2_CC0_PB0   SILABS_DBUS_TIMER2_CC0(0x1, 0x0)
+#define TIMER2_CC0_PB1   SILABS_DBUS_TIMER2_CC0(0x1, 0x1)
+#define TIMER2_CC0_PB2   SILABS_DBUS_TIMER2_CC0(0x1, 0x2)
+#define TIMER2_CC0_PB3   SILABS_DBUS_TIMER2_CC0(0x1, 0x3)
+#define TIMER2_CC0_PB4   SILABS_DBUS_TIMER2_CC0(0x1, 0x4)
+#define TIMER2_CC1_PA0   SILABS_DBUS_TIMER2_CC1(0x0, 0x0)
+#define TIMER2_CC1_PA1   SILABS_DBUS_TIMER2_CC1(0x0, 0x1)
+#define TIMER2_CC1_PA2   SILABS_DBUS_TIMER2_CC1(0x0, 0x2)
+#define TIMER2_CC1_PA3   SILABS_DBUS_TIMER2_CC1(0x0, 0x3)
+#define TIMER2_CC1_PA4   SILABS_DBUS_TIMER2_CC1(0x0, 0x4)
+#define TIMER2_CC1_PA5   SILABS_DBUS_TIMER2_CC1(0x0, 0x5)
+#define TIMER2_CC1_PA6   SILABS_DBUS_TIMER2_CC1(0x0, 0x6)
+#define TIMER2_CC1_PA7   SILABS_DBUS_TIMER2_CC1(0x0, 0x7)
+#define TIMER2_CC1_PA8   SILABS_DBUS_TIMER2_CC1(0x0, 0x8)
+#define TIMER2_CC1_PB0   SILABS_DBUS_TIMER2_CC1(0x1, 0x0)
+#define TIMER2_CC1_PB1   SILABS_DBUS_TIMER2_CC1(0x1, 0x1)
+#define TIMER2_CC1_PB2   SILABS_DBUS_TIMER2_CC1(0x1, 0x2)
+#define TIMER2_CC1_PB3   SILABS_DBUS_TIMER2_CC1(0x1, 0x3)
+#define TIMER2_CC1_PB4   SILABS_DBUS_TIMER2_CC1(0x1, 0x4)
+#define TIMER2_CC2_PA0   SILABS_DBUS_TIMER2_CC2(0x0, 0x0)
+#define TIMER2_CC2_PA1   SILABS_DBUS_TIMER2_CC2(0x0, 0x1)
+#define TIMER2_CC2_PA2   SILABS_DBUS_TIMER2_CC2(0x0, 0x2)
+#define TIMER2_CC2_PA3   SILABS_DBUS_TIMER2_CC2(0x0, 0x3)
+#define TIMER2_CC2_PA4   SILABS_DBUS_TIMER2_CC2(0x0, 0x4)
+#define TIMER2_CC2_PA5   SILABS_DBUS_TIMER2_CC2(0x0, 0x5)
+#define TIMER2_CC2_PA6   SILABS_DBUS_TIMER2_CC2(0x0, 0x6)
+#define TIMER2_CC2_PA7   SILABS_DBUS_TIMER2_CC2(0x0, 0x7)
+#define TIMER2_CC2_PA8   SILABS_DBUS_TIMER2_CC2(0x0, 0x8)
+#define TIMER2_CC2_PB0   SILABS_DBUS_TIMER2_CC2(0x1, 0x0)
+#define TIMER2_CC2_PB1   SILABS_DBUS_TIMER2_CC2(0x1, 0x1)
+#define TIMER2_CC2_PB2   SILABS_DBUS_TIMER2_CC2(0x1, 0x2)
+#define TIMER2_CC2_PB3   SILABS_DBUS_TIMER2_CC2(0x1, 0x3)
+#define TIMER2_CC2_PB4   SILABS_DBUS_TIMER2_CC2(0x1, 0x4)
+#define TIMER2_CDTI0_PA0 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x0)
+#define TIMER2_CDTI0_PA1 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x1)
+#define TIMER2_CDTI0_PA2 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x2)
+#define TIMER2_CDTI0_PA3 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x3)
+#define TIMER2_CDTI0_PA4 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x4)
+#define TIMER2_CDTI0_PA5 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x5)
+#define TIMER2_CDTI0_PA6 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x6)
+#define TIMER2_CDTI0_PA7 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x7)
+#define TIMER2_CDTI0_PA8 SILABS_DBUS_TIMER2_CDTI0(0x0, 0x8)
+#define TIMER2_CDTI0_PB0 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x0)
+#define TIMER2_CDTI0_PB1 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x1)
+#define TIMER2_CDTI0_PB2 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x2)
+#define TIMER2_CDTI0_PB3 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x3)
+#define TIMER2_CDTI0_PB4 SILABS_DBUS_TIMER2_CDTI0(0x1, 0x4)
+#define TIMER2_CDTI1_PA0 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x0)
+#define TIMER2_CDTI1_PA1 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x1)
+#define TIMER2_CDTI1_PA2 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x2)
+#define TIMER2_CDTI1_PA3 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x3)
+#define TIMER2_CDTI1_PA4 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x4)
+#define TIMER2_CDTI1_PA5 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x5)
+#define TIMER2_CDTI1_PA6 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x6)
+#define TIMER2_CDTI1_PA7 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x7)
+#define TIMER2_CDTI1_PA8 SILABS_DBUS_TIMER2_CDTI1(0x0, 0x8)
+#define TIMER2_CDTI1_PB0 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x0)
+#define TIMER2_CDTI1_PB1 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x1)
+#define TIMER2_CDTI1_PB2 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x2)
+#define TIMER2_CDTI1_PB3 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x3)
+#define TIMER2_CDTI1_PB4 SILABS_DBUS_TIMER2_CDTI1(0x1, 0x4)
+#define TIMER2_CDTI2_PA0 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x0)
+#define TIMER2_CDTI2_PA1 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x1)
+#define TIMER2_CDTI2_PA2 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x2)
+#define TIMER2_CDTI2_PA3 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x3)
+#define TIMER2_CDTI2_PA4 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x4)
+#define TIMER2_CDTI2_PA5 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x5)
+#define TIMER2_CDTI2_PA6 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x6)
+#define TIMER2_CDTI2_PA7 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x7)
+#define TIMER2_CDTI2_PA8 SILABS_DBUS_TIMER2_CDTI2(0x0, 0x8)
+#define TIMER2_CDTI2_PB0 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x0)
+#define TIMER2_CDTI2_PB1 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x1)
+#define TIMER2_CDTI2_PB2 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x2)
+#define TIMER2_CDTI2_PB3 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x3)
+#define TIMER2_CDTI2_PB4 SILABS_DBUS_TIMER2_CDTI2(0x1, 0x4)
+
+#define TIMER3_CC0_PC0   SILABS_DBUS_TIMER3_CC0(0x2, 0x0)
+#define TIMER3_CC0_PC1   SILABS_DBUS_TIMER3_CC0(0x2, 0x1)
+#define TIMER3_CC0_PC2   SILABS_DBUS_TIMER3_CC0(0x2, 0x2)
+#define TIMER3_CC0_PC3   SILABS_DBUS_TIMER3_CC0(0x2, 0x3)
+#define TIMER3_CC0_PC4   SILABS_DBUS_TIMER3_CC0(0x2, 0x4)
+#define TIMER3_CC0_PC5   SILABS_DBUS_TIMER3_CC0(0x2, 0x5)
+#define TIMER3_CC0_PC6   SILABS_DBUS_TIMER3_CC0(0x2, 0x6)
+#define TIMER3_CC0_PC7   SILABS_DBUS_TIMER3_CC0(0x2, 0x7)
+#define TIMER3_CC0_PD0   SILABS_DBUS_TIMER3_CC0(0x3, 0x0)
+#define TIMER3_CC0_PD1   SILABS_DBUS_TIMER3_CC0(0x3, 0x1)
+#define TIMER3_CC0_PD2   SILABS_DBUS_TIMER3_CC0(0x3, 0x2)
+#define TIMER3_CC0_PD3   SILABS_DBUS_TIMER3_CC0(0x3, 0x3)
+#define TIMER3_CC1_PC0   SILABS_DBUS_TIMER3_CC1(0x2, 0x0)
+#define TIMER3_CC1_PC1   SILABS_DBUS_TIMER3_CC1(0x2, 0x1)
+#define TIMER3_CC1_PC2   SILABS_DBUS_TIMER3_CC1(0x2, 0x2)
+#define TIMER3_CC1_PC3   SILABS_DBUS_TIMER3_CC1(0x2, 0x3)
+#define TIMER3_CC1_PC4   SILABS_DBUS_TIMER3_CC1(0x2, 0x4)
+#define TIMER3_CC1_PC5   SILABS_DBUS_TIMER3_CC1(0x2, 0x5)
+#define TIMER3_CC1_PC6   SILABS_DBUS_TIMER3_CC1(0x2, 0x6)
+#define TIMER3_CC1_PC7   SILABS_DBUS_TIMER3_CC1(0x2, 0x7)
+#define TIMER3_CC1_PD0   SILABS_DBUS_TIMER3_CC1(0x3, 0x0)
+#define TIMER3_CC1_PD1   SILABS_DBUS_TIMER3_CC1(0x3, 0x1)
+#define TIMER3_CC1_PD2   SILABS_DBUS_TIMER3_CC1(0x3, 0x2)
+#define TIMER3_CC1_PD3   SILABS_DBUS_TIMER3_CC1(0x3, 0x3)
+#define TIMER3_CC2_PC0   SILABS_DBUS_TIMER3_CC2(0x2, 0x0)
+#define TIMER3_CC2_PC1   SILABS_DBUS_TIMER3_CC2(0x2, 0x1)
+#define TIMER3_CC2_PC2   SILABS_DBUS_TIMER3_CC2(0x2, 0x2)
+#define TIMER3_CC2_PC3   SILABS_DBUS_TIMER3_CC2(0x2, 0x3)
+#define TIMER3_CC2_PC4   SILABS_DBUS_TIMER3_CC2(0x2, 0x4)
+#define TIMER3_CC2_PC5   SILABS_DBUS_TIMER3_CC2(0x2, 0x5)
+#define TIMER3_CC2_PC6   SILABS_DBUS_TIMER3_CC2(0x2, 0x6)
+#define TIMER3_CC2_PC7   SILABS_DBUS_TIMER3_CC2(0x2, 0x7)
+#define TIMER3_CC2_PD0   SILABS_DBUS_TIMER3_CC2(0x3, 0x0)
+#define TIMER3_CC2_PD1   SILABS_DBUS_TIMER3_CC2(0x3, 0x1)
+#define TIMER3_CC2_PD2   SILABS_DBUS_TIMER3_CC2(0x3, 0x2)
+#define TIMER3_CC2_PD3   SILABS_DBUS_TIMER3_CC2(0x3, 0x3)
+#define TIMER3_CDTI0_PC0 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x0)
+#define TIMER3_CDTI0_PC1 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x1)
+#define TIMER3_CDTI0_PC2 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x2)
+#define TIMER3_CDTI0_PC3 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x3)
+#define TIMER3_CDTI0_PC4 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x4)
+#define TIMER3_CDTI0_PC5 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x5)
+#define TIMER3_CDTI0_PC6 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x6)
+#define TIMER3_CDTI0_PC7 SILABS_DBUS_TIMER3_CDTI0(0x2, 0x7)
+#define TIMER3_CDTI0_PD0 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x0)
+#define TIMER3_CDTI0_PD1 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x1)
+#define TIMER3_CDTI0_PD2 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x2)
+#define TIMER3_CDTI0_PD3 SILABS_DBUS_TIMER3_CDTI0(0x3, 0x3)
+#define TIMER3_CDTI1_PC0 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x0)
+#define TIMER3_CDTI1_PC1 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x1)
+#define TIMER3_CDTI1_PC2 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x2)
+#define TIMER3_CDTI1_PC3 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x3)
+#define TIMER3_CDTI1_PC4 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x4)
+#define TIMER3_CDTI1_PC5 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x5)
+#define TIMER3_CDTI1_PC6 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x6)
+#define TIMER3_CDTI1_PC7 SILABS_DBUS_TIMER3_CDTI1(0x2, 0x7)
+#define TIMER3_CDTI1_PD0 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x0)
+#define TIMER3_CDTI1_PD1 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x1)
+#define TIMER3_CDTI1_PD2 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x2)
+#define TIMER3_CDTI1_PD3 SILABS_DBUS_TIMER3_CDTI1(0x3, 0x3)
+#define TIMER3_CDTI2_PC0 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x0)
+#define TIMER3_CDTI2_PC1 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x1)
+#define TIMER3_CDTI2_PC2 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x2)
+#define TIMER3_CDTI2_PC3 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x3)
+#define TIMER3_CDTI2_PC4 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x4)
+#define TIMER3_CDTI2_PC5 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x5)
+#define TIMER3_CDTI2_PC6 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x6)
+#define TIMER3_CDTI2_PC7 SILABS_DBUS_TIMER3_CDTI2(0x2, 0x7)
+#define TIMER3_CDTI2_PD0 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x0)
+#define TIMER3_CDTI2_PD1 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x1)
+#define TIMER3_CDTI2_PD2 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x2)
+#define TIMER3_CDTI2_PD3 SILABS_DBUS_TIMER3_CDTI2(0x3, 0x3)
+
+#define TIMER4_CC0_PA0   SILABS_DBUS_TIMER4_CC0(0x0, 0x0)
+#define TIMER4_CC0_PA1   SILABS_DBUS_TIMER4_CC0(0x0, 0x1)
+#define TIMER4_CC0_PA2   SILABS_DBUS_TIMER4_CC0(0x0, 0x2)
+#define TIMER4_CC0_PA3   SILABS_DBUS_TIMER4_CC0(0x0, 0x3)
+#define TIMER4_CC0_PA4   SILABS_DBUS_TIMER4_CC0(0x0, 0x4)
+#define TIMER4_CC0_PA5   SILABS_DBUS_TIMER4_CC0(0x0, 0x5)
+#define TIMER4_CC0_PA6   SILABS_DBUS_TIMER4_CC0(0x0, 0x6)
+#define TIMER4_CC0_PA7   SILABS_DBUS_TIMER4_CC0(0x0, 0x7)
+#define TIMER4_CC0_PA8   SILABS_DBUS_TIMER4_CC0(0x0, 0x8)
+#define TIMER4_CC0_PB0   SILABS_DBUS_TIMER4_CC0(0x1, 0x0)
+#define TIMER4_CC0_PB1   SILABS_DBUS_TIMER4_CC0(0x1, 0x1)
+#define TIMER4_CC0_PB2   SILABS_DBUS_TIMER4_CC0(0x1, 0x2)
+#define TIMER4_CC0_PB3   SILABS_DBUS_TIMER4_CC0(0x1, 0x3)
+#define TIMER4_CC0_PB4   SILABS_DBUS_TIMER4_CC0(0x1, 0x4)
+#define TIMER4_CC1_PA0   SILABS_DBUS_TIMER4_CC1(0x0, 0x0)
+#define TIMER4_CC1_PA1   SILABS_DBUS_TIMER4_CC1(0x0, 0x1)
+#define TIMER4_CC1_PA2   SILABS_DBUS_TIMER4_CC1(0x0, 0x2)
+#define TIMER4_CC1_PA3   SILABS_DBUS_TIMER4_CC1(0x0, 0x3)
+#define TIMER4_CC1_PA4   SILABS_DBUS_TIMER4_CC1(0x0, 0x4)
+#define TIMER4_CC1_PA5   SILABS_DBUS_TIMER4_CC1(0x0, 0x5)
+#define TIMER4_CC1_PA6   SILABS_DBUS_TIMER4_CC1(0x0, 0x6)
+#define TIMER4_CC1_PA7   SILABS_DBUS_TIMER4_CC1(0x0, 0x7)
+#define TIMER4_CC1_PA8   SILABS_DBUS_TIMER4_CC1(0x0, 0x8)
+#define TIMER4_CC1_PB0   SILABS_DBUS_TIMER4_CC1(0x1, 0x0)
+#define TIMER4_CC1_PB1   SILABS_DBUS_TIMER4_CC1(0x1, 0x1)
+#define TIMER4_CC1_PB2   SILABS_DBUS_TIMER4_CC1(0x1, 0x2)
+#define TIMER4_CC1_PB3   SILABS_DBUS_TIMER4_CC1(0x1, 0x3)
+#define TIMER4_CC1_PB4   SILABS_DBUS_TIMER4_CC1(0x1, 0x4)
+#define TIMER4_CC2_PA0   SILABS_DBUS_TIMER4_CC2(0x0, 0x0)
+#define TIMER4_CC2_PA1   SILABS_DBUS_TIMER4_CC2(0x0, 0x1)
+#define TIMER4_CC2_PA2   SILABS_DBUS_TIMER4_CC2(0x0, 0x2)
+#define TIMER4_CC2_PA3   SILABS_DBUS_TIMER4_CC2(0x0, 0x3)
+#define TIMER4_CC2_PA4   SILABS_DBUS_TIMER4_CC2(0x0, 0x4)
+#define TIMER4_CC2_PA5   SILABS_DBUS_TIMER4_CC2(0x0, 0x5)
+#define TIMER4_CC2_PA6   SILABS_DBUS_TIMER4_CC2(0x0, 0x6)
+#define TIMER4_CC2_PA7   SILABS_DBUS_TIMER4_CC2(0x0, 0x7)
+#define TIMER4_CC2_PA8   SILABS_DBUS_TIMER4_CC2(0x0, 0x8)
+#define TIMER4_CC2_PB0   SILABS_DBUS_TIMER4_CC2(0x1, 0x0)
+#define TIMER4_CC2_PB1   SILABS_DBUS_TIMER4_CC2(0x1, 0x1)
+#define TIMER4_CC2_PB2   SILABS_DBUS_TIMER4_CC2(0x1, 0x2)
+#define TIMER4_CC2_PB3   SILABS_DBUS_TIMER4_CC2(0x1, 0x3)
+#define TIMER4_CC2_PB4   SILABS_DBUS_TIMER4_CC2(0x1, 0x4)
+#define TIMER4_CDTI0_PA0 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x0)
+#define TIMER4_CDTI0_PA1 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x1)
+#define TIMER4_CDTI0_PA2 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x2)
+#define TIMER4_CDTI0_PA3 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x3)
+#define TIMER4_CDTI0_PA4 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x4)
+#define TIMER4_CDTI0_PA5 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x5)
+#define TIMER4_CDTI0_PA6 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x6)
+#define TIMER4_CDTI0_PA7 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x7)
+#define TIMER4_CDTI0_PA8 SILABS_DBUS_TIMER4_CDTI0(0x0, 0x8)
+#define TIMER4_CDTI0_PB0 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x0)
+#define TIMER4_CDTI0_PB1 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x1)
+#define TIMER4_CDTI0_PB2 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x2)
+#define TIMER4_CDTI0_PB3 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x3)
+#define TIMER4_CDTI0_PB4 SILABS_DBUS_TIMER4_CDTI0(0x1, 0x4)
+#define TIMER4_CDTI1_PA0 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x0)
+#define TIMER4_CDTI1_PA1 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x1)
+#define TIMER4_CDTI1_PA2 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x2)
+#define TIMER4_CDTI1_PA3 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x3)
+#define TIMER4_CDTI1_PA4 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x4)
+#define TIMER4_CDTI1_PA5 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x5)
+#define TIMER4_CDTI1_PA6 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x6)
+#define TIMER4_CDTI1_PA7 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x7)
+#define TIMER4_CDTI1_PA8 SILABS_DBUS_TIMER4_CDTI1(0x0, 0x8)
+#define TIMER4_CDTI1_PB0 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x0)
+#define TIMER4_CDTI1_PB1 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x1)
+#define TIMER4_CDTI1_PB2 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x2)
+#define TIMER4_CDTI1_PB3 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x3)
+#define TIMER4_CDTI1_PB4 SILABS_DBUS_TIMER4_CDTI1(0x1, 0x4)
+#define TIMER4_CDTI2_PA0 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x0)
+#define TIMER4_CDTI2_PA1 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x1)
+#define TIMER4_CDTI2_PA2 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x2)
+#define TIMER4_CDTI2_PA3 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x3)
+#define TIMER4_CDTI2_PA4 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x4)
+#define TIMER4_CDTI2_PA5 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x5)
+#define TIMER4_CDTI2_PA6 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x6)
+#define TIMER4_CDTI2_PA7 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x7)
+#define TIMER4_CDTI2_PA8 SILABS_DBUS_TIMER4_CDTI2(0x0, 0x8)
+#define TIMER4_CDTI2_PB0 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x0)
+#define TIMER4_CDTI2_PB1 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x1)
+#define TIMER4_CDTI2_PB2 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x2)
+#define TIMER4_CDTI2_PB3 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x3)
+#define TIMER4_CDTI2_PB4 SILABS_DBUS_TIMER4_CDTI2(0x1, 0x4)
+
+#define USART0_CS_PA0  SILABS_DBUS_USART0_CS(0x0, 0x0)
+#define USART0_CS_PA1  SILABS_DBUS_USART0_CS(0x0, 0x1)
+#define USART0_CS_PA2  SILABS_DBUS_USART0_CS(0x0, 0x2)
+#define USART0_CS_PA3  SILABS_DBUS_USART0_CS(0x0, 0x3)
+#define USART0_CS_PA4  SILABS_DBUS_USART0_CS(0x0, 0x4)
+#define USART0_CS_PA5  SILABS_DBUS_USART0_CS(0x0, 0x5)
+#define USART0_CS_PA6  SILABS_DBUS_USART0_CS(0x0, 0x6)
+#define USART0_CS_PA7  SILABS_DBUS_USART0_CS(0x0, 0x7)
+#define USART0_CS_PA8  SILABS_DBUS_USART0_CS(0x0, 0x8)
+#define USART0_CS_PB0  SILABS_DBUS_USART0_CS(0x1, 0x0)
+#define USART0_CS_PB1  SILABS_DBUS_USART0_CS(0x1, 0x1)
+#define USART0_CS_PB2  SILABS_DBUS_USART0_CS(0x1, 0x2)
+#define USART0_CS_PB3  SILABS_DBUS_USART0_CS(0x1, 0x3)
+#define USART0_CS_PB4  SILABS_DBUS_USART0_CS(0x1, 0x4)
+#define USART0_CS_PC0  SILABS_DBUS_USART0_CS(0x2, 0x0)
+#define USART0_CS_PC1  SILABS_DBUS_USART0_CS(0x2, 0x1)
+#define USART0_CS_PC2  SILABS_DBUS_USART0_CS(0x2, 0x2)
+#define USART0_CS_PC3  SILABS_DBUS_USART0_CS(0x2, 0x3)
+#define USART0_CS_PC4  SILABS_DBUS_USART0_CS(0x2, 0x4)
+#define USART0_CS_PC5  SILABS_DBUS_USART0_CS(0x2, 0x5)
+#define USART0_CS_PC6  SILABS_DBUS_USART0_CS(0x2, 0x6)
+#define USART0_CS_PC7  SILABS_DBUS_USART0_CS(0x2, 0x7)
+#define USART0_CS_PD0  SILABS_DBUS_USART0_CS(0x3, 0x0)
+#define USART0_CS_PD1  SILABS_DBUS_USART0_CS(0x3, 0x1)
+#define USART0_CS_PD2  SILABS_DBUS_USART0_CS(0x3, 0x2)
+#define USART0_CS_PD3  SILABS_DBUS_USART0_CS(0x3, 0x3)
+#define USART0_RTS_PA0 SILABS_DBUS_USART0_RTS(0x0, 0x0)
+#define USART0_RTS_PA1 SILABS_DBUS_USART0_RTS(0x0, 0x1)
+#define USART0_RTS_PA2 SILABS_DBUS_USART0_RTS(0x0, 0x2)
+#define USART0_RTS_PA3 SILABS_DBUS_USART0_RTS(0x0, 0x3)
+#define USART0_RTS_PA4 SILABS_DBUS_USART0_RTS(0x0, 0x4)
+#define USART0_RTS_PA5 SILABS_DBUS_USART0_RTS(0x0, 0x5)
+#define USART0_RTS_PA6 SILABS_DBUS_USART0_RTS(0x0, 0x6)
+#define USART0_RTS_PA7 SILABS_DBUS_USART0_RTS(0x0, 0x7)
+#define USART0_RTS_PA8 SILABS_DBUS_USART0_RTS(0x0, 0x8)
+#define USART0_RTS_PB0 SILABS_DBUS_USART0_RTS(0x1, 0x0)
+#define USART0_RTS_PB1 SILABS_DBUS_USART0_RTS(0x1, 0x1)
+#define USART0_RTS_PB2 SILABS_DBUS_USART0_RTS(0x1, 0x2)
+#define USART0_RTS_PB3 SILABS_DBUS_USART0_RTS(0x1, 0x3)
+#define USART0_RTS_PB4 SILABS_DBUS_USART0_RTS(0x1, 0x4)
+#define USART0_RTS_PC0 SILABS_DBUS_USART0_RTS(0x2, 0x0)
+#define USART0_RTS_PC1 SILABS_DBUS_USART0_RTS(0x2, 0x1)
+#define USART0_RTS_PC2 SILABS_DBUS_USART0_RTS(0x2, 0x2)
+#define USART0_RTS_PC3 SILABS_DBUS_USART0_RTS(0x2, 0x3)
+#define USART0_RTS_PC4 SILABS_DBUS_USART0_RTS(0x2, 0x4)
+#define USART0_RTS_PC5 SILABS_DBUS_USART0_RTS(0x2, 0x5)
+#define USART0_RTS_PC6 SILABS_DBUS_USART0_RTS(0x2, 0x6)
+#define USART0_RTS_PC7 SILABS_DBUS_USART0_RTS(0x2, 0x7)
+#define USART0_RTS_PD0 SILABS_DBUS_USART0_RTS(0x3, 0x0)
+#define USART0_RTS_PD1 SILABS_DBUS_USART0_RTS(0x3, 0x1)
+#define USART0_RTS_PD2 SILABS_DBUS_USART0_RTS(0x3, 0x2)
+#define USART0_RTS_PD3 SILABS_DBUS_USART0_RTS(0x3, 0x3)
+#define USART0_RX_PA0  SILABS_DBUS_USART0_RX(0x0, 0x0)
+#define USART0_RX_PA1  SILABS_DBUS_USART0_RX(0x0, 0x1)
+#define USART0_RX_PA2  SILABS_DBUS_USART0_RX(0x0, 0x2)
+#define USART0_RX_PA3  SILABS_DBUS_USART0_RX(0x0, 0x3)
+#define USART0_RX_PA4  SILABS_DBUS_USART0_RX(0x0, 0x4)
+#define USART0_RX_PA5  SILABS_DBUS_USART0_RX(0x0, 0x5)
+#define USART0_RX_PA6  SILABS_DBUS_USART0_RX(0x0, 0x6)
+#define USART0_RX_PA7  SILABS_DBUS_USART0_RX(0x0, 0x7)
+#define USART0_RX_PA8  SILABS_DBUS_USART0_RX(0x0, 0x8)
+#define USART0_RX_PB0  SILABS_DBUS_USART0_RX(0x1, 0x0)
+#define USART0_RX_PB1  SILABS_DBUS_USART0_RX(0x1, 0x1)
+#define USART0_RX_PB2  SILABS_DBUS_USART0_RX(0x1, 0x2)
+#define USART0_RX_PB3  SILABS_DBUS_USART0_RX(0x1, 0x3)
+#define USART0_RX_PB4  SILABS_DBUS_USART0_RX(0x1, 0x4)
+#define USART0_RX_PC0  SILABS_DBUS_USART0_RX(0x2, 0x0)
+#define USART0_RX_PC1  SILABS_DBUS_USART0_RX(0x2, 0x1)
+#define USART0_RX_PC2  SILABS_DBUS_USART0_RX(0x2, 0x2)
+#define USART0_RX_PC3  SILABS_DBUS_USART0_RX(0x2, 0x3)
+#define USART0_RX_PC4  SILABS_DBUS_USART0_RX(0x2, 0x4)
+#define USART0_RX_PC5  SILABS_DBUS_USART0_RX(0x2, 0x5)
+#define USART0_RX_PC6  SILABS_DBUS_USART0_RX(0x2, 0x6)
+#define USART0_RX_PC7  SILABS_DBUS_USART0_RX(0x2, 0x7)
+#define USART0_RX_PD0  SILABS_DBUS_USART0_RX(0x3, 0x0)
+#define USART0_RX_PD1  SILABS_DBUS_USART0_RX(0x3, 0x1)
+#define USART0_RX_PD2  SILABS_DBUS_USART0_RX(0x3, 0x2)
+#define USART0_RX_PD3  SILABS_DBUS_USART0_RX(0x3, 0x3)
+#define USART0_CLK_PA0 SILABS_DBUS_USART0_CLK(0x0, 0x0)
+#define USART0_CLK_PA1 SILABS_DBUS_USART0_CLK(0x0, 0x1)
+#define USART0_CLK_PA2 SILABS_DBUS_USART0_CLK(0x0, 0x2)
+#define USART0_CLK_PA3 SILABS_DBUS_USART0_CLK(0x0, 0x3)
+#define USART0_CLK_PA4 SILABS_DBUS_USART0_CLK(0x0, 0x4)
+#define USART0_CLK_PA5 SILABS_DBUS_USART0_CLK(0x0, 0x5)
+#define USART0_CLK_PA6 SILABS_DBUS_USART0_CLK(0x0, 0x6)
+#define USART0_CLK_PA7 SILABS_DBUS_USART0_CLK(0x0, 0x7)
+#define USART0_CLK_PA8 SILABS_DBUS_USART0_CLK(0x0, 0x8)
+#define USART0_CLK_PB0 SILABS_DBUS_USART0_CLK(0x1, 0x0)
+#define USART0_CLK_PB1 SILABS_DBUS_USART0_CLK(0x1, 0x1)
+#define USART0_CLK_PB2 SILABS_DBUS_USART0_CLK(0x1, 0x2)
+#define USART0_CLK_PB3 SILABS_DBUS_USART0_CLK(0x1, 0x3)
+#define USART0_CLK_PB4 SILABS_DBUS_USART0_CLK(0x1, 0x4)
+#define USART0_CLK_PC0 SILABS_DBUS_USART0_CLK(0x2, 0x0)
+#define USART0_CLK_PC1 SILABS_DBUS_USART0_CLK(0x2, 0x1)
+#define USART0_CLK_PC2 SILABS_DBUS_USART0_CLK(0x2, 0x2)
+#define USART0_CLK_PC3 SILABS_DBUS_USART0_CLK(0x2, 0x3)
+#define USART0_CLK_PC4 SILABS_DBUS_USART0_CLK(0x2, 0x4)
+#define USART0_CLK_PC5 SILABS_DBUS_USART0_CLK(0x2, 0x5)
+#define USART0_CLK_PC6 SILABS_DBUS_USART0_CLK(0x2, 0x6)
+#define USART0_CLK_PC7 SILABS_DBUS_USART0_CLK(0x2, 0x7)
+#define USART0_CLK_PD0 SILABS_DBUS_USART0_CLK(0x3, 0x0)
+#define USART0_CLK_PD1 SILABS_DBUS_USART0_CLK(0x3, 0x1)
+#define USART0_CLK_PD2 SILABS_DBUS_USART0_CLK(0x3, 0x2)
+#define USART0_CLK_PD3 SILABS_DBUS_USART0_CLK(0x3, 0x3)
+#define USART0_TX_PA0  SILABS_DBUS_USART0_TX(0x0, 0x0)
+#define USART0_TX_PA1  SILABS_DBUS_USART0_TX(0x0, 0x1)
+#define USART0_TX_PA2  SILABS_DBUS_USART0_TX(0x0, 0x2)
+#define USART0_TX_PA3  SILABS_DBUS_USART0_TX(0x0, 0x3)
+#define USART0_TX_PA4  SILABS_DBUS_USART0_TX(0x0, 0x4)
+#define USART0_TX_PA5  SILABS_DBUS_USART0_TX(0x0, 0x5)
+#define USART0_TX_PA6  SILABS_DBUS_USART0_TX(0x0, 0x6)
+#define USART0_TX_PA7  SILABS_DBUS_USART0_TX(0x0, 0x7)
+#define USART0_TX_PA8  SILABS_DBUS_USART0_TX(0x0, 0x8)
+#define USART0_TX_PB0  SILABS_DBUS_USART0_TX(0x1, 0x0)
+#define USART0_TX_PB1  SILABS_DBUS_USART0_TX(0x1, 0x1)
+#define USART0_TX_PB2  SILABS_DBUS_USART0_TX(0x1, 0x2)
+#define USART0_TX_PB3  SILABS_DBUS_USART0_TX(0x1, 0x3)
+#define USART0_TX_PB4  SILABS_DBUS_USART0_TX(0x1, 0x4)
+#define USART0_TX_PC0  SILABS_DBUS_USART0_TX(0x2, 0x0)
+#define USART0_TX_PC1  SILABS_DBUS_USART0_TX(0x2, 0x1)
+#define USART0_TX_PC2  SILABS_DBUS_USART0_TX(0x2, 0x2)
+#define USART0_TX_PC3  SILABS_DBUS_USART0_TX(0x2, 0x3)
+#define USART0_TX_PC4  SILABS_DBUS_USART0_TX(0x2, 0x4)
+#define USART0_TX_PC5  SILABS_DBUS_USART0_TX(0x2, 0x5)
+#define USART0_TX_PC6  SILABS_DBUS_USART0_TX(0x2, 0x6)
+#define USART0_TX_PC7  SILABS_DBUS_USART0_TX(0x2, 0x7)
+#define USART0_TX_PD0  SILABS_DBUS_USART0_TX(0x3, 0x0)
+#define USART0_TX_PD1  SILABS_DBUS_USART0_TX(0x3, 0x1)
+#define USART0_TX_PD2  SILABS_DBUS_USART0_TX(0x3, 0x2)
+#define USART0_TX_PD3  SILABS_DBUS_USART0_TX(0x3, 0x3)
+#define USART0_CTS_PA0 SILABS_DBUS_USART0_CTS(0x0, 0x0)
+#define USART0_CTS_PA1 SILABS_DBUS_USART0_CTS(0x0, 0x1)
+#define USART0_CTS_PA2 SILABS_DBUS_USART0_CTS(0x0, 0x2)
+#define USART0_CTS_PA3 SILABS_DBUS_USART0_CTS(0x0, 0x3)
+#define USART0_CTS_PA4 SILABS_DBUS_USART0_CTS(0x0, 0x4)
+#define USART0_CTS_PA5 SILABS_DBUS_USART0_CTS(0x0, 0x5)
+#define USART0_CTS_PA6 SILABS_DBUS_USART0_CTS(0x0, 0x6)
+#define USART0_CTS_PA7 SILABS_DBUS_USART0_CTS(0x0, 0x7)
+#define USART0_CTS_PA8 SILABS_DBUS_USART0_CTS(0x0, 0x8)
+#define USART0_CTS_PB0 SILABS_DBUS_USART0_CTS(0x1, 0x0)
+#define USART0_CTS_PB1 SILABS_DBUS_USART0_CTS(0x1, 0x1)
+#define USART0_CTS_PB2 SILABS_DBUS_USART0_CTS(0x1, 0x2)
+#define USART0_CTS_PB3 SILABS_DBUS_USART0_CTS(0x1, 0x3)
+#define USART0_CTS_PB4 SILABS_DBUS_USART0_CTS(0x1, 0x4)
+#define USART0_CTS_PC0 SILABS_DBUS_USART0_CTS(0x2, 0x0)
+#define USART0_CTS_PC1 SILABS_DBUS_USART0_CTS(0x2, 0x1)
+#define USART0_CTS_PC2 SILABS_DBUS_USART0_CTS(0x2, 0x2)
+#define USART0_CTS_PC3 SILABS_DBUS_USART0_CTS(0x2, 0x3)
+#define USART0_CTS_PC4 SILABS_DBUS_USART0_CTS(0x2, 0x4)
+#define USART0_CTS_PC5 SILABS_DBUS_USART0_CTS(0x2, 0x5)
+#define USART0_CTS_PC6 SILABS_DBUS_USART0_CTS(0x2, 0x6)
+#define USART0_CTS_PC7 SILABS_DBUS_USART0_CTS(0x2, 0x7)
+#define USART0_CTS_PD0 SILABS_DBUS_USART0_CTS(0x3, 0x0)
+#define USART0_CTS_PD1 SILABS_DBUS_USART0_CTS(0x3, 0x1)
+#define USART0_CTS_PD2 SILABS_DBUS_USART0_CTS(0x3, 0x2)
+#define USART0_CTS_PD3 SILABS_DBUS_USART0_CTS(0x3, 0x3)
+
+#define USART1_CS_PA0  SILABS_DBUS_USART1_CS(0x0, 0x0)
+#define USART1_CS_PA1  SILABS_DBUS_USART1_CS(0x0, 0x1)
+#define USART1_CS_PA2  SILABS_DBUS_USART1_CS(0x0, 0x2)
+#define USART1_CS_PA3  SILABS_DBUS_USART1_CS(0x0, 0x3)
+#define USART1_CS_PA4  SILABS_DBUS_USART1_CS(0x0, 0x4)
+#define USART1_CS_PA5  SILABS_DBUS_USART1_CS(0x0, 0x5)
+#define USART1_CS_PA6  SILABS_DBUS_USART1_CS(0x0, 0x6)
+#define USART1_CS_PA7  SILABS_DBUS_USART1_CS(0x0, 0x7)
+#define USART1_CS_PA8  SILABS_DBUS_USART1_CS(0x0, 0x8)
+#define USART1_CS_PB0  SILABS_DBUS_USART1_CS(0x1, 0x0)
+#define USART1_CS_PB1  SILABS_DBUS_USART1_CS(0x1, 0x1)
+#define USART1_CS_PB2  SILABS_DBUS_USART1_CS(0x1, 0x2)
+#define USART1_CS_PB3  SILABS_DBUS_USART1_CS(0x1, 0x3)
+#define USART1_CS_PB4  SILABS_DBUS_USART1_CS(0x1, 0x4)
+#define USART1_RTS_PA0 SILABS_DBUS_USART1_RTS(0x0, 0x0)
+#define USART1_RTS_PA1 SILABS_DBUS_USART1_RTS(0x0, 0x1)
+#define USART1_RTS_PA2 SILABS_DBUS_USART1_RTS(0x0, 0x2)
+#define USART1_RTS_PA3 SILABS_DBUS_USART1_RTS(0x0, 0x3)
+#define USART1_RTS_PA4 SILABS_DBUS_USART1_RTS(0x0, 0x4)
+#define USART1_RTS_PA5 SILABS_DBUS_USART1_RTS(0x0, 0x5)
+#define USART1_RTS_PA6 SILABS_DBUS_USART1_RTS(0x0, 0x6)
+#define USART1_RTS_PA7 SILABS_DBUS_USART1_RTS(0x0, 0x7)
+#define USART1_RTS_PA8 SILABS_DBUS_USART1_RTS(0x0, 0x8)
+#define USART1_RTS_PB0 SILABS_DBUS_USART1_RTS(0x1, 0x0)
+#define USART1_RTS_PB1 SILABS_DBUS_USART1_RTS(0x1, 0x1)
+#define USART1_RTS_PB2 SILABS_DBUS_USART1_RTS(0x1, 0x2)
+#define USART1_RTS_PB3 SILABS_DBUS_USART1_RTS(0x1, 0x3)
+#define USART1_RTS_PB4 SILABS_DBUS_USART1_RTS(0x1, 0x4)
+#define USART1_RX_PA0  SILABS_DBUS_USART1_RX(0x0, 0x0)
+#define USART1_RX_PA1  SILABS_DBUS_USART1_RX(0x0, 0x1)
+#define USART1_RX_PA2  SILABS_DBUS_USART1_RX(0x0, 0x2)
+#define USART1_RX_PA3  SILABS_DBUS_USART1_RX(0x0, 0x3)
+#define USART1_RX_PA4  SILABS_DBUS_USART1_RX(0x0, 0x4)
+#define USART1_RX_PA5  SILABS_DBUS_USART1_RX(0x0, 0x5)
+#define USART1_RX_PA6  SILABS_DBUS_USART1_RX(0x0, 0x6)
+#define USART1_RX_PA7  SILABS_DBUS_USART1_RX(0x0, 0x7)
+#define USART1_RX_PA8  SILABS_DBUS_USART1_RX(0x0, 0x8)
+#define USART1_RX_PB0  SILABS_DBUS_USART1_RX(0x1, 0x0)
+#define USART1_RX_PB1  SILABS_DBUS_USART1_RX(0x1, 0x1)
+#define USART1_RX_PB2  SILABS_DBUS_USART1_RX(0x1, 0x2)
+#define USART1_RX_PB3  SILABS_DBUS_USART1_RX(0x1, 0x3)
+#define USART1_RX_PB4  SILABS_DBUS_USART1_RX(0x1, 0x4)
+#define USART1_CLK_PA0 SILABS_DBUS_USART1_CLK(0x0, 0x0)
+#define USART1_CLK_PA1 SILABS_DBUS_USART1_CLK(0x0, 0x1)
+#define USART1_CLK_PA2 SILABS_DBUS_USART1_CLK(0x0, 0x2)
+#define USART1_CLK_PA3 SILABS_DBUS_USART1_CLK(0x0, 0x3)
+#define USART1_CLK_PA4 SILABS_DBUS_USART1_CLK(0x0, 0x4)
+#define USART1_CLK_PA5 SILABS_DBUS_USART1_CLK(0x0, 0x5)
+#define USART1_CLK_PA6 SILABS_DBUS_USART1_CLK(0x0, 0x6)
+#define USART1_CLK_PA7 SILABS_DBUS_USART1_CLK(0x0, 0x7)
+#define USART1_CLK_PA8 SILABS_DBUS_USART1_CLK(0x0, 0x8)
+#define USART1_CLK_PB0 SILABS_DBUS_USART1_CLK(0x1, 0x0)
+#define USART1_CLK_PB1 SILABS_DBUS_USART1_CLK(0x1, 0x1)
+#define USART1_CLK_PB2 SILABS_DBUS_USART1_CLK(0x1, 0x2)
+#define USART1_CLK_PB3 SILABS_DBUS_USART1_CLK(0x1, 0x3)
+#define USART1_CLK_PB4 SILABS_DBUS_USART1_CLK(0x1, 0x4)
+#define USART1_TX_PA0  SILABS_DBUS_USART1_TX(0x0, 0x0)
+#define USART1_TX_PA1  SILABS_DBUS_USART1_TX(0x0, 0x1)
+#define USART1_TX_PA2  SILABS_DBUS_USART1_TX(0x0, 0x2)
+#define USART1_TX_PA3  SILABS_DBUS_USART1_TX(0x0, 0x3)
+#define USART1_TX_PA4  SILABS_DBUS_USART1_TX(0x0, 0x4)
+#define USART1_TX_PA5  SILABS_DBUS_USART1_TX(0x0, 0x5)
+#define USART1_TX_PA6  SILABS_DBUS_USART1_TX(0x0, 0x6)
+#define USART1_TX_PA7  SILABS_DBUS_USART1_TX(0x0, 0x7)
+#define USART1_TX_PA8  SILABS_DBUS_USART1_TX(0x0, 0x8)
+#define USART1_TX_PB0  SILABS_DBUS_USART1_TX(0x1, 0x0)
+#define USART1_TX_PB1  SILABS_DBUS_USART1_TX(0x1, 0x1)
+#define USART1_TX_PB2  SILABS_DBUS_USART1_TX(0x1, 0x2)
+#define USART1_TX_PB3  SILABS_DBUS_USART1_TX(0x1, 0x3)
+#define USART1_TX_PB4  SILABS_DBUS_USART1_TX(0x1, 0x4)
+#define USART1_CTS_PA0 SILABS_DBUS_USART1_CTS(0x0, 0x0)
+#define USART1_CTS_PA1 SILABS_DBUS_USART1_CTS(0x0, 0x1)
+#define USART1_CTS_PA2 SILABS_DBUS_USART1_CTS(0x0, 0x2)
+#define USART1_CTS_PA3 SILABS_DBUS_USART1_CTS(0x0, 0x3)
+#define USART1_CTS_PA4 SILABS_DBUS_USART1_CTS(0x0, 0x4)
+#define USART1_CTS_PA5 SILABS_DBUS_USART1_CTS(0x0, 0x5)
+#define USART1_CTS_PA6 SILABS_DBUS_USART1_CTS(0x0, 0x6)
+#define USART1_CTS_PA7 SILABS_DBUS_USART1_CTS(0x0, 0x7)
+#define USART1_CTS_PA8 SILABS_DBUS_USART1_CTS(0x0, 0x8)
+#define USART1_CTS_PB0 SILABS_DBUS_USART1_CTS(0x1, 0x0)
+#define USART1_CTS_PB1 SILABS_DBUS_USART1_CTS(0x1, 0x1)
+#define USART1_CTS_PB2 SILABS_DBUS_USART1_CTS(0x1, 0x2)
+#define USART1_CTS_PB3 SILABS_DBUS_USART1_CTS(0x1, 0x3)
+#define USART1_CTS_PB4 SILABS_DBUS_USART1_CTS(0x1, 0x4)
+
+#define ABUS_AEVEN0_IADC0  SILABS_ABUS(0x0, 0x0, 0x1)
+#define ABUS_AEVEN0_ACMP0  SILABS_ABUS(0x0, 0x0, 0x2)
+#define ABUS_AEVEN1_IADC0  SILABS_ABUS(0x0, 0x1, 0x1)
+#define ABUS_AEVEN1_ACMP0  SILABS_ABUS(0x0, 0x1, 0x2)
+#define ABUS_AODD0_IADC0   SILABS_ABUS(0x0, 0x2, 0x1)
+#define ABUS_AODD0_ACMP0   SILABS_ABUS(0x0, 0x2, 0x2)
+#define ABUS_AODD1_IADC0   SILABS_ABUS(0x0, 0x3, 0x1)
+#define ABUS_AODD1_ACMP0   SILABS_ABUS(0x0, 0x3, 0x2)
+#define ABUS_BEVEN0_IADC0  SILABS_ABUS(0x1, 0x0, 0x1)
+#define ABUS_BEVEN0_ACMP0  SILABS_ABUS(0x1, 0x0, 0x2)
+#define ABUS_BEVEN1_IADC0  SILABS_ABUS(0x1, 0x1, 0x1)
+#define ABUS_BEVEN1_ACMP0  SILABS_ABUS(0x1, 0x1, 0x2)
+#define ABUS_BODD0_IADC0   SILABS_ABUS(0x1, 0x2, 0x1)
+#define ABUS_BODD0_ACMP0   SILABS_ABUS(0x1, 0x2, 0x2)
+#define ABUS_BODD1_IADC0   SILABS_ABUS(0x1, 0x3, 0x1)
+#define ABUS_BODD1_ACMP0   SILABS_ABUS(0x1, 0x3, 0x2)
+#define ABUS_CDEVEN0_IADC0 SILABS_ABUS(0x2, 0x0, 0x1)
+#define ABUS_CDEVEN0_ACMP0 SILABS_ABUS(0x2, 0x0, 0x2)
+#define ABUS_CDEVEN1_IADC0 SILABS_ABUS(0x2, 0x1, 0x1)
+#define ABUS_CDEVEN1_ACMP0 SILABS_ABUS(0x2, 0x1, 0x2)
+#define ABUS_CDODD0_IADC0  SILABS_ABUS(0x2, 0x2, 0x1)
+#define ABUS_CDODD0_ACMP0  SILABS_ABUS(0x2, 0x2, 0x2)
+#define ABUS_CDODD1_IADC0  SILABS_ABUS(0x2, 0x3, 0x1)
+#define ABUS_CDODD1_ACMP0  SILABS_ABUS(0x2, 0x3, 0x2)
+
+#endif /* ZEPHYR_DT_BINDINGS_PINCTRL_SILABS_XG29_PINCTRL_H_ */
diff --git a/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h b/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h
index 0c5933c580e..25b76bb2dd5 100644
--- a/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h
+++ b/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl-common.h
@@ -26,9 +26,10 @@
 #define	STM32_PORTN 13
 #define	STM32_PORTO 14
 #define	STM32_PORTP 15	/* IO port P (0xF) */
+#define	STM32_PORTQ 16	/* IO port Q (0x10) */
 
 #ifndef STM32_PORTS_MAX
-#define STM32_PORTS_MAX (STM32_PORTP + 1)
+#define STM32_PORTS_MAX (STM32_PORTQ + 1)
 #endif
 
 /**
diff --git a/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl.h b/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl.h
index 52612f6948d..aa055a5c3f7 100644
--- a/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl.h
+++ b/include/zephyr/dt-bindings/pinctrl/stm32-pinctrl.h
@@ -55,7 +55,7 @@
  * - line [ 5 : 8 ]
  * - port [ 9 : 13 ]
  *
- * @param port Port ('A'..'P')
+ * @param port Port ('A'..'Q')
  * @param line Pin (0..15)
  * @param mode Mode (ANALOG, GPIO_IN, ALTERNATE).
  */
diff --git a/include/zephyr/dt-bindings/power/imx95_power.h b/include/zephyr/dt-bindings/power/imx95_power.h
new file mode 100644
index 00000000000..164080d2d5d
--- /dev/null
+++ b/include/zephyr/dt-bindings/power/imx95_power.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_IMX95_POWER_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_IMX95_POWER_H_
+
+#define IMX95_PD_ANA       0
+#define IMX95_PD_AON       1
+#define IMX95_PD_BBSM      2
+#define IMX95_PD_CAMERA    3
+#define IMX95_PD_CCMSRCGPC 4
+#define IMX95_PD_A55C0     5
+#define IMX95_PD_A55C1     6
+#define IMX95_PD_A55C2     7
+#define IMX95_PD_A55C3     8
+#define IMX95_PD_A55C4     9
+#define IMX95_PD_A55C5     10
+#define IMX95_PD_A55P      11
+#define IMX95_PD_DDR       12
+#define IMX95_PD_DISPLAY   13
+#define IMX95_PD_GPU       14
+#define IMX95_PD_HSIO_TOP  15
+#define IMX95_PD_HSIO_WAON 16
+#define IMX95_PD_M7        17
+#define IMX95_PD_NETC      18
+#define IMX95_PD_NOC       19
+#define IMX95_PD_NPU       20
+#define IMX95_PD_VPU       21
+#define IMX95_PD_WAKEUP    22
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_POWER_IMX95_POWER_H_ */
diff --git a/include/zephyr/dt-bindings/power/stm32_pwr.h b/include/zephyr/dt-bindings/power/stm32_pwr.h
index 8c7962f14ad..b7eee000559 100644
--- a/include/zephyr/dt-bindings/power/stm32_pwr.h
+++ b/include/zephyr/dt-bindings/power/stm32_pwr.h
@@ -7,6 +7,8 @@
 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_POWER_STM32_PWR_H_
 #define ZEPHYR_INCLUDE_DT_BINDINGS_POWER_STM32_PWR_H_
 
+#include <zephyr/dt-bindings/dt-util.h>
+
 /**
  * @brief STM32 power controller
  * @{
@@ -17,9 +19,11 @@
  * @{
  */
 
-#define STM32_PWR_WKUP_PIN_SRC_0	0
-#define STM32_PWR_WKUP_PIN_SRC_1	1
-#define STM32_PWR_WKUP_PIN_SRC_2	(1 << 2)
+/* Use this flag on series where wake-up event source is fixed/not configurable */
+#define STM32_PWR_WKUP_PIN_NOT_MUXED	STM32_PWR_WKUP_EVT_SRC_0
+#define STM32_PWR_WKUP_EVT_SRC_0	BIT(0)
+#define STM32_PWR_WKUP_EVT_SRC_1	BIT(1)
+#define STM32_PWR_WKUP_EVT_SRC_2	BIT(2)
 
 /** @} */
 
diff --git a/include/zephyr/dt-bindings/pwm/renesas_rz_pwm.h b/include/zephyr/dt-bindings/pwm/renesas_rz_pwm.h
new file mode 100644
index 00000000000..8656ce617c5
--- /dev/null
+++ b/include/zephyr/dt-bindings/pwm/renesas_rz_pwm.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RENESAS_RZ_PWM_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_RENESAS_RZ_PWM_H_
+
+#define RZ_PWM_GPT_IO_A 0
+#define RZ_PWM_GPT_IO_B 1
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RENESAS_RZ_PWM_H_ */
diff --git a/include/zephyr/dt-bindings/qspi/nxp-s32-qspi.h b/include/zephyr/dt-bindings/qspi/nxp-s32-qspi.h
new file mode 100644
index 00000000000..3de35cec893
--- /dev/null
+++ b/include/zephyr/dt-bindings/qspi/nxp-s32-qspi.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_NXP_S32_QSPI_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_NXP_S32_QSPI_H_
+
+#include <zephyr/dt-bindings/dt-util.h>
+
+/* The QSPI secure attribute and secure policy references */
+#define NXP_S32_QSPI_NON_SECURE	BIT(0)
+#define NXP_S32_QSPI_SECURE	BIT(1)
+#define NXP_S32_QSPI_PRIVILEGE	BIT(2)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_NXP_S32_QSPI_H_ */
diff --git a/include/zephyr/dt-bindings/reset/numaker_m55m1x_reset.h b/include/zephyr/dt-bindings/reset/numaker_m55m1x_reset.h
new file mode 100644
index 00000000000..4410b22c2df
--- /dev/null
+++ b/include/zephyr/dt-bindings/reset/numaker_m55m1x_reset.h
@@ -0,0 +1,210 @@
+/*
+ * Copyright (c) 2025 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M55M1X_RESET_H
+#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_NUMAKER_M55M1X_RESET_H
+
+/* Beginning of M55M1 BSP sys_reg.h reset module copy */
+
+#define SYS_RSTCTL_CHIPRST_Pos           0
+#define SYS_RSTCTL_NPURST_Pos            6
+#define SYS_ACMPRST_ACMP01RST_Pos        0
+#define SYS_ACMPRST_ACMP23RST_Pos        1
+#define SYS_AWFRST_AWF0RST_Pos           0
+#define SYS_BPWMRST_BPWM0RST_Pos         0
+#define SYS_BPWMRST_BPWM1RST_Pos         1
+#define SYS_CANFDRST_CANFD0RST_Pos       0
+#define SYS_CANFDRST_CANFD1RST_Pos       1
+#define SYS_CCAPRST_CCAP0RST_Pos         0
+#define SYS_CRCRST_CRC0RST_Pos           0
+#define SYS_CRYPTORST_CRYPTO0RST_Pos     0
+#define SYS_DACRST_DAC01RST_Pos          0
+#define SYS_DMICRST_DMIC0RST_Pos         0
+#define SYS_EADCRST_EADC0RST_Pos         0
+#define SYS_EBIRST_EBI0RST_Pos           0
+#define SYS_ECAPRST_ECAP0RST_Pos         0
+#define SYS_ECAPRST_ECAP1RST_Pos         1
+#define SYS_ECAPRST_ECAP2RST_Pos         2
+#define SYS_ECAPRST_ECAP3RST_Pos         3
+#define SYS_EMACRST_EMAC0RST_Pos         0
+#define SYS_EPWMRST_EPWM0RST_Pos         0
+#define SYS_EPWMRST_EPWM1RST_Pos         1
+#define SYS_EQEIRST_EQEI0RST_Pos         0
+#define SYS_EQEIRST_EQEI1RST_Pos         1
+#define SYS_EQEIRST_EQEI2RST_Pos         2
+#define SYS_EQEIRST_EQEI3RST_Pos         3
+#define SYS_FMCRST_FMC0RST_Pos           0
+#define SYS_GDMARST_GDMA0RST_Pos         0
+#define SYS_GPIORST_GPIO0RST_Pos         0
+#define SYS_HSOTGRST_HSOTG0RST_Pos       0
+#define SYS_HSUSBDRST_HSUSBD0RST_Pos     0
+#define SYS_HSUSBHRST_HSUSBH0RST_Pos     0
+#define SYS_I2CRST_I2C0RST_Pos           0
+#define SYS_I2CRST_I2C1RST_Pos           1
+#define SYS_I2CRST_I2C2RST_Pos           2
+#define SYS_I2CRST_I2C3RST_Pos           3
+#define SYS_I2SRST_I2S0RST_Pos           0
+#define SYS_I2SRST_I2S1RST_Pos           1
+#define SYS_I3CRST_I3C0RST_Pos           0
+#define SYS_KDFRST_KDF0RST_Pos           0
+#define SYS_KPIRST_KPI0RST_Pos           0
+#define SYS_KSRST_KS0RST_Pos             0
+#define SYS_LPADCRST_LPADC0RST_Pos       0
+#define SYS_LPPDMARST_LPPDMA0RST_Pos     0
+#define SYS_LPGPIORST_LPGPIO0RST_Pos     0
+#define SYS_LPI2CRST_LPI2C0RST_Pos       0
+#define SYS_LPSPIRST_LPSPI0RST_Pos       0
+#define SYS_LPTMRRST_LPTMR0RST_Pos       0
+#define SYS_LPTMRRST_LPTMR1RST_Pos       1
+#define SYS_LPUARTRST_LPUART0RST_Pos     0
+#define SYS_OTFCRST_OTFC0RST_Pos         0
+#define SYS_OTGRST_OTG0RST_Pos           0
+#define SYS_PDMARST_PDMA0RST_Pos         0
+#define SYS_PDMARST_PDMA1RST_Pos         1
+#define SYS_PSIORST_PSIO0RST_Pos         0
+#define SYS_QSPIRST_QSPI0RST_Pos         0
+#define SYS_QSPIRST_QSPI1RST_Pos         1
+#define SYS_RTCRST_RTC0RST_Pos           0
+#define SYS_SCRST_SC0RST_Pos             0
+#define SYS_SCRST_SC1RST_Pos             1
+#define SYS_SCRST_SC2RST_Pos             2
+#define SYS_SCURST_SCU0RST_Pos           0
+#define SYS_SDHRST_SDH0RST_Pos           0
+#define SYS_SDHRST_SDH1RST_Pos           1
+#define SYS_SPIRST_SPI0RST_Pos           0
+#define SYS_SPIRST_SPI1RST_Pos           1
+#define SYS_SPIRST_SPI2RST_Pos           2
+#define SYS_SPIRST_SPI3RST_Pos           3
+#define SYS_SPIMRST_SPIM0RST_Pos         0
+#define SYS_TMRRST_TMR0RST_Pos           0
+#define SYS_TMRRST_TMR1RST_Pos           1
+#define SYS_TMRRST_TMR2RST_Pos           2
+#define SYS_TMRRST_TMR3RST_Pos           3
+#define SYS_TRNGRST_TRNG0RST_Pos         0
+#define SYS_TTMRRST_TTMR0RST_Pos         0
+#define SYS_TTMRRST_TTMR1RST_Pos         1
+#define SYS_UARTRST_UART0RST_Pos         0
+#define SYS_UARTRST_UART1RST_Pos         1
+#define SYS_UARTRST_UART2RST_Pos         2
+#define SYS_UARTRST_UART3RST_Pos         3
+#define SYS_UARTRST_UART4RST_Pos         4
+#define SYS_UARTRST_UART5RST_Pos         5
+#define SYS_UARTRST_UART6RST_Pos         6
+#define SYS_UARTRST_UART7RST_Pos         7
+#define SYS_UARTRST_UART8RST_Pos         8
+#define SYS_UARTRST_UART9RST_Pos         9
+#define SYS_USBDRST_USBD0RST_Pos         0
+#define SYS_USBHRST_USBH0RST_Pos         0
+#define SYS_USCIRST_USCI0RST_Pos         0
+#define SYS_UTCPDRST_UTCPD0RST_Pos       0
+#define SYS_WWDTRST_WWDT0RST_Pos         0
+#define SYS_WWDTRST_WWDT1RST_Pos         1
+
+/* End of M55M1 BSP sys_reg.h reset module copy */
+
+/* Beginning of M55M1 BSP sys.h reset module copy */
+
+/*---------------------------------------------------------------------
+ *  Module Reset Control Resister constant definitions.
+ *---------------------------------------------------------------------
+ */
+
+#define NUMAKER_SYS_ACMP01RST       ((0x200UL<<20) | SYS_ACMPRST_ACMP01RST_Pos)
+#define NUMAKER_SYS_ACMP23RST       ((0x200UL<<20) | SYS_ACMPRST_ACMP23RST_Pos)
+#define NUMAKER_SYS_AWF0RST         ((0x204UL<<20) | SYS_AWFRST_AWF0RST_Pos)
+#define NUMAKER_SYS_BPWM0RST        ((0x208UL<<20) | SYS_BPWMRST_BPWM0RST_Pos)
+#define NUMAKER_SYS_BPWM1RST        ((0x208UL<<20) | SYS_BPWMRST_BPWM1RST_Pos)
+#define NUMAKER_SYS_CANFD0RST       ((0x20CUL<<20) | SYS_CANFDRST_CANFD0RST_Pos)
+#define NUMAKER_SYS_CANFD1RST       ((0x20CUL<<20) | SYS_CANFDRST_CANFD1RST_Pos)
+#define NUMAKER_SYS_CCAP0RST        ((0x210UL<<20) | SYS_CCAPRST_CCAP0RST_Pos)
+#define NUMAKER_SYS_CRC0RST         ((0x214UL<<20) | SYS_CRCRST_CRC0RST_Pos)
+#define NUMAKER_SYS_CRYPTO0RST      ((0x218UL<<20) | SYS_CRYPTORST_CRYPTO0RST_Pos)
+#define NUMAKER_SYS_DAC01RST        ((0x21CUL<<20) | SYS_DACRST_DAC01RST_Pos)
+#define NUMAKER_SYS_DMIC0RST        ((0x220UL<<20) | SYS_DMICRST_DMIC0RST_Pos)
+#define NUMAKER_SYS_EADC0RST        ((0x224UL<<20) | SYS_EADCRST_EADC0RST_Pos)
+#define NUMAKER_SYS_EBI0RST         ((0x228UL<<20) | SYS_EBIRST_EBI0RST_Pos)
+#define NUMAKER_SYS_ECAP0RST        ((0x22CUL<<20) | SYS_ECAPRST_ECAP0RST_Pos)
+#define NUMAKER_SYS_ECAP1RST        ((0x22CUL<<20) | SYS_ECAPRST_ECAP1RST_Pos)
+#define NUMAKER_SYS_ECAP2RST        ((0x22CUL<<20) | SYS_ECAPRST_ECAP2RST_Pos)
+#define NUMAKER_SYS_ECAP3RST        ((0x22CUL<<20) | SYS_ECAPRST_ECAP3RST_Pos)
+#define NUMAKER_SYS_EMAC0RST        ((0x230UL<<20) | SYS_EMACRST_EMAC0RST_Pos)
+#define NUMAKER_SYS_EPWM0RST        ((0x234UL<<20) | SYS_EPWMRST_EPWM0RST_Pos)
+#define NUMAKER_SYS_EPWM1RST        ((0x234UL<<20) | SYS_EPWMRST_EPWM1RST_Pos)
+#define NUMAKER_SYS_EQEI0RST        ((0x238UL<<20) | SYS_EQEIRST_EQEI0RST_Pos)
+#define NUMAKER_SYS_EQEI1RST        ((0x238UL<<20) | SYS_EQEIRST_EQEI1RST_Pos)
+#define NUMAKER_SYS_EQEI2RST        ((0x238UL<<20) | SYS_EQEIRST_EQEI2RST_Pos)
+#define NUMAKER_SYS_EQEI3RST        ((0x238UL<<20) | SYS_EQEIRST_EQEI3RST_Pos)
+#define NUMAKER_SYS_FMC0RST         ((0x23CUL<<20) | SYS_FMCRST_FMC0RST_Pos)
+#define NUMAKER_SYS_GDMA0RST        ((0x240UL<<20) | SYS_GDMARST_GDMA0RST_Pos)
+#define NUMAKER_SYS_GPIO0RST        ((0x244UL<<20) | SYS_GPIORST_GPIO0RST_Pos)
+#define NUMAKER_SYS_HSOTG0RST       ((0x248UL<<20) | SYS_HSOTGRST_HSOTG0RST_Pos)
+#define NUMAKER_SYS_HSUSBD0RST      ((0x24CUL<<20) | SYS_HSUSBDRST_HSUSBD0RST_Pos)
+#define NUMAKER_SYS_HSUSBH0RST      ((0x250UL<<20) | SYS_HSUSBHRST_HSUSBH0RST_Pos)
+#define NUMAKER_SYS_I2C0RST         ((0x254UL<<20) | SYS_I2CRST_I2C0RST_Pos)
+#define NUMAKER_SYS_I2C1RST         ((0x254UL<<20) | SYS_I2CRST_I2C1RST_Pos)
+#define NUMAKER_SYS_I2C2RST         ((0x254UL<<20) | SYS_I2CRST_I2C2RST_Pos)
+#define NUMAKER_SYS_I2C3RST         ((0x254UL<<20) | SYS_I2CRST_I2C3RST_Pos)
+#define NUMAKER_SYS_I2S0RST         ((0x258UL<<20) | SYS_I2SRST_I2S0RST_Pos)
+#define NUMAKER_SYS_I2S1RST         ((0x258UL<<20) | SYS_I2SRST_I2S1RST_Pos)
+#define NUMAKER_SYS_I3C0RST         ((0x25CUL<<20) | SYS_I3CRST_I3C0RST_Pos)
+#define NUMAKER_SYS_KDF0RST         ((0x260UL<<20) | SYS_KDFRST_KDF0RST_Pos)
+#define NUMAKER_SYS_KPI0RST         ((0x264UL<<20) | SYS_KPIRST_KPI0RST_Pos)
+#define NUMAKER_SYS_KS0RST          ((0x268UL<<20) | SYS_KSRST_KS0RST_Pos)
+#define NUMAKER_SYS_LPADC0RST       ((0x26CUL<<20) | SYS_LPADCRST_LPADC0RST_Pos)
+#define NUMAKER_SYS_LPPDMA0RST      ((0x270UL<<20) | SYS_LPPDMARST_LPPDMA0RST_Pos)
+#define NUMAKER_SYS_LPGPIO0RST      ((0x274UL<<20) | SYS_LPGPIORST_LPGPIO0RST_Pos)
+#define NUMAKER_SYS_LPI2C0RST       ((0x278UL<<20) | SYS_LPI2CRST_LPI2C0RST_Pos)
+#define NUMAKER_SYS_LPSPI0RST       ((0x27CUL<<20) | SYS_LPSPIRST_LPSPI0RST_Pos)
+#define NUMAKER_SYS_LPTMR0RST       ((0x280UL<<20) | SYS_LPTMRRST_LPTMR0RST_Pos)
+#define NUMAKER_SYS_LPTMR1RST       ((0x280UL<<20) | SYS_LPTMRRST_LPTMR1RST_Pos)
+#define NUMAKER_SYS_LPUART0RST      ((0x284UL<<20) | SYS_LPUARTRST_LPUART0RST_Pos)
+#define NUMAKER_SYS_NPURST          ((0x004UL<<20) | SYS_RSTCTL_NPURST_Pos)
+#define NUMAKER_SYS_OTFC0RST        ((0x288UL<<20) | SYS_OTFCRST_OTFC0RST_Pos)
+#define NUMAKER_SYS_OTG0RST         ((0x28CUL<<20) | SYS_OTGRST_OTG0RST_Pos)
+#define NUMAKER_SYS_PDMA0RST        ((0x290UL<<20) | SYS_PDMARST_PDMA0RST_Pos)
+#define NUMAKER_SYS_PDMA1RST        ((0x290UL<<20) | SYS_PDMARST_PDMA1RST_Pos)
+#define NUMAKER_SYS_PSIO0RST        ((0x294UL<<20) | SYS_PSIORST_PSIO0RST_Pos)
+#define NUMAKER_SYS_QSPI0RST        ((0x298UL<<20) | SYS_QSPIRST_QSPI0RST_Pos)
+#define NUMAKER_SYS_QSPI1RST        ((0x298UL<<20) | SYS_QSPIRST_QSPI1RST_Pos)
+#define NUMAKER_SYS_RTC0RST         ((0x29CUL<<20) | SYS_RTCRST_RTC0RST_Pos)
+#define NUMAKER_SYS_SC0RST          ((0x2A0UL<<20) | SYS_SCRST_SC0RST_Pos)
+#define NUMAKER_SYS_SC1RST          ((0x2A0UL<<20) | SYS_SCRST_SC1RST_Pos)
+#define NUMAKER_SYS_SC2RST          ((0x2A0UL<<20) | SYS_SCRST_SC2RST_Pos)
+#define NUMAKER_SYS_SCU0RST         ((0x2A4UL<<20) | SYS_SCURST_SCU0RST_Pos)
+#define NUMAKER_SYS_SDH0RST         ((0x2A8UL<<20) | SYS_SDHRST_SDH0RST_Pos)
+#define NUMAKER_SYS_SDH1RST         ((0x2A8UL<<20) | SYS_SDHRST_SDH1RST_Pos)
+#define NUMAKER_SYS_SPI0RST         ((0x2ACUL<<20) | SYS_SPIRST_SPI0RST_Pos)
+#define NUMAKER_SYS_SPI1RST         ((0x2ACUL<<20) | SYS_SPIRST_SPI1RST_Pos)
+#define NUMAKER_SYS_SPI2RST         ((0x2ACUL<<20) | SYS_SPIRST_SPI2RST_Pos)
+#define NUMAKER_SYS_SPI3RST         ((0x2ACUL<<20) | SYS_SPIRST_SPI3RST_Pos)
+#define NUMAKER_SYS_SPIM0RST        ((0x2B0UL<<20) | SYS_SPIMRST_SPIM0RST_Pos)
+#define NUMAKER_SYS_TMR0RST         ((0x2C0UL<<20) | SYS_TMRRST_TMR0RST_Pos)
+#define NUMAKER_SYS_TMR1RST         ((0x2C0UL<<20) | SYS_TMRRST_TMR1RST_Pos)
+#define NUMAKER_SYS_TMR2RST         ((0x2C0UL<<20) | SYS_TMRRST_TMR2RST_Pos)
+#define NUMAKER_SYS_TMR3RST         ((0x2C0UL<<20) | SYS_TMRRST_TMR3RST_Pos)
+#define NUMAKER_SYS_TRNG0RST        ((0x2C4UL<<20) | SYS_TRNGRST_TRNG0RST_Pos)
+#define NUMAKER_SYS_TTMR0RST        ((0x2C8UL<<20) | SYS_TTMRRST_TTMR0RST_Pos)
+#define NUMAKER_SYS_TTMR1RST        ((0x2C8UL<<20) | SYS_TTMRRST_TTMR1RST_Pos)
+#define NUMAKER_SYS_UART0RST        ((0x2CCUL<<20) | SYS_UARTRST_UART0RST_Pos)
+#define NUMAKER_SYS_UART1RST        ((0x2CCUL<<20) | SYS_UARTRST_UART1RST_Pos)
+#define NUMAKER_SYS_UART2RST        ((0x2CCUL<<20) | SYS_UARTRST_UART2RST_Pos)
+#define NUMAKER_SYS_UART3RST        ((0x2CCUL<<20) | SYS_UARTRST_UART3RST_Pos)
+#define NUMAKER_SYS_UART4RST        ((0x2CCUL<<20) | SYS_UARTRST_UART4RST_Pos)
+#define NUMAKER_SYS_UART5RST        ((0x2CCUL<<20) | SYS_UARTRST_UART5RST_Pos)
+#define NUMAKER_SYS_UART6RST        ((0x2CCUL<<20) | SYS_UARTRST_UART6RST_Pos)
+#define NUMAKER_SYS_UART7RST        ((0x2CCUL<<20) | SYS_UARTRST_UART7RST_Pos)
+#define NUMAKER_SYS_UART8RST        ((0x2CCUL<<20) | SYS_UARTRST_UART8RST_Pos)
+#define NUMAKER_SYS_UART9RST        ((0x2CCUL<<20) | SYS_UARTRST_UART9RST_Pos)
+#define NUMAKER_SYS_USBD0RST        ((0x2D0UL<<20) | SYS_USBDRST_USBD0RST_Pos)
+#define NUMAKER_SYS_USBH0RST        ((0x2D4UL<<20) | SYS_USBHRST_USBH0RST_Pos)
+#define NUMAKER_SYS_USCI0RST        ((0x2D8UL<<20) | SYS_USCIRST_USCI0RST_Pos)
+#define NUMAKER_SYS_UTCPD0RST       ((0x2DCUL<<20) | SYS_UTCPDRST_UTCPD0RST_Pos)
+#define NUMAKER_SYS_WWDT0RST        ((0x2E0UL<<20) | SYS_WWDTRST_WWDT0RST_Pos)
+#define NUMAKER_SYS_WWDT1RST        ((0x2E0UL<<20) | SYS_WWDTRST_WWDT1RST_Pos)
+
+/* End of M55M1 BSP sys.h reset module copy */
+
+#endif
diff --git a/include/zephyr/dt-bindings/reset/stm32mp13_reset.h b/include/zephyr/dt-bindings/reset/stm32mp13_reset.h
new file mode 100644
index 00000000000..f393fdb2690
--- /dev/null
+++ b/include/zephyr/dt-bindings/reset/stm32mp13_reset.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP13_RESET_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP13_RESET_H_
+
+/**
+ * Pack RCC register offset and bit in one 32-bit value.
+ *
+ * bits[4..0] stores the reset controller bit in 32bit RCC register
+ * bits[16..5] stores the reset controller set register offset from RCC base
+ * bits[28..17] stores the reset controller clear register offset from RCC base
+ *
+ * @param bus STM32 bus name
+ * @param bit Reset bit
+ */
+#define STM32_RESET(bus, bit)                                                                      \
+	(((STM32_RESET_BUS_##bus##_CLR) << 17U) | ((STM32_RESET_BUS_##bus##_SET) << 5U) | (bit))
+
+/* RCC bus reset register offset */
+#define STM32_RESET_BUS_AHB2_SET   0x6D0
+#define STM32_RESET_BUS_AHB2_CLR   0x6D4
+#define STM32_RESET_BUS_AHB4_SET   0x6E0
+#define STM32_RESET_BUS_AHB4_CLR   0x6E4
+#define STM32_RESET_BUS_AHB5_SET   0x6E8
+#define STM32_RESET_BUS_AHB5_CLR   0x6EC
+#define STM32_RESET_BUS_AHB6_SET   0x6F0
+#define STM32_RESET_BUS_AHB6_CLR   0x6F4
+#define STM32_RESET_BUS_APB1_SET   0x6A0
+#define STM32_RESET_BUS_APB1_CLR   0x6A4
+#define STM32_RESET_BUS_APB2_SET   0x6A8
+#define STM32_RESET_BUS_APB2_CLR   0x6AC
+#define STM32_RESET_BUS_APB3_SET   0x6B0
+#define STM32_RESET_BUS_APB3_CLR   0x6B4
+#define STM32_RESET_BUS_APB4_SET   0x6B8
+#define STM32_RESET_BUS_APB4_CLR   0x6BC
+#define STM32_RESET_BUS_APB5_SET   0x6C0
+#define STM32_RESET_BUS_APB5_CLR   0x6C4
+#define STM32_RESET_BUS_APB6_SET   0x6C8
+#define STM32_RESET_BUS_APB6_CLR   0x6CC
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32MP13_RESET_H_ */
diff --git a/include/zephyr/dt-bindings/reset/stm32n6_reset.h b/include/zephyr/dt-bindings/reset/stm32n6_reset.h
new file mode 100644
index 00000000000..0b645598f08
--- /dev/null
+++ b/include/zephyr/dt-bindings/reset/stm32n6_reset.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32N6_RESET_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32N6_RESET_H_
+
+#include "stm32-common.h"
+
+/* RCC bus reset register offset */
+#define STM32_RESET_BUS_AHB1	0x210
+#define STM32_RESET_BUS_AHB2	0x214
+#define STM32_RESET_BUS_AHB3	0x218
+#define STM32_RESET_BUS_AHB4	0x21C
+#define STM32_RESET_BUS_AHB5	0x220
+#define STM32_RESET_BUS_APB1L	0x224
+#define STM32_RESET_BUS_APB1H	0x228
+#define STM32_RESET_BUS_APB2	0x22C
+#define STM32_RESET_BUS_APB4L	0x234
+#define STM32_RESET_BUS_APB4H	0x238
+#define STM32_RESET_BUS_APB5	0x23C
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_STM32N6_RESET_H_ */
diff --git a/include/zephyr/dt-bindings/sensor/icm45686.h b/include/zephyr/dt-bindings/sensor/icm45686.h
new file mode 100644
index 00000000000..11bf790c822
--- /dev/null
+++ b/include/zephyr/dt-bindings/sensor/icm45686.h
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2024 Intel Corporation
+ * Copyright (c) 2025 Croxel Inc.
+ * Copyright (c) 2025 CogniPilot Foundation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_TDK_ICM45686_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_TDK_ICM45686_H_
+
+/**
+ * @defgroup ICM45686 Invensense (TDK) ICM45686 DT Options
+ * @ingroup sensor_interface
+ * @{
+ */
+
+/**
+ * @defgroup ICM45686_ACCEL_POWER_MODES Accelerometer power modes
+ * @{
+ */
+#define ICM45686_DT_ACCEL_OFF		0
+#define ICM45686_DT_ACCEL_LP		2
+#define ICM45686_DT_ACCEL_LN		3
+/** @} */
+
+/**
+ * @defgroup ICM45686_GYRO_POWER_MODES Gyroscope power modes
+ * @{
+ */
+#define ICM45686_DT_GYRO_OFF		0
+#define ICM45686_DT_GYRO_STANDBY	1
+#define ICM45686_DT_GYRO_LP		2
+#define ICM45686_DT_GYRO_LN		3
+/** @} */
+
+/**
+ * @defgroup ICM45686_ACCEL_SCALE Accelerometer scale options
+ * @{
+ */
+#define ICM45686_DT_ACCEL_FS_32		0
+#define ICM45686_DT_ACCEL_FS_16		1
+#define ICM45686_DT_ACCEL_FS_8		2
+#define ICM45686_DT_ACCEL_FS_4		3
+#define ICM45686_DT_ACCEL_FS_2		4
+/** @} */
+
+/**
+ * @defgroup ICM45686_GYRO_SCALE Gyroscope scale options
+ * @{
+ */
+#define ICM45686_DT_GYRO_FS_4000	0
+#define ICM45686_DT_GYRO_FS_2000	1
+#define ICM45686_DT_GYRO_FS_1000	2
+#define ICM45686_DT_GYRO_FS_500		3
+#define ICM45686_DT_GYRO_FS_250		4
+#define ICM45686_DT_GYRO_FS_125		5
+#define ICM45686_DT_GYRO_FS_62_5	6
+#define ICM45686_DT_GYRO_FS_31_25	7
+#define ICM45686_DT_GYRO_FS_15_625	8
+/** @} */
+
+/**
+ * @defgroup ICM45686_ACCEL_DATA_RATE Accelerometer data rate options
+ * @{
+ */
+#define ICM45686_DT_ACCEL_ODR_6400	3 /* LN-mode only */
+#define ICM45686_DT_ACCEL_ODR_3200	4 /* LN-mode only */
+#define ICM45686_DT_ACCEL_ODR_1600	5 /* LN-mode only */
+#define ICM45686_DT_ACCEL_ODR_800	6 /* LN-mode only */
+#define ICM45686_DT_ACCEL_ODR_400	7 /* Both LN-mode and LP-mode */
+#define ICM45686_DT_ACCEL_ODR_200	8 /* Both LN-mode and LP-mode */
+#define ICM45686_DT_ACCEL_ODR_100	9 /* Both LN-mode and LP-mode */
+#define ICM45686_DT_ACCEL_ODR_50	10 /* Both LN-mode and LP-mode */
+#define ICM45686_DT_ACCEL_ODR_25	11 /* Both LN-mode and LP-mode */
+#define ICM45686_DT_ACCEL_ODR_12_5	12 /* Both LN-mode and LP-mode */
+#define ICM45686_DT_ACCEL_ODR_6_25	13 /* LP-mode only */
+#define ICM45686_DT_ACCEL_ODR_3_125	14 /* LP-mode only */
+#define ICM45686_DT_ACCEL_ODR_1_5625	15 /* LP-mode only */
+/** @} */
+
+/**
+ * @defgroup ICM45686_GYRO_DATA_RATE Gyroscope data rate options
+ * @{
+ */
+#define ICM45686_DT_GYRO_ODR_6400	3 /* LN-mode only */
+#define ICM45686_DT_GYRO_ODR_3200	4 /* LN-mode only */
+#define ICM45686_DT_GYRO_ODR_1600	5 /* LN-mode only */
+#define ICM45686_DT_GYRO_ODR_800	6 /* LN-mode only */
+#define ICM45686_DT_GYRO_ODR_400	7 /* Both LN-mode and LP-mode */
+#define ICM45686_DT_GYRO_ODR_200	8 /* Both LN-mode and LP-mode */
+#define ICM45686_DT_GYRO_ODR_100	9 /* Both LN-mode and LP-mode */
+#define ICM45686_DT_GYRO_ODR_50		10 /* Both LN-mode and LP-mode */
+#define ICM45686_DT_GYRO_ODR_25		11 /* Both LN-mode and LP-mode */
+#define ICM45686_DT_GYRO_ODR_12_5	12 /* Both LN-mode and LP-mode */
+#define ICM45686_DT_GYRO_ODR_6_25	13 /* LP-mode only */
+#define ICM45686_DT_GYRO_ODR_3_125	14 /* LP-mode only */
+#define ICM45686_DT_GYRO_ODR_1_5625	15 /* LP-mode only */
+/** @} */
+
+/**
+ * @defgroup ICM45686_GYRO_LPF Gyroscope Low-pass Filtering options
+ * @{
+ */
+#define ICM45686_DT_GYRO_LPF_BW_OFF	0
+#define ICM45686_DT_GYRO_LPF_BW_1_4	1
+#define ICM45686_DT_GYRO_LPF_BW_1_8	2
+#define ICM45686_DT_GYRO_LPF_BW_1_16	3
+#define ICM45686_DT_GYRO_LPF_BW_1_32	4
+#define ICM45686_DT_GYRO_LPF_BW_1_64	5
+#define ICM45686_DT_GYRO_LPF_BW_1_128	6
+/** @} */
+
+/**
+ * @defgroup ICM45686_ACCEL_LPF Accelerometer Low-pass Filtering options
+ * @{
+ */
+#define ICM45686_DT_ACCEL_LPF_BW_OFF	0
+#define ICM45686_DT_ACCEL_LPF_BW_1_4	1
+#define ICM45686_DT_ACCEL_LPF_BW_1_8	2
+#define ICM45686_DT_ACCEL_LPF_BW_1_16	3
+#define ICM45686_DT_ACCEL_LPF_BW_1_32	4
+#define ICM45686_DT_ACCEL_LPF_BW_1_64	5
+#define ICM45686_DT_ACCEL_LPF_BW_1_128	6
+/** @} */
+
+
+/** @} */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_TDK_ICM45686_H_ */
diff --git a/include/zephyr/dt-bindings/sensor/it51xxx_tach.h b/include/zephyr/dt-bindings/sensor/it51xxx_tach.h
new file mode 100644
index 00000000000..c8b9fa28441
--- /dev/null
+++ b/include/zephyr/dt-bindings/sensor/it51xxx_tach.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025 ITE Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_ITE_TACH_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_ITE_TACH_H_
+
+/**
+ * @name Tachometer input pin
+ * @{
+ */
+
+/** Tachometer input from pin A */
+#define IT51XXX_TACH_INPUT_PIN_A	0
+/** Tachometer input from pin B */
+#define IT51XXX_TACH_INPUT_PIN_B	1
+
+/** @} */
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_SENSOR_ITE_TACH_H_ */
diff --git a/include/zephyr/dt-bindings/sensor/lsm6dsv16x.h b/include/zephyr/dt-bindings/sensor/lsm6dsv16x.h
index 9cb142b2ed6..9f3b5afda2d 100644
--- a/include/zephyr/dt-bindings/sensor/lsm6dsv16x.h
+++ b/include/zephyr/dt-bindings/sensor/lsm6dsv16x.h
@@ -7,10 +7,14 @@
 #define ZEPHYR_INCLUDE_DT_BINDINGS_ST_LSM6DSV16X_H_
 
 /* Accel range */
-#define	LSM6DSV16X_DT_FS_2G			0
-#define	LSM6DSV16X_DT_FS_4G			1
-#define	LSM6DSV16X_DT_FS_8G			2
-#define	LSM6DSV16X_DT_FS_16G			3
+#define	LSM6DSV16X_DT_FS_2G			2
+#define	LSM6DSV16X_DT_FS_4G			4
+#define	LSM6DSV16X_DT_FS_8G			8
+#define	LSM6DSV16X_DT_FS_16G			16
+#define LSM6DSV32X_DT_FS_4G                     4
+#define LSM6DSV32X_DT_FS_8G                     8
+#define LSM6DSV32X_DT_FS_16G                    16
+#define LSM6DSV32X_DT_FS_32G                    32
 
 /* Gyro range */
 #define	LSM6DSV16X_DT_FS_125DPS			0x0
diff --git a/include/zephyr/dt-bindings/sensor/tmp114.h b/include/zephyr/dt-bindings/sensor/tmp114.h
new file mode 100644
index 00000000000..8bd96572122
--- /dev/null
+++ b/include/zephyr/dt-bindings/sensor/tmp114.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2024 Fredrik Gihl
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_TI_TMP114_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_TI_TMP114_H_
+
+/**
+ * @defgroup TMP114 Texas Instruments (TI) TMP114 DT Options
+ * @ingroup sensor_interface
+ * @{
+ */
+
+/**
+ * @defgroup TMP114_ODR Temperature output data rate
+ * @{
+ */
+#define TMP114_DT_ODR_6_4_MS   0
+#define TMP114_DT_ODR_31_25_MS 1
+#define TMP114_DT_ODR_62_5_MS  2
+#define TMP114_DT_ODR_125_MS   3
+#define TMP114_DT_ODR_250_MS   4
+#define TMP114_DT_ODR_500_MS   5
+#define TMP114_DT_ODR_1000_MS  6
+#define TMP114_DT_ODR_2000_MS  7
+/** @} */
+
+/** @} */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_TI_TMP114_H_ */
diff --git a/include/zephyr/dt-bindings/sensor/tmp116.h b/include/zephyr/dt-bindings/sensor/tmp116.h
deleted file mode 100644
index fa7c1363ec1..00000000000
--- a/include/zephyr/dt-bindings/sensor/tmp116.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (c) 2024 Vitrolife A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_TI_TMP116_H_
-#define ZEPHYR_INCLUDE_DT_BINDINGS_TI_TMP116_H_
-
-/**
- * @defgroup TMP116 Texas Instruments (TI) TMP116 DT Options
- * @ingroup sensor_interface
- * @{
- */
-
-/**
- * @defgroup TMP116_ODR Temperature output data rate
- * @{
- */
-#define TMP116_DT_ODR_15_5_MS  0
-#define TMP116_DT_ODR_125_MS   0x80
-#define TMP116_DT_ODR_250_MS   0x100
-#define TMP116_DT_ODR_500_MS   0x180
-#define TMP116_DT_ODR_1000_MS  0x200
-#define TMP116_DT_ODR_4000_MS  0x280
-#define TMP116_DT_ODR_8000_MS  0x300
-#define TMP116_DT_ODR_16000_MS 0x380
-/** @} */
-
-/** @} */
-
-#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_TI_TMP116_H_ */
diff --git a/include/zephyr/dt-bindings/sensor/tmp11x.h b/include/zephyr/dt-bindings/sensor/tmp11x.h
new file mode 100644
index 00000000000..b95774fd54d
--- /dev/null
+++ b/include/zephyr/dt-bindings/sensor/tmp11x.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2024 Vitrolife A/S
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_TI_TMP11X_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_TI_TMP11X_H_
+
+/**
+ * @defgroup TMP11X Texas Instruments (TI) TMP11X DT Options
+ * @ingroup sensor_interface
+ * @{
+ */
+
+/**
+ * @defgroup TMP11X_ODR Temperature output data rate
+ * @{
+ */
+#define TMP11X_DT_ODR_15_5_MS  0
+#define TMP11X_DT_ODR_125_MS   0x80
+#define TMP11X_DT_ODR_250_MS   0x100
+#define TMP11X_DT_ODR_500_MS   0x180
+#define TMP11X_DT_ODR_1000_MS  0x200
+#define TMP11X_DT_ODR_4000_MS  0x280
+#define TMP11X_DT_ODR_8000_MS  0x300
+#define TMP11X_DT_ODR_16000_MS 0x380
+/** @} */
+
+/**
+ * @defgroup TMP11X_OS Temperature average sample count
+ * @{
+ */
+#define TMP11X_DT_OVERSAMPLING_1  0
+#define TMP11X_DT_OVERSAMPLING_8  0x20
+#define TMP11X_DT_OVERSAMPLING_32 0x40
+#define TMP11X_DT_OVERSAMPLING_64 0x60
+/** @} */
+
+/** @} */
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_TI_TMP11X_H_ */
diff --git a/include/zephyr/fs/fs.h b/include/zephyr/fs/fs.h
index 57b7c84d683..e2cf7dff73b 100644
--- a/include/zephyr/fs/fs.h
+++ b/include/zephyr/fs/fs.h
@@ -78,7 +78,7 @@ enum {
 /** Flag requests file system driver to use Disk Access API. When the flag is
  * set to the fs_mount_t.flags prior to fs_mount call, a file system
  * needs to use the Disk Access API, otherwise mount callback for the driver
- * should return -ENOSUP; when the flag is not set the file system driver
+ * should return -ENOTSUP; when the flag is not set the file system driver
  * should use Flash API by default, unless it only supports Disc Access API.
  * When file system will use Disk Access API and the flag is not set, the mount
  * callback for the file system should set the flag on success.
diff --git a/include/zephyr/fs/zms.h b/include/zephyr/fs/zms.h
index 9a514d65818..8b776b426f9 100644
--- a/include/zephyr/fs/zms.h
+++ b/include/zephyr/fs/zms.h
@@ -1,4 +1,5 @@
-/* Copyright (c) 2024 BayLibre SAS
+/* Copyright (c) 2018 Laczen
+ * Copyright (c) 2024 BayLibre SAS
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -91,7 +92,8 @@ struct zms_fs {
 int zms_mount(struct zms_fs *fs);
 
 /**
- * @brief Clear the ZMS file system from device.
+ * @brief Clear the ZMS file system from device. The ZMS file system must be re-mounted after this
+ * operation.
  *
  * @param fs Pointer to the file system.
  *
diff --git a/include/zephyr/init.h b/include/zephyr/init.h
index 512ea9f67be..d7f254c3c51 100644
--- a/include/zephyr/init.h
+++ b/include/zephyr/init.h
@@ -41,7 +41,7 @@ extern "C" {
  * - `SMP`: Only available if @kconfig{CONFIG_SMP} is enabled, specific for
  *   SMP.
  *
- * Initialization priority can take a value in the range of 0 to 99.
+ * Initialization priority can take a value in the range of 0 to 999.
  *
  * @note The same infrastructure is used by devices.
  * @{
@@ -49,43 +49,6 @@ extern "C" {
 
 struct device;
 
-/**
- * @brief Initialization function for init entries.
- *
- * Init entries support both the system initialization and the device
- * APIs. Each API has its own init function signature; hence, we have a
- * union to cover both.
- */
-union init_function {
-	/**
-	 * System initialization function.
-	 *
-	 * @retval 0 On success
-	 * @retval -errno If init fails.
-	 */
-	int (*sys)(void);
-	/**
-	 * Device initialization function.
-	 *
-	 * @param dev Device instance.
-	 *
-	 * @retval 0 On success
-	 * @retval -errno If device initialization fails.
-	 */
-	int (*dev)(const struct device *dev);
-#ifdef CONFIG_DEVICE_MUTABLE
-	/**
-	 * Device initialization function (rw).
-	 *
-	 * @param dev Device instance.
-	 *
-	 * @retval 0 On success
-	 * @retval -errno If device initialization fails.
-	 */
-	int (*dev_rw)(struct device *dev);
-#endif
-};
-
 /**
  * @brief Structure to store initialization entry information.
  *
@@ -101,18 +64,16 @@ union init_function {
  * @endinternal
  */
 struct init_entry {
-	/** Initialization function. */
-	union init_function init_fn;
+	/**
+	 * If the init function belongs to a SYS_INIT, this field stored the
+	 * initialization function, otherwise it is set to NULL.
+	 */
+	int (*init_fn)(void);
 	/**
 	 * If the init entry belongs to a device, this fields stores a
 	 * reference to it, otherwise it is set to NULL.
 	 */
-	union {
-		const struct device *dev;
-#ifdef CONFIG_DEVICE_MUTABLE
-		struct device *dev_rw;
-#endif
-	};
+	const struct device *dev;
 };
 
 /** @cond INTERNAL_HIDDEN */
@@ -147,42 +108,9 @@ struct init_entry {
  * linker scripts to sort them according to the specified
  * level/priority/sub-priority.
  */
-#define Z_INIT_ENTRY_SECTION(level, prio, sub_prio)                           \
-	__attribute__((__section__(                                           \
-		".z_init_" #level STRINGIFY(prio)"_" STRINGIFY(sub_prio)"_")))
-
-
-/* Designated initializers where added to C in C99. There were added to
- * C++ 20 years later in a much more restricted form. C99 allows many
- * variations: out of order, mix of designated and not, overlap,
- * override,... but C++ allows none of these. See differences detailed
- * in the P0329R0.pdf C++ proposal.
- * Note __STDC_VERSION__ is undefined when compiling C++.
- */
-#if defined(__STDC_VERSION__) && (__STDC_VERSION__) < 201100
-
-/* Anonymous unions require C11. Some pre-C11 gcc versions have early
- * support for anonymous unions but they require these braces when
- * combined with C99 designated initializers, see longer discussion in
- * #69411.
- * These braces are compatible with any C version but not with C++20.
- */
-#  define Z_INIT_SYS_INIT_DEV_NULL  { .dev = NULL }
-
-#else
-
-/* When using -std=c++20 or higher, g++ (v12.2.0) reject braces for
- * initializing anonymous unions because it is technically a mix of
- * designated and not designated initializers which is not allowed in
- * C++. Interestingly, the _same_ g++ version does accept the braces above
- * when using -std=c++17 or lower!
- * The tests/lib/cpp/cxx/ added by commit 3d9c428d57bf invoke the C++
- * compiler with a range of different `-std=...` parameters without needing
- * any manual configuration.
- */
-#  define Z_INIT_SYS_INIT_DEV_NULL    .dev = NULL
-
-#endif
+#define Z_INIT_ENTRY_SECTION(level, prio, sub_prio)                                                \
+	__attribute__((__section__(                                                                \
+		".z_init_" #level "_P_" STRINGIFY(prio) "_SUB_" STRINGIFY(sub_prio)"_")))
 
 /** @endcond */
 
@@ -238,8 +166,7 @@ struct init_entry {
 #define SYS_INIT_NAMED(name, init_fn_, level, prio)                                       \
 	static const Z_DECL_ALIGN(struct init_entry)                                      \
 		Z_INIT_ENTRY_SECTION(level, prio, 0) __used __noasan                      \
-		Z_INIT_ENTRY_NAME(name) = {.init_fn = {.sys = (init_fn_)},                \
-			Z_INIT_SYS_INIT_DEV_NULL}
+		Z_INIT_ENTRY_NAME(name) = {.init_fn = (init_fn_), .dev = NULL}            \
 
 /** @} */
 
diff --git a/include/zephyr/input/cy8cmbr3xxx.h b/include/zephyr/input/cy8cmbr3xxx.h
new file mode 100644
index 00000000000..a2e3518f166
--- /dev/null
+++ b/include/zephyr/input/cy8cmbr3xxx.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2025 Basalte bv
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_INPUT_CY8CMBR3XXX_H_
+#define ZEPHYR_INCLUDE_INPUT_CY8CMBR3XXX_H_
+
+#include <zephyr/types.h>
+
+#define CY8CMBR3XXX_EZ_CLICK_CONFIG_SIZE 128
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+struct cy8cmbr3xxx_config_data {
+	uint8_t data[CY8CMBR3XXX_EZ_CLICK_CONFIG_SIZE];
+};
+
+/**
+ * @brief Configure the CY8CMBR3xxx device with an EZ-Click generated configuration.
+ *
+ * @param dev Pointer to the input device instance
+ * @param config_data Pointer to the configuration data for the device
+ *
+ * @retval 0 if successful
+ * @retval <0 if failed
+ */
+int cy8cmbr3xxx_configure(const struct device *dev,
+			  const struct cy8cmbr3xxx_config_data *config_data);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ZEPHYR_INCLUDE_INPUT_CY8CMBR3XXX_H_ */
diff --git a/include/zephyr/internal/syscall_handler.h b/include/zephyr/internal/syscall_handler.h
index b48070fad6b..877bb5b4df4 100644
--- a/include/zephyr/internal/syscall_handler.h
+++ b/include/zephyr/internal/syscall_handler.h
@@ -372,9 +372,9 @@ int k_usermode_string_copy(char *dst, const char *src, size_t maxlen);
 #define K_SYSCALL_VERIFY_MSG(expr, fmt, ...) ({ \
 	bool expr_copy = !(expr); \
 	if (expr_copy) { \
-		TOOLCHAIN_IGNORE_WSHADOW_BEGIN \
+		TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_SHADOW) \
 		LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL); \
-		TOOLCHAIN_IGNORE_WSHADOW_END \
+		TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_SHADOW) \
 		LOG_ERR("syscall %s failed check: " fmt, \
 			__func__, ##__VA_ARGS__); \
 	} \
diff --git a/include/zephyr/ipc/icmsg.h b/include/zephyr/ipc/icmsg.h
index 6e4cbaeaa86..41967d75153 100644
--- a/include/zephyr/ipc/icmsg.h
+++ b/include/zephyr/ipc/icmsg.h
@@ -27,14 +27,58 @@ extern "C" {
  */
 
 enum icmsg_state {
+	/** Instance is not initialized yet. In this state: sending will fail, opening allowed.
+	 */
 	ICMSG_STATE_OFF,
-	ICMSG_STATE_BUSY,
-	ICMSG_STATE_READY,
+
+	/** Instance is initializing without session handshake. In this state: sending will fail,
+	 * opening will fail.
+	 */
+	ICMSG_STATE_INITIALIZING_SID_DISABLED,
+
+	/** Instance is initializing with session handshake. It is waiting for remote to acknowledge
+	 * local session id. In this state: sending will fail, opening is allowed (local session id
+	 * will change, so the remote may get unbound() callback).
+	 */
+	ICMSG_STATE_INITIALIZING_SID_ENABLED,
+
+	/** Instance is initializing with detection of session handshake support on remote side.
+	 * It is waiting for remote to acknowledge local session id or to send magic bytes.
+	 * In this state: sending will fail, opening is allowed (local session id
+	 * will change, so the remote may get unbound() callback if it supports it).
+	 */
+	ICMSG_STATE_INITIALIZING_SID_DETECT,
+
+	/** Instance was closed on remote side. The unbound() callback was send on local side.
+	 * In this state: sending will be silently discarded (there may be outdated sends),
+	 * opening is allowed.
+	 */
+	ICMSG_STATE_DISCONNECTED,
+
+	/* Connected states must be at the end. */
+
+	/** Instance is connected without session handshake support. In this state: sending will be
+	 * successful, opening will fail.
+	 */
+	ICMSG_STATE_CONNECTED_SID_DISABLED,
+
+	/** Instance is connected with session handshake support. In this state: sending will be
+	 * successful, opening is allowed (session will change and remote will get unbound()
+	 * callback).
+	 */
+	ICMSG_STATE_CONNECTED_SID_ENABLED,
+};
+
+enum icmsg_unbound_mode {
+	ICMSG_UNBOUND_MODE_DISABLE = ICMSG_STATE_INITIALIZING_SID_DISABLED,
+	ICMSG_UNBOUND_MODE_ENABLE = ICMSG_STATE_INITIALIZING_SID_ENABLED,
+	ICMSG_UNBOUND_MODE_DETECT = ICMSG_STATE_INITIALIZING_SID_DETECT,
 };
 
 struct icmsg_config_t {
 	struct mbox_dt_spec mbox_tx;
 	struct mbox_dt_spec mbox_rx;
+	enum icmsg_unbound_mode unbound_mode;
 };
 
 struct icmsg_data_t {
@@ -52,9 +96,10 @@ struct icmsg_data_t {
 	/* General */
 	const struct icmsg_config_t *cfg;
 #ifdef CONFIG_MULTITHREADING
-	struct k_work_delayable notify_work;
 	struct k_work mbox_work;
 #endif
+	uint16_t remote_sid;
+	uint16_t local_sid;
 	atomic_t state;
 };
 
diff --git a/include/zephyr/ipc/ipc_service.h b/include/zephyr/ipc/ipc_service.h
index 65411a6be1c..dbc0b8b7ee4 100644
--- a/include/zephyr/ipc/ipc_service.h
+++ b/include/zephyr/ipc/ipc_service.h
@@ -151,6 +151,21 @@ struct ipc_service_cb {
 	 */
 	void (*bound)(void *priv);
 
+	/** @brief The endpoint unbound by the remote.
+	 *
+	 *  This callback is called when the endpoint binding is removed. It may happen on
+	 *  different reasons, e.g. when the remote deregistered the endpoint, connection was
+	 *  lost, or remote CPU got reset.
+	 *
+	 *  You may want to do some cleanup, resetting, e.t.c. and after that if you want to bound
+	 *  again, you can register the endpoint. When the remote becomes available again and it
+	 *  also registers the endpoint, the binding will be reestablished and the `bound()`
+	 *  callback will be called.
+	 *
+	 *  @param[in] priv Private user data.
+	 */
+	void (*unbound)(void *priv);
+
 	/** @brief New packet arrived.
 	 *
 	 *  This callback is called when new data is received.
diff --git a/include/zephyr/ipc/pbuf.h b/include/zephyr/ipc/pbuf.h
index 8783cdbbf14..4bc42bfdf45 100644
--- a/include/zephyr/ipc/pbuf.h
+++ b/include/zephyr/ipc/pbuf.h
@@ -47,20 +47,23 @@ extern "C" {
  * The structure contains configuration data.
  */
 struct pbuf_cfg {
-	volatile uint32_t *rd_idx_loc;	/* Address of the variable holding
-					 * index value of the first valid byte
-					 * in data[].
-					 */
-	volatile uint32_t *wr_idx_loc;	/* Address of the variable holding
-					 * index value of the first free byte
-					 * in data[].
-					 */
-	uint32_t dcache_alignment;	/* CPU data cache line size in bytes.
-					 * Used for validation - TODO: To be
-					 * replaced by flags.
-					 */
-	uint32_t len;			/* Length of data[] in bytes. */
-	uint8_t *data_loc;		/* Location of the data[]. */
+	volatile uint32_t *rd_idx_loc;	 /* Address of the variable holding
+					  * index value of the first valid byte
+					  * in data[].
+					  */
+	volatile uint32_t *handshake_loc;/* Address of the variable holding
+					  * handshake information.
+					  */
+	volatile uint32_t *wr_idx_loc;	 /* Address of the variable holding
+					  * index value of the first free byte
+					  * in data[].
+					  */
+	uint32_t dcache_alignment;	 /* CPU data cache line size in bytes.
+					  * Used for validation - TODO: To be
+					  * replaced by flags.
+					  */
+	uint32_t len;			 /* Length of data[] in bytes. */
+	uint8_t *data_loc;		 /* Location of the data[]. */
 };
 
 /**
@@ -111,16 +114,21 @@ struct pbuf {
  * @param mem_addr	Memory address for pbuf.
  * @param size		Size of the memory.
  * @param dcache_align	Data cache alignment.
+ * @param use_handshake	Add handshake word inside shared memory that can be access with
+ *			@ref pbuf_handshake_read and @ref pbuf_handshake_write.
  */
-#define PBUF_CFG_INIT(mem_addr, size, dcache_align)					\
+#define PBUF_CFG_INIT(mem_addr, size, dcache_align, use_handshake)			\
 {											\
 	.rd_idx_loc = (uint32_t *)(mem_addr),						\
-	.wr_idx_loc = (uint32_t *)((uint8_t *)(mem_addr) +				\
-				MAX(dcache_align, _PBUF_IDX_SIZE)),			\
+	.handshake_loc = use_handshake ? (uint32_t *)((uint8_t *)(mem_addr) +		\
+				_PBUF_IDX_SIZE) : NULL,					\
+	.wr_idx_loc = (uint32_t *)((uint8_t *)(mem_addr) + MAX(dcache_align,		\
+				(use_handshake ? 2 : 1) * _PBUF_IDX_SIZE)),		\
 	.data_loc = (uint8_t *)((uint8_t *)(mem_addr) +					\
-				MAX(dcache_align, _PBUF_IDX_SIZE) + _PBUF_IDX_SIZE),	\
-	.len = (uint32_t)((uint32_t)(size) - MAX(dcache_align, _PBUF_IDX_SIZE) -	\
-				_PBUF_IDX_SIZE),					\
+				MAX(dcache_align, (use_handshake ? 2 : 1) *		\
+						  _PBUF_IDX_SIZE) + _PBUF_IDX_SIZE),	\
+	.len = (uint32_t)((uint32_t)(size) - MAX(dcache_align,				\
+			(use_handshake ? 2 : 1) * _PBUF_IDX_SIZE) - _PBUF_IDX_SIZE),	\
 	.dcache_alignment = (dcache_align),						\
 }
 
@@ -140,9 +148,11 @@ struct pbuf {
  * @param name			Name of the pbuf.
  * @param mem_addr		Memory address for pbuf.
  * @param size			Size of the memory.
- * @param dcache_align	Data cache line size.
+ * @param dcache_align		Data cache line size.
+ * @param use_handshake		Add handshake word inside shared memory that can be access with
+ *				@ref pbuf_handshake_read and @ref pbuf_handshake_write.
  */
-#define PBUF_DEFINE(name, mem_addr, size, dcache_align)					\
+#define PBUF_DEFINE(name, mem_addr, size, dcache_align, use_handshake, compatibility)	\
 	BUILD_ASSERT(dcache_align >= 0,							\
 			"Cache line size must be non negative.");			\
 	BUILD_ASSERT((size) > 0 && IS_PTR_ALIGNED_BYTES(size, _PBUF_IDX_SIZE),		\
@@ -151,8 +161,10 @@ struct pbuf {
 			"Misaligned memory.");						\
 	BUILD_ASSERT(size >= (MAX(dcache_align, _PBUF_IDX_SIZE) + _PBUF_IDX_SIZE +	\
 			_PBUF_MIN_DATA_LEN), "Insufficient size.");			\
+	BUILD_ASSERT(!(compatibility) || (dcache_align) >= 8,				\
+		"Data cache alignment must be at least 8 if compatibility is enabled.");\
 	static PBUF_MAYBE_CONST struct pbuf_cfg cfg_##name =				\
-			PBUF_CFG_INIT(mem_addr, size, dcache_align);			\
+			PBUF_CFG_INIT(mem_addr, size, dcache_align, use_handshake);	\
 	static struct pbuf name = {							\
 		.cfg = &cfg_##name,							\
 	}
@@ -223,6 +235,40 @@ int pbuf_write(struct pbuf *pb, const char *buf, uint16_t len);
  */
 int pbuf_read(struct pbuf *pb, char *buf, uint16_t len);
 
+/**
+ * @brief Read handshake word from pbuf.
+ *
+ * The pb must be defined with "PBUF_DEFINE" with "use_handshake" set.
+ *
+ * @param pb		A buffer from which data will be read.
+ * @retval uint32_t	The handshake word value.
+ */
+uint32_t pbuf_handshake_read(struct pbuf *pb);
+
+/**
+ * @brief Write handshake word to pbuf.
+ *
+ * The pb must be defined with "PBUF_DEFINE" with "use_handshake" set.
+ *
+ * @param pb		A buffer to which data will be written.
+ * @param value		A handshake value.
+ */
+void pbuf_handshake_write(struct pbuf *pb, uint32_t value);
+
+/**
+ * @brief Get first buffer from pbuf.
+ *
+ * This function retrieves buffer located at the beginning of queue.
+ * It will be continuous block since it is the first buffer.
+ *
+ * @param pb		A buffer from which data will be read.
+ * @param[out] buf	A pointer to output pointer to the date of the first buffer.
+ * @param[out] len	A pointer to output length the first buffer.
+ * @retval		0 on success.
+ *			-EINVAL when there is no buffer at the beginning of queue.
+ */
+int pbuf_get_initial_buf(struct pbuf *pb, volatile char **buf, uint16_t *len);
+
 /**
  * @}
  */
diff --git a/include/zephyr/irq_multilevel.h b/include/zephyr/irq_multilevel.h
index dc18c3049b6..27d11f672e7 100644
--- a/include/zephyr/irq_multilevel.h
+++ b/include/zephyr/irq_multilevel.h
@@ -32,15 +32,19 @@ typedef union _z_irq {
 		uint32_t l1: CONFIG_1ST_LEVEL_INTERRUPT_BITS;
 		/* Second level interrupt bits */
 		uint32_t l2: CONFIG_2ND_LEVEL_INTERRUPT_BITS;
+#if defined(CONFIG_3RD_LEVEL_INTERRUPTS) || defined(__DOXYGEN__)
 		/* Third level interrupt bits */
 		uint32_t l3: CONFIG_3RD_LEVEL_INTERRUPT_BITS;
+#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
 	} bits;
 
+#if defined(CONFIG_3RD_LEVEL_INTERRUPTS) || defined(__DOXYGEN__)
 	/* Third level IRQ's interrupt controller */
 	struct {
 		/* IRQ of the third level interrupt aggregator */
 		uint32_t irq: CONFIG_1ST_LEVEL_INTERRUPT_BITS + CONFIG_2ND_LEVEL_INTERRUPT_BITS;
 	} l3_intc;
+#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
 
 	/* Second level IRQ's interrupt controller */
 	struct {
@@ -61,16 +65,20 @@ static inline uint32_t _z_l2_irq(_z_irq_t irq)
 	return irq.bits.l2 - 1;
 }
 
+#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
 static inline uint32_t _z_l3_irq(_z_irq_t irq)
 {
 	return irq.bits.l3 - 1;
 }
+#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
 
 static inline unsigned int _z_irq_get_level(_z_irq_t z_irq)
 {
+#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
 	if (z_irq.bits.l3 != 0) {
 		return 3;
 	}
+#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
 
 	if (z_irq.bits.l2 != 0) {
 		return 2;
@@ -142,7 +150,9 @@ static inline unsigned int irq_to_level_2(unsigned int irq)
 		.bits = {
 			.l1 = 0,
 			.l2 = irq + 1,
+#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
 			.l3 = 0,
+#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
 		},
 	};
 
@@ -168,6 +178,7 @@ static inline unsigned int irq_parent_level_2(unsigned int irq)
 	return _z_l1_irq(z_irq);
 }
 
+#if defined(CONFIG_3RD_LEVEL_INTERRUPTS) || defined(__DOXYGEN__)
 /**
  * @brief Return the 3rd level interrupt number
  *
@@ -241,6 +252,7 @@ static inline unsigned int irq_parent_level_3(unsigned int irq)
 
 	return _z_l2_irq(z_irq);
 }
+#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
 
 /**
  * @brief Return the interrupt number for a given level
@@ -256,11 +268,14 @@ static inline unsigned int irq_from_level(unsigned int irq, unsigned int level)
 		return irq;
 	} else if (level == 2) {
 		return irq_from_level_2(irq);
-	} else if (level == 3) {
+	}
+#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
+	else if (level == 3) {
 		return irq_from_level_3(irq);
 	}
+#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
 
-	/* level is higher than 3 */
+	/* level is higher than what's supported */
 	__ASSERT_NO_MSG(false);
 	return irq;
 }
@@ -279,11 +294,14 @@ static inline unsigned int irq_to_level(unsigned int irq, unsigned int level)
 		return irq;
 	} else if (level == 2) {
 		return irq_to_level_2(irq);
-	} else if (level == 3) {
+	}
+#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
+	else if (level == 3) {
 		return irq_to_level_3(irq);
 	}
+#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
 
-	/* level is higher than 3 */
+	/* level is higher than what's supported */
 	__ASSERT_NO_MSG(false);
 	return irq;
 }
@@ -303,11 +321,14 @@ static inline unsigned int irq_parent_level(unsigned int irq, unsigned int level
 		return irq;
 	} else if (level == 2) {
 		return irq_parent_level_2(irq);
-	} else if (level == 3) {
+	}
+#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
+	else if (level == 3) {
 		return irq_parent_level_3(irq);
 	}
+#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
 
-	/* level is higher than 3 */
+	/* level is higher than what's supported */
 	__ASSERT_NO_MSG(false);
 	return irq;
 }
@@ -322,19 +343,24 @@ static inline unsigned int irq_parent_level(unsigned int irq, unsigned int level
 static inline unsigned int irq_get_intc_irq(unsigned int irq)
 {
 	const unsigned int level = irq_get_level(irq);
-
-	__ASSERT_NO_MSG(level <= 3);
 	_z_irq_t z_irq = {
 		.irq = irq,
 	};
 
+#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
+	__ASSERT_NO_MSG(level <= 3);
 	if (level == 3) {
 		return z_irq.l3_intc.irq;
-	} else if (level == 2) {
+	}
+#else
+	__ASSERT_NO_MSG(level <= 2);
+#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
+
+	if (level == 2) {
 		return z_irq.l2_intc.irq;
-	} else {
-		return irq;
 	}
+
+	return irq;
 }
 
 /**
@@ -351,8 +377,12 @@ static inline unsigned int irq_increment(unsigned int irq, unsigned int val)
 		.irq = irq,
 	};
 
-	if (z_irq.bits.l3 != 0) {
+	if (false) {
+		/* so that it evaluates the next condition */
+#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
+	} else if (z_irq.bits.l3 != 0) {
 		z_irq.bits.l3 += val;
+#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
 	} else if (z_irq.bits.l2 != 0) {
 		z_irq.bits.l2 += val;
 	} else {
diff --git a/include/zephyr/kernel.h b/include/zephyr/kernel.h
index a7a474081e2..fd64e9d43b7 100644
--- a/include/zephyr/kernel.h
+++ b/include/zephyr/kernel.h
@@ -22,6 +22,7 @@
 #include <zephyr/tracing/tracing_macros.h>
 #include <zephyr/sys/mem_stats.h>
 #include <zephyr/sys/iterable_sections.h>
+#include <zephyr/sys/ring_buffer.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -331,8 +332,15 @@ void k_thread_foreach_unlocked_filter_by_cpu(unsigned int cpu,
 /**
  * @brief Dynamically allocate a thread stack.
  *
- * Relevant stack creation flags include:
- * - @ref K_USER allocate a userspace thread (requires `CONFIG_USERSPACE=y`)
+ * Dynamically allocate a thread stack either from a pool of thread stacks of
+ * size @kconfig{CONFIG_DYNAMIC_THREAD_POOL_SIZE}, or from the system heap.
+ * Order is determined by the @kconfig{CONFIG_DYNAMIC_THREAD_PREFER_ALLOC} and
+ * @kconfig{CONFIG_DYNAMIC_THREAD_PREFER_POOL} options. Thread stacks from the
+ * pool are of maximum size @kconfig{CONFIG_DYNAMIC_THREAD_STACK_SIZE}.
+ *
+ * @note When no longer required, thread stacks allocated with
+ * `k_thread_stack_alloc()` must be freed with @ref k_thread_stack_free to
+ * avoid leaking memory.
  *
  * @param size Stack size in bytes.
  * @param flags Stack creation flags, or 0.
@@ -340,7 +348,10 @@ void k_thread_foreach_unlocked_filter_by_cpu(unsigned int cpu,
  * @retval the allocated thread stack on success.
  * @retval NULL on failure.
  *
- * @see CONFIG_DYNAMIC_THREAD
+ * Relevant stack creation flags include:
+ * - @ref K_USER allocate a userspace thread (requires @kconfig{CONFIG_USERSPACE})
+ *
+ * @see @kconfig{CONFIG_DYNAMIC_THREAD}
  */
 __syscall k_thread_stack_t *k_thread_stack_alloc(size_t size, int flags);
 
@@ -354,7 +365,7 @@ __syscall k_thread_stack_t *k_thread_stack_alloc(size_t size, int flags);
  * @retval -EINVAL if @p stack is invalid.
  * @retval -ENOSYS if dynamic thread stack allocation is disabled
  *
- * @see CONFIG_DYNAMIC_THREAD
+ * @see @kconfig{CONFIG_DYNAMIC_THREAD}
  */
 __syscall int k_thread_stack_free(k_thread_stack_t *stack);
 
@@ -372,7 +383,7 @@ __syscall int k_thread_stack_free(k_thread_stack_t *stack);
  * K_FP_REGS, and K_SSE_REGS. Multiple options may be specified by separating
  * them using "|" (the logical OR operator).
  *
- * Stack objects passed to this function must be originally defined with
+ * Stack objects passed to this function may be statically allocated with
  * either of these macros in order to be portable:
  *
  * - K_THREAD_STACK_DEFINE() - For stacks that may support either user or
@@ -381,6 +392,9 @@ __syscall int k_thread_stack_free(k_thread_stack_t *stack);
  *   threads only. These stacks use less memory if CONFIG_USERSPACE is
  *   enabled.
  *
+ * Alternatively, the stack may be dynamically allocated using
+ * @ref k_thread_stack_alloc.
+ *
  * The stack_size parameter has constraints. It must either be:
  *
  * - The original size value passed to K_THREAD_STACK_DEFINE() or
@@ -544,9 +558,10 @@ __syscall int k_thread_join(struct k_thread *thread, k_timeout_t timeout);
  *
  * @param timeout Desired duration of sleep.
  *
- * @return Zero if the requested time has elapsed or if the thread was woken up
- * by the \ref k_wakeup call, the time left to sleep rounded up to the nearest
- * millisecond.
+ * @return Zero if the requested time has elapsed or the time left to
+ * sleep rounded up to the nearest millisecond (e.g. if the thread was
+ * awoken by the \ref k_wakeup call).  Will be clamped to INT_MAX in
+ * the case where the remaining time is unrepresentable in an int32_t.
  */
 __syscall int32_t k_sleep(k_timeout_t timeout);
 
@@ -755,7 +770,7 @@ struct _static_thread_data {
 #define Z_THREAD_INIT_DELAY_INITIALIZER(ms) .init_delay_ms = (ms)
 #define Z_THREAD_INIT_DELAY(thread) SYS_TIMEOUT_MS((thread)->init_delay_ms)
 #else
-#define Z_THREAD_INIT_DELAY_INITIALIZER(ms) .init_delay = SYS_TIMEOUT_MS(ms)
+#define Z_THREAD_INIT_DELAY_INITIALIZER(ms) .init_delay = SYS_TIMEOUT_MS_INIT(ms)
 #define Z_THREAD_INIT_DELAY(thread) (thread)->init_delay
 #endif
 
@@ -1481,6 +1496,19 @@ const char *k_thread_state_str(k_tid_t thread_id, char *buf, size_t buf_size);
 #define K_TIMEOUT_ABS_TICKS(t) \
 	Z_TIMEOUT_TICKS(Z_TICK_ABS((k_ticks_t)MAX(t, 0)))
 
+/**
+ * @brief Generates an absolute/uptime timeout value from seconds
+ *
+ * This macro generates a timeout delay that represents an expiration
+ * at the absolute uptime value specified, in seconds.  That is, the
+ * timeout will expire immediately after the system uptime reaches the
+ * specified tick count.
+ *
+ * @param t Second uptime value
+ * @return Timeout delay value
+ */
+#define K_TIMEOUT_ABS_SEC(t) K_TIMEOUT_ABS_TICKS(k_sec_to_ticks_ceil64(t))
+
 /**
  * @brief Generates an absolute/uptime timeout value from milliseconds
  *
@@ -1589,6 +1617,7 @@ struct k_timer {
 	.wait_q = Z_WAIT_Q_INIT(&obj.wait_q), \
 	.expiry_fn = expiry, \
 	.stop_fn = stop, \
+	.period = {}, \
 	.status = 0, \
 	.user_data = 0, \
 	}
@@ -2340,7 +2369,8 @@ struct k_event {
 #define Z_EVENT_INITIALIZER(obj) \
 	{ \
 	.wait_q = Z_WAIT_Q_INIT(&obj.wait_q), \
-	.events = 0 \
+	.events = 0, \
+	.lock = {}, \
 	}
 
 /**
@@ -3419,7 +3449,7 @@ int k_work_busy_get(const struct k_work *work);
 
 /** @brief Test whether a work item is currently pending.
  *
- * Wrapper to determine whether a work item is in a non-idle dstate.
+ * Wrapper to determine whether a work item is in a non-idle state.
  *
  * @note This is a live snapshot of state, which may change before the result
  * is checked.  Use locks where appropriate.
@@ -4587,6 +4617,7 @@ struct k_msgq {
 #define Z_MSGQ_INITIALIZER(obj, q_buffer, q_msg_size, q_max_msgs) \
 	{ \
 	.wait_q = Z_WAIT_Q_INIT(&obj.wait_q), \
+	.lock = {}, \
 	.msg_size = q_msg_size, \
 	.max_msgs = q_max_msgs, \
 	.buffer_start = q_buffer, \
@@ -4595,6 +4626,7 @@ struct k_msgq {
 	.write_ptr = q_buffer, \
 	.used_msgs = 0, \
 	Z_POLL_EVENT_OBJ_INIT(obj) \
+	.flags = 0, \
 	}
 
 /**
@@ -4991,6 +5023,18 @@ void k_mbox_data_get(struct k_mbox_msg *rx_msg, void *buffer);
  * @{
  */
 
+/**
+ * @brief initialize a pipe
+ *
+ * This routine initializes a pipe object, prior to its first use.
+ *
+ * @param pipe Address of the pipe.
+ * @param buffer Address of the pipe's buffer, or NULL if no ring buffer is used.
+ * @param buffer_size Size of the pipe's buffer, or zero if no ring buffer is used.
+ */
+__syscall void k_pipe_init(struct k_pipe *pipe, uint8_t *buffer, size_t buffer_size);
+
+#ifdef CONFIG_PIPES
 /** Pipe Structure */
 struct k_pipe {
 	unsigned char *buffer;          /**< Pipe buffer: may be NULL */
@@ -5061,19 +5105,7 @@ struct k_pipe {
 		Z_PIPE_INITIALIZER(name, _k_pipe_buf_##name, pipe_buffer_size)
 
 /**
- * @brief Initialize a pipe.
- *
- * This routine initializes a pipe object, prior to its first use.
- *
- * @param pipe Address of the pipe.
- * @param buffer Address of the pipe's ring buffer, or NULL if no ring buffer
- *               is used.
- * @param size Size of the pipe's ring buffer (in bytes), or zero if no ring
- *             buffer is used.
- */
-void k_pipe_init(struct k_pipe *pipe, unsigned char *buffer, size_t size);
-
-/**
+ * @deprecated Dynamic allocation of pipe buffers will be removed in the new k_pipe API.
  * @brief Release a pipe's allocated buffer
  *
  * If a pipe object was given a dynamically allocated buffer via
@@ -5084,9 +5116,10 @@ void k_pipe_init(struct k_pipe *pipe, unsigned char *buffer, size_t size);
  * @retval 0 on success
  * @retval -EAGAIN nothing to cleanup
  */
-int k_pipe_cleanup(struct k_pipe *pipe);
+__deprecated int k_pipe_cleanup(struct k_pipe *pipe);
 
 /**
+ * @deprecated Dynamic allocation of pipe buffers will be removed in the new k_pipe API.
  * @brief Initialize a pipe and allocate a buffer for it
  *
  * Storage for the buffer region will be allocated from the calling thread's
@@ -5101,9 +5134,10 @@ int k_pipe_cleanup(struct k_pipe *pipe);
  * @retval 0 on success
  * @retval -ENOMEM if memory couldn't be allocated
  */
-__syscall int k_pipe_alloc_init(struct k_pipe *pipe, size_t size);
+__deprecated __syscall int k_pipe_alloc_init(struct k_pipe *pipe, size_t size);
 
 /**
+ * @deprecated k_pipe_put() is replaced by k_pipe_write(...) in the new k_pipe API.
  * @brief Write data to a pipe.
  *
  * This routine writes up to @a bytes_to_write bytes of data to @a pipe.
@@ -5121,11 +5155,12 @@ __syscall int k_pipe_alloc_init(struct k_pipe *pipe, size_t size);
  * @retval -EAGAIN Waiting period timed out; between zero and @a min_xfer
  *                 minus one data bytes were written.
  */
-__syscall int k_pipe_put(struct k_pipe *pipe, const void *data,
+__deprecated __syscall int k_pipe_put(struct k_pipe *pipe, const void *data,
 			 size_t bytes_to_write, size_t *bytes_written,
 			 size_t min_xfer, k_timeout_t timeout);
 
 /**
+ * @deprecated k_pipe_get() is replaced by k_pipe_read(...) in the new k_pipe API.
  * @brief Read data from a pipe.
  *
  * This routine reads up to @a bytes_to_read bytes of data from @a pipe.
@@ -5144,11 +5179,12 @@ __syscall int k_pipe_put(struct k_pipe *pipe, const void *data,
  * @retval -EAGAIN Waiting period timed out; between zero and @a min_xfer
  *                 minus one data bytes were read.
  */
-__syscall int k_pipe_get(struct k_pipe *pipe, void *data,
+__deprecated  __syscall int k_pipe_get(struct k_pipe *pipe, void *data,
 			 size_t bytes_to_read, size_t *bytes_read,
 			 size_t min_xfer, k_timeout_t timeout);
 
 /**
+ * @deprecated k_pipe_read_avail() will be removed in the new k_pipe API.
  * @brief Query the number of bytes that may be read from @a pipe.
  *
  * @param pipe Address of the pipe.
@@ -5156,9 +5192,10 @@ __syscall int k_pipe_get(struct k_pipe *pipe, void *data,
  * @retval a number n such that 0 <= n <= @ref k_pipe.size; the
  *         result is zero for unbuffered pipes.
  */
-__syscall size_t k_pipe_read_avail(struct k_pipe *pipe);
+__deprecated  __syscall size_t k_pipe_read_avail(struct k_pipe *pipe);
 
 /**
+ * @deprecated k_pipe_write_avail() will be removed in the new k_pipe API.
  * @brief Query the number of bytes that may be written to @a pipe
  *
  * @param pipe Address of the pipe.
@@ -5166,9 +5203,10 @@ __syscall size_t k_pipe_read_avail(struct k_pipe *pipe);
  * @retval a number n such that 0 <= n <= @ref k_pipe.size; the
  *         result is zero for unbuffered pipes.
  */
-__syscall size_t k_pipe_write_avail(struct k_pipe *pipe);
+__deprecated __syscall size_t k_pipe_write_avail(struct k_pipe *pipe);
 
 /**
+ * @deprecated k_pipe_flush() will be removed in the new k_pipe API.
  * @brief Flush the pipe of write data
  *
  * This routine flushes the pipe. Flushing the pipe is equivalent to reading
@@ -5178,9 +5216,10 @@ __syscall size_t k_pipe_write_avail(struct k_pipe *pipe);
  *
  * @param pipe Address of the pipe.
  */
-__syscall void k_pipe_flush(struct k_pipe *pipe);
+__deprecated __syscall void k_pipe_flush(struct k_pipe *pipe);
 
 /**
+ * @deprecated k_pipe_buffer_flush will be removed in the new k_pipe API.
  * @brief Flush the pipe's internal buffer
  *
  * This routine flushes the pipe's internal buffer. This is equivalent to
@@ -5191,14 +5230,129 @@ __syscall void k_pipe_flush(struct k_pipe *pipe);
  *
  * @param pipe Address of the pipe.
  */
-__syscall void k_pipe_buffer_flush(struct k_pipe *pipe);
+__deprecated __syscall void k_pipe_buffer_flush(struct k_pipe *pipe);
 
-/** @} */
+#else /* CONFIG_PIPES */
+
+enum pipe_flags {
+	PIPE_FLAG_OPEN = BIT(0),
+	PIPE_FLAG_RESET = BIT(1),
+};
+
+struct k_pipe {
+	size_t waiting;
+	struct ring_buf buf;
+	struct k_spinlock lock;
+	_wait_q_t data;
+	_wait_q_t space;
+	uint8_t flags;
+
+	Z_DECL_POLL_EVENT
+#ifdef CONFIG_OBJ_CORE_PIPE
+	struct k_obj_core  obj_core;
+#endif
+	SYS_PORT_TRACING_TRACKING_FIELD(k_pipe)
+};
 
 /**
  * @cond INTERNAL_HIDDEN
  */
+#define Z_PIPE_INITIALIZER(obj, pipe_buffer, pipe_buffer_size)	\
+{								\
+	.buf = RING_BUF_INIT(pipe_buffer, pipe_buffer_size),	\
+	.data = Z_WAIT_Q_INIT(&obj.data),			\
+	.space = Z_WAIT_Q_INIT(&obj.space),			\
+	.flags = PIPE_FLAG_OPEN,				\
+	.waiting = 0,						\
+	Z_POLL_EVENT_OBJ_INIT(obj)				\
+}
+/**
+ * INTERNAL_HIDDEN @endcond
+ */
 
+/**
+ * @brief Statically define and initialize a pipe.
+ *
+ * The pipe can be accessed outside the module where it is defined using:
+ *
+ * @code extern struct k_pipe <name>; @endcode
+ *
+ * @param name Name of the pipe.
+ * @param pipe_buffer_size Size of the pipe's ring buffer (in bytes)
+ *                         or zero if no ring buffer is used.
+ * @param pipe_align Alignment of the pipe's ring buffer (power of 2).
+ *
+ */
+#define K_PIPE_DEFINE(name, pipe_buffer_size, pipe_align)		\
+	static unsigned char __noinit __aligned(pipe_align)		\
+		_k_pipe_buf_##name[pipe_buffer_size];			\
+	STRUCT_SECTION_ITERABLE(k_pipe, name) =				\
+		Z_PIPE_INITIALIZER(name, _k_pipe_buf_##name, pipe_buffer_size)
+
+
+/**
+ * @brief Write data to a pipe
+ *
+ * This routine writes up to @a len bytes of data to @a pipe.
+ * If the pipe is full, the routine will block until the data can be written or the timeout expires.
+ *
+ * @param pipe Address of the pipe.
+ * @param data Address of data to write.
+ * @param len Size of data (in bytes).
+ * @param timeout Waiting period to wait for the data to be written.
+ *
+ * @retval number of bytes written on success
+ * @retval -EAGAIN if no data could be written before the timeout expired
+ * @retval -ECANCELED if the write was interrupted by k_pipe_reset(..)
+ * @retval -EPIPE if the pipe was closed
+ */
+__syscall int k_pipe_write(struct k_pipe *pipe, const uint8_t *data, size_t len,
+			   k_timeout_t timeout);
+
+/**
+ * @brief Read data from a pipe
+ * This routine reads up to @a len bytes of data from @a pipe.
+ * If the pipe is empty, the routine will block until the data can be read or the timeout expires.
+ *
+ * @param pipe Address of the pipe.
+ * @param data Address to place the data read from pipe.
+ * @param len Requested number of bytes to read.
+ * @param timeout Waiting period to wait for the data to be read.
+ *
+ * @retval number of bytes read on success
+ * @retval -EAGAIN if no data could be read before the timeout expired
+ * @retval -ECANCELED if the read was interrupted by k_pipe_reset(..)
+ * @retval -EPIPE if the pipe was closed
+ */
+__syscall int k_pipe_read(struct k_pipe *pipe, uint8_t *data, size_t len,
+			  k_timeout_t timeout);
+
+/**
+ * @brief Reset a pipe
+ * This routine resets the pipe, discarding any unread data and unblocking any threads waiting to
+ * write or read, causing the waiting threads to return with -ECANCELED. Calling k_pipe_read(..) or
+ * k_pipe_write(..) when the pipe is resetting but not yet reset will return -ECANCELED.
+ * The pipe is left open after a reset and can be used as normal.
+ *
+ * @param pipe Address of the pipe.
+ */
+__syscall void k_pipe_reset(struct k_pipe *pipe);
+
+/**
+ * @brief Close a pipe
+ *
+ * This routine closes a pipe. Any threads that were blocked on the pipe
+ * will be unblocked and receive an error code.
+ *
+ * @param pipe Address of the pipe.
+ */
+__syscall void k_pipe_close(struct k_pipe *pipe);
+#endif /* CONFIG_PIPES */
+/** @} */
+
+/**
+ * @cond INTERNAL_HIDDEN
+ */
 struct k_mem_slab_info {
 	uint32_t num_blocks;
 	size_t   block_size;
@@ -5647,6 +5801,7 @@ void k_heap_free(struct k_heap *h, void *mem) __attribute_nonnull(1);
 
 /**
  * @defgroup heap_apis Heap APIs
+ * @brief Memory allocation from the Heap
  * @ingroup kernel_apis
  * @{
  */
@@ -5804,6 +5959,8 @@ enum _poll_states_bits {
 
 /**
  * @defgroup poll_apis Async polling APIs
+ * @brief An API to wait concurrently for any one of multiple conditions to be
+ *        fulfilled
  * @ingroup kernel_apis
  * @{
  */
@@ -5895,9 +6052,7 @@ struct k_poll_event {
 		struct k_fifo *fifo, *typed_K_POLL_TYPE_FIFO_DATA_AVAILABLE;
 		struct k_queue *queue, *typed_K_POLL_TYPE_DATA_AVAILABLE;
 		struct k_msgq *msgq, *typed_K_POLL_TYPE_MSGQ_DATA_AVAILABLE;
-#ifdef CONFIG_PIPES
 		struct k_pipe *pipe, *typed_K_POLL_TYPE_PIPE_DATA_AVAILABLE;
-#endif
 	};
 };
 
diff --git a/include/zephyr/kernel/thread.h b/include/zephyr/kernel/thread.h
index fd8e4c02f23..ae43d71115d 100644
--- a/include/zephyr/kernel/thread.h
+++ b/include/zephyr/kernel/thread.h
@@ -105,7 +105,9 @@ struct _thread_base {
 	int prio_deadline;
 #endif /* CONFIG_SCHED_DEADLINE */
 
+#if defined(CONFIG_SCHED_SCALABLE) || defined(CONFIG_WAITQ_SCALABLE)
 	uint32_t order_key;
+#endif
 
 #ifdef CONFIG_SMP
 	/* True for the per-CPU idle threads */
@@ -194,6 +196,7 @@ struct _mem_domain_info {
 	struct k_mem_domain *mem_domain;
 };
 
+typedef struct _mem_domain_info _mem_domain_info_t;
 #endif /* CONFIG_USERSPACE */
 
 #ifdef CONFIG_THREAD_USERSPACE_LOCAL_DATA
diff --git a/include/zephyr/kernel_structs.h b/include/zephyr/kernel_structs.h
index a712a876684..5bf9ae6df1c 100644
--- a/include/zephyr/kernel_structs.h
+++ b/include/zephyr/kernel_structs.h
@@ -217,20 +217,6 @@ struct z_kernel {
 	struct _ready_q ready_q;
 #endif
 
-#ifdef CONFIG_FPU_SHARING
-	/*
-	 * A 'current_sse' field does not exist in addition to the 'current_fp'
-	 * field since it's not possible to divide the IA-32 non-integer
-	 * registers into 2 distinct blocks owned by differing threads.  In
-	 * other words, given that the 'fxnsave/fxrstor' instructions
-	 * save/restore both the X87 FPU and XMM registers, it's not possible
-	 * for a thread to only "own" the XMM registers.
-	 */
-
-	/* thread that owns the FP regs */
-	struct k_thread *current_fp;
-#endif
-
 #if defined(CONFIG_THREAD_MONITOR)
 	struct k_thread *threads; /* singly linked list of ALL threads */
 #endif
@@ -271,6 +257,8 @@ __attribute_const__ struct k_thread *z_smp_current_get(void);
 #define _current _kernel.cpus[0].current
 #endif
 
+#define CPU_ID ((CONFIG_MP_MAX_NUM_CPUS == 1) ? 0 : _current_cpu->id)
+
 /* This is always invoked from a context where preemption is disabled */
 #define z_current_thread_set(thread) ({ _current_cpu->current = (thread); })
 
diff --git a/include/zephyr/kernel_version.h b/include/zephyr/kernel_version.h
index 7a21b437768..909800feeba 100644
--- a/include/zephyr/kernel_version.h
+++ b/include/zephyr/kernel_version.h
@@ -18,6 +18,8 @@ extern "C" {
  * @ingroup kernel_apis
  * @{
  *
+ * @brief Kernel Version APIs
+ *
  * The kernel version has been converted from a string to a four-byte
  * quantity that is divided into two parts.
  *
diff --git a/include/zephyr/linker/common-noinit.ld b/include/zephyr/linker/common-noinit.ld
index fba2221162b..8152629af6a 100644
--- a/include/zephyr/linker/common-noinit.ld
+++ b/include/zephyr/linker/common-noinit.ld
@@ -3,6 +3,7 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+/* Please keep in sync with cmake/linker_script/common/common-noinit.cmake */
 
 SECTION_PROLOGUE(_NOINIT_SECTION_NAME,(NOLOAD),)
 {
diff --git a/include/zephyr/linker/common-ram.ld b/include/zephyr/linker/common-ram.ld
index 1eef183d4ae..97763380526 100644
--- a/include/zephyr/linker/common-ram.ld
+++ b/include/zephyr/linker/common-ram.ld
@@ -1,4 +1,5 @@
 /* SPDX-License-Identifier: Apache-2.0 */
+/* Please keep in sync with cmake/linker_script/common/common-ram.cmake */
 
 #include <zephyr/linker/iterable_sections.h>
 
diff --git a/include/zephyr/linker/common-rom/common-rom-init.ld b/include/zephyr/linker/common-rom/common-rom-init.ld
index 04c504ce44a..2aa1873f9f7 100644
--- a/include/zephyr/linker/common-rom/common-rom-init.ld
+++ b/include/zephyr/linker/common-rom/common-rom-init.ld
@@ -1,76 +1,65 @@
 /* SPDX-License-Identifier: Apache-2.0 */
 
-#ifdef CONFIG_STATIC_INIT_GNU
-	SECTION_PROLOGUE(_CTOR_SECTION_NAME,,)
+#if defined(CONFIG_TOOLCHAIN_SUPPORTS_STATIC_INIT_GNU) || defined(CONFIG_NATIVE_APPLICATION)
+	SECTION_PROLOGUE(init_array,,)
 	{
 		/*
-		 * The compiler fills the constructor pointers table below,
-		 * hence symbol __CTOR_LIST__ must be aligned on word
-		 * boundary.  To align with the C++ standard, the first element
-		 * of the array contains the number of actual constructors. The
-		 * last element is NULL.
-		 *
-		 * The __CTOR_LIST__ and __CTOR_END__ symbols are always defined
-		 * to result in an empty list. This is necessary to fix an issue
-		 * where the glibc process initialization code on native_posix
-		 * platforms calls constructors before Zephyr loads (issue #39347).
-		 *
-		 * Zephyr's start-up code uses the __ZEPHYR_CTOR_LIST__ and
-		 * __ZEHPYR_CTOR_END__ symbols, so these need to be correctly set.
+		 * Add all of the GNU-style constructors in priority order. Note
+		 * that this doesn't build the ctors in the "usual" fashion with
+		 * a length value first and NULL terminator, but we're creating
+		 * an init_array style list and leaving the ctors list empty
+		 */
+#ifdef CONFIG_NATIVE_APPLICATION
+		/* Use the native LIBC constructor code so that any native
+		 * constructors get run before main is invoked
+		 */
+		__init_array_start = .;
+#else
+		__zephyr_init_array_start = .;
+#endif
+		KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*)
+			SORT_BY_INIT_PRIORITY(.ctors.*)))
+		KEEP (*(.init_array .ctors))
+#ifdef CONFIG_NATIVE_APPLICATION
+		__init_array_end = .;
+#else
+		__zephyr_init_array_end = .;
+#endif
+
+#ifdef CONFIG_NATIVE_LIBC
+		/*
+                 * The __CTOR_LIST__ and __CTOR_END__ symbols are always defined
+                 * to result in an empty list.
+		 * Instead, Zephyr's start-up code uses the __zephyr_init_array_start__ and
+		 * __zephyr_init_array_end__ symbols.
+		 * In this way, in native_simulator based targets, the host glibc process
+		 * initialization code will not call the constructors before Zephyr loads.
 		 */
-#ifdef CONFIG_64BIT
-		. = ALIGN(8);
-		__ZEPHYR_CTOR_LIST__ = .;
-		QUAD((__ZEPHYR_CTOR_END__ - __ZEPHYR_CTOR_LIST__) / 8 - 2)
-		KEEP(*(SORT_BY_NAME(".ctors*")))
 		__CTOR_LIST__ = .;
+#ifdef CONFIG_64BIT
 		QUAD(0)
-		__ZEPHYR_CTOR_END__ = .;
 		QUAD(0)
-		__CTOR_END__ = .;
 #else
-		. = ALIGN(4);
-		__ZEPHYR_CTOR_LIST__ = .;
-		LONG((__ZEPHYR_CTOR_END__ - __ZEPHYR_CTOR_LIST__) / 4 - 2)
-		KEEP(*(SORT_BY_NAME(".ctors*")))
-		__CTOR_LIST__ = .;
 		LONG(0)
-		__ZEPHYR_CTOR_END__ = .;
 		LONG(0)
-		__CTOR_END__ = .;
 #endif
-	} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
-
-	SECTION_PROLOGUE(init_array,,)
-	{
+		__CTOR_END__ = .;
+#ifndef CONFIG_NATIVE_APPLICATION
 		/*
-		* Similar to the schenanigans required for the __CTOR_LIST__ and
-		* __CTOR_END__ symbols we define __init_array_start and __init_array_end
-		* to the same address to define an empty list. This prevents the glibc
-		* startup code from calling any global constructors before Zephyr loads.
-		*
-		* Zephyr's start-up code uses the __zephyr_init_array_start and
-		* __zephyr_init_array_end sybmols, so these need to be set correctly.
-		*/
-		. = ALIGN(4);
+		 * Similar to the schenanigans required for the __CTOR_LIST__ and
+		 * __CTOR_END__ symbols we define __init_array_start and __init_array_end
+		 * to the same address to define an empty list. This prevents the glibc
+		 * startup code from calling any global constructors before Zephyr loads.
+		 */
 		__init_array_start = .;
 		__init_array_end = .;
-		__zephyr_init_array_start = .;
-		KEEP(*(SORT_BY_NAME(".init_array*")))
-		__zephyr_init_array_end = .;
+#endif
+#endif
 	} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
 
-#elif defined(CONFIG_TOOLCHAIN_SUPPORTS_STATIC_INIT_GNU) && !defined(CONFIG_NATIVE_APPLICATION)
-	/*
-	 * If the code to invoke constructors is not enabled,
-	 * make sure there aren't any in the application
-	 */
-	SECTION_PROLOGUE(init_array,,)
-	{
-		KEEP(*(SORT_BY_NAME(".ctors*")))
-		KEEP(*(SORT_BY_NAME(".init_array*")))
-	} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
+#if !defined(CONFIG_STATIC_INIT_GNU) && !defined(CONFIG_NATIVE_APPLICATION)
+	ASSERT(__zephyr_init_array_start == __zephyr_init_array_end,
+	       "GNU-style constructors required but STATIC_INIT_GNU not enabled")
+#endif
 
-	ASSERT (SIZEOF(init_array) == 0,
-		"GNU-style constructors required but STATIC_INIT_GNU not enabled")
 #endif
diff --git a/include/zephyr/linker/common-rom/common-rom-kernel-devices.ld b/include/zephyr/linker/common-rom/common-rom-kernel-devices.ld
index c6920b5bec0..1dde21d7adc 100644
--- a/include/zephyr/linker/common-rom/common-rom-kernel-devices.ld
+++ b/include/zephyr/linker/common-rom/common-rom-kernel-devices.ld
@@ -18,9 +18,6 @@
 		CREATE_OBJ_LEVEL(init, APPLICATION)
 		CREATE_OBJ_LEVEL(init, SMP)
 		__init_end = .;
-		__deferred_init_list_start = .;
-		KEEP(*(.z_deferred_init*))
-		__deferred_init_list_end = .;
 	} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
 
 	ITERABLE_SECTION_ROM_NUMERIC(device, Z_LINK_ITERABLE_SUBALIGN)
@@ -70,7 +67,7 @@
 	/* verify we don't have rogue .z_init_<something> initlevel sections */
 	SECTION_PROLOGUE(initlevel_error,,)
 	{
-		KEEP(*(SORT(.z_init_[_A-Z0-9]*)))
+		KEEP(*(SORT(.z_init_*)))
 	}
 	ASSERT(SIZEOF(initlevel_error) == 0, "Undefined initialization levels used.")
 
diff --git a/include/zephyr/linker/common-rom/common-rom-net.ld b/include/zephyr/linker/common-rom/common-rom-net.ld
index 5305f9cf873..2b779e46993 100644
--- a/include/zephyr/linker/common-rom/common-rom-net.ld
+++ b/include/zephyr/linker/common-rom/common-rom-net.ld
@@ -2,6 +2,10 @@
 
 #include <zephyr/linker/iterable_sections.h>
 
+#if defined(CONFIG_NETWORKING)
+	ITERABLE_SECTION_ROM(net_l3_register, Z_LINK_ITERABLE_SUBALIGN)
+#endif
+
 #if defined(CONFIG_NET_SOCKETS)
 	ITERABLE_SECTION_ROM(net_socket_register, Z_LINK_ITERABLE_SUBALIGN)
 #endif
diff --git a/include/zephyr/linker/cplusplus-rom.ld b/include/zephyr/linker/cplusplus-rom.ld
index 5981e2f7b98..0d815d4e69b 100644
--- a/include/zephyr/linker/cplusplus-rom.ld
+++ b/include/zephyr/linker/cplusplus-rom.ld
@@ -13,13 +13,17 @@
 #if defined (CONFIG_CPP_EXCEPTIONS)
 	SECTION_PROLOGUE(.eh_frame_hdr,,)
 	{
+	PROVIDE(__eh_frame_hdr_start = SIZEOF(.eh_frame_hdr) > 0 ? ADDR(.eh_frame_hdr) : 0);
 	*(.eh_frame_hdr)
+	PROVIDE(__eh_frame_hdr_end = SIZEOF(.eh_frame_hdr) > 0 ? . : 0);
 	} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
 
 	SECTION_PROLOGUE(.eh_frame,,)
 	{
+        PROVIDE (__eh_frame_start = .);
 	KEEP (*(SORT_NONE(EXCLUDE_FILE (*crtend.o) .eh_frame)))
 	KEEP (*(SORT_NONE(.eh_frame)))
+        PROVIDE (__eh_frame_end = .);
 	} GROUP_ROM_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
 #endif /* CONFIG_CPP_EXCEPTIONS */
 
diff --git a/include/zephyr/linker/debug-sections.ld b/include/zephyr/linker/debug-sections.ld
index 2a70cccb79e..f9a4e840fef 100644
--- a/include/zephyr/linker/debug-sections.ld
+++ b/include/zephyr/linker/debug-sections.ld
@@ -1,4 +1,5 @@
 /* SPDX-License-Identifier: Apache-2.0 */
+/* Please keep in sync with cmake/linker_script/common/debug-sections.cmake */
 
 	/* following sections are obtained via 'ld --verbose' */
 
diff --git a/include/zephyr/linker/devicetree_regions.h b/include/zephyr/linker/devicetree_regions.h
index 9a0139dfc8e..1735a9b439c 100644
--- a/include/zephyr/linker/devicetree_regions.h
+++ b/include/zephyr/linker/devicetree_regions.h
@@ -211,6 +211,7 @@
  *
  * @param node_id devicetree node identifier
  */
+/* clang-format off */
 #define _SECTION_DECLARE(node_id)								\
 	LINKER_DT_NODE_REGION_NAME_TOKEN(node_id) (NOLOAD) :					\
 	{											\
@@ -221,6 +222,7 @@
 	} > LINKER_DT_NODE_REGION_NAME_TOKEN(node_id)						\
 	_DT_SECTION_SIZE(node_id) = _DT_SECTION_END(node_id) - _DT_SECTION_START(node_id);	\
 	_DT_SECTION_LOAD(node_id) = LOADADDR(LINKER_DT_NODE_REGION_NAME_TOKEN(node_id));
+/* clang-format on */
 
 /** @endcond */
 
diff --git a/include/zephyr/linker/iterable_sections.h b/include/zephyr/linker/iterable_sections.h
index 3eb4e9527b8..c8030c53a1c 100644
--- a/include/zephyr/linker/iterable_sections.h
+++ b/include/zephyr/linker/iterable_sections.h
@@ -12,6 +12,7 @@
  * @{
  */
 
+/* clang-format off */
 #define Z_LINK_ITERABLE(struct_type) \
 	_CONCAT(_##struct_type, _list_start) = .; \
 	KEEP(*(SORT_BY_NAME(._##struct_type.static.*))); \
@@ -21,6 +22,9 @@
 	_CONCAT(_##struct_type, _list_start) = .; \
 	KEEP(*(SORT(._##struct_type.static.*_?_*))); \
 	KEEP(*(SORT(._##struct_type.static.*_??_*))); \
+	KEEP(*(SORT(._##struct_type.static.*_???_*))); \
+	KEEP(*(SORT(._##struct_type.static.*_????_*))); \
+	KEEP(*(SORT(._##struct_type.static.*_?????_*))); \
 	_CONCAT(_##struct_type, _list_end) = .
 
 #define Z_LINK_ITERABLE_ALIGNED(struct_type, align) \
@@ -31,6 +35,7 @@
 	_CONCAT(_##struct_type, _list_start) = .; \
 	*(SORT_BY_NAME(._##struct_type.static.*)); \
 	_CONCAT(_##struct_type, _list_end) = .
+/* clang-format on */
 
 #define Z_LINK_ITERABLE_SUBALIGN CONFIG_LINKER_ITERABLE_SUBALIGN
 
diff --git a/include/zephyr/linker/kobject-data.ld b/include/zephyr/linker/kobject-data.ld
index 573680b235e..f3bd54ca7c6 100644
--- a/include/zephyr/linker/kobject-data.ld
+++ b/include/zephyr/linker/kobject-data.ld
@@ -4,6 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+/* Please keep in sync with cmake/linker_script/common/kobject-data.cmake */
+
 #ifdef CONFIG_USERSPACE
 
 	z_kobject_data_begin = .;
diff --git a/include/zephyr/linker/kobject-priv-stacks.ld b/include/zephyr/linker/kobject-priv-stacks.ld
index 53bd508927e..5cc2ee713a0 100644
--- a/include/zephyr/linker/kobject-priv-stacks.ld
+++ b/include/zephyr/linker/kobject-priv-stacks.ld
@@ -3,6 +3,7 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+/* Please keep in sync with cmake/linker_script/common/kobject-priv-stacks.cmake */
 
 #ifdef CONFIG_USERSPACE
 #ifdef CONFIG_GEN_PRIV_STACKS
diff --git a/include/zephyr/linker/kobject-rom.ld b/include/zephyr/linker/kobject-rom.ld
index 1bb6ee10c15..cbe664aa30c 100644
--- a/include/zephyr/linker/kobject-rom.ld
+++ b/include/zephyr/linker/kobject-rom.ld
@@ -3,6 +3,7 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+/* Please keep in sync with cmake/linker_script/common/kobject-rom.cmake */
 
 #ifdef CONFIG_USERSPACE
 
diff --git a/include/zephyr/linker/kobject-text.ld b/include/zephyr/linker/kobject-text.ld
index b1c2b69e6df..0c9805c86f5 100644
--- a/include/zephyr/linker/kobject-text.ld
+++ b/include/zephyr/linker/kobject-text.ld
@@ -1,4 +1,5 @@
 /* SPDX-License-Identifier: Apache-2.0 */
+/* Plase keep in sync with cmake/linker_script/common/kobject-text.cmake */
 
 #ifdef CONFIG_USERSPACE
 	/* We need to reserve room for the gperf generated hash functions.
diff --git a/include/zephyr/linker/linker-defs.h b/include/zephyr/linker/linker-defs.h
index 14bbc250f4c..16e0dc2405b 100644
--- a/include/zephyr/linker/linker-defs.h
+++ b/include/zephyr/linker/linker-defs.h
@@ -44,10 +44,13 @@
  * (sorted by priority). Ensure the objects aren't discarded if there is
  * no direct reference to them
  */
+/* clang-format off */
 #define CREATE_OBJ_LEVEL(object, level)				\
 		__##object##_##level##_start = .;		\
-		KEEP(*(SORT(.z_##object##_##level?_*)));	\
-		KEEP(*(SORT(.z_##object##_##level??_*)));
+		KEEP(*(SORT(.z_##object##_##level##_P_?_*)));	\
+		KEEP(*(SORT(.z_##object##_##level##_P_??_*)));	\
+		KEEP(*(SORT(.z_##object##_##level##_P_???_*)));
+/* clang-format on */
 
 /*
  * link in shell initialization objects for all modules that use shell and
@@ -151,6 +154,12 @@ extern char _vector_end[];
 extern char __vector_relay_table[];
 #endif
 
+#ifdef CONFIG_SRAM_VECTOR_TABLE
+extern char _sram_vector_start[];
+extern char _sram_vector_end[];
+extern char _sram_vector_size[];
+#endif
+
 #ifdef CONFIG_COVERAGE_GCOV
 extern char __gcov_bss_start[];
 extern char __gcov_bss_end[];
@@ -161,7 +170,7 @@ extern char __gcov_bss_size[];
 extern char _end[];
 
 #if (DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_ccm)))
-extern char __ccm_data_rom_start[];
+extern char __ccm_data_load_start[];
 extern char __ccm_start[];
 extern char __ccm_data_start[];
 extern char __ccm_data_end[];
@@ -222,6 +231,7 @@ extern char __sg_size[];
 extern char _nocache_ram_start[];
 extern char _nocache_ram_end[];
 extern char _nocache_ram_size[];
+extern char _nocache_load_start[];
 #endif /* CONFIG_NOCACHE_MEMORY */
 
 /* Memory owned by the kernel. Start and end will be aligned for memory
diff --git a/include/zephyr/linker/ram-end.ld b/include/zephyr/linker/ram-end.ld
index 71d4571e0fb..77be2a57083 100644
--- a/include/zephyr/linker/ram-end.ld
+++ b/include/zephyr/linker/ram-end.ld
@@ -1,5 +1,6 @@
-/*
- * Added after the very last allocation that might land in RAM to define the various
+/* Please keep in sync with cmake/linker_script/common/ram-end.cmake */
+
+/* Added after the very last allocation that might land in RAM to define the various
  * end-of-used-memory symbols
  */
 
diff --git a/include/zephyr/linker/section_tags.h b/include/zephyr/linker/section_tags.h
index 560d7611b7a..ab73c044501 100644
--- a/include/zephyr/linker/section_tags.h
+++ b/include/zephyr/linker/section_tags.h
@@ -47,6 +47,7 @@
 #define __imx_boot_container_section Z_GENERIC_SECTION(_IMX_BOOT_CONTAINER_SECTION_NAME)
 #define __stm32_sdram1_section Z_GENERIC_SECTION(_STM32_SDRAM1_SECTION_NAME)
 #define __stm32_sdram2_section Z_GENERIC_SECTION(_STM32_SDRAM2_SECTION_NAME)
+#define __stm32_psram_section Z_GENERIC_SECTION(_STM32_PSRAM_SECTION_NAME)
 #define __stm32_backup_sram_section Z_GENERIC_SECTION(_STM32_BACKUP_SRAM_SECTION_NAME)
 #endif /* CONFIG_ARM */
 
diff --git a/include/zephyr/linker/sections.h b/include/zephyr/linker/sections.h
index 36159427fa6..dc6fce72e6b 100644
--- a/include/zephyr/linker/sections.h
+++ b/include/zephyr/linker/sections.h
@@ -71,6 +71,7 @@
 
 #define _STM32_SDRAM1_SECTION_NAME	.stm32_sdram1
 #define _STM32_SDRAM2_SECTION_NAME	.stm32_sdram2
+#define _STM32_PSRAM_SECTION_NAME	.stm32_psram
 
 #define _STM32_BACKUP_SRAM_SECTION_NAME	.stm32_backup_sram
 
diff --git a/include/zephyr/linker/thread-local-storage.ld b/include/zephyr/linker/thread-local-storage.ld
index 5a1313e1c8c..d2bc2b2b334 100644
--- a/include/zephyr/linker/thread-local-storage.ld
+++ b/include/zephyr/linker/thread-local-storage.ld
@@ -1,4 +1,5 @@
 /* SPDX-License-Identifier: Apache-2.0 */
+/* Please keep in sync with cmake/linker_script/common/thread-local-storage.cmake */
 
 #ifdef CONFIG_THREAD_LOCAL_STORAGE
 
diff --git a/include/zephyr/linker/utils.h b/include/zephyr/linker/utils.h
index c6f9177c42b..5b92f5b48dd 100644
--- a/include/zephyr/linker/utils.h
+++ b/include/zephyr/linker/utils.h
@@ -24,8 +24,8 @@
 static inline bool linker_is_in_rodata(const void *addr)
 {
 #if defined(CONFIG_LINKER_USE_PINNED_SECTION)
-	extern const char lnkr_pinned_rodata_start[];
-	extern const char lnkr_pinned_rodata_end[];
+	extern char lnkr_pinned_rodata_start[];
+	extern char lnkr_pinned_rodata_end[];
 
 	if (((const char *)addr >= (const char *)lnkr_pinned_rodata_start) &&
 	    ((const char *)addr < (const char *)lnkr_pinned_rodata_end)) {
diff --git a/include/zephyr/llext/buf_loader.h b/include/zephyr/llext/buf_loader.h
index 9d5dd1c9848..603685c28c2 100644
--- a/include/zephyr/llext/buf_loader.h
+++ b/include/zephyr/llext/buf_loader.h
@@ -39,15 +39,8 @@ struct llext_buf_loader {
 int llext_buf_read(struct llext_loader *ldr, void *buf, size_t len);
 int llext_buf_seek(struct llext_loader *ldr, size_t pos);
 void *llext_buf_peek(struct llext_loader *ldr, size_t pos);
-/** @endcond */
 
-/**
- * @brief Initializer for an llext_buf_loader structure
- *
- * @param _buf Buffer containing the ELF binary
- * @param _buf_len Buffer length in bytes
- */
-#define LLEXT_BUF_LOADER(_buf, _buf_len)                                                           \
+#define Z_LLEXT_BUF_LOADER(_buf, _buf_len, _storage)                                               \
 	{                                                                                          \
 		.loader =                                                                          \
 			{                                                                          \
@@ -56,11 +49,72 @@ void *llext_buf_peek(struct llext_loader *ldr, size_t pos);
 				.seek = llext_buf_seek,                                            \
 				.peek = llext_buf_peek,                                            \
 				.finalize = NULL,                                                  \
+				.storage = _storage,                                               \
 			},                                                                         \
 		.buf = (_buf),                                                                     \
 		.len = (_buf_len),                                                                 \
 		.pos = 0,                                                                          \
 	}
+/** @endcond */
+
+/**
+ * @brief Initializer for an llext_buf_loader structure
+ *
+ * The storage type for the provided buffer depends on the value of the
+ * @kconfig{CONFIG_LLEXT_STORAGE_WRITABLE} option: if it is defined, the
+ * buffer is assumed to be writable; otherwise it is assumed to be persistent.
+ *
+ * Consider using one of the alternative macros instead.
+ *
+ * @see LLEXT_TEMPORARY_BUF_LOADER
+ * @see LLEXT_PERSISTENT_BUF_LOADER
+ * @see LLEXT_WRITABLE_BUF_LOADER
+ *
+ * @param _buf Buffer containing the ELF binary
+ * @param _buf_len Buffer length in bytes
+ */
+#define LLEXT_BUF_LOADER(_buf, _buf_len) \
+	Z_LLEXT_BUF_LOADER(_buf, _buf_len,                                                         \
+			   IS_ENABLED(CONFIG_LLEXT_STORAGE_WRITABLE) ?                             \
+				LLEXT_STORAGE_WRITABLE : LLEXT_STORAGE_PERSISTENT)
+
+/* @brief Initialize an llext_buf_loader structure for a temporary buffer
+ *
+ * ELF data from the specified buffer can only be used during llext_load().
+ * The LLEXT subsystem will copy all necessary data to internal buffers at load
+ * time.
+ *
+ * @param _buf Buffer containing the ELF binary
+ * @param _buf_len Buffer length in bytes
+ */
+#define LLEXT_TEMPORARY_BUF_LOADER(_buf, _buf_len) \
+	Z_LLEXT_BUF_LOADER(_buf, _buf_len, LLEXT_STORAGE_TEMPORARY)
+
+/**
+ * @brief Initialize an llext_buf_loader structure for a persistent, read-only buffer
+ *
+ * ELF data from the specified buffer is guaranteed to be accessible for as
+ * long as the extension is loaded. The LLEXT subsystem may directly access the
+ * ELF data, as long as no modification is required during loading.
+ *
+ * @param _buf Buffer containing the ELF binary
+ * @param _buf_len Buffer length in bytes
+ */
+#define LLEXT_PERSISTENT_BUF_LOADER(_buf, _buf_len) \
+	Z_LLEXT_BUF_LOADER(_buf, _buf_len, LLEXT_STORAGE_PERSISTENT)
+
+/**
+ * @brief Initialize an llext_buf_loader structure for a persistent, writable buffer
+ *
+ * ELF data from the specified buffer is guaranteed to be accessible for as
+ * long as the extension is loaded. The LLEXT subsystem may directly access and
+ * modify the ELF data.
+ *
+ * @param _buf Buffer containing the ELF binary
+ * @param _buf_len Buffer length in bytes
+ */
+#define LLEXT_WRITABLE_BUF_LOADER(_buf, _buf_len) \
+	Z_LLEXT_BUF_LOADER(_buf, _buf_len, LLEXT_STORAGE_WRITABLE)
 
 /**
  * @}
diff --git a/include/zephyr/llext/elf.h b/include/zephyr/llext/elf.h
index 48a611a3f59..80176daa26b 100644
--- a/include/zephyr/llext/elf.h
+++ b/include/zephyr/llext/elf.h
@@ -211,9 +211,11 @@ struct elf64_shdr {
 #define SHT_PREINIT_ARRAY 0x10  /**< Array of pointers to early init functions */
 
 /** ELF section flags */
-#define SHF_WRITE 0x1           /**< Section is writable */
-#define SHF_ALLOC 0x2           /**< Section is present in memory */
-#define SHF_EXECINSTR 0x4       /**< Section contains executable instructions */
+#define SHF_WRITE 0x1                   /**< Section is writable */
+#define SHF_ALLOC 0x2                   /**< Section is present in memory */
+#define SHF_EXECINSTR 0x4               /**< Section contains executable instructions */
+#define SHF_MASKOS 0x0ff00000           /**< OS specific flags */
+#define SHF_LLEXT_HAS_RELOCS 0x00100000 /**< Section is a target for relocations */
 
 #define SHF_BASIC_TYPE_MASK	(SHF_WRITE | SHF_ALLOC | SHF_EXECINSTR)
 
diff --git a/include/zephyr/llext/fs_loader.h b/include/zephyr/llext/fs_loader.h
index 9cb41851cb0..3d27b69ebac 100644
--- a/include/zephyr/llext/fs_loader.h
+++ b/include/zephyr/llext/fs_loader.h
@@ -57,6 +57,7 @@ void llext_fs_finalize(struct llext_loader *ldr);
 				.seek = llext_fs_seek,                                             \
 				.peek = NULL,                                                      \
 				.finalize = llext_fs_finalize,                                     \
+				.storage = LLEXT_STORAGE_TEMPORARY,                                \
 			},                                                                         \
 		.is_open = false,                                                                  \
 		.name = (_filename),                                                               \
diff --git a/include/zephyr/llext/inspect.h b/include/zephyr/llext/inspect.h
new file mode 100644
index 00000000000..7e2d66fa577
--- /dev/null
+++ b/include/zephyr/llext/inspect.h
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2025 Arduino SA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_LLEXT_INSPECT_H
+#define ZEPHYR_LLEXT_INSPECT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stddef.h>
+#include <zephyr/llext/llext.h>
+#include <zephyr/llext/loader.h>
+#include <zephyr/llext/llext_internal.h>
+
+/**
+ * @file
+ * @brief LLEXT ELF inspection routines.
+ *
+ * This file contains routines to inspect the contents of an ELF file. It is
+ * intended to be used by applications that need advanced access to the ELF
+ * file structures of a loaded extension.
+ *
+ * @defgroup llext_inspect_apis ELF inspection APIs
+ * @ingroup llext_apis
+ * @{
+ */
+
+/**
+ * @brief Get information about a memory region for the specified extension.
+ *
+ * Retrieve information about a region (merged group of similar sections) in
+ * the extension. Any output parameter can be NULL if that information is not
+ * needed.
+ *
+ * @param[in] ldr Loader
+ * @param[in] ext Extension
+ * @param[in] region Region to get information about
+ * @param[out] hdr Variable storing the pointer to the region header
+ * @param[out] addr Variable storing the region load address
+ * @param[out] size Variable storing the region size
+ *
+ * @return 0 on success, -EINVAL if the region is invalid
+ */
+static inline int llext_get_region_info(const struct llext_loader *ldr,
+					const struct llext *ext,
+					enum llext_mem region,
+					const elf_shdr_t **hdr,
+					const void **addr, size_t *size)
+{
+	if ((unsigned int)region >= LLEXT_MEM_COUNT) {
+		return -EINVAL;
+	}
+
+	if (hdr) {
+		*hdr = &ldr->sects[region];
+	}
+
+	/* address and size compensated for alignment prepad */
+	if (addr) {
+		*addr = (void *)((uintptr_t)ext->mem[region] + ldr->sects[region].sh_info);
+	}
+	if (size) {
+		*size = ext->mem_size[region] - ldr->sects[region].sh_info;
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Get the index of a section with the specified name.
+ *
+ * Requires the @ref llext_load_param.keep_section_info flag to be set at
+ * extension load time.
+ *
+ * @param[in] ldr Loader
+ * @param[in] ext Extension
+ * @param[in] section_name Name of the section to look for
+ *
+ * @return Section index on success, -ENOENT if the section was not found,
+ *         -ENOTSUP if section data is not available.
+ */
+int llext_section_shndx(const struct llext_loader *ldr, const struct llext *ext,
+			    const char *section_name);
+
+/**
+ * @brief Get information about a section for the specified extension.
+ *
+ * Retrieve information about an ELF sections in the extension. Any output
+ * parameter can be @c NULL if that information is not needed.
+ *
+ * Requires the @ref llext_load_param.keep_section_info flag to be set at
+ * extension load time.
+ *
+ * @param[in] ldr Loader
+ * @param[in] ext Extension
+ * @param[in] shndx Section index
+ * @param[out] hdr Variable storing the pointer to the section header
+ * @param[out] region Variable storing the region the section belongs to
+ * @param[out] offset Variable storing the offset of the section in the region
+ *
+ * @return 0 on success, -EINVAL if the section index is invalid,
+ *         -ENOTSUP if section data is not available.
+ */
+static inline int llext_get_section_info(const struct llext_loader *ldr,
+					 const struct llext *ext,
+					 unsigned int shndx,
+					 const elf_shdr_t **hdr,
+					 enum llext_mem *region,
+					 size_t *offset)
+{
+	if (shndx < 0 || shndx >= ext->sect_cnt) {
+		return -EINVAL;
+	}
+	if (!ldr->sect_map) {
+		return -ENOTSUP;
+	}
+
+	enum llext_mem mem_idx = ldr->sect_map[shndx].mem_idx;
+
+	if (hdr) {
+		*hdr = &ext->sect_hdrs[shndx];
+	}
+	if (region) {
+		*region = mem_idx;
+	}
+
+	/* offset compensated for alignment prepad */
+	if (offset) {
+		*offset = ldr->sect_map[shndx].offset - ldr->sects[mem_idx].sh_info;
+	}
+
+	return 0;
+}
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_LLEXT_INSPECT_H */
diff --git a/include/zephyr/llext/llext.h b/include/zephyr/llext/llext.h
index fc9654c408a..76028e5dceb 100644
--- a/include/zephyr/llext/llext.h
+++ b/include/zephyr/llext/llext.h
@@ -65,7 +65,10 @@ enum llext_mem {
 struct llext_loader;
 /** @endcond */
 
-/* Maximim number of dependency LLEXTs */
+/** Maximum length of an extension name */
+#define LLEXT_MAX_NAME_LEN 15
+
+/** Maximum number of dependency LLEXTs */
 #define LLEXT_MAX_DEPENDENCIES 8
 
 /**
@@ -86,7 +89,7 @@ struct llext {
 	/** @endcond */
 
 	/** Name of the llext */
-	char name[16];
+	char name[LLEXT_MAX_NAME_LEN + 1];
 
 	/** Lookup table of memory regions */
 	void *mem[LLEXT_MEM_COUNT];
@@ -125,6 +128,7 @@ struct llext {
 	unsigned int sect_cnt;
 	elf_shdr_t *sect_hdrs;
 	bool sect_hdrs_on_heap;
+	bool mmu_permissions_set;
 	/** @endcond */
 };
 
@@ -146,20 +150,32 @@ static inline unsigned int llext_section_count(const struct llext *ext)
 struct llext_load_param {
 	/** Perform local relocation */
 	bool relocate_local;
+
 	/**
 	 * Use the virtual symbol addresses from the ELF, not addresses within
 	 * the memory buffer, when calculating relocation targets. It also
 	 * means, that the application will take care to place the extension at
 	 * those pre-defined addresses, so the LLEXT core doesn't have to do any
-	 * allocation and copying internally.
+	 * allocation and copying internally. Any MMU permission adjustment will
+	 * be done by the application too.
 	 */
 	bool pre_located;
+
 	/**
 	 * Extensions can implement custom ELF sections to be loaded in specific
 	 * memory regions, detached from other sections of compatible types.
 	 * This optional callback checks whether a section should be detached.
 	 */
 	bool (*section_detached)(const elf_shdr_t *shdr);
+
+	/**
+	 * Keep the ELF section data in memory after loading the extension. This
+	 * is needed to use some of the functions in @ref llext_inspect_apis.
+	 *
+	 * @note Related memory must be freed by @ref llext_free_inspection_data
+	 *       before the extension can be unloaded via @ref llext_unload.
+	 */
+	bool keep_section_info;
 };
 
 /** Default initializer for @ref llext_load_param */
@@ -211,6 +227,19 @@ int llext_load(struct llext_loader *loader, const char *name, struct llext **ext
  */
 int llext_unload(struct llext **ext);
 
+/**
+ * @brief Free any inspection-related memory for the specified loader and extension.
+ *
+ * This is only required if inspection data was requested at load time by
+ * setting @ref llext_load_param.keep_section_info; otherwise, this call will
+ * be a no-op.
+ *
+ * @param[in] ldr Extension loader
+ * @param[in] ext Extension
+ * @returns 0 on success, or a negative error code.
+ */
+int llext_free_inspection_data(struct llext_loader *ldr, struct llext *ext);
+
 /** @brief Entry point function signature for an extension. */
 typedef void (*llext_entry_fn_t)(void *user_data);
 
@@ -330,18 +359,19 @@ int llext_add_domain(struct llext *ext, struct k_mem_domain *domain);
  * symbolic data such as a section, function, or object. These relocations
  * are architecture specific and each architecture supporting LLEXT must
  * implement this.
+ * Arguments sym_base_addr, sym_name can be computed from the sym parameter,
+ * but these parameters are provided redundantly to increase efficiency.
  *
+ * @param[in] ldr Extension loader
+ * @param[in] ext Extension being relocated refers to
  * @param[in] rel Relocation data provided by ELF
- * @param[in] loc Address of opcode to rewrite
- * @param[in] sym_base_addr Address of symbol referenced by relocation
- * @param[in] sym_name Name of symbol referenced by relocation
- * @param[in] load_bias `.text` load address
+ * @param[in] shdr Header of the ELF section currently being located
  * @retval 0 Success
  * @retval -ENOTSUP Unsupported relocation
  * @retval -ENOEXEC Invalid relocation
  */
-int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc,
-			     uintptr_t sym_base_addr, const char *sym_name, uintptr_t load_bias);
+int arch_elf_relocate(struct llext_loader *ldr, struct llext *ext, elf_rela_t *rel,
+		      const elf_shdr_t *shdr);
 
 /**
  * @brief Locates an ELF section in the file.
diff --git a/include/zephyr/llext/llext_internal.h b/include/zephyr/llext/llext_internal.h
index f07dd5efd86..c920c261ea6 100644
--- a/include/zephyr/llext/llext_internal.h
+++ b/include/zephyr/llext/llext_internal.h
@@ -11,6 +11,8 @@
 extern "C" {
 #endif
 
+#include <zephyr/llext/llext.h>
+
 /**
  * @file
  * @brief Private header for linkable loadable extensions
@@ -18,11 +20,60 @@ extern "C" {
 
 /** @cond ignore */
 
-struct llext_loader;
-struct llext;
+
+struct llext_elf_sect_map {
+	enum llext_mem mem_idx;
+	size_t offset;
+};
 
 const void *llext_loaded_sect_ptr(struct llext_loader *ldr, struct llext *ext, unsigned int sh_ndx);
 
+
+static inline const char *llext_string(const struct llext_loader *ldr, const struct llext *ext,
+	enum llext_mem mem_idx, unsigned int idx)
+{
+	return (const char *)ext->mem[mem_idx] + idx;
+}
+
+static inline uintptr_t llext_get_reloc_instruction_location(struct llext_loader *ldr,
+							     struct llext *ext,
+							     int shndx,
+							     const elf_rela_t *rela)
+{
+	return (uintptr_t) llext_loaded_sect_ptr(ldr, ext, shndx) + rela->r_offset;
+}
+
+static inline const char *llext_section_name(const struct llext_loader *ldr,
+					     const struct llext *ext,
+					     const elf_shdr_t *shdr)
+{
+	return llext_string(ldr, ext, LLEXT_MEM_SHSTRTAB, shdr->sh_name);
+}
+
+static inline const char *llext_symbol_name(const struct llext_loader *ldr,
+					    const struct llext *ext,
+					    const elf_sym_t *sym)
+{
+	if (ELF_ST_TYPE(sym->st_info) == STT_SECTION) {
+		return llext_section_name(ldr, ext, ext->sect_hdrs + sym->st_shndx);
+	} else {
+		return llext_string(ldr, ext, LLEXT_MEM_STRTAB, sym->st_name);
+	}
+}
+
+/*
+ * Determine address of a symbol.
+ */
+int llext_lookup_symbol(struct llext_loader *ldr, struct llext *ext, uintptr_t *link_addr,
+			const elf_rela_t *rel, const elf_sym_t *sym, const char *name,
+			const elf_shdr_t *shdr);
+
+/*
+ * Read the symbol entry corresponding to a relocation from the binary.
+ */
+int llext_read_symbol(struct llext_loader *ldr, struct llext *ext, const elf_rela_t *rel,
+		      elf_sym_t *sym);
+
 /** @endcond */
 
 #ifdef __cplusplus
diff --git a/include/zephyr/llext/loader.h b/include/zephyr/llext/loader.h
index 3d043806ef7..ab6ea289a0e 100644
--- a/include/zephyr/llext/loader.h
+++ b/include/zephyr/llext/loader.h
@@ -32,6 +32,44 @@ extern "C" {
 struct llext_elf_sect_map; /* defined in llext_priv.h */
 /** @endcond */
 
+/**
+ * @brief Storage type for the ELF data to be loaded.
+ *
+ * This enum defines the storage type of the ELF data that will be loaded. The
+ * storage type determines which memory optimizations can be tried by the LLEXT
+ * subsystem during the load process.
+ *
+ * @note Even with the most permissive option, LLEXT might still have to copy
+ * ELF data into a separate memory region to comply with other restrictions,
+ * such as hardware memory protection and/or alignment rules.
+ * Sections such as BSS that have no space in the file will also be allocated
+ * in the LLEXT heap.
+ */
+enum llext_storage_type {
+	/**
+	 * ELF data is only available during llext_load(); even if the loader
+	 * supports directly accessing the memory via llext_peek(), the buffer
+	 * contents will be discarded afterwards.
+	 * LLEXT will allocate copies of all required data into its heap.
+	 */
+	LLEXT_STORAGE_TEMPORARY,
+	/**
+	 * ELF data is stored in a *read-only* buffer that is guaranteed to be
+	 * always accessible for as long as the extension is loaded. LLEXT may
+	 * directly reuse constant data from the buffer, but may still allocate
+	 * copies if relocations need to be applied.
+	 */
+	LLEXT_STORAGE_PERSISTENT,
+	/**
+	 * ELF data is stored in a *writable* memory buffer that is guaranteed
+	 * to be always accessible for as long as the extension is loaded.
+	 * LLEXT may freely modify and reuse data in the buffer; so, after the
+	 * extension is unloaded, the contents should be re-initialized before
+	 * a subsequent llext_load() call.
+	 */
+	LLEXT_STORAGE_WRITABLE,
+};
+
 /**
  * @brief Linkable loadable extension loader context
  *
@@ -95,6 +133,11 @@ struct llext_loader {
 	 */
 	void (*finalize)(struct llext_loader *ldr);
 
+	/**
+	 * @brief Storage type of the underlying data accessed by this loader.
+	 */
+	enum llext_storage_type storage;
+
 	/** @cond ignore */
 	elf_ehdr_t hdr;
 	elf_shdr_t sects[LLEXT_MEM_COUNT];
diff --git a/include/zephyr/llext/symbol.h b/include/zephyr/llext/symbol.h
index 9eb847b97fc..9a1394489cb 100644
--- a/include/zephyr/llext/symbol.h
+++ b/include/zephyr/llext/symbol.h
@@ -90,18 +90,30 @@ struct llext_symtable {
 /** @cond ignore */
 #ifdef LL_EXTENSION_BUILD
 /* Extension build: add exported symbols to llext table */
-#define Z_LL_EXTENSION_SYMBOL(x)						\
+#define Z_LL_EXTENSION_SYMBOL_NAMED(sym_ident, sym_name)			\
 	static const struct llext_const_symbol					\
-			Z_GENERIC_SECTION(".exported_sym") __used		\
-			__llext_sym_ ## x = {					\
-		.name = STRINGIFY(x), .addr = (const void *)&x,			\
+			Z_GENERIC_SECTION(.exported_sym) __used			\
+			__llext_sym_ ## sym_name = {				\
+		.name = STRINGIFY(sym_name), .addr = (const void *)&sym_ident,	\
 	}
 #else
 /* No-op when not building an extension */
-#define Z_LL_EXTENSION_SYMBOL(x)
+#define Z_LL_EXTENSION_SYMBOL_NAMED(sym_ident, sym_name)
 #endif
 /** @endcond */
 
+/**
+ * @brief Exports a symbol from an extension to the base image with a custom name
+ *
+ * Version of @ref LL_EXTENSION_SYMBOL that allows the user to specify a custom
+ * name for the exported symbol.
+ *
+ * @param sym_ident Extension symbol to export to the base image
+ * @param sym_name Name associated with the symbol
+ */
+#define LL_EXTENSION_SYMBOL_NAMED(sym_ident, sym_name)				\
+	Z_LL_EXTENSION_SYMBOL_NAMED(sym_ident, sym_name)
+
 /**
  * @brief Exports a symbol from an extension to the base image
  *
@@ -113,34 +125,50 @@ struct llext_symtable {
  *
  * @param x Extension symbol to export to the base image
  */
-#define LL_EXTENSION_SYMBOL(x) Z_LL_EXTENSION_SYMBOL(x)
+#define LL_EXTENSION_SYMBOL(x) Z_LL_EXTENSION_SYMBOL_NAMED(x, x)
 
 /** @cond ignore */
 #if defined(LL_EXTENSION_BUILD)
 /* Extension build: EXPORT_SYMBOL maps to LL_EXTENSION_SYMBOL */
-#define Z_EXPORT_SYMBOL(x) Z_LL_EXTENSION_SYMBOL(x)
+#define Z_EXPORT_SYMBOL_NAMED(sym_ident, sym_name)				\
+	Z_LL_EXTENSION_SYMBOL_NAMED(sym_ident, sym_name)
 #elif defined(CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID)
 /* SLID-enabled LLEXT application: export symbols, names in separate section */
-#define Z_EXPORT_SYMBOL(x)							\
-	static const char Z_GENERIC_SECTION("llext_exports_strtab") __used	\
-		__llext_sym_name_ ## x[] = STRINGIFY(x);				\
-	static const STRUCT_SECTION_ITERABLE(llext_const_symbol,                \
-					     __llext_sym_ ## x) = {	        \
-		.name = __llext_sym_name_ ## x, .addr = (const void *)&x,		\
+#define Z_EXPORT_SYMBOL_NAMED(sym_ident, sym_name)				\
+	static const char Z_GENERIC_SECTION(llext_exports_strtab) __used	\
+		__llext_sym_name_ ## sym_name[] = STRINGIFY(sym_name);		\
+	static const STRUCT_SECTION_ITERABLE(llext_const_symbol,		\
+					     __llext_sym_ ## sym_name) = {	\
+		.name = __llext_sym_name_ ## sym_name,				\
+		.addr = (const void *)&sym_ident,				\
 	}
 #elif defined(CONFIG_LLEXT)
 /* LLEXT application: export symbols */
-#define Z_EXPORT_SYMBOL(x)							\
-	static const STRUCT_SECTION_ITERABLE(llext_const_symbol,                \
-					     __llext_sym_ ## x) = {	        \
-		.name = STRINGIFY(x), .addr = (const void *)&x,			\
+#define Z_EXPORT_SYMBOL_NAMED(sym_ident, sym_name)				\
+	static const STRUCT_SECTION_ITERABLE(llext_const_symbol,		\
+					     __llext_sym_ ## sym_name) = {	\
+		.name = STRINGIFY(sym_name), .addr = (const void *)&sym_ident,	\
 	}
 #else
 /* No extension support in this build */
-#define Z_EXPORT_SYMBOL(x)
+#define Z_EXPORT_SYMBOL_NAMED(sym_ident, sym_name)
 #endif
 /** @endcond */
 
+/**
+ * @brief Export a constant symbol from the current build with a custom name
+ *
+ * Version of @ref EXPORT_SYMBOL that allows the user to specify a custom name
+ * for the exported symbol.
+ *
+ * When @c CONFIG_LLEXT is not enabled, this macro is a no-op.
+ *
+ * @param sym_ident Symbol to export
+ * @param sym_name Name associated with the symbol
+ */
+#define EXPORT_SYMBOL_NAMED(sym_ident, sym_name)				\
+	Z_EXPORT_SYMBOL_NAMED(sym_ident, sym_name)
+
 /**
  * @brief Export a constant symbol from the current build
  *
@@ -152,7 +180,7 @@ struct llext_symtable {
  *
  * @param x Symbol to export
  */
-#define EXPORT_SYMBOL(x) Z_EXPORT_SYMBOL(x)
+#define EXPORT_SYMBOL(x) EXPORT_SYMBOL_NAMED(x, x)
 
 /**
  * @}
diff --git a/include/zephyr/logging/log.h b/include/zephyr/logging/log.h
index 7edfca9ad8f..2358b332ef4 100644
--- a/include/zephyr/logging/log.h
+++ b/include/zephyr/logging/log.h
@@ -11,6 +11,10 @@
 #include <zephyr/logging/log_core.h>
 #include <zephyr/sys/iterable_sections.h>
 
+#if CONFIG_USERSPACE && CONFIG_LOG_ALWAYS_RUNTIME
+#include <zephyr/app_memory/app_memdomain.h>
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -355,6 +359,16 @@ void z_log_vprintk(const char *fmt, va_list ap);
 		   (Z_LOG_EVAL(_LOG_LEVEL_RESOLVE(__VA_ARGS__), (1), (0))) \
 		  )), (0))
 
+/* Determine if the data of the log module shall be in the partition
+ * 'k_log_partition' to allow a user mode thread access to this data.
+ */
+#if CONFIG_USERSPACE && CONFIG_LOG_ALWAYS_RUNTIME
+extern struct k_mem_partition k_log_partition;
+#define Z_LOG_MODULE_PARTITION(_k_app_mem) _k_app_mem(k_log_partition)
+#else
+#define Z_LOG_MODULE_PARTITION(_k_app_mem)
+#endif
+
 /**
  * @brief Create module-specific state and register the module with Logger.
  *
@@ -427,12 +441,14 @@ void z_log_vprintk(const char *fmt, va_list ap);
 	extern struct log_source_dynamic_data				      \
 			LOG_ITEM_DYNAMIC_DATA(GET_ARG_N(1, __VA_ARGS__));     \
 									      \
+	Z_LOG_MODULE_PARTITION(K_APP_DMEM)				      \
 	static const struct log_source_const_data *			      \
 		__log_current_const_data __unused =			      \
 			Z_DO_LOG_MODULE_REGISTER(__VA_ARGS__) ?		      \
 			&Z_LOG_ITEM_CONST_DATA(GET_ARG_N(1, __VA_ARGS__)) :   \
 			NULL;						      \
 									      \
+	Z_LOG_MODULE_PARTITION(K_APP_DMEM)				      \
 	static struct log_source_dynamic_data *				      \
 		__log_current_dynamic_data __unused =			      \
 			(Z_DO_LOG_MODULE_REGISTER(__VA_ARGS__) &&	      \
@@ -440,6 +456,7 @@ void z_log_vprintk(const char *fmt, va_list ap);
 			&LOG_ITEM_DYNAMIC_DATA(GET_ARG_N(1, __VA_ARGS__)) :   \
 			NULL;						      \
 									      \
+	Z_LOG_MODULE_PARTITION(K_APP_BMEM)				      \
 	static const uint32_t __log_level __unused =			      \
 					_LOG_LEVEL_RESOLVE(__VA_ARGS__)
 
diff --git a/include/zephyr/logging/log_backend.h b/include/zephyr/logging/log_backend.h
index e772ad2b9c8..c68d210af73 100644
--- a/include/zephyr/logging/log_backend.h
+++ b/include/zephyr/logging/log_backend.h
@@ -83,6 +83,7 @@ struct log_backend_control_block {
 	void *ctx;
 	uint8_t id;
 	bool active;
+	bool initialized;
 
 	/* Initialization level. */
 	uint8_t level;
@@ -140,6 +141,7 @@ static inline void log_backend_init(const struct log_backend *const backend)
 	if (backend->api->init) {
 		backend->api->init(backend);
 	}
+	backend->cb->initialized = true;
 }
 
 /**
diff --git a/include/zephyr/logging/log_core.h b/include/zephyr/logging/log_core.h
index 64cd2a6c9e5..730e5a7a053 100644
--- a/include/zephyr/logging/log_core.h
+++ b/include/zephyr/logging/log_core.h
@@ -262,10 +262,9 @@ static inline char z_log_minimal_level_to_char(int level)
 			     GET_ARG_N(1, __VA_ARGS__))
 
 #define LOG_POINTERS_VALIDATE(string_ok, ...) \
-	_Pragma("GCC diagnostic push") \
-	_Pragma("GCC diagnostic ignored \"-Wpointer-arith\"") \
+	TOOLCHAIN_DISABLE_GCC_WARNING(TOOLCHAIN_WARNING_POINTER_ARITH); \
 	string_ok = Z_CBPRINTF_POINTERS_VALIDATE(__VA_ARGS__); \
-	_Pragma("GCC diagnostic pop")
+	TOOLCHAIN_ENABLE_GCC_WARNING(TOOLCHAIN_WARNING_POINTER_ARITH);
 #else
 #define LOG_POINTERS_VALIDATE(string_ok, ...) string_ok = true
 #define LOG_STRING_WARNING(_mode, _src, ...)
@@ -353,13 +352,14 @@ static inline char z_log_minimal_level_to_char(int level)
 			z_log_minimal_hexdump_print((_level), (const char *)(_data), (_len));      \
 			break;                                                                     \
 		}                                                                                  \
-		int mode;                                                                          \
-		Z_LOG_MSG_CREATE(UTIL_NOT(IS_ENABLED(CONFIG_USERSPACE)), mode,                     \
+		int _mode;                                                                         \
+		Z_LOG_MSG_CREATE(UTIL_NOT(IS_ENABLED(CONFIG_USERSPACE)), _mode,                    \
 				 Z_LOG_LOCAL_DOMAIN_ID, _source, _level, _data, _len,              \
 				 COND_CODE_0(NUM_VA_ARGS_LESS_1(_, ##__VA_ARGS__), \
 				(), \
 			  (COND_CODE_0(NUM_VA_ARGS_LESS_1(__VA_ARGS__), \
 				  ("%s", __VA_ARGS__), (__VA_ARGS__)))));   \
+		(void)_mode;                                                                       \
 	} while (false)
 
 #define Z_LOG_HEXDUMP(_level, _data, _length, ...)                                                 \
@@ -400,12 +400,12 @@ static inline char z_log_minimal_level_to_char(int level)
 #define LOG_FILTER_SLOT_GET(_filters, _id) \
 	((*(_filters) >> LOG_FILTER_SLOT_SHIFT(_id)) & LOG_FILTER_SLOT_MASK)
 
-#define LOG_FILTER_SLOT_SET(_filters, _id, _filter)		     \
-	do {							     \
-		*(_filters) &= ~(LOG_FILTER_SLOT_MASK <<	     \
-				 LOG_FILTER_SLOT_SHIFT(_id));	     \
-		*(_filters) |= ((_filter) & LOG_FILTER_SLOT_MASK) << \
-			       LOG_FILTER_SLOT_SHIFT(_id);	     \
+#define LOG_FILTER_SLOT_SET(_filters, _id, _filter)			      \
+	do {								      \
+		uint32_t others = *(_filters) & ~(LOG_FILTER_SLOT_MASK <<     \
+				 LOG_FILTER_SLOT_SHIFT(_id));		      \
+		*(_filters) = others | (((_filter) & LOG_FILTER_SLOT_MASK) << \
+			       LOG_FILTER_SLOT_SHIFT(_id));		      \
 	} while (false)
 
 #define LOG_FILTER_AGGR_SLOT_IDX 0
diff --git a/include/zephyr/logging/log_ctrl.h b/include/zephyr/logging/log_ctrl.h
index 26d09589027..2a6b431f221 100644
--- a/include/zephyr/logging/log_ctrl.h
+++ b/include/zephyr/logging/log_ctrl.h
@@ -95,6 +95,17 @@ __syscall void log_panic(void);
  */
 __syscall bool log_process(void);
 
+/**
+ * @brief Process all pending log messages
+ */
+#ifdef CONFIG_LOG_MODE_DEFERRED
+void log_flush(void);
+#else
+static inline void log_flush(void)
+{
+}
+#endif
+
 /**
  * @brief Return number of buffered log messages.
  *
diff --git a/include/zephyr/logging/log_frontend_stmesp_demux.h b/include/zephyr/logging/log_frontend_stmesp_demux.h
index 1a32ff27218..1b74f9832a7 100644
--- a/include/zephyr/logging/log_frontend_stmesp_demux.h
+++ b/include/zephyr/logging/log_frontend_stmesp_demux.h
@@ -16,6 +16,7 @@ extern "C" {
 
 /**
  * @defgroup log_frontend_stmesp_apis Trace and Debug Domain APIs
+ * @ingroup logging
  * @{
  * @}
  * @defgroup log_frontend_stpesp_demux_apis Logging frontend STMESP Demultiplexer API
diff --git a/include/zephyr/logging/log_msg.h b/include/zephyr/logging/log_msg.h
index e75f7b7c2be..7337a501545 100644
--- a/include/zephyr/logging/log_msg.h
+++ b/include/zephyr/logging/log_msg.h
@@ -336,9 +336,9 @@ do { \
 		CBPRINTF_STATIC_PACKAGE(NULL, 0, _plen, Z_LOG_MSG_ALIGN_OFFSET, _options, \
 					__VA_ARGS__); \
 	} \
-	TOOLCHAIN_IGNORE_WSHADOW_BEGIN \
+	TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_SHADOW) \
 	struct log_msg *_msg; \
-	TOOLCHAIN_IGNORE_WSHADOW_END \
+	TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_SHADOW) \
 	Z_LOG_MSG_ON_STACK_ALLOC(_msg, Z_LOG_MSG_LEN(_plen, 0)); \
 	Z_LOG_ARM64_VLA_PROTECT(); \
 	if (_plen != 0) { \
@@ -560,7 +560,7 @@ do { \
 
 /* Create local variable from input variable (expect for the first (fmt) argument). */
 #define Z_LOG_LOCAL_ARG_CREATE(idx, arg) \
-	COND_CODE_0(idx, (), (Z_AUTO_TYPE Z_LOG_LOCAL_ARG_NAME(idx, arg) = (arg) + 0))
+	COND_CODE_0(idx, (), (Z_AUTO_TYPE Z_LOG_LOCAL_ARG_NAME(idx, arg) = Z_ARGIFY(arg)))
 
 /* First level of processing creates stack variables to be passed for further processing.
  * This is done to prevent multiple evaluations of input arguments (in case argument
@@ -569,10 +569,7 @@ do { \
 #define Z_LOG_MSG_CREATE2(_try_0cpy, _mode, _cstr_cnt,  _domain_id, _source, \
 			   _level, _data, _dlen, ...) \
 do { \
-	_Pragma("GCC diagnostic push") \
-	_Pragma("GCC diagnostic ignored \"-Wpointer-arith\"") \
 	FOR_EACH_IDX(Z_LOG_LOCAL_ARG_CREATE, (;), __VA_ARGS__); \
-	_Pragma("GCC diagnostic pop") \
 	Z_LOG_MSG_CREATE3(_try_0cpy, _mode,  _cstr_cnt, _domain_id, _source,\
 			   _level, _data, _dlen, \
 			   FOR_EACH_IDX(Z_LOG_LOCAL_ARG_NAME, (,), __VA_ARGS__)); \
diff --git a/include/zephyr/lorawan/lorawan.h b/include/zephyr/lorawan/lorawan.h
index 914997243e1..9f8688189cb 100644
--- a/include/zephyr/lorawan/lorawan.h
+++ b/include/zephyr/lorawan/lorawan.h
@@ -217,6 +217,35 @@ typedef uint8_t (*lorawan_battery_level_cb_t)(void);
  */
 typedef void (*lorawan_dr_changed_cb_t)(enum lorawan_datarate dr);
 
+/**
+ * @brief Defines the link check answer handler function signature.
+ *
+ * @param demod_margin The demodulation margin in db.
+ * @param nb_gateways The number of gateways the device is connected to.
+ */
+typedef void (*lorawan_link_check_ans_cb_t)(uint8_t demod_margin, uint8_t nb_gateways);
+
+/**
+ * @brief Defines the user's descriptor callback handler function signature.
+ *
+ * The use of this callback is optional. When Fragmented Data Block Transport
+ * is enabled, the application will be notified with the descriptor field present on
+ * the FragSessionSetupReq command.
+ *
+ * @param descriptor Descriptor value given on the FragSessionSetupReq command.
+ *
+ * The meaning of Descriptor is application dependent. When doing a FUOTA
+ * with a binary image, it may represent the version of the firmware
+ * transported.
+ *
+ * @return 0 if successful. This represents, in the case that the descriptor is the firmware
+ * version, that the end-device is able to receive binary firmware. Otherwise, a negative error code
+ * (errno.h) indicating the reason for failure. Any negative error code will result in setting
+ * the Wrong Descriptor status bit mask when sending FragSessionSetupAns to the Network Server.
+ *
+ */
+typedef int (*transport_descriptor_cb)(uint32_t descriptor);
+
 /**
  * @brief Register a battery level callback function.
  *
@@ -246,6 +275,14 @@ void lorawan_register_downlink_callback(struct lorawan_downlink_cb *cb);
  */
 void lorawan_register_dr_changed_callback(lorawan_dr_changed_cb_t cb);
 
+/**
+ * @brief Register a callback to be called when getting answer
+ * a to check link request.
+ *
+ * @param cb Pointer to link check ans callback
+ */
+void lorawan_register_link_check_ans_callback(lorawan_link_check_ans_cb_t cb);
+
 /**
  * @brief Join the LoRaWAN network
  *
@@ -405,6 +442,18 @@ int lorawan_request_device_time(bool force_request);
  */
 int lorawan_device_time_get(uint32_t *gps_time);
 
+/**
+ * @brief Request for link check according to LinkCheckReq MAC cmd
+ *
+ * Append MAC LinkCheckReq command. It will be processed on next send
+ * message or force sending empty message to request time immediately.
+ *
+ * @param force_request Immediately send an empty message to execute the request
+ *
+ * @return 0 if successful, negative errno otherwise
+ */
+int lorawan_request_link_check(bool force_request);
+
 #ifdef CONFIG_LORAWAN_APP_CLOCK_SYNC
 
 /**
@@ -439,6 +488,17 @@ int lorawan_clock_sync_get(uint32_t *gps_time);
 
 #ifdef CONFIG_LORAWAN_FRAG_TRANSPORT
 
+/**
+ * @brief Register a handle descriptor callback function.
+ *
+ * Provide to the fragmentation transport service a function to be called
+ * whenever a FragSessionSetupReq is received and Descriptor field should be
+ * handled.
+ *
+ * @param transport_descriptor_cb Callback for notification.
+ */
+void lorawan_frag_transport_register_descriptor_callback(transport_descriptor_cb cb);
+
 /**
  * @brief Run Fragmented Data Block Transport service
  *
diff --git a/include/zephyr/mgmt/mcumgr/grp/fs_mgmt/fs_mgmt_callbacks.h b/include/zephyr/mgmt/mcumgr/grp/fs_mgmt/fs_mgmt_callbacks.h
index 9a89555b85d..85135c9d638 100644
--- a/include/zephyr/mgmt/mcumgr/grp/fs_mgmt/fs_mgmt_callbacks.h
+++ b/include/zephyr/mgmt/mcumgr/grp/fs_mgmt/fs_mgmt_callbacks.h
@@ -21,10 +21,10 @@ extern "C" {
 
 /** The type of operation that is being requested for a given file access callback. */
 enum fs_mgmt_file_access_types {
-	/** Access to read file (file upload). */
+	/** Access to read file (file download). */
 	FS_MGMT_FILE_ACCESS_READ,
 
-	/** Access to write file (file download). */
+	/** Access to write file (file upload). */
 	FS_MGMT_FILE_ACCESS_WRITE,
 
 	/** Access to get status of file. */
diff --git a/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt.h b/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt.h
index 49dffc6b7ca..88ce62ca28c 100644
--- a/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt.h
+++ b/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt.h
@@ -9,11 +9,14 @@
 #define H_IMG_MGMT_
 
 #include <inttypes.h>
-#include <zephyr/mgmt/mcumgr/mgmt/mgmt.h>
-#include <zephyr/mgmt/mcumgr/smp/smp.h>
 #include <bootutil/image.h>
 #include <zcbor_common.h>
 
+#ifdef CONFIG_MCUMGR_GRP_IMG_VERBOSE_ERR
+#include <zephyr/mgmt/mcumgr/mgmt/mgmt.h>
+#include <zephyr/mgmt/mcumgr/smp/smp.h>
+#endif
+
 /**
  * @brief MCUmgr img_mgmt API
  * @defgroup mcumgr_img_mgmt MCUmgr img_mgmt API
diff --git a/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt_callbacks.h b/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt_callbacks.h
index 5c479fd9918..5a1b8de0343 100644
--- a/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt_callbacks.h
+++ b/include/zephyr/mgmt/mcumgr/grp/img_mgmt/img_mgmt_callbacks.h
@@ -41,6 +41,16 @@ struct img_mgmt_upload_check {
 	struct img_mgmt_upload_req *req;
 };
 
+/**
+ * Structure provided in the #MGMT_EVT_OP_IMG_MGMT_DFU_CONFIRMED notification callback: This
+ * callback function is used to notify the application about an image confirmation being executed
+ * successfully.
+ */
+struct img_mgmt_image_confirmed {
+	/** Image number which has been confirmed */
+	const uint8_t image;
+};
+
 /**
  * Structure provided in the #MGMT_EVT_OP_IMG_MGMT_IMAGE_SLOT_STATE notification callback: This
  * callback function is used to allow applications or modules append custom fields to the image
diff --git a/include/zephyr/mgmt/mcumgr/mgmt/callbacks.h b/include/zephyr/mgmt/mcumgr/mgmt/callbacks.h
index e3cd408ea73..e58ed93140e 100644
--- a/include/zephyr/mgmt/mcumgr/mgmt/callbacks.h
+++ b/include/zephyr/mgmt/mcumgr/mgmt/callbacks.h
@@ -76,9 +76,6 @@ enum mgmt_cb_return {
 	MGMT_CB_ERROR_ERR,
 };
 
-/* Deprecated after Zephyr 3.4, use MGMT_CB_ERROR_ERR instead */
-#define MGMT_CB_ERROR_RET __DEPRECATED_MACRO MGMT_CB_ERROR_ERR
-
 /**
  * @typedef mgmt_cb
  * @brief Function to be called on MGMT notification/event.
@@ -159,6 +156,9 @@ enum fs_mgmt_group_events {
 	/** Callback when a file has been accessed, data is fs_mgmt_file_access(). */
 	MGMT_EVT_OP_FS_MGMT_FILE_ACCESS		= MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_FS, 0),
 
+	/** Callback when a file upload/download is finished, data is fs_mgmt_file_access(). */
+	MGMT_EVT_OP_FS_MGMT_FILE_ACCESS_DONE	= MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_FS, 1),
+
 	/** Used to enable all fs_mgmt_group events. */
 	MGMT_EVT_OP_FS_MGMT_ALL			= MGMT_DEF_EVT_OP_ALL(MGMT_EVT_GRP_FS),
 };
@@ -179,19 +179,28 @@ enum img_mgmt_group_events {
 	/** Callback when a DFU operation has finished being transferred. */
 	MGMT_EVT_OP_IMG_MGMT_DFU_PENDING		= MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_IMG, 3),
 
-	/** Callback when an image has been confirmed. */
+	/** Callback when an image has been confirmed. data is img_mgmt_image_confirmed(). */
 	MGMT_EVT_OP_IMG_MGMT_DFU_CONFIRMED		= MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_IMG, 4),
 
 	/** Callback when an image write command has finished writing to flash. */
 	MGMT_EVT_OP_IMG_MGMT_DFU_CHUNK_WRITE_COMPLETE	= MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_IMG, 5),
 
-	/** Callback when an image slot's state is encoded for a response. */
+	/**
+	 * Callback when an image slot's state is encoded for a response, data is
+	 * img_mgmt_state_slot_encode().
+	 */
 	MGMT_EVT_OP_IMG_MGMT_IMAGE_SLOT_STATE		= MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_IMG, 6),
 
-	/** Callback when an slot list command outputs fields for an image. */
+	/**
+	 * Callback when a slot list command outputs fields for an image, data is
+	 * img_mgmt_slot_info_image().
+	 */
 	MGMT_EVT_OP_IMG_MGMT_SLOT_INFO_IMAGE		= MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_IMG, 7),
 
-	/** Callback when an slot list command outputs fields for a slot of an image. */
+	/**
+	 * Callback when a slot list command outputs fields for a slot of an image, data is
+	 * img_mgmt_slot_info_slot().
+	 */
 	MGMT_EVT_OP_IMG_MGMT_SLOT_INFO_SLOT		= MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_IMG, 8),
 
 	/** Used to enable all img_mgmt_group events. */
@@ -202,13 +211,13 @@ enum img_mgmt_group_events {
  * MGMT event opcodes for operating system management group.
  */
 enum os_mgmt_group_events {
-	/** Callback when a reset command has been received, data is os_mgmt_reset_data. */
+	/** Callback when a reset command has been received, data is os_mgmt_reset_data(). */
 	MGMT_EVT_OP_OS_MGMT_RESET		= MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_OS, 0),
 
-	/** Callback when an info command is processed, data is os_mgmt_info_check. */
+	/** Callback when an info command is processed, data is os_mgmt_info_check(). */
 	MGMT_EVT_OP_OS_MGMT_INFO_CHECK		= MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_OS, 1),
 
-	/** Callback when an info command needs to output data, data is os_mgmt_info_append. */
+	/** Callback when an info command needs to output data, data is os_mgmt_info_append(). */
 	MGMT_EVT_OP_OS_MGMT_INFO_APPEND		= MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_OS, 2),
 
 	/** Callback when a datetime get command has been received. */
@@ -219,7 +228,7 @@ enum os_mgmt_group_events {
 
 	/**
 	 * Callback when a bootloader info command has been received, data is
-	 * os_mgmt_bootloader_info_data.
+	 * os_mgmt_bootloader_info_data().
 	 */
 	MGMT_EVT_OP_OS_MGMT_BOOTLOADER_INFO	= MGMT_DEF_EVT_OP_ID(MGMT_EVT_GRP_OS, 5),
 
diff --git a/include/zephyr/mgmt/mcumgr/transport/smp_shell.h b/include/zephyr/mgmt/mcumgr/transport/smp_shell.h
index 705ec697ff7..a7c4831f58f 100644
--- a/include/zephyr/mgmt/mcumgr/transport/smp_shell.h
+++ b/include/zephyr/mgmt/mcumgr/transport/smp_shell.h
@@ -11,6 +11,7 @@
 #ifndef ZEPHYR_INCLUDE_MGMT_SMP_SHELL_H_
 #define ZEPHYR_INCLUDE_MGMT_SMP_SHELL_H_
 
+#include <zephyr/kernel.h>
 #include <zephyr/types.h>
 
 #ifdef __cplusplus
diff --git a/include/zephyr/net/buf.h b/include/zephyr/net/buf.h
deleted file mode 100644
index c537c03057f..00000000000
--- a/include/zephyr/net/buf.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2015 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_INCLUDE_NET_BUF_DEPRECATED_H_
-#define ZEPHYR_INCLUDE_NET_BUF_DEPRECATED_H_
-
-#include <zephyr/net_buf.h>
-
-#warning This header is deprecated, include <zephyr/net_buf.h> instead
-
-#endif /*  ZEPHYR_INCLUDE_NET_BUF_DEPRECATED_H_ */
diff --git a/include/zephyr/net/coap_client.h b/include/zephyr/net/coap_client.h
index ce09c56dd2e..2266821a691 100644
--- a/include/zephyr/net/coap_client.h
+++ b/include/zephyr/net/coap_client.h
@@ -24,6 +24,10 @@
 #include <zephyr/net/coap.h>
 #include <zephyr/kernel.h>
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 /** Maximum size of a CoAP message */
 #define MAX_COAP_MSG_LEN (CONFIG_COAP_CLIENT_MESSAGE_HEADER_SIZE + \
 			  CONFIG_COAP_CLIENT_MESSAGE_SIZE)
@@ -153,6 +157,8 @@ int coap_client_req(struct coap_client *client, int sock, const struct sockaddr
  *
  * This is intended for canceling long-running requests (e.g. GETs with the OBSERVE option set)
  * which has gone stale for some reason.
+ * The function should also be called before the corresponding client socket is closed,
+ * to prevent the socket from being monitored by the internal polling thread.
  *
  * @param client Client instance.
  */
@@ -184,16 +190,28 @@ void coap_client_cancel_request(struct coap_client *client, struct coap_client_r
  *
  * @return CoAP client initial Block2 option structure
  */
-static inline struct coap_client_option coap_client_option_initial_block2(void)
-{
-	struct coap_client_option block2 = {
-		.code = COAP_OPTION_BLOCK2,
-		.len = 1,
-		.value[0] = coap_bytes_to_block_size(CONFIG_COAP_CLIENT_BLOCK_SIZE),
-	};
-
-	return block2;
+struct coap_client_option coap_client_option_initial_block2(void);
+
+/**
+ * @brief Check if client has ongoing exchange.
+ *
+ * @note Function not only considers ongoing requests, but also lifetime of completed requests
+ * (which provides graceful duplicates handling).
+ *
+ * @note For socket handling.
+ * Function does no consider a socket POLL that has started before this call,
+ * therefore it is recommended to wait out POLL timeout before closing socket
+ * (e.g. call coap_client_cancel_requests() which applies delay for timeout).
+ *
+ * @param client Pointer to the CoAP client instance.
+ *
+ * @return true if there is an ongoing exchange, false otherwise.
+ */
+bool coap_client_has_ongoing_exchange(struct coap_client *client);
+
+#ifdef __cplusplus
 }
+#endif
 
 /**
  * @}
diff --git a/include/zephyr/net/dns_resolve.h b/include/zephyr/net/dns_resolve.h
index 33398dabdf1..3413a008395 100644
--- a/include/zephyr/net/dns_resolve.h
+++ b/include/zephyr/net/dns_resolve.h
@@ -15,6 +15,7 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/net/net_ip.h>
+#include <zephyr/net/net_if.h>
 #include <zephyr/net/socket_poll.h>
 #include <zephyr/net/net_core.h>
 
@@ -156,13 +157,14 @@ enum dns_socket_type {
 
 struct dns_resolve_context;
 struct mdns_responder_context;
+struct dns_socket_dispatcher;
 
 /**
  * @typedef dns_socket_dispatcher_cb
  * @brief Callback used when the DNS socket dispatcher has found a handler for
  * this type of socket.
  *
- * @param ctx DNS resolve or mDNS responder context.
+ * @param ctx struct dns_socket_dispatcher context.
  * @param sock Socket which is seeing traffic.
  * @param addr Socket address of the peer that sent the DNS packet.
  * @param addrlen Length of the socket address.
@@ -171,7 +173,7 @@ struct mdns_responder_context;
  *
  * @return 0 if ok, <0 if error
  */
-typedef int (*dns_socket_dispatcher_cb)(void *ctx, int sock,
+typedef int (*dns_socket_dispatcher_cb)(struct dns_socket_dispatcher *ctx, int sock,
 					struct sockaddr *addr, size_t addrlen,
 					struct net_buf *buf, size_t data_len);
 
@@ -214,13 +216,6 @@ struct dns_socket_dispatcher {
 	k_timeout_t buf_timeout;
 };
 
-struct mdns_responder_context {
-	struct sockaddr server_addr;
-	struct dns_socket_dispatcher dispatcher;
-	struct zsock_pollfd fds[1];
-	int sock;
-};
-
 /**
  * @brief Register a DNS dispatcher socket. Each code wanting to use
  * the dispatcher needs to create the dispatcher context and call
@@ -431,6 +426,29 @@ struct dns_resolve_context {
 	enum dns_resolve_context_state state;
 };
 
+/** @cond INTERNAL_HIDDEN */
+
+struct mdns_probe_user_data {
+	struct mdns_responder_context *ctx;
+	char query[DNS_MAX_NAME_SIZE + 1];
+	uint16_t dns_id;
+};
+
+struct mdns_responder_context {
+	struct sockaddr server_addr;
+	struct dns_socket_dispatcher dispatcher;
+	struct zsock_pollfd fds[1];
+	int sock;
+	struct net_if *iface;
+#if defined(CONFIG_MDNS_RESPONDER_PROBE)
+	struct k_work_delayable probe_timer;
+	struct dns_resolve_context probe_ctx;
+	struct mdns_probe_user_data probe_data;
+#endif
+};
+
+/** @endcond */
+
 /**
  * @brief Init DNS resolving context.
  *
diff --git a/include/zephyr/net/dsa.h b/include/zephyr/net/dsa.h
index db81a5e3536..8131574cd24 100644
--- a/include/zephyr/net/dsa.h
+++ b/include/zephyr/net/dsa.h
@@ -28,12 +28,8 @@
 #define NET_DSA_PORT_MAX_COUNT 8
 #define DSA_STATUS_PERIOD_MS K_MSEC(1000)
 
-/*
- * Size of the DSA TAG:
- * - KSZ8794 - 1 byte
- */
-#if defined(CONFIG_DSA_KSZ8794) && defined(CONFIG_DSA_KSZ_TAIL_TAGGING)
-#define DSA_TAG_SIZE 1
+#ifdef CONFIG_DSA_TAG_SIZE
+#define DSA_TAG_SIZE CONFIG_DSA_TAG_SIZE
 #else
 #define DSA_TAG_SIZE 0
 #endif
diff --git a/include/zephyr/net/dsa_core.h b/include/zephyr/net/dsa_core.h
new file mode 100644
index 00000000000..f22d4d0aa07
--- /dev/null
+++ b/include/zephyr/net/dsa_core.h
@@ -0,0 +1,219 @@
+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/** @file
+ * @brief Distributed Switch Architecture (DSA)
+ */
+
+#ifndef ZEPHYR_INCLUDE_NET_DSA_CORE_H_
+#define ZEPHYR_INCLUDE_NET_DSA_CORE_H_
+
+#include <errno.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/net/net_if.h>
+#include <zephyr/net/phy.h>
+
+/**
+ * @brief Distributed Switch Architecture (DSA)
+ * @defgroup dsa_core Distributed Switch Architecture (DSA)
+ * @since 4.2
+ * @version 0.8.0
+ * @ingroup networking
+ * @{
+ */
+
+/** @cond INTERNAL_HIDDEN */
+
+#if defined(CONFIG_DSA_PORT_MAX_COUNT)
+#define DSA_PORT_MAX_COUNT CONFIG_DSA_PORT_MAX_COUNT
+#else
+#define DSA_PORT_MAX_COUNT 0
+#endif
+
+#if defined(CONFIG_DSA_TAG_SIZE)
+#define DSA_TAG_SIZE CONFIG_DSA_TAG_SIZE
+#else
+#define DSA_TAG_SIZE 0
+#endif
+
+/** @endcond */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Macro for DSA port instance initialization.
+ *
+ * @param port	DSA port node identifier.
+ * @param n	DSA instance number.
+ * @param cfg	Pointer to dsa_port_config.
+ */
+#define DSA_PORT_INST_INIT(port, n, cfg)                                                           \
+	NET_DEVICE_INIT_INSTANCE(CONCAT(dsa_, n, port), DEVICE_DT_NAME(port), DT_REG_ADDR(port),   \
+				 dsa_port_initialize, NULL, &dsa_switch_context_##n, cfg,          \
+				 CONFIG_ETH_INIT_PRIORITY, &dsa_eth_api, ETHERNET_L2,              \
+				 NET_L2_GET_CTX_TYPE(ETHERNET_L2), NET_ETH_MTU);
+
+/**
+ * @brief Macro for DSA switch instance initialization.
+ *
+ * @param n	DSA instance number.
+ * @param _dapi	Pointer to dsa_api.
+ * @param data	Pointer to private data.
+ * @param fn	DSA port instance init function.
+ */
+#define DSA_SWITCH_INST_INIT(n, _dapi, data, fn)                                                   \
+	struct dsa_switch_context dsa_switch_context_##n = {                                       \
+		.dapi = _dapi,                                                                     \
+		.prv_data = data,                                                                  \
+		.init_ports = 0,                                                                   \
+		.num_ports = DT_INST_CHILD_NUM_STATUS_OKAY(n),                                     \
+	};                                                                                         \
+	DT_INST_FOREACH_CHILD_STATUS_OKAY_VARGS(n, fn, n);
+
+/** DSA switch context data */
+struct dsa_switch_context {
+	/** Pointers to all DSA user network interfaces */
+	struct net_if *iface_user[DSA_PORT_MAX_COUNT];
+
+	/** Pointer to DSA conduit network interface */
+	struct net_if *iface_conduit;
+
+	/** DSA specific API callbacks */
+	struct dsa_api *dapi;
+
+	/** Instance specific data */
+	void *prv_data;
+
+	/** Number of ports in the DSA switch */
+	uint8_t num_ports;
+
+	/** Number of initialized ports in the DSA switch */
+	uint8_t init_ports;
+};
+
+/**
+ * Structure to provide DSA switch api callbacks - it is an augmented
+ * struct ethernet_api.
+ */
+struct dsa_api {
+	/** DSA helper callbacks */
+
+	/** Handle receive packet on conduit port for untagging and redirection */
+	struct net_if *(*recv)(struct net_if *iface, struct net_pkt *pkt);
+
+	/** Transmit packet on the user port with tagging */
+	struct net_pkt *(*xmit)(struct net_if *iface, struct net_pkt *pkt);
+
+	/** Port init */
+	int (*port_init)(const struct device *dev);
+
+	/** Port link change */
+	void (*port_phylink_change)(const struct device *dev, struct phy_link_state *state,
+				    void *user_data);
+
+	/** Port generates random mac address */
+	void (*port_generate_random_mac)(uint8_t *mac_addr);
+
+	/** Switch setup */
+	int (*switch_setup)(const struct dsa_switch_context *dsa_switch_ctx);
+};
+
+/**
+ * Structure of DSA port configuration.
+ */
+struct dsa_port_config {
+	/** Port mac address */
+	uint8_t mac_addr[6];
+	/** Use random mac address or not */
+	const bool use_random_mac_addr;
+	/** Port index */
+	const int port_idx;
+	/** PHY device */
+	const struct device *phy_dev;
+	/** PHY mode */
+	const char *phy_mode;
+	/** Ethernet device connected to the port */
+	const struct device *ethernet_connection;
+	/** Instance specific config */
+	void *prv_config;
+};
+
+/** @cond INTERNAL_HIDDEN */
+
+enum dsa_port_type {
+	NON_DSA_PORT,
+	DSA_CONDUIT_PORT,
+	DSA_USER_PORT,
+	DSA_CPU_PORT,
+	DSA_PORT,
+};
+
+/*
+ * DSA port init
+ *
+ * Returns:
+ *  - 0 if ok, < 0 if error
+ */
+int dsa_port_initialize(const struct device *dev);
+
+/*
+ * DSA transmit function
+ *
+ * param dev: Port device to transmit
+ * param pkt: Network packet
+ *
+ * Returns:
+ *  - 0 if ok, < 0 if error
+ */
+int dsa_xmit(const struct device *dev, struct net_pkt *pkt);
+
+/*
+ * DSA receive function
+ *
+ * param iface: Interface of conduit port
+ * param pkt: Network packet
+ *
+ * Returns:
+ *  - Interface to redirect
+ */
+struct net_if *dsa_recv(struct net_if *iface, struct net_pkt *pkt);
+
+/*
+ * DSA ethernet init function to handle flags
+ *
+ * param iface: Interface of port
+ *
+ * Returns:
+ *  - 0 if ok, < 0 if error
+ */
+int dsa_eth_init(struct net_if *iface);
+
+/* Ethernet APIs definition for switch ports */
+extern const struct ethernet_api dsa_eth_api;
+
+/** @endcond */
+
+/**
+ * @brief      Get network interface of a user port
+ *
+ * @param      iface     Conduit port
+ * @param[in]  port_idx  Port index
+ *
+ * @return     network interface of the user if successful
+ * @return     NULL if user port does not exist
+ */
+struct net_if *dsa_user_get_iface(struct net_if *iface, int port_idx);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+ * @}
+ */
+#endif /* ZEPHYR_INCLUDE_NET_DSA_CORE_H_ */
diff --git a/include/zephyr/net/ethernet.h b/include/zephyr/net/ethernet.h
index b4943a34692..08e4d4d8265 100644
--- a/include/zephyr/net/ethernet.h
+++ b/include/zephyr/net/ethernet.h
@@ -26,8 +26,10 @@
 #include <zephyr/net/ethernet_vlan.h>
 #include <zephyr/net/ptp_time.h>
 
-#if defined(CONFIG_NET_DSA)
+#if defined(CONFIG_NET_DSA_DEPRECATED)
 #include <zephyr/net/dsa.h>
+#else
+#include <zephyr/net/dsa_core.h>
 #endif
 
 #if defined(CONFIG_NET_ETHERNET_BRIDGE)
@@ -58,57 +60,61 @@ struct net_eth_addr {
 
 #define NET_ETH_HDR(pkt) ((struct net_eth_hdr *)net_pkt_data(pkt))
 
+/* zephyr-keep-sorted-start */
+#define NET_ETH_PTYPE_ALL		0x0003 /* from linux/if_ether.h */
+#define NET_ETH_PTYPE_ARP		0x0806
 #define NET_ETH_PTYPE_CAN		0x000C /* CAN: Controller Area Network */
 #define NET_ETH_PTYPE_CANFD		0x000D /* CANFD: CAN flexible data rate*/
+#define NET_ETH_PTYPE_EAPOL		0x888e
+#define NET_ETH_PTYPE_ECAT		0x88a4
 #define NET_ETH_PTYPE_HDLC		0x0019 /* HDLC frames (like in PPP) */
-#define NET_ETH_PTYPE_ARP		0x0806
+#define NET_ETH_PTYPE_IEEE802154	0x00F6 /* from linux/if_ether.h: IEEE802.15.4 frame */
 #define NET_ETH_PTYPE_IP		0x0800
-#define NET_ETH_PTYPE_TSN		0x22f0 /* TSN (IEEE 1722) packet */
 #define NET_ETH_PTYPE_IPV6		0x86dd
-#define NET_ETH_PTYPE_VLAN		0x8100
-#define NET_ETH_PTYPE_PTP		0x88f7
 #define NET_ETH_PTYPE_LLDP		0x88cc
-#define NET_ETH_PTYPE_ALL               0x0003 /* from linux/if_ether.h */
-#define NET_ETH_PTYPE_ECAT		0x88a4
-#define NET_ETH_PTYPE_EAPOL		0x888e
-#define NET_ETH_PTYPE_IEEE802154	0x00F6 /* from linux/if_ether.h: IEEE802.15.4 frame */
+#define NET_ETH_PTYPE_PTP		0x88f7
+#define NET_ETH_PTYPE_TSN		0x22f0 /* TSN (IEEE 1722) packet */
+#define NET_ETH_PTYPE_VLAN		0x8100
+/* zephyr-keep-sorted-stop */
 
+/* zephyr-keep-sorted-start re(^#define) */
+#if !defined(ETH_P_8021Q)
+#define ETH_P_8021Q	NET_ETH_PTYPE_VLAN
+#endif
 #if !defined(ETH_P_ALL)
 #define ETH_P_ALL	NET_ETH_PTYPE_ALL
 #endif
-#if !defined(ETH_P_IP)
-#define ETH_P_IP	NET_ETH_PTYPE_IP
-#endif
 #if !defined(ETH_P_ARP)
 #define ETH_P_ARP	NET_ETH_PTYPE_ARP
 #endif
-#if !defined(ETH_P_IPV6)
-#define ETH_P_IPV6	NET_ETH_PTYPE_IPV6
+#if !defined(ETH_P_CAN)
+#define ETH_P_CAN	NET_ETH_PTYPE_CAN
 #endif
-#if !defined(ETH_P_8021Q)
-#define ETH_P_8021Q	NET_ETH_PTYPE_VLAN
+#if !defined(ETH_P_CANFD)
+#define ETH_P_CANFD	NET_ETH_PTYPE_CANFD
 #endif
-#if !defined(ETH_P_TSN)
-#define ETH_P_TSN	NET_ETH_PTYPE_TSN
+#if !defined(ETH_P_EAPOL)
+#define ETH_P_EAPOL	NET_ETH_PTYPE_EAPOL
 #endif
 #if !defined(ETH_P_ECAT)
-#define  ETH_P_ECAT	NET_ETH_PTYPE_ECAT
+#define ETH_P_ECAT	NET_ETH_PTYPE_ECAT
 #endif
-#if !defined(ETH_P_EAPOL)
-#define ETH_P_EAPOL	NET_ETH_PTYPE_EAPOL
+#if !defined(ETH_P_HDLC)
+#define ETH_P_HDLC	NET_ETH_PTYPE_HDLC
 #endif
 #if !defined(ETH_P_IEEE802154)
-#define  ETH_P_IEEE802154 NET_ETH_PTYPE_IEEE802154
+#define ETH_P_IEEE802154 NET_ETH_PTYPE_IEEE802154
 #endif
-#if !defined(ETH_P_CAN)
-#define ETH_P_CAN	NET_ETH_PTYPE_CAN
+#if !defined(ETH_P_IP)
+#define ETH_P_IP	NET_ETH_PTYPE_IP
 #endif
-#if !defined(ETH_P_CANFD)
-#define ETH_P_CANFD	NET_ETH_PTYPE_CANFD
+#if !defined(ETH_P_IPV6)
+#define ETH_P_IPV6	NET_ETH_PTYPE_IPV6
 #endif
-#if !defined(ETH_P_HDLC)
-#define ETH_P_HDLC	NET_ETH_PTYPE_HDLC
+#if !defined(ETH_P_TSN)
+#define ETH_P_TSN	NET_ETH_PTYPE_TSN
 #endif
+/* zephyr-keep-sorted-stop */
 
 /** @endcond */
 
@@ -124,17 +130,9 @@ struct net_eth_addr {
 #endif
 
 #define _NET_ETH_MAX_FRAME_SIZE	(NET_ETH_MTU + _NET_ETH_MAX_HDR_SIZE)
-/*
- * Extend the max frame size for DSA (KSZ8794) by one byte (to 1519) to
- * store tail tag.
- */
-#if defined(CONFIG_NET_DSA)
+
 #define NET_ETH_MAX_FRAME_SIZE (_NET_ETH_MAX_FRAME_SIZE + DSA_TAG_SIZE)
 #define NET_ETH_MAX_HDR_SIZE (_NET_ETH_MAX_HDR_SIZE + DSA_TAG_SIZE)
-#else
-#define NET_ETH_MAX_FRAME_SIZE (_NET_ETH_MAX_FRAME_SIZE)
-#define NET_ETH_MAX_HDR_SIZE (_NET_ETH_MAX_HDR_SIZE)
-#endif
 
 #define NET_ETH_VLAN_HDR_SIZE	4
 
@@ -187,11 +185,11 @@ enum ethernet_hw_caps {
 	/** VLAN Tag stripping */
 	ETHERNET_HW_VLAN_TAG_STRIP	= BIT(14),
 
-	/** DSA switch slave port */
-	ETHERNET_DSA_SLAVE_PORT		= BIT(15),
+	/** DSA switch user port */
+	ETHERNET_DSA_USER_PORT		= BIT(15),
 
-	/** DSA switch master port */
-	ETHERNET_DSA_MASTER_PORT	= BIT(16),
+	/** DSA switch conduit port */
+	ETHERNET_DSA_CONDUIT_PORT	= BIT(16),
 
 	/** IEEE 802.1Qbv (scheduled traffic) supported */
 	ETHERNET_QBV			= BIT(17),
@@ -614,9 +612,7 @@ struct ethernet_vlan {
 #if defined(CONFIG_NET_VLAN_COUNT)
 #define NET_VLAN_MAX_COUNT CONFIG_NET_VLAN_COUNT
 #else
-/* Even thou there are no VLAN support, the minimum count must be set to 1.
- */
-#define NET_VLAN_MAX_COUNT 1
+#define NET_VLAN_MAX_COUNT 0
 #endif
 
 /** @endcond */
@@ -677,7 +673,14 @@ struct ethernet_context {
 	struct net_if *iface;
 
 #if defined(CONFIG_NET_LLDP)
-	struct ethernet_lldp lldp[NET_VLAN_MAX_COUNT];
+#if NET_VLAN_MAX_COUNT > 0
+#define NET_LLDP_MAX_COUNT NET_VLAN_MAX_COUNT
+#else
+#define NET_LLDP_MAX_COUNT 1
+#endif /* NET_VLAN_MAX_COUNT > 0 */
+
+	/** LLDP specific parameters */
+	struct ethernet_lldp lldp[NET_LLDP_MAX_COUNT];
 #endif
 
 	/**
@@ -693,7 +696,7 @@ struct ethernet_context {
 	int port;
 #endif
 
-#if defined(CONFIG_NET_DSA)
+#if defined(CONFIG_NET_DSA_DEPRECATED)
 	/** DSA RX callback function - for custom processing - like e.g.
 	 * redirecting packets when MAC address is caught
 	 */
@@ -707,6 +710,13 @@ struct ethernet_context {
 
 	/** Send a network packet via DSA master port */
 	dsa_send_t dsa_send;
+
+#elif defined(CONFIG_NET_DSA)
+	/** DSA port tpye */
+	enum dsa_port_type dsa_port;
+
+	/** DSA switch context pointer */
+	struct dsa_switch_context *dsa_switch_ctx;
 #endif
 
 	/** Is network carrier up */
@@ -944,12 +954,21 @@ enum ethernet_hw_caps net_eth_get_hw_capabilities(struct net_if *iface)
 {
 	const struct device *dev = net_if_get_device(iface);
 	const struct ethernet_api *api = (struct ethernet_api *)dev->api;
-
-	if (!api || !api->get_capabilities) {
-		return (enum ethernet_hw_caps)0;
+	enum ethernet_hw_caps caps = (enum ethernet_hw_caps)0;
+#if defined(CONFIG_NET_DSA) && !defined(CONFIG_NET_DSA_DEPRECATED)
+	struct ethernet_context *eth_ctx = net_if_l2_data(iface);
+
+	if (eth_ctx->dsa_port == DSA_CONDUIT_PORT) {
+		caps |= ETHERNET_DSA_CONDUIT_PORT;
+	} else if (eth_ctx->dsa_port == DSA_USER_PORT) {
+		caps |= ETHERNET_DSA_USER_PORT;
+	}
+#endif
+	if (api == NULL || api->get_capabilities == NULL) {
+		return caps;
 	}
 
-	return api->get_capabilities(dev);
+	return (enum ethernet_hw_caps)(caps | api->get_capabilities(dev));
 }
 
 /**
@@ -984,7 +1003,7 @@ int net_eth_get_hw_config(struct net_if *iface, enum ethernet_config_type type,
  *
  * @return 0 if ok, <0 if error
  */
-#if defined(CONFIG_NET_VLAN)
+#if defined(CONFIG_NET_VLAN) && NET_VLAN_MAX_COUNT > 0
 int net_eth_vlan_enable(struct net_if *iface, uint16_t tag);
 #else
 static inline int net_eth_vlan_enable(struct net_if *iface, uint16_t tag)
@@ -1004,7 +1023,7 @@ static inline int net_eth_vlan_enable(struct net_if *iface, uint16_t tag)
  *
  * @return 0 if ok, <0 if error
  */
-#if defined(CONFIG_NET_VLAN)
+#if defined(CONFIG_NET_VLAN) && NET_VLAN_MAX_COUNT > 0
 int net_eth_vlan_disable(struct net_if *iface, uint16_t tag);
 #else
 static inline int net_eth_vlan_disable(struct net_if *iface, uint16_t tag)
@@ -1027,7 +1046,7 @@ static inline int net_eth_vlan_disable(struct net_if *iface, uint16_t tag)
  * @return VLAN tag for this interface or NET_VLAN_TAG_UNSPEC if VLAN
  * is not configured for that interface.
  */
-#if defined(CONFIG_NET_VLAN)
+#if defined(CONFIG_NET_VLAN) && NET_VLAN_MAX_COUNT > 0
 uint16_t net_eth_get_vlan_tag(struct net_if *iface);
 #else
 static inline uint16_t net_eth_get_vlan_tag(struct net_if *iface)
@@ -1069,7 +1088,7 @@ struct net_if *net_eth_get_vlan_iface(struct net_if *iface, uint16_t tag)
  * @return Network interface related to this tag or NULL if no such interface
  * exists.
  */
-#if defined(CONFIG_NET_VLAN)
+#if defined(CONFIG_NET_VLAN) && NET_VLAN_MAX_COUNT > 0
 struct net_if *net_eth_get_vlan_main(struct net_if *iface);
 #else
 static inline
@@ -1115,7 +1134,7 @@ static inline bool net_eth_is_vlan_enabled(struct ethernet_context *ctx,
  *
  * @return True if VLAN is enabled for this network interface, false if not.
  */
-#if defined(CONFIG_NET_VLAN)
+#if defined(CONFIG_NET_VLAN) && NET_VLAN_MAX_COUNT > 0
 bool net_eth_get_vlan_status(struct net_if *iface);
 #else
 static inline bool net_eth_get_vlan_status(struct net_if *iface)
@@ -1133,7 +1152,7 @@ static inline bool net_eth_get_vlan_status(struct net_if *iface)
  *
  * @return True if this network interface is VLAN one, false if not.
  */
-#if defined(CONFIG_NET_VLAN)
+#if defined(CONFIG_NET_VLAN) && NET_VLAN_MAX_COUNT > 0
 bool net_eth_is_vlan_interface(struct net_if *iface);
 #else
 static inline bool net_eth_is_vlan_interface(struct net_if *iface)
@@ -1162,7 +1181,8 @@ static inline bool net_eth_is_vlan_interface(struct net_if *iface)
 				       init_fn, pm, data, config, prio,	\
 				       api, mtu)			\
 	Z_DEVICE_STATE_DEFINE(dev_id);					\
-	Z_DEVICE_DEFINE(node_id, dev_id, name, init_fn, pm, data,	\
+	Z_DEVICE_DEFINE(node_id, dev_id, name, init_fn, NULL,		\
+			Z_DEVICE_DT_FLAGS(node_id), pm, data,		\
 			config, POST_KERNEL, prio, api,			\
 			&Z_DEVICE_STATE_NAME(dev_id));
 
@@ -1260,6 +1280,16 @@ static inline bool net_eth_is_vlan_interface(struct net_if *iface)
 #define ETH_NET_DEVICE_DT_INST_DEFINE(inst, ...) \
 	ETH_NET_DEVICE_DT_DEFINE(DT_DRV_INST(inst), __VA_ARGS__)
 
+/**
+ * @brief Ethernet L3 protocol register macro.
+ *
+ * @param name Name of the L3 protocol.
+ * @param ptype Ethernet protocol type.
+ * @param handler Handler function for this protocol type.
+ */
+#define ETH_NET_L3_REGISTER(name, ptype, handler) \
+	NET_L3_REGISTER(&NET_L2_GET_NAME(ETHERNET), name, ptype, handler)
+
 /**
  * @brief Inform ethernet L2 driver that ethernet carrier is detected.
  * This happens when cable is connected.
diff --git a/include/zephyr/net/ethernet_vlan.h b/include/zephyr/net/ethernet_vlan.h
index ba969954812..ff9f32524af 100644
--- a/include/zephyr/net/ethernet_vlan.h
+++ b/include/zephyr/net/ethernet_vlan.h
@@ -31,6 +31,9 @@ extern "C" {
 /** Unspecified VLAN tag value */
 #define NET_VLAN_TAG_UNSPEC 0x0fff
 
+/** VLAN ID for forwarding to the native interface (priority tagging) */
+#define NET_VLAN_TAG_PRIORITY 0x0000
+
 /**
  * @brief Get VLAN identifier from TCI.
  *
diff --git a/include/zephyr/net/hostname.h b/include/zephyr/net/hostname.h
index f187427a9ab..4865843fd97 100644
--- a/include/zephyr/net/hostname.h
+++ b/include/zephyr/net/hostname.h
@@ -75,6 +75,8 @@ int net_hostname_set(char *host, size_t len);
 #else
 static inline int net_hostname_set(char *host, size_t len)
 {
+	ARG_UNUSED(host);
+	ARG_UNUSED(len);
 	return -ENOTSUP;
 }
 #endif
diff --git a/include/zephyr/net/http/client.h b/include/zephyr/net/http/client.h
index 71eb1b32f33..bc86ba48ab4 100644
--- a/include/zephyr/net/http/client.h
+++ b/include/zephyr/net/http/client.h
@@ -197,9 +197,16 @@ struct http_response {
 	 */
 	uint16_t http_status_code;
 
+	/**
+	 * HTTP Content-Range response field value. Consist of range_start,
+	 * range_end and total_size. Total is set to 0 if not supplied.
+	 */
+	struct http_content_range content_range;
+
 	uint8_t cl_present : 1;       /**< Is Content-Length field present */
 	uint8_t body_found : 1;       /**< Is message body found */
 	uint8_t message_complete : 1; /**< Is HTTP message parsing complete */
+	uint8_t cr_present : 1;       /**< Is Content-Range field present */
 };
 
 /** HTTP client internal data that the application should not touch
diff --git a/include/zephyr/net/http/parser.h b/include/zephyr/net/http/parser.h
index 38006f5e985..dab7d43b6ae 100644
--- a/include/zephyr/net/http/parser.h
+++ b/include/zephyr/net/http/parser.h
@@ -48,6 +48,7 @@ typedef unsigned __int64 uint64_t;
 #include <zephyr/net/http/method.h>
 #include <zephyr/net/http/parser_state.h>
 #include <zephyr/net/http/parser_url.h>
+#include <stdbool.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -133,6 +134,8 @@ enum http_errno {
 	HPE_INVALID_CONTENT_LENGTH,
 	HPE_UNEXPECTED_CONTENT_LENGTH,
 	HPE_INVALID_CHUNK_SIZE,
+	HPE_INVALID_CONTENT_RANGE,
+	HPE_UNEXPECTED_CONTENT_RANGE,
 	HPE_INVALID_CONSTANT,
 	HPE_INVALID_INTERNAL_STATE,
 	HPE_STRICT,
@@ -143,6 +146,11 @@ enum http_errno {
 /* Get an http_errno value from an http_parser */
 #define HTTP_PARSER_ERRNO(p)            ((enum http_errno) (p)->http_errno)
 
+struct http_content_range {
+	uint64_t start;
+	uint64_t end;
+	uint64_t total;
+};
 
 struct http_parser {
 	/** PRIVATE **/
@@ -160,6 +168,8 @@ struct http_parser {
 	uint64_t content_length; /* # bytes in body (0 if no Content-Length
 				  * header)
 				  */
+	bool content_range_present;
+	struct http_content_range content_range;
 	/** READ-ONLY **/
 	unsigned short http_major;
 	unsigned short http_minor;
diff --git a/include/zephyr/net/http/server.h b/include/zephyr/net/http/server.h
index 4cb40e52eb6..461ac22187e 100644
--- a/include/zephyr/net/http/server.h
+++ b/include/zephyr/net/http/server.h
@@ -138,6 +138,16 @@ struct http_resource_detail_static_fs {
 	const char *fs_path;
 };
 
+/** @brief HTTP compressions */
+enum http_compression {
+	HTTP_NONE = 0,     /**< NONE */
+	HTTP_GZIP = 1,     /**< GZIP */
+	HTTP_COMPRESS = 2, /**< COMPRESS */
+	HTTP_DEFLATE = 3,  /**< DEFLATE */
+	HTTP_BR = 4,       /**< BR */
+	HTTP_ZSTD = 5      /**< ZSTD */
+};
+
 /** @cond INTERNAL_HIDDEN */
 /* Make sure that the common is the first in the struct. */
 BUILD_ASSERT(offsetof(struct http_resource_detail_static_fs, common) == 0);
@@ -254,6 +264,7 @@ BUILD_ASSERT(offsetof(struct http_resource_detail_dynamic, common) == 0);
  *        reading and writing websocket data, and closing the connection.
  *
  * @param ws_socket A socket for the Websocket data.
+ * @param request_ctx Request context structure associated with HTTP upgrade request
  * @param user_data User specified data.
  *
  * @return  0 Accepting the connection, HTTP server library will no longer
@@ -261,7 +272,7 @@ BUILD_ASSERT(offsetof(struct http_resource_detail_dynamic, common) == 0);
  *            to send and receive data to/from the supplied socket.
  *         <0 error, close the connection.
  */
-typedef int (*http_resource_websocket_cb_t)(int ws_socket,
+typedef int (*http_resource_websocket_cb_t)(int ws_socket, struct http_request_ctx *request_ctx,
 					    void *user_data);
 
 /** @brief Representation of a websocket server resource */
@@ -399,6 +410,9 @@ struct http_client_ctx {
 	/** Socket descriptor associated with the server. */
 	int fd;
 
+	/** HTTP service on which the client is connected */
+	const struct http_service_desc *service;
+
 	/** Client data buffer.  */
 	unsigned char buffer[HTTP_SERVER_CLIENT_BUFFER_SIZE];
 
@@ -471,6 +485,11 @@ struct http_client_ctx {
 	IF_ENABLED(CONFIG_WEBSOCKET, (uint8_t ws_sec_key[HTTP_SERVER_WS_MAX_SEC_KEY_LEN]));
 /** @endcond */
 
+/** @cond INTERNAL_HIDDEN */
+	/** Client supported compression. */
+	IF_ENABLED(CONFIG_HTTP_SERVER_COMPRESSION, (uint8_t supported_compression));
+/** @endcond */
+
 	/** Flag indicating that HTTP2 preface was sent. */
 	bool preface_sent : 1;
 
@@ -489,6 +508,9 @@ struct http_client_ctx {
 	/** Flag indicating Websocket key is being processed. */
 	bool websocket_sec_key_next : 1;
 
+	/** Flag indicating accept encoding is being processed. */
+	IF_ENABLED(CONFIG_HTTP_SERVER_COMPRESSION, (bool accept_encoding_next: 1));
+
 	/** The next frame on the stream is expectd to be a continuation frame. */
 	bool expect_continuation : 1;
 };
diff --git a/include/zephyr/net/http/service.h b/include/zephyr/net/http/service.h
index 6a836b73348..20e4d30a995 100644
--- a/include/zephyr/net/http/service.h
+++ b/include/zephyr/net/http/service.h
@@ -19,6 +19,7 @@
  * @{
  */
 
+#include "zephyr/net/http/server.h"
 #include <stdint.h>
 #include <stddef.h>
 
@@ -64,30 +65,45 @@ struct http_resource_desc {
 
 /** @cond INTERNAL_HIDDEN */
 
+struct http_service_runtime_data {
+	int num_clients;
+};
+
 struct http_service_desc {
 	const char *host;
 	uint16_t *port;
+	int *fd;
 	void *detail;
 	size_t concurrent;
 	size_t backlog;
+	struct http_service_runtime_data *data;
 	struct http_resource_desc *res_begin;
 	struct http_resource_desc *res_end;
+	struct http_resource_detail *res_fallback;
 #if defined(CONFIG_NET_SOCKETS_SOCKOPT_TLS)
 	const sec_tag_t *sec_tag_list;
 	size_t sec_tag_list_size;
 #endif
 };
 
-#define __z_http_service_define(_name, _host, _port, _concurrent, _backlog, _detail, _res_begin,   \
-				_res_end, ...)                                                     \
-	const STRUCT_SECTION_ITERABLE(http_service_desc, _name) = {				   \
+#define __z_http_service_define(_name, _host, _port, _concurrent, _backlog, _detail,               \
+				_res_fallback, _res_begin, _res_end, ...)                          \
+	BUILD_ASSERT(_concurrent <= CONFIG_HTTP_SERVER_MAX_CLIENTS,                                \
+		     "can't accept more then MAX_CLIENTS");                                        \
+	BUILD_ASSERT(_backlog > 0, "backlog can't be 0");                                          \
+	static int _name##_fd = -1;                                                                \
+	static struct http_service_runtime_data _name##_data = {0};                                \
+	const STRUCT_SECTION_ITERABLE(http_service_desc, _name) = {                                \
 		.host = _host,                                                                     \
 		.port = (uint16_t *)(_port),                                                       \
+		.fd = &_name##_fd,                                                                 \
 		.detail = (void *)(_detail),                                                       \
 		.concurrent = (_concurrent),                                                       \
+		.data = &_name##_data,                                                             \
 		.backlog = (_backlog),                                                             \
 		.res_begin = (_res_begin),                                                         \
 		.res_end = (_res_end),                                                             \
+		.res_fallback = (_res_fallback),                                                   \
 		COND_CODE_1(CONFIG_NET_SOCKETS_SOCKOPT_TLS,                                        \
 			    (.sec_tag_list = COND_CODE_0(NUM_VA_ARGS_LESS_1(__VA_ARGS__), (NULL),  \
 							 (GET_ARG_N(1, __VA_ARGS__))),), ())       \
@@ -113,12 +129,15 @@ struct http_service_desc {
  * @param _name Name of the service.
  * @param _host IP address or hostname associated with the service.
  * @param[inout] _port Pointer to port associated with the service.
- * @param _concurrent Maximum number of concurrent clients.
- * @param _backlog Maximum number queued connections.
- * @param _detail Implementation-specific detail associated with the service.
+ * @param _concurrent Maximum number of concurrent clients. (max. CONFIG_HTTP_SERVER_MAX_CLIENTS)
+ * @param _backlog Maximum number of queued connections. (min. 1)
+ * @param _detail User-defined detail associated with the service.
+ * @param _res_fallback Fallback resource to be served if no other resource matches path
  */
-#define HTTP_SERVICE_DEFINE_EMPTY(_name, _host, _port, _concurrent, _backlog, _detail)             \
-	__z_http_service_define(_name, _host, _port, _concurrent, _backlog, _detail, NULL, NULL)
+#define HTTP_SERVICE_DEFINE_EMPTY(_name, _host, _port, _concurrent, _backlog, _detail,             \
+				  _res_fallback)                                                   \
+	__z_http_service_define(_name, _host, _port, _concurrent, _backlog, _detail,               \
+				_res_fallback, NULL, NULL)
 
 /**
  * @brief Define an HTTPS service without static resources.
@@ -135,15 +154,17 @@ struct http_service_desc {
  * @param _name Name of the service.
  * @param _host IP address or hostname associated with the service.
  * @param[inout] _port Pointer to port associated with the service.
- * @param _concurrent Maximum number of concurrent clients.
- * @param _backlog Maximum number queued connections.
- * @param _detail Implementation-specific detail associated with the service.
+ * @param _concurrent Maximum number of concurrent clients. (max. CONFIG_HTTP_SERVER_MAX_CLIENTS)
+ * @param _backlog Maximum number of queued connections. (min. 1)
+ * @param _detail User-defined detail associated with the service.
+ * @param _res_fallback Fallback resource to be served if no other resource matches path
  * @param _sec_tag_list TLS security tag list used to setup a HTTPS socket.
  * @param _sec_tag_list_size TLS security tag list size used to setup a HTTPS socket.
  */
 #define HTTPS_SERVICE_DEFINE_EMPTY(_name, _host, _port, _concurrent, _backlog, _detail,          \
-				   _sec_tag_list, _sec_tag_list_size)                            \
-	__z_http_service_define(_name, _host, _port, _concurrent, _backlog, _detail, NULL, NULL, \
+				   _res_fallback, _sec_tag_list, _sec_tag_list_size)             \
+	__z_http_service_define(_name, _host, _port, _concurrent, _backlog, _detail,             \
+				_res_fallback, NULL, NULL,                                       \
 				_sec_tag_list, _sec_tag_list_size);				 \
 	BUILD_ASSERT(IS_ENABLED(CONFIG_NET_SOCKETS_SOCKOPT_TLS),				 \
 		     "TLS is required for HTTP secure (CONFIG_NET_SOCKETS_SOCKOPT_TLS)")
@@ -163,16 +184,18 @@ struct http_service_desc {
  * @param _name Name of the service.
  * @param _host IP address or hostname associated with the service.
  * @param[inout] _port Pointer to port associated with the service.
- * @param _concurrent Maximum number of concurrent clients.
- * @param _backlog Maximum number queued connections.
- * @param _detail Implementation-specific detail associated with the service.
+ * @param _concurrent Maximum number of concurrent clients. (max. CONFIG_HTTP_SERVER_MAX_CLIENTS)
+ * @param _backlog Maximum number of queued connections. (min. 1)
+ * @param _detail User-defined detail associated with the service.
+ * @param _res_fallback Fallback resource to be served if no other resource matches path
  */
-#define HTTP_SERVICE_DEFINE(_name, _host, _port, _concurrent, _backlog, _detail)                   \
+#define HTTP_SERVICE_DEFINE(_name, _host, _port, _concurrent, _backlog, _detail, _res_fallback)    \
 	extern struct http_resource_desc _CONCAT(_http_resource_desc_##_name, _list_start)[];      \
 	extern struct http_resource_desc _CONCAT(_http_resource_desc_##_name, _list_end)[];        \
 	__z_http_service_define(_name, _host, _port, _concurrent, _backlog, _detail,               \
+				_res_fallback,                                                     \
 				&_CONCAT(_http_resource_desc_##_name, _list_start)[0],             \
-				&_CONCAT(_http_resource_desc_##_name, _list_end)[0])
+				&_CONCAT(_http_resource_desc_##_name, _list_end)[0]);
 
 /**
  * @brief Define an HTTPS service with static resources.
@@ -189,17 +212,19 @@ struct http_service_desc {
  * @param _name Name of the service.
  * @param _host IP address or hostname associated with the service.
  * @param[inout] _port Pointer to port associated with the service.
- * @param _concurrent Maximum number of concurrent clients.
- * @param _backlog Maximum number queued connections.
- * @param _detail Implementation-specific detail associated with the service.
+ * @param _concurrent Maximum number of concurrent clients. (max. CONFIG_HTTP_SERVER_MAX_CLIENTS)
+ * @param _backlog Maximum number of queued connections. (min. 1)
+ * @param _detail User-defined detail associated with the service.
+ * @param _res_fallback Fallback resource to be served if no other resource matches path
  * @param _sec_tag_list TLS security tag list used to setup a HTTPS socket.
  * @param _sec_tag_list_size TLS security tag list size used to setup a HTTPS socket.
  */
 #define HTTPS_SERVICE_DEFINE(_name, _host, _port, _concurrent, _backlog, _detail,              \
-			     _sec_tag_list, _sec_tag_list_size)                                \
+			     _res_fallback, _sec_tag_list, _sec_tag_list_size)                 \
 	extern struct http_resource_desc _CONCAT(_http_resource_desc_##_name, _list_start)[];  \
 	extern struct http_resource_desc _CONCAT(_http_resource_desc_##_name, _list_end)[];    \
 	__z_http_service_define(_name, _host, _port, _concurrent, _backlog, _detail,           \
+				_res_fallback,                                                 \
 				&_CONCAT(_http_resource_desc_##_name, _list_start)[0],         \
 				&_CONCAT(_http_resource_desc_##_name, _list_end)[0],           \
 				_sec_tag_list, _sec_tag_list_size);                            \
diff --git a/include/zephyr/net/ieee802154.h b/include/zephyr/net/ieee802154.h
index b60aa7071f3..762d8e8841f 100644
--- a/include/zephyr/net/ieee802154.h
+++ b/include/zephyr/net/ieee802154.h
@@ -296,7 +296,7 @@ struct ieee802154_context {
 	uint8_t ext_addr[IEEE802154_MAX_ADDR_LENGTH];
 
 	/** Link layer address (in big endian) */
-	struct net_linkaddr_storage linkaddr;
+	struct net_linkaddr linkaddr;
 
 #ifdef CONFIG_NET_L2_IEEE802154_SECURITY
 	/** Security context */
diff --git a/include/zephyr/net/lldp.h b/include/zephyr/net/lldp.h
index 0d638f2783e..2b447653712 100644
--- a/include/zephyr/net/lldp.h
+++ b/include/zephyr/net/lldp.h
@@ -225,16 +225,6 @@ typedef enum net_verdict (*net_lldp_recv_cb_t)(struct net_if *iface,
  */
 int net_lldp_register_callback(struct net_if *iface, net_lldp_recv_cb_t cb);
 
-/**
- * @brief Parse LLDP packet
- *
- * @param iface Network interface
- * @param pkt Network packet
- *
- * @return Return the policy for network buffer
- */
-enum net_verdict net_lldp_recv(struct net_if *iface, struct net_pkt *pkt);
-
 /**
  * @brief Set LLDP protocol data unit (LLDPDU) for the network interface.
  *
diff --git a/include/zephyr/net/net_context.h b/include/zephyr/net/net_context.h
index 80d84426789..e43113a3ab3 100644
--- a/include/zephyr/net/net_context.h
+++ b/include/zephyr/net/net_context.h
@@ -7,6 +7,7 @@
 /*
  * Copyright (c) 2016 Intel Corporation
  * Copyright (c) 2021 Nordic Semiconductor
+ * Copyright (c) 2025 Aerlync Labs Inc.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -390,6 +391,11 @@ __net_socket struct net_context {
 			 */
 			uint8_t ipv4_mcast_ifindex;
 		};
+		/** Flag to enable/disable multicast loop */
+		union {
+			bool ipv6_mcast_loop;  /**< IPv6 multicast loop */
+			bool ipv4_mcast_loop;  /**< IPv4 multicast loop */
+		};
 #endif /* CONFIG_NET_IPV6 || CONFIG_NET_IPV4 */
 
 #if defined(CONFIG_NET_CONTEXT_TIMESTAMPING)
@@ -838,6 +844,38 @@ static inline void net_context_set_ipv4_mcast_ttl(struct net_context *context,
 	context->ipv4_mcast_ttl = ttl;
 }
 
+#if defined(CONFIG_NET_IPV4)
+/**
+ * @brief Get IPv4 multicast loop value for this context.
+ *
+ * @details This function returns the IPv4 multicast loop value
+ *	    that is set to this context.
+ *
+ * @param context Network context.
+ *
+ * @return IPv4 multicast loop value
+ */
+static inline bool net_context_get_ipv4_mcast_loop(struct net_context *context)
+{
+	return context->options.ipv4_mcast_loop;
+}
+
+/**
+ * @brief Set IPv4 multicast loop value for this context.
+ *
+ * @details This function sets the IPv4 multicast loop value for
+ *	    this context.
+ *
+ * @param context Network context.
+ * @param ipv4_mcast_loop IPv4 multicast loop value.
+ */
+static inline void net_context_set_ipv4_mcast_loop(struct net_context *context,
+						   bool ipv4_mcast_loop)
+{
+	context->options.ipv4_mcast_loop = ipv4_mcast_loop;
+}
+#endif
+
 /**
  * @brief Get IPv6 hop limit value for this context.
  *
@@ -897,6 +935,40 @@ static inline void net_context_set_ipv6_mcast_hop_limit(struct net_context *cont
 	context->ipv6_mcast_hop_limit = hop_limit;
 }
 
+#if defined(CONFIG_NET_IPV6)
+
+/**
+ * @brief Get IPv6 multicast loop value for this context.
+ *
+ * @details This function returns the IPv6 multicast loop value
+ *          that is set to this context.
+ *
+ * @param context Network context.
+ *
+ * @return IPv6 multicast loop value
+ */
+static inline bool net_context_get_ipv6_mcast_loop(struct net_context *context)
+{
+	return context->options.ipv6_mcast_loop;
+}
+
+/**
+ * @brief Set IPv6 multicast loop value for this context.
+ *
+ * @details This function sets the IPv6 multicast loop value for
+ *          this context.
+ *
+ * @param context Network context.
+ * @param ipv6_mcast_loop IPv6 multicast loop value.
+ */
+static inline void net_context_set_ipv6_mcast_loop(struct net_context *context,
+						   bool ipv6_mcast_loop)
+{
+	context->options.ipv6_mcast_loop = ipv6_mcast_loop;
+}
+
+#endif
+
 /**
  * @brief Enable or disable socks proxy support for this context.
  *
@@ -1199,7 +1271,7 @@ int net_context_send(struct net_context *context,
  * @param dst_addr Destination address.
  * @param addrlen Length of the address.
  * @param cb Caller-supplied callback function.
- * @param timeout Currently this value is not used.
+ * @param timeout Timeout for the send attempt.
  * @param user_data Caller-supplied user data.
  *
  * @return numbers of bytes sent on success, a negative errno otherwise
@@ -1325,6 +1397,8 @@ enum net_context_option {
 	NET_OPT_MCAST_IFINDEX     = 19, /**< IPv6 multicast output network interface index */
 	NET_OPT_MTU               = 20, /**< IPv4 socket path MTU */
 	NET_OPT_LOCAL_PORT_RANGE  = 21, /**< Clamp local port range */
+	NET_OPT_IPV6_MCAST_LOOP	  = 22, /**< IPV6 multicast loop */
+	NET_OPT_IPV4_MCAST_LOOP	  = 23, /**< IPV4 multicast loop */
 };
 
 /**
diff --git a/include/zephyr/net/net_core.h b/include/zephyr/net/net_core.h
index 4b07aaa3e94..e4b18418b3a 100644
--- a/include/zephyr/net/net_core.h
+++ b/include/zephyr/net/net_core.h
@@ -21,6 +21,7 @@
 #include <zephyr/kernel.h>
 
 #include <zephyr/net/net_timeout.h>
+#include <zephyr/net/net_linkaddr.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -123,18 +124,38 @@ enum net_verdict {
 int net_recv_data(struct net_if *iface, struct net_pkt *pkt);
 
 /**
- * @brief Send data to network.
+ * @brief Try sending data to network.
  *
  * @details Send data to network. This should not be used normally by
  * applications as it requires that the network packet is properly
  * constructed.
  *
  * @param pkt Network packet.
+ * @param timeout Timeout for send.
  *
  * @return 0 if ok, <0 if error. If <0 is returned, then the caller needs
  * to unref the pkt in order to avoid memory leak.
  */
-int net_send_data(struct net_pkt *pkt);
+int net_try_send_data(struct net_pkt *pkt, k_timeout_t timeout);
+
+/**
+ * @brief Send data to network.
+ *
+ * @details Send data to network. This should not be used normally by
+ * applications as it requires that the network packet is properly
+ * constructed. Equivalent to net_try_send_data with infinite timeout.
+ *
+ * @param pkt Network packet.
+ *
+ * @return 0 if ok, <0 if error. If <0 is returned, then the caller needs
+ * to unref the pkt in order to avoid memory leak.
+ */
+static inline int net_send_data(struct net_pkt *pkt)
+{
+	k_timeout_t timeout = k_is_in_isr() ? K_NO_WAIT : K_FOREVER;
+
+	return net_try_send_data(pkt, timeout);
+}
 
 /** @cond INTERNAL_HIDDEN */
 
@@ -154,6 +175,46 @@ int net_send_data(struct net_pkt *pkt);
 #define NET_TC_COUNT 0
 #endif /* CONFIG_NET_TC_TX_COUNT && CONFIG_NET_TC_RX_COUNT */
 
+/**
+ * @brief Registration information for a given L3 handler. Note that
+ *        the layer number (L3) just refers to something that is on top
+ *        of L2. So for example IPv6 is L3 and IPv4 is L3, but Ethernet
+ *        based LLDP, gPTP are more in the layer 2.5 but we consider them
+ *        as L3 here for simplicity.
+ */
+struct net_l3_register {
+	/** Store also the name of the L3 type in order to be able to
+	 * print it later.
+	 */
+	const char * const name;
+	/** What L2 layer this is for */
+	const struct net_l2 * const l2;
+	/** Handler function for the specified protocol type. If the handler
+	 * has taken ownership of the pkt, it must return NET_OK. If it wants to
+	 * continue processing at the next level (e.g. ipv4), it must return
+	 * NET_CONTINUE. If instead something is wrong with the packet (for
+	 * example, a multicast address that does not match the protocol type)
+	 * it must return NET_DROP so that the statistics can be updated
+	 * accordingly
+	 */
+	enum net_verdict (*handler)(struct net_if *iface,
+				    uint16_t ptype,
+				    struct net_pkt *pkt);
+	/** Protocol type */
+	uint16_t ptype;
+};
+
+#define NET_L3_GET_NAME(l3_name, ptype) __net_l3_register_##l3_name##_##ptype
+
+#define NET_L3_REGISTER(_l2_type, _name, _ptype, _handler)		\
+	static const STRUCT_SECTION_ITERABLE(net_l3_register,		\
+				    NET_L3_GET_NAME(_name, _ptype)) = { \
+		.ptype = _ptype,					\
+		.handler = _handler,					\
+		.name = STRINGIFY(_name),				\
+		.l2 = _l2_type,						\
+	};
+
 /* @endcond */
 
 /**
diff --git a/include/zephyr/net/net_event.h b/include/zephyr/net/net_event.h
index f0f8545a713..8c403b057c6 100644
--- a/include/zephyr/net/net_event.h
+++ b/include/zephyr/net/net_event.h
@@ -123,6 +123,10 @@ enum net_event_l4_cmd {
 	NET_EVENT_L4_CMD_HOSTNAME_CHANGED,
 	NET_EVENT_L4_CMD_CAPTURE_STARTED,
 	NET_EVENT_L4_CMD_CAPTURE_STOPPED,
+	NET_EVENT_L4_CMD_VPN_CONNECTED,
+	NET_EVENT_L4_CMD_VPN_DISCONNECTED,
+	NET_EVENT_L4_CMD_VPN_PEER_ADD,
+	NET_EVENT_L4_CMD_VPN_PEER_DEL,
 };
 
 /** @endcond */
@@ -358,6 +362,22 @@ enum net_event_l4_cmd {
 #define NET_EVENT_CAPTURE_STOPPED			\
 	(_NET_EVENT_L4_BASE | NET_EVENT_L4_CMD_CAPTURE_STOPPED)
 
+/** Event emitted when VPN network connectivity is available. */
+#define NET_EVENT_VPN_CONNECTED				\
+	(_NET_EVENT_L4_BASE | NET_EVENT_L4_CMD_VPN_CONNECTED)
+
+/** Event emitted when VPN network connectivity is lost. */
+#define NET_EVENT_VPN_DISCONNECTED			\
+	(_NET_EVENT_L4_BASE | NET_EVENT_L4_CMD_VPN_DISCONNECTED)
+
+/** Event emitted when a VPN peer is added to the system. */
+#define NET_EVENT_VPN_PEER_ADD				\
+	(_NET_EVENT_L4_BASE | NET_EVENT_L4_CMD_VPN_PEER_ADD)
+
+/** Event emitted when a VPN peer is removed from the system. */
+#define NET_EVENT_VPN_PEER_DEL				\
+	(_NET_EVENT_L4_BASE | NET_EVENT_L4_CMD_VPN_PEER_DEL)
+
 /**
  * @brief Network Management event information structure
  * Used to pass information on network events like
diff --git a/include/zephyr/net/net_if.h b/include/zephyr/net/net_if.h
index 14981e9200d..ad6f721ac21 100644
--- a/include/zephyr/net/net_if.h
+++ b/include/zephyr/net/net_if.h
@@ -96,6 +96,11 @@ struct net_if_addr {
 		struct {
 			/** Duplicate address detection (DAD) timer */
 			sys_snode_t dad_node;
+
+			/** DAD needed list node */
+			sys_snode_t dad_need_node;
+
+			/** DAD start time */
 			uint32_t dad_start;
 
 			/** How many times we have done DAD */
@@ -106,6 +111,11 @@ struct net_if_addr {
 		struct {
 			/** Address conflict detection (ACD) timer. */
 			sys_snode_t acd_node;
+
+			/** ACD needed list node */
+			sys_snode_t acd_need_node;
+
+			/** ACD timeout value. */
 			k_timepoint_t acd_timeout;
 
 			/** ACD probe/announcement counter. */
@@ -136,7 +146,10 @@ struct net_if_addr {
 	 */
 	uint8_t is_temporary : 1;
 
-	uint8_t _unused : 4;
+	/** Was this address added or not */
+	uint8_t is_added : 1;
+
+	uint8_t _unused : 3;
 };
 
 /**
@@ -148,6 +161,9 @@ struct net_if_mcast_addr {
 	/** IP address */
 	struct net_addr address;
 
+	/** Rejoining multicast groups list node */
+	sys_snode_t rejoin_node;
+
 #if defined(CONFIG_NET_IPV4_IGMPV3)
 	/** Sources to filter on */
 	struct net_addr sources[CONFIG_NET_IF_MCAST_IPV4_SOURCE_COUNT];
@@ -614,6 +630,12 @@ struct net_traffic_class {
 	/** Fifo for handling this Tx or Rx packet */
 	struct k_fifo fifo;
 
+#if NET_TC_COUNT > 1 || defined(CONFIG_NET_TC_TX_SKIP_FOR_HIGH_PRIO) \
+	|| defined(CONFIG_NET_TC_RX_SKIP_FOR_HIGH_PRIO)
+	/** Semaphore for tracking the available slots in the fifo */
+	struct k_sem fifo_slot;
+#endif
+
 	/** Traffic class handler thread */
 	struct k_thread handler;
 
@@ -902,15 +924,34 @@ static inline enum net_if_oper_state net_if_oper_state(struct net_if *iface)
 	return iface->if_dev->oper_state;
 }
 
+/**
+ * @brief Try sending a packet through a net iface
+ *
+ * @param iface Pointer to a network interface structure
+ * @param pkt Pointer to a net packet to send
+ * @param timeout timeout for attempting to send
+ *
+ * @return verdict about the packet
+ */
+enum net_verdict net_if_try_send_data(struct net_if *iface,
+				      struct net_pkt *pkt, k_timeout_t timeout);
+
 /**
  * @brief Send a packet through a net iface
  *
+ * This is equivalent to net_if_try_queue_tx with an infinite timeout
  * @param iface Pointer to a network interface structure
  * @param pkt Pointer to a net packet to send
  *
- * return verdict about the packet
+ * @return verdict about the packet
  */
-enum net_verdict net_if_send_data(struct net_if *iface, struct net_pkt *pkt);
+static inline enum net_verdict net_if_send_data(struct net_if *iface,
+						struct net_pkt *pkt)
+{
+	k_timeout_t timeout = k_is_in_isr() ? K_NO_WAIT : K_FOREVER;
+
+	return net_if_try_send_data(iface, pkt, timeout);
+}
 
 /**
  * @brief Get a pointer to the interface L2
@@ -970,13 +1011,28 @@ static inline const struct device *net_if_get_device(struct net_if *iface)
 	return iface->if_dev->dev;
 }
 
+/**
+ * @brief Try enqueuing a packet to the net interface TX queue
+ *
+ * @param iface Pointer to a network interface structure
+ * @param pkt Pointer to a net packet to queue
+ * @param timeout Timeout for the enqueuing attempt
+ */
+void net_if_try_queue_tx(struct net_if *iface, struct net_pkt *pkt, k_timeout_t timeout);
+
 /**
  * @brief Queue a packet to the net interface TX queue
  *
+ * This is equivalent to net_if_try_queue_tx with an infinite timeout
  * @param iface Pointer to a network interface structure
  * @param pkt Pointer to a net packet to queue
  */
-void net_if_queue_tx(struct net_if *iface, struct net_pkt *pkt);
+static inline void net_if_queue_tx(struct net_if *iface, struct net_pkt *pkt)
+{
+	k_timeout_t timeout = k_is_in_isr() ? K_NO_WAIT : K_FOREVER;
+
+	net_if_try_queue_tx(iface, pkt, timeout);
+}
 
 /**
  * @brief Return the IP offload status
@@ -1190,13 +1246,20 @@ static inline int net_if_set_link_addr_unlocked(struct net_if *iface,
 						uint8_t *addr, uint8_t len,
 						enum net_link_type type)
 {
+	int ret;
+
 	if (net_if_flag_is_set(iface, NET_IF_RUNNING)) {
 		return -EPERM;
 	}
 
-	net_if_get_link_addr(iface)->addr = addr;
-	net_if_get_link_addr(iface)->len = len;
-	net_if_get_link_addr(iface)->type = type;
+	if (len > sizeof(net_if_get_link_addr(iface)->addr)) {
+		return -EINVAL;
+	}
+
+	ret = net_linkaddr_create(net_if_get_link_addr(iface), addr, len, type);
+	if (ret < 0) {
+		return ret;
+	}
 
 	net_hostname_set_postfix(addr, len);
 
@@ -1211,9 +1274,10 @@ int net_if_set_link_addr_locked(struct net_if *iface,
 extern int net_if_addr_unref_debug(struct net_if *iface,
 				   sa_family_t family,
 				   const void *addr,
+				   struct net_if_addr **ifaddr,
 				   const char *caller, int line);
-#define net_if_addr_unref(iface, family, addr) \
-	net_if_addr_unref_debug(iface, family, addr, __func__, __LINE__)
+#define net_if_addr_unref(iface, family, addr, ifaddr)			\
+	net_if_addr_unref_debug(iface, family, addr, ifaddr, __func__, __LINE__)
 
 extern struct net_if_addr *net_if_addr_ref_debug(struct net_if *iface,
 						 sa_family_t family,
@@ -1225,7 +1289,8 @@ extern struct net_if_addr *net_if_addr_ref_debug(struct net_if *iface,
 #else
 extern int net_if_addr_unref(struct net_if *iface,
 			     sa_family_t family,
-			     const void *addr);
+			     const void *addr,
+			     struct net_if_addr **ifaddr);
 extern struct net_if_addr *net_if_addr_ref(struct net_if *iface,
 					   sa_family_t family,
 					   const void *addr);
@@ -2142,6 +2207,32 @@ static inline struct net_if *net_if_ipv6_select_src_iface(
 }
 #endif
 
+/**
+ * @brief Get a network interface that should be used when sending
+ * IPv6 network data to destination. Also return the source IPv6 address from
+ * that network interface.
+ *
+ * @param dst IPv6 destination address
+ * @param src_addr IPv6 source address. This can be set to NULL if the source
+ *                 address is not needed.
+ *
+ * @return Pointer to network interface to use, NULL if no suitable interface
+ * could be found.
+ */
+#if defined(CONFIG_NET_IPV6)
+struct net_if *net_if_ipv6_select_src_iface_addr(const struct in6_addr *dst,
+						 const struct in6_addr **src_addr);
+#else
+static inline struct net_if *net_if_ipv6_select_src_iface_addr(
+	const struct in6_addr *dst, const struct in6_addr **src_addr)
+{
+	ARG_UNUSED(dst);
+	ARG_UNUSED(src_addr);
+
+	return NULL;
+}
+#endif /* CONFIG_NET_IPV6 */
+
 /**
  * @brief Get a IPv6 link local address in a given state.
  *
@@ -2523,6 +2614,32 @@ static inline struct net_if *net_if_ipv4_select_src_iface(
 }
 #endif
 
+/**
+ * @brief Get a network interface that should be used when sending
+ * IPv4 network data to destination. Also return the source IPv4 address from
+ * that network interface.
+ *
+ * @param dst IPv4 destination address
+ * @param src_addr IPv4 source address. This can be set to NULL if the source
+ *                 address is not needed.
+ *
+ * @return Pointer to network interface to use, NULL if no suitable interface
+ * could be found.
+ */
+#if defined(CONFIG_NET_IPV4)
+struct net_if *net_if_ipv4_select_src_iface_addr(const struct in_addr *dst,
+						 const struct in_addr **src_addr);
+#else
+static inline struct net_if *net_if_ipv4_select_src_iface_addr(
+	const struct in_addr *dst, const struct in_addr **src_addr)
+{
+	ARG_UNUSED(dst);
+	ARG_UNUSED(src_addr);
+
+	return NULL;
+}
+#endif /* CONFIG_NET_IPV4 */
+
 /**
  * @brief Get a IPv4 source address that should be used when sending
  * network data to destination.
@@ -3269,7 +3386,7 @@ extern int net_stats_prometheus_scrape(struct prometheus_collector *collector,
 	};								\
 	static Z_DECL_ALIGN(struct net_if)				\
 		       NET_IF_GET_NAME(dev_id, sfx)[_num_configs]	\
-		       __used __in_section(_net_if, static,		\
+		       __used __noasan __in_section(_net_if, static,	\
 					   dev_id) = {			\
 		[0 ... (_num_configs - 1)] = {				\
 			.if_dev = &(NET_IF_DEV_GET_NAME(dev_id, sfx)),	\
@@ -3320,7 +3437,8 @@ extern int net_stats_prometheus_scrape(struct prometheus_collector *collector,
 				   init_fn, pm, data, config, prio,	\
 				   api, l2, l2_ctx_type, mtu)		\
 	Z_DEVICE_STATE_DEFINE(dev_id);					\
-	Z_DEVICE_DEFINE(node_id, dev_id, name, init_fn, pm, data,	\
+	Z_DEVICE_DEFINE(node_id, dev_id, name, init_fn, NULL,		\
+			Z_DEVICE_DT_FLAGS(node_id), pm, data,		\
 			config, POST_KERNEL, prio, api,			\
 			&Z_DEVICE_STATE_NAME(dev_id));			\
 	NET_L2_DATA_INIT(dev_id, instance, l2_ctx_type);		\
@@ -3467,7 +3585,8 @@ extern int net_stats_prometheus_scrape(struct prometheus_collector *collector,
 #define Z_NET_DEVICE_OFFLOAD_INIT(node_id, dev_id, name, init_fn, pm,	\
 				  data, config, prio, api, mtu)		\
 	Z_DEVICE_STATE_DEFINE(dev_id);					\
-	Z_DEVICE_DEFINE(node_id, dev_id, name, init_fn, pm, data,	\
+	Z_DEVICE_DEFINE(node_id, dev_id, name, init_fn,	NULL,		\
+			Z_DEVICE_DT_FLAGS(node_id), pm, data,		\
 			config, POST_KERNEL, prio, api,			\
 			&Z_DEVICE_STATE_NAME(dev_id));			\
 	NET_IF_OFFLOAD_INIT(dev_id, 0, mtu)
diff --git a/include/zephyr/net/net_ip.h b/include/zephyr/net/net_ip.h
index 214b90cd305..e34e1e113ab 100644
--- a/include/zephyr/net/net_ip.h
+++ b/include/zephyr/net/net_ip.h
@@ -496,7 +496,11 @@ enum net_ip_mtu {
 	/** IPv4 MTU length. We must be able to receive this size IPv4 packet
 	 * without fragmentation.
 	 */
+#if defined(CONFIG_NET_NATIVE_IPV4)
+	NET_IPV4_MTU = CONFIG_NET_IPV4_MTU,
+#else
 	NET_IPV4_MTU = 576,
+#endif
 };
 
 /** @brief Network packet priority settings described in IEEE 802.1Q Annex I.1 */
@@ -1539,11 +1543,26 @@ static inline bool net_ipv6_addr_based_on_ll(const struct in6_addr *addr,
 		}
 
 		break;
+	default:
+		return false;
 	}
 
 	return false;
 }
 
+/**
+ * @brief Get sockaddr from sockaddr_storage. This is a helper so that
+ * the code calling this function can be made shorter.
+ *
+ * @param addr Socket storage address
+ *
+ * @return Pointer to socket address (struct sockaddr)
+ */
+static inline struct sockaddr *net_sad(const struct sockaddr_storage *addr)
+{
+	return (struct sockaddr *)addr;
+}
+
 /**
  * @brief Get sockaddr_in6 from sockaddr. This is a helper so that
  * the code calling this function can be made shorter.
@@ -1655,6 +1674,32 @@ __syscall int net_addr_pton(sa_family_t family, const char *src, void *dst);
 __syscall char *net_addr_ntop(sa_family_t family, const void *src,
 			      char *dst, size_t size);
 
+/**
+ * @brief Create netmask from mask length.
+ *
+ * @param family IP address family (AF_INET or AF_INET6)
+ * @param mask_len Netmask length (in IPv4) or prefix length (in IPv6)
+ * @param mask Pointer to struct sockaddr_in if family is AF_INET or
+ * pointer to struct sockaddr_in6 if family is AF_INET6
+ *
+ * @return 0 if ok, < 0 if error
+ */
+int net_mask_len_to_netmask(sa_family_t family, uint8_t mask_len,
+			    struct sockaddr *mask);
+
+/**
+ * @brief Create mask length from netmask.
+ *
+ * @param family IP address family (AF_INET or AF_INET6)
+ * @param mask Pointer to struct sockaddr_in if family is AF_INET or
+ * pointer to struct sockaddr_in6 if family is AF_INET6
+ * @param mask_len Netmask length (in IPv4) or prefix length (in IPv6)
+ *
+ * @return 0 if ok, < 0 if error
+ */
+int net_netmask_to_mask_len(sa_family_t family, struct sockaddr *mask,
+			    uint8_t *mask_len);
+
 /**
  * @brief Parse a string that contains either IPv4 or IPv6 address
  * and optional port, and store the information in user supplied
@@ -1679,6 +1724,36 @@ __syscall char *net_addr_ntop(sa_family_t family, const void *src,
 bool net_ipaddr_parse(const char *str, size_t str_len,
 		      struct sockaddr *addr);
 
+/**
+ * @brief Parse a string that contains either IPv4 or IPv6 address
+ * and optional mask len, and store the information in user supplied
+ * sockaddr struct. There can be multiple IP addresses separated by
+ * comma or space. The function returns the pointer to the next IP address
+ * in the string.
+ *
+ * @details Syntax of the IP address string:
+ *   192.0.2.1/24
+ *   192.0.2.42
+ *   2001:db8::1/64
+ *   2001:db8::2
+ *   2001:db::42/128
+ *   2001:db8::1/64,192.0.2.1,2001:db8::2,192.0.2.2/24
+ *   2001:db8::1/64 192.0.2.1 2001:db8::2 192.0.2.2/24
+ * Note that the str_len parameter is used to restrict the amount of
+ * characters that are checked.
+ *
+ * @param str String that contains the IP address.
+ * @param str_len Length of the string to be parsed.
+ * @param addr Pointer to user supplied struct sockaddr.
+ * @param mask_len Pointer to mask_len which is returned to the caller.
+ *
+ * @return NULL if there was an error while parsing.
+ *         "" if we could parse the IP address and there is nothing more to parse.
+ *         All other values point to next character after the "," or " " in the string.
+ */
+const char *net_ipaddr_parse_mask(const char *str, size_t str_len,
+				  struct sockaddr *addr, uint8_t *mask_len);
+
 /**
  * @brief Set the default port in the sockaddr structure.
  * If the port is already set, then do nothing.
diff --git a/include/zephyr/net/net_linkaddr.h b/include/zephyr/net/net_linkaddr.h
index e5f0d5f2fc0..1f5825e045f 100644
--- a/include/zephyr/net/net_linkaddr.h
+++ b/include/zephyr/net/net_linkaddr.h
@@ -61,22 +61,6 @@ enum net_link_type {
 	NET_LINK_CANBUS_RAW,
 } __packed;
 
-/**
- *  @brief Hardware link address structure
- *
- *  Used to hold the link address information
- */
-struct net_linkaddr {
-	/** The array of byte representing the address */
-	uint8_t *addr; /* in big endian */
-
-	/** Length of that address array */
-	uint8_t len;
-
-	/** What kind of address is this for */
-	uint8_t type;
-};
-
 /**
  *  @brief Hardware link address structure
  *
@@ -87,7 +71,7 @@ struct net_linkaddr {
  *  handled differently than uint8_t addr[] and the fields are purposely
  *  in different order.
  */
-struct net_linkaddr_storage {
+struct net_linkaddr {
 	/** What kind of address is this for */
 	uint8_t type;
 
@@ -124,15 +108,17 @@ static inline bool net_linkaddr_cmp(struct net_linkaddr *lladdr1,
  *
  * @brief Set the member data of a link layer address storage structure.
  *
- * @param lladdr_store The link address storage structure to change.
+ * @param lladdr The link address storage structure to change.
  * @param new_addr Array of bytes containing the link address.
  * @param new_len Length of the link address array.
  * This value should always be <= NET_LINK_ADDR_MAX_LENGTH.
+ * @return 0 if ok, <0 if error
  */
-static inline int net_linkaddr_set(struct net_linkaddr_storage *lladdr_store,
-				   uint8_t *new_addr, uint8_t new_len)
+static inline int net_linkaddr_set(struct net_linkaddr *lladdr,
+				   const uint8_t *new_addr,
+				   uint8_t new_len)
 {
-	if (!lladdr_store || !new_addr) {
+	if (lladdr == NULL || new_addr == NULL) {
 		return -EINVAL;
 	}
 
@@ -140,12 +126,82 @@ static inline int net_linkaddr_set(struct net_linkaddr_storage *lladdr_store,
 		return -EMSGSIZE;
 	}
 
-	lladdr_store->len = new_len;
-	memcpy(lladdr_store->addr, new_addr, new_len);
+	lladdr->len = new_len;
+	memcpy(lladdr->addr, new_addr, new_len);
 
 	return 0;
 }
 
+/**
+ * @brief Copy link address from one variable to another.
+ *
+ * @param dst The link address structure destination.
+ * @param src The link address structure to source.
+ * @return 0 if ok, <0 if error
+ */
+static inline int net_linkaddr_copy(struct net_linkaddr *dst,
+				    const struct net_linkaddr *src)
+{
+	if (dst == NULL || src == NULL) {
+		return -EINVAL;
+	}
+
+	if (src->len > NET_LINK_ADDR_MAX_LENGTH) {
+		return -EMSGSIZE;
+	}
+
+	dst->type = src->type;
+	dst->len = src->len;
+	memcpy(dst->addr, src->addr, src->len);
+
+	return 0;
+}
+
+/**
+ * @brief Create a link address structure.
+ *
+ * @param lladdr The link address structure to change.
+ * @param addr Array of bytes containing the link address. If set to NULL,
+ * the address will be cleared.
+ * @param len Length of the link address array.
+ * @param type Type of the link address.
+ * @return 0 if ok, <0 if error
+ */
+static inline int net_linkaddr_create(struct net_linkaddr *lladdr,
+				      const uint8_t *addr, uint8_t len,
+				      enum net_link_type type)
+{
+	if (lladdr == NULL) {
+		return -EINVAL;
+	}
+
+	if (len > NET_LINK_ADDR_MAX_LENGTH) {
+		return -EMSGSIZE;
+	}
+
+	if (addr == NULL) {
+		memset(lladdr->addr, 0, NET_LINK_ADDR_MAX_LENGTH);
+	} else {
+		memcpy(lladdr->addr, addr, len);
+	}
+
+	lladdr->type = type;
+	lladdr->len = len;
+
+	return 0;
+}
+
+/**
+ * @brief Clear link address.
+ *
+ * @param lladdr The link address structure.
+ * @return 0 if ok, <0 if error
+ */
+static inline int net_linkaddr_clear(struct net_linkaddr *lladdr)
+{
+	return net_linkaddr_create(lladdr, NULL, 0, NET_LINK_UNKNOWN);
+}
+
 /**
  * @}
  */
diff --git a/include/zephyr/net/net_mgmt.h b/include/zephyr/net/net_mgmt.h
index fe3ee7f946d..876e4b66565 100644
--- a/include/zephyr/net/net_mgmt.h
+++ b/include/zephyr/net/net_mgmt.h
@@ -345,6 +345,12 @@ static inline int net_mgmt_event_wait(uint32_t mgmt_event_mask,
 				      size_t *info_length,
 				      k_timeout_t timeout)
 {
+	ARG_UNUSED(mgmt_event_mask);
+	ARG_UNUSED(raised_event);
+	ARG_UNUSED(iface);
+	ARG_UNUSED(info);
+	ARG_UNUSED(info_length);
+	ARG_UNUSED(timeout);
 	return 0;
 }
 #endif
@@ -383,6 +389,12 @@ static inline int net_mgmt_event_wait_on_iface(struct net_if *iface,
 					       size_t *info_length,
 					       k_timeout_t timeout)
 {
+	ARG_UNUSED(iface);
+	ARG_UNUSED(mgmt_event_mask);
+	ARG_UNUSED(raised_event);
+	ARG_UNUSED(info);
+	ARG_UNUSED(info_length);
+	ARG_UNUSED(timeout);
 	return 0;
 }
 #endif
diff --git a/include/zephyr/net/net_pkt.h b/include/zephyr/net/net_pkt.h
index 5fd05f658da..a05c3f1629d 100644
--- a/include/zephyr/net/net_pkt.h
+++ b/include/zephyr/net/net_pkt.h
@@ -123,6 +123,19 @@ struct net_pkt {
 	struct net_if *orig_iface; /* Original network interface */
 #endif
 
+#if defined(CONFIG_NET_VPN)
+	struct {
+		/** Original network interface */
+		struct net_if *iface;
+		/** Pointer to IP header of the encrypted pkt */
+		union net_ip_header ip_hdr;
+		/** Pointer to UDP header of the encrypted pkt */
+		union net_proto_header proto_hdr;
+		/** Peer id */
+		int peer_id;
+	} vpn;
+#endif
+
 #if defined(CONFIG_NET_PKT_TIMESTAMP) || defined(CONFIG_NET_PKT_TXTIME)
 	/**
 	 * TX or RX timestamp if available
@@ -410,6 +423,52 @@ static inline void net_pkt_set_orig_iface(struct net_pkt *pkt,
 #endif
 }
 
+#if defined(CONFIG_NET_VPN)
+static inline struct net_if *net_pkt_vpn_iface(struct net_pkt *pkt)
+{
+	return pkt->vpn.iface;
+}
+
+static inline void net_pkt_set_vpn_iface(struct net_pkt *pkt,
+					 struct net_if *iface)
+{
+	pkt->vpn.iface = iface;
+}
+
+static inline union net_ip_header *net_pkt_vpn_ip_hdr(struct net_pkt *pkt)
+{
+	return &pkt->vpn.ip_hdr;
+}
+
+static inline void net_pkt_set_vpn_ip_hdr(struct net_pkt *pkt,
+					  union net_ip_header *ip_hdr)
+{
+	pkt->vpn.ip_hdr = *ip_hdr;
+}
+
+static inline union net_proto_header *net_pkt_vpn_udp_hdr(struct net_pkt *pkt)
+{
+	return &pkt->vpn.proto_hdr;
+}
+
+static inline void net_pkt_set_vpn_udp_hdr(struct net_pkt *pkt,
+					   union net_proto_header *proto_hdr)
+{
+	pkt->vpn.proto_hdr = *proto_hdr;
+}
+
+static inline int net_pkt_vpn_peer_id(struct net_pkt *pkt)
+{
+	return pkt->vpn.peer_id;
+}
+
+static inline void net_pkt_set_vpn_peer_id(struct net_pkt *pkt,
+					   int peer_id)
+{
+	pkt->vpn.peer_id = peer_id;
+}
+#endif /* CONFIG_NET_VPN */
+
 static inline uint8_t net_pkt_family(struct net_pkt *pkt)
 {
 	return pkt->family;
@@ -1257,11 +1316,6 @@ static inline void net_pkt_set_stats_tick(struct net_pkt *pkt, uint32_t tick)
 #endif /* CONFIG_NET_PKT_TXTIME_STATS_DETAIL ||
 	  CONFIG_NET_PKT_RXTIME_STATS_DETAIL */
 
-static inline size_t net_pkt_get_len(struct net_pkt *pkt)
-{
-	return net_buf_frags_len(pkt->frags);
-}
-
 static inline uint8_t *net_pkt_data(struct net_pkt *pkt)
 {
 	return pkt->frags->data;
@@ -1289,16 +1343,23 @@ static inline struct net_linkaddr *net_pkt_lladdr_dst(struct net_pkt *pkt)
 
 static inline void net_pkt_lladdr_swap(struct net_pkt *pkt)
 {
-	uint8_t *addr = net_pkt_lladdr_src(pkt)->addr;
+	struct net_linkaddr tmp;
 
-	net_pkt_lladdr_src(pkt)->addr = net_pkt_lladdr_dst(pkt)->addr;
-	net_pkt_lladdr_dst(pkt)->addr = addr;
+	memcpy(tmp.addr,
+	       net_pkt_lladdr_src(pkt)->addr,
+	       net_pkt_lladdr_src(pkt)->len);
+	memcpy(net_pkt_lladdr_src(pkt)->addr,
+	       net_pkt_lladdr_dst(pkt)->addr,
+	       net_pkt_lladdr_dst(pkt)->len);
+	memcpy(net_pkt_lladdr_dst(pkt)->addr,
+	       tmp.addr,
+	       net_pkt_lladdr_src(pkt)->len);
 }
 
 static inline void net_pkt_lladdr_clear(struct net_pkt *pkt)
 {
-	net_pkt_lladdr_src(pkt)->addr = NULL;
-	net_pkt_lladdr_src(pkt)->len = 0U;
+	(void)net_linkaddr_clear(net_pkt_lladdr_src(pkt));
+	(void)net_linkaddr_clear(net_pkt_lladdr_dst(pkt));
 }
 
 static inline uint16_t net_pkt_ll_proto_type(struct net_pkt *pkt)
@@ -2476,6 +2537,18 @@ static inline int net_pkt_write_le16(struct net_pkt *pkt, uint16_t data)
  */
 size_t net_pkt_remaining_data(struct net_pkt *pkt);
 
+/**
+ * @brief Get the total amount of bytes stored in a packet.
+ *
+ * @param pkt Network packet
+ *
+ * @return Total amount of bytes stored in a packet.
+ */
+static inline size_t net_pkt_get_len(struct net_pkt *pkt)
+{
+	return net_buf_frags_len(pkt->frags);
+}
+
 /**
  * @brief Update the overall length of a packet
  *
diff --git a/include/zephyr/net/net_pkt_filter.h b/include/zephyr/net/net_pkt_filter.h
index 15406b6e6a7..1ee42e51b70 100644
--- a/include/zephyr/net/net_pkt_filter.h
+++ b/include/zephyr/net/net_pkt_filter.h
@@ -39,11 +39,48 @@ struct npf_test;
 
 typedef bool (npf_test_fn_t)(struct npf_test *test, struct net_pkt *pkt);
 
+enum npf_test_type {
+	NPF_TEST_TYPE_UNKNOWN = 0,
+	NPF_TEST_TYPE_IFACE_MATCH,
+	NPF_TEST_TYPE_IFACE_UNMATCH,
+	NPF_TEST_TYPE_ORIG_IFACE_MATCH,
+	NPF_TEST_TYPE_ORIG_IFACE_UNMATCH,
+	NPF_TEST_TYPE_SIZE_MIN,
+	NPF_TEST_TYPE_SIZE_MAX,
+	NPF_TEST_TYPE_SIZE_BOUNDS,
+	NPF_TEST_TYPE_IP_SRC_ADDR_ALLOWLIST,
+	NPF_TEST_TYPE_IP_SRC_ADDR_BLOCKLIST,
+	NPF_TEST_TYPE_ETH_SRC_ADDR_MATCH,
+	NPF_TEST_TYPE_ETH_SRC_ADDR_UNMATCH,
+	NPF_TEST_TYPE_ETH_DST_ADDR_MATCH,
+	NPF_TEST_TYPE_ETH_DST_ADDR_UNMATCH,
+	NPF_TEST_TYPE_ETH_SRC_ADDR_MASK_MATCH,
+	NPF_TEST_TYPE_ETH_DST_ADDR_MASK_MATCH,
+	NPF_TEST_TYPE_ETH_TYPE_MATCH,
+	NPF_TEST_TYPE_ETH_TYPE_UNMATCH,
+	NPF_TEST_TYPE_ETH_VLAN_TYPE_MATCH,
+	NPF_TEST_TYPE_ETH_VLAN_TYPE_UNMATCH,
+};
+
+#if defined(CONFIG_NET_PKT_FILTER_LOG_LEVEL_DBG) || \
+	defined(CONFIG_NET_SHELL_PKT_FILTER_SUPPORTED)
+#define NPF_TEST_ENABLE_NAME 1
+#elif defined(NPF_TEST_ENABLE_NAME)
+#undef NPF_TEST_ENABLE_NAME
+#endif
+
 /** @endcond */
 
 /** @brief common filter test structure to be embedded into larger structures */
 struct npf_test {
 	npf_test_fn_t *fn;	/**< packet condition test function */
+
+/** @cond INTERNAL_HIDDEN */
+	IF_ENABLED(NPF_TEST_ENABLE_NAME,
+		   (const char *name;))        /**< Name of the test */
+	IF_ENABLED(NPF_TEST_ENABLE_NAME,
+		   (enum npf_test_type type;)) /**< Type of the test */
+/** @endcond */
 };
 
 /** @brief filter rule structure */
@@ -237,10 +274,13 @@ extern npf_test_fn_t npf_orig_iface_unmatch;
  * @param _name Name of the condition
  * @param _iface Interface to match
  */
-#define NPF_IFACE_MATCH(_name, _iface) \
-	struct npf_test_iface _name = { \
-		.iface = (_iface), \
-		.test.fn = npf_iface_match, \
+#define NPF_IFACE_MATCH(_name, _iface)					\
+	struct npf_test_iface _name = {					\
+		.iface = (_iface),					\
+		.test.fn = npf_iface_match,				\
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,			\
+			   (.test.name = "iface",			\
+			    .test.type = NPF_TEST_TYPE_IFACE_MATCH,))	\
 	}
 
 /**
@@ -249,10 +289,13 @@ extern npf_test_fn_t npf_orig_iface_unmatch;
  * @param _name Name of the condition
  * @param _iface Interface to exclude
  */
-#define NPF_IFACE_UNMATCH(_name, _iface) \
-	struct npf_test_iface _name = { \
-		.iface = (_iface), \
-		.test.fn = npf_iface_unmatch, \
+#define NPF_IFACE_UNMATCH(_name, _iface)				\
+	struct npf_test_iface _name = {					\
+		.iface = (_iface),					\
+		.test.fn = npf_iface_unmatch,				\
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,			\
+			   (.test.name = "!iface",			\
+			    .test.type = NPF_TEST_TYPE_IFACE_UNMATCH,))	\
 	}
 
 /**
@@ -261,10 +304,13 @@ extern npf_test_fn_t npf_orig_iface_unmatch;
  * @param _name Name of the condition
  * @param _iface Interface to match
  */
-#define NPF_ORIG_IFACE_MATCH(_name, _iface) \
-	struct npf_test_iface _name = { \
-		.iface = (_iface), \
-		.test.fn = npf_orig_iface_match, \
+#define NPF_ORIG_IFACE_MATCH(_name, _iface)				\
+	struct npf_test_iface _name = {					\
+		.iface = (_iface),					\
+		.test.fn = npf_orig_iface_match,			\
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,			\
+			   (.test.name = "orig iface",			\
+			    .test.type = NPF_TEST_TYPE_ORIG_IFACE_MATCH,)) \
 	}
 
 /**
@@ -273,10 +319,13 @@ extern npf_test_fn_t npf_orig_iface_unmatch;
  * @param _name Name of the condition
  * @param _iface Interface to exclude
  */
-#define NPF_ORIG_IFACE_UNMATCH(_name, _iface) \
-	struct npf_test_iface _name = { \
-		.iface = (_iface), \
-		.test.fn = npf_orig_iface_unmatch, \
+#define NPF_ORIG_IFACE_UNMATCH(_name, _iface)				\
+	struct npf_test_iface _name = {					\
+		.iface = (_iface),					\
+		.test.fn = npf_orig_iface_unmatch,			\
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,			\
+			   (.test.name = "!orig iface",			\
+			    .test.type = NPF_TEST_TYPE_ORIG_IFACE_UNMATCH,)) \
 	}
 
 /** @cond INTERNAL_HIDDEN */
@@ -297,11 +346,14 @@ extern npf_test_fn_t npf_size_inbounds;
  * @param _name Name of the condition
  * @param _size Lower bound of the packet's data size
  */
-#define NPF_SIZE_MIN(_name, _size) \
-	struct npf_test_size_bounds _name = { \
-		.min = (_size), \
-		.max = SIZE_MAX, \
-		.test.fn = npf_size_inbounds, \
+#define NPF_SIZE_MIN(_name, _size)				   \
+	struct npf_test_size_bounds _name = {			   \
+		.min = (_size),					   \
+		.max = SIZE_MAX,				   \
+		.test.fn = npf_size_inbounds,			   \
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,		   \
+			   (.test.name = "size min",		   \
+			    .test.type = NPF_TEST_TYPE_SIZE_MIN,)) \
 	}
 
 /**
@@ -310,11 +362,14 @@ extern npf_test_fn_t npf_size_inbounds;
  * @param _name Name of the condition
  * @param _size Higher bound of the packet's data size
  */
-#define NPF_SIZE_MAX(_name, _size) \
-	struct npf_test_size_bounds _name = { \
-		.min = 0, \
-		.max = (_size), \
-		.test.fn = npf_size_inbounds, \
+#define NPF_SIZE_MAX(_name, _size)				   \
+	struct npf_test_size_bounds _name = {			   \
+		.min = 0,					   \
+		.max = (_size),					   \
+		.test.fn = npf_size_inbounds,			   \
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,		   \
+			   (.test.name = "size max",		   \
+			    .test.type = NPF_TEST_TYPE_SIZE_MAX,)) \
 	}
 
 /**
@@ -324,11 +379,14 @@ extern npf_test_fn_t npf_size_inbounds;
  * @param _min_size Lower bound of the packet's data size
  * @param _max_size Higher bound of the packet's data size
  */
-#define NPF_SIZE_BOUNDS(_name, _min_size, _max_size) \
-	struct npf_test_size_bounds _name = { \
-		.min = (_min_size), \
-		.max = (_max_size), \
-		.test.fn = npf_size_inbounds, \
+#define NPF_SIZE_BOUNDS(_name, _min_size, _max_size)		      \
+	struct npf_test_size_bounds _name = {			      \
+		.min = (_min_size),				      \
+		.max = (_max_size),				      \
+		.test.fn = npf_size_inbounds,			      \
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,		      \
+			   (.test.name = "size bounds",		      \
+			    .test.type = NPF_TEST_TYPE_SIZE_BOUNDS,)) \
 	}
 
 /** @cond INTERNAL_HIDDEN */
@@ -358,11 +416,14 @@ extern npf_test_fn_t npf_ip_src_addr_unmatch;
  * @param _af Addresses family type (AF_INET / AF_INET6) in the array
  */
 #define NPF_IP_SRC_ADDR_ALLOWLIST(_name, _ip_addr_array, _ip_addr_num, _af) \
-	struct npf_test_ip _name = { \
-		.addr_family = _af, \
-		.ipaddr = (_ip_addr_array), \
-		.ipaddr_num = _ip_addr_num, \
-		.test.fn = npf_ip_src_addr_match, \
+	struct npf_test_ip _name = {					\
+		.addr_family = _af,					\
+		.ipaddr = (_ip_addr_array),				\
+		.ipaddr_num = _ip_addr_num,				\
+		.test.fn = npf_ip_src_addr_match,			\
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,			\
+			   (.test.name = "ip src allow",		\
+			    .test.type = NPF_TEST_TYPE_IP_SRC_ADDR_ALLOWLIST,)) \
 	}
 
 /**
@@ -378,11 +439,14 @@ extern npf_test_fn_t npf_ip_src_addr_unmatch;
  * @param _af Addresses family type (AF_INET / AF_INET6) in the array
  */
 #define NPF_IP_SRC_ADDR_BLOCKLIST(_name, _ip_addr_array, _ip_addr_num, _af) \
-	struct npf_test_ip _name = { \
-		.addr_family = _af, \
-		.ipaddr = (_ip_addr_array), \
-		.ipaddr_num = _ip_addr_num, \
-		.test.fn = npf_ip_src_addr_unmatch, \
+	struct npf_test_ip _name = {					\
+		.addr_family = _af,					\
+		.ipaddr = (_ip_addr_array),				\
+		.ipaddr_num = _ip_addr_num,				\
+		.test.fn = npf_ip_src_addr_unmatch,			\
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,			\
+			   (.test.name = "ip src block",		\
+			    .test.type = NPF_TEST_TYPE_IP_SRC_ADDR_BLOCKLIST,)) \
 	}
 
 /** @} */
@@ -420,12 +484,15 @@ extern npf_test_fn_t npf_eth_dst_addr_unmatch;
  * @param _name Name of the condition
  * @param _addr_array Array of <tt>struct net_eth_addr</tt> items to test against
  */
-#define NPF_ETH_SRC_ADDR_MATCH(_name, _addr_array) \
-	struct npf_test_eth_addr _name = { \
-		.addresses = (_addr_array), \
-		.nb_addresses = ARRAY_SIZE(_addr_array), \
-		.test.fn = npf_eth_src_addr_match, \
-		.mask.addr = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, \
+#define NPF_ETH_SRC_ADDR_MATCH(_name, _addr_array)			\
+	struct npf_test_eth_addr _name = {				\
+		.addresses = (_addr_array),				\
+		.nb_addresses = ARRAY_SIZE(_addr_array),		\
+		.test.fn = npf_eth_src_addr_match,			\
+		.mask.addr = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },	\
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,			\
+			   (.test.name = "eth src",			\
+			    .test.type = NPF_TEST_TYPE_ETH_SRC_ADDR_MATCH,)) \
 	}
 
 /**
@@ -437,12 +504,15 @@ extern npf_test_fn_t npf_eth_dst_addr_unmatch;
  * @param _name Name of the condition
  * @param _addr_array Array of <tt>struct net_eth_addr</tt> items to test against
  */
-#define NPF_ETH_SRC_ADDR_UNMATCH(_name, _addr_array) \
-	struct npf_test_eth_addr _name = { \
-		.addresses = (_addr_array), \
-		.nb_addresses = ARRAY_SIZE(_addr_array), \
-		.test.fn = npf_eth_src_addr_unmatch, \
-		.mask.addr = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, \
+#define NPF_ETH_SRC_ADDR_UNMATCH(_name, _addr_array)			\
+	struct npf_test_eth_addr _name = {				\
+		.addresses = (_addr_array),				\
+		.nb_addresses = ARRAY_SIZE(_addr_array),		\
+		.test.fn = npf_eth_src_addr_unmatch,			\
+		.mask.addr = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },	\
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,			\
+			   (.test.name = "!eth src",			\
+			    .test.type = NPF_TEST_TYPE_ETH_SRC_ADDR_UNMATCH,)) \
 	}
 
 /**
@@ -454,12 +524,15 @@ extern npf_test_fn_t npf_eth_dst_addr_unmatch;
  * @param _name Name of the condition
  * @param _addr_array Array of <tt>struct net_eth_addr</tt> items to test against
  */
-#define NPF_ETH_DST_ADDR_MATCH(_name, _addr_array) \
-	struct npf_test_eth_addr _name = { \
-		.addresses = (_addr_array), \
-		.nb_addresses = ARRAY_SIZE(_addr_array), \
-		.test.fn = npf_eth_dst_addr_match, \
-		.mask.addr = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, \
+#define NPF_ETH_DST_ADDR_MATCH(_name, _addr_array)			\
+	struct npf_test_eth_addr _name = {				\
+		.addresses = (_addr_array),				\
+		.nb_addresses = ARRAY_SIZE(_addr_array),		\
+		.test.fn = npf_eth_dst_addr_match,			\
+		.mask.addr = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },	\
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,			\
+			   (.test.name = "eth dst",			\
+			    .test.type = NPF_TEST_TYPE_ETH_DST_ADDR_MATCH,)) \
 	}
 
 /**
@@ -471,12 +544,15 @@ extern npf_test_fn_t npf_eth_dst_addr_unmatch;
  * @param _name Name of the condition
  * @param _addr_array Array of <tt>struct net_eth_addr</tt> items to test against
  */
-#define NPF_ETH_DST_ADDR_UNMATCH(_name, _addr_array) \
-	struct npf_test_eth_addr _name = { \
-		.addresses = (_addr_array), \
-		.nb_addresses = ARRAY_SIZE(_addr_array), \
-		.test.fn = npf_eth_dst_addr_unmatch, \
-		.mask.addr = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, \
+#define NPF_ETH_DST_ADDR_UNMATCH(_name, _addr_array)			\
+	struct npf_test_eth_addr _name = {				\
+		.addresses = (_addr_array),				\
+		.nb_addresses = ARRAY_SIZE(_addr_array),		\
+		.test.fn = npf_eth_dst_addr_unmatch,			\
+		.mask.addr = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff },	\
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,			\
+			   (.test.name = "!eth dst",			\
+			    .test.type = NPF_TEST_TYPE_ETH_DST_ADDR_UNMATCH,)) \
 	}
 
 /**
@@ -489,12 +565,15 @@ extern npf_test_fn_t npf_eth_dst_addr_unmatch;
  * @param _addr_array Array of <tt>struct net_eth_addr</tt> items to test against
  * @param ... up to 6 mask bytes
  */
-#define NPF_ETH_SRC_ADDR_MASK_MATCH(_name, _addr_array, ...) \
-	struct npf_test_eth_addr _name = { \
-		.addresses = (_addr_array), \
-		.nb_addresses = ARRAY_SIZE(_addr_array), \
-		.mask.addr = { __VA_ARGS__ }, \
-		.test.fn = npf_eth_src_addr_match, \
+#define NPF_ETH_SRC_ADDR_MASK_MATCH(_name, _addr_array, ...)		\
+	struct npf_test_eth_addr _name = {				\
+		.addresses = (_addr_array),				\
+		.nb_addresses = ARRAY_SIZE(_addr_array),		\
+		.mask.addr = { __VA_ARGS__ },				\
+		.test.fn = npf_eth_src_addr_match,			\
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,			\
+			   (.test.name = "eth src mask",		\
+			    .test.type = NPF_TEST_TYPE_ETH_SRC_ADDR_MASK_MATCH,)) \
 	}
 
 /**
@@ -507,12 +586,15 @@ extern npf_test_fn_t npf_eth_dst_addr_unmatch;
  * @param _addr_array Array of <tt>struct net_eth_addr</tt> items to test against
  * @param ... up to 6 mask bytes
  */
-#define NPF_ETH_DST_ADDR_MASK_MATCH(_name, _addr_array, ...) \
-	struct npf_test_eth_addr _name = { \
-		.addresses = (_addr_array), \
-		.nb_addresses = ARRAY_SIZE(_addr_array), \
-		.mask.addr = { __VA_ARGS__ }, \
-		.test.fn = npf_eth_dst_addr_match, \
+#define NPF_ETH_DST_ADDR_MASK_MATCH(_name, _addr_array, ...)		\
+	struct npf_test_eth_addr _name = {				\
+		.addresses = (_addr_array),				\
+		.nb_addresses = ARRAY_SIZE(_addr_array),		\
+		.mask.addr = { __VA_ARGS__ },				\
+		.test.fn = npf_eth_dst_addr_match,			\
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,			\
+			   (.test.name = "eth dst mask",		\
+			    .test.type = NPF_TEST_TYPE_ETH_DST_ADDR_MASK_MATCH,)) \
 	}
 
 /** @cond INTERNAL_HIDDEN */
@@ -524,6 +606,8 @@ struct npf_test_eth_type {
 
 extern npf_test_fn_t npf_eth_type_match;
 extern npf_test_fn_t npf_eth_type_unmatch;
+extern npf_test_fn_t npf_eth_vlan_type_match;
+extern npf_test_fn_t npf_eth_vlan_type_unmatch;
 
 /** @endcond */
 
@@ -533,10 +617,13 @@ extern npf_test_fn_t npf_eth_type_unmatch;
  * @param _name Name of the condition
  * @param _type Ethernet type to match
  */
-#define NPF_ETH_TYPE_MATCH(_name, _type) \
-	struct npf_test_eth_type _name = { \
-		.type = htons(_type), \
-		.test.fn = npf_eth_type_match, \
+#define NPF_ETH_TYPE_MATCH(_name, _type)				\
+	struct npf_test_eth_type _name = {				\
+		.type = htons(_type),					\
+		.test.fn = npf_eth_type_match,				\
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,			\
+			   (.test.name = "eth type",			\
+			    .test.type = NPF_TEST_TYPE_ETH_TYPE_MATCH,)) \
 	}
 
 /**
@@ -545,12 +632,83 @@ extern npf_test_fn_t npf_eth_type_unmatch;
  * @param _name Name of the condition
  * @param _type Ethernet type to exclude
  */
-#define NPF_ETH_TYPE_UNMATCH(_name, _type) \
-	struct npf_test_eth_type _name = { \
-		.type = htons(_type), \
-		.test.fn = npf_eth_type_unmatch, \
+#define NPF_ETH_TYPE_UNMATCH(_name, _type)				\
+	struct npf_test_eth_type _name = {				\
+		.type = htons(_type),					\
+		.test.fn = npf_eth_type_unmatch,			\
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,			\
+			   (.test.name = "!eth type",			\
+			    .test.type = NPF_TEST_TYPE_ETH_TYPE_UNMATCH,)) \
+	}
+
+/**
+ * @brief Statically define an "Ethernet VLAN header type match" packet
+ *        filter condition.
+ *
+ * @param _name Name of the condition
+ * @param _type Ethernet VLAN header type to match
+ */
+#define NPF_ETH_VLAN_TYPE_MATCH(_name, _type)				\
+	struct npf_test_eth_type _name = {				\
+		.type = htons(_type),					\
+		.test.fn = npf_eth_vlan_type_match,			\
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,			\
+			   (.test.name = "eth vlan type",		\
+			    .test.type = NPF_TEST_TYPE_ETH_VLAN_TYPE_MATCH,)) \
+	}
+
+/**
+ * @brief Statically define an "Ethernet VLAN header type unmatch" packet
+ *        filter condition.
+ *
+ * @param _name Name of the condition
+ * @param _type Ethernet VLAN header type to exclude
+ */
+#define NPF_ETH_VLAN_TYPE_UNMATCH(_name, _type)				\
+	struct npf_test_eth_type _name = {				\
+		.type = htons(_type),					\
+		.test.fn = npf_eth_vlan_type_unmatch,			\
+		IF_ENABLED(NPF_TEST_ENABLE_NAME,			\
+			   (.test.name = "!eth vlan type",		\
+			    .test.type = NPF_TEST_TYPE_ETH_VLAN_TYPE_UNMATCH,)) \
 	}
 
+/** Type of the packet filter rule. */
+enum npf_rule_type {
+	NPF_RULE_TYPE_UNKNOWN = 0,   /**< Unknown rule type */
+	NPF_RULE_TYPE_SEND,          /**< Rule for outgoing packets */
+	NPF_RULE_TYPE_RECV,          /**< Rule for incoming packets */
+	NPF_RULE_TYPE_LOCAL_IN_RECV, /**< Rule for local incoming packets */
+	NPF_RULE_TYPE_IPV4_RECV,     /**< Rule for IPv4 incoming packets */
+	NPF_RULE_TYPE_IPV6_RECV,     /**< Rule for IPv6 incoming packets */
+};
+
+/**
+ * @typedef npf_rule_cb_t
+ * @brief Callback used while iterating over network packet filter rules.
+ *
+ * @param rule Pointer to current network packet filter rule
+ * @param type Type of the rule (rx, tx, local_in, IPv4 or IPv6)
+ * @param user_data A valid pointer to user data or NULL
+ */
+typedef void (*npf_rule_cb_t)(struct npf_rule *rule,
+			      enum npf_rule_type type,
+			      void *user_data);
+
+/**
+ * @brief Go through all the network packet filter rules and call callback
+ * for each of them.
+ *
+ * @param cb User-supplied callback function to call
+ * @param user_data User specified data
+ */
+void npf_rules_foreach(npf_rule_cb_t cb, void *user_data);
+
+/** @cond INTERNAL_HIDDEN */
+const char *npf_test_get_str(struct npf_test *test, char *buf,
+			     size_t len);
+/** @endcond */
+
 /** @} */
 
 #ifdef __cplusplus
diff --git a/include/zephyr/net/net_stats.h b/include/zephyr/net/net_stats.h
index 5b28d9941ab..588121f5be1 100644
--- a/include/zephyr/net/net_stats.h
+++ b/include/zephyr/net/net_stats.h
@@ -328,6 +328,8 @@ struct net_stats_tc {
 #endif
 		/** Number of packets sent for this traffic class */
 		net_stats_t pkts;
+		/** Number of packets dropped for this traffic class */
+		net_stats_t dropped;
 		/** Number of bytes sent for this traffic class */
 		net_stats_t bytes;
 		/** Priority of this traffic class */
@@ -345,6 +347,8 @@ struct net_stats_tc {
 #endif
 		/** Number of packets received for this traffic class */
 		net_stats_t pkts;
+		/** Number of packets dropped for this traffic class */
+		net_stats_t dropped;
 		/** Number of bytes received for this traffic class */
 		net_stats_t bytes;
 		/** Priority of this traffic class */
@@ -367,6 +371,34 @@ struct net_stats_pm {
 	uint32_t start_time;
 };
 
+/**
+ * @brief Network packet filter statistics
+ */
+struct net_stats_pkt_filter {
+	/** Network packet filter RX statistics */
+	struct {
+		/** Network packets dropped at network interface level */
+		net_stats_t drop;
+#if defined(CONFIG_NET_PKT_FILTER_IPV4_HOOK)
+		/** IPv4 packets dropped at network interface level */
+		net_stats_t ipv4_drop;
+#endif
+#if defined(CONFIG_NET_PKT_FILTER_IPV6_HOOK)
+		/** IPv6 packets dropped at network interface level */
+		net_stats_t ipv6_drop;
+#endif
+#if defined(CONFIG_NET_PKT_FILTER_LOCAL_IN_HOOK)
+		/** Packets dropped at connection input */
+		net_stats_t local_drop;
+#endif
+	} rx;
+
+	/** Network packet filter TX statistics */
+	struct {
+		/** Network packets dropped at network interface level */
+		net_stats_t drop;
+	} tx;
+};
 
 /**
  * @brief All network statistics in one struct.
@@ -384,6 +416,10 @@ struct net_stats {
 	/** IP layer errors */
 	struct net_stats_ip_errors ip_errors;
 
+#if defined(CONFIG_NET_STATISTICS_PKT_FILTER)
+	struct net_stats_pkt_filter pkt_filter;
+#endif
+
 #if defined(CONFIG_NET_STATISTICS_IPV6)
 	/** IPv6 statistics */
 	struct net_stats_ip ipv6;
@@ -705,6 +741,7 @@ struct net_stats_wifi {
 enum net_request_stats_cmd {
 	NET_REQUEST_STATS_CMD_GET_ALL = 1,
 	NET_REQUEST_STATS_CMD_GET_PROCESSING_ERROR,
+	NET_REQUEST_STATS_CMD_GET_PKT_FILTER_DROP,
 	NET_REQUEST_STATS_CMD_GET_BYTES,
 	NET_REQUEST_STATS_CMD_GET_IP_ERRORS,
 	NET_REQUEST_STATS_CMD_GET_IPV4,
@@ -720,6 +757,7 @@ enum net_request_stats_cmd {
 	NET_REQUEST_STATS_CMD_GET_PM,
 	NET_REQUEST_STATS_CMD_GET_WIFI,
 	NET_REQUEST_STATS_CMD_RESET_WIFI,
+	NET_REQUEST_STATS_CMD_GET_VPN,
 };
 
 /** @endcond */
@@ -732,6 +770,10 @@ enum net_request_stats_cmd {
 #define NET_REQUEST_STATS_GET_PROCESSING_ERROR				\
 	(_NET_STATS_BASE | NET_REQUEST_STATS_CMD_GET_PROCESSING_ERROR)
 
+/** Request all pkt_filter drop statistics */
+#define NET_REQUEST_STATS_GET_PKT_FILTER_DROP			\
+	(_NET_STATS_BASE | NET_REQUEST_STATS_CMD_GET_PKT_FILTER_DROP)
+
 /** Request number of received and sent bytes */
 #define NET_REQUEST_STATS_GET_BYTES				\
 	(_NET_STATS_BASE | NET_REQUEST_STATS_CMD_GET_BYTES)
@@ -747,6 +789,10 @@ NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_STATS_GET_PROCESSING_ERROR);
 NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_STATS_GET_BYTES);
 NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_STATS_GET_IP_ERRORS);
 
+#if defined(CONFIG_NET_STATISTICS_PKT_FILTER)
+NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_STATS_GET_PKT_FILTER_DROP);
+#endif /* CONFIG_NET_STATISTICS_PKT_FILTER */
+
 /** @endcond */
 
 #if defined(CONFIG_NET_STATISTICS_IPV4)
@@ -849,6 +895,16 @@ NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_STATS_GET_PPP);
 /** @endcond */
 #endif /* CONFIG_NET_STATISTICS_PPP */
 
+#if defined(CONFIG_NET_STATISTICS_VPN)
+/** Request VPN statistics */
+#define NET_REQUEST_STATS_GET_VPN				\
+	(_NET_STATS_BASE | NET_REQUEST_STATS_CMD_GET_VPN)
+
+/** @cond INTERNAL_HIDDEN */
+NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_STATS_GET_VPN);
+/** @endcond */
+#endif /* CONFIG_NET_STATISTICS_VPN */
+
 #endif /* CONFIG_NET_STATISTICS_USER_API */
 
 #if defined(CONFIG_NET_STATISTICS_POWER_MANAGEMENT)
@@ -1358,6 +1414,55 @@ NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_STATS_RESET_WIFI);
 #define NET_STATS_PROMETHEUS_RX_TIME(iface, dev_id, sfx)
 #endif
 
+#define NET_STATS_PROMETHEUS_PKT_FILTER_IPV4(iface, dev_id, sfx)	\
+	NET_STATS_PROMETHEUS_COUNTER_DEFINE(				\
+		"Packet filter RX IPv4 drop",				\
+		NET_STATS_GET_INSTANCE(dev_id, sfx, pkt_filter_rx_ipv4_drop), \
+		"packet_count",						\
+		NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx),		\
+		NET_STATS_GET_VAR(dev_id, sfx, pkt_filter_rx_ipv4_drop),\
+		&(iface)->stats.pkt_filter.rx.ipv4_drop);
+
+#define NET_STATS_PROMETHEUS_PKT_FILTER_IPV6(iface, dev_id, sfx)	\
+	NET_STATS_PROMETHEUS_COUNTER_DEFINE(				\
+		"Packet filter RX IPv6 drop",				\
+		NET_STATS_GET_INSTANCE(dev_id, sfx, pkt_filter_rx_ipv6_drop), \
+		"packet_count",						\
+		NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx),		\
+		NET_STATS_GET_VAR(dev_id, sfx, pkt_filter_rx_ipv6_drop),\
+		&(iface)->stats.pkt_filter.rx.ipv6_drop);
+
+#define NET_STATS_PROMETHEUS_PKT_FILTER_LOCAL(iface, dev_id, sfx)	\
+	NET_STATS_PROMETHEUS_COUNTER_DEFINE(				\
+		"Packet filter RX local drop",				\
+		NET_STATS_GET_INSTANCE(dev_id, sfx, pkt_filter_rx_local_drop), \
+		"packet_count",						\
+		NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx),		\
+		NET_STATS_GET_VAR(dev_id, sfx, pkt_filter_rx_local_drop),\
+		&(iface)->stats.pkt_filter.rx.local_drop);
+
+#define NET_STATS_PROMETHEUS_PKT_FILTER(iface, dev_id, sfx)		\
+	NET_STATS_PROMETHEUS_COUNTER_DEFINE(				\
+		"Packet filter RX drop",				\
+		NET_STATS_GET_INSTANCE(dev_id, sfx, pkt_filter_rx_drop),\
+		"packet_count",						\
+		NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx),		\
+		NET_STATS_GET_VAR(dev_id, sfx, pkt_filter_rx_drop),	\
+		&(iface)->stats.pkt_filter.rx.drop);			\
+	NET_STATS_PROMETHEUS_COUNTER_DEFINE(				\
+		"Packet filter TX drop",				\
+		NET_STATS_GET_INSTANCE(dev_id, sfx, pkt_filter_tx_drop),\
+		"packet_count",						\
+		NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx),		\
+		NET_STATS_GET_VAR(dev_id, sfx, pkt_filter_tx_drop),	\
+		&(iface)->stats.pkt_filter.tx.drop);			\
+	IF_ENABLED(CONFIG_NET_PKT_FILTER_IPV4_HOOK,			\
+		   (NET_STATS_PROMETHEUS_PKT_FILTER_IPV4(iface, dev_id, sfx))) \
+	IF_ENABLED(CONFIG_NET_PKT_FILTER_IPV6_HOOK,			\
+		   (NET_STATS_PROMETHEUS_PKT_FILTER_IPV6(iface, dev_id, sfx))) \
+	IF_ENABLED(CONFIG_NET_PKT_FILTER_LOCAL_IN_HOOK,			\
+		   (NET_STATS_PROMETHEUS_PKT_FILTER_LOCAL(iface, dev_id, sfx)))
+
 /* Per network interface statistics via Prometheus */
 #define NET_STATS_PROMETHEUS(iface, dev_id, sfx)			\
 	NET_STATS_PROMETHEUS_COUNTER_DEFINE(				\
@@ -1367,6 +1472,8 @@ NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_STATS_RESET_WIFI);
 		NET_STATS_GET_COLLECTOR_NAME(dev_id, sfx),		\
 		NET_STATS_GET_VAR(dev_id, sfx, processing_error),	\
 		&(iface)->stats.processing_error);			\
+	IF_ENABLED(CONFIG_NET_STATISTICS_PKT_FILTER,			\
+		   (NET_STATS_PROMETHEUS_PKT_FILTER(iface, dev_id, sfx))) \
 	/* IP layer error statistics */					\
 	NET_STATS_PROMETHEUS_COUNTER_DEFINE(				\
 		"IP proto error",					\
diff --git a/include/zephyr/net/phy.h b/include/zephyr/net/phy.h
index 0cffda13b0d..24201d915de 100644
--- a/include/zephyr/net/phy.h
+++ b/include/zephyr/net/phy.h
@@ -7,6 +7,7 @@
 /*
  * Copyright (c) 2021 IP-Logix Inc.
  * Copyright 2022 NXP
+ * Copyright (c) 2025 Aerlync Labs Inc.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -23,6 +24,7 @@
  */
 #include <zephyr/types.h>
 #include <zephyr/device.h>
+#include <errno.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -31,21 +33,21 @@ extern "C" {
 /** @brief Ethernet link speeds. */
 enum phy_link_speed {
 	/** 10Base-T Half-Duplex */
-	LINK_HALF_10BASE_T		= BIT(0),
+	LINK_HALF_10BASE_T = BIT(0),
 	/** 10Base-T Full-Duplex */
-	LINK_FULL_10BASE_T		= BIT(1),
+	LINK_FULL_10BASE_T = BIT(1),
 	/** 100Base-T Half-Duplex */
-	LINK_HALF_100BASE_T		= BIT(2),
+	LINK_HALF_100BASE_T = BIT(2),
 	/** 100Base-T Full-Duplex */
-	LINK_FULL_100BASE_T		= BIT(3),
+	LINK_FULL_100BASE_T = BIT(3),
 	/** 1000Base-T Half-Duplex */
-	LINK_HALF_1000BASE_T		= BIT(4),
+	LINK_HALF_1000BASE_T = BIT(4),
 	/** 1000Base-T Full-Duplex */
-	LINK_FULL_1000BASE_T		= BIT(5),
+	LINK_FULL_1000BASE_T = BIT(5),
 	/** 2.5GBase-T Full-Duplex */
-	LINK_FULL_2500BASE_T		= BIT(6),
+	LINK_FULL_2500BASE_T = BIT(6),
 	/** 5GBase-T Full-Duplex */
-	LINK_FULL_5000BASE_T		= BIT(7),
+	LINK_FULL_5000BASE_T = BIT(7),
 };
 
 /**
@@ -55,7 +57,7 @@ enum phy_link_speed {
  *
  * @return True if link is full duplex, false if not.
  */
-#define PHY_LINK_IS_FULL_DUPLEX(x)	(x & (BIT(1) | BIT(3) | BIT(5) | BIT(6) | BIT(7)))
+#define PHY_LINK_IS_FULL_DUPLEX(x) (x & (BIT(1) | BIT(3) | BIT(5) | BIT(6) | BIT(7)))
 
 /**
  * @brief Check if phy link speed is 1 Gbit/sec.
@@ -64,7 +66,7 @@ enum phy_link_speed {
  *
  * @return True if link is 1 Gbit/sec, false if not.
  */
-#define PHY_LINK_IS_SPEED_1000M(x)	(x & (BIT(4) | BIT(5)))
+#define PHY_LINK_IS_SPEED_1000M(x) (x & (BIT(4) | BIT(5)))
 
 /**
  * @brief Check if phy link speed is 100 Mbit/sec.
@@ -73,7 +75,7 @@ enum phy_link_speed {
  *
  * @return True if link is 1 Mbit/sec, false if not.
  */
-#define PHY_LINK_IS_SPEED_100M(x)	(x & (BIT(2) | BIT(3)))
+#define PHY_LINK_IS_SPEED_100M(x) (x & (BIT(2) | BIT(3)))
 
 /** @brief Link state */
 struct phy_link_state {
@@ -83,6 +85,63 @@ struct phy_link_state {
 	bool is_up;
 };
 
+/** @brief PLCA (Physical Layer Collision Avoidance) Reconciliation Sublayer configurations */
+struct phy_plca_cfg {
+	/** PLCA register map version */
+	uint8_t version;
+	/** PLCA configured mode (enable/disable) */
+	bool enable;
+	/** PLCA local node identifier */
+	uint8_t node_id;
+	/** PLCA node count */
+	uint8_t node_count;
+	/** Additional frames a node is allowed to send in single transmit opportunity (TO) */
+	uint8_t burst_count;
+	/** Wait time for the MAC to send a new frame before interrupting the burst */
+	uint8_t burst_timer;
+	/** PLCA to_timer in bit-times, which determines the PLCA transmit opportunity */
+	uint8_t to_timer;
+};
+
+/**
+ * @brief      Write PHY PLCA configuration
+ *
+ * This routine provides a generic interface to configure PHY PLCA settings.
+ *
+ * @param[in]  dev       PHY device structure
+ * @param[in]  plca_cfg  Pointer to plca configuration structure
+ *
+ * @retval 0 If successful.
+ * @retval -EIO If communication with PHY failed.
+ */
+int genphy_get_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg);
+
+/**
+ * @brief      Read PHY PLCA configuration
+ *
+ * This routine provides a generic interface to get PHY PLCA settings.
+ *
+ * @param[in]  dev       PHY device structure
+ * @param      plca_cfg  Pointer to plca configuration structure
+ *
+ * @retval 0 If successful.
+ * @retval -EIO If communication with PHY failed.
+ */
+int genphy_set_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg);
+
+/**
+ * @brief      Read PHY PLCA status
+ *
+ * This routine provides a generic interface to get PHY PLCA status.
+ *
+ * @param[in]  dev          PHY device structure
+ * @param      plca_status  Pointer to plca status
+ *
+ * @retval 0 If successful.
+ * @retval -EIO If communication with PHY failed.
+ */
+int genphy_get_plca_sts(const struct device *dev, bool *plca_status);
+
 /**
  * @typedef phy_callback_t
  * @brief Define the callback function signature for
@@ -92,8 +151,7 @@ struct phy_link_state {
  * @param state     Pointer to link_state structure.
  * @param user_data Pointer to data specified by user
  */
-typedef void (*phy_callback_t)(const struct device *dev,
-			       struct phy_link_state *state,
+typedef void (*phy_callback_t)(const struct device *dev, struct phy_link_state *state,
 			       void *user_data);
 
 /**
@@ -104,24 +162,36 @@ typedef void (*phy_callback_t)(const struct device *dev,
  */
 __subsystem struct ethphy_driver_api {
 	/** Get link state */
-	int (*get_link)(const struct device *dev,
-			struct phy_link_state *state);
+	int (*get_link)(const struct device *dev, struct phy_link_state *state);
 
 	/** Configure link */
-	int (*cfg_link)(const struct device *dev,
-			enum phy_link_speed adv_speeds);
+	int (*cfg_link)(const struct device *dev, enum phy_link_speed adv_speeds);
 
-	/** Set callback to be invoked when link state changes. */
-	int (*link_cb_set)(const struct device *dev, phy_callback_t cb,
-			   void *user_data);
+	/** Set callback to be invoked when link state changes. Driver has to invoke
+	 * callback once after setting it, even if link state has not changed.
+	 */
+	int (*link_cb_set)(const struct device *dev, phy_callback_t cb, void *user_data);
 
 	/** Read PHY register */
-	int (*read)(const struct device *dev, uint16_t reg_addr,
-		    uint32_t *data);
+	int (*read)(const struct device *dev, uint16_t reg_addr, uint32_t *data);
 
 	/** Write PHY register */
-	int (*write)(const struct device *dev, uint16_t reg_addr,
-		     uint32_t data);
+	int (*write)(const struct device *dev, uint16_t reg_addr, uint32_t data);
+
+	/** Read PHY C45 register */
+	int (*read_c45)(const struct device *dev, uint8_t devad, uint16_t regad, uint16_t *data);
+
+	/** Write PHY C45 register */
+	int (*write_c45)(const struct device *dev, uint8_t devad, uint16_t regad, uint16_t data);
+
+	/* Set PLCA settings */
+	int (*set_plca_cfg)(const struct device *dev, struct phy_plca_cfg *plca_cfg);
+
+	/* Get PLCA settings */
+	int (*get_plca_cfg)(const struct device *dev, struct phy_plca_cfg *plca_cfg);
+
+	/* Get PLCA status */
+	int (*get_plca_sts)(const struct device *dev, bool *plca_sts);
 };
 /**
  * @endcond
@@ -139,11 +209,13 @@ __subsystem struct ethphy_driver_api {
  * @retval -EIO If communication with PHY failed.
  * @retval -ENOTSUP If not supported.
  */
-static inline int phy_configure_link(const struct device *dev,
-				     enum phy_link_speed speeds)
+static inline int phy_configure_link(const struct device *dev, enum phy_link_speed speeds)
 {
-	const struct ethphy_driver_api *api =
-		(const struct ethphy_driver_api *)dev->api;
+	const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
+
+	if (api->cfg_link == NULL) {
+		return -ENOSYS;
+	}
 
 	return api->cfg_link(dev, speeds);
 }
@@ -161,11 +233,13 @@ static inline int phy_configure_link(const struct device *dev,
  * @retval 0 If successful.
  * @retval -EIO If communication with PHY failed.
  */
-static inline int phy_get_link_state(const struct device *dev,
-				     struct phy_link_state *state)
+static inline int phy_get_link_state(const struct device *dev, struct phy_link_state *state)
 {
-	const struct ethphy_driver_api *api =
-		(const struct ethphy_driver_api *)dev->api;
+	const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
+
+	if (api->get_link == NULL) {
+		return -ENOSYS;
+	}
 
 	return api->get_link(dev, state);
 }
@@ -175,7 +249,11 @@ static inline int phy_get_link_state(const struct device *dev,
  *
  * Sets a callback that is invoked when link state changes. This is the
  * preferred method for ethernet drivers to be notified of the PHY link
- * state change.
+ * state change. The callback will be invoked once after setting it,
+ * even if link state has not changed. There can only one callback
+ * function set and active at a time. This function is mainly used
+ * by ethernet drivers to register a callback to be notified of
+ * link state changes and should therefore not be used by applications.
  *
  * @param[in]  dev        PHY device structure
  * @param      callback   Callback handler
@@ -184,12 +262,14 @@ static inline int phy_get_link_state(const struct device *dev,
  * @retval 0 If successful.
  * @retval -ENOTSUP If not supported.
  */
-static inline int phy_link_callback_set(const struct device *dev,
-					phy_callback_t callback,
+static inline int phy_link_callback_set(const struct device *dev, phy_callback_t callback,
 					void *user_data)
 {
-	const struct ethphy_driver_api *api =
-		(const struct ethphy_driver_api *)dev->api;
+	const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
+
+	if (api->link_cb_set == NULL) {
+		return -ENOSYS;
+	}
 
 	return api->link_cb_set(dev, callback, user_data);
 }
@@ -206,11 +286,13 @@ static inline int phy_link_callback_set(const struct device *dev,
  * @retval 0 If successful.
  * @retval -EIO If communication with PHY failed.
  */
-static inline int phy_read(const struct device *dev, uint16_t reg_addr,
-			   uint32_t *value)
+static inline int phy_read(const struct device *dev, uint16_t reg_addr, uint32_t *value)
 {
-	const struct ethphy_driver_api *api =
-		(const struct ethphy_driver_api *)dev->api;
+	const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
+
+	if (api->read == NULL) {
+		return -ENOSYS;
+	}
 
 	return api->read(dev, reg_addr, value);
 }
@@ -227,15 +309,132 @@ static inline int phy_read(const struct device *dev, uint16_t reg_addr,
  * @retval 0 If successful.
  * @retval -EIO If communication with PHY failed.
  */
-static inline int phy_write(const struct device *dev, uint16_t reg_addr,
-			    uint32_t value)
+static inline int phy_write(const struct device *dev, uint16_t reg_addr, uint32_t value)
 {
-	const struct ethphy_driver_api *api =
-		(const struct ethphy_driver_api *)dev->api;
+	const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
+
+	if (api->write == NULL) {
+		return -ENOSYS;
+	}
 
 	return api->write(dev, reg_addr, value);
 }
 
+/**
+ * @brief      Read PHY C45 register
+ *
+ * This routine provides a generic interface to read to a PHY C45 register.
+ *
+ * @param[in]  dev       PHY device structure
+ * @param[in]  devad       Device address
+ * @param[in]  regad       Register address
+ * @param      data        Pointer to receive read data
+ *
+ * @retval 0 If successful.
+ * @retval -EIO If communication with PHY failed.
+ */
+static inline int phy_read_c45(const struct device *dev, uint8_t devad, uint16_t regad,
+			       uint16_t *data)
+{
+	const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
+
+	if (api->read_c45 == NULL) {
+		return -ENOSYS;
+	}
+
+	return api->read_c45(dev, devad, regad, data);
+}
+
+/**
+ * @brief      Write PHY C45 register
+ *
+ * This routine provides a generic interface to write to a PHY C45 register.
+ *
+ * @param[in]  dev       PHY device structure
+ * @param[in]  devad       Device address
+ * @param[in]  regad       Register address
+ * @param[in]  data        Data to write
+ *
+ * @retval 0 If successful.
+ * @retval -EIO If communication with PHY failed.
+ */
+static inline int phy_write_c45(const struct device *dev, uint8_t devad, uint16_t regad,
+				uint16_t data)
+{
+	const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
+
+	if (api->write_c45 == NULL) {
+		return -ENOSYS;
+	}
+
+	return api->write_c45(dev, devad, regad, data);
+}
+
+/**
+ * @brief      Write PHY PLCA configuration
+ *
+ * This routine provides a generic interface to configure PHY PLCA settings.
+ *
+ * @param[in]  dev       PHY device structure
+ * @param[in]  plca_cfg  Pointer to plca configuration structure
+ *
+ * @retval 0 If successful.
+ * @retval -EIO If communication with PHY failed.
+ */
+static inline int phy_set_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg)
+{
+	const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
+
+	if (api->set_plca_cfg == NULL) {
+		return -ENOSYS;
+	}
+
+	return api->set_plca_cfg(dev, plca_cfg);
+}
+
+/**
+ * @brief      Read PHY PLCA configuration
+ *
+ * This routine provides a generic interface to get PHY PLCA settings.
+ *
+ * @param[in]  dev       PHY device structure
+ * @param      plca_cfg  Pointer to plca configuration structure
+ *
+ * @retval 0 If successful.
+ * @retval -EIO If communication with PHY failed.
+ */
+static inline int phy_get_plca_cfg(const struct device *dev, struct phy_plca_cfg *plca_cfg)
+{
+	const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
+
+	if (api->get_plca_cfg == NULL) {
+		return -ENOSYS;
+	}
+
+	return api->get_plca_cfg(dev, plca_cfg);
+}
+
+/**
+ * @brief      Read PHY PLCA status
+ *
+ * This routine provides a generic interface to get PHY PLCA status.
+ *
+ * @param[in]  dev          PHY device structure
+ * @param      plca_status  Pointer to plca status
+ *
+ * @retval 0 If successful.
+ * @retval -EIO If communication with PHY failed.
+ */
+static inline int phy_get_plca_sts(const struct device *dev, bool *plca_status)
+{
+	const struct ethphy_driver_api *api = (const struct ethphy_driver_api *)dev->api;
+
+	if (api->get_plca_sts == NULL) {
+		return -ENOSYS;
+	}
+
+	return api->get_plca_sts(dev, plca_status);
+}
 
 #ifdef __cplusplus
 }
diff --git a/include/zephyr/net/sntp.h b/include/zephyr/net/sntp.h
index 66128f76b46..6b4f1456db3 100644
--- a/include/zephyr/net/sntp.h
+++ b/include/zephyr/net/sntp.h
@@ -14,6 +14,7 @@
 #define ZEPHYR_INCLUDE_NET_SNTP_H_
 
 #include <zephyr/net/socket.h>
+#include <zephyr/net/socket_service.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -99,6 +100,51 @@ int sntp_recv_response(struct sntp_ctx *ctx, uint32_t timeout, struct sntp_time
  */
 void sntp_close(struct sntp_ctx *ctx);
 
+/**
+ * @brief Initialise SNTP context for async operation
+ *
+ * Asynchronous operation is powered by @kconfig{CONFIG_NET_SOCKETS_SERVICE}.
+ *
+ * @param ctx Address of sntp context.
+ * @param addr IP address of NTP/SNTP server.
+ * @param addr_len IP address length of NTP/SNTP server.
+ * @param service Socket service defined by @ref NET_SOCKET_SERVICE_SYNC_DEFINE
+ *
+ * @return 0 if ok, <0 if error.
+ */
+int sntp_init_async(struct sntp_ctx *ctx, struct sockaddr *addr, socklen_t addr_len,
+		    const struct net_socket_service_desc *service);
+
+/**
+ * @brief Send the SNTP query
+ *
+ * @param ctx Address of sntp context.
+ *
+ * @return 0 if ok, <0 if error.
+ */
+int sntp_send_async(struct sntp_ctx *ctx);
+
+/**
+ * @brief Read the result of the SNTP query
+ *
+ * Must be called from the callback attached to the @ref net_socket_service_desc
+ * context.
+ *
+ * @param event Event pointer extracted from the service work callback
+ * @param ts Timestamp including integer and fractional seconds since
+ * 1 Jan 1970 (output).
+ *
+ * @return 0 if ok, <0 if error
+ */
+int sntp_read_async(struct net_socket_service_event *event, struct sntp_time *ts);
+
+/**
+ * @brief Release SNTP context
+ *
+ * @param service Socket service defined by @ref NET_SOCKET_SERVICE_SYNC_DEFINE
+ */
+void sntp_close_async(const struct net_socket_service_desc *service);
+
 /**
  * @brief Convenience function to query SNTP in one-shot fashion
  *
diff --git a/include/zephyr/net/socket.h b/include/zephyr/net/socket.h
index fd99b8daf28..273b2bfabaf 100644
--- a/include/zephyr/net/socket.h
+++ b/include/zephyr/net/socket.h
@@ -8,6 +8,7 @@
 /*
  * Copyright (c) 2017-2018 Linaro Limited
  * Copyright (c) 2021 Nordic Semiconductor
+ * Copyright (c) 2025 Aerlync Labs Inc.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -965,6 +966,8 @@ struct in_pktinfo {
 #define IP_MULTICAST_IF 32
 /** Set IPv4 multicast TTL value. */
 #define IP_MULTICAST_TTL 33
+/** Set IPv4 multicast loop value. */
+#define IP_MULTICAST_LOOP 34
 /** Join IPv4 multicast group. */
 #define IP_ADD_MEMBERSHIP 35
 /** Leave IPv4 multicast group. */
@@ -1006,6 +1009,9 @@ struct ip_mreq  {
 /** Set the multicast hop limit for the socket. */
 #define IPV6_MULTICAST_HOPS 18
 
+/** Set the multicast loop bit for the socket. */
+#define IPV6_MULTICAST_LOOP 19
+
 /** Join IPv6 multicast group. */
 #define IPV6_ADD_MEMBERSHIP 20
 
diff --git a/include/zephyr/net/virtual.h b/include/zephyr/net/virtual.h
index d229a214d23..d956ff1a4b9 100644
--- a/include/zephyr/net/virtual.h
+++ b/include/zephyr/net/virtual.h
@@ -46,6 +46,9 @@ enum virtual_interface_caps {
 	/** Virtual Ethernet bridge interface. */
 	VIRTUAL_INTERFACE_BRIDGE = BIT(3),
 
+	/** VPN interface */
+	VIRTUAL_INTERFACE_VPN = BIT(4),
+
 /** @cond INTERNAL_HIDDEN */
 	/* Marker for capabilities - must be at the end of the enum.
 	 * It is here because the capability list cannot be empty.
@@ -60,6 +63,8 @@ enum virtual_interface_config_type {
 	VIRTUAL_INTERFACE_CONFIG_TYPE_PEER_ADDRESS,
 	VIRTUAL_INTERFACE_CONFIG_TYPE_MTU,
 	VIRTUAL_INTERFACE_CONFIG_TYPE_LINK_TYPE,
+	VIRTUAL_INTERFACE_CONFIG_TYPE_PRIVATE_KEY,
+	VIRTUAL_INTERFACE_CONFIG_TYPE_PUBLIC_KEY,
 };
 
 struct virtual_interface_link_types {
@@ -69,6 +74,10 @@ struct virtual_interface_link_types {
 				  (1))];
 };
 
+#if !defined(NET_VIRTUAL_MAX_PUBLIC_KEY_LEN)
+#define NET_VIRTUAL_MAX_PUBLIC_KEY_LEN 32U
+#endif
+
 struct virtual_interface_config {
 	sa_family_t family;
 	union {
@@ -76,6 +85,14 @@ struct virtual_interface_config {
 		struct in6_addr peer6addr;
 		int mtu;
 		struct virtual_interface_link_types link_types;
+		struct {
+			size_t len;
+			uint8_t *data;
+		} private_key;
+		struct {
+			size_t len;
+			uint8_t data[NET_VIRTUAL_MAX_PUBLIC_KEY_LEN];
+		} public_key;
 	};
 };
 
@@ -160,7 +177,7 @@ struct virtual_interface_context {
 	bool is_init;
 
 	/** Link address for this network interface */
-	struct net_linkaddr_storage lladdr;
+	struct net_linkaddr lladdr;
 
 	/** User friendly name of this L2 layer. */
 	char name[VIRTUAL_MAX_NAME_LEN];
diff --git a/include/zephyr/net/virtual_mgmt.h b/include/zephyr/net/virtual_mgmt.h
index 04ca6ae9fd7..4b5e3163e59 100644
--- a/include/zephyr/net/virtual_mgmt.h
+++ b/include/zephyr/net/virtual_mgmt.h
@@ -46,6 +46,14 @@ struct virtual_interface_req_params {
 		struct in6_addr peer6addr;
 		int mtu;
 		struct virtual_interface_link_types link_types;
+		struct {
+			size_t len;
+			uint8_t *data;
+		} private_key;
+		struct {
+			size_t len;
+			uint8_t data[NET_VIRTUAL_MAX_PUBLIC_KEY_LEN];
+		} public_key;
 	};
 };
 
@@ -56,6 +64,8 @@ enum net_request_virtual_interface_cmd {
 	NET_REQUEST_VIRTUAL_INTERFACE_CMD_GET_MTU,
 	NET_REQUEST_VIRTUAL_INTERFACE_CMD_SET_LINK_TYPE,
 	NET_REQUEST_VIRTUAL_INTERFACE_CMD_GET_LINK_TYPE,
+	NET_REQUEST_VIRTUAL_INTERFACE_CMD_SET_PRIVATE_KEY,
+	NET_REQUEST_VIRTUAL_INTERFACE_CMD_GET_PUBLIC_KEY,
 };
 
 #define NET_REQUEST_VIRTUAL_INTERFACE_SET_PEER_ADDRESS		\
@@ -94,6 +104,18 @@ NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_GET_MTU);
 
 NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_GET_LINK_TYPE);
 
+#define NET_REQUEST_VIRTUAL_INTERFACE_SET_PRIVATE_KEY		\
+	(_NET_VIRTUAL_INTERFACE_BASE |				\
+	 NET_REQUEST_VIRTUAL_INTERFACE_CMD_SET_PRIVATE_KEY)
+
+NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_SET_PRIVATE_KEY);
+
+#define NET_REQUEST_VIRTUAL_INTERFACE_GET_PUBLIC_KEY		\
+	(_NET_VIRTUAL_INTERFACE_BASE |				\
+	 NET_REQUEST_VIRTUAL_INTERFACE_CMD_GET_PUBLIC_KEY)
+
+NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_GET_PUBLIC_KEY);
+
 struct net_if;
 
 /** @endcond */
diff --git a/include/zephyr/net/wifi.h b/include/zephyr/net/wifi.h
index dbe643c4d02..8b89ff57803 100644
--- a/include/zephyr/net/wifi.h
+++ b/include/zephyr/net/wifi.h
@@ -38,6 +38,33 @@
 extern "C" {
 #endif
 
+/** @brief Wi-Fi connect result codes. To be overlaid on top of \ref wifi_status
+ * in the connect result event for detailed status.
+ */
+enum wifi_conn_status {
+	/** Connection successful */
+	WIFI_STATUS_CONN_SUCCESS = 0,
+	/** Connection failed - generic failure */
+	WIFI_STATUS_CONN_FAIL,
+	/** Connection failed - wrong password
+	 * Few possible reasons for 4-way handshake failure that we can guess are as follows:
+	 * 1) Incorrect key
+	 * 2) EAPoL frames lost causing timeout
+	 *
+	 * #1 is the likely cause, so, we convey to the user that it is due to
+	 * Wrong passphrase/password.
+	 */
+	WIFI_STATUS_CONN_WRONG_PASSWORD,
+	/** Connection timed out */
+	WIFI_STATUS_CONN_TIMEOUT,
+	/** Connection failed - AP not found */
+	WIFI_STATUS_CONN_AP_NOT_FOUND,
+	/** Last connection status */
+	WIFI_STATUS_CONN_LAST_STATUS,
+	/** Connection disconnected status */
+	WIFI_STATUS_DISCONN_FIRST_STATUS = WIFI_STATUS_CONN_LAST_STATUS,
+};
+
 /** @brief IEEE 802.11 security types. */
 enum wifi_security_type {
 	/** No security. */
@@ -84,6 +111,8 @@ enum wifi_security_type {
 	WIFI_SECURITY_TYPE_FT_EAP,
 	/** FT-EAP-SHA384 security */
 	WIFI_SECURITY_TYPE_FT_EAP_SHA384,
+	/** SAE Extended key (uses group-dependent hashing) */
+	WIFI_SECURITY_TYPE_SAE_EXT_KEY,
 
 	/** @cond INTERNAL_HIDDEN */
 	__WIFI_SECURITY_TYPE_AFTER_LAST,
@@ -108,12 +137,26 @@ enum wifi_eap_type {
 	WIFI_EAP_TYPE_MSCHAPV2 = 26,
 };
 
-/** @brief Enterprise security WPA3 suiteb types. */
-enum wifi_suiteb_type {
-	/** suiteb. */
-	WIFI_SUITEB = 1,
-	/** suiteb-192. */
-	WIFI_SUITEB_192,
+/** @brief WPA3 Enterprise security types.
+ *
+ * See Section#3 in WFA WPA3 specification v3.4:
+ * https://www.wi-fi.org/file/wpa3-specification for details.
+ */
+enum wifi_wpa3_enterprise_type {
+	/** No WPA3 enterprise, either WPA2 Enterprise or personal mode */
+	WIFI_WPA3_ENTERPRISE_NA = 0,
+	/** WPA3 enterprise Suite-B (PMFR + WPA3-Suite-B). */
+	WIFI_WPA3_ENTERPRISE_SUITEB = 1,
+	/** WPA3 enterprise Suite-B-192 (PMFR + WPA3-Suite-B-192). */
+	WIFI_WPA3_ENTERPRISE_SUITEB_192,
+	/** WPA3 enterprise only (PMFR + WPA2-ENT disabled). */
+	WIFI_WPA3_ENTERPRISE_ONLY,
+
+	/** @cond INTERNAL_HIDDEN */
+	__WIFI_WPA3_ENTERPRISE_AFTER_LAST,
+	WIFI_WPA3_ENTERPRISE_MAX = __WIFI_WPA3_ENTERPRISE_AFTER_LAST - 1,
+	WIFI_WPA3_ENTERPRISE_UNKNOWN
+	/** @endcond */
 };
 
 enum wifi_eap_tls_cipher_type {
@@ -175,12 +218,12 @@ struct wifi_eap_cipher_config {
 
 struct wifi_eap_config {
 	/**  Security type. */
-	unsigned int type;
-	/** EPA method type of phase1. */
+	enum wifi_security_type type;
+	/** EAP method type of phase1. */
 	enum wifi_eap_type eap_type_phase1;
-	/** EPA method type of phase2. */
+	/** EAP method type of phase2. */
 	enum wifi_eap_type eap_type_phase2;
-	/** EPA method string. */
+	/** EAP method string. */
 	char *method;
 	/** Phase2 setting string. */
 	char *phase2;
@@ -189,6 +232,9 @@ struct wifi_eap_config {
 /** Helper function to get user-friendly security type name. */
 const char *wifi_security_txt(enum wifi_security_type security);
 
+/** Helper function to get user-friendly wpa3 enterprise security type name. */
+const char *wifi_wpa3_enterprise_txt(enum wifi_wpa3_enterprise_type wpa3_ent);
+
 /** @brief IEEE 802.11w - Management frame protection. */
 enum wifi_mfp_options {
 	/** MFP disabled. */
@@ -653,7 +699,6 @@ static const char * const wifi_ps_param_config_err_code_tbl[] = {
 };
 /** @endcond */
 
-#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM
 /** IEEE 802.11v BTM (BSS transition management) Query reasons.
  * Refer to IEEE Std 802.11v-2011 - Table 7-43x-Transition and Transition Query reasons table.
  */
@@ -665,7 +710,6 @@ enum wifi_btm_query_reason {
 	/** Leaving ESS. */
 	WIFI_BTM_QUERY_REASON_LEAVING_ESS = 20,
 };
-#endif
 
 /** Helper function to get user-friendly power save error code name. */
 static inline const char *wifi_ps_get_config_err_code_str(int16_t err_no)
@@ -691,6 +735,9 @@ enum wifi_ap_config_param {
 	WIFI_AP_CONFIG_PARAM_VHT_CAPAB = BIT(4),
 };
 
+/** Helper function to get user-friendly status name for the status code. */
+const char *wifi_conn_status_txt(enum wifi_conn_status status);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/zephyr/net/wifi_mgmt.h b/include/zephyr/net/wifi_mgmt.h
index 6dcafa8aee4..969a6c65ab0 100644
--- a/include/zephyr/net/wifi_mgmt.h
+++ b/include/zephyr/net/wifi_mgmt.h
@@ -111,10 +111,8 @@ enum net_request_wifi_cmd {
 	NET_REQUEST_WIFI_CMD_AP_CONFIG_PARAM,
 	/** DPP actions */
 	NET_REQUEST_WIFI_CMD_DPP,
-#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM
 	/** BSS transition management query */
 	NET_REQUEST_WIFI_CMD_BTM_QUERY,
-#endif
 	/** Flush PMKSA cache entries */
 	NET_REQUEST_WIFI_CMD_PMKSA_FLUSH,
 	/** Set enterprise mode credential */
@@ -277,12 +275,10 @@ NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_AP_CONFIG_PARAM);
 NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_DPP);
 #endif /* CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP */
 
-#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM
 /** Request a Wi-Fi BTM query */
 #define NET_REQUEST_WIFI_BTM_QUERY (_NET_WIFI_BASE | NET_REQUEST_WIFI_CMD_BTM_QUERY)
 
 NET_MGMT_DEFINE_REQUEST_HANDLER(NET_REQUEST_WIFI_BTM_QUERY);
-#endif
 
 /** Request a Wi-Fi PMKSA cache entries flush */
 #define NET_REQUEST_WIFI_PMKSA_FLUSH                           \
@@ -505,6 +501,8 @@ struct wifi_scan_result {
 	uint8_t channel;
 	/** Security type */
 	enum wifi_security_type security;
+	/** WPA3 enterprise type */
+	enum wifi_wpa3_enterprise_type wpa3_ent_type;
 	/** MFP options */
 	enum wifi_mfp_options mfp;
 	/** RSSI */
@@ -553,8 +551,8 @@ struct wifi_connect_req_params {
 	const uint8_t *key2_passwd;
 	/** key2 passwd length, max 128 */
 	uint8_t key2_passwd_length;
-	/** suiteb or suiteb-192 */
-	uint8_t suiteb_type;
+	/** wpa3 enterprise mode */
+	enum wifi_wpa3_enterprise_type wpa3_ent_mode;
 	/** TLS cipher */
 	uint8_t TLS_cipher;
 	/** eap version */
@@ -567,6 +565,8 @@ struct wifi_connect_req_params {
 	const uint8_t *eap_password;
 	/** eap passwd length, max 128 */
 	uint8_t eap_passwd_length;
+	/** Whether verify peer with CA or not: false-not verify, true-verify. */
+	bool verify_peer_cert;
 	/** Fast BSS Transition used */
 	bool ft_used;
 	/** Number of EAP users */
@@ -587,33 +587,6 @@ struct wifi_connect_req_params {
 	enum wifi_frequency_bandwidths bandwidth;
 };
 
-/** @brief Wi-Fi connect result codes. To be overlaid on top of \ref wifi_status
- * in the connect result event for detailed status.
- */
-enum wifi_conn_status {
-	/** Connection successful */
-	WIFI_STATUS_CONN_SUCCESS = 0,
-	/** Connection failed - generic failure */
-	WIFI_STATUS_CONN_FAIL,
-	/** Connection failed - wrong password
-	 * Few possible reasons for 4-way handshake failure that we can guess are as follows:
-	 * 1) Incorrect key
-	 * 2) EAPoL frames lost causing timeout
-	 *
-	 * #1 is the likely cause, so, we convey to the user that it is due to
-	 * Wrong passphrase/password.
-	 */
-	WIFI_STATUS_CONN_WRONG_PASSWORD,
-	/** Connection timed out */
-	WIFI_STATUS_CONN_TIMEOUT,
-	/** Connection failed - AP not found */
-	WIFI_STATUS_CONN_AP_NOT_FOUND,
-	/** Last connection status */
-	WIFI_STATUS_CONN_LAST_STATUS,
-	/** Connection disconnected status */
-	WIFI_STATUS_DISCONN_FIRST_STATUS = WIFI_STATUS_CONN_LAST_STATUS,
-};
-
 /** @brief Wi-Fi disconnect reason codes. To be overlaid on top of \ref wifi_status
  * in the disconnect result event for detailed reason.
  */
@@ -684,6 +657,8 @@ struct wifi_iface_status {
 	enum wifi_iface_mode iface_mode;
 	/** Link mode, see enum wifi_link_mode */
 	enum wifi_link_mode link_mode;
+	/** WPA3 enterprise type */
+	enum wifi_wpa3_enterprise_type wpa3_ent_type;
 	/** Security type, see enum wifi_security_type */
 	enum wifi_security_type security;
 	/** MFP options, see enum wifi_mfp_options */
@@ -1461,7 +1436,7 @@ struct wifi_mgmt_ops {
 	 * @return 0 if ok, < 0 if error
 	 */
 	int (*channel)(const struct device *dev, struct wifi_channel_info *channel);
-#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM
+
 	/** Send BTM query
 	 *
 	 * @param dev Pointer to the device structure for the driver instance.
@@ -1470,7 +1445,6 @@ struct wifi_mgmt_ops {
 	 * @return 0 if ok, < 0 if error
 	 */
 	int (*btm_query)(const struct device *dev, uint8_t reason);
-#endif
 	/** Judge ap whether support the capability
 	 *
 	 * @param dev Pointer to the device structure for the driver instance.
diff --git a/include/zephyr/net/zperf.h b/include/zephyr/net/zperf.h
index 4b6c50f4f61..abbdda6ee4a 100644
--- a/include/zephyr/net/zperf.h
+++ b/include/zephyr/net/zperf.h
@@ -45,6 +45,10 @@ struct zperf_upload_params {
 		uint8_t tos;
 		int tcp_nodelay;
 		int priority;
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+		int thread_priority;
+		bool wait_for_start;
+#endif
 		uint32_t report_interval_ms;
 	} options;
 };
diff --git a/include/zephyr/net_buf.h b/include/zephyr/net_buf.h
index 62f6299cd30..c4cc6a71e68 100644
--- a/include/zephyr/net_buf.h
+++ b/include/zephyr/net_buf.h
@@ -1098,6 +1098,9 @@ struct net_buf_pool {
 	/** Total size of the pool. */
 	const uint16_t pool_size;
 
+	/** Maximum count of used buffers. */
+	uint16_t max_used;
+
 	/** Name of the pool. Used when printing pool information. */
 	const char *name;
 #endif /* CONFIG_NET_BUF_POOL_USAGE */
@@ -1115,6 +1118,7 @@ struct net_buf_pool {
 /** @cond INTERNAL_HIDDEN */
 #define NET_BUF_POOL_USAGE_INIT(_pool, _count) \
 	IF_ENABLED(CONFIG_NET_BUF_POOL_USAGE, (.avail_count = ATOMIC_INIT(_count),)) \
+	IF_ENABLED(CONFIG_NET_BUF_POOL_USAGE, (.max_used = 0,)) \
 	IF_ENABLED(CONFIG_NET_BUF_POOL_USAGE, (.name = STRINGIFY(_pool),))
 
 #define NET_BUF_POOL_INITIALIZER(_pool, _alloc, _bufs, _count, _ud_size, _destroy) \
@@ -1419,29 +1423,6 @@ struct net_buf * __must_check net_buf_alloc_with_data(struct net_buf_pool *pool,
 						      k_timeout_t timeout);
 #endif
 
-/**
- * @brief Get a buffer from a FIFO.
- *
- * @deprecated Use @a k_fifo_get() instead.
- *
- * @param fifo Which FIFO to take the buffer from.
- * @param timeout Affects the action taken should the FIFO be empty.
- *        If K_NO_WAIT, then return immediately. If K_FOREVER, then wait as
- *        long as necessary. Otherwise, wait until the specified timeout.
- *
- * @return New buffer or NULL if the FIFO is empty.
- */
-#if defined(CONFIG_NET_BUF_LOG)
-__deprecated struct net_buf * __must_check net_buf_get_debug(struct k_fifo *fifo,
-							     k_timeout_t timeout,
-							     const char *func, int line);
-#define	net_buf_get(_fifo, _timeout) \
-	net_buf_get_debug(_fifo, _timeout, __func__, __LINE__)
-#else
-__deprecated struct net_buf * __must_check net_buf_get(struct k_fifo *fifo,
-						       k_timeout_t timeout);
-#endif
-
 /**
  * @brief Destroy buffer from custom destroy callback
  *
@@ -1501,16 +1482,6 @@ void net_buf_slist_put(sys_slist_t *list, struct net_buf *buf);
  */
 struct net_buf * __must_check net_buf_slist_get(sys_slist_t *list);
 
-/**
- * @brief Put a buffer to the end of a FIFO.
- *
- * @deprecated Use @a k_fifo_put() instead.
- *
- * @param fifo Which FIFO to put the buffer to.
- * @param buf Buffer.
- */
-__deprecated void net_buf_put(struct k_fifo *fifo, struct net_buf *buf);
-
 /**
  * @brief Decrements the reference count of a buffer.
  *
diff --git a/include/zephyr/pm/pm.h b/include/zephyr/pm/pm.h
index e1fb695415c..443f5e37d8b 100644
--- a/include/zephyr/pm/pm.h
+++ b/include/zephyr/pm/pm.h
@@ -135,11 +135,6 @@ const struct pm_state_info *pm_state_next_get(uint8_t cpu);
  */
 void pm_system_resume(void);
 
-
-/** @cond INTERNAL_HIDDEN */
-__deprecated void z_pm_save_idle_exit(void);
-/** @endcond */
-
 /**
  * @}
  */
@@ -199,9 +194,6 @@ static inline const struct pm_state_info *pm_state_next_get(uint8_t cpu)
 
 	return NULL;
 }
-static inline void z_pm_save_idle_exit(void)
-{
-}
 
 static inline void pm_system_resume(void)
 {
diff --git a/include/zephyr/pm/policy.h b/include/zephyr/pm/policy.h
index 057488d722d..9a2d1d159be 100644
--- a/include/zephyr/pm/policy.h
+++ b/include/zephyr/pm/policy.h
@@ -137,6 +137,31 @@ void pm_policy_state_lock_put(enum pm_state state, uint8_t substate_id);
  */
 bool pm_policy_state_lock_is_active(enum pm_state state, uint8_t substate_id);
 
+/**
+ * @brief Check if a power state is available.
+ *
+ * It is unavailable if locked or latency requirement cannot be fulfilled in that state.
+ *
+ * @param state Power state.
+ * @param substate_id Power substate ID. Use PM_ALL_SUBSTATES to affect all the
+ *		      substates in the given power state.
+ *
+ * @retval true if power state is active.
+ * @retval false if power state is not active.
+ */
+bool pm_policy_state_is_available(enum pm_state state, uint8_t substate_id);
+
+/**
+ * @brief Check if any power state can be used.
+ *
+ * Function allows to quickly check if any power state is available and exit
+ * suspend operation early.
+ *
+ * @retval true if any power state is active.
+ * @retval false if all power states are unavailable.
+ */
+bool pm_policy_state_any_active(void);
+
 /**
  * @brief Register an event.
  *
diff --git a/include/zephyr/pm/state.h b/include/zephyr/pm/state.h
index 6590b90c385..a0607997137 100644
--- a/include/zephyr/pm/state.h
+++ b/include/zephyr/pm/state.h
@@ -370,6 +370,16 @@ struct pm_state_constraint {
  */
 uint8_t pm_state_cpu_get_all(uint8_t cpu, const struct pm_state_info **states);
 
+/**
+ * Get power state structure.
+ *
+ * @param cpu CPU index.
+ * @param state Power state.
+ * @param substate_id Substate.
+ *
+ * @return Pointer to the power state structure or NULL if state is not found.
+ */
+const struct pm_state_info *pm_state_get(uint8_t cpu, enum pm_state state, uint8_t substate_id);
 /**
  * @}
  */
@@ -384,6 +394,17 @@ static inline uint8_t pm_state_cpu_get_all(uint8_t cpu, const struct pm_state_in
 	return 0;
 }
 
+static inline const struct pm_state_info *pm_state_get(uint8_t cpu,
+						       enum pm_state state,
+						       uint8_t substate_id)
+{
+	ARG_UNUSED(cpu);
+	ARG_UNUSED(state);
+	ARG_UNUSED(substate_id);
+
+	return NULL;
+}
+
 #endif /* CONFIG_PM */
 
 #ifdef __cplusplus
diff --git a/include/zephyr/pmci/mctp/mctp_uart.h b/include/zephyr/pmci/mctp/mctp_uart.h
new file mode 100644
index 00000000000..63eb1de9f25
--- /dev/null
+++ b/include/zephyr/pmci/mctp/mctp_uart.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2024 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#ifndef ZEPHYR_MCTP_UART_H_
+#define ZEPHYR_MCTP_UART_H_
+
+#include <stdint.h>
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <libmctp.h>
+
+/**
+ * @brief An MCTP binding for Zephyr's asynchronous UART interface
+ */
+struct mctp_binding_uart {
+	/** @cond INTERNAL_HIDDEN */
+	struct mctp_binding binding;
+	const struct device *dev;
+
+	/* receive buffers and state */
+	uint8_t rx_buf[2][256];
+	bool rx_buf_used[2];
+	struct mctp_pktbuf *rx_pkt;
+	uint8_t rx_exp_len;
+	uint16_t rx_fcs;
+	uint16_t rx_fcs_calc;
+	enum {
+		STATE_WAIT_SYNC_START,
+		STATE_WAIT_REVISION,
+		STATE_WAIT_LEN,
+		STATE_DATA,
+		STATE_DATA_ESCAPED,
+		STATE_WAIT_FCS1,
+		STATE_WAIT_FCS2,
+		STATE_WAIT_SYNC_END,
+	} rx_state;
+	int rx_res;
+
+	/* staging buffer for tx */
+	uint8_t tx_buf[256];
+	int tx_res;
+
+	/** @endcond INTERNAL_HIDDEN */
+};
+
+/**
+ * @brief Start the receive of a single mctp message
+ *
+ * Will read a single mctp message from the uart.
+ *
+ * @param uart MCTP UART binding
+ */
+void mctp_uart_start_rx(struct mctp_binding_uart *uart);
+
+/** @cond INTERNAL_HIDDEN */
+int mctp_uart_start(struct mctp_binding *binding);
+int mctp_uart_tx(struct mctp_binding *binding, struct mctp_pktbuf *pkt);
+/** @endcond INTERNAL_HIDDEN */
+
+/**
+ * @brief Statically define a MCTP bus binding for a UART
+ *
+ * @param _name Symbolic name of the bus binding variable
+ * @param _dev UART device
+ */
+#define MCTP_UART_DT_DEFINE(_name, _dev)                                                           \
+	struct mctp_binding_uart _name = {                                                         \
+		.binding =                                                                         \
+			{                                                                          \
+				.name = STRINGIFY(_name), .version = 1,                            \
+						  .pkt_size = MCTP_PACKET_SIZE(MCTP_BTU),          \
+						  .pkt_header = 0, .pkt_trailer = 0,               \
+						  .start = mctp_uart_start, .tx = mctp_uart_tx,    \
+				},                                                                 \
+				.dev = _dev,                                                       \
+				.rx_state = STATE_WAIT_SYNC_START,                                 \
+				.rx_pkt = NULL,                                                    \
+				.rx_res = 0,                                                       \
+				.tx_res = 0,                                                       \
+	};
+
+#endif /* ZEPHYR_MCTP_UART_H_ */
diff --git a/include/zephyr/portability/cmsis_types.h b/include/zephyr/portability/cmsis_types.h
new file mode 100644
index 00000000000..0bbe178522a
--- /dev/null
+++ b/include/zephyr/portability/cmsis_types.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2018 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_CMSIS_TYPES_H_
+#define ZEPHYR_INCLUDE_CMSIS_TYPES_H_
+
+#include <stdbool.h>
+#include <zephyr/kernel.h>
+#include <zephyr/portability/cmsis_os2.h>
+
+/**
+ * @brief Control block for a CMSIS-RTOSv2 thread.
+ *
+ * Application can use manual user-defined allocation for RTOS objects by supplying a pointer to
+ * thread control block. Control block is initiazed within `osThreadNew()`.
+ */
+struct cmsis_rtos_thread_cb {
+	sys_dnode_t node;
+	struct k_thread z_thread;
+	struct k_poll_signal poll_signal;
+	struct k_poll_event poll_event;
+	uint32_t signal_results;
+	uint32_t attr_bits;
+};
+
+/**
+ * @brief Control block for a CMSIS-RTOSv2 timer.
+ *
+ * Application can use manual user-defined allocation for RTOS objects by supplying a pointer to
+ * timer control block. Control block is initiazed within `osTimerNew()`.
+ */
+struct cmsis_rtos_timer_cb {
+	struct k_timer z_timer;
+	osTimerType_t type;
+	uint32_t status;
+	bool is_cb_dynamic_allocation;
+	const char *name;
+	void (*callback_function)(void *argument);
+	void *arg;
+};
+
+/**
+ * @brief Control block for a CMSIS-RTOSv2 mutex.
+ *
+ * Application can use manual user-defined allocation for RTOS objects by supplying a pointer to
+ * mutex control block. Control block is initiazed within `osMutexNew()`.
+ */
+struct cmsis_rtos_mutex_cb {
+	struct k_mutex z_mutex;
+	bool is_cb_dynamic_allocation;
+	const char *name;
+	uint32_t state;
+};
+
+/**
+ * @brief Control block for a CMSIS-RTOSv2 semaphore.
+ *
+ * Application can use manual user-defined allocation for RTOS objects by supplying a pointer to
+ * semaphore control block. Control block is initiazed within `osSemaphoreNew()`.
+ */
+struct cmsis_rtos_semaphore_cb {
+	struct k_sem z_semaphore;
+	bool is_cb_dynamic_allocation;
+	const char *name;
+};
+
+/**
+ * @brief Control block for a CMSIS-RTOSv2 memory pool.
+ *
+ * Application can use manual user-defined allocation for RTOS objects by supplying a pointer to
+ * memory pool control block. Control block is initiazed within `osMemoryPoolNew()`.
+ */
+struct cmsis_rtos_mempool_cb {
+	struct k_mem_slab z_mslab;
+	void *pool;
+	char is_dynamic_allocation;
+	bool is_cb_dynamic_allocation;
+	const char *name;
+};
+
+/**
+ * @brief Control block for a CMSIS-RTOSv2 message queue.
+ *
+ * Application can use manual user-defined allocation for RTOS objects by supplying a pointer to
+ * message queue control block. Control block is initiazed within `osMessageQueueNew()`.
+ */
+struct cmsis_rtos_msgq_cb {
+	struct k_msgq z_msgq;
+	void *pool;
+	char is_dynamic_allocation;
+	bool is_cb_dynamic_allocation;
+	const char *name;
+};
+
+/**
+ * @brief Control block for a CMSIS-RTOSv2 event flag.
+ *
+ * Application can use manual user-defined allocation for RTOS objects by supplying a pointer to
+ * event flag control block. Control block is initiazed within `osEventFlagsNew()`.
+ */
+struct cmsis_rtos_event_cb {
+	struct k_poll_signal poll_signal;
+	struct k_poll_event poll_event;
+	uint32_t signal_results;
+	bool is_cb_dynamic_allocation;
+	const char *name;
+};
+
+#endif
diff --git a/include/zephyr/posix/posix_features.h b/include/zephyr/posix/posix_features.h
index e4a91c6fc92..099484555bc 100644
--- a/include/zephyr/posix/posix_features.h
+++ b/include/zephyr/posix/posix_features.h
@@ -27,6 +27,11 @@
 #define _POSIX_AEP_REALTIME_DEDICATED 200312L
 #endif
 
+/*
+ * Subprofiling Considerations
+ */
+#define _POSIX_SUBPROFILE 1
+
 /*
  * POSIX System Interfaces
  */
@@ -201,9 +206,9 @@
 /*
  * POSIX2 Options
  */
-#define _POSIX2_VERSION _POSIX_VERSION
-#define _POSIX2_C_BIND  _POSIX2_VERSION
-#define _POSIX2_C_DEV   _POSIX2_VERSION
+/* #define _POSIX2_VERSION (-1) */
+#define _POSIX2_C_BIND _POSIX_VERSION
+/* #define _POSIX2_C_DEV (-1) */
 /* #define _POSIX2_CHAR_TERM (-1L) */
 /* #define _POSIX2_FORT_DEV (-1L) */
 /* #define _POSIX2_FORT_RUN (-1L) */
@@ -223,7 +228,13 @@
 #define _XOPEN_VERSION 700
 /* #define _XOPEN_CRYPT (-1L) */
 /* #define _XOPEN_ENH_I18N (-1L) */
-/* #define _XOPEN_REALTIME (-1L) */
+#if defined(CONFIG_XSI_REALTIME) ||                                                                \
+	(defined(CONFIG_POSIX_FSYNC) && defined(CONFIG_POSIX_MEMLOCK) &&                           \
+	 defined(CONFIG_POSIX_MEMLOCK_RANGE) && defined(CONFIG_POSIX_MESSAGE_PASSING) &&           \
+	 defined(CONFIG_POSIX_PRIORITY_SCHEDULING) &&                                              \
+	 defined(CONFIG_POSIX_SHARED_MEMORY_OBJECTS) && defined(CONFIG_POSIX_SYNCHRONIZED_IO))
+#define _XOPEN_REALTIME _XOPEN_VERSION
+#endif
 /* #define _XOPEN_REALTIME_THREADS (-1L) */
 /* #define _XOPEN_SHM (-1L) */
 
diff --git a/include/zephyr/posix/signal.h b/include/zephyr/posix/signal.h
index 38c3be378ca..827f1edff7e 100644
--- a/include/zephyr/posix/signal.h
+++ b/include/zephyr/posix/signal.h
@@ -122,9 +122,9 @@ unsigned int alarm(unsigned int seconds);
 int kill(pid_t pid, int sig);
 int pause(void);
 int raise(int signo);
-TOOLCHAIN_IGNORE_WSHADOW_BEGIN;
+TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_SHADOW);
 int sigaction(int sig, const struct sigaction *ZRESTRICT act, struct sigaction *ZRESTRICT oact);
-TOOLCHAIN_IGNORE_WSHADOW_END;
+TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_SHADOW);
 int sigpending(sigset_t *set);
 int sigsuspend(const sigset_t *sigmask);
 int sigwait(const sigset_t *ZRESTRICT set, int *ZRESTRICT signo);
diff --git a/include/zephyr/posix/sys/sysconf.h b/include/zephyr/posix/sys/sysconf.h
index c7d8228a8cd..67bf84bfb75 100644
--- a/include/zephyr/posix/sys/sysconf.h
+++ b/include/zephyr/posix/sys/sysconf.h
@@ -233,7 +233,8 @@ enum {
 #define __z_posix_sysconf_SC_BC_SCALE_MAX                 _POSIX2_BC_SCALE_MAX
 #define __z_posix_sysconf_SC_BC_STRING_MAX                _POSIX2_BC_STRING_MAX
 #define __z_posix_sysconf_SC_2_C_BIND                     _POSIX2_C_BIND
-#define __z_posix_sysconf_SC_2_C_DEV                      _POSIX2_C_DEV
+#define __z_posix_sysconf_SC_2_C_DEV                                                               \
+	COND_CODE_1(_POSIX2_C_DEV > 0, (_POSIX2_C_DEV), (-1))
 #define __z_posix_sysconf_SC_2_CHAR_TERM                  (-1L)
 #define __z_posix_sysconf_SC_COLL_WEIGHTS_MAX             _POSIX2_COLL_WEIGHTS_MAX
 #define __z_posix_sysconf_SC_DELAYTIMER_MAX               _POSIX_DELAYTIMER_MAX
@@ -250,7 +251,8 @@ enum {
 #define __z_posix_sysconf_SC_2_PBS_TRACK                  (-1L)
 #define __z_posix_sysconf_SC_2_SW_DEV                     (-1L)
 #define __z_posix_sysconf_SC_2_UPE                        (-1L)
-#define __z_posix_sysconf_SC_2_VERSION                    _POSIX2_VERSION
+#define __z_posix_sysconf_SC_2_VERSION                                                             \
+	COND_CODE_1(_POSIX2_VERSION > 0, (_POSIX2_VERSION), (-1))
 #define __z_posix_sysconf_SC_XOPEN_CRYPT                  (-1L)
 #define __z_posix_sysconf_SC_XOPEN_ENH_I18N               (-1L)
 #define __z_posix_sysconf_SC_XOPEN_REALTIME               (-1L)
diff --git a/include/zephyr/posix/time.h b/include/zephyr/posix/time.h
index 51542f304fa..7f944b7db97 100644
--- a/include/zephyr/posix/time.h
+++ b/include/zephyr/posix/time.h
@@ -85,11 +85,6 @@ extern "C" {
 #define TIMER_ABSTIME 4
 #endif
 
-static inline int32_t _ts_to_ms(const struct timespec *to)
-{
-	return (int32_t)(to->tv_sec * MSEC_PER_SEC) + (int32_t)(to->tv_nsec / NSEC_PER_MSEC);
-}
-
 int clock_gettime(clockid_t clock_id, struct timespec *ts);
 int clock_getres(clockid_t clock_id, struct timespec *ts);
 int clock_settime(clockid_t clock_id, const struct timespec *ts);
diff --git a/include/zephyr/rtio/rtio.h b/include/zephyr/rtio/rtio.h
index 9d117813185..ce5355aa52e 100644
--- a/include/zephyr/rtio/rtio.h
+++ b/include/zephyr/rtio/rtio.h
@@ -1137,10 +1137,14 @@ static inline uint32_t rtio_cqe_compute_flags(struct rtio_iodev_sqe *iodev_sqe)
 	if (iodev_sqe->sqe.op == RTIO_OP_RX && iodev_sqe->sqe.flags & RTIO_SQE_MEMPOOL_BUFFER) {
 		struct rtio *r = iodev_sqe->r;
 		struct sys_mem_blocks *mem_pool = r->block_pool;
-		int blk_index = (iodev_sqe->sqe.rx.buf - mem_pool->buffer) >>
-				mem_pool->info.blk_sz_shift;
-		int blk_count = iodev_sqe->sqe.rx.buf_len >> mem_pool->info.blk_sz_shift;
+		unsigned int blk_index = 0;
+		unsigned int blk_count = 0;
 
+		if (iodev_sqe->sqe.rx.buf) {
+			blk_index = (iodev_sqe->sqe.rx.buf - mem_pool->buffer) >>
+				    mem_pool->info.blk_sz_shift;
+			blk_count = iodev_sqe->sqe.rx.buf_len >> mem_pool->info.blk_sz_shift;
+		}
 		flags = RTIO_CQE_FLAG_PREP_MEMPOOL(blk_index, blk_count);
 	}
 #else
@@ -1173,15 +1177,21 @@ static inline int z_impl_rtio_cqe_get_mempool_buffer(const struct rtio *r, struc
 {
 #ifdef CONFIG_RTIO_SYS_MEM_BLOCKS
 	if (RTIO_CQE_FLAG_GET(cqe->flags) == RTIO_CQE_FLAG_MEMPOOL_BUFFER) {
-		int blk_idx = RTIO_CQE_FLAG_MEMPOOL_GET_BLK_IDX(cqe->flags);
-		int blk_count = RTIO_CQE_FLAG_MEMPOOL_GET_BLK_CNT(cqe->flags);
+		unsigned int blk_idx = RTIO_CQE_FLAG_MEMPOOL_GET_BLK_IDX(cqe->flags);
+		unsigned int blk_count = RTIO_CQE_FLAG_MEMPOOL_GET_BLK_CNT(cqe->flags);
 		uint32_t blk_size = rtio_mempool_block_size(r);
 
-		*buff = r->block_pool->buffer + blk_idx * blk_size;
 		*buff_len = blk_count * blk_size;
-		__ASSERT_NO_MSG(*buff >= r->block_pool->buffer);
-		__ASSERT_NO_MSG(*buff <
+
+		if (blk_count > 0) {
+			*buff = r->block_pool->buffer + blk_idx * blk_size;
+
+			__ASSERT_NO_MSG(*buff >= r->block_pool->buffer);
+			__ASSERT_NO_MSG(*buff <
 				r->block_pool->buffer + blk_size * r->block_pool->info.num_blocks);
+		} else {
+			*buff = NULL;
+		}
 		return 0;
 	}
 	return -EINVAL;
@@ -1249,7 +1259,16 @@ static inline void rtio_cqe_submit(struct rtio *r, int result, void *userdata, u
 		rtio_cqe_produce(r, cqe);
 	}
 
-	atomic_inc(&r->cq_count);
+	/* atomic_t isn't guaranteed to wrap correctly as it could be signed, so
+	 * we must resort to a cas loop.
+	 */
+	atomic_t val, new_val;
+
+	do {
+		val = atomic_get(&r->cq_count);
+		new_val = (atomic_t)((uintptr_t)val + 1);
+	} while (!atomic_cas(&r->cq_count, val, new_val));
+
 #ifdef CONFIG_RTIO_SUBMIT_SEM
 	if (r->submit_count > 0) {
 		r->submit_count--;
@@ -1500,6 +1519,8 @@ static inline int z_impl_rtio_cqe_copy_out(struct rtio *r,
  * submission chain, freeing submission queue events when done, and
  * producing completion queue events as submissions are completed.
  *
+ * @warning It is undefined behavior to have re-entrant calls to submit
+ *
  * @param r RTIO context
  * @param wait_count Number of submissions to wait for completion of.
  *
@@ -1507,13 +1528,11 @@ static inline int z_impl_rtio_cqe_copy_out(struct rtio *r,
  */
 __syscall int rtio_submit(struct rtio *r, uint32_t wait_count);
 
+#ifdef CONFIG_RTIO_SUBMIT_SEM
 static inline int z_impl_rtio_submit(struct rtio *r, uint32_t wait_count)
 {
 	int res = 0;
 
-#ifdef CONFIG_RTIO_SUBMIT_SEM
-	/* TODO undefined behavior if another thread calls submit of course
-	 */
 	if (wait_count > 0) {
 		__ASSERT(!k_is_in_isr(),
 			 "expected rtio submit with wait count to be called from a thread");
@@ -1521,35 +1540,43 @@ static inline int z_impl_rtio_submit(struct rtio *r, uint32_t wait_count)
 		k_sem_reset(r->submit_sem);
 		r->submit_count = wait_count;
 	}
-#else
-	uintptr_t cq_count = (uintptr_t)atomic_get(&r->cq_count) + wait_count;
-#endif
 
-	/* Submit the queue to the executor which consumes submissions
-	 * and produces completions through ISR chains or other means.
-	 */
 	rtio_executor_submit(r);
 
-
-	/* TODO could be nicer if we could suspend the thread and not
-	 * wake up on each completion here.
-	 */
-#ifdef CONFIG_RTIO_SUBMIT_SEM
-
 	if (wait_count > 0) {
 		res = k_sem_take(r->submit_sem, K_FOREVER);
 		__ASSERT(res == 0,
 			 "semaphore was reset or timed out while waiting on completions!");
 	}
+
+	return res;
+}
 #else
-	while ((uintptr_t)atomic_get(&r->cq_count) < cq_count) {
+static inline int z_impl_rtio_submit(struct rtio *r, uint32_t wait_count)
+{
+
+	int res = 0;
+	uintptr_t cq_count = (uintptr_t)atomic_get(&r->cq_count);
+	uintptr_t cq_complete_count = cq_count + wait_count;
+	bool wraps = cq_complete_count < cq_count;
+
+	rtio_executor_submit(r);
+
+	if (wraps) {
+		while ((uintptr_t)atomic_get(&r->cq_count) >= cq_count) {
+			Z_SPIN_DELAY(10);
+			k_yield();
+		}
+	}
+
+	while ((uintptr_t)atomic_get(&r->cq_count) < cq_complete_count) {
 		Z_SPIN_DELAY(10);
 		k_yield();
 	}
-#endif
 
 	return res;
 }
+#endif /* CONFIG_RTIO_SUBMIT_SEM */
 
 /**
  * @}
diff --git a/include/zephyr/shell/shell.h b/include/zephyr/shell/shell.h
index 9f7d18f7ce7..5115e35339b 100644
--- a/include/zephyr/shell/shell.h
+++ b/include/zephyr/shell/shell.h
@@ -952,7 +952,7 @@ extern void z_shell_print_stream(const void *user_ctx, const char *data,
 	static struct shell_ctx UTIL_CAT(_name, _ctx);                                             \
 	Z_SHELL_HISTORY_DEFINE(_name##_history, CONFIG_SHELL_HISTORY_BUFFER);                      \
 	Z_SHELL_FPRINTF_DEFINE(_name##_fprintf, &_name, _out_buf, CONFIG_SHELL_PRINTF_BUFF_SIZE,   \
-			       true, z_shell_print_stream);                                        \
+			       IS_ENABLED(CONFIG_SHELL_PRINTF_AUTOFLUSH), z_shell_print_stream);   \
 	LOG_INSTANCE_REGISTER(shell, _name, CONFIG_SHELL_LOG_LEVEL);                               \
 	Z_SHELL_STATS_DEFINE(_name);                                                               \
 	static K_KERNEL_STACK_DEFINE(_name##_stack, CONFIG_SHELL_STACK_SIZE);                      \
diff --git a/include/zephyr/shell/shell_websocket.h b/include/zephyr/shell/shell_websocket.h
index 12bd49727a2..dd93e6913ba 100644
--- a/include/zephyr/shell/shell_websocket.h
+++ b/include/zephyr/shell/shell_websocket.h
@@ -62,8 +62,8 @@ struct shell_websocket {
 };
 
 extern const struct shell_transport_api shell_websocket_transport_api;
-extern int shell_websocket_setup(int ws_socket, void *user_data);
-extern int shell_websocket_enable(const struct shell *sh);
+int shell_websocket_setup(int ws_socket, struct http_request_ctx *request_ctx, void *user_data);
+int shell_websocket_enable(const struct shell *sh);
 
 #define GET_WS_NAME(_service) ws_ctx_##_service
 #define GET_WS_SHELL_NAME(_name) shell_websocket_##_name
@@ -121,6 +121,7 @@ extern int shell_websocket_enable(const struct shell *sh);
 			     SHELL_WEBSOCKET_SERVICE_COUNT,		  \
 			     SHELL_WEBSOCKET_SERVICE_COUNT,		  \
 			     NULL,					  \
+			     NULL,                                        \
 			     _sec_tag_list,				  \
 			     _sec_tag_list_size);			  \
 	DEFINE_WEBSOCKET_SERVICE(_service);				  \
@@ -136,7 +137,7 @@ extern int shell_websocket_enable(const struct shell *sh);
 			    &SHELL_WS_PORT_NAME(_service),		\
 			    SHELL_WEBSOCKET_SERVICE_COUNT,		\
 			    SHELL_WEBSOCKET_SERVICE_COUNT,		\
-			    NULL);					\
+			    NULL, NULL);				\
 	DEFINE_WEBSOCKET_SERVICE(_service)
 
 #endif /* CONFIG_NET_SOCKETS_SOCKOPT_TLS */
diff --git a/include/zephyr/storage/flash_map.h b/include/zephyr/storage/flash_map.h
index 670a14308e6..f62f1c21718 100644
--- a/include/zephyr/storage/flash_map.h
+++ b/include/zephyr/storage/flash_map.h
@@ -188,6 +188,28 @@ int flash_area_read(const struct flash_area *fa, off_t off, void *dst,
 int flash_area_write(const struct flash_area *fa, off_t off, const void *src,
 		     size_t len);
 
+/**
+ * @brief Copy flash memory from one flash area to another.
+ *
+ * Copy data to flash area. Area boundaries are asserted before copy
+ * request.
+ *
+ * For more information, see flash_copy().
+ *
+ * @param[in]  src_fa  Source Flash area
+ * @param[in]  src_off Offset relative from beginning of source flash area.
+ * @param[in]  dst_fa  Destination Flash area
+ * @param[in]  dst_off Offset relative from beginning of destination flash area.
+ * @param[in]  len Number of bytes to copy, in bytes.
+ * @param[out] buf Pointer to a buffer of size @a buf_size.
+ * @param[in]  buf_size Size of the buffer pointed to by @a buf.
+ *
+ * @return  0 on success, negative errno code on fail.
+ */
+int flash_area_copy(const struct flash_area *src_fa, off_t src_off,
+		    const struct flash_area *dst_fa, off_t dst_off,
+		    off_t len, uint8_t *buf, size_t buf_size);
+
 /**
  * @brief Erase flash area
  *
diff --git a/include/zephyr/storage/stream_flash.h b/include/zephyr/storage/stream_flash.h
index a3e4473526d..ab3711ee4ff 100644
--- a/include/zephyr/storage/stream_flash.h
+++ b/include/zephyr/storage/stream_flash.h
@@ -65,7 +65,9 @@ struct stream_flash_ctx {
 	stream_flash_callback_t callback; /* Callback invoked after write op */
 #endif
 #ifdef CONFIG_STREAM_FLASH_ERASE
-	off_t last_erased_page_start_offset; /* Last erased offset */
+	size_t erased_up_to;		/* Offset of last erased byte, relative to
+					 * offset in this context.
+					 */
 #endif
 	size_t write_block_size;	/* Offset/size device write alignment */
 	uint8_t erase_value;
@@ -128,6 +130,9 @@ int stream_flash_buffered_write(struct stream_flash_ctx *ctx, const uint8_t *dat
 /**
  * @brief Erase the flash page to which a given offset belongs.
  *
+ * @deprecated Use @a flash_area_erase() or flash_erase(). Note that there
+ * is no Stream Flash API equivalent for that.
+ *
  * This function erases a flash page to which an offset belongs if this page
  * is not the page previously erased by the provided ctx
  * (ctx->last_erased_page_start_offset).
@@ -137,7 +142,7 @@ int stream_flash_buffered_write(struct stream_flash_ctx *ctx, const uint8_t *dat
  *
  * @return non-negative on success, negative errno code on fail
  */
-int stream_flash_erase_page(struct stream_flash_ctx *ctx, off_t off);
+__deprecated int stream_flash_erase_page(struct stream_flash_ctx *ctx, off_t off);
 
 /**
  * @brief Load persistent stream write progress stored with key
diff --git a/include/zephyr/sw_isr_table.h b/include/zephyr/sw_isr_table.h
index 3636f49591e..21bad9270d6 100644
--- a/include/zephyr/sw_isr_table.h
+++ b/include/zephyr/sw_isr_table.h
@@ -213,7 +213,7 @@ extern struct z_shared_isr_table_entry z_shared_sw_isr_table[];
 
 #define _Z_ISR_DECLARE_C(irq, flags, func, param, counter)                                \
 	_Z_ISR_TABLE_ENTRY(irq, func, param, _MK_ISR_ELEMENT_SECTION(counter));           \
-	static struct _isr_list_sname Z_GENERIC_SECTION(.intList)                         \
+	static Z_DECL_ALIGN(struct _isr_list_sname) Z_GENERIC_SECTION(.intList)           \
 		__used _MK_ISR_NAME(func, counter) =                                      \
 		{irq, flags, _MK_ISR_ELEMENT_SECTION(counter)}
 
@@ -247,7 +247,7 @@ extern struct z_shared_isr_table_entry z_shared_sw_isr_table[];
 
 #define _Z_ISR_DECLARE_DIRECT_C(irq, flags, func, counter)                                         \
 	_Z_ISR_DIRECT_TABLE_ENTRY(irq, func, _MK_IRQ_ELEMENT_SECTION(counter));                    \
-	static struct _isr_list_sname Z_GENERIC_SECTION(.intList)                                  \
+	static Z_DECL_ALIGN(struct _isr_list_sname) Z_GENERIC_SECTION(.intList)                    \
 		__used _MK_ISR_NAME(func, counter) = {                                             \
 			irq,                                                                       \
 			ISR_FLAG_DIRECT | (flags),                                                 \
diff --git a/include/zephyr/sys/byteorder.h b/include/zephyr/sys/byteorder.h
index 2b987dd14fe..6de4a3f8bad 100644
--- a/include/zephyr/sys/byteorder.h
+++ b/include/zephyr/sys/byteorder.h
@@ -13,7 +13,9 @@
 
 #include <zephyr/types.h>
 #include <stddef.h>
+#include <string.h>
 #include <zephyr/sys/__assert.h>
+#include <zephyr/sys/util_macro.h>
 #include <zephyr/toolchain.h>
 
 #define BSWAP_16(x) ((uint16_t) ((((x) >> 8) & 0xff) | (((x) & 0xff) << 8)))
@@ -719,4 +721,132 @@ static inline void sys_mem_swap(void *buf, size_t length)
 	}
 }
 
+/**
+ *  @brief Convert buffer from little-endian to host endianness.
+ *
+ * @param buf A valid pointer on a memory area to convert from little-endian to host endianness.
+ * @param length Size of buf memory area
+ */
+static inline void sys_le_to_cpu(void *buf, size_t length)
+{
+	if (IS_ENABLED(CONFIG_BIG_ENDIAN)) {
+		sys_mem_swap(buf, length);
+	}
+}
+
+/**
+ *  @brief Convert buffer from host endianness to little-endian.
+ *
+ * @param buf A valid pointer on a memory area to convert from host endianness to little-endian.
+ * @param length Size of buf memory area
+ */
+static inline void sys_cpu_to_le(void *buf, size_t length)
+{
+	if (IS_ENABLED(CONFIG_BIG_ENDIAN)) {
+		sys_mem_swap(buf, length);
+	}
+}
+
+/**
+ *  @brief Convert buffer from big-endian to host endianness.
+ *
+ * @param buf A valid pointer on a memory area to convert from big-endian to host endianness.
+ * @param length Size of buf memory area
+ */
+static inline void sys_be_to_cpu(void *buf, size_t length)
+{
+	if (IS_ENABLED(CONFIG_LITTLE_ENDIAN)) {
+		sys_mem_swap(buf, length);
+	}
+}
+
+/**
+ *  @brief Convert buffer from host endianness to big-endian.
+ *
+ * @param buf A valid pointer on a memory area to convert from host endianness to big-endian.
+ * @param length Size of buf memory area
+ */
+static inline void sys_cpu_to_be(void *buf, size_t length)
+{
+	if (IS_ENABLED(CONFIG_LITTLE_ENDIAN)) {
+		sys_mem_swap(buf, length);
+	}
+}
+
+/**
+ *  @brief Put a buffer as little-endian to arbitrary location.
+ *
+ *  Put a buffer originally in host endianness, to a
+ *  potentially unaligned memory location in little-endian format.
+ *
+ * @param dst A valid pointer on a memory area where to copy the data in
+ * @param src A valid pointer on a memory area where to copy the data from
+ * @param length Size of both dst and src memory areas
+ */
+static inline void sys_put_le(void *dst, const void *src, size_t length)
+{
+	if (IS_ENABLED(CONFIG_LITTLE_ENDIAN)) {
+		(void)memcpy(dst, src, length);
+	} else {
+		sys_memcpy_swap(dst, src, length);
+	}
+}
+
+/**
+ *  @brief Put a buffer as big-endian to arbitrary location.
+ *
+ *  Put a buffer originally in host endianness, to a
+ *  potentially unaligned memory location in big-endian format.
+ *
+ * @param dst A valid pointer on a memory area where to copy the data in
+ * @param src A valid pointer on a memory area where to copy the data from
+ * @param length Size of both dst and src memory areas
+ */
+static inline void sys_put_be(void *dst, const void *src, size_t length)
+{
+	if (IS_ENABLED(CONFIG_LITTLE_ENDIAN)) {
+		sys_memcpy_swap(dst, src, length);
+	} else {
+		(void)memcpy(dst, src, length);
+	}
+}
+
+/**
+ *  @brief Get a buffer stored in little-endian format.
+ *
+ *  Get a buffer, stored in little-endian format in a potentially
+ *  unaligned memory location, and convert it to the host endianness.
+ *
+ * @param dst A valid pointer on a memory area where to copy the data in
+ * @param src A valid pointer on a memory area where to copy the data from
+ * @param length Size of both dst and src memory areas
+ */
+static inline void sys_get_le(void *dst, const void *src, size_t length)
+{
+	if (IS_ENABLED(CONFIG_LITTLE_ENDIAN)) {
+		(void)memcpy(dst, src, length);
+	} else {
+		sys_memcpy_swap(dst, src, length);
+	}
+}
+
+/**
+ *  @brief Get a buffer stored in big-endian format.
+ *
+ *  Get a buffer, stored in big-endian format in a potentially
+ *  unaligned memory location, and convert it to the host endianness.
+ *
+ * @param dst A valid pointer on a memory area where to copy the data in
+ * @param src A valid pointer on a memory area where to copy the data from
+ * @param length Size of both dst and src memory areas
+ */
+static inline void sys_get_be(void *dst, const void *src, size_t length)
+{
+	if (IS_ENABLED(CONFIG_LITTLE_ENDIAN)) {
+		sys_memcpy_swap(dst, src, length);
+	} else {
+		(void)memcpy(dst, src, length);
+	}
+}
+
 #endif /* ZEPHYR_INCLUDE_SYS_BYTEORDER_H_ */
diff --git a/include/zephyr/sys/cbprintf_cxx.h b/include/zephyr/sys/cbprintf_cxx.h
index 75a2ba16ff4..f58ca636974 100644
--- a/include/zephyr/sys/cbprintf_cxx.h
+++ b/include/zephyr/sys/cbprintf_cxx.h
@@ -81,11 +81,10 @@ template < typename T >
 static inline int z_cbprintf_cxx_is_pchar(T arg, bool const_as_fixed)
 {
 	ARG_UNUSED(arg);
-	_Pragma("GCC diagnostic push")
-	_Pragma("GCC diagnostic ignored \"-Wpointer-arith\"")
+	TOOLCHAIN_DISABLE_GCC_WARNING(TOOLCHAIN_WARNING_POINTER_ARITH);
 	ARG_UNUSED(const_as_fixed);
 	return 0;
-	_Pragma("GCC diagnostic pop")
+	TOOLCHAIN_ENABLE_GCC_WARNING(TOOLCHAIN_WARNING_POINTER_ARITH);
 }
 
 /* C++ version for determining if variable type is numeric and fits in 32 bit word. */
@@ -133,10 +132,9 @@ template < typename T >
 static inline int z_cbprintf_cxx_is_word_num(T arg)
 {
 	ARG_UNUSED(arg);
-	_Pragma("GCC diagnostic push")
-	_Pragma("GCC diagnostic ignored \"-Wpointer-arith\"")
+	TOOLCHAIN_DISABLE_GCC_WARNING(TOOLCHAIN_WARNING_POINTER_ARITH);
 	return 0;
-	_Pragma("GCC diagnostic pop")
+	TOOLCHAIN_ENABLE_GCC_WARNING(TOOLCHAIN_WARNING_POINTER_ARITH);
 }
 
 /* C++ version for determining if argument is a none character pointer. */
diff --git a/include/zephyr/sys/cbprintf_internal.h b/include/zephyr/sys/cbprintf_internal.h
index b580eea8704..0ae27ac34a1 100644
--- a/include/zephyr/sys/cbprintf_internal.h
+++ b/include/zephyr/sys/cbprintf_internal.h
@@ -82,6 +82,12 @@ extern "C" {
 #define Z_CBPRINTF_VA_STACK_LL_DBL_MEMCPY	0
 #endif
 
+/** Trick compiler to allow working with all types of arguments, including bitfields,
+ * opaque struct pointers. Alternative is to add + 0 but that requires suppressing
+ * compiler warning about pointer arithmetic and does not cover opaque structs.
+ */
+#define Z_ARGIFY(arg) ((0) ? (arg) : (arg))
+
 /** @brief Return 1 if argument is a pointer to char or wchar_t
  *
  * @param x argument.
@@ -94,7 +100,7 @@ extern "C" {
 #else
 /* NOLINTBEGIN(misc-redundant-expression) */
 #define Z_CBPRINTF_IS_PCHAR(x, flags) \
-	_Generic((x) + 0, \
+	_Generic(Z_ARGIFY(x), \
 		/* char * */ \
 		char * : 1, \
 		const char * : ((flags) & CBPRINTF_PACKAGE_CONST_CHAR_RO) ? 0 : 1, \
@@ -154,7 +160,7 @@ extern "C" {
 #define Z_CBPRINTF_IS_NONE_CHAR_PTR(x) z_cbprintf_cxx_is_none_char_ptr(x)
 #else
 #define Z_CBPRINTF_IS_NONE_CHAR_PTR(x) \
-	_Generic((x) + 0, \
+	_Generic(Z_ARGIFY(x), \
 		char * : 0, \
 		volatile char * : 0, \
 		const char * : 0, \
@@ -530,15 +536,12 @@ extern "C" {
  */
 #if Z_C_GENERIC
 #define Z_CBPRINTF_MUST_RUNTIME_PACKAGE(flags, ...) ({\
-	_Pragma("GCC diagnostic push") \
-	_Pragma("GCC diagnostic ignored \"-Wpointer-arith\"") \
 	int _rv; \
 	if ((flags) & CBPRINTF_PACKAGE_ADD_RW_STR_POS) { \
 		_rv = 0; \
 	} else { \
 		_rv = Z_CBPRINTF_PCHAR_COUNT(flags, __VA_ARGS__) > 0 ? 1 : 0; \
 	} \
-	_Pragma("GCC diagnostic pop")\
 	_rv; \
 })
 #else
@@ -559,7 +562,7 @@ extern "C" {
 #else
 #define Z_CONSTIFY(v) (_Generic((v), char * : (const char *)(uintptr_t)(v), default : (v)))
 #define Z_CBPRINTF_ARG_SIZE(v) ({\
-	__auto_type __v = (Z_CONSTIFY(v)) + 0; \
+	__auto_type __v = Z_ARGIFY(Z_CONSTIFY(v)); \
 	/* Static code analysis may complain about unused variable. */ \
 	(void)__v; \
 	size_t __arg_size = _Generic((v), \
@@ -583,9 +586,9 @@ extern "C" {
 #define Z_CBPRINTF_STORE_ARG(buf, arg) do { \
 	if (Z_CBPRINTF_VA_STACK_LL_DBL_MEMCPY) { \
 		/* If required, copy arguments by word to avoid unaligned access.*/ \
-		__auto_type _v = (Z_CONSTIFY(arg)) + 0; \
-		double _d = _Generic((arg) + 0, \
-				float : (arg) + 0, \
+		__auto_type _v = Z_ARGIFY(Z_CONSTIFY(arg)); \
+		double _d = _Generic(Z_ARGIFY(arg), \
+				float : Z_ARGIFY(arg), \
 				default : \
 					0.0); \
 		/* Static code analysis may complain about unused variable. */ \
@@ -594,10 +597,10 @@ extern "C" {
 		size_t arg_size = Z_CBPRINTF_ARG_SIZE(arg); \
 		size_t _wsize = arg_size / sizeof(int); \
 		z_cbprintf_wcpy((int *)(buf), \
-			      (int *) _Generic((arg) + 0, float : &_d, default : &_v), \
+			      (int *) _Generic(Z_ARGIFY(arg), float : &_d, default : &_v), \
 			      _wsize); \
 	} else { \
-		*_Generic((arg) + 0, \
+		*_Generic(Z_ARGIFY(arg), \
 			char : (int *)(buf), \
 			unsigned char: (int *)(buf), \
 			short : (int *)(buf), \
@@ -627,14 +630,14 @@ extern "C" {
 #define Z_CBPRINTF_ALIGNMENT(_arg) z_cbprintf_cxx_alignment(_arg)
 #else
 #define Z_CBPRINTF_ALIGNMENT(_arg) \
-	MAX(_Generic((_arg) + 0, \
+	MAX(_Generic(Z_ARGIFY(_arg), \
 		float : VA_STACK_ALIGN(double), \
 		double : VA_STACK_ALIGN(double), \
 		long double : VA_STACK_ALIGN(long double), \
 		long long : VA_STACK_ALIGN(long long), \
 		unsigned long long : VA_STACK_ALIGN(long long), \
 		default : \
-			__alignof__((_arg) + 0)), VA_STACK_MIN_ALIGN)
+			__alignof__(Z_ARGIFY(_arg))), VA_STACK_MIN_ALIGN)
 #endif
 
 /** @brief Detect long double variable as a constant expression.
@@ -655,7 +658,7 @@ extern "C" {
 #endif
 #else
 #define Z_CBPRINTF_IS_LONGDOUBLE(x) \
-	_Generic((x) + 0, long double : 1, default : 0)
+	_Generic(Z_ARGIFY(x), long double : 1, default : 0)
 #endif
 
 /** @brief Safely package arguments to a buffer.
@@ -722,18 +725,6 @@ do { \
 #define Z_CBPRINTF_PACK_ARG(arg_idx, arg) \
 	Z_CBPRINTF_PACK_ARG2(arg_idx, _pbuf, _pkg_len, _pkg_offset, _pmax, arg)
 
-/* When using clang additional warning needs to be suppressed since each
- * argument of fmt string is used for sizeof() which results in the warning
- * if argument is a string literal. Suppression is added here instead of
- * the macro which generates the warning to not slow down the compiler.
- */
-#ifdef __clang__
-#define Z_CBPRINTF_SUPPRESS_SIZEOF_ARRAY_DECAY \
-	_Pragma("GCC diagnostic ignored \"-Wsizeof-array-decay\"")
-#else
-#define Z_CBPRINTF_SUPPRESS_SIZEOF_ARRAY_DECAY
-#endif
-
 /* Allocation to avoid using VLA and alloca. Alloc frees space when leaving
  * a function which can lead to increased stack usage if logging is used
  * multiple times. VLA is not always available.
@@ -760,6 +751,17 @@ do { \
 		 _name##_buf32)))
 #endif
 
+/* On Xtensa the cbprintf_package_desc requires
+ * an additional alignment array. This creates an
+ * initial value to hush the compiler when compiling
+ * with C++.
+ */
+#if defined(CONFIG_XTENSA) && defined(__cplusplus)
+#define Z_CBPRINTF_XTENSA_PKG_DESC_PADDING_INITIALIZER .xtensa_padding = { },
+#else
+#define Z_CBPRINTF_XTENSA_PKG_DESC_PADDING_INITIALIZER
+#endif
+
 /** @brief Statically package a formatted string with arguments.
  *
  * @param buf buffer. If null then only length is calculated.
@@ -778,9 +780,6 @@ do { \
 #define Z_CBPRINTF_STATIC_PACKAGE_GENERIC(buf, _inlen, _outlen, _align_offset, \
 					  flags, ... /* fmt, ... */) \
 do { \
-	_Pragma("GCC diagnostic push") \
-	_Pragma("GCC diagnostic ignored \"-Wpointer-arith\"") \
-	Z_CBPRINTF_SUPPRESS_SIZEOF_ARRAY_DECAY \
 	BUILD_ASSERT(!IS_ENABLED(CONFIG_XTENSA) || \
 		     (IS_ENABLED(CONFIG_XTENSA) && \
 		      !((_align_offset) % CBPRINTF_PACKAGE_ALIGNMENT)), \
@@ -852,13 +851,13 @@ do { \
 				.str_cnt = 0, \
 				.ro_str_cnt = _ros_cnt, \
 				.rw_str_cnt = _rws_cnt, \
+				Z_CBPRINTF_XTENSA_PKG_DESC_PADDING_INITIALIZER \
 			} \
 		}; \
 		IF_ENABLED(CONFIG_CBPRINTF_PACKAGE_HEADER_STORE_CREATION_FLAGS, \
 			   (pkg_hdr.desc.pkg_flags = flags)); \
 		*_len_loc = pkg_hdr; \
 	} \
-	_Pragma("GCC diagnostic pop") \
 } while (false)
 
 #if Z_C_GENERIC
diff --git a/include/zephyr/sys/crc.h b/include/zephyr/sys/crc.h
index 7a0c33cf9b5..647d72929b2 100644
--- a/include/zephyr/sys/crc.h
+++ b/include/zephyr/sys/crc.h
@@ -5,6 +5,7 @@
  * Copyright (c) 2015 Runtime Inc
  * Copyright (c) 2018 Google LLC.
  * Copyright (c) 2022 Meta
+ * Copyright (c) 2024 Intercreate, Inc.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -69,6 +70,7 @@ enum crc_type {
 	CRC24_PGP,   /**< Use @ref crc24_pgp */
 	CRC32_C,     /**< Use @ref crc32_c */
 	CRC32_IEEE,  /**< Use @ref crc32_ieee */
+	CRC32_K_4_2, /**< Use @ref crc32_k_4_2_update */
 };
 
 /**
@@ -263,6 +265,32 @@ uint32_t crc32_ieee_update(uint32_t crc, const uint8_t *data, size_t len);
 uint32_t crc32_c(uint32_t crc, const uint8_t *data,
 		 size_t len, bool first_pkt, bool last_pkt);
 
+/**
+ * @brief Update a CRC-32K/4.2 (*op) (Koopman) checksum. This is a good HD=4
+ * checksum up to 2,147,483,615 bits and HD=5/6 up to 6,167 bits.
+ *
+ * Hamming Distance and properties:
+ *
+ * - Polynomial: 0x93a409eb
+ * - reflect-in: false
+ * - initial value (xor-in): provided by caller as crc argument (0xFFFFFFFF is OK)
+ * - reflect-out: false
+ * - xor-out: 0
+ * - HD=4 @ 2,147,483,615 bits
+ * - HD=5 @ 6,167 bits
+ * - HD=6 @ 6,167 bits
+ * - HD=7 @ 148 bits
+ *
+ * Reference: https://users.ece.cmu.edu/~koopman/crc/crc32.html
+ *
+ * @param crc       CRC32 checksum that needs to be updated.
+ * @param data      Pointer to data on which the CRC should be calculated.
+ * @param len       Data length.
+ *
+ * @return CRC32 value.
+ */
+uint32_t crc32_k_4_2_update(uint32_t crc, const uint8_t *data, size_t len);
+
 /**
  * @brief Compute CCITT variant of CRC 8
  *
@@ -378,7 +406,7 @@ uint32_t crc24_pgp_update(uint32_t crc, const uint8_t *data, size_t len);
  * @param type CRC algorithm to use.
  * @param src Input bytes for the computation
  * @param len Length of the input in bytes
- * @param seed Value to seed the CRC with
+ * @param seed Seed or existing CRC value to update
  * @param poly The polynomial to use omitting the leading coefficient
  * @param reflect Should we use reflected/reversed values or not
  * @param first Whether this is the first packet in the stream.
@@ -425,6 +453,8 @@ static inline uint32_t crc_by_type(enum crc_type type, const uint8_t *src, size_
 		return crc32_c(seed, src, len, first, last);
 	case CRC32_IEEE:
 		return crc32_ieee_update(seed, src, len);
+	case CRC32_K_4_2:
+		return crc32_k_4_2_update(seed, src, len);
 	default:
 		break;
 	}
diff --git a/include/zephyr/sys/mutex.h b/include/zephyr/sys/mutex.h
index e34cc90d8d9..533374eb73b 100644
--- a/include/zephyr/sys/mutex.h
+++ b/include/zephyr/sys/mutex.h
@@ -35,7 +35,7 @@ struct sys_mutex {
 
 /**
  * @defgroup user_mutex_apis User mode mutex APIs
- * @ingroup kernel_apis
+ * @ingroup usermode_apis
  * @{
  */
 
diff --git a/include/zephyr/sys/notify.h b/include/zephyr/sys/notify.h
index 3eaeb9b9fc3..6086d2f5be2 100644
--- a/include/zephyr/sys/notify.h
+++ b/include/zephyr/sys/notify.h
@@ -73,7 +73,7 @@ struct sys_notify;
 
 /**
  * @defgroup sys_notify_apis Asynchronous Notification APIs
- * @ingroup kernel_apis
+ * @ingroup os_services
  * @{
  */
 
diff --git a/include/zephyr/sys/onoff.h b/include/zephyr/sys/onoff.h
index 9a3d19aea25..8330bb06fad 100644
--- a/include/zephyr/sys/onoff.h
+++ b/include/zephyr/sys/onoff.h
@@ -18,7 +18,7 @@ extern "C" {
 
 /**
  * @defgroup resource_mgmt_onoff_apis On-Off Service APIs
- * @ingroup kernel_apis
+ * @ingroup os_services
  * @{
  */
 
diff --git a/include/zephyr/sys/p4wq.h b/include/zephyr/sys/p4wq.h
index 8ddb8f0d7a7..967de8c8770 100644
--- a/include/zephyr/sys/p4wq.h
+++ b/include/zephyr/sys/p4wq.h
@@ -18,6 +18,13 @@ struct k_p4wq_work;
  */
 typedef void (*k_p4wq_handler_t)(struct k_p4wq_work *work);
 
+/**
+ * Optional P4 Queue done callback.
+ * Will be called after the memory structure is not used anymore by the p4wq.
+ * If it is not used it must be set to NULL.
+ */
+typedef void (*k_p4wq_done_handler_t)(struct k_p4wq_work *work);
+
 /**
  * @brief P4 Queue Work Item
  *
@@ -74,6 +81,11 @@ struct k_p4wq {
 
 	/* K_P4WQ_* flags above */
 	uint32_t flags;
+
+	/* done handler which is called every time after work was successfully executed
+	 * and k_p4wq_work is not needed by p4wq anymore
+	 */
+	k_p4wq_done_handler_t done_handler;
 };
 
 struct k_p4wq_initparam {
@@ -83,6 +95,7 @@ struct k_p4wq_initparam {
 	struct k_thread *threads;
 	struct z_thread_stack_element *stacks;
 	uint32_t flags;
+	k_p4wq_done_handler_t done_handler;
 };
 
 /**
@@ -95,8 +108,9 @@ struct k_p4wq_initparam {
  * @param name Symbol name of the struct k_p4wq that will be defined
  * @param n_threads Number of threads in the work queue pool
  * @param stack_sz Requested stack size of each thread, in bytes
+ * @param dn_handler Function pointer to handler of type k_p4wq_done_handler_t
  */
-#define K_P4WQ_DEFINE(name, n_threads, stack_sz)			\
+#define K_P4WQ_DEFINE_WITH_DONE_HANDLER(name, n_threads, stack_sz, dn_handler)			\
 	static K_THREAD_STACK_ARRAY_DEFINE(_p4stacks_##name,		\
 					   n_threads, stack_sz);	\
 	static struct k_thread _p4threads_##name[n_threads];		\
@@ -109,8 +123,19 @@ struct k_p4wq_initparam {
 		.stacks = &(_p4stacks_##name[0][0]),			\
 		.queue = &name,						\
 		.flags = 0,						\
+		.done_handler = dn_handler,			\
 	}
 
+/**
+ * @brief Statically initialize a P4 Work Queue
+ *
+ * Same like K_P4WQ_DEFINE_WITH_DONE_HANDLER but without an
+ * optional handler which is called everytime when work is executed
+ * and not used anymore by the p4wq
+ */
+#define K_P4WQ_DEFINE(name, n_threads, stack_sz)			\
+	K_P4WQ_DEFINE_WITH_DONE_HANDLER(name, n_threads, stack_sz, NULL)
+
 /**
  * @brief Statically initialize an array of P4 Work Queues
  *
@@ -122,8 +147,9 @@ struct k_p4wq_initparam {
  * @param n_threads Number of threads and work queues
  * @param stack_sz Requested stack size of each thread, in bytes
  * @param flg Flags
+ * @param dn_handler Function pointer to handler of type k_p4wq_done_handler_t
  */
-#define K_P4WQ_ARRAY_DEFINE(name, n_threads, stack_sz, flg)		\
+#define K_P4WQ_ARRAY_DEFINE_WITH_DONE_HANDLER(name, n_threads, stack_sz, flg, dn_handler) \
 	static K_THREAD_STACK_ARRAY_DEFINE(_p4stacks_##name,		\
 					   n_threads, stack_sz);	\
 	static struct k_thread _p4threads_##name[n_threads];		\
@@ -136,8 +162,19 @@ struct k_p4wq_initparam {
 		.stacks = &(_p4stacks_##name[0][0]),			\
 		.queue = name,						\
 		.flags = K_P4WQ_QUEUE_PER_THREAD | flg,			\
+		.done_handler = dn_handler,							\
 	}
 
+/**
+ * @brief Statically initialize an array of P4 Work Queues
+ *
+ * Same like K_P4WQ_ARRAY_DEFINE_WITH_DONE_HANDLER but without an
+ * optional handler which is called everytime when work is executed
+ * and not used anymore by the p4wq
+ */
+#define K_P4WQ_ARRAY_DEFINE(name, n_threads, stack_sz, flg)		\
+	K_P4WQ_ARRAY_DEFINE_WITH_DONE_HANDLER(name, n_threads, stack_sz, flg, NULL)
+
 /**
  * @brief Initialize P4 Queue
  *
diff --git a/include/zephyr/sys/ring_buffer.h b/include/zephyr/sys/ring_buffer.h
index 6bec33e9e3a..2c75cf1eb84 100644
--- a/include/zephyr/sys/ring_buffer.h
+++ b/include/zephyr/sys/ring_buffer.h
@@ -7,7 +7,6 @@
 #ifndef ZEPHYR_INCLUDE_SYS_RING_BUFFER_H_
 #define ZEPHYR_INCLUDE_SYS_RING_BUFFER_H_
 
-#include <zephyr/kernel.h>
 #include <zephyr/sys/util.h>
 #include <errno.h>
 
@@ -15,16 +14,6 @@
 extern "C" {
 #endif
 
-/** @cond INTERNAL_HIDDEN */
-/* The limit is used by algorithm for distinguishing between empty and full
- * state.
- */
-#define RING_BUFFER_MAX_SIZE 0x80000000U
-
-#define RING_BUFFER_SIZE_ASSERT_MSG \
-	"Size too big"
-/** @endcond */
-
 /**
  * @file
  * @defgroup ring_buffer_apis Ring Buffer APIs
@@ -35,31 +24,61 @@ extern "C" {
  * @{
  */
 
+/** @cond INTERNAL_HIDDEN */
+
+/* The limit is used by algorithm for distinguishing between empty and full
+ * state.
+ */
+#ifdef CONFIG_RING_BUFFER_LARGE
+typedef uint32_t ring_buf_idx_t;
+#define RING_BUFFER_MAX_SIZE (UINT32_MAX / 2)
+#else
+typedef uint16_t ring_buf_idx_t;
+#define RING_BUFFER_MAX_SIZE (UINT16_MAX / 2)
+#endif
+
+#define RING_BUFFER_SIZE_ASSERT_MSG "Size too big"
+
+struct ring_buf_index { ring_buf_idx_t head, tail, base; };
+
+/** @endcond */
+
 /**
  * @brief A structure to represent a ring buffer
  */
 struct ring_buf {
 	/** @cond INTERNAL_HIDDEN */
 	uint8_t *buffer;
-	int32_t put_head;
-	int32_t put_tail;
-	int32_t put_base;
-	int32_t get_head;
-	int32_t get_tail;
-	int32_t get_base;
+	struct ring_buf_index put;
+	struct ring_buf_index get;
 	uint32_t size;
 	/** @endcond */
 };
 
+/** @cond INTERNAL_HIDDEN */
+
+uint32_t ring_buf_area_claim(struct ring_buf *buf, struct ring_buf_index *ring,
+			     uint8_t **data, uint32_t size);
+int ring_buf_area_finish(struct ring_buf *buf, struct ring_buf_index *ring,
+			 uint32_t size);
+
 /**
  * @brief Function to force ring_buf internal states to given value
  *
  * Any value other than 0 makes sense only in validation testing context.
  */
-static inline void ring_buf_internal_reset(struct ring_buf *buf, int32_t value)
+static inline void ring_buf_internal_reset(struct ring_buf *buf, ring_buf_idx_t value)
 {
-	buf->put_head = buf->put_tail = buf->put_base = value;
-	buf->get_head = buf->get_tail = buf->get_base = value;
+	buf->put.head = buf->put.tail = buf->put.base = value;
+	buf->get.head = buf->get.tail = buf->get.base = value;
+}
+
+/** @endcond */
+
+#define RING_BUF_INIT(buf, size8)	\
+{					\
+	.buffer = buf,			\
+	.size = size8,			\
 }
 
 /**
@@ -77,13 +96,10 @@ static inline void ring_buf_internal_reset(struct ring_buf *buf, int32_t value)
  * @param size8 Size of ring buffer (in bytes).
  */
 #define RING_BUF_DECLARE(name, size8) \
-	BUILD_ASSERT(size8 < RING_BUFFER_MAX_SIZE,\
+	BUILD_ASSERT(size8 <= RING_BUFFER_MAX_SIZE,\
 		RING_BUFFER_SIZE_ASSERT_MSG); \
 	static uint8_t __noinit _ring_buffer_data_##name[size8]; \
-	struct ring_buf name = { \
-		.buffer = _ring_buffer_data_##name, \
-		.size = size8 \
-	}
+	struct ring_buf name = RING_BUF_INIT(_ring_buffer_data_##name, size8)
 
 /**
  * @brief Define and initialize an "item based" ring buffer.
@@ -101,7 +117,7 @@ static inline void ring_buf_internal_reset(struct ring_buf *buf, int32_t value)
  * @param size32 Size of ring buffer (in 32-bit words).
  */
 #define RING_BUF_ITEM_DECLARE(name, size32) \
-	BUILD_ASSERT((size32) < RING_BUFFER_MAX_SIZE / 4,\
+	BUILD_ASSERT((size32) <= RING_BUFFER_MAX_SIZE / 4, \
 		RING_BUFFER_SIZE_ASSERT_MSG); \
 	static uint32_t __noinit _ring_buffer_data_##name[size32]; \
 	struct ring_buf name = { \
@@ -158,7 +174,7 @@ static inline void ring_buf_init(struct ring_buf *buf,
 				 uint32_t size,
 				 uint8_t *data)
 {
-	__ASSERT(size < RING_BUFFER_MAX_SIZE, RING_BUFFER_SIZE_ASSERT_MSG);
+	__ASSERT(size <= RING_BUFFER_MAX_SIZE, RING_BUFFER_SIZE_ASSERT_MSG);
 
 	buf->size = size;
 	buf->buffer = data;
@@ -182,7 +198,7 @@ static inline void ring_buf_item_init(struct ring_buf *buf,
 				      uint32_t size,
 				      uint32_t *data)
 {
-	__ASSERT(size < RING_BUFFER_MAX_SIZE / 4, RING_BUFFER_SIZE_ASSERT_MSG);
+	__ASSERT(size <= RING_BUFFER_MAX_SIZE / 4, RING_BUFFER_SIZE_ASSERT_MSG);
 	ring_buf_init(buf, 4 * size, (uint8_t *)data);
 }
 
@@ -193,9 +209,9 @@ static inline void ring_buf_item_init(struct ring_buf *buf,
  *
  * @return true if the ring buffer is empty, or false if not.
  */
-static inline bool ring_buf_is_empty(struct ring_buf *buf)
+static inline bool ring_buf_is_empty(const struct ring_buf *buf)
 {
-	return buf->get_head == buf->put_tail;
+	return buf->get.head == buf->put.tail;
 }
 
 /**
@@ -215,9 +231,11 @@ static inline void ring_buf_reset(struct ring_buf *buf)
  *
  * @return Ring buffer free space (in bytes).
  */
-static inline uint32_t ring_buf_space_get(struct ring_buf *buf)
+static inline uint32_t ring_buf_space_get(const struct ring_buf *buf)
 {
-	return buf->size - (buf->put_head - buf->get_tail);
+	ring_buf_idx_t allocated = buf->put.head - buf->get.tail;
+
+	return buf->size - allocated;
 }
 
 /**
@@ -227,7 +245,7 @@ static inline uint32_t ring_buf_space_get(struct ring_buf *buf)
  *
  * @return Ring buffer free space (in 32-bit words).
  */
-static inline uint32_t ring_buf_item_space_get(struct ring_buf *buf)
+static inline uint32_t ring_buf_item_space_get(const struct ring_buf *buf)
 {
 	return ring_buf_space_get(buf) / 4;
 }
@@ -239,21 +257,23 @@ static inline uint32_t ring_buf_item_space_get(struct ring_buf *buf)
  *
  * @return Ring buffer capacity (in bytes).
  */
-static inline uint32_t ring_buf_capacity_get(struct ring_buf *buf)
+static inline uint32_t ring_buf_capacity_get(const struct ring_buf *buf)
 {
 	return buf->size;
 }
 
 /**
- * @brief Determine used space in a ring buffer.
+ * @brief Determine size of available data in a ring buffer.
  *
  * @param buf Address of ring buffer.
  *
- * @return Ring buffer space used (in bytes).
+ * @return Ring buffer data size (in bytes).
  */
-static inline uint32_t ring_buf_size_get(struct ring_buf *buf)
+static inline uint32_t ring_buf_size_get(const struct ring_buf *buf)
 {
-	return buf->put_tail - buf->get_head;
+	ring_buf_idx_t available = buf->put.tail - buf->get.head;
+
+	return available;
 }
 
 /**
@@ -280,9 +300,13 @@ static inline uint32_t ring_buf_size_get(struct ring_buf *buf)
  * @return Size of allocated buffer which can be smaller than requested if
  *	   there is not enough free space or buffer wraps.
  */
-uint32_t ring_buf_put_claim(struct ring_buf *buf,
-			    uint8_t **data,
-			    uint32_t size);
+static inline uint32_t ring_buf_put_claim(struct ring_buf *buf,
+					  uint8_t **data,
+					  uint32_t size)
+{
+	return ring_buf_area_claim(buf, &buf->put, data,
+				   MIN(size, ring_buf_space_get(buf)));
+}
 
 /**
  * @brief Indicate number of bytes written to allocated buffers.
@@ -306,7 +330,10 @@ uint32_t ring_buf_put_claim(struct ring_buf *buf,
  * @retval 0 Successful operation.
  * @retval -EINVAL Provided @a size exceeds free space in the ring buffer.
  */
-int ring_buf_put_finish(struct ring_buf *buf, uint32_t size);
+static inline int ring_buf_put_finish(struct ring_buf *buf, uint32_t size)
+{
+	return ring_buf_area_finish(buf, &buf->put, size);
+}
 
 /**
  * @brief Write (copy) data to a ring buffer.
@@ -354,9 +381,13 @@ uint32_t ring_buf_put(struct ring_buf *buf, const uint8_t *data, uint32_t size);
  * @return Number of valid bytes in the provided buffer which can be smaller
  *	   than requested if there is not enough free space or buffer wraps.
  */
-uint32_t ring_buf_get_claim(struct ring_buf *buf,
-			    uint8_t **data,
-			    uint32_t size);
+static inline uint32_t ring_buf_get_claim(struct ring_buf *buf,
+					  uint8_t **data,
+					  uint32_t size)
+{
+	return ring_buf_area_claim(buf, &buf->get, data,
+				   MIN(size, ring_buf_size_get(buf)));
+}
 
 /**
  * @brief Indicate number of bytes read from claimed buffer.
@@ -380,7 +411,10 @@ uint32_t ring_buf_get_claim(struct ring_buf *buf,
  * @retval 0 Successful operation.
  * @retval -EINVAL Provided @a size exceeds valid bytes in the ring buffer.
  */
-int ring_buf_get_finish(struct ring_buf *buf, uint32_t size);
+static inline int ring_buf_get_finish(struct ring_buf *buf, uint32_t size)
+{
+	return ring_buf_area_finish(buf, &buf->get, size);
+}
 
 /**
  * @brief Read data from a ring buffer.
diff --git a/include/zephyr/sys/sem.h b/include/zephyr/sys/sem.h
index 73e4d873725..16c6b33ba46 100644
--- a/include/zephyr/sys/sem.h
+++ b/include/zephyr/sys/sem.h
@@ -43,7 +43,7 @@ struct sys_sem {
 
 /**
  * @defgroup user_semaphore_apis User mode semaphore APIs
- * @ingroup kernel_apis
+ * @ingroup usermode_apis
  * @{
  */
 
diff --git a/include/zephyr/sys/sys_heap.h b/include/zephyr/sys/sys_heap.h
index f01bae189e6..86afd6df60f 100644
--- a/include/zephyr/sys/sys_heap.h
+++ b/include/zephyr/sys/sys_heap.h
@@ -73,13 +73,11 @@ struct z_heap_stress_result {
  * @{
  */
 
-#ifdef CONFIG_SYS_HEAP_RUNTIME_STATS
-
 /**
  * @brief Get the runtime statistics of a sys_heap
  *
  * @param heap Pointer to specified sys_heap
- * @param stats_t Pointer to struct to copy statistics into
+ * @param stats Pointer to struct to copy statistics into
  * @return -EINVAL if null pointers, otherwise 0
  */
 int sys_heap_runtime_stats_get(struct sys_heap *heap,
@@ -96,8 +94,6 @@ int sys_heap_runtime_stats_get(struct sys_heap *heap,
  */
 int sys_heap_runtime_stats_reset_max(struct sys_heap *heap);
 
-#endif
-
 /** @brief Initialize sys_heap
  *
  * Initializes a sys_heap struct to manage the specified memory.
@@ -142,6 +138,18 @@ void *sys_heap_alloc(struct sys_heap *heap, size_t bytes);
  */
 void *sys_heap_aligned_alloc(struct sys_heap *heap, size_t align, size_t bytes);
 
+/** @brief Allocate memory from a sys_heap
+ *
+ * This is a wrapper for sys_heap_alloc() whose purpose is to provide the same
+ * function signature as sys_heap_aligned_alloc().
+ *
+ * @param heap Heap from which to allocate
+ * @param align Ignored placeholder
+ * @param bytes Number of bytes requested
+ * @return Pointer to memory the caller can now use
+ */
+void *sys_heap_noalign_alloc(struct sys_heap *heap, size_t align, size_t bytes);
+
 /** @brief Free memory into a sys_heap
  *
  * De-allocates a pointer to memory previously returned from
@@ -171,6 +179,22 @@ void sys_heap_free(struct sys_heap *heap, void *mem);
  *
  * @param heap Heap from which to allocate
  * @param ptr Original pointer returned from a previous allocation
+ * @param bytes Number of bytes requested for the new block
+ * @return Pointer to memory the caller can now use, or NULL
+ */
+void *sys_heap_realloc(struct sys_heap *heap, void *ptr, size_t bytes);
+
+/** @brief Expand the size of an existing allocation
+ *
+ * Behaves in all ways like sys_heap_realloc(), except that the returned
+ * memory (if available) will have a starting address in memory which
+ * is a multiple of the specified power-of-two alignment value in
+ * bytes. In-place expansion will be attempted only if the provided memory
+ * pointer conforms to the specified alignment value otherwise the data will be
+ * moved to a new memory block.
+ *
+ * @param heap Heap from which to allocate
+ * @param ptr Original pointer returned from a previous allocation
  * @param align Alignment in bytes, must be a power of two
  * @param bytes Number of bytes requested for the new block
  * @return Pointer to memory the caller can now use, or NULL
@@ -178,9 +202,6 @@ void sys_heap_free(struct sys_heap *heap, void *mem);
 void *sys_heap_aligned_realloc(struct sys_heap *heap, void *ptr,
 			       size_t align, size_t bytes);
 
-#define sys_heap_realloc(heap, ptr, bytes) \
-	sys_heap_aligned_realloc(heap, ptr, 0, bytes)
-
 /** @brief Return allocated memory size
  *
  * Returns the size, in bytes, of a block returned from a successful
@@ -267,6 +288,24 @@ void sys_heap_stress(void *(*alloc_fn)(void *arg, size_t bytes),
  */
 void sys_heap_print_info(struct sys_heap *heap, bool dump_chunks);
 
+/** @brief Save the heap pointer
+ *
+ * The heap pointer is saved into an internal array, if there is space.
+ *
+ * @param heap Heap to save
+ * @return -EINVAL if null pointer or array is full, otherwise 0
+ */
+int sys_heap_array_save(struct sys_heap *heap);
+
+/** @brief Get the array of saved heap pointers
+ *
+ * Returns the pointer to the array of heap pointers.
+ *
+ * @param heap Heap array
+ * @return -EINVAL if null pointer, otherwise number of saved pointers
+ */
+int sys_heap_array_get(struct sys_heap ***heap);
+
 /**
  * @}
  */
diff --git a/include/zephyr/sys/time_units.h b/include/zephyr/sys/time_units.h
index c02fd012887..8f311d6f899 100644
--- a/include/zephyr/sys/time_units.h
+++ b/include/zephyr/sys/time_units.h
@@ -38,19 +38,25 @@ extern "C" {
  */
 #define SYS_FOREVER_US (-1)
 
+/** @brief System-wide macro to initialize #k_timeout_t with a number of ticks
+ * converted from milliseconds.
+ */
+#define SYS_TIMEOUT_MS_INIT(ms) \
+	Z_TIMEOUT_TICKS_INIT((ms) == SYS_FOREVER_MS ? \
+	K_TICKS_FOREVER : Z_TIMEOUT_MS_TICKS(ms))
+
 /** @brief System-wide macro to convert milliseconds to kernel timeouts
  */
-#define SYS_TIMEOUT_MS(ms) Z_TIMEOUT_TICKS((ms) == SYS_FOREVER_MS ? \
-					   K_TICKS_FOREVER : Z_TIMEOUT_MS_TICKS(ms))
+#define SYS_TIMEOUT_MS(ms) ((k_timeout_t) SYS_TIMEOUT_MS_INIT(ms))
 
 /* Exhaustively enumerated, highly optimized time unit conversion API */
 
 #if defined(CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME)
-__syscall int sys_clock_hw_cycles_per_sec_runtime_get(void);
+__syscall unsigned int sys_clock_hw_cycles_per_sec_runtime_get(void);
 
-static inline int z_impl_sys_clock_hw_cycles_per_sec_runtime_get(void)
+static inline unsigned int z_impl_sys_clock_hw_cycles_per_sec_runtime_get(void)
 {
-	extern int z_clock_hw_cycles_per_sec;
+	extern unsigned int z_clock_hw_cycles_per_sec;
 
 	return z_clock_hw_cycles_per_sec;
 }
@@ -73,7 +79,7 @@ static inline int z_impl_sys_clock_hw_cycles_per_sec_runtime_get(void)
 #if defined(CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME)
 #define sys_clock_hw_cycles_per_sec() sys_clock_hw_cycles_per_sec_runtime_get()
 #else
-#define sys_clock_hw_cycles_per_sec() CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
+#define sys_clock_hw_cycles_per_sec() (uint32_t)CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC
 #endif
 
 /** @internal
@@ -169,10 +175,10 @@ static inline int z_impl_sys_clock_hw_cycles_per_sec_runtime_get(void)
 #define z_tmcvt_int_div_32(__t, __from_hz, __to_hz, __round_up, __round_off) \
 	((uint64_t) (__t) <= 0xffffffffU -				\
 	 z_tmcvt_off_div(__from_hz, __to_hz, __round_up, __round_off) ?	\
-	 ((uint32_t)((__t) +						\
+	 ((uint32_t)(((__t) +						\
 		     z_tmcvt_off_div(__from_hz, __to_hz,		\
 				     __round_up, __round_off)) /	\
-	  z_tmcvt_divisor(__from_hz, __to_hz))				\
+	  z_tmcvt_divisor(__from_hz, __to_hz)))				\
 	 :								\
 	 (uint32_t) (((uint64_t) (__t) +				\
 		      z_tmcvt_off_div(__from_hz, __to_hz,		\
@@ -182,7 +188,7 @@ static inline int z_impl_sys_clock_hw_cycles_per_sec_runtime_get(void)
 
 /* Integer multiplication 32-bit conversion */
 #define z_tmcvt_int_mul_32(__t, __from_hz, __to_hz)	\
-	(uint32_t) (__t)*((__to_hz) / (__from_hz))
+	(uint32_t) ((__t)*((__to_hz) / (__from_hz)))
 
 /* General 32-bit conversion */
 #define z_tmcvt_gen_32(__t, __from_hz, __to_hz, __round_up, __round_off) \
diff --git a/include/zephyr/sys/util.h b/include/zephyr/sys/util.h
index 0e38acb4aae..150bad8737e 100644
--- a/include/zephyr/sys/util.h
+++ b/include/zephyr/sys/util.h
@@ -28,6 +28,7 @@
 #include <zephyr/types.h>
 #include <stddef.h>
 #include <stdint.h>
+#include <string.h>
 
 /** @brief Number of bits that make up a type */
 #define NUM_BITS(t) (sizeof(t) * BITS_PER_BYTE)
@@ -783,6 +784,40 @@ static inline void mem_xor_128(uint8_t dst[16], const uint8_t src1[16], const ui
 	mem_xor_n(dst, src1, src2, 16);
 }
 
+/**
+ * @brief Compare memory areas. The same way as `memcmp` it assume areas to be
+ * the same length
+ *
+ * @param m1 First memory area to compare, cannot be NULL even if length is 0
+ * @param m2 Second memory area to compare, cannot be NULL even if length is 0
+ * @param n First n bytes of @p m1 and @p m2 to compares
+ *
+ * @returns true if the @p n first bytes of @p m1 and @p m2 are the same, else
+ * false
+ */
+static inline bool util_memeq(const void *m1, const void *m2, size_t n)
+{
+	return memcmp(m1, m2, n) == 0;
+}
+
+/**
+ * @brief Compare memory areas and their length
+ *
+ * If the length are 0, return true.
+ *
+ * @param m1 First memory area to compare, cannot be NULL even if length is 0
+ * @param len1 Length of the first memory area to compare
+ * @param m2 Second memory area to compare, cannot be NULL even if length is 0
+ * @param len2 Length of the second memory area to compare
+ *
+ * @returns true if both the length of the memory areas and their content are
+ * equal else false
+ */
+static inline bool util_eq(const void *m1, size_t len1, const void *m2, size_t len2)
+{
+	return len1 == len2 && (m1 == m2 || util_memeq(m1, m2, len1));
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/zephyr/sys/util_macro.h b/include/zephyr/sys/util_macro.h
index 4a3767bf68a..c8901e21454 100644
--- a/include/zephyr/sys/util_macro.h
+++ b/include/zephyr/sys/util_macro.h
@@ -93,6 +93,14 @@ extern "C" {
  */
 #define IS_BIT_MASK(m) IS_SHIFTED_BIT_MASK(m, 0)
 
+/**
+ * @brief Check if bit is set in a value
+ *
+ * @param value Value that contain checked bit
+ * @param bit Bit number
+ */
+#define IS_BIT_SET(value, bit) ((((value) >> (bit)) & (0x1)) != 0)
+
 /** @brief Extract the Least Significant Bit from @p value. */
 #define LSB_GET(value) ((value) & -(value))
 
diff --git a/include/zephyr/sys/uuid.h b/include/zephyr/sys/uuid.h
new file mode 100644
index 00000000000..4283e7e6080
--- /dev/null
+++ b/include/zephyr/sys/uuid.h
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2025, SECO Mind Srl
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_SYS_UUID_H_
+#define ZEPHYR_INCLUDE_SYS_UUID_H_
+
+/**
+ * @file
+ *
+ * @brief Utility functions for the generation and parsing of Universal Unique Identifier.
+ * @details This driver is compliant with RFC9562: https://datatracker.ietf.org/doc/rfc9562/
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @defgroup uuid UUID
+ * @since 4.0
+ * @version 0.1.0
+ * @ingroup utilities
+ * @{
+ */
+
+/** @brief Number of bytes in the binary representation of a UUID. */
+#define UUID_SIZE 16U
+
+/** @brief Length of the UUID canonical string representation, including the NULL terminator. */
+#define UUID_STR_LEN 37U
+
+/** @brief Length of the UUID base64 string representation, including the NULL terminator. */
+#define UUID_BASE64_LEN 25U
+
+/**
+ * @brief Length of the UUID base64 URL and filename safe string representation, including the
+ * NULL terminator.
+ */
+#define UUID_BASE64URL_LEN 23U
+
+/** @brief Binary representation of a UUID. */
+struct uuid {
+	/** @cond INTERNAL_HIDDEN */
+	uint8_t val[UUID_SIZE];
+	/** @endcond */
+};
+
+/**
+ * @brief Generate a UUIDv4.
+ *
+ * @param out The UUID where the result will be written.
+ *
+ * @retval 0 The UUID has been correctly generated and stored in @p out
+ * @retval -EINVAL @p out is not acceptable
+ */
+int uuid_generate_v4(struct uuid *out);
+
+/**
+ * @brief Generate a UUIDv5.
+ *
+ * @details This function computes a deterministic UUID starting from a namespace UUID and binary
+ * data.
+ *
+ * @param namespace A pointer to an UUID to be used as namespace.
+ * @param data A pointer to the data that will be hashed to produce the UUID.
+ * @param data_size The size of the data buffer.
+ * @param out The UUID where the result will be written.
+ *
+ * @retval 0 The UUID has been correctly generated and stored in @p out
+ * @retval -EINVAL @p out is not acceptable
+ * @retval -ENOMEM Memory allocation failed
+ * @retval -ENOTSUP mbedTLS returned an unrecognized error
+ */
+int uuid_generate_v5(const struct uuid *namespace, const void *data, size_t data_size,
+		     struct uuid *out);
+
+/**
+ * @brief Copy an UUID into another UUID.
+ *
+ * @param data Input data to copy.
+ * @param out Destination for the copy.
+ *
+ * @retval 0 The UUID has been correctly copied in @p dst
+ * @retval -EINVAL @p dst is not acceptable
+ */
+int uuid_copy(const struct uuid *data, struct uuid *out);
+
+/**
+ * @brief Create a uuid_t from a binary (big-endian) formatted UUID.
+ *
+ * @param data The buffer where the binary UUID is stored in a big-endian order.
+ * @param out The UUID where the result will be written.
+ *
+ * @retval 0 The UUID has been correctly parsed and stored in @p out
+ * @retval -EINVAL @p data or @p out are not acceptable
+ */
+int uuid_from_buffer(const uint8_t data[UUID_SIZE], struct uuid *out);
+
+/**
+ * @brief Parse a UUID from its canonical (RFC9562) string representation.
+ *
+ * @param data A pointer to the string to be parsed.
+ * @param out The UUID where the result will be written.
+ *
+ * @retval 0 The UUID has been correctly parsed and stored in @p out
+ * @retval -EINVAL @p input or @p out are not acceptable
+ */
+int uuid_from_string(const char data[UUID_STR_LEN], struct uuid *out);
+
+/**
+ * @brief Create a uuid_t from a binary (big-endian) formatted UUID.
+ *
+ * @param data The input UUID to store in the buffer.
+ * @param out The buffer where the binary UUID is stored in a big-endian order.
+ *
+ * @retval 0 The UUID has been correctly parsed and stored in @p buff
+ * @retval -EINVAL @p buff is not acceptable
+ */
+int uuid_to_buffer(const struct uuid *data, uint8_t out[UUID_SIZE]);
+
+/**
+ * @brief Convert a UUID to its canonical (RFC9562) string representation.
+ *
+ * @param data The UUID to convert to string.
+ * @param out A pointer to a previously allocated buffer where the result will be written.
+ *
+ * @retval 0 The UUID has been converted and written in @p out
+ * @retval -EINVAL @p out is not acceptable
+ */
+int uuid_to_string(const struct uuid *data, char out[UUID_STR_LEN]);
+
+/**
+ * @brief Convert a UUID to its base 64 (RFC 3548, RFC 4648) string representation.
+ *
+ * @param data The UUID to convert to string.
+ * @param out A pointer to a previously allocated buffer where the result will be written.
+ *
+ * @retval 0 The UUID has been converted and written in @p out
+ * @retval -EINVAL @p out is not acceptable
+ */
+int uuid_to_base64(const struct uuid *data, char out[UUID_BASE64_LEN]);
+
+/**
+ * @brief Convert a UUID to its base 64 (RFC 4648 sec. 5) URL and filename safe string
+ * representation.
+ *
+ * @param data The UUID to convert to string.
+ * @param out A pointer to a previously allocated buffer where the result will be written.
+ *
+ * @retval 0 The UUID has been converted and written in @p out
+ * @retval -EINVAL @p out is not acceptable
+ */
+int uuid_to_base64url(const struct uuid *data, char out[UUID_BASE64URL_LEN]);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_INCLUDE_SYS_UUID_H_ */
diff --git a/include/zephyr/sys_clock.h b/include/zephyr/sys_clock.h
index 8d24f0317eb..6c3589a5102 100644
--- a/include/zephyr/sys_clock.h
+++ b/include/zephyr/sys_clock.h
@@ -79,7 +79,7 @@ typedef struct {
  */
 #define K_TIMEOUT_EQ(a, b) ((a).ticks == (b).ticks)
 
-/** number of nanoseconds per micorsecond */
+/** number of nanoseconds per microsecond */
 #define NSEC_PER_USEC 1000U
 
 /** number of nanoseconds per millisecond */
@@ -115,12 +115,14 @@ typedef struct {
 /** @} */
 
 /** @cond INTERNAL_HIDDEN */
-#define Z_TIMEOUT_NO_WAIT ((k_timeout_t) {0})
+#define Z_TIMEOUT_NO_WAIT_INIT {0}
+#define Z_TIMEOUT_NO_WAIT ((k_timeout_t) Z_TIMEOUT_NO_WAIT_INIT)
 #if defined(__cplusplus) && ((__cplusplus - 0) < 202002L)
-#define Z_TIMEOUT_TICKS(t) ((k_timeout_t) { (t) })
+#define Z_TIMEOUT_TICKS_INIT(t) { (t) }
 #else
-#define Z_TIMEOUT_TICKS(t) ((k_timeout_t) { .ticks = (t) })
+#define Z_TIMEOUT_TICKS_INIT(t) { .ticks = (t) }
 #endif
+#define Z_TIMEOUT_TICKS(t) ((k_timeout_t) Z_TIMEOUT_TICKS_INIT(t))
 #define Z_FOREVER Z_TIMEOUT_TICKS(K_TICKS_FOREVER)
 
 #ifdef CONFIG_TIMEOUT_64BIT
@@ -159,11 +161,12 @@ typedef struct {
 
 /** @endcond */
 
+#ifndef CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
 #if defined(CONFIG_SYS_CLOCK_EXISTS) && \
 	(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC == 0)
 #error "SYS_CLOCK_HW_CYCLES_PER_SEC must be non-zero!"
 #endif
-
+#endif /* CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME */
 
 /* kernel clocks */
 
diff --git a/include/zephyr/task_wdt/task_wdt.h b/include/zephyr/task_wdt/task_wdt.h
index 91cc9798505..dfeede4963a 100644
--- a/include/zephyr/task_wdt/task_wdt.h
+++ b/include/zephyr/task_wdt/task_wdt.h
@@ -102,6 +102,28 @@ int task_wdt_delete(int channel_id);
  */
 int task_wdt_feed(int channel_id);
 
+/**
+ * @brief Pause all channels before changing system power mode.
+ *
+ * Stop the internal timer and feed the hardware watchdog a last time
+ * (if enabled). It is expected that the system enters a low-power
+ * mode quite fast after this call.
+ *
+ * @note To pause the hardware watchdog (if this is supported),
+ * enable @kconfig{CONFIG_TASK_WDT_HW_FALLBACK_PAUSE_IN_SLEEP} in your
+ * configuration.
+ */
+void task_wdt_suspend(void);
+
+/**
+ * @brief Resume all channels execution.
+ *
+ * Resume the internal timer and feed all channels. Also feed the hardware
+ * watchdog (if enabled) to let enough time to the application to resume
+ * feeding the channels by itself.
+ */
+void task_wdt_resume(void);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/include/zephyr/toolchain.h b/include/zephyr/toolchain.h
index f8df4915736..6fca58a7b2f 100644
--- a/include/zephyr/toolchain.h
+++ b/include/zephyr/toolchain.h
@@ -44,6 +44,8 @@
 #include <zephyr/toolchain/mwdt.h>
 #elif defined(__ARMCOMPILER_VERSION)
 #include <zephyr/toolchain/armclang.h>
+#elif defined(__IAR_SYSTEMS_ICC__)
+#include <zephyr/toolchain/iar.h>
 #elif defined(__llvm__) || (defined(_LINKER) && defined(__LLD_LINKER_CMD__))
 #include <zephyr/toolchain/llvm.h>
 #elif defined(__GNUC__) || (defined(_LINKER) && defined(__GCC_LINKER_CMD__))
@@ -124,25 +126,196 @@
 #endif
 
 /**
- * @def TOOLCHAIN_IGNORE_WSHADOW_BEGIN
- * @brief Begin of block to ignore -Wshadow.
+ * @def TOOLCHAIN_PRAGMA
+ * @brief Helper for using pragma in macros.
+ */
+#ifdef TOOLCHAIN_HAS_PRAGMA_DIAG
+#define TOOLCHAIN_PRAGMA(x) _Pragma(#x)
+#else
+#define TOOLCHAIN_PRAGMA(x)
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER
+ * @brief Toolchain-specific warning for taking the address of a packed member.
  *
- * To be used inside another macro.
- * Only for toolchain supporting _Pragma("GCC diagnostic ...").
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER
+#define TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_ARRAY_BOUNDS
+ * @brief Toolchain-specific warning for array bounds violations.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_ARRAY_BOUNDS
+#define TOOLCHAIN_WARNING_ARRAY_BOUNDS
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_ATTRIBUTES
+ * @brief Toolchain-specific warning for unknown attributes.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_ATTRIBUTES
+#define TOOLCHAIN_WARNING_ATTRIBUTES
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_DELETE_NON_VIRTUAL_DTOR
+ * @brief Toolchain-specific warning for deleting a pointer to an object
+ * with a non-virtual destructor.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_DELETE_NON_VIRTUAL_DTOR
+#define TOOLCHAIN_WARNING_DELETE_NON_VIRTUAL_DTOR
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_EXTRA
+ * @brief Toolchain-specific warning for extra warnings.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_EXTRA
+#define TOOLCHAIN_WARNING_EXTRA
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_NONNULL
+ * @brief Toolchain-specific warning for null pointer arguments to functions marked with "nonnull".
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_NONNULL
+#define TOOLCHAIN_WARNING_NONNULL
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_POINTER_ARITH
+ * @brief Toolchain-specific warning for pointer arithmetic.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_POINTER_ARITH
+#define TOOLCHAIN_WARNING_POINTER_ARITH
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_SHADOW
+ * @brief Toolchain-specific warning for shadow variables.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_SHADOW
+#define TOOLCHAIN_WARNING_SHADOW
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_UNUSED_LABEL
+ * @brief Toolchain-specific warning for unused labels.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_UNUSED_LABEL
+#define TOOLCHAIN_WARNING_UNUSED_LABEL
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_UNUSED_VARIABLE
+ * @brief Toolchain-specific warning for unused variables.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_UNUSED_VARIABLE
+#define TOOLCHAIN_WARNING_UNUSED_VARIABLE
+#endif
+
+/**
+ * @def TOOLCHAIN_DISABLE_WARNING
+ * @brief Disable the specified compiler warning for all compilers.
+ */
+#ifndef TOOLCHAIN_DISABLE_WARNING
+#define TOOLCHAIN_DISABLE_WARNING(warning)
+#endif
+
+/**
+ * @def TOOLCHAIN_ENABLE_WARNING
+ * @brief Re-enable the specified compiler warning for all compilers.
+ *
+ * Can only be used after a call to @ref TOOLCHAIN_DISABLE_WARNING.
+ */
+#ifndef TOOLCHAIN_ENABLE_WARNING
+#define TOOLCHAIN_ENABLE_WARNING(warning)
+#endif
+
+/**
+ * @def TOOLCHAIN_DISABLE_CLANG_WARNING
+ * @brief Disable the specified compiler warning for clang.
+ */
+#ifndef TOOLCHAIN_DISABLE_CLANG_WARNING
+#define TOOLCHAIN_DISABLE_CLANG_WARNING(warning)
+#endif
+
+/**
+ * @def TOOLCHAIN_ENABLE_CLANG_WARNING
+ * @brief Re-enable the specified compiler warning for clang.
+ *
+ * Can only be used after a call to @ref TOOLCHAIN_DISABLE_CLANG_WARNING.
+ */
+#ifndef TOOLCHAIN_ENABLE_CLANG_WARNING
+#define TOOLCHAIN_ENABLE_CLANG_WARNING(warning)
+#endif
+
+/**
+ * @def TOOLCHAIN_DISABLE_GCC_WARNING
+ * @brief Disable the specified compiler warning for gcc.
+ */
+#ifndef TOOLCHAIN_DISABLE_GCC_WARNING
+#define TOOLCHAIN_DISABLE_GCC_WARNING(warning)
+#endif
+
+/**
+ * @def TOOLCHAIN_ENABLE_GCC_WARNING
+ * @brief Re-enable the specified compiler warning for gcc.
+ *
+ * Can only be used after a call to @ref TOOLCHAIN_DISABLE_GCC_WARNING.
+ */
+#ifndef TOOLCHAIN_ENABLE_GCC_WARNING
+#define TOOLCHAIN_ENABLE_GCC_WARNING(warning)
+#endif
+
+/**
+ * @def TOOLCHAIN_DISABLE_IAR_WARNING
+ * @brief Disable the specified compiler warning for IAR compilers.
  */
-#ifndef TOOLCHAIN_IGNORE_WSHADOW_BEGIN
-#define TOOLCHAIN_IGNORE_WSHADOW_BEGIN
+#ifndef TOOLCHAIN_DISABLE_IAR_WARNING
+#define TOOLCHAIN_DISABLE_IAR_WARNING(warning)
 #endif
 
 /**
- * @def TOOLCHAIN_IGNORE_WSHADOW_END
- * @brief End of block to ignore -Wshadow.
+ * @def TOOLCHAIN_ENABLE_IAR_WARNING
+ * @brief Re-enable the specified compiler warning for IAR compilers.
  *
- * To be used inside another macro.
- * Only for toolchain supporting _Pragma("GCC diagnostic ...").
+ * Can only be used after a call to @ref TOOLCHAIN_DISABLE_IAR_WARNING.
  */
-#ifndef TOOLCHAIN_IGNORE_WSHADOW_END
-#define TOOLCHAIN_IGNORE_WSHADOW_END
+#ifndef TOOLCHAIN_ENABLE_IAR_WARNING
+#define TOOLCHAIN_ENABLE_IAR_WARNING(warning)
 #endif
 
 /*
diff --git a/include/zephyr/toolchain/common.h b/include/zephyr/toolchain/common.h
index c84328365fd..ff9291d88d7 100644
--- a/include/zephyr/toolchain/common.h
+++ b/include/zephyr/toolchain/common.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2010-2014 Wind River Systems, Inc.
+ * Copyright (c) 2025 Siemens AG
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -60,6 +61,37 @@
   #define SECTION .section
 #endif
 
+/*
+ * General directive for assembly code, to align the following symbol, in bytes.
+ *
+ * Example:
+ *
+ *    ALIGN(4)
+ *    test_symbol:
+ *
+ * 'test_symbol' will get aligned to 4 bytes.
+ */
+
+#if defined(_ASMLANGUAGE) && !defined(_LINKER)
+
+  #if defined(CONFIG_X86) || defined(CONFIG_ARM) || defined(CONFIG_ARM64) || \
+	defined(CONFIG_NIOS2) || defined(CONFIG_RISCV) || \
+	defined(CONFIG_XTENSA) || defined(CONFIG_MIPS) || \
+	defined(CONFIG_ARCH_POSIX)
+    #define   ALIGN(x)    .balign   x
+  #elif defined(CONFIG_ARC)
+    /* .align assembler directive is supported by all ARC toolchains and it is
+     * implemented in the same way across ARC toolchains.
+     */
+    #define   ALIGN(x)    .align    x
+  #elif defined(CONFIG_SPARC)
+    #define   ALIGN(x)    .align    x
+  #else
+    #error Architecture unsupported
+  #endif
+
+#endif /* defined(_ASMLANGUAGE) && !defined(_LINKER) */
+
 /*
  * If the project is being built for speed (i.e. not for minimum size) then
  * align functions and branches in executable sections to improve performance.
diff --git a/include/zephyr/toolchain/gcc.h b/include/zephyr/toolchain/gcc.h
index bb55d50a858..3d63cda20c0 100644
--- a/include/zephyr/toolchain/gcc.h
+++ b/include/zephyr/toolchain/gcc.h
@@ -103,6 +103,10 @@
 #define FUNC_ALIAS(real_func, new_alias, return_type) \
 	return_type new_alias() ALIAS_OF(real_func)
 
+#if TOOLCHAIN_GCC_VERSION < 40500
+#define __builtin_unreachable() __builtin_trap()
+#endif
+
 #if defined(CONFIG_ARCH_POSIX) && !defined(_ASMLANGUAGE)
 #include <zephyr/arch/posix/posix_trace.h>
 
@@ -675,12 +679,36 @@ do {                                                                    \
 #define FUNC_NO_STACK_PROTECTOR
 #endif
 
-#define TOOLCHAIN_IGNORE_WSHADOW_BEGIN \
-	_Pragma("GCC diagnostic push") \
-	_Pragma("GCC diagnostic ignored \"-Wshadow\"")
+#endif /* !_LINKER */
+
+#define TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER "-Waddress-of-packed-member"
+#define TOOLCHAIN_WARNING_ARRAY_BOUNDS             "-Warray-bounds"
+#define TOOLCHAIN_WARNING_ATTRIBUTES               "-Wattributes"
+#define TOOLCHAIN_WARNING_DELETE_NON_VIRTUAL_DTOR  "-Wdelete-non-virtual-dtor"
+#define TOOLCHAIN_WARNING_EXTRA                    "-Wextra"
+#define TOOLCHAIN_WARNING_NONNULL                  "-Wnonnull"
+#define TOOLCHAIN_WARNING_SHADOW                   "-Wshadow"
+#define TOOLCHAIN_WARNING_UNUSED_LABEL             "-Wunused-label"
+#define TOOLCHAIN_WARNING_UNUSED_VARIABLE          "-Wunused-variable"
 
-#define TOOLCHAIN_IGNORE_WSHADOW_END \
-	_Pragma("GCC diagnostic pop")
+/* GCC-specific warnings that aren't in clang. */
+#if defined(__GNUC__) && !defined(__clang__)
+#define TOOLCHAIN_WARNING_POINTER_ARITH     "-Wpointer-arith"
+#define TOOLCHAIN_WARNING_STRINGOP_OVERREAD "-Wstringop-overread"
+#endif
+
+#define _TOOLCHAIN_DISABLE_WARNING(compiler, warning)                                              \
+	TOOLCHAIN_PRAGMA(compiler diagnostic push)                                                 \
+	TOOLCHAIN_PRAGMA(compiler diagnostic ignored warning)
+
+#define _TOOLCHAIN_ENABLE_WARNING(compiler, warning) TOOLCHAIN_PRAGMA(compiler diagnostic pop)
+
+#define TOOLCHAIN_DISABLE_WARNING(warning) _TOOLCHAIN_DISABLE_WARNING(GCC, warning)
+#define TOOLCHAIN_ENABLE_WARNING(warning) _TOOLCHAIN_ENABLE_WARNING(GCC, warning)
+
+#if defined(__GNUC__) && !defined(__clang__)
+#define TOOLCHAIN_DISABLE_GCC_WARNING(warning) _TOOLCHAIN_DISABLE_WARNING(GCC, warning)
+#define TOOLCHAIN_ENABLE_GCC_WARNING(warning)  _TOOLCHAIN_ENABLE_WARNING(GCC, warning)
+#endif
 
-#endif /* !_LINKER */
 #endif /* ZEPHYR_INCLUDE_TOOLCHAIN_GCC_H_ */
diff --git a/include/zephyr/toolchain/iar.h b/include/zephyr/toolchain/iar.h
new file mode 100644
index 00000000000..916a6ed7724
--- /dev/null
+++ b/include/zephyr/toolchain/iar.h
@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2025 IAR Systems AB
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_TOOLCHAIN_IAR_H_
+#define ZEPHYR_INCLUDE_TOOLCHAIN_IAR_H_
+
+#define TOOLCHAIN_HAS_PRAGMA_DIAG
+
+#define _TOOLCHAIN_DISABLE_WARNING(warning) TOOLCHAIN_PRAGMA(diag_suppress = warning)
+#define _TOOLCHAIN_ENABLE_WARNING(warning)  TOOLCHAIN_PRAGMA(diag_default = warning)
+
+#define TOOLCHAIN_DISABLE_WARNING(warning) _TOOLCHAIN_DISABLE_WARNING(warning)
+#define TOOLCHAIN_ENABLE_WARNING(warning)  _TOOLCHAIN_ENABLE_WARNING(warning)
+
+#define TOOLCHAIN_DISABLE_IAR_WARNING(warning) _TOOLCHAIN_DISABLE_WARNING(warning)
+#define TOOLCHAIN_ENABLE_IAR_WARNING(warning)  _TOOLCHAIN_ENABLE_WARNING(warning)
+
+/* Generic warnings */
+
+
+/**
+ * @def TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER
+ * @brief Toolchain-specific warning for taking the address of a packed member.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER
+#define TOOLCHAIN_WARNING_ADDRESS_OF_PACKED_MEMBER Pe001
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_ARRAY_BOUNDS
+ * @brief Toolchain-specific warning for array bounds violations.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_ARRAY_BOUNDS
+#define TOOLCHAIN_WARNING_ARRAY_BOUNDS Pe001
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_ATTRIBUTES
+ * @brief Toolchain-specific warning for unknown attributes.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_ATTRIBUTES
+#define TOOLCHAIN_WARNING_ATTRIBUTES Pe1097
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_DELETE_NON_VIRTUAL_DTOR
+ * @brief Toolchain-specific warning for deleting a pointer to an object
+ * with a non-virtual destructor.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_DELETE_NON_VIRTUAL_DTOR
+#define TOOLCHAIN_WARNING_DELETE_NON_VIRTUAL_DTOR Pe001
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_EXTRA
+ * @brief Toolchain-specific warning for extra warnings.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_EXTRA
+#define TOOLCHAIN_WARNING_EXTRA Pe001
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_NONNULL
+ * @brief Toolchain-specific warning for null pointer arguments to functions marked with "nonnull".
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_NONNULL
+#define TOOLCHAIN_WARNING_NONNULL Pe001
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_POINTER_ARITH
+ * @brief Toolchain-specific warning for pointer arithmetic.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_POINTER_ARITH
+#define TOOLCHAIN_WARNING_POINTER_ARITH Pe1143
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_SHADOW
+ * @brief Toolchain-specific warning for shadow variables.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_SHADOW
+#define TOOLCHAIN_WARNING_SHADOW Pe001
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_UNUSED_LABEL
+ * @brief Toolchain-specific warning for unused labels.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_UNUSED_LABEL
+#define TOOLCHAIN_WARNING_UNUSED_LABEL Pe001
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_UNUSED_VARIABLE
+ * @brief Toolchain-specific warning for unused variables.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#define TOOLCHAIN_WARNING_UNUSED_VARIABLE Pe001
+
+#define TOOLCHAIN_WARNING_UNUSED_FUNCTION Pe001
+
+#ifdef __ICCARM__
+#include "iar/iccarm.h"
+#endif
+#ifdef __ICCRISCV__
+#include "iar/iccriscv.h"
+#endif
+
+#endif /* ZEPHYR_INCLUDE_TOOLCHAIN_ICCARM_H_ */
diff --git a/include/zephyr/toolchain/iar/iar_missing_defs.h b/include/zephyr/toolchain/iar/iar_missing_defs.h
new file mode 100644
index 00000000000..44541adaccd
--- /dev/null
+++ b/include/zephyr/toolchain/iar/iar_missing_defs.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2025 IAR Systems AB
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Basic macro definitions that gcc and clang provide on their own
+ * but that iccarm lacks. Only those that Zephyr requires are provided here.
+ */
+
+#ifndef ZEPHYR_INCLUDE_TOOLCHAIN_ICCARM_MISSING_DEFS_H_
+#define ZEPHYR_INCLUDE_TOOLCHAIN_ICCARM_MISSING_DEFS_H_
+
+ /* We need to define NULL with a parenthesis around _NULL
+  * otherwise the DEBRACE macros won't work correctly
+  */
+
+#undef NULL
+#define NULL   (_NULL)
+
+#if defined(__IAR_SYSTEMS_ICC__)
+#ifndef __CHAR_BIT__
+#define __CHAR_BIT__ __CHAR_BITS__
+#endif
+#define __SCHAR_MAX__ __SIGNED_CHAR_MAX__
+
+#define __INT_MAX__    __SIGNED_INT_MAX__
+#define __INT_WIDTH__ (__INT_SIZE__*8)
+#define __SIZEOF_INT__ __INT_SIZE__
+
+#define __SHRT_MAX__     __SIGNED_SHORT_MAX__
+#define __SHRT_WIDTH__  (__SHORT_SIZE__*8)
+#define __SIZEOF_SHORT__ __SHORT_SIZE__
+
+#define __LONG_MAX__    __SIGNED_LONG_MAX__
+#define __LONG_WIDTH__ (__LONG_SIZE__*8)
+#define __SIZEOF_LONG__ __LONG_SIZE__
+
+#define __LONG_LONG_MAX__    __SIGNED_LONG_LONG_MAX__
+#define __LONG_LONG_WIDTH__ (__LONG_LONG_SIZE__*8)
+#define __SIZEOF_LONG_LONG__ __LONG_LONG_SIZE__
+
+#define __INTMAX_MAX__     __INTMAX_T_MAX__
+#define __SIZEOF_INTMAX__  sizeof(__INTMAX_T_TYPE__)
+#define __INTMAX_WIDTH__   (__SIZEOF_INTMAX__*8)
+#define __UINTMAX_MAX__    __UINTMAX_T_MAX__
+#define __SIZEOF_UINTMAX__ sizeof(__UINTMAX_T_TYPE__)
+#define __UINTMAX_WIDTH__  (__SIZEOF_UINTMAX__*8)
+
+#define __INTPTR_MAX__     __INTPTR_T_MAX__
+#define __INTPTR_TYPE__    __INTPTR_T_TYPE__
+#define __INTPTR_WIDTH__  (__INTPTR_T_SIZE__*8)
+#define __SIZEOF_POINTER__ __INTPTR_T_SIZE__
+
+#define __PTRDIFF_MAX__      __PTRDIFF_T_MAX__
+#define __PTRDIFF_WIDTH__   (__PTRDIFF_T_SIZE__*8)
+#define __SIZEOF_PTRDIFF_T__ __PTRDIFF_T_SIZE__
+
+#define __UINTPTR_MAX__  __UINTPTR_T_MAX__
+#define __UINTPTR_TYPE__ __UINTPTR_T_TYPE__
+
+/*
+ * ICCARM already defines __SIZE_T_MAX__ as "unsigned int" but there is no way
+ * to safeguard that here with preprocessor equality.
+ */
+
+#define __SIZE_TYPE__   __SIZE_T_TYPE__
+#define __SIZE_MAX__    __SIZE_T_MAX__
+#define __SIZE_WIDTH__ ((__SIZEOF_SIZE_T__)*8)
+/* #define __SIZEOF_SIZE_T__ 4 */
+
+/*
+ * The following defines are inferred from the ICCARM provided defines
+ * already tested above.
+ */
+
+
+#define __INT8_MAX__  __INT8_T_MAX__
+#define __INT8_TYPE__ __INT8_T_TYPE__
+
+#define __UINT8_MAX__  __UINT8_T_MAX__
+#define __UINT8_TYPE__ __UINT8_T_TYPE__
+
+#define __INT16_MAX__  __INT16_T_MAX__
+#define __INT16_TYPE__ __INT16_T_TYPE__
+
+#define __UINT16_MAX__  __UINT16_T_MAX__
+#define __UINT16_TYPE__ __UINT16_T_TYPE__
+
+#define __INT32_MAX__  __INT32_T_MAX__
+#define __INT32_TYPE__ __INT32_T_TYPE__
+
+#define __UINT32_MAX__  __UINT32_T_MAX__
+#define __UINT32_TYPE__ __UINT32_T_TYPE__
+
+#define __INT64_MAX__  __INT64_T_MAX__
+#define __INT64_TYPE__ __INT64_T_TYPE__
+
+#define __UINT64_MAX__  __UINT64_T_MAX__
+#define __UINT64_TYPE__ __UINT64_T_TYPE__
+
+#define __INT_FAST8_MAX__    __INT_FAST8_T_MAX__
+#define __INT_FAST8_TYPE__   __INT_FAST8_T_TYPE__
+#define __INT_FAST8_WIDTH__ (__INT_FAST8_T_SIZE__*8)
+
+#define __INT_FAST16_MAX__    __INT_FAST16_T_MAX__
+#define __INT_FAST16_TYPE__   __INT_FAST16_T_TYPE__
+#define __INT_FAST16_WIDTH__ (__INT_FAST16_T_SIZE__*8)
+
+#define __INT_FAST32_MAX__    __INT_FAST32_T_MAX__
+#define __INT_FAST32_TYPE__   __INT_FAST32_T_TYPE__
+#define __INT_FAST32_WIDTH__ (__INT_FAST32_T_SIZE__*8)
+
+#define __INT_FAST64_MAX__    __INT_FAST64_T_MAX__
+#define __INT_FAST64_TYPE__   __INT_FAST64_T_TYPE__
+#define __INT_FAST64_WIDTH__ (__INT_FAST64_T_SIZE__*8)
+
+#define __INT_LEAST8_MAX__    __INT_LEAST8_T_MAX__
+#define __INT_LEAST8_TYPE__   __INT_LEAST8_T_TYPE__
+#define __INT_LEAST8_WIDTH__ (__INT_LEAST8_T_SIZE__*8)
+
+#define __INT_LEAST16_MAX__    __INT_LEAST16_T_MAX__
+#define __INT_LEAST16_TYPE__   __INT_LEAST16_T_TYPE__
+#define __INT_LEAST16_WIDTH__ (__INT_LEAST16_T_SIZE__*8)
+
+#define __INT_LEAST32_MAX__    __INT_LEAST32_T_MAX__
+#define __INT_LEAST32_TYPE__   __INT_LEAST32_T_TYPE__
+#define __INT_LEAST32_WIDTH__ (__INT_LEAST32_T_SIZE__*8)
+
+#define __INT_LEAST64_MAX__    __INT_LEAST64_T_MAX__
+#define __INT_LEAST64_TYPE__   __INT_LEAST64_T_TYPE__
+#define __INT_LEAST64_WIDTH__ (__INT_LEAST64_T_SIZE__*8)
+
+#define __UINT_FAST8_MAX__  __UINT_FAST8_T_MAX__
+#define __UINT_FAST8_TYPE__ __UINT_FAST8_T_TYPE__
+
+#define __UINT_FAST16_MAX__  __UINT_FAST16_T_MAX__
+#define __UINT_FAST16_TYPE__ __UINT_FAST16_T_TYPE__
+
+#define __UINT_FAST32_MAX__  __UINT_FAST32_T_MAX__
+#define __UINT_FAST32_TYPE__ __UINT_FAST32_T_TYPE__
+
+#define __UINT_FAST64_MAX__  __UINT_FAST64_T_MAX__
+#define __UINT_FAST64_TYPE__ __UINT_FAST64_T_TYPE__
+
+#define __UINT_LEAST8_MAX__  __UINT_LEAST8_T_MAX__
+#define __UINT_LEAST8_TYPE__ __UINT_LEAST8_T_TYPE__
+
+#define __UINT_LEAST16_MAX__  __UINT_LEAST16_T_MAX__
+#define __UINT_LEAST16_TYPE__ __UINT_LEAST16_T_TYPE__
+
+#define __UINT_LEAST32_MAX__  __UINT_LEAST32_T_MAX__
+#define __UINT_LEAST32_TYPE__ __UINT_LEAST32_T_TYPE__
+
+#define __UINT_LEAST64_MAX__  __UINT_LEAST64_T_MAX__
+#define __UINT_LEAST64_TYPE__ __UINT_LEAST64_T_TYPE__
+
+#endif /* __IAR_SYSTEMS_ICC__ */
+
+#endif
diff --git a/include/zephyr/toolchain/iar/iccarm.h b/include/zephyr/toolchain/iar/iccarm.h
new file mode 100644
index 00000000000..cc791023329
--- /dev/null
+++ b/include/zephyr/toolchain/iar/iccarm.h
@@ -0,0 +1,456 @@
+/*
+ * Copyright (c) 2025 IAR Systems AB
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_TOOLCHAIN_ICCARM_H_
+#define ZEPHYR_INCLUDE_TOOLCHAIN_ICCARM_H_
+
+/**
+ * @file
+ * @brief ICCARM toolchain abstraction
+ *
+ * Macros to abstract compiler capabilities for ICCARM toolchain.
+ */
+
+/* ICCARM supports its own #pragma diag_{warning,default,error,warning}. */
+/* #define TOOLCHAIN_HAS_PRAGMA_DIAG 0 */
+
+#define TOOLCHAIN_HAS_C_GENERIC 1
+
+#define TOOLCHAIN_HAS_C_AUTO_TYPE 1
+
+/* #define TOOLCHAIN_HAS_ZLA 1 */
+
+/*
+ * IAR do not define __BYTE_ORDER__, so it must be manually
+ * detected and defined using arch-specific definitions.
+ */
+
+#ifndef _LINKER
+
+#ifndef __ORDER_BIG_ENDIAN__
+#define __ORDER_BIG_ENDIAN__            (1)
+#endif /* __ORDER_BIG_ENDIAN__ */
+
+#ifndef __ORDER_LITTLE_ENDIAN__
+#define __ORDER_LITTLE_ENDIAN__         (2)
+#endif /* __ORDER_LITTLE_ENDIAN__ */
+
+#ifndef __ORDER_PDP_ENDIAN__
+#define __ORDER_PDP_ENDIAN__            (3)
+#endif /* __ORDER_PDP_ENDIAN__ */
+
+#ifndef __BYTE_ORDER__
+
+#if __LITTLE_ENDIAN__ == 1
+#define __BYTE_ORDER__                  __ORDER_LITTLE_ENDIAN__
+#else
+#define __BYTE_ORDER__                  __ORDER_BIG_ENDIAN__
+#endif /* __LITTLE_ENDIAN__ == 1 */
+
+#endif /* __BYTE_ORDER__ */
+
+
+#if defined(__cplusplus) && (__cplusplus >= 201103L)
+#define BUILD_ASSERT(EXPR, MSG...)  static_assert(EXPR, "" MSG)
+#elif defined(__ICCARM__)
+#define BUILD_ASSERT(EXPR, MSG...) _Static_assert(EXPR, "" MSG)
+#endif
+
+/* Zephyr makes use of __ATOMIC_SEQ_CST */
+#ifdef __STDC_NO_ATOMICS__
+#ifndef __ATOMIC_SEQ_CST
+#define __MEMORY_ORDER_SEQ_CST__ 5
+#endif
+#endif
+#ifndef __ATOMIC_SEQ_CST
+#define __ATOMIC_SEQ_CST __MEMORY_ORDER_SEQ_CST__
+#endif
+
+/* By default, restrict is recognized in Standard C
+ * __restrict is always recognized
+ */
+#define ZRESTRICT __restrict
+
+#include <zephyr/toolchain/common.h>
+#include <stdbool.h>
+
+#define ALIAS_OF(of) __attribute__((alias(#of)))
+
+#define FUNC_ALIAS(real_func, new_alias, return_type) \
+	return_type new_alias() ALIAS_OF(real_func)
+
+#define CODE_UNREACHABLE __builtin_unreachable()
+#define FUNC_NORETURN    __attribute__((__noreturn__))
+
+#define _NODATA_SECTION(segment)  __attribute__((section(#segment)))
+
+/* Unaligned access */
+#define UNALIGNED_GET(p)						\
+__extension__ ({							\
+	struct  __attribute__((__packed__)) {				\
+		__typeof__(*(p)) __v;					\
+	} *__p = (__typeof__(__p)) (p);					\
+	__p->__v;							\
+})
+
+#define UNALIGNED_PUT(v, p)                                             \
+do {                                                                    \
+	struct __attribute__((__packed__)) {                            \
+		__typeof__(*p) __v;                                     \
+	} *__p = (__typeof__(__p)) (p);                                 \
+	__p->__v = (v);                                               \
+} while (false)
+
+
+/* Double indirection to ensure section names are expanded before
+ * stringification
+ */
+#define __GENERIC_SECTION(segment) __attribute__((section(STRINGIFY(segment))))
+#define Z_GENERIC_SECTION(segment) __GENERIC_SECTION(segment)
+
+#define __GENERIC_DOT_SECTION(segment) \
+	__attribute__((section("." STRINGIFY(segment))))
+#define Z_GENERIC_DOT_SECTION(segment) __GENERIC_DOT_SECTION(segment)
+
+#define ___in_section(a, b, c) \
+	__attribute__((section("." Z_STRINGIFY(a)			\
+				"." Z_STRINGIFY(b)			\
+				"." Z_STRINGIFY(c))))
+#define __in_section(a, b, c) ___in_section(a, b, c)
+
+#define __in_section_unique(seg) ___in_section(seg, __FILE__, __COUNTER__)
+
+#define __in_section_unique_named(seg, name) \
+	___in_section(seg, __FILE__, name)
+
+/* When using XIP, using '__ramfunc' places a function into RAM instead
+ * of FLASH. Make sure '__ramfunc' is defined only when
+ * CONFIG_ARCH_HAS_RAMFUNC_SUPPORT is defined, so that the compiler can
+ * report an error if '__ramfunc' is used but the architecture does not
+ * support it.
+ */
+#if !defined(CONFIG_XIP)
+#define __ramfunc
+#elif defined(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT)
+/* Use this instead of the IAR keyword __ramfunc to make sure it
+ * ends up in the correct section.
+ */
+#define __ramfunc __attribute__((noinline, section(".ramfunc")))
+#endif /* !CONFIG_XIP */
+
+/* TG-WG: ICCARM does not support __fallthrough */
+#define __fallthrough  [[fallthrough]]
+
+#ifndef __packed
+#define __packed        __attribute__((__packed__))
+#endif
+
+#ifndef __aligned
+#define __aligned(x)	__attribute__((__aligned__(x)))
+#endif
+
+#ifndef __noinline
+#define __noinline        __attribute__((noinline))
+#endif
+
+#if defined(__cplusplus)
+#define __alignof(x) alignof(x)
+#else
+#define __alignof(x) _Alignof(x)
+#endif
+
+#define __may_alias     __attribute__((__may_alias__))
+
+#ifndef __printf_like
+/*
+ * The Zephyr stdint convention enforces int32_t = int, int64_t = long long,
+ * and intptr_t = long so that short string format length modifiers can be
+ * used universally across ILP32 and LP64 architectures. Without that it
+ * is possible for ILP32 toolchains to have int32_t = long and intptr_t = int
+ * clashing with the Zephyr convention and generating pointless warnings
+ * as they're still the same size. Inhibit the format argument type
+ * validation in that case and let the other configs do it.
+ */
+#define __printf_like(f, a)
+#endif
+
+#define __used		__attribute__((__used__))
+#define __unused	__attribute__((__unused__))
+#define __maybe_unused  __attribute__((__unused__))
+
+#ifndef __deprecated
+#define __deprecated	__attribute__((deprecated))
+#endif
+
+#define FUNC_NO_STACK_PROTECTOR _Pragma("no_stack_protect")
+
+#ifndef __attribute_const__
+#if __VER__ > 0x09000000
+#define __attribute_const__ __attribute__((const))
+#else
+#define __attribute_const__
+#endif
+#endif
+
+#ifndef __must_check
+/* #warning "The attribute __warn_unused_result is not supported in ICCARM". */
+#define __must_check
+/* #define __must_check __attribute__((warn_unused_result)) */
+#endif
+
+#define __PRAGMA(...) _Pragma(#__VA_ARGS__)
+#define ARG_UNUSED(x) (void)(x)
+
+#define likely(x)   (__builtin_expect((bool)!!(x), true) != 0L)
+#define unlikely(x) (__builtin_expect((bool)!!(x), false) != 0L)
+#define POPCOUNT(x) __builtin_popcount(x)
+
+#ifndef __no_optimization
+#define __no_optimization __PRAGMA(optimize = none)
+#endif
+
+#ifndef __attribute_nonnull
+ #define __attribute_nonnull(...) __attribute__((nonnull(__VA_ARGS__)))
+#endif
+
+/* __weak is an ICCARM built-in, but it doesn't work in all positions */
+/* the Zephyr uses it so we replace it with an attribute((weak))      */
+#define __weak __attribute__((__weak__))
+
+/* Builtins */
+
+#include <intrinsics.h>
+
+/*
+ * Be *very* careful with these. You cannot filter out __DEPRECATED_MACRO with
+ * -wno-deprecated, which has implications for -Werror.
+ */
+
+
+/*
+ * Expands to nothing and generates a warning. Used like
+ *
+ *   #define FOO __WARN("Please use BAR instead") ...
+ *
+ * The warning points to the location where the macro is expanded.
+ */
+#define __WARN(s) __PRAGMA(message = #s)
+#define __WARN1(s) __PRAGMA(message = #s)
+
+/* Generic message */
+#ifndef __DEPRECATED_MACRO
+#define __DEPRECATED_MACRO __WARN("Macro is deprecated")
+#endif
+
+/* These macros allow having ARM asm functions callable from thumb */
+
+#if defined(_ASMLANGUAGE)
+
+#if defined(CONFIG_ASSEMBLER_ISA_THUMB2)
+#define FUNC_CODE() .code 32
+#define FUNC_INSTR(a)
+/* '.syntax unified' is a gcc-ism used in thumb-2 asm files */
+#define _ASM_FILE_PROLOGUE .text; .syntax unified; .thumb
+#else
+#define FUNC_CODE()
+#define FUNC_INSTR(a)
+#define _ASM_FILE_PROLOGUE .text; .code 32
+#endif /* CONFIG_ASSEMBLER_ISA_THUMB2 */
+
+/*
+ * These macros are used to declare assembly language symbols that need
+ * to be typed properly(func or data) to be visible to the OMF tool.
+ * So that the build tool could mark them as an entry point to be linked
+ * correctly.  This is an elfism. Use #if 0 for a.out.
+ */
+
+/* This is not implemented yet for IAR */
+#define GTEXT(sym)
+#define GDATA(sym)
+#define WTEXT(sym)
+#define WDATA(sym)
+
+#define SECTION_VAR(sect, sym)
+#define SECTION_FUNC(sect, sym)
+#define SECTION_SUBSEC_FUNC(sect, subsec, sym)
+
+#endif /* _ASMLANGUAGE */
+
+
+/*
+ * These macros generate absolute symbols for IAR
+ */
+
+/* create an extern reference to the absolute symbol */
+
+#define GEN_OFFSET_EXTERN(name) extern const char name[]
+
+#define GEN_ABS_SYM_BEGIN(name) \
+	EXTERN_C void name(void); \
+	void name(void)         \
+	{
+
+#define GEN_ABS_SYM_END }
+
+/*
+ * Note that GEN_ABSOLUTE_SYM(), depending on the architecture
+ * and toolchain, may restrict the range of values permitted
+ * for assignment to the named symbol.
+ */
+#define GEN_ABSOLUTE_SYM(name, value) \
+	__PRAGMA(public_equ = #name, (unsigned int)value)
+
+/*
+ * GEN_ABSOLUTE_SYM_KCONFIG() is outputted by the build system
+ * to generate named symbol/value pairs for kconfigs.
+ */
+#define GEN_ABSOLUTE_SYM_KCONFIG(name, value) \
+	__PRAGMA(public_equ = #name, (unsigned int)value)
+
+#define compiler_barrier() do { \
+	__asm volatile("" ::: "memory"); \
+} while (false)
+
+/** @brief Return larger value of two provided expressions.
+ *
+ * Macro ensures that expressions are evaluated only once.
+ *
+ * @note Macro has limited usage compared to the standard macro as it cannot be
+ *	 used:
+ *	 - to generate constant integer, e.g. __aligned(Z_MAX(4,5))
+ *	 - static variable, e.g. array like static uint8_t array[Z_MAX(...)];
+ */
+#define Z_MAX(a, b) ({ \
+		/* random suffix to avoid naming conflict */ \
+		__typeof__(a) _value_a_ = (a); \
+		__typeof__(b) _value_b_ = (b); \
+		_value_a_ > _value_b_ ? _value_a_ : _value_b_; \
+	})
+
+/** @brief Return smaller value of two provided expressions.
+ *
+ * Macro ensures that expressions are evaluated only once. See @ref Z_MAX for
+ * macro limitations.
+ */
+#define Z_MIN(a, b) ({ \
+		/* random suffix to avoid naming conflict */ \
+		__typeof__(a) _value_a_ = (a); \
+		__typeof__(b) _value_b_ = (b); \
+		_value_a_ < _value_b_ ? _value_a_ : _value_b_; \
+	})
+
+/** @brief Return a value clamped to a given range.
+ *
+ * Macro ensures that expressions are evaluated only once. See @ref Z_MAX for
+ * macro limitations.
+ */
+#define Z_CLAMP(val, low, high) ({                                             \
+		/* random suffix to avoid naming conflict */                   \
+		__typeof__(val) _value_val_ = (val);                           \
+		__typeof__(low) _value_low_ = (low);                           \
+		__typeof__(high) _value_high_ = (high);                        \
+		(_value_val_ < _value_low_)  ? _value_low_ :                   \
+		(_value_val_ > _value_high_) ? _value_high_ :                  \
+					       _value_val_;                    \
+	})
+
+/**
+ * @brief Calculate power of two ceiling for some nonzero value
+ *
+ * @param x Nonzero unsigned long value
+ * @return X rounded up to the next power of two
+ */
+#define Z_POW2_CEIL(x) \
+	((x) <= 2UL ? (x) : (1UL << (8 * sizeof(long) - __builtin_clzl((x) - 1))))
+
+/**
+ * @brief Check whether or not a value is a power of 2
+ *
+ * @param x The value to check
+ * @return true if x is a power of 2, false otherwise
+ */
+#define Z_IS_POW2(x) (((x) != 0) && (((x) & ((x)-1)) == 0))
+
+#ifndef __INT8_C
+#define __INT8_C(x)	x
+#endif
+
+#ifndef INT8_C
+#define INT8_C(x)	__INT8_C(x)
+#endif
+
+#ifndef __UINT8_C
+#define __UINT8_C(x)	x ## U
+#endif
+
+#ifndef UINT8_C
+#define UINT8_C(x)	__UINT8_C(x)
+#endif
+
+#ifndef __INT16_C
+#define __INT16_C(x)	x
+#endif
+
+#ifndef INT16_C
+#define INT16_C(x)	__INT16_C(x)
+#endif
+
+#ifndef __UINT16_C
+#define __UINT16_C(x)	x ## U
+#endif
+
+#ifndef UINT16_C
+#define UINT16_C(x)	__UINT16_C(x)
+#endif
+
+#ifndef __INT32_C
+#define __INT32_C(x)	x
+#endif
+
+#ifndef INT32_C
+#define INT32_C(x)	__INT32_C(x)
+#endif
+
+#ifndef __UINT32_C
+#define __UINT32_C(x)	x ## U
+#endif
+
+#ifndef UINT32_C
+#define UINT32_C(x)	__UINT32_C(x)
+#endif
+
+#ifndef __INT64_C
+#define __INT64_C(x)	x ## LL
+#endif
+
+#ifndef INT64_C
+#define INT64_C(x)	__INT64_C(x)
+#endif
+
+#ifndef __UINT64_C
+#define __UINT64_C(x)	x ## ULL
+#endif
+
+#ifndef UINT64_C
+#define UINT64_C(x)	__UINT64_C(x)
+#endif
+
+/* Convenience macros */
+#undef _GLUE_B
+#undef _GLUE
+#define _GLUE_B(x, y) x##y
+#define _GLUE(x, y)   _GLUE_B(x, y)
+
+#ifndef INTMAX_C
+#define INTMAX_C(x)  _GLUE(x, __INTMAX_C_SUFFIX__)
+#endif
+
+#ifndef UINTMAX_C
+#define UINTMAX_C(x) _GLUE(x, __UINTMAX_C_SUFFIX__)
+#endif
+
+#endif /* !_LINKER */
+#endif /* ZEPHYR_INCLUDE_TOOLCHAIN_ICCARM_H_ */
diff --git a/include/zephyr/toolchain/llvm.h b/include/zephyr/toolchain/llvm.h
index a8956807305..158ff083a38 100644
--- a/include/zephyr/toolchain/llvm.h
+++ b/include/zephyr/toolchain/llvm.h
@@ -30,12 +30,24 @@
 
 #include <zephyr/toolchain/gcc.h>
 
+#define TOOLCHAIN_WARNING_SIZEOF_ARRAY_DECAY            "-Wsizeof-array-decay"
+#define TOOLCHAIN_WARNING_UNNEEDED_INTERNAL_DECLARATION "-Wunneeded-internal-declaration"
+
+#define TOOLCHAIN_DISABLE_CLANG_WARNING(warning) _TOOLCHAIN_DISABLE_WARNING(clang, warning)
+#define TOOLCHAIN_ENABLE_CLANG_WARNING(warning)  _TOOLCHAIN_ENABLE_WARNING(clang, warning)
+
 /*
  * Provide these definitions only when minimal libc is used.
  * Avoid collision with defines from include/zephyr/toolchain/zephyr_stdint.h
  */
 #ifdef CONFIG_MINIMAL_LIBC
 
+/*
+ * Predefined __INTN_C/__UINTN_C macros are provided by clang starting in version 20.1.
+ * Avoid redefining these macros if a sufficiently modern clang is being used.
+ */
+#if TOOLCHAIN_CLANG_VERSION < 200100
+
 #define __int_c(v, suffix) v ## suffix
 #define int_c(v, suffix) __int_c(v, suffix)
 #define uint_c(v, suffix) __int_c(v ## U, suffix)
@@ -127,6 +139,8 @@
 #define __INTMAX_C(x)	int_c(x, __INTMAX_C_SUFFIX__)
 #define __UINTMAX_C(x)	int_c(x, __UINTMAX_C_SUFFIX__)
 
+#endif /* TOOLCHAIN_CLANG_VERSION < 200100 */
+
 #endif /* CONFIG_MINIMAL_LIBC */
 
 #endif /* ZEPHYR_INCLUDE_TOOLCHAIN_LLVM_H_ */
diff --git a/include/zephyr/toolchain/zephyr_stdint.h b/include/zephyr/toolchain/zephyr_stdint.h
index f9a44e4a25f..3cd4defbf6f 100644
--- a/include/zephyr/toolchain/zephyr_stdint.h
+++ b/include/zephyr/toolchain/zephyr_stdint.h
@@ -16,6 +16,33 @@
  * common expectations and usage.
  */
 
+/*
+ * If the compiler does not define __SIZEOF_INT__ deduce it from __INT_MAX__
+ * or INT_MAX.
+ */
+#if !defined(__SIZEOF_INT__)
+
+#if defined(__INT_MAX__)
+/* GCC >= 3.3.0 has __<val>__ implicitly defined. */
+#define __Z_INT_MAX __INT_MAX__
+#else
+/* Fall back to POSIX versions from <limits.h> */
+#define __Z_INT_MAX INT_MAX
+#include <limits.h>
+#endif
+
+#if __Z_INT_MAX == 0x7fff
+#define __SIZEOF_INT__ 2
+#elif __Z_INT_MAX == 0x7fffffffL
+#define __SIZEOF_INT__ 4
+#elif __Z_INT_MAX > 0x7fffffffL
+#define __SIZEOF_INT__ 8
+#endif
+
+#undef __Z_INT_MAX
+
+#endif
+
 #if __SIZEOF_INT__ != 4
 #error "unexpected int width"
 #endif
diff --git a/include/zephyr/tracing/tracing.h b/include/zephyr/tracing/tracing.h
index fd4a0d634ed..13b27cdbddc 100644
--- a/include/zephyr/tracing/tracing.h
+++ b/include/zephyr/tracing/tracing.h
@@ -1558,8 +1558,80 @@
 /**
  * @brief Trace initialization of Pipe
  * @param pipe Pipe object
+ * @param buffer data buffer
+ * @param size data buffer size
  */
-#define sys_port_trace_k_pipe_init(pipe)
+#define sys_port_trace_k_pipe_init(pipe, buffer, size)
+
+/**
+ * @brief Trace Pipe reset entry
+ * @param pipe Pipe object
+ */
+#define sys_port_trace_k_pipe_reset_enter(pipe)
+
+/**
+ * @brief Trace Pipe reset exit
+ * @param pipe Pipe object
+ */
+#define sys_port_trace_k_pipe_reset_exit(pipe)
+
+/**
+ * @brief Trace Pipe close entry
+ * @param pipe Pipe object
+ */
+#define sys_port_trace_k_pipe_close_enter(pipe)
+
+/**
+ * @brief Trace Pipe close exit
+ * @param pipe Pipe object
+ */
+#define sys_port_trace_k_pipe_close_exit(pipe)
+
+/**
+ * @brief Trace Pipe write attempt entry
+ * @param pipe Pipe object
+ * @param data pointer to data
+ * @param len length of data
+ * @param timeout Timeout period
+ */
+#define sys_port_trace_k_pipe_write_enter(pipe, data, len, timeout)
+
+/**
+ * @brief Trace Pipe write attempt blocking
+ * @param pipe Pipe object
+ * @param timeout Timeout period
+ */
+#define sys_port_trace_k_pipe_write_blocking(pipe, timeout)
+
+/**
+ * @brief Trace Pipe write attempt outcome
+ * @param pipe Pipe object
+ * @param ret Return value
+ */
+#define sys_port_trace_k_pipe_write_exit(pipe, ret)
+
+/**
+ * @brief Trace Pipe read attempt entry
+ * @param pipe Pipe object
+ * @param data Pointer to data
+ * @param len Length of data
+ * @param timeout Timeout period
+ */
+#define sys_port_trace_k_pipe_read_enter(pipe, data, len, timeout)
+
+/**
+ * @brief Trace Pipe read attempt blocking
+ * @param pipe Pipe object
+ * @param timeout Timeout period
+ */
+#define sys_port_trace_k_pipe_read_blocking(pipe, timeout)
+
+/**
+ * @brief Trace Pipe read attempt outcome
+ * @param pipe Pipe object
+ * @param ret Return value
+ */
+#define sys_port_trace_k_pipe_read_exit(pipe, ret)
 
 /**
  * @brief Trace Pipe cleanup entry
@@ -1681,7 +1753,7 @@
  * @param h Heap object
  * @param timeout Timeout period
  */
-#define sys_port_trace_k_heap_aligned_alloc_blocking(h, timeout)
+#define sys_port_trace_k_heap_alloc_helper_blocking(h, timeout)
 
 /**
  * @brief Trace Heap align alloc attempt outcome
@@ -2646,6 +2718,12 @@
 
 #if defined(CONFIG_PERCEPIO_TRACERECORDER)
 #include "tracing_tracerecorder.h"
+
+/**
+ * @brief Called when the cpu exits the idle state
+ */
+void sys_trace_idle_exit(void);
+
 #else
 /**
  * @brief Called when entering an ISR
@@ -2666,6 +2744,12 @@ void sys_trace_isr_exit_to_scheduler(void);
  * @brief Called when the cpu enters the idle state
  */
 void sys_trace_idle(void);
+
+/**
+ * @brief Called when the cpu exits the idle state
+ */
+void sys_trace_idle_exit(void);
+
 #endif /* CONFIG_PERCEPIO_TRACERECORDER */
 
 /**
diff --git a/include/zephyr/tracing/tracking.h b/include/zephyr/tracing/tracking.h
index 2b2429c83f7..d6e24ee46a8 100644
--- a/include/zephyr/tracing/tracking.h
+++ b/include/zephyr/tracing/tracking.h
@@ -73,8 +73,8 @@ extern struct k_event *_track_list_k_event;
 #define sys_port_track_k_queue_cancel_wait(queue)
 #define sys_port_track_k_queue_init(queue) \
 	sys_track_k_queue_init(queue)
-#define sys_port_track_k_pipe_init(pipe) \
-	sys_track_k_pipe_init(pipe)
+#define sys_port_track_k_pipe_init(pipe, buffer, buffer_size) \
+	sys_track_k_pipe_init(pipe, buffer, buffer_size)
 #define sys_port_track_k_condvar_init(condvar, ret)
 #define sys_port_track_k_stack_init(stack) \
 	sys_track_k_stack_init(stack)
@@ -105,7 +105,7 @@ void sys_track_k_mutex_init(struct k_mutex *mutex);
 void sys_track_k_stack_init(struct k_stack *stack);
 void sys_track_k_msgq_init(struct k_msgq *msgq);
 void sys_track_k_mbox_init(struct k_mbox *mbox);
-void sys_track_k_pipe_init(struct k_pipe *pipe);
+void sys_track_k_pipe_init(struct k_pipe *pipe, void *buffer, size_t size);
 void sys_track_k_queue_init(struct k_queue *queue);
 void sys_track_k_event_init(struct k_event *event);
 void sys_track_socket_init(int sock, int family, int type, int proto);
@@ -132,7 +132,7 @@ void sys_track_socket_init(int sock, int family, int type, int proto);
 #define sys_port_track_k_queue_peek_head(queue, ret)
 #define sys_port_track_k_queue_cancel_wait(queue)
 #define sys_port_track_k_queue_init(queue)
-#define sys_port_track_k_pipe_init(pipe)
+#define sys_port_track_k_pipe_init(pipe, buffer, buffer_size)
 #define sys_port_track_k_condvar_init(condvar, ret)
 #define sys_port_track_k_stack_init(stack)
 #define sys_port_track_k_thread_name_set(thread, ret)
diff --git a/include/zephyr/types.h b/include/zephyr/types.h
index 145957da059..b1a9a182fb3 100644
--- a/include/zephyr/types.h
+++ b/include/zephyr/types.h
@@ -48,11 +48,26 @@ typedef union {
 #endif /* Z_THREAD_LOCAL */
 
 #ifdef __cplusplus
-/* Zephyr requires an int main(void) signature with C linkage for the application main if present */
+
+#if (!__STDC_HOSTED__)
+/*
+ * Zephyr requires an int main(void) signature with C linkage for the
+ * application main if present. gcc, and clang when building in 'hosted' mode
+ * will correctly assume this. But, when building freestanding, clang does not
+ * treat main() specially, and by default name mangles its symbol, which
+ * results in the linker not linking from the kernel init code into this
+ * name mangled app main().
+ *
+ * At the same time, according to the C++ standard Section 6.9.3.1 of
+ * ISO/IEC 14882:2024, main cannot be explicitly declared to have "C" linkage.
+ * This restriction is relaxed for freestanding code, as main is not treated
+ * specially in these circumstances.
+ * Therefore, let's include the prototype when we are not building the code as
+ * freestanding/not-hosted.
+ */
 extern int main(void);
 #endif
 
-#ifdef __cplusplus
 }
 #endif
 
diff --git a/include/zephyr/usb/class/usbd_dfu.h b/include/zephyr/usb/class/usbd_dfu.h
new file mode 100644
index 00000000000..ab8207fd5ba
--- /dev/null
+++ b/include/zephyr/usb/class/usbd_dfu.h
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief USB Device Firmware Upgrade (DFU) public header
+ *
+ * Header exposes API for registering DFU images.
+ */
+
+#ifndef ZEPHYR_INCLUDE_USB_CLASS_USBD_DFU_H
+#define ZEPHYR_INCLUDE_USB_CLASS_USBD_DFU_H
+
+#include <stdint.h>
+
+/* DFU Class Subclass */
+#define USB_DFU_SUBCLASS		0x01
+
+/* DFU Class runtime Protocol */
+#define USB_DFU_PROTOCOL_RUNTIME	0x01
+
+/* DFU Class DFU mode Protocol */
+#define USB_DFU_PROTOCOL_DFU		0x02
+
+/* DFU Class Specific Requests */
+#define USB_DFU_REQ_DETACH			0x00
+#define USB_DFU_REQ_DNLOAD			0x01
+#define USB_DFU_REQ_UPLOAD			0x02
+#define USB_DFU_REQ_GETSTATUS			0x03
+#define USB_DFU_REQ_CLRSTATUS			0x04
+#define USB_DFU_REQ_GETSTATE			0x05
+#define USB_DFU_REQ_ABORT			0x06
+
+/* Run-Time DFU Functional Descriptor */
+struct usb_dfu_descriptor {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bmAttributes;
+	uint16_t wDetachTimeOut;
+	uint16_t wTransferSize;
+	uint16_t bcdDFUVersion;
+} __packed;
+
+/* DFU Functional Descriptor Type */
+#define USB_DESC_DFU_FUNCTIONAL			0x21
+
+/* DFU attributes DFU Functional Descriptor */
+#define USB_DFU_ATTR_WILL_DETACH		BIT(3)
+#define USB_DFU_ATTR_MANIFESTATION_TOLERANT	BIT(2)
+#define USB_DFU_ATTR_CAN_UPLOAD			BIT(1)
+#define USB_DFU_ATTR_CAN_DNLOAD			BIT(0)
+
+/* DFU Specification release */
+#define USB_DFU_VERSION				0x0110
+
+/* DFU device status */
+enum usb_dfu_status {
+	ERR_OK			= 0x00,
+	ERR_TARGET		= 0x01,
+	ERR_FILE		= 0x02,
+	ERR_WRITE		= 0x03,
+	ERR_ERASE		= 0x04,
+	ERR_CHECK_ERASED	= 0x05,
+	ERR_PROG		= 0x06,
+	ERR_VERIFY		= 0x07,
+	ERR_ADDRESS		= 0x08,
+	ERR_NOTDONE		= 0x09,
+	ERR_FIRMWARE		= 0x0A,
+	ERR_VENDOR		= 0x0B,
+	ERR_USBR		= 0x0C,
+	ERR_POR			= 0x0D,
+	ERR_UNKNOWN		= 0x0E,
+	ERR_STALLEDPKT		= 0x0F,
+};
+
+/* DFU device states */
+enum usb_dfu_state {
+	APP_IDLE		= 0,
+	APP_DETACH		= 1,
+	DFU_IDLE		= 2,
+	DFU_DNLOAD_SYNC		= 3,
+	DFU_DNBUSY		= 4,
+	DFU_DNLOAD_IDLE		= 5,
+	DFU_MANIFEST_SYNC	= 6,
+	DFU_MANIFEST		= 7,
+	DFU_MANIFEST_WAIT_RST	= 8,
+	DFU_UPLOAD_IDLE		= 9,
+	DFU_ERROR		= 10,
+	DFU_STATE_MAX		= 11,
+};
+
+struct usbd_dfu_image {
+	const char *name;
+	struct usb_if_descriptor *const if_desc;
+	void *const priv;
+	struct usbd_desc_node *const sd_nd;
+	bool (*next_cb)(void *const priv,
+			const enum usb_dfu_state state, const enum usb_dfu_state next);
+	int (*read_cb)(void *const priv,
+		       const uint32_t block, const uint16_t size,
+		       uint8_t buf[static CONFIG_USBD_DFU_TRANSFER_SIZE]);
+	int (*write_cb)(void *const priv,
+			const uint32_t block, const uint16_t size,
+			const uint8_t buf[static CONFIG_USBD_DFU_TRANSFER_SIZE]);
+};
+
+/**
+ * @brief USB DFU device update API
+ * @defgroup usbd_dfu USB DFU device update API
+ * @ingroup usb
+ * @{
+ */
+
+/**
+ * @brief Define USB DFU image
+ *
+ * Use this macro to create USB DFU image
+ *
+ * The callbacks must be in form:
+ *
+ * @code{.c}
+ * static int read(void *const priv, const uint32_t block, const uint16_t size,
+ *                 uint8_t buf[static CONFIG_USBD_DFU_TRANSFER_SIZE])
+ * {
+ *         int len;
+ *
+ *         return len;
+ * }
+ *
+ * static int write(void *const priv, const uint32_t block, const uint16_t size,
+ *                  const uint8_t buf[static CONFIG_USBD_DFU_TRANSFER_SIZE])
+ * {
+ *         return 0;
+ * }
+ *
+ * static bool next(void *const priv,
+ *                  const enum usb_dfu_state state, const enum usb_dfu_state next)
+ * {
+ *         return true;
+ * }
+ * @endcode
+ *
+ * @param id     Identifier by which the linker sorts registered images
+ * @param iname  Image name as used in interface descriptor
+ * @param iread  Image read callback
+ * @param iwrite Image write callback
+ * @param inext  Notify/confirm next state
+ */
+#define USBD_DFU_DEFINE_IMG(id, iname, ipriv, iread, iwrite, inext)			\
+	static __noinit struct usb_if_descriptor usbd_dfu_iface_##id;			\
+											\
+	USBD_DESC_STRING_DEFINE(usbd_dfu_str_##id, iname, USBD_DUT_STRING_INTERFACE);	\
+											\
+	static const STRUCT_SECTION_ITERABLE(usbd_dfu_image, usbd_dfu_image_##id) = {	\
+		.name = iname,								\
+		.if_desc = &usbd_dfu_iface_##id,					\
+		.priv = ipriv,								\
+		.sd_nd = &usbd_dfu_str_##id,						\
+		.read_cb = iread,							\
+		.write_cb = iwrite,							\
+		.next_cb = inext,							\
+	}
+
+/**
+ * @}
+ */
+#endif /* ZEPHYR_INCLUDE_USB_CLASS_USBD_DFU_H */
diff --git a/include/zephyr/usb/class/usbd_hid.h b/include/zephyr/usb/class/usbd_hid.h
index db2d55b6cbc..3772bb970d2 100644
--- a/include/zephyr/usb/class/usbd_hid.h
+++ b/include/zephyr/usb/class/usbd_hid.h
@@ -25,7 +25,7 @@ extern "C" {
  * @defgroup usbd_hid_device USBD HID device API
  * @ingroup usb
  * @since 3.7
- * @version 0.1.0
+ * @version 0.1.1
  * @{
  */
 
@@ -159,7 +159,8 @@ struct hid_device_ops {
 	 * If the device does not use the callback, hid_device_submit_report()
 	 * will be processed synchronously.
 	 */
-	void (*input_report_done)(const struct device *dev);
+	void (*input_report_done)(const struct device *dev,
+				  const uint8_t *const report);
 
 	/**
 	 * New output report callback. Callback will only be called for reports
diff --git a/include/zephyr/usb/class/usbd_midi2.h b/include/zephyr/usb/class/usbd_midi2.h
new file mode 100644
index 00000000000..e0354e17b90
--- /dev/null
+++ b/include/zephyr/usb/class/usbd_midi2.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2024 Titouan Christophe
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_USB_CLASS_USBD_MIDI_H_
+#define ZEPHYR_INCLUDE_USB_CLASS_USBD_MIDI_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief USB MIDI 2.0 class device API
+ * @defgroup usbd_midi2 USB MIDI 2.0 Class device API
+ * @ingroup usb
+ * @since 4.1
+ * @version 0.1.0
+ * @see midi20: "Universal Serial Bus Device Class Definition for MIDI Devices"
+ *              Document Release 2.0 (May 5, 2020)
+ * @{
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/audio/midi.h>
+
+/**
+ * @brief      MIDI2 application event handlers
+ */
+struct usbd_midi_ops {
+	/**
+	 * @brief Callback type for incoming Universal MIDI Packets from host
+	 * @param[in]  dev   The MIDI2 device receiving the packet
+	 * @param[in]  ump   The received packet in Universal MIDI Packet format
+	 */
+	void (*rx_packet_cb)(const struct device *dev, const struct midi_ump ump);
+
+	/**
+	 * @brief Callback type for MIDI2 interface runtime status change
+	 * @param[in]  dev    The MIDI2 device
+	 * @param[in]  ready  True if the interface is enabled by the host
+	 */
+	void (*ready_cb)(const struct device *dev, const bool ready);
+};
+
+/**
+ * @brief      Send a Universal MIDI Packet to the host
+ * @param[in]  dev   The MIDI2 device
+ * @param[in]  ump   The packet to send, in Universal MIDI Packet format
+ * @return     0 on success, all other values should be treated as error
+ *             -EIO if USB MIDI 2.0 is not enabled by the host
+ *             -ENOBUFS if there is no space in the TX buffer
+ */
+int usbd_midi_send(const struct device *dev, const struct midi_ump ump);
+
+/**
+ * @brief Set the application event handlers on a USB MIDI device
+ * @param[in]  dev   The MIDI2 device
+ * @param[in]  ops   The event handlers. Pass NULL to reset all callbacks
+ */
+void usbd_midi_set_ops(const struct device *dev, const struct usbd_midi_ops *ops);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/include/zephyr/usb/class/usbd_uac2.h b/include/zephyr/usb/class/usbd_uac2.h
index 271d9dd016e..45965d648d5 100644
--- a/include/zephyr/usb/class/usbd_uac2.h
+++ b/include/zephyr/usb/class/usbd_uac2.h
@@ -47,6 +47,7 @@ struct uac2_ops {
 	 * @brief Start of Frame callback
 	 *
 	 * Notifies application about SOF event on the bus.
+	 * This callback is mandatory to register.
 	 *
 	 * @param dev USB Audio 2 device
 	 * @param user_data Opaque user data pointer
@@ -56,6 +57,7 @@ struct uac2_ops {
 	 * @brief Terminal update callback
 	 *
 	 * Notifies application that host has enabled or disabled a terminal.
+	 * This callback is mandatory to register.
 	 *
 	 * @param dev USB Audio 2 device
 	 * @param terminal Terminal ID linked to AudioStreaming interface
@@ -73,6 +75,7 @@ struct uac2_ops {
 	 * AudioStreaming interface. The buffer is owned by USB stack until
 	 * @ref data_recv_cb callback is called. The buffer must be sufficiently
 	 * aligned and otherwise suitable for use by UDC driver.
+	 * This callback is mandatory to register for devices receiving USB audio from the USB host.
 	 *
 	 * @param dev USB Audio 2 device
 	 * @param terminal Input Terminal ID linked to AudioStreaming interface
@@ -86,6 +89,7 @@ struct uac2_ops {
 	 *
 	 * This function releases buffer obtained in @ref get_recv_buf after USB
 	 * has written data to the buffer and/or no longer needs it.
+	 * This callback is mandatory to register for devices receiving USB audio from the USB host.
 	 *
 	 * @param dev USB Audio 2 device
 	 * @param terminal Input Terminal ID linked to AudioStreaming interface
@@ -100,6 +104,7 @@ struct uac2_ops {
 	 *
 	 * This function releases buffer provided in @ref usbd_uac2_send when
 	 * the class no longer needs it.
+	 * This callback is mandatory to register if calling @ref usbd_uac2_send.
 	 *
 	 * @param dev USB Audio 2 device
 	 * @param terminal Output Terminal ID linked to AudioStreaming interface
@@ -118,6 +123,9 @@ struct uac2_ops {
 	 * capable device is operating at Full-Speed (microframes was false),
 	 * the format is Q10.14 stored on 24 least significant bits (i.e. 8 most
 	 * significant bits are ignored).
+	 * This callback is mandatory to register if there is USB Audio Streaming interface linked
+	 * to Input Terminal clocked from asynchronous clock (i.e. clock source without
+	 * sof-synchronized;) and there is no implicit-feedback; on the interface.
 	 *
 	 * @param dev USB Audio 2 device
 	 * @param terminal Input Terminal ID whose feedback should be returned
@@ -176,6 +184,9 @@ void usbd_uac2_set_ops(const struct device *dev,
  * Data buffer must be sufficiently aligned and otherwise suitable for use by
  * UDC driver.
  *
+ * @note Buffer ownership is transferred to the stack in case of success, in
+ * case of an error the caller retains the ownership of the buffer.
+ *
  * @param dev USB Audio 2 device
  * @param terminal Output Terminal ID linked to AudioStreaming interface
  * @param data Buffer containing outgoing data
diff --git a/include/zephyr/usb/usb_ch9.h b/include/zephyr/usb/usb_ch9.h
index 3f1ad5b8093..b78be4397fa 100644
--- a/include/zephyr/usb/usb_ch9.h
+++ b/include/zephyr/usb/usb_ch9.h
@@ -136,6 +136,13 @@ static inline bool usb_reqtype_is_to_device(const struct usb_setup_packet *setup
 #define USB_SFS_REMOTE_WAKEUP		0x01
 #define USB_SFS_TEST_MODE		0x02
 
+/** USB Test Mode Selectors defined in spec. Table 9-7 */
+#define USB_SFS_TEST_MODE_J		0x01
+#define USB_SFS_TEST_MODE_K		0x02
+#define USB_SFS_TEST_MODE_SE0_NAK	0x03
+#define USB_SFS_TEST_MODE_PACKET	0x04
+#define USB_SFS_TEST_MODE_FORCE_ENABLE	0x05
+
 /** Bits used for GetStatus response defined in spec. Figure 9-4 */
 #define USB_GET_STATUS_SELF_POWERED	BIT(0)
 #define USB_GET_STATUS_REMOTE_WAKEUP	BIT(1)
diff --git a/include/zephyr/usb/usb_device.h b/include/zephyr/usb/usb_device.h
index e596555ed50..39d66383693 100644
--- a/include/zephyr/usb/usb_device.h
+++ b/include/zephyr/usb/usb_device.h
@@ -73,9 +73,6 @@ extern "C" {
 #define USBD_DEFINE_CFG_DATA(name) \
 	static STRUCT_SECTION_ITERABLE(usb_cfg_data, name)
 
-#define USBD_CFG_DATA_DEFINE(p, name) __DEPRECATED_MACRO \
-	static __in_section(_usb_cfg_data, static, p##_name) __used __aligned(4)
-
 /*************************************************************************
  *  USB configuration
  **************************************************************************/
diff --git a/include/zephyr/usb/usbd.h b/include/zephyr/usb/usbd.h
index 7d125dfdf23..5850643b31f 100644
--- a/include/zephyr/usb/usbd.h
+++ b/include/zephyr/usb/usbd.h
@@ -37,6 +37,12 @@ extern "C" {
  * @{
  */
 
+/* 1 if USB device stack is compiled with High-Speed support */
+#define USBD_SUPPORTS_HIGH_SPEED IS_EQ(CONFIG_USBD_MAX_SPEED, 1)
+
+/* Maximum bulk max packet size the stack supports */
+#define USBD_MAX_BULK_MPS COND_CODE_1(USBD_SUPPORTS_HIGH_SPEED, (512), (64))
+
 /*
  * The USB Unicode bString is encoded in UTF16LE, which means it takes up
  * twice the amount of bytes than the same string encoded in ASCII7.
@@ -254,6 +260,8 @@ struct usbd_status {
 	unsigned int suspended : 1;
 	/** USB remote wake-up feature is enabled */
 	unsigned int rwup : 1;
+	/** USB device is self-powered */
+	unsigned int self_powered : 1;
 	/** USB device speed */
 	enum usbd_speed speed : 2;
 };
@@ -842,14 +850,30 @@ int usbd_register_class(struct usbd_context *uds_ctx,
  * usbd_register_class for any device, configuration number, or instance,
  * either usbd_register_class or this function will fail.
  *
+ * There may be situations where a particular function should not be
+ * registered, for example, when using the USB DFU implementation, the DFU mode
+ * function must be excluded during normal device operation. To do this, the
+ * device can pass a blocklist in the form shown below as an optional argument.
+ * If the blocklist is not needed, the argument should be NULL.
+ *
+ * @code{.c}
+ * static const char *const blocklist[] = {
+ *         "dfu_dfu",
+ *         NULL,
+ * };
+ * @endcode
+ *
  * @param[in] uds_ctx Pointer to USB device support context
  * @param[in] speed   Configuration speed
  * @param[in] cfg     Configuration value (bConfigurationValue)
+ * @param[in] blocklist Null pointer terminated array of pointers to string
+ *                      literals to be used as a block list
  *
  * @return 0 on success, other values on fail.
  */
 int usbd_register_all_classes(struct usbd_context *uds_ctx,
-			      const enum usbd_speed speed, uint8_t cfg);
+			      const enum usbd_speed speed, uint8_t cfg,
+			      const char *const blocklist[]);
 
 /**
  * @brief Unregister an USB class instance
@@ -1051,6 +1075,17 @@ bool usbd_is_suspended(struct usbd_context *uds_ctx);
  */
 int usbd_wakeup_request(struct usbd_context *uds_ctx);
 
+/**
+ * @brief Set the self-powered status of the USB device
+ *
+ * The status is used in the Self Powered field of the Get Status request
+ * response to indicate whether the device is currently self-powered.
+ *
+ * @param[in] uds_ctx Pointer to a device context
+ * @param[in] status Sets self-powered status if true, clears it otherwise
+ */
+void usbd_self_powered(struct usbd_context *uds_ctx, const bool status);
+
 /**
  * @brief Get actual device speed
  *
diff --git a/include/zephyr/usb/usbd_msg.h b/include/zephyr/usb/usbd_msg.h
index b9e99d00c70..2d81e0ef2f4 100644
--- a/include/zephyr/usb/usbd_msg.h
+++ b/include/zephyr/usb/usbd_msg.h
@@ -52,6 +52,10 @@ enum usbd_msg_type {
 	USBD_MSG_CDC_ACM_LINE_CODING,
 	/** CDC ACM Line State update */
 	USBD_MSG_CDC_ACM_CONTROL_LINE_STATE,
+	/** USB DFU class detach request */
+	USBD_MSG_DFU_APP_DETACH,
+	/** USB DFU class download completed */
+	USBD_MSG_DFU_DOWNLOAD_COMPLETED,
 	/** Maximum number of message types */
 	USBD_MSG_MAX_NUMBER,
 };
@@ -70,6 +74,8 @@ static const char *const usbd_msg_type_list[] = {
 	"Stack error",
 	"CDC ACM line coding",
 	"CDC ACM control line state",
+	"DFU detach request",
+	"DFU download completed",
 };
 
 BUILD_ASSERT(ARRAY_SIZE(usbd_msg_type_list) == USBD_MSG_MAX_NUMBER,
diff --git a/include/zephyr/usb/usbh.h b/include/zephyr/usb/usbh.h
index 869f3007a48..852d8b9ac69 100644
--- a/include/zephyr/usb/usbh.h
+++ b/include/zephyr/usb/usbh.h
@@ -18,6 +18,7 @@
 #include <zephyr/device.h>
 #include <zephyr/net_buf.h>
 #include <zephyr/sys/dlist.h>
+#include <zephyr/sys/bitarray.h>
 #include <zephyr/drivers/usb/uhc.h>
 #include <zephyr/sys/iterable_sections.h>
 
@@ -42,15 +43,21 @@ struct usbh_contex {
 	struct k_mutex mutex;
 	/** Pointer to UHC device struct */
 	const struct device *dev;
-	/** peripheral list */
-	sys_dlist_t peripherals;
+	/** USB device list */
+	sys_dlist_t udevs;
+	/** USB root device */
+	struct usb_device *root;
+	/** Allocated device addresses bit array */
+	struct sys_bitarray *addr_ba;
 };
 
 #define USBH_CONTROLLER_DEFINE(device_name, uhc_dev)			\
+	SYS_BITARRAY_DEFINE_STATIC(ba_##device_name, 128);		\
 	static STRUCT_SECTION_ITERABLE(usbh_contex, device_name) = {	\
 		.name = STRINGIFY(device_name),				\
 		.mutex = Z_MUTEX_INITIALIZER(device_name.mutex),	\
 		.dev = uhc_dev,						\
+		.addr_ba = &ba_##device_name,				\
 	}
 
 /**
diff --git a/include/zephyr/xen/gnttab.h b/include/zephyr/xen/gnttab.h
index be6a0d5c906..4cfc65e580e 100644
--- a/include/zephyr/xen/gnttab.h
+++ b/include/zephyr/xen/gnttab.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2022 EPAM Systems
+ * Copyright (c) 2021-2024 EPAM Systems
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -76,12 +76,12 @@ int gnttab_map_refs(struct gnttab_map_grant_ref *map_ops, unsigned int count);
  * Unmap foreign grant refs. The gnttab_put_page() should be used after this for
  * each page, that was successfully unmapped.
  *
- * @param unmap_ops - array of prepared gnttab_map_grant_ref's for unmapping
+ * @param unmap_ops - array of prepared gnttab_unmap_grant_ref's for unmapping
  * @param count - number of grefs in unmap_ops array
  * @return - @count on success or negative errno on failure
  *           also per-page status will be set in unmap_ops[i].status (GNTST_*)
  */
-int gnttab_unmap_refs(struct gnttab_map_grant_ref *unmap_ops, unsigned int count);
+int gnttab_unmap_refs(struct gnttab_unmap_grant_ref *unmap_ops, unsigned int count);
 
 /*
  * Convert grant ref status codes (GNTST_*) to text messages.
diff --git a/include/zephyr/xen/public/grant_table.h b/include/zephyr/xen/public/grant_table.h
index 0124046d042..81803a1daa3 100644
--- a/include/zephyr/xen/public/grant_table.h
+++ b/include/zephyr/xen/public/grant_table.h
@@ -324,7 +324,23 @@ struct gnttab_setup_table {
 typedef struct gnttab_setup_table gnttab_setup_table_t;
 DEFINE_XEN_GUEST_HANDLE(gnttab_setup_table_t);
 
-
+/*
+ * GNTTABOP_query_size: Query the current and maximum sizes of the shared
+ * grant table.
+ * NOTES:
+ *  1. <dom> may be specified as DOMID_SELF.
+ *  2. Only a sufficiently-privileged domain may specify <dom> != DOMID_SELF.
+ */
+struct gnttab_query_size {
+	/* IN parameters. */
+	domid_t  dom;
+	/* OUT parameters. */
+	uint32_t nr_frames;
+	uint32_t max_nr_frames;
+	int16_t  status;	/* => enum grant_status */
+};
+typedef struct gnttab_query_size gnttab_query_size_t;
+DEFINE_XEN_GUEST_HANDLE(gnttab_query_size_t);
 
 /*
  * Bitfield values for gnttab_map_grant_ref.flags.
diff --git a/include/zephyr/zbus/zbus.h b/include/zephyr/zbus/zbus.h
index 478268d85b4..c13e77082e7 100644
--- a/include/zephyr/zbus/zbus.h
+++ b/include/zephyr/zbus/zbus.h
@@ -861,6 +861,14 @@ static inline void zbus_chan_pub_stats_update(const struct zbus_channel *chan)
 
 #if defined(CONFIG_ZBUS_RUNTIME_OBSERVERS) || defined(__DOXYGEN__)
 
+/**
+ * @brief Structure for linking observers to chanels
+ */
+struct zbus_observer_node {
+	sys_snode_t node;
+	const struct zbus_observer *obs;
+};
+
 /**
  * @brief Add an observer to a channel.
  *
@@ -868,17 +876,17 @@ static inline void zbus_chan_pub_stats_update(const struct zbus_channel *chan)
  *
  * @param chan The channel's reference.
  * @param obs The observer's reference to be added.
+ * @param node Persistent structure to link the channel to the observer
  * @param timeout Waiting period to add an observer,
  *                or one of the special values K_NO_WAIT and K_FOREVER.
  *
  * @retval 0 Observer added to the channel.
  * @retval -EALREADY The observer is already present in the channel's runtime observers list.
- * @retval -ENOMEM Returned without waiting.
  * @retval -EAGAIN Waiting period timed out.
  * @retval -EINVAL Some parameter is invalid.
  */
 int zbus_chan_add_obs(const struct zbus_channel *chan, const struct zbus_observer *obs,
-		      k_timeout_t timeout);
+		      struct zbus_observer_node *node, k_timeout_t timeout);
 
 /**
  * @brief Remove an observer from a channel.
@@ -900,15 +908,6 @@ int zbus_chan_add_obs(const struct zbus_channel *chan, const struct zbus_observe
 int zbus_chan_rm_obs(const struct zbus_channel *chan, const struct zbus_observer *obs,
 		     k_timeout_t timeout);
 
-/** @cond INTERNAL_HIDDEN */
-
-struct zbus_observer_node {
-	sys_snode_t node;
-	const struct zbus_observer *obs;
-};
-
-/** @endcond */
-
 #endif /* CONFIG_ZBUS_RUNTIME_OBSERVERS */
 
 /**
diff --git a/kernel/CMakeLists.txt b/kernel/CMakeLists.txt
index e5db39713b6..075e091cbb6 100644
--- a/kernel/CMakeLists.txt
+++ b/kernel/CMakeLists.txt
@@ -55,7 +55,6 @@ list(APPEND kernel_files
   errno.c
   fatal.c
   init.c
-  init_static.c
   kheap.c
   mem_slab.c
   float.c
@@ -80,10 +79,18 @@ list(APPEND kernel_files
   system_work_q.c
   work.c
   condvar.c
-  priority_queues.c
   thread.c
   sched.c
   )
+
+if (CONFIG_SCHED_SCALABLE OR CONFIG_WAITQ_SCALABLE)
+list(APPEND kernel_files priority_queues.c)
+endif()
+
+# FIXME: Once the prior pipe implementation is removed, this should be included in the above list
+if(NOT CONFIG_PIPES)
+list(APPEND kernel_files pipe.c)
+endif() # NOT CONFIG_PIPES
 if(CONFIG_SMP)
 list(APPEND kernel_files
      smp.c
diff --git a/kernel/Kconfig b/kernel/Kconfig
index 5f4d78e02f7..f3f83a9e93e 100644
--- a/kernel/Kconfig
+++ b/kernel/Kconfig
@@ -12,6 +12,7 @@ source "subsys/logging/Kconfig.template.log_config"
 config MULTITHREADING
 	bool "Multi-threading" if ARCH_HAS_SINGLE_THREAD_SUPPORT
 	default y
+	select RING_BUFFER
 	help
 	  If disabled, only the main thread is available, so a main() function
 	  must be provided. Interrupts are available. Kernel objects will most
@@ -52,7 +53,7 @@ config NUM_PREEMPT_PRIORITIES
 	int "Number of preemptible priorities" if MULTITHREADING
 	default 0 if !MULTITHREADING
 	default 15
-	range 0 128
+	range 0 127
 	help
 	  Number of preemptible priorities available in the system. Gives access
 	  to priorities 0 to CONFIG_NUM_PREEMPT_PRIORITIES - 1.
@@ -728,6 +729,7 @@ config EVENTS
 
 config PIPES
 	bool "Pipe objects"
+	select DEPRECATED
 	help
 	  This option enables kernel pipes. A pipe is a kernel object that
 	  allows a thread to send a byte stream to another thread. Pipes can
@@ -735,6 +737,9 @@ config PIPES
 
 	  Note that setting this option slightly increases the size of the
 	  thread structure.
+	  This Kconfig is deprecated and will be removed, by disabling this
+	  kconfig another implementation of k_pipe will be available when
+	  CONFIG_MULTITHREADING is enabled.
 
 config KERNEL_MEM_POOL
 	bool "Use Kernel Memory Pool"
@@ -778,9 +783,9 @@ endmenu
 config SWAP_NONATOMIC
 	bool
 	help
-	  On some architectures, the _Swap() primitive cannot be made
+	  On some architectures, the z_swap() primitive cannot be made
 	  atomic with respect to the irq_lock being released.  That
-	  is, interrupts may be received between the entry to _Swap
+	  is, interrupts may be received between the entry to z_swap
 	  and the completion of the context switch.  There are a
 	  handful of workaround cases in the kernel that need to be
 	  enabled when this is true.  Currently, this only happens on
@@ -823,6 +828,7 @@ config SYS_CLOCK_TICKS_PER_SEC
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	int "System clock's h/w timer frequency"
+	default 0 if TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
 	help
 	  This option specifies the frequency of the hardware timer used for the
 	  system clock (in Hz). This option is set by the SOC's or board's Kconfig file
@@ -1041,10 +1047,10 @@ config KERNEL_WHOLE_ARCHIVE
 	  to be included, rather than searching the archive for required object files.
 
 config TOOLCHAIN_SUPPORTS_STATIC_INIT_GNU
-	# As of today only ARC MWDT toolchain doesn't support GNU-compatible
-	# initialization of static objects, new toolchains can be added
-	# here if required.
-	def_bool "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "arcmwdt"
+	# As of today, we don't know of any toolchains that don't create
+	# either .ctors or .init_array sections containing initializer
+	# addresses in a fashion compatible with how Zephyr uses them.
+	def_bool y
 
 config STATIC_INIT_GNU
 	bool "Support GNU-compatible initializers and constructors"
@@ -1054,14 +1060,11 @@ config STATIC_INIT_GNU
 	help
 	  GNU-compatible initialization of static objects. This is required for
 	  C++ constructor support as well as for initializer functions as
-	  defined by GNU-compatible toolchains. This increases the size
-	  of Zephyr binaries by around 100 bytes. If you know your
-	  application doesn't need any initializers, you can disable this
-	  option.
-	  The ARC MWDT toolchain, does not support or use this setting,
-	  and has instead separate C++ constructor initialization code.
-	  Note the option CMAKE_LINKER_GENERATOR does not yet support this feature
-	  or CPP.
+	  defined by GNU-compatible toolchains. This increases the size of
+	  Zephyr binaries by around 24 bytes. If you know your application
+	  doesn't need any initializers, you can disable this option. The linker
+	  will emit an error if constructors are needed and this option has been
+	  disabled.
 
 config BOOTARGS
 	bool "Support bootargs"
@@ -1070,7 +1073,7 @@ config BOOTARGS
 
 config DYNAMIC_BOOTARGS
 	bool "Support dynamic bootargs"
-	depends on BOOTARGS && (MULTIBOOT_INFO || BUILD_OUTPUT_EFI)
+	depends on BOOTARGS
 	help
 	  Enables dynamic bootargs support.
 
diff --git a/kernel/Kconfig.obj_core b/kernel/Kconfig.obj_core
index 5c9a1418ffe..5e846b20ffa 100644
--- a/kernel/Kconfig.obj_core
+++ b/kernel/Kconfig.obj_core
@@ -77,7 +77,7 @@ config OBJ_CORE_SEM
 
 config OBJ_CORE_PIPE
 	bool "Integrate pipe into object core framework"
-	default y if PIPES
+	default y
 	help
 	  When enabled, this option integrates pipes into the object core
 	  framework.
diff --git a/kernel/Kconfig.vm b/kernel/Kconfig.vm
index 923d511d9db..a8105d03da0 100644
--- a/kernel/Kconfig.vm
+++ b/kernel/Kconfig.vm
@@ -98,8 +98,10 @@ config KERNEL_DIRECT_MAP
 
 endif # KERNEL_VM_SUPPORT
 
-menuconfig MMU
-	bool "MMU features"
+menu "MMU Features"
+
+config MMU
+	bool
 	depends on CPU_HAS_MMU
 	select KERNEL_VM_SUPPORT
 	help
@@ -206,6 +208,7 @@ config DEMAND_PAGING_TIMING_HISTOGRAM_NUM_BINS
 
 endif # DEMAND_PAGING
 endif # MMU
+endmenu
 
 config KERNEL_VM_USE_CUSTOM_MEM_RANGE_CHECK
 	bool
diff --git a/kernel/condvar.c b/kernel/condvar.c
index 615a6b30f15..d00eb552ff7 100644
--- a/kernel/condvar.c
+++ b/kernel/condvar.c
@@ -93,7 +93,12 @@ int z_impl_k_condvar_broadcast(struct k_condvar *condvar)
 
 	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_condvar, broadcast, condvar, woken);
 
-	z_reschedule(&lock, key);
+
+	if (woken == 0) {
+		k_spin_unlock(&lock, key);
+	} else {
+		z_reschedule(&lock, key);
+	}
 
 	return woken;
 }
diff --git a/kernel/device.c b/kernel/device.c
index 7e882269580..ad97b0b0409 100644
--- a/kernel/device.c
+++ b/kernel/device.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <errno.h>
 #include <stddef.h>
 #include <string.h>
 #include <zephyr/device.h>
@@ -142,6 +143,38 @@ bool z_impl_device_is_ready(const struct device *dev)
 	return dev->state->initialized && (dev->state->init_res == 0U);
 }
 
+int z_impl_device_deinit(const struct device *dev)
+{
+	int ret;
+
+	if (!dev->state->initialized) {
+		return -EPERM;
+	}
+
+	if (dev->ops.deinit == NULL) {
+		return -ENOTSUP;
+	}
+
+	ret = dev->ops.deinit(dev);
+	if (ret < 0) {
+		return ret;
+	}
+
+	dev->state->initialized = false;
+
+	return 0;
+}
+
+#ifdef CONFIG_USERSPACE
+static inline int z_vrfy_device_deinit(const struct device *dev)
+{
+	K_OOPS(K_SYSCALL_OBJ_INIT(dev, K_OBJ_ANY));
+
+	return z_impl_device_deinit(dev);
+}
+#include <zephyr/syscalls/device_deinit_mrsh.c>
+#endif
+
 #ifdef CONFIG_DEVICE_DEPS
 
 static int device_visitor(const device_handle_t *handles,
diff --git a/kernel/futex.c b/kernel/futex.c
index 86acc0c74a0..c6e5e47e683 100644
--- a/kernel/futex.c
+++ b/kernel/futex.c
@@ -47,7 +47,11 @@ int z_impl_k_futex_wake(struct k_futex *futex, bool wake_all)
 		}
 	} while (thread && wake_all);
 
-	z_reschedule(&futex_data->lock, key);
+	if (woken == 0) {
+		k_spin_unlock(&futex_data->lock, key);
+	} else {
+		z_reschedule(&futex_data->lock, key);
+	}
 
 	return woken;
 }
diff --git a/kernel/idle.c b/kernel/idle.c
index 62ff84e4c88..3cf47910093 100644
--- a/kernel/idle.c
+++ b/kernel/idle.c
@@ -8,6 +8,7 @@
 #include <zephyr/toolchain.h>
 #include <zephyr/linker/sections.h>
 #include <zephyr/drivers/timer/system_timer.h>
+#include <zephyr/llext/symbol.h>
 #include <zephyr/pm/pm.h>
 #include <stdbool.h>
 #include <zephyr/logging/log.h>
@@ -100,3 +101,4 @@ void __weak arch_spin_relax(void)
 
 	arch_nop();
 }
+EXPORT_SYMBOL(arch_spin_relax);
diff --git a/kernel/include/kernel_internal.h b/kernel/include/kernel_internal.h
index 94f90ce9462..eadacf936c9 100644
--- a/kernel/include/kernel_internal.h
+++ b/kernel/include/kernel_internal.h
@@ -105,10 +105,7 @@ void *z_thread_aligned_alloc(size_t align, size_t size);
  * @return A pointer to the allocated memory, or NULL if there is insufficient
  * RAM in the pool or there is no pool to draw memory from
  */
-static inline void *z_thread_malloc(size_t size)
-{
-	return z_thread_aligned_alloc(0, size);
-}
+void *z_thread_malloc(size_t size);
 
 
 #ifdef CONFIG_USE_SWITCH
@@ -221,7 +218,7 @@ void z_mem_manage_init(void);
 void z_mem_manage_boot_finish(void);
 
 
-void z_handle_obj_poll_events(sys_dlist_t *events, uint32_t state);
+bool z_handle_obj_poll_events(sys_dlist_t *events, uint32_t state);
 
 #ifdef CONFIG_PM
 
diff --git a/kernel/include/kernel_offsets.h b/kernel/include/kernel_offsets.h
index 3cadf7e12a0..1d560cb602f 100644
--- a/kernel/include/kernel_offsets.h
+++ b/kernel/include/kernel_offsets.h
@@ -48,10 +48,6 @@ GEN_OFFSET_SYM(_kernel_t, ready_q);
 GEN_OFFSET_SYM(_ready_q_t, cache);
 #endif /* CONFIG_SMP */
 
-#ifdef CONFIG_FPU_SHARING
-GEN_OFFSET_SYM(_kernel_t, current_fp);
-#endif /* CONFIG_FPU_SHARING */
-
 GEN_OFFSET_SYM(_thread_base_t, user_options);
 
 GEN_OFFSET_SYM(_thread_t, base);
diff --git a/kernel/include/ksched.h b/kernel/include/ksched.h
index 1807330fe52..7858282d707 100644
--- a/kernel/include/ksched.h
+++ b/kernel/include/ksched.h
@@ -119,7 +119,7 @@ static inline bool z_is_prio_lower_or_equal(int prio1, int prio2)
 	return z_is_prio1_lower_than_or_equal_to_prio2(prio1, prio2);
 }
 
-static inline bool _is_valid_prio(int prio, void *entry_point)
+static inline bool _is_valid_prio(int prio, k_thread_entry_t entry_point)
 {
 	if ((prio == K_IDLE_PRIO) && z_is_idle_thread_entry(entry_point)) {
 		return true;
@@ -180,7 +180,7 @@ static ALWAYS_INLINE struct k_thread *z_unpend_first_thread(_wait_q_t *wait_q)
 		thread = _priq_wait_best(&wait_q->waitq);
 		if (unlikely(thread != NULL)) {
 			unpend_thread_no_timeout(thread);
-			(void)z_abort_thread_timeout(thread);
+			z_abort_thread_timeout(thread);
 		}
 	}
 
diff --git a/kernel/include/kswap.h b/kernel/include/kswap.h
index 803a4a546eb..03c4a991bb0 100644
--- a/kernel/include/kswap.h
+++ b/kernel/include/kswap.h
@@ -124,7 +124,6 @@ static ALWAYS_INLINE unsigned int do_swap(unsigned int key,
 		z_sched_usage_switch(new_thread);
 
 #ifdef CONFIG_SMP
-		_current_cpu->swap_ok = 0;
 		new_thread->base.cpu = arch_curr_cpu()->id;
 
 		if (!is_spinlock) {
@@ -235,30 +234,6 @@ static inline void z_swap_unlocked(void)
  *
  * The memory of the dummy thread can be completely uninitialized.
  */
-static inline void z_dummy_thread_init(struct k_thread *dummy_thread)
-{
-	dummy_thread->base.thread_state = _THREAD_DUMMY;
-#ifdef CONFIG_SCHED_CPU_MASK
-	dummy_thread->base.cpu_mask = -1;
-#endif /* CONFIG_SCHED_CPU_MASK */
-	dummy_thread->base.user_options = K_ESSENTIAL;
-#ifdef CONFIG_THREAD_STACK_INFO
-	dummy_thread->stack_info.start = 0U;
-	dummy_thread->stack_info.size = 0U;
-#endif /* CONFIG_THREAD_STACK_INFO */
-#ifdef CONFIG_USERSPACE
-	dummy_thread->mem_domain_info.mem_domain = &k_mem_domain_default;
-#endif /* CONFIG_USERSPACE */
-#if (K_HEAP_MEM_POOL_SIZE > 0)
-	k_thread_system_pool_assign(dummy_thread);
-#else
-	dummy_thread->resource_pool = NULL;
-#endif /* K_HEAP_MEM_POOL_SIZE */
+void z_dummy_thread_init(struct k_thread *dummy_thread);
 
-#ifdef CONFIG_TIMESLICE_PER_THREAD
-	dummy_thread->base.slice_ticks = 0;
-#endif /* CONFIG_TIMESLICE_PER_THREAD */
-
-	z_current_thread_set(dummy_thread);
-}
 #endif /* ZEPHYR_KERNEL_INCLUDE_KSWAP_H_ */
diff --git a/kernel/include/kthread.h b/kernel/include/kthread.h
index 636a62b7009..45a1fec06a1 100644
--- a/kernel/include/kthread.h
+++ b/kernel/include/kthread.h
@@ -108,8 +108,7 @@ static inline bool z_is_thread_timeout_active(struct k_thread *thread)
 
 static inline bool z_is_thread_ready(struct k_thread *thread)
 {
-	return !((z_is_thread_prevented_from_running(thread)) != 0U ||
-		 z_is_thread_timeout_active(thread));
+	return !z_is_thread_prevented_from_running(thread);
 }
 
 static inline bool z_is_thread_state_set(struct k_thread *thread, uint32_t state)
diff --git a/kernel/include/offsets_short.h b/kernel/include/offsets_short.h
index 373d7e02ec9..c97ba15e562 100644
--- a/kernel/include/offsets_short.h
+++ b/kernel/include/offsets_short.h
@@ -34,9 +34,6 @@
 #define _kernel_offset_to_idle \
 	(___kernel_t_idle_OFFSET)
 
-#define _kernel_offset_to_current_fp \
-	(___kernel_t_current_fp_OFFSET)
-
 #define _kernel_offset_to_ready_q_cache \
 	(___kernel_t_ready_q_OFFSET + ___ready_q_t_cache_OFFSET)
 
diff --git a/kernel/include/priority_q.h b/kernel/include/priority_q.h
index 304effc0752..09f86caa819 100644
--- a/kernel/include/priority_q.h
+++ b/kernel/include/priority_q.h
@@ -10,8 +10,6 @@
 #include <zephyr/sys/math_extras.h>
 #include <zephyr/sys/dlist.h>
 
-bool z_priq_rb_lessthan(struct rbnode *a, struct rbnode *b);
-
 /* Dumb Scheduling */
 #if defined(CONFIG_SCHED_SIMPLE)
 #define _priq_run_init		z_priq_simple_init
@@ -185,8 +183,11 @@ static ALWAYS_INLINE struct k_thread *z_priq_simple_mask_best(sys_dlist_t *pq)
 }
 #endif /* CONFIG_SCHED_CPU_MASK */
 
+#if defined(CONFIG_SCHED_SCALABLE) || defined(CONFIG_WAITQ_SCALABLE)
 static ALWAYS_INLINE void z_priq_rb_init(struct _priq_rb *pq)
 {
+	bool z_priq_rb_lessthan(struct rbnode *a, struct rbnode *b);
+
 	*pq = (struct _priq_rb) {
 		.tree = {
 			.lessthan_fn = z_priq_rb_lessthan,
@@ -244,6 +245,7 @@ static ALWAYS_INLINE struct k_thread *z_priq_rb_best(struct _priq_rb *pq)
 	}
 	return thread;
 }
+#endif
 
 struct prio_info {
 	uint8_t offset_prio;
diff --git a/kernel/include/timeout_q.h b/kernel/include/timeout_q.h
index a62242a9f3c..6ae627aadbd 100644
--- a/kernel/include/timeout_q.h
+++ b/kernel/include/timeout_q.h
@@ -22,13 +22,19 @@ extern "C" {
 
 #ifdef CONFIG_SYS_CLOCK_EXISTS
 
+/* Value written to dticks when timeout is aborted. */
+#define TIMEOUT_DTICKS_ABORTED (IS_ENABLED(CONFIG_TIMEOUT_64BIT) ? INT64_MIN : INT32_MIN)
+
 static inline void z_init_timeout(struct _timeout *to)
 {
 	sys_dnode_init(&to->node);
 }
 
-void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
-		   k_timeout_t timeout);
+/* Adds the timeout to the queue.
+ *
+ * @return Absolute tick value when timeout will expire.
+ */
+k_ticks_t z_add_timeout(struct _timeout *to, _timeout_func_t fn, k_timeout_t timeout);
 
 int z_abort_timeout(struct _timeout *to);
 
@@ -37,6 +43,12 @@ static inline bool z_is_inactive_timeout(const struct _timeout *to)
 	return !sys_dnode_is_linked(&to->node);
 }
 
+static inline bool z_is_aborted_timeout(const struct _timeout *to)
+{
+	/* When timeout is aborted then dticks is set to special value. */
+	return to->dticks == TIMEOUT_DTICKS_ABORTED;
+}
+
 static inline void z_init_thread_timeout(struct _thread_base *thread_base)
 {
 	z_init_timeout(&thread_base->timeout);
@@ -44,14 +56,20 @@ static inline void z_init_thread_timeout(struct _thread_base *thread_base)
 
 extern void z_thread_timeout(struct _timeout *timeout);
 
-static inline void z_add_thread_timeout(struct k_thread *thread, k_timeout_t ticks)
+static inline k_ticks_t z_add_thread_timeout(struct k_thread *thread, k_timeout_t ticks)
 {
-	z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
+	return z_add_timeout(&thread->base.timeout, z_thread_timeout, ticks);
 }
 
-static inline int z_abort_thread_timeout(struct k_thread *thread)
+static inline void z_abort_thread_timeout(struct k_thread *thread)
 {
-	return z_abort_timeout(&thread->base.timeout);
+	z_abort_timeout(&thread->base.timeout);
+}
+
+static inline bool z_is_aborted_thread_timeout(struct k_thread *thread)
+{
+
+	return z_is_aborted_timeout(&thread->base.timeout);
 }
 
 int32_t z_get_next_timeout_expiry(void);
@@ -62,15 +80,18 @@ k_ticks_t z_timeout_remaining(const struct _timeout *timeout);
 
 /* Stubs when !CONFIG_SYS_CLOCK_EXISTS */
 #define z_init_thread_timeout(thread_base) do {} while (false)
-#define z_abort_thread_timeout(to) (0)
+#define z_abort_thread_timeout(to) do {} while (false)
+#define z_is_aborted_thread_timeout(to) false
 #define z_is_inactive_timeout(to) 1
+#define z_is_aborted_timeout(to) false
 #define z_get_next_timeout_expiry() ((int32_t) K_TICKS_FOREVER)
 #define z_set_timeout_expiry(ticks, is_idle) do {} while (false)
 
-static inline void z_add_thread_timeout(struct k_thread *thread, k_timeout_t ticks)
+static inline k_ticks_t z_add_thread_timeout(struct k_thread *thread, k_timeout_t ticks)
 {
 	ARG_UNUSED(thread);
 	ARG_UNUSED(ticks);
+	return 0;
 }
 
 #endif /* CONFIG_SYS_CLOCK_EXISTS */
diff --git a/kernel/init.c b/kernel/init.c
index d6c4fb3c70c..c29ea8ff931 100644
--- a/kernel/init.c
+++ b/kernel/init.c
@@ -247,6 +247,11 @@ void z_bss_zero(void)
 	z_early_memset(&__gcov_bss_start, 0,
 		       ((uintptr_t) &__gcov_bss_end - (uintptr_t) &__gcov_bss_start));
 #endif /* CONFIG_COVERAGE_GCOV */
+#ifdef CONFIG_NOCACHE_MEMORY
+z_early_memset(&_nocache_ram_start, 0,
+		   (uintptr_t) &_nocache_ram_end
+		   - (uintptr_t) &_nocache_ram_start);
+#endif
 }
 
 #ifdef CONFIG_LINKER_USE_BOOT_SECTION
@@ -302,13 +307,12 @@ extern volatile uintptr_t __stack_chk_guard;
 __pinned_bss
 bool z_sys_post_kernel;
 
-static int do_device_init(const struct init_entry *entry)
+static int do_device_init(const struct device *dev)
 {
-	const struct device *dev = entry->dev;
 	int rc = 0;
 
-	if (entry->init_fn.dev != NULL) {
-		rc = entry->init_fn.dev(dev);
+	if (dev->ops.init != NULL) {
+		rc = dev->ops.init(dev);
 		/* Mark device initialized. If initialization
 		 * failed, record the error condition.
 		 */
@@ -362,13 +366,15 @@ static void z_sys_init_run_level(enum init_level level)
 
 	for (entry = levels[level]; entry < levels[level+1]; entry++) {
 		const struct device *dev = entry->dev;
-		int result;
+		int result = 0;
 
 		sys_trace_sys_init_enter(entry, level);
 		if (dev != NULL) {
-			result = do_device_init(entry);
+			if ((dev->flags & DEVICE_FLAG_INIT_DEFERRED) == 0U) {
+				result = do_device_init(dev);
+			}
 		} else {
-			result = entry->init_fn.sys();
+			result = entry->init_fn();
 		}
 		sys_trace_sys_init_exit(entry, level, result);
 	}
@@ -377,17 +383,11 @@ static void z_sys_init_run_level(enum init_level level)
 
 int z_impl_device_init(const struct device *dev)
 {
-	if (dev == NULL) {
-		return -ENOENT;
-	}
-
-	STRUCT_SECTION_FOREACH_ALTERNATE(_deferred_init, init_entry, entry) {
-		if (entry->dev == dev) {
-			return do_device_init(entry);
-		}
+	if (dev->state->initialized) {
+		return -EALREADY;
 	}
 
-	return -ENOENT;
+	return do_device_init(dev);
 }
 
 #ifdef CONFIG_USERSPACE
@@ -488,6 +488,27 @@ static char **prepare_main_args(int *argc)
 		(*argc)++;
 	}
 }
+
+#endif
+
+#ifdef CONFIG_STATIC_INIT_GNU
+
+extern void (*__zephyr_init_array_start[])();
+extern void (*__zephyr_init_array_end[])();
+
+static void z_static_init_gnu(void)
+{
+	void	(**fn)();
+
+	for (fn = __zephyr_init_array_start; fn != __zephyr_init_array_end; fn++) {
+		/* MWDT toolchain sticks a NULL at the end of the array */
+		if (*fn == NULL) {
+			break;
+		}
+		(**fn)();
+	}
+}
+
 #endif
 
 /**
@@ -529,8 +550,9 @@ static void bg_thread_main(void *unused1, void *unused2, void *unused3)
 #endif /* CONFIG_STACK_POINTER_RANDOM */
 	boot_banner();
 
-	void z_init_static(void);
-	z_init_static();
+#ifdef CONFIG_STATIC_INIT_GNU
+	z_static_init_gnu();
+#endif /* CONFIG_STATIC_INIT_GNU */
 
 	/* Final init level before app starts */
 	z_sys_init_run_level(INIT_LEVEL_APPLICATION);
diff --git a/kernel/init_static.c b/kernel/init_static.c
deleted file mode 100644
index 442757a73a6..00000000000
--- a/kernel/init_static.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (c) 2012-2015 Wind River Systems, Inc.
- * Copyright (c) 2021 Synopsys, Inc.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-void __do_global_ctors_aux(void);
-void __do_init_array_aux(void);
-
-void z_init_static(void)
-{
-#if defined(CONFIG_STATIC_INIT_GNU)
-	__do_global_ctors_aux();
-	__do_init_array_aux();
-#elif defined(__CCAC__) /* ARC MWDT */
-	__do_global_ctors_aux();
-#endif
-}
-
-/**
- * @section - Constructor module
- * @brief
- * The ctors section contains a list of function pointers that execute both the C++ constructors of
- * static global objects, as well as either C or C++ initializer functions (declared with the
- * attribute constructor). These must be executed before the application's main() routine.
- *
- * NOTE: Not all compilers put those function pointers into the ctors section;
- * some put them into the init_array section instead.
- */
-
-#ifdef CONFIG_STATIC_INIT_GNU
-
-/* What a constructor function pointer looks like */
-
-typedef void (*CtorFuncPtr)(void);
-
-/* Constructor function pointer list is generated by the linker script. */
-
-extern CtorFuncPtr __ZEPHYR_CTOR_LIST__[];
-extern CtorFuncPtr __ZEPHYR_CTOR_END__[];
-
-/**
- *
- * @brief Invoke all C++ style global object constructors
- *
- * This routine is invoked by the kernel prior to the execution of the
- * application's main().
- */
-void __do_global_ctors_aux(void)
-{
-	unsigned int nCtors;
-
-	nCtors = (unsigned long)__ZEPHYR_CTOR_LIST__[0];
-
-	while (nCtors >= 1U) {
-		__ZEPHYR_CTOR_LIST__[nCtors--]();
-	}
-}
-
-#endif
-
-/*
- * @section
- * @brief Execute initialization routines referenced in .init_array section
- */
-
-#ifdef CONFIG_STATIC_INIT_GNU
-
-typedef void (*func_ptr)(void);
-
-extern func_ptr __zephyr_init_array_start[];
-extern func_ptr __zephyr_init_array_end[];
-
-/**
- * @brief Execute initialization routines referenced in .init_array section
- */
-void __do_init_array_aux(void)
-{
-	for (func_ptr *func = __zephyr_init_array_start;
-		func < __zephyr_init_array_end;
-		func++) {
-		(*func)();
-	}
-}
-
-#endif
diff --git a/kernel/kheap.c b/kernel/kheap.c
index 7c402e740fd..90aa3b0ee1f 100644
--- a/kernel/kheap.c
+++ b/kernel/kheap.c
@@ -15,6 +15,7 @@
 void k_heap_init(struct k_heap *heap, void *mem, size_t bytes)
 {
 	z_waitq_init(&heap->wait_q);
+	heap->lock = (struct k_spinlock) {};
 	sys_heap_init(&heap->heap, mem, bytes);
 
 	SYS_PORT_TRACING_OBJ_INIT(k_heap, heap);
@@ -62,22 +63,23 @@ SYS_INIT_NAMED(statics_init_pre, statics_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_
 SYS_INIT_NAMED(statics_init_post, statics_init, POST_KERNEL, 0);
 #endif /* CONFIG_DEMAND_PAGING && !CONFIG_LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT */
 
-void *k_heap_aligned_alloc(struct k_heap *heap, size_t align, size_t bytes,
-			k_timeout_t timeout)
+typedef void * (sys_heap_allocator_t)(struct sys_heap *heap, size_t align, size_t bytes);
+
+static void *z_heap_alloc_helper(struct k_heap *heap, size_t align, size_t bytes,
+				 k_timeout_t timeout,
+				 sys_heap_allocator_t *sys_heap_allocator)
 {
 	k_timepoint_t end = sys_timepoint_calc(timeout);
 	void *ret = NULL;
 
 	k_spinlock_key_t key = k_spin_lock(&heap->lock);
 
-	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_heap, aligned_alloc, heap, timeout);
-
 	__ASSERT(!arch_is_in_isr() || K_TIMEOUT_EQ(timeout, K_NO_WAIT), "");
 
 	bool blocked_alloc = false;
 
 	while (ret == NULL) {
-		ret = sys_heap_aligned_alloc(&heap->heap, align, bytes);
+		ret = sys_heap_allocator(&heap->heap, align, bytes);
 
 		if (!IS_ENABLED(CONFIG_MULTITHREADING) ||
 		    (ret != NULL) || K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
@@ -87,7 +89,7 @@ void *k_heap_aligned_alloc(struct k_heap *heap, size_t align, size_t bytes,
 		if (!blocked_alloc) {
 			blocked_alloc = true;
 
-			SYS_PORT_TRACING_OBJ_FUNC_BLOCKING(k_heap, aligned_alloc, heap, timeout);
+			SYS_PORT_TRACING_OBJ_FUNC_BLOCKING(k_heap, alloc_helper, heap, timeout);
 		} else {
 			/**
 			 * @todo	Trace attempt to avoid empty trace segments
@@ -99,8 +101,6 @@ void *k_heap_aligned_alloc(struct k_heap *heap, size_t align, size_t bytes,
 		key = k_spin_lock(&heap->lock);
 	}
 
-	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_heap, aligned_alloc, heap, timeout, ret);
-
 	k_spin_unlock(&heap->lock, key);
 	return ret;
 }
@@ -109,13 +109,36 @@ void *k_heap_alloc(struct k_heap *heap, size_t bytes, k_timeout_t timeout)
 {
 	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_heap, alloc, heap, timeout);
 
-	void *ret = k_heap_aligned_alloc(heap, sizeof(void *), bytes, timeout);
+	void *ret = z_heap_alloc_helper(heap, 0, bytes, timeout,
+					sys_heap_noalign_alloc);
 
 	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_heap, alloc, heap, timeout, ret);
 
 	return ret;
 }
 
+void *k_heap_aligned_alloc(struct k_heap *heap, size_t align, size_t bytes,
+			k_timeout_t timeout)
+{
+	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_heap, aligned_alloc, heap, timeout);
+
+	void *ret = z_heap_alloc_helper(heap, align, bytes, timeout,
+					sys_heap_aligned_alloc);
+
+	/*
+	 * modules/debug/percepio/TraceRecorder/kernelports/Zephyr/include/tracing_tracerecorder.h
+	 * contains a concealed non-parameterized direct reference to a local
+	 * variable through the SYS_PORT_TRACING_OBJ_FUNC_EXIT macro below
+	 * that is no longer in scope. Provide a dummy stub for compilation
+	 * to still succeed until that module's layering violation is fixed.
+	 */
+	bool blocked_alloc = false; ARG_UNUSED(blocked_alloc);
+
+	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_heap, aligned_alloc, heap, timeout, ret);
+
+	return ret;
+}
+
 void *k_heap_calloc(struct k_heap *heap, size_t num, size_t size, k_timeout_t timeout)
 {
 	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_heap, calloc, heap, timeout);
@@ -147,7 +170,7 @@ void *k_heap_realloc(struct k_heap *heap, void *ptr, size_t bytes, k_timeout_t t
 	__ASSERT(!arch_is_in_isr() || K_TIMEOUT_EQ(timeout, K_NO_WAIT), "");
 
 	while (ret == NULL) {
-		ret = sys_heap_aligned_realloc(&heap->heap, ptr, sizeof(void *), bytes);
+		ret = sys_heap_realloc(&heap->heap, ptr, bytes);
 
 		if (!IS_ENABLED(CONFIG_MULTITHREADING) ||
 		    (ret != NULL) || K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
diff --git a/kernel/mempool.c b/kernel/mempool.c
index d8926c63ed9..62748f7ea81 100644
--- a/kernel/mempool.c
+++ b/kernel/mempool.c
@@ -9,11 +9,19 @@
 #include <zephyr/sys/math_extras.h>
 #include <zephyr/sys/util.h>
 
-static void *z_heap_aligned_alloc(struct k_heap *heap, size_t align, size_t size)
+typedef void * (sys_heap_allocator_t)(struct sys_heap *heap, size_t align, size_t bytes);
+
+static void *z_alloc_helper(struct k_heap *heap, size_t align, size_t size,
+			    sys_heap_allocator_t sys_heap_allocator)
 {
 	void *mem;
 	struct k_heap **heap_ref;
 	size_t __align;
+	k_spinlock_key_t key;
+
+	/* A power of 2 as well as 0 is OK */
+	__ASSERT((align & (align - 1)) == 0,
+		"align must be a power of 2");
 
 	/*
 	 * Adjust the size to make room for our heap reference.
@@ -26,7 +34,14 @@ static void *z_heap_aligned_alloc(struct k_heap *heap, size_t align, size_t size
 	}
 	__align = align | sizeof(heap_ref);
 
-	mem = k_heap_aligned_alloc(heap, __align, size, K_NO_WAIT);
+	/*
+	 * No point calling k_heap_malloc/k_heap_aligned_alloc with K_NO_WAIT.
+	 * Better bypass them and go directly to sys_heap_*() instead.
+	 */
+	key = k_spin_lock(&heap->lock);
+	mem = sys_heap_allocator(&heap->heap, __align, size);
+	k_spin_unlock(&heap->lock, key);
+
 	if (mem == NULL) {
 		return NULL;
 	}
@@ -64,16 +79,9 @@ K_HEAP_DEFINE(_system_heap, K_HEAP_MEM_POOL_SIZE);
 
 void *k_aligned_alloc(size_t align, size_t size)
 {
-	__ASSERT(align / sizeof(void *) >= 1
-		&& (align % sizeof(void *)) == 0,
-		"align must be a multiple of sizeof(void *)");
-
-	__ASSERT((align & (align - 1)) == 0,
-		"align must be a power of 2");
-
 	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_heap_sys, k_aligned_alloc, _SYSTEM_HEAP);
 
-	void *ret = z_heap_aligned_alloc(_SYSTEM_HEAP, align, size);
+	void *ret = z_alloc_helper(_SYSTEM_HEAP, align, size, sys_heap_aligned_alloc);
 
 	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_heap_sys, k_aligned_alloc, _SYSTEM_HEAP, ret);
 
@@ -84,7 +92,7 @@ void *k_malloc(size_t size)
 {
 	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_heap_sys, k_malloc, _SYSTEM_HEAP);
 
-	void *ret = k_aligned_alloc(sizeof(void *), size);
+	void *ret = z_alloc_helper(_SYSTEM_HEAP, 0, size, sys_heap_noalign_alloc);
 
 	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_heap_sys, k_malloc, _SYSTEM_HEAP, ret);
 
@@ -117,6 +125,7 @@ void *k_calloc(size_t nmemb, size_t size)
 void *k_realloc(void *ptr, size_t size)
 {
 	struct k_heap *heap, **heap_ref;
+	k_spinlock_key_t key;
 	void *ret;
 
 	if (size == 0) {
@@ -137,7 +146,13 @@ void *k_realloc(void *ptr, size_t size)
 		return NULL;
 	}
 
-	ret = k_heap_realloc(heap, ptr, size, K_NO_WAIT);
+	/*
+	 * No point calling k_heap_realloc() with K_NO_WAIT here.
+	 * Better bypass it and go directly to sys_heap_realloc() instead.
+	 */
+	key = k_spin_lock(&heap->lock);
+	ret = sys_heap_realloc(&heap->heap, ptr, size);
+	k_spin_unlock(&heap->lock, key);
 
 	if (ret != NULL) {
 		heap_ref = ret;
@@ -157,7 +172,8 @@ void k_thread_system_pool_assign(struct k_thread *thread)
 #define _SYSTEM_HEAP	NULL
 #endif /* K_HEAP_MEM_POOL_SIZE */
 
-void *z_thread_aligned_alloc(size_t align, size_t size)
+static void *z_thread_alloc_helper(size_t align, size_t size,
+				   sys_heap_allocator_t sys_heap_allocator)
 {
 	void *ret;
 	struct k_heap *heap;
@@ -169,10 +185,20 @@ void *z_thread_aligned_alloc(size_t align, size_t size)
 	}
 
 	if (heap != NULL) {
-		ret = z_heap_aligned_alloc(heap, align, size);
+		ret = z_alloc_helper(heap, align, size, sys_heap_allocator);
 	} else {
 		ret = NULL;
 	}
 
 	return ret;
 }
+
+void *z_thread_aligned_alloc(size_t align, size_t size)
+{
+	return z_thread_alloc_helper(align, size, sys_heap_aligned_alloc);
+}
+
+void *z_thread_malloc(size_t size)
+{
+	return z_thread_alloc_helper(0, size, sys_heap_noalign_alloc);
+}
diff --git a/kernel/msg_q.c b/kernel/msg_q.c
index 3998c235108..7b8686ffa63 100644
--- a/kernel/msg_q.c
+++ b/kernel/msg_q.c
@@ -29,12 +29,16 @@
 static struct k_obj_type obj_type_msgq;
 #endif /* CONFIG_OBJ_CORE_MSGQ */
 
-#ifdef CONFIG_POLL
-static inline void handle_poll_events(struct k_msgq *msgq, uint32_t state)
+static inline bool handle_poll_events(struct k_msgq *msgq)
 {
-	z_handle_obj_poll_events(&msgq->poll_events, state);
-}
+#ifdef CONFIG_POLL
+	return z_handle_obj_poll_events(&msgq->poll_events,
+					K_POLL_STATE_MSGQ_DATA_AVAILABLE);
+#else
+	ARG_UNUSED(msgq);
+	return false;
 #endif /* CONFIG_POLL */
+}
 
 void k_msgq_init(struct k_msgq *msgq, char *buffer, size_t msg_size,
 		 uint32_t max_msgs)
@@ -128,6 +132,7 @@ int z_impl_k_msgq_put(struct k_msgq *msgq, const void *data, k_timeout_t timeout
 	struct k_thread *pending_thread;
 	k_spinlock_key_t key;
 	int result;
+	bool resched = false;
 
 	key = k_spin_lock(&msgq->lock);
 
@@ -137,16 +142,13 @@ int z_impl_k_msgq_put(struct k_msgq *msgq, const void *data, k_timeout_t timeout
 		/* message queue isn't full */
 		pending_thread = z_unpend_first_thread(&msgq->wait_q);
 		if (unlikely(pending_thread != NULL)) {
-			SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_msgq, put, msgq, timeout, 0);
+			resched = true;
 
 			/* give message to waiting thread */
-			(void)memcpy(pending_thread->base.swap_data, data,
-			       msgq->msg_size);
+			(void)memcpy(pending_thread->base.swap_data, data, msgq->msg_size);
 			/* wake up waiting thread */
 			arch_thread_return_value_set(pending_thread, 0);
 			z_ready_thread(pending_thread);
-			z_reschedule(&msgq->lock, key);
-			return 0;
 		} else {
 			/* put message in queue */
 			__ASSERT_NO_MSG(msgq->write_ptr >= msgq->buffer_start &&
@@ -157,9 +159,7 @@ int z_impl_k_msgq_put(struct k_msgq *msgq, const void *data, k_timeout_t timeout
 				msgq->write_ptr = msgq->buffer_start;
 			}
 			msgq->used_msgs++;
-#ifdef CONFIG_POLL
-			handle_poll_events(msgq, K_POLL_STATE_MSGQ_DATA_AVAILABLE);
-#endif /* CONFIG_POLL */
+			resched = handle_poll_events(msgq);
 		}
 		result = 0;
 	} else if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
@@ -178,7 +178,11 @@ int z_impl_k_msgq_put(struct k_msgq *msgq, const void *data, k_timeout_t timeout
 
 	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_msgq, put, msgq, timeout, result);
 
-	z_reschedule(&msgq->lock, key);
+	if (resched) {
+		z_reschedule(&msgq->lock, key);
+	} else {
+		k_spin_unlock(&msgq->lock, key);
+	}
 
 	return result;
 }
@@ -220,6 +224,7 @@ int z_impl_k_msgq_get(struct k_msgq *msgq, void *data, k_timeout_t timeout)
 	k_spinlock_key_t key;
 	struct k_thread *pending_thread;
 	int result;
+	bool resched = false;
 
 	key = k_spin_lock(&msgq->lock);
 
@@ -253,11 +258,7 @@ int z_impl_k_msgq_get(struct k_msgq *msgq, void *data, k_timeout_t timeout)
 			/* wake up waiting thread */
 			arch_thread_return_value_set(pending_thread, 0);
 			z_ready_thread(pending_thread);
-			z_reschedule(&msgq->lock, key);
-
-			SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_msgq, get, msgq, timeout, 0);
-
-			return 0;
+			resched = true;
 		}
 		result = 0;
 	} else if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
@@ -276,7 +277,11 @@ int z_impl_k_msgq_get(struct k_msgq *msgq, void *data, k_timeout_t timeout)
 
 	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_msgq, get, msgq, timeout, result);
 
-	k_spin_unlock(&msgq->lock, key);
+	if (resched) {
+		z_reschedule(&msgq->lock, key);
+	} else {
+		k_spin_unlock(&msgq->lock, key);
+	}
 
 	return result;
 }
@@ -377,22 +382,29 @@ void z_impl_k_msgq_purge(struct k_msgq *msgq)
 {
 	k_spinlock_key_t key;
 	struct k_thread *pending_thread;
+	bool resched = false;
 
 	key = k_spin_lock(&msgq->lock);
 
 	SYS_PORT_TRACING_OBJ_FUNC(k_msgq, purge, msgq);
 
 	/* wake up any threads that are waiting to write */
-	for (pending_thread = z_unpend_first_thread(&msgq->wait_q); pending_thread != NULL;
-		 pending_thread = z_unpend_first_thread(&msgq->wait_q)) {
+	for (pending_thread = z_unpend_first_thread(&msgq->wait_q);
+	     pending_thread != NULL;
+	     pending_thread = z_unpend_first_thread(&msgq->wait_q)) {
 		arch_thread_return_value_set(pending_thread, -ENOMSG);
 		z_ready_thread(pending_thread);
+		resched = true;
 	}
 
 	msgq->used_msgs = 0;
 	msgq->read_ptr = msgq->write_ptr;
 
-	z_reschedule(&msgq->lock, key);
+	if (resched) {
+		z_reschedule(&msgq->lock, key);
+	} else {
+		k_spin_unlock(&msgq->lock, key);
+	}
 }
 
 #ifdef CONFIG_USERSPACE
diff --git a/kernel/pipe.c b/kernel/pipe.c
new file mode 100644
index 00000000000..c5157ea6921
--- /dev/null
+++ b/kernel/pipe.c
@@ -0,0 +1,358 @@
+/*
+ * Copyright (c) 2024 Måns Ansgariusson <mansgariusson@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/internal/syscall_handler.h>
+#include <ksched.h>
+#include <kthread.h>
+#include <wait_q.h>
+
+#ifdef CONFIG_OBJ_CORE_PIPE
+static struct k_obj_type obj_type_pipe;
+#endif /* CONFIG_OBJ_CORE_PIPE */
+
+static inline bool pipe_closed(struct k_pipe *pipe)
+{
+	return (pipe->flags & PIPE_FLAG_OPEN) == 0;
+}
+
+static inline bool pipe_resetting(struct k_pipe *pipe)
+{
+	return (pipe->flags & PIPE_FLAG_RESET) != 0;
+}
+
+static inline bool pipe_full(struct k_pipe *pipe)
+{
+	return ring_buf_space_get(&pipe->buf) == 0;
+}
+
+static inline bool pipe_empty(struct k_pipe *pipe)
+{
+	return ring_buf_is_empty(&pipe->buf);
+}
+
+static int wait_for(_wait_q_t *waitq, struct k_pipe *pipe, k_spinlock_key_t *key,
+		    k_timepoint_t time_limit, bool *need_resched)
+{
+	k_timeout_t timeout = sys_timepoint_timeout(time_limit);
+	int rc;
+
+	if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
+		return -EAGAIN;
+	}
+
+	pipe->waiting++;
+	*need_resched = false;
+	if (waitq == &pipe->space) {
+		SYS_PORT_TRACING_OBJ_FUNC_BLOCKING(k_pipe, write, pipe, timeout);
+	} else {
+		SYS_PORT_TRACING_OBJ_FUNC_BLOCKING(k_pipe, read, pipe, timeout);
+	}
+	rc = z_pend_curr(&pipe->lock, *key, waitq, timeout);
+	*key = k_spin_lock(&pipe->lock);
+	pipe->waiting--;
+	if (unlikely(pipe_resetting(pipe))) {
+		if (pipe->waiting == 0) {
+			pipe->flags &= ~PIPE_FLAG_RESET;
+		}
+		rc = -ECANCELED;
+	}
+
+	return rc;
+}
+
+void z_impl_k_pipe_init(struct k_pipe *pipe, uint8_t *buffer, size_t buffer_size)
+{
+	ring_buf_init(&pipe->buf, buffer_size, buffer);
+	pipe->flags = PIPE_FLAG_OPEN;
+	pipe->waiting = 0;
+
+	pipe->lock = (struct k_spinlock){};
+	z_waitq_init(&pipe->data);
+	z_waitq_init(&pipe->space);
+	k_object_init(pipe);
+
+#ifdef CONFIG_POLL
+	sys_dlist_init(&pipe->poll_events);
+#endif /* CONFIG_POLL */
+#ifdef CONFIG_OBJ_CORE_PIPE
+	k_obj_core_init_and_link(K_OBJ_CORE(pipe), &obj_type_pipe);
+#endif /* CONFIG_OBJ_CORE_PIPE */
+	SYS_PORT_TRACING_OBJ_INIT(k_pipe, pipe, buffer, buffer_size);
+}
+
+struct pipe_buf_spec {
+	uint8_t * const data;
+	const size_t len;
+	size_t used;
+};
+
+static size_t copy_to_pending_readers(struct k_pipe *pipe, bool *need_resched,
+				      const uint8_t *data, size_t len)
+{
+	struct k_thread *reader = NULL;
+	struct pipe_buf_spec *reader_buf;
+	size_t copy_size, written = 0;
+
+	/*
+	 * Attempt a direct data copy to waiting readers if any.
+	 * The copy has to be done under the scheduler lock to ensure all the
+	 * needed data is copied to the target thread whose buffer spec lives
+	 * on that thread's stack, and then the thread unpended only if it
+	 * received all the data it wanted, without racing with a potential
+	 * thread timeout/cancellation event.
+	 */
+	do {
+		LOCK_SCHED_SPINLOCK {
+			reader = _priq_wait_best(&pipe->data.waitq);
+			if (reader == NULL) {
+				K_SPINLOCK_BREAK;
+			}
+
+			reader_buf = reader->base.swap_data;
+			copy_size = MIN(len - written,
+					reader_buf->len - reader_buf->used);
+			memcpy(&reader_buf->data[reader_buf->used],
+			       &data[written], copy_size);
+			written += copy_size;
+			reader_buf->used += copy_size;
+
+			if (reader_buf->used < reader_buf->len) {
+				/* This reader wants more: don't unpend. */
+				reader = NULL;
+			} else {
+				/*
+				 * This reader has received all the data
+				 * it was waiting for: wake it up with
+				 * the scheduler lock still held.
+				 */
+				unpend_thread_no_timeout(reader);
+				z_abort_thread_timeout(reader);
+			}
+		}
+		if (reader != NULL) {
+			/* rest of thread wake-up outside the scheduler lock */
+			z_thread_return_value_set_with_data(reader, 0, NULL);
+			z_ready_thread(reader);
+			*need_resched = true;
+		}
+	} while (reader != NULL && written < len);
+
+	return written;
+}
+
+int z_impl_k_pipe_write(struct k_pipe *pipe, const uint8_t *data, size_t len, k_timeout_t timeout)
+{
+	int rc;
+	size_t written = 0;
+	k_timepoint_t end = sys_timepoint_calc(timeout);
+	k_spinlock_key_t key = k_spin_lock(&pipe->lock);
+	bool need_resched = false;
+
+	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_pipe, write, pipe, data, len, timeout);
+
+	if (unlikely(pipe_resetting(pipe))) {
+		rc = -ECANCELED;
+		goto exit;
+	}
+
+	for (;;) {
+		if (unlikely(pipe_closed(pipe))) {
+			rc = -EPIPE;
+			break;
+		}
+
+		if (pipe_empty(pipe)) {
+			if (IS_ENABLED(CONFIG_KERNEL_COHERENCE)) {
+				/*
+				 * Systems that enabled this option don't have
+				 * their stacks in coherent memory. Given our
+				 * pipe_buf_spec is stored on the stack, and
+				 * readers may also have their destination
+				 * buffer on their stack too, it is not worth
+				 * supporting direct-to-readers copy with them.
+				 * Simply wake up all pending readers instead.
+				 */
+				need_resched = z_sched_wake_all(&pipe->data, 0, NULL);
+			} else if (pipe->waiting != 0) {
+				written += copy_to_pending_readers(pipe, &need_resched,
+								   &data[written],
+								   len - written);
+				if (written >= len) {
+					rc = written;
+					break;
+				}
+			}
+		}
+
+#ifdef CONFIG_POLL
+		need_resched |= z_handle_obj_poll_events(&pipe->poll_events,
+							 K_POLL_STATE_PIPE_DATA_AVAILABLE);
+#endif /* CONFIG_POLL */
+
+		written += ring_buf_put(&pipe->buf, &data[written], len - written);
+		if (likely(written == len)) {
+			rc = written;
+			break;
+		}
+
+		rc = wait_for(&pipe->space, pipe, &key, end, &need_resched);
+		if (rc != 0) {
+			if (rc == -EAGAIN) {
+				rc = written ? written : -EAGAIN;
+			}
+			break;
+		}
+	}
+exit:
+	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_pipe, write, pipe, rc);
+	if (need_resched) {
+		z_reschedule(&pipe->lock, key);
+	} else {
+		k_spin_unlock(&pipe->lock, key);
+	}
+	return rc;
+}
+
+int z_impl_k_pipe_read(struct k_pipe *pipe, uint8_t *data, size_t len, k_timeout_t timeout)
+{
+	struct pipe_buf_spec buf = { data, len, 0 };
+	int rc;
+	k_timepoint_t end = sys_timepoint_calc(timeout);
+	k_spinlock_key_t key = k_spin_lock(&pipe->lock);
+	bool need_resched = false;
+
+	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_pipe, read, pipe, data, len, timeout);
+
+	if (unlikely(pipe_resetting(pipe))) {
+		rc = -ECANCELED;
+		goto exit;
+	}
+
+	for (;;) {
+		if (pipe_full(pipe)) {
+			/* One or more pending writers may exist. */
+			need_resched = z_sched_wake_all(&pipe->space, 0, NULL);
+		}
+
+		buf.used += ring_buf_get(&pipe->buf, &data[buf.used], len - buf.used);
+		if (likely(buf.used == len)) {
+			rc = buf.used;
+			break;
+		}
+
+		if (unlikely(pipe_closed(pipe))) {
+			rc = buf.used ? buf.used : -EPIPE;
+			break;
+		}
+
+		/* provide our "direct copy" info to potential writers */
+		_current->base.swap_data = &buf;
+
+		rc = wait_for(&pipe->data, pipe, &key, end, &need_resched);
+		if (rc != 0) {
+			if (rc == -EAGAIN) {
+				rc = buf.used ? buf.used : -EAGAIN;
+			}
+			break;
+		}
+	}
+exit:
+	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_pipe, read, pipe, rc);
+	if (need_resched) {
+		z_reschedule(&pipe->lock, key);
+	} else {
+		k_spin_unlock(&pipe->lock, key);
+	}
+	return rc;
+}
+
+void z_impl_k_pipe_reset(struct k_pipe *pipe)
+{
+	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_pipe, reset, pipe);
+	K_SPINLOCK(&pipe->lock) {
+		ring_buf_reset(&pipe->buf);
+		if (likely(pipe->waiting != 0)) {
+			pipe->flags |= PIPE_FLAG_RESET;
+			z_sched_wake_all(&pipe->data, 0, NULL);
+			z_sched_wake_all(&pipe->space, 0, NULL);
+		}
+	}
+	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_pipe, reset, pipe);
+}
+
+void z_impl_k_pipe_close(struct k_pipe *pipe)
+{
+	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_pipe, close, pipe);
+	K_SPINLOCK(&pipe->lock) {
+		pipe->flags = 0;
+		z_sched_wake_all(&pipe->data, 0, NULL);
+		z_sched_wake_all(&pipe->space, 0, NULL);
+	}
+	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_pipe, close, pipe);
+}
+
+#ifdef CONFIG_USERSPACE
+void z_vrfy_k_pipe_init(struct k_pipe *pipe, uint8_t *buffer, size_t buffer_size)
+{
+	K_OOPS(K_SYSCALL_OBJ(pipe, K_OBJ_PIPE));
+	K_OOPS(K_SYSCALL_MEMORY_WRITE(buffer, buffer_size));
+
+	z_impl_k_pipe_init(pipe, buffer, buffer_size);
+}
+#include <zephyr/syscalls/k_pipe_init_mrsh.c>
+
+int z_vrfy_k_pipe_read(struct k_pipe *pipe, uint8_t *data, size_t len, k_timeout_t timeout)
+{
+	K_OOPS(K_SYSCALL_OBJ(pipe, K_OBJ_PIPE));
+	K_OOPS(K_SYSCALL_MEMORY_WRITE(data, len));
+
+	return z_impl_k_pipe_read(pipe, data, len, timeout);
+}
+#include <zephyr/syscalls/k_pipe_read_mrsh.c>
+
+int z_vrfy_k_pipe_write(struct k_pipe *pipe, const uint8_t *data, size_t len, k_timeout_t timeout)
+{
+	K_OOPS(K_SYSCALL_OBJ(pipe, K_OBJ_PIPE));
+	K_OOPS(K_SYSCALL_MEMORY_READ(data, len));
+
+	return z_impl_k_pipe_write(pipe, data, len, timeout);
+}
+#include <zephyr/syscalls/k_pipe_write_mrsh.c>
+
+void z_vrfy_k_pipe_reset(struct k_pipe *pipe)
+{
+	K_OOPS(K_SYSCALL_OBJ(pipe, K_OBJ_PIPE));
+	z_impl_k_pipe_reset(pipe);
+}
+#include <zephyr/syscalls/k_pipe_reset_mrsh.c>
+
+void z_vrfy_k_pipe_close(struct k_pipe *pipe)
+{
+	K_OOPS(K_SYSCALL_OBJ(pipe, K_OBJ_PIPE));
+	z_impl_k_pipe_close(pipe);
+}
+#include <zephyr/syscalls/k_pipe_close_mrsh.c>
+#endif /* CONFIG_USERSPACE */
+
+#ifdef CONFIG_OBJ_CORE_PIPE
+static int init_pipe_obj_core_list(void)
+{
+	/* Initialize pipe object type */
+	z_obj_type_init(&obj_type_pipe, K_OBJ_TYPE_PIPE_ID,
+			offsetof(struct k_pipe, obj_core));
+
+	/* Initialize and link statically defined pipes */
+	STRUCT_SECTION_FOREACH(k_pipe, pipe) {
+		k_obj_core_init_and_link(K_OBJ_CORE(pipe), &obj_type_pipe);
+	}
+
+	return 0;
+}
+
+SYS_INIT(init_pipe_obj_core_list, PRE_KERNEL_1,
+	 CONFIG_KERNEL_INIT_PRIORITY_OBJECTS);
+#endif /* CONFIG_OBJ_CORE_PIPE */
diff --git a/kernel/pipes.c b/kernel/pipes.c
index a81393c508d..11d0d936f6b 100644
--- a/kernel/pipes.c
+++ b/kernel/pipes.c
@@ -36,7 +36,7 @@ static struct k_obj_type obj_type_pipe;
 #endif /* CONFIG_OBJ_CORE_PIPE */
 
 
-void k_pipe_init(struct k_pipe *pipe, unsigned char *buffer, size_t size)
+void z_impl_k_pipe_init(struct k_pipe *pipe, unsigned char *buffer, size_t size)
 {
 	pipe->buffer = buffer;
 	pipe->size = size;
@@ -46,7 +46,7 @@ void k_pipe_init(struct k_pipe *pipe, unsigned char *buffer, size_t size)
 	pipe->lock = (struct k_spinlock){};
 	z_waitq_init(&pipe->wait_q.writers);
 	z_waitq_init(&pipe->wait_q.readers);
-	SYS_PORT_TRACING_OBJ_INIT(k_pipe, pipe);
+	SYS_PORT_TRACING_OBJ_INIT(k_pipe, pipe, buffer, size);
 
 	pipe->flags = 0;
 
@@ -87,6 +87,15 @@ int z_impl_k_pipe_alloc_init(struct k_pipe *pipe, size_t size)
 }
 
 #ifdef CONFIG_USERSPACE
+static inline void z_vrfy_k_pipe_init(struct k_pipe *pipe, unsigned char *buffer, size_t size)
+{
+	K_OOPS(K_SYSCALL_OBJ_NEVER_INIT(pipe, K_OBJ_PIPE));
+	K_OOPS(K_SYSCALL_MEMORY_WRITE(buffer, size));
+
+	z_impl_k_pipe_init(pipe, buffer, size);
+}
+#include <zephyr/syscalls/k_pipe_init_mrsh.c>
+
 static inline int z_vrfy_k_pipe_alloc_init(struct k_pipe *pipe, size_t size)
 {
 	K_OOPS(K_SYSCALL_OBJ_NEVER_INIT(pipe, K_OBJ_PIPE));
@@ -96,12 +105,13 @@ static inline int z_vrfy_k_pipe_alloc_init(struct k_pipe *pipe, size_t size)
 #include <zephyr/syscalls/k_pipe_alloc_init_mrsh.c>
 #endif /* CONFIG_USERSPACE */
 
-static inline void handle_poll_events(struct k_pipe *pipe)
+static inline bool handle_poll_events(struct k_pipe *pipe)
 {
 #ifdef CONFIG_POLL
-	z_handle_obj_poll_events(&pipe->poll_events, K_POLL_STATE_PIPE_DATA_AVAILABLE);
+	return z_handle_obj_poll_events(&pipe->poll_events, K_POLL_STATE_PIPE_DATA_AVAILABLE);
 #else
 	ARG_UNUSED(pipe);
+	return false;
 #endif /* CONFIG_POLL */
 }
 
@@ -459,7 +469,7 @@ int z_impl_k_pipe_put(struct k_pipe *pipe, const void *data,
 	 */
 
 	if ((pipe->bytes_used != 0U) && (*bytes_written != 0U)) {
-		handle_poll_events(pipe);
+		reschedule_needed = handle_poll_events(pipe) || reschedule_needed;
 	}
 
 	/*
diff --git a/kernel/poll.c b/kernel/poll.c
index 502e97537b9..b6e20b24c3a 100644
--- a/kernel/poll.c
+++ b/kernel/poll.c
@@ -87,13 +87,16 @@ static inline bool is_condition_met(struct k_poll_event *event, uint32_t *state)
 			return true;
 		}
 		break;
-#ifdef CONFIG_PIPES
 	case K_POLL_TYPE_PIPE_DATA_AVAILABLE:
-		if (k_pipe_read_avail(event->pipe)) {
+#ifdef CONFIG_PIPES
+		if (event->pipe->bytes_used != 0) {
+#else
+		if (!ring_buf_is_empty(&event->pipe->buf)) {
+#endif
 			*state = K_POLL_STATE_PIPE_DATA_AVAILABLE;
 			return true;
 		}
-#endif /* CONFIG_PIPES */
+		break;
 	case K_POLL_TYPE_IGNORE:
 		break;
 	default:
@@ -154,12 +157,10 @@ static inline void register_event(struct k_poll_event *event,
 		__ASSERT(event->msgq != NULL, "invalid message queue\n");
 		add_event(&event->msgq->poll_events, event, poller);
 		break;
-#ifdef CONFIG_PIPES
 	case K_POLL_TYPE_PIPE_DATA_AVAILABLE:
 		__ASSERT(event->pipe != NULL, "invalid pipe\n");
 		add_event(&event->pipe->poll_events, event, poller);
 		break;
-#endif /* CONFIG_PIPES */
 	case K_POLL_TYPE_IGNORE:
 		/* nothing to do */
 		break;
@@ -195,12 +196,10 @@ static inline void clear_event_registration(struct k_poll_event *event)
 		__ASSERT(event->msgq != NULL, "invalid message queue\n");
 		remove_event = true;
 		break;
-#ifdef CONFIG_PIPES
 	case K_POLL_TYPE_PIPE_DATA_AVAILABLE:
 		__ASSERT(event->pipe != NULL, "invalid pipe\n");
 		remove_event = true;
 		break;
-#endif /* CONFIG_PIPES */
 	case K_POLL_TYPE_IGNORE:
 		/* nothing to do */
 		break;
@@ -413,11 +412,9 @@ static inline int z_vrfy_k_poll(struct k_poll_event *events,
 		case K_POLL_TYPE_MSGQ_DATA_AVAILABLE:
 			K_OOPS(K_SYSCALL_OBJ(e->msgq, K_OBJ_MSGQ));
 			break;
-#ifdef CONFIG_PIPES
 		case K_POLL_TYPE_PIPE_DATA_AVAILABLE:
 			K_OOPS(K_SYSCALL_OBJ(e->pipe, K_OBJ_PIPE));
 			break;
-#endif /* CONFIG_PIPES */
 		default:
 			ret = -EINVAL;
 			goto out_free;
@@ -464,7 +461,7 @@ static int signal_poll_event(struct k_poll_event *event, uint32_t state)
 	return retcode;
 }
 
-void z_handle_obj_poll_events(sys_dlist_t *events, uint32_t state)
+bool z_handle_obj_poll_events(sys_dlist_t *events, uint32_t state)
 {
 	struct k_poll_event *poll_event;
 	k_spinlock_key_t key = k_spin_lock(&lock);
@@ -475,6 +472,8 @@ void z_handle_obj_poll_events(sys_dlist_t *events, uint32_t state)
 	}
 
 	k_spin_unlock(&lock, key);
+
+	return (poll_event != NULL);
 }
 
 void z_impl_k_poll_signal_init(struct k_poll_signal *sig)
@@ -675,7 +674,7 @@ int k_work_poll_submit_to_queue(struct k_work_q *work_q,
 	__ASSERT(work_q != NULL, "NULL work_q\n");
 	__ASSERT(work != NULL, "NULL work\n");
 	__ASSERT(events != NULL, "NULL events\n");
-	__ASSERT(num_events > 0, "zero events\n");
+	__ASSERT(num_events >= 0, "<0 events\n");
 
 	SYS_PORT_TRACING_FUNC_ENTER(k_work_poll, submit_to_queue, work_q, work, timeout);
 
diff --git a/kernel/queue.c b/kernel/queue.c
index 4b00deeb1e7..af643787994 100644
--- a/kernel/queue.c
+++ b/kernel/queue.c
@@ -84,13 +84,15 @@ static void prepare_thread_to_run(struct k_thread *thread, void *data)
 	z_ready_thread(thread);
 }
 
-static inline void handle_poll_events(struct k_queue *queue, uint32_t state)
+static inline bool handle_poll_events(struct k_queue *queue, uint32_t state)
 {
 #ifdef CONFIG_POLL
-	z_handle_obj_poll_events(&queue->poll_events, state);
+	return z_handle_obj_poll_events(&queue->poll_events, state);
 #else
 	ARG_UNUSED(queue);
 	ARG_UNUSED(state);
+
+	return false;
 #endif /* CONFIG_POLL */
 }
 
@@ -100,15 +102,22 @@ void z_impl_k_queue_cancel_wait(struct k_queue *queue)
 
 	k_spinlock_key_t key = k_spin_lock(&queue->lock);
 	struct k_thread *first_pending_thread;
+	bool resched = false;
 
 	first_pending_thread = z_unpend_first_thread(&queue->wait_q);
 
 	if (first_pending_thread != NULL) {
+		resched = true;
 		prepare_thread_to_run(first_pending_thread, NULL);
 	}
 
-	handle_poll_events(queue, K_POLL_STATE_CANCELLED);
-	z_reschedule(&queue->lock, key);
+	resched = handle_poll_events(queue, K_POLL_STATE_CANCELLED) || resched;
+
+	if (resched) {
+		z_reschedule(&queue->lock, key);
+	} else {
+		k_spin_unlock(&queue->lock, key);
+	}
 }
 
 #ifdef CONFIG_USERSPACE
@@ -125,6 +134,8 @@ static int32_t queue_insert(struct k_queue *queue, void *prev, void *data,
 {
 	struct k_thread *first_pending_thread;
 	k_spinlock_key_t key = k_spin_lock(&queue->lock);
+	int32_t result = 0;
+	bool resched = false;
 
 	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_queue, queue_insert, queue, alloc);
 
@@ -137,11 +148,8 @@ static int32_t queue_insert(struct k_queue *queue, void *prev, void *data,
 		SYS_PORT_TRACING_OBJ_FUNC_BLOCKING(k_queue, queue_insert, queue, alloc, K_FOREVER);
 
 		prepare_thread_to_run(first_pending_thread, data);
-		z_reschedule(&queue->lock, key);
-
-		SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_queue, queue_insert, queue, alloc, 0);
-
-		return 0;
+		resched = true;
+		goto out;
 	}
 
 	/* Only need to actually allocate if no threads are pending */
@@ -150,12 +158,8 @@ static int32_t queue_insert(struct k_queue *queue, void *prev, void *data,
 
 		anode = z_thread_malloc(sizeof(*anode));
 		if (anode == NULL) {
-			k_spin_unlock(&queue->lock, key);
-
-			SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_queue, queue_insert, queue, alloc,
-				-ENOMEM);
-
-			return -ENOMEM;
+			result = -ENOMEM;
+			goto out;
 		}
 		anode->data = data;
 		sys_sfnode_init(&anode->node, 0x1);
@@ -167,12 +171,18 @@ static int32_t queue_insert(struct k_queue *queue, void *prev, void *data,
 	SYS_PORT_TRACING_OBJ_FUNC_BLOCKING(k_queue, queue_insert, queue, alloc, K_FOREVER);
 
 	sys_sflist_insert(&queue->data_q, prev, data);
-	handle_poll_events(queue, K_POLL_STATE_DATA_AVAILABLE);
-	z_reschedule(&queue->lock, key);
+	resched = handle_poll_events(queue, K_POLL_STATE_DATA_AVAILABLE);
 
-	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_queue, queue_insert, queue, alloc, 0);
+out:
+	if (resched) {
+		z_reschedule(&queue->lock, key);
+	} else {
+		k_spin_unlock(&queue->lock, key);
+	}
 
-	return 0;
+	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_queue, queue_insert, queue, alloc, result);
+
+	return result;
 }
 
 void k_queue_insert(struct k_queue *queue, void *prev, void *data)
@@ -247,6 +257,7 @@ static inline int32_t z_vrfy_k_queue_alloc_prepend(struct k_queue *queue,
 int k_queue_append_list(struct k_queue *queue, void *head, void *tail)
 {
 	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_queue, append_list, queue);
+	bool resched = false;
 
 	/* invalid head or tail of list */
 	CHECKIF((head == NULL) || (tail == NULL)) {
@@ -263,6 +274,7 @@ int k_queue_append_list(struct k_queue *queue, void *head, void *tail)
 	}
 
 	while ((head != NULL) && (thread != NULL)) {
+		resched = true;
 		prepare_thread_to_run(thread, head);
 		head = *(void **)head;
 		thread = z_unpend_first_thread(&queue->wait_q);
@@ -274,8 +286,14 @@ int k_queue_append_list(struct k_queue *queue, void *head, void *tail)
 
 	SYS_PORT_TRACING_OBJ_FUNC_EXIT(k_queue, append_list, queue, 0);
 
-	handle_poll_events(queue, K_POLL_STATE_DATA_AVAILABLE);
-	z_reschedule(&queue->lock, key);
+	resched = handle_poll_events(queue, K_POLL_STATE_DATA_AVAILABLE) || resched;
+
+	if (resched) {
+		z_reschedule(&queue->lock, key);
+	} else {
+		k_spin_unlock(&queue->lock, key);
+	}
+
 	return 0;
 }
 
diff --git a/kernel/sched.c b/kernel/sched.c
index e0b4f35938c..995ded3d322 100644
--- a/kernel/sched.c
+++ b/kernel/sched.c
@@ -273,7 +273,7 @@ static void update_metairq_preempt(struct k_thread *thread)
 	    !thread_is_preemptible(_current)) {
 		/* Record new preemption */
 		_current_cpu->metairq_preempted = _current;
-	} else if (!thread_is_metairq(thread) && !z_is_idle_thread_object(thread)) {
+	} else if (!thread_is_metairq(thread)) {
 		/* Returning from existing preemption */
 		_current_cpu->metairq_preempted = NULL;
 	}
@@ -433,6 +433,11 @@ static ALWAYS_INLINE void z_thread_halt(struct k_thread *thread, k_spinlock_key_
 	} else {
 		halt_thread(thread, terminate ? _THREAD_DEAD : _THREAD_SUSPENDED);
 		if ((thread == _current) && !arch_is_in_isr()) {
+			if (z_is_thread_essential(thread)) {
+				k_spin_unlock(&_sched_spinlock, key);
+				k_panic();
+				key = k_spin_lock(&_sched_spinlock);
+			}
 			z_swap(&_sched_spinlock, key);
 			__ASSERT(!terminate, "aborted _current back from dead");
 		} else {
@@ -453,7 +458,7 @@ void z_impl_k_thread_suspend(k_tid_t thread)
 	/* Special case "suspend the current thread" as it doesn't
 	 * need the async complexity below.
 	 */
-	if (thread == _current && !arch_is_in_isr() && !IS_ENABLED(CONFIG_SMP)) {
+	if (!IS_ENABLED(CONFIG_SMP) && (thread == _current) && !arch_is_in_isr()) {
 		k_spinlock_key_t key = k_spin_lock(&_sched_spinlock);
 
 		z_mark_thread_as_suspended(thread);
@@ -652,7 +657,7 @@ struct k_thread *z_unpend1_no_timeout(_wait_q_t *wait_q)
 void z_unpend_thread(struct k_thread *thread)
 {
 	z_unpend_thread_no_timeout(thread);
-	(void)z_abort_thread_timeout(thread);
+	z_abort_thread_timeout(thread);
 }
 
 /* Priority set utility that does no rescheduling, it just changes the
@@ -694,6 +699,16 @@ bool z_thread_prio_set(struct k_thread *thread, int prio)
 			}
 
 			update_cache(1);
+		} else if (z_is_thread_pending(thread)) {
+			/* Thread is pending, remove it from the waitq
+			 * and reinsert it with the new priority to avoid
+			 * violating waitq ordering and rb assumptions.
+			 */
+			_wait_q_t *wait_q = pended_on_thread(thread);
+
+			_priq_wait_remove(&wait_q->waitq, thread);
+			thread->base.prio = prio;
+			_priq_wait_add(&wait_q->waitq, thread);
 		} else {
 			thread->base.prio = prio;
 		}
@@ -1031,6 +1046,7 @@ static inline void z_vrfy_k_reschedule(void)
 {
 	z_impl_k_reschedule();
 }
+#include <zephyr/syscalls/k_reschedule_mrsh.c>
 #endif /* CONFIG_USERSPACE */
 
 bool k_can_yield(void)
@@ -1047,9 +1063,6 @@ void z_impl_k_yield(void)
 
 	k_spinlock_key_t key = k_spin_lock(&_sched_spinlock);
 
-#ifdef CONFIG_SMP
-	z_mark_thread_as_queued(_current);
-#endif
 	runq_yield();
 
 	update_cache(1);
@@ -1078,23 +1091,21 @@ static int32_t z_tick_sleep(k_timeout_t timeout)
 		return 0;
 	}
 
-	if (Z_IS_TIMEOUT_RELATIVE(timeout)) {
-		expected_wakeup_ticks = timeout.ticks + sys_clock_tick_get_32();
-	} else {
-		expected_wakeup_ticks = Z_TICK_ABS(timeout.ticks);
-	}
-
 	k_spinlock_key_t key = k_spin_lock(&_sched_spinlock);
 
 #if defined(CONFIG_TIMESLICING) && defined(CONFIG_SWAP_NONATOMIC)
 	pending_current = _current;
 #endif /* CONFIG_TIMESLICING && CONFIG_SWAP_NONATOMIC */
 	unready_thread(_current);
-	z_add_thread_timeout(_current, timeout);
+	expected_wakeup_ticks = (uint32_t)z_add_thread_timeout(_current, timeout);
 	z_mark_thread_as_sleeping(_current);
 
 	(void)z_swap(&_sched_spinlock, key);
 
+	if (!z_is_aborted_thread_timeout(_current)) {
+		return 0;
+	}
+
 	/* We require a 32 bit unsigned subtraction to care a wraparound */
 	uint32_t left_ticks = expected_wakeup_ticks - sys_clock_tick_get_32();
 
@@ -1118,12 +1129,12 @@ int32_t z_impl_k_sleep(k_timeout_t timeout)
 
 	ticks = z_tick_sleep(timeout);
 
-	int32_t ret = K_TIMEOUT_EQ(timeout, K_FOREVER) ? K_TICKS_FOREVER :
-		      k_ticks_to_ms_ceil64(ticks);
+	/* k_sleep() still returns 32 bit milliseconds for compatibility */
+	int64_t ms = K_TIMEOUT_EQ(timeout, K_FOREVER) ? K_TICKS_FOREVER :
+		CLAMP(k_ticks_to_ms_ceil64(ticks), 0, INT_MAX);
 
-	SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, ret);
-
-	return ret;
+	SYS_PORT_TRACING_FUNC_EXIT(k_thread, sleep, timeout, ms);
+	return (int32_t) ms;
 }
 
 #ifdef CONFIG_USERSPACE
@@ -1162,23 +1173,15 @@ void z_impl_k_wakeup(k_tid_t thread)
 {
 	SYS_PORT_TRACING_OBJ_FUNC(k_thread, wakeup, thread);
 
-	(void)z_abort_thread_timeout(thread);
-
 	k_spinlock_key_t  key = k_spin_lock(&_sched_spinlock);
 
-	if (!z_is_thread_sleeping(thread)) {
-		k_spin_unlock(&_sched_spinlock, key);
-		return;
-	}
-
-	z_mark_thread_as_not_sleeping(thread);
-
-	ready_thread(thread);
-
-	if (arch_is_in_isr()) {
-		k_spin_unlock(&_sched_spinlock, key);
-	} else {
+	if (z_is_thread_sleeping(thread)) {
+		z_abort_thread_timeout(thread);
+		z_mark_thread_as_not_sleeping(thread);
+		ready_thread(thread);
 		z_reschedule(&_sched_spinlock, key);
+	} else {
+		k_spin_unlock(&_sched_spinlock, key);
 	}
 }
 
@@ -1210,7 +1213,7 @@ static inline void unpend_all(_wait_q_t *wait_q)
 
 	for (thread = z_waitq_head(wait_q); thread != NULL; thread = z_waitq_head(wait_q)) {
 		unpend_thread_no_timeout(thread);
-		(void)z_abort_thread_timeout(thread);
+		z_abort_thread_timeout(thread);
 		arch_thread_return_value_set(thread, 0);
 		ready_thread(thread);
 	}
@@ -1245,7 +1248,7 @@ static ALWAYS_INLINE void halt_thread(struct k_thread *thread, uint8_t new_state
 			if (thread->base.pended_on != NULL) {
 				unpend_thread_no_timeout(thread);
 			}
-			(void)z_abort_thread_timeout(thread);
+			z_abort_thread_timeout(thread);
 			unpend_all(&thread->join_queue);
 
 			/* Edge case: aborting _current from within an
@@ -1324,21 +1327,20 @@ static ALWAYS_INLINE void halt_thread(struct k_thread *thread, uint8_t new_state
 
 void z_thread_abort(struct k_thread *thread)
 {
+	bool essential = z_is_thread_essential(thread);
 	k_spinlock_key_t key = k_spin_lock(&_sched_spinlock);
 
-	if (z_is_thread_essential(thread)) {
-		k_spin_unlock(&_sched_spinlock, key);
-		__ASSERT(false, "aborting essential thread %p", thread);
-		k_panic();
-		return;
-	}
-
 	if ((thread->base.thread_state & _THREAD_DEAD) != 0U) {
 		k_spin_unlock(&_sched_spinlock, key);
 		return;
 	}
 
 	z_thread_halt(thread, key, true);
+
+	if (essential) {
+		__ASSERT(!essential, "aborted essential thread %p", thread);
+		k_panic();
+	}
 }
 
 #if !defined(CONFIG_ARCH_HAS_THREAD_ABORT)
@@ -1456,7 +1458,7 @@ bool z_sched_wake(_wait_q_t *wait_q, int swap_retval, void *swap_data)
 							    swap_retval,
 							    swap_data);
 			unpend_thread_no_timeout(thread);
-			(void)z_abort_thread_timeout(thread);
+			z_abort_thread_timeout(thread);
 			ready_thread(thread);
 			ret = true;
 		}
diff --git a/kernel/sem.c b/kernel/sem.c
index 58d8a86f1e9..90876c834a3 100644
--- a/kernel/sem.c
+++ b/kernel/sem.c
@@ -85,8 +85,7 @@ int z_vrfy_k_sem_init(struct k_sem *sem, unsigned int initial_count,
 static inline bool handle_poll_events(struct k_sem *sem)
 {
 #ifdef CONFIG_POLL
-	z_handle_obj_poll_events(&sem->poll_events, K_POLL_STATE_SEM_AVAILABLE);
-	return true;
+	return z_handle_obj_poll_events(&sem->poll_events, K_POLL_STATE_SEM_AVAILABLE);
 #else
 	ARG_UNUSED(sem);
 	return false;
@@ -97,7 +96,7 @@ void z_impl_k_sem_give(struct k_sem *sem)
 {
 	k_spinlock_key_t key = k_spin_lock(&lock);
 	struct k_thread *thread;
-	bool resched = true;
+	bool resched;
 
 	SYS_PORT_TRACING_OBJ_FUNC_ENTER(k_sem, give, sem);
 
@@ -106,6 +105,7 @@ void z_impl_k_sem_give(struct k_sem *sem)
 	if (unlikely(thread != NULL)) {
 		arch_thread_return_value_set(thread, 0);
 		z_ready_thread(thread);
+		resched = true;
 	} else {
 		sem->count += (sem->count != sem->limit) ? 1U : 0U;
 		resched = handle_poll_events(sem);
@@ -167,12 +167,14 @@ void z_impl_k_sem_reset(struct k_sem *sem)
 {
 	struct k_thread *thread;
 	k_spinlock_key_t key = k_spin_lock(&lock);
+	bool resched = false;
 
 	while (true) {
 		thread = z_unpend_first_thread(&sem->wait_q);
 		if (thread == NULL) {
 			break;
 		}
+		resched = true;
 		arch_thread_return_value_set(thread, -EAGAIN);
 		z_ready_thread(thread);
 	}
@@ -180,9 +182,13 @@ void z_impl_k_sem_reset(struct k_sem *sem)
 
 	SYS_PORT_TRACING_OBJ_FUNC(k_sem, reset, sem);
 
-	handle_poll_events(sem);
+	resched = handle_poll_events(sem) || resched;
 
-	z_reschedule(&lock, key);
+	if (resched) {
+		z_reschedule(&lock, key);
+	} else {
+		k_spin_unlock(&lock, key);
+	}
 }
 
 #ifdef CONFIG_USERSPACE
diff --git a/kernel/spinlock_validate.c b/kernel/spinlock_validate.c
index cb7ff5a3e7f..103998dea2f 100644
--- a/kernel/spinlock_validate.c
+++ b/kernel/spinlock_validate.c
@@ -5,6 +5,7 @@
  */
 #include <kernel_internal.h>
 #include <zephyr/spinlock.h>
+#include <zephyr/llext/symbol.h>
 
 bool z_spin_lock_valid(struct k_spinlock *l)
 {
@@ -17,6 +18,7 @@ bool z_spin_lock_valid(struct k_spinlock *l)
 	}
 	return true;
 }
+EXPORT_SYMBOL(z_spin_lock_valid);
 
 bool z_spin_unlock_valid(struct k_spinlock *l)
 {
@@ -33,15 +35,18 @@ bool z_spin_unlock_valid(struct k_spinlock *l)
 	}
 	return true;
 }
+EXPORT_SYMBOL(z_spin_unlock_valid);
 
 void z_spin_lock_set_owner(struct k_spinlock *l)
 {
 	l->thread_cpu = _current_cpu->id | (uintptr_t)_current;
 }
+EXPORT_SYMBOL(z_spin_lock_set_owner);
 
 #ifdef CONFIG_KERNEL_COHERENCE
 bool z_spin_lock_mem_coherent(struct k_spinlock *l)
 {
 	return arch_mem_coherent((void *)l);
 }
+EXPORT_SYMBOL(z_spin_lock_mem_coherent);
 #endif /* CONFIG_KERNEL_COHERENCE */
diff --git a/kernel/system_work_q.c b/kernel/system_work_q.c
index 5cc26fd82e1..aa8c3de03ab 100644
--- a/kernel/system_work_q.c
+++ b/kernel/system_work_q.c
@@ -21,7 +21,7 @@ struct k_work_q k_sys_work_q;
 
 static int k_sys_work_q_init(void)
 {
-	struct k_work_queue_config cfg = {
+	static const struct k_work_queue_config cfg = {
 		.name = "sysworkq",
 		.no_yield = IS_ENABLED(CONFIG_SYSTEM_WORKQUEUE_NO_YIELD),
 		.essential = true,
diff --git a/kernel/thread.c b/kernel/thread.c
index c3535540a68..f77d70ce494 100644
--- a/kernel/thread.c
+++ b/kernel/thread.c
@@ -400,6 +400,7 @@ static char *setup_thread_stack(struct k_thread *new_thread,
 		stack_buf_start = K_KERNEL_STACK_BUFFER(stack);
 		stack_buf_size = stack_obj_size - K_KERNEL_STACK_RESERVED;
 
+#if defined(ARCH_KERNEL_STACK_RESERVED)
 		/* Zephyr treats stack overflow as an app bug.  But
 		 * this particular overflow can be seen by static
 		 * analysis so needs to be handled somehow.
@@ -407,7 +408,7 @@ static char *setup_thread_stack(struct k_thread *new_thread,
 		if (K_KERNEL_STACK_RESERVED > stack_obj_size) {
 			k_panic();
 		}
-
+#endif
 	}
 
 #ifdef CONFIG_THREAD_STACK_MEM_MAPPED
@@ -1123,3 +1124,30 @@ void k_thread_abort_cleanup_check_reuse(struct k_thread *thread)
 }
 
 #endif /* CONFIG_THREAD_ABORT_NEED_CLEANUP */
+
+void z_dummy_thread_init(struct k_thread *dummy_thread)
+{
+	dummy_thread->base.thread_state = _THREAD_DUMMY;
+#ifdef CONFIG_SCHED_CPU_MASK
+	dummy_thread->base.cpu_mask = -1;
+#endif /* CONFIG_SCHED_CPU_MASK */
+	dummy_thread->base.user_options = K_ESSENTIAL;
+#ifdef CONFIG_THREAD_STACK_INFO
+	dummy_thread->stack_info.start = 0U;
+	dummy_thread->stack_info.size = 0U;
+#endif /* CONFIG_THREAD_STACK_INFO */
+#ifdef CONFIG_USERSPACE
+	dummy_thread->mem_domain_info.mem_domain = &k_mem_domain_default;
+#endif /* CONFIG_USERSPACE */
+#if (K_HEAP_MEM_POOL_SIZE > 0)
+	k_thread_system_pool_assign(dummy_thread);
+#else
+	dummy_thread->resource_pool = NULL;
+#endif /* K_HEAP_MEM_POOL_SIZE */
+
+#ifdef CONFIG_TIMESLICE_PER_THREAD
+	dummy_thread->base.slice_ticks = 0;
+#endif /* CONFIG_TIMESLICE_PER_THREAD */
+
+	z_current_thread_set(dummy_thread);
+}
diff --git a/kernel/thread_monitor.c b/kernel/thread_monitor.c
index cba7d19e828..f6f7217b6f0 100644
--- a/kernel/thread_monitor.c
+++ b/kernel/thread_monitor.c
@@ -34,110 +34,77 @@ void z_thread_monitor_exit(struct k_thread *thread)
 	k_spin_unlock(&z_thread_monitor_lock, key);
 }
 
-
-void k_thread_foreach(k_thread_user_cb_t user_cb, void *user_data)
+/*
+ * Helper function to iterate over threads with optional filtering and locking behavior.
+ */
+static void thread_foreach_helper(k_thread_user_cb_t user_cb, void *user_data,
+		bool unlocked, bool filter_by_cpu, unsigned int cpu)
 {
 	struct k_thread *thread;
 	k_spinlock_key_t key;
 
 	__ASSERT(user_cb != NULL, "user_cb can not be NULL");
 
-	/*
-	 * Lock is needed to make sure that the _kernel.threads is not being
-	 * modified by the user_cb either directly or indirectly.
-	 * The indirect ways are through calling k_thread_create and
-	 * k_thread_abort from user_cb.
-	 */
-	key = k_spin_lock(&z_thread_monitor_lock);
+	if (filter_by_cpu) {
+		__ASSERT(cpu < CONFIG_MP_MAX_NUM_CPUS, "cpu filter out of bounds");
+	}
 
-	SYS_PORT_TRACING_FUNC_ENTER(k_thread, foreach);
+	key = k_spin_lock(&z_thread_monitor_lock);
 
 	for (thread = _kernel.threads; thread; thread = thread->next_thread) {
-		user_cb(thread, user_data);
-	}
+		/* cpu is only defined when SMP=y*/
+#ifdef CONFIG_SMP
+		bool on_cpu = (thread->base.cpu == cpu);
+#else
+		bool on_cpu = false;
+#endif
+		if (filter_by_cpu && !on_cpu) {
+			continue;
+		}
 
-	SYS_PORT_TRACING_FUNC_EXIT(k_thread, foreach);
+		if (unlocked) {
+			k_spin_unlock(&z_thread_monitor_lock, key);
+			user_cb(thread, user_data);
+			key = k_spin_lock(&z_thread_monitor_lock);
+		} else {
+			user_cb(thread, user_data);
+		}
+	}
 
 	k_spin_unlock(&z_thread_monitor_lock, key);
 }
 
-void k_thread_foreach_unlocked(k_thread_user_cb_t user_cb, void *user_data)
+/*
+ * Public API functions using the helper.
+ */
+void k_thread_foreach(k_thread_user_cb_t user_cb, void *user_data)
 {
-	struct k_thread *thread;
-	k_spinlock_key_t key;
-
-	__ASSERT(user_cb != NULL, "user_cb can not be NULL");
-
-	key = k_spin_lock(&z_thread_monitor_lock);
+	SYS_PORT_TRACING_FUNC_ENTER(k_thread, foreach);
+	thread_foreach_helper(user_cb, user_data, false, false, 0);
+	SYS_PORT_TRACING_FUNC_EXIT(k_thread, foreach);
+}
 
+void k_thread_foreach_unlocked(k_thread_user_cb_t user_cb, void *user_data)
+{
 	SYS_PORT_TRACING_FUNC_ENTER(k_thread, foreach_unlocked);
-
-	for (thread = _kernel.threads; thread; thread = thread->next_thread) {
-		k_spin_unlock(&z_thread_monitor_lock, key);
-		user_cb(thread, user_data);
-		key = k_spin_lock(&z_thread_monitor_lock);
-	}
-
+	thread_foreach_helper(user_cb, user_data, true, false, 0);
 	SYS_PORT_TRACING_FUNC_EXIT(k_thread, foreach_unlocked);
-
-	k_spin_unlock(&z_thread_monitor_lock, key);
-
 }
 
 #ifdef CONFIG_SMP
 void k_thread_foreach_filter_by_cpu(unsigned int cpu, k_thread_user_cb_t user_cb,
-				  void *user_data)
+		void *user_data)
 {
-	struct k_thread *thread;
-	k_spinlock_key_t key;
-
-	__ASSERT(user_cb != NULL, "user_cb can not be NULL");
-	__ASSERT(cpu < CONFIG_MP_MAX_NUM_CPUS, "cpu filter out of bounds");
-
-	/*
-	 * Lock is needed to make sure that the _kernel.threads is not being
-	 * modified by the user_cb either directly or indirectly.
-	 * The indirect ways are through calling k_thread_create and
-	 * k_thread_abort from user_cb.
-	 */
-	key = k_spin_lock(&z_thread_monitor_lock);
-
 	SYS_PORT_TRACING_FUNC_ENTER(k_thread, foreach);
-
-	for (thread = _kernel.threads; thread; thread = thread->next_thread) {
-		if (thread->base.cpu == cpu) {
-			user_cb(thread, user_data);
-		}
-	}
-
+	thread_foreach_helper(user_cb, user_data, false, true, cpu);
 	SYS_PORT_TRACING_FUNC_EXIT(k_thread, foreach);
-
-	k_spin_unlock(&z_thread_monitor_lock, key);
 }
 
 void k_thread_foreach_unlocked_filter_by_cpu(unsigned int cpu, k_thread_user_cb_t user_cb,
-					     void *user_data)
+		void *user_data)
 {
-	struct k_thread *thread;
-	k_spinlock_key_t key;
-
-	__ASSERT(user_cb != NULL, "user_cb can not be NULL");
-	__ASSERT(cpu < CONFIG_MP_MAX_NUM_CPUS, "cpu filter out of bounds");
-
-	key = k_spin_lock(&z_thread_monitor_lock);
-
 	SYS_PORT_TRACING_FUNC_ENTER(k_thread, foreach_unlocked);
-
-	for (thread = _kernel.threads; thread; thread = thread->next_thread) {
-		if (thread->base.cpu == cpu) {
-			k_spin_unlock(&z_thread_monitor_lock, key);
-			user_cb(thread, user_data);
-			key = k_spin_lock(&z_thread_monitor_lock);
-		}
-	}
-
+	thread_foreach_helper(user_cb, user_data, true, true, cpu);
 	SYS_PORT_TRACING_FUNC_EXIT(k_thread, foreach_unlocked);
-
-	k_spin_unlock(&z_thread_monitor_lock, key);
 }
 #endif /* CONFIG_SMP */
diff --git a/kernel/timeout.c b/kernel/timeout.c
index 4afe2fd5f10..f698a0779e5 100644
--- a/kernel/timeout.c
+++ b/kernel/timeout.c
@@ -16,6 +16,10 @@ static uint64_t curr_tick;
 
 static sys_dlist_t timeout_list = SYS_DLIST_STATIC_INIT(&timeout_list);
 
+/*
+ * The timeout code shall take no locks other than its own (timeout_lock), nor
+ * shall it call any other subsystem while holding this lock.
+ */
 static struct k_spinlock timeout_lock;
 
 #define MAX_WAIT (IS_ENABLED(CONFIG_SYSTEM_CLOCK_SLOPPY_IDLE) \
@@ -25,10 +29,10 @@ static struct k_spinlock timeout_lock;
 static int announce_remaining;
 
 #if defined(CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME)
-int z_clock_hw_cycles_per_sec = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
+unsigned int z_clock_hw_cycles_per_sec = CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC;
 
 #ifdef CONFIG_USERSPACE
-static inline int z_vrfy_sys_clock_hw_cycles_per_sec_runtime_get(void)
+static inline unsigned int z_vrfy_sys_clock_hw_cycles_per_sec_runtime_get(void)
 {
 	return z_impl_sys_clock_hw_cycles_per_sec_runtime_get();
 }
@@ -80,10 +84,9 @@ static int32_t elapsed(void)
 	return announce_remaining == 0 ? sys_clock_elapsed() : 0U;
 }
 
-static int32_t next_timeout(void)
+static int32_t next_timeout(int32_t ticks_elapsed)
 {
 	struct _timeout *to = first();
-	int32_t ticks_elapsed = elapsed();
 	int32_t ret;
 
 	if ((to == NULL) ||
@@ -96,11 +99,12 @@ static int32_t next_timeout(void)
 	return ret;
 }
 
-void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
-		   k_timeout_t timeout)
+k_ticks_t z_add_timeout(struct _timeout *to, _timeout_func_t fn, k_timeout_t timeout)
 {
+	k_ticks_t ticks = 0;
+
 	if (K_TIMEOUT_EQ(timeout, K_FOREVER)) {
-		return;
+		return 0;
 	}
 
 #ifdef CONFIG_KERNEL_COHERENCE
@@ -112,13 +116,19 @@ void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
 
 	K_SPINLOCK(&timeout_lock) {
 		struct _timeout *t;
+		int32_t ticks_elapsed;
+		bool has_elapsed = false;
 
 		if (Z_IS_TIMEOUT_RELATIVE(timeout)) {
-			to->dticks = timeout.ticks + 1 + elapsed();
+			ticks_elapsed = elapsed();
+			has_elapsed = true;
+			to->dticks = timeout.ticks + 1 + ticks_elapsed;
+			ticks = curr_tick + to->dticks;
 		} else {
-			k_ticks_t ticks = Z_TICK_ABS(timeout.ticks) - curr_tick;
+			k_ticks_t dticks = Z_TICK_ABS(timeout.ticks) - curr_tick;
 
-			to->dticks = MAX(1, ticks);
+			to->dticks = MAX(1, dticks);
+			ticks = timeout.ticks;
 		}
 
 		for (t = first(); t != NULL; t = next(t)) {
@@ -135,9 +145,17 @@ void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
 		}
 
 		if (to == first() && announce_remaining == 0) {
-			sys_clock_set_timeout(next_timeout(), false);
+			if (!has_elapsed) {
+				/* In case of absolute timeout that is first to expire
+				 * elapsed need to be read from the system clock.
+				 */
+				ticks_elapsed = elapsed();
+			}
+			sys_clock_set_timeout(next_timeout(ticks_elapsed), false);
 		}
 	}
+
+	return ticks;
 }
 
 int z_abort_timeout(struct _timeout *to)
@@ -149,9 +167,10 @@ int z_abort_timeout(struct _timeout *to)
 			bool is_first = (to == first());
 
 			remove_timeout(to);
+			to->dticks = TIMEOUT_DTICKS_ABORTED;
 			ret = 0;
 			if (is_first) {
-				sys_clock_set_timeout(next_timeout(), false);
+				sys_clock_set_timeout(next_timeout(elapsed()), false);
 			}
 		}
 	}
@@ -206,7 +225,7 @@ int32_t z_get_next_timeout_expiry(void)
 	int32_t ret = (int32_t) K_TICKS_FOREVER;
 
 	K_SPINLOCK(&timeout_lock) {
-		ret = next_timeout();
+		ret = next_timeout(elapsed());
 	}
 	return ret;
 }
@@ -253,7 +272,7 @@ void sys_clock_announce(int32_t ticks)
 	curr_tick += announce_remaining;
 	announce_remaining = 0;
 
-	sys_clock_set_timeout(next_timeout(), false);
+	sys_clock_set_timeout(next_timeout(0), false);
 
 	k_spin_unlock(&timeout_lock, key);
 
diff --git a/kernel/xip.c b/kernel/xip.c
index 66ce7907dde..9973b6ef595 100644
--- a/kernel/xip.c
+++ b/kernel/xip.c
@@ -31,8 +31,14 @@ void z_data_copy(void)
 	z_early_memcpy(&__ramfunc_region_start, &__ramfunc_load_start,
 		       __ramfunc_end - __ramfunc_region_start);
 #endif /* CONFIG_ARCH_HAS_RAMFUNC_SUPPORT */
+#ifdef CONFIG_ARCH_HAS_NOCACHE_MEMORY_SUPPORT
+#if CONFIG_NOCACHE_MEMORY
+	z_early_memcpy(&_nocache_ram_start, &_nocache_load_start,
+		       (uintptr_t) &_nocache_ram_size);
+#endif /* CONFIG_NOCACHE_MEMORY */
+#endif /* CONFIG_ARCH_HAS_NOCACHE_MEMORY_SUPPORT */
 #if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_ccm))
-	z_early_memcpy(&__ccm_data_start, &__ccm_data_rom_start,
+	z_early_memcpy(&__ccm_data_start, &__ccm_data_load_start,
 		       __ccm_data_end - __ccm_data_start);
 #endif
 #if DT_NODE_HAS_STATUS_OKAY(DT_CHOSEN(zephyr_itcm))
diff --git a/lib/CMakeLists.txt b/lib/CMakeLists.txt
index 52aeac58300..b945968c8fb 100644
--- a/lib/CMakeLists.txt
+++ b/lib/CMakeLists.txt
@@ -20,3 +20,4 @@ add_subdirectory(utils)
 add_subdirectory_ifdef(CONFIG_SMF smf)
 add_subdirectory_ifdef(CONFIG_OPENAMP              open-amp)
 add_subdirectory_ifdef(CONFIG_ACPI acpi)
+add_subdirectory(uuid)
diff --git a/lib/Kconfig b/lib/Kconfig
index bcf8f53235e..ae97399b199 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -30,4 +30,6 @@ source "lib/acpi/Kconfig"
 source "lib/runtime/Kconfig"
 
 source "lib/utils/Kconfig"
+
+source "lib/uuid/Kconfig"
 endmenu
diff --git a/lib/acpi/acpi.c b/lib/acpi/acpi.c
index d0ab79f72a5..cde781c478e 100644
--- a/lib/acpi/acpi.c
+++ b/lib/acpi/acpi.c
@@ -408,7 +408,7 @@ int acpi_legacy_irq_init(const char *hid, const char *uid)
 		 * If Name path exist then PCI interrupts are configurable and are not hardwired to
 		 * any specific interrupt inputs on the interrupt controller. OSPM can uses
 		 * _PRS/_CRS/_SRS to configure interrupts. But currently leave existing PCI bus
-		 * driver with arch_irq_allocate() menthod for allocate and configure interrupts
+		 * driver with arch_irq_allocate() method for allocate and configure interrupts
 		 * without conflicting.
 		 */
 		return -ENOENT;
diff --git a/lib/cpp/Kconfig b/lib/cpp/Kconfig
index 728162f5536..da309ee3fbc 100644
--- a/lib/cpp/Kconfig
+++ b/lib/cpp/Kconfig
@@ -12,6 +12,27 @@ config CPP
 
 if CPP
 
+config STD_CPP_VERSION
+	int
+	default 199711 if STD_CPP98
+	default 201103 if STD_CPP11
+	default 201402 if STD_CPP14
+	default 201703 if STD_CPP17
+	default 202002 if STD_CPP20 || STD_CPP2A || STD_CPP2B
+	help
+	  The version number of C++ standard being used (NOTE: this uses the
+	  full year and month, and is the same as the __cplusplus macro defined
+	  by the compiler). This config can be used to check for a minimum
+	  supported version. Example:
+
+	    depends on STD_CPP_VERSION >= 201703
+
+	  Adding this to your library's enablement Kconfig will force a minimum
+	  c++17 standard.
+
+	  The full year is used so c++98 can be checked using > and < operators
+	  without conflicting with c++11 or higher.
+
 choice STD_CPP
 	prompt "C++ Standard"
 	default STD_CPP11
diff --git a/lib/crc/CMakeLists.txt b/lib/crc/CMakeLists.txt
index 7285af4f3c2..6a6b35ea18a 100644
--- a/lib/crc/CMakeLists.txt
+++ b/lib/crc/CMakeLists.txt
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_sources_ifdef(CONFIG_CRC
+  crc32k_4_2_sw.c
   crc32c_sw.c
   crc32_sw.c
   crc24_sw.c
diff --git a/lib/crc/Kconfig b/lib/crc/Kconfig
index 0402df59d01..eb2ced63db2 100644
--- a/lib/crc/Kconfig
+++ b/lib/crc/Kconfig
@@ -1,4 +1,5 @@
 # Copyright (c) 2016,2023 Intel Corporation
+# Copyright (c) 2024 Intercreate, Inc.
 # SPDX-License-Identifier: Apache-2.0
 #
 config CRC
@@ -13,4 +14,10 @@ config CRC_SHELL
 	select POSIX_C_LIB_EXT
 	help
 	  Enable CRC checking for memory regions from the shell.
+
+config CRC32_K_4_2_TABLE_256
+	bool "Use 256-length table for CRC32-K/4.2"
+	help
+	  Enable the 256-length instead of 16-length table for CRC32-K/4.2.
+
 endif # CRC
diff --git a/lib/crc/crc32k_4_2_sw.c b/lib/crc/crc32k_4_2_sw.c
new file mode 100644
index 00000000000..9208d780de9
--- /dev/null
+++ b/lib/crc/crc32k_4_2_sw.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2024 Intercreate, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/sys/crc.h>
+
+uint32_t crc32_k_4_2_update(uint32_t crc, const uint8_t *const data, const size_t len)
+{
+
+#if defined(CONFIG_CRC32_K_4_2_TABLE_256)
+
+	/**
+	 * CRC table generated from polynomial 0x93a409eb CRC-32K/4.2 (*op) (Koopman)
+	 *
+	 * pycrc --width 32 --poly 0x93a409eb --reflect-in False --xor-in 0 --reflect-out False
+	 * --xor-out 0 --generate table --table-idx-width 8
+	 */
+	static const uint32_t table[256] = {
+		0x00000000, 0x93a409eb, 0xb4ec1a3d, 0x274813d6, 0xfa7c3d91, 0x69d8347a, 0x4e9027ac,
+		0xdd342e47, 0x675c72c9, 0xf4f87b22, 0xd3b068f4, 0x4014611f, 0x9d204f58, 0x0e8446b3,
+		0x29cc5565, 0xba685c8e, 0xceb8e592, 0x5d1cec79, 0x7a54ffaf, 0xe9f0f644, 0x34c4d803,
+		0xa760d1e8, 0x8028c23e, 0x138ccbd5, 0xa9e4975b, 0x3a409eb0, 0x1d088d66, 0x8eac848d,
+		0x5398aaca, 0xc03ca321, 0xe774b0f7, 0x74d0b91c, 0x0ed5c2cf, 0x9d71cb24, 0xba39d8f2,
+		0x299dd119, 0xf4a9ff5e, 0x670df6b5, 0x4045e563, 0xd3e1ec88, 0x6989b006, 0xfa2db9ed,
+		0xdd65aa3b, 0x4ec1a3d0, 0x93f58d97, 0x0051847c, 0x271997aa, 0xb4bd9e41, 0xc06d275d,
+		0x53c92eb6, 0x74813d60, 0xe725348b, 0x3a111acc, 0xa9b51327, 0x8efd00f1, 0x1d59091a,
+		0xa7315594, 0x34955c7f, 0x13dd4fa9, 0x80794642, 0x5d4d6805, 0xcee961ee, 0xe9a17238,
+		0x7a057bd3, 0x1dab859e, 0x8e0f8c75, 0xa9479fa3, 0x3ae39648, 0xe7d7b80f, 0x7473b1e4,
+		0x533ba232, 0xc09fabd9, 0x7af7f757, 0xe953febc, 0xce1bed6a, 0x5dbfe481, 0x808bcac6,
+		0x132fc32d, 0x3467d0fb, 0xa7c3d910, 0xd313600c, 0x40b769e7, 0x67ff7a31, 0xf45b73da,
+		0x296f5d9d, 0xbacb5476, 0x9d8347a0, 0x0e274e4b, 0xb44f12c5, 0x27eb1b2e, 0x00a308f8,
+		0x93070113, 0x4e332f54, 0xdd9726bf, 0xfadf3569, 0x697b3c82, 0x137e4751, 0x80da4eba,
+		0xa7925d6c, 0x34365487, 0xe9027ac0, 0x7aa6732b, 0x5dee60fd, 0xce4a6916, 0x74223598,
+		0xe7863c73, 0xc0ce2fa5, 0x536a264e, 0x8e5e0809, 0x1dfa01e2, 0x3ab21234, 0xa9161bdf,
+		0xddc6a2c3, 0x4e62ab28, 0x692ab8fe, 0xfa8eb115, 0x27ba9f52, 0xb41e96b9, 0x9356856f,
+		0x00f28c84, 0xba9ad00a, 0x293ed9e1, 0x0e76ca37, 0x9dd2c3dc, 0x40e6ed9b, 0xd342e470,
+		0xf40af7a6, 0x67aefe4d, 0x3b570b3c, 0xa8f302d7, 0x8fbb1101, 0x1c1f18ea, 0xc12b36ad,
+		0x528f3f46, 0x75c72c90, 0xe663257b, 0x5c0b79f5, 0xcfaf701e, 0xe8e763c8, 0x7b436a23,
+		0xa6774464, 0x35d34d8f, 0x129b5e59, 0x813f57b2, 0xf5efeeae, 0x664be745, 0x4103f493,
+		0xd2a7fd78, 0x0f93d33f, 0x9c37dad4, 0xbb7fc902, 0x28dbc0e9, 0x92b39c67, 0x0117958c,
+		0x265f865a, 0xb5fb8fb1, 0x68cfa1f6, 0xfb6ba81d, 0xdc23bbcb, 0x4f87b220, 0x3582c9f3,
+		0xa626c018, 0x816ed3ce, 0x12cada25, 0xcffef462, 0x5c5afd89, 0x7b12ee5f, 0xe8b6e7b4,
+		0x52debb3a, 0xc17ab2d1, 0xe632a107, 0x7596a8ec, 0xa8a286ab, 0x3b068f40, 0x1c4e9c96,
+		0x8fea957d, 0xfb3a2c61, 0x689e258a, 0x4fd6365c, 0xdc723fb7, 0x014611f0, 0x92e2181b,
+		0xb5aa0bcd, 0x260e0226, 0x9c665ea8, 0x0fc25743, 0x288a4495, 0xbb2e4d7e, 0x661a6339,
+		0xf5be6ad2, 0xd2f67904, 0x415270ef, 0x26fc8ea2, 0xb5588749, 0x9210949f, 0x01b49d74,
+		0xdc80b333, 0x4f24bad8, 0x686ca90e, 0xfbc8a0e5, 0x41a0fc6b, 0xd204f580, 0xf54ce656,
+		0x66e8efbd, 0xbbdcc1fa, 0x2878c811, 0x0f30dbc7, 0x9c94d22c, 0xe8446b30, 0x7be062db,
+		0x5ca8710d, 0xcf0c78e6, 0x123856a1, 0x819c5f4a, 0xa6d44c9c, 0x35704577, 0x8f1819f9,
+		0x1cbc1012, 0x3bf403c4, 0xa8500a2f, 0x75642468, 0xe6c02d83, 0xc1883e55, 0x522c37be,
+		0x28294c6d, 0xbb8d4586, 0x9cc55650, 0x0f615fbb, 0xd25571fc, 0x41f17817, 0x66b96bc1,
+		0xf51d622a, 0x4f753ea4, 0xdcd1374f, 0xfb992499, 0x683d2d72, 0xb5090335, 0x26ad0ade,
+		0x01e51908, 0x924110e3, 0xe691a9ff, 0x7535a014, 0x527db3c2, 0xc1d9ba29, 0x1ced946e,
+		0x8f499d85, 0xa8018e53, 0x3ba587b8, 0x81cddb36, 0x1269d2dd, 0x3521c10b, 0xa685c8e0,
+		0x7bb1e6a7, 0xe815ef4c, 0xcf5dfc9a, 0x5cf9f571};
+
+	for (size_t i = 0; i < len; i++) {
+		crc = (crc << 8) ^ table[((crc >> 24) ^ data[i]) & 0xff];
+	}
+
+#else
+
+	/**
+	 * CRC table generated from polynomial 0x93a409eb CRC-32K/4.2 (*op) (Koopman)
+	 *
+	 * pycrc --width 32 --poly 0x93a409eb --reflect-in False --xor-in 0 --reflect-out False
+	 * --xor-out 0 --generate table --table-idx-width 4
+	 */
+	static const uint32_t table[16] = {0x00000000, 0x93a409eb, 0xb4ec1a3d, 0x274813d6,
+					   0xfa7c3d91, 0x69d8347a, 0x4e9027ac, 0xdd342e47,
+					   0x675c72c9, 0xf4f87b22, 0xd3b068f4, 0x4014611f,
+					   0x9d204f58, 0x0e8446b3, 0x29cc5565, 0xba685c8e};
+
+	for (size_t i = 0; i < len; i++) {
+		crc = (crc << 4) ^ table[((crc >> 28) ^ (data[i] >> 4)) & 0x0f];
+		crc = (crc << 4) ^ table[((crc >> 28) ^ data[i]) & 0x0f];
+	}
+
+#endif
+
+	return crc;
+}
diff --git a/lib/crc/crc_shell.c b/lib/crc/crc_shell.c
index 3d08a59aa17..189ec764806 100644
--- a/lib/crc/crc_shell.c
+++ b/lib/crc/crc_shell.c
@@ -32,6 +32,7 @@ static const char *const crc_types[] = {
 	[CRC24_PGP] = "24_pgp",
 	[CRC32_C] = "32_c",
 	[CRC32_IEEE] = "32_ieee",
+	[CRC32_K_4_2] = "32_k_4_2",
 };
 
 static int string_to_crc_type(const char *s)
diff --git a/lib/heap/CMakeLists.txt b/lib/heap/CMakeLists.txt
index f3853fc5b7d..1e4a3391388 100644
--- a/lib/heap/CMakeLists.txt
+++ b/lib/heap/CMakeLists.txt
@@ -11,3 +11,4 @@ zephyr_sources_ifdef(CONFIG_SYS_HEAP_STRESS heap_stress.c)
 zephyr_sources_ifdef(CONFIG_SHARED_MULTI_HEAP shared_multi_heap.c)
 zephyr_sources_ifdef(CONFIG_MULTI_HEAP multi_heap.c)
 zephyr_sources_ifdef(CONFIG_HEAP_LISTENER heap_listener.c)
+zephyr_sources_ifdef(CONFIG_SYS_HEAP_ARRAY_SIZE heap_array.c)
diff --git a/lib/heap/Kconfig b/lib/heap/Kconfig
index 147659f96a9..9a39ab8ad73 100644
--- a/lib/heap/Kconfig
+++ b/lib/heap/Kconfig
@@ -52,6 +52,18 @@ config SYS_HEAP_RUNTIME_STATS
 	help
 	  Gather system heap runtime statistics.
 
+config SYS_HEAP_ARRAY_SIZE
+	int "Size of array to store heap pointers"
+	default 0
+	help
+	  The size of the internal array to store heap pointers. The array
+	  is filled with a heap pointer on every sys_heap_init() call.
+	  One can then iterate through the array to get all heaps statistics
+	  and to sum up the total memory allocated for all heaps.
+
+	  The default array size is zero, which disables the feature.
+	  To enable the feature, assign a value greater than zero.
+
 config SYS_HEAP_LISTENER
 	bool "sys_heap event notifications"
 	select HEAP_LISTENER
diff --git a/lib/heap/heap.c b/lib/heap/heap.c
index 7fb6884c90e..4f990f906a5 100644
--- a/lib/heap/heap.c
+++ b/lib/heap/heap.c
@@ -298,6 +298,13 @@ void *sys_heap_alloc(struct sys_heap *heap, size_t bytes)
 	return mem;
 }
 
+void *sys_heap_noalign_alloc(struct sys_heap *heap, size_t align, size_t bytes)
+{
+	ARG_UNUSED(align);
+
+	return sys_heap_alloc(heap, bytes);
+}
+
 void *sys_heap_aligned_alloc(struct sys_heap *heap, size_t align, size_t bytes)
 {
 	struct z_heap *h = heap->heap;
@@ -306,7 +313,7 @@ void *sys_heap_aligned_alloc(struct sys_heap *heap, size_t align, size_t bytes)
 	/*
 	 * Split align and rewind values (if any).
 	 * We allow for one bit of rewind in addition to the alignment
-	 * value to efficiently accommodate z_heap_aligned_alloc().
+	 * value to efficiently accommodate z_alloc_helper().
 	 * So if e.g. align = 0x28 (32 | 8) this means we align to a 32-byte
 	 * boundary and then rewind 8 bytes.
 	 */
@@ -376,37 +383,24 @@ void *sys_heap_aligned_alloc(struct sys_heap *heap, size_t align, size_t bytes)
 	return mem;
 }
 
-void *sys_heap_aligned_realloc(struct sys_heap *heap, void *ptr,
-			       size_t align, size_t bytes)
+static bool inplace_realloc(struct sys_heap *heap, void *ptr, size_t bytes)
 {
 	struct z_heap *h = heap->heap;
 
-	/* special realloc semantics */
-	if (ptr == NULL) {
-		return sys_heap_aligned_alloc(heap, align, bytes);
-	}
-	if (bytes == 0) {
-		sys_heap_free(heap, ptr);
-		return NULL;
-	}
-
-	__ASSERT((align & (align - 1)) == 0, "align must be a power of 2");
-
 	if (size_too_big(h, bytes)) {
-		return NULL;
+		return false;
 	}
 
 	chunkid_t c = mem_to_chunkid(h, ptr);
-	chunkid_t rc = right_chunk(h, c);
 	size_t align_gap = (uint8_t *)ptr - (uint8_t *)chunk_mem(h, c);
 	chunksz_t chunks_need = bytes_to_chunksz(h, bytes + align_gap);
 
-	if (align && ((uintptr_t)ptr & (align - 1))) {
-		/* ptr is not sufficiently aligned */
-	} else if (chunk_size(h, c) == chunks_need) {
+	if (chunk_size(h, c) == chunks_need) {
 		/* We're good already */
-		return ptr;
-	} else if (chunk_size(h, c) > chunks_need) {
+		return true;
+	}
+
+	if (chunk_size(h, c) > chunks_need) {
 		/* Shrink in place, split off and free unused suffix */
 #ifdef CONFIG_SYS_HEAP_LISTENER
 		size_t bytes_freed = chunksz_to_bytes(h, chunk_size(h, c));
@@ -428,9 +422,13 @@ void *sys_heap_aligned_realloc(struct sys_heap *heap, void *ptr,
 					  bytes_freed);
 #endif
 
-		return ptr;
-	} else if (!chunk_used(h, rc) &&
-		   (chunk_size(h, c) + chunk_size(h, rc) >= chunks_need)) {
+		return true;
+	}
+
+	chunkid_t rc = right_chunk(h, c);
+
+	if (!chunk_used(h, rc) &&
+	    (chunk_size(h, c) + chunk_size(h, rc) >= chunks_need)) {
 		/* Expand: split the right chunk and append */
 		chunksz_t split_size = chunks_need - chunk_size(h, c);
 
@@ -459,22 +457,66 @@ void *sys_heap_aligned_realloc(struct sys_heap *heap, void *ptr,
 					  bytes_freed);
 #endif
 
+		return true;
+	}
+
+	return false;
+}
+
+void *sys_heap_realloc(struct sys_heap *heap, void *ptr, size_t bytes)
+{
+	/* special realloc semantics */
+	if (ptr == NULL) {
+		return sys_heap_alloc(heap, bytes);
+	}
+	if (bytes == 0) {
+		sys_heap_free(heap, ptr);
+		return NULL;
+	}
+
+	if (inplace_realloc(heap, ptr, bytes)) {
+		return ptr;
+	}
+
+	/* In-place realloc was not possible: fallback to allocate and copy. */
+	void *ptr2 = sys_heap_alloc(heap, bytes);
+
+	if (ptr2 != NULL) {
+		size_t prev_size = sys_heap_usable_size(heap, ptr);
+
+		memcpy(ptr2, ptr, MIN(prev_size, bytes));
+		sys_heap_free(heap, ptr);
+	}
+	return ptr2;
+}
+
+void *sys_heap_aligned_realloc(struct sys_heap *heap, void *ptr,
+			       size_t align, size_t bytes)
+{
+	/* special realloc semantics */
+	if (ptr == NULL) {
+		return sys_heap_aligned_alloc(heap, align, bytes);
+	}
+	if (bytes == 0) {
+		sys_heap_free(heap, ptr);
+		return NULL;
+	}
+
+	__ASSERT((align & (align - 1)) == 0, "align must be a power of 2");
+
+	if ((align == 0 || ((uintptr_t)ptr & (align - 1)) == 0) &&
+	    inplace_realloc(heap, ptr, bytes)) {
 		return ptr;
-	} else {
-		;
 	}
 
 	/*
-	 * Fallback: allocate and copy
-	 *
-	 * Note for heap listener notification:
-	 * The calls to allocation and free functions generate
-	 * notification already, so there is no need to those here.
+	 * Either ptr is not sufficiently aligned for in-place realloc or
+	 * in-place realloc was not possible: fallback to allocate and copy.
 	 */
 	void *ptr2 = sys_heap_aligned_alloc(heap, align, bytes);
 
 	if (ptr2 != NULL) {
-		size_t prev_size = chunksz_to_bytes(h, chunk_size(h, c)) - align_gap;
+		size_t prev_size = sys_heap_usable_size(heap, ptr);
 
 		memcpy(ptr2, ptr, MIN(prev_size, bytes));
 		sys_heap_free(heap, ptr);
@@ -517,6 +559,10 @@ void sys_heap_init(struct sys_heap *heap, void *mem, size_t bytes)
 	h->max_allocated_bytes = 0;
 #endif
 
+#if CONFIG_SYS_HEAP_ARRAY_SIZE
+	sys_heap_array_save(heap);
+#endif
+
 	int nb_buckets = bucket_idx(h, heap_sz) + 1;
 	chunksz_t chunk0_size = chunksz(sizeof(struct z_heap) +
 				     nb_buckets * sizeof(struct z_heap_bucket));
diff --git a/lib/heap/heap.h b/lib/heap/heap.h
index 1be3bd91392..85ba12e9c81 100644
--- a/lib/heap/heap.h
+++ b/lib/heap/heap.h
@@ -10,7 +10,7 @@
  * Internal heap APIs
  */
 
-/* Theese validation checks are non-trivially expensive, so enable
+/* These validation checks are non-trivially expensive, so enable
  * only when debugging the heap code.  They shouldn't be routine
  * assertions.
  */
diff --git a/lib/heap/heap_array.c b/lib/heap/heap_array.c
new file mode 100644
index 00000000000..dc1b3a4535d
--- /dev/null
+++ b/lib/heap/heap_array.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc. www.silabs.com
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/sys/sys_heap.h>
+#include <zephyr/kernel.h>
+
+static size_t i;
+static struct sys_heap *heaps[CONFIG_SYS_HEAP_ARRAY_SIZE];
+
+int sys_heap_array_save(struct sys_heap *heap)
+{
+	if (heap == NULL) {
+		return -EINVAL;
+	}
+
+	if (i < CONFIG_SYS_HEAP_ARRAY_SIZE) {
+		heaps[i++] = heap;
+	} else {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int sys_heap_array_get(struct sys_heap ***heap)
+{
+	if (heap == NULL) {
+		return -EINVAL;
+	}
+
+	*heap = heaps;
+
+	return i;
+}
diff --git a/lib/libc/CMakeLists.txt b/lib/libc/CMakeLists.txt
index a6fecf09d66..075e066d59b 100644
--- a/lib/libc/CMakeLists.txt
+++ b/lib/libc/CMakeLists.txt
@@ -6,6 +6,7 @@ zephyr_syscall_header(
 
 add_subdirectory_ifdef(CONFIG_ARCMWDT_LIBC      arcmwdt)
 add_subdirectory_ifdef(CONFIG_ARMCLANG_STD_LIBC armstdc)
+add_subdirectory_ifdef(CONFIG_IAR_LIBC          iar)
 add_subdirectory_ifdef(CONFIG_MINIMAL_LIBC      minimal)
 add_subdirectory_ifdef(CONFIG_NEWLIB_LIBC       newlib)
 add_subdirectory_ifdef(CONFIG_PICOLIBC          picolibc)
diff --git a/lib/libc/Kconfig b/lib/libc/Kconfig
index 150ab256c6f..5d981e4719b 100644
--- a/lib/libc/Kconfig
+++ b/lib/libc/Kconfig
@@ -51,6 +51,13 @@ config PICOLIBC_SUPPORTED
 	help
 	  Selected when the target has support for picolibc.
 
+config IAR_LIBC_SUPPORTED
+	bool
+	default n
+	select FULL_LIBC_SUPPORTED
+	help
+	  Selected if the target is an IAR Systems compiler
+
 config NATIVE_LIBC_INCOMPATIBLE
 	bool
 	help
@@ -65,6 +72,7 @@ choice LIBC_IMPLEMENTATION
 	default PICOLIBC
 	default NEWLIB_LIBC if REQUIRES_FULL_LIBC
 	default MINIMAL_LIBC
+	default IAR_LIBC
 
 config MINIMAL_LIBC
 	bool "Minimal C library"
@@ -87,6 +95,7 @@ config PICOLIBC
 	select NEED_LIBC_MEM_PARTITION
 	select TC_PROVIDES_POSIX_C_LANG_SUPPORT_R
 	imply COMMON_LIBC_MALLOC
+	imply COMMON_LIBC_ABORT
 	depends on PICOLIBC_SUPPORTED
 	help
 	  Build with picolibc library. The picolibc library is built as
@@ -123,6 +132,17 @@ config EXTERNAL_LIBC
 	help
 	  Build with external/user provided C library.
 
+config IAR_LIBC
+	bool "IAR C Runtime Library"
+	depends on IAR_LIBC_SUPPORTED
+	depends on "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "iar"
+	select COMMON_LIBC_STRNLEN
+	select COMMON_LIBC_TIME if POSIX_TIMERS
+	help
+	  Use the full IAR Compiler runtime libraries.
+	  A reduced Zephyr minimal libc will be used for library functionality
+	  not provided by the IAR C Runtime Library.
+
 endchoice # LIBC_IMPLEMENTATION
 
 config HAS_NEWLIB_LIBC_NANO
diff --git a/lib/libc/common/source/stdlib/malloc.c b/lib/libc/common/source/stdlib/malloc.c
index 505bd50bad0..2821ae8173a 100644
--- a/lib/libc/common/source/stdlib/malloc.c
+++ b/lib/libc/common/source/stdlib/malloc.c
@@ -115,8 +115,8 @@ static POOL_SECTION unsigned char __aligned(HEAP_ALIGN) malloc_arena[HEAP_SIZE];
 
 #   define HEAP_BASE	ROUND_UP(USED_RAM_END_ADDR, HEAP_ALIGN)
 
-#   if defined(CONFIG_XTENSA) && (defined(CONFIG_SOC_FAMILY_INTEL_ADSP) \
-	|| defined(CONFIG_HAS_ESPRESSIF_HAL))
+#   if (defined(CONFIG_XTENSA) && defined(CONFIG_SOC_FAMILY_INTEL_ADSP)) \
+	|| defined(CONFIG_HAS_ESPRESSIF_HAL)
 extern char _heap_sentry[];
 #    define HEAP_SIZE  ROUND_DOWN((POINTER_TO_UINT(_heap_sentry) - HEAP_BASE), HEAP_ALIGN)
 #   else
diff --git a/lib/libc/iar/CMakeLists.txt b/lib/libc/iar/CMakeLists.txt
new file mode 100644
index 00000000000..f57ab75d2d3
--- /dev/null
+++ b/lib/libc/iar/CMakeLists.txt
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(src/libc-hooks.c)
+zephyr_system_include_directories(include)
diff --git a/lib/libc/iar/include/errno.h b/lib/libc/iar/include/errno.h
new file mode 100644
index 00000000000..6310531a75c
--- /dev/null
+++ b/lib/libc/iar/include/errno.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2025 IAR Systems AB
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Defines additional error numbers based on POSIX
+ */
+
+#ifndef ZEPHYR_LIB_LIBC_IAR_INCLUDE_ERRNO_H_
+#define ZEPHYR_LIB_LIBC_IAR_INCLUDE_ERRNO_H_
+
+#include_next <errno.h>
+
+#ifndef __cplusplus
+#define EPERM            1  /**< Not owner */
+#define ENOENT           2  /**< No such file or directory */
+#define ESRCH            3  /**< No such context */
+#define EINTR            4  /**< Interrupted system call */
+#define EIO              5  /**< I/O error */
+#define ENXIO            6  /**< No such device or address */
+#define E2BIG            7  /**< Arg list too long */
+#define ENOEXEC          8  /**< Exec format error */
+#define EBADF            9  /**< Bad file number */
+#define ECHILD          10  /**< No children */
+#define EAGAIN          11  /**< No more contexts */
+#define ENOMEM          12  /**< Not enough core */
+#define EACCES          13  /**< Permission denied */
+#define EFAULT          14  /**< Bad address */
+#define ENOTBLK         15  /**< Block device required */
+#define EBUSY           16  /**< Mount device busy */
+#define EEXIST          17  /**< File exists */
+#define EXDEV           18  /**< Cross-device link */
+#define ENODEV          19  /**< No such device */
+#define ENOTDIR         20  /**< Not a directory */
+#define EISDIR          21  /**< Is a directory */
+#define EINVAL          22  /**< Invalid argument */
+#define ENFILE          23  /**< File table overflow */
+#define EMFILE          24  /**< Too many open files */
+#define ENOTTY          25  /**< Not a typewriter */
+#define ETXTBSY         26  /**< Text file busy */
+#define EFBIG           27  /**< File too large */
+#define ENOSPC          28  /**< No space left on device */
+#define ESPIPE          29  /**< Illegal seek */
+#define EROFS           30  /**< Read-only file system */
+#define EMLINK          31  /**< Too many links */
+#define EPIPE           32  /**< Broken pipe */
+#define ENOMSG          35  /**< Unexpected message type */
+#define EDEADLK         45  /**< Resource deadlock avoided */
+#define ENOLCK          46  /**< No locks available */
+#define ENOSTR          60  /**< STREAMS device required */
+#define ENODATA         61  /**< Missing expected message data */
+#define ETIME           62  /**< STREAMS timeout occurred */
+#define ENOSR           63  /**< Insufficient memory */
+#define EPROTO          71  /**< Generic STREAMS error */
+#define EBADMSG         77  /**< Invalid STREAMS message */
+#define ENOSYS          88  /**< Function not implemented */
+#define ENOTEMPTY       90  /**< Directory not empty */
+#define ENAMETOOLONG    91  /**< File name too long */
+#define ELOOP           92  /**< Too many levels of symbolic links */
+#define EOPNOTSUPP      95  /**< Operation not supported on socket */
+#define EPFNOSUPPORT    96  /**< Protocol family not supported */
+#define ECONNRESET      104 /**< Connection reset by peer */
+#define ENOBUFS         105 /**< No buffer space available */
+#define EAFNOSUPPORT    106 /**< Addr family not supported */
+#define EPROTOTYPE      107 /**< Protocol wrong type for socket */
+#define ENOTSOCK        108 /**< Socket operation on non-socket */
+#define ENOPROTOOPT     109 /**< Protocol not available */
+#define ESHUTDOWN       110 /**< Can't send after socket shutdown */
+#define ECONNREFUSED    111 /**< Connection refused */
+#define EADDRINUSE      112 /**< Address already in use */
+#define ECONNABORTED    113 /**< Software caused connection abort */
+#define ENETUNREACH     114 /**< Network is unreachable */
+#define ENETDOWN        115 /**< Network is down */
+#define ETIMEDOUT       116 /**< Connection timed out */
+#define EHOSTDOWN       117 /**< Host is down */
+#define EHOSTUNREACH    118 /**< No route to host */
+#define EINPROGRESS     119 /**< Operation now in progress */
+#define EALREADY        120 /**< Operation already in progress */
+#define EDESTADDRREQ    121 /**< Destination address required */
+#define EMSGSIZE        122 /**< Message size */
+#define EPROTONOSUPPORT 123 /**< Protocol not supported */
+#define ESOCKTNOSUPPORT 124 /**< Socket type not supported */
+#define EADDRNOTAVAIL   125 /**< Can't assign requested address */
+#define ENETRESET       126 /**< Network dropped connection on reset */
+#define EISCONN         127 /**< Socket is already connected */
+#define ENOTCONN        128 /**< Socket is not connected */
+#define ETOOMANYREFS    129 /**< Too many references: can't splice */
+#define ENOTSUP         134 /**< Unsupported value */
+#define EOVERFLOW       139 /**< Value overflow */
+#define ECANCELED       140 /**< Operation canceled */
+#define EWOULDBLOCK  EAGAIN /**< Operation would block */
+#endif /* __cplusplus */
+#endif /* ZEPHYR_LIB_LIBC_IAR_INCLUDE_ERRNO_H_ */
diff --git a/lib/libc/iar/include/limits.h b/lib/libc/iar/include/limits.h
new file mode 100644
index 00000000000..50decad13ad
--- /dev/null
+++ b/lib/libc/iar/include/limits.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025 IAR Systems AB
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_LIB_LIBC_IAR_INCLUDE_LIMITS_H_
+#define ZEPHYR_LIB_LIBC_IAR_INCLUDE_LIMITS_H_
+
+#include_next <limits.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define PATH_MAX 256
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_LIB_LIBC_IAR_INCLUDE_LIMITS_H_ */
diff --git a/lib/libc/iar/include/sys/_timespec.h b/lib/libc/iar/include/sys/_timespec.h
new file mode 100644
index 00000000000..1ea3b4da5bf
--- /dev/null
+++ b/lib/libc/iar/include/sys/_timespec.h
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 IAR Systems AB
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* file is intentionally empty */
diff --git a/lib/libc/iar/include/sys/_timeval.h b/lib/libc/iar/include/sys/_timeval.h
new file mode 100644
index 00000000000..43f8f7f8c89
--- /dev/null
+++ b/lib/libc/iar/include/sys/_timeval.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2025 IAR Systems AB
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_LIB_LIBC_IAR_INCLUDE_SYS__TIMEVAL_H_
+#define ZEPHYR_LIB_LIBC_IAR_INCLUDE_SYS__TIMEVAL_H_
+
+#include <stdint.h>
+
+#if !defined(__time_t_defined)
+#define __time_t_defined
+typedef long long time_t;
+#endif
+
+#if !defined(__suseconds_t_defined)
+#define __suseconds_t_defined
+typedef int32_t suseconds_t;
+#endif
+
+struct timeval {
+	time_t tv_sec;
+	suseconds_t tv_usec;
+};
+
+#endif /* ZEPHYR_LIB_LIBC_IAR_INCLUDE_SYS__TIMEVAL_H_ */
diff --git a/lib/libc/iar/include/sys/cdefs.h b/lib/libc/iar/include/sys/cdefs.h
new file mode 100644
index 00000000000..1ea3b4da5bf
--- /dev/null
+++ b/lib/libc/iar/include/sys/cdefs.h
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 IAR Systems AB
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* file is intentionally empty */
diff --git a/lib/libc/iar/include/sys/timespec.h b/lib/libc/iar/include/sys/timespec.h
new file mode 100644
index 00000000000..d5c0549dbc9
--- /dev/null
+++ b/lib/libc/iar/include/sys/timespec.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025 IAR Systems AB
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_LIB_LIBC_IAR_INCLUDE_SYS_TIMESPEC_H_
+#define ZEPHYR_LIB_LIBC_IAR_INCLUDE_SYS_TIMESPEC_H_
+
+#include <sys/types.h>
+#include <sys/_timespec.h>
+
+struct itimerspec {
+	struct timespec it_interval;  /* Timer interval */
+	struct timespec it_value;     /* Timer expiration */
+};
+
+#endif /* ZEPHYR_LIB_LIBC_IAR_INCLUDE_SYS_TIMESPEC_H_ */
diff --git a/lib/libc/iar/include/sys/types.h b/lib/libc/iar/include/sys/types.h
new file mode 100644
index 00000000000..9654efc25ee
--- /dev/null
+++ b/lib/libc/iar/include/sys/types.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025 IAR Systems AB
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_LIB_LIBC_IAR_INCLUDE_SYS_TYPES_H_
+#define ZEPHYR_LIB_LIBC_IAR_INCLUDE_SYS_TYPES_H_
+
+typedef unsigned int mode_t;
+typedef signed long ssize_t;
+typedef int off_t;
+typedef __INT64_TYPE__ time_t;
+
+#if !defined(_CLOCK_T_DECLARED) && !defined(__clock_t_defined)
+typedef unsigned int clock_t;
+#define _CLOCK_T_DECLARED
+#define __clock_t_defined
+#endif
+
+#endif /* ZEPHYR_LIB_LIBC_IAR_INCLUDE_SYS_TYPES_H_ */
diff --git a/lib/libc/iar/include/time.h b/lib/libc/iar/include/time.h
new file mode 100644
index 00000000000..b0959878574
--- /dev/null
+++ b/lib/libc/iar/include/time.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 IAR Systems AB
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Declares additional time related functions based on POSIX
+ */
+
+#ifndef ZEPHYR_LIB_LIBC_IAR_INCLUDE_TIME_H_
+#define ZEPHYR_LIB_LIBC_IAR_INCLUDE_TIME_H_
+
+#include <zephyr/toolchain.h>
+#include_next <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+char      *asctime_r(const struct tm *ZRESTRICT tp, char *ZRESTRICT buf);
+char      *ctime_r(const time_t *clock, char *buf);
+struct tm *gmtime_r(const time_t *ZRESTRICT timep, struct tm *ZRESTRICT result);
+struct tm *localtime_r(const time_t *ZRESTRICT timer, struct tm *ZRESTRICT result);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_LIB_LIBC_IAR_INCLUDE_TIME_H_ */
diff --git a/lib/libc/iar/src/libc-hooks.c b/lib/libc/iar/src/libc-hooks.c
new file mode 100644
index 00000000000..d3deea9658a
--- /dev/null
+++ b/lib/libc/iar/src/libc-hooks.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2025 IAR Systems AB
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <stdio.h>
+
+static int _stdout_hook_default(int c)
+{
+	(void)(c); /* Prevent warning about unused argument */
+
+	return EOF;
+}
+
+static int (*_stdout_hook)(int) = _stdout_hook_default;
+
+void __stdout_hook_install(int (*hook)(int))
+{
+	_stdout_hook = hook;
+}
+
+int fputc(int c, FILE *f)
+{
+	return (_stdout_hook)(c);
+}
+
+#pragma weak __write
+size_t __write(int handle, const unsigned char *buf, size_t bufSize)
+{
+	size_t nChars = 0;
+	/* Check for the command to flush all handles */
+	if (handle == -1) {
+		return 0;
+	}
+	/* Check for stdout and stderr
+	 * (only necessary if FILE descriptors are enabled.)
+	 */
+	if (handle != 1 && handle != 2) {
+		return -1;
+	}
+	for (/* Empty */; bufSize > 0; --bufSize) {
+		int ret = (_stdout_hook)(*buf);
+
+		if (ret == EOF) {
+			break;
+		}
+		++buf;
+		++nChars;
+	}
+	return nChars;
+}
diff --git a/lib/libc/minimal/include/sys/cdefs.h b/lib/libc/minimal/include/sys/cdefs.h
index e69de29bb2d..036185a88ad 100644
--- a/lib/libc/minimal/include/sys/cdefs.h
+++ b/lib/libc/minimal/include/sys/cdefs.h
@@ -0,0 +1,4 @@
+/**
+ * This file is intentionally empty.
+ * It allows code including it to compile with the minimal libc.
+ */
diff --git a/lib/libc/picolibc/CMakeLists.txt b/lib/libc/picolibc/CMakeLists.txt
index fe9dd6d50f4..752379dd76d 100644
--- a/lib/libc/picolibc/CMakeLists.txt
+++ b/lib/libc/picolibc/CMakeLists.txt
@@ -11,7 +11,7 @@ zephyr_library_sources(
   stdio.c
   )
 
-zephyr_library_compile_options(-fno-lto)
+zephyr_library_compile_options($<TARGET_PROPERTY:compiler,prohibit_lto>)
 
 # define __LINUX_ERRNO_EXTENSIONS__ so we get errno defines like -ESHUTDOWN
 # used by the network stack
diff --git a/lib/libc/picolibc/assert.c b/lib/libc/picolibc/assert.c
index 806d996a230..7eede1e49d9 100644
--- a/lib/libc/picolibc/assert.c
+++ b/lib/libc/picolibc/assert.c
@@ -11,18 +11,22 @@
 FUNC_NORETURN void __assert_func(const char *file, int line,
 				 const char *function, const char *expression)
 {
+#if __ASSERT_ON
 	__ASSERT(0, "assertion \"%s\" failed: file \"%s\", line %d%s%s\n",
 		 expression, file, line,
 		 function ? ", function: " : "", function ? function : "");
-	CODE_UNREACHABLE;
+#endif
+	abort();
 }
 
 #else
 
 FUNC_NORETURN void __assert_no_args(void)
 {
+#if __ASSERT_ON
 	__ASSERT_NO_MSG(0);
-	CODE_UNREACHABLE;
+#endif
+	abort();
 }
 
 #endif
diff --git a/lib/net_buf/buf.c b/lib/net_buf/buf.c
index c8f42e6f510..fc861012ebc 100644
--- a/lib/net_buf/buf.c
+++ b/lib/net_buf/buf.c
@@ -338,6 +338,8 @@ struct net_buf *net_buf_alloc_len(struct net_buf_pool *pool, size_t size,
 #if defined(CONFIG_NET_BUF_POOL_USAGE)
 	atomic_dec(&pool->avail_count);
 	__ASSERT_NO_MSG(atomic_get(&pool->avail_count) >= 0);
+	pool->max_used = MAX(pool->max_used,
+			     pool->buf_count - atomic_get(&pool->avail_count));
 #endif
 	return buf;
 }
@@ -386,27 +388,6 @@ struct net_buf *net_buf_alloc_with_data(struct net_buf_pool *pool,
 	return buf;
 }
 
-#if defined(CONFIG_NET_BUF_LOG)
-struct net_buf *net_buf_get_debug(struct k_fifo *fifo, k_timeout_t timeout,
-				  const char *func, int line)
-#else
-struct net_buf *net_buf_get(struct k_fifo *fifo, k_timeout_t timeout)
-#endif
-{
-	struct net_buf *buf;
-
-	NET_BUF_DBG("%s():%d: fifo %p", func, line, fifo);
-
-	buf = k_fifo_get(fifo, timeout);
-	if (!buf) {
-		return NULL;
-	}
-
-	NET_BUF_DBG("%s():%d: buf %p fifo %p", func, line, buf, fifo);
-
-	return buf;
-}
-
 static struct k_spinlock net_buf_slist_lock;
 
 void net_buf_slist_put(sys_slist_t *list, struct net_buf *buf)
@@ -437,14 +418,6 @@ struct net_buf *net_buf_slist_get(sys_slist_t *list)
 	return buf;
 }
 
-void net_buf_put(struct k_fifo *fifo, struct net_buf *buf)
-{
-	__ASSERT_NO_MSG(fifo);
-	__ASSERT_NO_MSG(buf);
-
-	k_fifo_put(fifo, buf);
-}
-
 #if defined(CONFIG_NET_BUF_LOG)
 void net_buf_unref_debug(struct net_buf *buf, const char *func, int line)
 #else
diff --git a/lib/open-amp/Kconfig b/lib/open-amp/Kconfig
index 1ad554cd90b..b27c8c21644 100644
--- a/lib/open-amp/Kconfig
+++ b/lib/open-amp/Kconfig
@@ -34,3 +34,15 @@ config OPENAMP_RSC_TABLE_IPM_TX_ID
 	help
 	   This option specifies the IPM TX channel ID used in a VRING
 	   for interprocessor communication
+
+config OPENAMP_COPY_RSC_TABLE
+	bool "Copy resource table section"
+	help
+	  The .resource_table section must be placed in a specific location
+	  known by both this core and the remote core. If this is not taken
+	  care of by the remote then this firmware has the ability to copy
+	  the table to a specific location. This memory region can be declared
+	  in the device tree by the "zephyr,ipc_rsc_table" node.
+
+	  This is not needed if the remote loads this firmware and has control
+	  over the placement of the .resource_table section such as remoteproc.
diff --git a/lib/open-amp/resource_table.c b/lib/open-amp/resource_table.c
index 1bc8d5cb6eb..49e836d9afc 100644
--- a/lib/open-amp/resource_table.c
+++ b/lib/open-amp/resource_table.c
@@ -29,6 +29,12 @@
 #include <zephyr/kernel.h>
 #include <resource_table.h>
 
+#ifdef CONFIG_OPENAMP_COPY_RSC_TABLE
+#define RSC_TABLE_ADDR	DT_REG_ADDR(DT_CHOSEN(zephyr_ipc_rsc_table))
+#define RSC_TABLE_SIZE	DT_REG_SIZE(DT_CHOSEN(zephyr_ipc_rsc_table))
+BUILD_ASSERT(sizeof(struct fw_resource_table) <= RSC_TABLE_SIZE);
+#endif
+
 extern char ram_console_buf[];
 
 #define __resource Z_GENERIC_SECTION(.resource_table)
@@ -76,6 +82,11 @@ static struct fw_resource_table __resource resource_table = {
 
 void rsc_table_get(struct fw_resource_table **table_ptr, int *length)
 {
-	*table_ptr = &resource_table;
 	*length = sizeof(resource_table);
+#ifdef CONFIG_OPENAMP_COPY_RSC_TABLE
+	*table_ptr = (struct fw_resource_table *)RSC_TABLE_ADDR;
+	memcpy(*table_ptr, &resource_table, *length);
+#else
+	*table_ptr = &resource_table;
+#endif
 }
diff --git a/lib/os/Kconfig b/lib/os/Kconfig
index 9ce3be2a66e..004df87ccf3 100644
--- a/lib/os/Kconfig
+++ b/lib/os/Kconfig
@@ -106,6 +106,16 @@ config MPSC_CLEAR_ALLOCATED
 	  When enabled packet space is zeroed before returning from allocation.
 endif
 
+if SCHED_DEADLINE
+
+config P4WQ_INIT_STAGE_EARLY
+	bool "Early initialization of P4WQ threads"
+	help
+	  Initialize P4WQ threads early so that the P4WQ can be used on devices
+	  initialization sequence.
+
+endif
+
 config REBOOT
 	bool "Reboot functionality"
 	help
diff --git a/lib/os/fdtable.c b/lib/os/fdtable.c
index 0299e89812a..be53627efca 100644
--- a/lib/os/fdtable.c
+++ b/lib/os/fdtable.c
@@ -550,9 +550,7 @@ static ssize_t stdinout_read_vmeth(void *obj, void *buffer, size_t count)
 
 static ssize_t stdinout_write_vmeth(void *obj, const void *buffer, size_t count)
 {
-#if defined(CONFIG_BOARD_NATIVE_POSIX)
-	return zvfs_write(1, buffer, count, NULL);
-#elif defined(CONFIG_NEWLIB_LIBC) || defined(CONFIG_ARCMWDT_LIBC)
+#if defined(CONFIG_NEWLIB_LIBC) || defined(CONFIG_ARCMWDT_LIBC)
 	return z_impl_zephyr_write_stdout(buffer, count);
 #else
 	return 0;
diff --git a/lib/os/mpsc_pbuf.c b/lib/os/mpsc_pbuf.c
index 845c2456cfb..56c8def5bc4 100644
--- a/lib/os/mpsc_pbuf.c
+++ b/lib/os/mpsc_pbuf.c
@@ -201,10 +201,12 @@ static bool drop_item_locked(struct mpsc_pbuf_buffer *buffer,
 
 	uint32_t rd_wlen = buffer->get_wlen(item);
 
-	/* If packet is busy need to be ommited. */
+	/* If packet is busy need to be omitted. */
 	if (!is_valid(item)) {
 		return false;
 	} else if (item->hdr.busy) {
+		bool ret = true;
+
 		MPSC_PBUF_DBG(buffer, "no space: Found busy packet %p (len:%d)", item, rd_wlen);
 		/* Add skip packet before claimed packet. */
 		if (free_wlen) {
@@ -215,15 +217,18 @@ static bool drop_item_locked(struct mpsc_pbuf_buffer *buffer,
 		buffer->wr_idx = idx_inc(buffer, buffer->wr_idx, rd_wlen);
 
 		/* If allocation wrapped around the buffer and found busy packet
-		 * that was already ommited, skip it again.
+		 * that was already omitted, skip it again and indicate that no
+		 * packet was dropped.
 		 */
 		if (buffer->rd_idx == buffer->tmp_rd_idx) {
 			buffer->tmp_rd_idx = idx_inc(buffer, buffer->tmp_rd_idx, rd_wlen);
+			ret = false;
 		}
 
 		buffer->tmp_wr_idx = buffer->tmp_rd_idx;
 		buffer->rd_idx = buffer->tmp_rd_idx;
 		buffer->flags |= MPSC_PBUF_FULL;
+		return ret;
 	} else {
 		/* Prepare packet dropping. */
 		rd_idx_inc(buffer, rd_wlen);
@@ -622,18 +627,28 @@ bool mpsc_pbuf_is_pending(struct mpsc_pbuf_buffer *buffer)
 void mpsc_pbuf_get_utilization(struct mpsc_pbuf_buffer *buffer,
 			       uint32_t *size, uint32_t *now)
 {
+	k_spinlock_key_t key = k_spin_lock(&buffer->lock);
+
 	/* One byte is left for full/empty distinction. */
 	*size = (buffer->size - 1) * sizeof(int);
 	*now = get_usage(buffer) * sizeof(int);
+
+	k_spin_unlock(&buffer->lock, key);
 }
 
 int mpsc_pbuf_get_max_utilization(struct mpsc_pbuf_buffer *buffer, uint32_t *max)
 {
+	int rc;
+	k_spinlock_key_t key = k_spin_lock(&buffer->lock);
 
-	if (!(buffer->flags & MPSC_PBUF_MAX_UTILIZATION)) {
-		return -ENOTSUP;
+	if (buffer->flags & MPSC_PBUF_MAX_UTILIZATION) {
+		*max = buffer->max_usage * sizeof(int);
+		rc = 0;
+	} else {
+		rc = -ENOTSUP;
 	}
 
-	*max = buffer->max_usage * sizeof(int);
-	return 0;
+	k_spin_unlock(&buffer->lock, key);
+
+	return rc;
 }
diff --git a/lib/os/p4wq.c b/lib/os/p4wq.c
index 39b59de20d9..6d519230c37 100644
--- a/lib/os/p4wq.c
+++ b/lib/os/p4wq.c
@@ -104,7 +104,14 @@ static FUNC_NORETURN void p4wq_loop(void *p0, void *p1, void *p2)
 			if (!thread_was_requeued(_current)) {
 				sys_dlist_remove(&w->dlnode);
 				w->thread = NULL;
-				k_sem_give(&w->done_sem);
+
+				if (queue->done_handler) {
+					k_spin_unlock(&queue->lock, k);
+					queue->done_handler(w);
+					k = k_spin_lock(&queue->lock);
+				} else {
+					k_sem_give(&w->done_sem);
+				}
 			}
 		} else {
 			z_pend_curr(&queue->lock, k, &queue->waitq, K_FOREVER);
@@ -152,6 +159,7 @@ static int static_init(void)
 
 			if (!i || (pp->flags & K_P4WQ_QUEUE_PER_THREAD)) {
 				k_p4wq_init(q);
+				q->done_handler = pp->done_handler;
 			}
 
 			q->flags = pp->flags;
@@ -210,7 +218,11 @@ void k_p4wq_enable_static_thread(struct k_p4wq *queue, struct k_thread *thread,
  * so they can initialize in parallel instead of serially on the main
  * CPU.
  */
+#if defined(CONFIG_P4WQ_INIT_STAGE_EARLY)
+SYS_INIT(static_init, POST_KERNEL, 1);
+#else
 SYS_INIT(static_init, APPLICATION, 99);
+#endif
 
 void k_p4wq_submit(struct k_p4wq *queue, struct k_p4wq_work *item)
 {
@@ -296,7 +308,14 @@ bool k_p4wq_cancel(struct k_p4wq *queue, struct k_p4wq_work *item)
 
 	if (ret) {
 		rb_remove(&queue->queue, &item->rbnode);
-		k_sem_give(&item->done_sem);
+
+		if (queue->done_handler) {
+			k_spin_unlock(&queue->lock, k);
+			queue->done_handler(item);
+			k = k_spin_lock(&queue->lock);
+		} else {
+			k_sem_give(&item->done_sem);
+		}
 	}
 
 	k_spin_unlock(&queue->lock, k);
diff --git a/lib/posix/options/CMakeLists.txt b/lib/posix/options/CMakeLists.txt
index b6e9d0bad4e..58f44773e31 100644
--- a/lib/posix/options/CMakeLists.txt
+++ b/lib/posix/options/CMakeLists.txt
@@ -75,10 +75,6 @@ if (NOT CONFIG_TC_PROVIDES_POSIX_FILE_SYSTEM_R)
   zephyr_library_sources_ifdef(CONFIG_POSIX_FILE_SYSTEM_R file_system_r.c)
 endif()
 
-zephyr_library_sources_ifdef(CONFIG_POSIX_FSYNC fsync.c)
-zephyr_library_sources_ifdef(CONFIG_POSIX_MEMLOCK mlockall.c)
-zephyr_library_sources_ifdef(CONFIG_POSIX_MEMLOCK_RANGE mlock.c)
-
 if (NOT CONFIG_TC_PROVIDES_POSIX_MEMORY_PROTECTION)
 zephyr_library_sources_ifdef(CONFIG_POSIX_MEMORY_PROTECTION mprotect.c)
 endif()
@@ -87,8 +83,6 @@ if (NOT CONFIG_TC_PROVIDES_POSIX_MAPPED_FILES)
   zephyr_library_sources_ifdef(CONFIG_POSIX_MAPPED_FILES mmap.c)
 endif()
 
-zephyr_library_sources_ifdef(CONFIG_POSIX_MESSAGE_PASSING mqueue.c)
-
 if (NOT CONFIG_TC_PROVIDES_POSIX_MULTI_PROCESS)
   zephyr_library_sources_ifdef(CONFIG_POSIX_MULTI_PROCESS
     sleep.c
@@ -100,10 +94,6 @@ if (NOT CONFIG_TC_PROVIDES_POSIX_NETWORKING)
   zephyr_library_sources_ifdef(CONFIG_POSIX_NETWORKING net.c)
 endif()
 
-if (NOT CONFIG_TC_PROVIDES_POSIX_SHARED_MEMORY_OBJECTS)
-  zephyr_library_sources_ifdef(CONFIG_POSIX_SHARED_MEMORY_OBJECTS shm.c)
-endif()
-
 if (NOT CONFIG_TC_PROVIDES_POSIX_SIGNALS)
   zephyr_library_sources_ifdef(CONFIG_POSIX_SIGNALS signal.c ${STRSIGNAL_TABLE_H})
 endif()
@@ -129,8 +119,6 @@ if (NOT CONFIG_TC_PROVIDES_POSIX_TIMERS)
   )
 endif()
 
-zephyr_library_sources_ifdef(CONFIG_POSIX_PRIORITY_SCHEDULING sched.c)
-
 if (NOT CONFIG_TC_PROVIDES_POSIX_READER_WRITER_LOCKS)
   # Note: the Option is _POSIX_READER_WRITER_LOCKS, while the Option Group is POSIX_RW_LOCKS.
   # We have opted to use POSIX_READER_WRITER_LOCKS here to match the Option name.
@@ -154,6 +142,15 @@ if (NOT CONFIG_TC_PROVIDES_POSIX_THREADS)
   )
 endif()
 
+if(NOT CONFIG_TC_PROVIDES_XSI_REALTIME)
+  zephyr_library_sources_ifdef(CONFIG_POSIX_FSYNC fsync.c)
+  zephyr_library_sources_ifdef(CONFIG_POSIX_MEMLOCK mlockall.c)
+  zephyr_library_sources_ifdef(CONFIG_POSIX_MEMLOCK_RANGE mlock.c)
+  zephyr_library_sources_ifdef(CONFIG_POSIX_MESSAGE_PASSING mqueue.c)
+  zephyr_library_sources_ifdef(CONFIG_POSIX_PRIORITY_SCHEDULING sched.c)
+  zephyr_library_sources_ifdef(CONFIG_POSIX_SHARED_MEMORY_OBJECTS shm.c)
+endif()
+
 zephyr_library_sources_ifdef(CONFIG_XOPEN_STREAMS stropts.c)
 
 if (NOT CONFIG_TC_PROVIDES_XSI_SYSTEM_LOGGING)
diff --git a/lib/posix/options/Kconfig b/lib/posix/options/Kconfig
index c7e60d9e323..6c2b129170e 100644
--- a/lib/posix/options/Kconfig
+++ b/lib/posix/options/Kconfig
@@ -29,11 +29,18 @@ rsource "Kconfig.signal"
 rsource "Kconfig.spinlock"
 rsource "Kconfig.sync_io"
 rsource "Kconfig.timer"
-rsource "Kconfig.xsi"
 
-rsource "Kconfig.compat"
+menu "X/Open system interfaces"
+
+rsource "Kconfig.xsi_realtime"
+rsource "Kconfig.xsi_single_process"
+rsource "Kconfig.xsi_streams"
+rsource "Kconfig.xsi_system_logging"
+rsource "Kconfig.xsi_threads_ext"
 
-rsource "Kconfig.deprecated"
+endmenu # "X/Open system interfaces"
+
+rsource "Kconfig.compat"
 
 rsource "Kconfig.toolchain"
 
diff --git a/lib/posix/options/Kconfig.deprecated b/lib/posix/options/Kconfig.deprecated
deleted file mode 100644
index 95e1d04431e..00000000000
--- a/lib/posix/options/Kconfig.deprecated
+++ /dev/null
@@ -1,277 +0,0 @@
-# Copyright (c) 2024 Tenstorrent AI ULC
-#
-# SPDX-License-Identifier: Apache-2.0
-
-# This file should be removed after Zephyr 4.0 is released
-
-menu "Deprecated POSIX options"
-
-config EVENTFD_MAX
-	int "Maximum number of eventfd's [DEPRECATED]"
-	default ZVFS_EVENTFD_MAX if ZVFS_EVENTFD
-	default 0
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_ZVFS_EVENTFD_MAX instead.
-
-config FNMATCH
-	bool "Support for fnmatch [DEPRECATED]"
-	select DEPRECATED
-	select POSIX_C_LIB_EXT
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_C_LIB_EXT instead.
-
-config GETOPT
-	bool "Getopt library support [DEPRECATED]"
-	select DEPRECATED
-	select POSIX_C_LIB_EXT
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_C_LIB_EXT instead.
-
-config MAX_PTHREAD_COUNT
-	int "Maximum number of pthread_t [DEPRECATED]"
-	default POSIX_THREAD_THREADS_MAX if POSIX_THREADS
-	default 0
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_THREAD_THREADS_MAX instead.
-
-config MAX_PTHREAD_KEY_COUNT
-	int "Maximum number of pthread_key_t [DEPRECATED]"
-	default POSIX_THREAD_KEYS_MAX if POSIX_THREADS
-	default 0
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_THREAD_KEYS_MAX instead.
-
-config MAX_TIMER_COUNT
-	int "Maximum number of timer_t [DEPRECATED]"
-	default POSIX_TIMER_MAX if POSIX_TIMERS
-	default 0
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_TIMER_MAX instead.
-
-config MSG_COUNT_MAX
-	int "Maximum number of messages in a POSIX message queue [DEPRECATED]"
-	default POSIX_MQ_OPEN_MAX if POSIX_MESSAGE_PASSING
-	default 0
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_MQ_OPEN_MAX instead.
-
-config POSIX_CLOCK
-	bool "clock and sleep APIs [DEPRECATED]"
-	select DEPRECATED
-	select POSIX_CLOCK_SELECTION
-	select POSIX_CPUTIME
-	select POSIX_MONOTONIC_CLOCK
-	select POSIX_TIMERS
-	select POSIX_TIMEOUTS
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_TIMERS instead.
-
-config POSIX_FS
-	bool "Support for environ, getenv(), getenv_r(), setenv(), and unsetenv() [DEPRECATED]"
-	select DEPRECATED
-	select POSIX_FILE_SYSTEM
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_FILE_SYSTEM instead.
-
-config POSIX_LIMITS_RTSIG_MAX
-	int "_POSIX_RTSIG_MAX value in limits.h [DEPRECATED]"
-	default POSIX_RTSIG_MAX if POSIX_REALTIME_SIGNALS
-	default 0
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_RTSIG_MAX instead.
-
-config POSIX_MAX_FDS
-	int "Maximum number of open file descriptors [DEPRECATED]"
-	default POSIX_OPEN_MAX
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_OPEN_MAX instead.
-
-	  See also CONFIG_ZVFS_OPEN_MAX.
-
-config POSIX_MAX_OPEN_FILES
-	int "Maximum number of open file descriptors [DEPRECATED]"
-	default POSIX_OPEN_MAX
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_OPEN_MAX instead.
-
-	  See also CONFIG_ZVFS_OPEN_MAX.
-
-config POSIX_MQUEUE
-	bool "Message queue support [DEPRECATED]"
-	select DEPRECATED
-	select POSIX_MESSAGE_PASSING
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_MESSAGE_PASSING instead.
-
-config POSIX_PUTMSG
-	bool "Support for putmsg function [DEPRECATED]"
-	select DEPRECATED
-	select XOPEN_STREAMS
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_XOPEN_STREAMS instead.
-
-config POSIX_SIGNAL
-	bool "Support for POSIX signal APIs [DEPRECATED]"
-	select DEPRECATED
-	select POSIX_SIGNALS
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_SIGNALS instead.
-
-config POSIX_SYSCONF
-	bool "Support for sysconf() [DEPRECATED]"
-	select DEPRECATED
-	select POSIX_SINGLE_PROCESS
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_SINGLE_PROCESS instead.
-
-config POSIX_UNAME
-	bool "Support for uname [DEPRECATED]"
-	select DEPRECATED
-	select POSIX_SINGLE_PROCESS
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_SINGLE_PROCESS instead.
-
-config PTHREAD
-	bool "pthread_t support [DEPRECATED]"
-	select DEPRECATED
-	select POSIX_THREADS
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_THREADS instead.
-
-config PTHREAD_BARRIER
-	bool "pthread_barrier_t support [DEPRECATED]"
-	select DEPRECATED
-	select POSIX_BARRIERS
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_BARRIERS instead.
-
-config PTHREAD_COND
-	bool "pthread_cond_t support [DEPRECATED]"
-	select DEPRECATED
-	select POSIX_THREADS
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_THREADS instead.
-
-
-config PTHREAD_IPC
-	bool "POSIX pthread IPC API [DEPRECATED]"
-	select DEPRECATED
-	select POSIX_THREADS
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_THREADS instead.
-
-config PTHREAD_KEY
-	bool "pthread_key_t support [DEPRECATED]"
-	select DEPRECATED
-	select POSIX_THREADS
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_THREADS instead.
-
-config PTHREAD_MUTEX
-	bool "pthread_mutex_t support [DEPRECATED]"
-	select DEPRECATED
-	select POSIX_THREADS
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_THREADS instead.
-
-config PTHREAD_RWLOCK
-	bool "pthread_spinlock_t support [DEPRECATED]"
-	select DEPRECATED
-	select POSIX_READER_WRITER_LOCKS
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_READER_WRITER_LOCKS instead.
-
-config PTHREAD_SPINLOCK
-	bool "pthread_spinlock_t support [DEPRECATED]"
-	select DEPRECATED
-	select POSIX_SPIN_LOCKS
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_SPIN_LOCKS instead.
-
-config TIMER
-	bool "Timer support [DEPRECATED]"
-	select DEPRECATED
-	select POSIX_TIMERS
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_TIMERS instead.
-
-config TIMER_DELAYTIMER_MAX
-	int "Maximum count returned my timer_getoverrun() in POSIX application [DEPRECATED]"
-	default POSIX_DELAYTIMER_MAX if POSIX_TIMERS
-	default 0
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_DELAYTIMER_MAX instead.
-
-config SEM_NAMELEN_MAX
-	int "Maximum name length [DEPRECATED]"
-	default POSIX_SEM_NAMELEN_MAX if POSIX_SEMAPHORES
-	default 0
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_SEM_NAMELEN_MAX instead.
-
-config SEM_VALUE_MAX
-	int "Maximum semaphore limit [DEPRECATED]"
-	default POSIX_SEM_VALUE_MAX if POSIX_SEMAPHORES
-	default 0
-	help
-	  This option is deprecated.
-
-	  Please use CONFIG_POSIX_SEM_VALUE_MAX instead.
-
-endmenu
diff --git a/lib/posix/options/Kconfig.mem b/lib/posix/options/Kconfig.mem
index 57b74fe0a61..346b5d363aa 100644
--- a/lib/posix/options/Kconfig.mem
+++ b/lib/posix/options/Kconfig.mem
@@ -27,10 +27,12 @@ config POSIX_SHARED_MEMORY_OBJECTS
 
 config POSIX_MAPPED_FILES
 	bool "POSIX memory-mapped files"
-	imply MMU
 	help
 	  Select 'y' here and Zephyr will provide support for mmap(), msync(), and munmap().
 
+	  Note: This feature depends on hardware MMU support. If the underlying platform does not
+	  support an MMU, then affected POSIX API functions may return -1 and set errno to ENOTSUP.
+
 	  For more information, please see
 	  https://pubs.opengroup.org/onlinepubs/9699919799.orig/functions/V2_chap02.html
 	  https://pubs.opengroup.org/onlinepubs/9699919799/xrat/V4_port.html#tag_24_03_04
@@ -42,17 +44,23 @@ config POSIX_MEMLOCK
 	help
 	  Select 'y' here and Zephyr will provide support for mlockall() and munlockall().
 
+	  Note: This feature depends on hardware MMU support as well as DEMAND_PAGING. If the
+	  underlying platform does not support an MMU or DEMAND_PAGING, then affected POSIX API
+	  functions will return -1 and set errno to ENOTSUP.
+
 	  For more information, please see
 	  https://pubs.opengroup.org/onlinepubs/9699919799.orig/functions/V2_chap02.html
 	  https://pubs.opengroup.org/onlinepubs/9699919799/xrat/V4_port.html#tag_24_03_04
 
 config POSIX_MEMLOCK_RANGE
 	bool "POSIX range memory locking"
-	imply MMU
 	imply DEMAND_PAGING
 	help
 	  Select 'y' here and Zephyr will provide support for mlock() and munlock().
 
+	  Note: This feature depends on hardware MMU support. If the underlying platform does not
+	  support an MMU, then affected POSIX API functions will return -1 and set errno to ENOTSUP.
+
 	  For more information, please see
 	  https://pubs.opengroup.org/onlinepubs/9699919799.orig/functions/V2_chap02.html
 	  https://pubs.opengroup.org/onlinepubs/9699919799/xrat/V4_port.html#tag_24_03_04
diff --git a/lib/posix/options/Kconfig.profile b/lib/posix/options/Kconfig.profile
index b57e07fbc28..2eb0c9a11ce 100644
--- a/lib/posix/options/Kconfig.profile
+++ b/lib/posix/options/Kconfig.profile
@@ -11,7 +11,6 @@ config POSIX_API
 	select POSIX_NETWORKING if NETWORKING # inet_ntoa(), socket(), etc
 	imply EVENTFD # eventfd(), eventfd_read(), eventfd_write()
 	imply POSIX_FD_MGMT # open(), close(), read(), write()
-	imply POSIX_MESSAGE_PASSING # mq_open(), etc
 	imply POSIX_MULTI_PROCESS # sleep(), getpid(), etc
 	help
 	  This option enables the required POSIX System Interfaces (base definitions), all of PSE51,
@@ -102,8 +101,8 @@ config POSIX_BASE_DEFINITIONS
 	select POSIX_ASYNCHRONOUS_IO
 	select POSIX_BARRIERS
 	select POSIX_CLOCK_SELECTION
-	# select POSIX_MAPPED_FILES
-	# select POSIX_MEMORY_PROTECTION
+	select POSIX_MAPPED_FILES
+	select POSIX_MEMORY_PROTECTION
 	select POSIX_READER_WRITER_LOCKS
 	select POSIX_REALTIME_SIGNALS
 	select POSIX_SEMAPHORES
@@ -128,10 +127,10 @@ config POSIX_AEP_REALTIME_MINIMAL
 	select XSI_THREADS_EXT
 	# Options
 	select POSIX_FSYNC
-	# select POSIX_MEMLOCK
-	# select POSIX_MEMLOCK_RANGE
+	select POSIX_MEMLOCK
+	select POSIX_MEMLOCK_RANGE
 	select POSIX_MONOTONIC_CLOCK
-	# select POSIX_SHARED_MEMORY_OBJECTS
+	select POSIX_SHARED_MEMORY_OBJECTS
 	select POSIX_SYNCHRONIZED_IO
 	select POSIX_THREAD_ATTR_STACKADDR
 	select POSIX_THREAD_ATTR_STACKSIZE
diff --git a/lib/posix/options/Kconfig.pthread b/lib/posix/options/Kconfig.pthread
index 4eef794039a..438506fe218 100644
--- a/lib/posix/options/Kconfig.pthread
+++ b/lib/posix/options/Kconfig.pthread
@@ -15,6 +15,9 @@ menuconfig POSIX_THREADS
 
 if POSIX_THREADS
 
+config HEAP_MEM_POOL_ADD_SIZE_POSIX_THREADS
+	def_int 256
+
 config POSIX_THREAD_THREADS_MAX
 	int "Maximum number of POSIX threads"
 	default 5
diff --git a/lib/posix/options/Kconfig.semaphore b/lib/posix/options/Kconfig.semaphore
index b6b839c9b1f..b2640d97041 100644
--- a/lib/posix/options/Kconfig.semaphore
+++ b/lib/posix/options/Kconfig.semaphore
@@ -33,4 +33,7 @@ config POSIX_SEM_NAMELEN_MAX
 	  Maximum length of name for a named semaphore.
 	  The max value of 255 corresponds to {NAME_MAX}.
 
+config HEAP_MEM_POOL_ADD_SIZE_POSIX_SEMAPHORES
+	def_int 256
+
 endif # POSIX_SEMAPHORES
diff --git a/lib/posix/options/Kconfig.toolchain b/lib/posix/options/Kconfig.toolchain
index 30f274067e1..e328a030879 100644
--- a/lib/posix/options/Kconfig.toolchain
+++ b/lib/posix/options/Kconfig.toolchain
@@ -135,9 +135,6 @@ config TC_PROVIDES_POSIX_READER_WRITER_LOCKS
 config TC_PROVIDES_POSIX_SEMAPHORES
 	bool
 
-config TC_PROVIDES_POSIX_SHARED_MEMORY_OBJECTS
-	bool
-
 config TC_PROVIDES_POSIX_SHELL_FUNC
 	bool
 
@@ -215,6 +212,9 @@ config TC_PROVIDES_XSI_MATH
 config TC_PROVIDES_XSI_MULTI_PROCESS
 	bool
 
+config TC_PROVIDES_XSI_REALTIME
+	bool
+
 config TC_PROVIDES_XSI_SIGNALS
 	bool
 
diff --git a/lib/posix/options/Kconfig.xsi b/lib/posix/options/Kconfig.xsi
deleted file mode 100644
index f8be61e245d..00000000000
--- a/lib/posix/options/Kconfig.xsi
+++ /dev/null
@@ -1,45 +0,0 @@
-# Copyright (c) 2024 Tenstorrent AI ULC
-#
-# SPDX-License-Identifier: Apache-2.0
-
-menu "X/Open system interfaces"
-
-config XSI_SINGLE_PROCESS
-	bool "X/Open single process"
-	depends on POSIX_SINGLE_PROCESS
-	depends on POSIX_TIMERS
-	help
-	  Select 'y' here and Zephyr will provide implementations of
-	  gethostid(), gettimeofday(), and putenv().
-
-	  For more information, please see
-	  https://pubs.opengroup.org/onlinepubs/9699919799/xrat/V4_subprofiles.html
-
-config XOPEN_STREAMS
-	bool "X/Open streams"
-	help
-	  This option provides support for the X/Open Streams interface, including functions such as
-	  fattach(), fdetach(), getmsg(), getpmsg(), putmsg(), and putpmsg().
-
-	  For more information, please see
-	  https://pubs.opengroup.org/onlinepubs/9699919799/basedefs/V1_chap02.html#tag_02_01_05_09
-
-config XSI_SYSTEM_LOGGING
-	bool "X/Open system logging"
-	help
-	  This option provides support for closelog(), openlog(), syslog(),
-	  setlogmask(), and vsyslog().
-
-	  For more information, please see
-	  https://pubs.opengroup.org/onlinepubs/9699919799/xrat/V4_subprofiles.html
-
-config XSI_THREADS_EXT
-	bool "X/Open threads extensions"
-	help
-	  This option provides support for pthread_attr_getstack(), pthread_attr_setstack(),
-	  pthread_getconcurrency(), and pthread_setconcurrency().
-
-	  For more information, please see
-	  https://pubs.opengroup.org/onlinepubs/9699919799/xrat/V4_subprofiles.html
-
-endmenu
diff --git a/lib/posix/options/Kconfig.xsi_realtime b/lib/posix/options/Kconfig.xsi_realtime
new file mode 100644
index 00000000000..4c232b77a1d
--- /dev/null
+++ b/lib/posix/options/Kconfig.xsi_realtime
@@ -0,0 +1,28 @@
+# Copyright (c) 2024 Tenstorrent AI ULC
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config XSI_REALTIME
+	bool "X/Open realtime"
+	select POSIX_FSYNC
+	select POSIX_MEMLOCK
+	select POSIX_MEMLOCK_RANGE
+	select POSIX_MESSAGE_PASSING
+	# Not yet implemented, but optional
+	# imply POSIX_PRIORITIZED_IO
+	select POSIX_PRIORITY_SCHEDULING
+	select POSIX_SHARED_MEMORY_OBJECTS
+	select POSIX_SYNCHRONIZED_IO
+	help
+	  Select 'y' here and the following functions will be provided:
+
+	  fsync(), mlockall(), munlockall(), mlock(), munlock(), mq_close(), mq_getattr(), mq_notify(),
+	  mq_open(), mq_receive(), mq_send(), mq_setattr(), mq_unlink(), sched_get_priority_max(),
+	  sched_get_priority_min(), sched_getparam(), sched_getscheduler(), sched_rr_get_interval(),
+	  sched_setparam(), sched_setscheduler(), sched_yield(), mmap(), munmap(), shm_open(),
+	  shm_unlink()
+
+	  The functions fsync(), fdatasync(), and open() will provide synchronized I/O capability.
+
+	  For more information, please see
+	  https://pubs.opengroup.org/onlinepubs/9699919799/basedefs/V1_chap02.html
diff --git a/lib/posix/options/Kconfig.xsi_single_process b/lib/posix/options/Kconfig.xsi_single_process
new file mode 100644
index 00000000000..ac5a8316455
--- /dev/null
+++ b/lib/posix/options/Kconfig.xsi_single_process
@@ -0,0 +1,14 @@
+# Copyright (c) 2024 Tenstorrent AI ULC
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config XSI_SINGLE_PROCESS
+	bool "X/Open single process"
+	depends on POSIX_SINGLE_PROCESS
+	depends on POSIX_TIMERS
+	help
+	  Select 'y' here and Zephyr will provide implementations of
+	  gethostid(), gettimeofday(), and putenv().
+
+	  For more information, please see
+	  https://pubs.opengroup.org/onlinepubs/9699919799/xrat/V4_subprofiles.html
diff --git a/lib/posix/options/Kconfig.xsi_streams b/lib/posix/options/Kconfig.xsi_streams
new file mode 100644
index 00000000000..21b7e2010b5
--- /dev/null
+++ b/lib/posix/options/Kconfig.xsi_streams
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Tenstorrent AI ULC
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config XOPEN_STREAMS
+	bool "X/Open streams"
+	help
+	  This option provides support for the X/Open Streams interface, including functions such as
+	  fattach(), fdetach(), getmsg(), getpmsg(), putmsg(), and putpmsg().
+
+	  For more information, please see
+	  https://pubs.opengroup.org/onlinepubs/9699919799/basedefs/V1_chap02.html#tag_02_01_05_09
diff --git a/lib/posix/options/Kconfig.xsi_system_logging b/lib/posix/options/Kconfig.xsi_system_logging
new file mode 100644
index 00000000000..c7d9186bd9b
--- /dev/null
+++ b/lib/posix/options/Kconfig.xsi_system_logging
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Tenstorrent AI ULC
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config XSI_SYSTEM_LOGGING
+	bool "X/Open system logging"
+	help
+	  This option provides support for closelog(), openlog(), syslog(),
+	  setlogmask(), and vsyslog().
+
+	  For more information, please see
+	  https://pubs.opengroup.org/onlinepubs/9699919799/xrat/V4_subprofiles.html
diff --git a/lib/posix/options/Kconfig.xsi_threads_ext b/lib/posix/options/Kconfig.xsi_threads_ext
new file mode 100644
index 00000000000..b990ff46309
--- /dev/null
+++ b/lib/posix/options/Kconfig.xsi_threads_ext
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Tenstorrent AI ULC
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config XSI_THREADS_EXT
+	bool "X/Open threads extensions"
+	help
+	  This option provides support for pthread_attr_getstack(), pthread_attr_setstack(),
+	  pthread_getconcurrency(), and pthread_setconcurrency().
+
+	  For more information, please see
+	  https://pubs.opengroup.org/onlinepubs/9699919799/xrat/V4_subprofiles.html
diff --git a/lib/posix/options/barrier.c b/lib/posix/options/barrier.c
index 7e2598b1bde..c108b28da21 100644
--- a/lib/posix/options/barrier.c
+++ b/lib/posix/options/barrier.c
@@ -19,7 +19,9 @@ struct posix_barrier {
 	uint32_t count;
 };
 
+__pinned_bss
 static struct posix_barrier posix_barrier_pool[CONFIG_MAX_PTHREAD_BARRIER_COUNT];
+
 SYS_BITARRAY_DEFINE_STATIC(posix_barrier_bitarray, CONFIG_MAX_PTHREAD_BARRIER_COUNT);
 
 /*
@@ -195,6 +197,7 @@ int pthread_barrierattr_destroy(pthread_barrierattr_t *attr)
 	return 0;
 }
 
+__boot_func
 static int pthread_barrier_pool_init(void)
 {
 	int err;
diff --git a/lib/posix/options/cond.c b/lib/posix/options/cond.c
index f94c2ea7a3b..c93386ab539 100644
--- a/lib/posix/options/cond.c
+++ b/lib/posix/options/cond.c
@@ -5,6 +5,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "posix_clock.h"
 #include "posix_internal.h"
 
 #include <zephyr/init.h>
@@ -15,11 +16,13 @@
 
 LOG_MODULE_REGISTER(pthread_cond, CONFIG_PTHREAD_COND_LOG_LEVEL);
 
-int64_t timespec_to_timeoutms(const struct timespec *abstime);
+static __pinned_bss struct posix_cond posix_cond_pool[CONFIG_MAX_PTHREAD_COND_COUNT];
 
-static struct k_condvar posix_cond_pool[CONFIG_MAX_PTHREAD_COND_COUNT];
 SYS_BITARRAY_DEFINE_STATIC(posix_cond_bitarray, CONFIG_MAX_PTHREAD_COND_COUNT);
 
+BUILD_ASSERT(sizeof(struct posix_condattr) <= sizeof(pthread_condattr_t),
+	     "posix_condattr is too large");
+
 /*
  * We reserve the MSB to mark a pthread_cond_t as initialized (from the
  * perspective of the application). With a linear space, this means that
@@ -28,7 +31,7 @@ SYS_BITARRAY_DEFINE_STATIC(posix_cond_bitarray, CONFIG_MAX_PTHREAD_COND_COUNT);
 BUILD_ASSERT(CONFIG_MAX_PTHREAD_COND_COUNT < PTHREAD_OBJ_MASK_INIT,
 	     "CONFIG_MAX_PTHREAD_COND_COUNT is too high");
 
-static inline size_t posix_cond_to_offset(struct k_condvar *cv)
+static inline size_t posix_cond_to_offset(struct posix_cond *cv)
 {
 	return cv - posix_cond_pool;
 }
@@ -38,7 +41,7 @@ static inline size_t to_posix_cond_idx(pthread_cond_t cond)
 	return mark_pthread_obj_uninitialized(cond);
 }
 
-static struct k_condvar *get_posix_cond(pthread_cond_t cond)
+static struct posix_cond *get_posix_cond(pthread_cond_t cond)
 {
 	int actually_initialized;
 	size_t bit = to_posix_cond_idx(cond);
@@ -64,10 +67,10 @@ static struct k_condvar *get_posix_cond(pthread_cond_t cond)
 	return &posix_cond_pool[bit];
 }
 
-static struct k_condvar *to_posix_cond(pthread_cond_t *cvar)
+static struct posix_cond *to_posix_cond(pthread_cond_t *cvar)
 {
 	size_t bit;
-	struct k_condvar *cv;
+	struct posix_cond *cv;
 
 	if (*cvar != PTHREAD_COND_INITIALIZER) {
 		return get_posix_cond(*cvar);
@@ -83,15 +86,17 @@ static struct k_condvar *to_posix_cond(pthread_cond_t *cvar)
 	/* Record the associated posix_cond in mu and mark as initialized */
 	*cvar = mark_pthread_obj_initialized(bit);
 	cv = &posix_cond_pool[bit];
+	(void)pthread_condattr_init((pthread_condattr_t *)&cv->attr);
 
 	return cv;
 }
 
-static int cond_wait(pthread_cond_t *cond, pthread_mutex_t *mu, k_timeout_t timeout)
+static int cond_wait(pthread_cond_t *cond, pthread_mutex_t *mu, const struct timespec *abstime)
 {
 	int ret;
 	struct k_mutex *m;
-	struct k_condvar *cv;
+	struct posix_cond *cv;
+	k_timeout_t timeout = K_FOREVER;
 
 	m = to_posix_mutex(mu);
 	cv = to_posix_cond(cond);
@@ -99,8 +104,12 @@ static int cond_wait(pthread_cond_t *cond, pthread_mutex_t *mu, k_timeout_t time
 		return EINVAL;
 	}
 
+	if (abstime != NULL) {
+		timeout = K_MSEC(timespec_to_timeoutms(cv->attr.clock, abstime));
+	}
+
 	LOG_DBG("Waiting on cond %p with timeout %llx", cv, timeout.ticks);
-	ret = k_condvar_wait(cv, m, timeout);
+	ret = k_condvar_wait(&cv->condvar, m, timeout);
 	if (ret == -EAGAIN) {
 		LOG_DBG("Timeout waiting on cond %p", cv);
 		ret = ETIMEDOUT;
@@ -118,7 +127,7 @@ static int cond_wait(pthread_cond_t *cond, pthread_mutex_t *mu, k_timeout_t time
 int pthread_cond_signal(pthread_cond_t *cvar)
 {
 	int ret;
-	struct k_condvar *cv;
+	struct posix_cond *cv;
 
 	cv = to_posix_cond(cvar);
 	if (cv == NULL) {
@@ -126,7 +135,7 @@ int pthread_cond_signal(pthread_cond_t *cvar)
 	}
 
 	LOG_DBG("Signaling cond %p", cv);
-	ret = k_condvar_signal(cv);
+	ret = k_condvar_signal(&cv->condvar);
 	if (ret < 0) {
 		LOG_DBG("k_condvar_signal() failed: %d", ret);
 		return -ret;
@@ -140,7 +149,7 @@ int pthread_cond_signal(pthread_cond_t *cvar)
 int pthread_cond_broadcast(pthread_cond_t *cvar)
 {
 	int ret;
-	struct k_condvar *cv;
+	struct posix_cond *cv;
 
 	cv = get_posix_cond(*cvar);
 	if (cv == NULL) {
@@ -148,7 +157,7 @@ int pthread_cond_broadcast(pthread_cond_t *cvar)
 	}
 
 	LOG_DBG("Broadcasting on cond %p", cv);
-	ret = k_condvar_broadcast(cv);
+	ret = k_condvar_broadcast(&cv->condvar);
 	if (ret < 0) {
 		LOG_DBG("k_condvar_broadcast() failed: %d", ret);
 		return -ret;
@@ -161,27 +170,39 @@ int pthread_cond_broadcast(pthread_cond_t *cvar)
 
 int pthread_cond_wait(pthread_cond_t *cv, pthread_mutex_t *mut)
 {
-	return cond_wait(cv, mut, K_FOREVER);
+	return cond_wait(cv, mut, NULL);
 }
 
 int pthread_cond_timedwait(pthread_cond_t *cv, pthread_mutex_t *mut, const struct timespec *abstime)
 {
-	return cond_wait(cv, mut, K_MSEC((int32_t)timespec_to_timeoutms(abstime)));
+	if ((abstime == NULL) || !timespec_is_valid(abstime)) {
+		LOG_DBG("%s is invalid", "abstime");
+		return EINVAL;
+	}
+
+	return cond_wait(cv, mut, abstime);
 }
 
 int pthread_cond_init(pthread_cond_t *cvar, const pthread_condattr_t *att)
 {
-	struct k_condvar *cv;
+	struct posix_cond *cv;
+	struct posix_condattr *attr = (struct posix_condattr *)att;
 
-	ARG_UNUSED(att);
 	*cvar = PTHREAD_COND_INITIALIZER;
-
-	/* calls k_condvar_init() */
 	cv = to_posix_cond(cvar);
 	if (cv == NULL) {
 		return ENOMEM;
 	}
 
+	if (attr != NULL) {
+		if (!attr->initialized) {
+			return EINVAL;
+		}
+
+		(void)pthread_condattr_destroy((pthread_condattr_t *)&cv->attr);
+		cv->attr = *attr;
+	}
+
 	LOG_DBG("Initialized cond %p", cv);
 
 	return 0;
@@ -191,7 +212,7 @@ int pthread_cond_destroy(pthread_cond_t *cvar)
 {
 	int err;
 	size_t bit;
-	struct k_condvar *cv;
+	struct posix_cond *cv;
 
 	cv = get_posix_cond(*cvar);
 	if (cv == NULL) {
@@ -209,13 +230,14 @@ int pthread_cond_destroy(pthread_cond_t *cvar)
 	return 0;
 }
 
+__boot_func
 static int pthread_cond_pool_init(void)
 {
 	int err;
 	size_t i;
 
 	for (i = 0; i < CONFIG_MAX_PTHREAD_COND_COUNT; ++i) {
-		err = k_condvar_init(&posix_cond_pool[i]);
+		err = k_condvar_init(&posix_cond_pool[i].condvar);
 		__ASSERT_NO_MSG(err == 0);
 	}
 
@@ -224,16 +246,32 @@ static int pthread_cond_pool_init(void)
 
 int pthread_condattr_init(pthread_condattr_t *att)
 {
-	__ASSERT_NO_MSG(att != NULL);
+	struct posix_condattr *const attr = (struct posix_condattr *)att;
 
-	att->clock = CLOCK_MONOTONIC;
+	if (att == NULL) {
+		return EINVAL;
+	}
+	if (attr->initialized) {
+		LOG_DBG("%s %s initialized", "attribute", "already");
+		return EINVAL;
+	}
+
+	attr->clock = CLOCK_REALTIME;
+	attr->initialized = true;
 
 	return 0;
 }
 
 int pthread_condattr_destroy(pthread_condattr_t *att)
 {
-	ARG_UNUSED(att);
+	struct posix_condattr *const attr = (struct posix_condattr *)att;
+
+	if ((attr == NULL) || !attr->initialized) {
+		LOG_DBG("%s %s initialized", "attribute", "not");
+		return EINVAL;
+	}
+
+	*attr = (struct posix_condattr){0};
 
 	return 0;
 }
@@ -241,18 +279,32 @@ int pthread_condattr_destroy(pthread_condattr_t *att)
 int pthread_condattr_getclock(const pthread_condattr_t *ZRESTRICT att,
 		clockid_t *ZRESTRICT clock_id)
 {
-	*clock_id = att->clock;
+	struct posix_condattr *const attr = (struct posix_condattr *)att;
+
+	if ((attr == NULL) || !attr->initialized) {
+		LOG_DBG("%s %s initialized", "attribute", "not");
+		return EINVAL;
+	}
+
+	*clock_id = attr->clock;
 
 	return 0;
 }
 
 int pthread_condattr_setclock(pthread_condattr_t *att, clockid_t clock_id)
 {
+	struct posix_condattr *const attr = (struct posix_condattr *)att;
+
 	if (clock_id != CLOCK_REALTIME && clock_id != CLOCK_MONOTONIC) {
 		return -EINVAL;
 	}
 
-	att->clock = clock_id;
+	if ((attr == NULL) || !attr->initialized) {
+		LOG_DBG("%s %s initialized", "attribute", "not");
+		return EINVAL;
+	}
+
+	attr->clock = clock_id;
 
 	return 0;
 }
diff --git a/lib/posix/options/key.c b/lib/posix/options/key.c
index aba457e944e..db703949142 100644
--- a/lib/posix/options/key.c
+++ b/lib/posix/options/key.c
@@ -26,7 +26,7 @@ SYS_SEM_DEFINE(pthread_key_lock, 1, 1);
  * the theoretical pthread_key_t range is [0,2147483647].
  */
 BUILD_ASSERT(CONFIG_POSIX_THREAD_KEYS_MAX < PTHREAD_OBJ_MASK_INIT,
-	     "CONFIG_MAX_PTHREAD_KEY_COUNT is too high");
+	     "CONFIG_POSIX_THREAD_KEYS_MAX is too high");
 
 static pthread_key_obj posix_key_pool[CONFIG_POSIX_THREAD_KEYS_MAX];
 SYS_BITARRAY_DEFINE_STATIC(posix_key_bitarray, CONFIG_POSIX_THREAD_KEYS_MAX);
diff --git a/lib/posix/options/mlock.c b/lib/posix/options/mlock.c
index b81773c3a57..00fee6a2965 100644
--- a/lib/posix/options/mlock.c
+++ b/lib/posix/options/mlock.c
@@ -9,16 +9,32 @@
 #include <zephyr/kernel.h>
 #include <zephyr/posix/sys/mman.h>
 
+#include <zephyr/kernel/mm/demand_paging.h>
+
 int mlock(const void *addr, size_t len)
 {
-	k_mem_pin(addr, len);
+	if (IS_ENABLED(CONFIG_DEMAND_PAGING)) {
+		void *const _addr = (void *)addr;
+
+		k_mem_pin(_addr, len);
+
+		return 0;
+	}
 
-	return 0;
+	errno = ENOTSUP;
+	return -1;
 }
 
 int munlock(const void *addr, size_t len)
 {
-	k_mem_unpin(addr, len);
+	if (IS_ENABLED(CONFIG_DEMAND_PAGING)) {
+		void *const _addr = (void *)addr;
+
+		k_mem_unpin(_addr, len);
+
+		return 0;
+	}
 
-	return 0;
+	errno = ENOTSUP;
+	return -1;
 }
diff --git a/lib/posix/options/mlockall.c b/lib/posix/options/mlockall.c
index e921b932535..506eeb62102 100644
--- a/lib/posix/options/mlockall.c
+++ b/lib/posix/options/mlockall.c
@@ -9,6 +9,7 @@
 #include <sys/types.h>
 
 #include <zephyr/posix/sys/mman.h>
+#include <zephyr/toolchain.h>
 
 int mlockall(int flags)
 {
diff --git a/lib/posix/options/mprotect.c b/lib/posix/options/mprotect.c
index 3bd2762763a..6c795e3b963 100644
--- a/lib/posix/options/mprotect.c
+++ b/lib/posix/options/mprotect.c
@@ -9,6 +9,7 @@
 #include <sys/types.h>
 
 #include <zephyr/posix/sys/mman.h>
+#include <zephyr/toolchain.h>
 
 int mprotect(void *addr, size_t len, int prot)
 {
diff --git a/lib/posix/options/mqueue.c b/lib/posix/options/mqueue.c
index ce77283e637..0eef3f81ccf 100644
--- a/lib/posix/options/mqueue.c
+++ b/lib/posix/options/mqueue.c
@@ -4,6 +4,9 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+
+#include "posix_clock.h"
+
 #include <zephyr/kernel.h>
 #include <errno.h>
 #include <string.h>
@@ -34,7 +37,6 @@ K_SEM_DEFINE(mq_sem, 1, 1);
 /* Initialize the list */
 sys_slist_t mq_list = SYS_SLIST_STATIC_INIT(&mq_list);
 
-int64_t timespec_to_timeoutms(const struct timespec *abstime);
 static mqueue_object *find_in_list(const char *name);
 static int32_t send_message(mqueue_desc *mqd, const char *msg_ptr, size_t msg_len,
 			  k_timeout_t timeout);
@@ -255,9 +257,14 @@ int mq_timedsend(mqd_t mqdes, const char *msg_ptr, size_t msg_len,
 		 unsigned int msg_prio, const struct timespec *abstime)
 {
 	mqueue_desc *mqd = (mqueue_desc *)mqdes;
-	int32_t timeout = (int32_t) timespec_to_timeoutms(abstime);
 
-	return send_message(mqd, msg_ptr, msg_len, K_MSEC(timeout));
+	if ((abstime == NULL) || !timespec_is_valid(abstime)) {
+		errno = EINVAL;
+		return -1;
+	}
+
+	return send_message(mqd, msg_ptr, msg_len,
+			    K_MSEC(timespec_to_timeoutms(CLOCK_REALTIME, abstime)));
 }
 
 /**
@@ -286,9 +293,14 @@ int mq_timedreceive(mqd_t mqdes, char *msg_ptr, size_t msg_len,
 			unsigned int *msg_prio, const struct timespec *abstime)
 {
 	mqueue_desc *mqd = (mqueue_desc *)mqdes;
-	int32_t timeout = (int32_t) timespec_to_timeoutms(abstime);
 
-	return receive_message(mqd, msg_ptr, msg_len, K_MSEC(timeout));
+	if ((abstime == NULL) || !timespec_is_valid(abstime)) {
+		errno = EINVAL;
+		return -1;
+	}
+
+	return receive_message(mqd, msg_ptr, msg_len,
+			       K_MSEC(timespec_to_timeoutms(CLOCK_REALTIME, abstime)));
 }
 
 /**
@@ -424,7 +436,7 @@ static mqueue_object *find_in_list(const char *name)
 
 	while (mq != NULL) {
 		msg_queue = (mqueue_object *)mq;
-		if (strcmp(msg_queue->name, name) == 0) {
+		if ((msg_queue->name != NULL) && (strcmp(msg_queue->name, name) == 0)) {
 			return msg_queue;
 		}
 
diff --git a/lib/posix/options/mutex.c b/lib/posix/options/mutex.c
index cd320a969dc..52dec35d249 100644
--- a/lib/posix/options/mutex.c
+++ b/lib/posix/options/mutex.c
@@ -5,6 +5,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "posix_clock.h"
 #include "posix_internal.h"
 
 #include <zephyr/init.h>
@@ -18,8 +19,6 @@ LOG_MODULE_REGISTER(pthread_mutex, CONFIG_PTHREAD_MUTEX_LOG_LEVEL);
 
 static SYS_SEM_DEFINE(lock, 1, 1);
 
-int64_t timespec_to_timeoutms(const struct timespec *abstime);
-
 #define MUTEX_MAX_REC_LOCK 32767
 
 /*
@@ -29,7 +28,9 @@ static const struct pthread_mutexattr def_attr = {
 	.type = PTHREAD_MUTEX_DEFAULT,
 };
 
+__pinned_bss
 static struct k_mutex posix_mutex_pool[CONFIG_MAX_PTHREAD_MUTEX_COUNT];
+
 static uint8_t posix_mutex_type[CONFIG_MAX_PTHREAD_MUTEX_COUNT];
 SYS_BITARRAY_DEFINE_STATIC(posix_mutex_bitarray, CONFIG_MAX_PTHREAD_MUTEX_COUNT);
 
@@ -210,8 +211,12 @@ int pthread_mutex_trylock(pthread_mutex_t *m)
 int pthread_mutex_timedlock(pthread_mutex_t *m,
 			    const struct timespec *abstime)
 {
-	int32_t timeout = (int32_t)timespec_to_timeoutms(abstime);
-	return acquire_mutex(m, K_MSEC(timeout));
+	if ((abstime == NULL) || !timespec_is_valid(abstime)) {
+		LOG_DBG("%s is invalid", "abstime");
+		return EINVAL;
+	}
+
+	return acquire_mutex(m, K_MSEC(timespec_to_timeoutms(CLOCK_REALTIME, abstime)));
 }
 
 /**
@@ -451,6 +456,7 @@ int pthread_mutexattr_setprioceiling(pthread_mutexattr_t *attr, int prioceiling)
 
 #endif /* CONFIG_POSIX_THREAD_PRIO_PROTECT */
 
+__boot_func
 static int pthread_mutex_pool_init(void)
 {
 	int err;
diff --git a/lib/posix/options/net.c b/lib/posix/options/net.c
index 84e4001a9b4..883bb9145ac 100644
--- a/lib/posix/options/net.c
+++ b/lib/posix/options/net.c
@@ -19,7 +19,7 @@
 
 in_addr_t inet_addr(const char *cp)
 {
-	int val = 0;
+	unsigned int val = 0;
 	int len = 0;
 	int dots = 0;
 	int digits = 0;
diff --git a/lib/posix/options/posix_clock.h b/lib/posix/options/posix_clock.h
index f505dbc1752..12de6f9fe8c 100644
--- a/lib/posix/options/posix_clock.h
+++ b/lib/posix/options/posix_clock.h
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2023, Meta
+ * Copyright (c) 2025 Tenstorrent AI ULC
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,13 +8,65 @@
 #ifndef ZEPHYR_LIB_POSIX_POSIX_CLOCK_H_
 #define ZEPHYR_LIB_POSIX_POSIX_CLOCK_H_
 
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
 #include <time.h>
 
-#include <zephyr/kernel.h>
-#include <zephyr/posix/posix_types.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/sys/__assert.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @cond INTERNAL_HIDDEN */
+
+static inline bool timespec_is_valid(const struct timespec *ts)
+{
+	__ASSERT_NO_MSG(ts != NULL);
+	return (ts->tv_nsec >= 0) && (ts->tv_nsec < NSEC_PER_SEC);
+}
+
+static inline int64_t ts_to_ns(const struct timespec *ts)
+{
+	return ts->tv_sec * NSEC_PER_SEC + ts->tv_nsec;
+}
+
+static inline int64_t ts_to_ms(const struct timespec *ts)
+{
+	return ts->tv_sec * MSEC_PER_SEC + ts->tv_nsec / NSEC_PER_MSEC;
+}
+
+static inline bool tp_ge(const struct timespec *a, const struct timespec *b)
+{
+	return ts_to_ns(a) >= ts_to_ns(b);
+}
+
+static inline int64_t tp_diff(const struct timespec *a, const struct timespec *b)
+{
+	return ts_to_ns(a) - ts_to_ns(b);
+}
+
+/* lo <= (a - b) < hi */
+static inline bool tp_diff_in_range_ns(const struct timespec *a, const struct timespec *b,
+				       int64_t lo, int64_t hi)
+{
+	int64_t diff = tp_diff(a, b);
+
+	return diff >= lo && diff < hi;
+}
+
+uint32_t timespec_to_timeoutms(clockid_t clock_id, const struct timespec *abstime);
 
 __syscall int __posix_clock_get_base(clockid_t clock_id, struct timespec *ts);
 
+/** INTERNAL_HIDDEN @endcond */
+
 #include <zephyr/syscalls/posix_clock.h>
 
+#ifdef __cplusplus
+}
+#endif
+
 #endif
diff --git a/lib/posix/options/posix_internal.h b/lib/posix/options/posix_internal.h
index 24bfb83e14b..3a4804d0ee4 100644
--- a/lib/posix/options/posix_internal.h
+++ b/lib/posix/options/posix_internal.h
@@ -66,6 +66,20 @@ struct posix_thread {
 	uint8_t qid;
 };
 
+struct posix_condattr {
+	/* leaves room for CLOCK_REALTIME (1, default) and CLOCK_MONOTONIC (4) */
+	unsigned int clock: 3;
+	bool initialized: 1;
+#ifdef _POSIX_THREAD_PROCESS_SHARED
+	unsigned int pshared: 1;
+#endif
+};
+
+struct posix_cond {
+	struct k_condvar condvar;
+	struct posix_condattr attr;
+};
+
 typedef struct pthread_key_obj {
 	/* List of pthread_key_data objects that contain thread
 	 * specific data for the key
diff --git a/lib/posix/options/pthread.c b/lib/posix/options/pthread.c
index c54a061f9e7..c505b8564bb 100644
--- a/lib/posix/options/pthread.c
+++ b/lib/posix/options/pthread.c
@@ -5,6 +5,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "posix_clock.h"
 #include "posix_internal.h"
 #include "pthread_sched.h"
 
@@ -81,14 +82,17 @@ BUILD_ASSERT((PTHREAD_CANCEL_ENABLE == 0 || PTHREAD_CANCEL_DISABLE == 0) &&
 BUILD_ASSERT(CONFIG_POSIX_PTHREAD_ATTR_STACKSIZE_BITS + CONFIG_POSIX_PTHREAD_ATTR_GUARDSIZE_BITS <=
 	     32);
 
-int64_t timespec_to_timeoutms(const struct timespec *abstime);
 static void posix_thread_recycle(void);
+
+__pinned_data
 static sys_dlist_t posix_thread_q[] = {
 	SYS_DLIST_STATIC_INIT(&posix_thread_q[POSIX_THREAD_READY_Q]),
 	SYS_DLIST_STATIC_INIT(&posix_thread_q[POSIX_THREAD_RUN_Q]),
 	SYS_DLIST_STATIC_INIT(&posix_thread_q[POSIX_THREAD_DONE_Q]),
 };
-static struct posix_thread posix_thread_pool[CONFIG_MAX_PTHREAD_COUNT];
+
+static __pinned_bss struct posix_thread posix_thread_pool[CONFIG_POSIX_THREAD_THREADS_MAX];
+
 static SYS_SEM_DEFINE(pthread_pool_lock, 1, 1);
 static int pthread_concurrency;
 
@@ -1145,15 +1149,13 @@ static int pthread_timedjoin_internal(pthread_t pthread, void **status, k_timeou
  */
 int pthread_timedjoin_np(pthread_t pthread, void **status, const struct timespec *abstime)
 {
-	if (abstime == NULL) {
-		return EINVAL;
-	}
-
-	if (abstime->tv_sec < 0 || abstime->tv_nsec < 0 || abstime->tv_nsec >= NSEC_PER_SEC) {
+	if ((abstime == NULL) || !timespec_is_valid(abstime)) {
+		LOG_DBG("%s is invalid", "abstime");
 		return EINVAL;
 	}
 
-	return pthread_timedjoin_internal(pthread, status, K_MSEC(timespec_to_timeoutms(abstime)));
+	return pthread_timedjoin_internal(pthread, status,
+					  K_MSEC(timespec_to_timeoutms(CLOCK_REALTIME, abstime)));
 }
 
 /**
@@ -1536,6 +1538,7 @@ int pthread_sigmask(int how, const sigset_t *ZRESTRICT set, sigset_t *ZRESTRICT
 	return ret;
 }
 
+__boot_func
 static int posix_thread_pool_init(void)
 {
 	ARRAY_FOR_EACH_PTR(posix_thread_pool, th) {
diff --git a/lib/posix/options/rwlock.c b/lib/posix/options/rwlock.c
index fab35ec84a2..b7eb21bd6be 100644
--- a/lib/posix/options/rwlock.c
+++ b/lib/posix/options/rwlock.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "posix_clock.h"
 #include "posix_internal.h"
 
 #include <zephyr/init.h>
@@ -27,9 +28,8 @@ struct posix_rwlockattr {
 	bool pshared: 1;
 };
 
-int64_t timespec_to_timeoutms(const struct timespec *abstime);
-static uint32_t read_lock_acquire(struct posix_rwlock *rwl, int32_t timeout);
-static uint32_t write_lock_acquire(struct posix_rwlock *rwl, int32_t timeout);
+static uint32_t read_lock_acquire(struct posix_rwlock *rwl, uint32_t timeout);
+static uint32_t write_lock_acquire(struct posix_rwlock *rwl, uint32_t timeout);
 
 LOG_MODULE_REGISTER(pthread_rwlock, CONFIG_PTHREAD_RWLOCK_LOG_LEVEL);
 
@@ -198,22 +198,20 @@ int pthread_rwlock_rdlock(pthread_rwlock_t *rwlock)
 int pthread_rwlock_timedrdlock(pthread_rwlock_t *rwlock,
 			       const struct timespec *abstime)
 {
-	int32_t timeout;
 	uint32_t ret = 0U;
 	struct posix_rwlock *rwl;
 
-	if (abstime->tv_nsec < 0 || abstime->tv_nsec > NSEC_PER_SEC) {
+	if ((abstime == NULL) || !timespec_is_valid(abstime)) {
+		LOG_DBG("%s is invalid", "abstime");
 		return EINVAL;
 	}
 
-	timeout = (int32_t) timespec_to_timeoutms(abstime);
-
 	rwl = get_posix_rwlock(*rwlock);
 	if (rwl == NULL) {
 		return EINVAL;
 	}
 
-	if (read_lock_acquire(rwl, timeout) != 0U) {
+	if (read_lock_acquire(rwl, timespec_to_timeoutms(CLOCK_REALTIME, abstime)) != 0U) {
 		ret = ETIMEDOUT;
 	}
 
@@ -271,22 +269,20 @@ int pthread_rwlock_wrlock(pthread_rwlock_t *rwlock)
 int pthread_rwlock_timedwrlock(pthread_rwlock_t *rwlock,
 			       const struct timespec *abstime)
 {
-	int32_t timeout;
 	uint32_t ret = 0U;
 	struct posix_rwlock *rwl;
 
-	if (abstime->tv_nsec < 0 || abstime->tv_nsec > NSEC_PER_SEC) {
+	if ((abstime == NULL) || !timespec_is_valid(abstime)) {
+		LOG_DBG("%s is invalid", "abstime");
 		return EINVAL;
 	}
 
-	timeout = (int32_t) timespec_to_timeoutms(abstime);
-
 	rwl = get_posix_rwlock(*rwlock);
 	if (rwl == NULL) {
 		return EINVAL;
 	}
 
-	if (write_lock_acquire(rwl, timeout) != 0U) {
+	if (write_lock_acquire(rwl, timespec_to_timeoutms(CLOCK_REALTIME, abstime)) != 0U) {
 		ret = ETIMEDOUT;
 	}
 
@@ -345,7 +341,7 @@ int pthread_rwlock_unlock(pthread_rwlock_t *rwlock)
 	return 0;
 }
 
-static uint32_t read_lock_acquire(struct posix_rwlock *rwl, int32_t timeout)
+static uint32_t read_lock_acquire(struct posix_rwlock *rwl, uint32_t timeout)
 {
 	uint32_t ret = 0U;
 
@@ -360,7 +356,7 @@ static uint32_t read_lock_acquire(struct posix_rwlock *rwl, int32_t timeout)
 	return ret;
 }
 
-static uint32_t write_lock_acquire(struct posix_rwlock *rwl, int32_t timeout)
+static uint32_t write_lock_acquire(struct posix_rwlock *rwl, uint32_t timeout)
 {
 	uint32_t ret = 0U;
 	int64_t elapsed_time, st_time = k_uptime_get();
diff --git a/lib/posix/options/semaphore.c b/lib/posix/options/semaphore.c
index fddad0caf6b..55ac57c5cfd 100644
--- a/lib/posix/options/semaphore.c
+++ b/lib/posix/options/semaphore.c
@@ -5,6 +5,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "posix_clock.h"
+
 #include <errno.h>
 #include <zephyr/kernel.h>
 #include <zephyr/sys/atomic.h>
@@ -33,7 +35,7 @@ static inline void nsem_list_lock(void)
 
 static inline void nsem_list_unlock(void)
 {
-	k_mutex_unlock(&nsem_mutex);
+	(void)k_mutex_unlock(&nsem_mutex);
 }
 
 static struct nsem_obj *nsem_find(const char *name)
@@ -60,7 +62,7 @@ static void nsem_cleanup(struct nsem_obj *nsem)
 	}
 }
 
-/* Remove a named semaphore if it isn't unsed */
+/* Remove a named semaphore if it isn't used */
 static void nsem_unref(struct nsem_obj *nsem)
 {
 	nsem->ref_count -= 1;
@@ -159,31 +161,12 @@ int sem_post(sem_t *semaphore)
  */
 int sem_timedwait(sem_t *semaphore, struct timespec *abstime)
 {
-	int32_t timeout;
-	struct timespec current;
-	int64_t current_ms, abstime_ms;
-
-	__ASSERT(abstime, "abstime pointer NULL");
-
-	if ((abstime->tv_sec < 0) || (abstime->tv_nsec >= NSEC_PER_SEC)) {
+	if ((abstime == NULL) || !timespec_is_valid(abstime)) {
 		errno = EINVAL;
 		return -1;
 	}
 
-	if (clock_gettime(CLOCK_REALTIME, &current) < 0) {
-		return -1;
-	}
-
-	abstime_ms = (int64_t)_ts_to_ms(abstime);
-	current_ms = (int64_t)_ts_to_ms(&current);
-
-	if (abstime_ms <= current_ms) {
-		timeout = 0;
-	} else {
-		timeout = (int32_t)(abstime_ms - current_ms);
-	}
-
-	if (k_sem_take(semaphore, K_MSEC(timeout))) {
+	if (k_sem_take(semaphore, K_MSEC(timespec_to_timeoutms(CLOCK_REALTIME, abstime)))) {
 		errno = ETIMEDOUT;
 		return -1;
 	}
@@ -265,7 +248,7 @@ sem_t *sem_open(const char *name, int oflags, ...)
 		goto unlock;
 	}
 
-	/* Named sempahore doesn't exist, try to create new one */
+	/* Named semaphore doesn't exist, try to create new one */
 
 	if ((oflags & O_CREAT) == 0) {
 		errno = ENOENT;
diff --git a/lib/posix/options/shm.c b/lib/posix/options/shm.c
index d57fff74454..56f45d0457a 100644
--- a/lib/posix/options/shm.c
+++ b/lib/posix/options/shm.c
@@ -159,7 +159,7 @@ static off_t shm_lseek(struct shm_obj *shm, off_t offset, int whence, size_t cur
 		return -1;
 	}
 
-	if ((INTPTR_MAX - addend) < offset) {
+	if ((addend > INTPTR_MAX) || ((INTPTR_MAX - addend) < offset)) {
 		errno = EOVERFLOW;
 		return -1;
 	}
@@ -305,7 +305,7 @@ int shm_open(const char *name, int oflag, mode_t mode)
 	bool rw = (oflag & O_RDWR) != 0;
 	bool creat = (oflag & O_CREAT) != 0;
 	bool excl = (oflag & O_EXCL) != 0;
-	bool trunc = false; /* (oflag & O_TRUNC) != 0 */
+	bool trunc = (oflag & O_TRUNC) != 0;
 	size_t name_len = (name == NULL) ? 0 : strnlen(name, PATH_MAX);
 
 	/* revisit when file-based permissions are available */
diff --git a/lib/posix/options/timer.c b/lib/posix/options/timer.c
index 3c14a01a3ad..257fdce59ef 100644
--- a/lib/posix/options/timer.c
+++ b/lib/posix/options/timer.c
@@ -4,8 +4,12 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+
 #undef _POSIX_C_SOURCE
 #define _POSIX_C_SOURCE 200809L
+
+#include "posix_clock.h"
+
 #include <errno.h>
 
 #include <zephyr/kernel.h>
@@ -190,7 +194,7 @@ int timer_create(clockid_t clockid, struct sigevent *evp, timer_t *timerid)
 	goto out;
 
 free_timer:
-	k_mem_slab_free(&posix_timer_slab, (void *)&timer);
+	k_mem_slab_free(&posix_timer_slab, (void *)timer);
 
 out:
 	return ret;
@@ -241,11 +245,8 @@ int timer_settime(timer_t timerid, int flags, const struct itimerspec *value,
 	struct timer_obj *timer = (struct timer_obj *) timerid;
 	uint32_t duration, current;
 
-	if (timer == NULL ||
-	    value->it_interval.tv_nsec < 0 ||
-	    value->it_interval.tv_nsec >= NSEC_PER_SEC ||
-	    value->it_value.tv_nsec < 0 ||
-	    value->it_value.tv_nsec >= NSEC_PER_SEC) {
+	if ((timer == NULL) || !timespec_is_valid(&value->it_interval) ||
+	    !timespec_is_valid(&value->it_value)) {
 		errno = EINVAL;
 		return -1;
 	}
@@ -266,12 +267,12 @@ int timer_settime(timer_t timerid, int flags, const struct itimerspec *value,
 	}
 
 	/* Calculate timer period */
-	timer->reload = _ts_to_ms(&value->it_interval);
+	timer->reload = ts_to_ms(&value->it_interval);
 	timer->interval.tv_sec = value->it_interval.tv_sec;
 	timer->interval.tv_nsec = value->it_interval.tv_nsec;
 
 	/* Calculate timer duration */
-	duration = _ts_to_ms(&(value->it_value));
+	duration = ts_to_ms(&(value->it_value));
 	if ((flags & TIMER_ABSTIME) != 0) {
 		current = k_timer_remaining_get(&timer->ztimer);
 
diff --git a/lib/posix/options/timespec_to_timeout.c b/lib/posix/options/timespec_to_timeout.c
index e72956e6e3e..068646c2064 100644
--- a/lib/posix/options/timespec_to_timeout.c
+++ b/lib/posix/options/timespec_to_timeout.c
@@ -4,28 +4,21 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/kernel.h>
-#include <ksched.h>
+#include "posix_clock.h"
+
+#include <limits.h>
+#include <stdint.h>
+
 #include <zephyr/posix/time.h>
+#include <zephyr/sys/util.h>
 
-int64_t timespec_to_timeoutms(const struct timespec *abstime)
+uint32_t timespec_to_timeoutms(clockid_t clock_id, const struct timespec *abstime)
 {
-	int64_t milli_secs, secs, nsecs;
 	struct timespec curtime;
 
-	/* FIXME: Zephyr does have CLOCK_REALTIME to get time.
-	 * As per POSIX standard time should be calculated wrt CLOCK_REALTIME.
-	 * Zephyr deviates from POSIX 1003.1 standard on this aspect.
-	 */
-	clock_gettime(CLOCK_MONOTONIC, &curtime);
-	secs = abstime->tv_sec - curtime.tv_sec;
-	nsecs = abstime->tv_nsec - curtime.tv_nsec;
-
-	if (secs < 0 || (secs == 0 && nsecs < NSEC_PER_MSEC)) {
-		milli_secs = 0;
-	} else {
-		milli_secs =  secs * MSEC_PER_SEC + nsecs / NSEC_PER_MSEC;
+	if (clock_gettime(clock_id, &curtime) < 0) {
+		return 0;
 	}
 
-	return milli_secs;
+	return CLAMP(tp_diff(abstime, &curtime) / NSEC_PER_MSEC, 0, UINT32_MAX);
 }
diff --git a/lib/smf/smf.c b/lib/smf/smf.c
index 2c050526a56..e511db240ec 100644
--- a/lib/smf/smf.c
+++ b/lib/smf/smf.c
@@ -148,8 +148,6 @@ static bool smf_execute_ancestor_run_actions(struct smf_ctx *ctx)
 
 	/* The child state either transitioned or handled it. Either way, stop propagating. */
 	if (internal->new_state || internal->handled) {
-		internal->new_state = false;
-		internal->handled = false;
 		return false;
 	}
 
@@ -173,9 +171,6 @@ static bool smf_execute_ancestor_run_actions(struct smf_ctx *ctx)
 		}
 	}
 
-	internal->new_state = false;
-	internal->handled = false;
-
 	/* All done executing the run actions */
 
 	return false;
@@ -209,10 +204,24 @@ static bool smf_execute_all_exit_actions(struct smf_ctx *const ctx, const struct
 }
 #endif /* CONFIG_SMF_ANCESTOR_SUPPORT */
 
-void smf_set_initial(struct smf_ctx *ctx, const struct smf_state *init_state)
+/**
+ * @brief Reset the internal state of the state machine back to default values.
+ * Should be called on entry to smf_set_initial() and smf_set_state().
+ *
+ * @param ctx State machine context.
+ */
+static void smf_clear_internal_state(struct smf_ctx *ctx)
 {
 	struct internal_ctx *const internal = (void *)&ctx->internal;
 
+	internal->is_exit = false;
+	internal->terminate = false;
+	internal->handled = false;
+	internal->new_state = false;
+}
+
+void smf_set_initial(struct smf_ctx *ctx, const struct smf_state *init_state)
+{
 #ifdef CONFIG_SMF_INITIAL_TRANSITION
 	/*
 	 * The final target will be the deepest leaf state that
@@ -223,15 +232,14 @@ void smf_set_initial(struct smf_ctx *ctx, const struct smf_state *init_state)
 	}
 #endif
 
-	internal->is_exit = false;
-	internal->terminate = false;
-	internal->handled = false;
-	internal->new_state = false;
+	smf_clear_internal_state(ctx);
 	ctx->current = init_state;
 	ctx->previous = NULL;
 	ctx->terminate_val = 0;
 
 #ifdef CONFIG_SMF_ANCESTOR_SUPPORT
+	struct internal_ctx *const internal = (void *)&ctx->internal;
+
 	ctx->executing = init_state;
 	const struct smf_state *topmost = get_last_of(init_state);
 
@@ -389,6 +397,11 @@ int32_t smf_run_state(struct smf_ctx *const ctx)
 		return ctx->terminate_val;
 	}
 
+	/* Executing a states run function could cause a transition, so clear the
+	 * internal state to ensure that the transition is handled correctly.
+	 */
+	smf_clear_internal_state(ctx);
+
 #ifdef CONFIG_SMF_ANCESTOR_SUPPORT
 	ctx->executing = ctx->current;
 #endif
diff --git a/lib/utils/CMakeLists.txt b/lib/utils/CMakeLists.txt
index e0e1673f445..7062d69303d 100644
--- a/lib/utils/CMakeLists.txt
+++ b/lib/utils/CMakeLists.txt
@@ -11,6 +11,7 @@ zephyr_sources(
   )
 
 zephyr_sources_ifdef(CONFIG_ONOFF onoff.c)
+
 zephyr_sources_ifdef(CONFIG_NOTIFY notify.c)
 
 zephyr_sources_ifdef(CONFIG_JSON_LIBRARY json.c)
@@ -21,6 +22,8 @@ zephyr_sources_ifdef(CONFIG_UTF8 utf8.c)
 
 zephyr_sources_ifdef(CONFIG_WINSTREAM winstream.c)
 
+zephyr_sources_ifdef(CONFIG_COBS cobs.c)
+
 zephyr_library_include_directories(
   ${ZEPHYR_BASE}/kernel/include
   ${ZEPHYR_BASE}/arch/${ARCH}/include
diff --git a/lib/utils/Kconfig b/lib/utils/Kconfig
index 340c0ac42c2..4db79272bba 100644
--- a/lib/utils/Kconfig
+++ b/lib/utils/Kconfig
@@ -9,12 +9,30 @@ config JSON_LIBRARY
 	  Build a minimal JSON parsing/encoding library. Used by sample
 	  applications such as the NATS client.
 
+config JSON_LIBRARY_FP_SUPPORT
+	bool "Floating point support in JSON library"
+	depends on JSON_LIBRARY
+	select CBPRINTF_FP_SUPPORT
+	select REQUIRES_FULL_LIBC
+	help
+	  Build the JSON library with support for floating point types.
+
+	  Requires a libc implementation with support for floating point
+	  functions: strtof(), strtod(), isnan() and isinf().
+
 config RING_BUFFER
 	bool "Ring buffers"
 	help
-	  Enable usage of ring buffers. This is similar to kernel FIFOs but ring
-	  buffers manage their own buffer memory and can store arbitrary data.
-	  For optimal performance, use buffer sizes that are a power of 2.
+	  Provide highly efficient ring buffer management for arbitrary data.
+	  Some facilities such as kernel pipes are built on top of this.
+	  May be used directly e.g. when the pipe overhead is unnecessary.
+
+config RING_BUFFER_LARGE
+	bool "Allow large ring buffer sizes"
+	depends on RING_BUFFER
+	help
+	  Increase maximum buffer size from 32KB to 2GB. When this is enabled,
+	  all struct ring_buf instances become 12 bytes bigger.
 
 config NOTIFY
 	bool "Asynchronous Notifications"
@@ -57,4 +75,10 @@ config UTF8
 	  Enable the utf8 API. The API implements functions to specifically
 	  handle UTF-8 encoded strings.
 
+config COBS
+	bool "Consistent overhead byte stuffing"
+	select NET_BUF
+	help
+	  Enable consistent overhead byte stuffing
+
 endmenu
diff --git a/lib/utils/cobs.c b/lib/utils/cobs.c
new file mode 100644
index 00000000000..d500eb2b86f
--- /dev/null
+++ b/lib/utils/cobs.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2024 Kelly Helmut Lord
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <stdint.h>
+#include <zephyr/data/cobs.h>
+
+int cobs_encode(struct net_buf *src, struct net_buf *dst, uint32_t flags)
+{
+	uint8_t delimiter = COBS_FLAG_CUSTOM_DELIMITER(flags);
+
+	/* Calculate required space for worst case */
+	size_t max_encoded_size = cobs_max_encoded_len(src->len, flags);
+
+	/* Check if destination has enough space */
+	if (net_buf_tailroom(dst) < max_encoded_size) {
+		return -ENOMEM;
+	}
+
+	uint8_t *code_ptr = net_buf_add(dst, 1);
+	uint8_t code = 1;
+
+	/* Process all input bytes */
+	uint8_t data = 0;
+
+	while (src->len > 0) {
+		data = net_buf_pull_u8(src);
+		if (data == delimiter) {
+			/* Delimiter found - write current code and start new block */
+			*code_ptr = code;
+			code_ptr = net_buf_add(dst, 1);
+			code = 1;
+		} else {
+			/* Add non-zero byte to output */
+			net_buf_add_u8(dst, data);
+			code++;
+
+			/* If we've reached maximum block size, start a new block */
+			if (code == 0xFF && (src->len - 1 >= 0)) {
+				*code_ptr = code;
+				code_ptr = net_buf_add(dst, 1);
+				code = 1;
+			}
+		}
+	}
+
+	*code_ptr = code;
+
+	if (flags & COBS_FLAG_TRAILING_DELIMITER) {
+		/* Add final delimiter */
+		net_buf_add_u8(dst, delimiter);
+	}
+
+	return 0;
+}
+
+int cobs_decode(struct net_buf *src, struct net_buf *dst, uint32_t flags)
+{
+	uint8_t delimiter = COBS_FLAG_CUSTOM_DELIMITER(flags);
+
+	if (flags & COBS_FLAG_TRAILING_DELIMITER) {
+		uint8_t end_delim = net_buf_remove_u8(src);
+
+		if (end_delim != delimiter) {
+			return -EINVAL;
+		}
+	}
+
+	while (src->len > 0) {
+		/* Pull the COBS offset byte */
+		uint8_t offset = net_buf_pull_u8(src);
+
+		if (offset == delimiter && !(flags & COBS_FLAG_TRAILING_DELIMITER)) {
+			return -EINVAL;
+		}
+
+		/* Verify we have enough data */
+		if (src->len < (offset - 1)) {
+			return -EINVAL;
+		}
+
+		/* Copy offset-1 bytes */
+		for (uint8_t i = 0; i < offset - 1; i++) {
+			uint8_t byte = net_buf_pull_u8(src);
+
+			if (byte == delimiter) {
+				return -EINVAL;
+			}
+			net_buf_add_u8(dst, byte);
+		}
+
+		/* If this wasn't a maximum offset and we have more data,
+		 * there was a delimiter here in the original data
+		 */
+		if (offset != 0xFF && src->len > 0) {
+			net_buf_add_u8(dst, delimiter);
+		}
+	}
+
+	return 0;
+}
diff --git a/lib/utils/json.c b/lib/utils/json.c
index 6aa5f27646e..43a3128ce7e 100644
--- a/lib/utils/json.c
+++ b/lib/utils/json.c
@@ -8,6 +8,7 @@
 #include <ctype.h>
 #include <errno.h>
 #include <limits.h>
+#include <math.h>
 #include <zephyr/sys/printk.h>
 #include <zephyr/sys/util.h>
 #include <stdbool.h>
@@ -201,7 +202,7 @@ static void *lexer_number(struct json_lexer *lex)
 	while (true) {
 		int chr = next(lex);
 
-		if (isdigit(chr) != 0 || chr == '.') {
+		if (isdigit(chr) != 0 || chr == '.' || chr == 'e' || chr == '+' || chr == '-') {
 			continue;
 		}
 
@@ -212,6 +213,37 @@ static void *lexer_number(struct json_lexer *lex)
 	}
 }
 
+static void *lexer_number_nan(struct json_lexer *lex)
+{
+#ifdef CONFIG_JSON_LIBRARY_FP_SUPPORT
+	backup(lex);
+
+	switch (peek(lex)) {
+	case 'N':
+		if (!accept_run(lex, "NaN")) {
+			emit(lex, JSON_TOK_NUMBER);
+			return lexer_json;
+		}
+		break;
+	case 'I':
+		if (!accept_run(lex, "Infinity")) {
+			emit(lex, JSON_TOK_NUMBER);
+			return lexer_json;
+		}
+		break;
+	case '-':
+		if (!accept_run(lex, "-Infinity")) {
+			emit(lex, JSON_TOK_NUMBER);
+			return lexer_json;
+		}
+		break;
+	}
+
+#endif
+	emit(lex, JSON_TOK_ERROR);
+	return NULL;
+}
+
 static void *lexer_json(struct json_lexer *lex)
 {
 	while (true) {
@@ -236,10 +268,16 @@ static void *lexer_json(struct json_lexer *lex)
 		case 't':
 		case 'f':
 			return lexer_boolean;
+		case 'N':
+		case 'I':
+			return lexer_number_nan;
 		case '-':
 			if (isdigit(peek(lex)) != 0) {
 				return lexer_number;
 			}
+			if (peek(lex) == 'I') {
+				return lexer_number_nan;
+			}
 
 			__fallthrough;
 		default:
@@ -307,10 +345,15 @@ static int element_token(enum json_tokens token)
 	case JSON_TOK_OBJECT_START:
 	case JSON_TOK_ARRAY_START:
 	case JSON_TOK_STRING:
+	case JSON_TOK_STRING_BUF:
 	case JSON_TOK_NUMBER:
+	case JSON_TOK_INT:
+	case JSON_TOK_UINT:
 	case JSON_TOK_INT64:
 	case JSON_TOK_UINT64:
 	case JSON_TOK_FLOAT:
+	case JSON_TOK_FLOAT_FP:
+	case JSON_TOK_DOUBLE_FP:
 	case JSON_TOK_OPAQUE:
 	case JSON_TOK_OBJ_ARRAY:
 	case JSON_TOK_TRUE:
@@ -419,7 +462,22 @@ static int skip_field(struct json_obj *obj, struct json_obj_key_value *kv)
 	return 0;
 }
 
-static int decode_num(const struct json_token *token, int32_t *num)
+static int decode_string_buf(const struct json_token *token, char *str, size_t size)
+{
+	size_t len = token->end - token->start;
+
+	/* buffer 'str' must be large enough to fit string and null-terminator */
+	if (size <= len) {
+		return -EINVAL;
+	}
+
+	memcpy(str, token->start, len);
+	str[len] = '\0';
+
+	return 0;
+}
+
+static int decode_int32(const struct json_token *token, int32_t *num)
 {
 	/* FIXME: strtod() is not available in newlib/minimal libc,
 	 * so using strtol() here.
@@ -446,6 +504,30 @@ static int decode_num(const struct json_token *token, int32_t *num)
 	return 0;
 }
 
+static int decode_uint32(const struct json_token *token, uint32_t *num)
+{
+	char *endptr;
+	char prev_end;
+
+	prev_end = *token->end;
+	*token->end = '\0';
+
+	errno = 0;
+	*num = strtoul(token->start, &endptr, 10);
+
+	*token->end = prev_end;
+
+	if (errno != 0) {
+		return -errno;
+	}
+
+	if (endptr != token->end) {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 static int decode_int64(const struct json_token *token, int64_t *num)
 {
 	char *endptr;
@@ -494,6 +576,204 @@ static int decode_uint64(const struct json_token *token, uint64_t *num)
 	return 0;
 }
 
+static int decode_float(const struct json_token *token, float *num)
+{
+#ifdef CONFIG_JSON_LIBRARY_FP_SUPPORT
+	char *endptr;
+	char prev_end;
+
+	prev_end = *token->end;
+	*token->end = '\0';
+
+	errno = 0;
+	*num = strtof(token->start, &endptr);
+
+	*token->end = prev_end;
+
+	if (errno != 0) {
+		return -errno;
+	}
+
+	if (endptr != token->end) {
+		return -EINVAL;
+	}
+
+	return 0;
+
+#else
+	ARG_UNUSED(token);
+	ARG_UNUSED(num);
+	return -EINVAL;
+#endif
+}
+
+static int decode_double(const struct json_token *token, double *num)
+{
+#ifdef CONFIG_JSON_LIBRARY_FP_SUPPORT
+	char *endptr;
+	char prev_end;
+
+	prev_end = *token->end;
+	*token->end = '\0';
+
+	errno = 0;
+	*num = strtod(token->start, &endptr);
+
+	*token->end = prev_end;
+
+	if (errno != 0) {
+		return -errno;
+	}
+
+	if (endptr != token->end) {
+		return -EINVAL;
+	}
+
+	return 0;
+
+#else
+	ARG_UNUSED(token);
+	ARG_UNUSED(num);
+	return -EINVAL;
+#endif
+}
+
+static int decode_int8(const struct json_token *token, int8_t *num)
+{
+	int32_t num_i32;
+	int res;
+
+	res = decode_int32(token, &num_i32);
+
+	if (res != 0) {
+		return res;
+	}
+
+	if (num_i32 < INT8_MIN || num_i32 > INT8_MAX) {
+		return -EINVAL;
+	}
+
+	*num = num_i32;
+
+	return 0;
+}
+
+static int decode_uint8(const struct json_token *token, uint8_t *num)
+{
+	uint32_t num_u32;
+	int res;
+
+	res = decode_uint32(token, &num_u32);
+
+	if (res != 0) {
+		return res;
+	}
+
+	if (num_u32 > UINT8_MAX) {
+		return -EINVAL;
+	}
+
+	*num = num_u32;
+
+	return 0;
+}
+
+static int decode_int16(const struct json_token *token, int16_t *num)
+{
+	int32_t num_i32;
+	int res;
+
+	res = decode_int32(token, &num_i32);
+
+	if (res != 0) {
+		return res;
+	}
+
+	if (num_i32 < INT16_MIN || num_i32 > INT16_MAX) {
+		return -EINVAL;
+	}
+
+	*num = num_i32;
+
+	return 0;
+}
+
+static int decode_uint16(const struct json_token *token, uint16_t *num)
+{
+	uint32_t num_u32;
+	int res;
+
+	res = decode_uint32(token, &num_u32);
+
+	if (res != 0) {
+		return res;
+	}
+
+	if (num_u32 > UINT16_MAX) {
+		return -EINVAL;
+	}
+
+	*num = num_u32;
+
+	return 0;
+}
+
+static int decode_int(const struct json_token *token, void *field, size_t size)
+{
+	switch (size) {
+	case 1: {
+		int8_t *num = field;
+
+		return decode_int8(token, num);
+	}
+	case 2: {
+		int16_t *num = field;
+
+		return decode_int16(token, num);
+	}
+	case 4: {
+		int32_t *num = field;
+
+		return decode_int32(token, num);
+	}
+	case 8: {
+		int64_t *num = field;
+
+		return decode_int64(token, num);
+	}
+	default:
+		return -EINVAL;
+	}
+}
+
+static int decode_uint(const struct json_token *token, void *field, size_t size)
+{
+	switch (size) {
+	case 1: {
+		uint8_t *num = field;
+
+		return decode_uint8(token, num);
+	}
+	case 2: {
+		uint16_t *num = field;
+
+		return decode_uint16(token, num);
+	}
+	case 4: {
+		uint32_t *num = field;
+
+		return decode_uint32(token, num);
+	}
+	case 8: {
+		uint64_t *num = field;
+
+		return decode_uint64(token, num);
+	}
+	default:
+		return -EINVAL;
+	}
+}
+
 static bool equivalent_types(enum json_tokens type1, enum json_tokens type2)
 {
 	if (type1 == JSON_TOK_TRUE || type1 == JSON_TOK_FALSE) {
@@ -504,6 +784,22 @@ static bool equivalent_types(enum json_tokens type1, enum json_tokens type2)
 		return true;
 	}
 
+	if (type1 == JSON_TOK_NUMBER && type2 == JSON_TOK_FLOAT_FP) {
+		return true;
+	}
+
+	if (type1 == JSON_TOK_NUMBER && type2 == JSON_TOK_DOUBLE_FP) {
+		return true;
+	}
+
+	if (type1 == JSON_TOK_NUMBER && type2 == JSON_TOK_INT) {
+		return true;
+	}
+
+	if (type1 == JSON_TOK_NUMBER && type2 == JSON_TOK_UINT) {
+		return true;
+	}
+
 	if (type1 == JSON_TOK_NUMBER && type2 == JSON_TOK_INT64) {
 		return true;
 	}
@@ -516,6 +812,10 @@ static bool equivalent_types(enum json_tokens type1, enum json_tokens type2)
 		return true;
 	}
 
+	if (type1 == JSON_TOK_STRING && type2 == JSON_TOK_STRING_BUF) {
+		return true;
+	}
+
 	if (type1 == JSON_TOK_ARRAY_START && type2 == JSON_TOK_OBJ_ARRAY) {
 		return true;
 	}
@@ -567,7 +867,13 @@ static int64_t decode_value(struct json_obj *obj,
 	case JSON_TOK_NUMBER: {
 		int32_t *num = field;
 
-		return decode_num(value, num);
+		return decode_int32(value, num);
+	}
+	case JSON_TOK_INT: {
+		return decode_int(value, field, descr->field.size);
+	}
+	case JSON_TOK_UINT: {
+		return decode_uint(value, field, descr->field.size);
 	}
 	case JSON_TOK_INT64: {
 		int64_t *num = field;
@@ -579,6 +885,16 @@ static int64_t decode_value(struct json_obj *obj,
 
 		return decode_uint64(value, num);
 	}
+	case JSON_TOK_FLOAT_FP: {
+		float *num = field;
+
+		return decode_float(value, num);
+	}
+	case JSON_TOK_DOUBLE_FP: {
+		double *num = field;
+
+		return decode_double(value, num);
+	}
 	case JSON_TOK_OPAQUE:
 	case JSON_TOK_FLOAT: {
 		struct json_obj_token *obj_token = field;
@@ -595,6 +911,11 @@ static int64_t decode_value(struct json_obj *obj,
 
 		return 0;
 	}
+	case JSON_TOK_STRING_BUF: {
+		char *str = field;
+
+		return decode_string_buf(value, str, descr->field.size);
+	}
 	default:
 		return -EINVAL;
 	}
@@ -609,12 +930,20 @@ static ptrdiff_t get_elem_size(const struct json_obj_descr *descr)
 		return sizeof(int64_t);
 	case JSON_TOK_UINT64:
 		return sizeof(uint64_t);
+	case JSON_TOK_FLOAT_FP:
+		return sizeof(float);
+	case JSON_TOK_DOUBLE_FP:
+		return sizeof(double);
 	case JSON_TOK_OPAQUE:
 	case JSON_TOK_FLOAT:
 	case JSON_TOK_OBJ_ARRAY:
 		return sizeof(struct json_obj_token);
 	case JSON_TOK_STRING:
 		return sizeof(char *);
+	case JSON_TOK_INT:
+	case JSON_TOK_UINT:
+	case JSON_TOK_STRING_BUF:
+		return descr->field.size;
 	case JSON_TOK_TRUE:
 	case JSON_TOK_FALSE:
 		return sizeof(bool);
@@ -635,13 +964,17 @@ static ptrdiff_t get_elem_size(const struct json_obj_descr *descr)
 		size_t i;
 
 		for (i = 0; i < descr->object.sub_descr_len; i++) {
-			total += get_elem_size(&descr->object.sub_descr[i]);
-
 			if (descr->object.sub_descr[i].align_shift > align_shift) {
 				align_shift = descr->object.sub_descr[i].align_shift;
 			}
 		}
 
+		i = descr->object.sub_descr_len;
+		if (i > 0) {
+			total = descr->object.sub_descr[i - 1].offset +
+				get_elem_size(&descr->object.sub_descr[i - 1]);
+		}
+
 		return ROUND_UP(total, 1 << align_shift);
 	}
 	default:
@@ -728,7 +1061,7 @@ static int arr_data_parse(struct json_obj *obj, struct json_obj_token *val)
 			} else if (*obj->lex.pos == JSON_TOK_STRING) {
 				string_state = true;
 			} else if (*obj->lex.pos == JSON_TOK_ARRAY_START) {
-				/* arrary in array update structure count */
+				/* array in array update structure count */
 				array_in_array++;
 			}
 		}
@@ -1019,7 +1352,7 @@ static int arr_encode(const struct json_obj_descr *elem_descr,
 	return append_bytes("]", 1, data);
 }
 
-static int str_encode(const char **str, json_append_bytes_t append_bytes,
+static int str_encode(const char *str, json_append_bytes_t append_bytes,
 		      void *data)
 {
 	int ret;
@@ -1029,7 +1362,7 @@ static int str_encode(const char **str, json_append_bytes_t append_bytes,
 		return ret;
 	}
 
-	ret = json_escape_internal(*str, append_bytes, data);
+	ret = json_escape_internal(str, append_bytes, data);
 	if (!ret) {
 		return append_bytes("\"", 1, data);
 	}
@@ -1037,8 +1370,8 @@ static int str_encode(const char **str, json_append_bytes_t append_bytes,
 	return ret;
 }
 
-static int num_encode(const int32_t *num, json_append_bytes_t append_bytes,
-		      void *data)
+static int int32_encode(const int32_t *num, json_append_bytes_t append_bytes,
+			void *data)
 {
 	char buf[3 * sizeof(int32_t)];
 	int ret;
@@ -1054,6 +1387,23 @@ static int num_encode(const int32_t *num, json_append_bytes_t append_bytes,
 	return append_bytes(buf, (size_t)ret, data);
 }
 
+static int uint32_encode(const uint32_t *num, json_append_bytes_t append_bytes,
+			 void *data)
+{
+	char buf[3 * sizeof(uint32_t)];
+	int ret;
+
+	ret = snprintk(buf, sizeof(buf), "%u", *num);
+	if (ret < 0) {
+		return ret;
+	}
+	if (ret >= (int)sizeof(buf)) {
+		return -ENOMEM;
+	}
+
+	return append_bytes(buf, (size_t)ret, data);
+}
+
 static int int64_encode(const int64_t *num, json_append_bytes_t append_bytes,
 			void *data)
 {
@@ -1088,6 +1438,131 @@ static int uint64_encode(const uint64_t *num, json_append_bytes_t append_bytes,
 	return append_bytes(buf, (size_t)ret, data);
 }
 
+static int print_double(char *str, size_t size, const char *fmt, double num)
+{
+#ifdef CONFIG_JSON_LIBRARY_FP_SUPPORT
+	if (isnan(num)) {
+		return snprintk(str, size, "NaN");
+	}
+
+	if (isinf(num)) {
+		if (num < 0) {
+			return snprintk(str, size, "-Infinity");
+		}
+		return snprintk(str, size, "Infinity");
+	}
+
+	return snprintk(str, size, fmt, num);
+
+#else
+	str[0] = '\0';
+	ARG_UNUSED(size);
+	ARG_UNUSED(fmt);
+	ARG_UNUSED(num);
+	return -EINVAL;
+#endif
+}
+
+static int float_encode(const float *num, json_append_bytes_t append_bytes, void *data)
+{
+	char buf[sizeof("-3.40282347e+38")];
+	int ret;
+
+	ret = print_double(buf, sizeof(buf), "%.9g", (double)*num);
+
+	if (ret < 0) {
+		return ret;
+	}
+	if (ret >= (int)sizeof(buf)) {
+		return -ENOMEM;
+	}
+
+	return append_bytes(buf, (size_t)ret, data);
+}
+
+static int double_encode(const double *num, json_append_bytes_t append_bytes, void *data)
+{
+	char buf[sizeof("-1.797693134862316e+308")];
+	int ret;
+
+	ret = print_double(buf, sizeof(buf), "%.16g", *num);
+
+	if (ret < 0) {
+		return ret;
+	}
+	if (ret >= (int)sizeof(buf)) {
+		return -ENOMEM;
+	}
+
+	return append_bytes(buf, (size_t)ret, data);
+}
+
+static int int_encode(const void *ptr, size_t size, json_append_bytes_t append_bytes,
+		      void *data)
+{
+	switch (size) {
+	case 1: {
+		const int8_t *num_8 = ptr;
+		int32_t num = *num_8;
+
+		return int32_encode(&num, append_bytes, data);
+	}
+	case 2: {
+		const int16_t *num_16 = ptr;
+		int32_t num = *num_16;
+
+		return int32_encode(&num, append_bytes, data);
+	}
+	case 4: {
+		const int32_t *num_32 = ptr;
+		int32_t num = *num_32;
+
+		return int32_encode(&num, append_bytes, data);
+	}
+	case 8: {
+		const int64_t *num_64 = ptr;
+		int64_t num = *num_64;
+
+		return int64_encode(&num, append_bytes, data);
+	}
+	default:
+		return -EINVAL;
+	}
+}
+
+static int uint_encode(const void *ptr, size_t size, json_append_bytes_t append_bytes,
+		       void *data)
+{
+	switch (size) {
+	case 1: {
+		const uint8_t *num_8 = ptr;
+		uint32_t num = *num_8;
+
+		return uint32_encode(&num, append_bytes, data);
+	}
+	case 2: {
+		const uint16_t *num_16 = ptr;
+		uint32_t num = *num_16;
+
+		return uint32_encode(&num, append_bytes, data);
+	}
+	case 4: {
+		const uint32_t *num_32 = ptr;
+		uint32_t num = *num_32;
+
+		return uint32_encode(&num, append_bytes, data);
+	}
+	case 8: {
+		const uint64_t *num_64 = ptr;
+		uint64_t num = *num_64;
+
+		return uint64_encode(&num, append_bytes, data);
+	}
+	default:
+		return -EINVAL;
+	}
+}
+
 static int float_ascii_encode(struct json_obj_token *num, json_append_bytes_t append_bytes,
 		      void *data)
 {
@@ -1139,7 +1614,12 @@ static int encode(const struct json_obj_descr *descr, const void *val,
 	case JSON_TOK_FALSE:
 	case JSON_TOK_TRUE:
 		return bool_encode(ptr, append_bytes, data);
-	case JSON_TOK_STRING:
+	case JSON_TOK_STRING: {
+		const char **str = ptr;
+
+		return str_encode(*str, append_bytes, data);
+	}
+	case JSON_TOK_STRING_BUF:
 		return str_encode(ptr, append_bytes, data);
 	case JSON_TOK_ARRAY_START:
 		return arr_encode(descr->array.element_descr, ptr,
@@ -1149,11 +1629,19 @@ static int encode(const struct json_obj_descr *descr, const void *val,
 				       descr->object.sub_descr_len,
 				       ptr, append_bytes, data);
 	case JSON_TOK_NUMBER:
-		return num_encode(ptr, append_bytes, data);
+		return int32_encode(ptr, append_bytes, data);
+	case JSON_TOK_INT:
+		return int_encode(ptr, descr->field.size, append_bytes, data);
+	case JSON_TOK_UINT:
+		return uint_encode(ptr, descr->field.size, append_bytes, data);
 	case JSON_TOK_INT64:
 		return int64_encode(ptr, append_bytes, data);
 	case JSON_TOK_UINT64:
 		return uint64_encode(ptr, append_bytes, data);
+	case JSON_TOK_FLOAT_FP:
+		return float_encode(ptr, append_bytes, data);
+	case JSON_TOK_DOUBLE_FP:
+		return double_encode(ptr, append_bytes, data);
 	case JSON_TOK_FLOAT:
 		return float_ascii_encode(ptr, append_bytes, data);
 	case JSON_TOK_OPAQUE:
@@ -1178,8 +1666,7 @@ int json_obj_encode(const struct json_obj_descr *descr, size_t descr_len,
 	}
 
 	for (i = 0; i < descr_len; i++) {
-		ret = str_encode((const char **)&descr[i].field_name,
-				 append_bytes, data);
+		ret = str_encode(descr[i].field_name, append_bytes, data);
 		if (ret < 0) {
 			return ret;
 		}
diff --git a/lib/utils/ring_buffer.c b/lib/utils/ring_buffer.c
index 39e6e257e92..652b53b758f 100644
--- a/lib/utils/ring_buffer.c
+++ b/lib/utils/ring_buffer.c
@@ -9,46 +9,42 @@
 #include <zephyr/sys/ring_buffer.h>
 #include <string.h>
 
-uint32_t ring_buf_put_claim(struct ring_buf *buf, uint8_t **data, uint32_t size)
+uint32_t ring_buf_area_claim(struct ring_buf *buf, struct ring_buf_index *ring,
+			     uint8_t **data, uint32_t size)
 {
-	uint32_t free_space, wrap_size;
-	int32_t base;
-
-	base = buf->put_base;
-	wrap_size = buf->put_head - base;
-	if (unlikely(wrap_size >= buf->size)) {
-		/* put_base is not yet adjusted */
-		wrap_size -= buf->size;
-		base += buf->size;
-	}
-	wrap_size = buf->size - wrap_size;
+	ring_buf_idx_t head_offset, wrap_size;
 
-	free_space = ring_buf_space_get(buf);
-	size = MIN(size, free_space);
+	head_offset = ring->head - ring->base;
+	if (unlikely(head_offset >= buf->size)) {
+		/* ring->base is not yet adjusted */
+		head_offset -= buf->size;
+	}
+	wrap_size = buf->size - head_offset;
 	size = MIN(size, wrap_size);
 
-	*data = &buf->buffer[buf->put_head - base];
-	buf->put_head += size;
+	*data = &buf->buffer[head_offset];
+	ring->head += size;
 
 	return size;
 }
 
-int ring_buf_put_finish(struct ring_buf *buf, uint32_t size)
+int ring_buf_area_finish(struct ring_buf *buf, struct ring_buf_index *ring,
+			 uint32_t size)
 {
-	uint32_t finish_space, wrap_size;
+	ring_buf_idx_t claimed_size, tail_offset;
 
-	finish_space = buf->put_head - buf->put_tail;
-	if (unlikely(size > finish_space)) {
+	claimed_size = ring->head - ring->tail;
+	if (unlikely(size > claimed_size)) {
 		return -EINVAL;
 	}
 
-	buf->put_tail += size;
-	buf->put_head = buf->put_tail;
+	ring->tail += size;
+	ring->head = ring->tail;
 
-	wrap_size = buf->put_tail - buf->put_base;
-	if (unlikely(wrap_size >= buf->size)) {
-		/* we wrapped: adjust put_base */
-		buf->put_base += buf->size;
+	tail_offset = ring->tail - ring->base;
+	if (unlikely(tail_offset >= buf->size)) {
+		/* we wrapped: adjust ring->base */
+		ring->base += buf->size;
 	}
 
 	return 0;
@@ -63,11 +59,14 @@ uint32_t ring_buf_put(struct ring_buf *buf, const uint8_t *data, uint32_t size)
 
 	do {
 		partial_size = ring_buf_put_claim(buf, &dst, size);
+		if (partial_size == 0) {
+			break;
+		}
 		memcpy(dst, data, partial_size);
 		total_size += partial_size;
 		size -= partial_size;
 		data += partial_size;
-	} while (size && partial_size);
+	} while (size != 0);
 
 	err = ring_buf_put_finish(buf, total_size);
 	__ASSERT_NO_MSG(err == 0);
@@ -76,51 +75,6 @@ uint32_t ring_buf_put(struct ring_buf *buf, const uint8_t *data, uint32_t size)
 	return total_size;
 }
 
-uint32_t ring_buf_get_claim(struct ring_buf *buf, uint8_t **data, uint32_t size)
-{
-	uint32_t available_size, wrap_size;
-	int32_t base;
-
-	base = buf->get_base;
-	wrap_size = buf->get_head - base;
-	if (unlikely(wrap_size >= buf->size)) {
-		/* get_base is not yet adjusted */
-		wrap_size -= buf->size;
-		base += buf->size;
-	}
-	wrap_size = buf->size - wrap_size;
-
-	available_size = ring_buf_size_get(buf);
-	size = MIN(size, available_size);
-	size = MIN(size, wrap_size);
-
-	*data = &buf->buffer[buf->get_head - base];
-	buf->get_head += size;
-
-	return size;
-}
-
-int ring_buf_get_finish(struct ring_buf *buf, uint32_t size)
-{
-	uint32_t finish_space, wrap_size;
-
-	finish_space = buf->get_head - buf->get_tail;
-	if (unlikely(size > finish_space)) {
-		return -EINVAL;
-	}
-
-	buf->get_tail += size;
-	buf->get_head = buf->get_tail;
-
-	wrap_size = buf->get_tail - buf->get_base;
-	if (unlikely(wrap_size >= buf->size)) {
-		/* we wrapped: adjust get_base */
-		buf->get_base += buf->size;
-	}
-
-	return 0;
-}
-
 uint32_t ring_buf_get(struct ring_buf *buf, uint8_t *data, uint32_t size)
 {
 	uint8_t *src;
@@ -130,13 +84,16 @@ uint32_t ring_buf_get(struct ring_buf *buf, uint8_t *data, uint32_t size)
 
 	do {
 		partial_size = ring_buf_get_claim(buf, &src, size);
+		if (partial_size == 0) {
+			break;
+		}
 		if (data) {
 			memcpy(data, src, partial_size);
 			data += partial_size;
 		}
 		total_size += partial_size;
 		size -= partial_size;
-	} while (size && partial_size);
+	} while (size != 0);
 
 	err = ring_buf_get_finish(buf, total_size);
 	__ASSERT_NO_MSG(err == 0);
@@ -152,16 +109,17 @@ uint32_t ring_buf_peek(struct ring_buf *buf, uint8_t *data, uint32_t size)
 	uint32_t total_size = 0U;
 	int err;
 
-	size = MIN(size, ring_buf_size_get(buf));
-
 	do {
 		partial_size = ring_buf_get_claim(buf, &src, size);
+		if (partial_size == 0) {
+			break;
+		}
 		__ASSERT_NO_MSG(data != NULL);
 		memcpy(data, src, partial_size);
 		data += partial_size;
 		total_size += partial_size;
 		size -= partial_size;
-	} while (size && partial_size);
+	} while (size != 0);
 
 	/* effectively unclaim total_size bytes */
 	err = ring_buf_get_finish(buf, 0);
@@ -208,11 +166,14 @@ int ring_buf_item_put(struct ring_buf *buf, uint16_t type, uint8_t value,
 
 	do {
 		partial_size = ring_buf_put_claim(buf, &dst, size);
+		if (partial_size == 0) {
+			break;
+		}
 		memcpy(dst, data, partial_size);
 		size -= partial_size;
 		total_size += partial_size;
 		data += partial_size;
-	} while (size && partial_size);
+	} while (size != 0);
 	__ASSERT_NO_MSG(size == 0);
 
 	err = ring_buf_put_finish(buf, total_size);
@@ -254,13 +215,16 @@ int ring_buf_item_get(struct ring_buf *buf, uint16_t *type, uint8_t *value,
 
 	do {
 		partial_size = ring_buf_get_claim(buf, &src, size);
+		if (partial_size == 0) {
+			break;
+		}
 		if (data) {
 			memcpy(data, src, partial_size);
 			data += partial_size;
 		}
 		total_size += partial_size;
 		size -= partial_size;
-	} while (size && partial_size);
+	} while (size != 0);
 
 	err = ring_buf_get_finish(buf, total_size);
 	__ASSERT_NO_MSG(err == 0);
diff --git a/lib/uuid/CMakeLists.txt b/lib/uuid/CMakeLists.txt
new file mode 100644
index 00000000000..fa0b91ac5c5
--- /dev/null
+++ b/lib/uuid/CMakeLists.txt
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources_ifdef(CONFIG_UUID uuid.c)
+
+zephyr_library_link_libraries_ifdef(CONFIG_UUID_V5 mbedTLS)
diff --git a/lib/uuid/Kconfig b/lib/uuid/Kconfig
new file mode 100644
index 00000000000..8ee2a9a9cc3
--- /dev/null
+++ b/lib/uuid/Kconfig
@@ -0,0 +1,40 @@
+# Copyright (c) 2025, SECO Mind Srl
+#
+# SPDX-License-Identifier: Apache-2.0
+
+menu "Universally Unique Identifier (UUID)"
+
+config UUID
+	bool "UUID support [EXPERIMENTAL]"
+	select EXPERIMENTAL
+	help
+	  Enable use of the UUID library.
+
+config UUID_V4
+	bool "UUID version 4 generation support [EXPERIMENTAL]"
+	select EXPERIMENTAL
+	depends on UUID
+	depends on ENTROPY_GENERATOR
+	help
+	  Enable generation of UUID v4.
+
+config UUID_V5
+	bool "UUID version 5 generation support [EXPERIMENTAL]"
+	select EXPERIMENTAL
+	depends on UUID
+	depends on MBEDTLS
+	depends on MBEDTLS_MD
+	depends on MBEDTLS_SHA1
+	help
+	  Enable generation of UUID v5.
+
+config UUID_BASE64
+	bool "UUID Base64 support [EXPERIMENTAL]"
+	select EXPERIMENTAL
+	depends on UUID
+	depends on BASE64
+	help
+	  Enable conversion functions to write UUIDs in base 64
+	  formats.
+
+endmenu
diff --git a/lib/uuid/uuid.c b/lib/uuid/uuid.c
new file mode 100644
index 00000000000..58bb790fbc6
--- /dev/null
+++ b/lib/uuid/uuid.c
@@ -0,0 +1,267 @@
+/*
+ * Copyright (c) 2025, SECO Mind Srl
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/sys/uuid.h>
+
+#include <ctype.h>
+#include <string.h>
+#include <stdio.h>
+
+#if defined(CONFIG_UUID_V4)
+#include <zephyr/random/random.h>
+#endif
+
+#if defined(CONFIG_UUID_V5)
+#include <mbedtls/md.h>
+#endif
+
+#if defined(CONFIG_UUID_BASE64)
+#include <zephyr/sys/base64.h>
+#endif
+
+#define UUID_STR_POSITION_FIRST_HYPHEN  (8U)
+#define UUID_STR_POSITION_SECOND_HYPHEN (13U)
+#define UUID_STR_POSITION_THIRD_HYPHEN  (18U)
+#define UUID_STR_POSITION_FOURTH_HYPHEN (23U)
+
+#define UUID_POSITION_VERSION (6U)
+#define UUID_OFFSET_VERSION   (4U)
+#define UUID_MASK_VERSION     (0xF0U)
+#define UUID_POSITION_VARIANT (8U)
+#define UUID_OFFSET_VARIANT   (6U)
+#define UUID_MASK_VARIANT     (0xC0)
+
+#define UUID_V4_VERSION (4U)
+#define UUID_V4_VARIANT (2U)
+#define UUID_V5_VERSION (5U)
+#define UUID_V5_VARIANT (2U)
+
+#if defined(CONFIG_UUID_V4) || defined(CONFIG_UUID_V5)
+static void overwrite_uuid_version_and_variant(uint8_t version, uint8_t variant, struct uuid *out)
+{
+	/* Clear the 'ver' and 'var' fields */
+	out->val[UUID_POSITION_VERSION] &= ~UUID_MASK_VERSION;
+	out->val[UUID_POSITION_VARIANT] &= ~UUID_MASK_VARIANT;
+	/* Update the 'ver' and 'var' fields */
+	out->val[UUID_POSITION_VERSION] |= (uint8_t)(version << UUID_OFFSET_VERSION);
+	out->val[UUID_POSITION_VARIANT] |= (uint8_t)(variant << UUID_OFFSET_VARIANT);
+}
+#endif
+
+static bool should_be_hyphen(unsigned int position)
+{
+	switch (position) {
+	case UUID_STR_POSITION_FIRST_HYPHEN:
+	case UUID_STR_POSITION_SECOND_HYPHEN:
+	case UUID_STR_POSITION_THIRD_HYPHEN:
+	case UUID_STR_POSITION_FOURTH_HYPHEN:
+		return true;
+	default:
+		return false;
+	}
+}
+
+#if defined(CONFIG_UUID_V4)
+int uuid_generate_v4(struct uuid *out)
+{
+	if (out == NULL) {
+		return -EINVAL;
+	}
+	/* Fill the whole UUID struct with a random number */
+	sys_rand_get(out->val, UUID_SIZE);
+	/* Update version and variant */
+	overwrite_uuid_version_and_variant(UUID_V4_VERSION, UUID_V4_VARIANT, out);
+	return 0;
+}
+#endif
+
+#if defined(CONFIG_UUID_V5)
+int uuid_generate_v5(const struct uuid *namespace, const void *data, size_t data_size,
+		     struct uuid *out)
+{
+	if (out == NULL) {
+		return -EINVAL;
+	}
+	int ret = 0;
+	int mbedtls_err = 0;
+	mbedtls_md_context_t ctx = {0};
+	const mbedtls_md_info_t *md_info = mbedtls_md_info_from_type(MBEDTLS_MD_SHA1);
+	const size_t sha_1_bytes = 20;
+	uint8_t sha_result[sha_1_bytes];
+
+	mbedtls_md_init(&ctx);
+	mbedtls_err = mbedtls_md_setup(&ctx, md_info, 0);
+	/* Might return: MBEDTLS_ERR_MD_BAD_INPUT_DATA or MBEDTLS_ERR_MD_ALLOC_FAILED */
+	switch (mbedtls_err) {
+	case 0:
+		break;
+	case MBEDTLS_ERR_MD_BAD_INPUT_DATA:
+		ret = -EINVAL;
+		goto exit;
+	case MBEDTLS_ERR_MD_ALLOC_FAILED:
+		ret = -ENOMEM;
+		goto exit;
+	default:
+		ret = -ENOTSUP;
+		goto exit;
+	}
+	mbedtls_err = mbedtls_md_starts(&ctx);
+	if (mbedtls_err != 0) {
+		/* Might return MBEDTLS_ERR_MD_BAD_INPUT_DATA */
+		ret = -EINVAL;
+		goto exit;
+	}
+	mbedtls_err = mbedtls_md_update(&ctx, namespace->val, UUID_SIZE);
+	if (mbedtls_err != 0) {
+		/* Might return MBEDTLS_ERR_MD_BAD_INPUT_DATA */
+		ret = -EINVAL;
+		goto exit;
+	}
+	mbedtls_err = mbedtls_md_update(&ctx, data, data_size);
+	if (mbedtls_err != 0) {
+		/* Might return MBEDTLS_ERR_MD_BAD_INPUT_DATA */
+		ret = -EINVAL;
+		goto exit;
+	}
+	mbedtls_err = mbedtls_md_finish(&ctx, sha_result);
+	if (mbedtls_err != 0) {
+		/* Might return MBEDTLS_ERR_MD_BAD_INPUT_DATA */
+		ret = -EINVAL;
+		goto exit;
+	}
+
+	/* Store the computed SHA1 in the out struct */
+	for (unsigned int i = 0; i < UUID_SIZE; i++) {
+		out->val[i] = sha_result[i];
+	}
+	/* Update version and variant */
+	overwrite_uuid_version_and_variant(UUID_V5_VERSION, UUID_V5_VARIANT, out);
+
+exit:
+	mbedtls_md_free(&ctx);
+	return ret;
+}
+#endif
+
+int uuid_copy(const struct uuid *data, struct uuid *out)
+{
+	if (out == NULL) {
+		return -EINVAL;
+	}
+	memcpy(out->val, data->val, UUID_SIZE);
+	return 0;
+}
+
+int uuid_from_buffer(const uint8_t data[UUID_SIZE], struct uuid *out)
+{
+	if ((data == NULL) || (out == NULL)) {
+		return -EINVAL;
+	}
+	memcpy(out->val, data, UUID_SIZE);
+	return 0;
+}
+
+int uuid_from_string(const char data[UUID_STR_LEN], struct uuid *out)
+{
+	if ((data == NULL) || (strlen(data) + 1 != UUID_STR_LEN) || (out == NULL)) {
+		return -EINVAL;
+	}
+	for (unsigned int i = 0; i < UUID_STR_LEN - 1; i++) {
+		char char_i = data[i];
+		/* Check that hyphens are in the right place */
+		if (should_be_hyphen(i)) {
+			if (char_i != '-') {
+				return -EINVAL;
+			}
+			continue;
+		}
+		/* Check if the given input is hexadecimal */
+		if (!isxdigit(char_i)) {
+			return -EINVAL;
+		}
+	}
+
+	/* Content parsing */
+	unsigned int data_idx = 0U;
+	unsigned int out_idx = 0U;
+
+	while (data_idx < UUID_STR_LEN - 1) {
+		if (should_be_hyphen(data_idx)) {
+			data_idx += 1;
+			continue;
+		}
+
+		size_t hex2bin_rc =
+			hex2bin(&data[data_idx], 2, &out->val[out_idx], UUID_SIZE - out_idx);
+		if (hex2bin_rc != 1) {
+			return -EINVAL;
+		}
+		out_idx++;
+		data_idx += 2;
+	}
+	return 0;
+}
+
+int uuid_to_buffer(const struct uuid *data, uint8_t out[UUID_SIZE])
+{
+	if (out == NULL) {
+		return -EINVAL;
+	}
+	memcpy(out, data->val, UUID_SIZE);
+	return 0;
+}
+
+int uuid_to_string(const struct uuid *data, char out[UUID_STR_LEN])
+{
+	if (out == NULL) {
+		return -EINVAL;
+	}
+	snprintf(out, UUID_STR_LEN,
+		 "%02x%02x%02x%02x-%02x%02x-%02x%02x-%02x%02x-%02x%02x%02x%02x%02x%02x",
+		 data->val[0], data->val[1], data->val[2], data->val[3], data->val[4], data->val[5],
+		 data->val[6], data->val[7], data->val[8], data->val[9], data->val[10],
+		 data->val[11], data->val[12], data->val[13], data->val[14], data->val[15]);
+	return 0;
+}
+
+#if defined(CONFIG_UUID_BASE64)
+int uuid_to_base64(const struct uuid *data, char out[UUID_BASE64_LEN])
+{
+	if (out == NULL) {
+		return -EINVAL;
+	}
+
+	size_t olen = 0;
+
+	base64_encode(out, UUID_BASE64_LEN, &olen, data->val, UUID_SIZE);
+	return 0;
+}
+
+int uuid_to_base64url(const struct uuid *data, char out[UUID_BASE64URL_LEN])
+{
+	if (out == NULL) {
+		return -EINVAL;
+	}
+
+	/* Convert UUID to RFC 3548/4648 base 64 notation */
+	size_t olen = 0;
+	char uuid_base64[UUID_BASE64_LEN] = {0};
+
+	base64_encode(uuid_base64, UUID_BASE64_LEN, &olen, data->val, UUID_SIZE);
+	/* Convert UUID to RFC 4648 sec. 5 URL and filename safe base 64 notation */
+	for (unsigned int i = 0; i < UUID_BASE64URL_LEN - 1; i++) {
+		if (uuid_base64[i] == '+') {
+			uuid_base64[i] = '-';
+		}
+		if (uuid_base64[i] == '/') {
+			uuid_base64[i] = '_';
+		}
+	}
+	memcpy(out, uuid_base64, UUID_BASE64URL_LEN - 1);
+	out[UUID_BASE64URL_LEN - 1] = 0;
+	return 0;
+}
+#endif
diff --git a/misc/generated/configs.c.in b/misc/generated/configs.c.in
index 886636f2ad0..9de41052d39 100644
--- a/misc/generated/configs.c.in
+++ b/misc/generated/configs.c.in
@@ -1,7 +1,3 @@
-/*
- * SPDX-License-Identifier: Apache-2.0
- */
-
 /* file is auto-generated, do not modify ! */
 
 #include <zephyr/toolchain.h>
diff --git a/modules/Kconfig b/modules/Kconfig
index a8cf861a680..3b7f9dcb4ba 100644
--- a/modules/Kconfig
+++ b/modules/Kconfig
@@ -26,16 +26,13 @@ source "modules/Kconfig.chre"
 source "modules/Kconfig.cypress"
 source "modules/Kconfig.eos_s3"
 source "modules/Kconfig.esp32"
-source "modules/Kconfig.imx"
 source "modules/Kconfig.infineon"
 source "modules/Kconfig.libmetal"
 source "modules/lvgl/Kconfig"
-source "modules/Kconfig.mcux"
 source "modules/Kconfig.microchip"
 source "modules/Kconfig.nuvoton"
 source "modules/Kconfig.open-amp"
 source "modules/Kconfig.picolibc"
-source "modules/Kconfig.nxp_s32"
 source "modules/Kconfig.renesas_fsp"
 source "modules/Kconfig.rust"
 source "modules/Kconfig.simplelink"
@@ -66,12 +63,18 @@ comment "Unavailable modules, please install those via the project manifest."
 # config ZEPHYR_<MODULE_NAME_UPPER>_MODULE
 # 	bool
 
+comment "hal_bouffalolab module not available."
+	depends on !ZEPHYR_HAL_BOUFFALOLAB_MODULE
+
 comment "hal_gigadevice module not available."
 	depends on !ZEPHYR_HAL_GIGADEVICE_MODULE
 
 comment "hal_nordic module not available."
 	depends on !ZEPHYR_HAL_NORDIC_MODULE
 
+comment "hal_nxp module not available."
+	depends on !ZEPHYR_HAL_NXP_MODULE
+
 comment "liblc3 module not available."
 	depends on !ZEPHYR_LIBLC3_MODULE
 
diff --git a/modules/Kconfig.mcuboot b/modules/Kconfig.mcuboot
index 0e84cca48f2..c7afb9a0123 100644
--- a/modules/Kconfig.mcuboot
+++ b/modules/Kconfig.mcuboot
@@ -12,7 +12,7 @@ config MCUBOOT
 
 config BOOTLOADER_MCUBOOT
 	bool "MCUboot bootloader support"
-	select USE_DT_CODE_PARTITION
+	select USE_DT_CODE_PARTITION if !MCUBOOT_BOOTLOADER_MODE_RAM_LOAD
 	imply INIT_ARCH_HW_AT_BOOT if ARCH_SUPPORTS_ARCH_HW_INIT
 	depends on !MCUBOOT
 	help
@@ -134,7 +134,7 @@ menu "On board MCUboot operation mode"
 
 choice MCUBOOT_BOOTLOADER_MODE
 	prompt "Application assumed MCUboot mode of operation"
-	default MCUBOOT_BOOTLOADER_MODE_SWAP_WITHOUT_SCRATCH # MCUBOOT_BOOTLOADER_MODE
+	default MCUBOOT_BOOTLOADER_MODE_SWAP_USING_MOVE
 	help
 	  Informs application build on assumed MCUboot mode of operation.
 	  This is important for validataing application against DT configuration,
@@ -149,8 +149,17 @@ config MCUBOOT_BOOTLOADER_MODE_SINGLE_APP
 	  to DFU its own update to secondary slot and all updates need to
 	  be performed using MCUboot serial recovery.
 
-config MCUBOOT_BOOTLOADER_MODE_SWAP_WITHOUT_SCRATCH
-	bool "MCUboot has been configured for swap without scratch operation"
+config MCUBOOT_BOOTLOADER_MODE_SWAP_USING_OFFSET
+	bool "MCUboot has been configured for swap using offset operation"
+	select MCUBOOT_BOOTLOADER_MODE_HAS_NO_DOWNGRADE
+	help
+	  MCUboot expects slot0_partition and slot1_partition to be present
+	  in DT and application will boot from slot0_partition.
+	  MCUBOOT_BOOTLOADER_NO_DOWNGRADE should also be selected
+	  if MCUboot has been built with MCUBOOT_DOWNGRADE_PREVENTION.
+
+config MCUBOOT_BOOTLOADER_MODE_SWAP_USING_MOVE
+	bool "MCUboot has been configured for swap using move operation"
 	select MCUBOOT_BOOTLOADER_MODE_HAS_NO_DOWNGRADE
 	help
 	  MCUboot expects slot0_partition and slot1_partition to be present
@@ -158,6 +167,13 @@ config MCUBOOT_BOOTLOADER_MODE_SWAP_WITHOUT_SCRATCH
 	  MCUBOOT_BOOTLOADER_NO_DOWNGRADE should also be selected
 	  if MCUboot has been built with MCUBOOT_DOWNGRADE_PREVENTION.
 
+config MCUBOOT_BOOTLOADER_MODE_SWAP_WITHOUT_SCRATCH
+	bool "MCUboot has been configured for swap without scratch operation [DEPRECATED]"
+	select DEPRECATED
+	select MCUBOOT_BOOTLOADER_MODE_HAS_NO_DOWNGRADE
+	help
+	  This Kconfig is deprecated, use MCUBOOT_BOOTLOADER_MODE_SWAP_USING_MOVE instead.
+
 config MCUBOOT_BOOTLOADER_MODE_SWAP_SCRATCH
 	bool "MCUboot has been configured for swap using scratch operation"
 	select MCUBOOT_BOOTLOADER_MODE_HAS_NO_DOWNGRADE
@@ -238,6 +254,21 @@ config MCUBOOT_BOOTLOADER_MODE_FIRMWARE_UPDATER
 	  a dedicated firmware updater application used to update the slot0_partition
 	  application.
 
+config MCUBOOT_BOOTLOADER_MODE_SINGLE_APP_RAM_LOAD
+	bool "MCUboot has been configured in single app RAM load mode"
+	select MCUBOOT_BOOTLOADER_MODE_HAS_NO_DOWNGRADE
+	select MCUBOOT_BOOTLOADER_NO_DOWNGRADE
+	help
+	  MCUboot can load the image to RAM from an arbitrary location. In this mode,
+	  MCUboot will copy the image to RAM and begin execution from there. The image
+	  must be linked to execute from RAM, the address that it is copied to is
+	  specified using the load-addr argument when running imgtool.
+	  Note that while not used directly, a slot0_partition must be defined in the
+	  DT, as it is used to get information about size of the image to be loaded.
+	  This option automatically selects MCUBOOT_BOOTLOADER_NO_DOWNGRADE as it is
+	  not possible to swap back to older version of the application. In fact, none
+	  of the swap operations are supported in this mode.
+
 endchoice # MCUBOOT_BOOTLOADER_MODE
 
 config MCUBOOT_BOOTLOADER_MODE_HAS_NO_DOWNGRADE
diff --git a/modules/Kconfig.renesas_fsp b/modules/Kconfig.renesas_fsp
index 62221025388..01fd54cb081 100644
--- a/modules/Kconfig.renesas_fsp
+++ b/modules/Kconfig.renesas_fsp
@@ -1,6 +1,6 @@
 # Renesas FSP HAL config
 
-# Copyright (c) 2024 Renesas Electronics Corporation
+# Copyright (c) 2024-2025 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 config HAS_RENESAS_RA_FSP
@@ -35,6 +35,11 @@ config USE_RA_FSP_I2C_IIC
 	help
 	  Enable Renesas RA I2C IIC Master driver
 
+config USE_RA_FSP_SCI_B_I2C
+	bool
+	help
+	  Enable RA FSP SCI-B I2C driver
+
 config USE_RA_FSP_SCI_UART
 	bool
 	help
@@ -59,6 +64,13 @@ config HAS_RENESAS_RA_RSIP_E51A
 	help
 	  Includes RSIP-E51A implementation for SCE driver
 
+config HAS_RENESAS_RA_SCE9
+	bool
+	default y
+	depends on DT_HAS_RENESAS_RA_SCE9_RNG_ENABLED
+	help
+	  Includes SCE9 implementation for SCE driver
+
 config HAS_RENESAS_RA_SCE7
 	bool
 	default y
@@ -142,10 +154,42 @@ config USE_RA_FSP_SDHI
 	help
 	  Enable RA FSP SDHI driver
 
+config USE_RA_FSP_DAC
+	bool
+	help
+	  Enable RA FSP DAC driver
+
+config USE_RA_FSP_ACMPHS
+	bool
+	help
+	  Enable RA FSP ACMPHS driver
+
+config USE_RA_FSP_WDT
+	bool
+	help
+	  Enable RA FSP WDT driver
+
+config USE_RA_FSP_ULPT
+	bool
+	help
+	  Enable RA FSP ULPT driver
+
+config USE_RA_FSP_LPM
+	bool
+	default y
+	depends on PM
+	help
+	  Enable RA FSP LPM driver
+
 endif # HAS_RENESAS_RA_FSP
 
 if HAS_RENESAS_RZ_FSP
 
+config USE_RZ_FSP_ADC
+	bool
+	help
+	  Enable RZ FSP ADC driver
+
 config USE_RZ_FSP_IOPORT
 	bool
 	help
@@ -156,4 +200,44 @@ config USE_RZ_FSP_SCIF_UART
 	help
 	  Enable RZ FSP SCIF UART driver
 
+config USE_RZ_FSP_RIIC_MASTER
+	bool
+	help
+	  Enable RZ FSP RIIC MASTER driver
+
+config USE_RZ_FSP_GTM
+	bool
+	help
+	  Enable RZ FSP GTM driver
+
+config USE_RZ_FSP_GPT
+	bool
+	help
+	  Enable RZ FSP GPT driver
+
+config USE_RZ_FSP_EXT_IRQ
+	bool
+	help
+	  Enable RZ FSP External IRQ driver
+
+config USE_RZ_FSP_DMA
+	bool
+	help
+	  Enable RZ FSP DMA driver
+
+config USE_RZ_FSP_MHU
+	bool
+	help
+	  Enable RZ FSP MHU driver
+
+config USE_RZ_FSP_CPG
+	bool
+	help
+	  Enable RZ FSP CLOCK CONTROL driver
+
+config USE_RZ_FSP_SCI_UART
+	bool
+	help
+	  Enable RZ FSP SCI UART driver
+
 endif
diff --git a/modules/Kconfig.simplelink b/modules/Kconfig.simplelink
index 13b26b1ca1a..3a1cea8ebb3 100644
--- a/modules/Kconfig.simplelink
+++ b/modules/Kconfig.simplelink
@@ -32,3 +32,8 @@ config HAS_CC13X2_CC26X2_SDK
 
 config HAS_CC13X2X7_CC26X2X7_SDK
 	bool
+
+# CC23X0 SDK HAL configuration
+
+config HAS_CC23X0_SDK
+	bool
diff --git a/modules/Kconfig.stm32 b/modules/Kconfig.stm32
index c586a51fcf7..c7d4437fd13 100644
--- a/modules/Kconfig.stm32
+++ b/modules/Kconfig.stm32
@@ -30,6 +30,16 @@ config USE_STM32_HAL_ADC_EX
 	  Enable STM32Cube Extended Analog-to-Digital Converter (ADC) HAL
 	  module driver
 
+config USE_STM32_HAL_BSEC
+	bool
+	help
+	  Enable STM32Cube Boot and Security Control (BSEC) HAL module driver
+
+config USE_STM32_HAL_CACHEAXI
+	bool
+	help
+	  Enable STM32Cube AXI Cache (CACHEAXI) HAL module driver
+
 config USE_STM32_HAL_CAN
 	bool
 	help
@@ -213,6 +223,11 @@ config USE_STM32_HAL_GFXMMU
 	help
 	  Enable STM32Cube Chrom-GRCTM (GFXMMU) HAL module driver
 
+config USE_STM32_HAL_GFXTIM
+	bool
+	help
+	  Enable STM32Cube Graphic Timer (GFXTIM) HAL module driver
+
 config USE_STM32_HAL_GPIO
 	bool
 	help
@@ -335,6 +350,11 @@ config USE_STM32_HAL_LTDC_EX
 	help
 	  Enable STM32Cube Extended LCD-TFT controller (LTDC) HAL module driver
 
+config USE_STM32_HAL_MCE
+	bool
+	help
+	  Enable STM32Cube Memory Cipher Engine (MCE) HAL module driver
+
 config USE_STM32_HAL_MDF
 	bool
 	help
@@ -463,11 +483,21 @@ config USE_STM32_HAL_RAMECC
 	help
 	  Enable STM32Cube RAM ECC monitoring (RAMECC) HAL module driver
 
+config USE_STM32_HAL_RIF
+	bool
+	help
+	  Enable STM32Cube Resource Isolation Framework (RIF) HAL module driver
+
 config USE_STM32_HAL_RNG
 	bool
 	help
 	  Enable STM32Cube True random number generator (RNG) HAL module driver
 
+config USE_STM32_HAL_RNG_EX
+	bool
+	help
+	  Enable STM32Cube Extended True random number generator (RNG) HAL module driver
+
 config USE_STM32_HAL_RTC
 	bool
 	help
@@ -533,6 +563,11 @@ config USE_STM32_HAL_SMBUS
 	help
 	  Enable STM32Cube System Management Bus (SMBus) HAL module driver
 
+config USE_STM32_HAL_SMBUS_EX
+	bool
+	help
+	  Enable STM32Cube Extended System Management Bus (SMBus) HAL module driver
+
 config USE_STM32_HAL_SPDIFRX
 	bool
 	help
@@ -656,7 +691,7 @@ config USE_STM32_LL_DELAYBLOCK
 config USE_STM32_LL_DLYB
 	bool
 	help
-	  Enable STM32Cube DelayBlock (DELAYBLOCK) LL module driver (stm32U5)
+	  Enable STM32Cube DelayBlock (DELAYBLOCK) LL module driver (stm32U5 or STM32N6)
 
 config USE_STM32_LL_DMA
 	bool
@@ -823,4 +858,14 @@ config USE_STM32_LL_UTILS
 	help
 	  Enable STM32Cube Utility functions (UTILS) LL module driver
 
+config USE_STM32_LL_VENC
+	bool
+	help
+	  Enable STM32Cube Video Encoder (VENC) LL module driver
+
+config USE_STM32_UTIL_I3C
+	bool
+	help
+	  Enable STM32Cube I3C Timing Utility functions (UTILS) module driver
+
 endif # HAS_STM32CUBE
diff --git a/modules/cmsis-dsp/CMakeLists.txt b/modules/cmsis-dsp/CMakeLists.txt
index e5ebbfcf172..2a0924cc25c 100644
--- a/modules/cmsis-dsp/CMakeLists.txt
+++ b/modules/cmsis-dsp/CMakeLists.txt
@@ -8,7 +8,7 @@ if(CONFIG_CMSIS_DSP)
 
   zephyr_library()
 
-  zephyr_library_compile_options(-Ofast)
+  zephyr_library_compile_options($<TARGET_PROPERTY:compiler,optimization_fast>)
 
   zephyr_include_directories(
     ${CMSIS_DSP_DIR}/Include
@@ -47,8 +47,6 @@ if(CONFIG_CMSIS_DSP)
     endif()
   endif()
 
-  zephyr_library_compile_options(-Ofast)
-
   zephyr_compile_definitions_ifndef(CONFIG_ARM __GNUC_PYTHON__)
 
   # BasicMathFunctions
diff --git a/modules/cmsis-nn/CMakeLists.txt b/modules/cmsis-nn/CMakeLists.txt
index ec55bafbcfa..7c05e8a585a 100644
--- a/modules/cmsis-nn/CMakeLists.txt
+++ b/modules/cmsis-nn/CMakeLists.txt
@@ -8,7 +8,7 @@ if(CONFIG_CMSIS_NN)
 
   zephyr_library()
 
-  zephyr_library_compile_options(-Ofast)
+  zephyr_library_compile_options($<TARGET_PROPERTY:compiler,optimization_fast>)
 
   zephyr_include_directories(${CMSIS_NN_DIR}/Include)
 
@@ -85,4 +85,14 @@ if(CONFIG_CMSIS_NN)
     zephyr_library_sources(${SRC})
   endif()
 
+  if(CONFIG_CMSIS_NN_TRANSPOSE)
+    file(GLOB SRC "${CMSIS_NN_DIR}/Source/TransposeFunctions/*_s8.c")
+    zephyr_library_sources(${SRC})
+  endif()
+
+  if(CONFIG_CMSIS_NN_PAD)
+    file(GLOB SRC "${CMSIS_NN_DIR}/Source/PadFunctions/*_s8.c")
+    zephyr_library_sources(${SRC})
+  endif()
+
 endif()
diff --git a/modules/cmsis-nn/Kconfig b/modules/cmsis-nn/Kconfig
index 53c3aa4987d..dd5395f92ef 100644
--- a/modules/cmsis-nn/Kconfig
+++ b/modules/cmsis-nn/Kconfig
@@ -78,4 +78,14 @@ config CMSIS_NN_LSTM
 	help
 	  This option enables the NN libraries for Long Short-Term Memory.
 
+config CMSIS_NN_PAD
+	bool "Pad"
+	help
+	  This option enables the NN libraries for the pad layers.
+
+config CMSIS_NN_TRANSPOSE
+	bool "Transpose"
+	help
+	  This option enables the NN libraries for the transpose layers.
+
 endif #CMSIS_NN
diff --git a/modules/cmsis/cmsis_core_a_r_ext.h b/modules/cmsis/cmsis_core_a_r_ext.h
index 0752b1474fa..e1ddce4c066 100644
--- a/modules/cmsis/cmsis_core_a_r_ext.h
+++ b/modules/cmsis/cmsis_core_a_r_ext.h
@@ -29,6 +29,33 @@
 #define FSR_FS_ALIGNMENT_FAULT				(33)
 #define FSR_FS_DEBUG_EVENT				(34)
 #define FSR_FS_UNSUPPORTED_EXCLUSIVE_ACCESS_FAULT	(53)
+#elif defined(CONFIG_ARMV7_A)
+
+/**
+ * N.B.: these FSR encodings are only valid when the
+ * Short-descriptor translation table format is used
+ */
+
+#define FSR_FS_ALIGNMENT_FAULT					(1)
+#define FSR_FS_DEBUG_EVENT					(2)
+#define FSR_FS_ACCESS_FLAG_FAULT_1ST_LEVEL			(3)
+#define FSR_FS_CACHE_MAINTENANCE_INSTRUCTION_FAULT		(4)
+#define FSR_FS_TRANSLATION_FAULT				(5)
+#define FSR_FS_ACCESS_FLAG_FAULT_2ND_LEVEL			(6)
+#define FSR_FS_TRANSLATION_FAULT_2ND_LEVEL			(7)
+#define FSR_FS_SYNC_EXTERNAL_ABORT				(8)
+#define FSR_FS_DOMAIN_FAULT_1ST_LEVEL				(9)
+#define FSR_FS_DOMAIN_FAULT_2ND_LEVEL				(11)
+#define FSR_FS_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_1ST_LEVEL	(12)
+#define FSR_FS_PERMISSION_FAULT					(13)
+#define FSR_FS_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_2ND_LEVEL	(14)
+#define FSR_FS_PERMISSION_FAULT_2ND_LEVEL			(15)
+#define FSR_FS_TLB_CONFLICT_FAULT				(16)
+#define FSR_FS_ASYNC_EXTERNAL_ABORT				(22)
+#define FSR_FS_ASYNC_PARITY_ERROR				(24)
+#define FSR_FS_SYNC_PARITY_ERROR				(25)
+#define FSR_FS_SYNC_PARITY_ERROR_TRANSLATION_TABLE_1ST_LEVEL	(28)
+#define FSR_FS_SYNC_PARITY_ERROR_TRANSLATION_TABLE_2ND_LEVEL	(30)
 #else
 #define FSR_FS_BACKGROUND_FAULT		(0)
 #define FSR_FS_ALIGNMENT_FAULT		(1)
diff --git a/modules/fatfs/zephyr_fatfs_config.h b/modules/fatfs/zephyr_fatfs_config.h
index 396f303ac0f..cf06957eb2f 100644
--- a/modules/fatfs/zephyr_fatfs_config.h
+++ b/modules/fatfs/zephyr_fatfs_config.h
@@ -4,10 +4,12 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#if FFCONF_DEF != 80286
+#if FFCONF_DEF != 5380
 #error "Configuration version mismatch"
 #endif
 
+#include <zephyr/devicetree.h>
+
 /*
  * Overrides of FF_ options from ffconf.h
  */
@@ -100,13 +102,21 @@
 #define FF_STR_VOLUME_ID 1
 
 /* By default FF_STR_VOLUME_ID in ffconf.h is 0, which means that
- * FF_VOLUME_STRS is not used. Zephyr uses FF_VOLUME_STRS, which
- * by default holds 8 possible strings representing mount points,
- * and FF_VOLUMES needs to reflect that, which means that dolt
- * value of 1 is overridden here with 8.
+ * FF_VOLUME_STRS is not used. Zephyr uses FF_VOLUME_STRS.
+ * The array of volume strings is automatically generated from devicetree.
  */
+
+#define _FF_DISK_NAME(node) DT_PROP(node, disk_name),
+
+#undef FF_VOLUME_STRS
+#define FF_VOLUME_STRS \
+	DT_FOREACH_STATUS_OKAY(zephyr_flash_disk, _FF_DISK_NAME) \
+	DT_FOREACH_STATUS_OKAY(zephyr_ram_disk, _FF_DISK_NAME) \
+	DT_FOREACH_STATUS_OKAY(zephyr_sdmmc_disk, _FF_DISK_NAME) \
+	DT_FOREACH_STATUS_OKAY(st_stm32_sdmmc, _FF_DISK_NAME)
+
 #undef FF_VOLUMES
-#define FF_VOLUMES 8
+#define FF_VOLUMES NUM_VA_ARGS_LESS_1(FF_VOLUME_STRS _)
 
 #if defined(CONFIG_FS_FATFS_EXTRA_NATIVE_API)
 #undef FF_USE_LABEL
@@ -117,6 +127,21 @@
 #define FF_USE_FIND 1
 #endif /* defined(CONFIG_FS_FATFS_EXTRA_NATIVE_API) */
 
+/*
+ * When custom mount points are activated FF_VOLUME_STRS needs
+ * to be undefined in order to be able to provide a custom
+ * VolumeStr array containing the contents of
+ * CONFIG_FS_FATFS_CUSTOM_MOUNT_POINTS. Additionally the
+ * FF_VOLUMES define needs to be set to the correct mount
+ * point count contained in
+ * CONFIG_FS_FATFS_CUSTOM_MOUNT_POINT_COUNT.
+ */
+#if CONFIG_FS_FATFS_CUSTOM_MOUNT_POINT_COUNT
+#undef FF_VOLUMES
+#define FF_VOLUMES CONFIG_FS_FATFS_CUSTOM_MOUNT_POINT_COUNT
+#undef FF_VOLUME_STRS
+#endif /* CONFIG_FS_FATFS_CUSTOM_MOUNT_POINT_COUNT */
+
 /*
  * Options provided below have been added to ELM FAT source code to
  * support Zephyr specific features, and are not part of ffconf.h.
diff --git a/modules/fatfs/zfs_diskio.c b/modules/fatfs/zfs_diskio.c
index 2b0fa742e71..ef9fe8acd45 100644
--- a/modules/fatfs/zfs_diskio.c
+++ b/modules/fatfs/zfs_diskio.c
@@ -8,7 +8,7 @@
 /* The file is based on template file by (C)ChaN, 2019, as
  * available from FAT FS module source:
  * https://github.com/zephyrproject-rtos/fatfs/blob/master/diskio.c
- * and has been previously avaialble from directory for that module
+ * and has been previously available from directory for that module
  * under name zfs_diskio.c.
  */
 #include <ff.h>
@@ -16,14 +16,19 @@
 #include <zfs_diskio.h> /* Zephyr specific FatFS API */
 #include <zephyr/storage/disk_access.h>
 
-static const char * const pdrv_str[] = {FF_VOLUME_STRS};
+#if CONFIG_FS_FATFS_CUSTOM_MOUNT_POINT_COUNT
+#define PDRV_STR_ARRAY VolumeStr
+#else
+static const char *const pdrv_str[] = {FF_VOLUME_STRS};
+#define PDRV_STR_ARRAY pdrv_str
+#endif /* CONFIG_FS_FATFS_CUSTOM_MOUNT_POINT_COUNT */
 
 /* Get Drive Status */
 DSTATUS disk_status(BYTE pdrv)
 {
-	__ASSERT(pdrv < ARRAY_SIZE(pdrv_str), "pdrv out-of-range\n");
+	__ASSERT(pdrv < ARRAY_SIZE(PDRV_STR_ARRAY), "pdrv out-of-range\n");
 
-	if (disk_access_status(pdrv_str[pdrv]) != 0) {
+	if (disk_access_status(PDRV_STR_ARRAY[pdrv]) != 0) {
 		return STA_NOINIT;
 	} else {
 		return RES_OK;
@@ -41,22 +46,21 @@ DSTATUS disk_initialize(BYTE pdrv)
 /* Read Sector(s) */
 DRESULT disk_read(BYTE pdrv, BYTE *buff, LBA_t sector, UINT count)
 {
-	__ASSERT(pdrv < ARRAY_SIZE(pdrv_str), "pdrv out-of-range\n");
+	__ASSERT(pdrv < ARRAY_SIZE(PDRV_STR_ARRAY), "pdrv out-of-range\n");
 
-	if (disk_access_read(pdrv_str[pdrv], buff, sector, count) != 0) {
+	if (disk_access_read(PDRV_STR_ARRAY[pdrv], buff, sector, count) != 0) {
 		return RES_ERROR;
 	} else {
 		return RES_OK;
 	}
-
 }
 
 /* Write Sector(s) */
 DRESULT disk_write(BYTE pdrv, const BYTE *buff, LBA_t sector, UINT count)
 {
-	__ASSERT(pdrv < ARRAY_SIZE(pdrv_str), "pdrv out-of-range\n");
+	__ASSERT(pdrv < ARRAY_SIZE(PDRV_STR_ARRAY), "pdrv out-of-range\n");
 
-	if (disk_access_write(pdrv_str[pdrv], buff, sector, count) != 0) {
+	if (disk_access_write(PDRV_STR_ARRAY[pdrv], buff, sector, count) != 0) {
 		return RES_ERROR;
 	} else {
 		return RES_OK;
@@ -69,19 +73,18 @@ DRESULT disk_ioctl(BYTE pdrv, BYTE cmd, void *buff)
 	int ret = RES_OK;
 	uint32_t sector_size = 0;
 
-	__ASSERT(pdrv < ARRAY_SIZE(pdrv_str), "pdrv out-of-range\n");
+	__ASSERT(pdrv < ARRAY_SIZE(PDRV_STR_ARRAY), "pdrv out-of-range\n");
 
 	switch (cmd) {
 	case CTRL_SYNC:
-		if (disk_access_ioctl(pdrv_str[pdrv],
-				DISK_IOCTL_CTRL_SYNC, buff) != 0) {
+		if (disk_access_ioctl(PDRV_STR_ARRAY[pdrv], DISK_IOCTL_CTRL_SYNC, buff) != 0) {
 			ret = RES_ERROR;
 		}
 		break;
 
 	case GET_SECTOR_COUNT:
-		if (disk_access_ioctl(pdrv_str[pdrv],
-				DISK_IOCTL_GET_SECTOR_COUNT, buff) != 0) {
+		if (disk_access_ioctl(PDRV_STR_ARRAY[pdrv], DISK_IOCTL_GET_SECTOR_COUNT, buff) !=
+		    0) {
 			ret = RES_ERROR;
 		}
 		break;
@@ -91,9 +94,9 @@ DRESULT disk_ioctl(BYTE pdrv, BYTE cmd, void *buff)
 		 * 32-bit number while FatFS's GET_SECTOR_SIZE is supposed to
 		 * return a 16-bit number.
 		 */
-		if ((disk_access_ioctl(pdrv_str[pdrv],
-				DISK_IOCTL_GET_SECTOR_SIZE, &sector_size) == 0) &&
-			(sector_size == (uint16_t)sector_size)) {
+		if ((disk_access_ioctl(PDRV_STR_ARRAY[pdrv], DISK_IOCTL_GET_SECTOR_SIZE,
+				       &sector_size) == 0) &&
+		    (sector_size == (uint16_t)sector_size)) {
 			*(uint16_t *)buff = (uint16_t)sector_size;
 		} else {
 			ret = RES_ERROR;
@@ -101,8 +104,8 @@ DRESULT disk_ioctl(BYTE pdrv, BYTE cmd, void *buff)
 		break;
 
 	case GET_BLOCK_SIZE:
-		if (disk_access_ioctl(pdrv_str[pdrv],
-				DISK_IOCTL_GET_ERASE_BLOCK_SZ, buff) != 0) {
+		if (disk_access_ioctl(PDRV_STR_ARRAY[pdrv], DISK_IOCTL_GET_ERASE_BLOCK_SZ, buff) !=
+		    0) {
 			ret = RES_ERROR;
 		}
 		break;
@@ -113,16 +116,14 @@ DRESULT disk_ioctl(BYTE pdrv, BYTE cmd, void *buff)
 	case CTRL_POWER:
 		if (((*(uint8_t *)buff)) == DISK_IOCTL_POWER_OFF) {
 			/* Power disk off */
-			if (disk_access_ioctl(pdrv_str[pdrv],
-					      DISK_IOCTL_CTRL_DEINIT,
-					      NULL) != 0) {
+			if (disk_access_ioctl(PDRV_STR_ARRAY[pdrv], DISK_IOCTL_CTRL_DEINIT, NULL) !=
+			    0) {
 				ret = RES_ERROR;
 			}
 		} else {
 			/* Power disk on */
-			if (disk_access_ioctl(pdrv_str[pdrv],
-					      DISK_IOCTL_CTRL_INIT,
-					      NULL) != 0) {
+			if (disk_access_ioctl(PDRV_STR_ARRAY[pdrv], DISK_IOCTL_CTRL_INIT, NULL) !=
+			    0) {
 				ret = STA_NOINIT;
 			}
 		}
diff --git a/modules/hal_ambiq/Kconfig b/modules/hal_ambiq/Kconfig
index 1f48cbb4f76..855ccfe528e 100644
--- a/modules/hal_ambiq/Kconfig
+++ b/modules/hal_ambiq/Kconfig
@@ -1,78 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 # Copyright (c) 2023 Antmicro <www.antmicro.com>
+# Copyright (c) 2025, Ambiq Micro Inc. <www.ambiq.com>
 
-config AMBIQ_HAL
-	bool "Ambiq HAL drivers support"
-	depends on SOC_SERIES_APOLLO4X || SOC_SERIES_APOLLO3X
-	help
-	  Use the Ambiq HAL
-
-if AMBIQ_HAL
-
-config AMBIQ_HAL_USE_ADC
-	bool
-	help
-	  Use the ADC driver from Ambiq HAL
-
-config AMBIQ_HAL_USE_GPIO
-	bool
-	help
-	  Use the GPIO driver from Ambiq HAL
-
-config AMBIQ_HAL_USE_STIMER
-	bool
-	help
-	  Use the STIMER driver from Ambiq HAL
-
-config AMBIQ_HAL_USE_TIMER
-	bool
-	help
-	  Use the TIMER driver from Ambiq HAL
-
-config AMBIQ_HAL_USE_WDT
-	bool
-	help
-	  Use the WDT driver from Ambiq HAL
-
-config AMBIQ_HAL_USE_I2C
-	bool
-	help
-	  Use the I2C driver from Ambiq HAL
-
-config AMBIQ_HAL_USE_SPIC
-	bool
-	help
-	  Use the SPI Controller driver from Ambiq HAL
-
-config AMBIQ_HAL_USE_SPID
-	bool
-	help
-	  Use the SPI Device driver from Ambiq HAL
-
-config AMBIQ_HAL_USE_MSPI
-	bool
-	help
-	  Use the MSPI driver from Ambiq HAL
-
-config AMBIQ_HAL_USE_HWINFO
-	bool
-	help
-	  Use the HWINFO driver from Ambiq HAL
-
-config AMBIQ_HAL_USE_BLEIF
-	bool
-	help
-	  Use the BLEIF driver from Ambiq HAL
-
-config AMBIQ_HAL_USE_ADC
-	bool
-	help
-	  Use the ADC driver from Ambiq HAL
-
-config AMBIQ_HAL_USE_USB
-	bool
-	help
-	  Use the USB driver from Ambiq HAL
-
-endif # AMBIQ_HAL
+rsource "Kconfig.hal"
+rsource "Kconfig.components"
diff --git a/modules/hal_ambiq/Kconfig.components b/modules/hal_ambiq/Kconfig.components
new file mode 100644
index 00000000000..f9f98e9a5ab
--- /dev/null
+++ b/modules/hal_ambiq/Kconfig.components
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# Copyright (c) 2025, Ambiq Micro Inc. <www.ambiq.com>
+
+config AMBIQ_COMPONENT_USE_BT
+	bool
+	depends on SOC_AMBIQ_BT_SUPPORTED
+	help
+	  Use Bluetooth component from Ambiq
diff --git a/modules/hal_ambiq/Kconfig.hal b/modules/hal_ambiq/Kconfig.hal
new file mode 100644
index 00000000000..078d770e286
--- /dev/null
+++ b/modules/hal_ambiq/Kconfig.hal
@@ -0,0 +1,114 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# Copyright (c) 2025, Ambiq Micro Inc. <www.ambiq.com>
+
+config AMBIQ_HAL
+	bool "Ambiq HAL drivers support"
+	depends on SOC_SERIES_APOLLO3X || SOC_SERIES_APOLLO4X || SOC_SERIES_APOLLO5X
+	help
+	  Use the Ambiq HAL
+
+if AMBIQ_HAL
+
+config AMBIQ_HAL_USE_ADC
+	bool
+	help
+	  Use the ADC driver from Ambiq HAL
+
+config AMBIQ_HAL_USE_ITM
+	bool
+	help
+	  Use the ITM HAL from Ambiq
+
+config AMBIQ_HAL_USE_TPIU
+	bool
+	help
+	  Use the TPIU HAL from Ambiq
+
+config AMBIQ_HAL_USE_DCU
+	bool
+	help
+	  Use the DCU HAL from Ambiq
+
+config AMBIQ_HAL_USE_GPIO
+	bool
+	help
+	  Use the GPIO driver from Ambiq HAL
+
+config AMBIQ_HAL_USE_STIMER
+	bool
+	help
+	  Use the STIMER driver from Ambiq HAL
+
+config AMBIQ_HAL_USE_TIMER
+	bool
+	help
+	  Use the TIMER driver from Ambiq HAL
+
+config AMBIQ_HAL_USE_WDT
+	bool
+	help
+	  Use the WDT driver from Ambiq HAL
+
+config AMBIQ_HAL_USE_I2C
+	bool
+	help
+	  Use the I2C driver from Ambiq HAL
+
+config AMBIQ_HAL_USE_SPIC
+	bool
+	help
+	  Use the SPI Controller driver from Ambiq HAL
+
+config AMBIQ_HAL_USE_SPID
+	bool
+	help
+	  Use the SPI Device driver from Ambiq HAL
+
+config AMBIQ_HAL_USE_MSPI
+	bool
+	help
+	  Use the MSPI driver from Ambiq HAL
+
+config AMBIQ_HAL_USE_HWINFO
+	bool
+	help
+	  Use the HWINFO driver from Ambiq HAL
+
+config AMBIQ_HAL_USE_BLEIF
+	bool
+	help
+	  Use the BLEIF driver from Ambiq HAL
+
+config AMBIQ_HAL_USE_ADC
+	bool
+	help
+	  Use the ADC driver from Ambiq HAL
+
+config AMBIQ_HAL_USE_USB
+	bool
+	help
+	  Use the USB driver from Ambiq HAL
+
+config AMBIQ_HAL_USE_SDIO
+	bool
+	help
+	  Use the SDIO driver from Ambiq HAL
+
+config AMBIQ_HAL_USE_ADC
+	bool
+	help
+	  Use the ADC driver from Ambiq HAL
+
+config AMBIQ_HAL_USE_DSI
+	bool
+	help
+	  Use the DSI driver from Ambiq HAL
+
+config AMBIQ_HAL_USE_USB
+	bool
+	help
+	  Use the USB driver from Ambiq HAL
+
+endif # AMBIQ_HAL
diff --git a/modules/hal_bouffalolab/CMakeLists.txt b/modules/hal_bouffalolab/CMakeLists.txt
new file mode 100644
index 00000000000..eb56320bb7c
--- /dev/null
+++ b/modules/hal_bouffalolab/CMakeLists.txt
@@ -0,0 +1,55 @@
+# Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_FAMILY_BOUFFALOLAB_BFLB)
+  zephyr_library_named(hal_bouffalolab)
+
+  zephyr_library_compile_definitions(
+    BFLB_USE_HAL_DRIVER
+    BFLB_USE_CUSTOM_LD_SECTIONS
+  )
+
+  set(bflb_soc         bl602)
+  set(bflb_drv_dir     ${ZEPHYR_HAL_BOUFFALOLAB_MODULE_DIR}/drivers/${bflb_soc}_driver)
+  set(bflb_common_dir  ${ZEPHYR_HAL_BOUFFALOLAB_MODULE_DIR}/common)
+  set(bflb_drv_src_dir ${bflb_drv_dir}/std_drv/src)
+
+  # Global includes
+  zephyr_include_directories(
+    include
+    ${ZEPHYR_HAL_BOUFFALOLAB_MODULE_DIR}/include
+
+    ${bflb_drv_dir}/regs
+    ${bflb_drv_dir}/startup
+    ${bflb_drv_dir}/std_drv/inc
+
+    ${bflb_common_dir}/misc
+  )
+
+  zephyr_library_include_directories(
+    ${bflb_common_dir}/soft_crc
+  )
+
+  zephyr_library_sources(
+    ${bflb_drv_src_dir}/${bflb_soc}_aon.c
+    ${bflb_drv_src_dir}/${bflb_soc}_ef_ctrl.c
+    ${bflb_drv_src_dir}/${bflb_soc}_glb.c
+    ${bflb_drv_src_dir}/${bflb_soc}_hbn.c
+    ${bflb_drv_src_dir}/${bflb_soc}_l1c.c
+    ${bflb_drv_src_dir}/${bflb_soc}_pds.c
+    ${bflb_drv_src_dir}/${bflb_soc}_romapi.c
+
+    ${bflb_common_dir}/soft_crc/softcrc.c
+  )
+
+  zephyr_library_sources_ifdef(CONFIG_USE_BFLB_ACOMP ${bflb_drv_src_dir}/${bflb_soc}_acomp.c)
+  zephyr_library_sources_ifdef(CONFIG_USE_BFLB_ADC   ${bflb_drv_src_dir}/${bflb_soc}_adc.c)
+  zephyr_library_sources_ifdef(CONFIG_USE_BFLB_DAC   ${bflb_drv_src_dir}/${bflb_soc}_dac.c)
+  zephyr_library_sources_ifdef(CONFIG_USE_BFLB_DMA   ${bflb_drv_src_dir}/${bflb_soc}_dma.c)
+  zephyr_library_sources_ifdef(CONFIG_USE_BFLB_I2C   ${bflb_drv_src_dir}/${bflb_soc}_i2c.c)
+  zephyr_library_sources_ifdef(CONFIG_USE_BFLB_IR    ${bflb_drv_src_dir}/${bflb_soc}_ir.c)
+  zephyr_library_sources_ifdef(CONFIG_USE_BFLB_PWM   ${bflb_drv_src_dir}/${bflb_soc}_pwm.c)
+  zephyr_library_sources_ifdef(CONFIG_USE_BFLB_SPI   ${bflb_drv_src_dir}/${bflb_soc}_spi.c)
+  zephyr_library_sources_ifdef(CONFIG_USE_BFLB_UART  ${bflb_drv_src_dir}/${bflb_soc}_uart.c)
+endif() # SOC_FAMILY_BOUFFALOLAB_BFLB
diff --git a/modules/hal_bouffalolab/Kconfig b/modules/hal_bouffalolab/Kconfig
new file mode 100644
index 00000000000..c6c4469117b
--- /dev/null
+++ b/modules/hal_bouffalolab/Kconfig
@@ -0,0 +1,59 @@
+# Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config ZEPHYR_HAL_BOUFFALOLAB_MODULE
+	bool
+
+config HAS_BFLB_HAL
+	bool
+
+if HAS_BFLB_HAL
+
+config USE_BFLB_ACOMP
+	bool
+	help
+	  Enable BFLB Analog Comparator (ACOMP) HAL module driver
+
+config USE_BFLB_ADC
+	bool
+	help
+	  Enable BFLB Analog-to-Digital Converter (ADC) HAL module driver
+
+config USE_BFLB_DAC
+	bool
+	help
+	  Enable BFLB Digital-to-Analog Converter (DAC) HAL module driver
+
+config USE_BFLB_DMA
+	bool
+	help
+	  Enable BFLB Direct Memory Access controller (DMA) HAL module driver
+
+config USE_BFLB_I2C
+	bool
+	help
+	  Enable BFLB Inter-Integrated Circuit Interface (I2C) HAL module driver
+
+config USE_BFLB_IR
+	bool
+	help
+	  Enable BFLB Infrared Remote controller (IR) HAL module driver
+
+config USE_BFLB_PWM
+	bool
+	help
+	  Enable BFLB Pulse Width Modulation (PMU) HAL module driver
+
+config USE_BFLB_SPI
+	bool
+	help
+	  Enable BFLB Serial Peripheral Interface(SPI) HAL module driver
+
+config USE_BFLB_UART
+	bool
+	help
+	  Enable BFLB Universal Asynchronous Receiver/Transmitter (UART)
+	  HAL module driver
+
+endif # HAS_BFLB_HAL
diff --git a/modules/hal_bouffalolab/include/bflb_glb.h b/modules/hal_bouffalolab/include/bflb_glb.h
new file mode 100644
index 00000000000..d8aff224df9
--- /dev/null
+++ b/modules/hal_bouffalolab/include/bflb_glb.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_HAL_BFLB_GLB_H_
+#define ZEPHYR_HAL_BFLB_GLB_H_
+
+#ifdef CONFIG_SOC_SERIES_BL60X
+#include <bl602_glb.h>
+#endif
+
+#endif	/* ZEPHYR_HAL_BFLB_GLB_H_ */
diff --git a/modules/hal_bouffalolab/include/bflb_gpio.h b/modules/hal_bouffalolab/include/bflb_gpio.h
new file mode 100644
index 00000000000..9ac0ca7bf1d
--- /dev/null
+++ b/modules/hal_bouffalolab/include/bflb_gpio.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_HAL_BFLB_GPIO_H_
+#define ZEPHYR_HAL_BFLB_GPIO_H_
+
+#ifdef CONFIG_SOC_SERIES_BL60X
+#include <bl602_gpio.h>
+#endif
+
+#endif	/* ZEPHYR_HAL_BFLB_GPIO_H_ */
diff --git a/modules/hal_bouffalolab/include/bflb_hbn.h b/modules/hal_bouffalolab/include/bflb_hbn.h
new file mode 100644
index 00000000000..1580dea3ffb
--- /dev/null
+++ b/modules/hal_bouffalolab/include/bflb_hbn.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_HAL_BFLB_HBN_H_
+#define ZEPHYR_HAL_BFLB_HBN_H_
+
+#ifdef CONFIG_SOC_SERIES_BL60X
+#include <bl602_hbn.h>
+#endif
+
+#endif	/* ZEPHYR_HAL_BFLB_HBN_H_ */
diff --git a/modules/hal_bouffalolab/include/bflb_pinctrl.h b/modules/hal_bouffalolab/include/bflb_pinctrl.h
new file mode 100644
index 00000000000..8226b01ec5d
--- /dev/null
+++ b/modules/hal_bouffalolab/include/bflb_pinctrl.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_HAL_BFLB_PINCTRL_H_
+#define ZEPHYR_HAL_BFLB_PINCTRL_H_
+
+#ifdef CONFIG_SOC_SERIES_BL60X
+#include <zephyr/dt-bindings/pinctrl/bl60x-pinctrl.h>
+#endif
+#include <zephyr/dt-bindings/pinctrl/bflb-common-pinctrl.h>
+
+#endif	/* ZEPHYR_HAL_BFLB_PINCTRL_H_ */
diff --git a/modules/hal_bouffalolab/include/bflb_uart.h b/modules/hal_bouffalolab/include/bflb_uart.h
new file mode 100644
index 00000000000..d2675527297
--- /dev/null
+++ b/modules/hal_bouffalolab/include/bflb_uart.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_HAL_BFLB_UART_H_
+#define ZEPHYR_HAL_BFLB_UART_H_
+
+#ifdef CONFIG_SOC_SERIES_BL60X
+#include <bl602_uart.h>
+#endif
+
+#endif	/* ZEPHYR_HAL_BFLB_UART_H_ */
diff --git a/modules/hal_bouffalolab/include/bl_ld_sections.h b/modules/hal_bouffalolab/include/bl_ld_sections.h
new file mode 100644
index 00000000000..c1a9c11838f
--- /dev/null
+++ b/modules/hal_bouffalolab/include/bl_ld_sections.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef __BL_LD_SECTIONS_H
+#define __BL_LD_SECTIONS_H
+
+#define ATTR_STRINGIFY(x)          #x
+#define ATTR_TOSTRING(x)           ATTR_STRINGIFY(x)
+#define ATTR_SECTION(x)            __attribute__((section(x)))
+#define ATTR_UNI_SYMBOL            __FILE__ ATTR_TOSTRING(__LINE__)
+#define ATTR_CLOCK_SECTION         ATTR_SECTION(".itcm.sclock_rlt_code." ATTR_UNI_SYMBOL)
+#define ATTR_CLOCK_CONST_SECTION   ATTR_SECTION(".itcm.sclock_rlt_const." ATTR_UNI_SYMBOL)
+#define ATTR_TCM_SECTION           ATTR_SECTION(".itcm.code." ATTR_UNI_SYMBOL)
+#define ATTR_TCM_CONST_SECTION     ATTR_SECTION(".itcm.const." ATTR_UNI_SYMBOL)
+#define ATTR_DTCM_SECTION          ATTR_SECTION(".dtcm.data")
+#define ATTR_HSRAM_SECTION         ATTR_SECTION(".hsram_code")
+#define ATTR_DMA_RAM_SECTION       ATTR_SECTION(".system_ram")
+#define ATTR_HBN_RAM_SECTION       ATTR_SECTION(".hbn_ram_code")
+#define ATTR_HBN_RAM_CONST_SECTION ATTR_SECTION(".hbn_ram_data")
+#define ATTR_FALLTHROUGH()         __attribute__((fallthrough))
+#define ATTR_USED                  __attribute__((__used__))
+#define ATTR_EALIGN(x)             __aligned(size)
+
+#endif /* __BL_LD_SECTIONS_H */
diff --git a/modules/hal_infineon/CMakeLists.txt b/modules/hal_infineon/CMakeLists.txt
index 0715737250f..09cb72b0d8a 100644
--- a/modules/hal_infineon/CMakeLists.txt
+++ b/modules/hal_infineon/CMakeLists.txt
@@ -4,7 +4,7 @@
 
 if(CONFIG_HAS_XMCLIB OR CONFIG_SOC_FAMILY_PSOC6_LEGACY OR CONFIG_SOC_FAMILY_INFINEON_CAT1)
   zephyr_library_named(modules_hal_infineon)
-  zephyr_library_compile_options(-Wno-array-bounds)
+  zephyr_library_compile_options($<TARGET_PROPERTY:compiler,warning_no_array_bounds>)
 endif()
 
 ## Add PDL sources for XMC devices
diff --git a/modules/hal_infineon/Kconfig b/modules/hal_infineon/Kconfig
index 17c2d283ce4..eba1a49e24e 100644
--- a/modules/hal_infineon/Kconfig
+++ b/modules/hal_infineon/Kconfig
@@ -14,6 +14,11 @@ config USE_INFINEON_ADC
 	help
 	  Enable Analog-to-Digital Converter (ADC) HAL module driver for Infineon devices
 
+config USE_INFINEON_DMA
+	bool
+	help
+	  Enable ADC HAL module driver for Infineon devices
+
 config USE_INFINEON_I2C
 	bool
 	help
diff --git a/modules/hal_infineon/abstraction-rtos/source/COMPONENT_ZEPHYR/cyabs_rtos_zephyr.c b/modules/hal_infineon/abstraction-rtos/source/COMPONENT_ZEPHYR/cyabs_rtos_zephyr.c
index ae06b13892c..27cf46f9a58 100644
--- a/modules/hal_infineon/abstraction-rtos/source/COMPONENT_ZEPHYR/cyabs_rtos_zephyr.c
+++ b/modules/hal_infineon/abstraction-rtos/source/COMPONENT_ZEPHYR/cyabs_rtos_zephyr.c
@@ -308,10 +308,8 @@ cy_rslt_t cy_rtos_wait_thread_notification(cy_time_t timeout_ms)
 	return status;
 }
 
-cy_rslt_t cy_rtos_thread_set_notification(cy_thread_t *thread, bool in_isr)
+cy_rslt_t cy_rtos_thread_set_notification(cy_thread_t *thread)
 {
-	CY_UNUSED_PARAMETER(in_isr);
-
 	cy_rslt_t status = CY_RSLT_SUCCESS;
 
 	if (thread == NULL) {
@@ -426,8 +424,6 @@ cy_rslt_t cy_rtos_init_semaphore(cy_semaphore_t *semaphore, uint32_t maxcount, u
 
 cy_rslt_t cy_rtos_get_semaphore(cy_semaphore_t *semaphore, cy_time_t timeout_ms, bool in_isr)
 {
-	CY_UNUSED_PARAMETER(in_isr);
-
 	cy_rtos_error_t status_internal;
 	cy_rslt_t status;
 
@@ -462,8 +458,6 @@ cy_rslt_t cy_rtos_get_semaphore(cy_semaphore_t *semaphore, cy_time_t timeout_ms,
 
 cy_rslt_t cy_rtos_set_semaphore(cy_semaphore_t *semaphore, bool in_isr)
 {
-	CY_UNUSED_PARAMETER(in_isr);
-
 	cy_rslt_t status = CY_RSLT_SUCCESS;
 
 	if (semaphore == NULL) {
@@ -523,8 +517,6 @@ cy_rslt_t cy_rtos_init_event(cy_event_t *event)
 
 cy_rslt_t cy_rtos_setbits_event(cy_event_t *event, uint32_t bits, bool in_isr)
 {
-	CY_UNUSED_PARAMETER(in_isr);
-
 	cy_rslt_t status = CY_RSLT_SUCCESS;
 
 	if (event == NULL) {
@@ -539,8 +531,6 @@ cy_rslt_t cy_rtos_setbits_event(cy_event_t *event, uint32_t bits, bool in_isr)
 
 cy_rslt_t cy_rtos_clearbits_event(cy_event_t *event, uint32_t bits, bool in_isr)
 {
-	CY_UNUSED_PARAMETER(in_isr);
-
 	cy_rslt_t status = CY_RSLT_SUCCESS;
 
 	if (event == NULL) {
@@ -645,8 +635,6 @@ cy_rslt_t cy_rtos_init_queue(cy_queue_t *queue, size_t length, size_t itemsize)
 cy_rslt_t cy_rtos_put_queue(cy_queue_t *queue, const void *item_ptr, cy_time_t timeout_ms,
 			    bool in_isr)
 {
-	CY_UNUSED_PARAMETER(in_isr);
-
 	cy_rtos_error_t status_internal;
 	cy_rslt_t status;
 
@@ -674,8 +662,6 @@ cy_rslt_t cy_rtos_put_queue(cy_queue_t *queue, const void *item_ptr, cy_time_t t
 
 cy_rslt_t cy_rtos_get_queue(cy_queue_t *queue, void *item_ptr, cy_time_t timeout_ms, bool in_isr)
 {
-	CY_UNUSED_PARAMETER(in_isr);
-
 	cy_rtos_error_t status_internal;
 	cy_rslt_t status;
 
diff --git a/modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt b/modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt
index 268ae46546f..615d7874dec 100644
--- a/modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt
+++ b/modules/hal_infineon/mtb-hal-cat1/CMakeLists.txt
@@ -73,8 +73,6 @@ zephyr_library_sources_ifdef(CONFIG_SOC_DIE_PSOC6_04
   ${hal_cat1a_dir}/source/triggers/cyhal_triggers_psoc6_04.c)
 
 # High level interface for interacting with CAT1 hardware
-zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC     ${hal_dir}/source/cyhal_adc_sar.c)
-zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC     ${hal_dir}/source/cyhal_analog_common.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_FLASH   ${hal_dir}/source/cyhal_nvm.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_I2C     ${hal_dir}/source/cyhal_i2c.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_LPTIMER ${hal_dir}/source/cyhal_lptimer.c)
@@ -85,6 +83,9 @@ zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_TIMER   ${hal_dir}/source/cyhal
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_TRNG    ${hal_dir}/source/cyhal_trng.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_UART    ${hal_dir}/source/cyhal_uart.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_WDT     ${hal_dir}/source/cyhal_wdt.c)
+zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_DMA     ${hal_dir}/source/cyhal_dma.c)
+zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_DMA     ${hal_dir}/source/cyhal_dma_dw.c)
+zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_DMA     ${hal_dir}/source/cyhal_dma_dmac.c)
 
 if(CONFIG_USE_INFINEON_ADC OR CONFIG_USE_INFINEON_SMIF)
   zephyr_library_sources(${hal_dir}/source/cyhal_dma.c)
@@ -92,6 +93,16 @@ if(CONFIG_USE_INFINEON_ADC OR CONFIG_USE_INFINEON_SMIF)
   zephyr_library_sources(${hal_dir}/source/cyhal_dma_dw.c)
 endif()
 
+if(CONFIG_SOC_FAMILY_INFINEON_CAT1B)
+  zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC     ${hal_dir}/source/cyhal_adc_mic.c)
+else()
+  zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC     ${hal_dir}/source/cyhal_adc_sar.c)
+endif()
+
+if(CONFIG_USE_INFINEON_ADC)
+  zephyr_library_sources(${hal_dir}/source/cyhal_analog_common.c)
+endif()
+
 if(CONFIG_USE_INFINEON_TIMER)
   zephyr_library_sources(${hal_dir}/source/cyhal_tcpwm_common.c)
 endif()
diff --git a/modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt b/modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt
index 1166a484381..b46395bfbb8 100644
--- a/modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt
+++ b/modules/hal_infineon/mtb-pdl-cat1/CMakeLists.txt
@@ -33,7 +33,6 @@ zephyr_library_sources(${pdl_drv_dir}/source/TOOLCHAIN_GCC_ARM/cy_syslib_ext.S)
 
 # Peripheral drivers
 zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_PSOC6_LEGACY      ${pdl_drv_dir}/source/cy_sysint.c)
-zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_ADC      ${pdl_drv_dir}/source/cy_sar.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_I2C      ${pdl_drv_dir}/source/cy_scb_i2c.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_LPTIMER  ${pdl_drv_dir}/source/cy_mcwdt.c)
 zephyr_library_sources_ifdef(CONFIG_USE_INFINEON_PWM      ${pdl_drv_dir}/source/cy_tcpwm_pwm.c)
@@ -61,7 +60,7 @@ if(CONFIG_USE_INFINEON_UART OR CONFIG_USE_INFINEON_I2C OR CONFIG_USE_INFINEON_SP
   zephyr_library_sources(${pdl_drv_dir}/source/cy_scb_common.c)
 endif()
 
-if(CONFIG_USE_INFINEON_ADC OR CONFIG_USE_INFINEON_SMIF)
+if(CONFIG_USE_INFINEON_DMA OR CONFIG_USE_INFINEON_ADC OR CONFIG_USE_INFINEON_SMIF)
   zephyr_library_sources(${pdl_drv_dir}/source/cy_dma.c)
   zephyr_library_sources(${pdl_drv_dir}/source/cy_dmac.c)
 endif()
@@ -98,6 +97,7 @@ zephyr_library_sources(${pdl_drv_dir}/source/cy_syspm.c)
 zephyr_library_sources(${pdl_drv_dir}/source/cy_systick.c)
 zephyr_library_sources(${pdl_drv_dir}/source/cy_trigmux.c)
 zephyr_library_sources(${pdl_drv_dir}/source/cy_wdt.c)
+zephyr_library_sources(${pdl_drv_dir}/source/cy_tcpwm_pwm.c)
 
 # add IPC_BT driver for CYW208XX devices
 zephyr_library_sources_ifdef(CONFIG_BT_CYW208XX  ${pdl_drv_dir}/source/cy_ipc_bt.c)
diff --git a/modules/hal_infineon/wifi-host-driver/CMakeLists.txt b/modules/hal_infineon/wifi-host-driver/CMakeLists.txt
index 7f6d9420862..02794e80505 100644
--- a/modules/hal_infineon/wifi-host-driver/CMakeLists.txt
+++ b/modules/hal_infineon/wifi-host-driver/CMakeLists.txt
@@ -198,12 +198,12 @@ if(CONFIG_CYW4373_STERLING_LWB5PLUS AND NOT CONFIG_AIROC_WIFI_CUSTOM)
     set(cyw43xx_clm_bin    ${hal_blobs_dir}/clm/COMPONENT_4373/COMPONENT_STERLING-LWB5plus/4373A0-mfgtest.clm_blob)
     zephyr_library_sources(${hal_wifi_dir_resources}/clm/COMPONENT_4373/COMPONENT_STERLING-LWB5plus/4373A0-mfgtest_clm_blob.c)
   else()
-    set(cyw43xx_clm_bin    ${hal_blobs_dir}/clm/COMPONENT_4373/COMPONENT_STERLING-LWB5plus/4373A0.clm_blob)
+    set(cyw43xx_clm_bin    ${hal_blobs_dir}/clm/COMPONENT_4373/4373A0.clm_blob)
     zephyr_library_sources(${hal_wifi_dir_resources}/clm/COMPONENT_4373/COMPONENT_STERLING-LWB5plus/4373A0_clm_blob.c)
   endif()
 
   # nvram
-  zephyr_include_directories_ifdef(${hal_wifi_dir_resources}/nvram/COMPONENT_4373/COMPONENT_STERLING-LWB5plus)
+  zephyr_include_directories(${hal_wifi_dir_resources}/nvram/COMPONENT_4373/COMPONENT_STERLING-LWB5plus)
 endif()
 
 # generate FW inc_blob from fw_bin
diff --git a/modules/hal_nordic/nrfs/backends/nrfs_backend_ipc_service.c b/modules/hal_nordic/nrfs/backends/nrfs_backend_ipc_service.c
index a3e7ff22100..c41beec2bb3 100644
--- a/modules/hal_nordic/nrfs/backends/nrfs_backend_ipc_service.c
+++ b/modules/hal_nordic/nrfs/backends/nrfs_backend_ipc_service.c
@@ -54,6 +54,8 @@ static struct ipc_channel_config ipc_cpusys_channel_config = {
 	.enabled	 = true
 };
 
+static sys_slist_t nrfs_backend_info_cb_slist = SYS_SLIST_STATIC_INIT(&nrfs_backend_info_cb_slist);
+
 /**
  * @brief nrfs backend error handler
  *
@@ -103,6 +105,12 @@ static void ipc_sysctrl_ept_bound(void *priv)
 	if (k_msgq_num_used_get(&ipc_transmit_msgq) > 0) {
 		k_work_submit(&backend_send_work);
 	}
+
+	struct nrfs_backend_bound_info_subs *subs;
+
+	SYS_SLIST_FOR_EACH_CONTAINER(&nrfs_backend_info_cb_slist, subs, node) {
+		subs->cb();
+	}
 }
 
 static void ipc_sysctrl_ept_recv(const void *data, size_t size, void *priv)
@@ -257,6 +265,15 @@ int nrfs_backend_wait_for_connection(k_timeout_t timeout)
 	return (events == IPC_INIT_DONE_EVENT ? 0 : (-EAGAIN));
 }
 
+void nrfs_backend_register_bound_subscribe(struct nrfs_backend_bound_info_subs *subs,
+					   nrfs_backend_bound_info_cb_t cb)
+{
+	if (cb) {
+		subs->cb = cb;
+		sys_slist_append(&nrfs_backend_info_cb_slist, &subs->node);
+	}
+}
+
 __weak void nrfs_backend_fatal_error_handler(enum nrfs_backend_error error_id)
 {
 	LOG_ERR("Fatal error: %d rebooting...", error_id);
diff --git a/modules/hal_nordic/nrfs/backends/nrfs_backend_ipc_service.h b/modules/hal_nordic/nrfs/backends/nrfs_backend_ipc_service.h
index 015d3f99643..0e3a899ec48 100644
--- a/modules/hal_nordic/nrfs/backends/nrfs_backend_ipc_service.h
+++ b/modules/hal_nordic/nrfs/backends/nrfs_backend_ipc_service.h
@@ -87,6 +87,21 @@ nrfs_err_t nrfs_backend_send_ex(void *message, size_t size, k_timeout_t timeout,
  */
 void nrfs_backend_fatal_error_handler(enum nrfs_backend_error error_id);
 
+typedef void (*nrfs_backend_bound_info_cb_t)(void);
+struct nrfs_backend_bound_info_subs {
+	sys_snode_t node;
+	nrfs_backend_bound_info_cb_t cb;
+};
+/**
+ * @brief Register callback function to notify when nrfs is connected.
+ * There can be multiple callbacks registered.
+ *
+ * @param subs Subcription instance.
+ * @param cb Callback
+ */
+void nrfs_backend_register_bound_subscribe(struct nrfs_backend_bound_info_subs *subs,
+				    nrfs_backend_bound_info_cb_t cb);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/modules/hal_nordic/nrfs/dvfs/Kconfig b/modules/hal_nordic/nrfs/dvfs/Kconfig
index 45a99f8a7ad..a1958adea99 100644
--- a/modules/hal_nordic/nrfs/dvfs/Kconfig
+++ b/modules/hal_nordic/nrfs/dvfs/Kconfig
@@ -17,6 +17,7 @@ config NRFS_LOCAL_DOMAIN_DVFS_TEST
 
 config NRFS_LOCAL_DOMAIN_DVFS_SCALE_DOWN_AFTER_INIT
 	bool "Local domain scale down after init"
+	select DEPRECATED
 	help
 	  Request lowest oppoint after DVFS initialization.
 
diff --git a/modules/hal_nordic/nrfx/CMakeLists.txt b/modules/hal_nordic/nrfx/CMakeLists.txt
index 431ae0ff070..d1972356fcc 100644
--- a/modules/hal_nordic/nrfx/CMakeLists.txt
+++ b/modules/hal_nordic/nrfx/CMakeLists.txt
@@ -124,6 +124,7 @@ zephyr_library_sources_ifdef(CONFIG_NRFX_PRS     ${SRC_DIR}/prs/nrfx_prs.c)
 zephyr_library_sources_ifdef(CONFIG_NRFX_ADC     ${SRC_DIR}/nrfx_adc.c)
 zephyr_library_sources_ifdef(CONFIG_NRFX_CLOCK   ${SRC_DIR}/nrfx_clock.c)
 zephyr_library_sources_ifdef(CONFIG_NRFX_COMP    ${SRC_DIR}/nrfx_comp.c)
+zephyr_library_sources_ifdef(CONFIG_NRFX_CRACEN  ${SRC_DIR}/nrfx_cracen.c)
 zephyr_library_sources_ifdef(CONFIG_NRFX_DPPI    ${SRC_DIR}/nrfx_dppi.c)
 zephyr_library_sources_ifdef(CONFIG_NRFX_EGU     ${SRC_DIR}/nrfx_egu.c)
 zephyr_library_sources_ifdef(CONFIG_NRFX_GPIOTE  ${SRC_DIR}/nrfx_gpiote.c)
diff --git a/modules/hal_nordic/nrfx/Kconfig b/modules/hal_nordic/nrfx/Kconfig
index 1e9f717e4bc..25fb1e2c038 100644
--- a/modules/hal_nordic/nrfx/Kconfig
+++ b/modules/hal_nordic/nrfx/Kconfig
@@ -25,6 +25,10 @@ config NRFX_COMP
 	bool "COMP driver"
 	depends on $(dt_nodelabel_exists,comp)
 
+config NRFX_CRACEN
+	bool "CRACEN drivers"
+	depends on SOC_COMPATIBLE_NRF54LX
+
 config NRFX_DPPI
 	bool
 
diff --git a/modules/hal_nordic/nrfx/nrfx_kconfig.h b/modules/hal_nordic/nrfx/nrfx_kconfig.h
index 871c66ac325..ef870a568b2 100644
--- a/modules/hal_nordic/nrfx/nrfx_kconfig.h
+++ b/modules/hal_nordic/nrfx/nrfx_kconfig.h
@@ -75,6 +75,10 @@
 #define NRFX_COMP_CONFIG_LOG_ENABLED 1
 #endif
 
+#ifdef CONFIG_NRFX_CRACEN
+#define NRFX_CRACEN_ENABLED 1
+#endif
+
 #ifdef CONFIG_NRFX_DPPI
 #define NRFX_DPPI_ENABLED 1
 #endif
diff --git a/modules/hal_nxp/CMakeLists.txt b/modules/hal_nxp/CMakeLists.txt
index c338728c19a..81ea3f1a9d2 100644
--- a/modules/hal_nxp/CMakeLists.txt
+++ b/modules/hal_nxp/CMakeLists.txt
@@ -1,20 +1,12 @@
 #
 # Copyright (c) 2021 Linaro, Limited
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
 
 if(CONFIG_HAS_MCUX OR CONFIG_HAS_IMX_HAL OR CONFIG_HAS_NXP_S32_HAL)
-  add_subdirectory(${ZEPHYR_CURRENT_MODULE_DIR} hal_nxp)
-  add_subdirectory_ifdef(CONFIG_USB_DEVICE_DRIVER usb)
-  add_subdirectory_ifdef(CONFIG_UDC_DRIVER usb)
-
-  zephyr_sources_ifdef(CONFIG_PWM_MCUX_CTIMER ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/ctimer/fsl_ctimer.c)
-  zephyr_include_directories_ifdef(CONFIG_PWM_MCUX_CTIMER
-    ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/ctimer/)
-  zephyr_include_directories(.)
-
+  zephyr_library()
   zephyr_compile_definitions_ifdef(CONFIG_CAN_MCUX_FLEXCAN
     FLEXCAN_WAIT_TIMEOUT=${CONFIG_CAN_MCUX_FLEXCAN_WAIT_TIMEOUT})
 
@@ -29,9 +21,16 @@ if(CONFIG_HAS_MCUX OR CONFIG_HAS_IMX_HAL OR CONFIG_HAS_NXP_S32_HAL)
 
   zephyr_compile_definitions_ifdef(CONFIG_ETH_NXP_IMX_NETC FSL_ETH_ENABLE_CACHE_CONTROL=1)
 
-  add_subdirectory_ifdef(CONFIG_BT_H4_NXP_CTLR bt_controller)
-
   if(CONFIG_I2S_MCUX_SAI)
     zephyr_compile_definitions(MCUX_SDK_SAI_ALLOW_NULL_FIFO_WATERMARK=1)
   endif()
 endif()
+
+if(CONFIG_HAS_NXP_S32_HAL)
+  add_subdirectory(s32)
+else()
+  add_subdirectory_ifdef(CONFIG_HAS_IMX_HAL imx)
+  add_subdirectory_ifdef(CONFIG_HAS_MCUX mcux)
+endif()
+
+add_subdirectory(${ZEPHYR_CURRENT_MODULE_DIR}/zephyr/src hal_nxp)
diff --git a/modules/hal_nxp/Kconfig b/modules/hal_nxp/Kconfig
index 4f055faa07d..2aa8aa38aa6 100644
--- a/modules/hal_nxp/Kconfig
+++ b/modules/hal_nxp/Kconfig
@@ -1,8 +1,13 @@
 #
 # Copyright (c) 2021 Linaro, Limited
+# Copyright 2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
-#
 
-config MCUX_ACMP
-	bool "Include ACMP driver from MCUX SDK"
+
+config ZEPHYR_HAL_NXP_MODULE
+	bool
+
+rsource "imx/Kconfig.imx"
+rsource "s32/Kconfig.nxp_s32"
+rsource "mcux/Kconfig.mcux"
diff --git a/modules/hal_nxp/bt_controller/CMakeLists.txt b/modules/hal_nxp/bt_controller/CMakeLists.txt
deleted file mode 100644
index af3678364d3..00000000000
--- a/modules/hal_nxp/bt_controller/CMakeLists.txt
+++ /dev/null
@@ -1,21 +0,0 @@
-#
-# Copyright 2024 NXP
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-
-set(hal_nxp_dir           ${ZEPHYR_HAL_NXP_MODULE_DIR})
-set(hal_nxp_blobs_dir     ${hal_nxp_dir}/zephyr/blobs)
-set(blob_gen_file         ${ZEPHYR_BINARY_DIR}/include/generated/bt_nxp_ctlr_fw.h)
-
-if(CONFIG_BT_NXP_NW612)
-    set(blob_file ${hal_nxp_blobs_dir}/iw612/uart_nw61x_se.h)
-endif()
-
-if (NOT DEFINED blob_file)
-    message(FATAL_ERROR "Unsupported controller. Please select a BT conntroller, refer to ./driver/bluetooth/hci/Kconfig.nxp")
-endif()
-
-zephyr_blobs_verify(FILES ${blob_file} REQUIRED)
-
-configure_file(${blob_file} ${blob_gen_file} COPYONLY)
diff --git a/modules/hal_nxp/imx/CMakeLists.txt b/modules/hal_nxp/imx/CMakeLists.txt
new file mode 100644
index 00000000000..e41777c906b
--- /dev/null
+++ b/modules/hal_nxp/imx/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Translate the SoC name and part number into the imx device and cpu
+# name respectively.
+string(TOUPPER ${CONFIG_SOC} IMX_DEVICE)
+
+# Build imx drivers and utilities that can be used for multiple SoC's.
+add_subdirectory(${ZEPHYR_CURRENT_MODULE_DIR}/imx/drivers hal_nxp/imx/drivers)
+add_subdirectory(${ZEPHYR_CURRENT_MODULE_DIR}/imx/devices hal_nxp/imx/devices)
+add_subdirectory(${ZEPHYR_CURRENT_MODULE_DIR}/imx/devices/${IMX_DEVICE} hal_nxp/imx/devices/soc)
diff --git a/modules/Kconfig.imx b/modules/hal_nxp/imx/Kconfig.imx
similarity index 100%
rename from modules/Kconfig.imx
rename to modules/hal_nxp/imx/Kconfig.imx
diff --git a/modules/hal_nxp/mcux/CMakeLists.txt b/modules/hal_nxp/mcux/CMakeLists.txt
new file mode 100644
index 00000000000..07ba1fccd11
--- /dev/null
+++ b/modules/hal_nxp/mcux/CMakeLists.txt
@@ -0,0 +1,187 @@
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+set(MCUX_SDK_PROJECT_NAME ${ZEPHYR_CURRENT_LIBRARY})
+
+if(CONFIG_SOC_LPC11U66
+    OR CONFIG_SOC_LPC11U68
+    OR CONFIG_SOC_LPC54114
+    OR CONFIG_SOC_MIMX8ML8_A53
+    OR CONFIG_SOC_MIMX8ML8_ADSP
+    OR CONFIG_SOC_MIMX8MM6_A53
+    OR CONFIG_SOC_MIMX8MN6_A53
+    OR CONFIG_SOC_MIMX8QM6
+    OR CONFIG_SOC_MIMX8QX6
+    OR CONFIG_SOC_MIMX8UD7_ADSP
+    OR CONFIG_SOC_MIMX9352_A55
+    OR CONFIG_SOC_MIMX9596_A55
+    OR CONFIG_SOC_MIMX9596_M7
+    OR CONFIG_SOC_MK22F12
+    OR CONFIG_SOC_MK64F12
+    OR CONFIG_SOC_MK66F18
+    OR CONFIG_SOC_MK80F25615
+    OR CONFIG_SOC_MK82F25615
+    OR CONFIG_SOC_MKE14F16
+    OR CONFIG_SOC_MKE16F16
+    OR CONFIG_SOC_MKE18F16
+    OR CONFIG_SOC_MKL25Z4
+    OR CONFIG_SOC_MKV56F24
+    OR CONFIG_SOC_MKV58F24
+    OR CONFIG_SOC_MKW22D5
+    OR CONFIG_SOC_MKW24D5
+    OR CONFIG_SOC_MKW40Z4
+    OR CONFIG_SOC_MKW41Z4
+    OR CONFIG_SOC_MIMX9131
+    )
+
+    set (CONFIG_SOC_SDKNG_UNSUPPORTED ON)
+
+endif()
+
+# Translate the SoC name and part number into the mcux device and cpu
+# name respectively.
+# When this code completes, the following variables will be defined:
+# MCUX_DEVICE: SOC name, suffixed by core name when using a dual core part.
+#              Example: MIMXRT595S_cm33, or LPC55S36
+# MCUX_CPU: "CPU"+ SOC part number, followed by core name when using a dual core part.
+#              Example: CPU_MIMXRT595SFAWC_cm33, or  CPU_LPC55S36JBD100
+# MCU_DEVICE_PATH: SOC name without core suffix. Must match the name of the
+#              folder in MCUX HAL. IE MIMXRT595S, or LPC55S36
+
+if(NOT HWMv2)
+  # Include HWMv1 logic for MCUX variables
+  include(${CMAKE_CURRENT_LIST_DIR}/hwmv1.cmake)
+else()
+  string(TOUPPER ${CONFIG_SOC} MCUX_DEVICE_PATH)
+  string(TOUPPER ${CONFIG_SOC} MCUX_DEVICE)
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER})
+
+  if(DEFINED CONFIG_MCUX_CORE_SUFFIX)
+    string(APPEND MCUX_DEVICE ${CONFIG_MCUX_CORE_SUFFIX})
+    string(APPEND MCUX_CPU ${CONFIG_MCUX_CORE_SUFFIX})
+  endif()
+endif()
+
+if(DEFINED CONFIG_SOC_SDKNG_UNSUPPORTED)
+  zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/devices/${MCUX_DEVICE_PATH})
+  zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/devices/${MCUX_DEVICE_PATH}/drivers)
+
+  # include CMSIS of mcux-sdk for Cortex-A
+  if(CONFIG_CPU_CORTEX_A)
+    zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/CMSIS/Core_AArch64/Include)
+  endif()
+
+  # The mcux uses the cpu name to expose SoC-specific features
+  # of a given peripheral. For example, the UART peripheral may be
+  # instantiated with/without a hardware FIFO, and the size of that
+  # FIFO may be different for each instance in a given SoC. See
+  # fsl_device_registers.h and ${MCUX_DEVICE}_features.h
+  zephyr_compile_definitions(${MCUX_CPU})
+
+  # Build mcux device-specific objects. Although it is not normal
+  # practice, drilling down like this avoids the need for repetitive
+  # build scripts for every mcux device.
+  zephyr_library_sources(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/devices/${MCUX_DEVICE_PATH}/drivers/fsl_clock.c)
+
+  if(${MCUX_DEVICE} MATCHES "LPC")
+    zephyr_library_sources(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/devices/${MCUX_DEVICE_PATH}/drivers/fsl_power.c)
+    zephyr_library_sources(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/devices/${MCUX_DEVICE_PATH}/drivers/fsl_reset.c)
+  endif()
+
+  zephyr_library_sources_ifdef(CONFIG_SOC_LPC54114_M4
+    ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/devices/${MCUX_DEVICE_PATH}/gcc/startup_LPC54114_cm4.S
+    )
+
+  # Include middleware/usb
+  if(CONFIG_UDC_DRIVER OR CONFIG_USB_DEVICE_DRIVER)
+    if(CONFIG_DT_HAS_NXP_USBPHY_ENABLED)
+      zephyr_include_directories(${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/middleware/mcux-sdk-middleware-usb/phy)
+    endif()
+    # Include usb required header file.
+    zephyr_include_directories(${CMAKE_CURRENT_LIST_DIR}/mcux_sdk_ng/middleware)
+  endif()
+
+  # Include middleware/bt_controller.cmake
+  if(CONFIG_BT_H4_NXP_CTLR)
+    include(${CMAKE_CURRENT_LIST_DIR}/mcux_sdk_ng/middleware/bt_controller.cmake)
+  endif()
+
+  add_subdirectory(${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/components ${CMAKE_CURRENT_BINARY_DIR}/components)
+
+  # Include Entry cmake component
+  add_subdirectory(mcux-sdk)
+
+else() # CONFIG_SOC_SDKNG_UNSUPPORTED
+
+ add_subdirectory(mcux-sdk-ng)
+
+endif() # CONFIG_SOC_SDKNG_UNSUPPORTED
+
+enable_language(C ASM)
+
+zephyr_linker_sources(RWDATA
+  ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/quick_access_data.ld
+  )
+
+zephyr_linker_sources_ifdef(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT
+  RAMFUNC_SECTION
+  ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/quick_access_code.ld
+  )
+
+zephyr_linker_sources_ifdef(CONFIG_NOCACHE_MEMORY
+  NOCACHE_SECTION
+  ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/nocache.ld
+  )
+
+if(NOT CONFIG_ASSERT OR CONFIG_FORCE_NO_ASSERT)
+  zephyr_compile_definitions(NDEBUG) # squelch fsl_flexcan.c warning
+endif()
+
+zephyr_compile_definitions_ifdef(
+  CONFIG_PTP_CLOCK_NXP_ENET
+  ENET_ENHANCEDBUFFERDESCRIPTOR_MODE
+  )
+
+zephyr_compile_definitions_ifdef(
+  CONFIG_SOC_MIMX9596
+  FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL=1
+  )
+
+# note: if FSL_IRQSTEER_ENABLE_MASTER_INT is not
+# defined then it will automatically be defined
+# and set to 1 via fsl_irqsteer.h
+zephyr_library_compile_definitions_ifdef(CONFIG_NXP_IRQSTEER
+  FSL_IRQSTEER_ENABLE_MASTER_INT=0
+  )
+
+zephyr_library_compile_definitions_ifdef(CONFIG_DAI_NXP_SAI
+  MCUX_SDK_SAI_ALLOW_NULL_FIFO_WATERMARK=1
+  )
+
+zephyr_library_compile_definitions_ifdef(CONFIG_DAI_NXP_SAI
+  MCUX_SDK_SAI_DISABLE_IMPLICIT_CHAN_CONFIG=1
+  )
+
+zephyr_library_compile_definitions_ifdef(CONFIG_NOCACHE_MEMORY
+  __STARTUP_INITIALIZE_NONCACHEDATA
+  )
+
+zephyr_library_compile_definitions_ifdef(CONFIG_HAS_MCUX_CACHE
+  FSL_SDK_ENABLE_DRIVER_CACHE_CONTROL
+  )
+
+# MCUX_SDK and MCUX_SDK_NG share wireless/framework_5.3.3, wifi_nxp
+add_subdirectory_ifdef(CONFIG_IEEE802154_KW41Z
+  ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/middleware/wireless/framework_5.3.3
+  ${CMAKE_CURRENT_BINARY_DIR}/middleware/wireless/framework
+  )
+
+add_subdirectory_ifdef(CONFIG_WIFI_NXP
+  ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/middleware/wifi_nxp
+  ${CMAKE_CURRENT_BINARY_DIR}/middleware/wifi_nxp
+  )
+
+add_subdirectory(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/middleware
+  ${CMAKE_CURRENT_BINARY_DIR}/middleware
+  )
diff --git a/modules/Kconfig.mcux b/modules/hal_nxp/mcux/Kconfig.mcux
similarity index 96%
rename from modules/Kconfig.mcux
rename to modules/hal_nxp/mcux/Kconfig.mcux
index 47cb9743eb8..885a50d6d64 100644
--- a/modules/Kconfig.mcux
+++ b/modules/hal_nxp/mcux/Kconfig.mcux
@@ -4,13 +4,23 @@
 # Copyright 2024 NXP
 # SPDX-License-Identifier: Apache-2.0
 
+config SOC_SDKNG_UNSUPPORTED
+	bool
+	help
+	  Indicates whether the SDKNG supports the current SoC
+
+config MCUX_HW_DEVICE_CORE
+	string
+	help
+	  Indicates the current device core id
+
 config HAS_MCUX
 	bool
 	depends on SOC_FAMILY_KINETIS || SOC_FAMILY_NXP_IMX || SOC_FAMILY_LPC || \
 		SOC_FAMILY_NXP_S32 || SOC_FAMILY_NXP_IMXRT || SOC_FAMILY_NXP_RW || \
 		SOC_FAMILY_NXP_MCX
 
-if HAS_MCUX
+if	HAS_MCUX
 
 config MCUX_CORE_SUFFIX
 	string
@@ -18,11 +28,6 @@ config MCUX_CORE_SUFFIX
 	  String describing the core identifer used by MCUX SDK when using
 	  dual core parts
 
-config HAS_MCUX_12B1MSPS_SAR
-	bool
-	help
-	  Set if the 12B1MSPS SAR ADC module is present in the SoC.
-
 config HAS_MCUX_ADC12
 	bool
 	help
@@ -359,10 +364,10 @@ config HAS_MCUX_ADC_ETC
 	  Set if the ADC External Trigger Control module is present
 	  on the SoC.
 
-config HAS_MCUX_XBARA
+config HAS_MCUX_XCACHE
 	bool
 	help
-	  Set if the XBARA module is present on the SoC.
+	  Set if the XCACHE module is present on the SoC.
 
 config HAS_NXP_MONOLITHIC_NBU
 	bool
diff --git a/modules/hal_nxp/mcux/hwmv1.cmake b/modules/hal_nxp/mcux/hwmv1.cmake
new file mode 100644
index 00000000000..d95a18ed9dd
--- /dev/null
+++ b/modules/hal_nxp/mcux/hwmv1.cmake
@@ -0,0 +1,50 @@
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Get MCUX_DEVICE and MCUX_DEVICE_PATH from CONFIG_SOC
+# For example, if CONFIG_SOC=mimx8ml8_ca53, then MCUX_DEVICE=MIMX8ML8_ca53
+# and MCUX_DEVICE_PATH=MIMX8ML8
+string(FIND ${CONFIG_SOC} "_" pos)
+if(pos GREATER -1)
+  string(REPLACE "_" ";" MCUX_DEVICE_TMP ${CONFIG_SOC})
+  list(GET MCUX_DEVICE_TMP 0 MCUX_DEVICE_SOC)
+  list(GET MCUX_DEVICE_TMP 1 MCUX_DEVICE_CORE)
+  string(TOUPPER ${MCUX_DEVICE_SOC} MCUX_DEVICE_PATH)
+  set(MCUX_DEVICE ${MCUX_DEVICE_PATH}_${MCUX_DEVICE_CORE})
+else()
+  string(TOUPPER ${CONFIG_SOC} MCUX_DEVICE)
+  string(TOUPPER ${CONFIG_SOC} MCUX_DEVICE_PATH)
+endif()
+
+if("${MCUX_DEVICE}" STREQUAL "LPC51U68")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER})
+elseif("${MCUX_DEVICE}" STREQUAL "LPC54114")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm4)
+elseif("${MCUX_DEVICE}" STREQUAL "LPC54114_m0")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm0plus)
+elseif("${MCUX_DEVICE}" STREQUAL "LPC55S16")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER})
+elseif("${MCUX_DEVICE}" STREQUAL "LPC55S28")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER})
+elseif("${MCUX_DEVICE}" STREQUAL "LPC55S69_cpu0")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm33_core0)
+elseif("${MCUX_DEVICE}" STREQUAL "LPC55S69_cpu1")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm33_core1)
+elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT1052")
+  string(REGEX REPLACE "(.*)[AB]$" "CPU_\\1B" MCUX_CPU ${CONFIG_SOC_PART_NUMBER})
+elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT595S_cm33")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm33)
+elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT685S_cm33")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm33)
+elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT1176_cm4")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm4)
+elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT1176_cm7")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm7)
+elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT1166_cm4")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm4)
+elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT1166_cm7")
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm7)
+else()
+  set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER})
+endif()
diff --git a/modules/hal_nxp/mcux/mcux-sdk-ng/CMakeLists.txt b/modules/hal_nxp/mcux/mcux-sdk-ng/CMakeLists.txt
new file mode 100644
index 00000000000..56493f4b52b
--- /dev/null
+++ b/modules/hal_nxp/mcux/mcux-sdk-ng/CMakeLists.txt
@@ -0,0 +1,51 @@
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+set(MCUX_SDK_NG_DIR ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk-ng)
+# SdkRootDirPath is used by MCUX SDK NG CMake files.
+set(SdkRootDirPath ${MCUX_SDK_NG_DIR})
+
+# Functions for MCUX SDK cmake files
+include(${MCUX_SDK_NG_DIR}/cmake/extension/logging.cmake)
+include(${MCUX_SDK_NG_DIR}/cmake/extension/function.cmake)
+include(${MCUX_SDK_NG_DIR}/cmake/extension/basic_settings_lite.cmake)
+
+function(set_variable_ifdef feature_toggle variable)
+  if(${${feature_toggle}})
+    set(${variable} ON PARENT_SCOPE)
+  endif()
+endfunction()
+
+#specific operation to shared drivers
+if((DEFINED CONFIG_FLASH_MCUX_FLEXSPI_XIP) AND (DEFINED CONFIG_FLASH))
+  zephyr_code_relocate(FILES ${MCUX_SDK_NG_DIR}/drivers/flexspi/fsl_flexspi.c
+    LOCATION ${CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM}_TEXT)
+endif()
+
+if(CONFIG_NXP_RF_IMU AND CONFIG_SOC_SERIES_MCXW)
+  zephyr_compile_definitions(HAL_RPMSG_SELECT_ROLE=0U)
+endif()
+
+if((${MCUX_DEVICE} MATCHES "RW61") AND (NOT DEFINED CONFIG_MINIMAL_LIBC))
+  # Whenever building for RW61x without minimal LIBC, use optimized memcpy.
+  # This will avoid issues with unaligned access to peripheral RAM regions
+  # caused by the memcpy implementation in newlib
+  zephyr_library_sources(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk-ng/components/misc_utilities/fsl_memcpy.S)
+endif()
+
+include(middleware/middleware.cmake)
+include(components/components.cmake)
+include(drivers/drivers.cmake)
+include(device/device.cmake)
+
+# Expose the driver header include path, so that the shim driver can use them.
+get_target_property(MCUXSDK_INCLUDE_DIRS ${MCUX_SDK_PROJECT_NAME} INTERFACE_INCLUDE_DIRECTORIES)
+if(NOT MCUXSDK_INCLUDE_DIRS STREQUAL MCUXSDK_INCLUDE_DIRS-NOTFOUND)
+  zephyr_include_directories(${MCUXSDK_INCLUDE_DIRS})
+endif()
+
+get_target_property(MCUXSDK_COMPILE_DEFS ${MCUX_SDK_PROJECT_NAME} INTERFACE_COMPILE_DEFINITIONS)
+if(NOT MCUXSDK_COMPILE_DEFS STREQUAL MCUXSDK_COMPILE_DEFS-NOTFOUND)
+  zephyr_compile_definitions(${MCUXSDK_COMPILE_DEFS})
+endif()
diff --git a/modules/hal_nxp/mcux/mcux-sdk-ng/components/components.cmake b/modules/hal_nxp/mcux/mcux-sdk-ng/components/components.cmake
new file mode 100644
index 00000000000..8e2b4c105ec
--- /dev/null
+++ b/modules/hal_nxp/mcux/mcux-sdk-ng/components/components.cmake
@@ -0,0 +1,82 @@
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_WIFI_NXP)
+  set(CONFIG_MCUX_COMPONENT_component.wifi_bt_module.tx_pwr_limits ON)
+endif()
+
+if(CONFIG_NXP_FW_LOADER)
+  set(CONFIG_MCUX_COMPONENT_driver.conn_fwloader ON)
+  set(CONFIG_USE_component_osa_zephyr ON)
+endif()
+
+if(${MCUX_DEVICE} MATCHES "RW61")
+  set(CONFIG_USE_component_osa_zephyr ON)
+  if(CONFIG_NXP_FW_LOADER)
+    set(CONFIG_MCUX_COMPONENT_component.mflash_offchip ON)
+    set(CONFIG_MCUX_COMPONENT_driver.cache_cache64 ON)
+    set(CONFIG_MCUX_COMPONENT_driver.flexspi ON)
+  endif()
+endif()
+
+if(CONFIG_USB_DEVICE_DRIVER OR CONFIG_UDC_DRIVER OR CONFIG_BT)
+  set(CONFIG_USE_component_osa_zephyr ON)
+endif()
+
+if(CONFIG_NXP_RF_IMU)
+  if(CONFIG_SOC_SERIES_RW6XX)
+    set(CONFIG_MCUX_COMPONENT_driver.imu ON)
+    set(CONFIG_MCUX_COMPONENT_driver.gdma ON)
+    set(CONFIG_MCUX_COMPONENT_component.wireless_imu_adapter ON)
+    set(CONFIG_MCUX_PRJSEG_component.osa_interface.osa_macro_used ON)
+  elseif(CONFIG_SOC_SERIES_MCXW)
+    set(CONFIG_MCUX_COMPONENT_component.lists ON)
+    set(CONFIG_MCUX_COMPONENT_component.rpmsg_adapter ON)
+    zephyr_compile_definitions(HAL_RPMSG_SELECT_ROLE=0U)
+  endif()
+endif()
+
+if(CONFIG_SOC_SERIES_MCXW)
+  if(CONFIG_NET_L2_IEEE802154 OR CONFIG_NET_L2_OPENTHREAD)
+    set(CONFIG_MCUX_COMPONENT_component.lists ON)
+    set(CONFIG_USE_component_osa_zephyr ON)
+    zephyr_compile_definitions(OSA_USED=1U)
+  endif()
+endif()
+
+if(CONFIG_USE_component_osa_zephyr)
+  set(CONFIG_MCUX_COMPONENT_component.osa_template_config ON)
+  set(CONFIG_MCUX_COMPONENT_component.osa_zephyr ON)
+  set(CONFIG_MCUX_COMPONENT_component.osa_interface ON)
+endif()
+
+add_subdirectory(${MCUX_SDK_NG_DIR}/components/osa
+  ${CMAKE_CURRENT_BINARY_DIR}/osa
+  )
+
+add_subdirectory(${MCUX_SDK_NG_DIR}/components/wifi_bt_module
+  ${CMAKE_CURRENT_BINARY_DIR}/wifi_bt_module
+  )
+
+add_subdirectory(${MCUX_SDK_NG_DIR}/components/conn_fwloader
+  ${CMAKE_CURRENT_BINARY_DIR}/conn_fwloader
+  )
+
+add_subdirectory(${MCUX_SDK_NG_DIR}/components/lists
+  ${CMAKE_CURRENT_BINARY_DIR}/lists
+  )
+
+add_subdirectory(${MCUX_SDK_NG_DIR}/components/rpmsg
+  ${CMAKE_CURRENT_BINARY_DIR}/rpmsg
+  )
+
+add_subdirectory(${MCUX_SDK_NG_DIR}/components/imu_adapter
+  ${CMAKE_CURRENT_BINARY_DIR}/imu_adapter
+  )
+
+if(${MCUX_DEVICE} MATCHES "RW61")
+  add_subdirectory(${MCUX_SDK_NG_DIR}/components/flash/mflash/rdrw612bga
+    ${CMAKE_CURRENT_BINARY_DIR}/flash/mflash
+    )
+endif()
diff --git a/modules/hal_nxp/mcux/mcux-sdk-ng/device/device.cmake b/modules/hal_nxp/mcux/mcux-sdk-ng/device/device.cmake
new file mode 100644
index 00000000000..feb0df45670
--- /dev/null
+++ b/modules/hal_nxp/mcux/mcux-sdk-ng/device/device.cmake
@@ -0,0 +1,70 @@
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+string(TOUPPER ${CONFIG_SOC} MCUX_DEVICE)
+
+# Find the folder in mcux-sdk/devices that matches the device name
+message(STATUS "Looking for device ${MCUX_DEVICE} in ${SdkRootDirPath}/devices/")
+
+file(GLOB_RECURSE device_cmake_files ${SdkRootDirPath}/devices/*/CMakeLists.txt)
+foreach(file ${device_cmake_files})
+  get_filename_component(folder ${file} DIRECTORY)
+  get_filename_component(folder_name ${folder} NAME)
+  if(folder_name STREQUAL ${MCUX_DEVICE})
+    message(STATUS "Found device folder: ${folder}")
+    set(mcux_device_folder ${folder})
+    break()
+  endif()
+endforeach()
+
+if(NOT mcux_device_folder)
+  message(FATAL_ERROR "Device ${MCUX_DEVICE} not found in ${SdkRootDirPath}/devices/")
+endif()
+
+if(DEFINED CONFIG_MCUX_CORE_SUFFIX)
+  string (REGEX REPLACE "^_" "" core_id "${CONFIG_MCUX_CORE_SUFFIX}")
+endif()
+
+# Definitions to load device drivers
+set(CONFIG_MCUX_HW_DEVICE_CORE "${MCUX_DEVICE}${CONFIG_MCUX_CORE_SUFFIX}")
+
+# Define CPU macro
+zephyr_compile_definitions("CPU_${CONFIG_SOC_PART_NUMBER}${CONFIG_MCUX_CORE_SUFFIX}")
+
+if(CONFIG_SOC_SERIES_IMXRT10XX OR CONFIG_SOC_SERIES_IMXRT11XX)
+  set(CONFIG_MCUX_COMPONENT_device.boot_header ON)
+endif()
+
+set(CONFIG_MCUX_COMPONENT_device.system ON)
+set(CONFIG_MCUX_COMPONENT_device.CMSIS ON)
+set(CONFIG_MCUX_COMPONENT_driver.clock ON)
+
+if((NOT CONFIG_SOC_MIMXRT798S_HIFI1) AND (NOT CONFIG_SOC_MIMXRT798S_HIFI4))
+  set(CONFIG_MCUX_COMPONENT_driver.power ON)
+endif()
+
+set(CONFIG_MCUX_COMPONENT_driver.reset ON)
+set(CONFIG_MCUX_COMPONENT_driver.memory ON)
+
+# load device variables
+include(${mcux_device_folder}/variable.cmake)
+
+# Load device files
+mcux_add_cmakelists(${mcux_device_folder})
+
+# Workaround for fsl_flexspi_nor_boot link error, remove the one in SDK, use the Zephyr file.
+if(CONFIG_MCUX_COMPONENT_device.boot_header)
+
+  get_target_property(MCUXSDK_SOURCES ${MCUX_SDK_PROJECT_NAME} SOURCES)
+  list(FILTER MCUXSDK_SOURCES INCLUDE REGEX ".*fsl_flexspi_nor_boot\.c$")
+
+  if(NOT MCUXSDK_SOURCES STREQUAL "")
+    file(RELATIVE_PATH MCUXSDK_SOURCES ${SdkRootDirPath} ${MCUXSDK_SOURCES})
+    mcux_project_remove_source(
+      BASE_PATH ${SdkRootDirPath}
+      SOURCES ${MCUXSDK_SOURCES}
+    )
+  endif()
+
+endif()
diff --git a/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake b/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake
new file mode 100644
index 00000000000..86778d25db6
--- /dev/null
+++ b/modules/hal_nxp/mcux/mcux-sdk-ng/drivers/drivers.cmake
@@ -0,0 +1,268 @@
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# fsl_common driver
+zephyr_library_sources(${MCUX_SDK_NG_DIR}/drivers/common/fsl_common.c)
+zephyr_include_directories(${MCUX_SDK_NG_DIR}/drivers/common)
+
+if(CONFIG_ARCH STREQUAL "xtensa")
+  zephyr_library_sources(${MCUX_SDK_NG_DIR}/drivers/common/fsl_common_dsp.c)
+elseif(CONFIG_ARCH STREQUAL "arm")
+  zephyr_library_sources(${MCUX_SDK_NG_DIR}/drivers/common/fsl_common_arm.c)
+endif()
+
+set_variable_ifdef(CONFIG_HWINFO_MCUX_SRC_V2    CONFIG_MCUX_COMPONENT_driver.src_2)
+set_variable_ifdef(CONFIG_GPIO_MCUX_IGPIO       CONFIG_MCUX_COMPONENT_driver.igpio)
+set_variable_ifdef(CONFIG_ADC_MCUX_LPADC        CONFIG_MCUX_COMPONENT_driver.lpadc)
+set_variable_ifdef(CONFIG_COUNTER_MCUX_CTIMER   CONFIG_MCUX_COMPONENT_driver.ctimer)
+set_variable_ifdef(CONFIG_COUNTER_MCUX_LPC_RTC  CONFIG_MCUX_COMPONENT_driver.lpc_rtc)
+set_variable_ifdef(CONFIG_GLIKEY_MCUX_GLIKEY    CONFIG_MCUX_COMPONENT_driver.glikey)
+
+if(CONFIG_NXP_LP_FLEXCOMM)
+  set_variable_ifdef(CONFIG_I2C_MCUX_LPI2C      CONFIG_MCUX_COMPONENT_driver.lpflexcomm)
+  set_variable_ifdef(CONFIG_I2C_MCUX_LPI2C      CONFIG_MCUX_COMPONENT_driver.lpflexcomm_lpi2c)
+  set_variable_ifdef(CONFIG_UART_MCUX_LPUART    CONFIG_MCUX_COMPONENT_driver.lpflexcomm)
+  set_variable_ifdef(CONFIG_UART_MCUX_LPUART    CONFIG_MCUX_COMPONENT_driver.lpflexcomm_lpuart)
+  set_variable_ifdef(CONFIG_SPI_MCUX_LPSPI      CONFIG_MCUX_COMPONENT_driver.lpflexcomm)
+  set_variable_ifdef(CONFIG_SPI_MCUX_LPSPI      CONFIG_MCUX_COMPONENT_driver.lpflexcomm_lpspi)
+else()
+  set_variable_ifdef(CONFIG_I2C_MCUX_LPI2C      CONFIG_MCUX_COMPONENT_driver.lpi2c)
+  set_variable_ifdef(CONFIG_UART_MCUX_LPUART    CONFIG_MCUX_COMPONENT_driver.lpuart)
+  set_variable_ifdef(CONFIG_SPI_MCUX_LPSPI      CONFIG_MCUX_COMPONENT_driver.lpspi)
+endif()
+
+set_variable_ifdef(CONFIG_DMA_MCUX_LPC          CONFIG_MCUX_COMPONENT_driver.lpc_dma)
+set_variable_ifdef(CONFIG_GPIO_MCUX_LPC         CONFIG_MCUX_COMPONENT_driver.lpc_gpio)
+set_variable_ifdef(CONFIG_NXP_PINT              CONFIG_MCUX_COMPONENT_driver.pint)
+set_variable_ifdef(CONFIG_NXP_PINT              CONFIG_MCUX_COMPONENT_driver.inputmux)
+set_variable_ifdef(CONFIG_DMA_MCUX_SMARTDMA     CONFIG_MCUX_COMPONENT_driver.inputmux)
+set_variable_ifdef(CONFIG_I2C_MCUX_FLEXCOMM     CONFIG_MCUX_COMPONENT_driver.flexcomm)
+set_variable_ifdef(CONFIG_I2C_MCUX_FLEXCOMM     CONFIG_MCUX_COMPONENT_driver.flexcomm_i2c)
+set_variable_ifdef(CONFIG_I2S_MCUX_FLEXCOMM     CONFIG_MCUX_COMPONENT_driver.flexcomm)
+set_variable_ifdef(CONFIG_I2S_MCUX_FLEXCOMM     CONFIG_MCUX_COMPONENT_driver.flexcomm_i2s)
+set_variable_ifdef(CONFIG_SPI_MCUX_FLEXCOMM     CONFIG_MCUX_COMPONENT_driver.flexcomm)
+set_variable_ifdef(CONFIG_SPI_MCUX_FLEXCOMM     CONFIG_MCUX_COMPONENT_driver.flexcomm_spi)
+set_variable_ifdef(CONFIG_UART_MCUX_FLEXCOMM    CONFIG_MCUX_COMPONENT_driver.flexcomm)
+set_variable_ifdef(CONFIG_UART_MCUX_FLEXCOMM    CONFIG_MCUX_COMPONENT_driver.flexcomm_usart)
+set_variable_ifdef(CONFIG_MCUX_OS_TIMER         CONFIG_MCUX_COMPONENT_driver.ostimer)
+set_variable_ifdef(CONFIG_PWM_MCUX_SCTIMER      CONFIG_MCUX_COMPONENT_driver.sctimer)
+set_variable_ifdef(CONFIG_PWM_MCUX_CTIMER       CONFIG_MCUX_COMPONENT_driver.ctimer)
+set_variable_ifdef(CONFIG_SOC_FLASH_LPC         CONFIG_MCUX_COMPONENT_driver.flashiap)
+set_variable_ifdef(CONFIG_WDT_MCUX_WWDT         CONFIG_MCUX_COMPONENT_driver.wwdt)
+set_variable_ifdef(CONFIG_ADC_MCUX_ADC12        CONFIG_MCUX_COMPONENT_driver.adc12)
+set_variable_ifdef(CONFIG_ADC_MCUX_ADC16        CONFIG_MCUX_COMPONENT_driver.adc16)
+set_variable_ifdef(CONFIG_CAN_MCUX_FLEXCAN      CONFIG_MCUX_COMPONENT_driver.flexcan)
+set_variable_ifdef(CONFIG_CAN_MCUX_FLEXCAN_FD   CONFIG_MCUX_COMPONENT_driver.flexcan)
+set_variable_ifdef(CONFIG_COUNTER_NXP_PIT       CONFIG_MCUX_COMPONENT_driver.pit)
+set_variable_ifdef(CONFIG_COUNTER_MCUX_RTC      CONFIG_MCUX_COMPONENT_driver.rtc)
+set_variable_ifdef(CONFIG_DAC_MCUX_DAC          CONFIG_MCUX_COMPONENT_driver.dac)
+set_variable_ifdef(CONFIG_DAC_MCUX_DAC32        CONFIG_MCUX_COMPONENT_driver.dac32)
+set_variable_ifdef(CONFIG_DMA_MCUX_EDMA         CONFIG_MCUX_COMPONENT_driver.dmamux)
+set_variable_ifdef(CONFIG_DMA_MCUX_EDMA_V3      CONFIG_MCUX_COMPONENT_driver.dmamux)
+set_variable_ifdef(CONFIG_DMA_MCUX_EDMA         CONFIG_MCUX_COMPONENT_driver.edma)
+set_variable_ifdef(CONFIG_DMA_MCUX_EDMA_V3      CONFIG_MCUX_COMPONENT_driver.dma3)
+set_variable_ifdef(CONFIG_DMA_MCUX_EDMA_V4      CONFIG_MCUX_COMPONENT_driver.edma4)
+set_variable_ifdef(CONFIG_ENTROPY_MCUX_RNGA     CONFIG_MCUX_COMPONENT_driver.rnga)
+set_variable_ifdef(CONFIG_ENTROPY_MCUX_TRNG     CONFIG_MCUX_COMPONENT_driver.trng)
+set_variable_ifdef(CONFIG_ENTROPY_MCUX_CAAM     CONFIG_MCUX_COMPONENT_driver.caam)
+set_variable_ifdef(CONFIG_ETH_NXP_ENET          CONFIG_MCUX_COMPONENT_driver.enet)
+set_variable_ifdef(CONFIG_ETH_NXP_IMX_NETC      CONFIG_MCUX_COMPONENT_driver.netc)
+set_variable_ifdef(CONFIG_HAS_MCUX_SMC          CONFIG_MCUX_COMPONENT_driver.smc)
+set_variable_ifdef(CONFIG_I2C_MCUX              CONFIG_MCUX_COMPONENT_driver.i2c)
+set_variable_ifdef(CONFIG_I2C_NXP_II2C          CONFIG_MCUX_COMPONENT_driver.ii2c)
+set_variable_ifdef(CONFIG_I3C_MCUX              CONFIG_MCUX_COMPONENT_driver.i3c)
+set_variable_ifdef(CONFIG_SENSOR_MCUX_ACMP      CONFIG_MCUX_COMPONENT_driver.acmp)
+set_variable_ifdef(CONFIG_COMPARATOR_MCUX_ACMP  CONFIG_MCUX_COMPONENT_driver.acmp)
+set_variable_ifdef(CONFIG_PWM_MCUX_FTM          CONFIG_MCUX_COMPONENT_driver.ftm)
+set_variable_ifdef(CONFIG_PWM_MCUX_TPM          CONFIG_MCUX_COMPONENT_driver.tpm)
+set_variable_ifdef(CONFIG_COUNTER_MCUX_TPM      CONFIG_MCUX_COMPONENT_driver.tpm)
+set_variable_ifdef(CONFIG_PWM_MCUX_PWT          CONFIG_MCUX_COMPONENT_driver.pwt)
+set_variable_ifdef(CONFIG_COUNTER_MCUX_QTMR     CONFIG_MCUX_COMPONENT_driver.qtmr_1)
+set_variable_ifdef(CONFIG_PWM_MCUX_QTMR         CONFIG_MCUX_COMPONENT_driver.qtmr_1)
+set_variable_ifdef(CONFIG_SPI_MCUX_DSPI         CONFIG_MCUX_COMPONENT_driver.dspi)
+set_variable_ifdef(CONFIG_SPI_MCUX_ECSPI        CONFIG_MCUX_COMPONENT_driver.ecspi)
+set_variable_ifdef(CONFIG_MCUX_FLEXIO           CONFIG_MCUX_COMPONENT_driver.flexio)
+set_variable_ifdef(CONFIG_SPI_MCUX_FLEXIO       CONFIG_MCUX_COMPONENT_driver.flexio_spi)
+set_variable_ifdef(CONFIG_UART_MCUX             CONFIG_MCUX_COMPONENT_driver.uart)
+set_variable_ifdef(CONFIG_UART_MCUX_LPSCI       CONFIG_MCUX_COMPONENT_driver.lpsci)
+set_variable_ifdef(CONFIG_WDT_MCUX_WDOG         CONFIG_MCUX_COMPONENT_driver.wdog)
+set_variable_ifdef(CONFIG_WDT_MCUX_WDOG32       CONFIG_MCUX_COMPONENT_driver.wdog32)
+set_variable_ifdef(CONFIG_COUNTER_MCUX_GPT      CONFIG_MCUX_COMPONENT_driver.gpt)
+set_variable_ifdef(CONFIG_MCUX_GPT_TIMER        CONFIG_MCUX_COMPONENT_driver.gpt)
+set_variable_ifdef(CONFIG_DISPLAY_MCUX_ELCDIF   CONFIG_MCUX_COMPONENT_driver.elcdif)
+set_variable_ifdef(CONFIG_MCUX_PXP              CONFIG_MCUX_COMPONENT_driver.pxp)
+set_variable_ifdef(CONFIG_LV_USE_GPU_NXP_PXP    CONFIG_MCUX_COMPONENT_driver.pxp)
+set_variable_ifdef(CONFIG_GPIO_MCUX_RGPIO       CONFIG_MCUX_COMPONENT_driver.rgpio)
+set_variable_ifdef(CONFIG_I2S_MCUX_SAI          CONFIG_MCUX_COMPONENT_driver.sai)
+set_variable_ifdef(CONFIG_DAI_NXP_SAI           CONFIG_MCUX_COMPONENT_driver.sai)
+set_variable_ifdef(CONFIG_MEMC_MCUX_FLEXSPI     CONFIG_MCUX_COMPONENT_driver.flexspi)
+set_variable_ifdef(CONFIG_PWM_MCUX              CONFIG_MCUX_COMPONENT_driver.pwm)
+set_variable_ifdef(CONFIG_VIDEO_MCUX_CSI        CONFIG_MCUX_COMPONENT_driver.csi)
+set_variable_ifdef(CONFIG_WDT_MCUX_IMX_WDOG     CONFIG_MCUX_COMPONENT_driver.wdog01)
+set_variable_ifdef(CONFIG_WDT_MCUX_RTWDOG       CONFIG_MCUX_COMPONENT_driver.rtwdog)
+set_variable_ifdef(CONFIG_HAS_MCUX_RDC          CONFIG_MCUX_COMPONENT_driver.rdc)
+set_variable_ifdef(CONFIG_UART_MCUX_IUART       CONFIG_MCUX_COMPONENT_driver.iuart)
+set_variable_ifdef(CONFIG_ADC_MCUX_12B1MSPS_SAR CONFIG_MCUX_COMPONENT_driver.adc_12b1msps_sar)
+set_variable_ifdef(CONFIG_HWINFO_MCUX_SRC       CONFIG_MCUX_COMPONENT_driver.src)
+set_variable_ifdef(CONFIG_HWINFO_MCUX_SIM       CONFIG_MCUX_COMPONENT_driver.sim)
+set_variable_ifdef(CONFIG_HWINFO_MCUX_RCM       CONFIG_MCUX_COMPONENT_driver.rcm)
+set_variable_ifdef(CONFIG_IPM_MCUX              CONFIG_MCUX_COMPONENT_driver.mailbox)
+set_variable_ifdef(CONFIG_MBOX_NXP_MAILBOX      CONFIG_MCUX_COMPONENT_driver.mailbox)
+set_variable_ifdef(CONFIG_COUNTER_MCUX_SNVS     CONFIG_MCUX_COMPONENT_driver.snvs_hp)
+set_variable_ifdef(CONFIG_MCUX_LPTMR_TIMER      CONFIG_MCUX_COMPONENT_driver.lptmr)
+set_variable_ifdef(CONFIG_COUNTER_MCUX_LPTMR    CONFIG_MCUX_COMPONENT_driver.lptmr)
+set_variable_ifdef(CONFIG_IMX_USDHC	            CONFIG_MCUX_COMPONENT_driver.usdhc)
+set_variable_ifdef(CONFIG_MIPI_DSI_MCUX         CONFIG_MCUX_COMPONENT_driver.mipi_dsi_split)
+set_variable_ifdef(CONFIG_MIPI_DSI_MCUX_2L      CONFIG_MCUX_COMPONENT_driver.mipi_dsi)
+set_variable_ifdef(CONFIG_MCUX_SDIF             CONFIG_MCUX_COMPONENT_driver.sdif)
+set_variable_ifdef(CONFIG_ADC_MCUX_ETC          CONFIG_MCUX_COMPONENT_driver.adc_etc)
+set_variable_ifdef(CONFIG_MCUX_XBARA            CONFIG_MCUX_COMPONENT_driver.xbara)
+set_variable_ifdef(CONFIG_QDEC_MCUX             CONFIG_MCUX_COMPONENT_driver.enc)
+set_variable_ifdef(CONFIG_CRYPTO_MCUX_DCP       CONFIG_MCUX_COMPONENT_driver.dcp)
+set_variable_ifdef(CONFIG_DMA_MCUX_SMARTDMA     CONFIG_MCUX_COMPONENT_driver.smartdma)
+set_variable_ifdef(CONFIG_DAC_MCUX_LPDAC        CONFIG_MCUX_COMPONENT_driver.dac_1)
+set_variable_ifdef(CONFIG_NXP_IRQSTEER          CONFIG_MCUX_COMPONENT_driver.irqsteer)
+set_variable_ifdef(CONFIG_AUDIO_DMIC_MCUX       CONFIG_MCUX_COMPONENT_driver.dmic)
+set_variable_ifdef(CONFIG_DMA_NXP_SDMA          CONFIG_MCUX_COMPONENT_driver.sdma)
+set_variable_ifdef(CONFIG_ADC_MCUX_GAU          CONFIG_MCUX_COMPONENT_driver.cns_adc)
+set_variable_ifdef(CONFIG_DAC_MCUX_GAU          CONFIG_MCUX_COMPONENT_driver.cns_dac)
+set_variable_ifdef(CONFIG_DAI_NXP_ESAI          CONFIG_MCUX_COMPONENT_driver.esai)
+set_variable_ifdef(CONFIG_MCUX_LPCMP            CONFIG_MCUX_COMPONENT_driver.lpcmp)
+set_variable_ifdef(CONFIG_NXP_RF_IMU            CONFIG_MCUX_COMPONENT_driver.imu)
+set_variable_ifdef(CONFIG_TRDC_MCUX_TRDC        CONFIG_MCUX_COMPONENT_driver.trdc)
+set_variable_ifdef(CONFIG_S3MU_MCUX_S3MU        CONFIG_MCUX_COMPONENT_driver.s3mu)
+set_variable_ifdef(CONFIG_PINCTRL_NXP_PORT      CONFIG_MCUX_COMPONENT_driver.port)
+set_variable_ifdef(CONFIG_DMA_NXP_EDMA          CONFIG_MCUX_COMPONENT_driver.edma_soc_rev2)
+set_variable_ifdef(CONFIG_COUNTER_MCUX_SNVS_SRTC    CONFIG_MCUX_COMPONENT_driver.snvs_lp)
+set_variable_ifdef(CONFIG_DISPLAY_MCUX_DCNANO_LCDIF CONFIG_MCUX_COMPONENT_driver.lcdif)
+set_variable_ifdef(CONFIG_MIPI_DBI_NXP_DCNANO_LCDIF CONFIG_MCUX_COMPONENT_driver.lcdif)
+set_variable_ifdef(CONFIG_MIPI_DBI_NXP_FLEXIO_LCDIF CONFIG_MCUX_COMPONENT_driver.flexio_mculcd)
+set_variable_ifdef(CONFIG_VIDEO_MCUX_MIPI_CSI2RX    CONFIG_MCUX_COMPONENT_driver.mipi_csi2rx)
+set_variable_ifdef(CONFIG_ETH_NXP_IMX_NETC          CONFIG_MCUX_COMPONENT_driver.netc)
+set_variable_ifdef(CONFIG_ETH_NXP_IMX_NETC          CONFIG_MCUX_COMPONENT_driver.netc_switch)
+
+set_variable_ifdef(CONFIG_SOC_SERIES_IMXRT10XX    CONFIG_MCUX_COMPONENT_driver.ocotp)
+set_variable_ifdef(CONFIG_SOC_SERIES_IMXRT11XX    CONFIG_MCUX_COMPONENT_driver.ocotp)
+set_variable_ifdef(CONFIG_SOC_FAMILY_KINETIS      CONFIG_MCUX_COMPONENT_driver.port)
+set_variable_ifdef(CONFIG_SOC_SERIES_MCXW         CONFIG_MCUX_COMPONENT_driver.ccm32k)
+set_variable_ifdef(CONFIG_SOC_SERIES_IMXRT5XX     CONFIG_MCUX_COMPONENT_driver.iap3)
+
+if(CONFIG_SOC_MIMXRT1189)
+  set_variable_ifdef(CONFIG_ETH_NXP_IMX_NETC CONFIG_MCUX_COMPONENT_driver.netc_rt1180)
+  set_variable_ifdef(CONFIG_ETH_NXP_IMX_NETC CONFIG_MCUX_COMPONENT_driver.msgintr)
+elseif(CONFIG_SOC_MIMX9596)
+  set_variable_ifdef(CONFIG_ETH_NXP_IMX_NETC CONFIG_MCUX_COMPONENT_driver.netc_imx95)
+  set_variable_ifdef(CONFIG_ETH_NXP_IMX_NETC CONFIG_MCUX_COMPONENT_driver.msgintr)
+  set_variable_ifdef(CONFIG_ETH_NXP_IMX_NETC CONFIG_MCUX_COMPONENT_driver.irqsteer)
+endif()
+
+if(CONFIG_SOC_SERIES_MCXN OR CONFIG_SOC_SERIES_MCXA)
+  set(CONFIG_MCUX_COMPONENT_driver.mcx_spc ON)
+endif()
+
+if(CONFIG_BT_NXP AND CONFIG_SOC_SERIES_MCXW OR CONFIG_IEEE802154_MCXW)
+  set(CONFIG_MCUX_COMPONENT_driver.spc ON)
+endif()
+
+if(((${MCUX_DEVICE} MATCHES "MIMXRT1[0-9][0-9][0-9]") AND (NOT (CONFIG_SOC_MIMXRT1166_CM4 OR CONFIG_SOC_MIMXRT1176_CM4 OR CONFIG_SOC_MIMXRT1189_CM33))) OR
+    ((${MCUX_DEVICE} MATCHES "MIMX9596") AND CONFIG_SOC_MIMX9596_M7))
+  set_variable_ifdef(CONFIG_HAS_MCUX_CACHE		CONFIG_MCUX_COMPONENT_driver.cache_armv7_m7)
+elseif((${MCUX_DEVICE} MATCHES "MIMXRT(5|6)") OR (${MCUX_DEVICE} MATCHES "RW61") OR (${MCUX_DEVICE} MATCHES "MCXN.4."))
+  set_variable_ifdef(CONFIG_HAS_MCUX_CACHE		CONFIG_MCUX_COMPONENT_driver.cache_cache64)
+elseif((${MCUX_DEVICE} MATCHES "MK(28|66)") OR (${MCUX_DEVICE} MATCHES "MKE(14|16|18)") OR (CONFIG_SOC_MIMXRT1166_CM4) OR (CONFIG_SOC_MIMXRT1176_CM4))
+  set_variable_ifdef(CONFIG_HAS_MCUX_CACHE		CONFIG_MCUX_COMPONENT_driver.cache_lmem)
+endif()
+  set_variable_ifdef(CONFIG_HAS_MCUX_XCACHE		CONFIG_MCUX_COMPONENT_driver.cache_xcache)
+
+if((${MCUX_DEVICE} MATCHES "MIMX9596") OR (${MCUX_DEVICE} MATCHES "MIMX8UD7") OR (${MCUX_DEVICE} MATCHES "MIMXRT118"))
+  set_variable_ifdef(CONFIG_IPM_IMX	CONFIG_MCUX_COMPONENT_driver.mu1)
+  set_variable_ifdef(CONFIG_MBOX_NXP_IMX_MU	CONFIG_MCUX_COMPONENT_driver.mu1)
+else()
+  set_variable_ifdef(CONFIG_IPM_IMX	CONFIG_MCUX_COMPONENT_driver.mu)
+  set_variable_ifdef(CONFIG_MBOX_NXP_IMX_MU	CONFIG_MCUX_COMPONENT_driver.mu)
+endif()
+
+if(CONFIG_SOC_FAMILY_KINETIS OR CONFIG_SOC_SERIES_MCXC)
+  set_variable_ifdef(CONFIG_SOC_FLASH_MCUX CONFIG_MCUX_COMPONENT_driver.flash)
+endif()
+
+if(CONFIG_SOC_MK82F25615 OR CONFIG_SOC_MK64F12 OR CONFIG_SOC_MK66F18 OR
+    CONFIG_SOC_MKE14F16 OR CONFIG_SOC_MKE16F16 OR CONFIG_SOC_MKE18F16 OR
+    CONFIG_SOC_MK22F12)
+  set(CONFIG_MCUX_COMPONENT_driver.sysmpu ON)
+endif()
+
+if(CONFIG_SOC_SERIES_MCXW)
+  set_variable_ifdef(CONFIG_SOC_FLASH_MCUX CONFIG_MCUX_COMPONENT_driver.flash_k4)
+endif()
+
+if(CONFIG_SOC_SERIES_LPC51U68 OR CONFIG_SOC_SERIES_LPC54XXX)
+  set_variable_ifdef(CONFIG_SOC_FLASH_MCUX CONFIG_MCUX_COMPONENT_driver.iap)
+endif()
+
+if(CONFIG_SOC_SERIES_LPC51U68 OR CONFIG_SOC_SERIES_LPC54XXX)
+  set_variable_ifdef(CONFIG_ENTROPY_MCUX_RNG CONFIG_MCUX_COMPONENT_driver.rng)
+endif()
+
+if(CONFIG_SOC_SERIES_LPC55XXX)
+  set_variable_ifdef(CONFIG_ENTROPY_MCUX_RNG CONFIG_MCUX_COMPONENT_driver.rng_1)
+  if(CONFIG_SOC_LPC55S36)
+    set_variable_ifdef(CONFIG_SOC_FLASH_MCUX CONFIG_MCUX_COMPONENT_driver.romapi_flash)
+  else()
+    set_variable_ifdef(CONFIG_SOC_FLASH_MCUX CONFIG_MCUX_COMPONENT_driver.iap1)
+  endif()
+endif()
+
+if(CONFIG_SOC_SERIES_LPC51U68 OR CONFIG_SOC_SERIES_LPC54XXX OR CONFIG_SOC_SERIES_LPC55XXX)
+  set(CONFIG_MCUX_COMPONENT_driver.lpc_iocon ON)
+endif()
+
+if(CONFIG_SOC_LPC55S36)
+  set_variable_ifdef(CONFIG_ADC_MCUX_LPADC CONFIG_MCUX_COMPONENT_driver.vref_1)
+  set_variable_ifdef(CONFIG_DAC_MCUX_LPDAC CONFIG_MCUX_COMPONENT_driver.vref_1)
+endif()
+
+if(CONFIG_SOC_SERIES_IMXRT5XX OR CONFIG_SOC_SERIES_IMXRT6XX)
+  set(CONFIG_MCUX_COMPONENT_driver.lpc_iopctl ON)
+endif()
+
+if(CONFIG_SOC_SERIES_RW6XX)
+  set(CONFIG_MCUX_COMPONENT_driver.ocotp_rw61x ON)
+endif()
+
+if(CONFIG_SOC_SERIES_IMXRT10XX)
+  set_variable_ifdef(CONFIG_PM_MCUX_GPC CONFIG_MCUX_COMPONENT_driver.gpc_1)
+  set_variable_ifdef(CONFIG_PM_MCUX_DCDC CONFIG_MCUX_COMPONENT_driver.dcdc_1)
+  set_variable_ifdef(CONFIG_PM_MCUX_PMU CONFIG_MCUX_COMPONENT_driver.pmu)
+endif()
+
+if(CONFIG_SOC_SERIES_IMXRT11XX)
+  set(CONFIG_MCUX_COMPONENT_driver.romapi ON)
+  set(CONFIG_MCUX_COMPONENT_driver.anadig_pmu ON)
+  set(CONFIG_MCUX_COMPONENT_driver.pgmc ON)
+  set(CONFIG_MCUX_COMPONENT_driver.dcdc_2 ON)
+  set(CONFIG_MCUX_COMPONENT_driver.anatop_ai ON)
+  set(CONFIG_MCUX_COMPONENT_driver.gpc_xxx_ctrl ON)
+  set_variable_ifdef(CONFIG_VIDEO_MCUX_MIPI_CSI2RX CONFIG_MCUX_COMPONENT_driver.mipi_csi2rx_soc)
+endif()
+
+if(CONFIG_SOC_SERIES_IMXRT118X)
+  set(CONFIG_MCUX_COMPONENT_driver.ele_base_api ON)
+  set(CONFIG_MCUX_COMPONENT_driver.anadig_pmu_1 ON)
+  set_variable_ifdef(CONFIG_HWINFO_MCUX_SRC_V2 CONFIG_MCUX_COMPONENT_driver.src_3)
+  set_variable_ifdef(CONFIG_WDT_MCUX_RTWDOG	CONFIG_MCUX_COMPONENT_driver.src_3)
+endif()
+
+if(CONFIG_SOC_SERIES_MCXA)
+  set(CONFIG_MCUX_COMPONENT_driver.romapi ON)
+endif()
+
+if(CONFIG_SOC_SERIES_MCXN)
+  set_variable_ifdef(CONFIG_SOC_FLASH_MCUX CONFIG_MCUX_COMPONENT_driver.romapi_flashiap)
+endif()
+
+set_variable_ifdef(CONFIG_SOC_SERIES_MCXW CONFIG_MCUX_COMPONENT_driver.elemu)
+
+# Load all drivers
+mcux_load_all_cmakelists_in_directory(${SdkRootDirPath}/drivers)
diff --git a/modules/hal_nxp/mcux/mcux-sdk-ng/middleware/bt_controller/CMakeLists.txt b/modules/hal_nxp/mcux/mcux-sdk-ng/middleware/bt_controller/CMakeLists.txt
new file mode 100644
index 00000000000..9d17f2d353d
--- /dev/null
+++ b/modules/hal_nxp/mcux/mcux-sdk-ng/middleware/bt_controller/CMakeLists.txt
@@ -0,0 +1,25 @@
+#
+# Copyright 2024-2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+set(hal_nxp_dir           ${ZEPHYR_HAL_NXP_MODULE_DIR})
+set(hal_nxp_blobs_dir     ${hal_nxp_dir}/zephyr/blobs)
+set(blob_gen_file         ${ZEPHYR_BINARY_DIR}/include/generated/bt_nxp_ctlr_fw.h)
+
+if(CONFIG_BUILD_ONLY_NO_BLOBS)
+    set(blob_file src/no_blobs.h)
+elseif(CONFIG_BT_NXP_NW612)
+    set(blob_file ${hal_nxp_blobs_dir}/iw612/uart_nw61x_se.h)
+endif()
+
+if (NOT DEFINED blob_file)
+    message(FATAL_ERROR "Unsupported controller. Please select a BT conntroller, refer to ./driver/bluetooth/hci/Kconfig.nxp")
+endif()
+
+if(NOT CONFIG_BUILD_ONLY_NO_BLOBS)
+   zephyr_blobs_verify(FILES ${blob_file} REQUIRED)
+endif()
+
+configure_file(${blob_file} ${blob_gen_file} COPYONLY)
diff --git a/modules/hal_nxp/mcux/mcux-sdk-ng/middleware/bt_controller/src/no_blobs.h b/modules/hal_nxp/mcux/mcux-sdk-ng/middleware/bt_controller/src/no_blobs.h
new file mode 100644
index 00000000000..361d7420b87
--- /dev/null
+++ b/modules/hal_nxp/mcux/mcux-sdk-ng/middleware/bt_controller/src/no_blobs.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __UART_BT_FW_H__
+#define __UART_BT_FW_H__
+
+
+const unsigned char *bt_fw_bin;
+unsigned int bt_fw_bin_len;
+
+#endif /* __UART_BT_FW_H__ */
diff --git a/modules/hal_nxp/mcux/mcux-sdk-ng/middleware/middleware.cmake b/modules/hal_nxp/mcux/mcux-sdk-ng/middleware/middleware.cmake
new file mode 100644
index 00000000000..37b0b479abd
--- /dev/null
+++ b/modules/hal_nxp/mcux/mcux-sdk-ng/middleware/middleware.cmake
@@ -0,0 +1,43 @@
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_USB_DEVICE_DRIVER)
+  zephyr_include_directories(middleware)
+
+  set(CONFIG_MCUX_COMPONENT_middleware.usb.common_header ON)
+  set(CONFIG_MCUX_COMPONENT_middleware.usb.device.common_header ON)
+  set(CONFIG_MCUX_COMPONENT_middleware.usb.phy ON)
+
+  set_variable_ifdef(CONFIG_USB_DC_NXP_EHCI CONFIG_MCUX_COMPONENT_middleware.usb.device.ehci)
+  set_variable_ifdef(CONFIG_USB_DC_NXP_LPCIP3511 CONFIG_MCUX_COMPONENT_middleware.usb.device.ip3511fs)
+
+  # For soc.c build pass
+  zephyr_include_directories(.)
+  zephyr_include_directories(${MCUX_SDK_NG_DIR}/middleware/usb/device)
+  zephyr_include_directories(${MCUX_SDK_NG_DIR}/middleware/usb/phy)
+  zephyr_include_directories(${MCUX_SDK_NG_DIR}/middleware/usb/include)
+endif()
+
+if(CONFIG_UDC_DRIVER)
+  zephyr_include_directories(middleware)
+
+  set(CONFIG_MCUX_COMPONENT_middleware.usb.common_header ON)
+  set(CONFIG_MCUX_COMPONENT_middleware.usb.device.common_header ON)
+
+  set_variable_ifdef(CONFIG_DT_HAS_NXP_USBPHY_ENABLED CONFIG_MCUX_COMPONENT_middleware.usb.phy)
+  set_variable_ifdef(CONFIG_UDC_NXP_EHCI CONFIG_MCUX_COMPONENT_middleware.usb.device.ehci)
+  set_variable_ifdef(CONFIG_UDC_NXP_IP3511 CONFIG_MCUX_COMPONENT_middleware.usb.device.ip3511fs)
+
+  # For soc.c build pass
+  zephyr_include_directories(.)
+  zephyr_include_directories(${MCUX_SDK_NG_DIR}/middleware/usb/device)
+  zephyr_include_directories(${MCUX_SDK_NG_DIR}/middleware/usb/phy)
+  zephyr_include_directories(${MCUX_SDK_NG_DIR}/middleware/usb/include)
+endif()
+
+add_subdirectory(${MCUX_SDK_NG_DIR}/middleware/usb
+  ${CMAKE_CURRENT_BINARY_DIR}/usb
+)
+
+add_subdirectory_ifdef(CONFIG_BT_H4_NXP_CTLR ${CMAKE_CURRENT_LIST_DIR}/bt_controller)
diff --git a/modules/hal_nxp/usb/usb_device_config.h b/modules/hal_nxp/mcux/mcux-sdk-ng/middleware/usb_device_config.h
similarity index 100%
rename from modules/hal_nxp/usb/usb_device_config.h
rename to modules/hal_nxp/mcux/mcux-sdk-ng/middleware/usb_device_config.h
diff --git a/modules/hal_nxp/mcux/mcux-sdk/CMakeLists.txt b/modules/hal_nxp/mcux/mcux-sdk/CMakeLists.txt
new file mode 100644
index 00000000000..02f38951802
--- /dev/null
+++ b/modules/hal_nxp/mcux/mcux-sdk/CMakeLists.txt
@@ -0,0 +1,455 @@
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+list(APPEND CMAKE_MODULE_PATH
+    ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/devices/${MCUX_DEVICE_PATH}
+    ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/devices/${MCUX_DEVICE_PATH}/drivers
+    ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/common
+    ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/flexcomm
+    ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/lpflexcomm
+    ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/flexio
+    ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/dmamux
+    ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/components/osa
+    ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/components/lists
+)
+
+if(CONFIG_CPU_CORTEX_A)
+    list(APPEND CMAKE_MODULE_PATH
+        ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/CMSIS/Core_AArch64/Include
+    )
+else()
+    list(APPEND CMAKE_MODULE_PATH
+        ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/cache/armv7-m7
+        ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/CMSIS/Core/Include
+    )
+endif()
+
+function(include_ifdef feature_toggle module)
+  if(${${feature_toggle}})
+    include(${module})
+  endif()
+endfunction()
+
+function(include_driver_ifdef feature_toggle directory module)
+  if(${${feature_toggle}})
+    list(APPEND CMAKE_MODULE_PATH
+        ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/${directory}
+    )
+    zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/${directory})
+    include(${module})
+  endif()
+endfunction()
+
+message("Load components for ${MCUX_DEVICE}:")
+
+#specific operation to shared drivers
+if((DEFINED CONFIG_FLASH_MCUX_FLEXSPI_XIP) AND (DEFINED CONFIG_FLASH))
+  zephyr_code_relocate(FILES ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/flexspi/fsl_flexspi.c
+    LOCATION ${CONFIG_FLASH_MCUX_FLEXSPI_XIP_MEM}_TEXT)
+endif()
+
+# Required by all SCFW-based SoCs
+if (CONFIG_SOC_MIMX8QM6_ADSP OR CONFIG_SOC_MIMX8QX6_ADSP)
+    list(APPEND CMAKE_MODULE_PATH
+        ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/devices/${MCUX_DEVICE_PATH}/scfw_api
+    )
+    zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/devices/${MCUX_DEVICE_PATH}/scfw_api)
+    include(driver_scfw_api)
+endif()
+
+include(driver_common)
+
+#Include system_xxx file
+#This can be extended to other SoC series if needed
+if (DEFINED CONFIG_SOC_RESET_HOOK OR DEFINED CONFIG_SOC_SERIES_IMXRT6XX
+    OR DEFINED CONFIG_SOC_SERIES_LPC55XXX OR DEFINED CONFIG_SOC_SERIES_MCXN
+    OR DEFINED CONFIG_SOC_MCXW727C)
+  if (CONFIG_SOC_MIMXRT1166_CM4)
+    include(device_system_MIMXRT1166_cm4)
+  elseif (CONFIG_SOC_MIMXRT1166_CM7)
+    include(device_system_MIMXRT1166_cm7)
+  elseif (CONFIG_SOC_MIMXRT1176_CM4)
+    include(device_system_MIMXRT1176_cm4)
+  elseif (CONFIG_SOC_MIMXRT1176_CM7)
+    include(device_system_MIMXRT1176_cm7)
+  elseif (CONFIG_SOC_MIMXRT1189_CM33)
+    include(device_system_MIMXRT1189_cm33)
+  elseif (CONFIG_SOC_MIMXRT1189_CM7)
+    include(device_system_MIMXRT1189_cm7)
+  elseif (CONFIG_SOC_LPC55S69_CPU0)
+    include(device_system_LPC55S69_cm33_core0)
+  elseif (CONFIG_SOC_LPC55S69_CPU1)
+    include(device_system_LPC55S69_cm33_core1)
+  elseif (CONFIG_SOC_LPC54114_M4)
+    include(device_system_LPC54114_cm4)
+  elseif (CONFIG_SOC_LPC54114_M0)
+    include(device_system_LPC54114_cm0plus)
+  elseif (CONFIG_SOC_MCXN947_CPU0)
+    include(device_system_MCXN947_cm33_core0)
+  elseif (CONFIG_SOC_MCXN947_CPU1)
+    include(device_system_MCXN947_cm33_core1)
+  elseif (CONFIG_SOC_MCXN236)
+    include(device_system_MCXN236)
+  elseif (CONFIG_SOC_MIMXRT798S_CM33_CPU0)
+    include(device_system_MIMXRT798S_cm33_core0)
+  elseif (CONFIG_SOC_MIMXRT798S_CM33_CPU1)
+    include(device_system_MIMXRT798S_cm33_core1)
+  elseif (CONFIG_SOC_MCXW727C_CPU0)
+    include(device_system_MCXW727C_cm33_core0)
+  else()
+    include(device_system)
+  endif()
+endif()
+
+zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/common)
+
+#include shared drivers
+include_driver_ifdef(CONFIG_ADC_MCUX_LPADC		lpadc		driver_lpadc)
+include_driver_ifdef(CONFIG_COUNTER_MCUX_CTIMER		ctimer		driver_ctimer)
+include_driver_ifdef(CONFIG_COUNTER_MCUX_LPC_RTC	lpc_rtc		driver_lpc_rtc)
+include_driver_ifdef(CONFIG_DMA_MCUX_LPC		lpc_dma		driver_lpc_dma)
+include_driver_ifdef(CONFIG_GPIO_MCUX_LPC		lpc_gpio        driver_lpc_gpio)
+include_driver_ifdef(CONFIG_NXP_PINT			pint    	driver_pint)
+include_driver_ifdef(CONFIG_NXP_PINT			inputmux	driver_inputmux)
+include_driver_ifdef(CONFIG_I2C_MCUX_FLEXCOMM		flexcomm	driver_flexcomm)
+include_driver_ifdef(CONFIG_I2C_MCUX_FLEXCOMM		flexcomm/i2c	driver_flexcomm_i2c)
+include_driver_ifdef(CONFIG_I2S_MCUX_FLEXCOMM		flexcomm	driver_flexcomm)
+include_driver_ifdef(CONFIG_I2S_MCUX_FLEXCOMM		flexcomm/i2s	driver_flexcomm_i2s)
+include_driver_ifdef(CONFIG_MCUX_OS_TIMER		ostimer		driver_ostimer)
+include_driver_ifdef(CONFIG_PWM_MCUX_SCTIMER		sctimer		driver_sctimer)
+include_driver_ifdef(CONFIG_PWM_MCUX_CTIMER		ctimer		driver_ctimer)
+include_driver_ifdef(CONFIG_SOC_FLASH_LPC		flashiap	driver_flashiap)
+include_driver_ifdef(CONFIG_SPI_MCUX_FLEXCOMM		flexcomm	driver_flexcomm)
+include_driver_ifdef(CONFIG_SPI_MCUX_FLEXCOMM		flexcomm/spi	driver_flexcomm_spi)
+include_driver_ifdef(CONFIG_UART_MCUX_FLEXCOMM		flexcomm	driver_flexcomm)
+include_driver_ifdef(CONFIG_UART_MCUX_FLEXCOMM		flexcomm/usart	driver_flexcomm_usart)
+include_driver_ifdef(CONFIG_WDT_MCUX_WWDT		wwdt		driver_wwdt)
+include_driver_ifdef(CONFIG_ADC_MCUX_ADC12		adc12		driver_adc12)
+include_driver_ifdef(CONFIG_ADC_MCUX_ADC16		adc16		driver_adc16)
+include_driver_ifdef(CONFIG_CAN_MCUX_FLEXCAN		flexcan		driver_flexcan)
+include_driver_ifdef(CONFIG_CAN_MCUX_FLEXCAN_FD		flexcan		driver_flexcan)
+include_driver_ifdef(CONFIG_COUNTER_NXP_PIT		pit		driver_pit)
+include_driver_ifdef(CONFIG_COUNTER_MCUX_RTC		rtc		driver_rtc)
+include_driver_ifdef(CONFIG_DAC_MCUX_DAC		dac		driver_dac)
+include_driver_ifdef(CONFIG_DAC_MCUX_DAC32		dac32		driver_dac32)
+include_driver_ifdef(CONFIG_DMA_MCUX_EDMA		dmamux		driver_dmamux)
+include_driver_ifdef(CONFIG_DMA_MCUX_EDMA_V3		dmamux		driver_dmamux)
+include_driver_ifdef(CONFIG_DMA_MCUX_EDMA		edma		driver_edma)
+include_driver_ifdef(CONFIG_DMA_MCUX_EDMA_V3		dma3		driver_dma3)
+include_driver_ifdef(CONFIG_DMA_MCUX_EDMA_V4		edma4		driver_edma4)
+include_driver_ifdef(CONFIG_ENTROPY_MCUX_RNGA		rnga		driver_rnga)
+include_driver_ifdef(CONFIG_ENTROPY_MCUX_TRNG		trng		driver_trng)
+include_driver_ifdef(CONFIG_ENTROPY_MCUX_CAAM		caam		driver_caam)
+include_driver_ifdef(CONFIG_ETH_NXP_ENET		enet		driver_enet)
+include_driver_ifdef(CONFIG_ETH_NXP_IMX_NETC		netc		driver_netc)
+include_driver_ifdef(CONFIG_HAS_MCUX_SMC		smc		driver_smc)
+include_driver_ifdef(CONFIG_I2C_MCUX			i2c		driver_i2c)
+include_driver_ifdef(CONFIG_I2C_NXP_II2C		ii2c		driver_ii2c)
+if (CONFIG_NXP_LP_FLEXCOMM)
+include_driver_ifdef(CONFIG_I2C_MCUX_LPI2C		lpflexcomm	driver_lpflexcomm)
+include_driver_ifdef(CONFIG_I2C_MCUX_LPI2C		lpflexcomm/lpi2c	driver_lpi2c)
+else()
+include_driver_ifdef(CONFIG_I2C_MCUX_LPI2C		lpi2c		driver_lpi2c)
+endif()
+include_driver_ifdef(CONFIG_I3C_MCUX			i3c		driver_i3c)
+include_driver_ifdef(CONFIG_COMPARATOR_MCUX_ACMP	acmp		driver_acmp)
+include_driver_ifdef(CONFIG_SENSOR_MCUX_ACMP		acmp		driver_acmp)
+include_driver_ifdef(CONFIG_PWM_MCUX_FTM		ftm     	driver_ftm)
+include_driver_ifdef(CONFIG_PWM_MCUX_TPM		tpm		driver_tpm)
+include_driver_ifdef(CONFIG_PWM_MCUX_PWT		pwt		driver_pwt)
+include_driver_ifdef(CONFIG_PWM_MCUX_QTMR		qtmr_1		driver_qtmr_1)
+include_driver_ifdef(CONFIG_SPI_MCUX_DSPI		dspi		driver_dspi)
+include_driver_ifdef(CONFIG_SPI_MCUX_ECSPI		ecspi		driver_ecspi)
+if (CONFIG_NXP_LP_FLEXCOMM)
+include_driver_ifdef(CONFIG_SPI_MCUX_LPSPI		lpflexcomm	driver_lpflexcomm)
+include_driver_ifdef(CONFIG_SPI_MCUX_LPSPI		lpflexcomm/lpspi	driver_lpspi)
+else()
+include_driver_ifdef(CONFIG_SPI_MCUX_LPSPI		lpspi		driver_lpspi)
+endif()
+include_driver_ifdef(CONFIG_MCUX_FLEXIO			flexio		driver_flexio)
+include_driver_ifdef(CONFIG_SPI_MCUX_FLEXIO		flexio/spi	driver_flexio_spi)
+include_driver_ifdef(CONFIG_MIPI_DBI_NXP_FLEXIO_LCDIF	flexio/mculcd	driver_flexio_mculcd)
+include_driver_ifdef(CONFIG_UART_MCUX			uart		driver_uart)
+include_driver_ifdef(CONFIG_UART_MCUX_LPSCI		lpsci		driver_lpsci)
+if (CONFIG_NXP_LP_FLEXCOMM)
+include_driver_ifdef(CONFIG_UART_MCUX_LPUART		lpflexcomm	driver_lpflexcomm)
+include_driver_ifdef(CONFIG_UART_MCUX_LPUART		lpflexcomm/lpuart	driver_lpuart)
+else()
+include_driver_ifdef(CONFIG_UART_MCUX_LPUART		lpuart		driver_lpuart)
+endif()
+include_driver_ifdef(CONFIG_WDT_MCUX_WDOG		wdog		driver_wdog)
+include_driver_ifdef(CONFIG_WDT_MCUX_WDOG32		wdog32		driver_wdog32)
+include_driver_ifdef(CONFIG_COUNTER_MCUX_GPT		gpt		driver_gpt)
+include_driver_ifdef(CONFIG_COUNTER_MCUX_TPM		tpm		driver_tpm)
+include_driver_ifdef(CONFIG_MCUX_GPT_TIMER		gpt		driver_gpt)
+include_driver_ifdef(CONFIG_COUNTER_MCUX_QTMR		qtmr_1		driver_qtmr_1)
+include_driver_ifdef(CONFIG_DISPLAY_MCUX_ELCDIF		elcdif		driver_elcdif)
+include_driver_ifdef(CONFIG_DISPLAY_MCUX_DCNANO_LCDIF	lcdif		driver_lcdif)
+include_driver_ifdef(CONFIG_MCUX_PXP			pxp		driver_pxp)
+include_driver_ifdef(CONFIG_LV_USE_GPU_NXP_PXP		pxp		driver_pxp)
+include_driver_ifdef(CONFIG_GPIO_MCUX_IGPIO		igpio		driver_igpio)
+include_driver_ifdef(CONFIG_GPIO_MCUX_RGPIO		rgpio		driver_rgpio)
+include_driver_ifdef(CONFIG_I2S_MCUX_SAI		sai		driver_sai)
+include_driver_ifdef(CONFIG_DAI_NXP_SAI			sai		driver_sai)
+include_driver_ifdef(CONFIG_MEMC_MCUX_FLEXSPI		flexspi		driver_flexspi)
+include_driver_ifdef(CONFIG_PWM_MCUX			pwm		driver_pwm)
+include_driver_ifdef(CONFIG_VIDEO_MCUX_CSI		csi		driver_csi)
+include_driver_ifdef(CONFIG_VIDEO_MCUX_MIPI_CSI2RX	mipi_csi2rx     driver_mipi_csi2rx)
+include_driver_ifdef(CONFIG_WDT_MCUX_IMX_WDOG		wdog01		driver_wdog01)
+include_driver_ifdef(CONFIG_WDT_MCUX_RTWDOG		rtwdog		driver_rtwdog)
+include_driver_ifdef(CONFIG_DMA_MCUX_LPC		lpc_dma		driver_lpc_dma)
+include_driver_ifdef(CONFIG_MEMC_MCUX_FLEXSPI		flexspi		driver_flexspi)
+include_driver_ifdef(CONFIG_HAS_MCUX_RDC		rdc		driver_rdc)
+include_driver_ifdef(CONFIG_UART_MCUX_IUART		iuart		driver_iuart)
+include_driver_ifdef(CONFIG_ADC_MCUX_12B1MSPS_SAR	adc_12b1msps_sar	driver_adc_12b1msps_sar)
+include_driver_ifdef(CONFIG_HWINFO_MCUX_SRC		src		driver_src)
+include_driver_ifdef(CONFIG_HWINFO_MCUX_SIM		sim		driver_sim)
+include_driver_ifdef(CONFIG_HWINFO_MCUX_RCM		rcm		driver_rcm)
+include_driver_ifdef(CONFIG_IPM_MCUX			mailbox		driver_mailbox)
+include_driver_ifdef(CONFIG_MBOX_NXP_MAILBOX		mailbox		driver_mailbox)
+include_driver_ifdef(CONFIG_COUNTER_MCUX_SNVS		snvs_hp		driver_snvs_hp)
+include_driver_ifdef(CONFIG_COUNTER_MCUX_SNVS_SRTC	snvs_lp		driver_snvs_lp)
+include_driver_ifdef(CONFIG_COUNTER_MCUX_LPTMR		lptmr		driver_lptmr)
+include_driver_ifdef(CONFIG_MCUX_LPTMR_TIMER		lptmr		driver_lptmr)
+include_driver_ifdef(CONFIG_IMX_USDHC			usdhc		driver_usdhc)
+include_driver_ifdef(CONFIG_MIPI_DSI_MCUX		mipi_dsi_split	driver_mipi_dsi_split)
+include_driver_ifdef(CONFIG_MIPI_DSI_MCUX_2L		mipi_dsi	driver_mipi_dsi)
+include_driver_ifdef(CONFIG_MCUX_SDIF			sdif		driver_sdif)
+include_driver_ifdef(CONFIG_ADC_MCUX_ETC		adc_etc		driver_adc_etc)
+include_driver_ifdef(CONFIG_MCUX_XBARA			xbara		driver_xbara)
+include_driver_ifdef(CONFIG_MCUX_XBARB			xbarb		driver_xbarb)
+include_driver_ifdef(CONFIG_QDEC_MCUX			enc		driver_enc)
+include_driver_ifdef(CONFIG_CRYPTO_MCUX_DCP		dcp		driver_dcp)
+include_driver_ifdef(CONFIG_DMA_MCUX_SMARTDMA		smartdma	driver_lpc_smartdma)
+include_driver_ifdef(CONFIG_DMA_MCUX_SMARTDMA		inputmux	driver_inputmux)
+include_driver_ifdef(CONFIG_DAC_MCUX_LPDAC		dac_1		driver_dac_1)
+include_driver_ifdef(CONFIG_NXP_IRQSTEER		irqsteer	driver_irqsteer)
+include_driver_ifdef(CONFIG_AUDIO_DMIC_MCUX		dmic		driver_dmic)
+include_driver_ifdef(CONFIG_DMA_NXP_EDMA		edma_rev2	driver_edma_rev2)
+include_driver_ifdef(CONFIG_DMA_NXP_SDMA		sdma		driver_sdma)
+include_driver_ifdef(CONFIG_SOC_SERIES_MCXN		mcx_spc		driver_mcx_spc)
+include_driver_ifdef(CONFIG_SOC_SERIES_MCXA		mcx_spc		driver_mcx_spc)
+include_driver_ifdef(CONFIG_ADC_MCUX_GAU		cns_adc		driver_cns_adc)
+include_driver_ifdef(CONFIG_DAC_MCUX_GAU		cns_dac		driver_cns_dac)
+include_driver_ifdef(CONFIG_DAI_NXP_ESAI		esai		driver_esai)
+include_driver_ifdef(CONFIG_MCUX_LPCMP		        lpcmp		driver_lpcmp)
+include_driver_ifdef(CONFIG_NXP_RF_IMU			imu		driver_imu)
+include_driver_ifdef(CONFIG_TRDC_MCUX_TRDC              trdc            driver_trdc)
+include_driver_ifdef(CONFIG_S3MU_MCUX_S3MU              s3mu            driver_s3mu)
+include_driver_ifdef(CONFIG_DAI_NXP_MICFIL		pdm		driver_pdm)
+include_driver_ifdef(CONFIG_PINCTRL_NXP_PORT            port            driver_port)
+include_driver_ifdef(CONFIG_GLIKEY_MCUX_GLIKEY		glikey		driver_glikey)
+if(CONFIG_BT_NXP)
+include_driver_ifdef(CONFIG_SOC_SERIES_MCXW		spc		driver_spc)
+endif()
+
+if (${MCUX_DEVICE} MATCHES "MIMXRT1189")
+  include_driver_ifdef(CONFIG_ETH_NXP_IMX_NETC	netc/socs/imxrt1180	driver_netc_soc_imxrt1180)
+  include_driver_ifdef(CONFIG_ETH_NXP_IMX_NETC	msgintr			driver_msgintr)
+elseif (${MCUX_DEVICE} MATCHES "MIMX9596")
+  include_driver_ifdef(CONFIG_ETH_NXP_IMX_NETC	netc/socs/imx95		driver_netc_soc_imx95)
+  include_driver_ifdef(CONFIG_ETH_NXP_IMX_NETC	msgintr			driver_msgintr)
+  include_driver_ifdef(CONFIG_ETH_NXP_IMX_NETC	irqsteer		driver_irqsteer)
+endif()
+
+if (((${MCUX_DEVICE} MATCHES "MIMXRT1[0-9][0-9][0-9]") AND (NOT (CONFIG_SOC_MIMXRT1166_CM4 OR CONFIG_SOC_MIMXRT1176_CM4 OR CONFIG_SOC_MIMXRT1189_CM33))) OR
+    ((${MCUX_DEVICE} MATCHES "MIMX9596") AND CONFIG_SOC_MIMX9596_M7))
+  include_driver_ifdef(CONFIG_HAS_MCUX_CACHE		cache/armv7-m7	driver_cache_armv7_m7)
+elseif((${MCUX_DEVICE} MATCHES "MIMXRT(5|6|7)") OR (${MCUX_DEVICE} MATCHES "RW61") OR (${MCUX_DEVICE} MATCHES "MCXN.4."))
+  include_driver_ifdef(CONFIG_HAS_MCUX_CACHE		cache/cache64	driver_cache_cache64)
+elseif((${MCUX_DEVICE} MATCHES "MK(28|66)") OR (${MCUX_DEVICE} MATCHES "MKE(14|16|18)") OR (CONFIG_SOC_MIMXRT1166_CM4) OR (CONFIG_SOC_MIMXRT1176_CM4))
+  include_driver_ifdef(CONFIG_HAS_MCUX_CACHE		cache/lmem	driver_cache_lmem)
+endif()
+  include_driver_ifdef(CONFIG_HAS_MCUX_XCACHE		cache/xcache	driver_cache_xcache)
+
+if ((${MCUX_DEVICE} MATCHES "MIMX9596") OR (${MCUX_DEVICE} MATCHES "MIMX8UD7") OR (${MCUX_DEVICE} MATCHES "MIMXRT118"))
+  include_driver_ifdef(CONFIG_IPM_IMX			mu1		driver_mu1)
+  include_driver_ifdef(CONFIG_MBOX_NXP_IMX_MU		mu1		driver_mu1)
+else()
+  include_driver_ifdef(CONFIG_IPM_IMX			mu		driver_mu)
+  include_driver_ifdef(CONFIG_MBOX_NXP_IMX_MU		mu		driver_mu)
+endif()
+
+if(CONFIG_CPU_CORTEX_A)
+  include_driver_ifdef(CONFIG_HAS_MCUX_CACHE		cache/armv8-a	driver_cache_armv8a)
+endif()
+
+if (${MCUX_DEVICE} MATCHES "MIMXRT11[0-9][0-9]")
+   include_driver_ifdef(CONFIG_PM_MCUX_GPC		gpc_3		driver_gpc_3)
+   include_ifdef(CONFIG_HWINFO_MCUX_SRC_V2		driver_soc_src)
+   include_driver_ifdef(CONFIG_WDT_MCUX_RTWDOG		soc_src		driver_soc_src)
+elseif (${MCUX_DEVICE} MATCHES "MIMXRT10[0-9][0-9]")
+   include_driver_ifdef(CONFIG_PM_MCUX_GPC		gpc_1		driver_gpc_1)
+   include_driver_ifdef(CONFIG_PM_MCUX_DCDC		dcdc_1		driver_dcdc_1)
+   include_driver_ifdef(CONFIG_PM_MCUX_PMU		pmu		driver_pmu)
+endif()
+
+if((${MCUX_DEVICE} MATCHES "RW61") AND (NOT DEFINED CONFIG_MINIMAL_LIBC))
+	# Whenever building for RW61x without minimal LIBC, use optimized memcpy.
+	# This will avoid issues with unaligned access to peripheral RAM regions
+	# caused by the memcpy implementation in newlib
+	zephyr_library_sources(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/utilities/misc_utilities/fsl_memcpy.S)
+endif()
+
+
+if("${CONFIG_SOC_FAMILY}" STREQUAL "nxp_kinetis")
+
+  include_driver_ifdef(CONFIG_SOC_FLASH_MCUX		flash		driver_flash)
+
+  include(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/port/driver_port.cmake)
+  zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/port)
+
+  if(${MCUX_DEVICE} MATCHES "MK(80|82|64|66|M34|M35|E14F|E16F|E18F|22F12)")
+    include(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/sysmpu/driver_sysmpu.cmake)
+    zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/sysmpu)
+  endif()
+
+endif()
+
+if(CONFIG_SOC_SERIES_MCXC)
+    include_driver_ifdef(CONFIG_SOC_FLASH_MCUX		flash		driver_flash)
+elseif(CONFIG_SOC_SERIES_MCXA)
+    zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/mcxa_romapi)
+elseif(CONFIG_SOC_SERIES_MCXN)
+    include_driver_ifdef(CONFIG_SOC_FLASH_MCUX		mcx_romapi	driver_flashiap)
+    zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/mcx_romapi/flash)
+elseif(CONFIG_SOC_SERIES_MCXW)
+    include_driver_ifdef(CONFIG_SOC_FLASH_MCUX		flash_k4	driver_flash_k4)
+endif()
+
+# Temporary change to handle LPC SOC family name change between HWMv1 and HWMv2
+if(("${CONFIG_SOC_FAMILY}" STREQUAL "lpc") OR ("${CONFIG_SOC_FAMILY}" STREQUAL "nxp_lpc"))
+
+if ((${MCUX_DEVICE} MATCHES "LPC8[0-9][0-9]") OR (${MCUX_DEVICE} MATCHES "LPC5(1|4)"))
+  include_driver_ifdef(CONFIG_SOC_FLASH_MCUX		iap		driver_iap)
+  include_driver_ifdef(CONFIG_ENTROPY_MCUX_RNG		iap		driver_rng)
+elseif (${MCUX_DEVICE} MATCHES "LPC55")
+  if (${MCUX_DEVICE} MATCHES "LPC55S*3")
+   if(${CONFIG_SOC_FLASH_MCUX})
+      list(APPEND CMAKE_MODULE_PATH
+        ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/devices/LPC55S36/drivers
+      )
+      zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/devices/LPC55S36/drivers/flash)
+      include(driver_flashiap)
+    endif()
+  else()
+    include_driver_ifdef(CONFIG_SOC_FLASH_MCUX		iap1		driver_iap1)
+  endif()
+  include_driver_ifdef(CONFIG_ENTROPY_MCUX_RNG		rng_1		driver_rng_1)
+endif()
+
+if (${MCUX_DEVICE} MATCHES "LPC5")
+  include(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/lpc_iocon/driver_lpc_iocon.cmake)
+  zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/lpc_iocon)
+  if (${MCUX_DEVICE} MATCHES "LPC55S*3" AND (DEFINED CONFIG_ADC_MCUX_LPADC OR DEFINED CONFIG_DAC_MCUX_LPDAC))
+    include(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/vref_1/driver_vref_1.cmake)
+    zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/vref_1)
+  endif()
+elseif (${MCUX_DEVICE} MATCHES "LPC8")
+  include(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/lpc_iocon_lite/driver_lpc_iocon_lite.cmake)
+  zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/lpc_iocon_lite)
+endif()
+
+endif()
+
+if(${MCUX_DEVICE} MATCHES "MIMXRT(5|6)")
+  include(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/lpc_iopctl/driver_lpc_iopctl.cmake)
+  zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/lpc_iopctl)
+endif()
+
+if(CONFIG_SOC_FAMILY_NXP_IMXRT)
+  include_driver_ifdef(CONFIG_ETH_NXP_ENET ocotp driver_ocotp)
+endif()
+
+if (CONFIG_USB_DEVICE_DRIVER)
+  set(CONFIG_USE_component_osa_zephyr true)
+
+  list(APPEND CMAKE_MODULE_PATH
+    ${ZEPHYR_CURRENT_MODULE_DIR}/mcux-sdk/components/osa
+  )
+
+  list(APPEND CMAKE_MODULE_PATH
+    ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/middleware/mcux-sdk-middleware-usb
+  )
+  include(middleware_usb_phy)
+  include_ifdef(CONFIG_USB_DC_NXP_EHCI         middleware_usb_device_ehci)
+  include_ifdef(CONFIG_USB_DC_NXP_LPCIP3511    middleware_usb_device_ip3511fs)
+  include(set_component_osa)
+
+  zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/middleware/mcux-sdk-middleware-usb/device)
+  zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/middleware/mcux-sdk-middleware-usb/phy)
+  zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/middleware/mcux-sdk-middleware-usb/include)
+endif()
+
+if (CONFIG_UDC_DRIVER)
+  set(CONFIG_USE_component_osa_zephyr true)
+
+  list(APPEND CMAKE_MODULE_PATH
+    ${ZEPHYR_CURRENT_MODULE_DIR}/mcux-sdk/components/osa
+  )
+
+  list(APPEND CMAKE_MODULE_PATH
+    ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/middleware/mcux-sdk-middleware-usb
+  )
+  include_ifdef(CONFIG_DT_HAS_NXP_USBPHY_ENABLED  middleware_usb_phy)
+  include_ifdef(CONFIG_UDC_NXP_EHCI               middleware_usb_device_ehci)
+  include_ifdef(CONFIG_UDC_NXP_IP3511             middleware_usb_device_ip3511fs)
+  include(set_component_osa)
+
+  zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/middleware/mcux-sdk-middleware-usb/device)
+  zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/middleware/mcux-sdk-middleware-usb/phy)
+  zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/middleware/mcux-sdk-middleware-usb/include)
+endif()
+
+if(${MCUX_DEVICE} MATCHES "RW61")
+  set(CONFIG_USE_component_osa_zephyr true)
+  if(CONFIG_NXP_FW_LOADER)
+    list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/mcux-sdk/components/flash/mflash)
+    list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/mcux-sdk/components/flash/mflash/rdrw612bga)
+    list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/mcux-sdk/drivers/cache/cache64)
+    list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/mcux-sdk/drivers/flexspi)
+    include(component_mflash_rdrw610)
+  endif()
+endif()
+
+if(${CONFIG_USE_component_osa_zephyr})
+  zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR}/mcux-sdk/components/osa)
+endif()
+
+include_ifdef(CONFIG_USE_component_osa_zephyr set_component_osa)
+
+if(CONFIG_WIFI_NXP)
+    list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/mcux-sdk/components/wifi_bt_module)
+    include(component_wifi_bt_module_tx_pwr_limits)
+endif()
+
+if(CONFIG_NXP_FW_LOADER)
+    list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_SOURCE_DIR}/mcux-sdk/components/conn_fwloader)
+    include(driver_conn_fwloader)
+endif()
+
+if(CONFIG_NXP_RF_IMU)
+  if(CONFIG_SOC_SERIES_RW6XX)
+      list(APPEND CMAKE_MODULE_PATH
+          ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/components/rpmsg
+          ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/imu
+          ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/gdma
+      )
+    include(component_wireless_imu_adapter)
+  elseif(CONFIG_SOC_SERIES_MCXW)
+      zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/components/rpmsg)
+      zephyr_library_sources(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/components/rpmsg/fsl_adapter_rpmsg.c)
+      include(component_lists)
+      zephyr_compile_definitions(HAL_RPMSG_SELECT_ROLE=0U)
+  endif()
+endif()
+
+if(${MCUX_DEVICE} MATCHES "MCXW")
+  list(APPEND CMAKE_MODULE_PATH
+      ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/ccm32k
+  )
+
+  include(driver_ccm32k)
+  zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/ccm32k)
+endif()
diff --git a/modules/hal_nxp/s32/CMakeLists.txt b/modules/hal_nxp/s32/CMakeLists.txt
new file mode 100644
index 00000000000..f61365b42a1
--- /dev/null
+++ b/modules/hal_nxp/s32/CMakeLists.txt
@@ -0,0 +1,104 @@
+# Copyright 2022-2025 NXP
+
+# Set the SoC specific drivers and configuration to build
+if(HWMv2)
+  set(SOC_BASE ${CONFIG_SOC})
+else()
+  if(${CONFIG_SOC} STREQUAL "s32z27")
+    set(SOC_BASE "s32z270")
+  else()
+    set(SOC_BASE ${CONFIG_SOC})
+  endif()
+endif()
+
+add_subdirectory(${ZEPHYR_CURRENT_MODULE_DIR}/s32/drivers/${SOC_SERIES} hal_nxp/s32/drivers)
+add_subdirectory(${ZEPHYR_CURRENT_MODULE_DIR}/s32/soc/${SOC_BASE} hal_nxp/s32/soc)
+
+if(CONFIG_HAS_MCUX)
+
+  # This is an adaptation from hal_nxp/mcux/CMakeLists.txt entry CMake in order
+  # to build MCUX drivers together with RTD drivers for NXP S32 devices.
+  # MCUX don't have official support for NXP S32 devices but we are leveraging
+  # the existing shim drivers in Zephyr for those hardware blocks which are
+  # present in both NXP S32 and non NXP S32 devices.
+  #
+  # Glue code must be added for each device supported to build with MCUX. This
+  # can be found in hal_nxp/s32/mcux/devices:
+  # - s32/mcux/devices/${MCUX_DEVICE}/${MCUX_DEVICE}_device.h
+  #   redefine RTD module's peripheral access layers and its register masks to be
+  #   compatible with MCUX drivers for incompatible peripherals
+  # - s32/mcux/devices/${MCUX_DEVICE}/${MCUX_DEVICE}_features.h
+  #   define SoC module's features
+  # - s32/mcux/devices/${MCUX_DEVICE}/${MCUX_DEVICE}_glue_mcux.h
+  #   redefine RTD module's base addresses/pointers/interrupts to be compatible
+  #   with MCUX drivers
+  # - s32/mcux/devices/${MCUX_DEVICE}/fsl_device_registers.h
+  #   expose device features to the MCUX drivers
+  # - s32/mcux/devices/${MCUX_DEVICE}/drivers/fsl_clock.h
+  #   required by mcux/mcux-sdk/drivers/common/fsl_common_arm.h (at least)
+  # - s32/mcux/devices/${MCUX_DEVICE}/drivers/driver_reset.cmake
+  #   required by mcux/mcux-sdk/drivers/common/drivers_common.cmake
+  # - s32/mcux/devices/${MCUX_DEVICE}/device_system.cmake
+  #   required by mcux/hal_nxp.cmake
+  # - s32/mcux/devices/${MCUX_DEVICE}/device_CMSIS.cmake
+  #   required by mcux/mcux-sdk/drivers/common/drivers_common.cmake for non DSP
+  #   architectures
+
+  function(include_mcux_driver_ifdef feature_toggle directory module)
+    if(${${feature_toggle}})
+      list(APPEND CMAKE_MODULE_PATH
+          ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/${directory}
+      )
+      zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/${directory})
+      include(${module})
+      message(STATUS "directory ${directory} included")
+    endif()
+  endfunction()
+
+  set(MCUX_SDK_PROJECT_NAME ${ZEPHYR_CURRENT_LIBRARY})
+
+  # Translate the SoC name into the MCUX device
+  string(TOUPPER ${SOC_BASE} MCUX_DEVICE)
+
+  # This is normally done in mcux/hal_nxp.cmake, but we need to point to the
+  # path on this directory instead
+  list(APPEND CMAKE_MODULE_PATH
+    ${ZEPHYR_CURRENT_MODULE_DIR}/s32/mcux/devices/${MCUX_DEVICE}
+    ${ZEPHYR_CURRENT_MODULE_DIR}/s32/mcux/devices/${MCUX_DEVICE}/drivers
+  )
+
+  # MCUX uses the CPU name to expose SoC-specific features of a given peripheral
+  zephyr_compile_definitions(CPU_${MCUX_DEVICE})
+
+  # Clock control is supported through RTD, so disable it in the MCUX drivers
+  zephyr_compile_definitions(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL=1)
+
+  zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/s32/mcux/devices/${MCUX_DEVICE})
+  zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/s32/mcux/devices/${MCUX_DEVICE}/drivers)
+
+  zephyr_linker_sources(RWDATA
+    ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/quick_access_data.ld
+  )
+  zephyr_linker_sources_ifdef(CONFIG_ARCH_HAS_RAMFUNC_SUPPORT
+    RAMFUNC_SECTION
+    ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/quick_access_code.ld
+  )
+  zephyr_linker_sources_ifdef(CONFIG_NOCACHE_MEMORY
+    NOCACHE_SECTION
+    ${ZEPHYR_CURRENT_MODULE_DIR}/mcux/nocache.ld
+  )
+
+  # Entry CMake component for MCUX
+  include(${CMAKE_CURRENT_LIST_DIR}/../mcux/mcux-sdk/CMakeLists.txt)
+
+  if(${MCUX_DEVICE} MATCHES "S32K1")
+    zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/port)
+    include_mcux_driver_ifdef(CONFIG_PINCTRL port driver_port)
+
+    zephyr_include_directories(${ZEPHYR_CURRENT_MODULE_DIR}/mcux/mcux-sdk/drivers/sysmpu)
+    include_mcux_driver_ifdef(CONFIG_ARM_MPU sysmpu driver_sysmpu)
+
+    include_mcux_driver_ifdef(CONFIG_HAS_MCUX_CACHE cache/lmem driver_cache_lmem)
+  endif()
+
+endif()
diff --git a/modules/Kconfig.nxp_s32 b/modules/hal_nxp/s32/Kconfig.nxp_s32
similarity index 100%
rename from modules/Kconfig.nxp_s32
rename to modules/hal_nxp/s32/Kconfig.nxp_s32
diff --git a/modules/hal_nxp/usb/CMakeLists.txt b/modules/hal_nxp/usb/CMakeLists.txt
deleted file mode 100644
index da427e3601b..00000000000
--- a/modules/hal_nxp/usb/CMakeLists.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-#
-# Copyright (c) 2021,2024 NXP
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-zephyr_include_directories(.)
-if(CONFIG_DT_HAS_NXP_USBPHY_ENABLED)
-zephyr_include_directories(${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/middleware/mcux-sdk-middleware-usb/phy)
-endif()
diff --git a/modules/hal_rpi_pico/CMakeLists.txt b/modules/hal_rpi_pico/CMakeLists.txt
index 0898795a86d..046660a929a 100644
--- a/modules/hal_rpi_pico/CMakeLists.txt
+++ b/modules/hal_rpi_pico/CMakeLists.txt
@@ -4,6 +4,7 @@ include(ExternalProject)
 
 if(CONFIG_HAS_RPI_PICO)
   zephyr_library()
+  zephyr_library_compile_options(-std=gnu11)
 
   set(rp2_common_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/rp2_common)
   set(rp2xxx_dir ${ZEPHYR_HAL_RPI_PICO_MODULE_DIR}/src/${CONFIG_SOC_SERIES})
@@ -60,7 +61,6 @@ if(CONFIG_HAS_RPI_PICO)
     ${rp2_common_dir}/hardware_clocks/clocks.c
     ${rp2_common_dir}/hardware_pll/pll.c
     ${rp2_common_dir}/hardware_xosc/xosc.c
-    ${rp2_common_dir}/hardware_watchdog/watchdog.c
     ${rp2_common_dir}/hardware_sync_spin_lock/sync_spin_lock.c
     ${rp2_common_dir}/hardware_ticks/ticks.c
     ${rp2_common_dir}/pico_bootrom/bootrom.c
@@ -69,6 +69,7 @@ if(CONFIG_HAS_RPI_PICO)
 
   zephyr_include_directories(
     ${common_dir}/pico_base_headers/include
+    ${rp2_common_dir}/boot_bootrom_headers/include
     ${rp2_common_dir}/hardware_base/include
     ${rp2_common_dir}/hardware_clocks/include
     ${rp2_common_dir}/hardware_watchdog/include
@@ -82,6 +83,7 @@ if(CONFIG_HAS_RPI_PICO)
     ${rp2_common_dir}/hardware_ticks/include
     ${rp2_common_dir}/hardware_sync_spin_lock/include
     ${rp2_common_dir}/pico_bootrom/include
+    ${rp2_common_dir}/pico_flash/include
     ${rp2_common_dir}/pico_platform_compiler/include
     ${rp2_common_dir}/pico_platform_sections/include
     ${rp2_common_dir}/pico_platform_panic/include
@@ -102,9 +104,11 @@ if(CONFIG_HAS_RPI_PICO)
           ${rp2_common_dir}/hardware_uart/include)
 
   zephyr_library_sources_ifdef(CONFIG_PICOSDK_USE_FLASH
-          ${rp2_common_dir}/hardware_flash/flash.c)
+          ${rp2_common_dir}/hardware_flash/flash.c
+          ${rp2_common_dir}/hardware_xip_cache/xip_cache.c)
   zephyr_include_directories_ifdef(CONFIG_PICOSDK_USE_FLASH
-          ${rp2_common_dir}/hardware_flash/include)
+          ${rp2_common_dir}/hardware_flash/include
+          ${rp2_common_dir}/hardware_xip_cache/include)
 
   zephyr_include_directories_ifdef(CONFIG_PICOSDK_USE_PWM
           ${rp2_common_dir}/hardware_pwm/include)
diff --git a/modules/hal_silabs/CMakeLists.txt b/modules/hal_silabs/CMakeLists.txt
index 62d7ed54a15..29759a3f83e 100644
--- a/modules/hal_silabs/CMakeLists.txt
+++ b/modules/hal_silabs/CMakeLists.txt
@@ -1,4 +1,5 @@
 add_subdirectory_ifdef(CONFIG_SOC_FAMILY_SILABS_S0 gecko)
 add_subdirectory_ifdef(CONFIG_SOC_FAMILY_SILABS_S1 gecko)
 add_subdirectory_ifdef(CONFIG_SOC_FAMILY_SILABS_S2 simplicity_sdk)
+add_subdirectory_ifdef(CONFIG_SOC_FAMILY_SILABS_SIWX91X wiseconnect)
 add_subdirectory_ifdef(CONFIG_HAS_SILABS_SI32 si32)
diff --git a/modules/hal_silabs/Kconfig b/modules/hal_silabs/Kconfig
index b75796c432f..93dff37d753 100644
--- a/modules/hal_silabs/Kconfig
+++ b/modules/hal_silabs/Kconfig
@@ -12,8 +12,20 @@ config ZEPHYR_HAL_SILABS_MODULE_BLOBS
 config HAS_SILABS_GECKO
 	bool
 	select HAS_CMSIS_CORE
-	depends on SOC_FAMILY_SILABS_S0 || SOC_FAMILY_SILABS_S1 || SOC_FAMILY_SILABS_S2
+	depends on SOC_FAMILY_SILABS_S0 || SOC_FAMILY_SILABS_S1
+
+config HAS_SILABS_SISDK
+	bool
+	select HAS_CMSIS_CORE
+	depends on SOC_FAMILY_SILABS_S2
+
+config HAS_SILABS_WISECONNECT
+	bool
+	select HAS_CMSIS_CORE
+	depends on SOC_FAMILY_SILABS_SIWX91X
 
 config HAS_SILABS_SI32
 	bool
 	select HAS_CMSIS_CORE
+
+rsource "*/Kconfig"
diff --git a/modules/hal_silabs/simplicity_sdk/CMakeLists.txt b/modules/hal_silabs/simplicity_sdk/CMakeLists.txt
index 32bfac97074..04140171854 100644
--- a/modules/hal_silabs/simplicity_sdk/CMakeLists.txt
+++ b/modules/hal_silabs/simplicity_sdk/CMakeLists.txt
@@ -8,8 +8,10 @@
 # SPDX-License-Identifier: Apache-2.0
 
 set(EMLIB_DIR      ${ZEPHYR_HAL_SILABS_MODULE_DIR}/simplicity_sdk/platform/emlib)
+set(EMDRV_DIR      ${ZEPHYR_HAL_SILABS_MODULE_DIR}/simplicity_sdk/platform/emdrv)
 set(COMMON_DIR     ${ZEPHYR_HAL_SILABS_MODULE_DIR}/simplicity_sdk/platform/common)
 set(DEVICE_DIR     ${ZEPHYR_HAL_SILABS_MODULE_DIR}/simplicity_sdk/platform/Device)
+set(DRIVER_DIR     ${ZEPHYR_HAL_SILABS_MODULE_DIR}/simplicity_sdk/platform/driver)
 set(RADIO_DIR      ${ZEPHYR_HAL_SILABS_MODULE_DIR}/simplicity_sdk/platform/radio)
 set(SECURITY_DIR   ${ZEPHYR_HAL_SILABS_MODULE_DIR}/simplicity_sdk/platform/security)
 set(SERVICE_DIR    ${ZEPHYR_HAL_SILABS_MODULE_DIR}/simplicity_sdk/platform/service)
@@ -38,10 +40,13 @@ endfunction()
 
 if(CONFIG_SOC_GECKO_HAS_RADIO)
   zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_SILABS_S2
-    ${RADIO_DIR}/rail_lib/plugin/pa-conversions/efr32xg${SILABS_DEVICE_FAMILY_NUMBER}/config
     ${RADIO_DIR}/rail_lib/chip/efr32/efr32xg2x
   )
 
+  zephyr_compile_definitions(
+    SL_RAIL_UTIL_PA_CONFIG_HEADER="sl_rail_util_pa_config.h"
+  )
+
   zephyr_include_directories(
     ${RADIO_DIR}/rail_lib/common
     ${RADIO_DIR}/rail_lib/plugin/pa-conversions
@@ -52,12 +57,14 @@ if(CONFIG_SOC_GECKO_HAS_RADIO)
   zephyr_library_sources_ifdef(CONFIG_BT_SILABS_EFR32
     ${SECURITY_DIR}/sl_component/sl_protocol_crypto/src/sli_radioaes_management.c
     ${SECURITY_DIR}/sl_component/sl_protocol_crypto/src/sli_protocol_crypto_radioaes.c
+    ${SECURITY_DIR}/sl_component/sli_crypto/src/sl_crypto_s2.c
   )
 
   if(CONFIG_BT_SILABS_EFR32)
     # prebuilt libs
-    add_prebuilt_library(liblinklayer protocol/bluetooth/bgstack/ll/lib/libbluetooth_controller_efr32xg${SILABS_DEVICE_FAMILY_NUMBER}_gcc_release.a)
+    add_prebuilt_library(liblinklayer protocol/bluetooth/bgstack/ll/build/gcc/xg${SILABS_DEVICE_FAMILY_NUMBER}/release/liblinklayer.a)
     add_prebuilt_library(libbgcommon  protocol/bluetooth/bgcommon/lib/build/gcc/cortex-m33/bgcommon/release/libbgcommon.a)
+    zephyr_library_sources(src/sl_btctrl_hci_reset_shim.c)
 
     # link mbedTLS
     if(CONFIG_MBEDTLS)
@@ -92,6 +99,11 @@ zephyr_include_directories(
   ${DEVICE_DIR}/SiliconLabs/${SILABS_DEVICE_FAMILY}/Include
   ${COMMON_DIR}/config
   ${COMMON_DIR}/inc
+  ${DRIVER_DIR}/gpio/inc
+  ${EMDRV_DIR}/common/inc
+  ${EMDRV_DIR}/dmadrv/config/s2_8ch/
+  ${EMDRV_DIR}/dmadrv/inc
+  ${EMDRV_DIR}/dmadrv/inc/s2_signals/
   ${EMLIB_DIR}/inc
   ${PERIPHERAL_DIR}/inc
   ${SERVICE_DIR}/clock_manager/inc
@@ -100,20 +112,25 @@ zephyr_include_directories(
   ${SERVICE_DIR}/hfxo_manager/config
   ${SERVICE_DIR}/hfxo_manager/inc
   ${SERVICE_DIR}/hfxo_manager/src
+  ${SERVICE_DIR}/interrupt_manager/inc
   ${SERVICE_DIR}/memory_manager/inc
   ${SERVICE_DIR}/memory_manager/profiler/inc
   ${SERVICE_DIR}/power_manager/config
   ${SERVICE_DIR}/power_manager/inc
-  ${SERVICE_DIR}/power_manager/src
   ${SERVICE_DIR}/sleeptimer/config
   ${SERVICE_DIR}/sleeptimer/inc
   ${SERVICE_DIR}/sleeptimer/src
   ${SECURITY_DIR}/sl_component/sl_protocol_crypto/src
+  ${SECURITY_DIR}/sl_component/sli_crypto/inc
   ${BOARD_DIR}
 )
 
 zephyr_compile_definitions(
   ${SILABS_DEVICE_PART_NUMBER}
+  SL_CODE_COMPONENT_CLOCK_MANAGER=clock_manager
+  SL_CODE_COMPONENT_DEVICE_PERIPHERAL=peripheral
+  SL_CODE_COMPONENT_HAL_COMMON=hal_common
+  SL_CODE_COMPONENT_SYSTEM=system
 )
 
 zephyr_library_sources(
@@ -124,7 +141,6 @@ zephyr_library_sources(
   ${SERVICE_DIR}/clock_manager/src/sl_clock_manager_init.c
   ${SERVICE_DIR}/clock_manager/src/sl_clock_manager_init_hal_s2.c
   ${SERVICE_DIR}/device_manager/devices/sl_device_peripheral_hal_efr32xg${SILABS_DEVICE_FAMILY_NUMBER}.c
-  ${SERVICE_DIR}/device_manager/gpios/sl_device_gpio_common.c
   ${SERVICE_DIR}/device_manager/src/sl_device_clock.c
   ${SERVICE_DIR}/device_manager/src/sl_device_gpio.c
   ${SERVICE_DIR}/device_manager/src/sl_device_peripheral.c
@@ -147,6 +163,8 @@ if(CONFIG_SOC_SILABS_SLEEPTIMER)
   )
   zephyr_compile_definitions(
     SL_CATALOG_SLEEPTIMER_PRESENT
+    SL_CODE_COMPONENT_SLEEPTIMER=sleeptimer
+    SL_CODE_COMPONENT_HAL_SYSRTC=hal_sysrtc
   )
 endif()
 
@@ -164,11 +182,14 @@ endif()
 # Power Manager
 if(CONFIG_SOC_GECKO_PM_BACKEND_PMGR)
   zephyr_library_sources(
-    ${SERVICE_DIR}/power_manager/src/sl_power_manager.c
-    ${SERVICE_DIR}/power_manager/src/sl_power_manager_hal_s2.c
+    ${SERVICE_DIR}/power_manager/src/common/sl_power_manager_common.c
+    ${SERVICE_DIR}/power_manager/src/common/sl_power_manager_em4.c
+    ${SERVICE_DIR}/power_manager/src/sleep_loop/sl_power_manager.c
+    ${SERVICE_DIR}/power_manager/src/sleep_loop/sl_power_manager_hal_s2.c
   )
   zephyr_compile_definitions(
     SL_CATALOG_POWER_MANAGER_PRESENT
+    SL_CODE_COMPONENT_POWER_MANAGER=power_manager
   )
   zephyr_compile_definitions_ifdef(CONFIG_SOC_GECKO_RTCC
     SL_CATALOG_POWER_MANAGER_DEEPSLEEP_BLOCKING_HFXO_RESTORE_PRESENT
@@ -187,13 +208,32 @@ if(CONFIG_SOC_SILABS_HFXO_MANAGER)
 endif()
 
 zephyr_library_sources_ifdef(CONFIG_SOC_GECKO_DEV_INIT     ${COMMON_DIR}/src/sl_slist.c)
-zephyr_library_sources_ifdef(CONFIG_SOC_GECKO_CORE
-  ${EMLIB_DIR}/src/em_core.c
-  ${COMMON_DIR}/src/sl_core_cortexm.c
-)
+if(CONFIG_SOC_GECKO_CORE)
+  zephyr_library_sources_ifdef(CONFIG_SOC_GECKO_CORE
+    ${EMLIB_DIR}/src/em_core.c
+    ${COMMON_DIR}/src/sl_core_cortexm.c
+  )
+  zephyr_compile_definitions(
+    SL_CODE_COMPONENT_CORE=core
+  )
+endif()
+zephyr_library_sources_ifdef(CONFIG_SOC_SILABS_ACMP        ${EMLIB_DIR}/src/em_acmp.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_GECKO_CRYOTIMER    ${EMLIB_DIR}/src/em_cryotimer.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_GECKO_EMU          ${EMLIB_DIR}/src/em_emu.c)
-zephyr_library_sources_ifdef(CONFIG_SOC_GECKO_GPIO         ${EMLIB_DIR}/src/em_gpio.c)
+if(CONFIG_SOC_GECKO_GPIO)
+  zephyr_library_sources(
+    ${EMLIB_DIR}/src/em_gpio.c
+    ${DRIVER_DIR}/gpio/src/sl_gpio.c
+    ${PERIPHERAL_DIR}/src/sl_hal_gpio.c
+  )
+  zephyr_library_compile_definitions(
+    SL_CATALOG_GPIO_PRESENT
+    SL_CODE_COMPONENT_HAL_GPIO=hal_gpio
+  )
+endif()
+
+zephyr_library_sources_ifdef(CONFIG_SOC_GECKO_LDMA         ${EMDRV_DIR}/dmadrv/src/dmadrv.c)
+
 zephyr_library_sources_ifdef(CONFIG_SOC_GECKO_I2C          ${EMLIB_DIR}/src/em_i2c.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_GECKO_LETIMER      ${EMLIB_DIR}/src/em_letimer.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_GECKO_LEUART       ${EMLIB_DIR}/src/em_leuart.c)
@@ -211,22 +251,33 @@ zephyr_library_sources_ifdef(CONFIG_SOC_GECKO_WDOG         ${EMLIB_DIR}/src/em_w
 zephyr_include_directories_ifdef(CONFIG_SOC_GECKO_SE
   ${SECURITY_DIR}/sl_component/se_manager/src
   ${SECURITY_DIR}/sl_component/se_manager/inc
+  ${SECURITY_DIR}/sl_component/sli_psec_osal/inc
 )
 
 zephyr_library_sources_ifdef(CONFIG_SOC_GECKO_SE
-  ${EMLIB_DIR}/src/em_se.c
   ${SECURITY_DIR}/sl_component/se_manager/src/sl_se_manager.c
   ${SECURITY_DIR}/sl_component/se_manager/src/sl_se_manager_util.c
   ${SECURITY_DIR}/sl_component/se_manager/src/sli_se_manager_mailbox.c
 )
 
+zephyr_compile_definitions_ifdef(CONFIG_SOC_GECKO_SE
+  SL_CODE_COMPONENT_SE_MANAGER=se_manager
+  SL_CODE_COMPONENT_PSEC_OSAL=psec_osal
+)
+
 zephyr_library_sources_ifdef(CONFIG_ENTROPY_GECKO_SE
   ${SECURITY_DIR}/sl_component/se_manager/src/sl_se_manager_entropy.c
 )
 
-zephyr_library_sources(src/sl_memory_manager_shim.c)
+zephyr_library_sources(
+  src/sl_interrupt_manager_shim.c
+  src/sl_memory_manager_shim.c
+)
 
 zephyr_library_sources_ifdef(
   CONFIG_BUILD_ONLY_NO_BLOBS
   src/blob_stubs.c
 )
+
+zephyr_linker_sources(ROM_SECTIONS linker/code_classification_text.ld)
+zephyr_linker_sources(RAMFUNC_SECTION linker/code_classification_ramfunc.ld)
diff --git a/modules/hal_silabs/simplicity_sdk/Kconfig b/modules/hal_silabs/simplicity_sdk/Kconfig
new file mode 100644
index 00000000000..7d2c8fcfa4b
--- /dev/null
+++ b/modules/hal_silabs/simplicity_sdk/Kconfig
@@ -0,0 +1,31 @@
+# Copyright (c) 2025 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+menu "SiSDK configuration"
+	depends on HAS_SILABS_SISDK
+
+config RAIL_PA_CURVE_HEADER
+	string "RAIL PA custom curve header file"
+	default "pa_curves_efr32.h"
+	help
+	  Name of custom PA curve header file for use by PA initialization.
+	  See AN1127 for information on how to create a custom PA curve.
+	  The header file must be available on the include path.
+
+config RAIL_PA_CURVE_TYPES_HEADER
+	string "RAIL PA curve types header file"
+	default "pa_curve_types_efr32.h"
+	help
+	  Name of custom PA curve type header file for use by PA initialization.
+	  See AN1127 for information on how to create a custom PA curve.
+	  The header file must be available on the include path.
+
+config RAIL_PA_ENABLE_CALIBRATION
+	bool "RAIL PA: apply factory calibration offset"
+	default y
+	help
+	  Ensure that the PA power remains constant chip-to-chip by applying factory
+	  calibration. This option is enabled by default, and is recommended for all
+	  Series 2 devices.
+
+endmenu
diff --git a/modules/hal_silabs/simplicity_sdk/config/sl_rail_util_pa_config.h b/modules/hal_silabs/simplicity_sdk/config/sl_rail_util_pa_config.h
new file mode 100644
index 00000000000..9d3edccb059
--- /dev/null
+++ b/modules/hal_silabs/simplicity_sdk/config/sl_rail_util_pa_config.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * This configuration header is used by the HAL driver rail_util_pa from hal_silabs,
+ * invoked through the init function of the hci_silabs_efr32 Bluetooth driver.
+ * DeviceTree and Kconfig options are converted to config macros expected by the HAL driver.
+ */
+
+#ifndef SL_RAIL_UTIL_PA_CONFIG_H
+#define SL_RAIL_UTIL_PA_CONFIG_H
+
+#include <zephyr/devicetree.h>
+#include "rail_types.h"
+
+#define SL_RAIL_UTIL_PA_POWER_DECI_DBM (DT_PROP(DT_NODELABEL(radio), pa_initial_power_dbm) * 10)
+#define SL_RAIL_UTIL_PA_RAMP_TIME_US   DT_PROP(DT_NODELABEL(radio), pa_ramp_time_us)
+#define SL_RAIL_UTIL_PA_VOLTAGE_MV     DT_PROP(DT_NODELABEL(radio), pa_voltage_mv)
+
+#if DT_NODE_HAS_PROP(DT_NODELABEL(radio), pa_2p4ghz)
+#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ                                                           \
+	CONCAT(RAIL_TX_POWER_MODE_2P4GIG_, DT_STRING_UPPER_TOKEN(DT_NODELABEL(radio), pa_2p4ghz))
+#else
+#define SL_RAIL_UTIL_PA_SELECTION_2P4GHZ RAIL_TX_POWER_MODE_NONE
+#endif
+
+#if DT_NODE_HAS_PROP(DT_NODELABEL(radio), pa_subghz)
+#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ                                                           \
+	CONCAT(RAIL_TX_POWER_MODE_SUBGIG_, DT_STRING_UPPER_TOKEN(DT_NODELABEL(radio), pa_subghz))
+#else
+#define SL_RAIL_UTIL_PA_SELECTION_SUBGHZ RAIL_TX_POWER_MODE_NONE
+#endif
+
+#define SL_RAIL_UTIL_PA_CURVE_HEADER       CONFIG_RAIL_PA_CURVE_HEADER
+#define SL_RAIL_UTIL_PA_CURVE_TYPES        CONFIG_RAIL_PA_CURVE_TYPES_HEADER
+#define SL_RAIL_UTIL_PA_CALIBRATION_ENABLE CONFIG_RAIL_PA_ENABLE_CALIBRATION
+
+#endif /* SL_RAIL_UTIL_PA_CONFIG_H */
diff --git a/modules/hal_silabs/simplicity_sdk/linker/code_classification_ramfunc.ld b/modules/hal_silabs/simplicity_sdk/linker/code_classification_ramfunc.ld
new file mode 100644
index 00000000000..3a55e17a098
--- /dev/null
+++ b/modules/hal_silabs/simplicity_sdk/linker/code_classification_ramfunc.ld
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Place data annotated as ramfunc into the Zephyr .ramfunc section.
+ */
+
+*(text_application_ram)
diff --git a/modules/hal_silabs/simplicity_sdk/linker/code_classification_text.ld b/modules/hal_silabs/simplicity_sdk/linker/code_classification_text.ld
new file mode 100644
index 00000000000..d8596a63330
--- /dev/null
+++ b/modules/hal_silabs/simplicity_sdk/linker/code_classification_text.ld
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Place text sections tagged with Silicon Labs code classification annotations into flash.
+ */
+
+SECTION_PROLOGUE(.cc_text,,)
+{
+    _cc_text_start = .;
+    *(SORT_BY_ALIGNMENT(text_*[0-9]))
+    _cc_text_end = .;
+} GROUP_LINK_IN(ROMABLE_REGION)
+_cc_text_size = _cc_text_end - _cc_text_start;
diff --git a/modules/hal_silabs/simplicity_sdk/src/blob_stubs.c b/modules/hal_silabs/simplicity_sdk/src/blob_stubs.c
index 381c936adfc..ad06b11d61e 100644
--- a/modules/hal_silabs/simplicity_sdk/src/blob_stubs.c
+++ b/modules/hal_silabs/simplicity_sdk/src/blob_stubs.c
@@ -31,6 +31,11 @@ void BTLE_LL_Process(uint32_t events)
 {
 }
 
+int16_t BTLE_LL_SetMaxPower(int16_t power)
+{
+	return 0;
+}
+
 void sl_btctrl_disable_2m_phy(void)
 {
 }
@@ -109,6 +114,10 @@ void sl_btctrl_hci_parser_init_phy(void)
 {
 }
 
+void sl_bthci_init_vs(void)
+{
+}
+
 void AGC_IRQHandler(void)
 {
 }
diff --git a/modules/hal_silabs/simplicity_sdk/src/sl_btctrl_hci_reset_shim.c b/modules/hal_silabs/simplicity_sdk/src/sl_btctrl_hci_reset_shim.c
new file mode 100644
index 00000000000..4ba10cdfb89
--- /dev/null
+++ b/modules/hal_silabs/simplicity_sdk/src/sl_btctrl_hci_reset_shim.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Shim for sl_btctrl_hci_reset API
+ */
+
+#include <stdbool.h>
+
+bool sl_btctrl_hci_reset_reason_is_sys_reset(void)
+{
+	/* If this function returns true, the LL will emit command complete for HCI Reset during
+	 * init. This only makes sense when the LL runs on a separate device from the host stack.
+	 * Always return false.
+	 */
+	return false;
+}
+
+void sl_btctrl_hci_reset(void)
+{
+	/* This function works as a callback during processing of the HCI Reset command, and allows
+	 * for custom processing (such as fully resetting the device). This only makes sense when
+	 * the LL runs on a separate device from the host stack. Do nothing.
+	 */
+}
diff --git a/modules/hal_silabs/simplicity_sdk/src/sl_interrupt_manager_shim.c b/modules/hal_silabs/simplicity_sdk/src/sl_interrupt_manager_shim.c
new file mode 100644
index 00000000000..8f6bd5092d1
--- /dev/null
+++ b/modules/hal_silabs/simplicity_sdk/src/sl_interrupt_manager_shim.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Shim for sl_interrupt_manager API using Zephyr API
+ */
+
+#include <zephyr/kernel.h>
+
+#include "sl_interrupt_manager.h"
+
+#define LOCK_KEY_DEFAULT 0xFFFFFFFFU
+
+static unsigned int lock_key = LOCK_KEY_DEFAULT;
+
+void sl_interrupt_manager_disable_interrupts(void)
+{
+	__ASSERT(lock_key == LOCK_KEY_DEFAULT, "Interrupt manager doesn't support nested disable");
+	lock_key = irq_lock();
+}
+
+void sl_interrupt_manager_enable_interrupts(void)
+{
+	irq_unlock(lock_key);
+	lock_key = LOCK_KEY_DEFAULT;
+}
+
+void sl_interrupt_manager_disable_irq(int32_t irqn)
+{
+	irq_disable(irqn);
+}
+
+void sl_interrupt_manager_enable_irq(int32_t irqn)
+{
+	irq_enable(irqn);
+}
+
+bool sl_interrupt_manager_is_irq_disabled(int32_t irqn)
+{
+	return !irq_is_enabled(irqn);
+}
+
+bool sl_interrupt_manager_is_irq_pending(int32_t irqn)
+{
+	return NVIC_GetPendingIRQ(irqn);
+}
+
+void sl_interrupt_manager_set_irq_pending(int32_t irqn)
+{
+	NVIC_SetPendingIRQ(irqn);
+}
+
+void sl_interrupt_manager_clear_irq_pending(int32_t irqn)
+{
+	NVIC_ClearPendingIRQ(irqn);
+}
+
+uint32_t sl_interrupt_manager_get_irq_priority(int32_t irqn)
+{
+	return NVIC_GetPriority(irqn);
+}
+
+void sl_interrupt_manager_set_irq_priority(int32_t irqn, uint32_t priority)
+{
+	NVIC_SetPriority(irqn, priority);
+}
+
+uint32_t sl_interrupt_manager_get_active_irq(int32_t irqn)
+{
+	return NVIC_GetActive(irqn);
+}
diff --git a/modules/hal_silabs/wiseconnect/CMakeLists.txt b/modules/hal_silabs/wiseconnect/CMakeLists.txt
new file mode 100644
index 00000000000..7ca5909189b
--- /dev/null
+++ b/modules/hal_silabs/wiseconnect/CMakeLists.txt
@@ -0,0 +1,173 @@
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+set(SISDK_DIR ${ZEPHYR_HAL_SILABS_MODULE_DIR}/simplicity_sdk)
+set(WISECONNECT_DIR ${ZEPHYR_HAL_SILABS_MODULE_DIR}/wiseconnect)
+
+# Keep these values sync with
+# components/device/silabs/si91x/mcu/core/chip/component/siwg917*.slcc
+zephyr_compile_definitions(
+  SL_SI91X_ENABLE_LITTLE_ENDIAN
+  SLI_SI91X_MCU_COMMON_FLASH_MODE
+  SLI_SI91X_MCU_CONFIG_RADIO_BOARD_VER2
+  SLI_SI91X_MCU_CONFIG_RADIO_BOARD_BASE_VER
+  SLI_SI91X_MCU_ENABLE_FLASH_BASED_EXECUTION
+  SLI_SI91X_MCU_ENABLE_IPMU_APIS
+  SLI_SI91X_MCU_INTERFACE
+  SLI_SI917
+  SLI_SI917B0
+  CLOCK_ROMDRIVER_PRESENT
+)
+
+zephyr_include_directories(
+  ${SISDK_DIR}/platform/common/inc
+  ${SISDK_DIR}/platform/common/config
+  ${WISECONNECT_DIR}/components/board/silabs/inc
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/config
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/inc
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/config
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/rom_driver/inc
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/inc
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/service/clock_manager/inc
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/systemlevel/inc
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/unified_api/inc
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/inc
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/cmsis_driver/config
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/cmsis_driver
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/cmsis_driver/CMSIS/Driver/Include
+)
+
+zephyr_library_sources(
+  ${SISDK_DIR}/platform/common/src/sl_core_cortexm.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/src/rsi_deepsleep_soc.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/src/system_si91x.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/clock_update.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_pwm.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_sysrtc.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ipmu.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_pll.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_ulpss_clk.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/systemlevel/src/rsi_wwdt.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/service/clock_manager/src/sl_si91x_clock_manager.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_driver_gpio.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_pwm.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/unified_peripheral_drivers/src/sl_si91x_peripheral_gpio.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/ipmu_apis.c
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/src/iPMU_prog/iPMU_dotc/rsi_system_config_917.c
+)
+
+zephyr_library_sources_ifdef(CONFIG_ENTROPY_SILABS_SIWX91X
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/peripheral_drivers/src/rsi_rng.c
+)
+
+zephyr_compile_definitions_ifdef(CONFIG_DMA_SILABS_SIWX91X
+  UDMA_ROMDRIVER_PRESENT
+)
+
+zephyr_library_sources_ifdef(CONFIG_DMA_SILABS_SIWX91X
+  ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/rom_driver/src/rsi_rom_table_si91x.c
+)
+
+if(CONFIG_WIFI_SILABS_SIWX91X)
+  zephyr_library_sources(
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/sl_net/src/sl_si91x_net_credentials.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/sl_net/src/sl_si91x_net_internal_stack.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/sl_net/src/sl_net_si91x_integration_handler.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/sl_net/src/sl_net_rsi_utility.c
+    ${WISECONNECT_DIR}/components/protocol/wifi/src/sl_wifi_basic_credentials.c
+    ${WISECONNECT_DIR}/components/service/network_manager/si91x/sl_net_si91x.c
+    ${WISECONNECT_DIR}/components/service/network_manager/src/sl_net_basic_profiles.c
+    ${WISECONNECT_DIR}/components/service/network_manager/src/sl_net_credentials.c
+  )
+  zephyr_compile_definitions_ifdef(CONFIG_NET_IPV6
+    SLI_SI91X_ENABLE_IPV6
+  )
+  zephyr_compile_definitions_ifdef(CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_OFFLOAD
+    SLI_SI91X_OFFLOAD_NETWORK_STACK
+    SLI_SI91X_SOCKETS
+  )
+  zephyr_include_directories_ifdef(CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_OFFLOAD
+    # Needed for <sys/socket.h>
+    ${ZEPHYR_BASE}/include/zephyr/posix
+  )
+  zephyr_library_sources_ifdef(CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_OFFLOAD
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/socket/src/sl_si91x_socket_utility.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/asynchronous_socket/src/sl_si91x_socket.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/sl_net/src/sl_net_si91x_callback_framework.c
+    ${WISECONNECT_DIR}/components/service/network_manager/src/sl_net.c
+  )
+endif() # CONFIG_WIFI_SILABS_SIWX91X
+
+if(CONFIG_BT_SILABS_SIWX91X)
+  zephyr_compile_definitions(
+    SLI_SI91X_ENABLE_BLE
+  )
+  zephyr_include_directories(
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/ble/inc
+  )
+  zephyr_library_sources(
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/ble/src/rsi_bt_ble.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/ble/src/rsi_common_apis.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/ble/src/rsi_utils.c
+  )
+endif() # CONFIG_BT_SILABS_SIWX91X
+
+if(CONFIG_WISECONNECT_NETWORK_STACK)
+  zephyr_compile_definitions(
+    SLI_SI91X_ENABLE_OS
+    SL_SI91X_SI917_RAM_MEM_CONFIG=1
+    SL_WIFI_COMPONENT_INCLUDED # Depite de the name, required for everything
+  )
+  zephyr_include_directories(
+    # FIXME: find why this directory is not included when CMSIS_RTOS_V2=y
+    ${ZEPHYR_BASE}/include/zephyr/portability
+    ${SISDK_DIR}/platform/emlib/inc
+    ${WISECONNECT_DIR}/resources/defaults
+    ${WISECONNECT_DIR}/components/common/inc
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/inc
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/sl_net/inc
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/socket/inc
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/asynchronous_socket/inc
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/ahb_interface/inc
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/core/chip/config
+    ${WISECONNECT_DIR}/components/protocol/wifi/inc
+    ${WISECONNECT_DIR}/components/service/network_manager/inc
+  )
+  zephyr_library_sources(
+    ${WISECONNECT_DIR}/components/common/src/sl_utility.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_ram.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/ahb_interface/src/rsi_hal_mcu_m4_rom.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/ahb_interface/src/sli_siwx917_soc.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/ahb_interface/src/sl_platform_wireless.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/ahb_interface/src/sl_si91x_bus.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/host_mcu/si91x/siwx917_soc_ncp_host.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/memory/malloc_buffers.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/src/sl_rsi_utility.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/src/sl_si91x_driver.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/wireless/threading/sli_si91x_multithreaded.c
+    ${WISECONNECT_DIR}/components/protocol/wifi/si91x/sl_wifi.c
+    ${WISECONNECT_DIR}/components/protocol/wifi/src/sl_wifi_callback_framework.c
+  )
+endif() # CONFIG_WISECONNECT_NETWORK_STACK
+
+if(CONFIG_SOC_SILABS_SLEEPTIMER)
+  zephyr_include_directories(
+    ${SISDK_DIR}/platform/service/sleeptimer/inc
+    ${SISDK_DIR}/platform/service/sleeptimer/src
+    ${SISDK_DIR}/platform/service/sleeptimer/config
+  )
+
+  zephyr_library_sources(
+    ${SISDK_DIR}/platform/service/sleeptimer/src/sl_sleeptimer.c
+    ${WISECONNECT_DIR}/components/device/silabs/si91x/mcu/drivers/service/sleeptimer/src/sl_sleeptimer_hal_si91x_sysrtc.c
+  )
+  zephyr_compile_definitions(
+    SL_CATALOG_SLEEPTIMER_PRESENT
+    SL_CODE_COMPONENT_SLEEPTIMER=sleeptimer
+    SL_CODE_COMPONENT_HAL_SYSRTC=hal_sysrtc
+  )
+endif() # CONFIG_SOC_SILABS_SLEEPTIMER
+
+zephyr_linker_sources(ROM_SECTIONS linker/code_classification_text.ld)
+zephyr_linker_sources(RAMFUNC_SECTION linker/code_classification_ramfunc.ld)
diff --git a/modules/hal_silabs/wiseconnect/linker/code_classification_ramfunc.ld b/modules/hal_silabs/wiseconnect/linker/code_classification_ramfunc.ld
new file mode 100644
index 00000000000..3a55e17a098
--- /dev/null
+++ b/modules/hal_silabs/wiseconnect/linker/code_classification_ramfunc.ld
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Place data annotated as ramfunc into the Zephyr .ramfunc section.
+ */
+
+*(text_application_ram)
diff --git a/modules/hal_silabs/wiseconnect/linker/code_classification_text.ld b/modules/hal_silabs/wiseconnect/linker/code_classification_text.ld
new file mode 100644
index 00000000000..d8596a63330
--- /dev/null
+++ b/modules/hal_silabs/wiseconnect/linker/code_classification_text.ld
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Place text sections tagged with Silicon Labs code classification annotations into flash.
+ */
+
+SECTION_PROLOGUE(.cc_text,,)
+{
+    _cc_text_start = .;
+    *(SORT_BY_ALIGNMENT(text_*[0-9]))
+    _cc_text_end = .;
+} GROUP_LINK_IN(ROMABLE_REGION)
+_cc_text_size = _cc_text_end - _cc_text_start;
diff --git a/modules/hal_tdk/Kconfig b/modules/hal_tdk/Kconfig
index deeae5d0142..964c0513458 100644
--- a/modules/hal_tdk/Kconfig
+++ b/modules/hal_tdk/Kconfig
@@ -17,4 +17,22 @@ config USE_EMD_ICM42670
 	depends on DT_HAS_INVENSENSE_ICM42670P_ENABLED \
 		|| DT_HAS_INVENSENSE_ICM42670S_ENABLED
 
+config USE_EMD_ICM42370
+	bool "ICM42370P High Performance 3-Axis MotionTracking Accelerometer"
+	default y
+	imply TDK_HAL
+	depends on ZEPHYR_HAL_TDK_MODULE
+	depends on DT_HAS_INVENSENSE_ICM42370P_ENABLED
+
+config USE_EMD_ICP101XX
+	bool "ICP101XX Barometric Pressure and Temperature Sensors"
+	imply TDK_HAL
+	depends on ZEPHYR_HAL_TDK_MODULE
+	depends on DT_HAS_INVENSENSE_ICP101XX_ENABLED
+
+config USE_EMD_ICP201XX
+	bool "ICP201XX Barometric Pressure and Temperature Sensor"
+	imply TDK_HAL
+	depends on ZEPHYR_HAL_TDK_MODULE
+	depends on DT_HAS_INVENSENSE_ICP201XX_ENABLED
 endmenu
diff --git a/modules/hal_wch/CMakeLists.txt b/modules/hal_wch/CMakeLists.txt
index 729bc403567..ad16ad6c62b 100644
--- a/modules/hal_wch/CMakeLists.txt
+++ b/modules/hal_wch/CMakeLists.txt
@@ -1,3 +1,3 @@
-if(CONFIG_SOC_SERIES_CH32V00X)
+if(CONFIG_SOC_CH32V003 OR CONFIG_SOC_SERIES_QINGKE_V4C)
   zephyr_include_directories(${ZEPHYR_HAL_WCH_MODULE_DIR}/ch32v003fun .)
 endif()
diff --git a/modules/hal_wch/ch32fun.h b/modules/hal_wch/ch32fun.h
index b239ed5f61b..555bcd3e75b 100644
--- a/modules/hal_wch/ch32fun.h
+++ b/modules/hal_wch/ch32fun.h
@@ -12,4 +12,9 @@
 #include <ch32v003fun.h>
 #endif
 
+#if defined(CONFIG_SOC_SERIES_QINGKE_V4C)
+#define CH32V20x 1
+#include <ch32v003fun.h>
+#endif
+
 #endif
diff --git a/modules/hostap/CMakeLists.txt b/modules/hostap/CMakeLists.txt
index d623f298869..c30faaf9e5d 100644
--- a/modules/hostap/CMakeLists.txt
+++ b/modules/hostap/CMakeLists.txt
@@ -249,6 +249,11 @@ zephyr_library_sources_ifdef(CONFIG_WIFI_NM_HOSTAPD_AP
   ${WIFI_NM_HOSTAPD_BASE}/eap_register.c
   ${WIFI_NM_HOSTAPD_BASE}/hostapd_cli_cmds.c
   ${WIFI_NM_HOSTAPD_BASE}/hostapd_cli_zephyr.c
+
+  # Zephyr specific files (glue code)
+  src/hapd_main.c
+  src/hapd_api.c
+  src/hapd_events.c
 )
 
 zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_HOSTAPD_AP
@@ -383,6 +388,8 @@ zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_HOSTAPD_WPS
 
 zephyr_library_sources_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
   ${HOSTAP_SRC_BASE}/eap_common/eap_common.c
+  ${HOSTAP_SRC_BASE}/eap_peer/eap_tls_common.c
+
 )
 
 zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
@@ -392,7 +399,6 @@ zephyr_library_compile_definitions_ifdef(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_EN
 
 zephyr_library_sources_ifdef(CONFIG_EAP_TLS
   ${HOSTAP_SRC_BASE}/eap_peer/eap_tls.c
-  ${HOSTAP_SRC_BASE}/eap_peer/eap_tls_common.c
 )
 
 zephyr_library_compile_definitions_ifdef(CONFIG_EAP_TLS
@@ -441,7 +447,7 @@ zephyr_library_compile_definitions_ifdef(CONFIG_EAP_MSCHAPV2
   EAP_MSCHAPv2
 )
 
-if(CONFIG_EAP_TTLS OR CONFIG_EAP_MSCHAPV2)
+if(CONFIG_EAP_TTLS OR CONFIG_EAP_MSCHAPV2 OR CONFIG_EAP_MD5)
   zephyr_library_sources(${HOSTAP_SRC_BASE}/eap_common/chap.c)
 endif()
 
@@ -518,9 +524,12 @@ zephyr_library_compile_definitions_ifdef(CONFIG_EAP_IKEV2
   EAP_IKEV2
 )
 
+if (CONFIG_EAP_SIM OR CONFIG_EAP_AKA)
+  zephyr_library_sources(${HOSTAP_SRC_BASE}/eap_common/eap_sim_common.c)
+endif()
+
 zephyr_library_sources_ifdef(CONFIG_EAP_SIM
   ${HOSTAP_SRC_BASE}/eap_peer/eap_sim.c
-  ${HOSTAP_SRC_BASE}/eap_common/eap_sim_common.c
 )
 
 zephyr_library_compile_definitions_ifdef(CONFIG_EAP_SIM
diff --git a/modules/hostap/Kconfig b/modules/hostap/Kconfig
index 2836ba60ff4..b59657dc53e 100644
--- a/modules/hostap/Kconfig
+++ b/modules/hostap/Kconfig
@@ -10,7 +10,6 @@ config WIFI_NM_WPA_SUPPLICANT
 	select POSIX_TIMERS
 	select POSIX_SIGNALS
 	select POSIX_API
-	select FILE_SYSTEM
 	select NET_SOCKETS
 	select NET_SOCKETS_PACKET
 	select NET_SOCKETPAIR
@@ -135,6 +134,7 @@ config WIFI_NM_WPA_SUPPLICANT_CRYPTO_ALT
 	select MBEDTLS_CIPHER_DES_ENABLED
 	select MBEDTLS_MD5
 	select MBEDTLS_SHA1
+	select MBEDTLS_SHA384
 	select MBEDTLS_ENTROPY_C
 	select MBEDTLS_CIPHER
 	select MBEDTLS_ECP_C
@@ -145,6 +145,9 @@ config WIFI_NM_WPA_SUPPLICANT_CRYPTO_ALT
 	select MBEDTLS_ECDH_C
 	select MBEDTLS_ECDSA_C
 	select MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
+	select MBEDTLS_RSA_C
+	select MBEDTLS_PKCS1_V15
+	select MBEDTLS_PKCS1_V21
 	select MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
 	select MBEDTLS_NIST_KW_C
 	select MBEDTLS_DHM_C
@@ -294,6 +297,7 @@ config WIFI_NM_HOSTAPD_AP
 
 config WIFI_NM_HOSTAPD_CRYPTO_ENTERPRISE
 	bool "Hostapd crypto enterprise support"
+	depends on WIFI_NM_HOSTAPD_AP
 
 config EAP_SERVER_TLS
 	bool "EAP-TLS server support"
@@ -346,6 +350,7 @@ config WIFI_NM_WPA_SUPPLICANT_DPP
 	bool "WFA Easy Connect DPP"
 	select DPP
 	select DPP2
+	select DPP3
 	select GAS
 	select GAS_SERVER
 	select OFFCHANNEL
diff --git a/modules/hostap/src/hapd_api.c b/modules/hostap/src/hapd_api.c
new file mode 100644
index 00000000000..97367d35c53
--- /dev/null
+++ b/modules/hostap/src/hapd_api.c
@@ -0,0 +1,1032 @@
+/**
+ * Copyright 2023-2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/net/wifi_mgmt.h>
+#include "includes.h"
+#include "common.h"
+#include "common/defs.h"
+#include "wpa_supplicant_i.h"
+#include "hostapd.h"
+#include "hostapd_cli_zephyr.h"
+#include "ap_drv_ops.h"
+#include "hapd_main.h"
+#include "hapd_api.h"
+#include "supp_events.h"
+#include "supp_api.h"
+
+K_MUTEX_DEFINE(hostapd_mutex);
+
+#ifdef CONFIG_WIFI_NM_HOSTAPD_CRYPTO_ENTERPRISE
+static struct wifi_eap_config hapd_eap_config[] = {
+	{WIFI_SECURITY_TYPE_EAP_TLS, WIFI_EAP_TYPE_TLS, WIFI_EAP_TYPE_NONE, "TLS", NULL},
+	{WIFI_SECURITY_TYPE_EAP_PEAP_MSCHAPV2, WIFI_EAP_TYPE_PEAP, WIFI_EAP_TYPE_MSCHAPV2, "PEAP",
+	 "auth=MSCHAPV2"},
+	{WIFI_SECURITY_TYPE_EAP_PEAP_GTC, WIFI_EAP_TYPE_PEAP, WIFI_EAP_TYPE_GTC, "PEAP",
+	 "auth=GTC"},
+	{WIFI_SECURITY_TYPE_EAP_TTLS_MSCHAPV2, WIFI_EAP_TYPE_TTLS, WIFI_EAP_TYPE_NONE, "TTLS",
+	 "auth=MSCHAPV2"},
+	{WIFI_SECURITY_TYPE_EAP_PEAP_TLS, WIFI_EAP_TYPE_PEAP, WIFI_EAP_TYPE_TLS, "PEAP",
+	 "auth=TLS"},
+};
+
+static struct wifi_enterprise_creds_params hapd_enterprise_creds;
+#endif
+
+#define hostapd_cli_cmd_v(cmd, ...) ({					\
+	bool status;							\
+									\
+	if (zephyr_hostapd_cli_cmd_v(cmd, ##__VA_ARGS__) < 0) {		\
+		wpa_printf(MSG_ERROR,					\
+			   "Failed to execute wpa_cli command: %s",	\
+			   cmd);					\
+		status = false;						\
+	} else {							\
+		status = true;						\
+	}								\
+									\
+	status;								\
+})
+
+static inline struct hostapd_iface *get_hostapd_handle(const struct device *dev)
+{
+	struct net_if *iface = net_if_lookup_by_dev(dev);
+	char if_name[CONFIG_NET_INTERFACE_NAME_LEN + 1];
+	struct hostapd_iface *hapd;
+	int ret;
+
+	if (!iface) {
+		wpa_printf(MSG_ERROR, "Interface for device %s not found", dev->name);
+		return NULL;
+	}
+
+	ret = net_if_get_name(iface, if_name, sizeof(if_name));
+	if (!ret) {
+		wpa_printf(MSG_ERROR, "Cannot get interface name (%d)", ret);
+		return NULL;
+	}
+
+	hapd = zephyr_get_hapd_handle_by_ifname(if_name);
+	if (!hapd) {
+		wpa_printf(MSG_ERROR, "Interface %s not found", if_name);
+		return NULL;
+	}
+
+	return hapd;
+}
+
+#ifdef CONFIG_WIFI_NM_HOSTAPD_CRYPTO_ENTERPRISE
+static int hapd_process_cert_data(struct hostapd_bss_config *conf,
+				  char *type, uint8_t *data, uint32_t data_len)
+{
+	if (os_strcmp(type, "ca_cert_blob") == 0) {
+		conf->ca_cert_blob = data;
+		conf->ca_cert_blob_len = data_len;
+	} else if (os_strcmp(type, "server_cert_blob") == 0) {
+		conf->server_cert_blob = data;
+		conf->server_cert_blob_len = data_len;
+	} else if (os_strcmp(type, "private_key_blob") == 0) {
+		conf->private_key_blob = data;
+		conf->private_key_blob_len = data_len;
+	} else if (os_strcmp(type, "dh_blob") == 0) {
+		conf->dh_blob = data;
+		conf->dh_blob_len = data_len;
+	} else {
+		wpa_printf(MSG_ERROR, "input type error");
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static int hapd_get_eap_config(struct wifi_connect_req_params *params,
+			       struct wifi_eap_config *eap_cfg)
+{
+	unsigned int index = 0;
+
+	for (index = 0; index < ARRAY_SIZE(hapd_eap_config); index++) {
+		if (params->security == hapd_eap_config[index].type) {
+			memcpy(eap_cfg, &hapd_eap_config[index], sizeof(struct wifi_eap_config));
+			break;
+		}
+	}
+
+	if (index == ARRAY_SIZE(hapd_eap_config)) {
+		wpa_printf(MSG_ERROR, "Get eap method type with security type: %d",
+		params->security);
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static struct hostapd_eap_user *hapd_process_eap_user_phase1(
+	struct wifi_connect_req_params *params, struct hostapd_eap_user **pnew_user)
+{
+	struct hostapd_eap_user *user = NULL, *tail = NULL, *new_user = NULL;
+	struct wifi_eap_config eap_cfg;
+
+	user = os_zalloc(sizeof(*user));
+	if (user == NULL) {
+		wpa_printf(MSG_ERROR, "EAP user allocation failed");
+		goto failed;
+	}
+
+	user->force_version = -1;
+	if (params->eap_ver >= 0) {
+		user->force_version = params->eap_ver;
+	}
+
+	if (hapd_get_eap_config(params, &eap_cfg)) {
+		goto failed;
+	}
+
+	user->methods[0].method = eap_cfg.eap_type_phase1;
+	user->methods[0].vendor = 0;
+
+	if (tail == NULL) {
+		tail = new_user = user;
+	} else {
+		tail->next = user;
+		tail       = user;
+	}
+
+	*pnew_user = new_user;
+
+	return tail;
+
+failed:
+	if (user) {
+		hostapd_config_free_eap_user(user);
+	}
+
+	return NULL;
+}
+
+static int hapd_process_eap_user(struct wifi_connect_req_params *params,
+				 struct hostapd_bss_config *conf)
+{
+	struct hostapd_eap_user *user = NULL, *tail = NULL, *user_list = NULL;
+	int i, nusers = params->nusers;
+	const char *identity, *password;
+	struct wifi_eap_config eap_cfg;
+	int ret = 0;
+
+	if (hapd_get_eap_config(params, &eap_cfg)) {
+		goto failed;
+	}
+
+	if (eap_cfg.phase2 != NULL) {
+		tail = hapd_process_eap_user_phase1(params, &user_list);
+	}
+
+	if (eap_cfg.phase2 != NULL && !nusers) {
+		wpa_printf(MSG_ERROR, "EAP users not found.");
+		goto failed;
+	}
+
+	for (i = 0; i < nusers; i++) {
+		user = os_zalloc(sizeof(*user));
+		if (user == NULL) {
+			wpa_printf(MSG_ERROR, "EAP user allocation failed");
+			goto failed;
+		}
+
+		user->force_version = -1;
+		if (params->eap_ver >= 0) {
+			user->force_version = params->eap_ver;
+		}
+
+		identity = params->identities[i];
+		password = params->passwords[i];
+
+		user->identity = os_memdup(identity, os_strlen(identity));
+		if (user->identity == NULL) {
+			wpa_printf(MSG_ERROR,
+				   "Failed to allocate "
+				   "memory for EAP identity");
+			goto failed;
+		}
+		user->identity_len = os_strlen(identity);
+
+		user->methods[0].method = eap_cfg.eap_type_phase1;
+		user->methods[0].vendor = 0;
+
+		if (eap_cfg.phase2 != NULL) {
+			user->methods[0].method = eap_cfg.eap_type_phase2;
+			user->password = os_memdup(password, os_strlen(password));
+			if (user->password == NULL) {
+				wpa_printf(MSG_ERROR,
+					   "Failed to allocate "
+					   "memory for EAP password");
+				goto failed;
+			}
+			user->password_len = os_strlen(password);
+
+			user->phase2 = 1;
+		}
+
+		if (params->security == WIFI_SECURITY_TYPE_EAP_TTLS_MSCHAPV2) {
+			user->ttls_auth |= 0x1E;
+		}
+
+		if (tail == NULL) {
+			tail = user_list = user;
+		} else {
+			tail->next = user;
+			tail       = user;
+		}
+
+		continue;
+
+failed:
+		if (user) {
+			hostapd_config_free_eap_user(user);
+		}
+
+		ret = -1;
+		break;
+	}
+
+	if (ret == 0) {
+		hostapd_config_free_eap_users(conf->eap_user);
+		conf->eap_user = user_list;
+	} else {
+		hostapd_config_free_eap_users(user_list);
+	}
+
+	return ret;
+}
+
+int hapd_process_enterprise_config(struct hostapd_iface *iface,
+				   struct wifi_connect_req_params *params)
+{
+	struct wifi_eap_cipher_config cipher_config = {
+		NULL, "DEFAULT:!EXP:!LOW", "CCMP", "CCMP", "AES-128-CMAC", NULL};
+	int ret = 0;
+
+	if (process_cipher_config(params, &cipher_config)) {
+		goto out;
+	}
+
+	if (!hostapd_cli_cmd_v("set wpa %d", WPA_PROTO_RSN)) {
+		goto out;
+	}
+
+	if (!hostapd_cli_cmd_v("set wpa_key_mgmt %s", cipher_config.key_mgmt)) {
+		goto out;
+	}
+
+	if (!hostapd_cli_cmd_v("set rsn_pairwise %s", cipher_config.pairwise_cipher)) {
+		goto out;
+	}
+
+	if (!hostapd_cli_cmd_v("set wpa_pairwise %s", cipher_config.pairwise_cipher)) {
+		goto out;
+	}
+
+	if (!hostapd_cli_cmd_v("set group_cipher %s", cipher_config.group_cipher)) {
+		goto out;
+	}
+
+	if (!hostapd_cli_cmd_v("set group_mgmt_cipher %s", cipher_config.group_mgmt_cipher)) {
+		goto out;
+	}
+
+	if (cipher_config.tls_flags != NULL) {
+		if (!hostapd_cli_cmd_v("set tls_flags %s", cipher_config.tls_flags)) {
+			goto out;
+		}
+	}
+
+	if (!hostapd_cli_cmd_v("set ieee8021x %d", 1)) {
+		goto out;
+	}
+
+	if (!hostapd_cli_cmd_v("set eapol_version %d", 2)) {
+		goto out;
+	}
+
+	if (!hostapd_cli_cmd_v("set eap_server %d", 1)) {
+		goto out;
+	}
+
+	if (hapd_process_cert_data(iface->bss[0]->conf, "ca_cert_blob",
+		hapd_enterprise_creds.ca_cert, hapd_enterprise_creds.ca_cert_len)) {
+		goto out;
+	}
+
+	if (hapd_process_cert_data(iface->bss[0]->conf, "server_cert_blob",
+		hapd_enterprise_creds.server_cert, hapd_enterprise_creds.server_cert_len)) {
+		goto out;
+	}
+
+	if (hapd_process_cert_data(iface->bss[0]->conf, "private_key_blob",
+		hapd_enterprise_creds.server_key, hapd_enterprise_creds.server_key_len)) {
+		goto out;
+	}
+
+	if (hapd_process_cert_data(iface->bss[0]->conf, "dh_blob",
+		hapd_enterprise_creds.dh_param, hapd_enterprise_creds.dh_param_len)) {
+		goto out;
+	}
+
+	if (!hostapd_cli_cmd_v("set private_key_passwd %s", params->key_passwd)) {
+		goto out;
+	}
+
+	if (hapd_process_eap_user(params, iface->bss[0]->conf)) {
+		goto out;
+	}
+
+	return ret;
+out:
+	return -1;
+}
+
+int hostapd_add_enterprise_creds(const struct device *dev,
+				 struct wifi_enterprise_creds_params *creds)
+{
+	int ret = 0;
+
+	if (!creds) {
+		ret = -1;
+		wpa_printf(MSG_ERROR, "enterprise creds is NULL");
+		goto out;
+	}
+
+	memcpy((void *)&hapd_enterprise_creds, (void *)creds,
+	       sizeof(struct wifi_enterprise_creds_params));
+
+out:
+	return ret;
+}
+#endif
+
+bool hostapd_ap_reg_domain(struct wifi_reg_domain *reg_domain)
+{
+	return hostapd_cli_cmd_v("set country_code %s", reg_domain->country_code);
+}
+
+static int hapd_config_chan_center_seg0(struct wifi_connect_req_params *params)
+{
+	int ret = 0;
+	uint8_t center_freq_seg0_idx = 0;
+	uint8_t oper_chwidth = CHANWIDTH_USE_HT;
+	const uint8_t *center_freq = NULL;
+	static const uint8_t center_freq_40MHz[] = {38,  46,  54,  62,  102, 110,
+						    118, 126, 134, 142, 151, 159};
+	static const uint8_t center_freq_80MHz[] = {42, 58, 106, 122, 138, 155};
+	uint8_t index, index_max, chan_idx, ch_offset = 0;
+
+	/* Unless ACS is being used, both "channel" and "vht_oper_centr_freq_seg0_idx"
+	 * parameters must be set.
+	 */
+	switch (params->bandwidth) {
+	case WIFI_FREQ_BANDWIDTH_20MHZ:
+		oper_chwidth = CHANWIDTH_USE_HT;
+		center_freq_seg0_idx = params->channel;
+		break;
+	case WIFI_FREQ_BANDWIDTH_40MHZ:
+		oper_chwidth = CHANWIDTH_USE_HT;
+		center_freq = center_freq_40MHz;
+		index_max = ARRAY_SIZE(center_freq_40MHz);
+		ch_offset = 2;
+		break;
+	case WIFI_FREQ_BANDWIDTH_80MHZ:
+		oper_chwidth = CHANWIDTH_80MHZ;
+		center_freq = center_freq_80MHz;
+		index_max = ARRAY_SIZE(center_freq_80MHz);
+		ch_offset = 6;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (params->bandwidth != WIFI_FREQ_BANDWIDTH_20MHZ) {
+		chan_idx = params->channel;
+		for (index = 0; index < index_max; index++) {
+			if ((chan_idx >= (center_freq[index] - ch_offset)) &&
+			    (chan_idx <= (center_freq[index] + ch_offset))) {
+				center_freq_seg0_idx = center_freq[index];
+				break;
+			}
+		}
+	}
+
+	if (!hostapd_cli_cmd_v("set vht_oper_chwidth %d", oper_chwidth)) {
+		goto out;
+	}
+	if (!hostapd_cli_cmd_v("set vht_oper_centr_freq_seg0_idx %d", center_freq_seg0_idx)) {
+		goto out;
+	}
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_11AX
+	if (!hostapd_cli_cmd_v("set he_oper_chwidth %d", oper_chwidth)) {
+		goto out;
+	}
+	if (!hostapd_cli_cmd_v("set he_oper_centr_freq_seg0_idx %d", center_freq_seg0_idx)) {
+		goto out;
+	}
+#endif
+
+	return ret;
+out:
+	return -EINVAL;
+}
+
+int hapd_config_network(struct hostapd_iface *iface,
+			struct wifi_connect_req_params *params)
+{
+	int ret = 0;
+
+	if (!hostapd_cli_cmd_v("set ssid %s", params->ssid)) {
+		goto out;
+	}
+
+	if (params->channel == 0) {
+		if (params->band == 0) {
+			if (!hostapd_cli_cmd_v("set hw_mode g")) {
+				goto out;
+			}
+		} else if (params->band == 1) {
+			if (!hostapd_cli_cmd_v("set hw_mode a")) {
+				goto out;
+			}
+		} else {
+			wpa_printf(MSG_ERROR, "Invalid band %d", params->band);
+			goto out;
+		}
+	} else if (params->channel > 14) {
+		if (!hostapd_cli_cmd_v("set hw_mode a")) {
+			goto out;
+		}
+	} else {
+		if (!hostapd_cli_cmd_v("set hw_mode g")) {
+			goto out;
+		}
+	}
+
+	if (!hostapd_cli_cmd_v("set channel %d", params->channel)) {
+		goto out;
+	}
+
+	ret = hapd_config_chan_center_seg0(params);
+	if (ret) {
+		goto out;
+	}
+
+	if (params->security != WIFI_SECURITY_TYPE_NONE) {
+		if (params->security == WIFI_SECURITY_TYPE_WPA_PSK) {
+			if (!hostapd_cli_cmd_v("set wpa 1")) {
+				goto out;
+			}
+			if (!hostapd_cli_cmd_v("set wpa_key_mgmt WPA-PSK")) {
+				goto out;
+			}
+			if (!hostapd_cli_cmd_v("set wpa_passphrase %s", params->psk)) {
+				goto out;
+			}
+			if (!hostapd_cli_cmd_v("set wpa_pairwise CCMP")) {
+				goto out;
+			}
+		} else if (params->security == WIFI_SECURITY_TYPE_PSK) {
+			if (!hostapd_cli_cmd_v("set wpa 2")) {
+				goto out;
+			}
+			if (!hostapd_cli_cmd_v("set wpa_key_mgmt WPA-PSK")) {
+				goto out;
+			}
+			if (!hostapd_cli_cmd_v("set wpa_passphrase %s", params->psk)) {
+				goto out;
+			}
+			if (!hostapd_cli_cmd_v("set rsn_pairwise CCMP")) {
+				goto out;
+			}
+		} else if (params->security == WIFI_SECURITY_TYPE_PSK_SHA256) {
+			if (!hostapd_cli_cmd_v("set wpa 2")) {
+				goto out;
+			}
+			if (!hostapd_cli_cmd_v("set wpa_key_mgmt WPA-PSK-SHA256")) {
+				goto out;
+			}
+			if (!hostapd_cli_cmd_v("set wpa_passphrase %s", params->psk)) {
+				goto out;
+			}
+			if (!hostapd_cli_cmd_v("set rsn_pairwise CCMP")) {
+				goto out;
+			}
+		} else if (params->security == WIFI_SECURITY_TYPE_SAE_HNP ||
+			   params->security == WIFI_SECURITY_TYPE_SAE_H2E ||
+			   params->security == WIFI_SECURITY_TYPE_SAE_AUTO) {
+			if (!hostapd_cli_cmd_v("set wpa 2")) {
+				goto out;
+			}
+			if (!hostapd_cli_cmd_v("set wpa_key_mgmt SAE")) {
+				goto out;
+			}
+			if (!hostapd_cli_cmd_v("set sae_password %s",
+					       params->sae_password ? params->sae_password :
+					       params->psk)) {
+				goto out;
+			}
+			if (!hostapd_cli_cmd_v("set rsn_pairwise CCMP")) {
+				goto out;
+			}
+			if (params->security == WIFI_SECURITY_TYPE_SAE_H2E ||
+			    params->security == WIFI_SECURITY_TYPE_SAE_AUTO) {
+				if (!hostapd_cli_cmd_v("set sae_pwe %d",
+				    (params->security == WIFI_SECURITY_TYPE_SAE_H2E)
+						? 1
+						: 2)) {
+					goto out;
+				}
+			}
+		} else if (params->security == WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL) {
+			if (!hostapd_cli_cmd_v("set wpa 2")) {
+				goto out;
+			}
+
+			if (!hostapd_cli_cmd_v("set wpa_key_mgmt WPA-PSK SAE")) {
+				goto out;
+			}
+
+			if (!hostapd_cli_cmd_v("set wpa_passphrase %s", params->psk)) {
+				goto out;
+			}
+
+			if (!hostapd_cli_cmd_v("set sae_password %s",
+					       params->sae_password ? params->sae_password
+								    : params->psk)) {
+				goto out;
+			}
+
+			if (!hostapd_cli_cmd_v("set rsn_pairwise CCMP")) {
+				goto out;
+			}
+
+			if (!hostapd_cli_cmd_v("set sae_pwe 2")) {
+				goto out;
+			}
+		} else if (params->security == WIFI_SECURITY_TYPE_DPP) {
+			if (!hostapd_cli_cmd_v("set wpa 2")) {
+				goto out;
+			}
+			if (!hostapd_cli_cmd_v("set wpa_key_mgmt WPA-PSK DPP")) {
+				goto out;
+			}
+			if (!hostapd_cli_cmd_v("set wpa_passphrase %s", params->psk)) {
+				goto out;
+			}
+			if (!hostapd_cli_cmd_v("set wpa_pairwise CCMP")) {
+				goto out;
+			}
+			if (!hostapd_cli_cmd_v("set rsn_pairwise CCMP")) {
+				goto out;
+			}
+			if (!hostapd_cli_cmd_v("set dpp_configurator_connectivity 1")) {
+				goto out;
+			}
+#ifdef CONFIG_WIFI_NM_HOSTAPD_CRYPTO_ENTERPRISE
+		} else if (is_eap_valid_security(params->security)) {
+			if (hapd_process_enterprise_config(iface, params)) {
+				goto out;
+			}
+#endif
+		} else {
+			wpa_printf(MSG_ERROR, "Security type %d is not supported",
+				   params->security);
+			goto out;
+		}
+	} else {
+		if (!hostapd_cli_cmd_v("set wpa 0")) {
+			goto out;
+		}
+		iface->bss[0]->conf->wpa_key_mgmt = WPA_KEY_MGMT_NONE;
+	}
+
+	if (!hostapd_cli_cmd_v("set ieee80211w %d", params->mfp)) {
+		goto out;
+	}
+
+	if (!hostapd_cli_cmd_v("set ignore_broadcast_ssid %d", params->ignore_broadcast_ssid)) {
+		goto out;
+	}
+
+	return ret;
+out:
+	return -1;
+}
+
+static int set_ap_config_params(const struct device *dev, struct wifi_ap_config_params *params)
+{
+	const struct wifi_mgmt_ops *const wifi_mgmt_api = get_wifi_mgmt_api(dev);
+
+	if (wifi_mgmt_api == NULL || wifi_mgmt_api->ap_config_params == NULL) {
+		return -ENOTSUP;
+	}
+
+	return wifi_mgmt_api->ap_config_params(dev, params);
+}
+
+int hostapd_ap_config_params(const struct device *dev, struct wifi_ap_config_params *params)
+{
+	struct hostapd_iface *iface;
+	int ret = 0;
+
+	ret = set_ap_config_params(dev, params);
+	if (ret && (ret != -ENOTSUP)) {
+		wpa_printf(MSG_ERROR, "Failed to set ap config params");
+		return -EINVAL;
+	}
+
+	k_mutex_lock(&hostapd_mutex, K_FOREVER);
+
+	iface = get_hostapd_handle(dev);
+	if (iface == NULL) {
+		ret = -ENOENT;
+		wpa_printf(MSG_ERROR, "Interface %s not found", dev->name);
+		goto out;
+	}
+
+	if (iface->state > HAPD_IFACE_DISABLED) {
+		ret = -EBUSY;
+		wpa_printf(MSG_ERROR, "Interface %s is not in disable state", dev->name);
+		goto out;
+	}
+
+	if (params->type & WIFI_AP_CONFIG_PARAM_MAX_NUM_STA) {
+		if (!hostapd_cli_cmd_v("set max_num_sta %d", params->max_num_sta)) {
+			ret = -EINVAL;
+			wpa_printf(MSG_ERROR, "Failed to set maximum number of stations");
+			goto out;
+		}
+		wpa_printf(MSG_INFO, "Set maximum number of stations: %d", params->max_num_sta);
+	}
+
+	if (params->type & WIFI_AP_CONFIG_PARAM_HT_CAPAB) {
+		if (!hostapd_cli_cmd_v("set ht_capab %s", params->ht_capab)) {
+			ret = -EINVAL;
+			wpa_printf(MSG_ERROR, "Failed to set HT capabilities");
+			goto out;
+		}
+		wpa_printf(MSG_INFO, "Set HT capabilities: %s", params->ht_capab);
+	}
+
+	if (params->type & WIFI_AP_CONFIG_PARAM_VHT_CAPAB) {
+		if (!hostapd_cli_cmd_v("set vht_capab %s", params->vht_capab)) {
+			ret = -EINVAL;
+			wpa_printf(MSG_ERROR, "Failed to set VHT capabilities");
+			goto out;
+		}
+		wpa_printf(MSG_INFO, "Set VHT capabilities: %s", params->vht_capab);
+	}
+
+out:
+	k_mutex_unlock(&hostapd_mutex);
+	return ret;
+}
+
+int hostapd_ap_status(const struct device *dev, struct wifi_iface_status *status)
+{
+	int ret = 0;
+	struct hostapd_iface *iface;
+	struct hostapd_config *conf;
+	struct hostapd_data *hapd;
+	struct hostapd_bss_config *bss;
+	struct hostapd_ssid *ssid;
+	struct hostapd_hw_modes *hw_mode;
+	int proto;    /* Wi-Fi secure protocol */
+	int key_mgmt; /*  Wi-Fi key management */
+	int sae_pwe;
+
+	k_mutex_lock(&hostapd_mutex, K_FOREVER);
+
+	iface = get_hostapd_handle(dev);
+	if (!iface) {
+		ret = -1;
+		wpa_printf(MSG_ERROR, "Interface %s not found", dev->name);
+		goto out;
+	}
+
+	conf = iface->conf;
+	if (!conf) {
+		ret = -1;
+		wpa_printf(MSG_ERROR, "Conf %s not found", dev->name);
+		goto out;
+	}
+
+	bss = conf->bss[0];
+	if (!bss) {
+		ret = -1;
+		wpa_printf(MSG_ERROR, "Bss_conf %s not found", dev->name);
+		goto out;
+	}
+
+	hapd = iface->bss[0];
+	if (!hapd) {
+		ret = -1;
+		wpa_printf(MSG_ERROR, "Bss %s not found", dev->name);
+		goto out;
+	}
+
+	status->state = iface->state;
+	ssid = &bss->ssid;
+
+	os_memcpy(status->bssid, hapd->own_addr, WIFI_MAC_ADDR_LEN);
+	status->iface_mode = WIFI_MODE_AP;
+	status->band = wpas_band_to_zephyr(wpas_freq_to_band(iface->freq));
+	key_mgmt = bss->wpa_key_mgmt;
+	proto = bss->wpa;
+	sae_pwe = bss->sae_pwe;
+	status->wpa3_ent_type = wpas_key_mgmt_to_zephyr_wpa3_ent(key_mgmt);
+	status->security = wpas_key_mgmt_to_zephyr(1, hapd->conf, key_mgmt, proto, sae_pwe);
+	status->mfp = get_mfp(bss->ieee80211w);
+	status->channel = conf->channel;
+	os_memcpy(status->ssid, ssid->ssid, ssid->ssid_len);
+
+	status->dtim_period = bss->dtim_period;
+	status->beacon_interval = conf->beacon_int;
+
+	hw_mode = iface->current_mode;
+
+	status->link_mode = conf->ieee80211ax                          ? WIFI_6
+			    : conf->ieee80211ac                        ? WIFI_5
+			    : conf->ieee80211n                         ? WIFI_4
+			    : hw_mode->mode == HOSTAPD_MODE_IEEE80211G ? WIFI_3
+			    : hw_mode->mode == HOSTAPD_MODE_IEEE80211A ? WIFI_2
+			    : hw_mode->mode == HOSTAPD_MODE_IEEE80211B ? WIFI_1
+								       : WIFI_0;
+	status->twt_capable = (hw_mode->he_capab[IEEE80211_MODE_AP].mac_cap[0] & 0x04);
+
+out:
+	k_mutex_unlock(&hostapd_mutex);
+	return ret;
+}
+
+#ifdef CONFIG_WIFI_NM_HOSTAPD_WPS
+static int hapd_ap_wps_pbc(const struct device *dev)
+{
+	struct hostapd_iface *iface;
+	int ret = -1;
+
+	k_mutex_lock(&hostapd_mutex, K_FOREVER);
+
+	iface = get_hostapd_handle(dev);
+	if (!iface) {
+		ret = -1;
+		wpa_printf(MSG_ERROR, "Interface %s not found", dev->name);
+		goto out;
+	}
+
+	if (iface->state != HAPD_IFACE_ENABLED) {
+		ret = -EBUSY;
+		wpa_printf(MSG_ERROR, "Interface %s is not in enable state", dev->name);
+		goto out;
+	}
+
+	if (!hostapd_cli_cmd_v("wps_pbc")) {
+		goto out;
+	}
+
+	ret = 0;
+
+out:
+	k_mutex_unlock(&hostapd_mutex);
+	return ret;
+}
+
+static int hapd_ap_wps_pin(const struct device *dev, struct wifi_wps_config_params *params)
+{
+#define WPS_PIN_EXPIRE_TIME 120
+	struct hostapd_iface *iface;
+	char *get_pin_cmd = "WPS_AP_PIN random";
+	int ret  = 0;
+
+	k_mutex_lock(&hostapd_mutex, K_FOREVER);
+
+	iface = get_hostapd_handle(dev);
+	if (!iface) {
+		ret = -1;
+		wpa_printf(MSG_ERROR, "Interface %s not found", dev->name);
+		goto out;
+	}
+
+	if (iface->state != HAPD_IFACE_ENABLED) {
+		ret = -EBUSY;
+		wpa_printf(MSG_ERROR, "Interface %s is not in enable state", dev->name);
+		goto out;
+	}
+
+	if (params->oper == WIFI_WPS_PIN_GET) {
+		if (zephyr_hostapd_cli_cmd_resp(get_pin_cmd, params->pin)) {
+			goto out;
+		}
+	} else if (params->oper == WIFI_WPS_PIN_SET) {
+		if (!hostapd_cli_cmd_v("wps_check_pin %s", params->pin)) {
+			goto out;
+		}
+
+		if (!hostapd_cli_cmd_v("wps_pin any %s %d", params->pin, WPS_PIN_EXPIRE_TIME)) {
+			goto out;
+		}
+	} else {
+		wpa_printf(MSG_ERROR, "Error wps pin operation : %d", params->oper);
+		goto out;
+	}
+
+	ret = 0;
+
+out:
+	k_mutex_unlock(&hostapd_mutex);
+	return ret;
+}
+
+int hostapd_ap_wps_config(const struct device *dev, struct wifi_wps_config_params *params)
+{
+	int ret = 0;
+
+	if (params->oper == WIFI_WPS_PBC) {
+		ret = hapd_ap_wps_pbc(dev);
+	} else if (params->oper == WIFI_WPS_PIN_GET || params->oper == WIFI_WPS_PIN_SET) {
+		ret = hapd_ap_wps_pin(dev, params);
+	}
+
+	return ret;
+}
+#endif
+
+int hostapd_ap_enable(const struct device *dev,
+		      struct wifi_connect_req_params *params)
+{
+	struct hostapd_iface *iface;
+	struct hostapd_data *hapd;
+	struct wpa_driver_capa capa;
+	int ret;
+
+	if (!net_if_is_admin_up(net_if_lookup_by_dev(dev))) {
+		wpa_printf(MSG_ERROR,
+			   "Interface %s is down, dropping connect",
+			   dev->name);
+		return -1;
+	}
+
+	ret = set_ap_bandwidth(dev, params->bandwidth);
+	if (ret && (ret != -ENOTSUP)) {
+		wpa_printf(MSG_ERROR, "Failed to set ap bandwidth");
+		return -EINVAL;
+	}
+
+	k_mutex_lock(&hostapd_mutex, K_FOREVER);
+
+	iface = get_hostapd_handle(dev);
+	if (!iface) {
+		ret = -1;
+		wpa_printf(MSG_ERROR, "Interface %s not found", dev->name);
+		goto out;
+	}
+
+	iface->owner = iface;
+
+	if (iface->state == HAPD_IFACE_ENABLED) {
+		ret = -EBUSY;
+		wpa_printf(MSG_ERROR, "Interface %s is not in disable state", dev->name);
+		goto out;
+	}
+
+	ret = hapd_config_network(iface, params);
+	if (ret) {
+		wpa_printf(MSG_ERROR, "Failed to configure network for AP: %d", ret);
+		goto out;
+	}
+
+	hapd = iface->bss[0];
+	if (!iface->extended_capa || !iface->extended_capa_mask) {
+		if (hapd->driver->get_capa && hapd->driver->get_capa(hapd->drv_priv, &capa) == 0) {
+			iface->extended_capa         = capa.extended_capa;
+			iface->extended_capa_mask    = capa.extended_capa_mask;
+			iface->extended_capa_len     = capa.extended_capa_len;
+			iface->drv_max_acl_mac_addrs = capa.max_acl_mac_addrs;
+
+			/*
+			 * Override extended capa with per-interface type (AP), if
+			 * available from the driver.
+			 */
+			hostapd_get_ext_capa(iface);
+		} else {
+			ret = -1;
+			wpa_printf(MSG_ERROR, "Failed to get capability for AP: %d", ret);
+			goto out;
+		}
+	}
+
+	if (!hostapd_cli_cmd_v("enable")) {
+		goto out;
+	}
+out:
+	k_mutex_unlock(&hostapd_mutex);
+	return ret;
+}
+
+int hostapd_ap_disable(const struct device *dev)
+{
+	struct hostapd_iface *iface;
+	int ret = 0;
+
+	k_mutex_lock(&hostapd_mutex, K_FOREVER);
+
+	iface = get_hostapd_handle(dev);
+	if (!iface) {
+		ret = -ENOENT;
+		wpa_printf(MSG_ERROR, "Interface %s not found", dev->name);
+		goto out;
+	}
+
+	if (iface->state != HAPD_IFACE_ENABLED) {
+		ret = -EBUSY;
+		wpa_printf(MSG_ERROR, "Interface %s is not in enable state", dev->name);
+		goto out;
+	}
+
+	if (!hostapd_cli_cmd_v("disable")) {
+		goto out;
+	}
+
+	iface->freq = 0;
+
+out:
+	k_mutex_unlock(&hostapd_mutex);
+	return ret;
+}
+
+int hostapd_ap_sta_disconnect(const struct device *dev,
+			      const uint8_t *mac_addr)
+{
+	struct hostapd_iface *iface;
+	int ret  = 0;
+
+	k_mutex_lock(&hostapd_mutex, K_FOREVER);
+
+	iface = get_hostapd_handle(dev);
+	if (!iface) {
+		ret = -1;
+		wpa_printf(MSG_ERROR, "Interface %s not found", dev->name);
+		goto out;
+	}
+
+	if (iface->state != HAPD_IFACE_ENABLED) {
+		ret = -EBUSY;
+		wpa_printf(MSG_ERROR, "Interface %s is not in enable state", dev->name);
+		goto out;
+	}
+
+	if (!mac_addr) {
+		ret = -EINVAL;
+		wpa_printf(MSG_ERROR, "Invalid MAC address");
+		goto out;
+	}
+
+	if (!hostapd_cli_cmd_v("deauthenticate %02x:%02x:%02x:%02x:%02x:%02x",
+				mac_addr[0], mac_addr[1], mac_addr[2],
+				mac_addr[3], mac_addr[4], mac_addr[5])) {
+		goto out;
+	}
+
+out:
+	k_mutex_unlock(&hostapd_mutex);
+	return ret;
+}
+
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP
+int hostapd_dpp_dispatch(const struct device *dev, struct wifi_dpp_params *params)
+{
+	int ret;
+	char *cmd = NULL;
+
+	if (params == NULL) {
+		return -EINVAL;
+	}
+
+	cmd = os_zalloc(SUPPLICANT_DPP_CMD_BUF_SIZE);
+	if (cmd == NULL) {
+		return -ENOMEM;
+	}
+
+	/* leave one byte always be 0 */
+	ret = dpp_params_to_cmd(params, cmd, SUPPLICANT_DPP_CMD_BUF_SIZE - 2);
+	if (ret) {
+		os_free(cmd);
+		return ret;
+	}
+
+	wpa_printf(MSG_DEBUG, "hostapd_cli %s", cmd);
+	if (zephyr_hostapd_cli_cmd_resp(cmd, params->resp)) {
+		os_free(cmd);
+		return -ENOEXEC;
+	}
+
+	os_free(cmd);
+	return 0;
+}
+#endif /* CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP */
diff --git a/modules/hostap/src/hapd_api.h b/modules/hostap/src/hapd_api.h
new file mode 100644
index 00000000000..cc6f1fe7401
--- /dev/null
+++ b/modules/hostap/src/hapd_api.h
@@ -0,0 +1,91 @@
+/**
+ * Copyright 2023-2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __HAPD_API_H_
+#define __HAPD_API_H_
+
+#ifdef CONFIG_WIFI_NM_HOSTAPD_CRYPTO_ENTERPRISE
+int hostapd_add_enterprise_creds(const struct device *dev,
+			struct wifi_enterprise_creds_params *creds);
+#endif
+
+/**
+ * @brief Wi-Fi AP configuration parameter.
+ *
+ * @param dev Wi-Fi device
+ * @param params AP parameters
+ * @return 0 for OK; -1 for ERROR
+ */
+int hostapd_ap_config_params(const struct device *dev, struct wifi_ap_config_params *params);
+
+/**
+ * @brief Set Wi-Fi AP region domain
+ *
+ * @param reg_domain region domain parameters
+ * @return true for OK; false for ERROR
+ */
+bool hostapd_ap_reg_domain(struct wifi_reg_domain *reg_domain);
+
+#ifdef CONFIG_WIFI_NM_HOSTAPD_WPS
+/** Start AP WPS PBC/PIN
+ *
+ * @param dev Pointer to the device structure for the driver instance
+ * @param params wps operarion parameters
+ *
+ * @return 0 if ok, < 0 if error
+ */
+int hostapd_ap_wps_config(const struct device *dev, struct wifi_wps_config_params *params);
+#endif
+
+/**
+ * @brief Get Wi-Fi SAP status
+ *
+ * @param dev Wi-Fi device
+ * @param status SAP status
+ * @return 0 for OK; -1 for ERROR
+ */
+int hostapd_ap_status(const struct device *dev, struct wifi_iface_status *status);
+
+/**
+ * @brief Set Wi-Fi AP configuration
+ *
+ * @param dev Wi-Fi interface name to use
+ * @param params AP configuration parameters to set
+ * @return 0 for OK; -1 for ERROR
+ */
+int hostapd_ap_enable(const struct device *dev,
+		      struct wifi_connect_req_params *params);
+
+/**
+ * @brief Disable Wi-Fi AP
+ * @param dev Wi-Fi interface name to use
+ * @return 0 for OK; -1 for ERROR
+ */
+int hostapd_ap_disable(const struct device *dev);
+
+/**
+ * @brief Set Wi-Fi AP STA disconnect
+ * @param dev Wi-Fi interface name to use
+ * @param mac_addr MAC address of the station to disconnect
+ * @return 0 for OK; -1 for ERROR
+ */
+int hostapd_ap_sta_disconnect(const struct device *dev,
+			      const uint8_t *mac_addr);
+
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP
+#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
+/**
+ * @brief Dispatch DPP operations for AP
+ *
+ * @param dev Wi-Fi interface name to use
+ * @param dpp_params DPP action enum and params in string
+ * @return 0 for OK; -1 for ERROR
+ */
+int hostapd_dpp_dispatch(const struct device *dev, struct wifi_dpp_params *params);
+#endif /* CONFIG_WIFI_NM_HOSTAPD_AP */
+#endif /* CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP */
+
+#endif /* __HAPD_API_H_ */
diff --git a/modules/hostap/src/hapd_events.c b/modules/hostap/src/hapd_events.c
new file mode 100644
index 00000000000..c71015f7f92
--- /dev/null
+++ b/modules/hostap/src/hapd_events.c
@@ -0,0 +1,122 @@
+/**
+ * Copyright 2023-2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "includes.h"
+#include "common.h"
+#include "ap/sta_info.h"
+#include "ap/ieee802_11.h"
+#include "ap/hostapd.h"
+#include "wpa_supplicant_i.h"
+#include <zephyr/net/wifi_mgmt.h>
+#include "hapd_events.h"
+#include "supp_events.h"
+
+static enum wifi_link_mode hapd_get_sta_link_mode(struct hostapd_iface *iface,
+						  struct sta_info *sta)
+{
+	if (sta->flags & WLAN_STA_HE) {
+		return WIFI_6;
+	} else if (sta->flags & WLAN_STA_VHT) {
+		return WIFI_5;
+	} else if (sta->flags & WLAN_STA_HT) {
+		return WIFI_4;
+	} else if ((sta->flags & WLAN_STA_NONERP) ||
+		   (iface->current_mode->mode == HOSTAPD_MODE_IEEE80211B)) {
+		return WIFI_1;
+	} else if (iface->freq > 4000) {
+		return WIFI_2;
+	} else if (iface->freq > 2000) {
+		return WIFI_3;
+	} else {
+		return WIFI_LINK_MODE_UNKNOWN;
+	}
+}
+
+static bool hapd_is_twt_capable(struct hostapd_iface *iface, struct sta_info *sta)
+{
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_11AX
+	return hostapd_get_he_twt_responder(iface->bss[0], IEEE80211_MODE_AP);
+#else
+	return false;
+#endif
+}
+
+int hostapd_send_wifi_mgmt_ap_status(struct hostapd_iface *iface,
+				     enum net_event_wifi_cmd event,
+				     enum wifi_ap_status ap_status)
+{
+	char *ifname = iface->conf->bss[0]->iface;
+	int status = ap_status;
+
+	return supplicant_send_wifi_mgmt_event(ifname,
+					       event,
+					       (void *)&status,
+					       sizeof(int));
+}
+
+int hostapd_send_wifi_mgmt_ap_sta_event(struct hostapd_iface *ap_ctx,
+					enum net_event_wifi_cmd event,
+					void *data)
+{
+	struct sta_info *sta = data;
+	char *ifname = ap_ctx->bss[0]->conf->iface;
+	struct wifi_ap_sta_info sta_info = { 0 };
+
+	if (!ap_ctx || !sta) {
+		return -EINVAL;
+	}
+
+	memcpy(sta_info.mac, sta->addr, sizeof(sta_info.mac));
+
+	if (event == NET_EVENT_WIFI_CMD_AP_STA_CONNECTED) {
+		sta_info.link_mode = hapd_get_sta_link_mode(ap_ctx, sta);
+		sta_info.twt_capable = hapd_is_twt_capable(ap_ctx, sta);
+	}
+
+	return supplicant_send_wifi_mgmt_event(ifname,
+					       event,
+					       (void *)&sta_info,
+					       sizeof(sta_info));
+}
+
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP
+void hostapd_handle_dpp_event(void *ctx, char *buf, size_t len)
+{
+	struct hostapd_data *hapd = (struct hostapd_data *)ctx;
+
+	if (hapd == NULL) {
+		return;
+	}
+
+	struct hostapd_bss_config *conf = hapd->conf;
+
+	if (conf == NULL || !(conf->wpa_key_mgmt & WPA_KEY_MGMT_DPP)) {
+		return;
+	}
+
+	/* check hostapd */
+	if (!strncmp(buf, DPP_EVENT_CONNECTOR, sizeof(DPP_EVENT_CONNECTOR) - 1)) {
+		if (conf->dpp_connector) {
+			os_free(conf->dpp_connector);
+		}
+
+		conf->dpp_connector = os_strdup(buf + sizeof(DPP_EVENT_CONNECTOR) - 1);
+	} else if (!strncmp(buf, DPP_EVENT_C_SIGN_KEY, sizeof(DPP_EVENT_C_SIGN_KEY) - 1)) {
+		if (conf->dpp_csign) {
+			wpabuf_free(conf->dpp_csign);
+		}
+
+		conf->dpp_csign = wpabuf_parse_bin(buf + sizeof(DPP_EVENT_C_SIGN_KEY) - 1);
+	} else if (!strncmp(buf, DPP_EVENT_NET_ACCESS_KEY, sizeof(DPP_EVENT_NET_ACCESS_KEY) - 1)) {
+		if (conf->dpp_netaccesskey) {
+			wpabuf_free(conf->dpp_netaccesskey);
+		}
+
+		conf->dpp_netaccesskey =
+			wpabuf_parse_bin(buf + sizeof(DPP_EVENT_NET_ACCESS_KEY) - 1);
+	}
+}
+#endif /* CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP */
diff --git a/modules/hostap/src/hapd_events.h b/modules/hostap/src/hapd_events.h
new file mode 100644
index 00000000000..66ea7f6e1cc
--- /dev/null
+++ b/modules/hostap/src/hapd_events.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2023 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __HAPD_EVENTS_H__
+#define __HAPD_EVENTS_H__
+
+#include <zephyr/net/wifi_mgmt.h>
+
+int hostapd_send_wifi_mgmt_ap_status(struct hostapd_iface *iface,
+				     enum net_event_wifi_cmd event,
+				     enum wifi_ap_status ap_status);
+
+int hostapd_send_wifi_mgmt_ap_sta_event(struct hostapd_iface *ap_ctx,
+					enum net_event_wifi_cmd event,
+					void *data);
+
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP
+void hostapd_handle_dpp_event(void *ctx, char *buf, size_t len);
+#endif
+
+#endif /* __HAPD_EVENTS_H_ */
diff --git a/modules/hostap/src/hapd_main.c b/modules/hostap/src/hapd_main.c
new file mode 100644
index 00000000000..6c5e9c6d998
--- /dev/null
+++ b/modules/hostap/src/hapd_main.c
@@ -0,0 +1,554 @@
+/**
+ * Copyright 2023-2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/net/wifi_mgmt.h>
+#include <zephyr/net/wifi_nm.h>
+#include "includes.h"
+#include "common.h"
+#include "eloop.h"
+#include "wpa_supplicant_i.h"
+#include "hostapd.h"
+#include "hostapd_cli_zephyr.h"
+#include "eap_register.h"
+#include "ap_drv_ops.h"
+#include "l2_packet/l2_packet.h"
+#include "supp_main.h"
+#include "hapd_main.h"
+#include "supp_api.h"
+#include "hapd_api.h"
+#include "hapd_events.h"
+
+static const struct wifi_mgmt_ops mgmt_ap_ops = {
+	.ap_enable = hostapd_ap_enable,
+	.ap_disable = hostapd_ap_disable,
+	.ap_sta_disconnect = hostapd_ap_sta_disconnect,
+	.iface_status = hostapd_ap_status,
+#ifdef CONFIG_WIFI_NM_HOSTAPD_WPS
+	.wps_config = hostapd_ap_wps_config,
+#endif
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP
+	.dpp_dispatch = hostapd_dpp_dispatch,
+#endif /* CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP */
+	.ap_config_params = hostapd_ap_config_params,
+	.set_rts_threshold = supplicant_set_rts_threshold,
+#ifdef CONFIG_WIFI_NM_HOSTAPD_CRYPTO_ENTERPRISE
+	.enterprise_creds = hostapd_add_enterprise_creds,
+#endif
+	.set_btwt = supplicant_set_btwt,
+};
+
+DEFINE_WIFI_NM_INSTANCE(hostapd, &mgmt_ap_ops);
+
+struct hapd_global {
+	void **drv_priv;
+	size_t drv_count;
+};
+
+static struct hapd_global hglobal;
+
+#ifndef HOSTAPD_CLEANUP_INTERVAL
+#define HOSTAPD_CLEANUP_INTERVAL 10
+#endif /* HOSTAPD_CLEANUP_INTERVAL */
+
+static int hostapd_periodic_call(struct hostapd_iface *iface, void *ctx)
+{
+	hostapd_periodic_iface(iface);
+	return 0;
+}
+
+/* Periodic cleanup tasks */
+static void hostapd_periodic(void *eloop_ctx, void *timeout_ctx)
+{
+	struct hapd_interfaces *interfaces = eloop_ctx;
+
+	eloop_register_timeout(HOSTAPD_CLEANUP_INTERVAL, 0,
+			       hostapd_periodic, interfaces, NULL);
+	hostapd_for_each_interface(interfaces, hostapd_periodic_call, NULL);
+}
+
+struct hostapd_iface *zephyr_get_hapd_handle_by_ifname(const char *ifname)
+{
+	struct hapd_interfaces *interfaces = zephyr_get_default_hapd_context();
+	struct hostapd_data *hapd = NULL;
+
+	hapd = hostapd_get_iface(interfaces, ifname);
+	if (!hapd) {
+		wpa_printf(MSG_ERROR, "%s: Unable to get hapd handle for %s\n", __func__, ifname);
+		return NULL;
+	}
+
+	return hapd->iface;
+}
+
+static void hostapd_event_eapol_rx_cb(void *ctx, const u8 *src_addr,
+				      const u8 *buf, size_t len)
+{
+	hostapd_event_eapol_rx(ctx, src_addr, buf, len, FRAME_ENCRYPTION_UNKNOWN, -1);
+}
+
+struct hostapd_iface *hostapd_get_interface(const char *ifname)
+{
+	struct hapd_interfaces *interfaces = zephyr_get_default_hapd_context();
+
+	return interfaces->iface[0];
+}
+
+static int hostapd_enable_iface_cb(struct hostapd_iface *hapd_iface)
+{
+	struct hostapd_data *bss;
+
+	wpa_printf(MSG_DEBUG, "Enable interface %s", hapd_iface->conf->bss[0]->iface);
+
+	bss = hapd_iface->bss[0];
+
+	bss->conf->start_disabled = 0;
+
+	if (hostapd_config_check(hapd_iface->conf, 1) < 0) {
+		wpa_printf(MSG_INFO, "Invalid configuration - cannot enable");
+		return -1;
+	}
+
+	l2_packet_deinit(bss->l2);
+	bss->l2 = l2_packet_init(bss->conf->iface, bss->conf->bssid, ETH_P_EAPOL,
+				 &hostapd_event_eapol_rx_cb, bss, 0);
+	if (bss->l2 == NULL) {
+		wpa_printf(MSG_ERROR, "Failed to initialize l2 for hostapd interface");
+		return -1;
+	}
+
+	if (hostapd_setup_interface(hapd_iface)) {
+		wpa_printf(MSG_ERROR, "Failed to initialize hostapd interface");
+		return -1;
+	}
+
+	return 0;
+}
+
+static int hostapd_disable_iface_cb(struct hostapd_iface *hapd_iface)
+{
+	size_t j;
+	struct hostapd_data *hapd = NULL;
+
+	wpa_msg(hapd_iface->bss[0]->msg_ctx, MSG_INFO, AP_EVENT_DISABLED);
+
+	hapd_iface->driver_ap_teardown = !!(hapd_iface->drv_flags
+					    & WPA_DRIVER_FLAGS_AP_TEARDOWN_SUPPORT);
+
+#ifdef NEED_AP_MLME
+	for (j = 0; j < hapd_iface->num_bss; j++) {
+		hostapd_cleanup_cs_params(hapd_iface->bss[j]);
+	}
+#endif /* NEED_AP_MLME */
+
+	/* Same as hostapd_interface_deinit() without deinitializing control
+	 * interface
+	 */
+	for (j = 0; j < hapd_iface->num_bss; j++) {
+		hapd = hapd_iface->bss[j];
+		hostapd_bss_deinit_no_free(hapd);
+		hostapd_free_hapd_data(hapd);
+	}
+
+	hostapd_drv_stop_ap(hapd);
+
+	hostapd_cleanup_iface_partial(hapd_iface);
+
+	wpa_printf(MSG_DEBUG, "Interface %s disabled", hapd_iface->bss[0]->conf->iface);
+	hostapd_set_state(hapd_iface, HAPD_IFACE_DISABLED);
+	hostapd_send_wifi_mgmt_ap_status(hapd_iface,
+					 NET_EVENT_WIFI_CMD_AP_DISABLE_RESULT,
+					 WIFI_STATUS_AP_SUCCESS);
+	hostapd_config_free(hapd_iface->conf);
+	hapd_iface->conf = hapd_iface->interfaces->config_read_cb(hapd_iface->config_fname);
+	for (j = 0; j < hapd_iface->num_bss; j++) {
+		hapd = hapd_iface->bss[j];
+		hapd->iconf = hapd_iface->conf;
+		hapd->conf = hapd_iface->conf->bss[j];
+		hapd->driver = hapd_iface->conf->driver;
+	}
+
+	return 0;
+}
+
+static int hostapd_global_init(struct hapd_interfaces *interfaces, const char *entropy_file)
+{
+	int i;
+
+	os_memset(&hglobal, 0, sizeof(struct hapd_global));
+
+	if (eap_server_register_methods()) {
+		wpa_printf(MSG_ERROR, "Failed to register EAP methods");
+		return -1;
+	}
+
+	interfaces->eloop_initialized = 1;
+
+	for (i = 0; wpa_drivers[i]; i++) {
+		hglobal.drv_count++;
+	}
+
+	if (hglobal.drv_count == 0) {
+		wpa_printf(MSG_ERROR, "No drivers enabled");
+		return -1;
+	}
+	hglobal.drv_priv = os_calloc(hglobal.drv_count, sizeof(void *));
+	if (hglobal.drv_priv == NULL) {
+		return -1;
+	}
+
+	return 0;
+}
+
+static int hostapd_driver_init(struct hostapd_iface *iface)
+{
+	struct wpa_init_params params;
+	size_t i;
+	struct hostapd_data *hapd       = iface->bss[0];
+	struct hostapd_bss_config *conf = hapd->conf;
+	u8 *b                           = conf->bssid;
+	struct wpa_driver_capa capa;
+
+	if (hapd->driver == NULL || hapd->driver->hapd_init == NULL) {
+		wpa_printf(MSG_ERROR, "No hostapd driver wrapper available");
+		return -1;
+	}
+
+	/* Initialize the driver interface */
+	if (!(b[0] | b[1] | b[2] | b[3] | b[4] | b[5])) {
+		b = NULL;
+	}
+
+	os_memset(&params, 0, sizeof(params));
+	for (i = 0; wpa_drivers[i]; i++) {
+		if (wpa_drivers[i] != hapd->driver) {
+			continue;
+		}
+
+		if (hglobal.drv_priv[i] == NULL && wpa_drivers[i]->global_init) {
+			hglobal.drv_priv[i] = wpa_drivers[i]->global_init(iface->interfaces);
+			if (hglobal.drv_priv[i] == NULL) {
+				wpa_printf(MSG_ERROR, "Failed to initialize driver '%s'",
+					   wpa_drivers[i]->name);
+				return -1;
+			}
+			hglobal.drv_count++;
+		}
+
+		params.global_priv = hglobal.drv_priv[i];
+		break;
+	}
+	params.bssid              = b;
+	params.ifname             = hapd->conf->iface;
+	params.driver_params      = hapd->iconf->driver_params;
+	params.use_pae_group_addr = hapd->conf->use_pae_group_addr;
+	params.num_bridge         = hapd->iface->num_bss;
+	params.bridge             = os_calloc(hapd->iface->num_bss, sizeof(char *));
+	if (params.bridge == NULL) {
+		return -1;
+	}
+	for (i = 0; i < hapd->iface->num_bss; i++) {
+		struct hostapd_data *bss = hapd->iface->bss[i];
+
+		if (bss->conf->bridge[0]) {
+			params.bridge[i] = bss->conf->bridge;
+		}
+	}
+
+	params.own_addr = hapd->own_addr;
+
+	hapd->drv_priv = hapd->driver->hapd_init(hapd, &params);
+	os_free(params.bridge);
+	if (hapd->drv_priv == NULL) {
+		wpa_printf(MSG_ERROR, "%s driver initialization failed.",
+			   hapd->driver->name);
+		hapd->driver = NULL;
+		return -1;
+	}
+
+	if (hapd->driver->get_capa && hapd->driver->get_capa(hapd->drv_priv, &capa) == 0) {
+		struct wowlan_triggers *triggs;
+
+		iface->drv_flags           = capa.flags;
+		iface->drv_flags2          = capa.flags2;
+		iface->probe_resp_offloads = capa.probe_resp_offloads;
+		/*
+		 * Use default extended capa values from per-radio information
+		 */
+		iface->extended_capa         = capa.extended_capa;
+		iface->extended_capa_mask    = capa.extended_capa_mask;
+		iface->extended_capa_len     = capa.extended_capa_len;
+		iface->drv_max_acl_mac_addrs = capa.max_acl_mac_addrs;
+
+		/*
+		 * Override extended capa with per-interface type (AP), if
+		 * available from the driver.
+		 */
+		hostapd_get_ext_capa(iface);
+
+		triggs = wpa_get_wowlan_triggers(conf->wowlan_triggers, &capa);
+		if (triggs && hapd->driver->set_wowlan) {
+			if (hapd->driver->set_wowlan(hapd->drv_priv, triggs)) {
+				wpa_printf(MSG_ERROR, "set_wowlan failed");
+			}
+		}
+		os_free(triggs);
+	}
+
+	return 0;
+}
+
+struct hostapd_config *hostapd_config_read2(const char *fname)
+{
+	struct hostapd_config *conf;
+	const struct device *dev;
+	char ifname[IFNAMSIZ + 1] = {0};
+	int errors = 0;
+	size_t i;
+	int aCWmin = 4, aCWmax = 10;
+	/* background traffic */
+	struct hostapd_wmm_ac_params ac_bk = {aCWmin, aCWmax, 9, 0, 0};
+	/* best effort traffic */
+	struct hostapd_wmm_ac_params ac_be = {aCWmin, aCWmax - 4, 5, 0, 0};
+	/* video traffic */
+	struct hostapd_wmm_ac_params ac_vi = {aCWmin - 1, aCWmin, 3,
+					      3008 / 32, 0};
+	/* voice traffic */
+	struct hostapd_wmm_ac_params ac_vo = {aCWmin - 2, aCWmin - 1, 3,
+					      1504 / 32, 0};
+
+	dev = net_if_get_device(net_if_get_wifi_sap());
+	strncpy(ifname, dev->name, IFNAMSIZ);
+	ifname[IFNAMSIZ] = '\0';
+
+	conf = hostapd_config_defaults();
+	if (conf == NULL) {
+		return NULL;
+	}
+
+	conf->wmm_ac_params[0] = ac_be;
+	conf->wmm_ac_params[1] = ac_bk;
+	conf->wmm_ac_params[2] = ac_vi;
+	conf->wmm_ac_params[3] = ac_vo;
+
+	/* set default driver based on configuration */
+	conf->driver = wpa_drivers[0];
+	if (conf->driver == NULL) {
+		wpa_printf(MSG_ERROR, "No driver wrappers registered!");
+		hostapd_config_free(conf);
+		return NULL;
+	}
+	conf->last_bss = conf->bss[0];
+	struct hostapd_bss_config *bss;
+
+	bss                 = conf->last_bss;
+	bss->start_disabled = 1;
+	bss->max_num_sta    = CONFIG_WIFI_MGMT_AP_MAX_NUM_STA;
+	bss->dtim_period    = 1;
+	os_strlcpy(conf->bss[0]->iface, ifname, sizeof(conf->bss[0]->iface));
+	bss->logger_stdout_level = HOSTAPD_LEVEL_INFO;
+	bss->logger_stdout       = 0xffff;
+	bss->nas_identifier      = os_strdup("ap.example.com");
+	os_memcpy(conf->country, "US ", 3);
+	conf->hw_mode        = HOSTAPD_MODE_IEEE80211G;
+	bss->wps_state       = WPS_STATE_CONFIGURED;
+	bss->eap_server      = 1;
+#ifdef CONFIG_WPS
+	bss->ap_setup_locked = 1;
+#endif
+	conf->channel        = 1;
+	conf->acs            = conf->channel == 0;
+#ifdef CONFIG_ACS
+	conf->acs_num_scans  = 1;
+#endif
+	conf->ieee80211n     = 1;
+	conf->ieee80211h     = 0;
+	conf->ieee80211d     = 1;
+	conf->acs_exclude_dfs = 1;
+	conf->ht_capab |= HT_CAP_INFO_SHORT_GI20MHZ;
+	bss->auth_algs = 1;
+	bss->okc = 1;
+	conf->no_pri_sec_switch = 1;
+	conf->ht_op_mode_fixed  = 1;
+	conf->ieee80211ac       = 1;
+	conf->vht_oper_chwidth  = CHANWIDTH_USE_HT;
+	conf->vht_capab |= VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MAX;
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_11AX
+	conf->ieee80211ax       = 1;
+	conf->he_oper_chwidth   = CHANWIDTH_USE_HT;
+	conf->he_phy_capab.he_su_beamformer = 0;
+	conf->he_phy_capab.he_su_beamformee = 1;
+	conf->he_phy_capab.he_mu_beamformer = 0;
+	conf->he_op.he_bss_color = 1;
+	conf->he_op.he_default_pe_duration  = 0;
+	/* Set default basic MCS/NSS set to single stream MCS 0-7 */
+	conf->he_op.he_basic_mcs_nss_set    = 0xfffc;
+#endif
+
+	for (i = 0; i < conf->num_bss; i++) {
+		hostapd_set_security_params(conf->bss[i], 1);
+	}
+
+	if (hostapd_config_check(conf, 1)) {
+		errors++;
+	}
+
+#ifndef WPA_IGNORE_CONFIG_ERRORS
+	if (errors) {
+		wpa_printf(MSG_ERROR, "%d errors found in configuration file '%s'",
+			   errors, fname);
+		hostapd_config_free(conf);
+		conf = NULL;
+	}
+#endif /* WPA_IGNORE_CONFIG_ERRORS */
+	return conf;
+}
+
+static struct hostapd_iface *hostapd_interface_init(struct hapd_interfaces *interfaces,
+						    const char *if_name,
+						    const char *config_fname,
+						    int debug)
+{
+	struct hostapd_iface *iface;
+	int k;
+
+	wpa_printf(MSG_DEBUG, "Configuration file: %s", config_fname);
+	iface = hostapd_init(interfaces, config_fname);
+	if (!iface) {
+		return NULL;
+	}
+
+	if (if_name) {
+		os_strlcpy(iface->conf->bss[0]->iface, if_name,
+			   sizeof(iface->conf->bss[0]->iface));
+	}
+
+	iface->interfaces = interfaces;
+
+	for (k = 0; k < debug; k++) {
+		if (iface->bss[0]->conf->logger_stdout_level > 0) {
+			iface->bss[0]->conf->logger_stdout_level--;
+		}
+	}
+
+	if (iface->conf->bss[0]->iface[0] == '\0' &&
+	    !hostapd_drv_none(iface->bss[0])) {
+		wpa_printf(MSG_ERROR,
+			   "Interface name not specified in %s, nor by '-i' parameter",
+			   config_fname);
+		hostapd_interface_deinit_free(iface);
+		return NULL;
+	}
+
+	iface->bss[0]->is_hostapd = 1;
+
+	return iface;
+}
+
+void zephyr_hostapd_init(struct hapd_interfaces *interfaces)
+{
+	size_t i;
+	int ret, debug = 0;
+	struct net_if *iface;
+	char ifname[IFNAMSIZ + 1] = { 0 };
+	const char *entropy_file = NULL;
+	size_t num_bss_configs = 0;
+	int start_ifaces_in_sync = 0;
+#ifdef CONFIG_DPP
+	struct dpp_global_config dpp_conf;
+#endif /* CONFIG_DPP */
+
+	os_memset(interfaces, 0, sizeof(struct hapd_interfaces));
+	interfaces->reload_config      = hostapd_reload_config;
+	interfaces->config_read_cb     = hostapd_config_read2;
+	interfaces->for_each_interface = hostapd_for_each_interface;
+	interfaces->driver_init        = hostapd_driver_init;
+	interfaces->global_ctrl_sock   = -1;
+	dl_list_init(&interfaces->global_ctrl_dst);
+#ifdef CONFIG_DPP
+	os_memset(&dpp_conf, 0, sizeof(dpp_conf));
+	dpp_conf.cb_ctx = interfaces;
+	interfaces->dpp = dpp_global_init(&dpp_conf);
+	if (!interfaces->dpp) {
+		return;
+	}
+#endif /* CONFIG_DPP */
+
+	interfaces->count = 1;
+	if (interfaces->count || num_bss_configs) {
+		interfaces->iface = os_calloc(interfaces->count + num_bss_configs,
+					      sizeof(struct hostapd_iface *));
+		if (interfaces->iface == NULL) {
+			wpa_printf(MSG_ERROR, "malloc failed");
+			return;
+		}
+	}
+
+	if (hostapd_global_init(interfaces, entropy_file)) {
+		wpa_printf(MSG_ERROR, "Failed to initialize global context");
+		return;
+	}
+
+	eloop_register_timeout(HOSTAPD_CLEANUP_INTERVAL, 0,
+			       hostapd_periodic, interfaces, NULL);
+
+	iface = net_if_get_wifi_sap();
+	ret = net_if_get_name(iface, ifname, sizeof(ifname) - 1);
+	if (ret < 0) {
+		wpa_printf(MSG_ERROR, "Cannot get interface %d (%p) name",
+			   net_if_get_by_iface(iface), iface);
+		goto out;
+	}
+
+	for (i = 0; i < interfaces->count; i++) {
+		interfaces->iface[i] = hostapd_interface_init(interfaces, ifname,
+							      "hostapd.conf", debug);
+		if (!interfaces->iface[i]) {
+			wpa_printf(MSG_ERROR, "Failed to initialize interface");
+			goto out;
+		}
+		if (start_ifaces_in_sync) {
+			interfaces->iface[i]->need_to_start_in_sync = 0;
+		}
+	}
+
+	/*
+	 * Enable configured interfaces. Depending on channel configuration,
+	 * this may complete full initialization before returning or use a
+	 * callback mechanism to complete setup in case of operations like HT
+	 * co-ex scans, ACS, or DFS are needed to determine channel parameters.
+	 * In such case, the interface will be enabled from eloop context within
+	 * hostapd_global_run().
+	 */
+	interfaces->terminate_on_error = 0;
+	for (i = 0; i < interfaces->count; i++) {
+		if (hostapd_driver_init(interfaces->iface[i])) {
+			goto out;
+		}
+		interfaces->iface[i]->enable_iface_cb  = hostapd_enable_iface_cb;
+		interfaces->iface[i]->disable_iface_cb = hostapd_disable_iface_cb;
+		zephyr_hostapd_ctrl_init((void *)interfaces->iface[i]->bss[0]);
+	}
+
+out:
+	return;
+}
+
+void zephyr_hostapd_msg(void *ctx, const char *txt, size_t len)
+{
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP
+	struct hostapd_data *hapd = (struct hostapd_data *)ctx;
+#endif
+
+	if (!ctx || !txt) {
+		return;
+	}
+
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP
+	if (strncmp(txt, "DPP", 3) == 0) {
+		hostapd_handle_dpp_event(hapd, (char *)txt, len);
+	}
+#endif
+}
diff --git a/modules/hostap/src/hapd_main.h b/modules/hostap/src/hapd_main.h
new file mode 100644
index 00000000000..9f23d3e959c
--- /dev/null
+++ b/modules/hostap/src/hapd_main.h
@@ -0,0 +1,15 @@
+/**
+ * Copyright 2023-2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __HAPD_MAIN_H_
+#define __HAPD_MAIN_H_
+
+#include "common.h"
+
+struct hostapd_iface *zephyr_get_hapd_handle_by_ifname(const char *ifname);
+void zephyr_hostapd_init(struct hapd_interfaces *interfaces);
+void zephyr_hostapd_msg(void *ctx, const char *txt, size_t len);
+#endif /* __HAPD_MAIN_H_ */
diff --git a/modules/hostap/src/supp_api.c b/modules/hostap/src/supp_api.c
index 8be2b085bdd..4b0c156ca46 100644
--- a/modules/hostap/src/supp_api.c
+++ b/modules/hostap/src/supp_api.c
@@ -22,12 +22,12 @@
 #include "supp_main.h"
 #include "supp_api.h"
 #include "wpa_cli_zephyr.h"
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-#include "hostapd.h"
-#include "hostapd_cli_zephyr.h"
-#include "ap_drv_ops.h"
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
+#include "eap_peer/eap.h"
 #endif
 #include "supp_events.h"
+#include "hostapd.h"
+#include "hapd_api.h"
 #include "wpa_supplicant/bss.h"
 
 extern struct k_sem wpa_supplicant_ready_sem;
@@ -122,50 +122,6 @@ static struct wpa_supplicant *get_wpa_s_handle(const struct device *dev)
 	return wpa_s;
 }
 
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-#define hostapd_cli_cmd_v(cmd, ...) ({					\
-	bool status;							\
-									\
-	if (zephyr_hostapd_cli_cmd_v(cmd, ##__VA_ARGS__) < 0) {		\
-		wpa_printf(MSG_ERROR,					\
-			   "Failed to execute wpa_cli command: %s",	\
-			   cmd);					\
-		status = false;						\
-	} else {							\
-		status = true;						\
-	}								\
-									\
-	status;								\
-})
-
-static inline struct hostapd_iface *get_hostapd_handle(const struct device *dev)
-{
-	struct net_if *iface = net_if_lookup_by_dev(dev);
-	char if_name[CONFIG_NET_INTERFACE_NAME_LEN + 1];
-	struct hostapd_iface *hapd;
-	int ret;
-
-	if (!iface) {
-		wpa_printf(MSG_ERROR, "Interface for device %s not found", dev->name);
-		return NULL;
-	}
-
-	ret = net_if_get_name(iface, if_name, sizeof(if_name));
-	if (!ret) {
-		wpa_printf(MSG_ERROR, "Cannot get interface name (%d)", ret);
-		return NULL;
-	}
-
-	hapd = zephyr_get_hapd_handle_by_ifname(if_name);
-	if (!hapd) {
-		wpa_printf(MSG_ERROR, "Interface %s not found", if_name);
-		return NULL;
-	}
-
-	return hapd;
-}
-#endif
-
 #define WPA_SUPP_STATE_POLLING_MS 10
 static int wait_for_disconnect_complete(const struct device *dev)
 {
@@ -350,7 +306,7 @@ static inline int chan_to_freq(int chan)
 	return freq;
 }
 
-static inline enum wifi_frequency_bands wpas_band_to_zephyr(enum wpa_radio_work_band band)
+enum wifi_frequency_bands wpas_band_to_zephyr(enum wpa_radio_work_band band)
 {
 	switch (band) {
 	case BAND_2_4_GHZ:
@@ -362,13 +318,77 @@ static inline enum wifi_frequency_bands wpas_band_to_zephyr(enum wpa_radio_work_
 	}
 }
 
-static inline enum wifi_security_type wpas_key_mgmt_to_zephyr(int key_mgmt, int proto, int pwe)
+enum wifi_wpa3_enterprise_type wpas_key_mgmt_to_zephyr_wpa3_ent(int key_mgmt)
+{
+	switch (key_mgmt) {
+	case WPA_KEY_MGMT_IEEE8021X_SUITE_B:
+		return WIFI_WPA3_ENTERPRISE_SUITEB;
+	case WPA_KEY_MGMT_IEEE8021X_SUITE_B_192:
+		return WIFI_WPA3_ENTERPRISE_SUITEB_192;
+	case WPA_KEY_MGMT_IEEE8021X_SHA256:
+		return WIFI_WPA3_ENTERPRISE_ONLY;
+	default:
+		return WIFI_WPA3_ENTERPRISE_NA;
+	}
+}
+
+enum wifi_security_type wpas_key_mgmt_to_zephyr(bool is_hapd, void *config, int key_mgmt,
+						int proto, int pwe)
 {
 	switch (key_mgmt) {
+#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
 	case WPA_KEY_MGMT_IEEE8021X:
 	case WPA_KEY_MGMT_IEEE8021X_SUITE_B:
 	case WPA_KEY_MGMT_IEEE8021X_SUITE_B_192:
+	case WPA_KEY_MGMT_IEEE8021X_SHA256:
+		if (is_hapd) {
+#ifdef CONFIG_WIFI_NM_HOSTAPD_CRYPTO_ENTERPRISE
+			struct hostapd_bss_config *conf = (struct hostapd_bss_config *)config;
+
+			switch (conf->eap_user->methods[0].method) {
+			case WIFI_EAP_TYPE_PEAP:
+				if (conf->eap_user->next && conf->eap_user->next->phase2) {
+					switch (conf->eap_user->next->methods[0].method) {
+					case WIFI_EAP_TYPE_MSCHAPV2:
+						return WIFI_SECURITY_TYPE_EAP_PEAP_MSCHAPV2;
+					case WIFI_EAP_TYPE_GTC:
+						return WIFI_SECURITY_TYPE_EAP_PEAP_GTC;
+					case WIFI_EAP_TYPE_TLS:
+						return WIFI_SECURITY_TYPE_EAP_PEAP_TLS;
+					}
+				}
+			case WIFI_EAP_TYPE_TTLS:
+				if (conf->eap_user->next && conf->eap_user->next->phase2) {
+					if (conf->eap_user->next->ttls_auth & 0x1E) {
+						return WIFI_SECURITY_TYPE_EAP_TTLS_MSCHAPV2;
+					}
+				}
+			}
+#endif
+		} else {
+			struct wpa_ssid *ssid = (struct wpa_ssid *)config;
+
+			switch (ssid->eap.eap_methods->method) {
+			case WIFI_EAP_TYPE_TTLS:
+				if (!os_memcmp(ssid->eap.phase2, "auth=MSCHAPV2",
+							   os_strlen(ssid->eap.phase2))) {
+					return WIFI_SECURITY_TYPE_EAP_TTLS_MSCHAPV2;
+				}
+			case WIFI_EAP_TYPE_PEAP:
+				if (!os_memcmp(ssid->eap.phase2, "auth=MSCHAPV2",
+							   os_strlen(ssid->eap.phase2))) {
+					return WIFI_SECURITY_TYPE_EAP_PEAP_MSCHAPV2;
+				} else if (!os_memcmp(ssid->eap.phase2, "auth=GTC",
+							os_strlen(ssid->eap.phase2))) {
+					return WIFI_SECURITY_TYPE_EAP_PEAP_GTC;
+				} else if (!os_memcmp(ssid->eap.phase2, "auth=TLS",
+							os_strlen(ssid->eap.phase2))) {
+					return WIFI_SECURITY_TYPE_EAP_PEAP_TLS;
+				}
+			}
+		}
 		return WIFI_SECURITY_TYPE_EAP_TLS;
+#endif
 	case WPA_KEY_MGMT_NONE:
 		return WIFI_SECURITY_TYPE_NONE;
 	case WPA_KEY_MGMT_PSK:
@@ -397,6 +417,8 @@ static inline enum wifi_security_type wpas_key_mgmt_to_zephyr(int key_mgmt, int
 		return WIFI_SECURITY_TYPE_FT_EAP;
 	case WPA_KEY_MGMT_FT_IEEE8021X_SHA384:
 		return WIFI_SECURITY_TYPE_FT_EAP_SHA384;
+	case WPA_KEY_MGMT_SAE_EXT_KEY:
+		return WIFI_SECURITY_TYPE_SAE_EXT_KEY;
 	default:
 		return WIFI_SECURITY_TYPE_UNKNOWN;
 	}
@@ -490,13 +512,13 @@ int process_cipher_config(struct wifi_connect_req_params *params,
 	unsigned int gropu_mgmt_cipher_capa;
 	unsigned int index;
 
-	if (params->suiteb_type == WIFI_SUITEB) {
+	if (params->wpa3_ent_mode == WIFI_WPA3_ENTERPRISE_SUITEB) {
 		cipher_capa = WPA_CAPA_ENC_GCMP;
 		gropu_mgmt_cipher_capa = WPA_CAPA_ENC_BIP_GMAC_128;
 		cipher_config->key_mgmt = "WPA-EAP-SUITE-B";
 		cipher_config->openssl_ciphers = "SUITEB128";
 		cipher_config->tls_flags = "[SUITEB]";
-	} else if (params->suiteb_type == WIFI_SUITEB_192) {
+	} else if (params->wpa3_ent_mode == WIFI_WPA3_ENTERPRISE_SUITEB_192) {
 		cipher_capa = WPA_CAPA_ENC_GCMP_256;
 		gropu_mgmt_cipher_capa = WPA_CAPA_ENC_BIP_GMAC_256;
 		if (params->ft_used) {
@@ -506,6 +528,10 @@ int process_cipher_config(struct wifi_connect_req_params *params,
 		}
 		cipher_config->openssl_ciphers = "SUITEB192";
 		cipher_config->tls_flags = "[SUITEB]";
+	} else if (params->wpa3_ent_mode == WIFI_WPA3_ENTERPRISE_ONLY) {
+		cipher_capa = WPA_CAPA_ENC_CCMP;
+		gropu_mgmt_cipher_capa = WPA_CAPA_ENC_BIP;
+		cipher_config->key_mgmt = "WPA-EAP-SHA256";
 	} else {
 		cipher_capa = WPA_CAPA_ENC_CCMP;
 		gropu_mgmt_cipher_capa = WPA_CAPA_ENC_BIP;
@@ -546,7 +572,7 @@ int process_cipher_config(struct wifi_connect_req_params *params,
 	return -EINVAL;
 }
 
-static int is_eap_valid_security(int security)
+int is_eap_valid_security(int security)
 {
 	return (security == WIFI_SECURITY_TYPE_EAP_TLS ||
 		    security == WIFI_SECURITY_TYPE_EAP_PEAP_MSCHAPV2 ||
@@ -556,276 +582,6 @@ static int is_eap_valid_security(int security)
 }
 #endif
 
-#ifdef CONFIG_WIFI_NM_HOSTAPD_CRYPTO_ENTERPRISE
-static int hapd_process_cert_data(struct hostapd_bss_config *conf,
-	char *type, uint8_t *data, uint32_t data_len)
-{
-	if (os_strcmp(type, "ca_cert_blob") == 0) {
-		conf->ca_cert_blob = data;
-		conf->ca_cert_blob_len = data_len;
-	} else if (os_strcmp(type, "server_cert_blob") == 0) {
-		conf->server_cert_blob = data;
-		conf->server_cert_blob_len = data_len;
-	} else if (os_strcmp(type, "private_key_blob") == 0) {
-		conf->private_key_blob = data;
-		conf->private_key_blob_len = data_len;
-	} else if (os_strcmp(type, "dh_blob") == 0) {
-		conf->dh_blob = data;
-		conf->dh_blob_len = data_len;
-	} else {
-		wpa_printf(MSG_ERROR, "input type error");
-		return -ENOTSUP;
-	}
-
-	return 0;
-}
-
-static int hapd_get_eap_config(struct wifi_connect_req_params *params,
-	struct wifi_eap_config *eap_cfg)
-{
-	unsigned int index = 0;
-
-	for (index = 0; index < ARRAY_SIZE(eap_config); index++) {
-		if (params->security == eap_config[index].type) {
-			memcpy(eap_cfg, &eap_config[index], sizeof(struct wifi_eap_config));
-			break;
-		}
-	}
-
-	if (index == ARRAY_SIZE(eap_config)) {
-		wpa_printf(MSG_ERROR, "Get eap method type with security type: %d",
-		params->security);
-		return -ENOTSUP;
-	}
-
-	return 0;
-}
-
-static struct hostapd_eap_user *hostapd_process_eap_user_phase1(
-	struct wifi_connect_req_params *params, struct hostapd_eap_user **pnew_user)
-{
-	struct hostapd_eap_user *user = NULL, *tail = NULL, *new_user = NULL;
-	struct wifi_eap_config eap_cfg;
-
-	user = os_zalloc(sizeof(*user));
-	if (user == NULL) {
-		wpa_printf(MSG_ERROR, "EAP user allocation failed");
-		goto failed;
-	}
-
-	user->force_version = -1;
-	if (params->eap_ver >= 0) {
-		user->force_version = params->eap_ver;
-	}
-
-	if (hapd_get_eap_config(params, &eap_cfg)) {
-		goto failed;
-	}
-
-	user->methods[0].method = eap_cfg.eap_type_phase1;
-	user->methods[0].vendor = 0;
-
-	if (tail == NULL) {
-		tail = new_user = user;
-	} else {
-		tail->next = user;
-		tail       = user;
-	}
-
-	*pnew_user = new_user;
-
-	return tail;
-
-failed:
-	if (user) {
-		hostapd_config_free_eap_user(user);
-	}
-
-	return NULL;
-}
-
-static int hostapd_process_eap_user(struct wifi_connect_req_params *params,
-	struct hostapd_bss_config *conf)
-{
-	struct hostapd_eap_user *user = NULL, *tail = NULL, *user_list = NULL;
-	int i, nusers = params->nusers;
-	const char *identity, *password;
-	struct wifi_eap_config eap_cfg;
-	int ret = 0;
-
-	if (hapd_get_eap_config(params, &eap_cfg)) {
-		goto failed;
-	}
-
-	if (eap_cfg.phase2 != NULL) {
-		tail = hostapd_process_eap_user_phase1(params, &user_list);
-	}
-
-	if (eap_cfg.phase2 != NULL && !nusers) {
-		wpa_printf(MSG_ERROR, "EAP users not found.");
-		goto failed;
-	}
-
-	for (i = 0; i < nusers; i++) {
-		user = os_zalloc(sizeof(*user));
-		if (user == NULL) {
-			wpa_printf(MSG_ERROR, "EAP user allocation failed");
-			goto failed;
-		}
-
-		user->force_version = -1;
-		if (params->eap_ver >= 0) {
-			user->force_version = params->eap_ver;
-		}
-
-		identity = params->identities[i];
-		password = params->passwords[i];
-
-		user->identity = os_memdup(identity, os_strlen(identity));
-		if (user->identity == NULL) {
-			wpa_printf(MSG_ERROR,
-				"Failed to allocate "
-				"memory for EAP identity");
-			goto failed;
-		}
-		user->identity_len = os_strlen(identity);
-
-		user->methods[0].method = eap_cfg.eap_type_phase1;
-		user->methods[0].vendor = 0;
-
-		if (eap_cfg.phase2 != NULL) {
-			user->methods[0].method = eap_cfg.eap_type_phase2;
-			user->password = os_memdup(password, os_strlen(password));
-			if (user->password == NULL) {
-				wpa_printf(MSG_ERROR,
-					"Failed to allocate "
-					"memory for EAP password");
-				goto failed;
-			}
-			user->password_len = os_strlen(password);
-
-			user->phase2 = 1;
-		}
-
-		if (params->security == WIFI_SECURITY_TYPE_EAP_TTLS_MSCHAPV2) {
-			user->ttls_auth |= 0x1E;
-		}
-
-		if (tail == NULL) {
-			tail = user_list = user;
-		} else {
-			tail->next = user;
-			tail       = user;
-		}
-
-		continue;
-
-failed:
-		if (user) {
-			hostapd_config_free_eap_user(user);
-		}
-
-		ret = -1;
-		break;
-	}
-
-	if (ret == 0) {
-		hostapd_config_free_eap_users(conf->eap_user);
-		conf->eap_user = user_list;
-	} else {
-		hostapd_config_free_eap_users(user_list);
-	}
-
-	return ret;
-}
-
-int hapd_process_enterprise_config(struct hostapd_iface *iface,
-	struct wifi_connect_req_params *params)
-{
-	struct wifi_eap_cipher_config cipher_config = {
-		NULL, "DEFAULT:!EXP:!LOW", "CCMP", "CCMP", "AES-128-CMAC", NULL};
-	int ret = 0;
-
-	if (process_cipher_config(params, &cipher_config)) {
-		goto out;
-	}
-
-	if (!hostapd_cli_cmd_v("set wpa %d", WPA_PROTO_RSN)) {
-		goto out;
-	}
-
-	if (!hostapd_cli_cmd_v("set wpa_key_mgmt %s", cipher_config.key_mgmt)) {
-		goto out;
-	}
-
-	if (!hostapd_cli_cmd_v("set rsn_pairwise %s", cipher_config.pairwise_cipher)) {
-		goto out;
-	}
-
-	if (!hostapd_cli_cmd_v("set wpa_pairwise %s", cipher_config.pairwise_cipher)) {
-		goto out;
-	}
-
-	if (!hostapd_cli_cmd_v("set group_cipher %s", cipher_config.group_cipher)) {
-		goto out;
-	}
-
-	if (!hostapd_cli_cmd_v("set group_mgmt_cipher %s", cipher_config.group_mgmt_cipher)) {
-		goto out;
-	}
-
-	if (cipher_config.tls_flags != NULL) {
-		if (!hostapd_cli_cmd_v("set tls_flags %s", cipher_config.tls_flags)) {
-			goto out;
-		}
-	}
-
-	if (!hostapd_cli_cmd_v("set ieee8021x %d", 1)) {
-		goto out;
-	}
-
-	if (!hostapd_cli_cmd_v("set eapol_version %d", 2)) {
-		goto out;
-	}
-
-	if (!hostapd_cli_cmd_v("set eap_server %d", 1)) {
-		goto out;
-	}
-
-	if (hapd_process_cert_data(iface->bss[0]->conf, "ca_cert_blob",
-		enterprise_creds.ca_cert, enterprise_creds.ca_cert_len)) {
-		goto out;
-	}
-
-	if (hapd_process_cert_data(iface->bss[0]->conf, "server_cert_blob",
-		enterprise_creds.server_cert, enterprise_creds.server_cert_len)) {
-		goto out;
-	}
-
-	if (hapd_process_cert_data(iface->bss[0]->conf, "private_key_blob",
-		enterprise_creds.server_key, enterprise_creds.server_key_len)) {
-		goto out;
-	}
-
-	if (hapd_process_cert_data(iface->bss[0]->conf, "dh_blob",
-		enterprise_creds.dh_param, enterprise_creds.dh_param_len)) {
-		goto out;
-	}
-
-	if (!hostapd_cli_cmd_v("set private_key_passwd %s", params->key_passwd)) {
-		goto out;
-	}
-
-	if (hostapd_process_eap_user(params, iface->bss[0]->conf)) {
-		goto out;
-	}
-
-	return ret;
-out:
-	return -1;
-}
-#endif
-
 #ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE
 static void wpas_remove_certs(struct wpa_supplicant *wpa_s)
 {
@@ -951,7 +707,8 @@ static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s,
 
 		if (params->security == WIFI_SECURITY_TYPE_SAE_HNP ||
 		    params->security == WIFI_SECURITY_TYPE_SAE_H2E ||
-		    params->security == WIFI_SECURITY_TYPE_SAE_AUTO) {
+		    params->security == WIFI_SECURITY_TYPE_SAE_AUTO ||
+		    params->security == WIFI_SECURITY_TYPE_SAE_EXT_KEY) {
 			if (params->sae_password) {
 				if ((params->sae_password_length < WIFI_PSK_MIN_LEN) ||
 				    (params->sae_password_length > WIFI_SAE_PSWD_MAX_LEN)) {
@@ -974,19 +731,26 @@ static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s,
 				}
 			}
 
-			if (params->security == WIFI_SECURITY_TYPE_SAE_H2E ||
-			    params->security == WIFI_SECURITY_TYPE_SAE_AUTO) {
-				if (!wpa_cli_cmd_v("set sae_pwe %d",
-						   (params->security == WIFI_SECURITY_TYPE_SAE_H2E)
-							   ? 1
-							   : 2)) {
-					goto out;
-				}
+			if (!wpa_cli_cmd_v("set sae_pwe %d",
+				(params->security == WIFI_SECURITY_TYPE_SAE_H2E)
+				   ? 1
+				   : ((params->security == WIFI_SECURITY_TYPE_SAE_HNP)
+					   ? 0
+					   : 2))) {
+				goto out;
 			}
 
-			if (!wpa_cli_cmd_v("set_network %d key_mgmt SAE%s", resp.network_id,
-					   params->ft_used ? " FT-SAE" : "")) {
-				goto out;
+			if (params->security != WIFI_SECURITY_TYPE_SAE_EXT_KEY) {
+				if (!wpa_cli_cmd_v("set_network %d key_mgmt SAE%s", resp.network_id,
+						   params->ft_used ? " FT-SAE" : "")) {
+					goto out;
+				}
+			} else {
+				if (!wpa_cli_cmd_v("set_network %d key_mgmt SAE-EXT-KEY%s",
+						   resp.network_id,
+						   params->ft_used ? " FT-SAE-EXT-KEY" : "")) {
+					goto out;
+				}
 			}
 		} else if (params->security == WIFI_SECURITY_TYPE_PSK_SHA256) {
 			if (!wpa_cli_cmd_v("set_network %d psk \"%s\"",
@@ -1062,7 +826,7 @@ static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s,
 				goto out;
 			}
 
-			if (params->suiteb_type == WIFI_SUITEB_192) {
+			if (params->wpa3_ent_mode == WIFI_WPA3_ENTERPRISE_SUITEB_192) {
 				if (params->TLS_cipher == WIFI_EAP_TLS_ECC_P384) {
 					if (!wpa_cli_cmd_v("set_network %d openssl_ciphers \"%s\"",
 							resp.network_id,
@@ -1152,15 +916,19 @@ static int wpas_add_and_config_network(struct wpa_supplicant *wpa_s,
 				goto out;
 			}
 
-			if (wpas_config_process_blob(wpa_s->conf, "ca_cert",
-					   enterprise_creds.ca_cert,
-					   enterprise_creds.ca_cert_len)) {
-				goto out;
-			}
+			if (false == ((params->security == WIFI_SECURITY_TYPE_EAP_PEAP_MSCHAPV2 ||
+			    params->security == WIFI_SECURITY_TYPE_EAP_TTLS_MSCHAPV2) &&
+			    (!params->verify_peer_cert))) {
+				if (wpas_config_process_blob(wpa_s->conf, "ca_cert",
+						   enterprise_creds.ca_cert,
+						   enterprise_creds.ca_cert_len)) {
+					goto out;
+				}
 
-			if (!wpa_cli_cmd_v("set_network %d ca_cert \"blob://ca_cert\"",
-					   resp.network_id)) {
-				goto out;
+				if (!wpa_cli_cmd_v("set_network %d ca_cert \"blob://ca_cert\"",
+						   resp.network_id)) {
+					goto out;
+				}
 			}
 
 			if (wpas_config_process_blob(wpa_s->conf, "client_cert",
@@ -1444,7 +1212,7 @@ int supplicant_disconnect(const struct device *dev)
 	return wpas_disconnect_network(dev, WPAS_MODE_INFRA);
 }
 
-static enum wifi_mfp_options get_mfp(enum mfp_options supp_mfp_option)
+enum wifi_mfp_options get_mfp(enum mfp_options supp_mfp_option)
 {
 	switch (supp_mfp_option) {
 	case NO_MGMT_FRAME_PROTECTION:
@@ -1534,7 +1302,8 @@ int supplicant_status(const struct device *dev, struct wifi_iface_status *status
 		sae_pwe = wpa_s->conf->sae_pwe;
 		os_memcpy(status->bssid, wpa_s->bssid, WIFI_MAC_ADDR_LEN);
 		status->band = wpas_band_to_zephyr(wpas_freq_to_band(wpa_s->assoc_freq));
-		status->security = wpas_key_mgmt_to_zephyr(key_mgmt, proto, sae_pwe);
+		status->wpa3_ent_type = wpas_key_mgmt_to_zephyr_wpa3_ent(key_mgmt);
+		status->security = wpas_key_mgmt_to_zephyr(0, ssid, key_mgmt, proto, sae_pwe);
 		status->mfp = get_mfp(ssid->ieee80211w);
 		ieee80211_freq_to_chan(wpa_s->assoc_freq, &channel);
 		status->channel = channel;
@@ -1621,7 +1390,7 @@ int supplicant_status(const struct device *dev, struct wifi_iface_status *status
  * supplicant.
  */
 
-static const struct wifi_mgmt_ops *const get_wifi_mgmt_api(const struct device *dev)
+const struct wifi_mgmt_ops *const get_wifi_mgmt_api(const struct device *dev)
 {
 	struct net_wifi_mgmt_offload *api = (struct net_wifi_mgmt_offload *)dev->api;
 
@@ -1889,11 +1658,11 @@ int supplicant_reg_domain(const struct device *dev,
 			goto out;
 		}
 
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-		if (!hostapd_cli_cmd_v("set country_code %s", reg_domain->country_code)) {
-			goto out;
+		if (IS_ENABLED(CONFIG_WIFI_NM_HOSTAPD_AP)) {
+			if (!hostapd_ap_reg_domain(reg_domain)) {
+				goto out;
+			}
 		}
-#endif
 
 		ret = 0;
 
@@ -2134,546 +1903,25 @@ int supplicant_wps_config(const struct device *dev, struct wifi_wps_config_param
 }
 
 #ifdef CONFIG_AP
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-int hapd_state(const struct device *dev, int *state)
+int set_ap_bandwidth(const struct device *dev, enum wifi_frequency_bandwidths bandwidth)
 {
-	struct hostapd_iface *iface;
-	int ret = 0;
-
-	k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER);
+	const struct wifi_mgmt_ops *const wifi_mgmt_api = get_wifi_mgmt_api(dev);
+	struct wifi_ap_config_params params = {0};
 
-	iface = get_hostapd_handle(dev);
-	if (!iface) {
-		wpa_printf(MSG_ERROR, "Device %s not found", dev->name);
-		ret = -ENOENT;
-		goto out;
+	if (wifi_mgmt_api == NULL || wifi_mgmt_api->ap_config_params == NULL) {
+		return -ENOTSUP;
 	}
 
-	*state = iface->state;
-
-out:
-	k_mutex_unlock(&wpa_supplicant_mutex);
-	return ret;
+	params.bandwidth = bandwidth;
+	params.type = WIFI_AP_CONFIG_PARAM_BANDWIDTH;
+	return wifi_mgmt_api->ap_config_params(dev, &params);
 }
 
-static int hapd_config_chan_center_seg0(struct wifi_connect_req_params *params)
+int supplicant_ap_enable(const struct device *dev,
+			 struct wifi_connect_req_params *params)
 {
-	int ret = 0;
-	uint8_t center_freq_seg0_idx = 0;
-	uint8_t oper_chwidth = CHANWIDTH_USE_HT;
-	const uint8_t *center_freq = NULL;
-	static const uint8_t center_freq_40MHz[] = {38,  46,  54,  62,  102, 110,
-						    118, 126, 134, 142, 151, 159};
-	static const uint8_t center_freq_80MHz[] = {42, 58, 106, 122, 138, 155};
-	uint8_t index, index_max, chan_idx, ch_offset = 0;
-
-	/* Unless ACS is being used, both "channel" and "vht_oper_centr_freq_seg0_idx"
-	 * parameters must be set.
-	 */
-	switch (params->bandwidth) {
-	case WIFI_FREQ_BANDWIDTH_20MHZ:
-		oper_chwidth = CHANWIDTH_USE_HT;
-		center_freq_seg0_idx = params->channel;
-		break;
-	case WIFI_FREQ_BANDWIDTH_40MHZ:
-		oper_chwidth = CHANWIDTH_USE_HT;
-		center_freq = center_freq_40MHz;
-		index_max = ARRAY_SIZE(center_freq_40MHz);
-		ch_offset = 2;
-		break;
-	case WIFI_FREQ_BANDWIDTH_80MHZ:
-		oper_chwidth = CHANWIDTH_80MHZ;
-		center_freq = center_freq_80MHz;
-		index_max = ARRAY_SIZE(center_freq_80MHz);
-		ch_offset = 6;
-		break;
-	default:
-		return -EINVAL;
-	}
-
-	if (params->bandwidth != WIFI_FREQ_BANDWIDTH_20MHZ) {
-		chan_idx = params->channel;
-		for (index = 0; index < index_max; index++) {
-			if ((chan_idx >= (center_freq[index] - ch_offset)) &&
-			    (chan_idx <= (center_freq[index] + ch_offset))) {
-				center_freq_seg0_idx = center_freq[index];
-				break;
-			}
-		}
-	}
-
-	if (!hostapd_cli_cmd_v("set vht_oper_chwidth %d", oper_chwidth)) {
-		goto out;
-	}
-	if (!hostapd_cli_cmd_v("set vht_oper_centr_freq_seg0_idx %d", center_freq_seg0_idx)) {
-		goto out;
-	}
-#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_11AX
-	if (!hostapd_cli_cmd_v("set he_oper_chwidth %d", oper_chwidth)) {
-		goto out;
-	}
-	if (!hostapd_cli_cmd_v("set he_oper_centr_freq_seg0_idx %d", center_freq_seg0_idx)) {
-		goto out;
-	}
-#endif
-
-	return ret;
-out:
-	return -EINVAL;
-}
-
-int hapd_config_network(struct hostapd_iface *iface,
-			struct wifi_connect_req_params *params)
-{
-	int ret = 0;
-
-	if (!hostapd_cli_cmd_v("set ssid %s", params->ssid)) {
-		goto out;
-	}
-
-	if (params->channel == 0) {
-		if (params->band == 0) {
-			if (!hostapd_cli_cmd_v("set hw_mode g")) {
-				goto out;
-			}
-		} else if (params->band == 1) {
-			if (!hostapd_cli_cmd_v("set hw_mode a")) {
-				goto out;
-			}
-		} else {
-			wpa_printf(MSG_ERROR, "Invalid band %d", params->band);
-			goto out;
-		}
-	} else if (params->channel > 14) {
-		if (!hostapd_cli_cmd_v("set hw_mode a")) {
-			goto out;
-		}
-	} else {
-		if (!hostapd_cli_cmd_v("set hw_mode g")) {
-			goto out;
-		}
-	}
-
-	if (!hostapd_cli_cmd_v("set channel %d", params->channel)) {
-		goto out;
-	}
-
-	ret = hapd_config_chan_center_seg0(params);
-	if (ret) {
-		goto out;
-	}
-
-	if (params->security != WIFI_SECURITY_TYPE_NONE) {
-		if (params->security == WIFI_SECURITY_TYPE_WPA_PSK) {
-			if (!hostapd_cli_cmd_v("set wpa 1")) {
-				goto out;
-			}
-			if (!hostapd_cli_cmd_v("set wpa_key_mgmt WPA-PSK")) {
-				goto out;
-			}
-			if (!hostapd_cli_cmd_v("set wpa_passphrase %s", params->psk)) {
-				goto out;
-			}
-			if (!hostapd_cli_cmd_v("set wpa_pairwise CCMP")) {
-				goto out;
-			}
-		} else if (params->security == WIFI_SECURITY_TYPE_PSK) {
-			if (!hostapd_cli_cmd_v("set wpa 2")) {
-				goto out;
-			}
-			if (!hostapd_cli_cmd_v("set wpa_key_mgmt WPA-PSK")) {
-				goto out;
-			}
-			if (!hostapd_cli_cmd_v("set wpa_passphrase %s", params->psk)) {
-				goto out;
-			}
-			if (!hostapd_cli_cmd_v("set rsn_pairwise CCMP")) {
-				goto out;
-			}
-		} else if (params->security == WIFI_SECURITY_TYPE_PSK_SHA256) {
-			if (!hostapd_cli_cmd_v("set wpa 2")) {
-				goto out;
-			}
-			if (!hostapd_cli_cmd_v("set wpa_key_mgmt WPA-PSK-SHA256")) {
-				goto out;
-			}
-			if (!hostapd_cli_cmd_v("set wpa_passphrase %s", params->psk)) {
-				goto out;
-			}
-			if (!hostapd_cli_cmd_v("set rsn_pairwise CCMP")) {
-				goto out;
-			}
-		} else if (params->security == WIFI_SECURITY_TYPE_SAE_HNP ||
-			   params->security == WIFI_SECURITY_TYPE_SAE_H2E ||
-			   params->security == WIFI_SECURITY_TYPE_SAE_AUTO) {
-			if (!hostapd_cli_cmd_v("set wpa 2")) {
-				goto out;
-			}
-			if (!hostapd_cli_cmd_v("set wpa_key_mgmt SAE")) {
-				goto out;
-			}
-			if (!hostapd_cli_cmd_v("set sae_password %s",
-					       params->sae_password ? params->sae_password :
-					       params->psk)) {
-				goto out;
-			}
-			if (!hostapd_cli_cmd_v("set rsn_pairwise CCMP")) {
-				goto out;
-			}
-			if (params->security == WIFI_SECURITY_TYPE_SAE_H2E ||
-			    params->security == WIFI_SECURITY_TYPE_SAE_AUTO) {
-				if (!hostapd_cli_cmd_v("set sae_pwe %d",
-					(params->security == WIFI_SECURITY_TYPE_SAE_H2E)
-						? 1
-						: 2)) {
-					goto out;
-				}
-			}
-		} else if (params->security == WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL) {
-			if (!hostapd_cli_cmd_v("set wpa 2")) {
-				goto out;
-			}
-
-			if (!hostapd_cli_cmd_v("set wpa_key_mgmt WPA-PSK SAE")) {
-				goto out;
-			}
-
-			if (!hostapd_cli_cmd_v("set wpa_passphrase %s", params->psk)) {
-				goto out;
-			}
-
-			if (!hostapd_cli_cmd_v("set sae_password %s",
-					       params->sae_password ? params->sae_password
-								    : params->psk)) {
-				goto out;
-			}
-
-			if (!hostapd_cli_cmd_v("set rsn_pairwise CCMP")) {
-				goto out;
-			}
-
-			if (!hostapd_cli_cmd_v("set sae_pwe 2")) {
-				goto out;
-			}
-		} else if (params->security == WIFI_SECURITY_TYPE_DPP) {
-			if (!hostapd_cli_cmd_v("set wpa 2")) {
-				goto out;
-			}
-			if (!hostapd_cli_cmd_v("set wpa_key_mgmt WPA-PSK DPP")) {
-				goto out;
-			}
-			if (!hostapd_cli_cmd_v("set wpa_passphrase %s", params->psk)) {
-				goto out;
-			}
-			if (!hostapd_cli_cmd_v("set wpa_pairwise CCMP")) {
-				goto out;
-			}
-			if (!hostapd_cli_cmd_v("set rsn_pairwise CCMP")) {
-				goto out;
-			}
-			if (!hostapd_cli_cmd_v("set dpp_configurator_connectivity 1")) {
-				goto out;
-			}
-#ifdef CONFIG_WIFI_NM_HOSTAPD_CRYPTO_ENTERPRISE
-		} else if (is_eap_valid_security(params->security)) {
-			if (hapd_process_enterprise_config(iface, params)) {
-				goto out;
-			}
-#endif
-		}
-	} else {
-		if (!hostapd_cli_cmd_v("set wpa 0")) {
-			goto out;
-		}
-		iface->bss[0]->conf->wpa_key_mgmt = WPA_KEY_MGMT_NONE;
-	}
-
-	if (!hostapd_cli_cmd_v("set ieee80211w %d", params->mfp)) {
-		goto out;
-	}
-
-	if (!hostapd_cli_cmd_v("set ignore_broadcast_ssid %d", params->ignore_broadcast_ssid)) {
-		goto out;
-	}
-
-	return ret;
-out:
-	return -1;
-}
-
-static int set_ap_config_params(const struct device *dev, struct wifi_ap_config_params *params)
-{
-	const struct wifi_mgmt_ops *const wifi_mgmt_api = get_wifi_mgmt_api(dev);
-
-	if (wifi_mgmt_api == NULL || wifi_mgmt_api->ap_config_params == NULL) {
-		return -ENOTSUP;
-	}
-
-	return wifi_mgmt_api->ap_config_params(dev, params);
-}
-
-int supplicant_ap_config_params(const struct device *dev, struct wifi_ap_config_params *params)
-{
-	struct hostapd_iface *iface;
-	int ret = 0;
-
-	ret = set_ap_config_params(dev, params);
-	if (ret && (ret != -ENOTSUP)) {
-		wpa_printf(MSG_ERROR, "Failed to set ap config params");
-		return -EINVAL;
-	}
-
-	k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER);
-
-	iface = get_hostapd_handle(dev);
-	if (iface == NULL) {
-		ret = -ENOENT;
-		wpa_printf(MSG_ERROR, "Interface %s not found", dev->name);
-		goto out;
-	}
-
-	if (iface->state > HAPD_IFACE_DISABLED) {
-		ret = -EBUSY;
-		wpa_printf(MSG_ERROR, "Interface %s is not in disable state", dev->name);
-		goto out;
-	}
-
-	if (params->type & WIFI_AP_CONFIG_PARAM_MAX_NUM_STA) {
-		if (!hostapd_cli_cmd_v("set max_num_sta %d", params->max_num_sta)) {
-			ret = -EINVAL;
-			wpa_printf(MSG_ERROR, "Failed to set maximum number of stations");
-			goto out;
-		}
-		wpa_printf(MSG_INFO, "Set maximum number of stations: %d", params->max_num_sta);
-	}
-
-	if (params->type & WIFI_AP_CONFIG_PARAM_HT_CAPAB) {
-		if (!hostapd_cli_cmd_v("set ht_capab %s", params->ht_capab)) {
-			ret = -EINVAL;
-			wpa_printf(MSG_ERROR, "Failed to set HT capabilities");
-			goto out;
-		}
-		wpa_printf(MSG_INFO, "Set HT capabilities: %s", params->ht_capab);
-	}
-
-	if (params->type & WIFI_AP_CONFIG_PARAM_VHT_CAPAB) {
-		if (!hostapd_cli_cmd_v("set vht_capab %s", params->vht_capab)) {
-			ret = -EINVAL;
-			wpa_printf(MSG_ERROR, "Failed to set VHT capabilities");
-			goto out;
-		}
-		wpa_printf(MSG_INFO, "Set VHT capabilities: %s", params->vht_capab);
-	}
-
-out:
-		k_mutex_unlock(&wpa_supplicant_mutex);
-
-	return ret;
-}
-
-int supplicant_ap_status(const struct device *dev, struct wifi_iface_status *status)
-{
-	int ret = 0;
-	struct hostapd_iface *iface;
-	struct hostapd_config *conf;
-	struct hostapd_data *hapd;
-	struct hostapd_bss_config *bss;
-	struct hostapd_ssid *ssid;
-	struct hostapd_hw_modes *hw_mode;
-	int proto;    /* Wi-Fi secure protocol */
-	int key_mgmt; /*  Wi-Fi key management */
-	int sae_pwe;
-
-	k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER);
-
-	iface = get_hostapd_handle(dev);
-	if (!iface) {
-		ret = -1;
-		wpa_printf(MSG_ERROR, "Interface %s not found", dev->name);
-		goto out;
-	}
-
-	conf = iface->conf;
-	if (!conf) {
-		ret = -1;
-		wpa_printf(MSG_ERROR, "Conf %s not found", dev->name);
-		goto out;
-	}
-
-	bss = conf->bss[0];
-	if (!bss) {
-		ret = -1;
-		wpa_printf(MSG_ERROR, "Bss_conf %s not found", dev->name);
-		goto out;
-	}
-
-	hapd = iface->bss[0];
-	if (!hapd) {
-		ret = -1;
-		wpa_printf(MSG_ERROR, "Bss %s not found", dev->name);
-		goto out;
-	}
-
-	status->state = iface->state;
-	ssid = &bss->ssid;
-
-	os_memcpy(status->bssid, hapd->own_addr, WIFI_MAC_ADDR_LEN);
-	status->iface_mode = WIFI_MODE_AP;
-	status->band = wpas_band_to_zephyr(wpas_freq_to_band(iface->freq));
-	key_mgmt = bss->wpa_key_mgmt;
-	proto = bss->wpa;
-	sae_pwe = bss->sae_pwe;
-	status->security = wpas_key_mgmt_to_zephyr(key_mgmt, proto, sae_pwe);
-	status->mfp = get_mfp(bss->ieee80211w);
-	status->channel = conf->channel;
-	os_memcpy(status->ssid, ssid->ssid, ssid->ssid_len);
-
-	status->dtim_period = bss->dtim_period;
-	status->beacon_interval = conf->beacon_int;
-
-	hw_mode = iface->current_mode;
-
-	status->link_mode = conf->ieee80211ax                          ? WIFI_6
-			    : conf->ieee80211ac                        ? WIFI_5
-			    : conf->ieee80211n                         ? WIFI_4
-			    : hw_mode->mode == HOSTAPD_MODE_IEEE80211G ? WIFI_3
-			    : hw_mode->mode == HOSTAPD_MODE_IEEE80211A ? WIFI_2
-			    : hw_mode->mode == HOSTAPD_MODE_IEEE80211B ? WIFI_1
-								       : WIFI_0;
-	status->twt_capable = (hw_mode->he_capab[IEEE80211_MODE_AP].mac_cap[0] & 0x04);
-
-out:
-	k_mutex_unlock(&wpa_supplicant_mutex);
-	return ret;
-}
-#endif /* CONFIG_WIFI_NM_HOSTAPD_AP */
-
-#ifdef CONFIG_WIFI_NM_HOSTAPD_WPS
-int supplicant_ap_wps_pbc(const struct device *dev)
-{
-	struct hostapd_iface *iface;
-	int ret = -1;
-
-	k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER);
-
-	iface = get_hostapd_handle(dev);
-	if (!iface) {
-		ret = -1;
-		wpa_printf(MSG_ERROR, "Interface %s not found", dev->name);
-		goto out;
-	}
-
-	if (iface->state != HAPD_IFACE_ENABLED) {
-		ret = -EBUSY;
-		wpa_printf(MSG_ERROR, "Interface %s is not in enable state", dev->name);
-		goto out;
-	}
-
-	if (!hostapd_cli_cmd_v("wps_pbc")) {
-		goto out;
-	}
-
-	wpas_api_ctrl.dev = dev;
-	wpas_api_ctrl.requested_op = WPS_PBC;
-
-	ret = 0;
-
-out:
-	k_mutex_unlock(&wpa_supplicant_mutex);
-
-	return ret;
-}
-
-int supplicant_ap_wps_pin(const struct device *dev, struct wifi_wps_config_params *params)
-{
-#define WPS_PIN_EXPIRE_TIME 120
-	struct hostapd_iface *iface;
-	char *get_pin_cmd = "WPS_AP_PIN random";
-	int ret  = 0;
-
-	k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER);
-
-	iface = get_hostapd_handle(dev);
-	if (!iface) {
-		ret = -1;
-		wpa_printf(MSG_ERROR, "Interface %s not found", dev->name);
-		goto out;
-	}
-
-	if (iface->state != HAPD_IFACE_ENABLED) {
-		ret = -EBUSY;
-		wpa_printf(MSG_ERROR, "Interface %s is not in enable state", dev->name);
-		goto out;
-	}
-
-	if (params->oper == WIFI_WPS_PIN_GET) {
-		if (zephyr_hostapd_cli_cmd_resp(get_pin_cmd, params->pin)) {
-			goto out;
-		}
-	} else if (params->oper == WIFI_WPS_PIN_SET) {
-		if (!hostapd_cli_cmd_v("wps_check_pin %s", params->pin)) {
-			goto out;
-		}
-
-		if (!hostapd_cli_cmd_v("wps_pin any %s %d", params->pin, WPS_PIN_EXPIRE_TIME)) {
-			goto out;
-		}
-
-		wpas_api_ctrl.dev = dev;
-		wpas_api_ctrl.requested_op = WPS_PIN;
-	} else {
-		wpa_printf(MSG_ERROR, "Error wps pin operation : %d", params->oper);
-		goto out;
-	}
-
-	ret = 0;
-
-out:
-	k_mutex_unlock(&wpa_supplicant_mutex);
-
-	return ret;
-}
-
-
-int supplicant_ap_wps_config(const struct device *dev, struct wifi_wps_config_params *params)
-{
-	int ret = 0;
-
-	if (params->oper == WIFI_WPS_PBC) {
-		ret = supplicant_ap_wps_pbc(dev);
-	} else if (params->oper == WIFI_WPS_PIN_GET || params->oper == WIFI_WPS_PIN_SET) {
-		ret = supplicant_ap_wps_pin(dev, params);
-	}
-
-	return ret;
-}
-#endif
-
-static int set_ap_bandwidth(const struct device *dev, enum wifi_frequency_bandwidths bandwidth)
-{
-	const struct wifi_mgmt_ops *const wifi_mgmt_api = get_wifi_mgmt_api(dev);
-	struct wifi_ap_config_params params = {0};
-
-	if (wifi_mgmt_api == NULL || wifi_mgmt_api->ap_config_params == NULL) {
-		return -ENOTSUP;
-	}
-
-	params.bandwidth = bandwidth;
-	params.type = WIFI_AP_CONFIG_PARAM_BANDWIDTH;
-	return wifi_mgmt_api->ap_config_params(dev, &params);
-}
-
-int supplicant_ap_enable(const struct device *dev,
-			 struct wifi_connect_req_params *params)
-{
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-	struct hostapd_iface *iface;
-	struct hostapd_data *hapd;
-	struct wpa_driver_capa capa;
-#else
-	struct wpa_supplicant *wpa_s;
-#endif
-	int ret;
+	struct wpa_supplicant *wpa_s;
+	int ret;
 
 	if (!net_if_is_admin_up(net_if_lookup_by_dev(dev))) {
 		wpa_printf(MSG_ERROR,
@@ -2690,53 +1938,6 @@ int supplicant_ap_enable(const struct device *dev,
 
 	k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER);
 
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-	iface = get_hostapd_handle(dev);
-	if (!iface) {
-		ret = -1;
-		wpa_printf(MSG_ERROR, "Interface %s not found", dev->name);
-		goto out;
-	}
-
-	iface->owner = iface;
-
-	if (iface->state == HAPD_IFACE_ENABLED) {
-		ret = -EBUSY;
-		wpa_printf(MSG_ERROR, "Interface %s is not in disable state", dev->name);
-		goto out;
-	}
-
-	ret = hapd_config_network(iface, params);
-	if (ret) {
-		wpa_printf(MSG_ERROR, "Failed to configure network for AP: %d", ret);
-		goto out;
-	}
-
-	hapd = iface->bss[0];
-	if (!iface->extended_capa || !iface->extended_capa_mask) {
-		if (hapd->driver->get_capa && hapd->driver->get_capa(hapd->drv_priv, &capa) == 0) {
-			iface->extended_capa         = capa.extended_capa;
-			iface->extended_capa_mask    = capa.extended_capa_mask;
-			iface->extended_capa_len     = capa.extended_capa_len;
-			iface->drv_max_acl_mac_addrs = capa.max_acl_mac_addrs;
-
-			/*
-			 * Override extended capa with per-interface type (AP), if
-			 * available from the driver.
-			 */
-			hostapd_get_ext_capa(iface);
-		} else {
-			ret = -1;
-			wpa_printf(MSG_ERROR, "Failed to get capability for AP: %d", ret);
-			goto out;
-		}
-	}
-
-	if (!hostapd_cli_cmd_v("enable")) {
-		goto out;
-	}
-
-#else
 	wpa_s = get_wpa_s_handle(dev);
 	if (!wpa_s) {
 		ret = -1;
@@ -2760,7 +1961,6 @@ int supplicant_ap_enable(const struct device *dev,
 		wpa_printf(MSG_ERROR, "Failed to add and configure network for AP mode: %d", ret);
 		goto out;
 	}
-#endif
 
 out:
 	k_mutex_unlock(&wpa_supplicant_mutex);
@@ -2770,36 +1970,11 @@ int supplicant_ap_enable(const struct device *dev,
 
 int supplicant_ap_disable(const struct device *dev)
 {
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-	struct hostapd_iface *iface;
-	int ret = 0;
-#else
 	struct wpa_supplicant *wpa_s;
 	int ret = -1;
-#endif
 
 	k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER);
 
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-	iface = get_hostapd_handle(dev);
-	if (!iface) {
-		ret = -ENOENT;
-		wpa_printf(MSG_ERROR, "Interface %s not found", dev->name);
-		goto out;
-	}
-
-	if (iface->state != HAPD_IFACE_ENABLED) {
-		ret = -EBUSY;
-		wpa_printf(MSG_ERROR, "Interface %s is not in enable state", dev->name);
-		goto out;
-	}
-
-	if (!hostapd_cli_cmd_v("disable")) {
-		goto out;
-	}
-
-	iface->freq = 0;
-#else
 	wpa_s = get_wpa_s_handle(dev);
 	if (!wpa_s) {
 		ret = -1;
@@ -2815,7 +1990,6 @@ int supplicant_ap_disable(const struct device *dev)
 
 	/* Restore ap_scan to default value */
 	wpa_s->conf->ap_scan = 1;
-#endif
 
 out:
 	k_mutex_unlock(&wpa_supplicant_mutex);
@@ -2825,43 +1999,11 @@ int supplicant_ap_disable(const struct device *dev)
 int supplicant_ap_sta_disconnect(const struct device *dev,
 				 const uint8_t *mac_addr)
 {
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-	struct hostapd_iface *iface;
-	int ret  = 0;
-#else
 	struct wpa_supplicant *wpa_s;
 	int ret = -1;
-#endif
 
 	k_mutex_lock(&wpa_supplicant_mutex, K_FOREVER);
 
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-	iface = get_hostapd_handle(dev);
-	if (!iface) {
-		ret = -1;
-		wpa_printf(MSG_ERROR, "Interface %s not found", dev->name);
-		goto out;
-	}
-
-	if (iface->state != HAPD_IFACE_ENABLED) {
-		ret = -EBUSY;
-		wpa_printf(MSG_ERROR, "Interface %s is not in enable state", dev->name);
-		goto out;
-	}
-
-	if (!mac_addr) {
-		ret = -EINVAL;
-		wpa_printf(MSG_ERROR, "Invalid MAC address");
-		goto out;
-	}
-
-	if (!hostapd_cli_cmd_v("deauthenticate %02x:%02x:%02x:%02x:%02x:%02x",
-				mac_addr[0], mac_addr[1], mac_addr[2],
-				mac_addr[3], mac_addr[4], mac_addr[5])) {
-		goto out;
-	}
-
-#else
 	wpa_s = get_wpa_s_handle(dev);
 	if (!wpa_s) {
 		ret = -1;
@@ -2882,7 +2024,6 @@ int supplicant_ap_sta_disconnect(const struct device *dev,
 	}
 
 	ret = 0;
-#endif
 
 out:
 	k_mutex_unlock(&wpa_supplicant_mutex);
@@ -2958,10 +2099,9 @@ static void dpp_ssid_bin2str(char *dst, uint8_t *src, int max_len)
 	}
 }
 
-#define SUPPLICANT_DPP_CMD_BUF_SIZE 384
 #define STR_CUR_TO_END(cur) (cur) = (&(cur)[0] + strlen((cur)))
 
-static int dpp_params_to_cmd(struct wifi_dpp_params *params, char *cmd, size_t max_len)
+int dpp_params_to_cmd(struct wifi_dpp_params *params, char *cmd, size_t max_len)
 {
 	char *pos = cmd;
 	char *end = cmd + max_len;
@@ -3181,37 +2321,4 @@ int supplicant_dpp_dispatch(const struct device *dev, struct wifi_dpp_params *pa
 	os_free(cmd);
 	return 0;
 }
-
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-int hapd_dpp_dispatch(const struct device *dev, struct wifi_dpp_params *params)
-{
-	int ret;
-	char *cmd = NULL;
-
-	if (params == NULL) {
-		return -EINVAL;
-	}
-
-	cmd = os_zalloc(SUPPLICANT_DPP_CMD_BUF_SIZE);
-	if (cmd == NULL) {
-		return -ENOMEM;
-	}
-
-	/* leave one byte always be 0 */
-	ret = dpp_params_to_cmd(params, cmd, SUPPLICANT_DPP_CMD_BUF_SIZE - 2);
-	if (ret) {
-		os_free(cmd);
-		return ret;
-	}
-
-	wpa_printf(MSG_DEBUG, "hostapd_cli %s", cmd);
-	if (zephyr_hostapd_cli_cmd_resp(cmd, params->resp)) {
-		os_free(cmd);
-		return -ENOEXEC;
-	}
-
-	os_free(cmd);
-	return 0;
-}
-#endif /* CONFIG_WIFI_NM_HOSTAPD_AP */
 #endif /* CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP */
diff --git a/modules/hostap/src/supp_api.h b/modules/hostap/src/supp_api.h
index cb4e7836f1c..ddd3c3d6698 100644
--- a/modules/hostap/src/supp_api.h
+++ b/modules/hostap/src/supp_api.h
@@ -8,6 +8,7 @@
 #ifndef ZEPHYR_SUPP_MGMT_H
 #define ZEPHYR_SUPP_MGMT_H
 
+#include <defs.h>
 #include <zephyr/net/wifi_mgmt.h>
 
 #ifndef MAX_SSID_LEN
@@ -20,6 +21,17 @@
 #define MAC_STR_LEN 18 /* for ':' or '-' separated MAC address string */
 #define CHAN_NUM_LEN 6 /* for space-separated channel numbers string */
 
+enum wifi_frequency_bands wpas_band_to_zephyr(enum wpa_radio_work_band band);
+
+enum wifi_wpa3_enterprise_type wpas_key_mgmt_to_zephyr_wpa3_ent(int key_mgmt);
+
+enum wifi_security_type wpas_key_mgmt_to_zephyr(bool is_hapd, void *config,
+						int key_mgmt, int proto, int pwe);
+
+const struct wifi_mgmt_ops *const get_wifi_mgmt_api(const struct device *dev);
+
+enum wifi_mfp_options get_mfp(enum mfp_options supp_mfp_option);
+
 /**
  * @brief Get version
  *
@@ -194,6 +206,11 @@ int supplicant_mode(const struct device *dev, struct wifi_mode_info *mode);
 
 #if defined CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE || \
 	defined CONFIG_WIFI_NM_HOSTAPD_CRYPTO_ENTERPRISE
+int is_eap_valid_security(int security);
+
+int process_cipher_config(struct wifi_connect_req_params *params,
+			  struct wifi_eap_cipher_config *cipher_config);
+
 /** Set Wi-Fi enterprise mode CA/client Cert and key
  *
  * @param dev Pointer to the device structure for the driver instance
@@ -289,50 +306,7 @@ int supplicant_get_wifi_conn_params(const struct device *dev,
 int supplicant_wps_config(const struct device *dev, struct wifi_wps_config_params *params);
 
 #ifdef CONFIG_AP
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-/**
- * @brief Get Wi-Fi AP Status
- *
- * @param dev Wi-Fi device
- * @param params AP status
- * @return 0 for OK; -1 for ERROR
- */
-int hapd_state(const struct device *dev, int *state);
-
-/**
- * @brief Wi-Fi AP configuration parameter.
- *
- * @param dev Wi-Fi device
- * @param params AP parameters
- * @return 0 for OK; -1 for ERROR
- */
-int supplicant_ap_config_params(const struct device *dev, struct wifi_ap_config_params *params);
-#else
-static inline int hapd_state(const struct device *dev, int *state)
-{
-	return -EINVAL;
-}
-#endif
-
-#ifdef CONFIG_WIFI_NM_HOSTAPD_WPS
-/** Start AP WPS PBC/PIN
- *
- * @param dev Pointer to the device structure for the driver instance
- * @param params wps operarion parameters
- *
- * @return 0 if ok, < 0 if error
- */
-int supplicant_ap_wps_config(const struct device *dev, struct wifi_wps_config_params *params);
-#endif
-
-/**
- * @brief Get Wi-Fi SAP status
- *
- * @param dev Wi-Fi device
- * @param status SAP status
- * @return 0 for OK; -1 for ERROR
- */
-int supplicant_ap_status(const struct device *dev, struct wifi_iface_status *status);
+int set_ap_bandwidth(const struct device *dev, enum wifi_frequency_bandwidths bandwidth);
 
 /**
  * @brief Set Wi-Fi AP configuration
@@ -363,6 +337,10 @@ int supplicant_ap_sta_disconnect(const struct device *dev,
 #endif /* CONFIG_AP */
 
 #ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP
+#define SUPPLICANT_DPP_CMD_BUF_SIZE 384
+
+int dpp_params_to_cmd(struct wifi_dpp_params *params, char *cmd, size_t max_len);
+
 /**
  * @brief Dispatch DPP operations for STA
  *
@@ -371,16 +349,5 @@ int supplicant_ap_sta_disconnect(const struct device *dev,
  * @return 0 for OK; -1 for ERROR
  */
 int supplicant_dpp_dispatch(const struct device *dev, struct wifi_dpp_params *params);
-
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-/**
- * @brief Dispatch DPP operations for AP
- *
- * @param dev Wi-Fi interface name to use
- * @param dpp_params DPP action enum and params in string
- * @return 0 for OK; -1 for ERROR
- */
-int hapd_dpp_dispatch(const struct device *dev, struct wifi_dpp_params *params);
-#endif /* CONFIG_WIFI_NM_HOSTAPD_AP */
 #endif /* CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP */
 #endif /* ZEPHYR_SUPP_MGMT_H */
diff --git a/modules/hostap/src/supp_events.c b/modules/hostap/src/supp_events.c
index 22b406e2fdc..596ffa6ff56 100644
--- a/modules/hostap/src/supp_events.c
+++ b/modules/hostap/src/supp_events.c
@@ -252,11 +252,7 @@ int supplicant_send_wifi_mgmt_disc_event(void *ctx, int reason_code)
 }
 
 #ifdef CONFIG_AP
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-static enum wifi_link_mode get_sta_link_mode(struct hostapd_iface *iface, struct sta_info *sta)
-#else
 static enum wifi_link_mode get_sta_link_mode(struct wpa_supplicant *wpa_s, struct sta_info *sta)
-#endif
 {
 	if (sta->flags & WLAN_STA_HE) {
 		return WIFI_6;
@@ -264,37 +260,17 @@ static enum wifi_link_mode get_sta_link_mode(struct wpa_supplicant *wpa_s, struc
 		return WIFI_5;
 	} else if (sta->flags & WLAN_STA_HT) {
 		return WIFI_4;
-#ifndef CONFIG_WIFI_NM_HOSTAPD_AP
 	} else if (sta->flags & WLAN_STA_NONERP) {
 		return WIFI_1;
 	} else if (wpa_s->assoc_freq > 4000) {
 		return WIFI_2;
 	} else if (wpa_s->assoc_freq > 2000) {
 		return WIFI_3;
-#else
-	} else if ((sta->flags & WLAN_STA_NONERP) ||
-		   (iface->current_mode->mode == HOSTAPD_MODE_IEEE80211B)) {
-		return WIFI_1;
-	} else if (iface->freq > 4000) {
-		return WIFI_2;
-	} else if (iface->freq > 2000) {
-		return WIFI_3;
-#endif
 	} else {
 		return WIFI_LINK_MODE_UNKNOWN;
 	}
 }
 
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-static bool is_twt_capable(struct hostapd_iface *iface, struct sta_info *sta)
-{
-#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_11AX
-	return hostapd_get_he_twt_responder(iface->bss[0], IEEE80211_MODE_AP);
-#else
-	return false;
-#endif
-}
-#else
 static bool is_twt_capable(struct wpa_supplicant *wpa_s, struct sta_info *sta)
 {
 #ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_11AX
@@ -303,19 +279,13 @@ static bool is_twt_capable(struct wpa_supplicant *wpa_s, struct sta_info *sta)
 	return false;
 #endif
 }
-#endif
 
 int supplicant_send_wifi_mgmt_ap_status(void *ctx,
 					enum net_event_wifi_cmd event,
 					enum wifi_ap_status ap_status)
 {
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-	struct hostapd_iface *iface = ctx;
-	char *ifname = iface->conf->bss[0]->iface;
-#else
 	struct wpa_supplicant *wpa_s = ctx;
 	char *ifname = wpa_s->ifname;
-#endif
 	int status = ap_status;
 
 	return supplicant_send_wifi_mgmt_event(ifname,
@@ -329,13 +299,8 @@ int supplicant_send_wifi_mgmt_ap_sta_event(void *ctx,
 					   void *data)
 {
 	struct sta_info *sta = data;
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-	struct hostapd_iface *ap_ctx = ctx;
-	char *ifname = ap_ctx->bss[0]->conf->iface;
-#else
 	struct wpa_supplicant *ap_ctx = ctx;
 	char *ifname = ap_ctx->ifname;
-#endif
 	struct wifi_ap_sta_info sta_info = { 0 };
 
 	if (!ap_ctx || !sta) {
@@ -463,42 +428,3 @@ int supplicant_generate_state_event(const char *ifname,
 
 	return 0;
 }
-
-#if defined(CONFIG_WIFI_NM_HOSTAPD_AP) && defined(CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP)
-void hostapd_handle_dpp_event(void *ctx, char *buf, size_t len)
-{
-	struct hostapd_data *hapd = (struct hostapd_data *)ctx;
-
-	if (hapd == NULL) {
-		return;
-	}
-
-	struct hostapd_bss_config *conf = hapd->conf;
-
-	if (conf == NULL || !(conf->wpa_key_mgmt & WPA_KEY_MGMT_DPP)) {
-		return;
-	}
-
-	/* check hostapd */
-	if (!strncmp(buf, DPP_EVENT_CONNECTOR, sizeof(DPP_EVENT_CONNECTOR) - 1)) {
-		if (conf->dpp_connector) {
-			os_free(conf->dpp_connector);
-		}
-
-		conf->dpp_connector = os_strdup(buf + sizeof(DPP_EVENT_CONNECTOR) - 1);
-	} else if (!strncmp(buf, DPP_EVENT_C_SIGN_KEY, sizeof(DPP_EVENT_C_SIGN_KEY) - 1)) {
-		if (conf->dpp_csign) {
-			wpabuf_free(conf->dpp_csign);
-		}
-
-		conf->dpp_csign = wpabuf_parse_bin(buf + sizeof(DPP_EVENT_C_SIGN_KEY) - 1);
-	} else if (!strncmp(buf, DPP_EVENT_NET_ACCESS_KEY, sizeof(DPP_EVENT_NET_ACCESS_KEY) - 1)) {
-		if (conf->dpp_netaccesskey) {
-			wpabuf_free(conf->dpp_netaccesskey);
-		}
-
-		conf->dpp_netaccesskey =
-			wpabuf_parse_bin(buf + sizeof(DPP_EVENT_NET_ACCESS_KEY) - 1);
-	}
-}
-#endif /* CONFIG_WIFI_NM_HOSTAPD_AP && CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP */
diff --git a/modules/hostap/src/supp_events.h b/modules/hostap/src/supp_events.h
index 308a9e49734..dc922940d78 100644
--- a/modules/hostap/src/supp_events.h
+++ b/modules/hostap/src/supp_events.h
@@ -63,9 +63,6 @@ int supplicant_send_wifi_mgmt_ap_sta_event(void *ctx,
 					   enum net_event_wifi_cmd event,
 					   void *data);
 #endif /* CONFIG_AP */
-#if defined(CONFIG_WIFI_NM_HOSTAPD_AP) && defined(CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP)
-void hostapd_handle_dpp_event(void *ctx, char *buf, size_t len);
-#endif
 
 #define REASON_CODE_LEN 18
 #define NM_WIFI_EVENT_STR_LEN 64
diff --git a/modules/hostap/src/supp_main.c b/modules/hostap/src/supp_main.c
index 09bf22141f9..5ba2ef5b10c 100644
--- a/modules/hostap/src/supp_main.c
+++ b/modules/hostap/src/supp_main.c
@@ -46,10 +46,7 @@ static K_THREAD_STACK_DEFINE(iface_wq_stack, CONFIG_WIFI_NM_WPA_SUPPLICANT_WQ_ST
 #include "wpa_cli_zephyr.h"
 #ifdef CONFIG_WIFI_NM_HOSTAPD_AP
 #include "hostapd.h"
-#include "hostapd_cli_zephyr.h"
-#include "eap_register.h"
-#include "ap_drv_ops.h"
-#include "l2_packet/l2_packet.h"
+#include "hapd_main.h"
 #endif
 
 static const struct wifi_mgmt_ops mgmt_ops = {
@@ -100,29 +97,6 @@ static const struct wifi_mgmt_ops mgmt_ops = {
 
 DEFINE_WIFI_NM_INSTANCE(wifi_supplicant, &mgmt_ops);
 
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-static const struct wifi_mgmt_ops mgmt_ap_ops = {
-	.ap_enable = supplicant_ap_enable,
-	.ap_disable = supplicant_ap_disable,
-	.ap_sta_disconnect = supplicant_ap_sta_disconnect,
-	.iface_status = supplicant_ap_status,
-#ifdef CONFIG_WIFI_NM_HOSTAPD_WPS
-	.wps_config = supplicant_ap_wps_config,
-#endif
-#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP
-	.dpp_dispatch = hapd_dpp_dispatch,
-#endif /* CONFIG_WIFI_NM_WPA_SUPPLICANT_DPP */
-	.ap_config_params = supplicant_ap_config_params,
-	.set_rts_threshold = supplicant_set_rts_threshold,
-#ifdef CONFIG_WIFI_NM_HOSTAPD_CRYPTO_ENTERPRISE
-	.enterprise_creds = supplicant_add_enterprise_creds,
-#endif
-	.set_btwt = supplicant_set_btwt,
-};
-
-DEFINE_WIFI_NM_INSTANCE(hostapd, &mgmt_ap_ops);
-#endif
-
 #define WRITE_TIMEOUT 100 /* ms */
 #ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_INF_MON
 #define INTERFACE_EVENT_MASK (NET_EVENT_IF_ADMIN_UP | NET_EVENT_IF_ADMIN_DOWN)
@@ -141,38 +115,6 @@ struct supplicant_context {
 	int (*iface_handler)(struct supplicant_context *ctx, struct net_if *iface);
 };
 
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-struct hapd_global {
-	void **drv_priv;
-	size_t drv_count;
-};
-
-static struct hapd_global hglobal;
-
-#ifndef HOSTAPD_CLEANUP_INTERVAL
-#define HOSTAPD_CLEANUP_INTERVAL 10
-#endif /* HOSTAPD_CLEANUP_INTERVAL */
-
-static void zephyr_hostap_ctrl_iface_msg_cb(void *ctx, int level, enum wpa_msg_type type,
-					    const char *txt, size_t len);
-
-static int hostapd_periodic_call(struct hostapd_iface *iface, void *ctx)
-{
-	hostapd_periodic_iface(iface);
-	return 0;
-}
-
-/* Periodic cleanup tasks */
-static void hostapd_periodic(void *eloop_ctx, void *timeout_ctx)
-{
-	struct hapd_interfaces *interfaces = eloop_ctx;
-
-	eloop_register_timeout(HOSTAPD_CLEANUP_INTERVAL, 0,
-			       hostapd_periodic, interfaces, NULL);
-	hostapd_for_each_interface(interfaces, hostapd_periodic_call, NULL);
-}
-#endif
-
 static struct supplicant_context *get_default_context(void)
 {
 	static struct supplicant_context ctx;
@@ -185,6 +127,13 @@ struct wpa_global *zephyr_get_default_supplicant_context(void)
 	return get_default_context()->supplicant;
 }
 
+#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
+struct hapd_interfaces *zephyr_get_default_hapd_context(void)
+{
+	return &get_default_context()->hostapd;
+}
+#endif
+
 struct k_work_q *get_workq(void)
 {
 	return &get_default_context()->iface_wq;
@@ -265,22 +214,6 @@ struct wpa_supplicant *zephyr_get_handle_by_ifname(const char *ifname)
 	return wpa_s;
 }
 
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-struct hostapd_iface *zephyr_get_hapd_handle_by_ifname(const char *ifname)
-{
-	struct hostapd_data *hapd = NULL;
-	struct supplicant_context *ctx = get_default_context();
-
-	hapd = hostapd_get_iface(&ctx->hostapd, ifname);
-	if (!hapd) {
-		wpa_printf(MSG_ERROR, "%s: Unable to get hapd handle for %s\n", __func__, ifname);
-		return NULL;
-	}
-
-	return hapd->iface;
-}
-#endif
-
 static int get_iface_count(struct supplicant_context *ctx)
 {
 	/* FIXME, should not access ifaces as it is supplicant internal data */
@@ -294,6 +227,80 @@ static int get_iface_count(struct supplicant_context *ctx)
 	return count;
 }
 
+static void zephyr_wpa_supplicant_msg(void *ctx, const char *txt, size_t len)
+{
+	struct wpa_supplicant *wpa_s = (struct wpa_supplicant *)ctx;
+
+	if (!ctx || !txt) {
+		return;
+	}
+
+	/* Only interested in CTRL-EVENTs */
+	if (strncmp(txt, "CTRL-EVENT", 10) == 0) {
+		if (strncmp(txt, "CTRL-EVENT-SIGNAL-CHANGE", 24) == 0) {
+			supplicant_send_wifi_mgmt_event(wpa_s->ifname,
+						NET_EVENT_WIFI_CMD_SIGNAL_CHANGE,
+						(void *)txt, len);
+		} else {
+			supplicant_send_wifi_mgmt_event(wpa_s->ifname,
+						NET_EVENT_WIFI_CMD_SUPPLICANT,
+						(void *)txt, len);
+		}
+	} else if (strncmp(txt, "RRM-NEIGHBOR-REP-RECEIVED", 25) == 0) {
+		supplicant_send_wifi_mgmt_event(wpa_s->ifname,
+						NET_EVENT_WIFI_CMD_NEIGHBOR_REP_RECEIVED,
+						(void *)txt, len);
+	}
+}
+
+static const char *zephyr_hostap_msg_ifname_cb(void *ctx)
+{
+	if (ctx == NULL) {
+		return NULL;
+	}
+
+#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
+	if ((((struct wpa_supplicant *)ctx))->is_hostapd == 0) {
+		struct wpa_supplicant *wpa_s = ctx;
+
+		return wpa_s->ifname;
+	}
+
+	struct hostapd_data *hapd = ctx;
+
+	if (hapd && hapd->conf) {
+		return hapd->conf->iface;
+	}
+
+	return NULL;
+#else
+	struct wpa_supplicant *wpa_s = ctx;
+
+	return wpa_s->ifname;
+#endif
+}
+
+static void zephyr_hostap_ctrl_iface_msg_cb(void *ctx, int level, enum wpa_msg_type type,
+					    const char *txt, size_t len)
+{
+	ARG_UNUSED(level);
+	ARG_UNUSED(type);
+
+	if (ctx == NULL) {
+		return;
+	}
+
+#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
+	if ((((struct wpa_supplicant *)ctx))->is_hostapd == 0) {
+		zephyr_wpa_supplicant_msg(ctx, txt, len);
+	} else {
+		zephyr_hostapd_msg(ctx, txt, len);
+	}
+#else
+	zephyr_wpa_supplicant_msg(ctx, txt, len);
+#endif
+}
+
 static int add_interface(struct supplicant_context *ctx, struct net_if *iface)
 {
 	struct wpa_supplicant *wpa_s;
@@ -355,9 +362,7 @@ static int add_interface(struct supplicant_context *ctx, struct net_if *iface)
 		supplicant_generate_state_event(ifname, NET_EVENT_SUPPLICANT_CMD_READY, 0);
 	}
 
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
 	wpa_msg_register_cb(zephyr_hostap_ctrl_iface_msg_cb);
-#endif
 	ret = 0;
 
 out:
@@ -639,502 +644,13 @@ static int register_supplicant_event_socket(struct supplicant_context *ctx)
 	return 0;
 }
 
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-struct hostapd_iface *hostapd_get_interface(const char *ifname)
-{
-	struct supplicant_context *ctx;
-
-	ctx = get_default_context();
-	(void)ifname;
-	return ctx->hostapd.iface[0];
-}
-
-static void hostapd_event_eapol_rx_cb(void *ctx, const u8 *src_addr,
-				       const u8 *buf, size_t len)
-{
-	hostapd_event_eapol_rx(ctx, src_addr, buf, len, FRAME_ENCRYPTION_UNKNOWN, -1);
-}
-
-static int hostapd_enable_iface_cb(struct hostapd_iface *hapd_iface)
-{
-	struct hostapd_data *bss;
-
-	wpa_printf(MSG_DEBUG, "Enable interface %s", hapd_iface->conf->bss[0]->iface);
-
-	bss = hapd_iface->bss[0];
-
-	bss->conf->start_disabled = 0;
-
-	if (hostapd_config_check(hapd_iface->conf, 1) < 0) {
-		wpa_printf(MSG_INFO, "Invalid configuration - cannot enable");
-		return -1;
-	}
-
-	l2_packet_deinit(bss->l2);
-	bss->l2 = l2_packet_init(bss->conf->iface, bss->conf->bssid, ETH_P_EAPOL,
-				 &hostapd_event_eapol_rx_cb, bss, 0);
-	if (bss->l2 == NULL) {
-		wpa_printf(MSG_ERROR, "Failed to initialize l2 for hostapd interface");
-		return -1;
-	}
-
-	if (hostapd_setup_interface(hapd_iface)) {
-		wpa_printf(MSG_ERROR, "Failed to initialize hostapd interface");
-		return -1;
-	}
-
-	return 0;
-}
-
-static int hostapd_disable_iface_cb(struct hostapd_iface *hapd_iface)
-{
-	size_t j;
-	struct hostapd_data *hapd = NULL;
-
-	wpa_msg(hapd_iface->bss[0]->msg_ctx, MSG_INFO, AP_EVENT_DISABLED);
-
-	hapd_iface->driver_ap_teardown = !!(hapd_iface->drv_flags
-					    & WPA_DRIVER_FLAGS_AP_TEARDOWN_SUPPORT);
-
-#ifdef NEED_AP_MLME
-	for (j = 0; j < hapd_iface->num_bss; j++) {
-		hostapd_cleanup_cs_params(hapd_iface->bss[j]);
-	}
-#endif /* NEED_AP_MLME */
-
-	/* Same as hostapd_interface_deinit() without deinitializing control
-	 * interface
-	 */
-	for (j = 0; j < hapd_iface->num_bss; j++) {
-		hapd = hapd_iface->bss[j];
-		hostapd_bss_deinit_no_free(hapd);
-		hostapd_free_hapd_data(hapd);
-	}
-
-	hostapd_drv_stop_ap(hapd);
-
-	hostapd_cleanup_iface_partial(hapd_iface);
-
-	wpa_printf(MSG_DEBUG, "Interface %s disabled", hapd_iface->bss[0]->conf->iface);
-	hostapd_set_state(hapd_iface, HAPD_IFACE_DISABLED);
-	supplicant_send_wifi_mgmt_ap_status(hapd_iface,
-					    NET_EVENT_WIFI_CMD_AP_DISABLE_RESULT,
-					    WIFI_STATUS_AP_SUCCESS);
-	hostapd_config_free(hapd_iface->conf);
-	hapd_iface->conf = hapd_iface->interfaces->config_read_cb(hapd_iface->config_fname);
-	for (j = 0; j < hapd_iface->num_bss; j++) {
-		hapd = hapd_iface->bss[j];
-		hapd->iconf = hapd_iface->conf;
-		hapd->conf = hapd_iface->conf->bss[j];
-		hapd->driver = hapd_iface->conf->driver;
-	}
-
-	return 0;
-}
-
-static int hostapd_global_init(struct hapd_interfaces *interfaces, const char *entropy_file)
-{
-	int i;
-
-	os_memset(&hglobal, 0, sizeof(struct hapd_global));
-
-	if (eap_server_register_methods()) {
-		wpa_printf(MSG_ERROR, "Failed to register EAP methods");
-		return -1;
-	}
-
-	interfaces->eloop_initialized = 1;
-
-	for (i = 0; wpa_drivers[i]; i++) {
-		hglobal.drv_count++;
-	}
-
-	if (hglobal.drv_count == 0) {
-		wpa_printf(MSG_ERROR, "No drivers enabled");
-		return -1;
-	}
-	hglobal.drv_priv = os_calloc(hglobal.drv_count, sizeof(void *));
-	if (hglobal.drv_priv == NULL) {
-		return -1;
-	}
-
-	return 0;
-}
-
-static int hostapd_driver_init(struct hostapd_iface *iface)
-{
-	struct wpa_init_params params;
-	size_t i;
-	struct hostapd_data *hapd       = iface->bss[0];
-	struct hostapd_bss_config *conf = hapd->conf;
-	u8 *b                           = conf->bssid;
-	struct wpa_driver_capa capa;
-
-	if (hapd->driver == NULL || hapd->driver->hapd_init == NULL) {
-		wpa_printf(MSG_ERROR, "No hostapd driver wrapper available");
-		return -1;
-	}
-
-	/* Initialize the driver interface */
-	if (!(b[0] | b[1] | b[2] | b[3] | b[4] | b[5])) {
-		b = NULL;
-	}
-
-	os_memset(&params, 0, sizeof(params));
-	for (i = 0; wpa_drivers[i]; i++) {
-		if (wpa_drivers[i] != hapd->driver)
-			continue;
-
-		if (hglobal.drv_priv[i] == NULL && wpa_drivers[i]->global_init) {
-			hglobal.drv_priv[i] = wpa_drivers[i]->global_init(iface->interfaces);
-			if (hglobal.drv_priv[i] == NULL) {
-				wpa_printf(MSG_ERROR, "Failed to initialize driver '%s'",
-					   wpa_drivers[i]->name);
-				return -1;
-			}
-			hglobal.drv_count++;
-		}
-
-		params.global_priv = hglobal.drv_priv[i];
-		break;
-	}
-	params.bssid              = b;
-	params.ifname             = hapd->conf->iface;
-	params.driver_params      = hapd->iconf->driver_params;
-	params.use_pae_group_addr = hapd->conf->use_pae_group_addr;
-	params.num_bridge         = hapd->iface->num_bss;
-	params.bridge             = os_calloc(hapd->iface->num_bss, sizeof(char *));
-	if (params.bridge == NULL) {
-		return -1;
-	}
-	for (i = 0; i < hapd->iface->num_bss; i++) {
-		struct hostapd_data *bss = hapd->iface->bss[i];
-
-		if (bss->conf->bridge[0]) {
-			params.bridge[i] = bss->conf->bridge;
-		}
-	}
-
-	params.own_addr = hapd->own_addr;
-
-	hapd->drv_priv = hapd->driver->hapd_init(hapd, &params);
-	os_free(params.bridge);
-	if (hapd->drv_priv == NULL) {
-		wpa_printf(MSG_ERROR, "%s driver initialization failed.",
-			   hapd->driver->name);
-		hapd->driver = NULL;
-		return -1;
-	}
-
-	if (hapd->driver->get_capa && hapd->driver->get_capa(hapd->drv_priv, &capa) == 0) {
-		struct wowlan_triggers *triggs;
-
-		iface->drv_flags           = capa.flags;
-		iface->drv_flags2          = capa.flags2;
-		iface->probe_resp_offloads = capa.probe_resp_offloads;
-		/*
-		 * Use default extended capa values from per-radio information
-		 */
-		iface->extended_capa         = capa.extended_capa;
-		iface->extended_capa_mask    = capa.extended_capa_mask;
-		iface->extended_capa_len     = capa.extended_capa_len;
-		iface->drv_max_acl_mac_addrs = capa.max_acl_mac_addrs;
-
-		/*
-		 * Override extended capa with per-interface type (AP), if
-		 * available from the driver.
-		 */
-		hostapd_get_ext_capa(iface);
-
-		triggs = wpa_get_wowlan_triggers(conf->wowlan_triggers, &capa);
-		if (triggs && hapd->driver->set_wowlan) {
-			if (hapd->driver->set_wowlan(hapd->drv_priv, triggs)) {
-				wpa_printf(MSG_ERROR, "set_wowlan failed");
-			}
-		}
-		os_free(triggs);
-	}
-
-	return 0;
-}
-
-struct hostapd_config *hostapd_config_read2(const char *fname)
-{
-	struct hostapd_config *conf;
-	const struct device *dev;
-	char ifname[IFNAMSIZ + 1] = {0};
-	int errors = 0;
-	size_t i;
-	int aCWmin = 4, aCWmax = 10;
-	/* background traffic */
-	struct hostapd_wmm_ac_params ac_bk = {aCWmin, aCWmax, 9, 0, 0};
-	/* best effort traffic */
-	struct hostapd_wmm_ac_params ac_be = {aCWmin, aCWmax - 4, 5, 0, 0};
-	/* video traffic */
-	struct hostapd_wmm_ac_params ac_vi = {aCWmin - 1, aCWmin, 3,
-					      3008 / 32, 0};
-	/* voice traffic */
-	struct hostapd_wmm_ac_params ac_vo = {aCWmin - 2, aCWmin - 1, 3,
-					      1504 / 32, 0};
-
-	dev = net_if_get_device(net_if_get_wifi_sap());
-	strncpy(ifname, dev->name, IFNAMSIZ);
-	ifname[IFNAMSIZ] = '\0';
-
-	conf = hostapd_config_defaults();
-	if (conf == NULL) {
-		return NULL;
-	}
-
-	conf->wmm_ac_params[0] = ac_be;
-	conf->wmm_ac_params[1] = ac_bk;
-	conf->wmm_ac_params[2] = ac_vi;
-	conf->wmm_ac_params[3] = ac_vo;
-
-	/* set default driver based on configuration */
-	conf->driver = wpa_drivers[0];
-	if (conf->driver == NULL) {
-		wpa_printf(MSG_ERROR, "No driver wrappers registered!");
-		hostapd_config_free(conf);
-		return NULL;
-	}
-	conf->last_bss = conf->bss[0];
-	struct hostapd_bss_config *bss;
-
-	bss                 = conf->last_bss;
-	bss->start_disabled = 1;
-	bss->max_num_sta    = CONFIG_WIFI_MGMT_AP_MAX_NUM_STA;
-	bss->dtim_period    = 1;
-	os_strlcpy(conf->bss[0]->iface, ifname, sizeof(conf->bss[0]->iface));
-	bss->logger_stdout_level = HOSTAPD_LEVEL_INFO;
-	bss->logger_stdout       = 0xffff;
-	bss->nas_identifier      = os_strdup("ap.example.com");
-	os_memcpy(conf->country, "US ", 3);
-	conf->hw_mode        = HOSTAPD_MODE_IEEE80211G;
-	bss->wps_state       = WPS_STATE_CONFIGURED;
-	bss->eap_server      = 1;
-#ifdef CONFIG_WPS
-	bss->ap_setup_locked = 1;
-#endif
-	conf->channel        = 1;
-	conf->acs            = conf->channel == 0;
-#ifdef CONFIG_ACS
-	conf->acs_num_scans  = 1;
-#endif
-	conf->ieee80211n     = 1;
-	conf->ieee80211h     = 0;
-	conf->ieee80211d     = 1;
-	conf->acs_exclude_dfs = 1;
-	conf->ht_capab |= HT_CAP_INFO_SHORT_GI20MHZ;
-	bss->auth_algs = 1;
-	bss->okc = 1;
-	conf->no_pri_sec_switch = 1;
-	conf->ht_op_mode_fixed  = 1;
-	conf->ieee80211ac       = 1;
-	conf->vht_oper_chwidth  = CHANWIDTH_USE_HT;
-	conf->vht_capab |= VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MAX;
-#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_11AX
-	conf->ieee80211ax       = 1;
-	conf->he_oper_chwidth   = CHANWIDTH_USE_HT;
-	conf->he_phy_capab.he_su_beamformer = 0;
-	conf->he_phy_capab.he_su_beamformee = 1;
-	conf->he_phy_capab.he_mu_beamformer = 0;
-	conf->he_op.he_bss_color = 1;
-	conf->he_op.he_default_pe_duration  = 0;
-	/* Set default basic MCS/NSS set to single stream MCS 0-7 */
-	conf->he_op.he_basic_mcs_nss_set    = 0xfffc;
-#endif
-
-	for (i = 0; i < conf->num_bss; i++) {
-		hostapd_set_security_params(conf->bss[i], 1);
-	}
-
-	if (hostapd_config_check(conf, 1)) {
-		errors++;
-	}
-
-#ifndef WPA_IGNORE_CONFIG_ERRORS
-	if (errors) {
-		wpa_printf(MSG_ERROR, "%d errors found in configuration file '%s'",
-			   errors, fname);
-		hostapd_config_free(conf);
-		conf = NULL;
-	}
-#endif /* WPA_IGNORE_CONFIG_ERRORS */
-	return conf;
-}
-
-static struct hostapd_iface *hostapd_interface_init(struct hapd_interfaces *interfaces,
-						    const char *if_name,
-						    const char *config_fname,
-						    int debug)
-{
-	struct hostapd_iface *iface;
-	int k;
-
-	wpa_printf(MSG_DEBUG, "Configuration file: %s", config_fname);
-	iface = hostapd_init(interfaces, config_fname);
-	if (!iface) {
-		return NULL;
-	}
-
-	if (if_name) {
-		os_strlcpy(iface->conf->bss[0]->iface, if_name,
-			   sizeof(iface->conf->bss[0]->iface));
-	}
-
-	iface->interfaces = interfaces;
-
-	for (k = 0; k < debug; k++) {
-		if (iface->bss[0]->conf->logger_stdout_level > 0) {
-			iface->bss[0]->conf->logger_stdout_level--;
-		}
-	}
-
-	if (iface->conf->bss[0]->iface[0] == '\0' &&
-	    !hostapd_drv_none(iface->bss[0])) {
-		wpa_printf(MSG_ERROR,
-			   "Interface name not specified in %s, nor by '-i' parameter",
-			   config_fname);
-		hostapd_interface_deinit_free(iface);
-		return NULL;
-	}
-
-	iface->bss[0]->is_hostapd = 1;
-
-	return iface;
-}
-
-static void zephyr_hostapd_init(struct supplicant_context *ctx)
-{
-	struct hapd_interfaces *interfaces = &ctx->hostapd;
-	size_t i;
-	int ret, debug = 0;
-	struct net_if *iface;
-	char ifname[IFNAMSIZ + 1] = { 0 };
-	const char *entropy_file = NULL;
-	size_t num_bss_configs = 0;
-	int start_ifaces_in_sync = 0;
-#ifdef CONFIG_DPP
-	struct dpp_global_config dpp_conf;
-#endif /* CONFIG_DPP */
-
-	os_memset(interfaces, 0, sizeof(struct hapd_interfaces));
-	interfaces->reload_config      = hostapd_reload_config;
-	interfaces->config_read_cb     = hostapd_config_read2;
-	interfaces->for_each_interface = hostapd_for_each_interface;
-	interfaces->driver_init        = hostapd_driver_init;
-	interfaces->global_ctrl_sock   = -1;
-	dl_list_init(&interfaces->global_ctrl_dst);
-#ifdef CONFIG_DPP
-	os_memset(&dpp_conf, 0, sizeof(dpp_conf));
-	dpp_conf.cb_ctx = interfaces;
-	interfaces->dpp = dpp_global_init(&dpp_conf);
-	if (!interfaces->dpp) {
-		return;
-	}
-#endif /* CONFIG_DPP */
-
-	interfaces->count = 1;
-	if (interfaces->count || num_bss_configs) {
-		interfaces->iface = os_calloc(interfaces->count + num_bss_configs,
-					      sizeof(struct hostapd_iface *));
-		if (interfaces->iface == NULL) {
-			wpa_printf(MSG_ERROR, "malloc failed");
-			return;
-		}
-	}
-
-	if (hostapd_global_init(interfaces, entropy_file)) {
-		wpa_printf(MSG_ERROR, "Failed to initialize global context");
-		return;
-	}
-
-	eloop_register_timeout(HOSTAPD_CLEANUP_INTERVAL, 0,
-			       hostapd_periodic, interfaces, NULL);
-
-	iface = net_if_get_wifi_sap();
-	ret = net_if_get_name(iface, ifname, sizeof(ifname) - 1);
-	if (ret < 0) {
-		LOG_ERR("Cannot get interface %d (%p) name", net_if_get_by_iface(iface), iface);
-		goto out;
-	}
-
-	for (i = 0; i < interfaces->count; i++) {
-		interfaces->iface[i] = hostapd_interface_init(interfaces, ifname,
-							      "hostapd.conf", debug);
-		if (!interfaces->iface[i]) {
-			wpa_printf(MSG_ERROR, "Failed to initialize interface");
-			goto out;
-		}
-		if (start_ifaces_in_sync) {
-			interfaces->iface[i]->need_to_start_in_sync = 0;
-		}
-	}
-
-	/*
-	 * Enable configured interfaces. Depending on channel configuration,
-	 * this may complete full initialization before returning or use a
-	 * callback mechanism to complete setup in case of operations like HT
-	 * co-ex scans, ACS, or DFS are needed to determine channel parameters.
-	 * In such case, the interface will be enabled from eloop context within
-	 * hostapd_global_run().
-	 */
-	interfaces->terminate_on_error = 0;
-	for (i = 0; i < interfaces->count; i++) {
-		if (hostapd_driver_init(interfaces->iface[i])) {
-			goto out;
-		}
-
-		interfaces->iface[i]->enable_iface_cb  = hostapd_enable_iface_cb;
-		interfaces->iface[i]->disable_iface_cb = hostapd_disable_iface_cb;
-		zephyr_hostapd_ctrl_init((void *)interfaces->iface[i]->bss[0]);
-	}
-
-out:
-	return;
-}
-
-static const char *zephyr_hostap_msg_ifname_cb(void *ctx)
-{
-	if (ctx == NULL) {
-		return NULL;
-	}
-
-	if ((*((int *)ctx)) == 0) {
-		struct wpa_supplicant *wpa_s = ctx;
-
-		return wpa_s->ifname;
-	}
-
-	struct hostapd_data *hapd = ctx;
-
-	if (hapd && hapd->conf) {
-		return hapd->conf->iface;
-	}
-
-	return NULL;
-}
-
-static void zephyr_hostap_ctrl_iface_msg_cb(void *ctx, int level, enum wpa_msg_type type,
-					    const char *txt, size_t len)
-{
-	if (ctx == NULL) {
-		return;
-	}
-
-	if ((*((int *)ctx)) == 0) {
-		wpa_supplicant_msg_send(ctx, level, type, txt, len);
-	} else {
-		hostapd_msg_send(ctx, level, type, txt, len);
-	}
-}
-#endif
-
 static void handler(void)
 {
 	struct supplicant_context *ctx;
 	struct wpa_params params;
+	struct k_work_queue_config iface_wq_cfg = {
+		.name = "hostap_iface_wq",
+	};
 
 #if !defined(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_NONE) && !defined(CONFIG_MBEDTLS_ENABLE_HEAP)
 	/* Needed for crypto operation as default is no-op and fails */
@@ -1151,7 +667,7 @@ static void handler(void)
 	k_work_queue_start(&ctx->iface_wq, iface_wq_stack,
 			   K_THREAD_STACK_SIZEOF(iface_wq_stack),
 			   CONFIG_WIFI_NM_WPA_SUPPLICANT_WQ_PRIO,
-			   NULL);
+			   &iface_wq_cfg);
 
 	k_work_init(&ctx->iface_work, iface_work_handler);
 
@@ -1183,9 +699,9 @@ static void handler(void)
 	submit_iface_work(ctx, NULL, setup_interface_monitoring);
 
 #ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-	zephyr_hostapd_init(ctx);
-	wpa_msg_register_ifname_cb(zephyr_hostap_msg_ifname_cb);
+	zephyr_hostapd_init(&ctx->hostapd);
 #endif
+	wpa_msg_register_ifname_cb(zephyr_hostap_msg_ifname_cb);
 
 	(void)wpa_supplicant_run(ctx->supplicant);
 
@@ -1209,13 +725,30 @@ static void handler(void)
 
 static int init(void)
 {
+	k_tid_t id;
+
 	/* We create a thread that handles all supplicant connections */
-	k_thread_create(&tid, supplicant_thread_stack,
-			K_THREAD_STACK_SIZEOF(supplicant_thread_stack),
-			(k_thread_entry_t)handler, NULL, NULL, NULL,
-			CONFIG_WIFI_NM_WPA_SUPPLICANT_PRIO, 0, K_NO_WAIT);
+	id = k_thread_create(&tid, supplicant_thread_stack,
+			     K_THREAD_STACK_SIZEOF(supplicant_thread_stack),
+			     (k_thread_entry_t)handler, NULL, NULL, NULL,
+			     CONFIG_WIFI_NM_WPA_SUPPLICANT_PRIO, 0, K_NO_WAIT);
+
+	k_thread_name_set(id, "hostap_handler");
 
 	return 0;
 }
 
 SYS_INIT(init, APPLICATION, 0);
+
+static enum net_verdict eapol_recv(struct net_if *iface, uint16_t ptype,
+				   struct net_pkt *pkt)
+{
+	ARG_UNUSED(iface);
+	ARG_UNUSED(ptype);
+
+	net_pkt_set_family(pkt, AF_UNSPEC);
+
+	return NET_CONTINUE;
+}
+
+ETH_NET_L3_REGISTER(EAPOL, NET_ETH_PTYPE_EAPOL, eapol_recv);
diff --git a/modules/hostap/src/supp_main.h b/modules/hostap/src/supp_main.h
index 981bdf66958..60ac642f9c7 100644
--- a/modules/hostap/src/supp_main.h
+++ b/modules/hostap/src/supp_main.h
@@ -15,7 +15,8 @@
 	!defined(CONFIG_EAP_PSK) && !defined(CONFIG_EAP_PAX) && \
 	!defined(CONFIG_EAP_SAKE) && !defined(CONFIG_EAP_GPSK) && \
 	!defined(CONFIG_EAP_PWD) && !defined(CONFIG_EAP_EKE) && \
-	!defined(CONFIG_EAP_IKEV2) && !defined(CONFIG_EAP_GTC)
+	!defined(CONFIG_EAP_IKEV2) && !defined(CONFIG_EAP_GTC) && \
+	!defined(CONFIG_EAP_LEAP)
 #error "At least one of the following EAP methods need to be defined    \
 	CONFIG_EAP_TLS    \
 	CONFIG_EAP_TTLS   \
@@ -54,15 +55,11 @@ struct wpa_global *zephyr_get_default_supplicant_context(void);
 struct wpa_supplicant *zephyr_get_handle_by_ifname(const char *ifname);
 
 #ifdef CONFIG_WIFI_NM_HOSTAPD_AP
-#include "common.h"
-#include "wpa_debug_zephyr.h"
-
-struct hostapd_iface *zephyr_get_hapd_handle_by_ifname(const char *ifname);
-void wpa_supplicant_msg_send(void *ctx, int level, enum wpa_msg_type type, const char *txt,
-			     size_t len);
-void hostapd_msg_send(void *ctx, int level, enum wpa_msg_type type, const char *buf, size_t len);
+struct hapd_interfaces *zephyr_get_default_hapd_context(void);
 #endif
 
+struct wpa_supplicant *zephyr_get_handle_by_ifname(const char *ifname);
+
 struct wpa_supplicant_event_msg {
 #ifdef CONFIG_WIFI_NM_HOSTAPD_AP
 	int hostapd;
diff --git a/modules/lvgl/CMakeLists.txt b/modules/lvgl/CMakeLists.txt
index 5ef568e6b89..e388c4159e7 100644
--- a/modules/lvgl/CMakeLists.txt
+++ b/modules/lvgl/CMakeLists.txt
@@ -313,6 +313,7 @@ zephyr_library_sources(
     lvgl.c
     lvgl_display.c
     lvgl_display_mono.c
+    lvgl_display_8bit.c
     lvgl_display_16bit.c
     lvgl_display_24bit.c
     lvgl_display_32bit.c
diff --git a/modules/lvgl/Kconfig b/modules/lvgl/Kconfig
index 803243fa43e..8084dd11a33 100644
--- a/modules/lvgl/Kconfig
+++ b/modules/lvgl/Kconfig
@@ -22,6 +22,9 @@ config LV_CONF_SKIP
 	bool
 	default n
 
+config LV_USE_PRIVATE_API
+	bool
+
 config LV_USE_LOG
 	bool
 
@@ -158,6 +161,7 @@ config LV_DRAW_DMA2D_HAL_INCLUDE
 config LV_Z_USE_OSAL
 	bool "Use OSAL enabling parallel rendering"
 	depends on DYNAMIC_THREAD
+	select LV_USE_PRIVATE_API
 	help
 	  Use the Zephyr LVGL OSAL to enable parallel rendering
 	  pipelines.
diff --git a/modules/lvgl/include/lvgl_display.h b/modules/lvgl/include/lvgl_display.h
index bbe4a3193b2..68aeceb005c 100644
--- a/modules/lvgl/include/lvgl_display.h
+++ b/modules/lvgl/include/lvgl_display.h
@@ -30,6 +30,7 @@ struct lvgl_display_flush {
 };
 
 void lvgl_flush_cb_mono(lv_display_t *display, const lv_area_t *area, uint8_t *px_map);
+void lvgl_flush_cb_8bit(lv_display_t *display, const lv_area_t *area, uint8_t *px_map);
 void lvgl_flush_cb_16bit(lv_display_t *display, const lv_area_t *area, uint8_t *px_map);
 void lvgl_flush_cb_24bit(lv_display_t *display, const lv_area_t *area, uint8_t *px_map);
 void lvgl_flush_cb_32bit(lv_display_t *display, const lv_area_t *area, uint8_t *px_map);
diff --git a/modules/lvgl/lvgl.c b/modules/lvgl/lvgl.c
index 664f6fdb03a..cce276c6635 100644
--- a/modules/lvgl/lvgl.c
+++ b/modules/lvgl/lvgl.c
@@ -146,6 +146,9 @@ static int lvgl_allocate_rendering_buffers(lv_display_t *display)
 	case PIXEL_FORMAT_RGB_565:
 		buf_size = 2 * buf_nbr_pixels;
 		break;
+	case PIXEL_FORMAT_L_8:
+		buf_size = buf_nbr_pixels;
+		break;
 	case PIXEL_FORMAT_MONO01:
 	case PIXEL_FORMAT_MONO10:
 		buf_size = buf_nbr_pixels / 8 + 8;
diff --git a/modules/lvgl/lvgl_display.c b/modules/lvgl/lvgl_display.c
index 72c371cfc84..cc79c1994be 100644
--- a/modules/lvgl/lvgl_display.c
+++ b/modules/lvgl/lvgl_display.c
@@ -96,6 +96,12 @@ int set_lvgl_rendering_cb(lv_display_t *display)
 		lv_display_add_event_cb(display, lvgl_rounder_cb, LV_EVENT_INVALIDATE_AREA,
 					display);
 		break;
+	case PIXEL_FORMAT_L_8:
+		lv_display_set_color_format(display, LV_COLOR_FORMAT_L8);
+		lv_display_set_flush_cb(display, lvgl_flush_cb_8bit);
+		lv_display_add_event_cb(display, lvgl_rounder_cb, LV_EVENT_INVALIDATE_AREA,
+					display);
+		break;
 	case PIXEL_FORMAT_MONO01:
 	case PIXEL_FORMAT_MONO10:
 		lv_display_set_color_format(display, LV_COLOR_FORMAT_I1);
diff --git a/modules/lvgl/lvgl_display_8bit.c b/modules/lvgl/lvgl_display_8bit.c
new file mode 100644
index 00000000000..a843ece19a4
--- /dev/null
+++ b/modules/lvgl/lvgl_display_8bit.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <lvgl.h>
+#include "lvgl_display.h"
+
+void lvgl_flush_cb_8bit(lv_display_t *display, const lv_area_t *area, uint8_t *px_map)
+{
+	uint16_t w = area->x2 - area->x1 + 1;
+	uint16_t h = area->y2 - area->y1 + 1;
+	struct lvgl_display_flush flush;
+
+	flush.display = display;
+	flush.x = area->x1;
+	flush.y = area->y1;
+	flush.desc.buf_size = w * h;
+	flush.desc.width = w;
+	flush.desc.pitch = w;
+	flush.desc.height = h;
+	flush.buf = (void *)px_map;
+
+	lvgl_flush_display(&flush);
+}
diff --git a/modules/lvgl/lvgl_display_mono.c b/modules/lvgl/lvgl_display_mono.c
index c843cd96b54..09b9bfd2337 100644
--- a/modules/lvgl/lvgl_display_mono.c
+++ b/modules/lvgl/lvgl_display_mono.c
@@ -9,6 +9,8 @@
 #include <string.h>
 #include "lvgl_display.h"
 
+#define COLOR_PALETTE_HEADER_SIZE (8)
+
 static uint8_t *mono_conv_buf;
 static uint32_t mono_conv_buf_size;
 
@@ -50,8 +52,9 @@ static void lvgl_transform_buffer(uint8_t **px_map, uint32_t width, uint32_t hei
 
 	memset(mono_conv_buf, clear_color, mono_conv_buf_size);
 
-	/* Needed because LVGL reserves 2x4 bytes in the buffer for the color palette. */
-	*px_map += 8;
+	/* Needed because LVGL reserves some bytes in the buffer for the color palette. */
+	*px_map += COLOR_PALETTE_HEADER_SIZE;
+
 	uint8_t *src_buf = *px_map;
 	uint32_t stride = (width + CONFIG_LV_DRAW_BUF_STRIDE_ALIGN - 1) &
 			  ~(CONFIG_LV_DRAW_BUF_STRIDE_ALIGN - 1);
@@ -67,7 +70,7 @@ static void lvgl_transform_buffer(uint8_t **px_map, uint32_t width, uint32_t hei
 		}
 	}
 
-	memcpy(src_buf, mono_conv_buf, mono_conv_buf_size);
+	memcpy(src_buf, mono_conv_buf, mono_conv_buf_size - COLOR_PALETTE_HEADER_SIZE);
 }
 
 void lvgl_flush_cb_mono(lv_display_t *display, const lv_area_t *area, uint8_t *px_map)
diff --git a/modules/lvgl/lvgl_zephyr_osal.c b/modules/lvgl/lvgl_zephyr_osal.c
index 84c118f0020..fd5adb220c6 100644
--- a/modules/lvgl/lvgl_zephyr_osal.c
+++ b/modules/lvgl/lvgl_zephyr_osal.c
@@ -13,8 +13,8 @@ LOG_MODULE_DECLARE(lvgl, CONFIG_LV_Z_LOG_LEVEL);
 typedef void (*lv_thread_entry)(void *);
 static void thread_entry(void *thread, void *cb, void *user_data);
 
-lv_result_t lv_thread_init(lv_thread_t *thread, lv_thread_prio_t prio, void (*callback)(void *),
-			   size_t stack_size, void *user_data)
+lv_result_t lv_thread_init(lv_thread_t *thread, const char *const name, lv_thread_prio_t prio,
+			   void (*callback)(void *), size_t stack_size, void *user_data)
 {
 	int thread_priority;
 
@@ -29,6 +29,8 @@ lv_result_t lv_thread_init(lv_thread_t *thread, lv_thread_prio_t prio, void (*ca
 	thread->tid = k_thread_create(&thread->thread, thread->stack, stack_size, thread_entry,
 				      thread, callback, user_data, thread_priority, 0, K_NO_WAIT);
 
+	k_thread_name_set(thread->tid, name);
+
 	return LV_RESULT_OK;
 }
 
diff --git a/modules/mbedtls/Kconfig b/modules/mbedtls/Kconfig
index 8f96afc6825..aa8c479e89f 100644
--- a/modules/mbedtls/Kconfig
+++ b/modules/mbedtls/Kconfig
@@ -59,7 +59,7 @@ config CUSTOM_MBEDTLS_CFG_FILE
 config MBEDTLS_CFG_FILE
 	string "mbed TLS configuration file" if CUSTOM_MBEDTLS_CFG_FILE
 	depends on MBEDTLS_BUILTIN
-	default "config-tls-generic.h"
+	default "config-mbedtls.h"
 	help
 	  Use a specific mbedTLS configuration file. The default config file
 	  file can be tweaked with Kconfig. The default configuration is
@@ -68,7 +68,7 @@ config MBEDTLS_CFG_FILE
 	  special TLS usage, use available Kconfig options, or select an
 	  alternative config.
 
-rsource "Kconfig.tls-generic"
+rsource "Kconfig.mbedtls"
 
 config MBEDTLS_SSL_MAX_CONTENT_LEN
 	int "Max payload size for TLS protocol message"
diff --git a/modules/mbedtls/Kconfig.mbedtls b/modules/mbedtls/Kconfig.mbedtls
new file mode 100644
index 00000000000..7c08df10538
--- /dev/null
+++ b/modules/mbedtls/Kconfig.mbedtls
@@ -0,0 +1,740 @@
+# TLS/DTLS related options
+
+# Copyright (c) 2018 Intel Corporation
+# Copyright (c) 2018 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+menu "Mbed TLS configuration"
+	depends on MBEDTLS_BUILTIN && MBEDTLS_CFG_FILE = "config-mbedtls.h"
+
+if !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
+
+menu "TLS"
+
+config MBEDTLS_TLS_VERSION_1_2
+	bool "Support for TLS 1.2 (DTLS 1.2)"
+	select MBEDTLS_CIPHER
+	select MBEDTLS_MD
+
+if MBEDTLS_TLS_VERSION_1_2
+
+config MBEDTLS_DTLS
+	bool "Support for DTLS"
+
+endif # MBEDTLS_TLS_VERSION_1_2
+
+config MBEDTLS_TLS_VERSION_1_3
+	bool "Support for TLS 1.3"
+
+if MBEDTLS_TLS_VERSION_1_3
+
+config MBEDTLS_TLS_SESSION_TICKETS
+	bool "Support for RFC 5077 session tickets in TLS 1.3"
+
+endif # MBEDTLS_TLS_VERSION_1_3
+
+if MBEDTLS_TLS_VERSION_1_2 || MBEDTLS_TLS_VERSION_1_3
+
+config MBEDTLS_SSL_ALPN
+	bool "Support for setting the supported Application Layer Protocols"
+
+endif # MBEDTLS_TLS_VERSION_1_2 || MBEDTLS_TLS_VERSION_1_3
+
+endmenu # TLS
+
+endif # !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
+
+menu "Ciphersuite configuration"
+
+comment "Supported key exchange modes"
+
+config MBEDTLS_RSA_C
+	bool "RSA base support"
+	default y if UOSCORE || UEDHOC
+
+if MBEDTLS_RSA_C
+
+config MBEDTLS_PKCS1_V15
+	bool "RSA PKCS1 v1.5"
+	default y if UOSCORE || UEDHOC
+
+config MBEDTLS_PKCS1_V21
+	bool "RSA PKCS1 v2.1"
+	default y if UOSCORE || UEDHOC
+
+config MBEDTLS_GENPRIME_ENABLED
+	bool "Prime number generation code"
+
+endif # MBEDTLS_RSA_C
+
+config MBEDTLS_RSA_FULL
+	def_bool y
+	depends on MBEDTLS_RSA_C && MBEDTLS_PKCS1_V15 && MBEDTLS_PKCS1_V21
+
+if !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
+
+config MBEDTLS_KEY_EXCHANGE_ALL_ENABLED
+	bool "All available ciphersuite modes"
+	select MBEDTLS_MD
+	select MBEDTLS_RSA_C
+	select MBEDTLS_PKCS1_V15
+	select MBEDTLS_PKCS1_V21
+	select MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
+	select MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
+	select MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
+	select MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
+	select MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
+	select MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
+	select MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
+	select MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
+	select MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
+	select MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
+	select MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
+
+config MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
+	bool "PSK based ciphersuite modes"
+
+config MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
+	bool "DHE-PSK based ciphersuite modes"
+
+config MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
+	bool "ECDHE-PSK based ciphersuite modes"
+	depends on MBEDTLS_ECDH_C
+
+config MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
+	bool "RSA-PSK based ciphersuite modes"
+	depends on MBEDTLS_RSA_FULL
+
+endif # !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
+
+config MBEDTLS_PSK_MAX_LEN
+	int "Max size of TLS pre-shared keys"
+	default 32
+	help
+	  Max size of TLS pre-shared keys, in bytes. It has no effect if no
+	  PSK key exchange is used.
+
+if !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
+
+config MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
+	bool "RSA-only based ciphersuite modes"
+	default y if UOSCORE || UEDHOC
+	depends on MBEDTLS_MD
+	depends on MBEDTLS_RSA_FULL
+	select PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY if PSA_CRYPTO_CLIENT
+	select PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT if PSA_CRYPTO_CLIENT
+	select PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT if PSA_CRYPTO_CLIENT
+	select PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE if PSA_CRYPTO_CLIENT
+	select PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_DERIVE if PSA_CRYPTO_CLIENT
+
+config MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
+	bool "DHE-RSA based ciphersuite modes"
+	depends on MBEDTLS_RSA_FULL
+
+config MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
+	bool "ECDHE-RSA based ciphersuite modes"
+	depends on MBEDTLS_RSA_FULL
+	depends on MBEDTLS_ECDH_C
+
+config MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
+	bool "ECDHE-ECDSA based ciphersuite modes"
+	depends on (MBEDTLS_ECDH_C && MBEDTLS_ECDSA_C) || (PSA_WANT_ALG_ECDH && PSA_WANT_ALG_ECDSA)
+
+config MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
+	bool "ECDH-ECDSA based ciphersuite modes"
+	depends on (MBEDTLS_ECDH_C && MBEDTLS_ECDSA_C) || (PSA_WANT_ALG_ECDH && PSA_WANT_ALG_ECDSA)
+
+config MBEDTLS_ECDSA_DETERMINISTIC
+	bool "Deterministic ECDSA (RFC 6979)"
+
+config MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
+	bool "ECDH-RSA based ciphersuite modes"
+	depends on MBEDTLS_ECDH_C
+
+config MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
+	bool "ECJPAKE based ciphersuite modes"
+	depends on MBEDTLS_ECJPAKE_C
+
+if MBEDTLS_TLS_VERSION_1_3
+
+config MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED
+	bool "TLS 1.3 PSK key exchange mode"
+
+config MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED
+	bool "TLS 1.3 ephemeral key exchange mode"
+
+config MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED
+	bool "TLS 1.3 PSK ephemeral key exchange mode"
+
+endif # MBEDTLS_TLS_VERSION_1_3
+
+config MBEDTLS_HKDF_C
+	bool "HMAC-based Extract-and-Expand Key Derivation Function"
+
+comment "Elliptic curve libraries"
+
+config MBEDTLS_ECDH_C
+	bool "Elliptic curve Diffie-Hellman library"
+	depends on MBEDTLS_ECP_C
+
+config MBEDTLS_ECDSA_C
+	bool "Elliptic curve DSA library"
+	depends on MBEDTLS_ECP_C
+	select MBEDTLS_ASN1_PARSE_C
+
+config MBEDTLS_ECJPAKE_C
+	bool "Elliptic curve J-PAKE library"
+	depends on MBEDTLS_ECP_C
+
+config MBEDTLS_ECP_C
+	bool "Elliptic curve over GF(p) library"
+	default y if UOSCORE || UEDHOC
+
+if MBEDTLS_ECP_C
+
+comment "Supported elliptic curves"
+
+config MBEDTLS_ECP_ALL_ENABLED
+	bool "All available elliptic curves"
+	select MBEDTLS_ECP_DP_SECP192R1_ENABLED
+	select MBEDTLS_ECP_DP_SECP192R1_ENABLED
+	select MBEDTLS_ECP_DP_SECP224R1_ENABLED
+	select MBEDTLS_ECP_DP_SECP256R1_ENABLED
+	select MBEDTLS_ECP_DP_SECP384R1_ENABLED
+	select MBEDTLS_ECP_DP_SECP521R1_ENABLED
+	select MBEDTLS_ECP_DP_SECP192K1_ENABLED
+	select MBEDTLS_ECP_DP_SECP224K1_ENABLED
+	select MBEDTLS_ECP_DP_SECP256K1_ENABLED
+	select MBEDTLS_ECP_DP_BP256R1_ENABLED
+	select MBEDTLS_ECP_DP_BP384R1_ENABLED
+	select MBEDTLS_ECP_DP_BP512R1_ENABLED
+	select MBEDTLS_ECP_DP_CURVE25519_ENABLED
+	select MBEDTLS_ECP_DP_CURVE448_ENABLED
+	select MBEDTLS_ECP_NIST_OPTIM
+
+config MBEDTLS_ECP_DP_SECP192R1_ENABLED
+	bool "SECP192R1 elliptic curve"
+
+config MBEDTLS_ECP_DP_SECP224R1_ENABLED
+	bool "SECP224R1 elliptic curve"
+
+config MBEDTLS_ECP_DP_SECP256R1_ENABLED
+	bool "SECP256R1 elliptic curve"
+	default y if UOSCORE || UEDHOC
+
+config MBEDTLS_ECP_DP_SECP384R1_ENABLED
+	bool "SECP384R1 elliptic curve"
+
+config MBEDTLS_ECP_DP_SECP521R1_ENABLED
+	bool "SECP521R1 elliptic curve"
+
+config MBEDTLS_ECP_DP_SECP192K1_ENABLED
+	bool "SECP192K1 elliptic curve"
+
+config MBEDTLS_ECP_DP_SECP224K1_ENABLED
+	bool "SECP224K1 elliptic curve"
+
+config MBEDTLS_ECP_DP_SECP256K1_ENABLED
+	bool "SECP256K1 elliptic curve"
+
+config MBEDTLS_ECP_DP_BP256R1_ENABLED
+	bool "BP256R1 elliptic curve"
+
+config MBEDTLS_ECP_DP_BP384R1_ENABLED
+	bool "BP384R1 elliptic curve"
+
+config MBEDTLS_ECP_DP_BP512R1_ENABLED
+	bool "BP512R1 elliptic curve"
+
+config MBEDTLS_ECP_DP_CURVE25519_ENABLED
+	bool "CURVE25519 elliptic curve"
+
+config MBEDTLS_ECP_DP_CURVE448_ENABLED
+	bool "CURVE448 elliptic curve"
+
+config MBEDTLS_ECP_NIST_OPTIM
+	bool "NSIT curves optimization"
+
+endif
+
+endif # !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
+
+comment "Supported ciphers and cipher modes"
+
+if !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
+
+config MBEDTLS_CIPHER_ALL_ENABLED
+	bool "All available ciphers and modes"
+	select MBEDTLS_CIPHER_AES_ENABLED
+	select MBEDTLS_CIPHER_CAMELLIA_ENABLED
+	select MBEDTLS_CIPHER_DES_ENABLED
+	select MBEDTLS_CIPHER_CHACHA20_ENABLED
+	select MBEDTLS_CIPHER_CCM_ENABLED
+	select MBEDTLS_CIPHER_GCM_ENABLED
+	select MBEDTLS_CIPHER_MODE_XTS_ENABLED
+	select MBEDTLS_CIPHER_MODE_CBC_ENABLED
+	select MBEDTLS_CIPHER_MODE_CTR_ENABLED
+	select MBEDTLS_CHACHAPOLY_AEAD_ENABLED
+
+config MBEDTLS_SOME_AEAD_CIPHER_ENABLED
+	def_bool y
+	depends on \
+		MBEDTLS_CIPHER_AES_ENABLED || \
+		MBEDTLS_CIPHER_CAMELLIA_ENABLED
+
+config MBEDTLS_SOME_CIPHER_ENABLED
+	def_bool y
+	depends on \
+		MBEDTLS_SOME_AEAD_CIPHER_ENABLED || \
+		MBEDTLS_CIPHER_DES_ENABLED || \
+		MBEDTLS_CIPHER_CHACHA20_ENABLED
+
+config MBEDTLS_CIPHER_AES_ENABLED
+	bool "AES block cipher"
+
+if MBEDTLS_CIPHER_AES_ENABLED
+
+config MBEDTLS_AES_ROM_TABLES
+	bool "Use precomputed AES tables stored in ROM."
+
+config MBEDTLS_AES_FEWER_TABLES
+	bool "Reduce the size of precomputed AES tables by ~6kB"
+	default y
+	depends on MBEDTLS_AES_ROM_TABLES
+	help
+	  Reduce the size of the AES tables at a tradeoff of more
+	  arithmetic operations at runtime. Specifically 4 table
+	  lookups are converted to 1 table lookup, 3 additions
+	  and 6 bit shifts.
+
+config MBEDTLS_CIPHER_MODE_XTS_ENABLED
+	bool "Xor-encrypt-xor with ciphertext stealing mode (XTS) for AES"
+
+endif # MBEDTLS_CIPHER_AES_ENABLED
+
+config MBEDTLS_CIPHER_CAMELLIA_ENABLED
+	bool "Camellia block cipher"
+
+config MBEDTLS_CIPHER_DES_ENABLED
+	bool "DES block cipher"
+
+config MBEDTLS_CIPHER_CHACHA20_ENABLED
+	bool "ChaCha20 stream cipher"
+
+if MBEDTLS_SOME_AEAD_CIPHER_ENABLED
+
+config MBEDTLS_CIPHER_CCM_ENABLED
+	bool "Counter with CBC-MAC (CCM) mode for 128-bit block cipher"
+	default y if UOSCORE || UEDHOC
+
+config MBEDTLS_CIPHER_GCM_ENABLED
+	bool "Galois/Counter Mode (GCM) for symmetric ciphers"
+
+endif # MBEDTLS_SOME_AEAD_CIPHER_ENABLED
+
+if MBEDTLS_SOME_CIPHER_ENABLED
+
+config MBEDTLS_CIPHER_MODE_CBC_ENABLED
+	bool "Cipher Block Chaining mode (CBC) for symmetric ciphers"
+	default y if !NET_L2_OPENTHREAD
+
+config MBEDTLS_CIPHER_MODE_CTR_ENABLED
+	bool "Counter Block Cipher mode (CTR) for symmetric ciphers"
+
+endif # MBEDTLS_SOME_CIPHER_ENABLED
+
+config MBEDTLS_CHACHAPOLY_AEAD_ENABLED
+	bool "ChaCha20-Poly1305 AEAD algorithm"
+	depends on MBEDTLS_CIPHER_CHACHA20_ENABLED && MBEDTLS_POLY1305
+
+config MBEDTLS_CMAC
+	bool "CMAC (Cipher-based Message Authentication Code) mode for block ciphers."
+	depends on MBEDTLS_CIPHER_AES_ENABLED || MBEDTLS_CIPHER_DES_ENABLED
+
+endif # !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
+
+comment "Supported hash algorithms"
+
+if !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
+
+config MBEDTLS_HASH_ALL_ENABLED
+	bool "All available MAC methods"
+	select MBEDTLS_MD5
+	select MBEDTLS_SHA1
+	select MBEDTLS_SHA224
+	select MBEDTLS_SHA256
+	select MBEDTLS_SHA384
+	select MBEDTLS_SHA512
+	select MBEDTLS_POLY1305
+
+config MBEDTLS_MD5
+	bool "MD5 hash algorithm"
+
+config MBEDTLS_SHA1
+	bool "SHA-1 hash algorithm"
+
+config MBEDTLS_SHA224
+	bool "SHA-224 hash algorithm"
+
+config MBEDTLS_SHA256
+	bool "SHA-256 hash algorithm"
+	default y
+
+config MBEDTLS_SHA256_SMALLER
+	bool "Smaller SHA-256 implementation"
+	depends on MBEDTLS_SHA256
+	default y
+	help
+	  Enable an implementation of SHA-256 that has a
+	  smaller ROM footprint but also lower performance.
+
+config MBEDTLS_SHA384
+	bool "SHA-384 hash algorithm"
+
+config MBEDTLS_SHA512
+	bool "SHA-512 hash algorithm"
+
+config MBEDTLS_POLY1305
+	bool "Poly1305 hash family"
+
+endif # !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
+
+endmenu
+
+comment "Random number generators"
+
+if !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
+
+config MBEDTLS_CTR_DRBG_ENABLED
+	bool "CTR_DRBG AES-256-based random generator"
+	depends on MBEDTLS_CIPHER_AES_ENABLED
+	default y
+
+config MBEDTLS_HMAC_DRBG_ENABLED
+	bool "HMAC_DRBG random generator"
+	select MBEDTLS_MD
+
+endif # !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
+
+comment "Other configurations"
+
+config MBEDTLS_CIPHER
+	bool "generic cipher layer."
+	default y if PSA_WANT_ALG_CMAC
+
+if !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
+
+config MBEDTLS_MD
+	bool "generic message digest layer."
+	default y if UOSCORE || UEDHOC
+
+endif # !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
+
+config MBEDTLS_ASN1_PARSE_C
+	bool "Support for ASN1 parser functions"
+
+config MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
+	bool "Remove usage of standard libc functions"
+	help
+	  This prevents Mbed TLS from linking against the following standard functions
+	  from libc: `snprintf`, `vsnprintf`, `printf`, `fprintf`, `calloc`, `free`, `setbuf`, `exit`
+	  and `time`. By default Mbed TLS will use stub functions for all these functions.
+	  These stubs are just meant to return successfully, but they don't implement
+	  the required functionality.
+	  Users can individually override each of these stubs by calling
+	  `mbedtls_platform_set_xxx()` to set the their implementation of `xxx()` function
+	  at runtime.
+
+if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
+
+config MBEDTLS_PLATFORM_SNPRINTF_ALT
+	bool "Allow setting custom snprintf at run-time"
+	help
+	  Allow setting a custom `snprintf()` function with `mbedtls_platform_set_snprintf()`.
+	  Include `mbedtls/platform.h` for the prototype of this function.
+
+endif # MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
+
+config MBEDTLS_PEM_CERTIFICATE_FORMAT
+	bool "Support for PEM certificate format"
+	help
+	  By default only DER (binary) format of certificates is supported. Enable
+	  this option to enable support for PEM format.
+
+config MBEDTLS_HAVE_ASM
+	bool "Use of assembly code"
+	default y if !ARM
+	help
+	  Enable use of assembly code in mbedTLS. This improves the performances
+	  of asymmetric cryptography, however this might have an impact on the
+	  code size.
+
+if !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
+
+config MBEDTLS_ENTROPY_C
+	bool "Mbed TLS entropy accumulator"
+	depends on MBEDTLS_SHA256 || MBEDTLS_SHA384 || MBEDTLS_SHA512
+	help
+	  This module gathers entropy data from enabled entropy sources. It's
+	  mostly used in conjunction with CTR_DRBG or HMAC_DRBG to create
+	  a deterministic random number generator.
+
+endif # !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
+
+config MBEDTLS_ENTROPY_POLL_ZEPHYR
+	bool "Provide entropy data to Mbed TLS through entropy driver or random generator"
+	default y
+	depends on MBEDTLS_ENTROPY_C
+	help
+	  Provide entropy data to the Mbed TLS's entropy module through either
+	  an entropy driver (if available in the system) or a generic random
+	  number generator.
+	  Warning: the latter choice is potentially non secure because it might
+	  end up using weaker/test-only sources (ex: random number generator
+	  built on system timer).
+
+config MBEDTLS_OPENTHREAD_OPTIMIZATIONS_ENABLED
+	bool "MbedTLS optimizations for OpenThread"
+	depends on NET_L2_OPENTHREAD
+	default y if !NET_SOCKETS_SOCKOPT_TLS
+	help
+	  Enable some OpenThread specific mbedTLS optimizations that allows to
+	  save some RAM/ROM when OpenThread is used. Note, that when application
+	  aims to use other mbedTLS services on top of OpenThread (e.g. secure
+	  sockets), it's advised to disable this option.
+
+config MBEDTLS_USER_CONFIG_ENABLE
+	bool "User mbedTLS config file"
+	help
+	  Enable user mbedTLS config file that will be included at the end of
+	  the generic config file.
+
+config MBEDTLS_USER_CONFIG_FILE
+	string "User configuration file for mbed TLS" if MBEDTLS_USER_CONFIG_ENABLE
+	help
+	  User config file that can contain mbedTLS configs that were not
+	  covered by the generic config file.
+
+config MBEDTLS_SERVER_NAME_INDICATION
+	bool "Support for RFC 6066 server name indication (SNI) in SSL"
+	help
+	  Enable this to support RFC 6066 server name indication (SNI) in SSL.
+	  This requires that MBEDTLS_X509_CRT_PARSE_C is also set.
+
+config MBEDTLS_PK_WRITE_C
+	bool "The generic public (asymmetric) key writer"
+	help
+	  Enable generic public key write functions.
+
+config MBEDTLS_HAVE_TIME_DATE
+	bool "Date/time validation in mbed TLS"
+	help
+	  System has time.h, time(), and an implementation for gmtime_r().
+	  There also need to be a valid time source in the system, as mbedTLS
+	  expects a valid date/time for certificate validation."
+
+config MBEDTLS_PKCS5_C
+	bool "Password-based encryption functions"
+	select MBEDTLS_MD
+	help
+	  Enable PKCS5 functions
+
+config MBEDTLS_SSL_CACHE_C
+	bool "SSL session cache support"
+	help
+	  "This option enables simple SSL cache implementation (server side)."
+
+if MBEDTLS_SSL_CACHE_C
+
+config MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT
+	int "Default timeout for SSL cache entires"
+	default 86400
+
+config MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES
+	int "Maximum number of SSL cache entires"
+	default 5
+
+endif # MBEDTLS_SSL_CACHE_C
+
+config MBEDTLS_SSL_EXTENDED_MASTER_SECRET
+	bool "(D)TLS Extended Master Secret extension"
+	depends on MBEDTLS_TLS_VERSION_1_2
+	help
+	  Enable support for the (D)TLS Extended Master Secret extension
+	  which ensures that master secrets are different for every
+	  connection and every session.
+
+choice MBEDTLS_PSA_CRYPTO_RNG_SOURCE
+	prompt "Select random source for built-in PSA crypto"
+	depends on MBEDTLS_PSA_CRYPTO_C
+	# The only way to check if there is any entropy driver available on the
+	# platform is to check if the "zephyr,entropy" chosen property exists.
+	# CONFIG_CSPRNG_ENABLED cannot be used for this because it gets enabled by
+	# entropy drivers but these are gated by CONFIG_ENTROPY_GENERATOR which
+	# is disabled by default.
+	default MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG if CSPRNG_AVAILABLE
+	default MBEDTLS_PSA_CRYPTO_LEGACY_RNG
+
+config MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG
+	bool "Use a cryptographically secure driver as random source"
+	select ENTROPY_GENERATOR
+	help
+	  Use a cryptographically secure random generator to provide random data
+	  instead of legacy Mbed TLS modules. This has a smaller footprint
+	  than its legacy counterpart MBEDTLS_PSA_CRYPTO_LEGACY_RNG, but it
+	  requires a cryptographically secure random number generator (CSPRNG)
+	  to be available in the system. If no CSPRNG is available:
+	  - there is no fallback to weak entropy random generators.
+	  - the initialization of PSA crypto will fail and none of its API
+	    will be available.
+
+config MBEDTLS_PSA_CRYPTO_LEGACY_RNG
+	bool "Use legacy modules to generate random data"
+	select MBEDTLS_ENTROPY_C
+	select MBEDTLS_HMAC_DRBG_ENABLED if !MBEDTLS_CTR_DRBG_ENABLED
+	# If there is any entropy driver in the system, then the choice would be
+	# CONFIG_MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG. If we fall here, then the only
+	# way to get some random data is to enable CONFIG_TEST_RANDOM_GENERATOR.
+	select TEST_RANDOM_GENERATOR
+	help
+	  Use legacy Mbed TLS modules to generate random data. In this
+	  configuration the entropy module is used to gather some data and then
+	  either ctr_drbg or hmac_drbg are applied on top of it to improve
+	  the randomness.
+	  Security level in this case really depends on the type of entropy
+	  sources which are enabled in the system: if weak entropy sources are
+	  used, then the generated data will only be pseudo random. Strong
+	  entropy sources are strongly recommended (if possible) to have real
+	  random data.
+	  Another difference betwen this implementation and the
+	  MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG counterpart is the memory footprint:
+	  this implementation brings in legacy modules which are not required
+	  in the "external" version, so the footprint is larger.
+
+endchoice
+
+config MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG_ALLOW_NON_CSPRNG
+	bool "Allow non cryptographically secure random sources (for test only!)"
+	depends on MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG
+	help
+	  MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG is by default limited to rely only
+	  on cryptographically secure random number generators. However, only
+	  for test purposes, it might be useful to enable external random
+	  number generation, but have it using weak random sources (non
+	  cryptographically secure).
+	  Warning: this is meant to be enabled only for tests, not in production
+	  as the generated values are not cryptographically secure!
+
+config MBEDTLS_PSA_CRYPTO_C
+	bool "Platform Security Architecture cryptography API"
+	depends on !BUILD_WITH_TFM
+	default y if UOSCORE || UEDHOC
+
+config MBEDTLS_USE_PSA_CRYPTO
+	bool "Use PSA APIs instead of legacy MbedTLS when possible"
+	default y if MBEDTLS_PSA_CRYPTO_CLIENT
+	help
+	  Use PSA APIs instead of legacy MbedTLS functions in TLS/DTLS and other
+	  "intermediate" modules such as PK, MD and Cipher.
+
+config MBEDTLS_PSA_CRYPTO_CLIENT
+	def_bool y
+	depends on BUILD_WITH_TFM || MBEDTLS_PSA_CRYPTO_C
+	select PSA_CRYPTO_CLIENT
+
+config MBEDTLS_LMS
+	bool "Support LMS signature schemes"
+	depends on MBEDTLS_PSA_CRYPTO_CLIENT
+	depends on MBEDTLS_SHA256
+	select PSA_WANT_ALG_SHA_256
+
+if MBEDTLS_PSA_CRYPTO_C
+
+config MBEDTLS_PSA_P256M_DRIVER_ENABLED
+	bool "P256-M driver"
+	imply PSA_WANT_ALG_SHA_256
+	help
+	  Enable support for the optimized sofware implementation of the secp256r1
+	  curve through the standard PSA API.
+
+config MBEDTLS_PSA_P256M_DRIVER_RAW
+	bool "Access p256-m driver directly (without PSA interface)"
+	depends on MBEDTLS_PSA_P256M_DRIVER_ENABLED
+	help
+	  Allow direct access to the p256-m driver interface.
+	  Warning: Usage of this Kconfig option is prohibited in Zephyr's codebase.
+	           Users can enable it in case of very memory-constrained devices, but be aware that the p256-m interface is absolutely not guaranted to remain stable over time.
+
+config MBEDTLS_PSA_CRYPTO_STORAGE_C
+	bool
+
+config MBEDTLS_PSA_STATIC_KEY_SLOTS
+	bool "Use statically allocated key buffers to store key material"
+	default y if !MBEDTLS_ENABLE_HEAP
+	help
+	  By default Mbed TLS's PSA Crypto core uses heap memory to store the
+	  key material for each key slot. This might impose an undesired
+	  requirement to support heap memory and its management code, affecting
+	  RAM and ROM footprints at the same time.
+	  Enabling this symbol causes Mbed TLS to pre-allocate all the key slot
+	  buffers that are used to store the key material at build time, thus
+	  removing the need for heap memory. Each buffer will be sized to
+	  contain the largest asymmetric/symmetric key type enabled in the build
+	  through PSA_WANT symbols.
+
+config MBEDTLS_PSA_KEY_SLOT_COUNT
+	int "Number of key slots in PSA Crypto core"
+	default 16
+	help
+	  Set the number of key slots that are available in the PSA Crypto core.
+	  Be aware that each slot, even if unused, increases RAM consumption
+	  by ~40 bytes plus:
+	  * the length of the largest asymmetric/symmetric key type enabled in
+	    the build through PSA_WANT symbols, if MBEDTLS_PSA_STATIC_KEY_SLOTS
+	    is set. (This is all defined statically at build time).
+	  * the heap-allocated memory to store the key material of a given slot,
+	    if it is used and MBEDTLS_PSA_STATIC_KEY_SLOTS is not set.
+
+endif # MBEDTLS_PSA_CRYPTO_C
+
+config MBEDTLS_SSL_DTLS_CONNECTION_ID
+	bool "DTLS Connection ID extension"
+	depends on MBEDTLS_DTLS
+	help
+	  Enable support for the DTLS Connection ID extension
+	  which allows to identify DTLS connections across changes
+	  in the underlying transport.
+
+
+config MBEDTLS_NIST_KW_C
+	bool "NIST key wrap"
+	depends on MBEDTLS_CIPHER_AES_ENABLED
+	help
+	  Key Wrapping mode for 128-bit block ciphers,
+	  as defined in NIST SP 800-38F.
+
+config MBEDTLS_DHM_C
+	bool "Diffie-Hellman-Merkle mode"
+	help
+	  Used by the following key exchanges,
+	  DHE-RSA, DHE-PSK
+
+config MBEDTLS_X509_CRL_PARSE_C
+	bool "X.509 CRL parsing"
+	help
+	  Used by X.509 CRL parsing
+
+config MBEDTLS_X509_CSR_WRITE_C
+	bool "X.509 Certificate Signing Requests writing"
+	help
+	  For X.509 certificate request writing.
+
+config MBEDTLS_X509_CSR_PARSE_C
+	bool "X.509 Certificate Signing Request parsing"
+	help
+	  For reading X.509 certificate request.
+
+config MBEDTLS_X509_CRT_WRITE_C
+	bool "X.509 certificate creation"
+
+endmenu
diff --git a/modules/mbedtls/Kconfig.tls-generic b/modules/mbedtls/Kconfig.tls-generic
deleted file mode 100644
index 9214d3878ca..00000000000
--- a/modules/mbedtls/Kconfig.tls-generic
+++ /dev/null
@@ -1,714 +0,0 @@
-# TLS/DTLS related options
-
-# Copyright (c) 2018 Intel Corporation
-# Copyright (c) 2018 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-menu "Mbed TLS configuration"
-	depends on MBEDTLS_BUILTIN && MBEDTLS_CFG_FILE = "config-tls-generic.h"
-
-if !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
-
-menu "TLS"
-
-config MBEDTLS_TLS_VERSION_1_2
-	bool "Support for TLS 1.2 (DTLS 1.2)"
-	select MBEDTLS_CIPHER
-	select MBEDTLS_MD
-
-if MBEDTLS_TLS_VERSION_1_2
-
-config MBEDTLS_DTLS
-	bool "Support for DTLS"
-
-endif # MBEDTLS_TLS_VERSION_1_2
-
-config MBEDTLS_TLS_VERSION_1_3
-	bool "Support for TLS 1.3"
-
-if MBEDTLS_TLS_VERSION_1_3
-
-config MBEDTLS_TLS_SESSION_TICKETS
-	bool "Support for RFC 5077 session tickets in TLS 1.3"
-
-endif # MBEDTLS_TLS_VERSION_1_3
-
-if MBEDTLS_TLS_VERSION_1_2 || MBEDTLS_TLS_VERSION_1_3
-
-config MBEDTLS_SSL_ALPN
-	bool "Support for setting the supported Application Layer Protocols"
-
-endif # MBEDTLS_TLS_VERSION_1_2 || MBEDTLS_TLS_VERSION_1_3
-
-endmenu # TLS
-
-endif # !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
-
-menu "Ciphersuite configuration"
-
-comment "Supported key exchange modes"
-
-if !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
-
-config MBEDTLS_KEY_EXCHANGE_ALL_ENABLED
-	bool "All available ciphersuite modes"
-	select MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
-	select MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
-	select MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
-	select MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
-	select MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
-	select MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
-	select MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
-	select MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
-	select MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
-	select MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
-	select MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
-
-config MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
-	bool "PSK based ciphersuite modes"
-
-config MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
-	bool "DHE-PSK based ciphersuite modes"
-
-config MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
-	bool "ECDHE-PSK based ciphersuite modes"
-	depends on MBEDTLS_ECDH_C
-
-config MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
-	bool "RSA-PSK based ciphersuite modes"
-
-endif # !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
-
-config MBEDTLS_PSK_MAX_LEN
-	int "Max size of TLS pre-shared keys"
-	default 32
-	help
-	  Max size of TLS pre-shared keys, in bytes. It has no effect if no
-	  PSK key exchange is used.
-
-if !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
-
-config MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
-	bool "RSA-only based ciphersuite modes"
-	default y if UOSCORE || UEDHOC
-	select MBEDTLS_MD
-	select PSA_WANT_KEY_TYPE_RSA_PUBLIC_KEY if PSA_CRYPTO_CLIENT
-	select PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_IMPORT if PSA_CRYPTO_CLIENT
-	select PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_EXPORT if PSA_CRYPTO_CLIENT
-	select PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_GENERATE if PSA_CRYPTO_CLIENT
-	select PSA_WANT_KEY_TYPE_RSA_KEY_PAIR_DERIVE if PSA_CRYPTO_CLIENT
-
-config MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
-	bool "DHE-RSA based ciphersuite modes"
-
-config MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
-	bool "ECDHE-RSA based ciphersuite modes"
-	depends on MBEDTLS_ECDH_C
-
-config MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
-	bool "ECDHE-ECDSA based ciphersuite modes"
-	depends on MBEDTLS_ECDH_C && MBEDTLS_ECDSA_C || (PSA_WANT_ALG_ECDH && PSA_WANT_ALG_ECDSA)
-
-config MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
-	bool "ECDH-ECDSA based ciphersuite modes"
-	depends on (MBEDTLS_ECDH_C && MBEDTLS_ECDSA_C) || (PSA_WANT_ALG_ECDH && PSA_WANT_ALG_ECDSA)
-
-config MBEDTLS_ECDSA_DETERMINISTIC
-	bool "Deterministic ECDSA (RFC 6979)"
-
-config MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
-	bool "ECDH-RSA based ciphersuite modes"
-	depends on MBEDTLS_ECDH_C
-
-config MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
-	bool "ECJPAKE based ciphersuite modes"
-	depends on MBEDTLS_ECJPAKE_C
-
-if MBEDTLS_TLS_VERSION_1_3
-
-config MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED
-	bool "TLS 1.3 PSK key exchange mode"
-
-config MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED
-	bool "TLS 1.3 ephemeral key exchange mode"
-
-config MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED
-	bool "TLS 1.3 PSK ephemeral key exchange mode"
-
-endif # MBEDTLS_TLS_VERSION_1_3
-
-config MBEDTLS_HKDF_C
-	bool "HMAC-based Extract-and-Expand Key Derivation Function"
-
-comment "Elliptic curve libraries"
-
-config MBEDTLS_ECDH_C
-	bool "Elliptic curve Diffie-Hellman library"
-	depends on MBEDTLS_ECP_C
-
-config MBEDTLS_ECDSA_C
-	bool "Elliptic curve DSA library"
-	depends on MBEDTLS_ECP_C
-	select MBEDTLS_ASN1_PARSE_C
-
-config MBEDTLS_ECJPAKE_C
-	bool "Elliptic curve J-PAKE library"
-	depends on MBEDTLS_ECP_C
-
-config MBEDTLS_ECP_C
-	bool "Elliptic curve over GF(p) library"
-	default y if UOSCORE || UEDHOC
-
-if MBEDTLS_ECP_C
-
-comment "Supported elliptic curves"
-
-config MBEDTLS_ECP_ALL_ENABLED
-	bool "All available elliptic curves"
-	select MBEDTLS_ECP_DP_SECP192R1_ENABLED
-	select MBEDTLS_ECP_DP_SECP192R1_ENABLED
-	select MBEDTLS_ECP_DP_SECP224R1_ENABLED
-	select MBEDTLS_ECP_DP_SECP256R1_ENABLED
-	select MBEDTLS_ECP_DP_SECP384R1_ENABLED
-	select MBEDTLS_ECP_DP_SECP521R1_ENABLED
-	select MBEDTLS_ECP_DP_SECP192K1_ENABLED
-	select MBEDTLS_ECP_DP_SECP224K1_ENABLED
-	select MBEDTLS_ECP_DP_SECP256K1_ENABLED
-	select MBEDTLS_ECP_DP_BP256R1_ENABLED
-	select MBEDTLS_ECP_DP_BP384R1_ENABLED
-	select MBEDTLS_ECP_DP_BP512R1_ENABLED
-	select MBEDTLS_ECP_DP_CURVE25519_ENABLED
-	select MBEDTLS_ECP_DP_CURVE448_ENABLED
-	select MBEDTLS_ECP_NIST_OPTIM
-
-config MBEDTLS_ECP_DP_SECP192R1_ENABLED
-	bool "SECP192R1 elliptic curve"
-
-config MBEDTLS_ECP_DP_SECP224R1_ENABLED
-	bool "SECP224R1 elliptic curve"
-
-config MBEDTLS_ECP_DP_SECP256R1_ENABLED
-	bool "SECP256R1 elliptic curve"
-	default y if UOSCORE || UEDHOC
-
-config MBEDTLS_ECP_DP_SECP384R1_ENABLED
-	bool "SECP384R1 elliptic curve"
-
-config MBEDTLS_ECP_DP_SECP521R1_ENABLED
-	bool "SECP521R1 elliptic curve"
-
-config MBEDTLS_ECP_DP_SECP192K1_ENABLED
-	bool "SECP192K1 elliptic curve"
-
-config MBEDTLS_ECP_DP_SECP224K1_ENABLED
-	bool "SECP224K1 elliptic curve"
-
-config MBEDTLS_ECP_DP_SECP256K1_ENABLED
-	bool "SECP256K1 elliptic curve"
-
-config MBEDTLS_ECP_DP_BP256R1_ENABLED
-	bool "BP256R1 elliptic curve"
-
-config MBEDTLS_ECP_DP_BP384R1_ENABLED
-	bool "BP384R1 elliptic curve"
-
-config MBEDTLS_ECP_DP_BP512R1_ENABLED
-	bool "BP512R1 elliptic curve"
-
-config MBEDTLS_ECP_DP_CURVE25519_ENABLED
-	bool "CURVE25519 elliptic curve"
-
-config MBEDTLS_ECP_DP_CURVE448_ENABLED
-	bool "CURVE448 elliptic curve"
-
-config MBEDTLS_ECP_NIST_OPTIM
-	bool "NSIT curves optimization"
-
-endif
-
-endif # !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
-
-comment "Supported ciphers and cipher modes"
-
-if !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
-
-config MBEDTLS_CIPHER_ALL_ENABLED
-	bool "All available ciphers and modes"
-	select MBEDTLS_CIPHER_AES_ENABLED
-	select MBEDTLS_CIPHER_CAMELLIA_ENABLED
-	select MBEDTLS_CIPHER_DES_ENABLED
-	select MBEDTLS_CIPHER_CHACHA20_ENABLED
-	select MBEDTLS_CIPHER_CCM_ENABLED
-	select MBEDTLS_CIPHER_GCM_ENABLED
-	select MBEDTLS_CIPHER_MODE_XTS_ENABLED
-	select MBEDTLS_CIPHER_MODE_CBC_ENABLED
-	select MBEDTLS_CIPHER_MODE_CTR_ENABLED
-	select MBEDTLS_CHACHAPOLY_AEAD_ENABLED
-
-config MBEDTLS_SOME_AEAD_CIPHER_ENABLED
-	bool
-	default y
-	depends on \
-		MBEDTLS_CIPHER_AES_ENABLED || \
-		MBEDTLS_CIPHER_CAMELLIA_ENABLED
-
-config MBEDTLS_SOME_CIPHER_ENABLED
-	bool
-	default y
-	depends on \
-		MBEDTLS_SOME_AEAD_CIPHER_ENABLED || \
-		MBEDTLS_CIPHER_DES_ENABLED || \
-		MBEDTLS_CIPHER_CHACHA20_ENABLED
-
-config MBEDTLS_CIPHER_AES_ENABLED
-	bool "AES block cipher"
-
-if MBEDTLS_CIPHER_AES_ENABLED
-
-config MBEDTLS_AES_ROM_TABLES
-	bool "Use precomputed AES tables stored in ROM."
-
-config MBEDTLS_AES_FEWER_TABLES
-	bool "Reduce the size of precomputed AES tables by ~6kB"
-	default y
-	depends on MBEDTLS_AES_ROM_TABLES
-	help
-	  Reduce the size of the AES tables at a tradeoff of more
-	  arithmetic operations at runtime. Specifically 4 table
-	  lookups are converted to 1 table lookup, 3 additions
-	  and 6 bit shifts.
-
-config MBEDTLS_CIPHER_MODE_XTS_ENABLED
-	bool "Xor-encrypt-xor with ciphertext stealing mode (XTS) for AES"
-
-endif # MBEDTLS_CIPHER_AES_ENABLED
-
-config MBEDTLS_CIPHER_CAMELLIA_ENABLED
-	bool "Camellia block cipher"
-
-config MBEDTLS_CIPHER_DES_ENABLED
-	bool "DES block cipher"
-
-config MBEDTLS_CIPHER_CHACHA20_ENABLED
-	bool "ChaCha20 stream cipher"
-
-if MBEDTLS_SOME_AEAD_CIPHER_ENABLED
-
-config MBEDTLS_CIPHER_CCM_ENABLED
-	bool "Counter with CBC-MAC (CCM) mode for 128-bit block cipher"
-	default y if UOSCORE || UEDHOC
-
-config MBEDTLS_CIPHER_GCM_ENABLED
-	bool "Galois/Counter Mode (GCM) for symmetric ciphers"
-
-endif # MBEDTLS_SOME_AEAD_CIPHER_ENABLED
-
-if MBEDTLS_SOME_CIPHER_ENABLED
-
-config MBEDTLS_CIPHER_MODE_CBC_ENABLED
-	bool "Cipher Block Chaining mode (CBC) for symmetric ciphers"
-	default y if !NET_L2_OPENTHREAD
-
-config MBEDTLS_CIPHER_MODE_CTR_ENABLED
-	bool "Counter Block Cipher mode (CTR) for symmetric ciphers"
-
-endif # MBEDTLS_SOME_CIPHER_ENABLED
-
-config MBEDTLS_CHACHAPOLY_AEAD_ENABLED
-	bool "ChaCha20-Poly1305 AEAD algorithm"
-	depends on MBEDTLS_CIPHER_CHACHA20_ENABLED && MBEDTLS_POLY1305
-
-config MBEDTLS_CMAC
-	bool "CMAC (Cipher-based Message Authentication Code) mode for block ciphers."
-	depends on MBEDTLS_CIPHER_AES_ENABLED || MBEDTLS_CIPHER_DES_ENABLED
-
-endif # !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
-
-comment "Supported hash algorithms"
-
-if !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
-
-config MBEDTLS_HASH_ALL_ENABLED
-	bool "All available MAC methods"
-	select MBEDTLS_MD5
-	select MBEDTLS_SHA1
-	select MBEDTLS_SHA224
-	select MBEDTLS_SHA256
-	select MBEDTLS_SHA384
-	select MBEDTLS_SHA512
-	select MBEDTLS_POLY1305
-
-config MBEDTLS_MD5
-	bool "MD5 hash algorithm"
-
-config MBEDTLS_SHA1
-	bool "SHA-1 hash algorithm"
-
-config MBEDTLS_SHA224
-	bool "SHA-224 hash algorithm"
-
-config MBEDTLS_SHA256
-	bool "SHA-256 hash algorithm"
-	default y
-
-config MBEDTLS_SHA256_SMALLER
-	bool "Smaller SHA-256 implementation"
-	depends on MBEDTLS_SHA256
-	default y
-	help
-	  Enable an implementation of SHA-256 that has a
-	  smaller ROM footprint but also lower performance.
-
-config MBEDTLS_SHA384
-	bool "SHA-384 hash algorithm"
-
-config MBEDTLS_SHA512
-	bool "SHA-512 hash algorithm"
-
-config MBEDTLS_POLY1305
-	bool "Poly1305 hash family"
-
-endif # !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
-
-endmenu
-
-comment "Random number generators"
-
-if !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
-
-config MBEDTLS_CTR_DRBG_ENABLED
-	bool "CTR_DRBG AES-256-based random generator"
-	depends on MBEDTLS_CIPHER_AES_ENABLED
-	default y
-
-config MBEDTLS_HMAC_DRBG_ENABLED
-	bool "HMAC_DRBG random generator"
-	select MBEDTLS_MD
-
-endif # !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
-
-comment "Other configurations"
-
-config MBEDTLS_CIPHER
-	bool "generic cipher layer."
-	default y if PSA_WANT_ALG_CMAC
-
-if !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
-
-config MBEDTLS_MD
-	bool "generic message digest layer."
-
-endif # !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
-
-config MBEDTLS_GENPRIME_ENABLED
-	bool "prime-number generation code."
-
-config MBEDTLS_ASN1_PARSE_C
-	bool "Support for ASN1 parser functions"
-
-config MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
-	bool "Remove usage of standard libc functions"
-	help
-	  This prevents Mbed TLS from linking against the following standard functions
-	  from libc: `snprintf`, `vsnprintf`, `printf`, `fprintf`, `calloc`, `free`, `setbuf`, `exit`
-	  and `time`. By default Mbed TLS will use stub functions for all these functions.
-	  These stubs are just meant to return successfully, but they don't implement
-	  the required functionality.
-	  Users can individually override each of these stubs by calling
-	  `mbedtls_platform_set_xxx()` to set the their implementation of `xxx()` function
-	  at runtime.
-
-if MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
-
-config MBEDTLS_PLATFORM_SNPRINTF_ALT
-	bool "Allow setting custom snprintf at run-time"
-	help
-	  Allow setting a custom `snprintf()` function with `mbedtls_platform_set_snprintf()`.
-	  Include `mbedtls/platform.h` for the prototype of this function.
-
-endif # MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
-
-config MBEDTLS_PEM_CERTIFICATE_FORMAT
-	bool "Support for PEM certificate format"
-	help
-	  By default only DER (binary) format of certificates is supported. Enable
-	  this option to enable support for PEM format.
-
-config MBEDTLS_HAVE_ASM
-	bool "Use of assembly code"
-	default y if !ARM
-	help
-	  Enable use of assembly code in mbedTLS. This improves the performances
-	  of asymmetric cryptography, however this might have an impact on the
-	  code size.
-
-if !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
-
-config MBEDTLS_ENTROPY_C
-	bool "Mbed TLS entropy accumulator"
-	depends on MBEDTLS_SHA256 || MBEDTLS_SHA384 || MBEDTLS_SHA512
-	help
-	  This module gathers entropy data from enabled entropy sources. It's
-	  mostly used in conjunction with CTR_DRBG or HMAC_DRBG to create
-	  a deterministic random number generator.
-
-endif # !(NRF_SECURITY || NORDIC_SECURITY_BACKEND)
-
-config MBEDTLS_ENTROPY_POLL_ZEPHYR
-	bool "Provide entropy data to Mbed TLS through entropy driver or random generator"
-	default y
-	depends on MBEDTLS_ENTROPY_C
-	help
-	  Provide entropy data to the Mbed TLS's entropy module through either
-	  an entropy driver (if available in the system) or a generic random
-	  number generator.
-	  Warning: the latter choice is potentially non secure because it might
-	  end up using weaker/test-only sources (ex: random number generator
-	  built on system timer).
-
-config MBEDTLS_OPENTHREAD_OPTIMIZATIONS_ENABLED
-	bool "MbedTLS optimizations for OpenThread"
-	depends on NET_L2_OPENTHREAD
-	default y if !NET_SOCKETS_SOCKOPT_TLS
-	help
-	  Enable some OpenThread specific mbedTLS optimizations that allows to
-	  save some RAM/ROM when OpenThread is used. Note, that when application
-	  aims to use other mbedTLS services on top of OpenThread (e.g. secure
-	  sockets), it's advised to disable this option.
-
-config MBEDTLS_USER_CONFIG_ENABLE
-	bool "User mbedTLS config file"
-	help
-	  Enable user mbedTLS config file that will be included at the end of
-	  the generic config file.
-
-config MBEDTLS_USER_CONFIG_FILE
-	string "User configuration file for mbed TLS" if MBEDTLS_USER_CONFIG_ENABLE
-	help
-	  User config file that can contain mbedTLS configs that were not
-	  covered by the generic config file.
-
-config MBEDTLS_SERVER_NAME_INDICATION
-	bool "Support for RFC 6066 server name indication (SNI) in SSL"
-	help
-	  Enable this to support RFC 6066 server name indication (SNI) in SSL.
-	  This requires that MBEDTLS_X509_CRT_PARSE_C is also set.
-
-config MBEDTLS_PK_WRITE_C
-	bool "The generic public (asymmetric) key writer"
-	help
-	  Enable generic public key write functions.
-
-config MBEDTLS_HAVE_TIME_DATE
-	bool "Date/time validation in mbed TLS"
-	help
-	  System has time.h, time(), and an implementation for gmtime_r().
-	  There also need to be a valid time source in the system, as mbedTLS
-	  expects a valid date/time for certificate validation."
-
-config MBEDTLS_PKCS5_C
-	bool "Password-based encryption functions"
-	select MBEDTLS_MD
-	help
-	  Enable PKCS5 functions
-
-config MBEDTLS_SSL_CACHE_C
-	bool "SSL session cache support"
-	help
-	  "This option enables simple SSL cache implementation (server side)."
-
-if MBEDTLS_SSL_CACHE_C
-
-config MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT
-	int "Default timeout for SSL cache entires"
-	default 86400
-
-config MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES
-	int "Maximum number of SSL cache entires"
-	default 5
-
-endif # MBEDTLS_SSL_CACHE_C
-
-config MBEDTLS_SSL_EXTENDED_MASTER_SECRET
-	bool "(D)TLS Extended Master Secret extension"
-	depends on MBEDTLS_TLS_VERSION_1_2
-	help
-	  Enable support for the (D)TLS Extended Master Secret extension
-	  which ensures that master secrets are different for every
-	  connection and every session.
-
-choice MBEDTLS_PSA_CRYPTO_RNG_SOURCE
-	prompt "Select random source for built-in PSA crypto"
-	depends on MBEDTLS_PSA_CRYPTO_C
-	# The only way to check if there is any entropy driver available on the
-	# platform is to check if the "zephyr,entropy" chosen property exists.
-	# CONFIG_CSPRNG_ENABLED cannot be used for this because it gets enabled by
-	# entropy drivers but these are gated by CONFIG_ENTROPY_GENERATOR which
-	# is disabled by default.
-	default MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG if CSPRNG_AVAILABLE
-	default MBEDTLS_PSA_CRYPTO_LEGACY_RNG
-
-config MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG
-	bool "Use a cryptographically secure driver as random source"
-	select ENTROPY_GENERATOR
-	help
-	  Use a cryptographically secure random generator to provide random data
-	  instead of legacy Mbed TLS modules. This has a smaller footprint
-	  than its legacy counterpart MBEDTLS_PSA_CRYPTO_LEGACY_RNG, but it
-	  requires a cryptographically secure random number generator (CSPRNG)
-	  to be available in the system. If no CSPRNG is available:
-	  - there is no fallback to weak entropy random generators.
-	  - the initialization of PSA crypto will fail and none of its API
-	    will be available.
-
-config MBEDTLS_PSA_CRYPTO_LEGACY_RNG
-	bool "Use legacy modules to generate random data"
-	select MBEDTLS_ENTROPY_C
-	select MBEDTLS_HMAC_DRBG_ENABLED if !MBEDTLS_CTR_DRBG_ENABLED
-	# If there is any entropy driver in the system, then the choice would be
-	# CONFIG_MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG. If we fall here, then the only
-	# way to get some random data is to enable CONFIG_TEST_RANDOM_GENERATOR.
-	select TEST_RANDOM_GENERATOR
-	help
-	  Use legacy Mbed TLS modules to generate random data. In this
-	  configuration the entropy module is used to gather some data and then
-	  either ctr_drbg or hmac_drbg are applied on top of it to improve
-	  the randomness.
-	  Security level in this case really depends on the type of entropy
-	  sources which are enabled in the system: if weak entropy sources are
-	  used, then the generated data will only be pseudo random. Strong
-	  entropy sources are strongly recommended (if possible) to have real
-	  random data.
-	  Another difference betwen this implementation and the
-	  MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG counterpart is the memory footprint:
-	  this implementation brings in legacy modules which are not required
-	  in the "external" version, so the footprint is larger.
-
-endchoice
-
-config MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG_ALLOW_NON_CSPRNG
-	bool "Allow non cryptographically secure random sources (for test only!)"
-	depends on MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG
-	help
-	  MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG is by default limited to rely only
-	  on cryptographically secure random number generators. However, only
-	  for test purposes, it might be useful to enable external random
-	  number generation, but have it using weak random sources (non
-	  cryptographically secure).
-	  Warning: this is meant to be enabled only for tests, not in production
-	  as the generated values are not cryptographically secure!
-
-config MBEDTLS_PSA_CRYPTO_C
-	bool "Platform Security Architecture cryptography API"
-	depends on !BUILD_WITH_TFM
-	default y if UOSCORE || UEDHOC
-
-config MBEDTLS_USE_PSA_CRYPTO
-	bool "Use PSA APIs instead of legacy MbedTLS when possible"
-	default y if MBEDTLS_PSA_CRYPTO_CLIENT
-	help
-	  Use PSA APIs instead of legacy MbedTLS functions in TLS/DTLS and other
-	  "intermediate" modules such as PK, MD and Cipher.
-
-config MBEDTLS_PSA_CRYPTO_CLIENT
-	bool
-	default y
-	depends on BUILD_WITH_TFM || MBEDTLS_PSA_CRYPTO_C
-	select PSA_CRYPTO_CLIENT
-
-config MBEDTLS_LMS
-	bool "Support LMS signature schemes"
-	depends on MBEDTLS_PSA_CRYPTO_CLIENT
-	depends on MBEDTLS_SHA256
-	select PSA_WANT_ALG_SHA_256
-
-if MBEDTLS_PSA_CRYPTO_C
-
-config MBEDTLS_PSA_P256M_DRIVER_ENABLED
-	bool "P256-M driver"
-	imply PSA_WANT_ALG_SHA_256
-	help
-	  Enable support for the optimized sofware implementation of the secp256r1
-	  curve through the standard PSA API.
-
-config MBEDTLS_PSA_P256M_DRIVER_RAW
-	bool "Access p256-m driver directly (without PSA interface)"
-	depends on MBEDTLS_PSA_P256M_DRIVER_ENABLED
-	help
-	  Allow direct access to the p256-m driver interface.
-	  Warning: Usage of this Kconfig option is prohibited in Zephyr's codebase.
-	           Users can enable it in case of very memory-constrained devices, but be aware that the p256-m interface is absolutely not guaranted to remain stable over time.
-
-config MBEDTLS_PSA_CRYPTO_STORAGE_C
-	bool
-
-config MBEDTLS_PSA_STATIC_KEY_SLOTS
-	bool "Use statically allocated key buffers to store key material"
-	default y if !MBEDTLS_ENABLE_HEAP
-	help
-	  By default Mbed TLS's PSA Crypto core uses heap memory to store the
-	  key material for each key slot. This might impose an undesired
-	  requirement to support heap memory and its management code, affecting
-	  RAM and ROM footprints at the same time.
-	  Enabling this symbol causes Mbed TLS to pre-allocate all the key slot
-	  buffers that are used to store the key material at build time, thus
-	  removing the need for heap memory. Each buffer will be sized to
-	  contain the largest asymmetric/symmetric key type enabled in the build
-	  through PSA_WANT symbols.
-
-config MBEDTLS_PSA_KEY_SLOT_COUNT
-	int "Number of key slots in PSA Crypto core"
-	default 16
-	help
-	  Set the number of key slots that are available in the PSA Crypto core.
-	  Be aware that each slot, even if unused, increases RAM consumption
-	  by ~40 bytes plus:
-	  * the length of the largest asymmetric/symmetric key type enabled in
-	    the build through PSA_WANT symbols, if MBEDTLS_PSA_STATIC_KEY_SLOTS
-	    is set. (This is all defined statically at build time).
-	  * the heap-allocated memory to store the key material of a given slot,
-	    if it is used and MBEDTLS_PSA_STATIC_KEY_SLOTS is not set.
-
-endif # MBEDTLS_PSA_CRYPTO_C
-
-config MBEDTLS_SSL_DTLS_CONNECTION_ID
-	bool "DTLS Connection ID extension"
-	depends on MBEDTLS_DTLS
-	help
-	  Enable support for the DTLS Connection ID extension
-	  which allows to identify DTLS connections across changes
-	  in the underlying transport.
-
-
-config MBEDTLS_NIST_KW_C
-	bool "NIST key wrap"
-	depends on MBEDTLS_CIPHER_AES_ENABLED
-	help
-	  Key Wrapping mode for 128-bit block ciphers,
-	  as defined in NIST SP 800-38F.
-
-config MBEDTLS_DHM_C
-	bool "Diffie-Hellman-Merkle mode"
-	help
-	  Used by the following key exchanges,
-	  DHE-RSA, DHE-PSK
-
-config MBEDTLS_X509_CRL_PARSE_C
-	bool "X.509 CRL parsing"
-	help
-	  Used by X.509 CRL parsing
-
-config MBEDTLS_X509_CSR_WRITE_C
-	bool "X.509 Certificate Signing Requests writing"
-	help
-	  For X.509 certificate request writing.
-
-config MBEDTLS_X509_CSR_PARSE_C
-	bool "X.509 Certificate Signing Request parsing"
-	help
-	  For reading X.509 certificate request.
-
-config MBEDTLS_X509_CRT_WRITE_C
-	bool "X.509 certificate creation"
-
-endmenu
diff --git a/modules/mbedtls/configs/config-ccm-psk-tls1_2.h b/modules/mbedtls/configs/config-ccm-psk-tls1_2.h
deleted file mode 100644
index 06d71f14545..00000000000
--- a/modules/mbedtls/configs/config-ccm-psk-tls1_2.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/**
- * \file config-ccm-psk-tls1_2.h
- *
- * \brief Minimal configuration for TLS 1.2 with PSK and AES-CCM ciphersuites
- */
-/*
- *  Copyright The Mbed TLS Contributors
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- */
-/*
- * Minimal configuration for TLS 1.2 with PSK and AES-CCM ciphersuites
- * Distinguishing features:
- * - no bignum, no PK, no X509
- * - fully modern and secure (provided the pre-shared keys have high entropy)
- * - very low record overhead with CCM-8
- * - optimized for low RAM usage
- *
- * See README.txt for usage instructions.
- */
-#ifndef MBEDTLS_CONFIG_H
-#define MBEDTLS_CONFIG_H
-
-/* System support */
-//#define MBEDTLS_HAVE_TIME /* Optionally used in Hello messages */
-/* Other MBEDTLS_HAVE_XXX flags irrelevant for this configuration */
-
-/* mbed TLS feature support */
-#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
-#define MBEDTLS_SSL_PROTO_TLS1_2
-
-/* mbed TLS modules */
-#define MBEDTLS_AES_C
-#define MBEDTLS_CCM_C
-#define MBEDTLS_CIPHER_C
-#define MBEDTLS_CTR_DRBG_C
-#define MBEDTLS_ENTROPY_C
-#define MBEDTLS_MD_C
-#define MBEDTLS_NET_C
-#define MBEDTLS_SHA224_C
-#define MBEDTLS_SHA256_C
-#define MBEDTLS_SSL_CLI_C
-#define MBEDTLS_SSL_SRV_C
-#define MBEDTLS_SSL_TLS_C
-
-/* Save RAM at the expense of ROM */
-#define MBEDTLS_AES_ROM_TABLES
-
-/* Save some RAM by adjusting to your exact needs */
-#define MBEDTLS_PSK_MAX_LEN    16 /* 128-bits keys are generally enough */
-
-/*
- * You should adjust this to the exact number of sources you're using: default
- * is the "platform_entropy_poll" source, but you may want to add other ones
- * Minimum is 2 for the entropy test suite.
- */
-#define MBEDTLS_ENTROPY_MAX_SOURCES 2
-
-/*
- * Use only CCM_8 ciphersuites, and
- * save ROM and a few bytes of RAM by specifying our own ciphersuite list
- */
-#define MBEDTLS_SSL_CIPHERSUITES                        \
-        MBEDTLS_TLS_PSK_WITH_AES_256_CCM_8,             \
-        MBEDTLS_TLS_PSK_WITH_AES_128_CCM_8
-
-/*
- * Save RAM at the expense of interoperability: do this only if you control
- * both ends of the connection!  (See comments in "mbedtls/ssl.h".)
- * The optimal size here depends on the typical size of records.
- */
-#define MBEDTLS_SSL_MAX_CONTENT_LEN             1024
-
-#include "mbedtls/check_config.h"
-
-#endif /* MBEDTLS_CONFIG_H */
diff --git a/modules/mbedtls/configs/config-coap.h b/modules/mbedtls/configs/config-coap.h
deleted file mode 100644
index f610eb20bc6..00000000000
--- a/modules/mbedtls/configs/config-coap.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- *  Minimal configuration for DTLS 1.2 with PSK and AES-CCM ciphersuites
- *
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-/*
- * Minimal configuration for TLS 1.2 with PSK and AES-CCM ciphersuites
- * Distinguishing features:
- * - no bignum, no PK, no X509
- * - fully modern and secure (provided the pre-shared keys have high entropy)
- * - very low record overhead with CCM-8
- * - optimized for low RAM usage
- *
- * See README.txt for usage instructions.
- */
-#ifndef MBEDTLS_CONFIG_H
-#define MBEDTLS_CONFIG_H
-
-/* System support */
-#define MBEDTLS_PLATFORM_C
-#define MBEDTLS_PLATFORM_MEMORY
-#define MBEDTLS_MEMORY_BUFFER_ALLOC_C
-#define MBEDTLS_MEMORY_ALIGN_MULTIPLE (sizeof(void *))
-#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
-#define MBEDTLS_PLATFORM_EXIT_ALT
-#define MBEDTLS_NO_PLATFORM_ENTROPY
-#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
-#define MBEDTLS_PLATFORM_PRINTF_ALT
-
-#if defined(CONFIG_MBEDTLS_TEST)
-#define MBEDTLS_SELF_TEST
-#define MBEDTLS_DEBUG_C
-#else
-#define MBEDTLS_ENTROPY_C
-#endif
-
-
-/* mbed TLS feature support */
-#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
-#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
-#define MBEDTLS_SSL_PROTO_TLS1_2
-#define MBEDTLS_SSL_PROTO_DTLS
-#define MBEDTLS_SSL_DTLS_ANTI_REPLAY
-#define MBEDTLS_SSL_DTLS_HELLO_VERIFY
-
-
-/* mbed TLS modules */
-#define MBEDTLS_AES_C
-#define MBEDTLS_CCM_C
-#define MBEDTLS_CIPHER_C
-#define MBEDTLS_CTR_DRBG_C
-#define MBEDTLS_ENTROPY_C
-#define MBEDTLS_MD_C
-#define MBEDTLS_SHA224_C
-#define MBEDTLS_SHA256_C
-#define MBEDTLS_SSL_COOKIE_C
-#define MBEDTLS_SSL_CLI_C
-#define MBEDTLS_SSL_SRV_C
-#define MBEDTLS_SSL_TLS_C
-
-/* Save RAM at the expense of ROM */
-#define MBEDTLS_AES_ROM_TABLES
-
-/* Save some RAM by adjusting to your exact needs */
-#define MBEDTLS_PSK_MAX_LEN    16 /* 128-bits keys are generally enough */
-
-/*
- * You should adjust this to the exact number of sources you're using: default
- * is the "platform_entropy_poll" source, but you may want to add other ones
- * Minimum is 2 for the entropy test suite.
- */
-#define MBEDTLS_ENTROPY_MAX_SOURCES 2
-
-/*
- * Use only CCM_8 ciphersuites, and
- * save ROM and a few bytes of RAM by specifying our own ciphersuite list
- */
-#define MBEDTLS_SSL_CIPHERSUITES  MBEDTLS_TLS_PSK_WITH_AES_128_CCM_8
-
-/*
- * Allow to save RAM at the expense of interoperability: do this only if you
- * control both ends of the connection!  (See comments in "mbedtls/ssl.h".)
- * The optimal size here depends on the typical size of records.
- */
-#define MBEDTLS_SSL_MAX_CONTENT_LEN  CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN
-
-#include "mbedtls/check_config.h"
-
-#endif /* MBEDTLS_CONFIG_H */
diff --git a/modules/mbedtls/configs/config-mbedtls.h b/modules/mbedtls/configs/config-mbedtls.h
new file mode 100644
index 00000000000..38bf4fc63b9
--- /dev/null
+++ b/modules/mbedtls/configs/config-mbedtls.h
@@ -0,0 +1,556 @@
+/*
+ * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
+ * Copyright (c) 2017 Intel Corporation.
+ * Copyright (c) 2018 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Generic configuration for TLS, manageable by Kconfig.
+ */
+
+#ifndef MBEDTLS_CONFIG_H
+#define MBEDTLS_CONFIG_H
+
+/* System support */
+#define MBEDTLS_PLATFORM_C
+#define MBEDTLS_PLATFORM_MEMORY
+#define MBEDTLS_MEMORY_BUFFER_ALLOC_C
+#define MBEDTLS_MEMORY_ALIGN_MULTIPLE (sizeof(void *))
+#define MBEDTLS_PLATFORM_EXIT_ALT
+#define MBEDTLS_NO_PLATFORM_ENTROPY
+
+#if defined(CONFIG_MBEDTLS_ZEROIZE_ALT)
+#define MBEDTLS_PLATFORM_ZEROIZE_ALT
+#endif
+
+#if defined(CONFIG_MBEDTLS_PLATFORM_NO_STD_FUNCTIONS)
+#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
+#endif /* defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS) */
+
+#if defined(CONFIG_MBEDTLS_PLATFORM_SNPRINTF_ALT)
+#define MBEDTLS_PLATFORM_SNPRINTF_ALT
+#endif /* defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) */
+
+#if defined(CONFIG_MBEDTLS_ENTROPY_POLL_ZEPHYR)
+#define MBEDTLS_ENTROPY_HARDWARE_ALT
+#else
+#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
+#endif
+
+#if defined(CONFIG_MBEDTLS_HAVE_ASM)
+#define MBEDTLS_HAVE_ASM
+#endif
+
+#if defined(CONFIG_MBEDTLS_LMS)
+#define MBEDTLS_LMS_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_HAVE_TIME_DATE)
+#define MBEDTLS_HAVE_TIME
+#define MBEDTLS_HAVE_TIME_DATE
+#define MBEDTLS_PLATFORM_MS_TIME_ALT
+#endif
+
+#if defined(CONFIG_MBEDTLS_TEST)
+#define MBEDTLS_SELF_TEST
+#define MBEDTLS_DEBUG_C
+#endif
+
+/* mbedTLS feature support */
+
+/* Supported TLS versions */
+
+
+#if defined(CONFIG_MBEDTLS_TLS_VERSION_1_2)
+#define MBEDTLS_SSL_PROTO_TLS1_2
+#endif
+
+#if defined(CONFIG_MBEDTLS_TLS_VERSION_1_3)
+#define MBEDTLS_SSL_PROTO_TLS1_3
+#define MBEDTLS_SSL_KEEP_PEER_CERTIFICATE
+#define MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE
+#endif
+
+#if defined(CONFIG_MBEDTLS_TLS_VERSION_1_2) || \
+	defined(CONFIG_MBEDTLS_TLS_VERSION_1_3)
+
+/* Common modules required for TLS 1.2 and 1.3 */
+#define MBEDTLS_SSL_TLS_C
+#define MBEDTLS_SSL_SRV_C
+#define MBEDTLS_SSL_CLI_C
+
+/* This is not supported by Mbed TLS in TLS 1.3 mode
+ * (see modules/crypto/mbedtls/docs/architecture/tls13-support.md).
+ */
+#if !defined(CONFIG_MBEDTLS_TLS_VERSION_1_3)
+#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
+#endif
+
+#endif /* CONFIG_MBEDTLS_TLS_VERSION_1_2 || CONFIG_MBEDTLS_TLS_VERSION_1_3 */
+
+#if defined(CONFIG_MBEDTLS_TLS_SESSION_TICKETS)
+#define MBEDTLS_SSL_SESSION_TICKETS
+#define MBEDTLS_SSL_TICKET_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_DTLS)
+#define MBEDTLS_SSL_PROTO_DTLS
+#define MBEDTLS_SSL_DTLS_ANTI_REPLAY
+#define MBEDTLS_SSL_DTLS_HELLO_VERIFY
+#define MBEDTLS_SSL_COOKIE_C
+#endif
+
+/* Supported key exchange methods */
+
+#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED)
+#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED)
+#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED)
+#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED)
+#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_PSK_MAX_LEN)
+#define MBEDTLS_PSK_MAX_LEN	CONFIG_MBEDTLS_PSK_MAX_LEN
+#endif
+
+#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_ENABLED)
+#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED)
+#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED)
+#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED)
+#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED)
+#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_ECDSA_DETERMINISTIC)
+#define MBEDTLS_ECDSA_DETERMINISTIC
+#endif
+
+#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED)
+#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED)
+#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED)
+#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED
+#define MBEDTLS_SSL_EARLY_DATA
+#endif
+
+#if defined(CONFIG_MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED)
+#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED)
+#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED
+#define MBEDTLS_SSL_EARLY_DATA
+#endif
+
+#if defined(CONFIG_MBEDTLS_HKDF_C)
+#define MBEDTLS_HKDF_C
+#endif
+
+/* Supported cipher modes */
+
+#if defined(CONFIG_MBEDTLS_CIPHER_AES_ENABLED)
+#define MBEDTLS_AES_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_AES_ROM_TABLES)
+#define MBEDTLS_AES_ROM_TABLES
+#endif
+
+#if defined(CONFIG_MBEDTLS_AES_FEWER_TABLES)
+#define MBEDTLS_AES_FEWER_TABLES
+#endif
+
+#if defined(CONFIG_MBEDTLS_CIPHER_CAMELLIA_ENABLED)
+#define MBEDTLS_CAMELLIA_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_CIPHER_DES_ENABLED)
+#define MBEDTLS_DES_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_CIPHER_CHACHA20_ENABLED)
+#define MBEDTLS_CHACHA20_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_CIPHER_CCM_ENABLED)
+#define MBEDTLS_CCM_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_CIPHER_GCM_ENABLED)
+#define MBEDTLS_GCM_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_CIPHER_MODE_XTS_ENABLED)
+#define MBEDTLS_CIPHER_MODE_XTS
+#endif
+
+#if defined(CONFIG_MBEDTLS_CIPHER_MODE_CBC_ENABLED)
+#define MBEDTLS_CIPHER_MODE_CBC
+#endif
+
+#if defined(CONFIG_MBEDTLS_CIPHER_MODE_CTR_ENABLED)
+#define MBEDTLS_CIPHER_MODE_CTR
+#endif
+
+/* Supported elliptic curve libraries */
+
+#if defined(CONFIG_MBEDTLS_ECDH_C)
+#define MBEDTLS_ECDH_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_ECDSA_C)
+#define MBEDTLS_ECDSA_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_ECJPAKE_C)
+#define MBEDTLS_ECJPAKE_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_ECP_C)
+#define MBEDTLS_ECP_C
+#endif
+
+/* Supported elliptic curves */
+
+#if defined(CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED)
+#define MBEDTLS_ECP_DP_SECP192R1_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED)
+#define MBEDTLS_ECP_DP_SECP224R1_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED)
+#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED)
+#define MBEDTLS_ECP_DP_SECP384R1_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED)
+#define MBEDTLS_ECP_DP_SECP521R1_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED)
+#define MBEDTLS_ECP_DP_SECP192K1_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED)
+#define MBEDTLS_ECP_DP_SECP224K1_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED)
+#define MBEDTLS_ECP_DP_SECP256K1_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED)
+#define MBEDTLS_ECP_DP_BP256R1_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED)
+#define MBEDTLS_ECP_DP_BP384R1_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED)
+#define MBEDTLS_ECP_DP_BP512R1_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED)
+#define MBEDTLS_ECP_DP_CURVE25519_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_ECP_DP_CURVE448_ENABLED)
+#define MBEDTLS_ECP_DP_CURVE448_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_ECP_NIST_OPTIM)
+#define MBEDTLS_ECP_NIST_OPTIM
+#endif
+
+/* Supported hash algorithms */
+
+#if defined(CONFIG_MBEDTLS_MD5)
+#define MBEDTLS_MD5_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_SHA1)
+#define MBEDTLS_SHA1_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_SHA224)
+#define MBEDTLS_SHA224_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_SHA256)
+#define MBEDTLS_SHA256_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_SHA256_SMALLER)
+#define MBEDTLS_SHA256_SMALLER
+#endif
+
+#if defined(CONFIG_MBEDTLS_SHA384)
+#define MBEDTLS_SHA384_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_SHA512)
+#define MBEDTLS_SHA512_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_POLY1305)
+#define MBEDTLS_POLY1305_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_CMAC)
+#define MBEDTLS_CMAC_C
+#endif
+
+/* mbedTLS modules */
+#if defined(CONFIG_MBEDTLS_CTR_DRBG_ENABLED)
+#define MBEDTLS_CTR_DRBG_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_HMAC_DRBG_ENABLED)
+#define MBEDTLS_HMAC_DRBG_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_DEBUG)
+#define MBEDTLS_ERROR_C
+#define MBEDTLS_DEBUG_C
+#define MBEDTLS_SSL_DEBUG_ALL
+#define MBEDTLS_SSL_ALL_ALERT_MESSAGES
+#endif
+
+#if defined(CONFIG_MBEDTLS_MEMORY_DEBUG)
+#define MBEDTLS_MEMORY_DEBUG
+#endif
+
+#if defined(CONFIG_MBEDTLS_CHACHAPOLY_AEAD_ENABLED)
+#define MBEDTLS_CHACHAPOLY_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_GENPRIME_ENABLED)
+#define MBEDTLS_GENPRIME
+#endif
+
+#if defined(CONFIG_MBEDTLS_ENTROPY_C)
+#define MBEDTLS_ENTROPY_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_SSL_ALPN)
+#define MBEDTLS_SSL_ALPN
+#endif
+
+#if defined(CONFIG_MBEDTLS_CIPHER)
+#define MBEDTLS_CIPHER_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_MD)
+#define MBEDTLS_MD_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_RSA_C)
+#define MBEDTLS_RSA_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_PKCS1_V15)
+#define MBEDTLS_PKCS1_V15
+#endif
+
+#if defined(CONFIG_MBEDTLS_PKCS1_V15)
+#define MBEDTLS_PKCS1_V21
+#endif
+
+/* Automatic dependencies */
+
+#if defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) || \
+    defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED)
+#define MBEDTLS_DHM_C
+#endif
+
+#if defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) || \
+	defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) || \
+	defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || \
+	defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \
+	defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \
+	defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) || \
+	defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) || \
+	defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED)
+#define MBEDTLS_X509_CRT_PARSE_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_PEM_CERTIFICATE_FORMAT) && \
+    defined(MBEDTLS_X509_CRT_PARSE_C)
+#define MBEDTLS_PEM_PARSE_C
+#define MBEDTLS_PEM_WRITE_C
+#define MBEDTLS_BASE64_C
+#endif
+
+#if defined(MBEDTLS_X509_CRT_PARSE_C)
+#define MBEDTLS_X509_USE_C
+#endif
+
+#if defined(MBEDTLS_DHM_C) || \
+    defined(MBEDTLS_ECP_C) || \
+    defined(MBEDTLS_RSA_C) || \
+    defined(MBEDTLS_X509_USE_C) || \
+    defined(MBEDTLS_GENPRIME)
+#define MBEDTLS_BIGNUM_C
+#endif
+
+#if defined(MBEDTLS_RSA_C) || \
+    defined(MBEDTLS_X509_USE_C)
+#define MBEDTLS_OID_C
+#endif
+
+#if defined(MBEDTLS_X509_USE_C)
+#define MBEDTLS_PK_PARSE_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_PK_WRITE_C)
+#define MBEDTLS_PK_WRITE_C
+#endif
+
+#if defined(MBEDTLS_PK_PARSE_C) || defined(MBEDTLS_PK_WRITE_C)
+#define MBEDTLS_PK_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_ASN1_PARSE_C) || defined(MBEDTLS_X509_USE_C)
+#define MBEDTLS_ASN1_PARSE_C
+#endif
+
+#if defined(MBEDTLS_ECDSA_C) || defined(MBEDTLS_RSA_C) || defined(MBEDTLS_PK_WRITE_C)
+#define MBEDTLS_ASN1_WRITE_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_PKCS5_C)
+#define MBEDTLS_PKCS5_C
+#endif
+
+#define MBEDTLS_SSL_IN_CONTENT_LEN  CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN
+#define MBEDTLS_SSL_OUT_CONTENT_LEN  CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN
+
+/* Enable OpenThread optimizations. */
+#if defined(CONFIG_MBEDTLS_OPENTHREAD_OPTIMIZATIONS_ENABLED)
+#define MBEDTLS_MPI_WINDOW_SIZE            1 /**< Maximum windows size used. */
+#define MBEDTLS_MPI_MAX_SIZE              32 /**< Maximum number of bytes for usable MPIs. */
+#define MBEDTLS_ECP_WINDOW_SIZE            2 /**< Maximum window size used */
+#define MBEDTLS_ECP_FIXED_POINT_OPTIM      0 /**< Enable fixed-point speed-up */
+#define MBEDTLS_ENTROPY_MAX_SOURCES        1 /**< Maximum number of sources supported */
+#endif
+
+#if defined(CONFIG_MBEDTLS_SERVER_NAME_INDICATION) && \
+	defined(MBEDTLS_X509_CRT_PARSE_C)
+#define MBEDTLS_SSL_SERVER_NAME_INDICATION
+#endif
+
+#if defined(CONFIG_MBEDTLS_SSL_CACHE_C)
+#define MBEDTLS_SSL_CACHE_C
+#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT CONFIG_MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT
+#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES CONFIG_MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES
+#endif
+
+#if defined(CONFIG_MBEDTLS_SSL_EXTENDED_MASTER_SECRET)
+#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET
+#endif
+
+#if defined(CONFIG_MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG)
+#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG
+#endif
+
+#if defined(CONFIG_MBEDTLS_PSA_CRYPTO_C)
+#define MBEDTLS_PSA_CRYPTO_C
+#define MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS
+#endif
+
+#if defined(CONFIG_MBEDTLS_PSA_P256M_DRIVER_ENABLED)
+#define MBEDTLS_PSA_P256M_DRIVER_ENABLED
+#endif
+
+#if defined(CONFIG_MBEDTLS_PSA_CRYPTO_STORAGE_C)
+#define MBEDTLS_PSA_CRYPTO_STORAGE_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_PSA_STATIC_KEY_SLOTS)
+#define MBEDTLS_PSA_STATIC_KEY_SLOTS
+#endif
+
+#if defined(CONFIG_MBEDTLS_PSA_KEY_SLOT_COUNT)
+#define MBEDTLS_PSA_KEY_SLOT_COUNT CONFIG_MBEDTLS_PSA_KEY_SLOT_COUNT
+#endif
+
+#if defined(CONFIG_MBEDTLS_USE_PSA_CRYPTO)
+#define MBEDTLS_USE_PSA_CRYPTO
+#endif
+
+#if defined(CONFIG_MBEDTLS_PSA_CRYPTO_CLIENT)
+#define MBEDTLS_PSA_CRYPTO_CLIENT
+#define MBEDTLS_PSA_CRYPTO_CONFIG
+#define MBEDTLS_PSA_CRYPTO_CONFIG_FILE   "config-psa.h"
+#endif
+
+#if defined(CONFIG_MBEDTLS_TLS_VERSION_1_2) && defined(CONFIG_MBEDTLS_PSA_CRYPTO_C)
+#define MBEDTLS_SSL_ENCRYPT_THEN_MAC
+#endif
+
+#if defined(CONFIG_MBEDTLS_SSL_DTLS_CONNECTION_ID)
+#define MBEDTLS_SSL_DTLS_CONNECTION_ID
+#endif
+
+#if defined(CONFIG_MBEDTLS_NIST_KW_C)
+#define MBEDTLS_NIST_KW_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_DHM_C)
+#define MBEDTLS_DHM_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_X509_CRL_PARSE_C)
+#define MBEDTLS_X509_CRL_PARSE_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_X509_CSR_WRITE_C)
+#define MBEDTLS_X509_CSR_WRITE_C
+#define MBEDTLS_X509_CREATE_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_X509_CSR_PARSE_C)
+#define MBEDTLS_X509_CSR_PARSE_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_X509_CRT_WRITE_C)
+#define MBEDTLS_X509_CRT_WRITE_C
+#endif
+
+#if defined(CONFIG_MBEDTLS_USER_CONFIG_FILE)
+#include CONFIG_MBEDTLS_USER_CONFIG_FILE
+#endif
+
+#endif /* MBEDTLS_CONFIG_H */
diff --git a/modules/mbedtls/configs/config-mini-dtls1_2.h b/modules/mbedtls/configs/config-mini-dtls1_2.h
deleted file mode 100644
index ee0d70b5915..00000000000
--- a/modules/mbedtls/configs/config-mini-dtls1_2.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- * Copyright (c) 2017 Intel Corporation.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Minimal configuration for DTLS 1.2 for Zephyr with PSK and AES-CCM
- * ciphersuites.
- *
- * See README.txt for usage instructions.
- */
-#ifndef MBEDTLS_CONFIG_H
-#define MBEDTLS_CONFIG_H
-
-/* System support */
-#define MBEDTLS_PLATFORM_C
-#define MBEDTLS_PLATFORM_MEMORY
-#define MBEDTLS_MEMORY_BUFFER_ALLOC_C
-#define MBEDTLS_MEMORY_ALIGN_MULTIPLE (sizeof(void *))
-#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
-#define MBEDTLS_PLATFORM_EXIT_ALT
-#define MBEDTLS_NO_PLATFORM_ENTROPY
-#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
-#define MBEDTLS_PLATFORM_PRINTF_ALT
-
-#if defined(CONFIG_MBEDTLS_TEST)
-#define MBEDTLS_SELF_TEST
-#define MBEDTLS_DEBUG_C
-#else
-#define MBEDTLS_ENTROPY_C
-#endif
-
-/* mbed TLS feature support */
-#define MBEDTLS_CIPHER_MODE_CBC
-#define MBEDTLS_PKCS1_V15
-#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
-#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
-#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
-#define MBEDTLS_SSL_PROTO_TLS1_2
-#define MBEDTLS_SSL_PROTO_DTLS
-#define MBEDTLS_SSL_DTLS_ANTI_REPLAY
-#define MBEDTLS_SSL_DTLS_HELLO_VERIFY
-
-/* mbed TLS modules */
-#define MBEDTLS_AES_C
-#define MBEDTLS_ASN1_PARSE_C
-#define MBEDTLS_ASN1_WRITE_C
-#define MBEDTLS_BIGNUM_C
-#define MBEDTLS_CIPHER_C
-#define MBEDTLS_CTR_DRBG_C
-#define MBEDTLS_DES_C
-#define MBEDTLS_ENTROPY_C
-#define MBEDTLS_MD_C
-#define MBEDTLS_MD5_C
-#define MBEDTLS_OID_C
-#define MBEDTLS_RSA_C
-#define MBEDTLS_PK_C
-#define MBEDTLS_PK_PARSE_C
-#define MBEDTLS_SHA1_C
-#define MBEDTLS_SHA224_C
-#define MBEDTLS_SHA256_C
-#define MBEDTLS_SSL_CLI_C
-#define MBEDTLS_SSL_SRV_C
-#define MBEDTLS_SSL_TLS_C
-#define MBEDTLS_X509_CRT_PARSE_C
-#define MBEDTLS_X509_USE_C
-#define MBEDTLS_CCM_C
-#define MBEDTLS_SSL_COOKIE_C
-
-/* For test certificates */
-#define MBEDTLS_BASE64_C
-#define MBEDTLS_CERTS_C
-
-#if defined(CONFIG_MBEDTLS_DEBUG)
-#define MBEDTLS_ERROR_C
-#define MBEDTLS_DEBUG_C
-#define MBEDTLS_SSL_DEBUG_ALL
-#define MBEDTLS_SSL_ALL_ALERT_MESSAGES
-#endif
-
-#define MBEDTLS_SSL_MAX_CONTENT_LEN             1500
-
-#include "mbedtls/check_config.h"
-
-#endif /* MBEDTLS_CONFIG_H */
diff --git a/modules/mbedtls/configs/config-mini-tls1_1.h b/modules/mbedtls/configs/config-mini-tls1_1.h
deleted file mode 100644
index da8bf795c1d..00000000000
--- a/modules/mbedtls/configs/config-mini-tls1_1.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/**
- * \file config-mini-tls1_1.h
- *
- * \brief Minimal configuration for TLS 1.1 (RFC 4346)
- */
-/*
- *  Copyright The Mbed TLS Contributors
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- */
-/*
- * Minimal configuration for TLS 1.1 (RFC 4346), implementing only the
- * required ciphersuite: MBEDTLS_TLS_RSA_WITH_3DES_EDE_CBC_SHA
- *
- * See README.txt for usage instructions.
- */
-
-#ifndef MBEDTLS_CONFIG_H
-#define MBEDTLS_CONFIG_H
-
-/* System support */
-#define MBEDTLS_HAVE_ASM
-#define MBEDTLS_HAVE_TIME
-#define MBEDTLS_PLATFORM_MS_TIME_ALT
-
-/* mbed TLS feature support */
-#define MBEDTLS_CIPHER_MODE_CBC
-#define MBEDTLS_PKCS1_V15
-#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
-#define MBEDTLS_SSL_PROTO_TLS1_1
-
-/* mbed TLS modules */
-#define MBEDTLS_AES_C
-#define MBEDTLS_ASN1_PARSE_C
-#define MBEDTLS_ASN1_WRITE_C
-#define MBEDTLS_BIGNUM_C
-#define MBEDTLS_CIPHER_C
-#define MBEDTLS_CTR_DRBG_C
-#define MBEDTLS_DES_C
-#define MBEDTLS_ENTROPY_C
-#define MBEDTLS_MD_C
-#define MBEDTLS_MD5_C
-#define MBEDTLS_NET_C
-#define MBEDTLS_OID_C
-#define MBEDTLS_PK_C
-#define MBEDTLS_PK_PARSE_C
-#define MBEDTLS_RSA_C
-#define MBEDTLS_SHA1_C
-#define MBEDTLS_SHA224_C
-#define MBEDTLS_SHA256_C
-#define MBEDTLS_SSL_CLI_C
-#define MBEDTLS_SSL_SRV_C
-#define MBEDTLS_SSL_TLS_C
-#define MBEDTLS_X509_CRT_PARSE_C
-#define MBEDTLS_X509_USE_C
-
-/* For test certificates */
-#define MBEDTLS_BASE64_C
-#define MBEDTLS_CERTS_C
-#define MBEDTLS_PEM_PARSE_C
-
-/* For testing with compat.sh */
-#define MBEDTLS_FS_IO
-
-#include "mbedtls/check_config.h"
-
-#endif /* MBEDTLS_CONFIG_H */
diff --git a/modules/mbedtls/configs/config-mini-tls1_2.h b/modules/mbedtls/configs/config-mini-tls1_2.h
deleted file mode 100644
index 4045fe70478..00000000000
--- a/modules/mbedtls/configs/config-mini-tls1_2.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- * Copyright (c) 2017 Intel Corporation.
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Minimal configuration for TLS 1.2 (RFC 5246) for Zephyr, implementing only
- * a few of the most popular ciphersuites.
- */
-
-#ifndef MBEDTLS_CONFIG_H
-#define MBEDTLS_CONFIG_H
-
-/* System support */
-#define MBEDTLS_PLATFORM_C
-#define MBEDTLS_PLATFORM_MEMORY
-#define MBEDTLS_MEMORY_BUFFER_ALLOC_C
-#define MBEDTLS_MEMORY_ALIGN_MULTIPLE (sizeof(void *))
-#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
-#define MBEDTLS_PLATFORM_EXIT_ALT
-#define MBEDTLS_NO_PLATFORM_ENTROPY
-#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
-#define MBEDTLS_PLATFORM_PRINTF_ALT
-#define MBEDTLS_PLATFORM_SNPRINTF_ALT
-
-#if !defined(CONFIG_ARM)
-#define MBEDTLS_HAVE_ASM
-#endif
-
-#if defined(CONFIG_MBEDTLS_TEST)
-#define MBEDTLS_SELF_TEST
-#define MBEDTLS_DEBUG_C
-#else
-#define MBEDTLS_ENTROPY_C
-#endif
-
-/* mbed TLS feature support */
-#define MBEDTLS_CIPHER_MODE_CBC
-#define MBEDTLS_PKCS1_V15
-#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
-#define MBEDTLS_SSL_PROTO_TLS1_2
-
-/* mbed TLS modules */
-#define MBEDTLS_AES_C
-#define MBEDTLS_ASN1_PARSE_C
-#define MBEDTLS_ASN1_WRITE_C
-#define MBEDTLS_BIGNUM_C
-#define MBEDTLS_CIPHER_C
-#define MBEDTLS_CTR_DRBG_C
-#define MBEDTLS_DES_C
-#define MBEDTLS_ENTROPY_C
-#define MBEDTLS_MD_C
-#define MBEDTLS_MD5_C
-#define MBEDTLS_OID_C
-#define MBEDTLS_PK_C
-#define MBEDTLS_PK_PARSE_C
-#define MBEDTLS_RSA_C
-#define MBEDTLS_SHA1_C
-#define MBEDTLS_SHA224_C
-#define MBEDTLS_SHA256_C
-#define MBEDTLS_SSL_CLI_C
-#define MBEDTLS_SSL_SRV_C
-#define MBEDTLS_SSL_TLS_C
-#define MBEDTLS_X509_CRT_PARSE_C
-#define MBEDTLS_X509_USE_C
-
-/* For test certificates */
-#define MBEDTLS_BASE64_C
-#define MBEDTLS_CERTS_C
-
-#if defined(CONFIG_MBEDTLS_DEBUG)
-#define MBEDTLS_ERROR_C
-#define MBEDTLS_DEBUG_C
-#define MBEDTLS_SSL_DEBUG_ALL
-#define MBEDTLS_SSL_ALL_ALERT_MESSAGES
-#endif
-
-#define MBEDTLS_SSL_MAX_CONTENT_LEN  CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN
-
-#include "mbedtls/check_config.h"
-
-#endif /* MBEDTLS_CONFIG_H */
diff --git a/modules/mbedtls/configs/config-no-entropy.h b/modules/mbedtls/configs/config-no-entropy.h
deleted file mode 100644
index b3406a394b4..00000000000
--- a/modules/mbedtls/configs/config-no-entropy.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/**
- * \file config-no-entropy.h
- *
- * \brief Minimal configuration of features that do not require an entropy source
- */
-/*
- *  Copyright The Mbed TLS Contributors
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- */
-/*
- * Minimal configuration of features that do not require an entropy source
- * Distinguishing features:
- * - no entropy module
- * - no TLS protocol implementation available due to absence of an entropy
- *   source
- *
- * See README.txt for usage instructions.
- */
-
-#ifndef MBEDTLS_CONFIG_H
-#define MBEDTLS_CONFIG_H
-
-/* System support */
-#define MBEDTLS_HAVE_ASM
-#define MBEDTLS_HAVE_TIME
-#define MBEDTLS_PLATFORM_MS_TIME_ALT
-
-/* mbed TLS feature support */
-#define MBEDTLS_CIPHER_MODE_CBC
-#define MBEDTLS_CIPHER_PADDING_PKCS7
-#define MBEDTLS_REMOVE_ARC4_CIPHERSUITES
-#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
-#define MBEDTLS_ECP_DP_SECP384R1_ENABLED
-#define MBEDTLS_ECP_DP_CURVE25519_ENABLED
-#define MBEDTLS_ECP_NIST_OPTIM
-#define MBEDTLS_ECDSA_DETERMINISTIC
-#define MBEDTLS_PK_RSA_ALT_SUPPORT
-#define MBEDTLS_PKCS1_V15
-#define MBEDTLS_PKCS1_V21
-#define MBEDTLS_SELF_TEST
-#define MBEDTLS_VERSION_FEATURES
-#define MBEDTLS_X509_CHECK_KEY_USAGE
-#define MBEDTLS_X509_CHECK_EXTENDED_KEY_USAGE
-
-/* mbed TLS modules */
-#define MBEDTLS_AES_C
-#define MBEDTLS_ASN1_PARSE_C
-#define MBEDTLS_ASN1_WRITE_C
-#define MBEDTLS_BASE64_C
-#define MBEDTLS_BIGNUM_C
-#define MBEDTLS_CCM_C
-#define MBEDTLS_CIPHER_C
-#define MBEDTLS_ECDSA_C
-#define MBEDTLS_ECP_C
-#define MBEDTLS_ERROR_C
-#define MBEDTLS_GCM_C
-#define MBEDTLS_HMAC_DRBG_C
-#define MBEDTLS_MD_C
-#define MBEDTLS_OID_C
-#define MBEDTLS_PEM_PARSE_C
-#define MBEDTLS_PK_C
-#define MBEDTLS_PK_PARSE_C
-#define MBEDTLS_PK_WRITE_C
-#define MBEDTLS_PLATFORM_C
-#define MBEDTLS_RSA_C
-#define MBEDTLS_SHA224_C
-#define MBEDTLS_SHA256_C
-#define MBEDTLS_SHA384_C
-#define MBEDTLS_SHA512_C
-#define MBEDTLS_VERSION_C
-#define MBEDTLS_X509_USE_C
-#define MBEDTLS_X509_CRT_PARSE_C
-#define MBEDTLS_X509_CRL_PARSE_C
-//#define MBEDTLS_CMAC_C
-
-/* Miscellaneous options */
-#define MBEDTLS_AES_ROM_TABLES
-
-#include "check_config.h"
-
-#endif /* MBEDTLS_CONFIG_H */
diff --git a/modules/mbedtls/configs/config-suite-b.h b/modules/mbedtls/configs/config-suite-b.h
deleted file mode 100644
index 7468f763358..00000000000
--- a/modules/mbedtls/configs/config-suite-b.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/**
- * \file config-suite-b.h
- *
- * \brief Minimal configuration for TLS NSA Suite B Profile (RFC 6460)
- */
-/*
- *  Copyright The Mbed TLS Contributors
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- */
-/*
- * Minimal configuration for TLS NSA Suite B Profile (RFC 6460)
- *
- * Distinguishing features:
- * - no RSA or classic DH, fully based on ECC
- * - optimized for low RAM usage
- *
- * Possible improvements:
- * - if 128-bit security is enough, disable secp384r1 and SHA-512
- * - use embedded certs in DER format and disable PEM_PARSE_C and BASE64_C
- *
- * See README.txt for usage instructions.
- */
-
-#ifndef MBEDTLS_CONFIG_H
-#define MBEDTLS_CONFIG_H
-
-/* System support */
-#define MBEDTLS_HAVE_ASM
-#define MBEDTLS_HAVE_TIME
-#define MBEDTLS_PLATFORM_MS_TIME_ALT
-
-/* mbed TLS feature support */
-#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
-#define MBEDTLS_ECP_DP_SECP384R1_ENABLED
-#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
-#define MBEDTLS_SSL_PROTO_TLS1_2
-
-/* mbed TLS modules */
-#define MBEDTLS_AES_C
-#define MBEDTLS_ASN1_PARSE_C
-#define MBEDTLS_ASN1_WRITE_C
-#define MBEDTLS_BIGNUM_C
-#define MBEDTLS_CIPHER_C
-#define MBEDTLS_CTR_DRBG_C
-#define MBEDTLS_ECDH_C
-#define MBEDTLS_ECDSA_C
-#define MBEDTLS_ECP_C
-#define MBEDTLS_ENTROPY_C
-#define MBEDTLS_GCM_C
-#define MBEDTLS_MD_C
-#define MBEDTLS_NET_C
-#define MBEDTLS_OID_C
-#define MBEDTLS_PK_C
-#define MBEDTLS_PK_PARSE_C
-#define MBEDTLS_SHA224_C
-#define MBEDTLS_SHA256_C
-#define MBEDTLS_SHA384_C
-#define MBEDTLS_SHA512_C
-#define MBEDTLS_SSL_CLI_C
-#define MBEDTLS_SSL_SRV_C
-#define MBEDTLS_SSL_TLS_C
-#define MBEDTLS_X509_CRT_PARSE_C
-#define MBEDTLS_X509_USE_C
-
-/* For test certificates */
-#define MBEDTLS_BASE64_C
-#define MBEDTLS_CERTS_C
-#define MBEDTLS_PEM_PARSE_C
-
-/* Save RAM at the expense of ROM */
-#define MBEDTLS_AES_ROM_TABLES
-
-/* Save RAM by adjusting to our exact needs */
-#define MBEDTLS_MPI_MAX_SIZE    48 // 384 bits is 48 bytes
-
-/* Save RAM at the expense of speed, see ecp.h */
-#define MBEDTLS_ECP_WINDOW_SIZE        2
-#define MBEDTLS_ECP_FIXED_POINT_OPTIM  0
-
-/* Significant speed benefit at the expense of some ROM */
-#define MBEDTLS_ECP_NIST_OPTIM
-
-/*
- * You should adjust this to the exact number of sources you're using: default
- * is the "mbedtls_platform_entropy_poll" source, but you may want to add other ones.
- * Minimum is 2 for the entropy test suite.
- */
-#define MBEDTLS_ENTROPY_MAX_SOURCES 2
-
-/* Save ROM and a few bytes of RAM by specifying our own ciphersuite list */
-#define MBEDTLS_SSL_CIPHERSUITES                        \
-    MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_256_GCM_SHA384,    \
-    MBEDTLS_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256
-
-/*
- * Save RAM at the expense of interoperability: do this only if you control
- * both ends of the connection!  (See comments in "mbedtls/ssl.h".)
- * The minimum size here depends on the certificate chain used as well as the
- * typical size of records.
- */
-#define MBEDTLS_SSL_MAX_CONTENT_LEN             1024
-
-#include "mbedtls/check_config.h"
-
-#endif /* MBEDTLS_CONFIG_H */
diff --git a/modules/mbedtls/configs/config-thread.h b/modules/mbedtls/configs/config-thread.h
deleted file mode 100644
index 24ac5a928cb..00000000000
--- a/modules/mbedtls/configs/config-thread.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/**
- * \file config-thread.h
- *
- * \brief Minimal configuration for using TLS as part of Thread
- */
-/*
- *  Copyright The Mbed TLS Contributors
- *  SPDX-License-Identifier: Apache-2.0 OR GPL-2.0-or-later
- *
- *  This file is provided under the Apache License 2.0, or the
- *  GNU General Public License v2.0 or later.
- *
- *  **********
- *  Apache License 2.0:
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  **********
- *
- *  **********
- *  GNU General Public License v2.0 or later:
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *  **********
- */
-
-/*
- * Minimal configuration for using TLS a part of Thread
- * http://threadgroup.org/
- *
- * Distinguishing features:
- * - no RSA or classic DH, fully based on ECC
- * - no X.509
- * - support for experimental EC J-PAKE key exchange
- *
- * See README.txt for usage instructions.
- */
-
-#ifndef MBEDTLS_CONFIG_H
-#define MBEDTLS_CONFIG_H
-
-/* System support */
-#define MBEDTLS_HAVE_ASM
-
-/* mbed TLS feature support */
-#define MBEDTLS_AES_ROM_TABLES
-#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
-#define MBEDTLS_ECP_NIST_OPTIM
-#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
-#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
-#define MBEDTLS_SSL_PROTO_TLS1_2
-#define MBEDTLS_SSL_PROTO_DTLS
-#define MBEDTLS_SSL_DTLS_ANTI_REPLAY
-#define MBEDTLS_SSL_DTLS_HELLO_VERIFY
-#define MBEDTLS_SSL_EXPORT_KEYS
-
-/* mbed TLS modules */
-#define MBEDTLS_AES_C
-#define MBEDTLS_ASN1_PARSE_C
-#define MBEDTLS_ASN1_WRITE_C
-#define MBEDTLS_BIGNUM_C
-#define MBEDTLS_CCM_C
-#define MBEDTLS_CIPHER_C
-#define MBEDTLS_CTR_DRBG_C
-#define MBEDTLS_CMAC_C
-#define MBEDTLS_ECJPAKE_C
-#define MBEDTLS_ECP_C
-#define MBEDTLS_ENTROPY_C
-#define MBEDTLS_HMAC_DRBG_C
-#define MBEDTLS_MD_C
-#define MBEDTLS_OID_C
-#define MBEDTLS_PK_C
-#define MBEDTLS_PK_PARSE_C
-#define MBEDTLS_SHA224_C
-#define MBEDTLS_SHA256_C
-#define MBEDTLS_SSL_COOKIE_C
-#define MBEDTLS_SSL_CLI_C
-#define MBEDTLS_SSL_SRV_C
-#define MBEDTLS_SSL_TLS_C
-
-/* For tests using ssl-opt.sh */
-#define MBEDTLS_NET_C
-#define MBEDTLS_TIMING_C
-
-/* Save RAM at the expense of ROM */
-#define MBEDTLS_AES_ROM_TABLES
-
-/* Save RAM by adjusting to our exact needs */
-#define MBEDTLS_MPI_MAX_SIZE              32 // 256 bits is 32 bytes
-
-/* Save ROM and a few bytes of RAM by specifying our own ciphersuite list */
-#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8
-
-#include "mbedtls/check_config.h"
-
-#endif /* MBEDTLS_CONFIG_H */
diff --git a/modules/mbedtls/configs/config-threadnet.h b/modules/mbedtls/configs/config-threadnet.h
deleted file mode 100644
index c6676f03433..00000000000
--- a/modules/mbedtls/configs/config-threadnet.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- *  Minimal configuration for using TLS as part of Thread
- *
- *  Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- *  SPDX-License-Identifier: Apache-2.0
- *
- *  Licensed under the Apache License, Version 2.0 (the "License"); you may
- *  not use this file except in compliance with the License.
- *  You may obtain a copy of the License at
- *
- *  http://www.apache.org/licenses/LICENSE-2.0
- *
- *  Unless required by applicable law or agreed to in writing, software
- *  distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- *  WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- *  See the License for the specific language governing permissions and
- *  limitations under the License.
- *
- *  This file is part of mbed TLS (https://tls.mbed.org)
- */
-
-/*
- * Minimal configuration for using TLS a part of Thread
- * http://threadgroup.org/
- *
- * Distinguishing features:
- * - no RSA or classic DH, fully based on ECC
- * - no X.509
- * - support for experimental EC J-PAKE key exchange
- *
- * See README.txt for usage instructions.
- */
-
-#ifndef MBEDTLS_CONFIG_H
-#define MBEDTLS_CONFIG_H
-
-/* System support */
-#define MBEDTLS_PLATFORM_C
-#define MBEDTLS_PLATFORM_MEMORY
-#define MBEDTLS_MEMORY_BUFFER_ALLOC_C
-#define MBEDTLS_MEMORY_ALIGN_MULTIPLE (sizeof(void *))
-#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
-#define MBEDTLS_PLATFORM_EXIT_ALT
-#define MBEDTLS_NO_PLATFORM_ENTROPY
-#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
-#define MBEDTLS_PLATFORM_PRINTF_ALT
-
-#if !defined(CONFIG_ARM)
-#define MBEDTLS_HAVE_ASM
-#endif
-
-#if defined(CONFIG_MBEDTLS_TEST)
-#define MBEDTLS_SELF_TEST
-#define MBEDTLS_DEBUG_C
-#else
-#define MBEDTLS_ENTROPY_C
-#endif
-
-/* mbed TLS feature support */
-#define MBEDTLS_AES_ROM_TABLES
-#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
-#define MBEDTLS_ECP_NIST_OPTIM
-#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
-#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
-#define MBEDTLS_SSL_PROTO_TLS1_2
-#define MBEDTLS_SSL_PROTO_DTLS
-#define MBEDTLS_SSL_DTLS_ANTI_REPLAY
-#define MBEDTLS_SSL_DTLS_HELLO_VERIFY
-#define MBEDTLS_SSL_EXPORT_KEYS
-
-/* mbed TLS modules */
-#define MBEDTLS_AES_C
-#define MBEDTLS_ASN1_PARSE_C
-#define MBEDTLS_ASN1_WRITE_C
-#define MBEDTLS_BIGNUM_C
-#define MBEDTLS_CCM_C
-#define MBEDTLS_CIPHER_C
-#define MBEDTLS_CTR_DRBG_C
-#define MBEDTLS_CMAC_C
-#define MBEDTLS_ECJPAKE_C
-#define MBEDTLS_ECP_C
-#define MBEDTLS_HMAC_DRBG_C
-#define MBEDTLS_MD_C
-#define MBEDTLS_OID_C
-#define MBEDTLS_PK_C
-#define MBEDTLS_PK_PARSE_C
-#define MBEDTLS_SHA224_C
-#define MBEDTLS_SHA256_C
-#define MBEDTLS_SSL_COOKIE_C
-#define MBEDTLS_SSL_CLI_C
-#define MBEDTLS_SSL_SRV_C
-#define MBEDTLS_SSL_TLS_C
-
-
-/* Save RAM at the expense of ROM */
-#define MBEDTLS_AES_ROM_TABLES
-
-/* Save RAM by adjusting to our exact needs */
-#define MBEDTLS_MPI_MAX_SIZE              32 // 256 bits is 32 bytes
-
-#define MBEDTLS_SSL_MAX_CONTENT_LEN 1024
-
-/* Save ROM and a few bytes of RAM by specifying our own ciphersuite list */
-#define MBEDTLS_SSL_CIPHERSUITES MBEDTLS_TLS_ECJPAKE_WITH_AES_128_CCM_8
-
-#include "mbedtls/check_config.h"
-
-#endif /* MBEDTLS_CONFIG_H */
diff --git a/modules/mbedtls/configs/config-tls-generic.h b/modules/mbedtls/configs/config-tls-generic.h
deleted file mode 100644
index 1165314f118..00000000000
--- a/modules/mbedtls/configs/config-tls-generic.h
+++ /dev/null
@@ -1,553 +0,0 @@
-/*
- * Copyright (C) 2006-2015, ARM Limited, All Rights Reserved
- * Copyright (c) 2017 Intel Corporation.
- * Copyright (c) 2018 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Generic configuration for TLS, manageable by Kconfig.
- */
-
-#ifndef MBEDTLS_CONFIG_H
-#define MBEDTLS_CONFIG_H
-
-/* System support */
-#define MBEDTLS_PLATFORM_C
-#define MBEDTLS_PLATFORM_MEMORY
-#define MBEDTLS_MEMORY_BUFFER_ALLOC_C
-#define MBEDTLS_MEMORY_ALIGN_MULTIPLE (sizeof(void *))
-#define MBEDTLS_PLATFORM_EXIT_ALT
-#define MBEDTLS_NO_PLATFORM_ENTROPY
-
-#if defined(CONFIG_MBEDTLS_ZEROIZE_ALT)
-#define MBEDTLS_PLATFORM_ZEROIZE_ALT
-#endif
-
-#if defined(CONFIG_MBEDTLS_PLATFORM_NO_STD_FUNCTIONS)
-#define MBEDTLS_PLATFORM_NO_STD_FUNCTIONS
-#endif /* defined(MBEDTLS_PLATFORM_NO_STD_FUNCTIONS) */
-
-#if defined(CONFIG_MBEDTLS_PLATFORM_SNPRINTF_ALT)
-#define MBEDTLS_PLATFORM_SNPRINTF_ALT
-#endif /* defined(MBEDTLS_PLATFORM_SNPRINTF_ALT) */
-
-#if defined(CONFIG_MBEDTLS_ENTROPY_POLL_ZEPHYR)
-#define MBEDTLS_ENTROPY_HARDWARE_ALT
-#else
-#define MBEDTLS_NO_DEFAULT_ENTROPY_SOURCES
-#endif
-
-#if defined(CONFIG_MBEDTLS_HAVE_ASM)
-#define MBEDTLS_HAVE_ASM
-#endif
-
-#if defined(CONFIG_MBEDTLS_LMS)
-#define MBEDTLS_LMS_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_HAVE_TIME_DATE)
-#define MBEDTLS_HAVE_TIME
-#define MBEDTLS_HAVE_TIME_DATE
-#define MBEDTLS_PLATFORM_MS_TIME_ALT
-#endif
-
-#if defined(CONFIG_MBEDTLS_TEST)
-#define MBEDTLS_SELF_TEST
-#define MBEDTLS_DEBUG_C
-#endif
-
-/* mbedTLS feature support */
-
-/* Supported TLS versions */
-
-
-#if defined(CONFIG_MBEDTLS_TLS_VERSION_1_2)
-#define MBEDTLS_SSL_PROTO_TLS1_2
-#endif
-
-#if defined(CONFIG_MBEDTLS_TLS_VERSION_1_3)
-#define MBEDTLS_SSL_PROTO_TLS1_3
-#define MBEDTLS_SSL_KEEP_PEER_CERTIFICATE
-#define MBEDTLS_SSL_TLS1_3_COMPATIBILITY_MODE
-#endif
-
-#if defined(CONFIG_MBEDTLS_TLS_VERSION_1_2) || \
-	defined(CONFIG_MBEDTLS_TLS_VERSION_1_3)
-
-/* Common modules required for TLS 1.2 and 1.3 */
-#define MBEDTLS_SSL_TLS_C
-#define MBEDTLS_SSL_SRV_C
-#define MBEDTLS_SSL_CLI_C
-
-/* This is not supported by Mbed TLS in TLS 1.3 mode
- * (see modules/crypto/mbedtls/docs/architecture/tls13-support.md).
- */
-#if !defined(CONFIG_MBEDTLS_TLS_VERSION_1_3)
-#define MBEDTLS_SSL_MAX_FRAGMENT_LENGTH
-#endif
-
-#endif /* CONFIG_MBEDTLS_TLS_VERSION_1_2 || CONFIG_MBEDTLS_TLS_VERSION_1_3 */
-
-#if defined(CONFIG_MBEDTLS_TLS_SESSION_TICKETS)
-#define MBEDTLS_SSL_SESSION_TICKETS
-#define MBEDTLS_SSL_TICKET_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_DTLS)
-#define MBEDTLS_SSL_PROTO_DTLS
-#define MBEDTLS_SSL_DTLS_ANTI_REPLAY
-#define MBEDTLS_SSL_DTLS_HELLO_VERIFY
-#define MBEDTLS_SSL_COOKIE_C
-#endif
-
-/* Supported key exchange methods */
-
-#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE_PSK_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE_ECDHE_PSK_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_PSK_MAX_LEN)
-#define MBEDTLS_PSK_MAX_LEN	CONFIG_MBEDTLS_PSK_MAX_LEN
-#endif
-
-#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_ECDSA_DETERMINISTIC)
-#define MBEDTLS_ECDSA_DETERMINISTIC
-#endif
-
-#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED)
-#define MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED)
-#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_ENABLED
-#define MBEDTLS_SSL_EARLY_DATA
-#endif
-
-#if defined(CONFIG_MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED)
-#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED)
-#define MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_PSK_EPHEMERAL_ENABLED
-#define MBEDTLS_SSL_EARLY_DATA
-#endif
-
-#if defined(CONFIG_MBEDTLS_HKDF_C)
-#define MBEDTLS_HKDF_C
-#endif
-
-/* Supported cipher modes */
-
-#if defined(CONFIG_MBEDTLS_CIPHER_AES_ENABLED)
-#define MBEDTLS_AES_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_AES_ROM_TABLES)
-#define MBEDTLS_AES_ROM_TABLES
-#endif
-
-#if defined(CONFIG_MBEDTLS_AES_FEWER_TABLES)
-#define MBEDTLS_AES_FEWER_TABLES
-#endif
-
-#if defined(CONFIG_MBEDTLS_CIPHER_CAMELLIA_ENABLED)
-#define MBEDTLS_CAMELLIA_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_CIPHER_DES_ENABLED)
-#define MBEDTLS_DES_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_CIPHER_CHACHA20_ENABLED)
-#define MBEDTLS_CHACHA20_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_CIPHER_CCM_ENABLED)
-#define MBEDTLS_CCM_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_CIPHER_GCM_ENABLED)
-#define MBEDTLS_GCM_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_CIPHER_MODE_XTS_ENABLED)
-#define MBEDTLS_CIPHER_MODE_XTS
-#endif
-
-#if defined(CONFIG_MBEDTLS_CIPHER_MODE_CBC_ENABLED)
-#define MBEDTLS_CIPHER_MODE_CBC
-#endif
-
-#if defined(CONFIG_MBEDTLS_CIPHER_MODE_CTR_ENABLED)
-#define MBEDTLS_CIPHER_MODE_CTR
-#endif
-
-/* Supported elliptic curve libraries */
-
-#if defined(CONFIG_MBEDTLS_ECDH_C)
-#define MBEDTLS_ECDH_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_ECDSA_C)
-#define MBEDTLS_ECDSA_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_ECJPAKE_C)
-#define MBEDTLS_ECJPAKE_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_ECP_C)
-#define MBEDTLS_ECP_C
-#endif
-
-/* Supported elliptic curves */
-
-#if defined(CONFIG_MBEDTLS_ECP_DP_SECP192R1_ENABLED)
-#define MBEDTLS_ECP_DP_SECP192R1_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_ECP_DP_SECP224R1_ENABLED)
-#define MBEDTLS_ECP_DP_SECP224R1_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED)
-#define MBEDTLS_ECP_DP_SECP256R1_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_ECP_DP_SECP384R1_ENABLED)
-#define MBEDTLS_ECP_DP_SECP384R1_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_ECP_DP_SECP521R1_ENABLED)
-#define MBEDTLS_ECP_DP_SECP521R1_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_ECP_DP_SECP192K1_ENABLED)
-#define MBEDTLS_ECP_DP_SECP192K1_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_ECP_DP_SECP224K1_ENABLED)
-#define MBEDTLS_ECP_DP_SECP224K1_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_ECP_DP_SECP256K1_ENABLED)
-#define MBEDTLS_ECP_DP_SECP256K1_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_ECP_DP_BP256R1_ENABLED)
-#define MBEDTLS_ECP_DP_BP256R1_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_ECP_DP_BP384R1_ENABLED)
-#define MBEDTLS_ECP_DP_BP384R1_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_ECP_DP_BP512R1_ENABLED)
-#define MBEDTLS_ECP_DP_BP512R1_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_ECP_DP_CURVE25519_ENABLED)
-#define MBEDTLS_ECP_DP_CURVE25519_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_ECP_DP_CURVE448_ENABLED)
-#define MBEDTLS_ECP_DP_CURVE448_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_ECP_NIST_OPTIM)
-#define MBEDTLS_ECP_NIST_OPTIM
-#endif
-
-/* Supported hash algorithms */
-
-#if defined(CONFIG_MBEDTLS_MD5)
-#define MBEDTLS_MD5_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_SHA1)
-#define MBEDTLS_SHA1_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_SHA224)
-#define MBEDTLS_SHA224_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_SHA256)
-#define MBEDTLS_SHA256_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_SHA256_SMALLER)
-#define MBEDTLS_SHA256_SMALLER
-#endif
-
-#if defined(CONFIG_MBEDTLS_SHA384)
-#define MBEDTLS_SHA384_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_SHA512)
-#define MBEDTLS_SHA512_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_POLY1305)
-#define MBEDTLS_POLY1305_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_CMAC)
-#define MBEDTLS_CMAC_C
-#endif
-
-/* mbedTLS modules */
-#if defined(CONFIG_MBEDTLS_CTR_DRBG_ENABLED)
-#define MBEDTLS_CTR_DRBG_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_HMAC_DRBG_ENABLED)
-#define MBEDTLS_HMAC_DRBG_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_DEBUG)
-#define MBEDTLS_ERROR_C
-#define MBEDTLS_DEBUG_C
-#define MBEDTLS_SSL_DEBUG_ALL
-#define MBEDTLS_SSL_ALL_ALERT_MESSAGES
-#endif
-
-#if defined(CONFIG_MBEDTLS_MEMORY_DEBUG)
-#define MBEDTLS_MEMORY_DEBUG
-#endif
-
-#if defined(CONFIG_MBEDTLS_CHACHAPOLY_AEAD_ENABLED)
-#define MBEDTLS_CHACHAPOLY_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_GENPRIME_ENABLED)
-#define MBEDTLS_GENPRIME
-#endif
-
-#if defined(CONFIG_MBEDTLS_ENTROPY_C)
-#define MBEDTLS_ENTROPY_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_SSL_ALPN)
-#define MBEDTLS_SSL_ALPN
-#endif
-
-#if defined(CONFIG_MBEDTLS_CIPHER)
-#define MBEDTLS_CIPHER_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_MD)
-#define MBEDTLS_MD_C
-#endif
-
-/* Automatic dependencies */
-
-#if defined(MBEDTLS_KEY_EXCHANGE_DHE_PSK_ENABLED) || \
-    defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED)
-#define MBEDTLS_DHM_C
-#endif
-
-#if defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) || \
-    defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) || \
-    defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || \
-    defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED)
-#define MBEDTLS_RSA_C
-#define MBEDTLS_PKCS1_V15
-#define MBEDTLS_PKCS1_V21
-#endif
-
-#if defined(MBEDTLS_KEY_EXCHANGE_RSA_PSK_ENABLED) || \
-	defined(MBEDTLS_KEY_EXCHANGE_RSA_ENABLED) || \
-	defined(MBEDTLS_KEY_EXCHANGE_DHE_RSA_ENABLED) || \
-	defined(MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED) || \
-	defined(MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED) || \
-	defined(MBEDTLS_KEY_EXCHANGE_ECDH_ECDSA_ENABLED) || \
-	defined(MBEDTLS_KEY_EXCHANGE_ECDH_RSA_ENABLED) || \
-	defined(MBEDTLS_SSL_TLS1_3_KEY_EXCHANGE_MODE_EPHEMERAL_ENABLED)
-#define MBEDTLS_X509_CRT_PARSE_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_PEM_CERTIFICATE_FORMAT) && \
-    defined(MBEDTLS_X509_CRT_PARSE_C)
-#define MBEDTLS_PEM_PARSE_C
-#define MBEDTLS_PEM_WRITE_C
-#define MBEDTLS_BASE64_C
-#endif
-
-#if defined(MBEDTLS_X509_CRT_PARSE_C)
-#define MBEDTLS_X509_USE_C
-#endif
-
-#if defined(MBEDTLS_DHM_C) || \
-    defined(MBEDTLS_ECP_C) || \
-    defined(MBEDTLS_RSA_C) || \
-    defined(MBEDTLS_X509_USE_C) || \
-    defined(MBEDTLS_GENPRIME)
-#define MBEDTLS_BIGNUM_C
-#endif
-
-#if defined(MBEDTLS_RSA_C) || \
-    defined(MBEDTLS_X509_USE_C)
-#define MBEDTLS_OID_C
-#endif
-
-#if defined(MBEDTLS_X509_USE_C)
-#define MBEDTLS_PK_PARSE_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_PK_WRITE_C)
-#define MBEDTLS_PK_WRITE_C
-#endif
-
-#if defined(MBEDTLS_PK_PARSE_C) || defined(MBEDTLS_PK_WRITE_C)
-#define MBEDTLS_PK_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_ASN1_PARSE_C) || defined(MBEDTLS_X509_USE_C)
-#define MBEDTLS_ASN1_PARSE_C
-#endif
-
-#if defined(MBEDTLS_ECDSA_C) || defined(MBEDTLS_RSA_C) || defined(MBEDTLS_PK_WRITE_C)
-#define MBEDTLS_ASN1_WRITE_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_PKCS5_C)
-#define MBEDTLS_PKCS5_C
-#endif
-
-#define MBEDTLS_SSL_IN_CONTENT_LEN  CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN
-#define MBEDTLS_SSL_OUT_CONTENT_LEN  CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN
-
-/* Enable OpenThread optimizations. */
-#if defined(CONFIG_MBEDTLS_OPENTHREAD_OPTIMIZATIONS_ENABLED)
-#define MBEDTLS_MPI_WINDOW_SIZE            1 /**< Maximum windows size used. */
-#define MBEDTLS_MPI_MAX_SIZE              32 /**< Maximum number of bytes for usable MPIs. */
-#define MBEDTLS_ECP_WINDOW_SIZE            2 /**< Maximum window size used */
-#define MBEDTLS_ECP_FIXED_POINT_OPTIM      0 /**< Enable fixed-point speed-up */
-#define MBEDTLS_ENTROPY_MAX_SOURCES        1 /**< Maximum number of sources supported */
-#endif
-
-#if defined(CONFIG_MBEDTLS_SERVER_NAME_INDICATION) && \
-	defined(MBEDTLS_X509_CRT_PARSE_C)
-#define MBEDTLS_SSL_SERVER_NAME_INDICATION
-#endif
-
-#if defined(CONFIG_MBEDTLS_SSL_CACHE_C)
-#define MBEDTLS_SSL_CACHE_C
-#define MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT CONFIG_MBEDTLS_SSL_CACHE_DEFAULT_TIMEOUT
-#define MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES CONFIG_MBEDTLS_SSL_CACHE_DEFAULT_MAX_ENTRIES
-#endif
-
-#if defined(CONFIG_MBEDTLS_SSL_EXTENDED_MASTER_SECRET)
-#define MBEDTLS_SSL_EXTENDED_MASTER_SECRET
-#endif
-
-#if defined(CONFIG_MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG)
-#define MBEDTLS_PSA_CRYPTO_EXTERNAL_RNG
-#endif
-
-#if defined(CONFIG_MBEDTLS_PSA_CRYPTO_C)
-#define MBEDTLS_PSA_CRYPTO_C
-#define MBEDTLS_PSA_ASSUME_EXCLUSIVE_BUFFERS
-#endif
-
-#if defined(CONFIG_MBEDTLS_PSA_P256M_DRIVER_ENABLED)
-#define MBEDTLS_PSA_P256M_DRIVER_ENABLED
-#endif
-
-#if defined(CONFIG_MBEDTLS_PSA_CRYPTO_STORAGE_C)
-#define MBEDTLS_PSA_CRYPTO_STORAGE_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_PSA_STATIC_KEY_SLOTS)
-#define MBEDTLS_PSA_STATIC_KEY_SLOTS
-#endif
-
-#if defined(CONFIG_MBEDTLS_PSA_KEY_SLOT_COUNT)
-#define MBEDTLS_PSA_KEY_SLOT_COUNT CONFIG_MBEDTLS_PSA_KEY_SLOT_COUNT
-#endif
-
-#if defined(CONFIG_MBEDTLS_USE_PSA_CRYPTO)
-#define MBEDTLS_USE_PSA_CRYPTO
-#endif
-
-#if defined(CONFIG_MBEDTLS_PSA_CRYPTO_CLIENT)
-#define MBEDTLS_PSA_CRYPTO_CLIENT
-#define MBEDTLS_PSA_CRYPTO_CONFIG
-#define MBEDTLS_PSA_CRYPTO_CONFIG_FILE   "config-psa.h"
-#endif
-
-#if defined(CONFIG_MBEDTLS_TLS_VERSION_1_2) && defined(CONFIG_MBEDTLS_PSA_CRYPTO_C)
-#define MBEDTLS_SSL_ENCRYPT_THEN_MAC
-#endif
-
-#if defined(CONFIG_MBEDTLS_SSL_DTLS_CONNECTION_ID)
-#define MBEDTLS_SSL_DTLS_CONNECTION_ID
-#endif
-
-#if defined(CONFIG_MBEDTLS_NIST_KW_C)
-#define MBEDTLS_NIST_KW_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_DHM_C)
-#define MBEDTLS_DHM_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_X509_CRL_PARSE_C)
-#define MBEDTLS_X509_CRL_PARSE_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_X509_CSR_WRITE_C)
-#define MBEDTLS_X509_CSR_WRITE_C
-#define MBEDTLS_X509_CREATE_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_X509_CSR_PARSE_C)
-#define MBEDTLS_X509_CSR_PARSE_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_X509_CRT_WRITE_C)
-#define MBEDTLS_X509_CRT_WRITE_C
-#endif
-
-#if defined(CONFIG_MBEDTLS_USER_CONFIG_FILE)
-#include CONFIG_MBEDTLS_USER_CONFIG_FILE
-#endif
-
-#endif /* MBEDTLS_CONFIG_H */
diff --git a/modules/nrf_wifi/bus/CMakeLists.txt b/modules/nrf_wifi/bus/CMakeLists.txt
index 3e433949da6..c36fec9d737 100644
--- a/modules/nrf_wifi/bus/CMakeLists.txt
+++ b/modules/nrf_wifi/bus/CMakeLists.txt
@@ -1,14 +1,9 @@
 #
 # Copyright (c) 2024 Nordic Semiconductor ASA
 #
-# SPDX-License-Identifier: BSD-3-Clause
+# SPDX-License-Identifier: Apache-2.0
 #
 
-# Check if ZEPHYR_BASE is set
-if(NOT DEFINED ENV{ZEPHYR_BASE})
-    message(FATAL_ERROR "ZEPHYR_BASE environment variable is not set. Please set it to the Zephyr base directory.")
-endif()
-
 set(NRF_WIFI_DIR ${ZEPHYR_CURRENT_MODULE_DIR})
 
 if (CONFIG_NRF70_BUSLIB)
@@ -31,18 +26,8 @@ if (CONFIG_NRF70_BUSLIB)
     inc
     ${NRF_WIFI_DIR}/os_if/inc
   )
-  zephyr_library_include_directories_ifdef(CONFIG_NRF71_ON_IPC
-    ${NRF_WIFI_DIR}/bus_if/bal/inc
-    # QSPI is common to (Q)SPI and IPC
-    ${NRF_WIFI_DIR}/bus_if/bus/qspi/inc
-    ${NRF_WIFI_DIR}/fw_if/umac_if/inc/fw
-    ${NRF_WIFI_DIR}/hw_if/hal/inc
-  )
-
-  zephyr_library_compile_definitions_ifdef(CONFIG_NRF71_ON_IPC
-    NRF71_ON_IPC
-  )
   zephyr_library_sources(
+    rpu_hw_if.c
     device.c
   )
   if(NOT CONFIG_WIFI_NRF70)
@@ -51,16 +36,9 @@ if (CONFIG_NRF70_BUSLIB)
     )
   endif()
   zephyr_library_sources_ifdef(CONFIG_NRF70_ON_QSPI
-    rpu_hw_if.c
     qspi_if.c
   )
   zephyr_library_sources_ifdef(CONFIG_NRF70_ON_SPI
-    rpu_hw_if.c
     spi_if.c
   )
-  zephyr_library_sources_ifdef(CONFIG_NRF71_ON_IPC
-    ipc_if.c
-    ipc_service.c
-    spsc_qm.c
-  )
 endif()
diff --git a/modules/nrf_wifi/bus/Kconfig b/modules/nrf_wifi/bus/Kconfig
index fe6b0f34553..152904e86b7 100644
--- a/modules/nrf_wifi/bus/Kconfig
+++ b/modules/nrf_wifi/bus/Kconfig
@@ -10,7 +10,6 @@ DT_COMPAT_NORDIC_NRF7001_QSPI := nordic,nrf7001-qspi
 DT_COMPAT_NORDIC_NRF7001_SPI := nordic,nrf7001-spi
 DT_COMPAT_NORDIC_NRF7000_QSPI := nordic,nrf7000-qspi
 DT_COMPAT_NORDIC_NRF7000_SPI := nordic,nrf7000-spi
-DT_COMPAT_NORDIC_WIFI71 := nordic,wifi71
 
 menuconfig NRF70_BUSLIB
 	bool "NRF70 Bus Library"
@@ -31,15 +30,6 @@ config NRF70_ON_SPI
 			 $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF7000_SPI))
 	select SPI
 
-config NRF71_ON_IPC
-	def_bool $(dt_compat_enabled,$(DT_COMPAT_NORDIC_WIFI71))
-	select MBOX
-	select IPC_SERVICE
-	select SPSC_PBUF
-	help
-	  nRF71 is a Wi-Fi and BLE combo SoC and uses IPC as a communication
-	  between APP and Wi-Fi cores.
-
 module = WIFI_NRF70_BUSLIB
 module-dep = LOG
 module-str = Log level for Wi-Fi nRF70 bus library
diff --git a/modules/nrf_wifi/bus/device.c b/modules/nrf_wifi/bus/device.c
index 611af2489c8..8cf0b77cd67 100644
--- a/modules/nrf_wifi/bus/device.c
+++ b/modules/nrf_wifi/bus/device.c
@@ -12,26 +12,15 @@
 #include <zephyr/kernel.h>
 #include <zephyr/sys/printk.h>
 #include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/wifi/nrf_wifi/bus/qspi_if.h>
 #include <stdio.h>
 #include <string.h>
 
-#if defined(CONFIG_NRF71_ON_IPC)
-#include "ipc_if.h"
-#else
-#include <zephyr/drivers/wifi/nrf_wifi/bus/qspi_if.h>
 #include "spi_if.h"
+
 static struct qspi_config config;
-#endif
 
-#if defined(CONFIG_NRF71_ON_IPC)
-static struct rpu_dev ipc = {
-	.init = ipc_init,
-	.deinit = ipc_deinit,
-	.send = ipc_send,
-	.recv = ipc_recv,
-	.register_rx_cb = ipc_register_rx_cb,
-};
-#elif defined(CONFIG_NRF70_ON_QSPI)
+#if defined(CONFIG_NRF70_ON_QSPI)
 static struct qspi_dev qspi = {.init = qspi_init,
 			       .deinit = qspi_deinit,
 			       .read = qspi_read,
@@ -45,7 +34,6 @@ static struct qspi_dev spim = {.init = spim_init,
 			       .hl_read = spim_hl_read};
 #endif
 
-#ifndef CONFIG_NRF71_ON_IPC
 struct qspi_config *qspi_defconfig(void)
 {
 	memset(&config, 0, sizeof(struct qspi_config));
@@ -83,20 +71,12 @@ struct qspi_config *qspi_get_config(void)
 {
 	return &config;
 }
-#endif
 
-#ifndef CONFIG_NRF71_ON_IPC
 struct qspi_dev *qspi_dev(void)
 {
-#if defined(CONFIG_NRF70_ON_QSPI)
+#if CONFIG_NRF70_ON_QSPI
 	return &qspi;
 #else
 	return &spim;
 #endif
 }
-#else
-struct rpu_dev *rpu_dev(void)
-{
-	return &ipc;
-}
-#endif /*! CONFIG_NRF71_ON_IPC */
diff --git a/modules/nrf_wifi/bus/ipc_if.c b/modules/nrf_wifi/bus/ipc_if.c
deleted file mode 100644
index 5a07a434173..00000000000
--- a/modules/nrf_wifi/bus/ipc_if.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * Copyright (c) 2024 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @brief File containing API definitions for the
- * IPC bus layer of the nRF71 Wi-Fi driver.
- */
-#include <zephyr/kernel.h>
-#include <zephyr/logging/log.h>
-
-LOG_MODULE_DECLARE(wifi_nrf_bus, CONFIG_WIFI_NRF70_BUSLIB_LOG_LEVEL);
-
-#include "ipc_if.h"
-#include "bal_structs.h"
-#include "qspi.h"
-#include "common/hal_structs_common.h"
-
-/* Define addresses to use for the free queues */
-#define EVENT_FREEQ_ADDR 0x200C2000
-#define CMD_FREEQ_ADDR   0x200C3000
-
-#define NUM_INSTANCES 3
-#define NUM_ENDPOINTS 1
-
-struct device *ipc_instances[NUM_INSTANCES];
-struct ipc_ept ept[NUM_ENDPOINTS];
-struct ipc_ept_cfg ept_cfg[NUM_ENDPOINTS];
-
-static wifi_ipc_t wifi_event;
-static wifi_ipc_t wifi_cmd;
-static wifi_ipc_t wifi_tx;
-
-static int (*callback_func)(void *data);
-
-static void event_recv(void *data, void *priv)
-{
-	struct nrf_wifi_bus_qspi_dev_ctx *dev_ctx = NULL;
-	struct nrf_wifi_bal_dev_ctx *bal_dev_ctx = NULL;
-	struct nrf_wifi_hal_dev_ctx *hal_dev_ctx = NULL;
-
-	dev_ctx = (struct nrf_wifi_bus_qspi_dev_ctx *)priv;
-	bal_dev_ctx = (struct nrf_wifi_bal_dev_ctx *)dev_ctx->bal_dev_ctx;
-	hal_dev_ctx = (struct nrf_wifi_hal_dev_ctx *)bal_dev_ctx->hal_dev_ctx;
-	LOG_DBG("Event IPC received");
-
-	hal_dev_ctx->ipc_msg = data;
-	callback_func(priv);
-	LOG_DBG("Event IPC callback completed");
-}
-
-int ipc_init(void)
-{
-	wifi_ipc_host_event_init(&wifi_event, EVENT_FREEQ_ADDR);
-	LOG_DBG("Event IPC initialized");
-	wifi_ipc_host_cmd_init(&wifi_cmd, CMD_FREEQ_ADDR);
-	LOG_DBG("Command IPC initialized");
-	return 0;
-}
-
-int ipc_deinit(void)
-{
-	return 0;
-}
-
-int ipc_recv(ipc_ctx_t ctx, void *data, int len)
-{
-	return 0;
-}
-
-int ipc_send(ipc_ctx_t ctx, const void *data, int len)
-{
-
-	int ret = 0;
-
-	switch (ctx.inst) {
-	case IPC_INSTANCE_CMD_CTRL:
-		/* IPC service on RPU may not have been established. Keep trying. */
-		do {
-			ret = wifi_ipc_host_cmd_send_memcpy(&wifi_cmd, data, len);
-		} while (ret == WIFI_IPC_STATUS_BUSYQ_NOTREADY);
-
-		/* Critical error during IPC service transfer. Should never happen. */
-		if (ret == WIFI_IPC_STATUS_BUSYQ_CRITICAL_ERR) {
-			LOG_ERR("Critical error during IPC CMD busyq transfer");
-			return -1;
-		}
-		break;
-	case IPC_INSTANCE_CMD_TX:
-		/* IPC service on RPU may not have been established. Keep trying. */
-		do {
-			ret = wifi_ipc_host_tx_send(&wifi_tx, data);
-		} while (ret == WIFI_IPC_STATUS_BUSYQ_NOTREADY);
-
-		/* Critical error during IPC service transfer. Should never happen. */
-		if (ret == WIFI_IPC_STATUS_BUSYQ_CRITICAL_ERR) {
-			LOG_ERR("Critical error during IPC TX busyq transfer");
-			return -1;
-		}
-	case IPC_INSTANCE_RX:
-		break;
-	default:
-		break;
-	}
-
-	LOG_DBG("IPC send completed: %d", ret);
-
-	return ret;
-}
-
-int ipc_register_rx_cb(int (*rx_handler)(void *priv), void *data)
-{
-	int ret;
-
-	callback_func = rx_handler;
-
-	ret = wifi_ipc_bind_ipc_service_tx_rx(&wifi_cmd, &wifi_event,
-					      DEVICE_DT_GET(DT_NODELABEL(ipc0)), event_recv, data);
-	if (ret != WIFI_IPC_STATUS_OK) {
-		LOG_ERR("Failed to bind IPC service: %d", ret);
-		return -1;
-	}
-
-	ret = wifi_ipc_bind_ipc_service(&wifi_tx, DEVICE_DT_GET(DT_NODELABEL(ipc1)), event_recv,
-					data);
-	if (ret != WIFI_IPC_STATUS_OK) {
-		LOG_ERR("Failed to bind IPC service: %d", ret);
-		return -1;
-	}
-
-	return 0;
-}
diff --git a/modules/nrf_wifi/bus/ipc_if.h b/modules/nrf_wifi/bus/ipc_if.h
deleted file mode 100644
index 5dbc2edf4f4..00000000000
--- a/modules/nrf_wifi/bus/ipc_if.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2024 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef __IPC_IF_H__
-#define __IPC_IF_H__
-
-#include <zephyr/kernel.h>
-#include "ipc_service.h"
-
-typedef enum {
-	IPC_INSTANCE_CMD_CTRL = 0,
-	IPC_INSTANCE_CMD_TX,
-	IPC_INSTANCE_EVT,
-	IPC_INSTANCE_RX
-} ipc_instances_nrf71_t;
-
-typedef enum {
-	IPC_EPT_UMAC = 0,
-	IPC_EPT_LMAC
-} ipc_epts_nrf71_t;
-
-typedef struct ipc_ctx {
-	ipc_instances_nrf71_t inst;
-	ipc_epts_nrf71_t ept;
-} ipc_ctx_t;
-
-struct rpu_dev {
-	int (*init)();
-	int (*deinit)(void);
-	int (*send)(ipc_ctx_t ctx, const void *data, int len);
-	int (*recv)(ipc_ctx_t ctx, void *data, int len);
-	int (*register_rx_cb)(int (*rx_handler)(void *priv), void *data);
-};
-
-struct rpu_dev *rpu_dev(void);
-
-int ipc_init(void);
-int ipc_deinit(void);
-int ipc_send(ipc_ctx_t ctx, const void *data, int len);
-/* Blocking Receive */
-int ipc_recv(ipc_ctx_t ctx, void *data, int len);
-/* Non-blocking Receive (global, not per instance) */
-int ipc_register_rx_cb(int (*rx_handler)(void *priv), void *data);
-
-#endif /* __IPC_IF_H__ */
diff --git a/modules/nrf_wifi/bus/ipc_service.c b/modules/nrf_wifi/bus/ipc_service.c
deleted file mode 100644
index e1e6b3cf4fb..00000000000
--- a/modules/nrf_wifi/bus/ipc_service.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * Copyright (c) 2025 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @brief File containing API definitions for the
- * IPC service layer of the nrf71 Wi-Fi driver.
- */
-#include <zephyr/kernel.h>
-#include <zephyr/logging/log.h>
-
-LOG_MODULE_REGISTER(wifi_nrf_bus, CONFIG_WIFI_NRF70_BUSLIB_LOG_LEVEL);
-
-#include "ipc_service.h"
-
-static void wifi_ipc_ep_bound(void *priv)
-{
-	wifi_ipc_t *context = (wifi_ipc_t *)priv;
-
-	context->busy_q.ipc_ready = true;
-}
-
-static void wifi_ipc_recv_callback(const void *data, size_t len, void *priv)
-{
-	(void)len;
-	uint32_t global_addr = *((uint32_t *)data);
-
-	wifi_ipc_t *context = (wifi_ipc_t *)priv;
-
-	context->busy_q.recv_cb((void *)global_addr, context->busy_q.priv);
-
-	if (context->free_q != NULL) {
-		while (!spsc32_push(context->free_q, global_addr)) {
-		};
-	}
-}
-
-static void wifi_ipc_busyq_init(wifi_ipc_busyq_t *busyq, const ipc_device_wrapper_t *ipc_inst,
-				void *rx_cb, void *priv)
-{
-	busyq->ipc_inst = ipc_inst;
-	busyq->ipc_ep_cfg.cb.bound = wifi_ipc_ep_bound;
-	busyq->ipc_ep_cfg.cb.received = wifi_ipc_recv_callback;
-	busyq->recv_cb = rx_cb;
-	busyq->ipc_ready = false;
-	busyq->priv = priv;
-}
-
-/**
- * Register the IPC service on the busy_queue
- */
-static wifi_ipc_status_t wifi_ipc_busyq_register(wifi_ipc_t *context)
-{
-	int ret;
-	const struct device *ipc_instance = GET_IPC_INSTANCE(context->busy_q.ipc_inst);
-
-	ret = ipc_service_open_instance(ipc_instance);
-	if (ret < 0) {
-		return WIFI_IPC_STATUS_INIT_ERR;
-	}
-
-	context->busy_q.ipc_ep_cfg.name = "ep";
-	context->busy_q.ipc_ep_cfg.priv = context;
-
-	ret = ipc_service_register_endpoint(ipc_instance, &context->busy_q.ipc_ep,
-						&context->busy_q.ipc_ep_cfg);
-	if (ret < 0 && ret != -EALREADY) {
-		return WIFI_IPC_STATUS_INIT_ERR;
-	}
-
-	LOG_INF("IPC busy queue registered");
-
-	return WIFI_IPC_STATUS_OK;
-}
-
-wifi_ipc_status_t wifi_ipc_bind_ipc_service(wifi_ipc_t *context,
-						const ipc_device_wrapper_t *ipc_inst,
-						void (*rx_cb)(void *data, void *priv), void *priv)
-{
-	wifi_ipc_busyq_init(&context->busy_q, ipc_inst, rx_cb, priv);
-	return wifi_ipc_busyq_register(context);
-}
-
-wifi_ipc_status_t wifi_ipc_bind_ipc_service_tx_rx(wifi_ipc_t *tx, wifi_ipc_t *rx,
-						  const ipc_device_wrapper_t *ipc_inst,
-						  void (*rx_cb)(void *data, void *priv), void *priv)
-{
-	wifi_ipc_busyq_init(&rx->busy_q, ipc_inst, rx_cb, priv);
-
-	/**
-	 * When initialising an IPC service, both TX and RX mailboxes need to be
-	 * registered at the same time using a single function call. Both tx and
-	 * rx need to refer to the same IPC instance.
-	 */
-	tx->linked_ipc = &rx->busy_q;
-
-	return wifi_ipc_busyq_register(rx);
-}
-
-wifi_ipc_status_t wifi_ipc_freeq_get(wifi_ipc_t *context, uint32_t *data)
-{
-	if (context->free_q == NULL) {
-		LOG_ERR("Free queue is not initialised");
-		return WIFI_IPC_STATUS_FREEQ_UNINIT_ERR;
-	}
-
-	if (spsc32_is_empty(context->free_q)) {
-		LOG_DBG("Free queue is empty");
-		return WIFI_IPC_STATUS_FREEQ_EMPTY;
-	}
-
-	if (!spsc32_read_head(context->free_q, data)) {
-		LOG_DBG("Free queue is empty");
-		return WIFI_IPC_STATUS_FREEQ_EMPTY;
-	}
-
-	return WIFI_IPC_STATUS_OK;
-}
-
-wifi_ipc_status_t wifi_ipc_freeq_send(wifi_ipc_t *context, uint32_t data)
-{
-	return (spsc32_push(context->free_q, data) == true ? WIFI_IPC_STATUS_OK
-								 : WIFI_IPC_STATUS_FREEQ_FULL);
-}
-
-wifi_ipc_status_t wifi_ipc_busyq_send(wifi_ipc_t *context, uint32_t *data)
-{
-	/* Get correct linked endpoint */
-	wifi_ipc_busyq_t *busyq =
-		context->linked_ipc ? context->linked_ipc : &context->busy_q;
-
-	if (!busyq->ipc_ready) {
-		LOG_ERR("IPC service is not ready");
-		return WIFI_IPC_STATUS_BUSYQ_NOTREADY;
-	}
-
-	int ret = ipc_service_send(&busyq->ipc_ep, data, sizeof(*data));
-
-	if (ret == -ENOMEM) {
-		LOG_ERR("No space in the buffer");
-		/* No space in the buffer */
-		return WIFI_IPC_STATUS_BUSYQ_FULL;
-	} else if (ret < 0) {
-		LOG_ERR("Critical IPC failure: %d", ret);
-		/* Critical IPC failure */
-		return WIFI_IPC_STATUS_BUSYQ_CRITICAL_ERR;
-	}
-
-	if (context->free_q != NULL) {
-		/* Free up global address pointer from the free queue */
-		uint32_t data_out;
-
-		return (spsc32_pop(context->free_q, &data_out) == true
-				? (*data == data_out ? WIFI_IPC_STATUS_OK
-							: WIFI_IPC_STATUS_FREEQ_INVALID)
-				: WIFI_IPC_STATUS_FREEQ_EMPTY);
-	}
-
-	return WIFI_IPC_STATUS_OK;
-}
-
-wifi_ipc_status_t wifi_ipc_host_cmd_init(wifi_ipc_t *context, uint32_t addr_freeq)
-{
-	context->free_q = (void *)addr_freeq;
-	return WIFI_IPC_STATUS_OK;
-}
-
-wifi_ipc_status_t wifi_ipc_host_event_init(wifi_ipc_t *context, uint32_t addr_freeq)
-{
-	context->free_q = (void *)addr_freeq;
-	return WIFI_IPC_STATUS_OK;
-}
-
-wifi_ipc_status_t wifi_ipc_host_cmd_get(wifi_ipc_t *context, uint32_t *data)
-{
-	return wifi_ipc_freeq_get(context, data);
-}
-
-wifi_ipc_status_t wifi_ipc_host_cmd_send(wifi_ipc_t *context, uint32_t *data)
-{
-	return wifi_ipc_busyq_send(context, data);
-}
-
-wifi_ipc_status_t wifi_ipc_host_cmd_send_memcpy(wifi_ipc_t *context, const void *msg,
-						size_t len)
-{
-	int ret;
-	uint32_t gdram_addr;
-
-	ret = wifi_ipc_host_cmd_get(context, &gdram_addr);
-	if (ret != WIFI_IPC_STATUS_OK) {
-		LOG_ERR("Failed to get command location from free queue: %d", ret);
-		return ret;
-	}
-
-	memcpy((void *)gdram_addr, msg, len);
-
-	return wifi_ipc_host_cmd_send(context, &gdram_addr);
-}
-
-wifi_ipc_status_t wifi_ipc_host_tx_send(wifi_ipc_t *context, const void *msg)
-{
-	return wifi_ipc_host_cmd_send(context, (uint32_t *)&msg);
-}
diff --git a/modules/nrf_wifi/bus/ipc_service.h b/modules/nrf_wifi/bus/ipc_service.h
deleted file mode 100644
index 3d355e0c23a..00000000000
--- a/modules/nrf_wifi/bus/ipc_service.h
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * Copyright (c) 2025 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef IPC_SERVICE_H
-#define IPC_SERVICE_H
-
-#include <zephyr/device.h>
-#include <zephyr/ipc/ipc_service.h>
-#include "spsc_qm.h"
-
-#define GET_IPC_INSTANCE(dev) (dev)
-typedef struct device ipc_device_wrapper_t;
-
-#include <stdint.h>
-#include <stdbool.h>
-
-/*
- * Must be large enough to contain the internal struct (spsc_pbuf struct) and
- * at least two bytes of data (one is reserved for written message length)
- */
-#define _MIN_SPSC_SIZE            (sizeof(spsc_queue_t) + sizeof(uint32_t))
-/*
- * TODO: Unsure why some additional bytes are needed for overhead.
- */
-#define WIFI_IPC_GET_SPSC_SIZE(x) (_MIN_SPSC_SIZE + 12 + (x))
-
-/* 4 x cmd location 32-bit pointers of 400 bytes each */
-#define WIFI_IPC_CMD_SIZE      400
-#define WIFI_IPC_CMD_NUM       4
-#define WIFI_IPC_CMD_SPSC_SIZE WIFI_IPC_GET_SPSC_SIZE(WIFI_IPC_CMD_NUM * sizeof(uint32_t))
-
-/* 7 x event location 32-bit pointers of 1000 bytes each */
-#define WIFI_IPC_EVENT_SIZE      1000
-#define WIFI_IPC_EVENT_NUM       7
-#define WIFI_IPC_EVENT_SPSC_SIZE WIFI_IPC_GET_SPSC_SIZE(WIFI_IPC_EVENT_NUM * sizeof(uint32_t))
-
-/**
- * @enum wifi_ipc_status_t
- * @brief Status codes for the Wi-Fi IPC service.
- *
- * This enumeration defines various status codes that represent
- * the state or result of operations in the Wi-Fi IPC service.
- */
-typedef enum {
-	/** Status indicating the operation completed successfully. */
-	WIFI_IPC_STATUS_OK = 0,
-
-	/** Error indicating failure to register IPC service for the Busy queue. */
-	WIFI_IPC_STATUS_INIT_ERR,
-
-	/** Error indicating that the Free queue has not been initialized. */
-	WIFI_IPC_STATUS_FREEQ_UNINIT_ERR,
-
-	/** Status indicating that the Free queue is empty. */
-	WIFI_IPC_STATUS_FREEQ_EMPTY,
-
-	/** Error indicating that the value passed to wifi_ipc_busyq_send()
-	 * does not match the value from the Free queue.
-	 */
-	WIFI_IPC_STATUS_FREEQ_INVALID,
-
-	/** Status indicating that the Free queue is full. */
-	WIFI_IPC_STATUS_FREEQ_FULL,
-
-	/** Error indicating that the IPC service for the Busy queue connection
-	 * has not been established.
-	 */
-	WIFI_IPC_STATUS_BUSYQ_NOTREADY,
-
-	/** Status indicating that the Busy queue is full. */
-	WIFI_IPC_STATUS_BUSYQ_FULL,
-
-	/** Critical error indicating an IPC transfer failure. This should never happen. */
-	WIFI_IPC_STATUS_BUSYQ_CRITICAL_ERR,
-} wifi_ipc_status_t;
-
-/**
- * Structure to hold context information for busy queue.
- */
-typedef struct {
-	const ipc_device_wrapper_t *ipc_inst;
-	struct ipc_ept ipc_ep;
-	struct ipc_ept_cfg ipc_ep_cfg;
-	void (*recv_cb)(const void *data, const void *priv);
-	const void *priv;
-	volatile bool ipc_ready;
-} wifi_ipc_busyq_t;
-
-/**
- * Top-level structure to hold context information for sending data between RPU
- * and the Host.
- */
-typedef struct {
-	spsc_queue_t *free_q;
-
-	wifi_ipc_busyq_t busy_q;
-	wifi_ipc_busyq_t *linked_ipc;
-} wifi_ipc_t;
-
-/**
- * Performs memory-to-memory copy via MVDMA.
- *
- * Enters low power state by issuing wait-for-interrupt (WFI) while waiting for
- * MVDMA event to complete.
- *
- * @param[in] p_dest : Pointer to destination memory to be copied to.
- * @param[in] p_src : Pointer to source memory to be copied from.
- * @param[in] len : Number of bytes to be copied.
- */
-void wifi_ipc_mvdma_copy(void *p_dest, const void *p_src, size_t len);
-
-/**
- * Bind either TX or RX context to one IPC service. This utilises the half-duplex
- * capability of the IPC service.
- *
- * @param[in] p_context : Pointer to wifi_ipc_t struct.
- * @param[in] ipc_inst : Pointer to the IPC instance.
- * @param[in] rx_cb : If binding RX context, this is the callback function.
- *                    Leave NULL if binding to a TX.
- * @param[in] priv : If binding RX context, this is the private data to be passed
- *                   along with the callback function.
- *                   Leave NULL if binding to a TX.
- * @return : wifi_ipc_status_ok if successful, otherwise wifi_ipc_status_init_err.
- */
-wifi_ipc_status_t wifi_ipc_bind_ipc_service(wifi_ipc_t *p_context,
-						const ipc_device_wrapper_t *ipc_inst,
-						void (*rx_cb)(void *data, void *priv), void *priv);
-
-/**
- * Bind both TX and RX contexts to a single IPC service. This utilises the
- * full-duplex capability of the IPC service.
- *
- * @param[in] p_tx : Pointer to wifi_ipc_t struct to bind IPC TX mailbox to.
- * @param[in] p_rx : Pointer to wifi_ipc_t struct to bind IPC RX mailbox to.
- * @param[in] ipc_inst : Pointer to the IPC instance.
- * @param[in] rx_cb : Callback function to bind to data in received from RX mailbox.
- * @param[in] priv : Private data to the callback function.
- * @return : wifi_ipc_status_ok if successful, otherwise wifi_ipc_status_init_err.
- */
-wifi_ipc_status_t wifi_ipc_bind_ipc_service_tx_rx(wifi_ipc_t *p_tx, wifi_ipc_t *p_rx,
-						  const ipc_device_wrapper_t *ipc_inst,
-						  void (*rx_cb)(void *data, void *priv),
-						  void *priv);
-
-/**
- * Get data from the free queue.
- *
- * @param[in] p_context : Pointer to wifi_ipc_t struct.
- * @param[out] data : Pointer to the data to read to.
- * @return : wifi_ipc_status_ok if successful, otherwise wifi_ipc_status_freeq_empty.
- */
-wifi_ipc_status_t wifi_ipc_freeq_get(wifi_ipc_t *p_context, uint32_t *data);
-
-/**
- * Send data to the free queue.
- *
- * @param[in] p_context : Pointer to wifi_ipc_t struct.
- * @param[in] data : 32-bit data to send.
- * @return : wifi_ipc_status_ok if successful, otherwise wifi_ipc_status_freeq_full.
- */
-wifi_ipc_status_t wifi_ipc_freeq_send(wifi_ipc_t *p_context, uint32_t data);
-
-/**
- * Send data to the busy queue over IPC service, and pop the same data from the
- * free queue.
- *
- * @param[in] p_context : Pointer to wifi_ipc_t struct.
- * @param[in] data : Pointer to the data to send to.
- * @return : wifi_ipc_status_ok if successful, otherwise one of the following:
- *              - wifi_ipc_status_busyq_notready
- *              - wifi_ipc_status_busyq_full
- *              - wifi_ipc_status_busyq_critical_err
- *              - wifi_ipc_status_freeq_invalid
- *              - wifi_ipc_status_freeq_empty
- */
-wifi_ipc_status_t wifi_ipc_busyq_send(wifi_ipc_t *p_context, uint32_t *data);
-
-/**
- * Prepares and initialises the Host for sending a command to RPU.
- *
- * The free queue points to the already allocated free queue from the RPU.
- *
- * The busy queue using IPC service must be initialised using @see wifi_ipc_bind_ipc_service()
- * or @see wifi_ipc_bind_ipc_service_tx_rx().
- *
- * @param[in] p_context : Pointer to wifi_ipc_t struct.
- * @param[in] addr_freeq : Address of the allocated free queue.
- * @return : wifi_ipc_status_ok if successful.
- */
-wifi_ipc_status_t wifi_ipc_host_cmd_init(wifi_ipc_t *p_context, uint32_t addr_freeq);
-
-/**
- * Prepares and initialises the Host for receiving an event from RPU.
- *
- * The free queue points to the already allocated free queue from the RPU.
- *
- * The busy queue using IPC service must be initialised using @see wifi_ipc_bind_ipc_service()
- * or @see wifi_ipc_bind_ipc_service_tx_rx().
- *
- * @param[in] p_context : Pointer to wifi_ipc_t struct.
- * @param[in] addr_freeq : Address of the allocated SPSC free queue.
- * @return : wifi_ipc_status_ok if successful.
- */
-wifi_ipc_status_t wifi_ipc_host_event_init(wifi_ipc_t *p_context, uint32_t addr_freeq);
-
-/**
- * Get a command location from the free queue.
- *
- * @param[in] p_context : Pointer to wifi_ipc_t struct.
- * @param[out] p_data : Pointer to data to write event location to.
- * @return : wifi_ipc_status_ok if successful, otherwise wifi_ipc_status_freeq_empty.
- */
-wifi_ipc_status_t wifi_ipc_host_cmd_get(wifi_ipc_t *p_context, uint32_t *p_data);
-
-/**
- * Send an event location pointer to the Host and frees up the event location
- * pointer from the free queue.
- *
- * @param[in] p_context : Pointer to wifi_ipc_t struct.
- * @param[in] p_data : Pointer to command location to be sent.
- * @return : wifi_ipc_status_ok if successful, otherwise one of the following
- *              - wifi_ipc_status_busyq_notready
- *              - wifi_ipc_status_busyq_full
- *              - wifi_ipc_status_busyq_critical_err
- *              - wifi_ipc_status_freeq_invalid
- *              - wifi_ipc_status_freeq_empty
- */
-wifi_ipc_status_t wifi_ipc_host_cmd_send(wifi_ipc_t *p_context, uint32_t *p_data);
-
-/**
- * Send a command from the Host to RPU using standard memcpy.
- *
- * 1. Retrieves an address pointer of Packet RAM from the free queue.
- * 2. Copies local message to the retrieved address pointer via memcpy.
- * 3. Sends the address pointer to the busy queue via IPC service.
- * 4. Upon successful transmission, removes the address pointer the free queue.
- *
- * @param[in] p_context : Pointer to wifi_ipc_t struct.
- * @param[in] p_msg : Pointer the local message to be copied to Packet RAM via memcpy.
- * @param[in] len : Length of the local message in bytes.
- * @return : wifi_ipc_status_ok if send is successful, otherwise one of
- *           status code from wifi_ipc_status_t will be returned.
- */
-wifi_ipc_status_t wifi_ipc_host_cmd_send_memcpy(wifi_ipc_t *p_context, const void *p_msg,
-						size_t len);
-
-/**
- * Send a tx data pointer from the Host to RPU and raises RPU interrupt.
- *
- * @param[in] p_context : Pointer to wifi_ipc_t struct.
- * @param[in] p_msg : Pointer to message.
- * @return : wifi_ipc_status_ok if send is successful, otherwise one of
- *           status code from wifi_ipc_status_t will be returned.
- */
-wifi_ipc_status_t wifi_ipc_host_tx_send(wifi_ipc_t *p_context, const void *p_msg);
-
-#endif /* IPC_SERVICE_H */
diff --git a/modules/nrf_wifi/bus/rpu_hw_if.c b/modules/nrf_wifi/bus/rpu_hw_if.c
index 8b9393f6f2e..5dd71a86de2 100644
--- a/modules/nrf_wifi/bus/rpu_hw_if.c
+++ b/modules/nrf_wifi/bus/rpu_hw_if.c
@@ -239,8 +239,8 @@ static int rpu_pwron(void)
 		gpio_pin_set_dt(&bucken_spec, 0);
 		return ret;
 	}
-	/* Settling time for iovdd nRF7002 DK/EK - switch (TCK106AG): ~600us */
-	k_msleep(1);
+	/* Settling time for IOVDD */
+	k_msleep(DT_PROP(NRF7002_NODE, iovdd_power_up_delay_ms));
 
 	if ((bucken_spec.port == iovdd_ctrl_spec.port) &&
 	    (bucken_spec.pin == iovdd_ctrl_spec.pin)) {
diff --git a/modules/nrf_wifi/bus/spsc_qm.c b/modules/nrf_wifi/bus/spsc_qm.c
deleted file mode 100644
index 01da1b5e897..00000000000
--- a/modules/nrf_wifi/bus/spsc_qm.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright (c) 2025 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @brief File containing API definitions for the
- * SPSC queue management layer of the nRF71 Wi-Fi driver.
- */
-#include <zephyr/kernel.h>
-#include <zephyr/logging/log.h>
-
-LOG_MODULE_DECLARE(wifi_nrf_bus, CONFIG_WIFI_NRF70_BUSLIB_LOG_LEVEL);
-
-#include "spsc_qm.h"
-
-spsc_queue_t *spsc32_init(uint32_t address, size_t size)
-{
-	return spsc_pbuf_init((void *)address, size, 0);
-}
-
-bool spsc32_push(spsc_queue_t *queue, uint32_t value)
-{
-	char *pbuf;
-	uint8_t len = sizeof(uint32_t);
-
-	if (spsc_pbuf_alloc(queue, len, &pbuf) != len) {
-		LOG_ERR("%s: Failed to allocate buffer", __func__);
-		return false;
-	}
-
-	memcpy(pbuf, &value, len);
-	spsc_pbuf_commit(queue, len);
-
-	return true;
-}
-
-bool spsc32_pop(spsc_queue_t *queue, uint32_t *out_value)
-{
-	char *buf;
-	uint16_t plen = spsc_pbuf_claim(queue, &buf);
-
-	if (plen == 0) {
-		LOG_ERR("%s: Failed to claim buffer", __func__);
-		return false;
-	}
-
-	spsc_pbuf_free(queue, plen);
-
-	*out_value = *((uint32_t *)buf);
-
-	return true;
-}
-
-bool spsc32_read_head(spsc_queue_t *queue, uint32_t *out_value)
-{
-	char *buf;
-	uint16_t plen = spsc_pbuf_claim(queue, &buf);
-
-	if (plen == 0) {
-		LOG_ERR("%s: Failed to claim buffer", __func__);
-		return false;
-	}
-
-	*out_value = *((uint32_t *)buf);
-
-	return true;
-}
-
-bool spsc32_is_empty(spsc_queue_t *queue)
-{
-	char *buf;
-
-	return spsc_pbuf_claim(queue, &buf) == 0;
-}
-
-bool spsc32_is_full(spsc_queue_t *queue)
-{
-	char *pbuf;
-	uint8_t len = sizeof(uint32_t);
-
-	return spsc_pbuf_alloc(queue, len, &pbuf) != len;
-}
diff --git a/modules/nrf_wifi/bus/spsc_qm.h b/modules/nrf_wifi/bus/spsc_qm.h
deleted file mode 100644
index 063cb470b52..00000000000
--- a/modules/nrf_wifi/bus/spsc_qm.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright (c) 2025 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @brief File containing API definitions for the
- * SPSC queue management layer of the nRF71 Wi-Fi driver.
-
- * SPSC Queue Manager API for handling 32-bit values.
- *
- * The Queue Manager API for Single-Producer, Single-Consumer (SPSC) queue. This
- * API allows queues to be allocated, pushed and popped.
- */
-
-#ifndef SPSC_QM_H
-#define SPSC_QM_H
-
-#include <zephyr/sys/spsc_pbuf.h>
-
-#include <stdint.h>
-#include <stdbool.h>
-
-typedef struct spsc_pbuf spsc_queue_t;
-
-/**
- * Initialise and allocate SPSC queue.
- *
- * @param[in] address : Address to allocate.
- * @param[in] size : Size in bytes to allocate.
- * @return : SPSC packet queue.
- */
-spsc_queue_t *spsc32_init(uint32_t address, size_t size);
-
-/**
- * Push a value onto the tail of a queue.
- *
- * @param[in] pb : Pointer to SPSC packet queue.
- * @param[in] value : The value to push to the queue.
- * @return : true if push is successful, false otherwise.
- */
-bool spsc32_push(spsc_queue_t *pb, uint32_t value);
-
-/**
- * Pop a value from the head of a queue and return it.
- *
- * @param[in] pb : Pointer to SPSC packet queue.
- * @param[out] out_value : Pointer to the value to pop to.
- * @return : true if pop is successful, false otherwise.
- */
-bool spsc32_pop(spsc_queue_t *pb, uint32_t *out_value);
-
-/**
- * Return a value at the head of a queue without popping it.
- *
- * @param[in] pb : Pointer to SPSC packet queue.
- * @param[out] out_value : Pointer to value to read from the head of the queue.
- * @return : true if read is successful, false otherwise.
- */
-bool spsc32_read_head(spsc_queue_t *pb, uint32_t *out_value);
-
-/**
- * Test whether a queue is empty.
- *
- * @param[in] pb : Pointer to SPSC packet queue.
- * @return : true if the queue is empty, false otherwise.
- */
-bool spsc32_is_empty(spsc_queue_t *pb);
-
-/**
- * Test whether a queue is full.
- *
- * @param[in] pb : Pointer to SPSC packet queue.
- * @return : true if the queue is full, false otherwise.
- */
-bool spsc32_is_full(spsc_queue_t *pb);
-
-#endif /* SPSC_QM_H */
diff --git a/modules/nrf_wifi/os/CMakeLists.txt b/modules/nrf_wifi/os/CMakeLists.txt
index ce1c9a850c8..e4f9cf2a0b6 100644
--- a/modules/nrf_wifi/os/CMakeLists.txt
+++ b/modules/nrf_wifi/os/CMakeLists.txt
@@ -15,13 +15,5 @@ zephyr_library_sources(
   timer.c
   work.c
 )
-zephyr_include_directories_ifdef(CONFIG_NRF71_ON_IPC
-  ${CMAKE_CURRENT_LIST_DIR}/../bus/
-  ${CMAKE_CURRENT_LIST_DIR}/../hw_if/hal/inc
-)
-
-zephyr_library_compile_definitions_ifdef(CONFIG_NRF71_ON_IPC
-  NRF71_ON_IPC
-)
 
 zephyr_library_link_libraries(nrf-wifi-osal)
diff --git a/modules/nrf_wifi/os/shim.c b/modules/nrf_wifi/os/shim.c
index b892d50df7f..997704b01bb 100644
--- a/modules/nrf_wifi/os/shim.c
+++ b/modules/nrf_wifi/os/shim.c
@@ -18,19 +18,14 @@
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/sys/__assert.h>
-#ifdef CONFIG_NRF71_ON_IPC
-#include "ipc_if.h"
-#else
 #include <zephyr/drivers/wifi/nrf_wifi/bus/rpu_hw_if.h>
 #include <zephyr/drivers/wifi/nrf_wifi/bus/qspi_if.h>
-#endif /* CONFIG_NRF71_ON_IPC */
 #include <zephyr/sys/math_extras.h>
 
 #include "shim.h"
 #include "work.h"
 #include "timer.h"
 #include "osal_ops.h"
-#include "common/hal_structs_common.h"
 
 LOG_MODULE_REGISTER(wifi_nrf, CONFIG_WIFI_NRF70_LOG_LEVEL);
 #if defined(CONFIG_NOCACHE_MEMORY)
@@ -127,7 +122,6 @@ static int zep_shim_mem_cmp(const void *addr1,
 	return memcmp(addr1, addr2, size);
 }
 
-#ifndef CONFIG_NRF71_ON_IPC
 static unsigned int zep_shim_qspi_read_reg32(void *priv, unsigned long addr)
 {
 	unsigned int val;
@@ -180,7 +174,6 @@ static void zep_shim_qspi_cpy_to(void *priv, unsigned long addr, const void *src
 
 	dev->write(addr, src, count_aligned);
 }
-#endif /* !CONFIG_NRF71_ON_IPC */
 
 static void *zep_shim_spinlock_alloc(void)
 {
@@ -814,56 +807,14 @@ static enum nrf_wifi_status zep_shim_bus_qspi_dev_init(void *os_qspi_dev_ctx)
 static void zep_shim_bus_qspi_dev_deinit(void *priv)
 {
 	struct zep_shim_bus_qspi_priv *qspi_priv = priv;
-#ifndef CONFIG_NRF71_ON_IPC
 	volatile struct qspi_dev *dev = qspi_priv->qspi_dev;
-#else
-	volatile struct rpu_dev *dev = qspi_priv->qspi_dev;
-#endif /* !CONFIG_NRF71_ON_IPC */
-	dev->deinit();
-}
 
-#ifdef CONFIG_NRF71_ON_IPC
-static int ipc_send_msg(unsigned int msg_type, void *msg, unsigned int len)
-{
-	enum nrf_wifi_status status = NRF_WIFI_STATUS_FAIL;
-	struct rpu_dev *dev = rpu_dev();
-	int ret;
-	ipc_ctx_t ctx;
-
-	switch (msg_type) {
-	case NRF_WIFI_HAL_MSG_TYPE_CMD_CTRL:
-		ctx.inst = IPC_INSTANCE_CMD_CTRL;
-		ctx.ept = IPC_EPT_UMAC;
-		break;
-	case NRF_WIFI_HAL_MSG_TYPE_CMD_DATA_TX:
-		ctx.inst = IPC_INSTANCE_CMD_TX;
-		ctx.ept = IPC_EPT_UMAC;
-		break;
-	case NRF_WIFI_HAL_MSG_TYPE_CMD_DATA_RX:
-		ctx.inst = IPC_INSTANCE_RX;
-		ctx.ept = IPC_EPT_LMAC;
-		break;
-	default:
-		nrf_wifi_osal_log_err("%s: Invalid msg_type (%d)", __func__, msg_type);
-		goto out;
-	};
-
-	ret = dev->send(ctx, msg, len);
-	if (ret < 0) {
-		nrf_wifi_osal_log_err("%s: Sending message to RPU failed\n", __func__);
-		goto out;
-	}
-
-	status = NRF_WIFI_STATUS_SUCCESS;
-out:
-	return status;
+	dev->deinit();
 }
-#endif /*  CONFIG_NRF71_ON_IPC */
 
 static void *zep_shim_bus_qspi_dev_add(void *os_qspi_priv, void *osal_qspi_dev_ctx)
 {
 	struct zep_shim_bus_qspi_priv *zep_qspi_priv = os_qspi_priv;
-#ifndef CONFIG_NRF71_ON_IPC
 	struct qspi_dev *dev = qspi_dev();
 	int ret;
 	enum nrf_wifi_status status;
@@ -885,11 +836,6 @@ static void *zep_shim_bus_qspi_dev_add(void *os_qspi_priv, void *osal_qspi_dev_c
 		LOG_ERR("%s: RPU enable failed with error %d", __func__, ret);
 		return NULL;
 	}
-#else
-	struct rpu_dev *dev = rpu_dev();
-
-	dev->init();
-#endif /* !CONFIG_NRF71_ON_IPC */
 	zep_qspi_priv->qspi_dev = dev;
 	zep_qspi_priv->dev_added = true;
 
@@ -903,10 +849,8 @@ static void zep_shim_bus_qspi_dev_rem(void *priv)
 
 	ARG_UNUSED(dev);
 
-#ifndef CONFIG_NRF71_ON_IPC
 	/* TODO: Make qspi_dev a dynamic instance and remove it here */
 	rpu_disable();
-#endif /* !CONFIG_NRF71_ON_IPC */
 }
 
 static void *zep_shim_bus_qspi_init(void)
@@ -964,7 +908,6 @@ static void zep_shim_bus_qspi_dev_host_map_get(void *os_qspi_dev_ctx,
 	host_map->addr = 0;
 }
 
-#ifndef CONFIG_NRF71_ON_IPC
 static void irq_work_handler(struct k_work *work)
 {
 	int ret = 0;
@@ -997,8 +940,6 @@ static void zep_shim_irq_handler(const struct device *dev, struct gpio_callback
 	k_work_schedule_for_queue(&zep_wifi_intr_q, &intr_priv->work, K_NO_WAIT);
 }
 
-#endif /* !CONFIG_NRF71_ON_IPC */
-
 static enum nrf_wifi_status zep_shim_bus_qspi_intr_reg(void *os_dev_ctx, void *callbk_data,
 						       int (*callbk_fn)(void *callbk_data))
 {
@@ -1007,14 +948,6 @@ static enum nrf_wifi_status zep_shim_bus_qspi_intr_reg(void *os_dev_ctx, void *c
 
 	ARG_UNUSED(os_dev_ctx);
 
-#ifdef CONFIG_NRF71_ON_IPC
-	ret = ipc_register_rx_cb(callbk_fn, callbk_data);
-	if (ret) {
-		LOG_ERR("%s: ipc_register_rx_cb failed\n", __func__);
-		goto out;
-	}
-	status = NRF_WIFI_STATUS_SUCCESS;
-#else
 	intr_priv = zep_shim_mem_zalloc(sizeof(*intr_priv));
 
 	if (!intr_priv) {
@@ -1037,20 +970,18 @@ static enum nrf_wifi_status zep_shim_bus_qspi_intr_reg(void *os_dev_ctx, void *c
 	}
 
 	status = NRF_WIFI_STATUS_SUCCESS;
-#endif /* CONFIG_NRF71_ON_IPC */
+
 out:
 	return status;
 }
 
 static void zep_shim_bus_qspi_intr_unreg(void *os_qspi_dev_ctx)
 {
-#ifndef CONFIG_NRF71_ON_IPC
 	struct k_work_sync sync;
 	int ret;
-#endif /* !CONFIG_NRF71_ON_IPC */
 
 	ARG_UNUSED(os_qspi_dev_ctx);
-#ifndef CONFIG_NRF71_ON_IPC
+
 	ret = rpu_irq_remove(&intr_priv->gpio_cb_data);
 	if (ret) {
 		LOG_ERR("%s: rpu_irq_remove failed", __func__);
@@ -1061,7 +992,6 @@ static void zep_shim_bus_qspi_intr_unreg(void *os_qspi_dev_ctx)
 
 	zep_shim_mem_free(intr_priv);
 	intr_priv = NULL;
-#endif /*! CONFIG_NRF71_ON_IPC */
 }
 
 #ifdef CONFIG_NRF_WIFI_LOW_POWER
@@ -1142,12 +1072,12 @@ const struct nrf_wifi_osal_ops nrf_wifi_os_zep_ops = {
 	.mem_cpy = zep_shim_mem_cpy,
 	.mem_set = zep_shim_mem_set,
 	.mem_cmp = zep_shim_mem_cmp,
-#ifndef CONFIG_NRF71_ON_IPC
+
 	.qspi_read_reg32 = zep_shim_qspi_read_reg32,
 	.qspi_write_reg32 = zep_shim_qspi_write_reg32,
 	.qspi_cpy_from = zep_shim_qspi_cpy_from,
 	.qspi_cpy_to = zep_shim_qspi_cpy_to,
-#endif /* CONFIG_NRF71_ON_IPC */
+
 	.spinlock_alloc = zep_shim_spinlock_alloc,
 	.spinlock_free = zep_shim_spinlock_free,
 	.spinlock_init = zep_shim_spinlock_init,
@@ -1227,9 +1157,7 @@ const struct nrf_wifi_osal_ops nrf_wifi_os_zep_ops = {
 	.bus_qspi_ps_wake = zep_shim_bus_qspi_ps_wake,
 	.bus_qspi_ps_status = zep_shim_bus_qspi_ps_status,
 #endif /* CONFIG_NRF_WIFI_LOW_POWER */
+
 	.assert = zep_shim_assert,
 	.strlen = zep_shim_strlen,
-#ifdef CONFIG_NRF71_ON_IPC
-	.ipc_send_msg = ipc_send_msg,
-#endif /* CONFIG_NRF71_ON_IPC */
 };
diff --git a/modules/openthread/Kconfig b/modules/openthread/Kconfig
index 4ff059de486..27832a581e1 100644
--- a/modules/openthread/Kconfig
+++ b/modules/openthread/Kconfig
@@ -3,11 +3,323 @@
 
 config OPENTHREAD
 	bool "OpenThread Support"
+	imply FLASH
+	imply FLASH_MAP
+	imply MPU_ALLOW_FLASH_WRITE
+
+	select SETTINGS if FLASH
+	select OPENTHREAD_SETTINGS_RAM if !FLASH
+	select CPP
+	select REBOOT
+	select ENTROPY_GENERATOR
 	help
 	  This option enables the OpenThread library
 
 if OPENTHREAD
 
+choice OPENTHREAD_IMPLEMENTATION
+	prompt "OpenThread origin selection"
+	help
+	  Select OpenThread stack to use for build. Custom OpenThread implementations
+	  can be added to the application Kconfig.
+
+config OPENTHREAD_SOURCES
+	bool "OpenThread from sources"
+	help
+	  Build Zephyr's OpenThread port from sources.
+
+endchoice
+
+config OPENTHREAD_MANUAL_START
+	bool "Start OpenThread stack manually"
+	help
+	  If enabled, OpenThread stack will have to be configured and
+	  started manually, with respective API calls or CLI/NCP commands.
+	  Otherwise, OpenThread will configure the network parameters and try to
+	  join the Thread network automatically during initialization (using
+	  credentials stored in persistent storage, obtained during
+	  commissioning or pre-commissioned with other Kconfig options,
+	  depending on configuration used).
+
+menu "Logging"
+
+menuconfig OPENTHREAD_DEBUG
+	bool "OpenThread stack logging support"
+	help
+	  This option enables logging support for OpenThread.
+
+choice OPENTHREAD_LOG_LEVEL_CHOICE
+	prompt "OpenThread stack log level"
+	depends on OPENTHREAD_DEBUG
+	help
+	  This option selects log level for OpenThread stack.
+
+config OPENTHREAD_LOG_LEVEL_CRIT
+	bool "Critical"
+config OPENTHREAD_LOG_LEVEL_WARN
+	bool "Warning"
+config OPENTHREAD_LOG_LEVEL_NOTE
+	bool "Notice"
+config OPENTHREAD_LOG_LEVEL_INFO
+	bool "Informational"
+config OPENTHREAD_LOG_LEVEL_DEBG
+	bool "Debug"
+endchoice # OPENTHREAD_LOG_LEVEL_CHOICE
+
+config OPENTHREAD_LOG_LEVEL
+	int
+	default 1 if OPENTHREAD_LOG_LEVEL_CRIT
+	default 2 if OPENTHREAD_LOG_LEVEL_WARN
+	default 3 if OPENTHREAD_LOG_LEVEL_NOTE
+	default 4 if OPENTHREAD_LOG_LEVEL_INFO
+	default 5 if OPENTHREAD_LOG_LEVEL_DEBG
+	default 0
+	help
+	  Log level for OpenThread stack.
+
+config OPENTHREAD_PLATFORM_LOG_LEVEL
+	int
+	default 1 if OPENTHREAD_LOG_LEVEL_CRIT
+	default 2 if OPENTHREAD_LOG_LEVEL_WARN
+	default 3 if OPENTHREAD_LOG_LEVEL_NOTE || OPENTHREAD_LOG_LEVEL_INFO
+	default 4 if OPENTHREAD_LOG_LEVEL_DEBG
+	default 0
+	help
+	  Log level for OpenThread Zephyr platform.
+
+endmenu # "Logging"
+
+menu "Zephyr optimizations"
+
+config OPENTHREAD_THREAD_PREEMPTIVE
+	bool "Set Openthread thread to be preemptive"
+
+config OPENTHREAD_THREAD_PRIORITY
+	int "OpenThread thread priority"
+	default 0 if OPENTHREAD_THREAD_PREEMPTIVE
+	default 8
+
+config OPENTHREAD_THREAD_STACK_SIZE
+	int "OpenThread thread stack size"
+	default 6144 if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER
+	default 6240 if (OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER) && MPU_STACK_GUARD && FPU_SHARING && CPU_CORTEX_M
+	default 3168 if MPU_STACK_GUARD && FPU_SHARING && CPU_CORTEX_M
+	default 3072
+
+
+config OPENTHREAD_PKT_LIST_SIZE
+	int "List size for IPv6 packet buffering"
+	default 10
+
+config OPENTHREAD_RADIO_WORKQUEUE_STACK_SIZE
+	int "OpenThread radio transmit workqueue stack size"
+	default 608 if MPU_STACK_GUARD && FPU_SHARING && CPU_CORTEX_M
+	default 512
+
+endmenu # "Zephyr optimizations"
+
+
+config OPENTHREAD_SHELL
+	bool "OpenThread shell"
+	depends on SHELL
+
+config MBEDTLS_PROMPTLESS
+	bool
+	default y if !CUSTOM_OPENTHREAD_SECURITY
+
+choice OPENTHREAD_SECURITY
+	prompt "OpenThread security"
+	default OPENTHREAD_MBEDTLS_CHOICE
+
+config CUSTOM_OPENTHREAD_SECURITY
+	bool "Custom"
+	help
+	  Security settings will be controlled directly by the user.
+	  Enabling this setting will give access to full control of mbed TLS
+	  configuration.
+
+config OPENTHREAD_MBEDTLS_CHOICE
+	bool "mbed TLS built-in"
+	select OPENTHREAD_MBEDTLS
+	help
+	  Use the OpenThread mbed TLS configuration pre-defined security scheme.
+
+endchoice
+
+config OPENTHREAD_MBEDTLS
+	bool
+	select MBEDTLS
+	select MBEDTLS_ENABLE_HEAP
+	select MBEDTLS_CIPHER_AES_ENABLED
+	select MBEDTLS_CIPHER_CCM_ENABLED
+	select MBEDTLS_SHA256
+	select MBEDTLS_ENTROPY_C
+	select MBEDTLS_CMAC
+	select MBEDTLS_CIPHER
+	select MBEDTLS_MD
+	select MBEDTLS_TLS_VERSION_1_2 if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER
+	select MBEDTLS_DTLS if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER
+	select MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER
+	select MBEDTLS_ECJPAKE_C if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER
+	select MBEDTLS_ECP_DP_SECP256R1_ENABLED if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER || \
+	    OPENTHREAD_SRP_CLIENT || OPENTHREAD_SRP_SERVER
+	select MBEDTLS_ECP_NIST_OPTIM if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER
+	select MBEDTLS_CTR_DRBG_ENABLED if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER
+	select MBEDTLS_HMAC_DRBG_ENABLED if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER || \
+	    OPENTHREAD_SRP_CLIENT || OPENTHREAD_SRP_SERVER
+	select MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED if OPENTHREAD_ECDSA
+	select MBEDTLS_ECDH_C if OPENTHREAD_ECDSA
+	select MBEDTLS_ECDSA_C if OPENTHREAD_ECDSA
+	select MBEDTLS_ECDSA_DETERMINISTIC if OPENTHREAD_ECDSA
+	select MBEDTLS_PK_WRITE_C if OPENTHREAD_ECDSA
+	select MBEDTLS_ECP_C if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER || OPENTHREAD_ECDSA
+
+
+config OPENTHREAD_MBEDTLS_LIB_NAME
+	string "mbedtls lib name"
+	default "mbedTLS"
+	help
+	  This option allows to specify one or more mbedtls library files to be
+	  linked with OpenThread. Separate multiple values with space " ".
+
+config OPENTHREAD_COPROCESSOR
+	bool "OpenThread Co-Processor"
+	select OPENTHREAD_MANUAL_START
+	select RING_BUFFER
+	select UART_INTERRUPT_DRIVEN
+	help
+	  Enable Co-Processor in OpenThread stack.
+
+if OPENTHREAD_COPROCESSOR
+
+choice OPENTHREAD_COPROCESSOR_CHOICE
+	prompt "OpenThread Co-Processor type"
+	help
+	  This option selects Thread network co-processor type
+
+config OPENTHREAD_COPROCESSOR_NCP
+	bool "NCP - Network Co-Processor"
+config OPENTHREAD_COPROCESSOR_RCP
+	bool "RCP - Radio Co-Processor"
+endchoice # OPENTHREAD_COPROCESSOR_CHOICE
+
+config OPENTHREAD_COPROCESSOR_UART_RING_BUFFER_SIZE
+	int "Set Co-Processor UART ring buffer size"
+	default 4096
+	help
+	  TX buffer size for the OpenThread Co-Processor UART.
+
+config OPENTHREAD_COPROCESSOR_VENDOR_HOOK_SOURCE
+	string "Path to vendor hook source file"
+	help
+	  Provides path to compile vendor hook file.
+
+endif # OPENTHREAD_COPROCESSOR
+
+config OPENTHREAD_PLATFORM_INFO
+	string "Platform information for OpenThread"
+	default "ZEPHYR"
+	help
+	  Platform information for OpenThread
+
+config OPENTHREAD_CUSTOM_PARAMETERS
+	string "Custom Parameters to pass to OpenThread build system"
+	default ""
+	help
+	  This option is intended for advanced users only.
+	  Pass additional parameters that do not have corresponding Kconfig
+	  options to the OpenThread build system. Separate multiple values with
+	  space " ", for example:
+	  "OPENTHREAD_CONFIG_JOINER_ENABLE=1 OPENTHREAD_CONFIG_JOINER_MAX_CANDIDATES=3"
+
+config OPENTHREAD_NUM_MESSAGE_BUFFERS
+	int "The number of message buffers in the buffer pool"
+	default 128
+	help
+	  "The number of message buffers in the buffer pool."
+
+config OPENTHREAD_MESSAGE_BUFFER_SIZE
+	int "The size of a message buffer in bytes"
+	default 128
+	help
+	  "The size of a message buffer in bytes"
+
+config OPENTHREAD_PLATFORM_MESSAGE_MANAGEMENT
+	bool "Use platform message management"
+	help
+	  The message pool is managed by platform defined logic.
+
+config OPENTHREAD_MAX_STATECHANGE_HANDLERS
+	int "The maximum number of state-changed callback handlers"
+	default 2
+	help
+	  The maximum number of state-changed callback handlers
+	  set using otSetStateChangedCallback.
+
+config OPENTHREAD_TMF_ADDRESS_CACHE_ENTRIES
+	int "The number of EID-to-RLOC cache entries"
+	default 20
+	help
+	  The number of EID-to-RLOC cache entries.
+
+config OPENTHREAD_TMF_ADDRESS_CACHE_MAX_SNOOP_ENTRIES
+	int "The maximum number of EID-to-RLOC cache entries"
+	default 2
+	help
+	  The maximum number of EID-to-RLOC cache entries that can be used for
+	  "snoop optimization" where an entry is created by inspecting a received
+	  message.
+
+config OPENTHREAD_LOG_PREPEND_LEVEL_ENABLE
+	bool "Prepending the log level to all OpenThread log messages"
+	help
+	  When enabled the OpenThread logs will be prepended with the appropriate
+	  log level prefix i.e. [CRIT], [WARN], [NOTE], [INFO], [DEBG].
+
+config OPENTHREAD_MAC_SOFTWARE_ACK_TIMEOUT_ENABLE
+	bool "Software ACK timeout logic"
+	default y
+	help
+	  Set y if the radio supports AckTime event
+
+config OPENTHREAD_MAC_SOFTWARE_RETRANSMIT_ENABLE
+	bool "Software retransmission logic"
+	default y
+	help
+	  Set y if the radio supports tx retry logic with collision avoidance (CSMA)
+
+config OPENTHREAD_MAC_SOFTWARE_CSMA_BACKOFF_ENABLE
+	bool "Software CSMA backoff logic"
+	default y
+	help
+	  Set y to enable software CSMA backoff. The option can be disabled if
+	  the radio has hardware support for this feature (IEEE802154_HW_CSMA).
+
+config OPENTHREAD_CRYPTO_PSA
+	bool "ARM PSA crypto API"
+	depends on MBEDTLS_PSA_CRYPTO_CLIENT
+	select OPENTHREAD_PLATFORM_KEY_REF if !OPENTHREAD_COPROCESSOR_RCP
+	imply OPENTHREAD_PLATFORM_KEYS_EXPORTABLE_ENABLE
+	help
+	  Enable crypto backend library implementation based on ARM PSA crypto
+	  API instead of the default, using mbedTLS.
+
+config OPENTHREAD_PLATFORM_KEYS_EXPORTABLE_ENABLE
+	bool "Make MAC keys exportable"
+	depends on OPENTHREAD_PLATFORM_KEY_REF
+	help
+	  Enable the creation of exportable MAC keys in the OpenThread Key Manager.
+
+config OPENTHREAD_INTERFACE_EARLY_UP
+	bool "Make OpenThread interface ready as soon as Thread is enabled"
+	help
+	  When enabled, OpenThread interface will be marked ready (operational
+	  UP) as soon as Thread has been enabled. This means the interface will
+	  be ready to transmit application packets during the Mesh Link
+	  Establishment phase.
+	  Otherwise, OpenThread interface will be marked operational UP only
+	  after the device joins a Thread network.
+
 menu "OpenThread stack features"
 rsource "Kconfig.features"
 endmenu
diff --git a/modules/openthread/platform/crypto_psa.c b/modules/openthread/platform/crypto_psa.c
index 6ad286f3734..bab1afbd7e9 100644
--- a/modules/openthread/platform/crypto_psa.c
+++ b/modules/openthread/platform/crypto_psa.c
@@ -226,7 +226,7 @@ otError otPlatCryptoHmacSha256Init(otCryptoContext *aContext)
 	}
 
 	operation = aContext->mContext;
-	*operation = psa_mac_operation_init();
+	memset(operation, 0, sizeof(*operation));
 
 	return OT_ERROR_NONE;
 }
@@ -347,7 +347,7 @@ otError otPlatCryptoSha256Init(otCryptoContext *aContext)
 	}
 
 	operation = aContext->mContext;
-	*operation = psa_hash_operation_init();
+	memset(operation, 0, sizeof(*operation));
 
 	return OT_ERROR_NONE;
 }
diff --git a/modules/openthread/platform/diag.c b/modules/openthread/platform/diag.c
index 79f4e38984a..3bd4b549536 100644
--- a/modules/openthread/platform/diag.c
+++ b/modules/openthread/platform/diag.c
@@ -90,10 +90,16 @@ otError otPlatDiagProcess(otInstance *aInstance, uint8_t aArgsLength, char *aArg
 
 void otPlatDiagModeSet(bool aMode)
 {
+	otError error;
+
 	sDiagMode = aMode;
 
 	if (!sDiagMode) {
-		otPlatRadioSleep(NULL);
+		error = otPlatRadioSleep(NULL);
+		if (error != OT_ERROR_NONE) {
+			otPlatLog(OT_LOG_LEVEL_WARN, OT_LOG_REGION_PLATFORM,
+				  "%s failed (%d)", "otPlatRadioSleep", error);
+		}
 	}
 }
 
@@ -345,6 +351,7 @@ static otError startModCarrier(otInstance *aInstance, uint8_t aArgsLength, char
 void otPlatDiagAlarmCallback(otInstance *aInstance)
 {
 	uint32_t now;
+	otError error;
 	otRadioFrame *txPacket;
 	const uint16_t diag_packet_len = 30;
 
@@ -370,7 +377,11 @@ void otPlatDiagAlarmCallback(otInstance *aInstance)
 				txPacket->mPsdu[i] = i;
 			}
 
-			otPlatRadioTransmit(aInstance, txPacket);
+			error = otPlatRadioTransmit(aInstance, txPacket);
+			if (error != OT_ERROR_NONE) {
+				otPlatLog(OT_LOG_LEVEL_WARN, OT_LOG_REGION_PLATFORM,
+					  "%s failed (%d)", "otPlatRadioTransmit", error);
+			}
 
 			if (sTxCount != -1) {
 				sTxCount--;
@@ -405,8 +416,11 @@ static otError processTransmit(otInstance *aInstance, uint8_t aArgsLength, char
 		otPlatAlarmMilliStop(aInstance);
 		diag_output("diagnostic message transmission is stopped\r\n");
 		sTransmitMode = DIAG_TRANSMIT_MODE_IDLE;
-		otPlatRadioReceive(aInstance, sChannel);
-
+		error = otPlatRadioReceive(aInstance, sChannel);
+		if (error != OT_ERROR_NONE) {
+			otPlatLog(OT_LOG_LEVEL_WARN, OT_LOG_REGION_PLATFORM,
+				  "%s failed (%d)", "otPlatRadioReceive", error);
+		}
 	} else if (strcmp(aArgs[0], "start") == 0) {
 		if (sTransmitMode != DIAG_TRANSMIT_MODE_IDLE) {
 			return OT_ERROR_INVALID_STATE;
diff --git a/modules/openthread/platform/platform-zephyr.h b/modules/openthread/platform/platform-zephyr.h
index d6dd26adea0..7671729208e 100644
--- a/modules/openthread/platform/platform-zephyr.h
+++ b/modules/openthread/platform/platform-zephyr.h
@@ -117,4 +117,4 @@ int notify_new_rx_frame(struct net_pkt *pkt);
  */
 int notify_new_tx_frame(struct net_pkt *pkt);
 
-#endif  /* PLATFORM_POSIX_H_ */
+#endif /* PLATFORM_ZEPHYR_H_ */
diff --git a/modules/segger/CMakeLists.txt b/modules/segger/CMakeLists.txt
index dcccd4d4ecc..5b3181743e2 100644
--- a/modules/segger/CMakeLists.txt
+++ b/modules/segger/CMakeLists.txt
@@ -1,5 +1,6 @@
 if(CONFIG_USE_SEGGER_RTT)
   zephyr_library()
+  zephyr_library_compile_definitions(SEGGER_RTT_ALIGNMENT=CONFIG_SEGGER_RTT_CB_ALIGNMENT)
   set(SEGGER_DIR ${ZEPHYR_CURRENT_MODULE_DIR})
   zephyr_include_directories_ifdef(CONFIG_USE_SEGGER_RTT
     ${SEGGER_DIR}/SEGGER
@@ -12,6 +13,8 @@ if(CONFIG_USE_SEGGER_RTT)
   zephyr_library_sources_ifdef(CONFIG_SEGGER_SYSTEMVIEW ${SEGGER_DIR}/SEGGER/SEGGER_SYSVIEW.c)
   # Using sort key AAA to ensure that we are placed at start of RAM
   zephyr_linker_sources_ifdef(CONFIG_SEGGER_RTT_SECTION_CUSTOM RAM_SECTIONS SORT_KEY aaa segger_rtt.ld)
+  zephyr_linker_section_ifdef(CONFIG_SEGGER_RTT_SECTION_CUSTOM NAME "rtt_buff_data" GROUP RAM_REGION ALIGN 4 NOINPUT)
+  zephyr_linker_section_configure(SECTION "rtt_buff_data" INPUT "${CONFIG_SEGGER_RTT_SECTION_CUSTOM_NAME}" SYMBOLS )
 endif()
 
 if(CONFIG_SEGGER_DEBUGMON)
diff --git a/modules/segger/Kconfig b/modules/segger/Kconfig
index bd19b00731e..ca2d27d4bcf 100644
--- a/modules/segger/Kconfig
+++ b/modules/segger/Kconfig
@@ -25,6 +25,14 @@ config SEGGER_RTT_CUSTOM_LOCKING
 	help
 	  Enable custom locking using Zephyr APIs.
 
+config SEGGER_RTT_CB_ALIGNMENT
+	int "Alignment of the RTT control block"
+	default 16
+	help
+	  Specify the alignment of the RTT control block in memory. The default
+	  alignment of 16 bytes is chosen because PyOCD fails to discover blocks
+	  where the 16 byte `acID` field falls across a 32 byte boundary.
+
 config SEGGER_RTT_MAX_NUM_UP_BUFFERS
 	int "Maximum number of up-buffers"
 	default 3
diff --git a/modules/tflite-micro/CMakeLists.txt b/modules/tflite-micro/CMakeLists.txt
index c0893a7d807..95301b34c79 100644
--- a/modules/tflite-micro/CMakeLists.txt
+++ b/modules/tflite-micro/CMakeLists.txt
@@ -41,9 +41,12 @@ if(CONFIG_TENSORFLOW_LITE_MICRO)
     ${TENSORFLOW_LITE_MICRO_DIR}/signal/src/kiss_fft_wrappers/kiss_fft_float.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/signal/src/kiss_fft_wrappers/kiss_fft_int16.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/signal/src/kiss_fft_wrappers/kiss_fft_int32.cc
+    ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/compiler/mlir/lite/core/api/error_reporter.cc
+    ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/compiler/mlir/lite/schema/schema_utils.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/array.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/core/c/common.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/debug_log.cc
+    ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/hexdump.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/fake_micro_context.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/memory_helpers.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/micro_allocation_info.cc
@@ -81,9 +84,7 @@ if(CONFIG_TENSORFLOW_LITE_MICRO)
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/kernels/internal/reference/portable_tensor_utils.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/kernels/kernel_util.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/core/api/flatbuffer_conversions.cc
-    ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/core/api/error_reporter.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/core/api/tensor_utils.cc
-    ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/schema/schema_utils.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/activations.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/activations_common.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/${CMSIS_NN_OPTIMIZED_KERNEL_DIR}/add.cc
@@ -91,7 +92,7 @@ if(CONFIG_TENSORFLOW_LITE_MICRO)
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/add_n.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/arg_min_max.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/assign_variable.cc
-    ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/batch_matmul.cc
+    ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/${CMSIS_NN_OPTIMIZED_KERNEL_DIR}/batch_matmul.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/batch_to_space_nd.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/broadcast_args.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/broadcast_to.cc
@@ -105,6 +106,8 @@ if(CONFIG_TENSORFLOW_LITE_MICRO)
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/${CMSIS_NN_OPTIMIZED_KERNEL_DIR}/conv.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/conv_common.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/cumsum.cc
+    ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/decompress.cc
+    ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/decompress_common.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/depth_to_space.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/${CMSIS_NN_OPTIMIZED_KERNEL_DIR}/depthwise_conv.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/depthwise_conv_common.cc
@@ -142,7 +145,7 @@ if(CONFIG_TENSORFLOW_LITE_MICRO)
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/lstm_eval.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/lstm_eval_common.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/log_softmax.cc
-    ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/maximum_minimum.cc
+    ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/${CMSIS_NN_OPTIMIZED_KERNEL_DIR}/maximum_minimum.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/micro_tensor_utils.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/mirror_pad.cc
     ${TENSORFLOW_LITE_MICRO_DIR}/tensorflow/lite/micro/kernels/${CMSIS_NN_OPTIMIZED_KERNEL_DIR}/mul.cc
diff --git a/modules/tflite-micro/Kconfig b/modules/tflite-micro/Kconfig
index 72789bd51de..99a49d6a633 100644
--- a/modules/tflite-micro/Kconfig
+++ b/modules/tflite-micro/Kconfig
@@ -28,6 +28,8 @@ config TENSORFLOW_LITE_MICRO_CMSIS_NN_KERNELS
 	select CMSIS_NN_SOFTMAX
 	select CMSIS_NN_SVD
 	select CMSIS_NN_LSTM
+	select CMSIS_NN_TRANSPOSE
+	select CMSIS_NN_PAD
 	help
 	  This option adds support for CMSIS-NN optimized kernels when using TensorFlow Lite Micro.
 
diff --git a/modules/thrift/src/thrift/server/TServerFramework.cpp b/modules/thrift/src/thrift/server/TServerFramework.cpp
index c5061fcaeac..678d70702d7 100644
--- a/modules/thrift/src/thrift/server/TServerFramework.cpp
+++ b/modules/thrift/src/thrift/server/TServerFramework.cpp
@@ -236,8 +236,7 @@ void TServerFramework::newlyConnectedClient(const shared_ptr<TConnectedClient> &
 	onClientConnected(pClient);
 }
 
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wdelete-non-virtual-dtor"
+TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_DELETE_NON_VIRTUAL_DTOR)
 void TServerFramework::disposeConnectedClient(TConnectedClient *pClient)
 {
 	onClientDisconnected(pClient);
@@ -248,7 +247,7 @@ void TServerFramework::disposeConnectedClient(TConnectedClient *pClient)
 		// mon_.notify();
 	}
 }
-#pragma GCC diagnostic pop
+TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_DELETE_NON_VIRTUAL_DTOR)
 
 } // namespace server
 } // namespace thrift
diff --git a/modules/trusted-firmware-m/CMakeLists.txt b/modules/trusted-firmware-m/CMakeLists.txt
index 3388389b034..ff4a3093fdc 100644
--- a/modules/trusted-firmware-m/CMakeLists.txt
+++ b/modules/trusted-firmware-m/CMakeLists.txt
@@ -18,6 +18,14 @@ set(TFM_VALID_PARTITIONS
 if (CONFIG_BUILD_WITH_TFM)
   # PSA API awareness for the Non-Secure application
   target_compile_definitions(app PRIVATE "TFM_PSA_API")
+
+  if(CONFIG_TFM_BL1)
+    list(APPEND TFM_CMAKE_ARGS -DBL1:BOOL=ON)
+    if(CONFIG_TFM_BL2_SIGNING_KEY_PATH)
+      list(APPEND TFM_CMAKE_ARGS -DTFM_BL2_SIGNING_KEY_PATH=${CONFIG_TFM_BL2_SIGNING_KEY_PATH})
+    endif()
+  endif()
+
   if (CONFIG_TFM_SFN)
     list(APPEND TFM_CMAKE_ARGS -DCONFIG_TFM_SPM_BACKEND="SFN")
   else() # CONFIG_TFM_IPC
@@ -162,6 +170,10 @@ if (CONFIG_BUILD_WITH_TFM)
     set(BL2_ELF_FILE ${TFM_BINARY_DIR}/bin/bl2.elf)
     set(BL2_BIN_FILE ${TFM_BINARY_DIR}/bin/bl2.bin)
     set(BL2_HEX_FILE ${TFM_BINARY_DIR}/bin/bl2.hex)
+    if(CONFIG_TFM_BL1)
+      set(BL2_SIGNED_BIN_FILE ${TFM_BINARY_DIR}/bin/bl2_signed.bin)
+      set(BL2_SIGNED_HEX_FILE ${TFM_BINARY_DIR}/bin/bl2_signed.hex)
+    endif()
   endif()
   set(TFM_S_ELF_FILE ${TFM_BINARY_DIR}/bin/tfm_s.elf)
   set(TFM_S_BIN_FILE ${TFM_BINARY_DIR}/bin/tfm_s.bin)
@@ -179,6 +191,8 @@ if (CONFIG_BUILD_WITH_TFM)
     ${BL2_ELF_FILE}
     ${BL2_BIN_FILE}
     ${BL2_HEX_FILE}
+    $<$<BOOL:${CONFIG_TFM_BL1}>:${BL2_SIGNED_BIN_FILE}>
+    $<$<BOOL:${CONFIG_TFM_BL1}>:${BL2_SIGNED_HEX_FILE}>
     ${TFM_S_ELF_FILE}
     ${TFM_S_BIN_FILE}
     ${TFM_S_HEX_FILE}
@@ -210,10 +224,6 @@ if (CONFIG_BUILD_WITH_TFM)
     set(TFM_TOOLCHAIN_FILE "toolchain_GNUARM.cmake")
     set(TFM_TOOLCHAIN_PREFIX "arm-none-eabi")
     set(TFM_TOOLCHAIN_PATH ${GNUARMEMB_TOOLCHAIN_PATH}/bin)
-  elseif(${ZEPHYR_TOOLCHAIN_VARIANT} STREQUAL "xtools")
-    set(TFM_TOOLCHAIN_FILE "toolchain_GNUARM.cmake")
-    set(TFM_TOOLCHAIN_PREFIX "arm-zephyr-eabi")
-    set(TFM_TOOLCHAIN_PATH ${XTOOLS_TOOLCHAIN_PATH}/arm-zephyr-eabi/bin)
   else()
     message(FATAL_ERROR "Unsupported ZEPHYR_TOOLCHAIN_VARIANT: ${ZEPHYR_TOOLCHAIN_VARIANT}")
   endif()
@@ -257,7 +267,9 @@ if (CONFIG_BUILD_WITH_TFM)
 
   list(APPEND TFM_CMAKE_ARGS -DTFM_TESTS_REVISION_CHECKS=OFF)
 
-  list(APPEND TFM_CMAKE_ARGS -DETHOS_DRIVER_PATH=${CONFIG_TFM_ETHOS_DRIVER_PATH_LOCAL})
+  if(CONFIG_TFM_ETHOS_DRIVER_PATH_LOCAL)
+    list(APPEND TFM_CMAKE_ARGS -DETHOS_DRIVER_PATH=${CONFIG_TFM_ETHOS_DRIVER_PATH_LOCAL})
+  endif()
 
   file(MAKE_DIRECTORY ${TFM_BINARY_DIR})
   add_custom_target(tfm_cmake
@@ -331,6 +343,10 @@ if (CONFIG_BUILD_WITH_TFM)
       BL2_BIN_FILE ${BL2_BIN_FILE}
       BL2_HEX_FILE ${BL2_HEX_FILE}
       )
+      if(CONFIG_TFM_BL1)
+        set_target_properties(tfm PROPERTIES BL2_SIGNED_BIN_FILE ${BL2_SIGNED_BIN_FILE})
+        set_target_properties(tfm PROPERTIES BL2_SIGNED_HEX_FILE ${BL2_SIGNED_HEX_FILE})
+      endif()
   endif()
 
   # Set TFM S/NS executable file paths as target properties on 'tfm'
@@ -490,7 +506,8 @@ if (CONFIG_BUILD_WITH_TFM)
 
       COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/build/mergehex.py
         -o ${MERGED_FILE}
-        $<TARGET_PROPERTY:tfm,BL2_HEX_FILE>
+        $<$<BOOL:${CONFIG_TFM_BL1}>:$<TARGET_PROPERTY:tfm,BL2_SIGNED_HEX_FILE>>
+        $<$<NOT:$<BOOL:${CONFIG_TFM_BL1}>>:$<TARGET_PROPERTY:tfm,BL2_HEX_FILE>>
         ${S_NS_SIGNED_FILE}
     )
 
@@ -516,7 +533,8 @@ if (CONFIG_BUILD_WITH_TFM)
 
       COMMAND ${PYTHON_EXECUTABLE} ${ZEPHYR_BASE}/scripts/build/mergehex.py
         -o ${MERGED_FILE}
-        $<TARGET_PROPERTY:tfm,BL2_HEX_FILE>
+        $<$<BOOL:${CONFIG_TFM_BL1}>:$<TARGET_PROPERTY:tfm,BL2_SIGNED_HEX_FILE>>
+        $<$<NOT:$<BOOL:${CONFIG_TFM_BL1}>>:$<TARGET_PROPERTY:tfm,BL2_HEX_FILE>>
         ${S_SIGNED_FILE}
         ${NS_SIGNED_FILE}
     )
diff --git a/modules/trusted-firmware-m/Kconfig.tfm b/modules/trusted-firmware-m/Kconfig.tfm
index c8f8b656e28..7a8e4592009 100644
--- a/modules/trusted-firmware-m/Kconfig.tfm
+++ b/modules/trusted-firmware-m/Kconfig.tfm
@@ -26,6 +26,7 @@ config TFM_BOARD
 	default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic/nrf9120" if SOC_NRF9120
 	default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic/nrf5340_cpuapp" if SOC_NRF5340_CPUAPP
 	default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic/nrf54l15_cpuapp" if SOC_NRF54L15_CPUAPP
+	default "${ZEPHYR_BASE}/modules/trusted-firmware-m/nordic/nrf54l10_cpuapp" if SOC_NRF54L10_CPUAPP
 	help
 	  The board name used for building TFM. Building with TFM requires that
 	  TFM has been ported to the given board/SoC.
@@ -207,6 +208,12 @@ config TFM_IMAGE_VERSION_NS
 	help
 	  Version of the non-secure image.
 
+config TFM_BL1
+	bool "Add BL1 to TFM"
+	help
+	  TFM is designed to run with BL1 in a certain configuration.
+	  This config adds BL1 to the build - built via TFM's build system.
+
 config TFM_BL2
 	bool "Add MCUboot to TFM"
 	depends on !TFM_BL2_NOT_SUPPORTED
@@ -241,6 +248,18 @@ config TFM_CONNECTION_BASED_SERVICE_API
 	  system. When this option is not enabled in the TF-M build system this
 	  will result in compilation error.
 
+
+if TFM_BL1
+
+config TFM_BL2_SIGNING_KEY_PATH
+	string "Path to private key used to sign BL2 firmware images."
+	help
+	  Path to binary BL2 signing private key
+	  Default is ${ZEPHYR_TRUSTED_FIRMWARE_M_MODULE_DIR}/bl1/bl1_2/bl1_dummy_rotpk
+	  if it has not been changed on TF-M side for your board
+
+endif # TFM_BL1
+
 if TFM_BL2
 
 config TFM_IMAGE_SECURITY_COUNTER
@@ -313,6 +332,7 @@ endchoice
 
 config TFM_ETHOS_DRIVER_PATH_LOCAL
 	string "Path to a locally available Ethos-U driver or an empty string"
+	depends on SOC_SERIES_MPS3
 	default "${ZEPHYR_HAL_ETHOS_U_MODULE_DIR}"
 	help
 	  Path to a locally available Ethos-U driver to be used for TF-M builds or
diff --git a/modules/trusted-firmware-m/nordic/include/tfm_peripherals_config.h b/modules/trusted-firmware-m/nordic/include/tfm_peripherals_config.h
index 6f27e60fd57..2b50abc57ae 100644
--- a/modules/trusted-firmware-m/nordic/include/tfm_peripherals_config.h
+++ b/modules/trusted-firmware-m/nordic/include/tfm_peripherals_config.h
@@ -13,7 +13,7 @@ extern "C" {
 
 #ifdef SECURE_UART1
 
-#if defined(NRF54L15_XXAA)
+#if defined(NRF54L_SERIES)
 #define TFM_PERIPHERAL_UARTE30_SECURE 1
 #else
 #define TFM_PERIPHERAL_UARTE1_SECURE 1
@@ -35,8 +35,8 @@ extern "C" {
     #include <tfm_peripherals_config_nrf91.h>
 #elif defined(NRF5340_XXAA_APPLICATION)
     #include <tfm_peripherals_config_nrf5340_application.h>
-#elif defined(NRF54L15_XXAA)
-    #include <tfm_peripherals_config_nrf54l15.h>
+#elif defined(NRF54L_SERIES)
+    #include <tfm_peripherals_config_nrf54l.h>
 #else
     #error "Unknown device."
 #endif
diff --git a/modules/trusted-firmware-m/nordic/nrf54l10_cpuapp/CMakeLists.txt b/modules/trusted-firmware-m/nordic/nrf54l10_cpuapp/CMakeLists.txt
new file mode 100644
index 00000000000..c1bdb28c52c
--- /dev/null
+++ b/modules/trusted-firmware-m/nordic/nrf54l10_cpuapp/CMakeLists.txt
@@ -0,0 +1,23 @@
+#
+# Copyright (c) 2025, Nordic Semiconductor ASA.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+set(NRF_BOARD_SELECTED True)
+
+add_subdirectory(${Trusted\ Firmware\ M_SOURCE_DIR}/platform/ext/target/nordic_nrf/common/nrf54l10 nrf54l10)
+
+add_subdirectory(.. common)
+
+install(FILES       ${CMAKE_CURRENT_LIST_DIR}/ns/cpuarch_ns.cmake
+        DESTINATION ${INSTALL_PLATFORM_NS_DIR}
+        RENAME      cpuarch.cmake)
+
+install(FILES       config.cmake
+        DESTINATION ${INSTALL_PLATFORM_NS_DIR})
+
+install(DIRECTORY   ${Trusted\ Firmware\ M_SOURCE_DIR}/platform/ext/target/nordic_nrf/nrf54l15dk_nrf54l10_cpuapp/tests
+
+        DESTINATION ${INSTALL_PLATFORM_NS_DIR}
+)
diff --git a/modules/trusted-firmware-m/nordic/nrf54l10_cpuapp/config.cmake b/modules/trusted-firmware-m/nordic/nrf54l10_cpuapp/config.cmake
new file mode 100644
index 00000000000..275295a164d
--- /dev/null
+++ b/modules/trusted-firmware-m/nordic/nrf54l10_cpuapp/config.cmake
@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2025, Nordic Semiconductor ASA.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+set(NRF_SOC_VARIANT nrf54l10 CACHE STRING "nRF SoC Variant")
+
+include(${PLATFORM_PATH}/common/nrf54l10/config.cmake)
diff --git a/modules/trusted-firmware-m/nordic/nrf54l10_cpuapp/cpuarch.cmake b/modules/trusted-firmware-m/nordic/nrf54l10_cpuapp/cpuarch.cmake
new file mode 100644
index 00000000000..e6b6c70674e
--- /dev/null
+++ b/modules/trusted-firmware-m/nordic/nrf54l10_cpuapp/cpuarch.cmake
@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2025, Nordic Semiconductor ASA.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+set(PLATFORM_PATH platform/ext/target/nordic_nrf)
+
+include(${PLATFORM_PATH}/common/nrf54l10/cpuarch.cmake)
diff --git a/modules/trusted-firmware-m/nordic/nrf54l10_cpuapp/ns/cpuarch_ns.cmake b/modules/trusted-firmware-m/nordic/nrf54l10_cpuapp/ns/cpuarch_ns.cmake
new file mode 100644
index 00000000000..c45f535be70
--- /dev/null
+++ b/modules/trusted-firmware-m/nordic/nrf54l10_cpuapp/ns/cpuarch_ns.cmake
@@ -0,0 +1,10 @@
+#
+# Copyright (c) 2025, Nordic Semiconductor ASA.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+set(PLATFORM_DIR  ${CMAKE_CURRENT_LIST_DIR})
+set(PLATFORM_PATH ${CMAKE_CURRENT_LIST_DIR})
+
+include(${CMAKE_CURRENT_LIST_DIR}/common/nrf54l10/cpuarch.cmake)
diff --git a/modules/uoscore-uedhoc/CMakeLists.txt b/modules/uoscore-uedhoc/CMakeLists.txt
index aaf842e392c..a7f08928381 100644
--- a/modules/uoscore-uedhoc/CMakeLists.txt
+++ b/modules/uoscore-uedhoc/CMakeLists.txt
@@ -107,7 +107,8 @@ if (CONFIG_UOSCORE OR CONFIG_UEDHOC)
       ${UOSCORE_UEDHOC_SRC_DIR}/cbor/edhoc_decode_message_1.c
       ${UOSCORE_UEDHOC_SRC_DIR}/cbor/edhoc_decode_message_2.c
       ${UOSCORE_UEDHOC_SRC_DIR}/cbor/edhoc_decode_message_3.c
-      ${UOSCORE_UEDHOC_SRC_DIR}/cbor/edhoc_decode_plaintext.c
+      ${UOSCORE_UEDHOC_SRC_DIR}/cbor/edhoc_decode_plaintext2.c
+      ${UOSCORE_UEDHOC_SRC_DIR}/cbor/edhoc_decode_plaintext3.c
       ${UOSCORE_UEDHOC_SRC_DIR}/cbor/edhoc_encode_bstr_type.c
       ${UOSCORE_UEDHOC_SRC_DIR}/cbor/edhoc_encode_data_2.c
       ${UOSCORE_UEDHOC_SRC_DIR}/cbor/edhoc_encode_enc_structure.c
diff --git a/modules/zcbor/Kconfig b/modules/zcbor/Kconfig
index deb976bbcd0..5f6ef3b7684 100644
--- a/modules/zcbor/Kconfig
+++ b/modules/zcbor/Kconfig
@@ -16,7 +16,12 @@ config ZCBOR_CANONICAL
 	bool "Produce canonical CBOR"
 	help
 	  Enabling this will prevent zcbor from creating lists and maps with
-	  indefinite-length arrays (it will still decode them properly).
+	  indefinite-length arrays.
+	  Enabling this also enables the state->constant_state->enforce_canonical
+	  flag in all zcbor states. This flag controls validation of canonical
+	  data when decoding. If you only want canonical encoding, please set
+	  the enforce_canonical flag to false in all new state structs after
+	  initialization.
 
 config ZCBOR_STOP_ON_ERROR
 	bool "Stop on error when processing (Must also be enabled in state var)"
@@ -28,7 +33,7 @@ config ZCBOR_STOP_ON_ERROR
 	  has already happened.
 
 config ZCBOR_VERBOSE
-	bool "Make zcbor code print messages"
+	bool "Make zcbor code print messages via printf"
 
 config ZCBOR_ASSERT
 	def_bool ASSERT
diff --git a/samples/application_development/code_relocation_nocopy/boards/stm32f746g_disco.conf b/samples/application_development/code_relocation_nocopy/boards/stm32f746g_disco.conf
new file mode 100644
index 00000000000..eac2504a785
--- /dev/null
+++ b/samples/application_development/code_relocation_nocopy/boards/stm32f746g_disco.conf
@@ -0,0 +1,2 @@
+CONFIG_FLASH=y
+CONFIG_STM32_MEMMAP=y
diff --git a/samples/application_development/code_relocation_nocopy/linker_arm_nocopy.ld b/samples/application_development/code_relocation_nocopy/linker_arm_nocopy.ld
index 0a11783cca2..699a044373b 100644
--- a/samples/application_development/code_relocation_nocopy/linker_arm_nocopy.ld
+++ b/samples/application_development/code_relocation_nocopy/linker_arm_nocopy.ld
@@ -31,21 +31,21 @@
 
 #define EXTFLASH_NODE	DT_INST(0, st_stm32_ospi_nor)
 #define EXTFLASH_ADDR	DT_REG_ADDR(DT_INST(0, st_stm32_ospi_nor))
-#define EXTFLASH_SIZE	DT_REG_ADDR_BY_IDX(DT_INST(0, st_stm32_ospi_nor), 1)
+#define EXTFLASH_SIZE	DT_REG_SIZE(DT_INST(0, st_stm32_ospi_nor))
 
 #elif defined(CONFIG_STM32_MEMMAP) && DT_NODE_EXISTS(DT_INST(0, st_stm32_qspi_nor))
 /* On stm32 QSPI, external flash is mapped in XIP region at address given by the reg property. */
 
 #define EXTFLASH_NODE	DT_INST(0, st_stm32_qspi_nor)
 #define EXTFLASH_ADDR	DT_REG_ADDR(DT_INST(0, st_stm32_qspi_nor))
-#define EXTFLASH_SIZE	DT_REG_ADDR_BY_IDX(DT_INST(0, st_stm32_qspi_nor), 1)
+#define EXTFLASH_SIZE	DT_REG_SIZE(DT_INST(0, st_stm32_qspi_nor))
 
 #elif defined(CONFIG_STM32_MEMMAP) && DT_NODE_EXISTS(DT_INST(0, st_stm32_xspi_nor))
 /* On stm32 XSPI, external flash is mapped in XIP region at address given by the reg property. */
 
 #define EXTFLASH_NODE	DT_INST(0, st_stm32_xspi_nor)
 #define EXTFLASH_ADDR	DT_REG_ADDR(DT_INST(0, st_stm32_xspi_nor))
-#define EXTFLASH_SIZE	DT_REG_ADDR_BY_IDX(DT_INST(0, st_stm32_xspi_nor), 1)
+#define EXTFLASH_SIZE	DT_REG_SIZE(DT_INST(0, st_stm32_xspi_nor))
 
 #elif defined(CONFIG_FLASH_MSPI_NOR) && defined(CONFIG_SOC_NRF54H20_CPUAPP)
 
diff --git a/samples/application_development/code_relocation_nocopy/sample.yaml b/samples/application_development/code_relocation_nocopy/sample.yaml
index d90172ee140..37e009bc987 100644
--- a/samples/application_development/code_relocation_nocopy/sample.yaml
+++ b/samples/application_development/code_relocation_nocopy/sample.yaml
@@ -2,7 +2,7 @@ sample:
   description: Code data relocation nocopy Sample
   name: code relocation nocopy
 tests:
-  sample.application_development.code_relocation_nocopy:
+  sample.app_dev.code_relocation_nocopy:
     platform_allow:
       - qemu_cortex_m3
       - nrf5340dk/nrf5340/cpuapp
diff --git a/samples/arch/mpu/mpu_test/sample.yaml b/samples/arch/mpu/mpu_test/sample.yaml
index ca604ed9fc7..29bd87d9173 100644
--- a/samples/arch/mpu/mpu_test/sample.yaml
+++ b/samples/arch/mpu/mpu_test/sample.yaml
@@ -4,5 +4,8 @@ tests:
   sample.mpu.mpu_test:
     arch_allow: arm
     filter: CONFIG_CPU_HAS_MPU and not CONFIG_ARM64
-    tags: mpu
-    harness: keyboard
+    tags:
+      - mpu
+    harness: shell
+    integration_platforms:
+      - mps2/an385
diff --git a/samples/arch/mpu/mpu_test/test_shell.yml b/samples/arch/mpu/mpu_test/test_shell.yml
new file mode 100644
index 00000000000..fcce9e59ce9
--- /dev/null
+++ b/samples/arch/mpu/mpu_test/test_shell.yml
@@ -0,0 +1,4 @@
+- command: "mpu mtest 1"
+  expected: "The value is: 0x.*"
+- command: "mpu mtest 2"
+  expected: "The value is: 0x.*"
diff --git a/samples/arch/smp/pi/src/main.c b/samples/arch/smp/pi/src/main.c
index f5797c43f79..fe6a67cacc6 100644
--- a/samples/arch/smp/pi/src/main.c
+++ b/samples/arch/smp/pi/src/main.c
@@ -30,6 +30,8 @@ static struct k_thread tthread[THREADS_NUM];
 static char th_buffer[THREADS_NUM][DIGITS_NUM + 1];
 static atomic_t th_counter = THREADS_NUM;
 
+K_SEM_DEFINE(main_sem, 0, 1);
+
 void test_thread(void *arg1, void *arg2, void *arg3)
 {
 	atomic_t *counter = (atomic_t *)arg1;
@@ -74,7 +76,9 @@ void test_thread(void *arg1, void *arg2, void *arg3)
 		buffer += 4;
 	}
 
-	atomic_dec(counter);
+	if (atomic_dec(counter) == 1) {
+		k_sem_give(&main_sem);
+	}
 }
 
 int main(void)
@@ -96,9 +100,7 @@ int main(void)
 	}
 
 	/* Wait for all workers to finish their calculations */
-	while (th_counter) {
-		k_sleep(K_MSEC(1));
-	}
+	k_sem_take(&main_sem, K_FOREVER);
 
 	/* Capture final time stamp */
 	stop_time = k_cycle_get_32();
diff --git a/samples/basic/blinky_pwm/README.rst b/samples/basic/blinky_pwm/README.rst
index 21e086edfc3..d9863b1a786 100644
--- a/samples/basic/blinky_pwm/README.rst
+++ b/samples/basic/blinky_pwm/README.rst
@@ -63,7 +63,7 @@ In these other cases, however, manual wiring is necessary:
 Building and Running
 ********************
 
-To build and flash this sample for the :ref:`nrf52840dk_nrf52840`:
+To build and flash this sample for the :zephyr:board:`nrf52840dk`:
 
 .. zephyr-app-commands::
    :zephyr-app: samples/basic/blinky_pwm
diff --git a/samples/basic/blinky_pwm/boards/arduino_uno_r4_r7fa4m1ab3cfm_minima.overlay b/samples/basic/blinky_pwm/boards/arduino_uno_r4_r7fa4m1ab3cfm_minima.overlay
new file mode 100644
index 00000000000..3f413b4120b
--- /dev/null
+++ b/samples/basic/blinky_pwm/boards/arduino_uno_r4_r7fa4m1ab3cfm_minima.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pwm/pwm.h>
+#include <zephyr/dt-bindings/pwm/ra_pwm.h>
+
+/ {
+	leds {
+		status = "disabled";
+	};
+
+	pwm_leds {
+		status = "okay";
+	};
+};
+
+&pinctrl {
+	pwm3_default: pwm3_default {
+		group1 {
+			/* GTIOC3A */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 11)>;
+		};
+	};
+};
+
+&pwm3 {
+	pinctrl-0 = <&pwm3_default>;
+	pinctrl-names = "default";
+	interrupts = <30 1>, <31 1>;
+	interrupt-names = "gtioca", "overflow";
+	status = "okay";
+	divider = <RA_PWM_SOURCE_DIV_1024>;
+};
diff --git a/samples/basic/blinky_pwm/boards/arduino_uno_r4_r7fa4m1ab3cfm_wifi.overlay b/samples/basic/blinky_pwm/boards/arduino_uno_r4_r7fa4m1ab3cfm_wifi.overlay
new file mode 100644
index 00000000000..45912b9358b
--- /dev/null
+++ b/samples/basic/blinky_pwm/boards/arduino_uno_r4_r7fa4m1ab3cfm_wifi.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pwm/pwm.h>
+#include <zephyr/dt-bindings/pwm/ra_pwm.h>
+
+/ {
+	leds {
+		status = "disabled";
+	};
+
+	pwm_leds {
+		status = "okay";
+	};
+};
+
+&pinctrl {
+	pwm2_default: pwm2_default {
+		group1 {
+			/* GTIOC2B */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 2)>;
+		};
+	};
+};
+
+&pwm2 {
+	pinctrl-0 = <&pwm2_default>;
+	pinctrl-names = "default";
+	interrupts = <30 1>, <31 1>;
+	interrupt-names = "gtioca", "overflow";
+	status = "okay";
+	divider = <RA_PWM_SOURCE_DIV_1024>;
+};
diff --git a/samples/basic/blinky_pwm/boards/esp32c3_supermini.overlay b/samples/basic/blinky_pwm/boards/esp32c3_supermini.overlay
new file mode 100644
index 00000000000..ed2fc7c1b7b
--- /dev/null
+++ b/samples/basic/blinky_pwm/boards/esp32c3_supermini.overlay
@@ -0,0 +1,44 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2021 Andrei-Edward Popa
+ * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
+ */
+
+ #include <zephyr/dt-bindings/pwm/pwm.h>
+
+/ {
+	aliases {
+		pwm-0 = &ledc0;
+		pwm-led0 = &pwm_led_blue;
+	};
+
+	pwmleds {
+		compatible = "pwm-leds";
+		pwm_led_blue: pwm-led-gpio0-2 {
+			label = "PWM LED0";
+			pwms = <&ledc0 0 1000 PWM_POLARITY_NORMAL>;
+		};
+	};
+};
+
+&pinctrl {
+	ledc0_default: ledc0-default {
+		group1 {
+			pinmux = <LEDC_CH0_GPIO2>;
+			output-enable;
+		};
+	};
+};
+
+&ledc0 {
+	pinctrl-0 = <&ledc0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	channel0@0 {
+		reg = <0x0>;
+		timer = <0>;
+	};
+};
diff --git a/samples/basic/blinky_pwm/sample.yaml b/samples/basic/blinky_pwm/sample.yaml
index d2087f73347..cdf568b307d 100644
--- a/samples/basic/blinky_pwm/sample.yaml
+++ b/samples/basic/blinky_pwm/sample.yaml
@@ -3,6 +3,8 @@ sample:
 tests:
   sample.basic.blink_led:
     filter: dt_alias_exists("pwm-led0") and dt_compat_enabled("pwm-leds")
+    integration_platforms:
+      - esp32c3_devkitm
     tags:
       - drivers
       - pwm
diff --git a/samples/basic/button/boards/rd_rw612_bga.conf b/samples/basic/button/boards/rd_rw612_bga.conf
new file mode 100644
index 00000000000..b0995a93b88
--- /dev/null
+++ b/samples/basic/button/boards/rd_rw612_bga.conf
@@ -0,0 +1,6 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+CONFIG_PM=y
diff --git a/samples/basic/button/boards/rd_rw612_bga.overlay b/samples/basic/button/boards/rd_rw612_bga.overlay
new file mode 100644
index 00000000000..65821c8b3eb
--- /dev/null
+++ b/samples/basic/button/boards/rd_rw612_bga.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&standby {
+	status = "okay";
+};
diff --git a/samples/basic/fade_led/README.rst b/samples/basic/fade_led/README.rst
index 2b569f6d5a5..9de9c79cc37 100644
--- a/samples/basic/fade_led/README.rst
+++ b/samples/basic/fade_led/README.rst
@@ -24,7 +24,7 @@ This sample has the same requirements and wiring considerations as the
 Building and Running
 ********************
 
-To build and flash this sample for the :ref:`nrf52840dk_nrf52840`:
+To build and flash this sample for the :zephyr:board:`nrf52840dk`:
 
 .. zephyr-app-commands::
    :zephyr-app: samples/basic/fade_led
diff --git a/samples/basic/fade_led/boards/arduino_uno_r4_r7fa4m1ab3cfm_minima.overlay b/samples/basic/fade_led/boards/arduino_uno_r4_r7fa4m1ab3cfm_minima.overlay
new file mode 100644
index 00000000000..3f413b4120b
--- /dev/null
+++ b/samples/basic/fade_led/boards/arduino_uno_r4_r7fa4m1ab3cfm_minima.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pwm/pwm.h>
+#include <zephyr/dt-bindings/pwm/ra_pwm.h>
+
+/ {
+	leds {
+		status = "disabled";
+	};
+
+	pwm_leds {
+		status = "okay";
+	};
+};
+
+&pinctrl {
+	pwm3_default: pwm3_default {
+		group1 {
+			/* GTIOC3A */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 11)>;
+		};
+	};
+};
+
+&pwm3 {
+	pinctrl-0 = <&pwm3_default>;
+	pinctrl-names = "default";
+	interrupts = <30 1>, <31 1>;
+	interrupt-names = "gtioca", "overflow";
+	status = "okay";
+	divider = <RA_PWM_SOURCE_DIV_1024>;
+};
diff --git a/samples/basic/fade_led/boards/arduino_uno_r4_r7fa4m1ab3cfm_wifi.overlay b/samples/basic/fade_led/boards/arduino_uno_r4_r7fa4m1ab3cfm_wifi.overlay
new file mode 100644
index 00000000000..45912b9358b
--- /dev/null
+++ b/samples/basic/fade_led/boards/arduino_uno_r4_r7fa4m1ab3cfm_wifi.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pwm/pwm.h>
+#include <zephyr/dt-bindings/pwm/ra_pwm.h>
+
+/ {
+	leds {
+		status = "disabled";
+	};
+
+	pwm_leds {
+		status = "okay";
+	};
+};
+
+&pinctrl {
+	pwm2_default: pwm2_default {
+		group1 {
+			/* GTIOC2B */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 2)>;
+		};
+	};
+};
+
+&pwm2 {
+	pinctrl-0 = <&pwm2_default>;
+	pinctrl-names = "default";
+	interrupts = <30 1>, <31 1>;
+	interrupt-names = "gtioca", "overflow";
+	status = "okay";
+	divider = <RA_PWM_SOURCE_DIV_1024>;
+};
diff --git a/samples/basic/fade_led/src/main.c b/samples/basic/fade_led/src/main.c
index c6a49a13a12..1a7b7ef26fd 100644
--- a/samples/basic/fade_led/src/main.c
+++ b/samples/basic/fade_led/src/main.c
@@ -14,46 +14,57 @@
 #include <zephyr/device.h>
 #include <zephyr/drivers/pwm.h>
 
-static const struct pwm_dt_spec pwm_led0 = PWM_DT_SPEC_GET(DT_ALIAS(pwm_led0));
+#define PWM_LED_ALIAS(i) DT_ALIAS(_CONCAT(pwm_led, i))
+#define PWM_LED_IS_OKAY(i) DT_NODE_HAS_STATUS_OKAY(DT_PARENT(PWM_LED_ALIAS(i)))
+#define PWM_LED(i, _) IF_ENABLED(PWM_LED_IS_OKAY(i), (PWM_DT_SPEC_GET(PWM_LED_ALIAS(i)),))
+
+#define MAX_LEDS 10
+static const struct pwm_dt_spec pwm_leds[] = {LISTIFY(MAX_LEDS, PWM_LED, ())};
 
 #define NUM_STEPS	50U
 #define SLEEP_MSEC	25U
 
 int main(void)
 {
-	uint32_t pulse_width = 0U;
-	uint32_t step = pwm_led0.period / NUM_STEPS;
+	uint32_t pulse_widths[ARRAY_SIZE(pwm_leds)];
+	uint32_t steps[ARRAY_SIZE(pwm_leds)];
 	uint8_t dir = 1U;
 	int ret;
 
-	printk("PWM-based LED fade\n");
-
-	if (!pwm_is_ready_dt(&pwm_led0)) {
-		printk("Error: PWM device %s is not ready\n",
-		       pwm_led0.dev->name);
-		return 0;
-	}
+	printk("PWM-based LED fade. Found %d LEDs\n", ARRAY_SIZE(pwm_leds));
 
-	while (1) {
-		ret = pwm_set_pulse_dt(&pwm_led0, pulse_width);
-		if (ret) {
-			printk("Error %d: failed to set pulse width\n", ret);
+	for (size_t i = 0; i < ARRAY_SIZE(pwm_leds); i++) {
+		pulse_widths[i] = 0;
+		steps[i] = pwm_leds[i].period / NUM_STEPS;
+		if (!pwm_is_ready_dt(&pwm_leds[i])) {
+			printk("Error: PWM device %s is not ready\n", pwm_leds[i].dev->name);
 			return 0;
 		}
-		printk("Using pulse width %d%%\n", 100 * pulse_width / pwm_led0.period);
+	}
 
-		if (dir) {
-			pulse_width += step;
-			if (pulse_width >= pwm_led0.period) {
-				pulse_width = pwm_led0.period - step;
-				dir = 0U;
+	while (1) {
+		for (size_t i = 0; i < ARRAY_SIZE(pwm_leds); i++) {
+			ret = pwm_set_pulse_dt(&pwm_leds[i], pulse_widths[i]);
+			if (ret) {
+				printk("Error %d: failed to set pulse width for LED %d\n", ret, i);
 			}
-		} else {
-			if (pulse_width >= step) {
-				pulse_width -= step;
+			printk("LED %d: Using pulse width %d%%\n", i,
+			       100 * pulse_widths[i] / pwm_leds[i].period);
+
+			if (dir) {
+				if (pulse_widths[i] + steps[i] >= pwm_leds[i].period) {
+					pulse_widths[i] = pwm_leds[i].period;
+					dir = 0U;
+				} else {
+					pulse_widths[i] += steps[i];
+				}
 			} else {
-				pulse_width = step;
-				dir = 1U;
+				if (pulse_widths[i] <= steps[i]) {
+					pulse_widths[i] = 0;
+					dir = 1U;
+				} else {
+					pulse_widths[i] -= steps[i];
+				}
 			}
 		}
 
diff --git a/samples/basic/hash_map/sample.yaml b/samples/basic/hash_map/sample.yaml
index dad9af8a994..b4fcf4a784c 100644
--- a/samples/basic/hash_map/sample.yaml
+++ b/samples/basic/hash_map/sample.yaml
@@ -20,34 +20,34 @@ common:
 
 tests:
   # Minimal Libc
-  libraries.hash_map.minimal.separate_chaining.djb2:
+  sample.libraries.hash_map.minimal.separate_chaining.djb2:
     extra_configs:
       - CONFIG_MINIMAL_LIBC=y
       - CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE=8192
       - CONFIG_SYS_HASH_MAP_CHOICE_SC=y
       - CONFIG_SYS_HASH_FUNC32_CHOICE_DJB2=y
-  libraries.hash_map.minimal.open_addressing.djb2:
+  sample.libraries.hash_map.minimal.open_addressing.djb2:
     extra_configs:
       - CONFIG_MINIMAL_LIBC=y
       - CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE=8192
       - CONFIG_SYS_HASH_MAP_CHOICE_OA_LP=y
       - CONFIG_SYS_HASH_FUNC32_CHOICE_DJB2=y
   # Newlib
-  libraries.hash_map.newlib.separate_chaining.djb2:
+  sample.libraries.hash_map.newlib.separate_chaining.djb2:
     filter: TOOLCHAIN_HAS_NEWLIB == 1
     extra_configs:
       - CONFIG_NEWLIB_LIBC=y
       - CONFIG_NEWLIB_LIBC_MIN_REQUIRED_HEAP_SIZE=8192
       - CONFIG_SYS_HASH_MAP_CHOICE_SC=y
       - CONFIG_SYS_HASH_FUNC32_CHOICE_DJB2=y
-  libraries.hash_map.newlib.open_addressing.djb2:
+  sample.libraries.hash_map.newlib.open_addressing.djb2:
     filter: TOOLCHAIN_HAS_NEWLIB == 1
     extra_configs:
       - CONFIG_NEWLIB_LIBC=y
       - CONFIG_NEWLIB_LIBC_MIN_REQUIRED_HEAP_SIZE=8192
       - CONFIG_SYS_HASH_MAP_CHOICE_OA_LP=y
       - CONFIG_SYS_HASH_FUNC32_CHOICE_DJB2=y
-  libraries.hash_map.newlib.cxx_unordered_map.djb2:
+  sample.libraries.hash_map.newlib.cxx_unordered_map.djb2:
     filter: TOOLCHAIN_HAS_NEWLIB == 1
     extra_configs:
       - CONFIG_NEWLIB_LIBC=y
@@ -56,13 +56,13 @@ tests:
       - CONFIG_SYS_HASH_FUNC32_CHOICE_DJB2=y
       - CONFIG_MAIN_STACK_SIZE=2048
   # PicoLibc
-  libraries.hash_map.picolibc.separate_chaining.djb2:
+  sample.libraries.hash_map.picolibc.separate_chaining.djb2:
     extra_configs:
       - CONFIG_PICOLIBC=y
       - CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE=8192
       - CONFIG_SYS_HASH_MAP_CHOICE_SC=y
       - CONFIG_SYS_HASH_FUNC32_CHOICE_DJB2=y
-  libraries.hash_map.picolibc.open_addressing.djb2:
+  sample.libraries.hash_map.picolibc.open_addressing.djb2:
     extra_configs:
       - CONFIG_PICOLIBC=y
       - CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE=8192
diff --git a/samples/basic/minimal/sample.yaml b/samples/basic/minimal/sample.yaml
index 5665dd7face..d1b276ae374 100644
--- a/samples/basic/minimal/sample.yaml
+++ b/samples/basic/minimal/sample.yaml
@@ -18,6 +18,7 @@ tests:
       - nrf51dk/nrf51822
       - nucleo_f429zi
       - disco_l475_iot1
+      - xg29_rb4412a
     integration_platforms:
       - frdm_k64f
   sample.minimal.mt-no-preempt.arm:
@@ -29,6 +30,7 @@ tests:
       - nrf51dk/nrf51822
       - nucleo_f429zi
       - disco_l475_iot1
+      - xg29_rb4412a
     integration_platforms:
       - frdm_k64f
   sample.minimal.mt-no-preempt-no-timers.arm:
@@ -40,6 +42,7 @@ tests:
       - nrf51dk/nrf51822
       - nucleo_f429zi
       - disco_l475_iot1
+      - xg29_rb4412a
     integration_platforms:
       - frdm_k64f
   sample.minimal.no-mt.arm:
@@ -51,6 +54,7 @@ tests:
       - nrf51dk/nrf51822
       - nucleo_f429zi
       - disco_l475_iot1
+      - xg29_rb4412a
     integration_platforms:
       - frdm_k64f
   sample.minimal.no-mt-no-timers.arm:
@@ -62,6 +66,7 @@ tests:
       - nrf51dk/nrf51822
       - nucleo_f429zi
       - disco_l475_iot1
+      - xg29_rb4412a
     integration_platforms:
       - frdm_k64f
   sample.minimal.mt.x86:
diff --git a/samples/basic/sys_heap/prj.conf b/samples/basic/sys_heap/prj.conf
index 2ffddad1e9b..0c486563862 100644
--- a/samples/basic/sys_heap/prj.conf
+++ b/samples/basic/sys_heap/prj.conf
@@ -1 +1,2 @@
 CONFIG_SYS_HEAP_RUNTIME_STATS=y
+CONFIG_SYS_HEAP_ARRAY_SIZE=4
diff --git a/samples/basic/sys_heap/src/main.c b/samples/basic/sys_heap/src/main.c
index 33f72302688..e59ab749283 100644
--- a/samples/basic/sys_heap/src/main.c
+++ b/samples/basic/sys_heap/src/main.c
@@ -9,10 +9,13 @@
 
 #define HEAP_SIZE	256
 
+K_HEAP_DEFINE(my_kernel_heap, HEAP_SIZE);
+
 static char heap_mem[HEAP_SIZE];
 static struct sys_heap heap;
 
-static void print_sys_memory_stats(void);
+static void print_sys_memory_stats(struct sys_heap *);
+static void print_all_heaps(void);
 
 int main(void)
 {
@@ -21,26 +24,42 @@ int main(void)
 	printk("System heap sample\n\n");
 
 	sys_heap_init(&heap, heap_mem, HEAP_SIZE);
-	print_sys_memory_stats();
+	print_sys_memory_stats(&heap);
 
 	p = sys_heap_alloc(&heap, 150);
-	print_sys_memory_stats();
+	print_sys_memory_stats(&heap);
 
 	p = sys_heap_realloc(&heap, p, 100);
-	print_sys_memory_stats();
+	print_sys_memory_stats(&heap);
 
 	sys_heap_free(&heap, p);
-	print_sys_memory_stats();
+	print_sys_memory_stats(&heap);
+
+	print_all_heaps();
 	return 0;
 }
 
-static void print_sys_memory_stats(void)
+static void print_sys_memory_stats(struct sys_heap *hp)
 {
 	struct sys_memory_stats stats;
 
-	sys_heap_runtime_stats_get(&heap, &stats);
+	sys_heap_runtime_stats_get(hp, &stats);
 
 	printk("allocated %zu, free %zu, max allocated %zu, heap size %u\n",
 		stats.allocated_bytes, stats.free_bytes,
 		stats.max_allocated_bytes, HEAP_SIZE);
 }
+
+static void print_all_heaps(void)
+{
+	struct sys_heap **ha;
+	size_t i, n;
+
+	n = sys_heap_array_get(&ha);
+	printk("There are %zu heaps allocated:\n", n);
+
+	for (i = 0; i < n; i++) {
+		printk("\t%zu - address %p ", i, ha[i]);
+		print_sys_memory_stats(ha[i]);
+	}
+}
diff --git a/samples/bluetooth/bap_broadcast_sink/CMakeLists.txt b/samples/bluetooth/bap_broadcast_sink/CMakeLists.txt
index 66649d87a33..3efc14377b1 100644
--- a/samples/bluetooth/bap_broadcast_sink/CMakeLists.txt
+++ b/samples/bluetooth/bap_broadcast_sink/CMakeLists.txt
@@ -2,10 +2,16 @@
 
 cmake_minimum_required(VERSION 3.20.0)
 find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(bap_unicast_server)
+project(bap_unicast_sink)
 
 target_sources(app PRIVATE
   src/main.c
+  src/stream_rx.c
 )
 
-zephyr_library_include_directories(${ZEPHYR_BASE}/samples/bluetooth)
+target_sources_ifdef(CONFIG_ENABLE_LC3 app PRIVATE src/lc3.c)
+
+if (CONFIG_USE_USB_AUDIO_OUTPUT)
+  include(${ZEPHYR_BASE}/samples/subsys/usb/common/common.cmake)
+  target_sources(app PRIVATE src/usb.c)
+endif()
diff --git a/samples/bluetooth/bap_broadcast_sink/Kconfig b/samples/bluetooth/bap_broadcast_sink/Kconfig
index e8e10d84a74..2d483082fd4 100644
--- a/samples/bluetooth/bap_broadcast_sink/Kconfig
+++ b/samples/bluetooth/bap_broadcast_sink/Kconfig
@@ -41,7 +41,7 @@ config MAX_CODEC_FRAMES_PER_SDU
 	range 1 255
 	help
 	  Maximum number of codec frames per SDU supported by this device. Increasing this value
-	  allows support for a greater variaty of broadcasts, but also increases memory usage.
+	  allows support for a greater variety of broadcasts, but also increases memory usage.
 
 config ENABLE_LC3
 	bool "Enable the LC3 codec"
@@ -55,8 +55,8 @@ config ENABLE_LC3
 config USE_USB_AUDIO_OUTPUT
 	bool "Use USB Audio as output"
 	depends on ENABLE_LC3
-	select USB_DEVICE_STACK
-	select USB_DEVICE_AUDIO
+	select USB_DEVICE_STACK_NEXT
+	select USBD_AUDIO2_CLASS
 	select RING_BUFFER
 	help
 	  Enables USB audio as output as a USB peripheral. This does not support providing USB
@@ -80,4 +80,16 @@ config TARGET_BROADCAST_CHANNEL
 	  Channel Audio Location to sync to. These corresponds to the bt_audio_location,
 	  supporting mono, left and right channels
 
+config INFO_REPORTING_INTERVAL
+	int "Number of SDUs received between each information report"
+	default 1000
+	help
+	  Determines how often information about received data is logged.
+	  Set to 0 to disable reporting.
+
+# Source common USB sample options used to initialize new experimental USB device stack.
+# The scope of these options is limited to USB samples in project tree,
+# you cannot use them in your own application.
+source "samples/subsys/usb/common/Kconfig.sample_usbd"
+
 source "Kconfig.zephyr"
diff --git a/samples/bluetooth/bap_broadcast_sink/app.overlay b/samples/bluetooth/bap_broadcast_sink/app.overlay
new file mode 100644
index 00000000000..7ea46c51156
--- /dev/null
+++ b/samples/bluetooth/bap_broadcast_sink/app.overlay
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/usb/audio.h>
+
+/ {
+	uac2_microphone: usb_audio2 {
+		compatible = "zephyr,uac2";
+		status = "okay";
+		full-speed;
+		audio-function = <AUDIO_FUNCTION_MICROPHONE>;
+
+		/* Clock supporting 48KHz
+		 *
+		 * Since the incoming audio may be between 8 and 48 KHz, we always upsample to 48KHz
+		 */
+		uac_aclk: aclk {
+			compatible = "zephyr,uac2-clock-source";
+			clock-type = "internal-programmable";
+			frequency-control = "read-only";
+			sampling-frequencies = <48000>;
+			/* Falsely claim synchronous audio because we
+			 * currently don't calculate feedback value
+			 */
+			sof-synchronized;
+		};
+
+		/* The out_terminal supports the incoming Bluetooth LE Audio over ISO
+		 * and treats it as a microphone towards the USB host
+		 */
+		out_terminal: out_terminal {
+			compatible = "zephyr,uac2-input-terminal";
+			clock-source = <&uac_aclk>;
+			terminal-type = <INPUT_TERMINAL_MICROPHONE>;
+			front-left;
+			front-right;
+		};
+
+		/* USB Audio terminal from USB device to USB host */
+		in_terminal: in_terminal {
+			compatible = "zephyr,uac2-output-terminal";
+			data-source = <&out_terminal>;
+			clock-source = <&uac_aclk>;
+			terminal-type = <USB_TERMINAL_STREAMING>;
+		};
+
+		as_iso_in: in_interface {
+			compatible = "zephyr,uac2-audio-streaming";
+			linked-terminal = <&in_terminal>;
+			subslot-size = <2>;
+			bit-resolution = <16>;
+		};
+	};
+};
diff --git a/samples/bluetooth/bap_broadcast_sink/boards/nrf52833dk_nrf52833.conf b/samples/bluetooth/bap_broadcast_sink/boards/nrf52833dk_nrf52833.conf
index 69b3cc51473..a37005f3bca 100644
--- a/samples/bluetooth/bap_broadcast_sink/boards/nrf52833dk_nrf52833.conf
+++ b/samples/bluetooth/bap_broadcast_sink/boards/nrf52833dk_nrf52833.conf
@@ -1,3 +1,3 @@
 # Use USB Audio as audio sink
 CONFIG_USE_USB_AUDIO_OUTPUT=y
-CONFIG_USB_DEVICE_PRODUCT="USB Broadcast Sink"
+CONFIG_SAMPLE_USBD_PRODUCT="USB Broadcast Sink sample"
diff --git a/samples/bluetooth/bap_broadcast_sink/boards/nrf52833dk_nrf52833.overlay b/samples/bluetooth/bap_broadcast_sink/boards/nrf52833dk_nrf52833.overlay
index b8e72f1b61c..94b67c37c70 100644
--- a/samples/bluetooth/bap_broadcast_sink/boards/nrf52833dk_nrf52833.overlay
+++ b/samples/bluetooth/bap_broadcast_sink/boards/nrf52833dk_nrf52833.overlay
@@ -1,15 +1,7 @@
-zephyr_udc0: &usbd {
-	compatible = "nordic,nrf-usbd";
-	status = "okay";
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
-	hs_0: hs_0 {
-		compatible = "usb-audio-hs";
-		mic-feature-mute;
-		mic-channel-l;
-		mic-channel-r;
-
-		hp-feature-mute;
-		hp-channel-l;
-		hp-channel-r;
-	};
-};
+#include "../app.overlay"
diff --git a/samples/bluetooth/bap_broadcast_sink/boards/nrf52840dk_nrf52840.conf b/samples/bluetooth/bap_broadcast_sink/boards/nrf52840dk_nrf52840.conf
new file mode 100644
index 00000000000..a37005f3bca
--- /dev/null
+++ b/samples/bluetooth/bap_broadcast_sink/boards/nrf52840dk_nrf52840.conf
@@ -0,0 +1,3 @@
+# Use USB Audio as audio sink
+CONFIG_USE_USB_AUDIO_OUTPUT=y
+CONFIG_SAMPLE_USBD_PRODUCT="USB Broadcast Sink sample"
diff --git a/samples/bluetooth/bap_broadcast_sink/boards/nrf52840dk_nrf52840.overlay b/samples/bluetooth/bap_broadcast_sink/boards/nrf52840dk_nrf52840.overlay
new file mode 100644
index 00000000000..94b67c37c70
--- /dev/null
+++ b/samples/bluetooth/bap_broadcast_sink/boards/nrf52840dk_nrf52840.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../app.overlay"
diff --git a/samples/bluetooth/bap_broadcast_sink/boards/nrf52840dongle_nrf52840.conf b/samples/bluetooth/bap_broadcast_sink/boards/nrf52840dongle_nrf52840.conf
index 69b3cc51473..61db369175b 100644
--- a/samples/bluetooth/bap_broadcast_sink/boards/nrf52840dongle_nrf52840.conf
+++ b/samples/bluetooth/bap_broadcast_sink/boards/nrf52840dongle_nrf52840.conf
@@ -1,3 +1,5 @@
 # Use USB Audio as audio sink
 CONFIG_USE_USB_AUDIO_OUTPUT=y
-CONFIG_USB_DEVICE_PRODUCT="USB Broadcast Sink"
+CONFIG_SAMPLE_USBD_PRODUCT="USB Broadcast Sink sample"
+
+CONFIG_BOARD_SERIAL_BACKEND_CDC_ACM=n
diff --git a/samples/bluetooth/bap_broadcast_sink/boards/nrf52840dongle_nrf52840.overlay b/samples/bluetooth/bap_broadcast_sink/boards/nrf52840dongle_nrf52840.overlay
index b8e72f1b61c..94b67c37c70 100644
--- a/samples/bluetooth/bap_broadcast_sink/boards/nrf52840dongle_nrf52840.overlay
+++ b/samples/bluetooth/bap_broadcast_sink/boards/nrf52840dongle_nrf52840.overlay
@@ -1,15 +1,7 @@
-zephyr_udc0: &usbd {
-	compatible = "nordic,nrf-usbd";
-	status = "okay";
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
-	hs_0: hs_0 {
-		compatible = "usb-audio-hs";
-		mic-feature-mute;
-		mic-channel-l;
-		mic-channel-r;
-
-		hp-feature-mute;
-		hp-channel-l;
-		hp-channel-r;
-	};
-};
+#include "../app.overlay"
diff --git a/samples/bluetooth/bap_broadcast_sink/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf b/samples/bluetooth/bap_broadcast_sink/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf
index 69b3cc51473..a37005f3bca 100644
--- a/samples/bluetooth/bap_broadcast_sink/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf
+++ b/samples/bluetooth/bap_broadcast_sink/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf
@@ -1,3 +1,3 @@
 # Use USB Audio as audio sink
 CONFIG_USE_USB_AUDIO_OUTPUT=y
-CONFIG_USB_DEVICE_PRODUCT="USB Broadcast Sink"
+CONFIG_SAMPLE_USBD_PRODUCT="USB Broadcast Sink sample"
diff --git a/samples/bluetooth/bap_broadcast_sink/boards/nrf5340_audio_dk_nrf5340_cpuapp.overlay b/samples/bluetooth/bap_broadcast_sink/boards/nrf5340_audio_dk_nrf5340_cpuapp.overlay
new file mode 100644
index 00000000000..94b67c37c70
--- /dev/null
+++ b/samples/bluetooth/bap_broadcast_sink/boards/nrf5340_audio_dk_nrf5340_cpuapp.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../app.overlay"
diff --git a/samples/bluetooth/bap_broadcast_sink/boards/nrf5340dk_nrf5340_cpuapp.conf b/samples/bluetooth/bap_broadcast_sink/boards/nrf5340dk_nrf5340_cpuapp.conf
index 69b3cc51473..a37005f3bca 100644
--- a/samples/bluetooth/bap_broadcast_sink/boards/nrf5340dk_nrf5340_cpuapp.conf
+++ b/samples/bluetooth/bap_broadcast_sink/boards/nrf5340dk_nrf5340_cpuapp.conf
@@ -1,3 +1,3 @@
 # Use USB Audio as audio sink
 CONFIG_USE_USB_AUDIO_OUTPUT=y
-CONFIG_USB_DEVICE_PRODUCT="USB Broadcast Sink"
+CONFIG_SAMPLE_USBD_PRODUCT="USB Broadcast Sink sample"
diff --git a/samples/bluetooth/bap_broadcast_sink/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/bluetooth/bap_broadcast_sink/boards/nrf5340dk_nrf5340_cpuapp.overlay
index b8e72f1b61c..94b67c37c70 100644
--- a/samples/bluetooth/bap_broadcast_sink/boards/nrf5340dk_nrf5340_cpuapp.overlay
+++ b/samples/bluetooth/bap_broadcast_sink/boards/nrf5340dk_nrf5340_cpuapp.overlay
@@ -1,15 +1,7 @@
-zephyr_udc0: &usbd {
-	compatible = "nordic,nrf-usbd";
-	status = "okay";
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
-	hs_0: hs_0 {
-		compatible = "usb-audio-hs";
-		mic-feature-mute;
-		mic-channel-l;
-		mic-channel-r;
-
-		hp-feature-mute;
-		hp-channel-l;
-		hp-channel-r;
-	};
-};
+#include "../app.overlay"
diff --git a/samples/bluetooth/bap_broadcast_sink/prj.conf b/samples/bluetooth/bap_broadcast_sink/prj.conf
index def80a0c1ba..c3780e12539 100644
--- a/samples/bluetooth/bap_broadcast_sink/prj.conf
+++ b/samples/bluetooth/bap_broadcast_sink/prj.conf
@@ -18,8 +18,8 @@ CONFIG_BT_ISO_SYNC_RECEIVER=y
 CONFIG_BT_BAP_BROADCAST_SINK=y
 CONFIG_BT_BAP_SCAN_DELEGATOR=y
 CONFIG_BT_ISO_MAX_CHAN=2
-# Allocate 2 RX buffers per channel
-CONFIG_BT_ISO_RX_BUF_COUNT=4
+# Allocate 4 RX buffers per channel
+CONFIG_BT_ISO_RX_BUF_COUNT=8
 CONFIG_BT_BAP_BROADCAST_SNK_SUBGROUP_COUNT=2
 CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT=2
 CONFIG_BT_BAP_BASS_MAX_SUBGROUPS=2
diff --git a/samples/bluetooth/bap_broadcast_sink/src/lc3.c b/samples/bluetooth/bap_broadcast_sink/src/lc3.c
new file mode 100644
index 00000000000..c05de47d355
--- /dev/null
+++ b/samples/bluetooth/bap_broadcast_sink/src/lc3.c
@@ -0,0 +1,487 @@
+/**
+ * @file
+ * @brief Bluetooth BAP Broadcast Sink LC3 extension
+ *
+ * This files handles all the LC3 related functionality for the sample
+ *
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/audio/audio.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/bluetooth/iso.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/logging/log_core.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/sys/ring_buffer.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/toolchain.h>
+#include <zephyr/usb/usb_device.h>
+#include <zephyr/usb/class/usb_audio.h>
+
+#include <lc3.h>
+
+#include "lc3.h"
+#include "stream_rx.h"
+#include "usb.h"
+
+LOG_MODULE_REGISTER(lc3, CONFIG_LOG_DEFAULT_LEVEL);
+
+#define LC3_ENCODER_STACK_SIZE 4096
+#define LC3_ENCODER_PRIORITY   5
+
+struct lc3_data {
+	void *fifo_reserved; /* 1st word reserved for use by FIFO */
+	struct net_buf *buf;
+	struct stream_rx *stream;
+	uint32_t ts;
+	bool do_plc;
+};
+
+K_MEM_SLAB_DEFINE_STATIC(lc3_data_slab, sizeof(struct lc3_data), CONFIG_BT_ISO_RX_BUF_COUNT,
+			 __alignof__(struct lc3_data));
+
+static int16_t lc3_rx_buf[LC3_MAX_NUM_SAMPLES_MONO];
+static K_FIFO_DEFINE(lc3_in_fifo);
+
+/* We only want to send USB to left/right from a single stream. If we have 2 left streams, the
+ * outgoing audio is going to be terrible.
+ * Since a stream can contain stereo data, both of these may be the same stream.
+ */
+static struct stream_rx *usb_left_stream;
+static struct stream_rx *usb_right_stream;
+
+static int init_lc3_decoder(struct stream_rx *stream, uint32_t lc3_frame_duration_us,
+			    uint32_t lc3_freq_hz)
+{
+	if (stream == NULL) {
+		LOG_ERR("NULL stream to init LC3 decoder");
+		return -EINVAL;
+	}
+
+	if (stream->lc3_decoder != NULL) {
+		LOG_ERR("Already initialized");
+		return -EALREADY;
+	}
+
+	if (lc3_freq_hz == 0U || lc3_frame_duration_us == 0U) {
+		LOG_ERR("Invalid freq (%u) or frame duration (%u)", lc3_freq_hz,
+			lc3_frame_duration_us);
+
+		return -EINVAL;
+	}
+
+	LOG_INF("Initializing the LC3 decoder with %u us duration and %u Hz frequency",
+		lc3_frame_duration_us, lc3_freq_hz);
+	/* Create the decoder instance. This shall complete before stream_started() is called. */
+	stream->lc3_decoder =
+		lc3_setup_decoder(lc3_frame_duration_us, lc3_freq_hz,
+				  IS_ENABLED(CONFIG_USE_USB_AUDIO_OUTPUT) ? USB_SAMPLE_RATE_HZ : 0,
+				  &stream->lc3_decoder_mem);
+	if (stream->lc3_decoder == NULL) {
+		LOG_ERR("Failed to setup LC3 decoder - wrong parameters?\n");
+		return -EINVAL;
+	}
+
+	LOG_INF("Initialized LC3 decoder for %p", stream);
+
+	return 0;
+}
+
+static bool decode_frame(struct lc3_data *data, size_t frame_cnt)
+{
+	const struct stream_rx *stream = data->stream;
+	const size_t total_frames = stream->lc3_chan_cnt * stream->lc3_frame_blocks_per_sdu;
+	const uint16_t octets_per_frame = stream->lc3_octets_per_frame;
+	struct net_buf *buf = data->buf;
+	void *iso_data;
+	int err;
+
+	if (data->do_plc) {
+		iso_data = NULL; /* perform PLC */
+
+#if CONFIG_INFO_REPORTING_INTERVAL > 0
+		if ((stream->reporting_info.lc3_decoded_cnt % CONFIG_INFO_REPORTING_INTERVAL) ==
+		    0) {
+			LOG_DBG("[%zu]: Performing PLC", stream->reporting_info.lc3_decoded_cnt);
+		}
+#endif /* CONFIG_INFO_REPORTING_INTERVAL > 0 */
+
+		data->do_plc = false; /* clear flag */
+	} else {
+		iso_data = net_buf_pull_mem(data->buf, octets_per_frame);
+
+#if CONFIG_INFO_REPORTING_INTERVAL > 0
+		if ((stream->reporting_info.lc3_decoded_cnt % CONFIG_INFO_REPORTING_INTERVAL) ==
+		    0) {
+			LOG_DBG("[%zu]: Decoding frame of size %u (%u/%u)",
+				stream->reporting_info.lc3_decoded_cnt, octets_per_frame,
+				frame_cnt + 1, total_frames);
+		}
+#endif /* CONFIG_INFO_REPORTING_INTERVAL > 0 */
+	}
+
+	err = lc3_decode(stream->lc3_decoder, iso_data, octets_per_frame, LC3_PCM_FORMAT_S16,
+			 lc3_rx_buf, 1);
+	if (err < 0) {
+		LOG_ERR("Failed to decode LC3 data (%u/%u - %u/%u)", frame_cnt + 1, total_frames,
+			octets_per_frame * frame_cnt, buf->len);
+		return false;
+	}
+
+	return true;
+}
+
+static int get_lc3_chan_alloc_from_index(const struct stream_rx *stream, uint8_t index,
+					 enum bt_audio_location *chan_alloc)
+{
+#if defined(CONFIG_USE_USB_AUDIO_OUTPUT)
+	const bool has_left = (stream->lc3_chan_allocation & BT_AUDIO_LOCATION_FRONT_LEFT) != 0;
+	const bool has_right = (stream->lc3_chan_allocation & BT_AUDIO_LOCATION_FRONT_RIGHT) != 0;
+	const bool is_mono = stream->lc3_chan_allocation == BT_AUDIO_LOCATION_MONO_AUDIO;
+	const bool is_left = index == 0 && has_left;
+	const bool is_right = has_right && (index == 0U || (index == 1U && has_left));
+
+	/* LC3 is always Left before Right, so we can use the index and the stream channel
+	 * allocation to determine if index 0 is left or right.
+	 */
+	if (is_left) {
+		*chan_alloc = BT_AUDIO_LOCATION_FRONT_LEFT;
+	} else if (is_right) {
+		*chan_alloc = BT_AUDIO_LOCATION_FRONT_RIGHT;
+	} else if (is_mono) {
+		*chan_alloc = BT_AUDIO_LOCATION_MONO_AUDIO;
+	} else {
+		/* Not suitable for USB */
+		return -EINVAL;
+	}
+
+	return 0;
+#else  /* !CONFIG_USE_USB_AUDIO_OUTPUT */
+	return -EINVAL;
+#endif /* CONFIG_USE_USB_AUDIO_OUTPUT */
+}
+
+static size_t decode_frame_block(struct lc3_data *data, size_t frame_cnt)
+{
+	const struct stream_rx *stream = data->stream;
+	const uint8_t chan_cnt = stream->lc3_chan_cnt;
+	size_t decoded_frames = 0U;
+
+	for (uint8_t i = 0U; i < chan_cnt; i++) {
+		/* We provide the total number of decoded frames to `decode_frame` for logging
+		 * purposes
+		 */
+		if (decode_frame(data, frame_cnt + decoded_frames)) {
+			decoded_frames++;
+
+			if (IS_ENABLED(CONFIG_USE_USB_AUDIO_OUTPUT)) {
+				enum bt_audio_location chan_alloc;
+				int err;
+
+				err = get_lc3_chan_alloc_from_index(stream, i, &chan_alloc);
+				if (err != 0) {
+					/* Not suitable for USB */
+					continue;
+				}
+
+				/* We only want to left or right from one stream to USB */
+				if ((chan_alloc == BT_AUDIO_LOCATION_FRONT_LEFT &&
+				     stream != usb_left_stream) ||
+				    (chan_alloc == BT_AUDIO_LOCATION_FRONT_RIGHT &&
+				     stream != usb_right_stream)) {
+					continue;
+				}
+
+				/* TODO: Add support for properly support the presentation delay.
+				 * For now we just send audio to USB as soon as we get it
+				 */
+				err = usb_add_frame_to_usb(chan_alloc, lc3_rx_buf,
+							   sizeof(lc3_rx_buf), data->ts);
+				if (err == -EINVAL) {
+					continue;
+				}
+			}
+		} else {
+			/* If decoding failed, we clear the data to USB as it would contain
+			 * invalid data
+			 */
+			if (IS_ENABLED(CONFIG_USE_USB_AUDIO_OUTPUT)) {
+				usb_clear_frames_to_usb();
+			}
+
+			break;
+		}
+	}
+
+	return decoded_frames;
+}
+
+static void do_lc3_decode(struct lc3_data *data)
+{
+	struct stream_rx *stream = data->stream;
+
+	if (stream->lc3_decoder != NULL) {
+		const uint8_t frame_blocks_per_sdu = stream->lc3_frame_blocks_per_sdu;
+		size_t frame_cnt;
+
+		frame_cnt = 0;
+		for (uint8_t i = 0U; i < frame_blocks_per_sdu; i++) {
+			const size_t decoded_frames = decode_frame_block(data, frame_cnt);
+
+			if (decoded_frames == 0) {
+				break;
+			}
+
+			frame_cnt += decoded_frames;
+		}
+
+#if CONFIG_INFO_REPORTING_INTERVAL > 0
+		stream->reporting_info.lc3_decoded_cnt++;
+#endif /* CONFIG_INFO_REPORTING_INTERVAL > 0 */
+	}
+
+	net_buf_unref(data->buf);
+}
+
+static void lc3_decoder_thread_func(void *arg1, void *arg2, void *arg3)
+{
+	while (true) {
+		struct lc3_data *data = k_fifo_get(&lc3_in_fifo, K_FOREVER);
+		struct stream_rx *stream = data->stream;
+
+		if (stream->lc3_decoder == NULL) {
+			LOG_WRN("Decoder is NULL, discarding data from FIFO");
+			k_mem_slab_free(&lc3_data_slab, (void *)data);
+			continue; /* Wait for new data */
+		}
+
+		do_lc3_decode(data);
+
+		k_mem_slab_free(&lc3_data_slab, (void *)data);
+	}
+}
+
+int lc3_enable(struct stream_rx *stream)
+{
+	const struct bt_audio_codec_cfg *codec_cfg = stream->stream.codec_cfg;
+	uint32_t lc3_frame_duration_us;
+	uint32_t lc3_freq_hz;
+	int ret;
+
+	if (codec_cfg->id != BT_HCI_CODING_FORMAT_LC3) {
+		return -EINVAL;
+	}
+
+	ret = bt_audio_codec_cfg_get_freq(codec_cfg);
+	if (ret >= 0) {
+		ret = bt_audio_codec_cfg_freq_to_freq_hz(ret);
+
+		if (ret > 0) {
+			if (ret == 8000 || ret == 16000 || ret == 24000 || ret == 32000 ||
+			    ret == 48000) {
+				lc3_freq_hz = (uint32_t)ret;
+			} else {
+				LOG_ERR("Unsupported frequency for LC3: %d", ret);
+				lc3_freq_hz = 0U;
+			}
+		} else {
+			LOG_ERR("Invalid frequency: %d", ret);
+			lc3_freq_hz = 0U;
+		}
+	} else {
+		LOG_ERR("Could not get frequency: %d", ret);
+		lc3_freq_hz = 0U;
+	}
+
+	if (lc3_freq_hz == 0U) {
+		return -EINVAL;
+	}
+
+	ret = bt_audio_codec_cfg_get_frame_dur(codec_cfg);
+	if (ret >= 0) {
+		ret = bt_audio_codec_cfg_frame_dur_to_frame_dur_us(ret);
+		if (ret > 0) {
+			lc3_frame_duration_us = (uint32_t)ret;
+		} else {
+			LOG_ERR("Invalid frame duration: %d", ret);
+			lc3_frame_duration_us = 0U;
+		}
+	} else {
+		LOG_ERR("Could not get frame duration: %d", ret);
+		lc3_frame_duration_us = 0U;
+	}
+
+	if (lc3_frame_duration_us == 0U) {
+		return -EINVAL;
+	}
+
+	ret = bt_audio_codec_cfg_get_chan_allocation(codec_cfg, &stream->lc3_chan_allocation, true);
+	if (ret == 0) {
+		stream->lc3_chan_cnt = bt_audio_get_chan_count(stream->lc3_chan_allocation);
+	} else {
+		LOG_DBG("Could not get channel allocation: %d", ret);
+		stream->lc3_chan_cnt = 0U;
+	}
+
+	if (stream->lc3_chan_cnt == 0U) {
+		return -EINVAL;
+	}
+
+	ret = bt_audio_codec_cfg_get_frame_blocks_per_sdu(codec_cfg, true);
+	if (ret >= 0) {
+		stream->lc3_frame_blocks_per_sdu = (uint8_t)ret;
+	} else {
+		LOG_ERR("Could not get frame blocks per SDU: %d", ret);
+		stream->lc3_frame_blocks_per_sdu = 0U;
+	}
+
+	if (stream->lc3_frame_blocks_per_sdu == 0U) {
+		return -EINVAL;
+	}
+
+	ret = bt_audio_codec_cfg_get_octets_per_frame(codec_cfg);
+	if (ret >= 0) {
+		stream->lc3_octets_per_frame = (uint16_t)ret;
+	} else {
+		LOG_ERR("Could not get octets per frame: %d", ret);
+		stream->lc3_octets_per_frame = 0U;
+	}
+
+	if (stream->lc3_octets_per_frame == 0U) {
+		return -EINVAL;
+	}
+
+	if (stream->lc3_decoder == NULL) {
+		const int err = init_lc3_decoder(stream, lc3_frame_duration_us, lc3_freq_hz);
+
+		if (err != 0) {
+			LOG_ERR("Failed to init LC3 decoder: %d", err);
+
+			return err;
+		}
+	}
+
+	if (IS_ENABLED(CONFIG_USE_USB_AUDIO_OUTPUT)) {
+		if ((stream->lc3_chan_allocation & BT_AUDIO_LOCATION_FRONT_LEFT) != 0) {
+			if (usb_left_stream == NULL) {
+				LOG_INF("Setting USB left stream to %p", stream);
+				usb_left_stream = stream;
+			} else {
+				LOG_WRN("Multiple left streams started");
+			}
+		}
+
+		if ((stream->lc3_chan_allocation & BT_AUDIO_LOCATION_FRONT_RIGHT) != 0) {
+			if (usb_right_stream == NULL) {
+				LOG_INF("Setting USB right stream to %p", stream);
+				usb_right_stream = stream;
+			} else {
+				LOG_WRN("Multiple right streams started");
+			}
+		}
+	}
+
+	return 0;
+}
+
+int lc3_disable(struct stream_rx *stream)
+{
+	if (stream->lc3_decoder == NULL) {
+		return -EINVAL;
+	}
+
+	stream->lc3_decoder = NULL;
+
+	if (IS_ENABLED(CONFIG_USB_DEVICE_AUDIO)) {
+		if (usb_left_stream == stream) {
+			usb_left_stream = NULL;
+		}
+		if (usb_right_stream == stream) {
+			usb_right_stream = NULL;
+		}
+	}
+
+	return 0;
+}
+
+void lc3_enqueue_for_decoding(struct stream_rx *stream, const struct bt_iso_recv_info *info,
+			      struct net_buf *buf)
+{
+	const uint8_t frame_blocks_per_sdu = stream->lc3_frame_blocks_per_sdu;
+	const uint16_t octets_per_frame = stream->lc3_octets_per_frame;
+	const uint8_t chan_cnt = stream->lc3_chan_cnt;
+	struct lc3_data *data;
+
+	if (stream->lc3_decoder == NULL) {
+		return;
+	}
+
+	/* Allocate a context that holds both the buffer and the stream so that we can
+	 * send both of these values to the LC3 decoder thread as a single struct
+	 * in a FIFO
+	 */
+	if (k_mem_slab_alloc(&lc3_data_slab, (void **)&data, K_NO_WAIT)) {
+		LOG_WRN("Could not allocate LC3 data item");
+		return;
+	}
+
+	if ((info->flags & BT_ISO_FLAGS_VALID) == 0) {
+		data->do_plc = true;
+	} else if (buf->len != (octets_per_frame * chan_cnt * frame_blocks_per_sdu)) {
+		if (buf->len != 0U) {
+			LOG_WRN("Expected %u frame blocks with %u channels of size %u, but "
+				"length is %u",
+				frame_blocks_per_sdu, chan_cnt, octets_per_frame, buf->len);
+		}
+
+		data->do_plc = true;
+	}
+
+	data->buf = net_buf_ref(buf);
+	data->stream = stream;
+	if (info->flags & BT_ISO_FLAGS_TS) {
+		data->ts = info->ts;
+	} else {
+		data->ts = 0U;
+	}
+
+	k_fifo_put(&lc3_in_fifo, data);
+}
+
+int lc3_init(void)
+{
+	static K_KERNEL_STACK_DEFINE(lc3_decoder_thread_stack, 4096);
+	const int lc3_decoder_thread_prio = K_PRIO_PREEMPT(5);
+	static struct k_thread lc3_decoder_thread;
+	static bool initialized;
+
+	if (initialized) {
+		return -EALREADY;
+	}
+
+	k_thread_create(&lc3_decoder_thread, lc3_decoder_thread_stack,
+			K_KERNEL_STACK_SIZEOF(lc3_decoder_thread_stack), lc3_decoder_thread_func,
+			NULL, NULL, NULL, lc3_decoder_thread_prio, 0, K_NO_WAIT);
+	k_thread_name_set(&lc3_decoder_thread, "LC3 Decoder");
+
+	LOG_INF("LC3 initialized");
+	initialized = true;
+
+	return 0;
+}
diff --git a/samples/bluetooth/bap_broadcast_sink/src/lc3.h b/samples/bluetooth/bap_broadcast_sink/src/lc3.h
new file mode 100644
index 00000000000..865d5c021f6
--- /dev/null
+++ b/samples/bluetooth/bap_broadcast_sink/src/lc3.h
@@ -0,0 +1,85 @@
+/**
+ * @file
+ * @brief Bluetooth BAP Broadcast Sink LC3 header
+ *
+ * This files handles all the LC3 related functionality for the sample
+ *
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef SAMPLE_BAP_BROADCAST_SINK_LC3_H
+#define SAMPLE_BAP_BROADCAST_SINK_LC3_H
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/audio/audio.h>
+#include <zephyr/bluetooth/iso.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/sys/ring_buffer.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/toolchain.h>
+#include <zephyr/usb/usb_device.h>
+#include <zephyr/usb/class/usb_audio.h>
+
+#include "stream_rx.h"
+
+#define LC3_MAX_SAMPLE_RATE_HZ     48000U
+#define LC3_MAX_FRAME_DURATION_US  10000U
+#define LC3_MAX_NUM_SAMPLES_MONO                                                                   \
+	((LC3_MAX_FRAME_DURATION_US * LC3_MAX_SAMPLE_RATE_HZ) / USEC_PER_SEC)
+#define LC3_MAX_NUM_SAMPLES_STEREO (LC3_MAX_NUM_SAMPLES_MONO * 2U)
+
+/**
+ * @brief Enables LC3 for a stream
+ *
+ * This will initialize the LC3 decoder given the @p stream codec configuration
+ *
+ * @param stream The stream to enable LC3 for
+
+ * @retval 0 Success
+ * @retval -EINVAL The stream is not LC3 codec configured or the codec configuration is invalid
+ */
+int lc3_enable(struct stream_rx *stream);
+
+/**
+ * @brief Disabled LC3 for a stream
+ *
+ * @param stream The stream to disable LC3 for
+
+ * @retval 0 Success
+ * @retval -EINVAL The stream is LC3 initialized
+ */
+int lc3_disable(struct stream_rx *stream);
+
+/**
+ * @brief Enqueue an SDU for decoding
+ *
+ * @param stream The stream that received the SDU
+ * @param info Information about the SDU
+ * @param buf The buffer of the SDU
+ */
+void lc3_enqueue_for_decoding(struct stream_rx *stream, const struct bt_iso_recv_info *info,
+			      struct net_buf *buf);
+
+/**
+ * @brief Initialize the LC3 module
+ *
+ * This will start the thread if not already initialized
+ *
+ * @retval 0 Success
+ * @retval -EALREADY Already initialized
+ */
+int lc3_init(void);
+#endif /* SAMPLE_BAP_BROADCAST_SINK_LC3_H */
diff --git a/samples/bluetooth/bap_broadcast_sink/src/main.c b/samples/bluetooth/bap_broadcast_sink/src/main.c
index c10c9329447..98b404f9e89 100644
--- a/samples/bluetooth/bap_broadcast_sink/src/main.c
+++ b/samples/bluetooth/bap_broadcast_sink/src/main.c
@@ -32,17 +32,9 @@
 #include <zephyr/sys_clock.h>
 #include <zephyr/toolchain.h>
 
-#if defined(CONFIG_LIBLC3)
 #include "lc3.h"
-#endif /* defined(CONFIG_LIBLC3) */
-#if defined(CONFIG_USB_DEVICE_AUDIO)
-#include <zephyr/device.h>
-#include <zephyr/devicetree.h>
-#include <zephyr/usb/usb_device.h>
-#include <zephyr/usb/class/usb_audio.h>
-#include <zephyr/sys/ring_buffer.h>
-#endif /* defined(CONFIG_USB_DEVICE_AUDIO) */
-
+#include "stream_rx.h"
+#include "usb.h"
 
 BUILD_ASSERT(IS_ENABLED(CONFIG_SCAN_SELF) || IS_ENABLED(CONFIG_SCAN_OFFLOAD),
 	     "Either SCAN_SELF or SCAN_OFFLOAD must be enabled");
@@ -63,27 +55,6 @@ BUILD_ASSERT(IS_ENABLED(CONFIG_SCAN_SELF) || IS_ENABLED(CONFIG_SCAN_OFFLOAD),
 #define NAME_LEN                    sizeof(CONFIG_TARGET_BROADCAST_NAME) + 1
 #define BROADCAST_DATA_ELEMENT_SIZE sizeof(int16_t)
 
-#if defined(CONFIG_LIBLC3)
-#define LC3_MAX_SAMPLE_RATE        48000U
-#define LC3_MAX_FRAME_DURATION_US  10000U
-#define LC3_MAX_NUM_SAMPLES_MONO   ((LC3_MAX_FRAME_DURATION_US * LC3_MAX_SAMPLE_RATE)              \
-				    / USEC_PER_SEC)
-#define LC3_MAX_NUM_SAMPLES_STEREO (LC3_MAX_NUM_SAMPLES_MONO * 2)
-
-#define LC3_ENCODER_STACK_SIZE  4096
-#define LC3_ENCODER_PRIORITY    5
-#endif /* defined(CONFIG_LIBLC3) */
-
-#if defined(CONFIG_USB_DEVICE_AUDIO)
-#define USB_ENQUEUE_COUNT            10U
-#define USB_SAMPLE_RATE	             48000U
-#define USB_FRAME_DURATION_US        1000U
-#define USB_MONO_SAMPLE_SIZE                                                                       \
-	((USB_FRAME_DURATION_US * USB_SAMPLE_RATE * BROADCAST_DATA_ELEMENT_SIZE) / USEC_PER_SEC)
-#define USB_STEREO_SAMPLE_SIZE       (USB_MONO_SAMPLE_SIZE * 2)
-#define USB_RING_BUF_SIZE            (5 * LC3_MAX_NUM_SAMPLES_STEREO) /* 5 SDUs*/
-#endif /* defined(CONFIG_USB_DEVICE_AUDIO) */
-
 static K_SEM_DEFINE(sem_broadcast_sink_stopped, 0U, 1U);
 static K_SEM_DEFINE(sem_connected, 0U, 1U);
 static K_SEM_DEFINE(sem_disconnected, 0U, 1U);
@@ -107,29 +78,7 @@ static struct bt_le_scan_recv_info broadcaster_info;
 static bt_addr_le_t broadcaster_addr;
 static struct bt_le_per_adv_sync *pa_sync;
 static uint32_t broadcaster_broadcast_id;
-static struct broadcast_sink_stream {
-	struct bt_bap_stream stream;
-	size_t recv_cnt;
-	size_t loss_cnt;
-	size_t error_cnt;
-	size_t valid_cnt;
-#if defined(CONFIG_LIBLC3)
-	struct net_buf *in_buf;
-	struct k_work_delayable lc3_decode_work;
-
-	/* LC3 config values */
-	enum bt_audio_location chan_allocation;
-	uint16_t lc3_octets_per_frame;
-	uint8_t lc3_frames_blocks_per_sdu;
-
-	/* Internal lock for protecting net_buf from multiple access */
-	struct k_mutex lc3_decoder_mutex;
-	lc3_decoder_t lc3_decoder;
-	lc3_decoder_mem_48k_t lc3_decoder_mem;
-#endif /* defined(CONFIG_LIBLC3) */
-} streams[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT];
-
-static struct bt_bap_stream *streams_p[ARRAY_SIZE(streams)];
+static struct bt_bap_stream *bap_streams_p[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT];
 static volatile bool big_synced;
 static volatile bool base_received;
 static struct bt_conn *broadcast_assistant_conn;
@@ -145,360 +94,25 @@ static const struct bt_audio_codec_cap codec_cap = BT_AUDIO_CODEC_CAP_LC3(
 /* Create a mask for the maximum BIS we can sync to using the number of streams
  * we have. Bit 0 is BIS index 1.
  */
-static const uint32_t bis_index_mask = BIT_MASK(ARRAY_SIZE(streams));
+static const uint32_t bis_index_mask = BIT_MASK(CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT);
 static uint32_t requested_bis_sync;
 static uint32_t bis_index_bitfield;
 static uint8_t sink_broadcast_code[BT_ISO_BROADCAST_CODE_SIZE];
 
-uint64_t total_rx_iso_packet_count; /* This value is exposed to test code */
-
 static int stop_adv(void);
 
-#if defined(CONFIG_USB_DEVICE_AUDIO)
-RING_BUF_DECLARE(usb_ring_buf, USB_RING_BUF_SIZE);
-NET_BUF_POOL_DEFINE(usb_tx_buf_pool, USB_ENQUEUE_COUNT, USB_STEREO_SAMPLE_SIZE, 0, net_buf_destroy);
-
-static void add_to_usb_ring_buf(const int16_t audio_buf[LC3_MAX_NUM_SAMPLES_STEREO]);
-#endif /* defined(CONFIG_USB_DEVICE_AUDIO) */
-
-#if defined(CONFIG_LIBLC3)
-static K_SEM_DEFINE(lc3_decoder_sem, 0, 1);
-
-static void do_lc3_decode(lc3_decoder_t decoder, const void *in_data, uint8_t octets_per_frame,
-			  int16_t out_data[LC3_MAX_NUM_SAMPLES_MONO]);
-static void lc3_decoder_thread(void *arg1, void *arg2, void *arg3);
-K_THREAD_DEFINE(decoder_tid, LC3_ENCODER_STACK_SIZE, lc3_decoder_thread,
-		NULL, NULL, NULL, LC3_ENCODER_PRIORITY, 0, -1);
-
-/* Consumer thread of the decoded stream data */
-static void lc3_decoder_thread(void *arg1, void *arg2, void *arg3)
-{
-	while (true) {
-#if defined(CONFIG_USB_DEVICE_AUDIO)
-		static int16_t right_frames[CONFIG_MAX_CODEC_FRAMES_PER_SDU]
-					   [LC3_MAX_NUM_SAMPLES_MONO];
-		static int16_t left_frames[CONFIG_MAX_CODEC_FRAMES_PER_SDU]
-					  [LC3_MAX_NUM_SAMPLES_MONO];
-		size_t right_frames_cnt = 0;
-		size_t left_frames_cnt = 0;
-
-		memset(right_frames, 0, sizeof(right_frames));
-		memset(left_frames, 0, sizeof(left_frames));
-#else
-		static int16_t lc3_audio_buf[LC3_MAX_NUM_SAMPLES_MONO];
-#endif /* CONFIG_USB_DEVICE_AUDIO */
-
-		k_sem_take(&lc3_decoder_sem, K_FOREVER);
-
-		for (size_t i = 0; i < ARRAY_SIZE(streams); i++) {
-			struct broadcast_sink_stream *stream = &streams[i];
-			const uint8_t frames_blocks_per_sdu = stream->lc3_frames_blocks_per_sdu;
-			const uint16_t octets_per_frame = stream->lc3_octets_per_frame;
-			uint16_t frames_per_block;
-			struct net_buf *buf;
-
-			k_mutex_lock(&stream->lc3_decoder_mutex, K_FOREVER);
-
-			if (stream->in_buf == NULL) {
-				k_mutex_unlock(&stream->lc3_decoder_mutex);
-
-				continue;
-			}
-
-			buf = net_buf_ref(stream->in_buf);
-			net_buf_unref(stream->in_buf);
-			stream->in_buf = NULL;
-			k_mutex_unlock(&stream->lc3_decoder_mutex);
-
-			frames_per_block = bt_audio_get_chan_count(stream->chan_allocation);
-			if (buf->len !=
-			    (frames_per_block * octets_per_frame * frames_blocks_per_sdu)) {
-				printk("Expected %u frame blocks with %u frames of size %u, but "
-				       "length is %u\n",
-				       frames_blocks_per_sdu, frames_per_block, octets_per_frame,
-				       buf->len);
-
-				net_buf_unref(buf);
-
-				continue;
-			}
-
-#if defined(CONFIG_USB_DEVICE_AUDIO)
-			const bool has_left =
-				(stream->chan_allocation & BT_AUDIO_LOCATION_FRONT_LEFT) != 0;
-			const bool has_right =
-				(stream->chan_allocation & BT_AUDIO_LOCATION_FRONT_RIGHT) != 0;
-			const bool is_mono =
-				stream->chan_allocation == BT_AUDIO_LOCATION_MONO_AUDIO;
-
-			/* Split the SDU into frames*/
-			for (uint8_t i = 0U; i < frames_blocks_per_sdu; i++) {
-				for (uint16_t j = 0U; j < frames_per_block; j++) {
-					const bool is_left = j == 0 && has_left;
-					const bool is_right =
-						has_right && (j == 0 || (j == 1 && has_left));
-					const void *data = net_buf_pull_mem(buf, octets_per_frame);
-					int16_t *out_frame;
-
-					if (is_left) {
-						out_frame = left_frames[left_frames_cnt++];
-					} else if (is_right) {
-						out_frame = right_frames[right_frames_cnt++];
-					} else if (is_mono) {
-						/* Use left as mono*/
-						out_frame = left_frames[left_frames_cnt++];
-					} else {
-						/* unused channel */
-						break;
-					}
-
-					do_lc3_decode(stream->lc3_decoder, data, octets_per_frame,
-						      out_frame);
-				}
-			}
-#else
-			/* Dummy behavior: Decode and discard data */
-			for (uint8_t i = 0U; i < frames_blocks_per_sdu; i++) {
-				for (uint16_t j = 0U; j < frames_per_block; j++) {
-					const void *data = net_buf_pull_mem(buf, octets_per_frame);
-
-					do_lc3_decode(stream->lc3_decoder, data, octets_per_frame,
-						      lc3_audio_buf);
-				}
-			}
-#endif /* CONFIG_USB_DEVICE_AUDIO */
-
-			net_buf_unref(buf);
-		}
-
-#if defined(CONFIG_USB_DEVICE_AUDIO)
-		const bool is_left_only = right_frames_cnt == 0U;
-		const bool is_right_only = left_frames_cnt == 0U;
-
-		if (!is_left_only && !is_right_only && left_frames_cnt != right_frames_cnt) {
-			printk("Mismatch between number of left (%zu) and right (%zu) frames, "
-			       "discard SDU",
-			       left_frames_cnt, right_frames_cnt);
-			continue;
-		}
-
-		/* Send frames to USB - If we only have a single channel we mix it to stereo */
-		for (size_t i = 0U; i < MAX(left_frames_cnt, right_frames_cnt); i++) {
-			const bool is_single_channel = is_left_only || is_right_only;
-			static int16_t stereo_frame[LC3_MAX_NUM_SAMPLES_STEREO];
-			int16_t *right_frame = right_frames[i];
-			int16_t *left_frame = left_frames[i];
-
-			/* Not enough space to store data */
-			if (ring_buf_space_get(&usb_ring_buf) < sizeof(stereo_frame)) {
-				break;
-			}
-
-			memset(stereo_frame, 0, sizeof(stereo_frame));
-
-			/* Generate the stereo frame
-			 *
-			 * If we only have single channel then that is always stored in the
-			 * left_frame, and we mix that to stereo
-			 */
-			for (int j = 0; j < LC3_MAX_NUM_SAMPLES_MONO; j++) {
-				if (is_single_channel) {
-					/* Mix to stereo */
-					if (is_left_only) {
-						stereo_frame[j * 2] = left_frame[j];
-						stereo_frame[j * 2 + 1] = left_frame[j];
-					} else if (is_right_only) {
-						stereo_frame[j * 2] = right_frame[j];
-						stereo_frame[j * 2 + 1] = right_frame[j];
-					}
-				} else {
-					stereo_frame[j * 2] = left_frame[j];
-					stereo_frame[j * 2 + 1] = right_frame[j];
-				}
-			}
-
-			add_to_usb_ring_buf(stereo_frame);
-		}
-#endif /* CONFIG_USB_DEVICE_AUDIO */
-	}
-}
-
-/** Decode LC3 data on a stream and returns true if successful */
-static void do_lc3_decode(lc3_decoder_t decoder, const void *in_data, uint8_t octets_per_frame,
-			  int16_t out_data[LC3_MAX_NUM_SAMPLES_MONO])
-{
-	int err;
-
-	err = lc3_decode(decoder, in_data, octets_per_frame, LC3_PCM_FORMAT_S16, out_data, 1);
-	if (err == 1) {
-		printk("  decoder performed PLC\n");
-	} else if (err < 0) {
-		printk("  decoder failed - wrong parameters? (err = %d)\n", err);
-	}
-}
-
-static int lc3_enable(struct broadcast_sink_stream *sink_stream)
+static void stream_connected_cb(struct bt_bap_stream *bap_stream)
 {
-	size_t chan_alloc_bit_cnt;
-	size_t sdu_size_required;
-	int frame_duration_us;
-	int freq_hz;
-	int ret;
-
-	printk("Enable: stream with codec %p\n", sink_stream->stream.codec_cfg);
-
-	ret = bt_audio_codec_cfg_get_freq(sink_stream->stream.codec_cfg);
-	if (ret > 0) {
-		freq_hz = bt_audio_codec_cfg_freq_to_freq_hz(ret);
-	} else {
-		printk("Error: Codec frequency not set, cannot start codec.");
-		return -1;
-	}
-
-	ret = bt_audio_codec_cfg_get_frame_dur(sink_stream->stream.codec_cfg);
-	if (ret > 0) {
-		frame_duration_us = bt_audio_codec_cfg_frame_dur_to_frame_dur_us(ret);
-	} else {
-		printk("Error: Frame duration not set, cannot start codec.");
-		return ret;
-	}
-
-	ret = bt_audio_codec_cfg_get_chan_allocation(sink_stream->stream.codec_cfg,
-						     &sink_stream->chan_allocation, true);
-	if (ret != 0) {
-		printk("Error: Channel allocation not set, invalid configuration for LC3");
-		return ret;
-	}
-
-	ret = bt_audio_codec_cfg_get_octets_per_frame(sink_stream->stream.codec_cfg);
-	if (ret > 0) {
-		sink_stream->lc3_octets_per_frame = (uint16_t)ret;
-	} else {
-		printk("Error: Octets per frame not set, invalid configuration for LC3");
-		return ret;
-	}
-
-	ret = bt_audio_codec_cfg_get_frame_blocks_per_sdu(sink_stream->stream.codec_cfg, true);
-	if (ret > 0) {
-		sink_stream->lc3_frames_blocks_per_sdu = (uint8_t)ret;
-	} else {
-		printk("Error: Frame blocks per SDU not set, invalid configuration for LC3");
-		return ret;
-	}
-
-	/* An SDU can consist of X frame blocks, each with Y frames (one per channel) of size Z in
-	 * them. The minimum SDU size required for this is X * Y * Z.
-	 */
-	chan_alloc_bit_cnt = bt_audio_get_chan_count(sink_stream->chan_allocation);
-	sdu_size_required = chan_alloc_bit_cnt * sink_stream->lc3_octets_per_frame *
-			    sink_stream->lc3_frames_blocks_per_sdu;
-	if (sdu_size_required > sink_stream->stream.qos->sdu) {
-		printk("With %zu channels and %u octets per frame and %u frames per block, SDUs "
-		       "shall be at minimum %zu, but the stream has been configured for %u",
-		       chan_alloc_bit_cnt, sink_stream->lc3_octets_per_frame,
-		       sink_stream->lc3_frames_blocks_per_sdu, sdu_size_required,
-		       sink_stream->stream.qos->sdu);
-
-		return -EINVAL;
-	}
-
-	printk("Enabling LC3 decoder with frame duration %uus, frequency %uHz and with channel "
-	       "allocation 0x%08X, %u octets per frame and %u frame blocks per SDU\n",
-	       frame_duration_us, freq_hz, sink_stream->chan_allocation,
-	       sink_stream->lc3_octets_per_frame, sink_stream->lc3_frames_blocks_per_sdu);
-
-#if defined(CONFIG_USB_DEVICE_AUDIO)
-	sink_stream->lc3_decoder = lc3_setup_decoder(frame_duration_us, freq_hz, USB_SAMPLE_RATE,
-						     &sink_stream->lc3_decoder_mem);
-#else
-	sink_stream->lc3_decoder = lc3_setup_decoder(frame_duration_us, freq_hz, 0,
-						     &sink_stream->lc3_decoder_mem);
-#endif /* defined(CONFIG_USB_DEVICE_AUDIO) */
-
-	if (sink_stream->lc3_decoder == NULL) {
-		printk("ERROR: Failed to setup LC3 decoder - wrong parameters?\n");
-		return -1;
-	}
-
-	k_thread_start(decoder_tid);
-
-	return 0;
-}
-#endif /* defined(CONFIG_LIBLC3) */
-
-#if defined(CONFIG_USB_DEVICE_AUDIO)
-/* Move the LC3 data to the USB ring buffer */
-static void add_to_usb_ring_buf(const int16_t audio_buf[LC3_MAX_NUM_SAMPLES_STEREO])
-{
-	uint32_t size;
-
-	size = ring_buf_put(&usb_ring_buf, (uint8_t *)audio_buf,
-			    LC3_MAX_NUM_SAMPLES_STEREO * sizeof(int16_t));
-	if (size != LC3_MAX_NUM_SAMPLES_STEREO) {
-		static int rb_put_failures;
-
-		rb_put_failures++;
-		if (rb_put_failures == LOG_INTERVAL) {
-			printk("%s: Failure to add to usb_ring_buf %d, %u\n", __func__,
-			       rb_put_failures, size);
-		}
-	}
-}
-
-/* USB consumer callback, called every 1ms, consumes data from ring-buffer */
-static void usb_data_request_cb(const struct device *dev)
-{
-	uint8_t usb_audio_data[USB_STEREO_SAMPLE_SIZE] = {0};
-	static struct net_buf *pcm_buf;
-	static size_t cnt;
-	int err;
-
-	ring_buf_get(&usb_ring_buf, (uint8_t *)usb_audio_data, sizeof(usb_audio_data));
-	/* Ignore ring_buf_get() return value, if size is 0 we send empty PCM frames to
-	 * not starve USB audio interface, if size is lower than USB_STEREO_SAMPLE_SIZE
-	 * we send frames padded with 0's as usb_audio_data is 0-initialized
-	 */
-
-	pcm_buf = net_buf_alloc(&usb_tx_buf_pool, K_NO_WAIT);
-	if (pcm_buf == NULL) {
-		printk("Could not allocate pcm_buf\n");
-		return;
-	}
-
-	net_buf_add_mem(pcm_buf, usb_audio_data, sizeof(usb_audio_data));
-
-	if (cnt % LOG_INTERVAL == 0) {
-		printk("Sending USB audio (count = %zu)\n", cnt);
-	}
-
-	err = usb_audio_send(dev, pcm_buf, USB_STEREO_SAMPLE_SIZE);
-	if (err) {
-		printk("Failed to send USB audio: %d\n", err);
-		net_buf_unref(pcm_buf);
-	}
-
-	cnt++;
-}
-
-static void usb_data_written_cb(const struct device *dev, struct net_buf *buf, size_t size)
-{
-	/* Unreference the buffer now that the USB is done with it */
-	net_buf_unref(buf);
-}
-#endif /* defined(CONFIG_USB_DEVICE_AUDIO) */
-
-static void stream_connected_cb(struct bt_bap_stream *stream)
-{
-	printk("Stream %p connected\n", stream);
+	printk("Stream %p connected\n", bap_stream);
 
 	k_sem_give(&sem_stream_connected);
 }
 
-static void stream_disconnected_cb(struct bt_bap_stream *stream, uint8_t reason)
+static void stream_disconnected_cb(struct bt_bap_stream *bap_stream, uint8_t reason)
 {
 	int err;
 
-	printk("Stream %p disconnected with reason 0x%02X\n", stream, reason);
+	printk("Stream %p disconnected with reason 0x%02X\n", bap_stream, reason);
 
 	err = k_sem_take(&sem_stream_connected, K_NO_WAIT);
 	if (err != 0) {
@@ -506,43 +120,30 @@ static void stream_disconnected_cb(struct bt_bap_stream *stream, uint8_t reason)
 	}
 }
 
-static void stream_started_cb(struct bt_bap_stream *stream)
+static void stream_started_cb(struct bt_bap_stream *bap_stream)
 {
-	struct broadcast_sink_stream *sink_stream =
-		CONTAINER_OF(stream, struct broadcast_sink_stream, stream);
-
-	printk("Stream %p started\n", stream);
-
-	total_rx_iso_packet_count = 0U;
-	sink_stream->recv_cnt = 0U;
-	sink_stream->loss_cnt = 0U;
-	sink_stream->valid_cnt = 0U;
-	sink_stream->error_cnt = 0U;
-
-#if defined(CONFIG_LIBLC3)
 	int err;
 
-	if (stream->codec_cfg != 0 && stream->codec_cfg->id != BT_HCI_CODING_FORMAT_LC3) {
-		/* No subgroups with LC3 was found */
-		printk("Did not parse an LC3 codec\n");
-		return;
-	}
+	printk("Stream %p started\n", bap_stream);
 
-	err = lc3_enable(sink_stream);
-	if (err < 0) {
-		printk("Error: cannot enable LC3 codec: %d", err);
-		return;
+	err = stream_rx_started(bap_stream);
+	if (err != 0) {
+		printk("stream_rx_started returned error: %d\n", err);
 	}
-#endif /* CONFIG_LIBLC3 */
 
 	k_sem_give(&sem_stream_started);
 }
 
-static void stream_stopped_cb(struct bt_bap_stream *stream, uint8_t reason)
+static void stream_stopped_cb(struct bt_bap_stream *bap_stream, uint8_t reason)
 {
 	int err;
 
-	printk("Stream %p stopped with reason 0x%02X\n", stream, reason);
+	printk("Stream %p stopped with reason 0x%02X\n", bap_stream, reason);
+
+	err = stream_rx_stopped(bap_stream);
+	if (err != 0) {
+		printk("stream_rx_stopped returned error: %d\n", err);
+	}
 
 	err = k_sem_take(&sem_stream_started, K_NO_WAIT);
 	if (err != 0) {
@@ -550,42 +151,10 @@ static void stream_stopped_cb(struct bt_bap_stream *stream, uint8_t reason)
 	}
 }
 
-static void stream_recv_cb(struct bt_bap_stream *stream, const struct bt_iso_recv_info *info,
+static void stream_recv_cb(struct bt_bap_stream *bap_stream, const struct bt_iso_recv_info *info,
 			   struct net_buf *buf)
 {
-	struct broadcast_sink_stream *sink_stream =
-		CONTAINER_OF(stream, struct broadcast_sink_stream, stream);
-
-	if (info->flags & BT_ISO_FLAGS_ERROR) {
-		sink_stream->error_cnt++;
-	}
-
-	if (info->flags & BT_ISO_FLAGS_LOST) {
-		sink_stream->loss_cnt++;
-	}
-
-	if (info->flags & BT_ISO_FLAGS_VALID) {
-		sink_stream->valid_cnt++;
-#if defined(CONFIG_LIBLC3)
-		k_mutex_lock(&sink_stream->lc3_decoder_mutex, K_FOREVER);
-		if (sink_stream->in_buf != NULL) {
-			net_buf_unref(sink_stream->in_buf);
-			sink_stream->in_buf = NULL;
-		}
-
-		sink_stream->in_buf = net_buf_ref(buf);
-		k_mutex_unlock(&sink_stream->lc3_decoder_mutex);
-		k_sem_give(&lc3_decoder_sem);
-#endif /* defined(CONFIG_LIBLC3) */
-	}
-
-	total_rx_iso_packet_count++;
-	sink_stream->recv_cnt++;
-	if ((sink_stream->recv_cnt % LOG_INTERVAL) == 0U) {
-		printk("Stream %p: received %u total ISO packets: Valid %u | Error %u | Loss %u\n",
-		       &sink_stream->stream, sink_stream->recv_cnt, sink_stream->valid_cnt,
-		       sink_stream->error_cnt, sink_stream->loss_cnt);
-	}
+	stream_rx_recv(bap_stream, info, buf);
 }
 
 static struct bt_bap_stream_ops stream_ops = {
@@ -1272,8 +841,13 @@ static struct bt_le_per_adv_sync_cb bap_pa_sync_cb = {
 	.term = bap_pa_sync_terminated_cb,
 };
 
+
 static int init(void)
 {
+	const struct bt_pacs_register_param pacs_param = {
+		.snk_pac = true,
+		.snk_loc = true,
+	};
 	int err;
 
 	err = bt_enable(NULL);
@@ -1284,6 +858,12 @@ static int init(void)
 
 	printk("Bluetooth initialized\n");
 
+	err = bt_pacs_register(&pacs_param);
+	if (err) {
+		printk("Could not register PACS (err %d)\n", err);
+		return err;
+	}
+
 	err = bt_pacs_cap_register(BT_AUDIO_DIR_SINK, &cap);
 	if (err) {
 		printk("Capability register failed (err %d)\n", err);
@@ -1300,30 +880,19 @@ static int init(void)
 	bt_le_per_adv_sync_cb_register(&bap_pa_sync_cb);
 	bt_le_scan_cb_register(&bap_scan_cb);
 
-	for (size_t i = 0U; i < ARRAY_SIZE(streams); i++) {
-		streams[i].stream.ops = &stream_ops;
-	}
+	stream_rx_get_streams(bap_streams_p);
 
-	/* Initialize ring buffers and USB */
-#if defined(CONFIG_USB_DEVICE_AUDIO)
-	const struct device *hs_dev = DEVICE_DT_GET(DT_NODELABEL(hs_0));
-	static const struct usb_audio_ops usb_ops = {
-		.data_request_cb = usb_data_request_cb,
-		.data_written_cb = usb_data_written_cb,
-	};
+	for (size_t i = 0U; i < CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT; i++) {
+		bt_bap_stream_cb_register(bap_streams_p[i], &stream_ops);
+	}
 
-	if (!device_is_ready(hs_dev)) {
-		printk("Cannot get USB Headset Device\n");
-		return -EIO;
+	if (IS_ENABLED(CONFIG_LIBLC3)) {
+		lc3_init();
 	}
 
-	usb_audio_register(hs_dev, &usb_ops);
-	err = usb_enable(NULL);
-	if (err && err != -EALREADY) {
-		printk("Failed to enable USB\n");
-		return err;
+	if (IS_ENABLED(CONFIG_USE_USB_AUDIO_OUTPUT)) {
+		usb_init();
 	}
-#endif /* defined(CONFIG_USB_DEVICE_AUDIO) */
 
 	return 0;
 }
@@ -1465,13 +1034,6 @@ int main(void)
 		return 0;
 	}
 
-	for (size_t i = 0U; i < ARRAY_SIZE(streams_p); i++) {
-		streams_p[i] = &streams[i].stream;
-#if defined(CONFIG_LIBLC3)
-		k_mutex_init(&streams[i].lc3_decoder_mutex);
-#endif /* defined(CONFIG_LIBLC3) */
-	}
-
 	while (true) {
 		uint32_t sync_bitfield;
 
@@ -1634,7 +1196,7 @@ int main(void)
 		       "(req_bis_sync), stream_count = %u\n",
 		       sync_bitfield, bis_index_bitfield, requested_bis_sync, stream_count);
 
-		err = bt_bap_broadcast_sink_sync(broadcast_sink, sync_bitfield, streams_p,
+		err = bt_bap_broadcast_sink_sync(broadcast_sink, sync_bitfield, bap_streams_p,
 						 sink_broadcast_code);
 		if (err != 0) {
 			printk("Unable to sync to broadcast source: %d\n", err);
diff --git a/samples/bluetooth/bap_broadcast_sink/src/stream_rx.c b/samples/bluetooth/bap_broadcast_sink/src/stream_rx.c
new file mode 100644
index 00000000000..1caaec5361c
--- /dev/null
+++ b/samples/bluetooth/bap_broadcast_sink/src/stream_rx.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <errno.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/audio/audio.h>
+#include <zephyr/bluetooth/audio/bap.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/bluetooth/iso.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/logging/log_core.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+
+#if defined(CONFIG_LIBLC3)
+#include <lc3.h>
+#endif /* defined(CONFIG_LIBLC3) */
+
+#include "stream_rx.h"
+#include "lc3.h"
+
+struct stream_rx rx_streams[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT];
+uint64_t total_rx_iso_packet_count; /* This value is exposed to test code */
+
+LOG_MODULE_REGISTER(stream_rx, CONFIG_LOG_DEFAULT_LEVEL);
+
+#if CONFIG_INFO_REPORTING_INTERVAL > 0
+static void log_stream_rx(const struct stream_rx *stream, const struct bt_iso_recv_info *info,
+			  const struct net_buf *buf)
+{
+	LOG_INF("[%zu]: Incoming audio on stream %p len %u, flags 0x%02X, seq_num %u and ts %u: "
+		"Valid %zu | Error %zu | Loss %zu | Dup TS %zu | Dup PSN %zu",
+		stream->reporting_info.recv_cnt, &stream->stream, buf->len, info->flags,
+		info->seq_num, info->ts, stream->reporting_info.valid_cnt,
+		stream->reporting_info.error_cnt, stream->reporting_info.loss_cnt,
+		stream->reporting_info.dup_ts_cnt, stream->reporting_info.dup_psn_cnt);
+}
+#endif /* CONFIG_INFO_REPORTING_INTERVAL > 0 */
+
+void stream_rx_recv(struct bt_bap_stream *bap_stream, const struct bt_iso_recv_info *info,
+		    struct net_buf *buf)
+{
+	struct stream_rx *stream = CONTAINER_OF(bap_stream, struct stream_rx, stream);
+
+#if CONFIG_INFO_REPORTING_INTERVAL > 0
+	if ((stream->reporting_info.recv_cnt % CONFIG_INFO_REPORTING_INTERVAL) == 0U) {
+		log_stream_rx(stream, info, buf);
+	}
+
+	if (stream->reporting_info.recv_cnt > 0U && info->ts == stream->reporting_info.last_ts) {
+		log_stream_rx(stream, info, buf);
+		LOG_WRN("Duplicated timestamp received: %u\n", stream->reporting_info.last_ts);
+		stream->reporting_info.dup_ts_cnt++;
+	}
+
+	if (stream->reporting_info.recv_cnt > 0U &&
+	    info->seq_num == stream->reporting_info.last_seq_num) {
+		log_stream_rx(stream, info, buf);
+		LOG_WRN("Duplicated PSN received: %u\n", stream->reporting_info.last_seq_num);
+		stream->reporting_info.dup_psn_cnt++;
+	}
+
+	if (info->flags & BT_ISO_FLAGS_ERROR) {
+		log_stream_rx(stream, info, buf);
+		LOG_DBG("ISO receive error\n");
+		stream->reporting_info.error_cnt++;
+	}
+
+	if (info->flags & BT_ISO_FLAGS_LOST) {
+		log_stream_rx(stream, info, buf);
+		LOG_DBG("ISO receive lost\n");
+		stream->reporting_info.loss_cnt++;
+	}
+
+	if (info->flags & BT_ISO_FLAGS_VALID) {
+		if (buf->len == 0U) {
+			stream->reporting_info.empty_sdu_cnt++;
+		} else {
+			stream->reporting_info.valid_cnt++;
+		}
+	}
+
+	stream->reporting_info.last_seq_num = info->seq_num;
+	stream->reporting_info.last_ts = info->ts;
+	stream->reporting_info.recv_cnt++;
+#endif /* CONFIG_INFO_REPORTING_INTERVAL > 0 */
+
+	total_rx_iso_packet_count++;
+
+	if (IS_ENABLED(CONFIG_LIBLC3)) {
+		/* Invalid SDUs will trigger PLC */
+		lc3_enqueue_for_decoding(stream, info, buf);
+	}
+}
+
+int stream_rx_started(struct bt_bap_stream *bap_stream)
+{
+	struct stream_rx *stream = CONTAINER_OF(bap_stream, struct stream_rx, stream);
+
+	if (stream == NULL) {
+		return -EINVAL;
+	}
+
+#if CONFIG_INFO_REPORTING_INTERVAL > 0
+	memset(&stream->reporting_info, 0, sizeof((stream->reporting_info)));
+#endif /* CONFIG_INFO_REPORTING_INTERVAL > 0 */
+
+	if (IS_ENABLED(CONFIG_LIBLC3) && bap_stream->codec_cfg != NULL &&
+	    bap_stream->codec_cfg->id == BT_HCI_CODING_FORMAT_LC3) {
+		int err;
+
+		err = lc3_enable(stream);
+		if (err < 0) {
+			LOG_ERR("Error: cannot enable LC3 codec: %d", err);
+			return err;
+		}
+	}
+
+	return 0;
+}
+
+int stream_rx_stopped(struct bt_bap_stream *bap_stream)
+{
+	struct stream_rx *stream = CONTAINER_OF(bap_stream, struct stream_rx, stream);
+
+	if (bap_stream == NULL) {
+		return -EINVAL;
+	}
+
+	if (IS_ENABLED(CONFIG_LIBLC3) && bap_stream->codec_cfg != NULL &&
+	    bap_stream->codec_cfg->id == BT_HCI_CODING_FORMAT_LC3) {
+		int err;
+
+		err = lc3_disable(stream);
+		if (err < 0) {
+			LOG_ERR("Error: cannot disable LC3 codec: %d", err);
+			return err;
+		}
+	}
+
+	return 0;
+}
+
+void stream_rx_get_streams(
+	struct bt_bap_stream *bap_streams[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT])
+{
+	for (size_t i = 0U; i < ARRAY_SIZE(rx_streams); i++) {
+		bap_streams[i] = &rx_streams[i].stream;
+	}
+}
diff --git a/samples/bluetooth/bap_broadcast_sink/src/stream_rx.h b/samples/bluetooth/bap_broadcast_sink/src/stream_rx.h
new file mode 100644
index 00000000000..b2afc643492
--- /dev/null
+++ b/samples/bluetooth/bap_broadcast_sink/src/stream_rx.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef SAMPLE_BAP_BROADCAST_SINK_STREAM_RX_H
+#define SAMPLE_BAP_BROADCAST_SINK_STREAM_RX_H
+
+#include <stddef.h>
+#include <stdint.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/audio/audio.h>
+#include <zephyr/bluetooth/audio/bap.h>
+#include <zephyr/bluetooth/iso.h>
+#include <zephyr/kernel.h>
+#include <zephyr/net_buf.h>
+
+#if defined(CONFIG_LIBLC3)
+#include <lc3.h>
+#endif /* defined(CONFIG_LIBLC3) */
+
+struct stream_rx {
+	/* A BAP stream object */
+	struct bt_bap_stream stream;
+#if CONFIG_INFO_REPORTING_INTERVAL > 0
+	/** Struct containing information useful for logging purposes */
+	struct {
+		/** Total Number of SDUs received */
+		size_t recv_cnt;
+		/** Number of lost SDUs */
+		size_t loss_cnt;
+		/** Number of SDUs containing errors */
+		size_t error_cnt;
+		/** Number of valid SDUs received */
+		size_t valid_cnt;
+		/** Number of empty SDUs received */
+		size_t empty_sdu_cnt;
+		/** Number of SDUs with duplicated packet sequence number received */
+		size_t dup_psn_cnt;
+		/** Number of SDUs with duplicated timestamps received */
+		size_t dup_ts_cnt;
+		/** The last received timestamp to track dup_ts_cnt */
+		uint32_t last_ts;
+		/** The last received sequence number to track dup_psn_cnt */
+		uint16_t last_seq_num;
+#if CONFIG_LIBLC3 > 0
+		/** Number of SDUs decoded  */
+		size_t lc3_decoded_cnt;
+#endif /* CONFIG_LIBLC3 > 0 */
+	} reporting_info;
+#endif /* CONFIG_INFO_REPORTING_INTERVAL > 0 */
+
+#if defined(CONFIG_LIBLC3)
+	/** Octets per frame - Used to validate that the incoming data is of correct size  */
+	uint16_t lc3_octets_per_frame;
+	/** Frame blocks per SDU - Used to split the SDU into frame blocks when decoding */
+	uint8_t lc3_frame_blocks_per_sdu;
+
+	/** Number of channels - Used to split the SDU into frame blocks when decoding */
+	uint8_t lc3_chan_cnt;
+
+	/**
+	 * @brief The configured channels of the stream
+	 *
+	 * Used to determine whether to send data to USB and count number of channels
+	 */
+	enum bt_audio_location lc3_chan_allocation;
+
+	/** Memory use for the LC3 decoder - Supports any configuration */
+	lc3_decoder_mem_48k_t lc3_decoder_mem;
+	/** Reference to the LC3 decoder */
+	lc3_decoder_t lc3_decoder;
+#endif /* defined(CONFIG_LIBLC3) */
+};
+
+/**
+ * @brief Function to call for each SDU received
+ *
+ * Will decode with LC3 and send to USB if enabled
+ */
+void stream_rx_recv(struct bt_bap_stream *bap_stream, const struct bt_iso_recv_info *info,
+		    struct net_buf *buf);
+
+size_t stream_rx_get_streaming_cnt(void);
+int stream_rx_started(struct bt_bap_stream *bap_stream);
+int stream_rx_stopped(struct bt_bap_stream *bap_stream);
+void stream_rx_get_streams(
+	struct bt_bap_stream *bap_streams[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT]);
+
+#endif /* SAMPLE_BAP_BROADCAST_SINK_STREAM_RX_H */
diff --git a/samples/bluetooth/bap_broadcast_sink/src/usb.c b/samples/bluetooth/bap_broadcast_sink/src/usb.c
new file mode 100644
index 00000000000..5dc2f825902
--- /dev/null
+++ b/samples/bluetooth/bap_broadcast_sink/src/usb.c
@@ -0,0 +1,376 @@
+/**
+ * @file
+ * @brief Bluetooth BAP Broadcast Sink Sample LC3
+ *
+ * This files handles all the USB related functionality to audio out for the Sample
+ *
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/audio/audio.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/usb/udc_buf.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/sys/ring_buffer.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/toolchain.h>
+#include <zephyr/usb/class/usbd_uac2.h>
+#include <zephyr/usb/usbd.h>
+
+#include <sample_usbd.h>
+
+#include "lc3.h"
+#include "usb.h"
+
+LOG_MODULE_REGISTER(usb, CONFIG_LOG_DEFAULT_LEVEL);
+
+#define USB_ENQUEUE_COUNT        30U /* 30 times 1ms frames => 30ms */
+#define USB_FRAME_DURATION_US    1000U
+#define USB_SAMPLE_CNT           ((USB_FRAME_DURATION_US * USB_SAMPLE_RATE_HZ) / USEC_PER_SEC)
+#define USB_BYTES_PER_SAMPLE     sizeof(int16_t)
+#define USB_MONO_FRAME_SIZE      (USB_SAMPLE_CNT * USB_BYTES_PER_SAMPLE)
+#define USB_CHANNELS             2U
+#define USB_STEREO_FRAME_SIZE    (USB_MONO_FRAME_SIZE * USB_CHANNELS)
+#define USB_OUT_RING_BUF_SIZE    (CONFIG_BT_ISO_RX_BUF_COUNT * LC3_MAX_NUM_SAMPLES_STEREO)
+#define USB_IN_RING_BUF_SIZE     (USB_MONO_FRAME_SIZE * USB_ENQUEUE_COUNT)
+
+#define IN_TERMINAL_ID UAC2_ENTITY_ID(DT_NODELABEL(in_terminal))
+
+struct decoded_sdu {
+	int16_t right_frames[CONFIG_MAX_CODEC_FRAMES_PER_SDU][LC3_MAX_NUM_SAMPLES_MONO];
+	int16_t left_frames[CONFIG_MAX_CODEC_FRAMES_PER_SDU][LC3_MAX_NUM_SAMPLES_MONO];
+	size_t right_frames_cnt;
+	size_t left_frames_cnt;
+	size_t mono_frames_cnt;
+	uint32_t ts;
+} decoded_sdu;
+
+RING_BUF_DECLARE(usb_out_ring_buf, USB_OUT_RING_BUF_SIZE);
+K_MEM_SLAB_DEFINE_STATIC(usb_out_buf_pool, ROUND_UP(USB_STEREO_FRAME_SIZE, UDC_BUF_GRANULARITY),
+			 USB_ENQUEUE_COUNT, UDC_BUF_ALIGN);
+static volatile bool terminal_enabled;
+
+/* USB consumer callback, called every 1ms, consumes data from ring-buffer */
+static void uac2_sof_cb(const struct device *dev, void *user_data)
+{
+	void *pcm_buf;
+	uint32_t size;
+	int err;
+
+	if (!terminal_enabled) {
+		/* Simply discard the data then */
+		(void)ring_buf_get(&usb_out_ring_buf, NULL, USB_STEREO_FRAME_SIZE);
+		return;
+	}
+
+	err = k_mem_slab_alloc(&usb_out_buf_pool, &pcm_buf, K_NO_WAIT);
+	if (err != 0) {
+		LOG_WRN("Could not allocate pcm_buf");
+		return;
+	}
+
+	size = ring_buf_get(&usb_out_ring_buf, pcm_buf, USB_STEREO_FRAME_SIZE);
+	if (size != USB_STEREO_FRAME_SIZE) {
+		/* If we could not fill the buffer, zero-fill the rest (possibly all) */
+		memset(((uint8_t *)pcm_buf) + size, 0, USB_STEREO_FRAME_SIZE - size);
+	}
+
+	if (CONFIG_INFO_REPORTING_INTERVAL > 0) {
+		if (size != 0) {
+			static size_t cnt;
+
+			if (++cnt % (CONFIG_INFO_REPORTING_INTERVAL * 10) == 0U) {
+				LOG_INF("[%zu]: Sending USB audio", cnt);
+			}
+		} else {
+			static size_t cnt;
+
+			if (++cnt % (CONFIG_INFO_REPORTING_INTERVAL * 10) == 0U) {
+				LOG_INF("[%zu]: Sending empty USB audio", cnt);
+			}
+		}
+	}
+
+	err = usbd_uac2_send(dev, IN_TERMINAL_ID, pcm_buf, USB_STEREO_FRAME_SIZE);
+	if (err != 0) {
+		if (CONFIG_INFO_REPORTING_INTERVAL > 0) {
+			static size_t cnt;
+
+			if (cnt++ % (CONFIG_INFO_REPORTING_INTERVAL * 10) == 0) {
+				LOG_ERR("[%zu]: Failed to send USB audio: %d", cnt, err);
+			}
+		}
+
+		k_mem_slab_free(&usb_out_buf_pool, pcm_buf);
+	} /* USB owns the buffer which will be released in uac2_buf_release_cb */
+}
+
+static void uac2_buf_release_cb(const struct device *dev, uint8_t terminal, void *buf,
+				void *user_data)
+{
+	k_mem_slab_free(&usb_out_buf_pool, buf);
+}
+
+static void terminal_update_cb(const struct device *dev, uint8_t terminal, bool enabled,
+			       bool microframes, void *user_data)
+{
+	terminal_enabled = enabled;
+}
+
+static void usb_send_frames_to_usb(void)
+{
+	const bool is_left_only =
+		decoded_sdu.right_frames_cnt == 0U && decoded_sdu.mono_frames_cnt == 0U;
+	const bool is_right_only =
+		decoded_sdu.left_frames_cnt == 0U && decoded_sdu.mono_frames_cnt == 0U;
+	const bool is_mono_only =
+		decoded_sdu.left_frames_cnt == 0U && decoded_sdu.right_frames_cnt == 0U;
+	const bool is_single_channel = is_left_only || is_right_only || is_mono_only;
+	const size_t frame_cnt =
+		MAX(decoded_sdu.mono_frames_cnt,
+		    MAX(decoded_sdu.left_frames_cnt, decoded_sdu.right_frames_cnt));
+	static size_t cnt;
+
+	/* Send frames to USB - If we only have a single channel we mix it to stereo */
+	for (size_t i = 0U; i < frame_cnt; i++) {
+		static int16_t stereo_frame[LC3_MAX_NUM_SAMPLES_STEREO];
+		const int16_t *right_frame = decoded_sdu.right_frames[i];
+		const int16_t *left_frame = decoded_sdu.left_frames[i];
+		const int16_t *mono_frame = decoded_sdu.left_frames[i]; /* use left as mono */
+		static size_t fail_cnt;
+		uint32_t rb_size;
+
+		/* Not enough space to store data */
+		if (ring_buf_space_get(&usb_out_ring_buf) < sizeof(stereo_frame)) {
+			if (CONFIG_INFO_REPORTING_INTERVAL > 0 &&
+			    (fail_cnt % CONFIG_INFO_REPORTING_INTERVAL) == 0U) {
+				LOG_WRN("[%zu] Could not send more than %zu frames to USB",
+					fail_cnt, i);
+			}
+
+			fail_cnt++;
+
+			break;
+		}
+
+		fail_cnt = 0U;
+
+		/* Generate the stereo frame
+		 *
+		 * If we only have single channel then we mix that to stereo
+		 */
+		for (int j = 0; j < LC3_MAX_NUM_SAMPLES_MONO; j++) {
+			if (is_single_channel) {
+				int16_t sample = 0;
+
+				/* Mix to stereo as LRLRLRLR */
+				if (is_left_only) {
+					sample = left_frame[j];
+				} else if (is_right_only) {
+					sample = right_frame[j];
+				} else if (is_mono_only) {
+					sample = mono_frame[j];
+				}
+
+				stereo_frame[j * 2] = sample;
+				stereo_frame[j * 2 + 1] = sample;
+			} else {
+				stereo_frame[j * 2] = left_frame[j];
+				stereo_frame[j * 2 + 1] = right_frame[j];
+			}
+		}
+
+		rb_size = ring_buf_put(&usb_out_ring_buf, (uint8_t *)stereo_frame,
+				       sizeof(stereo_frame));
+		if (rb_size != sizeof(stereo_frame)) {
+			LOG_WRN("Failed to put frame on USB ring buf");
+
+			break;
+		}
+	}
+
+	if (CONFIG_INFO_REPORTING_INTERVAL > 0 && (++cnt % CONFIG_INFO_REPORTING_INTERVAL) == 0U) {
+		LOG_INF("[%zu]: Sending %u USB audio frame", cnt, frame_cnt);
+	}
+
+	usb_clear_frames_to_usb();
+}
+
+static bool ts_overflowed(uint32_t ts)
+{
+	/* If the timestamp is a factor of 10 in difference, then we assume that TS overflowed
+	 * We cannot simply check if `ts < decoded_sdu.ts` as that could also indicate old data
+	 */
+	return ((uint64_t)ts * 10 < decoded_sdu.ts);
+}
+
+int usb_add_frame_to_usb(enum bt_audio_location chan_allocation, const int16_t *frame,
+			 size_t frame_size, uint32_t ts)
+{
+	const bool is_left = (chan_allocation & BT_AUDIO_LOCATION_FRONT_LEFT) != 0;
+	const bool is_right = (chan_allocation & BT_AUDIO_LOCATION_FRONT_RIGHT) != 0;
+	const bool is_mono = chan_allocation == BT_AUDIO_LOCATION_MONO_AUDIO;
+	const uint8_t ts_jitter_us = 100; /* timestamps may have jitter */
+	static size_t cnt;
+
+	if (!terminal_enabled) {
+		/* Simply discard the data then */
+		/* TODO: Consider if we still want to decode the incoming audio */
+		return 0;
+	}
+
+	if (CONFIG_INFO_REPORTING_INTERVAL > 0 && (++cnt % CONFIG_INFO_REPORTING_INTERVAL) == 0U) {
+		LOG_INF("[%zu]: Adding USB audio frame", cnt);
+	}
+
+	if (frame_size > LC3_MAX_NUM_SAMPLES_MONO * sizeof(int16_t) || frame_size == 0U) {
+		LOG_DBG("Invalid frame of size %zu", frame_size);
+
+		return -EINVAL;
+	}
+
+	if (bt_audio_get_chan_count(chan_allocation) != 1) {
+		LOG_DBG("Invalid channel allocation %d", chan_allocation);
+
+		return -EINVAL;
+	}
+
+	if (((is_left || is_right) && decoded_sdu.mono_frames_cnt != 0) ||
+	    (is_mono &&
+	     (decoded_sdu.left_frames_cnt != 0U || decoded_sdu.right_frames_cnt != 0U))) {
+		LOG_DBG("Cannot mix and match mono with left or right");
+
+		return -EINVAL;
+	}
+
+	/* Check if the frame can be combined with a previous frame from another channel, of if
+	 * we have to send previous data to USB and then store the current frame
+	 *
+	 * This is done by comparing the timestamps of the frames, and in the case that they are the
+	 * same, there are additional checks to see if we have received more left than right frames,
+	 * in which case we also send existing data
+	 */
+
+	if (ts + ts_jitter_us < decoded_sdu.ts && !ts_overflowed(ts)) {
+		/* Old data, discard */
+		return -ENOEXEC;
+	} else if (ts > decoded_sdu.ts + ts_jitter_us || ts_overflowed(ts)) {
+		/* We are getting new data - Send existing data to ring buffer */
+		usb_send_frames_to_usb();
+	} else { /* same timestamp */
+		bool send = false;
+
+		if (is_left && decoded_sdu.left_frames_cnt > decoded_sdu.right_frames_cnt) {
+			/* We are receiving left again before a right, send to USB */
+			send = true;
+		} else if (is_right && decoded_sdu.right_frames_cnt > decoded_sdu.left_frames_cnt) {
+			/* We are receiving right again before a left, send to USB */
+			send = true;
+		} else if (is_mono) {
+			/* always send mono as it comes */
+			send = true;
+		}
+
+		if (send) {
+			usb_send_frames_to_usb();
+		}
+	}
+
+	if (is_left) {
+		if (decoded_sdu.left_frames_cnt >= ARRAY_SIZE(decoded_sdu.left_frames)) {
+			LOG_WRN("Could not add more left frames");
+
+			return -ENOMEM;
+		}
+
+		memcpy(decoded_sdu.left_frames[decoded_sdu.left_frames_cnt++], frame, frame_size);
+	} else if (is_right) {
+		if (decoded_sdu.right_frames_cnt >= ARRAY_SIZE(decoded_sdu.right_frames)) {
+			LOG_WRN("Could not add more right frames");
+
+			return -ENOMEM;
+		}
+
+		memcpy(decoded_sdu.right_frames[decoded_sdu.right_frames_cnt++], frame, frame_size);
+	} else if (is_mono) {
+		/* Use left as mono*/
+		if (decoded_sdu.mono_frames_cnt >= ARRAY_SIZE(decoded_sdu.left_frames)) {
+			LOG_WRN("Could not add more mono frames");
+
+			return -ENOMEM;
+		}
+
+		memcpy(decoded_sdu.left_frames[decoded_sdu.mono_frames_cnt++], frame, frame_size);
+	} else {
+		/* Unsupported channel */
+		LOG_DBG("Unsupported channel %d", chan_allocation);
+
+		return -EINVAL;
+	}
+
+	decoded_sdu.ts = ts;
+
+	return 0;
+}
+
+void usb_clear_frames_to_usb(void)
+{
+	decoded_sdu.mono_frames_cnt = 0U;
+	decoded_sdu.right_frames_cnt = 0U;
+	decoded_sdu.left_frames_cnt = 0U;
+	decoded_sdu.ts = 0U;
+}
+
+int usb_init(void)
+{
+	const struct device *mic_dev = DEVICE_DT_GET(DT_NODELABEL(uac2_microphone));
+	static struct uac2_ops usb_audio_ops = {
+		.sof_cb = uac2_sof_cb,
+		.buf_release_cb = uac2_buf_release_cb,
+		.terminal_update_cb = terminal_update_cb,
+	};
+	struct usbd_context *sample_usbd;
+	static bool initialized;
+	int err;
+
+	if (initialized) {
+		return -EALREADY;
+	}
+
+	if (!device_is_ready(mic_dev)) {
+		LOG_ERR("Cannot get USB Microphone Device");
+		return -EIO;
+	}
+
+	usbd_uac2_set_ops(mic_dev, &usb_audio_ops, NULL);
+
+	sample_usbd = sample_usbd_init_device(NULL);
+	if (sample_usbd == NULL) {
+		return -ENODEV;
+	}
+
+	err = usbd_enable(sample_usbd);
+	if (err != 0) {
+		return err;
+	}
+
+	LOG_INF("USB initialized");
+	initialized = true;
+
+	return 0;
+}
diff --git a/samples/bluetooth/bap_broadcast_sink/src/usb.h b/samples/bluetooth/bap_broadcast_sink/src/usb.h
new file mode 100644
index 00000000000..e05a997c251
--- /dev/null
+++ b/samples/bluetooth/bap_broadcast_sink/src/usb.h
@@ -0,0 +1,71 @@
+/**
+ * @file
+ * @brief Bluetooth BAP Broadcast Sink sample USB header
+ *
+ * This files handles all the USB related functionality for the sample
+ *
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef SAMPLE_BAP_BROADCAST_SINK_USB_H
+#define SAMPLE_BAP_BROADCAST_SINK_USB_H
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/audio/audio.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/sys/ring_buffer.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/toolchain.h>
+#include <zephyr/usb/usb_device.h>
+#include <zephyr/usb/class/usb_audio.h>
+
+#define USB_SAMPLE_RATE_HZ 48000U
+
+/**
+ * @brief Add decoded frame to the USB buffer
+ *
+ * @param chan_allocation The channel of the frame (@ref BT_AUDIO_LOCATION_FRONT_LEFT, @ref
+ *                        BT_AUDIO_LOCATION_FRONT_RIGHT or @ref BT_AUDIO_LOCATION_MONO_AUDIO)
+ * @param frame The frame
+ * @param frame_size The size of @p in octets
+ * @param ts The timestamp of the frame
+ *
+ * @retval 0 Success
+ * @retval -EINVAL Invalid channel, frame of framesize
+ * @retval -ENOEXEC Old timestamp, discarded
+ * @retval -ENOMEM No memory to enqueue
+ */
+int usb_add_frame_to_usb(enum bt_audio_location chan_allocation, const int16_t *frame,
+			 size_t frame_size, uint32_t ts);
+
+/**
+ * @brief Clear last sent SDU
+ *
+ * If only part of the SDU could be decoded, this should be called
+ */
+void usb_clear_frames_to_usb(void);
+
+/**
+ * @brief Initialize the USB module
+ *
+ * This will start the USB thread if not already initialized
+ *
+ * @retval 0 Success
+ * @retval -EALREADY Already initialized
+ */
+int usb_init(void);
+
+#endif /* SAMPLE_BAP_BROADCAST_SINK_USB_H */
diff --git a/samples/bluetooth/bap_broadcast_source/CMakeLists.txt b/samples/bluetooth/bap_broadcast_source/CMakeLists.txt
index 66649d87a33..dc0187ae927 100644
--- a/samples/bluetooth/bap_broadcast_source/CMakeLists.txt
+++ b/samples/bluetooth/bap_broadcast_source/CMakeLists.txt
@@ -8,4 +8,6 @@ target_sources(app PRIVATE
   src/main.c
 )
 
-zephyr_library_include_directories(${ZEPHYR_BASE}/samples/bluetooth)
+if (CONFIG_USE_USB_AUDIO_INPUT)
+  include(${ZEPHYR_BASE}/samples/subsys/usb/common/common.cmake)
+endif()
diff --git a/samples/bluetooth/bap_broadcast_source/Kconfig b/samples/bluetooth/bap_broadcast_source/Kconfig
index 97ec40502f9..27e0fcf384c 100644
--- a/samples/bluetooth/bap_broadcast_source/Kconfig
+++ b/samples/bluetooth/bap_broadcast_source/Kconfig
@@ -29,13 +29,18 @@ config ENABLE_LC3
 	select LIBLC3
 	select FPU
 
+config ISO_PACKING_INTERLEAVED
+	bool "Use interleaved packing"
+	help
+	  Use interleaved packing between BIS ISO stream subevents.
+
 config USE_USB_AUDIO_INPUT
 	bool "Use USB Audio as input"
 	# By default, use the USB Audio path is disabled.
 	default n
 	depends on ENABLE_LC3
-	select USB_DEVICE_STACK
-	select USB_DEVICE_AUDIO
+	select USB_DEVICE_STACK_NEXT
+	select USBD_AUDIO2_CLASS
 	select RING_BUFFER
 
 config BROADCAST_CODE
@@ -59,4 +64,9 @@ config BROADCAST_ID
 	help
 	   This is the 3-octet broadcast ID advertised if static broadcast IDs are enabled.
 
+# Source common USB sample options used to initialize new experimental USB device stack.
+# The scope of these options is limited to USB samples in project tree,
+# you cannot use them in your own application.
+source "samples/subsys/usb/common/Kconfig.sample_usbd"
+
 source "Kconfig.zephyr"
diff --git a/samples/bluetooth/bap_broadcast_source/README.rst b/samples/bluetooth/bap_broadcast_source/README.rst
index 501f4231b98..7235ee8343e 100644
--- a/samples/bluetooth/bap_broadcast_source/README.rst
+++ b/samples/bluetooth/bap_broadcast_source/README.rst
@@ -31,6 +31,8 @@ Building and Running
 When building targeting an nrf52 series board with the Zephyr Bluetooth Controller,
 use ``-DEXTRA_CONF_FILE=overlay-bt_ll_sw_split.conf`` to enable the required ISO
 feature support.
+The sample defaults to sequential packing of BIS subevents, add
+``-DCONFIG_ISO_PACKING_INTERLEAVED=y`` to use interleaved packing.
 
 Building for an nrf5340dk
 -------------------------
diff --git a/samples/bluetooth/bap_broadcast_source/app.overlay b/samples/bluetooth/bap_broadcast_source/app.overlay
new file mode 100644
index 00000000000..2293f07f821
--- /dev/null
+++ b/samples/bluetooth/bap_broadcast_source/app.overlay
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/usb/audio.h>
+
+/ {
+	uac2_broadcaster: usb_audio2 {
+		compatible = "zephyr,uac2";
+		status = "okay";
+		full-speed;
+		audio-function = <AUDIO_FUNCTION_OTHER>;
+
+		/* Clock supporting 48KHz
+		 *
+		 * For simplicity we claim support for 48KHz only and then downsample if needed
+		 */
+		uac_aclk: aclk {
+			compatible = "zephyr,uac2-clock-source";
+			clock-type = "internal-programmable";
+			frequency-control = "read-only";
+			sampling-frequencies = <48000>;
+			/* Falsely claim synchronous audio because we
+			 * currently don't calculate feedback value
+			 */
+			sof-synchronized;
+		};
+
+		/* USB Audio terminal from USB host to USB device */
+		out_terminal: out_terminal {
+			compatible = "zephyr,uac2-input-terminal";
+			clock-source = <&uac_aclk>;
+			terminal-type = <USB_TERMINAL_STREAMING>;
+			front-left;
+			front-right;
+		};
+
+		/* The broadcaster_output terminal defines what we are sending over Bluetooth */
+		broadcaster_output: headphones {
+			compatible = "zephyr,uac2-output-terminal";
+			data-source = <&out_terminal>;
+			clock-source = <&uac_aclk>;
+			terminal-type = <OUTPUT_TERMINAL_UNDEFINED>;
+		};
+
+		as_iso_out: out_interface {
+			compatible = "zephyr,uac2-audio-streaming";
+			linked-terminal = <&out_terminal>;
+			subslot-size = <2>;
+			bit-resolution = <16>;
+		};
+	};
+};
diff --git a/samples/bluetooth/bap_broadcast_source/boards/nrf52833dk_nrf52833.conf b/samples/bluetooth/bap_broadcast_source/boards/nrf52833dk_nrf52833.conf
index 8b65fa9a9d8..54c9145ae9f 100644
--- a/samples/bluetooth/bap_broadcast_source/boards/nrf52833dk_nrf52833.conf
+++ b/samples/bluetooth/bap_broadcast_source/boards/nrf52833dk_nrf52833.conf
@@ -1,3 +1,3 @@
 # Use USB Audio as audio source
 CONFIG_USE_USB_AUDIO_INPUT=y
-CONFIG_USB_DEVICE_PRODUCT="Zephyr Broadcast Source"
+CONFIG_SAMPLE_USBD_PRODUCT="USB Broadcast Source sample"
diff --git a/samples/bluetooth/bap_broadcast_source/boards/nrf52833dk_nrf52833.overlay b/samples/bluetooth/bap_broadcast_source/boards/nrf52833dk_nrf52833.overlay
index b8e72f1b61c..94b67c37c70 100644
--- a/samples/bluetooth/bap_broadcast_source/boards/nrf52833dk_nrf52833.overlay
+++ b/samples/bluetooth/bap_broadcast_source/boards/nrf52833dk_nrf52833.overlay
@@ -1,15 +1,7 @@
-zephyr_udc0: &usbd {
-	compatible = "nordic,nrf-usbd";
-	status = "okay";
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
-	hs_0: hs_0 {
-		compatible = "usb-audio-hs";
-		mic-feature-mute;
-		mic-channel-l;
-		mic-channel-r;
-
-		hp-feature-mute;
-		hp-channel-l;
-		hp-channel-r;
-	};
-};
+#include "../app.overlay"
diff --git a/samples/bluetooth/bap_broadcast_source/boards/nrf52840dk_nrf52840.conf b/samples/bluetooth/bap_broadcast_source/boards/nrf52840dk_nrf52840.conf
new file mode 100644
index 00000000000..54c9145ae9f
--- /dev/null
+++ b/samples/bluetooth/bap_broadcast_source/boards/nrf52840dk_nrf52840.conf
@@ -0,0 +1,3 @@
+# Use USB Audio as audio source
+CONFIG_USE_USB_AUDIO_INPUT=y
+CONFIG_SAMPLE_USBD_PRODUCT="USB Broadcast Source sample"
diff --git a/samples/bluetooth/bap_broadcast_source/boards/nrf52840dk_nrf52840.overlay b/samples/bluetooth/bap_broadcast_source/boards/nrf52840dk_nrf52840.overlay
new file mode 100644
index 00000000000..94b67c37c70
--- /dev/null
+++ b/samples/bluetooth/bap_broadcast_source/boards/nrf52840dk_nrf52840.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../app.overlay"
diff --git a/samples/bluetooth/bap_broadcast_source/boards/nrf52840dongle_nrf52840.conf b/samples/bluetooth/bap_broadcast_source/boards/nrf52840dongle_nrf52840.conf
index 8b65fa9a9d8..39522210d28 100644
--- a/samples/bluetooth/bap_broadcast_source/boards/nrf52840dongle_nrf52840.conf
+++ b/samples/bluetooth/bap_broadcast_source/boards/nrf52840dongle_nrf52840.conf
@@ -1,3 +1,5 @@
 # Use USB Audio as audio source
 CONFIG_USE_USB_AUDIO_INPUT=y
-CONFIG_USB_DEVICE_PRODUCT="Zephyr Broadcast Source"
+CONFIG_SAMPLE_USBD_PRODUCT="USB Broadcast Source sample"
+
+CONFIG_BOARD_SERIAL_BACKEND_CDC_ACM=n
diff --git a/samples/bluetooth/bap_broadcast_source/boards/nrf52840dongle_nrf52840.overlay b/samples/bluetooth/bap_broadcast_source/boards/nrf52840dongle_nrf52840.overlay
index b8e72f1b61c..94b67c37c70 100644
--- a/samples/bluetooth/bap_broadcast_source/boards/nrf52840dongle_nrf52840.overlay
+++ b/samples/bluetooth/bap_broadcast_source/boards/nrf52840dongle_nrf52840.overlay
@@ -1,15 +1,7 @@
-zephyr_udc0: &usbd {
-	compatible = "nordic,nrf-usbd";
-	status = "okay";
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
-	hs_0: hs_0 {
-		compatible = "usb-audio-hs";
-		mic-feature-mute;
-		mic-channel-l;
-		mic-channel-r;
-
-		hp-feature-mute;
-		hp-channel-l;
-		hp-channel-r;
-	};
-};
+#include "../app.overlay"
diff --git a/samples/bluetooth/bap_broadcast_source/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf b/samples/bluetooth/bap_broadcast_source/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf
index 8b65fa9a9d8..54c9145ae9f 100644
--- a/samples/bluetooth/bap_broadcast_source/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf
+++ b/samples/bluetooth/bap_broadcast_source/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf
@@ -1,3 +1,3 @@
 # Use USB Audio as audio source
 CONFIG_USE_USB_AUDIO_INPUT=y
-CONFIG_USB_DEVICE_PRODUCT="Zephyr Broadcast Source"
+CONFIG_SAMPLE_USBD_PRODUCT="USB Broadcast Source sample"
diff --git a/samples/bluetooth/bap_broadcast_source/boards/nrf5340_audio_dk_nrf5340_cpuapp.overlay b/samples/bluetooth/bap_broadcast_source/boards/nrf5340_audio_dk_nrf5340_cpuapp.overlay
new file mode 100644
index 00000000000..94b67c37c70
--- /dev/null
+++ b/samples/bluetooth/bap_broadcast_source/boards/nrf5340_audio_dk_nrf5340_cpuapp.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../app.overlay"
diff --git a/samples/bluetooth/bap_broadcast_source/boards/nrf5340_audio_dk_nrf5340_cpuapp_nrf21540_ek.overlay b/samples/bluetooth/bap_broadcast_source/boards/nrf5340_audio_dk_nrf5340_cpuapp_nrf21540_ek.overlay
new file mode 100644
index 00000000000..d35e19ce79b
--- /dev/null
+++ b/samples/bluetooth/bap_broadcast_source/boards/nrf5340_audio_dk_nrf5340_cpuapp_nrf21540_ek.overlay
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include "../app.overlay"
+
+/ {
+	gpio_fwd: nrf-gpio-forwarder {
+		compatible = "nordic,nrf-gpio-forwarder";
+		status = "okay";
+
+		nrf21540-gpio-if {
+			gpios = <&arduino_header 11 0>, /* tx-en-gpios */
+				<&arduino_header 9  0>, /* rx-en-gpios */
+				<&arduino_header 15 0>,	/* pdn-gpios */
+				<&arduino_header 10 0>, /* ant-sel-gpios */
+				<&arduino_header 8  0>; /* mode-gpios */
+		};
+
+		nrf21540-spi-if {
+			gpios = <&arduino_header 16 0>, /* cs-gpios */
+				<&gpio0          8  0>, /* SPIM_SCK */
+				<&gpio0          10 0>, /* SPIM_MISO */
+				<&gpio0          9  0>; /* SPIM_MOSI */
+		};
+	};
+};
diff --git a/samples/bluetooth/bap_broadcast_source/boards/nrf5340dk_nrf5340_cpuapp.conf b/samples/bluetooth/bap_broadcast_source/boards/nrf5340dk_nrf5340_cpuapp.conf
index 8b65fa9a9d8..54c9145ae9f 100644
--- a/samples/bluetooth/bap_broadcast_source/boards/nrf5340dk_nrf5340_cpuapp.conf
+++ b/samples/bluetooth/bap_broadcast_source/boards/nrf5340dk_nrf5340_cpuapp.conf
@@ -1,3 +1,3 @@
 # Use USB Audio as audio source
 CONFIG_USE_USB_AUDIO_INPUT=y
-CONFIG_USB_DEVICE_PRODUCT="Zephyr Broadcast Source"
+CONFIG_SAMPLE_USBD_PRODUCT="USB Broadcast Source sample"
diff --git a/samples/bluetooth/bap_broadcast_source/boards/nrf5340dk_nrf5340_cpuapp.overlay b/samples/bluetooth/bap_broadcast_source/boards/nrf5340dk_nrf5340_cpuapp.overlay
index b8e72f1b61c..94b67c37c70 100644
--- a/samples/bluetooth/bap_broadcast_source/boards/nrf5340dk_nrf5340_cpuapp.overlay
+++ b/samples/bluetooth/bap_broadcast_source/boards/nrf5340dk_nrf5340_cpuapp.overlay
@@ -1,15 +1,7 @@
-zephyr_udc0: &usbd {
-	compatible = "nordic,nrf-usbd";
-	status = "okay";
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 
-	hs_0: hs_0 {
-		compatible = "usb-audio-hs";
-		mic-feature-mute;
-		mic-channel-l;
-		mic-channel-r;
-
-		hp-feature-mute;
-		hp-channel-l;
-		hp-channel-r;
-	};
-};
+#include "../app.overlay"
diff --git a/samples/bluetooth/bap_broadcast_source/overlay-bt_ll_sw_split.conf b/samples/bluetooth/bap_broadcast_source/overlay-bt_ll_sw_split.conf
index 3711a349213..4e873d42cb2 100644
--- a/samples/bluetooth/bap_broadcast_source/overlay-bt_ll_sw_split.conf
+++ b/samples/bluetooth/bap_broadcast_source/overlay-bt_ll_sw_split.conf
@@ -6,6 +6,8 @@ CONFIG_BT_CTLR_ADV_DATA_LEN_MAX=191
 
 # Enable support for Broadcast ISO in Zephyr Bluetooth Controller
 CONFIG_BT_CTLR_ADV_ISO=y
+CONFIG_BT_CTLR_ADV_ISO_SEQUENTIAL=y
+CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED=y
 
 # Sufficient ISO PDU length for any BAP LC3 presets (155)
 CONFIG_BT_CTLR_ADV_ISO_PDU_LEN_MAX=155
@@ -18,3 +20,4 @@ CONFIG_BT_CTLR_ISOAL_SOURCES=2
 # packet overhead (the Packet_Sequence_Number, ISO_SDU_Length, Packet_Status_Flag fields; and
 # the optional Time_Stamp field, if supplied)
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=163
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=155
diff --git a/samples/bluetooth/bap_broadcast_source/overlay-interleaved.conf b/samples/bluetooth/bap_broadcast_source/overlay-interleaved.conf
new file mode 100644
index 00000000000..3e5f87fa69b
--- /dev/null
+++ b/samples/bluetooth/bap_broadcast_source/overlay-interleaved.conf
@@ -0,0 +1 @@
+CONFIG_ISO_PACKING_INTERLEAVED=y
diff --git a/samples/bluetooth/bap_broadcast_source/overlay-sequential.conf b/samples/bluetooth/bap_broadcast_source/overlay-sequential.conf
new file mode 100644
index 00000000000..5ce5226aef9
--- /dev/null
+++ b/samples/bluetooth/bap_broadcast_source/overlay-sequential.conf
@@ -0,0 +1 @@
+CONFIG_ISO_PACKING_INTERLEAVED=n
diff --git a/samples/bluetooth/bap_broadcast_source/prj.conf b/samples/bluetooth/bap_broadcast_source/prj.conf
index 8daf74f8571..34d636f7e0f 100644
--- a/samples/bluetooth/bap_broadcast_source/prj.conf
+++ b/samples/bluetooth/bap_broadcast_source/prj.conf
@@ -11,6 +11,9 @@ CONFIG_BT_BAP_BROADCAST_SRC_STREAM_COUNT=2
 # Two streams in one subgroup (stereo)
 CONFIG_BT_BAP_BROADCAST_SRC_SUBGROUP_COUNT=1
 
+# Uncomment below to use Broadcast ISO interleaved packing
+# CONFIG_ISO_PACKING_INTERLEAVED=y
+
 CONFIG_BT_ISO_TX_BUF_COUNT=6
 CONFIG_BT_ISO_TX_MTU=60
 
diff --git a/samples/bluetooth/bap_broadcast_source/sample.yaml b/samples/bluetooth/bap_broadcast_source/sample.yaml
index 37008007c92..5f745cd0895 100644
--- a/samples/bluetooth/bap_broadcast_source/sample.yaml
+++ b/samples/bluetooth/bap_broadcast_source/sample.yaml
@@ -14,6 +14,17 @@ tests:
       - nrf5340dk/nrf5340/cpuapp
     tags: bluetooth
     sysbuild: true
+  sample.bluetooth.bap_broadcast_source.nrf5340_audio_dk_cpuapp.fem:
+    harness: bluetooth
+    platform_allow:
+      - nrf5340_audio_dk/nrf5340/cpuapp
+    integration_platforms:
+      - nrf5340_audio_dk/nrf5340/cpuapp
+    extra_args:
+      - DTC_OVERLAY_FILE=boards/nrf5340_audio_dk_nrf5340_cpuapp_nrf21540_ek.overlay
+      - hci_ipc_DTC_OVERLAY_FILE=boards/nrf5340_audio_dk_nrf5340_cpunet_nrf21540_ek.overlay
+    tags: bluetooth
+    sysbuild: true
   sample.bluetooth.bap_broadcast_source.bt_ll_sw_split:
     harness: bluetooth
     platform_allow:
diff --git a/samples/bluetooth/bap_broadcast_source/src/main.c b/samples/bluetooth/bap_broadcast_source/src/main.c
index 9448f91e330..30ca1a5026c 100644
--- a/samples/bluetooth/bap_broadcast_source/src/main.c
+++ b/samples/bluetooth/bap_broadcast_source/src/main.c
@@ -15,17 +15,22 @@
 #include <zephyr/bluetooth/audio/bap_lc3_preset.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/byteorder.h>
+#include <zephyr/bluetooth/crypto.h>
 #include <zephyr/bluetooth/gap.h>
 #include <zephyr/bluetooth/iso.h>
 #include <zephyr/bluetooth/uuid.h>
 #include <zephyr/device.h>
 #include <zephyr/devicetree.h>
+#include <zephyr/drivers/usb/udc_buf.h>
 #include <zephyr/kernel.h>
 #include <zephyr/net_buf.h>
+#include <zephyr/sys/__assert.h>
 #include <zephyr/sys/printk.h>
 #include <zephyr/sys/util.h>
 #include <zephyr/sys_clock.h>
 #include <zephyr/toolchain.h>
+#include <zephyr/usb/class/usbd_uac2.h>
+#include <zephyr/usb/usbd.h>
 
 BUILD_ASSERT(strlen(CONFIG_BROADCAST_CODE) <= BT_ISO_BROADCAST_CODE_SIZE, "Invalid broadcast code");
 
@@ -68,22 +73,31 @@ static struct bt_bap_lc3_preset preset_active = BT_BAP_LC3_BROADCAST_PRESET_24_2
 #if defined(CONFIG_LIBLC3)
 #include "lc3.h"
 
-#if defined(CONFIG_USB_DEVICE_AUDIO)
+#if defined(CONFIG_USE_USB_AUDIO_INPUT)
 #include <zephyr/usb/usb_device.h>
 #include <zephyr/usb/class/usb_audio.h>
 #include <zephyr/sys/ring_buffer.h>
 
+#include <sample_usbd.h>
+
 /* USB Audio Data is downsampled from 48kHz to match broadcast preset when receiving data */
-#define USB_SAMPLE_RATE       48000
-#define USB_DOWNSAMPLE_RATE   BROADCAST_SAMPLE_RATE
-#define USB_FRAME_DURATION_US 1000
-#define USB_NUM_SAMPLES       ((USB_FRAME_DURATION_US * USB_DOWNSAMPLE_RATE) / USEC_PER_SEC)
-#define USB_BYTES_PER_SAMPLE  2
-#define USB_CHANNELS          2
+#define USB_SAMPLE_RATE           48000
+#define USB_DOWNSAMPLE_RATE       BROADCAST_SAMPLE_RATE
+#define USB_FRAME_DURATION_US     1000
+#define USB_SAMPLE_CNT            ((USB_FRAME_DURATION_US * USB_SAMPLE_RATE) / USEC_PER_SEC)
+#define USB_DOWNSSAMPLE_CNT       ((USB_FRAME_DURATION_US * USB_DOWNSAMPLE_RATE) / USEC_PER_SEC)
+#define USB_BYTES_PER_SAMPLE      2
+#define USB_CHANNELS              2
+#define USB_MONO_FRAME_SIZE       (USB_SAMPLE_CNT * USB_BYTES_PER_SAMPLE)
+/* The number of samples received may be USB_SAMPLE_CNT -+ 1 */
+#define USB_MAX_MONO_FRAME_SIZE   ((USB_SAMPLE_CNT + 1) * USB_BYTES_PER_SAMPLE)
+#define USB_STEREO_FRAME_SIZE     (USB_MONO_FRAME_SIZE * USB_CHANNELS)
+#define USB_MAX_STEREO_FRAME_SIZE (USB_MAX_MONO_FRAME_SIZE * USB_CHANNELS)
+#define USB_ENQUEUE_COUNT         30U /* 30 times 1ms frames => 30ms */
 
 #define RING_BUF_USB_FRAMES  20
-#define AUDIO_RING_BUF_BYTES (USB_NUM_SAMPLES * USB_BYTES_PER_SAMPLE * RING_BUF_USB_FRAMES)
-#else /* !defined(CONFIG_USB_DEVICE_AUDIO) */
+#define AUDIO_RING_BUF_BYTES (USB_DOWNSSAMPLE_CNT * USB_BYTES_PER_SAMPLE * RING_BUF_USB_FRAMES)
+#else /* !defined(CONFIG_USE_USB_AUDIO_INPUT) */
 
 #include <math.h>
 
@@ -110,7 +124,7 @@ static void fill_audio_buf_sin(int16_t *buf, int length_us, int frequency_hz, in
 		buf[i] = (int16_t)(AUDIO_VOLUME * sample);
 	}
 }
-#endif /* defined(CONFIG_USB_DEVICE_AUDIO) */
+#endif /* defined(CONFIG_USE_USB_AUDIO_INPUT) */
 #endif /* defined(CONFIG_LIBLC3) */
 
 static struct broadcast_source_stream {
@@ -124,10 +138,10 @@ static struct broadcast_source_stream {
 #elif defined(CONFIG_BAP_BROADCAST_24_2_1)
 	lc3_encoder_mem_48k_t lc3_encoder_mem;
 #endif
-#if defined(CONFIG_USB_DEVICE_AUDIO)
+#if defined(CONFIG_USE_USB_AUDIO_INPUT)
 	struct ring_buf audio_ring_buf;
 	uint8_t _ring_buffer_memory[AUDIO_RING_BUF_BYTES];
-#endif /* defined(CONFIG_USB_DEVICE_AUDIO) */
+#endif /* defined(CONFIG_USE_USB_AUDIO_INPUT) */
 #endif /* defined(CONFIG_LIBLC3) */
 } streams[CONFIG_BT_BAP_BROADCAST_SRC_STREAM_COUNT];
 static struct bt_bap_broadcast_source *broadcast_source;
@@ -179,7 +193,7 @@ static void send_data(struct broadcast_source_stream *source_stream)
 		return;
 	}
 
-#if defined(CONFIG_USB_DEVICE_AUDIO)
+#if defined(CONFIG_USE_USB_AUDIO_INPUT)
 	uint32_t size = ring_buf_get(&source_stream->audio_ring_buf, (uint8_t *)send_pcm_data,
 				     sizeof(send_pcm_data));
 
@@ -257,7 +271,7 @@ static void init_lc3_thread(void *arg1, void *arg2, void *arg3)
 		return;
 	}
 
-#if !defined(CONFIG_USB_DEVICE_AUDIO)
+#if !defined(CONFIG_USE_USB_AUDIO_INPUT)
 	/* If USB is not used as a sound source, generate a sine wave */
 	fill_audio_buf_sin(send_pcm_data, frame_duration_us, AUDIO_TONE_FREQUENCY_HZ, freq_hz);
 #endif
@@ -289,28 +303,62 @@ static void init_lc3_thread(void *arg1, void *arg2, void *arg3)
 K_THREAD_DEFINE(encoder, LC3_ENCODER_STACK_SIZE, init_lc3_thread, NULL, NULL, NULL,
 		LC3_ENCODER_PRIORITY, 0, -1);
 
-#if defined(CONFIG_USB_DEVICE_AUDIO)
-static void data_received(const struct device *dev, struct net_buf *buffer, size_t size)
+#if defined(CONFIG_USE_USB_AUDIO_INPUT)
+/* Allocate 3: 1 for USB to receive data to and 2 additional buffers to prevent out of memory
+ * errors when USB host decides to perform rapid terminal enable/disable cycles.
+ */
+K_MEM_SLAB_DEFINE_STATIC(usb_in_buf_pool, USB_MAX_STEREO_FRAME_SIZE, 3, UDC_BUF_ALIGN);
+static bool terminal_enabled;
+
+static void terminal_update_cb(const struct device *dev, uint8_t terminal, bool enabled,
+			       bool microframes, void *user_data)
 {
-	static int count;
-	int16_t *pcm;
-	int nsamples, ratio;
-	int16_t usb_pcm_data[USB_CHANNELS][USB_NUM_SAMPLES];
+	terminal_enabled = enabled;
+}
 
-	if (!buffer) {
-		return;
+static void uac2_sof_cb(const struct device *dev, void *user_data)
+{
+	/* no-op, but has to be registered */
+}
+
+static void *get_recv_buf_cb(const struct device *dev, uint8_t terminal, uint16_t size,
+			     void *user_data)
+{
+	void *buf = NULL;
+	int ret;
+
+	if (!terminal_enabled) {
+		return NULL;
+	}
+
+	__ASSERT(size <= USB_MAX_STEREO_FRAME_SIZE, "%u was not <= %d", size,
+		 USB_MAX_STEREO_FRAME_SIZE);
+
+	ret = k_mem_slab_alloc(&usb_in_buf_pool, &buf, K_NO_WAIT);
+	if (ret != 0) {
+		printk("Failed to allocate buffer: %d\n", ret);
 	}
 
-	if (!size) {
-		net_buf_unref(buffer);
+	return buf;
+}
+
+static void data_recv_cb(const struct device *dev, uint8_t terminal, void *buf, uint16_t size,
+			 void *user_data)
+{
+	int16_t usb_pcm_data[USB_CHANNELS][USB_DOWNSSAMPLE_CNT];
+	int nsamples, ratio;
+	static int count;
+	int16_t *pcm;
+
+	if (!terminal_enabled || buf == NULL || size == 0U) {
+		k_mem_slab_free(&usb_in_buf_pool, buf);
 		return;
 	}
 
-	pcm = (int16_t *)net_buf_pull_mem(buffer, size);
+	pcm = (int16_t *)buf;
 
 	/* 'size' is in bytes, containing 1ms, 48kHz, stereo, 2 bytes per sample.
-	 * Take left channel and do a simple downsample to 16kHz/24Khz
-	 * matching the broadcast preset.
+	 * Do a simple downsample to 16kHz/24Khz matching the broadcast preset.
 	 */
 
 	ratio = USB_SAMPLE_RATE / USB_DOWNSAMPLE_RATE;
@@ -333,15 +381,13 @@ static void data_received(const struct device *dev, struct net_buf *buffer, size
 	}
 
 	count++;
-	if ((count % 1000) == 0) {
+	if ((count % 10000) == 0) {
 		printk("USB Data received (count = %d)\n", count);
 	}
 
-	net_buf_unref(buffer);
+	k_mem_slab_free(&usb_in_buf_pool, buf);
 }
-
-static const struct usb_audio_ops ops = {.data_received_cb = data_received};
-#endif /* defined(CONFIG_USB_DEVICE_AUDIO) */
+#endif /* defined(CONFIG_USE_USB_AUDIO_INPUT) */
 #endif /* defined(CONFIG_LIBLC3) */
 
 static void stream_started_cb(struct bt_bap_stream *stream)
@@ -402,7 +448,9 @@ static int setup_broadcast_source(struct bt_bap_broadcast_source **source)
 	create_param.params = subgroup_param;
 	create_param.qos = &preset_active.qos;
 	create_param.encryption = strlen(CONFIG_BROADCAST_CODE) > 0;
-	create_param.packing = BT_ISO_PACKING_SEQUENTIAL;
+	create_param.packing = (IS_ENABLED(CONFIG_ISO_PACKING_INTERLEAVED) ?
+				BT_ISO_PACKING_INTERLEAVED :
+				BT_ISO_PACKING_SEQUENTIAL);
 
 	if (create_param.encryption) {
 		memcpy(create_param.broadcast_code, CONFIG_BROADCAST_CODE,
@@ -461,14 +509,19 @@ int main(void)
 	}
 
 #if defined(CONFIG_LIBLC3)
-#if defined(CONFIG_USB_DEVICE_AUDIO)
-	const struct device *hs_dev;
-
-	hs_dev = DEVICE_DT_GET(DT_NODELABEL(hs_0));
+#if defined(CONFIG_USE_USB_AUDIO_INPUT)
+	const struct device *broadcaster_dev = DEVICE_DT_GET(DT_NODELABEL(uac2_broadcaster));
+	static struct uac2_ops usb_audio_ops = {
+		.terminal_update_cb = terminal_update_cb,
+		.get_recv_buf = get_recv_buf_cb,
+		.data_recv_cb = data_recv_cb,
+		.sof_cb = uac2_sof_cb,
+	};
+	struct usbd_context *sample_usbd;
 
-	if (!device_is_ready(hs_dev)) {
-		printk("Device USB Headset is not ready\n");
-		return 0;
+	if (!device_is_ready(broadcaster_dev)) {
+		printk("Cannot get USB Broadcaster Device\n");
+		return -EIO;
 	}
 
 	printk("Found USB Headset Device\n");
@@ -482,15 +535,23 @@ int main(void)
 		       ring_buf_capacity_get(&(streams[i].audio_ring_buf)));
 	}
 
-	usb_audio_register(hs_dev, &ops);
+	usbd_uac2_set_ops(broadcaster_dev, &usb_audio_ops, NULL);
 
-	err = usb_enable(NULL);
-	if (err && err != -EALREADY) {
-		printk("Failed to enable USB (%d)", err);
-		return 0;
+	sample_usbd = sample_usbd_init_device(NULL);
+	if (sample_usbd == NULL) {
+		printk("Failed to init USBD device: %d\n", err);
+		return -ENODEV;
+	}
+
+	err = usbd_enable(sample_usbd);
+	if (err != 0) {
+		printk("Failed to enable USBD: %d\n", err);
+		return err;
 	}
 
-#endif /* defined(CONFIG_USB_DEVICE_AUDIO) */
+	printk("USB initialized\n");
+
+#endif /* defined(CONFIG_USE_USB_AUDIO_INPUT) */
 	k_thread_start(encoder);
 #endif /* defined(CONFIG_LIBLC3) */
 
@@ -596,10 +657,10 @@ int main(void)
 			}
 		}
 
-#if defined(CONFIG_LIBLC3) && defined(CONFIG_USB_DEVICE_AUDIO)
+#if defined(CONFIG_LIBLC3) && defined(CONFIG_USE_USB_AUDIO_INPUT)
 		/* Never stop streaming when using USB Audio as input */
 		k_sleep(K_FOREVER);
-#endif /* defined(CONFIG_LIBLC3) && defined(CONFIG_USB_DEVICE_AUDIO) */
+#endif /* defined(CONFIG_LIBLC3) && defined(CONFIG_USE_USB_AUDIO_INPUT) */
 		printk("Waiting %u seconds before stopped\n", BROADCAST_SOURCE_LIFETIME);
 		k_sleep(K_SECONDS(BROADCAST_SOURCE_LIFETIME));
 		printk("Stopping broadcast source\n");
diff --git a/samples/bluetooth/bap_unicast_client/boards/native_sim.conf b/samples/bluetooth/bap_unicast_client/boards/native_sim.conf
index 8ab1d7be113..87e355c8675 100644
--- a/samples/bluetooth/bap_unicast_client/boards/native_sim.conf
+++ b/samples/bluetooth/bap_unicast_client/boards/native_sim.conf
@@ -6,4 +6,4 @@ CONFIG_FPU=y
 # For LE-audio at 10ms intervals we need the tick counter to occur more frequently
 # than every 10 ms as each PDU for some reason takes 2 ticks to process.
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
-CONFIG_NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME=y
+CONFIG_NATIVE_SIM_SLOWDOWN_TO_REAL_TIME=y
diff --git a/samples/bluetooth/bap_unicast_client/boards/nrf54l15bsim_nrf54l15_cpuapp.conf b/samples/bluetooth/bap_unicast_client/boards/nrf54l15bsim_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..8bfd5bc41f9
--- /dev/null
+++ b/samples/bluetooth/bap_unicast_client/boards/nrf54l15bsim_nrf54l15_cpuapp.conf
@@ -0,0 +1,3 @@
+# For LC3 the following configs are needed
+CONFIG_FPU=y
+CONFIG_LIBLC3=y
diff --git a/samples/bluetooth/bap_unicast_client/overlay-bt_ll_sw_split.conf b/samples/bluetooth/bap_unicast_client/overlay-bt_ll_sw_split.conf
index 755e7fafa78..722b8c25ef1 100644
--- a/samples/bluetooth/bap_unicast_client/overlay-bt_ll_sw_split.conf
+++ b/samples/bluetooth/bap_unicast_client/overlay-bt_ll_sw_split.conf
@@ -8,6 +8,7 @@ CONFIG_BT_CTLR_ISOAL_SINKS=1
 # packet overhead (the Packet_Sequence_Number, ISO_SDU_Length, Packet_Status_Flag fields; and
 # the optional Time_Stamp field, if supplied)
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=163
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=155
 
 CONFIG_BT_CTLR_ADVANCED_FEATURES=y
 CONFIG_BT_CTLR_CONN_ISO_LOW_LATENCY_POLICY=y
diff --git a/samples/bluetooth/bap_unicast_server/boards/native_sim.conf b/samples/bluetooth/bap_unicast_server/boards/native_sim.conf
index 8ab1d7be113..87e355c8675 100644
--- a/samples/bluetooth/bap_unicast_server/boards/native_sim.conf
+++ b/samples/bluetooth/bap_unicast_server/boards/native_sim.conf
@@ -6,4 +6,4 @@ CONFIG_FPU=y
 # For LE-audio at 10ms intervals we need the tick counter to occur more frequently
 # than every 10 ms as each PDU for some reason takes 2 ticks to process.
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
-CONFIG_NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME=y
+CONFIG_NATIVE_SIM_SLOWDOWN_TO_REAL_TIME=y
diff --git a/samples/bluetooth/bap_unicast_server/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf b/samples/bluetooth/bap_unicast_server/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf
index 9b059b92ddc..a8d2d0a04d6 100644
--- a/samples/bluetooth/bap_unicast_server/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf
+++ b/samples/bluetooth/bap_unicast_server/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf
@@ -1,6 +1,9 @@
 # For LC3 the following configs are needed
 CONFIG_FPU=y
 CONFIG_LIBLC3=y
+# The LC3 codec uses a large amount of stack. This app runs the codec in the BT RX thread, hence
+# increase stack size for that thread.
+CONFIG_BT_RX_STACK_SIZE=4096
 
 CONFIG_BT_BUF_EVT_RX_SIZE=255
 CONFIG_BT_BUF_ACL_RX_SIZE=255
diff --git a/samples/bluetooth/bap_unicast_server/boards/nrf5340dk_nrf5340_cpuapp.conf b/samples/bluetooth/bap_unicast_server/boards/nrf5340dk_nrf5340_cpuapp.conf
index 31b3a09380f..a8d2d0a04d6 100644
--- a/samples/bluetooth/bap_unicast_server/boards/nrf5340dk_nrf5340_cpuapp.conf
+++ b/samples/bluetooth/bap_unicast_server/boards/nrf5340dk_nrf5340_cpuapp.conf
@@ -1,9 +1,9 @@
 # For LC3 the following configs are needed
 CONFIG_FPU=y
 CONFIG_LIBLC3=y
-# The LC3 codec uses a large amount of stack. This app runs the codec in the work-queue, hence
-# inctease stack size for that thread.
-CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=4096
+# The LC3 codec uses a large amount of stack. This app runs the codec in the BT RX thread, hence
+# increase stack size for that thread.
+CONFIG_BT_RX_STACK_SIZE=4096
 
 CONFIG_BT_BUF_EVT_RX_SIZE=255
 CONFIG_BT_BUF_ACL_RX_SIZE=255
diff --git a/samples/bluetooth/bap_unicast_server/boards/nrf54l15bsim_nrf54l15_cpuapp.conf b/samples/bluetooth/bap_unicast_server/boards/nrf54l15bsim_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..8bfd5bc41f9
--- /dev/null
+++ b/samples/bluetooth/bap_unicast_server/boards/nrf54l15bsim_nrf54l15_cpuapp.conf
@@ -0,0 +1,3 @@
+# For LC3 the following configs are needed
+CONFIG_FPU=y
+CONFIG_LIBLC3=y
diff --git a/samples/bluetooth/bap_unicast_server/overlay-bt_ll_sw_split.conf b/samples/bluetooth/bap_unicast_server/overlay-bt_ll_sw_split.conf
index 8c6d99253a6..fd04f621bfd 100644
--- a/samples/bluetooth/bap_unicast_server/overlay-bt_ll_sw_split.conf
+++ b/samples/bluetooth/bap_unicast_server/overlay-bt_ll_sw_split.conf
@@ -8,6 +8,7 @@ CONFIG_BT_CTLR_ISOAL_SINKS=2
 # packet overhead (the Packet_Sequence_Number, ISO_SDU_Length, Packet_Status_Flag fields; and
 # the optional Time_Stamp field, if supplied)
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=163
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=155
 
 # Use the below if the sample is sending stale packet sequence number
 # CONFIG_BT_CTLR_ADVANCED_FEATURES=y
diff --git a/samples/bluetooth/bap_unicast_server/src/main.c b/samples/bluetooth/bap_unicast_server/src/main.c
index c3e310b35d8..cdf3bb01fe6 100644
--- a/samples/bluetooth/bap_unicast_server/src/main.c
+++ b/samples/bluetooth/bap_unicast_server/src/main.c
@@ -509,7 +509,7 @@ static void stream_recv_lc3_codec(struct bt_bap_stream *stream,
 				  const struct bt_iso_recv_info *info,
 				  struct net_buf *buf)
 {
-	const bool valid_data = (info->flags & BT_ISO_FLAGS_VALID) == 0;
+	const bool valid_data = (info->flags & BT_ISO_FLAGS_VALID) != 0;
 	const int octets_per_frame = buf->len / frames_per_sdu;
 
 	if (lc3_decoder == NULL) {
@@ -721,9 +721,16 @@ static int set_available_contexts(void)
 	return 0;
 }
 
+
 int main(void)
 {
 	struct bt_le_ext_adv *adv;
+	const struct bt_pacs_register_param pacs_param = {
+		.snk_pac = true,
+		.snk_loc = true,
+		.src_pac = true,
+		.src_loc = true,
+	};
 	int err;
 
 	err = bt_enable(NULL);
@@ -734,6 +741,12 @@ int main(void)
 
 	printk("Bluetooth initialized\n");
 
+	err = bt_pacs_register(&pacs_param);
+	if (err) {
+		printk("Could not register PACS (err %d)\n", err);
+		return 0;
+	}
+
 	bt_bap_unicast_server_register(&param);
 	bt_bap_unicast_server_register_cb(&unicast_server_cb);
 
diff --git a/samples/bluetooth/beacon/sample.yaml b/samples/bluetooth/beacon/sample.yaml
index 6ab2413ca8f..819ac3d3002 100644
--- a/samples/bluetooth/beacon/sample.yaml
+++ b/samples/bluetooth/beacon/sample.yaml
@@ -9,12 +9,14 @@ tests:
       - nrf51dk/nrf51822
       - nrf52dk/nrf52832
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     tags: bluetooth
     integration_platforms:
       - qemu_cortex_m3
       - nrf51dk/nrf51822
       - nrf52dk/nrf52832
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
   sample.bluetooth.beacon-coex:
     extra_args:
       - CONF_FILE="prj-coex.conf"
diff --git a/samples/bluetooth/cap_acceptor/overlay-bt_ll_sw_split.conf b/samples/bluetooth/cap_acceptor/overlay-bt_ll_sw_split.conf
index fa88804bece..940133b21e5 100644
--- a/samples/bluetooth/cap_acceptor/overlay-bt_ll_sw_split.conf
+++ b/samples/bluetooth/cap_acceptor/overlay-bt_ll_sw_split.conf
@@ -9,3 +9,4 @@ CONFIG_BT_CTLR_ADV_DATA_LEN_MAX=191
 # packet overhead (the Packet_Sequence_Number, ISO_SDU_Length, Packet_Status_Flag fields; and
 # the optional Time_Stamp field, if supplied)
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=163
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=155
diff --git a/samples/bluetooth/cap_acceptor/src/cap_acceptor_broadcast.c b/samples/bluetooth/cap_acceptor/src/cap_acceptor_broadcast.c
index 444c5f06e3c..190bef26eab 100644
--- a/samples/bluetooth/cap_acceptor/src/cap_acceptor_broadcast.c
+++ b/samples/bluetooth/cap_acceptor/src/cap_acceptor_broadcast.c
@@ -13,6 +13,7 @@
 #include <strings.h>
 
 #include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/audio/audio.h>
 #include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/audio/cap.h>
@@ -20,9 +21,11 @@
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gap.h>
 #include <zephyr/bluetooth/iso.h>
+#include <zephyr/bluetooth/uuid.h>
 #include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/logging/log_core.h>
+#include <zephyr/net_buf.h>
 #include <zephyr/sys/atomic.h>
 #include <zephyr/sys/byteorder.h>
 #include <zephyr/sys/util.h>
@@ -605,8 +608,8 @@ static bool scan_check_and_sync_broadcast(struct bt_data *data, void *user_data)
 
 	bt_addr_le_to_str(info->addr, le_addr, sizeof(le_addr));
 
-	printk("Found broadcaster with ID 0x%06X and addr %s and sid 0x%02X\n", broadcast_id,
-	       le_addr, info->sid);
+	LOG_INF("Found broadcaster with ID 0x%06X and addr %s and sid 0x%02X\n", broadcast_id,
+		le_addr, info->sid);
 
 	bt_addr_le_copy(&param.addr, info->addr);
 	param.options = BT_LE_PER_ADV_SYNC_OPT_FILTER_DUPLICATE;
diff --git a/samples/bluetooth/cap_acceptor/src/cap_acceptor_unicast.c b/samples/bluetooth/cap_acceptor/src/cap_acceptor_unicast.c
index 132ee499c87..55a9f91099e 100644
--- a/samples/bluetooth/cap_acceptor/src/cap_acceptor_unicast.c
+++ b/samples/bluetooth/cap_acceptor/src/cap_acceptor_unicast.c
@@ -456,5 +456,8 @@ int init_cap_acceptor_unicast(struct peer_config *peer)
 		}
 	}
 
+	k_sem_init(&peer->source_stream_sem, 0, 1);
+	k_sem_init(&peer->sink_stream_sem, 0, 1);
+
 	return 0;
 }
diff --git a/samples/bluetooth/cap_acceptor/src/main.c b/samples/bluetooth/cap_acceptor/src/main.c
index c7652551c01..702bd074b32 100644
--- a/samples/bluetooth/cap_acceptor/src/main.c
+++ b/samples/bluetooth/cap_acceptor/src/main.c
@@ -257,6 +257,12 @@ static int init_cap_acceptor(void)
 	static const struct bt_audio_codec_cap lc3_codec_cap = BT_AUDIO_CODEC_CAP_LC3(
 		SUPPORTED_FREQ, SUPPORTED_DURATION, MAX_CHAN_PER_STREAM, MIN_SDU, MAX_SDU,
 		FRAMES_PER_SDU, (SINK_CONTEXT | SOURCE_CONTEXT));
+	const struct bt_pacs_register_param pacs_param = {
+		.snk_pac = true,
+		.snk_loc = true,
+		.src_pac = true,
+		.src_loc = true,
+	};
 	int err;
 
 	err = bt_enable(NULL);
@@ -268,6 +274,12 @@ static int init_cap_acceptor(void)
 
 	LOG_INF("Bluetooth initialized");
 
+	err = bt_pacs_register(&pacs_param);
+	if (err) {
+		LOG_ERR("Could not register PACS (err %d)", err);
+		return 0;
+	}
+
 	if (IS_ENABLED(CONFIG_BT_PAC_SNK)) {
 		static struct bt_pacs_cap sink_cap = {
 			.codec_cap = &lc3_codec_cap,
diff --git a/samples/bluetooth/cap_initiator/overlay-bt_ll_sw_split.conf b/samples/bluetooth/cap_initiator/overlay-bt_ll_sw_split.conf
index fa88804bece..940133b21e5 100644
--- a/samples/bluetooth/cap_initiator/overlay-bt_ll_sw_split.conf
+++ b/samples/bluetooth/cap_initiator/overlay-bt_ll_sw_split.conf
@@ -9,3 +9,4 @@ CONFIG_BT_CTLR_ADV_DATA_LEN_MAX=191
 # packet overhead (the Packet_Sequence_Number, ISO_SDU_Length, Packet_Status_Flag fields; and
 # the optional Time_Stamp field, if supplied)
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=163
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=155
diff --git a/samples/bluetooth/cap_initiator/src/cap_initiator_broadcast.c b/samples/bluetooth/cap_initiator/src/cap_initiator_broadcast.c
index f6c9d81f9dc..55898056e75 100644
--- a/samples/bluetooth/cap_initiator/src/cap_initiator_broadcast.c
+++ b/samples/bluetooth/cap_initiator/src/cap_initiator_broadcast.c
@@ -12,6 +12,7 @@
 #include <zephyr/bluetooth/audio/cap.h>
 #include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/crypto.h>
 #include <zephyr/bluetooth/gap.h>
 #include <zephyr/bluetooth/uuid.h>
 #include <zephyr/kernel.h>
@@ -136,7 +137,7 @@ static int setup_extended_adv_data(struct bt_cap_broadcast_source *source,
 #else
 	err = bt_rand(&broadcast_id, BT_AUDIO_BROADCAST_ID_SIZE);
 	if (err) {
-		printk("Unable to generate broadcast ID: %d\n", err);
+		LOG_ERR("Unable to generate broadcast ID: %d\n", err);
 		return err;
 	}
 #endif /* CONFIG_STATIC_BROADCAST_ID */
diff --git a/samples/bluetooth/ccp_call_control_client/CMakeLists.txt b/samples/bluetooth/ccp_call_control_client/CMakeLists.txt
new file mode 100644
index 00000000000..101c16bf0d6
--- /dev/null
+++ b/samples/bluetooth/ccp_call_control_client/CMakeLists.txt
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(ccp_call_control_client)
+
+target_sources(app PRIVATE
+  src/main.c
+)
+
+zephyr_library_include_directories(${ZEPHYR_BASE}/samples/bluetooth)
diff --git a/samples/bluetooth/ccp_call_control_client/Kconfig.sysbuild b/samples/bluetooth/ccp_call_control_client/Kconfig.sysbuild
new file mode 100644
index 00000000000..f37b265ecbc
--- /dev/null
+++ b/samples/bluetooth/ccp_call_control_client/Kconfig.sysbuild
@@ -0,0 +1,15 @@
+# Copyright 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+source "share/sysbuild/Kconfig"
+
+config NET_CORE_BOARD
+	string
+	default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk"
+	default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk"
+	default "nrf5340bsim/nrf5340/cpunet" if $(BOARD_TARGET_STRING) = "NRF5340BSIM_NRF5340_CPUAPP"
+
+config NET_CORE_IMAGE_HCI_IPC
+	bool "HCI IPC image on network core"
+	default y
+	depends on NET_CORE_BOARD != ""
diff --git a/samples/bluetooth/ccp_call_control_client/README.rst b/samples/bluetooth/ccp_call_control_client/README.rst
new file mode 100644
index 00000000000..ae27a843a6d
--- /dev/null
+++ b/samples/bluetooth/ccp_call_control_client/README.rst
@@ -0,0 +1,78 @@
+.. zephyr:code-sample:: bluetooth_ccp_call_control_client
+   :name: Call Control Profile (CCP) Call Control Server
+   :relevant-api: bluetooth bt_ccp bt_tbs
+
+   CCP Call Control Server sample that registers one or more TBS bearers and advertises the
+   TBS UUID(s).
+
+Overview
+********
+
+Application demonstrating the CCP Call Control Client functionality.
+Starts by scanning for a CCP Call Control Server to connect and set up calls.
+
+The profile works for both GAP Central and GAP Peripheral devices, but this sample only assumes the
+GAP Central role.
+
+This sample can be found under :zephyr_file:`samples/bluetooth/ccp_call_control_client`
+in the Zephyr tree.
+
+Check the :zephyr:code-sample-category:`bluetooth` samples for general information.
+
+Requirements
+************
+
+* BlueZ running on the host, or
+* A board with Bluetooth Low Energy 5.2 support
+
+Building and Running
+********************
+
+When building targeting an nrf52 series board with the Zephyr Bluetooth Controller,
+use ``-DEXTRA_CONF_FILE=overlay-bt_ll_sw_split.conf`` to enable the required feature support.
+
+Building for an nrf5340dk
+-------------------------
+
+You can build both the application core image and an appropriate controller image for the network
+core with:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/bluetooth/ccp_call_control_client/
+   :board: nrf5340dk/nrf5340/cpuapp
+   :goals: build
+   :west-args: --sysbuild
+
+If you prefer to only build the application core image, you can do so by doing instead:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/bluetooth/ccp_call_control_client/
+   :board: nrf5340dk/nrf5340/cpuapp
+   :goals: build
+
+In that case you can pair this application core image with the
+:zephyr:code-sample:`bluetooth_hci_ipc` sample
+:zephyr_file:`samples/bluetooth/hci_ipc/nrf5340_cpunet_iso-bt_ll_sw_split.conf` configuration.
+
+Building for a simulated nrf5340bsim
+------------------------------------
+
+Similarly to how you would for real HW, you can do:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/bluetooth/ccp_call_control_client/
+   :board: nrf5340bsim/nrf5340/cpuapp
+   :goals: build
+   :west-args: --sysbuild
+
+Note this will produce a Linux executable in :file:`./build/zephyr/zephyr.exe`.
+For more information, check :ref:`this board documentation <nrf5340bsim>`.
+
+Building for a simulated nrf52_bsim
+-----------------------------------
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/bluetooth/ccp_call_control_client/
+   :board: nrf52_bsim
+   :goals: build
+   :gen-args: -DEXTRA_CONF_FILE=overlay-bt_ll_sw_split.conf
diff --git a/samples/bluetooth/ccp_call_control_client/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf b/samples/bluetooth/ccp_call_control_client/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf
new file mode 100644
index 00000000000..09fa41842eb
--- /dev/null
+++ b/samples/bluetooth/ccp_call_control_client/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf
@@ -0,0 +1,4 @@
+CONFIG_BT_BUF_EVT_RX_SIZE=255
+CONFIG_BT_BUF_ACL_RX_SIZE=255
+CONFIG_BT_BUF_ACL_TX_SIZE=251
+CONFIG_BT_BUF_CMD_TX_SIZE=255
diff --git a/samples/bluetooth/ccp_call_control_client/boards/nrf5340dk_nrf5340_cpuapp.conf b/samples/bluetooth/ccp_call_control_client/boards/nrf5340dk_nrf5340_cpuapp.conf
new file mode 100644
index 00000000000..09fa41842eb
--- /dev/null
+++ b/samples/bluetooth/ccp_call_control_client/boards/nrf5340dk_nrf5340_cpuapp.conf
@@ -0,0 +1,4 @@
+CONFIG_BT_BUF_EVT_RX_SIZE=255
+CONFIG_BT_BUF_ACL_RX_SIZE=255
+CONFIG_BT_BUF_ACL_TX_SIZE=251
+CONFIG_BT_BUF_CMD_TX_SIZE=255
diff --git a/samples/bluetooth/ccp_call_control_client/overlay-bt_ll_sw_split.conf b/samples/bluetooth/ccp_call_control_client/overlay-bt_ll_sw_split.conf
new file mode 100644
index 00000000000..dce0f2c298e
--- /dev/null
+++ b/samples/bluetooth/ccp_call_control_client/overlay-bt_ll_sw_split.conf
@@ -0,0 +1,6 @@
+# Zephyr Bluetooth Controller
+CONFIG_BT_LL_SW_SPLIT=y
+
+# Zephyr Controller tested maximum advertising data that can be set in a single HCI command
+CONFIG_BT_CTLR_ADV_DATA_LEN_MAX=191
+CONFIG_BT_CTLR_SCAN_DATA_LEN_MAX=191
diff --git a/samples/bluetooth/ccp_call_control_client/prj.conf b/samples/bluetooth/ccp_call_control_client/prj.conf
new file mode 100644
index 00000000000..85549f2c321
--- /dev/null
+++ b/samples/bluetooth/ccp_call_control_client/prj.conf
@@ -0,0 +1,22 @@
+CONFIG_BT=y
+CONFIG_LOG=y
+CONFIG_BT_CENTRAL=y
+CONFIG_BT_GATT_CLIENT=y
+CONFIG_BT_GATT_AUTO_DISCOVER_CCC=y
+CONFIG_BT_AUDIO=y
+CONFIG_BT_EXT_ADV=y
+CONFIG_BT_DEVICE_NAME="CCP Call Control Client"
+
+CONFIG_BT_SMP=y
+CONFIG_BT_KEYS_OVERWRITE_OLDEST=y
+
+# CCP support
+CONFIG_BT_CCP_CALL_CONTROL_CLIENT=y
+CONFIG_BT_CCP_CALL_CONTROL_CLIENT_BEARER_COUNT=2
+CONFIG_BT_TBS_CLIENT_GTBS=y
+CONFIG_BT_TBS_CLIENT_TBS=y
+CONFIG_BT_TBS_CLIENT_MAX_TBS_INSTANCES=1
+CONFIG_UTF8=y
+
+# TBS Client may require up to 12 buffers
+CONFIG_BT_ATT_TX_COUNT=12
diff --git a/samples/bluetooth/ccp_call_control_client/sample.yaml b/samples/bluetooth/ccp_call_control_client/sample.yaml
new file mode 100644
index 00000000000..c4e565d1bb6
--- /dev/null
+++ b/samples/bluetooth/ccp_call_control_client/sample.yaml
@@ -0,0 +1,30 @@
+sample:
+  description: Bluetooth Low Energy Call Control Profile Server sample
+  name: Bluetooth Low Energy Call Control Profile Server sample
+tests:
+  sample.bluetooth.ccp_call_control_client:
+    harness: bluetooth
+    platform_allow:
+      - qemu_cortex_m3
+      - qemu_x86
+      - nrf5340dk/nrf5340/cpuapp
+      - nrf5340bsim/nrf5340/cpuapp
+    integration_platforms:
+      - qemu_x86
+      - nrf5340dk/nrf5340/cpuapp
+    tags: bluetooth
+    sysbuild: true
+  sample.bluetooth.ccp_call_control_client.bt_ll_sw_split:
+    harness: bluetooth
+    platform_allow:
+      - nrf52_bsim
+      - nrf52833dk/nrf52833
+      - nrf52840dk/nrf52840
+      - nrf52840dongle/nrf52840
+    integration_platforms:
+      - nrf52_bsim
+      - nrf52833dk/nrf52833
+      - nrf52840dk/nrf52840
+      - nrf52840dongle/nrf52840
+    extra_args: EXTRA_CONF_FILE=overlay-bt_ll_sw_split.conf
+    tags: bluetooth
diff --git a/samples/bluetooth/ccp_call_control_client/src/main.c b/samples/bluetooth/ccp_call_control_client/src/main.c
new file mode 100644
index 00000000000..db8341204a4
--- /dev/null
+++ b/samples/bluetooth/ccp_call_control_client/src/main.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/audio/tbs.h>
+#include <zephyr/bluetooth/audio/ccp.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/bluetooth/uuid.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+
+LOG_MODULE_REGISTER(ccp_call_control_client, CONFIG_LOG_DEFAULT_LEVEL);
+
+#define SEM_TIMEOUT K_SECONDS(10)
+
+static struct bt_conn *peer_conn;
+/* client is not static as it is used for testing purposes */
+struct bt_ccp_call_control_client *client;
+static struct bt_ccp_call_control_client_bearers client_bearers;
+
+static K_SEM_DEFINE(sem_conn_state_change, 0, 1);
+static K_SEM_DEFINE(sem_security_updated, 0, 1);
+static K_SEM_DEFINE(sem_ccp_action_completed, 0, 1);
+
+static void connected_cb(struct bt_conn *conn, uint8_t err)
+{
+	char addr[BT_ADDR_LE_STR_LEN];
+
+	(void)bt_addr_le_to_str(bt_conn_get_dst(conn), addr, sizeof(addr));
+	LOG_INF("Connected: %s", addr);
+
+	k_sem_give(&sem_conn_state_change);
+}
+
+static void disconnected_cb(struct bt_conn *conn, uint8_t reason)
+{
+	char addr[BT_ADDR_LE_STR_LEN];
+
+	if (conn != peer_conn) {
+		return;
+	}
+
+	(void)bt_addr_le_to_str(bt_conn_get_dst(conn), addr, sizeof(addr));
+	LOG_INF("Disconnected: %s (reason 0x%02x)", addr, reason);
+
+	bt_conn_unref(peer_conn);
+	peer_conn = NULL;
+	client = NULL;
+	memset(&client_bearers, 0, sizeof(client_bearers));
+	k_sem_give(&sem_conn_state_change);
+}
+
+static void security_changed_cb(struct bt_conn *conn, bt_security_t level, enum bt_security_err err)
+{
+	if (err == 0) {
+		k_sem_give(&sem_security_updated);
+	} else {
+		LOG_ERR("Failed to set security level: %s(%u)", bt_security_err_to_str(err), err);
+	}
+}
+
+BT_CONN_CB_DEFINE(conn_callbacks) = {
+	.connected = connected_cb,
+	.disconnected = disconnected_cb,
+	.security_changed = security_changed_cb,
+};
+
+static bool check_gtbs_support(struct bt_data *data, void *user_data)
+{
+	struct net_buf_simple svc_data;
+	bool *connect = user_data;
+	const struct bt_uuid *uuid;
+	uint16_t uuid_val;
+
+	if (data->type != BT_DATA_SVC_DATA16) {
+		return true; /* Continue parsing to next AD data type */
+	}
+
+	if (data->data_len < sizeof(uuid_val)) {
+		LOG_WRN("AD invalid size %u", data->data_len);
+		return true; /* Continue parsing to next AD data type */
+	}
+
+	net_buf_simple_init_with_data(&svc_data, (void *)data->data, data->data_len);
+
+	/* Pull the 16-bit service data and compare to what we are searching for */
+	uuid_val = net_buf_simple_pull_le16(&svc_data);
+	uuid = BT_UUID_DECLARE_16(sys_le16_to_cpu(uuid_val));
+	if (bt_uuid_cmp(uuid, BT_UUID_GTBS) != 0) {
+		/* We are looking for the GTBS service data */
+		return true; /* Continue parsing to next AD data type */
+	}
+
+	*connect = true;
+
+	return false; /* Stop parsing */
+}
+
+static void scan_recv_cb(const struct bt_le_scan_recv_info *info, struct net_buf_simple *ad)
+{
+	char addr_str[BT_ADDR_LE_STR_LEN];
+	bool connect = false;
+
+	if (peer_conn != NULL) {
+		/* Already connected */
+		return;
+	}
+
+	/* CCP mandates that connectbale extended advertising is used by the peripherals so we
+	 * ignore any scan report this is not that.
+	 * We also ignore reports with poor RSSI
+	 */
+	if (info->adv_type != BT_GAP_ADV_TYPE_EXT_ADV ||
+	    (info->adv_props & BT_GAP_ADV_PROP_EXT_ADV) == 0 ||
+	    (info->adv_props & BT_GAP_ADV_PROP_CONNECTABLE) == 0 || info->rssi < -70) {
+		return;
+	}
+
+	(void)bt_addr_le_to_str(info->addr, addr_str, sizeof(addr_str));
+	LOG_INF("Connectable device found: %s (RSSI %d)", addr_str, info->rssi);
+
+	/* Iterate on the advertising data to see if claims GTBS support */
+	bt_data_parse(ad, check_gtbs_support, &connect);
+
+	if (connect) {
+		int err;
+
+		err = bt_le_scan_stop();
+		if (err != 0) {
+			LOG_ERR("Scanning failed to stop (err %d)", err);
+			return;
+		}
+
+		LOG_INF("Connecting to found CCP server");
+		err = bt_conn_le_create(info->addr, BT_CONN_LE_CREATE_CONN,
+					BT_LE_CONN_PARAM_DEFAULT, &peer_conn);
+		if (err != 0) {
+			LOG_ERR("Conn create failed: %d", err);
+		}
+	}
+}
+
+static int scan_and_connect(void)
+{
+	int err;
+
+	err = bt_le_scan_start(BT_LE_SCAN_PASSIVE, NULL);
+	if (err != 0) {
+		LOG_ERR("Scanning failed to start (err %d)", err);
+		return err;
+	}
+
+	LOG_INF("Scanning successfully started");
+
+	err = k_sem_take(&sem_conn_state_change, K_FOREVER);
+	if (err != 0) {
+		LOG_ERR("failed to take sem_connected (err %d)", err);
+		return err;
+	}
+
+	err = bt_conn_set_security(peer_conn, BT_SECURITY_L2);
+	if (err != 0) {
+		LOG_ERR("failed to set security (err %d)", err);
+		return err;
+	}
+
+	err = k_sem_take(&sem_security_updated, SEM_TIMEOUT);
+	if (err != 0) {
+		LOG_ERR("failed to take sem_security_updated (err %d)", err);
+		return err;
+	}
+
+	LOG_INF("Security successfully updated");
+
+	return 0;
+}
+
+static void ccp_call_control_client_discover_cb(struct bt_ccp_call_control_client *client, int err,
+						struct bt_ccp_call_control_client_bearers *bearers)
+{
+	if (err != 0) {
+		LOG_ERR("Discovery failed: %d", err);
+		return;
+	}
+
+	LOG_INF("Discovery completed with %s%u TBS bearers",
+		bearers->gtbs_bearer != NULL ? "GTBS and " : "", bearers->tbs_count);
+
+	memcpy(&client_bearers, bearers, sizeof(client_bearers));
+
+	k_sem_give(&sem_ccp_action_completed);
+}
+
+static int reset_ccp_call_control_client(void)
+{
+	int err;
+
+	LOG_INF("Resetting");
+
+	if (peer_conn != NULL) {
+		err = bt_conn_disconnect(peer_conn, BT_HCI_ERR_REMOTE_USER_TERM_CONN);
+		if (err != 0) {
+			return err;
+		}
+
+		err = k_sem_take(&sem_conn_state_change, K_FOREVER);
+		if (err != 0) {
+			LOG_ERR("Failed to take sem_conn_state_change: %d", err);
+			return err;
+		}
+	}
+
+	/* If scanning is already stopped it will still return `0` */
+	err = bt_le_scan_stop();
+	if (err != 0) {
+		LOG_ERR("Scanning failed to stop (err %d)", err);
+		return err;
+	}
+
+	k_sem_reset(&sem_conn_state_change);
+
+	return 0;
+}
+
+static int discover_services(void)
+{
+	int err;
+
+	LOG_INF("Discovering GTBS and TBS");
+
+	err = bt_ccp_call_control_client_discover(peer_conn, &client);
+	if (err != 0) {
+		LOG_ERR("Failed to discover: %d", err);
+		return err;
+	}
+
+	err = k_sem_take(&sem_ccp_action_completed, SEM_TIMEOUT);
+	if (err != 0) {
+		LOG_ERR("Failed to take sem_ccp_action_completed: %d", err);
+		return err;
+	}
+
+	return 0;
+}
+
+static int init_ccp_call_control_client(void)
+{
+	static struct bt_le_scan_cb scan_cbs = {
+		.recv = scan_recv_cb,
+	};
+	static struct bt_ccp_call_control_client_cb ccp_call_control_client_cbs = {
+		.discover = ccp_call_control_client_discover_cb,
+	};
+	int err;
+
+	err = bt_enable(NULL);
+	if (err != 0) {
+		LOG_ERR("Bluetooth enable failed (err %d)", err);
+
+		return err;
+	}
+
+	LOG_DBG("Bluetooth initialized");
+	err = bt_le_scan_cb_register(&scan_cbs);
+	if (err != 0) {
+		LOG_ERR("Bluetooth enable failed (err %d)", err);
+
+		return err;
+	}
+
+	err = bt_ccp_call_control_client_register_cb(&ccp_call_control_client_cbs);
+	if (err != 0) {
+		LOG_ERR("Bluetooth enable failed (err %d)", err);
+
+		return err;
+	}
+
+	return 0;
+}
+
+int main(void)
+{
+	int err;
+
+	err = init_ccp_call_control_client();
+	if (err != 0) {
+		return 0;
+	}
+
+	LOG_INF("CCP Call Control Client initialized");
+
+	while (true) {
+		err = reset_ccp_call_control_client();
+		if (err != 0) {
+			break;
+		}
+
+		/* Start scanning for CCP servers and connect to the first we find */
+		err = scan_and_connect();
+		if (err != 0) {
+			continue;
+		}
+
+		/* Discover TBS and GTBS on the remove server */
+		err = discover_services();
+		if (err != 0) {
+			continue;
+		}
+
+		/* Reset if disconnected */
+		err = k_sem_take(&sem_conn_state_change, K_FOREVER);
+		if (err != 0) {
+			LOG_ERR("Failed to take sem_conn_state_change: err %d", err);
+			break;
+		}
+	}
+
+	return 0;
+}
diff --git a/samples/bluetooth/ccp_call_control_client/sysbuild.cmake b/samples/bluetooth/ccp_call_control_client/sysbuild.cmake
new file mode 100644
index 00000000000..2523aac8ea7
--- /dev/null
+++ b/samples/bluetooth/ccp_call_control_client/sysbuild.cmake
@@ -0,0 +1,24 @@
+# Copyright (c) 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if(SB_CONFIG_NET_CORE_IMAGE_HCI_IPC)
+	# For builds in the nrf5340, we build the netcore image with the controller
+
+	set(NET_APP hci_ipc)
+	set(NET_APP_SRC_DIR ${ZEPHYR_BASE}/samples/bluetooth/${NET_APP})
+
+	ExternalZephyrProject_Add(
+		APPLICATION ${NET_APP}
+		SOURCE_DIR  ${NET_APP_SRC_DIR}
+		BOARD       ${SB_CONFIG_NET_CORE_BOARD}
+	)
+
+	set(${NET_APP}_CONF_FILE
+	 ${NET_APP_SRC_DIR}/nrf5340_cpunet_iso-bt_ll_sw_split.conf
+	 CACHE INTERNAL ""
+	)
+
+	native_simulator_set_child_images(${DEFAULT_IMAGE} ${NET_APP})
+endif()
+
+native_simulator_set_final_executable(${DEFAULT_IMAGE})
diff --git a/samples/bluetooth/ccp_call_control_server/README.rst b/samples/bluetooth/ccp_call_control_server/README.rst
index eab3bbbdc0a..da8594e0349 100644
--- a/samples/bluetooth/ccp_call_control_server/README.rst
+++ b/samples/bluetooth/ccp_call_control_server/README.rst
@@ -28,7 +28,7 @@ Building and Running
 ********************
 
 When building targeting an nrf52 series board with the Zephyr Bluetooth Controller,
-use ``-DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf`` to enable the required feature support.
+use ``-DEXTRA_CONF_FILE=overlay-bt_ll_sw_split.conf`` to enable the required feature support.
 
 Building for an nrf5340dk
 -------------------------
@@ -74,4 +74,4 @@ Building for a simulated nrf52_bsim
    :zephyr-app: samples/bluetooth/ccp_call_control_server/
    :board: nrf52_bsim
    :goals: build
-   :gen-args: -DOVERLAY_CONFIG=overlay-bt_ll_sw_split.conf
+   :gen-args: -DEXTRA_CONF_FILE=overlay-bt_ll_sw_split.conf
diff --git a/samples/bluetooth/ccp_call_control_server/sample.yaml b/samples/bluetooth/ccp_call_control_server/sample.yaml
index 501c5b37421..1e93a6938e5 100644
--- a/samples/bluetooth/ccp_call_control_server/sample.yaml
+++ b/samples/bluetooth/ccp_call_control_server/sample.yaml
@@ -26,5 +26,5 @@ tests:
       - nrf52833dk/nrf52833
       - nrf52840dk/nrf52840
       - nrf52840dongle/nrf52840
-    extra_args: OVERLAY_CONFIG=overlay-bt_ll_sw_split.conf
+    extra_args: EXTRA_CONF_FILE=overlay-bt_ll_sw_split.conf
     tags: bluetooth
diff --git a/samples/bluetooth/central/README.rst b/samples/bluetooth/central/README.rst
index 0a47dd07b5c..9b67dbd54f5 100644
--- a/samples/bluetooth/central/README.rst
+++ b/samples/bluetooth/central/README.rst
@@ -2,14 +2,41 @@
    :name: Central
    :relevant-api: bluetooth
 
-   Implement basic Bluetooth LE Central role functionality (scanning and connecting).
+   Implement basic Bluetooth LE Central role functionality
+   (scanning and connecting).
 
 Overview
 ********
 
-Application demonstrating very basic Bluetooth LE Central role functionality by scanning
-for other Bluetooth LE devices and establishing a connection to the first one with a
-strong enough signal.
+This application demonstrates basic Bluetooth LE Central role functionality
+by scanning for other Bluetooth LE devices and establishing a connection
+to the first one with a strong enough signal.
+
+Core features
+*************
+
+Scanning for devices
+====================
+
+The application initiates a passive scan to detect nearby Bluetooth LE devices.
+It specifically looks for devices that have a signal strength greater
+than -50dBm. This threshold helps the app filter out weaker signals,
+ensuring it only interacts with devices that are within a reasonable RSSI
+range for communication.
+
+Connection handling
+===================
+
+1. The Central scans for Peripheral devices and if it finds a Peripheral
+   which has a signal strength higher than -50dBm, an attempt to establish
+   LE connection is made.
+2. If the connection is successful, the Central initiates disconnect to
+   the Peripheral and then restarts the scan.
+3. If there are no connections, the Central keeps scanning continuously.
+
+The sample is used to demonstrate the Central mode capabilities of Bluetooth LE and
+hence a disconnect is issued right immediately after establishing a connection with
+a Peripheral, allowing the Central to resume scanning for other devices.
 
 Requirements
 ************
@@ -17,9 +44,18 @@ Requirements
 * BlueZ running on the host, or
 * A board with Bluetooth LE support
 
-Building and Running
+Building and running
 ********************
-This sample can be found under :zephyr_file:`samples/bluetooth/central` in the
-Zephyr tree.
 
-See :zephyr:code-sample-category:`bluetooth` samples for details.
+Build and flash the sample as follows, replacing board_name with your
+target board:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/bluetooth/central
+   :board: board_name
+   :goals: build flash
+   :compact:
+
+To test Central's scanning functionality, either flash the :zephyr:code-sample:`ble_peripheral`
+sample on a second compatible board or use an off-the-shelf Bluetooth LE enabled
+device that can act as a Peripheral (eg. smartphone, smartwatch, etc.).
diff --git a/samples/bluetooth/central/sample.yaml b/samples/bluetooth/central/sample.yaml
index 2001b6409d1..959a67491d4 100644
--- a/samples/bluetooth/central/sample.yaml
+++ b/samples/bluetooth/central/sample.yaml
@@ -19,4 +19,5 @@ tests:
       - sltb010a/efr32bg22c224f512im40
       - xg24_rb4187c/efr32mg24b220f1536im48
       - xg27_dk2602a/efr32bg27c140f768im40
+      - xg29_rb4412a/efr32mg29b140f1024im40
     build_only: true
diff --git a/samples/bluetooth/central_gatt_write/src/gatt_write_common.c b/samples/bluetooth/central_gatt_write/src/gatt_write_common.c
index 7bd597e95dc..99d2e830aea 100644
--- a/samples/bluetooth/central_gatt_write/src/gatt_write_common.c
+++ b/samples/bluetooth/central_gatt_write/src/gatt_write_common.c
@@ -12,10 +12,137 @@
 #include <zephyr/bluetooth/gatt.h>
 #include <zephyr/bluetooth/hci.h>
 
+/* Count down number of metrics intervals before performing a PHY update */
+#define PHY_UPDATE_COUNTDOWN 3U
+static uint32_t phy_update_countdown;
+static uint8_t phy_param_idx;
+
+static void phy_update_iterate(struct bt_conn *conn)
+{
+	const struct bt_conn_le_phy_param phy_param[] = {
+		/* List of 1M Tx with Rx on other PHYs */
+		{
+			.options = BT_CONN_LE_PHY_OPT_NONE,
+			.pref_tx_phy = BT_GAP_LE_PHY_1M,
+			.pref_rx_phy = BT_GAP_LE_PHY_1M,
+		}, {
+			.options = BT_CONN_LE_PHY_OPT_NONE,
+			.pref_tx_phy = BT_GAP_LE_PHY_1M,
+			.pref_rx_phy = BT_GAP_LE_PHY_2M,
+		}, {
+			.options = BT_CONN_LE_PHY_OPT_NONE,
+			.pref_tx_phy = BT_GAP_LE_PHY_1M,
+			.pref_rx_phy = BT_GAP_LE_PHY_CODED,
+		},
+
+		/* List of 2M Tx with Rx on other PHYs */
+		{
+			.options = BT_CONN_LE_PHY_OPT_NONE,
+			.pref_tx_phy = BT_GAP_LE_PHY_2M,
+			.pref_rx_phy = BT_GAP_LE_PHY_1M,
+		}, {
+			.options = BT_CONN_LE_PHY_OPT_NONE,
+			.pref_tx_phy = BT_GAP_LE_PHY_2M,
+			.pref_rx_phy = BT_GAP_LE_PHY_2M,
+		}, {
+			.options = BT_CONN_LE_PHY_OPT_NONE,
+			.pref_tx_phy = BT_GAP_LE_PHY_2M,
+			.pref_rx_phy = BT_GAP_LE_PHY_CODED,
+		},
+
+		/* List of Coded PHY S8 Tx with Rx on other PHYs */
+		{
+			.options = BT_CONN_LE_PHY_OPT_CODED_S8,
+			.pref_tx_phy = BT_GAP_LE_PHY_CODED,
+			.pref_rx_phy = BT_GAP_LE_PHY_1M,
+		}, {
+			.options = BT_CONN_LE_PHY_OPT_CODED_S8,
+			.pref_tx_phy = BT_GAP_LE_PHY_CODED,
+			.pref_rx_phy = BT_GAP_LE_PHY_2M,
+		}, {
+			.options = BT_CONN_LE_PHY_OPT_CODED_S8,
+			.pref_tx_phy = BT_GAP_LE_PHY_CODED,
+			.pref_rx_phy = BT_GAP_LE_PHY_CODED,
+		},
+
+		/* List of Coded PHY S2 Tx with Rx on other PHYs */
+		{
+			.options = BT_CONN_LE_PHY_OPT_CODED_S2,
+			.pref_tx_phy = BT_GAP_LE_PHY_CODED,
+			.pref_rx_phy = BT_GAP_LE_PHY_1M,
+		}, {
+			.options = BT_CONN_LE_PHY_OPT_CODED_S2,
+			.pref_tx_phy = BT_GAP_LE_PHY_CODED,
+			.pref_rx_phy = BT_GAP_LE_PHY_2M,
+		}, {
+			.options = BT_CONN_LE_PHY_OPT_CODED_S2,
+			.pref_tx_phy = BT_GAP_LE_PHY_CODED,
+			.pref_rx_phy = BT_GAP_LE_PHY_CODED,
+		},
+
+		/* Finally stop at 2M Tx with Rx on 2M */
+		{
+			.options = BT_CONN_LE_PHY_OPT_NONE,
+			.pref_tx_phy = BT_GAP_LE_PHY_2M,
+			.pref_rx_phy = BT_GAP_LE_PHY_2M,
+		},
+	};
+	int err;
+
+	if (phy_update_countdown--) {
+		return;
+	}
+
+	phy_update_countdown = PHY_UPDATE_COUNTDOWN;
+
+	phy_param_idx++;
+	if (phy_param_idx >= ARRAY_SIZE(phy_param)) {
+		/* No more PHY updates, stay at the last index */
+		phy_param_idx = ARRAY_SIZE(phy_param);
+		return;
+	}
+
+	struct bt_conn_info conn_info;
+
+	err = bt_conn_get_info(conn, &conn_info);
+	if (err) {
+		printk("Failed to get connection info (%d).\n", err);
+		return;
+	}
+
+	struct bt_conn_le_phy_param conn_phy_param;
+
+	if (conn_info.role == BT_CONN_ROLE_CENTRAL) {
+		conn_phy_param.options = phy_param[phy_param_idx].options;
+		conn_phy_param.pref_tx_phy = phy_param[phy_param_idx].pref_tx_phy;
+		conn_phy_param.pref_rx_phy = phy_param[phy_param_idx].pref_rx_phy;
+	} else {
+		conn_phy_param.options = phy_param[phy_param_idx].options;
+		conn_phy_param.pref_tx_phy = phy_param[phy_param_idx].pref_rx_phy;
+		conn_phy_param.pref_rx_phy = phy_param[phy_param_idx].pref_tx_phy;
+	}
+
+	printk("%s: PHY Update requested %u %u (%u)\n", __func__,
+	       conn_phy_param.pref_tx_phy,
+	       conn_phy_param.pref_rx_phy,
+	       conn_phy_param.options);
+
+	err = bt_conn_le_phy_update(conn, &conn_phy_param);
+	if (err) {
+		printk("Failed to update PHY (%d).\n", err);
+		return;
+	}
+}
+
+/* Interval between storing the measured write rate */
+#define METRICS_INTERVAL 1U /* seconds */
+
 static struct bt_gatt_exchange_params mtu_exchange_params;
 static uint32_t write_count;
 static uint32_t write_len;
 static uint32_t write_rate;
+
+/* Globals, reused by central_gatt_write and peripheral_gatt_write samples */
 struct bt_conn *conn_connected;
 uint32_t last_write_rate;
 void (*start_scan_func)(void);
@@ -36,7 +163,7 @@ static void write_cmd_cb(struct bt_conn *conn, void *user_data)
 	/* if last data rx-ed was greater than 1 second in the past,
 	 * reset the metrics.
 	 */
-	if (delta > (1U * NSEC_PER_SEC)) {
+	if (delta > (METRICS_INTERVAL * NSEC_PER_SEC)) {
 		printk("%s: count= %u, len= %u, rate= %u bps.\n", __func__,
 		       write_count, write_len, write_rate);
 
@@ -46,6 +173,11 @@ static void write_cmd_cb(struct bt_conn *conn, void *user_data)
 		write_len = 0U;
 		write_rate = 0U;
 		cycle_stamp = k_cycle_get_32();
+
+		if (IS_ENABLED(CONFIG_BT_USER_PHY_UPDATE)) {
+			phy_update_iterate(conn);
+		}
+
 	} else {
 		uint16_t len;
 
@@ -55,7 +187,7 @@ static void write_cmd_cb(struct bt_conn *conn, void *user_data)
 		len = (uint32_t)user_data & 0xFFFF;
 
 		write_len += len;
-		write_rate = ((uint64_t)write_len << 3) * (1U * NSEC_PER_SEC) /
+		write_rate = ((uint64_t)write_len << 3) * (METRICS_INTERVAL * NSEC_PER_SEC) /
 			     delta;
 	}
 }
@@ -119,6 +251,11 @@ static void connected(struct bt_conn *conn, uint8_t conn_err)
 		}
 	}
 #endif
+
+	if (IS_ENABLED(CONFIG_BT_USER_PHY_UPDATE)) {
+		phy_update_countdown = PHY_UPDATE_COUNTDOWN;
+		phy_param_idx = 0U;
+	}
 }
 
 static void disconnected(struct bt_conn *conn, uint8_t reason)
@@ -171,14 +308,50 @@ static void security_changed(struct bt_conn *conn, bt_security_t level,
 }
 #endif
 
+#if defined(CONFIG_BT_USER_PHY_UPDATE)
+static void le_phy_updated(struct bt_conn *conn,
+			   struct bt_conn_le_phy_info *param)
+{
+	char addr[BT_ADDR_LE_STR_LEN];
+
+	bt_addr_le_to_str(bt_conn_get_dst(conn), addr, sizeof(addr));
+
+	printk("LE PHY Updated: %s Tx 0x%x, Rx 0x%x\n", addr, param->tx_phy,
+	       param->rx_phy);
+}
+#endif /* CONFIG_BT_USER_PHY_UPDATE */
+
+#if defined(CONFIG_BT_USER_DATA_LEN_UPDATE)
+static void le_data_len_updated(struct bt_conn *conn,
+				struct bt_conn_le_data_len_info *info)
+{
+	char addr[BT_ADDR_LE_STR_LEN];
+
+	bt_addr_le_to_str(bt_conn_get_dst(conn), addr, sizeof(addr));
+
+	printk("Data length updated: %s max tx %u (%u us) max rx %u (%u us)\n",
+	       addr, info->tx_max_len, info->tx_max_time, info->rx_max_len,
+	       info->rx_max_time);
+}
+#endif /* CONFIG_BT_USER_DATA_LEN_UPDATE */
+
 BT_CONN_CB_DEFINE(conn_callbacks) = {
 	.connected = connected,
 	.disconnected = disconnected,
 	.le_param_req = le_param_req,
 	.le_param_updated = le_param_updated,
+
 #if defined(CONFIG_BT_SMP)
 	.security_changed = security_changed,
 #endif
+
+#if defined(CONFIG_BT_USER_PHY_UPDATE)
+	.le_phy_updated = le_phy_updated,
+#endif /* CONFIG_BT_USER_PHY_UPDATE */
+
+#if defined(CONFIG_BT_USER_DATA_LEN_UPDATE)
+	.le_data_len_updated = le_data_len_updated,
+#endif /* CONFIG_BT_USER_DATA_LEN_UPDATE */
 };
 
 int write_cmd(struct bt_conn *conn)
diff --git a/samples/bluetooth/central_hr/prj_minimal.conf b/samples/bluetooth/central_hr/prj_minimal.conf
index be0ed341b78..2a4b31d5f03 100644
--- a/samples/bluetooth/central_hr/prj_minimal.conf
+++ b/samples/bluetooth/central_hr/prj_minimal.conf
@@ -94,7 +94,7 @@ CONFIG_BT_CTLR_PHY_2M=n
 # Reduce Bluetooth buffers
 CONFIG_BT_BUF_EVT_DISCARDABLE_COUNT=1
 CONFIG_BT_BUF_EVT_DISCARDABLE_SIZE=45
-CONFIG_BT_BUF_EVT_RX_COUNT=2
+CONFIG_BT_BUF_EVT_RX_COUNT=4
 
 CONFIG_BT_L2CAP_TX_BUF_COUNT=2
 CONFIG_BT_CTLR_RX_BUFFERS=1
diff --git a/samples/bluetooth/central_multilink/README.rst b/samples/bluetooth/central_multilink/README.rst
index 61d64d79806..2b31c6f614d 100644
--- a/samples/bluetooth/central_multilink/README.rst
+++ b/samples/bluetooth/central_multilink/README.rst
@@ -8,7 +8,7 @@ Overview
 ********
 
 Application demonstrating Bluetooth LE Central role functionality by scanning for other
-BLE devices and establishing connection to up to 62 peripherals with a strong
+Bluetooth LE devices and establishing connection to up to 62 peripherals with a strong
 enough signal.
 
 Requirements
diff --git a/samples/bluetooth/central_multilink/src/central_multilink.c b/samples/bluetooth/central_multilink/src/central_multilink.c
index 537b323efa4..f070ec56230 100644
--- a/samples/bluetooth/central_multilink/src/central_multilink.c
+++ b/samples/bluetooth/central_multilink/src/central_multilink.c
@@ -75,8 +75,9 @@ static void device_found(const bt_addr_le_t *addr, int8_t rssi, uint8_t type,
 		return;
 	}
 
-	if (bt_le_scan_stop()) {
-		printk("Scanning successfully stopped\n");
+	err = bt_le_scan_stop();
+	if (err != 0) {
+		printk("Failed to stop scanning (err %d)\n", err);
 		return;
 	}
 
diff --git a/samples/bluetooth/channel_sounding/README.rst b/samples/bluetooth/channel_sounding/README.rst
index 8f94a00b78c..971e3c4b940 100644
--- a/samples/bluetooth/channel_sounding/README.rst
+++ b/samples/bluetooth/channel_sounding/README.rst
@@ -37,7 +37,7 @@ connected devices are available in [#cs_setup_phase]_ and [#cs_start]_.
 Requirements
 ************
 
-* Two boards with Bluetooth LE and Channel Sounding support (such as an :ref:`nRF54L15 <nrf54l15dk_nrf54l15>`)
+* Two boards with Bluetooth LE and Channel Sounding support (such as an :zephyr:board:`nrf54l15dk`)
 * A controller that supports the Channel Sounding feature
 
 Building and Running
diff --git a/samples/bluetooth/direction_finding_central/README.rst b/samples/bluetooth/direction_finding_central/README.rst
index e6ce68d0352..9484092f885 100644
--- a/samples/bluetooth/direction_finding_central/README.rst
+++ b/samples/bluetooth/direction_finding_central/README.rst
@@ -15,7 +15,7 @@ Requirements
 ************
 
 * Nordic nRF SoC based board with Direction Finding support (example boards:
-  :ref:`nrf52833dk_nrf52833`, :ref:`nrf52833dk_nrf52820`, :ref:`nrf5340dk_nrf5340`)
+  :zephyr:board:`nrf52833dk`, :zephyr:board:`nrf5340dk`)
 * Antenna matrix for AoA (optional)
 
 Check your SoC's product specification for Direction Finding support if you are
diff --git a/samples/bluetooth/direction_finding_connectionless_rx/README.rst b/samples/bluetooth/direction_finding_connectionless_rx/README.rst
index 691e3f7e4eb..ec3cbfccf40 100644
--- a/samples/bluetooth/direction_finding_connectionless_rx/README.rst
+++ b/samples/bluetooth/direction_finding_connectionless_rx/README.rst
@@ -15,7 +15,7 @@ Requirements
 ************
 
 * Nordic nRF SoC based board with Direction Finding support (example boards:
-  :ref:`nrf52833dk_nrf52833`, :ref:`nrf5340dk_nrf5340`)
+  :zephyr:board:`nrf52833dk`, :zephyr:board:`nrf5340dk`)
 * Antenna matrix for AoA (optional)
 
 Check your SoC's product specification for Direction Finding support if you are
diff --git a/samples/bluetooth/direction_finding_connectionless_tx/README.rst b/samples/bluetooth/direction_finding_connectionless_tx/README.rst
index 004c5099962..437f53ee085 100644
--- a/samples/bluetooth/direction_finding_connectionless_tx/README.rst
+++ b/samples/bluetooth/direction_finding_connectionless_tx/README.rst
@@ -14,7 +14,7 @@ Requirements
 ************
 
 * Nordic nRF SoC based board with Direction Finding support (example boards:
-  :ref:`nrf52833dk_nrf52833`, :ref:`nrf5340dk_nrf5340`)
+  :zephyr:board:`nrf52833dk`, :zephyr:board:`nrf5340dk`)
 * Antenna matrix for AoD (optional)
 
 Check your SoC's product specification for Direction Finding support if you are
diff --git a/samples/bluetooth/direction_finding_peripheral/README.rst b/samples/bluetooth/direction_finding_peripheral/README.rst
index a7eb3cdf398..5bd4ee2a11b 100644
--- a/samples/bluetooth/direction_finding_peripheral/README.rst
+++ b/samples/bluetooth/direction_finding_peripheral/README.rst
@@ -14,7 +14,7 @@ Requirements
 ************
 
 * Nordic nRF SoC based board with Direction Finding support (example boards:
-  :ref:`nrf52833dk_nrf52833`, :ref:`nrf52833dk_nrf52820`, :ref:`nrf5340dk_nrf5340`)
+  :zephyr:board:`nrf52833dk`, :zephyr:board:`nrf5340dk`)
 * Antenna matrix for AoA (optional)
 
 Check your SoC's product specification for Direction Finding support if you are
diff --git a/samples/bluetooth/handsfree/boards/mimxrt1040_evk_mimxrt1042.conf b/samples/bluetooth/handsfree/boards/mimxrt1040_evk_mimxrt1042.conf
index 9e8851c73af..0dfb6c0bc02 100644
--- a/samples/bluetooth/handsfree/boards/mimxrt1040_evk_mimxrt1042.conf
+++ b/samples/bluetooth/handsfree/boards/mimxrt1040_evk_mimxrt1042.conf
@@ -1,2 +1,2 @@
-#select NXP NW612 Chipset
+#select NXP NW612 firmware for IW612 Chipset
 CONFIG_BT_NXP_NW612=y
diff --git a/samples/bluetooth/handsfree/src/main.c b/samples/bluetooth/handsfree/src/main.c
index 6aeb7219f0a..140eed4a350 100644
--- a/samples/bluetooth/handsfree/src/main.c
+++ b/samples/bluetooth/handsfree/src/main.c
@@ -19,67 +19,103 @@
 #include <zephyr/bluetooth/classic/hfp_hf.h>
 #include <zephyr/settings/settings.h>
 
-static void connected(struct bt_conn *conn)
+static void hf_connected(struct bt_conn *conn, struct bt_hfp_hf *hf)
 {
 	printk("HFP HF Connected!\n");
 }
 
-static void disconnected(struct bt_conn *conn)
+static void hf_disconnected(struct bt_hfp_hf *hf)
 {
 	printk("HFP HF Disconnected!\n");
 }
 
-static void service(struct bt_conn *conn, uint32_t value)
+static void hf_sco_connected(struct bt_hfp_hf *hf, struct bt_conn *sco_conn)
+{
+	printk("HF SCO connected\n");
+}
+
+static void hf_sco_disconnected(struct bt_conn *sco_conn, uint8_t reason)
+{
+	printk("HF SCO disconnected\n");
+}
+
+static void hf_service(struct bt_hfp_hf *hf, uint32_t value)
 {
 	printk("Service indicator value: %u\n", value);
 }
 
-static void call(struct bt_conn *conn, uint32_t value)
+static void hf_outgoing(struct bt_hfp_hf *hf, struct bt_hfp_hf_call *call)
+{
+	printk("HF call %p outgoing\n", call);
+}
+
+static void hf_remote_ringing(struct bt_hfp_hf_call *call)
+{
+	printk("HF remote call %p start ringing\n", call);
+}
+
+static void hf_incoming(struct bt_hfp_hf *hf, struct bt_hfp_hf_call *call)
+{
+	printk("HF call %p incoming\n", call);
+}
+
+static void hf_incoming_held(struct bt_hfp_hf_call *call)
+{
+	printk("HF call %p is held\n", call);
+}
+
+static void hf_accept(struct bt_hfp_hf_call *call)
 {
-	printk("Call indicator value: %u\n", value);
+	printk("HF call %p accepted\n", call);
 }
 
-static void call_setup(struct bt_conn *conn, uint32_t value)
+static void hf_reject(struct bt_hfp_hf_call *call)
 {
-	printk("Call Setup indicator value: %u\n", value);
+	printk("HF call %p rejected\n", call);
 }
 
-static void call_held(struct bt_conn *conn, uint32_t value)
+static void hf_terminate(struct bt_hfp_hf_call *call)
 {
-	printk("Call Held indicator value: %u\n", value);
+	printk("HF call %p terminated\n", call);
 }
 
-static void signal(struct bt_conn *conn, uint32_t value)
+static void hf_signal(struct bt_hfp_hf *hf, uint32_t value)
 {
 	printk("Signal indicator value: %u\n", value);
 }
 
-static void roam(struct bt_conn *conn, uint32_t value)
+static void hf_roam(struct bt_hfp_hf *hf, uint32_t value)
 {
 	printk("Roaming indicator value: %u\n", value);
 }
 
-static void battery(struct bt_conn *conn, uint32_t value)
+static void hf_battery(struct bt_hfp_hf *hf, uint32_t value)
 {
 	printk("Battery indicator value: %u\n", value);
 }
 
-static void ring_cb(struct bt_conn *conn)
+static void hf_ring_indication(struct bt_hfp_hf_call *call)
 {
-	printk("Incoming Call...\n");
+	printk("HF call %p ring\n", call);
 }
 
 static struct bt_hfp_hf_cb hf_cb = {
-	.connected = connected,
-	.disconnected = disconnected,
-	.service = service,
-	.call = call,
-	.call_setup = call_setup,
-	.call_held = call_held,
-	.signal = signal,
-	.roam = roam,
-	.battery = battery,
-	.ring_indication = ring_cb,
+	.connected = hf_connected,
+	.disconnected = hf_disconnected,
+	.sco_connected = hf_sco_connected,
+	.sco_disconnected = hf_sco_disconnected,
+	.service = hf_service,
+	.outgoing = hf_outgoing,
+	.remote_ringing = hf_remote_ringing,
+	.incoming = hf_incoming,
+	.incoming_held = hf_incoming_held,
+	.accept = hf_accept,
+	.reject = hf_reject,
+	.terminate = hf_terminate,
+	.signal = hf_signal,
+	.roam = hf_roam,
+	.battery = hf_battery,
+	.ring_indication = hf_ring_indication,
 };
 
 static void bt_ready(int err)
@@ -100,7 +136,7 @@ static void bt_ready(int err)
 		printk("BR/EDR set/rest connectable failed (err %d)\n", err);
 		return;
 	}
-	err = bt_br_set_discoverable(true);
+	err = bt_br_set_discoverable(true, false);
 	if (err) {
 		printk("BR/EDR set discoverable failed (err %d)\n", err);
 		return;
diff --git a/samples/bluetooth/handsfree_ag/src/main.c b/samples/bluetooth/handsfree_ag/src/main.c
index a87608c6eaa..0adbc951595 100644
--- a/samples/bluetooth/handsfree_ag/src/main.c
+++ b/samples/bluetooth/handsfree_ag/src/main.c
@@ -25,8 +25,7 @@
 
 static struct bt_conn *default_conn;
 struct bt_hfp_ag *hfp_ag;
-
-static struct bt_br_discovery_param br_discover;
+struct bt_hfp_ag_call *hfp_ag_call;
 
 static struct bt_br_discovery_param br_discover;
 static struct bt_br_discovery_result scan_result[CONFIG_BT_HFP_AG_DISCOVER_RESULT_COUNT];
@@ -41,8 +40,15 @@ struct k_work_delayable call_remote_accept_work;
 NET_BUF_POOL_DEFINE(sdp_discover_pool, 10, BT_L2CAP_BUF_SIZE(CONFIG_BT_L2CAP_TX_MTU),
 		    CONFIG_BT_CONN_TX_USER_DATA_SIZE, NULL);
 
-static void ag_connected(struct bt_hfp_ag *ag)
+static void ag_connected(struct bt_conn *conn, struct bt_hfp_ag *ag)
 {
+	if (conn != default_conn) {
+		printk("The conn %p is not aligned with ACL conn %p", conn, default_conn);
+	}
+
+	if (!hfp_ag) {
+		hfp_ag = ag;
+	}
 	printk("HFP AG connected!\n");
 	k_work_schedule(&call_connect_work, K_MSEC(CONFIG_BT_HFP_AG_START_CALL_DELAY_TIME));
 }
@@ -57,43 +63,45 @@ static void ag_sco_connected(struct bt_hfp_ag *ag, struct bt_conn *sco_conn)
 	printk("HFP AG SCO connected!\n");
 }
 
-static void ag_sco_disconnected(struct bt_hfp_ag *ag)
+static void ag_sco_disconnected(struct bt_conn *sco_conn, uint8_t reason)
 {
-	printk("HFP AG SCO disconnected!\n");
+	printk("HFP AG SCO disconnected %u!\n", reason);
 }
 
-static void ag_ringing(struct bt_hfp_ag *ag, bool in_band)
+static void ag_ringing(struct bt_hfp_ag_call *call, bool in_band)
 {
 	printk("Ringing (in bond? %s)\n", in_band ? "Yes" : "No");
 }
 
-static void ag_accept(struct bt_hfp_ag *ag)
+static void ag_accept(struct bt_hfp_ag_call *call)
 {
 	printk("Call Accepted\n");
 	k_work_schedule(&call_disconnect_work, K_SECONDS(10));
 }
 
-static void ag_reject(struct bt_hfp_ag *ag)
+static void ag_reject(struct bt_hfp_ag_call *call)
 {
 	printk("Call Rejected\n");
 	k_work_schedule(&call_disconnect_work, K_SECONDS(1));
 }
 
-static void ag_terminate(struct bt_hfp_ag *ag)
+static void ag_terminate(struct bt_hfp_ag_call *call)
 {
 	printk("Call terminated\n");
 	k_work_schedule(&call_disconnect_work, K_SECONDS(1));
 }
 
-static void ag_outgoing(struct bt_hfp_ag *ag, const char *number)
+static void ag_outgoing(struct bt_hfp_ag *ag, struct bt_hfp_ag_call *call, const char *number)
 {
+	hfp_ag_call = call;
 	printk("Call outgoing, remote number %s\n", number);
 	k_work_cancel_delayable(&call_connect_work);
 	k_work_schedule(&call_remote_ringing_work, K_SECONDS(1));
 }
 
-static void ag_incoming(struct bt_hfp_ag *ag, const char *number)
+static void ag_incoming(struct bt_hfp_ag *ag, struct bt_hfp_ag_call *call, const char *number)
 {
+	hfp_ag_call = call;
 	printk("Incoming call, remote number %s\n", number);
 	k_work_cancel_delayable(&call_connect_work);
 }
@@ -329,7 +337,7 @@ static void call_remote_ringing_work_handler(struct k_work *work)
 
 	printk("Remote starts ringing\n");
 
-	err = bt_hfp_ag_remote_ringing(hfp_ag);
+	err = bt_hfp_ag_remote_ringing(hfp_ag_call);
 
 	if (err != 0) {
 		printk("Fail to notify hfp unit that the remote starts ringing (err %d)\n", err);
@@ -344,7 +352,7 @@ static void call_remote_accept_work_handler(struct k_work *work)
 
 	printk("Remote accepts the call\n");
 
-	err = bt_hfp_ag_remote_accept(hfp_ag);
+	err = bt_hfp_ag_remote_accept(hfp_ag_call);
 
 	if (err != 0) {
 		printk("Fail to notify hfp unit that the remote accepts call (err %d)\n", err);
diff --git a/samples/bluetooth/hap_ha/src/bap_unicast_sr.c b/samples/bluetooth/hap_ha/src/bap_unicast_sr.c
index 6c8cd6fd862..b6f9658fc61 100644
--- a/samples/bluetooth/hap_ha/src/bap_unicast_sr.c
+++ b/samples/bluetooth/hap_ha/src/bap_unicast_sr.c
@@ -6,17 +6,28 @@
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
+#include <errno.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
 
-#include <zephyr/kernel.h>
-#include <zephyr/sys/byteorder.h>
-#include <zephyr/sys/printk.h>
-
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/audio/lc3.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/gap.h>
 #include <zephyr/bluetooth/hci.h>
 #include <zephyr/bluetooth/audio/audio.h>
 #include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/audio/pacs.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/bluetooth/iso.h>
+#include <zephyr/kernel.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/printk.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
 
 NET_BUF_POOL_FIXED_DEFINE(tx_pool, CONFIG_BT_ASCS_MAX_ASE_SRC_COUNT,
 			  BT_ISO_SDU_BUF_SIZE(CONFIG_BT_ISO_TX_MTU),
@@ -405,6 +416,20 @@ static struct bt_pacs_cap cap_source = {
 
 int bap_unicast_sr_init(void)
 {
+	const struct bt_pacs_register_param pacs_param = {
+		.snk_pac = true,
+		.snk_loc = true,
+		.src_pac = true,
+		.src_loc = true,
+	};
+	int err;
+
+	err = bt_pacs_register(&pacs_param);
+	if (err) {
+		printk("Could not register PACS (err %d)\n", err);
+		return err;
+	}
+
 	bt_bap_unicast_server_register(&param);
 	bt_bap_unicast_server_register_cb(&unicast_server_cb);
 
diff --git a/samples/bluetooth/hap_ha/src/ccp_call_ctrl.c b/samples/bluetooth/hap_ha/src/ccp_call_ctrl.c
index dcf1c4dffb4..82da06d7f08 100644
--- a/samples/bluetooth/hap_ha/src/ccp_call_ctrl.c
+++ b/samples/bluetooth/hap_ha/src/ccp_call_ctrl.c
@@ -6,14 +6,16 @@
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
+#include <stdint.h>
 
-#include <zephyr/kernel.h>
-#include <zephyr/sys/printk.h>
-#include <zephyr/sys/util.h>
-
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/hci.h>
 #include <zephyr/bluetooth/audio/tbs.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/printk.h>
+#include <zephyr/sys/util.h>
 
 enum {
 	CCP_FLAG_PROFILE_CONNECTED,
diff --git a/samples/bluetooth/hap_ha/src/csip_set_member.c b/samples/bluetooth/hap_ha/src/csip_set_member.c
index 962ac3579da..d3b258e7edf 100644
--- a/samples/bluetooth/hap_ha/src/csip_set_member.c
+++ b/samples/bluetooth/hap_ha/src/csip_set_member.c
@@ -5,12 +5,16 @@
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
+#include <errno.h>
+#include <stddef.h>
+#include <stdint.h>
 
-#include <zephyr/kernel.h>
-#include <zephyr/sys/printk.h>
-
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/audio/cap.h>
 #include <zephyr/bluetooth/audio/csip.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/printk.h>
 
 #define CSIP_SIRK_DEBUG	{ 0xcd, 0xcc, 0x72, 0xdd, 0x86, 0x8c, 0xcd, 0xce, \
 			  0x22, 0xfd, 0xa1, 0x21, 0x09, 0x7d, 0x7d, 0x45 }
diff --git a/samples/bluetooth/hap_ha/src/hap_ha.h b/samples/bluetooth/hap_ha/src/hap_ha.h
index e4964035355..5e1915c970a 100644
--- a/samples/bluetooth/hap_ha/src/hap_ha.h
+++ b/samples/bluetooth/hap_ha/src/hap_ha.h
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/types.h>
+#include <stdint.h>
 
 /**
  * @brief Initialize the BAP Unicast Server role
diff --git a/samples/bluetooth/hap_ha/src/has_server.c b/samples/bluetooth/hap_ha/src/has_server.c
index b23b5a3c9a6..5faf24735d9 100644
--- a/samples/bluetooth/hap_ha/src/has_server.c
+++ b/samples/bluetooth/hap_ha/src/has_server.c
@@ -5,12 +5,15 @@
  *
  *  SPDX-License-Identifier: Apache-2.0
  */
+#include <stddef.h>
+#include <stdint.h>
 
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/audio/has.h>
 #include <zephyr/kernel.h>
 #include <zephyr/sys/printk.h>
 #include <zephyr/sys/util.h>
-
-#include <zephyr/bluetooth/audio/has.h>
+#include <zephyr/sys/util_macro.h>
 
 #define PRESET_INDEX_UNIVERSAL  1
 #define PRESET_INDEX_OUTDOOR    5
diff --git a/samples/bluetooth/hap_ha/src/main.c b/samples/bluetooth/hap_ha/src/main.c
index 04c865b984d..0822ef95abd 100644
--- a/samples/bluetooth/hap_ha/src/main.c
+++ b/samples/bluetooth/hap_ha/src/main.c
@@ -3,10 +3,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-
-#include <zephyr/kernel.h>
-#include <zephyr/sys/byteorder.h>
-#include <zephyr/sys/printk.h>
+#include <stddef.h>
+#include <stdint.h>
 
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/byteorder.h>
@@ -15,7 +13,15 @@
 #include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/audio/pacs.h>
 #include <zephyr/bluetooth/audio/csip.h>
+#include <zephyr/bluetooth/gap.h>
 #include <zephyr/bluetooth/services/ias.h>
+#include <zephyr/bluetooth/uuid.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/printk.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
 
 #include "hap_ha.h"
 
diff --git a/samples/bluetooth/hap_ha/src/micp_mic_dev.c b/samples/bluetooth/hap_ha/src/micp_mic_dev.c
index bd36c587002..e579836ced6 100644
--- a/samples/bluetooth/hap_ha/src/micp_mic_dev.c
+++ b/samples/bluetooth/hap_ha/src/micp_mic_dev.c
@@ -8,13 +8,16 @@
  *  SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/kernel.h>
-#include <zephyr/sys/printk.h>
-#include <stdlib.h>
+#include <stdint.h>
 #include <stdio.h>
+#include <string.h>
 
+#include <zephyr/bluetooth/audio/aics.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/audio/micp.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/printk.h>
+#include <zephyr/sys/util.h>
 
 static void micp_mic_dev_mute_cb(uint8_t mute)
 {
diff --git a/samples/bluetooth/hap_ha/src/vcp_vol_renderer.c b/samples/bluetooth/hap_ha/src/vcp_vol_renderer.c
index 4e2c47744e7..cfe7e1f6470 100644
--- a/samples/bluetooth/hap_ha/src/vcp_vol_renderer.c
+++ b/samples/bluetooth/hap_ha/src/vcp_vol_renderer.c
@@ -8,13 +8,17 @@
  *  SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/kernel.h>
-#include <zephyr/sys/printk.h>
-#include <stdlib.h>
+#include <stdint.h>
 #include <stdio.h>
+#include <string.h>
 
+#include <zephyr/bluetooth/audio/aics.h>
+#include <zephyr/bluetooth/audio/vocs.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/audio/vcp.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/printk.h>
+#include <zephyr/sys/util.h>
 
 static struct bt_vcp_included vcp_included;
 
diff --git a/samples/bluetooth/hci_ipc/nrf5340_cpunet_bis-bt_ll_sw_split.conf b/samples/bluetooth/hci_ipc/nrf5340_cpunet_bis-bt_ll_sw_split.conf
index f58d44035a7..e1b91fa381a 100644
--- a/samples/bluetooth/hci_ipc/nrf5340_cpunet_bis-bt_ll_sw_split.conf
+++ b/samples/bluetooth/hci_ipc/nrf5340_cpunet_bis-bt_ll_sw_split.conf
@@ -10,12 +10,7 @@ CONFIG_HEAP_MEM_POOL_SIZE=4096
 CONFIG_BT=y
 CONFIG_BT_HCI_RAW=y
 
-# Workaround: Unable to allocate command buffer when using K_NO_WAIT since
-# Host number of completed commands does not follow normal flow control.
-CONFIG_BT_BUF_CMD_TX_COUNT=10
-
 CONFIG_BT_BUF_EVT_RX_COUNT=16
-
 CONFIG_BT_BUF_EVT_RX_SIZE=255
 CONFIG_BT_BUF_ACL_RX_SIZE=255
 CONFIG_BT_BUF_ACL_TX_SIZE=251
@@ -106,6 +101,7 @@ CONFIG_BT_CTLR_SYNC_ISO_PDU_LEN_MAX=251
 CONFIG_BT_CTLR_ISOAL_SOURCES=4
 CONFIG_BT_CTLR_ISO_TX_BUFFERS=12
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=255
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=247
 
 # ISO Receptions
 CONFIG_BT_CTLR_ISO_RX_BUFFERS=8
diff --git a/samples/bluetooth/hci_ipc/nrf5340_cpunet_bt_mesh-bt_ll_sw_split.conf b/samples/bluetooth/hci_ipc/nrf5340_cpunet_bt_mesh-bt_ll_sw_split.conf
index 8a031231c5a..89ba46ff357 100644
--- a/samples/bluetooth/hci_ipc/nrf5340_cpunet_bt_mesh-bt_ll_sw_split.conf
+++ b/samples/bluetooth/hci_ipc/nrf5340_cpunet_bt_mesh-bt_ll_sw_split.conf
@@ -10,11 +10,6 @@ CONFIG_BT=y
 CONFIG_BT_HCI_RAW=y
 CONFIG_BT_MAX_CONN=16
 
-
-# Workaround: Unable to allocate command buffer when using K_NO_WAIT since
-# Host number of completed commands does not follow normal flow control.
-CONFIG_BT_BUF_CMD_TX_COUNT=10
-
 # Controller
 CONFIG_BT_LL_SW_SPLIT=y
 
diff --git a/samples/bluetooth/hci_ipc/nrf5340_cpunet_cis-bt_ll_sw_split.conf b/samples/bluetooth/hci_ipc/nrf5340_cpunet_cis-bt_ll_sw_split.conf
index db4705c7b1e..c71e29d0b07 100644
--- a/samples/bluetooth/hci_ipc/nrf5340_cpunet_cis-bt_ll_sw_split.conf
+++ b/samples/bluetooth/hci_ipc/nrf5340_cpunet_cis-bt_ll_sw_split.conf
@@ -10,12 +10,7 @@ CONFIG_HEAP_MEM_POOL_SIZE=4096
 CONFIG_BT=y
 CONFIG_BT_HCI_RAW=y
 
-# Workaround: Unable to allocate command buffer when using K_NO_WAIT since
-# Host number of completed commands does not follow normal flow control.
-CONFIG_BT_BUF_CMD_TX_COUNT=10
-
 CONFIG_BT_BUF_EVT_RX_COUNT=16
-
 CONFIG_BT_BUF_EVT_RX_SIZE=255
 CONFIG_BT_BUF_ACL_RX_SIZE=255
 CONFIG_BT_BUF_ACL_TX_SIZE=251
@@ -89,7 +84,6 @@ CONFIG_BT_CTLR_PERIPHERAL_ISO=y
 CONFIG_BT_CTLR_CONN_ISO_GROUPS=1
 CONFIG_BT_CTLR_CONN_ISO_STREAMS=2
 CONFIG_BT_CTLR_CONN_ISO_STREAMS_PER_GROUP=2
-CONFIG_BT_CTLR_CONN_ISO_SDU_LEN_MAX=247
 CONFIG_BT_CTLR_CONN_ISO_PDU_LEN_MAX=251
 CONFIG_BT_CTLR_CONN_ISO_LOW_LATENCY_POLICY=y
 
@@ -97,6 +91,7 @@ CONFIG_BT_CTLR_CONN_ISO_LOW_LATENCY_POLICY=y
 CONFIG_BT_CTLR_ISOAL_SOURCES=2
 CONFIG_BT_CTLR_ISO_TX_BUFFERS=12
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=255
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=247
 
 # ISO Receptions
 CONFIG_BT_CTLR_ISO_RX_BUFFERS=8
diff --git a/samples/bluetooth/hci_ipc/nrf5340_cpunet_df-bt_ll_sw_split.conf b/samples/bluetooth/hci_ipc/nrf5340_cpunet_df-bt_ll_sw_split.conf
index 19adc889598..538d965c12a 100644
--- a/samples/bluetooth/hci_ipc/nrf5340_cpunet_df-bt_ll_sw_split.conf
+++ b/samples/bluetooth/hci_ipc/nrf5340_cpunet_df-bt_ll_sw_split.conf
@@ -10,12 +10,7 @@ CONFIG_HEAP_MEM_POOL_SIZE=4096
 CONFIG_BT=y
 CONFIG_BT_HCI_RAW=y
 
-# Workaround: Unable to allocate command buffer when using K_NO_WAIT since
-# Host number of completed commands does not follow normal flow control.
-CONFIG_BT_BUF_CMD_TX_COUNT=10
-
 CONFIG_BT_BUF_EVT_RX_COUNT=16
-
 CONFIG_BT_BUF_EVT_RX_SIZE=255
 CONFIG_BT_BUF_ACL_RX_SIZE=255
 CONFIG_BT_BUF_ACL_TX_SIZE=251
diff --git a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso-bt_ll_sw_split.conf b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso-bt_ll_sw_split.conf
index 6c28a4537e6..21c5ac86e7c 100644
--- a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso-bt_ll_sw_split.conf
+++ b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso-bt_ll_sw_split.conf
@@ -14,12 +14,7 @@ CONFIG_LTO=y
 CONFIG_BT=y
 CONFIG_BT_HCI_RAW=y
 
-# Workaround: Unable to allocate command buffer when using K_NO_WAIT since
-# Host number of completed commands does not follow normal flow control.
-CONFIG_BT_BUF_CMD_TX_COUNT=10
-
 CONFIG_BT_BUF_EVT_RX_COUNT=16
-
 CONFIG_BT_BUF_EVT_RX_SIZE=255
 CONFIG_BT_BUF_ACL_RX_SIZE=255
 CONFIG_BT_BUF_ACL_TX_SIZE=251
@@ -104,6 +99,8 @@ CONFIG_BT_CTLR_ADV_EXT=y
 CONFIG_BT_CTLR_ADV_PERIODIC=y
 CONFIG_BT_CTLR_SYNC_TRANSFER_SENDER=y
 CONFIG_BT_CTLR_ADV_ISO=y
+CONFIG_BT_CTLR_ADV_ISO_SEQUENTIAL=y
+CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED=y
 CONFIG_BT_CTLR_ADV_ISO_SET=1
 CONFIG_BT_CTLR_ADV_ISO_STREAM_COUNT=2
 CONFIG_BT_CTLR_ADV_ISO_STREAM_MAX=2
@@ -114,6 +111,8 @@ CONFIG_BT_CTLR_ADV_EXT=y
 CONFIG_BT_CTLR_SYNC_PERIODIC=y
 CONFIG_BT_CTLR_SYNC_TRANSFER_RECEIVER=y
 CONFIG_BT_CTLR_SYNC_ISO=y
+CONFIG_BT_CTLR_SYNC_ISO_SEQUENTIAL=y
+CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED=y
 CONFIG_BT_CTLR_SCAN_SYNC_ISO_SET=1
 CONFIG_BT_CTLR_SYNC_ISO_STREAM_COUNT=2
 CONFIG_BT_CTLR_SYNC_ISO_STREAM_MAX=2
@@ -125,7 +124,6 @@ CONFIG_BT_CTLR_PERIPHERAL_ISO=y
 CONFIG_BT_CTLR_CONN_ISO_GROUPS=1
 CONFIG_BT_CTLR_CONN_ISO_STREAMS=2
 CONFIG_BT_CTLR_CONN_ISO_STREAMS_PER_GROUP=2
-CONFIG_BT_CTLR_CONN_ISO_SDU_LEN_MAX=247
 CONFIG_BT_CTLR_CONN_ISO_PDU_LEN_MAX=251
 CONFIG_BT_CTLR_CONN_ISO_LOW_LATENCY_POLICY=y
 
@@ -133,6 +131,7 @@ CONFIG_BT_CTLR_CONN_ISO_LOW_LATENCY_POLICY=y
 CONFIG_BT_CTLR_ISOAL_SOURCES=2
 CONFIG_BT_CTLR_ISO_TX_BUFFERS=8
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=255
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=247
 
 # ISO Receptions
 CONFIG_BT_CTLR_ISOAL_SINKS=2
diff --git a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_broadcast-bt_ll_sw_split.conf b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_broadcast-bt_ll_sw_split.conf
index 0fec7c0d824..c63928dd27c 100644
--- a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_broadcast-bt_ll_sw_split.conf
+++ b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_broadcast-bt_ll_sw_split.conf
@@ -10,10 +10,6 @@ CONFIG_HEAP_MEM_POOL_SIZE=4096
 CONFIG_BT=y
 CONFIG_BT_HCI_RAW=y
 
-# Workaround: Unable to allocate command buffer when using K_NO_WAIT since
-# Host number of completed commands does not follow normal flow control.
-CONFIG_BT_BUF_CMD_TX_COUNT=10
-
 # Host and Controller common dependencies
 CONFIG_BT_BROADCASTER=y
 CONFIG_BT_OBSERVER=n
@@ -45,6 +41,7 @@ CONFIG_BT_CTLR_ISOAL_SOURCES=4
 
 CONFIG_BT_CTLR_ISO_TX_BUFFERS=12
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=255
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=247
 
 CONFIG_BT_CTLR_ADVANCED_FEATURES=y
 CONFIG_BT_CTLR_ADV_RESERVE_MAX=n
diff --git a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_central-bt_ll_sw_split.conf b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_central-bt_ll_sw_split.conf
index 58469a0309b..90565665e3a 100644
--- a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_central-bt_ll_sw_split.conf
+++ b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_central-bt_ll_sw_split.conf
@@ -10,10 +10,6 @@ CONFIG_HEAP_MEM_POOL_SIZE=4096
 CONFIG_BT=y
 CONFIG_BT_HCI_RAW=y
 
-# Workaround: Unable to allocate command buffer when using K_NO_WAIT since
-# Host number of completed commands does not follow normal flow control.
-CONFIG_BT_BUF_CMD_TX_COUNT=10
-
 CONFIG_BT_BUF_EVT_RX_SIZE=255
 CONFIG_BT_BUF_ACL_RX_SIZE=255
 CONFIG_BT_BUF_ACL_TX_SIZE=251
@@ -53,7 +49,6 @@ CONFIG_BT_CTLR_PERIPHERAL_ISO=n
 CONFIG_BT_CTLR_CONN_ISO_GROUPS=1
 CONFIG_BT_CTLR_CONN_ISO_STREAMS=2
 CONFIG_BT_CTLR_CONN_ISO_STREAMS_PER_GROUP=2
-CONFIG_BT_CTLR_CONN_ISO_SDU_LEN_MAX=247
 CONFIG_BT_CTLR_CONN_ISO_PDU_LEN_MAX=251
 CONFIG_BT_CTLR_CONN_ISO_LOW_LATENCY_POLICY=y
 
@@ -61,6 +56,7 @@ CONFIG_BT_CTLR_CONN_ISO_LOW_LATENCY_POLICY=y
 CONFIG_BT_CTLR_ISOAL_SOURCES=2
 CONFIG_BT_CTLR_ISO_TX_BUFFERS=12
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=255
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=247
 
 # ISO Receptions
 CONFIG_BT_CTLR_ISOAL_SINKS=2
diff --git a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_peripheral-bt_ll_sw_split.conf b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_peripheral-bt_ll_sw_split.conf
index 1ff7ad685cf..9120f517800 100644
--- a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_peripheral-bt_ll_sw_split.conf
+++ b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_peripheral-bt_ll_sw_split.conf
@@ -10,10 +10,6 @@ CONFIG_HEAP_MEM_POOL_SIZE=4096
 CONFIG_BT=y
 CONFIG_BT_HCI_RAW=y
 
-# Workaround: Unable to allocate command buffer when using K_NO_WAIT since
-# Host number of completed commands does not follow normal flow control.
-CONFIG_BT_BUF_CMD_TX_COUNT=10
-
 CONFIG_BT_BUF_EVT_RX_SIZE=255
 CONFIG_BT_BUF_ACL_RX_SIZE=255
 CONFIG_BT_BUF_ACL_TX_SIZE=251
@@ -53,7 +49,6 @@ CONFIG_BT_CTLR_PERIPHERAL_ISO=y
 CONFIG_BT_CTLR_CONN_ISO_GROUPS=1
 CONFIG_BT_CTLR_CONN_ISO_STREAMS=2
 CONFIG_BT_CTLR_CONN_ISO_STREAMS_PER_GROUP=2
-CONFIG_BT_CTLR_CONN_ISO_SDU_LEN_MAX=247
 CONFIG_BT_CTLR_CONN_ISO_PDU_LEN_MAX=251
 CONFIG_BT_CTLR_CONN_ISO_LOW_LATENCY_POLICY=y
 
@@ -61,6 +56,7 @@ CONFIG_BT_CTLR_CONN_ISO_LOW_LATENCY_POLICY=y
 CONFIG_BT_CTLR_ISOAL_SOURCES=2
 CONFIG_BT_CTLR_ISO_TX_BUFFERS=12
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=255
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=247
 
 # ISO Receptions
 CONFIG_BT_CTLR_ISOAL_SINKS=2
diff --git a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_receive-bt_ll_sw_split.conf b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_receive-bt_ll_sw_split.conf
index 0375097d091..ed0ccb14ef7 100644
--- a/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_receive-bt_ll_sw_split.conf
+++ b/samples/bluetooth/hci_ipc/nrf5340_cpunet_iso_receive-bt_ll_sw_split.conf
@@ -10,10 +10,6 @@ CONFIG_HEAP_MEM_POOL_SIZE=4096
 CONFIG_BT=y
 CONFIG_BT_HCI_RAW=y
 
-# Workaround: Unable to allocate command buffer when using K_NO_WAIT since
-# Host number of completed commands does not follow normal flow control.
-CONFIG_BT_BUF_CMD_TX_COUNT=10
-
 # Host and Controller common dependencies
 CONFIG_BT_BROADCASTER=n
 CONFIG_BT_OBSERVER=y
diff --git a/samples/bluetooth/hci_ipc/prj.conf b/samples/bluetooth/hci_ipc/prj.conf
index 08b1aed9e7f..f73553b47e6 100644
--- a/samples/bluetooth/hci_ipc/prj.conf
+++ b/samples/bluetooth/hci_ipc/prj.conf
@@ -10,11 +10,6 @@ CONFIG_BT=y
 CONFIG_BT_HCI_RAW=y
 CONFIG_BT_MAX_CONN=16
 
-
-# Workaround: Unable to allocate command buffer when using K_NO_WAIT since
-# Host number of completed commands does not follow normal flow control.
-CONFIG_BT_BUF_CMD_TX_COUNT=10
-
 # Enable and adjust the below value as necessary
 # CONFIG_BT_BUF_EVT_RX_COUNT=16
 # CONFIG_BT_BUF_EVT_RX_SIZE=255
diff --git a/samples/bluetooth/hci_ipc/src/main.c b/samples/bluetooth/hci_ipc/src/main.c
index 4de71c85e34..c08a485df1c 100644
--- a/samples/bluetooth/hci_ipc/src/main.c
+++ b/samples/bluetooth/hci_ipc/src/main.c
@@ -29,6 +29,9 @@
 
 LOG_MODULE_REGISTER(hci_ipc, CONFIG_BT_LOG_LEVEL);
 
+BUILD_ASSERT(!IS_ENABLED(CONFIG_BT_CONN) || IS_ENABLED(CONFIG_BT_HCI_ACL_FLOW_CONTROL),
+	     "HCI IPC driver can drop ACL data without Controller-to-Host ACL flow control");
+
 static struct ipc_ept hci_ept;
 
 static K_THREAD_STACK_DEFINE(tx_thread_stack, CONFIG_BT_HCI_TX_STACK_SIZE);
diff --git a/samples/bluetooth/hci_spi/README.rst b/samples/bluetooth/hci_spi/README.rst
index b29ab85b72c..8964b5d6cab 100644
--- a/samples/bluetooth/hci_spi/README.rst
+++ b/samples/bluetooth/hci_spi/README.rst
@@ -25,7 +25,7 @@ the host and associates the application with a SPI bus to use.
 
 See :zephyr_file:`boards/nrf51dk_nrf51822.overlay
 <samples/bluetooth/hci_spi/boards/nrf51dk_nrf51822.overlay>` in this sample
-directory for an example overlay for the :ref:`nrf51dk_nrf51822` board.
+directory for an example overlay for the :zephyr:board:`nrf51dk` board.
 
 You can then build this application and flash it onto your board in
 the usual way; see :ref:`boards` for board-specific building and
diff --git a/samples/bluetooth/hci_spi/prj.conf b/samples/bluetooth/hci_spi/prj.conf
index fbab977c266..54fa4acf0c5 100644
--- a/samples/bluetooth/hci_spi/prj.conf
+++ b/samples/bluetooth/hci_spi/prj.conf
@@ -5,7 +5,3 @@ CONFIG_MAIN_STACK_SIZE=512
 CONFIG_BT=y
 CONFIG_BT_HCI_RAW=y
 CONFIG_BT_MAX_CONN=16
-
-# Workaround: Unable to allocate command buffer when using K_NO_WAIT since
-# Host number of completed commands does not follow normal flow control.
-CONFIG_BT_BUF_CMD_TX_COUNT=10
diff --git a/samples/bluetooth/hci_uart/README.rst b/samples/bluetooth/hci_uart/README.rst
index 5c5ab8b7198..2260c7e0d29 100644
--- a/samples/bluetooth/hci_uart/README.rst
+++ b/samples/bluetooth/hci_uart/README.rst
@@ -33,11 +33,11 @@ Zephyr tree, and it is built as a standard Zephyr application.
 Using the controller with emulators and BlueZ
 *********************************************
 
-The instructions below show how to use a Nordic nRF5x device as a Zephyr BLE
+The instructions below show how to use a Nordic nRF5x device as a Zephyr Bluetooth
 controller and expose it to Linux's BlueZ. This can be very useful for testing
 the Zephyr Link Layer with the BlueZ Host. The Zephyr Bluetooth LE controller can also
 provide a modern Bluetooth LE 5.0 controller to a Linux-based machine for native
-BLE support or QEMU-based development.
+Bluetooth support or QEMU-based development.
 
 First, make sure you have a recent BlueZ version installed by following the
 instructions in the :ref:`bluetooth_bluez` section.
diff --git a/samples/bluetooth/hci_uart/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/samples/bluetooth/hci_uart/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..362de531b25
--- /dev/null
+++ b/samples/bluetooth/hci_uart/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&uart20 {
+	compatible = "nordic,nrf-uarte";
+	current-speed = <1000000>;
+	status = "okay";
+	hw-flow-control;
+};
diff --git a/samples/bluetooth/hci_uart/boards/bl54l15_dvk_nrf54l15_cpuapp_df.overlay b/samples/bluetooth/hci_uart/boards/bl54l15_dvk_nrf54l15_cpuapp_df.overlay
new file mode 100644
index 00000000000..4bdb11e70fd
--- /dev/null
+++ b/samples/bluetooth/hci_uart/boards/bl54l15_dvk_nrf54l15_cpuapp_df.overlay
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&uart20 {
+	compatible = "nordic,nrf-uarte";
+	current-speed = <1000000>;
+	status = "okay";
+	hw-flow-control;
+};
+
+&radio {
+	status = "okay";
+	/* This is an example number of antennas that may be available
+	 * on antenna matrix board.
+	 */
+	dfe-antenna-num = <10>;
+	/* This is an example switch pattern that will be used to set an
+	 * antenna for Tx PDU (period before start of Tx CTE).
+	 */
+	dfe-pdu-antenna = <0x0>;
+
+	/* These are example GPIO pin numbers that are provided to
+	 * Radio peripheral. The pins will be acquired by Radio to
+	 * drive antenna switching when AoD is enabled.
+	 */
+	dfegpio0-gpios = <&gpio1 4 0>;
+	dfegpio1-gpios = <&gpio1 5 0>;
+	dfegpio2-gpios = <&gpio1 6 0>;
+	dfegpio3-gpios = <&gpio1 7 0>;
+};
diff --git a/samples/bluetooth/hci_uart/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/samples/bluetooth/hci_uart/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..362de531b25
--- /dev/null
+++ b/samples/bluetooth/hci_uart/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&uart20 {
+	compatible = "nordic,nrf-uarte";
+	current-speed = <1000000>;
+	status = "okay";
+	hw-flow-control;
+};
diff --git a/samples/bluetooth/hci_uart/boards/bl54l15u_dvk_nrf54l15_cpuapp_df.overlay b/samples/bluetooth/hci_uart/boards/bl54l15u_dvk_nrf54l15_cpuapp_df.overlay
new file mode 100644
index 00000000000..4bdb11e70fd
--- /dev/null
+++ b/samples/bluetooth/hci_uart/boards/bl54l15u_dvk_nrf54l15_cpuapp_df.overlay
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&uart20 {
+	compatible = "nordic,nrf-uarte";
+	current-speed = <1000000>;
+	status = "okay";
+	hw-flow-control;
+};
+
+&radio {
+	status = "okay";
+	/* This is an example number of antennas that may be available
+	 * on antenna matrix board.
+	 */
+	dfe-antenna-num = <10>;
+	/* This is an example switch pattern that will be used to set an
+	 * antenna for Tx PDU (period before start of Tx CTE).
+	 */
+	dfe-pdu-antenna = <0x0>;
+
+	/* These are example GPIO pin numbers that are provided to
+	 * Radio peripheral. The pins will be acquired by Radio to
+	 * drive antenna switching when AoD is enabled.
+	 */
+	dfegpio0-gpios = <&gpio1 4 0>;
+	dfegpio1-gpios = <&gpio1 5 0>;
+	dfegpio2-gpios = <&gpio1 6 0>;
+	dfegpio3-gpios = <&gpio1 7 0>;
+};
diff --git a/samples/bluetooth/hci_uart/boards/nrf5340dk_nrf5340_cpuapp.conf b/samples/bluetooth/hci_uart/boards/nrf5340dk_nrf5340_cpuapp.conf
new file mode 100644
index 00000000000..b290e9f8eeb
--- /dev/null
+++ b/samples/bluetooth/hci_uart/boards/nrf5340dk_nrf5340_cpuapp.conf
@@ -0,0 +1,16 @@
+# Host and Controller common dependencies
+CONFIG_BT_EXT_ADV=y
+CONFIG_BT_PER_ADV=y
+CONFIG_BT_PER_ADV_SYNC=y
+CONFIG_BT_PER_ADV_SYNC_MAX=2
+
+# Broadcast and Connected ISO
+CONFIG_BT_ISO_BROADCASTER=y
+CONFIG_BT_ISO_SYNC_RECEIVER=y
+CONFIG_BT_ISO_CENTRAL=y
+CONFIG_BT_ISO_PERIPHERAL=y
+
+# ISO Streams
+CONFIG_BT_ISO_MAX_CHAN=4
+CONFIG_BT_ISO_TX_BUF_COUNT=18
+CONFIG_BT_ISO_RX_BUF_COUNT=1
diff --git a/samples/bluetooth/hci_uart/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/samples/bluetooth/hci_uart/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..32ba7837840
--- /dev/null
+++ b/samples/bluetooth/hci_uart/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&uart20 {
+	compatible = "nordic,nrf-uarte";
+	current-speed = <1000000>;
+	status = "okay";
+	hw-flow-control;
+};
diff --git a/samples/bluetooth/hci_uart/boards/panb511evb_nrf54l15_cpuapp.overlay b/samples/bluetooth/hci_uart/boards/panb511evb_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..fde3e0775dd
--- /dev/null
+++ b/samples/bluetooth/hci_uart/boards/panb511evb_nrf54l15_cpuapp.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&uart30 {
+	compatible = "nordic,nrf-uarte";
+	current-speed = <1000000>;
+	status = "okay";
+	hw-flow-control;
+};
diff --git a/samples/bluetooth/hci_uart/boards/panb511evb_nrf54l15_cpuapp_df.overlay b/samples/bluetooth/hci_uart/boards/panb511evb_nrf54l15_cpuapp_df.overlay
new file mode 100644
index 00000000000..0d2af26d4ed
--- /dev/null
+++ b/samples/bluetooth/hci_uart/boards/panb511evb_nrf54l15_cpuapp_df.overlay
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&uart30 {
+	compatible = "nordic,nrf-uarte";
+	current-speed = <1000000>;
+	status = "okay";
+	hw-flow-control;
+};
+
+&radio {
+	status = "okay";
+	/* This is an example number of antennas that may be available
+	 * on antenna matrix board.
+	 */
+	dfe-antenna-num = <10>;
+	/* This is an example switch pattern that will be used to set an
+	 * antenna for Tx PDU (period before start of Tx CTE).
+	 */
+	dfe-pdu-antenna = <0x0>;
+
+	/* These are example GPIO pin numbers that are provided to
+	 * Radio peripheral. The pins will be acquired by Radio to
+	 * drive antenna switching when AoD is enabled.
+	 */
+	dfegpio0-gpios = <&gpio1 4 0>;
+	dfegpio1-gpios = <&gpio1 5 0>;
+	dfegpio2-gpios = <&gpio1 6 0>;
+	dfegpio3-gpios = <&gpio1 7 0>;
+};
diff --git a/samples/bluetooth/hci_uart/overlay-all-bt_ll_sw_split.conf b/samples/bluetooth/hci_uart/overlay-all-bt_ll_sw_split.conf
index a4054de0934..18c87bc0c18 100644
--- a/samples/bluetooth/hci_uart/overlay-all-bt_ll_sw_split.conf
+++ b/samples/bluetooth/hci_uart/overlay-all-bt_ll_sw_split.conf
@@ -94,6 +94,8 @@ CONFIG_BT_CTLR_ADV_EXT=y
 CONFIG_BT_CTLR_ADV_PERIODIC=y
 CONFIG_BT_CTLR_SYNC_TRANSFER_SENDER=y
 CONFIG_BT_CTLR_ADV_ISO=y
+CONFIG_BT_CTLR_ADV_ISO_SEQUENTIAL=y
+CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED=y
 CONFIG_BT_CTLR_ADV_ISO_SET=2
 CONFIG_BT_CTLR_ADV_ISO_STREAM_COUNT=4
 CONFIG_BT_CTLR_ADV_ISO_STREAM_MAX=2
@@ -104,6 +106,8 @@ CONFIG_BT_CTLR_ADV_EXT=y
 CONFIG_BT_CTLR_SYNC_PERIODIC=y
 CONFIG_BT_CTLR_SYNC_TRANSFER_RECEIVER=y
 CONFIG_BT_CTLR_SYNC_ISO=y
+CONFIG_BT_CTLR_SYNC_ISO_SEQUENTIAL=y
+CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED=y
 CONFIG_BT_CTLR_SCAN_SYNC_ISO_SET=1
 CONFIG_BT_CTLR_SYNC_ISO_STREAM_COUNT=2
 CONFIG_BT_CTLR_SYNC_ISO_STREAM_MAX=2
@@ -115,7 +119,6 @@ CONFIG_BT_CTLR_PERIPHERAL_ISO=y
 CONFIG_BT_CTLR_CONN_ISO_STREAMS=2
 CONFIG_BT_CTLR_CONN_ISO_GROUPS=1
 CONFIG_BT_CTLR_CONN_ISO_STREAMS_PER_GROUP=2
-CONFIG_BT_CTLR_CONN_ISO_SDU_LEN_MAX=247
 CONFIG_BT_CTLR_CONN_ISO_PDU_LEN_MAX=251
 CONFIG_BT_CTLR_CONN_ISO_LOW_LATENCY_POLICY=y
 
@@ -123,6 +126,7 @@ CONFIG_BT_CTLR_CONN_ISO_LOW_LATENCY_POLICY=y
 CONFIG_BT_CTLR_ISOAL_SOURCES=4
 CONFIG_BT_CTLR_ISO_TX_BUFFERS=18
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=255
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=247
 
 # ISO Receptions
 CONFIG_BT_CTLR_ISOAL_SINKS=2
diff --git a/samples/bluetooth/hci_uart/prj.conf b/samples/bluetooth/hci_uart/prj.conf
index bb4a25b2886..b5b1a30fee6 100644
--- a/samples/bluetooth/hci_uart/prj.conf
+++ b/samples/bluetooth/hci_uart/prj.conf
@@ -16,7 +16,3 @@ CONFIG_BT_MAX_CONN=16
 CONFIG_BT_CTLR_DTM_HCI=y
 
 CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=512
-
-# Workaround: Unable to allocate command buffer when using K_NO_WAIT since
-# Host number of completed commands does not follow normal flow control.
-CONFIG_BT_BUF_CMD_TX_COUNT=10
diff --git a/samples/bluetooth/hci_uart/src/main.c b/samples/bluetooth/hci_uart/src/main.c
index 626ff56ec70..322291e3739 100644
--- a/samples/bluetooth/hci_uart/src/main.c
+++ b/samples/bluetooth/hci_uart/src/main.c
@@ -54,7 +54,7 @@ static K_FIFO_DEFINE(uart_tx_queue);
 #define ST_DISCARD 3	/* Dropping packet. */
 
 /* Length of a discard/flush buffer.
- * This is sized to align with a BLE HCI packet:
+ * This is sized to align with a Bluetooth HCI packet:
  * 1 byte H:4 header + 32 bytes ACL/event data
  * Bigger values might overflow the stack since this is declared as a local
  * variable, smaller ones will force the caller to call into discard more
diff --git a/samples/bluetooth/hci_uart_3wire/README.rst b/samples/bluetooth/hci_uart_3wire/README.rst
index ccf412b031d..b846c9892fd 100644
--- a/samples/bluetooth/hci_uart_3wire/README.rst
+++ b/samples/bluetooth/hci_uart_3wire/README.rst
@@ -33,11 +33,11 @@ Zephyr tree, and it is built as a standard Zephyr application.
 Using the controller with emulators and BlueZ
 *********************************************
 
-The instructions below show how to use a Nordic nRF5x device as a Zephyr BLE
+The instructions below show how to use a Nordic nRF5x device as a Zephyr Bluetooth
 controller and expose it to Linux's BlueZ. This can be very useful for testing
 the Zephyr Link Layer with the BlueZ Host. The Zephyr Bluetooth LE controller can also
 provide a modern Bluetooth LE 5.0 controller to a Linux-based machine for native
-BLE support or QEMU-based development.
+Bluetooth support or QEMU-based development.
 
 First, make sure you have a recent BlueZ version installed by following the
 instructions in the :ref:`bluetooth_bluez` section.
diff --git a/samples/bluetooth/hci_uart_3wire/overlay-all-bt_ll_sw_split.conf b/samples/bluetooth/hci_uart_3wire/overlay-all-bt_ll_sw_split.conf
index 8a0f9d3364a..72dd6caa609 100644
--- a/samples/bluetooth/hci_uart_3wire/overlay-all-bt_ll_sw_split.conf
+++ b/samples/bluetooth/hci_uart_3wire/overlay-all-bt_ll_sw_split.conf
@@ -93,6 +93,8 @@ CONFIG_BT_CTLR_ADV_EXT=y
 CONFIG_BT_CTLR_ADV_PERIODIC=y
 CONFIG_BT_CTLR_SYNC_TRANSFER_SENDER=y
 CONFIG_BT_CTLR_ADV_ISO=y
+CONFIG_BT_CTLR_ADV_ISO_SEQUENTIAL=y
+CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED=y
 CONFIG_BT_CTLR_ADV_ISO_SET=2
 CONFIG_BT_CTLR_ADV_ISO_STREAM_COUNT=4
 CONFIG_BT_CTLR_ADV_ISO_STREAM_MAX=2
@@ -103,6 +105,8 @@ CONFIG_BT_CTLR_ADV_EXT=y
 CONFIG_BT_CTLR_SYNC_PERIODIC=y
 CONFIG_BT_CTLR_SYNC_TRANSFER_RECEIVER=y
 CONFIG_BT_CTLR_SYNC_ISO=y
+CONFIG_BT_CTLR_SYNC_ISO_SEQUENTIAL=y
+CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED=y
 CONFIG_BT_CTLR_SCAN_SYNC_ISO_SET=1
 CONFIG_BT_CTLR_SYNC_ISO_STREAM_COUNT=2
 CONFIG_BT_CTLR_SYNC_ISO_STREAM_MAX=2
@@ -114,7 +118,6 @@ CONFIG_BT_CTLR_PERIPHERAL_ISO=y
 CONFIG_BT_CTLR_CONN_ISO_STREAMS=2
 CONFIG_BT_CTLR_CONN_ISO_GROUPS=1
 CONFIG_BT_CTLR_CONN_ISO_STREAMS_PER_GROUP=2
-CONFIG_BT_CTLR_CONN_ISO_SDU_LEN_MAX=247
 CONFIG_BT_CTLR_CONN_ISO_PDU_LEN_MAX=251
 CONFIG_BT_CTLR_CONN_ISO_LOW_LATENCY_POLICY=y
 
@@ -122,6 +125,7 @@ CONFIG_BT_CTLR_CONN_ISO_LOW_LATENCY_POLICY=y
 CONFIG_BT_CTLR_ISOAL_SOURCES=4
 CONFIG_BT_CTLR_ISO_TX_BUFFERS=18
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=255
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=247
 
 # ISO Receptions
 CONFIG_BT_CTLR_ISOAL_SINKS=2
diff --git a/samples/bluetooth/hci_uart_3wire/prj.conf b/samples/bluetooth/hci_uart_3wire/prj.conf
index d9a03554f9f..b8fb9fef61f 100644
--- a/samples/bluetooth/hci_uart_3wire/prj.conf
+++ b/samples/bluetooth/hci_uart_3wire/prj.conf
@@ -15,7 +15,3 @@ CONFIG_BT_MAX_CONN=16
 CONFIG_BT_CTLR_DTM_HCI=y
 
 CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=512
-
-# Workaround: Unable to allocate command buffer when using K_NO_WAIT since
-# Host number of completed commands does not follow normal flow control.
-CONFIG_BT_BUF_CMD_TX_COUNT=10
diff --git a/samples/bluetooth/hci_uart_async/README.rst b/samples/bluetooth/hci_uart_async/README.rst
index ce1a369b2fc..77877416833 100644
--- a/samples/bluetooth/hci_uart_async/README.rst
+++ b/samples/bluetooth/hci_uart_async/README.rst
@@ -36,7 +36,7 @@ in the Zephyr tree and is built as a standard Zephyr application.
 Using the controller with emulators and BlueZ
 *********************************************
 
-The instructions below show how to use a Nordic nRF5x device as a Zephyr BLE
+The instructions below show how to use a Nordic nRF5x device as a Zephyr Bluetooth
 controller and expose it to Linux's BlueZ.
 
 First, make sure you have a recent BlueZ version installed by following the
diff --git a/samples/bluetooth/hci_usb/README.rst b/samples/bluetooth/hci_usb/README.rst
index c8ac294a72f..c87dbb0e013 100644
--- a/samples/bluetooth/hci_usb/README.rst
+++ b/samples/bluetooth/hci_usb/README.rst
@@ -8,7 +8,7 @@ Overview
 ********
 
 Make a USB Bluetooth dongle out of Zephyr. Requires USB device support from the
-board it runs on (e.g. :ref:`nrf52840dk_nrf52840` supports both Bluetooth LE and USB).
+board it runs on (e.g. :zephyr:board:`nrf52840dk` supports both Bluetooth LE and USB).
 
 Requirements
 ************
diff --git a/samples/bluetooth/hci_usb/prj.conf b/samples/bluetooth/hci_usb/prj.conf
index 0f809e424d6..7f0a2d9fe6a 100644
--- a/samples/bluetooth/hci_usb/prj.conf
+++ b/samples/bluetooth/hci_usb/prj.conf
@@ -11,7 +11,3 @@ CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n
 CONFIG_SERIAL=n
 CONFIG_CONSOLE=n
 CONFIG_UART_CONSOLE=n
-
-# Workaround: Unable to allocate command buffer when using K_NO_WAIT since
-# Host number of completed commands does not follow normal flow control.
-CONFIG_BT_BUF_CMD_TX_COUNT=10
diff --git a/samples/bluetooth/iso_broadcast/Kconfig b/samples/bluetooth/iso_broadcast/Kconfig
index 21df24566f6..0183fa782c8 100644
--- a/samples/bluetooth/iso_broadcast/Kconfig
+++ b/samples/bluetooth/iso_broadcast/Kconfig
@@ -1,13 +1,18 @@
 # Copyright (c) 2023 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
-source "Kconfig.zephyr"
-
 mainmenu "Bluetooth: ISO Broadcast"
 
+config ISO_PACKING_INTERLEAVED
+	bool "Use interleaved packing"
+	help
+	  Use interleaved packing between BIS ISO stream subevents.
+
 config ISO_PRINT_INTERVAL
 	int "Interval between each packet report"
 	range 1 360000
 	default 1
 	help
 	  Only print the packet report once in a given interval of ISO packets.
+
+source "Kconfig.zephyr"
diff --git a/samples/bluetooth/iso_broadcast/README.rst b/samples/bluetooth/iso_broadcast/README.rst
index 79eae0e3a7d..3662230ca2b 100644
--- a/samples/bluetooth/iso_broadcast/README.rst
+++ b/samples/bluetooth/iso_broadcast/README.rst
@@ -24,6 +24,8 @@ Building and Running
 This sample can be found under :zephyr_file:`samples/bluetooth/iso_broadcast` in
 the Zephyr tree. Use ``-DEXTRA_CONF_FILE=overlay-bt_ll_sw_split.conf`` to enable
 required ISO feature support in Zephyr Bluetooth Controller on supported boards.
+The sample defaults to sequential packing of BIS subevents, add
+``-DCONFIG_ISO_PACKING_INTERLEAVED=y`` to use interleaved packing.
 
 Use the sample found under :zephyr_file:`samples/bluetooth/iso_receive` in the
 Zephyr tree that will scan, establish a periodic advertising synchronization,
diff --git a/samples/bluetooth/iso_broadcast/overlay-bt_ll_sw_split.conf b/samples/bluetooth/iso_broadcast/overlay-bt_ll_sw_split.conf
index 19264a9d041..0f8fa6c128c 100644
--- a/samples/bluetooth/iso_broadcast/overlay-bt_ll_sw_split.conf
+++ b/samples/bluetooth/iso_broadcast/overlay-bt_ll_sw_split.conf
@@ -6,6 +6,8 @@ CONFIG_BT_CTLR_ADV_DATA_LEN_MAX=191
 
 # Enable support for Broadcast ISO in Zephyr Bluetooth Controller
 CONFIG_BT_CTLR_ADV_ISO=y
+CONFIG_BT_CTLR_ADV_ISO_SEQUENTIAL=y
+CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED=y
 
 # Sufficient ISO PDU length for this sample
 CONFIG_BT_CTLR_ADV_ISO_PDU_LEN_MAX=4
@@ -14,7 +16,6 @@ CONFIG_BT_CTLR_ADV_ISO_PDU_LEN_MAX=4
 CONFIG_BT_CTLR_ADV_ISO_STREAM_MAX=2
 CONFIG_BT_CTLR_ISOAL_SOURCES=2
 
-# Support the highest SDU size required by any BAP LC3 presets (155) + 8 bytes of HCI ISO Data
-# packet overhead (the Packet_Sequence_Number, ISO_SDU_Length, Packet_Status_Flag fields; and
-# the optional Time_Stamp field, if supplied)
+# Support the highest SDU size required by this sample
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=12
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=4
diff --git a/samples/bluetooth/iso_broadcast/prj.conf b/samples/bluetooth/iso_broadcast/prj.conf
index 8a9a5f19691..d6d4c9936ce 100644
--- a/samples/bluetooth/iso_broadcast/prj.conf
+++ b/samples/bluetooth/iso_broadcast/prj.conf
@@ -6,5 +6,9 @@ CONFIG_BT_DEVICE_NAME="Test ISO Broadcaster"
 CONFIG_BT_ISO_MAX_CHAN=2
 CONFIG_BT_ISO_TX_BUF_COUNT=4
 
+# This sample defaults to sequential packing.
+# Uncomment below to use Broadcast ISO interleaved packing.
+# CONFIG_ISO_PACKING_INTERLEAVED=y
+
 # Just needs to send a uint32_t value
 CONFIG_BT_ISO_TX_MTU=4
diff --git a/samples/bluetooth/iso_broadcast/src/main.c b/samples/bluetooth/iso_broadcast/src/main.c
index da06a9c417d..5f7296b28db 100644
--- a/samples/bluetooth/iso_broadcast/src/main.c
+++ b/samples/bluetooth/iso_broadcast/src/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2024 Nordic Semiconductor ASA
+ * Copyright (c) 2021-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,6 +8,7 @@
 
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/iso.h>
 #include <zephyr/sys/byteorder.h>
 
@@ -31,10 +32,21 @@ static uint16_t seq_num;
 
 static void iso_connected(struct bt_iso_chan *chan)
 {
+	const struct bt_iso_chan_path hci_path = {
+		.pid = BT_ISO_DATA_PATH_HCI,
+		.format = BT_HCI_CODING_FORMAT_TRANSPARENT,
+	};
+	int err;
+
 	printk("ISO Channel %p connected\n", chan);
 
 	seq_num = 0U;
 
+	err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR, &hci_path);
+	if (err != 0) {
+		printk("Failed to setup ISO TX data path: %d\n", err);
+	}
+
 	k_sem_give(&sem_big_cmplt);
 }
 
@@ -81,7 +93,9 @@ static struct bt_iso_big_create_param big_create_param = {
 	.bis_channels = bis,
 	.interval = BIG_SDU_INTERVAL_US, /* in microseconds */
 	.latency = 10, /* in milliseconds */
-	.packing = 0, /* 0 - sequential, 1 - interleaved */
+	.packing = (IS_ENABLED(CONFIG_ISO_PACKING_INTERLEAVED) ?
+		    BT_ISO_PACKING_INTERLEAVED :
+		    BT_ISO_PACKING_SEQUENTIAL),
 	.framing = 0, /* 0 - unframed, 1 - framed */
 };
 
diff --git a/samples/bluetooth/iso_broadcast_benchmark/sample.yaml b/samples/bluetooth/iso_broadcast_benchmark/sample.yaml
index d9804ac7029..cb8b5d76e20 100644
--- a/samples/bluetooth/iso_broadcast_benchmark/sample.yaml
+++ b/samples/bluetooth/iso_broadcast_benchmark/sample.yaml
@@ -1,5 +1,5 @@
 sample:
-  name: BLE ISO Broadcast
+  name: Bluetooth LE ISO Broadcast
   description: Bluetooth Low Energy ISO Broadcast Benchmark sample
 tests:
   sample.bluetooth.iso_broadcast_benchmark:
diff --git a/samples/bluetooth/iso_broadcast_benchmark/src/broadcaster.c b/samples/bluetooth/iso_broadcast_benchmark/src/broadcaster.c
index 4665eed3ca8..3f12619ed81 100644
--- a/samples/bluetooth/iso_broadcast_benchmark/src/broadcaster.c
+++ b/samples/bluetooth/iso_broadcast_benchmark/src/broadcaster.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2024 Nordic Semiconductor ASA
+ * Copyright (c) 2021-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,6 +9,7 @@
 #include <stdint.h>
 
 #include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/console/console.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/iso.h>
@@ -72,8 +73,19 @@ static const struct bt_data ad[] = {
 
 static void iso_connected(struct bt_iso_chan *chan)
 {
+	const struct bt_iso_chan_path hci_path = {
+		.pid = BT_ISO_DATA_PATH_HCI,
+		.format = BT_HCI_CODING_FORMAT_TRANSPARENT,
+	};
+	int err;
+
 	LOG_INF("ISO Channel %p connected", chan);
 
+	err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR, &hci_path);
+	if (err != 0) {
+		printk("Failed to setup ISO TX data path: %d\n", err);
+	}
+
 	connected_bis++;
 	if (connected_bis == big_create_param.num_bis) {
 		seq_num = 0U;
diff --git a/samples/bluetooth/iso_broadcast_benchmark/src/receiver.c b/samples/bluetooth/iso_broadcast_benchmark/src/receiver.c
index af684cecc52..45efaf66a4b 100644
--- a/samples/bluetooth/iso_broadcast_benchmark/src/receiver.c
+++ b/samples/bluetooth/iso_broadcast_benchmark/src/receiver.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 Nordic Semiconductor ASA
+ * Copyright (c) 2021-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,6 +7,7 @@
 #include <ctype.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/iso.h>
 #include <zephyr/sys/byteorder.h>
 #include <zephyr/console/console.h>
@@ -229,10 +230,21 @@ static void iso_recv(struct bt_iso_chan *chan,
 
 static void iso_connected(struct bt_iso_chan *chan)
 {
+	const struct bt_iso_chan_path hci_path = {
+		.pid = BT_ISO_DATA_PATH_HCI,
+		.format = BT_HCI_CODING_FORMAT_TRANSPARENT,
+	};
+	int err;
+
 	LOG_INF("ISO Channel %p connected", chan);
 
 	big_sync_start_time = k_uptime_get();
 
+	err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_CTLR_TO_HOST, &hci_path);
+	if (err != 0) {
+		printk("Failed to setup ISO RX data path: %d\n", err);
+	}
+
 	k_sem_give(&sem_big_sync);
 }
 
diff --git a/samples/bluetooth/iso_central/overlay-bt_ll_sw_split.conf b/samples/bluetooth/iso_central/overlay-bt_ll_sw_split.conf
index 320c5c352b1..2c91650470d 100644
--- a/samples/bluetooth/iso_central/overlay-bt_ll_sw_split.conf
+++ b/samples/bluetooth/iso_central/overlay-bt_ll_sw_split.conf
@@ -13,7 +13,7 @@ CONFIG_BT_CTLR_SCAN_DATA_LEN_MAX=1650
 CONFIG_BT_CTLR_RX_BUFFERS=9
 
 # Sufficient ISO SDU and PDU length for this sample with ISO_TX_MTU of 247
-CONFIG_BT_CTLR_CONN_ISO_SDU_LEN_MAX=247
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=247
 CONFIG_BT_CTLR_CONN_ISO_PDU_LEN_MAX=251
 
 # Number of supported streami sources and sinks
diff --git a/samples/bluetooth/iso_central/src/main.c b/samples/bluetooth/iso_central/src/main.c
index a9352363714..24b2f0d0668 100644
--- a/samples/bluetooth/iso_central/src/main.c
+++ b/samples/bluetooth/iso_central/src/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021-2024 Nordic Semiconductor ASA
+ * Copyright (c) 2021-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,6 +16,7 @@
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/uuid.h>
 #include <zephyr/bluetooth/gatt.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/iso.h>
 #include <zephyr/settings/settings.h>
 #include <zephyr/sys/byteorder.h>
@@ -142,18 +143,36 @@ static void start_scan(void)
 
 static void iso_connected(struct bt_iso_chan *chan)
 {
+	const struct bt_iso_chan_path hci_path = {
+		.pid = BT_ISO_DATA_PATH_HCI,
+		.format = BT_HCI_CODING_FORMAT_TRANSPARENT,
+	};
+	int err;
+
 	printk("ISO Channel %p connected\n", chan);
 
 	seq_num = 0U;
 
-	/* Start send timer */
-	k_work_schedule(&iso_send_work, K_MSEC(0));
+	err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR, &hci_path);
+	if (err != 0) {
+		printk("Failed to setup ISO TX data path: %d\n", err);
+	} else {
+		/* Start send timer */
+		k_work_schedule(&iso_send_work, K_NO_WAIT);
+	}
 }
 
 static void iso_disconnected(struct bt_iso_chan *chan, uint8_t reason)
 {
+	int err;
+
 	printk("ISO Channel %p disconnected (reason 0x%02x)\n", chan, reason);
 	k_work_cancel_delayable(&iso_send_work);
+
+	err = bt_iso_remove_data_path(chan, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR);
+	if (err != 0) {
+		printk("Failed to setup ISO TX data path: %d\n", err);
+	}
 }
 
 static struct bt_iso_chan_ops iso_ops = {
@@ -165,7 +184,6 @@ static struct bt_iso_chan_io_qos iso_tx = {
 	.sdu = CONFIG_BT_ISO_TX_MTU,
 	.phy = BT_GAP_LE_PHY_2M,
 	.rtn = 1,
-	.path = NULL,
 };
 
 static struct bt_iso_chan_qos iso_qos = {
diff --git a/samples/bluetooth/iso_connected_benchmark/sample.yaml b/samples/bluetooth/iso_connected_benchmark/sample.yaml
index fd4eb7d9615..c2a82196e19 100644
--- a/samples/bluetooth/iso_connected_benchmark/sample.yaml
+++ b/samples/bluetooth/iso_connected_benchmark/sample.yaml
@@ -1,5 +1,5 @@
 sample:
-  name: BLE ISO Connected
+  name: Bluetooth LE ISO Connected
   description: Bluetooth Low Energy ISO Connected Benchmark sample
 tests:
   sample.bluetooth.iso_connected_benchmark:
diff --git a/samples/bluetooth/iso_connected_benchmark/src/main.c b/samples/bluetooth/iso_connected_benchmark/src/main.c
index 1933033f844..c6c807125ad 100644
--- a/samples/bluetooth/iso_connected_benchmark/src/main.c
+++ b/samples/bluetooth/iso_connected_benchmark/src/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 Nordic Semiconductor ASA
+ * Copyright (c) 2021-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,6 +7,7 @@
 #include <ctype.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/kernel.h>
 #include <string.h>
 #include <stdint.h>
@@ -306,7 +307,12 @@ static void iso_recv(struct bt_iso_chan *chan,
 
 static void iso_connected(struct bt_iso_chan *chan)
 {
+	const struct bt_iso_chan_path hci_path = {
+		.pid = BT_ISO_DATA_PATH_HCI,
+		.format = BT_HCI_CODING_FORMAT_TRANSPARENT,
+	};
 	struct iso_chan_work *chan_work;
+	struct bt_iso_info iso_info;
 	int err;
 
 	LOG_INF("ISO Channel %p connected", chan);
@@ -325,6 +331,20 @@ static void iso_connected(struct bt_iso_chan *chan)
 	chan_work = CONTAINER_OF(chan, struct iso_chan_work, chan);
 	chan_work->seq_num = 0U;
 
+	if (iso_info.can_recv) {
+		err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_CTLR_TO_HOST, &hci_path);
+		if (err != 0) {
+			LOG_ERR("Failed to setup ISO RX data path: %d", err);
+		}
+	}
+
+	if (iso_info.can_send) {
+		err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR, &hci_path);
+		if (err != 0) {
+			LOG_ERR("Failed to setup ISO TX data path: %d", err);
+		}
+	}
+
 	k_sem_give(&sem_iso_connected);
 }
 
@@ -337,8 +357,10 @@ static void iso_disconnected(struct bt_iso_chan *chan, uint8_t reason)
 	 * of the last created CIS.
 	 */
 	static int64_t average_duration;
+	struct bt_iso_info iso_info;
 	uint64_t iso_conn_duration;
 	uint64_t total_duration;
+	int err;
 
 	if (iso_conn_start_time > 0) {
 		iso_conn_duration = k_uptime_get() - iso_conn_start_time;
@@ -354,6 +376,25 @@ static void iso_disconnected(struct bt_iso_chan *chan, uint8_t reason)
 		chan, reason, iso_conn_duration, average_duration);
 
 	k_sem_give(&sem_iso_disconnected);
+
+	err = bt_iso_chan_get_info(chan, &iso_info);
+	if (err != 0) {
+		LOG_ERR("Failed to get ISO info: %d\n", err);
+	} else if (iso_info.type == BT_ISO_CHAN_TYPE_CENTRAL) {
+		if (iso_info.can_recv) {
+			err = bt_iso_remove_data_path(chan, BT_HCI_DATAPATH_DIR_CTLR_TO_HOST);
+			if (err != 0) {
+				LOG_ERR("Failed to remove ISO RX data path: %d\n", err);
+			}
+		}
+
+		if (iso_info.can_send) {
+			err = bt_iso_remove_data_path(chan, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR);
+			if (err != 0) {
+				LOG_ERR("Failed to remove ISO TX data path: %d\n", err);
+			}
+		}
+	}
 }
 
 static struct bt_iso_chan_ops iso_ops = {
diff --git a/samples/bluetooth/iso_peripheral/src/main.c b/samples/bluetooth/iso_peripheral/src/main.c
index d11baa9633f..47d69595b5e 100644
--- a/samples/bluetooth/iso_peripheral/src/main.c
+++ b/samples/bluetooth/iso_peripheral/src/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 Nordic Semiconductor ASA
+ * Copyright (c) 2021-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,6 +15,7 @@
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/hci.h>
 #include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/iso.h>
 #include <zephyr/settings/settings.h>
 
@@ -104,7 +105,18 @@ static void iso_recv(struct bt_iso_chan *chan, const struct bt_iso_recv_info *in
 
 static void iso_connected(struct bt_iso_chan *chan)
 {
+	const struct bt_iso_chan_path hci_path = {
+		.pid = BT_ISO_DATA_PATH_HCI,
+		.format = BT_HCI_CODING_FORMAT_TRANSPARENT,
+	};
+	int err;
+
 	printk("ISO Channel %p connected\n", chan);
+
+	err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_CTLR_TO_HOST, &hci_path);
+	if (err != 0) {
+		printk("Failed to setup ISO RX data path: %d", err);
+	}
 }
 
 static void iso_disconnected(struct bt_iso_chan *chan, uint8_t reason)
@@ -120,7 +132,6 @@ static struct bt_iso_chan_ops iso_ops = {
 
 static struct bt_iso_chan_io_qos iso_rx = {
 	.sdu = CONFIG_BT_ISO_TX_MTU,
-	.path = NULL,
 };
 
 static struct bt_iso_chan_qos iso_qos = {
diff --git a/samples/bluetooth/iso_receive/src/main.c b/samples/bluetooth/iso_receive/src/main.c
index e51bbe6d34b..81f2b80da66 100644
--- a/samples/bluetooth/iso_receive/src/main.c
+++ b/samples/bluetooth/iso_receive/src/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 Nordic Semiconductor ASA
+ * Copyright (c) 2021-2024 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,6 +9,7 @@
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/iso.h>
 #include <zephyr/sys/byteorder.h>
 
@@ -233,7 +234,19 @@ static void iso_recv(struct bt_iso_chan *chan, const struct bt_iso_recv_info *in
 
 static void iso_connected(struct bt_iso_chan *chan)
 {
+	const struct bt_iso_chan_path hci_path = {
+		.pid = BT_ISO_DATA_PATH_HCI,
+		.format = BT_HCI_CODING_FORMAT_TRANSPARENT,
+	};
+	int err;
+
 	printk("ISO Channel %p connected\n", chan);
+
+	err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_CTLR_TO_HOST, &hci_path);
+	if (err != 0) {
+		printk("Failed to setup ISO RX data path: %d\n", err);
+	}
+
 	k_sem_give(&sem_big_sync);
 }
 
diff --git a/samples/bluetooth/mesh/README.rst b/samples/bluetooth/mesh/README.rst
index f566c071ad2..0d131a864be 100644
--- a/samples/bluetooth/mesh/README.rst
+++ b/samples/bluetooth/mesh/README.rst
@@ -2,7 +2,7 @@
    :name: Mesh
    :relevant-api: bt_mesh bluetooth
 
-   Use basic Bluetooth LE Mesh functionality.
+   Use basic Bluetooth Mesh functionality.
 
 Overview
 ********
@@ -45,7 +45,7 @@ For other boards, build and flash the application as follows:
 Refer to your :ref:`board's documentation <boards>` for alternative
 flash instructions if your board doesn't support the ``flash`` target.
 
-To run the application on an :ref:`nrf5340dk_nrf5340`, a Bluetooth controller application
+To run the application on an :zephyr:board:`nrf5340dk`, a Bluetooth controller application
 must also run on the network core. The :zephyr:code-sample:`bluetooth_hci_ipc` sample
 application may be used. Build this sample with configuration
 :zephyr_file:`samples/bluetooth/hci_ipc/nrf5340_cpunet_bt_mesh-bt_ll_sw_split.conf`
diff --git a/samples/bluetooth/mesh/boards/bbc_microbit.conf b/samples/bluetooth/mesh/boards/bbc_microbit.conf
index 053053e7818..d71bc9400ae 100644
--- a/samples/bluetooth/mesh/boards/bbc_microbit.conf
+++ b/samples/bluetooth/mesh/boards/bbc_microbit.conf
@@ -13,9 +13,11 @@ CONFIG_BT_PERIPHERAL=n
 CONFIG_BT_EXT_ADV=n
 CONFIG_BT_RX_STACK_SIZE=1100
 CONFIG_BT_BUF_EVT_RX_COUNT=3
-CONFIG_BT_BUF_ACL_RX_COUNT_EXTRA=1
 CONFIG_BT_BUF_EVT_DISCARDABLE_COUNT=3
 
+# CONFIG_BT_BUF_ACL_TX_COUNT has to be less than CONFIG_BT_BUF_EVT_RX_COUNT
+CONFIG_BT_BUF_ACL_TX_COUNT=1
+
 CONFIG_BT_CTLR_ADV_EXT=n
 
 CONFIG_BT_MESH_ADV_BUF_COUNT=3
diff --git a/samples/bluetooth/mesh_demo/README.rst b/samples/bluetooth/mesh_demo/README.rst
index 070dd5a45a4..44be6e90782 100644
--- a/samples/bluetooth/mesh_demo/README.rst
+++ b/samples/bluetooth/mesh_demo/README.rst
@@ -56,7 +56,7 @@ For other boards, build and flash the application as follows:
 Refer to your :ref:`board's documentation <boards>` for alternative
 flash instructions if your board doesn't support the ``flash`` target.
 
-To run the application on an :ref:`nrf5340dk_nrf5340`, a Bluetooth controller application
+To run the application on an :zephyr:board:`nrf5340dk`, a Bluetooth controller application
 must also run on the network core. The :zephyr:code-sample:`bluetooth_hci_ipc` sample
 application may be used. Build this sample with configuration
 :zephyr_file:`samples/bluetooth/hci_ipc/nrf5340_cpunet_bt_mesh-bt_ll_sw_split.conf`
diff --git a/samples/bluetooth/mesh_provisioner/README.rst b/samples/bluetooth/mesh_provisioner/README.rst
index 10600ef89f3..db693735d6d 100644
--- a/samples/bluetooth/mesh_provisioner/README.rst
+++ b/samples/bluetooth/mesh_provisioner/README.rst
@@ -54,7 +54,7 @@ For other boards, build and flash the application as follows:
 Refer to your :ref:`board's documentation <boards>` for alternative
 flash instructions if your board doesn't support the ``flash`` target.
 
-To run the application on an :ref:`nrf5340dk_nrf5340`, a Bluetooth controller application
+To run the application on an :zephyr:board:`nrf5340dk`, a Bluetooth controller application
 must also run on the network core. The :zephyr:code-sample:`bluetooth_hci_ipc` sample
 application may be used. Build this sample with configuration
 :zephyr_file:`samples/bluetooth/hci_ipc/nrf5340_cpunet_bt_mesh-bt_ll_sw_split.conf`
diff --git a/samples/bluetooth/mtu_update/peripheral/src/peripheral_mtu_update.c b/samples/bluetooth/mtu_update/peripheral/src/peripheral_mtu_update.c
index a5bbef6f5ee..44ac61ac33e 100644
--- a/samples/bluetooth/mtu_update/peripheral/src/peripheral_mtu_update.c
+++ b/samples/bluetooth/mtu_update/peripheral/src/peripheral_mtu_update.c
@@ -97,8 +97,10 @@ void run_peripheral_sample(uint8_t *notify_data, size_t notify_data_size, uint16
 
 	for (int i = 0; (i < seconds) || infinite; i++) {
 		k_sleep(K_SECONDS(1));
+		if (default_conn == NULL) {
+			printk("Skipping notification since connection is not yet established\n");
 		/* Only send the notification if the UATT MTU supports the required length */
-		if (bt_gatt_get_uatt_mtu(default_conn) >= ATT_NTF_SIZE(notify_data_size)) {
+		} else if (bt_gatt_get_uatt_mtu(default_conn) >= ATT_NTF_SIZE(notify_data_size)) {
 			bt_gatt_notify(default_conn, notify_crch, notify_data, notify_data_size);
 		} else {
 			printk("Skipping notification since UATT MTU is not sufficient."
diff --git a/samples/bluetooth/pbp_public_broadcast_sink/prj.conf b/samples/bluetooth/pbp_public_broadcast_sink/prj.conf
index 1cc458a4798..b2054ce9be3 100644
--- a/samples/bluetooth/pbp_public_broadcast_sink/prj.conf
+++ b/samples/bluetooth/pbp_public_broadcast_sink/prj.conf
@@ -10,7 +10,6 @@ CONFIG_UTF8=y
 CONFIG_BT_SMP=y
 CONFIG_BT_KEYS_OVERWRITE_OLDEST=y
 CONFIG_BT_L2CAP_TX_BUF_COUNT=20
-CONFIG_BT_HCI_ACL_FLOW_CONTROL=n
 CONFIG_BT_AUDIO_CODEC_CAP_MAX_METADATA_SIZE=196
 
 # CAP
diff --git a/samples/bluetooth/pbp_public_broadcast_source/overlay-bt_ll_sw_split.conf b/samples/bluetooth/pbp_public_broadcast_source/overlay-bt_ll_sw_split.conf
index 3711a349213..4e873d42cb2 100644
--- a/samples/bluetooth/pbp_public_broadcast_source/overlay-bt_ll_sw_split.conf
+++ b/samples/bluetooth/pbp_public_broadcast_source/overlay-bt_ll_sw_split.conf
@@ -6,6 +6,8 @@ CONFIG_BT_CTLR_ADV_DATA_LEN_MAX=191
 
 # Enable support for Broadcast ISO in Zephyr Bluetooth Controller
 CONFIG_BT_CTLR_ADV_ISO=y
+CONFIG_BT_CTLR_ADV_ISO_SEQUENTIAL=y
+CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED=y
 
 # Sufficient ISO PDU length for any BAP LC3 presets (155)
 CONFIG_BT_CTLR_ADV_ISO_PDU_LEN_MAX=155
@@ -18,3 +20,4 @@ CONFIG_BT_CTLR_ISOAL_SOURCES=2
 # packet overhead (the Packet_Sequence_Number, ISO_SDU_Length, Packet_Status_Flag fields; and
 # the optional Time_Stamp field, if supplied)
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=163
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=155
diff --git a/samples/bluetooth/pbp_public_broadcast_source/prj.conf b/samples/bluetooth/pbp_public_broadcast_source/prj.conf
index 004e1832b64..d7d6e9fe667 100644
--- a/samples/bluetooth/pbp_public_broadcast_source/prj.conf
+++ b/samples/bluetooth/pbp_public_broadcast_source/prj.conf
@@ -10,7 +10,6 @@ CONFIG_BT_ISO_MAX_CHAN=2
 CONFIG_BT_BAP_BROADCAST_SRC_STREAM_COUNT=2
 CONFIG_BT_BAP_BROADCAST_SRC_SUBGROUP_COUNT=2
 CONFIG_BT_ISO_TX_BUF_COUNT=4
-CONFIG_BT_HCI_ACL_FLOW_CONTROL=n
 
 # PBP support
 CONFIG_BT_PBP=y
diff --git a/samples/bluetooth/pbp_public_broadcast_source/src/main.c b/samples/bluetooth/pbp_public_broadcast_source/src/main.c
index 00e12d95b9d..2f97db69220 100644
--- a/samples/bluetooth/pbp_public_broadcast_source/src/main.c
+++ b/samples/bluetooth/pbp_public_broadcast_source/src/main.c
@@ -16,6 +16,7 @@
 #include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/audio/pbp.h>
 #include <zephyr/bluetooth/byteorder.h>
+#include <zephyr/bluetooth/crypto.h>
 #include <zephyr/bluetooth/gap.h>
 #include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/iso.h>
diff --git a/samples/bluetooth/periodic_adv_conn/README.rst b/samples/bluetooth/periodic_adv_conn/README.rst
index 7ae2095c78b..0676bc16fe0 100644
--- a/samples/bluetooth/periodic_adv_conn/README.rst
+++ b/samples/bluetooth/periodic_adv_conn/README.rst
@@ -7,7 +7,7 @@
 Overview
 ********
 
-A simple application demonstrating the initiator side of the BLE
+A simple application demonstrating the initiator side of the Bluetooth LE
 Periodic Advertising Connection Procedure.
 
 How the initiator decides the address of the synced device to connect to
diff --git a/samples/bluetooth/periodic_sync_conn/README.rst b/samples/bluetooth/periodic_sync_conn/README.rst
index 1ec8aec3d25..24c9ee5f527 100644
--- a/samples/bluetooth/periodic_sync_conn/README.rst
+++ b/samples/bluetooth/periodic_sync_conn/README.rst
@@ -7,7 +7,7 @@
 Overview
 ********
 
-A simple application demonstrating the responder side of the BLE
+A simple application demonstrating the responder side of the Bluetooth LE
 Periodic Advertising Connection Procedure.
 
 This sample will send its address in response to the advertiser when receiving
diff --git a/samples/bluetooth/peripheral/sample.yaml b/samples/bluetooth/peripheral/sample.yaml
index e1c05c7967c..aca027dfc1d 100644
--- a/samples/bluetooth/peripheral/sample.yaml
+++ b/samples/bluetooth/peripheral/sample.yaml
@@ -1,6 +1,6 @@
 sample:
   name: Bluetooth Peripheral
-  description: Demonstrates the BLE Peripheral role
+  description: Demonstrates the Bluetooth LE Peripheral role
 tests:
   sample.bluetooth.peripheral:
     harness: bluetooth
@@ -29,4 +29,5 @@ tests:
       - sltb010a/efr32bg22c224f512im40
       - xg24_rb4187c/efr32mg24b220f1536im48
       - xg27_dk2602a/efr32bg27c140f768im40
+      - xg29_rb4412a/efr32mg29b140f1024im40
     build_only: true
diff --git a/samples/bluetooth/peripheral_accept_list/README.rst b/samples/bluetooth/peripheral_accept_list/README.rst
index 4f405561466..cce075d5594 100644
--- a/samples/bluetooth/peripheral_accept_list/README.rst
+++ b/samples/bluetooth/peripheral_accept_list/README.rst
@@ -12,7 +12,7 @@ If no device is bonded to the peripheral, casual advertising will be performed.
 Once a device is bonded, on subsequent boots, connection requests will only be
 accepted if the central device is on the accept list. Additionally, scan response
 data will only be sent to devices that are on the accept list. As a result, some
-BLE central devices (such as Android smartphones) might not display the device
+Bluetooth LE central devices (such as Android smartphones) might not display the device
 in the scan results if the central device is not on the accept list.
 
 This sample also provides two Bluetooth LE characteristics. To perform a write, devices need
diff --git a/samples/bluetooth/peripheral_dis/prj.conf b/samples/bluetooth/peripheral_dis/prj.conf
index cc58337db9c..c6f74dba8c5 100644
--- a/samples/bluetooth/peripheral_dis/prj.conf
+++ b/samples/bluetooth/peripheral_dis/prj.conf
@@ -16,6 +16,25 @@ CONFIG_BT_DIS_FW_REV_STR="Zephyr Firmware"
 CONFIG_BT_DIS_HW_REV_STR="Zephyr Hardware"
 CONFIG_BT_DIS_SW_REV_STR="Zephyr Software"
 
+CONFIG_BT_DIS_UDI=y
+CONFIG_BT_DIS_UDI_LABEL_STR="Zephyr Test UDI Label"
+CONFIG_BT_DIS_UDI_DI_STR="(01)0123456789ABCD(11)241125(17)341125(10)A1234(21)0123456789"
+CONFIG_BT_DIS_UDI_ISSUER_STR="1.3.6.1.4.1.99999"
+CONFIG_BT_DIS_UDI_AUTHORITY_STR="1.3.6.1.4.1.99999"
+
+CONFIG_BT_DIS_PNP=y
+CONFIG_BT_DIS_PNP_VID_SRC=1
+CONFIG_BT_DIS_PNP_VID=0xFFFF
+CONFIG_BT_DIS_PNP_PID=0xFFFF
+CONFIG_BT_DIS_PNP_VER=0
+
+CONFIG_BT_DIS_SYSTEM_ID=y
+CONFIG_BT_DIS_SYSTEM_ID_OUI=0xFFFFFF
+CONFIG_BT_DIS_SYSTEM_ID_IDENTIFIER=0xFFFFFFFFFF
+
+CONFIG_BT_DIS_IEEE_RCDL=y
+CONFIG_BT_DIS_IEEE_RCDL_STR="Zephyr Test IEEE RCDL"
+
 CONFIG_BT_DEVICE_NAME="DIS peripheral"
 
 # Below is setup to let DIS information be read from settings
@@ -25,4 +44,4 @@ CONFIG_SETTINGS=y
 CONFIG_SETTINGS_NONE=y
 
 CONFIG_BT_DIS_SETTINGS=y
-CONFIG_BT_DIS_STR_MAX=21
+CONFIG_BT_DIS_STR_MAX=100
diff --git a/samples/bluetooth/peripheral_dis/sample.yaml b/samples/bluetooth/peripheral_dis/sample.yaml
index 0521956f6e1..7a2bc6ca023 100644
--- a/samples/bluetooth/peripheral_dis/sample.yaml
+++ b/samples/bluetooth/peripheral_dis/sample.yaml
@@ -7,6 +7,7 @@ tests:
     platform_allow:
       - qemu_cortex_m3
       - qemu_x86
+      - ophelia4ev/nrf54l15/cpuapp
     tags: bluetooth
     integration_platforms:
       - qemu_cortex_m3
diff --git a/samples/bluetooth/peripheral_hr/prj_minimal.conf b/samples/bluetooth/peripheral_hr/prj_minimal.conf
index 203ab47808d..5e3f92c91cb 100644
--- a/samples/bluetooth/peripheral_hr/prj_minimal.conf
+++ b/samples/bluetooth/peripheral_hr/prj_minimal.conf
@@ -100,7 +100,7 @@ CONFIG_BT_CTLR_PHY_2M=n
 # Reduce Bluetooth buffers
 CONFIG_BT_BUF_EVT_DISCARDABLE_COUNT=1
 CONFIG_BT_BUF_EVT_DISCARDABLE_SIZE=45
-CONFIG_BT_BUF_EVT_RX_COUNT=2
+CONFIG_BT_BUF_EVT_RX_COUNT=4
 
 CONFIG_BT_L2CAP_TX_BUF_COUNT=2
 CONFIG_BT_CTLR_RX_BUFFERS=1
diff --git a/samples/bluetooth/peripheral_hr/sample.yaml b/samples/bluetooth/peripheral_hr/sample.yaml
index b233fb48abc..8b0722d169f 100644
--- a/samples/bluetooth/peripheral_hr/sample.yaml
+++ b/samples/bluetooth/peripheral_hr/sample.yaml
@@ -14,6 +14,7 @@ tests:
       - nrf52840dk/nrf52840
       - nrf5340dk/nrf5340/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - qemu_cortex_m3
       - nrf52_bsim
@@ -23,6 +24,7 @@ tests:
       - nrf52840dk/nrf52840
       - nrf5340dk/nrf5340/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     tags: bluetooth
   sample.bluetooth.peripheral_hr.minimal:
     harness: bluetooth
diff --git a/samples/bluetooth/peripheral_ht/sample.yaml b/samples/bluetooth/peripheral_ht/sample.yaml
index 826fceb3a56..3316b0fdc81 100644
--- a/samples/bluetooth/peripheral_ht/sample.yaml
+++ b/samples/bluetooth/peripheral_ht/sample.yaml
@@ -17,12 +17,15 @@ tests:
     platform_allow:
       - mimxrt1020_evk
       - mimxrt1050_evk/mimxrt1052/hyperflash
-      - mimxrt1060_evk/mimxrt1062/qspi
+      - mimxrt1060_evk@A/mimxrt1062/qspi
+      - mimxrt1060_evk@B/mimxrt1062/qspi
+      - mimxrt1060_evk@C/mimxrt1062/qspi
       - frdm_k64f
     tags: bluetooth
     extra_args: SHIELD=frdm_kw41z
     integration_platforms:
       - mimxrt1020_evk
+      - mimxrt1060_evk/mimxrt1062/qspi
   sample.bluetooth.peripheral_ht.nxp:
     # Disabling monolithic since CI environment doesn't use blobs
     build_only: true
diff --git a/samples/bluetooth/peripheral_nus/sample.yaml b/samples/bluetooth/peripheral_nus/sample.yaml
index af70193ec1e..0bb22b190e3 100644
--- a/samples/bluetooth/peripheral_nus/sample.yaml
+++ b/samples/bluetooth/peripheral_nus/sample.yaml
@@ -8,6 +8,7 @@ tests:
       - qemu_cortex_m3
       - qemu_x86
       - nrf52840dk/nrf52840
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - qemu_cortex_m3
     tags: bluetooth
diff --git a/samples/bluetooth/peripheral_nus/src/main.c b/samples/bluetooth/peripheral_nus/src/main.c
index dd4d57cf31d..ac987ddfa63 100644
--- a/samples/bluetooth/peripheral_nus/src/main.c
+++ b/samples/bluetooth/peripheral_nus/src/main.c
@@ -29,13 +29,10 @@ static void notif_enabled(bool enabled, void *ctx)
 
 static void received(struct bt_conn *conn, const void *data, uint16_t len, void *ctx)
 {
-	char message[CONFIG_BT_L2CAP_TX_MTU + 1] = "";
-
 	ARG_UNUSED(conn);
 	ARG_UNUSED(ctx);
 
-	memcpy(message, data, MIN(sizeof(message) - 1, len));
-	printk("%s() - Len: %d, Message: %s\n", __func__, len, message);
+	printk("%s() - Len: %d, Message: %.*s\n", __func__, len, len, (char *)data);
 }
 
 struct bt_nus_cb nus_listener = {
diff --git a/samples/bluetooth/peripheral_sc_only/src/main.c b/samples/bluetooth/peripheral_sc_only/src/main.c
index f4ae4252cdc..1a7860851fa 100644
--- a/samples/bluetooth/peripheral_sc_only/src/main.c
+++ b/samples/bluetooth/peripheral_sc_only/src/main.c
@@ -28,6 +28,18 @@ static const struct bt_data sd[] = {
 	BT_DATA(BT_DATA_NAME_COMPLETE, CONFIG_BT_DEVICE_NAME, sizeof(CONFIG_BT_DEVICE_NAME) - 1),
 };
 
+static void start_adv(void)
+{
+	int err;
+
+	err = bt_le_adv_start(BT_LE_ADV_CONN_FAST_1, ad, ARRAY_SIZE(ad), sd, ARRAY_SIZE(sd));
+	if (err) {
+		printk("Advertising failed to start (err %d)\n", err);
+	} else {
+		printk("Advertising successfully started\n");
+	}
+}
+
 static void connected(struct bt_conn *conn, uint8_t err)
 {
 	char addr[BT_ADDR_LE_STR_LEN];
@@ -86,6 +98,7 @@ static void security_changed(struct bt_conn *conn, bt_security_t level,
 BT_CONN_CB_DEFINE(conn_callbacks) = {
 	.connected = connected,
 	.disconnected = disconnected,
+	.recycled = start_adv,
 	.identity_resolved = identity_resolved,
 	.security_changed = security_changed,
 };
@@ -145,12 +158,7 @@ int main(void)
 	bt_conn_auth_cb_register(&auth_cb_display);
 	bt_conn_auth_info_cb_register(&auth_cb_info);
 
-	err = bt_le_adv_start(BT_LE_ADV_CONN_FAST_1, ad, ARRAY_SIZE(ad), sd, ARRAY_SIZE(sd));
-	if (err) {
-		printk("Advertising failed to start (err %d)\n", err);
-		return 0;
-	}
+	start_adv();
 
-	printk("Advertising successfully started\n");
 	return 0;
 }
diff --git a/samples/bluetooth/scan_adv/sample.yaml b/samples/bluetooth/scan_adv/sample.yaml
index 52ec407b0a7..e1e501e93c3 100644
--- a/samples/bluetooth/scan_adv/sample.yaml
+++ b/samples/bluetooth/scan_adv/sample.yaml
@@ -1,6 +1,6 @@
 sample:
   name: Bluetooth Scan & Advertise
-  description: Demonstrates combined BLE Broadcaster & Observer role functionality
+  description: Demonstrates combined Bluetooth LE Broadcaster & Observer role functionality
 tests:
   sample.bluetooth.scan_adv:
     harness: bluetooth
diff --git a/samples/bluetooth/st_ble_sensor/README.rst b/samples/bluetooth/st_ble_sensor/README.rst
index b1cad9d78e8..30d6f2fd1b3 100644
--- a/samples/bluetooth/st_ble_sensor/README.rst
+++ b/samples/bluetooth/st_ble_sensor/README.rst
@@ -2,7 +2,7 @@
    :name: ST Bluetooth LE Sensor Demo
    :relevant-api: bt_gatt bluetooth
 
-   Export vendor-specific GATT services over BLE.
+   Export vendor-specific GATT services over Bluetooth.
 
 Overview
 ********
diff --git a/samples/bluetooth/st_ble_sensor/sample.yaml b/samples/bluetooth/st_ble_sensor/sample.yaml
index 16936ebbc14..d53b4e63c1c 100644
--- a/samples/bluetooth/st_ble_sensor/sample.yaml
+++ b/samples/bluetooth/st_ble_sensor/sample.yaml
@@ -1,6 +1,6 @@
 sample:
-  name: Bluetooth ST BLE Sensor Demo
-  description: Demonstrates BLE peripheral by exposing vendor-specific GATT
+  name: Bluetooth ST Bluetooth LE Sensor Demo
+  description: Demonstrates Bluetooth LE peripheral by exposing vendor-specific GATT
     services
 tests:
   sample.bluetooth.st_ble_sensor:
diff --git a/samples/bluetooth/tmap_bmr/boards/native_posix.conf b/samples/bluetooth/tmap_bmr/boards/native_posix.conf
deleted file mode 100644
index 8ab1d7be113..00000000000
--- a/samples/bluetooth/tmap_bmr/boards/native_posix.conf
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_LOG_MODE_IMMEDIATE=y
-
-CONFIG_LIBLC3=y
-CONFIG_FPU=y
-
-# For LE-audio at 10ms intervals we need the tick counter to occur more frequently
-# than every 10 ms as each PDU for some reason takes 2 ticks to process.
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
-CONFIG_NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME=y
diff --git a/samples/bluetooth/tmap_bmr/src/bap_broadcast_sink.c b/samples/bluetooth/tmap_bmr/src/bap_broadcast_sink.c
index 9c2994f9997..0271645184a 100644
--- a/samples/bluetooth/tmap_bmr/src/bap_broadcast_sink.c
+++ b/samples/bluetooth/tmap_bmr/src/bap_broadcast_sink.c
@@ -313,8 +313,18 @@ static int reset(void)
 
 int bap_broadcast_sink_init(void)
 {
+	const struct bt_pacs_register_param pacs_param = {
+		.snk_pac = true,
+		.snk_loc = true,
+	};
 	int err;
 
+	err = bt_pacs_register(&pacs_param);
+	if (err) {
+		printk("Could not register PACS (err %d)\n", err);
+		return err;
+	}
+
 	bt_bap_broadcast_sink_register_cb(&broadcast_sink_cbs);
 	bt_le_per_adv_sync_cb_register(&broadcast_sync_cb);
 
diff --git a/samples/bluetooth/tmap_bms/boards/native_posix.conf b/samples/bluetooth/tmap_bms/boards/native_posix.conf
deleted file mode 100644
index 8ab1d7be113..00000000000
--- a/samples/bluetooth/tmap_bms/boards/native_posix.conf
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_LOG_MODE_IMMEDIATE=y
-
-CONFIG_LIBLC3=y
-CONFIG_FPU=y
-
-# For LE-audio at 10ms intervals we need the tick counter to occur more frequently
-# than every 10 ms as each PDU for some reason takes 2 ticks to process.
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
-CONFIG_NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME=y
diff --git a/samples/bluetooth/tmap_bms/src/cap_initiator.c b/samples/bluetooth/tmap_bms/src/cap_initiator.c
index b7553d7d652..c8b701d62a7 100644
--- a/samples/bluetooth/tmap_bms/src/cap_initiator.c
+++ b/samples/bluetooth/tmap_bms/src/cap_initiator.c
@@ -15,6 +15,7 @@
 #include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/audio/tmap.h>
 #include <zephyr/bluetooth/byteorder.h>
+#include <zephyr/bluetooth/crypto.h>
 #include <zephyr/bluetooth/gap.h>
 #include <zephyr/bluetooth/iso.h>
 #include <zephyr/bluetooth/uuid.h>
diff --git a/samples/bluetooth/tmap_central/boards/native_posix.conf b/samples/bluetooth/tmap_central/boards/native_posix.conf
deleted file mode 100644
index 8ab1d7be113..00000000000
--- a/samples/bluetooth/tmap_central/boards/native_posix.conf
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_LOG_MODE_IMMEDIATE=y
-
-CONFIG_LIBLC3=y
-CONFIG_FPU=y
-
-# For LE-audio at 10ms intervals we need the tick counter to occur more frequently
-# than every 10 ms as each PDU for some reason takes 2 ticks to process.
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
-CONFIG_NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME=y
diff --git a/samples/bluetooth/tmap_central/src/mcp_server.c b/samples/bluetooth/tmap_central/src/mcp_server.c
index 1144569a1ba..5225e5b51ea 100644
--- a/samples/bluetooth/tmap_central/src/mcp_server.c
+++ b/samples/bluetooth/tmap_central/src/mcp_server.c
@@ -6,13 +6,10 @@
  *  SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/kernel.h>
-#include <zephyr/sys/printk.h>
-#include <stdlib.h>
-#include <stdio.h>
-
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/audio/media_proxy.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/printk.h>
 
 int mcp_server_init(void)
 {
diff --git a/samples/bluetooth/tmap_peripheral/boards/native_posix.conf b/samples/bluetooth/tmap_peripheral/boards/native_posix.conf
deleted file mode 100644
index 8ab1d7be113..00000000000
--- a/samples/bluetooth/tmap_peripheral/boards/native_posix.conf
+++ /dev/null
@@ -1,9 +0,0 @@
-CONFIG_LOG_MODE_IMMEDIATE=y
-
-CONFIG_LIBLC3=y
-CONFIG_FPU=y
-
-# For LE-audio at 10ms intervals we need the tick counter to occur more frequently
-# than every 10 ms as each PDU for some reason takes 2 ticks to process.
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
-CONFIG_NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME=y
diff --git a/samples/bluetooth/tmap_peripheral/src/bap_unicast_sr.c b/samples/bluetooth/tmap_peripheral/src/bap_unicast_sr.c
index 0aea8794f29..8883a2aad2c 100644
--- a/samples/bluetooth/tmap_peripheral/src/bap_unicast_sr.c
+++ b/samples/bluetooth/tmap_peripheral/src/bap_unicast_sr.c
@@ -367,8 +367,23 @@ static struct bt_pacs_cap cap = {
 	.codec_cap = &lc3_codec_cap,
 };
 
+
 int bap_unicast_sr_init(void)
 {
+	const struct bt_pacs_register_param pacs_param = {
+		.snk_pac = true,
+		.snk_loc = true,
+		.src_pac = true,
+		.src_loc = true,
+	};
+	int err;
+
+	err = bt_pacs_register(&pacs_param);
+	if (err) {
+		printk("Could not register PACS (err %d)\n", err);
+		return err;
+	}
+
 	bt_bap_unicast_server_register(&param);
 	bt_bap_unicast_server_register_cb(&unicast_server_cb);
 
diff --git a/samples/boards/bbc/microbit/pong/boards/bbc_microbit_v2.overlay b/samples/boards/bbc/microbit/pong/boards/bbc_microbit_v2.overlay
new file mode 100644
index 00000000000..33e471dc6b5
--- /dev/null
+++ b/samples/boards/bbc/microbit/pong/boards/bbc_microbit_v2.overlay
@@ -0,0 +1,6 @@
+/ {
+	zephyr,user {
+		/* period cell corresponds to initial period */
+		pwms = <&pwm1 0 PWM_USEC(1500) PWM_POLARITY_NORMAL>;
+	};
+};
diff --git a/samples/boards/espressif/deep_sleep/boards/esp32c6_devkitc.conf b/samples/boards/espressif/deep_sleep/boards/esp32c6_devkitc_hpcore.conf
similarity index 100%
rename from samples/boards/espressif/deep_sleep/boards/esp32c6_devkitc.conf
rename to samples/boards/espressif/deep_sleep/boards/esp32c6_devkitc_hpcore.conf
diff --git a/samples/boards/espressif/deep_sleep/src/main.c b/samples/boards/espressif/deep_sleep/src/main.c
index 519a1a550df..5cf93c6a98c 100644
--- a/samples/boards/espressif/deep_sleep/src/main.c
+++ b/samples/boards/espressif/deep_sleep/src/main.c
@@ -9,7 +9,9 @@
 #include <esp_sleep.h>
 #include <driver/rtc_io.h>
 
-#define WAKEUP_TIME_SEC		(20)
+#include <esp_attr.h>
+
+#define WAKEUP_TIME_SEC		(5)
 
 #ifdef CONFIG_EXAMPLE_EXT1_WAKEUP
 #define EXT_WAKEUP_PIN_1	(2)
@@ -24,8 +26,15 @@ static const struct gpio_dt_spec wakeup_button = GPIO_DT_SPEC_GET(DT_ALIAS(wakeu
 #endif
 #endif
 
+/* keep data in RTC memory after deep-sleep */
+RTC_DATA_ATTR int s_rtc_data = 0;
+
 int main(void)
 {
+#ifdef CONFIG_BOOTLOADER_MCUBOOT
+	printk("ESP32 deep sleep example, current counter is %d\r\n", s_rtc_data++);
+#endif
+
 	switch (esp_sleep_get_wakeup_cause()) {
 #ifdef CONFIG_EXAMPLE_EXT1_WAKEUP
 	case ESP_SLEEP_WAKEUP_EXT1:
diff --git a/samples/boards/espressif/spiram_test/prj.conf b/samples/boards/espressif/spiram_test/prj.conf
index c7dc9a2f6a9..64d0f6d73c9 100644
--- a/samples/boards/espressif/spiram_test/prj.conf
+++ b/samples/boards/espressif/spiram_test/prj.conf
@@ -1,3 +1,2 @@
 CONFIG_ESP_SPIRAM=y
 CONFIG_HEAP_MEM_POOL_SIZE=98304
-CONFIG_ESP_HEAP_SEARCH_ALL_REGIONS=n
diff --git a/samples/boards/espressif/ulp/index.rst b/samples/boards/espressif/ulp/index.rst
new file mode 100644
index 00000000000..89ff6980ec0
--- /dev/null
+++ b/samples/boards/espressif/ulp/index.rst
@@ -0,0 +1,5 @@
+.. zephyr:code-sample-category:: ulp
+   :name: Ultra Low Power coprocessor (ULP)
+   :show-listing:
+
+   These samples demonstrate how to use the ULP in Espressif SOCs.
diff --git a/samples/boards/espressif/ulp/lp_core/debug_ulp/CMakeLists.txt b/samples/boards/espressif/ulp/lp_core/debug_ulp/CMakeLists.txt
new file mode 100644
index 00000000000..c12f9e3c74c
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/debug_ulp/CMakeLists.txt
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+set(REMOTE_ZEPHYR_DIR ${CMAKE_CURRENT_BINARY_DIR}/../hello_ulp_lpcore/zephyr)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+message(STATUS "${CONFIG_BOARD_TARGET} compile as Master in this sample")
+project(debug_ulp_hpcore)
+
+target_sources(app PRIVATE src/main.c)
diff --git a/samples/boards/espressif/ulp/lp_core/debug_ulp/Kconfig.sysbuild b/samples/boards/espressif/ulp/lp_core/debug_ulp/Kconfig.sysbuild
new file mode 100644
index 00000000000..1a54b95872b
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/debug_ulp/Kconfig.sysbuild
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+source "share/sysbuild/Kconfig"
+
+config ULP_REMOTE_BOARD
+	string
+	default "esp32c6_devkitc/esp32c6/lpcore" if $(BOARD) = "esp32c6_devkitc"
diff --git a/samples/boards/espressif/ulp/lp_core/debug_ulp/README.rst b/samples/boards/espressif/ulp/lp_core/debug_ulp/README.rst
new file mode 100644
index 00000000000..c1011edf4e1
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/debug_ulp/README.rst
@@ -0,0 +1,123 @@
+.. zephyr:code-sample:: debug-ulp
+   :name: Debug ULP
+
+   Debug the LP Core in ESP32C6.
+
+Overview
+********
+
+This example demonstrates how to build, flash and debug a simple application on the LP core.
+
+This sample also provides a custom ``gdbinit`` file to be loaded by GDB to set up the debugging environment.
+It connects with the remote OpenOCD server, loads the symbols from the LP Core application
+and sets an initial breakpoint.
+
+Limitations
+***********
+1. Currently debugging is not supported when either HP or LP core enters any sleep mode. So this limits debugging scenarios.
+2. OS support is disabled when debugging the LP core, so you won't be able to see tasks running in the system. Instead there will be two threads representing HP ('esp32c6.cpu0') and LP ('esp32c6.cpu1') cores:
+
+.. code-block:: console
+
+   (gdb) info thread
+     Id   Target Id                                                                Frame
+     1    Thread 1 "esp32c6.hp.cpu0" (Name: esp32c6.hp.cpu0, state: debug-request) arch_irq_unlock (key=8) at zephyr/include/zephyr/arch/riscv/arch.h:259
+   * 2    Thread 2 "esp32c6.lp.cpu" (Name: esp32c6.lp.cpu, state: breakpoint)      do_things (max=1000000000) at zephyr/samples/boards/espressif/ulp/lp_core/debug_ulp/remote/src/main.c:28
+
+3. When setting HW breakpoint in GDB it is set on both cores, so the number of available HW breakpoints is limited to the number of them supported by LP core (2 for ESP32-C6).
+
+Sysbuild
+********
+
+Sysbuild is in charge of building the application located in the ``remote`` folder for the LP Core target.
+The build and flashing orders are as follows:
+
+Build:
+
+- MCUboot bootloader
+- LP Core application
+- HP Core application
+
+Flash:
+
+- MCUboot bootloader
+- HP Core application
+- LP Core application
+
+Building and Flashing
+*********************
+
+Build the sample code as follows:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/boards/espressif/ulp/lp_core/debug_ulp
+   :board: esp32c6_devkitc/esp32c6/hpcore
+   :west-args: --sysbuild
+   :goals: build
+   :compact:
+
+Flash it to the device with the command:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/boards/espressif/ulp/lp_core/debug_ulp
+   :board: esp32c6_devkitc/esp32c6/hpcore
+   :west-args: --sysbuild
+   :goals: flash
+   :compact:
+
+Debugging
+*********
+
+Connect the USB cable to the USB port of the ESP32-C6 Devkitc board.
+
+The ESP32-C6 modules require patches to OpenOCD that are not upstreamed yet.
+Espressif maintains their own fork of the project.
+The custom OpenOCD can be obtained at `OpenOCD ESP32`_.
+
+In one terminal instance run the Espressif's OpenOCD:
+
+.. code-block:: shell
+
+   <path/to/openocd-esp32>/bin/openocd -f board/esp32c6-lpcore-builtin.cfg
+
+Wait for the following output to show up in the console:
+
+.. code-block:: console
+
+   Info : Listening on port 3333 for gdb connections
+
+On another terminal instance, run the GDB:
+
+.. code-block:: shell
+
+   <path/to/zephyr/sdk>/riscv64-zephyr-elf/bin/riscv64-zephyr-elf-gdb -x samples/boards/espressif/ulp/lp_core/debug_ulp/gdbinit build/debug_ulp/zephyr/zephyr.elf
+
+The following output should be displayed:
+
+.. code-block:: console
+
+   [esp32c6.hp.cpu0] Reset cause (24) - (JTAG CPU reset)
+   add symbol table from file "build/debug_ulp_lpcore/zephyr/zephyr.elf"
+   Hardware assisted breakpoint 1 at 0x500000ec: file zephyr/samples/boards/espressif/ulp/lp_core/debug_ulp/remote/src/main.c, line 28.
+   (gdb)
+
+From now on you can use the GDB commands to debug the application. By using the command ``continue`` the LP Core application stop at the assigned breakpoint:
+
+.. code-block:: console
+
+   (gdb) continue
+   Continuing.
+   [Switching to Thread 2]
+
+   Thread 2 "esp32c6.lp.cpu" hit Temporary breakpoint 1, do_things (max=1000000000) at zephyr/samples/boards/espressif/ulp/lp_core/debug_ulp/remote/src/main.c:28
+   28                      for (int i = 0; i < max; i++) {
+   (gdb)
+
+When the application reaches the ``abort()`` function it will automatically break.
+
+References
+**********
+
+.. target-notes::
+
+.. _`OpenOCD ESP32`: https://github.com/espressif/openocd-esp32/releases
diff --git a/samples/boards/espressif/ulp/lp_core/debug_ulp/gdbinit b/samples/boards/espressif/ulp/lp_core/debug_ulp/gdbinit
new file mode 100644
index 00000000000..b1da390631b
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/debug_ulp/gdbinit
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+set pagination off
+target extended-remote :3333
+
+mon reset halt
+maintenance flush register-cache
+
+add-symbol build/debug_ulp_lpcore/zephyr/zephyr.elf
+thb do_things
diff --git a/samples/boards/espressif/ulp/lp_core/debug_ulp/prj.conf b/samples/boards/espressif/ulp/lp_core/debug_ulp/prj.conf
new file mode 100644
index 00000000000..ddeb8d78974
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/debug_ulp/prj.conf
@@ -0,0 +1,2 @@
+CONFIG_ULP_COPROC_ENABLED=y
+CONFIG_LOG=y
diff --git a/samples/boards/espressif/ulp/lp_core/debug_ulp/remote/CMakeLists.txt b/samples/boards/espressif/ulp/lp_core/debug_ulp/remote/CMakeLists.txt
new file mode 100644
index 00000000000..bca02c90158
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/debug_ulp/remote/CMakeLists.txt
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+message(STATUS "${BOARD} compiles as remote in this sample")
+project(debug_ulp_lpcore)
+
+target_sources(app PRIVATE src/main.c)
diff --git a/samples/boards/espressif/ulp/lp_core/debug_ulp/remote/prj.conf b/samples/boards/espressif/ulp/lp_core/debug_ulp/remote/prj.conf
new file mode 100644
index 00000000000..7c76e06e876
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/debug_ulp/remote/prj.conf
@@ -0,0 +1,6 @@
+CONFIG_DEBUG=y
+CONFIG_NO_OPTIMIZATIONS=y
+
+# Create a disassembly file
+CONFIG_OUTPUT_DISASSEMBLY=y
+CONFIG_OUTPUT_DISASSEMBLE_ALL=y
diff --git a/samples/boards/espressif/ulp/lp_core/debug_ulp/remote/src/main.c b/samples/boards/espressif/ulp/lp_core/debug_ulp/remote/src/main.c
new file mode 100644
index 00000000000..b8a7ffc5a25
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/debug_ulp/remote/src/main.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include "ulp_lp_core_utils.h"
+#include <esp_cpu.h>
+#include "riscv/rvruntime-frames.h"
+
+/* Override for the ulp_lp_core_panic_handler() so it stops the debugger when abort() is called */
+void ulp_lp_core_panic_handler(RvExcFrame *frame, int exccause)
+{
+	esp_cpu_dbgr_break();
+}
+
+void do_crash(void)
+{
+	volatile int *p = (int *)0x0;
+	*p = 32;
+	abort();
+}
+
+void do_things(int max)
+{
+	while (1) {
+		for (int i = 0; i < max; i++) {
+			ulp_lp_core_delay_us(100000);
+			if (i > 0) {
+				do_crash();
+			}
+		}
+	}
+}
+
+int main(void)
+{
+	do_things(1000000000);
+	return 0;
+}
diff --git a/samples/boards/espressif/ulp/lp_core/debug_ulp/sample.yaml b/samples/boards/espressif/ulp/lp_core/debug_ulp/sample.yaml
new file mode 100644
index 00000000000..d5f80d99f9e
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/debug_ulp/sample.yaml
@@ -0,0 +1,9 @@
+sample:
+  name: ESP32C6 LP_CORE Debug Sample
+tests:
+  sample.boards.espressif.ulp.lp_core.debug_ulp:
+    platform_allow:
+      - esp32c6_devkitc/esp32c6/hpcore
+    tags:
+      - samples
+    sysbuild: true
diff --git a/samples/boards/espressif/ulp/lp_core/debug_ulp/src/main.c b/samples/boards/espressif/ulp/lp_core/debug_ulp/src/main.c
new file mode 100644
index 00000000000..bfb97b8f271
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/debug_ulp/src/main.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <zephyr/sys/poweroff.h>
+#include <esp_sleep.h>
+#include <ulp_lp_core.h>
+#include <zephyr/kernel.h>
+
+int main(void)
+{
+	while (1) {
+		k_sleep(K_MSEC(1000));
+	}
+
+	return 0;
+}
diff --git a/samples/boards/espressif/ulp/lp_core/debug_ulp/sysbuild.cmake b/samples/boards/espressif/ulp/lp_core/debug_ulp/sysbuild.cmake
new file mode 100644
index 00000000000..79b72a6fd8d
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/debug_ulp/sysbuild.cmake
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright 2025 Espressif
+
+# Add external project
+ExternalZephyrProject_Add(
+    APPLICATION debug_ulp_lpcore
+    SOURCE_DIR ${APP_DIR}/remote
+    BOARD ${SB_CONFIG_ULP_REMOTE_BOARD}
+  )
+
+# Add dependencies so that the remote sample will be built first
+# This is required because some primary cores need information from the
+# remote core's build, such as the output image's LMA
+add_dependencies(debug_ulp debug_ulp_lpcore)
+sysbuild_add_dependencies(CONFIGURE debug_ulp debug_ulp_lpcore)
+sysbuild_add_dependencies(FLASH debug_ulp_lpcore debug_ulp)
+
+if(SB_CONFIG_BOOTLOADER_MCUBOOT)
+  # Make sure MCUboot is flashed first
+  sysbuild_add_dependencies(FLASH debug_ulp mcuboot)
+endif()
diff --git a/samples/boards/espressif/ulp/lp_core/echo_ulp/CMakeLists.txt b/samples/boards/espressif/ulp/lp_core/echo_ulp/CMakeLists.txt
new file mode 100644
index 00000000000..8567bfb13c7
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/echo_ulp/CMakeLists.txt
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+set(REMOTE_ZEPHYR_DIR ${CMAKE_CURRENT_BINARY_DIR}/../echo_ulp_lpcore/zephyr)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+message(STATUS "${CONFIG_BOARD_TARGET} compile as Master in this sample")
+project(echo_ulp_hpcore)
+
+target_sources(app PRIVATE src/main.c)
diff --git a/samples/boards/espressif/ulp/lp_core/echo_ulp/Kconfig.sysbuild b/samples/boards/espressif/ulp/lp_core/echo_ulp/Kconfig.sysbuild
new file mode 100644
index 00000000000..1a54b95872b
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/echo_ulp/Kconfig.sysbuild
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+source "share/sysbuild/Kconfig"
+
+config ULP_REMOTE_BOARD
+	string
+	default "esp32c6_devkitc/esp32c6/lpcore" if $(BOARD) = "esp32c6_devkitc"
diff --git a/samples/boards/espressif/ulp/lp_core/echo_ulp/README.rst b/samples/boards/espressif/ulp/lp_core/echo_ulp/README.rst
new file mode 100644
index 00000000000..5e1b63bfe8f
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/echo_ulp/README.rst
@@ -0,0 +1,39 @@
+.. zephyr:code-sample:: echo-ulp
+   :name: Echo ULP
+
+   Leverage Zephyr's UART API to use the LP UART on the ESP32-C6's LP core.
+
+Overview
+********
+
+This sample application demonstrates how to use poll-based APIs from the Zephyr
+UART driver subsystem. It reads characters from the LP UART using
+:c:func:`uart_poll_in` and echoes them back using :c:func:`uart_poll_out`.
+
+Building and Flashing
+*********************
+
+Build the sample code as follows:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/boards/espressif/ulp/lp_core/echo_ulp
+   :board: esp32c6_devkitc/esp32c6/hpcore
+   :west-args: --sysbuild
+   :goals: build
+   :compact:
+
+Flash it to the device with the command:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/boards/espressif/ulp/lp_core/echo_ulp
+   :board: esp32c6_devkitc/esp32c6/hpcore
+   :west-args: --sysbuild
+   :goals: flash
+   :compact:
+
+Sample Output
+=============
+
+.. code-block:: console
+
+    UART echo example started. Type something...
diff --git a/samples/boards/espressif/ulp/lp_core/echo_ulp/app.overlay b/samples/boards/espressif/ulp/lp_core/echo_ulp/app.overlay
new file mode 100644
index 00000000000..244dc34aa97
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/echo_ulp/app.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&lp_uart {
+	status = "okay";
+};
diff --git a/samples/boards/espressif/ulp/lp_core/echo_ulp/prj.conf b/samples/boards/espressif/ulp/lp_core/echo_ulp/prj.conf
new file mode 100644
index 00000000000..7d425a10aa2
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/echo_ulp/prj.conf
@@ -0,0 +1 @@
+CONFIG_ULP_COPROC_ENABLED=y
diff --git a/samples/boards/espressif/ulp/lp_core/echo_ulp/remote/CMakeLists.txt b/samples/boards/espressif/ulp/lp_core/echo_ulp/remote/CMakeLists.txt
new file mode 100644
index 00000000000..27258dcbb0d
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/echo_ulp/remote/CMakeLists.txt
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+message(STATUS "${BOARD} compiles as remote in this sample")
+project(echo_ulp_lpcore)
+
+target_sources(app PRIVATE src/main.c)
diff --git a/samples/boards/espressif/ulp/lp_core/echo_ulp/remote/prj.conf b/samples/boards/espressif/ulp/lp_core/echo_ulp/remote/prj.conf
new file mode 100644
index 00000000000..5b2f334cc4a
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/echo_ulp/remote/prj.conf
@@ -0,0 +1,3 @@
+CONFIG_MAIN_STACK_SIZE=1024
+CONFIG_ISR_STACK_SIZE=64
+CONFIG_IDLE_STACK_SIZE=32
diff --git a/samples/boards/espressif/ulp/lp_core/echo_ulp/remote/src/main.c b/samples/boards/espressif/ulp/lp_core/echo_ulp/remote/src/main.c
new file mode 100644
index 00000000000..53c6ee4fd5a
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/echo_ulp/remote/src/main.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/uart.h>
+
+#define UART_DEVICE_NODE DT_NODELABEL(lp_uart)
+
+int main(void)
+{
+	const struct device *uart_dev = DEVICE_DT_GET(UART_DEVICE_NODE);
+	char c;
+	int ret = 0;
+
+	printf("UART echo example started. Type something...\n");
+
+	while (1) {
+		ret = uart_poll_in(uart_dev, &c);
+		if (ret == 0) {
+			/* Echo character back out */
+			uart_poll_out(uart_dev, c);
+			if (c == '\r') {
+				uart_poll_out(uart_dev, '\n');
+			}
+		}
+	}
+
+	return 0;
+}
diff --git a/samples/boards/espressif/ulp/lp_core/echo_ulp/sample.yaml b/samples/boards/espressif/ulp/lp_core/echo_ulp/sample.yaml
new file mode 100644
index 00000000000..a3260b2b60e
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/echo_ulp/sample.yaml
@@ -0,0 +1,9 @@
+sample:
+  name: ESP32-C6 LP_CORE Echo Sample
+tests:
+  sample.boards.espressif.ulp.lp_core.echo_ulp:
+    platform_allow:
+      - esp32c6_devkitc/esp32c6/hpcore
+    tags:
+      - samples
+    sysbuild: true
diff --git a/samples/boards/espressif/ulp/lp_core/echo_ulp/src/main.c b/samples/boards/espressif/ulp/lp_core/echo_ulp/src/main.c
new file mode 100644
index 00000000000..bfb97b8f271
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/echo_ulp/src/main.c
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <zephyr/sys/poweroff.h>
+#include <esp_sleep.h>
+#include <ulp_lp_core.h>
+#include <zephyr/kernel.h>
+
+int main(void)
+{
+	while (1) {
+		k_sleep(K_MSEC(1000));
+	}
+
+	return 0;
+}
diff --git a/samples/boards/espressif/ulp/lp_core/echo_ulp/sysbuild.cmake b/samples/boards/espressif/ulp/lp_core/echo_ulp/sysbuild.cmake
new file mode 100644
index 00000000000..5eaf61a64da
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/echo_ulp/sysbuild.cmake
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright 2024 Espressif
+
+# Add external project
+ExternalZephyrProject_Add(
+    APPLICATION echo_ulp_lpcore
+    SOURCE_DIR ${APP_DIR}/remote
+    BOARD ${SB_CONFIG_ULP_REMOTE_BOARD}
+  )
+
+# Add dependencies so that the remote sample will be built first
+# This is required because some primary cores need information from the
+# remote core's build, such as the output image's LMA
+add_dependencies(echo_ulp echo_ulp_lpcore)
+sysbuild_add_dependencies(CONFIGURE echo_ulp echo_ulp_lpcore)
+sysbuild_add_dependencies(FLASH echo_ulp_lpcore echo_ulp)
+
+if(SB_CONFIG_BOOTLOADER_MCUBOOT)
+  # Make sure MCUboot is flashed first
+  sysbuild_add_dependencies(FLASH echo_ulp mcuboot)
+endif()
diff --git a/samples/boards/espressif/ulp/lp_core/index.rst b/samples/boards/espressif/ulp/lp_core/index.rst
new file mode 100644
index 00000000000..d06d7a11443
--- /dev/null
+++ b/samples/boards/espressif/ulp/lp_core/index.rst
@@ -0,0 +1,5 @@
+.. zephyr:code-sample-category:: lp-core
+   :name: Low-Power CPU (LP CORE)
+   :show-listing:
+
+   These samples demonstrate how to use the LP Core in Espressif SOCs.
diff --git a/samples/boards/microchip/mec15xxevb_assy6853/power_management/prj.conf b/samples/boards/microchip/mec15xxevb_assy6853/power_management/prj.conf
index 5f4d0ced0e8..1db43e4d329 100644
--- a/samples/boards/microchip/mec15xxevb_assy6853/power_management/prj.conf
+++ b/samples/boards/microchip/mec15xxevb_assy6853/power_management/prj.conf
@@ -9,6 +9,5 @@ CONFIG_THREAD_NAME=y
 
 # Enable additional drivers to evaluate power consumption without activity
 CONFIG_PECI=y
-CONFIG_KSCAN=y
 
 CONFIG_IDLE_STACK_SIZE=512
diff --git a/samples/boards/nordic/coresight_stm/sample.yaml b/samples/boards/nordic/coresight_stm/sample.yaml
index bf9016baaba..000241d4d97 100644
--- a/samples/boards/nordic/coresight_stm/sample.yaml
+++ b/samples/boards/nordic/coresight_stm/sample.yaml
@@ -2,7 +2,7 @@ sample:
   name: Logging using Coresight STM on nrf54h20
 
 common:
-  tags: stm
+  tags: coresight_stm
   sysbuild: true
   platform_allow:
     - nrf54h20dk/nrf54h20/cpuapp
diff --git a/samples/boards/nordic/nrf_sys_event/sample.yaml b/samples/boards/nordic/nrf_sys_event/sample.yaml
index c5ea3d8a23d..40e6d6d229b 100644
--- a/samples/boards/nordic/nrf_sys_event/sample.yaml
+++ b/samples/boards/nordic/nrf_sys_event/sample.yaml
@@ -19,6 +19,7 @@ tests:
       - nrf54h20dk/nrf54h20/cpuapp
       - nrf54h20dk/nrf54h20/cpurad
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf52840dk/nrf52840
       - nrf5340dk/nrf5340/cpuapp
@@ -26,3 +27,4 @@ tests:
       - nrf54h20dk/nrf54h20/cpuapp
       - nrf54h20dk/nrf54h20/cpurad
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
diff --git a/samples/boards/nordic/nrfx_prs/src/main.c b/samples/boards/nordic/nrfx_prs/src/main.c
index cf989b4c4c9..1b9411d2da4 100644
--- a/samples/boards/nordic/nrfx_prs/src/main.c
+++ b/samples/boards/nordic/nrfx_prs/src/main.c
@@ -122,6 +122,7 @@ static bool switch_to_spim(void)
 {
 	int ret;
 	nrfx_err_t err;
+	uint32_t sck_pin;
 
 	PINCTRL_DT_DEFINE(SPIM_NODE);
 
@@ -155,8 +156,11 @@ static bool switch_to_spim(void)
 	}
 
 	/* Set initial state of SCK according to the SPI mode. */
-	nrfy_gpio_pin_write(nrfy_spim_sck_pin_get(spim.p_reg),
-			    (spim_config.mode <= NRF_SPIM_MODE_1) ? 0 : 1);
+	sck_pin = nrfy_spim_sck_pin_get(spim.p_reg);
+
+	if (sck_pin != NRF_SPIM_PIN_NOT_CONNECTED) {
+		nrfy_gpio_pin_write(sck_pin, (spim_config.mode <= NRF_SPIM_MODE_1) ? 0 : 1);
+	}
 
 	err = nrfx_spim_init(&spim, &spim_config, spim_handler, NULL);
 	if (err != NRFX_SUCCESS) {
diff --git a/samples/boards/nordic/system_off/sample.yaml b/samples/boards/nordic/system_off/sample.yaml
index c3d7998854b..6e17223e12b 100644
--- a/samples/boards/nordic/system_off/sample.yaml
+++ b/samples/boards/nordic/system_off/sample.yaml
@@ -115,12 +115,6 @@ tests:
         - "system off demo"
         - "Retained data not supported"
         - "Entering system off; change signal level at comparator input to restart"
-        - "system off demo"
-        - "Retained data not supported"
-        - "Entering system off; change signal level at comparator input to restart"
-        - "system off demo"
-        - "Retained data not supported"
-        - "Entering system off; change signal level at comparator input to restart"
   sample.boards.nrf.system_off.retained_mem.lpcomp_wakeup:
     extra_args:
       - "DTC_OVERLAY_FILE=
@@ -145,9 +139,3 @@ tests:
         - "Off count: 0"
         - "Active Ticks:"
         - "Entering system off; change signal level at comparator input to restart"
-        - "system off demo"
-        - "Retained data: valid"
-        - "Boot count: 2"
-        - "Off count: 1"
-        - "Active Ticks:"
-        - "Entering system off; change signal level at comparator input to restart"
diff --git a/samples/boards/nxp/mimxrt1060_evk/system_off/sample.yaml b/samples/boards/nxp/mimxrt1060_evk/system_off/sample.yaml
index c620b53c5f3..d6ca0dd5ee0 100644
--- a/samples/boards/nxp/mimxrt1060_evk/system_off/sample.yaml
+++ b/samples/boards/nxp/mimxrt1060_evk/system_off/sample.yaml
@@ -6,7 +6,8 @@ tests:
   sample.boards.mimxrt1060_evk.system_off:
     build_only: true
     platform_allow:
-      - mimxrt1060_evk/mimxrt1062/qspi
+      - mimxrt1060_evk@A/mimxrt1062/qspi
       - mimxrt1060_evk@B/mimxrt1062/qspi
+      - mimxrt1060_evk@C/mimxrt1062/qspi
     integration_platforms:
       - mimxrt1060_evk/mimxrt1062/qspi
diff --git a/samples/boards/nxp/mimxrt1170_evk_cm7/magic_addr/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/samples/boards/nxp/mimxrt1170_evk_cm7/magic_addr/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay
new file mode 100644
index 00000000000..3a05d47bdfb
--- /dev/null
+++ b/samples/boards/nxp/mimxrt1170_evk_cm7/magic_addr/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay
@@ -0,0 +1,19 @@
+/* default fuse */
+&flexram {
+	flexram,bank-spec = <FLEXRAM_DTCM>,
+			    <FLEXRAM_DTCM>,
+			    <FLEXRAM_DTCM>,
+			    <FLEXRAM_DTCM>,
+			    <FLEXRAM_ITCM>,
+			    <FLEXRAM_ITCM>,
+			    <FLEXRAM_ITCM>,
+			    <FLEXRAM_ITCM>,
+			    <FLEXRAM_DTCM>,
+			    <FLEXRAM_DTCM>,
+			    <FLEXRAM_DTCM>,
+			    <FLEXRAM_DTCM>,
+			    <FLEXRAM_ITCM>,
+			    <FLEXRAM_ITCM>,
+			    <FLEXRAM_ITCM>,
+			    <FLEXRAM_ITCM>;
+};
diff --git a/samples/boards/renesas/comparator/CMakeLists.txt b/samples/boards/renesas/comparator/CMakeLists.txt
new file mode 100644
index 00000000000..3fffa20e3ff
--- /dev/null
+++ b/samples/boards/renesas/comparator/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(renesas_comparator)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/samples/boards/renesas/comparator/Kconfig b/samples/boards/renesas/comparator/Kconfig
new file mode 100644
index 00000000000..97b44b8c886
--- /dev/null
+++ b/samples/boards/renesas/comparator/Kconfig
@@ -0,0 +1,13 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+mainmenu "Comparator sample additional options"
+
+source "Kconfig.zephyr"
+
+ZEPHYR_USER := zephyr,user
+
+config DAC_REFERENCE_SOURCE
+	bool
+	select DAC
+	default y if $(dt_node_has_prop,/$(ZEPHYR_USER),vref-dac)
diff --git a/samples/boards/renesas/comparator/README.rst b/samples/boards/renesas/comparator/README.rst
new file mode 100644
index 00000000000..d9fefcf4222
--- /dev/null
+++ b/samples/boards/renesas/comparator/README.rst
@@ -0,0 +1,48 @@
+.. zephyr:code-sample:: renesas_comparator
+   :name: Renesas comparator
+
+   Monitor the output of comparator.
+
+Overview
+********
+
+A sample that help to monitor the output of comparator.
+
+Hardware Setup
+**************
+
+* The IVREF is connected to the internal output of DA0 (DAC module).
+  By default, DA0 is set to ~1.75V (half of the full-scale voltage).
+
+* For IVCOMP, the user can connect the IVCMP3 input to either:
+
+   * Case 1: IVCMP3 with SW0 (button on board, on ek_ra8m1 is P600).
+   * Case 2: IVCMP3 with external voltage for comparison.
+
+Building and Running
+********************
+
+This application can be built and executed on RA boards as follows:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/boards/renesas/comparator
+   :board: ek_ra8m1
+   :goals: build flash
+   :compact:
+
+The comparator's output controls LED0:
+
+   * If the comparator output is HIGH, LED0 turns on.
+   * If the comparator output is LOW, LED0 turns off.
+
+   Example case:
+
+   * Case 1: IVCMP3 connected to SW0 (Pull up)
+
+      * SW0 not pressed --> Comparator output HIGH --> LED0 on
+      * SW0 pressed --> Comparator output LOW --> LED0 off
+
+   * Case 2: IVCMP3 connected to another reference voltage
+
+      * IVCMP3 HIGH --> Comparator output HIGH --> LED0 on
+      * IVCMP3 LOW --> Comparator output LOW --> LED0 off
diff --git a/samples/boards/renesas/comparator/boards/ek_ra8d1.overlay b/samples/boards/renesas/comparator/boards/ek_ra8d1.overlay
new file mode 100644
index 00000000000..ea9bcf5b487
--- /dev/null
+++ b/samples/boards/renesas/comparator/boards/ek_ra8d1.overlay
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	aliases {
+		sample-comp = &acmphs0;
+	};
+
+	zephyr,user {
+		vref-dac = <&dac0>;
+	};
+};
+
+&acmphs_global {
+	status = "okay";
+
+	acmphs0 {
+		/*
+		 * Since ivref3 is internally routed from to DA0 (DAC),
+		 * there is no need to add pinsel of ivref3.
+		 */
+		pinctrl-0 = <&acmphs0_ivcmp3>;
+		pinctrl-names = "default";
+		interrupts = <90 12>;
+		interrupt-names = "hs";
+		reference-input-source = "ivref3";
+		compare-input-source = "ivcmp3";
+		status = "okay";
+	};
+};
diff --git a/samples/boards/renesas/comparator/boards/ek_ra8m1.overlay b/samples/boards/renesas/comparator/boards/ek_ra8m1.overlay
new file mode 100644
index 00000000000..5d97c6005a2
--- /dev/null
+++ b/samples/boards/renesas/comparator/boards/ek_ra8m1.overlay
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		sample-comp = &acmphs0;
+	};
+
+	zephyr,user {
+		vref-dac = <&dac0>;
+	};
+};
+
+&acmphs_global {
+	status = "okay";
+
+	acmphs0 {
+		/*
+		 * Since ivref3 is internally routed from to DA0 (DAC),
+		 * there is no need to add pinsel of ivref3.
+		 */
+		pinctrl-0 = <&acmphs0_ivcmp3>;
+		pinctrl-names = "default";
+		interrupts = <90 12>;
+		interrupt-names = "hs";
+		reference-input-source = "ivref3";
+		compare-input-source = "ivcmp3";
+		status = "okay";
+	};
+};
diff --git a/samples/boards/renesas/comparator/prj.conf b/samples/boards/renesas/comparator/prj.conf
new file mode 100644
index 00000000000..94d0c848f17
--- /dev/null
+++ b/samples/boards/renesas/comparator/prj.conf
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_GPIO=y
+CONFIG_COMPARATOR=y
diff --git a/samples/boards/renesas/comparator/sample.yaml b/samples/boards/renesas/comparator/sample.yaml
new file mode 100644
index 00000000000..133521066a7
--- /dev/null
+++ b/samples/boards/renesas/comparator/sample.yaml
@@ -0,0 +1,9 @@
+sample:
+  name: Comparator
+tests:
+  sample.boards.renesas.comparator:
+    build_only: true
+    platform_allow:
+      - ek_ra8m1
+      - ek_ra8d1
+    tags: comparator
diff --git a/samples/boards/renesas/comparator/src/main.c b/samples/boards/renesas/comparator/src/main.c
new file mode 100644
index 00000000000..053280da0e4
--- /dev/null
+++ b/samples/boards/renesas/comparator/src/main.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/comparator.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/printk.h>
+#ifdef CONFIG_DAC_REFERENCE_SOURCE
+#include <zephyr/drivers/dac.h>
+#endif
+
+/*
+ * Get button configuration from the devicetree sw0 alias. This is mandatory.
+ */
+#define SW0_NODE DT_ALIAS(sw0)
+#if !DT_NODE_HAS_STATUS_OKAY(SW0_NODE)
+#error "Unsupported board: sw0 devicetree alias is not defined"
+#endif
+
+static const struct gpio_dt_spec button = GPIO_DT_SPEC_GET_OR(SW0_NODE, gpios, {0});
+static struct gpio_dt_spec led = GPIO_DT_SPEC_GET_OR(DT_ALIAS(led0), gpios, {0});
+static const struct device *comp_dev = DEVICE_DT_GET(DT_ALIAS(sample_comp));
+
+#ifdef CONFIG_DAC_REFERENCE_SOURCE
+static const struct dac_channel_cfg dac_ch_cfg = {
+	.channel_id = 0,
+	.resolution = 12,
+	.buffered = true,
+};
+
+static const struct device *init_dac(void)
+{
+	int ret;
+	const struct device *const dac_dev = DEVICE_DT_GET(DT_PROP(DT_PATH(zephyr_user), vref_dac));
+
+	ret = device_is_ready(dac_dev);
+	if (ret != true) {
+		printk("DAC device is not ready\n");
+		return NULL;
+	}
+
+	ret = dac_channel_setup(dac_dev, &dac_ch_cfg);
+	if (ret != 0) {
+		printk("Setting up of the first channel failed with code %d\n", ret);
+		return NULL;
+	}
+
+	return dac_dev;
+}
+#endif
+
+static void comp_callback(const struct device *dev, void *user_data)
+{
+	int val = comparator_get_output(comp_dev);
+
+	gpio_pin_set_dt(&led, val);
+	printk("Comparator output value %d\n", val);
+}
+
+int main(void)
+{
+	int ret;
+#ifdef CONFIG_DAC_REFERENCE_SOURCE
+	const struct device *dac_dev = init_dac();
+
+	if (dac_dev == NULL) {
+		printk("Init_dac failed\n");
+		return 0;
+	}
+	/* write a value of half the full scale resolution */
+	ret = dac_write_value(dac_dev, dac_ch_cfg.channel_id, (1U << dac_ch_cfg.resolution) / 2);
+	if (ret != 0) {
+		printk("dac_write_value() failed with code %d", ret);
+		return 0;
+	}
+#endif
+
+	if (!gpio_is_ready_dt(&button)) {
+		printk("Error: button device %s is not ready\n", button.port->name);
+		return 0;
+	}
+
+	ret = gpio_pin_configure_dt(&button, GPIO_INPUT);
+	if (ret != 0) {
+		printk("Error %d: failed to configure %s pin %d\n", ret, button.port->name,
+		       button.pin);
+		return 0;
+	}
+
+	if (led.port && !gpio_is_ready_dt(&led)) {
+		printk("Error %d: LED device %s is not ready; ignoring it\n", ret, led.port->name);
+		led.port = NULL;
+	}
+
+	if (led.port) {
+		ret = gpio_pin_configure_dt(&led, GPIO_OUTPUT);
+		if (ret != 0) {
+			printk("Error %d: failed to configure LED device %s pin %d\n", ret,
+			       led.port->name, led.pin);
+			led.port = NULL;
+		}
+	}
+
+	comparator_set_trigger(comp_dev, COMPARATOR_TRIGGER_BOTH_EDGES);
+	comparator_set_trigger_callback(comp_dev, comp_callback, NULL);
+
+	printk("Press the button\n");
+
+	return 0;
+}
diff --git a/samples/boards/renesas/index.rst b/samples/boards/renesas/index.rst
new file mode 100644
index 00000000000..e0b2898847a
--- /dev/null
+++ b/samples/boards/renesas/index.rst
@@ -0,0 +1,5 @@
+.. zephyr:code-sample-category:: renesas
+   :name: Renesas
+   :show-listing:
+
+   Samples that showcase the use of Renesas boards in Zephyr.
diff --git a/samples/boards/renesas/openamp_linux_zephyr/CMakeLists.txt b/samples/boards/renesas/openamp_linux_zephyr/CMakeLists.txt
new file mode 100644
index 00000000000..7e6ce78c07b
--- /dev/null
+++ b/samples/boards/renesas/openamp_linux_zephyr/CMakeLists.txt
@@ -0,0 +1,20 @@
+cmake_minimum_required(VERSION 3.20.0)
+# Copyright (c) 2025 Renesas Electronics Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+project(openamp_linux_zephyr)
+
+# METAL_MAX_DEVICE_REGIONS is used to give the number of memory regions shared
+# between processors. By default only one region is defined for the vrings
+# and rpmsg buffers. The METAL_MAX_DEVICE_REGIONS has to be redefined to add a
+# second region for the resource table.
+zephyr_compile_definitions(METAL_MAX_DEVICE_REGIONS=2)
+
+target_include_directories(app PRIVATE ${LIBMETAL_INCLUDE_DIR} ${OPENAMP_INCLUDE_DIR} ${PLATFORM_DIR})
+target_include_directories(app PRIVATE src)
+
+target_sources(app PRIVATE src/resource_table.c src/main_remote.c)
diff --git a/samples/boards/renesas/openamp_linux_zephyr/README.rst b/samples/boards/renesas/openamp_linux_zephyr/README.rst
new file mode 100644
index 00000000000..1afac299194
--- /dev/null
+++ b/samples/boards/renesas/openamp_linux_zephyr/README.rst
@@ -0,0 +1,175 @@
+.. zephyr:code-sample:: rz-openamp-linux-zephyr
+   :name: OpenAMP Linux Zephyr RPMsg
+   :relevant-api: mbox_interface
+
+   Enable message exchange between two cores, with the application core running Linux
+   and the real-time core running Zephyr, using the OpenAMP library.
+
+Overview
+********
+
+This application demonstrates how to use OpenAMP for communication between Zephyr and Linux,
+where both sides utilize the OpenAMP library.
+
+On the Linux side, the application uses the OpenAMP library provided by `meta-openamp <https://github.com/OpenAMP/meta-openamp>`_, ensuring
+a consistent and standardized approach to inter-core communication.
+
+Building the application
+*************************
+
+Zephyr
+======
+
+Build command:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/boards/renesas/openamp_linux_zephyr
+   :board: rzg3s_smarc/r9a08g045s33gbg/cm33
+   :goals: build
+   :compact:
+
+Running the sample
+*************************
+
+Linux setup
+===========
+
+The sample currently supports the Linux RZ/G Multi-OS Package V2.2.0. The build steps for Renesas Multi-OS Package V2.2.0 are described below.
+
+1. Follow the procedures in ''3.Multi-OS Package Setup'' of `Release Note for RZ/G Multi-OS Package V2.2.0 <https://www.renesas.com/en/document/rln/release-note-rzg-multi-os-package-v220?r=1522841>`_
+   without initiating the build process.
+2. For RZ/G3S, add ``PLAT_M33_BOOT_SUPPORT=1`` by following this guide:
+   `RZ/G3S SMARC Evaluation Board Kit <https://docs.zephyrproject.org/latest/boards/renesas/rzg3s_smarc/doc/index.html#programming-and-debugging>`_
+
+3. Insert the highlighted lines of code into the following file: meta-rz-features/meta-rz-multi-os/meta-rzg3s/recipes-example/rpmsg-sample/files/platform_info.c
+
+   .. code-block:: c
+      :emphasize-lines: 5,6,7,8,9,10
+
+      if (ret) {
+      LPRINTF("failed rpmsg_init_vdev");
+      goto err;
+      }
+      /* RPMsg virtio enables callback for avail flags */
+      ret = virtqueue_enable_cb(rpmsg_vdev->rvq);
+      if (ret) {
+         LPRINTF("Failed release availability flags");
+         goto err;
+      }
+      #ifndef __linux__ /* uC3 */
+      start_ipi_task(rproc);
+      #endif
+      return rpmsg_virtio_get_rpmsg_device(rpmsg_vdev);
+
+4. Start the build.
+
+5. For deploying bootloader files, Linux kernel image, device tree and rootfs, follow the procedures in ''3.5.1 In case of configuring CA55 as Boot CPU'' of `Release Note for RZ/G Multi-OS Package V2.2.0 <https://www.renesas.com/en/document/rln/release-note-rzg-multi-os-package-v220?r=1522841>`_
+
+Zephyr setup
+============
+
+1. Flash the sample to the board.
+
+2. Open a serial terminal (minicom, putty, etc.) and connect to the board with the following
+   settings:
+
+   - Speed: 115200
+   - Data: 8 bits
+   - Parity: None
+   - Stop bits: 1
+
+Linux console
+=============
+
+1. Open a Linux shell (minicom, ssh, etc.) and login as root:
+
+   .. code-block:: console
+
+      smarc-<device> login: root
+
+2. Run the following command:
+
+   .. code-block:: console
+
+      root@smarc-<device>:~# rpmsg_sample_client 0 0
+
+3. The following output should appear:
+
+   .. code-block:: console
+
+      root@smarc-<device>:~# rpmsg_sample_client 0 0
+      [211] proc_id:0 rsc_id:0 mbx_id:0
+      metal: info:      metal_uio_dev_open: No IRQ for device 10400000.mbox-uio.
+      metal: info:      metal_uio_dev_open: No IRQ for device 11010000.cpg-uio.
+      [211] Successfully probed IPI device
+      metal: info:      metal_uio_dev_open: No IRQ for device 42f00000.rsctbl.
+      [211] Successfully open uio device: 42f00000.rsctbl.
+      [211] Successfully added memory device 42f00000.rsctbl.
+      metal: info:      metal_uio_dev_open: No IRQ for device 43000000.vring-ctl0.
+      [211] Successfully open uio device: 43000000.vring-ctl0.
+      [211] Successfully added memory device 43000000.vring-ctl0.
+      metal: info:      metal_uio_dev_open: No IRQ for device 43200000.vring-shm0.
+      [211] Successfully open uio device: 43200000.vring-shm0.
+      [211] Successfully added memory device 43200000.vring-shm0.
+      metal: info:      metal_uio_dev_open: No IRQ for device 43100000.vring-ctl1.
+      [211] Successfully open uio device: 43100000.vring-ctl1.
+      [211] Successfully added memory device 43100000.vring-ctl1.
+      metal: info:      metal_uio_dev_open: No IRQ for device 43500000.vring-shm1.
+      [211] Successfully open uio device: 43500000.vring-shm1.
+      [211] Successfully added memory device 43500000.vring-shm1.
+      metal: info:      metal_uio_dev_open: No IRQ for device 42f01000.mhu-shm.
+      [211] Successfully open uio device: 42f01000.mhu-shm.
+      [211] Successfully added memory device 42f01000.mhu-shm.
+      [211] Initialize remoteproc successfully.
+      [211] proc_id:1 rsc_id:1 mbx_id:0
+      [211] Initialize remoteproc successfully.
+      [211] proc_id:0 rsc_id:0 mbx_id:1
+      [211] Initialize remoteproc successfully.
+      [211] proc_id:1 rsc_id:1 mbx_id:1
+      [211] Initialize remoteproc successfully.
+      [217] thread start
+      [CM33] creating remoteproc virtio
+      [CM33] initializing rpmsg shared buffer pool
+      [CM33] initializing rpmsg vdev
+      [CM33]  1 - Send data to remote core, retrieve the echo and validate its integrity ..
+      [CM33] Remote proc init.
+      [CM33] RPMSG endpoint has created. rp_ept:0xffff9c86f870
+      [CM33] register sig:2 succeeded.
+      [CM33] register sig:15 succeeded.
+      [CM33] RPMSG service has created.
+      [CM33] sending payload number 0 of size 17
+      [CM33]  received payload number 0 of size 17
+      [CM33] sending payload number 1 of size 18
+      [CM33]  received payload number 1 of size 18
+
+      [snip]
+
+      [CM33] sending payload number 471 of size 488
+      [CM33]  received payload number 471 of size 488
+      [CM33] ************************************
+      [CM33]  Test Results: Error count = 0
+      [CM33] ************************************
+      [CM33] Quitting application .. Echo test end
+      [CM33] Stopping application...
+      [211] 42f00000.rsctbl closed
+      [211] 43000000.vring-ctl0 closed
+      [211] 43200000.vring-shm0 closed
+      [211] 43100000.vring-ctl1 closed
+      [211] 43500000.vring-shm1 closed
+      [211] 42f01000.mhu-shm closed
+
+Zephyr console
+==============
+
+The following message will appear on the Zephyr console.
+
+   .. code-block:: console
+
+      *** Booting Zephyr OS build zephyr-v#.#.#-####-g########## ***
+      I: Starting application..!
+      I: Starting application threads!
+      I: OpenAMP[remote]  linux responder demo started
+      I: new_service_cb: message received from service rpmsg-service-0
+      I: OpenAMP[remote] Linux sample client responder started
+      I: OpenAMP demo ended
+      I: OpenAMP Linux sample client responder ended
diff --git a/samples/boards/renesas/openamp_linux_zephyr/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/samples/boards/renesas/openamp_linux_zephyr/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
new file mode 100644
index 00000000000..4c78b84427d
--- /dev/null
+++ b/samples/boards/renesas/openamp_linux_zephyr/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2024 Epam Systems
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	/*
+	 * Allocating whole openamp region as reserved memory
+	 * to save MPU entries
+	 */
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		openamp_shm: memory-region@62F00000 {
+			compatible = "zephyr,memory-region";
+			reg = <0x62F00000 0x600000>;
+			zephyr,memory-region = "openamp_memory";
+			zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
+		};
+	};
+
+	chosen {
+		zephyr,ipc_shm = &vring_shm0;
+		zephyr,ipc = &mbox_consumer;
+	};
+
+	vring_ctrl0: memory@63000000 {
+		compatible = "mmio-sram";
+		reg = <0x63000000 0x50000>;
+	};
+
+	vring_ctrl1: memory@63050000 {
+		compatible = "mmio-sram";
+		reg = <0x63050000 0x50000>;
+	};
+
+	vring_shm0: memory@63200000 {
+		compatible = "mmio-sram";
+		reg = <0x63200000 0x300000>;
+	};
+
+	rsctbl: memory@62F00000 {
+		compatible = "mmio-sram";
+		reg = <0x62F00000 0x1000>;
+	};
+
+	mhu1_shm: memory@62F01008 {
+		compatible = "mmio-sram";
+		reg = <0x62F01008 0x8>;
+	};
+
+	mhu3_shm: memory@62F01018 {
+		compatible = "mmio-sram";
+		reg = <0x62F01018 0x8>;
+	};
+
+	mhu4_shm: memory@62F01020 {
+		compatible = "mmio-sram";
+		reg = <0x62F01020 0x8>;
+	};
+
+	mhu5_shm: memory@62F01028 {
+		compatible = "mmio-sram";
+		reg = <0x62F01028 0x8>;
+	};
+
+	mbox_consumer: mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox1 1>, <&mbox1 0>;
+		mbox-names = "tx", "rx";
+	};
+
+};
+
+&mbox1 {
+	shared-memory = <&mhu1_shm>;
+	status = "okay";
+};
diff --git a/samples/boards/renesas/openamp_linux_zephyr/prj.conf b/samples/boards/renesas/openamp_linux_zephyr/prj.conf
new file mode 100644
index 00000000000..2264866c65e
--- /dev/null
+++ b/samples/boards/renesas/openamp_linux_zephyr/prj.conf
@@ -0,0 +1,7 @@
+CONFIG_KERNEL_BIN_NAME="openamp_linux_zephyr"
+CONFIG_LOG=y
+CONFIG_LOG_MODE_MINIMAL=y
+CONFIG_MBOX=y
+CONFIG_HEAP_MEM_POOL_SIZE=16384
+CONFIG_OPENAMP=y
+CONFIG_OPENAMP_RSC_TABLE=n
diff --git a/samples/boards/renesas/openamp_linux_zephyr/sample.yaml b/samples/boards/renesas/openamp_linux_zephyr/sample.yaml
new file mode 100644
index 00000000000..31c68f14575
--- /dev/null
+++ b/samples/boards/renesas/openamp_linux_zephyr/sample.yaml
@@ -0,0 +1,14 @@
+sample:
+  description: Enable message exchange between two cores, with the application core running Linux
+   and the real-time core running Zephyr, using the OpenAMP library.
+  name: OpenAMP Linux Zephyr RPMsg
+tests:
+  sample.boards.renesas.openamp_linux_zephyr:
+    build_only: true
+    platform_allow:
+      - rzg3s_smarc/r9a08g045s33gbg/cm33
+    integration_platforms:
+      - rzg3s_smarc/r9a08g045s33gbg/cm33
+    tags:
+      - mbox
+      - openamp
diff --git a/samples/boards/renesas/openamp_linux_zephyr/src/main_remote.c b/samples/boards/renesas/openamp_linux_zephyr/src/main_remote.c
new file mode 100644
index 00000000000..49df6c27c33
--- /dev/null
+++ b/samples/boards/renesas/openamp_linux_zephyr/src/main_remote.c
@@ -0,0 +1,371 @@
+/*
+ * Copyright (c) 2024 EPAM Systems
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <string.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <zephyr/drivers/mbox.h>
+
+#include <openamp/open_amp.h>
+#include <metal/device.h>
+#include "resource_table.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(openamp_rsc_table);
+
+#define SHM_DEVICE_NAME "shm"
+
+#if !DT_HAS_CHOSEN(zephyr_ipc_shm)
+#error "Sample requires definition of shared memory for rpmsg"
+#endif
+
+#define APP_EPT_ADDR 1024
+
+#define SHUTDOWN_MSG (0xEF56A55A)
+
+/* Constants derived from device tree */
+#define SHM_NODE       DT_CHOSEN(zephyr_ipc_shm)
+#define SHM_START_ADDR DT_REG_ADDR(SHM_NODE)
+#define SHM_SIZE       DT_REG_SIZE(SHM_NODE)
+
+#define RSC_TABLE_ADDR DT_REG_ADDR(DT_NODELABEL(rsctbl))
+
+#define APP_TASK_STACK_SIZE (1024)
+
+K_THREAD_STACK_DEFINE(thread_mng_stack, APP_TASK_STACK_SIZE);
+K_THREAD_STACK_DEFINE(thread_rp__client_stack, APP_TASK_STACK_SIZE);
+
+static struct k_thread thread_mng_data;
+static struct k_thread thread_rp__client_data;
+
+const struct mbox_dt_spec tx_channel = MBOX_DT_SPEC_GET(DT_CHOSEN(zephyr_ipc), tx);
+const struct mbox_dt_spec rx_channel = MBOX_DT_SPEC_GET(DT_CHOSEN(zephyr_ipc), rx);
+
+static metal_phys_addr_t shm_physmap = CM33_TO_A55_ADDR_NS(SHM_START_ADDR);
+static metal_phys_addr_t rsc_physmap = RSC_TABLE_ADDR;
+
+struct metal_device shm_device = {
+	.name = SHM_DEVICE_NAME,
+	.num_regions = 2,
+	{
+		{.virt = NULL}, /* shared memory */
+		{.virt = NULL}, /* rsc_table memory */
+	},
+	.node = {NULL},
+	.irq_num = 0,
+
+};
+
+struct rpmsg_rcv_msg {
+	void *data;
+	size_t len;
+};
+
+static struct metal_io_region *shm_io;
+static struct rpmsg_virtio_shm_pool shpool;
+
+static struct metal_io_region *rsc_io;
+static struct rpmsg_virtio_device rvdev;
+
+static void *rsc_table;
+static struct rpmsg_device *rpdev;
+
+static char rx_sc_msg[512];
+static struct rpmsg_endpoint sc_ept;
+static struct rpmsg_rcv_msg sc_msg = {.data = rx_sc_msg};
+
+static K_SEM_DEFINE(data_sem, 0, 1);
+static K_SEM_DEFINE(data_sc_sem, 0, 1);
+
+static volatile int finish;
+
+static void platform_mbox_callback(const struct device *dev, mbox_channel_id_t channel_id,
+				   void *user_data, struct mbox_msg *data)
+{
+	k_sem_give(&data_sem);
+}
+
+static int rpmsg_recv_cs_callback(struct rpmsg_endpoint *ept, void *data, size_t len, uint32_t src,
+				  void *priv)
+{
+	memcpy(sc_msg.data, data, len);
+	sc_msg.len = len;
+	if ((*(unsigned int *)data) == SHUTDOWN_MSG) {
+		finish = 1;
+	}
+	k_sem_give(&data_sc_sem);
+
+	return RPMSG_SUCCESS;
+}
+
+static void receive_message(unsigned char **msg, unsigned int *len)
+{
+	int status = k_sem_take(&data_sem, K_FOREVER);
+
+	if (status == 0) {
+		rproc_virtio_notified(rvdev.vdev, VRING1_ID);
+	}
+}
+
+static void new_service_cb(struct rpmsg_device *rdev, const char *name, uint32_t src)
+{
+	LOG_INF("%s: message received from service %s", __func__, name);
+}
+
+int mailbox_notify(void *priv, uint32_t id)
+{
+	ARG_UNUSED(priv);
+
+	mbox_send_dt(&tx_channel, NULL);
+	return 0;
+}
+
+int platform_init(void)
+{
+	void *rsc_tab_addr;
+	int rsc_size;
+	struct metal_device *device;
+	struct metal_init_params metal_params = METAL_INIT_DEFAULTS;
+	int status;
+
+	status = metal_init(&metal_params);
+	if (status) {
+		LOG_ERR("metal_init: failed: %d", status);
+		return -1;
+	}
+
+	status = metal_register_generic_device(&shm_device);
+	if (status) {
+		LOG_ERR("Couldn't register shared memory: %d", status);
+		return -1;
+	}
+
+	status = metal_device_open("generic", SHM_DEVICE_NAME, &device);
+	if (status) {
+		LOG_ERR("metal_device_open failed: %d", status);
+		return -1;
+	}
+
+	/* declare shared memory region */
+	metal_io_init(&device->regions[0], (void *)SHM_START_ADDR, &shm_physmap, SHM_SIZE, -1, 0,
+		      NULL);
+
+	shm_io = metal_device_io_region(device, 0);
+	if (!shm_io) {
+		LOG_ERR("Failed to get shm_io region");
+		return -1;
+	}
+
+	/* declare resource table region */
+	rsc_table_get(&rsc_tab_addr, &rsc_size);
+	memcpy((void *)RSC_TABLE_ADDR, rsc_tab_addr, rsc_size);
+	rsc_table = (struct st_resource_table *)RSC_TABLE_ADDR;
+
+	metal_io_init(&device->regions[1], (void *)RSC_TABLE_ADDR, &rsc_physmap, rsc_size, -1, 0,
+		      NULL);
+
+	rsc_io = metal_device_io_region(device, 1);
+	if (!rsc_io) {
+		LOG_ERR("Failed to get rsc_io region");
+		return -1;
+	}
+
+	/* Setup MBOX */
+	if (!mbox_is_ready_dt(&tx_channel)) {
+		LOG_ERR("MBOX TX device is not ready");
+		return -1;
+	}
+
+	if (!mbox_is_ready_dt(&rx_channel)) {
+		LOG_ERR("MBOX RX device is not ready");
+		return -1;
+	}
+
+	mbox_register_callback_dt(&rx_channel, platform_mbox_callback, NULL);
+
+	status = mbox_set_enabled_dt(&rx_channel, true);
+	if (status) {
+		LOG_ERR("mbox_set_enabled_dt failed");
+		return -1;
+	}
+
+	return 0;
+}
+
+static void platform_deinit(void)
+{
+	mbox_set_enabled_dt(&rx_channel, false);
+
+	metal_finish();
+}
+
+static void cleanup_system(void)
+{
+	struct fw_resource_table *rsc_tbl = (struct fw_resource_table *)RSC_TABLE_ADDR;
+
+	rpmsg_deinit_vdev(&rvdev);
+	rproc_virtio_remove_vdev(rvdev.vdev);
+	/*
+	 * Clean vdev status in rsc_table because it may not be cleared from
+	 * master end. This is not default work behavior. By default rsc_table
+	 * should be provided and managed by master.
+	 */
+	rsc_tbl->vdev.status = 0;
+}
+
+struct rpmsg_device *platform_create_rpmsg_vdev(unsigned int vdev_index, unsigned int role,
+						void (*rst_cb)(struct virtio_device *vdev),
+						rpmsg_ns_bind_cb ns_cb)
+{
+	struct fw_rsc_vdev_vring *vring_rsc;
+	struct virtio_device *vdev;
+	int ret;
+
+	vdev = rproc_virtio_create_vdev(VIRTIO_DEV_DEVICE, VDEV_ID, rsc_table_to_vdev(rsc_table),
+					rsc_io, NULL, mailbox_notify, NULL);
+
+	if (!vdev) {
+		LOG_ERR("failed to create vdev");
+		return NULL;
+	}
+
+	/* Set gfeatures because they should be equal to dfeatures
+	 * when create_ept is called. As rproc_virtio_create_vdev
+	 * doesn't set them because its VIRTIO_DEVICE not DRIVER.
+	 * Assume the virtio driver support all remote features.
+	 */
+	virtio_set_features(vdev, 0x1);
+
+	/* wait master rpmsg init completion */
+	rproc_virtio_wait_remote_ready(vdev);
+
+	vring_rsc = rsc_table_get_vring0(rsc_table);
+
+	ret = rproc_virtio_init_vring(vdev, 0, vring_rsc->notifyid, (void *)VRING_TX_ADDR_CM33,
+				      rsc_io, vring_rsc->num, vring_rsc->align);
+	if (ret) {
+		LOG_ERR("failed to init vring 0");
+		goto failed;
+	}
+
+	vring_rsc = rsc_table_get_vring1(rsc_table);
+
+	ret = rproc_virtio_init_vring(vdev, 1, vring_rsc->notifyid, (void *)VRING_RX_ADDR_CM33,
+				      rsc_io, vring_rsc->num, vring_rsc->align);
+	if (ret) {
+		LOG_ERR("failed to init vring 1");
+		goto failed;
+	}
+
+	rpmsg_virtio_init_shm_pool(&shpool, NULL, SHM_SIZE);
+	ret = rpmsg_init_vdev(&rvdev, vdev, ns_cb, shm_io, &shpool);
+
+	if (ret) {
+		LOG_ERR("failed rpmsg_init_vdev");
+		goto failed;
+	}
+
+	return rpmsg_virtio_get_rpmsg_device(&rvdev);
+
+failed:
+	rproc_virtio_remove_vdev(vdev);
+
+	return NULL;
+}
+
+void app_rpmsg_client_sample(void *arg1, void *arg2, void *arg3)
+{
+	ARG_UNUSED(arg1);
+	ARG_UNUSED(arg2);
+	ARG_UNUSED(arg3);
+	unsigned int msg_cnt = 0;
+	int ret = 0;
+
+	k_sem_take(&data_sc_sem, K_FOREVER);
+
+	LOG_INF("OpenAMP[remote] Linux sample client responder started");
+
+	ret = rpmsg_create_ept(&sc_ept, rpdev, "rpmsg-service-0", APP_EPT_ADDR, RPMSG_ADDR_ANY,
+			       rpmsg_recv_cs_callback, NULL);
+
+	while (!finish) {
+		k_sem_take(&data_sc_sem, K_FOREVER);
+		msg_cnt++;
+		rpmsg_send(&sc_ept, sc_msg.data, sc_msg.len);
+	}
+
+	rpmsg_destroy_ept(&sc_ept);
+	k_sem_reset(&data_sc_sem);
+
+	LOG_INF("OpenAMP Linux sample client responder ended");
+}
+
+void rpmsg_mng_task(void *arg1, void *arg2, void *arg3)
+{
+	ARG_UNUSED(arg1);
+	ARG_UNUSED(arg2);
+	ARG_UNUSED(arg3);
+	unsigned char *msg;
+	unsigned int len;
+	int ret = 0;
+
+	LOG_INF("OpenAMP[remote]  linux responder demo started");
+
+	/* Initialize platform */
+	rpdev = platform_create_rpmsg_vdev(0, VIRTIO_DEV_DEVICE, NULL, new_service_cb);
+	if (!rpdev) {
+		LOG_ERR("Failed to create rpmsg virtio device");
+		ret = -1;
+		goto task_end;
+	}
+
+	/* start the rpmsg clients */
+	k_sem_give(&data_sc_sem);
+
+	while (!finish) {
+		receive_message(&msg, &len);
+	}
+
+task_end:
+	cleanup_system();
+
+	LOG_INF("OpenAMP demo ended");
+}
+
+int main(void)
+{
+	LOG_INF("Starting application..!");
+
+	/* Initialize platform */
+	int ret = platform_init();
+
+	if (ret) {
+		LOG_ERR("Failed to initialize platform");
+		return -1;
+	}
+
+	while (1) {
+		finish = 0;
+
+		LOG_INF("Starting application threads!");
+		k_thread_create(&thread_mng_data, thread_mng_stack, APP_TASK_STACK_SIZE,
+				(k_thread_entry_t)rpmsg_mng_task, NULL, NULL, NULL, K_PRIO_COOP(8),
+				0, K_NO_WAIT);
+		k_thread_create(&thread_rp__client_data, thread_rp__client_stack,
+				APP_TASK_STACK_SIZE, (k_thread_entry_t)app_rpmsg_client_sample,
+				NULL, NULL, NULL, K_PRIO_COOP(7), 0, K_NO_WAIT);
+
+		k_thread_join(&thread_mng_data, K_FOREVER);
+		k_thread_join(&thread_rp__client_data, K_FOREVER);
+	}
+
+	platform_deinit();
+	return 0;
+}
diff --git a/samples/boards/renesas/openamp_linux_zephyr/src/resource_table.c b/samples/boards/renesas/openamp_linux_zephyr/src/resource_table.c
new file mode 100644
index 00000000000..8f50e2d944b
--- /dev/null
+++ b/samples/boards/renesas/openamp_linux_zephyr/src/resource_table.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2024 EPAM Systems
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Overriding Zephyr resource_table and set correct vring 0 and vring 1 addresses
+ * to match the work behaviour of master device. According to the commit:
+ * 25ec73986b (lib: open-amp: add helper to add resource table in project)
+ * vring RX and TX addresses should be allocated by master processor.
+ * Current Master Sample implementation expects slave to provide valid
+ * rsc_table so update vring addresses here.
+ *
+ * Dependencies:
+ *   to be compliant with Linux kernel OS the resource table must be linked in a
+ *   specific section named ".resource_table".
+ */
+
+#include <zephyr/kernel.h>
+#include <resource_table.h>
+
+#define __resource Z_GENERIC_SECTION(.resource_table)
+
+static struct fw_resource_table __resource resource_table = {
+	.ver = 1,
+	.num = RSC_TABLE_NUM_ENTRY,
+	.reserved = {0, 0},
+	/* Offset */
+	{
+		offsetof(struct fw_resource_table, vdev),
+	},
+	/* Virtio device entry */
+	{
+		RSC_VDEV,
+		VIRTIO_ID_RPMSG,
+		0,
+		RPMSG_IPU_C0_FEATURES,
+		0,
+		0,
+		0,
+		VRING_COUNT,
+		{0, 0},
+	},
+	/* Vring rsc entry - part of vdev rsc entry */
+	.vring0 = {VRING_TX_ADDR_A55, VRING_ALIGNMENT, RSC_TABLE_NUM_RPMSG_BUFF, VRING0_ID, 0},
+	.vring1 = {VRING_RX_ADDR_A55, VRING_ALIGNMENT, RSC_TABLE_NUM_RPMSG_BUFF, VRING1_ID, 0},
+};
+
+void rsc_table_get(void **table_ptr, int *length)
+{
+	*table_ptr = (void *)&resource_table;
+	*length = sizeof(resource_table);
+}
diff --git a/samples/boards/renesas/openamp_linux_zephyr/src/resource_table.h b/samples/boards/renesas/openamp_linux_zephyr/src/resource_table.h
new file mode 100644
index 00000000000..5c950097f6b
--- /dev/null
+++ b/samples/boards/renesas/openamp_linux_zephyr/src/resource_table.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2024 EPAM Systems
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef RESOURCE_TABLE_H__
+#define RESOURCE_TABLE_H__
+
+#include <openamp/remoteproc.h>
+#include <openamp/virtio.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define VDEV_ID   0xFF
+#define VRING0_ID 0
+#define VRING1_ID 1
+
+#define VRING_COUNT           2
+#define RPMSG_IPU_C0_FEATURES 1
+
+#define R_VRING_TX         DT_NODELABEL(vring_ctrl0)
+#define R_VRING_RX         DT_NODELABEL(vring_ctrl1)
+#define VRING_TX_ADDR_CM33 DT_REG_ADDR(R_VRING_TX)
+#define VRING_RX_ADDR_CM33 DT_REG_ADDR(R_VRING_RX)
+
+/*
+ * Macro to convert across CM33/CM33_FPU and A55 address spaces
+ * This macro are designed to convert CM33 addresses to A55 addresses
+ * in secure and non-secure space. According to Table 5.2 of HW Manual.
+ */
+#ifndef _ASMLANGUAGE
+
+#define CM33_ADDRESS_OFFSET_SECURE    (0x30000000)
+#define CM33_ADDRESS_OFFSET_NONSECURE (0x20000000)
+#define CM33_TO_A55_ADDR_S(x)         ((x) - CM33_ADDRESS_OFFSET_SECURE)
+#define CM33_TO_A55_ADDR_NS(x)        ((x) - CM33_ADDRESS_OFFSET_NONSECURE)
+
+#endif
+/* End of convert macro */
+
+#define VRING_TX_ADDR_A55 CM33_TO_A55_ADDR_NS(VRING_TX_ADDR_CM33)
+#define VRING_RX_ADDR_A55 CM33_TO_A55_ADDR_NS(VRING_RX_ADDR_CM33)
+#define VRING_ALIGNMENT   (0x100U)
+
+#define RSC_TABLE_NUM_RPMSG_BUFF 512
+
+enum rsc_table_entries {
+	RSC_TABLE_VDEV_ENTRY,
+	RSC_TABLE_NUM_ENTRY
+};
+
+struct fw_resource_table {
+	unsigned int ver;
+	unsigned int num;
+	unsigned int reserved[2];
+	unsigned int offset[RSC_TABLE_NUM_ENTRY];
+
+	struct fw_rsc_vdev vdev;
+	struct fw_rsc_vdev_vring vring0;
+	struct fw_rsc_vdev_vring vring1;
+} METAL_PACKED_END;
+
+void rsc_table_get(void **table_ptr, int *length);
+
+static inline struct fw_rsc_vdev *rsc_table_to_vdev(void *rsc_table)
+{
+	return &((struct fw_resource_table *)rsc_table)->vdev;
+}
+
+static inline struct fw_rsc_vdev_vring *rsc_table_get_vring0(void *rsc_table)
+{
+	return &((struct fw_resource_table *)rsc_table)->vring0;
+}
+
+static inline struct fw_rsc_vdev_vring *rsc_table_get_vring1(void *rsc_table)
+{
+	return &((struct fw_resource_table *)rsc_table)->vring1;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/samples/boards/st/backup_sram/sample.yaml b/samples/boards/st/backup_sram/sample.yaml
index 8c22ee9566b..2a73295db8d 100644
--- a/samples/boards/st/backup_sram/sample.yaml
+++ b/samples/boards/st/backup_sram/sample.yaml
@@ -6,3 +6,7 @@ tests:
     depends_on: backup_sram
     build_only: true
     filter: dt_compat_enabled("st,stm32-backup-sram")
+    vendor_allow:
+      - st
+    integration_platforms:
+      - nucleo_f207zg/stm32f207xx
diff --git a/samples/boards/st/bluetooth/interactive_gui/src/main.c b/samples/boards/st/bluetooth/interactive_gui/src/main.c
index 9b31a1e69ff..56ef463c761 100644
--- a/samples/boards/st/bluetooth/interactive_gui/src/main.c
+++ b/samples/boards/st/bluetooth/interactive_gui/src/main.c
@@ -51,7 +51,7 @@ static K_FIFO_DEFINE(uart_tx_queue);
 #define ST_DISCARD	3 /* Dropping packet. */
 
 /* Length of a discard/flush buffer.
- * This is sized to align with a BLE HCI packet:
+ * This is sized to align with a Bluetooth HCI packet:
  * 1 byte H:4 header + 32 bytes ACL/event data
  * Bigger values might overflow the stack since this is declared as a local
  * variable, smaller ones will force the caller to call into discard more
diff --git a/samples/boards/st/ccm/src/main.c b/samples/boards/st/ccm/src/main.c
index 8cd888641b7..36630d02858 100644
--- a/samples/boards/st/ccm/src/main.c
+++ b/samples/boards/st/ccm/src/main.c
@@ -125,7 +125,7 @@ int main(void)
 	printf("Initialised DATA area     : [%p, %p)\n",
 		&__ccm_data_start, &__ccm_data_end);
 	printf("Start of DATA in FLASH    : %p\n",
-		&__ccm_data_rom_start);
+		&__ccm_data_load_start);
 
 	check_initial_var_values();
 
diff --git a/samples/boards/st/h7_dual_core/sample.yaml b/samples/boards/st/h7_dual_core/sample.yaml
index 08ffab25c48..9b3e2b11e07 100644
--- a/samples/boards/st/h7_dual_core/sample.yaml
+++ b/samples/boards/st/h7_dual_core/sample.yaml
@@ -3,6 +3,9 @@ sample:
   name: stm32_h7_dual_core
 tests:
   sample.boards.stm32.h7_dual_core:
-    depends_on: mailbox
     build_only: true
+    vendor_allow:
+      - st
     filter: dt_compat_enabled("st,stm32-hsem-mailbox")
+    integration_platforms:
+      - stm32h747i_disco/stm32h747xx/m4
diff --git a/samples/boards/st/mco/boards/nucleo_f411re.overlay b/samples/boards/st/mco/boards/nucleo_f411re.overlay
index 3e71e127fd0..7c83914b2c0 100644
--- a/samples/boards/st/mco/boards/nucleo_f411re.overlay
+++ b/samples/boards/st/mco/boards/nucleo_f411re.overlay
@@ -8,6 +8,11 @@
 	status = "okay";
 };
 
+/* Enable HSI as it will be output on MCO pin by this sample */
+&clk_hsi {
+	status = "okay";
+};
+
 /* see RefMan RM0383 */
 &mco1 {
 	/* Select One of the line below for clock source */
diff --git a/samples/boards/st/mco/boards/nucleo_wba55cg.overlay b/samples/boards/st/mco/boards/nucleo_wba55cg.overlay
new file mode 100644
index 00000000000..328e5058a98
--- /dev/null
+++ b/samples/boards/st/mco/boards/nucleo_wba55cg.overlay
@@ -0,0 +1,30 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 STMicroelectronics
+ */
+
+/* The clock that is output must be enabled. */
+&clk_lse {
+	status = "okay";
+};
+
+/ {
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+	};
+};
+
+&usart1 {
+	/* Do not use the console RX pin : dedicated to the MCO */
+	pinctrl-0 = <&usart1_tx_pb12 &analog_pa8>;
+};
+
+&mco1 {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_LSE MCO1_SEL(MCO_SEL_LSE)>;
+	prescaler = <MCO1_PRE(MCO_PRE_DIV_2)>;
+	pinctrl-0 = <&rcc_mco_pa8>;
+	pinctrl-names = "default";
+};
diff --git a/samples/boards/st/mco/boards/nucleo_wl55jc.overlay b/samples/boards/st/mco/boards/nucleo_wl55jc.overlay
new file mode 100644
index 00000000000..fced2482454
--- /dev/null
+++ b/samples/boards/st/mco/boards/nucleo_wl55jc.overlay
@@ -0,0 +1,18 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 STMicroelectronics
+ */
+
+/* Enable the clock we are going to output */
+&clk_lse {
+	status = "okay";
+};
+
+&mco1 {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_LSE MCO1_SEL(MCO_SEL_LSE)>;
+	prescaler = <MCO1_PRE(MCO_PRE_DIV_1)>;
+	pinctrl-0 = <&rcc_mco_pa8>;
+	pinctrl-names = "default";
+};
diff --git a/samples/boards/st/mco/sample.yaml b/samples/boards/st/mco/sample.yaml
index 6d052cae771..77dda18c803 100644
--- a/samples/boards/st/mco/sample.yaml
+++ b/samples/boards/st/mco/sample.yaml
@@ -2,11 +2,14 @@ sample:
   name: STM32 microcontroller clock output (MCO) example
 tests:
   sample.board.stm32.mco:
+    build_only: true
     platform_allow:
       - nucleo_f411re
       - nucleo_f446ze
       - stm32f746g_disco
       - nucleo_u5a5zj_q
+      - nucleo_wba55cg
+      - nucleo_wl55jc
     integration_platforms:
       - stm32f746g_disco
     tags: board
diff --git a/samples/boards/st/power_mgmt/adc/boards/nucleo_wba52cg.overlay b/samples/boards/st/power_mgmt/adc/boards/nucleo_wba55cg.overlay
similarity index 100%
rename from samples/boards/st/power_mgmt/adc/boards/nucleo_wba52cg.overlay
rename to samples/boards/st/power_mgmt/adc/boards/nucleo_wba55cg.overlay
diff --git a/samples/boards/st/power_mgmt/blinky/README.rst b/samples/boards/st/power_mgmt/blinky/README.rst
index 6e2920ca0ec..0d114180c42 100644
--- a/samples/boards/st/power_mgmt/blinky/README.rst
+++ b/samples/boards/st/power_mgmt/blinky/README.rst
@@ -31,7 +31,7 @@ Building and Running
 Build and flash Blinky as follows, changing ``stm32l562e_dk`` for your board:
 
 .. zephyr-app-commands::
-   :zephyr-app: samples/basic/blinky
+   :zephyr-app: samples/boards/st/power_mgmt/blinky
    :board: stm32l562e_dk
    :goals: build flash
    :compact:
diff --git a/samples/boards/st/power_mgmt/stm32wb_ble/src/main.c b/samples/boards/st/power_mgmt/stm32wb_ble/src/main.c
index faabd4eda30..659c7016cf5 100644
--- a/samples/boards/st/power_mgmt/stm32wb_ble/src/main.c
+++ b/samples/boards/st/power_mgmt/stm32wb_ble/src/main.c
@@ -122,7 +122,7 @@ int main(void)
 	/* Give time to bt_ready sequence */
 	k_sleep(K_SECONDS(6));
 
-	printk("BLE disable\n");
+	printk("Bluetooth disable\n");
 	err = bt_disable();
 	if (err) {
 		printk("Bluetooth disable failed (err %d)\n", err);
@@ -130,7 +130,7 @@ int main(void)
 
 	k_sleep(K_SECONDS(2));
 
-	printk("BLE restart\n");
+	printk("Bluetooth restart\n");
 	/* Initialize the Bluetooth Subsystem */
 	err = bt_enable(bt_ready);
 	if (err) {
@@ -140,7 +140,7 @@ int main(void)
 	/* Give time to bt_ready sequence */
 	k_sleep(K_SECONDS(6));
 
-	printk("BLE disable\n");
+	printk("Bluetooth disable\n");
 	err = bt_disable();
 	if (err) {
 		printk("Bluetooth disable failed (err %d)\n", err);
diff --git a/samples/boards/st/uart/circular_dma/CMakeLists.txt b/samples/boards/st/uart/circular_dma/CMakeLists.txt
new file mode 100644
index 00000000000..375342e5943
--- /dev/null
+++ b/samples/boards/st/uart/circular_dma/CMakeLists.txt
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(circular_dma)
+
+target_sources(app PRIVATE src/main.c)
diff --git a/samples/boards/st/uart/circular_dma/README.rst b/samples/boards/st/uart/circular_dma/README.rst
new file mode 100644
index 00000000000..d4c448670c0
--- /dev/null
+++ b/samples/boards/st/uart/circular_dma/README.rst
@@ -0,0 +1,49 @@
+.. zephyr:code-sample:: uart-circular-dma
+   :name: UART circular mode
+   :relevant-api: uart_interface
+
+   Read data from the console and echo it back using a circular DMA configuration.
+
+Overview
+********
+
+This sample demonstrates how to use STM32 UART serial driver with DMA in circular mode.
+It reads data from the console and echoes it back.
+
+By default, the UART peripheral that is normally assigned to the Zephyr shell
+is used, hence the majority of boards should be able to run this sample.
+
+Building and Running
+********************
+
+Build and flash the sample as follows, changing ``nucleo_g071rb`` for
+your board:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/boards/st/uart/circular_dma
+   :board: nucleo_g071rb
+   :goals: build flash
+   :compact:
+
+Sample Output
+=============
+
+.. code-block:: console
+
+    Enter message to fill RX buffer size and press enter :
+    # Type e.g. :
+    # "Lorem Ipsum is simply dummy text of the printing and typesetting industry.
+    # Lorem Ipsum has been the industry's standard dummy text ever since the 1500s,
+    # when an unknown printer took a galley of type and scrambled it to make a type specimen book.
+    # It has survived not only five centuries, but also the leap into electronic typesetting,
+    # remaining essentially unchanged. It was popularised in the 1960s with the release of Letraset
+    # sheets containing Lorem Ipsum passages, and more recently with desktop publishing software
+    # like Aldus PageMaker including versions of Lorem Ipsum."
+
+    Lorem Ipsum is simply dummy text of the printing and typesetting industry.
+    Lorem Ipsum has been the industry's standard dummy text ever since the 1500s,
+    when an unknown printer took a galley of type and scrambled it to make a type specimen book.
+    It has survived not only five centuries, but also the leap into electronic typesetting,
+    remaining essentially unchanged. It was popularised in the 1960s with the release of Letraset
+    sheets containing Lorem Ipsum passages, and more recently with desktop publishing software
+    like Aldus PageMaker including versions of Lorem Ipsum.
diff --git a/samples/boards/st/uart/circular_dma/boards/nucleo_c031c6.overlay b/samples/boards/st/uart/circular_dma/boards/nucleo_c031c6.overlay
new file mode 100644
index 00000000000..de7d0772e51
--- /dev/null
+++ b/samples/boards/st/uart/circular_dma/boards/nucleo_c031c6.overlay
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&usart2 {
+	dmas = <&dmamux1 0 53 (STM32_DMA_PERIPH_TX)>,
+		<&dmamux1 3 52 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_8BITS | STM32_DMA_MODE_CYCLIC)>;
+	dma-names = "tx", "rx";
+	fifo-enable;
+};
+
+&dma1 {
+	status = "okay";
+};
+
+&dmamux1 {
+	status = "okay";
+};
diff --git a/samples/boards/st/uart/circular_dma/boards/nucleo_f091rc.overlay b/samples/boards/st/uart/circular_dma/boards/nucleo_f091rc.overlay
new file mode 100644
index 00000000000..274b8d1d5b7
--- /dev/null
+++ b/samples/boards/st/uart/circular_dma/boards/nucleo_f091rc.overlay
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&usart2 {
+	dmas = <&dma1 4 (STM32_DMA_PERIPH_TX)>,
+		<&dma1 5 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_8BITS | STM32_DMA_MODE_CYCLIC)>;
+	dma-names = "tx", "rx";
+	fifo-enable;
+};
+
+&dma1 {
+	status = "okay";
+};
diff --git a/samples/boards/st/uart/circular_dma/boards/nucleo_g071rb.overlay b/samples/boards/st/uart/circular_dma/boards/nucleo_g071rb.overlay
new file mode 100644
index 00000000000..de7d0772e51
--- /dev/null
+++ b/samples/boards/st/uart/circular_dma/boards/nucleo_g071rb.overlay
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&usart2 {
+	dmas = <&dmamux1 0 53 (STM32_DMA_PERIPH_TX)>,
+		<&dmamux1 3 52 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_8BITS | STM32_DMA_MODE_CYCLIC)>;
+	dma-names = "tx", "rx";
+	fifo-enable;
+};
+
+&dma1 {
+	status = "okay";
+};
+
+&dmamux1 {
+	status = "okay";
+};
diff --git a/samples/boards/st/uart/circular_dma/boards/nucleo_u575zi_q.overlay b/samples/boards/st/uart/circular_dma/boards/nucleo_u575zi_q.overlay
new file mode 100644
index 00000000000..370cf3def47
--- /dev/null
+++ b/samples/boards/st/uart/circular_dma/boards/nucleo_u575zi_q.overlay
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&usart1 {
+	dmas = <&gpdma1 0 25 (STM32_DMA_PERIPH_TX)
+		&gpdma1 1 24 (STM32_DMA_MODE_CYCLIC | STM32_DMA_PERIPH_RX | STM32_DMA_MEM_8BITS)>;
+	dma-names = "tx", "rx";
+	fifo-enable;
+};
+
+&gpdma1 {
+	status = "okay";
+};
diff --git a/samples/boards/st/uart/circular_dma/boards/nucleo_wba55cg.overlay b/samples/boards/st/uart/circular_dma/boards/nucleo_wba55cg.overlay
new file mode 100644
index 00000000000..751836f8554
--- /dev/null
+++ b/samples/boards/st/uart/circular_dma/boards/nucleo_wba55cg.overlay
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&usart1 {
+	dmas = <&gpdma1 0 12 (STM32_DMA_PERIPH_TX)
+		&gpdma1 1 11 (STM32_DMA_MODE_CYCLIC | STM32_DMA_PERIPH_RX | STM32_DMA_MEM_8BITS)>;
+	dma-names = "tx", "rx";
+	fifo-enable;
+};
+
+&gpdma1 {
+	status = "okay";
+};
diff --git a/samples/boards/st/uart/circular_dma/prj.conf b/samples/boards/st/uart/circular_dma/prj.conf
new file mode 100644
index 00000000000..ad49326a82a
--- /dev/null
+++ b/samples/boards/st/uart/circular_dma/prj.conf
@@ -0,0 +1,3 @@
+CONFIG_SERIAL=y
+CONFIG_UART_ASYNC_API=y
+CONFIG_RING_BUFFER=y
diff --git a/samples/boards/st/uart/circular_dma/sample.yaml b/samples/boards/st/uart/circular_dma/sample.yaml
new file mode 100644
index 00000000000..1fa418f0c4e
--- /dev/null
+++ b/samples/boards/st/uart/circular_dma/sample.yaml
@@ -0,0 +1,11 @@
+sample:
+  name: UART driver sample
+tests:
+  sample.boards.stm32.uart.circular_dma:
+    integration_platforms:
+      - nucleo_g071rb
+    tags:
+      - serial
+      - uart
+    filter: dt_chosen_enabled("zephyr,shell-uart") and CONFIG_SOC_FAMILY_STM32
+    harness: keyboard
diff --git a/samples/boards/st/uart/circular_dma/src/main.c b/samples/boards/st/uart/circular_dma/src/main.c
new file mode 100644
index 00000000000..f230a500dc2
--- /dev/null
+++ b/samples/boards/st/uart/circular_dma/src/main.c
@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/uart.h>
+#include <zephyr/sys/ring_buffer.h>
+#include <zephyr/sys/printk.h>
+#include <string.h>
+
+#define RING_BUF_SIZE 1000
+#define RX_BUF_SIZE   10
+
+#define RECEIVE_TIMEOUT 0
+
+#define STACK_SIZE 1024
+
+#define UART_DEVICE_NODE DT_CHOSEN(zephyr_shell_uart)
+
+static const struct device *const uart_dev = DEVICE_DT_GET(UART_DEVICE_NODE);
+
+/* uart configuration structure */
+const struct uart_config uart_cfg = {.baudrate = 115200,
+				     .parity = UART_CFG_PARITY_NONE,
+				     .stop_bits = UART_CFG_STOP_BITS_1,
+				     .data_bits = UART_CFG_DATA_BITS_8,
+				     .flow_ctrl = UART_CFG_FLOW_CTRL_NONE};
+
+/* define a ring buffer to get raw bytes*/
+RING_BUF_DECLARE(ring_buf, RING_BUF_SIZE);
+
+/* define uart rx buffer */
+static uint8_t rx_buffer[RX_BUF_SIZE];
+
+/* define thread  stack size */
+static K_THREAD_STACK_DEFINE(uart_rx_stack, STACK_SIZE);
+
+/* struct uart_event async_evt */
+static struct k_thread uart_rx_thread_data = {0};
+
+void print_uart(char *buf, int len)
+{
+	for (int i = 0; i < len; i++) {
+
+		if ((buf[i] == '\n' || buf[i] == '\r')) {
+			uart_poll_out(uart_dev, '\n');
+		} else {
+			uart_poll_out(uart_dev, buf[i]);
+		}
+	}
+}
+
+/* Data processing thread */
+static void uart_rx_thread(void *p1, void *p2, void *p3)
+{
+	uint8_t rx_data[RX_BUF_SIZE];
+	size_t len;
+
+	while (1) {
+
+		/* Check if there's data in the ring buffer */
+		len = ring_buf_get(&ring_buf, rx_data, sizeof(rx_data));
+
+		if (len > 0) {
+
+			/* Process `len` bytes of data */
+			print_uart(rx_data, len);
+		}
+	}
+}
+
+void uart_cb(const struct device *dev, struct uart_event *evt, void *user_data)
+{
+	switch (evt->type) {
+	case UART_RX_RDY:
+		/* Data received; place into ring buffer */
+		ring_buf_put(&ring_buf, evt->data.rx.buf + evt->data.rx.offset, evt->data.rx.len);
+
+		break;
+
+	case UART_RX_DISABLED:
+		/* Re-enable RX */
+		uart_rx_enable(uart_dev, rx_buffer, sizeof(rx_buffer), RECEIVE_TIMEOUT);
+
+		break;
+
+	default:
+		break;
+	}
+}
+
+int main(void)
+{
+	if (!uart_dev) {
+		printk("Failed to get UART device");
+		return 1;
+	}
+
+	/* uart configuration parameters */
+	int err = uart_configure(uart_dev, &uart_cfg);
+
+	if (err == -ENOSYS) {
+		printk("Configuration is not supported by device or driver,"
+			" check the UART settings configuration\n");
+		return -ENOSYS;
+	}
+
+	/* Configure uart callback */
+	uart_callback_set(uart_dev, uart_cb, NULL);
+
+	/* enable uart reception */
+	uart_rx_enable(uart_dev, rx_buffer, sizeof(rx_buffer), RECEIVE_TIMEOUT);
+
+	printk("\n Enter message to fill RX buffer size :\n");
+
+	/* start uart data processing thread */
+	k_tid_t tid = k_thread_create(&uart_rx_thread_data, uart_rx_stack,
+				      K_THREAD_STACK_SIZEOF(uart_rx_stack), uart_rx_thread, NULL,
+				      NULL, NULL, 5, 0, K_NO_WAIT);
+	k_thread_name_set(tid, "RX_thread");
+}
diff --git a/samples/boards/st/uart/single_wire/README.rst b/samples/boards/st/uart/single_wire/README.rst
index 09c01c81725..67484bfa596 100644
--- a/samples/boards/st/uart/single_wire/README.rst
+++ b/samples/boards/st/uart/single_wire/README.rst
@@ -7,14 +7,18 @@
 Overview
 ********
 
-A simple application demonstrating how to use the single wire / half-duplex UART
-functionality of STM32. Without adaptions this example runs on STM32F3 discovery
-board. You need to establish a physical connection between pins PA2 (USART2_TX) and
-PC10 (UART4_TX).
-
+A simple application demonstrating how to use the single-wire/half-duplex
+UART functionality of STM32 devices. The example runs on various STM32
+boards with minimal adaptations.
 Add a ``single_wire_uart_loopback`` fixture to your board in the hardware map to allow
 twister to verify this sample's output automatically.
 
+Hardware Setup
+**************
+
+You need to establish a physical connection between UART pins on the board.
+Refer to the specific board overlay file for the exact pin connections.
+
 Building and Running
 ********************
 
diff --git a/samples/boards/st/uart/single_wire/boards/nucleo_wba55cg.overlay b/samples/boards/st/uart/single_wire/boards/nucleo_wba55cg.overlay
new file mode 100644
index 00000000000..375d125fbaa
--- /dev/null
+++ b/samples/boards/st/uart/single_wire/boards/nucleo_wba55cg.overlay
@@ -0,0 +1,36 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 STMicroelectronics
+ */
+
+&usart2 {
+	status = "okay";
+	pinctrl-0 = <&usart2_tx_pa12>;
+	current-speed = <115200>;
+	single-wire;
+};
+
+&lpuart1 {
+	status = "okay";
+	pinctrl-0 = <&lpuart1_tx_pa2>;
+	current-speed = <115200>;
+	single-wire;
+};
+
+&usart2_tx_pa12 {
+	bias-pull-up;
+	drive-open-drain;
+};
+
+&lpuart1_tx_pa2 {
+	bias-pull-up;
+	drive-open-drain;
+};
+
+/ {
+	aliases {
+	single-line-uart1 = &usart2;
+	single-line-uart2 = &lpuart1;
+	};
+};
diff --git a/samples/boards/st/uart/single_wire/sample.yaml b/samples/boards/st/uart/single_wire/sample.yaml
index 6bf267e50a4..9d9bbaa0abe 100644
--- a/samples/boards/st/uart/single_wire/sample.yaml
+++ b/samples/boards/st/uart/single_wire/sample.yaml
@@ -2,7 +2,9 @@ sample:
   name: STM32 Single Wire UART sample
 tests:
   sample.boards.stm32.uart.single_wire:
-    platform_allow: stm32f3_disco
+    platform_allow:
+      - stm32f3_disco
+      - nucleo_wba55cg
     tags:
       - drivers
       - uart
diff --git a/samples/cpp/hello_world/sample.yaml b/samples/cpp/hello_world/sample.yaml
index 244c7b4f345..98ae71ebe83 100644
--- a/samples/cpp/hello_world/sample.yaml
+++ b/samples/cpp/hello_world/sample.yaml
@@ -2,7 +2,9 @@ sample:
   description: Hello World C++ sample, the simplest C++ Zephyr application
   name: hello cpp world
 common:
-  tags: introduction
+  tags:
+    - introduction
+    - cpp
   integration_platforms:
     - qemu_riscv32
   harness: console
diff --git a/samples/drivers/adc/adc_dt/boards/arduino_uno_r4.overlay b/samples/drivers/adc/adc_dt/boards/arduino_uno_r4.overlay
new file mode 100644
index 00000000000..c9a0303f4be
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/arduino_uno_r4.overlay
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&arduino_adc 0>, <&arduino_adc 1>, <&arduino_adc 2>,
+			      <&arduino_adc 3>, <&arduino_adc 4>, <&arduino_adc 5>;
+	};
+};
+
+&adc0 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_VDD_1";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <5000>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_VDD_1";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <5000>;
+	};
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_VDD_1";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <5000>;
+	};
+
+	channel@9 {
+		reg = <9>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_VDD_1";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <5000>;
+	};
+
+	channel@21 {
+		reg = <21>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_VDD_1";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <5000>;
+	};
+
+	channel@22 {
+		reg = <22>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_VDD_1";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <5000>;
+	};
+};
diff --git a/samples/drivers/adc/adc_dt/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/samples/drivers/adc/adc_dt/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..ea775bd1b1e
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,56 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 7>;
+	};
+};
+
+&adc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN4>; /* P1.11 */
+		zephyr,resolution = <10>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN2>; /* P1.06 */
+		zephyr,resolution = <12>;
+		zephyr,oversampling = <8>;
+	};
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_VDD>;
+		zephyr,resolution = <12>;
+		zephyr,oversampling = <8>;
+	};
+
+	channel@7 {
+		reg = <7>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN6>; /* P1.13 */
+		zephyr,input-negative = <NRF_SAADC_AIN7>; /* P1.14 */
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/samples/drivers/adc/adc_dt/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/samples/drivers/adc/adc_dt/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..ea775bd1b1e
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,56 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 7>;
+	};
+};
+
+&adc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN4>; /* P1.11 */
+		zephyr,resolution = <10>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN2>; /* P1.06 */
+		zephyr,resolution = <12>;
+		zephyr,oversampling = <8>;
+	};
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_VDD>;
+		zephyr,resolution = <12>;
+		zephyr,oversampling = <8>;
+	};
+
+	channel@7 {
+		reg = <7>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN6>; /* P1.13 */
+		zephyr,input-negative = <NRF_SAADC_AIN7>; /* P1.14 */
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/samples/drivers/adc/adc_dt/boards/cyw920829m2evk_02.overlay b/samples/drivers/adc/adc_dt/boards/cyw920829m2evk_02.overlay
new file mode 100644
index 00000000000..71b416c018a
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/cyw920829m2evk_02.overlay
@@ -0,0 +1,56 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2023 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>;
+	};
+};
+
+&adc0 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@4 {
+		reg = <4>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 1)>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <16>;
+		zephyr,input-positive = <4>;   /* P3.4 */
+	};
+
+	channel@5 {
+		reg = <5>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 1)>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <16>;
+		zephyr,input-positive = <5>;   /* P3.5 */
+	};
+
+	channel@6 {
+		reg = <6>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 1)>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <16>;
+		zephyr,input-positive = <6>;   /* P3.6 */
+	};
+
+	channel@7 {
+		reg = <7>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 1)>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <16>;
+		zephyr,input-positive = <7>;   /* P3.7 */
+	};
+};
diff --git a/samples/drivers/adc/adc_dt/boards/frdm_mcxa156.conf b/samples/drivers/adc/adc_dt/boards/frdm_mcxa156.conf
deleted file mode 100644
index 6beae3f4655..00000000000
--- a/samples/drivers/adc/adc_dt/boards/frdm_mcxa156.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_LPADC_DO_OFFSET_CALIBRATION=y
diff --git a/samples/drivers/adc/adc_dt/boards/frdm_mcxc444.conf b/samples/drivers/adc/adc_dt/boards/frdm_mcxc444.conf
new file mode 100644
index 00000000000..3201f7a9cc4
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/frdm_mcxc444.conf
@@ -0,0 +1 @@
+CONFIG_ADC_MCUX_ADC16_VREF_ALTERNATE=y
diff --git a/samples/drivers/adc/adc_dt/boards/frdm_mcxc444.overlay b/samples/drivers/adc/adc_dt/boards/frdm_mcxc444.overlay
new file mode 100644
index 00000000000..a20b62decf9
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/frdm_mcxc444.overlay
@@ -0,0 +1,31 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright 2024 NXP
+ */
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&adc0 0>;
+	};
+};
+
+&adc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/*
+	 * To use this sample:
+	 * - Connect ADC0 SE0 signal to voltage between 0~3.3V (J4 pin 1)
+	 */
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_VDD_1";
+		zephyr,vref-mv = <3300>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/samples/drivers/adc/adc_dt/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/samples/drivers/adc/adc_dt/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..784cb453605
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&lpadc0 0>, <&lpadc0 1>;
+	};
+};
+
+&lpadc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/*
+	 * To use this sample:
+	 * LPADC0 CH1A and CH1B are set up in differential mode (B-A)
+	 * - Connect LPADC0 CH1A signal to voltage between 0~1.8V (J20 pin 20)
+	 * - Connect LPADC0 CH1B signal to voltage between 0~1.8V (J20 pin 24)
+	 * LPADC0 CH2A is set up in single ended mode
+	 * - Connect LPADC0 CH2A signal to voltage between 0~1.8V (J20 pin 28)
+	 */
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL1";
+		zephyr,vref-mv = <1800>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <13>;
+		zephyr,input-positive = <MCUX_LPADC_CH1B>;
+		zephyr,input-negative = <MCUX_LPADC_CH1A>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL1";
+		zephyr,vref-mv = <1800>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <MCUX_LPADC_CH2A>;
+	};
+};
diff --git a/samples/drivers/adc/adc_dt/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay b/samples/drivers/adc/adc_dt/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay
new file mode 100644
index 00000000000..784cb453605
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&lpadc0 0>, <&lpadc0 1>;
+	};
+};
+
+&lpadc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/*
+	 * To use this sample:
+	 * LPADC0 CH1A and CH1B are set up in differential mode (B-A)
+	 * - Connect LPADC0 CH1A signal to voltage between 0~1.8V (J20 pin 20)
+	 * - Connect LPADC0 CH1B signal to voltage between 0~1.8V (J20 pin 24)
+	 * LPADC0 CH2A is set up in single ended mode
+	 * - Connect LPADC0 CH2A signal to voltage between 0~1.8V (J20 pin 28)
+	 */
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL1";
+		zephyr,vref-mv = <1800>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <13>;
+		zephyr,input-positive = <MCUX_LPADC_CH1B>;
+		zephyr,input-negative = <MCUX_LPADC_CH1A>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL1";
+		zephyr,vref-mv = <1800>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <MCUX_LPADC_CH2A>;
+	};
+};
diff --git a/samples/drivers/adc/adc_dt/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/samples/drivers/adc/adc_dt/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
new file mode 100644
index 00000000000..45fe5e8b5e5
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
@@ -0,0 +1,25 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2021 NXP
+ */
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&adc1 0>;
+	};
+};
+
+&adc1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/samples/drivers/adc/adc_dt/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/samples/drivers/adc/adc_dt/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
similarity index 100%
rename from samples/drivers/adc/adc_dt/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
rename to samples/drivers/adc/adc_dt/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
diff --git a/samples/drivers/adc/adc_dt/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/samples/drivers/adc/adc_dt/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay
deleted file mode 100644
index b07fe80528b..00000000000
--- a/samples/drivers/adc/adc_dt/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * SPDX-License-Identifier: Apache-2.0
- *
- * Copyright (c) 2020 Linaro Limited
- * Copyright 2023-2024 NXP
- */
-
-#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
-
-/ {
-	zephyr,user {
-		/* adjust channel number according to pinmux in board.dts */
-		io-channels = <&lpadc0 0>;
-	};
-};
-
-&lpadc0 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	/*
-	 * To use this sample:
-	 * - Connect LPADC0 CH0 signal to voltage between 0~1.8V (J9 pin 10)
-	 */
-
-	channel@0 {
-		reg = <0>;
-		zephyr,gain = "ADC_GAIN_1";
-		zephyr,reference = "ADC_REF_EXTERNAL0";
-		zephyr,vref-mv = <1800>;
-		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_TICKS, 7)>;
-		zephyr,resolution = <12>;
-		zephyr,input-positive = <MCUX_LPADC_CH0A>;
-	};
-};
diff --git a/samples/drivers/adc/adc_dt/boards/nrf54h20dk_nrf54h20_common.dtsi b/samples/drivers/adc/adc_dt/boards/nrf54h20dk_nrf54h20_common.dtsi
new file mode 100644
index 00000000000..7c78d5891d4
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/nrf54h20dk_nrf54h20_common.dtsi
@@ -0,0 +1,45 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>, <&adc 1>, <&adc 7>;
+	};
+};
+
+&adc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1_2";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN1>; /* P1.01 */
+		zephyr,resolution = <10>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1_2";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN2>; /* P1.02 */
+		zephyr,resolution = <12>;
+		zephyr,oversampling = <8>;
+	};
+
+	channel@7 {
+		reg = <7>;
+		zephyr,gain = "ADC_GAIN_1_2";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN3>; /* P1.03 */
+		zephyr,input-negative = <NRF_SAADC_AIN7>; /* P1.07 */
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/samples/drivers/adc/adc_dt/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/samples/drivers/adc/adc_dt/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
index 7c78d5891d4..658b19b0ae5 100644
--- a/samples/drivers/adc/adc_dt/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
+++ b/samples/drivers/adc/adc_dt/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
@@ -4,42 +4,4 @@
  * Copyright (c) 2024 Nordic Semiconductor ASA
  */
 
-/ {
-	zephyr,user {
-		io-channels = <&adc 0>, <&adc 1>, <&adc 7>;
-	};
-};
-
-&adc {
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	channel@0 {
-		reg = <0>;
-		zephyr,gain = "ADC_GAIN_1_2";
-		zephyr,reference = "ADC_REF_INTERNAL";
-		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
-		zephyr,input-positive = <NRF_SAADC_AIN1>; /* P1.01 */
-		zephyr,resolution = <10>;
-	};
-
-	channel@1 {
-		reg = <1>;
-		zephyr,gain = "ADC_GAIN_1_2";
-		zephyr,reference = "ADC_REF_INTERNAL";
-		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
-		zephyr,input-positive = <NRF_SAADC_AIN2>; /* P1.02 */
-		zephyr,resolution = <12>;
-		zephyr,oversampling = <8>;
-	};
-
-	channel@7 {
-		reg = <7>;
-		zephyr,gain = "ADC_GAIN_1_2";
-		zephyr,reference = "ADC_REF_INTERNAL";
-		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
-		zephyr,input-positive = <NRF_SAADC_AIN3>; /* P1.03 */
-		zephyr,input-negative = <NRF_SAADC_AIN7>; /* P1.07 */
-		zephyr,resolution = <12>;
-	};
-};
+#include "nrf54h20dk_nrf54h20_common.dtsi"
diff --git a/samples/drivers/adc/adc_dt/boards/nrf54h20dk_nrf54h20_cpuppr.overlay b/samples/drivers/adc/adc_dt/boards/nrf54h20dk_nrf54h20_cpuppr.overlay
new file mode 100644
index 00000000000..4599ed3f8a0
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/nrf54h20dk_nrf54h20_cpuppr.overlay
@@ -0,0 +1,11 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ */
+
+#include "nrf54h20dk_nrf54h20_common.dtsi"
+
+&adc {
+	status = "okay";
+};
diff --git a/samples/drivers/adc/adc_dt/boards/nucleo_c071rb.overlay b/samples/drivers/adc/adc_dt/boards/nucleo_c071rb.overlay
new file mode 100644
index 00000000000..716a674b29a
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/nucleo_c071rb.overlay
@@ -0,0 +1,41 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 STMicroelectronics
+ */
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&adc1 0>, <&adc1 1>, <&adc1 4>;
+	};
+};
+
+&adc1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@4 {
+		reg = <4>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/samples/drivers/adc/adc_dt/boards/nucleo_wba52cg.overlay b/samples/drivers/adc/adc_dt/boards/nucleo_wba55cg.overlay
similarity index 100%
rename from samples/drivers/adc/adc_dt/boards/nucleo_wba52cg.overlay
rename to samples/drivers/adc/adc_dt/boards/nucleo_wba55cg.overlay
diff --git a/samples/drivers/adc/adc_dt/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/samples/drivers/adc/adc_dt/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..321f7e6b05a
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,55 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 7>;
+	};
+};
+
+&adc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN4>; /* P1.11 */
+		zephyr,resolution = <10>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN2>; /* P1.06 */
+		zephyr,resolution = <12>;
+		zephyr,oversampling = <8>;
+	};
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_VDD>;
+		zephyr,resolution = <12>;
+		zephyr,oversampling = <8>;
+	};
+
+	channel@7 {
+		reg = <7>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN6>; /* P1.13 */
+		zephyr,input-negative = <NRF_SAADC_AIN7>; /* P1.14 */
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/samples/drivers/adc/adc_dt/boards/pico_plus2_rp2350b_m33.overlay b/samples/drivers/adc/adc_dt/boards/pico_plus2_rp2350b_m33.overlay
new file mode 100644
index 00000000000..abf2d227844
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/pico_plus2_rp2350b_m33.overlay
@@ -0,0 +1,24 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>;
+	};
+};
+
+&adc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/samples/drivers/adc/adc_dt/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/samples/drivers/adc/adc_dt/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
new file mode 100644
index 00000000000..1d80e7ce421
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>, <&adc 2>;
+	};
+};
+
+&adc {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <1800>;
+	};
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <1800>;
+	};
+};
diff --git a/samples/drivers/adc/adc_dt/boards/xg24_rb4187c.overlay b/samples/drivers/adc/adc_dt/boards/xg24_rb4187c.overlay
new file mode 100644
index 00000000000..6ab6c25219f
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/xg24_rb4187c.overlay
@@ -0,0 +1,50 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ */
+
+#include <dt-bindings/pinctrl/silabs/xg24-pinctrl.h>
+#include <dt-bindings/adc/silabs-adc.h>
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 3>, <&adc0 4>;
+	};
+};
+
+&pinctrl {
+	adc0_default: adc0_default {
+		group0 {
+			/* Allocate odd bus 0 on GPIO port B to IADC for access to pin PB1 */
+			silabs,analog-bus = <ABUS_BODD0_IADC0>;
+		};
+	};
+};
+
+&adc0 {
+	pinctrl-0 = <&adc0_default>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	channel@3 {
+		reg = <3>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <IADC_INPUT_AVDD>;
+	};
+
+	channel@4 {
+		reg = <4>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_VDD_1";
+		zephyr,vref-mv = <3300>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <IADC_INPUT_PB1>;
+	};
+};
diff --git a/samples/drivers/adc/adc_dt/boards/xg29_rb4412a.overlay b/samples/drivers/adc/adc_dt/boards/xg29_rb4412a.overlay
new file mode 100644
index 00000000000..720a26a5688
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/boards/xg29_rb4412a.overlay
@@ -0,0 +1,50 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ */
+
+#include <dt-bindings/pinctrl/silabs/xg29-pinctrl.h>
+#include <dt-bindings/adc/silabs-adc.h>
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 3>, <&adc0 4>;
+	};
+};
+
+&pinctrl {
+	adc0_default: adc0_default {
+		group0 {
+			/* Allocate odd bus 0 on GPIO port B to IADC for access to pin PB1 */
+			silabs,analog-bus = <ABUS_BODD0_IADC0>;
+		};
+	};
+};
+
+&adc0 {
+	pinctrl-0 = <&adc0_default>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	channel@3 {
+		reg = <3>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <IADC_INPUT_AVDD>;
+	};
+
+	channel@4 {
+		reg = <4>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_VDD_1";
+		zephyr,vref-mv = <3300>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <IADC_INPUT_PD3>;
+	};
+};
diff --git a/samples/drivers/adc/adc_dt/sample.yaml b/samples/drivers/adc/adc_dt/sample.yaml
index a855a3f5238..588ea29941c 100644
--- a/samples/drivers/adc/adc_dt/sample.yaml
+++ b/samples/drivers/adc/adc_dt/sample.yaml
@@ -17,6 +17,7 @@ tests:
       - nrf52840dk/nrf52840
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54h20dk/nrf54h20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
       - mec172xevb_assy6906
       - gd32f350r_eval
       - gd32f450i_eval
@@ -33,8 +34,11 @@ tests:
       - longan_nano/gd32vf103/lite
       - rd_rw612_bga
       - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
       - frdm_mcxc242
       - ucans32k1sic
+      - xg24_rb4187c
+      - xg29_rb4412a
     integration_platforms:
       - nucleo_l073rz
       - nrf52840dk/nrf52840
diff --git a/samples/drivers/adc/adc_dt/sysbuild/vpr_launcher/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/samples/drivers/adc/adc_dt/sysbuild/vpr_launcher/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
new file mode 100644
index 00000000000..d3ddd5ac093
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/sysbuild/vpr_launcher/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "../../../boards/nrf54h20dk_nrf54h20_common.dtsi"
+
+&adc {
+	status = "reserved";
+	interrupt-parent = <&cpuppr_clic>;
+};
diff --git a/samples/drivers/adc/adc_dt/sysbuild/vpr_launcher/prj.conf b/samples/drivers/adc/adc_dt/sysbuild/vpr_launcher/prj.conf
new file mode 100644
index 00000000000..b2a4ba59104
--- /dev/null
+++ b/samples/drivers/adc/adc_dt/sysbuild/vpr_launcher/prj.conf
@@ -0,0 +1 @@
+# nothing here
diff --git a/samples/drivers/adc/adc_sequence/Kconfig b/samples/drivers/adc/adc_sequence/Kconfig
index c8351a5e712..e2d97244d4f 100644
--- a/samples/drivers/adc/adc_sequence/Kconfig
+++ b/samples/drivers/adc/adc_sequence/Kconfig
@@ -9,4 +9,8 @@ config SEQUENCE_RESOLUTION
 	int "Set the resolution of the sequence readings."
 	default 12
 
+config SEQUENCE_32BITS_REGISTERS
+	bool "ADC data sequences are on 32bits"
+	default n
+
 source "Kconfig.zephyr"
diff --git a/samples/drivers/adc/adc_sequence/README.rst b/samples/drivers/adc/adc_sequence/README.rst
index 1227f44d9a1..5c5cd9b58e1 100644
--- a/samples/drivers/adc/adc_sequence/README.rst
+++ b/samples/drivers/adc/adc_sequence/README.rst
@@ -31,7 +31,7 @@ Building and Running for Nordic nRF52840
 ========================================
 
 The sample can be built and executed for the
-:ref:`nrf52840dk_nrf52840` as follows:
+:zephyr:board:`nrf52840dk` as follows:
 
 .. zephyr-app-commands::
    :zephyr-app: samples/drivers/adc/adc_sequence
diff --git a/samples/drivers/adc/adc_sequence/boards/arduino_due.overlay b/samples/drivers/adc/adc_sequence/boards/arduino_due.overlay
new file mode 100644
index 00000000000..ca34d9d18ad
--- /dev/null
+++ b/samples/drivers/adc/adc_sequence/boards/arduino_due.overlay
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2024 Centro de Inovacao EDGE
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		adc0 = &adc0;
+	};
+};
+
+&adc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	pinctrl-0 = <&adc0_default>;
+	pinctrl-names = "default";
+
+	prescaler = <9>;
+	startup-time = <64>;
+	settling-time = <3>;
+	tracking-time = <2>;
+
+	/* External ADC(+) */
+	channel@6 { // Connector A1
+		reg = <6>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <6>;
+		zephyr,vref-mv = <3300>;
+	};
+	channel@7 { // Connector A0
+		reg = <7>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <7>;
+		zephyr,vref-mv = <3300>;
+	};
+};
diff --git a/samples/drivers/adc/adc_sequence/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/samples/drivers/adc/adc_sequence/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..e798e92876a
--- /dev/null
+++ b/samples/drivers/adc/adc_sequence/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,62 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 7>;
+	};
+};
+
+/ {
+	aliases {
+		adc0 = &adc;
+	};
+};
+
+&adc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN4>; /* P1.11 */
+		zephyr,resolution = <10>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN2>; /* P1.06 */
+		zephyr,resolution = <12>;
+		zephyr,oversampling = <8>;
+	};
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_DVDD>; /* 0.9 V internal */
+		zephyr,resolution = <12>;
+		zephyr,oversampling = <8>;
+	};
+
+	channel@7 {
+		reg = <7>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN6>; /* P1.13 */
+		zephyr,input-negative = <NRF_SAADC_AIN7>; /* P1.14 */
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/samples/drivers/adc/adc_sequence/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/samples/drivers/adc/adc_sequence/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..e798e92876a
--- /dev/null
+++ b/samples/drivers/adc/adc_sequence/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,62 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 7>;
+	};
+};
+
+/ {
+	aliases {
+		adc0 = &adc;
+	};
+};
+
+&adc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN4>; /* P1.11 */
+		zephyr,resolution = <10>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN2>; /* P1.06 */
+		zephyr,resolution = <12>;
+		zephyr,oversampling = <8>;
+	};
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_DVDD>; /* 0.9 V internal */
+		zephyr,resolution = <12>;
+		zephyr,oversampling = <8>;
+	};
+
+	channel@7 {
+		reg = <7>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN6>; /* P1.13 */
+		zephyr,input-negative = <NRF_SAADC_AIN7>; /* P1.14 */
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/samples/drivers/adc/adc_sequence/boards/frdm_mcxc444.conf b/samples/drivers/adc/adc_sequence/boards/frdm_mcxc444.conf
new file mode 100644
index 00000000000..3201f7a9cc4
--- /dev/null
+++ b/samples/drivers/adc/adc_sequence/boards/frdm_mcxc444.conf
@@ -0,0 +1 @@
+CONFIG_ADC_MCUX_ADC16_VREF_ALTERNATE=y
diff --git a/samples/drivers/adc/adc_sequence/boards/frdm_mcxc444.overlay b/samples/drivers/adc/adc_sequence/boards/frdm_mcxc444.overlay
new file mode 100644
index 00000000000..ef107d2a365
--- /dev/null
+++ b/samples/drivers/adc/adc_sequence/boards/frdm_mcxc444.overlay
@@ -0,0 +1,30 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright 2024 NXP
+ */
+
+/ {
+	aliases {
+		adc0 = &adc0;
+	};
+};
+
+&adc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/*
+	 * To use this sample:
+	 * - Connect ADC0 SE0 signal to voltage between 0~3.3V (J4 pin 1)
+	 */
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_VDD_1";
+		zephyr,vref-mv = <3300>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/samples/drivers/adc/adc_sequence/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/samples/drivers/adc/adc_sequence/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..7fedbe52ad2
--- /dev/null
+++ b/samples/drivers/adc/adc_sequence/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,61 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 7>;
+	};
+};
+
+/ {
+	aliases {
+		adc0 = &adc;
+	};
+};
+
+&adc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN4>; /* P1.11 */
+		zephyr,resolution = <10>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN2>; /* P1.06 */
+		zephyr,resolution = <12>;
+		zephyr,oversampling = <8>;
+	};
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_DVDD>; /* 0.9 V internal */
+		zephyr,resolution = <12>;
+		zephyr,oversampling = <8>;
+	};
+
+	channel@7 {
+		reg = <7>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN6>; /* P1.13 */
+		zephyr,input-negative = <NRF_SAADC_AIN7>; /* P1.14 */
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/samples/drivers/adc/adc_sequence/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.conf b/samples/drivers/adc/adc_sequence/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.conf
new file mode 100644
index 00000000000..65f176fd23b
--- /dev/null
+++ b/samples/drivers/adc/adc_sequence/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.conf
@@ -0,0 +1 @@
+CONFIG_SEQUENCE_RESOLUTION=12
diff --git a/samples/drivers/adc/adc_sequence/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/samples/drivers/adc/adc_sequence/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
new file mode 100644
index 00000000000..8f8b9739b97
--- /dev/null
+++ b/samples/drivers/adc/adc_sequence/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+/ {
+	aliases {
+		adc0 = &adc;
+	};
+};
+
+&adc {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <1800>;
+	};
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <1800>;
+	};
+};
diff --git a/samples/drivers/adc/adc_sequence/boards/stm32f3_disco.conf b/samples/drivers/adc/adc_sequence/boards/stm32f3_disco.conf
new file mode 100644
index 00000000000..08cc33d8603
--- /dev/null
+++ b/samples/drivers/adc/adc_sequence/boards/stm32f3_disco.conf
@@ -0,0 +1,4 @@
+# A4114 driver can only acquire one sequence sample
+CONFIG_SEQUENCE_SAMPLES=1
+CONFIG_SEQUENCE_RESOLUTION=12
+CONFIG_SEQUENCE_32BITS_REGISTERS=y
diff --git a/samples/drivers/adc/adc_sequence/boards/stm32f3_disco.overlay b/samples/drivers/adc/adc_sequence/boards/stm32f3_disco.overlay
new file mode 100644
index 00000000000..7b171fe759c
--- /dev/null
+++ b/samples/drivers/adc/adc_sequence/boards/stm32f3_disco.overlay
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2024 Pierrick Curt
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		adc0 = &adc_ad4114;
+	};
+};
+
+&spi1 {
+	pinctrl-0 = <&spi1_nss_pa4 &spi1_sck_pa5
+		     &spi1_miso_pa6 &spi1_mosi_pa7>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	adc_ad4114: adc_ad4114@0 {
+		compatible = "adi,ad4114-adc";
+		spi-max-frequency = <DT_FREQ_M(1)>;
+		status = "okay";
+		reg = <0>;
+		#io-channel-cells = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		/* INPUTx mapping bits [9:0] for CH0 to CH15 */
+		map-inputs = <0x10 0x30 0x50 0x70 0x90 0xB0 0xD0 0xF0 0x110 \
+					0x130 0x150 0x170 0x190 0x1B0 0x1D0 0x1F0>;
+
+
+		channel@0 {
+			reg = <0x0>;
+			zephyr,gain = "ADC_GAIN_1";
+			zephyr,reference = "ADC_REF_EXTERNAL0";
+			zephyr,vref-mv = <8>;
+			zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		};
+		channel@1 {
+			reg = <1>;
+			zephyr,gain = "ADC_GAIN_1";
+			zephyr,reference = "ADC_REF_EXTERNAL0";
+			zephyr,vref-mv = <8>;
+			zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		};
+		channel@2 {
+			reg = <2>;
+			zephyr,gain = "ADC_GAIN_1";
+			zephyr,reference = "ADC_REF_EXTERNAL0";
+			zephyr,vref-mv = <8>;
+			zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		};
+		channel@3 {
+			reg = <3>;
+			zephyr,gain = "ADC_GAIN_1";
+			zephyr,reference = "ADC_REF_EXTERNAL0";
+			zephyr,vref-mv = <8>;
+			zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		};
+		channel@4 {
+			reg = <4>;
+			zephyr,gain = "ADC_GAIN_1";
+			zephyr,reference = "ADC_REF_EXTERNAL0";
+			zephyr,vref-mv = <8>;
+			zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		};
+		channel@5 {
+			reg = <5>;
+			zephyr,gain = "ADC_GAIN_1";
+			zephyr,reference = "ADC_REF_EXTERNAL0";
+			zephyr,vref-mv = <8>;
+			zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		};
+		channel@6 {
+			reg = <6>;
+			zephyr,gain = "ADC_GAIN_1";
+			zephyr,reference = "ADC_REF_EXTERNAL0";
+			zephyr,vref-mv = <8>;
+			zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		};
+		channel@7 {
+			reg = <7>;
+			zephyr,gain = "ADC_GAIN_1";
+			zephyr,reference = "ADC_REF_EXTERNAL0";
+			zephyr,vref-mv = <8>;
+			zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		};
+		channel@8 {
+			reg = <8>;
+			zephyr,gain = "ADC_GAIN_1";
+			zephyr,reference = "ADC_REF_EXTERNAL0";
+			zephyr,vref-mv = <8>;
+			zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		};
+		channel@9 {
+			reg = <9>;
+			zephyr,gain = "ADC_GAIN_1";
+			zephyr,reference = "ADC_REF_EXTERNAL0";
+			zephyr,vref-mv = <8>;
+			zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		};
+		channel@a {
+			reg = <0xa>;
+			zephyr,gain = "ADC_GAIN_1";
+			zephyr,reference = "ADC_REF_EXTERNAL0";
+			zephyr,vref-mv = <8>;
+			zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		};
+		channel@b {
+			reg = <0xb>;
+			zephyr,gain = "ADC_GAIN_1";
+			zephyr,reference = "ADC_REF_EXTERNAL0";
+			zephyr,vref-mv = <8>;
+			zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		};
+		channel@c {
+			reg = <0xc>;
+			zephyr,gain = "ADC_GAIN_1";
+			zephyr,reference = "ADC_REF_EXTERNAL0";
+			zephyr,vref-mv = <8>;
+			zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		};
+		channel@d {
+			reg = <0xd>;
+			zephyr,gain = "ADC_GAIN_1";
+			zephyr,reference = "ADC_REF_EXTERNAL0";
+			zephyr,vref-mv = <8>;
+			zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		};
+		channel@e {
+			reg = <0xe>;
+			zephyr,gain = "ADC_GAIN_1";
+			zephyr,reference = "ADC_REF_EXTERNAL0";
+			zephyr,vref-mv = <8>;
+			zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		};
+		channel@f {
+			reg = <0xf>;
+			zephyr,gain = "ADC_GAIN_1";
+			zephyr,reference = "ADC_REF_EXTERNAL0";
+			zephyr,vref-mv = <8>;
+			zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		};
+	};
+};
diff --git a/samples/drivers/adc/adc_sequence/sample.yaml b/samples/drivers/adc/adc_sequence/sample.yaml
index 29bcadf4497..099cedca654 100644
--- a/samples/drivers/adc/adc_sequence/sample.yaml
+++ b/samples/drivers/adc/adc_sequence/sample.yaml
@@ -11,8 +11,10 @@ tests:
       - nrf52840dk/nrf52840
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54h20dk/nrf54h20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
       - ucans32k1sic
       - frdm_mcxc242
+      - stm32f3_disco
     integration_platforms:
       - nrf52840dk/nrf52840
     harness: console
diff --git a/samples/drivers/adc/adc_sequence/src/main.c b/samples/drivers/adc/adc_sequence/src/main.c
index 084dbf428f3..aa6d64d7a72 100644
--- a/samples/drivers/adc/adc_sequence/src/main.c
+++ b/samples/drivers/adc/adc_sequence/src/main.c
@@ -30,7 +30,11 @@ int main(void)
 {
 	int err;
 	uint32_t count = 0;
+#ifdef CONFIG_SEQUENCE_32BITS_REGISTERS
+	uint32_t channel_reading[CONFIG_SEQUENCE_SAMPLES][CHANNEL_COUNT];
+#else
 	uint16_t channel_reading[CONFIG_SEQUENCE_SAMPLES][CHANNEL_COUNT];
+#endif
 
 	/* Options for the sequence sampling. */
 	const struct adc_sequence_options options = {
diff --git a/samples/drivers/audio/dmic/README.rst b/samples/drivers/audio/dmic/README.rst
index 1382ff0a9ce..2c124b8e83d 100644
--- a/samples/drivers/audio/dmic/README.rst
+++ b/samples/drivers/audio/dmic/README.rst
@@ -17,8 +17,8 @@ Requirements
 
 The device to be used by the sample is specified by defining a devicetree node
 label named ``dmic_dev``.
-The sample has been tested on :ref:`nrf52840dk_nrf52840` (nrf52840dk/nrf52840)
-and :ref:`nrf5340dk_nrf5340` (nrf5340dk/nrf5340/cpuapp), and provides overlay
+The sample has been tested on :zephyr:board:`nrf52840dk` (nrf52840dk/nrf52840)
+and :zephyr:board:`nrf5340dk` (nrf5340dk/nrf5340/cpuapp), and provides overlay
 files for both of these boards.
 
 Building and Running
diff --git a/samples/drivers/audio/dmic/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/samples/drivers/audio/dmic/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..1e64758f5b5
--- /dev/null
+++ b/samples/drivers/audio/dmic/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	pdm20_default_alt: pdm20_default_alt {
+		group1 {
+			psels = <NRF_PSEL(PDM_CLK, 1, 12)>,
+				<NRF_PSEL(PDM_DIN, 1, 13)>;
+		};
+	};
+};
+
+dmic_dev: &pdm20 {
+	status = "okay";
+	pinctrl-0 = <&pdm20_default_alt>;
+	pinctrl-names = "default";
+	clock-source = "PCLK32M";
+};
diff --git a/samples/drivers/audio/dmic/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/samples/drivers/audio/dmic/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..1e64758f5b5
--- /dev/null
+++ b/samples/drivers/audio/dmic/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	pdm20_default_alt: pdm20_default_alt {
+		group1 {
+			psels = <NRF_PSEL(PDM_CLK, 1, 12)>,
+				<NRF_PSEL(PDM_DIN, 1, 13)>;
+		};
+	};
+};
+
+dmic_dev: &pdm20 {
+	status = "okay";
+	pinctrl-0 = <&pdm20_default_alt>;
+	pinctrl-names = "default";
+	clock-source = "PCLK32M";
+};
diff --git a/samples/drivers/audio/dmic/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/samples/drivers/audio/dmic/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..45e09d9a0f3
--- /dev/null
+++ b/samples/drivers/audio/dmic/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	pdm20_default_alt: pdm20_default_alt {
+		group1 {
+			psels = <NRF_PSEL(PDM_CLK, 1, 12)>,
+				<NRF_PSEL(PDM_DIN, 1, 13)>;
+		};
+	};
+};
+
+dmic_dev: &pdm20 {
+	status = "okay";
+	pinctrl-0 = <&pdm20_default_alt>;
+	pinctrl-names = "default";
+	clock-source = "PCLK32M";
+};
diff --git a/samples/drivers/clock_control_litex/README.rst b/samples/drivers/clock_control_litex/README.rst
index eb01b39b994..c32ecb27767 100644
--- a/samples/drivers/clock_control_litex/README.rst
+++ b/samples/drivers/clock_control_litex/README.rst
@@ -132,4 +132,5 @@ Sample output
 
 References
 **********
-- :ref:`litex-vexriscv`
+
+- :zephyr:board:`litex_vexriscv`
diff --git a/samples/drivers/counter/alarm/boards/ek_ra4m1.overlay b/samples/drivers/counter/alarm/boards/ek_ra4m1.overlay
new file mode 100644
index 00000000000..5b83678c38c
--- /dev/null
+++ b/samples/drivers/counter/alarm/boards/ek_ra4m1.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&agt0 {
+	status = "okay";
+	interrupts = <30 1>, <31 1>;
+	interrupt-names = "agti", "agtcmai";
+	renesas,prescaler = <4>;
+	counter0: counter {
+		status = "okay";
+	};
+};
diff --git a/samples/drivers/counter/alarm/boards/fpb_ra4e1.overlay b/samples/drivers/counter/alarm/boards/fpb_ra4e1.overlay
new file mode 100644
index 00000000000..881baf7475a
--- /dev/null
+++ b/samples/drivers/counter/alarm/boards/fpb_ra4e1.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&agt0 {
+	status = "okay";
+	interrupts = <83 1>, <84 1>;
+	interrupt-names = "agti", "agtcmai";
+	renesas,prescaler = <4>;
+	counter0: counter {
+		status = "okay";
+	};
+};
diff --git a/samples/drivers/counter/alarm/boards/max78000evkit_max78000_m4.overlay b/samples/drivers/counter/alarm/boards/max78000evkit_max78000_m4.overlay
new file mode 100644
index 00000000000..9c5ef490ac4
--- /dev/null
+++ b/samples/drivers/counter/alarm/boards/max78000evkit_max78000_m4.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&timer0 {
+	status = "okay";
+	counter0: counter {
+		status = "okay";
+	};
+};
diff --git a/samples/drivers/counter/alarm/boards/max78000fthr_max78000_m4.overlay b/samples/drivers/counter/alarm/boards/max78000fthr_max78000_m4.overlay
new file mode 100644
index 00000000000..9c5ef490ac4
--- /dev/null
+++ b/samples/drivers/counter/alarm/boards/max78000fthr_max78000_m4.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&timer0 {
+	status = "okay";
+	counter0: counter {
+		status = "okay";
+	};
+};
diff --git a/samples/drivers/counter/alarm/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/samples/drivers/counter/alarm/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
new file mode 100644
index 00000000000..98bb1332ad8
--- /dev/null
+++ b/samples/drivers/counter/alarm/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&gtm0 {
+	counter {
+		status = "okay";
+	};
+};
diff --git a/samples/drivers/counter/alarm/boards/voice_ra4e1.overlay b/samples/drivers/counter/alarm/boards/voice_ra4e1.overlay
new file mode 100644
index 00000000000..881baf7475a
--- /dev/null
+++ b/samples/drivers/counter/alarm/boards/voice_ra4e1.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&agt0 {
+	status = "okay";
+	interrupts = <83 1>, <84 1>;
+	interrupt-names = "agti", "agtcmai";
+	renesas,prescaler = <4>;
+	counter0: counter {
+		status = "okay";
+	};
+};
diff --git a/samples/drivers/counter/alarm/src/main.c b/samples/drivers/counter/alarm/src/main.c
index 7a345de8230..6690aca8344 100644
--- a/samples/drivers/counter/alarm/src/main.c
+++ b/samples/drivers/counter/alarm/src/main.c
@@ -31,7 +31,7 @@ struct counter_alarm_cfg alarm_cfg;
 #define TIMER DT_INST(0, st_stm32_rtc)
 #elif defined(CONFIG_COUNTER_SMARTBOND_TIMER)
 #define TIMER DT_NODELABEL(timer3)
-#elif defined(CONFIG_COUNTER_NATIVE_POSIX)
+#elif defined(CONFIG_COUNTER_NATIVE_SIM)
 #define TIMER DT_NODELABEL(counter0)
 #elif defined(CONFIG_COUNTER_XLNX_AXI_TIMER)
 #define TIMER DT_INST(0, xlnx_xps_timer_1_00_a)
@@ -54,11 +54,17 @@ struct counter_alarm_cfg alarm_cfg;
 #elif defined(CONFIG_COUNTER_SNPS_DW)
 #define TIMER DT_NODELABEL(timer0)
 #elif defined(CONFIG_COUNTER_TIMER_RPI_PICO)
+#ifdef CONFIG_SOC_SERIES_RP2040
 #define TIMER DT_NODELABEL(timer)
+#elif CONFIG_SOC_SERIES_RP2350
+#define TIMER DT_NODELABEL(timer0)
+#endif
 #elif defined(CONFIG_COUNTER_TIMER_MAX32)
 #define TIMER DT_NODELABEL(counter0)
 #elif defined(CONFIG_COUNTER_RA_AGT)
 #define TIMER DT_NODELABEL(counter0)
+#elif defined(CONFIG_COUNTER_RENESAS_RZ_GTM)
+#define TIMER DT_INST(0, renesas_rz_gtm_counter)
 #else
 #error Unable to find a counter device node in devicetree
 #endif
diff --git a/samples/drivers/crypto/src/main.c b/samples/drivers/crypto/src/main.c
index d4609fc2d10..a5a2fe01fab 100644
--- a/samples/drivers/crypto/src/main.c
+++ b/samples/drivers/crypto/src/main.c
@@ -31,6 +31,8 @@ LOG_MODULE_REGISTER(main);
 #define CRYPTO_DEV_COMPAT nordic_nrf_ecb
 #elif DT_HAS_COMPAT_STATUS_OKAY(renesas_smartbond_crypto)
 #define CRYPTO_DEV_COMPAT renesas_smartbond_crypto
+#elif DT_HAS_COMPAT_STATUS_OKAY(ti_cc23x0_aes)
+#define CRYPTO_DEV_COMPAT ti_cc23x0_aes
 #elif CONFIG_CRYPTO_SI32
 #define CRYPTO_DEV_COMPAT silabs_si32_aes
 #else
@@ -396,7 +398,7 @@ static const uint8_t ccm_expected[31] = {0x58, 0x8c, 0x97, 0x9a, 0x61, 0xc6, 0x6
 void ccm_mode(const struct device *dev)
 {
 	uint8_t encrypted[50] __aligned(IO_ALIGNMENT_BYTES);
-	uint8_t decrypted[25] __aligned(IO_ALIGNMENT_BYTES);
+	uint8_t decrypted[32] __aligned(IO_ALIGNMENT_BYTES);
 	struct cipher_ctx ini = {
 		.keylen = sizeof(ccm_key),
 		.key.bit_stream = ccm_key,
diff --git a/samples/drivers/dac/Kconfig b/samples/drivers/dac/Kconfig
new file mode 100644
index 00000000000..ce025e047cf
--- /dev/null
+++ b/samples/drivers/dac/Kconfig
@@ -0,0 +1,22 @@
+# Private config options for dac sample
+
+# Copyright (c) 2025 NXP
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+mainmenu "DAC sample application"
+
+source "Kconfig.zephyr"
+
+ZEPHYR_USER := zephyr,user
+
+config DAC_SAMPLE_RUN
+	bool "Run DAC sample application"
+	default y if $(dt_node_has_prop,/$(ZEPHYR_USER),dac)
+	help
+	  platform supports dac sample
+
+config DAC_BUFFER_NOT_SUPPORT
+	bool "DAC on board/SoC does not support output buffer mode"
+	help
+	  If this config is turned on, the sample will run with no output buffer enabled
diff --git a/samples/drivers/dac/boards/ek_ra2a1.overlay b/samples/drivers/dac/boards/ek_ra2a1.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/ek_ra2a1.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/ek_ra4e2.overlay b/samples/drivers/dac/boards/ek_ra4e2.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/ek_ra4e2.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/ek_ra4l1.conf b/samples/drivers/dac/boards/ek_ra4l1.conf
new file mode 100644
index 00000000000..3f37d94739f
--- /dev/null
+++ b/samples/drivers/dac/boards/ek_ra4l1.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DAC_BUFFER_NOT_SUPPORT=y
diff --git a/samples/drivers/dac/boards/ek_ra4l1.overlay b/samples/drivers/dac/boards/ek_ra4l1.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/ek_ra4l1.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/ek_ra4m1.conf b/samples/drivers/dac/boards/ek_ra4m1.conf
new file mode 100644
index 00000000000..3f37d94739f
--- /dev/null
+++ b/samples/drivers/dac/boards/ek_ra4m1.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DAC_BUFFER_NOT_SUPPORT=y
diff --git a/samples/drivers/dac/boards/ek_ra4m1.overlay b/samples/drivers/dac/boards/ek_ra4m1.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/ek_ra4m1.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/ek_ra4m2.overlay b/samples/drivers/dac/boards/ek_ra4m2.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/ek_ra4m2.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/ek_ra4m3.overlay b/samples/drivers/dac/boards/ek_ra4m3.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/ek_ra4m3.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/ek_ra4w1.conf b/samples/drivers/dac/boards/ek_ra4w1.conf
new file mode 100644
index 00000000000..3f37d94739f
--- /dev/null
+++ b/samples/drivers/dac/boards/ek_ra4w1.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DAC_BUFFER_NOT_SUPPORT=y
diff --git a/samples/drivers/dac/boards/ek_ra4w1.overlay b/samples/drivers/dac/boards/ek_ra4w1.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/ek_ra4w1.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/ek_ra6e2.overlay b/samples/drivers/dac/boards/ek_ra6e2.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/ek_ra6e2.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/ek_ra6m1.overlay b/samples/drivers/dac/boards/ek_ra6m1.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/ek_ra6m1.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/ek_ra6m2.overlay b/samples/drivers/dac/boards/ek_ra6m2.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/ek_ra6m2.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/ek_ra6m3.overlay b/samples/drivers/dac/boards/ek_ra6m3.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/ek_ra6m3.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/ek_ra6m4.overlay b/samples/drivers/dac/boards/ek_ra6m4.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/ek_ra6m4.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/ek_ra6m5.overlay b/samples/drivers/dac/boards/ek_ra6m5.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/ek_ra6m5.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/ek_ra8d1.overlay b/samples/drivers/dac/boards/ek_ra8d1.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/ek_ra8d1.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/ek_ra8m1.overlay b/samples/drivers/dac/boards/ek_ra8m1.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/ek_ra8m1.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/fpb_ra4e1.overlay b/samples/drivers/dac/boards/fpb_ra4e1.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/fpb_ra4e1.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/fpb_ra6e1.overlay b/samples/drivers/dac/boards/fpb_ra6e1.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/fpb_ra6e1.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/fpb_ra6e2.overlay b/samples/drivers/dac/boards/fpb_ra6e2.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/fpb_ra6e2.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/mck_ra8t1.overlay b/samples/drivers/dac/boards/mck_ra8t1.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/mck_ra8t1.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/samples/drivers/dac/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..77c5f5f61bc
--- /dev/null
+++ b/samples/drivers/dac/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+
+	/*
+	 * Please note on the MCX-N9XX-EVK board, DAC0 output signal port is J1-4.
+	 */
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay b/samples/drivers/dac/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay
new file mode 100644
index 00000000000..77c5f5f61bc
--- /dev/null
+++ b/samples/drivers/dac/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay
@@ -0,0 +1,17 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+
+	/*
+	 * Please note on the MCX-N9XX-EVK board, DAC0 output signal port is J1-4.
+	 */
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/sam4s_xplained.overlay b/samples/drivers/dac/boards/sam4s_xplained.overlay
new file mode 100644
index 00000000000..a075a04a5e7
--- /dev/null
+++ b/samples/drivers/dac/boards/sam4s_xplained.overlay
@@ -0,0 +1,7 @@
+/ {
+	zephyr,user {
+		dac = <&dacc>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/boards/sam_v71_xult_samv71q21.overlay b/samples/drivers/dac/boards/sam_v71_xult_samv71q21.overlay
index a075a04a5e7..dad493e5f04 100644
--- a/samples/drivers/dac/boards/sam_v71_xult_samv71q21.overlay
+++ b/samples/drivers/dac/boards/sam_v71_xult_samv71q21.overlay
@@ -5,3 +5,17 @@
 		dac-resolution = <12>;
 	};
 };
+
+&dacc{
+	status = "okay";
+	pinctrl-0 = <&dac_default>;
+	pinctrl-names = "default";
+};
+
+&pinctrl{
+	dac_default: dac_default{
+		group1 {
+			pinmux = <PB13X_DACC_DAC0>;
+		};
+	};
+};
diff --git a/samples/drivers/dac/boards/sam_v71_xult_samv71q21b.overlay b/samples/drivers/dac/boards/sam_v71_xult_samv71q21b.overlay
index a075a04a5e7..dad493e5f04 100644
--- a/samples/drivers/dac/boards/sam_v71_xult_samv71q21b.overlay
+++ b/samples/drivers/dac/boards/sam_v71_xult_samv71q21b.overlay
@@ -5,3 +5,17 @@
 		dac-resolution = <12>;
 	};
 };
+
+&dacc{
+	status = "okay";
+	pinctrl-0 = <&dac_default>;
+	pinctrl-names = "default";
+};
+
+&pinctrl{
+	dac_default: dac_default{
+		group1 {
+			pinmux = <PB13X_DACC_DAC0>;
+		};
+	};
+};
diff --git a/samples/drivers/dac/boards/voice_ra4e1.overlay b/samples/drivers/dac/boards/voice_ra4e1.overlay
new file mode 100644
index 00000000000..a726274e2b2
--- /dev/null
+++ b/samples/drivers/dac/boards/voice_ra4e1.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
diff --git a/samples/drivers/dac/sample.yaml b/samples/drivers/dac/sample.yaml
index 9c7a53beef1..a94482fa06f 100644
--- a/samples/drivers/dac/sample.yaml
+++ b/samples/drivers/dac/sample.yaml
@@ -3,48 +3,8 @@ sample:
 tests:
   sample.drivers.dac:
     tags: DAC
-    platform_allow:
-      - arduino_zero
-      - b_u585i_iot02a
-      - bl652_dvk
-      - bl653_dvk
-      - bl654_dvk
-      - bl5340_dvk/nrf5340/cpuapp
-      - disco_l475_iot1
-      - esp32_devkitc_wroom/esp32/procpu
-      - esp32_devkitc_wrover/esp32/procpu
-      - esp32s2_saola
-      - frdm_k22f
-      - frdm_k64f
-      - gd32a503v_eval
-      - gd32e103v_eval
-      - gd32f450i_eval
-      - longan_nano
-      - longan_nano/gd32vf103/lite
-      - nucleo_f091rc
-      - nucleo_f207zg
-      - nucleo_f429zi
-      - nucleo_f746zg
-      - nucleo_f767zi
-      - nucleo_g071rb
-      - nucleo_g431rb
-      - nucleo_g474re
-      - nucleo_h743zi
-      - nucleo_l073rz
-      - nucleo_l152re
-      - nucleo_l552ze_q
-      - nucleo_u575zi_q
-      - nucleo_wl55jc
-      - sam_e70_xplained/same70q21
-      - sam_e70_xplained/same70q21b
-      - sam_v71_xult/samv71q21
-      - sam_v71_xult/samv71q21b
-      - stm32f3_disco
-      - stm32l562e_dk
-      - twr_ke18f
-      - lpcxpresso55s36
-      - rd_rw612_bga
     depends_on: dac
+    filter: CONFIG_DAC_SAMPLE_RUN
     integration_platforms:
       - nucleo_l152re
     harness: console
diff --git a/samples/drivers/dac/src/main.c b/samples/drivers/dac/src/main.c
index 308777928b1..71657a19341 100644
--- a/samples/drivers/dac/src/main.c
+++ b/samples/drivers/dac/src/main.c
@@ -28,7 +28,11 @@ static const struct device *const dac_dev = DEVICE_DT_GET(DAC_NODE);
 static const struct dac_channel_cfg dac_ch_cfg = {
 	.channel_id  = DAC_CHANNEL_ID,
 	.resolution  = DAC_RESOLUTION,
-	.buffered = true
+#if defined(CONFIG_DAC_BUFFER_NOT_SUPPORT)
+	.buffered = false,
+#else
+	.buffered = true,
+#endif /* CONFIG_DAC_BUFFER_NOT_SUPPORT */
 };
 
 int main(void)
diff --git a/samples/drivers/display/README.rst b/samples/drivers/display/README.rst
index 4b8ff6b6375..a0d3616dd3e 100644
--- a/samples/drivers/display/README.rst
+++ b/samples/drivers/display/README.rst
@@ -15,12 +15,23 @@ grey changes from black through to white. If the grey looks too green or red
 at any point or the order of the corners is not as described above then the LCD
 may be endian swapped.
 
+On displays with the :c:enumerator:`SCREEN_INFO_X_ALIGNMENT_WIDTH` capability,
+such as those using the :dtcompatible:`sharp,ls0xx` driver, it is only possible
+to draw full lines at a time. On these displays, the rectangles described above
+will be replaced with bars that take up the entire width of the display. Only
+the green and grey bar will be visible.
+
+On monochrome displays, the rectangles (or bars) will all be some shade of grey.
+
+On displays with 1 bit per pixel, the greyscale animation of the bottom
+rectangle (or bar) will appear as flickering between black and white.
+
 Building and Running
 ********************
 
 As this is a generic sample it should work with any display supported by Zephyr.
 
-Below is an example on how to build for a :ref:`nrf52840dk_nrf52840` board with a
+Below is an example on how to build for a :zephyr:board:`nrf52840dk` board with a
 :ref:`adafruit_2_8_tft_touch_v2`.
 
 .. zephyr-app-commands::
diff --git a/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7.conf
similarity index 100%
rename from samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf
rename to samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7.conf
diff --git a/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf
deleted file mode 100644
index 0fbbef94c32..00000000000
--- a/samples/drivers/display/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright 2023, NXP
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-
-CONFIG_HEAP_MEM_POOL_SIZE=64928
diff --git a/samples/drivers/display/boards/stm32n6570_dk.conf b/samples/drivers/display/boards/stm32n6570_dk.conf
new file mode 100644
index 00000000000..89de7acad83
--- /dev/null
+++ b/samples/drivers/display/boards/stm32n6570_dk.conf
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 ST Microelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+# On STM32N6 DK board, display being larger, it requires
+# more memory to draw squares on the display (40K)
+CONFIG_HEAP_MEM_POOL_SIZE=65536
diff --git a/samples/drivers/display/boards/stm32n6570_dk_stm32n657xx_sb.conf b/samples/drivers/display/boards/stm32n6570_dk_stm32n657xx_sb.conf
new file mode 100644
index 00000000000..89de7acad83
--- /dev/null
+++ b/samples/drivers/display/boards/stm32n6570_dk_stm32n657xx_sb.conf
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 ST Microelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+# On STM32N6 DK board, display being larger, it requires
+# more memory to draw squares on the display (40K)
+CONFIG_HEAP_MEM_POOL_SIZE=65536
diff --git a/samples/drivers/display/sample.yaml b/samples/drivers/display/sample.yaml
index b0123fb3c6e..44762871589 100644
--- a/samples/drivers/display/sample.yaml
+++ b/samples/drivers/display/sample.yaml
@@ -5,12 +5,10 @@ tests:
   sample.display.sdl:
     build_only: true
     platform_allow:
-      - native_posix/native/64
       - native_sim/native/64
     tags: display
   sample.display.dummy:
     platform_allow:
-      - native_posix
       - native_sim
     extra_args: DTC_OVERLAY_FILE="dummy_dc.overlay"
     extra_configs:
@@ -24,7 +22,9 @@ tests:
       regex:
         - "Display sample for (.*)"
   sample.display.g1120b0mipi:
-    platform_allow: mimxrt595_evk/mimxrt595s/cm33
+    platform_allow:
+      - mimxrt595_evk/mimxrt595s/cm33
+      - mimxrt700_evk/mimxrt798s/cm33_cpu0
     tags: display
     harness: console
     extra_args: SHIELD=g1120b0mipi
@@ -61,7 +61,9 @@ tests:
   sample.display.rk043fn02h_ct:
     platform_allow:
       - mimxrt1064_evk
-      - mimxrt1060_evk/mimxrt1062/qspi
+      - mimxrt1060_evk@A/mimxrt1062/qspi
+      - mimxrt1060_evk@B/mimxrt1062/qspi
+      - mimxrt1060_evk@C/mimxrt1062/qspi
       - mimxrt1050_evk/mimxrt1052/hyperflash
       - mimxrt1040_evk
     integration_platforms:
@@ -105,6 +107,9 @@ tests:
       - platform:mimxrt1050_evk/mimxrt1052:SHIELD=rk043fn66hs_ctg
       - platform:mimxrt1040_evk/mimxrt1042:SHIELD=rk043fn66hs_ctg
       - platform:frdm_mcxn947/mcxn947/cpu0:SHIELD=lcd_par_s035_8080
+      - platform:mcx_n9xx_evk/mcxn947/cpu0:SHIELD=lcd_par_s035_8080
       - platform:frdm_mcxn236/mcxn236:SHIELD=lcd_par_s035_8080
       - platform:frdm_mcxa156/mcxa156:SHIELD=lcd_par_s035_8080
+      - platform:frdm_rw612:SHIELD=lcd_par_s035_spi
       - platform:ek_ra8d1:SHIELD=rtkmipilcdb00000be
+      - platform:ek_ra8d1:SHIELD=rtk7eka6m3b00001bu
diff --git a/samples/drivers/display/src/main.c b/samples/drivers/display/src/main.c
index cdb4c2b4c8d..d7b53938f78 100644
--- a/samples/drivers/display/src/main.c
+++ b/samples/drivers/display/src/main.c
@@ -158,6 +158,13 @@ static void fill_buffer_mono(enum corner corner, uint8_t grey,
 	memset(buf, color, buf_size);
 }
 
+static inline void fill_buffer_l_8(enum corner corner, uint8_t grey, uint8_t *buf, size_t buf_size)
+{
+	for (size_t idx = 0; idx < buf_size; idx += 1) {
+		*(uint8_t *)(buf + idx) = grey;
+	}
+}
+
 static inline void fill_buffer_mono01(enum corner corner, uint8_t grey,
 				      uint8_t *buf, size_t buf_size)
 {
@@ -231,6 +238,10 @@ int main(void)
 		grey_scale_sleep = 100;
 	}
 
+	if (capabilities.screen_info & SCREEN_INFO_X_ALIGNMENT_WIDTH) {
+		rect_w = capabilities.x_resolution;
+	}
+
 	buf_size = rect_w * rect_h;
 
 	if (buf_size < (capabilities.x_resolution * h_step)) {
@@ -258,6 +269,10 @@ int main(void)
 		fill_buffer_fnc = fill_buffer_bgr565;
 		buf_size *= 2;
 		break;
+	case PIXEL_FORMAT_L_8:
+		bg_color = 0xFFu;
+		fill_buffer_fnc = fill_buffer_l_8;
+		break;
 	case PIXEL_FORMAT_MONO01:
 		bg_color = 0xFFu;
 		fill_buffer_fnc = fill_buffer_mono01;
diff --git a/samples/drivers/eeprom/sample.yaml b/samples/drivers/eeprom/sample.yaml
index 95fb7f88418..b3eec0f4618 100644
--- a/samples/drivers/eeprom/sample.yaml
+++ b/samples/drivers/eeprom/sample.yaml
@@ -6,8 +6,6 @@ tests:
     tags: eeprom
     platform_allow:
       - gd32f450i_eval
-      - native_posix
-      - native_posix/native/64
       - native_sim
       - native_sim/native/64
     integration_platforms:
diff --git a/samples/drivers/ethernet/eth_ivshmem/prj.conf b/samples/drivers/ethernet/eth_ivshmem/prj.conf
index 788afb9866b..850f6660714 100644
--- a/samples/drivers/ethernet/eth_ivshmem/prj.conf
+++ b/samples/drivers/ethernet/eth_ivshmem/prj.conf
@@ -26,6 +26,7 @@ CONFIG_TEST_RANDOM_GENERATOR=y
 CONFIG_SHELL=y
 CONFIG_NET_SHELL=y
 CONFIG_NET_ZPERF=y
+CONFIG_NET_ZPERF_SERVER=y
 
 CONFIG_NET_TCP_WORKQ_STACK_SIZE=4096
 CONFIG_NET_RX_STACK_SIZE=4096
diff --git a/samples/drivers/flash_shell/sample.yaml b/samples/drivers/flash_shell/sample.yaml
index ed75923bc9d..0fa0e1440cf 100644
--- a/samples/drivers/flash_shell/sample.yaml
+++ b/samples/drivers/flash_shell/sample.yaml
@@ -6,11 +6,15 @@ tests:
     tags:
       - flash
       - shell
-    filter: CONFIG_FLASH_HAS_DRIVER_ENABLED
+    filter: CONFIG_FLASH_HAS_DRIVER_ENABLED and dt_chosen_enabled('zephyr,flash-controller')
+            and not CONFIG_SOC_SERIES_BSIM_NRFXX
     platform_exclude:
       - stm32h7s78_dk
       - gd32f350r_eval
-    harness: keyboard
+    harness: shell
+    extra_configs:
+      - arch:posix:CONFIG_UART_NATIVE_PTY_0_ON_STDINOUT=y
     min_ram: 12
     integration_platforms:
       - qemu_x86
+      - native_sim
diff --git a/samples/drivers/flash_shell/test_shell.yml b/samples/drivers/flash_shell/test_shell.yml
new file mode 100644
index 00000000000..2e4dbee98a0
--- /dev/null
+++ b/samples/drivers/flash_shell/test_shell.yml
@@ -0,0 +1,2 @@
+- command: "flash page_info 0"
+  expected: "Page for address 0x0"
diff --git a/samples/drivers/gnss/sample.yaml b/samples/drivers/gnss/sample.yaml
index 385a4ca0b67..0ddd7262a21 100644
--- a/samples/drivers/gnss/sample.yaml
+++ b/samples/drivers/gnss/sample.yaml
@@ -9,4 +9,5 @@ tests:
       - drivers
       - gnss
     filter: dt_alias_exists("gnss")
-    depends_on: gnss
+    integration_platforms:
+      - mimxrt1062_fmurt6
diff --git a/samples/drivers/ht16k33/README.rst b/samples/drivers/ht16k33/README.rst
index a7e747f2f92..eb6f730022e 100644
--- a/samples/drivers/ht16k33/README.rst
+++ b/samples/drivers/ht16k33/README.rst
@@ -1,6 +1,6 @@
 .. zephyr:code-sample:: ht16k33
    :name: HT16K33 LED driver with keyscan
-   :relevant-api: led_interface kscan_interface
+   :relevant-api: led_interface input_interface
 
    Control up to 128 LEDs connected to an HT16K33 LED driver and log keyscan events.
 
@@ -23,7 +23,7 @@ The sample logs keyscan events on the console.
 Building and Running
 ********************
 
-Build the application for the :ref:`nrf52840dk_nrf52840` board, and
+Build the application for the :zephyr:board:`nrf52840dk` board, and
 connect an HT16K33 LED driver at address 0x70 on the I2C-0 bus.
 
 .. zephyr-app-commands::
@@ -33,7 +33,7 @@ connect an HT16K33 LED driver at address 0x70 on the I2C-0 bus.
    :compact:
 
 For flashing the application, refer to the Flashing section of the
-:ref:`nrf52840dk_nrf52840` board documentation.
+:zephyr:board:`nrf52840dk` board documentation.
 
 References
 **********
diff --git a/samples/drivers/ht16k33/boards/nrf52840dk_nrf52840.overlay b/samples/drivers/ht16k33/boards/nrf52840dk_nrf52840.overlay
index 7f859fb1615..3fc5507ad25 100644
--- a/samples/drivers/ht16k33/boards/nrf52840dk_nrf52840.overlay
+++ b/samples/drivers/ht16k33/boards/nrf52840dk_nrf52840.overlay
@@ -12,9 +12,5 @@
 		reg = <0x70>;
 		/* Uncomment to use IRQ instead of polling: */
 		/* irq-gpios = <&gpio1 8 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>; */
-
-		kscan-input {
-			compatible = "zephyr,kscan-input";
-		};
 	};
 };
diff --git a/samples/drivers/ht16k33/prj.conf b/samples/drivers/ht16k33/prj.conf
index fb580b93002..acfe5eba3ea 100644
--- a/samples/drivers/ht16k33/prj.conf
+++ b/samples/drivers/ht16k33/prj.conf
@@ -1,6 +1,6 @@
 CONFIG_LOG=y
 CONFIG_I2C=y
 CONFIG_LED=y
-CONFIG_KSCAN=y
 CONFIG_INPUT=y
+CONFIG_INPUT_EVENT_DUMP=y
 CONFIG_HT16K33_KEYSCAN=y
diff --git a/samples/drivers/ht16k33/src/main.c b/samples/drivers/ht16k33/src/main.c
index 7ede8c6a0d3..e30c36122f9 100644
--- a/samples/drivers/ht16k33/src/main.c
+++ b/samples/drivers/ht16k33/src/main.c
@@ -5,7 +5,6 @@
  */
 
 #include <zephyr/drivers/led.h>
-#include <zephyr/drivers/kscan.h>
 #include <zephyr/devicetree.h>
 #include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
@@ -13,20 +12,10 @@
 LOG_MODULE_REGISTER(main, CONFIG_LOG_DEFAULT_LEVEL);
 
 #define LED_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(holtek_ht16k33)
-#define KEY_NODE DT_CHILD(LED_NODE, kscan_input)
-
-static void keyscan_callback(const struct device *dev, uint32_t row,
-			     uint32_t column, bool pressed)
-{
-	LOG_INF("Row %d, column %d %s", row, column,
-		pressed ? "pressed" : "released");
-}
 
 int main(void)
 {
 	const struct device *const led = DEVICE_DT_GET(LED_NODE);
-	const struct device *const key = DEVICE_DT_GET(KEY_NODE);
-	int err;
 	int i;
 
 	if (!device_is_ready(led)) {
@@ -34,16 +23,6 @@ int main(void)
 		return 0;
 	}
 
-	if (!device_is_ready(key)) {
-		LOG_ERR("Keyscan device not ready");
-		return 0;
-	}
-
-	err = kscan_config(key, keyscan_callback);
-	if (err) {
-		LOG_ERR("Failed to add keyscan callback (err %d)", err);
-	}
-
 	while (1) {
 		LOG_INF("Iterating through all LEDs, turning them on "
 			"one-by-one");
diff --git a/samples/drivers/i2c/rtio_loopback/boards/bl54l15_dvk_nrf54l15_cpuapp.conf b/samples/drivers/i2c/rtio_loopback/boards/bl54l15_dvk_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..16c07c2111f
--- /dev/null
+++ b/samples/drivers/i2c/rtio_loopback/boards/bl54l15_dvk_nrf54l15_cpuapp.conf
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_I2C_NRFX_TWIS_BUF_SIZE=256
diff --git a/samples/drivers/i2c/rtio_loopback/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/samples/drivers/i2c/rtio_loopback/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..b00332bd6b9
--- /dev/null
+++ b/samples/drivers/i2c/rtio_loopback/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * SDA = P1.8 and P1.9
+ * SCL = P1.10 and P1.11
+ */
+
+/ {
+	aliases {
+		i2c-controller = &i2c21;
+		i2c-controller-target = &i2c22;
+	};
+};
+
+&pinctrl {
+	i2c21_default: i2c21_default {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 8)>,
+				<NRF_PSEL(TWIS_SCL, 1, 10)>;
+			bias-pull-up;
+		};
+	};
+
+	i2c21_sleep: i2c21_sleep {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 8)>,
+				<NRF_PSEL(TWIS_SCL, 1, 10)>;
+			low-power-enable;
+		};
+	};
+
+	i2c22_default: i2c22_default {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 9)>,
+				<NRF_PSEL(TWIS_SCL, 1, 11)>;
+			bias-pull-up;
+		};
+	};
+
+	i2c22_sleep: i2c22_sleep {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 9)>,
+				<NRF_PSEL(TWIS_SCL, 1, 11)>;
+			low-power-enable;
+		};
+	};
+};
+
+&i2c21 {
+	pinctrl-0 = <&i2c21_default>;
+	pinctrl-1 = <&i2c21_sleep>;
+	pinctrl-names = "default", "sleep";
+	zephyr,concat-buf-size = <256>;
+	status = "okay";
+};
+
+&i2c22 {
+	compatible = "nordic,nrf-twis";
+	pinctrl-0 = <&i2c22_default>;
+	pinctrl-1 = <&i2c22_sleep>;
+	pinctrl-names = "default", "sleep";
+	status = "okay";
+};
diff --git a/samples/drivers/i2c/rtio_loopback/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf b/samples/drivers/i2c/rtio_loopback/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..16c07c2111f
--- /dev/null
+++ b/samples/drivers/i2c/rtio_loopback/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_I2C_NRFX_TWIS_BUF_SIZE=256
diff --git a/samples/drivers/i2c/rtio_loopback/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/samples/drivers/i2c/rtio_loopback/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..b00332bd6b9
--- /dev/null
+++ b/samples/drivers/i2c/rtio_loopback/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * SDA = P1.8 and P1.9
+ * SCL = P1.10 and P1.11
+ */
+
+/ {
+	aliases {
+		i2c-controller = &i2c21;
+		i2c-controller-target = &i2c22;
+	};
+};
+
+&pinctrl {
+	i2c21_default: i2c21_default {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 8)>,
+				<NRF_PSEL(TWIS_SCL, 1, 10)>;
+			bias-pull-up;
+		};
+	};
+
+	i2c21_sleep: i2c21_sleep {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 8)>,
+				<NRF_PSEL(TWIS_SCL, 1, 10)>;
+			low-power-enable;
+		};
+	};
+
+	i2c22_default: i2c22_default {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 9)>,
+				<NRF_PSEL(TWIS_SCL, 1, 11)>;
+			bias-pull-up;
+		};
+	};
+
+	i2c22_sleep: i2c22_sleep {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 9)>,
+				<NRF_PSEL(TWIS_SCL, 1, 11)>;
+			low-power-enable;
+		};
+	};
+};
+
+&i2c21 {
+	pinctrl-0 = <&i2c21_default>;
+	pinctrl-1 = <&i2c21_sleep>;
+	pinctrl-names = "default", "sleep";
+	zephyr,concat-buf-size = <256>;
+	status = "okay";
+};
+
+&i2c22 {
+	compatible = "nordic,nrf-twis";
+	pinctrl-0 = <&i2c22_default>;
+	pinctrl-1 = <&i2c22_sleep>;
+	pinctrl-names = "default", "sleep";
+	status = "okay";
+};
diff --git a/samples/drivers/i2c/rtio_loopback/boards/ophelia4ev_nrf54l15_cpuapp.conf b/samples/drivers/i2c/rtio_loopback/boards/ophelia4ev_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..c8ffd42673e
--- /dev/null
+++ b/samples/drivers/i2c/rtio_loopback/boards/ophelia4ev_nrf54l15_cpuapp.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_I2C_NRFX_TWIS_BUF_SIZE=256
diff --git a/samples/drivers/i2c/rtio_loopback/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/samples/drivers/i2c/rtio_loopback/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..f47fe8bad2a
--- /dev/null
+++ b/samples/drivers/i2c/rtio_loopback/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * SDA = P1.8 and P1.9
+ * SCL = P1.10 and P1.11
+ */
+
+/ {
+	aliases {
+		i2c-controller = &i2c21;
+		i2c-controller-target = &i2c22;
+	};
+};
+
+&pinctrl {
+	i2c21_default: i2c21_default {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 8)>,
+				<NRF_PSEL(TWIS_SCL, 1, 10)>;
+			bias-pull-up;
+		};
+	};
+
+	i2c21_sleep: i2c21_sleep {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 8)>,
+				<NRF_PSEL(TWIS_SCL, 1, 10)>;
+			low-power-enable;
+		};
+	};
+
+	i2c22_default: i2c22_default {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 9)>,
+				<NRF_PSEL(TWIS_SCL, 1, 11)>;
+			bias-pull-up;
+		};
+	};
+
+	i2c22_sleep: i2c22_sleep {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 9)>,
+				<NRF_PSEL(TWIS_SCL, 1, 11)>;
+			low-power-enable;
+		};
+	};
+};
+
+&i2c21 {
+	pinctrl-0 = <&i2c21_default>;
+	pinctrl-1 = <&i2c21_sleep>;
+	pinctrl-names = "default", "sleep";
+	zephyr,concat-buf-size = <256>;
+	status = "okay";
+};
+
+&i2c22 {
+	compatible = "nordic,nrf-twis";
+	pinctrl-0 = <&i2c22_default>;
+	pinctrl-1 = <&i2c22_sleep>;
+	pinctrl-names = "default", "sleep";
+	status = "okay";
+};
diff --git a/samples/drivers/i2c/rtio_loopback/sample.yaml b/samples/drivers/i2c/rtio_loopback/sample.yaml
index a9d41fbf8cd..cf081c7670c 100644
--- a/samples/drivers/i2c/rtio_loopback/sample.yaml
+++ b/samples/drivers/i2c/rtio_loopback/sample.yaml
@@ -16,3 +16,4 @@ tests:
       - nrf5340dk/nrf5340/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54h20dk/nrf54h20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
diff --git a/samples/drivers/i2s/echo/README.rst b/samples/drivers/i2s/echo/README.rst
index 6dfb674c1e2..041bfd0de73 100644
--- a/samples/drivers/i2s/echo/README.rst
+++ b/samples/drivers/i2s/echo/README.rst
@@ -22,8 +22,8 @@ a devicetree node label named ``i2s_rxtx`` or separate node labels ``i2s_rx``
 and ``i2s_tx`` if separate I2S devices are to be used for the RX and TX
 streams.
 
-This sample has been tested on :ref:`nrf52840dk_nrf52840` (nrf52840dk/nrf52840)
-and :ref:`nrf5340dk_nrf5340` (nrf5340dk/nrf5340/cpuapp), using the Audio Codec
+This sample has been tested on :zephyr:board:`nrf52840dk` (nrf52840dk/nrf52840)
+and :zephyr:board:`nrf5340dk` (nrf5340dk/nrf5340/cpuapp), using the Audio Codec
 Shield, and provides overlay files for both of these boards.
 
 More information about the used shield and the CODEC itself can be found here:
diff --git a/samples/drivers/i2s/echo/boards/esp32_devkitc_wrover_procpu.overlay b/samples/drivers/i2s/echo/boards/esp32_devkitc_wrover_procpu.overlay
new file mode 100644
index 00000000000..a0eb2eb24cc
--- /dev/null
+++ b/samples/drivers/i2s/echo/boards/esp32_devkitc_wrover_procpu.overlay
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&i2s0_default {
+	group1 {
+		pinmux = <I2S0_O_WS_GPIO33>,
+				<I2S0_O_BCK_GPIO32>,
+				<I2S0_O_SD_GPIO27>,
+				<I2S0_I_WS_GPIO26>,
+				<I2S0_I_BCK_GPIO25>;
+		output-enable;
+	};
+	group2 {
+		pinmux = <I2S0_I_SD_GPIO18>;
+		input-enable;
+	};
+};
+
+i2s_rxtx: &i2s0 {
+	status = "okay";
+
+	interrupts = <I2S0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>,
+		<I2S0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
+	interrupt-names = "tx", "rx";
+
+};
diff --git a/samples/drivers/i2s/echo/boards/esp32s2_devkitc.overlay b/samples/drivers/i2s/echo/boards/esp32s2_devkitc.overlay
new file mode 100644
index 00000000000..fca91d46bd5
--- /dev/null
+++ b/samples/drivers/i2s/echo/boards/esp32s2_devkitc.overlay
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&i2s0_default {
+	group1 {
+		pinmux = <I2S0_O_WS_GPIO17>,
+				<I2S0_O_BCK_GPIO16>,
+				<I2S0_O_SD_GPIO15>,
+				<I2S0_I_WS_GPIO11>,
+				<I2S0_I_BCK_GPIO10>;
+		output-enable;
+	};
+	group2 {
+		pinmux = <I2S0_I_SD_GPIO18>;
+		input-enable;
+	};
+};
+
+i2s_rxtx: &i2s0 {
+	status = "okay";
+
+	interrupts = <I2S0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>,
+		<I2S0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
+	interrupt-names = "tx", "rx";
+
+};
diff --git a/samples/drivers/i2s/echo/boards/esp32s3_devkitc_procpu.overlay b/samples/drivers/i2s/echo/boards/esp32s3_devkitc_procpu.overlay
index 951f535893d..de41dcb08d2 100644
--- a/samples/drivers/i2s/echo/boards/esp32s3_devkitc_procpu.overlay
+++ b/samples/drivers/i2s/echo/boards/esp32s3_devkitc_procpu.overlay
@@ -1,52 +1,28 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-&pinctrl {
-	i2s0_pinconf: i2s0_pinconf {
-		group1 {
-			pinmux = <I2S0_MCLK_GPIO42>,
-				 <I2S0_O_WS_GPIO41>,
-				 <I2S0_O_BCK_GPIO40>,
-				 <I2S0_O_SD_GPIO39>;
-			output-enable;
-		};
+&i2s0_default {
+	group1 {
+		pinmux = <I2S0_MCLK_GPIO42>,
+				<I2S0_O_WS_GPIO41>,
+				<I2S0_O_BCK_GPIO40>,
+				<I2S0_O_SD_GPIO39>;
+		output-enable;
 	};
-
-	i2s1_pinconf: i2s1_pinconf {
-		group1 {
-			pinmux = <I2S1_MCLK_GPIO35>,
-				 <I2S1_I_WS_GPIO36>,
-				 <I2S1_I_BCK_GPIO37>;
-			output-enable;
-		};
-		group2 {
-			pinmux = <I2S1_I_SD_GPIO38>;
-			input-enable;
-		};
+	group2 {
+		pinmux = <I2S0_I_SD_GPIO38>;
+		input-enable;
 	};
 };
 
-i2s_tx: &i2s0 {
+i2s_rxtx: &i2s0 {
 	status = "okay";
 
-	pinctrl-0 = <&i2s0_pinconf>;
-	pinctrl-names = "default";
-
-	dmas = <&dma 3>;
-	dma-names = "tx";
-};
-
-i2s_rx: &i2s1 {
-	status = "okay";
-
-	pinctrl-0 = <&i2s1_pinconf>;
-	pinctrl-names = "default";
-
-	dmas = <&dma 4>;
-	dma-names = "rx";
+	dmas = <&dma 2>, <&dma 3>;
+	dma-names = "rx", "tx";
 };
 
 &dma {
diff --git a/samples/drivers/i2s/i2s_codec/boards/stm32f4_disco.conf b/samples/drivers/i2s/i2s_codec/boards/stm32f4_disco.conf
new file mode 100644
index 00000000000..b3872c1efe5
--- /dev/null
+++ b/samples/drivers/i2s/i2s_codec/boards/stm32f4_disco.conf
@@ -0,0 +1,8 @@
+# Copyright 2025 Titouan Christophe
+# SPDX-License-Identifier: Apache-2.0
+
+# Even though the stm32f4_disco board overlay is tuned for 22.05/44.1/88.2kHz
+# audio output, it hasn't enough RAM to hold all buffers allocated by this
+# sample at such higher audio rates
+CONFIG_SAMPLE_FREQ=8000
+CONFIG_AUDIO_CODEC=y
diff --git a/samples/drivers/i2s/i2s_codec/boards/stm32f4_disco.overlay b/samples/drivers/i2s/i2s_codec/boards/stm32f4_disco.overlay
new file mode 100644
index 00000000000..e4adf924578
--- /dev/null
+++ b/samples/drivers/i2s/i2s_codec/boards/stm32f4_disco.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2025 Titouan Christophe
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		i2s-codec-tx = &i2s3;
+	};
+};
diff --git a/samples/drivers/i2s/output/boards/esp32_devkitc_wrover_procpu.overlay b/samples/drivers/i2s/output/boards/esp32_devkitc_wrover_procpu.overlay
new file mode 100644
index 00000000000..ee5fa6e31d5
--- /dev/null
+++ b/samples/drivers/i2s/output/boards/esp32_devkitc_wrover_procpu.overlay
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		i2s-tx = &i2s0;
+	};
+};
+
+&i2s0_default {
+	group1 {
+		pinmux = <I2S0_O_WS_GPIO33>,
+				<I2S0_O_BCK_GPIO32>,
+				<I2S0_O_SD_GPIO27>;
+		output-enable;
+	};
+	group2 {
+		pinmux = <I2S0_I_SD_GPIO18>;
+		input-enable;
+	};
+};
+
+&i2s0 {
+	status = "okay";
+
+	interrupts = <I2S0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
+	interrupt-names = "tx";
+};
diff --git a/samples/drivers/i2s/output/sample.yaml b/samples/drivers/i2s/output/sample.yaml
index 8763b5128b2..d86bd18278b 100644
--- a/samples/drivers/i2s/output/sample.yaml
+++ b/samples/drivers/i2s/output/sample.yaml
@@ -2,8 +2,11 @@ sample:
   description: I2S Output Sample
   name: i2s_output
 common:
-  tags: drivers
-  depends_on: i2s
+  tags:
+    - drivers
+    - i2s
 tests:
   sample.drivers.i2s.output:
     filter: dt_alias_exists("i2s-tx")
+    integration_platforms:
+      - mimxrt1060_evk@B/mimxrt1062/qspi
diff --git a/samples/drivers/ipm/ipm_esp32/sample.yaml b/samples/drivers/ipm/ipm_esp32/sample.yaml
index 68ef394450c..14e81e1dbbe 100644
--- a/samples/drivers/ipm/ipm_esp32/sample.yaml
+++ b/samples/drivers/ipm/ipm_esp32/sample.yaml
@@ -8,4 +8,3 @@ tests:
     tags:
       - samples
       - ipm
-    skip: true
diff --git a/samples/drivers/jesd216/src/main.c b/samples/drivers/jesd216/src/main.c
index b8dad485997..9f28dac4a0a 100644
--- a/samples/drivers/jesd216/src/main.c
+++ b/samples/drivers/jesd216/src/main.c
@@ -340,7 +340,7 @@ int main(void)
 			const struct jesd216_bfp *bfp = (struct jesd216_bfp *)dw;
 
 			dump_bfp(php, bfp);
-			printf("size = <%u> bits;\n", (uint32_t)jesd216_bfp_density(bfp));
+			printf("size = <%u>; // bits\n", (uint32_t)jesd216_bfp_density(bfp));
 			printf("sfdp-bfp =");
 		} else {
 			printf("sfdp-%04x =", id);
diff --git a/samples/drivers/kscan/CMakeLists.txt b/samples/drivers/kscan/CMakeLists.txt
deleted file mode 100644
index 1c5812ccffb..00000000000
--- a/samples/drivers/kscan/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-cmake_minimum_required(VERSION 3.20.0)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(kscan)
-
-FILE(GLOB app_sources src/*.c)
-target_sources(app PRIVATE ${app_sources})
diff --git a/samples/drivers/kscan/README.rst b/samples/drivers/kscan/README.rst
deleted file mode 100644
index e2d2d129b6b..00000000000
--- a/samples/drivers/kscan/README.rst
+++ /dev/null
@@ -1,33 +0,0 @@
-.. zephyr:code-sample:: kscan
-   :name: KSCAN
-   :relevant-api: kscan_interface timer_apis
-
-   Use the KSCAN API to read key presses and releases on a keyboard matrix.
-
-Overview
-********
-
-This sample demonstrates how to use the :ref:`KSCAN API <kscan_api>`.
-Callbacks are registered that will write to the console indicating KSCAN events.
-These events indicate key presses and releases.
-
-Building and Running
-********************
-
-The sample can be built and executed on boards supporting a Keyboard Matrix.
-It requires a correct fixture setup. Please connect a Keyboard Matrix to
-exercise the functionality (you need to obtain the right keymap from the vendor
-because they vary across different manufactures).
-For the correct execution of that sample in twister, add into boards's
-map-file next fixture settings::
-
-      - fixture: fixture_connect_keyboard
-
-Sample output
-=============
-
-.. code-block:: console
-
-   KSCAN test with a Keyboard matrix
-   Note: You are expected to see several callbacks
-   as you press and release keys!
diff --git a/samples/drivers/kscan/boards/mec15xxevb_assy6853.conf b/samples/drivers/kscan/boards/mec15xxevb_assy6853.conf
deleted file mode 100644
index 1eed72b67d5..00000000000
--- a/samples/drivers/kscan/boards/mec15xxevb_assy6853.conf
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_CONSOLE=y
-CONFIG_LOG=y
-CONFIG_LOG_PROCESS_THREAD_SLEEP_MS=100
diff --git a/samples/drivers/kscan/prj.conf b/samples/drivers/kscan/prj.conf
deleted file mode 100644
index e55038ab558..00000000000
--- a/samples/drivers/kscan/prj.conf
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_STDOUT_CONSOLE=y
-CONFIG_PRINTK=y
-CONFIG_KSCAN=y
-CONFIG_LOG=y
diff --git a/samples/drivers/kscan/sample.yaml b/samples/drivers/kscan/sample.yaml
deleted file mode 100644
index e276641711a..00000000000
--- a/samples/drivers/kscan/sample.yaml
+++ /dev/null
@@ -1,16 +0,0 @@
-sample:
-  name: KSCAN driver sample
-tests:
-  sample.drivers.kscan:
-    tags:
-      - drivers
-      - kscan
-    harness: console
-    harness_config:
-      type: multi_line
-      ordered: true
-      regex:
-        - "kb data(.*)"
-      fixture: fixture_connect_keyboard
-    depends_on: kscan
-    filter: dt_chosen_enabled("zephyr,keyboard-scan")
diff --git a/samples/drivers/kscan/src/main.c b/samples/drivers/kscan/src/main.c
deleted file mode 100644
index 66fdd5727bb..00000000000
--- a/samples/drivers/kscan/src/main.c
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Copyright (c) 2019 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/kernel.h>
-#include <zephyr/sys/printk.h>
-#include <soc.h>
-#include <zephyr/drivers/kscan.h>
-
-#define LOG_LEVEL LOG_LEVEL_DBG
-#include <zephyr/logging/log.h>
-
-LOG_MODULE_REGISTER(main);
-
-const struct device *const kscan_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_keyboard_scan));
-static struct k_timer typematic_timer;
-static struct k_timer block_matrix_timer;
-
-#define KEY_RSVD 0U
-#define MAX_MATRIX_KEY_COLS 16
-#define MAX_MATRIX_KEY_ROWS 8
-
-/****************************************************************************/
-/*  Fujitsu keyboard model N860-7401-TOO1                                   */
-/*                                                                          */
-/*  Sense7  Sense6  Sense5  Sense4  Sense3  Sense2  Sense1  Sense0          */
-/*+---------------------------------------------------------------+         */
-/*|       | Capslk|       |   1!  |  Tab  |   F1  |   `~  |       | Scan  0 */
-/*|       |  (30) |       |  (2)  |  (16) | (112) |  (1)  |       | (KEY #) */
-/*|-------+-------+-------+-------+-------+-------+-------+-------|         */
-/*|       |   W   |   Q   |   F7  |       |  Esc  |   F6  |   F5  | Scan  1 */
-/*|       |  (18) |  (17) | (118) |       | (110) | (117) | (116) | (KEY #) */
-/*|-------+-------+-------+-------+-------+-------+-------+-------|         */
-/*|       |   F8  |       |   2@  |   F4  |   F3  |       |   F2  | Scan  2 */
-/*|       | (119) |       |  (3)  | (115) | (114) |       | (113) | (KEY #) */
-/*|-------+-------+-------+-------+-------+-------+-------+-------|         */
-/*|       |   R   |   E   |   3#  |   4$  |   C   |   F   |   V   | Scan  3 */
-/*|       |  (20) |  (19) |  (4)  |  (5)  |  (48) |  (34) |  (49) | (KEY #) */
-/*|-------+-------+-------+-------+-------+-------+-------+-------|         */
-/*|   N   |   Y   |   6^  |   5%  |   B   |   T   |   H   |   G   | Scan  4 */
-/*|  (51) |  (22) |  (7)  |  (6)  | (50)  |  (21) |  (36) |  (35) | (KEY #) */
-/*|-------+-------+-------+-------+-------+-------+-------+-------|         */
-/*| SpaceB|   M   |   A   |   7&  |   J   |   D   |   S   |   U   | Scan  5 */
-/*|  (61) |  (52) |  (31) |  (8)  |  (37) |  (33) |  (32) |  (23) | (KEY #) */
-/*|-------+-------+-------+-------+-------+-------+-------+-------|         */
-/*|   F9  |   I   |   ,<  |   8*  |       |   Z   |   X   |   K   | Scan  6 */
-/*| (120) |  (24) |  (53) |  (9)  |       |  (46) |  (47) |  (38) | (KEY #) */
-/*|-------+-------+-------+-------+-------+-------+-------+-------|         */
-/*|       |   =+  |   ]}  |   9(  |   L   |       |  CRSL |   O   | Scan  7 */
-/*|       |  (13) |  (28) |  (10) |  (39) |       |  (79) |  (25) | (KEY #) */
-/*|-------+-------+-------+-------+-------+-------+-------+-------|         */
-/*|   -_  |   0)  |   /?  |   [{  |   ;:  |       |       |   '"  | Scan  8 */
-/*|  (12) |  (11) |  (55) |  (27) |  (40) |       |       |  (41) | (KEY #) */
-/*|-------+-------+-------+-------+-------+-------+-------+-------|         */
-/*|  F10  | Pause | NumLK |   P   |       |       |       |       | Scan  9 */
-/*| (121) | (126) |  (90) |  (26) |       |       |       |       | (KEY #) */
-/*|-------+-------+-------+-------+-------+-------+-------+-------|         */
-/*| BkSpac|   \|  |  F11  |   .>  |       |       | W-Appl|  CRSD | Scan 10 */
-/*|  (15) |  (29) | (122) |  (54) |       |       |  (71) |  (84) | (KEY #) */
-/*|-------+-------+-------+-------+-------+-------+-------+-------|         */
-/*| Enter | Delete| Insert|  F12  |       |       |  CRSU |  CRSR | Scan 11 */
-/*|  (43) |  (76) |  (75) | (123) |       |       |  (83) |  (89) | (KEY #) */
-/*|-------+-------+-------+-------+-------+-------+-------+-------|         */
-/*|       | R-WIN |       |       |       |       | L-WIN |   Fn  | Scan 12 */
-/*|       |  (87) |       |       |       |       |  (59) | (255) | (KEY #) */
-/*|-------+-------+-------+-------+-------+-------+-------+-------|         */
-/*|       |       |       | RShift| LShift|       |       |       | Scan 13 */
-/*|       |       |       |  (57) |  (44) |       |       |       | (KEY #) */
-/*|-------+-------+-------+-------+-------+-------+-------+-------|         */
-/*|       |       |       |       |       |       | L Alt | R Alt | Scan 14 */
-/*|       |       |       |       |       |       |  (60) |  (62) | (KEY #) */
-/*|-------+-------+-------+-------+-------+-------+-------+-------|         */
-/*| R Ctrl|       |       |       |       | L Ctrl|       |       | Scan 15 */
-/*|  (64) |       |       |       |       |  (58) |       |       | (KEY #) */
-/*+---------------------------------------------------------------+         */
-/*                                                                          */
-/****************************************************************************/
-
-static const uint8_t keymap[MAX_MATRIX_KEY_COLS][MAX_MATRIX_KEY_ROWS] = {
-	{KEY_RSVD, 1, 112, 16, 2, KEY_RSVD, 30, KEY_RSVD},
-	{116, 117, 110, KEY_RSVD, 118, 17, 18, KEY_RSVD},
-	{113, KEY_RSVD, 114, 115, 3, KEY_RSVD, 119, KEY_RSVD},
-	{49, 34, 48, 5, 4, 19, 20, KEY_RSVD},
-	{35, 36, 21, 50, 6, 7, 22, 51},
-	{23, 32, 33, 37, 8, 31, 52, 61},
-	{38, 47, 46, KEY_RSVD, 9, 53, 24, 120},
-	{25, 79, KEY_RSVD, 39, 10, 28, 13, KEY_RSVD},
-	{41, KEY_RSVD, KEY_RSVD, 40, 27, 55, 11, 12},
-	{KEY_RSVD, KEY_RSVD, KEY_RSVD, KEY_RSVD, 26, 90, 126, 121},
-	{84, 71, KEY_RSVD, KEY_RSVD, 54, 122, 29, 15},
-	{89, 83, KEY_RSVD, KEY_RSVD, 123, 75, 76, 43},
-	{255, 59, KEY_RSVD, KEY_RSVD, KEY_RSVD, KEY_RSVD, 87, KEY_RSVD},
-	{KEY_RSVD, KEY_RSVD, 44, 57, KEY_RSVD, KEY_RSVD, KEY_RSVD},
-	{62, 60, KEY_RSVD, KEY_RSVD, KEY_RSVD, KEY_RSVD, KEY_RSVD, KEY_RSVD},
-	{KEY_RSVD, KEY_RSVD, 58, KEY_RSVD, KEY_RSVD, KEY_RSVD, KEY_RSVD, 64},
-};
-
-/* Key used for typematic */
-static uint8_t last_key;
-
-/* Typematic rate and delay values correspond to the data passed after
- * the F3 command (See the 8042 spec online)
- */
-static const uint16_t period[] = {
-	33U,  37U,  42U,  46U,  50U,  54U,  58U,  63U,
-	67U,  75U,  83U,  92U, 100U, 109U, 116U, 125U,
-	133U, 149U, 167U, 182U, 200U, 217U, 232U, 250U,
-	270U, 303U, 333U, 370U, 400U, 435U, 470U, 500U
-};
-
-static const uint16_t delay[] = { 250U, 500U, 750U, 1000U };
-
-static bool block_kb_matrix;
-
-static void typematic_callback(struct k_timer *timer)
-{
-	LOG_INF("Typematic : %u\n", last_key);
-}
-
-static void kb_callback(const struct device *dev, uint32_t row, uint32_t col,
-			bool pressed)
-{
-	ARG_UNUSED(dev);
-	last_key = keymap[col][row];
-
-	LOG_INF("Key code = %u Pressed = %u\n", last_key, pressed);
-
-	if (pressed) {
-		k_timer_start(&typematic_timer,
-			      K_MSEC(delay[0]), K_MSEC(period[0]));
-	} else {
-		k_timer_stop(&typematic_timer);
-	}
-}
-
-static void block_matrix_callback(struct k_timer *timer)
-{
-	LOG_DBG("block host : %d\n", block_kb_matrix);
-	if (block_kb_matrix) {
-		kscan_disable_callback(kscan_dev);
-		block_kb_matrix = false;
-		k_timer_stop(&typematic_timer);
-	} else {
-		kscan_enable_callback(kscan_dev);
-		block_kb_matrix = true;
-	}
-}
-
-int main(void)
-{
-	printk("Kscan matrix sample application\n");
-
-	if (!device_is_ready(kscan_dev)) {
-		LOG_ERR("kscan device %s not ready", kscan_dev->name);
-		return 0;
-	}
-
-	kscan_config(kscan_dev, kb_callback);
-	k_timer_init(&typematic_timer, typematic_callback, NULL);
-	k_timer_init(&block_matrix_timer, block_matrix_callback, NULL);
-	k_timer_start(&block_matrix_timer, K_SECONDS(1), K_SECONDS(3));
-
-	return 0;
-}
diff --git a/samples/drivers/led/is31fl3733/sample.yaml b/samples/drivers/led/is31fl3733/sample.yaml
index a16b0c469a0..468d91c87fd 100644
--- a/samples/drivers/led/is31fl3733/sample.yaml
+++ b/samples/drivers/led/is31fl3733/sample.yaml
@@ -6,3 +6,5 @@ tests:
     filter: dt_compat_enabled("issi,is31fl3733")
     tags: LED
     depends_on: i2c
+    integration_platforms:
+      - frdm_k22f
diff --git a/samples/drivers/led/led_strip/Kconfig b/samples/drivers/led/led_strip/Kconfig
index fdf12abde24..803a1ea6cc9 100644
--- a/samples/drivers/led/led_strip/Kconfig
+++ b/samples/drivers/led/led_strip/Kconfig
@@ -9,6 +9,14 @@ config SAMPLE_LED_UPDATE_DELAY
 	help
 	  Delay between LED updates in ms.
 
+config SAMPLE_LED_BRIGHTNESS
+	int "LED brightness"
+	default 16
+	range 1 255
+	help
+	  Brightness level of each LED. Defaults to a low value to make
+	  it easier to distinguish colors.
+
 endmenu
 
 source "Kconfig.zephyr"
diff --git a/samples/drivers/led/led_strip/README.rst b/samples/drivers/led/led_strip/README.rst
index 9c4efdc2c44..0807639c0af 100644
--- a/samples/drivers/led/led_strip/README.rst
+++ b/samples/drivers/led/led_strip/README.rst
@@ -65,6 +65,9 @@ Building and Running
 The sample updates the LED strip periodically. The update frequency can be
 modified by changing the :kconfig:option:`CONFIG_SAMPLE_LED_UPDATE_DELAY`.
 
+The brightness level of each LED can be adjusted by changing the
+:kconfig:option:`CONFIG_SAMPLE_LED_BRIGHTNESS` configuration option.
+
 Then build and flash the application:
 
 .. zephyr-app-commands::
diff --git a/samples/drivers/led/led_strip/boards/adafruit_feather_esp32s2.conf b/samples/drivers/led/led_strip/boards/adafruit_feather_esp32s2.conf
new file mode 100644
index 00000000000..8230eb9896b
--- /dev/null
+++ b/samples/drivers/led/led_strip/boards/adafruit_feather_esp32s2.conf
@@ -0,0 +1,2 @@
+CONFIG_GPIO=y
+CONFIG_GPIO_HOGS=y
diff --git a/samples/drivers/led/led_strip/boards/adafruit_feather_esp32s2_tft.conf b/samples/drivers/led/led_strip/boards/adafruit_feather_esp32s2_tft.conf
new file mode 100644
index 00000000000..8230eb9896b
--- /dev/null
+++ b/samples/drivers/led/led_strip/boards/adafruit_feather_esp32s2_tft.conf
@@ -0,0 +1,2 @@
+CONFIG_GPIO=y
+CONFIG_GPIO_HOGS=y
diff --git a/samples/drivers/led/led_strip/boards/adafruit_feather_esp32s2_tft_reverse.conf b/samples/drivers/led/led_strip/boards/adafruit_feather_esp32s2_tft_reverse.conf
new file mode 100644
index 00000000000..8230eb9896b
--- /dev/null
+++ b/samples/drivers/led/led_strip/boards/adafruit_feather_esp32s2_tft_reverse.conf
@@ -0,0 +1,2 @@
+CONFIG_GPIO=y
+CONFIG_GPIO_HOGS=y
diff --git a/samples/drivers/led/led_strip/boards/adafruit_feather_esp32s3_procpu.conf b/samples/drivers/led/led_strip/boards/adafruit_feather_esp32s3_procpu.conf
new file mode 100644
index 00000000000..0968fb220e0
--- /dev/null
+++ b/samples/drivers/led/led_strip/boards/adafruit_feather_esp32s3_procpu.conf
@@ -0,0 +1,4 @@
+CONFIG_POWER_DOMAIN=y
+CONFIG_GPIO=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_DEVICE_POWER_DOMAIN=y
diff --git a/samples/drivers/led/led_strip/boards/esp32s2_devkitc.conf b/samples/drivers/led/led_strip/boards/esp32s2_devkitc.conf
new file mode 100644
index 00000000000..c1378264b96
--- /dev/null
+++ b/samples/drivers/led/led_strip/boards/esp32s2_devkitc.conf
@@ -0,0 +1 @@
+CONFIG_I2S=y
diff --git a/samples/drivers/led/led_strip/boards/esp32s2_devkitc.overlay b/samples/drivers/led/led_strip/boards/esp32s2_devkitc.overlay
new file mode 100644
index 00000000000..9b7c301a3fc
--- /dev/null
+++ b/samples/drivers/led/led_strip/boards/esp32s2_devkitc.overlay
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/led/led.h>
+
+/ {
+	aliases {
+		led-strip = &led_strip;
+	};
+};
+
+&i2s0_default {
+	group1 {
+		pinmux = <I2S0_O_SD_GPIO18>;
+		output-enable;
+	};
+};
+
+i2s_led: &i2s0 {
+	status = "okay";
+
+	interrupts = <I2S0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
+	interrupt-names = "tx";
+
+	led_strip: ws2812@0 {
+		compatible = "worldsemi,ws2812-i2s";
+		reg = <0>;
+
+		chain-length = <1>;
+		color-mapping = <LED_COLOR_ID_GREEN
+				 LED_COLOR_ID_RED
+				 LED_COLOR_ID_BLUE>;
+		reset-delay = <500>;
+	};
+};
diff --git a/samples/drivers/led/led_strip/boards/esp32s3_devkitc_procpu.conf b/samples/drivers/led/led_strip/boards/esp32s3_devkitc_procpu.conf
new file mode 100644
index 00000000000..c1378264b96
--- /dev/null
+++ b/samples/drivers/led/led_strip/boards/esp32s3_devkitc_procpu.conf
@@ -0,0 +1 @@
+CONFIG_I2S=y
diff --git a/samples/drivers/led/led_strip/boards/esp32s3_devkitc_procpu.overlay b/samples/drivers/led/led_strip/boards/esp32s3_devkitc_procpu.overlay
index 8818cbd2384..ab31f1d9b77 100644
--- a/samples/drivers/led/led_strip/boards/esp32s3_devkitc_procpu.overlay
+++ b/samples/drivers/led/led_strip/boards/esp32s3_devkitc_procpu.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,11 +12,16 @@
 	};
 };
 
+&i2s0_default {
+	group1 {
+		pinmux = <I2S0_O_SD_GPIO38>;
+		output-enable;
+	};
+};
+
 i2s_led: &i2s0 {
 	status = "okay";
 
-	pinctrl-0 = <&i2s0_pinconf>;
-
 	dmas = <&dma 3>;
 	dma-names = "tx";
 
@@ -24,7 +29,7 @@ i2s_led: &i2s0 {
 		compatible = "worldsemi,ws2812-i2s";
 
 		reg = <0>;
-		chain-length = <46>;
+		chain-length = <1>;
 		color-mapping = <LED_COLOR_ID_GREEN
 				 LED_COLOR_ID_RED
 				 LED_COLOR_ID_BLUE>;
@@ -35,12 +40,3 @@ i2s_led: &i2s0 {
 &dma {
 	status = "okay";
 };
-
-&pinctrl {
-	i2s0_pinconf: i2s0_pinconf {
-		group1 {
-			pinmux = <I2S0_O_SD_GPIO38>;
-			output-enable;
-		};
-	};
-};
diff --git a/samples/drivers/led/led_strip/src/main.c b/samples/drivers/led/led_strip/src/main.c
index 45e8fad35cd..c2bd74268d6 100644
--- a/samples/drivers/led/led_strip/src/main.c
+++ b/samples/drivers/led/led_strip/src/main.c
@@ -32,9 +32,9 @@ LOG_MODULE_REGISTER(main);
 #define RGB(_r, _g, _b) { .r = (_r), .g = (_g), .b = (_b) }
 
 static const struct led_rgb colors[] = {
-	RGB(0x0f, 0x00, 0x00), /* red */
-	RGB(0x00, 0x0f, 0x00), /* green */
-	RGB(0x00, 0x00, 0x0f), /* blue */
+	RGB(CONFIG_SAMPLE_LED_BRIGHTNESS, 0x00, 0x00), /* red */
+	RGB(0x00, CONFIG_SAMPLE_LED_BRIGHTNESS, 0x00), /* green */
+	RGB(0x00, 0x00, CONFIG_SAMPLE_LED_BRIGHTNESS), /* blue */
 };
 
 static struct led_rgb pixels[STRIP_NUM_PIXELS];
diff --git a/samples/drivers/led/lp5562/README.rst b/samples/drivers/led/lp5562/README.rst
index 9cc8583161d..657e75c2d36 100644
--- a/samples/drivers/led/lp5562/README.rst
+++ b/samples/drivers/led/lp5562/README.rst
@@ -30,7 +30,7 @@ mappings used by this sample.
 Building and Running
 ********************
 
-Build the application for the :ref:`nrf52840dk_nrf52840` board, and connect
+Build the application for the :zephyr:board:`nrf52840dk` board, and connect
 a LP5562 LED driver on the bus I2C0 at the address 0x30.
 
 .. zephyr-app-commands::
@@ -40,6 +40,6 @@ a LP5562 LED driver on the bus I2C0 at the address 0x30.
    :compact:
 
 For flashing the application, refer to the Flashing section of the
-:ref:`nrf52840dk_nrf52840` board documentation.
+:zephyr:board:`nrf52840dk` board documentation.
 
 .. _LP5562 Manual: http://www.ti.com/lit/ds/symlink/lp5562.pdf
diff --git a/samples/drivers/led/lp5569/README.rst b/samples/drivers/led/lp5569/README.rst
index f39fcd1678c..488ffb76964 100644
--- a/samples/drivers/led/lp5569/README.rst
+++ b/samples/drivers/led/lp5569/README.rst
@@ -16,7 +16,7 @@ This pattern then repeats indefinitely.
 Building and Running
 ********************
 
-Build the application for the :ref:`nrf52840dk_nrf52840` board, and connect
+Build the application for the :zephyr:board:`nrf52840dk` board, and connect
 a LP5569 LED controller on the bus I2C0 at the address 0x32.
 
 .. zephyr-app-commands::
@@ -26,7 +26,7 @@ a LP5569 LED controller on the bus I2C0 at the address 0x32.
    :compact:
 
 For flashing the application, refer to the Flashing section of the
-:ref:`nrf52840dk_nrf52840` board documentation.
+:zephyr:board:`nrf52840dk` board documentation.
 
 .. code-block:: none
 
diff --git a/samples/drivers/led/pwm/boards/arduino_uno_r4_r7fa4m1ab3cfm_minima.conf b/samples/drivers/led/pwm/boards/arduino_uno_r4_r7fa4m1ab3cfm_minima.conf
new file mode 100644
index 00000000000..0febfc75605
--- /dev/null
+++ b/samples/drivers/led/pwm/boards/arduino_uno_r4_r7fa4m1ab3cfm_minima.conf
@@ -0,0 +1,3 @@
+CONFIG_BLINK_DELAY_SHORT=20
+CONFIG_BLINK_DELAY_LONG=65
+CONFIG_FADE_DELAY=15
diff --git a/samples/drivers/led/pwm/boards/arduino_uno_r4_r7fa4m1ab3cfm_minima.overlay b/samples/drivers/led/pwm/boards/arduino_uno_r4_r7fa4m1ab3cfm_minima.overlay
new file mode 100644
index 00000000000..9f5fb4f94d9
--- /dev/null
+++ b/samples/drivers/led/pwm/boards/arduino_uno_r4_r7fa4m1ab3cfm_minima.overlay
@@ -0,0 +1,30 @@
+#include <zephyr/dt-bindings/pwm/pwm.h>
+#include <zephyr/dt-bindings/pwm/ra_pwm.h>
+
+/ {
+	leds {
+		status = "disabled";
+	};
+
+	pwm_leds {
+		status = "okay";
+	};
+};
+
+&pinctrl {
+	pwm3_default: pwm3_default {
+		group1 {
+			/* GTIOC3A */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 11)>;
+		};
+	};
+};
+
+&pwm3 {
+	pinctrl-0 = <&pwm3_default>;
+	pinctrl-names = "default";
+	interrupts = <30 1>, <31 1>;
+	interrupt-names = "gtioca", "overflow";
+	status = "okay";
+	divider = <RA_PWM_SOURCE_DIV_1024>;
+};
diff --git a/samples/drivers/led/pwm/boards/arduino_uno_r4_r7fa4m1ab3cfm_wifi.conf b/samples/drivers/led/pwm/boards/arduino_uno_r4_r7fa4m1ab3cfm_wifi.conf
new file mode 100644
index 00000000000..0febfc75605
--- /dev/null
+++ b/samples/drivers/led/pwm/boards/arduino_uno_r4_r7fa4m1ab3cfm_wifi.conf
@@ -0,0 +1,3 @@
+CONFIG_BLINK_DELAY_SHORT=20
+CONFIG_BLINK_DELAY_LONG=65
+CONFIG_FADE_DELAY=15
diff --git a/samples/drivers/led/pwm/boards/arduino_uno_r4_r7fa4m1ab3cfm_wifi.overlay b/samples/drivers/led/pwm/boards/arduino_uno_r4_r7fa4m1ab3cfm_wifi.overlay
new file mode 100644
index 00000000000..c845d33d23b
--- /dev/null
+++ b/samples/drivers/led/pwm/boards/arduino_uno_r4_r7fa4m1ab3cfm_wifi.overlay
@@ -0,0 +1,30 @@
+#include <zephyr/dt-bindings/pwm/pwm.h>
+#include <zephyr/dt-bindings/pwm/ra_pwm.h>
+
+/ {
+	leds {
+		status = "disabled";
+	};
+
+	pwm_leds {
+		status = "okay";
+	};
+};
+
+&pinctrl {
+	pwm2_default: pwm2_default {
+		group1 {
+			/* GTIOC2B */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 2)>;
+		};
+	};
+};
+
+&pwm2 {
+	pinctrl-0 = <&pwm2_default>;
+	pinctrl-names = "default";
+	interrupts = <30 1>, <31 1>;
+	interrupt-names = "gtioca", "overflow";
+	status = "okay";
+	divider = <RA_PWM_SOURCE_DIV_1024>;
+};
diff --git a/samples/drivers/led/pwm/boards/pico_plus2_rp2350b_m33.overlay b/samples/drivers/led/pwm/boards/pico_plus2_rp2350b_m33.overlay
new file mode 100644
index 00000000000..565dcd6fbba
--- /dev/null
+++ b/samples/drivers/led/pwm/boards/pico_plus2_rp2350b_m33.overlay
@@ -0,0 +1,15 @@
+/ {
+	leds {
+		status = "disabled";
+	};
+
+	pwm_leds {
+		status = "okay";
+	};
+};
+
+&pwm {
+	status = "okay";
+	divider-frac-4 = <15>;
+	divider-int-4 = <255>;
+};
diff --git a/samples/drivers/led/pwm/sample.yaml b/samples/drivers/led/pwm/sample.yaml
index 8b7e745a292..8551f658e15 100644
--- a/samples/drivers/led/pwm/sample.yaml
+++ b/samples/drivers/led/pwm/sample.yaml
@@ -7,6 +7,8 @@ tests:
     tags: LED
     depends_on: pwm
     platform_exclude: reel_board
+    integration_platforms:
+      - frdm_k22f
     timeout: 20
     harness: console
     harness_config:
diff --git a/samples/drivers/mbox/CMakeLists.txt b/samples/drivers/mbox/CMakeLists.txt
index 7ae21a6a8e9..e37892f0b88 100644
--- a/samples/drivers/mbox/CMakeLists.txt
+++ b/samples/drivers/mbox/CMakeLists.txt
@@ -1,6 +1,7 @@
 #
 # Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
-# Copyright 2023-2024 NXP
+# Copyright 2023-2025 NXP
+# Copyright 2025 Ezurio LLC
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -16,13 +17,20 @@ if(CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP OR
    CONFIG_BOARD_ADP_XC7K_AE350 OR
    CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7 OR
    CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 OR
+   CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33 OR
    CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 OR
+   CONFIG_BOARD_FRDM_MCXN947_MCXN947_CPU0 OR
+   CONFIG_BOARD_MCX_N9XX_EVK_MCXN947_CPU0 OR
    CONFIG_BOARD_ESP32_DEVKITC_WROOM_ESP32_PROCPU OR
    CONFIG_BOARD_ESP32S3_DEVKITM_ESP32S3_PROCPU OR
    CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR
    CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD OR
+   CONFIG_BOARD_NRF54L09PDK_NRF54L09_CPUAPP OR
    CONFIG_BOARD_NRF54L15DK_NRF54L15_CPUAPP OR
-   CONFIG_BOARD_STM32H747I_DISCO_STM32H747XX_M7)
+   CONFIG_BOARD_NRF54L20PDK_NRF54L20_CPUAPP OR
+   CONFIG_BOARD_STM32H747I_DISCO_STM32H747XX_M7 OR
+   CONFIG_BOARD_BL54L15_DVK_NRF54L15_CPUAPP OR
+   CONFIG_BOARD_BL54L15U_DVK_NRF54L15_CPUAPP)
   message(STATUS "${BOARD}${BOARD_QUALIFIERS} compile as Main in this sample")
 else()
   message(FATAL_ERROR "${BOARD}${BOARD_QUALIFIERS} is not supported for this sample")
diff --git a/samples/drivers/mbox/Kconfig.sysbuild b/samples/drivers/mbox/Kconfig.sysbuild
index cc0a847f28d..143bd89a1b0 100644
--- a/samples/drivers/mbox/Kconfig.sysbuild
+++ b/samples/drivers/mbox/Kconfig.sysbuild
@@ -1,5 +1,6 @@
 # Copyright 2023 Nordic Semiconductor ASA
-# Copyright 2023-2024 NXP
+# Copyright 2023-2025 NXP
+# Copyright 2025 Ezurio LLC
 #
 # SPDX-License-Identifier: Apache-2.0
 
@@ -13,9 +14,17 @@ config REMOTE_BOARD
 	default "mimxrt1170_evkb/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evkb"
 	default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk"
 	default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk"
+	default "mimxrt1180_evk/mimxrt1189/cm7" if $(BOARD) = "mimxrt1180_evk"
 	default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69"
+	default "frdm_mcxn947/mcxn947/cpu1" if $(BOARD) = "frdm_mcxn947"
+	default "mcx_n9xx_evk/mcxn947/cpu1" if $(BOARD) = "mcx_n9xx_evk"
 	default "nrf54h20dk/nrf54h20/cpuapp" if "$(BOARD)${BOARD_QUALIFIERS}" = "nrf54h20dk/nrf54h20/cpurad"
+	default "nrf54l09pdk/nrf54l09/cpuflpr" if $(BOARD) = "nrf54l09pdk"
 	default "nrf54l15dk/nrf54l15/cpuflpr" if $(BOARD) = "nrf54l15dk"
+	default "nrf54l20pdk/nrf54l20/cpuflpr" if $(BOARD) = "nrf54l20pdk"
+	default "ophelia4ev/cpuflpr" if $(BOARD) = "ophelia4ev"
 	default "stm32h747i_disco/stm32h747xx/m4" if $(BOARD) = "stm32h747i_disco"
 	default "esp32_devkitc_wroom/esp32/appcpu" if "$(BOARD)${BOARD_QUALIFIERS}" = "esp32_devkitc_wroom/esp32/procpu"
 	default "esp32s3_devkitm/esp32s3/appcpu" if "$(BOARD)${BOARD_QUALIFIERS}" = "esp32s3_devkitm/esp32s3/procpu"
+	default "bl54l15_dvk/nrf54l15/cpuflpr" if "$(BOARD)${BOARD_QUALIFIERS}" = "bl54l15_dvk/nrf54l15/cpuapp"
+	default "bl54l15u_dvk/nrf54l15/cpuflpr" if $(BOARD) = "bl54l15u_dvk"
diff --git a/samples/drivers/mbox/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/samples/drivers/mbox/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..6d78003344c
--- /dev/null
+++ b/samples/drivers/mbox/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_tx 21>;
+		mbox-names = "rx", "tx";
+	};
+};
+
+&cpuapp_vevif_rx {
+	status = "okay";
+};
+
+&cpuapp_vevif_tx {
+	status = "okay";
+};
diff --git a/samples/drivers/mbox/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/samples/drivers/mbox/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..6d78003344c
--- /dev/null
+++ b/samples/drivers/mbox/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_tx 21>;
+		mbox-names = "rx", "tx";
+	};
+};
+
+&cpuapp_vevif_rx {
+	status = "okay";
+};
+
+&cpuapp_vevif_tx {
+	status = "okay";
+};
diff --git a/samples/drivers/mbox/boards/frdm_mcxn947_mcxn947_cpu0.conf b/samples/drivers/mbox/boards/frdm_mcxn947_mcxn947_cpu0.conf
new file mode 100644
index 00000000000..7e6904d56d5
--- /dev/null
+++ b/samples/drivers/mbox/boards/frdm_mcxn947_mcxn947_cpu0.conf
@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/drivers/mbox/boards/frdm_mcxn947_mcxn947_cpu0.overlay b/samples/drivers/mbox/boards/frdm_mcxn947_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..42601e95336
--- /dev/null
+++ b/samples/drivers/mbox/boards/frdm_mcxn947_mcxn947_cpu0.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox 1>, <&mbox 0>;
+		mbox-names = "tx", "rx";
+	};
+};
diff --git a/samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay b/samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay
index 4ee8379dc9e..dea949213a5 100644
--- a/samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay
+++ b/samples/drivers/mbox/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay
@@ -6,7 +6,7 @@
 
 / {
 	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/drivers/mbox/boards/mcx_n9xx_evk_mcxn947_cpu0.conf b/samples/drivers/mbox/boards/mcx_n9xx_evk_mcxn947_cpu0.conf
new file mode 100644
index 00000000000..7e6904d56d5
--- /dev/null
+++ b/samples/drivers/mbox/boards/mcx_n9xx_evk_mcxn947_cpu0.conf
@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/drivers/mbox/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/samples/drivers/mbox/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..42601e95336
--- /dev/null
+++ b/samples/drivers/mbox/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox 1>, <&mbox 0>;
+		mbox-names = "tx", "rx";
+	};
+};
diff --git a/samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay
index 254741183ee..5113882e1bc 100644
--- a/samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay
+++ b/samples/drivers/mbox/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay
@@ -6,7 +6,7 @@
 
 / {
 	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7.conf
similarity index 100%
rename from samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf
rename to samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7.conf
diff --git a/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
new file mode 100644
index 00000000000..5113882e1bc
--- /dev/null
+++ b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		/* Delete ipc chosen property where old IPM mailbox driver below is
+		 * configured.
+		 */
+		/delete-property/ zephyr,ipc;
+	};
+
+	soc {
+		/* Delete IPM Driver node nxp,imx-mu */
+		/delete-node/ mailbox@40c48000;
+
+		/* Attach MBOX driver to MU Unit */
+		mbox:mbox@40c48000 {
+			compatible = "nxp,mbox-imx-mu";
+			reg = <0x40c48000 0x4000>;
+			interrupts = <118 0>;
+			rx-channels = <4>;
+			#mbox-cells = <1>;
+			status = "okay";
+		};
+	};
+
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox 1>, <&mbox 0>;
+		mbox-names = "tx", "rx";
+	};
+};
diff --git a/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay
deleted file mode 100644
index 254741183ee..00000000000
--- a/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2023 NXP
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
-	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
-		 * configured.
-		 */
-		/delete-property/ zephyr,ipc;
-	};
-
-	soc {
-		/* Delete IPM Driver node nxp,imx-mu */
-		/delete-node/ mailbox@40c48000;
-
-		/* Attach MBOX driver to MU Unit */
-		mbox:mbox@40c48000 {
-			compatible = "nxp,mbox-imx-mu";
-			reg = <0x40c48000 0x4000>;
-			interrupts = <118 0>;
-			rx-channels = <4>;
-			#mbox-cells = <1>;
-			status = "okay";
-		};
-	};
-
-	mbox-consumer {
-		compatible = "vnd,mbox-consumer";
-		mboxes = <&mbox 1>, <&mbox 0>;
-		mbox-names = "tx", "rx";
-	};
-};
diff --git a/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
deleted file mode 100644
index 254741183ee..00000000000
--- a/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2023 NXP
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
-	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
-		 * configured.
-		 */
-		/delete-property/ zephyr,ipc;
-	};
-
-	soc {
-		/* Delete IPM Driver node nxp,imx-mu */
-		/delete-node/ mailbox@40c48000;
-
-		/* Attach MBOX driver to MU Unit */
-		mbox:mbox@40c48000 {
-			compatible = "nxp,mbox-imx-mu";
-			reg = <0x40c48000 0x4000>;
-			interrupts = <118 0>;
-			rx-channels = <4>;
-			#mbox-cells = <1>;
-			status = "okay";
-		};
-	};
-
-	mbox-consumer {
-		compatible = "vnd,mbox-consumer";
-		mboxes = <&mbox 1>, <&mbox 0>;
-		mbox-names = "tx", "rx";
-	};
-};
diff --git a/samples/drivers/mbox/boards/mimxrt1180_evk_mimxrt1189_cm33.conf b/samples/drivers/mbox/boards/mimxrt1180_evk_mimxrt1189_cm33.conf
new file mode 100644
index 00000000000..60eead5a076
--- /dev/null
+++ b/samples/drivers/mbox/boards/mimxrt1180_evk_mimxrt1189_cm33.conf
@@ -0,0 +1,2 @@
+CONFIG_SECOND_CORE_MCUX=y
+CONFIG_INCLUDE_REMOTE_DIR=y
diff --git a/samples/drivers/mbox/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay b/samples/drivers/mbox/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
new file mode 100644
index 00000000000..9836b08ebe3
--- /dev/null
+++ b/samples/drivers/mbox/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox1_a 1>, <&mbox1_a 0>;
+		mbox-names = "tx", "rx";
+	};
+};
diff --git a/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_cpuflpr.overlay b/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_cpuflpr.overlay
index 421881adb2e..7007a6eb329 100644
--- a/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_cpuflpr.overlay
+++ b/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_cpuflpr.overlay
@@ -13,6 +13,10 @@
 
 &cpuapp_bellboard {
 	status = "okay";
+	/* When other cpuapp_bellboard channel is selected for RX,
+	 * make sure it's enabled in the interrupt mask.
+	 * See `nordic,interrupt-mapping` property.
+	 */
 };
 
 &cpuflpr_vevif {
diff --git a/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_cpuppr.overlay b/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_cpuppr.overlay
index 2e5aba6d2f0..86e800350ec 100644
--- a/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_cpuppr.overlay
+++ b/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpuapp_cpuppr.overlay
@@ -13,6 +13,10 @@
 
 &cpuapp_bellboard {
 	status = "okay";
+	/* When other cpuapp_bellboard channel is selected for RX,
+	 * make sure it's enabled in the interrupt mask.
+	 * See `nordic,interrupt-mapping` property.
+	 */
 };
 
 &cpuppr_vevif {
diff --git a/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpurad.overlay b/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpurad.overlay
index d2230e8ef20..42e6f83cbff 100644
--- a/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpurad.overlay
+++ b/samples/drivers/mbox/boards/nrf54h20dk_nrf54h20_cpurad.overlay
@@ -17,4 +17,8 @@
 
 &cpurad_bellboard {
 	status = "okay";
+	/* When other cpurad_bellboard channel is selected for RX,
+	 * make sure it's enabled in the interrupt mask.
+	 * See `nordic,interrupt-mapping` property.
+	 */
 };
diff --git a/samples/drivers/mbox/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay b/samples/drivers/mbox/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay
new file mode 100644
index 00000000000..fd2f23402f5
--- /dev/null
+++ b/samples/drivers/mbox/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_tx 21>;
+		mbox-names = "rx", "tx";
+	};
+};
+
+&cpuapp_vevif_rx {
+	status = "okay";
+};
+
+&cpuapp_vevif_tx {
+	status = "okay";
+};
diff --git a/samples/drivers/mbox/boards/nrf54l20pdk_nrf54l20_cpuapp.overlay b/samples/drivers/mbox/boards/nrf54l20pdk_nrf54l20_cpuapp.overlay
new file mode 100644
index 00000000000..fd2f23402f5
--- /dev/null
+++ b/samples/drivers/mbox/boards/nrf54l20pdk_nrf54l20_cpuapp.overlay
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_tx 21>;
+		mbox-names = "rx", "tx";
+	};
+};
+
+&cpuapp_vevif_rx {
+	status = "okay";
+};
+
+&cpuapp_vevif_tx {
+	status = "okay";
+};
diff --git a/samples/drivers/mbox/remote/CMakeLists.txt b/samples/drivers/mbox/remote/CMakeLists.txt
index 311e489177d..76719ff1459 100644
--- a/samples/drivers/mbox/remote/CMakeLists.txt
+++ b/samples/drivers/mbox/remote/CMakeLists.txt
@@ -1,6 +1,7 @@
 #
 # Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
-# Copyright 2023-2024 NXP
+# Copyright 2023-2025 NXP
+# Copyright 2025 Ezurio LLC
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -14,14 +15,21 @@ if(CONFIG_BOARD_NRF5340DK_NRF5340_CPUNET OR
    CONFIG_BOARD_ADP_XC7K_AE350 OR
    CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM4 OR
    CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4 OR
+   CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM7 OR
    CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU1 OR
+   CONFIG_BOARD_FRDM_MCXN947_MCXN947_CPU1 OR
+   CONFIG_BOARD_MCX_N9XX_EVK_MCXN947_CPU1 OR
    CONFIG_BOARD_ESP32_DEVKITC_WROOM_ESP32_APPCPU OR
    CONFIG_BOARD_ESP32S3_DEVKITM_ESP32S3_APPCPU OR
    CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUPPR OR
    CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUFLPR OR
    CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR
+   CONFIG_BOARD_NRF54L09PDK_NRF54L09_CPUFLPR OR
    CONFIG_BOARD_NRF54L15DK_NRF54L15_CPUFLPR OR
-   CONFIG_BOARD_STM32H747I_DISCO_STM32H747XX_M4)
+   CONFIG_BOARD_NRF54L20PDK_NRF54L20_CPUFLPR OR
+   CONFIG_BOARD_STM32H747I_DISCO_STM32H747XX_M4 OR
+   CONFIG_BOARD_BL54L15_DVK_NRF54L15_CPUFLPR OR
+   CONFIG_BOARD_BL54L15U_DVK_NRF54L15_CPUFLPR)
   message(STATUS "${BOARD}${BOARD_QUALIFIERS} compile as remote in this sample")
 else()
   message(FATAL_ERROR "${BOARD}${BOARD_QUALIFIERS} is not supported for this sample")
diff --git a/samples/drivers/mbox/remote/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay b/samples/drivers/mbox/remote/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..76030bd1825
--- /dev/null
+++ b/samples/drivers/mbox/remote/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&cpuflpr_vevif_rx 21>, <&cpuflpr_vevif_tx 20>;
+		mbox-names = "rx", "tx";
+	};
+};
+
+&cpuflpr_vevif_rx {
+	status = "okay";
+};
+
+&cpuflpr_vevif_tx {
+	status = "okay";
+};
+
+&uart30 {
+	/delete-property/ hw-flow-control;
+};
diff --git a/samples/drivers/mbox/remote/boards/bl54l15_dvk_nrf54l15_cpuflpr_xip.overlay b/samples/drivers/mbox/remote/boards/bl54l15_dvk_nrf54l15_cpuflpr_xip.overlay
new file mode 100644
index 00000000000..76030bd1825
--- /dev/null
+++ b/samples/drivers/mbox/remote/boards/bl54l15_dvk_nrf54l15_cpuflpr_xip.overlay
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&cpuflpr_vevif_rx 21>, <&cpuflpr_vevif_tx 20>;
+		mbox-names = "rx", "tx";
+	};
+};
+
+&cpuflpr_vevif_rx {
+	status = "okay";
+};
+
+&cpuflpr_vevif_tx {
+	status = "okay";
+};
+
+&uart30 {
+	/delete-property/ hw-flow-control;
+};
diff --git a/samples/drivers/mbox/remote/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay b/samples/drivers/mbox/remote/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..76030bd1825
--- /dev/null
+++ b/samples/drivers/mbox/remote/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&cpuflpr_vevif_rx 21>, <&cpuflpr_vevif_tx 20>;
+		mbox-names = "rx", "tx";
+	};
+};
+
+&cpuflpr_vevif_rx {
+	status = "okay";
+};
+
+&cpuflpr_vevif_tx {
+	status = "okay";
+};
+
+&uart30 {
+	/delete-property/ hw-flow-control;
+};
diff --git a/samples/drivers/mbox/remote/boards/bl54l15u_dvk_nrf54l15_cpuflpr_xip.overlay b/samples/drivers/mbox/remote/boards/bl54l15u_dvk_nrf54l15_cpuflpr_xip.overlay
new file mode 100644
index 00000000000..76030bd1825
--- /dev/null
+++ b/samples/drivers/mbox/remote/boards/bl54l15u_dvk_nrf54l15_cpuflpr_xip.overlay
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&cpuflpr_vevif_rx 21>, <&cpuflpr_vevif_tx 20>;
+		mbox-names = "rx", "tx";
+	};
+};
+
+&cpuflpr_vevif_rx {
+	status = "okay";
+};
+
+&cpuflpr_vevif_tx {
+	status = "okay";
+};
+
+&uart30 {
+	/delete-property/ hw-flow-control;
+};
diff --git a/samples/drivers/mbox/remote/boards/frdm_mcxn947_mcxn947_cpu1.conf b/samples/drivers/mbox/remote/boards/frdm_mcxn947_mcxn947_cpu1.conf
new file mode 100644
index 00000000000..7e6904d56d5
--- /dev/null
+++ b/samples/drivers/mbox/remote/boards/frdm_mcxn947_mcxn947_cpu1.conf
@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/drivers/mbox/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay b/samples/drivers/mbox/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay
new file mode 100644
index 00000000000..4e3b4ae1208
--- /dev/null
+++ b/samples/drivers/mbox/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox 0>, <&mbox 1>;
+		mbox-names = "tx", "rx";
+	};
+};
diff --git a/samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay b/samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay
index c1b12825fc0..689cf0e3977 100644
--- a/samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay
+++ b/samples/drivers/mbox/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay
@@ -6,7 +6,7 @@
 
 / {
 	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/drivers/mbox/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.conf b/samples/drivers/mbox/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.conf
new file mode 100644
index 00000000000..7e6904d56d5
--- /dev/null
+++ b/samples/drivers/mbox/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.conf
@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/drivers/mbox/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay b/samples/drivers/mbox/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay
new file mode 100644
index 00000000000..4e3b4ae1208
--- /dev/null
+++ b/samples/drivers/mbox/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox 0>, <&mbox 1>;
+		mbox-names = "tx", "rx";
+	};
+};
diff --git a/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay
index 93538b0acf2..0d15908a63c 100644
--- a/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay
+++ b/samples/drivers/mbox/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay
@@ -10,7 +10,7 @@
 		zephyr,console = &lpuart1;
 		zephyr,shell-uart = &lpuart1;
 
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay
index 93538b0acf2..0d15908a63c 100644
--- a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay
+++ b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay
@@ -10,7 +10,7 @@
 		zephyr,console = &lpuart1;
 		zephyr,shell-uart = &lpuart1;
 
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay
index c2c38c0b930..56d26cc1b59 100644
--- a/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay
+++ b/samples/drivers/mbox/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay
@@ -10,7 +10,7 @@
 		zephyr,console = &lpuart1;
 		zephyr,shell-uart = &lpuart1;
 
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/drivers/mbox/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.conf b/samples/drivers/mbox/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
new file mode 100644
index 00000000000..77adcfa24f4
--- /dev/null
+++ b/samples/drivers/mbox/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
@@ -0,0 +1,2 @@
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/drivers/mbox/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay b/samples/drivers/mbox/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
new file mode 100644
index 00000000000..db51f5184fd
--- /dev/null
+++ b/samples/drivers/mbox/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox1_b 0>, <&mbox1_b 1>;
+		mbox-names = "tx", "rx";
+	};
+};
diff --git a/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
index a3ee9c3e060..3ee1deb9341 100644
--- a/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
+++ b/samples/drivers/mbox/remote/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
@@ -13,6 +13,10 @@
 
 &cpuapp_bellboard {
 	status = "okay";
+	/* When other cpurad_bellboard channel is selected for RX,
+	 * make sure it's enabled in the interrupt mask.
+	 * See `nordic,interrupt-mapping` property.
+	 */
 };
 
 &cpurad_bellboard {
diff --git a/samples/drivers/mbox/remote/boards/nrf54l09pdk_nrf54l09_cpuflpr.overlay b/samples/drivers/mbox/remote/boards/nrf54l09pdk_nrf54l09_cpuflpr.overlay
new file mode 100644
index 00000000000..ea88120ad06
--- /dev/null
+++ b/samples/drivers/mbox/remote/boards/nrf54l09pdk_nrf54l09_cpuflpr.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&cpuflpr_vevif_rx 21>, <&cpuflpr_vevif_tx 20>;
+		mbox-names = "rx", "tx";
+	};
+};
+
+&cpuflpr_vevif_rx {
+	status = "okay";
+};
+
+&cpuflpr_vevif_tx {
+	status = "okay";
+};
+
+&uart30 {
+	/delete-property/ hw-flow-control;
+};
diff --git a/samples/drivers/mbox/remote/boards/nrf54l20pdk_nrf54l20_cpuflpr.overlay b/samples/drivers/mbox/remote/boards/nrf54l20pdk_nrf54l20_cpuflpr.overlay
new file mode 100644
index 00000000000..ea88120ad06
--- /dev/null
+++ b/samples/drivers/mbox/remote/boards/nrf54l20pdk_nrf54l20_cpuflpr.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&cpuflpr_vevif_rx 21>, <&cpuflpr_vevif_tx 20>;
+		mbox-names = "rx", "tx";
+	};
+};
+
+&cpuflpr_vevif_rx {
+	status = "okay";
+};
+
+&cpuflpr_vevif_tx {
+	status = "okay";
+};
+
+&uart30 {
+	/delete-property/ hw-flow-control;
+};
diff --git a/samples/drivers/mbox/sample.yaml b/samples/drivers/mbox/sample.yaml
index f264050b68e..f1a1e56e771 100644
--- a/samples/drivers/mbox/sample.yaml
+++ b/samples/drivers/mbox/sample.yaml
@@ -5,23 +5,23 @@ common:
   tags: mbox
   timeout: 30
 tests:
-  sample.drivers.mbox.real_hw:
-    platform_allow:
-      - nrf5340dk/nrf5340/cpuapp
-      - adp_xc7k/ae350
-      - mimxrt1170_evk@B/mimxrt1176/cm7
-      - mimxrt1170_evk/mimxrt1176/cm7
-      - mimxrt1160_evk/mimxrt1166/cm7
-      - lpcxpresso55s69/lpc55s69/cpu0
+  sample.drivers.mbox:
+    filter: dt_compat_enabled("vnd,mbox-consumer")
+    platform_exclude:
+      - nrf54h20dk/nrf54h20/cpuapp
+      - nrf54h20dk/nrf54h20/cpurad
+      - nrf54l09pdk/nrf54l09/cpuapp
+      - nrf54l15dk/nrf54l15/cpuapp
+      - nrf54l20pdk/nrf54l20/cpuapp
     integration_platforms:
-      - nrf5340dk/nrf5340/cpuapp
+      - nrf5340bsim/nrf5340/cpuapp
     harness: console
     harness_config:
       type: multi_line
       ordered: false
       regex:
-        - "Pong \\(on channel 0\\)"
-        - "Ping \\(on channel 1\\)"
+        - "Pong \\(on channel.*\\)"
+        - "Ping \\(on channel.*\\)"
 
   sample.drivers.mbox.nrf54h20_app_ppr:
     platform_allow:
@@ -73,20 +73,11 @@ tests:
         - "Ping \\(on channel 18\\)"
         - "Pong \\(on channel 12\\)"
 
-  sample.drivers.mbox.simu:
-    platform_allow:
-      - nrf5340bsim/nrf5340/cpuapp
-    harness: console
-    harness_config:
-      type: multi_line
-      ordered: false
-      regex:
-        - "Pong \\(on channel 0\\)"
-        - "Ping \\(on channel 1\\)"
-
-  sample.drivers.mbox.nrf54l15:
+  sample.drivers.mbox.nrf54l:
     platform_allow:
+      - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
+      - nrf54l20pdk/nrf54l20/cpuapp
     integration_platforms:
       - nrf54l15dk/nrf54l15/cpuapp
     extra_args: mbox_SNIPPET=nordic-flpr
@@ -99,9 +90,11 @@ tests:
         - "Ping \\(on channel 21\\)"
         - "Pong \\(on channel 20\\)"
 
-  sample.drivers.mbox.nrf54l15_no_multithreading:
+  sample.drivers.mbox.nrf54l_no_multithreading:
     platform_allow:
+      - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
+      - nrf54l20pdk/nrf54l20/cpuapp
     integration_platforms:
       - nrf54l15dk/nrf54l15/cpuapp
     extra_args:
@@ -117,9 +110,11 @@ tests:
         - "Ping \\(on channel 21\\)"
         - "Pong \\(on channel 20\\)"
 
-  sample.drivers.mbox.nrf54l15_remote_no_multithreading:
+  sample.drivers.mbox.nrf54l_remote_no_multithreading:
     platform_allow:
+      - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
+      - nrf54l20pdk/nrf54l20/cpuapp
     integration_platforms:
       - nrf54l15dk/nrf54l15/cpuapp
     extra_args:
diff --git a/samples/drivers/mbox/sysbuild.cmake b/samples/drivers/mbox/sysbuild.cmake
index e2a5a03b87e..31802733514 100644
--- a/samples/drivers/mbox/sysbuild.cmake
+++ b/samples/drivers/mbox/sysbuild.cmake
@@ -1,5 +1,5 @@
 # Copyright (c) 2023 Nordic Semiconductor ASA
-# Copyright 2023-2024 NXP
+# Copyright 2023-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 if("${SB_CONFIG_REMOTE_BOARD}" STREQUAL "")
@@ -22,6 +22,7 @@ native_simulator_set_final_executable(${DEFAULT_IMAGE})
 
 if(SB_CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 OR
    SB_CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7 OR
+   SB_CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33 OR
    SB_CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0)
   # For these NXP boards the main core application is dependent on
   # 'zephyr_image_info.h' generated by remote application.
diff --git a/samples/drivers/mbox_data/CMakeLists.txt b/samples/drivers/mbox_data/CMakeLists.txt
index e816cf7426f..52192878048 100644
--- a/samples/drivers/mbox_data/CMakeLists.txt
+++ b/samples/drivers/mbox_data/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -11,6 +11,9 @@ set(REMOTE_ZEPHYR_DIR ${CMAKE_CURRENT_BINARY_DIR}/../remote/zephyr)
 
 if(CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7 OR
    CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 OR
+   CONFIG_BOARD_FRDM_MCXN947_MCXN947_CPU0 OR
+   CONFIG_BOARD_MCX_N9XX_EVK_MCXN947_CPU0 OR
+   CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33 OR
    CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0)
   message(STATUS "${BOARD}${BOARD_QUALIFIERS} compile as Main in this sample")
 else()
diff --git a/samples/drivers/mbox_data/Kconfig.sysbuild b/samples/drivers/mbox_data/Kconfig.sysbuild
index 66a4e929ae2..d6388b3aa54 100644
--- a/samples/drivers/mbox_data/Kconfig.sysbuild
+++ b/samples/drivers/mbox_data/Kconfig.sysbuild
@@ -1,4 +1,4 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 
@@ -9,4 +9,7 @@ string
 	default "mimxrt1170_evkb/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evkb"
 	default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk"
 	default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk"
+	default "mimxrt1180_evk/mimxrt1189/cm7" if $(BOARD) = "mimxrt1180_evk"
 	default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69"
+	default "frdm_mcxn947/mcxn947/cpu1" if $(BOARD) = "frdm_mcxn947"
+	default "mcx_n9xx_evk/mcxn947/cpu1" if $(BOARD) = "mcx_n9xx_evk"
diff --git a/samples/drivers/mbox_data/README.rst b/samples/drivers/mbox_data/README.rst
index 1f8b1615f8e..b42a52e452f 100644
--- a/samples/drivers/mbox_data/README.rst
+++ b/samples/drivers/mbox_data/README.rst
@@ -36,21 +36,21 @@ Building the application for mimxrt1170_evk_cm7
    :goals: debug
    :west-args: --sysbuild
 
-Building the application for mimxrt1170_evkb_cm7
-================================================
+Building the application for lpcxpresso55s69_cpu1
+=================================================
 
 .. zephyr-app-commands::
    :zephyr-app: samples/drivers/mbox_data/
-   :board: mimxrt1170_evkb_cm7
+   :board: lpcxpresso55s69_cpu1
    :goals: debug
    :west-args: --sysbuild
 
-Building the application for lpcxpresso55s69_cpu1
-=================================================
+Building the application for frdm_mcxn947/mcxn947/cpu0
+======================================================
 
 .. zephyr-app-commands::
    :zephyr-app: samples/drivers/mbox_data/
-   :board: lpcxpresso55s69_cpu1
+   :board: frdm_mcxn947/mcxn947/cpu0
    :goals: debug
    :west-args: --sysbuild
 
diff --git a/samples/drivers/mbox_data/boards/frdm_mcxn947_mcxn947_cpu0.conf b/samples/drivers/mbox_data/boards/frdm_mcxn947_mcxn947_cpu0.conf
new file mode 100644
index 00000000000..7e6904d56d5
--- /dev/null
+++ b/samples/drivers/mbox_data/boards/frdm_mcxn947_mcxn947_cpu0.conf
@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/drivers/mbox_data/boards/frdm_mcxn947_mcxn947_cpu0.overlay b/samples/drivers/mbox_data/boards/frdm_mcxn947_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..42601e95336
--- /dev/null
+++ b/samples/drivers/mbox_data/boards/frdm_mcxn947_mcxn947_cpu0.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox 1>, <&mbox 0>;
+		mbox-names = "tx", "rx";
+	};
+};
diff --git a/samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay b/samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay
index 76773b87fcd..eafeeb83cba 100644
--- a/samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay
+++ b/samples/drivers/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay
@@ -6,7 +6,7 @@
 
 / {
 	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/drivers/mbox_data/boards/mcx_n9xx_evk_mcxn947_cpu0.conf b/samples/drivers/mbox_data/boards/mcx_n9xx_evk_mcxn947_cpu0.conf
new file mode 100644
index 00000000000..7e6904d56d5
--- /dev/null
+++ b/samples/drivers/mbox_data/boards/mcx_n9xx_evk_mcxn947_cpu0.conf
@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/drivers/mbox_data/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/samples/drivers/mbox_data/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..42601e95336
--- /dev/null
+++ b/samples/drivers/mbox_data/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox 1>, <&mbox 0>;
+		mbox-names = "tx", "rx";
+	};
+};
diff --git a/samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay
index c2014d3d809..0ed27fea4f3 100644
--- a/samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay
+++ b/samples/drivers/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay
@@ -6,7 +6,7 @@
 
 / {
 	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7.conf
similarity index 100%
rename from samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf
rename to samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7.conf
diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
new file mode 100644
index 00000000000..0ed27fea4f3
--- /dev/null
+++ b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		/* Delete ipc chosen property where old IPM mailbox driver below is
+		 * configured.
+		 */
+		/delete-property/ zephyr,ipc;
+	};
+
+	soc {
+		/* Delete IPM Driver node nxp,imx-mu */
+		/delete-node/ mailbox@40c48000;
+
+		/* Attach MBOX driver to MU Unit */
+		mbox:mbox@40c48000 {
+			compatible = "nxp,mbox-imx-mu";
+			reg = <0x40c48000 0x4000>;
+			interrupts = <118 0>;
+			rx-channels = <4>;
+			#mbox-cells = <1>;
+			status = "okay";
+		};
+	};
+
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox 3>, <&mbox 2>;
+		mbox-names = "tx", "rx";
+	};
+};
diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay
deleted file mode 100644
index c2014d3d809..00000000000
--- a/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2024 NXP
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
-	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
-		 * configured.
-		 */
-		/delete-property/ zephyr,ipc;
-	};
-
-	soc {
-		/* Delete IPM Driver node nxp,imx-mu */
-		/delete-node/ mailbox@40c48000;
-
-		/* Attach MBOX driver to MU Unit */
-		mbox:mbox@40c48000 {
-			compatible = "nxp,mbox-imx-mu";
-			reg = <0x40c48000 0x4000>;
-			interrupts = <118 0>;
-			rx-channels = <4>;
-			#mbox-cells = <1>;
-			status = "okay";
-		};
-	};
-
-	mbox-consumer {
-		compatible = "vnd,mbox-consumer";
-		mboxes = <&mbox 3>, <&mbox 2>;
-		mbox-names = "tx", "rx";
-	};
-};
diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf
deleted file mode 100644
index 0dfb100ed70..00000000000
--- a/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_MBOX_NXP_IMX_MU=y
-CONFIG_SECOND_CORE_MCUX=y
-CONFIG_INCLUDE_REMOTE_DIR=y
diff --git a/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
deleted file mode 100644
index c2014d3d809..00000000000
--- a/samples/drivers/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Copyright 2024 NXP
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
-	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
-		 * configured.
-		 */
-		/delete-property/ zephyr,ipc;
-	};
-
-	soc {
-		/* Delete IPM Driver node nxp,imx-mu */
-		/delete-node/ mailbox@40c48000;
-
-		/* Attach MBOX driver to MU Unit */
-		mbox:mbox@40c48000 {
-			compatible = "nxp,mbox-imx-mu";
-			reg = <0x40c48000 0x4000>;
-			interrupts = <118 0>;
-			rx-channels = <4>;
-			#mbox-cells = <1>;
-			status = "okay";
-		};
-	};
-
-	mbox-consumer {
-		compatible = "vnd,mbox-consumer";
-		mboxes = <&mbox 3>, <&mbox 2>;
-		mbox-names = "tx", "rx";
-	};
-};
diff --git a/samples/drivers/mbox_data/boards/mimxrt1180_evk_mimxrt1189_cm33.conf b/samples/drivers/mbox_data/boards/mimxrt1180_evk_mimxrt1189_cm33.conf
new file mode 100644
index 00000000000..60eead5a076
--- /dev/null
+++ b/samples/drivers/mbox_data/boards/mimxrt1180_evk_mimxrt1189_cm33.conf
@@ -0,0 +1,2 @@
+CONFIG_SECOND_CORE_MCUX=y
+CONFIG_INCLUDE_REMOTE_DIR=y
diff --git a/samples/drivers/mbox_data/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay b/samples/drivers/mbox_data/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
new file mode 100644
index 00000000000..9836b08ebe3
--- /dev/null
+++ b/samples/drivers/mbox_data/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox1_a 1>, <&mbox1_a 0>;
+		mbox-names = "tx", "rx";
+	};
+};
diff --git a/samples/drivers/mbox_data/remote/CMakeLists.txt b/samples/drivers/mbox_data/remote/CMakeLists.txt
index d3d0991a65c..efb3e573dce 100644
--- a/samples/drivers/mbox_data/remote/CMakeLists.txt
+++ b/samples/drivers/mbox_data/remote/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -9,6 +9,9 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
 
 if(CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM4 OR
    CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4 OR
+   CONFIG_BOARD_FRDM_MCXN947_MCXN947_CPU1 OR
+   CONFIG_BOARD_MCX_N9XX_EVK_MCXN947_CPU1 OR
+   CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM7 OR
    CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU1)
   message(STATUS "${BOARD}${BOARD_QUALIFIERS} compile as remote in this sample")
 else()
diff --git a/samples/drivers/mbox_data/remote/boards/frdm_mcxn947_mcxn947_cpu1.conf b/samples/drivers/mbox_data/remote/boards/frdm_mcxn947_mcxn947_cpu1.conf
new file mode 100644
index 00000000000..7e6904d56d5
--- /dev/null
+++ b/samples/drivers/mbox_data/remote/boards/frdm_mcxn947_mcxn947_cpu1.conf
@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/drivers/mbox_data/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay b/samples/drivers/mbox_data/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay
new file mode 100644
index 00000000000..4e3b4ae1208
--- /dev/null
+++ b/samples/drivers/mbox_data/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox 0>, <&mbox 1>;
+		mbox-names = "tx", "rx";
+	};
+};
diff --git a/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay b/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay
index c0d1a027087..5f623200d9e 100644
--- a/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay
+++ b/samples/drivers/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay
@@ -6,7 +6,7 @@
 
 / {
 	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/drivers/mbox_data/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.conf b/samples/drivers/mbox_data/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.conf
new file mode 100644
index 00000000000..7e6904d56d5
--- /dev/null
+++ b/samples/drivers/mbox_data/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.conf
@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/drivers/mbox_data/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay b/samples/drivers/mbox_data/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay
new file mode 100644
index 00000000000..4e3b4ae1208
--- /dev/null
+++ b/samples/drivers/mbox_data/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox 0>, <&mbox 1>;
+		mbox-names = "tx", "rx";
+	};
+};
diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay
index 42453413134..cb93c8b88cb 100644
--- a/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay
+++ b/samples/drivers/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay
@@ -10,7 +10,7 @@
 		zephyr,console = &lpuart2;
 		zephyr,shell-uart = &lpuart2;
 
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay
index 42453413134..cb93c8b88cb 100644
--- a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay
+++ b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay
@@ -10,7 +10,7 @@
 		zephyr,console = &lpuart2;
 		zephyr,shell-uart = &lpuart2;
 
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay
index 42453413134..cb93c8b88cb 100644
--- a/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay
+++ b/samples/drivers/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay
@@ -10,7 +10,7 @@
 		zephyr,console = &lpuart2;
 		zephyr,shell-uart = &lpuart2;
 
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.conf b/samples/drivers/mbox_data/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
new file mode 100644
index 00000000000..77adcfa24f4
--- /dev/null
+++ b/samples/drivers/mbox_data/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
@@ -0,0 +1,2 @@
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/drivers/mbox_data/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay b/samples/drivers/mbox_data/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
new file mode 100644
index 00000000000..db51f5184fd
--- /dev/null
+++ b/samples/drivers/mbox_data/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox1_b 0>, <&mbox1_b 1>;
+		mbox-names = "tx", "rx";
+	};
+};
diff --git a/samples/drivers/mbox_data/sample.yaml b/samples/drivers/mbox_data/sample.yaml
index 53390b5b16a..b874ec6e855 100644
--- a/samples/drivers/mbox_data/sample.yaml
+++ b/samples/drivers/mbox_data/sample.yaml
@@ -5,11 +5,7 @@ common:
   tags: mbox
 tests:
   sample.drivers.mbox_data.real_hw:
-    platform_allow:
-      - mimxrt1170_evk@B/mimxrt1176/cm7
-      - mimxrt1170_evk/mimxrt1176/cm7
-      - mimxrt1160_evk/mimxrt1166/cm7
-      - lpcxpresso55s69/lpc55s69/cpu0
+    filter: dt_compat_enabled("vnd,mbox-consumer")
     integration_platforms:
       - mimxrt1160_evk/mimxrt1166/cm7
       - lpcxpresso55s69/lpc55s69/cpu0
@@ -18,12 +14,12 @@ tests:
       type: multi_line
       ordered: false
       regex:
-        - "Client received \\(on channel 2\\) value: 1"
-        - "Client send \\(on channel 3\\) value: 2"
-        - "Client received \\(on channel 2\\) value: 3"
-        - "Client send \\(on channel 3\\) value: 4"
-        - "Client received \\(on channel 2\\) value: 41"
-        - "Client send \\(on channel 3\\) value: 42"
-        - "Client received \\(on channel 2\\) value: 97"
-        - "Client send \\(on channel 3\\) value: 98"
-        - "Client received \\(on channel 2\\) value: 99"
+        - "Client received .+ value: 1"
+        - "Client send .+ value: 2"
+        - "Client received .+ value: 3"
+        - "Client send .+ value: 4"
+        - "Client received .+ value: 41"
+        - "Client send .+ value: 42"
+        - "Client received .+ value: 97"
+        - "Client send .+ value: 98"
+        - "Client received .+ value: 99"
diff --git a/samples/drivers/mbox_data/sysbuild.cmake b/samples/drivers/mbox_data/sysbuild.cmake
index 0fb83fbadd3..dcb2509a05d 100644
--- a/samples/drivers/mbox_data/sysbuild.cmake
+++ b/samples/drivers/mbox_data/sysbuild.cmake
@@ -1,4 +1,4 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 
@@ -18,6 +18,7 @@ ExternalZephyrProject_Add(
 
 if(SB_CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 OR
    SB_CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7 OR
+   SB_CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33 OR
    SB_CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0)
   # For these NXP boards the main core application is dependent on
   # 'zephyr_image_info.h' generated by remote application.
diff --git a/samples/drivers/misc/ft800/src/main.c b/samples/drivers/misc/ft800/src/main.c
index 44178d9e143..48e763bb931 100644
--- a/samples/drivers/misc/ft800/src/main.c
+++ b/samples/drivers/misc/ft800/src/main.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <zephyr/device.h>
 #include <zephyr/kernel.h>
 
 #include <zephyr/drivers/misc/ft8xx/ft8xx.h>
@@ -23,22 +24,31 @@
 
 static volatile bool process_touch;
 
-static void touch_irq(void)
+static void touch_irq(const struct device *dev, void *user_data)
 {
+	(void)dev;
+	(void)user_data;
+
 	process_touch = true;
 }
 
 int main(void)
 {
+	const struct device *ft8xx = DEVICE_DT_GET_ONE(ftdi_ft800);
 	int cnt;
 	int val;
 	struct ft8xx_touch_transform tt;
 
+	if (!device_is_ready(ft8xx)) {
+		printk("FT8xx device is not ready. Aborting\n");
+		return -1;
+	}
+
 	/* To get touch events calibrate the display */
-	ft8xx_calibrate(&tt);
+	ft8xx_calibrate(ft8xx, &tt);
 
 	/* Get interrupts on touch event */
-	ft8xx_register_int(touch_irq);
+	ft8xx_register_int(ft8xx, touch_irq, NULL);
 
 	/* Starting counting */
 	val = 0;
@@ -46,40 +56,40 @@ int main(void)
 
 	while (1) {
 		/* Start Display List */
-		ft8xx_copro_cmd_dlstart();
-		ft8xx_copro_cmd(FT8XX_CLEAR_COLOR_RGB(0x00, 0x00, 0x00));
-		ft8xx_copro_cmd(FT8XX_CLEAR(1, 1, 1));
+		ft8xx_copro_cmd_dlstart(ft8xx);
+		ft8xx_copro_cmd(ft8xx, FT8XX_CLEAR_COLOR_RGB(0x00, 0x00, 0x00));
+		ft8xx_copro_cmd(ft8xx, FT8XX_CLEAR(1, 1, 1));
 
 		/* Set color */
-		ft8xx_copro_cmd(FT8XX_COLOR_RGB(0xf0, 0xf0, 0xf0));
+		ft8xx_copro_cmd(ft8xx, FT8XX_COLOR_RGB(0xf0, 0xf0, 0xf0));
 
 		/* Display the counter */
-		ft8xx_copro_cmd_number(20, 20, 29, FT8XX_OPT_SIGNED, cnt);
+		ft8xx_copro_cmd_number(ft8xx, 20, 20, 29, FT8XX_OPT_SIGNED, cnt);
 		cnt++;
 
 		/* Display the hello message */
-		ft8xx_copro_cmd_text(20, 70, 30, 0, "Hello,");
+		ft8xx_copro_cmd_text(ft8xx, 20, 70, 30, 0, "Hello,");
 		/* Set Zephyr color */
-		ft8xx_copro_cmd(FT8XX_COLOR_RGB(0x78, 0x29, 0xd2));
-		ft8xx_copro_cmd_text(20, 105, 30, 0, "Zephyr!");
+		ft8xx_copro_cmd(ft8xx, FT8XX_COLOR_RGB(0x78, 0x29, 0xd2));
+		ft8xx_copro_cmd_text(ft8xx, 20, 105, 30, 0, "Zephyr!");
 
 		/* Display value set with buttons */
-		ft8xx_copro_cmd(FT8XX_COLOR_RGB(0xff, 0xff, 0xff));
-		ft8xx_copro_cmd_number(80, 170, 29,
+		ft8xx_copro_cmd(ft8xx, FT8XX_COLOR_RGB(0xff, 0xff, 0xff));
+		ft8xx_copro_cmd_number(ft8xx, 80, 170, 29,
 					FT8XX_OPT_SIGNED | FT8XX_OPT_RIGHTX,
 					val);
-		ft8xx_copro_cmd(FT8XX_TAG(TAG_PLUS));
-		ft8xx_copro_cmd_text(90, 160, 31, 0, "+");
-		ft8xx_copro_cmd(FT8XX_TAG(TAG_MINUS));
-		ft8xx_copro_cmd_text(20, 160, 31, 0, "-");
+		ft8xx_copro_cmd(ft8xx, FT8XX_TAG(TAG_PLUS));
+		ft8xx_copro_cmd_text(ft8xx, 90, 160, 31, 0, "+");
+		ft8xx_copro_cmd(ft8xx, FT8XX_TAG(TAG_MINUS));
+		ft8xx_copro_cmd_text(ft8xx, 20, 160, 31, 0, "-");
 
 		/* Finish Display List */
-		ft8xx_copro_cmd(FT8XX_DISPLAY());
+		ft8xx_copro_cmd(ft8xx, FT8XX_DISPLAY());
 		/* Display created frame */
-		ft8xx_copro_cmd_swap();
+		ft8xx_copro_cmd_swap(ft8xx);
 
 		if (process_touch) {
-			int tag = ft8xx_get_touch_tag();
+			int tag = ft8xx_get_touch_tag(ft8xx);
 
 			if (tag == TAG_PLUS) {
 				val++;
diff --git a/samples/drivers/mspi/mspi_flash/sample.yaml b/samples/drivers/mspi/mspi_flash/sample.yaml
index db742ac8f46..0e6abf8406c 100644
--- a/samples/drivers/mspi/mspi_flash/sample.yaml
+++ b/samples/drivers/mspi/mspi_flash/sample.yaml
@@ -20,3 +20,5 @@ tests:
         - "Attempting to write 4 bytes"
         - "Data read matches data written. Good!!"
     depends_on: mspi
+    integration_platforms:
+      - apollo3p_evb
diff --git a/samples/drivers/spi_flash/boards/blackpill_f411ce.overlay b/samples/drivers/spi_flash/boards/blackpill_f411ce.overlay
new file mode 100644
index 00000000000..d4c0e4c1482
--- /dev/null
+++ b/samples/drivers/spi_flash/boards/blackpill_f411ce.overlay
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2025 Javad Rahimipetroudi <javad.rahimipetroudi@mind.be>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* NOTES:
+ *  1- BlackPill board may be offered with/without soldered flash chips,
+ *  Modify the following configuration based on your chip properties.
+ *  2- If you are using V3.1 board, you may need to change miso port. Please
+ *  check the schematic before any change.
+ */
+
+&spi1 {
+	pinctrl-0 = <&spi1_sck_pa5  &spi1_miso_pb4 &spi1_mosi_pa7>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpioa 4 GPIO_ACTIVE_LOW>;
+
+	status = "okay";
+
+	w25q64_spi: spi-nor-flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+		size = <DT_SIZE_M(64)>; /* 64 Mbits */
+		status = "okay";
+		jedec-id = [ef 40 17];
+		has-dpd;
+		t-enter-dpd = <3500>;
+		t-exit-dpd = <3500>;
+	};
+};
diff --git a/samples/drivers/spi_flash/boards/max32655evkit_max32655_m4.conf b/samples/drivers/spi_flash/boards/max32655evkit_max32655_m4.conf
new file mode 100644
index 00000000000..e8a061fe077
--- /dev/null
+++ b/samples/drivers/spi_flash/boards/max32655evkit_max32655_m4.conf
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2025 Analog Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_SPI_MAX32_INTERRUPT=y
diff --git a/samples/drivers/spi_flash_at45/sample.yaml b/samples/drivers/spi_flash_at45/sample.yaml
index c362fa5a693..e7a25239a2b 100644
--- a/samples/drivers/spi_flash_at45/sample.yaml
+++ b/samples/drivers/spi_flash_at45/sample.yaml
@@ -1,44 +1,27 @@
 sample:
   name: SPI Flash AT45 Sample
+common:
+  depends_on: spi
+  filter: dt_compat_enabled("atmel,at45")
+  integration_platforms:
+    - sam4l_wm400_cape
+  tags:
+    - spi
+    - flash
 tests:
   sample.drivers.spi.flash.at45.build:
-    tags:
-      - spi
-      - flash
-    depends_on: spi
-    filter: dt_compat_enabled("atmel,at45")
     build_only: true
   sample.drivers.spi.flash.at45.build.page_layout:
     extra_args: EXTRA_CONF_FILE="overlay-page_layout.conf"
-    tags:
-      - spi
-      - flash
-    depends_on: spi
-    filter: dt_compat_enabled("atmel,at45")
     build_only: true
   sample.drivers.spi.flash.at45.build.pm:
     extra_args: EXTRA_CONF_FILE="overlay-pm.conf"
-    tags:
-      - spi
-      - flash
-    depends_on: spi
-    filter: dt_compat_enabled("atmel,at45")
     build_only: true
   sample.drivers.spi.flash.at45.build.page_layout_pm:
     extra_args: EXTRA_CONF_FILE="overlay-page_layout.conf;overlay-pm.conf"
-    tags:
-      - spi
-      - flash
-    depends_on: spi
-    filter: dt_compat_enabled("atmel,at45")
     build_only: true
   sample.drivers.spi.flash.at45:
     extra_args: EXTRA_CONF_FILE="overlay-page_layout.conf;overlay-pm.conf"
-    tags:
-      - spi
-      - flash
-    depends_on: spi
-    filter: dt_compat_enabled("atmel,at45")
     harness: console
     harness_config:
       type: multi_line
diff --git a/samples/drivers/stepper/generic/CMakeLists.txt b/samples/drivers/stepper/generic/CMakeLists.txt
new file mode 100644
index 00000000000..3139442c041
--- /dev/null
+++ b/samples/drivers/stepper/generic/CMakeLists.txt
@@ -0,0 +1,10 @@
+ # SPDX-FileCopyrightText: Copyright (c) 2025 Jilay Sandeep Pandya
+ # SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(stepper_generic)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/samples/drivers/stepper/generic/Kconfig b/samples/drivers/stepper/generic/Kconfig
new file mode 100644
index 00000000000..a9259ff3b8a
--- /dev/null
+++ b/samples/drivers/stepper/generic/Kconfig
@@ -0,0 +1,26 @@
+# SPDX-FileCopyrightText: Copyright (c) 2025 Jilay Sandeep Pandya
+# SPDX-License-Identifier: Apache-2.0
+
+mainmenu "Stepper generic sample application"
+
+config STEPS_PER_REV
+	int "Steps per revolution"
+	default 200
+
+config STEP_INTERVAL_NS
+	int "Step interval (ns)"
+	default 1000000
+
+config PING_PONG_N_REV
+	int "Change direction every N revolutions"
+	default 1
+
+config MONITOR_THREAD_TIMEOUT_MS
+	int "Monitor thread timeout (ms)"
+	default 1000
+
+config MONITOR_THREAD_STACK_SIZE
+	int "Monitor thread stack size"
+	default 1024
+
+source "Kconfig.zephyr"
diff --git a/samples/drivers/stepper/generic/README.rst b/samples/drivers/stepper/generic/README.rst
new file mode 100644
index 00000000000..e23461f8d77
--- /dev/null
+++ b/samples/drivers/stepper/generic/README.rst
@@ -0,0 +1,56 @@
+.. zephyr:code-sample:: stepper
+   :name: Stepper
+   :relevant-api: stepper_interface
+
+   Rotate a stepper motor in 4 different modes.
+
+Description
+***********
+
+This sample demonstrates how to use the stepper driver API to control a stepper motor. The sample
+spins, enables, disables, stops the stepper and outputs the events to the console.
+
+The stepper spins in 4 different modes: ping_pong_relative, ping_pong_absolute, continuous_clockwise
+and continuous_anticlockwise. The micro-step interval in nanoseconds can be configured using the
+:kconfig:option:`CONFIG_STEP_INTERVAL_NS`. The sample also demonstrates how to use the stepper callback
+to change the direction of the stepper after a certain number of steps.
+
+Pressing any button should change the mode of the stepper. The mode is printed to the console.
+Following modes are supported: enable, ping_pong_relative, ping_pong_absolute, rotate_cw, rotate_ccw,
+stop and disable.
+
+The sample also has a monitor thread that prints the actual position of the stepper motor every
+:kconfig:option:`CONFIG_MONITOR_THREAD_TIMEOUT_MS` milliseconds.
+
+Building and Running
+********************
+
+This project spins the stepper and outputs the events to the console.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/drivers/stepper/generic
+   :board: nucleo_g071rb
+   :goals: build flash
+
+Sample Output
+=============
+
+.. code-block:: console
+
+   *** Booting Zephyr OS build v4.1.0-568-gad33d28d0348 ***
+   [00:00:00.000,000] <inf> stepper: Starting generic stepper sample
+   [00:00:00.000,000] <dbg> stepper: main: stepper is 0x80086b8, name is gpio_stepper
+   [00:00:00.000,000] <dbg> gpio_stepper_motor_controller: gpio_stepper_set_microstep_interval: Setting Motor step interval to 1000000
+   [00:00:00.000,000] <dbg> stepper: monitor_thread: Actual position: 0
+   [00:00:00.491,000] <inf> stepper: mode: enable
+   [00:00:00.876,000] <inf> stepper: mode: ping pong relative
+   [00:00:01.000,000] <dbg> stepper: monitor_thread: Actual position: -114
+   [00:00:01.237,000] <inf> stepper: mode: ping pong absolute
+   [00:00:01.564,000] <inf> stepper: mode: rotate cw
+   [00:00:01.871,000] <inf> stepper: mode: rotate ccw
+   [00:00:02.000,000] <dbg> stepper: monitor_thread: Actual position: 129
+   [00:00:02.164,000] <inf> stepper: mode: stop
+   [00:00:02.444,000] <inf> stepper: mode: disable
+   [00:00:02.755,000] <inf> stepper: mode: enable
+
+   <repeats endlessly>
diff --git a/samples/drivers/stepper/generic/boards/nucleo_g071rb.overlay b/samples/drivers/stepper/generic/boards/nucleo_g071rb.overlay
new file mode 100644
index 00000000000..e392a028cb3
--- /dev/null
+++ b/samples/drivers/stepper/generic/boards/nucleo_g071rb.overlay
@@ -0,0 +1,17 @@
+/ {
+	aliases {
+		stepper = &gpio_stepper;
+	};
+};
+
+/ {
+	gpio_stepper: gpio_stepper {
+		compatible = "zephyr,gpio-stepper";
+		status = "okay";
+		micro-step-res = <2>;
+		gpios = <&gpioa 9 GPIO_ACTIVE_HIGH>,	/* D8 */
+			<&gpioc 7 GPIO_ACTIVE_HIGH>,	/* D9 */
+			<&gpiob 0 GPIO_ACTIVE_HIGH>,	/* D10 */
+			<&gpioa 7 GPIO_ACTIVE_HIGH>;	/* D11 */
+	};
+};
diff --git a/samples/drivers/stepper/generic/prj.conf b/samples/drivers/stepper/generic/prj.conf
new file mode 100644
index 00000000000..7b579deb99f
--- /dev/null
+++ b/samples/drivers/stepper/generic/prj.conf
@@ -0,0 +1,3 @@
+CONFIG_STEPPER=y
+CONFIG_LOG=y
+CONFIG_INPUT=y
diff --git a/samples/drivers/stepper/generic/sample.yaml b/samples/drivers/stepper/generic/sample.yaml
new file mode 100644
index 00000000000..765b3b35c6e
--- /dev/null
+++ b/samples/drivers/stepper/generic/sample.yaml
@@ -0,0 +1,8 @@
+sample:
+  name: Generic Stepper Sample
+tests:
+  sample.drivers.stepper.generic:
+    harness: stepper
+    tags: stepper
+    platform_allow: nucleo_g071rb
+    depends_on: gpio input
diff --git a/samples/drivers/stepper/generic/src/main.c b/samples/drivers/stepper/generic/src/main.c
new file mode 100644
index 00000000000..f1323e50850
--- /dev/null
+++ b/samples/drivers/stepper/generic/src/main.c
@@ -0,0 +1,128 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2025 Jilay Sandeep Pandya.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/stepper.h>
+#include <zephyr/input/input.h>
+#include <zephyr/kernel.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(stepper, CONFIG_STEPPER_LOG_LEVEL);
+
+static const struct device *stepper = DEVICE_DT_GET(DT_ALIAS(stepper));
+
+enum stepper_mode {
+	STEPPER_MODE_ENABLE,
+	STEPPER_MODE_PING_PONG_RELATIVE,
+	STEPPER_MODE_PING_PONG_ABSOLUTE,
+	STEPPER_MODE_ROTATE_CW,
+	STEPPER_MODE_ROTATE_CCW,
+	STEPPER_MODE_STOP,
+	STEPPER_MODE_DISABLE,
+};
+
+static atomic_t stepper_mode = ATOMIC_INIT(STEPPER_MODE_DISABLE);
+
+static int32_t ping_pong_target_position =
+	CONFIG_STEPS_PER_REV * CONFIG_PING_PONG_N_REV * DT_PROP(DT_ALIAS(stepper), micro_step_res);
+
+static K_SEM_DEFINE(stepper_generic_sem, 0, 1);
+
+static void stepper_callback(const struct device *dev, const enum stepper_event event,
+			     void *user_data)
+{
+	switch (event) {
+	case STEPPER_EVENT_STEPS_COMPLETED:
+		k_sem_give(&stepper_generic_sem);
+		break;
+	default:
+		break;
+	}
+}
+
+static void button_pressed(struct input_event *event, void *user_data)
+{
+	ARG_UNUSED(user_data);
+
+	if (event->value == 0 && event->type == INPUT_EV_KEY) {
+		return;
+	}
+	enum stepper_mode mode = atomic_get(&stepper_mode);
+
+	if (mode == STEPPER_MODE_DISABLE) {
+		atomic_set(&stepper_mode, STEPPER_MODE_ENABLE);
+	} else {
+		atomic_inc(&stepper_mode);
+	}
+	k_sem_give(&stepper_generic_sem);
+}
+
+INPUT_CALLBACK_DEFINE(NULL, button_pressed, NULL);
+
+int main(void)
+{
+	LOG_INF("Starting generic stepper sample\n");
+	if (!device_is_ready(stepper)) {
+		LOG_ERR("Device %s is not ready\n", stepper->name);
+		return -ENODEV;
+	}
+	LOG_DBG("stepper is %p, name is %s\n", stepper, stepper->name);
+
+	stepper_set_event_callback(stepper, stepper_callback, NULL);
+	stepper_set_reference_position(stepper, 0);
+	stepper_set_microstep_interval(stepper, CONFIG_STEP_INTERVAL_NS);
+
+	for (;;) {
+		k_sem_take(&stepper_generic_sem, K_FOREVER);
+		switch (atomic_get(&stepper_mode)) {
+		case STEPPER_MODE_ENABLE:
+			stepper_enable(stepper);
+			LOG_INF("mode: enable\n");
+			break;
+		case STEPPER_MODE_STOP:
+			stepper_stop(stepper);
+			LOG_INF("mode: stop\n");
+			break;
+		case STEPPER_MODE_ROTATE_CW:
+			stepper_run(stepper, STEPPER_DIRECTION_POSITIVE);
+			LOG_INF("mode: rotate cw\n");
+			break;
+		case STEPPER_MODE_ROTATE_CCW:
+			stepper_run(stepper, STEPPER_DIRECTION_NEGATIVE);
+			LOG_INF("mode: rotate ccw\n");
+			break;
+		case STEPPER_MODE_PING_PONG_RELATIVE:
+			ping_pong_target_position *= -1;
+			stepper_move_by(stepper, ping_pong_target_position);
+			LOG_INF("mode: ping pong relative\n");
+			break;
+		case STEPPER_MODE_PING_PONG_ABSOLUTE:
+			ping_pong_target_position *= -1;
+			stepper_move_to(stepper, ping_pong_target_position);
+			LOG_INF("mode: ping pong absolute\n");
+			break;
+		case STEPPER_MODE_DISABLE:
+			stepper_disable(stepper);
+			LOG_INF("mode: disable\n");
+			break;
+		}
+	}
+	return 0;
+}
+
+static void monitor_thread(void)
+{
+	for (;;) {
+		int32_t actual_position;
+
+		stepper_get_actual_position(stepper, &actual_position);
+		LOG_DBG("Actual position: %d\n", actual_position);
+		k_sleep(K_MSEC(CONFIG_MONITOR_THREAD_TIMEOUT_MS));
+	}
+}
+
+K_THREAD_DEFINE(monitor_tid, CONFIG_MONITOR_THREAD_STACK_SIZE, monitor_thread, NULL, NULL, NULL, 5,
+		0, 0);
diff --git a/samples/drivers/stepper/index.rst b/samples/drivers/stepper/index.rst
new file mode 100644
index 00000000000..7592d15577c
--- /dev/null
+++ b/samples/drivers/stepper/index.rst
@@ -0,0 +1,5 @@
+.. zephyr:code-sample-category:: stepper
+   :name: Stepper
+   :show-listing:
+
+   These samples demonstrate how to use the :ref:`stepper <stepper_api>` driver API.
diff --git a/samples/drivers/stepper/tmc50xx/CMakeLists.txt b/samples/drivers/stepper/tmc50xx/CMakeLists.txt
new file mode 100644
index 00000000000..7d5a7d600f2
--- /dev/null
+++ b/samples/drivers/stepper/tmc50xx/CMakeLists.txt
@@ -0,0 +1,10 @@
+ # SPDX-FileCopyrightText: Copyright (c) 2025 Jilay Sandeep Pandya
+ # SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(tmc50xx)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/samples/drivers/stepper/tmc50xx/Kconfig b/samples/drivers/stepper/tmc50xx/Kconfig
new file mode 100644
index 00000000000..59e2cc9f8d6
--- /dev/null
+++ b/samples/drivers/stepper/tmc50xx/Kconfig
@@ -0,0 +1,18 @@
+# SPDX-FileCopyrightText: Copyright (c) 2025 Jilay Sandeep Pandya
+# SPDX-License-Identifier: Apache-2.0
+
+mainmenu "TMC50XX sample application"
+
+config STEPS_PER_REV
+	int "Steps per revolution"
+	default 200
+
+config PING_PONG_N_REV
+	int "Change direction every N revolutions"
+	default 1
+
+config MAX_VELOCITY_MULTIPLIER
+	int "Max velocity multiplier"
+	default 1
+
+source "Kconfig.zephyr"
diff --git a/samples/drivers/stepper/tmc50xx/README.rst b/samples/drivers/stepper/tmc50xx/README.rst
new file mode 100644
index 00000000000..75e2dd22ee0
--- /dev/null
+++ b/samples/drivers/stepper/tmc50xx/README.rst
@@ -0,0 +1,48 @@
+.. zephyr:code-sample:: tmc50xx
+   :name: TMC50XX stepper
+   :relevant-api: stepper_interface
+
+   Rotate a TMC50XX stepper motor and change velocity at runtime.
+
+Description
+***********
+
+This sample application periodically spins the stepper clockwise and counterclockwise depending on
+the :kconfig:option:`CONFIG_PING_PONG_N_REV` configuration.
+
+References
+**********
+
+ - TMC5041: https://www.analog.com/media/en/technical-documentation/data-sheets/TMC5041_datasheet_rev1.16.pdf
+ - TMC5072: https://www.analog.com/media/en/technical-documentation/data-sheets/TMC5072_datasheet_rev1.26.pdf
+
+Wiring
+*******
+
+This sample uses the TMC5072 BOB controlled using the SPI interface. The board's Devicetree must define
+a ``stepper`` alias for the stepper motor node.
+
+Building and Running
+********************
+
+This project spins the stepper and outputs the events to the console. It requires an TMC50XX stepper
+driver. It should work with any platform featuring a SPI peripheral interface.
+It does not work on QEMU.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/drivers/stepper/tmc50xx
+   :board: nucleo_g071rb
+   :goals: build flash
+
+Sample Output
+=============
+
+.. code-block:: console
+
+   Starting tmc50xx stepper sample
+   stepper is 0x8007240, name is tmc_stepper@0
+   stepper_callback steps completed changing direction
+   stepper_callback steps completed changing direction
+   stepper_callback steps completed changing direction
+
+   <repeats endlessly>
diff --git a/samples/drivers/stepper/tmc50xx/boards/nucleo_g071rb.overlay b/samples/drivers/stepper/tmc50xx/boards/nucleo_g071rb.overlay
new file mode 100644
index 00000000000..e3b70a35531
--- /dev/null
+++ b/samples/drivers/stepper/tmc50xx/boards/nucleo_g071rb.overlay
@@ -0,0 +1,52 @@
+/ {
+	aliases {
+		stepper = &tmc_stepper;
+	};
+};
+
+&spi1 {
+	pinctrl-0 = <&spi1_sck_pa5 &spi1_miso_pa6 &spi1_mosi_pa7>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpiob 0 GPIO_ACTIVE_LOW>;
+	status = "okay";
+	tmc50xx: tmc50xx@0 {
+		compatible = "adi,tmc50xx";
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_M(1)>; /* Maximum SPI bus frequency */
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		clock-frequency = <DT_FREQ_M(10)>; /* Internal/External Clock frequency */
+
+		tmc_stepper: tmc_stepper@0 {
+			status = "okay";
+			reg = <0>;
+
+			/* common stepper controller settings */
+			micro-step-res = <256>;
+
+			/* ADI TMC stallguard settings specific to TMC50XX */
+			activate-stallguard2;
+			stallguard-velocity-check-interval-ms=<1000>;
+			stallguard2-threshold=<30>;
+			stallguard-threshold-velocity=<200000>;
+
+			/* ADI TMC ramp generator as well as current settings */
+			vstart = <1000>;
+			vstop = <10>;
+			a1 = <10000>;
+			v1 = <50000>;
+			d1 = <14000>;
+			vmax = <900000>;
+			amax = <50000>;
+			dmax = <7000>;
+			tzerowait = <100>;
+			vhigh = <900000>;
+			vcoolthrs = <900000>;
+			ihold = <1>;
+			irun = <10>;
+			iholddelay = <1>;
+		};
+	};
+};
diff --git a/samples/drivers/stepper/tmc50xx/prj.conf b/samples/drivers/stepper/tmc50xx/prj.conf
new file mode 100644
index 00000000000..f17d0707cf5
--- /dev/null
+++ b/samples/drivers/stepper/tmc50xx/prj.conf
@@ -0,0 +1,2 @@
+CONFIG_STEPPER=y
+CONFIG_LOG=y
diff --git a/samples/drivers/stepper/tmc50xx/sample.yaml b/samples/drivers/stepper/tmc50xx/sample.yaml
new file mode 100644
index 00000000000..dddd010d191
--- /dev/null
+++ b/samples/drivers/stepper/tmc50xx/sample.yaml
@@ -0,0 +1,8 @@
+sample:
+  name: TMC50XX Stepper Sample
+tests:
+  sample.drivers.stepper.tmc50xx:
+    harness: stepper
+    tags: stepper
+    platform_allow: nucleo_g071rb
+    depends_on: spi
diff --git a/samples/drivers/stepper/tmc50xx/src/main.c b/samples/drivers/stepper/tmc50xx/src/main.c
new file mode 100644
index 00000000000..8604f610c96
--- /dev/null
+++ b/samples/drivers/stepper/tmc50xx/src/main.c
@@ -0,0 +1,55 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2025 Jilay Sandeep Pandya.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/stepper.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/stepper/stepper_trinamic.h>
+
+const struct device *stepper = DEVICE_DT_GET(DT_ALIAS(stepper));
+
+int32_t ping_pong_target_position = CONFIG_STEPS_PER_REV * CONFIG_PING_PONG_N_REV *
+				    DT_PROP(DT_ALIAS(stepper), micro_step_res);
+
+K_SEM_DEFINE(steps_completed_sem, 0, 1);
+
+void stepper_callback(const struct device *dev, const enum stepper_event event, void *user_data)
+{
+	switch (event) {
+	case STEPPER_EVENT_STEPS_COMPLETED:
+		k_sem_give(&steps_completed_sem);
+		break;
+	default:
+		break;
+	}
+}
+
+int main(void)
+{
+	printf("Starting tmc50xx stepper sample\n");
+	if (!device_is_ready(stepper)) {
+		printf("Device %s is not ready\n", stepper->name);
+		return -ENODEV;
+	}
+	printf("stepper is %p, name is %s\n", stepper, stepper->name);
+
+	stepper_set_event_callback(stepper, stepper_callback, NULL);
+	stepper_enable(stepper);
+	stepper_set_reference_position(stepper, 0);
+	stepper_move_by(stepper, ping_pong_target_position);
+
+	/* Change Max Velocity during runtime */
+	int32_t tmc_velocity = DT_PROP(DT_ALIAS(stepper), vmax) * CONFIG_MAX_VELOCITY_MULTIPLIER;
+	(void)tmc50xx_stepper_set_max_velocity(stepper, tmc_velocity);
+
+	for (;;) {
+		if (k_sem_take(&steps_completed_sem, K_FOREVER) == 0) {
+			ping_pong_target_position *= -1;
+			stepper_move_by(stepper, ping_pong_target_position);
+		}
+	}
+	return 0;
+}
diff --git a/samples/drivers/uart/native_tty/boards/native_posix.overlay b/samples/drivers/uart/native_tty/boards/native_posix.overlay
deleted file mode 100644
index 6a3daca3241..00000000000
--- a/samples/drivers/uart/native_tty/boards/native_posix.overlay
+++ /dev/null
@@ -1 +0,0 @@
-#include "native_sim.overlay"
diff --git a/samples/drivers/uart/native_tty/sample.yaml b/samples/drivers/uart/native_tty/sample.yaml
index 1e059d9ce3a..a8d570701e1 100644
--- a/samples/drivers/uart/native_tty/sample.yaml
+++ b/samples/drivers/uart/native_tty/sample.yaml
@@ -4,7 +4,6 @@ tests:
   sample.drivers.uart.native_tty:
     build_only: true
     platform_allow:
-      - native_posix
       - native_sim
     tags:
       - serial
diff --git a/samples/drivers/video/capture/README.rst b/samples/drivers/video/capture/README.rst
index 823e263ebdc..2a8fefc0ff0 100644
--- a/samples/drivers/video/capture/README.rst
+++ b/samples/drivers/video/capture/README.rst
@@ -24,7 +24,7 @@ Supported camera modules on some i.MX RT boards can be found below.
 - :zephyr:board:`mimxrt1170_evk`
 - `OV5640 camera module`_
 
-Also :ref:`arduino_nicla_vision_board` can be used in this sample as capture device, in that case
+Also :zephyr:board:`arduino_nicla_vision` can be used in this sample as capture device, in that case
 The user can transfer the captured frames through on board USB.
 
 Wiring
@@ -38,7 +38,7 @@ On :zephyr:board:`mimxrt1170_evk`, the OV5640 camera module should be plugged in
 J2 camera connector. A USB cable should be connected from a host to the micro
 USB debug connector (J11) in order to get console output via the daplink interface.
 
-For :ref:`arduino_nicla_vision_board` there is no extra wiring required.
+For :zephyr:board:`arduino_nicla_vision` there is no extra wiring required.
 
 Building and Running
 ********************
@@ -61,7 +61,8 @@ For :zephyr:board:`mimxrt1170_evk`, build this sample application with the follo
    :goals: build
    :compact:
 
-For :ref:`arduino_nicla_vision_board`, build this sample application with the following commands:
+For :zephyr:board:`arduino_nicla_vision`, build this sample application with the following
+commands:
 
 .. zephyr-app-commands::
    :zephyr-app: samples/drivers/video/capture
diff --git a/samples/drivers/video/capture/boards/esp32s3_eye_procpu.conf b/samples/drivers/video/capture/boards/esp32s3_eye_procpu.conf
index 76321800fa0..24a8455c94b 100644
--- a/samples/drivers/video/capture/boards/esp32s3_eye_procpu.conf
+++ b/samples/drivers/video/capture/boards/esp32s3_eye_procpu.conf
@@ -9,3 +9,4 @@ CONFIG_VIDEO_BUFFER_SMH_ATTRIBUTE=2
 CONFIG_VIDEO_FRAME_HEIGHT=240
 CONFIG_VIDEO_FRAME_WIDTH=240
 CONFIG_VIDEO_PIXEL_FORMAT="RGBP"
+CONFIG_ST7789V_BGR565=y
diff --git a/samples/drivers/video/capture/src/main.c b/samples/drivers/video/capture/src/main.c
index 10af7ef7d9e..501ebd8794a 100644
--- a/samples/drivers/video/capture/src/main.c
+++ b/samples/drivers/video/capture/src/main.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2019 Linaro Limited
+ * Copyright 2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -120,11 +121,10 @@ int main(void)
 	while (caps.format_caps[i].pixelformat) {
 		const struct video_format_cap *fcap = &caps.format_caps[i];
 		/* fourcc to string */
-		LOG_INF("  %c%c%c%c width [%u; %u; %u] height [%u; %u; %u]",
-		       (char)fcap->pixelformat, (char)(fcap->pixelformat >> 8),
-		       (char)(fcap->pixelformat >> 16), (char)(fcap->pixelformat >> 24),
-		       fcap->width_min, fcap->width_max, fcap->width_step, fcap->height_min,
-		       fcap->height_max, fcap->height_step);
+		LOG_INF("  %s width [%u; %u; %u] height [%u; %u; %u]",
+		       VIDEO_FOURCC_TO_STR(fcap->pixelformat),
+		       fcap->width_min, fcap->width_max, fcap->width_step,
+		       fcap->height_min, fcap->height_max, fcap->height_step);
 		i++;
 	}
 
@@ -144,14 +144,11 @@ int main(void)
 #endif
 
 	if (strcmp(CONFIG_VIDEO_PIXEL_FORMAT, "")) {
-		fmt.pixelformat =
-			video_fourcc(CONFIG_VIDEO_PIXEL_FORMAT[0], CONFIG_VIDEO_PIXEL_FORMAT[1],
-				     CONFIG_VIDEO_PIXEL_FORMAT[2], CONFIG_VIDEO_PIXEL_FORMAT[3]);
+		fmt.pixelformat = VIDEO_FOURCC_FROM_STR(CONFIG_VIDEO_PIXEL_FORMAT);
 	}
 
-	LOG_INF("- Video format: %c%c%c%c %ux%u", (char)fmt.pixelformat,
-	       (char)(fmt.pixelformat >> 8), (char)(fmt.pixelformat >> 16),
-	       (char)(fmt.pixelformat >> 24), fmt.width, fmt.height);
+	LOG_INF("- Video format: %s %ux%u",
+		VIDEO_FOURCC_TO_STR(fmt.pixelformat), fmt.width, fmt.height);
 
 	if (video_set_format(video_dev, VIDEO_EP_OUT, &fmt)) {
 		LOG_ERR("Unable to set format");
@@ -178,13 +175,26 @@ int main(void)
 		fie.index++;
 	}
 
+	/* Get supported controls */
+	LOG_INF("- Supported controls:");
+
+	struct video_ctrl_query cq = {.id = VIDEO_CTRL_FLAG_NEXT_CTRL};
+
+	while (!video_query_ctrl(video_dev, &cq)) {
+		video_print_ctrl(video_dev, &cq);
+		cq.id |= VIDEO_CTRL_FLAG_NEXT_CTRL;
+	}
+
 	/* Set controls */
+	struct video_control ctrl = {.id = VIDEO_CID_HFLIP, .val = 1};
+
 	if (IS_ENABLED(CONFIG_VIDEO_CTRL_HFLIP)) {
-		video_set_ctrl(video_dev, VIDEO_CID_HFLIP, (void *)1);
+		video_set_ctrl(video_dev, &ctrl);
 	}
 
 #ifdef CONFIG_TEST
-	video_set_ctrl(video_dev, VIDEO_CID_TEST_PATTERN, (void *)1);
+	ctrl.id = VIDEO_CID_TEST_PATTERN;
+	video_set_ctrl(video_dev, &ctrl);
 #endif
 
 #if DT_HAS_CHOSEN(zephyr_display)
diff --git a/samples/drivers/video/capture_to_lvgl/boards/stm32h7b3i_dk.conf b/samples/drivers/video/capture_to_lvgl/boards/stm32h7b3i_dk.conf
new file mode 100644
index 00000000000..bb4f8b12a92
--- /dev/null
+++ b/samples/drivers/video/capture_to_lvgl/boards/stm32h7b3i_dk.conf
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2025 Charles Dias <charlesdias.cd@outlook.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_LOG_BUFFER_SIZE=2048
+
+CONFIG_VIDEO_WIDTH=480
+CONFIG_VIDEO_HEIGHT=272
+CONFIG_VIDEO_BUFFER_POOL_SZ_MAX=262144
diff --git a/samples/drivers/video/capture_to_lvgl/boards/stm32h7b3i_dk.overlay b/samples/drivers/video/capture_to_lvgl/boards/stm32h7b3i_dk.overlay
new file mode 100644
index 00000000000..b9e8ba05e94
--- /dev/null
+++ b/samples/drivers/video/capture_to_lvgl/boards/stm32h7b3i_dk.overlay
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025 Charles Dias <charlesdias.cd@outlook.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+/delete-node/ &sram1;
+/delete-node/ &sram2;
+
+/* Increase the SRAM0 bank memory size to accommodate the VIDEO_BUFFER_POOL_SZ_MAX configuration. */
+&sram0 {
+	reg = <0x24000000 DT_SIZE_K(1024)>;
+};
diff --git a/samples/drivers/video/capture_to_lvgl/src/main.c b/samples/drivers/video/capture_to_lvgl/src/main.c
index ab57c9a52a5..201e0a8bed9 100644
--- a/samples/drivers/video/capture_to_lvgl/src/main.c
+++ b/samples/drivers/video/capture_to_lvgl/src/main.c
@@ -106,21 +106,17 @@ int main(void)
 		video_enqueue(video_dev, VIDEO_EP_OUT, buffers[i]);
 	}
 
-#ifdef CONFIG_VIDEO_HFLIP
-	/* Video flip image horizontally */
-	if (video_set_ctrl(video_dev, VIDEO_CID_HFLIP, (void *)1)) {
-		LOG_ERR("Unable to set video control (HFLIP)");
-		return 0;
+	/* Set controls */
+	struct video_control ctrl = {.id = VIDEO_CID_HFLIP, .val = 1};
+
+	if (IS_ENABLED(CONFIG_VIDEO_HFLIP)) {
+		video_set_ctrl(video_dev, &ctrl);
 	}
-#endif
 
-#ifdef CONFIG_VIDEO_VFLIP
-	/* Video flip image vertically */
-	if (video_set_ctrl(video_dev, VIDEO_CID_VFLIP, (void *)1)) {
-		LOG_ERR("Unable to set video control (VFLIP)");
-		return 0;
+	if (IS_ENABLED(CONFIG_VIDEO_VFLIP)) {
+		ctrl.id = VIDEO_CID_VFLIP;
+		video_set_ctrl(video_dev, &ctrl);
 	}
-#endif
 
 	/* Start video capture */
 	if (video_stream_start(video_dev)) {
diff --git a/samples/drivers/video/tcpserversink/src/main.c b/samples/drivers/video/tcpserversink/src/main.c
index af728d85887..da3f9e4a831 100644
--- a/samples/drivers/video/tcpserversink/src/main.c
+++ b/samples/drivers/video/tcpserversink/src/main.c
@@ -94,9 +94,8 @@ int main(void)
 		return 0;
 	}
 
-	printk("Video device detected, format: %c%c%c%c %ux%u\n", (char)fmt.pixelformat,
-	       (char)(fmt.pixelformat >> 8), (char)(fmt.pixelformat >> 16),
-	       (char)(fmt.pixelformat >> 24), fmt.width, fmt.height);
+	printk("Video device detected, format: %s %ux%u\n",
+		VIDEO_FOURCC_TO_STR(fmt.pixelformat), fmt.width, fmt.height);
 
 	if (caps.min_line_count != LINE_COUNT_HEIGHT) {
 		LOG_ERR("Partial framebuffers not supported by this sample");
diff --git a/samples/drivers/w1/scanner/boards/max32655evkit_max32655_m4.overlay b/samples/drivers/w1/scanner/boards/max32655evkit_max32655_m4.overlay
new file mode 100644
index 00000000000..b39b6bfd394
--- /dev/null
+++ b/samples/drivers/w1/scanner/boards/max32655evkit_max32655_m4.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&owm_io_p0_6 {
+	power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&owm_pe_p0_7 {
+	power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&w1 {
+	status = "okay";
+	internal-pullup = <1>;
+	external-pullup = <0>;
+};
diff --git a/samples/drivers/w1/scanner/boards/max32666evkit_max32666_cpu0.overlay b/samples/drivers/w1/scanner/boards/max32666evkit_max32666_cpu0.overlay
new file mode 100644
index 00000000000..eee8e0fc933
--- /dev/null
+++ b/samples/drivers/w1/scanner/boards/max32666evkit_max32666_cpu0.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&owm_io_p0_4 {
+	power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&owm_pe_p0_5 {
+	power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&w1 {
+	status = "okay";
+	internal-pullup = <1>;
+	external-pullup = <0>;
+};
diff --git a/samples/drivers/w1/scanner/boards/max32666fthr_max32666_cpu0.overlay b/samples/drivers/w1/scanner/boards/max32666fthr_max32666_cpu0.overlay
new file mode 100644
index 00000000000..90602378976
--- /dev/null
+++ b/samples/drivers/w1/scanner/boards/max32666fthr_max32666_cpu0.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&owm_io_p0_12 {
+	power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&owm_pe_p0_13 {
+	power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&w1 {
+	status = "okay";
+	internal-pullup = <1>;
+	external-pullup = <0>;
+};
diff --git a/samples/drivers/w1/scanner/boards/max32690evkit_max32690_m4.overlay b/samples/drivers/w1/scanner/boards/max32690evkit_max32690_m4.overlay
new file mode 100644
index 00000000000..31b91be77b7
--- /dev/null
+++ b/samples/drivers/w1/scanner/boards/max32690evkit_max32690_m4.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&owm_io_p0_8 {
+	power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&owm_pe_p0_7 {
+	power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&w1 {
+	status = "okay";
+	internal-pullup = <1>;
+	external-pullup = <0>;
+};
diff --git a/samples/drivers/w1/scanner/boards/max78000evkit_max78000_m4.overlay b/samples/drivers/w1/scanner/boards/max78000evkit_max78000_m4.overlay
new file mode 100644
index 00000000000..933dd2f3de9
--- /dev/null
+++ b/samples/drivers/w1/scanner/boards/max78000evkit_max78000_m4.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&owm_io_p0_18 {
+	power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&owm_pe_p0_19 {
+	power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&w1 {
+	status = "okay";
+	internal-pullup = <1>;
+	external-pullup = <0>;
+};
diff --git a/samples/drivers/w1/scanner/boards/max78000fthr_max78000_m4.overlay b/samples/drivers/w1/scanner/boards/max78000fthr_max78000_m4.overlay
new file mode 100644
index 00000000000..933dd2f3de9
--- /dev/null
+++ b/samples/drivers/w1/scanner/boards/max78000fthr_max78000_m4.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&owm_io_p0_18 {
+	power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&owm_pe_p0_19 {
+	power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&w1 {
+	status = "okay";
+	internal-pullup = <1>;
+	external-pullup = <0>;
+};
diff --git a/samples/drivers/w1/scanner/boards/max78002evkit_max78002_m4.overlay b/samples/drivers/w1/scanner/boards/max78002evkit_max78002_m4.overlay
new file mode 100644
index 00000000000..b39b6bfd394
--- /dev/null
+++ b/samples/drivers/w1/scanner/boards/max78002evkit_max78002_m4.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&owm_io_p0_6 {
+	power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&owm_pe_p0_7 {
+	power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&w1 {
+	status = "okay";
+	internal-pullup = <1>;
+	external-pullup = <0>;
+};
diff --git a/samples/drivers/w1/scanner/sample.yaml b/samples/drivers/w1/scanner/sample.yaml
index 9a610bf63f1..776eb3babb5 100644
--- a/samples/drivers/w1/scanner/sample.yaml
+++ b/samples/drivers/w1/scanner/sample.yaml
@@ -3,6 +3,8 @@ sample:
 
 common:
   harness: console
+  tags:
+    - w1
 
 tests:
   sample.drivers.w1.scanner.ds2482-800:
@@ -25,7 +27,7 @@ tests:
       regex:
         - "Number of devices found on bus: .*"
       fixture: w1_scanner_ds2484
-  samples.drivers.w1.scanner.ds2485:
+  sample.drivers.w1.scanner.ds2485:
     depends_on: arduino_i2c
     extra_args: DTC_OVERLAY_FILE=ds2485.overlay
     platform_allow:
@@ -36,7 +38,7 @@ tests:
       regex:
         - "Number of devices found on bus: .*"
       fixture: w1_scanner_ds2485
-  samples.drivers.w1.scanner.w1_serial:
+  sample.drivers.w1.scanner.w1_serial:
     depends_on:
       - arduino_serial
     extra_args: DTC_OVERLAY_FILE=w1_serial.overlay
@@ -48,3 +50,20 @@ tests:
       regex:
         - "Number of devices found on bus: .*"
       fixture: w1_scanner_w1_serial
+  sample.drivers.w1.scanner.max:
+    depends_on: w1
+    platform_allow:
+      - max32655evkit/max32655/m4
+      - max32666evkit/max32666/cpu0
+      - max32666fthr/max32666/cpu0
+      - max32690evkit/max32690/m4
+      - max78000evkit/max78000/m4
+      - max78000fthr/max78000/m4
+      - max78002evkit/max78002/m4
+    integration_platforms:
+      - max32655evkit/max32655/m4
+    harness_config:
+      type: one_line
+      regex:
+        - "Number of devices found on bus: .*"
+      fixture: w1_scanner_w1_max
diff --git a/samples/drivers/watchdog/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay b/samples/drivers/watchdog/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay
new file mode 100644
index 00000000000..d1c11622866
--- /dev/null
+++ b/samples/drivers/watchdog/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/samples/drivers/watchdog/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/samples/drivers/watchdog/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..d1c11622866
--- /dev/null
+++ b/samples/drivers/watchdog/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/samples/drivers/watchdog/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay b/samples/drivers/watchdog/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..d1c11622866
--- /dev/null
+++ b/samples/drivers/watchdog/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/samples/drivers/watchdog/boards/bl54l15_dvk_nrf54l15_cpuflpr_xip.overlay b/samples/drivers/watchdog/boards/bl54l15_dvk_nrf54l15_cpuflpr_xip.overlay
new file mode 100644
index 00000000000..d1c11622866
--- /dev/null
+++ b/samples/drivers/watchdog/boards/bl54l15_dvk_nrf54l15_cpuflpr_xip.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/samples/drivers/watchdog/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/samples/drivers/watchdog/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..d1c11622866
--- /dev/null
+++ b/samples/drivers/watchdog/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/samples/drivers/watchdog/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay b/samples/drivers/watchdog/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..d1c11622866
--- /dev/null
+++ b/samples/drivers/watchdog/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/samples/drivers/watchdog/boards/bl54l15u_dvk_nrf54l15_cpuflpr_xip.overlay b/samples/drivers/watchdog/boards/bl54l15u_dvk_nrf54l15_cpuflpr_xip.overlay
new file mode 100644
index 00000000000..d1c11622866
--- /dev/null
+++ b/samples/drivers/watchdog/boards/bl54l15u_dvk_nrf54l15_cpuflpr_xip.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/samples/drivers/watchdog/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay b/samples/drivers/watchdog/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay
new file mode 100644
index 00000000000..cfb41e09b99
--- /dev/null
+++ b/samples/drivers/watchdog/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/samples/drivers/watchdog/boards/nrf54l09pdk_nrf54l09_cpuflpr.overlay b/samples/drivers/watchdog/boards/nrf54l09pdk_nrf54l09_cpuflpr.overlay
new file mode 100644
index 00000000000..cfb41e09b99
--- /dev/null
+++ b/samples/drivers/watchdog/boards/nrf54l09pdk_nrf54l09_cpuflpr.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/samples/drivers/watchdog/boards/nrf54l20pdk_nrf54l20_cpuflpr.overlay b/samples/drivers/watchdog/boards/nrf54l20pdk_nrf54l20_cpuflpr.overlay
new file mode 100644
index 00000000000..cfb41e09b99
--- /dev/null
+++ b/samples/drivers/watchdog/boards/nrf54l20pdk_nrf54l20_cpuflpr.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/samples/drivers/watchdog/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/samples/drivers/watchdog/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..025e0b8aedb
--- /dev/null
+++ b/samples/drivers/watchdog/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/samples/drivers/watchdog/boards/ophelia4ev_nrf54l15_cpuflpr.overlay b/samples/drivers/watchdog/boards/ophelia4ev_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..025e0b8aedb
--- /dev/null
+++ b/samples/drivers/watchdog/boards/ophelia4ev_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/samples/drivers/watchdog/boards/siwx917_rb4338a.overlay b/samples/drivers/watchdog/boards/siwx917_rb4338a.overlay
new file mode 100644
index 00000000000..bccfe1a3d69
--- /dev/null
+++ b/samples/drivers/watchdog/boards/siwx917_rb4338a.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		watchdog0 = &watchdog;
+	};
+};
+
+&watchdog {
+	status = "okay";
+};
diff --git a/samples/drivers/watchdog/sample.yaml b/samples/drivers/watchdog/sample.yaml
index ce97a6f9213..5360cd386a5 100644
--- a/samples/drivers/watchdog/sample.yaml
+++ b/samples/drivers/watchdog/sample.yaml
@@ -22,6 +22,14 @@ tests:
       - s32z2xxdc2/s32z270/rtu1
       - s32z2xxdc2@D/s32z270/rtu0
       - s32z2xxdc2@D/s32z270/rtu1
+      - panb511evb/nrf54l15/cpuapp
+      - panb511evb/nrf54l15/cpuflpr
+      - panb511evb/nrf54l15/cpuflpr/xip
+      - nrf54l15dk/nrf54l15/cpuapp/ns
+      - nrf54l15dk/nrf54l10/cpuapp/ns
+      - bl54l15_dvk/nrf54l10/cpuapp/ns
+      - bl54l15_dvk/nrf54l15/cpuapp/ns
+      - bl54l15u_dvk/nrf54l15/cpuapp/ns
   sample.drivers.watchdog.stm32_wwdg:
     extra_args: DTC_OVERLAY_FILE=boards/stm32_wwdg.overlay
     filter: dt_compat_enabled("st,stm32-window-watchdog")
diff --git a/samples/drivers/watchdog/src/main.c b/samples/drivers/watchdog/src/main.c
index cad88ebcf66..faeb79c5b8a 100644
--- a/samples/drivers/watchdog/src/main.c
+++ b/samples/drivers/watchdog/src/main.c
@@ -40,6 +40,8 @@
 #define WDT_MIN_WINDOW	320U
 #define WDT_OPT 0
 #define WDG_FEED_INTERVAL (WDT_MIN_WINDOW + ((WDT_MAX_WINDOW - WDT_MIN_WINDOW) / 4))
+#elif DT_HAS_COMPAT_STATUS_OKAY(renesas_ra_wdt)
+#define WDT_ALLOW_CALLBACK 0
 #endif
 
 #ifndef WDT_ALLOW_CALLBACK
diff --git a/samples/fuel_gauge/max17048/boards/adafruit_feather_esp32s2_C.conf b/samples/fuel_gauge/max17048/boards/adafruit_feather_esp32s2_C.conf
new file mode 100644
index 00000000000..0968fb220e0
--- /dev/null
+++ b/samples/fuel_gauge/max17048/boards/adafruit_feather_esp32s2_C.conf
@@ -0,0 +1,4 @@
+CONFIG_POWER_DOMAIN=y
+CONFIG_GPIO=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_DEVICE_POWER_DOMAIN=y
diff --git a/samples/fuel_gauge/max17048/boards/adafruit_feather_esp32s2_C.overlay b/samples/fuel_gauge/max17048/boards/adafruit_feather_esp32s2_C.overlay
new file mode 100644
index 00000000000..66298554285
--- /dev/null
+++ b/samples/fuel_gauge/max17048/boards/adafruit_feather_esp32s2_C.overlay
@@ -0,0 +1,8 @@
+&i2c0 {
+	max17048: max17048@36 {
+		compatible = "maxim,max17048";
+		status = "okay";
+		reg = <0x36 >;
+		power-domains = <&i2c_reg>;
+	};
+};
diff --git a/samples/fuel_gauge/max17048/boards/adafruit_feather_esp32s2_tft.conf b/samples/fuel_gauge/max17048/boards/adafruit_feather_esp32s2_tft.conf
new file mode 100644
index 00000000000..0968fb220e0
--- /dev/null
+++ b/samples/fuel_gauge/max17048/boards/adafruit_feather_esp32s2_tft.conf
@@ -0,0 +1,4 @@
+CONFIG_POWER_DOMAIN=y
+CONFIG_GPIO=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_DEVICE_POWER_DOMAIN=y
diff --git a/samples/fuel_gauge/max17048/boards/adafruit_feather_esp32s2_tft.overlay b/samples/fuel_gauge/max17048/boards/adafruit_feather_esp32s2_tft.overlay
new file mode 100644
index 00000000000..66298554285
--- /dev/null
+++ b/samples/fuel_gauge/max17048/boards/adafruit_feather_esp32s2_tft.overlay
@@ -0,0 +1,8 @@
+&i2c0 {
+	max17048: max17048@36 {
+		compatible = "maxim,max17048";
+		status = "okay";
+		reg = <0x36 >;
+		power-domains = <&i2c_reg>;
+	};
+};
diff --git a/samples/fuel_gauge/max17048/boards/adafruit_feather_esp32s2_tft_reverse.conf b/samples/fuel_gauge/max17048/boards/adafruit_feather_esp32s2_tft_reverse.conf
new file mode 100644
index 00000000000..0968fb220e0
--- /dev/null
+++ b/samples/fuel_gauge/max17048/boards/adafruit_feather_esp32s2_tft_reverse.conf
@@ -0,0 +1,4 @@
+CONFIG_POWER_DOMAIN=y
+CONFIG_GPIO=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_DEVICE_POWER_DOMAIN=y
diff --git a/samples/fuel_gauge/max17048/boards/adafruit_feather_esp32s3_procpu.conf b/samples/fuel_gauge/max17048/boards/adafruit_feather_esp32s3_procpu.conf
new file mode 100644
index 00000000000..0968fb220e0
--- /dev/null
+++ b/samples/fuel_gauge/max17048/boards/adafruit_feather_esp32s3_procpu.conf
@@ -0,0 +1,4 @@
+CONFIG_POWER_DOMAIN=y
+CONFIG_GPIO=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_DEVICE_POWER_DOMAIN=y
diff --git a/samples/hello_world/sample.yaml b/samples/hello_world/sample.yaml
index 1bcb7db62f2..ac4dfeac52d 100644
--- a/samples/hello_world/sample.yaml
+++ b/samples/hello_world/sample.yaml
@@ -3,6 +3,8 @@ sample:
     application
   name: hello world
 common:
+  min_ram: 2
+  min_flash: 16
   tags: introduction
   integration_platforms:
     - native_sim
diff --git a/samples/modules/lvgl/accelerometer_chart/README.rst b/samples/modules/lvgl/accelerometer_chart/README.rst
index a41f79a091b..c572ffcbc11 100644
--- a/samples/modules/lvgl/accelerometer_chart/README.rst
+++ b/samples/modules/lvgl/accelerometer_chart/README.rst
@@ -25,7 +25,7 @@ Requirements
 .. note::
 
    A Devicetree overlay declaring an emulated BMI160 accelerometer is provided for the
-   ``native_posix*`` and ``native_sim*`` board variants, making it possible to run this sample on
+   ``native_sim*`` board variants, making it possible to run this sample on
    your local machine.
 
 .. _lvgl_accelerometer_chart_building_and_running:
diff --git a/samples/modules/lvgl/accelerometer_chart/boards/native_posix.overlay b/samples/modules/lvgl/accelerometer_chart/boards/native_posix.overlay
deleted file mode 100644
index dc4174b58d7..00000000000
--- a/samples/modules/lvgl/accelerometer_chart/boards/native_posix.overlay
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright (c) 2023 Benjamin Cabé <benjamin@zephyrproject.org>
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
-	aliases {
-		accel0 = &bmi_i2c;
-	};
-};
-
-&i2c0 {
-	bmi_i2c: bmi@68 {
-		compatible = "bosch,bmi160";
-		reg = <0x68>;
-	};
-};
diff --git a/samples/modules/lvgl/accelerometer_chart/boards/native_sim.overlay b/samples/modules/lvgl/accelerometer_chart/boards/native_sim.overlay
index 2b055bf3de6..dc4174b58d7 100644
--- a/samples/modules/lvgl/accelerometer_chart/boards/native_sim.overlay
+++ b/samples/modules/lvgl/accelerometer_chart/boards/native_sim.overlay
@@ -1 +1,16 @@
-#include "native_posix.overlay"
+/* Copyright (c) 2023 Benjamin Cabé <benjamin@zephyrproject.org>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		accel0 = &bmi_i2c;
+	};
+};
+
+&i2c0 {
+	bmi_i2c: bmi@68 {
+		compatible = "bosch,bmi160";
+		reg = <0x68>;
+	};
+};
diff --git a/samples/modules/lvgl/accelerometer_chart/boards/native_posix.conf b/samples/modules/lvgl/accelerometer_chart/boards/native_sim_native_64.conf
similarity index 100%
rename from samples/modules/lvgl/accelerometer_chart/boards/native_posix.conf
rename to samples/modules/lvgl/accelerometer_chart/boards/native_sim_native_64.conf
diff --git a/samples/modules/lvgl/accelerometer_chart/boards/native_sim_native_64.overlay b/samples/modules/lvgl/accelerometer_chart/boards/native_sim_native_64.overlay
new file mode 100644
index 00000000000..d4b0ac659d8
--- /dev/null
+++ b/samples/modules/lvgl/accelerometer_chart/boards/native_sim_native_64.overlay
@@ -0,0 +1,5 @@
+/* Copyright (c) 2023 Benjamin Cabé <benjamin@zephyrproject.org>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "native_sim.overlay"
diff --git a/samples/modules/lvgl/demos/boards/native_posix.conf b/samples/modules/lvgl/demos/boards/native_posix.conf
deleted file mode 100644
index a99f38b8d84..00000000000
--- a/samples/modules/lvgl/demos/boards/native_posix.conf
+++ /dev/null
@@ -1,4 +0,0 @@
-# Copyright 2023 Fabian Blatz <fabianblatz@gmail.com>
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_LV_COLOR_DEPTH_32=y
diff --git a/samples/modules/lvgl/demos/boards/native_posix.overlay b/samples/modules/lvgl/demos/boards/native_posix.overlay
deleted file mode 100644
index eab17f916bd..00000000000
--- a/samples/modules/lvgl/demos/boards/native_posix.overlay
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2023, Fabian Blatz <fabianblatz@gmail.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&sdl_dc {
-	compatible = "zephyr,sdl-dc";
-	height = <272>;
-	width = <480>;
-};
diff --git a/samples/modules/lvgl/demos/boards/native_posix_64.overlay b/samples/modules/lvgl/demos/boards/native_posix_64.overlay
deleted file mode 100644
index eab17f916bd..00000000000
--- a/samples/modules/lvgl/demos/boards/native_posix_64.overlay
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2023, Fabian Blatz <fabianblatz@gmail.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&sdl_dc {
-	compatible = "zephyr,sdl-dc";
-	height = <272>;
-	width = <480>;
-};
diff --git a/samples/modules/lvgl/demos/boards/native_posix_native_64.conf b/samples/modules/lvgl/demos/boards/native_posix_native_64.conf
deleted file mode 100644
index c7a2f1ff941..00000000000
--- a/samples/modules/lvgl/demos/boards/native_posix_native_64.conf
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright 2023 Fabian Blatz <fabianblatz@gmail.com>
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_LV_COLOR_DEPTH_32=y
-CONFIG_LV_Z_MEM_POOL_SIZE=65536
diff --git a/samples/modules/lvgl/demos/boards/native_sim.overlay b/samples/modules/lvgl/demos/boards/native_sim.overlay
index ab50aa66f82..eab17f916bd 100644
--- a/samples/modules/lvgl/demos/boards/native_sim.overlay
+++ b/samples/modules/lvgl/demos/boards/native_sim.overlay
@@ -3,4 +3,9 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#include "native_posix.overlay"
+
+&sdl_dc {
+	compatible = "zephyr,sdl-dc";
+	height = <272>;
+	width = <480>;
+};
diff --git a/samples/modules/lvgl/demos/boards/native_sim_64.overlay b/samples/modules/lvgl/demos/boards/native_sim_64.overlay
index ab50aa66f82..47fdc4be34c 100644
--- a/samples/modules/lvgl/demos/boards/native_sim_64.overlay
+++ b/samples/modules/lvgl/demos/boards/native_sim_64.overlay
@@ -3,4 +3,4 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#include "native_posix.overlay"
+#include "native_sim.overlay"
diff --git a/samples/modules/lvgl/demos/boards/native_sim_native_64.conf b/samples/modules/lvgl/demos/boards/native_sim_native_64.conf
index c7a2f1ff941..36220318e8a 100644
--- a/samples/modules/lvgl/demos/boards/native_sim_native_64.conf
+++ b/samples/modules/lvgl/demos/boards/native_sim_native_64.conf
@@ -2,4 +2,4 @@
 # SPDX-License-Identifier: Apache-2.0
 
 CONFIG_LV_COLOR_DEPTH_32=y
-CONFIG_LV_Z_MEM_POOL_SIZE=65536
+CONFIG_LV_Z_MEM_POOL_SIZE=75264
diff --git a/samples/modules/lvgl/demos/prj.conf b/samples/modules/lvgl/demos/prj.conf
index aad236d1c36..4b7ab1bb7db 100644
--- a/samples/modules/lvgl/demos/prj.conf
+++ b/samples/modules/lvgl/demos/prj.conf
@@ -3,7 +3,7 @@ CONFIG_LOG=y
 CONFIG_SHELL=y
 
 CONFIG_LVGL=y
-CONFIG_LV_Z_MEM_POOL_SIZE=49152
+CONFIG_LV_Z_MEM_POOL_SIZE=58368
 CONFIG_LV_Z_SHELL=y
 CONFIG_LV_USE_MONKEY=y
 
diff --git a/samples/modules/lvgl/demos/rtk7eka6m3b00001bu.overlay b/samples/modules/lvgl/demos/rtk7eka6m3b00001bu.overlay
new file mode 100644
index 00000000000..8bfc4173581
--- /dev/null
+++ b/samples/modules/lvgl/demos/rtk7eka6m3b00001bu.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	lvgl_pointer {
+		compatible = "zephyr,lvgl-pointer-input";
+		swap-xy;
+		input = <&ft5336_rtk7eka6m3b00001bu>;
+	};
+};
diff --git a/samples/modules/lvgl/demos/sample.yaml b/samples/modules/lvgl/demos/sample.yaml
index 4fdb529d998..1d9a9b306a9 100644
--- a/samples/modules/lvgl/demos/sample.yaml
+++ b/samples/modules/lvgl/demos/sample.yaml
@@ -97,3 +97,21 @@ tests:
       - shield
       - lvgl
       - gui
+  sample.modules.lvgl.demos.rtk7eka6m3b00001bu:
+    platform_allow: ek_ra8d1
+    harness: console
+    harness_config:
+      fixture: fixture_display
+    extra_args:
+      - SHIELD=rtk7eka6m3b00001bu
+      - DTC_OVERLAY_FILE=rtk7eka6m3b00001bu.overlay
+    extra_configs:
+      - CONFIG_LV_DEMO_MUSIC_LANDSCAPE=y
+    modules:
+      - lvgl
+    tags:
+      - samples
+      - display
+      - shield
+      - lvgl
+      - gui
diff --git a/samples/modules/lvgl/screen_transparency/src/main.c b/samples/modules/lvgl/screen_transparency/src/main.c
index b0e6164fc8b..16faa7a1927 100644
--- a/samples/modules/lvgl/screen_transparency/src/main.c
+++ b/samples/modules/lvgl/screen_transparency/src/main.c
@@ -44,7 +44,7 @@ int main(void)
 	}
 
 	display_get_capabilities(display_dev, &display_caps);
-	if (!(display_caps.supported_pixel_formats | PIXEL_FORMAT_ARGB_8888)) {
+	if (!(display_caps.supported_pixel_formats & PIXEL_FORMAT_ARGB_8888)) {
 		LOG_ERR("Display does not support ARGB8888 mode");
 		return -ENOTSUP;
 	}
diff --git a/samples/modules/pmci/index.rst b/samples/modules/pmci/index.rst
new file mode 100644
index 00000000000..23c10268122
--- /dev/null
+++ b/samples/modules/pmci/index.rst
@@ -0,0 +1,5 @@
+.. zephyr:code-sample-category:: pmci
+   :name: PMCI
+   :show-listing:
+
+   These samples demonstrate the use of PMCI related protocols in Zephyr.
diff --git a/samples/modules/pmci/mctp/endpoint/CMakeLists.txt b/samples/modules/pmci/mctp/endpoint/CMakeLists.txt
new file mode 100644
index 00000000000..e3f4e04676a
--- /dev/null
+++ b/samples/modules/pmci/mctp/endpoint/CMakeLists.txt
@@ -0,0 +1,7 @@
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+project(mctp_endpoint)
+
+target_sources(app PRIVATE src/main.c)
diff --git a/samples/modules/pmci/mctp/endpoint/README.rst b/samples/modules/pmci/mctp/endpoint/README.rst
new file mode 100644
index 00000000000..a7e2f28047f
--- /dev/null
+++ b/samples/modules/pmci/mctp/endpoint/README.rst
@@ -0,0 +1,41 @@
+.. zephyr:code-sample:: mctp_endpoint_sample
+   :name: MCTP Endpoint Sample
+
+   Create an MCTP endpoint over UART.
+
+Overview
+********
+Sets up an MCTP node that listens on a UART for messages targeting a particular
+MCTP endpoint id with the message "hello". Responds to this "hello" message with
+"world".
+
+Requirements
+************
+A board and SoC that provide access to a UART and a driver that implements the
+UART async API.
+
+Wiring
+******
+The listening UART pins should be wired to a board which will run the MCTP host
+sample such that this board's UART tx pin connects to the host board's rx pin,
+and this board's UART rx pin connects to the host board's tx pin. The boards'
+grounds should also be wired together.
+
+Optionally a logic analyzer can be wired up and listening to the UART to inspect
+the data flowing.
+
+Building and Running
+********************
+
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/modules/pmci/mctp/endpoint
+   :host-os: unix
+   :board: nrf52840_nrf52840dk
+   :goals: run
+   :compact:
+
+References
+**********
+
+`MCTP Base Specification 2019 <https://www.dmtf.org/sites/default/files/standards/documents/DSP0236_1.3.1.pdf>`_
diff --git a/samples/modules/pmci/mctp/endpoint/boards/nrf52840dk_nrf52840.overlay b/samples/modules/pmci/mctp/endpoint/boards/nrf52840dk_nrf52840.overlay
new file mode 100644
index 00000000000..48c7f840dca
--- /dev/null
+++ b/samples/modules/pmci/mctp/endpoint/boards/nrf52840dk_nrf52840.overlay
@@ -0,0 +1,3 @@
+&arduino_serial{
+	status = "okay";
+};
diff --git a/samples/modules/pmci/mctp/endpoint/prj.conf b/samples/modules/pmci/mctp/endpoint/prj.conf
new file mode 100644
index 00000000000..495c9ca12fa
--- /dev/null
+++ b/samples/modules/pmci/mctp/endpoint/prj.conf
@@ -0,0 +1,8 @@
+CONFIG_SERIAL=y
+CONFIG_UART_ASYNC_API=y
+CONFIG_MCTP=y
+CONFIG_MCTP_UART=y
+CONFIG_LOG=y
+CONFIG_LOG_BUFFER_SIZE=4096
+CONFIG_MCTP_LOG_LEVEL_DBG=y
+CONFIG_ISR_STACK_SIZE=4096
diff --git a/samples/modules/pmci/mctp/endpoint/src/main.c b/samples/modules/pmci/mctp/endpoint/src/main.c
new file mode 100644
index 00000000000..66a2afa465a
--- /dev/null
+++ b/samples/modules/pmci/mctp/endpoint/src/main.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2024 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <assert.h>
+#include <unistd.h>
+#include <zephyr/kernel.h>
+#include <zephyr/types.h>
+#include <zephyr/pmci/mctp/mctp_uart.h>
+#include <libmctp.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(mctp_endpoint);
+
+#include <zephyr/drivers/uart.h>
+
+static struct mctp *mctp_ctx;
+
+#define LOCAL_HELLO_EID 10
+
+#define REMOTE_HELLO_EID 20
+
+K_SEM_DEFINE(mctp_rx, 0, 1);
+
+static void rx_message(uint8_t eid, bool tag_owner, uint8_t msg_tag, void *data, void *msg,
+		       size_t len)
+{
+	switch (eid) {
+	case REMOTE_HELLO_EID:
+		LOG_INF("got mctp message %s for eid %d, replying to 5 with \"world\"", (char *)msg,
+			eid);
+		mctp_message_tx(mctp_ctx, LOCAL_HELLO_EID, false, 0, "world", sizeof("world"));
+		break;
+	default:
+		LOG_INF("Unknown endpoint %d", eid);
+		break;
+	}
+
+	k_sem_give(&mctp_rx);
+}
+
+MCTP_UART_DT_DEFINE(mctp_endpoint, DEVICE_DT_GET(DT_NODELABEL(arduino_serial)));
+
+#define RX_BUF_SZ 128
+
+int main(void)
+{
+	LOG_INF("MCTP Endpoint EID:%d on %s\n", LOCAL_HELLO_EID, CONFIG_BOARD_TARGET);
+
+	mctp_set_alloc_ops(malloc, free, realloc);
+	mctp_ctx = mctp_init();
+	__ASSERT_NO_MSG(mctp_ctx != NULL);
+	mctp_register_bus(mctp_ctx, &mctp_endpoint.binding, LOCAL_HELLO_EID);
+	mctp_set_rx_all(mctp_ctx, rx_message, NULL);
+
+	/* MCTP poll loop */
+	while (true) {
+		mctp_uart_start_rx(&mctp_endpoint);
+		k_sem_take(&mctp_rx, K_FOREVER);
+	}
+
+	LOG_INF("exiting");
+	return 0;
+}
diff --git a/samples/modules/pmci/mctp/host/CMakeLists.txt b/samples/modules/pmci/mctp/host/CMakeLists.txt
new file mode 100644
index 00000000000..4b19d992eb2
--- /dev/null
+++ b/samples/modules/pmci/mctp/host/CMakeLists.txt
@@ -0,0 +1,6 @@
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(mctp_host)
+
+target_sources(app PRIVATE src/main.c)
diff --git a/samples/modules/pmci/mctp/host/README.rst b/samples/modules/pmci/mctp/host/README.rst
new file mode 100644
index 00000000000..e1eb0abf756
--- /dev/null
+++ b/samples/modules/pmci/mctp/host/README.rst
@@ -0,0 +1,40 @@
+.. zephyr:code-sample:: mctp_host_sample
+   :name: MCTP Host Sample
+
+   Create an MCTP host over UART.
+
+Overview
+********
+Sets up an MCTP node that sends a request on a UART targeting a particular MCTP
+endpoint id with the message "hello". Expects and waits for a response to this
+"hello" message containing "world".
+
+Requirements
+************
+A board and SoC that provide access to a UART and a driver that implements the
+UART async API.
+
+Wiring
+******
+The UART pins should be wired to a board which will run the MCTP endpoint
+sample such that this board's UART tx pin connects to the endpoint board's rx
+pin, and this board's UART rx pin connects to the endpoint board's tx pin. The
+boards' grounds should also be wired together.
+
+Optionally a logic analyzer can be wired up and listening to the UART to inspect
+the data flowing.
+
+Building and Running
+********************
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/modules/pmci/mctp/host
+   :host-os: unix
+   :board: nrf52840_nrf52840dk
+   :goals: run
+   :compact:
+
+References
+**********
+
+`MCTP Base Specification 2019 <https://www.dmtf.org/sites/default/files/standards/documents/DSP0236_1.3.1.pdf>`_
diff --git a/samples/modules/pmci/mctp/host/boards/nrf52840dk_nrf52840.overlay b/samples/modules/pmci/mctp/host/boards/nrf52840dk_nrf52840.overlay
new file mode 100644
index 00000000000..48c7f840dca
--- /dev/null
+++ b/samples/modules/pmci/mctp/host/boards/nrf52840dk_nrf52840.overlay
@@ -0,0 +1,3 @@
+&arduino_serial{
+	status = "okay";
+};
diff --git a/samples/modules/pmci/mctp/host/prj.conf b/samples/modules/pmci/mctp/host/prj.conf
new file mode 100644
index 00000000000..341787ecbd3
--- /dev/null
+++ b/samples/modules/pmci/mctp/host/prj.conf
@@ -0,0 +1,8 @@
+# nothing here
+CONFIG_SERIAL=y
+CONFIG_UART_ASYNC_API=y
+CONFIG_MCTP=y
+CONFIG_MCTP_UART=y
+CONFIG_MCTP_LOG_LEVEL_DBG=y
+CONFIG_LOG=y
+CONFIG_LOG_BUFFER_SIZE=4096
diff --git a/samples/modules/pmci/mctp/host/src/main.c b/samples/modules/pmci/mctp/host/src/main.c
new file mode 100644
index 00000000000..8a2fd4e9e64
--- /dev/null
+++ b/samples/modules/pmci/mctp/host/src/main.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2024 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <assert.h>
+#include <unistd.h>
+#include <zephyr/types.h>
+#include <zephyr/kernel.h>
+#include <libmctp.h>
+#include <zephyr/pmci/mctp/mctp_uart.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(mctp_host);
+
+#define LOCAL_HELLO_EID 20
+
+#define REMOTE_HELLO_EID 10
+
+K_SEM_DEFINE(mctp_rx, 0, 1);
+
+static void rx_message(uint8_t eid, bool tag_owner, uint8_t msg_tag, void *data, void *msg,
+		       size_t len)
+{
+	LOG_INF("received message %s for endpoint %d, msg_tag %d, len %zu", (char *)msg, eid,
+		msg_tag, len);
+	k_sem_give(&mctp_rx);
+}
+
+MCTP_UART_DT_DEFINE(mctp_host, DEVICE_DT_GET(DT_NODELABEL(arduino_serial)));
+
+int main(void)
+{
+	int rc;
+	struct mctp *mctp_ctx;
+
+	LOG_INF("MCTP Host EID:%d on %s\n", LOCAL_HELLO_EID, CONFIG_BOARD_TARGET);
+
+	mctp_set_alloc_ops(malloc, free, realloc);
+	mctp_ctx = mctp_init();
+	__ASSERT_NO_MSG(mctp_ctx != NULL);
+	mctp_register_bus(mctp_ctx, &mctp_host.binding, LOCAL_HELLO_EID);
+	mctp_set_rx_all(mctp_ctx, rx_message, NULL);
+	mctp_uart_start_rx(&mctp_host);
+
+	/* MCTP poll loop, send "hello" and get "world" back */
+	while (true) {
+		rc = mctp_message_tx(mctp_ctx, REMOTE_HELLO_EID, false, 0, "hello",
+				     sizeof("hello"));
+		if (rc != 0) {
+			LOG_WRN("Failed to send message, errno %d\n", rc);
+			k_msleep(1000);
+		} else {
+			k_sem_take(&mctp_rx, K_MSEC(10));
+		}
+		rc = 0;
+	}
+
+	return 0;
+}
diff --git a/samples/modules/pmci/mctp/mctp.rst b/samples/modules/pmci/mctp/mctp.rst
new file mode 100644
index 00000000000..6bfebf7c474
--- /dev/null
+++ b/samples/modules/pmci/mctp/mctp.rst
@@ -0,0 +1,5 @@
+.. zephyr:code-sample-category:: mctp
+   :name: MCTP
+   :show-listing:
+
+   These samples demonstrate how to build communicating firmwares using MCTP in Zephyr.
diff --git a/samples/modules/tflite-micro/magic_wand/README.rst b/samples/modules/tflite-micro/magic_wand/README.rst
index e1ca13faf58..a3507f3c615 100644
--- a/samples/modules/tflite-micro/magic_wand/README.rst
+++ b/samples/modules/tflite-micro/magic_wand/README.rst
@@ -32,7 +32,7 @@ Add the tflite-micro module to your West manifest and pull it:
     west config manifest.project-filter -- +tflite-micro
     west update
 
-The application can be built for the :ref:`litex-vexriscv` for
+The application can be built for the :zephyr:board:`litex_vexriscv` for
 emulation in Renode as follows:
 
 .. zephyr-app-commands::
diff --git a/samples/net/cloud/aws_iot_mqtt/CMakeLists.txt b/samples/net/cloud/aws_iot_mqtt/CMakeLists.txt
index 7ee0400ba7c..c3e6c69dda7 100644
--- a/samples/net/cloud/aws_iot_mqtt/CMakeLists.txt
+++ b/samples/net/cloud/aws_iot_mqtt/CMakeLists.txt
@@ -21,3 +21,5 @@ else()
 endif()
 
 target_sources(app PRIVATE "src/main.c" ${creds})
+
+include(${ZEPHYR_BASE}/samples/net/common/common.cmake)
diff --git a/samples/net/cloud/aws_iot_mqtt/Kconfig b/samples/net/cloud/aws_iot_mqtt/Kconfig
index a80d28db5c6..da81b7b8595 100644
--- a/samples/net/cloud/aws_iot_mqtt/Kconfig
+++ b/samples/net/cloud/aws_iot_mqtt/Kconfig
@@ -81,4 +81,5 @@ config AWS_EXPONENTIAL_BACKOFF
 
 endmenu
 
+source "samples/net/common/Kconfig"
 source "Kconfig.zephyr"
diff --git a/samples/net/cloud/aws_iot_mqtt/boards/mg100.conf b/samples/net/cloud/aws_iot_mqtt/boards/mg100.conf
new file mode 100644
index 00000000000..4278846625f
--- /dev/null
+++ b/samples/net/cloud/aws_iot_mqtt/boards/mg100.conf
@@ -0,0 +1,12 @@
+# The HL7800 driver gets its IP settings from the cell network
+CONFIG_NET_CONFIG_SETTINGS=n
+CONFIG_NET_DHCPV4=n
+CONFIG_DNS_SERVER_IP_ADDRESSES=n
+# NB-IoT has large latency, so increase timeouts. It is ok to use this for Cat-M1 as well.
+CONFIG_NET_SOCKETS_DNS_TIMEOUT=12000
+CONFIG_NET_SOCKETS_CONNECT_TIMEOUT=15000
+# Wait for the network to be ready
+CONFIG_NET_CONNECTION_MANAGER=y
+CONFIG_NET_SAMPLE_COMMON_WAIT_DNS_SERVER_ADDITION=y
+# Don't require device to have time/date
+CONFIG_MBEDTLS_HAVE_TIME_DATE=n
diff --git a/samples/net/cloud/aws_iot_mqtt/boards/pinnacle_100_dvk.conf b/samples/net/cloud/aws_iot_mqtt/boards/pinnacle_100_dvk.conf
new file mode 100644
index 00000000000..4278846625f
--- /dev/null
+++ b/samples/net/cloud/aws_iot_mqtt/boards/pinnacle_100_dvk.conf
@@ -0,0 +1,12 @@
+# The HL7800 driver gets its IP settings from the cell network
+CONFIG_NET_CONFIG_SETTINGS=n
+CONFIG_NET_DHCPV4=n
+CONFIG_DNS_SERVER_IP_ADDRESSES=n
+# NB-IoT has large latency, so increase timeouts. It is ok to use this for Cat-M1 as well.
+CONFIG_NET_SOCKETS_DNS_TIMEOUT=12000
+CONFIG_NET_SOCKETS_CONNECT_TIMEOUT=15000
+# Wait for the network to be ready
+CONFIG_NET_CONNECTION_MANAGER=y
+CONFIG_NET_SAMPLE_COMMON_WAIT_DNS_SERVER_ADDITION=y
+# Don't require device to have time/date
+CONFIG_MBEDTLS_HAVE_TIME_DATE=n
diff --git a/samples/net/cloud/aws_iot_mqtt/prj.conf b/samples/net/cloud/aws_iot_mqtt/prj.conf
index fa0a5202a5d..ef5f6574ef7 100644
--- a/samples/net/cloud/aws_iot_mqtt/prj.conf
+++ b/samples/net/cloud/aws_iot_mqtt/prj.conf
@@ -71,3 +71,9 @@ CONFIG_MBEDTLS_TLS_VERSION_1_2=y
 CONFIG_MBEDTLS_MEMORY_DEBUG=y
 CONFIG_MBEDTLS_HAVE_TIME_DATE=y
 CONFIG_MBEDTLS_SSL_ALPN=y
+
+# Debugging options
+# CONFIG_MBEDTLS_DEBUG=y
+# CONFIG_MBEDTLS_LOG_LEVEL_DBG=y
+# CONFIG_LOG_PROCESS_THREAD_SLEEP_MS=1
+# CONFIG_LOG_BUFFER_SIZE=50000
diff --git a/samples/net/cloud/aws_iot_mqtt/src/main.c b/samples/net/cloud/aws_iot_mqtt/src/main.c
index 4bb226ea97a..61548c338f4 100644
--- a/samples/net/cloud/aws_iot_mqtt/src/main.c
+++ b/samples/net/cloud/aws_iot_mqtt/src/main.c
@@ -17,6 +17,7 @@
 #include <zephyr/data/json.h>
 #include <zephyr/random/random.h>
 #include <zephyr/logging/log.h>
+#include "net_sample_common.h"
 
 
 #if defined(CONFIG_MBEDTLS_MEMORY_DEBUG)
@@ -453,6 +454,8 @@ int main(void)
 {
 	setup_credentials();
 
+	wait_for_network();
+
 	for (;;) {
 		resolve_broker_addr(&aws_broker);
 
diff --git a/samples/net/cloud/mqtt_azure/prj.conf b/samples/net/cloud/mqtt_azure/prj.conf
index b857f7e4317..87fce73d774 100644
--- a/samples/net/cloud/mqtt_azure/prj.conf
+++ b/samples/net/cloud/mqtt_azure/prj.conf
@@ -35,6 +35,9 @@ CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=10240
 CONFIG_MBEDTLS_PEM_CERTIFICATE_FORMAT=y
 CONFIG_MBEDTLS_SHA1=y
 CONFIG_MBEDTLS_SHA384=y
+CONFIG_MBEDTLS_RSA_C=y
+CONFIG_MBEDTLS_PKCS1_V15=y
+CONFIG_MBEDTLS_PKCS1_V21=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_RSA_ENABLED=y
 CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y
 CONFIG_MBEDTLS_ECDH_C=y
diff --git a/samples/net/common/Kconfig b/samples/net/common/Kconfig
new file mode 100644
index 00000000000..afaab763ac5
--- /dev/null
+++ b/samples/net/common/Kconfig
@@ -0,0 +1,52 @@
+#
+# Copyright (c) 2025 Ezurio
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config NET_SAMPLE_COMMON_WAIT_DNS_SERVER_ADDITION
+	bool "Wait DNS server addition before considering connection to be up"
+	depends on MODEM_HL7800 && !DNS_SERVER_IP_ADDRESSES
+	help
+	  Make sure we get DNS server addresses from the network
+	  before considering the connection to be up.
+
+config NET_SAMPLE_COMMON_VLAN_SETUP_1
+	string "VLAN setup for the 1st VLAN interface"
+	default ""
+	depends on NET_VLAN
+	help
+	  This can setup the first VLAN network interface.
+	  The format of the string looks like this:
+	    <VLAN-tag>;<ip-address/mask-len>,...
+	  Example:
+	    100;198.51.100.1/24,2001:db8:100::1/64
+	  The VLAN tag can have values between 0 and 4094.
+	  There can be multiple IP addresses specified, and the
+	  code tries to apply them all to this interface.
+
+config NET_SAMPLE_COMMON_VLAN_SETUP_2
+	string "VLAN setup for the 2nd VLAN interface"
+	default ""
+	depends on NET_VLAN
+	help
+	  This can setup the first VLAN network interface.
+	  The format of the string looks like this:
+	    <VLAN-tag>;<ip-address/mask-len>,...
+	  Example:
+	    200;203.0.113.1/24,2001:db8:200::1/64
+	  The VLAN tag can have values between 0 and 4094.
+	  There can be multiple IP addresses specified, and the
+	  code tries to apply them all to this interface.
+
+config NET_SAMPLE_COMMON_TUNNEL_PEER_ADDR
+	string "Remote IP address of the tunnel interface"
+	depends on NET_L2_IPIP
+	help
+	  Use overlay-tunnel.conf to setup the tunnel support.
+
+config NET_SAMPLE_COMMON_TUNNEL_MY_ADDR
+	string "My address for tunnel interface"
+	depends on NET_L2_IPIP
+	help
+	  The value depends on your network setup.
diff --git a/samples/net/common/README.rst b/samples/net/common/README.rst
new file mode 100644
index 00000000000..774e0990462
--- /dev/null
+++ b/samples/net/common/README.rst
@@ -0,0 +1,64 @@
+.. _networking_samples_common:
+
+Overview
+********
+
+Various network samples can utilize common code to enable generic
+features like VLAN support.
+
+The source code for the common sample can be found at:
+:zephyr_file:`samples/net/common`.
+
+VLAN
+****
+
+If you want to enable VLAN support to network sample application,
+then add :file:`overlay-vlan.conf` to your sample application compilation
+like in this example for echo-server sample application:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/net/sockets/echo_server
+   :host-os: unix
+   :board: native_sim
+   :conf: "prj.conf overlay-vlan.conf"
+   :goals: run
+   :compact:
+
+You host setup for the VLAN can be done like this:
+
+.. code-block:: console
+
+    $ cd tools/net-setup
+    $ ./net-setup.sh -c zeth-vlan.conf
+
+The example configuration will create this kind of configuration:
+
+* In host side:
+
+  * Normal ``zeth`` interface is created. It has ``192.0.2.2/24``
+    address. All the network traffic to Zephyr will go through this
+    interface.
+
+  * VLAN interface ``vlan.100`` is used for VLAN tag 100 network traffic.
+    It has ``198.51.100.2`` IPv4 and ``2001:db8:100::2`` IPv6 addresses.
+
+  * VLAN interface ``vlan.200`` is used for VLAN tag 200 network traffic.
+    It has ``203.0.113.2`` IPv4 and ``2001:db8:200::2`` IPv6 addresses.
+
+* The network interfaces and addresses in Zephyr side:
+
+  * The ``eth0`` is the main interface, it has ``192.0.2.1/24``
+    address and it has connection to the host.
+
+  * The ``VLAN-100`` is a virtual interface for VLAN tag 100 traffic.
+    It has ``198.51.100.1/24`` IPv4 and ``2001:db8:100::1/64`` addresses.
+
+  * The ``VLAN-200`` is a virtual interface for VLAN tag 200 traffic.
+    It has ``203.0.113.1/24`` IPv4 and ``2001:db8:200::1/64`` addresses.
+
+.. warning::
+
+   The IPv4 and IPv6 addresses used in the samples are not to be used
+   in any live network and are only meant for these network samples.
+   These IPv4 and IPv6 addresses are meant for documentation use only and
+   are not routable.
diff --git a/samples/net/common/common.cmake b/samples/net/common/common.cmake
index c0e0e511179..6c4de029eeb 100644
--- a/samples/net/common/common.cmake
+++ b/samples/net/common/common.cmake
@@ -4,3 +4,9 @@
 
 target_include_directories(app PRIVATE ${ZEPHYR_BASE}/samples/net/common/)
 target_sources(app PRIVATE $ENV{ZEPHYR_BASE}/samples/net/common/net_sample_common.c)
+
+target_sources_ifdef(CONFIG_NET_VLAN app PRIVATE
+  $ENV{ZEPHYR_BASE}/samples/net/common/vlan.c)
+
+target_sources_ifdef(CONFIG_NET_L2_IPIP app PRIVATE
+  $ENV{ZEPHYR_BASE}/samples/net/common/tunnel.c)
diff --git a/samples/net/common/net_sample_common.c b/samples/net/common/net_sample_common.c
index 1e744f178b5..e1b91c91122 100644
--- a/samples/net/common/net_sample_common.c
+++ b/samples/net/common/net_sample_common.c
@@ -8,9 +8,14 @@
 LOG_MODULE_REGISTER(net_samples_common, LOG_LEVEL_DBG);
 
 #include <zephyr/net/conn_mgr_connectivity.h>
+#include <zephyr/net/conn_mgr_monitor.h>
 
 #if defined(CONFIG_NET_CONNECTION_MANAGER)
+#if defined(CONFIG_NET_SAMPLE_COMMON_WAIT_DNS_SERVER_ADDITION)
+#define L4_EVENT_MASK (NET_EVENT_DNS_SERVER_ADD | NET_EVENT_L4_DISCONNECTED)
+#else
 #define L4_EVENT_MASK (NET_EVENT_L4_CONNECTED | NET_EVENT_L4_DISCONNECTED)
+#endif
 
 static struct net_mgmt_event_callback l4_cb;
 static K_SEM_DEFINE(network_connected, 0, 1);
@@ -19,7 +24,11 @@ static void l4_event_handler(struct net_mgmt_event_callback *cb, uint32_t event,
 			     struct net_if *iface)
 {
 	switch (event) {
+#if defined(CONFIG_NET_SAMPLE_COMMON_WAIT_DNS_SERVER_ADDITION)
+	case NET_EVENT_DNS_SERVER_ADD:
+#else
 	case NET_EVENT_L4_CONNECTED:
+#endif
 		LOG_INF("Network connectivity established and IP address assigned");
 		k_sem_give(&network_connected);
 		break;
@@ -34,6 +43,7 @@ void wait_for_network(void)
 {
 	net_mgmt_init_event_callback(&l4_cb, l4_event_handler, L4_EVENT_MASK);
 	net_mgmt_add_event_callback(&l4_cb);
+	conn_mgr_mon_resend_status();
 
 	LOG_INF("Waiting for network...");
 
diff --git a/samples/net/common/net_sample_common.h b/samples/net/common/net_sample_common.h
index f44e852a0da..bef73f6b07d 100644
--- a/samples/net/common/net_sample_common.h
+++ b/samples/net/common/net_sample_common.h
@@ -4,8 +4,35 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <zephyr/net/net_if.h>
+
 #if defined(CONFIG_NET_CONNECTION_MANAGER)
 void wait_for_network(void);
 #else
 static inline void wait_for_network(void) { }
 #endif /* CONFIG_NET_CONNECTION_MANAGER */
+
+#if defined(CONFIG_NET_VLAN)
+int init_vlan(void);
+#else
+static inline int init_vlan(void)
+{
+	return 0;
+}
+#endif /* CONFIG_NET_VLAN */
+
+#if defined(CONFIG_NET_L2_IPIP)
+int init_tunnel(void);
+bool is_tunnel(struct net_if *iface);
+#else
+static inline int init_tunnel(void)
+{
+	return 0;
+}
+
+static inline bool is_tunnel(struct net_if *iface)
+{
+	ARG_UNUSED(iface);
+	return false;
+}
+#endif /* CONFIG_NET_L2_IPIP */
diff --git a/samples/net/sockets/echo_server/src/tunnel.c b/samples/net/common/tunnel.c
similarity index 82%
rename from samples/net/sockets/echo_server/src/tunnel.c
rename to samples/net/common/tunnel.c
index da04f6f864a..613527aa103 100644
--- a/samples/net/sockets/echo_server/src/tunnel.c
+++ b/samples/net/common/tunnel.c
@@ -5,7 +5,7 @@
  */
 
 #include <zephyr/logging/log.h>
-LOG_MODULE_DECLARE(net_echo_server_sample, LOG_LEVEL_DBG);
+LOG_MODULE_DECLARE(net_samples_common, LOG_LEVEL_DBG);
 
 #include <zephyr/kernel.h>
 
@@ -13,6 +13,18 @@ LOG_MODULE_DECLARE(net_echo_server_sample, LOG_LEVEL_DBG);
 #include <zephyr/net/virtual_mgmt.h>
 #include <zephyr/net/conn_mgr_monitor.h>
 
+#if defined(CONFIG_NET_SAMPLE_COMMON_TUNNEL_PEER_ADDR)
+#define NET_SAMPLE_COMMON_TUNNEL_PEER_ADDR CONFIG_NET_SAMPLE_COMMON_TUNNEL_PEER_ADDR
+#else
+#define NET_SAMPLE_COMMON_TUNNEL_PEER_ADDR ""
+#endif
+
+#if defined(CONFIG_NET_SAMPLE_COMMON_TUNNEL_MY_ADDR)
+#define NET_SAMPLE_COMMON_TUNNEL_MY_ADDR CONFIG_NET_SAMPLE_COMMON_TUNNEL_MY_ADDR
+#else
+#define NET_SAMPLE_COMMON_TUNNEL_MY_ADDR ""
+#endif
+
 /* User data for the interface callback */
 struct ud {
 	struct net_if *tunnel;
@@ -88,16 +100,16 @@ int init_tunnel(void)
 
 	memset(&ud, 0, sizeof(ud));
 
-	if (CONFIG_NET_SAMPLE_TUNNEL_PEER_ADDR[0] == '\0') {
+	if (NET_SAMPLE_COMMON_TUNNEL_PEER_ADDR[0] == '\0') {
 		LOG_INF("Tunnel peer address not set.");
 		return 0;
 	}
 
-	if (!net_ipaddr_parse(CONFIG_NET_SAMPLE_TUNNEL_PEER_ADDR,
-			      strlen(CONFIG_NET_SAMPLE_TUNNEL_PEER_ADDR),
+	if (!net_ipaddr_parse(NET_SAMPLE_COMMON_TUNNEL_PEER_ADDR,
+			      strlen(NET_SAMPLE_COMMON_TUNNEL_PEER_ADDR),
 			      &peer)) {
 		LOG_ERR("Tunnel peer address \"%s\" invalid.",
-			CONFIG_NET_SAMPLE_TUNNEL_PEER_ADDR);
+			NET_SAMPLE_COMMON_TUNNEL_PEER_ADDR);
 		return -EINVAL;
 	}
 
@@ -130,7 +142,7 @@ int init_tunnel(void)
 
 	if (ud.peer == NULL) {
 		LOG_ERR("Peer address %s unreachable",
-			CONFIG_NET_SAMPLE_TUNNEL_PEER_ADDR);
+			NET_SAMPLE_COMMON_TUNNEL_PEER_ADDR);
 		return -ENETUNREACH;
 	}
 
@@ -146,7 +158,7 @@ int init_tunnel(void)
 	if (ret < 0 && ret != -ENOTSUP) {
 		LOG_ERR("Cannot set peer address %s to "
 			"interface %d (%d)",
-			CONFIG_NET_SAMPLE_TUNNEL_PEER_ADDR,
+			NET_SAMPLE_COMMON_TUNNEL_PEER_ADDR,
 			net_if_get_by_iface(ud.tunnel),
 			ret);
 	}
@@ -161,10 +173,10 @@ int init_tunnel(void)
 	}
 
 	ret = setup_iface(ud.tunnel,
-			  CONFIG_NET_SAMPLE_TUNNEL_MY_ADDR);
+			  NET_SAMPLE_COMMON_TUNNEL_MY_ADDR);
 	if (ret < 0) {
 		LOG_ERR("Cannot set IP address %s to tunnel interface",
-			CONFIG_NET_SAMPLE_TUNNEL_MY_ADDR);
+			NET_SAMPLE_COMMON_TUNNEL_MY_ADDR);
 		return -EINVAL;
 	}
 
diff --git a/samples/net/common/vlan.c b/samples/net/common/vlan.c
new file mode 100644
index 00000000000..0c04ff15b2e
--- /dev/null
+++ b/samples/net/common/vlan.c
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2018 Intel Corporation.
+ * Copyright (c) 2025 Nordic Semiconductor
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(net_samples_common, LOG_LEVEL_DBG);
+
+#include <stdlib.h>
+#include <zephyr/kernel.h>
+#include <zephyr/posix/arpa/inet.h>
+#include <zephyr/net/ethernet.h>
+
+/* User data for the interface callback */
+struct ud {
+	struct net_if *first;
+	struct net_if *second;
+	struct net_if *eth;
+};
+
+static void iface_cb(struct net_if *iface, void *user_data)
+{
+	struct ud *ud = user_data;
+
+	if (net_if_l2(iface) == &NET_L2_GET_NAME(ETHERNET) && ud->eth == NULL) {
+		ud->eth = iface;
+		return;
+	}
+
+	if (net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL)) {
+		return;
+	}
+
+	if (!ud->first) {
+		ud->first = iface;
+		return;
+	}
+
+	if (!ud->second) {
+		ud->second = iface;
+		return;
+	}
+}
+
+static int setup_iface(struct net_if *eth_iface,
+		       struct net_if *vlan_iface,
+		       const char *option)
+{
+	struct sockaddr_storage addr = { 0 };
+	struct sockaddr *paddr = (struct sockaddr *)&addr;
+	const char *addr_str, *next;
+	struct net_if_addr *ifaddr;
+	uint8_t mask_len = 0;
+	unsigned long value;
+	uint16_t vlan_tag;
+	char *endptr;
+	bool status;
+	int ret;
+
+	if (option[0] == '\0') {
+		return 0;
+	}
+
+	next = strstr(option, ";");
+	if (next == NULL) {
+		LOG_ERR("VLAN tag not found, invalid option \"%s\"", option);
+		return -EINVAL;
+	}
+
+	value = strtoul(option, &endptr, 10);
+	if (*endptr != '\0' && endptr != next) {
+		LOG_ERR("Invalid VLAN tag \"%s\"", option);
+		return -EINVAL;
+	}
+
+	vlan_tag = (uint16_t)value;
+	addr_str = ++next;
+
+	do {
+		char my_addr[INET6_ADDRSTRLEN] = { 'N', 'o', ' ', 'I', 'P', '\0'};
+
+		next = net_ipaddr_parse_mask(addr_str, strlen(addr_str),
+					     paddr, &mask_len);
+		if (next == NULL) {
+			LOG_ERR("Cannot parse IP address \"%s\"", addr_str);
+			return -EINVAL;
+		}
+
+		inet_ntop(paddr->sa_family, net_sin(paddr)->sin_addr.s4_addr,
+			  my_addr, sizeof(my_addr));
+
+		if (paddr->sa_family == AF_INET) {
+			struct sockaddr_in *addr4 = (struct sockaddr_in *)paddr;
+			struct sockaddr_in mask;
+
+			ifaddr = net_if_ipv4_addr_add(vlan_iface, &addr4->sin_addr,
+						      NET_ADDR_MANUAL, 0);
+
+			ret = net_mask_len_to_netmask(AF_INET, mask_len,
+						      (struct sockaddr *)&mask);
+			if (ret < 0) {
+				LOG_ERR("Invalid network mask length (%d)", ret);
+				return ret;
+			}
+
+			status = net_if_ipv4_set_netmask_by_addr(vlan_iface,
+								 &addr4->sin_addr,
+								 &mask.sin_addr);
+
+		} else if (paddr->sa_family == AF_INET6) {
+			struct sockaddr_in6 *addr6 = (struct sockaddr_in6 *)paddr;
+			struct in6_addr netaddr6;
+
+			ifaddr = net_if_ipv6_addr_add(vlan_iface, &addr6->sin6_addr,
+						      NET_ADDR_MANUAL, 0);
+
+			net_ipv6_addr_prefix_mask((uint8_t *)&addr6->sin6_addr,
+						  (uint8_t *)&netaddr6,
+						  mask_len);
+
+			if (!net_if_ipv6_prefix_add(vlan_iface, &netaddr6, mask_len,
+						    (uint32_t)0xffffffff)) {
+				LOG_ERR("Cannot add %s to interface %d", my_addr,
+					net_if_get_by_iface(vlan_iface));
+				return -EINVAL;
+			}
+
+		} else {
+			LOG_ERR("Cannot parse IP address \"%s\"", my_addr);
+			return -EAFNOSUPPORT;
+		}
+
+		if (ifaddr == NULL) {
+			LOG_ERR("Cannot add IP address \"%s\" to interface %d",
+				my_addr, net_if_get_by_iface(vlan_iface));
+			return -ENOENT;
+		}
+
+		addr_str = next;
+	} while (addr_str != NULL && *addr_str != '\0');
+
+	ret = net_eth_vlan_enable(eth_iface, vlan_tag);
+	if (ret < 0) {
+		LOG_ERR("Cannot enable VLAN for tag %d (%d)", vlan_tag, ret);
+	}
+
+	LOG_DBG("Interface %d VLAN tag %d setup done.",
+		net_if_get_by_iface(vlan_iface), vlan_tag);
+
+	/* Take the interface up if the setup was ok */
+	net_if_up(vlan_iface);
+
+	return 0;
+}
+
+int init_vlan(void)
+{
+	struct ud user_data;
+	int ret;
+
+	if (CONFIG_NET_VLAN_COUNT == 0) {
+		LOG_DBG("No VLAN interfaces defined.");
+		return 0;
+	}
+
+	memset(&user_data, 0, sizeof(user_data));
+
+	net_if_foreach(iface_cb, &user_data);
+
+	/* This sample has two VLANs. For the second one we need to manually
+	 * create IP address for this test. But first the VLAN needs to be
+	 * added to the interface so that IPv6 DAD can work properly.
+	 */
+	ret = setup_iface(user_data.eth, user_data.first,
+			  CONFIG_NET_SAMPLE_COMMON_VLAN_SETUP_1);
+	if (ret < 0) {
+		return ret;
+	}
+
+	ret = setup_iface(user_data.eth, user_data.second,
+			  CONFIG_NET_SAMPLE_COMMON_VLAN_SETUP_2);
+	if (ret < 0) {
+		return ret;
+	}
+
+	return 0;
+}
diff --git a/samples/net/dhcpv4_client/sample.yaml b/samples/net/dhcpv4_client/sample.yaml
index 44e1f91dc48..5656717934e 100644
--- a/samples/net/dhcpv4_client/sample.yaml
+++ b/samples/net/dhcpv4_client/sample.yaml
@@ -4,9 +4,6 @@ tests:
   sample.net.dhcpv4_client:
     harness: net
     depends_on: netif
-    platform_exclude:
-      - native_posix/native/64
-      - native_posix
     tags:
       - net
       - http
diff --git a/samples/net/dns_resolve/sample.yaml b/samples/net/dns_resolve/sample.yaml
index 0d346fec821..f62c25fccc8 100644
--- a/samples/net/dns_resolve/sample.yaml
+++ b/samples/net/dns_resolve/sample.yaml
@@ -4,9 +4,6 @@ common:
   tags:
     - net
     - dns
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 sample:
   description: DNS resolver, mDNS and LLMNR responder
   name: DNS resolver and responder sample application
diff --git a/samples/net/dsa/CMakeLists.txt b/samples/net/dsa/CMakeLists.txt
index 6f80b96f5e1..f22d38467c7 100644
--- a/samples/net/dsa/CMakeLists.txt
+++ b/samples/net/dsa/CMakeLists.txt
@@ -5,4 +5,5 @@ cmake_minimum_required(VERSION 3.20.0)
 find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
 project(dsa)
 
-target_sources(app PRIVATE src/main.c src/dsa_lldp.c)
+target_sources(app PRIVATE src/main.c)
+target_sources_ifdef(CONFIG_NET_SAMPLE_DSA_LLDP app PRIVATE src/dsa_lldp.c)
diff --git a/samples/net/dsa/Kconfig b/samples/net/dsa/Kconfig
new file mode 100644
index 00000000000..41811f5cad2
--- /dev/null
+++ b/samples/net/dsa/Kconfig
@@ -0,0 +1,25 @@
+# Private config options for DSA
+
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+mainmenu "DSA sample application"
+
+if NET_DSA
+
+config NET_SAMPLE_DSA_MAX_USER_PORTS
+	int "DSA user ports maximum number"
+	range 2 10
+	default 3
+	help
+	  DSA user ports maximum number.
+
+config NET_SAMPLE_DSA_LLDP
+	bool "DSA LLDP example"
+	default y
+	help
+	  Enable DSA LLDP example.
+
+endif
+
+source "Kconfig.zephyr"
diff --git a/samples/net/dsa/boards/ip_k66f.conf b/samples/net/dsa/boards/ip_k66f.conf
new file mode 100644
index 00000000000..a4407f29db3
--- /dev/null
+++ b/samples/net/dsa/boards/ip_k66f.conf
@@ -0,0 +1,16 @@
+CONFIG_DSA_SPI=y
+CONFIG_DSA_KSZ_TAIL_TAGGING=y
+
+CONFIG_SHELL_BACKEND_RTT=y
+CONFIG_SHELL_BACKEND_SERIAL=n
+CONFIG_LOG_BACKEND_RTT=n
+
+CONFIG_NET_DSA_DEPRECATED=y
+CONFIG_NET_CONFIG_SETTINGS=y
+CONFIG_NET_CONFIG_NEED_IPV6=y
+CONFIG_NET_CONFIG_NEED_IPV4=y
+CONFIG_NET_CONFIG_INIT_TIMEOUT=10
+
+CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.0.2.2"
+CONFIG_NET_CONFIG_MY_IPV4_GW="192.0.2.1"
+CONFIG_NET_CONFIG_MY_IPV6_ADDR="2001:db8::1"
diff --git a/samples/net/dsa/boards/mimxrt1180_evk_mimxrt1189_cm33.conf b/samples/net/dsa/boards/mimxrt1180_evk_mimxrt1189_cm33.conf
new file mode 100644
index 00000000000..971d4323fb9
--- /dev/null
+++ b/samples/net/dsa/boards/mimxrt1180_evk_mimxrt1189_cm33.conf
@@ -0,0 +1,5 @@
+CONFIG_NET_IF_MAX_IPV4_COUNT=7
+CONFIG_NET_IF_MAX_IPV6_COUNT=7
+
+CONFIG_NET_SAMPLE_DSA_LLDP=n
+CONFIG_NET_SAMPLE_DSA_MAX_USER_PORTS=5
diff --git a/samples/net/dsa/boards/mimxrt1180_evk_mimxrt1189_cm7.conf b/samples/net/dsa/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
new file mode 100644
index 00000000000..971d4323fb9
--- /dev/null
+++ b/samples/net/dsa/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
@@ -0,0 +1,5 @@
+CONFIG_NET_IF_MAX_IPV4_COUNT=7
+CONFIG_NET_IF_MAX_IPV6_COUNT=7
+
+CONFIG_NET_SAMPLE_DSA_LLDP=n
+CONFIG_NET_SAMPLE_DSA_MAX_USER_PORTS=5
diff --git a/samples/net/dsa/prj.conf b/samples/net/dsa/prj.conf
index 84a2317555f..02d94378f82 100644
--- a/samples/net/dsa/prj.conf
+++ b/samples/net/dsa/prj.conf
@@ -2,7 +2,7 @@ CONFIG_NETWORKING=y
 CONFIG_NET_LOG=y
 CONFIG_NET_IPV6=y
 CONFIG_NET_IPV4=y
-CONFIG_NET_DHCPV4=n
+CONFIG_NET_DHCPV4=y
 CONFIG_NET_UDP=y
 CONFIG_NET_TCP=y
 CONFIG_NET_STATISTICS=y
@@ -18,6 +18,9 @@ CONFIG_NET_IF_UNICAST_IPV6_ADDR_COUNT=5
 CONFIG_NET_IF_MCAST_IPV6_ADDR_COUNT=5
 CONFIG_NET_IF_UNICAST_IPV4_ADDR_COUNT=1
 CONFIG_NET_MAX_CONTEXTS=4
+CONFIG_ZVFS_OPEN_MAX=4
+CONFIG_ZVFS_POLL_MAX=4
+CONFIG_NET_MAX_CONN=4
 
 CONFIG_INIT_STACKS=y
 CONFIG_PRINTK=y
@@ -25,16 +28,10 @@ CONFIG_NET_SHELL=y
 
 # DSA support
 CONFIG_NET_DSA=y
-CONFIG_DSA_SPI=y
-CONFIG_DSA_KSZ_TAIL_TAGGING=y
 
 # Ethernet is needed for LLDP
 CONFIG_NET_L2_ETHERNET=y
 
-CONFIG_NET_CONFIG_NEED_IPV6=y
-CONFIG_NET_CONFIG_NEED_IPV4=y
-CONFIG_NET_CONFIG_SETTINGS=y
-
 # Logging
 CONFIG_LOG=y
 CONFIG_NET_DSA_LOG_LEVEL_INF=y
@@ -47,20 +44,15 @@ CONFIG_POSIX_API=y
 # How many traffic classes to enable
 CONFIG_NET_TC_TX_COUNT=6
 CONFIG_NET_TC_RX_COUNT=4
-CONFIG_NET_CONFIG_INIT_TIMEOUT=10
 
 CONFIG_REQUIRES_FULL_LIBC=y
 
 CONFIG_NET_IF_MAX_IPV4_COUNT=4
 CONFIG_NET_IF_MAX_IPV6_COUNT=4
-CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.168.0.2"
-CONFIG_NET_CONFIG_MY_IPV4_GW="192.168.0.1"
-CONFIG_NET_CONFIG_MY_IPV6_ADDR="2001:db8::1"
 
-# Add RTT SHELL support -> Instead of LOG_BACKEND_RTT
-# Shell can be used to test the DSA operation with e.g.
-# 'net ping -I3 192.168.0.1'
-CONFIG_SHELL=y
-CONFIG_SHELL_BACKEND_RTT=y
-CONFIG_SHELL_BACKEND_SERIAL=n
-CONFIG_LOG_BACKEND_RTT=n
+CONFIG_NET_MGMT=y
+CONFIG_NET_MGMT_EVENT=y
+CONFIG_NET_MGMT_EVENT_STACK_SIZE=2048
+
+CONFIG_NET_HOSTNAME_ENABLE=y
+CONFIG_NET_HOSTNAME="dsa"
diff --git a/samples/net/dsa/sample.yaml b/samples/net/dsa/sample.yaml
index fe4bd46d810..3016a7e5f6f 100644
--- a/samples/net/dsa/sample.yaml
+++ b/samples/net/dsa/sample.yaml
@@ -9,5 +9,8 @@ common:
 tests:
   sample.net.dsa:
     build_only: true
-    platform_allow: ip_k66f
+    platform_allow:
+      - ip_k66f
+      - mimxrt1180_evk/mimxrt1189/cm33
+      - mimxrt1180_evk/mimxrt1189/cm7
     depends_on: eth
diff --git a/samples/net/dsa/src/dsa.h b/samples/net/dsa/src/dsa.h
new file mode 100644
index 00000000000..cd8a28bca45
--- /dev/null
+++ b/samples/net/dsa/src/dsa.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2020 DENX Software Engineering GmbH
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __DSA_SAMPLE__
+#define __DSA_SAMPLE__
+
+#if defined(CONFIG_NET_DSA_DEPRECATED)
+#include <zephyr/net/dsa.h>
+#else
+#include <zephyr/net/dsa_core.h>
+#endif
+#include <zephyr/net/ethernet.h>
+
+extern struct ud user_data;
+
+/* User data for the interface callback */
+struct ud {
+	struct net_if *lan[CONFIG_NET_SAMPLE_DSA_MAX_USER_PORTS];
+	struct net_if *conduit;
+};
+
+#endif
diff --git a/samples/net/dsa/src/dsa_lldp.c b/samples/net/dsa/src/dsa_lldp.c
index 5f14af271a3..368579cddd9 100644
--- a/samples/net/dsa/src/dsa_lldp.c
+++ b/samples/net/dsa/src/dsa_lldp.c
@@ -18,24 +18,90 @@
 #include <errno.h>
 
 #include <zephyr/logging/log.h>
-#include "main.h"
 
 /* Loglevel of dsa_lldp function */
-LOG_MODULE_DECLARE(net_dsa_lldp_sample, CONFIG_NET_DSA_LOG_LEVEL);
+LOG_MODULE_DECLARE(net_dsa_sample, CONFIG_NET_DSA_LOG_LEVEL);
 
-#define LLDP_SYSTEM_NAME_SIZE 24
-#define LLDP_ETHER_TYPE 0x88CC
+#include "dsa_lldp.h"
+
+#define LLDP_SYSTEM_NAME_SIZE    24
+#define LLDP_ETHER_TYPE          0x88CC
 #define LLDP_INPUT_DATA_BUF_SIZE 512
-#define DSA_BUF_SIZ 128
-int dsa_lldp_send(struct net_if *iface, struct instance_data *pd,
-		  uint16_t lan, int src_port, int origin_port, int cmd,
-		  struct eth_addr *origin_addr)
+#define DSA_BUF_SIZ              128
+
+static const uint8_t eth_filter_l2_addr_base[][6] = {
+	/* MAC address of other device - for filtering testing */
+	{0x01, 0x80, 0xc2, 0x00, 0x00, 0x03}};
+
+enum net_verdict dsa_ll_addr_switch_cb(struct net_if *iface, struct net_pkt *pkt)
+{
+	struct net_eth_hdr *hdr = NET_ETH_HDR(pkt);
+	struct net_linkaddr lladst = { 0 };
+
+	net_pkt_cursor_init(pkt);
+
+	(void)net_linkaddr_set(&lladst, (const uint8_t *)hdr->dst.addr,
+			       sizeof(hdr->dst.addr));
+
+	/*
+	 * Pass packet to lan1..3 when matching one from
+	 * check_ll_ether_addr table
+	 */
+	if (check_ll_ether_addr(lladst.addr, &eth_filter_l2_addr_base[0][0])) {
+		return NET_CONTINUE;
+	}
+
+	return NET_OK;
+}
+
+int start_user_port_packet_socket(struct net_if *iface, struct instance_data *pd)
+{
+	struct sockaddr_ll dst;
+	int ret;
+
+	pd->sock = socket(AF_PACKET, SOCK_RAW, htons(ETH_P_ALL));
+	if (pd->sock < 0) {
+		LOG_ERR("Failed to create RAW socket : %d", errno);
+		return -errno;
+	}
+
+	dst.sll_ifindex = net_if_get_by_iface(iface);
+	dst.sll_family = AF_PACKET;
+
+	ret = bind(pd->sock, (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll));
+	if (ret < 0) {
+		LOG_ERR("Failed to bind packet socket : %d", errno);
+		return -errno;
+	}
+
+	return 0;
+}
+
+void dsa_lldp(struct ud *user_data)
+{
+	uint8_t tbl_buf[8];
+
+	/*
+	 * Set static table to forward LLDP protocol packets
+	 * to conduit port.
+	 */
+	dsa_switch_set_mac_table_entry(user_data->lan[0], &eth_filter_l2_addr_base[0][0], BIT(4), 0,
+				       0);
+	dsa_switch_get_mac_table_entry(user_data->lan[0], tbl_buf, 0);
+
+	LOG_INF("DSA static MAC address table entry [%d]:", 0);
+	LOG_INF("0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x", tbl_buf[7], tbl_buf[6], tbl_buf[5],
+		tbl_buf[4], tbl_buf[3], tbl_buf[2], tbl_buf[1], tbl_buf[0]);
+}
+
+static int dsa_lldp_send(struct net_if *iface, struct instance_data *pd, uint16_t lan, int src_port,
+			 int origin_port, int cmd, struct eth_addr *origin_addr)
 {
 	int ret, len;
 	char buffer[DSA_BUF_SIZ], sys_name[LLDP_SYSTEM_NAME_SIZE];
 	struct sockaddr_ll dst;
 	struct ethernet_context *ctx = net_if_l2_data(iface);
-	struct net_eth_hdr *eth_hdr = (struct net_eth_hdr *) buffer;
+	struct net_eth_hdr *eth_hdr = (struct net_eth_hdr *)buffer;
 	uint8_t *p = &buffer[sizeof(struct net_eth_hdr)];
 	uint8_t *pb = p;
 
@@ -92,7 +158,7 @@ int dsa_lldp_send(struct net_if *iface, struct instance_data *pd,
 	return 0;
 }
 
-void dsa_lldp_print_info(uint8_t *lldp_p, uint8_t lanid)
+static void dsa_lldp_print_info(uint8_t *lldp_p, uint8_t lanid)
 {
 	uint16_t tl, length;
 	uint8_t type, subtype;
@@ -104,7 +170,7 @@ void dsa_lldp_print_info(uint8_t *lldp_p, uint8_t lanid)
 		/* In-buffer data is stored as big endian */
 		t1 = *lldp_p++;
 		t2 = *lldp_p++;
-		tl = (uint16_t) t1 << 8 | t2;
+		tl = (uint16_t)t1 << 8 | t2;
 
 		/* Get type and length */
 		type = tl >> 9;
@@ -125,16 +191,16 @@ void dsa_lldp_print_info(uint8_t *lldp_p, uint8_t lanid)
 		case LLDP_TLV_END_LLDPDU:
 			return;
 		case LLDP_TLV_CHASSIS_ID:
-			LOG_INF("\tCHASSIS ID:\t%02x:%02x:%02x:%02x:%02x:%02x",
-				p[0], p[1], p[2], p[3], p[4], p[5]);
+			LOG_INF("\tCHASSIS ID:\t%02x:%02x:%02x:%02x:%02x:%02x", p[0], p[1], p[2],
+				p[3], p[4], p[5]);
 			break;
 		case LLDP_TLV_PORT_ID:
-			LOG_INF("\tPORT ID:\t%02x:%02x:%02x:%02x:%02x:%02x",
-				p[0], p[1], p[2], p[3], p[4], p[5]);
+			LOG_INF("\tPORT ID:\t%02x:%02x:%02x:%02x:%02x:%02x", p[0], p[1], p[2], p[3],
+				p[4], p[5]);
 			break;
 		case LLDP_TLV_TTL:
 			/* TTL field has 2 bytes in BE */
-			LOG_INF("\tTTL:\t\t%ds", (uint16_t) p[0] << 8 | p[1]);
+			LOG_INF("\tTTL:\t\t%ds", (uint16_t)p[0] << 8 | p[1]);
 			break;
 		case LLDP_TLV_SYSTEM_NAME:
 			memset(t, 0, length + 1);
@@ -146,21 +212,18 @@ void dsa_lldp_print_info(uint8_t *lldp_p, uint8_t lanid)
 	} while (1);
 }
 
-int dsa_lldp_recv(struct net_if *iface, struct instance_data *pd,
-		  uint16_t *lan, int *origin_port,
-		  struct eth_addr *origin_addr)
+static int dsa_lldp_recv(struct net_if *iface, struct instance_data *pd, uint16_t *lan,
+			 int *origin_port, struct eth_addr *origin_addr)
 {
 	struct ethernet_context *ctx = net_if_l2_data(iface);
-	struct net_eth_hdr *eth_hdr =
-		(struct net_eth_hdr *) pd->recv_buffer;
+	struct net_eth_hdr *eth_hdr = (struct net_eth_hdr *)pd->recv_buffer;
 	uint8_t *lldp_p = &pd->recv_buffer[sizeof(struct net_eth_hdr)];
 	int received;
 
 	*lan = ctx->dsa_port_idx;
 
 	/* Receive data */
-	received = recv(pd->sock, pd->recv_buffer,
-			sizeof(pd->recv_buffer), 0);
+	received = recv(pd->sock, pd->recv_buffer, sizeof(pd->recv_buffer), 0);
 	if (received < 0) {
 		LOG_ERR("RAW : recv error %d", errno);
 		return -1;
diff --git a/samples/net/dsa/src/dsa_lldp.h b/samples/net/dsa/src/dsa_lldp.h
new file mode 100644
index 00000000000..72c46f73cef
--- /dev/null
+++ b/samples/net/dsa/src/dsa_lldp.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2020 DENX Software Engineering GmbH
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __DSA_SAMPLE_LLDP__
+#define __DSA_SAMPLE_LLDP__
+
+#include "dsa.h"
+
+#define MCAST_DEST_MAC0 0x01
+#define MCAST_DEST_MAC1 0x80
+#define MCAST_DEST_MAC2 0xc2
+#define MCAST_DEST_MAC3 0x00
+#define MCAST_DEST_MAC4 0x00
+#define MCAST_DEST_MAC5 0x03
+
+#define RECV_BUFFER_SIZE 1280
+#define ETH_ALEN         6
+#define PACKET_LEN       128
+
+struct eth_addr {
+	uint8_t addr[ETH_ALEN]; /* origin hardware address */
+};
+
+struct instance_data {
+	char *if_name;
+	int sock;
+	char recv_buffer[RECV_BUFFER_SIZE];
+};
+
+static inline bool check_ll_ether_addr(const uint8_t *a, const uint8_t *b)
+{
+	return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2]) | (a[3] ^ b[3]) | (a[4] ^ b[4]) |
+		(a[5] ^ b[5])) == 0;
+}
+
+static inline void dsa_buf_write_be16(uint16_t tl, uint8_t **p)
+{
+	uint8_t *v = (uint8_t *)&tl;
+	**p = v[1];
+	(*p)++;
+	**p = v[0];
+	(*p)++;
+}
+
+int start_user_port_packet_socket(struct net_if *iface, struct instance_data *pd);
+
+enum net_verdict dsa_ll_addr_switch_cb(struct net_if *iface, struct net_pkt *pkt);
+
+void dsa_lldp(struct ud *user_data);
+
+#define CMD_DISCOVER           0
+#define CMD_ACK                1
+#define DSA_STACK_SIZE         4096
+#define DSA_PRIORITY           5
+#define DSA_THREAD_START_DELAY 4000
+
+#define DSA_THREAD(ID, FN_RECV, FN_SEND)                                                           \
+	static void dsa_thread_##ID(void *t1, void *t2, void *t3);                                 \
+	K_THREAD_DEFINE(dsa_tid_##ID, DSA_STACK_SIZE, dsa_thread_##ID, NULL, NULL, NULL,           \
+			DSA_PRIORITY, 0, DSA_THREAD_START_DELAY);                                  \
+                                                                                                   \
+	void dsa_thread_##ID(void *t1, void *t2, void *t3)                                         \
+	{                                                                                          \
+		int origin_port, ret;                                                              \
+		uint16_t seq;                                                                      \
+		struct eth_addr origin_addr;                                                       \
+		struct instance_data data;                                                         \
+		struct net_if *iface;                                                              \
+                                                                                                   \
+		iface = user_data.lan[ID - 1];                                                     \
+                                                                                                   \
+		data.if_name = "lan" #ID;                                                          \
+		ret = start_user_port_packet_socket(iface, &data);                                \
+		if (ret < 0) {                                                                     \
+			LOG_ERR("start_user_port_packet_socket failed %d", ret);                  \
+			return;                                                                    \
+		}                                                                                  \
+		dsa_register_recv_callback(iface, dsa_ll_addr_switch_cb);                          \
+                                                                                                   \
+		LOG_INF("DSA -> eth/lan" #ID " idx: %d sock: %d", net_if_get_by_iface(iface),      \
+			data.sock);                                                                \
+		do {                                                                               \
+			ret = FN_RECV(iface, &data, &seq, &origin_port, &origin_addr);             \
+			if (ret) {                                                                 \
+				break;                                                             \
+			}                                                                          \
+			ret = FN_SEND(iface, &data, seq, 0, origin_port, CMD_ACK, &origin_addr);   \
+			if (ret) {                                                                 \
+				break;                                                             \
+			}                                                                          \
+		} while (true);                                                                    \
+	}
+
+#endif /* __DSA_SAMPLE_LLDP__ */
diff --git a/samples/net/dsa/src/main.c b/samples/net/dsa/src/main.c
index a7c0e14dd2c..16d41af5999 100644
--- a/samples/net/dsa/src/main.c
+++ b/samples/net/dsa/src/main.c
@@ -5,12 +5,17 @@
  */
 
 #include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(net_dsa_lldp_sample, CONFIG_NET_DSA_LOG_LEVEL);
+LOG_MODULE_REGISTER(net_dsa_sample, CONFIG_NET_DSA_LOG_LEVEL);
 
-#include <zephyr/net/dsa.h>
-#include "main.h"
+#include "dsa.h"
 
-static void iface_cb(struct net_if *iface, void *user_data)
+#if defined(CONFIG_NET_SAMPLE_DSA_LLDP)
+#include "dsa_lldp.h"
+#endif
+
+struct ud user_data;
+
+static void dsa_iface_find_cb(struct net_if *iface, void *user_data)
 {
 
 	struct ud *ifaces = user_data;
@@ -19,107 +24,68 @@ static void iface_cb(struct net_if *iface, void *user_data)
 		return;
 	}
 
-	if (net_eth_get_hw_capabilities(iface) & ETHERNET_DSA_MASTER_PORT) {
-		if (ifaces->master == NULL) {
-			ifaces->master = iface;
+	if (net_eth_get_hw_capabilities(iface) & ETHERNET_DSA_CONDUIT_PORT) {
+		if (ifaces->conduit == NULL) {
+			ifaces->conduit = iface;
 
-			/* Get slave interfaces */
+			/* Get user interfaces */
 			for (int i = 0; i < ARRAY_SIZE(ifaces->lan); i++) {
-				struct net_if *slave = dsa_get_slave_port(iface, i);
-
-				if (slave == NULL) {
-					LOG_ERR("Slave interface %d not found.", i);
-					break;
+#if defined(CONFIG_NET_DSA_DEPRECATED)
+				struct net_if *user = dsa_get_slave_port(iface, i);
+#else
+				struct net_if *user = dsa_user_get_iface(iface, i);
+#endif
+
+				if (user == NULL) {
+					continue;
 				}
+				LOG_INF("[%d] User interface %d found.", i,
+					net_if_get_by_iface(user));
 
-				ifaces->lan[i] = slave;
+				ifaces->lan[i] = user;
 			}
 			return;
 		}
 	}
 }
 
-static const uint8_t eth_filter_l2_addr_base[][6] = {
-	/* MAC address of other device - for filtering testing */
-	{ 0x01, 0x80, 0xc2, 0x00, 0x00, 0x03 }
-};
-
-enum net_verdict dsa_ll_addr_switch_cb(struct net_if *iface,
-				       struct net_pkt *pkt)
-{
-	struct net_eth_hdr *hdr = NET_ETH_HDR(pkt);
-	struct net_linkaddr lladst;
-
-	net_pkt_cursor_init(pkt);
-	lladst.len = sizeof(hdr->dst.addr);
-	lladst.addr = &hdr->dst.addr[0];
-
-	/*
-	 * Pass packet to lan1..3 when matching one from
-	 * check_ll_ether_addr table
-	 */
-	if (check_ll_ether_addr(lladst.addr, &eth_filter_l2_addr_base[0][0])) {
-		return 1;
-	}
-
-	return 0;
-}
+#if defined(CONFIG_NET_MGMT_EVENT)
+#define EVENT_MASK (NET_EVENT_IF_UP)
+static struct net_mgmt_event_callback mgmt_cb;
 
-int start_slave_port_packet_socket(struct net_if *iface,
-				   struct instance_data *pd)
+static void event_handler(struct net_mgmt_event_callback *cb,
+			  uint32_t mgmt_event, struct net_if *iface)
 {
-	struct sockaddr_ll dst;
-	int ret;
+	ARG_UNUSED(iface);
+	ARG_UNUSED(cb);
 
-	pd->sock = socket(AF_PACKET, SOCK_RAW, htons(ETH_P_ALL));
-	if (pd->sock < 0) {
-		LOG_ERR("Failed to create RAW socket : %d", errno);
-		return -errno;
-	}
+	if (mgmt_event == NET_EVENT_IF_UP) {
+		LOG_INF("Port %d is up", net_if_get_by_iface(iface));
 
-	dst.sll_ifindex = net_if_get_by_iface(iface);
-	dst.sll_family = AF_PACKET;
+#if defined(CONFIG_NET_DHCPV4)
+		net_dhcpv4_start(iface);
+#endif
 
-	ret = bind(pd->sock, (const struct sockaddr *)&dst,
-		   sizeof(struct sockaddr_ll));
-	if (ret < 0) {
-		LOG_ERR("Failed to bind packet socket : %d", errno);
-		return -errno;
+		return;
 	}
-
-	return 0;
-}
-
-struct ud user_data_ifaces;
-static int init_dsa_ports(void)
-{
-	uint8_t tbl_buf[8];
-
-	/* Initialize interfaces - read them to user_data_ifaces */
-	(void)memset(&user_data_ifaces, 0, sizeof(user_data_ifaces));
-	net_if_foreach(iface_cb, &user_data_ifaces);
-
-	/*
-	 * Set static table to forward LLDP protocol packets
-	 * to master port.
-	 */
-	dsa_switch_set_mac_table_entry(user_data_ifaces.lan[0],
-					      &eth_filter_l2_addr_base[0][0],
-					      BIT(4), 0, 0);
-	dsa_switch_get_mac_table_entry(user_data_ifaces.lan[0], tbl_buf, 0);
-
-	LOG_INF("DSA static MAC address table entry [%d]:", 0);
-	LOG_INF("0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x",
-		tbl_buf[7], tbl_buf[6], tbl_buf[5], tbl_buf[4],
-		tbl_buf[3], tbl_buf[2], tbl_buf[1], tbl_buf[0]);
-
-	return 0;
 }
+#endif /* CONFIG_NET_MGMT_EVENT */
 
 int main(void)
 {
-	init_dsa_ports();
-
+	/* Initialize interfaces - read them to user_data */
+	(void)memset(&user_data, 0, sizeof(user_data));
+	net_if_foreach(dsa_iface_find_cb, &user_data);
+
+#if defined(CONFIG_NET_MGMT_EVENT)
+	net_mgmt_init_event_callback(&mgmt_cb,
+				     event_handler, EVENT_MASK);
+	net_mgmt_add_event_callback(&mgmt_cb);
+#endif /* CONFIG_NET_MGMT_EVENT */
+
+#if defined(CONFIG_NET_SAMPLE_DSA_LLDP)
+	dsa_lldp(&user_data);
+#endif
 	LOG_INF("DSA ports init - OK");
 	return 0;
 }
diff --git a/samples/net/dsa/src/main.h b/samples/net/dsa/src/main.h
deleted file mode 100644
index 5d8cd70e6ad..00000000000
--- a/samples/net/dsa/src/main.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright (c) 2020 DENX Software Engineering GmbH
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef __DSA_SAMPLE__
-#define __DSA_SAMPLE__
-
-#include <zephyr/kernel.h>
-#include <errno.h>
-
-#include <zephyr/net/net_core.h>
-#include <zephyr/net/net_l2.h>
-#include <zephyr/net/net_if.h>
-#include <zephyr/net/socket.h>
-#include <zephyr/net/ethernet.h>
-
-#define MCAST_DEST_MAC0 0x01
-#define MCAST_DEST_MAC1 0x80
-#define MCAST_DEST_MAC2 0xc2
-#define MCAST_DEST_MAC3 0x00
-#define MCAST_DEST_MAC4 0x00
-#define MCAST_DEST_MAC5 0x03
-
-#define RECV_BUFFER_SIZE 1280
-#define ETH_ALEN 6
-#define PACKET_LEN 128
-
-extern struct ud user_data_ifaces;
-
-struct eth_addr {
-	uint8_t addr[ETH_ALEN]; /* origin hardware address */
-};
-
-struct instance_data {
-	char *if_name;
-	int sock;
-	char recv_buffer[RECV_BUFFER_SIZE];
-};
-
-/* User data for the interface callback */
-struct ud {
-	struct net_if *lan[3];
-	struct net_if *master;
-};
-
-static inline bool check_ll_ether_addr(const uint8_t *a, const uint8_t *b)
-{
-	return ((a[0] ^ b[0]) | (a[1] ^ b[1]) | (a[2] ^ b[2]) |
-		(a[3] ^ b[3]) | (a[4] ^ b[4]) | (a[5] ^ b[5])) == 0;
-}
-
-static inline void dsa_buf_write_be16(uint16_t tl, uint8_t **p)
-{
-	uint8_t *v = (uint8_t *) &tl;
-	**p = v[1];
-	(*p)++;
-	**p = v[0];
-	(*p)++;
-}
-
-int start_slave_port_packet_socket(struct net_if *iface,
-				   struct instance_data *pd);
-
-enum net_verdict dsa_ll_addr_switch_cb(struct net_if *iface,
-				       struct net_pkt *pkt);
-
-#define CMD_DISCOVER 0
-#define CMD_ACK      1
-#define DSA_STACK_SIZE 4096
-#define DSA_PRIORITY      5
-#define DSA_THREAD_START_DELAY 4000
-
-#define DSA_THREAD(ID, FN_RECV, FN_SEND)                                       \
-	static void dsa_thread_##ID(void *t1, void *t2, void *t3);             \
-	K_THREAD_DEFINE(dsa_tid_##ID, DSA_STACK_SIZE,                          \
-		dsa_thread_##ID, NULL, NULL, NULL,                             \
-			DSA_PRIORITY, 0, DSA_THREAD_START_DELAY);              \
-									       \
-	void dsa_thread_##ID(void *t1, void *t2, void *t3)                     \
-	{                                                                      \
-		int origin_port, ret;                                          \
-		uint16_t seq;                                                  \
-		struct eth_addr origin_addr;                                   \
-		struct instance_data data;                                     \
-		struct net_if *iface;                                          \
-									       \
-		iface = user_data_ifaces.lan[ID-1];                            \
-									       \
-		data.if_name = "lan"#ID;                                       \
-		ret = start_slave_port_packet_socket(iface, &data);            \
-		if (ret < 0) {                                                 \
-			LOG_ERR("start_slave_port_packet_socket failed %d",    \
-				ret);                                          \
-			return;                                                \
-		}                                                              \
-		dsa_register_recv_callback(iface,                              \
-						dsa_ll_addr_switch_cb);        \
-									       \
-		LOG_INF("DSA -> eth/lan"#ID" idx: %d sock: %d",                \
-			net_if_get_by_iface(iface), data.sock);                \
-		do {                                                           \
-			ret = FN_RECV(iface, &data, &seq,                      \
-					&origin_port, &origin_addr);           \
-			if (ret) {                                             \
-				break;                                         \
-			}                                                      \
-			ret = FN_SEND(iface, &data,                            \
-					seq, 0, origin_port, CMD_ACK,          \
-					&origin_addr);                         \
-			if (ret) {                                             \
-				break;                                         \
-			}                                                      \
-		} while (true);                                                \
-	}
-
-#endif /* __DSA_SAMPLE__ */
diff --git a/samples/net/gptp/boards/mimxrt1050_evk.conf b/samples/net/gptp/boards/mimxrt1050_evk_mimxrt1052_hyperflash.conf
similarity index 100%
rename from samples/net/gptp/boards/mimxrt1050_evk.conf
rename to samples/net/gptp/boards/mimxrt1050_evk_mimxrt1052_hyperflash.conf
diff --git a/samples/net/gptp/boards/native_sim.conf b/samples/net/gptp/boards/native_sim.conf
index c514520186c..104c6cd4817 100644
--- a/samples/net/gptp/boards/native_sim.conf
+++ b/samples/net/gptp/boards/native_sim.conf
@@ -1,8 +1,8 @@
-# Settings for native_posix ethernet driver
-CONFIG_ETH_NATIVE_POSIX_PTP_CLOCK=y
+# Settings for native_sim / native_tap ethernet driver
+CONFIG_ETH_NATIVE_TAP_PTP_CLOCK=y
 
-#CONFIG_ETH_NATIVE_POSIX_RANDOM_MAC=y
-CONFIG_ETH_NATIVE_POSIX_MAC_ADDR="00:00:5e:00:53:2a"
+#CONFIG_ETH_NATIVE_TAP_RANDOM_MAC=y
+CONFIG_ETH_NATIVE_TAP_MAC_ADDR="00:00:5e:00:53:2a"
 
-# Assume 1 ms accuracy for native_posix simulated clock
+# Assume 1 ms accuracy for native_sim simulated clock
 CONFIG_NET_GPTP_CLOCK_ACCURACY_1MS=y
diff --git a/samples/net/lwm2m_client/Kconfig b/samples/net/lwm2m_client/Kconfig
index 1bc4b6c49b0..9625cb1b949 100644
--- a/samples/net/lwm2m_client/Kconfig
+++ b/samples/net/lwm2m_client/Kconfig
@@ -5,7 +5,7 @@
 
 mainmenu "LwM2M Client sample"
 
-config LWM2M_APP_ID
+config NET_SAMPLE_LWM2M_ID
 	string "LwM2M Client identity"
 	default ""
 	help
@@ -13,24 +13,28 @@ config LWM2M_APP_ID
 	  Leave empty for using CONFIG_BOARD
 
 if LWM2M_DTLS_SUPPORT
-config LWM2M_APP_PSK
+config NET_SAMPLE_LWM2M_PSK
 	string "PSK key"
 	default "000102030405060708090a0b0c0d0e0f"
 	help
 	  PSK key as a hex string.
 	  Maximum binary size is CONFIG_LWM2M_SECURITY_KEY_SIZE.
 
-config LWM2M_APP_TLS_TAG
+config NET_SAMPLE_LWM2M_TLS_TAG
 	int "TLS security tag"
 	default 1
 	help
 	  TLS security tag to use when connecting.
 endif
 
-config LWM2M_APP_SERVER
+config NET_SAMPLE_MIGHT_HAVE_INTERNET
+	bool
+	default y if (WIFI || MODEM)
+
+config NET_SAMPLE_LWM2M_SERVER
 	string "LwM2M server address"
-	default "coap://leshan.eclipseprojects.io:5683" if (WIFI && !LWM2M_DTLS_SUPPORT)
-	default "coaps://leshan.eclipseprojects.io:5684" if (WIFI && LWM2M_DTLS_SUPPORT)
+	default "coap://leshan.eclipseprojects.io:5683" if (NET_SAMPLE_MIGHT_HAVE_INTERNET && !LWM2M_DTLS_SUPPORT)
+	default "coaps://leshan.eclipseprojects.io:5684" if (NET_SAMPLE_MIGHT_HAVE_INTERNET && LWM2M_DTLS_SUPPORT)
 	default "coap://192.0.2.2:5683" if !LWM2M_DTLS_SUPPORT
 	default "coaps://192.0.2.2:5684" if (LWM2M_DTLS_SUPPORT && !LWM2M_RD_CLIENT_SUPPORT_BOOTSTRAP)
 	default "coaps://192.0.2.2:5784" if (LWM2M_DTLS_SUPPORT && LWM2M_RD_CLIENT_SUPPORT_BOOTSTRAP)
@@ -41,4 +45,11 @@ config LWM2M_APP_SERVER
 	  When port number is missing, CONFIG_LWM2M_PEER_PORT is used instead.
 	  IPv6 addresses must be enclosed in square brackets, for example "coap://[fd00::1]".
 
+config NET_SAMPLE_LWM2M_WAIT_DNS
+	bool "Wait DNS server addition before considering connection to be up"
+	depends on MODEM_HL7800 && !DNS_SERVER_IP_ADDRESSES
+	help
+	  Make sure we get DNS server addresses from the network
+	  before considering the connection to be up.
+
 source "Kconfig.zephyr"
diff --git a/samples/net/lwm2m_client/boards/native_posix.conf b/samples/net/lwm2m_client/boards/native_posix.conf
deleted file mode 100644
index 3e21f837f7c..00000000000
--- a/samples/net/lwm2m_client/boards/native_posix.conf
+++ /dev/null
@@ -1,5 +0,0 @@
-CONFIG_DNS_RESOLVER=y
-CONFIG_DNS_SERVER_IP_ADDRESSES=y
-CONFIG_DNS_SERVER1="192.0.2.2"
-CONFIG_LWM2M_DNS_SUPPORT=y
-CONFIG_NET_CONFIG_MY_IPV4_GW="192.0.2.2"
diff --git a/samples/net/lwm2m_client/boards/nrf9160dk_nrf52840.conf b/samples/net/lwm2m_client/boards/nrf9160dk_nrf52840.conf
new file mode 100644
index 00000000000..175066b865a
--- /dev/null
+++ b/samples/net/lwm2m_client/boards/nrf9160dk_nrf52840.conf
@@ -0,0 +1,34 @@
+CONFIG_UART_ASYNC_API=y
+CONFIG_UART_1_ASYNC=y
+CONFIG_UART_1_INTERRUPT_DRIVEN=n
+
+# Align with the Serial LTE Modem (SLM) application.
+CONFIG_MODEM_CELLULAR_UART_BUFFER_SIZES=6000
+
+# Networking
+CONFIG_NETWORKING=y
+CONFIG_NET_NATIVE=y
+CONFIG_NET_L2_PPP=y
+CONFIG_NET_IPV4=y
+CONFIG_NET_UDP=y
+CONFIG_NET_SOCKETS=y
+CONFIG_NET_CONTEXT_RCVTIMEO=y
+
+# DNS
+CONFIG_DNS_RESOLVER=y
+CONFIG_NET_L2_PPP_OPTION_DNS_USE=y
+CONFIG_DNS_SERVER_IP_ADDRESSES=y
+CONFIG_DNS_SERVER1="8.8.8.8"
+CONFIG_LWM2M_DNS_SUPPORT=y
+
+# Network management
+CONFIG_NET_MGMT=y
+CONFIG_NET_MGMT_EVENT=y
+CONFIG_NET_CONNECTION_MANAGER=y
+
+# Modem driver
+CONFIG_MODEM=y
+CONFIG_MODEM_CELLULAR=y
+
+# LwM2M client does not use power management
+CONFIG_PM_DEVICE=n
diff --git a/samples/net/lwm2m_client/boards/nrf9160dk_nrf52840.overlay b/samples/net/lwm2m_client/boards/nrf9160dk_nrf52840.overlay
new file mode 100644
index 00000000000..6fd249e01c4
--- /dev/null
+++ b/samples/net/lwm2m_client/boards/nrf9160dk_nrf52840.overlay
@@ -0,0 +1,18 @@
+#include <nrf52840/nrf9160dk_uart1_on_if0_3.dtsi>
+
+/ {
+	aliases {
+		modem = &modem;
+	};
+};
+
+&uart1 {
+	current-speed = <115200>;
+	hw-flow-control;
+
+	modem: modem {
+		compatible = "nordic,nrf91-slm";
+		status = "okay";
+		mdm-power-gpios = <&interface_to_nrf9160 4 GPIO_ACTIVE_LOW>;
+	};
+};
diff --git a/samples/net/lwm2m_client/overlay-data-cache.conf b/samples/net/lwm2m_client/overlay-data-cache.conf
new file mode 100644
index 00000000000..e7c410f51c0
--- /dev/null
+++ b/samples/net/lwm2m_client/overlay-data-cache.conf
@@ -0,0 +1,5 @@
+CONFIG_ZCBOR=y
+CONFIG_ZCBOR_CANONICAL=y
+CONFIG_LWM2M_RW_SENML_CBOR_SUPPORT=y
+CONFIG_POSIX_TIMERS=y
+CONFIG_LWM2M_RESOURCE_DATA_CACHE_SUPPORT=y
diff --git a/samples/net/lwm2m_client/overlay-dtls.conf b/samples/net/lwm2m_client/overlay-dtls.conf
index b19c2f8c952..c379c1f2607 100644
--- a/samples/net/lwm2m_client/overlay-dtls.conf
+++ b/samples/net/lwm2m_client/overlay-dtls.conf
@@ -32,3 +32,10 @@ CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=2048
 # then this has to be match length of CONFIG_BOARD. Default 16 is not enough
 # for some boards, so, increase it to 32.
 CONFIG_LWM2M_SECURITY_KEY_SIZE=32
+
+# Debug options
+# CONFIG_NET_SOCKETS_LOG_LEVEL_DBG=y
+# CONFIG_MBEDTLS_DEBUG=y
+# CONFIG_MBEDTLS_LOG_LEVEL_DBG=y
+# CONFIG_MBEDTLS_MEMORY_DEBUG=y
+# CONFIG_MBEDTLS_SHELL=y
diff --git a/samples/net/lwm2m_client/overlay-hl7800.conf b/samples/net/lwm2m_client/overlay-hl7800.conf
new file mode 100644
index 00000000000..645222db49f
--- /dev/null
+++ b/samples/net/lwm2m_client/overlay-hl7800.conf
@@ -0,0 +1,18 @@
+# Ensure your board has proper device tree configuration for the HL7800 modem
+CONFIG_MODEM=y
+CONFIG_MODEM_HL7800=y
+
+# The HL7800 driver gets its IP settings from the cell network
+CONFIG_NET_CONFIG_SETTINGS=n
+CONFIG_NET_CONNECTION_MANAGER=y
+CONFIG_NET_SAMPLE_LWM2M_WAIT_DNS=y
+CONFIG_DNS_RESOLVER=y
+
+# NB-IoT has large latency, so increase timeouts. It is ok to use this for Cat-M1 as well.
+CONFIG_NET_SOCKETS_DNS_TIMEOUT=12000
+CONFIG_NET_SOCKETS_CONNECT_TIMEOUT=13000
+CONFIG_NET_SOCKETS_DTLS_TIMEOUT=15000
+CONFIG_COAP_INIT_ACK_TIMEOUT_MS=15000
+
+# Debug options
+# CONFIG_MODEM_LOG_LEVEL_DBG=y
diff --git a/samples/net/lwm2m_client/overlay-ot.conf b/samples/net/lwm2m_client/overlay-ot.conf
index ee9750d2518..92b69006627 100644
--- a/samples/net/lwm2m_client/overlay-ot.conf
+++ b/samples/net/lwm2m_client/overlay-ot.conf
@@ -35,7 +35,7 @@ CONFIG_OPENTHREAD_NETWORKKEY="00:11:22:33:44:55:66:77:88:99:aa:bb:cc:dd:ee:ff"
 
 CONFIG_NET_CONFIG_MY_IPV6_ADDR="fdde:ad00:beef::1"
 CONFIG_NET_CONFIG_PEER_IPV6_ADDR="fdde:ad00:beef::2"
-CONFIG_LWM2M_APP_SERVER="coap://[fdde:ad00:beef::2]"
+CONFIG_NET_SAMPLE_LWM2M_SERVER="coap://[fdde:ad00:beef::2]"
 
 # mbedTLS tweaks
 CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=768
diff --git a/samples/net/lwm2m_client/sample.yaml b/samples/net/lwm2m_client/sample.yaml
index 5c8f0eb7f11..a3f21d89a01 100644
--- a/samples/net/lwm2m_client/sample.yaml
+++ b/samples/net/lwm2m_client/sample.yaml
@@ -64,6 +64,18 @@ tests:
     tags:
       - net
       - lwm2m
+  sample.net.lwm2m_client.data_cache:
+    harness: net
+    depends_on: netif
+    extra_args: EXTRA_CONF_FILE=overlay-data-cache.conf
+    platform_allow:
+      - qemu_x86
+      - native_sim
+    integration_platforms:
+      - qemu_x86
+    tags:
+      - net
+      - lwm2m
   sample.net.lwm2m_client.wnc_m14a2a:
     harness: net
     extra_args: SHIELD=wnc_m14a2a
diff --git a/samples/net/lwm2m_client/src/lwm2m-client.c b/samples/net/lwm2m_client/src/lwm2m-client.c
index d1334bcac99..9127769ff6b 100644
--- a/samples/net/lwm2m_client/src/lwm2m-client.c
+++ b/samples/net/lwm2m_client/src/lwm2m-client.c
@@ -30,10 +30,14 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
 #define CLIENT_SERIAL_NUMBER	"345000123"
 #define CLIENT_FIRMWARE_VER	"1.0"
 #define CLIENT_HW_VER		"1.0.1"
-#define TEMP_SENSOR_UNITS	"Celcius"
+#define TEMP_SENSOR_UNITS       "Celsius"
 
 /* Macros used to subscribe to specific Zephyr NET management events. */
+#if defined(CONFIG_NET_SAMPLE_LWM2M_WAIT_DNS)
+#define L4_EVENT_MASK (NET_EVENT_DNS_SERVER_ADD | NET_EVENT_L4_DISCONNECTED)
+#else
 #define L4_EVENT_MASK (NET_EVENT_L4_CONNECTED | NET_EVENT_L4_DISCONNECTED)
+#endif
 #define CONN_LAYER_EVENT_MASK (NET_EVENT_CONN_IF_FATAL_ERROR)
 
 static uint8_t bat_idx = LWM2M_DEVICE_PWR_SRC_TYPE_BAT_INT;
@@ -52,7 +56,7 @@ static double max_range = 100;
 static struct lwm2m_ctx client_ctx;
 
 static const char *endpoint =
-	(sizeof(CONFIG_LWM2M_APP_ID) > 1 ? CONFIG_LWM2M_APP_ID : CONFIG_BOARD);
+	(sizeof(CONFIG_NET_SAMPLE_LWM2M_ID) > 1 ? CONFIG_NET_SAMPLE_LWM2M_ID : CONFIG_BOARD);
 
 #if defined(CONFIG_LWM2M_DTLS_SUPPORT)
 BUILD_ASSERT(sizeof(endpoint) <= CONFIG_LWM2M_SECURITY_KEY_SIZE,
@@ -105,17 +109,17 @@ static int lwm2m_setup(void)
 	/* setup SECURITY object */
 
 	/* Server URL */
-	lwm2m_set_string(&LWM2M_OBJ(0, 0, 0), CONFIG_LWM2M_APP_SERVER);
+	lwm2m_set_string(&LWM2M_OBJ(0, 0, 0), CONFIG_NET_SAMPLE_LWM2M_SERVER);
 
 	/* Security Mode */
 	lwm2m_set_u8(&LWM2M_OBJ(0, 0, 2), IS_ENABLED(CONFIG_LWM2M_DTLS_SUPPORT) ? 0 : 3);
 #if defined(CONFIG_LWM2M_DTLS_SUPPORT)
 	lwm2m_set_string(&LWM2M_OBJ(0, 0, 3), endpoint);
-	if (sizeof(CONFIG_LWM2M_APP_PSK) > 1) {
-		char psk[1 + sizeof(CONFIG_LWM2M_APP_PSK) / 2];
+	if (sizeof(CONFIG_NET_SAMPLE_LWM2M_PSK) > 1) {
+		char psk[1 + sizeof(CONFIG_NET_SAMPLE_LWM2M_PSK) / 2];
 		/* Need to skip the nul terminator from string */
-		size_t len = hex2bin(CONFIG_LWM2M_APP_PSK, sizeof(CONFIG_LWM2M_APP_PSK) - 1, psk,
-				     sizeof(psk));
+		size_t len = hex2bin(CONFIG_NET_SAMPLE_LWM2M_PSK,
+				     sizeof(CONFIG_NET_SAMPLE_LWM2M_PSK) - 1, psk, sizeof(psk));
 		if (len <= 0) {
 			return -EINVAL;
 		}
@@ -334,7 +338,11 @@ static void l4_event_handler(struct net_mgmt_event_callback *cb,
 			     struct net_if *iface)
 {
 	switch (event) {
+#if defined(CONFIG_NET_SAMPLE_LWM2M_WAIT_DNS)
+	case NET_EVENT_DNS_SERVER_ADD:
+#else
 	case NET_EVENT_L4_CONNECTED:
+#endif
 		LOG_INF("IP Up");
 		on_net_event_l4_connected();
 		break;
@@ -368,6 +376,13 @@ int main(void)
 	k_sem_init(&quit_lock, 0, K_SEM_MAX_LIMIT);
 
 	if (IS_ENABLED(CONFIG_NET_CONNECTION_MANAGER)) {
+		struct net_if *iface = net_if_get_default();
+
+		if (!iface) {
+			LOG_ERR("No network interface found!");
+			return -ENODEV;
+		}
+
 		/* Setup handler for Zephyr NET Connection Manager events. */
 		net_mgmt_init_event_callback(&l4_cb, l4_event_handler, L4_EVENT_MASK);
 		net_mgmt_add_event_callback(&l4_cb);
@@ -377,15 +392,16 @@ int main(void)
 					     CONN_LAYER_EVENT_MASK);
 		net_mgmt_add_event_callback(&conn_cb);
 
-		ret = net_if_up(net_if_get_default());
+		ret = net_if_up(iface);
 
 		if (ret < 0 && ret != -EALREADY) {
 			LOG_ERR("net_if_up, error: %d", ret);
 			return ret;
 		}
 
-		(void)conn_mgr_if_connect(net_if_get_default());
+		(void)conn_mgr_if_connect(iface);
 
+		LOG_INF("Waiting for network connection...");
 		k_sem_take(&network_connected_sem, K_FOREVER);
 	}
 
@@ -397,7 +413,7 @@ int main(void)
 
 	(void)memset(&client_ctx, 0x0, sizeof(client_ctx));
 #if defined(CONFIG_LWM2M_DTLS_SUPPORT)
-	client_ctx.tls_tag = CONFIG_LWM2M_APP_TLS_TAG;
+	client_ctx.tls_tag = CONFIG_NET_SAMPLE_LWM2M_TLS_TAG;
 #endif
 	client_ctx.set_socket_state = socket_state;
 
diff --git a/samples/net/mdns_responder/CMakeLists.txt b/samples/net/mdns_responder/CMakeLists.txt
index 5c4e88178a9..a9003b52486 100644
--- a/samples/net/mdns_responder/CMakeLists.txt
+++ b/samples/net/mdns_responder/CMakeLists.txt
@@ -6,6 +6,5 @@ project(mdns_responder)
 
 target_sources(app PRIVATE src/main.c)
 target_sources(app PRIVATE src/service.c)
-target_sources_ifdef(CONFIG_NET_VLAN app PRIVATE src/vlan.c)
 
 include(${ZEPHYR_BASE}/samples/net/common/common.cmake)
diff --git a/samples/net/mdns_responder/Kconfig b/samples/net/mdns_responder/Kconfig
index 53cc3d2153d..ceeb6f1abba 100644
--- a/samples/net/mdns_responder/Kconfig
+++ b/samples/net/mdns_responder/Kconfig
@@ -5,52 +5,5 @@
 
 mainmenu "Networking mDNS responder sample application"
 
-config NET_SAMPLE_IFACE2_MY_IPV6_ADDR
-	string "My IPv6 address for second interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE2_MY_IPV4_ADDR
-	string "My IPv4 address for second interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE2_MY_IPV4_NETMASK
-	string "My IPv4 netmask for second interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE2_VLAN_TAG
-	int "VLAN tag for second interface"
-	default 100
-	range 0 4094
-	depends on NET_VLAN
-	help
-	  Set VLAN (virtual LAN) tag (id) that is used in the sample
-	  application.
-
-config NET_SAMPLE_IFACE3_MY_IPV6_ADDR
-	string "My IPv6 address for third interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE3_MY_IPV4_ADDR
-	string "My IPv4 address for third interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE3_MY_IPV4_NETMASK
-	string "My IPv4 netmask for third interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE3_VLAN_TAG
-	int "VLAN tag for third interface"
-	default 200
-	range 0 4094
-	depends on NET_VLAN
-	help
-	  Set VLAN (virtual LAN) tag (id) that is used in the sample
-	  application.
-
+source "samples/net/common/Kconfig"
 source "Kconfig.zephyr"
diff --git a/samples/net/mdns_responder/overlay-vlan.conf b/samples/net/mdns_responder/overlay-vlan.conf
index bdab8a44350..bcae2b5799d 100644
--- a/samples/net/mdns_responder/overlay-vlan.conf
+++ b/samples/net/mdns_responder/overlay-vlan.conf
@@ -11,21 +11,11 @@ CONFIG_NET_CONFIG_PEER_IPV6_ADDR="2001:db8::2"
 CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.0.2.1"
 CONFIG_NET_CONFIG_PEER_IPV4_ADDR="192.0.2.2"
 
-# Second ethernet interface will have these settings
-CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR="2001:db8:100::1"
-# TEST-NET-2 from RFC 5737
-CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR="198.51.100.1"
-CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_NETMASK="255.255.255.0"
-# VLAN tag for the second interface
-CONFIG_NET_SAMPLE_IFACE2_VLAN_TAG=100
+# Second VLAN interface will have these settings
+CONFIG_NET_SAMPLE_COMMON_VLAN_SETUP_1="100;2001:db8:100::1/64,198.51.100.1/24"
 
-# Settings for the third network interface
-CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR="2001:db8:200::1"
-# TEST-NET-3 from RFC 5737
-CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR="203.0.113.1"
-CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_NETMASK="255.255.255.0"
-# VLAN tag for the second interface
-CONFIG_NET_SAMPLE_IFACE3_VLAN_TAG=200
+# Third VLAN interface will have these settings
+CONFIG_NET_SAMPLE_COMMON_VLAN_SETUP_2="200;2001:db8:200::1/64,203.0.113.1/24"
 
 # Each interface needs at least 2 context. So if we have three
 # interfaces we need minimum 6 context but allocate more so that
diff --git a/samples/net/mdns_responder/prj.conf b/samples/net/mdns_responder/prj.conf
index 4bc9b6b13d2..97461678430 100644
--- a/samples/net/mdns_responder/prj.conf
+++ b/samples/net/mdns_responder/prj.conf
@@ -8,7 +8,7 @@ CONFIG_NET_IPV4=y
 CONFIG_NET_IF_MAX_IPV6_COUNT=3
 CONFIG_NET_IF_MAX_IPV4_COUNT=3
 
-CONFIG_ZVFS_POLL_MAX=7
+CONFIG_ZVFS_POLL_MAX=9
 
 CONFIG_NET_HOSTNAME_ENABLE=y
 CONFIG_NET_HOSTNAME_UNIQUE=n
diff --git a/samples/net/mdns_responder/sample.yaml b/samples/net/mdns_responder/sample.yaml
index 17b0b2f914e..48ab0bf7050 100644
--- a/samples/net/mdns_responder/sample.yaml
+++ b/samples/net/mdns_responder/sample.yaml
@@ -12,6 +12,14 @@ tests:
       - qemu_cortex_m3
     integration_platforms:
       - qemu_x86
+  sample.net.mdns_responder.probing:
+    extra_args:
+      - CONFIG_MDNS_RESPONDER_PROBE=y
+    platform_allow:
+      - qemu_x86
+      - qemu_cortex_m3
+    integration_platforms:
+      - qemu_x86
   sample.net.mdns_responder.wifi.nrf70dk:
     extra_args:
       - SNIPPET=wifi-ipv4
diff --git a/samples/net/mdns_responder/src/main.c b/samples/net/mdns_responder/src/main.c
index d6eea7c8337..b373ea78ca8 100644
--- a/samples/net/mdns_responder/src/main.c
+++ b/samples/net/mdns_responder/src/main.c
@@ -16,15 +16,6 @@ LOG_MODULE_REGISTER(net_mdns_responder_sample, LOG_LEVEL_DBG);
 
 extern void service(void);
 
-#if defined(CONFIG_NET_VLAN)
-int init_vlan(void);
-#else
-static inline int init_vlan(void)
-{
-	return 0;
-}
-#endif /* CONFIG_NET_VLAN */
-
 /*
  * Note that mDNS support requires no application interaction with zephyr,
  * beyond optional runtime hostname configuration calls and setting
@@ -36,10 +27,11 @@ static inline int init_vlan(void)
  */
 int main(void)
 {
+	init_vlan();
+
 	wait_for_network();
 
 	LOG_INF("Waiting mDNS queries...");
-	init_vlan();
 	service();
 	return 0;
 }
diff --git a/samples/net/mdns_responder/src/vlan.c b/samples/net/mdns_responder/src/vlan.c
deleted file mode 100644
index 832b172f367..00000000000
--- a/samples/net/mdns_responder/src/vlan.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Copyright (c) 2018 Intel Corporation.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/logging/log.h>
-LOG_MODULE_DECLARE(net_mdns_responder_sample, LOG_LEVEL_DBG);
-
-#include <zephyr/kernel.h>
-
-#include <zephyr/net/ethernet.h>
-
-/* User data for the interface callback */
-struct ud {
-	struct net_if *first;
-	struct net_if *second;
-};
-
-static void iface_cb(struct net_if *iface, void *user_data_param)
-{
-	struct ud *user_data = user_data_param;
-
-	if (net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL)) {
-		return;
-	}
-
-	if (!user_data->first) {
-		user_data->first = iface;
-		return;
-	}
-
-	if (!user_data->second) {
-		user_data->second = iface;
-		return;
-	}
-}
-
-static int setup_iface(struct net_if *eth_iface,
-		       struct net_if *iface,
-		       const char *ipv6_addr,
-		       const char *ipv4_addr,
-		       const char *netmask,
-		       uint16_t vlan_tag)
-{
-	struct net_if_addr *ifaddr;
-	struct in_addr addr4;
-	struct in6_addr addr6;
-	int ret;
-
-	ret = net_eth_vlan_enable(eth_iface, vlan_tag);
-	if (ret < 0) {
-		LOG_ERR("Cannot enable VLAN for tag %d (%d)", vlan_tag, ret);
-	}
-
-	if (IS_ENABLED(CONFIG_NET_IPV6)) {
-		if (net_addr_pton(AF_INET6, ipv6_addr, &addr6)) {
-			LOG_ERR("Invalid address: %s", ipv6_addr);
-			return -EINVAL;
-		}
-
-		ifaddr = net_if_ipv6_addr_add(iface, &addr6,
-					      NET_ADDR_MANUAL, 0);
-		if (!ifaddr) {
-			LOG_ERR("Cannot add %s to interface %p",
-				ipv6_addr, iface);
-			return -EINVAL;
-		}
-	}
-
-	if (IS_ENABLED(CONFIG_NET_IPV4)) {
-		if (net_addr_pton(AF_INET, ipv4_addr, &addr4)) {
-			LOG_ERR("Invalid address: %s", ipv4_addr);
-			return -EINVAL;
-		}
-
-		ifaddr = net_if_ipv4_addr_add(iface, &addr4,
-					      NET_ADDR_MANUAL, 0);
-		if (!ifaddr) {
-			LOG_ERR("Cannot add %s to interface %p",
-				ipv4_addr, iface);
-			return -EINVAL;
-		}
-
-		if (netmask && netmask[0]) {
-			struct in_addr nm;
-
-			if (net_addr_pton(AF_INET, netmask, &nm)) {
-				LOG_ERR("Invalid netmask: %s", ipv4_addr);
-				return -EINVAL;
-			}
-
-			net_if_ipv4_set_netmask_by_addr(iface, &addr4, &nm);
-		}
-	}
-
-	LOG_DBG("Interface %p VLAN tag %d setup done.", iface, vlan_tag);
-
-	return 0;
-}
-
-int init_vlan(void)
-{
-	struct net_if *iface;
-	struct ud user_data;
-	int ret;
-
-	iface = net_if_get_first_by_type(&NET_L2_GET_NAME(ETHERNET));
-	if (!iface) {
-		LOG_ERR("No ethernet interfaces found.");
-		return -ENOENT;
-	}
-
-	memset(&user_data, 0, sizeof(user_data));
-
-	net_if_foreach(iface_cb, &user_data);
-
-	/* This sample has two VLANs. For the second one we need to manually
-	 * create IP address for this test. But first the VLAN needs to be
-	 * added to the interface so that IPv6 DAD can work properly.
-	 */
-	ret = setup_iface(iface, user_data.first,
-			  CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_NETMASK,
-			  CONFIG_NET_SAMPLE_IFACE2_VLAN_TAG);
-	if (ret < 0) {
-		return ret;
-	}
-
-	ret = setup_iface(iface, user_data.second,
-			  CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_NETMASK,
-			  CONFIG_NET_SAMPLE_IFACE3_VLAN_TAG);
-	if (ret < 0) {
-		return ret;
-	}
-
-	/* Bring up the VLAN interface automatically */
-	net_if_up(user_data.first);
-	net_if_up(user_data.second);
-
-	return 0;
-}
diff --git a/samples/net/mqtt_publisher/docker-test.sh b/samples/net/mqtt_publisher/docker-test.sh
index 4c26be07718..797e250747a 100644
--- a/samples/net/mqtt_publisher/docker-test.sh
+++ b/samples/net/mqtt_publisher/docker-test.sh
@@ -13,7 +13,7 @@ start_configuration || return $?
 start_docker \
     "/usr/local/sbin/mosquitto -v -c /usr/local/etc/mosquitto/mosquitto.conf" || return $?
 
-start_zephyr -DOVERLAY_CONFIG=overlay-sample.conf "$overlay"
+start_zephyr -DEXTRA_CONF_FILE=overlay-sample.conf "$overlay"
 
 wait_zephyr
 result=$?
@@ -30,7 +30,7 @@ echo "Starting MQTT TLS test"
 start_docker \
     "/usr/local/sbin/mosquitto -v -c /usr/local/etc/mosquitto/mosquitto-tls.conf" || return $?
 
-start_zephyr -DOVERLAY_CONFIG="overlay-tls.conf overlay-sample.conf" "$overlay"
+start_zephyr -DEXTRA_CONF_FILE="overlay-tls.conf overlay-sample.conf" "$overlay"
 
 wait_zephyr
 result=$?
@@ -49,7 +49,9 @@ echo "Starting MQTT TLS + proxy test"
 
 start_docker "/usr/sbin/danted" || return $?
 
-start_zephyr -DOVERLAY_CONFIG="overlay-tls.conf overlay-sample.conf overlay-socks5.conf" "$overlay" || return $?
+start_zephyr \
+    -DEXTRA_CONF_FILE="overlay-tls.conf overlay-sample.conf overlay-socks5.conf" "$overlay" || \
+    return $?
 
 wait_zephyr
 result=$?
diff --git a/samples/net/mqtt_sn_publisher/boards/native_posix.conf b/samples/net/mqtt_sn_publisher/boards/native_posix.conf
deleted file mode 100644
index 357bbc8f5df..00000000000
--- a/samples/net/mqtt_sn_publisher/boards/native_posix.conf
+++ /dev/null
@@ -1,6 +0,0 @@
-# Configuration options for MQTT-SN sample
-
-# Copyright (c) 2022 René Beckmann
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME=y
diff --git a/samples/net/openthread/coap/CMakeLists.txt b/samples/net/openthread/coap/CMakeLists.txt
new file mode 100644
index 00000000000..3d39d1e6d13
--- /dev/null
+++ b/samples/net/openthread/coap/CMakeLists.txt
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(ot_coap)
+
+target_include_directories(app PRIVATE src)
+
+target_sources(app PRIVATE
+    src/main.c
+    src/coap_utils.c
+    src/coap_shell.c
+)
+
+target_sources_ifdef(CONFIG_OT_COAP_SAMPLE_LED app PRIVATE src/led.c)
+target_sources_ifdef(CONFIG_OT_COAP_SAMPLE_SW app PRIVATE src/button.c)
+
+include(${ZEPHYR_BASE}/samples/net/common/common.cmake)
+
+set(gen_dir ${ZEPHYR_BINARY_DIR}/include/generated/)
diff --git a/samples/net/openthread/coap/Kconfig b/samples/net/openthread/coap/Kconfig
new file mode 100644
index 00000000000..b3ddcad321e
--- /dev/null
+++ b/samples/net/openthread/coap/Kconfig
@@ -0,0 +1,23 @@
+# Config options for OpenThread Border CoAP sample app
+
+# Copyright (c) 2024 Alexandre Bailon
+# SPDX-License-Identifier: Apache-2.0
+
+mainmenu "OpenThread CoAP Sample"
+
+menu "Application configuration"
+
+config OT_COAP_SAMPLE_SERVER
+	bool "Build the sample CoAP server application"
+
+config OT_COAP_SAMPLE_LED
+	bool "Enable LED support"
+	default y
+
+config OT_COAP_SAMPLE_SW
+	bool "Enable switch support"
+	default y
+
+endmenu
+
+source "Kconfig.zephyr"
diff --git a/samples/net/openthread/coap/README.rst b/samples/net/openthread/coap/README.rst
new file mode 100644
index 00000000000..7a9c6ad1511
--- /dev/null
+++ b/samples/net/openthread/coap/README.rst
@@ -0,0 +1,196 @@
+.. zephyr:code-sample:: ot-coap
+   :name: OpenThread CoAP client and server application
+   :relevant-api: openthread
+
+   Build a Full Thread Device (FTD) CoAP server and client.
+
+Overview
+********
+
+This sample demonstrates how to use OpenThread CoAP API.
+It can be built to work as a server or as a client.
+
+By running a client and server on two boards, a local Thread network can be created.
+To create the network, OpenThread uses the network key provided with Kconfig.
+Once the boards have been flashed, the network will be
+automatically created and configured.
+
+Once the network is operational, then the client could start interacting with
+the server.
+Every time the user presses the button, the LED on server should toggle.
+
+The source code for this sample application can be found at:
+:zephyr_file:`samples/net/openthread/coap`.
+
+.. note::
+   This sample uses the OpenThread CoAP API whereas Zephyr has its own CoAP API.
+   So, why are we using the OpenThread CoAP API here ?
+
+   * OpenThread uses it internaly to implement many of its services.
+   * OpenThread CoAP API has a more direct access to radio.
+
+   So by using OpenThread CoAP API instead of Zephyr one,
+   we could expect less overhead although this makes the application less portable.
+
+Building and Running
+********************
+
+Build the OpenThread FTD CoAP server sample application like this:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/net/openthread/coap
+   :board: <board to use>
+   :west-args: -T sample.net.openthread.ftd.coap.server
+   :goals: build
+   :compact:
+
+Build the OpenThread FTD CoAP client sample application like this:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/net/openthread/coap
+   :board: <board to use>
+   :west-args: -T sample.net.openthread.ftd.coap.client
+   :goals: build
+   :compact:
+
+Example building CoAP server for the cc1352p7 launchpad:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/net/openthread/coap
+   :host-os: unix
+   :board: cc1352p7_lp
+   :west-args: -T sample.net.openthread.ftd.coap.server
+   :goals: build flash
+   :compact:
+
+Example building CoAP client for the cc1352p7 launchpad:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/net/openthread/coap
+   :host-os: unix
+   :board: cc1352p7_lp
+   :west-args: -T sample.net.openthread.ftd.coap.client
+   :goals: build flash
+   :compact:
+
+Checking Thread network state
+*****************************
+
+Open a console on both server and client boards then check the sate:
+
+.. code-block:: console
+
+   server:~$ ot state
+   router
+   Done
+
+A valid state could be child, router or leader.
+
+Once Thread network is operational, you could start using client.
+
+Controlling server board's LED using a button on client board
+*************************************************************
+
+There is nothing to do once Thread network is operational.
+Just press the button sw0 on the client and you should see led0 toggling.
+
+The client uses a broadcast address to request CoAP server to toggle the LED.
+It does not know the address of the server so if there is a second server
+on the network, then the LED of the second board will toggle too.
+
+Controlling server board's LED from a computer
+**********************************************
+
+Although we use OpenThread CoAP API, we could interact with any CoAP client
+or server available on network. In this example, we are going to control the
+LED from a computer that is not in the Thread network.
+This requires an `OpenThread Border Router`_ with NAT64 support enabled on the same network.
+
+First, check that the server (or the client) is connected to the otbr and
+can use NAT64:
+
+.. code-block:: console
+
+   server:~$ ot netdata show
+   router
+   Done
+   Prefixes:
+   fd6f:cb3a:802:1::/64 paos low dc00
+   Routes:
+   fc00::/7 sa med dc00
+   fd6f:cb3a:802:2:0:0::/96 sn low dc00
+   Services:
+   44970 01 14000500000e10 s dc00 0
+   44970 5d fd78b9ce54779c6eb5484d062c3b5b22d120 s dc00 1
+   Contexts:
+   fd6f:cb3a:802:1::/64 1 c
+   Commissioning:
+   11426 - - -
+   Done
+
+Prefixes show the IPv6 prefies that could be used by device outside the
+Thread network to contact devices on Thread network.
+
+We should have an IPv6 address using the prefix:
+
+.. code-block:: console
+
+   server:~$ ot ipaddr
+   fd78:b9ce:5477:9c6e:0:ff:fe00:a800
+   fd6f:cb3a:802:1:f0ec:c1e2:c1bb:744
+   fd78:b9ce:5477:9c6e:75b8:386c:1f79:1013
+   fe80:0:0:0:50d1:bed5:6e6e:ad75
+   Done
+
+fd6f:cb3a:802:1:f0ec:c1e2:c1bb:744 is the IPv6 address that could be used
+to contact the CoAP server outside of the Thread network.
+
+We could also check that we could access internet from Thread network:
+
+.. code-block:: console
+
+   server:~$ ot ping 8.8.8.8
+   Pinging synthesized IPv6 address: fd6f:cb3a:802:2:0:0:808:808
+   16 bytes from fd6f:cb3a:802:2:0:0:808:808: icmp_seq=1 hlim=114 time=36ms
+   1 packets transmitted, 1 packets received. Packet loss = 0.0%. Round-trip min/avg/max = 36/36.0/36 ms.
+   Done
+
+If everything is working, then, we could start controlling the LED from a computer.
+To do that, let's use aiocoap-client, a tool written in python.
+First, install it:
+
+.. code-block:: shell
+
+   pip install aiocoap
+
+
+Then, send a request to the server to toggle the LED:
+
+.. code-block:: shell
+
+    aiocoap-client -m PUT --payload '{"led_id":0,"state":2}'  coap://[fd6f:cb3a:802:1:f0ec:c1e2:c1bb:744]/led
+
+The LED state should have changed.
+
+
+.. _OpenThread Border Router: https://openthread.io/codelabs/openthread-border-router-nat64
+
+Controlling server board's LED using shell command
+**************************************************
+
+The example also provides a shell command to control the LED on the server from the client.
+
+To toggle the LED:
+
+.. code-block::
+
+   $client:~$ ot_coap led set 0 toggle
+
+The LED state should have changed.
+
+Same as for the button, this uses the broadcast address by default.
+To control the LED of a specific server, we can use it IPv6 address:
+
+.. code-block::
+
+   $client:~$ ot_coap led set 0 toggle fd6f:cb3a:802:1:f0ec:c1e2:c1bb:744
diff --git a/samples/net/openthread/coap/prj.conf b/samples/net/openthread/coap/prj.conf
new file mode 100644
index 00000000000..959fb3c6268
--- /dev/null
+++ b/samples/net/openthread/coap/prj.conf
@@ -0,0 +1,28 @@
+CONFIG_NETWORKING=y
+CONFIG_NET_L2_OPENTHREAD=y
+CONFIG_OPENTHREAD_COAP=y
+CONFIG_OPENTHREAD_SLAAC=y
+CONFIG_JSON_LIBRARY=y
+
+# Logging
+CONFIG_LOG=y
+CONFIG_LOG_MAX_LEVEL=1
+CONFIG_LOG_MODE_MINIMAL=n
+CONFIG_BOOT_BANNER=y
+CONFIG_LOG_BACKEND_UART=y
+
+# Kernel options
+CONFIG_MAIN_STACK_SIZE=2560
+CONFIG_INIT_STACKS=y
+
+# Add features required for FTD CLI
+CONFIG_SHELL=y
+CONFIG_OPENTHREAD_SHELL=y
+CONFIG_OPENTHREAD_PING_SENDER=y
+
+# Network config
+CONFIG_OPENTHREAD_PANID=4660
+CONFIG_OPENTHREAD_XPANID="11:11:11:11:22:22:22:22"
+CONFIG_OPENTHREAD_NETWORKKEY="00:11:22:33:44:55:66:77:88:99:aa:bb:cc:dd:ee:ff"
+CONFIG_OPENTHREAD_CHANNEL=15
+CONFIG_OPENTHREAD_NETWORK_NAME="OpenThreadDemo"
diff --git a/samples/net/openthread/coap/sample.yaml b/samples/net/openthread/coap/sample.yaml
new file mode 100644
index 00000000000..7727aa287fd
--- /dev/null
+++ b/samples/net/openthread/coap/sample.yaml
@@ -0,0 +1,21 @@
+common:
+  harness: net
+  tags:
+    - net
+    - openthread
+  depends_on: openthread
+  min_flash: 140
+sample:
+  description: Runs the OpenThread stack as FTD with CoAP
+  name: OpenThread FTD CoAP
+tests:
+  sample.net.openthread.ftd.coap.client:
+    build_only: true
+    platform_allow:
+      - cc1352p7_lp
+  sample.net.openthread.ftd.coap.server:
+    build_only: true
+    platform_allow:
+      - cc1352p7_lp
+    extra_configs:
+      - CONFIG_OT_COAP_SAMPLE_SERVER=y
diff --git a/samples/net/openthread/coap/src/button.c b/samples/net/openthread/coap/src/button.c
new file mode 100644
index 00000000000..da054c3e71c
--- /dev/null
+++ b/samples/net/openthread/coap/src/button.c
@@ -0,0 +1,180 @@
+/*
+ * Copyright (c) 2024 Alexandre Bailon
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(coap);
+
+#include "coap_utils.h"
+#include "button.h"
+
+struct btn_rsc_data {
+	const struct gpio_dt_spec gpio;
+};
+
+struct btn_rsc_ctx {
+	struct btn_rsc_data *btn;
+	int count;
+};
+
+static const struct json_obj_descr json_btn_state_descr[] = {
+	JSON_OBJ_DESCR_PRIM(struct json_btn_state, btn_id, JSON_TOK_NUMBER),
+	JSON_OBJ_DESCR_PRIM(struct json_btn_state, state, JSON_TOK_NUMBER),
+};
+
+static const struct json_obj_descr json_btn_get_descr[] = {
+	JSON_OBJ_DESCR_PRIM(struct json_btn_get, device_id, JSON_TOK_STRING),
+	JSON_OBJ_DESCR_OBJ_ARRAY(struct json_btn_get, btns, JSON_MAX_BTN, count,
+				 json_btn_state_descr, ARRAY_SIZE(json_btn_state_descr)),
+};
+
+static K_SEM_DEFINE(btn_get_sem, 0, 1);
+
+#ifdef CONFIG_OT_COAP_SAMPLE_SERVER
+static int btn_handler_get(void *ctx, otMessage *msg, const otMessageInfo *msg_info)
+{
+	uint8_t buf[COAP_MAX_BUF_SIZE];
+	struct btn_rsc_ctx *btn_ctx = ctx;
+
+	struct json_btn_get btn_data = {
+		.device_id = coap_device_id(),
+	};
+
+	for (int i = 0; i < btn_ctx->count; i++) {
+		btn_data.btns[i].btn_id = i;
+		btn_data.btns[i].state = gpio_pin_get_dt(&btn_ctx->btn[i].gpio);
+	}
+	btn_data.count = btn_ctx->count;
+
+	json_obj_encode_buf(json_btn_get_descr, ARRAY_SIZE(json_btn_get_descr), &btn_data, buf,
+			    COAP_MAX_BUF_SIZE);
+
+	return coap_resp_send(msg, msg_info, buf, strlen(buf) + 1);
+}
+
+static void btn_handler(void *ctx, otMessage *msg, const otMessageInfo *msg_info)
+{
+	coap_req_handler(ctx, msg, msg_info, NULL, btn_handler_get);
+}
+
+#define DEFINE_BTN_CTX(node_id)                                                                    \
+	{                                                                                          \
+		.gpio = GPIO_DT_SPEC_GET(node_id, gpios),                                          \
+	},
+
+#define DEFINE_BTNS_CTX(inst, compat, ...) DT_FOREACH_CHILD(DT_INST(inst, compat), DEFINE_BTN_CTX)
+
+static struct btn_rsc_data btn_rsc_data[] = {
+	DT_COMPAT_FOREACH_STATUS_OKAY_VARGS(gpio_keys, DEFINE_BTNS_CTX)};
+
+static struct btn_rsc_ctx btn_rsc_ctx = {
+	.btn = btn_rsc_data,
+	.count = ARRAY_SIZE(btn_rsc_data),
+};
+
+static otCoapResource btn_rsc = {
+	.mUriPath = BTN_URI,
+	.mHandler = btn_handler,
+	.mContext = &btn_rsc_ctx,
+	.mNext = NULL,
+};
+
+static int button_init_rsc(otCoapResource *rsc)
+{
+	int ret = 0;
+
+	struct btn_rsc_ctx *btn_ctx = rsc->mContext;
+	const struct gpio_dt_spec *gpio;
+
+	LOG_INF("Initializing the buttons");
+	for (int i = 0; i < btn_ctx->count; i++) {
+		gpio = &btn_ctx->btn[i].gpio;
+		ret = button_init(gpio);
+		if (ret) {
+			break;
+		}
+	}
+
+	return ret;
+}
+
+void coap_btn_reg_rsc(void)
+{
+	otInstance *ot = openthread_get_default_instance();
+
+	button_init_rsc(&btn_rsc);
+	LOG_INF("Registering button rsc");
+	otCoapAddResource(ot, &btn_rsc);
+}
+#endif /* CONFIG_OT_COAP_SAMPLE_SERVER */
+
+int button_init(const struct gpio_dt_spec *gpio)
+{
+	int ret;
+
+	if (!gpio_is_ready_dt(gpio)) {
+		LOG_ERR("Error: button device %s is not ready\n", gpio->port->name);
+		return -ENODEV;
+	}
+
+	ret = gpio_pin_configure_dt(gpio, GPIO_INPUT);
+	if (ret != 0) {
+		LOG_ERR("Error %d: failed to configure %s pin %d\n", ret, gpio->port->name,
+			gpio->pin);
+		return ret;
+	}
+
+	ret = gpio_pin_interrupt_configure_dt(gpio, GPIO_INT_EDGE_TO_ACTIVE);
+	if (ret != 0) {
+		LOG_ERR("Error %d: failed to configure interrupt on %s pin %d\n", ret,
+			gpio->port->name, gpio->pin);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void coap_btn_get_state_cb(void *ctx, otMessage *msg, const otMessageInfo *msg_info,
+				  otError error)
+{
+	uint8_t buf[COAP_MAX_BUF_SIZE];
+	int len = COAP_MAX_BUF_SIZE;
+	struct json_btn_get *btn = (struct json_btn_get *)ctx;
+	int ret;
+
+	ret = coap_get_data(msg, buf, &len);
+	if (ret) {
+		btn->count = 0;
+		goto exit;
+	}
+
+	json_obj_parse(buf, len, json_btn_get_descr, ARRAY_SIZE(json_btn_get_descr), btn);
+exit:
+	k_sem_give(&btn_get_sem);
+}
+
+int coap_btn_get_state(const char *addr, int btn_id, int *state)
+{
+	struct json_btn_get btn;
+	int ret;
+
+	ret = coap_get_req_send(addr, BTN_URI, NULL, 0, coap_btn_get_state_cb, &btn);
+	if (ret) {
+		return ret;
+	}
+
+	ret = k_sem_take(&btn_get_sem, K_FOREVER);
+	if (ret) {
+		return ret;
+	}
+
+	if (btn_id >= btn.count) {
+		return -ENODEV;
+	}
+
+	*state = btn.btns[btn_id].state;
+	return ret;
+}
diff --git a/samples/net/openthread/coap/src/button.h b/samples/net/openthread/coap/src/button.h
new file mode 100644
index 00000000000..2f2a0a3e777
--- /dev/null
+++ b/samples/net/openthread/coap/src/button.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2024 Alexandre Bailon
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef COAP_BUTTON_H
+#define COAP_BUTTON_H
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/data/json.h>
+
+#define BTN_URI "sw"
+
+#define BTN_MSG_STATE_OFF 0
+#define BTN_MSG_STATE_ON  1
+
+#define JSON_MAX_BTN 4
+
+struct json_btn_state {
+	int btn_id;
+	int state;
+};
+
+struct json_btn_get {
+	const char *device_id;
+	struct json_btn_state btns[JSON_MAX_BTN];
+	int count;
+};
+
+int button_init(const struct gpio_dt_spec *gpio);
+int coap_btn_get_state(const char *addr, int led_id, int *state);
+
+#ifdef CONFIG_OT_COAP_SAMPLE_SERVER
+void coap_btn_reg_rsc(void);
+#endif
+
+#endif /* COAP_BUTTON_H */
diff --git a/samples/net/openthread/coap/src/coap_shell.c b/samples/net/openthread/coap/src/coap_shell.c
new file mode 100644
index 00000000000..22e330104fb
--- /dev/null
+++ b/samples/net/openthread/coap/src/coap_shell.c
@@ -0,0 +1,148 @@
+/*
+ * Copyright (c) 2024 Alexandre Bailon
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/shell/shell.h>
+
+#include "led.h"
+#include "button.h"
+
+static int coap_cmd_led_set(const struct shell *sh, size_t argc, char **argv)
+{
+	int led_id;
+	int led_state;
+	const char *addr;
+	int err = 0;
+
+	led_id = shell_strtol(argv[1], 10, &err);
+	if (err) {
+		shell_error(sh, "Failed to get a valid LED id: %s", argv[1]);
+		return err;
+	}
+
+	if (!strcmp(argv[2], "on")) {
+		led_state = LED_MSG_STATE_ON;
+	} else if (!strcmp(argv[2], "off")) {
+		led_state = LED_MSG_STATE_OFF;
+	} else if (!strcmp(argv[2], "toggle")) {
+		led_state = LED_MSG_STATE_TOGGLE;
+	} else {
+		shell_error(sh, "Failed to get a valid LED state");
+		return -EINVAL;
+	}
+
+	if (argc <= 3) {
+		addr = "ff03::1";
+	} else {
+		addr = argv[3];
+	}
+
+	return coap_led_set_state(addr, led_id, led_state);
+}
+
+static int coap_cmd_led_get(const struct shell *sh, size_t argc, char **argv)
+{
+	int led_id;
+	int led_state;
+	const char *addr;
+	int err = 0;
+
+	led_id = shell_strtol(argv[1], 10, &err);
+	if (err) {
+		shell_error(sh, "Failed to get a valid LED id: %s", argv[1]);
+		return err;
+	}
+
+	if (argc <= 3) {
+		addr = "ff03::1";
+	} else {
+		addr = argv[3];
+	}
+
+	err = coap_led_get_state(addr, led_id, &led_state);
+	if (err) {
+		return err;
+	}
+
+	if (led_state == LED_MSG_STATE_ON) {
+		shell_info(sh, "on");
+	} else {
+		shell_info(sh, "off");
+	}
+
+	return 0;
+}
+
+static int coap_cmd_btn_get(const struct shell *sh, size_t argc, char **argv)
+{
+	int btn_id;
+	int btn_state;
+	const char *addr;
+	int err = 0;
+
+	btn_id = shell_strtol(argv[1], 10, &err);
+	if (err) {
+		shell_error(sh, "Failed to get a valid button id: %s", argv[1]);
+		return err;
+	}
+
+	if (argc <= 3) {
+		addr = "ff03::1";
+	} else {
+		addr = argv[3];
+	}
+
+	err = coap_btn_get_state(addr, btn_id, &btn_state);
+	if (err) {
+		return err;
+	}
+
+	if (btn_state == BTN_MSG_STATE_ON) {
+		shell_info(sh, "on");
+	} else {
+		shell_info(sh, "off");
+	}
+
+	return 0;
+}
+
+static const char coap_cmd_led_set_help[] =
+	"Set a LED state using CoAP\n"
+	"led set <led_id> <led_state> [addr]\n"
+	"\tled_id: a number defining the LED to control from CoAP server\n"
+	"\tled_state: on, off or toggle\n"
+	"\taddr: the IPv6 address of CoAP server. If not defined, it will broadcast to all CoAP "
+	"servers\n";
+
+static const char coap_cmd_led_get_help[] =
+	"Get a LED state using CoAP\n"
+	"led get <led_id> [addr]\n"
+	"\tled_id: a number defining the LED to get from CoAP server\n"
+	"\taddr: the IPv6 address of CoAP server. If not defined, it "
+	"will broadcast to all CoAP servers\n";
+
+SHELL_STATIC_SUBCMD_SET_CREATE(
+	coap_led_subcmd, SHELL_CMD_ARG(set, NULL, coap_cmd_led_set_help, coap_cmd_led_set, 3, 1),
+	SHELL_CMD_ARG(get, NULL, coap_cmd_led_get_help, coap_cmd_led_get, 2, 1),
+	SHELL_SUBCMD_SET_END);
+
+static const char coap_cmd_btn_get_help[] =
+	"Get a button state using CoAP\n"
+	"btn get <btn_id> [addr]\n"
+	"\tbtn_id: a number defining the button to get from CoAP server\n"
+	"\taddr: the IPv6 address of CoAP server. If not defined, it "
+	"will broadcast to all CoAP servers\n";
+
+SHELL_STATIC_SUBCMD_SET_CREATE(coap_btn_subcmd,
+			       SHELL_CMD_ARG(get, NULL, coap_cmd_btn_get_help, coap_cmd_btn_get, 2,
+					     1),
+			       SHELL_SUBCMD_SET_END);
+
+SHELL_STATIC_SUBCMD_SET_CREATE(coap_subcmd,
+			       SHELL_CMD(led, &coap_led_subcmd, "Manage a LED using CoAP", NULL),
+			       SHELL_CMD(btn, &coap_btn_subcmd, "Manage a button using CoAP", NULL),
+			       SHELL_SUBCMD_SET_END);
+
+SHELL_CMD_REGISTER(ot_coap, &coap_subcmd, "CoAP sample client", NULL);
diff --git a/samples/net/openthread/coap/src/coap_utils.c b/samples/net/openthread/coap/src/coap_utils.c
new file mode 100644
index 00000000000..4f4e8af7c0a
--- /dev/null
+++ b/samples/net/openthread/coap/src/coap_utils.c
@@ -0,0 +1,284 @@
+/*
+ * Copyright (c) 2024 Alexandre Bailon
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(coap);
+
+#include "coap_utils.h"
+
+static uint8_t coap_buf[COAP_MAX_BUF_SIZE];
+static uint8_t coap_dev_id[COAP_DEVICE_ID_SIZE];
+
+#ifdef CONFIG_OT_COAP_SAMPLE_SERVER
+static void coap_default_handler(void *context, otMessage *message,
+				 const otMessageInfo *message_info)
+{
+	ARG_UNUSED(context);
+	ARG_UNUSED(message);
+	ARG_UNUSED(message_info);
+
+	LOG_INF("Received CoAP message that does not match any request "
+		"or resource");
+}
+#endif /* CONFIG_OT_COAP_SAMPLE_SERVER */
+
+static int coap_req_send(const char *addr, const char *uri, uint8_t *buf, int len,
+			 otCoapResponseHandler handler, void *ctx, otCoapCode code)
+{
+	otInstance *ot;
+	otMessage *msg;
+	otMessageInfo msg_info;
+	otError err;
+	int ret;
+
+	ot = openthread_get_default_instance();
+	if (!ot) {
+		LOG_ERR("Failed to get an OpenThread instance");
+		return -ENODEV;
+	}
+
+	memset(&msg_info, 0, sizeof(msg_info));
+	otIp6AddressFromString(addr, &msg_info.mPeerAddr);
+	msg_info.mPeerPort = OT_DEFAULT_COAP_PORT;
+
+	msg = otCoapNewMessage(ot, NULL);
+	if (!msg) {
+		LOG_ERR("Failed to allocate a new CoAP message");
+		return -ENOMEM;
+	}
+
+	otCoapMessageInit(msg, OT_COAP_TYPE_CONFIRMABLE, code);
+
+	err = otCoapMessageAppendUriPathOptions(msg, uri);
+	if (err != OT_ERROR_NONE) {
+		LOG_ERR("Failed to append uri-path: %s", otThreadErrorToString(err));
+		ret = -EBADMSG;
+		goto err;
+	}
+
+	err = otCoapMessageSetPayloadMarker(msg);
+	if (err != OT_ERROR_NONE) {
+		LOG_ERR("Failed to set payload marker: %s", otThreadErrorToString(err));
+		ret = -EBADMSG;
+		goto err;
+	}
+
+	err = otMessageAppend(msg, buf, len);
+	if (err != OT_ERROR_NONE) {
+		LOG_ERR("Failed to set append payload to response: %s", otThreadErrorToString(err));
+		ret = -EBADMSG;
+		goto err;
+	}
+
+	err = otCoapSendRequest(ot, msg, &msg_info, handler, ctx);
+	if (err != OT_ERROR_NONE) {
+		LOG_ERR("Failed to send the request: %s", otThreadErrorToString(err));
+		ret = -EIO; /* Find a better error code */
+		goto err;
+	}
+
+	return 0;
+
+err:
+	otMessageFree(msg);
+	return ret;
+}
+
+int coap_put_req_send(const char *addr, const char *uri, uint8_t *buf, int len,
+		      otCoapResponseHandler handler, void *ctx)
+{
+	return coap_req_send(addr, uri, buf, len, handler, ctx, OT_COAP_CODE_PUT);
+}
+
+int coap_get_req_send(const char *addr, const char *uri, uint8_t *buf, int len,
+		      otCoapResponseHandler handler, void *ctx)
+{
+	return coap_req_send(addr, uri, buf, len, handler, ctx, OT_COAP_CODE_GET);
+}
+
+int coap_resp_send(otMessage *req, const otMessageInfo *req_info, uint8_t *buf, int len)
+{
+	otInstance *ot;
+	otMessage *resp;
+	otCoapCode resp_code;
+	otCoapType resp_type;
+	otError err;
+	int ret;
+
+	ot = openthread_get_default_instance();
+	if (!ot) {
+		LOG_ERR("Failed to get an OpenThread instance");
+		return -ENODEV;
+	}
+
+	resp = otCoapNewMessage(ot, NULL);
+	if (!resp) {
+		LOG_ERR("Failed to allocate a new CoAP message");
+		return -ENOMEM;
+	}
+
+	switch (otCoapMessageGetType(req)) {
+	case OT_COAP_TYPE_CONFIRMABLE:
+		resp_type = OT_COAP_TYPE_ACKNOWLEDGMENT;
+		break;
+	case OT_COAP_TYPE_NON_CONFIRMABLE:
+		resp_type = OT_COAP_TYPE_NON_CONFIRMABLE;
+		break;
+	default:
+		LOG_ERR("Invalid message type");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	switch (otCoapMessageGetCode(req)) {
+	case OT_COAP_CODE_GET:
+		resp_code = OT_COAP_CODE_CONTENT;
+		break;
+	case OT_COAP_CODE_PUT:
+		resp_code = OT_COAP_CODE_CHANGED;
+		break;
+	default:
+		LOG_ERR("Invalid message code");
+		ret = -EINVAL;
+		goto err;
+	}
+
+	err = otCoapMessageInitResponse(resp, req, resp_type, resp_code);
+	if (err != OT_ERROR_NONE) {
+		LOG_ERR("Failed to initialize the response: %s", otThreadErrorToString(err));
+		ret = -EBADMSG;
+		goto err;
+	}
+
+	err = otCoapMessageSetPayloadMarker(resp);
+	if (err != OT_ERROR_NONE) {
+		LOG_ERR("Failed to set payload marker: %s", otThreadErrorToString(err));
+		ret = -EBADMSG;
+		goto err;
+	}
+
+	err = otMessageAppend(resp, buf, len);
+	if (err != OT_ERROR_NONE) {
+		LOG_ERR("Failed to set append payload to response: %s", otThreadErrorToString(err));
+		ret = -EBADMSG;
+		goto err;
+	}
+
+	err = otCoapSendResponse(ot, resp, req_info);
+	if (err != OT_ERROR_NONE) {
+		LOG_ERR("Failed to send the response: %s", otThreadErrorToString(err));
+		ret = -EIO;
+		goto err;
+	}
+
+	return 0;
+
+err:
+	otMessageFree(resp);
+	return ret;
+}
+
+int coap_req_handler(void *ctx, otMessage *msg, const otMessageInfo *msg_info,
+		     coap_req_handler_put put_fn, coap_req_handler_get get_fn)
+{
+	otCoapCode msg_code = otCoapMessageGetCode(msg);
+	otCoapType msg_type = otCoapMessageGetType(msg);
+	int ret;
+
+	if (msg_type != OT_COAP_TYPE_CONFIRMABLE && msg_type != OT_COAP_TYPE_NON_CONFIRMABLE) {
+		return -EINVAL;
+	}
+
+	if (msg_code == OT_COAP_CODE_PUT && put_fn) {
+		int len = otMessageGetLength(msg) - otMessageGetOffset(msg);
+
+		otMessageRead(msg, otMessageGetOffset(msg), coap_buf, len);
+		ret = put_fn(ctx, coap_buf, len);
+		if (ret) {
+			return ret;
+		}
+
+		if (msg_type == OT_COAP_TYPE_CONFIRMABLE) {
+			ret = get_fn(ctx, msg, msg_info);
+		}
+
+		return ret;
+	}
+
+	if (msg_code == OT_COAP_CODE_GET) {
+		return get_fn(ctx, msg, msg_info);
+	}
+
+	return -EINVAL;
+}
+
+const char *coap_device_id(void)
+{
+	otInstance *ot = openthread_get_default_instance();
+	otExtAddress eui64;
+	int i;
+
+	if (coap_dev_id[0] != '\0') {
+		return coap_dev_id;
+	}
+
+	otPlatRadioGetIeeeEui64(ot, eui64.m8);
+	for (i = 0; i < 8; i++) {
+		if (i * 2 >= COAP_DEVICE_ID_SIZE) {
+			i = COAP_DEVICE_ID_SIZE - 1;
+			break;
+		}
+		sprintf(coap_dev_id + i * 2, "%02x", eui64.m8[i]);
+	}
+	coap_dev_id[i * 2] = '\0';
+
+	return coap_dev_id;
+}
+
+int coap_get_data(otMessage *msg, void *buf, int *len)
+{
+	int coap_len = otMessageGetLength(msg) - otMessageGetOffset(msg);
+
+	if (coap_len > *len) {
+		return -ENOMEM;
+	}
+
+	*len = coap_len;
+	otMessageRead(msg, otMessageGetOffset(msg), buf, coap_len);
+
+	return 0;
+}
+
+int coap_init(void)
+{
+	otError err;
+	otInstance *ot;
+
+#ifdef CONFIG_OT_COAP_SAMPLE_SERVER
+	LOG_INF("Initializing OpenThread CoAP server");
+#else  /* CONFIG_OT_COAP_SAMPLE_SERVER */
+	LOG_INF("Initializing OpenThread CoAP client");
+#endif /* CONFIG_OT_COAP_SAMPLE_SERVER */
+	ot = openthread_get_default_instance();
+	if (!ot) {
+		LOG_ERR("Failed to get an OpenThread instance");
+		return -ENODEV;
+	}
+
+#ifdef CONFIG_OT_COAP_SAMPLE_SERVER
+	otCoapSetDefaultHandler(ot, coap_default_handler, NULL);
+#endif /* CONFIG_OT_COAP_SAMPLE_SERVER */
+
+	err = otCoapStart(ot, OT_DEFAULT_COAP_PORT);
+	if (err != OT_ERROR_NONE) {
+		LOG_ERR("Cannot start CoAP: %s", otThreadErrorToString(err));
+		return -EBADMSG;
+	}
+
+	return 0;
+}
diff --git a/samples/net/openthread/coap/src/coap_utils.h b/samples/net/openthread/coap/src/coap_utils.h
new file mode 100644
index 00000000000..6db5db6379d
--- /dev/null
+++ b/samples/net/openthread/coap/src/coap_utils.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2024 Alexandre Bailon
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef COAP_UTILS_H
+#define COAP_UTILS_H
+
+#include <zephyr/net/openthread.h>
+#include <openthread/coap.h>
+
+#define COAP_MAX_BUF_SIZE   128
+#define COAP_DEVICE_ID_SIZE 25
+
+typedef int (*coap_req_handler_put)(void *ctx, uint8_t *buf, int size);
+typedef int (*coap_req_handler_get)(void *ctx, otMessage *msg, const otMessageInfo *msg_info);
+
+int coap_init(void);
+int coap_req_handler(void *ctx, otMessage *msg, const otMessageInfo *msg_info,
+		     coap_req_handler_put put_fn, coap_req_handler_get get_fn);
+int coap_resp_send(otMessage *req, const otMessageInfo *req_info, uint8_t *buf, int len);
+int coap_put_req_send(const char *addr, const char *uri, uint8_t *buf, int len,
+		      otCoapResponseHandler handler, void *ctx);
+int coap_get_req_send(const char *addr, const char *uri, uint8_t *buf, int len,
+		      otCoapResponseHandler handler, void *ctx);
+const char *coap_device_id(void);
+int coap_get_data(otMessage *msg, void *buf, int *len);
+
+#endif /* COAP_UTILS_H */
diff --git a/samples/net/openthread/coap/src/led.c b/samples/net/openthread/coap/src/led.c
new file mode 100644
index 00000000000..739e0f2de47
--- /dev/null
+++ b/samples/net/openthread/coap/src/led.c
@@ -0,0 +1,218 @@
+/*
+ * Copyright (c) 2024 Alexandre Bailon
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(coap);
+
+#include "coap_utils.h"
+#include "led.h"
+
+#ifdef CONFIG_OT_COAP_SAMPLE_SERVER
+struct led_rsc_data {
+	const struct gpio_dt_spec gpio;
+	int state;
+};
+
+struct led_rsc_ctx {
+	struct led_rsc_data *led;
+	int count;
+};
+#endif
+
+static const struct json_obj_descr json_led_state_descr[] = {
+	JSON_OBJ_DESCR_PRIM(struct json_led_state, led_id, JSON_TOK_NUMBER),
+	JSON_OBJ_DESCR_PRIM(struct json_led_state, state, JSON_TOK_NUMBER),
+};
+
+static const struct json_obj_descr json_led_get_descr[] = {
+	JSON_OBJ_DESCR_PRIM(struct json_led_get, device_id, JSON_TOK_STRING),
+	JSON_OBJ_DESCR_OBJ_ARRAY(struct json_led_get, leds, JSON_MAX_LED, count,
+				 json_led_state_descr, ARRAY_SIZE(json_led_state_descr)),
+};
+
+K_SEM_DEFINE(led_get_sem, 0, 1);
+
+#ifdef CONFIG_OT_COAP_SAMPLE_SERVER
+static int led_init(otCoapResource *rsc)
+{
+	struct led_rsc_ctx *led_ctx = rsc->mContext;
+	int ret;
+
+	LOG_INF("Initializing the LED");
+	for (int i = 0; i < led_ctx->count; i++) {
+		struct led_rsc_data *led = &led_ctx->led[i];
+
+		if (!gpio_is_ready_dt(&led->gpio)) {
+			return -ENODEV;
+		}
+
+		ret = gpio_pin_configure_dt(&led->gpio, GPIO_OUTPUT);
+		if (ret) {
+			LOG_ERR("Failed to configure the GPIO");
+			return ret;
+		}
+	}
+
+	return 0;
+}
+
+static int led_handler_put(void *ctx, uint8_t *buf, int size)
+{
+	struct json_led_state led_data;
+	struct led_rsc_ctx *led_ctx = ctx;
+	struct led_rsc_data *led;
+	int ret = -EINVAL;
+
+	json_obj_parse(buf, size, json_led_state_descr, ARRAY_SIZE(json_led_state_descr),
+		       &led_data);
+
+	if (led_data.led_id >= led_ctx->count) {
+		LOG_ERR("Invalid led id: %x", led_data.led_id);
+		return -EINVAL;
+	}
+	led = &led_ctx->led[led_data.led_id];
+
+	switch (led_data.state) {
+	case LED_MSG_STATE_ON:
+		ret = gpio_pin_set_dt(&led->gpio, 1);
+		led->state = 1;
+		break;
+	case LED_MSG_STATE_OFF:
+		ret = gpio_pin_set_dt(&led->gpio, 0);
+		led->state = 0;
+		break;
+	case LED_MSG_STATE_TOGGLE:
+		led->state = 1 - led->state;
+		ret = gpio_pin_set_dt(&led->gpio, led->state);
+		break;
+	default:
+		LOG_ERR("Set an unsupported LED state: %x", led_data.state);
+	}
+
+	return ret;
+}
+
+static int led_handler_get(void *ctx, otMessage *msg, const otMessageInfo *msg_info)
+{
+	uint8_t buf[COAP_MAX_BUF_SIZE];
+	struct led_rsc_ctx *led_ctx = ctx;
+
+	struct json_led_get led_data = {
+		.device_id = coap_device_id(),
+	};
+
+	for (int i = 0; i < led_ctx->count; i++) {
+		led_data.leds[i].led_id = i;
+		led_data.leds[i].state = led_ctx->led[i].state;
+	}
+	led_data.count = led_ctx->count;
+
+	json_obj_encode_buf(json_led_get_descr, ARRAY_SIZE(json_led_get_descr), &led_data, buf,
+			    COAP_MAX_BUF_SIZE);
+
+	return coap_resp_send(msg, msg_info, buf, strlen(buf) + 1);
+}
+
+static void led_handler(void *ctx, otMessage *msg, const otMessageInfo *msg_info)
+{
+	coap_req_handler(ctx, msg, msg_info, led_handler_put, led_handler_get);
+}
+
+#define DEFINE_LED_CTX(node_id)                                                                    \
+	{                                                                                          \
+		.gpio = GPIO_DT_SPEC_GET(node_id, gpios),                                          \
+		.state = 0,                                                                        \
+	},
+
+#define DEFINE_LEDS_CTX(inst, compat, ...) DT_FOREACH_CHILD(DT_INST(inst, compat), DEFINE_LED_CTX)
+
+static struct led_rsc_data led_rsc_data[] = {
+	DT_COMPAT_FOREACH_STATUS_OKAY_VARGS(gpio_leds, DEFINE_LEDS_CTX)};
+
+static struct led_rsc_ctx led_rsc_ctx = {
+	.led = led_rsc_data,
+	.count = ARRAY_SIZE(led_rsc_data),
+};
+
+static otCoapResource led_rsc = {
+	.mUriPath = LED_URI,
+	.mHandler = led_handler,
+	.mContext = &led_rsc_ctx,
+	.mNext = NULL,
+};
+
+void coap_led_reg_rsc(void)
+{
+	otInstance *ot = openthread_get_default_instance();
+
+	LOG_INF("Registering LED rsc");
+	led_init(&led_rsc);
+	otCoapAddResource(ot, &led_rsc);
+}
+#endif /* CONFIG_OT_COAP_SAMPLE_SERVER */
+
+static void coap_led_send_req_cb(void *ctx, otMessage *msg, const otMessageInfo *msg_info,
+				 otError error)
+{
+}
+
+int coap_led_set_state(const char *addr, int led_id, int state)
+{
+	uint8_t buf[COAP_MAX_BUF_SIZE];
+
+	struct json_led_state led_data = {
+		.led_id = led_id,
+		.state = state,
+	};
+
+	json_obj_encode_buf(json_led_state_descr, ARRAY_SIZE(json_led_state_descr), &led_data, buf,
+			    COAP_MAX_BUF_SIZE);
+
+	return coap_put_req_send(addr, LED_URI, buf, strlen(buf) + 1, coap_led_send_req_cb, NULL);
+}
+
+static void coap_led_get_state_cb(void *ctx, otMessage *msg, const otMessageInfo *msg_info,
+				  otError error)
+{
+	uint8_t buf[COAP_MAX_BUF_SIZE];
+	int len = COAP_MAX_BUF_SIZE;
+	struct json_led_get *led = (struct json_led_get *)ctx;
+	int ret;
+
+	ret = coap_get_data(msg, buf, &len);
+	if (ret) {
+		led->count = 0;
+		goto exit;
+	}
+
+	json_obj_parse(buf, len, json_led_get_descr, ARRAY_SIZE(json_led_get_descr), led);
+exit:
+	k_sem_give(&led_get_sem);
+}
+
+int coap_led_get_state(const char *addr, int led_id, int *state)
+{
+	struct json_led_get led;
+	int ret;
+
+	ret = coap_get_req_send(addr, LED_URI, NULL, 0, coap_led_get_state_cb, &led);
+	if (ret) {
+		return ret;
+	}
+
+	ret = k_sem_take(&led_get_sem, K_FOREVER);
+	if (ret) {
+		return ret;
+	}
+
+	if (led_id >= led.count) {
+		return -ENODEV;
+	}
+
+	*state = led.leds[led_id].state;
+	return ret;
+}
diff --git a/samples/net/openthread/coap/src/led.h b/samples/net/openthread/coap/src/led.h
new file mode 100644
index 00000000000..6c07f65d4e4
--- /dev/null
+++ b/samples/net/openthread/coap/src/led.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2024 Alexandre Bailon
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef COAP_LED_H
+#define COAP_LED_H
+
+#include <zephyr/data/json.h>
+
+#define LED_URI "led"
+
+#define LED_MSG_STATE_OFF    0
+#define LED_MSG_STATE_ON     1
+#define LED_MSG_STATE_TOGGLE 2
+
+#define JSON_MAX_LED 4
+
+struct json_led_state {
+	int led_id;
+	int state;
+};
+
+struct json_led_get {
+	const char *device_id;
+	struct json_led_state leds[JSON_MAX_LED];
+	int count;
+};
+
+int coap_led_set_state(const char *addr, int led_id, int state);
+int coap_led_get_state(const char *addr, int led_id, int *state);
+
+#ifdef CONFIG_OT_COAP_SAMPLE_SERVER
+void coap_led_reg_rsc(void);
+#endif /* CONFIG_OT_COAP_SAMPLE_SERVER */
+
+#endif /* COAP_LED_H */
diff --git a/samples/net/openthread/coap/src/main.c b/samples/net/openthread/coap/src/main.c
new file mode 100644
index 00000000000..f9d3fbf6c5f
--- /dev/null
+++ b/samples/net/openthread/coap/src/main.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2024 Alexandre Bailon
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(coap);
+
+#include <coap_utils.h>
+
+#ifdef CONFIG_OT_COAP_SAMPLE_LED
+#include "led.h"
+#endif /* CONFIG_OT_COAP_SAMPLE_LED */
+
+#ifdef CONFIG_OT_COAP_SAMPLE_SW
+#include <zephyr/drivers/gpio.h>
+#include "button.h"
+
+/*
+ * Get button configuration from the devicetree sw0 alias. This is mandatory.
+ */
+#define SW0_NODE DT_ALIAS(sw0)
+#if !DT_NODE_HAS_STATUS_OKAY(SW0_NODE)
+#error "Unsupported board: sw0 devicetree alias is not defined"
+#endif
+static const struct gpio_dt_spec button = GPIO_DT_SPEC_GET_OR(SW0_NODE, gpios, {0});
+static struct gpio_callback button_cb_data;
+
+void button_pressed(const struct device *dev, struct gpio_callback *cb, uint32_t pins)
+{
+	coap_led_set_state("ff03::1", 0, LED_MSG_STATE_TOGGLE);
+}
+#endif /* CONFIG_OT_COAP_SAMPLE_SW */
+
+int main(void)
+{
+	int ret;
+
+#ifdef CONFIG_OT_COAP_SAMPLE_SERVER
+#ifdef CONFIG_OT_COAP_SAMPLE_LED
+	coap_led_reg_rsc();
+#endif /* CONFIG_OT_COAP_SAMPLE_LED */
+#ifdef CONFIG_OT_COAP_SAMPLE_SW
+	coap_btn_reg_rsc();
+#endif /* CONFIG_OT_COAP_SAMPLE_SW */
+#endif /* CONFIG_OT_COAP_SAMPLE_SERVER */
+
+	ret = coap_init();
+	if (ret) {
+		return ret;
+	}
+
+#ifdef CONFIG_OT_COAP_SAMPLE_SW
+	button_init(&button);
+
+	gpio_init_callback(&button_cb_data, button_pressed, BIT(button.pin));
+	gpio_add_callback_dt(&button, &button_cb_data);
+#endif /*CONFIG_OT_COAP_SAMPLE_SW */
+
+	return 0;
+}
diff --git a/samples/net/openthread/coprocessor/overlay-tri-n4m-br.conf b/samples/net/openthread/coprocessor/overlay-tri-n4m-br.conf
index 4cb1b26b30d..35781afcf5e 100644
--- a/samples/net/openthread/coprocessor/overlay-tri-n4m-br.conf
+++ b/samples/net/openthread/coprocessor/overlay-tri-n4m-br.conf
@@ -16,6 +16,5 @@ CONFIG_USB_REQUEST_BUFFER_SIZE=2048
 
 # disable ethernet on K64
 CONFIG_NET_L2_ETHERNET=n
-CONFIG_ETH_MCUX=n
 
 CONFIG_ISR_STACK_SIZE=4096
diff --git a/samples/net/pkt_filter/CMakeLists.txt b/samples/net/pkt_filter/CMakeLists.txt
new file mode 100644
index 00000000000..e7491e45d3c
--- /dev/null
+++ b/samples/net/pkt_filter/CMakeLists.txt
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(pkt_filter)
+
+target_sources(app PRIVATE src/main.c)
+
+include(${ZEPHYR_BASE}/samples/net/common/common.cmake)
diff --git a/samples/net/pkt_filter/Kconfig b/samples/net/pkt_filter/Kconfig
new file mode 100644
index 00000000000..5a084b0fff5
--- /dev/null
+++ b/samples/net/pkt_filter/Kconfig
@@ -0,0 +1,7 @@
+# Private config options for pkt_filter sample app
+
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+source "samples/net/common/Kconfig"
+source "Kconfig.zephyr"
diff --git a/samples/net/pkt_filter/README.rst b/samples/net/pkt_filter/README.rst
new file mode 100644
index 00000000000..2759085475b
--- /dev/null
+++ b/samples/net/pkt_filter/README.rst
@@ -0,0 +1,120 @@
+.. zephyr:code-sample:: net-pkt-filter
+   :name: Network packet filter
+   :relevant-api: net_pkt_filter
+
+   Install network packet filter hooks.
+
+Overview
+********
+
+This sample shows how to set network packet filters from a user application.
+
+The source code for this sample application can be found at:
+:zephyr_file:`samples/net/pkt_filter`.
+
+Requirements
+************
+
+- :ref:`networking_with_host`
+
+Building and Running
+********************
+
+A good way to run this sample application is with QEMU or native_sim board
+as described in :ref:`networking_with_host`.
+
+For demo purposes, the VLAN support needs to be enabled in host side like this.
+Execute these commands in a terminal window:
+
+.. code-block:: console
+
+   $ cd tools/net-tools
+   $ ./net-setup.sh  -c zeth-vlan.conf
+
+Then follow these steps to build the network packet filter sample application for
+either ``qemu_x86`` or ``native_sim`` boards:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/net/pkt_filter
+   :board: <board to use>
+   :conf: "prj.conf overlay-vlan.conf"
+   :goals: build
+   :compact:
+
+In this example, we enable VLAN support with these settings:
+
+The VLAN overlay configuration file :zephyr_file:`samples/net/pkt_filter/overlay-vlan.conf`
+creates two virtual LAN networks with these settings:
+
+- VLAN tag 100: IPv4 198.51.100.1 and IPv6 2001:db8:100::1
+- VLAN tag 200: IPv4 203.0.113.1 and IPv6 2001:db8:200::1
+
+In network shell, you can monitor the network packet filters:
+
+.. code-block:: console
+
+   uart:~$ net filter
+   Rule  Type        Verdict  Tests
+   [ 1]  recv        OK       3    eth vlan type[0x0800],size max[200],iface[2]
+   [ 2]  recv        OK       3    eth vlan type[0x0800],size min[100],iface[3]
+   [ 3]  recv        OK       1    iface[1]
+   [ 4]  recv        OK       2    eth vlan type[0x0806],iface[2]
+   [ 5]  recv        OK       2    eth vlan type[0x0806],iface[3]
+   [ 6]  recv        DROP     0
+
+The above sample application network packet filter rules can be interpreted
+like this:
+
+* Rule 1: Allow IPv4 (Ethernet type 0x0800) packets with max size 200 bytes
+  to network interface 2 which is the first VLAN interface.
+
+* Rule 2: Allow IPv4 packets with min size 100 bytes to network interface 3
+  which is the second VLAN interface.
+
+* Rule 3: Allow all incoming traffic to Ethernet interface 1
+
+* Rule 4: Allow ARP packets (Ethernet type 0x0806) to VLAN interface 2
+
+* Rule 5: Allow ARP packets (Ethernet type 0x0806) to VLAN interface 3
+
+* Rule 6: Drop all other packets. This also means that IPv6 packets are
+  dropped.
+
+The network statistics can be used to see that the packets are dropped.
+Use ``net stats`` command to monitor statistics.
+
+You can verify the rules from network shell:
+
+.. code-block:: console
+
+   uart:~$ net ping 2001:db8:100::2 -c 2
+   PING 2001:db8:100::2
+   Ping timeout
+   uart:~$ net stats 2
+   Interface 0x8089c6c (Virtual) [2]
+   ==================================
+   IPv6 recv      0        sent    3       drop    0       forwarded       0
+   IPv6 ND recv   0        sent    7       drop    1
+   IPv6 MLD recv  0        sent    0       drop    0
+   ICMP recv      0        sent    3       drop    0
+   ...
+   Filter drop rx 10       tx      0
+   Bytes received 320
+   Bytes sent     660
+   Processing err 10
+
+   uart:~$ net ping 198.51.100.2 -c 1
+   PING 198.51.100.2
+   28 bytes from 198.51.100.2 to 198.51.100.1: icmp_seq=1 ttl=64 time=100 ms
+
+   uart:~$ net ping 198.51.100.2 -c 1 -s 201
+   PING 198.51.100.2
+   Ping timeout
+
+   uart:~$ net ping 203.0.113.2 -c 1
+   PING 203.0.113.2
+   Ping timeout
+
+   uart:~$ net ping 203.0.113.2 -c 1 -s 101
+   PING 203.0.113.2
+   125 bytes from 203.0.113.2 to 203.0.113.1: icmp_seq=1 ttl=64 time=20 ms
diff --git a/samples/net/pkt_filter/overlay-vlan.conf b/samples/net/pkt_filter/overlay-vlan.conf
new file mode 100644
index 00000000000..21da953356e
--- /dev/null
+++ b/samples/net/pkt_filter/overlay-vlan.conf
@@ -0,0 +1,23 @@
+CONFIG_NET_VLAN=y
+
+# Allow useful interface assigned to VLAN interface
+CONFIG_NET_INTERFACE_NAME_LEN=15
+
+# We have one non-vlan interface and two VLAN interfaces
+CONFIG_NET_VLAN_COUNT=2
+
+# There will be three network interfaces so allocate enough IPv4 and IPv6 configs.
+CONFIG_NET_IF_MAX_IPV4_COUNT=3
+CONFIG_NET_IF_MAX_IPV6_COUNT=3
+
+# First ethernet interface will use these settings
+CONFIG_NET_CONFIG_MY_IPV6_ADDR="2001:db8::1"
+CONFIG_NET_CONFIG_PEER_IPV6_ADDR="2001:db8::2"
+CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.0.2.1"
+CONFIG_NET_CONFIG_PEER_IPV4_ADDR="192.0.2.2"
+
+# First VLAN interface will have these settings
+CONFIG_NET_SAMPLE_COMMON_VLAN_SETUP_1="100;2001:db8:100::1/64,198.51.100.1/24"
+
+# Second VLAN interface will have these settings
+CONFIG_NET_SAMPLE_COMMON_VLAN_SETUP_2="200;2001:db8:200::1/64,203.0.113.1/24"
diff --git a/samples/net/pkt_filter/prj.conf b/samples/net/pkt_filter/prj.conf
new file mode 100644
index 00000000000..1ec1c27ef7f
--- /dev/null
+++ b/samples/net/pkt_filter/prj.conf
@@ -0,0 +1,54 @@
+# Generic network options
+CONFIG_NETWORKING=y
+CONFIG_NET_LOG=y
+CONFIG_NET_IPV6=y
+CONFIG_NET_IPV4=y
+CONFIG_NET_DHCPV4=n
+CONFIG_NET_UDP=y
+CONFIG_NET_TCP=y
+CONFIG_NET_L2_ETHERNET=y
+
+# Enable packet filtering
+CONFIG_NET_PKT_FILTER=y
+CONFIG_NET_PKT_FILTER_IPV4_HOOK=y
+CONFIG_NET_PKT_FILTER_IPV6_HOOK=y
+CONFIG_NET_PKT_FILTER_LOCAL_IN_HOOK=y
+
+# Network statistics options
+CONFIG_NET_STATISTICS=y
+CONFIG_NET_STATISTICS_USER_API=y
+CONFIG_NET_STATISTICS_PER_INTERFACE=y
+CONFIG_NET_STATISTICS_ETHERNET=y
+
+CONFIG_TEST_RANDOM_GENERATOR=y
+
+# Network packet configuration
+CONFIG_NET_PKT_RX_COUNT=32
+CONFIG_NET_PKT_TX_COUNT=32
+CONFIG_NET_BUF_RX_COUNT=32
+CONFIG_NET_BUF_TX_COUNT=32
+
+# IP address configuration
+CONFIG_NET_IF_UNICAST_IPV6_ADDR_COUNT=5
+CONFIG_NET_IF_MCAST_IPV6_ADDR_COUNT=5
+CONFIG_NET_IF_UNICAST_IPV4_ADDR_COUNT=1
+CONFIG_NET_MAX_CONTEXTS=10
+
+CONFIG_INIT_STACKS=y
+CONFIG_PRINTK=y
+CONFIG_NET_SHELL=y
+
+# Application configuration
+CONFIG_NET_CONFIG_NEED_IPV6=y
+CONFIG_NET_CONFIG_NEED_IPV4=y
+CONFIG_NET_CONFIG_SETTINGS=y
+
+# IP address configuration
+CONFIG_NET_CONFIG_MY_IPV6_ADDR="2001:db8::1"
+CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.0.2.1"
+CONFIG_NET_CONFIG_PEER_IPV6_ADDR="2001:db8::2"
+CONFIG_NET_CONFIG_PEER_IPV4_ADDR="192.0.2.2"
+
+# Logging
+CONFIG_LOG=y
+CONFIG_LOG_BUFFER_SIZE=4096
diff --git a/samples/net/pkt_filter/sample.yaml b/samples/net/pkt_filter/sample.yaml
new file mode 100644
index 00000000000..7122b4b8926
--- /dev/null
+++ b/samples/net/pkt_filter/sample.yaml
@@ -0,0 +1,14 @@
+sample:
+  description: Network packet filtering functionality
+  name: Network packet filter sample app
+tests:
+  sample.net.pkt_filter:
+    harness: net
+    min_ram: 64
+    tags:
+      - net
+      - statistics
+      - net_pkt_filter
+    depends_on: netif
+    integration_platforms:
+      - native_sim
diff --git a/samples/net/pkt_filter/src/main.c b/samples/net/pkt_filter/src/main.c
new file mode 100644
index 00000000000..d88a29436be
--- /dev/null
+++ b/samples/net/pkt_filter/src/main.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(net_stats_sample, LOG_LEVEL_DBG);
+
+#include <zephyr/kernel.h>
+#include <errno.h>
+
+#include <zephyr/net/net_core.h>
+#include <zephyr/net/net_if.h>
+#include <zephyr/net/ethernet.h>
+#include <zephyr/net/net_pkt_filter.h>
+
+#include "net_sample_common.h"
+
+#define MAX_INTERFACES 3
+
+static struct net_if *interfaces[MAX_INTERFACES];
+
+/* Interface match rule. The interface value is set at runtime in init_app() */
+static NPF_IFACE_MATCH(match_iface_vlan1, NULL);
+static NPF_IFACE_MATCH(match_iface_vlan2, NULL);
+static NPF_IFACE_MATCH(match_iface_eth, NULL);
+
+/* Allow all traffic to Ethernet interface, drop VLAN traffic except
+ * couple of exceptions for IPv4 and IPv6
+ */
+static NPF_RULE(eth_iface_rule, NET_OK, match_iface_eth);
+
+/* Match max size rule */
+static NPF_SIZE_MAX(maxsize_200, 200);
+static NPF_ETH_VLAN_TYPE_MATCH(ipv4_packet1, NET_ETH_PTYPE_IP);
+static NPF_RULE(small_ipv4_pkt, NET_OK, ipv4_packet1, maxsize_200,
+		match_iface_vlan1);
+
+/* Match min size rule */
+static NPF_SIZE_MIN(minsize_100, 100);
+static NPF_ETH_VLAN_TYPE_MATCH(ipv4_packet2, NET_ETH_PTYPE_IP);
+static NPF_RULE(large_ipv4_pkt, NET_OK, ipv4_packet2, minsize_100,
+		match_iface_vlan2);
+
+/* Allow ARP for VLAN interface */
+static NPF_ETH_VLAN_TYPE_MATCH(arp_packet, NET_ETH_PTYPE_ARP);
+static NPF_RULE(arp_pkt_vlan1, NET_OK, arp_packet, match_iface_vlan1);
+static NPF_RULE(arp_pkt_vlan2, NET_OK, arp_packet, match_iface_vlan2);
+
+static void iface_cb(struct net_if *iface, void *user_data)
+{
+	int count = 0;
+
+	ARG_UNUSED(user_data);
+
+	ARRAY_FOR_EACH(interfaces, i) {
+		if (interfaces[i] == NULL) {
+			interfaces[i] = iface;
+			return;
+		}
+
+		count++;
+	}
+
+	LOG_ERR("Too many interfaces %d (max is %d)", count, MAX_INTERFACES);
+}
+
+static void init_app(void)
+{
+	struct net_if *iface, *eth = NULL, *vlan1 = NULL, *vlan2 = NULL;
+	int found = 0;
+
+	ARRAY_FOR_EACH(interfaces, i) {
+		if (interfaces[i] == NULL) {
+			continue;
+		}
+
+		iface = interfaces[i];
+
+		if (net_eth_is_vlan_interface(iface)) {
+			if (vlan1 == NULL) {
+				vlan1 = iface;
+			} else if (vlan2 == NULL) {
+				vlan2 = iface;
+			}
+		} else if (net_if_l2(iface) == &NET_L2_GET_NAME(ETHERNET)) {
+			eth = iface;
+		} else {
+			continue;
+		}
+
+		found++;
+	}
+
+	if (found == 0) {
+		LOG_ERR("No interfaces found");
+		return;
+	}
+
+	match_iface_vlan1.iface = vlan1;
+	match_iface_vlan2.iface = vlan2;
+	match_iface_eth.iface = eth;
+
+	/* The sample will setup the Ethernet interface and two VLAN
+	 * optional interfaces (if VLAN is enabled).
+	 * We allow all traffic to the Ethernet interface, but have
+	 * filters for the VLAN interfaces.
+	 */
+
+	/* We allow small IPv4 packets to the VLAN interface 1 */
+	npf_append_recv_rule(&small_ipv4_pkt);
+
+	/* We allow large IPv4 packets to the VLAN interface 2 */
+	npf_append_recv_rule(&large_ipv4_pkt);
+
+	/* We allow all traffic to the Ethernet interface */
+	npf_append_recv_rule(&eth_iface_rule);
+
+	/* We allow ARP traffic to the VLAN 1 interface */
+	npf_append_recv_rule(&arp_pkt_vlan1);
+
+	/* We allow ARP traffic to the VLAN 2 interface */
+	npf_append_recv_rule(&arp_pkt_vlan2);
+
+	/* The remaining packets that do not match are dropped */
+	npf_append_recv_rule(&npf_default_drop);
+}
+
+int main(void)
+{
+	net_if_foreach(iface_cb, interfaces);
+
+	init_vlan();
+	init_app();
+
+	return 0;
+}
diff --git a/samples/net/prometheus/prj.conf b/samples/net/prometheus/prj.conf
index d7c2741f01e..b863915a838 100644
--- a/samples/net/prometheus/prj.conf
+++ b/samples/net/prometheus/prj.conf
@@ -5,7 +5,7 @@ CONFIG_LOG=y
 CONFIG_ENTROPY_GENERATOR=y
 CONFIG_TEST_RANDOM_GENERATOR=y
 CONFIG_INIT_STACKS=y
-CONFIG_POSIX_MAX_FDS=32
+CONFIG_ZVFS_OPEN_MAX=32
 CONFIG_POSIX_API=y
 CONFIG_FDTABLE=y
 CONFIG_NET_SOCKETS_POLL_MAX=32
diff --git a/samples/net/prometheus/sample.yaml b/samples/net/prometheus/sample.yaml
index 57fa5abfef1..944e0df61a3 100644
--- a/samples/net/prometheus/sample.yaml
+++ b/samples/net/prometheus/sample.yaml
@@ -11,10 +11,9 @@ common:
     - server
     - socket
     - prometheus
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
   # Exclude CONFIG_HAS_RENESAS_RA_FSP as Renesas RA HAL has build error with mbedtls Socket
   filter: not CONFIG_HAS_RENESAS_RA_FSP
+  integration_platforms:
+    - qemu_x86
 tests:
   sample.net.prometheus: {}
diff --git a/samples/net/prometheus/src/main.c b/samples/net/prometheus/src/main.c
index 7f0f152a27f..61aa362cc32 100644
--- a/samples/net/prometheus/src/main.c
+++ b/samples/net/prometheus/src/main.c
@@ -39,8 +39,8 @@ struct app_context {
 
 #if defined(CONFIG_NET_SAMPLE_HTTP_SERVICE)
 static uint16_t test_http_service_port = CONFIG_NET_SAMPLE_HTTP_SERVER_SERVICE_PORT;
-HTTP_SERVICE_DEFINE(test_http_service, CONFIG_NET_CONFIG_MY_IPV4_ADDR, &test_http_service_port, 1,
-		    10, NULL);
+HTTP_SERVICE_DEFINE(test_http_service, CONFIG_NET_CONFIG_MY_IPV4_ADDR, &test_http_service_port,
+		    CONFIG_HTTP_SERVER_MAX_CLIENTS, 10, NULL, NULL);
 
 static int dyn_handler(struct http_client_ctx *client, enum http_data_status status,
 		       const struct http_request_ctx *request_ctx,
@@ -99,7 +99,8 @@ const sec_tag_t sec_tag_list_verify_none[] = {
 
 static uint16_t test_https_service_port = CONFIG_NET_SAMPLE_HTTPS_SERVER_SERVICE_PORT;
 HTTPS_SERVICE_DEFINE(test_https_service, CONFIG_NET_CONFIG_MY_IPV4_ADDR, &test_https_service_port,
-		     1, 10, NULL, sec_tag_list_verify_none, sizeof(sec_tag_list_verify_none));
+		     CONFIG_HTTP_SERVER_MAX_CLIENTS, 10, NULL, NULL, sec_tag_list_verify_none,
+		     sizeof(sec_tag_list_verify_none));
 
 HTTP_RESOURCE_DEFINE(index_html_gz_resource_https, test_https_service, "/metrics",
 		     &dyn_resource_detail);
diff --git a/samples/net/ptp/boards/native_posix.conf b/samples/net/ptp/boards/native_posix.conf
deleted file mode 100644
index e2f26372eed..00000000000
--- a/samples/net/ptp/boards/native_posix.conf
+++ /dev/null
@@ -1,8 +0,0 @@
-# Settings for native_posix ethernet driver
-CONFIG_ETH_NATIVE_POSIX_PTP_CLOCK=y
-
-#CONFIG_ETH_NATIVE_POSIX_RANDOM_MAC=y
-CONFIG_ETH_NATIVE_POSIX_MAC_ADDR="00:00:5e:00:53:2a"
-
-# Assume 1 ms accuracy for native_posix simulated clock
-CONFIG_PTP_CLOCK_ACCURACY_1MS=y
diff --git a/samples/net/ptp/boards/native_posix_native_64.conf b/samples/net/ptp/boards/native_posix_native_64.conf
deleted file mode 100644
index e2f26372eed..00000000000
--- a/samples/net/ptp/boards/native_posix_native_64.conf
+++ /dev/null
@@ -1,8 +0,0 @@
-# Settings for native_posix ethernet driver
-CONFIG_ETH_NATIVE_POSIX_PTP_CLOCK=y
-
-#CONFIG_ETH_NATIVE_POSIX_RANDOM_MAC=y
-CONFIG_ETH_NATIVE_POSIX_MAC_ADDR="00:00:5e:00:53:2a"
-
-# Assume 1 ms accuracy for native_posix simulated clock
-CONFIG_PTP_CLOCK_ACCURACY_1MS=y
diff --git a/samples/net/ptp/boards/native_sim.conf b/samples/net/ptp/boards/native_sim.conf
index e2f26372eed..830898e1d9a 100644
--- a/samples/net/ptp/boards/native_sim.conf
+++ b/samples/net/ptp/boards/native_sim.conf
@@ -1,8 +1,8 @@
-# Settings for native_posix ethernet driver
-CONFIG_ETH_NATIVE_POSIX_PTP_CLOCK=y
+# Settings for native_sim / native_tap ethernet driver
+CONFIG_ETH_NATIVE_TAP_PTP_CLOCK=y
 
-#CONFIG_ETH_NATIVE_POSIX_RANDOM_MAC=y
-CONFIG_ETH_NATIVE_POSIX_MAC_ADDR="00:00:5e:00:53:2a"
+#CONFIG_ETH_NATIVE_TAP_RANDOM_MAC=y
+CONFIG_ETH_NATIVE_TAP_MAC_ADDR="00:00:5e:00:53:2a"
 
-# Assume 1 ms accuracy for native_posix simulated clock
+# Assume 1 ms accuracy for native_sim simulated clock
 CONFIG_PTP_CLOCK_ACCURACY_1MS=y
diff --git a/samples/net/ptp/boards/native_sim_native_64.conf b/samples/net/ptp/boards/native_sim_native_64.conf
index e2f26372eed..830898e1d9a 100644
--- a/samples/net/ptp/boards/native_sim_native_64.conf
+++ b/samples/net/ptp/boards/native_sim_native_64.conf
@@ -1,8 +1,8 @@
-# Settings for native_posix ethernet driver
-CONFIG_ETH_NATIVE_POSIX_PTP_CLOCK=y
+# Settings for native_sim / native_tap ethernet driver
+CONFIG_ETH_NATIVE_TAP_PTP_CLOCK=y
 
-#CONFIG_ETH_NATIVE_POSIX_RANDOM_MAC=y
-CONFIG_ETH_NATIVE_POSIX_MAC_ADDR="00:00:5e:00:53:2a"
+#CONFIG_ETH_NATIVE_TAP_RANDOM_MAC=y
+CONFIG_ETH_NATIVE_TAP_MAC_ADDR="00:00:5e:00:53:2a"
 
-# Assume 1 ms accuracy for native_posix simulated clock
+# Assume 1 ms accuracy for native_sim simulated clock
 CONFIG_PTP_CLOCK_ACCURACY_1MS=y
diff --git a/samples/net/secure_mqtt_sensor_actuator/overlay-static-insecure.conf b/samples/net/secure_mqtt_sensor_actuator/overlay-static-insecure.conf
index 33655bfe4e1..cd6fa5a7166 100644
--- a/samples/net/secure_mqtt_sensor_actuator/overlay-static-insecure.conf
+++ b/samples/net/secure_mqtt_sensor_actuator/overlay-static-insecure.conf
@@ -1,7 +1,7 @@
 # Config to disable TLS and DHCPv4, allowing insecure MQTT and a static IP address.
 # This allows quick testing of the application without need for a DHCP server or secure MQTT broker set up.
 # Only recommended for quick sampling/testing.
-# Usage: west build -b <board> -- -DOVERLAY_CONFIG=overlay-static-insecure.conf
+# Usage: west build -b <board> -- -DEXTRA_CONF_FILE=overlay-static-insecure.conf
 
 # Disable MQTT with TLS
 CONFIG_MQTT_LIB_TLS=n
diff --git a/samples/net/sockets/big_http_download/sample.yaml b/samples/net/sockets/big_http_download/sample.yaml
index 0851eeffec0..4c70c0d15d0 100644
--- a/samples/net/sockets/big_http_download/sample.yaml
+++ b/samples/net/sockets/big_http_download/sample.yaml
@@ -10,9 +10,6 @@ common:
   tags:
     - net
     - socket
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   sample.net.sockets.big_http_download:
     extra_configs:
diff --git a/samples/net/sockets/can/sample.yaml b/samples/net/sockets/can/sample.yaml
index a9dff7079d3..4e1d9d1c9fa 100644
--- a/samples/net/sockets/can/sample.yaml
+++ b/samples/net/sockets/can/sample.yaml
@@ -8,10 +8,6 @@ common:
   filter: dt_chosen_enabled("zephyr,canbus") and not dt_compat_enabled("kvaser,pcican")
   depends_on: can
   harness: console
-  # native_posix does not work with CONFIG_POSIX_API
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   sample.net.sockets.can.one_socket:
     extra_configs:
diff --git a/samples/net/sockets/coap_download/src/main.c b/samples/net/sockets/coap_download/src/main.c
index 2bc935f9d7d..bb15551cfba 100644
--- a/samples/net/sockets/coap_download/src/main.c
+++ b/samples/net/sockets/coap_download/src/main.c
@@ -82,6 +82,8 @@ static void do_coap_download(struct sockaddr *sa)
 	/* Wait for CoAP request to complete */
 	k_sem_take(&coap_done_sem, K_FOREVER);
 
+	coap_client_cancel_requests(&client);
+
 	zsock_close(sockfd);
 }
 
diff --git a/samples/net/sockets/coap_server/boards/native_posix.conf b/samples/net/sockets/coap_server/boards/native_posix.conf
deleted file mode 100644
index b8f2d57be74..00000000000
--- a/samples/net/sockets/coap_server/boards/native_posix.conf
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_NET_L2_ETHERNET=y
-CONFIG_NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME=y
-CONFIG_NATIVE_UART_0_ON_STDINOUT=y
diff --git a/samples/net/sockets/coap_server/boards/native_sim.conf b/samples/net/sockets/coap_server/boards/native_sim.conf
index ac091ebe5db..605b575e76a 100644
--- a/samples/net/sockets/coap_server/boards/native_sim.conf
+++ b/samples/net/sockets/coap_server/boards/native_sim.conf
@@ -1,4 +1,4 @@
 CONFIG_NET_L2_ETHERNET=y
 CONFIG_NATIVE_SIM_SLOWDOWN_TO_REAL_TIME=y
-CONFIG_NATIVE_UART_0_ON_STDINOUT=y
+CONFIG_UART_NATIVE_PTY_0_ON_STDINOUT=y
 CONFIG_PICOLIBC=y
diff --git a/samples/net/sockets/dumb_http_server/overlay-netusb.conf b/samples/net/sockets/dumb_http_server/overlay-netusb.conf
deleted file mode 100644
index b39bdaac0f6..00000000000
--- a/samples/net/sockets/dumb_http_server/overlay-netusb.conf
+++ /dev/null
@@ -1,9 +0,0 @@
-# USB Device settings
-CONFIG_USB_DEVICE_STACK=y
-
-# Select USB Configurations
-CONFIG_USB_DEVICE_NETWORK_ECM=y
-
-# Logging
-CONFIG_USB_DRIVER_LOG_LEVEL_INF=y
-CONFIG_USB_DEVICE_LOG_LEVEL_INF=y
diff --git a/samples/net/sockets/dumb_http_server/sample.yaml b/samples/net/sockets/dumb_http_server/sample.yaml
index 7e076a94eb1..301f70820d4 100644
--- a/samples/net/sockets/dumb_http_server/sample.yaml
+++ b/samples/net/sockets/dumb_http_server/sample.yaml
@@ -14,25 +14,3 @@ tests:
   sample.net.sockets.dumb_http_server:
     extra_configs:
       - CONFIG_POSIX_API=y
-  sample.net.sockets.dumb_http_server.netusb:
-    depends_on: usb_device
-    harness: net
-    extra_args: EXTRA_CONF_FILE="overlay-netusb.conf"
-    tags: usb
-    # native_sim usb driver does not work with CONFIG_POSIX_API
-    platform_exclude:
-      - native_sim
-      - native_sim/native/64
-      - native_posix
-      - native_posix/native/64
-  sample.net.sockets.dumb_http_server.netusb_zeroconf:
-    depends_on: usb_device
-    harness: net
-    extra_args: EXTRA_CONF_FILE="overlay-netusb.conf;overlay-zeroconf.conf"
-    tags: usb
-    # native_sim usb driver does not work with CONFIG_POSIX_API
-    platform_exclude:
-      - native_sim
-      - native_sim/native/64
-      - native_posix
-      - native_posix/native/64
diff --git a/samples/net/sockets/dumb_http_server_mt/docker-test.sh b/samples/net/sockets/dumb_http_server_mt/docker-test.sh
index 442272c86fe..5036b140a7e 100644
--- a/samples/net/sockets/dumb_http_server_mt/docker-test.sh
+++ b/samples/net/sockets/dumb_http_server_mt/docker-test.sh
@@ -36,7 +36,7 @@ fi
 if [ -n "$zephyr_overlay" ]; then
 	overlay="${zephyr_overlay};overlay-tls.conf"
 else
-	overlay="-DOVERLAY_CONFIG=overlay-tls.conf"
+	overlay="-DEXTRA_CONF_FILE=overlay-tls.conf"
 fi
 
 start_configuration || return $?
diff --git a/samples/net/sockets/dumb_http_server_mt/sample.yaml b/samples/net/sockets/dumb_http_server_mt/sample.yaml
index 4d278431c22..1fffeb3174d 100644
--- a/samples/net/sockets/dumb_http_server_mt/sample.yaml
+++ b/samples/net/sockets/dumb_http_server_mt/sample.yaml
@@ -10,10 +10,6 @@ common:
     - net
     - socket
     - http
-  # native_posix does not work with CONFIG_POSIX_API
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   sample.net.sockets.dumb_http_server_mt:
     extra_configs:
diff --git a/samples/net/sockets/echo_client/CMakeLists.txt b/samples/net/sockets/echo_client/CMakeLists.txt
index 0fe1ad126cc..0a176e2499b 100644
--- a/samples/net/sockets/echo_client/CMakeLists.txt
+++ b/samples/net/sockets/echo_client/CMakeLists.txt
@@ -21,7 +21,6 @@ endif()
 target_sources(                     app PRIVATE src/echo-client.c)
 target_sources_ifdef(CONFIG_NET_UDP app PRIVATE src/udp.c)
 target_sources_ifdef(CONFIG_NET_TCP app PRIVATE src/tcp.c)
-target_sources_ifdef(CONFIG_NET_VLAN app PRIVATE src/vlan.c)
 
 include(${ZEPHYR_BASE}/samples/net/common/common.cmake)
 
diff --git a/samples/net/sockets/echo_client/README.rst b/samples/net/sockets/echo_client/README.rst
index 02cc74b302d..db92c35104b 100644
--- a/samples/net/sockets/echo_client/README.rst
+++ b/samples/net/sockets/echo_client/README.rst
@@ -48,6 +48,10 @@ echo-client directory:
 - :file:`overlay-tls.conf`
   This overlay config enables support for TLS.
 
+- :file:`overlay-vlan.conf`
+  This overlay config enables support for Virtual LAN.
+  See :ref:`networking_samples_common` for details.
+
 Build echo-client sample application like this:
 
 .. zephyr-app-commands::
diff --git a/samples/net/sockets/echo_client/boards/frdm_mcxw71.conf b/samples/net/sockets/echo_client/boards/frdm_mcxw71.conf
new file mode 100644
index 00000000000..36b66408f86
--- /dev/null
+++ b/samples/net/sockets/echo_client/boards/frdm_mcxw71.conf
@@ -0,0 +1,4 @@
+CONFIG_COUNTER=y
+
+CONFIG_OPENTHREAD_MAX_IP_ADDR_PER_CHILD=4
+CONFIG_OPENTHREAD_MAX_CHILDREN=30
diff --git a/samples/net/sockets/echo_client/boards/frdm_mcxw71.overlay b/samples/net/sockets/echo_client/boards/frdm_mcxw71.overlay
new file mode 100644
index 00000000000..71da6a25089
--- /dev/null
+++ b/samples/net/sockets/echo_client/boards/frdm_mcxw71.overlay
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2023-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&stcm {
+	ranges = <0x0 0x30000000 DT_SIZE_K(112)>;
+
+	stcm1: system_memory@1a000 {
+		compatible = "zephyr,memory-region","mmio-sram";
+		reg = <0x1a000 DT_SIZE_K(4)>;
+		zephyr,memory-region = "RetainedMem";
+	};
+};
+
+&stcm0 {
+	/* With only the first 64KB having ECC */
+	reg = <0x0 DT_SIZE_K(108)>;
+};
diff --git a/samples/net/sockets/echo_client/overlay-vlan.conf b/samples/net/sockets/echo_client/overlay-vlan.conf
index 73d1fc9cb6e..c34f79c3ac7 100644
--- a/samples/net/sockets/echo_client/overlay-vlan.conf
+++ b/samples/net/sockets/echo_client/overlay-vlan.conf
@@ -12,16 +12,8 @@ CONFIG_NET_CONFIG_PEER_IPV6_ADDR="2001:db8::2"
 CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.0.2.1"
 CONFIG_NET_CONFIG_PEER_IPV4_ADDR="192.0.2.2"
 
-# Second ethernet interface will have these settings
-CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR="2001:db8:100::1"
-# TEST-NET-2 from RFC 5737
-CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR="198.51.100.1"
-# VLAN tag for the second interface
-CONFIG_NET_SAMPLE_IFACE2_VLAN_TAG=100
+# First VLAN interface will have these settings
+CONFIG_NET_SAMPLE_COMMON_VLAN_SETUP_1="100;2001:db8:100::1/64,198.51.100.1/24"
 
-# Settings for the third network interface
-CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR="2001:db8:200::1"
-# TEST-NET-3 from RFC 5737
-CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR="203.0.113.1"
-# VLAN tag for the second interface
-CONFIG_NET_SAMPLE_IFACE3_VLAN_TAG=200
+# Second VLAN interface will have these settings
+CONFIG_NET_SAMPLE_COMMON_VLAN_SETUP_2="200;2001:db8:200::1/64,203.0.113.1/24"
diff --git a/samples/net/sockets/echo_client/sample.yaml b/samples/net/sockets/echo_client/sample.yaml
index ccde0349ed4..c640696c209 100644
--- a/samples/net/sockets/echo_client/sample.yaml
+++ b/samples/net/sockets/echo_client/sample.yaml
@@ -70,39 +70,27 @@ tests:
   sample.net.sockets.echo_client.nrf_802154:
     extra_args: EXTRA_CONF_FILE="overlay-802154.conf"
     platform_allow: nrf52840dk/nrf52840
-  sample.net.sockets.echo_client.nrf_openthread:
+  sample.net.sockets.echo_client.openthread:
     extra_args: EXTRA_CONF_FILE="overlay-ot.conf"
     slow: true
     tags:
       - net
       - openthread
-    platform_allow: nrf52840dk/nrf52840
+    platform_allow:
+      - frdm_kw41z
+      - frdm_mcxw71
+      - nrf52840dk/nrf52840
+      - tlsr9518adk80d
     filter: CONFIG_FULL_LIBC_SUPPORTED and not CONFIG_NATIVE_LIBC
   sample.net.sockets.echo_client.b91_802154:
     extra_args: EXTRA_CONF_FILE="overlay-802154.conf"
     platform_allow: tlsr9518adk80d
-  sample.net.sockets.echo_client.b91_openthread:
-    extra_args: EXTRA_CONF_FILE="overlay-ot.conf"
-    slow: true
-    tags:
-      - net
-      - openthread
-    platform_allow: tlsr9518adk80d
-    filter: CONFIG_FULL_LIBC_SUPPORTED and not CONFIG_NATIVE_LIBC
-  sample.net.sockets.echo_client.kw41z_openthread:
-    extra_args: EXTRA_CONF_FILE="overlay-ot.conf"
-    slow: true
-    tags:
-      - net
-      - openthread
-    platform_allow: frdm_kw41z
-    filter: CONFIG_FULL_LIBC_SUPPORTED and not CONFIG_NATIVE_LIBC
   sample.net.sockets.echo_client.rw612_openthread_rcp_host:
     build_only: true
     extra_args:
       # Disabling monolithic since CI environment doesn't use blobs
       - CONFIG_NXP_MONOLITHIC_NBU=n
-      - OVERLAY_CONFIG="overlay-ot-rcp-host-nxp.conf"
+      - EXTRA_CONF_FILE="overlay-ot-rcp-host-nxp.conf"
     slow: true
     tags:
       - net
diff --git a/samples/net/sockets/echo_client/src/common.h b/samples/net/sockets/echo_client/src/common.h
index 76bbc5604de..65749c83f7b 100644
--- a/samples/net/sockets/echo_client/src/common.h
+++ b/samples/net/sockets/echo_client/src/common.h
@@ -7,6 +7,8 @@
 
 #include <zephyr/kernel.h>
 
+#include "net_sample_common.h"
+
 /* Value of 0 will cause the IP stack to select next free port */
 #define MY_PORT 0
 
@@ -96,12 +98,3 @@ static inline void stop_udp(void) { }
 int start_tcp(void);
 int process_tcp(void);
 void stop_tcp(void);
-
-#if defined(CONFIG_NET_VLAN)
-int init_vlan(void);
-#else
-static inline int init_vlan(void)
-{
-	return 0;
-}
-#endif
diff --git a/samples/net/sockets/echo_client/src/vlan.c b/samples/net/sockets/echo_client/src/vlan.c
deleted file mode 100644
index f7b96c9863f..00000000000
--- a/samples/net/sockets/echo_client/src/vlan.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright (c) 2018 Intel Corporation.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/logging/log.h>
-LOG_MODULE_DECLARE(net_echo_client_sample, LOG_LEVEL_DBG);
-
-#include <zephyr/kernel.h>
-
-#include <zephyr/net/ethernet.h>
-
-/* User data for the interface callback */
-struct ud {
-	struct net_if *first;
-	struct net_if *second;
-};
-
-static void iface_cb(struct net_if *iface, void *user_data)
-{
-	struct ud *ud = user_data;
-
-	if (net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL)) {
-		return;
-	}
-
-	if (!ud->first) {
-		ud->first = iface;
-		return;
-	}
-
-	if (!ud->second) {
-		ud->second = iface;
-		return;
-	}
-}
-
-static int setup_iface(struct net_if *eth_iface,
-		       struct net_if *iface,
-		       const char *ipv6_addr,
-		       const char *ipv4_addr,
-		       uint16_t vlan_tag)
-{
-	struct net_if_addr *ifaddr;
-	struct in_addr addr4;
-	struct in6_addr addr6;
-	int ret;
-
-	ret = net_eth_vlan_enable(eth_iface, vlan_tag);
-	if (ret < 0) {
-		LOG_ERR("Cannot enable VLAN for tag %d (%d)", vlan_tag, ret);
-	}
-
-	if (net_addr_pton(AF_INET6, ipv6_addr, &addr6)) {
-		LOG_ERR("Invalid address: %s", ipv6_addr);
-		return -EINVAL;
-	}
-
-	ifaddr = net_if_ipv6_addr_add(iface, &addr6, NET_ADDR_MANUAL, 0);
-	if (!ifaddr) {
-		LOG_ERR("Cannot add %s to interface %p", ipv6_addr, iface);
-		return -EINVAL;
-	}
-
-	if (net_addr_pton(AF_INET, ipv4_addr, &addr4)) {
-		LOG_ERR("Invalid address: %s", ipv4_addr);
-		return -EINVAL;
-	}
-
-	ifaddr = net_if_ipv4_addr_add(iface, &addr4, NET_ADDR_MANUAL, 0);
-	if (!ifaddr) {
-		LOG_ERR("Cannot add %s to interface %p", ipv4_addr, iface);
-		return -EINVAL;
-	}
-
-	LOG_DBG("Interface %p VLAN tag %d setup done.", iface, vlan_tag);
-
-	return 0;
-}
-
-int init_vlan(void)
-{
-	struct net_if *iface;
-	struct ud ud;
-	int ret;
-
-	iface = net_if_get_first_by_type(&NET_L2_GET_NAME(ETHERNET));
-	if (!iface) {
-		LOG_ERR("No ethernet interfaces found.");
-		return -ENOENT;
-	}
-
-	memset(&ud, 0, sizeof(ud));
-
-	net_if_foreach(iface_cb, &ud);
-
-	ret = setup_iface(iface, ud.first,
-			  CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE2_VLAN_TAG);
-	if (ret < 0) {
-		return ret;
-	}
-
-	ret = setup_iface(iface, ud.second,
-			  CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE3_VLAN_TAG);
-	if (ret < 0) {
-		return ret;
-	}
-
-	/* Bring up the VLAN interface automatically */
-	net_if_up(ud.first);
-	net_if_up(ud.second);
-
-	return 0;
-}
diff --git a/samples/net/sockets/echo_server/CMakeLists.txt b/samples/net/sockets/echo_server/CMakeLists.txt
index 52251bca394..9f7ce64760d 100644
--- a/samples/net/sockets/echo_server/CMakeLists.txt
+++ b/samples/net/sockets/echo_server/CMakeLists.txt
@@ -21,8 +21,6 @@ endif()
 target_sources(                     app PRIVATE src/echo-server.c)
 target_sources_ifdef(CONFIG_NET_UDP app PRIVATE src/udp.c)
 target_sources_ifdef(CONFIG_NET_TCP app PRIVATE src/tcp.c)
-target_sources_ifdef(CONFIG_NET_VLAN app PRIVATE src/vlan.c)
-target_sources_ifdef(CONFIG_NET_L2_IPIP app PRIVATE src/tunnel.c)
 
 if (CONFIG_USB_DEVICE_STACK)
   target_sources(app PRIVATE src/usb.c)
diff --git a/samples/net/sockets/echo_server/Kconfig b/samples/net/sockets/echo_server/Kconfig
index 5f1334b7f19..66bd5b63ca2 100644
--- a/samples/net/sockets/echo_server/Kconfig
+++ b/samples/net/sockets/echo_server/Kconfig
@@ -27,51 +27,6 @@ config NET_SAMPLE_IFACE2_MY_IPV4_NETMASK
 	help
 	  The value depends on your network setup.
 
-config NET_SAMPLE_IFACE2_VLAN_TAG
-	int "VLAN tag for second interface"
-	default 100
-	range 0 4094
-	depends on NET_VLAN
-	help
-	  Set VLAN (virtual LAN) tag (id) that is used in the sample
-	  application.
-
-config NET_SAMPLE_IFACE3_MY_IPV6_ADDR
-	string "My IPv6 address for third interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE3_MY_IPV4_ADDR
-	string "My IPv4 address for third interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE3_MY_IPV4_NETMASK
-	string "My IPv4 netmask for third interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE3_VLAN_TAG
-	int "VLAN tag for third interface"
-	default 200
-	range 0 4094
-	depends on NET_VLAN
-	help
-	  Set VLAN (virtual LAN) tag (id) that is used in the sample
-	  application.
-
-config NET_SAMPLE_TUNNEL_PEER_ADDR
-	string "Remote IP address of the tunnel interface"
-	depends on NET_L2_IPIP
-	help
-	  Use overlay-tunnel.conf to setup the tunnel support.
-
-config NET_SAMPLE_TUNNEL_MY_ADDR
-	string "My address for tunnel interface"
-	depends on NET_L2_IPIP
-	help
-	  The value depends on your network setup.
-
 config NET_SAMPLE_PSK_HEADER_FILE
 	string "Header file containing PSK"
 	default "dummy_psk.h"
@@ -111,4 +66,5 @@ if USB_DEVICE_STACK_NEXT
 	source "samples/subsys/usb/common/Kconfig.sample_usbd"
 endif
 
+source "samples/net/common/Kconfig"
 source "Kconfig.zephyr"
diff --git a/samples/net/sockets/echo_server/README.rst b/samples/net/sockets/echo_server/README.rst
index cb4aa3756ae..c8d8a8bec94 100644
--- a/samples/net/sockets/echo_server/README.rst
+++ b/samples/net/sockets/echo_server/README.rst
@@ -52,6 +52,10 @@ echo-server directory:
 - :file:`overlay-tunnel.conf`
   This overlay config enables support for IP tunneling.
 
+- :file:`overlay-vlan.conf`
+  This overlay config enables support for Virtual LAN.
+  See :ref:`networking_samples_common` for details.
+
 Build echo-server sample application like this:
 
 .. zephyr-app-commands::
diff --git a/samples/net/sockets/echo_server/boards/frdm_mcxw71.conf b/samples/net/sockets/echo_server/boards/frdm_mcxw71.conf
new file mode 100644
index 00000000000..36b66408f86
--- /dev/null
+++ b/samples/net/sockets/echo_server/boards/frdm_mcxw71.conf
@@ -0,0 +1,4 @@
+CONFIG_COUNTER=y
+
+CONFIG_OPENTHREAD_MAX_IP_ADDR_PER_CHILD=4
+CONFIG_OPENTHREAD_MAX_CHILDREN=30
diff --git a/samples/net/sockets/echo_server/boards/frdm_mcxw71.overlay b/samples/net/sockets/echo_server/boards/frdm_mcxw71.overlay
new file mode 100644
index 00000000000..71da6a25089
--- /dev/null
+++ b/samples/net/sockets/echo_server/boards/frdm_mcxw71.overlay
@@ -0,0 +1,20 @@
+/*
+ * Copyright 2023-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&stcm {
+	ranges = <0x0 0x30000000 DT_SIZE_K(112)>;
+
+	stcm1: system_memory@1a000 {
+		compatible = "zephyr,memory-region","mmio-sram";
+		reg = <0x1a000 DT_SIZE_K(4)>;
+		zephyr,memory-region = "RetainedMem";
+	};
+};
+
+&stcm0 {
+	/* With only the first 64KB having ECC */
+	reg = <0x0 DT_SIZE_K(108)>;
+};
diff --git a/samples/net/sockets/echo_server/overlay-nsos.conf b/samples/net/sockets/echo_server/overlay-nsos.conf
index eaee3e55615..b6e0ca5a02b 100644
--- a/samples/net/sockets/echo_server/overlay-nsos.conf
+++ b/samples/net/sockets/echo_server/overlay-nsos.conf
@@ -1,4 +1,4 @@
-CONFIG_ETH_NATIVE_POSIX=n
+CONFIG_ETH_NATIVE_TAP=n
 CONFIG_NET_DRIVERS=y
 CONFIG_NET_SOCKETS=y
 CONFIG_NET_SOCKETS_OFFLOAD=y
diff --git a/samples/net/sockets/echo_server/overlay-tunnel.conf b/samples/net/sockets/echo_server/overlay-tunnel.conf
index 54e7ab149bf..4f5a850c08b 100644
--- a/samples/net/sockets/echo_server/overlay-tunnel.conf
+++ b/samples/net/sockets/echo_server/overlay-tunnel.conf
@@ -6,11 +6,11 @@ CONFIG_NET_IF_MAX_IPV6_COUNT=4
 CONFIG_NET_IF_MAX_IPV4_COUNT=4
 
 # First tunneling interface will have these settings
-CONFIG_NET_SAMPLE_TUNNEL_PEER_ADDR="192.0.2.2"
-#CONFIG_NET_SAMPLE_TUNNEL_PEER_ADDR="2001:db8::2"
+CONFIG_NET_SAMPLE_COMMON_TUNNEL_PEER_ADDR="192.0.2.2"
+#CONFIG_NET_SAMPLE_COMMON_TUNNEL_PEER_ADDR="2001:db8::2"
 
 # Use this for IPv6 over IPv4
-CONFIG_NET_SAMPLE_TUNNEL_MY_ADDR="2001:db8:200::1"
+CONFIG_NET_SAMPLE_COMMON_TUNNEL_MY_ADDR="2001:db8:200::1"
 
 # Use this for IPv4 over IPv4
-#CONFIG_NET_SAMPLE_TUNNEL_MY_ADDR="198.51.100.1"
+#CONFIG_NET_SAMPLE_COMMON_TUNNEL_MY_ADDR="198.51.100.1"
diff --git a/samples/net/sockets/echo_server/overlay-vlan.conf b/samples/net/sockets/echo_server/overlay-vlan.conf
index 8467c436e27..21da953356e 100644
--- a/samples/net/sockets/echo_server/overlay-vlan.conf
+++ b/samples/net/sockets/echo_server/overlay-vlan.conf
@@ -16,18 +16,8 @@ CONFIG_NET_CONFIG_PEER_IPV6_ADDR="2001:db8::2"
 CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.0.2.1"
 CONFIG_NET_CONFIG_PEER_IPV4_ADDR="192.0.2.2"
 
-# Second ethernet interface will have these settings
-CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR="2001:db8:100::1"
-# TEST-NET-2 from RFC 5737
-CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR="198.51.100.1"
-CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_NETMASK="255.255.255.0"
-# VLAN tag for the second interface
-CONFIG_NET_SAMPLE_IFACE2_VLAN_TAG=100
+# First VLAN interface will have these settings
+CONFIG_NET_SAMPLE_COMMON_VLAN_SETUP_1="100;2001:db8:100::1/64,198.51.100.1/24"
 
-# Settings for the third network interface
-CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR="2001:db8:200::1"
-# TEST-NET-3 from RFC 5737
-CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR="203.0.113.1"
-CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_NETMASK="255.255.255.0"
-# VLAN tag for the second interface
-CONFIG_NET_SAMPLE_IFACE3_VLAN_TAG=200
+# Second VLAN interface will have these settings
+CONFIG_NET_SAMPLE_COMMON_VLAN_SETUP_2="200;2001:db8:200::1/64,203.0.113.1/24"
diff --git a/samples/net/sockets/echo_server/sample.yaml b/samples/net/sockets/echo_server/sample.yaml
index deaa6247aa4..e3cfd3527d9 100644
--- a/samples/net/sockets/echo_server/sample.yaml
+++ b/samples/net/sockets/echo_server/sample.yaml
@@ -86,38 +86,24 @@ tests:
     platform_exclude:
       - native_sim
       - native_sim/native/64
-      - native_posix
-      - native_posix/native/64
-  sample.net.sockets.echo_server.nrf_openthread:
+  sample.net.sockets.echo_server.openthread:
     extra_args: EXTRA_CONF_FILE="overlay-ot.conf"
     slow: true
     tags:
       - net
       - openthread
-    platform_allow: nrf52840dk/nrf52840
-    filter: CONFIG_FULL_LIBC_SUPPORTED and not CONFIG_NATIVE_LIBC
-  sample.net.sockets.echo_server.b91_openthread:
-    extra_args: EXTRA_CONF_FILE="overlay-ot.conf"
-    slow: true
-    tags:
-      - net
-      - openthread
-    platform_allow: tlsr9518adk80d
-    filter: CONFIG_FULL_LIBC_SUPPORTED and not CONFIG_NATIVE_LIBC
-  sample.net.sockets.echo_server.kw41z_openthread:
-    extra_args: EXTRA_CONF_FILE="overlay-ot.conf"
-    slow: true
-    tags:
-      - net
-      - openthread
-    platform_allow: frdm_kw41z
+    platform_allow:
+      - frdm_kw41z
+      - frdm_mcxw71
+      - nrf52840dk/nrf52840
+      - tlsr9518adk80d
     filter: CONFIG_FULL_LIBC_SUPPORTED and not CONFIG_NATIVE_LIBC
   sample.net.sockets.echo_server.rw612_openthread_rcp_host:
     build_only: true
     extra_args:
       # Disabling monolithic since CI environment doesn't use blobs
       - CONFIG_NXP_MONOLITHIC_NBU=n
-      - OVERLAY_CONFIG="overlay-ot-rcp-host-nxp.conf"
+      - EXTRA_CONF_FILE="overlay-ot-rcp-host-nxp.conf"
     slow: true
     tags:
       - net
@@ -151,11 +137,21 @@ tests:
     integration_platforms:
       - qemu_x86
   sample.net.sockets.echo_server.nsos:
+    harness: console
     platform_allow:
       - native_sim
       - native_sim/native/64
     extra_args:
       - EXTRA_CONF_FILE="overlay-nsos.conf"
+    harness_config:
+      type: multi_line
+      ordered: false
+      regex:
+        - "Network connected"
+        - "Waiting for TCP.*IPv4"
+        - "Waiting for TCP.*IPv6"
+        - "Waiting for UDP.*IPv4"
+        - "Waiting for UDP.*IPv6"
   sample.net.sockets.echo_server.802154.subg:
     extra_args: EXTRA_CONF_FILE="overlay-802154-subg.conf"
     platform_allow: beagleconnect_freedom
diff --git a/samples/net/sockets/echo_server/src/common.h b/samples/net/sockets/echo_server/src/common.h
index d5641fdf5f7..10268c15338 100644
--- a/samples/net/sockets/echo_server/src/common.h
+++ b/samples/net/sockets/echo_server/src/common.h
@@ -5,6 +5,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "net_sample_common.h"
 
 #define MY_PORT 4242
 #if defined(CONFIG_NET_SOCKETS_SOCKOPT_TLS) || defined(CONFIG_NET_TCP) || \
@@ -73,15 +74,6 @@ void stop_tcp(void);
 
 void quit(void);
 
-#if defined(CONFIG_NET_VLAN)
-int init_vlan(void);
-#else
-static inline int init_vlan(void)
-{
-	return 0;
-}
-#endif /* CONFIG_NET_VLAN */
-
 #if defined(CONFIG_NET_SAMPLE_WEBSOCKET_CONSOLE)
 int init_ws(void);
 #else
@@ -91,22 +83,6 @@ static inline int init_ws(void)
 }
 #endif /* CONFIG_NET_SAMPLE_WEBSOCKET_CONSOLE */
 
-#if defined(CONFIG_NET_L2_IPIP)
-int init_tunnel(void);
-bool is_tunnel(struct net_if *iface);
-#else
-static inline int init_tunnel(void)
-{
-	return 0;
-}
-
-static inline bool is_tunnel(struct net_if *iface)
-{
-	ARG_UNUSED(iface);
-	return false;
-}
-#endif /* CONFIG_NET_L2_IPIP */
-
 #if defined(CONFIG_USB_DEVICE_STACK) || defined(CONFIG_USB_DEVICE_STACK_NEXT)
 int init_usb(void);
 #else
diff --git a/samples/net/sockets/echo_server/src/vlan.c b/samples/net/sockets/echo_server/src/vlan.c
deleted file mode 100644
index b9a28d222c4..00000000000
--- a/samples/net/sockets/echo_server/src/vlan.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * Copyright (c) 2018 Intel Corporation.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/logging/log.h>
-LOG_MODULE_DECLARE(net_echo_server_sample, LOG_LEVEL_DBG);
-
-#include <zephyr/kernel.h>
-
-#include <zephyr/net/ethernet.h>
-
-/* User data for the interface callback */
-struct ud {
-	struct net_if *first;
-	struct net_if *second;
-	struct net_if *eth;
-};
-
-static void iface_cb(struct net_if *iface, void *user_data)
-{
-	struct ud *ud = user_data;
-
-	if (net_if_l2(iface) == &NET_L2_GET_NAME(ETHERNET) && ud->eth == NULL) {
-		ud->eth = iface;
-		return;
-	}
-
-	if (net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL)) {
-		return;
-	}
-
-	if (!ud->first) {
-		ud->first = iface;
-		return;
-	}
-
-	if (!ud->second) {
-		ud->second = iface;
-		return;
-	}
-}
-
-static int setup_iface(struct net_if *iface, struct net_if *vlan,
-		       const char *ipv6_addr, const char *ipv4_addr,
-		       const char *netmask, uint16_t vlan_tag)
-{
-	struct net_if_addr *ifaddr;
-	struct in_addr addr4;
-	struct in6_addr addr6;
-	int ret;
-
-	ret = net_eth_vlan_enable(iface, vlan_tag);
-	if (ret < 0) {
-		LOG_ERR("Cannot enable VLAN for tag %d (%d)", vlan_tag, ret);
-	}
-
-	if (IS_ENABLED(CONFIG_NET_IPV6)) {
-		if (net_addr_pton(AF_INET6, ipv6_addr, &addr6)) {
-			LOG_ERR("Invalid address: %s", ipv6_addr);
-			return -EINVAL;
-		}
-
-		ifaddr = net_if_ipv6_addr_add(vlan, &addr6,
-					      NET_ADDR_MANUAL, 0);
-		if (!ifaddr) {
-			LOG_ERR("Cannot add %s to interface %p",
-				ipv6_addr, vlan);
-			return -EINVAL;
-		}
-	}
-
-	if (IS_ENABLED(CONFIG_NET_IPV4)) {
-		if (net_addr_pton(AF_INET, ipv4_addr, &addr4)) {
-			LOG_ERR("Invalid address: %s", ipv4_addr);
-			return -EINVAL;
-		}
-
-		ifaddr = net_if_ipv4_addr_add(vlan, &addr4,
-					      NET_ADDR_MANUAL, 0);
-		if (!ifaddr) {
-			LOG_ERR("Cannot add %s to interface %p",
-				ipv4_addr, vlan);
-			return -EINVAL;
-		}
-
-		if (netmask && netmask[0]) {
-			struct in_addr nm;
-
-			if (net_addr_pton(AF_INET, netmask, &nm)) {
-				LOG_ERR("Invalid netmask: %s", ipv4_addr);
-				return -EINVAL;
-			}
-
-			net_if_ipv4_set_netmask_by_addr(vlan, &addr4, &nm);
-		}
-	}
-
-	LOG_DBG("Interface %p VLAN tag %d setup done.", vlan, vlan_tag);
-
-	return 0;
-}
-
-int init_vlan(void)
-{
-	struct ud ud;
-	int ret;
-
-	memset(&ud, 0, sizeof(ud));
-
-	net_if_foreach(iface_cb, &ud);
-
-	/* This sample has two VLANs. For the second one we need to manually
-	 * create IP address for this test. But first the VLAN needs to be
-	 * added to the interface so that IPv6 DAD can work properly.
-	 */
-	ret = setup_iface(ud.eth, ud.first,
-			  CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_NETMASK,
-			  CONFIG_NET_SAMPLE_IFACE2_VLAN_TAG);
-	if (ret < 0) {
-		return ret;
-	}
-
-	ret = setup_iface(ud.eth, ud.second,
-			  CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_NETMASK,
-			  CONFIG_NET_SAMPLE_IFACE3_VLAN_TAG);
-	if (ret < 0) {
-		return ret;
-	}
-
-	return 0;
-}
diff --git a/samples/net/sockets/echo_server/src/ws_console/index.html b/samples/net/sockets/echo_server/src/ws_console/index.html
index add412e3b4c..a5381947bf1 100644
--- a/samples/net/sockets/echo_server/src/ws_console/index.html
+++ b/samples/net/sockets/echo_server/src/ws_console/index.html
@@ -16,8 +16,8 @@
 	ws.onopen = function() {
 		output("Connection opened");
 		connected = "true";
-		// No need to print Escape codes for colors
-		ws.send("shell colors off\n");
+		// No need to print escape codes
+		ws.send("shell colors off\nshell vt100 off\n");
 	};
 
 	ws.onmessage = function(e) {
diff --git a/samples/net/sockets/echo_service/README.rst b/samples/net/sockets/echo_service/README.rst
index 3e1d7625d70..abb791b07b0 100644
--- a/samples/net/sockets/echo_service/README.rst
+++ b/samples/net/sockets/echo_service/README.rst
@@ -7,8 +7,8 @@
 Overview
 ********
 
-The sockets/echo_service sample application for Zephyr implements a TCP echo
-server supporting both IPv4 and IPv6 and using a BSD Sockets compatible API.
+The sockets/echo_service sample application for Zephyr implements a TCP and UDP
+echo server supporting both IPv4 and IPv6 and using a BSD Sockets compatible API.
 
 The purpose of this sample is to show how to use socket service API.
 The socket service is a concept where many blocking sockets can be listened by
diff --git a/samples/net/sockets/echo_service/sample.yaml b/samples/net/sockets/echo_service/sample.yaml
index 5feb3cc826c..40ea95ed332 100644
--- a/samples/net/sockets/echo_service/sample.yaml
+++ b/samples/net/sockets/echo_service/sample.yaml
@@ -5,10 +5,6 @@ common:
   harness: net
   depends_on: netif
   filter: CONFIG_FULL_LIBC_SUPPORTED and not CONFIG_NATIVE_LIBC
-  # eventfd does not work properly with native_posix so exclude it here
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   sample.net.sockets.service.echo:
     tags:
diff --git a/samples/net/sockets/echo_service/src/main.c b/samples/net/sockets/echo_service/src/main.c
index d1728049f21..0db44ad30c5 100644
--- a/samples/net/sockets/echo_service/src/main.c
+++ b/samples/net/sockets/echo_service/src/main.c
@@ -38,11 +38,6 @@ static void tcp_service_handler(struct net_socket_service_event *pev)
 {
 	static char buf[1500];
 
-	/* Note that in this application we receive / send data from
-	 * system work queue. In proper application the socket reading and data
-	 * sending should be done so that the system work queue is not blocked.
-	 * It is possible to create a socket service that uses own work queue.
-	 */
 	receive_data(false, pev, buf, sizeof(buf));
 }
 
diff --git a/samples/net/sockets/http_client/docker-test.sh b/samples/net/sockets/http_client/docker-test.sh
index 5f9468112d4..f9022aa4415 100644
--- a/samples/net/sockets/http_client/docker-test.sh
+++ b/samples/net/sockets/http_client/docker-test.sh
@@ -28,7 +28,7 @@ echo "HTTPS client test"
 if [ -n "$zephyr_overlay" ]; then
 	overlay="${zephyr_overlay};overlay-tls.conf"
 else
-	overlay="-DOVERLAY_CONFIG=overlay-tls.conf"
+	overlay="-DEXTRA_CONF_FILE=overlay-tls.conf"
 fi
 
 start_configuration "--ip=192.0.2.2 --ip6=2001:db8::2" || return $?
diff --git a/samples/net/sockets/http_client/sample.yaml b/samples/net/sockets/http_client/sample.yaml
index afd14a1a255..271f61b94ec 100644
--- a/samples/net/sockets/http_client/sample.yaml
+++ b/samples/net/sockets/http_client/sample.yaml
@@ -5,10 +5,6 @@ common:
     - http_client
   min_ram: 32
   depends_on: netif
-  # native_posix does not work with CONFIG_POSIX_API
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 sample:
   description: HTTP client sample
   name: http_client
diff --git a/samples/net/sockets/http_get/Kconfig b/samples/net/sockets/http_get/Kconfig
new file mode 100644
index 00000000000..1fd79445866
--- /dev/null
+++ b/samples/net/sockets/http_get/Kconfig
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2025 Ezurio
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+source "samples/net/common/Kconfig"
+source "Kconfig.zephyr"
diff --git a/samples/net/sockets/http_get/overlay-hl7800.conf b/samples/net/sockets/http_get/overlay-hl7800.conf
new file mode 100644
index 00000000000..d941052c89f
--- /dev/null
+++ b/samples/net/sockets/http_get/overlay-hl7800.conf
@@ -0,0 +1,15 @@
+# The HL7800 driver gets its IP settings from the cell network
+CONFIG_DNS_SERVER_IP_ADDRESSES=n
+CONFIG_NET_CONFIG_SETTINGS=n
+# Wait for the network to be ready
+CONFIG_NET_CONNECTION_MANAGER=y
+CONFIG_NET_SAMPLE_COMMON_WAIT_DNS_SERVER_ADDITION=y
+# NB-IoT has large latency, so increase timeouts. It is ok to use this for Cat-M1 as well.
+CONFIG_NET_SOCKETS_DNS_TIMEOUT=12000
+CONFIG_NET_SOCKETS_CONNECT_TIMEOUT=15000
+
+# CONFIG_MODEM_LOG_LEVEL_DBG=y
+# CONFIG_LOG_PROCESS_THREAD_SLEEP_MS=1
+# CONFIG_LOG_BUFFER_SIZE=20000
+# CONFIG_MODEM_HL7800_SET_APN_NAME_ON_STARTUP=y
+# CONFIG_MODEM_HL7800_APN_NAME="VZWINTERNET"
diff --git a/samples/net/sockets/http_get/overlay-nsos.conf b/samples/net/sockets/http_get/overlay-nsos.conf
index 0af19c1b112..dfe7324e0f9 100644
--- a/samples/net/sockets/http_get/overlay-nsos.conf
+++ b/samples/net/sockets/http_get/overlay-nsos.conf
@@ -1,4 +1,4 @@
-CONFIG_ETH_NATIVE_POSIX=n
+CONFIG_ETH_NATIVE_TAP=n
 CONFIG_NET_DRIVERS=y
 CONFIG_NET_SOCKETS=y
 CONFIG_NET_SOCKETS_OFFLOAD=y
diff --git a/samples/net/sockets/http_get/overlay-tls.conf b/samples/net/sockets/http_get/overlay-tls.conf
index 0cf82f18cf8..70da5798663 100644
--- a/samples/net/sockets/http_get/overlay-tls.conf
+++ b/samples/net/sockets/http_get/overlay-tls.conf
@@ -10,3 +10,7 @@ CONFIG_MBEDTLS_HASH_ALL_ENABLED=y
 CONFIG_MBEDTLS_CMAC=y
 
 CONFIG_NET_SOCKETS_SOCKOPT_TLS=y
+
+# Debugging options
+#CONFIG_MBEDTLS_DEBUG=y
+#CONFIG_MBEDTLS_LOG_LEVEL_DBG=y
diff --git a/samples/net/sockets/http_get/sample.yaml b/samples/net/sockets/http_get/sample.yaml
index d30583f7a84..d6e385c49e9 100644
--- a/samples/net/sockets/http_get/sample.yaml
+++ b/samples/net/sockets/http_get/sample.yaml
@@ -9,9 +9,6 @@ common:
   tags:
     - net
     - socket
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   sample.net.sockets.http_get:
     filter: not CONFIG_NET_SOCKETS_OFFLOAD and not CONFIG_NATIVE_LIBC
diff --git a/samples/net/sockets/http_get/src/http_get.c b/samples/net/sockets/http_get/src/http_get.c
index b4ad0ff8410..81b268fe533 100644
--- a/samples/net/sockets/http_get/src/http_get.c
+++ b/samples/net/sockets/http_get/src/http_get.c
@@ -40,11 +40,10 @@
 /* HTTP path to request */
 #define HTTP_PATH "/"
 
-
 #define SSTRLEN(s) (sizeof(s) - 1)
-#define CHECK(r) { if (r == -1) { printf("Error: " #r "\n"); exit(1); } }
+#define CHECK(r) { if (r < 0) { printf("Error: %d\n", (int)r); exit(1); } }
 
-#define REQUEST "GET " HTTP_PATH " HTTP/1.0\r\nHost: " HTTP_HOST "\r\n\r\n"
+#define REQUEST "GET " HTTP_PATH " HTTP/1.1\r\nHost: " HTTP_HOST "\r\n\r\n"
 
 static char response[1024];
 
@@ -52,9 +51,8 @@ void dump_addrinfo(const struct addrinfo *ai)
 {
 	printf("addrinfo @%p: ai_family=%d, ai_socktype=%d, ai_protocol=%d, "
 	       "sa_family=%d, sin_port=%x\n",
-	       ai, ai->ai_family, ai->ai_socktype, ai->ai_protocol,
-	       ai->ai_addr->sa_family,
-	       ((struct sockaddr_in *)ai->ai_addr)->sin_port);
+	       ai, ai->ai_family, ai->ai_socktype, ai->ai_protocol, ai->ai_addr->sa_family,
+	       ntohs(((struct sockaddr_in *)ai->ai_addr)->sin_port));
 }
 
 int main(void)
@@ -110,7 +108,9 @@ int main(void)
 			 HTTP_HOST, sizeof(HTTP_HOST)))
 #endif
 
+	printf("Connecting to server...\n");
 	CHECK(connect(sock, res->ai_addr, res->ai_addrlen));
+	printf("Connected!\r\nSending request...\n");
 	CHECK(send(sock, REQUEST, SSTRLEN(REQUEST), 0));
 
 	printf("Response:\n\n");
@@ -131,7 +131,7 @@ int main(void)
 		printf("%s", response);
 	}
 
-	printf("\n");
+	printf("\nClose socket\n");
 
 	(void)close(sock);
 	return 0;
diff --git a/samples/net/sockets/http_server/Kconfig b/samples/net/sockets/http_server/Kconfig
index 861178a09d2..1accd285941 100644
--- a/samples/net/sockets/http_server/Kconfig
+++ b/samples/net/sockets/http_server/Kconfig
@@ -17,6 +17,7 @@ config NET_SAMPLE_HTTP_SERVER_SERVICE_PORT
 config NET_SAMPLE_HTTPS_SERVICE
 	bool "Enable https service"
 	depends on NET_SOCKETS_SOCKOPT_TLS || TLS_CREDENTIALS
+	imply MBEDTLS_PSA_CRYPTO_C if !BUILD_WITH_TFM
 
 if NET_SAMPLE_HTTPS_SERVICE
 
diff --git a/samples/net/sockets/http_server/README.rst b/samples/net/sockets/http_server/README.rst
index 9d33cb2e26a..c058971537b 100644
--- a/samples/net/sockets/http_server/README.rst
+++ b/samples/net/sockets/http_server/README.rst
@@ -34,12 +34,24 @@ There are configuration files for various setups in the
     * - :zephyr_file:`overlay-netusb.conf <samples/net/sockets/http_server/overlay-netusb.conf>`
       - This overlay config can be added for connecting via network USB.
 
-To build and run the application:
+    * - :zephyr_file:`overlay-tls.conf <samples/net/sockets/http_server/overlay-tls.conf>`
+      - This overlay config can be added to build the HTTPS variant.
+
+    * - :zephyr_file:`overlay-dhcpv4.conf <samples/net/sockets/http_server/overlay-dhcpv4.conf>`
+      - This overlay enables DHCPv4 client feature.
+
+To build and run the HTTP server application:
 
 .. code-block:: bash
 
    $ west build -p auto -b <board_to_use> -t run samples/net/sockets/http_server
 
+For the HTTPS version:
+
+.. code-block:: bash
+
+   $ west build -p auto -b <board_to_use> -t run --test samples/net/sockets/http_server/sample.net.sockets.https.server
+
 When the server is up, we can make requests to the server using either HTTP/1.1 or
 HTTP/2 protocol from the host machine.
 
@@ -56,9 +68,10 @@ HTTP/2 protocol from the host machine.
 - Using h2load: ``h2load -n10 http://192.0.2.1/``
 
 Web browsers use stricter security settings for the HTTP/2 protocol. So to use HTTP/2
-with a web browser, you must enable ``CONFIG_NET_SAMPLE_HTTPS_SERVICE`` and
-``CONFIG_NET_SAMPLE_HTTPS_USE_ALPN``. Additionally the server certificate must be signed
-by a CA certificate trusted by your browser.
+with a web browser, you must ALPN (add ``-DCONFIG_NET_SAMPLE_HTTPS_USE_ALPN`` to
+the west build command) on top of the HTTPS build shown above.
+Additionally the server certificate must be signed by a CA certificate trusted
+by your browser.
 
 The best way to do this is to generate your own CA certificate:
 
@@ -137,6 +150,61 @@ connectivity.
    ws.close()
 
 
+Testing over USB
+----------------
+
+Let's see a real example on how the HTTP(S) server can be tested on a real device
+using an USB connection toward a Linux host PC. For this purpose let's take an
+NRF52840 board as example.
+
+First of all build the sample enabling HTTPS service and flash the board:
+
+.. zephyr-app-commands::
+         :zephyr-app: samples/net/sockets/http_server/
+         :board: nrf52840dk/nrf52840
+         :goals: build
+         :gen-args: -DCONFIG_NET_SAMPLE_HTTPS_SERVICE=y -DEXTRA_CONF_FILE=overlay-netusb.conf
+
+Then connect the USB cable to the host PC and issue:
+
+.. code-block:: bash
+
+   $ ip link show
+
+to get the device name Linux assigned to the USB-Ethernet interface. For the
+following let's assume that the name is ``eth-device``.
+
+Now we need to configure IP and routing for this interface:
+
+.. code-block:: bash
+
+   $ sudo ip addr add 192.0.2.2/24 dev eth-device
+   $ sudo ip route add 192.0.2.0/24 dev eth-device
+
+Here:
+
+* we picked an IP address for the interface, i.e. ``192.0.2.2/24``, which is
+  different form the server one, i.e. :kconfig:option:`CONFIG_NET_CONFIG_MY_IPV4_ADDR`,
+  but in the allowed IP range defined by the ``/24`` mask.
+* we assume that 192.168.0.x range do not conflict with other addresses and
+  routes in the host system. If that's the case, then all IP addresses should
+  be fixed (sample, host IP interface, certificate).
+
+Once this is done, it should be possible to test either HTTP and HTTPS with
+``curl``:
+
+.. code-block:: bash
+
+   $ curl -v --compressed http://192.0.2.1
+   $ curl -v --compressed https://192.0.2.1
+
+.. note::
+
+   To have a successful HTTPS connection ensure to update the CA certificates
+   of the host Linux system adding
+   :zephyr_file:`samples/net/sockets/http_server/src/certs/ca_cert.pem` to the
+   list of known CAs.
+
 Performance Analysis
 --------------------
 
diff --git a/samples/net/sockets/http_server/overlay-dhcpv4.conf b/samples/net/sockets/http_server/overlay-dhcpv4.conf
new file mode 100644
index 00000000000..95842b1da55
--- /dev/null
+++ b/samples/net/sockets/http_server/overlay-dhcpv4.conf
@@ -0,0 +1,2 @@
+CONFIG_NET_DHCPV4=y
+CONFIG_ZVFS_EVENTFD_MAX=2
diff --git a/samples/net/sockets/http_server/overlay-tls.conf b/samples/net/sockets/http_server/overlay-tls.conf
new file mode 100644
index 00000000000..b35ab7fcf27
--- /dev/null
+++ b/samples/net/sockets/http_server/overlay-tls.conf
@@ -0,0 +1,26 @@
+CONFIG_NET_SAMPLE_HTTPS_SERVICE=y
+
+# TLS configuration
+CONFIG_MBEDTLS=y
+CONFIG_MBEDTLS_BUILTIN=y
+CONFIG_MBEDTLS_ENABLE_HEAP=y
+CONFIG_MBEDTLS_HEAP_SIZE=60000
+CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=2048
+CONFIG_NET_SOCKETS_SOCKOPT_TLS=y
+CONFIG_NET_SOCKETS_TLS_MAX_CONTEXTS=6
+CONFIG_TLS_CREDENTIALS=y
+CONFIG_TLS_MAX_CREDENTIALS_NUMBER=5
+CONFIG_PSA_WANT_ALG_ECDH=y
+CONFIG_PSA_WANT_ALG_ECDSA=y
+CONFIG_PSA_WANT_ECC_SECP_R1_256=y
+CONFIG_PSA_WANT_KEY_TYPE_ECC_PUBLIC_KEY=y
+CONFIG_PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_IMPORT=y
+CONFIG_PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_EXPORT=y
+CONFIG_PSA_WANT_KEY_TYPE_ECC_KEY_PAIR_GENERATE=y
+CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED=y
+CONFIG_PSA_WANT_ALG_CCM=y
+CONFIG_PSA_WANT_ALG_GCM=y
+CONFIG_MBEDTLS_PK_WRITE_C=y
+CONFIG_PSA_WANT_ALG_TLS12_PRF=y
+CONFIG_PSA_WANT_ALG_SHA_1=y
+CONFIG_PSA_WANT_ALG_SHA_256=y
diff --git a/samples/net/sockets/http_server/prj.conf b/samples/net/sockets/http_server/prj.conf
index 73024d1aca1..5cfe2a04ad2 100644
--- a/samples/net/sockets/http_server/prj.conf
+++ b/samples/net/sockets/http_server/prj.conf
@@ -58,26 +58,6 @@ CONFIG_NET_CONFIG_MY_IPV4_GW="192.0.2.2"
 CONFIG_NET_CONFIG_MY_IPV6_ADDR="2001:db8::1"
 CONFIG_NET_CONFIG_PEER_IPV6_ADDR="2001:db8::2"
 
-# TLS configuration
-CONFIG_MBEDTLS=y
-CONFIG_MBEDTLS_BUILTIN=y
-CONFIG_MBEDTLS_ENABLE_HEAP=y
-CONFIG_MBEDTLS_HEAP_SIZE=60000
-CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=2048
-CONFIG_MBEDTLS_USE_PSA_CRYPTO=n
-CONFIG_NET_SOCKETS_SOCKOPT_TLS=y
-CONFIG_NET_SOCKETS_TLS_MAX_CONTEXTS=6
-CONFIG_TLS_CREDENTIALS=y
-CONFIG_TLS_MAX_CREDENTIALS_NUMBER=5
-CONFIG_MBEDTLS_ECDH_C=y
-CONFIG_MBEDTLS_ECDSA_C=y
-CONFIG_MBEDTLS_ECP_C=y
-CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y
-CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_ENABLED=n
-CONFIG_MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED=y
-CONFIG_MBEDTLS_CIPHER_CCM_ENABLED=y
-CONFIG_MBEDTLS_CIPHER_GCM_ENABLED=y
-
 # Networking tweaks
 # Required to handle large number of consecutive connections,
 # e.g. when testing with ApacheBench.
diff --git a/samples/net/sockets/http_server/sample.yaml b/samples/net/sockets/http_server/sample.yaml
index 38206644533..bce7a11e4b8 100644
--- a/samples/net/sockets/http_server/sample.yaml
+++ b/samples/net/sockets/http_server/sample.yaml
@@ -11,8 +11,8 @@ common:
     - server
     - socket
   platform_exclude:
-    - native_posix
-    - native_posix/native/64
     - nrf5340dk/nrf5340/cpuapp/ns # Excluding due to ROM overflow.
 tests:
   sample.net.sockets.http.server: {}
+  sample.net.sockets.https.server:
+    extra_args: EXTRA_CONF_FILE="overlay-tls.conf"
diff --git a/samples/net/sockets/http_server/src/certs/ca.der b/samples/net/sockets/http_server/src/certs/ca.der
deleted file mode 100644
index b1d3e097cad..00000000000
Binary files a/samples/net/sockets/http_server/src/certs/ca.der and /dev/null differ
diff --git a/samples/net/sockets/http_server/src/main.c b/samples/net/sockets/http_server/src/main.c
index 4cfe06ff97c..4615d0dcb24 100644
--- a/samples/net/sockets/http_server/src/main.c
+++ b/samples/net/sockets/http_server/src/main.c
@@ -247,8 +247,8 @@ struct http_resource_detail_websocket ws_netstats_resource_detail = {
 
 #if defined(CONFIG_NET_SAMPLE_HTTP_SERVICE)
 static uint16_t test_http_service_port = CONFIG_NET_SAMPLE_HTTP_SERVER_SERVICE_PORT;
-HTTP_SERVICE_DEFINE(test_http_service, NULL, &test_http_service_port, 1,
-		    10, NULL);
+HTTP_SERVICE_DEFINE(test_http_service, NULL, &test_http_service_port,
+		    CONFIG_HTTP_SERVER_MAX_CLIENTS, 10, NULL, NULL);
 
 HTTP_RESOURCE_DEFINE(index_html_gz_resource, test_http_service, "/",
 		     &index_html_gz_resource_detail);
@@ -280,9 +280,9 @@ static const sec_tag_t sec_tag_list_verify_none[] = {
 	};
 
 static uint16_t test_https_service_port = CONFIG_NET_SAMPLE_HTTPS_SERVER_SERVICE_PORT;
-HTTPS_SERVICE_DEFINE(test_https_service, NULL,
-		     &test_https_service_port, 1, 10, NULL,
-		     sec_tag_list_verify_none, sizeof(sec_tag_list_verify_none));
+HTTPS_SERVICE_DEFINE(test_https_service, NULL, &test_https_service_port,
+		     CONFIG_HTTP_SERVER_MAX_CLIENTS, 10, NULL, NULL, sec_tag_list_verify_none,
+		     sizeof(sec_tag_list_verify_none));
 
 HTTP_RESOURCE_DEFINE(index_html_gz_resource_https, test_https_service, "/",
 		     &index_html_gz_resource_detail);
diff --git a/samples/net/sockets/http_server/src/ws.c b/samples/net/sockets/http_server/src/ws.c
index 7215aeefb62..1338e437419 100644
--- a/samples/net/sockets/http_server/src/ws.c
+++ b/samples/net/sockets/http_server/src/ws.c
@@ -295,7 +295,7 @@ int ws_netstats_init(void)
 }
 SYS_INIT(ws_netstats_init, APPLICATION, 0);
 
-int ws_echo_setup(int ws_socket, void *user_data)
+int ws_echo_setup(int ws_socket, struct http_request_ctx *request_ctx, void *user_data)
 {
 	int slot;
 
@@ -331,7 +331,7 @@ int ws_echo_setup(int ws_socket, void *user_data)
 	return 0;
 }
 
-int ws_netstats_setup(int ws_socket, void *user_data)
+int ws_netstats_setup(int ws_socket, struct http_request_ctx *request_ctx, void *user_data)
 {
 	int ret;
 	int slot;
diff --git a/samples/net/sockets/http_server/src/ws.h b/samples/net/sockets/http_server/src/ws.h
index 85ba61bbe16..0afdd6287f0 100644
--- a/samples/net/sockets/http_server/src/ws.h
+++ b/samples/net/sockets/http_server/src/ws.h
@@ -4,22 +4,26 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <zephyr/net/http/server.h>
+
 /**
  * @brief Setup websocket for echoing data back to client
  *
  * @param ws_socket Socket file descriptor associated with websocket
+ * @param request_ctx Request context associated with websocket HTTP upgrade request
  * @param user_data User data pointer
  *
  * @return 0 on success
  */
-int ws_echo_setup(int ws_socket, void *user_data);
+int ws_echo_setup(int ws_socket, struct http_request_ctx *request_ctx, void *user_data);
 
 /**
  * @brief Setup websocket for sending net statistics to client
  *
  * @param ws_socket Socket file descriptor associated with websocket
+ * @param request_ctx Request context associated with websocket HTTP upgrade request
  * @param user_data User data pointer
  *
  * @return 0 on success
  */
-int ws_netstats_setup(int ws_socket, void *user_data);
+int ws_netstats_setup(int ws_socket, struct http_request_ctx *request_ctx, void *user_data);
diff --git a/samples/net/sockets/net_mgmt/sample.yaml b/samples/net/sockets/net_mgmt/sample.yaml
index e2d7a0e0ed9..ee966ef9491 100644
--- a/samples/net/sockets/net_mgmt/sample.yaml
+++ b/samples/net/sockets/net_mgmt/sample.yaml
@@ -6,9 +6,6 @@ common:
     - net
     - socket
     - mgmt
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 sample:
   description: Test network management socket sample
   name: net_mgmt socket
diff --git a/samples/net/sockets/sntp_client/Kconfig b/samples/net/sockets/sntp_client/Kconfig
new file mode 100644
index 00000000000..8841fa1fc74
--- /dev/null
+++ b/samples/net/sockets/sntp_client/Kconfig
@@ -0,0 +1,15 @@
+# Copyright (c) 2024 Embeint Inc
+
+config NET_SAMPLE_SNTP_SERVER_ADDRESS
+	string "SNTP server address"
+	default "pool.ntp.org"
+
+config NET_SAMPLE_SNTP_SERVER_PORT
+	int "SNTP server port"
+	default 123
+
+config NET_SAMPLE_SNTP_SERVER_TIMEOUT_MS
+	int "Duration to wait for response"
+	default 2000
+
+source "Kconfig.zephyr"
diff --git a/samples/net/sockets/sntp_client/overlay-nsos.conf b/samples/net/sockets/sntp_client/overlay-nsos.conf
new file mode 100644
index 00000000000..dec4079422e
--- /dev/null
+++ b/samples/net/sockets/sntp_client/overlay-nsos.conf
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Embeint Inc
+
+CONFIG_ETH_NATIVE_TAP=n
+CONFIG_NET_DRIVERS=y
+CONFIG_NET_SOCKETS=y
+CONFIG_NET_SOCKETS_OFFLOAD=y
+CONFIG_NET_NATIVE_OFFLOADED_SOCKETS=y
+CONFIG_HEAP_MEM_POOL_SIZE=4096
+
+# IPv6 DAD requires lower level network interface access, below exposed socket-level access
+CONFIG_NET_IPV6_DAD=n
diff --git a/samples/net/sockets/sntp_client/prj.conf b/samples/net/sockets/sntp_client/prj.conf
index 12798c12cf3..4b94923895b 100644
--- a/samples/net/sockets/sntp_client/prj.conf
+++ b/samples/net/sockets/sntp_client/prj.conf
@@ -11,6 +11,7 @@ CONFIG_NET_SHELL=y
 
 # Sockets
 CONFIG_NET_SOCKETS=y
+CONFIG_NET_SOCKETS_SERVICE=y
 CONFIG_ZVFS_POLL_MAX=4
 
 # Network driver config
@@ -21,12 +22,7 @@ CONFIG_NET_CONFIG_SETTINGS=y
 CONFIG_NET_CONFIG_NEED_IPV4=y
 CONFIG_NET_CONFIG_NEED_IPV6=y
 CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.0.2.1"
-CONFIG_NET_CONFIG_MY_IPV4_GW="192.0.2.2"
-# Address of SNTP IPv4 server
-CONFIG_NET_CONFIG_PEER_IPV4_ADDR="192.0.2.2"
 CONFIG_NET_CONFIG_MY_IPV6_ADDR="2001:db8::1"
-# Address of SNTP IPv6 server
-CONFIG_NET_CONFIG_PEER_IPV6_ADDR="2001:db8::2"
 
 # SNTP
 CONFIG_SNTP=y
diff --git a/samples/net/sockets/sntp_client/sample.yaml b/samples/net/sockets/sntp_client/sample.yaml
index 81d5fc6e95b..e4cf1ac9965 100644
--- a/samples/net/sockets/sntp_client/sample.yaml
+++ b/samples/net/sockets/sntp_client/sample.yaml
@@ -9,6 +9,15 @@ tests:
     platform_allow:
       - qemu_x86
       - native_sim
+  sample.net.sockets.sntp_client.native:
+    platform_allow:
+      - native_sim
+    integration_platforms:
+      - native_sim
+    extra_configs:
+      - CONFIG_NATIVE_SIM_SLOWDOWN_TO_REAL_TIME=y
+    extra_args:
+      - EXTRA_CONF_FILE="overlay-nsos.conf"
   sample.net.sockets.sntp_client.wifi.nrf70dk:
     extra_args:
       - SNIPPET=wifi-ipv4
diff --git a/samples/net/sockets/sntp_client/src/config.h b/samples/net/sockets/sntp_client/src/config.h
deleted file mode 100644
index 38ceb54eeaa..00000000000
--- a/samples/net/sockets/sntp_client/src/config.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2019 Linaro Limited
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef __CONFIG_H__
-#define __CONFIG_H__
-
-#ifdef CONFIG_NET_CONFIG_SETTINGS
-#ifdef CONFIG_NET_IPV6
-#define SERVER_ADDR6		CONFIG_NET_CONFIG_PEER_IPV6_ADDR
-#endif
-#define SERVER_ADDR		CONFIG_NET_CONFIG_PEER_IPV4_ADDR
-#else
-#ifdef CONFIG_NET_IPV6
-#define SERVER_ADDR6		"2001:db8::2"
-#endif
-#define SERVER_ADDR		"192.0.2.2"
-#endif
-
-#endif
diff --git a/samples/net/sockets/sntp_client/src/main.c b/samples/net/sockets/sntp_client/src/main.c
index 66cf8a759e8..3725f46d91a 100644
--- a/samples/net/sockets/sntp_client/src/main.c
+++ b/samples/net/sockets/sntp_client/src/main.c
@@ -8,80 +8,134 @@
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(net_sntp_client_sample, LOG_LEVEL_DBG);
 
+#include <zephyr/net/socket.h>
+#include <zephyr/net/socket_service.h>
 #include <zephyr/net/sntp.h>
 #include <arpa/inet.h>
 
-#include "config.h"
 #include "net_sample_common.h"
 
-#define SNTP_PORT 123
+static K_SEM_DEFINE(sntp_async_received, 0, 1);
+static void sntp_service_handler(struct net_socket_service_event *pev);
 
-int main(void)
+NET_SOCKET_SERVICE_SYNC_DEFINE_STATIC(service_sntp_async, sntp_service_handler, 1);
+
+int dns_query(const char *host, uint16_t port, int family, int socktype, struct sockaddr *addr,
+			  socklen_t *addrlen)
 {
-	struct sntp_ctx ctx;
-	struct sockaddr_in addr;
-#if defined(CONFIG_NET_IPV6)
-	struct sockaddr_in6 addr6;
-#endif
-	struct sntp_time sntp_time;
+	struct addrinfo hints = {
+		.ai_family = family,
+		.ai_socktype = socktype,
+	};
+	struct addrinfo *res = NULL;
+	char addr_str[INET6_ADDRSTRLEN] = {0};
 	int rv;
 
-	wait_for_network();
+	/* Perform DNS query */
+	rv = getaddrinfo(host, NULL, &hints, &res);
+	if (rv < 0) {
+		LOG_ERR("getaddrinfo failed (%d, errno %d)", rv, errno);
+		return rv;
+	}
+	/* Store the first result */
+	*addr = *res->ai_addr;
+	*addrlen = res->ai_addrlen;
+	/* Free the allocated memory */
+	freeaddrinfo(res);
+	/* Store the port */
+	net_sin(addr)->sin_port = htons(port);
+	/* Print the found address */
+	inet_ntop(addr->sa_family, &net_sin(addr)->sin_addr, addr_str, sizeof(addr_str));
+	LOG_INF("%s -> %s", host, addr_str);
+	return 0;
+}
 
-	/* ipv4 */
-	memset(&addr, 0, sizeof(addr));
-	addr.sin_family = AF_INET;
-	addr.sin_port = htons(SNTP_PORT);
-	inet_pton(AF_INET, SERVER_ADDR, &addr.sin_addr);
+static void sntp_service_handler(struct net_socket_service_event *pev)
+{
+	struct sntp_time s_time;
+	int rc;
+
+	/* Read the response from the socket */
+	rc = sntp_read_async(pev, &s_time);
+	if (rc != 0) {
+		LOG_ERR("Failed to read SNTP response (%d)", rc);
+		return;
+	}
+
+	/* Close the service */
+	sntp_close_async(&service_sntp_async);
 
-	rv = sntp_init(&ctx, (struct sockaddr *) &addr,
-		       sizeof(struct sockaddr_in));
+	LOG_INF("SNTP Time: %llu (async)", s_time.seconds);
+
+	/* Notify test thread */
+	k_sem_give(&sntp_async_received);
+}
+
+static void do_sntp(int family)
+{
+	char *family_str = family == AF_INET ? "IPv4" : "IPv6";
+	struct sntp_time s_time;
+	struct sntp_ctx ctx;
+	struct sockaddr addr;
+	socklen_t addrlen;
+	int rv;
+
+	/* Get SNTP server */
+	rv = dns_query(CONFIG_NET_SAMPLE_SNTP_SERVER_ADDRESS, CONFIG_NET_SAMPLE_SNTP_SERVER_PORT,
+				   family, SOCK_DGRAM, &addr, &addrlen);
+	if (rv != 0) {
+		LOG_ERR("Failed to lookup %s SNTP server (%d)", family_str, rv);
+		return;
+	}
+
+	rv = sntp_init(&ctx, &addr, addrlen);
 	if (rv < 0) {
-		LOG_ERR("Failed to init SNTP IPv4 ctx: %d", rv);
+		LOG_ERR("Failed to init SNTP %s ctx: %d", family_str, rv);
 		goto end;
 	}
 
-	LOG_INF("Sending SNTP IPv4 request...");
-	rv = sntp_query(&ctx, 4 * MSEC_PER_SEC, &sntp_time);
+	LOG_INF("Sending SNTP %s request...", family_str);
+	rv = sntp_query(&ctx, 4 * MSEC_PER_SEC, &s_time);
 	if (rv < 0) {
-		LOG_ERR("SNTP IPv4 request failed: %d", rv);
+		LOG_ERR("SNTP %s request failed: %d", family_str, rv);
 		goto end;
 	}
 
-	LOG_INF("status: %d", rv);
-	LOG_INF("time since Epoch: high word: %u, low word: %u",
-		(uint32_t)(sntp_time.seconds >> 32), (uint32_t)sntp_time.seconds);
+	LOG_INF("SNTP Time: %llu", s_time.seconds);
 
-#if defined(CONFIG_NET_IPV6)
 	sntp_close(&ctx);
 
-	/* ipv6 */
-	memset(&addr6, 0, sizeof(addr6));
-	addr6.sin6_family = AF_INET6;
-	addr6.sin6_port = htons(SNTP_PORT);
-	inet_pton(AF_INET6, SERVER_ADDR6, &addr6.sin6_addr);
-
-	rv = sntp_init(&ctx, (struct sockaddr *) &addr6,
-		       sizeof(struct sockaddr_in6));
+	rv = sntp_init_async(&ctx, &addr, addrlen, &service_sntp_async);
 	if (rv < 0) {
-		LOG_ERR("Failed to init SNTP IPv6 ctx: %d", rv);
+		LOG_ERR("Failed to initialise SNTP context (%d)", rv);
 		goto end;
 	}
 
-	LOG_INF("Sending SNTP IPv6 request...");
-	/* With such a timeout, this is expected to fail. */
-	rv = sntp_query(&ctx, 0, &sntp_time);
+	rv = sntp_send_async(&ctx);
 	if (rv < 0) {
-		LOG_ERR("SNTP IPv6 request: %d", rv);
+		LOG_ERR("Failed to send SNTP query (%d)", rv);
 		goto end;
 	}
 
-	LOG_INF("status: %d", rv);
-	LOG_INF("time since Epoch: high word: %u, low word: %u",
-		(uint32_t)(sntp_time.seconds >> 32), (uint32_t)sntp_time.seconds);
-#endif
+	/* Wait for the response to be received asynchronously */
+	rv = k_sem_take(&sntp_async_received, K_MSEC(CONFIG_NET_SAMPLE_SNTP_SERVER_TIMEOUT_MS));
+	if (rv < 0) {
+		LOG_INF("SNTP response timed out (%d)", rv);
+	}
 
 end:
 	sntp_close(&ctx);
+}
+
+int main(void)
+{
+	wait_for_network();
+
+	do_sntp(AF_INET);
+
+#if defined(CONFIG_NET_IPV6)
+	do_sntp(AF_INET6);
+#endif
+
 	return 0;
 }
diff --git a/samples/net/sockets/txtime/CMakeLists.txt b/samples/net/sockets/txtime/CMakeLists.txt
index 2077eff5909..44eef0c70e4 100644
--- a/samples/net/sockets/txtime/CMakeLists.txt
+++ b/samples/net/sockets/txtime/CMakeLists.txt
@@ -6,4 +6,5 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
 project(sockets_txtime)
 
 target_sources(app PRIVATE src/main.c)
-target_sources_ifdef(CONFIG_NET_VLAN app PRIVATE src/vlan.c)
+
+include(${ZEPHYR_BASE}/samples/net/common/common.cmake)
diff --git a/samples/net/sockets/txtime/Kconfig b/samples/net/sockets/txtime/Kconfig
index b4feeb33d1a..5c03c83cb96 100644
--- a/samples/net/sockets/txtime/Kconfig
+++ b/samples/net/sockets/txtime/Kconfig
@@ -63,42 +63,5 @@ config NET_SAMPLE_PACKET_TXTIME
 	  but for purpose of this sample application, we set the time in
 	  microseconds in this config option.
 
-config NET_SAMPLE_IFACE2_MY_IPV6_ADDR
-	string "My IPv6 address for second interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE2_MY_IPV4_ADDR
-	string "My IPv4 address for second interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE2_VLAN_TAG
-	int "VLAN tag for second interface"
-	default 100
-	range 0 4094
-	depends on NET_VLAN
-	help
-	  Set VLAN (virtual LAN) tag (id) that is used in the sample
-	  application.
-
-config NET_SAMPLE_IFACE3_MY_IPV6_ADDR
-	string "My IPv6 address for third interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE3_MY_IPV4_ADDR
-	string "My IPv4 address for third interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE3_VLAN_TAG
-	int "VLAN tag for third interface"
-	default 200
-	range 0 4094
-	depends on NET_VLAN
-	help
-	  Set VLAN (virtual LAN) tag (id) that is used in the sample
-	  application.
-
+source "samples/net/common/Kconfig"
 source "Kconfig.zephyr"
diff --git a/samples/net/sockets/txtime/boards/native_sim.conf b/samples/net/sockets/txtime/boards/native_sim.conf
index 6e1628ae391..641cb846fc1 100644
--- a/samples/net/sockets/txtime/boards/native_sim.conf
+++ b/samples/net/sockets/txtime/boards/native_sim.conf
@@ -1,2 +1,2 @@
-CONFIG_ETH_NATIVE_POSIX_PTP_CLOCK=y
+CONFIG_ETH_NATIVE_TAP_PTP_CLOCK=y
 CONFIG_PTP=y
diff --git a/samples/net/sockets/txtime/overlay-vlan.conf b/samples/net/sockets/txtime/overlay-vlan.conf
index 78b6e1f3831..73ac192ee46 100644
--- a/samples/net/sockets/txtime/overlay-vlan.conf
+++ b/samples/net/sockets/txtime/overlay-vlan.conf
@@ -11,16 +11,8 @@ CONFIG_NET_CONFIG_PEER_IPV6_ADDR="2001:db8::2"
 CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.0.2.1"
 CONFIG_NET_CONFIG_PEER_IPV4_ADDR="192.0.2.2"
 
-# Second ethernet interface will have these settings
-CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR="2001:db8:100::1"
-# TEST-NET-2 from RFC 5737
-CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR="198.51.100.1"
-# VLAN tag for the second interface
-CONFIG_NET_SAMPLE_IFACE2_VLAN_TAG=100
+# First VLAN interface will have these settings
+CONFIG_NET_SAMPLE_COMMON_VLAN_SETUP_1="100;2001:db8:100::1/64,198.51.100.1/24"
 
-# Settings for the third network interface
-CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR="2001:db8:200::1"
-# TEST-NET-3 from RFC 5737
-CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR="203.0.113.1"
-# VLAN tag for the second interface
-CONFIG_NET_SAMPLE_IFACE3_VLAN_TAG=200
+# Second VLAN interface will have these settings
+CONFIG_NET_SAMPLE_COMMON_VLAN_SETUP_2="200;2001:db8:200::1/64,203.0.113.1/24"
diff --git a/samples/net/sockets/txtime/src/main.c b/samples/net/sockets/txtime/src/main.c
index f5f9df96475..d4bc85a3f2a 100644
--- a/samples/net/sockets/txtime/src/main.c
+++ b/samples/net/sockets/txtime/src/main.c
@@ -22,6 +22,8 @@ LOG_MODULE_REGISTER(net_txtime_sample, LOG_LEVEL_DBG);
 #include <zephyr/net/ethernet.h>
 #include <zephyr/net/ethernet_mgmt.h>
 
+#include "net_sample_common.h"
+
 #define APP_BANNER "Run SO_TXTIME client"
 
 #define DHCPV4_MASK (NET_EVENT_IPV4_DHCP_BOUND | \
@@ -63,8 +65,6 @@ K_SEM_DEFINE(run_app, 0, 1);
 static bool want_to_quit;
 static bool connected;
 
-extern int init_vlan(void);
-
 static void quit(void)
 {
 	k_sem_give(&quit_lock);
diff --git a/samples/net/sockets/txtime/src/vlan.c b/samples/net/sockets/txtime/src/vlan.c
deleted file mode 100644
index 8eee42161de..00000000000
--- a/samples/net/sockets/txtime/src/vlan.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Copyright (c) 2020 Intel Corporation.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/logging/log.h>
-LOG_MODULE_DECLARE(net_txtime_sample, LOG_LEVEL_DBG);
-
-#include <zephyr/kernel.h>
-
-#include <zephyr/net/ethernet.h>
-
-/* User data for the interface callback */
-struct ud {
-	struct net_if *first;
-	struct net_if *second;
-};
-
-static void iface_cb(struct net_if *iface, void *user_data)
-{
-	struct ud *ud = user_data;
-
-	if (net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL)) {
-		return;
-	}
-
-	if (!ud->first) {
-		ud->first = iface;
-		return;
-	}
-
-	if (!ud->second) {
-		ud->second = iface;
-		return;
-	}
-}
-
-static int setup_iface(struct net_if *eth_iface,
-		       struct net_if *iface,
-		       const char *ipv6_addr,
-		       const char *ipv4_addr,
-		       uint16_t vlan_tag)
-{
-	struct net_if_addr *ifaddr;
-	struct in_addr addr4;
-	struct in6_addr addr6;
-	int ret;
-
-	if (!iface) {
-		LOG_DBG("VLAN interface not set");
-		return -ENOENT;
-	}
-
-	ret = net_eth_vlan_enable(eth_iface, vlan_tag);
-	if (ret < 0) {
-		LOG_ERR("Cannot enable VLAN for tag %d (%d)", vlan_tag, ret);
-	}
-
-	if (IS_ENABLED(CONFIG_NET_IPV6)) {
-		if (net_addr_pton(AF_INET6, ipv6_addr, &addr6)) {
-			LOG_ERR("Invalid address: %s", ipv6_addr);
-			return -EINVAL;
-		}
-
-		ifaddr = net_if_ipv6_addr_add(iface, &addr6,
-					      NET_ADDR_MANUAL, 0);
-		if (!ifaddr) {
-			LOG_ERR("Cannot add %s to interface %p",
-				ipv6_addr, iface);
-			return -EINVAL;
-		}
-	}
-
-	if (IS_ENABLED(CONFIG_NET_IPV4)) {
-		if (net_addr_pton(AF_INET, ipv4_addr, &addr4)) {
-			LOG_ERR("Invalid address: %s", ipv6_addr);
-			return -EINVAL;
-		}
-
-		ifaddr = net_if_ipv4_addr_add(iface, &addr4,
-					      NET_ADDR_MANUAL, 0);
-		if (!ifaddr) {
-			LOG_ERR("Cannot add %s to interface %p",
-				ipv4_addr, iface);
-			return -EINVAL;
-		}
-	}
-
-	LOG_DBG("Interface %p VLAN tag %d setup done.", iface, vlan_tag);
-
-	return 0;
-}
-
-int init_vlan(void)
-{
-	struct net_if *iface;
-	enum ethernet_hw_caps caps;
-	struct ud ud;
-	int ret;
-
-	iface = net_if_get_first_by_type(&NET_L2_GET_NAME(ETHERNET));
-	if (!iface) {
-		LOG_ERR("No ethernet interfaces found.");
-		return -ENOENT;
-	}
-
-	memset(&ud, 0, sizeof(ud));
-
-	net_if_foreach(iface_cb, &ud);
-
-	caps = net_eth_get_hw_capabilities(iface);
-	if (!(caps & ETHERNET_HW_VLAN)) {
-		LOG_DBG("Interface %p does not support %s", iface, "VLAN");
-		return -ENOENT;
-	}
-
-	ret = setup_iface(iface, ud.first,
-			  CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE2_VLAN_TAG);
-	if (ret < 0) {
-		return ret;
-	}
-
-	ret = setup_iface(iface, ud.second,
-			  CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE3_VLAN_TAG);
-	if (ret < 0) {
-		return ret;
-	}
-
-	/* Bring up the VLAN interface automatically */
-	net_if_up(ud.first);
-	net_if_up(ud.second);
-
-	return 0;
-}
diff --git a/samples/net/sockets/websocket_client/sample.yaml b/samples/net/sockets/websocket_client/sample.yaml
index df7603cf1a1..a0472b856f9 100644
--- a/samples/net/sockets/websocket_client/sample.yaml
+++ b/samples/net/sockets/websocket_client/sample.yaml
@@ -7,10 +7,6 @@ common:
     - websocket
   min_ram: 35
   depends_on: netif
-  # native_posix does not work with CONFIG_POSIX_API
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 sample:
   description: Websocket client sample
   name: websocket_client
diff --git a/samples/net/telnet/sample.yaml b/samples/net/telnet/sample.yaml
index 5dd685e6bf3..2a29b5af542 100644
--- a/samples/net/telnet/sample.yaml
+++ b/samples/net/telnet/sample.yaml
@@ -7,10 +7,7 @@ common:
 sample:
   name: Telnet Server
 tests:
-  sample.net.telnet:
-    platform_exclude:
-      - native_posix
-      - native_posix/native/64
+  sample.net.telnet: {}
   sample.net.telnet.wifi.nrf70dk:
     extra_args:
       - SNIPPET=wifi-ipv4
diff --git a/samples/net/vlan/Kconfig b/samples/net/vlan/Kconfig
index 88ae77ef983..fde211744a7 100644
--- a/samples/net/vlan/Kconfig
+++ b/samples/net/vlan/Kconfig
@@ -5,54 +5,6 @@
 
 mainmenu "Networking VLAN sample application"
 
-config NET_SAMPLE_IFACE2_MY_IPV6_ADDR
-	string "My IPv6 address for second interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE2_MY_IPV4_ADDR
-	string "My IPv4 address for second interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE2_MY_IPV4_NETMASK
-	string "My IPv4 netmask for second interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE2_VLAN_TAG
-	int "VLAN tag for second interface"
-	default 100
-	range 0 4094
-	depends on NET_VLAN
-	help
-	  Set VLAN (virtual LAN) tag (id) that is used in the sample
-	  application.
-
-config NET_SAMPLE_IFACE3_MY_IPV6_ADDR
-	string "My IPv6 address for third interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE3_MY_IPV4_ADDR
-	string "My IPv4 address for third interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE3_MY_IPV4_NETMASK
-	string "My IPv4 netmask for third interface"
-	help
-	  The value depends on your network setup.
-
-config NET_SAMPLE_IFACE3_VLAN_TAG
-	int "VLAN tag for third interface"
-	default 200
-	range 0 4094
-	depends on NET_VLAN
-	help
-	  Set VLAN (virtual LAN) tag (id) that is used in the sample
-	  application.
-
 config NET_SAMPLE_IFACE_MY_IPV6_PREFIXLEN
 	int "IPv6 address prefix length for the interfaces"
 	default 64
@@ -61,4 +13,5 @@ config NET_SAMPLE_IFACE_MY_IPV6_PREFIXLEN
 	  Set the IPv6 address prefix length (netmask) for the interfaces
 	  that is used in the sample application.
 
+source "samples/net/common/Kconfig"
 source "Kconfig.zephyr"
diff --git a/samples/net/vlan/prj.conf b/samples/net/vlan/prj.conf
index 20ea9f0627b..8215a18a809 100644
--- a/samples/net/vlan/prj.conf
+++ b/samples/net/vlan/prj.conf
@@ -6,6 +6,7 @@ CONFIG_NET_DHCPV4=n
 CONFIG_NET_UDP=y
 CONFIG_NET_TCP=y
 CONFIG_NET_STATISTICS=y
+CONFIG_POSIX_API=y
 
 CONFIG_TEST_RANDOM_GENERATOR=y
 
@@ -41,21 +42,13 @@ CONFIG_NET_CONFIG_PEER_IPV6_ADDR="2001:db8::2"
 CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.0.2.1"
 CONFIG_NET_CONFIG_PEER_IPV4_ADDR="192.0.2.2"
 
-# Second VLAN supported network interface will have these settings
-CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR="2001:db8:100::1"
+# First VLAN interface will have these settings
 # TEST-NET-2 from RFC 5737
-CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR="198.51.100.1"
-CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_NETMASK="255.255.255.0"
-# VLAN tag for the second interface
-CONFIG_NET_SAMPLE_IFACE2_VLAN_TAG=100
+CONFIG_NET_SAMPLE_COMMON_VLAN_SETUP_1="100;2001:db8:100::1/64,198.51.100.1/24"
 
-# Settings for the third VLAN supported network interface
-CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR="2001:db8:200::1"
+# Second VLAN interface will have these settings
 # TEST-NET-3 from RFC 5737
-CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR="203.0.113.1"
-CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_NETMASK="255.255.255.0"
-# VLAN tag for the second interface
-CONFIG_NET_SAMPLE_IFACE3_VLAN_TAG=200
+CONFIG_NET_SAMPLE_COMMON_VLAN_SETUP_2="200;2001:db8:200::1/64,203.0.113.1/24"
 
 # Logging
 CONFIG_LOG=y
diff --git a/samples/net/vlan/src/main.c b/samples/net/vlan/src/main.c
index cfcff4c2643..865e9f306b8 100644
--- a/samples/net/vlan/src/main.c
+++ b/samples/net/vlan/src/main.c
@@ -15,144 +15,10 @@ LOG_MODULE_REGISTER(net_vlan_sample, LOG_LEVEL_DBG);
 #include <zephyr/net/net_if.h>
 #include <zephyr/net/ethernet.h>
 
-struct ud {
-	struct net_if *first;
-	struct net_if *second;
-};
-
-static void iface_cb(struct net_if *iface, void *user_data)
-{
-	struct ud *ud = user_data;
-
-	if (net_if_l2(iface) != &NET_L2_GET_NAME(VIRTUAL)) {
-		return;
-	}
-
-	if (ud->first == NULL) {
-		ud->first = iface;
-		return;
-	}
-
-	ud->second = iface;
-}
-
-static int setup_iface(struct net_if *iface, struct net_if *vlan,
-		       const char *ipv6_addr, const char *ipv4_addr,
-		       const char *netmask, uint16_t vlan_tag)
-{
-	struct net_if_addr *ifaddr;
-	struct in_addr addr4;
-	struct in6_addr addr6, netaddr6;
-	int ret;
-
-	ret = net_eth_vlan_enable(iface, vlan_tag);
-	if (ret < 0) {
-		LOG_ERR("Cannot enable VLAN for tag %d (%d)", vlan_tag, ret);
-	}
-
-	if (IS_ENABLED(CONFIG_NET_IPV6)) {
-		if (net_addr_pton(AF_INET6, ipv6_addr, &addr6)) {
-			LOG_ERR("Invalid address: %s", ipv6_addr);
-			return -EINVAL;
-		}
-
-		ifaddr = net_if_ipv6_addr_add(vlan, &addr6,
-					      NET_ADDR_MANUAL, 0);
-		if (!ifaddr) {
-			LOG_ERR("Cannot add %s to interface %p",
-				ipv6_addr, vlan);
-			return -EINVAL;
-		}
-
-		net_ipv6_addr_prefix_mask((uint8_t *)&addr6,
-					  (uint8_t *)&netaddr6,
-					  CONFIG_NET_SAMPLE_IFACE_MY_IPV6_PREFIXLEN);
-
-		if (!net_if_ipv6_prefix_add(vlan, &netaddr6,
-					    CONFIG_NET_SAMPLE_IFACE_MY_IPV6_PREFIXLEN,
-					    (uint32_t)0xffffffff)) {
-			LOG_ERR("Cannot add %s with prefix_len %d to interface %p",
-				ipv6_addr,
-				CONFIG_NET_SAMPLE_IFACE_MY_IPV6_PREFIXLEN,
-				vlan);
-			return -EINVAL;
-		}
-	}
-
-	if (IS_ENABLED(CONFIG_NET_IPV4)) {
-		if (net_addr_pton(AF_INET, ipv4_addr, &addr4)) {
-			LOG_ERR("Invalid address: %s", ipv4_addr);
-			return -EINVAL;
-		}
-
-		ifaddr = net_if_ipv4_addr_add(vlan, &addr4,
-					      NET_ADDR_MANUAL, 0);
-		if (!ifaddr) {
-			LOG_ERR("Cannot add %s to interface %p",
-				ipv4_addr, vlan);
-			return -EINVAL;
-		}
-
-		if (netmask && netmask[0]) {
-			struct in_addr nm;
-
-			if (net_addr_pton(AF_INET, netmask, &nm)) {
-				LOG_ERR("Invalid netmask: %s", ipv4_addr);
-				return -EINVAL;
-			}
-
-			net_if_ipv4_set_netmask_by_addr(vlan, &addr4, &nm);
-		}
-	}
-
-	LOG_DBG("Interface %p VLAN tag %d setup done.", vlan, vlan_tag);
-
-	return 0;
-}
-
-static int init_app(void)
-{
-	struct net_if *iface;
-	struct ud ud;
-	int ret;
-
-	iface = net_if_get_first_by_type(&NET_L2_GET_NAME(ETHERNET));
-	if (!iface) {
-		LOG_ERR("No ethernet interfaces found.");
-		return -ENOENT;
-	}
-
-	memset(&ud, 0, sizeof(ud));
-
-	net_if_foreach(iface_cb, &ud);
-
-	ret = setup_iface(iface, ud.first,
-			  CONFIG_NET_SAMPLE_IFACE2_MY_IPV6_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE2_MY_IPV4_NETMASK,
-			  CONFIG_NET_SAMPLE_IFACE2_VLAN_TAG);
-	if (ret < 0) {
-		return ret;
-	}
-
-	ret = setup_iface(iface, ud.second,
-			  CONFIG_NET_SAMPLE_IFACE3_MY_IPV6_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_ADDR,
-			  CONFIG_NET_SAMPLE_IFACE3_MY_IPV4_NETMASK,
-			  CONFIG_NET_SAMPLE_IFACE3_VLAN_TAG);
-	if (ret < 0) {
-		return ret;
-	}
-
-	/* Bring up the VLAN interface automatically */
-	net_if_up(ud.first);
-	net_if_up(ud.second);
-
-	return ret;
-}
+#include "net_sample_common.h"
 
 int main(void)
 {
-	init_app();
+	init_vlan();
 	return 0;
 }
diff --git a/samples/net/wifi/apsta_mode/README.rst b/samples/net/wifi/apsta_mode/README.rst
index 38f5c1c2e7c..06a6b46381e 100644
--- a/samples/net/wifi/apsta_mode/README.rst
+++ b/samples/net/wifi/apsta_mode/README.rst
@@ -40,7 +40,7 @@ Building, Flashing and Running
 ******************************
 
 .. zephyr-app-commands::
-   :zephyr-app: samples/boards/espressif/deep_sleep
+   :zephyr-app: samples/net/wifi/apsta_mode
    :board: esp32_devkitc_wroom/esp32/procpu
    :goals: build flash
    :compact:
diff --git a/samples/net/wifi/apsta_mode/boards/esp32_devkitc_wroom_procpu.overlay b/samples/net/wifi/apsta_mode/boards/esp32_devkitc_wroom_procpu.overlay
deleted file mode 100644
index a53651c69a2..00000000000
--- a/samples/net/wifi/apsta_mode/boards/esp32_devkitc_wroom_procpu.overlay
+++ /dev/null
@@ -1,10 +0,0 @@
-&wifi {
-	status = "okay";
-};
-
-/ {
-	wifi_ap: wifi_ap {
-		compatible = "espressif,esp32-wifi";
-		status = "okay";
-	};
-};
diff --git a/samples/net/wifi/apsta_mode/boards/esp32_devkitc_wroom_procpu.conf b/samples/net/wifi/apsta_mode/socs/esp32_procpu.conf
similarity index 100%
rename from samples/net/wifi/apsta_mode/boards/esp32_devkitc_wroom_procpu.conf
rename to samples/net/wifi/apsta_mode/socs/esp32_procpu.conf
diff --git a/samples/net/wifi/apsta_mode/socs/esp32_procpu.overlay b/samples/net/wifi/apsta_mode/socs/esp32_procpu.overlay
new file mode 100644
index 00000000000..7d1a4893c71
--- /dev/null
+++ b/samples/net/wifi/apsta_mode/socs/esp32_procpu.overlay
@@ -0,0 +1,6 @@
+/ {
+	wifi_ap: wifi_ap {
+		compatible = "espressif,esp32-wifi";
+		status = "okay";
+	};
+};
diff --git a/samples/net/wifi/shell/boards/frdm_rw612.conf b/samples/net/wifi/shell/boards/frdm_rw612.conf
index 2b17e4ea9ac..89a89028522 100644
--- a/samples/net/wifi/shell/boards/frdm_rw612.conf
+++ b/samples/net/wifi/shell/boards/frdm_rw612.conf
@@ -1,124 +1,11 @@
 CONFIG_WIFI_NXP=y
 CONFIG_NXP_RW610=y
-CONFIG_NXP_WIFI_SHELL=y
-
-#
-# C Library
-#
-CONFIG_REQUIRES_FULL_LIBC=y
-CONFIG_CBPRINTF_FP_SUPPORT=y
-
-# log
-CONFIG_WIFI_LOG_LEVEL_DBG=y
-CONFIG_THREAD_LOCAL_STORAGE=y
-CONFIG_ASSERT=y
-CONFIG_ASSERT_LEVEL=2
-CONFIG_LOG_MODE_IMMEDIATE=y
-CONFIG_LOG_PRINTK=n
-
-# os
-CONFIG_THREAD_CUSTOM_DATA=y
-CONFIG_EVENTS=y
-CONFIG_SYS_HEAP_AUTO=y
-CONFIG_SCHED_MULTIQ=y
-CONFIG_ZVFS_OPEN_MAX=30
-
-# shell
-CONFIG_SHELL_ARGC_MAX=48
-CONFIG_WIFI_SHELL_MAX_AP_STA=8
-CONFIG_WIFI_MGMT_AP_MAX_NUM_STA=8
-CONFIG_SHELL_CMD_BUFF_SIZE=512
-
-# net
-CONFIG_NET_L2_ETHERNET=y
-CONFIG_NET_DHCPV4_SERVER_ADDR_COUNT=32
-CONFIG_NET_IPV4=y
-CONFIG_NET_IPV6=y
-CONFIG_ETH_MCUX=n
-CONFIG_NET_ZPERF=y
-CONFIG_NET_ZPERF_MAX_PACKET_SIZE=1500
-CONFIG_NET_BUF_LOG=y
-CONFIG_NET_PKT_RX_COUNT=60
-CONFIG_NET_PKT_TX_COUNT=40
-CONFIG_NET_BUF_RX_COUNT=60
-CONFIG_NET_BUF_TX_COUNT=80
-CONFIG_NET_BUF_DATA_SIZE=1744
-CONFIG_NET_TC_TX_COUNT=1
-CONFIG_NET_TC_RX_COUNT=1
-CONFIG_NET_MGMT_EVENT_QUEUE_SIZE=20
-CONFIG_NET_IF_MAX_IPV4_COUNT=2
-CONFIG_NET_IF_MAX_IPV6_COUNT=2
-CONFIG_DNS_RESOLVER=y
-CONFIG_DNS_RESOLVER_MAX_SERVERS=2
-CONFIG_NET_SOCKETS_POLL_MAX=14
-CONFIG_NET_ZPERF_MAX_SESSIONS=6
-CONFIG_NET_IPV4_FRAGMENT=y
-CONFIG_NET_IPV4_FRAGMENT_MAX_COUNT=3
-CONFIG_NET_IPV4_FRAGMENT_MAX_PKT=7
-CONFIG_NET_IPV4_FRAGMENT_TIMEOUT=3
-CONFIG_NET_IPV6_FRAGMENT=y
-CONFIG_NET_IPV6_FRAGMENT_MAX_COUNT=3
-CONFIG_NET_IPV6_FRAGMENT_MAX_PKT=8
-CONFIG_NET_IPV6_FRAGMENT_TIMEOUT=3
-CONFIG_NET_MAX_CONN=10
-CONFIG_NET_DHCPV4_SERVER_ICMP_PROBE_TIMEOUT=100
 CONFIG_ETH_DRIVER=n
 
-# net threads priority
-CONFIG_NET_TC_THREAD_PRIO_CUSTOM=y
-CONFIG_NET_TC_THREAD_PREEMPTIVE=y
-CONFIG_NET_TCP_WORKER_PRIO=-16
-CONFIG_NET_TC_TX_THREAD_BASE_PRIO=3
-CONFIG_NET_TC_RX_THREAD_BASE_PRIO=3
-CONFIG_ZPERF_WORK_Q_THREAD_PRIORITY=3
-CONFIG_NET_SOCKETS_SERVICE_THREAD_PRIO=3
-CONFIG_NET_TC_SKIP_FOR_HIGH_PRIO=y
-CONFIG_NET_CONTEXT_PRIORITY=y
-CONFIG_NET_MGMT_THREAD_PRIO_CUSTOM=y
-CONFIG_NET_MGMT_THREAD_PRIORITY=3
-
-# power management
-CONFIG_PM=y
-CONFIG_PM_DEVICE=y
-CONFIG_PM_LOG_LEVEL_OFF=y
-CONFIG_PM_DEVICE_LOG_LEVEL_OFF=y
-CONFIG_IDLE_STACK_SIZE=1024
-
 # stack size
 CONFIG_SHELL_STACK_SIZE=6144
 CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=2048
 CONFIG_NET_MGMT_EVENT_STACK_SIZE=4608
 CONFIG_NET_TCP_WORKQ_STACK_SIZE=2048
 CONFIG_MAIN_STACK_SIZE=4096
-CONFIG_NET_SOCKETS_SERVICE_STACK_SIZE=4096
-
-# optimization level
-# refer to Kconfig.zephyr for Optimizations Level
-CONFIG_SPEED_OPTIMIZATIONS=y
-#CONFIG_SIZE_OPTIMIZATIONS=y
-#CONFIG_DEBUG_OPTIMIZATIONS=y
-#CONFIG_NO_OPTIMIZATIONS=y
-
-# debug & stats
-CONFIG_SYS_HEAP_VALIDATE=y
-CONFIG_SYS_HEAP_RUNTIME_STATS=y
-#CONFIG_NET_PKT_TXTIME_STATS=y
-#CONFIG_NET_PKT_TXTIME_STATS_DETAIL=y
-CONFIG_NET_STATISTICS_WIFI=y
-CONFIG_NET_STATISTICS_USER_API=y
-#CONFIG_NET_STATISTICS_PERIODIC_OUTPUT=y
-#CONFIG_NET_BUF_POOL_USAGE=y
-#CONFIG_NET_DEBUG_NET_PKT_ALLOC=y
-
-# stack size for -O0
-#CONFIG_SHELL_STACK_SIZE=8192
-#CONFIG_NET_TCP_WORKQ_STACK_SIZE=4096
-#CONFIG_NET_TX_STACK_SIZE=4096
-#CONFIG_NET_RX_STACK_SIZE=4096
-#CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=4096
-#CONFIG_ZPERF_WORK_Q_STACK_SIZE=4096
-#CONFIG_MAIN_STACK_SIZE=4096
-#CONFIG_IDLE_STACK_SIZE=2048
-
-# comment out for -O0
-CONFIG_CODE_DATA_RELOCATION_SRAM=y
+CONFIG_IDLE_STACK_SIZE=1024
diff --git a/samples/net/wifi/shell/boards/rd_rw612_bga.conf b/samples/net/wifi/shell/boards/rd_rw612_bga.conf
index b3880cc0670..2ebe1e0001a 100644
--- a/samples/net/wifi/shell/boards/rd_rw612_bga.conf
+++ b/samples/net/wifi/shell/boards/rd_rw612_bga.conf
@@ -1,87 +1,5 @@
 CONFIG_WIFI_NXP=y
 CONFIG_NXP_RW610=y
-CONFIG_NXP_WIFI_SHELL=y
-
-#
-# C Library
-#
-CONFIG_REQUIRES_FULL_LIBC=y
-CONFIG_CBPRINTF_FP_SUPPORT=y
-
-# log
-CONFIG_WIFI_LOG_LEVEL_DBG=y
-CONFIG_THREAD_LOCAL_STORAGE=y
-CONFIG_ASSERT=y
-CONFIG_ASSERT_LEVEL=2
-CONFIG_LOG_MODE_IMMEDIATE=y
-CONFIG_LOG_PRINTK=n
-
-# os
-CONFIG_THREAD_CUSTOM_DATA=y
-CONFIG_EVENTS=y
-CONFIG_SYS_HEAP_AUTO=y
-CONFIG_SCHED_MULTIQ=y
-CONFIG_ZVFS_OPEN_MAX=30
-
-# shell
-CONFIG_SHELL_ARGC_MAX=48
-CONFIG_WIFI_SHELL_MAX_AP_STA=8
-CONFIG_WIFI_MGMT_AP_MAX_NUM_STA=8
-CONFIG_SHELL_CMD_BUFF_SIZE=512
-
-# net
-CONFIG_NET_L2_ETHERNET=y
-CONFIG_NET_DHCPV4_SERVER_ADDR_COUNT=32
-CONFIG_NET_IPV4=y
-CONFIG_NET_IPV6=y
-CONFIG_ETH_MCUX=n
-CONFIG_NET_ZPERF=y
-CONFIG_NET_ZPERF_MAX_PACKET_SIZE=1500
-CONFIG_NET_BUF_LOG=y
-CONFIG_NET_PKT_RX_COUNT=60
-CONFIG_NET_PKT_TX_COUNT=40
-CONFIG_NET_BUF_RX_COUNT=60
-CONFIG_NET_BUF_TX_COUNT=80
-CONFIG_NET_BUF_DATA_SIZE=1744
-CONFIG_NET_TC_TX_COUNT=1
-CONFIG_NET_TC_RX_COUNT=1
-CONFIG_NET_MGMT_EVENT_QUEUE_SIZE=20
-CONFIG_NET_IF_MAX_IPV4_COUNT=2
-CONFIG_NET_IF_MAX_IPV6_COUNT=2
-CONFIG_DNS_RESOLVER=y
-CONFIG_DNS_RESOLVER_MAX_SERVERS=2
-CONFIG_NET_SOCKETS_POLL_MAX=14
-CONFIG_NET_ZPERF_MAX_SESSIONS=6
-CONFIG_NET_IPV4_FRAGMENT=y
-CONFIG_NET_IPV4_FRAGMENT_MAX_COUNT=3
-CONFIG_NET_IPV4_FRAGMENT_MAX_PKT=7
-CONFIG_NET_IPV4_FRAGMENT_TIMEOUT=3
-CONFIG_NET_IPV6_FRAGMENT=y
-CONFIG_NET_IPV6_FRAGMENT_MAX_COUNT=3
-CONFIG_NET_IPV6_FRAGMENT_MAX_PKT=8
-CONFIG_NET_IPV6_FRAGMENT_TIMEOUT=3
-CONFIG_NET_MAX_CONN=10
-CONFIG_NET_DHCPV4_SERVER_ICMP_PROBE_TIMEOUT=100
-
-# net threads priority
-CONFIG_NET_TC_THREAD_PRIO_CUSTOM=y
-CONFIG_NET_TC_THREAD_PREEMPTIVE=y
-CONFIG_NET_TCP_WORKER_PRIO=-16
-CONFIG_NET_TC_TX_THREAD_BASE_PRIO=3
-CONFIG_NET_TC_RX_THREAD_BASE_PRIO=3
-CONFIG_ZPERF_WORK_Q_THREAD_PRIORITY=3
-CONFIG_NET_SOCKETS_SERVICE_THREAD_PRIO=3
-CONFIG_NET_TC_SKIP_FOR_HIGH_PRIO=y
-CONFIG_NET_CONTEXT_PRIORITY=y
-CONFIG_NET_MGMT_THREAD_PRIO_CUSTOM=y
-CONFIG_NET_MGMT_THREAD_PRIORITY=3
-
-# power management
-CONFIG_PM=y
-CONFIG_PM_DEVICE=y
-CONFIG_PM_LOG_LEVEL_OFF=y
-CONFIG_PM_DEVICE_LOG_LEVEL_OFF=y
-CONFIG_IDLE_STACK_SIZE=1024
 
 # stack size
 CONFIG_SHELL_STACK_SIZE=6144
@@ -89,35 +7,4 @@ CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=2048
 CONFIG_NET_MGMT_EVENT_STACK_SIZE=4608
 CONFIG_NET_TCP_WORKQ_STACK_SIZE=2048
 CONFIG_MAIN_STACK_SIZE=4096
-CONFIG_NET_SOCKETS_SERVICE_STACK_SIZE=4096
-
-# optimization level
-# refer to Kconfig.zephyr for Optimizations Level
-CONFIG_SPEED_OPTIMIZATIONS=y
-#CONFIG_SIZE_OPTIMIZATIONS=y
-#CONFIG_DEBUG_OPTIMIZATIONS=y
-#CONFIG_NO_OPTIMIZATIONS=y
-
-# debug & stats
-CONFIG_SYS_HEAP_VALIDATE=y
-CONFIG_SYS_HEAP_RUNTIME_STATS=y
-#CONFIG_NET_PKT_TXTIME_STATS=y
-#CONFIG_NET_PKT_TXTIME_STATS_DETAIL=y
-CONFIG_NET_STATISTICS_WIFI=y
-CONFIG_NET_STATISTICS_USER_API=y
-#CONFIG_NET_STATISTICS_PERIODIC_OUTPUT=y
-#CONFIG_NET_BUF_POOL_USAGE=y
-#CONFIG_NET_DEBUG_NET_PKT_ALLOC=y
-
-# stack size for -O0
-#CONFIG_SHELL_STACK_SIZE=8192
-#CONFIG_NET_TCP_WORKQ_STACK_SIZE=4096
-#CONFIG_NET_TX_STACK_SIZE=4096
-#CONFIG_NET_RX_STACK_SIZE=4096
-#CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=4096
-#CONFIG_ZPERF_WORK_Q_STACK_SIZE=4096
-#CONFIG_MAIN_STACK_SIZE=4096
-#CONFIG_IDLE_STACK_SIZE=2048
-
-# comment out for -O0
-CONFIG_CODE_DATA_RELOCATION_SRAM=y
+CONFIG_IDLE_STACK_SIZE=1024
diff --git a/samples/net/wifi/shell/boards/overlay_hostap_rw612.conf b/samples/net/wifi/shell/nxp/overlay_hostap_rw612.conf
similarity index 79%
rename from samples/net/wifi/shell/boards/overlay_hostap_rw612.conf
rename to samples/net/wifi/shell/nxp/overlay_hostap_rw612.conf
index 1d6b298768d..28bb9eec041 100644
--- a/samples/net/wifi/shell/boards/overlay_hostap_rw612.conf
+++ b/samples/net/wifi/shell/nxp/overlay_hostap_rw612.conf
@@ -1,3 +1,6 @@
+# This conf is used for supplicant support, including enterprise,
+# WPS and DPP mode.
+
 # wpa_supplicant
 CONFIG_WIFI_NM_WPA_SUPPLICANT=y
 CONFIG_WIFI_NM_WPA_SUPPLICANT_CLI=y
@@ -9,10 +12,7 @@ CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_MBEDTLS_PSA=y
 CONFIG_WIFI_NM_WPA_SUPPLICANT_INF_MON=n
 CONFIG_WIFI_NM_MAX_MANAGED_INTERFACES=2
 CONFIG_SAE_PWE_EARLY_EXIT=y
-CONFIG_WIFI_NM_HOSTAPD_AP=y
 CONFIG_WIFI_NM_WPA_SUPPLICANT_WPS=y
-CONFIG_WIFI_NM_HOSTAPD_WPS=y
-CONFIG_WIFI_NM_HOSTAPD_CRYPTO_ENTERPRISE=y
 
 # Enable mbedtls
 CONFIG_MBEDTLS=y
@@ -23,11 +23,12 @@ CONFIG_ENTROPY_GENERATOR=y
 CONFIG_MBEDTLS_PSA_CRYPTO_C=y
 CONFIG_MBEDTLS_ENTROPY_C=y
 CONFIG_MBEDTLS_SSL_MAX_CONTENT_LEN=8192
+
 # mbedtls heap for enterprise case
 CONFIG_MBEDTLS_ENABLE_HEAP=y
 CONFIG_MBEDTLS_HEAP_SIZE=69952
 
-#priority
+# priority
 CONFIG_WIFI_NM_WPA_SUPPLICANT_WQ_PRIO=3
 CONFIG_WIFI_NM_WPA_SUPPLICANT_PRIO=3
 
@@ -35,10 +36,5 @@ CONFIG_WIFI_NM_WPA_SUPPLICANT_PRIO=3
 CONFIG_WIFI_NM_WPA_SUPPLICANT_WQ_STACK_SIZE=12288
 CONFIG_WIFI_NM_WPA_SUPPLICANT_THREAD_STACK_SIZE=12288
 
-# stack size for -O0
-#CONFIG_WIFI_NM_WPA_SUPPLICANT_WQ_STACK_SIZE=16384
-#CONFIG_WIFI_NM_WPA_SUPPLICANT_THREAD_STACK_SIZE=16384
-
 # debug level
-#CONFIG_WIFI_NM_WPA_SUPPLICANT_DEBUG_LEVEL=2
 CONFIG_WIFI_NM_WPA_SUPPLICANT_LOG_LEVEL_INF=y
diff --git a/samples/net/wifi/shell/nxp/overlay_hostap_rw612_debug.conf b/samples/net/wifi/shell/nxp/overlay_hostap_rw612_debug.conf
new file mode 100644
index 00000000000..6e57a8f1a39
--- /dev/null
+++ b/samples/net/wifi/shell/nxp/overlay_hostap_rw612_debug.conf
@@ -0,0 +1,9 @@
+# This conf is used for supplicant debug mode.
+
+# stack size
+CONFIG_WIFI_NM_WPA_SUPPLICANT_WQ_STACK_SIZE=16384
+CONFIG_WIFI_NM_WPA_SUPPLICANT_THREAD_STACK_SIZE=16384
+
+# debug level
+CONFIG_WIFI_NM_WPA_SUPPLICANT_DEBUG_LEVEL=2
+CONFIG_WIFI_NM_WPA_SUPPLICANT_LOG_LEVEL_DBG=y
diff --git a/samples/net/wifi/shell/nxp/overlay_rw612.conf b/samples/net/wifi/shell/nxp/overlay_rw612.conf
new file mode 100644
index 00000000000..957a93795ac
--- /dev/null
+++ b/samples/net/wifi/shell/nxp/overlay_rw612.conf
@@ -0,0 +1,93 @@
+# This conf is used for adding SAP, IPv4/IPv6, Zperf, PM support,
+# and is optimized to get higher throughput performance.
+
+# log & stats
+CONFIG_WIFI_LOG_LEVEL_DBG=y
+CONFIG_THREAD_LOCAL_STORAGE=y
+CONFIG_ASSERT=y
+CONFIG_ASSERT_LEVEL=2
+CONFIG_LOG_MODE_IMMEDIATE=y
+CONFIG_LOG_PRINTK=n
+CONFIG_SYS_HEAP_VALIDATE=y
+CONFIG_SYS_HEAP_RUNTIME_STATS=y
+CONFIG_NET_STATISTICS_WIFI=y
+CONFIG_NET_STATISTICS_USER_API=y
+
+# lib & os
+CONFIG_REQUIRES_FULL_LIBC=y
+CONFIG_CBPRINTF_FP_SUPPORT=y
+CONFIG_THREAD_CUSTOM_DATA=y
+CONFIG_EVENTS=y
+CONFIG_SYS_HEAP_AUTO=y
+CONFIG_SCHED_MULTIQ=y
+CONFIG_ZVFS_OPEN_MAX=30
+
+# shell
+CONFIG_SHELL_ARGC_MAX=48
+CONFIG_SHELL_CMD_BUFF_SIZE=512
+
+# wifi
+CONFIG_NXP_WIFI_SOFTAP_SUPPORT=y
+CONFIG_WIFI_SHELL_MAX_AP_STA=8
+CONFIG_NXP_WIFI_TX_RX_ZERO_COPY=y
+
+# net
+CONFIG_NET_IPV4=y
+CONFIG_NET_IPV6=y
+CONFIG_NET_ZPERF=y
+CONFIG_NET_ZPERF_SERVER=y
+CONFIG_NET_ZPERF_MAX_PACKET_SIZE=1500
+CONFIG_NET_BUF_LOG=y
+CONFIG_NET_PKT_RX_COUNT=36
+CONFIG_NET_PKT_TX_COUNT=36
+CONFIG_NET_BUF_RX_COUNT=40
+CONFIG_NET_BUF_TX_COUNT=40
+CONFIG_NET_BUF_DATA_SIZE=1744
+CONFIG_NET_TCP_MAX_SEND_WINDOW_SIZE=46720
+CONFIG_NET_TCP_MAX_RECV_WINDOW_SIZE=46720
+CONFIG_NET_TC_TX_COUNT=1
+CONFIG_NET_TC_RX_COUNT=1
+CONFIG_NET_MGMT_EVENT_QUEUE_SIZE=20
+CONFIG_NET_IF_MAX_IPV4_COUNT=2
+CONFIG_NET_IF_MAX_IPV6_COUNT=2
+CONFIG_DNS_RESOLVER=y
+CONFIG_DNS_RESOLVER_MAX_SERVERS=2
+CONFIG_NET_SOCKETS_POLL_MAX=14
+CONFIG_NET_ZPERF_MAX_SESSIONS=6
+CONFIG_NET_IPV4_FRAGMENT=y
+CONFIG_NET_IPV4_FRAGMENT_MAX_COUNT=3
+CONFIG_NET_IPV4_FRAGMENT_MAX_PKT=7
+CONFIG_NET_IPV4_FRAGMENT_TIMEOUT=3
+CONFIG_NET_IPV6_FRAGMENT=y
+CONFIG_NET_IPV6_FRAGMENT_MAX_COUNT=3
+CONFIG_NET_IPV6_FRAGMENT_MAX_PKT=8
+CONFIG_NET_IPV6_FRAGMENT_TIMEOUT=3
+CONFIG_NET_MAX_CONN=10
+
+# net threads priority
+CONFIG_NET_TC_THREAD_PRIO_CUSTOM=y
+CONFIG_NET_TC_THREAD_PREEMPTIVE=y
+CONFIG_NET_TCP_WORKER_PRIO=-16
+CONFIG_NET_TC_TX_THREAD_BASE_PRIO=3
+CONFIG_NET_TC_RX_THREAD_BASE_PRIO=3
+CONFIG_ZPERF_WORK_Q_THREAD_PRIORITY=3
+CONFIG_NET_SOCKETS_SERVICE_THREAD_PRIO=3
+CONFIG_NET_TC_TX_SKIP_FOR_HIGH_PRIO=y
+CONFIG_NET_CONTEXT_PRIORITY=y
+CONFIG_NET_MGMT_THREAD_PRIO_CUSTOM=y
+CONFIG_NET_MGMT_THREAD_PRIORITY=3
+
+# stack size
+CONFIG_NET_SOCKETS_SERVICE_STACK_SIZE=4096
+
+# power management
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_LOG_LEVEL_OFF=y
+CONFIG_PM_DEVICE_LOG_LEVEL_OFF=y
+
+# optimization level
+CONFIG_SPEED_OPTIMIZATIONS=y
+
+# data relocation
+CONFIG_CODE_DATA_RELOCATION_SRAM=y
diff --git a/samples/net/wifi/shell/nxp/overlay_rw612_debug.conf b/samples/net/wifi/shell/nxp/overlay_rw612_debug.conf
new file mode 100644
index 00000000000..39084d8bf97
--- /dev/null
+++ b/samples/net/wifi/shell/nxp/overlay_rw612_debug.conf
@@ -0,0 +1,27 @@
+# This conf is used for O0 debug mode and net debug support
+
+# optimization level
+CONFIG_SPEED_OPTIMIZATIONS=n
+CONFIG_NO_OPTIMIZATIONS=y
+
+# power management
+CONFIG_PM=n
+CONFIG_PM_DEVICE=n
+
+# stack size
+CONFIG_SHELL_STACK_SIZE=8192
+CONFIG_NET_TCP_WORKQ_STACK_SIZE=4096
+CONFIG_NET_TX_STACK_SIZE=4096
+CONFIG_NET_RX_STACK_SIZE=4096
+CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=4096
+CONFIG_ZPERF_WORK_Q_STACK_SIZE=4096
+CONFIG_MAIN_STACK_SIZE=4096
+CONFIG_IDLE_STACK_SIZE=2048
+CONFIG_NXP_WIFI_DRIVER_TASK_STACK_SIZE=4096
+
+# net
+CONFIG_NET_BUF_POOL_USAGE=y
+CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION=y
+
+# data relocation
+CONFIG_CODE_DATA_RELOCATION_SRAM=n
diff --git a/samples/net/wifi/shell/overlay-debug.conf b/samples/net/wifi/shell/overlay-debug.conf
new file mode 100644
index 00000000000..d28921e3e8b
--- /dev/null
+++ b/samples/net/wifi/shell/overlay-debug.conf
@@ -0,0 +1,5 @@
+# Debugging
+CONFIG_STACK_SENTINEL=y
+CONFIG_DEBUG_COREDUMP=y
+CONFIG_DEBUG_COREDUMP_BACKEND_LOGGING=y
+CONFIG_DEBUG_COREDUMP_MEMORY_DUMP_MIN=y
diff --git a/samples/net/wifi/shell/sample.yaml b/samples/net/wifi/shell/sample.yaml
index 308d2e59dc6..75b751c0acf 100644
--- a/samples/net/wifi/shell/sample.yaml
+++ b/samples/net/wifi/shell/sample.yaml
@@ -12,6 +12,7 @@ tests:
       - cc3220sf_launchxl
       - disco_l475_iot1
       - reel_board
+      - siwx917_rb4338a
     integration_platforms:
       - cc3220sf_launchxl
   sample.net.wifi.mikroe_wifi_bt_click:
@@ -91,4 +92,9 @@ tests:
       - esp32c3_devkitm
       - esp32s3_devkitm/esp32s3/procpu
       - esp8684_devkitm
-      - esp32c6_devkitc
+      - esp32c6_devkitc/esp32c6/hpcore
+  sample.net.wifi.siwx91x_offloaded:
+    extra_args:
+      - CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_OFFLOAD=y
+    platform_allow:
+      - siwx917_rb4338a
diff --git a/samples/net/wifi/shell/socs/esp32_procpu.conf b/samples/net/wifi/shell/socs/esp32_procpu.conf
index a72fdf39efa..97ce6b96475 100644
--- a/samples/net/wifi/shell/socs/esp32_procpu.conf
+++ b/samples/net/wifi/shell/socs/esp32_procpu.conf
@@ -1,11 +1 @@
-CONFIG_WIFI=y
-
-CONFIG_NETWORKING=y
-CONFIG_NET_L2_ETHERNET=y
-
-CONFIG_NET_IPV6=n
-CONFIG_NET_IPV4=y
-CONFIG_NET_DHCPV4=y
 CONFIG_ESP32_WIFI_STA_AUTO_DHCPV4=y
-
-CONFIG_NET_LOG=y
diff --git a/samples/net/wifi/shell/socs/esp32_procpu.overlay b/samples/net/wifi/shell/socs/esp32_procpu.overlay
deleted file mode 100644
index ea9865cf5f8..00000000000
--- a/samples/net/wifi/shell/socs/esp32_procpu.overlay
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&wifi {
-	status = "okay";
-};
diff --git a/samples/net/wifi/shell/socs/esp32c3.conf b/samples/net/wifi/shell/socs/esp32c3.conf
index a72fdf39efa..97ce6b96475 100644
--- a/samples/net/wifi/shell/socs/esp32c3.conf
+++ b/samples/net/wifi/shell/socs/esp32c3.conf
@@ -1,11 +1 @@
-CONFIG_WIFI=y
-
-CONFIG_NETWORKING=y
-CONFIG_NET_L2_ETHERNET=y
-
-CONFIG_NET_IPV6=n
-CONFIG_NET_IPV4=y
-CONFIG_NET_DHCPV4=y
 CONFIG_ESP32_WIFI_STA_AUTO_DHCPV4=y
-
-CONFIG_NET_LOG=y
diff --git a/samples/net/wifi/shell/socs/esp32c3.overlay b/samples/net/wifi/shell/socs/esp32c3.overlay
deleted file mode 100644
index ea9865cf5f8..00000000000
--- a/samples/net/wifi/shell/socs/esp32c3.overlay
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&wifi {
-	status = "okay";
-};
diff --git a/samples/net/wifi/shell/socs/esp32c3_usb.conf b/samples/net/wifi/shell/socs/esp32c3_usb.conf
index a72fdf39efa..97ce6b96475 100644
--- a/samples/net/wifi/shell/socs/esp32c3_usb.conf
+++ b/samples/net/wifi/shell/socs/esp32c3_usb.conf
@@ -1,11 +1 @@
-CONFIG_WIFI=y
-
-CONFIG_NETWORKING=y
-CONFIG_NET_L2_ETHERNET=y
-
-CONFIG_NET_IPV6=n
-CONFIG_NET_IPV4=y
-CONFIG_NET_DHCPV4=y
 CONFIG_ESP32_WIFI_STA_AUTO_DHCPV4=y
-
-CONFIG_NET_LOG=y
diff --git a/samples/net/wifi/shell/socs/esp32c3_usb.overlay b/samples/net/wifi/shell/socs/esp32c3_usb.overlay
deleted file mode 100644
index ea9865cf5f8..00000000000
--- a/samples/net/wifi/shell/socs/esp32c3_usb.overlay
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&wifi {
-	status = "okay";
-};
diff --git a/samples/net/wifi/shell/socs/esp32c6.conf b/samples/net/wifi/shell/socs/esp32c6.conf
deleted file mode 100644
index a72fdf39efa..00000000000
--- a/samples/net/wifi/shell/socs/esp32c6.conf
+++ /dev/null
@@ -1,11 +0,0 @@
-CONFIG_WIFI=y
-
-CONFIG_NETWORKING=y
-CONFIG_NET_L2_ETHERNET=y
-
-CONFIG_NET_IPV6=n
-CONFIG_NET_IPV4=y
-CONFIG_NET_DHCPV4=y
-CONFIG_ESP32_WIFI_STA_AUTO_DHCPV4=y
-
-CONFIG_NET_LOG=y
diff --git a/samples/net/wifi/shell/socs/esp32c6_hpcore.conf b/samples/net/wifi/shell/socs/esp32c6_hpcore.conf
new file mode 100644
index 00000000000..97ce6b96475
--- /dev/null
+++ b/samples/net/wifi/shell/socs/esp32c6_hpcore.conf
@@ -0,0 +1 @@
+CONFIG_ESP32_WIFI_STA_AUTO_DHCPV4=y
diff --git a/samples/net/wifi/shell/socs/esp32s2.conf b/samples/net/wifi/shell/socs/esp32s2.conf
index da326160cb5..97ce6b96475 100644
--- a/samples/net/wifi/shell/socs/esp32s2.conf
+++ b/samples/net/wifi/shell/socs/esp32s2.conf
@@ -1,12 +1 @@
-CONFIG_WIFI=y
-
-CONFIG_NETWORKING=y
-CONFIG_NET_L2_ETHERNET=y
-
-CONFIG_NET_IPV6=n
-CONFIG_NET_IPV4=y
-CONFIG_NET_DHCPV4=y
 CONFIG_ESP32_WIFI_STA_AUTO_DHCPV4=y
-
-CONFIG_LOG_MODE_MINIMAL=y
-CONFIG_NET_LOG=y
diff --git a/samples/net/wifi/shell/socs/esp32s2.overlay b/samples/net/wifi/shell/socs/esp32s2.overlay
deleted file mode 100644
index ea9865cf5f8..00000000000
--- a/samples/net/wifi/shell/socs/esp32s2.overlay
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&wifi {
-	status = "okay";
-};
diff --git a/samples/net/wifi/shell/socs/esp32s3_procpu.conf b/samples/net/wifi/shell/socs/esp32s3_procpu.conf
index a72fdf39efa..97ce6b96475 100644
--- a/samples/net/wifi/shell/socs/esp32s3_procpu.conf
+++ b/samples/net/wifi/shell/socs/esp32s3_procpu.conf
@@ -1,11 +1 @@
-CONFIG_WIFI=y
-
-CONFIG_NETWORKING=y
-CONFIG_NET_L2_ETHERNET=y
-
-CONFIG_NET_IPV6=n
-CONFIG_NET_IPV4=y
-CONFIG_NET_DHCPV4=y
 CONFIG_ESP32_WIFI_STA_AUTO_DHCPV4=y
-
-CONFIG_NET_LOG=y
diff --git a/samples/net/wifi/shell/socs/esp32s3_procpu.overlay b/samples/net/wifi/shell/socs/esp32s3_procpu.overlay
deleted file mode 100644
index ea9865cf5f8..00000000000
--- a/samples/net/wifi/shell/socs/esp32s3_procpu.overlay
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&wifi {
-	status = "okay";
-};
diff --git a/samples/net/wifi/test_certs/rsa2k/ca.pem b/samples/net/wifi/test_certs/rsa2k/ca.pem
new file mode 100644
index 00000000000..a267be8fe47
--- /dev/null
+++ b/samples/net/wifi/test_certs/rsa2k/ca.pem
@@ -0,0 +1,29 @@
+-----BEGIN CERTIFICATE-----
+MIIE+TCCA+GgAwIBAgIUH614zvmCngpSc26BLLFu2loqvfgwDQYJKoZIhvcNAQEL
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+-----END CERTIFICATE-----
diff --git a/samples/net/wifi/test_certs/rsa2k/ca2.pem b/samples/net/wifi/test_certs/rsa2k/ca2.pem
new file mode 100644
index 00000000000..a267be8fe47
--- /dev/null
+++ b/samples/net/wifi/test_certs/rsa2k/ca2.pem
@@ -0,0 +1,29 @@
+-----BEGIN CERTIFICATE-----
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+-----END CERTIFICATE-----
diff --git a/samples/net/wifi/test_certs/rsa2k/client-key.pem b/samples/net/wifi/test_certs/rsa2k/client-key.pem
new file mode 100644
index 00000000000..4fbf52d284f
--- /dev/null
+++ b/samples/net/wifi/test_certs/rsa2k/client-key.pem
@@ -0,0 +1,30 @@
+-----BEGIN ENCRYPTED PRIVATE KEY-----
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+-----END ENCRYPTED PRIVATE KEY-----
diff --git a/samples/net/wifi/test_certs/rsa2k/client-key2.pem b/samples/net/wifi/test_certs/rsa2k/client-key2.pem
new file mode 100644
index 00000000000..4fbf52d284f
--- /dev/null
+++ b/samples/net/wifi/test_certs/rsa2k/client-key2.pem
@@ -0,0 +1,30 @@
+-----BEGIN ENCRYPTED PRIVATE KEY-----
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+D4mU9Io0mhON+5ZNhwqurQ==
+-----END ENCRYPTED PRIVATE KEY-----
diff --git a/samples/net/wifi/test_certs/rsa2k/client.pem b/samples/net/wifi/test_certs/rsa2k/client.pem
new file mode 100644
index 00000000000..33eeed9918e
--- /dev/null
+++ b/samples/net/wifi/test_certs/rsa2k/client.pem
@@ -0,0 +1,27 @@
+-----BEGIN CERTIFICATE-----
+MIIEgzCCA2ugAwIBAgIBAzANBgkqhkiG9w0BAQsFADCBkjELMAkGA1UEBhMCRlIx
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+MDWMXTRNsJMGMVOy6YWZAdvW0pj9tTN1shhYBRA3Wi8W/HrvlPtQWfrJqaTHNJ32
+sTKtziYlCg==
+-----END CERTIFICATE-----
diff --git a/samples/net/wifi/test_certs/rsa2k/client2.pem b/samples/net/wifi/test_certs/rsa2k/client2.pem
new file mode 100644
index 00000000000..33eeed9918e
--- /dev/null
+++ b/samples/net/wifi/test_certs/rsa2k/client2.pem
@@ -0,0 +1,27 @@
+-----BEGIN CERTIFICATE-----
+MIIEgzCCA2ugAwIBAgIBAzANBgkqhkiG9w0BAQsFADCBkjELMAkGA1UEBhMCRlIx
+DzANBgNVBAgMBlJhZGl1czESMBAGA1UEBwwJU29tZXdoZXJlMRQwEgYDVQQKDAtF
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+UraELVaPeSRuZLgustDtIbMdyC6yTBTfCaRHPDmgYAxVVhzR29kitMO/hoJIAt8d
+MDWMXTRNsJMGMVOy6YWZAdvW0pj9tTN1shhYBRA3Wi8W/HrvlPtQWfrJqaTHNJ32
+sTKtziYlCg==
+-----END CERTIFICATE-----
diff --git a/samples/net/wifi/test_certs/rsa2k/server-key.pem b/samples/net/wifi/test_certs/rsa2k/server-key.pem
new file mode 100644
index 00000000000..5a6a2e77e65
--- /dev/null
+++ b/samples/net/wifi/test_certs/rsa2k/server-key.pem
@@ -0,0 +1,30 @@
+-----BEGIN ENCRYPTED PRIVATE KEY-----
+MIIFHDBOBgkqhkiG9w0BBQ0wQTApBgkqhkiG9w0BBQwwHAQIZwdmrQt6RogCAggA
+MAwGCCqGSIb3DQIJBQAwFAYIKoZIhvcNAwcECHEftLym1jQkBIIEyH5UdHK2L2sR
+frTjMbkJBty0NxC8ucPqmBleZPkpAOF8XazZkfiq40/Vj9D+wTgXWL9/UNQHrY1m
+MbJvBaONODXnJe14rsL18NzN+LoUscE4poKBcrZ4Hbua5mS8mJ+WtPs9AfARyaEZ
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+PiKkcj9J5oOcIyH9PE5D9Mid7+As2kkz614J3zeCG2s9xtUkgoasiabTKZNYgL4K
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+CTIsY/ZiA5f7Gk6BL1MbRTsLqch+5pmh43gDwfbq22gPs/TwQKxx3YZJfuUy2L7A
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+gb7Ze1dOPH8Fy/hy+wGp7+gLLLTv23RRYFZZsHBCat9qTyP97vzsckvL3VQN6zWE
+3W8TB2HBVKKkszv5ov0r8/mf5k6aqSw+IYHnkXehkTcRfENUdl7X/x0LM5Hi+I5F
+ZhbtWEETZlcu8XWaIAvW3eV2AOlf0xzC1SmCYEuQ6V9dSxGNuVn4pIMzxfLDfPOw
+gqheYFzSrKZJfB/iGI7XpN2XjWo61ZKudKRxZXSVxPM1hTOqtAFiE4mKarJUTkvC
+TWKmPppA4suT1wV79CMMxWBhe4Kj4STHYSHQfUS22SqsqJbdK/1DD9u+nNANnKol
+riIOT3CiCzNDQyu627UONg==
+-----END ENCRYPTED PRIVATE KEY-----
diff --git a/samples/net/wifi/test_certs/rsa2k/server.pem b/samples/net/wifi/test_certs/rsa2k/server.pem
new file mode 100644
index 00000000000..d894c33ded1
--- /dev/null
+++ b/samples/net/wifi/test_certs/rsa2k/server.pem
@@ -0,0 +1,31 @@
+-----BEGIN CERTIFICATE-----
+MIIFaTCCBFGgAwIBAgIBATANBgkqhkiG9w0BAQsFADCBkjELMAkGA1UEBhMCRlIx
+DzANBgNVBAgMBlJhZGl1czESMBAGA1UEBwwJU29tZXdoZXJlMRQwEgYDVQQKDAtF
+eGFtcGxlIEluYzEgMB4GCSqGSIb3DQEJARYRYWRtaW5AZXhhbXBsZS5vcmcxJjAk
+BgNVBAMMHUV4YW1wbGUgQ2VydGlmaWNhdGUgQXV0aG9yaXR5MCAXDTI1MDMyNzEy
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+UmFkaXVzMRQwEgYDVQQKDAtFeGFtcGxlIEluYzEjMCEGA1UEAwwaRXhhbXBsZSBT
+ZXJ2ZXIgQ2VydGlmaWNhdGUxIDAeBgkqhkiG9w0BCQEWEWFkbWluQGV4YW1wbGUu
+b3JnMIIBIjANBgkqhkiG9w0BAQEFAAOCAQ8AMIIBCgKCAQEAxtIpRygUsyReit9O
+/15T0lf3p0ck1Sjw3ufaqaXXzEcM7i/w7UoSfNyqrjmCsZhfIDHqzWKdRUD+jE3Z
+TfRzrF/nGtyG2jjjqZy/p+0uTL0cN/QdMjUEvla/eRIgMHPPNG0oFn7GkzbrrqFt
++f3RgsWV6Anw+8ipZvd8BjsummA4W4v6A86zXgORlefU4A7JOlxHXYvhFwS044nd
+N1Fvi0bjyZ7ciKltVCxjLDJEzV7I3ttoO57TI85vtEIjMMwkGywx6ICyLbLrgycl
+OeMmArC86MFINUor3oz+mfI8ETOIfLftqVN+oPRtDqjLlrIvtaDV6PsEoiFajpdx
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+A1UdEQQzMDGCEnJhZGl1cy5leGFtcGxlLm9yZ6AbBggrBgEFBQcICKAPDA0qLmV4
+YW1wbGUuY29tMA0GCSqGSIb3DQEBCwUAA4IBAQAov9HxapiYtoAUebNdGU6hFz7G
+3F6Jtpg5d34/AW1ntmgxHryNn5dJp/fmc3eyndMLQRJhDIksc/6Tmp0jUs6DhxE5
+5BmdAPVsAPhYfr3ylOoOP21wtmaH4MeRtBYuBsdvLgyiIXMWrliQnJa+12ovdqMX
++9KJJLWJm81IH6O2kEZ7HmoWkY6XXYpJZqw3c8FukuUoFQQk2mJ4u2yncq4oFQSn
+uu5G4UL8o3blhkY1pK8WmuzUiafyJjjlwBcsBkk47BuKbyQCquOXl/O+lzteJMEZ
+Z83ZANWQb7g1vhIVvse5qLZ9Osa68TJFDaHWcmIyFutbyfdAJy4XEGawf1Fq
+-----END CERTIFICATE-----
diff --git a/samples/net/wifi/test_certs/ca.pem b/samples/net/wifi/test_certs/rsa3k/ca.pem
similarity index 100%
rename from samples/net/wifi/test_certs/ca.pem
rename to samples/net/wifi/test_certs/rsa3k/ca.pem
diff --git a/samples/net/wifi/test_certs/ca2.pem b/samples/net/wifi/test_certs/rsa3k/ca2.pem
similarity index 100%
rename from samples/net/wifi/test_certs/ca2.pem
rename to samples/net/wifi/test_certs/rsa3k/ca2.pem
diff --git a/samples/net/wifi/test_certs/client-key.pem b/samples/net/wifi/test_certs/rsa3k/client-key.pem
similarity index 100%
rename from samples/net/wifi/test_certs/client-key.pem
rename to samples/net/wifi/test_certs/rsa3k/client-key.pem
diff --git a/samples/net/wifi/test_certs/client-key2.pem b/samples/net/wifi/test_certs/rsa3k/client-key2.pem
similarity index 100%
rename from samples/net/wifi/test_certs/client-key2.pem
rename to samples/net/wifi/test_certs/rsa3k/client-key2.pem
diff --git a/samples/net/wifi/test_certs/client.pem b/samples/net/wifi/test_certs/rsa3k/client.pem
similarity index 100%
rename from samples/net/wifi/test_certs/client.pem
rename to samples/net/wifi/test_certs/rsa3k/client.pem
diff --git a/samples/net/wifi/test_certs/client2.pem b/samples/net/wifi/test_certs/rsa3k/client2.pem
similarity index 100%
rename from samples/net/wifi/test_certs/client2.pem
rename to samples/net/wifi/test_certs/rsa3k/client2.pem
diff --git a/samples/net/wifi/test_certs/server-key.pem b/samples/net/wifi/test_certs/rsa3k/server-key.pem
similarity index 100%
rename from samples/net/wifi/test_certs/server-key.pem
rename to samples/net/wifi/test_certs/rsa3k/server-key.pem
diff --git a/samples/net/wifi/test_certs/server.pem b/samples/net/wifi/test_certs/rsa3k/server.pem
similarity index 100%
rename from samples/net/wifi/test_certs/server.pem
rename to samples/net/wifi/test_certs/rsa3k/server.pem
diff --git a/samples/net/wpan_serial/sample.yaml b/samples/net/wpan_serial/sample.yaml
index 78c8c9c517b..2a17bf5d62c 100644
--- a/samples/net/wpan_serial/sample.yaml
+++ b/samples/net/wpan_serial/sample.yaml
@@ -15,6 +15,8 @@ tests:
       - thingy53/nrf5340/cpuapp/ns
       - raytac_mdbt53_db_40/nrf5340/cpuapp/ns
       - raytac_mdbt53_db_40/nrf5340/cpuapp
+    integration_platforms:
+      - usb_kw24d512
   sample.net.wpan_serial.frdm_cr20a:
     extra_args: SHIELD=frdm_cr20a
     platform_allow: frdm_k64f
diff --git a/samples/net/zperf/Kconfig b/samples/net/zperf/Kconfig
index 795613f1a49..a476a9fec3f 100644
--- a/samples/net/zperf/Kconfig
+++ b/samples/net/zperf/Kconfig
@@ -1,8 +1,6 @@
 # Copyright 2023 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-source "Kconfig.zephyr"
-
 config NET_SAMPLE_CODE_RELOCATE
 	bool "Relocate networking code into RAM"
 	select CODE_DATA_RELOCATION
@@ -27,3 +25,9 @@ if USB_DEVICE_STACK_NEXT
 # tree, you cannot use them in your own application.
 	source "samples/subsys/usb/common/Kconfig.sample_usbd"
 endif
+
+configdefault NRF_WIFI_DATA_HEAP_SIZE
+	default 30000 if NRF_WIFI_ZERO_COPY_TX
+	default 50000
+
+source "Kconfig.zephyr"
diff --git a/samples/net/zperf/README.rst b/samples/net/zperf/README.rst
index 79ea582e1a4..165cdc0b437 100644
--- a/samples/net/zperf/README.rst
+++ b/samples/net/zperf/README.rst
@@ -13,13 +13,8 @@ allows to evaluate network bandwidth.
 Features
 *********
 
-- Compatible with iPerf_2.0.5. Note that in newer iPerf versions,
-  an error message like this is printed and the server reported statistics
-  are missing.
-
-.. code-block:: console
-
-   LAST PACKET NOT RECEIVED!!!
+- Compatible with iPerf v2.0.10 and newer. For older versions, enable
+  :kconfig:option:`CONFIG_NET_ZPERF_LEGACY_HEADER_COMPAT`.
 
 - Client or server mode allowed without need to modify the source code.
 
@@ -50,7 +45,7 @@ sample does not fit into target platform RAM, reduce the following configs:
 Requirements
 ************
 
-- iPerf 2.0.5 installed on the host machine
+- iPerf 2.0.10 or newer installed on the host machine
 - Supported board
 
 Depending on the network technology chosen, extra steps may be required
diff --git a/samples/net/zperf/boards/frdm_rw612.conf b/samples/net/zperf/boards/frdm_rw612.conf
new file mode 100644
index 00000000000..70aa6c94b27
--- /dev/null
+++ b/samples/net/zperf/boards/frdm_rw612.conf
@@ -0,0 +1,15 @@
+CONFIG_WIFI_NXP=y
+CONFIG_NXP_RW610=y
+CONFIG_NXP_WIFI_SHELL=y
+
+CONFIG_WIFI_NM_WPA_SUPPLICANT=y
+
+# stack size
+CONFIG_SHELL_STACK_SIZE=6144
+CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=2048
+CONFIG_NET_MGMT_EVENT_STACK_SIZE=4608
+CONFIG_NET_TCP_WORKQ_STACK_SIZE=2048
+CONFIG_MAIN_STACK_SIZE=4096
+CONFIG_NET_SOCKETS_SERVICE_STACK_SIZE=4096
+CONFIG_WIFI_NM_WPA_SUPPLICANT_WQ_STACK_SIZE=12288
+CONFIG_WIFI_NM_WPA_SUPPLICANT_THREAD_STACK_SIZE=12288
diff --git a/samples/net/zperf/boards/mimxrt1050_evk.conf b/samples/net/zperf/boards/mimxrt1050_evk_mimxrt1052_hyperflash.conf
similarity index 100%
rename from samples/net/zperf/boards/mimxrt1050_evk.conf
rename to samples/net/zperf/boards/mimxrt1050_evk_mimxrt1052_hyperflash.conf
diff --git a/samples/net/zperf/boards/mimxrt1060_evk.conf b/samples/net/zperf/boards/mimxrt1060_evk_mimxrt1062_qspi.conf
similarity index 100%
rename from samples/net/zperf/boards/mimxrt1060_evk.conf
rename to samples/net/zperf/boards/mimxrt1060_evk_mimxrt1062_qspi.conf
diff --git a/samples/net/zperf/boards/native_posix.conf b/samples/net/zperf/boards/native_posix.conf
deleted file mode 100644
index eb56d825c96..00000000000
--- a/samples/net/zperf/boards/native_posix.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME=y
diff --git a/samples/net/zperf/boards/nrf7002dk_nrf5340_cpuapp.conf b/samples/net/zperf/boards/nrf7002dk_nrf5340_cpuapp.conf
index 2b7f5e48de1..8907ee8fbbd 100644
--- a/samples/net/zperf/boards/nrf7002dk_nrf5340_cpuapp.conf
+++ b/samples/net/zperf/boards/nrf7002dk_nrf5340_cpuapp.conf
@@ -4,7 +4,6 @@ CONFIG_NET_PKT_TX_COUNT=28
 CONFIG_NET_BUF_RX_COUNT=28
 CONFIG_NET_BUF_TX_COUNT=28
 CONFIG_NRF70_RX_NUM_BUFS=16
-CONFIG_NRF_WIFI_DATA_HEAP_SIZE=30000
 CONFIG_NET_PKT_BUF_TX_DATA_POOL_SIZE=20000
 CONFIG_NRF70_MAX_TX_AGGREGATION=4
 CONFIG_NRF70_QSPI_LOW_POWER=n
diff --git a/samples/net/zperf/prj.conf b/samples/net/zperf/prj.conf
index 91d46d763f9..ff9674fa7e5 100644
--- a/samples/net/zperf/prj.conf
+++ b/samples/net/zperf/prj.conf
@@ -1,5 +1,6 @@
 CONFIG_NETWORKING=y
 CONFIG_NET_ZPERF=y
+CONFIG_NET_ZPERF_SERVER=y
 CONFIG_NET_LOG=y
 CONFIG_NET_IPV6=y
 CONFIG_NET_IPV4=y
diff --git a/samples/net/zperf/sample.yaml b/samples/net/zperf/sample.yaml
index 7dbb0cb8acf..c97e239ff6b 100644
--- a/samples/net/zperf/sample.yaml
+++ b/samples/net/zperf/sample.yaml
@@ -2,10 +2,7 @@ common:
   tags:
     - net
     - zperf
-  # TODO: Does not work properly with native_posix, need more TLC
   platform_exclude:
-    - native_posix
-    - native_posix/native/64
     - sam_e70_xplained/same70q21
   min_ram: 64
 sample:
@@ -15,6 +12,11 @@ tests:
   sample.net.zperf:
     harness: net
     platform_allow: qemu_x86
+  sample.net.zperf_no_server:
+    harness: net
+    platform_allow: qemu_x86
+    extra_configs:
+      - CONFIG_NET_ZPERF_SERVER=n
   sample.net.zperf_st:
     harness: console
     harness_config:
@@ -34,6 +36,11 @@ tests:
     extra_configs:
       - CONFIG_NET_SHELL=n
     platform_allow: qemu_x86
+  sample.net.zperf_concurrent_upload:
+    harness: net
+    extra_configs:
+      - CONFIG_ZPERF_SESSION_PER_THREAD=y
+    platform_allow: qemu_x86
   sample.net.zperf.netusb_ecm:
     harness: net
     extra_args: EXTRA_CONF_FILE="overlay-netusb.conf"
diff --git a/samples/philosophers/src/main.c b/samples/philosophers/src/main.c
index 493d11dc5e1..ddda605d5d2 100644
--- a/samples/philosophers/src/main.c
+++ b/samples/philosophers/src/main.c
@@ -147,7 +147,7 @@ void philosopher(void *id, void *unused1, void *unused2)
 
 	int my_id = POINTER_TO_INT(id);
 
-	/* Djkstra's solution: always pick up the lowest numbered fork first */
+	/* Dijkstra's solution: always pick up the lowest numbered fork first */
 	if (is_last_philosopher(my_id)) {
 		my_fork1 = fork(0);
 		my_fork2 = fork(my_id);
diff --git a/samples/posix/env/sample.yaml b/samples/posix/env/sample.yaml
index 7cca65b292e..756b914dcc8 100644
--- a/samples/posix/env/sample.yaml
+++ b/samples/posix/env/sample.yaml
@@ -5,9 +5,6 @@ common:
   tags:
     - posix
     - env
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
   integration_platforms:
     - native_sim
   harness: console
diff --git a/samples/posix/gettimeofday/sample.yaml b/samples/posix/gettimeofday/sample.yaml
index 88748aab2a6..a71d29f09c5 100644
--- a/samples/posix/gettimeofday/sample.yaml
+++ b/samples/posix/gettimeofday/sample.yaml
@@ -10,9 +10,6 @@ common:
   tags:
     - posix
     - net
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   sample.posix.gettimeofday:
     harness: net
diff --git a/samples/posix/uname/sample.yaml b/samples/posix/uname/sample.yaml
index 6b0b0817c16..d65596b72a3 100644
--- a/samples/posix/uname/sample.yaml
+++ b/samples/posix/uname/sample.yaml
@@ -3,9 +3,6 @@ sample:
   name: posix uname
 common:
   tags: posix
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
   integration_platforms:
     - native_sim
     - qemu_riscv64
diff --git a/samples/psa/its/overlay-secure_storage.conf b/samples/psa/its/overlay-secure_storage.conf
index 3473ae38910..9265b38ccc7 100644
--- a/samples/psa/its/overlay-secure_storage.conf
+++ b/samples/psa/its/overlay-secure_storage.conf
@@ -8,3 +8,9 @@ CONFIG_MBEDTLS_PSA_CRYPTO_C=y
 CONFIG_MAIN_STACK_SIZE=3072
 
 CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_SETTINGS=y
+CONFIG_SETTINGS=y
+CONFIG_SETTINGS_NVS=y
+CONFIG_NVS=y
+CONFIG_FLASH=y
+CONFIG_FLASH_MAP=y
diff --git a/samples/psa/persistent_key/overlay-secure_storage.conf b/samples/psa/persistent_key/overlay-secure_storage.conf
index 7c1d782c4c2..c5cff5f364a 100644
--- a/samples/psa/persistent_key/overlay-secure_storage.conf
+++ b/samples/psa/persistent_key/overlay-secure_storage.conf
@@ -10,3 +10,9 @@ CONFIG_MBEDTLS_HEAP_SIZE=1024
 CONFIG_MAIN_STACK_SIZE=3072
 
 CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_SETTINGS=y
+CONFIG_SETTINGS=y
+CONFIG_SETTINGS_NVS=y
+CONFIG_NVS=y
+CONFIG_FLASH=y
+CONFIG_FLASH_MAP=y
diff --git a/samples/sensor/6dof_motion_drdy/prj.conf b/samples/sensor/6dof_motion_drdy/prj.conf
index 30d93977483..7731b5b6de1 100644
--- a/samples/sensor/6dof_motion_drdy/prj.conf
+++ b/samples/sensor/6dof_motion_drdy/prj.conf
@@ -16,4 +16,4 @@ CONFIG_CBPRINTF_FP_SUPPORT=y
 CONFIG_USE_SEGGER_RTT=n
 
 # Trigger mode: sample is using interrupt triggering
-CONFIG_ICM42670_TRIGGER_OWN_THREAD=y
+CONFIG_ICM42X70_TRIGGER_OWN_THREAD=y
diff --git a/samples/sensor/accel_polling/sample.yaml b/samples/sensor/accel_polling/sample.yaml
index b4752dfcff3..74c5f07f5ba 100644
--- a/samples/sensor/accel_polling/sample.yaml
+++ b/samples/sensor/accel_polling/sample.yaml
@@ -1,15 +1,16 @@
 sample:
   name: Accelerometer polling sample
+common:
+  tags: sensors
+  harness: console
+  harness_config:
+    type: one_line
+    regex:
+      - "^\\s*[0-9A-Za-z_,+-.]*@[0-9A-Fa-f]* \\[m\/s\\^2\\]:    \
+         \\(\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*\\)$"
 tests:
   sample.sensor.accel_polling:
-    harness: console
-    tags: sensors
     filter: dt_alias_exists("accel0")
-    harness_config:
-      type: one_line
-      regex:
-        - "^\\s*[0-9A-Za-z_,+-.]*@[0-9A-Fa-f]* \\[m\/s\\^2\\]:    \
-           \\(\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*\\)$"
     integration_platforms:
       - cc1352r_sensortag               # adxl362
       - blueclover_plt_demo_v2/nrf52832 # bmi270
@@ -27,13 +28,6 @@ tests:
       - sensortile_box                  # lis2dw12, lsm6dso, iisdhhc
       - thingy53/nrf5340/cpuapp         # adxl362, bmi270
   sample.sensor.accel_polling.adxl362-stream:
-    harness: console
-    tags: sensors
-    harness_config:
-      type: one_line
-      regex:
-        - "^\\s*[0-9A-Za-z_,+-.]*@[0-9A-Fa-f]* \\[m\/s\\^2\\]:    \
-           \\(\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*\\)$"
     extra_args:
       - SHIELD=eval_adxl362_ardz
       - EXTRA_CONF_FILE=adxl362-stream.conf
diff --git a/samples/sensor/accel_trig/Kconfig b/samples/sensor/accel_trig/Kconfig
new file mode 100644
index 00000000000..ec0fa9d253e
--- /dev/null
+++ b/samples/sensor/accel_trig/Kconfig
@@ -0,0 +1,13 @@
+#
+#  Copyright (c) 2025 Pierrick Curt
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+mainmenu "Accelerometer trigger sample application"
+
+config SAMPLE_TAP_DETECTION
+	bool "Set tap detection as trigger in the sample"
+	default n
+
+source "Kconfig.zephyr"
diff --git a/samples/sensor/accel_trig/README.rst b/samples/sensor/accel_trig/README.rst
index 37a3f18e8c8..29b952a6847 100644
--- a/samples/sensor/accel_trig/README.rst
+++ b/samples/sensor/accel_trig/README.rst
@@ -7,6 +7,10 @@ Overview
 ********
 
 This sample application demonstrates how to use 3-Axis accelerometers with triggers.
+By default it uses a data ready trigger to read the accelerometer data and print it to the console.
+
+If the accelerometer is enabled with a tap trigger, the sample uses the tap trigger event to
+read the accelerometer data and print it to the console.
 
 Building and Running
 ********************
@@ -27,8 +31,22 @@ Make sure the aliases are in devicetree, then build and run with:
    :goals: build flash
    :compact:
 
-Sample Output
-=============
+With this example, you can also detect a double tap with an accelerometer by activating the
+:kconfig:option:`CONFIG_SAMPLE_TAP_DETECTION`.
+In this example we use a x_nucleo_iks01a3 shield with a LIS2DW12 accelerometer.
+You can build it with the following command:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/sensor/accel_trig
+   :board: nrf52dk/nrf52832
+   :shield: x_nucleo_iks01a3
+   :goals: build
+   :west-args: --extra-dtc-overlay x_nucleo_iks01a3.overlay
+   :compact:
+
+
+Sample Output (SENSOR_TRIG_DATA_READY)
+=======================================
 
 .. code-block:: console
 
@@ -43,3 +61,28 @@ Sample Output
      fxos8700@1d [m/s^2]:    (   -0.105345,    -0.028731,     9.921571)
      fxos8700@1d [m/s^2]:    (   -0.095769,    -0.028731,     9.931148)
      fxos8700@1d [m/s^2]:    (   -0.095769,    -0.009577,     9.940725)
+
+
+Sample Output (SENSOR_TRIG_DOUBLE_TAP)
+======================================
+
+.. code-block:: console
+
+  TAP detected
+     lis2dw12@19 [m/s^2]:    (   -1.899901,   -12.550355,    -2.742174)
+  TAP detected
+     lis2dw12@19 [m/s^2]:    (   12.349357,   -18.125630,     6.015556)
+  TAP detected
+     lis2dw12@19 [m/s^2]:    (  -11.385050,    -7.274181,    -9.229117)
+  TAP detected
+     lis2dw12@19 [m/s^2]:    (    9.214760,    -9.286545,     2.311466)
+  TAP detected
+     lis2dw12@19 [m/s^2]:    (   10.090533,   -17.391034,    12.320643)
+  TAP detected
+     lis2dw12@19 [m/s^2]:    (   -0.478564,     2.390429,    15.876378)
+  TAP detected
+     lis2dw12@19 [m/s^2]:    (   -5.668596,   -13.138989,     0.741775)
+  TAP detected
+     lis2dw12@19 [m/s^2]:    (   -2.385644,   -10.559526,     9.899107)
+  TAP detected
+     lis2dw12@19 [m/s^2]:    (    7.537391,    -8.551948,    16.740187)
diff --git a/samples/sensor/accel_trig/boards/frdm_k82f.conf b/samples/sensor/accel_trig/boards/frdm_k82f.conf
new file mode 100644
index 00000000000..ebcb58d5b54
--- /dev/null
+++ b/samples/sensor/accel_trig/boards/frdm_k82f.conf
@@ -0,0 +1,2 @@
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
+CONFIG_FXOS8700_MODE_ACCEL=y
diff --git a/samples/sensor/accel_trig/boards/frdm_kl25z.conf b/samples/sensor/accel_trig/boards/frdm_kl25z.conf
new file mode 100644
index 00000000000..ebcb58d5b54
--- /dev/null
+++ b/samples/sensor/accel_trig/boards/frdm_kl25z.conf
@@ -0,0 +1,2 @@
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
+CONFIG_FXOS8700_MODE_ACCEL=y
diff --git a/samples/sensor/accel_trig/boards/frdm_kw41z.conf b/samples/sensor/accel_trig/boards/frdm_kw41z.conf
new file mode 100644
index 00000000000..ebcb58d5b54
--- /dev/null
+++ b/samples/sensor/accel_trig/boards/frdm_kw41z.conf
@@ -0,0 +1,2 @@
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
+CONFIG_FXOS8700_MODE_ACCEL=y
diff --git a/samples/sensor/accel_trig/boards/frdm_mcxc242.conf b/samples/sensor/accel_trig/boards/frdm_mcxc242.conf
new file mode 100644
index 00000000000..9dc813d038c
--- /dev/null
+++ b/samples/sensor/accel_trig/boards/frdm_mcxc242.conf
@@ -0,0 +1 @@
+CONFIG_FXLS8974_TRIGGER_OWN_THREAD=y
diff --git a/samples/sensor/accel_trig/boards/lpcxpresso55s28.conf b/samples/sensor/accel_trig/boards/lpcxpresso55s28.conf
new file mode 100644
index 00000000000..ebcb58d5b54
--- /dev/null
+++ b/samples/sensor/accel_trig/boards/lpcxpresso55s28.conf
@@ -0,0 +1,2 @@
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
+CONFIG_FXOS8700_MODE_ACCEL=y
diff --git a/samples/sensor/accel_trig/boards/lpcxpresso55s69_lpc55s69_cpu0.conf b/samples/sensor/accel_trig/boards/lpcxpresso55s69_lpc55s69_cpu0.conf
new file mode 100644
index 00000000000..ebcb58d5b54
--- /dev/null
+++ b/samples/sensor/accel_trig/boards/lpcxpresso55s69_lpc55s69_cpu0.conf
@@ -0,0 +1,2 @@
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
+CONFIG_FXOS8700_MODE_ACCEL=y
diff --git a/samples/sensor/accel_trig/boards/mimxrt1040_evk.conf b/samples/sensor/accel_trig/boards/mimxrt1040_evk.conf
new file mode 100644
index 00000000000..9dc813d038c
--- /dev/null
+++ b/samples/sensor/accel_trig/boards/mimxrt1040_evk.conf
@@ -0,0 +1 @@
+CONFIG_FXLS8974_TRIGGER_OWN_THREAD=y
diff --git a/samples/sensor/accel_trig/boards/mimxrt1040_evk.overlay b/samples/sensor/accel_trig/boards/mimxrt1040_evk.overlay
new file mode 100644
index 00000000000..56ec2a98c5b
--- /dev/null
+++ b/samples/sensor/accel_trig/boards/mimxrt1040_evk.overlay
@@ -0,0 +1,12 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright 2025 NXP
+ */
+
+
+&fxls8974 {
+	status = "okay";
+	int1-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+	int2-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
+};
diff --git a/samples/sensor/accel_trig/boards/mimxrt1050_evk_mimxrt1052_hyperflash.conf b/samples/sensor/accel_trig/boards/mimxrt1050_evk_mimxrt1052_hyperflash.conf
new file mode 100644
index 00000000000..ebcb58d5b54
--- /dev/null
+++ b/samples/sensor/accel_trig/boards/mimxrt1050_evk_mimxrt1052_hyperflash.conf
@@ -0,0 +1,2 @@
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
+CONFIG_FXOS8700_MODE_ACCEL=y
diff --git a/samples/sensor/accel_trig/boards/mimxrt1160_evk_mimxrt1166_cm7.conf b/samples/sensor/accel_trig/boards/mimxrt1160_evk_mimxrt1166_cm7.conf
new file mode 100644
index 00000000000..e3dadc69fc7
--- /dev/null
+++ b/samples/sensor/accel_trig/boards/mimxrt1160_evk_mimxrt1166_cm7.conf
@@ -0,0 +1,6 @@
+#
+# check the fxos8700 dts for this board for addition settings
+#
+
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
+CONFIG_FXOS8700_MODE_ACCEL=y
diff --git a/samples/sensor/accel_trig/boards/mimxrt1170_evk@A_mimxrt1176_cm7.conf b/samples/sensor/accel_trig/boards/mimxrt1170_evk@A_mimxrt1176_cm7.conf
new file mode 100644
index 00000000000..e3dadc69fc7
--- /dev/null
+++ b/samples/sensor/accel_trig/boards/mimxrt1170_evk@A_mimxrt1176_cm7.conf
@@ -0,0 +1,6 @@
+#
+# check the fxos8700 dts for this board for addition settings
+#
+
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
+CONFIG_FXOS8700_MODE_ACCEL=y
diff --git a/samples/sensor/accel_trig/boards/mimxrt595_evk_mimxrt595s_cm33.conf b/samples/sensor/accel_trig/boards/mimxrt595_evk_mimxrt595s_cm33.conf
new file mode 100644
index 00000000000..ebcb58d5b54
--- /dev/null
+++ b/samples/sensor/accel_trig/boards/mimxrt595_evk_mimxrt595s_cm33.conf
@@ -0,0 +1,2 @@
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
+CONFIG_FXOS8700_MODE_ACCEL=y
diff --git a/samples/sensor/accel_trig/boards/mimxrt685_evk_mimxrt685s_cm33.conf b/samples/sensor/accel_trig/boards/mimxrt685_evk_mimxrt685s_cm33.conf
new file mode 100644
index 00000000000..ebcb58d5b54
--- /dev/null
+++ b/samples/sensor/accel_trig/boards/mimxrt685_evk_mimxrt685s_cm33.conf
@@ -0,0 +1,2 @@
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
+CONFIG_FXOS8700_MODE_ACCEL=y
diff --git a/samples/sensor/accel_trig/boards/stm32f3_disco.conf b/samples/sensor/accel_trig/boards/stm32f3_disco.conf
new file mode 100644
index 00000000000..67dc73ec342
--- /dev/null
+++ b/samples/sensor/accel_trig/boards/stm32f3_disco.conf
@@ -0,0 +1,4 @@
+CONFIG_I2C=y
+CONFIG_SENSOR_LOG_LEVEL_DBG=y
+CONFIG_LIS2DW12_TRIGGER_GLOBAL_THREAD=y
+CONFIG_LIS2DW12_TAP=y
diff --git a/samples/sensor/accel_trig/boards/stm32f3_disco.overlay b/samples/sensor/accel_trig/boards/stm32f3_disco.overlay
new file mode 100644
index 00000000000..79d5a106a88
--- /dev/null
+++ b/samples/sensor/accel_trig/boards/stm32f3_disco.overlay
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2024, Pierrick Curt.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/sensor/lis2dw12.h>
+
+/ {
+	aliases {
+		accel0 = &lis2dw12_accel;
+	};
+};
+
+&i2c2 {
+	pinctrl-0 = <&i2c2_scl_pa9 &i2c2_sda_pa10>;
+	pinctrl-names = "default";
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+
+	lis2dw12_accel: lis2dw12@19 {
+		compatible = "st,lis2dw12";
+		reg = <0x19>;
+		odr = <400>;
+		tap-mode = <LIS2DW12_DT_SINGLE_DOUBLE_TAP>;
+		tap-threshold = <12>, <12>, <12>;
+		power-mode = <LIS2DW12_DT_HP_MODE>;
+		tap-shock = <0x03>;
+		tap-quiet = <0x03>;
+		tap-latency = <0x03>;
+		irq-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>;
+	};
+};
diff --git a/samples/sensor/accel_trig/boards/twr_ke18f.conf b/samples/sensor/accel_trig/boards/twr_ke18f.conf
new file mode 100644
index 00000000000..ebcb58d5b54
--- /dev/null
+++ b/samples/sensor/accel_trig/boards/twr_ke18f.conf
@@ -0,0 +1,2 @@
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
+CONFIG_FXOS8700_MODE_ACCEL=y
diff --git a/samples/sensor/accel_trig/boards/twr_ke18f.overlay b/samples/sensor/accel_trig/boards/twr_ke18f.overlay
new file mode 100644
index 00000000000..4f82667c80b
--- /dev/null
+++ b/samples/sensor/accel_trig/boards/twr_ke18f.overlay
@@ -0,0 +1,11 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright 2025 NXP
+ */
+
+&fxos8700 {
+	status = "okay";
+	int1-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
+	int2-gpios = <&gpioa 17 GPIO_ACTIVE_LOW>;
+};
diff --git a/samples/sensor/accel_trig/boards/twr_kv58f220m.conf b/samples/sensor/accel_trig/boards/twr_kv58f220m.conf
new file mode 100644
index 00000000000..ebcb58d5b54
--- /dev/null
+++ b/samples/sensor/accel_trig/boards/twr_kv58f220m.conf
@@ -0,0 +1,2 @@
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
+CONFIG_FXOS8700_MODE_ACCEL=y
diff --git a/samples/sensor/accel_trig/sample.yaml b/samples/sensor/accel_trig/sample.yaml
index 9392668a5e0..31b7ddfbb72 100644
--- a/samples/sensor/accel_trig/sample.yaml
+++ b/samples/sensor/accel_trig/sample.yaml
@@ -1,15 +1,18 @@
 sample:
   name: Accelerometer trigger sample
+common:
+  tags: sensors
+  harness: console
+  harness_config:
+    type: one_line
+    regex:
+      - "^\\s*[0-9A-Za-z_,+-.]*@[0-9A-Fa-f]* \\[m\/s\\^2\\]:    \
+        \\(\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*\\)$"
 tests:
   sample.sensor.accel_trig:
-    harness: console
-    tags: sensors
     filter: dt_alias_exists("accel0")
     harness_config:
-      type: one_line
-      regex:
-        - "^\\s*[0-9A-Za-z_,+-.]*@[0-9A-Fa-f]* \\[m\/s\\^2\\]:    \
-          \\(\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*\\)$"
+      fixture: fixture_sensor_accel_int
     integration_platforms:
       - frdm_k64f                       # fxos8700
     platform_exclude:
@@ -21,16 +24,28 @@ tests:
       - stm32l562e_dk
       - stm32wb5mm_dk
   sample.sensor.accel_trig.adxl362-trigger:
-    harness: console
-    tags: sensors
-    harness_config:
-      type: one_line
-      regex:
-        - "^\\s*[0-9A-Za-z_,+-.]*@[0-9A-Fa-f]* \\[m\/s\\^2\\]:    \
-          \\(\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*\\)$"
     extra_args:
       - SHIELD=eval_adxl362_ardz
       - EXTRA_CONF_FILE=adxl362-trigger.conf
       - SNIPPET=rtt-tracing;rtt-console
     platform_allow:
       - apard32690/max32690/m4
+  sample.sensor.accel_trig.shield-tap:
+    extra_args:
+      - SHIELD=x_nucleo_iks01a3
+      - EXTRA_DTC_OVERLAY_FILE=x_nucleo_iks01a3.overlay
+      - CONFIG_SAMPLE_TAP_DETECTION=y
+    depends_on:
+      - arduino_i2c
+      - arduino_gpio
+    platform_allow:
+      - nrf52dk/nrf52832
+    integration_platforms:
+      - nrf52dk/nrf52832
+  sample.sensor.accel_trig.generic-tap:
+    filter: dt_compat_enabled("nxp,fxos8700") or dt_compat_enabled("invensense,icm42605") or
+            dt_compat_enabled("st,iis2dlpc") or dt_compat_enabled("st,lis2dw12")
+    extra_args:
+      - CONFIG_SAMPLE_TAP_DETECTION=y
+    integration_platforms:
+      - stm32f3_disco
diff --git a/samples/sensor/accel_trig/src/main.c b/samples/sensor/accel_trig/src/main.c
index e5ddde1e2be..6f56cc1e9d5 100644
--- a/samples/sensor/accel_trig/src/main.c
+++ b/samples/sensor/accel_trig/src/main.c
@@ -11,6 +11,19 @@
 
 K_SEM_DEFINE(sem, 0, 1); /* starts off "not available" */
 
+#ifdef CONFIG_SAMPLE_TAP_DETECTION
+static void tap_trigger_handler(const struct device *dev, const struct sensor_trigger *trigger)
+{
+	ARG_UNUSED(trigger);
+	printf("TAP detected\n");
+
+	if (sensor_sample_fetch_chan(dev, SENSOR_CHAN_ACCEL_XYZ) < 0) {
+		printf("ERROR: SENSOR_CHAN_ACCEL_XYZ fetch failed\n");
+	}
+
+	k_sem_give(&sem);
+}
+#else
 static void trigger_handler(const struct device *dev, const struct sensor_trigger *trigger)
 {
 	ARG_UNUSED(trigger);
@@ -25,6 +38,7 @@ static void trigger_handler(const struct device *dev, const struct sensor_trigge
 
 	k_sem_give(&sem);
 }
+#endif
 
 int main(void)
 {
@@ -41,10 +55,19 @@ int main(void)
 		return 0;
 	}
 
+#ifdef CONFIG_SAMPLE_TAP_DETECTION
+	trig.type = SENSOR_TRIG_DOUBLE_TAP;
+	trig.chan = SENSOR_CHAN_ACCEL_XYZ;
+	if (sensor_trigger_set(dev, &trig, tap_trigger_handler) < 0) {
+		printf("Could not set tap trigger\n");
+		return 0;
+	}
+#else
 	if (sensor_trigger_set(dev, &trig, trigger_handler)) {
 		printf("Could not set trigger\n");
 		return 0;
 	}
+#endif
 
 	while (1) {
 		k_sem_take(&sem, K_FOREVER);
diff --git a/samples/sensor/accel_trig/x_nucleo_iks01a3.overlay b/samples/sensor/accel_trig/x_nucleo_iks01a3.overlay
new file mode 100644
index 00000000000..f33cce20221
--- /dev/null
+++ b/samples/sensor/accel_trig/x_nucleo_iks01a3.overlay
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025 Pierrick Curt
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/dt-bindings/sensor/lis2dw12.h>
+
+&lis2dw12_19_x_nucleo_iks01a3 {
+	status = "okay";
+	compatible = "st,lis2dw12";
+	reg = <0x19>;
+	odr = <400>;
+	tap-mode = <LIS2DW12_DT_SINGLE_DOUBLE_TAP>;
+	tap-threshold = <12>, <12>, <12>;
+	power-mode = <LIS2DW12_DT_HP_MODE>;
+	tap-shock = <0x03>;
+	tap-quiet = <0x03>;
+	tap-latency = <0x03>;
+	irq-gpios =  <&arduino_header 3 GPIO_ACTIVE_HIGH>; /* A3 */
+};
diff --git a/samples/sensor/adt7420/README.rst b/samples/sensor/adt7420/README.rst
index 7900a15df95..02ccc01c2ae 100644
--- a/samples/sensor/adt7420/README.rst
+++ b/samples/sensor/adt7420/README.rst
@@ -37,7 +37,7 @@ Building and Running
 This project outputs sensor data to the console. It requires an ADT7420
 sensor. It should work with any platform featuring a I2C peripheral interface.
 It does not work on QEMU.
-In this example below the :ref:`nrf52dk_nrf52832` board is used.
+In this example below the :zephyr:board:`nrf52dk` board is used.
 
 
 .. zephyr-app-commands::
diff --git a/samples/sensor/bme280/boards/adafruit_feather_esp32s2.overlay b/samples/sensor/bme280/boards/adafruit_feather_esp32s2.overlay
new file mode 100644
index 00000000000..7259b070ebb
--- /dev/null
+++ b/samples/sensor/bme280/boards/adafruit_feather_esp32s2.overlay
@@ -0,0 +1,6 @@
+&i2c0 {
+	bme280: bme280@77 {
+		compatible = "bosch,bme280";
+		reg = <0x77>;
+	};
+};
diff --git a/samples/sensor/bme280/boards/adafruit_feather_esp32s2_tft.overlay b/samples/sensor/bme280/boards/adafruit_feather_esp32s2_tft.overlay
new file mode 100644
index 00000000000..7259b070ebb
--- /dev/null
+++ b/samples/sensor/bme280/boards/adafruit_feather_esp32s2_tft.overlay
@@ -0,0 +1,6 @@
+&i2c0 {
+	bme280: bme280@77 {
+		compatible = "bosch,bme280";
+		reg = <0x77>;
+	};
+};
diff --git a/samples/sensor/bme280/boards/adafruit_feather_esp32s2_tft_reverse.overlay b/samples/sensor/bme280/boards/adafruit_feather_esp32s2_tft_reverse.overlay
new file mode 100644
index 00000000000..7259b070ebb
--- /dev/null
+++ b/samples/sensor/bme280/boards/adafruit_feather_esp32s2_tft_reverse.overlay
@@ -0,0 +1,6 @@
+&i2c0 {
+	bme280: bme280@77 {
+		compatible = "bosch,bme280";
+		reg = <0x77>;
+	};
+};
diff --git a/samples/sensor/bme280/sample.yaml b/samples/sensor/bme280/sample.yaml
index 2e84cd1af03..94b7ebf4afa 100644
--- a/samples/sensor/bme280/sample.yaml
+++ b/samples/sensor/bme280/sample.yaml
@@ -1,9 +1,13 @@
 sample:
   name: BME280 Sensor sample
+common:
+  filter: dt_compat_enabled("bosch,bme280")
+  tags:
+    - sensors
+    - bme280
 tests:
   sample.sensor.bme280:
     harness: console
-    tags: sensors
     platform_allow:
       - adafruit_feather_m0_basic_proto
       - rpi_pico
@@ -16,11 +20,11 @@ tests:
       fixture: fixture_i2c_bme280
   sample.sensor.bme280.spi:
     harness: console
-    tags: sensors
+    platform_allow:
+      - lpcxpresso55s16
     depends_on:
       - spi
-      - bme280
-    extra_args: "DTC_OVERLAY_FILE=arduino_spi.overlay"
+    extra_args: "SHIELD=mikroe_weather_click_spi"
     harness_config:
       type: one_line
       regex:
@@ -28,7 +32,6 @@ tests:
       fixture: fixture_spi_bme280
   sample.sensor.bme280.rpi_pico.pio:
     harness: console
-    tags: sensors
     platform_allow: rpi_pico
     integration_platforms:
       - rpi_pico
diff --git a/samples/sensor/bmg160/README.rst b/samples/sensor/bmg160/README.rst
new file mode 100644
index 00000000000..a46995a68fd
--- /dev/null
+++ b/samples/sensor/bmg160/README.rst
@@ -0,0 +1,61 @@
+.. zephyr:code-sample:: bmg160
+   :name: BMG160 3-axis gyroscope
+   :relevant-api: sensor_interface
+
+   Get temperature, and angular velocity data from a BMG160 sensor.
+
+Overview
+********
+
+This sample shows how to use the Zephyr :ref:`sensor` API driver for the
+`Bosch BMG160`_ environmental sensor.
+
+.. _Bosch BMG160:
+   https://web.archive.org/web/20181111220522/https://ae-bst.resource.bosch.com/media/_tech/media/datasheets/BST-BMG160-DS000-09.pdf
+
+The sample first runs in polling mode for 15 seconds, then in trigger mode, display the temperature and angular velocity data from the BMG160 sensor.
+
+Building and Running
+********************
+
+The sample can be configured to support BMG160 sensors connected via I2C. Configuration is done via :ref:`devicetree <dt-guide>`. The devicetree
+must have an enabled node with ``compatible = "bosch,bmg160";``. See
+:dtcompatible:`bosch,bmg160` for the devicetree binding and see below for
+examples and common configurations.
+
+If the sensor is not built into your board, start by wiring the sensor pins
+according to the connection diagram given in the `BMG160 datasheet`_ at
+page 78.
+
+.. _BMG160 datasheet:
+   https://www.mouser.com/datasheet/2/783/BST-BMG160-DS000-1509613.pdf
+
+Sample Output
+=============
+
+The sample prints output to the serial console. BMG160 device driver messages
+are also logged. Refer to your board's documentation for information on
+connecting to its serial console.
+
+Here is example output for the default application settings, assuming that only
+one BMG160 sensor is connected to the standard Arduino I2C pins:
+
+.. code-block:: none
+
+   *** Booting Zephyr OS v3.7.0 ***
+   Testing the polling mode.
+   Gyro (rad/s): X=3.6, Y=14.0, Z=0.0f,
+   Temperature (Celsius): 29.4
+   Gyro (rad/s): X=5.1, Y=-9.0, Z=0.0f,
+   Temperature (Celsius): 29.5
+   ...
+   Polling mode test finished.
+   Testing the trigger mode.
+   Gyro: Testing anymotion trigger.
+   Gyro: rotate the device and wait for events.
+   Gyro (rad/s): X=13.6, Y=14.0, Z=10.0f,
+   Gyro: Anymotion trigger test finished.
+   Gyro: Testing data ready trigger.
+   Gyro (rad/s): X=3.6, Y=5.4, Z=1.1f,
+   Gyro: Data ready trigger test finished.
+   Trigger mode test finished
diff --git a/samples/sensor/bmi270/README.rst b/samples/sensor/bmi270/README.rst
index e7985c4d547..798de78968f 100644
--- a/samples/sensor/bmi270/README.rst
+++ b/samples/sensor/bmi270/README.rst
@@ -30,7 +30,7 @@ Building and Running
 This project outputs sensor data to the console. It requires a BMI270
 sensor. It should work with any platform featuring a I2C peripheral interface.
 It does not work on QEMU.
-In this example below the :ref:`nrf52840dk_nrf52840` board is used.
+In this example below the :zephyr:board:`nrf52840dk` board is used.
 
 
 .. zephyr-app-commands::
diff --git a/samples/sensor/clock/CMakeLists.txt b/samples/sensor/clock/CMakeLists.txt
new file mode 100644
index 00000000000..412f9ec7bfd
--- /dev/null
+++ b/samples/sensor/clock/CMakeLists.txt
@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2024 Cienet
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(clock)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/samples/sensor/clock/README.rst b/samples/sensor/clock/README.rst
new file mode 100644
index 00000000000..551cf681b02
--- /dev/null
+++ b/samples/sensor/clock/README.rst
@@ -0,0 +1,53 @@
+.. zephyr:code-sample:: sensor_clock
+   :name: Sensor Clock
+   :relevant-api: sensor_interface
+
+   Test and debug Sensor Clock functionality.
+
+Overview
+********
+
+This sample application demonstrates how to select the sensor clock source
+and utilize the Sensor Clock API.
+
+Building and Running
+********************
+
+The sample below uses the :zephyr:board:`nrf52840dk` and :zephyr:board:`nrf52833dk` boards.
+
+To run this sample, ensure the following configurations:
+
+    * Enable one of the Kconfig options:
+      :kconfig:option:`CONFIG_SENSOR_CLOCK_COUNTER`,
+      :kconfig:option:`CONFIG_SENSOR_CLOCK_RTC`, or
+      :kconfig:option:`CONFIG_SENSOR_CLOCK_SYSTEM`.
+
+Build and run the sample with the following command:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/sensor/clock
+   :board: <board to use>
+   :goals: build flash
+
+Sample Output
+=============
+
+The application will print the current sensor clock cycles and
+their corresponding time in nanoseconds.
+
+.. code-block:: console
+
+   Cycles: 143783087
+   Nanoseconds: 8986442937
+   Cycles: 159776386
+   Nanoseconds: 9986024125
+   Cycles: 175772543
+   Nanoseconds: 10985783937
+   Cycles: 191771203
+   Nanoseconds: 11985700187
+   Cycles: 207758870
+   Nanoseconds: 12984929375
+   Cycles: 223752074
+   Nanoseconds: 13984504625
+
+   ...
diff --git a/samples/sensor/clock/boards/nrf52833dk_nrf52833.overlay b/samples/sensor/clock/boards/nrf52833dk_nrf52833.overlay
new file mode 100644
index 00000000000..057465d1075
--- /dev/null
+++ b/samples/sensor/clock/boards/nrf52833dk_nrf52833.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Cienet
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&rtc0 {
+	status = "okay";
+};
+
+&timer0 {
+	status = "okay";
+};
diff --git a/samples/sensor/clock/boards/nrf52840dk_nrf52840.overlay b/samples/sensor/clock/boards/nrf52840dk_nrf52840.overlay
new file mode 100644
index 00000000000..057465d1075
--- /dev/null
+++ b/samples/sensor/clock/boards/nrf52840dk_nrf52840.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Cienet
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&rtc0 {
+	status = "okay";
+};
+
+&timer0 {
+	status = "okay";
+};
diff --git a/samples/sensor/clock/boards/nrf528xx_counter.overlay b/samples/sensor/clock/boards/nrf528xx_counter.overlay
new file mode 100644
index 00000000000..51def7ff522
--- /dev/null
+++ b/samples/sensor/clock/boards/nrf528xx_counter.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Cienet
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,sensor-clock = &timer0;
+	};
+};
diff --git a/samples/sensor/clock/boards/nrf528xx_rtc.overlay b/samples/sensor/clock/boards/nrf528xx_rtc.overlay
new file mode 100644
index 00000000000..ddacc146841
--- /dev/null
+++ b/samples/sensor/clock/boards/nrf528xx_rtc.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Cienet
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,sensor-clock = &rtc0;
+	};
+};
diff --git a/samples/sensor/clock/prj.conf b/samples/sensor/clock/prj.conf
new file mode 100644
index 00000000000..8fdcaf2c196
--- /dev/null
+++ b/samples/sensor/clock/prj.conf
@@ -0,0 +1,14 @@
+#
+# Copyright (c) 2024 Cienet
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+CONFIG_LOG=y
+CONFIG_LOG_DEFAULT_LEVEL=3
+
+CONFIG_SENSOR=y
+CONFIG_COUNTER=y
+CONFIG_RTC=y
+CONFIG_SENSOR_ASYNC_API=y
+
+CONFIG_SENSOR_CLOCK_COUNTER=y
diff --git a/samples/sensor/clock/sample.yaml b/samples/sensor/clock/sample.yaml
new file mode 100644
index 00000000000..0f4b1e05c79
--- /dev/null
+++ b/samples/sensor/clock/sample.yaml
@@ -0,0 +1,47 @@
+#
+# Copyright (c) 2024 Cienet
+#
+# SPDX-License-Identifier: Apache-2.0
+
+common:
+  harness: console
+  harness_config:
+    type: multi_line
+    ordered: false
+    regex:
+      - "Cycles:.*"
+      - "Nanoseconds:.*"
+
+tests:
+  sample.sensor.clock.counter:
+    filter: CONFIG_SENSOR_CLOCK_COUNTER
+    tags:
+      - drivers
+      - sensor
+      - counter
+    platform_allow:
+      - nrf52840dk/nrf52840
+      - nrf52833dk/nrf52833
+    extra_dtc_overlay_files:
+      - "boards/${BOARD}${NORMALIZED_BOARD_QUALIFIERS}.overlay"
+      - "boards/nrf528xx_counter.overlay"
+
+  sample.sensor.clock.rtc:
+    filter: CONFIG_SENSOR_CLOCK_RTC
+    tags:
+      - drivers
+      - sensor
+      - rtc
+    platform_allow:
+      - nrf52840dk/nrf52840
+      - nrf52833dk/nrf52833
+    extra_dtc_overlay_files:
+      - "boards/${BOARD}${NORMALIZED_BOARD_QUALIFIERS}.overlay"
+      - "boards/nrf528xx_rtc.overlay"
+
+  sample.sensor.clock.system:
+    filter: CONFIG_SENSOR_CLOCK_SYSTEM
+    tags:
+      - drivers
+      - sensor
+      - system_clock
diff --git a/samples/sensor/clock/src/main.c b/samples/sensor/clock/src/main.c
new file mode 100644
index 00000000000..fcaf6520af4
--- /dev/null
+++ b/samples/sensor/clock/src/main.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2024 Cienet
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/sensor_clock.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/drivers/counter.h>
+#include <stdio.h>
+
+int main(void)
+{
+	uint64_t cycles = 0;
+	uint64_t delta_ns = 0;
+	int err;
+
+	while (true) {
+		k_sleep(K_MSEC(1000));
+
+		err = sensor_clock_get_cycles(&cycles);
+		if (err) {
+			printf("Failed to get sensor clock cycles, error: %d\n", err);
+			continue;
+		}
+
+		printf("Cycles: %llu\n", cycles);
+
+		delta_ns = sensor_clock_cycles_to_ns(cycles);
+
+		printf("Nanoseconds: %llu\n", delta_ns);
+	}
+
+	return 0;
+}
diff --git a/samples/sensor/co2_polling/sample.yaml b/samples/sensor/co2_polling/sample.yaml
index 2bba3191fa2..b7f6019aed9 100644
--- a/samples/sensor/co2_polling/sample.yaml
+++ b/samples/sensor/co2_polling/sample.yaml
@@ -5,6 +5,5 @@ tests:
     harness: sensor
     tags: sensors
     filter: dt_alias_exists("co2")
-    depends_on:
-      - serial
-      - uart_interrupt_driven
+    integration_platforms:
+      - nucleo_h563zi
diff --git a/samples/sensor/dht_polling/src/main.c b/samples/sensor/dht_polling/src/main.c
index 9055f07cb92..fcbe0ca9295 100644
--- a/samples/sensor/dht_polling/src/main.c
+++ b/samples/sensor/dht_polling/src/main.c
@@ -84,7 +84,7 @@ int main(void)
 					(struct sensor_chan_spec) {SENSOR_CHAN_HUMIDITY, 0},
 					&hum_fit, 1, &hum_data);
 
-			printk("%16s: temp is %s%d.%d °C humidity is %s%d.%d RH\n", dev->name,
+			printk("%16s: temp is %s%d.%d °C humidity is %s%d.%d %%RH\n", dev->name,
 				PRIq_arg(temp_data.readings[0].temperature, 2, temp_data.shift),
 				PRIq_arg(hum_data.readings[0].humidity, 2, hum_data.shift));
 		}
diff --git a/samples/sensor/die_temp_polling/boards/esp32c6_devkitc_hpcore.overlay b/samples/sensor/die_temp_polling/boards/esp32c6_devkitc_hpcore.overlay
new file mode 100644
index 00000000000..cd60462728c
--- /dev/null
+++ b/samples/sensor/die_temp_polling/boards/esp32c6_devkitc_hpcore.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025 Patrick Harböck
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Application overlay for enabling temperature sensor device instance
+ */
+
+&coretemp {
+	status = "okay";
+};
diff --git a/samples/sensor/die_temp_polling/boards/mimxrt1050_evk.conf b/samples/sensor/die_temp_polling/boards/mimxrt1050_evk_mimxrt1052_hyperflash.conf
similarity index 100%
rename from samples/sensor/die_temp_polling/boards/mimxrt1050_evk.conf
rename to samples/sensor/die_temp_polling/boards/mimxrt1050_evk_mimxrt1052_hyperflash.conf
diff --git a/samples/sensor/die_temp_polling/boards/mimxrt1064_evk.overlay b/samples/sensor/die_temp_polling/boards/mimxrt1064_evk.overlay
new file mode 100644
index 00000000000..77b70f05777
--- /dev/null
+++ b/samples/sensor/die_temp_polling/boards/mimxrt1064_evk.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2025 SECO Mind Srl
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&tempmon {
+	status = "okay";
+};
diff --git a/samples/sensor/die_temp_polling/boards/pico_plus2_rp2350b_m33.conf b/samples/sensor/die_temp_polling/boards/pico_plus2_rp2350b_m33.conf
new file mode 100644
index 00000000000..488a81dca52
--- /dev/null
+++ b/samples/sensor/die_temp_polling/boards/pico_plus2_rp2350b_m33.conf
@@ -0,0 +1 @@
+CONFIG_ADC=y
diff --git a/samples/sensor/die_temp_polling/boards/pico_plus2_rp2350b_m33.overlay b/samples/sensor/die_temp_polling/boards/pico_plus2_rp2350b_m33.overlay
new file mode 100644
index 00000000000..38f5ece1c98
--- /dev/null
+++ b/samples/sensor/die_temp_polling/boards/pico_plus2_rp2350b_m33.overlay
@@ -0,0 +1,9 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 TOKITA Hiroshi
+ */
+
+&die_temp {
+	status = "okay";
+};
diff --git a/samples/sensor/fxos8700/README.rst b/samples/sensor/fxos8700/README.rst
deleted file mode 100644
index cc0f3a5885a..00000000000
--- a/samples/sensor/fxos8700/README.rst
+++ /dev/null
@@ -1,150 +0,0 @@
-.. zephyr:code-sample:: fxos8700
-   :name: FXOS8700 Accelerometer/Magnetometer Sensor
-   :relevant-api: sensor_interface
-
-   Get accelerometer and magnetometer data from an FXOS8700 sensor (polling & trigger mode).
-
-Overview
-********
-
-This sample application shows how to use the FXOS8700 driver.
-The driver supports FXOS8700 accelerometer/magnetometer and
-MMA8451Q, MMA8652FC, MMA8653FC accelerometers.
-
-Building and Running
-********************
-
-This project outputs sensor data to the console. FXOS8700
-sensor is present on the :zephyr:board:`frdm_k64f`, :zephyr:board:`frdm_k22f`,
-:zephyr:board:`frdm_kw41z`, :ref:`hexiwear`, and :zephyr:board:`twr_ke18f` boards.
-Accelerometer only devices are present on the :zephyr:board:`frdm_kl25z`,
-:zephyr:board:`bbc_microbit`, and :ref:`reel_board` boards. It does not work on
-QEMU.
-
-Building and Running for FRDM-K64F
-==================================
-FRDM-K64F is equipped with FXOS8700CQ accelerometer and magnetometer.
-Sample can be built and executed for the FRDM-K64F as follows:
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/sensor/fxos8700
-   :board: frdm_k64f
-   :goals: build flash
-   :compact:
-
-Example building for the FRDM-K64F with motion detection support:
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/sensor/fxos8700
-   :board: frdm_k64f
-   :conf: "prj.conf overlay-motion.conf"
-   :goals: build flash
-   :compact:
-
-Building and Running for FRDM-K22F
-==================================
-FRDM-K22F is equipped with FXOS8700CQ accelerometer and magnetometer.
-Sample can be built and executed for the FRDM-K22F as follows:
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/sensor/fxos8700
-   :board: frdm_k22f
-   :goals: build flash
-   :compact:
-
-Example building for the FRDM-K22F with motion detection support:
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/sensor/fxos8700
-   :board: frdm_k22f
-   :conf: "prj.conf overlay-motion.conf"
-   :goals: build flash
-   :compact:
-
-Building and Running for TWR-KE18F
-==================================
-TWR-KE18F is equipped with FXOS8700CQ accelerometer and magnetometer.
-The FXOS8700CQ IRQ lines, however, are not connected by default, so
-motion detection is not supported.
-
-Sample can be built and executed for the TWR-KE18F as follows:
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/sensor/fxos8700
-   :board: twr_ke18f
-   :goals: build flash
-   :compact:
-
-Building and Running for FRDM-KL25Z
-===================================
-FRDM-KL25Z is equipped with MMA8451Q accelerometer.
-Sample can be built and executed for the FRDM-KL25Z as follows:
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/sensor/fxos8700
-   :board: frdm_kl25z
-   :conf: "prj_accel.conf"
-   :goals: build flash
-   :compact:
-
-Building and Running for Micro Bit
-==================================
-Micro Bit is equipped with MMA8653FC accelerometer.
-Sample can be built and executed for the Micro Bit as follows:
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/sensor/fxos8700
-   :board: bbc_microbit
-   :conf: "prj_accel.conf"
-   :goals: build flash
-   :compact:
-
-Building and Running for reel board
-===================================
-The reel board is equipped with MMA8652FC accelerometer.
-Sample can be built and executed for the reel board as follows:
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/sensor/fxos8700
-   :board: reel_board
-   :conf: "prj_accel.conf"
-   :goals: build flash
-   :compact:
-
-Building and Running for MIMXRT685-EVK
-======================================
-MIMXRT685-EVK is equipped with FXOS8700CQ accelerometer and magnetometer.
-Sample can be built and executed for the MIMXRT685-EVK as follows:
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/sensor/fxos8700
-   :board: mimxrt685_evk/mimxrt685s/cm33
-   :goals: build flash
-   :compact:
-
-Building and Running for MIMXRT595-EVK
-======================================
-MIMXRT595-EVK is optionally equipped with FXOS8700CQ accelerometer and magnetometer.
-Please confirm the FXOS8700CQ(U6) is populated on your board.
-Sample can be built and executed for the MIMXRT595-EVK as follows:
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/sensor/fxos8700
-   :board: mimxrt595_evk/mimxrt595s/cm33
-   :goals: build flash
-   :compact:
-
-Sample Output
-=============
-
-.. code-block:: console
-
-   AX= -0.191537 AY=  0.067037 AZ=  9.902418 MX=  0.379000 MY=  0.271000 MZ= -0.056000 T= 22.080000
-   AX= -0.162806 AY=  0.143652 AZ=  9.940725 MX=  0.391000 MY=  0.307000 MZ= -0.058000 T= 22.080000
-   AX= -0.172383 AY=  0.134075 AZ=  9.969455 MX=  0.395000 MY=  0.287000 MZ= -0.017000 T= 22.080000
-   AX= -0.210690 AY=  0.105344 AZ=  9.911994 MX=  0.407000 MY=  0.306000 MZ= -0.068000 T= 22.080000
-   AX= -0.153229 AY=  0.124498 AZ=  9.950302 MX=  0.393000 MY=  0.301000 MZ= -0.021000 T= 22.080000
-   AX= -0.153229 AY=  0.095768 AZ=  9.921571 MX=  0.398000 MY=  0.278000 MZ= -0.040000 T= 22.080000
-   AX= -0.162806 AY=  0.105344 AZ=  9.902418 MX=  0.372000 MY=  0.300000 MZ= -0.046000 T= 22.080000
-
-<repeats endlessly>
diff --git a/samples/sensor/grove_light/CMakeLists.txt b/samples/sensor/grove_light/CMakeLists.txt
deleted file mode 100644
index 7c0b23d0778..00000000000
--- a/samples/sensor/grove_light/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-cmake_minimum_required(VERSION 3.20.0)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(grove_light)
-
-FILE(GLOB app_sources src/*.c)
-target_sources(app PRIVATE ${app_sources})
diff --git a/samples/sensor/grove_light/README.rst b/samples/sensor/grove_light/README.rst
deleted file mode 100644
index 696235ab902..00000000000
--- a/samples/sensor/grove_light/README.rst
+++ /dev/null
@@ -1,51 +0,0 @@
-.. zephyr:code-sample:: grove_light
-   :name: Grove Light Sensor
-   :relevant-api: sensor_interface
-
-   Get illuminance data from a Grove Light Sensor.
-
-Overview
-********
-
-This sample application gets the output of the grove light sensor and prints it to the console, in
-units of lux, once every second.
-
-Requirements
-************
-
-To use this sample, the following hardware is required:
-
-* A board with ADC support
-* `Grove Light Sensor`_
-* `Grove Base Shield`_
-
-Wiring
-******
-
-The easiest way to connect the sensor is to connect it to a Grove shield on a board that supports
-Arduino shields. Provide a devicetree overlay that specifies the sensor location. If using the
-overlay provided for the sample, the sensor should be connected to A0 on the Grove shield.
-
-Building and Running
-********************
-
-Build and flash the sample as follows, changing ``nrf52dk_nrf52832`` to your board:
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/sensor/grove_light
-   :board: nrf52dk_nrf52832
-   :goals: build flash
-   :compact:
-
-Sample Output
-=============
-
-.. code-block:: console
-
-    *** Booting Zephyr OS build v3.6.0-rc1-32-gba639ed6a893 ***
-    lux: 0.945751
-    lux: 0.882292
-    lux: 0.755973
-
-.. _Grove Base Shield: https://wiki.seeedstudio.com/Base_Shield_V2/
-.. _Grove Light Sensor: https://wiki.seeedstudio.com/Grove-Light_Sensor/
diff --git a/samples/sensor/grove_light/boards/nrf52dk_nrf52832.overlay b/samples/sensor/grove_light/boards/nrf52dk_nrf52832.overlay
deleted file mode 100644
index 5556e2ce054..00000000000
--- a/samples/sensor/grove_light/boards/nrf52dk_nrf52832.overlay
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright (c) 2019 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
-	ntc {
-		compatible = "seeed,grove-light";
-		io-channels = <&arduino_adc 0>;
-	};
-};
diff --git a/samples/sensor/grove_light/sample.yaml b/samples/sensor/grove_light/sample.yaml
deleted file mode 100644
index 24e020f7fb5..00000000000
--- a/samples/sensor/grove_light/sample.yaml
+++ /dev/null
@@ -1,16 +0,0 @@
-common:
-  filter: CONFIG_FULL_LIBC_SUPPORTED
-sample:
-  name: Grove Light Sensor
-tests:
-  sample.sensor.grove_light:
-    tags:
-      - drivers
-      - sensor
-      - grove
-      - light
-    platform_allow: nrf52dk/nrf52832
-    integration_platforms:
-      - nrf52dk/nrf52832
-    harness: grove
-    depends_on: adc
diff --git a/samples/sensor/grove_light/src/main.c b/samples/sensor/grove_light/src/main.c
deleted file mode 100644
index 57de0ea9967..00000000000
--- a/samples/sensor/grove_light/src/main.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (c) 2016 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/kernel.h>
-#include <zephyr/init.h>
-#include <stdio.h>
-#include <zephyr/drivers/sensor.h>
-
-#define SLEEP_TIME	K_MSEC(1000)
-
-int main(void)
-{
-	const struct device *const dev = DEVICE_DT_GET_ONE(seeed_grove_light);
-
-	if (!device_is_ready(dev)) {
-		printk("sensor: device not ready.\n");
-		return 0;
-	}
-
-	while (1) {
-		int read;
-		struct sensor_value lux;
-
-		read = sensor_sample_fetch(dev);
-		if (read) {
-			printf("sample fetch error %d\n", read);
-			continue;
-		}
-
-		sensor_channel_get(dev, SENSOR_CHAN_LIGHT, &lux);
-
-		printf("lux: %f\n", sensor_value_to_double(&lux));
-
-		k_sleep(SLEEP_TIME);
-	}
-	return 0;
-}
diff --git a/samples/sensor/light_polling/CMakeLists.txt b/samples/sensor/light_polling/CMakeLists.txt
new file mode 100644
index 00000000000..78c0ee9c7de
--- /dev/null
+++ b/samples/sensor/light_polling/CMakeLists.txt
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(light)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/samples/sensor/light_polling/README.rst b/samples/sensor/light_polling/README.rst
new file mode 100644
index 00000000000..183180e9624
--- /dev/null
+++ b/samples/sensor/light_polling/README.rst
@@ -0,0 +1,48 @@
+.. zephyr:code-sample:: light_sensor_polling
+   :name: Generic Light Sensor Polling
+   :relevant-api: sensor_interface
+
+   Get illuminance data from a light sensor.
+
+Overview
+********
+
+This sample application gets the output of the light sensor and prints it to the console, in
+units of lux, once every second.
+
+Requirements
+************
+
+To use this sample, the following hardware is required:
+
+* A board with ADC support
+* A supported light sensor (e.g., `Grove Light Sensor`_), available as ``light-sensor`` Devicetree alias.
+
+Wiring
+******
+
+The wiring depends on the specific light sensor and board being used. Provide a devicetree
+overlay that specifies the sensor configuration for your setup.
+
+Building and Running
+********************
+
+Build and flash the sample as follows, changing ``nrf52dk_nrf52832`` to your board:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/sensor/light_polling
+   :board: nrf52dk_nrf52832
+   :goals: build flash
+   :compact:
+
+Sample Output
+=============
+
+.. code-block:: console
+
+    *** Booting Zephyr OS build v3.6.0-rc1-32-gba639ed6a893 ***
+    lux: 0.945751
+    lux: 0.882292
+    lux: 0.755973
+
+.. _Grove Light Sensor: https://wiki.seeedstudio.com/Grove-Light_Sensor/
diff --git a/samples/sensor/light_polling/boards/frdm_mcxw71.overlay b/samples/sensor/light_polling/boards/frdm_mcxw71.overlay
new file mode 100644
index 00000000000..25d7461675b
--- /dev/null
+++ b/samples/sensor/light_polling/boards/frdm_mcxw71.overlay
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2025 Dipak Shetty <shetty.dipak@gmx.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+
+/ {
+	aliases {
+		light-sensor = &als_pt19_315c;
+	};
+
+	als_pt19_315c: als-pt19-315c {
+		compatible = "everlight,als-pt19";
+		io-channels = <&adc0 2>;
+		load-resistor = <15000>;
+	};
+};
+
+&adc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@2 {
+		reg = <0x2>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,vref-mv = <3300>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <MCUX_LPADC_CH2B>;
+	};
+};
diff --git a/samples/sensor/light_polling/boards/nrf52dk_nrf52832.overlay b/samples/sensor/light_polling/boards/nrf52dk_nrf52832.overlay
new file mode 100644
index 00000000000..c61fcd45593
--- /dev/null
+++ b/samples/sensor/light_polling/boards/nrf52dk_nrf52832.overlay
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2019 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+
+	aliases {
+		light-sensor = &grove_light;
+	};
+
+	grove_light: grove_light {
+		compatible = "seeed,grove-light";
+		io-channels = <&arduino_adc 0>;
+	};
+};
diff --git a/samples/sensor/grove_light/prj.conf b/samples/sensor/light_polling/prj.conf
similarity index 100%
rename from samples/sensor/grove_light/prj.conf
rename to samples/sensor/light_polling/prj.conf
diff --git a/samples/sensor/light_polling/sample.yaml b/samples/sensor/light_polling/sample.yaml
new file mode 100644
index 00000000000..ddfecfd0feb
--- /dev/null
+++ b/samples/sensor/light_polling/sample.yaml
@@ -0,0 +1,28 @@
+sample:
+  name: Light Sensor Polling Sample
+common:
+  filter: dt_alias_exists("light-sensor")
+tests:
+  sample.sensor.light_polling.grove:
+    tags:
+      - drivers
+      - sensor
+      - grove
+      - light
+    platform_allow:
+      - nrf52dk/nrf52832
+    integration_platforms:
+      - nrf52dk/nrf52832
+    harness: grove
+    depends_on: adc
+  sample.sensor.light_polling.als_pt19:
+    tags:
+      - drivers
+      - sensor
+      - light
+    platform_allow:
+      - frdm_mcxw71/mcxw716c
+    integration_platforms:
+      - frdm_mcxw71/mcxw716c
+    depends_on:
+      - adc
diff --git a/samples/sensor/light_polling/src/main.c b/samples/sensor/light_polling/src/main.c
new file mode 100644
index 00000000000..b598c9a2f4c
--- /dev/null
+++ b/samples/sensor/light_polling/src/main.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2016 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/init.h>
+#include <stdio.h>
+#include <zephyr/drivers/sensor.h>
+
+#define SLEEP_TIME K_MSEC(1000)
+
+int main(void)
+{
+	const struct device *const dev = DEVICE_DT_GET(DT_ALIAS(light_sensor));
+
+	if (!device_is_ready(dev)) {
+		printk("sensor: device not ready.\n");
+		return 0;
+	}
+
+	while (1) {
+		int read;
+		struct sensor_value lux;
+
+		read = sensor_sample_fetch(dev);
+		if (read) {
+			printf("sample fetch error %d\n", read);
+			continue;
+		}
+
+		sensor_channel_get(dev, SENSOR_CHAN_LIGHT, &lux);
+
+		printf("lux: %f\n", sensor_value_to_double(&lux));
+
+		k_sleep(SLEEP_TIME);
+	}
+	return 0;
+}
diff --git a/samples/sensor/lis2dh/README.rst b/samples/sensor/lis2dh/README.rst
index 0b635de1c47..274277e1e8f 100644
--- a/samples/sensor/lis2dh/README.rst
+++ b/samples/sensor/lis2dh/README.rst
@@ -30,7 +30,7 @@ The LIS2DH2 or compatible sensors are available on a variety of boards
 and shields supported by Zephyr, including:
 
 * :zephyr:board:`actinius_icarus`
-* :ref:`thingy52_nrf52832`
+* :zephyr:board:`thingy52`
 * :zephyr:board:`stm32f3_disco`
 * :ref:`x-nucleo-iks01a2`
 
diff --git a/samples/sensor/lis2dh/sample.yaml b/samples/sensor/lis2dh/sample.yaml
index 8054b378686..27296cf1e53 100644
--- a/samples/sensor/lis2dh/sample.yaml
+++ b/samples/sensor/lis2dh/sample.yaml
@@ -2,10 +2,12 @@ sample:
   name: LIS2DH Accelerometer Monitor
 tests:
   sample.sensor.lis2dh:
+    filter: dt_compat_enabled("st,lis2dh")
     harness: sensor
     tags:
       - samples
       - sensor
     depends_on:
       - i2c
-      - lis2dh
+    integration_platforms:
+      - sparkfun_thing_plus/nrf9160
diff --git a/samples/sensor/magn_trig/boards/frdm_k82f.conf b/samples/sensor/magn_trig/boards/frdm_k82f.conf
new file mode 100644
index 00000000000..008252267cd
--- /dev/null
+++ b/samples/sensor/magn_trig/boards/frdm_k82f.conf
@@ -0,0 +1 @@
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
diff --git a/samples/sensor/magn_trig/boards/frdm_kw41z.conf b/samples/sensor/magn_trig/boards/frdm_kw41z.conf
new file mode 100644
index 00000000000..008252267cd
--- /dev/null
+++ b/samples/sensor/magn_trig/boards/frdm_kw41z.conf
@@ -0,0 +1 @@
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
diff --git a/samples/sensor/magn_trig/boards/mimxrt1050_evk_mimxrt1052_hyperflash.conf b/samples/sensor/magn_trig/boards/mimxrt1050_evk_mimxrt1052_hyperflash.conf
new file mode 100644
index 00000000000..008252267cd
--- /dev/null
+++ b/samples/sensor/magn_trig/boards/mimxrt1050_evk_mimxrt1052_hyperflash.conf
@@ -0,0 +1 @@
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
diff --git a/samples/sensor/magn_trig/boards/mimxrt1160_evk_mimxrt1166_cm7.conf b/samples/sensor/magn_trig/boards/mimxrt1160_evk_mimxrt1166_cm7.conf
new file mode 100644
index 00000000000..2a9f025bc1f
--- /dev/null
+++ b/samples/sensor/magn_trig/boards/mimxrt1160_evk_mimxrt1166_cm7.conf
@@ -0,0 +1,5 @@
+#
+# check the fxos8700 dts for this board for addition settings
+#
+
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
diff --git a/samples/sensor/magn_trig/boards/mimxrt1170_evk@A_mimxrt1176_cm7.conf b/samples/sensor/magn_trig/boards/mimxrt1170_evk@A_mimxrt1176_cm7.conf
new file mode 100644
index 00000000000..2a9f025bc1f
--- /dev/null
+++ b/samples/sensor/magn_trig/boards/mimxrt1170_evk@A_mimxrt1176_cm7.conf
@@ -0,0 +1,5 @@
+#
+# check the fxos8700 dts for this board for addition settings
+#
+
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
diff --git a/samples/sensor/magn_trig/boards/mimxrt595_evk_mimxrt595s_cm33.conf b/samples/sensor/magn_trig/boards/mimxrt595_evk_mimxrt595s_cm33.conf
new file mode 100644
index 00000000000..ebcb58d5b54
--- /dev/null
+++ b/samples/sensor/magn_trig/boards/mimxrt595_evk_mimxrt595s_cm33.conf
@@ -0,0 +1,2 @@
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
+CONFIG_FXOS8700_MODE_ACCEL=y
diff --git a/samples/sensor/magn_trig/boards/mimxrt685_evk_mimxrt685s_cm33.conf b/samples/sensor/magn_trig/boards/mimxrt685_evk_mimxrt685s_cm33.conf
new file mode 100644
index 00000000000..008252267cd
--- /dev/null
+++ b/samples/sensor/magn_trig/boards/mimxrt685_evk_mimxrt685s_cm33.conf
@@ -0,0 +1 @@
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
diff --git a/samples/sensor/magn_trig/boards/twr_ke18f.conf b/samples/sensor/magn_trig/boards/twr_ke18f.conf
new file mode 100644
index 00000000000..008252267cd
--- /dev/null
+++ b/samples/sensor/magn_trig/boards/twr_ke18f.conf
@@ -0,0 +1 @@
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
diff --git a/samples/sensor/magn_trig/boards/twr_ke18f.overlay b/samples/sensor/magn_trig/boards/twr_ke18f.overlay
new file mode 100644
index 00000000000..c35b67ae86d
--- /dev/null
+++ b/samples/sensor/magn_trig/boards/twr_ke18f.overlay
@@ -0,0 +1,12 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright 2025 NXP
+ */
+
+
+&fxos8700 {
+	status = "okay";
+	int1-gpios = <&gpioa 14 GPIO_ACTIVE_LOW>;
+	int2-gpios = <&gpioa 17 GPIO_ACTIVE_LOW>;
+};
diff --git a/samples/sensor/magn_trig/boards/twr_kv58f220m.conf b/samples/sensor/magn_trig/boards/twr_kv58f220m.conf
new file mode 100644
index 00000000000..008252267cd
--- /dev/null
+++ b/samples/sensor/magn_trig/boards/twr_kv58f220m.conf
@@ -0,0 +1 @@
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
diff --git a/samples/sensor/magn_trig/sample.yaml b/samples/sensor/magn_trig/sample.yaml
index 8f4a27381a0..0e49242ce77 100644
--- a/samples/sensor/magn_trig/sample.yaml
+++ b/samples/sensor/magn_trig/sample.yaml
@@ -6,6 +6,7 @@ tests:
     tags: sensors
     filter: dt_alias_exists("magn0")
     harness_config:
+      fixture: fixture_sensor_magn_int
       type: one_line
       regex:
         - "^\\s*[0-9A-Za-z_,+-.]*@[0-9A-Fa-f]* \\(x, y, z\\):    \
diff --git a/samples/sensor/mcux_acmp/README.rst b/samples/sensor/mcux_acmp/README.rst
index 765169fa0e1..5a5951c2bf7 100644
--- a/samples/sensor/mcux_acmp/README.rst
+++ b/samples/sensor/mcux_acmp/README.rst
@@ -42,7 +42,7 @@ ACMP input voltage by changing the voltage input to J25-13.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/sensor/mcux_acmp
-   :board: mimxrt1170_evk_cm7
+   :board: mimxrt1170_evk/mimxrt1176/cm7
    :goals: flash
    :compact:
 
diff --git a/samples/sensor/mcux_acmp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/samples/sensor/mcux_acmp/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
similarity index 100%
rename from samples/sensor/mcux_acmp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay
rename to samples/sensor/mcux_acmp/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
diff --git a/samples/sensor/mcux_acmp/sample.yaml b/samples/sensor/mcux_acmp/sample.yaml
index a00773fdbb6..47a0056843a 100644
--- a/samples/sensor/mcux_acmp/sample.yaml
+++ b/samples/sensor/mcux_acmp/sample.yaml
@@ -4,10 +4,10 @@ sample:
 common:
   platform_allow:
     - twr_ke18f
-    - mimxrt1170_evk/mimxrt1176/cm7
-    - mimxrt1170_evk/mimxrt1176/cm4
     - frdm_ke17z
     - frdm_ke17z512
+    - mimxrt1170_evk/mimxrt1176/cm7
+    - mimxrt1170_evk/mimxrt1176/cm4
     - mimxrt1180_evk/mimxrt1189/cm33
     - mimxrt1180_evk/mimxrt1189/cm7
   integration_platforms:
diff --git a/samples/sensor/mcux_lpcmp/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/samples/sensor/mcux_lpcmp/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..b856f1622d6
--- /dev/null
+++ b/samples/sensor/mcux_lpcmp/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Sample requires node labeled lpcmp0, map to lpcmp2
+ * Apply input voltage to LPCMP on header J1-pin 14 (P1_2)
+ */
+/delete-node/ &lpcmp0;
+lpcmp0: &lpcmp2 {
+	function-clock = "CMP_CLOCK";
+};
diff --git a/samples/sensor/mcux_lpcmp/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay b/samples/sensor/mcux_lpcmp/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay
new file mode 100644
index 00000000000..b856f1622d6
--- /dev/null
+++ b/samples/sensor/mcux_lpcmp/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay
@@ -0,0 +1,14 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Sample requires node labeled lpcmp0, map to lpcmp2
+ * Apply input voltage to LPCMP on header J1-pin 14 (P1_2)
+ */
+/delete-node/ &lpcmp0;
+lpcmp0: &lpcmp2 {
+	function-clock = "CMP_CLOCK";
+};
diff --git a/samples/sensor/mcux_lpcmp/sample.yaml b/samples/sensor/mcux_lpcmp/sample.yaml
index d23c4b5ed9e..49657b6f970 100644
--- a/samples/sensor/mcux_lpcmp/sample.yaml
+++ b/samples/sensor/mcux_lpcmp/sample.yaml
@@ -4,6 +4,7 @@ sample:
 common:
   platform_allow:
     - frdm_mcxn947/mcxn947/cpu0
+    - mcx_n9xx_evk/mcxn947/cpu0
     - frdm_mcxn236
     - frdm_mcxa156
   integration_platforms:
diff --git a/samples/sensor/mpr/README.rst b/samples/sensor/mpr/README.rst
index b1f8d8ff0e7..4813b8d1116 100644
--- a/samples/sensor/mpr/README.rst
+++ b/samples/sensor/mpr/README.rst
@@ -27,7 +27,7 @@ Building and Running
 This project outputs sensor data to the console. It requires a sensor from the
 MPR series.
 It does not work on QEMU.
-In the sample below the :ref:`arduino_due` board is used.
+In the sample below the :zephyr:board:`arduino_due` board is used.
 
 .. zephyr-app-commands::
    :zephyr-app: samples/sensor/mpr
diff --git a/samples/sensor/mpu6050/README.rst b/samples/sensor/mpu6050/README.rst
index d1287461476..189bd24f735 100644
--- a/samples/sensor/mpu6050/README.rst
+++ b/samples/sensor/mpu6050/README.rst
@@ -12,8 +12,8 @@ This sample application periodically (0.5 Hz) measures the sensor
 temperature, acceleration, and angular velocity, displaying the values
 on the console along with a timestamp since startup.
 
-When triggered mode is enabled the measurements are displayed at the
-rate they are produced by the sensor.
+When triggered mode is enabled the measurements are displayed at a rate
+of 32Hz governed by the sensor's internal clock and divider.
 
 Wiring
 *******
diff --git a/samples/sensor/mpu6050/boards/nrf52dk_nrf52832.overlay b/samples/sensor/mpu6050/boards/nrf52dk_nrf52832.overlay
index 77bcfef9825..d328de20ba6 100644
--- a/samples/sensor/mpu6050/boards/nrf52dk_nrf52832.overlay
+++ b/samples/sensor/mpu6050/boards/nrf52dk_nrf52832.overlay
@@ -10,5 +10,6 @@
 		reg = <0x68>;
 		status = "okay";
 		int-gpios = <&gpio0 11 GPIO_ACTIVE_HIGH>;
+		smplrt-div = <249>;
 	};
 };
diff --git a/samples/sensor/ms5837/README.rst b/samples/sensor/ms5837/README.rst
index 6bc90fa5312..d05ee011640 100644
--- a/samples/sensor/ms5837/README.rst
+++ b/samples/sensor/ms5837/README.rst
@@ -42,7 +42,7 @@ Build this sample using the following commands:
    :goals: build
    :compact:
 
-See :ref:`nrf52840dk_nrf52840` on how to flash the build.
+See :zephyr:board:`nrf52840dk` on how to flash the build.
 
 References
 **********
diff --git a/samples/sensor/ms5837/boards/nrf52840dk_nrf52840.overlay b/samples/sensor/ms5837/boards/nrf52840dk_nrf52840.overlay
index 7b5e801a828..39dcb323ccd 100644
--- a/samples/sensor/ms5837/boards/nrf52840dk_nrf52840.overlay
+++ b/samples/sensor/ms5837/boards/nrf52840dk_nrf52840.overlay
@@ -8,7 +8,8 @@
 	status = "okay";
 	clock-frequency = <I2C_BITRATE_STANDARD>;
 	ms5837@76 {
-		compatible = "meas,ms5837";
+		compatible = "meas,ms5837-30ba";
 		reg = <0x76>;
+		status = "okay";
 	};
 };
diff --git a/samples/sensor/paj7620_gesture/CMakeLists.txt b/samples/sensor/paj7620_gesture/CMakeLists.txt
new file mode 100644
index 00000000000..c1f0bfcb580
--- /dev/null
+++ b/samples/sensor/paj7620_gesture/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Paul Timke <ptimkec@live.com>
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(paj7620_gesture)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/samples/sensor/paj7620_gesture/Kconfig b/samples/sensor/paj7620_gesture/Kconfig
new file mode 100644
index 00000000000..b977690ddf3
--- /dev/null
+++ b/samples/sensor/paj7620_gesture/Kconfig
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Paul Timke <ptimkec@live.com>
+# SPDX-License-Identifier: Apache-2.0
+
+mainmenu "PAJ7620 sample application"
+
+config APP_USE_POLLING
+	bool "Select y to use polling, otherwise the sample will use triggers"
+	default y
+
+source "Kconfig.zephyr"
diff --git a/samples/sensor/paj7620_gesture/README.rst b/samples/sensor/paj7620_gesture/README.rst
new file mode 100644
index 00000000000..788e7561888
--- /dev/null
+++ b/samples/sensor/paj7620_gesture/README.rst
@@ -0,0 +1,41 @@
+.. zephyr:code-sample:: paj7620_gesture
+   :name: PAJ7620 Gesture Sensor
+   :relevant-api: sensor_interface
+
+   Get hand gesture data from PAJ7620 sensor.
+
+Overview
+********
+
+This sample application gets the output of a gesture sensor (paj7620) using either polling or
+triggers (depending on CONFIG_APP_USE_POLLING) and outputs the corresponding gesture to the
+console, each time one is detected.
+
+Requirements
+************
+
+To use this sample, the following hardware is required:
+
+* A board with I2C support and GPIO to detect external interrutps
+* PAJ7620 sensor
+
+Building and Running
+********************
+
+This sample outputs data to the console. It requires a PAJ7620 sensor.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/sensor/paj7620_gesture
+   :board: nucleo_f334r8
+   :goals: build
+   :compact:
+
+Sample Output
+=============
+
+.. code-block:: console
+
+   Gesture LEFT
+   Gesture RIGHT
+   Gesture UP
+   Gesture DOWN
diff --git a/samples/sensor/paj7620_gesture/boards/nucleo_f334r8.overlay b/samples/sensor/paj7620_gesture/boards/nucleo_f334r8.overlay
new file mode 100644
index 00000000000..0e67fa6a052
--- /dev/null
+++ b/samples/sensor/paj7620_gesture/boards/nucleo_f334r8.overlay
@@ -0,0 +1,13 @@
+&gpioa {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+
+	paj7620: paj7620@73 {
+		compatible = "pixart,paj7620";
+		reg = <0x73>;
+		int-gpios = <&gpioa 9 (GPIO_PULL_UP)>;
+	};
+};
diff --git a/samples/sensor/paj7620_gesture/prj.conf b/samples/sensor/paj7620_gesture/prj.conf
new file mode 100644
index 00000000000..845bcc219b1
--- /dev/null
+++ b/samples/sensor/paj7620_gesture/prj.conf
@@ -0,0 +1,5 @@
+CONFIG_GPIO=y
+CONFIG_STDOUT_CONSOLE=y
+CONFIG_I2C=y
+CONFIG_SENSOR=y
+CONFIG_PAJ7620_TRIGGER_OWN_THREAD=y
diff --git a/samples/sensor/paj7620_gesture/sample.yaml b/samples/sensor/paj7620_gesture/sample.yaml
new file mode 100644
index 00000000000..33ee9743178
--- /dev/null
+++ b/samples/sensor/paj7620_gesture/sample.yaml
@@ -0,0 +1,17 @@
+sample:
+  name: PAJ7620 gesture trigger sample
+tests:
+  sample.sensor.paj7620_gesture_trig:
+    build_only: true
+    tags: sensors
+    platform_allow: nucleo_f334r8
+    depends_on:
+      - i2c
+      - gpio
+    filter: dt_compat_enabled("pixart,paj7620")
+  sample.sensor.paj7620_gesture_polling:
+    build_only: true
+    tags: sensors
+    platform_allow: nucleo_f334r8
+    depends_on: i2c
+    filter: dt_compat_enabled("pixart,paj7620")
diff --git a/samples/sensor/paj7620_gesture/src/main.c b/samples/sensor/paj7620_gesture/src/main.c
new file mode 100644
index 00000000000..c0dbdc735c2
--- /dev/null
+++ b/samples/sensor/paj7620_gesture/src/main.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2025 Paul Timke <ptimkec@live.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/sensor/paj7620.h>
+
+#define GESTURE_POLL_TIME_MS 100
+
+K_SEM_DEFINE(sem, 0, 1); /* starts off "not available" */
+
+static void trigger_handler(const struct device *dev, const struct sensor_trigger *trigger)
+{
+	ARG_UNUSED(trigger);
+
+	if (sensor_sample_fetch(dev) < 0) {
+		printf("sensor_sample_fetch failed\n");
+		return;
+	}
+
+	k_sem_give(&sem);
+}
+
+static void print_hand_gesture(uint16_t gest_flags)
+{
+	if ((gest_flags & PAJ7620_FLAG_GES_UP) != 0) {
+		printf("Gesture UP\n");
+	}
+	if ((gest_flags & PAJ7620_FLAG_GES_DOWN) != 0) {
+		printf("Gesture DOWN\n");
+	}
+	if ((gest_flags & PAJ7620_FLAG_GES_LEFT) != 0) {
+		printf("Gesture LEFT\n");
+	}
+	if ((gest_flags & PAJ7620_FLAG_GES_RIGHT) != 0) {
+		printf("Gesture RIGHT\n");
+	}
+	if ((gest_flags & PAJ7620_FLAG_GES_FORWARD) != 0) {
+		printf("Gesture FORWARD\n");
+	}
+	if ((gest_flags & PAJ7620_FLAG_GES_BACKWARD) != 0) {
+		printf("Gesture BACKWARD\n");
+	}
+	if ((gest_flags & PAJ7620_FLAG_GES_CLOCKWISE) != 0) {
+		printf("Gesture CLOCKWISE\n");
+	}
+	if ((gest_flags & PAJ7620_FLAG_GES_COUNTERCLOCKWISE) != 0) {
+		printf("Gesture COUNTER CLOCKWISE\n");
+	}
+}
+
+static void trigger_main_loop(const struct device *dev)
+{
+	struct sensor_value data;
+
+	while (1) {
+		k_sem_take(&sem, K_FOREVER);
+
+		(void)sensor_channel_get(dev, (enum sensor_channel)SENSOR_CHAN_PAJ7620_GESTURES,
+					 &data);
+
+		print_hand_gesture(data.val1);
+	}
+}
+
+static void polling_main_loop(const struct device *dev)
+{
+	struct sensor_value data;
+
+	while (1) {
+		(void)sensor_sample_fetch(dev);
+		(void)sensor_channel_get(dev, (enum sensor_channel)SENSOR_CHAN_PAJ7620_GESTURES,
+					 &data);
+
+		print_hand_gesture(data.val1);
+		k_msleep(GESTURE_POLL_TIME_MS);
+	}
+}
+
+int main(void)
+{
+	int ret;
+	const struct device *dev = DEVICE_DT_GET_ONE(pixart_paj7620);
+
+	struct sensor_trigger trig = {
+		.type = SENSOR_TRIG_MOTION,
+		.chan = (enum sensor_channel)SENSOR_CHAN_PAJ7620_GESTURES,
+	};
+
+	if (!device_is_ready(dev)) {
+		printf("Device %s is not ready\n", dev->name);
+		return -ENODEV;
+	}
+
+	if (IS_ENABLED(CONFIG_APP_USE_POLLING)) {
+		polling_main_loop(dev);
+	} else {
+		/* App was configured to NOT use polling, so use triggers */
+		ret = sensor_trigger_set(dev, &trig, trigger_handler);
+		if (ret < 0) {
+			printf("Could not set trigger\n");
+			return ret;
+		}
+
+		trigger_main_loop(dev);
+	}
+}
diff --git a/samples/sensor/pressure_interrupt/CMakeLists.txt b/samples/sensor/pressure_interrupt/CMakeLists.txt
new file mode 100644
index 00000000000..09ca28e4cb1
--- /dev/null
+++ b/samples/sensor/pressure_interrupt/CMakeLists.txt
@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2024 TDK Invensense
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(icp201xx)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/samples/sensor/pressure_interrupt/Kconfig b/samples/sensor/pressure_interrupt/Kconfig
new file mode 100644
index 00000000000..b5062e52ff2
--- /dev/null
+++ b/samples/sensor/pressure_interrupt/Kconfig
@@ -0,0 +1,31 @@
+# Copyright (c) 2024, TDK Invensense
+# SPDX-License-Identifier: Apache-2.0
+
+config LOG
+	default y
+
+config LOG_PRINTK
+	default y
+
+config SENSOR_LOG_LEVEL
+	default 4
+
+config PRESSURE_DRDY
+	bool "Enable pressure data ready interrupt"
+	default y
+
+config PRESSURE_THRESHOLD
+	bool "Enable pressure threshold interrupt"
+	default y
+
+config PRESSURE_DELTA
+	bool "Enable pressure delta interrupt"
+	default y
+
+choice ICP201XX_TRIGGER_MODE
+	default ICP201XX_TRIGGER_GLOBAL_THREAD
+	depends on ICP201XX
+
+endchoice
+
+source "Kconfig.zephyr"
diff --git a/samples/sensor/pressure_interrupt/README.rst b/samples/sensor/pressure_interrupt/README.rst
new file mode 100644
index 00000000000..d59dce60fbd
--- /dev/null
+++ b/samples/sensor/pressure_interrupt/README.rst
@@ -0,0 +1,73 @@
+.. zephyr:code-sample:: pressure_interrupt
+   :name: Barometric pressure and temperature sensor interrupt example
+   :relevant-api: sensor_interface
+
+   Manage interrupts from a barometric pressure and temperature sensor.
+
+Overview
+********
+
+This sample application uses a pressure sensor interrupt line to:
+
+* Inform when a measure is available in the sensor FIFO.
+  Temperature and pressure data are read and displayed in terminal.
+  If floats are supported, estimated altitude is also displayed.
+* Inform when the pressure value crosses a specified threshold.
+  Threshold corresponds to around a 50cm altitude increase.
+  A message is displayed in the terminal.
+* Inform when the pressure value changed more than the specified
+  value between two consecutive samples.
+  Change value corresponds to a finger pressing the sensor.
+  A message is displayed in the terminal.
+
+Wiring
+*******
+
+This sample uses an external breakout for the sensor.  A devicetree
+overlay must be provided to identify the I2C/SPI bus and GPIO used to
+control the sensor.
+
+Building and Running
+********************
+
+This sample supports pressure sensor devices. Device needs
+to be aliased as ``pressure-sensor``. For example:
+
+.. code-block:: devicetree
+
+	/ {
+		aliases {
+			pressure-sensor = &icp201xx;
+		};
+	};
+
+Make sure the aliases are in devicetree, then build and run with:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/sensor/pressure_interrupt
+   :board: nrf52dk/nrf52832
+   :goals: build flash
+
+Sample Output
+=============
+
+.. code-block:: console
+
+## Default configuration
+
+   [00:00:00.266,479] <inf> PRESS_INT_SAMPLE: Starting ICP201xx sample.
+   [00:00:00.273,803] <inf> PRESS_INT_SAMPLE: temp 25.49 Cel, pressure 96.271438 kPa, altitude 447.208465 m
+   [00:00:00.280,914] <inf> PRESS_INT_SAMPLE: temp 25.50 Cel, pressure 96.271331 kPa, altitude 447.234161 m
+   [00:00:00.288,024] <inf> PRESS_INT_SAMPLE: temp 25.49 Cel, pressure 96.266685 kPa, altitude 447.636077 m
+   [00:00:00.295,135] <inf> PRESS_INT_SAMPLE: temp 25.50 Cel, pressure 96.267951 kPa, altitude 447.537078 m
+   [00:00:00.302,246] <inf> PRESS_INT_SAMPLE: temp 25.51 Cel, pressure 96.268577 kPa, altitude 447.488281 m
+   [00:00:00.309,356] <inf> PRESS_INT_SAMPLE: temp 25.50 Cel, pressure 96.269340 kPa, altitude 447.414978 m
+   [00:00:00.316,467] <inf> PRESS_INT_SAMPLE: temp 25.50 Cel, pressure 96.268562 kPa, altitude 447.473663 m
+   [00:00:00.323,547] <inf> PRESS_INT_SAMPLE: temp 25.50 Cel, pressure 96.267341 kPa, altitude 447.596496 m
+   <repeats endlessly>
+
+   <when sensor is pressed>
+   [00:00:09.819,061] <inf> PRESS_INT_SAMPLE: PRESSURE CHANGE INTERRUPT
+
+   <when the sensor pressure crosses defined threhold>
+   [00:00:09.859,039] <inf> PRESS_INT_SAMPLE: PRESSURE THRESHOLD INTERRUPT
diff --git a/samples/sensor/pressure_interrupt/boards/nrf52dk_nrf52832.overlay b/samples/sensor/pressure_interrupt/boards/nrf52dk_nrf52832.overlay
new file mode 100644
index 00000000000..ad26418fd22
--- /dev/null
+++ b/samples/sensor/pressure_interrupt/boards/nrf52dk_nrf52832.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2024, TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Get a node identifier for pressure sensor.
+ */
+/ {
+	aliases {
+		pressure-sensor = &icp201xx;
+	};
+};
+
+/* Example configuration of a ICP2021XX device on an Arduino SPI bus. */
+&arduino_spi {
+	status = "okay";
+	cs-gpios = <&arduino_header 14 GPIO_ACTIVE_LOW>; /* D8 */
+	icp201xx: icp201xx@0 {
+		compatible = "invensense,icp201xx";
+		reg = <0>;
+		spi-max-frequency = <500000>; /* conservatively set to 500k */
+		int-gpios = <&arduino_header 8 GPIO_ACTIVE_HIGH>; /* D2 */
+		drive-strength = "current_4mA_1_8V"; /* Avoid cross talk */
+	};
+};
+
+/*
+ * Increase native UART speed.
+ */
+&uart0 {
+	compatible = "nordic,nrf-uarte";
+	status = "okay";
+	current-speed = <1000000>;
+};
diff --git a/samples/sensor/pressure_interrupt/prj.conf b/samples/sensor/pressure_interrupt/prj.conf
new file mode 100644
index 00000000000..bea79e439eb
--- /dev/null
+++ b/samples/sensor/pressure_interrupt/prj.conf
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2024 TDK Invensense
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_SENSOR=y
+
+# Floating point format support
+# Selecting this increases stack size requirements slightly, but increases code size significantly.
+CONFIG_CBPRINTF_FP_SUPPORT=y
+
+# Buffer size for console. The defaults are optimized to save RAM
+CONFIG_CONSOLE_SUBSYS=y
+CONFIG_CONSOLE_GETCHAR=y
+CONFIG_CONSOLE_GETCHAR_BUFSIZE=16
+CONFIG_CONSOLE_PUTCHAR_BUFSIZE=512
diff --git a/samples/sensor/pressure_interrupt/sample.yaml b/samples/sensor/pressure_interrupt/sample.yaml
new file mode 100644
index 00000000000..e170db1509a
--- /dev/null
+++ b/samples/sensor/pressure_interrupt/sample.yaml
@@ -0,0 +1,9 @@
+sample:
+  name: Pressure sensor interrupt
+tests:
+  sample.sensor.pressure_interrupt:
+    build_only: true
+    tags: sensors
+    filter: dt_alias_exists("pressure-sensor")
+    integration_platforms:
+      - nrf52dk/nrf52832
diff --git a/samples/sensor/pressure_interrupt/src/main.c b/samples/sensor/pressure_interrupt/src/main.c
new file mode 100644
index 00000000000..6c55e6d1840
--- /dev/null
+++ b/samples/sensor/pressure_interrupt/src/main.c
@@ -0,0 +1,157 @@
+/*
+ * Copyright (c) 2024 TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/sensor.h>
+#include <stdio.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(PRESS_INT_SAMPLE, CONFIG_SENSOR_LOG_LEVEL);
+
+/*
+ * Get a device structure from a devicetree node from alias
+ * "pressure_sensor".
+ */
+static const struct device *get_pressure_sensor_device(void)
+{
+	const struct device *const dev = DEVICE_DT_GET(DT_ALIAS(pressure_sensor));
+
+	if (!device_is_ready(dev)) {
+		printk("\nError: Device \"%s\" is not ready; "
+		       "check the driver initialization logs for errors.\n",
+		       dev->name);
+		return NULL;
+	}
+
+	printk("Found device \"%s\", getting sensor data\n", dev->name);
+	return dev;
+}
+
+#ifdef CONFIG_PRESSURE_DRDY
+static void data_ready_handler(const struct device *dev, const struct sensor_trigger *trig)
+{
+
+	if (trig->type == SENSOR_TRIG_DATA_READY) {
+		int rc = sensor_sample_fetch_chan(dev, trig->chan);
+
+		if (rc < 0) {
+			printf("sample fetch failed: %d\n", rc);
+			printf("cancelling trigger\n");
+			(void)sensor_trigger_set(dev, trig, NULL);
+			return;
+		} else if (rc == 0) {
+
+			struct sensor_value pressure;
+			struct sensor_value temperature;
+			struct sensor_value altitude;
+
+			sensor_channel_get(dev, SENSOR_CHAN_PRESS, &pressure);
+			sensor_channel_get(dev, SENSOR_CHAN_AMBIENT_TEMP, &temperature);
+			sensor_channel_get(dev, SENSOR_CHAN_ALTITUDE, &altitude);
+
+			LOG_INF("temp %.2f Cel, pressure %f kPa, altitude %f m",
+				sensor_value_to_double(&temperature),
+				sensor_value_to_double(&pressure),
+				sensor_value_to_double(&altitude));
+		}
+	}
+}
+#endif
+
+#ifdef CONFIG_PRESSURE_THRESHOLD
+static void threshold_handler(const struct device *dev, const struct sensor_trigger *trig)
+{
+	if (trig->type == SENSOR_TRIG_THRESHOLD) {
+		LOG_INF("PRESSURE THRESHOLD INTERRUPT");
+	}
+}
+#endif
+
+#ifdef CONFIG_PRESSURE_DELTA
+static void delta_handler(const struct device *dev, const struct sensor_trigger *trig)
+{
+	if (trig->type == SENSOR_TRIG_DELTA) {
+		LOG_INF("PRESSURE CHANGE INTERRUPT\n");
+	}
+}
+#endif
+
+int main(void)
+{
+	static struct sensor_trigger data_ready_trigger;
+	const struct device *dev = get_pressure_sensor_device();
+#ifdef CONFIG_PRESSURE_THRESHOLD
+	static struct sensor_trigger threshold_trigger;
+	struct sensor_value pressure, pressure_threshold;
+#endif
+#ifdef CONFIG_PRESSURE_DELTA
+	static struct sensor_trigger delta_trigger;
+	struct sensor_value pressure_delta;
+#endif
+
+	if (dev == NULL) {
+		return 0;
+	}
+#ifdef CONFIG_PRESSURE_DRDY
+	/* Configure data ready trigger */
+	data_ready_trigger = (struct sensor_trigger){
+		.type = SENSOR_TRIG_DATA_READY,
+		.chan = SENSOR_CHAN_ALL,
+	};
+	if (sensor_trigger_set(dev, &data_ready_trigger, data_ready_handler) < 0) {
+		printf("Cannot configure data trigger!!!\n");
+		return 0;
+	}
+#endif
+
+#ifdef CONFIG_PRESSURE_THRESHOLD
+	/* Configure pressure threshold trigger */
+	/* Interrupt is triggered if sensor is lifted of about 50cm */
+	/* Read current pressure */
+	k_sleep(K_MSEC(50));
+	sensor_sample_fetch_chan(dev, SENSOR_CHAN_PRESS);
+	sensor_channel_get(dev, SENSOR_CHAN_PRESS, &pressure);
+
+	/* Retrieve 5 Pa, around 50cm altitude increase */
+	pressure_threshold.val1 = pressure.val1;
+	pressure_threshold.val2 = pressure.val2 - 5000;
+	sensor_attr_set(dev, SENSOR_CHAN_PRESS, SENSOR_ATTR_LOWER_THRESH, &pressure_threshold);
+
+	LOG_INF("Pressure at reset %.3f kPa, interrupt sets at %.3f kPa.\n",
+		sensor_value_to_double(&pressure), sensor_value_to_double(&pressure_threshold));
+
+	threshold_trigger = (struct sensor_trigger){
+		.type = SENSOR_TRIG_THRESHOLD,
+		.chan = SENSOR_CHAN_PRESS,
+	};
+	if (sensor_trigger_set(dev, &threshold_trigger, threshold_handler) < 0) {
+		printf("Cannot configure threshold trigger!!!\n");
+		return 0;
+	}
+#endif
+
+#ifdef CONFIG_PRESSURE_DELTA
+	/* Configure pressure delta trigger */
+	/* Set pressure delta to 0.01 kPa to detect a press on the sensor */
+	pressure_delta.val1 = 0;
+	pressure_delta.val2 = 10000;
+	sensor_attr_set(dev, SENSOR_CHAN_PRESS, SENSOR_ATTR_SLOPE_TH, &pressure_delta);
+	delta_trigger = (struct sensor_trigger){
+		.type = SENSOR_TRIG_DELTA,
+		.chan = SENSOR_CHAN_PRESS,
+	};
+	if (sensor_trigger_set(dev, &delta_trigger, delta_handler) < 0) {
+		printf("Cannot configure threshold trigger!!!\n");
+		return 0;
+	}
+#endif
+
+	LOG_INF("Starting pressure event sample.\n");
+
+	return 0;
+}
diff --git a/samples/sensor/pressure_polling/CMakeLists.txt b/samples/sensor/pressure_polling/CMakeLists.txt
new file mode 100644
index 00000000000..b7dbb9dc728
--- /dev/null
+++ b/samples/sensor/pressure_polling/CMakeLists.txt
@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2024 TDK Invensense
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(pressure_polling)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/samples/sensor/pressure_polling/Kconfig b/samples/sensor/pressure_polling/Kconfig
new file mode 100644
index 00000000000..fc80e211464
--- /dev/null
+++ b/samples/sensor/pressure_polling/Kconfig
@@ -0,0 +1,13 @@
+# Copyright (c) 2024, TDK Invensense
+# SPDX-License-Identifier: Apache-2.0
+
+config LOG
+	default y
+
+config LOG_PRINTK
+	default y
+
+config SENSOR_LOG_LEVEL
+	default 4
+
+source "Kconfig.zephyr"
diff --git a/samples/sensor/pressure_polling/README.rst b/samples/sensor/pressure_polling/README.rst
new file mode 100644
index 00000000000..f224c4a5343
--- /dev/null
+++ b/samples/sensor/pressure_polling/README.rst
@@ -0,0 +1,60 @@
+.. zephyr:code-sample:: pressure_polling
+   :name: Barometric pressure and temperature sensor polling example
+   :relevant-api: sensor_interface
+
+   Get barometric pressure and temperature data from a sensor.
+
+Overview
+********
+
+This sample application periodically reads the sensor
+temperature and pressure, displaying the
+values on the console along with a timestamp since startup.
+It also displays the estimated altitude if floating point is supported.
+
+Wiring
+*******
+
+This sample uses an external breakout for the sensor.  A devicetree
+overlay must be provided to identify the I2C/SPI used to control the sensor.
+
+Building and Running
+********************
+
+This sample supports pressure sensor devices. Device needs
+to be aliased as ``pressure-sensor``. For example:
+
+.. code-block:: devicetree
+
+	/ {
+		aliases {
+			pressure-sensor = &icp201xx;
+		};
+	};
+
+Make sure the aliases are in devicetree, then build and run with:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/sensor/pressure_polling
+   :board: nrf52dk/nrf52832
+   :goals: build flash
+
+Sample Output
+=============
+
+.. code-block:: console
+
+## Default configuration
+
+   Found device "icp101xx@63", getting sensor data
+   [00:00:00.266,479] <inf> PRESSURE_POLLING: Starting pressure and altitude polling sample.
+   [00:00:00.273,803] <inf> PRESSURE_POLLING: temp 25.49 Cel, pressure 96.271438 kPa, altitude 447.208465 m
+   [00:00:00.280,914] <inf> PRESSURE_POLLING: temp 25.50 Cel, pressure 96.271331 kPa, altitude 447.234161 m
+   [00:00:00.288,024] <inf> PRESSURE_POLLING: temp 25.49 Cel, pressure 96.266685 kPa, altitude 447.636077 m
+   [00:00:00.295,135] <inf> PRESSURE_POLLING: temp 25.50 Cel, pressure 96.267951 kPa, altitude 447.537078 m
+   [00:00:00.302,246] <inf> PRESSURE_POLLING: temp 25.51 Cel, pressure 96.268577 kPa, altitude 447.488281 m
+   [00:00:00.309,356] <inf> PRESSURE_POLLING: temp 25.50 Cel, pressure 96.269340 kPa, altitude 447.414978 m
+   [00:00:00.316,467] <inf> PRESSURE_POLLING: temp 25.50 Cel, pressure 96.268562 kPa, altitude 447.473663 m
+   [00:00:00.323,547] <inf> PRESSURE_POLLING: temp 25.50 Cel, pressure 96.267341 kPa, altitude 447.596496 m
+
+   <repeats endlessly>
diff --git a/samples/sensor/pressure_polling/boards/nrf52dk_nrf52832.overlay b/samples/sensor/pressure_polling/boards/nrf52dk_nrf52832.overlay
new file mode 100644
index 00000000000..5409e0c3a6e
--- /dev/null
+++ b/samples/sensor/pressure_polling/boards/nrf52dk_nrf52832.overlay
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2024, TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Get a node identifier for pressure sensor.
+ */
+/ {
+	aliases {
+		pressure-sensor = &icp201xx;
+	};
+};
+
+/*
+ * Example configuration of a icp201xx device on an Arduino I2C bus.
+ *
+ * Device address 0x63 is assumed. Your device may have a different
+ * address; check your device documentation if unsure.
+ */
+&arduino_i2c {
+	status = "okay";
+	icp201xx: icp201xx@63 {
+		compatible = "invensense,icp201xx";
+		reg = <0x63>;
+	};
+};
+
+/*
+ * Increase native UART speed to report sensor data.
+ */
+&uart0 {
+	compatible = "nordic,nrf-uarte";
+	status = "okay";
+	current-speed = <1000000>;
+};
diff --git a/samples/sensor/pressure_polling/prj.conf b/samples/sensor/pressure_polling/prj.conf
new file mode 100644
index 00000000000..bea79e439eb
--- /dev/null
+++ b/samples/sensor/pressure_polling/prj.conf
@@ -0,0 +1,17 @@
+#
+# Copyright (c) 2024 TDK Invensense
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_SENSOR=y
+
+# Floating point format support
+# Selecting this increases stack size requirements slightly, but increases code size significantly.
+CONFIG_CBPRINTF_FP_SUPPORT=y
+
+# Buffer size for console. The defaults are optimized to save RAM
+CONFIG_CONSOLE_SUBSYS=y
+CONFIG_CONSOLE_GETCHAR=y
+CONFIG_CONSOLE_GETCHAR_BUFSIZE=16
+CONFIG_CONSOLE_PUTCHAR_BUFSIZE=512
diff --git a/samples/sensor/pressure_polling/sample.yaml b/samples/sensor/pressure_polling/sample.yaml
new file mode 100644
index 00000000000..1fae99115af
--- /dev/null
+++ b/samples/sensor/pressure_polling/sample.yaml
@@ -0,0 +1,9 @@
+sample:
+  name: Pressure polling sample
+tests:
+  sample.sensor.pressure_sensor:
+    build_only: true
+    tags: sensors
+    filter: dt_alias_exists("pressure-sensor")
+    integration_platforms:
+      - nrf52dk/nrf52832
diff --git a/samples/sensor/pressure_polling/src/main.c b/samples/sensor/pressure_polling/src/main.c
new file mode 100644
index 00000000000..ea3af570db9
--- /dev/null
+++ b/samples/sensor/pressure_polling/src/main.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2024 TDK Invensense
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/sensor.h>
+#include <stdio.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(PRESSURE_POLLING, CONFIG_SENSOR_LOG_LEVEL);
+
+/*
+ * Get a device structure from a devicetree node from alias
+ * "pressure_sensor".
+ */
+static const struct device *get_pressure_sensor_device(void)
+{
+	const struct device *const dev = DEVICE_DT_GET(DT_ALIAS(pressure_sensor));
+
+	if (!device_is_ready(dev)) {
+		printk("\nError: Device \"%s\" is not ready; "
+		       "check the driver initialization logs for errors.\n",
+		       dev->name);
+		return NULL;
+	}
+
+	printk("Found device \"%s\", getting sensor data\n", dev->name);
+	return dev;
+}
+
+int main(void)
+{
+	const struct device *dev = get_pressure_sensor_device();
+
+	if (dev == NULL) {
+		return 0;
+	}
+	struct sensor_value pressure;
+	struct sensor_value temperature;
+	struct sensor_value altitude;
+
+	LOG_INF("Starting pressure and altitude polling sample.\n");
+
+	while (1) {
+		if (sensor_sample_fetch_chan(dev, SENSOR_CHAN_ALL) == 0) {
+			sensor_channel_get(dev, SENSOR_CHAN_PRESS, &pressure);
+			sensor_channel_get(dev, SENSOR_CHAN_AMBIENT_TEMP, &temperature);
+			sensor_channel_get(dev, SENSOR_CHAN_ALTITUDE, &altitude);
+
+			LOG_INF("temp %.2f Cel, pressure %f kPa, altitude %f m",
+				sensor_value_to_double(&temperature),
+				sensor_value_to_double(&pressure),
+				sensor_value_to_double(&altitude));
+		}
+	}
+	return 0;
+}
diff --git a/samples/sensor/qdec/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/samples/sensor/qdec/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..53ca74e6bfe
--- /dev/null
+++ b/samples/sensor/qdec/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		qdec0 = &qdec20;
+		qenca = &phase_a;
+		qencb = &phase_b;
+	};
+
+	encoder-emulate {
+		compatible = "gpio-leds";
+
+		phase_a: phase_a {
+			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+		};
+
+		phase_b: phase_b {
+			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&pinctrl {
+	qdec_pinctrl: qdec_pinctrl {
+		group1 {
+			psels = <NRF_PSEL(QDEC_A, 1, 8)>,
+				<NRF_PSEL(QDEC_B, 1, 10)>;
+		};
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&qdec20 {
+	status = "okay";
+	pinctrl-0 = <&qdec_pinctrl>;
+	pinctrl-names = "default";
+	steps = <120>;
+	led-pre = <500>;
+};
diff --git a/samples/sensor/qdec/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/samples/sensor/qdec/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..53ca74e6bfe
--- /dev/null
+++ b/samples/sensor/qdec/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		qdec0 = &qdec20;
+		qenca = &phase_a;
+		qencb = &phase_b;
+	};
+
+	encoder-emulate {
+		compatible = "gpio-leds";
+
+		phase_a: phase_a {
+			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+		};
+
+		phase_b: phase_b {
+			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&pinctrl {
+	qdec_pinctrl: qdec_pinctrl {
+		group1 {
+			psels = <NRF_PSEL(QDEC_A, 1, 8)>,
+				<NRF_PSEL(QDEC_B, 1, 10)>;
+		};
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&qdec20 {
+	status = "okay";
+	pinctrl-0 = <&qdec_pinctrl>;
+	pinctrl-names = "default";
+	steps = <120>;
+	led-pre = <500>;
+};
diff --git a/samples/sensor/qdec/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/samples/sensor/qdec/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..58cf87f20b1
--- /dev/null
+++ b/samples/sensor/qdec/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		qdec0 = &qdec20;
+		qenca = &phase_a;
+		qencb = &phase_b;
+	};
+
+	encoder-emulate {
+		compatible = "gpio-leds";
+
+		phase_a: phase_a {
+			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+		};
+
+		phase_b: phase_b {
+			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&pinctrl {
+	qdec_pinctrl: qdec_pinctrl {
+		group1 {
+			psels = <NRF_PSEL(QDEC_A, 1, 8)>,
+				<NRF_PSEL(QDEC_B, 1, 10)>;
+		};
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&qdec20 {
+	status = "okay";
+	pinctrl-0 = <&qdec_pinctrl>;
+	pinctrl-names = "default";
+	steps = <120>;
+	led-pre = <500>;
+};
diff --git a/samples/sensor/qdec/sample.yaml b/samples/sensor/qdec/sample.yaml
index d4d685c43fb..0cb399b21fc 100644
--- a/samples/sensor/qdec/sample.yaml
+++ b/samples/sensor/qdec/sample.yaml
@@ -43,11 +43,13 @@ tests:
       - nrf5340dk/nrf5340/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54h20dk/nrf54h20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf52840dk/nrf52840
       - nrf5340dk/nrf5340/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54h20dk/nrf54h20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     harness_config:
       fixture: gpio_loopback
       type: multi_line
diff --git a/samples/sensor/sensor_shell/Kconfig b/samples/sensor/sensor_shell/Kconfig
index 38fcdfa7eb6..8d274a19032 100644
--- a/samples/sensor/sensor_shell/Kconfig
+++ b/samples/sensor/sensor_shell/Kconfig
@@ -3,6 +3,8 @@
 
 config SAMPLES_SENSOR_SHELL_FAKE_SENSOR
 	bool "Enable fake sensor"
+	default y
+	depends on DT_HAS_VND_FAKE_SENSOR_ENABLED
 	help
 	  On boards that do not have a sensor, enabling this will build a fake
 	  sensor that can be interacted with via the sensor shell.
diff --git a/samples/sensor/sensor_shell/README.rst b/samples/sensor/sensor_shell/README.rst
index 9853157d89f..65653741bc2 100644
--- a/samples/sensor/sensor_shell/README.rst
+++ b/samples/sensor/sensor_shell/README.rst
@@ -19,13 +19,14 @@ enabled, for example:
    :board: reel_board
    :goals: build flash
 
-For boards that do not have a sensor, a simple fake sensor driver is provided, for example:
+For boards that do not have a sensor, a simple fake sensor driver is provided and can enabled by
+adding the following overlay:
 
 .. zephyr-app-commands::
    :zephyr-app: samples/sensor/sensor_shell
    :board: qemu_riscv64
    :goals: run
-   :gen-args: -DCONFIG_SAMPLES_SENSOR_SHELL_FAKE_SENSOR=y
+   :gen-args: -DEXTRA_DTC_OVERLAY_FILE=fake_sensor.overlay
 
 Shell Module Command Help
 =========================
diff --git a/samples/sensor/sensor_shell/boards/vmu_rt1170_mimxrt1176_cm7.conf b/samples/sensor/sensor_shell/boards/vmu_rt1170_mimxrt1176_cm7.conf
new file mode 100644
index 00000000000..80b1183f91e
--- /dev/null
+++ b/samples/sensor/sensor_shell/boards/vmu_rt1170_mimxrt1176_cm7.conf
@@ -0,0 +1,10 @@
+# Copyright 2025 CogniPilot Foundation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DEBUG=y
+CONFIG_SENSOR_SHELL_STREAM=y
+CONFIG_SENSOR_LOG_LEVEL_DBG=n
+CONFIG_RTIO_SUBMIT_SEM=y
+CONFIG_SPI_RTIO=y
+CONFIG_SPI_ASYNC=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=10000
diff --git a/samples/sensor/sensor_shell/boards/vmu_rt1170_mimxrt1176_cm7.overlay b/samples/sensor/sensor_shell/boards/vmu_rt1170_mimxrt1176_cm7.overlay
new file mode 100644
index 00000000000..fa28bdb2430
--- /dev/null
+++ b/samples/sensor/sensor_shell/boards/vmu_rt1170_mimxrt1176_cm7.overlay
@@ -0,0 +1,26 @@
+/* Copyright 2025 CogniPilot Foundation */
+/* SPDX-License-Identifier: Apache-2.0 */
+
+&lpspi1 {
+	/delete-node/ icm42688p0@0;
+	/delete-property/ dmas;
+	/delete-property/ dma-names;
+};
+
+&lpspi2 {
+	status = "okay";
+	cs-gpios =<&gpio3 24 GPIO_ACTIVE_LOW>;
+
+	icm42688_1: icm42688p1@0 {
+		compatible = "invensense,icm42688";
+		reg = <0>;
+		int-gpios = <&gpio2 7 GPIO_ACTIVE_HIGH>;
+		spi-max-frequency = <24000000>;
+		accel-pwr-mode = <ICM42688_DT_ACCEL_LN>;
+		accel-odr = <ICM42688_DT_ACCEL_ODR_1000>;
+		accel-fs = <ICM42688_DT_ACCEL_FS_16>;
+		gyro-pwr-mode = <ICM42688_DT_GYRO_LN>;
+		gyro-odr = <ICM42688_DT_GYRO_ODR_1000>;
+		gyro-fs = <ICM42688_DT_GYRO_FS_2000>;
+	};
+};
diff --git a/samples/sensor/sensor_shell/dts/bindings/vnd,sensor.yaml b/samples/sensor/sensor_shell/dts/bindings/vnd,fake-sensor.yaml
similarity index 100%
rename from samples/sensor/sensor_shell/dts/bindings/vnd,sensor.yaml
rename to samples/sensor/sensor_shell/dts/bindings/vnd,fake-sensor.yaml
diff --git a/samples/sensor/sensor_shell/app.overlay b/samples/sensor/sensor_shell/fake_sensor.overlay
similarity index 100%
rename from samples/sensor/sensor_shell/app.overlay
rename to samples/sensor/sensor_shell/fake_sensor.overlay
diff --git a/samples/sensor/sensor_shell/pytest/test_sensor_shell.py b/samples/sensor/sensor_shell/pytest/test_sensor_shell.py
index 7a01bec9978..49627d6f4a2 100644
--- a/samples/sensor/sensor_shell/pytest/test_sensor_shell.py
+++ b/samples/sensor/sensor_shell/pytest/test_sensor_shell.py
@@ -21,16 +21,12 @@ def test_sensor_shell_info(shell: Shell):
 def test_sensor_shell_get(shell: Shell):
     logger.info('send "sensor get" command')
 
-    lines = shell.exec_command('sensor get sensor@0 voltage')
-    assert any(['channel type=31(voltage)' in line for line in lines]), 'expected response not found'
-
-    lines = shell.exec_command('sensor get sensor@1 53')
-    assert any(['channel type=53(gauge_state_of_health)' in line for line in lines]), 'expected response not found'
-
     # Channel should be the last one before 'all' (because 'all' doesn't print anything) so that the
     # for-loop in `parse_named_int()` will go through everything
-    lines = shell.exec_command('sensor get sensor@0 gauge_desired_charging_current')
-    assert any(['channel type=59(gauge_desired_charging_current)' in line for line in lines]), 'expected response not found'
+    for channel in range(59):
+        logger.info(f'channel {channel}')
+        lines = shell.exec_command(f'sensor get sensor@0 {channel}')
+        assert any([f'channel type={channel}' in line for line in lines]), 'expected response not found'
 
     logger.info('response is valid')
 
@@ -41,7 +37,7 @@ def test_sensor_shell_attr_get(shell: Shell):
     lines = shell.exec_command('sensor attr_get sensor@0 co2 sampling_frequency')
     assert any(['sensor@0(channel=co2, attr=sampling_frequency)' in line for line in lines]), 'expected response not found'
 
-    lines = shell.exec_command('sensor attr_get sensor@1 53 3')
+    lines = shell.exec_command('sensor attr_get sensor@1 54 3')
     assert any(['sensor@1(channel=gauge_state_of_health, attr=slope_th)' in line for line in lines]), 'expected response not found'
 
     logger.info('response is valid')
@@ -54,7 +50,7 @@ def test_sensor_shell_attr_set(shell: Shell):
     expected_line = 'sensor@0 channel=co2, attr=sampling_frequency set to value=1'
     assert any([expected_line in line for line in lines]), 'expected response not found'
 
-    lines = shell.exec_command('sensor attr_set sensor@1 53 3 1')
+    lines = shell.exec_command('sensor attr_set sensor@1 54 3 1')
     expected_line = 'sensor@1 channel=gauge_state_of_health, attr=slope_th set to value=1'
     assert any([expected_line in line for line in lines]), 'expected response not found'
 
diff --git a/samples/sensor/sensor_shell/sample.yaml b/samples/sensor/sensor_shell/sample.yaml
index a694f140589..b8e98572dbd 100644
--- a/samples/sensor/sensor_shell/sample.yaml
+++ b/samples/sensor/sensor_shell/sample.yaml
@@ -21,7 +21,7 @@ tests:
     harness: pytest
     timeout: 180
     extra_configs:
-      - arch:posix:CONFIG_NATIVE_UART_0_ON_STDINOUT=y
-      - CONFIG_SAMPLES_SENSOR_SHELL_FAKE_SENSOR=y
+      - arch:posix:CONFIG_UART_NATIVE_PTY_0_ON_STDINOUT=y
+    extra_args: DTC_OVERLAY_FILE=fake_sensor.overlay
     integration_platforms:
       - native_sim
diff --git a/samples/sensor/stream_fifo/CMakeLists.txt b/samples/sensor/stream_fifo/CMakeLists.txt
new file mode 100644
index 00000000000..e056c0a32bc
--- /dev/null
+++ b/samples/sensor/stream_fifo/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(stream_fifo)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/samples/sensor/stream_fifo/README.rst b/samples/sensor/stream_fifo/README.rst
new file mode 100644
index 00000000000..708e5f18ad0
--- /dev/null
+++ b/samples/sensor/stream_fifo/README.rst
@@ -0,0 +1,143 @@
+.. zephyr:code-sample:: stream_fifo
+   :name: Generic device FIFO streaming
+   :relevant-api: sensor_interface
+
+   Get accelerometer/gyroscope/temperature FIFO data frames from a sensor using
+   SENSOR_TRIG_FIFO_WATERMARK as a trigger.
+
+Overview
+********
+
+This sample application demonstrates how to stream FIFO data using the :ref:`RTIO framework <rtio>`.
+
+The streaming is started using the sensor_stream() API and it is self-sustained by the
+SENSOR_TRIG_FIFO_WATERMARK trigger.
+
+Currently the sample gets/prints data for the following sensor channels:
+
+- SENSOR_CHAN_ACCEL_XYZ
+- SENSOR_CHAN_GYRO_XYZ
+- SENSOR_CHAN_DIE_TEMP
+- SENSOR_CHAN_GAME_ROTATION_VECTOR
+- SENSOR_CHAN_GRAVITY_VECTOR
+- SENSOR_CHAN_GBIAS_XYZ
+
+Building and Running
+********************
+
+This sample supports up to 10 FIFO streaming devices. Each device needs
+to be aliased as :samp:`stream{N}` where ``N`` goes from ``0`` to ``9``. For example:
+
+.. code-block:: devicetree
+
+  / {
+      aliases {
+                   stream0 = &lsm6dsv16x_6b_x_nucleo_iks4a1;
+              };
+      };
+
+.. note::
+    Note that NUM_SENSORS defined in main.c must match ``N`` and should be set accordingly.
+
+Example devicetree overlays and configurations are already available for nucleo_f401re and
+nucleo_h503rb in the boards directory:
+
+- :zephyr_file:`samples/sensor/stream_fifo/boards/nucleo_f401re.overlay`
+
+  DT overlay file for the nucleo_f401re board.
+
+- :zephyr_file:`samples/sensor/stream_fifo/boards/nucleo_f401re.conf`
+
+  Configuration file for the nucleo_f401re board.
+
+- :zephyr_file:`samples/sensor/stream_fifo/boards/nucleo_h503rb.overlay`
+
+  DT overlay file for the nucleo_h503rb board.
+
+- :zephyr_file:`samples/sensor/stream_fifo/boards/nucleo_h503rb.conf`
+
+  Configuration file for the nucleo_h503rb board.
+
+For example, build and run sample for nucleo_h503rb with:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/sensor/stream_fifo
+   :board: nucleo_h503rb
+   :goals: build flash
+   :compact:
+
+Sample Output
+=============
+
+The following example output is for lsm6dsv16x IMU device with accelerometer, gyroscope
+and temperature sensor including also the Sensor Fusion Low Power (SFLP) information.
+The FIFO watermark is set to 64. The board used is a nucleo_h503rb
+equipped with a :ref:`x-nucleo-iks4a1` shield.
+
+.. code-block:: console
+
+       FIFO count - 64
+       XL data for lsm6dsv16x@6b 1680572433340ns (0.373229, -0.009569, 9.909734)
+       XL data for lsm6dsv16x@6b 1680639100006ns (0.354089, -0.023924, 9.909734)
+       XL data for lsm6dsv16x@6b 1680705766672ns (0.368444, 0.000000, 9.933659)
+       XL data for lsm6dsv16x@6b 1680772433338ns (0.373229, 0.000000, 9.924089)
+       XL data for lsm6dsv16x@6b 1680839100004ns (0.368444, -0.004784, 9.924089)
+       XL data for lsm6dsv16x@6b 1680905766670ns (0.363659, -0.009569, 9.924089)
+       XL data for lsm6dsv16x@6b 1680972433336ns (0.358874, -0.004784, 9.928874)
+       XL data for lsm6dsv16x@6b 1681039100002ns (0.363659, 0.004784, 9.928874)
+       GY data for lsm6dsv16x@6b 1680572433340ns (0.001524, -0.000609, 0.004269)
+       GY data for lsm6dsv16x@6b 1680639100006ns (-0.001219, 0.002134, 0.004879)
+       GY data for lsm6dsv16x@6b 1680705766672ns (0.001219, -0.001219, 0.004879)
+       GY data for lsm6dsv16x@6b 1680772433338ns (-0.000914, 0.001219, 0.003964)
+       GY data for lsm6dsv16x@6b 1680839100004ns (0.000914, -0.001219, 0.004574)
+       GY data for lsm6dsv16x@6b 1680905766670ns (0.001829, 0.000914, 0.005489)
+       GY data for lsm6dsv16x@6b 1680972433336ns (-0.000609, 0.000304, 0.004574)
+       GY data for lsm6dsv16x@6b 1681039100002ns (0.001829, 0.000304, 0.004879)
+       TP data for lsm6dsv16x@6b 1680572433340ns 24.347656 °C
+       TP data for lsm6dsv16x@6b 1680639100006ns 24.324218 °C
+       TP data for lsm6dsv16x@6b 1680705766672ns 24.316406 °C
+       TP data for lsm6dsv16x@6b 1680772433338ns 24.296875 °C
+       ROT data for lsm6dsv16x@6b 1680639100006ns (-0.000008, -0.018661, 0.021575, 0.999593)
+       ROT data for lsm6dsv16x@6b 1680705766672ns (-0.000139, -0.018524, 0.021606, 0.999594)
+       ROT data for lsm6dsv16x@6b 1680772433338ns (-0.000055, -0.018569, 0.021621, 0.999593)
+       ROT data for lsm6dsv16x@6b 1680839100004ns (-0.000050, -0.018539, 0.021606, 0.999594)
+       ROT data for lsm6dsv16x@6b 1680905766670ns (-0.000003, -0.018569, 0.021621, 0.999593)
+       ROT data for lsm6dsv16x@6b 1680972433336ns (0.000044, -0.018493, 0.021667, 0.999594)
+       ROT data for lsm6dsv16x@6b 1681039100002ns (0.000013, -0.018432, 0.021667, 0.999595)
+       ROT data for lsm6dsv16x@6b 1681105766668ns (0.000113, -0.018402, 0.021682, 0.999595)
+       GV data for lsm6dsv16x@6b 1680639100006ns (37.270999, -0.792999, 998.447998)
+       GV data for lsm6dsv16x@6b 1680705766672ns (36.965999, -1.037000, 998.447998)
+       GV data for lsm6dsv16x@6b 1680772433338ns (37.088001, -0.854000, 998.447998)
+       GV data for lsm6dsv16x@6b 1680839100004ns (37.027000, -0.854000, 998.447998)
+       GV data for lsm6dsv16x@6b 1680905766670ns (37.088001, -0.792999, 998.447998)
+       GV data for lsm6dsv16x@6b 1680972433336ns (36.904998, -0.670999, 998.447998)
+       GV data for lsm6dsv16x@6b 1681039100002ns (36.783000, -0.732000, 998.447998)
+       GV data for lsm6dsv16x@6b 1681105766668ns (36.722000, -0.548999, 998.447998)
+       GY GBIAS data for lsm6dsv16x@6b 1680572433340ns (0.000303, -0.000151, 0.004179)
+       GY GBIAS data for lsm6dsv16x@6b 1680639100006ns (0.000303, 0.000000, 0.004179)
+       GY GBIAS data for lsm6dsv16x@6b 1680705766672ns (0.000303, -0.000075, 0.004179)
+       GY GBIAS data for lsm6dsv16x@6b 1680772433338ns (0.000227, 0.000000, 0.004179)
+       GY GBIAS data for lsm6dsv16x@6b 1680839100004ns (0.000303, -0.000075, 0.004179)
+       GY GBIAS data for lsm6dsv16x@6b 1680905766670ns (0.000303, 0.000000, 0.004255)
+       GY GBIAS data for lsm6dsv16x@6b 1680972433336ns (0.000303, 0.000000, 0.004255)
+       GY GBIAS data for lsm6dsv16x@6b 1681039100002ns (0.000379, 0.000000, 0.004255)
+       XL data for lsm6dsv16x@6b 1681105766668ns (0.358874, -0.019139, 9.928874)
+       XL data for lsm6dsv16x@6b 1681172433334ns (0.382799, -0.004784, 9.962369)
+       XL data for lsm6dsv16x@6b 1681239100000ns (0.354089, 0.000000, 9.914519)
+       GY data for lsm6dsv16x@6b 1681105766668ns (0.000304, 0.002134, 0.004574)
+       GY data for lsm6dsv16x@6b 1681172433334ns (-0.000914, 0.000914, 0.004574)
+       GY data for lsm6dsv16x@6b 1681239100000ns (0.002744, -0.002439, 0.004879)
+       TP data for lsm6dsv16x@6b 1680839100004ns 24.339843 °C
+       TP data for lsm6dsv16x@6b 1680905766670ns 24.339843 °C
+       TP data for lsm6dsv16x@6b 1680972433336ns 24.289062 °C
+       TP data for lsm6dsv16x@6b 1681039100002ns 24.296875 °C
+       ROT data for lsm6dsv16x@6b 1681172433334ns (0.000049, -0.018310, 0.021697, 0.999596)
+       ROT data for lsm6dsv16x@6b 1681239100000ns (0.000020, -0.018371, 0.021697, 0.999595)
+       GV data for lsm6dsv16x@6b 1681172433334ns (36.539001, -0.670999, 998.447998)
+       GV data for lsm6dsv16x@6b 1681239100000ns (36.660999, -0.732000, 998.447998)
+       GY GBIAS data for lsm6dsv16x@6b 1681105766668ns (0.000379, 0.000000, 0.004331)
+       GY GBIAS data for lsm6dsv16x@6b 1681172433334ns (0.000303, 0.000075, 0.004331)
+       GY GBIAS data for lsm6dsv16x@6b 1681239100000ns (0.000379, 0.000000, 0.004331)
+       TP data for lsm6dsv16x@6b 1681105766668ns 24.289062 °C
+       TP data for lsm6dsv16x@6b 1681172433334ns 24.324218 °C
+       TP data for lsm6dsv16x@6b 1681239100000ns 24.281250 °C
diff --git a/samples/sensor/stream_fifo/boards/nucleo_f401re.conf b/samples/sensor/stream_fifo/boards/nucleo_f401re.conf
new file mode 100644
index 00000000000..877b30fd2d6
--- /dev/null
+++ b/samples/sensor/stream_fifo/boards/nucleo_f401re.conf
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_I2C_RTIO=y
+CONFIG_LSM6DSV16X_STREAM=y
+CONFIG_LSM6DSV16X_ENABLE_TEMP=y
diff --git a/samples/sensor/stream_fifo/boards/nucleo_f401re.overlay b/samples/sensor/stream_fifo/boards/nucleo_f401re.overlay
new file mode 100644
index 00000000000..a428b585ed5
--- /dev/null
+++ b/samples/sensor/stream_fifo/boards/nucleo_f401re.overlay
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/dt-bindings/sensor/lsm6dsv16x.h>
+
+
+/*
+ * Nucleo F401RE board + shield iks4a1
+ *
+ * This devicetree overlay file will be automatically picked by the Zephyr
+ * build system when building the sample for the nucleo_f401re board.
+ */
+
+/ {
+	aliases {
+		stream0 = &lsm6dsv16x_6b_x_nucleo_iks4a1;
+	};
+};
+
+&arduino_i2c {
+	lsm6dsv16x_6b_x_nucleo_iks4a1: lsm6dsv16x@6b {
+		compatible = "st,lsm6dsv16x";
+		reg = <0x6b>;
+		accel-odr = <LSM6DSV16X_DT_ODR_AT_480Hz>;
+		accel-range = <LSM6DSV16X_DT_FS_16G>;
+		gyro-odr = <LSM6DSV16X_DT_ODR_AT_480Hz>;
+		gyro-range = <LSM6DSV16X_DT_FS_500DPS>;
+		fifo-watermark = <64>;
+		accel-fifo-batch-rate = <LSM6DSV16X_DT_XL_BATCHED_AT_60Hz>;
+		gyro-fifo-batch-rate = <LSM6DSV16X_DT_GY_BATCHED_AT_60Hz>;
+		temp-fifo-batch-rate = <LSM6DSV16X_DT_TEMP_BATCHED_AT_15Hz>;
+		int2-gpios =  <&arduino_header 10 GPIO_ACTIVE_HIGH>; /* D4 (PB5) */
+		drdy-pin = <2>;
+		drdy-pulsed;
+	};
+};
diff --git a/samples/sensor/stream_fifo/boards/nucleo_h503rb.conf b/samples/sensor/stream_fifo/boards/nucleo_h503rb.conf
new file mode 100644
index 00000000000..877b30fd2d6
--- /dev/null
+++ b/samples/sensor/stream_fifo/boards/nucleo_h503rb.conf
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_I2C_RTIO=y
+CONFIG_LSM6DSV16X_STREAM=y
+CONFIG_LSM6DSV16X_ENABLE_TEMP=y
diff --git a/samples/sensor/stream_fifo/boards/nucleo_h503rb.overlay b/samples/sensor/stream_fifo/boards/nucleo_h503rb.overlay
new file mode 100644
index 00000000000..95fbcacd48d
--- /dev/null
+++ b/samples/sensor/stream_fifo/boards/nucleo_h503rb.overlay
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/dt-bindings/sensor/lsm6dsv16x.h>
+
+
+/*
+ * Nucleo F401RE board + shield iks4a1
+ *
+ * This devicetree overlay file will be automatically picked by the Zephyr
+ * build system when building the sample for the nucleo_f401re board.
+ */
+
+/ {
+	aliases {
+		stream0 = &lsm6dsv16x_6b_x_nucleo_iks4a1;
+	};
+};
+
+&arduino_i2c {
+	lsm6dsv16x_6b_x_nucleo_iks4a1: lsm6dsv16x@6b {
+		compatible = "st,lsm6dsv16x";
+		reg = <0x6b>;
+		accel-odr = <LSM6DSV16X_DT_ODR_AT_480Hz>;
+		accel-range = <LSM6DSV16X_DT_FS_16G>;
+		gyro-odr = <LSM6DSV16X_DT_ODR_AT_480Hz>;
+		gyro-range = <LSM6DSV16X_DT_FS_500DPS>;
+		fifo-watermark = <64>;
+		accel-fifo-batch-rate = <LSM6DSV16X_DT_XL_BATCHED_AT_15Hz>;
+		gyro-fifo-batch-rate = <LSM6DSV16X_DT_GY_BATCHED_AT_15Hz>;
+		temp-fifo-batch-rate = <LSM6DSV16X_DT_TEMP_BATCHED_AT_15Hz>;
+
+		sflp-odr = <LSM6DSV16X_DT_SFLP_ODR_AT_15Hz>;
+		sflp-fifo-enable = <LSM6DSV16X_DT_SFLP_FIFO_GAME_ROTATION_GRAVITY_GBIAS>;
+		int2-gpios =  <&arduino_header 10 GPIO_ACTIVE_HIGH>; /* D4 (PB5) */
+		drdy-pin = <2>;
+		drdy-pulsed;
+	};
+};
diff --git a/samples/sensor/stream_fifo/boards/sensortile_box_pro.conf b/samples/sensor/stream_fifo/boards/sensortile_box_pro.conf
new file mode 100644
index 00000000000..c0b1e377b34
--- /dev/null
+++ b/samples/sensor/stream_fifo/boards/sensortile_box_pro.conf
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SPI_RTIO=y
+CONFIG_LSM6DSV16X_STREAM=y
+CONFIG_LSM6DSV16X_ENABLE_TEMP=y
diff --git a/samples/sensor/stream_fifo/boards/sensortile_box_pro.overlay b/samples/sensor/stream_fifo/boards/sensortile_box_pro.overlay
new file mode 100644
index 00000000000..4ed5566a47b
--- /dev/null
+++ b/samples/sensor/stream_fifo/boards/sensortile_box_pro.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/dt-bindings/sensor/lsm6dsv16x.h>
+
+
+/*
+ * This devicetree overlay file will be automatically picked by the Zephyr
+ * build system when building the sample for the sensortile_box_pro board.
+ */
+
+/ {
+	aliases {
+		stream0 = &lsm6dsv16x_0;
+	};
+};
+
+&spi2 {
+	lsm6dsv16x_0: lsm6dsv16x@0 {
+		compatible = "st,lsm6dsv16x";
+
+		accel-odr = <LSM6DSV16X_DT_ODR_AT_480Hz>;
+		accel-range = <LSM6DSV16X_DT_FS_16G>;
+		gyro-odr = <LSM6DSV16X_DT_ODR_AT_480Hz>;
+		gyro-range = <LSM6DSV16X_DT_FS_500DPS>;
+		fifo-watermark = <64>;
+		accel-fifo-batch-rate = <LSM6DSV16X_DT_XL_BATCHED_AT_15Hz>;
+		gyro-fifo-batch-rate = <LSM6DSV16X_DT_GY_BATCHED_AT_15Hz>;
+		temp-fifo-batch-rate = <LSM6DSV16X_DT_TEMP_BATCHED_AT_15Hz>;
+
+		sflp-odr = <LSM6DSV16X_DT_SFLP_ODR_AT_15Hz>;
+		sflp-fifo-enable = <LSM6DSV16X_DT_SFLP_FIFO_GAME_ROTATION_GRAVITY_GBIAS>;
+	};
+};
diff --git a/samples/sensor/stream_fifo/prj.conf b/samples/sensor/stream_fifo/prj.conf
new file mode 100644
index 00000000000..b638fffcb38
--- /dev/null
+++ b/samples/sensor/stream_fifo/prj.conf
@@ -0,0 +1,7 @@
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_STDOUT_CONSOLE=y
+CONFIG_SENSOR=y
+CONFIG_SENSOR_ASYNC_API=y
+CONFIG_CBPRINTF_FP_SUPPORT=y
diff --git a/samples/sensor/stream_fifo/sample.yaml b/samples/sensor/stream_fifo/sample.yaml
new file mode 100644
index 00000000000..a3cd7465ae6
--- /dev/null
+++ b/samples/sensor/stream_fifo/sample.yaml
@@ -0,0 +1,12 @@
+sample:
+  name: Stream FIFO sample
+tests:
+  sample.sensor.stream_fifo:
+    harness: console
+    tags: sensors
+    filter: dt_alias_exists("stream0")
+    harness_config:
+      type: one_line
+      regex:
+        - "^\\s*[0-9A-Za-z_,+-.]*@[0-9A-Fa-f]* \\[m\/s\\^2\\]:    \
+           \\(\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*,\\s*-?[0-9\\.]*\\)$"
diff --git a/samples/sensor/stream_fifo/src/main.c b/samples/sensor/stream_fifo/src/main.c
new file mode 100644
index 00000000000..45dd3cab8f4
--- /dev/null
+++ b/samples/sensor/stream_fifo/src/main.c
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/kernel.h>
+#include <zephyr/rtio/rtio.h>
+#include <zephyr/drivers/sensor.h>
+
+#define STREAMDEV_ALIAS(i) DT_ALIAS(_CONCAT(stream, i))
+#define STREAMDEV_DEVICE(i, _) \
+	IF_ENABLED(DT_NODE_EXISTS(STREAMDEV_ALIAS(i)), (DEVICE_DT_GET(STREAMDEV_ALIAS(i)),))
+#define NUM_SENSORS 1
+
+/* support up to 10 sensors */
+static const struct device *const sensors[] = { LISTIFY(10, STREAMDEV_DEVICE, ()) };
+
+#define STREAM_IODEV_SYM(id) CONCAT(stream_iodev, id)
+#define STREAM_IODEV_PTR(id, _) &STREAM_IODEV_SYM(id)
+
+#define STREAM_TRIGGERS					   \
+	{ SENSOR_TRIG_FIFO_FULL, SENSOR_STREAM_DATA_NOP }, \
+	{ SENSOR_TRIG_FIFO_WATERMARK, SENSOR_STREAM_DATA_INCLUDE }
+
+#define STREAM_DEFINE_IODEV(id, _)    \
+	SENSOR_DT_STREAM_IODEV(	      \
+		STREAM_IODEV_SYM(id), \
+		STREAMDEV_ALIAS(id),  \
+		STREAM_TRIGGERS);
+
+LISTIFY(NUM_SENSORS, STREAM_DEFINE_IODEV, (;));
+
+struct rtio_iodev *iodevs[NUM_SENSORS] = { LISTIFY(NUM_SENSORS, STREAM_IODEV_PTR, (,)) };
+
+RTIO_DEFINE_WITH_MEMPOOL(stream_ctx, NUM_SENSORS, NUM_SENSORS,
+			 NUM_SENSORS * 20, 256, sizeof(void *));
+
+struct sensor_chan_spec accel_chan = { SENSOR_CHAN_ACCEL_XYZ, 0 };
+struct sensor_chan_spec gyro_chan = { SENSOR_CHAN_GYRO_XYZ, 0 };
+struct sensor_chan_spec temp_chan = { SENSOR_CHAN_DIE_TEMP, 0 };
+struct sensor_chan_spec rot_vector_chan = { SENSOR_CHAN_GAME_ROTATION_VECTOR, 0 };
+struct sensor_chan_spec gravity_chan = { SENSOR_CHAN_GRAVITY_VECTOR, 0 };
+struct sensor_chan_spec gbias_chan = { SENSOR_CHAN_GBIAS_XYZ, 0 };
+
+#define TASK_STACK_SIZE           2048ul
+static K_THREAD_STACK_ARRAY_DEFINE(thread_stack, NUM_SENSORS, TASK_STACK_SIZE);
+static struct k_thread thread_id[NUM_SENSORS];
+
+static void print_stream(void *p1, void *p2, void *p3)
+{
+	const struct device *dev = (const struct device *)p1;
+	struct rtio_iodev *iodev = (struct rtio_iodev *)p2;
+	int rc = 0;
+	const struct sensor_decoder_api *decoder;
+	struct rtio_cqe *cqe;
+	uint8_t *buf;
+	uint32_t buf_len;
+	struct rtio_sqe *handle;
+	uint8_t accel_buf[128] = { 0 };
+	uint8_t gyro_buf[128] = { 0 };
+	uint8_t temp_buf[64] = { 0 };
+	uint8_t rot_vect_buf[128] = { 0 };
+	uint8_t gravity_buf[128] = { 0 };
+	uint8_t gbias_buf[128] = { 0 };
+	struct sensor_three_axis_data *accel_data = (struct sensor_three_axis_data *)accel_buf;
+	struct sensor_three_axis_data *gyro_data = (struct sensor_three_axis_data *)gyro_buf;
+	struct sensor_q31_data *temp_data = (struct sensor_q31_data *)temp_buf;
+	struct sensor_game_rotation_vector_data *rot_vect_data =
+				(struct sensor_game_rotation_vector_data *)rot_vect_buf;
+	struct sensor_three_axis_data *gravity_data = (struct sensor_three_axis_data *)gravity_buf;
+	struct sensor_three_axis_data *gbias_data = (struct sensor_three_axis_data *)gbias_buf;
+
+	/* Start the stream */
+	printk("sensor_stream\n");
+	sensor_stream(iodev, &stream_ctx, NULL, &handle);
+
+	while (1) {
+		cqe = rtio_cqe_consume_block(&stream_ctx);
+
+		if (cqe->result != 0) {
+			printk("async read failed %d\n", cqe->result);
+			return;
+		}
+
+		rc = rtio_cqe_get_mempool_buffer(&stream_ctx, cqe, &buf, &buf_len);
+
+		if (rc != 0) {
+			printk("get mempool buffer failed %d\n", rc);
+			return;
+		}
+
+		const struct device *sensor = dev;
+
+		rtio_cqe_release(&stream_ctx, cqe);
+
+		rc = sensor_get_decoder(sensor, &decoder);
+
+		if (rc != 0) {
+			printk("sensor_get_decoder failed %d\n", rc);
+			return;
+		}
+
+		/* Frame iterator values when data comes from a FIFO */
+		uint32_t accel_fit = 0, gyro_fit = 0;
+		uint32_t temp_fit = 0;
+		uint32_t rot_vect_fit = 0, gravity_fit = 0, gbias_fit = 0;
+
+		/* Number of sensor data frames */
+		uint16_t xl_count, gy_count, tp_count;
+		uint16_t rot_vect_count, gravity_count, gbias_count, frame_count;
+
+		rc = decoder->get_frame_count(buf, accel_chan, &xl_count);
+		rc += decoder->get_frame_count(buf, gyro_chan, &gy_count);
+		rc += decoder->get_frame_count(buf, temp_chan, &tp_count);
+		rc += decoder->get_frame_count(buf, rot_vector_chan, &rot_vect_count);
+		rc += decoder->get_frame_count(buf, gravity_chan, &gravity_count);
+		rc += decoder->get_frame_count(buf, gbias_chan, &gbias_count);
+
+		if (rc != 0) {
+			printk("sensor_get_frame failed %d\n", rc);
+			return;
+		}
+
+		frame_count = xl_count + gy_count + tp_count;
+		frame_count += rot_vect_count + gravity_count + gbias_count;
+
+		/* If a tap has occurred lets print it out */
+		if (decoder->has_trigger(buf, SENSOR_TRIG_TAP)) {
+			printk("Tap! Sensor %s\n", dev->name);
+		}
+
+		/* Decode all available sensor FIFO frames */
+		printk("FIFO count - %d\n", frame_count);
+
+		int i = 0;
+
+		while (i < frame_count) {
+			int8_t c = 0;
+
+			/* decode and print Accelerometer FIFO frames */
+			c = decoder->decode(buf, accel_chan, &accel_fit, 8, accel_data);
+
+			for (int k = 0; k < c; k++) {
+				printk("XL data for %s %lluns (%" PRIq(6) ", %" PRIq(6)
+				       ", %" PRIq(6) ")\n", dev->name,
+				       PRIsensor_three_axis_data_arg(*accel_data, k));
+			}
+			i += c;
+
+			/* decode and print Gyroscope FIFO frames */
+			c = decoder->decode(buf, gyro_chan, &gyro_fit, 8, gyro_data);
+
+			for (int k = 0; k < c; k++) {
+				printk("GY data for %s %lluns (%" PRIq(6) ", %" PRIq(6)
+				       ", %" PRIq(6) ")\n", dev->name,
+				       PRIsensor_three_axis_data_arg(*gyro_data, k));
+			}
+			i += c;
+
+			/* decode and print Temperature FIFO frames */
+			c = decoder->decode(buf, temp_chan, &temp_fit, 4, temp_data);
+
+			for (int k = 0; k < c; k++) {
+				printk("TP data for %s %lluns %s%d.%d °C\n", dev->name,
+				       PRIsensor_q31_data_arg(*temp_data, k));
+			}
+			i += c;
+
+			/* decode and print Game Rotation Vector FIFO frames */
+			c = decoder->decode(buf, rot_vector_chan, &rot_vect_fit, 8, rot_vect_data);
+
+			for (int k = 0; k < c; k++) {
+				printk("ROT data for %s %lluns (%" PRIq(6) ", %" PRIq(6)
+				       ", %" PRIq(6) ", %" PRIq(6) ")\n", dev->name,
+				       PRIsensor_game_rotation_vector_data_arg(*rot_vect_data, k));
+			}
+			i += c;
+
+			/* decode and print Gravity Vector FIFO frames */
+			c = decoder->decode(buf, gravity_chan, &gravity_fit, 8, gravity_data);
+
+			for (int k = 0; k < c; k++) {
+				printk("GV data for %s %lluns (%" PRIq(6) ", %" PRIq(6)
+				       ", %" PRIq(6) ")\n", dev->name,
+				       PRIsensor_three_axis_data_arg(*gravity_data, k));
+			}
+			i += c;
+
+			/* decode and print Gyroscope GBIAS FIFO frames */
+			c = decoder->decode(buf, gbias_chan, &gbias_fit, 8, gbias_data);
+
+			for (int k = 0; k < c; k++) {
+				printk("GY GBIAS data for %s %lluns (%" PRIq(6) ", %" PRIq(6)
+				       ", %" PRIq(6) ")\n", dev->name,
+				       PRIsensor_three_axis_data_arg(*gbias_data, k));
+			}
+			i += c;
+		}
+
+		rtio_release_buffer(&stream_ctx, buf, buf_len);
+	}
+}
+
+static void check_sensor_is_off(const struct device *dev)
+{
+	int ret;
+	struct sensor_value odr;
+
+	ret = sensor_attr_get(dev, SENSOR_CHAN_ACCEL_XYZ, SENSOR_ATTR_SAMPLING_FREQUENCY, &odr);
+
+	/* Check if accel is off */
+	if (ret != 0 || (odr.val1 == 0 && odr.val2 == 0)) {
+		printk("%s WRN : accelerometer device is off\n", dev->name);
+	}
+
+	ret = sensor_attr_get(dev, SENSOR_CHAN_GYRO_XYZ, SENSOR_ATTR_SAMPLING_FREQUENCY, &odr);
+
+	/* Check if gyro is off */
+	if (ret != 0 || (odr.val1 == 0 && odr.val2 == 0)) {
+		printk("%s WRN : gyroscope device is off\n", dev->name);
+	}
+}
+
+int main(void)
+{
+	struct sensor_value gbias[3];
+
+	for (size_t i = 0; i < ARRAY_SIZE(sensors); i++) {
+		if (!device_is_ready(sensors[i])) {
+			printk("sensor: device %s not ready.\n", sensors[i]->name);
+			return 0;
+		}
+		check_sensor_is_off(sensors[i]);
+
+		/*
+		 * Set GBIAS as 0.5 rad/s, -1 rad/s, 0.2 rad/s
+		 *
+		 * (here application should initialize gbias x/y/z with latest values
+		 * calculated from previous run and probably saved to non volatile memory)
+		 */
+		gbias[0].val1 = 0;
+		gbias[0].val2 = 500000;
+		gbias[1].val1 = -1;
+		gbias[1].val2 = 0;
+		gbias[2].val1 = 0;
+		gbias[2].val2 = 200000;
+		sensor_attr_set(sensors[i], SENSOR_CHAN_GBIAS_XYZ, SENSOR_ATTR_OFFSET, gbias);
+
+		k_thread_create(&thread_id[i], thread_stack[i], TASK_STACK_SIZE, print_stream,
+			(void *)sensors[i], (void *)iodevs[i], NULL, K_PRIO_COOP(5),
+			K_INHERIT_PERMS, K_FOREVER);
+		k_thread_start(&thread_id[i]);
+	}
+
+	return 0;
+}
diff --git a/samples/sensor/tdk_apex/README.rst b/samples/sensor/tdk_apex/README.rst
index 9d6f9c20d13..e38188b6ef8 100644
--- a/samples/sensor/tdk_apex/README.rst
+++ b/samples/sensor/tdk_apex/README.rst
@@ -51,7 +51,7 @@ to be aliased as ``tdk-apex-sensorN`` where ``N`` goes from ``0`` to ``9``. For
 		};
 	};
 
-This sample supports APEX feature of TDK device. It needs to be specified as bellow:
+This sample supports APEX feature of TDK device. It needs to be specified as below:
 
 .. code-block:: devicetree
 
diff --git a/samples/sensor/tdk_apex/prj.conf b/samples/sensor/tdk_apex/prj.conf
index 30d93977483..7731b5b6de1 100644
--- a/samples/sensor/tdk_apex/prj.conf
+++ b/samples/sensor/tdk_apex/prj.conf
@@ -16,4 +16,4 @@ CONFIG_CBPRINTF_FP_SUPPORT=y
 CONFIG_USE_SEGGER_RTT=n
 
 # Trigger mode: sample is using interrupt triggering
-CONFIG_ICM42670_TRIGGER_OWN_THREAD=y
+CONFIG_ICM42X70_TRIGGER_OWN_THREAD=y
diff --git a/samples/sensor/th02/sample.yaml b/samples/sensor/th02/sample.yaml
index eace959779b..b0ab5881f6f 100644
--- a/samples/sensor/th02/sample.yaml
+++ b/samples/sensor/th02/sample.yaml
@@ -6,3 +6,5 @@ tests:
     tags: sensors
     depends_on: i2c
     filter: dt_compat_enabled("hoperf,th02") and dt_compat_enabled("seeed,grove-lcd-rgb")
+    integration_platforms:
+      - frdm_k64f
diff --git a/samples/sensor/thermometer/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/samples/sensor/thermometer/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..9c2991a4d23
--- /dev/null
+++ b/samples/sensor/thermometer/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <freq.h>
+
+/ {
+	aliases {
+		ambient-temp0 = &p3t1755;
+	};
+};
+
+&i3c1 {
+	status = "okay";
+
+	i2c-scl-hz = <DT_FREQ_K(400)>;
+	i3c-scl-hz = <DT_FREQ_M(4)>;
+	i3c-od-scl-hz = <DT_FREQ_K(1500)>;
+
+	p3t1755: p3t1755@4800000236152a0090 {
+		compatible = "nxp,p3t1755";
+		reg = <0x48 0x0236 0x152a0090>;
+		status = "okay";
+	};
+};
diff --git a/samples/sensor/thermometer/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay b/samples/sensor/thermometer/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay
new file mode 100644
index 00000000000..9c2991a4d23
--- /dev/null
+++ b/samples/sensor/thermometer/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <freq.h>
+
+/ {
+	aliases {
+		ambient-temp0 = &p3t1755;
+	};
+};
+
+&i3c1 {
+	status = "okay";
+
+	i2c-scl-hz = <DT_FREQ_K(400)>;
+	i3c-scl-hz = <DT_FREQ_M(4)>;
+	i3c-od-scl-hz = <DT_FREQ_K(1500)>;
+
+	p3t1755: p3t1755@4800000236152a0090 {
+		compatible = "nxp,p3t1755";
+		reg = <0x48 0x0236 0x152a0090>;
+		status = "okay";
+	};
+};
diff --git a/samples/sensor/thermometer/sample.yaml b/samples/sensor/thermometer/sample.yaml
index c2f13aa26cb..c482ee6dc34 100644
--- a/samples/sensor/thermometer/sample.yaml
+++ b/samples/sensor/thermometer/sample.yaml
@@ -18,10 +18,12 @@ tests:
       - frdm_k22f             # tcn75a
       - robokit1              # ntc_thermistor
       - adi_eval_adin1110ebz  # adt7420
+      - frdm_rw612            # p3t1755
     extra_args:
       - platform:mimxrt1180_evk/mimxrt1189/cm33:SHIELD=p3t1755dp_ard_i2c
       - platform:mimxrt1180_evk/mimxrt1189/cm7:SHIELD=p3t1755dp_ard_i2c
       - platform:frdm_mcxn236/mcxn236:SHIELD=p3t1755dp_ard_i2c
+      - platform:mimxrt700_evk/mimxrt798s/cm33_cpu0:SHIELD=p3t1755dp_ard_i2c
   sample.sensor.thermometer_i3c:
     tags: sensors
     harness_config:
diff --git a/samples/sensor/tmp116/CMakeLists.txt b/samples/sensor/tmp116/CMakeLists.txt
deleted file mode 100644
index ccbe7ff815a..00000000000
--- a/samples/sensor/tmp116/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-cmake_minimum_required(VERSION 3.20.0)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(tmp116)
-
-FILE(GLOB app_sources src/*.c)
-target_sources(app PRIVATE ${app_sources})
diff --git a/samples/sensor/tmp116/README.rst b/samples/sensor/tmp116/README.rst
deleted file mode 100644
index 87c91f83f3c..00000000000
--- a/samples/sensor/tmp116/README.rst
+++ /dev/null
@@ -1,63 +0,0 @@
-.. _ti_tmp116_sample:
-
-TI_TMP116 Sample
-################
-
-Description
-***********
-
-This sample application periodically takes temperature readings using the ti_tmp116
-sensor driver. The result is written to the console. This sample also included the code
-to use the  features provided by TMP117, which is a sensor similar to TMP116
-
-Requirements
-************
-
-This sample needs a TI TMP116 or TI TMP117 sensor connected to the target board's I2C
-connector.
-
-
-Wiring
-******
-
-This sample is tested with Nucleo STM32F401RE board.
-
-The sensor operates at 3.3V and uses I2C to communicate with the board.
-
-External Wires:
-
-* Breakout **GND** pin <--> Nucleo **GND** pin
-* Breakout **VCC** pin <--> Nucleo **3V3** pin
-* Breakout **SDA** pin <--> Nucleo **CN5-D14** pin
-* Breakout **SCL** pin <--> Nucleo **CN5-D15** pin
-
-Building and Running
-********************
-
-In order to build the sample, connect the board to the computer with a USB cable and enter the
-following commands:
-
-.. zephyr-app-commands::
-   :zephyr-app: samples/sensor/tmp116
-   :board: nucleo_f401re
-   :goals: build flash
-   :compact:
-
-Sample Output
-*************
-The output can be seen via a terminal emulator (e.g. minicom). Connect the board with a USB cable
-to the computer and open /dev/ttyACM0 with the below serial settings:
-
-* Baudrate: 115200
-* Parity: None
-* Data: 8
-* Stop bits: 1
-
-The output should look like this:
-
-.. code-block:: console
-
-    Device TMP116 - 0x200010a8 is ready
-    temp is 26.7031250 oC
-    temp is 26.7109375 oC
-    ...
diff --git a/samples/sensor/tmp116/boards/nucleo_f401re.overlay b/samples/sensor/tmp116/boards/nucleo_f401re.overlay
deleted file mode 100644
index 0ab15f7bf64..00000000000
--- a/samples/sensor/tmp116/boards/nucleo_f401re.overlay
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2019 Centaur Analytics, Inc
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&i2c1 {
-
-	ti_tmp116: ti_tmp116@4b {
-		compatible = "ti,tmp116";
-		reg = <0x4B>;
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		eeprom: ti_tmp116_eeprom@0 {
-			compatible = "ti,tmp116-eeprom";
-			reg = <0x0>;
-			read-only;
-		};
-	};
-
-};
diff --git a/samples/sensor/tmp116/prj.conf b/samples/sensor/tmp116/prj.conf
deleted file mode 100644
index 27651f09f3f..00000000000
--- a/samples/sensor/tmp116/prj.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_STDOUT_CONSOLE=y
-CONFIG_I2C=y
-CONFIG_SENSOR=y
-CONFIG_SENSOR_INIT_PRIORITY=90
-CONFIG_EEPROM=y
-CONFIG_EEPROM_INIT_PRIORITY=91
-CONFIG_EEPROM_TMP116=y
diff --git a/samples/sensor/tmp116/sample.yaml b/samples/sensor/tmp116/sample.yaml
deleted file mode 100644
index 3527b16edca..00000000000
--- a/samples/sensor/tmp116/sample.yaml
+++ /dev/null
@@ -1,15 +0,0 @@
-sample:
-  name: TI TMP116 Sensor Sample
-tests:
-  sample.sensor.tmp116:
-    harness: console
-    platform_allow: nucleo_f401re
-    integration_platforms:
-      - nucleo_f401re
-    tags: sensors
-    depends_on: i2c
-    harness_config:
-      type: one_line
-      regex:
-        - "temp is (.*) oC"
-      fixture: fixture_i2c_tmp116
diff --git a/samples/sensor/tmp116/src/main.c b/samples/sensor/tmp116/src/main.c
deleted file mode 100644
index d594a2664d7..00000000000
--- a/samples/sensor/tmp116/src/main.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (c) 2019 Centaur Analytics, Inc
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/kernel.h>
-#include <zephyr/device.h>
-#include <zephyr/drivers/sensor.h>
-#include <zephyr/drivers/eeprom.h>
-#include <zephyr/drivers/sensor/tmp116.h>
-#include <zephyr/sys/printk.h>
-#include <zephyr/sys/__assert.h>
-
-#define TMP116_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(ti_tmp116)
-#define TMP116_EEPROM_NODE DT_CHILD(TMP116_NODE, ti_tmp116_eeprom_0)
-
-static uint8_t eeprom_content[EEPROM_TMP116_SIZE];
-
-int main(void)
-{
-	const struct device *const dev = DEVICE_DT_GET(TMP116_NODE);
-	const struct device *const eeprom = DEVICE_DT_GET(TMP116_EEPROM_NODE);
-	struct sensor_value temp_value;
-
-	/* offset to be added to the temperature
-	 * only supported by TMP117
-	 */
-	struct sensor_value offset_value;
-	int ret;
-
-	__ASSERT(device_is_ready(dev), "TMP116 device not ready");
-	__ASSERT(device_is_ready(eeprom), "TMP116 eeprom device not ready");
-
-	printk("Device %s - %p is ready\n", dev->name, dev);
-
-	ret = eeprom_read(eeprom, 0, eeprom_content, sizeof(eeprom_content));
-	if (ret == 0) {
-		printk("eeprom content %02x%02x%02x%02x%02x%02x%02x%02x\n",
-		       eeprom_content[0], eeprom_content[1],
-		       eeprom_content[2], eeprom_content[3],
-		       eeprom_content[4], eeprom_content[5],
-		       eeprom_content[6], eeprom_content[7]);
-	} else {
-		printk("Failed to get eeprom content\n");
-	}
-
-	/*
-	 * if an offset of 2.5 oC is to be added,
-	 * set val1 = 2 and val2 = 500000.
-	 * See struct sensor_value documentation for more details.
-	 */
-	offset_value.val1 = 0;
-	offset_value.val2 = 0;
-	ret = sensor_attr_set(dev, SENSOR_CHAN_AMBIENT_TEMP,
-			      SENSOR_ATTR_OFFSET, &offset_value);
-	if (ret) {
-		printk("sensor_attr_set failed ret = %d\n", ret);
-		printk("SENSOR_ATTR_OFFSET is only supported by TMP117\n");
-	}
-	while (1) {
-		ret = sensor_sample_fetch(dev);
-		if (ret) {
-			printk("Failed to fetch measurements (%d)\n", ret);
-			return 0;
-		}
-
-		ret = sensor_channel_get(dev, SENSOR_CHAN_AMBIENT_TEMP,
-					 &temp_value);
-		if (ret) {
-			printk("Failed to get measurements (%d)\n", ret);
-			return 0;
-		}
-
-		printk("temp is %d.%d oC\n", temp_value.val1, temp_value.val2);
-
-		k_sleep(K_MSEC(1000));
-	}
-	return 0;
-}
diff --git a/samples/sensor/tmp11x/CMakeLists.txt b/samples/sensor/tmp11x/CMakeLists.txt
new file mode 100644
index 00000000000..9241a3e9b27
--- /dev/null
+++ b/samples/sensor/tmp11x/CMakeLists.txt
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(tmp11x)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/samples/sensor/tmp11x/README.rst b/samples/sensor/tmp11x/README.rst
new file mode 100644
index 00000000000..1cc257ec70d
--- /dev/null
+++ b/samples/sensor/tmp11x/README.rst
@@ -0,0 +1,63 @@
+.. _ti_tmp11x_sample:
+
+TI_TMP11X Sample
+################
+
+Description
+***********
+
+This sample application periodically takes temperature readings using the ti_tmp11x
+sensor driver. The result is written to the console. This sample also included the code
+to use the features provided by TMP117 and TMP119, which are sensors similar to TMP116.
+
+Requirements
+************
+
+This sample needs a TI TMP116, TI TMP117 or TI TMP119 sensor connected to the target board's I2C
+connector.
+
+
+Wiring
+******
+
+This sample is tested with Nucleo STM32F401RE board.
+
+The sensor operates at 3.3V and uses I2C to communicate with the board.
+
+External Wires:
+
+* Breakout **GND** pin <--> Nucleo **GND** pin
+* Breakout **VCC** pin <--> Nucleo **3V3** pin
+* Breakout **SDA** pin <--> Nucleo **CN5-D14** pin
+* Breakout **SCL** pin <--> Nucleo **CN5-D15** pin
+
+Building and Running
+********************
+
+In order to build the sample, connect the board to the computer with a USB cable and enter the
+following commands:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/sensor/tmp11x
+   :board: nucleo_f401re
+   :goals: build flash
+   :compact:
+
+Sample Output
+*************
+The output can be seen via a terminal emulator (e.g. minicom). Connect the board with a USB cable
+to the computer and open /dev/ttyACM0 with the below serial settings:
+
+* Baudrate: 115200
+* Parity: None
+* Data: 8
+* Stop bits: 1
+
+The output should look like this:
+
+.. code-block:: console
+
+    Device TMP11X - 0x200010a8 is ready
+    temp is 26.7031250 oC
+    temp is 26.7109375 oC
+    ...
diff --git a/samples/sensor/tmp11x/boards/nucleo_f401re.overlay b/samples/sensor/tmp11x/boards/nucleo_f401re.overlay
new file mode 100644
index 00000000000..ba29a788bef
--- /dev/null
+++ b/samples/sensor/tmp11x/boards/nucleo_f401re.overlay
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&i2c1 {
+
+	ti_tmp11x: ti_tmp11x@4b {
+		compatible = "ti,tmp11x";
+		reg = <0x4B>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		eeprom: ti_tmp11x_eeprom@0 {
+			compatible = "ti,tmp11x-eeprom";
+			reg = <0x0>;
+			read-only;
+		};
+	};
+
+};
diff --git a/samples/sensor/tmp11x/prj.conf b/samples/sensor/tmp11x/prj.conf
new file mode 100644
index 00000000000..8bd0810adcc
--- /dev/null
+++ b/samples/sensor/tmp11x/prj.conf
@@ -0,0 +1,7 @@
+CONFIG_STDOUT_CONSOLE=y
+CONFIG_I2C=y
+CONFIG_SENSOR=y
+CONFIG_SENSOR_INIT_PRIORITY=90
+CONFIG_EEPROM=y
+CONFIG_EEPROM_INIT_PRIORITY=91
+CONFIG_EEPROM_TMP11X=y
diff --git a/samples/sensor/tmp11x/sample.yaml b/samples/sensor/tmp11x/sample.yaml
new file mode 100644
index 00000000000..3246dffedbb
--- /dev/null
+++ b/samples/sensor/tmp11x/sample.yaml
@@ -0,0 +1,15 @@
+sample:
+  name: TI TMP11X Sensor Sample
+tests:
+  sample.sensor.tmp11x:
+    harness: console
+    platform_allow: nucleo_f401re
+    integration_platforms:
+      - nucleo_f401re
+    tags: sensors
+    depends_on: i2c
+    harness_config:
+      type: one_line
+      regex:
+        - "temp is (.*) oC"
+      fixture: fixture_i2c_tmp11x
diff --git a/samples/sensor/tmp11x/src/main.c b/samples/sensor/tmp11x/src/main.c
new file mode 100644
index 00000000000..1aaa8eb9da8
--- /dev/null
+++ b/samples/sensor/tmp11x/src/main.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2019 Centaur Analytics, Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/eeprom.h>
+#include <zephyr/drivers/sensor/tmp11x.h>
+#include <zephyr/sys/printk.h>
+#include <zephyr/sys/__assert.h>
+
+#define TMP11X_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(ti_tmp11x)
+#define TMP11X_EEPROM_NODE DT_CHILD(TMP11X_NODE, ti_tmp11x_eeprom_0)
+
+static uint8_t eeprom_content[EEPROM_TMP11X_SIZE];
+
+int main(void)
+{
+	const struct device *const dev = DEVICE_DT_GET(TMP11X_NODE);
+	const struct device *const eeprom = DEVICE_DT_GET(TMP11X_EEPROM_NODE);
+	struct sensor_value temp_value;
+
+	/* offset to be added to the temperature
+	 * only supported by TMP117 and TMP119
+	 */
+	struct sensor_value offset_value;
+	int ret;
+
+	__ASSERT(device_is_ready(dev), "tmp11x device not ready");
+	__ASSERT(device_is_ready(eeprom), "tmp11x eeprom device not ready");
+
+	printk("Device %s - %p is ready\n", dev->name, dev);
+
+	ret = eeprom_read(eeprom, 0, eeprom_content, sizeof(eeprom_content));
+	if (ret == 0) {
+		printk("eeprom content %02x%02x%02x%02x%02x%02x%02x%02x\n",
+		       eeprom_content[0], eeprom_content[1],
+		       eeprom_content[2], eeprom_content[3],
+		       eeprom_content[4], eeprom_content[5],
+		       eeprom_content[6], eeprom_content[7]);
+	} else {
+		printk("Failed to get eeprom content\n");
+	}
+
+	/*
+	 * if an offset of 2.5 oC is to be added,
+	 * set val1 = 2 and val2 = 500000.
+	 * See struct sensor_value documentation for more details.
+	 */
+	offset_value.val1 = 0;
+	offset_value.val2 = 0;
+	ret = sensor_attr_set(dev, SENSOR_CHAN_AMBIENT_TEMP,
+			      SENSOR_ATTR_OFFSET, &offset_value);
+	if (ret) {
+		printk("sensor_attr_set failed ret = %d\n", ret);
+		printk("SENSOR_ATTR_OFFSET is only supported by TMP117 and TMP119\n");
+	}
+	while (1) {
+		ret = sensor_sample_fetch(dev);
+		if (ret) {
+			printk("Failed to fetch measurements (%d)\n", ret);
+			return 0;
+		}
+
+		ret = sensor_channel_get(dev, SENSOR_CHAN_AMBIENT_TEMP,
+					 &temp_value);
+		if (ret) {
+			printk("Failed to get measurements (%d)\n", ret);
+			return 0;
+		}
+
+		printk("temp is %d.%d oC\n", temp_value.val1, temp_value.val2);
+
+		k_sleep(K_MSEC(1000));
+	}
+	return 0;
+}
diff --git a/samples/sensor/veaa_x_3/sample.yaml b/samples/sensor/veaa_x_3/sample.yaml
index 0191620ffb6..89be41f00ed 100644
--- a/samples/sensor/veaa_x_3/sample.yaml
+++ b/samples/sensor/veaa_x_3/sample.yaml
@@ -8,3 +8,5 @@ tests:
     depends_on:
       - adc
       - dac
+    integration_platforms:
+      - nucleo_h563zi
diff --git a/samples/sensor/veml6031/CMakeLists.txt b/samples/sensor/veml6031/CMakeLists.txt
new file mode 100644
index 00000000000..641ae9ad6ec
--- /dev/null
+++ b/samples/sensor/veml6031/CMakeLists.txt
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(veml6031)
+
+target_sources(app PRIVATE src/main.c)
diff --git a/samples/sensor/veml6031/README.rst b/samples/sensor/veml6031/README.rst
new file mode 100644
index 00000000000..e686ef373f1
--- /dev/null
+++ b/samples/sensor/veml6031/README.rst
@@ -0,0 +1,92 @@
+.. zephyr:code-sample:: veml6031
+   :name: VEML6031 High Accuracy Ambient Light Sensor
+   :relevant-api: sensor_interface
+
+   Get ambient light data from a VEML4040 sensor (polling mode).
+
+Overview
+********
+
+ This sample measures the ambient light for all possible combinations of sensor
+ attributes. There are:
+ - integration time
+ - effective photodiode size
+ - gain
+ These attributes can be used to put the sensor in an optimal working area.
+ When the light value reaches the maximum raw value (0xFFFF) an error is
+ returned to indicate the out of bounds situation to the user program.
+ With this program the raw value is also printed out together with the
+ attributes to be able to select good attribute values.
+ Interrupt and trigger mode is not supported so far, but planned for future
+ development.
+
+Requirements
+************
+
+ This sample uses the VEML6031 sensor controlled using the I2C-2 interface at
+ the Olimex-STM32-E407 board on feather PF0 and PF1.
+
+References
+**********
+
+ - VEML6031: https://www.vishay.com/docs/80007/veml6031x00.pdf
+
+Building and Running
+********************
+
+ This project outputs sensor data to the console. It requires a VEML6031
+ sensor to be connected to the desired board.
+
+ .. zephyr-app-commands::
+    :zephyr-app: samples/sensor/veml6031/
+    :goals: build flash
+
+
+Sample Output
+=============
+
+ .. code-block:: console
+
+    Test all attributes for a good guess of attribute usage away of saturation.
+    Light (lux):   6179 ALS (raw):   7100 IR (raw):     27   it: 0 div4: 0 gain: 0  --
+    Light (lux):   1500 ALS (raw):   3447 IR (raw):     34   it: 0 div4: 0 gain: 1  --
+    Light (lux):   4664 ALS (raw):   3537 IR (raw):     17   it: 0 div4: 0 gain: 2  --
+    Light (lux):   5601 ALS (raw):   3218 IR (raw):     13   it: 0 div4: 0 gain: 3  --
+    Light (lux):   1302 ALS (raw):    374 IR (raw):      5   it: 0 div4: 1 gain: 0  --
+    Light (lux):   5584 ALS (raw):   3208 IR (raw):     11   it: 0 div4: 1 gain: 1  --
+    Light (lux):   5285 ALS (raw):   1002 IR (raw):      3   it: 0 div4: 1 gain: 2  --
+    Light (lux):   1455 ALS (raw):    209 IR (raw):      2   it: 0 div4: 1 gain: 3  --
+    Light (lux):   4925 ALS (raw):  11317 IR (raw):     50   it: 1 div4: 0 gain: 0  --
+    Light (lux):   3916 ALS (raw):  17999 IR (raw):     90   it: 1 div4: 0 gain: 1  --
+    Light (lux):   2796 ALS (raw):   4299 IR (raw):     28   it: 1 div4: 0 gain: 2  --
+    Light (lux):   5178 ALS (raw):   5950 IR (raw):     26   it: 1 div4: 0 gain: 3  --
+    Light (lux):   4339 ALS (raw):   2493 IR (raw):     12   it: 1 div4: 1 gain: 0  --
+    Light (lux):   2186 ALS (raw):   2512 IR (raw):     19   it: 1 div4: 1 gain: 1  --
+    Light (lux):   5578 ALS (raw):   2115 IR (raw):      8   it: 1 div4: 1 gain: 2  --
+    Light (lux):   4494 ALS (raw):   1291 IR (raw):      6   it: 1 div4: 1 gain: 3  --
+    Light (lux):   3675 ALS (raw):  16892 IR (raw):     93   it: 2 div4: 0 gain: 0  --
+    Light (lux):   3209 ALS (raw):  29495 IR (raw):    172   it: 2 div4: 0 gain: 1  --
+    Light (lux):   4520 ALS (raw):  13710 IR (raw):     66   it: 2 div4: 0 gain: 2  --
+    Light (lux):   4215 ALS (raw):   9687 IR (raw):     49   it: 2 div4: 0 gain: 3  --
+    Light (lux):   3492 ALS (raw):   4013 IR (raw):     22   it: 2 div4: 1 gain: 0  --
+    Light (lux):   3786 ALS (raw):   8700 IR (raw):     43   it: 2 div4: 1 gain: 1  --
+    Light (lux):   4735 ALS (raw):   3591 IR (raw):     15   it: 2 div4: 1 gain: 2  --
+    Light (lux):   3779 ALS (raw):   2171 IR (raw):     11   it: 2 div4: 1 gain: 3  --
+    Light (lux):   3848 ALS (raw):  35376 IR (raw):    188   it: 3 div4: 0 gain: 0  --
+    Light (lux):   3565 ALS (raw):  65535 IR (raw):    359   it: 3 div4: 0 gain: 1  --  OVERFLOW
+    Light (lux):   4333 ALS (raw):  26297 IR (raw):    130   it: 3 div4: 0 gain: 2  --
+    Light (lux):   3576 ALS (raw):  16435 IR (raw):     93   it: 3 div4: 0 gain: 3  --
+    Light (lux):   4409 ALS (raw):  10133 IR (raw):     47   it: 3 div4: 1 gain: 0  --
+    Light (lux):   3395 ALS (raw):  15606 IR (raw):     85   it: 3 div4: 1 gain: 1  --
+    Light (lux):   4519 ALS (raw):   6854 IR (raw):     31   it: 3 div4: 1 gain: 2  --
+    Light (lux):   3694 ALS (raw):   4245 IR (raw):     23   it: 3 div4: 1 gain: 3  --
+    Light (lux):   3565 ALS (raw):  65535 IR (raw):    376   it: 4 div4: 0 gain: 0  --  OVERFLOW
+    Light (lux):   1782 ALS (raw):  65535 IR (raw):    723   it: 4 div4: 0 gain: 1  --  OVERFLOW
+    Light (lux):   3992 ALS (raw):  48450 IR (raw):    253   it: 4 div4: 0 gain: 2  --
+    Light (lux):   3943 ALS (raw):  36247 IR (raw):    191   it: 4 div4: 0 gain: 3  --
+    Light (lux):   3970 ALS (raw):  18248 IR (raw):     92   it: 4 div4: 1 gain: 0  --
+    Light (lux):   3814 ALS (raw):  35064 IR (raw):    176   it: 4 div4: 1 gain: 1  --
+    Light (lux):   4082 ALS (raw):  12381 IR (raw):     62   it: 4 div4: 1 gain: 2  --
+    Light (lux):   4052 ALS (raw):   9311 IR (raw):     47   it: 4 div4: 1 gain: 3  --
+    [...]
+    Test finished.
diff --git a/samples/sensor/veml6031/boards/olimex_stm32_e407.overlay b/samples/sensor/veml6031/boards/olimex_stm32_e407.overlay
new file mode 100644
index 00000000000..d6b785d0839
--- /dev/null
+++ b/samples/sensor/veml6031/boards/olimex_stm32_e407.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2025 Andreas Klinger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	i2c2_sda_pf0: i2c2_sda_pf0 {
+		pinmux = < 0xa04 >;
+		bias-pull-up;
+		drive-open-drain;
+	};
+	i2c2_scl_pf1: i2c2_scl_pf1 {
+		pinmux = < 0xa24 >;
+		bias-pull-up;
+		drive-open-drain;
+	};
+};
+
+&i2c2 {
+	pinctrl-0 = < &i2c2_scl_pf1 &i2c2_sda_pf0 >;
+	pinctrl-names = "default";
+	status = "okay";
+	light: light@29 {
+		compatible = "vishay,veml6031";
+		reg = <0x29>;
+	};
+};
diff --git a/samples/sensor/veml6031/prj.conf b/samples/sensor/veml6031/prj.conf
new file mode 100644
index 00000000000..42fcd3c973b
--- /dev/null
+++ b/samples/sensor/veml6031/prj.conf
@@ -0,0 +1 @@
+CONFIG_SENSOR=y
diff --git a/samples/sensor/veml6031/sample.yaml b/samples/sensor/veml6031/sample.yaml
new file mode 100644
index 00000000000..9e0792971af
--- /dev/null
+++ b/samples/sensor/veml6031/sample.yaml
@@ -0,0 +1,10 @@
+sample:
+  name: VEML6031 Sensor Sample
+tests:
+  sample.sensor.veml6031:
+    harness: sensor
+    platform_allow: olimex_stm32_e407
+    integration_platforms:
+      - olimex_stm32_e407
+    tags: sensors
+    filter: dt_compat_enabled("vishay,veml6031")
diff --git a/samples/sensor/veml6031/src/main.c b/samples/sensor/veml6031/src/main.c
new file mode 100644
index 00000000000..97239aa32a0
--- /dev/null
+++ b/samples/sensor/veml6031/src/main.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2025 Andreas Klinger
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+
+#include <zephyr/sys/printk.h>
+#include <zephyr/sys_clock.h>
+#include <stdio.h>
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/i2c.h>
+
+#include <zephyr/drivers/sensor/veml6031.h>
+
+static void read_with_attr(const struct device *dev, int it, int div4, int gain)
+{
+	int ret;
+	struct sensor_value light;
+	struct sensor_value als_raw;
+	struct sensor_value ir_raw;
+	struct sensor_value sen;
+
+	sen.val2 = 0;
+
+	sen.val1 = it;
+	ret = sensor_attr_set(dev, SENSOR_CHAN_LIGHT, SENSOR_ATTR_VEML6031_IT, &sen);
+	if (ret) {
+		printf("Failed to set it attribute ret: %d\n", ret);
+	}
+	sen.val1 = div4;
+	ret = sensor_attr_set(dev, SENSOR_CHAN_LIGHT, SENSOR_ATTR_VEML6031_DIV4, &sen);
+	if (ret) {
+		printf("Failed to set div4 attribute ret: %d\n", ret);
+	}
+	sen.val1 = gain;
+	ret = sensor_attr_set(dev, SENSOR_CHAN_LIGHT, SENSOR_ATTR_VEML6031_GAIN, &sen);
+	if (ret) {
+		printf("Failed to set gain attribute ret: %d\n", ret);
+	}
+
+	ret = sensor_sample_fetch(dev);
+	if ((ret < 0) && (ret != -E2BIG)) {
+		printf("sample update error. ret: %d\n", ret);
+	}
+
+	sensor_channel_get(dev, SENSOR_CHAN_LIGHT, &light);
+
+	sensor_channel_get(dev, SENSOR_CHAN_VEML6031_ALS_RAW_COUNTS, &als_raw);
+
+	sensor_channel_get(dev, SENSOR_CHAN_VEML6031_IR_RAW_COUNTS, &ir_raw);
+
+	printf("Light (lux): %6d ALS (raw): %6d IR (raw): %6d "
+	       "  it: %d div4: %d gain: %d  --  %s\n",
+	       light.val1, als_raw.val1, ir_raw.val1, it, div4, gain,
+	       ret == -E2BIG ? "OVERFLOW"
+	       : ret         ? "ERROR"
+			     : "");
+}
+
+static void read_with_all_attr(const struct device *dev)
+{
+	int it, div4, gain;
+
+	for (it = VEML6031_IT_3_125; it <= VEML6031_IT_400; it++) {
+		for (div4 = VEML6031_SIZE_4_4; div4 <= VEML6031_SIZE_1_4; div4++) {
+			for (gain = VEML6031_GAIN_1; gain <= VEML6031_GAIN_0_5; gain++) {
+				read_with_attr(dev, it, div4, gain);
+			}
+		}
+	}
+}
+
+int main(void)
+{
+	const struct device *const veml = DEVICE_DT_GET(DT_NODELABEL(light));
+
+	if (!device_is_ready(veml)) {
+		printk("sensor: device not ready.\n");
+		return 0;
+	}
+
+	printf("Test all attributes for a good guess of attribute usage away of saturation.\n");
+	read_with_all_attr(veml);
+	printf("Test finished.\n");
+
+	return 0;
+}
diff --git a/samples/sensor/vl53l0x/README.rst b/samples/sensor/vl53l0x/README.rst
index 53f4bc9e1f9..4d7fbc6f020 100644
--- a/samples/sensor/vl53l0x/README.rst
+++ b/samples/sensor/vl53l0x/README.rst
@@ -9,7 +9,7 @@ Overview
 
 This sample periodically measures distance between vl53l0x sensor
 and target. The result is displayed on the console.
-It also shows how we can use the vl53l0x as a proximity sensor.
+It shows the usage of all available channels including private ones.
 
 Requirements
 ************
@@ -24,24 +24,33 @@ References
 Building and Running
 ********************
 
- This project outputs sensor data to the console. It requires a VL53L0X
- sensor, which is present on the disco_l475_iot1 board.
+This project outputs sensor data to the console. It requires a VL53L0X
+sensor, which is present on the disco_l475_iot1 board.
 
- .. zephyr-app-commands::
-    :zephyr-app: samples/sensor/vl53l0x/
-    :goals: build flash
+.. zephyr-app-commands::
+   :zephyr-app: samples/sensor/vl53l0x/
+   :goals: build flash
 
 
 Sample Output
 =============
 
- .. code-block:: console
-
-    prox is 0
-    distance is 1938
-    prox is 1
-    distance is 70
-    prox is 0
-    distance is 1995
-
-    <repeats endlessly every second>
+.. code-block:: console
+
+   prox is 0
+   distance is 1874 mm
+   Max distance is 000 mm
+   Signal rate is 33435 Cps
+   Ambient rate is 17365 Cps
+   SPADs used: 195
+   Status: OK
+
+   prox is 0
+   distance is 1888 mm
+   Max distance is 000 mm
+   Signal rate is 20846 Cps
+   Ambient rate is 25178 Cps
+   SPADs used: 195
+   Status: OK
+
+   <repeats endlessly every 5 seconds>
diff --git a/samples/sensor/vl53l0x/sample.yaml b/samples/sensor/vl53l0x/sample.yaml
index 01c6912550c..ca3dbbb9410 100644
--- a/samples/sensor/vl53l0x/sample.yaml
+++ b/samples/sensor/vl53l0x/sample.yaml
@@ -2,8 +2,16 @@ sample:
   name: Sample for MEMS sensors VL53L0X
 tests:
   sample.sensor.vl53l0x:
-    build_only: true
     depends_on:
       - i2c
       - vl53l0x
-    tags: sensors
+    tags:
+      - sensors
+    integration_platforms:
+      - disco_l475_iot1
+    harness: console
+    harness_config:
+      type: multi_line
+      regex:
+        - "prox is .*"
+        - "distance is .*"
diff --git a/samples/sensor/vl53l0x/src/main.c b/samples/sensor/vl53l0x/src/main.c
index cfed1adaa62..e9b76d410e7 100644
--- a/samples/sensor/vl53l0x/src/main.c
+++ b/samples/sensor/vl53l0x/src/main.c
@@ -7,8 +7,8 @@
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/drivers/sensor.h>
-#include <stdio.h>
 #include <zephyr/sys/printk.h>
+#include <zephyr/drivers/sensor/vl53l0x.h>
 
 int main(void)
 {
@@ -31,12 +31,30 @@ int main(void)
 		ret = sensor_channel_get(dev, SENSOR_CHAN_PROX, &value);
 		printk("prox is %d\n", value.val1);
 
-		ret = sensor_channel_get(dev,
-					 SENSOR_CHAN_DISTANCE,
-					 &value);
-		printf("distance is %.3fm\n", sensor_value_to_double(&value));
+		ret = sensor_channel_get(dev, SENSOR_CHAN_DISTANCE, &value);
+		printk("distance is %.3lld mm\n", sensor_value_to_milli(&value));
 
-		k_sleep(K_MSEC(1000));
+		ret = sensor_channel_get(dev, SENSOR_CHAN_VL53L0X_RANGE_DMAX, &value);
+		printk("Max distance is %.3lld mm\n", sensor_value_to_milli(&value));
+
+		ret = sensor_channel_get(dev, SENSOR_CHAN_VL53L0X_SIGNAL_RATE_RTN_CPS, &value);
+		printk("Signal rate is %d Cps\n", value.val1);
+
+		ret = sensor_channel_get(dev, SENSOR_CHAN_VL53L0X_AMBIENT_RATE_RTN_CPS, &value);
+		printk("Ambient rate is %d Cps\n", value.val1);
+
+		ret = sensor_channel_get(dev, SENSOR_CHAN_VL53L0X_EFFECTIVE_SPAD_RTN_COUNT, &value);
+		printk("SPADs used: %d\n", value.val1);
+
+		ret = sensor_channel_get(dev, SENSOR_CHAN_VL53L0X_RANGE_STATUS, &value);
+		if (value.val1 == VL53L0X_RANGE_STATUS_RANGE_VALID) {
+			printk("Status: OK\n");
+		} else {
+			printk("Status: Error code %d\n", value.val1);
+		}
+
+		printk("\n");
+		k_sleep(K_MSEC(5000));
 	}
 	return 0;
 }
diff --git a/samples/shields/x_nucleo_53l0a1/sample.yaml b/samples/shields/x_nucleo_53l0a1/sample.yaml
index c380e1c964f..81f4896e664 100644
--- a/samples/shields/x_nucleo_53l0a1/sample.yaml
+++ b/samples/shields/x_nucleo_53l0a1/sample.yaml
@@ -6,3 +6,5 @@ tests:
     tags: shield
     depends_on: arduino_i2c
     filter: dt_enabled_alias_with_parent_compat("sw0", "gpio-keys")
+    integration_platforms:
+      - nucleo_g431rb/stm32g431xx
diff --git a/samples/subsys/bindesc/read_bindesc/sample.yaml b/samples/subsys/bindesc/read_bindesc/sample.yaml
index d6fafc34a74..c24a7183468 100644
--- a/samples/subsys/bindesc/read_bindesc/sample.yaml
+++ b/samples/subsys/bindesc/read_bindesc/sample.yaml
@@ -11,3 +11,5 @@ tests:
     tags: bindesc
     filter: dt_chosen_enabled("zephyr,flash-controller") and CONFIG_FLASH_HAS_DRIVER_ENABLED
       and CONFIG_ARCH_SUPPORTS_ROM_START
+    integration_platforms:
+      - mps2/an385
diff --git a/samples/subsys/dap/CMakeLists.txt b/samples/subsys/dap/CMakeLists.txt
index 72ea1953b3c..f0b914c0dab 100644
--- a/samples/subsys/dap/CMakeLists.txt
+++ b/samples/subsys/dap/CMakeLists.txt
@@ -5,5 +5,6 @@ cmake_minimum_required(VERSION 3.20.0)
 find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
 project(dap)
 
+include(${ZEPHYR_BASE}/samples/subsys/usb/common/common.cmake)
 FILE(GLOB app_sources src/*.c)
 target_sources(app PRIVATE ${app_sources})
diff --git a/samples/subsys/dap/Kconfig b/samples/subsys/dap/Kconfig
new file mode 100644
index 00000000000..96c54558948
--- /dev/null
+++ b/samples/subsys/dap/Kconfig
@@ -0,0 +1,9 @@
+# Copyright (c) 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Source common USB sample options used to initialize new experimental USB
+# device stack. The scope of these options is limited to USB samples in project
+# tree, you cannot use them in your own application.
+source "samples/subsys/usb/common/Kconfig.sample_usbd"
+
+source "Kconfig.zephyr"
diff --git a/samples/subsys/dap/README.rst b/samples/subsys/dap/README.rst
index 1f34f02c523..cec0e1681a3 100644
--- a/samples/subsys/dap/README.rst
+++ b/samples/subsys/dap/README.rst
@@ -7,7 +7,7 @@ Overview
 ********
 
 This sample app demonstrates use of a SWDP interface driver and CMSIS DAP
-controller through USB Bulk interface.
+controller through DAP USB backend.
 
 Requirements
 ************
@@ -21,8 +21,6 @@ e.g. if the SWD connections are multiplexed.
 Building and Running
 ********************
 
-In order for our debug adapter to be recognized by pyOCD we need to change
-Zephyr's VID/PID to IDs known to pyOCD, this is up to the user.
 The following commands build and flash DAP sample.
 
 .. zephyr-app-commands::
diff --git a/samples/subsys/dap/prj.conf b/samples/subsys/dap/prj.conf
index 85e26acafa9..062bec17569 100644
--- a/samples/subsys/dap/prj.conf
+++ b/samples/subsys/dap/prj.conf
@@ -1,19 +1,18 @@
+CONFIG_USB_DEVICE_STACK_NEXT=y
+CONFIG_SAMPLE_USBD_PRODUCT="Zephyr CMSIS-DAP"
+CONFIG_SAMPLE_USBD_PID=0x0204
+CONFIG_SAMPLE_USBD_20_EXTENSION_DESC=y
+
 CONFIG_STDOUT_CONSOLE=y
-CONFIG_USB_DEVICE_STACK=y
-CONFIG_USB_DEVICE_BOS=y
 CONFIG_SERIAL=y
-CONFIG_USB_DEVICE_PRODUCT="Zephyr CMSIS-DAP"
-CONFIG_USB_DEVICE_PID=0x0204
 CONFIG_UART_INTERRUPT_DRIVEN=y
 CONFIG_UART_LINE_CTRL=y
-CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n
 
 CONFIG_LOG=y
+CONFIG_LOG_DEFAULT_LEVEL=2
 
-CONFIG_USB_DRIVER_LOG_LEVEL_INF=y
-CONFIG_USB_DEVICE_LOG_LEVEL_INF=y
 CONFIG_DAP_LOG_LEVEL_INF=y
 CONFIG_DP_DRIVER_LOG_LEVEL_INF=y
 CONFIG_DAP=y
+CONFIG_DAP_BACKEND_USB=y
 CONFIG_GPIO=y
-CONFIG_NET_BUF=y
diff --git a/samples/subsys/dap/sample.yaml b/samples/subsys/dap/sample.yaml
index 7730fcade67..bcdcd53658f 100644
--- a/samples/subsys/dap/sample.yaml
+++ b/samples/subsys/dap/sample.yaml
@@ -5,7 +5,7 @@ tests:
     build_only: true
     depends_on:
       - arduino_gpio
-      - usb_device
+      - usbd
     platform_allow:
       - nrf52840dk/nrf52840
       - frdm_k64f
diff --git a/samples/subsys/dap/src/main.c b/samples/subsys/dap/src/main.c
index c8682f2e5c0..55288af1eff 100644
--- a/samples/subsys/dap/src/main.c
+++ b/samples/subsys/dap/src/main.c
@@ -4,367 +4,64 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <sample_usbd.h>
+
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/sys/byteorder.h>
-#include <zephyr/usb/usb_device.h>
+#include <zephyr/usb/usbd.h>
 #include <zephyr/usb/bos.h>
 #include <zephyr/usb/msos_desc.h>
-#include <zephyr/net_buf.h>
 
-#include <usb_descriptor.h>
 #include <cmsis_dap.h>
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(dap_sample, LOG_LEVEL_INF);
 
-NET_BUF_POOL_FIXED_DEFINE(dapusb_rx_pool, CONFIG_CMSIS_DAP_PACKET_COUNT,
-			  CONFIG_CMSIS_DAP_PACKET_SIZE, 0, NULL);
-
-static uint8_t rx_buf[CONFIG_CMSIS_DAP_PACKET_SIZE];
-static uint8_t tx_buf[CONFIG_CMSIS_DAP_PACKET_SIZE];
-
-static K_FIFO_DEFINE(dap_rx_queue);
-
-#define DAP_IFACE_STR_DESC		"CMSIS-DAP v2"
-
-struct dap_iface_descriptor {
-	uint8_t bLength;
-	uint8_t bDescriptorType;
-	uint8_t bString[USB_BSTRING_LENGTH(DAP_IFACE_STR_DESC)];
-} __packed;
-
-USBD_STRING_DESCR_USER_DEFINE(primary) struct dap_iface_descriptor dap_iface_desc = {
-	.bLength = USB_STRING_DESCRIPTOR_LENGTH(DAP_IFACE_STR_DESC),
-	.bDescriptorType = USB_DESC_STRING,
-	.bString = DAP_IFACE_STR_DESC
-};
-
-#define DAP_USB_EP_IN		0x81
-#define DAP_USB_EP_OUT		0x01
-#define DAP_USB_EP_IN_IDX	0
-#define DAP_USB_EP_OUT_IDX	1
-
-#define WEBUSB_VENDOR_CODE	0x21
-#define WINUSB_VENDOR_CODE	0x20
-
-/* {CDB3B5AD-293B-4663-AA36-1AAE46463776} */
-#define CMSIS_DAP_V2_DEVICE_INTERFACE_GUID \
-	'{', 0x00, 'C', 0x00, 'D', 0x00, 'B', 0x00, '3', 0x00, 'B', 0x00, \
-	'5', 0x00, 'A', 0x00, 'D', 0x00, '-', 0x00, '2', 0x00, '9', 0x00, \
-	'3', 0x00, 'B', 0x00, '-', 0x00, '4', 0x00, '6', 0x00, '6', 0x00, \
-	'3', 0x00, '-', 0x00, 'A', 0x00, 'A', 0x00, '3', 0x00, '6', 0x00, \
-	'-', 0x00, '1', 0x00, 'A', 0x00, 'A', 0x00, 'E', 0x00, '4', 0x00, \
-	'6', 0x00, '4', 0x00, '6', 0x00, '3', 0x00, '7', 0x00, '7', 0x00, \
-	'6', 0x00, '}', 0x00, 0x00, 0x00, 0x00, 0x00
-
-#define COMPATIBLE_ID_WINUSB \
-	'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00
-
-static struct msosv2_descriptor {
-	struct msosv2_descriptor_set_header header;
-#if defined(CONFIG_USB_COMPOSITE_DEVICE)
-	struct msosv2_function_subset_header subset_header;
-#endif
-	struct msosv2_compatible_id compatible_id;
-	struct msosv2_guids_property guids_property;
-} __packed msosv2_cmsis_dap_desc = {
-	/*
-	 * Microsoft OS 2.0 descriptor set. This tells Windows what kind
-	 * of device this is and to install the WinUSB driver.
-	 */
-	.header = {
-		.wLength = sizeof(struct msosv2_descriptor_set_header),
-		.wDescriptorType = MS_OS_20_SET_HEADER_DESCRIPTOR,
-		.dwWindowsVersion = 0x06030000,
-		.wTotalLength = sizeof(struct msosv2_descriptor),
-	},
-#if defined(CONFIG_USB_COMPOSITE_DEVICE)
-	.subset_header = {
-		.wLength = sizeof(struct msosv2_function_subset_header),
-		.wDescriptorType = MS_OS_20_SUBSET_HEADER_FUNCTION,
-		.wSubsetLength = sizeof(struct msosv2_function_subset_header)
-			+ sizeof(struct msosv2_compatible_id)
-			+ sizeof(struct msosv2_guids_property),
-	},
-#endif
-	.compatible_id = {
-		.wLength = sizeof(struct msosv2_compatible_id),
-		.wDescriptorType = MS_OS_20_FEATURE_COMPATIBLE_ID,
-		.CompatibleID = {COMPATIBLE_ID_WINUSB},
-	},
-	.guids_property = {
-		.wLength = sizeof(struct msosv2_guids_property),
-		.wDescriptorType = MS_OS_20_FEATURE_REG_PROPERTY,
-		.wPropertyDataType = MS_OS_20_PROPERTY_DATA_REG_MULTI_SZ,
-		.wPropertyNameLength = 42,
-		.PropertyName = {DEVICE_INTERFACE_GUIDS_PROPERTY_NAME},
-		.wPropertyDataLength = 80,
-		.bPropertyData = {CMSIS_DAP_V2_DEVICE_INTERFACE_GUID},
-	},
-};
-
-USB_DEVICE_BOS_DESC_DEFINE_CAP struct usb_bos_msosv2_desc {
-	struct usb_bos_platform_descriptor platform;
-	struct usb_bos_capability_msos cap;
-} __packed bos_cap_msosv2 = {
-	/* Microsoft OS 2.0 Platform Capability Descriptor */
-	.platform = {
-		.bLength = sizeof(struct usb_bos_platform_descriptor)
-			+ sizeof(struct usb_bos_capability_msos),
-		.bDescriptorType = USB_DESC_DEVICE_CAPABILITY,
-		.bDevCapabilityType = USB_BOS_CAPABILITY_PLATFORM,
-		.bReserved = 0,
-		.PlatformCapabilityUUID = {
-			/**
-			 * MS OS 2.0 Platform Capability ID
-			 * D8DD60DF-4589-4CC7-9CD2-659D9E648A9F
-			 */
-			0xDF, 0x60, 0xDD, 0xD8,
-			0x89, 0x45,
-			0xC7, 0x4C,
-			0x9C, 0xD2,
-			0x65, 0x9D, 0x9E, 0x64, 0x8A, 0x9F,
-		},
-	},
-	.cap = {
-		/* Windows version (8.1) (0x06030000) */
-		.dwWindowsVersion = sys_cpu_to_le32(0x06030000),
-		.wMSOSDescriptorSetTotalLength =
-			sys_cpu_to_le16(sizeof(msosv2_cmsis_dap_desc)),
-		.bMS_VendorCode = WINUSB_VENDOR_CODE,
-		.bAltEnumCode = 0x00
-	},
-};
-
-USB_DEVICE_BOS_DESC_DEFINE_CAP struct usb_bos_webusb_desc {
-	struct usb_bos_platform_descriptor platform;
-	struct usb_bos_capability_webusb cap;
-} __packed bos_cap_webusb = {
-	/* WebUSB Platform Capability Descriptor:
-	 * https://wicg.github.io/webusb/#webusb-platform-capability-descriptor
-	 */
-	.platform = {
-		.bLength = sizeof(struct usb_bos_platform_descriptor)
-			 + sizeof(struct usb_bos_capability_webusb),
-		.bDescriptorType = USB_DESC_DEVICE_CAPABILITY,
-		.bDevCapabilityType = USB_BOS_CAPABILITY_PLATFORM,
-		.bReserved = 0,
-		/* WebUSB Platform Capability UUID
-		 * 3408b638-09a9-47a0-8bfd-a0768815b665
-		 */
-		.PlatformCapabilityUUID = {
-			0x38, 0xB6, 0x08, 0x34,
-			0xA9, 0x09,
-			0xA0, 0x47,
-			0x8B, 0xFD,
-			0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65,
-		},
-	},
-	.cap = {
-		.bcdVersion = sys_cpu_to_le16(0x0100),
-		.bVendorCode = WEBUSB_VENDOR_CODE,
-		.iLandingPage = 0x01
-	}
-};
-
-/* URL Descriptor: https://wicg.github.io/webusb/#url-descriptor */
-static const uint8_t webusb_origin_url[] = {
-	/* Length, DescriptorType, Scheme */
-	24, 0x03, 0x01,
-	'w', 'w', 'w', '.',
-	'z', 'e', 'p', 'h', 'y', 'r', 'p', 'r', 'o', 'j', 'e', 'c', 't', '.',
-	'o', 'r', 'g', '/',
-};
-
-static int msosv2_vendor_handle_req(struct usb_setup_packet *setup,
-				    int32_t *len, uint8_t **data)
-{
-	if (usb_reqtype_is_to_device(setup)) {
-		return -ENOTSUP;
-	}
-
-	if (setup->bRequest == WEBUSB_VENDOR_CODE && setup->wIndex == 0x02) {
-		*data = (uint8_t *)(&webusb_origin_url);
-		*len = sizeof(webusb_origin_url);
-
-		LOG_DBG("Get URL request");
-
-		return 0;
-	}
-
-	if (setup->bRequest == WINUSB_VENDOR_CODE &&
-	    setup->wIndex == MS_OS_20_DESCRIPTOR_INDEX) {
-		*data = (uint8_t *)(&msosv2_cmsis_dap_desc);
-		*len = sizeof(msosv2_cmsis_dap_desc);
-
-		LOG_DBG("Get MS OS Descriptors v2");
-
-		return 0;
-	}
-
-	return -ENOTSUP;
-}
-
-USBD_CLASS_DESCR_DEFINE(primary, 0) struct {
-	struct usb_if_descriptor if0;
-	struct usb_ep_descriptor if0_out_ep;
-	struct usb_ep_descriptor if0_in_ep;
-} __packed dapusb_desc = {
-	.if0 = {
-		.bLength = sizeof(struct usb_if_descriptor),
-		.bDescriptorType = USB_DESC_INTERFACE,
-		.bInterfaceNumber = 0,
-		.bAlternateSetting = 0,
-		.bNumEndpoints = 2,
-		.bInterfaceClass = USB_BCC_VENDOR,
-		.bInterfaceSubClass = 0,
-		.bInterfaceProtocol = 0,
-		.iInterface = 0,
-	},
-	.if0_out_ep = {
-		.bLength = sizeof(struct usb_ep_descriptor),
-		.bDescriptorType = USB_DESC_ENDPOINT,
-		.bEndpointAddress = DAP_USB_EP_OUT,
-		.bmAttributes = USB_DC_EP_BULK,
-		.wMaxPacketSize = sys_cpu_to_le16(CONFIG_CMSIS_DAP_PACKET_SIZE),
-		.bInterval = 0,
-	},
-	.if0_in_ep = {
-		.bLength = sizeof(struct usb_ep_descriptor),
-		.bDescriptorType = USB_DESC_ENDPOINT,
-		.bEndpointAddress = DAP_USB_EP_IN,
-		.bmAttributes = USB_DC_EP_BULK,
-		.wMaxPacketSize = sys_cpu_to_le16(CONFIG_CMSIS_DAP_PACKET_SIZE),
-		.bInterval = 0,
-	},
-};
-
-static struct usb_ep_cfg_data dapusb_ep_data[] = {
-	{
-		.ep_cb	= usb_transfer_ep_callback,
-		.ep_addr = DAP_USB_EP_OUT
-	},
-	{
-		.ep_cb = usb_transfer_ep_callback,
-		.ep_addr = DAP_USB_EP_IN
-	}
-};
-
-static void iface_string_desc_init(struct usb_cfg_data *bulk_cfg)
-{
-	struct usb_if_descriptor *bulk_if = bulk_cfg->interface_descriptor;
-
-	bulk_if->iInterface = usb_get_str_descriptor_idx(&dap_iface_desc);
-}
-
-static void dapusb_read_cb(uint8_t ep, int size, void *priv)
-{
-	struct usb_cfg_data *cfg = priv;
-	struct net_buf *buf;
-
-	LOG_DBG("cfg %p ep %x size %u", cfg, ep, size);
-
-	if (size <= 0) {
-		goto read_cb_done;
-	}
-
-	buf = net_buf_alloc(&dapusb_rx_pool, K_FOREVER);
-	net_buf_add_mem(buf, rx_buf, MIN(size, CONFIG_CMSIS_DAP_PACKET_SIZE));
-	k_fifo_put(&dap_rx_queue, buf);
-
-read_cb_done:
-	usb_transfer(ep, rx_buf, sizeof(rx_buf), USB_TRANS_READ, dapusb_read_cb, cfg);
-}
-
-static void dapusb_dev_status_cb(struct usb_cfg_data *cfg,
-				 enum usb_dc_status_code status,
-				 const uint8_t *param)
-{
-	ARG_UNUSED(param);
-
-	if (status == USB_DC_CONFIGURED) {
-		dapusb_read_cb(cfg->endpoint[DAP_USB_EP_IN_IDX].ep_addr, 0, cfg);
-	}
-}
-
-static void dapusb_interface_config(struct usb_desc_header *head,
-				    uint8_t bInterfaceNumber)
-{
-	ARG_UNUSED(head);
-
-	dapusb_desc.if0.bInterfaceNumber = bInterfaceNumber;
-#if defined(CONFIG_USB_COMPOSITE_DEVICE)
-	msosv2_cmsis_dap_desc.subset_header.bFirstInterface = bInterfaceNumber;
-#endif
-}
-
-USBD_DEFINE_CFG_DATA(dapusb_config) = {
-	.usb_device_description = NULL,
-	.interface_config = dapusb_interface_config,
-	.interface_descriptor = &dapusb_desc.if0,
-	.cb_usb_status = dapusb_dev_status_cb,
-	.interface = {
-		.class_handler = NULL,
-		.custom_handler = NULL,
-		.vendor_handler = msosv2_vendor_handle_req,
-	},
-	.num_endpoints = ARRAY_SIZE(dapusb_ep_data),
-	.endpoint = dapusb_ep_data
-};
-
-static int dap_usb_process(void)
-{
-	uint8_t ep = dapusb_config.endpoint[DAP_USB_EP_OUT_IDX].ep_addr;
-	struct net_buf *buf;
-	size_t len;
-	int err;
-
-	buf = k_fifo_get(&dap_rx_queue, K_FOREVER);
-
-	len = dap_execute_cmd(buf->data, tx_buf);
-	LOG_DBG("response length %u, starting with [0x%02X, 0x%02X]",
-		len, tx_buf[0], tx_buf[1]);
-	net_buf_unref(buf);
-
-	err = usb_transfer_sync(ep, tx_buf, len, USB_TRANS_WRITE | USB_TRANS_NO_ZLP);
-	if (err < 0 || err != len) {
-		LOG_ERR("usb_transfer_sync failed, %d", err);
-		return -EIO;
-	}
-
-	return 0;
-}
+#include "webusb.h"
+#include "msosv2.h"
 
 int main(void)
 {
 	const struct device *const swd_dev = DEVICE_DT_GET_ONE(zephyr_swdp_gpio);
+	struct usbd_context *sample_usbd;
 	int ret;
 
-	if (!device_is_ready(swd_dev)) {
-		LOG_ERR("SWD device is not ready");
+	ret = dap_setup(swd_dev);
+	if (ret) {
+		LOG_ERR("Failed to initialize DAP controller, %d", ret);
+		return ret;
+	}
+
+	sample_usbd = sample_usbd_setup_device(NULL);
+	if (sample_usbd == NULL) {
+		LOG_ERR("Failed to setup USB device");
 		return -ENODEV;
 	}
 
-	ret = dap_setup(swd_dev);
+	ret = usbd_add_descriptor(sample_usbd, &bos_vreq_msosv2);
 	if (ret) {
-		LOG_ERR("Failed to initialize DAP controller, %d", ret);
+		LOG_ERR("Failed to add MSOSv2 capability descriptor");
 		return ret;
 	}
 
-	/* Add MS OS 2.0 BOS descriptor to BOS structure */
-	usb_bos_register_cap((void *)&bos_cap_msosv2);
-	/* Point interface index to string descriptor */
-	iface_string_desc_init(&dapusb_config);
+	ret = usbd_add_descriptor(sample_usbd, &bos_vreq_webusb);
+	if (ret) {
+		LOG_ERR("Failed to add WebUSB capability descriptor");
+		return ret;
+	}
 
-	ret = usb_enable(NULL);
-	if (ret != 0) {
-		LOG_ERR("Failed to enable USB");
-		return 0;
+	ret = usbd_init(sample_usbd);
+	if (ret) {
+		LOG_ERR("Failed to initialize device support");
+		return ret;
 	}
 
-	while (!dap_usb_process()) {
+	ret = usbd_enable(sample_usbd);
+	if (ret) {
+		LOG_ERR("Failed to enable device support");
+		return ret;
 	}
 
-	return usb_disable();
+	return 0;
 }
diff --git a/samples/subsys/dap/src/msosv2.h b/samples/subsys/dap/src/msosv2.h
new file mode 100644
index 00000000000..c00d614c350
--- /dev/null
+++ b/samples/subsys/dap/src/msosv2.h
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2016-2019 Intel Corporation
+ * Copyright (c) 2023-2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_MSOSV2_DESCRIPTOR_H
+#define ZEPHYR_INCLUDE_MSOSV2_DESCRIPTOR_H
+
+/*
+ * Microsoft OS 2.0 platform capability and Microsoft OS 2.0 descriptor set.
+ * See Microsoft OS 2.0 Descriptors Specification for reference.
+ */
+
+#define SAMPLE_MSOS2_VENDOR_CODE	0x02U
+/* Windows version (10)*/
+#define SAMPLE_MSOS2_OS_VERSION		0x0A000000UL
+
+/* {CDB3B5AD-293B-4663-AA36-1AAE46463776} */
+#define CMSIS_DAP_V2_DEVICE_INTERFACE_GUID \
+	'{', 0x00, 'C', 0x00, 'D', 0x00, 'B', 0x00, '3', 0x00, 'B', 0x00, \
+	'5', 0x00, 'A', 0x00, 'D', 0x00, '-', 0x00, '2', 0x00, '9', 0x00, \
+	'3', 0x00, 'B', 0x00, '-', 0x00, '4', 0x00, '6', 0x00, '6', 0x00, \
+	'3', 0x00, '-', 0x00, 'A', 0x00, 'A', 0x00, '3', 0x00, '6', 0x00, \
+	'-', 0x00, '1', 0x00, 'A', 0x00, 'A', 0x00, 'E', 0x00, '4', 0x00, \
+	'6', 0x00, '4', 0x00, '6', 0x00, '3', 0x00, '7', 0x00, '7', 0x00, \
+	'6', 0x00, '}', 0x00, 0x00, 0x00, 0x00, 0x00
+
+#define CDC_ACM_DESCRIPTOR_LENGTH 160
+
+struct msosv2_descriptor {
+	struct msosv2_descriptor_set_header header;
+#if defined(CONFIG_USBD_CDC_ACM_CLASS)
+	/*
+	 * The composition of this descriptor is specific to the WebUSB example
+	 * in its default configuration. If you use it for your application or
+	 * change the configuration, you may need to modify this descriptor for
+	 * your USB device. The following only covers the case where the CDC
+	 * ACM implementation is enabled, and there is only one CDC ACM UART
+	 * instance, and the CDC ACM communication interface is the first in
+	 * the configuration.
+	 */
+	struct msosv2_function_subset_header subset_header;
+#endif
+	struct msosv2_compatible_id compatible_id;
+	struct msosv2_guids_property guids_property;
+} __packed;
+
+static struct msosv2_descriptor msosv2_desc = {
+	.header = {
+		.wLength = sizeof(struct msosv2_descriptor_set_header),
+		.wDescriptorType = MS_OS_20_SET_HEADER_DESCRIPTOR,
+		.dwWindowsVersion = sys_cpu_to_le32(SAMPLE_MSOS2_OS_VERSION),
+		.wTotalLength = sizeof(msosv2_desc),
+	},
+#if defined(CONFIG_USBD_CDC_ACM_CLASS)
+	.subset_header = {
+		.wLength = sizeof(struct msosv2_function_subset_header),
+		.wDescriptorType = MS_OS_20_SUBSET_HEADER_FUNCTION,
+		.bFirstInterface = 0,
+		.wSubsetLength = CDC_ACM_DESCRIPTOR_LENGTH,
+	},
+#endif
+	.compatible_id = {
+		.wLength = sizeof(struct msosv2_compatible_id),
+		.wDescriptorType = MS_OS_20_FEATURE_COMPATIBLE_ID,
+		.CompatibleID = {'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00},
+	},
+	.guids_property = {
+		.wLength = sizeof(struct msosv2_guids_property),
+		.wDescriptorType = MS_OS_20_FEATURE_REG_PROPERTY,
+		.wPropertyDataType = MS_OS_20_PROPERTY_DATA_REG_MULTI_SZ,
+		.wPropertyNameLength = 42,
+		.PropertyName = {DEVICE_INTERFACE_GUIDS_PROPERTY_NAME},
+		.wPropertyDataLength = 80,
+		.bPropertyData = {CMSIS_DAP_V2_DEVICE_INTERFACE_GUID},
+	},
+};
+
+struct bos_msosv2_descriptor {
+	struct usb_bos_platform_descriptor platform;
+	struct usb_bos_capability_msos cap;
+} __packed;
+
+struct bos_msosv2_descriptor bos_msosv2_desc = {
+	/*
+	 * Microsoft OS 2.0 Platform Capability Descriptor,
+	 * see Microsoft OS 2.0 Descriptors Specification
+	 */
+	.platform = {
+		.bLength = sizeof(struct usb_bos_platform_descriptor)
+			 + sizeof(struct usb_bos_capability_msos),
+		.bDescriptorType = USB_DESC_DEVICE_CAPABILITY,
+		.bDevCapabilityType = USB_BOS_CAPABILITY_PLATFORM,
+		.bReserved = 0,
+		/* Microsoft OS 2.0 descriptor platform capability UUID
+		 * D8DD60DF-4589-4CC7-9CD2-659D9E648A9F
+		 */
+		.PlatformCapabilityUUID = {
+			0xDF, 0x60, 0xDD, 0xD8,
+			0x89, 0x45,
+			0xC7, 0x4C,
+			0x9C, 0xD2,
+			0x65, 0x9D, 0x9E, 0x64, 0x8A, 0x9F,
+		},
+	},
+	.cap = {
+		.dwWindowsVersion = sys_cpu_to_le32(SAMPLE_MSOS2_OS_VERSION),
+		.wMSOSDescriptorSetTotalLength = sys_cpu_to_le16(sizeof(msosv2_desc)),
+		.bMS_VendorCode = SAMPLE_MSOS2_VENDOR_CODE,
+		.bAltEnumCode = 0x00
+	},
+};
+
+static int msosv2_to_host_cb(const struct usbd_context *const ctx,
+			     const struct usb_setup_packet *const setup,
+			     struct net_buf *const buf)
+{
+	LOG_INF("Vendor callback to host");
+
+	if (setup->bRequest == SAMPLE_MSOS2_VENDOR_CODE &&
+	    setup->wIndex == MS_OS_20_DESCRIPTOR_INDEX) {
+		LOG_INF("Get MS OS 2.0 Descriptor Set");
+
+		net_buf_add_mem(buf, &msosv2_desc,
+				MIN(net_buf_tailroom(buf), sizeof(msosv2_desc)));
+
+		return 0;
+	}
+
+	return -ENOTSUP;
+}
+
+USBD_DESC_BOS_VREQ_DEFINE(bos_vreq_msosv2, sizeof(bos_msosv2_desc), &bos_msosv2_desc,
+			  SAMPLE_MSOS2_VENDOR_CODE, msosv2_to_host_cb, NULL);
+
+#endif /* ZEPHYR_INCLUDE_MSOSV2_DESCRIPTOR_H */
diff --git a/samples/subsys/dap/src/webusb.h b/samples/subsys/dap/src/webusb.h
new file mode 100644
index 00000000000..c1cda8924ec
--- /dev/null
+++ b/samples/subsys/dap/src/webusb.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2016-2019 Intel Corporation
+ * Copyright (c) 2023-2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_WEBUSB_DESCRIPTOR_H
+#define ZEPHYR_INCLUDE_WEBUSB_DESCRIPTOR_H
+
+/*
+ * WebUSB platform capability and WebUSB URL descriptor.
+ * See https://wicg.github.io/webusb for reference.
+ */
+
+#define WEBUSB_REQ_GET_URL		0x02U
+#define WEBUSB_DESC_TYPE_URL		0x03U
+#define WEBUSB_URL_PREFIX_HTTP		0x00U
+#define WEBUSB_URL_PREFIX_HTTPS		0x01U
+
+#define SAMPLE_WEBUSB_VENDOR_CODE	0x01U
+#define SAMPLE_WEBUSB_LANDING_PAGE	0x01U
+
+struct usb_bos_webusb_desc {
+	struct usb_bos_platform_descriptor platform;
+	struct usb_bos_capability_webusb cap;
+} __packed;
+
+static const struct usb_bos_webusb_desc bos_cap_webusb = {
+	/* WebUSB Platform Capability Descriptor:
+	 * https://wicg.github.io/webusb/#webusb-platform-capability-descriptor
+	 */
+	.platform = {
+		.bLength = sizeof(struct usb_bos_platform_descriptor)
+			 + sizeof(struct usb_bos_capability_webusb),
+		.bDescriptorType = USB_DESC_DEVICE_CAPABILITY,
+		.bDevCapabilityType = USB_BOS_CAPABILITY_PLATFORM,
+		.bReserved = 0,
+		/* WebUSB Platform Capability UUID
+		 * 3408b638-09a9-47a0-8bfd-a0768815b665
+		 */
+		.PlatformCapabilityUUID = {
+			0x38, 0xB6, 0x08, 0x34,
+			0xA9, 0x09,
+			0xA0, 0x47,
+			0x8B, 0xFD,
+			0xA0, 0x76, 0x88, 0x15, 0xB6, 0x65,
+		},
+	},
+	.cap = {
+		.bcdVersion = sys_cpu_to_le16(0x0100),
+		.bVendorCode = SAMPLE_WEBUSB_VENDOR_CODE,
+		.iLandingPage = SAMPLE_WEBUSB_LANDING_PAGE
+	}
+};
+
+/* WebUSB URL Descriptor, see https://wicg.github.io/webusb/#webusb-descriptors */
+static const uint8_t webusb_origin_url[] = {
+	/* bLength, bDescriptorType, bScheme, UTF-8 encoded URL */
+	0x24, WEBUSB_DESC_TYPE_URL, WEBUSB_URL_PREFIX_HTTPS,
+	'w', 'w', 'w', '.',
+	'z', 'e', 'p', 'h', 'y', 'r', 'p', 'r', 'o', 'j', 'e', 'c', 't', '.',
+	'o', 'r', 'g', '/',
+};
+
+static int webusb_to_host_cb(const struct usbd_context *const ctx,
+			     const struct usb_setup_packet *const setup,
+			     struct net_buf *const buf)
+{
+	LOG_INF("Vendor callback to host");
+
+	if (setup->wIndex == WEBUSB_REQ_GET_URL) {
+		uint8_t index = USB_GET_DESCRIPTOR_INDEX(setup->wValue);
+
+		if (index != SAMPLE_WEBUSB_LANDING_PAGE) {
+			return -ENOTSUP;
+		}
+
+		LOG_INF("Get URL request, index %u", index);
+		net_buf_add_mem(buf, &webusb_origin_url,
+				MIN(net_buf_tailroom(buf), sizeof(webusb_origin_url)));
+
+		return 0;
+	}
+
+	return -ENOTSUP;
+}
+
+USBD_DESC_BOS_VREQ_DEFINE(bos_vreq_webusb, sizeof(bos_cap_webusb), &bos_cap_webusb,
+			  SAMPLE_WEBUSB_VENDOR_CODE, webusb_to_host_cb, NULL);
+
+#endif /* ZEPHYR_INCLUDE_WEBUSB_DESCRIPTOR_H */
diff --git a/samples/subsys/debug/fuzz/sample.yaml b/samples/subsys/debug/fuzz/sample.yaml
index 3b1dc0b92ec..917986aeaf5 100644
--- a/samples/subsys/debug/fuzz/sample.yaml
+++ b/samples/subsys/debug/fuzz/sample.yaml
@@ -1,10 +1,10 @@
 sample:
-  description: native_posix-based libfuzzer example
+  description: native_sim-based libfuzzer example
   name: fuzz
 tests:
   sample.debug.fuzz:
     toolchain_allow: llvm
-    platform_allow: native_posix/native/64
+    platform_allow: native_sim/native/64
     harness: console
     harness_config:
       type: one_line
diff --git a/samples/subsys/debug/fuzz/src/main.c b/samples/subsys/debug/fuzz/src/main.c
index 95de5986282..bac005be7d1 100644
--- a/samples/subsys/debug/fuzz/src/main.c
+++ b/samples/subsys/debug/fuzz/src/main.c
@@ -9,12 +9,6 @@
 #if defined(CONFIG_BOARD_NATIVE_SIM)
 #include <nsi_cpu_if.h>
 #include <nsi_main_semipublic.h>
-#elif defined(CONFIG_BOARD_NATIVE_POSIX)
-/* Note: native_posix will be deprecated soon */
-extern void posix_init(int argc, char *argv[]);
-extern void posix_exec_for(uint64_t us);
-#define nsi_init posix_init
-#define nsi_exec_for posix_exec_for
 #else
 #error "Platform not supported"
 #endif
diff --git a/samples/subsys/display/cfb/src/main.c b/samples/subsys/display/cfb/src/main.c
index 45369d7ffab..079dd0a355f 100644
--- a/samples/subsys/display/cfb/src/main.c
+++ b/samples/subsys/display/cfb/src/main.c
@@ -44,7 +44,7 @@ int main(void)
 	display_blanking_off(dev);
 
 	x_res = cfb_get_display_parameter(dev, CFB_DISPLAY_WIDTH);
-	y_res = cfb_get_display_parameter(dev, CFB_DISPLAY_HEIGH);
+	y_res = cfb_get_display_parameter(dev, CFB_DISPLAY_HEIGHT);
 	rows = cfb_get_display_parameter(dev, CFB_DISPLAY_ROWS);
 	ppt = cfb_get_display_parameter(dev, CFB_DISPLAY_PPT);
 
diff --git a/samples/subsys/display/lvgl/README.rst b/samples/subsys/display/lvgl/README.rst
index 0bfeff7c763..080c5f33a33 100644
--- a/samples/subsys/display/lvgl/README.rst
+++ b/samples/subsys/display/lvgl/README.rst
@@ -38,14 +38,15 @@ Requirements
 Display shield and a board which provides a configuration
 for corresponding connectors, for example:
 
-- :ref:`adafruit_2_8_tft_touch_v2` and :ref:`nrf52840dk_nrf52840`
-- :ref:`buydisplay_2_8_tft_touch_arduino` and :ref:`nrf52840dk_nrf52840`
+- :ref:`adafruit_2_8_tft_touch_v2` and :zephyr:board:`nrf52840dk`
+- :ref:`buydisplay_2_8_tft_touch_arduino` and :zephyr:board:`nrf52840dk`
 - :ref:`ssd1306_128_shield` and :zephyr:board:`frdm_k64f`
 - :ref:`seeed_xiao_round_display` and :zephyr:board:`xiao_ble`
 
 or a board with an integrated display:
 
 - :zephyr:board:`esp_wrover_kit`
+- :zephyr:board:`adafruit_feather_esp32s3_tft`
 
 or a simulated display environment in a :ref:`native_sim <native_sim>` application:
 
@@ -65,7 +66,7 @@ or
 Building and Running
 ********************
 
-Example building for :ref:`nrf52840dk_nrf52840`:
+Example building for :zephyr:board:`nrf52840dk`:
 
 .. zephyr-app-commands::
    :zephyr-app: samples/subsys/display/lvgl
diff --git a/samples/subsys/display/lvgl/boards/adafruit_feather_esp32s2_tft.conf b/samples/subsys/display/lvgl/boards/adafruit_feather_esp32s2_tft.conf
new file mode 100644
index 00000000000..cf023663fe5
--- /dev/null
+++ b/samples/subsys/display/lvgl/boards/adafruit_feather_esp32s2_tft.conf
@@ -0,0 +1,6 @@
+CONFIG_POWER_DOMAIN=y
+CONFIG_GPIO=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_DEVICE_POWER_DOMAIN=y
+
+CONFIG_MAIN_STACK_SIZE=4096
diff --git a/samples/subsys/display/lvgl/boards/adafruit_feather_esp32s2_tft.overlay b/samples/subsys/display/lvgl/boards/adafruit_feather_esp32s2_tft.overlay
new file mode 100644
index 00000000000..bf62c27670a
--- /dev/null
+++ b/samples/subsys/display/lvgl/boards/adafruit_feather_esp32s2_tft.overlay
@@ -0,0 +1,3 @@
+&st7789v_tft {
+	status = "okay";
+};
diff --git a/samples/subsys/display/lvgl/boards/adafruit_feather_esp32s2_tft_reverse.conf b/samples/subsys/display/lvgl/boards/adafruit_feather_esp32s2_tft_reverse.conf
new file mode 100644
index 00000000000..cf023663fe5
--- /dev/null
+++ b/samples/subsys/display/lvgl/boards/adafruit_feather_esp32s2_tft_reverse.conf
@@ -0,0 +1,6 @@
+CONFIG_POWER_DOMAIN=y
+CONFIG_GPIO=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_DEVICE_POWER_DOMAIN=y
+
+CONFIG_MAIN_STACK_SIZE=4096
diff --git a/samples/subsys/display/lvgl/boards/adafruit_feather_esp32s2_tft_reverse.overlay b/samples/subsys/display/lvgl/boards/adafruit_feather_esp32s2_tft_reverse.overlay
new file mode 100644
index 00000000000..bf62c27670a
--- /dev/null
+++ b/samples/subsys/display/lvgl/boards/adafruit_feather_esp32s2_tft_reverse.overlay
@@ -0,0 +1,3 @@
+&st7789v_tft {
+	status = "okay";
+};
diff --git a/samples/subsys/display/lvgl/boards/adafruit_feather_esp32s3_tft_procpu.conf b/samples/subsys/display/lvgl/boards/adafruit_feather_esp32s3_tft_procpu.conf
new file mode 100644
index 00000000000..cf023663fe5
--- /dev/null
+++ b/samples/subsys/display/lvgl/boards/adafruit_feather_esp32s3_tft_procpu.conf
@@ -0,0 +1,6 @@
+CONFIG_POWER_DOMAIN=y
+CONFIG_GPIO=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_DEVICE_POWER_DOMAIN=y
+
+CONFIG_MAIN_STACK_SIZE=4096
diff --git a/samples/subsys/display/lvgl/boards/adafruit_feather_esp32s3_tft_procpu.overlay b/samples/subsys/display/lvgl/boards/adafruit_feather_esp32s3_tft_procpu.overlay
new file mode 100644
index 00000000000..bf62c27670a
--- /dev/null
+++ b/samples/subsys/display/lvgl/boards/adafruit_feather_esp32s3_tft_procpu.overlay
@@ -0,0 +1,3 @@
+&st7789v_tft {
+	status = "okay";
+};
diff --git a/samples/subsys/display/lvgl/boards/native_posix.conf b/samples/subsys/display/lvgl/boards/native_posix.conf
deleted file mode 100644
index e5f19abc888..00000000000
--- a/samples/subsys/display/lvgl/boards/native_posix.conf
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_LV_COLOR_DEPTH_32=y
-CONFIG_GPIO=y
-CONFIG_INPUT=y
diff --git a/samples/subsys/display/lvgl/boards/native_posix.overlay b/samples/subsys/display/lvgl/boards/native_posix.overlay
deleted file mode 100644
index 29c03cc0928..00000000000
--- a/samples/subsys/display/lvgl/boards/native_posix.overlay
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * Copyright (c) 2022, Basalte bv
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/dt-bindings/input/input-event-codes.h>
-#include <zephyr/dt-bindings/lvgl/lvgl.h>
-
-/ {
-	aliases {
-		sw0 = &button0;
-	};
-
-	qdec {
-		compatible = "gpio-qdec";
-		gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>, <&gpio0 5 GPIO_ACTIVE_HIGH>;
-		steps-per-period = <4>;
-		zephyr,axis = <INPUT_REL_WHEEL>;
-		sample-time-us = <2000>;
-		idle-timeout-ms = <200>;
-	};
-
-	keys: keys {
-		compatible = "gpio-keys";
-		button0: button0 {
-			/* gpio0 pin 0 is already aliased to led0 */
-			gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
-			zephyr,code = <INPUT_KEY_R>;
-		};
-
-		button1: button1 {
-			gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
-			zephyr,code = <INPUT_KEY_B>;
-		};
-
-		encoder_button: encoder_button {
-			gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
-			zephyr,code = <INPUT_KEY_0>;
-		};
-
-		button_left: button_left {
-			gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
-			zephyr,code = <INPUT_KEY_LEFT>;
-		};
-
-		button_right: button_right {
-			gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
-			zephyr,code = <INPUT_KEY_RIGHT>;
-		};
-
-		button_enter: button_enter {
-			gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
-			zephyr,code = <INPUT_KEY_ENTER>;
-		};
-	};
-
-	lvgl_button_input {
-		compatible = "zephyr,lvgl-button-input";
-		input = <&keys>;
-		input-codes = <INPUT_KEY_B>;
-		coordinates = <160 120>;
-	};
-
-	lvgl_encoder_input {
-		compatible = "zephyr,lvgl-encoder-input";
-		rotation-input-code = <INPUT_REL_WHEEL>;
-		button-input-code = <INPUT_KEY_0>;
-	};
-
-	lvgl_keypad_input {
-		compatible = "zephyr,lvgl-keypad-input";
-		input = <&keys>;
-		input-codes = <INPUT_KEY_LEFT INPUT_KEY_RIGHT INPUT_KEY_ENTER>;
-		lvgl-codes = <LV_KEY_LEFT LV_KEY_RIGHT LV_KEY_ENTER>;
-	};
-};
-
-&gpio0 {
-	ngpios = <9>;
-
-	sdl_gpio {
-		status = "okay";
-		compatible = "zephyr,gpio-emul-sdl";
-		/* Skip pin 0 with the unknown code 0 */
-		scancodes = <0 21 5 30 31 32 80 79 40>;
-	};
-};
diff --git a/samples/subsys/display/lvgl/boards/native_sim.overlay b/samples/subsys/display/lvgl/boards/native_sim.overlay
index a77c43378bd..29c03cc0928 100644
--- a/samples/subsys/display/lvgl/boards/native_sim.overlay
+++ b/samples/subsys/display/lvgl/boards/native_sim.overlay
@@ -1,6 +1,88 @@
 /*
- * Copyright (c) 2023, Nordic Semiconductor ASA
+ * Copyright (c) 2022, Basalte bv
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#include "native_posix.overlay"
+
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+#include <zephyr/dt-bindings/lvgl/lvgl.h>
+
+/ {
+	aliases {
+		sw0 = &button0;
+	};
+
+	qdec {
+		compatible = "gpio-qdec";
+		gpios = <&gpio0 4 GPIO_ACTIVE_HIGH>, <&gpio0 5 GPIO_ACTIVE_HIGH>;
+		steps-per-period = <4>;
+		zephyr,axis = <INPUT_REL_WHEEL>;
+		sample-time-us = <2000>;
+		idle-timeout-ms = <200>;
+	};
+
+	keys: keys {
+		compatible = "gpio-keys";
+		button0: button0 {
+			/* gpio0 pin 0 is already aliased to led0 */
+			gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
+			zephyr,code = <INPUT_KEY_R>;
+		};
+
+		button1: button1 {
+			gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
+			zephyr,code = <INPUT_KEY_B>;
+		};
+
+		encoder_button: encoder_button {
+			gpios = <&gpio0 3 GPIO_ACTIVE_HIGH>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		button_left: button_left {
+			gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
+			zephyr,code = <INPUT_KEY_LEFT>;
+		};
+
+		button_right: button_right {
+			gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+			zephyr,code = <INPUT_KEY_RIGHT>;
+		};
+
+		button_enter: button_enter {
+			gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
+			zephyr,code = <INPUT_KEY_ENTER>;
+		};
+	};
+
+	lvgl_button_input {
+		compatible = "zephyr,lvgl-button-input";
+		input = <&keys>;
+		input-codes = <INPUT_KEY_B>;
+		coordinates = <160 120>;
+	};
+
+	lvgl_encoder_input {
+		compatible = "zephyr,lvgl-encoder-input";
+		rotation-input-code = <INPUT_REL_WHEEL>;
+		button-input-code = <INPUT_KEY_0>;
+	};
+
+	lvgl_keypad_input {
+		compatible = "zephyr,lvgl-keypad-input";
+		input = <&keys>;
+		input-codes = <INPUT_KEY_LEFT INPUT_KEY_RIGHT INPUT_KEY_ENTER>;
+		lvgl-codes = <LV_KEY_LEFT LV_KEY_RIGHT LV_KEY_ENTER>;
+	};
+};
+
+&gpio0 {
+	ngpios = <9>;
+
+	sdl_gpio {
+		status = "okay";
+		compatible = "zephyr,gpio-emul-sdl";
+		/* Skip pin 0 with the unknown code 0 */
+		scancodes = <0 21 5 30 31 32 80 79 40>;
+	};
+};
diff --git a/samples/subsys/display/lvgl/prj.conf b/samples/subsys/display/lvgl/prj.conf
index b3d6db3822b..2d7f2f196f2 100644
--- a/samples/subsys/display/lvgl/prj.conf
+++ b/samples/subsys/display/lvgl/prj.conf
@@ -1,6 +1,6 @@
 CONFIG_LV_Z_MEM_POOL_SIZE=16384
 CONFIG_LV_Z_SHELL=y
-CONFIG_MAIN_STACK_SIZE=2048
+CONFIG_MAIN_STACK_SIZE=4096
 
 CONFIG_DISPLAY=y
 CONFIG_DISPLAY_LOG_LEVEL_ERR=y
diff --git a/samples/subsys/display/lvgl/sample.yaml b/samples/subsys/display/lvgl/sample.yaml
index a58e6d3a576..b2dc1af4750 100644
--- a/samples/subsys/display/lvgl/sample.yaml
+++ b/samples/subsys/display/lvgl/sample.yaml
@@ -1,6 +1,14 @@
 sample:
   description: LVGL sample application
   name: lvgl
+common:
+  tags:
+    - display
+    - gui
+    - lvgl
+    - samples
+  modules:
+    - lvgl
 tests:
   sample.display.lvgl.gui:
     filter: dt_chosen_enabled("zephyr,display")
@@ -11,16 +19,10 @@ tests:
     min_flash: 250
     min_ram: 32
     harness: none
-    tags:
-      - samples
-      - display
-      - gui
-      - lvgl
-    modules:
-      - lvgl
     integration_platforms:
       - native_sim/native/64
   sample.display.lvgl.rk055hdmipi4m:
+    tags: shield
     # This sample is intended to test the RT1170 and RT595, which require
     # a display shield to work with LVGL
     min_flash: 250
@@ -28,12 +30,6 @@ tests:
     # but the RT595 uses external PSRAM for the display buffer
     min_ram: 32
     harness: none
-    tags:
-      - samples
-      - display
-      - gui
-    modules:
-      - lvgl
     extra_args: SHIELD="rk055hdmipi4m"
     platform_allow:
       - mimxrt1170_evk/mimxrt1176/cm7
@@ -43,36 +39,23 @@ tests:
     harness_config:
       fixture: fixture_display_rk055hdmipi4m
   sample.subsys.display.lvgl.st_b_lcd40_dsi1_mb1166:
+    tags: shield
     filter: dt_compat_enabled("orisetech,otm8009a")
     platform_allow: stm32h747i_disco/stm32h747xx/m7
     extra_args: SHIELD=st_b_lcd40_dsi1_mb1166
     harness: console
     harness_config:
       fixture: fixture_display
-    modules:
-      - lvgl
-    tags:
-      - samples
-      - display
-      - shield
-      - lvgl
-      - gui
   sample.subsys.display.lvgl.st_b_lcd40_dsi1_mb1166_a09:
+    tags: shield
     filter: dt_compat_enabled("frida,nt35510")
     platform_allow: stm32h747i_disco/stm32h747xx/m7
     extra_args: SHIELD=st_b_lcd40_dsi1_mb1166_a09
     harness: console
     harness_config:
       fixture: fixture_display
-    modules:
-      - lvgl
-    tags:
-      - samples
-      - display
-      - shield
-      - lvgl
-      - gui
-  samples.subsys.display.lvgl.rk043fn66hs_ctg:
+  sample.subsys.display.lvgl.rk043fn66hs_ctg:
+    tags: shield
     platform_allow:
       - mimxrt1064_evk
       - mimxrt1060_evk/mimxrt1062/qspi
@@ -80,31 +63,45 @@ tests:
       - mimxrt1040_evk
     integration_platforms:
       - mimxrt1040_evk
-    tags: display
     harness: console
     extra_args: SHIELD=rk043fn66hs_ctg
     harness_config:
       fixture: fixture_display_rk043fn66hs_ctg
-  samples.subsys.display.lvgl.rk043fn02h_ct:
+  sample.subsys.display.lvgl.rk043fn02h_ct:
+    tags: shield
     platform_allow:
       - mimxrt1064_evk
-      - mimxrt1060_evk/mimxrt1062/qspi
+      - mimxrt1060_evk@C/mimxrt1062/qspi
       - mimxrt1050_evk/mimxrt1052/hyperflash
       - mimxrt1040_evk
     integration_platforms:
       - mimxrt1040_evk
-    tags: display
     harness: console
     extra_args: SHIELD=rk043fn02h_ct
     harness_config:
       fixture: fixture_display_rk043fn02h_ct
-  samples.subsys.display.lvgl.rtkmipilcdb00000be:
-    platform_allow:
-      - ek_ra8d1
+  sample.subsys.display.lvgl.renesas_ra_glcdc:
     tags:
-      - display
       - shield
-    harness: console
-    extra_args: SHIELD=rtkmipilcdb00000be
+    filter: dt_compat_enabled("renesas,ra-glcdc")
+    extra_args:
+      - platform:ek_ra8d1/r7fa8d1bhecbd:SHIELD=rtkmipilcdb00000be
+      - platform:ek_ra8d1/r7fa8d1bhecbd:SHIELD=rtk7eka6m3b00001bu
     harness_config:
       fixture: fixture_display
+  sample.subsys.display.lvgl.seeed_xiao_round_display:
+    tags: shield
+    min_flash: 320
+    min_ram: 64
+    depends_on:
+      - xiao_adc
+      - xiao_gpio
+      - xiao_i2c
+      - xiao_spi
+    integration_platforms:
+      - xiao_ble
+      - xiao_esp32s3/esp32s3/procpu
+    extra_args: SHIELD=seeed_xiao_round_display
+    harness: console
+    harness_config:
+      fixture: fixture_seeed_xiao_round_display
diff --git a/samples/subsys/fs/fatfs_fstab/CMakeLists.txt b/samples/subsys/fs/fatfs_fstab/CMakeLists.txt
new file mode 100644
index 00000000000..3b5f0cb2158
--- /dev/null
+++ b/samples/subsys/fs/fatfs_fstab/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Endress+Hauser AG
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(fatfs_fstab_sample)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/samples/subsys/fs/fatfs_fstab/README.rst b/samples/subsys/fs/fatfs_fstab/README.rst
new file mode 100644
index 00000000000..6ad098d0a6e
--- /dev/null
+++ b/samples/subsys/fs/fatfs_fstab/README.rst
@@ -0,0 +1,36 @@
+.. zephyr:code-sample:: fatfs-fstab
+   :name: Fatfs filesystem fstab
+   :relevant-api: file_system_api
+
+   Define fatfs filesystems in the devicetree.
+
+Overview
+***********
+
+This sample shows how to define a fatfs fstab entry in the devicetree.
+This scenario uses a fatfs on a RAM disk. The sample is run on the
+``native_sim`` board.
+
+Building and running
+********************
+
+To run this sample, build it for the ``native_sim`` board
+and afterwards run the generated executable file within the build folder.
+
+The RAM disk sample for the ``native_sim`` board can be built as follows:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/subsys/fs/fatfs_fstab
+   :host-os: unix
+   :board: native_sim
+   :gen-args: -DDTC_OVERLAY_FILE=fatfs_fstab.overlay
+   :goals: build
+   :compact:
+
+Sample Output
+=============
+
+When the sample runs successfully you should see following message on the screen:
+.. code-block:: console
+
+  I: Filesystem access successful
diff --git a/samples/subsys/fs/fatfs_fstab/fatfs_fstab.overlay b/samples/subsys/fs/fatfs_fstab/fatfs_fstab.overlay
new file mode 100644
index 00000000000..d537973911c
--- /dev/null
+++ b/samples/subsys/fs/fatfs_fstab/fatfs_fstab.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025 Endress+Hauser AG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	fstab {
+		compatible = "zephyr,fstab";
+		ffs1: ffs1 {
+			compatible = "zephyr,fstab,fatfs";
+			automount;
+			disk-access;
+			mount-point = "/RAM:";
+		};
+	};
+
+	ramdisk0 {
+		compatible = "zephyr,ram-disk";
+		disk-name = "RAM";
+		sector-size = <512>;
+		sector-count = <128>;
+	};
+};
diff --git a/samples/subsys/fs/fatfs_fstab/prj.conf b/samples/subsys/fs/fatfs_fstab/prj.conf
new file mode 100644
index 00000000000..339f38486f8
--- /dev/null
+++ b/samples/subsys/fs/fatfs_fstab/prj.conf
@@ -0,0 +1,10 @@
+CONFIG_DISK_ACCESS=y
+CONFIG_DISK_DRIVERS=y
+
+CONFIG_LOG=y
+CONFIG_LOG_MODE_MINIMAL=y
+
+CONFIG_FILE_SYSTEM=y
+CONFIG_FILE_SYSTEM_MKFS=y
+CONFIG_FAT_FILESYSTEM_ELM=y
+CONFIG_FS_FATFS_FSTAB_AUTOMOUNT=y
diff --git a/samples/subsys/fs/fatfs_fstab/sample.yaml b/samples/subsys/fs/fatfs_fstab/sample.yaml
new file mode 100644
index 00000000000..b9464174925
--- /dev/null
+++ b/samples/subsys/fs/fatfs_fstab/sample.yaml
@@ -0,0 +1,14 @@
+sample:
+  name: fatfs fstab sample
+tests:
+  sample.filesystem.fat_fs.fstab:
+    platform_allow:
+      - native_sim
+    extra_args:
+      - EXTRA_DTC_OVERLAY_FILE="fatfs_fstab.overlay"
+    tags: filesystem
+    harness: console
+    harness_config:
+      type: one_line
+      regex:
+        - "I: Filesystem access successful"
diff --git a/samples/subsys/fs/fatfs_fstab/src/main.c b/samples/subsys/fs/fatfs_fstab/src/main.c
new file mode 100644
index 00000000000..3f98d0debda
--- /dev/null
+++ b/samples/subsys/fs/fatfs_fstab/src/main.c
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2025 Endress+Hauser AG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <ff.h>
+#include <zephyr/device.h>
+#include <zephyr/fs/fs.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/storage/disk_access.h>
+
+LOG_MODULE_REGISTER(main, LOG_LEVEL_INF);
+
+#define AUTOMOUNT_NODE DT_NODELABEL(ffs1)
+FS_FSTAB_DECLARE_ENTRY(AUTOMOUNT_NODE);
+
+#define FILE_PATH "/RAM:/hello.txt"
+
+int main(void)
+{
+	struct fs_file_t file;
+	int rc;
+	static const char data[] = "Hello";
+	/* You can get direct mount point to automounted node too */
+	struct fs_mount_t *auto_mount_point = &FS_FSTAB_ENTRY(AUTOMOUNT_NODE);
+	struct fs_dirent stat;
+
+	fs_file_t_init(&file);
+
+	rc = fs_open(&file, FILE_PATH, FS_O_CREATE | FS_O_WRITE);
+	if (rc != 0) {
+		LOG_ERR("Accessing filesystem failed");
+		return rc;
+	}
+
+	rc = fs_write(&file, data, strlen(data));
+	if (rc != strlen(data)) {
+		LOG_ERR("Writing filesystem failed");
+		return rc;
+	}
+
+	rc = fs_close(&file);
+	if (rc != 0) {
+		LOG_ERR("Closing file failed");
+		return rc;
+	}
+
+	/* You can unmount the automount node */
+	rc = fs_unmount(auto_mount_point);
+	if (rc != 0) {
+		LOG_ERR("Failed to do unmount");
+		return rc;
+	};
+
+	/* And mount it back */
+	rc = fs_mount(auto_mount_point);
+	if (rc != 0) {
+		LOG_ERR("Failed to remount the auto-mount node");
+		return rc;
+	}
+
+	/* Is the file still there? */
+	rc = fs_stat(FILE_PATH, &stat);
+	if (rc != 0) {
+		LOG_ERR("File status check failed %d", rc);
+		return rc;
+	}
+
+	LOG_INF("Filesystem access successful");
+
+	return 0;
+}
diff --git a/samples/subsys/fs/format/README.rst b/samples/subsys/fs/format/README.rst
index 59029d2dbfa..327563fbd9d 100644
--- a/samples/subsys/fs/format/README.rst
+++ b/samples/subsys/fs/format/README.rst
@@ -45,6 +45,7 @@ Sample Output
 =============
 
 When the sample runs successfully you should see following message on the screen:
+
 .. code-block:: console
 
   I: LittleFS version 2.4, disk version 2.0
diff --git a/samples/subsys/fs/fs_sample/boards/apollo4p_evb.conf b/samples/subsys/fs/fs_sample/boards/apollo4p_evb.conf
new file mode 100644
index 00000000000..dd0e39f6b37
--- /dev/null
+++ b/samples/subsys/fs/fs_sample/boards/apollo4p_evb.conf
@@ -0,0 +1,11 @@
+CONFIG_DISK_DRIVER_MMC=y
+CONFIG_MMC_STACK=y
+CONFIG_SDHC=y
+CONFIG_MMC_SUBSYS=y
+
+CONFIG_MAIN_STACK_SIZE=8192
+CONFIG_IDLE_STACK_SIZE=4096
+CONFIG_AMBIQ_SDIO_ASYNC=y
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_PM_DEVICE_RUNTIME=y
diff --git a/samples/subsys/fs/fs_sample/boards/bl54l15_dvk_nrf54l15_cpuapp.conf b/samples/subsys/fs/fs_sample/boards/bl54l15_dvk_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..56d24fc0618
--- /dev/null
+++ b/samples/subsys/fs/fs_sample/boards/bl54l15_dvk_nrf54l15_cpuapp.conf
@@ -0,0 +1,11 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DISK_DRIVERS=y
+CONFIG_DISK_DRIVER_FLASH=y
+# There may be no files on internal SoC flash, so this Kconfig
+# options has ben enabled to create some if listing does not
+# find in the first place.
+CONFIG_FS_SAMPLE_CREATE_SOME_ENTRIES=y
diff --git a/samples/subsys/fs/fs_sample/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/samples/subsys/fs/fs_sample/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..2311a039702
--- /dev/null
+++ b/samples/subsys/fs/fs_sample/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Because FAT FS needs at least 64kiB partition and default
+ * storage_partition is 36kiB for this board, we need to reorganize
+ * partitions to get at least 64KiB.
+ */
+/delete-node/ &slot0_partition;
+/delete-node/ &slot1_partition;
+/delete-node/ &slot0_ns_partition;
+/delete-node/ &slot1_ns_partition;
+/delete-node/ &storage_partition;
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		slot0_partition: parition@10000 {
+			reg = <0x00010000 DT_SIZE_K(300)>;
+		};
+
+		slot1_partition: partition@5b000 {
+			reg = <0x0005b000 DT_SIZE_K(300)>;
+		};
+
+		storage_partition: partition@a6000 {
+			label = "storage";
+			reg = <0x000a6000 DT_SIZE_K(128)>;
+		};
+	};
+};
+
+/ {
+	msc_disk0 {
+		status="okay";
+		compatible = "zephyr,flash-disk";
+		partition = <&storage_partition>;
+		disk-name = "SD";
+		cache-size = <512>;
+	};
+};
diff --git a/samples/subsys/fs/fs_sample/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf b/samples/subsys/fs/fs_sample/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..56d24fc0618
--- /dev/null
+++ b/samples/subsys/fs/fs_sample/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf
@@ -0,0 +1,11 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DISK_DRIVERS=y
+CONFIG_DISK_DRIVER_FLASH=y
+# There may be no files on internal SoC flash, so this Kconfig
+# options has ben enabled to create some if listing does not
+# find in the first place.
+CONFIG_FS_SAMPLE_CREATE_SOME_ENTRIES=y
diff --git a/samples/subsys/fs/fs_sample/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/samples/subsys/fs/fs_sample/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..2311a039702
--- /dev/null
+++ b/samples/subsys/fs/fs_sample/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Because FAT FS needs at least 64kiB partition and default
+ * storage_partition is 36kiB for this board, we need to reorganize
+ * partitions to get at least 64KiB.
+ */
+/delete-node/ &slot0_partition;
+/delete-node/ &slot1_partition;
+/delete-node/ &slot0_ns_partition;
+/delete-node/ &slot1_ns_partition;
+/delete-node/ &storage_partition;
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		slot0_partition: parition@10000 {
+			reg = <0x00010000 DT_SIZE_K(300)>;
+		};
+
+		slot1_partition: partition@5b000 {
+			reg = <0x0005b000 DT_SIZE_K(300)>;
+		};
+
+		storage_partition: partition@a6000 {
+			label = "storage";
+			reg = <0x000a6000 DT_SIZE_K(128)>;
+		};
+	};
+};
+
+/ {
+	msc_disk0 {
+		status="okay";
+		compatible = "zephyr,flash-disk";
+		partition = <&storage_partition>;
+		disk-name = "SD";
+		cache-size = <512>;
+	};
+};
diff --git a/samples/subsys/fs/fs_sample/boards/max32666fthr_max32666_cpu0.conf b/samples/subsys/fs/fs_sample/boards/max32666fthr_max32666_cpu0.conf
new file mode 100644
index 00000000000..7b52334dee7
--- /dev/null
+++ b/samples/subsys/fs/fs_sample/boards/max32666fthr_max32666_cpu0.conf
@@ -0,0 +1,3 @@
+CONFIG_SDMMC_SUBSYS=y
+CONFIG_SDHC=y
+CONFIG_LOG=n
diff --git a/samples/subsys/fs/fs_sample/boards/ophelia4ev_nrf54l15_cpuapp.conf b/samples/subsys/fs/fs_sample/boards/ophelia4ev_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..e142dedd450
--- /dev/null
+++ b/samples/subsys/fs/fs_sample/boards/ophelia4ev_nrf54l15_cpuapp.conf
@@ -0,0 +1,12 @@
+#
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_DISK_DRIVERS=y
+CONFIG_DISK_DRIVER_FLASH=y
+# There may be no files on internal SoC flash, so this Kconfig
+# options has ben enabled to create some if listing does not
+# find in the first place.
+CONFIG_FS_SAMPLE_CREATE_SOME_ENTRIES=y
diff --git a/samples/subsys/fs/fs_sample/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/samples/subsys/fs/fs_sample/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..da13128938a
--- /dev/null
+++ b/samples/subsys/fs/fs_sample/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Because FAT FS needs at least 64kiB partition and default
+ * storage_partition is 36kiB for this board, we need to reorganize
+ * partitions to get at least 64KiB.
+ */
+/delete-node/ &slot0_partition;
+/delete-node/ &slot1_partition;
+/delete-node/ &slot0_ns_partition;
+/delete-node/ &slot1_ns_partition;
+/delete-node/ &storage_partition;
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		slot0_partition: parition@10000 {
+			reg = <0x00010000 DT_SIZE_K(300)>;
+		};
+
+		slot1_partition: partition@5b000 {
+			reg = <0x0005b000 DT_SIZE_K(300)>;
+		};
+
+		storage_partition: partition@a6000 {
+			label = "storage";
+			reg = <0x000a6000 DT_SIZE_K(128)>;
+		};
+	};
+};
+
+/ {
+	msc_disk0 {
+		status = "okay";
+		compatible = "zephyr,flash-disk";
+		partition = <&storage_partition>;
+		disk-name = "SD";
+		cache-size = <512>;
+	};
+};
diff --git a/samples/subsys/fs/fs_sample/sample.yaml b/samples/subsys/fs/fs_sample/sample.yaml
index af7e4913c6b..e62f32eaee8 100644
--- a/samples/subsys/fs/fs_sample/sample.yaml
+++ b/samples/subsys/fs/fs_sample/sample.yaml
@@ -58,6 +58,9 @@ tests:
   sample.filesystem.fat_fs.nrf54l15dk:
     build_only: true
     platform_allow: nrf54l15dk/nrf54l15/cpuapp
+  sample.filesystem.fat_fs.ophelia4ev:
+    build_only: true
+    platform_allow: ophelia4ev/nrf54l15/cpuapp
   sample.filesystem.fat_fs.nrf52840dk_nrf52840.qspi:
     build_only: true
     platform_allow: nrf52840dk/nrf52840
diff --git a/samples/subsys/fs/littlefs/sample.yaml b/samples/subsys/fs/littlefs/sample.yaml
index 85fa6468ee4..2ab2b47a3c3 100644
--- a/samples/subsys/fs/littlefs/sample.yaml
+++ b/samples/subsys/fs/littlefs/sample.yaml
@@ -24,6 +24,7 @@ tests:
       - stm32h747i_disco/stm32h747xx/m7
       - stm32h750b_dk
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
       - frdm_ke17z
       - frdm_ke17z512
       - s32z2xxdc2/s32z270/rtu0
diff --git a/samples/subsys/ipc/ipc_service/icmsg/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/samples/subsys/ipc/ipc_service/icmsg/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..089508044b5
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/icmsg/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			sram_rx: memory@20018000 {
+				reg = <0x20018000 0x0800>;
+			};
+
+			sram_tx: memory@20020000 {
+				reg = <0x20020000 0x0800>;
+			};
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icmsg";
+			dcache-alignment = <32>;
+			tx-region = <&sram_tx>;
+			rx-region = <&sram_rx>;
+			mboxes = <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_tx 21>;
+			mbox-names = "rx", "tx";
+			status = "okay";
+		};
+	};
+};
+
+&cpuapp_vevif_rx {
+	status = "okay";
+};
+
+&cpuapp_vevif_tx {
+	status = "okay";
+};
diff --git a/samples/subsys/ipc/ipc_service/icmsg/boards/bl54l15_dvk_nrf54l15_cpuapp_icbmsg.overlay b/samples/subsys/ipc/ipc_service/icmsg/boards/bl54l15_dvk_nrf54l15_cpuapp_icbmsg.overlay
new file mode 100644
index 00000000000..b1068f04069
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/icmsg/boards/bl54l15_dvk_nrf54l15_cpuapp_icbmsg.overlay
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			sram_rx: memory@20018000 {
+				reg = <0x20018000 0x0800>;
+			};
+
+			sram_tx: memory@20020000 {
+				reg = <0x20020000 0x0800>;
+			};
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icbmsg";
+			dcache-alignment = <32>;
+			tx-region = <&sram_tx>;
+			rx-region = <&sram_rx>;
+			tx-blocks = <16>;
+			rx-blocks = <18>;
+			mboxes = <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_tx 21>;
+			mbox-names = "rx", "tx";
+			status = "okay";
+		};
+	};
+};
+
+&cpuapp_vevif_rx {
+	status = "okay";
+};
+
+&cpuapp_vevif_tx {
+	status = "okay";
+};
diff --git a/samples/subsys/ipc/ipc_service/icmsg/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/samples/subsys/ipc/ipc_service/icmsg/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..089508044b5
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/icmsg/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			sram_rx: memory@20018000 {
+				reg = <0x20018000 0x0800>;
+			};
+
+			sram_tx: memory@20020000 {
+				reg = <0x20020000 0x0800>;
+			};
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icmsg";
+			dcache-alignment = <32>;
+			tx-region = <&sram_tx>;
+			rx-region = <&sram_rx>;
+			mboxes = <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_tx 21>;
+			mbox-names = "rx", "tx";
+			status = "okay";
+		};
+	};
+};
+
+&cpuapp_vevif_rx {
+	status = "okay";
+};
+
+&cpuapp_vevif_tx {
+	status = "okay";
+};
diff --git a/samples/subsys/ipc/ipc_service/icmsg/boards/bl54l15u_dvk_nrf54l15_cpuapp_icbmsg.overlay b/samples/subsys/ipc/ipc_service/icmsg/boards/bl54l15u_dvk_nrf54l15_cpuapp_icbmsg.overlay
new file mode 100644
index 00000000000..b1068f04069
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/icmsg/boards/bl54l15u_dvk_nrf54l15_cpuapp_icbmsg.overlay
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			sram_rx: memory@20018000 {
+				reg = <0x20018000 0x0800>;
+			};
+
+			sram_tx: memory@20020000 {
+				reg = <0x20020000 0x0800>;
+			};
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icbmsg";
+			dcache-alignment = <32>;
+			tx-region = <&sram_tx>;
+			rx-region = <&sram_rx>;
+			tx-blocks = <16>;
+			rx-blocks = <18>;
+			mboxes = <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_tx 21>;
+			mbox-names = "rx", "tx";
+			status = "okay";
+		};
+	};
+};
+
+&cpuapp_vevif_rx {
+	status = "okay";
+};
+
+&cpuapp_vevif_tx {
+	status = "okay";
+};
diff --git a/samples/subsys/ipc/ipc_service/icmsg/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/samples/subsys/ipc/ipc_service/icmsg/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..22c74fe1178
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/icmsg/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			sram_rx: memory@20018000 {
+				reg = <0x20018000 0x0800>;
+			};
+
+			sram_tx: memory@20020000 {
+				reg = <0x20020000 0x0800>;
+			};
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icmsg";
+			dcache-alignment = <32>;
+			tx-region = <&sram_tx>;
+			rx-region = <&sram_rx>;
+			mboxes = <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_tx 21>;
+			mbox-names = "rx", "tx";
+			status = "okay";
+		};
+	};
+};
+
+&cpuapp_vevif_rx {
+	status = "okay";
+};
+
+&cpuapp_vevif_tx {
+	status = "okay";
+};
diff --git a/samples/subsys/ipc/ipc_service/icmsg/remote/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..1638208917c
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			sram_tx: memory@20018000 {
+				reg = <0x20018000 0x0800>;
+			};
+
+			sram_rx: memory@20020000 {
+				reg = <0x20020000 0x0800>;
+			};
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icmsg";
+			dcache-alignment = <32>;
+			tx-region = <&sram_tx>;
+			rx-region = <&sram_rx>;
+			mboxes = <&cpuflpr_vevif_rx 21>, <&cpuflpr_vevif_tx 20>;
+			mbox-names = "rx", "tx";
+			status = "okay";
+		};
+	};
+};
+
+&cpuflpr_vevif_rx {
+	status = "okay";
+};
+
+&cpuflpr_vevif_tx {
+	status = "okay";
+};
+
+&uart30 {
+	/delete-property/ hw-flow-control;
+};
diff --git a/samples/subsys/ipc/ipc_service/icmsg/remote/boards/bl54l15_dvk_nrf54l15_cpuflpr_icbmsg.overlay b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/bl54l15_dvk_nrf54l15_cpuflpr_icbmsg.overlay
new file mode 100644
index 00000000000..af1fa7ba411
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/bl54l15_dvk_nrf54l15_cpuflpr_icbmsg.overlay
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			sram_tx: memory@20018000 {
+				reg = <0x20018000 0x0800>;
+			};
+
+			sram_rx: memory@20020000 {
+				reg = <0x20020000 0x0800>;
+			};
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icbmsg";
+			dcache-alignment = <32>;
+			tx-region = <&sram_tx>;
+			rx-region = <&sram_rx>;
+			tx-blocks = <18>;
+			rx-blocks = <16>;
+			mboxes = <&cpuflpr_vevif_rx 21>, <&cpuflpr_vevif_tx 20>;
+			mbox-names = "rx", "tx";
+			status = "okay";
+		};
+	};
+};
+
+&cpuflpr_vevif_rx {
+	status = "okay";
+};
+
+&cpuflpr_vevif_tx {
+	status = "okay";
+};
+
+&uart30 {
+	/delete-property/ hw-flow-control;
+};
diff --git a/samples/subsys/ipc/ipc_service/icmsg/remote/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..1638208917c
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			sram_tx: memory@20018000 {
+				reg = <0x20018000 0x0800>;
+			};
+
+			sram_rx: memory@20020000 {
+				reg = <0x20020000 0x0800>;
+			};
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icmsg";
+			dcache-alignment = <32>;
+			tx-region = <&sram_tx>;
+			rx-region = <&sram_rx>;
+			mboxes = <&cpuflpr_vevif_rx 21>, <&cpuflpr_vevif_tx 20>;
+			mbox-names = "rx", "tx";
+			status = "okay";
+		};
+	};
+};
+
+&cpuflpr_vevif_rx {
+	status = "okay";
+};
+
+&cpuflpr_vevif_tx {
+	status = "okay";
+};
+
+&uart30 {
+	/delete-property/ hw-flow-control;
+};
diff --git a/samples/subsys/ipc/ipc_service/icmsg/remote/boards/bl54l15u_dvk_nrf54l15_cpuflpr_icbmsg.overlay b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/bl54l15u_dvk_nrf54l15_cpuflpr_icbmsg.overlay
new file mode 100644
index 00000000000..af1fa7ba411
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/icmsg/remote/boards/bl54l15u_dvk_nrf54l15_cpuflpr_icbmsg.overlay
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			sram_tx: memory@20018000 {
+				reg = <0x20018000 0x0800>;
+			};
+
+			sram_rx: memory@20020000 {
+				reg = <0x20020000 0x0800>;
+			};
+		};
+	};
+
+	ipc {
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-icbmsg";
+			dcache-alignment = <32>;
+			tx-region = <&sram_tx>;
+			rx-region = <&sram_rx>;
+			tx-blocks = <18>;
+			rx-blocks = <16>;
+			mboxes = <&cpuflpr_vevif_rx 21>, <&cpuflpr_vevif_tx 20>;
+			mbox-names = "rx", "tx";
+			status = "okay";
+		};
+	};
+};
+
+&cpuflpr_vevif_rx {
+	status = "okay";
+};
+
+&cpuflpr_vevif_tx {
+	status = "okay";
+};
+
+&uart30 {
+	/delete-property/ hw-flow-control;
+};
diff --git a/samples/subsys/ipc/ipc_service/icmsg/src/main.c b/samples/subsys/ipc/ipc_service/icmsg/src/main.c
index 86469cac64b..afb5016dbeb 100644
--- a/samples/subsys/ipc/ipc_service/icmsg/src/main.c
+++ b/samples/subsys/ipc/ipc_service/icmsg/src/main.c
@@ -40,6 +40,11 @@ static void ep_bound(void *priv)
 	LOG_INF("Ep bounded");
 }
 
+static void ep_unbound(void *priv)
+{
+	LOG_INF("Ep unbounded");
+}
+
 static void ep_recv(const void *data, size_t len, void *priv)
 {
 #if defined(CONFIG_ASSERT)
@@ -68,6 +73,11 @@ static void ep_recv(const void *data, size_t len, void *priv)
 	}
 }
 
+static void ep_error(const char *message, void *priv)
+{
+	LOG_ERR("ICMsg error: %s", message);
+}
+
 static int send_for_time(struct ipc_ept *ep, const int64_t sending_time_ms)
 {
 	struct data_packet msg = {.data[0] = 'a'};
@@ -123,7 +133,9 @@ static int send_for_time(struct ipc_ept *ep, const int64_t sending_time_ms)
 static struct ipc_ept_cfg ep_cfg = {
 	.cb = {
 		.bound    = ep_bound,
+		.unbound  = ep_unbound,
 		.received = ep_recv,
+		.error    = ep_error,
 	},
 };
 
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/CMakeLists.txt b/samples/subsys/ipc/ipc_service/static_vrings/CMakeLists.txt
index 588bfe71dd0..33ee890f8f8 100644
--- a/samples/subsys/ipc/ipc_service/static_vrings/CMakeLists.txt
+++ b/samples/subsys/ipc/ipc_service/static_vrings/CMakeLists.txt
@@ -1,6 +1,6 @@
 #
 # Copyright (c) 2021 Carlo Caione <ccaione@baylibre.com>
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -9,18 +9,24 @@ cmake_minimum_required(VERSION 3.20.0)
 
 find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
 
+if(CONFIG_INCLUDE_REMOTE_DIR)
 set(REMOTE_ZEPHYR_DIR ${CMAKE_CURRENT_BINARY_DIR}/../remote/zephyr)
+endif()
 
 if(NOT (CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP OR
         CONFIG_BOARD_NRF5340BSIM_NRF5340_CPUAPP OR
         CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 OR
         CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 OR
-        CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7
+        CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7 OR
+        CONFIG_BOARD_FRDM_MCXN947_MCXN947_CPU0 OR
+        CONFIG_BOARD_MCX_N9XX_EVK_MCXN947_CPU0 OR
+        CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33
        )
   )
-  message(FATAL_ERROR "${BOARD} is not supported for this sample")
+  message("${BOARD} is not supported for this sample")
 endif()
 
+
 project(ipc_service)
 
 if(CONFIG_INCLUDE_REMOTE_DIR)
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/Kconfig.sysbuild b/samples/subsys/ipc/ipc_service/static_vrings/Kconfig.sysbuild
index 4f9caa82501..4f6465f0e43 100644
--- a/samples/subsys/ipc/ipc_service/static_vrings/Kconfig.sysbuild
+++ b/samples/subsys/ipc/ipc_service/static_vrings/Kconfig.sysbuild
@@ -1,5 +1,5 @@
 # Copyright 2023 Nordic Semiconductor ASA
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 
@@ -13,3 +13,6 @@ string
 	default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk"
 	default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk"
 	default "mimxrt1170_evkb/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evkb"
+	default "frdm_mcxn947/mcxn947/cpu1" if $(BOARD) = "frdm_mcxn947"
+	default "mcx_n9xx_evk/mcxn947/cpu1" if $(BOARD) = "mcx_n9xx_evk"
+	default "mimxrt1180_evk/mimxrt1189/cm7" if $(BOARD) = "mimxrt1180_evk"
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/README.rst b/samples/subsys/ipc/ipc_service/static_vrings/README.rst
index 8fe0591b786..b0b164abf4e 100644
--- a/samples/subsys/ipc/ipc_service/static_vrings/README.rst
+++ b/samples/subsys/ipc/ipc_service/static_vrings/README.rst
@@ -47,12 +47,12 @@ Building the application for mimxrt1170_evk/mimxrt1176/cm7
    :goals: debug
    :west-args: --sysbuild
 
-Building the application for mimxrt1170_evk@B/mimxrt1176/cm7
+Building the application for frdm_mcxn947/mcxn947/cpu0
 ************************************************************
 
 .. zephyr-app-commands::
    :zephyr-app: samples/subsys/ipc/ipc_service/static_vrings
-   :board: mimxrt1170_evk@B/mimxrt1176/cm7
+   :board: frdm_mcxn947/mcxn947/cpu0
    :goals: debug
    :west-args: --sysbuild
 
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/frdm_mcxn947_mcxn947_cpu0.conf b/samples/subsys/ipc/ipc_service/static_vrings/boards/frdm_mcxn947_mcxn947_cpu0.conf
new file mode 100644
index 00000000000..7e6904d56d5
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/frdm_mcxn947_mcxn947_cpu0.conf
@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/frdm_mcxn947_mcxn947_cpu0.overlay b/samples/subsys/ipc/ipc_service/static_vrings/boards/frdm_mcxn947_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..19bbe1e16d7
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/frdm_mcxn947_mcxn947_cpu0.overlay
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/ipc_service/static_vrings.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	/* Define memory regions for IPC
+	 * Note that shared memory must have specific MPU attributes set.
+	 */
+	sram1_ipc0: memory@20060000{
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20060000 DT_SIZE_K(16)>;
+		zephyr,memory-region="SRAM1_IPC0";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>;
+	};
+
+	sram1_ipc1: memory@20064000{
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20064000 DT_SIZE_K(16)>;
+		zephyr,memory-region="SRAM1_IPC1";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>;
+	};
+
+	ipc {
+		/delete-node/ ipc0;
+
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-openamp-static-vrings";
+			memory-region = <&sram1_ipc0>;
+			mboxes = <&mbox 0>, <&mbox 1>;
+			mbox-names = "tx", "rx";
+			role = "host";
+			status = "okay";
+		};
+
+		ipc1: ipc1 {
+			compatible = "zephyr,ipc-openamp-static-vrings";
+			memory-region = <&sram1_ipc1>;
+			mboxes = <&mbox 2>, <&mbox 3>;
+			mbox-names = "tx", "rx";
+			role = "host";
+			zephyr,priority = <1 PRIO_COOP>;
+			zephyr,buffer-size = <128>;
+			status = "okay";
+		};
+	};
+};
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay b/samples/subsys/ipc/ipc_service/static_vrings/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay
index 63efb05fee5..282c868cd14 100644
--- a/samples/subsys/ipc/ipc_service/static_vrings/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay
+++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay
@@ -9,7 +9,7 @@
 
 / {
 	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/mcx_n9xx_evk_mcxn947_cpu0.conf b/samples/subsys/ipc/ipc_service/static_vrings/boards/mcx_n9xx_evk_mcxn947_cpu0.conf
new file mode 100644
index 00000000000..7e6904d56d5
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/mcx_n9xx_evk_mcxn947_cpu0.conf
@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/samples/subsys/ipc/ipc_service/static_vrings/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..19bbe1e16d7
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/ipc_service/static_vrings.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	/* Define memory regions for IPC
+	 * Note that shared memory must have specific MPU attributes set.
+	 */
+	sram1_ipc0: memory@20060000{
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20060000 DT_SIZE_K(16)>;
+		zephyr,memory-region="SRAM1_IPC0";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>;
+	};
+
+	sram1_ipc1: memory@20064000{
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20064000 DT_SIZE_K(16)>;
+		zephyr,memory-region="SRAM1_IPC1";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>;
+	};
+
+	ipc {
+		/delete-node/ ipc0;
+
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-openamp-static-vrings";
+			memory-region = <&sram1_ipc0>;
+			mboxes = <&mbox 0>, <&mbox 1>;
+			mbox-names = "tx", "rx";
+			role = "host";
+			status = "okay";
+		};
+
+		ipc1: ipc1 {
+			compatible = "zephyr,ipc-openamp-static-vrings";
+			memory-region = <&sram1_ipc1>;
+			mboxes = <&mbox 2>, <&mbox 3>;
+			mbox-names = "tx", "rx";
+			role = "host";
+			zephyr,priority = <1 PRIO_COOP>;
+			zephyr,buffer-size = <128>;
+			status = "okay";
+		};
+	};
+};
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay
index 0abcec2d647..35cf8f60649 100644
--- a/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay
+++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay
@@ -9,7 +9,7 @@
 
 / {
 	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
index 132401362cb..13f89c250e2 100644
--- a/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
+++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
@@ -9,7 +9,7 @@
 
 / {
 	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf
deleted file mode 100644
index 0dfb100ed70..00000000000
--- a/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_MBOX_NXP_IMX_MU=y
-CONFIG_SECOND_CORE_MCUX=y
-CONFIG_INCLUDE_REMOTE_DIR=y
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
deleted file mode 100644
index 132401362cb..00000000000
--- a/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright 2024 NXP
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/dt-bindings/ipc_service/static_vrings.h>
-#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
-
-/ {
-	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
-		 * configured.
-		 */
-		/delete-property/ zephyr,ipc;
-		/delete-property/ zephyr,ipc_shm;
-
-		zephyr,console = &lpuart1;
-		zephyr,shell-uart = &lpuart1;
-	};
-
-	/* Define memory regions for IPC
-	 * Note that shared memory must have specific MPU attributes set.
-	 */
-	ocram2_ipc0: memory@202c0000{
-		compatible = "zephyr,memory-region", "mmio-sram";
-		reg = <0x202c0000 DT_SIZE_K(32)>;
-		zephyr,memory-region="OCRAM2_IPC0";
-		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>;
-	};
-	ocram2_ipc1: memory@202c8000{
-		compatible = "zephyr,memory-region", "mmio-sram";
-		reg = <0x202c8000 DT_SIZE_K(32)>;
-		zephyr,memory-region="OCRAM2_IPC1";
-		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>;
-	};
-
-	soc {
-		/* Delete IPM Driver node nxp,imx-mu */
-		/delete-node/ mailbox@40c48000;
-
-		/* Attach MBOX driver to MU Unit */
-		mbox:mbox@40c48000 {
-			compatible = "nxp,mbox-imx-mu";
-			reg = <0x40c48000 0x4000>;
-			interrupts = <118 0>;
-			rx-channels = <4>;
-			#mbox-cells = <1>;
-			status = "okay";
-		};
-	};
-
-	ipc {
-		/delete-node/ ipc0;
-
-		ipc0: ipc0 {
-			compatible = "zephyr,ipc-openamp-static-vrings";
-			memory-region = <&ocram2_ipc0>;
-			mboxes = <&mbox 0>, <&mbox 1>;
-			mbox-names = "tx", "rx";
-			role = "host";
-			status = "okay";
-		};
-
-		ipc1: ipc1 {
-			compatible = "zephyr,ipc-openamp-static-vrings";
-			memory-region = <&ocram2_ipc1>;
-			mboxes = <&mbox 2>, <&mbox 3>;
-			mbox-names = "tx", "rx";
-			role = "host";
-			zephyr,priority = <1 PRIO_COOP>;
-			zephyr,buffer-size = <128>;
-			status = "okay";
-		};
-	};
-};
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1180_evk_mimxrt1189_cm33.conf b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1180_evk_mimxrt1189_cm33.conf
new file mode 100644
index 00000000000..60eead5a076
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1180_evk_mimxrt1189_cm33.conf
@@ -0,0 +1,2 @@
+CONFIG_SECOND_CORE_MCUX=y
+CONFIG_INCLUDE_REMOTE_DIR=y
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
new file mode 100644
index 00000000000..2bcb5766605
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/static_vrings/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/ipc_service/static_vrings.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	/* Define memory regions for IPC */
+	ocram2_ipc0: memory@20500000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20500000 DT_SIZE_K(16)>;
+		zephyr,memory-region="OCRAM2_IPC0";
+		zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_IO))>;
+	};
+
+	ocram2_ipc1: memory@20504000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20504000 DT_SIZE_K(16)>;
+		zephyr,memory-region="OCRAM2_IPC1";
+		zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_IO))>;
+	};
+
+	ipc {
+		/delete-node/ ipc0;
+
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-openamp-static-vrings";
+			memory-region = <&ocram2_ipc0>;
+			mboxes = <&mbox1_a 0>, <&mbox1_a 1>;
+			mbox-names = "tx", "rx";
+			role = "host";
+			status = "okay";
+		};
+
+		ipc1: ipc1 {
+			compatible = "zephyr,ipc-openamp-static-vrings";
+			memory-region = <&ocram2_ipc1>;
+			mboxes = <&mbox1_a 2>, <&mbox1_a 3>;
+			mbox-names = "tx", "rx";
+			role = "host";
+			zephyr,priority = <1 PRIO_COOP>;
+			zephyr,buffer-size = <128>;
+			status = "okay";
+		};
+	};
+};
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/frdm_mcxn947_mcxn947_cpu1.conf b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/frdm_mcxn947_mcxn947_cpu1.conf
new file mode 100644
index 00000000000..7e6904d56d5
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/frdm_mcxn947_mcxn947_cpu1.conf
@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay
new file mode 100644
index 00000000000..4960c985616
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/ipc_service/static_vrings.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	/* Define memory regions for IPC
+	 * Note that shared memory must have specific MPU attributes set.
+	 */
+	 sram1_ipc0: memory@20060000{
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20060000 DT_SIZE_K(16)>;
+		zephyr,memory-region="SRAM1_IPC0";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>;
+	};
+
+	sram1_ipc1: memory@20064000{
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20064000 DT_SIZE_K(16)>;
+		zephyr,memory-region="SRAM1_IPC1";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>;
+	};
+
+	ipc {
+		/delete-node/ ipc0;
+
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-openamp-static-vrings";
+			memory-region = <&sram1_ipc0>;
+			mboxes = <&mbox 0>, <&mbox 1>;
+			mbox-names = "rx", "tx";
+			role = "remote";
+			status = "okay";
+		};
+
+		ipc1: ipc1 {
+			compatible = "zephyr,ipc-openamp-static-vrings";
+			memory-region = <&sram1_ipc1>;
+			mboxes = <&mbox 2>, <&mbox 3>;
+			mbox-names = "rx", "tx";
+			role = "remote";
+			zephyr,priority = <1 PRIO_COOP>;
+			zephyr,buffer-size = <128>;
+			status = "okay";
+		};
+	};
+};
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay
index 9c155598246..2fba21fb1e4 100644
--- a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay
+++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay
@@ -9,7 +9,7 @@
 
 / {
 	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.conf b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.conf
new file mode 100644
index 00000000000..7e6904d56d5
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.conf
@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay
new file mode 100644
index 00000000000..4960c985616
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/ipc_service/static_vrings.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	/* Define memory regions for IPC
+	 * Note that shared memory must have specific MPU attributes set.
+	 */
+	 sram1_ipc0: memory@20060000{
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20060000 DT_SIZE_K(16)>;
+		zephyr,memory-region="SRAM1_IPC0";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>;
+	};
+
+	sram1_ipc1: memory@20064000{
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20064000 DT_SIZE_K(16)>;
+		zephyr,memory-region="SRAM1_IPC1";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO))>;
+	};
+
+	ipc {
+		/delete-node/ ipc0;
+
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-openamp-static-vrings";
+			memory-region = <&sram1_ipc0>;
+			mboxes = <&mbox 0>, <&mbox 1>;
+			mbox-names = "rx", "tx";
+			role = "remote";
+			status = "okay";
+		};
+
+		ipc1: ipc1 {
+			compatible = "zephyr,ipc-openamp-static-vrings";
+			memory-region = <&sram1_ipc1>;
+			mboxes = <&mbox 2>, <&mbox 3>;
+			mbox-names = "rx", "tx";
+			role = "remote";
+			zephyr,priority = <1 PRIO_COOP>;
+			zephyr,buffer-size = <128>;
+			status = "okay";
+		};
+	};
+};
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay
index 274700289bf..8ba9d176fd3 100644
--- a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay
+++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay
@@ -13,7 +13,7 @@
 		zephyr,console = &lpuart2;
 		zephyr,shell-uart = &lpuart2;
 
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay
index 274700289bf..8ba9d176fd3 100644
--- a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay
+++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay
@@ -13,7 +13,7 @@
 		zephyr,console = &lpuart2;
 		zephyr,shell-uart = &lpuart2;
 
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay
index 274700289bf..8ba9d176fd3 100644
--- a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay
+++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay
@@ -13,7 +13,7 @@
 		zephyr,console = &lpuart2;
 		zephyr,shell-uart = &lpuart2;
 
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.conf b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
new file mode 100644
index 00000000000..77adcfa24f4
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
@@ -0,0 +1,2 @@
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
new file mode 100644
index 00000000000..d6958308790
--- /dev/null
+++ b/samples/subsys/ipc/ipc_service/static_vrings/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/ipc_service/static_vrings.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	/* Define memory regions for IPC */
+	ocram2_ipc0: memory@20500000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20500000 DT_SIZE_K(16)>;
+		zephyr,memory-region="OCRAM2_IPC0";
+		zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_IO))>;
+	};
+
+	ocram2_ipc1: memory@20504000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20504000 DT_SIZE_K(16)>;
+		zephyr,memory-region="OCRAM2_IPC1";
+		zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_IO))>;
+	};
+
+	ipc {
+		/delete-node/ ipc0;
+
+		ipc0: ipc0 {
+			compatible = "zephyr,ipc-openamp-static-vrings";
+			memory-region = <&ocram2_ipc0>;
+			mboxes = <&mbox1_b 0>, <&mbox1_b 1>;
+			mbox-names = "rx", "tx";
+			role = "remote";
+			status = "okay";
+		};
+
+		ipc1: ipc1 {
+			compatible = "zephyr,ipc-openamp-static-vrings";
+			memory-region = <&ocram2_ipc1>;
+			mboxes = <&mbox1_b 2>, <&mbox1_b 3>;
+			mbox-names = "rx", "tx";
+			role = "remote";
+			zephyr,priority = <1 PRIO_COOP>;
+			zephyr,buffer-size = <128>;
+			status = "okay";
+		};
+	};
+};
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/sample.yaml b/samples/subsys/ipc/ipc_service/static_vrings/sample.yaml
index d15df7b803e..64abcf6375a 100644
--- a/samples/subsys/ipc/ipc_service/static_vrings/sample.yaml
+++ b/samples/subsys/ipc/ipc_service/static_vrings/sample.yaml
@@ -2,13 +2,8 @@ sample:
   name: IPC Service example integration (OpenAMP static_vrings backend)
 tests:
   sample.ipc.static_vrings:
-    platform_allow:
-      - nrf5340dk/nrf5340/cpuapp
-      - nrf5340bsim/nrf5340/cpuapp
-      - lpcxpresso55s69/lpc55s69/cpu0
-      - mimxrt1160_evk/mimxrt1166/cm7
-      - mimxrt1170_evk/mimxrt1176/cm7
-      - mimxrt1170_evk@B/mimxrt1176/cm7
+    filter: dt_compat_enabled("zephyr,ipc-openamp-static-vrings") and
+            dt_nodelabel_enabled("ipc0") and dt_nodelabel_enabled("ipc1")
     integration_platforms:
       - nrf5340dk/nrf5340/cpuapp
       - nrf5340bsim/nrf5340/cpuapp
diff --git a/samples/subsys/ipc/ipc_service/static_vrings/sysbuild.cmake b/samples/subsys/ipc/ipc_service/static_vrings/sysbuild.cmake
index cf5de9dd941..0e58efa5f6f 100644
--- a/samples/subsys/ipc/ipc_service/static_vrings/sysbuild.cmake
+++ b/samples/subsys/ipc/ipc_service/static_vrings/sysbuild.cmake
@@ -3,7 +3,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 if("${SB_CONFIG_NET_CORE_BOARD}" STREQUAL "")
-	message(FATAL_ERROR
+	message(
 	"Target ${BOARD} not supported for this sample. "
 	"There is no remote board selected in Kconfig.sysbuild")
 endif()
diff --git a/samples/subsys/ipc/openamp/Kconfig.sysbuild b/samples/subsys/ipc/openamp/Kconfig.sysbuild
index 9063dacafa1..6861e262118 100644
--- a/samples/subsys/ipc/openamp/Kconfig.sysbuild
+++ b/samples/subsys/ipc/openamp/Kconfig.sysbuild
@@ -1,4 +1,4 @@
-# Copyright 2022-2023 NXP
+# Copyright 2022-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 
@@ -13,3 +13,6 @@ string
 	default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk"
 	default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk"
 	default "mimxrt1170_evkb/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evkb"
+	default "frdm_mcxn947/mcxn947/cpu1" if $(BOARD) = "frdm_mcxn947"
+	default "mcx_n9xx_evk/mcxn947/cpu1" if $(BOARD) = "mcx_n9xx_evk"
+	default "mimxrt1180_evk/mimxrt1189/cm7" if $(BOARD) = "mimxrt1180_evk"
diff --git a/samples/subsys/ipc/openamp/README.rst b/samples/subsys/ipc/openamp/README.rst
index a75ef69017d..9f3416ade7f 100644
--- a/samples/subsys/ipc/openamp/README.rst
+++ b/samples/subsys/ipc/openamp/README.rst
@@ -57,6 +57,15 @@ Building the application for mimxrt1170_evk_cm7
    :goals: debug
    :west-args: --sysbuild
 
+Building the application for frdm_mcxn947/mcxn947/cpu0
+******************************************************
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/subsys/ipc/openamp
+   :board: frdm_mcxn947/mcxn947/cpu0
+   :goals: debug
+   :west-args: --sysbuild
+
 Open a serial terminal (minicom, putty, etc.) and connect the board with the
 following settings:
 
diff --git a/samples/subsys/ipc/openamp/boards/frdm_mcxn947_mcxn947_cpu0.conf b/samples/subsys/ipc/openamp/boards/frdm_mcxn947_mcxn947_cpu0.conf
new file mode 100644
index 00000000000..7e6904d56d5
--- /dev/null
+++ b/samples/subsys/ipc/openamp/boards/frdm_mcxn947_mcxn947_cpu0.conf
@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/subsys/ipc/openamp/boards/frdm_mcxn947_mcxn947_cpu0.overlay b/samples/subsys/ipc/openamp/boards/frdm_mcxn947_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..f2436532b8c
--- /dev/null
+++ b/samples/subsys/ipc/openamp/boards/frdm_mcxn947_mcxn947_cpu0.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		/*
+		 * shared memory reserved for the inter-processor communication
+		 */
+
+		zephyr,ipc_shm = &sramh;
+		zephyr,ipc = &mailbox0;
+	};
+
+	/* Delete MBOX Driver node */
+	/delete-node/ mbox@b2000;
+	soc {
+		mailbox0:mailbox@400b2000 {
+			compatible = "nxp,lpc-mailbox";
+			reg = <0x400b2000 0xEC>;
+			interrupts = <54 0>;
+			resets = <&reset NXP_SYSCON_RESET(0, 26)>;
+			status = "okay";
+		};
+	};
+};
diff --git a/samples/subsys/ipc/openamp/boards/mcx_n9xx_evk_mcxn947_cpu0.conf b/samples/subsys/ipc/openamp/boards/mcx_n9xx_evk_mcxn947_cpu0.conf
new file mode 100644
index 00000000000..7e6904d56d5
--- /dev/null
+++ b/samples/subsys/ipc/openamp/boards/mcx_n9xx_evk_mcxn947_cpu0.conf
@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/subsys/ipc/openamp/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/samples/subsys/ipc/openamp/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..f2436532b8c
--- /dev/null
+++ b/samples/subsys/ipc/openamp/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		/*
+		 * shared memory reserved for the inter-processor communication
+		 */
+
+		zephyr,ipc_shm = &sramh;
+		zephyr,ipc = &mailbox0;
+	};
+
+	/* Delete MBOX Driver node */
+	/delete-node/ mbox@b2000;
+	soc {
+		mailbox0:mailbox@400b2000 {
+			compatible = "nxp,lpc-mailbox";
+			reg = <0x400b2000 0xEC>;
+			interrupts = <54 0>;
+			resets = <&reset NXP_SYSCON_RESET(0, 26)>;
+			status = "okay";
+		};
+	};
+};
diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7.conf
similarity index 100%
rename from samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf
rename to samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7.conf
diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
similarity index 100%
rename from samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
rename to samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf
deleted file mode 100644
index 630a1933d62..00000000000
--- a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_INCLUDE_REMOTE_DIR=y
-CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay
deleted file mode 100644
index 7facea692cb..00000000000
--- a/samples/subsys/ipc/openamp/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (c) 2022 NXP
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
-
-/ {
-	chosen {
-		zephyr,ipc_shm = &ocram2_overlay;
-	};
-
-	/* OpenAMP fails with full 512K OCRAM2 memory region as shared memory.
-	 * Define a subset of the OCRAM2 region for demo to use
-	 * Note that shared memory must have specific MPU attributes set.
-	 */
-	ocram2_overlay: memory@202c0000{
-		compatible = "zephyr,memory-region", "mmio-sram";
-		reg = <0x202c0000 DT_SIZE_K(16)>;
-		zephyr,memory-region="OCRAM2_OVERLAY";
-		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
-	};
-};
diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1180_evk_mimxrt1189_cm33.conf b/samples/subsys/ipc/openamp/boards/mimxrt1180_evk_mimxrt1189_cm33.conf
new file mode 100644
index 00000000000..b57d6b0281a
--- /dev/null
+++ b/samples/subsys/ipc/openamp/boards/mimxrt1180_evk_mimxrt1189_cm33.conf
@@ -0,0 +1,5 @@
+CONFIG_SECOND_CORE_MCUX=y
+CONFIG_INCLUDE_REMOTE_DIR=y
+CONFIG_IPM=y
+CONFIG_IPM_MBOX=y
+CONFIG_MBOX=y
diff --git a/samples/subsys/ipc/openamp/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay b/samples/subsys/ipc/openamp/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
new file mode 100644
index 00000000000..582c4271c5d
--- /dev/null
+++ b/samples/subsys/ipc/openamp/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/ipc_service/static_vrings.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	chosen {
+		/*
+		 * shared memory reserved for the inter-processor communication
+		 */
+
+		zephyr,ipc_shm = &ocram2_sh_mem;
+		zephyr,ipc = &mailbox_a;
+	};
+
+	/* Define memory regions for IPC */
+	ocram2_sh_mem: memory@20500000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20500000 DT_SIZE_K(32)>;
+		zephyr,memory-region="OCRAM2_SH_MEM";
+		zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_IO))>;
+	};
+
+	mailbox_a: ipm-mbox {
+		compatible = "zephyr,mbox-ipm";
+		mboxes = <&mbox1_a 1>, <&mbox1_a 0>;
+		mbox-names = "tx", "rx";
+	};
+};
diff --git a/samples/subsys/ipc/openamp/remote/boards/frdm_mcxn947_mcxn947_cpu1.conf b/samples/subsys/ipc/openamp/remote/boards/frdm_mcxn947_mcxn947_cpu1.conf
new file mode 100644
index 00000000000..7e6904d56d5
--- /dev/null
+++ b/samples/subsys/ipc/openamp/remote/boards/frdm_mcxn947_mcxn947_cpu1.conf
@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/subsys/ipc/openamp/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay b/samples/subsys/ipc/openamp/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay
new file mode 100644
index 00000000000..f2436532b8c
--- /dev/null
+++ b/samples/subsys/ipc/openamp/remote/boards/frdm_mcxn947_mcxn947_cpu1.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		/*
+		 * shared memory reserved for the inter-processor communication
+		 */
+
+		zephyr,ipc_shm = &sramh;
+		zephyr,ipc = &mailbox0;
+	};
+
+	/* Delete MBOX Driver node */
+	/delete-node/ mbox@b2000;
+	soc {
+		mailbox0:mailbox@400b2000 {
+			compatible = "nxp,lpc-mailbox";
+			reg = <0x400b2000 0xEC>;
+			interrupts = <54 0>;
+			resets = <&reset NXP_SYSCON_RESET(0, 26)>;
+			status = "okay";
+		};
+	};
+};
diff --git a/samples/subsys/ipc/openamp/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.conf b/samples/subsys/ipc/openamp/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.conf
new file mode 100644
index 00000000000..7e6904d56d5
--- /dev/null
+++ b/samples/subsys/ipc/openamp/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.conf
@@ -0,0 +1 @@
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/samples/subsys/ipc/openamp/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay b/samples/subsys/ipc/openamp/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay
new file mode 100644
index 00000000000..f2436532b8c
--- /dev/null
+++ b/samples/subsys/ipc/openamp/remote/boards/mcx_n9xx_evk_mcxn947_cpu1.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		/*
+		 * shared memory reserved for the inter-processor communication
+		 */
+
+		zephyr,ipc_shm = &sramh;
+		zephyr,ipc = &mailbox0;
+	};
+
+	/* Delete MBOX Driver node */
+	/delete-node/ mbox@b2000;
+	soc {
+		mailbox0:mailbox@400b2000 {
+			compatible = "nxp,lpc-mailbox";
+			reg = <0x400b2000 0xEC>;
+			interrupts = <54 0>;
+			resets = <&reset NXP_SYSCON_RESET(0, 26)>;
+			status = "okay";
+		};
+	};
+};
diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.conf b/samples/subsys/ipc/openamp/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
new file mode 100644
index 00000000000..b31b3845def
--- /dev/null
+++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
@@ -0,0 +1,5 @@
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_SECOND_CORE_MCUX=y
+CONFIG_IPM=y
+CONFIG_IPM_MBOX=y
+CONFIG_MBOX=y
diff --git a/samples/subsys/ipc/openamp/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay b/samples/subsys/ipc/openamp/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
new file mode 100644
index 00000000000..80831a425fc
--- /dev/null
+++ b/samples/subsys/ipc/openamp/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/ipc_service/static_vrings.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	chosen {
+		/*
+		 * shared memory reserved for the inter-processor communication
+		 */
+
+		zephyr,ipc_shm = &ocram2_sh_mem;
+		zephyr,ipc = &mailbox_b;
+	};
+
+	/* Define memory regions for IPC */
+	ocram2_sh_mem: memory@20500000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x20500000 DT_SIZE_K(32)>;
+		zephyr,memory-region="OCRAM2_SH_MEM";
+		zephyr,memory-attr = <(DT_MEM_ARM(ATTR_MPU_IO))>;
+	};
+
+	mailbox_b: ipm-mbox {
+		compatible = "zephyr,mbox-ipm";
+		mboxes = <&mbox1_b 0>, <&mbox1_b 1>;
+		mbox-names = "tx", "rx";
+	};
+};
diff --git a/samples/subsys/ipc/openamp/remote/sample.yaml b/samples/subsys/ipc/openamp/remote/sample.yaml
index 906449cfdc3..09d67460237 100644
--- a/samples/subsys/ipc/openamp/remote/sample.yaml
+++ b/samples/subsys/ipc/openamp/remote/sample.yaml
@@ -3,9 +3,7 @@ sample:
   name: OpenAMP example integration (remote)
 tests:
   sample.ipc.openamp.remote:
-    platform_allow:
-      - lpcxpresso54114/lpc54114/m0
-      - lpcxpresso55s69/lpc55s69/cpu1
+    filter: dt_chosen_enabled("zephyr,ipc") and dt_chosen_enabled("zephyr,ipc_shm")
     integration_platforms:
       - lpcxpresso54114/lpc54114/m0
     tags: ipm
diff --git a/samples/subsys/ipc/openamp/sample.yaml b/samples/subsys/ipc/openamp/sample.yaml
index 1679d6a4697..0a2debc8690 100644
--- a/samples/subsys/ipc/openamp/sample.yaml
+++ b/samples/subsys/ipc/openamp/sample.yaml
@@ -3,11 +3,8 @@ sample:
   name: OpenAMP example integration
 tests:
   sample.ipc.openamp:
-    platform_allow:
-      - lpcxpresso54114/lpc54114/m4
-      - lpcxpresso55s69/lpc55s69/cpu0
-      - mps2/an521/cpu0
-      - v2m_musca_b1/musca_b1
+    filter: dt_chosen_enabled("zephyr,ipc") and dt_chosen_enabled("zephyr,ipc_shm")
+      and not (CONFIG_SOC_ESP32_APPCPU or CONFIG_SOC_ESP32S3_APPCPU)
     integration_platforms:
       - mps2/an521/cpu0
     tags:
diff --git a/samples/subsys/ipc/openamp_rsc_table/boards/colibri_imx7d_mcimx7d_m4.conf b/samples/subsys/ipc/openamp_rsc_table/boards/colibri_imx7d_mcimx7d_m4.conf
index 1933f35d626..f1ca31a8d94 100644
--- a/samples/subsys/ipc/openamp_rsc_table/boards/colibri_imx7d_mcimx7d_m4.conf
+++ b/samples/subsys/ipc/openamp_rsc_table/boards/colibri_imx7d_mcimx7d_m4.conf
@@ -1,11 +1,7 @@
-CONFIG_IPM=y
 CONFIG_IPM_IMX_MAX_DATA_SIZE_4=y
 CONFIG_OPENAMP_WITH_DCACHE=y
 CONFIG_SOC_RESET_HOOK=n
-CONFIG_OPENAMP=y
 CONFIG_OPENAMP_RSC_TABLE_NUM_RPMSG_BUFF=32
-CONFIG_OPENAMP_RSC_TABLE=y
-CONFIG_OPENAMP_MASTER=n
 
 
 CONFIG_ROMSTART_RELOCATION_ROM=y
diff --git a/samples/subsys/ipc/openamp_rsc_table/boards/imx95_evk_mimx9596_m7.conf b/samples/subsys/ipc/openamp_rsc_table/boards/imx95_evk_mimx9596_m7.conf
new file mode 100644
index 00000000000..69b5f1215d5
--- /dev/null
+++ b/samples/subsys/ipc/openamp_rsc_table/boards/imx95_evk_mimx9596_m7.conf
@@ -0,0 +1,12 @@
+CONFIG_CLOCK_CONTROL=y
+CONFIG_LOG=y
+CONFIG_CONSOLE=y
+CONFIG_OPENAMP_WITH_DCACHE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_ARM_SCMI=y
+CONFIG_IPM_MBOX=y
+CONFIG_MBOX_NXP_IMX_MU=y
+CONFIG_MBOX_INIT_PRIORITY=0
+CONFIG_LOG_MODE_MINIMAL=y
+CONFIG_LOG_DEFAULT_LEVEL=0
+CONFIG_OPENAMP_COPY_RSC_TABLE=y
diff --git a/samples/subsys/ipc/openamp_rsc_table/boards/imx95_evk_mimx9596_m7.overlay b/samples/subsys/ipc/openamp_rsc_table/boards/imx95_evk_mimx9596_m7.overlay
new file mode 100644
index 00000000000..471887b9452
--- /dev/null
+++ b/samples/subsys/ipc/openamp_rsc_table/boards/imx95_evk_mimx9596_m7.overlay
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		/*
+		 * shared memory reserved for the inter-processor communication
+		 */
+		zephyr,ipc_shm = &shmem;
+		zephyr,ipc_rsc_table = &rsc_table;
+		zephyr,ipc = &mailbox0;
+	};
+
+	shmem: memory@88000000 {
+		compatible = "mmio-sram";
+		reg = <0x88000000 0x500000>;
+	};
+
+	rsc_table: memory@88220000 {
+		compatible = "mmio-sram";
+		reg = <0x88220000 0x100>;
+	};
+
+	mailbox0: mailbox {
+		compatible = "zephyr,mbox-ipm";
+		mboxes = <&mu7 1>, <&mu7 1>;
+		mbox-names = "tx", "rx";
+		status = "okay";
+	};
+};
+
+&mu7 {
+	status = "okay";
+};
diff --git a/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c b/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c
index a28e017e9be..ef8e2c47bf5 100644
--- a/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c
+++ b/samples/subsys/ipc/openamp_rsc_table/src/main_remote.c
@@ -23,7 +23,7 @@
 #endif
 
 #include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(openamp_rsc_table, LOG_LEVEL_DBG);
+LOG_MODULE_REGISTER(openamp_rsc_table);
 
 #define SHM_DEVICE_NAME	"shm"
 
@@ -133,7 +133,7 @@ int mailbox_notify(void *priv, uint32_t id)
 	ARG_UNUSED(priv);
 
 	LOG_DBG("%s: msg received", __func__);
-	ipm_send(ipm_handle, 0, id, NULL, 0);
+	ipm_send(ipm_handle, 0, id, &id, 4);
 
 	return 0;
 }
diff --git a/samples/subsys/llext/modules/CMakeLists.txt b/samples/subsys/llext/modules/CMakeLists.txt
index 9e5f0e427a5..5c90a655683 100644
--- a/samples/subsys/llext/modules/CMakeLists.txt
+++ b/samples/subsys/llext/modules/CMakeLists.txt
@@ -11,7 +11,7 @@ if(CONFIG_HELLO_WORLD_MODE STREQUAL "m")
 
   set(ext_name hello_world)
   set(ext_src src/${ext_name}_ext.c)
-  set(ext_bin ${ZEPHYR_BINARY_DIR}/${ext_name}.llext)
+  set(ext_bin ${PROJECT_BINARY_DIR}/llext/${ext_name}.llext)
   set(ext_inc ${ZEPHYR_BINARY_DIR}/include/generated/${ext_name}_ext.inc)
   add_llext_target(${ext_name}_ext
     OUTPUT  ${ext_bin}
diff --git a/samples/subsys/llext/shell_loader/CMakeLists.txt b/samples/subsys/llext/shell_loader/CMakeLists.txt
index a9d5d832334..c6af8da1bff 100644
--- a/samples/subsys/llext/shell_loader/CMakeLists.txt
+++ b/samples/subsys/llext/shell_loader/CMakeLists.txt
@@ -7,3 +7,11 @@ project(fs_shell)
 
 FILE(GLOB app_sources src/*.c)
 target_sources(app PRIVATE ${app_sources})
+
+# Add a target for building the extension code
+set(ext_src ${PROJECT_SOURCE_DIR}/hello_world.c)
+set(ext_bin ${PROJECT_BINARY_DIR}/hello_world.llext)
+add_llext_target(hello_world_ext
+	OUTPUT  ${ext_bin}
+	SOURCES ${ext_src}
+)
diff --git a/samples/subsys/llext/shell_loader/README.rst b/samples/subsys/llext/shell_loader/README.rst
index 681a9487ced..3d7e1840b28 100644
--- a/samples/subsys/llext/shell_loader/README.rst
+++ b/samples/subsys/llext/shell_loader/README.rst
@@ -13,55 +13,64 @@ ability to manage loadable code extensions in the shell.
 Requirements
 ************
 
-A board with a supported llext architecture and shell capable console.
+A board with a supported LLEXT architecture and shell capable console. The
+following example uses an ARMv7 CPU, but the same instructions can be adapted
+to any LLEXT-supported target.
 
 Building
 ********
 
+The following command will build the main shell application:
+
 .. zephyr-app-commands::
    :zephyr-app: samples/subsys/llext/shell_loader
    :board: robokit1
    :goals: build
    :compact:
 
-.. note:: You may need to disable memory protection for the sample to work (e.g. CONFIG_ARM_MPU=n).
+.. note::
 
-Running
-*******
+   You may need to disable memory protection for the sample to work (e.g.
+   ``CONFIG_ARM_MPU=n``). See the full list of similar flags in
+   :zephyr_file:`tests/subsys/llext/no_mem_protection.conf`.
 
-Once the board has booted, you will be presented with a shell prompt.
-All the llext system related commands are available as sub-commands of llext
-which can be seen with llext help
+This sample also includes the source for a very basic extension,
+:zephyr_file:`samples/subsys/llext/shell_loader/hello_world.c`, which can be
+used to test the LLEXT features.
+
+It can be compiled to :file:`build/hello_world.llext` using the Zephyr build
+system like this:
 
 .. code-block:: console
 
-  uart:~$ llext help
-  llext - Loadable extension commands
-  Subcommands:
-    list          :List loaded extensions and their size in memory
-    load_hex      :Load an elf file encoded in hex directly from the shell input.
-                   Syntax:
-                   <ext_name> <ext_hex_string>
-    unload        :Unload an extension by name. Syntax:
-                   <ext_name>
-    list_symbols  :List extension symbols. Syntax:
-                   <ext_name>
-    call_fn       :Call extension function with prototype void fn(void). Syntax:
-                   <ext_name> <function_name>
+   $ ninja -C build -vvv hello_world_ext
+
+On a host machine with the Zephyr SDK and the ``arm-zephyr-eabi`` toolchain in
+``PATH``, you can also obtain the same result directly with ``gcc``:
+
+.. code-block:: console
+
+   $ arm-zephyr-eabi-gcc -mlong-calls -mthumb -c -o build/hello_world.llext samples/subsys/llext/shell/hello_world.c
+
+.. note::
 
-A hello world C file can be found in tests/subsys/llext/hello_world/hello_world.c
+   LLEXT by default only imports symbols that have been explicitly exported by
+   the extension via the :c:macro:`EXPORT_SYMBOL` macro. Compiling with this
+   macro requires using the full Zephyr build system, or at least the
+   :ref:`LLEXT EDK <llext_build_edk>`.
 
-This can be built into a relocatable elf usable on arm v7 platforms. It can be
-inspected with some binutils to see symbols, sections, and relocations.
-Then using additional tools converted to a hex string usable by the llext
-load_hex shell command.
+   To avoid this complexity, this sample configures Zephyr to use all global
+   symbols defined in the extension ELF file via the Kconfig option
+   :kconfig:option:`CONFIG_LLEXT_IMPORT_ALL_GLOBALS`. This is not recommended
+   for large extensions as the memory usage increases significantly.
 
-On a host machine with the zephyr sdk setup and the arm toolchain in PATH
+The compiled extension can be inspected with the usual binutils utilities to
+see symbols, sections, and relocations. Then, using additional tools, converted
+to a hex string usable by the ``llext load_hex`` shell command:
 
 .. code-block:: console
 
-  $ arm-zephyr-eabi-gcc -mlong-calls -mthumb -c -o hello_world.elf tests/subsys/llext/hello_world/hello_world.c
-  $ arm-zephyr-eabi-objdump -r -d -x hello_world.elf
+  $ arm-zephyr-eabi-objdump -r -d -x build/hello_world.llext
 
 	hello_world.elf:     file format elf32-littlearm
 	hello_world.elf
@@ -128,9 +137,40 @@ On a host machine with the zephyr sdk setup and the arm toolchain in PATH
 	  34:	4718      	bx	r3
 	  36:	46c0      	nop			; (mov r8, r8)
 
-  $ xxd -p hello_world.elf | tr -d '\n'
+  $ xxd -p build/hello_world.llext | tr -d '\n'
+  7f454c4601010100000000000000000001002800010000000000000000000000680200000000000534000000000028000b000a0080b500af084b1800084b00f013f82a22074b11001800054b00f00cf8c046bd4680bc01bc0047c0460400000000000000140000001847c0462a00000068656c6c6f20776f726c640a0000000041206e756d62657220697320256c750a00004743433a20285a65706879722053444b20302e31362e31292031322e322e30004129000000616561626900011f000000053454000602080109011204140115011703180119011a011e06000000000000000000000000000000000100000000000000000000000400f1ff000000000000000000000000030001000000000000000000000000000300030000000000000000000000000003000400000000000000000000000000030005000f00000000000000000000000000050012000000000000000400000001000500190000000000000000000000000001000f0000002800000000000000000001001900000034000000000000000000010000000000000000000000000003000600000000000000000000000000030007001c000000010000003400000012000100280000000000000000000000100000000068656c6c6f5f776f726c642e63002464006e756d6265720024740068656c6c6f5f776f726c64007072696e746b000028000000020500002c000000020e00003000000002050000002e73796d746162002e737472746162002e7368737472746162002e72656c2e74657874002e64617461002e627373002e726f64617461002e636f6d6d656e74002e41524d2e6174747269627574657300000000000000000000000000000000000000000000000000000000000000000000000000000000000000001f0000000100000006000000000000003400000038000000000000000000000004000000000000001b000000090000004000000000000000fc0100001800000008000000010000000400000008000000250000000100000003000000000000006c00000000000000000000000000000001000000000000002b0000000800000003000000000000006c0000000000000000000000000000000100000000000000300000000100000002000000000000006c00000025000000000000000000000004000000000000003800000001000000300000000000000091000000210000000000000000000000010000000100000041000000030000700000000000000000b20000002a0000000000000000000000010000000000000001000000020000000000000000000000dc000000f0000000090000000d000000040000001000000009000000030000000000000000000000cc0100002f0000000000000000000000010000000000000011000000030000000000000000000000140200005100000000000000000000000100000000000000
 
-The resulting hex string can be used to load the extension.
+In this sample there are 3 absolute (``R_ARM_ABS32``) relocations, 2 of which
+are meant to hold addresses into the ``.rodata`` sections where the strings are
+located. A third is an address of where the ``printk`` function (symbol) can be
+found. At load time LLEXT replaces the values in the ``.text`` section with
+real memory addresses so that ``printk`` works as expected with the strings
+included in the hello world sample.
+
+Running
+*******
+
+Once the board has booted, you will be presented with a shell prompt.
+All the LLEXT system related commands are available as sub-commands of
+``llext``, and can be seen with ``llext help``:
+
+.. code-block:: console
+
+  uart:~$ llext help
+  llext - Loadable extension commands
+  Subcommands:
+    list          :List loaded extensions and their size in memory
+    load_hex      :Load an elf file encoded in hex directly from the shell input.
+                   Syntax:
+                   <ext_name> <ext_hex_string>
+    unload        :Unload an extension by name. Syntax:
+                   <ext_name>
+    list_symbols  :List extension symbols. Syntax:
+                   <ext_name>
+    call_fn       :Call extension function with prototype void fn(void). Syntax:
+                   <ext_name> <function_name>
+
+The hex string generated above can be used to load the extension:
 
 .. code-block:: console
 
@@ -144,6 +184,3 @@ run (``call_fn``).
 
   uart:~$ llext call_fn hello_world hello_world
   hello world
-  A number is 42
-
-In this sample there are 3 absolute (R_ARM_ABS32) relocations, 2 of which are meant to hold addresses into the .rodata sections where the strings are located. A third is an address of where the printk function (symbol) can be found. At load time llext replaces the values in the .text section with real memory addresses so that printk works as expected with the strings included in the hello world sample.
diff --git a/samples/subsys/llext/shell_loader/hello_world.c b/samples/subsys/llext/shell_loader/hello_world.c
new file mode 100644
index 00000000000..8469e9b2727
--- /dev/null
+++ b/samples/subsys/llext/shell_loader/hello_world.c
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * This very simple hello world C code can be used while learning about llext.
+ */
+
+extern void printk(const char *fmt, ...);
+
+void hello_world(void)
+{
+	printk("hello world\n");
+}
diff --git a/samples/subsys/llext/shell_loader/prj.conf b/samples/subsys/llext/shell_loader/prj.conf
index 0e0d38fdcf4..923560ce0f0 100644
--- a/samples/subsys/llext/shell_loader/prj.conf
+++ b/samples/subsys/llext/shell_loader/prj.conf
@@ -8,5 +8,6 @@ CONFIG_SHELL_STACK_SIZE=4096
 
 CONFIG_LLEXT=y
 CONFIG_LLEXT_LOG_LEVEL_DBG=y
+CONFIG_LLEXT_IMPORT_ALL_GLOBALS=y
 CONFIG_LLEXT_HEAP_SIZE=8
 CONFIG_LLEXT_SHELL=y
diff --git a/samples/subsys/llext/shell_loader/sample.yaml b/samples/subsys/llext/shell_loader/sample.yaml
index f1d7b6907d9..a9e76eed348 100644
--- a/samples/subsys/llext/shell_loader/sample.yaml
+++ b/samples/subsys/llext/shell_loader/sample.yaml
@@ -6,6 +6,7 @@ common:
     - arm
     - xtensa
   filter: not CONFIG_MPU and not CONFIG_MMU and not CONFIG_SOC_SERIES_S32ZE
+    and not CONFIG_SOC_SERIES_RZA2M
   platform_exclude:
     # platforms with active issues
     - apollo4p_evb            # See #73443
@@ -21,6 +22,7 @@ common:
     - qemu_arc/qemu_arc_hs6x
     - qemu_cortex_m0
     - qemu_xtensa/dc233c/mmu
+    - rza2m_evk
 
 sample:
   description: Loadable extensions with shell sample
diff --git a/samples/subsys/logging/ble_backend/README.rst b/samples/subsys/logging/ble_backend/README.rst
index 7e229b6dea0..add2d90dd22 100644
--- a/samples/subsys/logging/ble_backend/README.rst
+++ b/samples/subsys/logging/ble_backend/README.rst
@@ -1,24 +1,24 @@
 .. zephyr:code-sample:: logging-ble-backend
-   :name: BLE logging backend
+   :name: Bluetooth logging backend
    :relevant-api: log_api log_backend bt_gatt
 
-   Send log messages over BLE using the BLE logging backend.
+   Send log messages over Bluetooth using the Bluetooth logging backend.
 
 Overview
 ********
 
-Sample that demonstrates how to setup and use the BLE Logging backend. The
-BLE Logger uses the NRF Connect SDK NUS service as UUID to make it compatible
-with already existing apps to debug BLE connections over UART.
+Sample that demonstrates how to setup and use the Bluetooth Logging backend. The
+Bluetooth Logger uses the NRF Connect SDK NUS service as UUID to make it compatible
+with already existing apps to debug Bluetooth connections over UART.
 
-The notification size of the ble backend buffer is dependent on the
+The notification size of the Bluetooth backend buffer is dependent on the
 transmission size of the mtu set with :kconfig:option:`CONFIG_BT_L2CAP_TX_MTU`. Be sure
-to change this configuration to increase the logger throughput over BLE.
+to change this configuration to increase the logger throughput over Bluetooth.
 
 Requirements
 ************
 
-* A board with BLE support
+* A board with Bluetooth LE support
 
 Building and Running
 ********************
@@ -26,5 +26,5 @@ Building and Running
 This sample can be found under :zephyr_file:`samples/subsys/logging/ble_backend` in the
 Zephyr tree.
 
-The BLE logger can be tested with the NRF Toolbox app or any similar app that can connect over
-BLE and detect the NRF NUS UUID service.
+The Bluetooth logger can be tested with the NRF Toolbox app or any similar app that can connect over
+Bluetooth and detect the NRF NUS UUID service.
diff --git a/samples/subsys/logging/ble_backend/sample.yaml b/samples/subsys/logging/ble_backend/sample.yaml
index 5a025aa80f2..6c3ec10a6b5 100644
--- a/samples/subsys/logging/ble_backend/sample.yaml
+++ b/samples/subsys/logging/ble_backend/sample.yaml
@@ -1,6 +1,6 @@
 sample:
-  description: A simple application that demonstrates the use of the logging ble backend.
-  name: logger backend ble
+  description: A simple application that demonstrates the use of the logging Bluetooth backend.
+  name: logger backend Bluetooth
 tests:
   sample.logging.ble_backend.nrf52833:
     harness: bluetooth
diff --git a/samples/subsys/logging/ble_backend/src/main.c b/samples/subsys/logging/ble_backend/src/main.c
index 249e582a0e8..87a5fd56987 100644
--- a/samples/subsys/logging/ble_backend/src/main.c
+++ b/samples/subsys/logging/ble_backend/src/main.c
@@ -73,9 +73,9 @@ void backend_ble_hook(bool status, void *ctx)
 	ARG_UNUSED(ctx);
 
 	if (status) {
-		LOG_INF("BLE Logger Backend enabled.");
+		LOG_INF("Bluetooth Logger Backend enabled.");
 	} else {
-		LOG_INF("BLE Logger Backend disabled.");
+		LOG_INF("Bluetooth Logger Backend disabled.");
 	}
 }
 
@@ -84,7 +84,7 @@ int main(void)
 {
 	int err;
 
-	LOG_INF("BLE LOG Demo");
+	LOG_INF("Bluetooth LOG Demo");
 	logger_backend_ble_set_hook(backend_ble_hook, NULL);
 	err = bt_enable(NULL);
 	if (err) {
diff --git a/samples/subsys/lorawan/class_a/README.rst b/samples/subsys/lorawan/class_a/README.rst
index 22d9b8f3a48..4d8c421209a 100644
--- a/samples/subsys/lorawan/class_a/README.rst
+++ b/samples/subsys/lorawan/class_a/README.rst
@@ -25,3 +25,16 @@ The following commands build and flash the sample.
    :board: nucleo_wl55jc
    :goals: build flash
    :compact:
+
+Important Notes for Multiple Runs
+*********************************
+
+By default, this example will only succeed the first time it is run. On subsequent join attempts, the LoRaWAN network server may reject the join request due to a hardcoded ``dev_nonce`` value. According to the LoRaWAN specification, ``dev_nonce`` must increment for every new connection attempt.
+
+To run this sample multiple times, choose one of the following options:
+
+1. **Manually Increment ``dev_nonce``:**
+   Modify the sample code to increment ``join_cfg.otaa.dev_nonce`` before each connection attempt and ensure it is preserved across reboots.
+
+2. **Built-in Zephyr Settings Implementation:**
+   Enable :kconfig:option:`CONFIG_LORAWAN_NVM_SETTINGS` in the Kconfig. This allows proper storage and reuse of configuration settings, including the ``dev_nonce``, across multiple runs.
diff --git a/samples/subsys/lorawan/fuota/src/main.c b/samples/subsys/lorawan/fuota/src/main.c
index ef6f8680cea..1cfb5ec2fba 100644
--- a/samples/subsys/lorawan/fuota/src/main.c
+++ b/samples/subsys/lorawan/fuota/src/main.c
@@ -41,6 +41,18 @@ static void datarate_changed(enum lorawan_datarate dr)
 	LOG_INF("New Datarate: DR %d, Max Payload %d", dr, max_size);
 }
 
+int descriptor_cb(uint32_t descriptor)
+{
+	/*
+	 * In an actual application the firmware may be able to handle
+	 * the descriptor field
+	 */
+
+	LOG_INF("Received descriptor %u", descriptor);
+
+	return 0;
+}
+
 static void fuota_finished(void)
 {
 	LOG_INF("FUOTA finished. Reset device to apply firmware upgrade.");
@@ -114,6 +126,8 @@ int main(void)
 	 */
 	lorawan_frag_transport_run(fuota_finished);
 
+	lorawan_frag_transport_register_descriptor_callback(descriptor_cb);
+
 	/*
 	 * Regular uplinks are required to open downlink slots in class A for
 	 * FUOTA setup by the server.
diff --git a/samples/subsys/mgmt/hawkbit/README.rst b/samples/subsys/mgmt/hawkbit/README.rst
index f4a206c32f9..7e5fa64239d 100644
--- a/samples/subsys/mgmt/hawkbit/README.rst
+++ b/samples/subsys/mgmt/hawkbit/README.rst
@@ -29,7 +29,7 @@ Caveats
   :zephyr:board:`Freedom-K64F <frdm_k64f>` MCU by default. The application should
   build and run for other platforms with support internet connection. Some
   platforms need some modification. Overlay files would be needed to support
-  BLE 6lowpan, 802.15.4 or OpenThread configurations as well as the
+  Bluetooth LE, 6lowpan, 802.15.4 or OpenThread configurations as well as the
   understanding that most other connectivity options would require an edge
   gateway of some sort (Border Router, etc).
 
diff --git a/samples/subsys/mgmt/hawkbit/sample.yaml b/samples/subsys/mgmt/hawkbit/sample.yaml
index 4a7bf0db6c7..6104df0035a 100644
--- a/samples/subsys/mgmt/hawkbit/sample.yaml
+++ b/samples/subsys/mgmt/hawkbit/sample.yaml
@@ -34,3 +34,7 @@ tests:
   sample.net.hawkbit.set_settings_runtime:
     extra_configs:
       - CONFIG_HAWKBIT_SET_SETTINGS_RUNTIME=y
+  sample.net.hawkbit.save_progress:
+    extra_configs:
+      - CONFIG_HAWKBIT_SAVE_PROGRESS=y
+      - CONFIG_STREAM_FLASH_PROGRESS=y
diff --git a/samples/subsys/mgmt/mcumgr/smp_svr/README.rst b/samples/subsys/mgmt/mcumgr/smp_svr/README.rst
index 8d8830903b9..755f880ab6c 100644
--- a/samples/subsys/mgmt/mcumgr/smp_svr/README.rst
+++ b/samples/subsys/mgmt/mcumgr/smp_svr/README.rst
@@ -12,7 +12,7 @@ This sample application implements a Simple Management Protocol (SMP) server.
 SMP is a basic transfer encoding for use with the MCUmgr management protocol.
 For more information about MCUmgr and SMP, please see :ref:`device_mgmt`.
 
-This sample application supports the following mcumgr transports by default:
+This sample application supports the following MCUmgr transports by default:
 
     * Shell
     * Bluetooth
@@ -41,7 +41,8 @@ Use of a tool
 
 To interact remotely with the management subsystem on a device, a tool is required to interact with
 it. There are various tools available which are listed on the :ref:`mcumgr_tools_libraries` page
-of the Management subsystem documentation.
+of the Management subsystem documentation which can be used as a client for a Zephyr MCUmgr SMP
+server.
 
 Building a BLE Controller
 =========================
@@ -54,30 +55,13 @@ Bluetooth Low Energy (BLE) and do not have a built-in or pluggable BLE radio,
 you can build one and use it following the instructions in
 :ref:`bluetooth-hci-uart-bluez`.
 
-Building and flashing MCUboot
-*****************************
-
-The below steps describe how to build and run the MCUboot bootloader.
-Detailed instructions can be found in the :ref:`mcuboot` documentation page.
-
-The Zephyr port of MCUboot is essentially a normal Zephyr application, which means that
-it can be built and flashed like normal using ``west``, like so:
-
-.. code-block:: console
-
-   west build -b <board> -d build_mcuboot bootloader/mcuboot/boot/zephyr
-   west flash -d build_mcuboot
-
-Substitute <board> for one of the boards supported by the sample, see
-:file:`sample.yaml`.
-
 .. _smp_svr_sample_build:
 
 Building the sample application
 *******************************
 
-The below steps describe how to build and run the ``smp_svr`` sample in
-Zephyr. The ``smp_svr`` sample comes in different flavours.
+The below steps describe how to build and run the ``smp_svr`` sample in Zephyr with ``MCUboot``
+included. The ``smp_svr`` sample comes in different flavours.
 
 .. tabs::
 
@@ -85,50 +69,53 @@ Zephyr. The ``smp_svr`` sample comes in different flavours.
 
       To build the bluetooth sample:
 
-      .. code-block:: console
-
-         west build \
-            -b nrf52dk/nrf52832 \
-            samples/subsys/mgmt/mcumgr/smp_svr \
-            -- \
-            -DEXTRA_CONF_FILE=overlay-bt.conf
+      .. zephyr-app-commands::
+         :tool: west
+         :zephyr-app: samples/subsys/mgmt/mcumgr/smp_svr
+         :board: nrf52dk/nrf52832
+         :goals: build
+         :west-args: --sysbuild
+         :gen-args: -DEXTRA_CONF_FILE="overlay-bt.conf"
+         :compact:
 
    .. group-tab:: Serial
 
       To build the serial sample with file-system and shell management support:
 
-      .. code-block:: console
-
-         west build \
-            -b frdm_k64f \
-            samples/subsys/mgmt/mcumgr/smp_svr \
-            -- \
-            -DEXTRA_CONF_FILE='overlay-serial.conf;overlay-fs.conf;overlay-shell-mgmt.conf'
+      .. zephyr-app-commands::
+         :tool: west
+         :zephyr-app: samples/subsys/mgmt/mcumgr/smp_svr
+         :board: frdm_k64f
+         :goals: build
+         :west-args: --sysbuild
+         :gen-args: -DEXTRA_CONF_FILE="overlay-serial.conf;overlay-fs.conf;overlay-shell-mgmt.conf"
+         :compact:
 
    .. group-tab:: USB CDC_ACM
 
       To build the serial sample with USB CDC_ACM backend:
 
-      .. code-block:: console
-
-         west build \
-            -b nrf52840dk/nrf52840 \
-            samples/subsys/mgmt/mcumgr/smp_svr \
-            -- \
-            -DEXTRA_CONF_FILE=overlay-cdc.conf \
-            -DDTC_OVERLAY_FILE=usb.overlay
+      .. zephyr-app-commands::
+         :tool: west
+         :zephyr-app: samples/subsys/mgmt/mcumgr/smp_svr
+         :board: nrf52840dk/nrf52840
+         :goals: build
+         :west-args: --sysbuild
+         :gen-args: -DEXTRA_CONF_FILE="overlay-cdc.conf" -DEXTRA_DTC_OVERLAY_FILE="usb.overlay"
+         :compact:
 
    .. group-tab:: Shell
 
       To build the shell sample:
 
-      .. code-block:: console
-
-         west build \
-            -b frdm_k64f \
-            samples/subsys/mgmt/mcumgr/smp_svr \
-            -- \
-            -DEXTRA_CONF_FILE='overlay-shell.conf'
+      .. zephyr-app-commands::
+         :tool: west
+         :zephyr-app: samples/subsys/mgmt/mcumgr/smp_svr
+         :board: frdm_k64f
+         :goals: build
+         :west-args: --sysbuild
+         :gen-args: -DEXTRA_CONF_FILE="overlay-shell.conf"
+         :compact:
 
    .. group-tab:: UDP
 
@@ -138,49 +125,24 @@ Zephyr. The ``smp_svr`` sample comes in different flavours.
 
       To build the UDP sample:
 
-      .. code-block:: console
-
-         west build \
-            -b frdm_k64f \
-            samples/subsys/mgmt/mcumgr/smp_svr \
-            -- \
-            -DEXTRA_CONF_FILE=overlay-udp.conf
-
-.. _smp_svr_sample_sign:
-
-Signing the sample image
-************************
-
-A key feature of MCUboot is that images must be signed before they can be successfully
-uploaded and run on a target. To sign images, the MCUboot tool :file:`imgtool` can be used.
-
-To sign the sample image built in the previous step:
-
-.. code-block:: console
-
-    west sign -t imgtool -- --key bootloader/mcuboot/root-rsa-2048.pem
-
-The above command creates an image file called :file:`zephyr.signed.bin` in the
-build directory.
-
-For more information on image signing and ``west sign``, see the :ref:`west-sign`
-documentation.
+      .. zephyr-app-commands::
+         :tool: west
+         :zephyr-app: samples/subsys/mgmt/mcumgr/smp_svr
+         :board: frdm_k64f
+         :goals: build
+         :west-args: --sysbuild
+         :gen-args: -DEXTRA_CONF_FILE="overlay-udp.conf"
+         :compact:
 
 Flashing the sample image
 *************************
 
-Upload the :file:`zephyr.signed.bin` file from the previous to image slot-0 of your
-board.  See :ref:`flash_map_api` for details on flash partitioning.
-
-To upload the initial image file to an empty slot-0, use ``west flash`` like normal.
-``west flash`` will automatically detect slot-0 address and confirm the image.
+The original application will be built for slot-0, see :ref:`flash_map_api` for details on flash
+partitioning. Flash both MCUboot and the sample application:
 
 .. code-block:: console
 
-    west flash --bin-file build/zephyr/zephyr.signed.bin
-
-The *signed* image file needs to be used specifically, otherwise the non-signed version
-will be used and the image won't be runnable.
+    west flash
 
 Sample image: hello world!
 ==========================
@@ -204,24 +166,23 @@ instructions on :ref:`nordic_segger_msd` to disable MSD support.
 Device Firmware Upgrade (DFU)
 *****************************
 
-Now that the SMP server is running on your board and you are able to communicate
-with it using :file:`mcumgr`, you might want to test what is commonly called
-"OTA DFU", or Over-The-Air Device Firmware Upgrade. This works for both BT and UDP.
+Now that the SMP server is running on your board and you are able to communicate with it using a
+client, you might want to test what is commonly called "OTA DFU", or Over-The-Air Device Firmware
+Upgrade. This works for both BT and UDP.
 
 The general sequence of a DFU process is as follows:
 
-* Build an MCUboot enabled application, see :ref:`smp_svr_sample_build`
-* Sign the application image, see :ref:`smp_svr_sample_sign`
-* Upload the signed image using :file:`mcumgr`
-* Listing the images on the device using :file:`mcumgr`
-* Mark the uploaded image for testing using :file:`mcumgr`
-* Reset the device remotely using :file:`mcumgr`
-* Confirm the uploaded image using :file:`mcumgr` (optional)
+* Build an MCUboot enabled application using sysbuild, see :ref:`smp_svr_sample_build`
+* Upload the signed image using an MCUmgr client
+* Listing the images on the device using an MCUmgr client
+* Mark the uploaded image for testing using an MCUmgr client
+* Reset the device remotely using an MCUmgr client
+* Confirm the uploaded image using an MCUmgr client (optional)
 
 Direct image upload and Image mapping to MCUboot slot
 =====================================================
 
-Currently the mcumgr supports, for direct upload, 4 target images, of which first two are mapped
+Currently MCUmgr supports, for direct upload, 4 target images, of which first two are mapped
 into MCUboot primary (slot-0) and secondary (slot-1) respectively.
 
 For clarity, here is DTS label to slot to ``<image>`` translation table:
@@ -238,6 +199,12 @@ For clarity, here is DTS label to slot to ``<image>`` translation table:
     | "image-3" |        |     3      |
     +-----------+--------+------------+
 
+.. note::
+
+   There is a slot info command that can be used to see information on all slots and get the
+   upload ``image`` ID to use to update that slot, see :ref:`mcumgr_smp_group_1_slot_info` for
+   details.
+
 Upload the signed image
 =======================
 
@@ -246,15 +213,15 @@ firmware file to upload and begin the upload.
 
 .. note::
 
-   At the beginning of the upload process, the target might start erasing
-   the image slot, taking several dozen seconds for some targets.
+   At the beginning of the upload process, the target might start erasing the image slot, taking
+   several dozen seconds for some targets.
 
 List the images
 ===============
 
-A list of images (slot-0 and slot-1) that are present can now be obtained on the remote target device using
-the tool of your choice, which should print the status and hash values of each of the images
-present.
+A list of images (slot-0 and slot-1) that are present can now be obtained on the remote target
+device using the tool of your choice, which should print the status and hash values of each of
+the images present.
 
 Test the image
 ==============
@@ -264,8 +231,35 @@ boots, see the instructions in the tool of your choice. Upon reboot, MCUBoot wil
 image.
 
 .. note::
-   There is not yet any way of getting the image hash without actually uploading the
-   image and getting the hash.
+
+   Some tools may allow for listing the hash of an image without needing to upload them.
+   ``imgtool`` can also be used to list the image hash, albeit in a C hex-array format, by using
+   the ``dumpinfo`` command on the signed update file, e.g.
+
+   .. code-block:: console
+
+       imgtool dumpinfo smp_svr/zephyr/zephyr.signed.bin
+
+       Printing content of signed image: zephyr.signed.bin
+
+       #### Image header (offset: 0x0) ############################
+       magic:              0x96f3b83d
+       ...
+       #### TLV area (offset: 0xbfa0) #############################
+       magic:     0x6907
+       area size: 0x150
+               ---------------------------------------------
+               type: SHA256 (0x10)
+               len:  0x20
+               data: 0x9b 0xa9 0x84 0x48 0xe5 0x4d 0xac 0x40
+                     0x62 0x29 0xe2 0x11 0x17 0x96 0x66 0xd9
+                     0xae 0x83 0x9a 0x37 0x71 0x00 0xfc 0xe2
+                     0xc0 0x30 0x30 0x4f 0xfc 0x40 0x58 0xaa
+               ---------------------------------------------
+       ...
+
+   The full SHA256 hash for the above output would be:
+   9ba98448e54dac406229e211179666d9ae839a377100fce2c030304ffc4058aa
 
 Reset remotely
 ==============
@@ -280,14 +274,16 @@ Confirm new image
 The new image is now loaded into slot-0, but it will be swapped back into slot-1 on the next
 reset unless the image is confirmed. Confirm the image using the tool of your choice.
 
-Note that if you try to send the very same image that is already flashed in
-slot-0 then the procedure will not complete successfully since the hash values
-for both slots will be identical.
+.. note::
+
+   If you try to send the very same image that is already flashed in slot-0 then the procedure
+   will not complete successfully since the hash values for both slots will be identical.
 
-Download file from File System
-******************************
+Download files from/upload files to file system
+***********************************************
 
-SMP server supports downloading files from File System on device via
-:file:`mcumgr`. This is useful with FS log backend, when files are stored in
-non-volatile memory. Build and flash both MCUboot and smp_svr applications and
-then use the tool of your choice to download files from the file system.
+SMP server supports downloading files from/uploading files to the on-device
+:ref:`file_system_api`, this is useful with e.g. FS log backend, when files are stored in
+non-volatile memory. Build and flash ``smp_svr`` using sysbuild and then use the tool of your
+choice to download files from the file system. The full path of the file on the device must be
+known and used.
diff --git a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml
index cc7e86e7a47..dcdd8cfc76f 100644
--- a/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml
+++ b/samples/subsys/mgmt/mcumgr/smp_svr/sample.yaml
@@ -36,6 +36,7 @@ tests:
     extra_args: EXTRA_CONF_FILE="overlay-udp.conf"
     platform_allow:
       - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
       - frdm_k64f
     integration_platforms:
       - frdm_k64f
@@ -45,6 +46,7 @@ tests:
       - DTC_OVERLAY_FILE="usb.overlay"
     platform_allow:
       - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
       - nrf52833dk/nrf52820
       - nrf52833dk/nrf52833
       - nrf52840dk/nrf52840
@@ -67,6 +69,7 @@ tests:
       - twr_ke18f
       - twr_kv58f220m
       - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
       - lpcxpresso55s06
       - lpcxpresso55s16
       - lpcxpresso55s28
@@ -126,6 +129,7 @@ tests:
       - twr_ke18f
       - twr_kv58f220m
       - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
       - lpcxpresso55s06
       - lpcxpresso55s16
       - lpcxpresso55s28
diff --git a/samples/subsys/mgmt/mcumgr/smp_svr/sysbuild/nrf52840dk_nrf52840_mcuboot_ram_load.overlay b/samples/subsys/mgmt/mcumgr/smp_svr/sysbuild/nrf52840dk_nrf52840_mcuboot_ram_load.overlay
index fbd19b0b74d..90d209ddfe8 100644
--- a/samples/subsys/mgmt/mcumgr/smp_svr/sysbuild/nrf52840dk_nrf52840_mcuboot_ram_load.overlay
+++ b/samples/subsys/mgmt/mcumgr/smp_svr/sysbuild/nrf52840dk_nrf52840_mcuboot_ram_load.overlay
@@ -1,4 +1,12 @@
+&gpregret1 {
+	/delete-node/ boot_mode@0;
+};
+
 / {
+	chosen {
+		/delete-property/ zephyr,boot-mode;
+	};
+
 	sram@2003FC00 {
 		compatible = "zephyr,memory-region", "mmio-sram";
 		reg = <0x2003FC00 DT_SIZE_K(1)>;
diff --git a/samples/subsys/mgmt/updatehub/README.rst b/samples/subsys/mgmt/updatehub/README.rst
index 733df73b267..0e973dda029 100644
--- a/samples/subsys/mgmt/updatehub/README.rst
+++ b/samples/subsys/mgmt/updatehub/README.rst
@@ -454,7 +454,7 @@ The below list of hardware have been used by UpdateHub team.
    :width: 800px
 
    :zephyr:board:`frdm_k64f`, "1, 2, 3, 4"
-   :ref:`nrf52840dk_nrf52840`, "2, 3, 4, 5, 6"
+   :zephyr:board:`nrf52840dk`, "2, 3, 4, 5, 6"
    :zephyr:board:`nucleo_f767zi`, "1, 2, 3, 4"
 
 
diff --git a/samples/subsys/nvs/Kconfig b/samples/subsys/nvs/Kconfig
new file mode 100644
index 00000000000..1caa07ef749
--- /dev/null
+++ b/samples/subsys/nvs/Kconfig
@@ -0,0 +1,28 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+mainmenu "NVS Sample Configuration"
+
+config NVS_SAMPLE_MAX_REBOOT
+	int "Maximum reboot counter value"
+	default 5
+	range 1 1000
+	help
+	  Maximum number of reboots to perform before resetting the counter.
+
+config NVS_SAMPLE_REBOOT_COUNTDOWN
+	int "Reboot countdown value (in iterations)"
+	default 5
+	range 1 60
+	help
+	  Number of countdown iterations to wait before rebooting the device.
+	  Each iteration takes NVS_SAMPLE_SLEEP_TIME milliseconds.
+
+config NVS_SAMPLE_SLEEP_TIME
+	int "Sleep time between reboot countdown iterations (in milliseconds)"
+	default 100
+	range 10 10000
+	help
+	  Duration in milliseconds to sleep between reboot countdown iterations.
+
+source "Kconfig.zephyr"
diff --git a/samples/subsys/nvs/prj.conf b/samples/subsys/nvs/prj.conf
index 17bcf7fb2e3..bbec69f5f4d 100644
--- a/samples/subsys/nvs/prj.conf
+++ b/samples/subsys/nvs/prj.conf
@@ -6,3 +6,4 @@ CONFIG_LOG_MODE_IMMEDIATE=y
 CONFIG_NVS_LOG_LEVEL_DBG=y
 CONFIG_REBOOT=y
 CONFIG_MPU_ALLOW_FLASH_WRITE=y
+CONFIG_MAIN_STACK_SIZE=2048
diff --git a/samples/subsys/nvs/src/main.c b/samples/subsys/nvs/src/main.c
index 5df97ab9c1b..222ebe0ac95 100644
--- a/samples/subsys/nvs/src/main.c
+++ b/samples/subsys/nvs/src/main.c
@@ -52,12 +52,6 @@ static struct nvs_fs fs;
 #define NVS_PARTITION_DEVICE	FIXED_PARTITION_DEVICE(NVS_PARTITION)
 #define NVS_PARTITION_OFFSET	FIXED_PARTITION_OFFSET(NVS_PARTITION)
 
-/* 1000 msec = 1 sec */
-#define SLEEP_TIME      100
-/* maximum reboot counts, make high enough to trigger sector change (buffer */
-/* rotation). */
-#define MAX_REBOOT 400
-
 #define ADDRESS_ID 1
 #define KEY_ID 2
 #define RBT_CNT_ID 3
@@ -192,11 +186,11 @@ int main(void)
 		}
 	}
 
-	cnt = 5;
+	cnt = CONFIG_NVS_SAMPLE_REBOOT_COUNTDOWN;
 	while (1) {
-		k_msleep(SLEEP_TIME);
-		if (reboot_counter < MAX_REBOOT) {
-			if (cnt == 5) {
+		k_msleep(CONFIG_NVS_SAMPLE_SLEEP_TIME);
+		if (reboot_counter < CONFIG_NVS_SAMPLE_MAX_REBOOT) {
+			if (cnt == CONFIG_NVS_SAMPLE_REBOOT_COUNTDOWN) {
 				/* print some history information about
 				 * the reboot counter
 				 * Check the counter history in flash
@@ -230,7 +224,7 @@ int main(void)
 				(void)nvs_write(
 					&fs, RBT_CNT_ID, &reboot_counter,
 					sizeof(reboot_counter));
-				if (reboot_counter == MAX_REBOOT) {
+				if (reboot_counter == CONFIG_NVS_SAMPLE_MAX_REBOOT) {
 					printk("Doing last reboot...\n");
 				}
 				sys_reboot(0);
diff --git a/samples/subsys/pm/latency/boards/native_posix.overlay b/samples/subsys/pm/latency/boards/native_posix.overlay
deleted file mode 100644
index 6a3daca3241..00000000000
--- a/samples/subsys/pm/latency/boards/native_posix.overlay
+++ /dev/null
@@ -1 +0,0 @@
-#include "native_sim.overlay"
diff --git a/samples/subsys/settings/sample.yaml b/samples/subsys/settings/sample.yaml
index 7dcf6c45720..51b050dfd4b 100644
--- a/samples/subsys/settings/sample.yaml
+++ b/samples/subsys/settings/sample.yaml
@@ -4,7 +4,7 @@ sample:
 tests:
   sample.subsys.settings:
     tags: settings
-    timeout: 10
+    timeout: 20
     filter: dt_label_with_parent_compat_enabled("storage_partition", "fixed-partitions")
     platform_exclude:
       - qemu_cortex_m0/nrf51822
diff --git a/samples/subsys/shell/fs/sample.yaml b/samples/subsys/shell/fs/sample.yaml
index afba7ddf0e2..2ac6864f719 100644
--- a/samples/subsys/shell/fs/sample.yaml
+++ b/samples/subsys/shell/fs/sample.yaml
@@ -18,7 +18,7 @@ tests:
       - s32z2xxdc2@D/s32z270/rtu0
       - s32z2xxdc2@D/s32z270/rtu1
     integration_platforms:
-      - reel_board
+      - native_sim
   sample.filesystem.shell.fuse:
     platform_allow:
       - native_sim
diff --git a/samples/subsys/shell/shell_module/sample.yaml b/samples/subsys/shell/shell_module/sample.yaml
index 46c7fbb127f..9b9e8662ccf 100644
--- a/samples/subsys/shell/shell_module/sample.yaml
+++ b/samples/subsys/shell/shell_module/sample.yaml
@@ -1,19 +1,17 @@
 sample:
   name: Shell Sample
 common:
-  filter: not CONFIG_NATIVE_LIBC
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
+  filter: not CONFIG_NATIVE_LIBC and not CONFIG_SOC_SERIES_BSIM_NRFXX
 tests:
   sample.shell.shell_module:
     filter: CONFIG_SERIAL and dt_chosen_enabled("zephyr,shell-uart")
     tags: shell
-    harness: keyboard
+    harness: shell
     min_ram: 40
     integration_platforms:
       - native_sim
-      - intel_socfpga_agilex5_socdk
+    extra_configs:
+      - arch:posix:CONFIG_UART_NATIVE_PTY_0_ON_STDINOUT=y
   sample.shell.shell_module.usb:
     depends_on: usb_device
     tags:
diff --git a/samples/subsys/shell/shell_module/shell_module.robot b/samples/subsys/shell/shell_module/shell_module.robot
index 334d040a2cc..c0675287bab 100644
--- a/samples/subsys/shell/shell_module/shell_module.robot
+++ b/samples/subsys/shell/shell_module/shell_module.robot
@@ -7,7 +7,6 @@ Resource                      ${KEYWORDS}
 Should Read Version From Shell
     # `Prepare Machine` keyword comes from $ZEPHYR_BASE/tests/robot/common.robot file, which is imported as a resource
     Prepare Machine
-    Start Emulation
     Wait For Prompt On Uart   uart:~$
     Write Line To Uart        version
     Wait For Line On Uart     Zephyr version
diff --git a/samples/subsys/shell/shell_module/src/test_module.c b/samples/subsys/shell/shell_module/src/test_module.c
index 3d9b1975188..6723629d930 100644
--- a/samples/subsys/shell/shell_module/src/test_module.c
+++ b/samples/subsys/shell/shell_module/src/test_module.c
@@ -42,5 +42,5 @@ static int sub_cmd1_handler(const struct shell *sh, size_t argc, char **argv)
 	return 0;
 }
 
-SHELL_SUBCMD_COND_ADD(1, (section_cmd, cmd1), sub_cmd1, NULL, "help for cmd2",
+SHELL_SUBCMD_COND_ADD(1, (section_cmd, cmd1), sub_cmd1, NULL, "help for sub_cmd1",
 			sub_cmd1_handler, 1, 0);
diff --git a/samples/subsys/shell/shell_module/test_shell.yml b/samples/subsys/shell/shell_module/test_shell.yml
new file mode 100644
index 00000000000..172651f7847
--- /dev/null
+++ b/samples/subsys/shell/shell_module/test_shell.yml
@@ -0,0 +1,4 @@
+- command: "kernel cycles"
+  expected: "cycles: .* hw cycles"
+- command: "kernel version"
+  expected: "Zephyr version .*"
diff --git a/samples/subsys/task_wdt/src/main.c b/samples/subsys/task_wdt/src/main.c
index 6b5202fee61..143bece9666 100644
--- a/samples/subsys/task_wdt/src/main.c
+++ b/samples/subsys/task_wdt/src/main.c
@@ -67,9 +67,11 @@ int main(void)
 
 	if (!device_is_ready(hw_wdt_dev)) {
 		printk("Hardware watchdog not ready; ignoring it.\n");
+		ret = task_wdt_init(NULL);
+	} else {
+		ret = task_wdt_init(hw_wdt_dev);
 	}
 
-	ret = task_wdt_init(hw_wdt_dev);
 	if (ret != 0) {
 		printk("task wdt init failure: %d\n", ret);
 		return 0;
diff --git a/samples/subsys/testsuite/integration/testcase.yaml b/samples/subsys/testsuite/integration/testcase.yaml
index 1cc0ad1c8ee..90bbd9bf64e 100644
--- a/samples/subsys/testsuite/integration/testcase.yaml
+++ b/samples/subsys/testsuite/integration/testcase.yaml
@@ -3,7 +3,6 @@ tests:
   sample.testing.ztest:
     build_only: true
     platform_allow:
-      - native_posix
       - native_sim
     integration_platforms:
       - native_sim
diff --git a/samples/subsys/testsuite/pytest/shell/testcase.yaml b/samples/subsys/testsuite/pytest/shell/testcase.yaml
index 86b9314f444..2e76f920865 100644
--- a/samples/subsys/testsuite/pytest/shell/testcase.yaml
+++ b/samples/subsys/testsuite/pytest/shell/testcase.yaml
@@ -1,14 +1,34 @@
+common:
+  tags:
+    - test_framework
+    - pytest
+    - shell
+  filter: CONFIG_SERIAL and not CONFIG_SMP and dt_chosen_enabled("zephyr,shell-uart")
+  extra_configs:
+    - arch:posix:CONFIG_UART_NATIVE_PTY_0_ON_STDINOUT=y
+  min_ram: 40
+  integration_platforms:
+    - native_sim
+    - qemu_cortex_m3
 tests:
   sample.pytest.shell:
-    filter: CONFIG_SERIAL and dt_chosen_enabled("zephyr,shell-uart")
-    min_ram: 40
     harness: pytest
+  sample.pytest.shell.vt100_colors_off:
+    harness: pytest
+    extra_configs:
+      - CONFIG_SHELL_VT100_COLORS=n
+  sample.harness.shell:
+    harness: shell
+    harness_config:
+      shell_commands: &kernel_commands
+        - command: "kernel cycles"
+          expected: "cycles: .* hw cycles"
+        - command: "kernel version"
+          expected: "Zephyr version .*"
+        - command: "kernel sleep 100"
+  sample.harness.shell.vt100_colors_off:
+    harness: shell
     extra_configs:
-      - arch:posix:CONFIG_NATIVE_UART_0_ON_STDINOUT=y
-    integration_platforms:
-      - native_sim
-      - qemu_cortex_m3
-    tags:
-      - test_framework
-      - pytest
-      - shell
+      - CONFIG_SHELL_VT100_COLORS=n
+    harness_config:
+      shell_commands: *kernel_commands
diff --git a/samples/subsys/usb/cdc_acm/README.rst b/samples/subsys/usb/cdc_acm/README.rst
index e30edfcec7b..21ce853ae08 100644
--- a/samples/subsys/usb/cdc_acm/README.rst
+++ b/samples/subsys/usb/cdc_acm/README.rst
@@ -93,6 +93,3 @@ For this example, it would look like this:
 .. code-block:: none
 
    ATTRS{idVendor}=="8086" ATTRS{idProduct}=="f8a1", ENV{ID_MM_DEVICE_IGNORE}="1"
-
-You can use
-``/lib/udev/rules.d/77-mm-usb-device-blacklist.rules`` as reference.
diff --git a/samples/subsys/usb/cdc_acm/app.overlay b/samples/subsys/usb/cdc_acm/app.overlay
index c50d0fd9d69..56ed8d4b43f 100644
--- a/samples/subsys/usb/cdc_acm/app.overlay
+++ b/samples/subsys/usb/cdc_acm/app.overlay
@@ -7,5 +7,6 @@
 &zephyr_udc0 {
 	cdc_acm_uart0 {
 		compatible = "zephyr,cdc-acm-uart";
+		label = "Zephyr USB CDC-ACM";
 	};
 };
diff --git a/samples/subsys/usb/cdc_acm/sample.yaml b/samples/subsys/usb/cdc_acm/sample.yaml
index d1906f58502..f802443cad5 100644
--- a/samples/subsys/usb/cdc_acm/sample.yaml
+++ b/samples/subsys/usb/cdc_acm/sample.yaml
@@ -22,6 +22,7 @@ tests:
       - nucleo_f413zh
       - mimxrt685_evk/mimxrt685s/cm33
       - mimxrt1060_evk/mimxrt1062/qspi
+      - max32690evkit/max32690/m4
     harness: console
     harness_config:
       type: one_line
diff --git a/samples/subsys/usb/common/sample_usbd_init.c b/samples/subsys/usb/common/sample_usbd_init.c
index 25e3a455546..69642372a58 100644
--- a/samples/subsys/usb/common/sample_usbd_init.c
+++ b/samples/subsys/usb/common/sample_usbd_init.c
@@ -15,6 +15,12 @@ LOG_MODULE_REGISTER(usbd_sample_config);
 
 #define ZEPHYR_PROJECT_USB_VID		0x2fe3
 
+/* By default, do not register the USB DFU class DFU mode instance. */
+static const char *const blocklist[] = {
+	"dfu_dfu",
+	NULL,
+};
+
 /* doc device instantiation start */
 /*
  * Instantiate a context named sample_usbd using the default USB device
@@ -74,6 +80,7 @@ static void sample_fix_code_triple(struct usbd_context *uds_ctx,
 	if (IS_ENABLED(CONFIG_USBD_CDC_ACM_CLASS) ||
 	    IS_ENABLED(CONFIG_USBD_CDC_ECM_CLASS) ||
 	    IS_ENABLED(CONFIG_USBD_CDC_NCM_CLASS) ||
+	    IS_ENABLED(CONFIG_USBD_MIDI2_CLASS) ||
 	    IS_ENABLED(CONFIG_USBD_AUDIO2_CLASS)) {
 		/*
 		 * Class with multiple interfaces have an Interface
@@ -119,7 +126,8 @@ struct usbd_context *sample_usbd_setup_device(usbd_msg_cb_t msg_cb)
 	}
 	/* doc add string descriptor end */
 
-	if (usbd_caps_speed(&sample_usbd) == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_caps_speed(&sample_usbd) == USBD_SPEED_HS) {
 		err = usbd_add_configuration(&sample_usbd, USBD_SPEED_HS,
 					     &sample_hs_config);
 		if (err) {
@@ -127,7 +135,8 @@ struct usbd_context *sample_usbd_setup_device(usbd_msg_cb_t msg_cb)
 			return NULL;
 		}
 
-		err = usbd_register_all_classes(&sample_usbd, USBD_SPEED_HS, 1);
+		err = usbd_register_all_classes(&sample_usbd, USBD_SPEED_HS, 1,
+						blocklist);
 		if (err) {
 			LOG_ERR("Failed to add register classes");
 			return NULL;
@@ -146,7 +155,7 @@ struct usbd_context *sample_usbd_setup_device(usbd_msg_cb_t msg_cb)
 	/* doc configuration register end */
 
 	/* doc functions register start */
-	err = usbd_register_all_classes(&sample_usbd, USBD_SPEED_FS, 1);
+	err = usbd_register_all_classes(&sample_usbd, USBD_SPEED_FS, 1, blocklist);
 	if (err) {
 		LOG_ERR("Failed to add register classes");
 		return NULL;
@@ -154,6 +163,7 @@ struct usbd_context *sample_usbd_setup_device(usbd_msg_cb_t msg_cb)
 	/* doc functions register end */
 
 	sample_fix_code_triple(&sample_usbd, USBD_SPEED_FS);
+	usbd_self_powered(&sample_usbd, attributes & USB_SCD_SELF_POWERED);
 
 	if (msg_cb != NULL) {
 		/* doc device init-and-msg start */
diff --git a/samples/subsys/usb/dfu-next/CMakeLists.txt b/samples/subsys/usb/dfu-next/CMakeLists.txt
new file mode 100644
index 00000000000..defe46f998f
--- /dev/null
+++ b/samples/subsys/usb/dfu-next/CMakeLists.txt
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(usb-dfu)
+
+include(${ZEPHYR_BASE}/samples/subsys/usb/common/common.cmake)
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/samples/subsys/usb/dfu-next/Kconfig b/samples/subsys/usb/dfu-next/Kconfig
new file mode 100644
index 00000000000..44a54b057d3
--- /dev/null
+++ b/samples/subsys/usb/dfu-next/Kconfig
@@ -0,0 +1,36 @@
+# Copyright (c) 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+menu "USB DFU sample options"
+
+config APP_USB_DFU_USE_FLASH_BACKEND
+	select FLASH
+	select FLASH_MAP
+	select STREAM_FLASH
+	select IMG_MANAGER
+	select IMG_ERASE_PROGRESSIVELY
+	bool "Option to clear the flash area before mounting"
+	help
+	  Use this to force an existing file system to be created.
+
+if APP_USB_DFU_USE_FLASH_BACKEND
+
+config USBD_DFU_FLASH
+	default y
+
+config USBD_DFU_FLASH_SLOT0
+	default n
+
+config USBD_DFU_FLASH_SLOT1
+	default y
+
+endif
+
+endmenu
+
+# Source common USB sample options used to initialize new experimental USB
+# device stack. The scope of these options is limited to USB samples in project
+# tree, you cannot use them in your own application.
+source "samples/subsys/usb/common/Kconfig.sample_usbd"
+
+source "Kconfig.zephyr"
diff --git a/samples/subsys/usb/dfu-next/README.rst b/samples/subsys/usb/dfu-next/README.rst
new file mode 100644
index 00000000000..7d78fedc079
--- /dev/null
+++ b/samples/subsys/usb/dfu-next/README.rst
@@ -0,0 +1,137 @@
+.. zephyr:code-sample:: dfu-next
+   :name: USB DFU
+   :relevant-api: usbd_api usbd_dfu
+
+   Implement a basic USB DFU device
+
+Overview
+********
+
+This sample application demonstrates the USB DFU implementation using the
+new experimental USB device stack.
+
+Requirements
+************
+
+This project requires an experimental USB device driver (UDC API) and uses the
+:ref:`disk_access_api` and RAM-disk to download/upload the image.
+
+Building and Running
+********************
+
+This sample can be built for multiple boards, in this example we will build it
+for the reel board:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/subsys/usb/dfu-next
+   :board: reel_board
+   :goals: build flash
+   :compact:
+
+`dfu-util`_ tool can be used to download or upload the images. There are two
+modes of operation in the USB DFU, runtime and DFU. The example starts in
+runtime mode. To switch to DFU mode without uploading or downloading, the
+following command can be used:
+
+.. code-block:: console
+
+   dfu-util --detach
+
+Use the following command to upload the ``ramdisk0`` image to the host:
+
+.. code-block:: console
+
+   dfu-util --alt 0 --upload ramdisk0_backup.bin
+
+Use the following command to download the ``ramdisk0`` image to the device:
+
+.. code-block:: console
+
+   dfu-util --alt 0 --download ramdisk0_backup.bin
+
+Building with flash backend enabled
+***********************************
+
+The USB DFU device support has a built-in flash backend. This backend uses
+:ref:`flash_img_api` and :ref:`flash_map_api` to write or read flash image, the
+implementation is similar to the one we had in the previous USB DFU device
+example.
+
+To use flash backend set the :kconfig:option:`CONFIG_APP_USB_DFU_USE_FLASH_BACKEND`.
+An additional interface will be available in DFU mode to upload/download the
+SLOT-1 image.
+
+It is also possible to try the sample together with the MCUboot bootloader
+library. The following example shows how to build MCUboot and this sample with
+flash backend and MCUboot support enabled using the :ref:`sysbuild`:
+
+.. zephyr-app-commands::
+   :tool: west
+   :zephyr-app: samples/subsys/usb/dfu-next
+   :board: reel_board
+   :goals: build flash
+   :west-args: --sysbuild
+   :gen-args: -DSB_CONFIG_BOOTLOADER_MCUBOOT=y -DCONFIG_APP_USB_DFU_USE_FLASH_BACKEND=y
+
+Another application image is required to be used as a firmware update and
+downloaded to SLOT-1. Build and sign a second application image e.g.
+:zephyr:code-sample:`hello_world`, which will be used as an image for the
+update. Do not forget to enable the required :kconfig:option:`CONFIG_BOOTLOADER_MCUBOOT`
+option (as described in :ref:`mcuboot`). For example:
+
+.. zephyr-app-commands::
+   :app: zephyr/samples/hello_world
+   :board: reel_board
+   :gen-args: -DCONFIG_MCUBOOT_SIGNATURE_KEY_FILE=\"bootloader/mcuboot/root-rsa-2048.pem\" -DCONFIG_BOOTLOADER_MCUBOOT=y
+   :goals: flash
+
+Use the following command to download new image to the device:
+
+.. code-block:: console
+
+   dfu-util --alt 1 --download build/zephyr/zephyr.signed.bin
+
+Reset the SoC. MCUboot boot will swap the images and boot the new application,
+showing this output to the console:
+
+.. code-block:: console
+
+   *** Booting MCUboot v2.1.0-rc1-134-gb9d69dd2a2d6 ***
+   *** Using Zephyr OS build v3.7.0-4345-ga5d0d8533a41 ***
+   I: Starting bootloader
+   I: Primary image: magic=good, swap_type=0x4, copy_done=0x1, image_ok=0x1
+   I: Secondary image: magic=good, swap_type=0x2, copy_done=0x3, image_ok=0x3
+   I: Boot source: none
+   I: Image index: 0, Swap type: test
+   I: Starting swap using move algorithm.
+   I: Bootloader chainload address offset: 0xc000
+   I: Image version: v0.0.0
+   I: Jumping to the first image slot
+   *** Booting Zephyr OS build v3.7.0-4345-ga5d0d8533a41 ***
+   Hello World! reel_board@1/nrf52840
+
+
+Reset the SoC again and MCUboot should revert the images and boot
+USB DFU sample, showing this output to the console:
+
+.. code-block:: console
+
+   *** Booting MCUboot v2.1.0-rc1-134-gb9d69dd2a2d6 ***
+   *** Using Zephyr OS build v3.7.0-4345-ga5d0d8533a41 ***
+   I: Starting bootloader
+   I: Primary image: magic=good, swap_type=0x2, copy_done=0x1, image_ok=0x3
+   I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
+   I: Boot source: none
+   I: Image index: 0, Swap type: revert
+   I: Starting swap using move algorithm.
+   I: Secondary image: magic=unset, swap_type=0x1, copy_done=0x3, image_ok=0x3
+   I: Bootloader chainload address offset: 0xc000
+   I: Image version: v0.0.0
+   I: Jumping to the first image slot
+   *** Booting Zephyr OS build v3.7.0-4345-ga5d0d8533a41 ***
+   [00:00:00.000,335] <inf> main: USBD message: VBUS ready
+   [00:00:00.000,427] <inf> main: USB DFU sample is initialized
+
+
+.. _dfu-util: https://dfu-util.sourceforge.net/
+.. _Using MCUboot with Zephyr: https://docs.mcuboot.com/readme-zephyr
diff --git a/samples/subsys/usb/dfu-next/app.overlay b/samples/subsys/usb/dfu-next/app.overlay
new file mode 100644
index 00000000000..ef18db35ccb
--- /dev/null
+++ b/samples/subsys/usb/dfu-next/app.overlay
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	ramdisk0 {
+		compatible = "zephyr,ram-disk";
+		disk-name = "image0";
+		sector-size = <512>;
+		sector-count = <32>;
+	};
+};
diff --git a/samples/subsys/usb/dfu-next/prj.conf b/samples/subsys/usb/dfu-next/prj.conf
new file mode 100644
index 00000000000..4ac6e6dd8d2
--- /dev/null
+++ b/samples/subsys/usb/dfu-next/prj.conf
@@ -0,0 +1,10 @@
+CONFIG_USB_DEVICE_STACK_NEXT=y
+CONFIG_USBD_DFU=y
+
+CONFIG_LOG=y
+CONFIG_USBD_LOG_LEVEL_WRN=y
+CONFIG_USBD_DFU_LOG_LEVEL_WRN=y
+CONFIG_UDC_DRIVER_LOG_LEVEL_WRN=y
+CONFIG_SAMPLE_USBD_PID=0x0005
+
+CONFIG_DISK_ACCESS=y
diff --git a/samples/subsys/usb/dfu-next/sample.yaml b/samples/subsys/usb/dfu-next/sample.yaml
new file mode 100644
index 00000000000..2190adf686f
--- /dev/null
+++ b/samples/subsys/usb/dfu-next/sample.yaml
@@ -0,0 +1,30 @@
+sample:
+  name: USB DFU sample
+common:
+  min_ram: 64
+  depends_on:
+    - usbd
+  harness: console
+  harness_config:
+    type: one_line
+    regex:
+      - "USB DFU sample is initialized"
+tests:
+  sample.usbd.dfu:
+    integration_platforms:
+      - nrf52840dk/nrf52840
+      - nrf54h20dk/nrf54h20/cpuapp
+      - frdm_k64f
+      - stm32f723e_disco
+      - nucleo_f413zh
+      - mimxrt685_evk/mimxrt685s/cm33
+      - mimxrt1060_evk/mimxrt1062/qspi
+    tags: usb
+  sample.usbd.dfu-flash:
+    platform_allow:
+      - nrf52840dk/nrf52840
+      - frdm_k64f
+    min_flash: 1024
+    tags: usb
+    extra_configs:
+      - CONFIG_APP_USB_DFU_USE_FLASH_BACKEND=y
diff --git a/samples/subsys/usb/dfu-next/src/main.c b/samples/subsys/usb/dfu-next/src/main.c
new file mode 100644
index 00000000000..81f8aa6c89c
--- /dev/null
+++ b/samples/subsys/usb/dfu-next/src/main.c
@@ -0,0 +1,291 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <sample_usbd.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/usb/usbd.h>
+#include <zephyr/usb/class/usbd_dfu.h>
+#include <zephyr/storage/disk_access.h>
+#include <zephyr/dfu/mcuboot.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(main, LOG_LEVEL_INF);
+
+USBD_DEVICE_DEFINE(dfu_usbd,
+		   DEVICE_DT_GET(DT_NODELABEL(zephyr_udc0)),
+		   0x2fe3, 0xffff);
+
+USBD_DESC_LANG_DEFINE(sample_lang);
+USBD_DESC_CONFIG_DEFINE(fs_cfg_desc, "DFU FS Configuration");
+USBD_DESC_CONFIG_DEFINE(hs_cfg_desc, "DFU HS Configuration");
+
+static const uint8_t attributes = (IS_ENABLED(CONFIG_SAMPLE_USBD_SELF_POWERED) ?
+				   USB_SCD_SELF_POWERED : 0) |
+				  (IS_ENABLED(CONFIG_SAMPLE_USBD_REMOTE_WAKEUP) ?
+				   USB_SCD_REMOTE_WAKEUP : 0);
+/* Full speed configuration */
+USBD_CONFIGURATION_DEFINE(sample_fs_config,
+			  attributes,
+			  CONFIG_SAMPLE_USBD_MAX_POWER, &fs_cfg_desc);
+
+/* High speed configuration */
+USBD_CONFIGURATION_DEFINE(sample_hs_config,
+			  attributes,
+			  CONFIG_SAMPLE_USBD_MAX_POWER, &hs_cfg_desc);
+
+static void switch_to_dfu_mode(struct usbd_context *const ctx);
+
+struct dfu_ramdisk_data {
+	const char *name;
+	uint32_t last_block;
+	uint32_t sector_size;
+	uint32_t sector_count;
+	union {
+		uint32_t uploaded;
+		uint32_t downloaded;
+	};
+};
+
+static struct dfu_ramdisk_data ramdisk0_data = {
+	.name = "image0",
+};
+
+static int init_dfu_ramdisk_data(struct dfu_ramdisk_data *const data)
+{
+	int err;
+
+	err = disk_access_init(data->name);
+	if (err) {
+		return err;
+	}
+
+	err = disk_access_status(data->name);
+	if (err) {
+		return err;
+	}
+
+	err = disk_access_ioctl(data->name, DISK_IOCTL_GET_SECTOR_COUNT, &data->sector_count);
+	if (err) {
+		return err;
+	}
+
+	err = disk_access_ioctl(data->name, DISK_IOCTL_GET_SECTOR_SIZE, &data->sector_size);
+	if (err) {
+		return err;
+	}
+
+	LOG_INF("disk %s sector count %u sector size %u",
+		data->name, data->sector_count, data->sector_size);
+
+	return err;
+}
+
+static int ramdisk_read(void *const priv, const uint32_t block, const uint16_t size,
+			uint8_t buf[static CONFIG_USBD_DFU_TRANSFER_SIZE])
+{
+	struct dfu_ramdisk_data *const data = priv;
+	int err;
+
+	if (size == 0) {
+		/* There is nothing to upload */
+		return 0;
+	}
+
+	if (block == 0) {
+		if (init_dfu_ramdisk_data(data)) {
+			LOG_ERR("Failed to init ramdisk data");
+			return -EINVAL;
+		}
+
+		data->last_block = 0;
+		data->uploaded = 0;
+	} else {
+		if (data->last_block + 1U != block) {
+			return -EINVAL;
+		}
+
+	}
+
+	if (block >= data->sector_count) {
+		/* Nothing to upload */
+		return 0;
+	}
+
+	err = disk_access_read(data->name, buf, block, 1);
+	if (err) {
+		LOG_ERR("Failed to read from RAMdisk");
+		return err;
+	}
+
+	data->last_block = block;
+	data->uploaded += MIN(size, data->sector_size);
+	LOG_INF("block %u size %u uploaded %u", block, size, data->uploaded);
+
+	return size;
+}
+
+static int ramdisk_write(void *const priv, const uint32_t block, const uint16_t size,
+			 const uint8_t buf[static CONFIG_USBD_DFU_TRANSFER_SIZE])
+{
+	struct dfu_ramdisk_data *const data = priv;
+	int err;
+
+	if (block == 0) {
+		if (init_dfu_ramdisk_data(data)) {
+			LOG_ERR("Failed to init ramdisk data");
+			return -EINVAL;
+		}
+
+		data->last_block = 0;
+		data->downloaded = 0;
+	} else {
+		if (data->last_block + 1U != block) {
+			return -EINVAL;
+		}
+
+	}
+
+	if (size == 0) {
+		/* Nothing to write */
+		return 0;
+	}
+
+	err = disk_access_write(data->name, buf, block, 1);
+	if (err) {
+		LOG_ERR("Failed to write to RAMdisk");
+		return err;
+	}
+
+	data->last_block = block;
+	data->downloaded += size;
+	LOG_INF("block %u size %u downloaded %u", block, size, data->downloaded);
+
+	return 0;
+}
+
+USBD_DFU_DEFINE_IMG(ramdisk0, "ramdisk0", &ramdisk0_data, ramdisk_read, ramdisk_write, NULL);
+
+static void msg_cb(struct usbd_context *const usbd_ctx,
+		   const struct usbd_msg *const msg)
+{
+	LOG_INF("USBD message: %s", usbd_msg_type_string(msg->type));
+
+	if (msg->type == USBD_MSG_CONFIGURATION) {
+		LOG_INF("\tConfiguration value %d", msg->status);
+	}
+
+	if (usbd_can_detect_vbus(usbd_ctx)) {
+		if (msg->type == USBD_MSG_VBUS_READY) {
+			if (usbd_enable(usbd_ctx)) {
+				LOG_ERR("Failed to enable device support");
+			}
+		}
+
+		if (msg->type == USBD_MSG_VBUS_REMOVED) {
+			if (usbd_disable(usbd_ctx)) {
+				LOG_ERR("Failed to disable device support");
+			}
+		}
+	}
+
+	if (msg->type == USBD_MSG_DFU_APP_DETACH) {
+		switch_to_dfu_mode(usbd_ctx);
+	}
+
+	if (msg->type == USBD_MSG_DFU_DOWNLOAD_COMPLETED) {
+		if (IS_ENABLED(CONFIG_BOOTLOADER_MCUBOOT) &&
+		    IS_ENABLED(CONFIG_APP_USB_DFU_USE_FLASH_BACKEND)) {
+			boot_request_upgrade(false);
+		}
+	}
+}
+
+static void switch_to_dfu_mode(struct usbd_context *const ctx)
+{
+	int err;
+
+	LOG_INF("Detach USB device");
+	usbd_disable(ctx);
+	usbd_shutdown(ctx);
+
+	err = usbd_add_descriptor(&dfu_usbd, &sample_lang);
+	if (err) {
+		LOG_ERR("Failed to initialize language descriptor (%d)", err);
+		return;
+	}
+
+	if (usbd_caps_speed(&dfu_usbd) == USBD_SPEED_HS) {
+		err = usbd_add_configuration(&dfu_usbd, USBD_SPEED_HS, &sample_hs_config);
+		if (err) {
+			LOG_ERR("Failed to add High-Speed configuration");
+			return;
+		}
+
+		err = usbd_register_class(&dfu_usbd, "dfu_dfu", USBD_SPEED_HS, 1);
+		if (err) {
+			LOG_ERR("Failed to add register classes");
+			return;
+		}
+
+		usbd_device_set_code_triple(&dfu_usbd, USBD_SPEED_HS, 0, 0, 0);
+	}
+
+	err = usbd_add_configuration(&dfu_usbd, USBD_SPEED_FS, &sample_fs_config);
+	if (err) {
+		LOG_ERR("Failed to add Full-Speed configuration");
+		return;
+	}
+
+	err = usbd_register_class(&dfu_usbd, "dfu_dfu", USBD_SPEED_FS, 1);
+	if (err) {
+		LOG_ERR("Failed to add register classes");
+		return;
+	}
+
+	usbd_device_set_code_triple(&dfu_usbd, USBD_SPEED_FS, 0, 0, 0);
+
+	err = usbd_init(&dfu_usbd);
+	if (err) {
+		LOG_ERR("Failed to initialize USB device support");
+		return;
+	}
+
+	err = usbd_msg_register_cb(&dfu_usbd, msg_cb);
+	if (err) {
+		LOG_ERR("Failed to register message callback");
+		return;
+	}
+
+	err = usbd_enable(&dfu_usbd);
+	if (err) {
+		LOG_ERR("Failed to enable USB device support");
+	}
+}
+
+int main(void)
+{
+	struct usbd_context *sample_usbd;
+	int ret;
+
+	sample_usbd = sample_usbd_init_device(msg_cb);
+	if (sample_usbd == NULL) {
+		LOG_ERR("Failed to initialize USB device");
+		return -ENODEV;
+	}
+
+	if (!usbd_can_detect_vbus(sample_usbd)) {
+		ret = usbd_enable(sample_usbd);
+		if (ret) {
+			LOG_ERR("Failed to enable device support");
+			return ret;
+		}
+	}
+
+	LOG_INF("USB DFU sample is initialized");
+
+	return 0;
+}
diff --git a/samples/subsys/usb/dfu/sample.yaml b/samples/subsys/usb/dfu/sample.yaml
index 9e5d3549ae7..e9b9c213323 100644
--- a/samples/subsys/usb/dfu/sample.yaml
+++ b/samples/subsys/usb/dfu/sample.yaml
@@ -8,11 +8,17 @@ common:
     - mimxrt1010_evk
     - mimxrt1020_evk
     - mimxrt1015_evk
-    - mimxrt1060_evk/mimxrt1062/qspi
+    - mimxrt1060_evk@A/mimxrt1062/qspi
+    - mimxrt1060_evk@B/mimxrt1062/qspi
+    - mimxrt1060_evk@C/mimxrt1062/qspi
     - sam4l_ek
+    - same54_xpro
+    - samr21_xpro
     - mimxrt1050_evk/mimxrt1052/hyperflash
     - mimxrt1050_evk/mimxrt1052/qspi
     - mimxrt1060_evk/mimxrt1062/hyperflash
+    - mimxrt1180_evk/mimxrt1189/cm7
+    - mimxrt700_evk/mimxrt798s/cm33_cpu0
     - nucleo_f207zg
     - teensy40
     - teensy41
diff --git a/samples/subsys/usb/hid-keyboard/prj.conf b/samples/subsys/usb/hid-keyboard/prj.conf
index 04ce14ad588..a854a502f06 100644
--- a/samples/subsys/usb/hid-keyboard/prj.conf
+++ b/samples/subsys/usb/hid-keyboard/prj.conf
@@ -6,6 +6,7 @@ CONFIG_USBD_LOG_LEVEL_WRN=y
 CONFIG_USBD_HID_LOG_LEVEL_WRN=y
 CONFIG_UDC_DRIVER_LOG_LEVEL_WRN=y
 CONFIG_SAMPLE_USBD_PID=0x0007
+CONFIG_SAMPLE_USBD_REMOTE_WAKEUP=y
 
 CONFIG_GPIO=y
 CONFIG_INPUT=y
diff --git a/samples/subsys/usb/hid-keyboard/src/main.c b/samples/subsys/usb/hid-keyboard/src/main.c
index 14f360beb3a..c02072d3f5d 100644
--- a/samples/subsys/usb/hid-keyboard/src/main.c
+++ b/samples/subsys/usb/hid-keyboard/src/main.c
@@ -279,6 +279,17 @@ int main(void)
 			continue;
 		}
 
+		if (usbd_is_suspended(sample_usbd)) {
+			/* on a press of any button, send wakeup request */
+			if (kb_evt.value) {
+				ret = usbd_wakeup_request(sample_usbd);
+				if (ret) {
+					LOG_ERR("Remote wakeup error, %d", ret);
+				}
+			}
+			continue;
+		}
+
 		ret = hid_device_submit_report(hid_dev, KB_REPORT_COUNT, report);
 		if (ret) {
 			LOG_ERR("HID submit report error, %d", ret);
diff --git a/samples/subsys/usb/hid-mouse/sample.yaml b/samples/subsys/usb/hid-mouse/sample.yaml
index a9d65e3b501..132c71c928b 100644
--- a/samples/subsys/usb/hid-mouse/sample.yaml
+++ b/samples/subsys/usb/hid-mouse/sample.yaml
@@ -21,8 +21,8 @@ tests:
       - frdm_k64f
       - stm32f723e_disco
       - nucleo_f413zh
-      - mimxrt685_evk/mimxrt685s/cm33
       - mimxrt1060_evk/mimxrt1062/qspi
+      - max32690evkit/max32690/m4
     extra_args:
       - CONF_FILE="usbd_next_prj.conf"
       - EXTRA_DTC_OVERLAY_FILE="usbd_next.overlay"
diff --git a/samples/subsys/usb/mass/sample.yaml b/samples/subsys/usb/mass/sample.yaml
index 352ee210022..4dbf2126798 100644
--- a/samples/subsys/usb/mass/sample.yaml
+++ b/samples/subsys/usb/mass/sample.yaml
@@ -30,6 +30,7 @@ tests:
       - nucleo_f413zh
       - mimxrt685_evk/mimxrt685s/cm33
       - mimxrt1060_evk/mimxrt1062/qspi
+      - max32690evkit/max32690/m4
     extra_args:
       - CONF_FILE="usbd_next_prj.conf"
       - EXTRA_DTC_OVERLAY_FILE="ramdisk.overlay"
diff --git a/samples/subsys/usb/midi/CMakeLists.txt b/samples/subsys/usb/midi/CMakeLists.txt
new file mode 100644
index 00000000000..5bb9b0097df
--- /dev/null
+++ b/samples/subsys/usb/midi/CMakeLists.txt
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(usb_midi)
+
+include(${ZEPHYR_BASE}/samples/subsys/usb/common/common.cmake)
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/samples/subsys/usb/midi/Kconfig b/samples/subsys/usb/midi/Kconfig
new file mode 100644
index 00000000000..b6cd6618aff
--- /dev/null
+++ b/samples/subsys/usb/midi/Kconfig
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Titouan Christophe
+# SPDX-License-Identifier: Apache-2.0
+
+# Source common USB sample options used to initialize new experimental USB
+# device stack. The scope of these options is limited to USB samples in project
+# tree, you cannot use them in your own application.
+source "samples/subsys/usb/common/Kconfig.sample_usbd"
+
+source "Kconfig.zephyr"
diff --git a/samples/subsys/usb/midi/README.rst b/samples/subsys/usb/midi/README.rst
new file mode 100644
index 00000000000..35c2b52acaa
--- /dev/null
+++ b/samples/subsys/usb/midi/README.rst
@@ -0,0 +1,84 @@
+.. zephyr:code-sample:: usb-midi2-device
+   :name: USB MIDI2 device
+   :relevant-api: usbd_api usbd_midi2 input_events
+
+   Implements a simple USB MIDI loopback and keyboard device.
+
+Overview
+********
+
+This sample demonstrates how to implement a USB MIDI device. It can run on
+any board with a USB device controller. This sample sends all MIDI1 messages
+sent to the device back to the host. In addition, presses and release on
+input keys (such as the board user buttons) are sent as MIDI1 note on and
+note off events.
+
+The application exposes a single USB-MIDI interface with a single bidirectional
+group terminal. This allows exchanging data with the host on a "virtual wire"
+that carries MIDI1 messages, pretty much like a standard USB-MIDI in/out adapter
+would provide. The loopback acts as if a real MIDI cable was connected between
+the output and the input, and the input keys act as a MIDI keyboard.
+
+Building and Running
+********************
+
+The code can be found in :zephyr_file:`samples/subsys/usb/midi`.
+
+To build and flash the application:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/subsys/usb/midi
+   :board: nucleo_f429zi
+   :goals: build flash
+   :compact:
+
+Using the MIDI interface
+************************
+
+Once this sample is flashed, connect the device USB port to a host computer
+with MIDI support. For example, on Linux, you can use alsa to access the device:
+
+.. code-block:: console
+
+  $ amidi -l
+  Dir Device    Name
+  IO  hw:2,1,0  Group 1 (USBD MIDI Sample)
+
+On Mac OS you can use the system tool "Audio MIDI Setup" to view the device,
+see https://support.apple.com/guide/audio-midi-setup/set-up-midi-devices-ams875bae1e0/mac
+
+The "USBD MIDI Sample" interface should also appear in any program with MIDI
+support; like your favorite Digital Audio Workstation or synthetizer. If you
+don't have any such program at hand, there are some webmidi programs online,
+for example: https://muted.io/piano/.
+
+Testing loopback
+****************
+
+Open a first shell, and start dumping MIDI events:
+
+.. code-block:: console
+
+  $ amidi -p hw:2,1,0 -d
+
+
+Then, in a second shell, send some MIDI events (for example note-on/note-off):
+
+.. code-block:: console
+
+  $ amidi -p hw:2,1,0 -S "90427f 804200"
+
+These events should then appear in the first shell (dump)
+
+On devboards with a user button, press it and observe that there are some note
+on/note off events delivered to the first shell (dump)
+
+.. code-block:: console
+
+  $ amidi -p hw:2,1,0 -d
+
+  90 40 7F
+  80 40 7F
+  90 40 7F
+  80 40 7F
+  [...]
diff --git a/samples/subsys/usb/midi/app.overlay b/samples/subsys/usb/midi/app.overlay
new file mode 100644
index 00000000000..7d8ba72ef5c
--- /dev/null
+++ b/samples/subsys/usb/midi/app.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2024 Titouan Christophe
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	usb_midi: usb_midi {
+		compatible = "zephyr,midi2-device";
+		status = "okay";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		midi_in_out@0 {
+			reg = <0 1>;
+			protocol = "midi1-up-to-128b";
+		};
+	};
+};
diff --git a/samples/subsys/usb/midi/prj.conf b/samples/subsys/usb/midi/prj.conf
new file mode 100644
index 00000000000..fdc77affb23
--- /dev/null
+++ b/samples/subsys/usb/midi/prj.conf
@@ -0,0 +1,11 @@
+CONFIG_USB_DEVICE_STACK_NEXT=y
+CONFIG_USBD_MIDI2_CLASS=y
+
+CONFIG_SAMPLE_USBD_PRODUCT="USBD MIDI Sample"
+CONFIG_SAMPLE_USBD_PID=0x0010
+
+CONFIG_INPUT=y
+
+CONFIG_LOG=y
+CONFIG_USBD_LOG_LEVEL_WRN=y
+CONFIG_UDC_DRIVER_LOG_LEVEL_WRN=y
diff --git a/samples/subsys/usb/midi/sample.yaml b/samples/subsys/usb/midi/sample.yaml
new file mode 100644
index 00000000000..5189725c1a4
--- /dev/null
+++ b/samples/subsys/usb/midi/sample.yaml
@@ -0,0 +1,11 @@
+sample:
+  name: USB MIDI 2.0 device class sample
+tests:
+  sample.usb_device_next.midi:
+    depends_on: usbd
+    tags: usb
+    harness: console
+    harness_config:
+      type: one_line
+      regex:
+        - "USB device support enabled"
diff --git a/samples/subsys/usb/midi/src/main.c b/samples/subsys/usb/midi/src/main.c
new file mode 100644
index 00000000000..4581d1f0183
--- /dev/null
+++ b/samples/subsys/usb/midi/src/main.c
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2024 Titouan Christophe
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * @file
+ * @brief Sample application for USB MIDI 2.0 device class
+ */
+
+#include <sample_usbd.h>
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/input/input.h>
+#include <zephyr/usb/class/usbd_midi2.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(sample_usb_midi, LOG_LEVEL_INF);
+
+static const struct device *const midi = DEVICE_DT_GET(DT_NODELABEL(usb_midi));
+
+static struct gpio_dt_spec led = GPIO_DT_SPEC_GET_OR(DT_ALIAS(led0), gpios, {0});
+
+static void key_press(struct input_event *evt, void *user_data)
+{
+	/* Only handle key presses in the 7bit MIDI range */
+	if (evt->type != INPUT_EV_KEY || evt->code > 0x7f) {
+		return;
+	}
+	uint8_t command = evt->value ? UMP_MIDI_NOTE_ON : UMP_MIDI_NOTE_OFF;
+	uint8_t channel = 0;
+	uint8_t note = evt->code;
+	uint8_t velocity = 100;
+
+	struct midi_ump ump = UMP_MIDI1_CHANNEL_VOICE(0, command, channel,
+						      note, velocity);
+	usbd_midi_send(midi, ump);
+}
+INPUT_CALLBACK_DEFINE(NULL, key_press, NULL);
+
+static void on_midi_packet(const struct device *dev, const struct midi_ump ump)
+{
+	LOG_INF("Received MIDI packet (MT=%X)", UMP_MT(ump));
+
+	/* Only send MIDI1 channel voice messages back to the host */
+	if (UMP_MT(ump) == UMP_MT_MIDI1_CHANNEL_VOICE) {
+		LOG_INF("Send back MIDI1 message %02X %02X %02X", UMP_MIDI_STATUS(ump),
+			UMP_MIDI1_P1(ump), UMP_MIDI1_P2(ump));
+		usbd_midi_send(dev, ump);
+	}
+}
+
+static void on_device_ready(const struct device *dev, const bool ready)
+{
+	/* Light up the LED (if any) when USB-MIDI2.0 is enabled */
+	if (led.port) {
+		gpio_pin_set_dt(&led, ready);
+	}
+}
+
+static const struct usbd_midi_ops ops = {
+	.rx_packet_cb = on_midi_packet,
+	.ready_cb = on_device_ready,
+};
+
+int main(void)
+{
+	struct usbd_context *sample_usbd;
+
+	if (!device_is_ready(midi)) {
+		LOG_ERR("MIDI device not ready");
+		return -1;
+	}
+
+	if (led.port) {
+		if (gpio_pin_configure_dt(&led, GPIO_OUTPUT)) {
+			LOG_ERR("Unable to setup LED, not using it");
+			memset(&led, 0, sizeof(led));
+		}
+	}
+
+	usbd_midi_set_ops(midi, &ops);
+
+	sample_usbd = sample_usbd_init_device(NULL);
+	if (sample_usbd == NULL) {
+		LOG_ERR("Failed to initialize USB device");
+		return -1;
+	}
+
+	if (usbd_enable(sample_usbd)) {
+		LOG_ERR("Failed to enable device support");
+		return -1;
+	}
+
+	LOG_INF("USB device support enabled");
+	return 0;
+}
diff --git a/samples/subsys/usb/shell/prj.conf b/samples/subsys/usb/shell/prj.conf
index e821f19c03a..03d6eb8f1bb 100644
--- a/samples/subsys/usb/shell/prj.conf
+++ b/samples/subsys/usb/shell/prj.conf
@@ -2,6 +2,7 @@ CONFIG_SHELL=y
 CONFIG_USB_DEVICE_STACK_NEXT=y
 CONFIG_USBD_SHELL=y
 CONFIG_USBD_LOOPBACK_CLASS=y
+CONFIG_UDC_BUF_POOL_SIZE=4096
 
 CONFIG_LOG=y
 CONFIG_USBD_LOG_LEVEL_WRN=y
diff --git a/samples/subsys/usb/testusb/CMakeLists.txt b/samples/subsys/usb/testusb/CMakeLists.txt
index 2351275f036..353c10f0738 100644
--- a/samples/subsys/usb/testusb/CMakeLists.txt
+++ b/samples/subsys/usb/testusb/CMakeLists.txt
@@ -4,5 +4,6 @@ cmake_minimum_required(VERSION 3.20.0)
 find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
 project(testusb)
 
+include(${ZEPHYR_BASE}/samples/subsys/usb/common/common.cmake)
 FILE(GLOB app_sources src/*.c)
 target_sources(app PRIVATE ${app_sources})
diff --git a/samples/subsys/usb/testusb/Kconfig b/samples/subsys/usb/testusb/Kconfig
new file mode 100644
index 00000000000..96c54558948
--- /dev/null
+++ b/samples/subsys/usb/testusb/Kconfig
@@ -0,0 +1,9 @@
+# Copyright (c) 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Source common USB sample options used to initialize new experimental USB
+# device stack. The scope of these options is limited to USB samples in project
+# tree, you cannot use them in your own application.
+source "samples/subsys/usb/common/Kconfig.sample_usbd"
+
+source "Kconfig.zephyr"
diff --git a/samples/subsys/usb/testusb/README.rst b/samples/subsys/usb/testusb/README.rst
index 03e6f6c104a..52a124e05e6 100644
--- a/samples/subsys/usb/testusb/README.rst
+++ b/samples/subsys/usb/testusb/README.rst
@@ -1,6 +1,6 @@
 .. zephyr:code-sample:: testusb-app
-   :name: USB testing application
-   :relevant-api: _usb_device_core_api
+   :name: USB device testing application
+   :relevant-api: usbd_api
 
    Test USB device drivers using a loopback function.
 
diff --git a/samples/subsys/usb/testusb/prj.conf b/samples/subsys/usb/testusb/prj.conf
index e310a67818d..fcbf19c62e8 100644
--- a/samples/subsys/usb/testusb/prj.conf
+++ b/samples/subsys/usb/testusb/prj.conf
@@ -1,11 +1,11 @@
-CONFIG_STDOUT_CONSOLE=y
+CONFIG_USB_DEVICE_STACK_NEXT=y
+CONFIG_USBD_LOOPBACK_CLASS=y
+CONFIG_UDC_BUF_POOL_SIZE=4096
 
-#USB related configs
-CONFIG_USB_DEVICE_STACK=y
-CONFIG_USB_DEVICE_PRODUCT="Zephyr testusb sample"
-CONFIG_USB_DEVICE_PID=0x0009
 CONFIG_LOG=y
-CONFIG_USB_DRIVER_LOG_LEVEL_ERR=y
-CONFIG_USB_DEVICE_LOOPBACK=y
-CONFIG_USB_DEVICE_LOG_LEVEL_ERR=y
-CONFIG_USB_DEVICE_INITIALIZE_AT_BOOT=n
+CONFIG_USBD_LOG_LEVEL_ERR=y
+CONFIG_UDC_DRIVER_LOG_LEVEL_ERR=y
+CONFIG_USBD_LOOPBACK_LOG_LEVEL_ERR=y
+
+CONFIG_SAMPLE_USBD_PID=0x0009
+CONFIG_SAMPLE_USBD_PRODUCT="Zephyr testusb sample"
diff --git a/samples/subsys/usb/testusb/sample.yaml b/samples/subsys/usb/testusb/sample.yaml
index c251eaded73..7a6cb3dbb1c 100644
--- a/samples/subsys/usb/testusb/sample.yaml
+++ b/samples/subsys/usb/testusb/sample.yaml
@@ -1,10 +1,7 @@
 sample:
-  name: USB loopback sample
+  name: USB device loopback sample
 tests:
-  sample.usb.loopback:
-    depends_on: usb_device
+  sample.usbd.loopback:
+    depends_on: usbd
+    build_only: true
     tags: usb
-    platform_exclude:
-      - native_posix
-      - native_posix/native/64
-    harness: button
diff --git a/samples/subsys/usb/testusb/src/main.c b/samples/subsys/usb/testusb/src/main.c
index 936608fc2e9..04344e97543 100644
--- a/samples/subsys/usb/testusb/src/main.c
+++ b/samples/subsys/usb/testusb/src/main.c
@@ -1,24 +1,37 @@
 /*
- * Copyright (c) 2018 Phytec Messtechnik GmbH
+ * Copyright (c) 2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/kernel.h>
+#include <sample_usbd.h>
+#include <zephyr/usb/usbd.h>
+
 #include <zephyr/logging/log.h>
-#include <zephyr/usb/usb_device.h>
-LOG_MODULE_REGISTER(main);
+LOG_MODULE_REGISTER(main, LOG_LEVEL_INF);
 
 int main(void)
 {
+	struct usbd_context *sample_usbd;
 	int ret;
 
-	ret = usb_enable(NULL);
-	if (ret != 0) {
-		LOG_ERR("Failed to enable USB");
-		return 0;
+	sample_usbd = sample_usbd_setup_device(NULL);
+	if (sample_usbd == NULL) {
+		LOG_ERR("Failed to setup USB device");
+		return -ENODEV;
+	}
+
+	ret = usbd_init(sample_usbd);
+	if (ret) {
+		LOG_ERR("Failed to initialize device support");
+		return ret;
+	}
+
+	ret = usbd_enable(sample_usbd);
+	if (ret) {
+		LOG_ERR("Failed to enable device support");
+		return ret;
 	}
 
-	LOG_INF("entered main.");
 	return 0;
 }
diff --git a/samples/subsys/usb/uac2_explicit_feedback/README.rst b/samples/subsys/usb/uac2_explicit_feedback/README.rst
index 4cc856f2343..d0ea63c5acf 100644
--- a/samples/subsys/usb/uac2_explicit_feedback/README.rst
+++ b/samples/subsys/usb/uac2_explicit_feedback/README.rst
@@ -15,6 +15,12 @@ The device running this sample presents itself to the host as a Full-Speed
 Asynchronous USB Audio 2 class device supporting 48 kHz 16-bit 2-channel
 (stereo) playback.
 
+.. warning::
+   Microsoft Windows USB Audio 2.0 driver available since Windows 10,
+   release 1703 expects Full-Speed explicit feedback endpoint wMaxPacketSize to
+   be equal 4, which violates the USB 2.0 Specification.
+   See https://aka.ms/AArvnax for Windows Feedback Hub report.
+
 Explicit Feedback
 *****************
 
@@ -42,11 +48,11 @@ is not available, the DPPI and TIMER peripherals on nRF5340 can be configured to
 provide relative timing information between I2S FRAMESTART and USB SOF.
 
 This sample in both modes (direct sample counting and indirect I2S buffer output
-to USB SOF offset) has been tested on :ref:`nrf5340dk_nrf5340`.
+to USB SOF offset) has been tested on :zephyr:board:`nrf5340dk`.
 
 The sample defaults to indirect feedback calculation because direct sample
 counting requires external connection between I2S LRCLK output pin to GPIOTE
-input pin (hardcoded to P1.09) on :ref:`nrf5340dk_nrf5340`. In the indirect mode
+input pin (hardcoded to P1.09) on :zephyr:board:`nrf5340dk`. In the indirect mode
 no extra connections are necessary and the sample can even be used without any
 I2S device connected where I2S signals can be checked e.g. on logic analyzer.
 
diff --git a/samples/subsys/usb/uac2_implicit_feedback/README.rst b/samples/subsys/usb/uac2_implicit_feedback/README.rst
index 99e4bd72aa6..b878f95e5f5 100644
--- a/samples/subsys/usb/uac2_implicit_feedback/README.rst
+++ b/samples/subsys/usb/uac2_implicit_feedback/README.rst
@@ -12,6 +12,10 @@ This sample demonstrates how to implement USB asynchronous bidirectional audio
 with implicit feedback. The host adjusts number of stereo samples sent for
 headphones playback based on the number of mono microphone samples received.
 
+.. warning::
+   Microsoft Windows USB Audio 2.0 driver available since Windows 10,
+   release 1703 does not support implicit feedback.
+
 Requirements
 ************
 
@@ -19,7 +23,7 @@ Target must be able to measure I2S block start (i.e. first sample from output
 buffer gets out) relative to USB SOF. The relative offset must be reported with
 single sample accuracy.
 
-This sample has been tested on :ref:`nrf5340dk_nrf5340`. While for actual audio
+This sample has been tested on :zephyr:board:`nrf5340dk`. While for actual audio
 experience it is necessary to connect external I2S ADC and I2S DAC, simple echo
 can be accomplished by shorting I2S data output with I2S data input.
 
diff --git a/samples/subsys/usb/webusb-next/sample.yaml b/samples/subsys/usb/webusb-next/sample.yaml
index e26352fe50e..d1f6d44f84b 100644
--- a/samples/subsys/usb/webusb-next/sample.yaml
+++ b/samples/subsys/usb/webusb-next/sample.yaml
@@ -12,4 +12,5 @@ tests:
       - nucleo_f413zh
       - mimxrt685_evk/mimxrt685s/cm33
       - mimxrt1060_evk/mimxrt1062/qspi
+      - max32690evkit/max32690/m4
     harness: TBD
diff --git a/samples/subsys/usb/webusb/sample.yaml b/samples/subsys/usb/webusb/sample.yaml
index c68c0366eaa..a640ffb97ce 100644
--- a/samples/subsys/usb/webusb/sample.yaml
+++ b/samples/subsys/usb/webusb/sample.yaml
@@ -4,7 +4,4 @@ tests:
   sample.usb.webusb:
     depends_on: usb_device
     tags: usb
-    platform_exclude:
-      - native_posix
-      - native_posix/native/64
     harness: TBD
diff --git a/samples/subsys/uuid/CMakeLists.txt b/samples/subsys/uuid/CMakeLists.txt
new file mode 100644
index 00000000000..98b06b94203
--- /dev/null
+++ b/samples/subsys/uuid/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright (c) 2025, SECO Mind Srl
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(dap)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/samples/subsys/uuid/README.rst b/samples/subsys/uuid/README.rst
new file mode 100644
index 00000000000..c020063389e
--- /dev/null
+++ b/samples/subsys/uuid/README.rst
@@ -0,0 +1,38 @@
+.. zephyr:code-sample:: uuid
+   :name: UUID
+
+   Manipulate UUID v4 and v5 compliant with IETF RFC 9562.
+
+Overview
+********
+
+This sample app demonstrates the use of the :c:group:`uuid` utilities to generate and manipulate
+UUIDs accordingly to IETF RFC 9562.
+
+The following functionality is demonstrated:
+
+- UUIDv4 generation
+- UUIDv5 generation from namespace and data
+- UUID conversion from/to string and to base64 and base64 URL safe formats
+
+Requirements
+************
+
+This sample relies on the following modules:
+
+- MbedTLS for the UUIDv5 hash functions
+- Base64 for the base64 encoding of UUIDs
+- Entropy source for the pseudo-random generation of UUIDv4
+
+Building and Running
+********************
+
+Use the standard ``west`` commands to build and flash this application.
+For example, for ``native_sim``:
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/subsys/uuid
+   :host-os: unix
+   :board: native_sim
+   :goals: run
+   :compact:
diff --git a/samples/subsys/uuid/prj.conf b/samples/subsys/uuid/prj.conf
new file mode 100644
index 00000000000..e68bba789fb
--- /dev/null
+++ b/samples/subsys/uuid/prj.conf
@@ -0,0 +1,13 @@
+CONFIG_UUID=y
+CONFIG_UUID_V5=y
+CONFIG_UUID_V4=y
+CONFIG_UUID_BASE64=y
+
+CONFIG_ENTROPY_GENERATOR=y
+
+CONFIG_MBEDTLS=y
+CONFIG_MBEDTLS_MD=y
+CONFIG_MBEDTLS_SHA1=y
+CONFIG_BASE64=y
+
+CONFIG_LOG=y
diff --git a/samples/subsys/uuid/sample.yaml b/samples/subsys/uuid/sample.yaml
new file mode 100644
index 00000000000..b8ec922c994
--- /dev/null
+++ b/samples/subsys/uuid/sample.yaml
@@ -0,0 +1,17 @@
+sample:
+  name: UUID
+tests:
+  sample.subsys.uuid:
+    tags: uuid
+    platform_allow:
+      - qemu_x86
+      - native_sim
+      - native_sim/native/64
+    integration_platforms:
+      - native_sim
+    filter: CONFIG_ENTROPY_HAS_DRIVER
+    harness: console
+    harness_config:
+      type: one_line
+      regex:
+        - "UUID sample completed successfully"
diff --git a/samples/subsys/uuid/src/main.c b/samples/subsys/uuid/src/main.c
new file mode 100644
index 00000000000..436e790e562
--- /dev/null
+++ b/samples/subsys/uuid/src/main.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2025, SECO Mind Srl
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/sys/uuid.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(uuid_sample, LOG_LEVEL_INF);
+
+int main(void)
+{
+	int result;
+	struct uuid uuid_v4 = {0};
+	struct uuid uuid_v5_namespace = {0};
+	struct uuid uuid_v5 = {0};
+	char uuid_v4_str[UUID_STR_LEN] = {0};
+	char uuid_v5_str[UUID_STR_LEN] = {0};
+	char uuid_v4_base64[UUID_BASE64_LEN] = {0};
+	char uuid_v4_base64url[UUID_BASE64URL_LEN] = {0};
+
+	/* Generate an UUID v4 from pseudo-random data */
+	result = uuid_generate_v4(&uuid_v4);
+	if (result != 0) {
+		LOG_ERR("UUID v4 generation failed, error: %s (%d)", strerror(result), result);
+		return -1;
+	}
+	/* Convert the UUID to string and to its base 64 and base 64 URL safe formats */
+	result = uuid_to_string(&uuid_v4, uuid_v4_str);
+	if (result != 0) {
+		LOG_ERR("UUID v4 to string failed, error: %s (%d)", strerror(result), result);
+		return -1;
+	}
+	LOG_INF("UUID v4: '%s'", uuid_v4_str);
+	result = uuid_to_base64(&uuid_v4, uuid_v4_base64);
+	if (result != 0) {
+		LOG_ERR("UUID v4 to base 64 failed, error: %s (%d)", strerror(result), result);
+		return -1;
+	}
+	LOG_INF("UUID v4 base 64: '%s'", uuid_v4_base64);
+	result = uuid_to_base64url(&uuid_v4, uuid_v4_base64url);
+	if (result != 0) {
+		LOG_ERR("UUID v4 to base 64 URL safe failed, error: %s (%d)", strerror(result),
+			result);
+		return -1;
+	}
+	LOG_INF("UUID v4 base 64 URL safe: '%s'", uuid_v4_base64url);
+
+	/* Generate an UUID v5 */
+	/* This UUID is the same as in RFC 9562 Appendix A.4: "Example of a UUIDv5 Value" */
+	result = uuid_from_string("6ba7b810-9dad-11d1-80b4-00c04fd430c8", &uuid_v5_namespace);
+	if (result != 0) {
+		LOG_ERR("Namespace string to UUID failed, error: %s (%d)", strerror(result),
+			result);
+		return -1;
+	}
+	result = uuid_generate_v5(&uuid_v5_namespace, "www.example.com", strlen("www.example.com"),
+				  &uuid_v5);
+	if (result != 0) {
+		LOG_ERR("UUID v5 generation failed, error: %s (%d)", strerror(result), result);
+		return -1;
+	}
+	result = uuid_to_string(&uuid_v5, uuid_v5_str);
+	if (result != 0) {
+		LOG_ERR("UUID v4 to string failed, error: %s (%d)", strerror(result), result);
+		return -1;
+	}
+	LOG_INF("UUID v5: '%s'", uuid_v5_str);
+
+	LOG_INF("UUID sample completed successfully");
+
+	return 0;
+}
diff --git a/samples/subsys/zbus/remote_mock/boards/native_sim.conf b/samples/subsys/zbus/remote_mock/boards/native_sim.conf
index f328c599f26..0843e94acbd 100644
--- a/samples/subsys/zbus/remote_mock/boards/native_sim.conf
+++ b/samples/subsys/zbus/remote_mock/boards/native_sim.conf
@@ -1,2 +1 @@
-CONFIG_UART_NATIVE_POSIX_PORT_1_ENABLE=y
 CONFIG_NATIVE_SIM_SLOWDOWN_TO_REAL_TIME=y
diff --git a/samples/subsys/zbus/remote_mock/boards/native_sim.overlay b/samples/subsys/zbus/remote_mock/boards/native_sim.overlay
new file mode 100644
index 00000000000..c49b63d8e4b
--- /dev/null
+++ b/samples/subsys/zbus/remote_mock/boards/native_sim.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+&uart1 {
+	status = "okay";
+};
diff --git a/samples/subsys/zbus/runtime_obs_registration/src/main.c b/samples/subsys/zbus/runtime_obs_registration/src/main.c
index f389d61c706..8f66f3644e1 100644
--- a/samples/subsys/zbus/runtime_obs_registration/src/main.c
+++ b/samples/subsys/zbus/runtime_obs_registration/src/main.c
@@ -44,10 +44,11 @@ int main(void)
 	LOG_INF("System started");
 
 	const struct zbus_channel *chan;
+	struct zbus_observer_node obs_node;
 
 	while (1) {
 		LOG_INF("Activating filter");
-		zbus_chan_add_obs(&raw_data_chan, &filter_lis, K_MSEC(200));
+		zbus_chan_add_obs(&raw_data_chan, &filter_lis, &obs_node, K_MSEC(200));
 
 		zbus_sub_wait(&state_change_sub, &chan, K_FOREVER);
 
@@ -55,7 +56,7 @@ int main(void)
 		zbus_chan_rm_obs(&raw_data_chan, &filter_lis, K_MSEC(200));
 
 		LOG_INF("Bypass filter");
-		zbus_chan_add_obs(&raw_data_chan, &consumer_sub, K_MSEC(200));
+		zbus_chan_add_obs(&raw_data_chan, &consumer_sub, &obs_node, K_MSEC(200));
 
 		zbus_sub_wait(&state_change_sub, &chan, K_FOREVER);
 
diff --git a/samples/subsys/zbus/uart_bridge/boards/native_posix.conf b/samples/subsys/zbus/uart_bridge/boards/native_posix.conf
deleted file mode 100644
index b552360756c..00000000000
--- a/samples/subsys/zbus/uart_bridge/boards/native_posix.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_UART_NATIVE_POSIX_PORT_1_ENABLE=y
diff --git a/samples/subsys/zbus/uart_bridge/boards/native_posix_native_64.conf b/samples/subsys/zbus/uart_bridge/boards/native_posix_native_64.conf
deleted file mode 100644
index b552360756c..00000000000
--- a/samples/subsys/zbus/uart_bridge/boards/native_posix_native_64.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_UART_NATIVE_POSIX_PORT_1_ENABLE=y
diff --git a/samples/subsys/zbus/uart_bridge/boards/native_sim.conf b/samples/subsys/zbus/uart_bridge/boards/native_sim.conf
deleted file mode 100644
index b552360756c..00000000000
--- a/samples/subsys/zbus/uart_bridge/boards/native_sim.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_UART_NATIVE_POSIX_PORT_1_ENABLE=y
diff --git a/samples/subsys/zbus/uart_bridge/boards/native_sim.overlay b/samples/subsys/zbus/uart_bridge/boards/native_sim.overlay
new file mode 100644
index 00000000000..c49b63d8e4b
--- /dev/null
+++ b/samples/subsys/zbus/uart_bridge/boards/native_sim.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+&uart1 {
+	status = "okay";
+};
diff --git a/samples/subsys/zbus/uart_bridge/boards/native_sim_native_64.conf b/samples/subsys/zbus/uart_bridge/boards/native_sim_native_64.conf
deleted file mode 100644
index b552360756c..00000000000
--- a/samples/subsys/zbus/uart_bridge/boards/native_sim_native_64.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_UART_NATIVE_POSIX_PORT_1_ENABLE=y
diff --git a/samples/subsys/zbus/uart_bridge/boards/native_sim_native_64.overlay b/samples/subsys/zbus/uart_bridge/boards/native_sim_native_64.overlay
new file mode 100644
index 00000000000..0b47ddd4332
--- /dev/null
+++ b/samples/subsys/zbus/uart_bridge/boards/native_sim_native_64.overlay
@@ -0,0 +1,6 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "native_sim.overlay"
diff --git a/samples/sysbuild/hello_world/README.rst b/samples/sysbuild/hello_world/README.rst
index 611d4a4781e..d16f0fa51c6 100644
--- a/samples/sysbuild/hello_world/README.rst
+++ b/samples/sysbuild/hello_world/README.rst
@@ -30,7 +30,7 @@ to boot a remote core.
    ``-T`` option.
 
 Here's an example to build and flash the sample for the
-:ref:`nrf54h20dk_nrf54h20`, using application and radio cores:
+:zephyr:board:`nrf54h20dk`, using application and radio cores:
 
 .. zephyr-app-commands::
    :zephyr-app: samples/sysbuild/hello_world
diff --git a/samples/sysbuild/hello_world/sample.yaml b/samples/sysbuild/hello_world/sample.yaml
index 68eae58739c..cbc58e2a336 100644
--- a/samples/sysbuild/hello_world/sample.yaml
+++ b/samples/sysbuild/hello_world/sample.yaml
@@ -48,8 +48,10 @@ tests:
   sample.sysbuild.hello_world.nrf54l15dk_nrf54l15_cpuflpr:
     platform_allow:
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     extra_args:
 
       - SB_CONF_FILE=sysbuild/nrf54l15dk_nrf54l15_cpuflpr.conf
@@ -71,3 +73,19 @@ tests:
     extra_args:
       - SB_CONF_FILE=sysbuild/nrf54h20dk_nrf54h20_cpuflpr_xip.conf
       - hello_world_SNIPPET=nordic-flpr-xip
+  sample.sysbuild.hello_world.bl54l15_dvk_nrf54l15_cpuflpr:
+    platform_allow:
+      - bl54l15_dvk/nrf54l15/cpuapp
+    integration_platforms:
+      - bl54l15_dvk/nrf54l15/cpuapp
+    extra_args:
+      - SB_CONF_FILE=sysbuild/bl54l15_dvk_nrf54l15_cpuflpr.conf
+      - hello_world_SNIPPET=nordic-flpr
+  sample.sysbuild.hello_world.bl54l15u_dvk_nrf54l15_cpuflpr:
+    platform_allow:
+      - bl54l15u_dvk/nrf54l15/cpuapp
+    integration_platforms:
+      - bl54l15u_dvk/nrf54l15/cpuapp
+    extra_args:
+      - SB_CONF_FILE=sysbuild/bl54l15u_dvk_nrf54l15_cpuflpr.conf
+      - hello_world_SNIPPET=nordic-flpr
diff --git a/samples/sysbuild/hello_world/sysbuild/bl54l15_dvk_nrf54l15_cpuflpr.conf b/samples/sysbuild/hello_world/sysbuild/bl54l15_dvk_nrf54l15_cpuflpr.conf
new file mode 100644
index 00000000000..e8014484067
--- /dev/null
+++ b/samples/sysbuild/hello_world/sysbuild/bl54l15_dvk_nrf54l15_cpuflpr.conf
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+#
+# SPDX-License-Identifier: Apache-2.0
+
+SB_CONFIG_REMOTE_BOARD="bl54l15_dvk/nrf54l15/cpuflpr"
diff --git a/samples/sysbuild/hello_world/sysbuild/bl54l15u_dvk_nrf54l15_cpuflpr.conf b/samples/sysbuild/hello_world/sysbuild/bl54l15u_dvk_nrf54l15_cpuflpr.conf
new file mode 100644
index 00000000000..927961f56e3
--- /dev/null
+++ b/samples/sysbuild/hello_world/sysbuild/bl54l15u_dvk_nrf54l15_cpuflpr.conf
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+#
+# SPDX-License-Identifier: Apache-2.0
+
+SB_CONFIG_REMOTE_BOARD="bl54l15u_dvk/nrf54l15/cpuflpr"
diff --git a/samples/sysbuild/with_mcuboot/CMakeLists.txt b/samples/sysbuild/with_mcuboot/CMakeLists.txt
index ca0a689a6d9..41a45be011a 100644
--- a/samples/sysbuild/with_mcuboot/CMakeLists.txt
+++ b/samples/sysbuild/with_mcuboot/CMakeLists.txt
@@ -5,7 +5,7 @@ cmake_minimum_required(VERSION 3.20.0)
 find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
 project(sample_with_mcuboot)
 
-# Verify that this samnple is built through sysbuild to ensure MCUboot is
+# Verify that this sample is built through sysbuild to ensure MCUboot is
 # automatically included and that sample specific MCUboot configurations are
 # used when building MCUboot.
 test_sysbuild()
diff --git a/samples/sysbuild/with_mcuboot/sample.yaml b/samples/sysbuild/with_mcuboot/sample.yaml
index 2478fa9df34..0348b74dfe3 100644
--- a/samples/sysbuild/with_mcuboot/sample.yaml
+++ b/samples/sysbuild/with_mcuboot/sample.yaml
@@ -13,14 +13,14 @@ tests:
       - esp32s2_devkitc
       - esp32s3_devkitm/esp32s3/procpu
       - esp32c3_devkitm
-      - esp32c6_devkitc
+      - esp32c6_devkitc/esp32c6/hpcore
     integration_platforms:
       - nrf52840dk/nrf52840
       - esp32_devkitc_wrover/esp32/procpu
       - esp32s2_devkitc
       - esp32s3_devkitm/esp32s3/procpu
       - esp32c3_devkitm
-      - esp32c6_devkitc
+      - esp32c6_devkitc/esp32c6/hpcore
     tags: mcuboot
     harness: console
     harness_config:
diff --git a/samples/tfm_integration/config_build/sample.yaml b/samples/tfm_integration/config_build/sample.yaml
index f57da72a379..3c46c148f7b 100644
--- a/samples/tfm_integration/config_build/sample.yaml
+++ b/samples/tfm_integration/config_build/sample.yaml
@@ -9,6 +9,7 @@ common:
     - nrf5340dk/nrf5340/cpuapp/ns
     - nrf9160dk/nrf9160/ns
     - nrf54l15dk/nrf54l15/cpuapp/ns
+    - nrf54l15dk/nrf54l10/cpuapp/ns
     - bl5340_dvk/nrf5340/cpuapp/ns
   integration_platforms:
     - nrf5340dk/nrf5340/cpuapp/ns
diff --git a/samples/tfm_integration/psa_crypto/prj.conf b/samples/tfm_integration/psa_crypto/prj.conf
index ad9de1f0797..1d5024f1242 100644
--- a/samples/tfm_integration/psa_crypto/prj.conf
+++ b/samples/tfm_integration/psa_crypto/prj.conf
@@ -39,6 +39,10 @@ CONFIG_MBEDTLS_ENTROPY_C=y
 CONFIG_MBEDTLS_ECP_C=y
 CONFIG_MBEDTLS_ECP_DP_SECP256R1_ENABLED=y
 CONFIG_MBEDTLS_ECDSA_C=y
+CONFIG_MBEDTLS_MD=y
+CONFIG_MBEDTLS_RSA_C=y
+CONFIG_MBEDTLS_PKCS1_V15=y
+CONFIG_MBEDTLS_PKCS1_V21=y
 CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_ENABLED=y
 CONFIG_MBEDTLS_PK_WRITE_C=y
 
diff --git a/samples/tfm_integration/tfm_ipc/sample.yaml b/samples/tfm_integration/tfm_ipc/sample.yaml
index fb0acbdd988..390efa24fb7 100644
--- a/samples/tfm_integration/tfm_ipc/sample.yaml
+++ b/samples/tfm_integration/tfm_ipc/sample.yaml
@@ -34,6 +34,7 @@ tests:
     platform_allow:
       - mps2/an521/cpu0/ns
       - nrf54l15dk/nrf54l15/cpuapp/ns
+      - nrf54l15dk/nrf54l10/cpuapp/ns
     extra_configs:
       - CONFIG_TFM_BL2=n
     harness: console
diff --git a/samples/tfm_integration/tfm_psa_test/sample.yaml b/samples/tfm_integration/tfm_psa_test/sample.yaml
index d924e704618..2d7c7d1c0c2 100644
--- a/samples/tfm_integration/tfm_psa_test/sample.yaml
+++ b/samples/tfm_integration/tfm_psa_test/sample.yaml
@@ -10,7 +10,6 @@ common:
     - v2m_musca_s1/musca_s1/ns
   modules:
     - psa-arch-tests
-    - tf-m-tests
   integration_platforms:
     - mps2/an521/cpu0/ns
   harness: console
diff --git a/samples/tfm_integration/tfm_regression_test/sample.yaml b/samples/tfm_integration/tfm_regression_test/sample.yaml
index 61af265e77b..30d29f35c95 100644
--- a/samples/tfm_integration/tfm_regression_test/sample.yaml
+++ b/samples/tfm_integration/tfm_regression_test/sample.yaml
@@ -3,7 +3,7 @@ common:
     - trusted-firmware-m
     - mcuboot
   modules:
-    - psa-arch-tests
+    - tf-m-tests
   platform_allow:
     - nrf5340dk/nrf5340/cpuapp/ns
     - nrf9160dk/nrf9160/ns
diff --git a/samples/userspace/prod_consumer/src/sample_driver_foo.c b/samples/userspace/prod_consumer/src/sample_driver_foo.c
index 929ff6c1e00..c84efe94589 100644
--- a/samples/userspace/prod_consumer/src/sample_driver_foo.c
+++ b/samples/userspace/prod_consumer/src/sample_driver_foo.c
@@ -65,7 +65,7 @@ static int sample_driver_foo_state_set(const struct device *dev, bool active)
 	return 0;
 }
 
-static struct sample_driver_api sample_driver_foo_api = {
+static DEVICE_API(sample, sample_driver_foo_api) = {
 	.write = sample_driver_foo_write,
 	.set_callback = sample_driver_foo_set_callback,
 	.state_set = sample_driver_foo_state_set
diff --git a/samples/userspace/shared_mem/sample.yaml b/samples/userspace/shared_mem/sample.yaml
index e53d93490fd..19749ed7cef 100644
--- a/samples/userspace/shared_mem/sample.yaml
+++ b/samples/userspace/shared_mem/sample.yaml
@@ -21,5 +21,7 @@ tests:
       - cy8cproto_062_4343w
       - cy8cproto_063_ble
       - ucans32k1sic
+      - mimxrt700_evk/mimxrt798s/cm33_cpu0
+      - mimxrt700_evk/mimxrt798s/cm33_cpu1
     extra_configs:
       - CONFIG_TEST_HW_STACK_PROTECTION=n
diff --git a/scripts/build/elf_parser.py b/scripts/build/elf_parser.py
old mode 100644
new mode 100755
diff --git a/scripts/build/file2hex.py b/scripts/build/file2hex.py
index 2bb967cf29d..b6e1acc8c07 100755
--- a/scripts/build/file2hex.py
+++ b/scripts/build/file2hex.py
@@ -1,6 +1,7 @@
 #!/usr/bin/env python3
 #
 # Copyright (c) 2017 Intel Corporation
+# Copyright (c) 2025 Siemens AG
 #
 # SPDX-License-Identifier: Apache-2.0
 
@@ -31,6 +32,8 @@ def parse_args():
     parser.add_argument("-l", "--length", type=lambda x: int(x, 0), default=-1,
                         help="""Length in bytes to read from the input file.
                         Defaults to reading till the end of the input file.""")
+    parser.add_argument("-m", "--format", default="list",
+                        help="Output format: 'list' (default) or 'literal' (string literal)")
     parser.add_argument("-g", "--gzip", action="store_true",
                         help="Compress the file using gzip before output")
     parser.add_argument("-t", "--gzip-mtime", type=int, default=0,
@@ -43,7 +46,11 @@ def parse_args():
 
 
 def get_nice_string(list_or_iterator):
-    return ", ".join("0x" + str(x) for x in list_or_iterator)
+    # Convert into comma separated list form.
+    s = ", ".join("0x" + str(x) for x in list_or_iterator)
+
+    # Format the list to eight values per line.
+    return "\n".join(s[i:i+47] for i in range(0, len(s), 48))
 
 
 def make_hex(chunk):
@@ -52,6 +59,12 @@ def make_hex(chunk):
     print(get_nice_string(hexlist) + ',')
 
 
+def make_string_literal(chunk):
+    hexdata = codecs.encode(chunk, 'hex').decode("utf-8")
+    hexlist = map(''.join, zip(*[iter(hexdata)] * 2))
+    print(''.join("\\x" + str(x) for x in hexlist), end='')
+
+
 def main():
     parse_args()
 
@@ -65,19 +78,41 @@ def main():
                     gz_obj.write(fg.read(args.length))
 
             content.seek(0)
-            for chunk in iter(lambda: content.read(8), b''):
-                make_hex(chunk)
+            if args.format == "literal":
+                print('"', end='')
+                for chunk in iter(lambda: content.read(1024), b''):
+                    make_string_literal(chunk)
+                print('"', end='')
+            else:
+                for chunk in iter(lambda: content.read(1024), b''):
+                    make_hex(chunk)
     else:
         with open(args.file, "rb") as fp:
             fp.seek(args.offset)
-            if args.length < 0:
-                for chunk in iter(lambda: fp.read(8), b''):
-                    make_hex(chunk)
+
+            if args.format == "literal":
+                if args.length < 0:
+                    print('"', end='')
+                    for chunk in iter(lambda: fp.read(1024), b''):
+                        make_string_literal(chunk)
+                    print('"', end='')
+                else:
+                    print('"', end='')
+                    remainder = args.length
+                    for chunk in iter(lambda: fp.read(min(1024, remainder)), b''):
+                        make_string_literal(chunk)
+                        remainder = remainder - len(chunk)
+                    print('"', end='')
+
             else:
-                remainder = args.length
-                for chunk in iter(lambda: fp.read(min(8, remainder)), b''):
-                    make_hex(chunk)
-                    remainder = remainder - len(chunk)
+                if args.length < 0:
+                    for chunk in iter(lambda: fp.read(1024), b''):
+                        make_hex(chunk)
+                else:
+                    remainder = args.length
+                    for chunk in iter(lambda: fp.read(min(1024, remainder)), b''):
+                        make_hex(chunk)
+                        remainder = remainder - len(chunk)
 
 
 if __name__ == "__main__":
diff --git a/scripts/build/gen_app_partitions.py b/scripts/build/gen_app_partitions.py
old mode 100644
new mode 100755
index ec0a4bbfc7e..4a178762afc
--- a/scripts/build/gen_app_partitions.py
+++ b/scripts/build/gen_app_partitions.py
@@ -27,11 +27,148 @@
 - key/value pairs mapping static library files to what partitions their globals
   should end up in.
 
-The output is a linker script fragment containing the definition of the
-app shared memory section, which is further divided, for each partition
-found, into data and BSS for each partition.
+The output is either a linker script fragment or linker-script generator
+fragments containing the definition of the app shared memory section, which
+is further divided, for each partition found, into data and BSS for each
+partition.
 """
 
+#The linker script fragments looks something like this:
+# SECTION_PROLOGUE(_APP_SMEM_SECTION_NAME,,)
+# 	{
+# 		APP_SHARED_ALIGN;
+# 		_app_smem_start = .;
+
+# 		/* Auto generated code do not modify */
+# 		SMEM_PARTITION_ALIGN(z_data_smem_ztest_mem_partition_bss_end - z_data_smem_ztest_mem_partition_part_start);
+# 		z_data_smem_ztest_mem_partition_part_start = .;
+# 		KEEP(*(data_smem_ztest_mem_partition_data*))
+
+# 		z_data_smem_ztest_mem_partition_bss_start = .;
+# 		KEEP(*(data_smem_ztest_mem_partition_bss*))
+
+# 		z_data_smem_ztest_mem_partition_bss_end = .;
+# 		SMEM_PARTITION_ALIGN(z_data_smem_ztest_mem_partition_bss_end - z_data_smem_ztest_mem_partition_part_start);
+# 		z_data_smem_ztest_mem_partition_part_end = .;
+
+# 		/* Auto generated code do not modify */
+# 		SMEM_PARTITION_ALIGN(z_data_smem_z_libc_partition_bss_end - z_data_smem_z_libc_partition_part_start);
+# 		z_data_smem_z_libc_partition_part_start = .;
+# 		KEEP(*(data_smem_z_libc_partition_data*))
+
+# 		z_data_smem_z_libc_partition_bss_start = .;
+# 		KEEP(*(data_smem_z_libc_partition_bss*))
+
+# 		z_data_smem_z_libc_partition_bss_end = .;
+# 		SMEM_PARTITION_ALIGN(z_data_smem_z_libc_partition_bss_end - z_data_smem_z_libc_partition_part_start);
+# 		z_data_smem_z_libc_partition_part_end = .;
+
+# 		APP_SHARED_ALIGN;
+# 		_app_smem_end = .;
+# 	} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
+
+# 	z_data_smem_ztest_mem_partition_part_size = z_data_smem_ztest_mem_partition_part_end - z_data_smem_ztest_mem_partition_part_start;
+# 	z_data_smem_ztest_mem_partition_bss_size = z_data_smem_ztest_mem_partition_bss_end - z_data_smem_ztest_mem_partition_bss_start;
+
+# 	z_data_smem_z_libc_partition_part_size = z_data_smem_z_libc_partition_part_end - z_data_smem_z_libc_partition_part_start;
+# 	z_data_smem_z_libc_partition_bss_size = z_data_smem_z_libc_partition_bss_end - z_data_smem_z_libc_partition_bss_start;
+
+# the linker script generator fragments looks something like this:
+# There is a zephyr_linker_group() called APP_SMEM_GROUP for these sections
+# defined in linker.cmake
+# _APP_SMEM_SECTION_NAME is #defined in sections.h to "app_smem". Ideally we should have that here too.
+#
+# zephyr_linker_section(NAME _APP_SMEM_SECTION_NAME GROUP APP_SMEM_GROUP NOINPUT ALIGN_WITH_INPUT)
+#   zephyr_linker_section_configure(
+#     SECTION
+#     _APP_SMEM_SECTION_NAME
+#     SYMBOLS
+#     _app_smem_start
+#     )
+#   zephyr_linker_section_configure(
+#     SECTION
+#     _APP_SMEM_SECTION_NAME
+#     INPUT
+#     "data_smem_ztest_mem_partition_data*"
+#     KEEP
+#     SYMBOLS
+#     z_data_smem_ztest_mem_partition_part_start
+#     )
+#   zephyr_linker_section_configure(
+#     SECTION
+#     _APP_SMEM_SECTION_NAME
+#     INPUT
+#     "data_smem_ztest_mem_partition_bss*"
+#     KEEP
+#     SYMBOLS
+#     z_data_smem_ztest_mem_partition_bss_start
+#     z_data_smem_ztest_mem_partition_bss_end
+#     )
+#   zephyr_linker_section_configure(
+#     SECTION
+#     _APP_SMEM_SECTION_NAME
+#     SYMBOLS
+#     z_data_smem_ztest_mem_partition_part_end
+#     )
+
+#   zephyr_linker_section_configure(
+#     SECTION
+#     _APP_SMEM_SECTION_NAME
+#     INPUT
+#     "data_smem_z_libc_partition_data*"
+#     KEEP
+#     SYMBOLS
+#     z_data_smem_z_libc_partition_part_start
+#     )
+#   zephyr_linker_section_configure(
+#     SECTION
+#     _APP_SMEM_SECTION_NAME
+#     INPUT
+#     "data_smem_z_libc_partition_bss*"
+#     KEEP
+#     SYMBOLS
+#     z_data_smem_z_libc_partition_bss_start
+#     z_data_smem_z_libc_partition_bss_end
+#     )
+#   zephyr_linker_section_configure(
+#     SECTION
+#     _APP_SMEM_SECTION_NAME
+#     SYMBOLS
+#     z_data_smem_z_libc_partition_part_end
+#     )
+#   zephyr_linker_section_configure(
+#     SECTION
+#     _APP_SMEM_SECTION_NAME
+#     SYMBOLS
+#     _app_smem_end
+#     )
+#   zephyr_linker_symbol(
+#     SYMBOL
+#     z_data_smem_ztest_mem_partition_part_size
+#     EXPR
+#     "(@z_data_smem_ztest_mem_partition_part_end@ - @z_data_smem_ztest_mem_partition_part_start@)"
+#     )
+#   zephyr_linker_symbol(
+#     SYMBOL
+#     z_data_smem_ztest_mem_partition_bss_size
+#     EXPR
+#     "(@z_data_smem_ztest_mem_partition_bss_end@ - @z_data_smem_ztest_mem_partition_bss_start@)"
+#     )
+
+#   zephyr_linker_symbol(
+#     SYMBOL
+#     z_data_smem_z_libc_partition_part_size
+#     EXPR
+#     "(@z_data_smem_z_libc_partition_part_end@ - @z_data_smem_z_libc_partition_part_start@)"
+#     )
+#   zephyr_linker_symbol(
+#     SYMBOL
+#     z_data_smem_z_libc_partition_bss_size
+#     EXPR
+#     "(@z_data_smem_z_libc_partition_bss_end@ - @z_data_smem_z_libc_partition_bss_start@)"
+#     )
+
+
 import sys
 import argparse
 import json
@@ -50,60 +187,133 @@
 # application shared memory partitions.
 # these are later read by the macros defined in app_memdomain.h for
 # initialization purpose when USERSPACE is enabled.
-data_template = """
-		/* Auto generated code do not modify */
-		SMEM_PARTITION_ALIGN(z_data_smem_{0}_bss_end - z_data_smem_{0}_part_start);
-		z_data_smem_{0}_part_start = .;
-		KEEP(*(data_smem_{0}_data*))
-"""
-
-library_data_template = """
-		\"*{0}:*\"(.data .data.* .sdata .sdata.*)
-"""
 
-bss_template = """
-		z_data_smem_{0}_bss_start = .;
-		KEEP(*(data_smem_{0}_bss*))
-"""
-
-library_bss_template = """
-		\"*{0}:*\"(.bss .bss.* .sbss .sbss.* COMMON COMMON.*)
-"""
-
-footer_template = """
-		z_data_smem_{0}_bss_end = .;
-		SMEM_PARTITION_ALIGN(z_data_smem_{0}_bss_end - z_data_smem_{0}_part_start);
-		z_data_smem_{0}_part_end = .;
-"""
-
-linker_start_seq = """
-	SECTION_PROLOGUE(_APP_SMEM{1}_SECTION_NAME,,)
-	{{
-		APP_SHARED_ALIGN;
-		_app_smem{0}_start = .;
-"""
-
-linker_end_seq = """
-		APP_SHARED_ALIGN;
-		_app_smem{0}_end = .;
-	}} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
-"""
-
-empty_app_smem = """
-	SECTION_PROLOGUE(_APP_SMEM{1}_SECTION_NAME,,)
-	{{
-#ifdef EMPTY_APP_SHARED_ALIGN
-		EMPTY_APP_SHARED_ALIGN;
-#endif
-		_app_smem{0}_start = .;
-		_app_smem{0}_end = .;
-	}} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
-"""
-
-size_cal_string = """
-	z_data_smem_{0}_part_size = z_data_smem_{0}_part_end - z_data_smem_{0}_part_start;
-	z_data_smem_{0}_bss_size = z_data_smem_{0}_bss_end - z_data_smem_{0}_bss_start;
-"""
+class LDScriptTemlate:
+    data_template = """
+            /* Auto generated code do not modify */
+            SMEM_PARTITION_ALIGN(z_data_smem_{partition}_bss_end - z_data_smem_{partition}_part_start);
+            z_data_smem_{partition}_part_start = .;
+            KEEP(*(data_smem_{partition}_data*))
+    """
+
+    library_data_template = """
+            \"*{lib}:*\"(.data .data.* .sdata .sdata.*)
+    """
+
+    bss_template = """
+            z_data_smem_{partition}_bss_start = .;
+            KEEP(*(data_smem_{partition}_bss*))
+    """
+
+    library_bss_template = """
+            \"*{lib}:*\"(.bss .bss.* .sbss .sbss.* COMMON COMMON.*)
+    """
+
+    footer_template = """
+            z_data_smem_{partition}_bss_end = .;
+            SMEM_PARTITION_ALIGN(z_data_smem_{partition}_bss_end - z_data_smem_{partition}_part_start);
+            z_data_smem_{partition}_part_end = .;
+    """
+
+    linker_start_seq = """
+        SECTION_PROLOGUE(_APP_SMEM{SECTION}_SECTION_NAME,,)
+        {{
+            APP_SHARED_ALIGN;
+            _app_smem{section}_start = .;
+    """
+
+    linker_end_seq = """
+            APP_SHARED_ALIGN;
+            _app_smem{section}_end = .;
+        }} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
+    """
+
+    empty_app_smem = """
+        SECTION_PROLOGUE(_APP_SMEM{SECTION}_SECTION_NAME,,)
+        {{
+    #ifdef EMPTY_APP_SHARED_ALIGN
+            EMPTY_APP_SHARED_ALIGN;
+    #endif
+            _app_smem{section}_start = .;
+            _app_smem{section}_end = .;
+        }} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
+    """
+
+    size_cal_string = """
+        z_data_smem_{partition}_part_size = z_data_smem_{partition}_part_end - z_data_smem_{partition}_part_start;
+        z_data_smem_{partition}_bss_size = z_data_smem_{partition}_bss_end - z_data_smem_{partition}_bss_start;
+    """
+
+def cmake_list_append(list, props):
+    tokens = [fr"{key}\;{value}" for key, value in props.items()]
+    stuff = r"\;".join(tokens)
+    return """list(APPEND """+ list + """ \"{{""" + stuff + """}}\")\n"""
+
+def zephyr_linker_section(name, group, align = None, noinput = True, align_with_input = True, hidden = False, noinit = False):
+    props = {"""NAME""": name, """GROUP""": group}
+    if align :
+        props['ALIGN'] = align
+    #The bool flags are always there:
+    props['NOIPUT'] = noinput
+    props['ALIGN_WITH_INPUT'] = align_with_input
+    props['HIDDEN'] = hidden
+    props['NOINIT'] = noinit
+    return cmake_list_append("SECTIONS", props)
+
+def zephyr_linker_section_configure(section, input = None, symbols = None, align = None, any = False, first = False, keep = False):
+    props = {"SECTION": section}
+    if input:
+        props["INPUT"] = input
+    #ANY\;FALSE\;FIRST\;FALSE\;KEEP\;FALSE\
+    props['ANY'] = any
+    props['FIRST'] = first
+    props['KEEP'] = keep
+    if symbols:
+        props["SYMBOLS"] = symbols
+    if align:
+        props["ALIGN"] = align
+    return cmake_list_append("SECTION_SETTINGS", props)
+
+def zephyr_linker_symbol(symbol, expr) :
+    return cmake_list_append("SYMBOLS", {'SYMBOL': symbol, 'EXPR':expr})
+
+class CmakeTemplate:
+    section_name = "@_APP_SMEM{SECTION}_SECTION_NAME@"
+    data_template = (
+        zephyr_linker_section_configure(section=section_name, align="@SMEM_PARTITION_ALIGN_BYTES@")+
+        zephyr_linker_section_configure(section=section_name, input="data_smem_{partition}_data*", symbols="z_data_smem_{partition}_part_start", keep=True)
+    )
+
+    library_data_template = zephyr_linker_section_configure(section=section_name, input="*{lib}:*(.data .data.* .sdata .sdata.*)")
+
+    bss_template = (
+        zephyr_linker_section_configure(section=section_name, input="data_smem_{partition}_bss*", symbols="z_data_smem_{partition}_bss_start", keep=True)
+    )
+
+    library_bss_template = zephyr_linker_section_configure(section=section_name, input="*{lib}:*(.bss .bss.* .sbss .sbss.* COMMON COMMON.*)")
+
+    footer_template = (
+        zephyr_linker_section_configure(section=section_name, symbols="z_data_smem_{partition}_bss_end", keep=True) +
+        zephyr_linker_section_configure(section=section_name, align="@SMEM_PARTITION_ALIGN_BYTES@") +
+        zephyr_linker_section_configure(section=section_name, symbols="z_data_smem_{partition}_part_end", keep=True)
+    )
+
+    linker_start_seq = (
+        zephyr_linker_section(name=section_name, group="APP_SMEM_GROUP", noinput=True, align_with_input=True) +
+        zephyr_linker_section_configure(section=section_name, align="@APP_SHARED_ALIGN_BYTES@", symbols="_app_smem{section}_start"))
+
+    linker_end_seq = (
+        zephyr_linker_section_configure(section=section_name, align="@APP_SHARED_ALIGN_BYTES@") +
+        zephyr_linker_section_configure(section=section_name, symbols="_app_smem{section}_end") )
+
+    empty_app_smem = (
+        zephyr_linker_section(name=section_name, group="APP_SMEM_GROUP", align="@APP_SHARED_ALIGN_BYTES@", noinput=True, align_with_input=True) +
+        zephyr_linker_section_configure(section = section_name, symbols="_app_smem{section}_start") +
+        zephyr_linker_section_configure(section = section_name, symbols="_app_smem{section}_end") )
+
+    size_cal_string = (
+        zephyr_linker_symbol(symbol='z_data_smem_{partition}_part_size', expr='@z_data_smem_{partition}_part_end@ - @z_data_smem_{partition}_part_start@') +
+        zephyr_linker_symbol(symbol='z_data_smem_{partition}_bss_size', expr='@z_data_smem_{partition}_bss_end@ - @z_data_smem_{partition}_bss_start@'))
 
 section_regex = re.compile(r'data_smem_([A-Za-z0-9_]*)_(data|bss)*')
 
@@ -200,34 +410,45 @@ def parse_elf_file(partitions):
                 else:
                     partitions[partition_name][SZ] += size
 
+def generate_final(linker_file, partitions, lnkr_sect=""):
+    if linker_file.endswith(".ld"):
+        template = LDScriptTemlate
+    else:
+        template = CmakeTemplate
+    generate_final_linker(template, linker_file, partitions, lnkr_sect)
 
-def generate_final_linker(linker_file, partitions, lnkr_sect=""):
+def generate_final_linker(template, linker_file, partitions, lnkr_sect):
     string = ""
-
+    props = { 'section' : lnkr_sect, 'SECTION' : lnkr_sect.upper() }
     if len(partitions) > 0:
-        string = linker_start_seq.format(lnkr_sect, lnkr_sect.upper())
+        string = template.linker_start_seq.format(**props)
         size_string = ''
         for partition, item in partitions.items():
-            string += data_template.format(partition)
+            part_props = props
+            part_props["partition"] = partition
+            string += template.data_template.format(**part_props)
             if LIB in item:
                 for lib in item[LIB]:
-                    string += library_data_template.format(lib)
-            string += bss_template.format(partition, lnkr_sect)
+                    lib_props = part_props
+                    lib_props["lib"] = lib
+                    string += template.library_data_template.format(**lib_props)
+            string += template.bss_template.format(**part_props)
             if LIB in item:
                 for lib in item[LIB]:
-                    string += library_bss_template.format(lib)
-            string += footer_template.format(partition)
-            size_string += size_cal_string.format(partition)
+                    lib_props = part_props
+                    lib_props["lib"] = lib
+                    string += template.library_bss_template.format(**lib_props)
+            string += template.footer_template.format(**part_props)
+            size_string += template.size_cal_string.format(**part_props)
 
-        string += linker_end_seq.format(lnkr_sect)
+        string += template.linker_end_seq.format(**props)
         string += size_string
     else:
-        string = empty_app_smem.format(lnkr_sect, lnkr_sect.upper())
+        string = template.empty_app_smem.format(**props) #lnkr_sect, lnkr_sect.upper())
 
     with open(linker_file, "w") as fw:
         fw.write(string)
 
-
 def parse_args():
     global args
     parser = argparse.ArgumentParser(
@@ -294,7 +515,8 @@ def main():
 
     partsorted = OrderedDict(decreasing_tuples)
 
-    generate_final_linker(args.output, partsorted)
+    generate_final(args.output, partsorted)
+
     if args.verbose:
         print("Partitions retrieved:")
         for key in partsorted:
@@ -308,7 +530,7 @@ def main():
 
         partsorted = OrderedDict(decreasing_tuples)
 
-        generate_final_linker(args.pinoutput, partsorted, lnkr_sect="_pinned")
+        generate_final(args.pinoutput, partsorted, lnkr_sect="_pinned")
         if args.verbose:
             print("Pinned partitions retrieved:")
             for key in partsorted:
diff --git a/scripts/build/gen_image_info.py b/scripts/build/gen_image_info.py
old mode 100644
new mode 100755
diff --git a/scripts/build/gen_isr_tables_parser_carrays.py b/scripts/build/gen_isr_tables_parser_carrays.py
old mode 100644
new mode 100755
diff --git a/scripts/build/gen_isr_tables_parser_local.py b/scripts/build/gen_isr_tables_parser_local.py
old mode 100644
new mode 100755
diff --git a/scripts/build/gen_iter_sections.py b/scripts/build/gen_iter_sections.py
old mode 100644
new mode 100755
diff --git a/scripts/build/gen_relocate_app.py b/scripts/build/gen_relocate_app.py
old mode 100644
new mode 100755
index 48ef8a4bf95..8baae18c576
--- a/scripts/build/gen_relocate_app.py
+++ b/scripts/build/gen_relocate_app.py
@@ -44,7 +44,6 @@
 
 import sys
 import argparse
-import os
 import glob
 import re
 import warnings
@@ -491,19 +490,18 @@ def parse_args():
                         help="Verbose Output")
     args = parser.parse_args()
 
+def gen_all_obj_files(searchpath):
+    return list(Path(searchpath).rglob('*.o')) + list(Path(searchpath).rglob('*.obj'))
 
 # return the absolute path for the object file.
-def get_obj_filename(searchpath, filename):
+def get_obj_filename(all_obj_files, filename):
     # get the object file name which is almost always pended with .obj
     obj_filename = filename.split("/")[-1] + ".obj"
 
-    for dirpath, _, files in os.walk(searchpath):
-        for filename1 in files:
-            if filename1 == obj_filename:
-                if filename.split("/")[-2] in dirpath.split("/")[-1]:
-                    fullname = os.path.join(dirpath, filename1)
-                    return fullname
-
+    for obj_file in all_obj_files:
+        if obj_file.name == obj_filename:
+            if filename.split("/")[-2] in obj_file.parent.name:
+                return str(obj_file)
 
 # Extracts all possible components for the input string:
 # <mem_region>[\ :program_header]:<flag_1>[;<flag_2>...]:<file_1>[;<file_2>...][,filter]
@@ -587,6 +585,7 @@ def main():
     mpu_align = {}
     parse_args()
     searchpath = args.directory
+    all_obj_files = gen_all_obj_files(searchpath)
     linker_file = args.output
     sram_data_linker_file = args.output_sram_data
     sram_bss_linker_file = args.output_sram_bss
@@ -602,7 +601,7 @@ def main():
         full_list_of_sections: 'dict[SectionKind, list[OutputSection]]' = defaultdict(list)
 
         for filename, symbol_filter in files:
-            obj_filename = get_obj_filename(searchpath, filename)
+            obj_filename = get_obj_filename(all_obj_files, filename)
             # the obj file wasn't found. Probably not compiled.
             if not obj_filename:
                 continue
diff --git a/scripts/build/gen_symtab.py b/scripts/build/gen_symtab.py
old mode 100644
new mode 100755
diff --git a/scripts/build/llext_inject_slids.py b/scripts/build/llext_inject_slids.py
index 19e87edba93..b2f42f0c813 100755
--- a/scripts/build/llext_inject_slids.py
+++ b/scripts/build/llext_inject_slids.py
@@ -36,20 +36,22 @@ def __init__(self, elf_path, log):
         self.elf = ELFFile(self.elf_fd)
 
     def _find_symtab(self):
-        supported_symtab_sections = [
-            ".symtab",
-            ".dynsym",
-        ]
-
-        symtab = None
-        for section_name in supported_symtab_sections:
-            symtab = self.elf.get_section_by_name(section_name)
-            if not isinstance(symtab, SymbolTableSection):
-                self.log.debug(f"section {section_name} not found.")
-            else:
-                self.log.info(f"processing '{section_name}' symbol table...")
-                self.log.debug(f"(symbol table is at file offset 0x{symtab['sh_offset']:X})")
-                break
+        e_type = self.elf.header['e_type']
+        if e_type == 'ET_DYN':
+            symtab_name = ".dynsym"
+        elif e_type == 'ET_REL':
+            symtab_name = ".symtab"
+        else:
+            self.log.error(f"unexpected ELF file type {e_type}")
+            return None
+
+        symtab = self.elf.get_section_by_name(symtab_name)
+        if not isinstance(symtab, SymbolTableSection):
+            self.log.debug(f"section {symtab_name} not found.")
+            return None
+
+        self.log.info(f"processing symbol table from '{symtab_name}'...")
+        self.log.debug(f"(symbol table is at file offset 0x{symtab['sh_offset']:X})")
         return symtab
 
     def _find_imports_in_symtab(self, symtab):
diff --git a/scripts/build/mergehex.py b/scripts/build/mergehex.py
old mode 100644
new mode 100755
diff --git a/scripts/build/parse_syscalls.py b/scripts/build/parse_syscalls.py
old mode 100644
new mode 100755
diff --git a/scripts/build/subfolder_list.py b/scripts/build/subfolder_list.py
old mode 100644
new mode 100755
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 27c1f54e54f..25b09073bdb 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -6050,6 +6050,7 @@ sub process {
 
 # Check for __attribute__ aligned, prefer __aligned
 		if ($realfile !~ m@\binclude/uapi/@ &&
+		    $realfile !~ m@\binclude/zephyr/toolchain@ &&
 		    $line =~ /\b__attribute__\s*\(\s*\(.*aligned/) {
 			WARN("PREFER_ALIGNED",
 			     "__aligned(size) is preferred over __attribute__((aligned(size)))\n" . $herecurr);
@@ -6565,9 +6566,10 @@ sub process {
 		}
 
 # check for uses of __BYTE_ORDER__
-		while ($line =~ /\b(__BYTE_ORDER__)\b/g) {
-			ERROR("BYTE_ORDER",
-			      "Use of the '$1' macro is disallowed. Use CONFIG_(BIG|LITTLE)_ENDIAN instead\n" . $herecurr);
+		while ($realfile !~ m@^include/zephyr/toolchain@ &&
+		       $line =~ /\b(__BYTE_ORDER__)\b/g) {
+				ERROR("BYTE_ORDER",
+				      "Use of the '$1' macro is disallowed. Use CONFIG_(BIG|LITTLE)_ENDIAN instead\n" . $herecurr);
 		}
 
 # check for use of yield()
diff --git a/scripts/checkpatch/typedefsfile b/scripts/checkpatch/typedefsfile
index 0fc22b9779b..ad569c5e330 100644
--- a/scripts/checkpatch/typedefsfile
+++ b/scripts/checkpatch/typedefsfile
@@ -2,7 +2,6 @@ _cpu_arch_t
 k_mem_partition_attr_t
 k_timepoint_t
 mbedtls_pk_context
-z_arch_esf_t
 pinctrl_soc_pin_t
 io_rw_32
 \b[a-zA-Z_][a-zA-Z0-9_]*TypeDef
diff --git a/scripts/ci/check_compliance.py b/scripts/ci/check_compliance.py
index c311b3f7265..a36374e0ab0 100755
--- a/scripts/ci/check_compliance.py
+++ b/scripts/ci/check_compliance.py
@@ -6,7 +6,6 @@
 
 import argparse
 import collections
-from email.utils import parseaddr
 from itertools import takewhile
 import json
 import logging
@@ -76,11 +75,47 @@ def get_files(filter=None, paths=None):
     out = git('diff', '--name-only', *filter_arg, COMMIT_RANGE, *paths_arg)
     files = out.splitlines()
     for file in list(files):
-        if not os.path.isfile(os.path.join(GIT_TOP, file)):
+        if not (GIT_TOP / file).exists():
             # Drop submodule directories from the list.
             files.remove(file)
     return files
 
+def get_module_setting_root(root, settings_file):
+    """
+    Parse the Zephyr module generated settings file given by 'settings_file'
+    and return all root settings defined by 'root'.
+    """
+    # Invoke the script directly using the Python executable since this is
+    # not a module nor a pip-installed Python utility
+    root_paths = []
+
+    if os.path.exists(settings_file):
+        with open(settings_file, 'r') as fp_setting_file:
+            content = fp_setting_file.read()
+
+        lines = content.strip().split('\n')
+        for line in lines:
+            root = root.upper()
+            if line.startswith(f'"{root}_ROOT":'):
+                _, root_path = line.split(":", 1)
+                root_paths.append(Path(root_path.strip('"')))
+    return root_paths
+
+def get_vendor_prefixes(path, errfn = print) -> set[str]:
+    vendor_prefixes = set()
+    with open(path) as fp:
+        for line in fp.readlines():
+            line = line.strip()
+            if not line or line.startswith("#"):
+                continue
+            try:
+                vendor, _ = line.split("\t", 2)
+                vendor_prefixes.add(vendor)
+            except ValueError:
+                errfn(f"Invalid line in {path}:\"{line}\".")
+                errfn("Did you forget the tab character?")
+    return vendor_prefixes
+
 class FmtdFailure(Failure):
     def __init__(
         self, severity, title, file, line=None, col=None, desc="", end_line=None, end_col=None
@@ -121,19 +156,21 @@ class ComplianceTest:
       Link to documentation related to what's being tested
 
     path_hint:
-      The path the test runs itself in. This is just informative and used in
-      the message that gets printed when running the test.
-
-      There are two magic strings that can be used instead of a path:
-      - The magic string "<zephyr-base>" can be used to refer to the
-      environment variable ZEPHYR_BASE or, when missing, the calculated base of
-      the zephyr tree
-      - The magic string "<git-top>" refers to the top-level repository
-      directory. This avoids running 'git' to find the top-level directory
-      before main() runs (class variable assignments run when the 'class ...'
-      statement runs). That avoids swallowing errors, because main() reports
-      them to GitHub
+      The path the test runs itself in. By default it uses the magic string
+      "<git-top>" which refers to the top-level repository directory.
+
+      This avoids running 'git' to find the top-level directory before main()
+      runs (class variable assignments run when the 'class ...' statement
+      runs). That avoids swallowing errors, because main() reports them to
+      GitHub.
+
+      Subclasses may override the default with a specific path or one of the
+      magic strings below:
+      - "<zephyr-base>" can be used to refer to the environment variable
+        ZEPHYR_BASE or, when missing, the calculated base of the zephyr tree.
     """
+    path_hint = "<git-top>"
+
     def __init__(self):
         self.case = TestCase(type(self).name, "Guidelines")
         # This is necessary because Failure can be subclassed, but since it is
@@ -205,23 +242,35 @@ class CheckPatch(ComplianceTest):
     """
     name = "Checkpatch"
     doc = "See https://docs.zephyrproject.org/latest/contribute/guidelines.html#coding-style for more details."
-    path_hint = "<git-top>"
 
     def run(self):
-        checkpatch = os.path.join(ZEPHYR_BASE, 'scripts', 'checkpatch.pl')
-        if not os.path.exists(checkpatch):
+        checkpatch = ZEPHYR_BASE / 'scripts' / 'checkpatch.pl'
+        if not checkpatch.exists():
             self.skip(f'{checkpatch} not found')
 
+        # check for Perl installation on Windows
+        if os.name == 'nt':
+            if not shutil.which('perl'):
+                self.failure("Perl not installed - required for checkpatch.pl. Please install Perl or add to PATH.")
+                return
+            else:
+                cmd = ['perl', checkpatch]
+
+        # Linux and MacOS
+        else:
+            cmd = [checkpatch]
+
+        cmd.extend(['--mailback', '--no-tree', '-'])
         diff = subprocess.Popen(('git', 'diff', '--no-ext-diff', COMMIT_RANGE),
                                 stdout=subprocess.PIPE,
                                 cwd=GIT_TOP)
         try:
-            subprocess.run((checkpatch, '--mailback', '--no-tree', '-'),
+            subprocess.run(cmd,
                            check=True,
                            stdin=diff.stdout,
                            stdout=subprocess.PIPE,
                            stderr=subprocess.STDOUT,
-                           shell=True, cwd=GIT_TOP)
+                           shell=False, cwd=GIT_TOP)
 
         except subprocess.CalledProcessError as ex:
             output = ex.output.decode("utf-8")
@@ -251,7 +300,6 @@ class BoardYmlCheck(ComplianceTest):
     """
     name = "BoardYml"
     doc = "Check the board.yml file format"
-    path_hint = "<zephyr-base>"
 
     def check_board_file(self, file, vendor_prefixes):
         """Validate a single board file."""
@@ -266,20 +314,19 @@ def check_board_file(self, file, vendor_prefixes):
                                           desc=desc)
 
     def run(self):
-        vendor_prefixes = ["others"]
-        with open(os.path.join(ZEPHYR_BASE, "dts", "bindings", "vendor-prefixes.txt")) as fp:
-            for line in fp.readlines():
-                line = line.strip()
-                if not line or line.startswith("#"):
-                    continue
-                try:
-                    vendor, _ = line.split("\t", 2)
-                    vendor_prefixes.append(vendor)
-                except ValueError:
-                    self.error(f"Invalid line in vendor-prefixes.txt:\"{line}\".")
-                    self.error("Did you forget the tab character?")
-
-        path = Path(ZEPHYR_BASE)
+        path = resolve_path_hint(self.path_hint)
+
+        vendor_prefixes = {"others"}
+        # add vendor prefixes from the main zephyr repo
+        vendor_prefixes |= get_vendor_prefixes(ZEPHYR_BASE / "dts" / "bindings" / "vendor-prefixes.txt", self.error)
+
+        # add vendor prefixes from the current repo
+        dts_roots = get_module_setting_root('dts', path / "zephyr" / "module.yml")
+        for dts_root in dts_roots:
+            vendor_prefix_file = dts_root / "dts" / "bindings" / "vendor-prefixes.txt"
+            if vendor_prefix_file.exists():
+                vendor_prefixes |= get_vendor_prefixes(vendor_prefix_file, self.error)
+
         for file in path.glob("**/board.yml"):
             self.check_board_file(file, vendor_prefixes)
 
@@ -290,7 +337,6 @@ class ClangFormatCheck(ComplianceTest):
     """
     name = "ClangFormat"
     doc = "See https://docs.zephyrproject.org/latest/contribute/guidelines.html#clang-format for more details."
-    path_hint = "<git-top>"
 
     def run(self):
         exe = f"clang-format-diff.{'exe' if platform.system() == 'Windows' else 'py'}"
@@ -332,7 +378,6 @@ class DevicetreeBindingsCheck(ComplianceTest):
     """
     name = "DevicetreeBindings"
     doc = "See https://docs.zephyrproject.org/latest/build/dts/bindings.html for more details."
-    path_hint = "<zephyr-base>"
 
     def run(self, full=True):
         dts_bindings = self.parse_dt_bindings()
@@ -369,12 +414,15 @@ class KconfigCheck(ComplianceTest):
     """
     name = "Kconfig"
     doc = "See https://docs.zephyrproject.org/latest/build/kconfig/tips.html for more details."
-    path_hint = "<zephyr-base>"
 
-    def run(self, full=True, no_modules=False, filename="Kconfig", hwm=None):
-        self.no_modules = no_modules
+    # Top-level Kconfig file. The path can be relative to srctree (ZEPHYR_BASE).
+    FILENAME = "Kconfig"
 
-        kconf = self.parse_kconfig(filename=filename, hwm=hwm)
+    # Kconfig symbol prefix/namespace.
+    CONFIG_ = "CONFIG_"
+
+    def run(self):
+        kconf = self.parse_kconfig()
 
         self.check_top_menu_not_too_long(kconf)
         self.check_no_pointless_menuconfigs(kconf)
@@ -382,10 +430,10 @@ def run(self, full=True, no_modules=False, filename="Kconfig", hwm=None):
         self.check_no_redefined_in_defconfig(kconf)
         self.check_no_enable_in_boolean_prompt(kconf)
         self.check_soc_name_sync(kconf)
-        if full:
-            self.check_no_undef_outside_kconfig(kconf)
+        self.check_no_undef_outside_kconfig(kconf)
+        self.check_disallowed_defconfigs(kconf)
 
-    def get_modules(self, modules_file, settings_file):
+    def get_modules(self, modules_file, sysbuild_modules_file, settings_file):
         """
         Get a list of modules and put them in a file that is parsed by
         Kconfig
@@ -393,26 +441,22 @@ def get_modules(self, modules_file, settings_file):
         This is needed to complete Kconfig sanity tests.
 
         """
-        if self.no_modules:
-            with open(modules_file, 'w') as fp_module_file:
-                fp_module_file.write("# Empty\n")
-            return
-
         # Invoke the script directly using the Python executable since this is
         # not a module nor a pip-installed Python utility
-        zephyr_module_path = os.path.join(ZEPHYR_BASE, "scripts",
-                                          "zephyr_module.py")
+        zephyr_module_path = ZEPHYR_BASE / "scripts" / "zephyr_module.py"
         cmd = [sys.executable, zephyr_module_path,
-               '--kconfig-out', modules_file, '--settings-out', settings_file]
+               '--kconfig-out', modules_file,
+               '--sysbuild-kconfig-out', sysbuild_modules_file,
+               '--settings-out', settings_file]
         try:
             subprocess.run(cmd, check=True, stdout=subprocess.PIPE,
                            stderr=subprocess.STDOUT)
         except subprocess.CalledProcessError as ex:
             self.error(ex.output.decode("utf-8"))
 
-        modules_dir = ZEPHYR_BASE + '/modules'
+        modules_dir = ZEPHYR_BASE / 'modules'
         modules = [name for name in os.listdir(modules_dir) if
-                   os.path.exists(os.path.join(modules_dir, name, 'Kconfig'))]
+                   modules_dir / name / 'Kconfig']
 
         nrf_modules_dir = ZEPHYR_BASE + '/../nrf/modules'
         nrf_modules = []
@@ -428,7 +472,7 @@ def get_modules(self, modules_file, settings_file):
             for module in modules:
                 fp_module_file.write("ZEPHYR_{}_KCONFIG = {}\n".format(
                     re.sub('[^a-zA-Z0-9]', '_', module).upper(),
-                    modules_dir + '/' + module + '/Kconfig'
+                    modules_dir / module / 'Kconfig'
                 ))
             for module in nrf_modules:
                 fp_module_file.write("ZEPHYR_{}_KCONFIG = {}\n".format(
@@ -441,27 +485,6 @@ def get_modules(self, modules_file, settings_file):
                 ))
             fp_module_file.write(content)
 
-    def get_module_setting_root(self, root, settings_file):
-        """
-        Parse the Zephyr module generated settings file given by 'settings_file'
-        and return all root settings defined by 'root'.
-        """
-        # Invoke the script directly using the Python executable since this is
-        # not a module nor a pip-installed Python utility
-        root_paths = []
-
-        if os.path.exists(settings_file):
-            with open(settings_file, 'r') as fp_setting_file:
-                content = fp_setting_file.read()
-
-            lines = content.strip().split('\n')
-            for line in lines:
-                root = root.upper()
-                if line.startswith(f'"{root}_ROOT":'):
-                    _, root_path = line.split(":", 1)
-                    root_paths.append(Path(root_path.strip('"')))
-        return root_paths
-
     def get_kconfig_dts(self, kconfig_dts_file, settings_file):
         """
         Generate the Kconfig.dts using dts/bindings as the source.
@@ -471,12 +494,11 @@ def get_kconfig_dts(self, kconfig_dts_file, settings_file):
         """
         # Invoke the script directly using the Python executable since this is
         # not a module nor a pip-installed Python utility
-        zephyr_drv_kconfig_path = os.path.join(ZEPHYR_BASE, "scripts", "dts",
-                                               "gen_driver_kconfig_dts.py")
+        zephyr_drv_kconfig_path = ZEPHYR_BASE / "scripts" / "dts" / "gen_driver_kconfig_dts.py"
         binding_paths = []
-        binding_paths.append(os.path.join(ZEPHYR_BASE, "dts", "bindings"))
+        binding_paths.append(ZEPHYR_BASE / "dts" / "bindings")
 
-        dts_root_paths = self.get_module_setting_root('dts', settings_file)
+        dts_root_paths = get_module_setting_root('dts', settings_file)
         for p in dts_root_paths:
             binding_paths.append(p / "dts" / "bindings")
 
@@ -490,32 +512,6 @@ def get_kconfig_dts(self, kconfig_dts_file, settings_file):
         except subprocess.CalledProcessError as ex:
             self.error(ex.output.decode("utf-8"))
 
-    def get_v1_model_syms(self, kconfig_v1_file, kconfig_v1_syms_file):
-        """
-        Generate a symbol define Kconfig file.
-        This function creates a file with all Kconfig symbol definitions from
-        old boards model so that those symbols will not appear as undefined
-        symbols in hardware model v2.
-
-        This is needed to complete Kconfig compliance tests.
-        """
-        os.environ['HWM_SCHEME'] = 'v1'
-        # 'kconfiglib' is global
-        # pylint: disable=undefined-variable
-
-        try:
-            kconf_v1 = kconfiglib.Kconfig(filename=kconfig_v1_file, warn=False)
-        except kconfiglib.KconfigError as e:
-            self.failure(str(e))
-            raise EndTest
-
-        with open(kconfig_v1_syms_file, 'w') as fp_kconfig_v1_syms_file:
-            for s in kconf_v1.defined_syms:
-                if s.type != kconfiglib.UNKNOWN:
-                    fp_kconfig_v1_syms_file.write('config ' + s.name)
-                    fp_kconfig_v1_syms_file.write('\n\t' + kconfiglib.TYPE_TO_STR[s.type])
-                    fp_kconfig_v1_syms_file.write('\n\n')
-
     def get_v2_model(self, kconfig_dir, settings_file):
         """
         Get lists of v2 boards and SoCs and put them in a file that is parsed by
@@ -524,14 +520,21 @@ def get_v2_model(self, kconfig_dir, settings_file):
         This is needed to complete Kconfig sanity tests.
         """
         os.environ['HWM_SCHEME'] = 'v2'
+        os.environ["KCONFIG_BOARD_DIR"] = os.path.join(kconfig_dir, 'boards')
+
+        os.makedirs(os.path.join(kconfig_dir, 'boards'), exist_ok=True)
+        os.makedirs(os.path.join(kconfig_dir, 'soc'), exist_ok=True)
+        os.makedirs(os.path.join(kconfig_dir, 'arch'), exist_ok=True)
+
         kconfig_file = os.path.join(kconfig_dir, 'boards', 'Kconfig')
         kconfig_boards_file = os.path.join(kconfig_dir, 'boards', 'Kconfig.boards')
+        kconfig_sysbuild_file = os.path.join(kconfig_dir, 'boards', 'Kconfig.sysbuild')
         kconfig_defconfig_file = os.path.join(kconfig_dir, 'boards', 'Kconfig.defconfig')
 
-        board_roots = self.get_module_setting_root('board', settings_file)
-        board_roots.insert(0, Path(ZEPHYR_BASE))
-        soc_roots = self.get_module_setting_root('soc', settings_file)
-        soc_roots.insert(0, Path(ZEPHYR_BASE))
+        board_roots = get_module_setting_root('board', settings_file)
+        board_roots.insert(0, ZEPHYR_BASE)
+        soc_roots = get_module_setting_root('soc', settings_file)
+        soc_roots.insert(0, ZEPHYR_BASE)
         root_args = argparse.Namespace(**{'board_roots': board_roots,
                                           'soc_roots': soc_roots, 'board': None,
                                           'board_dir': []})
@@ -542,6 +545,11 @@ def get_v2_model(self, kconfig_dir, settings_file):
                 for board_dir in board.directories:
                     fp.write('osource "' + (board_dir / 'Kconfig.defconfig').as_posix() + '"\n')
 
+        with open(kconfig_sysbuild_file, 'w') as fp:
+            for board in v2_boards:
+                for board_dir in board.directories:
+                    fp.write('osource "' + (board_dir / 'Kconfig.sysbuild').as_posix() + '"\n')
+
         with open(kconfig_boards_file, 'w') as fp:
             for board in v2_boards:
                 board_str = 'BOARD_' + re.sub(r"[^a-zA-Z0-9_]", "_", board.name).upper()
@@ -558,14 +566,12 @@ def get_v2_model(self, kconfig_dir, settings_file):
                     )
 
         with open(kconfig_file, 'w') as fp:
-            fp.write(
-                'osource "' + (Path(kconfig_dir) / 'boards' / 'Kconfig.syms.v1').as_posix() + '"\n'
-            )
             for board in v2_boards:
                 for board_dir in board.directories:
                     fp.write('osource "' + (board_dir / 'Kconfig').as_posix() + '"\n')
 
         kconfig_defconfig_file = os.path.join(kconfig_dir, 'soc', 'Kconfig.defconfig')
+        kconfig_sysbuild_file = os.path.join(kconfig_dir, 'soc', 'Kconfig.sysbuild')
         kconfig_soc_file = os.path.join(kconfig_dir, 'soc', 'Kconfig.soc')
         kconfig_file = os.path.join(kconfig_dir, 'soc', 'Kconfig')
 
@@ -577,6 +583,10 @@ def get_v2_model(self, kconfig_dir, settings_file):
             for folder in soc_folders:
                 fp.write('osource "' + (Path(folder) / 'Kconfig.defconfig').as_posix() + '"\n')
 
+        with open(kconfig_sysbuild_file, 'w') as fp:
+            for folder in soc_folders:
+                fp.write('osource "' + (Path(folder) / 'Kconfig.sysbuild').as_posix() + '"\n')
+
         with open(kconfig_soc_file, 'w') as fp:
             for folder in soc_folders:
                 fp.write('source "' + (Path(folder) / 'Kconfig.soc').as_posix() + '"\n')
@@ -587,34 +597,34 @@ def get_v2_model(self, kconfig_dir, settings_file):
 
         kconfig_file = os.path.join(kconfig_dir, 'arch', 'Kconfig')
 
-        root_args = argparse.Namespace(**{'arch_roots': [Path(ZEPHYR_BASE)], 'arch': None})
+        root_args = argparse.Namespace(**{'arch_roots': [ZEPHYR_BASE], 'arch': None})
         v2_archs = list_hardware.find_v2_archs(root_args)
 
         with open(kconfig_file, 'w') as fp:
             for arch in v2_archs['archs']:
                 fp.write('source "' + (Path(arch['path']) / 'Kconfig').as_posix() + '"\n')
 
-    def parse_kconfig(self, filename="Kconfig", hwm=None):
+    def parse_kconfig(self):
         """
         Returns a kconfiglib.Kconfig object for the Kconfig files. We reuse
         this object for all tests to avoid having to reparse for each test.
         """
         # Put the Kconfiglib path first to make sure no local Kconfiglib version is
         # used
-        kconfig_path = os.path.join(ZEPHYR_BASE, "scripts", "kconfig")
-        if not os.path.exists(kconfig_path):
+        kconfig_path = ZEPHYR_BASE / "scripts" / "kconfig"
+        if not kconfig_path.exists():
             self.error(kconfig_path + " not found")
 
         kconfiglib_dir = tempfile.mkdtemp(prefix="kconfiglib_")
 
-        sys.path.insert(0, kconfig_path)
+        sys.path.insert(0, str(kconfig_path))
         # Import globally so that e.g. kconfiglib.Symbol can be referenced in
         # tests
         global kconfiglib
         import kconfiglib
 
         # Look up Kconfig files relative to ZEPHYR_BASE
-        os.environ["srctree"] = ZEPHYR_BASE
+        os.environ["srctree"] = str(ZEPHYR_BASE)
 
         # Parse the entire Kconfig tree, to make sure we see all symbols
         os.environ["SOC_DIR"] = "soc/"
@@ -631,18 +641,12 @@ def parse_kconfig(self, filename="Kconfig", hwm=None):
 
         # For multi repo support
         self.get_modules(os.path.join(kconfiglib_dir, "Kconfig.modules"),
+                         os.path.join(kconfiglib_dir, "Kconfig.sysbuild.modules"),
                          os.path.join(kconfiglib_dir, "settings_file.txt"))
         # For Kconfig.dts support
         self.get_kconfig_dts(os.path.join(kconfiglib_dir, "Kconfig.dts"),
                              os.path.join(kconfiglib_dir, "settings_file.txt"))
-
-        # To make compliance work with old hw model and HWMv2 simultaneously.
-        kconfiglib_boards_dir = os.path.join(kconfiglib_dir, 'boards')
-        os.makedirs(kconfiglib_boards_dir, exist_ok=True)
-        os.makedirs(os.path.join(kconfiglib_dir, 'soc'), exist_ok=True)
-        os.makedirs(os.path.join(kconfiglib_dir, 'arch'), exist_ok=True)
-
-        os.environ["KCONFIG_BOARD_DIR"] = kconfiglib_boards_dir
+        # For hardware model support (board, soc, arch)
         self.get_v2_model(kconfiglib_dir, os.path.join(kconfiglib_dir, "settings_file.txt"))
 
         # Tells Kconfiglib to generate warnings for all references to undefined
@@ -654,7 +658,7 @@ def parse_kconfig(self, filename="Kconfig", hwm=None):
             # them: so some warnings might get printed
             # twice. "warn_to_stderr=False" could unfortunately cause
             # some (other) warnings to never be printed.
-            return kconfiglib.Kconfig(filename=filename)
+            return kconfiglib.Kconfig(filename=self.FILENAME)
         except kconfiglib.KconfigError as e:
             self.failure(str(e))
             raise EndTest
@@ -695,6 +699,86 @@ def get_logging_syms(self, kconf):
 
         return set(kconf_syms)
 
+    def check_disallowed_defconfigs(self, kconf):
+        """
+        Checks that there are no disallowed Kconfigs used in board/SoC defconfig files
+        """
+        # Grep for symbol references.
+        #
+        # Example output line for a reference to CONFIG_FOO at line 17 of
+        # foo/bar.c:
+        #
+        #   foo/bar.c<null>17<null>#ifdef CONFIG_FOO
+        #
+        # 'git grep --only-matching' would get rid of the surrounding context
+        # ('#ifdef '), but it was added fairly recently (second half of 2018),
+        # so we extract the references from each line ourselves instead.
+        #
+        # The regex uses word boundaries (\b) to isolate the reference, and
+        # negative lookahead to automatically allowlist the following:
+        #
+        #  - ##, for token pasting (CONFIG_FOO_##X)
+        #
+        #  - $, e.g. for CMake variable expansion (CONFIG_FOO_${VAR})
+        #
+        #  - @, e.g. for CMakes's configure_file() (CONFIG_FOO_@VAR@)
+        #
+        #  - {, e.g. for Python scripts ("CONFIG_FOO_{}_BAR".format(...)")
+        #
+        #  - *, meant for comments like '#endif /* CONFIG_FOO_* */
+
+        disallowed_symbols = {
+            "PINCTRL": "Drivers requiring PINCTRL must SELECT it instead.",
+            "BOARD_EARLY_INIT_HOOK": "Boards requiring hooks must SELECT them instead.",
+            "BOARD_LATE_INIT_HOOK": "Boards requiring hooks must SELECT them instead.",
+        }
+
+        disallowed_regex = "(" + "|".join(disallowed_symbols.keys()) + ")$"
+
+        # Warning: Needs to work with both --perl-regexp and the 're' module
+        regex_boards = r"\bCONFIG_[A-Z0-9_]+\b(?!\s*##|[$@{(.*])"
+        regex_socs = r"\bconfig\s+[A-Z0-9_]+$"
+
+        grep_stdout_boards = git("grep", "--line-number", "-I", "--null",
+                                 "--perl-regexp", regex_boards, "--", ":boards",
+                                 cwd=ZEPHYR_BASE)
+        grep_stdout_socs = git("grep", "--line-number", "-I", "--null",
+                               "--perl-regexp", regex_socs, "--", ":soc",
+                               cwd=ZEPHYR_BASE)
+
+        # Board processing
+        # splitlines() supports various line terminators
+        for grep_line in grep_stdout_boards.splitlines():
+            path, lineno, line = grep_line.split("\0")
+
+            # Extract symbol references (might be more than one) within the line
+            for sym_name in re.findall(regex_boards, line):
+                sym_name = sym_name[len("CONFIG_"):]
+                # Only check in Kconfig fragment files, references might exist in documentation
+                if re.match(disallowed_regex, sym_name) and (path[-len("conf"):] == "conf" or
+                path[-len("defconfig"):] == "defconfig"):
+                    reason = disallowed_symbols.get(sym_name)
+                    self.fmtd_failure("error", "BoardDisallowedKconfigs", path, lineno, desc=f"""
+Found disallowed Kconfig symbol in board Kconfig files: CONFIG_{sym_name:35}
+{reason}
+""")
+
+        # SoCs processing
+        # splitlines() supports various line terminators
+        for grep_line in grep_stdout_socs.splitlines():
+            path, lineno, line = grep_line.split("\0")
+
+            # Extract symbol references (might be more than one) within the line
+            for sym_name in re.findall(regex_socs, line):
+                sym_name = sym_name[len("config"):].strip()
+                # Only check in Kconfig defconfig files
+                if re.match(disallowed_regex, sym_name) and "defconfig" in path:
+                    reason = disallowed_symbols.get(sym_name, "Unknown reason")
+                    self.fmtd_failure("error", "SoCDisallowedKconfigs", path, lineno, desc=f"""
+Found disallowed Kconfig symbol in SoC Kconfig files: {sym_name:35}
+{reason}
+""")
+
     def get_defined_syms(self, kconf):
         # Returns a set() with the names of all defined Kconfig symbols (with no
         # 'CONFIG_' prefix). This is complicated by samples and tests defining
@@ -822,7 +906,7 @@ def check_no_undef_within_kconfig(self, kconf):
             self.failure(f"Undefined Kconfig symbols:\n\n {undef_ref_warnings}")
 
     def check_soc_name_sync(self, kconf):
-        root_args = argparse.Namespace(**{'soc_roots': [Path(ZEPHYR_BASE)]})
+        root_args = argparse.Namespace(**{'soc_roots': [ZEPHYR_BASE]})
         v2_systems = list_hardware.find_v2_systems(root_args)
 
         soc_names = {soc.name for soc in v2_systems.get_socs()}
@@ -866,7 +950,7 @@ def check_no_undef_outside_kconfig(self, kconf):
         # so we extract the references from each line ourselves instead.
         #
         # The regex uses word boundaries (\b) to isolate the reference, and
-        # negative lookahead to automatically whitelist the following:
+        # negative lookahead to automatically allowlist the following:
         #
         #  - ##, for token pasting (CONFIG_FOO_##X)
         #
@@ -884,14 +968,14 @@ def check_no_undef_outside_kconfig(self, kconf):
         undef_to_locs = collections.defaultdict(list)
 
         # Warning: Needs to work with both --perl-regexp and the 're' module
-        regex = r"\bCONFIG_[A-Z0-9_]+\b(?!\s*##|[$@{(.*])"
+        regex = r"\b" + self.CONFIG_ + r"[A-Z0-9_]+\b(?!\s*##|[$@{(.*])"
 
         # Skip doc/releases and doc/security/vulnerabilities.rst, which often
         # reference removed symbols
         grep_stdout = git("grep", "--line-number", "-I", "--null",
                           "--perl-regexp", regex, "--", ":!/doc/releases",
                           ":!/doc/security/vulnerabilities.rst",
-                          cwd=Path(GIT_TOP))
+                          cwd=GIT_TOP)
 
         # splitlines() supports various line terminators
         for grep_line in grep_stdout.splitlines():
@@ -900,7 +984,7 @@ def check_no_undef_outside_kconfig(self, kconf):
             # Extract symbol references (might be more than one) within the
             # line
             for sym_name in re.findall(regex, line):
-                sym_name = sym_name[7:]  # Strip CONFIG_
+                sym_name = sym_name[len(self.CONFIG_):]  # Strip CONFIG_
                 if sym_name not in defined_syms and \
                    sym_name not in self.UNDEF_KCONFIG_ALLOWLIST and \
                    not (sym_name.endswith("_MODULE") and sym_name[:-7] in defined_syms):
@@ -916,7 +1000,7 @@ def check_no_undef_outside_kconfig(self, kconf):
         #
         #   CONFIG_ALSO_MISSING    arch/xtensa/core/fatal.c:273
         #   CONFIG_MISSING         arch/xtensa/core/fatal.c:264, subsys/fb/cfb.c:20
-        undef_desc = "\n".join(f"CONFIG_{sym_name:35} {', '.join(locs)}"
+        undef_desc = "\n".join(f"{self.CONFIG_}{sym_name:35} {', '.join(locs)}"
             for sym_name, locs in sorted(undef_to_locs.items()))
 
         self.failure(f"""
@@ -956,6 +1040,7 @@ def check_no_undef_outside_kconfig(self, kconf):
         "BOOT_ENCRYPTION_KEY_FILE", # Used in sysbuild
         "BOOT_ENCRYPT_IMAGE", # Used in sysbuild
         "BOOT_FIRMWARE_LOADER", # Used in sysbuild for MCUboot configuration
+        "BOOT_FIRMWARE_LOADER_BOOT_MODE", # Used in sysbuild for MCUboot configuration
         "BOOT_MAX_IMG_SECTORS_AUTO", # Used in sysbuild
         "BOOT_RAM_LOAD", # Used in sysbuild for MCUboot configuration
         "BOOT_SERIAL_BOOT_MODE",     # Used in (sysbuild-based) test/
@@ -972,6 +1057,7 @@ def check_no_undef_outside_kconfig(self, kconf):
         "BOOT_SIGNATURE_TYPE_NONE",       # MCUboot setting used by sysbuild
         "BOOT_SIGNATURE_TYPE_RSA",        # MCUboot setting used by sysbuild
         "BOOT_SWAP_USING_MOVE", # Used in sysbuild for MCUboot configuration
+        "BOOT_SWAP_USING_OFFSET", # Used in sysbuild for MCUboot configuration
         "BOOT_SWAP_USING_SCRATCH", # Used in sysbuild for MCUboot configuration
         "BOOT_UPGRADE_ONLY", # Used in example adjusting MCUboot config, but
                              # symbol is defined in MCUboot itself.
@@ -1000,6 +1086,11 @@ def check_no_undef_outside_kconfig(self, kconf):
         "FOO_SETTING_2",
         "HEAP_MEM_POOL_ADD_SIZE_", # Used as an option matching prefix
         "HUGETLBFS",          # Linux, in boards/xtensa/intel_adsp_cavs25/doc
+        "IAR_BUFFERED_WRITE",
+        "IAR_LIBCPP",
+        "IAR_SEMIHOSTING",
+        "IPC_SERVICE_ICMSG_BOND_NOTIFY_REPEAT_TO_MS", # Used in ICMsg tests for intercompatibility
+                                                      # with older versions of the ICMsg.
         "LIBGCC_RTLIB",
         "LLVM_USE_LD",   # Both LLVM_USE_* are in cmake/toolchain/llvm/Kconfig
         "LLVM_USE_LLD",  # which are only included if LLVM is selected but
@@ -1012,6 +1103,7 @@ def check_no_undef_outside_kconfig(self, kconf):
         "MCUBOOT_CLEANUP_ARM_CORE", # Used in (sysbuild-based) test
         "MCUBOOT_DOWNGRADE_PREVENTION", # but symbols are defined in MCUboot
                                         # itself.
+        "MCUBOOT_LOG_LEVEL_DBG",
         "MCUBOOT_LOG_LEVEL_INF",
         "MCUBOOT_LOG_LEVEL_WRN",        # Used in example adjusting MCUboot
                                         # config,
@@ -1036,6 +1128,7 @@ def check_no_undef_outside_kconfig(self, kconf):
         "SEL",
         "SHIFT",
         "SINGLE_APPLICATION_SLOT", # Used in sysbuild for MCUboot configuration
+        "SINGLE_APPLICATION_SLOT_RAM_LOAD", # Used in sysbuild for MCUboot configuration
         "SOC_SERIES_", # Used as regex in scripts/utils/board_v1_to_v2.py
         "SOC_WATCH",  # Issue 13749
         "SOME_BOOL",
@@ -1069,26 +1162,29 @@ class KconfigBasicCheck(KconfigCheck):
     references inside the Kconfig tree.
     """
     name = "KconfigBasic"
-    doc = "See https://docs.zephyrproject.org/latest/build/kconfig/tips.html for more details."
-    path_hint = "<zephyr-base>"
 
-    def run(self):
-        super().run(full=False)
+    def check_no_undef_outside_kconfig(self, kconf):
+        pass
 
-class KconfigBasicNoModulesCheck(KconfigCheck):
+
+class KconfigBasicNoModulesCheck(KconfigBasicCheck):
     """
     Checks if we are introducing any new warnings/errors with Kconfig when no
     modules are available. Catches symbols used in the main repository but
     defined only in a module.
     """
     name = "KconfigBasicNoModules"
-    doc = "See https://docs.zephyrproject.org/latest/build/kconfig/tips.html for more details."
     path_hint = "<zephyr-base>"
-    def run(self):
-        super().run(full=False, no_modules=True)
+
+    def get_modules(self, modules_file, sysbuild_modules_file, settings_file):
+        with open(modules_file, 'w') as fp_module_file:
+            fp_module_file.write("# Empty\n")
+
+        with open(sysbuild_modules_file, 'w') as fp_module_file:
+            fp_module_file.write("# Empty\n")
 
 
-class KconfigHWMv2Check(KconfigCheck, ComplianceTest):
+class KconfigHWMv2Check(KconfigBasicCheck):
     """
     This runs the Kconfig test for board and SoC v2 scheme.
     This check ensures that all symbols inside the v2 scheme is also defined
@@ -1096,13 +1192,56 @@ class KconfigHWMv2Check(KconfigCheck, ComplianceTest):
     This ensures the board and SoC trees are fully self-contained and reusable.
     """
     name = "KconfigHWMv2"
-    doc = "See https://docs.zephyrproject.org/latest/guides/kconfig/index.html for more details."
 
-    def run(self):
-        # Use dedicated Kconfig board / soc v2 scheme file.
-        # This file sources only v2 scheme tree.
-        kconfig_file = os.path.join(os.path.dirname(__file__), "Kconfig.board.v2")
-        super().run(full=False, hwm="v2", filename=kconfig_file)
+    # Use dedicated Kconfig board / soc v2 scheme file.
+    # This file sources only v2 scheme tree.
+    FILENAME = os.path.join(os.path.dirname(__file__), "Kconfig.board.v2")
+
+
+class SysbuildKconfigCheck(KconfigCheck):
+    """
+    Checks if we are introducing any new warnings/errors with sysbuild Kconfig,
+    for example using undefined Kconfig variables.
+    """
+    name = "SysbuildKconfig"
+
+    FILENAME = "share/sysbuild/Kconfig"
+    CONFIG_ = "SB_CONFIG_"
+
+    # A different allowlist is used for symbols prefixed with SB_CONFIG_ (omitted here).
+    UNDEF_KCONFIG_ALLOWLIST = {
+        # zephyr-keep-sorted-start re(^\s+")
+        "FOO",
+        "MY_IMAGE", # Used in sysbuild documentation as example
+        "OTHER_APP_IMAGE_NAME", # Used in sysbuild documentation as example
+        "OTHER_APP_IMAGE_PATH", # Used in sysbuild documentation as example
+        "SECOND_SAMPLE", # Used in sysbuild documentation
+        "SUIT_ENVELOPE", # Used by nRF runners to program provisioning data
+        "SUIT_MPI_APP_AREA_PATH", # Used by nRF runners to program provisioning data
+        "SUIT_MPI_GENERATE", # Used by nRF runners to program provisioning data
+        "SUIT_MPI_RAD_AREA_PATH", # Used by nRF runners to program provisioning data
+        # zephyr-keep-sorted-stop
+    }
+
+
+class SysbuildKconfigBasicCheck(SysbuildKconfigCheck, KconfigBasicCheck):
+    """
+    Checks if we are introducing any new warnings/errors with sysbuild Kconfig,
+    for example using undefined Kconfig variables.
+    This runs the basic Kconfig test, which is checking only for undefined
+    references inside the sysbuild Kconfig tree.
+    """
+    name = "SysbuildKconfigBasic"
+
+
+class SysbuildKconfigBasicNoModulesCheck(SysbuildKconfigCheck, KconfigBasicNoModulesCheck):
+    """
+    Checks if we are introducing any new warnings/errors with sysbuild Kconfig
+    when no modules are available. Catches symbols used in the main repository
+    but defined only in a module.
+    """
+    name = "SysbuildKconfigBasicNoModules"
+    path_hint = "<zephyr-base>"
 
 
 class Nits(ComplianceTest):
@@ -1112,7 +1251,6 @@ class Nits(ComplianceTest):
     """
     name = "Nits"
     doc = "See https://docs.zephyrproject.org/latest/contribute/guidelines.html#coding-style for more details."
-    path_hint = "<git-top>"
 
     def run(self):
         # Loop through added/modified files
@@ -1136,7 +1274,7 @@ def run(self):
     def check_kconfig_header(self, fname):
         # Checks for a spammy copy-pasted header format
 
-        with open(os.path.join(GIT_TOP, fname), encoding="utf-8") as f:
+        with open(GIT_TOP / fname, encoding="utf-8") as f:
             contents = f.read()
 
         # 'Kconfig - yada yada' has a copy-pasted redundant filename at the
@@ -1162,7 +1300,7 @@ def check_redundant_zephyr_source(self, fname):
         # Checks for 'source "$(ZEPHYR_BASE)/Kconfig[.zephyr]"', which can be
         # be simplified to 'source "Kconfig[.zephyr]"'
 
-        with open(os.path.join(GIT_TOP, fname), encoding="utf-8") as f:
+        with open(GIT_TOP / fname, encoding="utf-8") as f:
             # Look for e.g. rsource as well, for completeness
             match = re.search(
                 r'^\s*(?:o|r|or)?source\s*"\$\(?ZEPHYR_BASE\)?/(Kconfig(?:\.zephyr)?)"',
@@ -1177,7 +1315,7 @@ def check_redundant_zephyr_source(self, fname):
     def check_redundant_document_separator(self, fname):
         # Looks for redundant '...' document separators in bindings
 
-        with open(os.path.join(GIT_TOP, fname), encoding="utf-8") as f:
+        with open(GIT_TOP / fname, encoding="utf-8") as f:
             if re.search(r"^\.\.\.", f.read(), re.MULTILINE):
                 self.failure(f"""\
 Redundant '...' document separator in {fname}. Binding YAML files are never
@@ -1186,7 +1324,7 @@ def check_redundant_document_separator(self, fname):
     def check_source_file(self, fname):
         # Generic nits related to various source files
 
-        with open(os.path.join(GIT_TOP, fname), encoding="utf-8") as f:
+        with open(GIT_TOP / fname, encoding="utf-8") as f:
             contents = f.read()
 
         if not contents.endswith("\n"):
@@ -1206,7 +1344,6 @@ class GitDiffCheck(ComplianceTest):
     """
     name = "GitDiffCheck"
     doc = "Git conflict markers and whitespace errors are not allowed in added changes"
-    path_hint = "<git-top>"
 
     def run(self):
         offending_lines = []
@@ -1217,7 +1354,7 @@ def run(self):
         for shaidx in get_shas(COMMIT_RANGE):
             # Ignore non-zero return status code
             # Reason: `git diff --check` sets the return code to the number of offending lines
-            diff = git("diff", f"{shaidx}^!", "--check", ignore_non_zero=True)
+            diff = git("diff", f"{shaidx}^!", "--check", "--", ":!*.diff", ":!*.patch", ignore_non_zero=True)
 
             lines = p.findall(diff)
             lines = map(lambda x: f"{shaidx}: {x}", lines)
@@ -1234,7 +1371,6 @@ class GitLint(ComplianceTest):
     """
     name = "Gitlint"
     doc = "See https://docs.zephyrproject.org/latest/contribute/guidelines.html#commit-guidelines for more details"
-    path_hint = "<git-top>"
 
     def run(self):
         # By default gitlint looks for .gitlint configuration only in
@@ -1257,7 +1393,6 @@ class PyLint(ComplianceTest):
     """
     name = "Pylint"
     doc = "See https://www.pylint.org/ for more details"
-    path_hint = "<git-top>"
 
     def run(self):
         # Path to pylint configuration file
@@ -1332,50 +1467,38 @@ class Identity(ComplianceTest):
     """
     name = "Identity"
     doc = "See https://docs.zephyrproject.org/latest/contribute/guidelines.html#commit-guidelines for more details"
-    # git rev-list and git log don't depend on the current (sub)directory
-    # unless explicited
-    path_hint = "<git-top>"
 
     def run(self):
         for shaidx in get_shas(COMMIT_RANGE):
-            commit = git("log", "--decorate=short", "--no-use-mailmap", "-n 1", shaidx)
-            signed = []
-            author = ""
-            sha = ""
-            parsed_addr = None
-            for line in commit.split("\n"):
-                match = re.search(r"^commit\s([^\s]*)", line)
-                if match:
-                    sha = match.group(1)
-                match = re.search(r"^Author:\s(.*)", line)
-                if match:
-                    author = match.group(1)
-                    parsed_addr = parseaddr(author)
-                match = re.search(r"signed-off-by:\s(.*)", line, re.IGNORECASE)
-                if match:
-                    signed.append(match.group(1))
-
-            error1 = f"{sha}: author email ({author}) needs to match one of " \
-                     f"the signed-off-by entries."
-            error2 = f"{sha}: author email ({author}) does not follow the " \
-                     f"syntax: First Last <email>."
-            error3 = f"{sha}: author email ({author}) must be a real email " \
-                     f"and cannot end in @users.noreply.github.com"
-            failure = None
-            if author not in signed:
-                failure = error1
-
-            if not parsed_addr or len(parsed_addr[0].split(" ")) < 2:
-                if not failure:
-
-                    failure = error2
-                else:
-                    failure = failure + "\n" + error2
-            elif parsed_addr[1].endswith("@users.noreply.github.com"):
-                failure = error3
-
-            if failure:
-                self.failure(failure)
+            auth_name, auth_email, body = git(
+                'show', '-s', '--format=%an%n%ae%n%b', shaidx
+            ).split('\n', 2)
+
+            match_signoff = re.search(r"signed-off-by:\s(.*)", body,
+                                      re.IGNORECASE)
+            detailed_match = re.search(r"signed-off-by:\s(.*) <(.*)>", body,
+                                       re.IGNORECASE)
+
+            failures = []
+
+            if auth_email.endswith("@users.noreply.github.com"):
+                failures.append(f"{shaidx}: author email ({auth_email}) must "
+                                "be a real email and cannot end in "
+                                "@users.noreply.github.com")
+
+            if not match_signoff:
+                failures.append(f'{shaidx}: Missing signed-off-by line')
+            elif not detailed_match:
+                signoff = match_signoff.group(0)
+                failures.append(f"{shaidx}: Signed-off-by line ({signoff}) "
+                                "does not follow the syntax: First "
+                                "Last <email>.")
+            elif (auth_name, auth_email) != detailed_match.groups():
+                failures.append(f"{shaidx}: author email ({auth_email}) needs "
+                                "to match one of the signed-off-by entries.")
+
+            if failures:
+                self.failure('\n'.join(failures))
 
 
 class BinaryFiles(ComplianceTest):
@@ -1384,7 +1507,6 @@ class BinaryFiles(ComplianceTest):
     """
     name = "BinaryFiles"
     doc = "No binary files allowed."
-    path_hint = "<git-top>"
 
     def run(self):
         BINARY_ALLOW_PATHS = ("doc/", "boards/", "samples/")
@@ -1407,14 +1529,13 @@ class ImageSize(ComplianceTest):
     """
     name = "ImageSize"
     doc = "Check the size of image files."
-    path_hint = "<git-top>"
 
     def run(self):
         SIZE_LIMIT = 250 << 10
         BOARD_SIZE_LIMIT = 100 << 10
 
         for file in get_files(filter="d"):
-            full_path = os.path.join(GIT_TOP, file)
+            full_path = GIT_TOP / file
             mime_type = magic.from_file(full_path, mime=True)
 
             if not mime_type.startswith("image/"):
@@ -1437,7 +1558,6 @@ class MaintainersFormat(ComplianceTest):
     """
     name = "MaintainersFormat"
     doc = "Check that MAINTAINERS file parses correctly."
-    path_hint = "<git-top>"
 
     def run(self):
         MAINTAINERS_FILES = ["MAINTAINERS.yml", "MAINTAINERS.yaml"]
@@ -1457,7 +1577,6 @@ class ModulesMaintainers(ComplianceTest):
     """
     name = "ModulesMaintainers"
     doc = "Check that all modules have a MAINTAINERS entry."
-    path_hint = "<git-top>"
 
     def run(self):
         MAINTAINERS_FILES = ["MAINTAINERS.yml", "MAINTAINERS.yaml"]
@@ -1492,10 +1611,9 @@ class YAMLLint(ComplianceTest):
     """
     name = "YAMLLint"
     doc = "Check YAML files with YAMLLint."
-    path_hint = "<git-top>"
 
     def run(self):
-        config_file = os.path.join(ZEPHYR_BASE, ".yamllint")
+        config_file = ZEPHYR_BASE / ".yamllint"
 
         for file in get_files(filter="d"):
             if Path(file).suffix not in ['.yaml', '.yml']:
@@ -1523,7 +1641,6 @@ class SphinxLint(ComplianceTest):
 
     name = "SphinxLint"
     doc = "Check Sphinx/reStructuredText files with sphinx-lint."
-    path_hint = "<git-top>"
 
     # Checkers added/removed to sphinx-lint's default set
     DISABLE_CHECKERS = ["horizontal-tab", "missing-space-before-default-role"]
@@ -1565,7 +1682,6 @@ class KeepSorted(ComplianceTest):
     """
     name = "KeepSorted"
     doc = "Check for blocks of code or config that should be kept sorted."
-    path_hint = "<git-top>"
 
     MARKER = "zephyr-keep-sorted"
 
@@ -1661,11 +1777,10 @@ class Ruff(ComplianceTest):
     """
     name = "Ruff"
     doc = "Check python files with ruff."
-    path_hint = "<git-top>"
 
     def run(self):
         for file in get_files(filter="d"):
-            if not file.endswith(".py"):
+            if not file.endswith((".py", ".pyi")):
                 continue
 
             try:
@@ -1709,7 +1824,6 @@ class TextEncoding(ComplianceTest):
     """
     name = "TextEncoding"
     doc = "Check the encoding of text files."
-    path_hint = "<git-top>"
 
     ALLOWED_CHARSETS = ["us-ascii", "utf-8"]
 
@@ -1717,7 +1831,7 @@ def run(self):
         m = magic.Magic(mime=True, mime_encoding=True)
 
         for file in get_files(filter="d"):
-            full_path = os.path.join(GIT_TOP, file)
+            full_path = GIT_TOP / file
             mime_type = m.from_file(full_path)
 
             if not mime_type.startswith("text/"):
@@ -1827,11 +1941,12 @@ def _main(args):
 
         # Propagate this decision to child processes.
         os.environ['ZEPHYR_BASE'] = ZEPHYR_BASE
+    ZEPHYR_BASE = Path(ZEPHYR_BASE)
 
     # The absolute path of the top-level git directory. Initialize it here so
     # that issues running Git can be reported to GitHub.
     global GIT_TOP
-    GIT_TOP = git("rev-parse", "--show-toplevel")
+    GIT_TOP = Path(git("rev-parse", "--show-toplevel"))
 
     # The commit range passed in --commit, e.g. "HEAD~3"
     global COMMIT_RANGE
diff --git a/scripts/ci/coverage/coverage_analysis.py b/scripts/ci/coverage/coverage_analysis.py
index 759690753bd..df0ebc20a73 100644
--- a/scripts/ci/coverage/coverage_analysis.py
+++ b/scripts/ci/coverage/coverage_analysis.py
@@ -334,7 +334,7 @@ def _xlsx_generate_summary_page(self, workbook, json_report):
             {
                 "bold": True,
                 "fg_color":  "#538DD5",
-                "color":"white"
+                "font_color":"white"
             }
         )
         cell_format = workbook.add_format(
@@ -404,7 +404,7 @@ def generate_xlsx_report(self, json_report, output):
             {
                 "bold": True,
                 "fg_color":  "#538DD5",
-                "color":"white"
+                "font_color":"white"
             }
         )
 
@@ -415,7 +415,7 @@ def generate_xlsx_report(self, json_report, output):
                 "align": "center",
                 "valign": "vcenter",
                 "fg_color":  "#538DD5",
-                "color":"white"
+                "font_color":"white"
             }
         )
         cell_format = self.report_book.add_format(
diff --git a/scripts/ci/twister_ignore.txt b/scripts/ci/twister_ignore.txt
index abcdc774ed4..846495d6ce6 100644
--- a/scripts/ci/twister_ignore.txt
+++ b/scripts/ci/twister_ignore.txt
@@ -25,6 +25,7 @@
 .github/workflows/issues-report-config.json
 .github/workflows/backport_issue_check.yml
 MAINTAINERS.yml
+CODEOWNERS
 LICENSE
 Makefile
 doc/*
@@ -43,6 +44,7 @@ scripts/ci/errno.py
 scripts/ci/upload_test_results_es.py
 scripts/ci/what_changed.py
 scripts/ci/version_mgr.py
+scripts/ci/twister_report_analyzer.py
 scripts/ci/stats/*
 scripts/requirements*
 scripts/checkpatch/*
diff --git a/scripts/ci/twister_report_analyzer.py b/scripts/ci/twister_report_analyzer.py
new file mode 100755
index 00000000000..3a52c8a2bfe
--- /dev/null
+++ b/scripts/ci/twister_report_analyzer.py
@@ -0,0 +1,380 @@
+#!/usr/bin/env python3
+# Copyright (c) 2025 Nordic Semiconductor NA
+# SPDX-License-Identifier: Apache-2.0
+from __future__ import annotations
+
+import argparse
+import csv
+import json
+import logging
+import os
+import textwrap
+from dataclasses import asdict, dataclass, field, is_dataclass
+
+logger = logging.getLogger(__name__)
+
+
+def create_parser() -> argparse.ArgumentParser:
+    parser = argparse.ArgumentParser(
+        formatter_class=argparse.RawDescriptionHelpFormatter,
+        allow_abbrev=False,
+        description='Analyzes Twister JSON reports',
+        epilog=(
+            textwrap.dedent("""
+            Example usage:
+                To analyze errors with predefined CMake and Build error patterns, run:
+                > python %(prog)s twister_reports/*.json --long-summary
+                The summary will be saved to twister_report_summary.json file unless --output option is used.
+                To save error summary to CSV file, use --output-csv option (number of test files is limited to 100):
+                > python %(prog)s twister_reports/*.json --output-csv twister_report_summary.csv
+                One can use --error-patterns option to provide custom error patterns file:
+                > python %(prog)s **/twister.json --error-patterns error_patterns.txt
+        """)  # noqa E501
+        ),
+    )
+    parser.add_argument('inputs', type=str, nargs="+", help='twister.json files to read')
+    parser.add_argument(
+        '--error-patterns',
+        type=str,
+        help='text file with custom error patterns, ' 'each entry must be separated by newlines',
+    )
+    parser.add_argument(
+        '--output',
+        type=str,
+        default='twister_report_summary.json',
+        help='output json file name, default: twister_report_summary.json',
+    )
+    parser.add_argument('--output-csv', type=str, help='output csv file name')
+    parser.add_argument(
+        '--output-md', type=str, help='output markdown file name to store table with errors'
+    )
+    parser.add_argument(
+        '--status',
+        action='store_true',
+        help='add statuses of testsuites and testcases to the summary',
+    )
+    parser.add_argument(
+        '--platforms',
+        action='store_true',
+        help='add errors per platform to the summary',
+    )
+    parser.add_argument(
+        '--long-summary',
+        action='store_true',
+        help='show all matched errors grouped by reason, otherwise show only most common errors',
+    )
+
+    parser.add_argument(
+        '-ll',
+        '--log-level',
+        type=str.upper,
+        default='INFO',
+        choices=['DEBUG', 'INFO', 'WARNING', 'ERROR', 'CRITICAL'],
+    )
+    return parser
+
+
+@dataclass
+class Counters:
+    counters: dict[str, TestCollection] = field(default_factory=dict)
+
+    def add_counter(self, key: str, test: str = '') -> None:
+        self.counters[key] = self.counters.get(key, TestCollection())
+        self.counters[key].append(test)
+
+    def print_counters(self, indent: int = 0):
+        for key, value in self.counters.items():
+            print(f'{" " * indent}{value.quantity:4}    {key}')
+            if value.has_subcounters():
+                value.subcounters.print_counters(indent + 4)
+
+    def sort_by_quantity(self):
+        self.counters = dict(
+            sorted(self.counters.items(), key=lambda item: item[1].quantity, reverse=True)
+        )
+        for value in self.counters.values():
+            if value.has_subcounters():
+                value.subcounters.sort_by_quantity()
+
+    def get_next_entry(self, depth: int = 0, max_depth: int = 10):
+        for key, value in self.counters.items():
+            # limit number of test files to 100 to not exceed CSV cell limit
+            yield depth, value.quantity, key, ', '.join(value.tests[0:100])
+            if value.has_subcounters() and depth < max_depth:
+                yield from value.subcounters.get_next_entry(depth + 1, max_depth)
+
+    def _flatten(self):
+        """
+        Yield all deepest counters in a flat structure.
+        Deepest counters refer to those counters which
+        do not contain any further nested subcounters.
+        """
+        for key, value in self.counters.items():
+            if value.has_subcounters():
+                yield from value.subcounters._flatten()
+            else:
+                yield key, value
+
+    def get_most_common(self, n: int = 10):
+        return dict(sorted(self._flatten(), key=lambda item: item[1].quantity, reverse=True)[:n])
+
+
+@dataclass
+class TestCollection:
+    quantity: int = 0
+    tests: list[str] = field(default_factory=list)
+    subcounters: Counters = field(default_factory=Counters)
+
+    def append(self, test: str = ''):
+        self.quantity += 1
+        if test:
+            self.tests.append(test)
+
+    def has_subcounters(self):
+        return bool(self.subcounters.counters)
+
+
+class TwisterReports:
+    def __init__(self):
+        self.status: Counters = Counters()
+        self.errors: Counters = Counters()
+        self.platforms: Counters = Counters()
+
+    def parse_report(self, json_filename):
+        logger.info(f'Process {json_filename}')
+        with open(json_filename) as json_results:
+            json_data = json.load(json_results)
+
+        for ts in json_data.get('testsuites', []):
+            self.parse_statuses(ts)
+
+        for ts in json_data.get('testsuites', []):
+            self.parse_testsuite(ts)
+
+    def parse_statuses(self, testsuite):
+        ts_status = testsuite.get('status', 'no status in testsuite')
+        self.status.add_counter(ts_status)
+        # Process testcases
+        for tc in testsuite.get('testcases', []):
+            tc_status = tc.get('status')
+            self.status.counters[ts_status].subcounters.add_counter(tc_status)
+
+    def parse_testsuite(self, testsuite):
+        ts_status = testsuite.get('status') or 'no status in testsuite'
+        if ts_status not in ('error', 'failed'):
+            return
+
+        ts_platform = testsuite.get('platform') or 'Unknown platform'
+        self.platforms.add_counter(ts_platform)
+        ts_reason = testsuite.get('reason') or 'Unknown reason'
+        ts_log = testsuite.get('log')
+        test_identifier = f'{testsuite.get("platform")}:{testsuite.get("name")}'
+
+        # CMake and Build failures are treated separately.
+        # Extract detailed information to group errors. Keep the parsing methods
+        # to allow for further customization and keep backward compatibility.
+        if ts_reason.startswith('CMake build failure'):
+            reason = 'CMake build failure'
+            self.errors.add_counter(reason)
+            error_key = ts_reason.split(reason, 1)[-1].lstrip(' -')
+            if not error_key:
+                error_key = self._parse_cmake_build_failure(ts_log)
+            self.errors.counters[reason].subcounters.add_counter(error_key, test_identifier)
+            ts_reason = reason
+        elif ts_reason.startswith('Build failure'):
+            reason = 'Build failure'
+            self.errors.add_counter(reason)
+            error_key = ts_reason.split(reason, 1)[-1].lstrip(' -')
+            if not error_key:
+                error_key = self._parse_build_failure(ts_log)
+            self.errors.counters[reason].subcounters.add_counter(error_key, test_identifier)
+            ts_reason = reason
+        else:
+            self.errors.add_counter(ts_reason)
+
+        # Process testcases
+        for tc in testsuite.get('testcases', []):
+            tc_reason = tc.get('reason')
+            tc_log = tc.get('log')
+            if tc_reason and tc_log:
+                self.errors.counters[ts_reason].subcounters.add_counter(tc_reason, test_identifier)
+
+        if not self.errors.counters[ts_reason].has_subcounters():
+            self.errors.counters[ts_reason].tests.append(test_identifier)
+
+    def _parse_cmake_build_failure(self, log: str) -> str | None:
+        last_warning = 'no warning found'
+        lines = log.splitlines()
+        for i, line in enumerate(lines):
+            if "warning: " in line:
+                last_warning = line
+            elif "devicetree error: " in line:
+                return "devicetree error"
+            elif "fatal error: " in line:
+                return line[line.index('fatal error: ') :].strip()
+            elif "error: " in line:  # error: Aborting due to Kconfig warnings
+                if "undefined symbol" in last_warning:
+                    return last_warning[last_warning.index('undefined symbol') :].strip()
+                return last_warning
+            elif "CMake Error at" in line:
+                for next_line in lines[i + 1 :]:
+                    if next_line.strip():
+                        return line + ' ' + next_line
+                return line
+        return "No matching CMake error pattern found"
+
+    def _parse_build_failure(self, log: str) -> str | None:
+        last_warning = ''
+        lines = log.splitlines()
+        for i, line in enumerate(lines):
+            if "undefined reference" in line:
+                return line[line.index('undefined reference') :].strip()
+            elif "error: ld returned" in line:
+                if last_warning:
+                    return last_warning
+                elif "overflowed by" in lines[i - 1]:
+                    return "ld.bfd: region overflowed"
+                elif "ld.bfd: warning: " in lines[i - 1]:
+                    return "ld.bfd:" + lines[i - 1].split("ld.bfd:", 1)[-1]
+                return line
+            elif "error: " in line:
+                return line[line.index('error: ') :].strip()
+            elif ": in function " in line:
+                last_warning = line[line.index('in function') :].strip()
+        return "No matching build error pattern found"
+
+    def sort_counters(self):
+        self.status.sort_by_quantity()
+        self.platforms.sort_by_quantity()
+        self.errors.sort_by_quantity()
+
+
+class TwisterReportsWithPatterns(TwisterReports):
+    def __init__(self, error_patterns_file):
+        super().__init__()
+        self.error_patterns = []
+        self.add_error_patterns(error_patterns_file)
+
+    def add_error_patterns(self, filename):
+        with open(filename) as f:
+            self.error_patterns = [
+                line
+                for line in f.read().splitlines()
+                if line.strip() and not line.strip().startswith('#')
+            ]
+        logger.info(f'Loaded {len(self.error_patterns)} error patterns from {filename}')
+
+    def parse_testsuite(self, testsuite):
+        ts_status = testsuite.get('status') or 'no status in testsuite'
+        if ts_status not in ('error', 'failed'):
+            return
+
+        ts_log = testsuite.get('log')
+        test_identifier = f'{testsuite.get("platform")}:{testsuite.get("name")}'
+        if key := self._parse_log_with_error_paterns(ts_log):
+            self.errors.add_counter(key, test_identifier)
+        # Process testcases
+        for tc in testsuite.get('testcases', []):
+            tc_log = tc.get('log')
+            if tc_log and (key := self._parse_log_with_error_paterns(tc_log)):
+                self.errors.add_counter(key, test_identifier)
+
+    def _parse_log_with_error_paterns(self, log: str) -> str | None:
+        for line in log.splitlines():
+            for error_pattern in self.error_patterns:
+                if error_pattern in line:
+                    logger.debug(f'Matched: {error_pattern} in {line}')
+                    return error_pattern
+        return None
+
+
+class EnhancedJSONEncoder(json.JSONEncoder):
+    def default(self, o):
+        if is_dataclass(o):
+            return asdict(o)
+        return super().default(o)
+
+
+def dump_to_json(filename, data):
+    with open(filename, 'w') as f:
+        json.dump(data, f, indent=4, cls=EnhancedJSONEncoder)
+    logger.info(f'Data saved to {filename}')
+
+
+def dump_to_csv(filename, data: Counters):
+    with open(filename, 'w', newline='') as csvfile:
+        csvwriter = csv.writer(csvfile)
+        # Write headers
+        csvwriter.writerow(['Depth', 'Counter', 'Key', 'Tests'])
+        # Write error data
+        for csv_data in data.get_next_entry():
+            csvwriter.writerow(csv_data)
+    logger.info(f'Data saved to {filename}')
+
+
+def dump_markdown_table(filename, data: Counters, max_depth=2):
+    with open(filename, 'w', newline='') as md:
+        for depth, quantity, key, _ in data.get_next_entry(max_depth=max_depth):
+            if depth == 0:
+                md.write('\n')
+            md.write(f'| {quantity:4} | {key} |\n')
+            if depth == 0:
+                md.write('|-------|------|\n')
+    logger.info(f'Markdown table saved to {filename}')
+
+
+def summary_with_most_common_errors(errors: Counters, limit: int = 15):
+    print('\nMost common errors summary:')
+    for key, value in errors.get_most_common(n=limit).items():
+        print(f'{value.quantity:4}    {key}')
+
+
+def main():
+    parser = create_parser()
+    args = parser.parse_args()
+
+    logging.basicConfig(level=args.log_level, format='%(levelname)-8s:  %(message)s')
+    logger = logging.getLogger()
+
+    if args.error_patterns:
+        reports = TwisterReportsWithPatterns(args.error_patterns)
+    else:
+        reports = TwisterReports()
+
+    for filename in args.inputs:
+        if os.path.exists(filename):
+            reports.parse_report(filename)
+        else:
+            logger.warning(f'File not found: {filename}')
+
+    reports.sort_counters()
+    dump_to_json(
+        args.output,
+        {'status': reports.status, 'platforms': reports.platforms, 'errors': reports.errors},
+    )
+
+    if args.status:
+        print('\nTestsuites and testcases status summary:')
+        reports.status.print_counters()
+
+    if not reports.errors.counters:
+        return
+
+    if args.platforms and reports.platforms.counters:
+        print('\nErrors per platform:')
+        reports.platforms.print_counters()
+
+    if args.long_summary:
+        print('\nErrors summary:')
+        reports.errors.print_counters()
+    else:
+        summary_with_most_common_errors(reports.errors)
+
+    if args.output_csv:
+        dump_to_csv(args.output_csv, reports.errors)
+    if args.output_md:
+        dump_markdown_table(args.output_md, reports.errors, max_depth=2)
+
+
+if __name__ == '__main__':
+    main()
diff --git a/scripts/dts/gen_defines.py b/scripts/dts/gen_defines.py
index eb9fc5e8ce0..99aac7d720c 100755
--- a/scripts/dts/gen_defines.py
+++ b/scripts/dts/gen_defines.py
@@ -720,6 +720,9 @@ def fmt_dep_list(dep_list):
         else:
             return "/* nothing */"
 
+    out_comment("Node's hash:")
+    out_dt_define(f"{node.z_path_id}_HASH", node.hash)
+
     out_comment("Node's dependency ordinal:")
     out_dt_define(f"{node.z_path_id}_ORD", node.dep_ordinal)
     out_dt_define(f"{node.z_path_id}_ORD_STR_SORTABLE", f"{node.dep_ordinal:0>5}")
diff --git a/scripts/dts/gen_driver_kconfig_dts.py b/scripts/dts/gen_driver_kconfig_dts.py
index 2d433bbd5dd..6014027b455 100755
--- a/scripts/dts/gen_driver_kconfig_dts.py
+++ b/scripts/dts/gen_driver_kconfig_dts.py
@@ -1,13 +1,12 @@
 #!/usr/bin/env python3
 #
 # Copyright (c) 2022 Kumar Gala <galak@kernel.org>
+# Copyright (c) 2025 Nordic Semiconductor ASA
 #
 # SPDX-License-Identifier: Apache-2.0
 
 import argparse
 import os
-import sys
-import re
 
 import yaml
 try:
@@ -16,22 +15,33 @@
 except ImportError:
     from yaml import SafeLoader     # type: ignore
 
-sys.path.insert(0, os.path.join(os.path.dirname(__file__), 'python-devicetree',
-                                'src'))
 
-def binding_paths(bindings_dirs):
-    # Returns a list with the paths to all bindings (.yaml files) in
-    # 'bindings_dirs'
+HEADER = """\
+# Generated devicetree Kconfig
+#
+# SPDX-License-Identifier: Apache-2.0"""
+
+
+KCONFIG_TEMPLATE = """
+DT_COMPAT_{COMPAT} := {compat}
+
+config DT_HAS_{COMPAT}_ENABLED
+\tdef_bool $(dt_compat_enabled,$(DT_COMPAT_{COMPAT}))"""
 
-    binding_paths = []
+
+# Character translation table used to derive Kconfig symbol names
+TO_UNDERSCORES = str.maketrans("-,.@/+", "______")
+
+
+def binding_paths(bindings_dirs):
+    # Yields paths to all bindings (.yaml files) in 'bindings_dirs'
 
     for bindings_dir in bindings_dirs:
         for root, _, filenames in os.walk(bindings_dir):
             for filename in filenames:
-                if filename.endswith(".yaml") or filename.endswith(".yml"):
-                    binding_paths.append(os.path.join(root, filename))
+                if filename.endswith((".yaml", ".yml")):
+                    yield os.path.join(root, filename)
 
-    return binding_paths
 
 def parse_args():
     # Returns parsed command-line arguments
@@ -45,56 +55,38 @@ def parse_args():
 
     return parser.parse_args()
 
-def printfile(s):
-    print(s, file=kconfig_file)
-
-def str2ident(s):
-    # Converts 's' to a form suitable for (part of) an identifier
-
-    return re.sub('[-,.@/+]', '_', s.upper())
-
-def compat2kconfig(compat):
-    compat_ident = str2ident(compat)
-
-    printfile(f'')
-    printfile(f'DT_COMPAT_{compat_ident} := {compat}')
-    printfile(f'')
-    printfile(f'config DT_HAS_{compat_ident}_ENABLED')
-    printfile(f'\tdef_bool $(dt_compat_enabled,$(DT_COMPAT_{compat_ident}))')
 
 def main():
-    global kconfig_file
     args = parse_args()
 
-    compat_list = []
+    compats = set()
 
     for binding_path in binding_paths(args.bindings_dirs):
         with open(binding_path, encoding="utf-8") as f:
-            contents = f.read()
-
             try:
-                # Parsed PyYAML output (Python lists/dictionaries/strings/etc.,
-                # representing the file)
-                raw = yaml.load(contents, Loader=SafeLoader)
+                # Parsed PyYAML representation graph. For our purpose,
+                # we don't need the whole file converted into a dict.
+                root = yaml.compose(f, Loader=SafeLoader)
             except yaml.YAMLError as e:
                 print(f"WARNING: '{binding_path}' appears in binding "
                       f"directories but isn't valid YAML: {e}")
                 continue
-        if raw is None or 'compatible' not in raw:
-            continue
 
-        compat_list.append(raw['compatible'])
-
-    # Remove any duplicates and sort the list
-    compat_list = sorted(set(compat_list))
+        if not isinstance(root, yaml.MappingNode):
+            continue
+        for key, node in root.value:
+            if key.value == "compatible" and isinstance(node, yaml.ScalarNode):
+                compats.add(node.value)
+                break
 
     with open(args.kconfig_out, "w", encoding="utf-8") as kconfig_file:
-        printfile(f'# Generated devicetree Kconfig')
-        printfile(f'#')
-        printfile(f'# SPDX-License-Identifier: Apache-2.0')
+        print(HEADER, file=kconfig_file)
 
-        for c in compat_list:
-            compat2kconfig(c)
+        for c in sorted(compats):
+            out = KCONFIG_TEMPLATE.format(
+                compat=c, COMPAT=c.upper().translate(TO_UNDERSCORES)
+            )
+            print(out, file=kconfig_file)
 
 
 if __name__ == "__main__":
diff --git a/scripts/dts/python-devicetree/src/devicetree/dtlib.py b/scripts/dts/python-devicetree/src/devicetree/dtlib.py
index cf1d80a9c49..38f74f338d2 100644
--- a/scripts/dts/python-devicetree/src/devicetree/dtlib.py
+++ b/scripts/dts/python-devicetree/src/devicetree/dtlib.py
@@ -20,9 +20,8 @@
 import string
 import sys
 import textwrap
-from typing import (Any, Iterable,
-                    NamedTuple, NoReturn, Optional,
-                    TYPE_CHECKING, Union)
+from collections.abc import Iterable
+from typing import TYPE_CHECKING, Any, NamedTuple, NoReturn, Optional, Union
 
 # NOTE: tests/test_dtlib.py is the test suite for this library.
 
@@ -38,6 +37,12 @@ class Node:
     name:
       The name of the node (a string).
 
+    filename:
+      The name of the .dts file where the node is defined
+
+    lineno:
+      The line number in the .dts file where the node starts.
+
     unit_addr:
       The portion after the '@' in the node's name, or the empty string if the
       name has no '@' in it.
@@ -85,13 +90,15 @@ class Node:
     # Public interface
     #
 
-    def __init__(self, name: str, parent: Optional['Node'], dt: 'DT'):
+    def __init__(self, name: str, parent: Optional["Node"], dt: "DT", filename: str, lineno: int):
         """
         Node constructor. Not meant to be called directly by clients.
         """
         # Remember to update DT.__deepcopy__() if you change this.
 
         self._name = name
+        self._filename = filename
+        self._lineno = lineno
         self.props: dict[str, Property] = {}
         self.nodes: dict[str, Node] = {}
         self.labels: list[str] = []
@@ -103,7 +110,7 @@ def __init__(self, name: str, parent: Optional['Node'], dt: 'DT'):
 
         if name.count("@") > 1:
             dt._parse_error("multiple '@' in node name")
-        if not name == "/":
+        if name != "/":
             for char in name:
                 if char not in _nodename_chars:
                     dt._parse_error(f"{self.path}: bad character '{char}' "
@@ -118,6 +125,20 @@ def name(self) -> str:
         # via DT.move_node.
         return self._name
 
+    @property
+    def lineno(self) -> int:
+        """
+        See the class documentation.
+        """
+        return self._lineno
+
+    @property
+    def filename(self) -> str:
+        """
+        See the class documentation.
+        """
+        return self._filename
+
     @property
     def unit_addr(self) -> str:
         """
@@ -240,6 +261,12 @@ class Property:
     name:
       The name of the property (a string).
 
+    filename:
+      The name of the .dts file where the property is defined
+
+    lineno:
+      The line number in the .dts file where the property starts.
+
     value:
       The value of the property, as a 'bytes' string. Numbers are stored in
       big-endian format, and strings are null-terminated. Putting multiple
@@ -308,6 +335,8 @@ def __init__(self, node: Node, name: str):
             node.dt._parse_error("'@' is only allowed in node names")
 
         self.name = name
+        self.filename = ""
+        self.lineno = -1
         self.value = b""
         self.labels: list[str] = []
         # We have to wait to set this until later, when we've got
@@ -381,10 +410,9 @@ def to_num(self, signed=False) -> int:
           unsigned.
         """
         if self.type is not Type.NUM:
-            _err("expected property '{0}' on {1} in {2} to be assigned with "
-                 "'{0} = < (number) >;', not '{3}'"
-                 .format(self.name, self.node.path, self.node.dt.filename,
-                         self))
+            _err(f"expected property '{self.name}' on {self.node.path} in "
+                 f"{self.node.dt.filename} to be assigned with "
+                 f"'{self.name} = < (number) >;', not '{self}'")
 
         return int.from_bytes(self.value, "big", signed=signed)
 
@@ -402,10 +430,9 @@ def to_nums(self, signed=False) -> list[int]:
           unsigned.
         """
         if self.type not in (Type.NUM, Type.NUMS):
-            _err("expected property '{0}' on {1} in {2} to be assigned with "
-                 "'{0} = < (number) (number) ... >;', not '{3}'"
-                 .format(self.name, self.node.path, self.node.dt.filename,
-                         self))
+            _err(f"expected property '{self.name}' on {self.node.path} in "
+                 f"{self.node.dt.filename} to be assigned with "
+                 f"'{self.name} = < (number) (number) ... >;', not '{self}'")
 
         return [int.from_bytes(self.value[i:i + 4], "big", signed=signed)
                 for i in range(0, len(self.value), 4)]
@@ -421,10 +448,9 @@ def to_bytes(self) -> bytes:
             foo = [ 01 ... ];
         """
         if self.type is not Type.BYTES:
-            _err("expected property '{0}' on {1} in {2} to be assigned with "
-                 "'{0} = [ (byte) (byte) ... ];', not '{3}'"
-                 .format(self.name, self.node.path, self.node.dt.filename,
-                         self))
+            _err(f"expected property '{self.name}' on {self.node.path} "
+                 f"in {self.node.dt.filename} to be assigned with "
+                 f"'{self.name} = [ (byte) (byte) ... ];', not '{self}'")
 
         return self.value
 
@@ -441,10 +467,9 @@ def to_string(self) -> str:
         not valid UTF-8.
         """
         if self.type is not Type.STRING:
-            _err("expected property '{0}' on {1} in {2} to be assigned with "
-                 "'{0} = \"string\";', not '{3}'"
-                 .format(self.name, self.node.path, self.node.dt.filename,
-                         self))
+            _err(f"expected property '{self.name}' on {self.node.path} "
+                 f"in {self.node.dt.filename} to be assigned with "
+                 f"'{self.name} = \"string\";', not '{self}'")
 
         try:
             ret = self.value.decode("utf-8")[:-1]  # Strip null
@@ -467,10 +492,9 @@ def to_strings(self) -> list[str]:
         Also raises DTError if any of the strings are not valid UTF-8.
         """
         if self.type not in (Type.STRING, Type.STRINGS):
-            _err("expected property '{0}' on {1} in {2} to be assigned with "
-                 "'{0} = \"string\", \"string\", ... ;', not '{3}'"
-                 .format(self.name, self.node.path, self.node.dt.filename,
-                         self))
+            _err(f"expected property '{self.name}' on {self.node.path} in "
+                 f"{self.node.dt.filename} to be assigned with "
+                 f"'{self.name} = \"string\", \"string\", ... ;', not '{self}'")
 
         try:
             ret = self.value.decode("utf-8").split("\0")[:-1]
@@ -491,10 +515,9 @@ def to_node(self) -> Node:
             foo = < &bar >;
         """
         if self.type is not Type.PHANDLE:
-            _err("expected property '{0}' on {1} in {2} to be assigned with "
-                 "'{0} = < &foo >;', not '{3}'"
-                 .format(self.name, self.node.path, self.node.dt.filename,
-                         self))
+            _err(f"expected property '{self.name}' on {self.node.path} in "
+                 f"{self.node.dt.filename} to be assigned with "
+                 f"'{self.name} = < &foo >;', not '{self}'")
 
         return self.node.dt.phandle2node[int.from_bytes(self.value, "big")]
 
@@ -517,10 +540,9 @@ def type_ok():
             return self.type is Type.NUMS and not self.value
 
         if not type_ok():
-            _err("expected property '{0}' on {1} in {2} to be assigned with "
-                 "'{0} = < &foo &bar ... >;', not '{3}'"
-                 .format(self.name, self.node.path,
-                         self.node.dt.filename, self))
+            _err(f"expected property '{self.name}' on {self.node.path} in "
+                 f"{self.node.dt.filename} to be assigned with "
+                 f"'{self.name} = < &foo &bar ... >;', not '{self}'")
 
         return [self.node.dt.phandle2node[int.from_bytes(self.value[i:i + 4],
                                                          "big")]
@@ -539,10 +561,10 @@ def to_path(self) -> Node:
         For the second case, DTError is raised if the path does not exist.
         """
         if self.type not in (Type.PATH, Type.STRING):
-            _err("expected property '{0}' on {1} in {2} to be assigned with "
-                 "either '{0} = &foo' or '{0} = \"/path/to/node\"', not '{3}'"
-                 .format(self.name, self.node.path, self.node.dt.filename,
-                         self))
+            _err(f"expected property '{self.name}' on {self.node.path} in "
+                 f"{self.node.dt.filename} to be assigned with either "
+                 f"'{self.name} = &foo' or '{self.name} = \"/path/to/node\"', "
+                 f"not '{self}'")
 
         try:
             path = self.value.decode("utf-8")[:-1]
@@ -620,7 +642,6 @@ def __str__(self):
 
         return s + ";"
 
-
     def __repr__(self):
         return (f"<Property '{self.name}' at '{self.node.path}' in "
                 f"'{self.node.dt.filename}'>")
@@ -934,7 +955,7 @@ def __deepcopy__(self, memo):
         # them without any properties. We will recursively initialize
         # copies of parents before copies of children next.
         path2node_copy = {
-            node.path: Node(node.name, None, ret)
+            node.path: Node(node.name, None, ret, node.filename, node.lineno)
             for node in self.node_iter()
         }
 
@@ -963,6 +984,8 @@ def __deepcopy__(self, memo):
                 prop_copy.offset_labels = prop.offset_labels.copy()
                 prop_copy._label_offset_lst = prop._label_offset_lst[:]
                 prop_copy._markers = [marker[:] for marker in prop._markers]
+                prop_copy.filename = prop.filename
+                prop_copy.lineno = prop.lineno
             node_copy.props = prop_name2prop_copy
 
             node_copy.nodes = {
@@ -1090,7 +1113,9 @@ def _parse_dt(self):
             if tok.val == "/":
                 # '/ { ... };', the root node
                 if not self._root:
-                    self._root = Node(name="/", parent=None, dt=self)
+                    self._root = Node(
+                        name="/", parent=None, dt=self, filename=self.filename, lineno=self._lineno
+                    )
                 self._parse_node(self.root)
 
             elif tok.id in (_T.LABEL, _T.REF):
@@ -1153,7 +1178,13 @@ def _parse_node(self, node):
                         if child.name in current_child_names:
                             self._parse_error(f'{child.path}: duplicate node name')
                     else:
-                        child = Node(name=tok.val, parent=node, dt=self)
+                        child = Node(
+                            name=tok.val,
+                            parent=node,
+                            dt=self,
+                            filename=self.filename,
+                            lineno=self._lineno,
+                        )
                         current_child_names.add(tok.val)
 
                     for label in labels:
@@ -1173,6 +1204,8 @@ def _parse_node(self, node):
                             "/omit-if-no-ref/ can only be used on nodes")
 
                     prop = node._get_prop(tok.val)
+                    prop.filename = self.filename
+                    prop.lineno = self._lineno
 
                     if self._check_token("="):
                         self._parse_assignment(prop)
@@ -1950,13 +1983,20 @@ def _unescape(self, b):
 
         def sub(match):
             esc = match.group(1)
-            if esc == b"a": return b"\a"
-            if esc == b"b": return b"\b"
-            if esc == b"t": return b"\t"
-            if esc == b"n": return b"\n"
-            if esc == b"v": return b"\v"
-            if esc == b"f": return b"\f"
-            if esc == b"r": return b"\r"
+            if esc == b"a":
+                return b"\a"
+            if esc == b"b":
+                return b"\b"
+            if esc == b"t":
+                return b"\t"
+            if esc == b"n":
+                return b"\n"
+            if esc == b"v":
+                return b"\v"
+            if esc == b"f":
+                return b"\f"
+            if esc == b"r":
+                return b"\r"
 
             if esc[0] in b"01234567":
                 # Octal escape
diff --git a/scripts/dts/python-devicetree/src/devicetree/edtlib.py b/scripts/dts/python-devicetree/src/devicetree/edtlib.py
index 752e15dc81d..b6f93543580 100644
--- a/scripts/dts/python-devicetree/src/devicetree/edtlib.py
+++ b/scripts/dts/python-devicetree/src/devicetree/edtlib.py
@@ -67,28 +67,38 @@
 #   @properties are documented in the class docstring, as if they were
 #   variables. See the existing @properties for a template.
 
-from collections import defaultdict
-from copy import deepcopy
-from dataclasses import dataclass
-from typing import (Any, Callable, Iterable, NoReturn,
-                    Optional, TYPE_CHECKING, Union)
+import base64
+import hashlib
 import logging
 import os
 import re
+from collections import defaultdict
+from collections.abc import Callable, Iterable
+from copy import deepcopy
+from dataclasses import dataclass
+from typing import TYPE_CHECKING, Any, NoReturn, Optional, Union
 
 import yaml
+
 try:
     # Use the C LibYAML parser if available, rather than the Python parser.
     # This makes e.g. gen_defines.py more than twice as fast.
     from yaml import CLoader as Loader
 except ImportError:
-    from yaml import Loader     # type: ignore
+    from yaml import Loader  # type: ignore
 
-from devicetree.dtlib import DT, DTError, to_num, to_nums, Type
+from devicetree._private import _slice_helper
+from devicetree.dtlib import DT, DTError, Type, to_num, to_nums
 from devicetree.dtlib import Node as dtlib_Node
 from devicetree.dtlib import Property as dtlib_Property
 from devicetree.grutils import Graph
-from devicetree._private import _slice_helper
+
+
+def _compute_hash(path: str) -> str:
+    # Calculates the hash associated with the node's full path.
+    hasher = hashlib.sha256()
+    hasher.update(path.encode())
+    return base64.b64encode(hasher.digest(), altchars=b'__').decode().rstrip('=')
 
 #
 # Public classes
@@ -104,8 +114,21 @@ class Binding:
     path:
       The absolute path to the file defining the binding.
 
+    title:
+      The free-form title of the binding (optional).
+
+      When the content in the 'description:' is too long, the 'title:' can
+      be used as a heading for the extended description. Typically, it serves
+      as a description of the hardware model. For example:
+
+      title: Nordic GPIO
+
+      description: |
+        Descriptions and example nodes related to GPIO.
+        ...
+
     description:
-      The free-form description of the binding, or None.
+      The free-form description of the binding.
 
     compatible:
       The compatible string the binding matches.
@@ -163,7 +186,7 @@ class Binding:
 
     def __init__(self, path: Optional[str], fname2path: dict[str, str],
                  raw: Any = None, require_compatible: bool = True,
-                 require_description: bool = True):
+                 require_description: bool = True, require_title: bool = False):
         """
         Binding constructor.
 
@@ -191,6 +214,12 @@ def __init__(self, path: Optional[str], fname2path: dict[str, str],
           "description:" line. If False, a missing "description:" is
           not an error. Either way, "description:" must be a string
           if it is present in the binding.
+
+        require_title:
+          If True, it is an error if the binding does not contain a
+          "title:" line. If False, a missing "title:" is not an error.
+          Either way, "title:" must be a string if it is present in
+          the binding.
         """
         self.path: Optional[str] = path
         self._fname2path: dict[str, str] = fname2path
@@ -207,13 +236,13 @@ def __init__(self, path: Optional[str], fname2path: dict[str, str],
         self.raw: dict = self._merge_includes(raw, self.path)
 
         # Recursively initialize any child bindings. These don't
-        # require a 'compatible' or 'description' to be well defined,
-        # but they must be dicts.
+        # require a 'compatible', 'description' or 'title' to be well
+        # defined, but they must be dicts.
         if "child-binding" in raw:
             if not isinstance(raw["child-binding"], dict):
                 _err(f"malformed 'child-binding:' in {self.path}, "
                      "expected a binding (dictionary with keys/values)")
-            self.child_binding: Optional['Binding'] = Binding(
+            self.child_binding: Optional[Binding] = Binding(
                 path, fname2path,
                 raw=raw["child-binding"],
                 require_compatible=False,
@@ -222,11 +251,11 @@ def __init__(self, path: Optional[str], fname2path: dict[str, str],
             self.child_binding = None
 
         # Make sure this is a well defined object.
-        self._check(require_compatible, require_description)
+        self._check(require_compatible, require_description, require_title)
 
         # Initialize look up tables.
-        self.prop2specs: dict[str, 'PropertySpec'] = {}
-        for prop_name in self.raw.get("properties", {}).keys():
+        self.prop2specs: dict[str, PropertySpec] = {}
+        for prop_name in self.raw.get("properties", {}):
             self.prop2specs[prop_name] = PropertySpec(prop_name, self)
         self.specifier2cells: dict[str, list[str]] = {}
         for key, val in self.raw.items():
@@ -241,6 +270,11 @@ def __repr__(self) -> str:
         basename = os.path.basename(self.path or "")
         return f"<Binding {basename}" + compat + ">"
 
+    @property
+    def title(self) -> Optional[str]:
+        "See the class docstring"
+        return self.raw.get('title')
+
     @property
     def description(self) -> Optional[str]:
         "See the class docstring"
@@ -354,7 +388,8 @@ def _load_raw(self, fname: str) -> dict:
 
         return self._merge_includes(contents, path)
 
-    def _check(self, require_compatible: bool, require_description: bool):
+    def _check(self, require_compatible: bool, require_description: bool,
+               require_title: bool):
         # Does sanity checking on the binding.
 
         raw = self.raw
@@ -368,6 +403,13 @@ def _check(self, require_compatible: bool, require_description: bool):
         elif require_compatible:
             _err(f"missing 'compatible' in {self.path}")
 
+        if "title" in raw:
+            title = raw["title"]
+            if not isinstance(title, str) or not title:
+                _err(f"malformed or empty 'title' in {self.path}")
+        elif require_title:
+            _err(f"missing 'title' in {self.path}")
+
         if "description" in raw:
             description = raw["description"]
             if not isinstance(description, str) or not description:
@@ -377,8 +419,8 @@ def _check(self, require_compatible: bool, require_description: bool):
 
         # Allowed top-level keys. The 'include' key should have been
         # removed by _load_raw() already.
-        ok_top = {"description", "compatible", "bus", "on-bus",
-                  "properties", "child-binding"}
+        ok_top = {"title", "description", "compatible", "bus",
+                  "on-bus", "properties", "child-binding"}
 
         # Descriptive errors for legacy bindings.
         legacy_errors = {
@@ -388,7 +430,6 @@ def _check(self, require_compatible: bool, require_description: bool):
             "parent": "use 'on-bus: <bus>' instead",
             "parent-bus": "use 'on-bus: <bus>' instead",
             "sub-node": "use 'child-binding' instead",
-            "title": "use 'description' instead",
         }
 
         for key in raw:
@@ -421,11 +462,11 @@ def _check(self, require_compatible: bool, require_description: bool):
         self._check_properties()
 
         for key, val in raw.items():
-            if key.endswith("-cells"):
-                if (not isinstance(val, list)
-                    or not all(isinstance(elem, str) for elem in val)):
-                    _err(f"malformed '{key}:' in {self.path}, "
-                         "expected a list of strings")
+            if (key.endswith("-cells")
+                and not isinstance(val, list)
+                or not all(isinstance(elem, str) for elem in val)):
+                _err(f"malformed '{key}:' in {self.path}, "
+                     "expected a list of strings")
 
     def _check_properties(self) -> None:
         # _check() helper for checking the contents of 'properties:'.
@@ -485,7 +526,9 @@ class PropertySpec:
 
     path:
       The file where this property was defined. In case a binding includes
-      other bindings, this is the file where the property was last modified.
+      other bindings, this is the including binding file.
+      Generally this means that this will be the binding file specifying
+      the devicetree node of which this is a property.
 
     type:
       The type of the property as a string, as given in the binding.
@@ -912,6 +955,11 @@ class Node:
       The ordinal is defined for all Nodes, and is unique among nodes in its
       EDT 'nodes' list.
 
+    hash:
+      A hashed value of the devicetree path of the node. This is defined for
+      all Nodes, and is checked for uniqueness among nodes in its EDT 'nodes'
+      list.
+
     required_by:
       A list with the nodes that directly depend on the node
 
@@ -947,8 +995,9 @@ class Node:
 
     props:
       A dict that maps property names to Property objects.
-      Property objects are created for all devicetree properties on the node
-      that are mentioned in 'properties:' in the binding.
+      Property objects are created for the devicetree properties
+      defined by the node's binding and that have a default value
+      or for which a value is set in the DTS.
 
     aliases:
       A list of aliases for the node. This is fetched from the /aliases node.
@@ -1018,7 +1067,7 @@ def __init__(
         self._binding: Optional[Binding] = None
 
         # Public, some of which are initialized properly later:
-        self.edt: 'EDT' = edt
+        self.edt: EDT = edt
         self.dep_ordinal: int = -1
         self.compats: list[str] = compats
         self.ranges: list[Range] = []
@@ -1027,6 +1076,7 @@ def __init__(
         self.interrupts: list[ControllerAndData] = []
         self.pinctrls: list[PinCtrl] = []
         self.bus_node = self._bus_node(support_fixed_partitions_on_any_bus)
+        self.hash: str = _compute_hash(dt_node.path)
 
         self._init_binding()
         self._init_regs()
@@ -1037,6 +1087,16 @@ def name(self) -> str:
         "See the class docstring"
         return self._node.name
 
+    @property
+    def filename(self) -> str:
+        "See the class docstring"
+        return self._node.filename
+
+    @property
+    def lineno(self) -> int:
+        "See the class docstring"
+        return self._node.lineno
+
     @property
     def unit_addr(self) -> Optional[int]:
         "See the class docstring"
@@ -1231,10 +1291,10 @@ def gpio_hogs(self) -> list[ControllerAndData]:
         if "gpio-hog" not in self.props:
             return []
 
-        if not self.parent or not "gpio-controller" in self.parent.props:
+        if not self.parent or "gpio-controller" not in self.parent.props:
             _err(f"GPIO hog {self!r} lacks parent GPIO controller node")
 
-        if not "#gpio-cells" in self.parent._node.props:
+        if "#gpio-cells" not in self.parent._node.props:
             _err(f"GPIO hog {self!r} parent node lacks #gpio-cells")
 
         n_cells = self.parent._node.props["#gpio-cells"].to_num()
@@ -1533,11 +1593,9 @@ def _prop_val(
 
         if prop_type == "boolean":
             if prop.type != Type.EMPTY:
-                _err(
-                    "'{0}' in {1!r} is defined with 'type: boolean' in {2}, "
-                    "but is assigned a value ('{3}') instead of being empty "
-                    "('{0};')".format(name, node, binding_path, prop)
-                )
+                _err(f"'{name}' in {node!r} is defined with 'type: boolean' "
+                     f"in {binding_path}, but is assigned a value ('{prop}') "
+                     f"instead of being empty ('{name};')")
             return True
 
         if prop_type == "int":
@@ -1852,7 +1910,7 @@ def _named_cells(
                  f"{controller._node!r} - {len(cell_names)} "
                  f"instead of {len(data_list)}")
 
-        return dict(zip(cell_names, data_list))
+        return dict(zip(cell_names, data_list, strict=False))
 
 
 class EDT:
@@ -2096,7 +2154,7 @@ def scc_order(self) -> list[list[Node]]:
         try:
             return self._graph.scc_order()
         except Exception as e:
-            raise EDTError(e)
+            raise EDTError(e) from None
 
     def _process_properties_r(self, root_node: Node, props_node: Node) -> None:
         """
@@ -2270,10 +2328,18 @@ def _init_nodes(self) -> None:
         # Creates a list of edtlib.Node objects from the dtlib.Node objects, in
         # self.nodes
 
+        hash2node: dict[str, Node] = {}
+
         for dt_node in self._dt.node_iter():
             # Warning: We depend on parent Nodes being created before their
             # children. This is guaranteed by node_iter().
             node = Node(dt_node, self, self._fixed_partitions_no_bus)
+
+            if node.hash in hash2node:
+                _err(f"hash collision between '{node.path}' and "
+                     f"'{hash2node[node.hash].path}'")
+            hash2node[node.hash] = node
+
             self.nodes.append(node)
             self._node2enode[dt_node] = node
 
@@ -2422,7 +2488,7 @@ def load_vendor_prefixes_txt(vendor_prefixes: str) -> dict[str, str]:
     representation mapping a vendor prefix to the vendor name.
     """
     vnd2vendor: dict[str, str] = {}
-    with open(vendor_prefixes, 'r', encoding='utf-8') as f:
+    with open(vendor_prefixes, encoding='utf-8') as f:
         for line in f:
             line = line.strip()
 
@@ -2449,23 +2515,19 @@ def _dt_compats(dt: DT) -> set[str]:
 
     return {compat
             for node in dt.node_iter()
-                if "compatible" in node.props
-                    for compat in node.props["compatible"].to_strings()}
+            if "compatible" in node.props
+            for compat in node.props["compatible"].to_strings()}
 
 
 def _binding_paths(bindings_dirs: list[str]) -> list[str]:
     # Returns a list with the paths to all bindings (.yaml files) in
     # 'bindings_dirs'
 
-    binding_paths = []
-
-    for bindings_dir in bindings_dirs:
-        for root, _, filenames in os.walk(bindings_dir):
-            for filename in filenames:
-                if filename.endswith(".yaml") or filename.endswith(".yml"):
-                    binding_paths.append(os.path.join(root, filename))
-
-    return binding_paths
+    return [os.path.join(root, filename)
+            for bindings_dir in bindings_dirs
+            for root, _, filenames in os.walk(bindings_dir)
+            for filename in filenames
+            if filename.endswith((".yaml", ".yml"))]
 
 
 def _binding_inc_error(msg):
@@ -2680,11 +2742,12 @@ def _check_prop_by_type(prop_name: str,
         _err(f"'specifier-space' in 'properties: {prop_name}' "
              f"has type '{prop_type}', expected 'phandle-array'")
 
-    if prop_type == "phandle-array":
-        if not prop_name.endswith("s") and not "specifier-space" in options:
-            _err(f"'{prop_name}' in 'properties:' in {binding_path} "
-                 f"has type 'phandle-array' and its name does not end in 's', "
-                 f"but no 'specifier-space' was provided.")
+    if (prop_type == "phandle-array"
+        and not prop_name.endswith("s")
+        and "specifier-space" not in options):
+        _err(f"'{prop_name}' in 'properties:' in {binding_path} "
+             f"has type 'phandle-array' and its name does not end in 's', "
+             f"but no 'specifier-space' was provided.")
 
     # If you change const_types, be sure to update the type annotation
     # for PropertySpec.const.
@@ -2806,7 +2869,7 @@ def _add_names(node: dtlib_Node, names_ident: str, objs: Any) -> None:
                  f"in {node.dt.filename} has {len(names)} strings, "
                  f"expected {len(objs)} strings")
 
-        for obj, name in zip(objs, names):
+        for obj, name in zip(objs, names, strict=False):
             if obj is None:
                 continue
             obj.name = name
@@ -3082,7 +3145,7 @@ def _and(b1: bytes, b2: bytes) -> bytes:
     # Pad on the left, to equal length
     maxlen = max(len(b1), len(b2))
     return bytes(x & y for x, y in zip(b1.rjust(maxlen, b'\xff'),
-                                       b2.rjust(maxlen, b'\xff')))
+                                       b2.rjust(maxlen, b'\xff'), strict=False))
 
 
 def _or(b1: bytes, b2: bytes) -> bytes:
@@ -3092,7 +3155,7 @@ def _or(b1: bytes, b2: bytes) -> bytes:
     # Pad on the left, to equal length
     maxlen = max(len(b1), len(b2))
     return bytes(x | y for x, y in zip(b1.rjust(maxlen, b'\x00'),
-                                       b2.rjust(maxlen, b'\x00')))
+                                       b2.rjust(maxlen, b'\x00'), strict=False))
 
 
 def _not(b: bytes) -> bytes:
@@ -3216,11 +3279,10 @@ def _check_dt(dt: DT) -> None:
                      " (see the devicetree specification)")
 
         ranges_prop = node.props.get("ranges")
-        if ranges_prop:
-            if ranges_prop.type not in (Type.EMPTY, Type.NUMS):
-                _err(f"expected 'ranges = < ... >;' in {node.path} in "
-                     f"{node.dt.filename}, not '{ranges_prop}' "
-                     "(see the devicetree specification)")
+        if ranges_prop and ranges_prop.type not in (Type.EMPTY, Type.NUMS):
+            _err(f"expected 'ranges = < ... >;' in {node.path} in "
+                 f"{node.dt.filename}, not '{ranges_prop}' "
+                  "(see the devicetree specification)")
 
 
 def _err(msg) -> NoReturn:
@@ -3293,7 +3355,8 @@ def _raw_default_property_for(
             for name in _DEFAULT_PROP_TYPES
         },
     },
-    require_compatible=False, require_description=False,
+    require_compatible=False,
+    require_description=False,
 )
 
 _DEFAULT_PROP_SPECS: dict[str, PropertySpec] = {
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/base.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/base.yaml
new file mode 100644
index 00000000000..7535b28b544
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/base.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Base include file for testing bindings initialization.
+#
+# Involves base property definitions ("type:", "description:", "const:",
+# "required:", "enum:" and "default:") up to the grandchild-binding level.
+#
+# Binding:
+#   + prop-1
+#   + prop-2
+#   + prop-enum
+#   + prop-req
+#   + prop-const
+#   + prop-default
+#
+#   Child-binding:
+#     + child-prop-1
+#     + child-prop-2
+#     + child-prop-enum
+#     + child-prop-req
+#     + child-prop-const
+#     + child-prop-default
+#
+#     Grandchild-binding:
+#       + grandchild-prop-1
+#       + grandchild-prop-2
+#       + grandchild-prop-enum
+#       + grandchild-prop-req
+#       + grandchild-prop-const
+#       + grandchild-prop-default
+
+description: Base property specifications.
+
+properties:
+  prop-1:
+    description: Base property 1.
+    type: int
+  prop-2:
+    type: string
+  prop-enum:
+    type: string
+    required: false
+    enum:
+      - FOO
+      - BAR
+  prop-const:
+    type: int
+    const: 8
+  prop-req:
+    type: int
+    required: true
+  prop-default:
+    type: int
+    default: 1
+
+child-binding:
+  description: Base child-binding description.
+
+  properties:
+    child-prop-1:
+      description: Base child-prop 1.
+      type: int
+    child-prop-2:
+      type: string
+    child-prop-enum:
+      type: string
+      required: false
+      enum:
+        - CHILD_FOO
+        - CHILD_BAR
+    child-prop-const:
+      type: int
+      const: 16
+    child-prop-req:
+      type: int
+      required: true
+    child-prop-default:
+      type: int
+      default: 2
+
+  child-binding:
+    description: Base grandchild-binding description.
+
+    properties:
+      grandchild-prop-1:
+        description: Base grandchild-prop 1.
+        type: int
+      grandchild-prop-2:
+        type: string
+      grandchild-prop-enum:
+        type: string
+        required: false
+        enum:
+          - GRANDCHILD_FOO
+          - GRANDCHILD_BAR
+      grandchild-prop-const:
+        type: int
+        const: 32
+      grandchild-prop-req:
+        type: int
+        required: true
+      grandchild-prop-default:
+        type: int
+        default: 3
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/base_amend.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/base_amend.yaml
new file mode 100644
index 00000000000..bd24de099c8
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/base_amend.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Amends base properties specifications:
+# - extends property specifications by adding definitions,
+#   e.g. setting a "default:" value
+# - overwrites existing definitions of a property,
+#   e.g. change its "description:"
+# - specify new properties
+#
+# The same kind of amendments are applied to the same properties
+# at each level (binding, child-binding, grandchild-binding).
+#
+# | Definition     | Extended for | Overwritten for |
+# |----------------|--------------|-----------------|
+# | description:   | prop-2       | prop-1          |
+# | required:      |              | prop-enum       |
+# | enum:          | prop-2       |                 |
+# | const:         | prop-1       |                 |
+# | default:       | prop-2       |                 |
+#
+# Non authorized amendments, e.g. changing a "const:" value
+# or downgrading a "required: true" definition are tested separately.
+
+description: Amended description.
+
+include: base.yaml
+
+properties:
+  prop-1:
+    # The including binding is permitted to overwrite a property description.
+    description: Overwritten description.
+    # The including binding is permitted to set a "const:" value.
+    const: 0xf0
+
+  prop-2:
+    # The including binding is permitted to add a property description.
+    description: New description.
+    # The including binding is permitted to limit property values
+    # to an enumeration.
+    enum:
+      - EXT_FOO
+      - EXT_BAR
+    # The including binding is permitted to set a default value.
+    default: EXT_FOO
+
+  # The including binding is permitted to promote a property
+  # to requirement.
+  prop-enum:
+    required: true
+
+  # The including binding is permitted to define a new property.
+  prop-new:
+    type: int
+
+# Same amendments at the child-binding level.
+child-binding:
+  properties:
+    child-prop-1:
+      description: Overwritten description (child).
+      const: 0xf1
+
+    child-prop-2:
+      description: New description (child).
+      enum:
+        - CHILD_EXT_FOO
+        - CHILD_EXT_BAR
+      default: CHILD_EXT_FOO
+
+    child-prop-enum:
+      required: true
+
+    child-prop-new:
+      type: int
+
+  # Same amendments at the grandchild-binding level.
+  child-binding:
+    # Plus amended grandchild-binding description.
+    description: Amended grandchild-binding description.
+
+    properties:
+      grandchild-prop-1:
+        description: Overwritten description (grandchild).
+        const: 0xf2
+
+      grandchild-prop-2:
+        description: New description (grandchild).
+        enum:
+          - GRANDCHILD_EXT_FOO
+          - GRANDCHILD_EXT_BAR
+        default: GRANDCHILD_EXT_FOO
+
+      grandchild-prop-enum:
+        required: true
+
+      grandchild-prop-new:
+        type: int
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/base_inherit.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/base_inherit.yaml
new file mode 100644
index 00000000000..eec7711c7a4
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/base_inherit.yaml
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Inherit base specifications without modification.
+
+include: base.yaml
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/base_multi.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/base_multi.yaml
new file mode 100644
index 00000000000..7165dd16e91
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/base_multi.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Includes base bindings at multiple levels (binding,
+# child-binding, grandchild-binding):
+#
+#   include: base.yaml
+#   child-binding:
+#     include: base.yaml
+#     child-binding:
+#       include: base.yaml
+#
+# Which properties are specified at which levels is summarized below
+# for convenience.
+#
+# Child-binding level:
+#   From top-level "include:" element.
+#   - child-prop-1 (amended)
+#   - child-prop-2
+#   - child-prop-enum
+#   From "child-binding: include:" element.
+#   - prop-1 (amended)
+#   - prop-2 (amended)
+#   - prop-enum (amended)
+#
+# Grandchild-binding level:
+#   From top-level "include:" element.
+#   - grandchild-prop-1 (amended)
+#   - grandchild-prop-2
+#   - grandchild-prop-enum
+#   From "child-binding: include:" element.
+#   - child-prop-1 (amended)
+#   - child-prop-2
+#   - child-prop-enum
+#   From "child-binding: child-binding: include:" element.
+#   - prop-1 (amended)
+#   - prop-2 (amended)
+#   - prop-enum (amended)
+#
+# Grand-grandchild-binding level:
+#   From "child-binding: include:" element.
+#   - child-prop-1
+#   - child-prop-2
+#   - child-prop-enum
+#   From "child-binding: child-binding: include:" element.
+#   - grandchild-prop-1
+#   - grandchild-prop-2
+#   - grandchild-prop-enum
+
+description: Description of 'base_multi.yaml'.
+
+include:
+  - name: base.yaml
+    child-binding:
+      property-allowlist: [child-prop-1, child-prop-2, child-prop-enum]
+      child-binding:
+        property-allowlist: [grandchild-prop-1, grandchild-prop-2, grandchild-prop-enum]
+
+child-binding:
+  include:
+    - name: base.yaml
+      property-allowlist: [prop-1, prop-2, prop-enum]
+      child-binding:
+        property-allowlist: [child-prop-1, child-prop-2, child-prop-enum]
+        child-binding:
+          property-allowlist: [grandchild-prop-1, grandchild-prop-2, grandchild-prop-enum]
+
+  properties:
+    # Amend top-level "include:" element.
+    child-prop-1:
+      const: 0xf1
+    # Amend this "child-binding: include:" element.
+    prop-1:
+      const: 0xf1
+    prop-2:
+      description: New description (child).
+    prop-enum:
+      required: true
+      default: FOO
+
+  child-binding:
+    include:
+      - name: base.yaml
+        property-allowlist: [prop-1, prop-2, prop-enum]
+        child-binding:
+          property-allowlist: [child-prop-1, child-prop-2, child-prop-enum]
+          child-binding:
+            property-allowlist: [grandchild-prop-1, grandchild-prop-2, grandchild-prop-enum]
+
+    properties:
+      # Amend above top-level "include:" element.
+      grandchild-prop-1:
+        const: 0xf2
+      # Amend above "child-binding: include:" element.
+      child-prop-1:
+        const: 0xf2
+      # Amend this "child-binding: child-binding: include:" element.
+      prop-1:
+        const: 0xf2
+      prop-2:
+        description: New description (grandchild).
+      prop-enum:
+        required: true
+        default: FOO
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/compat_desc.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/compat_desc.yaml
new file mode 100644
index 00000000000..1bd5bce1c81
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/compat_desc.yaml
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Test inheritance rules applied to compatible strings
+# and bindings descriptions.
+
+description: Binding description.
+
+compatible: vnd,compat-desc
+
+include: compat_desc_base.yaml
+
+child-binding:
+  description: Child-binding description.
+  compatible: vnd,child-compat-desc
+
+  child-binding:
+    description: Grandchild-binding description.
+    compatible: vnd,grandchild-compat-desc
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/compat_desc_base.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/compat_desc_base.yaml
new file mode 100644
index 00000000000..263b5adcbb9
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/compat_desc_base.yaml
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Base file for testing inheritance rules applied to
+# compatible strings and bindings descriptions.
+
+description: Binding description (base).
+
+compatible: vnd,compat-desc-base
+
+child-binding:
+  description: Child-binding description (base).
+  compatible: vnd,child-compat-desc-base
+
+  child-binding:
+    description: Grandchild-binding description (base).
+    compatible: vnd,grandchild-compat-desc-base
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/compat_desc_multi.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/compat_desc_multi.yaml
new file mode 100644
index 00000000000..fc7fdd95eae
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/compat_desc_multi.yaml
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Test consequences of inclusion order on inherited
+# compatible strings and descriptions.
+
+description: Binding description (multi).
+
+compatible: vnd,compat-desc-multi
+
+# Descriptions at the child-binding level and below
+# will depend on inclusion order: the first wins.
+include:
+  - compat_desc_base.yaml
+  - compat_desc.yaml
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/diamond.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/diamond.yaml
new file mode 100644
index 00000000000..dfd573e1a19
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/diamond.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Binding file for testing diamond inheritance (top-bottom).
+#
+#                diamond.yaml
+#                  /    \
+#                 /      \
+#   base_amend.yaml      thing.yaml
+#                \         /
+#                 \       /
+#                 base.yaml
+#
+# Which properties are specified at which levels is summarized below
+# for convenience.
+#
+# * Binding level.
+#   Diamond's left:
+#   - prop-1 (amended in base_amend.yaml)
+#   - prop-enum (amended in base_amend.yaml)
+#   - prop-default (inherited from base.yaml)
+#   Diamond's right:
+#   - prop-1 (last amended in thing.yaml)
+#   - prop-enum (amended in thing.yaml)
+#   - prop-thing (inherited from thing.yaml)
+#   Diamond's top:
+#   - prop-enum (last amended here)
+#   - prop-diamond
+#
+# * Child-binding level:
+#   Diamond's left:
+#   - child-prop-1 (amended in base_amend.yaml)
+#   - child-prop-enum (amended in base_amend.yaml)
+#   - child-prop-default (inherited from base.yaml)
+#   Diamond's right:
+#   - child-prop-1 (last amended in thing.yaml)
+#   - child-prop-enum (amended in thing.yaml)
+#   - child-prop-thing (inherited from thing.yaml)
+#   Diamond's top:
+#   - child-prop-enum (last amended here)
+#   - child-prop-diamond
+#
+# * Grandchild-binding level:
+#   Diamond's left:
+#   - grandchild-prop-1 (amended in base_amend.yaml)
+#   - grandchild-prop-enum (amended in base_amend.yaml)
+#   - grandchild-prop-default (inherited from base.yaml)
+#   Diamond's right:
+#   - grandchild-prop-1 (last amended in thing.yaml)
+#   - grandchild-prop-enum (amended in thing.yaml)
+#   - grandchild-prop-thing (inherited from thing.yaml)
+#   Diamond's top:
+#   - grandchild-prop-enum (last amended here)
+#   - grandchild-prop-diamond
+
+description: Diamond's top.
+
+compatible: diamond
+
+include:
+  # Diamond's left.
+  - name: base_amend.yaml
+    property-allowlist: [prop-1, prop-enum, prop-default]
+    child-binding:
+      property-allowlist: [child-prop-1, child-prop-enum, child-prop-default]
+      child-binding:
+        property-allowlist: [grandchild-prop-1, grandchild-prop-enum, grandchild-prop-default]
+  # Diamond's right.
+  - name: thing.yaml
+
+properties:
+  prop-diamond:
+    type: int
+  prop-enum:
+    description: Overwritten in diamond.yaml.
+    default: FOO
+
+child-binding:
+  description: Diamond's child-binding.
+
+  properties:
+    child-prop-diamond:
+      type: int
+    child-prop-enum:
+      description: Overwritten in diamond.yaml (child).
+      default: CHILD_FOO
+
+  child-binding:
+    properties:
+      grandchild-prop-diamond:
+        type: int
+      grandchild-prop-enum:
+        description: Overwritten in diamond.yaml (grandchild).
+        default: GRANDCHILD_FOO
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/filter_allows_notblocked.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/filter_allows_notblocked.yaml
new file mode 100644
index 00000000000..1af2b2d3463
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/filter_allows_notblocked.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# This binding file allows a property which is not blocked
+# in simple_blocklist.yaml: we should end up with this property.
+
+include:
+  - name: simple_blocklist.yaml
+    property-allowlist: [prop-2]
+    child-binding:
+      property-allowlist: [child-prop-2]
+      child-binding:
+        property-allowlist: [grandchild-prop-2]
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/filter_among_allowed.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/filter_among_allowed.yaml
new file mode 100644
index 00000000000..3faa647926b
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/filter_among_allowed.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# This binding file allows only properties that are not allowed
+# in simple_allowlist.yaml: we should end up with no property at all.
+
+include:
+  - name: simple_allowlist.yaml
+    property-allowlist: [prop-3]
+    child-binding:
+      property-allowlist: [child-prop-3]
+      child-binding:
+        property-allowlist: [grandchild-prop-3]
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/filter_among_notblocked.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/filter_among_notblocked.yaml
new file mode 100644
index 00000000000..873f762ed1d
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/filter_among_notblocked.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# This binding file blocks all properties not blocked
+# in simple_filter.yaml: we should end up with no property at all.
+
+include:
+  - name: simple_blocklist.yaml
+    property-blocklist: [prop-2, prop-3]
+    child-binding:
+      property-blocklist: [child-prop-2, child-prop-3]
+      child-binding:
+        property-blocklist: [grandchild-prop-2, grandchild-prop-3]
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_child_propconst.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_child_propconst.yaml
new file mode 100644
index 00000000000..20739bad14a
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_child_propconst.yaml
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# This binding should not try to override the "const:" value
+# in a property specification inherited from an included file.
+
+include: base.yaml
+
+child-binding:
+  properties:
+    child-prop-const:
+      const: 999
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_child_propdefault.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_child_propdefault.yaml
new file mode 100644
index 00000000000..fd1ec813612
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_child_propdefault.yaml
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# This binding should not try to override the "default:" value
+# in a property specification inherited from an included file.
+
+include: base.yaml
+
+child-binding:
+  properties:
+    child-prop-default:
+      default: 999
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_child_propenum.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_child_propenum.yaml
new file mode 100644
index 00000000000..73947b3007e
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_child_propenum.yaml
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# This binding should not try to change the "enum:" values
+# in a property specification inherited from an included file.
+
+include: base.yaml
+
+child-binding:
+  properties:
+    child-prop-enum:
+      enum:
+        - OTHER_FOO
+        - OTHER_BAR
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_child_propreq.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_child_propreq.yaml
new file mode 100644
index 00000000000..298a3624ffb
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_child_propreq.yaml
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# This binding should not try to override "required: true"
+# in a property specification inherited from an included file.
+
+include: base.yaml
+
+child-binding:
+  properties:
+    child-prop-req:
+      required: false
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_child_proptype.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_child_proptype.yaml
new file mode 100644
index 00000000000..8f80ec81e38
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_child_proptype.yaml
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# This binding should not try to override the "type:"
+# of an inherited property.
+
+include: base.yaml
+
+child-binding:
+  properties:
+    child-prop-1:
+      type: string
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_grandchild_propconst.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_grandchild_propconst.yaml
new file mode 100644
index 00000000000..5b8a1cb0d51
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_grandchild_propconst.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# This binding should not try to override the "const:" value
+# in a property specification inherited from an included file.
+
+include: base.yaml
+
+child-binding:
+  child-binding:
+    properties:
+      grandchild-prop-const:
+        const: 999
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_grandchild_propdefault.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_grandchild_propdefault.yaml
new file mode 100644
index 00000000000..f2f69d31e4b
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_grandchild_propdefault.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# This binding should not try to override the "default:" value
+# in a property specification inherited from an included file.
+
+include: base.yaml
+
+child-binding:
+  child-binding:
+    properties:
+      grandchild-prop-default:
+        default: 999
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_grandchild_propenum.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_grandchild_propenum.yaml
new file mode 100644
index 00000000000..637ba811e3d
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_grandchild_propenum.yaml
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# This binding should not try to change the "enum:" values
+# in a property specification inherited from an included file.
+
+include: base.yaml
+
+child-binding:
+  child-binding:
+    properties:
+      grandchild-prop-enum:
+        enum:
+          - OTHER_FOO
+          - OTHER_BAR
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_grandchild_propreq.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_grandchild_propreq.yaml
new file mode 100644
index 00000000000..dc9273a7adc
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_grandchild_propreq.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# This binding should not try to override "required: true"
+# in a property specification inherited from an included file.
+
+include: base.yaml
+
+child-binding:
+  child-binding:
+    properties:
+      grandchild-prop-req:
+        required: false
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_grandchild_proptype.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_grandchild_proptype.yaml
new file mode 100644
index 00000000000..4135db67f1d
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_grandchild_proptype.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# This binding should not try to override the "type:"
+# of an inherited property.
+
+include: base.yaml
+
+child-binding:
+  child-binding:
+    properties:
+      grandchild-prop-1:
+        type: string
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_propconst.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_propconst.yaml
new file mode 100644
index 00000000000..9eaa11e31d5
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_propconst.yaml
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# This binding should not try to override the "const:" value
+# in a property specification inherited from an included file.
+#
+# Bindings, child-bindings and grandchild-bindings have
+# to be tested separately, see also:
+# - invalid_child_propconst.yaml
+# - invalid_grandchild_propconst.yaml
+
+include: base.yaml
+
+properties:
+  prop-const:
+    const: 999
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_propdefault.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_propdefault.yaml
new file mode 100644
index 00000000000..8b621a24098
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_propdefault.yaml
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# This binding should not try to override the "default:" value
+# in a property specification inherited from an included file.
+#
+# Bindings, child-bindings and grandchild-bindings have
+# to be tested separately, see also:
+# - invalid_child_propdefault.yaml
+# - invalid_grandchild_propdefault.yaml
+
+include: base.yaml
+
+properties:
+  prop-default:
+    default: 999
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_propenum.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_propenum.yaml
new file mode 100644
index 00000000000..38839826536
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_propenum.yaml
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# This binding should not try to change the "enum:" values
+# in a property specification inherited from an included file.
+#
+# Bindings, child-bindings and grandchild-bindings have
+# to be tested separately, see also:
+# - invalid_child_propenum.yaml
+# - invalid_grandchild_propenum.yaml
+
+include: base.yaml
+
+properties:
+  prop-enum:
+    enum:
+      - OTHER_FOO
+      - OTHER_BAR
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_propreq.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_propreq.yaml
new file mode 100644
index 00000000000..fd0412c505b
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_propreq.yaml
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# This binding should not try to override "required: true"
+# in a property specification inherited from an included file.
+#
+# Bindings, child-bindings and grandchild-bindings have
+# to be tested separately, see also:
+# - invalid_child_propreq.yaml
+# - invalid_grandchild_propreq.yaml
+
+include: base.yaml
+
+properties:
+  prop-req:
+    required: false
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_proptype.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_proptype.yaml
new file mode 100644
index 00000000000..fca2c752676
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/invalid_proptype.yaml
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# This binding should not try to override the "type:"
+# of an inherited property.
+#
+# Bindings, child-bindings and grandchild-bindings have
+# to be tested separately, see also:
+# - invalid_child_protype.yaml
+# - invalid_grandchild_proptype.yaml
+
+include: base.yaml
+
+properties:
+  prop-1:
+    type: string
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/simple.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/simple.yaml
new file mode 100644
index 00000000000..27f6ce8120d
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/simple.yaml
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Base properties for testing property filters propagation
+# up to the grandchild-binding level.
+
+properties:
+  prop-1:
+    type: int
+  prop-2:
+    type: int
+  prop-3:
+    type: int
+
+child-binding:
+  properties:
+    child-prop-1:
+      type: int
+    child-prop-2:
+      type: int
+    child-prop-3:
+      type: int
+
+  child-binding:
+    properties:
+      grandchild-prop-1:
+        type: int
+      grandchild-prop-2:
+        type: int
+      grandchild-prop-3:
+        type: int
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/simple_allowlist.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/simple_allowlist.yaml
new file mode 100644
index 00000000000..7294393a2a2
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/simple_allowlist.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Filter inherited property specifications
+# up to the grandchild-binding level.
+
+include:
+  - name: simple_inherit.yaml
+    property-allowlist: [prop-1, prop-2]
+    child-binding:
+      property-allowlist: [child-prop-1, child-prop-2]
+      child-binding:
+        property-allowlist: [grandchild-prop-1, grandchild-prop-2]
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/simple_blocklist.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/simple_blocklist.yaml
new file mode 100644
index 00000000000..c9d581e2c07
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/simple_blocklist.yaml
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Filter inherited property specifications
+# up to the grandchild-binding level.
+
+include:
+  - name: simple_inherit.yaml
+    property-blocklist: [prop-1]
+    child-binding:
+      property-blocklist: [child-prop-1]
+      child-binding:
+        property-blocklist: [grandchild-prop-1]
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/simple_inherit.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/simple_inherit.yaml
new file mode 100644
index 00000000000..8a95ef38f95
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/simple_inherit.yaml
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Inherits property specifications without modification.
+
+include: simple.yaml
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/thing.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/thing.yaml
new file mode 100644
index 00000000000..82a31aaa391
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/thing.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Right (included last) YAML file for testing diamond inheritance.
+#
+# Amends base.yaml.
+#
+# Binding level:
+# - prop-1 (amended)
+# - prop-enum (amended)
+# - prop-thing (new property)
+#
+# Child-binding level:
+#  - child-prop-1 (amended)
+#  - child-prop-enum (amended)
+#  - child-prop-thing (new property)
+#
+# Grandchild-binding level:
+#   - grandchild-prop-1 (amended)
+#   - grandchild-prop-enum (amended)
+#   - grandchild-prop-thing (new property)
+
+description: Description of 'thing.yaml'.
+
+include:
+  - name: base.yaml
+    property-allowlist: [prop-1, prop-enum]
+    child-binding:
+      property-allowlist: [child-prop-1, child-prop-enum]
+      child-binding:
+        property-allowlist: [grandchild-prop-1, grandchild-prop-enum]
+
+properties:
+  prop-1:
+    default: 1
+    # Diamond inheritance in diamond.yaml: should overwrite
+    # the amended description from base_amend.yaml.
+    description: Overwritten in thing.yaml.
+
+  prop-enum:
+    # This is the definition inherited from base.yaml.
+    #
+    # Diamond inheritance in diamond.yaml: should be ORed
+    # with the definition inherited via base_amend.yaml.
+    required: false
+
+  prop-thing:
+    description: Thing property.
+    type: int
+
+child-binding:
+  description: Child-binding description (thing).
+  properties:
+    child-prop-1:
+      description: Overwritten in thing.yaml (child).
+      default: 2
+    child-prop-enum:
+      required: false
+    child-prop-thing:
+      description: Thing child-binding property.
+      type: int
+
+  child-binding:
+    description: Grandchild-binding description (thing).
+    properties:
+      grandchild-prop-1:
+        description: Overwritten in thing.yaml (grandchild).
+        default: 3
+      grandchild-prop-enum:
+        required: false
+      grandchild-prop-thing:
+        description: Thing grandchild-binding property.
+        type: int
diff --git a/scripts/dts/python-devicetree/tests/test-bindings-init/vnd,thing.yaml b/scripts/dts/python-devicetree/tests/test-bindings-init/vnd,thing.yaml
new file mode 100644
index 00000000000..30015716a7d
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test-bindings-init/vnd,thing.yaml
@@ -0,0 +1,20 @@
+# SPDX-License-Identifier: BSD-3-Clause
+#
+# Top level binding file (device binding) for testing
+# descriptions and compatible strings.
+
+description: The Thing device.
+
+compatible: "vnd,thing"
+
+include:
+  - name: base_amend.yaml
+  - name: thing.yaml
+
+child-binding:
+  compatible: "vnd,thing-child"
+  description: The Thing's child-binding.
+
+  child-binding:
+    compatible: "vnd,thing-grandchild"
+    description: The Thing's grandchild-binding.
diff --git a/scripts/dts/python-devicetree/tests/test-bindings/defaults.yaml b/scripts/dts/python-devicetree/tests/test-bindings/defaults.yaml
index 4d3cfda3067..0a9b63a87ae 100644
--- a/scripts/dts/python-devicetree/tests/test-bindings/defaults.yaml
+++ b/scripts/dts/python-devicetree/tests/test-bindings/defaults.yaml
@@ -1,5 +1,7 @@
 # SPDX-License-Identifier: BSD-3-Clause
 
+title: Test binding
+
 description: Property default value test
 
 compatible: "defaults"
diff --git a/scripts/dts/python-devicetree/tests/test_dtlib.py b/scripts/dts/python-devicetree/tests/test_dtlib.py
index bf80e85638f..c16e1eae688 100644
--- a/scripts/dts/python-devicetree/tests/test_dtlib.py
+++ b/scripts/dts/python-devicetree/tests/test_dtlib.py
@@ -2499,3 +2499,59 @@ def test_move_node():
     with dtlib_raises("can't move '/newpath' to '/foo/bar': "
                       "parent node '/foo' doesn't exist"):
         dt.move_node(parent, '/foo/bar')
+
+def test_filename_and_lineno():
+    """Test that filename and lineno are correctly tracked for nodes and properties."""
+
+    with tempfile.TemporaryDirectory() as tmpdir:
+        included_file = os.path.join(tmpdir, 'included.dtsi')
+        with open(included_file, 'w') as f:
+            f.write('''/* a new node */
+/ {
+	node1: test-node1 {
+		prop1A = "value1A";
+	};
+};
+''')
+
+        main_file = os.path.join(tmpdir, 'test_with_include.dts')
+        with open(main_file, 'w') as f:
+            f.write('''/dts-v1/;
+
+/include/ "included.dtsi"
+
+/ {
+	node2: test-node2 {
+		prop2A = "value2A";
+		prop2B = "value2B";
+	};
+};
+
+&node1 {
+	prop1B = "value1B";
+};
+''')
+
+        dt = dtlib.DT(main_file, include_path=[tmpdir])
+
+        test_node2 = dt.get_node('/test-node2')
+        prop2A = test_node2.props['prop2A']
+        prop2B = test_node2.props['prop2B']
+
+        assert os.path.samefile(test_node2.filename, main_file)
+        assert test_node2.lineno == 6
+        assert os.path.samefile(prop2A.filename, main_file)
+        assert prop2A.lineno == 7
+        assert os.path.samefile(prop2B.filename, main_file)
+        assert prop2B.lineno == 8
+
+        test_node1 = dt.get_node('/test-node1')
+        prop1A = test_node1.props['prop1A']
+        prop1B = test_node1.props['prop1B']
+
+        assert os.path.samefile(test_node1.filename, included_file)
+        assert test_node1.lineno == 3
+        assert os.path.samefile(prop1A.filename, included_file)
+        assert prop1A.lineno == 4
+        assert os.path.samefile(prop1B.filename, main_file)
+        assert prop1B.lineno == 13
diff --git a/scripts/dts/python-devicetree/tests/test_edtlib.py b/scripts/dts/python-devicetree/tests/test_edtlib.py
index 30fbc7c3fc3..8c826225c9b 100644
--- a/scripts/dts/python-devicetree/tests/test_edtlib.py
+++ b/scripts/dts/python-devicetree/tests/test_edtlib.py
@@ -531,6 +531,20 @@ def test_bus():
     assert str(edt.get_node("/buses/foo-bus/node1/nested").binding_path) == \
         hpath("test-bindings/device-on-foo-bus.yaml")
 
+def test_binding_top_key():
+    fname2path = {'include.yaml': 'test-bindings-include/include.yaml',
+                  'include-2.yaml': 'test-bindings-include/include-2.yaml'}
+
+    with from_here():
+        binding = edtlib.Binding("test-bindings/defaults.yaml", fname2path)
+    title = binding.title
+    description = binding.description
+    compatible = binding.compatible
+
+    assert title == "Test binding"
+    assert description == "Property default value test"
+    assert compatible == "defaults"
+
 def test_child_binding():
     '''Test 'child-binding:' in bindings'''
     with from_here():
diff --git a/scripts/dts/python-devicetree/tests/test_edtlib_binding_init.py b/scripts/dts/python-devicetree/tests/test_edtlib_binding_init.py
new file mode 100644
index 00000000000..d4ded2965c3
--- /dev/null
+++ b/scripts/dts/python-devicetree/tests/test_edtlib_binding_init.py
@@ -0,0 +1,1160 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2024 Christophe Dufaza
+
+"""Unit tests dedicated to edtlib.Binding objects initialization.
+
+Running the assumption that any (valid) YAML binding file is
+something we can make a Binding instance with:
+- check which properties are defined at which level (binding, child-binding,
+  grandchild-binding, etc) and their specifications once the binding
+  is initialized
+- check how including bindings are permitted to specialize
+  the specifications of inherited properties
+- check the rules applied when overwriting a binding's description
+  or compatible string (at the binding, child-binding, etc, levels)
+
+At any level, an including binding is permitted to:
+- filter the properties it chooses to inherit with either "property:allowlist"
+  or "property:blocklist" but not both
+- extend inherited properties:
+  - override (implicit or) explicit "required: false" with "required: true"
+  - add constraints to the possible value(s) of a property with "const:"
+    or "enum:"
+  - add a "default:" value to a property
+  - add or overwrite a property's "description:"; when overwritten multiple
+    times by several included binding files, "include:"ed first "wins"
+- define new properties
+
+At any level, an including binding is NOT permitted to:
+- remove a requirement by overriding "required: true" with "required: false"
+- change existing constrains applied to the possible values of
+  an inherited property with "const:" or "enum:"
+- change the "default:" value of an inherited property
+- change the "type:" of an inherited property
+
+Rules applying to bindings' descriptions and compatible strings:
+- included files can't overwrite the description or compatible string set
+  by the including binding (despite that "description:" appears before
+  "include:"): this seems consistent, the top-level binding file "wins"
+- an including binding can overwrite descriptions and compatible strings
+  inherited at the child-binding levels: this seems consistent,
+  the top-level binding file "wins"
+- when we include multiple files overwriting a description or compatible
+  string inherited at the child-binding levels, order of inclusion matters,
+  the first "wins"; this is consistent with property descriptions
+
+For all tests, the entry point is a Binding instance initialized
+by loading the YAML file which represents the test case: our focus here
+really is what happens when we (recursively) call Binding's constructor,
+independently of any actual devicetree model (edtlib.EDT instance).
+"""
+
+# pylint: disable=too-many-statements
+
+import contextlib
+import os
+from collections.abc import Generator
+from typing import Any
+
+import pytest
+from devicetree import edtlib
+
+YAML_KNOWN_BASE_BINDINGS: dict[str, str] = {
+    # Base properties, bottom of the diamond test case.
+    "base.yaml": "test-bindings-init/base.yaml",
+    # Amended properties, left (first) "include:" in the diamond test case.
+    "base_amend.yaml": "test-bindings-init/base_amend.yaml",
+    # Amended properties, right (last) "include:" in the diamond test case.
+    "thing.yaml": "test-bindings-init/thing.yaml",
+    # Used for testing property filters when "A includes B includes C".
+    "simple.yaml": "test-bindings-init/simple.yaml",
+    "simple_inherit.yaml": "test-bindings-init/simple_inherit.yaml",
+    "simple_allowlist.yaml": "test-bindings-init/simple_allowlist.yaml",
+    "simple_blocklist.yaml": "test-bindings-init/simple_blocklist.yaml",
+    # Test applied rules for compatible strings and descriptions.
+    "compat_desc_base.yaml": "test-bindings-init/compat_desc_base.yaml",
+    "compat_desc.yaml": "test-bindings-init/compat_desc.yaml",
+}
+
+
+def load_binding(path: str) -> edtlib.Binding:
+    """Load YAML file as Binding instance,
+    using YAML_BASE to resolve includes.
+
+    Args:
+        path: Path relative to ZEPHYR_BASE/scripts/dts/python-devicetree/tests.
+    """
+    with _from_here():
+        binding = edtlib.Binding(
+            path=path,
+            fname2path=YAML_KNOWN_BASE_BINDINGS,
+            raw=None,
+            require_compatible=False,
+            require_description=False,
+        )
+    return binding
+
+
+def child_binding_of(path: str) -> edtlib.Binding:
+    """Load YAML file as Binding instance, and returns its child-binding.
+    The child-binding must exist.
+
+    Args:
+        path: Path relative to ZEPHYR_BASE/scripts/dts/python-devicetree/tests.
+    """
+    binding = load_binding(path)
+    assert binding.child_binding
+    return binding.child_binding
+
+
+def grandchild_binding_of(path: str) -> edtlib.Binding:
+    """Load YAML file as Binding instance, and returns its grandchild-binding.
+    The grandchild-binding must exist.
+
+    Args:
+        path: Path relative to ZEPHYR_BASE/scripts/dts/python-devicetree/tests.
+    """
+    child_binding = child_binding_of(path)
+    assert child_binding.child_binding
+    return child_binding.child_binding
+
+
+def verify_expected_propspec(
+    propspec: edtlib.PropertySpec,
+    /,
+    *,
+    # Most properties are integers.
+    expect_type: str = "int",
+    expect_req: bool = False,
+    expect_desc: str | None = None,
+    expect_enum: list[int | str] | None = None,
+    expect_const: Any | None = None,
+    expect_default: Any | None = None,
+) -> None:
+    """Compare a property specification with the definitions
+    we (finally) expect.
+
+    All definitions are tested for equality.
+
+    Args:
+        propsec: The property specification to verify.
+        expect_type: The expected property type definition.
+        expect_req: Whether the property is expected to be required.
+        expect_desc: The expected property description.
+        expect_enum: The expected property "enum:" definition.
+        expect_const: The expected property "const:" definition.
+        expect_default: The expected property "default:" definition.
+    """
+    assert expect_type == propspec.type
+    assert expect_req == propspec.required
+    assert expect_desc == propspec.description
+    assert expect_enum == propspec.enum
+    assert expect_const == propspec.const
+    assert expect_default == propspec.default
+
+
+def verify_binding_propspecs_consistency(binding: edtlib.Binding) -> None:
+    """Verify consistency between what's in Binding.prop2specs
+    and Binding.raw.
+
+    Asserts that:
+        Binding.raw["properties"][prop] == Binding.prop2specs[prop]._raw
+
+    If the binding has a child-binding, also recursively verify child-bindings.
+
+    NOTE: do not confuse with binding.prop2specs[prop].binding == binding,
+    which we do not assume here.
+    """
+    if binding.prop2specs:
+        assert set(binding.raw["properties"].keys()) == set(binding.prop2specs.keys())
+        assert all(
+            binding.raw["properties"][prop] == propspec._raw
+            for prop, propspec in binding.prop2specs.items()
+        )
+    if binding.child_binding:
+        verify_binding_propspecs_consistency(binding.child_binding)
+
+
+def test_expect_propspecs_inherited_bindings() -> None:
+    """Test the basics of including property specifications.
+
+    Specifications are simply inherited without modifications
+    up to the grandchild-binding level.
+
+    Check that we actually inherit all expected definitions as-is.
+    """
+    binding = load_binding("test-bindings-init/base_inherit.yaml")
+
+    # Binding level.
+    assert {
+        "prop-1",
+        "prop-2",
+        "prop-enum",
+        "prop-req",
+        "prop-const",
+        "prop-default",
+    } == set(binding.prop2specs.keys())
+    propspec = binding.prop2specs["prop-1"]
+    verify_expected_propspec(propspec, expect_desc="Base property 1.")
+    propspec = binding.prop2specs["prop-2"]
+    verify_expected_propspec(propspec, expect_type="string")
+    propspec = binding.prop2specs["prop-enum"]
+    verify_expected_propspec(propspec, expect_type="string", expect_enum=["FOO", "BAR"])
+    propspec = binding.prop2specs["prop-const"]
+    verify_expected_propspec(propspec, expect_const=8)
+    propspec = binding.prop2specs["prop-req"]
+    verify_expected_propspec(propspec, expect_req=True)
+    propspec = binding.prop2specs["prop-default"]
+    verify_expected_propspec(propspec, expect_default=1)
+
+    # Child-Binding level.
+    assert binding.child_binding
+    child_binding = binding.child_binding
+    assert {
+        "child-prop-1",
+        "child-prop-2",
+        "child-prop-enum",
+        "child-prop-req",
+        "child-prop-const",
+        "child-prop-default",
+    } == set(child_binding.prop2specs.keys())
+    propspec = child_binding.prop2specs["child-prop-1"]
+    verify_expected_propspec(propspec, expect_desc="Base child-prop 1.")
+    propspec = child_binding.prop2specs["child-prop-2"]
+    verify_expected_propspec(propspec, expect_type="string")
+    propspec = child_binding.prop2specs["child-prop-enum"]
+    verify_expected_propspec(propspec, expect_type="string", expect_enum=["CHILD_FOO", "CHILD_BAR"])
+    propspec = child_binding.prop2specs["child-prop-const"]
+    verify_expected_propspec(propspec, expect_const=16)
+    propspec = child_binding.prop2specs["child-prop-req"]
+    verify_expected_propspec(propspec, expect_req=True)
+    propspec = child_binding.prop2specs["child-prop-default"]
+    verify_expected_propspec(propspec, expect_default=2)
+
+    # GrandChild-Binding level.
+    assert child_binding.child_binding
+    grandchild_binding = child_binding.child_binding
+    assert {
+        "grandchild-prop-1",
+        "grandchild-prop-2",
+        "grandchild-prop-enum",
+        "grandchild-prop-req",
+        "grandchild-prop-const",
+        "grandchild-prop-default",
+    } == set(grandchild_binding.prop2specs.keys())
+    propspec = grandchild_binding.prop2specs["grandchild-prop-1"]
+    verify_expected_propspec(propspec, expect_desc="Base grandchild-prop 1.")
+    propspec = grandchild_binding.prop2specs["grandchild-prop-2"]
+    verify_expected_propspec(propspec, expect_type="string")
+    propspec = grandchild_binding.prop2specs["grandchild-prop-enum"]
+    verify_expected_propspec(
+        propspec,
+        expect_type="string",
+        expect_enum=["GRANDCHILD_FOO", "GRANDCHILD_BAR"],
+    )
+    propspec = grandchild_binding.prop2specs["grandchild-prop-const"]
+    verify_expected_propspec(propspec, expect_const=32)
+    propspec = grandchild_binding.prop2specs["grandchild-prop-req"]
+    verify_expected_propspec(propspec, expect_req=True)
+    propspec = grandchild_binding.prop2specs["grandchild-prop-default"]
+    verify_expected_propspec(propspec, expect_default=3)
+
+
+def test_expect_propspecs_amended_bindings() -> None:
+    """Test the basics of including and amending property specifications.
+
+    Base specifications are included once at the binding level:
+
+        include: base.yaml
+        properties:
+          # Amend base.yaml
+        child-binding:
+          properties:
+            # Amend base.yaml
+          child-binding:
+            properties:
+              # Amend base.yaml
+
+    Check that we finally get the expected property specifications
+    up to the grandchild-binding level.
+    """
+    binding = load_binding("test-bindings-init/base_amend.yaml")
+
+    # Binding level.
+    #
+    assert {
+        "prop-1",
+        "prop-2",
+        "prop-enum",
+        "prop-req",
+        "prop-const",
+        "prop-default",
+        "prop-new",
+    } == set(binding.prop2specs.keys())
+    propspec = binding.prop2specs["prop-1"]
+    verify_expected_propspec(
+        propspec,
+        # Amended in base_amend.yaml.
+        expect_desc="Overwritten description.",
+        expect_const=0xF0,
+    )
+    propspec = binding.prop2specs["prop-2"]
+    verify_expected_propspec(
+        propspec,
+        expect_type="string",
+        # Amended in base_amend.yaml.
+        expect_desc="New description.",
+        expect_enum=["EXT_FOO", "EXT_BAR"],
+        expect_default="EXT_FOO",
+    )
+    propspec = binding.prop2specs["prop-enum"]
+    verify_expected_propspec(
+        propspec,
+        expect_type="string",
+        expect_enum=["FOO", "BAR"],
+        # Amended in base_amend.yaml.
+        expect_req=True,
+    )
+    # Inherited from base.yaml without modification.
+    propspec = binding.prop2specs["prop-const"]
+    verify_expected_propspec(propspec, expect_const=8)
+    propspec = binding.prop2specs["prop-req"]
+    verify_expected_propspec(propspec, expect_req=True)
+    propspec = binding.prop2specs["prop-default"]
+    verify_expected_propspec(propspec, expect_default=1)
+
+    # New property in base_amend.yaml.
+    propspec = binding.prop2specs["prop-new"]
+    verify_expected_propspec(propspec)
+
+    # Child-Binding level.
+    #
+    assert binding.child_binding
+    child_binding = binding.child_binding
+    assert {
+        "child-prop-1",
+        "child-prop-2",
+        "child-prop-enum",
+        "child-prop-req",
+        "child-prop-const",
+        "child-prop-default",
+        "child-prop-new",
+    } == set(child_binding.prop2specs.keys())
+    propspec = child_binding.prop2specs["child-prop-1"]
+    verify_expected_propspec(
+        propspec,
+        # Amended in base_amend.yaml.
+        expect_desc="Overwritten description (child).",
+        expect_const=0xF1,
+    )
+    propspec = child_binding.prop2specs["child-prop-2"]
+    verify_expected_propspec(
+        propspec,
+        expect_type="string",
+        # Amended in base_amend.yaml.
+        expect_desc="New description (child).",
+        expect_enum=["CHILD_EXT_FOO", "CHILD_EXT_BAR"],
+        expect_default="CHILD_EXT_FOO",
+    )
+    propspec = child_binding.prop2specs["child-prop-enum"]
+    verify_expected_propspec(
+        propspec,
+        expect_type="string",
+        expect_enum=["CHILD_FOO", "CHILD_BAR"],
+        # Amended in base_amend.yaml.
+        expect_req=True,
+    )
+    # Inherited from base.yaml without modification.
+    propspec = child_binding.prop2specs["child-prop-const"]
+    verify_expected_propspec(propspec, expect_const=16)
+    propspec = child_binding.prop2specs["child-prop-req"]
+    verify_expected_propspec(propspec, expect_req=True)
+    propspec = child_binding.prop2specs["child-prop-default"]
+    verify_expected_propspec(propspec, expect_default=2)
+
+    # New property in base_amend.yaml.
+    propspec = child_binding.prop2specs["child-prop-new"]
+    verify_expected_propspec(propspec)
+
+    # GrandChild-Binding level.
+    #
+    assert child_binding.child_binding
+    grandchild_binding = child_binding.child_binding
+    assert {
+        "grandchild-prop-1",
+        "grandchild-prop-2",
+        "grandchild-prop-enum",
+        "grandchild-prop-req",
+        "grandchild-prop-const",
+        "grandchild-prop-default",
+        "grandchild-prop-new",
+    } == set(grandchild_binding.prop2specs.keys())
+    propspec = grandchild_binding.prop2specs["grandchild-prop-1"]
+    verify_expected_propspec(
+        propspec,
+        # Amended in base_amend.yaml.
+        expect_desc="Overwritten description (grandchild).",
+        expect_const=0xF2,
+    )
+    propspec = grandchild_binding.prop2specs["grandchild-prop-2"]
+    verify_expected_propspec(
+        propspec,
+        expect_type="string",
+        # Amended in base_amend.yaml.
+        expect_desc="New description (grandchild).",
+        expect_enum=["GRANDCHILD_EXT_FOO", "GRANDCHILD_EXT_BAR"],
+        expect_default="GRANDCHILD_EXT_FOO",
+    )
+    propspec = grandchild_binding.prop2specs["grandchild-prop-enum"]
+    verify_expected_propspec(
+        propspec,
+        expect_type="string",
+        expect_enum=["GRANDCHILD_FOO", "GRANDCHILD_BAR"],
+        # Amended in base_amend.yaml.
+        expect_req=True,
+    )
+    # Inherited from base.yaml without modification.
+    propspec = grandchild_binding.prop2specs["grandchild-prop-const"]
+    verify_expected_propspec(propspec, expect_const=32)
+    propspec = grandchild_binding.prop2specs["grandchild-prop-req"]
+    verify_expected_propspec(propspec, expect_req=True)
+    propspec = grandchild_binding.prop2specs["grandchild-prop-default"]
+    verify_expected_propspec(propspec, expect_default=3)
+
+    # New property in base_amend.yaml.
+    propspec = grandchild_binding.prop2specs["grandchild-prop-new"]
+    verify_expected_propspec(propspec)
+
+
+def test_expect_propspecs_multi_child_binding() -> None:
+    """Test including base bindings at multiple levels.
+
+    Base specifications are included at the binding, child-binding
+    and child-binding levels:
+
+        include: base.yaml
+        child-binding:
+          include: base.yaml
+          child-binding:
+            include: base.yaml
+
+    This test checks that we finally get the expected property specifications
+    at the child-binding level.
+    """
+    binding = child_binding_of("test-bindings-init/base_multi.yaml")
+
+    assert {
+        # From top-level "include:" element.
+        "child-prop-1",
+        "child-prop-2",
+        "child-prop-enum",
+        # From "child-binding: include:" element.
+        "prop-1",
+        "prop-2",
+        "prop-enum",
+    } == set(binding.prop2specs.keys())
+
+    # Inherited from base.yaml without modification.
+    propspec = binding.prop2specs["child-prop-2"]
+    verify_expected_propspec(propspec, expect_type="string")
+    propspec = binding.prop2specs["child-prop-enum"]
+    verify_expected_propspec(propspec, expect_type="string", expect_enum=["CHILD_FOO", "CHILD_BAR"])
+
+    propspec = binding.prop2specs["child-prop-1"]
+    verify_expected_propspec(
+        propspec,
+        expect_desc="Base child-prop 1.",
+        # Amended in base_multi.yaml.
+        expect_const=0xF1,
+    )
+    propspec = binding.prop2specs["prop-1"]
+    verify_expected_propspec(
+        propspec,
+        expect_desc="Base property 1.",
+        # Amended in base_multi.yaml.
+        expect_const=0xF1,
+    )
+    propspec = binding.prop2specs["prop-2"]
+    verify_expected_propspec(
+        propspec,
+        expect_type="string",
+        # Amended in base_multi.yaml.
+        expect_desc="New description (child).",
+    )
+    propspec = binding.prop2specs["prop-enum"]
+    verify_expected_propspec(
+        propspec,
+        expect_type="string",
+        expect_enum=["FOO", "BAR"],
+        # Amended in base_multi.yaml.
+        expect_default="FOO",
+        expect_req=True,
+    )
+
+
+def test_expect_propspecs_multi_grandchild_binding() -> None:
+    """Test including base bindings at multiple levels.
+
+    This test checks that we finally get the expected property specifications
+    at the grandchild-binding level.
+
+    See also: test_expect_propspecs_multi_child_binding()
+    """
+    binding = grandchild_binding_of("test-bindings-init/base_multi.yaml")
+
+    assert {
+        # From top-level "include:" element.
+        "grandchild-prop-1",
+        "grandchild-prop-2",
+        "grandchild-prop-enum",
+        # From "child-binding: include:" element.
+        "child-prop-1",
+        "child-prop-2",
+        "child-prop-enum",
+        # From "child-binding: child-binding: include:" element.
+        "prop-1",
+        "prop-2",
+        "prop-enum",
+    } == set(binding.prop2specs.keys())
+
+    # Inherited from base.yaml without modification.
+    propspec = binding.prop2specs["grandchild-prop-2"]
+    verify_expected_propspec(propspec, expect_type="string")
+    propspec = binding.prop2specs["grandchild-prop-enum"]
+    verify_expected_propspec(
+        propspec,
+        expect_type="string",
+        expect_enum=["GRANDCHILD_FOO", "GRANDCHILD_BAR"],
+    )
+    propspec = binding.prop2specs["child-prop-2"]
+    verify_expected_propspec(propspec, expect_type="string")
+    propspec = binding.prop2specs["child-prop-enum"]
+    verify_expected_propspec(propspec, expect_type="string", expect_enum=["CHILD_FOO", "CHILD_BAR"])
+
+    propspec = binding.prop2specs["grandchild-prop-1"]
+    verify_expected_propspec(
+        propspec,
+        expect_desc="Base grandchild-prop 1.",
+        # Amended in base_multi.yaml.
+        expect_const=0xF2,
+    )
+    propspec = binding.prop2specs["child-prop-1"]
+    verify_expected_propspec(
+        propspec,
+        expect_desc="Base child-prop 1.",
+        # Amended in base_multi.yaml.
+        expect_const=0xF2,
+    )
+    propspec = binding.prop2specs["prop-1"]
+    verify_expected_propspec(
+        propspec,
+        expect_desc="Base property 1.",
+        # Amended in base_amend.yaml.
+        expect_const=0xF2,
+    )
+    propspec = binding.prop2specs["prop-2"]
+    verify_expected_propspec(
+        propspec,
+        expect_type="string",
+        # Amended in base_amend.yaml.
+        expect_desc="New description (grandchild).",
+    )
+    propspec = binding.prop2specs["prop-enum"]
+    verify_expected_propspec(
+        propspec,
+        expect_type="string",
+        expect_enum=["FOO", "BAR"],
+        # Amended in base_amend.yaml.
+        expect_req=True,
+        expect_default="FOO",
+    )
+
+
+def test_expect_propspecs_multi_grand_grandchild_binding() -> None:
+    """Test including base bindings at multiple levels.
+
+    This test checks that we finally get the expected property specifications
+    at the grand-grandchild-binding level.
+
+    See also: test_expect_propspecs_multi_child_binding()
+    """
+    binding = grandchild_binding_of("test-bindings-init/base_multi.yaml").child_binding
+    assert binding
+
+    assert {
+        # From "child-binding: include:" element.
+        "child-prop-1",
+        "child-prop-2",
+        "child-prop-enum",
+        # From "child-binding: child-binding: include:" element.
+        "grandchild-prop-1",
+        "grandchild-prop-2",
+        "grandchild-prop-enum",
+    } == set(binding.prop2specs.keys())
+
+    # Inherited from base.yaml without modification.
+    propspec = binding.prop2specs["child-prop-1"]
+    verify_expected_propspec(propspec, expect_desc="Base child-prop 1.")
+    propspec = binding.prop2specs["child-prop-2"]
+    verify_expected_propspec(propspec, expect_type="string")
+    propspec = binding.prop2specs["child-prop-enum"]
+    verify_expected_propspec(propspec, expect_type="string", expect_enum=["CHILD_FOO", "CHILD_BAR"])
+    propspec = binding.prop2specs["grandchild-prop-1"]
+    verify_expected_propspec(propspec, expect_desc="Base grandchild-prop 1.")
+    propspec = binding.prop2specs["grandchild-prop-2"]
+    verify_expected_propspec(propspec, expect_type="string")
+    propspec = binding.prop2specs["grandchild-prop-enum"]
+    verify_expected_propspec(
+        propspec,
+        expect_type="string",
+        expect_enum=["GRANDCHILD_FOO", "GRANDCHILD_BAR"],
+    )
+
+
+def test_expect_propspecs_diamond_binding() -> None:
+    """Test property specifications produced by diamond inheritance.
+
+    This test checks that we finally get the expected property specifications
+    at the binding level.
+    """
+    binding = load_binding("test-bindings-init/diamond.yaml")
+
+    assert {
+        # From base.yaml, amended in base_amend.yaml (left),
+        # last modified in thing.yaml (right).
+        "prop-1",
+        # From base.yaml, amended in base_amend.yaml (left),
+        # and thing.yaml (right), last modified in diamond.yaml(top).
+        "prop-enum",
+        # From base.yaml, inherited in base_amend.yaml (left).
+        "prop-default",
+        # From thing.yaml (right).
+        "prop-thing",
+        # From diamond.yaml (top).
+        "prop-diamond",
+    } == set(binding.prop2specs.keys())
+
+    # Inherited from base.yaml without modification.
+    propspec = binding.prop2specs["prop-default"]
+    verify_expected_propspec(propspec, expect_default=1)
+    # Inherited from thing.yaml without modification.
+    propspec = binding.prop2specs["prop-thing"]
+    verify_expected_propspec(propspec, expect_desc="Thing property.")
+
+    # New property in diamond.yaml.
+    propspec = binding.prop2specs["prop-diamond"]
+    verify_expected_propspec(propspec)
+
+    propspec = binding.prop2specs["prop-1"]
+    verify_expected_propspec(
+        propspec,
+        # From base_amend.yaml.
+        expect_const=0xF0,
+        # Included first wins.
+        expect_desc="Overwritten description.",
+        # From thing.yaml.
+        expect_default=1,
+    )
+    propspec = binding.prop2specs["prop-enum"]
+    verify_expected_propspec(
+        propspec,
+        expect_type="string",
+        expect_enum=["FOO", "BAR"],
+        # From base_amend.yaml.
+        expect_req=True,
+        # From diamond.yaml.
+        expect_desc="Overwritten in diamond.yaml.",
+        expect_default="FOO",
+    )
+
+
+def test_expect_propspecs_diamond_child_binding() -> None:
+    """Test property specifications produced by diamond inheritance.
+
+    This test checks that we finally get the expected property specifications
+    at the child-binding level.
+    """
+    binding = child_binding_of("test-bindings-init/diamond.yaml")
+
+    assert {
+        # From base.yaml, amended in base_amend.yaml (left),
+        # last modified in thing.yaml (right).
+        "child-prop-1",
+        # From base.yaml, amended in base_amend.yaml (left),
+        # and thing.yaml (right), last modified in diamond.yaml(top).
+        "child-prop-enum",
+        # From base.yaml, inherited in base_amend.yaml (left).
+        "child-prop-default",
+        # From thing.yaml (right).
+        "child-prop-thing",
+        # From diamond.yaml (top).
+        "child-prop-diamond",
+    } == set(binding.prop2specs.keys())
+
+    propspec = binding.prop2specs["child-prop-1"]
+    verify_expected_propspec(
+        propspec,
+        # From base_amend.yaml.
+        expect_const=0xF1,
+        # Included first wins.
+        expect_desc="Overwritten description (child).",
+        # From thing.yaml.
+        expect_default=2,
+    )
+
+    propspec = binding.prop2specs["child-prop-enum"]
+    verify_expected_propspec(
+        propspec,
+        expect_type="string",
+        expect_enum=["CHILD_FOO", "CHILD_BAR"],
+        # From base_amend.yaml.
+        # ORed with thing.yaml.
+        expect_req=True,
+        # From diamond.yaml.
+        expect_default="CHILD_FOO",
+        expect_desc="Overwritten in diamond.yaml (child).",
+    )
+
+    # Inherited from base.yaml without modification.
+    propspec = binding.prop2specs["child-prop-default"]
+    verify_expected_propspec(propspec, expect_default=2)
+    # Inherited from thing.yaml without modification.
+    propspec = binding.prop2specs["child-prop-thing"]
+    verify_expected_propspec(propspec, expect_desc="Thing child-binding property.")
+
+    # New property in diamond.yaml.
+    propspec = binding.prop2specs["child-prop-diamond"]
+    verify_expected_propspec(propspec)
+
+
+def test_expect_propspecs_diamond_grandchild_binding() -> None:
+    """Test property specifications produced by diamond inheritance.
+
+    This test checks that we finally get the expected property specifications
+    at the grandchild-binding level.
+    """
+    binding = grandchild_binding_of("test-bindings-init/diamond.yaml")
+
+    assert {
+        # From base.yaml, amended in base_amend.yaml (left),
+        # last modified in thing.yaml (right).
+        "grandchild-prop-1",
+        # From base.yaml, amended in base_amend.yaml (left),
+        # last modified in diamond.yaml (top).
+        "grandchild-prop-enum",
+        # From base.yaml, inherited in base_amend.yaml (left).
+        "grandchild-prop-default",
+        # From thing.yaml (right).
+        "grandchild-prop-thing",
+        # From diamond.yaml (top).
+        "grandchild-prop-diamond",
+    } == set(binding.prop2specs.keys())
+
+    propspec = binding.prop2specs["grandchild-prop-1"]
+    verify_expected_propspec(
+        propspec,
+        # From base_amend.yaml.
+        expect_const=0xF2,
+        # Included first wins.
+        expect_desc="Overwritten description (grandchild).",
+        # From thing.yaml.
+        expect_default=3,
+    )
+
+    propspec = binding.prop2specs["grandchild-prop-enum"]
+    verify_expected_propspec(
+        propspec,
+        expect_type="string",
+        expect_enum=["GRANDCHILD_FOO", "GRANDCHILD_BAR"],
+        # From base_amend.yaml.
+        # ORed with thing.yaml.
+        expect_req=True,
+        # From diamond.yaml.
+        expect_default="GRANDCHILD_FOO",
+        expect_desc="Overwritten in diamond.yaml (grandchild).",
+    )
+
+    # Inherited from base.yaml without modification.
+    propspec = binding.prop2specs["grandchild-prop-default"]
+    verify_expected_propspec(propspec, expect_default=3)
+    # Inherited from thing.yaml without modification.
+    propspec = binding.prop2specs["grandchild-prop-thing"]
+    verify_expected_propspec(propspec, expect_desc="Thing grandchild-binding property.")
+
+    # New property in diamond.yaml.
+    propspec = binding.prop2specs["grandchild-prop-diamond"]
+    verify_expected_propspec(propspec)
+
+
+def test_binding_description_overwrite() -> None:
+    """Test whether we can overwrite a binding's description.
+
+    Included files can't overwrite the description set by the including binding
+    (despite that "description:" appears before "include:").
+
+    This seems consistent: the top-level binding file "wins".
+    """
+    binding = load_binding("test-bindings-init/compat_desc.yaml")
+    assert binding.description == "Binding description."
+
+    binding = load_binding("test-bindings-init/compat_desc_multi.yaml")
+    assert binding.description == "Binding description (multi)."
+
+
+def test_binding_compat_overwrite() -> None:
+    """Test whether we can overwrite a binding's compatible string.
+
+    Included files can't overwrite the compatible string set by the
+    including binding (despite that "compatible:" appears before "include:").
+
+    This seems consistent: the top-level binding file "wins".
+    """
+    binding = load_binding("test-bindings-init/compat_desc.yaml")
+    assert binding.compatible == "vnd,compat-desc"
+
+    binding = load_binding("test-bindings-init/compat_desc_multi.yaml")
+    assert binding.compatible == "vnd,compat-desc-multi"
+
+
+def test_child_binding_description_overwrite() -> None:
+    """Test whether we can overwrite a child-binding's description.
+
+    An including binding can overwrite an inherited child-binding's description.
+
+    When we include multiple files overwriting the description
+    at the child-binding level, the first "wins".
+    """
+    child_binding = child_binding_of("test-bindings-init/compat_desc.yaml")
+    # Overwrite inherited description.
+    assert child_binding.description == "Child-binding description."
+
+    child_binding = child_binding_of("test-bindings-init/compat_desc_multi.yaml")
+    # When inherited multiple times, the first "description:" wins.
+    assert child_binding.description == "Child-binding description (base)."
+
+
+def test_child_binding_compat_overwrite() -> None:
+    """Test whether we can overwrite a child-binding's compatible string.
+
+    An including binding can overwrite an inherited child-binding's
+    compatible string.
+
+    When we include multiple files overwriting the compatible string
+    at the child-binding level, the first "wins".
+    """
+    child_binding = child_binding_of("test-bindings-init/compat_desc.yaml")
+    # Overwrite inherited description.
+    assert child_binding.compatible == "vnd,child-compat-desc"
+
+    child_binding = child_binding_of("test-bindings-init/compat_desc_multi.yaml")
+    # When inherited multiple times, the first "compatible:" wins.
+    assert child_binding.compatible == "vnd,child-compat-desc-base"
+
+
+def test_grandchild_binding_description_overwrite() -> None:
+    """Test whether we can overwrite a grandchild-binding's description.
+
+    See also: test_child_binding_description_overwrite()
+    """
+    grandchild_binding = grandchild_binding_of("test-bindings-init/compat_desc.yaml")
+    assert grandchild_binding.description == "Grandchild-binding description."
+
+    grandchild_binding = grandchild_binding_of("test-bindings-init/compat_desc_multi.yaml")
+    assert grandchild_binding.description == "Grandchild-binding description (base)."
+
+
+def test_grandchild_binding_compat_overwrite() -> None:
+    """Test whether we can overwrite a grandchild-binding's compatible string.
+
+    See also: test_child_binding_compat_overwrite()
+    """
+    grandchild_binding = grandchild_binding_of("test-bindings-init/compat_desc.yaml")
+    # Overwrite inherited description.
+    assert grandchild_binding.compatible == "vnd,grandchild-compat-desc"
+
+    grandchild_binding = grandchild_binding_of("test-bindings-init/compat_desc_multi.yaml")
+    # When inherited multiple times, the first "compatible:" wins.
+    assert grandchild_binding.compatible == "vnd,grandchild-compat-desc-base"
+
+
+def test_filter_inherited_propspecs_basics() -> None:
+    """Test the basics of filtering properties inherited via an intermediary
+    binding file.
+
+    Use-case "B filters I includes X":
+    - X is a base binding file, specifying common properties
+    - I is an intermediary binding file, which includes X without modification
+      nor filter
+    - B includes I, filtering the properties it chooses to inherit
+      with an allowlist or a blocklist
+
+    Checks, up to the grandchild-binding level, that the properties inherited
+    from X via I are actually filtered as B intends to.
+    """
+    # Binding level.
+    binding = load_binding("test-bindings-init/simple_allowlist.yaml")
+    # Allowed properties.
+    assert {"prop-1", "prop-2"} == set(binding.prop2specs.keys())
+    binding = load_binding("test-bindings-init/simple_blocklist.yaml")
+    # Non blocked properties.
+    assert {"prop-2", "prop-3"} == set(binding.prop2specs.keys())
+
+    # Child-binding level.
+    child_binding = child_binding_of("test-bindings-init/simple_allowlist.yaml")
+    # Allowed properties.
+    assert {"child-prop-1", "child-prop-2"} == set(child_binding.prop2specs.keys())
+    child_binding = child_binding_of("test-bindings-init/simple_blocklist.yaml")
+    # Non blocked properties.
+    assert {"child-prop-2", "child-prop-3"} == set(child_binding.prop2specs.keys())
+
+    # GrandChild-binding level.
+    grandchild_binding = grandchild_binding_of("test-bindings-init/simple_allowlist.yaml")
+    # Allowed properties.
+    assert {"grandchild-prop-1", "grandchild-prop-2"} == set(grandchild_binding.prop2specs.keys())
+    grandchild_binding = grandchild_binding_of("test-bindings-init/simple_blocklist.yaml")
+    # Non blocked properties.
+    assert {"grandchild-prop-2", "grandchild-prop-3"} == set(grandchild_binding.prop2specs.keys())
+
+
+def test_filter_inherited_propspecs_among_allowed() -> None:
+    """Test filtering properties which have been allowed by an intermediary
+    binding file.
+
+    Complementary to test_filter_inherited_propspecs_basics().
+
+    Use-case "B filters I filters X":
+    - X is a base binding file, specifying common properties
+    - I is an intermediary binding file, filtering the properties specified
+      in X with an allowlist
+    - B includes I, filtering the properties it chooses to inherit
+      also with an allowlist
+
+    Checks, up to the grandchild-binding level, that B inherits the properties
+    specified in X which are first allowed in I, then also allowed in B.
+
+    For that, we check that if B allows only properties that are not allowed in I,
+    we then end up with no property at all.
+    """
+    binding = load_binding("test-bindings-init/filter_among_allowed.yaml")
+    assert not set(binding.prop2specs.keys())
+    assert binding.child_binding
+    child_binding = binding.child_binding
+    assert not set(child_binding.prop2specs.keys())
+    assert child_binding.child_binding
+    grandchild_binding = child_binding.child_binding
+    assert not set(grandchild_binding.prop2specs.keys())
+
+
+def test_filter_inherited_propspecs_among_notblocked() -> None:
+    """Test filtering properties which have not been blocked by an intermediary
+    binding file.
+
+    Complementary to test_filter_inherited_propspecs_basics().
+
+    Use-case "B filters I filters X":
+    - X is a base binding file, specifying common properties
+    - I is an intermediary binding file, filtering the properties specified
+      in X with a blocklist
+    - B includes I, filtering the properties it chooses to inherit
+      also with a blocklist
+
+    Checks, up to the grandchild-binding level, that B inherits the properties
+    specified in X which are not blocked in I, then neither blocked in B.
+
+    For that, we check that if B blocks all properties that are not blocked in I,
+    we then end up with no property at all.
+    """
+    binding = load_binding("test-bindings-init/filter_among_notblocked.yaml")
+    assert not set(binding.prop2specs.keys())
+    assert binding.child_binding
+    child_binding = binding.child_binding
+    assert not set(child_binding.prop2specs.keys())
+    assert child_binding.child_binding
+    grandchild_binding = child_binding.child_binding
+    assert not set(grandchild_binding.prop2specs.keys())
+
+
+def test_filter_inherited_propspecs_allows_notblocked() -> None:
+    """Test allowing properties which have not been blocked by an intermediary
+    binding file.
+
+    Complementary to test_filter_inherited_propspecs_basics().
+
+    Use-case "B filters I filters X":
+    - X is a base binding file, specifying common properties
+    - I is an intermediary binding file, filtering the properties specified
+      in X with a blocklist
+    - B includes I, filtering the properties it chooses to inherit
+      also with an allowlist
+
+    Checks, up to the grandchild-binding level, that B inherits the properties
+    specified in X which are not blocked in I, then allowed in B.
+
+    Permits to verify we can apply both "property-allowlist"
+    and "property-blocklist" filters to the same file,
+    as long as they're not applied simultaneously
+    (i.e. within the same YAML "include:" map).
+    """
+    binding = load_binding("test-bindings-init/filter_allows_notblocked.yaml")
+    assert {"prop-2"} == set(binding.prop2specs.keys())
+    assert binding.child_binding
+    child_binding = binding.child_binding
+    assert {"child-prop-2"} == set(child_binding.prop2specs.keys())
+    assert child_binding.child_binding
+    grandchild_binding = child_binding.child_binding
+    assert {"grandchild-prop-2"} == set(grandchild_binding.prop2specs.keys())
+
+
+def test_invalid_binding_type_override() -> None:
+    """An including binding should not try to override the "type:"
+    of an inherited property.
+
+    Tested up to the grandchild-binding level.
+    """
+    with pytest.raises(edtlib.EDTError) as e:
+        load_binding("test-bindings-init/invalid_proptype.yaml")
+    assert "prop-1" in str(e)
+    assert "'int' replaced with 'string'" in str(e)
+
+    with pytest.raises(edtlib.EDTError) as e:
+        load_binding("test-bindings-init/invalid_child_proptype.yaml")
+    assert "child-prop-1" in str(e)
+    assert "'int' replaced with 'string'" in str(e)
+
+    with pytest.raises(edtlib.EDTError) as e:
+        load_binding("test-bindings-init/invalid_grandchild_proptype.yaml")
+    assert "grandchild-prop-1" in str(e)
+    assert "'int' replaced with 'string'" in str(e)
+
+
+def test_invalid_binding_const_override() -> None:
+    """An including binding should not try to override the "const:" value
+    in a property specification inherited from an included file.
+
+    Tested up to the grandchild-binding level.
+    """
+    with pytest.raises(edtlib.EDTError) as e:
+        load_binding("test-bindings-init/invalid_propconst.yaml")
+    assert "prop-const" in str(e)
+    assert "'8' replaced with '999'" in str(e)
+
+    with pytest.raises(edtlib.EDTError) as e:
+        load_binding("test-bindings-init/invalid_child_propconst.yaml")
+    assert "child-prop-const" in str(e)
+    assert "'16' replaced with '999'" in str(e)
+
+    with pytest.raises(edtlib.EDTError) as e:
+        load_binding("test-bindings-init/invalid_grandchild_propconst.yaml")
+    assert "grandchild-prop-const" in str(e)
+    assert "'32' replaced with '999'" in str(e)
+
+
+def test_invalid_binding_required_override() -> None:
+    """An including binding should not try to override "required: true"
+    in a property specification inherited from an included file.
+
+    Tested up to the grandchild-binding level.
+    """
+    with pytest.raises(edtlib.EDTError) as e:
+        load_binding("test-bindings-init/invalid_propreq.yaml")
+    assert "prop-req" in str(e)
+    assert "'True' replaced with 'False'" in str(e)
+
+    with pytest.raises(edtlib.EDTError) as e:
+        load_binding("test-bindings-init/invalid_child_propreq.yaml")
+    assert "child-prop-req" in str(e)
+    assert "'True' replaced with 'False'" in str(e)
+
+    with pytest.raises(edtlib.EDTError) as e:
+        load_binding("test-bindings-init/invalid_grandchild_propreq.yaml")
+    assert "grandchild-prop-req" in str(e)
+    assert "'True' replaced with 'False'" in str(e)
+
+
+def test_invalid_binding_default_override() -> None:
+    """An including binding should not try to override the "default:" value
+    in a property specification inherited from an included file.
+
+    Tested up to the grandchild-binding level.
+    """
+    with pytest.raises(edtlib.EDTError) as e:
+        load_binding("test-bindings-init/invalid_propdefault.yaml")
+    assert "prop-default" in str(e)
+    assert "'1' replaced with '999'" in str(e)
+
+    with pytest.raises(edtlib.EDTError) as e:
+        load_binding("test-bindings-init/invalid_child_propdefault.yaml")
+    assert "child-prop-default" in str(e)
+    assert "'2' replaced with '999'" in str(e)
+
+    with pytest.raises(edtlib.EDTError) as e:
+        load_binding("test-bindings-init/invalid_grandchild_propdefault.yaml")
+    assert "grandchild-prop-default" in str(e)
+    assert "'3' replaced with '999'" in str(e)
+
+
+def test_invalid_binding_enum_override() -> None:
+    """An including binding should not try to override the "enum:" values
+    in a property specification inherited from an included file.
+
+    Tested up to the grandchild-binding level.
+    """
+    with pytest.raises(edtlib.EDTError) as e:
+        load_binding("test-bindings-init/invalid_propenum.yaml")
+    assert "prop-enum" in str(e)
+    assert "'['FOO', 'BAR']' replaced with '['OTHER_FOO', 'OTHER_BAR']'" in str(e)
+
+    with pytest.raises(edtlib.EDTError) as e:
+        load_binding("test-bindings-init/invalid_child_propenum.yaml")
+    assert "child-prop-enum" in str(e)
+    assert "'['CHILD_FOO', 'CHILD_BAR']' replaced with '['OTHER_FOO', 'OTHER_BAR']'" in str(e)
+
+    with pytest.raises(edtlib.EDTError) as e:
+        load_binding("test-bindings-init/invalid_grandchild_propenum.yaml")
+    assert "grandchild-prop-enum" in str(e)
+    assert (
+        "'['GRANDCHILD_FOO', 'GRANDCHILD_BAR']' replaced with '['OTHER_FOO', 'OTHER_BAR']'"
+        in str(e)
+    )
+
+
+def test_bindings_propspecs_consistency() -> None:
+    """Verify property specifications consistency.
+
+    Consistency is recursively checked for all defined properties,
+    from top-level binding files down to their child bindings.
+
+    Consistency is checked with:
+        Binding.raw["properties"][prop] == Binding.prop2specs[prop]._raw
+
+    See verify_binding_propspecs_consistency().
+    """
+    binding = load_binding("test-bindings-init/base_inherit.yaml")
+    verify_binding_propspecs_consistency(binding)
+
+    binding = load_binding("test-bindings-init/base_amend.yaml")
+    verify_binding_propspecs_consistency(binding)
+
+    binding = load_binding("test-bindings-init/base_multi.yaml")
+    verify_binding_propspecs_consistency(binding)
+
+    binding = load_binding("test-bindings-init/thing.yaml")
+    verify_binding_propspecs_consistency(binding)
+
+    binding = load_binding("test-bindings-init/diamond.yaml")
+    verify_binding_propspecs_consistency(binding)
+
+
+# Borrowed from test_edtlib.py.
+@contextlib.contextmanager
+def _from_here() -> Generator[None, None, None]:
+    cwd = os.getcwd()
+    try:
+        os.chdir(os.path.dirname(__file__))
+        yield
+    finally:
+        os.chdir(cwd)
+
+
+def _basename(path: str | None) -> str:
+    return os.path.basename(path or "?")
diff --git a/scripts/footprint/plan.txt b/scripts/footprint/plan.txt
index f53a1371e7c..a28cb93f142 100644
--- a/scripts/footprint/plan.txt
+++ b/scripts/footprint/plan.txt
@@ -5,7 +5,7 @@ footprints,userspace,disco_l475_iot1,tests/benchmarks/footprints,-DCONF_FILE=prj
 footprints,default,nrf5340dk/nrf5340/cpuapp,tests/benchmarks/footprints,,benchmark.kernel.footprints.default
 footprints,default,nrf51dk/nrf51822,tests/benchmarks/footprints,,benchmark.kernel.footprints.default
 footprints,default,altera_max10,tests/benchmarks/footprints,,benchmark.kernel.footprints.default
-footprints,default,hifive1_revb,tests/benchmarks/footprints,,benchmark.kernel.footprints.default
+footprints,default,hifive1@B,tests/benchmarks/footprints,,benchmark.kernel.footprints.default
 footprints,default,intel_ehl_crb,tests/benchmarks/footprints,,benchmark.kernel.footprints.default
 footprints,userspace,intel_ehl_crb,tests/benchmarks/footprints,-DCONF_FILE=prj_userspace.conf,benchmark.kernel.footprints.userspace
 footprints,power-management,frdm_k64f,tests/benchmarks/footprints,-DCONF_FILE=prj_pm.conf,benchmark.kernel.footprints.pm
diff --git a/scripts/footprint/size_report b/scripts/footprint/size_report
index 3712d0f7d53..c4d73b8e2d0 100755
--- a/scripts/footprint/size_report
+++ b/scripts/footprint/size_report
@@ -207,6 +207,11 @@ def get_section_ranges(elf):
     ram_size = 0
     unassigned_size = 0
 
+    xip = any(section.get_symbol_by_name('CONFIG_XIP')
+              for section in elf.iter_sections('SHT_SYMTAB'))
+    if args.verbose:
+        print(f'INFO: XIP={xip}')
+
     for section in elf.iter_sections():
         size = section['sh_size']
         sec_start = section['sh_addr']
@@ -232,14 +237,16 @@ def get_section_ranges(elf):
                 print_section_info(section, "ROM txt section")
 
             elif (flags & SHF_WRITE_ALLOC) == SHF_WRITE_ALLOC:
-                # Data occupies both ROM and RAM
-                # since at boot, content is copied from ROM to RAM
-                rom_addr_ranges.append(bound)
-                rom_size += size
+                # Read/write data
+                if xip:
+                    # For XIP, the data section occupies both ROM and RAM
+                    # since at boot, content is copied from ROM to RAM
+                    rom_addr_ranges.append(bound)
+                    rom_size += size
                 ram_addr_ranges.append(bound)
                 ram_size += size
                 is_assigned = True
-                print_section_info(section, "ROM,RAM section")
+                print_section_info(section, "DATA r/w section")
 
             elif (flags & SHF_ALLOC) == SHF_ALLOC:
                 # Read only data
diff --git a/scripts/kconfig/hardened.csv b/scripts/kconfig/hardened.csv
index d91029a046d..4a126b96fc1 100644
--- a/scripts/kconfig/hardened.csv
+++ b/scripts/kconfig/hardened.csv
@@ -17,7 +17,6 @@ CORTEX_M_DEBUG_MONITOR_HOOK,n
 DMA_INTEL_ADSP_GPDMA_DEBUG,n
 ESPI_PERIPHERAL_DEBUG_PORT_80,n
 ETH_E1000_VERBOSE_DEBUG,n
-ETH_MCUX_PHY_EXTRA_DEBUG,n
 EXECUTE_XOR_WRITE,y
 FAULT_DUMP,0
 HW_STACK_PROTECTION,y
diff --git a/scripts/native_simulator/Makefile b/scripts/native_simulator/Makefile
index 392df5f5412..905fe88be98 100644
--- a/scripts/native_simulator/Makefile
+++ b/scripts/native_simulator/Makefile
@@ -38,6 +38,8 @@ NSI_COVERAGE?=--coverage
 NSI_LOCALIZE_OPTIONS?=
 NSI_BUILD_OPTIONS?=${NSI_ARCH} ${NSI_COVERAGE}
 NSI_LINK_OPTIONS?=${NSI_ARCH} ${NSI_COVERAGE}
+NSI_BUILD_C_OPTIONS?=
+NSI_BUILD_CXX_OPTIONS?=
 #  Extra source files to be built in the runner context
 NSI_EXTRA_SRCS?=
 #  Extra include directories to be used while building in the runner context
@@ -48,6 +50,8 @@ NSI_EXTRA_LIBS?=
 SHELL?=bash
 #  Compiler
 NSI_CC?=gcc
+NSI_CXX?=g++
+NSI_LINKER?=${NSI_CC}
 #  Archive program (it is unlikely you'll need to change this)
 NSI_AR?=ar
 #  Objcopy program (it is unlikely you'll need to change this)
@@ -64,8 +68,10 @@ NSI_CPPFLAGS?=-D_POSIX_C_SOURCE=200809L -D_XOPEN_SOURCE=600 -D_XOPEN_SOURCE_EXTE
 
 NO_PIE_CO:=-fno-pie -fno-pic
 DEPENDFLAGS:=-MMD -MP
-CFLAGS:=${NSI_DEBUG} ${NSI_WARNINGS} ${NSI_OPT} ${NO_PIE_CO} -DNSI_N_CPUS=${NSI_N_CPUS} \
-  -ffunction-sections -fdata-sections ${DEPENDFLAGS} -std=c11 ${NSI_BUILD_OPTIONS}
+COMMON_BUILD_FLAGS:=-DNSI_RUNNER_BUILD ${NSI_DEBUG} ${NSI_WARNINGS} ${NSI_OPT} ${NO_PIE_CO} \
+  -DNSI_N_CPUS=${NSI_N_CPUS} -ffunction-sections -fdata-sections ${DEPENDFLAGS} ${NSI_BUILD_OPTIONS}
+CFLAGS:=-std=c11 ${COMMON_BUILD_FLAGS} ${NSI_BUILD_C_OPTIONS}
+CXXFLAGS:=${COMMON_BUILD_FLAGS} ${NSI_BUILD_CXX_OPTIONS}
 FINALLINK_FLAGS:=${NO_PIE_CO} -no-pie  ${NSI_WARNINGS} \
   -Wl,--gc-sections -ldl -pthread \
   ${NSI_LINK_OPTIONS} -lm
@@ -89,7 +95,7 @@ ifdef NSI_NATIVE
   INCLUDES+=-I${NSI_PATH}native/src/include/
 endif
 
-EXTRA_OBJS:=$(abspath $(addprefix $(NSI_BUILD_PATH)/,$(sort ${NSI_EXTRA_SRCS:%.c=%.o})))
+EXTRA_OBJS:=$(abspath $(addprefix $(NSI_BUILD_PATH)/,$(sort $(patsubst %.c,%.o,${NSI_EXTRA_SRCS:%.cpp=%.c}))))
 OBJS:=$(abspath $(addprefix $(NSI_BUILD_PATH)/,${SRCS:${NSI_PATH}%.c=%.o})) ${EXTRA_OBJS}
 
 DEPENDFILES:=$(addsuffix .d,$(basename ${OBJS}))
@@ -106,6 +112,11 @@ ${NSI_BUILD_PATH}/%.o: /%.c ${NSI_PATH}Makefile ${NSI_CONFIG_FILE}
 	@if [ ! -d $(dir $@) ]; then mkdir -p $(dir $@); fi
 	${NSI_CC} ${NSI_CPPFLAGS} ${INCLUDES} ${CFLAGS} -c $< -o $@
 
+#Extra C++ sources build:
+${NSI_BUILD_PATH}/%.o: /%.cpp ${NSI_PATH}Makefile ${NSI_CONFIG_FILE}
+	@if [ ! -d $(dir $@) ]; then mkdir -p $(dir $@); fi
+	${NSI_CXX} ${NSI_CPPFLAGS} ${INCLUDES} ${CXXFLAGS} -c $< -o $@
+
 ${NSI_BUILD_PATH}/%.o: ${NSI_PATH}/%.c ${NSI_PATH}Makefile ${NSI_CONFIG_FILE}
 	@if [ ! -d $(dir $@) ]; then mkdir -p $(dir $@); fi
 	${NSI_CC} ${NSI_CPPFLAGS} ${INCLUDES} ${CFLAGS} -c $< -o $@
@@ -128,7 +139,7 @@ ${NSI_BUILD_PATH}/%.loc_cpusw.o: /% ${NSI_CONFIG_FILE}
 
 ${NSI_EXE}: ${NSI_BUILD_PATH}/${RUNNER_LIB} ${LOCALIZED_EMBSW} ${NSI_EXTRA_LIBS} \
  ${NSI_BUILD_PATH}/linker_script.ld
-	${NSI_CC} -Wl,--whole-archive ${LOCALIZED_EMBSW} ${NSI_BUILD_PATH}/${RUNNER_LIB} \
+	${NSI_LINKER} -Wl,--whole-archive ${LOCALIZED_EMBSW} ${NSI_BUILD_PATH}/${RUNNER_LIB} \
 	  ${NSI_EXTRA_LIBS} -Wl,--no-whole-archive \
 	  -o $@ ${FINALLINK_FLAGS} -T ${NSI_BUILD_PATH}/linker_script.ld
 
diff --git a/scripts/native_simulator/common/src/include/nsi_errno.h b/scripts/native_simulator/common/src/include/nsi_errno.h
new file mode 100644
index 00000000000..317d113cdde
--- /dev/null
+++ b/scripts/native_simulator/common/src/include/nsi_errno.h
@@ -0,0 +1,115 @@
+/**
+ * Copyright (c) 2023-2024 Marcin Niestroj
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef NSI_COMMON_SRC_NSI_ERRNO_H
+#define NSI_COMMON_SRC_NSI_ERRNO_H
+
+/*
+ * Optional utility module to convert errno values from one libC to another,
+ * where one libC would normally be the embedded libC used to build the embedded code and the other
+ * the host libC.
+ *
+ * It works by converting the errno values from/to either libC into an intermediate set of values
+ * (NSI_ERRNO_MID_E*).
+ * When two components would like to exchange errors, they should include nsi_errno.h and build and
+ * link to nsi_errno.c in their context. And convert to/from these intermediate error values
+ * before passing them to/after receiving them from the other side by using
+ * nsi_errno_to_mid() / nsi_errno_from_mid().
+ */
+
+#include <errno.h>
+
+#define NSI_ERRNO_MID_EPERM             1 /**< Not owner */
+#define NSI_ERRNO_MID_ENOENT            2 /**< No such file or directory */
+#define NSI_ERRNO_MID_ESRCH             3 /**< No such context */
+#define NSI_ERRNO_MID_EINTR             4 /**< Interrupted system call */
+#define NSI_ERRNO_MID_EIO               5 /**< I/O error */
+#define NSI_ERRNO_MID_ENXIO             6 /**< No such device or address */
+#define NSI_ERRNO_MID_E2BIG             7 /**< Arg list too long */
+#define NSI_ERRNO_MID_ENOEXEC           8 /**< Exec format error */
+#define NSI_ERRNO_MID_EBADF             9 /**< Bad file number */
+#define NSI_ERRNO_MID_ECHILD           10 /**< No children */
+#define NSI_ERRNO_MID_EAGAIN           11 /**< No more contexts */
+#define NSI_ERRNO_MID_ENOMEM           12 /**< Not enough core */
+#define NSI_ERRNO_MID_EACCES           13 /**< Permission denied */
+#define NSI_ERRNO_MID_EFAULT           14 /**< Bad address */
+#define NSI_ERRNO_MID_ENOTBLK          15 /**< Block device required */
+#define NSI_ERRNO_MID_EBUSY            16 /**< Mount device busy */
+#define NSI_ERRNO_MID_EEXIST           17 /**< File exists */
+#define NSI_ERRNO_MID_EXDEV            18 /**< Cross-device link */
+#define NSI_ERRNO_MID_ENODEV           19 /**< No such device */
+#define NSI_ERRNO_MID_ENOTDIR          20 /**< Not a directory */
+#define NSI_ERRNO_MID_EISDIR           21 /**< Is a directory */
+#define NSI_ERRNO_MID_EINVAL           22 /**< Invalid argument */
+#define NSI_ERRNO_MID_ENFILE           23 /**< File table overflow */
+#define NSI_ERRNO_MID_EMFILE           24 /**< Too many open files */
+#define NSI_ERRNO_MID_ENOTTY           25 /**< Not a typewriter */
+#define NSI_ERRNO_MID_ETXTBSY          26 /**< Text file busy */
+#define NSI_ERRNO_MID_EFBIG            27 /**< File too large */
+#define NSI_ERRNO_MID_ENOSPC           28 /**< No space left on device */
+#define NSI_ERRNO_MID_ESPIPE           29 /**< Illegal seek */
+#define NSI_ERRNO_MID_EROFS            30 /**< Read-only file system */
+#define NSI_ERRNO_MID_EMLINK           31 /**< Too many links */
+#define NSI_ERRNO_MID_EPIPE            32 /**< Broken pipe */
+#define NSI_ERRNO_MID_EDOM             33 /**< Argument too large */
+#define NSI_ERRNO_MID_ERANGE           34 /**< Result too large */
+#define NSI_ERRNO_MID_ENOMSG           35 /**< Unexpected message type */
+#define NSI_ERRNO_MID_EDEADLK          45 /**< Resource deadlock avoided */
+#define NSI_ERRNO_MID_ENOLCK           46 /**< No locks available */
+#define NSI_ERRNO_MID_ENOSTR           60 /**< STREAMS device required */
+#define NSI_ERRNO_MID_ENODATA          61 /**< Missing expected message data */
+#define NSI_ERRNO_MID_ETIME            62 /**< STREAMS timeout occurred */
+#define NSI_ERRNO_MID_ENOSR            63 /**< Insufficient memory */
+#define NSI_ERRNO_MID_EPROTO           71 /**< Generic STREAMS error */
+#define NSI_ERRNO_MID_EBADMSG          77 /**< Invalid STREAMS message */
+#define NSI_ERRNO_MID_ENOSYS           88 /**< Function not implemented */
+#define NSI_ERRNO_MID_ENOTEMPTY        90 /**< Directory not empty */
+#define NSI_ERRNO_MID_ENAMETOOLONG     91 /**< File name too long */
+#define NSI_ERRNO_MID_ELOOP            92 /**< Too many levels of symbolic links */
+#define NSI_ERRNO_MID_EOPNOTSUPP       95 /**< Operation not supported on socket */
+#define NSI_ERRNO_MID_EPFNOSUPPORT     96 /**< Protocol family not supported */
+#define NSI_ERRNO_MID_ECONNRESET      104 /**< Connection reset by peer */
+#define NSI_ERRNO_MID_ENOBUFS         105 /**< No buffer space available */
+#define NSI_ERRNO_MID_EAFNOSUPPORT    106 /**< Addr family not supported */
+#define NSI_ERRNO_MID_EPROTOTYPE      107 /**< Protocol wrong type for socket */
+#define NSI_ERRNO_MID_ENOTSOCK        108 /**< Socket operation on non-socket */
+#define NSI_ERRNO_MID_ENOPROTOOPT     109 /**< Protocol not available */
+#define NSI_ERRNO_MID_ESHUTDOWN       110 /**< Can't send after socket shutdown */
+#define NSI_ERRNO_MID_ECONNREFUSED    111 /**< Connection refused */
+#define NSI_ERRNO_MID_EADDRINUSE      112 /**< Address already in use */
+#define NSI_ERRNO_MID_ECONNABORTED    113 /**< Software caused connection abort */
+#define NSI_ERRNO_MID_ENETUNREACH     114 /**< Network is unreachable */
+#define NSI_ERRNO_MID_ENETDOWN        115 /**< Network is down */
+#define NSI_ERRNO_MID_ETIMEDOUT       116 /**< Connection timed out */
+#define NSI_ERRNO_MID_EHOSTDOWN       117 /**< Host is down */
+#define NSI_ERRNO_MID_EHOSTUNREACH    118 /**< No route to host */
+#define NSI_ERRNO_MID_EINPROGRESS     119 /**< Operation now in progress */
+#define NSI_ERRNO_MID_EALREADY        120 /**< Operation already in progress */
+#define NSI_ERRNO_MID_EDESTADDRREQ    121 /**< Destination address required */
+#define NSI_ERRNO_MID_EMSGSIZE        122 /**< Message size */
+#define NSI_ERRNO_MID_EPROTONOSUPPORT 123 /**< Protocol not supported */
+#define NSI_ERRNO_MID_ESOCKTNOSUPPORT 124 /**< Socket type not supported */
+#define NSI_ERRNO_MID_EADDRNOTAVAIL   125 /**< Can't assign requested address */
+#define NSI_ERRNO_MID_ENETRESET       126 /**< Network dropped connection on reset */
+#define NSI_ERRNO_MID_EISCONN         127 /**< Socket is already connected */
+#define NSI_ERRNO_MID_ENOTCONN        128 /**< Socket is not connected */
+#define NSI_ERRNO_MID_ETOOMANYREFS    129 /**< Too many references: can't splice */
+#define NSI_ERRNO_MID_ENOTSUP         134 /**< Unsupported value */
+#define NSI_ERRNO_MID_EILSEQ          138 /**< Illegal byte sequence */
+#define NSI_ERRNO_MID_EOVERFLOW       139 /**< Value overflow */
+#define NSI_ERRNO_MID_ECANCELED       140 /**< Operation canceled */
+
+/* Convert a errno value to the intermediate represetation to pass it to the other side */
+int nsi_errno_to_mid(int err);
+/* Convert a errno value from the intermediate representation into the local libC value */
+int nsi_errno_from_mid(int err);
+/* Return the middleground representation of the current host libC errno */
+int nsi_get_errno_in_mid(void);
+/* Return the local representation of the current host libC errno */
+int nsi_host_get_errno(void);
+
+#endif /* NSI_COMMON_SRC_NSI_ERRNO_H */
diff --git a/scripts/native_simulator/common/src/include/nsi_utils.h b/scripts/native_simulator/common/src/include/nsi_utils.h
index 43d171a8e89..aff6e9aff43 100644
--- a/scripts/native_simulator/common/src/include/nsi_utils.h
+++ b/scripts/native_simulator/common/src/include/nsi_utils.h
@@ -21,6 +21,8 @@
 #define NSI_MAX(a, b)  (((a) > (b)) ? (a) : (b))
 #define NSI_MIN(a, b) (((a) < (b)) ? (a) : (b))
 
+#define NSI_ARRAY_SIZE(array) (sizeof(array) / sizeof((array)[0]))
+
 #ifndef NSI_ARG_UNUSED
 #define NSI_ARG_UNUSED(x) (void)(x)
 #endif
diff --git a/scripts/native_simulator/common/src/nsi_errno.c b/scripts/native_simulator/common/src/nsi_errno.c
new file mode 100644
index 00000000000..25b58e85fa8
--- /dev/null
+++ b/scripts/native_simulator/common/src/nsi_errno.c
@@ -0,0 +1,142 @@
+/**
+ * Copyright (c) 2023-2024 Marcin Niestroj
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "nsi_errno.h"
+#include "nsi_utils.h"
+
+struct nsi_errno_mid_map {
+	/** Embedded/host error code */
+	int err;
+	/** NSI_errno middleground error code */
+	int mid_err;
+};
+
+#define ERR(_name) {_name, NSI_ERRNO_MID_##_name}
+
+static const struct nsi_errno_mid_map map[] = {
+	ERR(EPERM),
+	ERR(ENOENT),
+	ERR(ESRCH),
+	ERR(EINTR),
+	ERR(EIO),
+	ERR(ENXIO),
+	ERR(E2BIG),
+	ERR(ENOEXEC),
+	ERR(EBADF),
+	ERR(ECHILD),
+	ERR(EAGAIN),
+	ERR(ENOMEM),
+	ERR(EACCES),
+	ERR(EFAULT),
+	ERR(ENOTBLK),
+	ERR(EBUSY),
+	ERR(EEXIST),
+	ERR(EXDEV),
+	ERR(ENODEV),
+	ERR(ENOTDIR),
+	ERR(EISDIR),
+	ERR(EINVAL),
+	ERR(ENFILE),
+	ERR(EMFILE),
+	ERR(ENOTTY),
+	ERR(ETXTBSY),
+	ERR(EFBIG),
+	ERR(ENOSPC),
+	ERR(ESPIPE),
+	ERR(EROFS),
+	ERR(EMLINK),
+	ERR(EPIPE),
+	ERR(EDOM),
+	ERR(ERANGE),
+	ERR(ENOMSG),
+	ERR(EDEADLK),
+	ERR(ENOLCK),
+	ERR(ENOSTR),
+	ERR(ENODATA),
+	ERR(ETIME),
+	ERR(ENOSR),
+	ERR(EPROTO),
+	ERR(EBADMSG),
+	ERR(ENOSYS),
+	ERR(ENOTEMPTY),
+	ERR(ENAMETOOLONG),
+	ERR(ELOOP),
+	ERR(EOPNOTSUPP),
+	ERR(EPFNOSUPPORT),
+	ERR(ECONNRESET),
+	ERR(ENOBUFS),
+	ERR(EAFNOSUPPORT),
+	ERR(EPROTOTYPE),
+	ERR(ENOTSOCK),
+	ERR(ENOPROTOOPT),
+	ERR(ESHUTDOWN),
+	ERR(ECONNREFUSED),
+	ERR(EADDRINUSE),
+	ERR(ECONNABORTED),
+	ERR(ENETUNREACH),
+	ERR(ENETDOWN),
+	ERR(ETIMEDOUT),
+	ERR(EHOSTDOWN),
+	ERR(EHOSTUNREACH),
+	ERR(EINPROGRESS),
+	ERR(EALREADY),
+	ERR(EDESTADDRREQ),
+	ERR(EMSGSIZE),
+	ERR(EPROTONOSUPPORT),
+	ERR(ESOCKTNOSUPPORT),
+	ERR(EADDRNOTAVAIL),
+	ERR(ENETRESET),
+	ERR(EISCONN),
+	ERR(ENOTCONN),
+	ERR(ETOOMANYREFS),
+	ERR(ENOTSUP),
+	ERR(EILSEQ),
+	ERR(EOVERFLOW),
+	ERR(ECANCELED),
+};
+
+int nsi_errno_to_mid(int err)
+{
+	if (err == 0) {
+		return err;
+	}
+
+	for (int i = 0; i < NSI_ARRAY_SIZE(map); i++) {
+		if (map[i].err == err) {
+			return map[i].mid_err;
+		}
+	}
+
+	return err;
+}
+
+int nsi_errno_from_mid(int err)
+{
+	if (err == 0) {
+		return err;
+	}
+
+	for (int i = 0; i < NSI_ARRAY_SIZE(map); i++) {
+		if (map[i].mid_err == err) {
+			return map[i].err;
+		}
+	}
+
+	return err;
+}
+
+#if defined(NSI_RUNNER_BUILD)
+int nsi_get_errno_in_mid(void)
+{
+	return nsi_errno_to_mid(errno);
+}
+#endif
+
+int nsi_host_get_errno(void)
+{
+	return nsi_errno_from_mid(nsi_get_errno_in_mid());
+}
diff --git a/scripts/pylib/power-twister-harness/abstract/PowerMonitor.py b/scripts/pylib/power-twister-harness/abstract/PowerMonitor.py
new file mode 100644
index 00000000000..75618b681f0
--- /dev/null
+++ b/scripts/pylib/power-twister-harness/abstract/PowerMonitor.py
@@ -0,0 +1,40 @@
+# Copyright: (c)  2025, Intel Corporation
+# Author: Arkadiusz Cholewinski <arkadiuszx.cholewinski@intel.com>
+
+import string
+from abc import ABC, abstractmethod
+
+
+class PowerMonitor(ABC):
+    @abstractmethod
+    def init(self, device_id: string):
+        """
+        Abstract method to initialize the power monitor.
+
+        Agr:
+            string: Address of the power monitor
+
+        Return:
+            bool: True of False.
+        """
+
+    @abstractmethod
+    def measure(self, duration: int):
+        """
+        Abstract method to measure current with specified measurement time.
+
+        Args:
+            duration (int): The duration of the measurement in seconds.
+        """
+
+    @abstractmethod
+    def get_data(self, duration: int) -> list[float]:
+        """
+        Measure current with specified measurement time.
+
+        Args:
+            duration (int): The duration of the measurement in seconds.
+
+        Returns:
+            List[float]: An array of measured current values in amperes.
+        """
diff --git a/scripts/pylib/power-twister-harness/conftest.py b/scripts/pylib/power-twister-harness/conftest.py
new file mode 100644
index 00000000000..01c880043e5
--- /dev/null
+++ b/scripts/pylib/power-twister-harness/conftest.py
@@ -0,0 +1,61 @@
+# Copyright: (c)  2025, Intel Corporation
+import json
+import logging
+
+import pytest
+from twister_harness import DeviceAdapter
+
+
+def pytest_addoption(parser):
+    parser.addoption('--testdata')
+
+
+@pytest.fixture
+def probe_class(request, probe_path):
+    path = probe_path  # Get path of power device
+    if request.param == 'stm_powershield':
+        from stm32l562e_dk.PowerShield import PowerShield
+
+        probe = PowerShield()  # Instantiate the power monitor probe
+        probe.connect(path)
+        probe.init()
+
+    yield probe
+
+    if request.param == 'stm_powershield':
+        probe.disconnect()
+
+
+@pytest.fixture(name='probe_path', scope='session')
+def fixture_probe_path(request, dut: DeviceAdapter):
+    for fixture in dut.device_config.fixtures:
+        if fixture.startswith('pm_probe'):
+            probe_port = fixture.split(':')[1]
+    return probe_port
+
+
+@pytest.fixture(name='test_data', scope='session')
+def fixture_test_data(request):
+    # Get test data from the configuration and parse it into a dictionary
+    measurements = request.config.getoption("--testdata")
+    measurements = measurements.replace("'", '"')  # Ensure the data is properly formatted as JSON
+    measurements_dict = json.loads(measurements)
+
+    # Data validation
+    required_keys = [
+        'elements_to_trim',
+        'min_peak_distance',
+        'min_peak_height',
+        'peak_padding',
+        'measurement_duration',
+        'num_of_transitions',
+        'expected_rms_values',
+        'tolerance_percentage',
+    ]
+
+    for key in required_keys:
+        if key not in measurements_dict:
+            logging.error(f"Missing required test data key: {key}")
+            pytest.fail(f"Missing required test data key: {key}")
+
+    return measurements_dict
diff --git a/scripts/pylib/power-twister-harness/stm32l562e_dk/PowerShield.py b/scripts/pylib/power-twister-harness/stm32l562e_dk/PowerShield.py
new file mode 100644
index 00000000000..c5b95bd9864
--- /dev/null
+++ b/scripts/pylib/power-twister-harness/stm32l562e_dk/PowerShield.py
@@ -0,0 +1,484 @@
+# Copyright: (c)  2025, Intel Corporation
+# Author: Arkadiusz Cholewinski <arkadiuszx.cholewinski@intel.com>
+
+import csv
+import logging
+import queue
+import re
+import threading
+import time
+
+import utils.UtilityFunctions as UtilityFunctions
+from abstract.PowerMonitor import PowerMonitor
+from stm32l562e_dk.PowerShieldConfig import PowerShieldConf
+from stm32l562e_dk.PowerShieldData import PowerShieldData
+from stm32l562e_dk.SerialHandler import SerialHandler
+
+
+class PowerShield(PowerMonitor):
+    def __init__(self):
+        """
+        Initializes the PowerShield.
+        """
+        self.handler = None
+        self.dataQueue = queue.Queue()
+        self.acqComplete = False
+        self.acqStart = False
+        self.target_voltage = None
+        self.target_temperature = None
+        self.acqTimeoutThread = None
+        self.power_shield_conf = PowerShieldConf()
+        self.power_shield_data = PowerShieldData()
+
+    def init(self):
+        """
+        Initializes the power monitor.
+        """
+        self.__take_control()
+        self.__set_voltage(self.power_shield_conf.target_voltage)
+        self.__set_format(self.power_shield_conf.data_format)
+        self.__set_func_mode(self.power_shield_conf.function_mode)
+
+    def connect(self, power_device_path: str):
+        """Opens the connection using the SerialHandler."""
+        self.handler = SerialHandler(power_device_path, 3686400)
+        self.handler.open()
+
+    def disconnect(self):
+        """Closes the connection using the SerialHandler."""
+        self.handler.close()
+
+    def __send_command(self, command: str, expected_ack: str = None, ack: bool = False) -> str:
+        """
+        Sends a command to the device, retrieves the response,
+        and optionally verifies the acknowledgment.
+
+        :param command: The command to send.
+        :param expected_ack: The expected acknowledgment response (e.g., "ack htc").
+        :return: The response received from the device.
+        """
+        if not self.handler.is_open():
+            logging.info(f"Error: Connection is not open. Cannot send command: {command}")
+            return ""
+
+        logging.debug(f"Sending command: {command}")
+        self.handler.send_cmd(command)
+        if ack:
+            response = self.handler.receive_cmd()
+            logging.debug(f"Response: {response}")
+
+            # Check if the response contains the expected acknowledgment
+            if expected_ack and expected_ack not in response:
+                logging.error(f"Error: Expected acknowledgment '{expected_ack}' not found.")
+                return ""
+
+            return response
+        return 0
+
+    def __test_communication(self):
+        """
+        Sends a version command to the device.
+        """
+        if not self.handler.is_open():
+            logging.error("Error: Connection is not open. Cannot send version command.")
+            return ""
+        command = 'version'
+        logging.info(f"Sending command: {command}")
+        self.handler.send_cmd(command)
+        response = self.handler.receive_cmd()
+        logging.info(f"Response: {response}")
+        return response
+
+    def __reset(self):
+        """
+        Sends the reset command ('PSRST') to the power monitor device,
+        closes the connection, waits for the reset process to complete,
+        and repeatedly attempts to reconnect until successful.
+        """
+        command = "psrst"
+
+        if not self.handler.is_open():
+            logging.error("Error: Connection is not open. Cannot reset the device.")
+            return
+
+        logging.info(f"Sending reset command: {command}")
+        self.handler.send_cmd(command)
+
+        # Close the connection
+        self.handler.close()
+        self.handler.serial_connection = None
+
+        time.sleep(5)
+        # Attempt to reopen the connection
+        try:
+            self.handler.open()
+            logging.info("Connection reopened after reset.")
+        except Exception as e:
+            logging.error(f"Failed to reopen connection after reset: {e}")
+
+    def __get_voltage_level(self) -> float:
+        """
+        Sends the 'volt get' command and returns the voltage value as a float.
+
+        :return: The voltage level as a float, in volts (V).
+        """
+        command = 'volt get'
+        response = self.__send_command(command, expected_ack="ack volt get", ack=True)
+
+        # If response contains the expected acknowledgment, extract and return the voltage
+        if response:
+            parts = response.split()
+            try:
+                if len(parts) >= 5:
+                    # Use regex to find a string that matches the pattern, e.g., "3292-03"
+                    match = re.search(r'(\d+)-(\d+)', parts[5])
+                    if match:
+                        # Extract the base (3292) and exponent (03)
+                        base = match.group(1)
+                        exponent = match.group(2)
+
+                        # Construct the scientific notation string (e.g., 3292e-03)
+                        voltage_str = f"{base}e-{exponent}"
+
+                        # Convert the string into a float
+                        voltage = float(voltage_str)
+
+                        # Return the voltage as a float
+                        self.target_voltage = round(voltage, 3)
+                        return self.target_voltage
+            except ValueError:
+                logging.error("Error: Could not convert temperature value.")
+                return float('nan')
+        else:
+            logging.error("Error: No response for voltage command.")
+        return float('nan')
+
+    def __get_temperature(self, unit: str = PowerShieldConf.TemperatureUnit.CELSIUS) -> float:
+        """
+        Sends the temperature command and returns the temperature as a float.
+
+        :param unit: The unit to request the temperature in, either 'degc' or 'degf'.
+        :return: The temperature value as a float, in the specified unit (°C or °F).
+        """
+        # Send the temp command with the unit
+        response = self.__send_command(f"temp {unit}", expected_ack=f"ack temp {unit}", ack=True)
+
+        # If response contains the expected acknowledgment, extract the temperature
+        if response:
+            try:
+                # Example response format: "PowerShield > ack temp degc 28.0"
+                parts = response.split()
+                if len(parts) >= 5 and parts[5].replace('.', '', 1).isdigit():
+                    # Extract temperature and convert to float
+                    self.target_temetarute = float(parts[5])
+                    logging.info(f"Temperature: {self.target_temetarute} {unit}")
+                    return self.target_temetarute
+                else:
+                    print("Error: Temperature value not found in response.")
+                    return None
+            except ValueError:
+                logging.error("Error: Could not convert temperature value.")
+                return None
+        else:
+            logging.error("Error: No response for temp command.")
+        return None
+
+    def __take_control(self) -> str:
+        """
+        Sends the 'htc' command and verifies the acknowledgment.
+
+        :return: The acknowledgment response or error message.
+        """
+        return self.__send_command("htc", expected_ack="ack htc", ack=True)
+
+    def __set_format(self, data_format: str = PowerShieldConf.DataFormat.ASCII_DEC):
+        """
+        Sets the measurement data format.
+        The format can be either ASCII (decimal) or Binary (hexadecimal).
+
+        :param data_format: The data format to set.
+                            Options are 'ascii_dec' or 'bin_hexa'.
+        :return: None
+        """
+        # Validate the input format
+        if data_format not in vars(PowerShieldConf.DataFormat).values():
+            logging.error(
+                f"Error: Invalid format '{data_format}'. "
+                "Valid options are 'ascii_dec' or 'bin_hexa'."
+            )
+            return
+
+        command = f"format {data_format}"
+        response = self.__send_command(command, expected_ack=f"ack format {data_format}", ack=True)
+
+        # If response contains the expected acknowledgment, the format was set successfully
+        if response:
+            logging.info(f"Data format set to {data_format}.")
+        else:
+            logging.error(f"Error: Failed to set data format to {data_format}.")
+
+    def __set_frequency(self, frequency: enumerate):
+        """
+        Sets the sampling frequency for the measurement.
+        The frequency can be any valid value from the list.
+
+        :param frequency: The sampling frequency to set.
+        Valid options include:
+        {100k, 50k, 20k, 10k, 5k, 2k, 1k, 500, 200, 100, 50, 20, 10, 5, 2, 1}.
+
+        :return: None
+        """
+        # Validate the input frequency
+        if frequency not in vars(PowerShieldConf.SamplingFrequency).values():
+            logging.error(
+                f"Error: Invalid frequency '{frequency}'."
+                "Valid options are:"
+                "100k, 50k, 20k, 10k, 5k, 2k, 1k, 500, 200, 100, 50, 20, 10, 5, 2, 1."
+            )
+            return
+
+        command = f"freq {frequency}"
+        response = self.__send_command(command, expected_ack=f"ack freq {frequency}", ack=True)
+
+        if response:
+            logging.info(f"Sampling frequency set to {frequency}.")
+        else:
+            logging.error(f"Error: Failed to set sampling frequency to {frequency}.")
+
+    def __set_acquisition_time(self, acquisition_time: str = '0'):
+        command = f"acqtime {acquisition_time}"
+        response = self.__send_command(
+            command, expected_ack=f"ack acqtime {acquisition_time}", ack=True
+        )
+
+        if response:
+            logging.info(f"Acquisition time set to {acquisition_time}.")
+        else:
+            logging.error(f"Error: Failed to set acquisition time to {acquisition_time}.")
+
+    def __set_voltage(self, voltage: enumerate):
+        command = f"volt {voltage}"
+        response = self.__send_command(command, expected_ack=f"ack volt {voltage}", ack=True)
+
+        if response:
+            logging.info(f"Voltage set to {voltage}.")
+        else:
+            logging.error(f"Error: Failed to set voltage to {voltage}.")
+
+    def __set_func_mode(self, function_mode: str = PowerShieldConf.FunctionMode.HIGH):
+        """
+        Sets the acquisition mode for current measurement.
+        The function_mode can be either 'optim' or 'high'.
+
+        - 'optim': Priority on current resolution (100 nA - 10 mA) with max freq at 100 kHz.
+        - 'high': High current (30 µA - 10 mA), high frequency (50-100 kHz), high resolution.
+
+        :param mode: The acquisition mode. Must be either 'optim' or 'high'.
+        :return: None
+        """
+        # Validate the input format
+        if function_mode not in vars(PowerShieldConf.FunctionMode).values():
+            logging.error(
+                f"Error: Invalid format '{function_mode}'."
+                "Valid options are 'ascii_dec' or 'bin_hexa'."
+            )
+            return
+
+        command = f"funcmode {function_mode}"
+        response = self.__send_command(
+            command, expected_ack=f"ack funcmode {function_mode}", ack=True
+        )
+
+        if response:
+            logging.info(f"Data format set to {function_mode}.")
+        else:
+            logging.error(f"Error: Failed to set data format to {function_mode}.")
+
+    def __acq_data(self):
+        """
+        Continuously reads data from the serial port and puts it
+        into a queue until acquisition is complete.
+        """
+        logging.info("Started data acquisition...")
+        while True:
+            # Read the first byte
+            first_byte = self.handler.read_bytes(1)
+            if len(first_byte) < 1 or self.acqComplete:  # Exit conditions
+                logging.info("Stopping data acquisition...")
+                return
+
+            # Check if it's metadata
+            if first_byte == b'\xf0':  # Metadata marker
+                second_byte = self.handler.read_bytes(1)
+                # Handle metadata types
+                metadata_type = second_byte[0]
+                self.__handle_metadata(metadata_type)
+            else:
+                # Not metadata, treat as data
+                if self.acqStart:
+                    second_byte = self.handler.read_bytes(1)
+                    data = []
+                    data.append(first_byte)
+                    if len(second_byte) < 1 or self.acqComplete:
+                        logging.info("Stopping data acquisition...")
+                        return
+                    data.append(second_byte)
+                    amps = UtilityFunctions.convert_to_amps(
+                        UtilityFunctions.bytes_to_twobyte_values(data)
+                    )
+                    self.dataQueue.put([amps])
+
+    def __handle_metadata(self, metadata_type):
+        if metadata_type == 0xF1:
+            logging.info("Received Metadata: ASCII error message.")
+            # self.handle_metadata_error()
+        elif metadata_type == 0xF2:
+            logging.info("Received Metadata: ASCII information message.")
+            # self.handle_metadata_info()
+        elif metadata_type == 0xF3:
+            logging.info("Received Metadata: Timestamp message.")
+            self.__handle_metadata_timestamp()
+            self.acqStart = True
+        elif metadata_type == 0xF4:
+            logging.info("Received Metadata: End of acquisition tag.")
+            self.__handle_metadata_end()
+            self.__handle_summary()
+        elif metadata_type == 0xF5:
+            logging.info("Received Metadata: Overcurrent detected.")
+            # self.handle_metadata_overcurrent()
+        else:
+            logging.error(f"Error: Unknown Metadata Type: {metadata_type:#04x}")
+
+    def __handle_summary(self):
+        s = ""
+        while True:
+            # Read the first byte
+            x = self.handler.read_bytes(1)
+            if len(x) < 1 or x == 0xF0:
+                self.acqComplete = True
+                return s.replace("\0", "").strip().replace("\r", "").replace("\n\n\n", "\n")
+            s += str(x, encoding='ascii', errors='ignore')
+
+    def __handle_metadata_end(self):
+        """
+        Handle metadata end of acquisition message.
+        """
+        # Read the next 2 bytes
+        metadata_bytes = self.handler.read_bytes(2)
+        if len(metadata_bytes) < 2:
+            logging.error("Error: Incomplete end of acquisition metadata reveived.")
+            return
+        # Check for end tags (last 2 bytes)
+        end_tag_1 = metadata_bytes[0]
+        end_tag_2 = metadata_bytes[1]
+        if end_tag_1 != 0xFF or end_tag_2 != 0xFF:
+            logging.error("Error: Invalid metadata end tags received.")
+            return
+
+    def __handle_metadata_timestamp(self):
+        """
+        Handle metadata timestamp message. Parses and displays the timestamp and buffer load.
+        """
+        # Read the next 7 bytes (timestamp + buffer load + end tags)
+        metadata_bytes = self.handler.read_bytes(7)
+        if len(metadata_bytes) < 7:
+            logging.error("Error: Incomplete timestamp metadata received.")
+            return
+
+        # Parse the timestamp (4 bytes, big-endian)
+        timestamp_ms = int.from_bytes(metadata_bytes[0:4], byteorder='big', signed=False)
+        # Parse the buffer Tx load value (1 byte)
+        buffer_load = metadata_bytes[4]
+        # Check for end tags (last 2 bytes)
+        end_tag_1 = metadata_bytes[5]
+        end_tag_2 = metadata_bytes[6]
+        if end_tag_1 != 0xFF or end_tag_2 != 0xFF:
+            logging.error("Error: Invalid metadata end tags received.")
+            return
+
+        # Display parsed values
+        logging.info(f"Metadata Timestamp: {timestamp_ms} ms")
+        logging.info(f"Buffer Tx Load: {buffer_load}%")
+
+    def __start_measurement(self):
+        """
+        Starts the measurement by sending the 'start' command. Once the measurement starts,
+        data can be received continuously until the 'stop' command is sent.
+
+        :return: None
+        """
+        command = "start"
+        self.acqComplete = False
+        self.__send_command(command)
+
+        raw_to_file_Thread = threading.Thread(
+            target=self.__raw_to_file, args=(self.power_shield_conf.output_file,)
+        )
+        raw_to_file_Thread.start()
+        logging.info("Measurement started. Receiving data...")
+        self.__acq_data()
+        raw_to_file_Thread.join()
+
+    def __raw_to_file(self, outputFilePath: str):
+        # Open a CSV file for writing
+        with open(outputFilePath, 'w', newline='') as outputFile:
+            writer = csv.writer(outputFile)
+            while True:
+                if self.dataQueue.empty() and bool(self.acqComplete):
+                    outputFile.close()
+                    break
+                if not self.dataQueue.empty():
+                    data = self.dataQueue.get()
+                    writer.writerow(data)
+                    outputFile.flush()
+                else:
+                    time.sleep(0.1)
+
+    def measure(self, time: int, freq: str = None, reset: bool = False):
+        self.power_shield_conf.acquisition_time = time
+        _time, self.power_shield_conf.acquisition_time_unit = UtilityFunctions.convert_acq_time(
+            time
+        )
+
+        if reset:
+            self.__reset()
+        self.__take_control()
+        self.__set_format(self.power_shield_conf.data_format)
+        if freq is not None:
+            self.__set_frequency(freq)
+        else:
+            self.__set_frequency(self.power_shield_conf.sampling_frequency)
+        self.__set_acquisition_time(
+            UtilityFunctions.convert_to_scientific_notation(
+                time=_time, unit=self.power_shield_conf.acquisition_time_unit
+            )
+        )
+        self.__start_measurement()
+
+    def get_data(self, unit: str = PowerShieldConf.MeasureUnit.RAW_DATA):
+        if self.acqComplete:
+            # Open the CSV file
+            with open(self.power_shield_conf.output_file) as file:
+                csv_reader = csv.reader(file)
+                for row in csv_reader:
+                    self.power_shield_data.data.append(row[0])
+                if unit == PowerShieldConf.MeasureUnit.CURRENT_RMS:
+                    self.power_shield_data.current_RMS = UtilityFunctions.calculate_rms(
+                        self.power_shield_data.data
+                    )
+                    return self.power_shield_data.current_RMS
+                elif unit == PowerShieldConf.MeasureUnit.POWER:
+                    _delta_time = self.power_shield_conf.acquisition_time
+                    self.power_shield_data.power = 0
+                    for data in self.power_shield_data.data:
+                        self.power_shield_data.power += float(
+                            float(data) * float(_delta_time) * float(self.target_voltage)
+                        )
+                    return self.power_shield_data.power
+                elif unit == PowerShieldConf.MeasureUnit.RAW_DATA:
+                    return self.power_shield_data.data
+                else:
+                    logging.error("Error: Unknown unit of requested data")
+        else:
+            logging.info("Acquisition not complete.")
+        return None
diff --git a/scripts/pylib/power-twister-harness/stm32l562e_dk/PowerShieldConfig.py b/scripts/pylib/power-twister-harness/stm32l562e_dk/PowerShieldConfig.py
new file mode 100644
index 00000000000..abd3a9d7e32
--- /dev/null
+++ b/scripts/pylib/power-twister-harness/stm32l562e_dk/PowerShieldConfig.py
@@ -0,0 +1,79 @@
+# Copyright: (c)  2025, Intel Corporation
+# Author: Arkadiusz Cholewinski <arkadiuszx.cholewinski@intel.com>
+from dataclasses import dataclass, field
+
+
+@dataclass
+class PowerShieldConf:
+    class PowerMode:
+        """
+        Class representing power mode
+        """
+
+        AUTO = "auto"  # Power-on when acquisition start
+        ON = "on"  # Power-on manually
+        OFF = "off"  # Power-off manually
+
+    class MeasureUnit:
+        """
+        Class representing measure units.
+        """
+
+        VOLTAGE = "voltage"  # Target Volatege
+        CURRENT_RMS = "current_rms"  # Current RMS value
+        POWER = "power"  # Total power consumption
+        RAW_DATA = "rawdata"  # Get Raw Data (current probes)
+
+    class TemperatureUnit:
+        """
+        Class representing temperature units.
+        """
+
+        CELSIUS = "degc"  # Celsius temperature unit
+        FAHRENHEIT = "degf"  # Fahrenheit temperature unit
+
+    class FunctionMode:
+        """
+        Class representing functional modes of a power monitor.
+        """
+
+        OPTIM = "optim"  # Optimized mode for lower power or efficiency
+        HIGH = "high"  # High performance mode
+
+    class DataFormat:
+        """
+        Class representing different data formats for representation.
+        """
+
+        ASCII_DEC = "ascii_dec"  # ASCII encoded decimal format
+        BIN_HEXA = "bin_hexa"  # Binary/hexadecimal format
+
+    class SamplingFrequency:
+        """
+        Class representing various sampling frequencies.
+        """
+
+        FREQ_100K = "100k"  # 100 kHz frequency
+        FREQ_50K = "50k"  # 50 kHz frequency
+        FREQ_20K = "20k"  # 20 kHz frequency
+        FREQ_10K = "10k"  # 10 kHz frequency
+        FREQ_5K = "5k"  # 5 kHz frequency
+        FREQ_2K = "2k"  # 2 kHz frequency
+        FREQ_1K = "1k"  # 1 kHz frequency
+        FREQ_500 = "500"  # 500 Hz frequency
+        FREQ_200 = "200"  # 200 Hz frequency
+        FREQ_100 = "100"  # 100 Hz frequency
+        FREQ_50 = "50"  # 50 Hz frequency
+        FREQ_20 = "20"  # 20 Hz frequency
+        FREQ_10 = "10"  # 10 Hz frequency
+        FREQ_5 = "5"  # 5 Hz frequency
+        FREQ_2 = "2"  # 2 Hz frequency
+        FREQ_1 = "1"  # 1 Hz frequency
+
+    output_file: str = "rawData.csv"
+    sampling_frequency: str = SamplingFrequency.FREQ_1K
+    data_format: str = DataFormat.BIN_HEXA
+    function_mode: str = FunctionMode.HIGH
+    target_voltage: str = "3300m"
+    temperature_unit: str = TemperatureUnit.CELSIUS
+    acquisition_time: str = field(default=None, init=False)
diff --git a/scripts/pylib/power-twister-harness/stm32l562e_dk/PowerShieldData.py b/scripts/pylib/power-twister-harness/stm32l562e_dk/PowerShieldData.py
new file mode 100644
index 00000000000..db51b00b73c
--- /dev/null
+++ b/scripts/pylib/power-twister-harness/stm32l562e_dk/PowerShieldData.py
@@ -0,0 +1,9 @@
+# Copyright: (c)  2025, Intel Corporation
+# Author: Arkadiusz Cholewinski <arkadiuszx.cholewinski@intel.com>
+
+
+class PowerShieldData:
+    def __init__(self):
+        self.data = []
+        self.current_RMS = None
+        self.power = None
diff --git a/scripts/pylib/power-twister-harness/stm32l562e_dk/SerialHandler.py b/scripts/pylib/power-twister-harness/stm32l562e_dk/SerialHandler.py
new file mode 100644
index 00000000000..28812f87772
--- /dev/null
+++ b/scripts/pylib/power-twister-harness/stm32l562e_dk/SerialHandler.py
@@ -0,0 +1,80 @@
+# Copyright: (c)  2025, Intel Corporation
+# Author: Arkadiusz Cholewinski <arkadiuszx.cholewinski@intel.com>
+
+import logging
+import re
+
+import serial
+
+
+class SerialHandler:
+    def __init__(self, port: str, baudrate: int = 9600, timeout: float = 1.0):
+        """
+        Initializes the class for serial communication.
+
+        :param port: The serial port name (e.g., 'COM1', '/dev/ttyUSB0').
+        :param baudrate: The baud rate for the connection (default is 9600).
+        :param timeout: The timeout for read operations in seconds (default is 1.0).
+        """
+        self.port = port
+        self.baudrate = baudrate
+        self.timeout = timeout
+        self.serial_connection = None
+
+    def open(self):
+        """
+        Opens the serial connection.
+        """
+        if self.serial_connection is None:
+            try:
+                self.serial_connection = serial.Serial(
+                    self.port, self.baudrate, timeout=self.timeout
+                )
+                logging.info(
+                    "Connection to %s at %d baud opened successfully.", self.port, self.baudrate
+                )
+            except serial.SerialException as e:
+                logging.error("Error opening serial port %s: %s", self.port, str(e))
+                self.serial_connection = None
+                raise
+
+    def close(self):
+        """Closes the serial connection."""
+        if self.serial_connection and self.serial_connection.is_open:
+            self.serial_connection.close()
+            logging.info("Serial connection closed.")
+
+    def send_cmd(self, cmd: str):
+        """
+        Sends a command to the serial device with a newline, and prints it.
+
+        :param cmd: The command to be sent.
+        """
+        if self.serial_connection and self.serial_connection.is_open:
+            try:
+                self.serial_connection.write((cmd + "\r\n").encode('ascii'))
+            except serial.SerialException as e:
+                logging.error(f"Error sending command: {e}")
+
+    def read_bytes(self, count: int):
+        if self.serial_connection:
+            x = self.serial_connection.read(count)
+            return x
+
+    def receive_cmd(self) -> str:
+        """
+        Reads data from the serial device until no more data is available.
+
+        :return: The processed received data as a string.
+        """
+        output = ""
+        if self.serial_connection and self.serial_connection.is_open:
+            while True:
+                x = self.serial_connection.read()
+                if len(x) < 1 or x == 0xF0:
+                    return re.sub(r'(\0|\r|\n\n\n)', '', output).strip()
+                output += str(x, encoding='ascii', errors='ignore')
+
+    def is_open(self) -> bool:
+        """Checks if the connection is open."""
+        return self.serial_connection and self.serial_connection.is_open
diff --git a/scripts/pylib/power-twister-harness/test_power.py b/scripts/pylib/power-twister-harness/test_power.py
new file mode 100644
index 00000000000..b6a4158525c
--- /dev/null
+++ b/scripts/pylib/power-twister-harness/test_power.py
@@ -0,0 +1,82 @@
+# Copyright: (c)  2024, Intel Corporation
+
+import logging
+
+import pytest
+from abstract.PowerMonitor import PowerMonitor
+from twister_harness import DeviceAdapter
+from utils.UtilityFunctions import current_RMS
+
+logger = logging.getLogger(__name__)
+
+
+@pytest.mark.parametrize("probe_class", ['stm_powershield'], indirect=True)
+def test_power_harness(probe_class: PowerMonitor, test_data, request, dut: DeviceAdapter):
+    """
+    This test measures and validates the RMS current values from the power monitor
+    and compares them against expected RMS values.
+
+    Arguments:
+    probe_class -- The Abstract class of the power monitor.
+    test_data -- Fixture to prepare data.
+    request -- Request object that provides access to test configuration.
+    dut -- The Device Under Test (DUT) that the power monitor is measuring.
+    """
+
+    # Initialize the probe with the provided path
+    probe = probe_class  # Instantiate the power monitor probe
+
+    # Get test data
+    measurements_dict = test_data
+
+    # Start the measurement process with the provided duration
+    probe.measure(time=measurements_dict['measurement_duration'])
+
+    # Retrieve the measured data
+    data = probe.get_data()
+
+    # Calculate the RMS current values using utility functions
+    rms_values_measured = current_RMS(
+        data,
+        trim=measurements_dict['elements_to_trim'],
+        num_peaks=measurements_dict['num_of_transitions'],
+        peak_distance=measurements_dict['min_peak_distance'],
+        peak_height=measurements_dict['min_peak_height'],
+        padding=measurements_dict['peak_padding'],
+    )
+
+    # # Convert measured values from amps to milliamps for comparison
+    rms_values_in_milliamps = [value * 1e4 for value in rms_values_measured]
+
+    # # Log the calculated values in milliamps for debugging purposes
+    logger.debug(f"Measured RMS values in mA: {rms_values_in_milliamps}")
+
+    tuples = zip(measurements_dict['expected_rms_values'], rms_values_in_milliamps, strict=False)
+    for expected_rms_value, measured_rms_value in tuples:
+        assert is_within_tolerance(
+            measured_rms_value, expected_rms_value, measurements_dict['tolerance_percentage']
+        )
+
+
+def is_within_tolerance(measured_rms_value, expected_rms_value, tolerance_percentage) -> bool:
+    """
+    Checks if the measured RMS value is within the acceptable tolerance.
+
+    Arguments:
+    measured_rms_value -- The measured RMS current value in milliamps.
+    expected_rms_value -- The expected RMS current value in milliamps.
+    tolerance_percentage -- The allowed tolerance as a percentage of the expected value.
+
+    Returns:
+    bool -- True if the measured value is within the tolerance, False otherwise.
+    """
+    # Calculate tolerance as a percentage of the expected value
+    tolerance = (tolerance_percentage / 100) * expected_rms_value
+
+    # Log the values for debugging purposes
+    logger.debug(f"Expected RMS: {expected_rms_value:.2f} mA")
+    logger.debug(f"Tolerance: {tolerance:.2f} mA")
+    logger.debug(f"Measured  RMS: {measured_rms_value:.2f} mA")
+
+    # Check if the measured value is within the range of expected ± tolerance
+    return (expected_rms_value - tolerance) < measured_rms_value < (expected_rms_value + tolerance)
diff --git a/scripts/pylib/power-twister-harness/utils/UtilityFunctions.py b/scripts/pylib/power-twister-harness/utils/UtilityFunctions.py
new file mode 100644
index 00000000000..00ae294f3fa
--- /dev/null
+++ b/scripts/pylib/power-twister-harness/utils/UtilityFunctions.py
@@ -0,0 +1,154 @@
+# Copyright: (c)  2025, Intel Corporation
+# Author: Arkadiusz Cholewinski <arkadiuszx.cholewinski@intel.com>
+
+import numpy as np
+from scipy import signal
+
+
+def convert_acq_time(value):
+    """
+    Converts an acquisition time value to a more readable format with units.
+    - Converts values to m (milli), u (micro), or leaves them as is for whole numbers.
+
+    :param value: The numeric value to convert.
+    :return: A tuple with the value and the unit as separate elements.
+    """
+    if value < 1e-3:
+        # If the value is smaller than 1 millisecond (10^-3), express in micro (u)
+        return f"{value * 1e6:.0f}", "us"
+    elif value < 1:
+        # If the value is smaller than 1 but larger than or equal to 1 milli (10^-3)
+        return f"{value * 1e3:.0f}", "ms"
+    else:
+        # If the value is 1 or larger, express in seconds (s)
+        return f"{value:.0f}", "s"
+
+
+def calculate_rms(data):
+    """
+    Calculate the Root Mean Square (RMS) of a given data array.
+
+    :param data: List or numpy array containing the data
+    :return: RMS value
+    """
+    # Convert to a numpy array for easier mathematical operations
+    data_array = np.array(data, dtype=np.float64)  # Convert to float64 to avoid type issues
+
+    # Calculate the RMS value
+    rms = np.sqrt(np.mean(np.square(data_array)))
+    return rms
+
+
+def bytes_to_twobyte_values(data):
+    value = int.from_bytes(data[0], 'big') << 8 | int.from_bytes(data[1], 'big')
+    return value
+
+
+def convert_to_amps(value):
+    """
+    Convert amps to watts
+    """
+    amps = (value & 4095) * (16 ** (0 - (value >> 12)))
+    return amps
+
+
+def convert_to_scientific_notation(time: int, unit: str) -> str:
+    """
+    Converts time to scientific notation based on the provided unit.
+    :param time: The time value to convert.
+    :param unit: The unit of the time ('us', 'ms', or 's').
+    :return: A string representing the time in scientific notation.
+    """
+    if unit == 'us':  # microseconds
+        return f"{time}-6"
+    elif unit == 'ms':  # milliseconds
+        return f"{time}-3"
+    elif unit == 's':  # seconds
+        return f"{time}"
+    else:
+        raise ValueError("Invalid unit. Use 'us', 'ms', or 's'.")
+
+
+def current_RMS(data, trim=100, num_peaks=1, peak_height=0.008, peak_distance=40, padding=40):
+    """
+    Function to process a given data array, find peaks, split data into chunks,
+    and then compute the Root Mean Square (RMS) value for each chunk. The function
+    allows for excluding the first `trim` number of data points, specifies the
+    number of peaks to consider for chunking, and allows for configurable peak
+    height and peak distance for detecting peaks.
+
+    Args:
+    - data (list or numpy array): The input data array for RMS calculation.
+    - trim (int): The number of initial elements to exclude
+    from the data before processing (default is 100).
+    - num_peaks (int): The number of peaks to consider for splitting
+    the data into chunks (default is 1).
+    - peak_height (float): The minimum height of the peaks to consider
+    when detecting them (default is 0.008).
+    - peak_distance (int): The minimum distance (in samples) between
+    consecutive peaks (default is 40).
+    - padding (int): The padding to add around the detected peaks when
+    chunking the data (default is 40).
+
+    Returns:
+    - rms_values (list): A list of RMS values calculated
+    from the data chunks based on the detected peaks.
+
+    The function will exclude the first `trim` elements of the data and look
+    for peaks that meet the specified criteria (`peak_height` and `peak_distance`).
+    The data will be split into chunks around the detected peaks, and RMS values
+    will be computed for each chunk.
+    """
+
+    # Optionally exclude the first x elements of the data
+    data = data[trim:]
+
+    # Convert the data to a list of floats for consistency
+    data = [float(x) for x in data]
+
+    # Find the peaks in the data using the `find_peaks` function
+    peaks = signal.find_peaks(data, distance=peak_distance, height=peak_height)[0]
+
+    # Check if we have enough peaks, otherwise raise an exception
+    if len(peaks) < num_peaks:
+        raise ValueError(
+            f"Not enough peaks detected. Expected at least {num_peaks}, but found {len(peaks)}."
+        )
+
+    # Limit the number of peaks based on the `num_peaks` parameter
+    peaks = peaks[:num_peaks]
+
+    # Add the start (index 0) and end (index of the last data point) to the list of peak indices
+    indices = np.concatenate(([0], np.array(peaks), [len(data)]))
+
+    # Split the data into chunks based on the peak indices
+    # with padding of 'padding' elements at both ends
+    split_data = []
+    for i in range(len(indices) - 1):
+        start_idx = indices[i] + padding
+        end_idx = indices[i + 1] - padding
+        split_data.append(data[start_idx:end_idx])
+
+    # Function to calculate RMS for a given list of data chunks
+    def calculate_rms(chunks):
+        """
+        Helper function to compute RMS values for each data chunk.
+
+        Args:
+        - chunks (list): A list of data chunks.
+
+        Returns:
+        - rms (list): A list of RMS values, one for each data chunk.
+        """
+        rms = []
+        for chunk in chunks:
+            # Calculate RMS by taking the square root of the mean of squared values
+            rms_value = np.sqrt(np.mean(np.square(chunk)))
+            rms.append(rms_value)
+        return rms
+
+    # Calculate RMS for each chunk of data
+    rms_values = calculate_rms(split_data)
+
+    # Return the calculated RMS values
+    return rms_values
diff --git a/scripts/pylib/pytest-twister-harness/README.rst b/scripts/pylib/pytest-twister-harness/README.rst
index 99e0045ee08..81e8300d140 100644
--- a/scripts/pylib/pytest-twister-harness/README.rst
+++ b/scripts/pylib/pytest-twister-harness/README.rst
@@ -35,7 +35,7 @@ or build shell application by west and call pytest directly:
   cd ${ZEPHYR_BASE}/samples/subsys/testsuite/pytest/shell
 
   # native_sim
-  west build -p -b native_sim -- -DCONFIG_NATIVE_UART_0_ON_STDINOUT=y
+  west build -p -b native_sim -- -DCONFIG_UART_NATIVE_PTY_0_ON_STDINOUT=y
   pytest --twister-harness --device-type=native --build-dir=build -p twister_harness.plugin
 
   # QEMU
diff --git a/scripts/pylib/pytest-twister-harness/src/twister_harness/device/device_adapter.py b/scripts/pylib/pytest-twister-harness/src/twister_harness/device/device_adapter.py
index fd97972c74a..87ecac0f75a 100644
--- a/scripts/pylib/pytest-twister-harness/src/twister_harness/device/device_adapter.py
+++ b/scripts/pylib/pytest-twister-harness/src/twister_harness/device/device_adapter.py
@@ -240,7 +240,7 @@ def _handle_device_output(self) -> None:
         with open(self.handler_log_path, 'a+') as log_file:
             while self.is_device_running():
                 if self.is_device_connected():
-                    output = self._read_device_output().decode(errors='replace').strip()
+                    output = self._read_device_output().decode(errors='replace').rstrip("\r\n")
                     if output:
                         self._device_read_queue.put(output)
                         log_file.write(f'{output}\n')
diff --git a/scripts/pylib/pytest-twister-harness/src/twister_harness/device/hardware_adapter.py b/scripts/pylib/pytest-twister-harness/src/twister_harness/device/hardware_adapter.py
index 991b347b752..79a3a935644 100644
--- a/scripts/pylib/pytest-twister-harness/src/twister_harness/device/hardware_adapter.py
+++ b/scripts/pylib/pytest-twister-harness/src/twister_harness/device/hardware_adapter.py
@@ -73,6 +73,9 @@ def _prepare_runner_args(self) -> tuple[list[str], list[str]]:
             if runner == 'pyocd':
                 extra_args.append('--board-id')
                 extra_args.append(board_id)
+            elif runner == "esp32":
+                extra_args.append("--esp-device")
+                extra_args.append(board_id)
             elif runner in ('nrfjprog', 'nrfutil'):
                 extra_args.append('--dev-id')
                 extra_args.append(board_id)
diff --git a/scripts/pylib/pytest-twister-harness/src/twister_harness/device/utils.py b/scripts/pylib/pytest-twister-harness/src/twister_harness/device/utils.py
index 60ee2537bb8..787b4e6a72e 100644
--- a/scripts/pylib/pytest-twister-harness/src/twister_harness/device/utils.py
+++ b/scripts/pylib/pytest-twister-harness/src/twister_harness/device/utils.py
@@ -4,6 +4,7 @@
 
 from __future__ import annotations
 
+import contextlib
 import logging
 import os
 import platform
@@ -41,11 +42,10 @@ def terminate_process(proc: subprocess.Popen) -> None:
     """
     Try to terminate provided process and all its subprocesses recursively.
     """
-    for child in psutil.Process(proc.pid).children(recursive=True):
-        try:
-            os.kill(child.pid, signal.SIGTERM)
-        except (ProcessLookupError, psutil.NoSuchProcess):
-            pass
+    with contextlib.suppress(ProcessLookupError, psutil.NoSuchProcess):
+        for child in psutil.Process(proc.pid).children(recursive=True):
+            with contextlib.suppress(ProcessLookupError, psutil.NoSuchProcess):
+                os.kill(child.pid, signal.SIGTERM)
     proc.terminate()
     # sleep for a while before attempting to kill
     time.sleep(0.5)
diff --git a/scripts/pylib/shell-twister-harness/conftest.py b/scripts/pylib/shell-twister-harness/conftest.py
new file mode 100644
index 00000000000..54cb2239ec4
--- /dev/null
+++ b/scripts/pylib/shell-twister-harness/conftest.py
@@ -0,0 +1,7 @@
+# Copyright (c) 2025 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+
+
+def pytest_addoption(parser):
+    parser.addoption('--testdata')
diff --git a/scripts/pylib/shell-twister-harness/test_shell.py b/scripts/pylib/shell-twister-harness/test_shell.py
new file mode 100644
index 00000000000..62c22453730
--- /dev/null
+++ b/scripts/pylib/shell-twister-harness/test_shell.py
@@ -0,0 +1,41 @@
+# Copyright (c) 2025 Intel Corporation
+#
+# SPDX-License-Identifier: Apache-2.0
+import logging
+import re
+
+import pytest
+import yaml
+from twister_harness import Shell
+
+logger = logging.getLogger(__name__)
+
+
+@pytest.fixture
+def testdata_path(request):
+    return request.config.getoption("--testdata")
+
+
+def get_next_commands(testdata_path):
+    with open(testdata_path) as yaml_file:
+        data = yaml.safe_load(yaml_file)
+    for entry in data:
+        yield entry['command'], entry.get('expected', None)
+
+
+def test_shell_harness(shell: Shell, testdata_path):
+    if not testdata_path:
+        pytest.skip('testdata not provided')
+    for command, expected in get_next_commands(testdata_path):
+        logger.info('send command: %s', command)
+        lines = shell.exec_command(command)
+        if not expected:
+            logger.debug('no expected response')
+            continue
+        match = False
+        for line in lines:
+            if re.match(expected, line):
+                match = True
+                break
+        assert match, 'expected response not found'
+        logger.info('response is valid')
diff --git a/scripts/pylib/twister/__init__.py b/scripts/pylib/twister/__init__.py
new file mode 100644
index 00000000000..f90a0a326fe
--- /dev/null
+++ b/scripts/pylib/twister/__init__.py
@@ -0,0 +1,2 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
diff --git a/scripts/pylib/twister/twisterlib/__init__.py b/scripts/pylib/twister/twisterlib/__init__.py
new file mode 100644
index 00000000000..f90a0a326fe
--- /dev/null
+++ b/scripts/pylib/twister/twisterlib/__init__.py
@@ -0,0 +1,2 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
diff --git a/scripts/pylib/twister/twisterlib/config_parser.py b/scripts/pylib/twister/twisterlib/config_parser.py
index e5a379d0445..738fa8285b4 100644
--- a/scripts/pylib/twister/twisterlib/config_parser.py
+++ b/scripts/pylib/twister/twisterlib/config_parser.py
@@ -5,18 +5,21 @@
 
 import copy
 import warnings
+from typing import Any
 
 import scl
 from twisterlib.error import ConfigurationError
 
 
-def extract_fields_from_arg_list(target_fields: set, arg_list: str | list):
+def extract_fields_from_arg_list(
+    target_fields: set, arg_list: str | list
+ ) -> tuple[dict[str, list[str]], list[str]]:
     """
     Given a list of "FIELD=VALUE" args, extract values of args with a
     given field name and return the remaining args separately.
     """
-    extracted_fields = {f : list() for f in target_fields}
-    other_fields = []
+    extracted_fields: dict[str, list[str]] = {f: list() for f in target_fields}
+    other_fields: list[str] = []
 
     if isinstance(arg_list, str):
         args = arg_list.strip().split()
@@ -39,64 +42,66 @@ def extract_fields_from_arg_list(target_fields: set, arg_list: str | list):
 
     return extracted_fields, other_fields
 
+
 class TwisterConfigParser:
     """Class to read testsuite yaml files with semantic checking
     """
 
-    testsuite_valid_keys = {"tags": {"type": "set", "required": False},
-                       "type": {"type": "str", "default": "integration"},
-                       "extra_args": {"type": "list"},
-                       "extra_configs": {"type": "list"},
-                       "extra_conf_files": {"type": "list", "default": []},
-                       "extra_overlay_confs" : {"type": "list", "default": []},
-                       "extra_dtc_overlay_files": {"type": "list", "default": []},
-                       "required_snippets": {"type": "list"},
-                       "build_only": {"type": "bool", "default": False},
-                       "build_on_all": {"type": "bool", "default": False},
-                       "skip": {"type": "bool", "default": False},
-                       "slow": {"type": "bool", "default": False},
-                       "timeout": {"type": "int", "default": 60},
-                       "min_ram": {"type": "int", "default": 16},
-                       "modules": {"type": "list", "default": []},
-                       "depends_on": {"type": "set"},
-                       "min_flash": {"type": "int", "default": 32},
-                       "arch_allow": {"type": "set"},
-                       "arch_exclude": {"type": "set"},
-                       "vendor_allow": {"type": "set"},
-                       "vendor_exclude": {"type": "set"},
-                       "extra_sections": {"type": "list", "default": []},
-                       "integration_platforms": {"type": "list", "default": []},
-                       "integration_toolchains": {"type": "list", "default": []},
-                       "ignore_faults": {"type": "bool", "default": False },
-                       "ignore_qemu_crash": {"type": "bool", "default": False },
-                       "testcases": {"type": "list", "default": []},
-                       "platform_type": {"type": "list", "default": []},
-                       "platform_exclude": {"type": "set"},
-                       "platform_allow": {"type": "set"},
-                       "platform_key": {"type": "list", "default": []},
-                       "simulation_exclude": {"type": "list", "default": []},
-                       "toolchain_exclude": {"type": "set"},
-                       "toolchain_allow": {"type": "set"},
-                       "filter": {"type": "str"},
-                       "levels": {"type": "list", "default": []},
-                       "harness": {"type": "str", "default": "test"},
-                       "harness_config": {"type": "map", "default": {}},
-                       "seed": {"type": "int", "default": 0},
-                       "sysbuild": {"type": "bool", "default": False}
-                       }
-
-    def __init__(self, filename, schema):
+    testsuite_valid_keys: dict[str, dict[str, Any]] = {
+        "tags": {"type": "set", "required": False},
+        "type": {"type": "str", "default": "integration"},
+        "extra_args": {"type": "list"},
+        "extra_configs": {"type": "list"},
+        "extra_conf_files": {"type": "list", "default": []},
+        "extra_overlay_confs": {"type": "list", "default": []},
+        "extra_dtc_overlay_files": {"type": "list", "default": []},
+        "required_snippets": {"type": "list"},
+        "build_only": {"type": "bool", "default": False},
+        "build_on_all": {"type": "bool", "default": False},
+        "skip": {"type": "bool", "default": False},
+        "slow": {"type": "bool", "default": False},
+        "timeout": {"type": "int", "default": 60},
+        "min_ram": {"type": "int", "default": 16},
+        "modules": {"type": "list", "default": []},
+        "depends_on": {"type": "set"},
+        "min_flash": {"type": "int", "default": 32},
+        "arch_allow": {"type": "set"},
+        "arch_exclude": {"type": "set"},
+        "vendor_allow": {"type": "set"},
+        "vendor_exclude": {"type": "set"},
+        "extra_sections": {"type": "list", "default": []},
+        "integration_platforms": {"type": "list", "default": []},
+        "integration_toolchains": {"type": "list", "default": []},
+        "ignore_faults": {"type": "bool", "default": False},
+        "ignore_qemu_crash": {"type": "bool", "default": False},
+        "testcases": {"type": "list", "default": []},
+        "platform_type": {"type": "list", "default": []},
+        "platform_exclude": {"type": "set"},
+        "platform_allow": {"type": "set"},
+        "platform_key": {"type": "list", "default": []},
+        "simulation_exclude": {"type": "list", "default": []},
+        "toolchain_exclude": {"type": "set"},
+        "toolchain_allow": {"type": "set"},
+        "filter": {"type": "str"},
+        "levels": {"type": "list", "default": []},
+        "harness": {"type": "str", "default": "test"},
+        "harness_config": {"type": "map", "default": {}},
+        "seed": {"type": "int", "default": 0},
+        "sysbuild": {"type": "bool", "default": False}
+    }
+
+    def __init__(self, filename: str, schema: dict[str, Any]) -> None:
         """Instantiate a new TwisterConfigParser object
 
         @param filename Source .yaml file to read
         """
-        self.data = {}
         self.schema = schema
         self.filename = filename
-        self.scenarios = {}
-        self.common = {}
+        self.data: dict[str, Any] = {}
+        self.scenarios: dict[str, Any] = {}
+        self.common: dict[str, Any] = {}
 
-    def load(self):
+    def load(self) -> dict[str, Any]:
         data = scl.yaml_load_verify(self.filename, self.schema)
         self.data = data
 
@@ -106,7 +111,7 @@ def load(self):
             self.common = self.data['common']
         return data
 
-    def _cast_value(self, value, typestr):
+    def _cast_value(self, value: Any, typestr: str) -> Any:
         if typestr == "str":
             return value.strip()
 
@@ -142,7 +147,7 @@ def _cast_value(self, value, typestr):
         else:
             raise ConfigurationError(self.filename, f"unknown type '{value}'")
 
-    def get_scenario(self, name):
+    def get_scenario(self, name: str) -> dict[str, Any]:
         """Get a dictionary representing the keys/values within a scenario
 
         @param name The scenario in the .yaml file to retrieve data from
@@ -152,10 +157,10 @@ def get_scenario(self, name):
 
         # "CONF_FILE", "OVERLAY_CONFIG", and "DTC_OVERLAY_FILE" fields from each
         # of the extra_args lines
-        extracted_common = {}
-        extracted_testsuite = {}
+        extracted_common: dict = {}
+        extracted_testsuite: dict = {}
 
-        d = {}
+        d: dict[str, Any] = {}
         for k, v in self.common.items():
             if k == "extra_args":
                 # Pull out these fields and leave the rest
@@ -223,7 +228,7 @@ def get_scenario(self, name):
             self.scenarios[name].get("extra_dtc_overlay_files", [])
 
         if any({len(x) > 0 for x in extracted_common.values()}) or \
-           any({len(x) > 0 for x in extracted_testsuite.values()}):
+            any({len(x) > 0 for x in extracted_testsuite.values()}):
             warnings.warn(
                 "Do not specify CONF_FILE, OVERLAY_CONFIG, or DTC_OVERLAY_FILE "
                 "in extra_args. This feature is deprecated and will soon "
diff --git a/scripts/pylib/twister/twisterlib/coverage.py b/scripts/pylib/twister/twisterlib/coverage.py
index dd647c60ddc..3aba6705a8a 100644
--- a/scripts/pylib/twister/twisterlib/coverage.py
+++ b/scripts/pylib/twister/twisterlib/coverage.py
@@ -1,6 +1,6 @@
 # vim: set syntax=python ts=4 :
 #
-# Copyright (c) 2018-2022 Intel Corporation
+# Copyright (c) 2018-2025 Intel Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 import contextlib
@@ -15,7 +15,6 @@
 import tempfile
 
 logger = logging.getLogger('twister')
-logger.setLevel(logging.DEBUG)
 
 supported_coverage_formats = {
     "gcovr": ["html", "xml", "csv", "txt", "coveralls", "sonarqube"],
@@ -31,6 +30,10 @@ def __init__(self):
         self.gcov_tool = None
         self.base_dir = None
         self.output_formats = None
+        self.coverage_capture = True
+        self.coverage_report = True
+        self.coverage_per_instance = False
+        self.instances = {}
 
     @staticmethod
     def factory(tool, jobs=None):
@@ -109,7 +112,7 @@ def merge_hexdumps(self, hexdumps):
 
     def create_gcda_files(self, extracted_coverage_info):
         gcda_created = True
-        logger.debug("Generating gcda files")
+        logger.debug(f"Generating {len(extracted_coverage_info)} gcda files")
         for filename, hexdumps in extracted_coverage_info.items():
             # if kobject_hash is given for coverage gcovr fails
             # hence skipping it problem only in gcovr v4.1
@@ -132,7 +135,7 @@ def create_gcda_files(self, extracted_coverage_info):
                 gcda_created = False
         return gcda_created
 
-    def generate(self, outdir):
+    def capture_data(self, outdir):
         coverage_completed = True
         for filename in glob.glob(f"{outdir}/**/handler.log", recursive=True):
             gcov_data = self.__class__.retrieve_gcov_data(filename)
@@ -148,9 +151,18 @@ def generate(self, outdir):
             else:
                 logger.error(f"Gcov data capture incomplete: {filename}")
                 coverage_completed = False
+        return coverage_completed
 
+    def generate(self, outdir):
+        coverage_completed = self.capture_data(outdir) if self.coverage_capture else True
+        if not coverage_completed or not self.coverage_report:
+            return coverage_completed, {}
+        build_dirs = None
+        if not self.coverage_capture and self.coverage_report and self.coverage_per_instance:
+            build_dirs = [instance.build_dir for instance in self.instances.values()]
+        reports = {}
         with open(os.path.join(outdir, "coverage.log"), "a") as coveragelog:
-            ret = self._generate(outdir, coveragelog)
+            ret, reports = self._generate(outdir, coveragelog, build_dirs)
             if ret == 0:
                 report_log = {
                     "html": "HTML report generated: {}".format(
@@ -180,7 +192,7 @@ def generate(self, outdir):
             else:
                 coverage_completed = False
         logger.debug(f"All coverage data processed: {coverage_completed}")
-        return coverage_completed
+        return coverage_completed, reports
 
 
 class Lcov(CoverageTool):
@@ -261,24 +273,56 @@ def run_lcov(self, args, coveragelog):
         ] + parallel + args
         return self.run_command(cmd, coveragelog)
 
-    def _generate(self, outdir, coveragelog):
+
+    def _generate(self, outdir, coveragelog, build_dirs=None):
         coveragefile = os.path.join(outdir, "coverage.info")
         ztestfile = os.path.join(outdir, "ztest.info")
 
-        cmd = ["--capture", "--directory", outdir, "--output-file", coveragefile]
-        self.run_lcov(cmd, coveragelog)
+        if build_dirs:
+            files = []
+            for dir_ in build_dirs:
+                files_ = [fname for fname in
+                            [os.path.join(dir_, "coverage.info"),
+                             os.path.join(dir_, "ztest.info")]
+                          if os.path.exists(fname)]
+                if not files_:
+                    logger.debug("Coverage merge no files in: %s", dir_)
+                    continue
+                files += files_
+            logger.debug("Coverage merge %d reports in %s", len(files), outdir)
+            cmd = ["--output-file", coveragefile]
+            for filename in files:
+                cmd.append("--add-tracefile")
+                cmd.append(filename)
+        else:
+            cmd = ["--capture", "--directory", outdir, "--output-file", coveragefile]
+            if self.coverage_per_instance and len(self.instances) == 1:
+                invalid_chars = re.compile(r"[^A-Za-z0-9_]")
+                cmd.append("--test-name")
+                cmd.append(invalid_chars.sub("_", next(iter(self.instances))))
+        ret = self.run_lcov(cmd, coveragelog)
+        if ret:
+            logger.error("LCOV capture report stage failed with %s", ret)
+            return ret, {}
 
         # We want to remove tests/* and tests/ztest/test/* but save tests/ztest
         cmd = ["--extract", coveragefile,
                os.path.join(self.base_dir, "tests", "ztest", "*"),
                "--output-file", ztestfile]
-        self.run_lcov(cmd, coveragelog)
+        ret = self.run_lcov(cmd, coveragelog)
+        if ret:
+            logger.error("LCOV extract report stage failed with %s", ret)
+            return ret, {}
 
+        files = []
         if os.path.exists(ztestfile) and os.path.getsize(ztestfile) > 0:
             cmd = ["--remove", ztestfile,
                    os.path.join(self.base_dir, "tests/ztest/test/*"),
                    "--output-file", ztestfile]
-            self.run_lcov(cmd, coveragelog)
+            ret = self.run_lcov(cmd, coveragelog)
+            if ret:
+                logger.error("LCOV remove ztest report stage failed with %s", ret)
+                return ret, {}
 
             files = [coveragefile, ztestfile]
         else:
@@ -286,15 +330,26 @@ def _generate(self, outdir, coveragelog):
 
         for i in self.ignores:
             cmd = ["--remove", coveragefile, i, "--output-file", coveragefile]
-            self.run_lcov(cmd, coveragelog)
+            ret = self.run_lcov(cmd, coveragelog)
+            if ret:
+                logger.error("LCOV remove ignores report stage failed with %s", ret)
+                return ret, {}
 
         if 'html' not in self.output_formats.split(','):
-            return 0
+            return 0, {}
 
         cmd = ["genhtml", "--legend", "--branch-coverage",
                "--prefix", self.base_dir,
-               "-output-directory", os.path.join(outdir, "coverage")] + files
-        return self.run_command(cmd, coveragelog)
+               "-output-directory", os.path.join(outdir, "coverage")]
+        if self.coverage_per_instance:
+            cmd.append("--show-details")
+        cmd += files
+        ret = self.run_command(cmd, coveragelog)
+        if ret:
+            logger.error("LCOV genhtml report stage failed with %s", ret)
+
+        # TODO: Add LCOV summary coverage report.
+        return ret, { 'report': coveragefile, 'ztest': ztestfile, 'summary': None }
 
 
 class Gcovr(CoverageTool):
@@ -305,6 +360,10 @@ def __init__(self):
         self.ignore_branch_patterns = []
         self.output_formats = "html"
         self.version = self.get_version()
+        # Different ifdef-ed implementations of the same function should not be
+        # in conflict treated by GCOVR as separate objects for coverage statistics.
+        self.options = ["-v", "--merge-mode-functions=separate"]
+
 
     def get_version(self):
         try:
@@ -343,39 +402,73 @@ def _interleave_list(prefix, list):
     def _flatten_list(list):
         return [a for b in list for a in b]
 
-    def _generate(self, outdir, coveragelog):
-        coveragefile = os.path.join(outdir, "coverage.json")
-        ztestfile = os.path.join(outdir, "ztest.json")
-
+    def collect_coverage(self, outdir, coverage_file, ztest_file, coveragelog):
         excludes = Gcovr._interleave_list("-e", self.ignores)
         if len(self.ignore_branch_patterns) > 0:
             # Last pattern overrides previous values, so merge all patterns together
             merged_regex = "|".join([f"({p})" for p in self.ignore_branch_patterns])
             excludes += ["--exclude-branches-by-pattern", merged_regex]
 
-        # Different ifdef-ed implementations of the same function should not be
-        # in conflict treated by GCOVR as separate objects for coverage statistics.
-        mode_options = ["--merge-mode-functions=separate"]
-
         # We want to remove tests/* and tests/ztest/test/* but save tests/ztest
         cmd = ["gcovr", "-r", self.base_dir,
                "--gcov-ignore-parse-errors=negative_hits.warn_once_per_file",
                "--gcov-executable", self.gcov_tool,
                "-e", "tests/*"]
-        cmd += excludes + mode_options + ["--json", "-o", coveragefile, outdir]
+        cmd += excludes + self.options + ["--json", "-o", coverage_file, outdir]
         cmd_str = " ".join(cmd)
-        logger.debug(f"Running {cmd_str}...")
-        subprocess.call(cmd, stdout=coveragelog)
-
-        subprocess.call(["gcovr", "-r", self.base_dir, "--gcov-executable",
-                         self.gcov_tool, "-f", "tests/ztest", "-e",
-                         "tests/ztest/test/*", "--json", "-o", ztestfile,
-                         outdir] + mode_options, stdout=coveragelog)
-
-        if os.path.exists(ztestfile) and os.path.getsize(ztestfile) > 0:
-            files = [coveragefile, ztestfile]
+        logger.debug(f"Running: {cmd_str}")
+        coveragelog.write(f"Running: {cmd_str}\n")
+        coveragelog.flush()
+        ret = subprocess.call(cmd, stdout=coveragelog, stderr=coveragelog)
+        if ret:
+            logger.error(f"GCOVR failed with {ret}")
+            return ret, []
+
+        cmd = ["gcovr", "-r", self.base_dir] + self.options
+        cmd += ["--gcov-executable", self.gcov_tool,
+                "-f", "tests/ztest", "-e", "tests/ztest/test/*",
+                "--json", "-o", ztest_file, outdir]
+        cmd_str = " ".join(cmd)
+        logger.debug(f"Running: {cmd_str}")
+        coveragelog.write(f"Running: {cmd_str}\n")
+        coveragelog.flush()
+        ret = subprocess.call(cmd, stdout=coveragelog, stderr=coveragelog)
+        if ret:
+            logger.error(f"GCOVR ztest stage failed with {ret}")
+            return ret, []
+
+        return ret, [file_ for file_ in [coverage_file, ztest_file]
+                     if os.path.exists(file_) and os.path.getsize(file_) > 0]
+
+
+    def _generate(self, outdir, coveragelog, build_dirs=None):
+        coverage_file = os.path.join(outdir, "coverage.json")
+        coverage_summary = os.path.join(outdir, "coverage_summary.json")
+        ztest_file = os.path.join(outdir, "ztest.json")
+
+        ret = 0
+        cmd_ = []
+        files = []
+        if build_dirs:
+            for dir_ in build_dirs:
+                files_ = [fname for fname in
+                            [os.path.join(dir_, "coverage.json"),
+                             os.path.join(dir_, "ztest.json")]
+                          if os.path.exists(fname)]
+                if not files_:
+                    logger.debug(f"Coverage merge no files in: {dir_}")
+                    continue
+                files += files_
+            logger.debug(f"Coverage merge {len(files)} reports in {outdir}")
+            ztest_file = None
+            cmd_ = ["--json-pretty", "--json", coverage_file]
         else:
-            files = [coveragefile]
+            ret, files = self.collect_coverage(outdir, coverage_file, ztest_file, coveragelog)
+            logger.debug(f"Coverage collected {len(files)} reports from: {outdir}")
+
+        if not files:
+            logger.warning(f"No coverage files to compose report for {outdir}")
+            return ret, {}
 
         subdir = os.path.join(outdir, "coverage")
         os.makedirs(subdir, exist_ok=True)
@@ -396,21 +489,22 @@ def _generate(self, outdir, coveragelog):
             [report_options[r] for r in self.output_formats.split(',')]
         )
 
-        return subprocess.call(
-            ["gcovr", "-r", self.base_dir] \
-                + mode_options + gcovr_options + tracefiles, stdout=coveragelog
-        )
+        cmd = ["gcovr", "-r", self.base_dir] + self.options + gcovr_options + tracefiles
+        cmd += cmd_
+        cmd += ["--json-summary-pretty", "--json-summary", coverage_summary]
+        cmd_str = " ".join(cmd)
+        logger.debug(f"Running: {cmd_str}")
+        coveragelog.write(f"Running: {cmd_str}\n")
+        coveragelog.flush()
+        ret = subprocess.call(cmd, stdout=coveragelog, stderr=coveragelog)
+        if ret:
+            logger.error(f"GCOVR merge report stage failed with {ret}")
 
+        return ret, { 'report': coverage_file, 'ztest': ztest_file, 'summary': coverage_summary }
 
 
-def run_coverage(testplan, options):
-    use_system_gcov = False
+def choose_gcov_tool(options, is_system_gcov):
     gcov_tool = None
-
-    for plat in options.coverage_platform:
-        _plat = testplan.get_platform(plat)
-        if _plat and (_plat.type in {"native", "unit"}):
-            use_system_gcov = True
     if not options.gcov_tool:
         zephyr_sdk_gcov_tool = os.path.join(
             os.environ.get("ZEPHYR_SDK_INSTALL_DIR", default=""),
@@ -427,7 +521,7 @@ def run_coverage(testplan, options):
             except OSError:
                 shutil.copy(llvm_cov, gcov_lnk)
             gcov_tool = gcov_lnk
-        elif use_system_gcov:
+        elif is_system_gcov:
             gcov_tool = "gcov"
         elif os.path.exists(zephyr_sdk_gcov_tool):
             gcov_tool = zephyr_sdk_gcov_tool
@@ -439,10 +533,22 @@ def run_coverage(testplan, options):
     else:
         gcov_tool = str(options.gcov_tool)
 
-    logger.info("Generating coverage files...")
-    logger.info(f"Using gcov tool: {gcov_tool}")
+    return gcov_tool
+
+
+def run_coverage_tool(options, outdir, is_system_gcov, instances,
+                      coverage_capture, coverage_report):
     coverage_tool = CoverageTool.factory(options.coverage_tool, jobs=options.jobs)
-    coverage_tool.gcov_tool = gcov_tool
+    if not coverage_tool:
+        return False, {}
+
+    coverage_tool.gcov_tool = str(choose_gcov_tool(options, is_system_gcov))
+    logger.debug(f"Using gcov tool: {coverage_tool.gcov_tool}")
+
+    coverage_tool.instances = instances
+    coverage_tool.coverage_per_instance = options.coverage_per_instance
+    coverage_tool.coverage_capture = coverage_capture
+    coverage_tool.coverage_report = coverage_report
     coverage_tool.base_dir = os.path.abspath(options.coverage_basedir)
     # Apply output format default
     if options.coverage_formats is not None:
@@ -456,5 +562,34 @@ def run_coverage(testplan, options):
     # Ignore branch coverage on __ASSERT* macros
     # Covering the failing case is not desirable as it will immediately terminate the test.
     coverage_tool.add_ignore_branch_pattern(r"^\s*__ASSERT(?:_EVAL|_NO_MSG|_POST_ACTION)?\(.*")
-    coverage_completed = coverage_tool.generate(options.outdir)
-    return coverage_completed
+    return coverage_tool.generate(outdir)
+
+
+def has_system_gcov(platform):
+    return platform and (platform.type in {"native", "unit"})
+
+
+def run_coverage(options, testplan):
+    """ Summary code coverage over the full test plan's scope.
+    """
+    is_system_gcov = False
+
+    for plat in options.coverage_platform:
+        if has_system_gcov(testplan.get_platform(plat)):
+            is_system_gcov = True
+            break
+
+    return run_coverage_tool(options, options.outdir, is_system_gcov,
+                             instances=testplan.instances,
+                             coverage_capture=False,
+                             coverage_report=True)
+
+
+def run_coverage_instance(options, instance):
+    """ Per-instance code coverage called by ProjectBuilder ('coverage' operation).
+    """
+    is_system_gcov = has_system_gcov(instance.platform)
+    return run_coverage_tool(options, instance.build_dir, is_system_gcov,
+                             instances={instance.name: instance},
+                             coverage_capture=True,
+                             coverage_report=options.coverage_per_instance)
diff --git a/scripts/pylib/twister/twisterlib/environment.py b/scripts/pylib/twister/twisterlib/environment.py
index 0cf1ea18ce6..ba0c9737a8c 100644
--- a/scripts/pylib/twister/twisterlib/environment.py
+++ b/scripts/pylib/twister/twisterlib/environment.py
@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 # vim: set syntax=python ts=4 :
 #
-# Copyright (c) 2018-2024 Intel Corporation
+# Copyright (c) 2018-2025 Intel Corporation
 # Copyright 2022 NXP
 # Copyright (c) 2024 Arm Limited (or its affiliates). All rights reserved.
 #
@@ -27,7 +27,6 @@
 from twisterlib.log_helper import log_command
 
 logger = logging.getLogger('twister')
-logger.setLevel(logging.DEBUG)
 
 ZEPHYR_BASE = os.getenv("ZEPHYR_BASE")
 if not ZEPHYR_BASE:
@@ -114,6 +113,12 @@ def add_parse_arguments(parser = None) -> argparse.ArgumentParser:
        title="Memory footprint",
        description="Collect and report ROM/RAM size footprint for the test instance images built.")
 
+    coverage_group = parser.add_argument_group(
+        title="Code coverage",
+        description="Build with code coverage support, collect code coverage statistics "
+                    "executing tests, compose code coverage report at the end.\n"
+                    "Effective for devices with 'HAS_COVERAGE_SUPPORT'.")
+
     test_plan_report_xor.add_argument(
         "-E",
         "--save-tests",
@@ -128,7 +133,7 @@ def add_parse_arguments(parser = None) -> argparse.ArgumentParser:
         "--load-tests",
         metavar="FILENAME",
         action="store",
-        help="Load a list of tests and platforms to be run"
+        help="Load a list of tests and platforms to be run "
              "from a JSON file ('testplan.json' schema)."
     )
 
@@ -229,7 +234,7 @@ def add_parse_arguments(parser = None) -> argparse.ArgumentParser:
 
     test_or_build.add_argument(
         "--prep-artifacts-for-testing", action="store_true",
-        help="Generate artifacts for testing, do not attempt to run the"
+        help="Generate artifacts for testing, do not attempt to run the "
               "code on targets.")
 
     parser.add_argument(
@@ -275,6 +280,12 @@ def add_parse_arguments(parser = None) -> argparse.ArgumentParser:
         will extend the pytest_args from the harness_config in YAML file.
         """)
 
+    parser.add_argument(
+        "--ctest-args", action="append",
+        help="""Pass additional arguments to the ctest subprocess. This parameter
+        will extend the ctest_args from the harness_config in YAML file.
+        """)
+
     valgrind_asan_group.add_argument(
         "--enable-valgrind", action="store_true",
         help="""Run binary through valgrind and check for several memory access
@@ -336,10 +347,6 @@ def add_parse_arguments(parser = None) -> argparse.ArgumentParser:
                 If not provided, seed in generated by system.
                 Used only when --shuffle-tests is provided.""")
 
-    parser.add_argument("-C", "--coverage", action="store_true",
-                        help="Generate coverage reports. Implies "
-                             "--enable-coverage.")
-
     parser.add_argument(
         "-c", "--clobber-output", action="store_true",
         help="Cleaning the output directory will simply delete it instead "
@@ -349,27 +356,51 @@ def add_parse_arguments(parser = None) -> argparse.ArgumentParser:
         "--cmake-only", action="store_true",
         help="Only run cmake, do not build or run.")
 
-    parser.add_argument("--coverage-basedir", default=ZEPHYR_BASE,
-                        help="Base source directory for coverage report.")
-
-    parser.add_argument("--coverage-platform", action="append", default=[],
-                        help="Platforms to run coverage reports on. "
-                             "This option may be used multiple times. "
-                             "Default to what was selected with --platform.")
-
-    parser.add_argument("--coverage-tool", choices=['lcov', 'gcovr'], default='gcovr',
-                        help="Tool to use to generate coverage report.")
-
-    parser.add_argument(
-        "--coverage-formats",
-        action="store",
-        default=None, # default behavior is set in run_coverage
-        help="Output formats to use for generated coverage reports, as a comma-separated list. " +
-             "Valid options for 'gcovr' tool are: " +
-             ','.join(supported_coverage_formats['gcovr']) + " (html - default)." +
-             " Valid options for 'lcov' tool are: " +
-             ','.join(supported_coverage_formats['lcov']) + " (html,lcov - default)."
-        )
+    coverage_group.add_argument("--enable-coverage", action="store_true",
+                     help="Enable code coverage collection using gcov.")
+
+    coverage_group.add_argument("-C", "--coverage", action="store_true",
+                     help="Generate coverage reports. Implies "
+                          "--enable-coverage to collect the coverage data first.")
+
+    coverage_group.add_argument("--gcov-tool", type=Path, default=None,
+                     help="Path to the 'gcov' tool to use for code coverage reports. "
+                          "By default it will be chosen in the following order:"
+                          " using ZEPHYR_TOOLCHAIN_VARIANT ('llvm': from LLVM_TOOLCHAIN_PATH),"
+                          " gcov installed on the host - for 'native' or 'unit' platform types,"
+                          " using ZEPHYR_SDK_INSTALL_DIR.")
+
+    coverage_group.add_argument("--coverage-basedir", default=ZEPHYR_BASE,
+                    help="Base source directory for coverage report.")
+
+    coverage_group.add_argument("--coverage-platform", action="append", default=[],
+                    help="Platforms to run coverage reports on. "
+                         "This option may be used multiple times. "
+                         "Default to what was selected with --platform.")
+
+    coverage_group.add_argument("--coverage-tool", choices=['lcov', 'gcovr'], default='gcovr',
+                    help="Tool to use to generate coverage reports (%(default)s - default).")
+
+    coverage_group.add_argument("--coverage-formats", action="store", default=None,
+                    help="Output formats to use for generated coverage reports " +
+                         "as a comma-separated list without spaces. " +
+                         "Valid options for 'gcovr' tool are: " +
+                         ','.join(supported_coverage_formats['gcovr']) + " (html - default)." +
+                         " Valid options for 'lcov' tool are: " +
+                         ','.join(supported_coverage_formats['lcov']) + " (html,lcov - default).")
+
+    coverage_group.add_argument("--coverage-per-instance", action="store_true", default=False,
+                help="""Compose individual coverage reports for each test suite
+                        when coverage reporting is enabled; it might run in addition to
+                        the default aggregation mode which produces one coverage report for
+                        all executed test suites. Default: %(default)s""")
+
+    coverage_group.add_argument("--disable-coverage-aggregation",
+                action="store_true", default=False,
+                help="""Don't aggregate coverage report statistics for all the test suites
+                        selected to run with enabled coverage. Requires another reporting mode to be
+                        active (`--coverage-per-instance`) to have at least one of these reporting
+                        modes. Default: %(default)s""")
 
     parser.add_argument(
         "--test-config",
@@ -379,7 +410,7 @@ def add_parse_arguments(parser = None) -> argparse.ArgumentParser:
     )
 
     parser.add_argument("--level", action="store",
-        help="Test level to be used. By default, no levels are used for filtering"
+        help="Test level to be used. By default, no levels are used for filtering "
              "and do the selection based on existing filters.")
 
     parser.add_argument(
@@ -396,9 +427,6 @@ def add_parse_arguments(parser = None) -> argparse.ArgumentParser:
                         help="Specify tags of tests that should not run. "
                              "Default is to run all tests with all tags.")
 
-    parser.add_argument("--enable-coverage", action="store_true",
-                        help="Enable code coverage using gcov.")
-
     parser.add_argument(
         "--enable-lsan", action="store_true",
         help="""Enable leak sanitizer to check for heap memory leaks.
@@ -431,10 +459,6 @@ def add_parse_arguments(parser = None) -> argparse.ArgumentParser:
                         help="Do not filter based on toolchain, use the set "
                              " toolchain unconditionally")
 
-    parser.add_argument("--gcov-tool", type=Path, default=None,
-                        help="Path to the gcov tool to use for code coverage "
-                             "reports")
-
     footprint_group.add_argument(
         "--create-rom-ram-report",
         action="store_true",
@@ -458,12 +482,6 @@ def add_parse_arguments(parser = None) -> argparse.ArgumentParser:
         action="store_true",
         help="Collect and report ROM/RAM section sizes for each test image built.")
 
-    parser.add_argument(
-        "--disable-unrecognized-section-test",
-        action="store_true",
-        default=False,
-        help="Don't error on unrecognized sections in the binary images.")
-
     footprint_group.add_argument(
         "--footprint-from-buildlog",
         action = "store_true",
@@ -553,6 +571,11 @@ def add_parse_arguments(parser = None) -> argparse.ArgumentParser:
         which only removes artifacts of passing tests. If you wish to
         remove all artificats including those of failed tests, use 'all'.""")
 
+    parser.add_argument(
+        "--keep-artifacts", action="append", default=[],
+        help="""Keep specified artifacts when cleaning up at runtime. Multiple invocations
+        are possible."""
+    )
     test_xor_generator.add_argument(
         "-N", "--ninja", action="store_true",
         default=not any(a in sys.argv for a in ("-k", "--make")),
@@ -599,7 +622,7 @@ def add_parse_arguments(parser = None) -> argparse.ArgumentParser:
 
     parser.add_argument(
         "--detailed-skipped-report", action="store_true",
-        help="Generate a detailed report with all skipped test cases"
+        help="Generate a detailed report with all skipped test cases "
              "including those that are filtered based on testsuite definition."
         )
 
@@ -671,7 +694,7 @@ def add_parse_arguments(parser = None) -> argparse.ArgumentParser:
     parser.add_argument(
         "--quarantine-verify",
         action="store_true",
-        help="Use the list of test scenarios under quarantine and run them"
+        help="Use the list of test scenarios under quarantine and run them "
              "to verify their current status.")
 
     parser.add_argument(
@@ -896,6 +919,21 @@ def parse_arguments(
     if options.enable_coverage and not options.coverage_platform:
         options.coverage_platform = options.platform
 
+    if (
+        (not options.coverage)
+        and (options.disable_coverage_aggregation or options.coverage_per_instance)
+    ):
+        logger.error("Enable coverage reporting to set its aggregation mode.")
+        sys.exit(1)
+
+    if (
+        options.coverage
+        and options.disable_coverage_aggregation and (not options.coverage_per_instance)
+    ):
+        logger.error("At least one coverage reporting mode should be enabled: "
+                     "either aggregation, or per-instance, or both.")
+        sys.exit(1)
+
     if options.coverage_formats:
         for coverage_format in options.coverage_formats.split(','):
             if coverage_format not in supported_coverage_formats[options.coverage_tool]:
diff --git a/scripts/pylib/twister/twisterlib/error.py b/scripts/pylib/twister/twisterlib/error.py
index 26180653a95..7a88a5d9d54 100644
--- a/scripts/pylib/twister/twisterlib/error.py
+++ b/scripts/pylib/twister/twisterlib/error.py
@@ -6,7 +6,7 @@
 import traceback
 
 logger = logging.getLogger('twister')
-logger.setLevel(logging.DEBUG)
+
 
 class TwisterException(Exception):
     def __init__(self, message="TwisterException"):
diff --git a/scripts/pylib/twister/twisterlib/handlers.py b/scripts/pylib/twister/twisterlib/handlers.py
index eb7d90ddd3e..dc1ff258935 100755
--- a/scripts/pylib/twister/twisterlib/handlers.py
+++ b/scripts/pylib/twister/twisterlib/handlers.py
@@ -47,7 +47,6 @@
         raise capture_error
 
 logger = logging.getLogger('twister')
-logger.setLevel(logging.DEBUG)
 
 
 def terminate_process(proc):
@@ -59,9 +58,10 @@ def terminate_process(proc):
     so we need to use try_kill_process_by_pid.
     """
 
-    for child in psutil.Process(proc.pid).children(recursive=True):
-        with contextlib.suppress(ProcessLookupError, psutil.NoSuchProcess):
-            os.kill(child.pid, signal.SIGTERM)
+    with contextlib.suppress(ProcessLookupError, psutil.NoSuchProcess):
+        for child in psutil.Process(proc.pid).children(recursive=True):
+            with contextlib.suppress(ProcessLookupError, psutil.NoSuchProcess):
+                os.kill(child.pid, signal.SIGTERM)
     proc.terminate()
     # sleep for a while before attempting to kill
     time.sleep(0.5)
@@ -565,14 +565,13 @@ def _create_command(self, runner, hardware):
 
                 board_id = hardware.probe_id or hardware.id
                 product = hardware.product
-                serial_port = hardware.serial
                 if board_id is not None:
                     if runner in ("pyocd", "nrfjprog", "nrfutil"):
                         command_extra_args.append("--dev-id")
                         command_extra_args.append(board_id)
                     elif runner == "esp32":
                         command_extra_args.append("--esp-device")
-                        command_extra_args.append(serial_port)
+                        command_extra_args.append(board_id)
                     elif (
                         runner == "openocd"
                         and product == "STM32 STLink"
@@ -595,7 +594,7 @@ def _create_command(self, runner, hardware):
                         # --probe=#<number> select by probe index
                         # --probe=<serial number> select by probe serial number
                         command.append(f"--probe={board_id}")
-                    elif runner == "stm32cubeprogrammer":
+                    elif runner == "stm32cubeprogrammer" and product != "BOOT-SERIAL":
                         command.append(f"--tool-opt=sn={board_id}")
 
                     # Receive parameters from runner_params field.
diff --git a/scripts/pylib/twister/twisterlib/hardwaremap.py b/scripts/pylib/twister/twisterlib/hardwaremap.py
index 74e97def989..5c0c5eb1238 100644
--- a/scripts/pylib/twister/twisterlib/hardwaremap.py
+++ b/scripts/pylib/twister/twisterlib/hardwaremap.py
@@ -30,7 +30,6 @@
     print("Install tabulate python module with pip to use --device-testing option.")
 
 logger = logging.getLogger('twister')
-logger.setLevel(logging.DEBUG)
 
 
 class DUT:
@@ -383,6 +382,9 @@ def readlink(link):
                 logger.warning(f"Unsupported device ({d.manufacturer}): {d}")
 
     def save(self, hwm_file):
+        # list of board ids with boot-serial sequence
+        boot_ids = []
+
         # use existing map
         self.detected.sort(key=lambda x: x.serial or '')
         if os.path.exists(hwm_file):
@@ -391,10 +393,13 @@ def save(self, hwm_file):
                 if hwm:
                     hwm.sort(key=lambda x: x.get('id', ''))
 
-                    # disconnect everything
+                    # disconnect everything except boards with boot-serial sequence
                     for h in hwm:
-                        h['connected'] = False
-                        h['serial'] = None
+                        if h['product'] != 'BOOT-SERIAL' :
+                            h['connected'] = False
+                            h['serial'] = None
+                        else :
+                            boot_ids.append(h['id'])
 
                     for _detected in self.detected:
                         for h in hwm:
@@ -419,6 +424,11 @@ def save(self, hwm_file):
                 else:
                     hwm = new
 
+            #remove duplicated devices with unknown platform names before saving the file
+            for h in hwm :
+                if h['id'] in boot_ids and h['platform'] == 'unknown':
+                    hwm.remove(h)
+
             with open(hwm_file, 'w') as yaml_file:
                 yaml.dump(hwm, yaml_file, Dumper=Dumper, default_flow_style=False)
 
diff --git a/scripts/pylib/twister/twisterlib/harness.py b/scripts/pylib/twister/twisterlib/harness.py
index 9f5bd70b20d..33120ccf7aa 100644
--- a/scripts/pylib/twister/twisterlib/harness.py
+++ b/scripts/pylib/twister/twisterlib/harness.py
@@ -16,6 +16,8 @@
 from collections import OrderedDict
 from enum import Enum
 
+import junitparser.junitparser as junit
+import yaml
 from pytest import ExitCode
 from twisterlib.constants import SUPPORTED_SIMS_IN_PYTEST
 from twisterlib.environment import PYTEST_PLUGIN_INSTALLED, ZEPHYR_BASE
@@ -26,7 +28,6 @@
 from twisterlib.testinstance import TestInstance
 
 logger = logging.getLogger('twister')
-logger.setLevel(logging.DEBUG)
 
 _WINDOWS = platform.system() == 'Windows'
 
@@ -52,7 +53,8 @@ def __init__(self):
         self.capture_coverage = False
         self.next_pattern = 0
         self.record = None
-        self.record_pattern = None
+        self.record_patterns = []
+        self.record_merge = False
         self.record_as_json = None
         self.recording = []
         self.ztest = False
@@ -89,6 +91,7 @@ def configure(self, instance):
         config = instance.testsuite.harness_config
         self.id = instance.testsuite.id
         self.run_id = instance.run_id
+        self.expect_reboot = getattr(instance.testsuite, 'expect_reboot', False)
         if instance.testsuite.ignore_faults:
             self.fail_on_fault = False
 
@@ -98,7 +101,8 @@ def configure(self, instance):
             self.ordered = config.get('ordered', True)
             self.record = config.get('record', {})
             if self.record:
-                self.record_pattern = re.compile(self.record.get("regex", ""))
+                self.record_patterns = [re.compile(p) for p in self.record.get("regex", [])]
+                self.record_merge = self.record.get("merge", False)
                 self.record_as_json = self.record.get("as_json")
 
     def build(self):
@@ -124,17 +128,27 @@ def translate_record(self, record: dict) -> dict:
                     record[k] = { 'ERROR': { 'msg': str(parse_error), 'doc': record[k] } }
         return record
 
-    def parse_record(self, line) -> re.Match:
-        match = None
-        if self.record_pattern:
-            match = self.record_pattern.search(line)
+    def parse_record(self, line) -> int:
+        match_cnt = 0
+        for record_pattern in self.record_patterns:
+            match = record_pattern.search(line)
             if match:
+                match_cnt += 1
                 rec = self.translate_record(
                     { k:v.strip() for k,v in match.groupdict(default="").items() }
                 )
-                self.recording.append(rec)
-        return match
-    #
+                if self.record_merge and len(self.recording) > 0:
+                    for k,v in rec.items():
+                        if k in self.recording[0]:
+                            if isinstance(self.recording[0][k], list):
+                                self.recording[0][k].append(v)
+                            else:
+                                self.recording[0][k] = [self.recording[0][k], v]
+                        else:
+                            self.recording[0][k] = v
+                else:
+                    self.recording.append(rec)
+        return match_cnt
 
     def process_test(self, line):
 
@@ -183,7 +197,7 @@ def handle(self, line):
         ''' Test cases that make use of this harness care about results given
             by Robot Framework which is called in run_robot_test(), so works of this
             handle is trying to give a PASS or FAIL to avoid timeout, nothing
-            is writen into handler.log
+            is written into handler.log
         '''
         self.instance.status = TwisterStatus.PASS
         tc = self.instance.get_case_or_create(self.id)
@@ -388,11 +402,9 @@ def generate_command(self):
             '-s', '-v',
             f'--build-dir={self.running_dir}',
             f'--junit-xml={self.report_file}',
-            '--log-file-level=DEBUG',
-            '--log-file-format=%(asctime)s.%(msecs)03d:%(levelname)s:%(name)s: %(message)s',
-            f'--log-file={self.pytest_log_file_path}',
             f'--platform={self.instance.platform.name}'
         ]
+
         command.extend([os.path.normpath(os.path.join(
             self.source_dir, os.path.expanduser(os.path.expandvars(src)))) for src in pytest_root])
 
@@ -516,9 +528,9 @@ def run_command(self, cmd, timeout):
         if proc.returncode in (ExitCode.INTERRUPTED, ExitCode.USAGE_ERROR, ExitCode.INTERNAL_ERROR):
             self.status = TwisterStatus.ERROR
             self.instance.reason = f'Pytest error - return code {proc.returncode}'
-            with open(self.pytest_log_file_path, 'w') as log_file:
-                log_file.write(shlex.join(cmd) + '\n\n')
-                log_file.write('\n'.join(self._output))
+        with open(self.pytest_log_file_path, 'w') as log_file:
+            log_file.write(shlex.join(cmd) + '\n\n')
+            log_file.write('\n'.join(self._output))
 
     @staticmethod
     def _update_command_with_env_dependencies(cmd):
@@ -618,6 +630,47 @@ def _parse_report_file(self, report):
             self.instance.reason = 'No tests collected'
 
 
+class Shell(Pytest):
+    def generate_command(self):
+        config = self.instance.testsuite.harness_config
+        pytest_root = [os.path.join(ZEPHYR_BASE, 'scripts', 'pylib', 'shell-twister-harness')]
+        config['pytest_root'] = pytest_root
+
+        command = super().generate_command()
+        if test_shell_file := self._get_shell_commands_file(config):
+            command.append(f'--testdata={test_shell_file}')
+        else:
+            logger.warning('No shell commands provided')
+        return command
+
+    def _get_shell_commands_file(self, harness_config):
+        if shell_commands := harness_config.get('shell_commands'):
+            test_shell_file = os.path.join(self.running_dir, 'test_shell.yml')
+            with open(test_shell_file, 'w') as f:
+                yaml.dump(shell_commands, f)
+            return test_shell_file
+
+        test_shell_file = harness_config.get('shell_commands_file', 'test_shell.yml')
+        test_shell_file = os.path.join(
+            self.source_dir, os.path.expanduser(os.path.expandvars(test_shell_file))
+        )
+        if os.path.exists(test_shell_file):
+            return test_shell_file
+        return None
+
+class Power(Pytest):
+    def generate_command(self):
+        config = self.instance.testsuite.harness_config
+        pytest_root = [os.path.join(ZEPHYR_BASE, 'scripts', 'pylib', 'power-twister-harness')]
+        config['pytest_root'] = pytest_root
+
+        command = super().generate_command()
+
+        if self.instance.testsuite.harness == 'power':
+            measurements = config.get('power_measurements')
+            command.append(f'--testdata={measurements}')
+        return command
+
 class Gtest(Harness):
     ANSI_ESCAPE = re.compile(r'\x1B(?:[@-Z\\-_]|\[[0-?]*[ -/]*[@-~])')
     _NAME_PATTERN = "[a-zA-Z_][a-zA-Z0-9_]*"
@@ -733,6 +786,9 @@ def _check_result(self, line):
 class Test(Harness):
     __test__ = False  # for pytest to skip this class when collects tests
 
+    # Ztest log patterns don't require to match the line start exactly: there are platforms
+    # where there is some logging prefix at each console line whereas on other platforms
+    # without prefixes the leading space is stripped.
     test_suite_start_pattern = re.compile(r"Running TESTSUITE (?P<suite_name>\S*)")
     test_suite_end_pattern = re.compile(
         r"TESTSUITE (?P<suite_name>\S*)\s+(?P<suite_status>succeeded|failed)"
@@ -746,7 +802,7 @@ class Test(Harness):
         r" .* duration = (\d*[.,]?\d*) seconds"
     )
     test_case_summary_pattern = re.compile(
-        r" - (PASS|FAIL|SKIP) - \[([^\.]*).(test_)?(\S*)\] duration = (\d*[.,]?\d*) seconds"
+        r".*- (PASS|FAIL|SKIP) - \[([^\.]*).(test_)?(\S*)\] duration = (\d*[.,]?\d*) seconds"
     )
 
 
@@ -793,7 +849,7 @@ def start_suite(self, suite_name, phase='TS_START'):
             logger.debug(f"{phase}: unexpected Ztest suite '{suite_name}' is "
                          f"not present among: {self.instance.testsuite.ztest_suite_names}")
         if suite_name in self.started_suites:
-            if self.started_suites[suite_name]['count'] > 0:
+            if self.started_suites[suite_name]['count'] > 0 and not self.expect_reboot:
                 # Either the suite restarts itself or unexpected state transition.
                 logger.warning(f"{phase}: already STARTED '{suite_name}':"
                                f"{self.started_suites[suite_name]}")
@@ -823,7 +879,7 @@ def end_suite(self, suite_name, phase='TS_END', suite_status=None):
 
     def start_case(self, tc_name, phase='TC_START'):
         if tc_name in self.started_cases:
-            if self.started_cases[tc_name]['count'] > 0:
+            if self.started_cases[tc_name]['count'] > 0 and not self.expect_reboot:
                 logger.warning(f"{phase}: already STARTED case "
                                f"'{tc_name}':{self.started_cases[tc_name]}")
             self.started_cases[tc_name]['count'] += 1
@@ -844,17 +900,16 @@ def end_case(self, tc_name, phase='TC_END'):
         elif phase != 'TS_SUM':
             logger.warning(f"{phase}: END case '{tc_name}' without START detected")
 
-
     def handle(self, line):
         testcase_match = None
         if self._match:
             self.testcase_output += line + "\n"
-
         if test_suite_start_match := re.search(self.test_suite_start_pattern, line):
             self.start_suite(test_suite_start_match.group("suite_name"))
         elif test_suite_end_match := re.search(self.test_suite_end_pattern, line):
             suite_name=test_suite_end_match.group("suite_name")
             self.end_suite(suite_name)
+            self.ztest = True
         elif testcase_match := re.search(self.test_case_start_pattern, line):
             tc_name = testcase_match.group(2)
             tc = self.get_testcase(tc_name, 'TC_START')
@@ -895,6 +950,11 @@ def handle(self, line):
             tc_name = test_case_summary_match.group(4)
             tc = self.get_testcase(tc_name, 'TS_SUM', suite_name)
             self.end_case(tc.name, 'TS_SUM')
+            if tc.status not in [TwisterStatus.NONE, TwisterStatus[matched_status]]:
+                # TestCase miss its END log entry, so its status is from the Suite summary.
+                logger.warning(
+                    f"TS_SUM: {tc.name} force status: {tc.status}->{TwisterStatus[matched_status]}"
+                )
             tc.status = TwisterStatus[matched_status]
             if tc.status == TwisterStatus.SKIP:
                 tc.reason = "ztest skip"
@@ -908,7 +968,7 @@ def handle(self, line):
         self.process_test(line)
 
         if not self.ztest and self.status != TwisterStatus.NONE:
-            logger.debug(f"not a ztest and no state for {self.id}")
+            logger.debug(f"{self.id} is not a Ztest, status:{self.status}")
             tc = self.instance.get_case_or_create(self.id)
             if self.status == TwisterStatus.PASS:
                 tc.status = TwisterStatus.PASS
@@ -955,6 +1015,142 @@ def build(self):
         logger.debug(f'Copying executable from {original_exe_path} to {new_exe_path}')
         shutil.copy(original_exe_path, new_exe_path)
 
+class Ctest(Harness):
+    def configure(self, instance: TestInstance):
+        super().configure(instance)
+        self.running_dir = instance.build_dir
+        self.report_file = os.path.join(self.running_dir, 'report.xml')
+        self.ctest_log_file_path = os.path.join(self.running_dir, 'twister_harness.log')
+        self._output = []
+
+    def ctest_run(self, timeout):
+        assert self.instance is not None
+        try:
+            cmd = self.generate_command()
+            self.run_command(cmd, timeout)
+        except Exception as err:
+            logger.error(str(err))
+            self.status = TwisterStatus.FAIL
+            self.instance.reason = str(err)
+        finally:
+            self.instance.record(self.recording)
+            self._update_test_status()
+
+    def generate_command(self):
+        config = self.instance.testsuite.harness_config
+        handler: Handler = self.instance.handler
+        ctest_args_yaml = config.get('ctest_args', []) if config else []
+        command = [
+            'ctest',
+            '--build-nocmake',
+            '--test-dir',
+            self.running_dir,
+            '--output-junit',
+            self.report_file,
+            '--output-log',
+            self.ctest_log_file_path,
+            '--output-on-failure',
+        ]
+        base_timeout = handler.get_test_timeout()
+        command.extend(['--timeout', str(base_timeout)])
+        command.extend(ctest_args_yaml)
+
+        if handler.options.ctest_args:
+            command.extend(handler.options.ctest_args)
+
+        return command
+
+    def run_command(self, cmd, timeout):
+        with subprocess.Popen(
+            cmd,
+            stdout=subprocess.PIPE,
+            stderr=subprocess.STDOUT,
+        ) as proc:
+            try:
+                reader_t = threading.Thread(target=self._output_reader, args=(proc,), daemon=True)
+                reader_t.start()
+                reader_t.join(timeout)
+                if reader_t.is_alive():
+                    terminate_process(proc)
+                    logger.warning('Timeout has occurred. Can be extended in testspec file. '
+                                   f'Currently set to {timeout} seconds.')
+                    self.instance.reason = 'Ctest timeout'
+                    self.status = TwisterStatus.FAIL
+                proc.wait(timeout)
+            except subprocess.TimeoutExpired:
+                self.status = TwisterStatus.FAIL
+                proc.kill()
+
+        if proc.returncode in (ExitCode.INTERRUPTED, ExitCode.USAGE_ERROR, ExitCode.INTERNAL_ERROR):
+            self.status = TwisterStatus.ERROR
+            self.instance.reason = f'Ctest error - return code {proc.returncode}'
+            with open(self.ctest_log_file_path, 'w') as log_file:
+                log_file.write(shlex.join(cmd) + '\n\n')
+                log_file.write('\n'.join(self._output))
+
+    def _output_reader(self, proc):
+        self._output = []
+        while proc.stdout.readable() and proc.poll() is None:
+            line = proc.stdout.readline().decode().strip()
+            if not line:
+                continue
+            self._output.append(line)
+            logger.debug(f'CTEST: {line}')
+            self.parse_record(line)
+        proc.communicate()
+
+    def _update_test_status(self):
+        if self.status == TwisterStatus.NONE:
+            self.instance.testcases = []
+            try:
+                self._parse_report_file(self.report_file)
+            except Exception as e:
+                logger.error(f'Error when parsing file {self.report_file}: {e}')
+                self.status = TwisterStatus.FAIL
+            finally:
+                if not self.instance.testcases:
+                    self.instance.init_cases()
+
+        self.instance.status = self.status if self.status != TwisterStatus.NONE else \
+                               TwisterStatus.FAIL
+        if self.instance.status in [TwisterStatus.ERROR, TwisterStatus.FAIL]:
+            self.instance.reason = self.instance.reason or 'Ctest failed'
+            self.instance.add_missing_case_status(TwisterStatus.BLOCK, self.instance.reason)
+
+    def _parse_report_file(self, report):
+        suite = junit.JUnitXml.fromfile(report)
+        if suite is None:
+            self.status = TwisterStatus.SKIP
+            self.instance.reason = 'No tests collected'
+            return
+
+        assert isinstance(suite, junit.TestSuite)
+
+        if suite.failures and suite.failures > 0:
+            self.status = TwisterStatus.FAIL
+            self.instance.reason = f"{suite.failures}/{suite.tests} ctest scenario(s) failed"
+        elif suite.errors and suite.errors > 0:
+            self.status = TwisterStatus.ERROR
+            self.instance.reason = 'Error during ctest execution'
+        elif suite.skipped and suite.skipped > 0:
+            self.status = TwisterStatus.SKIP
+        else:
+            self.status = TwisterStatus.PASS
+        self.instance.execution_time = suite.time
+
+        for case in suite:
+            tc = self.instance.add_testcase(f"{self.id}.{case.name}")
+            tc.duration = case.time
+            if any(isinstance(r, junit.Failure) for r in case.result):
+                tc.status = TwisterStatus.FAIL
+                tc.output = case.system_out
+            elif any(isinstance(r, junit.Error) for r in case.result):
+                tc.status = TwisterStatus.ERROR
+                tc.output = case.system_out
+            elif any(isinstance(r, junit.Skipped) for r in case.result):
+                tc.status = TwisterStatus.SKIP
+            else:
+                tc.status = TwisterStatus.PASS
 
 class HarnessImporter:
 
diff --git a/scripts/pylib/twister/twisterlib/jobserver.py b/scripts/pylib/twister/twisterlib/jobserver.py
index f66e6b08db0..cd08eabf0d2 100644
--- a/scripts/pylib/twister/twisterlib/jobserver.py
+++ b/scripts/pylib/twister/twisterlib/jobserver.py
@@ -14,7 +14,7 @@
 import sys
 
 logger = logging.getLogger('twister')
-logger.setLevel(logging.DEBUG)
+
 
 class JobHandle:
     """Small object to handle claim of a job."""
diff --git a/scripts/pylib/twister/twisterlib/log_helper.py b/scripts/pylib/twister/twisterlib/log_helper.py
index 3604f64ce1e..a92d4edacef 100644
--- a/scripts/pylib/twister/twisterlib/log_helper.py
+++ b/scripts/pylib/twister/twisterlib/log_helper.py
@@ -5,10 +5,13 @@
 Common code used when logging that is needed by multiple modules.
 '''
 
+import logging
+import os
 import platform
 import shlex
 
-_WINDOWS = (platform.system() == 'Windows')
+_WINDOWS = platform.system() == 'Windows'
+
 
 def log_command(logger, msg, args):
     '''Platform-independent helper for logging subprocess invocations.
@@ -20,8 +23,59 @@ def log_command(logger, msg, args):
     :param msg: message to associate with the command
     :param args: argument list as passed to subprocess module
     '''
+    logger = logging.getLogger("twister")
+    logger.setLevel(logging.DEBUG)
+
     msg = f'{msg}: %s'
     if _WINDOWS:
         logger.debug(msg, str(args))
     else:
         logger.debug(msg, shlex.join(args))
+
+def setup_logging(outdir, log_file, log_level, timestamps):
+    logger = logging.getLogger("twister")
+    logger.setLevel(logging.DEBUG)
+
+    # create file handler which logs even debug messages
+    if log_file:
+        file_handler = logging.FileHandler(log_file)
+    else:
+        file_handler = logging.FileHandler(os.path.join(outdir, "twister.log"))
+
+    file_handler.setLevel(logging.DEBUG)
+
+    # create console handler with a higher log level
+    console_handler = logging.StreamHandler()
+    console_handler.setLevel(getattr(logging, log_level))
+
+    # create formatter and add it to the handlers
+    if timestamps:
+        formatter = logging.Formatter("%(asctime)s - %(levelname)s - %(message)s")
+    else:
+        formatter = logging.Formatter("%(levelname)-7s - %(message)s")
+
+    formatter_file = logging.Formatter(
+        "%(asctime)s - %(name)s - %(levelname)s - %(message)s"
+    )
+    console_handler.setFormatter(formatter)
+    file_handler.setFormatter(formatter_file)
+
+    # add the handlers to logger
+    logger.addHandler(console_handler)
+    logger.addHandler(file_handler)
+
+
+def close_logging():
+    logger = logging.getLogger("twister")
+    handlers = logger.handlers[:]
+
+    for handler in handlers:
+        logger.removeHandler(handler)
+        handler.close()
+
+    loggers = [logging.getLogger(name) for name in logging.root.manager.loggerDict]
+    for logg in loggers:
+        handls = logg.handlers[:]
+        for handl in handls:
+            logg.removeHandler(handl)
+            handl.close()
diff --git a/scripts/pylib/twister/twisterlib/platform.py b/scripts/pylib/twister/twisterlib/platform.py
index 869680e251d..5c7ac81b102 100644
--- a/scripts/pylib/twister/twisterlib/platform.py
+++ b/scripts/pylib/twister/twisterlib/platform.py
@@ -9,13 +9,15 @@
 import logging
 import os
 import shutil
+from argparse import Namespace
+from itertools import groupby
 
+import list_boards
 import scl
 from twisterlib.constants import SUPPORTED_SIMS
 from twisterlib.environment import ZEPHYR_BASE
 
 logger = logging.getLogger('twister')
-logger.setLevel(logging.DEBUG)
 
 
 class Simulator:
@@ -28,6 +30,9 @@ def __init__(self, data: dict[str, str]):
         self.exec = data.get("exec")
 
     def is_runnable(self) -> bool:
+        if self.name == "simics":
+            return shutil.which(self.exec, path=os.environ.get("SIMICS_PROJECT")) is not None
+
         return not bool(self.exec) or bool(shutil.which(self.exec))
 
     def __str__(self):
@@ -70,6 +75,7 @@ def __init__(self):
         # if no flash size is specified by the board, take a default of 512K
         self.flash = 512
         self.supported = set()
+        self.binaries = []
 
         self.arch = None
         self.vendor = ""
@@ -84,69 +90,82 @@ def __init__(self):
         self.uart = ""
         self.resc = ""
 
-    def load(self, board, target, aliases, data):
+    def load(self, board, target, aliases, data, variant_data):
         """Load the platform data from the board data and target data
         board: the board object as per the zephyr build system
         target: the target name of the board as per the zephyr build system
         aliases: list of aliases for the target
-        data: the data from the twister.yaml file for the target
+        data: the default data from the twister.yaml file for the board
+        variant_data: the target-specific data to replace the default data
         """
         self.name = target
         self.aliases = aliases
 
         self.normalized_name = self.name.replace("/", "_")
-        self.sysbuild = data.get("sysbuild", self.sysbuild)
-        self.twister = data.get("twister", self.twister)
+        self.sysbuild = variant_data.get("sysbuild", data.get("sysbuild", self.sysbuild))
+        self.twister = variant_data.get("twister", data.get("twister", self.twister))
 
         # if no RAM size is specified by the board, take a default of 128K
-        self.ram = data.get("ram", self.ram)
+        self.ram = variant_data.get("ram", data.get("ram", self.ram))
         # if no flash size is specified by the board, take a default of 512K
-        self.flash = data.get("flash", self.flash)
+        self.flash = variant_data.get("flash", data.get("flash", self.flash))
 
         testing = data.get("testing", {})
-        self.timeout_multiplier = testing.get("timeout_multiplier", self.timeout_multiplier)
-        self.ignore_tags = testing.get("ignore_tags", self.ignore_tags)
-        self.only_tags = testing.get("only_tags", self.only_tags)
+        self.ignore_tags = testing.get("ignore_tags", [])
+        self.only_tags = testing.get("only_tags", [])
         self.default = testing.get("default", self.default)
         self.binaries = testing.get("binaries", [])
+        self.timeout_multiplier = testing.get("timeout_multiplier", self.timeout_multiplier)
+
+        # testing data for variant
+        testing_var = variant_data.get("testing", data.get("testing", {}))
+        self.timeout_multiplier = testing_var.get("timeout_multiplier", self.timeout_multiplier)
+        self.ignore_tags = testing_var.get("ignore_tags", self.ignore_tags)
+        self.only_tags = testing_var.get("only_tags", self.only_tags)
+        self.default = testing_var.get("default", self.default)
+        self.binaries = testing_var.get("binaries", self.binaries)
         renode = testing.get("renode", {})
         self.uart = renode.get("uart", "")
         self.resc = renode.get("resc", "")
+
         self.supported = set()
-        for supp_feature in data.get("supported", []):
+        for supp_feature in variant_data.get("supported", data.get("supported", [])):
             for item in supp_feature.split(":"):
                 self.supported.add(item)
 
-        self.arch = data.get('arch', self.arch)
+        self.arch = variant_data.get('arch', data.get('arch', self.arch))
         self.vendor = board.vendor
-        self.tier = data.get("tier", self.tier)
-        self.type = data.get('type', self.type)
+        self.tier = variant_data.get("tier", data.get("tier", self.tier))
+        self.type = variant_data.get('type', data.get('type', self.type))
 
         self.simulators = [
-            Simulator(data) for data in data.get('simulation', self.simulators)
+            Simulator(data) for data in variant_data.get(
+                'simulation',
+                data.get('simulation', self.simulators)
+            )
         ]
         default_sim = self.simulator_by_name(None)
         if default_sim:
             self.simulation = default_sim.name
 
-        self.supported_toolchains = data.get("toolchain", [])
+        self.supported_toolchains = variant_data.get("toolchain", data.get("toolchain", []))
         if self.supported_toolchains is None:
             self.supported_toolchains = []
 
         support_toolchain_variants = {
           # we don't provide defaults for 'arc' intentionally: some targets can't be built with GNU
-          # toolchain ("zephyr", "cross-compile", "xtools" options) and for some targets we haven't
-          # provided MWDT compiler / linker options in corresponding SoC file in Zephyr, so these
-          # targets can't be built with ARC MWDT toolchain ("arcmwdt" option) by Zephyr build system
-          # Instead for 'arc' we rely on 'toolchain' option in board yaml configuration.
-          "arm": ["zephyr", "gnuarmemb", "xtools", "armclang", "llvm"],
+          # toolchain ("zephyr", "cross-compile" options) and for some targets we haven't provided
+          # MWDT compiler / linker options in corresponding SoC file in Zephyr, so these targets
+          # can't be built with ARC MWDT toolchain ("arcmwdt" option) by Zephyr build system Instead
+          # for 'arc' we rely on 'toolchain' option in board yaml configuration.
+          "arm": ["zephyr", "gnuarmemb", "armclang", "llvm"],
           "arm64": ["zephyr", "cross-compile"],
-          "mips": ["zephyr", "xtools"],
-          "nios2": ["zephyr", "xtools"],
+          "mips": ["zephyr"],
+          "nios2": ["zephyr"],
           "riscv": ["zephyr", "cross-compile"],
           "posix": ["host", "llvm"],
-          "sparc": ["zephyr", "xtools"],
-          "x86": ["zephyr", "xtools", "llvm"],
+          "sparc": ["zephyr"],
+          "x86": ["zephyr", "llvm"],
           # Xtensa is not listed on purpose, since there is no single toolchain
           # that is supported on all board targets for xtensa.
         }
@@ -156,7 +175,7 @@ def load(self, board, target, aliases, data):
                 if toolchain not in self.supported_toolchains:
                     self.supported_toolchains.append(toolchain)
 
-        self.env = data.get("env", [])
+        self.env = variant_data.get("env", data.get("env", []))
         self.env_satisfied = True
         for env in self.env:
             if not os.environ.get(env, None):
@@ -170,3 +189,116 @@ def simulator_by_name(self, sim_name: str | None) -> Simulator | None:
 
     def __repr__(self):
         return f"<{self.name} on {self.arch}>"
+
+
+def generate_platforms(board_roots, soc_roots, arch_roots):
+    """Initialize and yield all Platform instances.
+
+    Using the provided board/soc/arch roots, determine the available
+    platform names and load the test platform description files.
+
+    An exception is raised if not all platform files are valid YAML,
+    or if not all platform names are unique.
+    """
+    alias2target = {}
+    target2board = {}
+    target2data = {}
+    dir2data = {}
+    legacy_files = []
+
+    lb_args = Namespace(board_roots=board_roots, soc_roots=soc_roots, arch_roots=arch_roots,
+                        board=None, board_dir=None)
+
+    for board in list_boards.find_v2_boards(lb_args).values():
+        for board_dir in board.directories:
+            if board_dir in dir2data:
+                # don't load the same board data twice
+                continue
+            file = board_dir / "twister.yaml"
+            if file.is_file():
+                data = scl.yaml_load_verify(file, Platform.platform_schema)
+            else:
+                data = None
+            dir2data[board_dir] = data
+
+            legacy_files.extend(
+                file for file in board_dir.glob("*.yaml") if file.name != "twister.yaml"
+            )
+
+        for qual in list_boards.board_v2_qualifiers(board):
+            if board.revisions:
+                for rev in board.revisions:
+                    if rev.name:
+                        target = f"{board.name}@{rev.name}/{qual}"
+                        alias2target[target] = target
+                        if rev.name == board.revision_default:
+                            alias2target[f"{board.name}/{qual}"] = target
+                        if '/' not in qual and len(board.socs) == 1:
+                            if rev.name == board.revision_default:
+                                alias2target[f"{board.name}"] = target
+                            alias2target[f"{board.name}@{rev.name}"] = target
+                    else:
+                        target = f"{board.name}/{qual}"
+                        alias2target[target] = target
+                        if '/' not in qual and len(board.socs) == 1 \
+                                and rev.name == board.revision_default:
+                            alias2target[f"{board.name}"] = target
+
+                    target2board[target] = board
+            else:
+                target = f"{board.name}/{qual}"
+                alias2target[target] = target
+                if '/' not in qual and len(board.socs) == 1:
+                    alias2target[board.name] = target
+                target2board[target] = board
+
+    for board_dir, data in dir2data.items():
+        if data is None:
+            continue
+        # Separate the default and variant information in the loaded board data.
+        # The default (top-level) data can be shared by multiple board targets;
+        # it will be overlaid by the variant data (if present) for each target.
+        variant_data = data.pop("variants", {})
+        for variant in variant_data:
+            target = alias2target.get(variant)
+            if target is None:
+                continue
+            if target in target2data:
+                logger.error(f"Duplicate platform {target} in {board_dir}")
+                raise Exception(f"Duplicate platform identifier {target} found")
+            target2data[target] = variant_data[variant]
+
+    # note: this inverse mapping will only be used for loading legacy files
+    target2aliases = {}
+
+    for target, aliases in groupby(alias2target, alias2target.get):
+        aliases = list(aliases)
+        board = target2board[target]
+
+        # Default board data always comes from the primary 'board.dir'.
+        # Other 'board.directories' can only supply variant data.
+        data = dir2data[board.dir]
+        if data is not None:
+            variant_data = target2data.get(target, {})
+
+            platform = Platform()
+            platform.load(board, target, aliases, data, variant_data)
+            yield platform
+
+        target2aliases[target] = aliases
+
+    for file in legacy_files:
+        data = scl.yaml_load_verify(file, Platform.platform_schema)
+        target = alias2target.get(data.get("identifier"))
+        if target is None:
+            continue
+
+        board = target2board[target]
+        if dir2data[board.dir] is not None:
+            # all targets are already loaded for this board
+            logger.error(f"Duplicate platform {target} in {file.parent}")
+            raise Exception(f"Duplicate platform identifier {target} found")
+
+        platform = Platform()
+        platform.load(board, target, target2aliases[target], data, variant_data={})
+        yield platform
diff --git a/scripts/pylib/twister/twisterlib/py.typed b/scripts/pylib/twister/twisterlib/py.typed
new file mode 100644
index 00000000000..e69de29bb2d
diff --git a/scripts/pylib/twister/twisterlib/reports.py b/scripts/pylib/twister/twisterlib/reports.py
index f28fbab991a..c9eccbf9cae 100644
--- a/scripts/pylib/twister/twisterlib/reports.py
+++ b/scripts/pylib/twister/twisterlib/reports.py
@@ -11,13 +11,12 @@
 import xml.etree.ElementTree as ET
 from datetime import datetime
 from enum import Enum
-from pathlib import Path, PosixPath
+from pathlib import Path
 
 from colorama import Fore
 from twisterlib.statuses import TwisterStatus
 
 logger = logging.getLogger('twister')
-logger.setLevel(logging.DEBUG)
 
 
 class ReportStatus(str, Enum):
@@ -29,6 +28,13 @@ def __str__(self):
     SKIP = 'skipped'
 
 
+class ReportingJSONEncoder(json.JSONEncoder):
+    def default(self, obj):
+        if isinstance(obj, Path):
+            return str(obj)
+        return super().default(obj)
+
+
 class Reporting:
 
     json_filters = {
@@ -51,6 +57,7 @@ def __init__(self, plan, env) -> None:
         self.outdir = os.path.abspath(env.options.outdir)
         self.instance_fail_count = plan.instance_fail_count
         self.footprint = None
+        self.coverage_status = None
 
 
     @staticmethod
@@ -294,10 +301,6 @@ def json_report(self, filename, version="NA", platform=None, filters=None):
         else:
             report_options = self.env.non_default_options()
 
-        # Resolve known JSON serialization problems.
-        for k,v in report_options.items():
-            report_options[k] = str(v) if type(v) in [PosixPath] else v
-
         report = {}
         report["environment"] = {"os": os.name,
                                  "zephyr_version": version,
@@ -368,7 +371,6 @@ def json_report(self, filename, version="NA", platform=None, filters=None):
                 suite["available_rom"] = available_rom
             if instance.status in [TwisterStatus.ERROR, TwisterStatus.FAIL]:
                 suite['status'] = instance.status
-                suite["reason"] = instance.reason
                 # FIXME
                 if os.path.exists(pytest_log):
                     suite["log"] = self.process_log(pytest_log)
@@ -378,6 +380,11 @@ def json_report(self, filename, version="NA", platform=None, filters=None):
                     suite["log"] = self.process_log(device_log)
                 else:
                     suite["log"] = self.process_log(build_log)
+
+                suite["reason"] = self.get_detailed_reason(instance.reason, suite["log"])
+                # update the reason to get more details also in other reports (e.g. junit)
+                # where build log is not available
+                instance.reason = suite["reason"]
             elif instance.status == TwisterStatus.FILTER:
                 suite["status"] = TwisterStatus.FILTER
                 suite["reason"] = instance.reason
@@ -483,7 +490,7 @@ def json_report(self, filename, version="NA", platform=None, filters=None):
 
         report["testsuites"] = suites
         with open(filename, 'w') as json_file:
-            json.dump(report, json_file, indent=4, separators=(',',':'))
+            json.dump(report, json_file, indent=4, separators=(',',':'), cls=ReportingJSONEncoder)
 
 
     def compare_metrics(self, filename):
@@ -625,19 +632,12 @@ def synopsis(self):
             )
             logger.info("-+" * 40)
 
-    def summary(self, results, ignore_unrecognized_sections, duration):
+    def summary(self, results, duration):
         failed = 0
         run = 0
         for instance in self.instances.values():
             if instance.status == TwisterStatus.FAIL:
                 failed += 1
-            elif not ignore_unrecognized_sections and instance.metrics.get("unrecognized"):
-                logger.error(
-                    f"{Fore.RED}FAILED{Fore.RESET}:"
-                    f" {instance.name} has unrecognized binary sections:"
-                    f" {instance.metrics.get('unrecognized', [])!s}"
-                )
-                failed += 1
 
             # FIXME: need a better way to identify executed tests
             handler_time = instance.metrics.get('handler_time', 0)
@@ -794,3 +794,55 @@ def target_report(self, json_file, outdir, suffix):
                 self.json_report(json_platform_file + "_footprint.json",
                                  version=self.env.version, platform=platform.name,
                                  filters=self.json_filters['footprint.json'])
+
+    def get_detailed_reason(self, reason: str, log: str) -> str:
+        if reason == 'CMake build failure':
+            if error_key := self._parse_cmake_build_failure(log):
+                return f"{reason} - {error_key}"
+        elif reason == 'Build failure':  # noqa SIM102
+            if error_key := self._parse_build_failure(log):
+                return f"{reason} - {error_key}"
+        return reason
+
+    @staticmethod
+    def _parse_cmake_build_failure(log: str) -> str | None:
+        last_warning = 'no warning found'
+        lines = log.splitlines()
+        for i, line in enumerate(lines):
+            if "warning: " in line:
+                last_warning = line
+            elif "devicetree error: " in line:
+                return "devicetree error"
+            elif "fatal error: " in line:
+                return line[line.index('fatal error: ') :].strip()
+            elif "error: " in line:  # error: Aborting due to Kconfig warnings
+                if "undefined symbol" in last_warning:
+                    return last_warning[last_warning.index('undefined symbol') :].strip()
+                return last_warning
+            elif "CMake Error at" in line:
+                for next_line in lines[i + 1 :]:
+                    if next_line.strip():
+                        return line + ' ' + next_line
+                return line
+        return None
+
+    @staticmethod
+    def _parse_build_failure(log: str) -> str | None:
+        last_warning = ''
+        lines = log.splitlines()
+        for i, line in enumerate(lines):
+            if "undefined reference" in line:
+                return line[line.index('undefined reference') :].strip()
+            elif "error: ld returned" in line:
+                if last_warning:
+                    return last_warning
+                elif "overflowed by" in lines[i - 1]:
+                    return "ld.bfd: region overflowed"
+                elif "ld.bfd: warning: " in lines[i - 1]:
+                    return "ld.bfd:" + lines[i - 1].split("ld.bfd:", 1)[-1]
+                return line
+            elif "error: " in line:
+                return line[line.index('error: ') :].strip()
+            elif ": in function " in line:
+                last_warning = line[line.index('in function') :].strip()
+        return None
diff --git a/scripts/pylib/twister/twisterlib/runner.py b/scripts/pylib/twister/twisterlib/runner.py
index 94629576859..54524757e7c 100644
--- a/scripts/pylib/twister/twisterlib/runner.py
+++ b/scripts/pylib/twister/twisterlib/runner.py
@@ -1,6 +1,6 @@
 # vim: set syntax=python ts=4 :
 #
-# Copyright (c) 2018-2024 Intel Corporation
+# Copyright (c) 2018-2025 Intel Corporation
 # Copyright 2022 NXP
 # SPDX-License-Identifier: Apache-2.0
 
@@ -29,6 +29,7 @@
 from twisterlib.cmakecache import CMakeCache
 from twisterlib.environment import canonical_zephyr_base
 from twisterlib.error import BuildError, ConfigurationError, StatusAttributeError
+from twisterlib.log_helper import setup_logging
 from twisterlib.statuses import TwisterStatus
 
 if version.parse(elftools.__version__) < version.parse('0.24'):
@@ -42,8 +43,9 @@
 
 sys.path.insert(0, os.path.join(ZEPHYR_BASE, "scripts/pylib/build_helpers"))
 from domains import Domains
+from twisterlib.coverage import run_coverage_instance
 from twisterlib.environment import TwisterEnv
-from twisterlib.harness import HarnessImporter, Pytest
+from twisterlib.harness import Ctest, HarnessImporter, Pytest
 from twisterlib.log_helper import log_command
 from twisterlib.platform import Platform
 from twisterlib.testinstance import TestInstance
@@ -59,7 +61,6 @@
 from anytree import Node, RenderTree
 
 logger = logging.getLogger('twister')
-logger.setLevel(logging.DEBUG)
 
 
 class ExecutionCounter:
@@ -598,10 +599,13 @@ def run_build(self, args=None):
                     log.write(log_msg)
 
             if log_msg:
-                overflow_found = re.findall(
-                    "region `(FLASH|ROM|RAM|ICCM|DCCM|SRAM|dram\\d_\\d_seg)' overflowed by",
-                    log_msg
+                pattern = (
+                    r"region `(FLASH|ROM|RAM|ICCM|DCCM|SRAM|"
+                    r"dram\d_\d_seg|iram\d_\d_seg)' "
+                    "overflowed by"
                 )
+                overflow_found = re.findall(pattern, log_msg)
+
                 imgtool_overflow_found = re.findall(
                     r"Error: Image size \(.*\) \+ trailer \(.*\) exceeds requested size",
                     log_msg
@@ -974,7 +978,9 @@ def process(self, pipeline, done, message, lock, results):
         additionals = {}
 
         op = message.get('op')
-
+        options = self.options
+        if not logger.handlers:
+            setup_logging(options.outdir, options.log_file, options.log_level, options.timestamps)
         self.instance.setup_handler(self.env)
 
         if op == "filter":
@@ -1127,7 +1133,7 @@ def process(self, pipeline, done, message, lock, results):
                 self.instance.handler.thread = None
                 self.instance.handler.duts = None
 
-                next_op = 'report'
+                next_op = "coverage" if self.options.coverage else "report"
                 additionals = {
                     "status": self.instance.status,
                     "reason": self.instance.reason
@@ -1143,6 +1149,28 @@ def process(self, pipeline, done, message, lock, results):
             finally:
                 self._add_to_pipeline(pipeline, next_op, additionals)
 
+        # Run per-instance code coverage
+        elif op == "coverage":
+            try:
+                logger.debug(f"Run coverage for '{self.instance.name}'")
+                self.instance.coverage_status, self.instance.coverage = \
+                        run_coverage_instance(self.options, self.instance)
+                next_op = 'report'
+                additionals = {
+                    "status": self.instance.status,
+                    "reason": self.instance.reason
+                }
+            except StatusAttributeError as sae:
+                logger.error(str(sae))
+                self.instance.status = TwisterStatus.ERROR
+                reason = f"Incorrect status assignment on {op}"
+                self.instance.reason = reason
+                self.instance.add_missing_case_status(TwisterStatus.BLOCK, reason)
+                next_op = 'report'
+                additionals = {}
+            finally:
+                self._add_to_pipeline(pipeline, next_op, additionals)
+
         # Report results and output progress to screen
         elif op == "report":
             try:
@@ -1181,7 +1209,7 @@ def process(self, pipeline, done, message, lock, results):
                     mode == "passed"
                     or (mode == "all" and self.instance.reason != "CMake build failure")
                 ):
-                    self.cleanup_artifacts()
+                    self.cleanup_artifacts(self.options.keep_artifacts)
             except StatusAttributeError as sae:
                 logger.error(str(sae))
                 self.instance.status = TwisterStatus.ERROR
@@ -1287,6 +1315,8 @@ def cleanup_artifacts(self, additional_keep: list[str] = None):
             'recording.csv',
             'rom.json',
             'ram.json',
+            'build_info.yml',
+            'zephyr/zephyr.dts',
             # below ones are needed to make --test-only work as well
             'Makefile',
             'CMakeCache.txt',
@@ -1320,7 +1350,7 @@ def cleanup_device_testing_artifacts(self):
         files_to_keep = self._get_binaries()
         files_to_keep.append(os.path.join('zephyr', 'runners.yaml'))
 
-        if self.instance.sysbuild:
+        if self.instance.sysbuild and self.instance.domains:
             files_to_keep.append('domains.yaml')
             for domain in self.instance.domains.get_domains():
                 files_to_keep += self._get_artifact_allow_list_for_domain(domain.name)
@@ -1360,7 +1390,7 @@ def _get_binaries(self) -> list[str]:
         # Get binaries for a single-domain build
         binaries += self._get_binaries_from_runners()
         # Get binaries in the case of a multiple-domain build
-        if self.instance.sysbuild:
+        if self.instance.sysbuild and self.instance.domains:
             for domain in self.instance.domains.get_domains():
                 binaries += self._get_binaries_from_runners(domain.name)
 
@@ -1636,8 +1666,8 @@ def cmake_assemble_args(extra_args, handler, extra_conf_files, extra_overlay_con
                             extra_dtc_overlay_files, cmake_extra_args,
                             build_dir):
         # Retain quotes around config options
-        config_options = [arg for arg in extra_args if arg.startswith("CONFIG_")]
-        args = [arg for arg in extra_args if not arg.startswith("CONFIG_")]
+        config_options = [arg for arg in extra_args if arg.startswith(("CONFIG_", "SB_CONFIG_"))]
+        args = [arg for arg in extra_args if not arg.startswith(("CONFIG_", "SB_CONFIG_"))]
 
         args_expanded = ["-D{}".format(a.replace('"', '\"')) for a in config_options]
 
@@ -1727,8 +1757,8 @@ def run(self):
 
             if(self.options.seed is not None and instance.platform.name.startswith("native_")):
                 self.parse_generated()
-                if('CONFIG_FAKE_ENTROPY_NATIVE_POSIX' in self.defconfig and
-                    self.defconfig['CONFIG_FAKE_ENTROPY_NATIVE_POSIX'] == 'y'):
+                if('CONFIG_FAKE_ENTROPY_NATIVE_SIM' in self.defconfig and
+                    self.defconfig['CONFIG_FAKE_ENTROPY_NATIVE_SIM'] == 'y'):
                     instance.handler.seed = self.options.seed
 
             if self.options.extra_test_args and instance.platform.arch == "posix":
@@ -1745,6 +1775,8 @@ def run(self):
             #
             if isinstance(harness, Pytest):
                 harness.pytest_run(instance.handler.get_test_timeout())
+            elif isinstance(harness, Ctest):
+                harness.ctest_run(instance.handler.get_test_timeout())
             else:
                 instance.handler.handle(harness)
 
@@ -1761,7 +1793,6 @@ def gather_metrics(self, instance: TestInstance):
             instance.metrics["used_rom"] = 0
             instance.metrics["available_rom"] = 0
             instance.metrics["available_ram"] = 0
-            instance.metrics["unrecognized"] = []
         return build_result
 
     @staticmethod
@@ -1777,13 +1808,11 @@ def calc_size(instance: TestInstance, from_buildlog: bool):
                 instance.metrics["used_rom"] = size_calc.get_used_rom()
                 instance.metrics["available_rom"] = size_calc.get_available_rom()
                 instance.metrics["available_ram"] = size_calc.get_available_ram()
-                instance.metrics["unrecognized"] = size_calc.unrecognized_sections()
             else:
                 instance.metrics["used_ram"] = 0
                 instance.metrics["used_rom"] = 0
                 instance.metrics["available_rom"] = 0
                 instance.metrics["available_ram"] = 0
-                instance.metrics["unrecognized"] = []
             instance.metrics["handler_time"] = instance.execution_time
 
 class TwisterRunner:
@@ -1844,8 +1873,8 @@ def run(self):
                 self.results.done = self.results.total - self.results.failed
                 self.results.failed = 0
                 if self.options.retry_build_errors:
-                    self.results.error = 0
                     self.results.done -= self.results.error
+                    self.results.error = 0
             else:
                 self.results.done = self.results.filtered_static
 
@@ -1859,7 +1888,6 @@ def run(self):
                 else:
                     inst.metrics.update(self.instances[inst.name].metrics)
                     inst.metrics["handler_time"] = inst.execution_time
-                    inst.metrics["unrecognized"] = []
                     self.instances[inst.name] = inst
 
             print("")
@@ -1989,7 +2017,7 @@ def pipeline_mgr(self, pipeline, done_queue, lock, results):
                             break
                 return True
         except Exception as e:
-            logger.error(f"General exception: {e}")
+            logger.error(f"General exception: {e}\n{traceback.format_exc()}")
             sys.exit(1)
 
     def execute(self, pipeline, done):
diff --git a/scripts/pylib/twister/twisterlib/size_calc.py b/scripts/pylib/twister/twisterlib/size_calc.py
index 8034dca44ee..a3f1969b122 100644
--- a/scripts/pylib/twister/twisterlib/size_calc.py
+++ b/scripts/pylib/twister/twisterlib/size_calc.py
@@ -13,7 +13,7 @@
 from twisterlib.error import TwisterRuntimeError
 
 logger = logging.getLogger('twister')
-logger.setLevel(logging.DEBUG)
+
 
 class SizeCalculator:
     alloc_sections = [
@@ -154,17 +154,6 @@ def get_used_rom(self):
         """
         return self.used_rom
 
-    def unrecognized_sections(self):
-        """Get a list of sections inside the binary that weren't recognized
-
-        @return list of unrecognized section names
-        """
-        slist = []
-        for v in self.sections:
-            if not v["recognized"]:
-                slist.append(v["name"])
-        return slist
-
     def get_available_ram(self) -> int:
         """Get the total available RAM.
 
@@ -251,7 +240,6 @@ def _get_info_elf_sections(self) -> None:
 
             # Add section to memory use totals (for both non-XIP and XIP scenarios)
             # Unrecognized section names are not included in the calculations.
-            recognized = True
 
             # If build.log file exists, check errors (unrecognized sections
             # in ELF file).
@@ -262,8 +250,6 @@ def _get_info_elf_sections(self) -> None:
                     continue
                 else:
                     stype = "unknown"
-                    if name not in self.extra_sections:
-                        recognized = False
             else:
                 if name in SizeCalculator.alloc_sections:
                     self.used_ram += size
@@ -279,12 +265,10 @@ def _get_info_elf_sections(self) -> None:
                     stype = "ro"
                 else:
                     stype = "unknown"
-                    if name not in self.extra_sections:
-                        recognized = False
 
             self.sections.append({"name": name, "load_addr": load_addr,
                                   "size": size, "virt_addr": virt_addr,
-                                  "type": stype, "recognized": recognized})
+                                  "type": stype})
 
     def _analyze_elf_file(self) -> None:
         self._check_elf_file()
diff --git a/scripts/pylib/twister/twisterlib/testinstance.py b/scripts/pylib/twister/twisterlib/testinstance.py
index 49d845d5929..b205aa895fc 100644
--- a/scripts/pylib/twister/twisterlib/testinstance.py
+++ b/scripts/pylib/twister/twisterlib/testinstance.py
@@ -1,6 +1,6 @@
 # vim: set syntax=python ts=4 :
 #
-# Copyright (c) 2018-2024 Intel Corporation
+# Copyright (c) 2018-2025 Intel Corporation
 # Copyright 2022 NXP
 # Copyright (c) 2024 Arm Limited (or its affiliates). All rights reserved.
 #
@@ -36,7 +36,7 @@
 from twisterlib.testsuite import TestCase, TestSuite
 
 logger = logging.getLogger('twister')
-logger.setLevel(logging.DEBUG)
+
 
 class TestInstance:
     """Class representing the execution of a particular TestSuite on a platform
@@ -59,6 +59,8 @@ def __init__(self, testsuite, platform, toolchain, outdir):
         self.metrics = dict()
         self.handler = None
         self.recording = None
+        self.coverage = None
+        self.coverage_status = None
         self.outdir = outdir
         self.execution_time = 0
         self.build_time = 0
@@ -105,9 +107,12 @@ def record(self, recording, fname_csv="recording.csv"):
                 self.recording.extend(recording)
 
             filename = os.path.join(self.build_dir, fname_csv)
+            fieldnames = set()
+            for r in self.recording:
+                fieldnames.update(r)
             with open(filename, 'w') as csvfile:
                 cw = csv.DictWriter(csvfile,
-                                    fieldnames = self.recording[0].keys(),
+                                    fieldnames = sorted(list(fieldnames)),
                                     lineterminator = os.linesep,
                                     quoting = csv.QUOTE_NONNUMERIC)
                 cw.writeheader()
@@ -147,7 +152,7 @@ def _get_run_id(self):
             with open(run_id_file) as fp:
                 run_id = fp.read()
         else:
-            hash_object = hashlib.md5(self.name.encode())
+            hash_object = hashlib.md5(self.name.encode(), usedforsecurity=False)
             random_str = f"{random.getrandbits(64)}".encode()
             hash_object.update(random_str)
             run_id = hash_object.hexdigest()
@@ -213,7 +218,17 @@ def get_case_or_create(self, name):
     def testsuite_runnable(testsuite, fixtures):
         can_run = False
         # console harness allows us to run the test and capture data.
-        if testsuite.harness in [ 'console', 'ztest', 'pytest', 'test', 'gtest', 'robot']:
+        if testsuite.harness in [
+            'console',
+            'ztest',
+            'pytest',
+            'power',
+            'test',
+            'gtest',
+            'robot',
+            'ctest',
+            'shell'
+            ]:
             can_run = True
             # if we have a fixture that is also being supplied on the
             # command-line, then we need to run the test, not just build it.
@@ -256,6 +271,8 @@ def setup_handler(self, env: TwisterEnv):
             handler.ready = True
         else:
             handler = Handler(self, "", *common_args)
+            if self.testsuite.harness == "ctest":
+                handler.ready = True
 
         self.handler = handler
 
@@ -291,12 +308,13 @@ def check_runnable(self,
 
         target_ready = bool(self.testsuite.type == "unit" or \
                             self.platform.type == "native" or \
+                            self.testsuite.harness == "ctest" or \
                             (simulator and simulator.name in SUPPORTED_SIMS and \
                              simulator.name not in self.testsuite.simulation_exclude) or \
                             device_testing)
 
         # check if test is runnable in pytest
-        if self.testsuite.harness == 'pytest':
+        if self.testsuite.harness in ['pytest', 'shell', 'power']:
             target_ready = bool(
                 filter == 'runnable' or simulator and simulator.name in SUPPORTED_SIMS_IN_PYTEST
             )
@@ -311,7 +329,7 @@ def check_runnable(self,
 
         if hardware_map:
             for h in hardware_map.duts:
-                if (h.platform == self.platform.name and
+                if (h.platform in self.platform.aliases and
                         self.testsuite_runnable(self.testsuite, h.fixtures)):
                     testsuite_runnable = True
                     break
diff --git a/scripts/pylib/twister/twisterlib/testplan.py b/scripts/pylib/twister/twisterlib/testplan.py
index be232e61f78..12c10ee1b14 100755
--- a/scripts/pylib/twister/twisterlib/testplan.py
+++ b/scripts/pylib/twister/twisterlib/testplan.py
@@ -27,11 +27,10 @@
 except ImportError:
     print("Install the anytree module to use the --test-tree option")
 
-import list_boards
 import scl
 from twisterlib.config_parser import TwisterConfigParser
 from twisterlib.error import TwisterRuntimeError
-from twisterlib.platform import Platform
+from twisterlib.platform import Platform, generate_platforms
 from twisterlib.quarantine import Quarantine
 from twisterlib.statuses import TwisterStatus
 from twisterlib.testinstance import TestInstance
@@ -39,7 +38,6 @@
 from zephyr_module import parse_modules
 
 logger = logging.getLogger('twister')
-logger.setLevel(logging.DEBUG)
 
 ZEPHYR_BASE = os.getenv("ZEPHYR_BASE")
 if not ZEPHYR_BASE:
@@ -441,125 +439,16 @@ def add_configurations(self):
         # Note, internally in twister a board root includes the `boards` folder
         # but in Zephyr build system, the board root is without the `boards` in folder path.
         board_roots = [Path(os.path.dirname(root)) for root in self.env.board_roots]
-        lb_args = Namespace(arch_roots=self.env.arch_roots, soc_roots=self.env.soc_roots,
-                            board_roots=board_roots, board=None, board_dir=None)
+        soc_roots = self.env.soc_roots
+        arch_roots = self.env.arch_roots
 
-        known_boards = list_boards.find_v2_boards(lb_args)
         platform_config = self.test_config.get('platforms', {})
 
-        alias2target = {}
-        target2board = {}
-        target2data = {}
-        dir2data = {}
-        legacy_files = []
-
-        # helper function to initialize and add platforms
-        def init_and_add_platforms(data, board, target, aliases, src_dir):
-            platform = Platform()
-            platform.load(board, target, aliases, data)
-            if platform.name in [p.name for p in self.platforms]:
-                logger.error(f"Duplicate platform {platform.name} in {src_dir}")
-                raise Exception(f"Duplicate platform identifier {platform.name} found")
+        for platform in generate_platforms(board_roots, soc_roots, arch_roots):
             if not platform.twister:
-                return
-            self.platforms.append(platform)
-
-        for board in known_boards.values():
-            for board_dir in board.directories:
-                if board_dir in dir2data:
-                    # don't load the same board data twice
-                    continue
-                legacy_files.extend(
-                    file for file in board_dir.glob("*.yaml") if file.name != "twister.yaml"
-                )
-                data = None
-                file = board_dir / "twister.yaml"
-                if file.is_file():
-                    try:
-                        data = scl.yaml_load_verify(file, Platform.platform_schema)
-                    except Exception as e:
-                        logger.error(f"Error loading {file}: {e!r}")
-                        self.load_errors += 1
-                dir2data[board_dir] = data
-
-
-
-            for qual in list_boards.board_v2_qualifiers(board):
-
-                if board.revisions:
-                    for rev in board.revisions:
-                        if rev.name:
-                            target = f"{board.name}@{rev.name}/{qual}"
-                            alias2target[target] = target
-                            if rev.name == board.revision_default:
-                                alias2target[f"{board.name}/{qual}"] = target
-                            if '/' not in qual and len(board.socs) == 1:
-                                if rev.name == board.revision_default:
-                                    alias2target[f"{board.name}"] = target
-                                alias2target[f"{board.name}@{rev.name}"] = target
-                        else:
-                            target = f"{board.name}/{qual}"
-                            alias2target[target] = target
-                            if '/' not in qual and len(board.socs) == 1 \
-                                    and rev.name == board.revision_default:
-                                alias2target[f"{board.name}"] = target
-
-                        target2board[target] = board
-                else:
-                    target = f"{board.name}/{qual}"
-                    alias2target[target] = target
-                    if '/' not in qual and len(board.socs) == 1:
-                        alias2target[board.name] = target
-                    target2board[target] = board
-
-        for board_dir, data in dir2data.items():
-            if data is None:
-                continue
-            # Separate the default and variant information in the loaded board data.
-            # The default (top-level) data can be shared by multiple board targets;
-            # it will be overlaid by the variant data (if present) for each target.
-            variant_data = data.pop("variants", {})
-            for variant in variant_data:
-                target = alias2target.get(variant)
-                if target is None:
-                    continue
-                if target in target2data:
-                    logger.error(f"Duplicate platform {target} in {board_dir}")
-                    raise Exception(f"Duplicate platform identifier {target} found")
-                target2data[target] = variant_data[variant]
-
-        # note: this inverse mapping will only be used for loading legacy files
-        target2aliases = {}
-
-        for target, aliases in itertools.groupby(alias2target, alias2target.get):
-            aliases = list(aliases)
-            board = target2board[target]
-
-            # Default board data always comes from the primary 'board.dir'.
-            # Other 'board.directories' can only supply variant data.
-            data = dir2data[board.dir]
-            if data is not None:
-                if target in target2data:
-                    data = copy.deepcopy(data)
-                    data.update(target2data[target])
-                init_and_add_platforms(data, board, target, aliases, board.dir)
-
-            target2aliases[target] = aliases
-
-        for file in legacy_files:
-            try:
-                data = scl.yaml_load_verify(file, Platform.platform_schema)
-            except Exception as e:
-                logger.error(f"Error loading {file}: {e!r}")
-                self.load_errors += 1
                 continue
-            target = alias2target.get(data.get("identifier"))
-            if target is not None:
-                init_and_add_platforms(
-                    data, target2board[target], target, target2aliases[target], file.parent
-                )
+            self.platforms.append(platform)
 
-        for platform in self.platforms:
             if not platform_config.get('override_default_platforms', False):
                 if platform.default:
                     self.default_platforms.append(platform.name)
@@ -706,12 +595,14 @@ def get_platform(self, name):
 
     def handle_quarantined_tests(self, instance: TestInstance, plat: Platform):
         if self.quarantine:
-            simulator = plat.simulator_by_name(self.options)
+            sim_name = plat.simulation
+            if sim_name != "na" and (simulator := plat.simulator_by_name(self.options.sim_name)):
+                sim_name = simulator.name
             matched_quarantine = self.quarantine.get_matched_quarantine(
                 instance.testsuite.id,
                 plat.name,
                 plat.arch,
-                simulator.name if simulator is not None else 'na'
+                sim_name
             )
             if matched_quarantine and not self.options.quarantine_verify:
                 instance.add_filter("Quarantine: " + matched_quarantine, Filters.QUARANTINE)
@@ -844,7 +735,7 @@ def apply_filters(self, **kwargs):
             logger.info("Selecting default platforms per testsuite scenario")
             default_platforms = True
         elif emu_filter:
-            logger.info("Selecting emulation platforms per testsuite scenraio")
+            logger.info("Selecting emulation platforms per testsuite scenario")
             emulation_platforms = True
         elif vendor_filter:
             vendor_platforms = True
@@ -878,29 +769,35 @@ def apply_filters(self, **kwargs):
             platforms = self.platforms
 
         platform_config = self.test_config.get('platforms', {})
+        # test configuration options
+        test_config_options = self.test_config.get('options', {})
+        integration_mode_list = test_config_options.get('integration_mode', [])
+
         logger.info("Building initial testsuite list...")
 
         keyed_tests = {}
-
         for _, ts in self.testsuites.items():
-            if (
-                ts.build_on_all
-                and not platform_filter
-                and platform_config.get('increased_platform_scope', True)
-            ):
-                platform_scope = self.platforms
-            elif ts.integration_platforms:
-                integration_platforms = list(
+            if ts.integration_platforms:
+                _integration_platforms = list(
                     filter(lambda item: item.name in ts.integration_platforms, self.platforms)
                 )
-                if self.options.integration:
-                    platform_scope = integration_platforms
+            else:
+                _integration_platforms = []
+
+            if (ts.build_on_all and not platform_filter and
+                platform_config.get('increased_platform_scope', True)):
+                # if build_on_all is set, we build on all platforms
+                platform_scope = self.platforms
+            elif ts.integration_platforms and self.options.integration:
+                # if integration is set, we build on integration platforms
+                platform_scope = _integration_platforms
+            elif ts.integration_platforms and not platform_filter:
+                # if integration platforms are set, we build on those and integration mode is set
+                # for this test suite, we build on integration platforms
+                if any(ts.id.startswith(i) for i in integration_mode_list):
+                    platform_scope = _integration_platforms
                 else:
-                    # if not in integration mode, still add integration platforms to the list
-                    if not platform_filter:
-                        platform_scope = platforms + integration_platforms
-                    else:
-                        platform_scope = platforms
+                    platform_scope = platforms + _integration_platforms
             else:
                 platform_scope = platforms
 
@@ -928,9 +825,14 @@ def apply_filters(self, **kwargs):
             ):
                 if itoolchain:
                     toolchain = itoolchain
+                elif plat.arch in ['posix', 'unit']:
+                    # workaround until toolchain variant in zephyr is overhauled and improved.
+                    if self.env.toolchain in ['llvm']:
+                        toolchain = 'llvm'
+                    else:
+                        toolchain = 'host'
                 else:
-                    default_toolchain = "zephyr" if not self.env.toolchain else self.env.toolchain
-                    toolchain = default_toolchain if plat.arch not in ['posix', 'unit'] else "host"
+                    toolchain = "zephyr" if not self.env.toolchain else self.env.toolchain
 
                 instance = TestInstance(ts, plat, toolchain, self.env.outdir)
                 instance.run = instance.check_runnable(
@@ -1038,6 +940,8 @@ def apply_filters(self, **kwargs):
                         "Environment ({}) not satisfied".format(", ".join(plat.env)),
                         Filters.ENVIRONMENT
                     )
+                if plat.type == 'native' and sys.platform != 'linux':
+                    instance.add_filter("Native platform requires Linux", Filters.ENVIRONMENT)
 
                 if not force_toolchain \
                         and toolchain and (toolchain not in plat.supported_toolchains):
@@ -1060,7 +964,10 @@ def apply_filters(self, **kwargs):
                 if ts.depends_on:
                     dep_intersection = ts.depends_on.intersection(set(plat.supported))
                     if dep_intersection != set(ts.depends_on):
-                        instance.add_filter("No hardware support", Filters.PLATFORM)
+                        instance.add_filter(
+                            f"No hardware support for {set(ts.depends_on)-dep_intersection}",
+                            Filters.PLATFORM
+                        )
 
                 if plat.flash < ts.min_flash:
                     instance.add_filter("Not enough FLASH", Filters.PLATFORM)
diff --git a/scripts/pylib/twister/twisterlib/testsuite.py b/scripts/pylib/twister/twisterlib/testsuite.py
index a99e9c88e09..5d4f346effc 100644
--- a/scripts/pylib/twister/twisterlib/testsuite.py
+++ b/scripts/pylib/twister/twisterlib/testsuite.py
@@ -18,7 +18,6 @@
 from twisterlib.statuses import TwisterStatus
 
 logger = logging.getLogger('twister')
-logger.setLevel(logging.DEBUG)
 
 class ScanPathResult:
     """Result of the scan_tesuite_path function call.
diff --git a/scripts/pylib/twister/twisterlib/twister_main.py b/scripts/pylib/twister/twisterlib/twister_main.py
index 9d4485c885e..fabd739ba9c 100644
--- a/scripts/pylib/twister/twisterlib/twister_main.py
+++ b/scripts/pylib/twister/twisterlib/twister_main.py
@@ -15,51 +15,19 @@
 from twisterlib.coverage import run_coverage
 from twisterlib.environment import TwisterEnv
 from twisterlib.hardwaremap import HardwareMap
+from twisterlib.log_helper import close_logging, setup_logging
 from twisterlib.package import Artifacts
 from twisterlib.reports import Reporting
 from twisterlib.runner import TwisterRunner
 from twisterlib.statuses import TwisterStatus
 from twisterlib.testplan import TestPlan
 
-logger = logging.getLogger("twister")
-logger.setLevel(logging.DEBUG)
-
-
-def setup_logging(outdir, log_file, log_level, timestamps):
-    # create file handler which logs even debug messages
-    if log_file:
-        fh = logging.FileHandler(log_file)
-    else:
-        fh = logging.FileHandler(os.path.join(outdir, "twister.log"))
-
-    fh.setLevel(logging.DEBUG)
-
-    # create console handler with a higher log level
-    ch = logging.StreamHandler()
-    ch.setLevel(getattr(logging, log_level))
-
-    # create formatter and add it to the handlers
-    if timestamps:
-        formatter = logging.Formatter("%(asctime)s - %(levelname)s - %(message)s")
-    else:
-        formatter = logging.Formatter("%(levelname)-7s - %(message)s")
-
-    formatter_file = logging.Formatter(
-        "%(asctime)s - %(name)s - %(levelname)s - %(message)s"
-    )
-    ch.setFormatter(formatter)
-    fh.setFormatter(formatter_file)
-
-    # add the handlers to logger
-    logger.addHandler(ch)
-    logger.addHandler(fh)
-
 
 def init_color(colorama_strip):
     colorama.init(strip=colorama_strip)
 
 
-def main(options: argparse.Namespace, default_options: argparse.Namespace):
+def twister(options: argparse.Namespace, default_options: argparse.Namespace):
     start_time = time.time()
 
     # Configure color output
@@ -108,6 +76,7 @@ def main(options: argparse.Namespace, default_options: argparse.Namespace):
             fp.write(previous_results)
 
     setup_logging(options.outdir, options.log_file, options.log_level, options.timestamps)
+    logger = logging.getLogger("twister")
 
     env = TwisterEnv(options, default_options)
     env.discover()
@@ -212,12 +181,12 @@ def main(options: argparse.Namespace, default_options: argparse.Namespace):
     if options.verbose > 1:
         runner.results.summary()
 
-    report.summary(runner.results, options.disable_unrecognized_section_test, duration)
+    report.summary(runner.results, duration)
 
-    coverage_completed = True
-    if options.coverage:
+    report.coverage_status = True
+    if options.coverage and not options.disable_coverage_aggregation:
         if not options.build_only:
-            coverage_completed = run_coverage(tplan, options)
+            report.coverage_status, report.coverage = run_coverage(options, tplan)
         else:
             logger.info("Skipping coverage report generation due to --build-only.")
 
@@ -242,7 +211,7 @@ def main(options: argparse.Namespace, default_options: argparse.Namespace):
         runner.results.failed
         or runner.results.error
         or (tplan.warnings and options.warnings_as_errors)
-        or (options.coverage and not coverage_completed)
+        or (options.coverage and not report.coverage_status)
     ):
         if env.options.quit_on_failure:
             logger.info("twister aborted because of a failure/error")
@@ -252,3 +221,11 @@ def main(options: argparse.Namespace, default_options: argparse.Namespace):
 
     logger.info("Run completed")
     return 0
+
+
+def main(options: argparse.Namespace, default_options: argparse.Namespace):
+    try:
+        return_code = twister(options, default_options)
+    finally:
+        close_logging()
+    return return_code
diff --git a/scripts/requirements-actions.in b/scripts/requirements-actions.in
new file mode 100644
index 00000000000..01b58392914
--- /dev/null
+++ b/scripts/requirements-actions.in
@@ -0,0 +1,41 @@
+# zephyr-keep-sorted-start
+anytree
+awscli
+canopen
+clang-format>=15.0.0
+elasticsearch
+exceptiongroup>=1.0.0rc8
+gcovr==6.0
+gitlint>=0.19.1
+gitpython>=3.1.41
+ijson
+intelhex
+junit2html
+junitparser>=2
+lxml>=5.3.0
+mock
+mypy
+natsort
+ply>=3.10
+progress
+psutil>=5.6.6
+pyelftools>=0.29
+pygithub
+pykwalify
+pylint>=3
+pyserial
+pytest
+python-magic-bin; sys_platform == "win32"
+python-magic; sys_platform != "win32"
+pyyaml
+ruff==0.8.1
+setuptools>=70.2.0
+sphinx-lint
+tabulate
+tomli>=1.1.0
+tox
+unidiff
+west>=0.14.0
+xlsxwriter
+yamllint
+# zephyr-keep-sorted-stop
diff --git a/scripts/requirements-actions.txt b/scripts/requirements-actions.txt
new file mode 100644
index 00000000000..eefc92109a1
--- /dev/null
+++ b/scripts/requirements-actions.txt
@@ -0,0 +1,1345 @@
+# This file was autogenerated by uv via the following command:
+#    uv pip compile --universal --python-version 3.10 --generate-hashes requirements-actions.in
+anytree==2.12.1 \
+    --hash=sha256:244def434ccf31b668ed282954e5d315b4e066c4940b94aff4a7962d85947830 \
+    --hash=sha256:5ea9e61caf96db1e5b3d0a914378d2cd83c269dfce1fb8242ce96589fa3382f0
+    # via -r requirements-actions.in
+arrow==1.2.3 \
+    --hash=sha256:3934b30ca1b9f292376d9db15b19446088d12ec58629bc3f0da28fd55fb633a1 \
+    --hash=sha256:5a49ab92e3b7b71d96cd6bfcc4df14efefc9dfa96ea19045815914a6ab6b1fe2
+    # via gitlint-core
+astroid==3.3.9 \
+    --hash=sha256:622cc8e3048684aa42c820d9d218978021c3c3d174fb03a9f0d615921744f550 \
+    --hash=sha256:d05bfd0acba96a7bd43e222828b7d9bc1e138aaeb0649707908d3702a9831248
+    # via pylint
+awscli==1.38.23 \
+    --hash=sha256:43815c87b655d1cb8b41be2c40ce8c47348999a93f8b52f6c462fa4ada5768e3 \
+    --hash=sha256:8d4746235f4565760cadcb8b303d9d6756dbba1edd7bae8e219ef0910ed61cf4
+    # via -r requirements-actions.in
+botocore==1.37.23 \
+    --hash=sha256:3a249c950cef9ee9ed7b2278500ad83a4ad6456bc433a43abd1864d1b61b2acb \
+    --hash=sha256:ffbe1f5958adb1c50d72d3ad1018cb265fe349248c08782d334601c0814f0e38
+    # via
+    #   awscli
+    #   s3transfer
+cachetools==5.5.2 \
+    --hash=sha256:1a661caa9175d26759571b2e19580f9d6393969e5dfca11fdb1f947a23e640d4 \
+    --hash=sha256:d26a22bcc62eb95c3beabd9f1ee5e820d3d2704fe2967cbe350e20c8ffcd3f0a
+    # via tox
+canopen==2.3.0 \
+    --hash=sha256:792084a93c138d5b2a406ddd2d4eb5ce208f03bd8fda60f81ad2bb8d56c6b827 \
+    --hash=sha256:7a62274af6ded7ee85ee96f4ada3afa38bc8607a91f306dcc202c3c8cf2850d7
+    # via -r requirements-actions.in
+certifi==2025.1.31 \
+    --hash=sha256:3d5da6925056f6f18f119200434a4780a94263f10d1c21d032a6f6b2baa20651 \
+    --hash=sha256:ca78db4565a652026a4db2bcdf68f2fb589ea80d0be70e03929ed730746b84fe
+    # via
+    #   elastic-transport
+    #   requests
+cffi==1.17.1 \
+    --hash=sha256:045d61c734659cc045141be4bae381a41d89b741f795af1dd018bfb532fd0df8 \
+    --hash=sha256:0984a4925a435b1da406122d4d7968dd861c1385afe3b45ba82b750f229811e2 \
+    --hash=sha256:0e2b1fac190ae3ebfe37b979cc1ce69c81f4e4fe5746bb401dca63a9062cdaf1 \
+    --hash=sha256:0f048dcf80db46f0098ccac01132761580d28e28bc0f78ae0d58048063317e15 \
+    --hash=sha256:1257bdabf294dceb59f5e70c64a3e2f462c30c7ad68092d01bbbfb1c16b1ba36 \
+    --hash=sha256:1c39c6016c32bc48dd54561950ebd6836e1670f2ae46128f67cf49e789c52824 \
+    --hash=sha256:1d599671f396c4723d016dbddb72fe8e0397082b0a77a4fab8028923bec050e8 \
+    --hash=sha256:28b16024becceed8c6dfbc75629e27788d8a3f9030691a1dbf9821a128b22c36 \
+    --hash=sha256:2bb1a08b8008b281856e5971307cc386a8e9c5b625ac297e853d36da6efe9c17 \
+    --hash=sha256:30c5e0cb5ae493c04c8b42916e52ca38079f1b235c2f8ae5f4527b963c401caf \
+    --hash=sha256:31000ec67d4221a71bd3f67df918b1f88f676f1c3b535a7eb473255fdc0b83fc \
+    --hash=sha256:386c8bf53c502fff58903061338ce4f4950cbdcb23e2902d86c0f722b786bbe3 \
+    --hash=sha256:3edc8d958eb099c634dace3c7e16560ae474aa3803a5df240542b305d14e14ed \
+    --hash=sha256:45398b671ac6d70e67da8e4224a065cec6a93541bb7aebe1b198a61b58c7b702 \
+    --hash=sha256:46bf43160c1a35f7ec506d254e5c890f3c03648a4dbac12d624e4490a7046cd1 \
+    --hash=sha256:4ceb10419a9adf4460ea14cfd6bc43d08701f0835e979bf821052f1805850fe8 \
+    --hash=sha256:51392eae71afec0d0c8fb1a53b204dbb3bcabcb3c9b807eedf3e1e6ccf2de903 \
+    --hash=sha256:5da5719280082ac6bd9aa7becb3938dc9f9cbd57fac7d2871717b1feb0902ab6 \
+    --hash=sha256:610faea79c43e44c71e1ec53a554553fa22321b65fae24889706c0a84d4ad86d \
+    --hash=sha256:636062ea65bd0195bc012fea9321aca499c0504409f413dc88af450b57ffd03b \
+    --hash=sha256:6883e737d7d9e4899a8a695e00ec36bd4e5e4f18fabe0aca0efe0a4b44cdb13e \
+    --hash=sha256:6b8b4a92e1c65048ff98cfe1f735ef8f1ceb72e3d5f0c25fdb12087a23da22be \
+    --hash=sha256:6f17be4345073b0a7b8ea599688f692ac3ef23ce28e5df79c04de519dbc4912c \
+    --hash=sha256:706510fe141c86a69c8ddc029c7910003a17353970cff3b904ff0686a5927683 \
+    --hash=sha256:72e72408cad3d5419375fc87d289076ee319835bdfa2caad331e377589aebba9 \
+    --hash=sha256:733e99bc2df47476e3848417c5a4540522f234dfd4ef3ab7fafdf555b082ec0c \
+    --hash=sha256:7596d6620d3fa590f677e9ee430df2958d2d6d6de2feeae5b20e82c00b76fbf8 \
+    --hash=sha256:78122be759c3f8a014ce010908ae03364d00a1f81ab5c7f4a7a5120607ea56e1 \
+    --hash=sha256:805b4371bf7197c329fcb3ead37e710d1bca9da5d583f5073b799d5c5bd1eee4 \
+    --hash=sha256:85a950a4ac9c359340d5963966e3e0a94a676bd6245a4b55bc43949eee26a655 \
+    --hash=sha256:8f2cdc858323644ab277e9bb925ad72ae0e67f69e804f4898c070998d50b1a67 \
+    --hash=sha256:9755e4345d1ec879e3849e62222a18c7174d65a6a92d5b346b1863912168b595 \
+    --hash=sha256:98e3969bcff97cae1b2def8ba499ea3d6f31ddfdb7635374834cf89a1a08ecf0 \
+    --hash=sha256:a08d7e755f8ed21095a310a693525137cfe756ce62d066e53f502a83dc550f65 \
+    --hash=sha256:a1ed2dd2972641495a3ec98445e09766f077aee98a1c896dcb4ad0d303628e41 \
+    --hash=sha256:a24ed04c8ffd54b0729c07cee15a81d964e6fee0e3d4d342a27b020d22959dc6 \
+    --hash=sha256:a45e3c6913c5b87b3ff120dcdc03f6131fa0065027d0ed7ee6190736a74cd401 \
+    --hash=sha256:a9b15d491f3ad5d692e11f6b71f7857e7835eb677955c00cc0aefcd0669adaf6 \
+    --hash=sha256:ad9413ccdeda48c5afdae7e4fa2192157e991ff761e7ab8fdd8926f40b160cc3 \
+    --hash=sha256:b2ab587605f4ba0bf81dc0cb08a41bd1c0a5906bd59243d56bad7668a6fc6c16 \
+    --hash=sha256:b62ce867176a75d03a665bad002af8e6d54644fad99a3c70905c543130e39d93 \
+    --hash=sha256:c03e868a0b3bc35839ba98e74211ed2b05d2119be4e8a0f224fba9384f1fe02e \
+    --hash=sha256:c59d6e989d07460165cc5ad3c61f9fd8f1b4796eacbd81cee78957842b834af4 \
+    --hash=sha256:c7eac2ef9b63c79431bc4b25f1cd649d7f061a28808cbc6c47b534bd789ef964 \
+    --hash=sha256:c9c3d058ebabb74db66e431095118094d06abf53284d9c81f27300d0e0d8bc7c \
+    --hash=sha256:ca74b8dbe6e8e8263c0ffd60277de77dcee6c837a3d0881d8c1ead7268c9e576 \
+    --hash=sha256:caaf0640ef5f5517f49bc275eca1406b0ffa6aa184892812030f04c2abf589a0 \
+    --hash=sha256:cdf5ce3acdfd1661132f2a9c19cac174758dc2352bfe37d98aa7512c6b7178b3 \
+    --hash=sha256:d016c76bdd850f3c626af19b0542c9677ba156e4ee4fccfdd7848803533ef662 \
+    --hash=sha256:d01b12eeeb4427d3110de311e1774046ad344f5b1a7403101878976ecd7a10f3 \
+    --hash=sha256:d63afe322132c194cf832bfec0dc69a99fb9bb6bbd550f161a49e9e855cc78ff \
+    --hash=sha256:da95af8214998d77a98cc14e3a3bd00aa191526343078b530ceb0bd710fb48a5 \
+    --hash=sha256:dd398dbc6773384a17fe0d3e7eeb8d1a21c2200473ee6806bb5e6a8e62bb73dd \
+    --hash=sha256:de2ea4b5833625383e464549fec1bc395c1bdeeb5f25c4a3a82b5a8c756ec22f \
+    --hash=sha256:de55b766c7aa2e2a3092c51e0483d700341182f08e67c63630d5b6f200bb28e5 \
+    --hash=sha256:df8b1c11f177bc2313ec4b2d46baec87a5f3e71fc8b45dab2ee7cae86d9aba14 \
+    --hash=sha256:e03eab0a8677fa80d646b5ddece1cbeaf556c313dcfac435ba11f107ba117b5d \
+    --hash=sha256:e221cf152cff04059d011ee126477f0d9588303eb57e88923578ace7baad17f9 \
+    --hash=sha256:e31ae45bc2e29f6b2abd0de1cc3b9d5205aa847cafaecb8af1476a609a2f6eb7 \
+    --hash=sha256:edae79245293e15384b51f88b00613ba9f7198016a5948b5dddf4917d4d26382 \
+    --hash=sha256:f1e22e8c4419538cb197e4dd60acc919d7696e5ef98ee4da4e01d3f8cfa4cc5a \
+    --hash=sha256:f3a2b4222ce6b60e2e8b337bb9596923045681d71e5a082783484d845390938e \
+    --hash=sha256:f6a16c31041f09ead72d69f583767292f750d24913dadacf5756b966aacb3f1a \
+    --hash=sha256:f75c7ab1f9e4aca5414ed4d8e5c0e303a34f4421f8a0d47a4d019ceff0ab6af4 \
+    --hash=sha256:f79fc4fc25f1c8698ff97788206bb3c2598949bfe0fef03d299eb1b5356ada99 \
+    --hash=sha256:f7f5baafcc48261359e14bcd6d9bff6d4b28d9103847c9e136694cb0501aef87 \
+    --hash=sha256:fc48c783f9c87e60831201f2cce7f3b2e4846bf4d8728eabe54d60700b318a0b
+    # via
+    #   cryptography
+    #   pynacl
+chardet==5.2.0 \
+    --hash=sha256:1b3b6ff479a8c414bc3fa2c0852995695c4a026dcd6d0633b2dd092ca39c1cf7 \
+    --hash=sha256:e1cf59446890a00105fe7b7912492ea04b6e6f06d4b742b2c788469e34c82970
+    # via tox
+charset-normalizer==3.4.1 \
+    --hash=sha256:0167ddc8ab6508fe81860a57dd472b2ef4060e8d378f0cc555707126830f2537 \
+    --hash=sha256:01732659ba9b5b873fc117534143e4feefecf3b2078b0a6a2e925271bb6f4cfa \
+    --hash=sha256:01ad647cdd609225c5350561d084b42ddf732f4eeefe6e678765636791e78b9a \
+    --hash=sha256:04432ad9479fa40ec0f387795ddad4437a2b50417c69fa275e212933519ff294 \
+    --hash=sha256:0907f11d019260cdc3f94fbdb23ff9125f6b5d1039b76003b5b0ac9d6a6c9d5b \
+    --hash=sha256:0924e81d3d5e70f8126529951dac65c1010cdf117bb75eb02dd12339b57749dd \
+    --hash=sha256:09b26ae6b1abf0d27570633b2b078a2a20419c99d66fb2823173d73f188ce601 \
+    --hash=sha256:09b5e6733cbd160dcc09589227187e242a30a49ca5cefa5a7edd3f9d19ed53fd \
+    --hash=sha256:0af291f4fe114be0280cdd29d533696a77b5b49cfde5467176ecab32353395c4 \
+    --hash=sha256:0f55e69f030f7163dffe9fd0752b32f070566451afe180f99dbeeb81f511ad8d \
+    --hash=sha256:1a2bc9f351a75ef49d664206d51f8e5ede9da246602dc2d2726837620ea034b2 \
+    --hash=sha256:22e14b5d70560b8dd51ec22863f370d1e595ac3d024cb8ad7d308b4cd95f8313 \
+    --hash=sha256:234ac59ea147c59ee4da87a0c0f098e9c8d169f4dc2a159ef720f1a61bbe27cd \
+    --hash=sha256:2369eea1ee4a7610a860d88f268eb39b95cb588acd7235e02fd5a5601773d4fa \
+    --hash=sha256:237bdbe6159cff53b4f24f397d43c6336c6b0b42affbe857970cefbb620911c8 \
+    --hash=sha256:28bf57629c75e810b6ae989f03c0828d64d6b26a5e205535585f96093e405ed1 \
+    --hash=sha256:2967f74ad52c3b98de4c3b32e1a44e32975e008a9cd2a8cc8966d6a5218c5cb2 \
+    --hash=sha256:2a75d49014d118e4198bcee5ee0a6f25856b29b12dbf7cd012791f8a6cc5c496 \
+    --hash=sha256:2bdfe3ac2e1bbe5b59a1a63721eb3b95fc9b6817ae4a46debbb4e11f6232428d \
+    --hash=sha256:2d074908e1aecee37a7635990b2c6d504cd4766c7bc9fc86d63f9c09af3fa11b \
+    --hash=sha256:2fb9bd477fdea8684f78791a6de97a953c51831ee2981f8e4f583ff3b9d9687e \
+    --hash=sha256:311f30128d7d333eebd7896965bfcfbd0065f1716ec92bd5638d7748eb6f936a \
+    --hash=sha256:329ce159e82018d646c7ac45b01a430369d526569ec08516081727a20e9e4af4 \
+    --hash=sha256:345b0426edd4e18138d6528aed636de7a9ed169b4aaf9d61a8c19e39d26838ca \
+    --hash=sha256:363e2f92b0f0174b2f8238240a1a30142e3db7b957a5dd5689b0e75fb717cc78 \
+    --hash=sha256:3a3bd0dcd373514dcec91c411ddb9632c0d7d92aed7093b8c3bbb6d69ca74408 \
+    --hash=sha256:3bed14e9c89dcb10e8f3a29f9ccac4955aebe93c71ae803af79265c9ca5644c5 \
+    --hash=sha256:44251f18cd68a75b56585dd00dae26183e102cd5e0f9f1466e6df5da2ed64ea3 \
+    --hash=sha256:44ecbf16649486d4aebafeaa7ec4c9fed8b88101f4dd612dcaf65d5e815f837f \
+    --hash=sha256:4532bff1b8421fd0a320463030c7520f56a79c9024a4e88f01c537316019005a \
+    --hash=sha256:49402233c892a461407c512a19435d1ce275543138294f7ef013f0b63d5d3765 \
+    --hash=sha256:4c0907b1928a36d5a998d72d64d8eaa7244989f7aaaf947500d3a800c83a3fd6 \
+    --hash=sha256:4d86f7aff21ee58f26dcf5ae81a9addbd914115cdebcbb2217e4f0ed8982e146 \
+    --hash=sha256:5777ee0881f9499ed0f71cc82cf873d9a0ca8af166dfa0af8ec4e675b7df48e6 \
+    --hash=sha256:5df196eb874dae23dcfb968c83d4f8fdccb333330fe1fc278ac5ceeb101003a9 \
+    --hash=sha256:619a609aa74ae43d90ed2e89bdd784765de0a25ca761b93e196d938b8fd1dbbd \
+    --hash=sha256:6e27f48bcd0957c6d4cb9d6fa6b61d192d0b13d5ef563e5f2ae35feafc0d179c \
+    --hash=sha256:6ff8a4a60c227ad87030d76e99cd1698345d4491638dfa6673027c48b3cd395f \
+    --hash=sha256:73d94b58ec7fecbc7366247d3b0b10a21681004153238750bb67bd9012414545 \
+    --hash=sha256:7461baadb4dc00fd9e0acbe254e3d7d2112e7f92ced2adc96e54ef6501c5f176 \
+    --hash=sha256:75832c08354f595c760a804588b9357d34ec00ba1c940c15e31e96d902093770 \
+    --hash=sha256:7709f51f5f7c853f0fb938bcd3bc59cdfdc5203635ffd18bf354f6967ea0f824 \
+    --hash=sha256:78baa6d91634dfb69ec52a463534bc0df05dbd546209b79a3880a34487f4b84f \
+    --hash=sha256:7974a0b5ecd505609e3b19742b60cee7aa2aa2fb3151bc917e6e2646d7667dcf \
+    --hash=sha256:7a4f97a081603d2050bfaffdefa5b02a9ec823f8348a572e39032caa8404a487 \
+    --hash=sha256:7b1bef6280950ee6c177b326508f86cad7ad4dff12454483b51d8b7d673a2c5d \
+    --hash=sha256:7d053096f67cd1241601111b698f5cad775f97ab25d81567d3f59219b5f1adbd \
+    --hash=sha256:804a4d582ba6e5b747c625bf1255e6b1507465494a40a2130978bda7b932c90b \
+    --hash=sha256:807f52c1f798eef6cf26beb819eeb8819b1622ddfeef9d0977a8502d4db6d534 \
+    --hash=sha256:80ed5e856eb7f30115aaf94e4a08114ccc8813e6ed1b5efa74f9f82e8509858f \
+    --hash=sha256:8417cb1f36cc0bc7eaba8ccb0e04d55f0ee52df06df3ad55259b9a323555fc8b \
+    --hash=sha256:8436c508b408b82d87dc5f62496973a1805cd46727c34440b0d29d8a2f50a6c9 \
+    --hash=sha256:89149166622f4db9b4b6a449256291dc87a99ee53151c74cbd82a53c8c2f6ccd \
+    --hash=sha256:8bfa33f4f2672964266e940dd22a195989ba31669bd84629f05fab3ef4e2d125 \
+    --hash=sha256:8c60ca7339acd497a55b0ea5d506b2a2612afb2826560416f6894e8b5770d4a9 \
+    --hash=sha256:91b36a978b5ae0ee86c394f5a54d6ef44db1de0815eb43de826d41d21e4af3de \
+    --hash=sha256:955f8851919303c92343d2f66165294848d57e9bba6cf6e3625485a70a038d11 \
+    --hash=sha256:97f68b8d6831127e4787ad15e6757232e14e12060bec17091b85eb1486b91d8d \
+    --hash=sha256:9b23ca7ef998bc739bf6ffc077c2116917eabcc901f88da1b9856b210ef63f35 \
+    --hash=sha256:9f0b8b1c6d84c8034a44893aba5e767bf9c7a211e313a9605d9c617d7083829f \
+    --hash=sha256:aabfa34badd18f1da5ec1bc2715cadc8dca465868a4e73a0173466b688f29dda \
+    --hash=sha256:ab36c8eb7e454e34e60eb55ca5d241a5d18b2c6244f6827a30e451c42410b5f7 \
+    --hash=sha256:b010a7a4fd316c3c484d482922d13044979e78d1861f0e0650423144c616a46a \
+    --hash=sha256:b1ac5992a838106edb89654e0aebfc24f5848ae2547d22c2c3f66454daa11971 \
+    --hash=sha256:b7b2d86dd06bfc2ade3312a83a5c364c7ec2e3498f8734282c6c3d4b07b346b8 \
+    --hash=sha256:b97e690a2118911e39b4042088092771b4ae3fc3aa86518f84b8cf6888dbdb41 \
+    --hash=sha256:bc2722592d8998c870fa4e290c2eec2c1569b87fe58618e67d38b4665dfa680d \
+    --hash=sha256:c0429126cf75e16c4f0ad00ee0eae4242dc652290f940152ca8c75c3a4b6ee8f \
+    --hash=sha256:c30197aa96e8eed02200a83fba2657b4c3acd0f0aa4bdc9f6c1af8e8962e0757 \
+    --hash=sha256:c4c3e6da02df6fa1410a7680bd3f63d4f710232d3139089536310d027950696a \
+    --hash=sha256:c75cb2a3e389853835e84a2d8fb2b81a10645b503eca9bcb98df6b5a43eb8886 \
+    --hash=sha256:c96836c97b1238e9c9e3fe90844c947d5afbf4f4c92762679acfe19927d81d77 \
+    --hash=sha256:d7f50a1f8c450f3925cb367d011448c39239bb3eb4117c36a6d354794de4ce76 \
+    --hash=sha256:d973f03c0cb71c5ed99037b870f2be986c3c05e63622c017ea9816881d2dd247 \
+    --hash=sha256:d98b1668f06378c6dbefec3b92299716b931cd4e6061f3c875a71ced1780ab85 \
+    --hash=sha256:d9c3cdf5390dcd29aa8056d13e8e99526cda0305acc038b96b30352aff5ff2bb \
+    --hash=sha256:dad3e487649f498dd991eeb901125411559b22e8d7ab25d3aeb1af367df5efd7 \
+    --hash=sha256:dccbe65bd2f7f7ec22c4ff99ed56faa1e9f785482b9bbd7c717e26fd723a1d1e \
+    --hash=sha256:dd78cfcda14a1ef52584dbb008f7ac81c1328c0f58184bf9a84c49c605002da6 \
+    --hash=sha256:e218488cd232553829be0664c2292d3af2eeeb94b32bea483cf79ac6a694e037 \
+    --hash=sha256:e358e64305fe12299a08e08978f51fc21fac060dcfcddd95453eabe5b93ed0e1 \
+    --hash=sha256:ea0d8d539afa5eb2728aa1932a988a9a7af94f18582ffae4bc10b3fbdad0626e \
+    --hash=sha256:eab677309cdb30d047996b36d34caeda1dc91149e4fdca0b1a039b3f79d9a807 \
+    --hash=sha256:eb8178fe3dba6450a3e024e95ac49ed3400e506fd4e9e5c32d30adda88cbd407 \
+    --hash=sha256:ecddf25bee22fe4fe3737a399d0d177d72bc22be6913acfab364b40bce1ba83c \
+    --hash=sha256:eea6ee1db730b3483adf394ea72f808b6e18cf3cb6454b4d86e04fa8c4327a12 \
+    --hash=sha256:f08ff5e948271dc7e18a35641d2f11a4cd8dfd5634f55228b691e62b37125eb3 \
+    --hash=sha256:f30bf9fd9be89ecb2360c7d94a711f00c09b976258846efe40db3d05828e8089 \
+    --hash=sha256:fa88b843d6e211393a37219e6a1c1df99d35e8fd90446f1118f4216e307e48cd \
+    --hash=sha256:fc54db6c8593ef7d4b2a331b58653356cf04f67c960f584edb7c3d8c97e8f39e \
+    --hash=sha256:fd4ec41f914fa74ad1b8304bbc634b3de73d2a0889bd32076342a573e0779e00 \
+    --hash=sha256:ffc9202a29ab3920fa812879e95a9e78b2465fd10be7fcbd042899695d75e616
+    # via requests
+clang-format==20.1.0 \
+    --hash=sha256:1a023510c49a5c0bf9966263503b3af20f42ef6425d8f4a53141c41c58f84d25 \
+    --hash=sha256:48369361bf8bef60ca3aeee51c8d55821bb62228489c1a1155703a2634598df6 \
+    --hash=sha256:5413c54938d31673ae9c3043527ee4414e0b8980b89b8417bd9663bf18ab2010 \
+    --hash=sha256:5a2dbe11203275627cea3286f018b4eee36670607b76b467f067132c8eb999d0 \
+    --hash=sha256:5e5d6bc8d2f54d8e8058b93627468c571ce971c541cd3ea7751cd6d711eb5a19 \
+    --hash=sha256:6d054c0a328926436262ba0e00b527059e14c7f65bf5bad5a8f82fbed680bd53 \
+    --hash=sha256:700b32da1e03c485a53113b41693846e930c3066803e713064a1ff2797dbeba3 \
+    --hash=sha256:82b2a19e5b345fcf7d6bf478b5d48e242eb84d47ae04cb54ae0561464f812bcd \
+    --hash=sha256:85599f9f2314d3a82c002362e1119d49726ef8dc2082497acfea2892e9a446f1 \
+    --hash=sha256:934bc103f9cd3009ee7259ac54df08dbcef38d4c970c0171bc68517f67e4720f \
+    --hash=sha256:ade5b45e2faadddbf3fabe93b65d04567ded59fb483708a8417bacc4a96d5bc3 \
+    --hash=sha256:c20b5be0d9347b5b3a2c4af67e3e9d7a7254a8a9fa7f17628639e2c0a3fea8e9 \
+    --hash=sha256:ca6410aacd5e7b827f9025a52ac01344ed5df58bd27adbce0d1564ea331919ea \
+    --hash=sha256:dc4b094b4cd1824342b1f6f78f41d2c7f336df89e785b506fcd098d1d3f02d82 \
+    --hash=sha256:e1cd4a018ea15a5f675158ab1468d4a2e827f8266fa56773916a5f294a32c51d
+    # via -r requirements-actions.in
+click==8.1.3 \
+    --hash=sha256:7682dc8afb30297001674575ea00d1814d808d6a36af415a82bd481d37ba7b8e \
+    --hash=sha256:bb4d8133cb15a609f44e8213d9b391b0809795062913b383c62be0ee95b1db48
+    # via gitlint-core
+colorama==0.4.6 \
+    --hash=sha256:08695f5cb7ed6e0531a20572697297273c47b8cae5a63ffc6d6ed5c201be6e44 \
+    --hash=sha256:4f1d9991f5acc0ca119f9d443620b77f9d6b33703e51011c16baf57afb285fc6
+    # via
+    #   awscli
+    #   click
+    #   pylint
+    #   pytest
+    #   tox
+    #   west
+cryptography==44.0.2 \
+    --hash=sha256:04abd71114848aa25edb28e225ab5f268096f44cf0127f3d36975bdf1bdf3390 \
+    --hash=sha256:0529b1d5a0105dd3731fa65680b45ce49da4d8115ea76e9da77a875396727b41 \
+    --hash=sha256:1bc312dfb7a6e5d66082c87c34c8a62176e684b6fe3d90fcfe1568de675e6688 \
+    --hash=sha256:268e4e9b177c76d569e8a145a6939eca9a5fec658c932348598818acf31ae9a5 \
+    --hash=sha256:29ecec49f3ba3f3849362854b7253a9f59799e3763b0c9d0826259a88efa02f1 \
+    --hash=sha256:2bf7bf75f7df9715f810d1b038870309342bff3069c5bd8c6b96128cb158668d \
+    --hash=sha256:3b721b8b4d948b218c88cb8c45a01793483821e709afe5f622861fc6182b20a7 \
+    --hash=sha256:3c00b6b757b32ce0f62c574b78b939afab9eecaf597c4d624caca4f9e71e7843 \
+    --hash=sha256:3dc62975e31617badc19a906481deacdeb80b4bb454394b4098e3f2525a488c5 \
+    --hash=sha256:4973da6ca3db4405c54cd0b26d328be54c7747e89e284fcff166132eb7bccc9c \
+    --hash=sha256:4e389622b6927d8133f314949a9812972711a111d577a5d1f4bee5e58736b80a \
+    --hash=sha256:51e4de3af4ec3899d6d178a8c005226491c27c4ba84101bfb59c901e10ca9f79 \
+    --hash=sha256:5f6f90b72d8ccadb9c6e311c775c8305381db88374c65fa1a68250aa8a9cb3a6 \
+    --hash=sha256:6210c05941994290f3f7f175a4a57dbbb2afd9273657614c506d5976db061181 \
+    --hash=sha256:6f101b1f780f7fc613d040ca4bdf835c6ef3b00e9bd7125a4255ec574c7916e4 \
+    --hash=sha256:7bdcd82189759aba3816d1f729ce42ffded1ac304c151d0a8e89b9996ab863d5 \
+    --hash=sha256:7ca25849404be2f8e4b3c59483d9d3c51298a22c1c61a0e84415104dacaf5562 \
+    --hash=sha256:81276f0ea79a208d961c433a947029e1a15948966658cf6710bbabb60fcc2639 \
+    --hash=sha256:8cadc6e3b5a1f144a039ea08a0bdb03a2a92e19c46be3285123d32029f40a922 \
+    --hash=sha256:8e0ddd63e6bf1161800592c71ac794d3fb8001f2caebe0966e77c5234fa9efc3 \
+    --hash=sha256:909c97ab43a9c0c0b0ada7a1281430e4e5ec0458e6d9244c0e821bbf152f061d \
+    --hash=sha256:96e7a5e9d6e71f9f4fca8eebfd603f8e86c5225bb18eb621b2c1e50b290a9471 \
+    --hash=sha256:9a1e657c0f4ea2a23304ee3f964db058c9e9e635cc7019c4aa21c330755ef6fd \
+    --hash=sha256:9eb9d22b0a5d8fd9925a7764a054dca914000607dff201a24c791ff5c799e1fa \
+    --hash=sha256:af4ff3e388f2fa7bff9f7f2b31b87d5651c45731d3e8cfa0944be43dff5cfbdb \
+    --hash=sha256:b042d2a275c8cee83a4b7ae30c45a15e6a4baa65a179a0ec2d78ebb90e4f6699 \
+    --hash=sha256:bc821e161ae88bfe8088d11bb39caf2916562e0a2dc7b6d56714a48b784ef0bb \
+    --hash=sha256:c505d61b6176aaf982c5717ce04e87da5abc9a36a5b39ac03905c4aafe8de7aa \
+    --hash=sha256:c63454aa261a0cf0c5b4718349629793e9e634993538db841165b3df74f37ec0 \
+    --hash=sha256:c7362add18b416b69d58c910caa217f980c5ef39b23a38a0880dfd87bdf8cd23 \
+    --hash=sha256:d03806036b4f89e3b13b6218fefea8d5312e450935b1a2d55f0524e2ed7c59d9 \
+    --hash=sha256:d1b3031093a366ac767b3feb8bcddb596671b3aaff82d4050f984da0c248b615 \
+    --hash=sha256:d1c3572526997b36f245a96a2b1713bf79ce99b271bbcf084beb6b9b075f29ea \
+    --hash=sha256:efcfe97d1b3c79e486554efddeb8f6f53a4cdd4cf6086642784fa31fc384e1d7 \
+    --hash=sha256:f514ef4cd14bb6fb484b4a60203e912cfcb64f2ab139e88c2274511514bf7308
+    # via pyjwt
+deprecated==1.2.18 \
+    --hash=sha256:422b6f6d859da6f2ef57857761bfb392480502a64c3028ca9bbe86085d72115d \
+    --hash=sha256:bd5011788200372a32418f888e326a09ff80d0214bd961147cfed01b5c018eec
+    # via pygithub
+dill==0.3.9 \
+    --hash=sha256:468dff3b89520b474c0397703366b7b95eebe6303f108adf9b19da1f702be87a \
+    --hash=sha256:81aa267dddf68cbfe8029c42ca9ec6a4ab3b22371d1c450abc54422577b4512c
+    # via pylint
+distlib==0.3.9 \
+    --hash=sha256:47f8c22fd27c27e25a65601af709b38e4f0a45ea4fc2e710f65755fa8caaaf87 \
+    --hash=sha256:a60f20dea646b8a33f3e7772f74dc0b2d0772d2837ee1342a00645c81edf9403
+    # via virtualenv
+docopt==0.6.2 \
+    --hash=sha256:49b3a825280bd66b3aa83585ef59c4a8c82f2c8a522dbe754a8bc8d08c85c491
+    # via pykwalify
+docutils==0.16 \
+    --hash=sha256:0c5b78adfbf7762415433f5515cd5c9e762339e23369dbe8000d84a4bf4ab3af \
+    --hash=sha256:c2de3a60e9e7d07be26b7f2b00ca0309c207e06c100f9cc2a94931fc75a478fc
+    # via awscli
+elastic-transport==8.17.1 \
+    --hash=sha256:192718f498f1d10c5e9aa8b9cf32aed405e469a7f0e9d6a8923431dbb2c59fb8 \
+    --hash=sha256:5edef32ac864dca8e2f0a613ef63491ee8d6b8cfb52881fa7313ba9290cac6d2
+    # via elasticsearch
+elasticsearch==8.17.2 \
+    --hash=sha256:2d058dcddd8f2686cd431a916cdf983f9fb7d211d902834f564ab7df05ba6478 \
+    --hash=sha256:ff7f1db8aeefd87ceba4edce3aa4070994582e6cf029d2e67b74e66d634509db
+    # via -r requirements-actions.in
+exceptiongroup==1.2.2 \
+    --hash=sha256:3111b9d131c238bec2f8f516e123e14ba243563fb135d3fe885990585aa7795b \
+    --hash=sha256:47c2edf7c6738fafb49fd34290706d1a1a2f4d1c6df275526b62cbb4aa5393cc
+    # via
+    #   -r requirements-actions.in
+    #   pytest
+filelock==3.18.0 \
+    --hash=sha256:adbc88eabb99d2fec8c9c1b229b171f18afa655400173ddc653d5d01501fb9f2 \
+    --hash=sha256:c401f4f8377c4464e6db25fff06205fd89bdd83b65eb0488ed1b160f780e21de
+    # via
+    #   tox
+    #   virtualenv
+gcovr==6.0 \
+    --hash=sha256:2e52019fdb76c6e327f48c2a2d8555fb5e362570b79cc74c5498804d1ce54a60 \
+    --hash=sha256:8638d5f44def10e38e3166c8a33bef6643ec204687e0ac7d345ce41a98c5750b
+    # via -r requirements-actions.in
+gitdb==4.0.12 \
+    --hash=sha256:5ef71f855d191a3326fcfbc0d5da835f26b13fbcba60c32c21091c349ffdb571 \
+    --hash=sha256:67073e15955400952c6565cc3e707c554a4eea2e428946f7a4c162fab9bd9bcf
+    # via gitpython
+gitlint==0.19.1 \
+    --hash=sha256:26bb085959148d99fbbc178b4e56fda6c3edd7646b7c2a24d8ee1f8e036ed85d \
+    --hash=sha256:b5b70fb894e80849b69abbb65ee7dbb3520fc3511f202a6e6b6ddf1a71ee8f61
+    # via -r requirements-actions.in
+gitlint-core==0.19.1 \
+    --hash=sha256:7bf977b03ff581624a9e03f65ebb8502cc12dfaa3e92d23e8b2b54bbdaa29992 \
+    --hash=sha256:f41effd1dcbc06ffbfc56b6888cce72241796f517b46bd9fd4ab1b145056988c
+    # via gitlint
+gitpython==3.1.44 \
+    --hash=sha256:9e0e10cda9bed1ee64bc9a6de50e7e38a9c9943241cd7f585f6df3ed28011110 \
+    --hash=sha256:c87e30b26253bf5418b01b0660f818967f3c503193838337fe5e573331249269
+    # via -r requirements-actions.in
+idna==3.10 \
+    --hash=sha256:12f65c9b470abda6dc35cf8e63cc574b1c52b11df2c86030af0ac09b01b13ea9 \
+    --hash=sha256:946d195a0d259cbba61165e88e65941f16e9b36ea6ddb97f00452bae8b1287d3
+    # via requests
+ijson==3.3.0 \
+    --hash=sha256:0015354011303175eae7e2ef5136414e91de2298e5a2e9580ed100b728c07e51 \
+    --hash=sha256:034642558afa57351a0ffe6de89e63907c4cf6849070cc10a3b2542dccda1afe \
+    --hash=sha256:0420c24e50389bc251b43c8ed379ab3e3ba065ac8262d98beb6735ab14844460 \
+    --hash=sha256:04366e7e4a4078d410845e58a2987fd9c45e63df70773d7b6e87ceef771b51ee \
+    --hash=sha256:0b003501ee0301dbf07d1597482009295e16d647bb177ce52076c2d5e64113e0 \
+    --hash=sha256:0ee57a28c6bf523d7cb0513096e4eb4dac16cd935695049de7608ec110c2b751 \
+    --hash=sha256:192e4b65495978b0bce0c78e859d14772e841724d3269fc1667dc6d2f53cc0ea \
+    --hash=sha256:1efb521090dd6cefa7aafd120581947b29af1713c902ff54336b7c7130f04c47 \
+    --hash=sha256:25fd49031cdf5fd5f1fd21cb45259a64dad30b67e64f745cc8926af1c8c243d3 \
+    --hash=sha256:2636cb8c0f1023ef16173f4b9a233bcdb1df11c400c603d5f299fac143ca8d70 \
+    --hash=sha256:29ce02af5fbf9ba6abb70765e66930aedf73311c7d840478f1ccecac53fefbf3 \
+    --hash=sha256:2af323a8aec8a50fa9effa6d640691a30a9f8c4925bd5364a1ca97f1ac6b9b5c \
+    --hash=sha256:30cfea40936afb33b57d24ceaf60d0a2e3d5c1f2335ba2623f21d560737cc730 \
+    --hash=sha256:33afc25057377a6a43c892de34d229a86f89ea6c4ca3dd3db0dcd17becae0dbb \
+    --hash=sha256:36aa56d68ea8def26778eb21576ae13f27b4a47263a7a2581ab2ef58b8de4451 \
+    --hash=sha256:3917b2b3d0dbbe3296505da52b3cb0befbaf76119b2edaff30bd448af20b5400 \
+    --hash=sha256:3aba5c4f97f4e2ce854b5591a8b0711ca3b0c64d1b253b04ea7b004b0a197ef6 \
+    --hash=sha256:3c556f5553368dff690c11d0a1fb435d4ff1f84382d904ccc2dc53beb27ba62e \
+    --hash=sha256:3dc1fb02c6ed0bae1b4bf96971258bf88aea72051b6e4cebae97cff7090c0607 \
+    --hash=sha256:3e8d8de44effe2dbd0d8f3eb9840344b2d5b4cc284a14eb8678aec31d1b6bea8 \
+    --hash=sha256:40ee3821ee90be0f0e95dcf9862d786a7439bd1113e370736bfdf197e9765bfb \
+    --hash=sha256:44367090a5a876809eb24943f31e470ba372aaa0d7396b92b953dda953a95d14 \
+    --hash=sha256:45ff05de889f3dc3d37a59d02096948ce470699f2368b32113954818b21aa74a \
+    --hash=sha256:4690e3af7b134298055993fcbea161598d23b6d3ede11b12dca6815d82d101d5 \
+    --hash=sha256:473f5d921fadc135d1ad698e2697025045cd8ed7e5e842258295012d8a3bc702 \
+    --hash=sha256:47c144117e5c0e2babb559bc8f3f76153863b8dd90b2d550c51dab5f4b84a87f \
+    --hash=sha256:4ac6c3eeed25e3e2cb9b379b48196413e40ac4e2239d910bb33e4e7f6c137745 \
+    --hash=sha256:4b72178b1e565d06ab19319965022b36ef41bcea7ea153b32ec31194bec032a2 \
+    --hash=sha256:4e9ffe358d5fdd6b878a8a364e96e15ca7ca57b92a48f588378cef315a8b019e \
+    --hash=sha256:501dce8eaa537e728aa35810656aa00460a2547dcb60937c8139f36ec344d7fc \
+    --hash=sha256:5378d0baa59ae422905c5f182ea0fd74fe7e52a23e3821067a7d58c8306b2191 \
+    --hash=sha256:542c1e8fddf082159a5d759ee1412c73e944a9a2412077ed00b303ff796907dc \
+    --hash=sha256:63afea5f2d50d931feb20dcc50954e23cef4127606cc0ecf7a27128ed9f9a9e6 \
+    --hash=sha256:658ba9cad0374d37b38c9893f4864f284cdcc7d32041f9808fba8c7bcaadf134 \
+    --hash=sha256:6b661a959226ad0d255e49b77dba1d13782f028589a42dc3172398dd3814c797 \
+    --hash=sha256:72e3488453754bdb45c878e31ce557ea87e1eb0f8b4fc610373da35e8074ce42 \
+    --hash=sha256:7914d0cf083471856e9bc2001102a20f08e82311dfc8cf1a91aa422f9414a0d6 \
+    --hash=sha256:7ab00721304af1ae1afa4313ecfa1bf16b07f55ef91e4a5b93aeaa3e2bd7917c \
+    --hash=sha256:7d0b6b637d05dbdb29d0bfac2ed8425bb369e7af5271b0cc7cf8b801cb7360c2 \
+    --hash=sha256:7e2b3e9ca957153557d06c50a26abaf0d0d6c0ddf462271854c968277a6b5372 \
+    --hash=sha256:7f172e6ba1bee0d4c8f8ebd639577bfe429dee0f3f96775a067b8bae4492d8a0 \
+    --hash=sha256:7f7a5250599c366369fbf3bc4e176f5daa28eb6bc7d6130d02462ed335361675 \
+    --hash=sha256:844c0d1c04c40fd1b60f148dc829d3f69b2de789d0ba239c35136efe9a386529 \
+    --hash=sha256:8643c255a25824ddd0895c59f2319c019e13e949dc37162f876c41a283361527 \
+    --hash=sha256:8795e88adff5aa3c248c1edce932db003d37a623b5787669ccf205c422b91e4a \
+    --hash=sha256:87c727691858fd3a1c085d9980d12395517fcbbf02c69fbb22dede8ee03422da \
+    --hash=sha256:8851584fb931cffc0caa395f6980525fd5116eab8f73ece9d95e6f9c2c326c4c \
+    --hash=sha256:891f95c036df1bc95309951940f8eea8537f102fa65715cdc5aae20b8523813b \
+    --hash=sha256:8c85447569041939111b8c7dbf6f8fa7a0eb5b2c4aebb3c3bec0fb50d7025121 \
+    --hash=sha256:8e0ff16c224d9bfe4e9e6bd0395826096cda4a3ef51e6c301e1b61007ee2bd24 \
+    --hash=sha256:8f83f553f4cde6d3d4eaf58ec11c939c94a0ec545c5b287461cafb184f4b3a14 \
+    --hash=sha256:8f890d04ad33262d0c77ead53c85f13abfb82f2c8f078dfbf24b78f59534dfdd \
+    --hash=sha256:8fdf3721a2aa7d96577970f5604bd81f426969c1822d467f07b3d844fa2fecc7 \
+    --hash=sha256:907f3a8674e489abdcb0206723e5560a5cb1fa42470dcc637942d7b10f28b695 \
+    --hash=sha256:92355f95a0e4da96d4c404aa3cff2ff033f9180a9515f813255e1526551298c1 \
+    --hash=sha256:97a9aea46e2a8371c4cf5386d881de833ed782901ac9f67ebcb63bb3b7d115af \
+    --hash=sha256:988e959f2f3d59ebd9c2962ae71b97c0df58323910d0b368cc190ad07429d1bb \
+    --hash=sha256:99f5c8ab048ee4233cc4f2b461b205cbe01194f6201018174ac269bf09995749 \
+    --hash=sha256:9cd5c03c63ae06d4f876b9844c5898d0044c7940ff7460db9f4cd984ac7862b5 \
+    --hash=sha256:a3b730ef664b2ef0e99dec01b6573b9b085c766400af363833e08ebc1e38eb2f \
+    --hash=sha256:a716e05547a39b788deaf22725490855337fc36613288aa8ae1601dc8c525553 \
+    --hash=sha256:a7ec759c4a0fc820ad5dc6a58e9c391e7b16edcb618056baedbedbb9ea3b1524 \
+    --hash=sha256:aaa6bfc2180c31a45fac35d40e3312a3d09954638ce0b2e9424a88e24d262a13 \
+    --hash=sha256:ad04cf38164d983e85f9cba2804566c0160b47086dcca4cf059f7e26c5ace8ca \
+    --hash=sha256:b2f73f0d0fce5300f23a1383d19b44d103bb113b57a69c36fd95b7c03099b181 \
+    --hash=sha256:b325f42e26659df1a0de66fdb5cde8dd48613da9c99c07d04e9fb9e254b7ee1c \
+    --hash=sha256:b51bab2c4e545dde93cb6d6bb34bf63300b7cd06716f195dd92d9255df728331 \
+    --hash=sha256:b5c3e285e0735fd8c5a26d177eca8b52512cdd8687ca86ec77a0c66e9c510182 \
+    --hash=sha256:b73b493af9e947caed75d329676b1b801d673b17481962823a3e55fe529c8b8b \
+    --hash=sha256:b9d85a02e77ee8ea6d9e3fd5d515bcc3d798d9c1ea54817e5feb97a9bc5d52fe \
+    --hash=sha256:bdcfc88347fd981e53c33d832ce4d3e981a0d696b712fbcb45dcc1a43fe65c65 \
+    --hash=sha256:c594c0abe69d9d6099f4ece17763d53072f65ba60b372d8ba6de8695ce6ee39e \
+    --hash=sha256:c8a9befb0c0369f0cf5c1b94178d0d78f66d9cebb9265b36be6e4f66236076b8 \
+    --hash=sha256:cd174b90db68c3bcca273e9391934a25d76929d727dc75224bf244446b28b03b \
+    --hash=sha256:d5576415f3d76290b160aa093ff968f8bf6de7d681e16e463a0134106b506f49 \
+    --hash=sha256:d654d045adafdcc6c100e8e911508a2eedbd2a1b5f93f930ba13ea67d7704ee9 \
+    --hash=sha256:d92e339c69b585e7b1d857308ad3ca1636b899e4557897ccd91bb9e4a56c965b \
+    --hash=sha256:da3b6987a0bc3e6d0f721b42c7a0198ef897ae50579547b0345f7f02486898f5 \
+    --hash=sha256:dd26b396bc3a1e85f4acebeadbf627fa6117b97f4c10b177d5779577c6607744 \
+    --hash=sha256:de7c1ddb80fa7a3ab045266dca169004b93f284756ad198306533b792774f10a \
+    --hash=sha256:df3ab5e078cab19f7eaeef1d5f063103e1ebf8c26d059767b26a6a0ad8b250a3 \
+    --hash=sha256:e0155a8f079c688c2ccaea05de1ad69877995c547ba3d3612c1c336edc12a3a5 \
+    --hash=sha256:e10c14535abc7ddf3fd024aa36563cd8ab5d2bb6234a5d22c77c30e30fa4fb2b \
+    --hash=sha256:e4396b55a364a03ff7e71a34828c3ed0c506814dd1f50e16ebed3fc447d5188e \
+    --hash=sha256:e5589225c2da4bb732c9c370c5961c39a6db72cf69fb2a28868a5413ed7f39e6 \
+    --hash=sha256:e6576cdc36d5a09b0c1a3d81e13a45d41a6763188f9eaae2da2839e8a4240bce \
+    --hash=sha256:e6850ae33529d1e43791b30575070670070d5fe007c37f5d06aebc1dd152ab3f \
+    --hash=sha256:e9afd97339fc5a20f0542c971f90f3ca97e73d3050cdc488d540b63fae45329a \
+    --hash=sha256:ead50635fb56577c07eff3e557dac39533e0fe603000684eea2af3ed1ad8f941 \
+    --hash=sha256:ed1336a2a6e5c427f419da0154e775834abcbc8ddd703004108121c6dd9eba9d \
+    --hash=sha256:f0c819f83e4f7b7f7463b2dc10d626a8be0c85fbc7b3db0edc098c2b16ac968e \
+    --hash=sha256:f64f01795119880023ba3ce43072283a393f0b90f52b66cc0ea1a89aa64a9ccb \
+    --hash=sha256:f87a7e52f79059f9c58f6886c262061065eb6f7554a587be7ed3aa63e6b71b34 \
+    --hash=sha256:ff835906f84451e143f31c4ce8ad73d83ef4476b944c2a2da91aec8b649570e1
+    # via -r requirements-actions.in
+iniconfig==2.1.0 \
+    --hash=sha256:3abbd2e30b36733fee78f9c7f7308f2d0050e88f0087fd25c2645f63c773e1c7 \
+    --hash=sha256:9deba5723312380e77435581c6bf4935c94cbfab9b1ed33ef8d238ea168eb760
+    # via pytest
+intelhex==2.3.0 \
+    --hash=sha256:87cc5225657524ec6361354be928adfd56bcf2a3dcc646c40f8f094c39c07db4 \
+    --hash=sha256:892b7361a719f4945237da8ccf754e9513db32f5628852785aea108dcd250093
+    # via -r requirements-actions.in
+isort==6.0.1 \
+    --hash=sha256:1cb5df28dfbc742e490c5e41bad6da41b805b0a8be7bc93cd0fb2a8a890ac450 \
+    --hash=sha256:2dc5d7f65c9678d94c88dfc29161a320eec67328bc97aad576874cb4be1e9615
+    # via pylint
+jinja2==3.1.6 \
+    --hash=sha256:0137fb05990d35f1275a587e9aee6d56da821fc83491a0fb838183be43f66d6d \
+    --hash=sha256:85ece4451f492d0c13c5dd7c13a64681a86afae63a5f347908daf103ce6d2f67
+    # via
+    #   gcovr
+    #   junit2html
+jmespath==1.0.1 \
+    --hash=sha256:02e2e4cc71b5bcab88332eebf907519190dd9e6e82107fa7f83b1003a6252980 \
+    --hash=sha256:90261b206d6defd58fdd5e85f478bf633a2901798906be2ad389150c5c60edbe
+    # via botocore
+junit2html==31.0.2 \
+    --hash=sha256:c7fd1f253d423f0df031d0cee8ef7d4d98d9f8bf6383a2d40dca639686814866
+    # via -r requirements-actions.in
+junitparser==3.2.0 \
+    --hash=sha256:b05e89c27e7b74b3c563a078d6e055d95cf397444f8f689b0ca616ebda0b3c65 \
+    --hash=sha256:e14fdc0a999edfc15889b637390e8ef6ca09a49532416d3bd562857d42d4b96d
+    # via -r requirements-actions.in
+lxml==5.3.1 \
+    --hash=sha256:016b96c58e9a4528219bb563acf1aaaa8bc5452e7651004894a973f03b84ba81 \
+    --hash=sha256:05123fad495a429f123307ac6d8fd6f977b71e9a0b6d9aeeb8f80c017cb17131 \
+    --hash=sha256:057e30d0012439bc54ca427a83d458752ccda725c1c161cc283db07bcad43cf9 \
+    --hash=sha256:06a20d607a86fccab2fc15a77aa445f2bdef7b49ec0520a842c5c5afd8381576 \
+    --hash=sha256:094b28ed8a8a072b9e9e2113a81fda668d2053f2ca9f2d202c2c8c7c2d6516b1 \
+    --hash=sha256:0bcfadea3cdc68e678d2b20cb16a16716887dd00a881e16f7d806c2138b8ff0c \
+    --hash=sha256:0d6b2fa86becfa81f0a0271ccb9eb127ad45fb597733a77b92e8a35e53414914 \
+    --hash=sha256:0f2cfae0688fd01f7056a17367e3b84f37c545fb447d7282cf2c242b16262607 \
+    --hash=sha256:106b7b5d2977b339f1e97efe2778e2ab20e99994cbb0ec5e55771ed0795920c8 \
+    --hash=sha256:133f3493253a00db2c870d3740bc458ebb7d937bd0a6a4f9328373e0db305709 \
+    --hash=sha256:136bf638d92848a939fd8f0e06fcf92d9f2e4b57969d94faae27c55f3d85c05b \
+    --hash=sha256:155e1a5693cf4b55af652f5c0f78ef36596c7f680ff3ec6eb4d7d85367259b2c \
+    --hash=sha256:1637fa31ec682cd5760092adfabe86d9b718a75d43e65e211d5931809bc111e7 \
+    --hash=sha256:172d65f7c72a35a6879217bcdb4bb11bc88d55fb4879e7569f55616062d387c2 \
+    --hash=sha256:17b5d7f8acf809465086d498d62a981fa6a56d2718135bb0e4aa48c502055f5c \
+    --hash=sha256:198bb4b4dd888e8390afa4f170d4fa28467a7eaf857f1952589f16cfbb67af27 \
+    --hash=sha256:1b6f92e35e2658a5ed51c6634ceb5ddae32053182851d8cad2a5bc102a359b33 \
+    --hash=sha256:1b92fe86e04f680b848fff594a908edfa72b31bfc3499ef7433790c11d4c8cd8 \
+    --hash=sha256:1bcc211542f7af6f2dfb705f5f8b74e865592778e6cafdfd19c792c244ccce19 \
+    --hash=sha256:1c93ed3c998ea8472be98fb55aed65b5198740bfceaec07b2eba551e55b7b9ae \
+    --hash=sha256:203b1d3eaebd34277be06a3eb880050f18a4e4d60861efba4fb946e31071a295 \
+    --hash=sha256:22ec2b3c191f43ed21f9545e9df94c37c6b49a5af0a874008ddc9132d49a2d9c \
+    --hash=sha256:231cf4d140b22a923b1d0a0a4e0b4f972e5893efcdec188934cc65888fd0227b \
+    --hash=sha256:236610b77589faf462337b3305a1be91756c8abc5a45ff7ca8f245a71c5dab70 \
+    --hash=sha256:29bfc8d3d88e56ea0a27e7c4897b642706840247f59f4377d81be8f32aa0cfbf \
+    --hash=sha256:2b8969dbc8d09d9cd2ae06362c3bad27d03f433252601ef658a49bd9f2b22d79 \
+    --hash=sha256:2dd0b80ac2d8f13ffc906123a6f20b459cb50a99222d0da492360512f3e50f84 \
+    --hash=sha256:2df7ed5edeb6bd5590914cd61df76eb6cce9d590ed04ec7c183cf5509f73530d \
+    --hash=sha256:2e4a570f6a99e96c457f7bec5ad459c9c420ee80b99eb04cbfcfe3fc18ec6423 \
+    --hash=sha256:2f1be45d4c15f237209bbf123a0e05b5d630c8717c42f59f31ea9eae2ad89394 \
+    --hash=sha256:2f23cf50eccb3255b6e913188291af0150d89dab44137a69e14e4dcb7be981f1 \
+    --hash=sha256:3031e4c16b59424e8d78522c69b062d301d951dc55ad8685736c3335a97fc270 \
+    --hash=sha256:33e06717c00c788ab4e79bc4726ecc50c54b9bfb55355eae21473c145d83c2d2 \
+    --hash=sha256:364de8f57d6eda0c16dcfb999af902da31396949efa0e583e12675d09709881b \
+    --hash=sha256:3715cdf0dd31b836433af9ee9197af10e3df41d273c19bb249230043667a5dfd \
+    --hash=sha256:3bb8149840daf2c3f97cebf00e4ed4a65a0baff888bf2605a8d0135ff5cf764e \
+    --hash=sha256:3c3c8b55c7fc7b7e8877b9366568cc73d68b82da7fe33d8b98527b73857a225f \
+    --hash=sha256:3d68eeef7b4d08a25e51897dac29bcb62aba830e9ac6c4e3297ee7c6a0cf6439 \
+    --hash=sha256:3dddf0fb832486cc1ea71d189cb92eb887826e8deebe128884e15020bb6e3f61 \
+    --hash=sha256:3edbb9c9130bac05d8c3fe150c51c337a471cc7fdb6d2a0a7d3a88e88a829314 \
+    --hash=sha256:3effe081b3135237da6e4c4530ff2a868d3f80be0bda027e118a5971285d42d0 \
+    --hash=sha256:422c179022ecdedbe58b0e242607198580804253da220e9454ffe848daa1cfd2 \
+    --hash=sha256:42978a68d3825eaac55399eb37a4d52012a205c0c6262199b8b44fcc6fd686e8 \
+    --hash=sha256:4399b4226c4785575fb20998dc571bc48125dc92c367ce2602d0d70e0c455eb0 \
+    --hash=sha256:45fbb70ccbc8683f2fb58bea89498a7274af1d9ec7995e9f4af5604e028233fc \
+    --hash=sha256:4867361c049761a56bd21de507cab2c2a608c55102311d142ade7dab67b34f32 \
+    --hash=sha256:48fd46bf7155def2e15287c6f2b133a2f78e2d22cdf55647269977b873c65499 \
+    --hash=sha256:4b0d5cdba1b655d5b18042ac9c9ff50bda33568eb80feaaca4fc237b9c4fbfde \
+    --hash=sha256:4df0ec814b50275ad6a99bc82a38b59f90e10e47714ac9871e1b223895825468 \
+    --hash=sha256:4e52e1b148867b01c05e21837586ee307a01e793b94072d7c7b91d2c2da02ffe \
+    --hash=sha256:514fe78fc4b87e7a7601c92492210b20a1b0c6ab20e71e81307d9c2e377c64de \
+    --hash=sha256:524ccfded8989a6595dbdda80d779fb977dbc9a7bc458864fc9a0c2fc15dc877 \
+    --hash=sha256:528f3a0498a8edc69af0559bdcf8a9f5a8bf7c00051a6ef3141fdcf27017bbf5 \
+    --hash=sha256:52d82b0d436edd6a1d22d94a344b9a58abd6c68c357ed44f22d4ba8179b37629 \
+    --hash=sha256:5412500e0dc5481b1ee9cf6b38bb3b473f6e411eb62b83dc9b62699c3b7b79f7 \
+    --hash=sha256:585c4dc429deebc4307187d2b71ebe914843185ae16a4d582ee030e6cfbb4d8a \
+    --hash=sha256:5865b270b420eda7b68928d70bb517ccbe045e53b1a428129bb44372bf3d7dd5 \
+    --hash=sha256:5881aaa4bf3a2d086c5f20371d3a5856199a0d8ac72dd8d0dbd7a2ecfc26ab73 \
+    --hash=sha256:5885bc586f1edb48e5d68e7a4b4757b5feb2a496b64f462b4d65950f5af3364f \
+    --hash=sha256:5a11b16a33656ffc43c92a5343a28dc71eefe460bcc2a4923a96f292692709f6 \
+    --hash=sha256:5a997b784a639e05b9d4053ef3b20c7e447ea80814a762f25b8ed5a89d261eac \
+    --hash=sha256:5be8f5e4044146a69c96077c7e08f0709c13a314aa5315981185c1f00235fe65 \
+    --hash=sha256:63d57fc94eb0bbb4735e45517afc21ef262991d8758a8f2f05dd6e4174944519 \
+    --hash=sha256:673b9d8e780f455091200bba8534d5f4f465944cbdd61f31dc832d70e29064a5 \
+    --hash=sha256:67d2f8ad9dcc3a9e826bdc7802ed541a44e124c29b7d95a679eeb58c1c14ade8 \
+    --hash=sha256:67f5e80adf0aafc7b5454f2c1cb0cde920c9b1f2cbd0485f07cc1d0497c35c5d \
+    --hash=sha256:68018c4c67d7e89951a91fbd371e2e34cd8cfc71f0bb43b5332db38497025d51 \
+    --hash=sha256:6c4dd3bfd0c82400060896717dd261137398edb7e524527438c54a8c34f736bf \
+    --hash=sha256:71f31eda4e370f46af42fc9f264fafa1b09f46ba07bdbee98f25689a04b81c20 \
+    --hash=sha256:7512b4d0fc5339d5abbb14d1843f70499cab90d0b864f790e73f780f041615d7 \
+    --hash=sha256:75fa3d6946d317ffc7016a6fcc44f42db6d514b7fdb8b4b28cbe058303cb6e53 \
+    --hash=sha256:779e851fd0e19795ccc8a9bb4d705d6baa0ef475329fe44a13cf1e962f18ff1e \
+    --hash=sha256:796520afa499732191e39fc95b56a3b07f95256f2d22b1c26e217fb69a9db5b5 \
+    --hash=sha256:7aae7a3d63b935babfdc6864b31196afd5145878ddd22f5200729006366bc4d5 \
+    --hash=sha256:7b82e67c5feb682dbb559c3e6b78355f234943053af61606af126df2183b9ef9 \
+    --hash=sha256:7c0536bd9178f754b277a3e53f90f9c9454a3bd108b1531ffff720e082d824f2 \
+    --hash=sha256:7eda194dd46e40ec745bf76795a7cccb02a6a41f445ad49d3cf66518b0bd9cff \
+    --hash=sha256:82a4bb10b0beef1434fb23a09f001ab5ca87895596b4581fd53f1e5145a8934a \
+    --hash=sha256:85c4f11be9cf08917ac2a5a8b6e1ef63b2f8e3799cec194417e76826e5f1de9c \
+    --hash=sha256:88b72eb7222d918c967202024812c2bfb4048deeb69ca328363fb8e15254c549 \
+    --hash=sha256:89934f9f791566e54c1d92cdc8f8fd0009447a5ecdb1ec6b810d5f8c4955f6be \
+    --hash=sha256:8b1942b3e4ed9ed551ed3083a2e6e0772de1e5e3aca872d955e2e86385fb7ff9 \
+    --hash=sha256:8ffb141361108e864ab5f1813f66e4e1164181227f9b1f105b042729b6c15125 \
+    --hash=sha256:8fffc08de02071c37865a155e5ea5fce0282e1546fd5bde7f6149fcaa32558ac \
+    --hash=sha256:91fb6a43d72b4f8863d21f347a9163eecbf36e76e2f51068d59cd004c506f332 \
+    --hash=sha256:928e75a7200a4c09e6efc7482a1337919cc61fe1ba289f297827a5b76d8969c2 \
+    --hash=sha256:96eef5b9f336f623ffc555ab47a775495e7e8846dde88de5f941e2906453a1ce \
+    --hash=sha256:a0611da6b07dd3720f492db1b463a4d1175b096b49438761cc9f35f0d9eaaef5 \
+    --hash=sha256:a091026c3bf7519ab1e64655a3f52a59ad4a4e019a6f830c24d6430695b1cf6a \
+    --hash=sha256:a22f66270bd6d0804b02cd49dae2b33d4341015545d17f8426f2c4e22f557a23 \
+    --hash=sha256:a243132767150a44e6a93cd1dde41010036e1cbc63cc3e9fe1712b277d926ce3 \
+    --hash=sha256:a31fa7536ec1fb7155a0cd3a4e3d956c835ad0a43e3610ca32384d01f079ea1c \
+    --hash=sha256:a364e8e944d92dcbf33b6b494d4e0fb3499dcc3bd9485beb701aa4b4201fa414 \
+    --hash=sha256:a4058f16cee694577f7e4dd410263cd0ef75644b43802a689c2b3c2a7e69453b \
+    --hash=sha256:a4b382e0e636ed54cd278791d93fe2c4f370772743f02bcbe431a160089025c9 \
+    --hash=sha256:a83d3adea1e0ee36dac34627f78ddd7f093bb9cfc0a8e97f1572a949b695cb98 \
+    --hash=sha256:a8ade0363f776f87f982572c2860cc43c65ace208db49c76df0a21dde4ddd16e \
+    --hash=sha256:aa59974880ab5ad8ef3afaa26f9bda148c5f39e06b11a8ada4660ecc9fb2feb3 \
+    --hash=sha256:aa826340a609d0c954ba52fd831f0fba2a4165659ab0ee1a15e4aac21f302406 \
+    --hash=sha256:aaca5a812f050ab55426c32177091130b1e49329b3f002a32934cd0245571307 \
+    --hash=sha256:ae82fce1d964f065c32c9517309f0c7be588772352d2f40b1574a214bd6e6098 \
+    --hash=sha256:aed57b541b589fa05ac248f4cb1c46cbb432ab82cbd467d1c4f6a2bdc18aecf9 \
+    --hash=sha256:afa578b6524ff85fb365f454cf61683771d0170470c48ad9d170c48075f86725 \
+    --hash=sha256:b0884e3f22d87c30694e625b1e62e6f30d39782c806287450d9dc2fdf07692fd \
+    --hash=sha256:b2aca14c235c7a08558fe0a4786a1a05873a01e86b474dfa8f6df49101853a4e \
+    --hash=sha256:b450d7cabcd49aa7ab46a3c6aa3ac7e1593600a1a0605ba536ec0f1b99a04322 \
+    --hash=sha256:b725e70d15906d24615201e650d5b0388b08a5187a55f119f25874d0103f90dd \
+    --hash=sha256:bfbbab9316330cf81656fed435311386610f78b6c93cc5db4bebbce8dd146675 \
+    --hash=sha256:c093c7088b40d8266f57ed71d93112bd64c6724d31f0794c1e52cc4857c28e0e \
+    --hash=sha256:c2e49dc23a10a1296b04ca9db200c44d3eb32c8d8ec532e8c1fd24792276522a \
+    --hash=sha256:c4393600915c308e546dc7003d74371744234e8444a28622d76fe19b98fa59d1 \
+    --hash=sha256:c5ae125276f254b01daa73e2c103363d3e99e3e10505686ac7d9d2442dd4627a \
+    --hash=sha256:c6aacf00d05b38a5069826e50ae72751cb5bc27bdc4d5746203988e429b385bb \
+    --hash=sha256:c76722b5ed4a31ba103e0dc77ab869222ec36efe1a614e42e9bcea88a36186fe \
+    --hash=sha256:c809eef167bf4a57af4b03007004896f5c60bd38dc3852fcd97a26eae3d4c9e6 \
+    --hash=sha256:c92ea6d9dd84a750b2bae72ff5e8cf5fdd13e58dda79c33e057862c29a8d5b50 \
+    --hash=sha256:cb659702a45136c743bc130760c6f137870d4df3a9e14386478b8a0511abcfca \
+    --hash=sha256:ce0930a963ff593e8bb6fda49a503911accc67dee7e5445eec972668e672a0f0 \
+    --hash=sha256:d0751528b97d2b19a388b302be2a0ee05817097bab46ff0ed76feeec24951f78 \
+    --hash=sha256:d184f85ad2bb1f261eac55cddfcf62a70dee89982c978e92b9a74a1bfef2e367 \
+    --hash=sha256:d2a3e412ce1849be34b45922bfef03df32d1410a06d1cdeb793a343c2f1fd666 \
+    --hash=sha256:d61ec60945d694df806a9aec88e8f29a27293c6e424f8ff91c80416e3c617645 \
+    --hash=sha256:db0c742aad702fd5d0c6611a73f9602f20aec2007c102630c06d7633d9c8f09a \
+    --hash=sha256:db4743e30d6f5f92b6d2b7c86b3ad250e0bad8dee4b7ad8a0c44bfb276af89a3 \
+    --hash=sha256:dbf7bebc2275016cddf3c997bf8a0f7044160714c64a9b83975670a04e6d2252 \
+    --hash=sha256:de1fc314c3ad6bc2f6bd5b5a5b9357b8c6896333d27fdbb7049aea8bd5af2d79 \
+    --hash=sha256:df7e5edac4778127f2bf452e0721a58a1cfa4d1d9eac63bdd650535eb8543615 \
+    --hash=sha256:e220f7b3e8656ab063d2eb0cd536fafef396829cafe04cb314e734f87649058f \
+    --hash=sha256:e3c623923967f3e5961d272718655946e5322b8d058e094764180cdee7bab1af \
+    --hash=sha256:e69add9b6b7b08c60d7ff0152c7c9a6c45b4a71a919be5abde6f98f1ea16421c \
+    --hash=sha256:e8e0d177b1fe251c3b1b914ab64135475c5273c8cfd2857964b2e3bb0fe196a7 \
+    --hash=sha256:ef45f31aec9be01379fc6c10f1d9c677f032f2bac9383c827d44f620e8a88407 \
+    --hash=sha256:f1208c1c67ec9e151d78aa3435aa9b08a488b53d9cfac9b699f15255a3461ef2 \
+    --hash=sha256:f12582b8d3b4c6be1d298c49cb7ae64a3a73efaf4c2ab4e37db182e3545815ac \
+    --hash=sha256:f1de541a9893cf8a1b1db9bf0bf670a2decab42e3e82233d36a74eda7822b4c9 \
+    --hash=sha256:f4eac0584cdc3285ef2e74eee1513a6001681fd9753b259e8159421ed28a72e5 \
+    --hash=sha256:f7b64fcd670bca8800bc10ced36620c6bbb321e7bc1214b9c0c0df269c1dddc2 \
+    --hash=sha256:fb7c61d4be18e930f75948705e9718618862e6fc2ed0d7159b2262be73f167a2
+    # via
+    #   -r requirements-actions.in
+    #   gcovr
+markupsafe==3.0.2 \
+    --hash=sha256:0bff5e0ae4ef2e1ae4fdf2dfd5b76c75e5c2fa4132d05fc1b0dabcd20c7e28c4 \
+    --hash=sha256:0f4ca02bea9a23221c0182836703cbf8930c5e9454bacce27e767509fa286a30 \
+    --hash=sha256:1225beacc926f536dc82e45f8a4d68502949dc67eea90eab715dea3a21c1b5f0 \
+    --hash=sha256:131a3c7689c85f5ad20f9f6fb1b866f402c445b220c19fe4308c0b147ccd2ad9 \
+    --hash=sha256:15ab75ef81add55874e7ab7055e9c397312385bd9ced94920f2802310c930396 \
+    --hash=sha256:1a9d3f5f0901fdec14d8d2f66ef7d035f2157240a433441719ac9a3fba440b13 \
+    --hash=sha256:1c99d261bd2d5f6b59325c92c73df481e05e57f19837bdca8413b9eac4bd8028 \
+    --hash=sha256:1e084f686b92e5b83186b07e8a17fc09e38fff551f3602b249881fec658d3eca \
+    --hash=sha256:2181e67807fc2fa785d0592dc2d6206c019b9502410671cc905d132a92866557 \
+    --hash=sha256:2cb8438c3cbb25e220c2ab33bb226559e7afb3baec11c4f218ffa7308603c832 \
+    --hash=sha256:3169b1eefae027567d1ce6ee7cae382c57fe26e82775f460f0b2778beaad66c0 \
+    --hash=sha256:3809ede931876f5b2ec92eef964286840ed3540dadf803dd570c3b7e13141a3b \
+    --hash=sha256:38a9ef736c01fccdd6600705b09dc574584b89bea478200c5fbf112a6b0d5579 \
+    --hash=sha256:3d79d162e7be8f996986c064d1c7c817f6df3a77fe3d6859f6f9e7be4b8c213a \
+    --hash=sha256:444dcda765c8a838eaae23112db52f1efaf750daddb2d9ca300bcae1039adc5c \
+    --hash=sha256:48032821bbdf20f5799ff537c7ac3d1fba0ba032cfc06194faffa8cda8b560ff \
+    --hash=sha256:4aa4e5faecf353ed117801a068ebab7b7e09ffb6e1d5e412dc852e0da018126c \
+    --hash=sha256:52305740fe773d09cffb16f8ed0427942901f00adedac82ec8b67752f58a1b22 \
+    --hash=sha256:569511d3b58c8791ab4c2e1285575265991e6d8f8700c7be0e88f86cb0672094 \
+    --hash=sha256:57cb5a3cf367aeb1d316576250f65edec5bb3be939e9247ae594b4bcbc317dfb \
+    --hash=sha256:5b02fb34468b6aaa40dfc198d813a641e3a63b98c2b05a16b9f80b7ec314185e \
+    --hash=sha256:6381026f158fdb7c72a168278597a5e3a5222e83ea18f543112b2662a9b699c5 \
+    --hash=sha256:6af100e168aa82a50e186c82875a5893c5597a0c1ccdb0d8b40240b1f28b969a \
+    --hash=sha256:6c89876f41da747c8d3677a2b540fb32ef5715f97b66eeb0c6b66f5e3ef6f59d \
+    --hash=sha256:6e296a513ca3d94054c2c881cc913116e90fd030ad1c656b3869762b754f5f8a \
+    --hash=sha256:70a87b411535ccad5ef2f1df5136506a10775d267e197e4cf531ced10537bd6b \
+    --hash=sha256:7e94c425039cde14257288fd61dcfb01963e658efbc0ff54f5306b06054700f8 \
+    --hash=sha256:846ade7b71e3536c4e56b386c2a47adf5741d2d8b94ec9dc3e92e5e1ee1e2225 \
+    --hash=sha256:88416bd1e65dcea10bc7569faacb2c20ce071dd1f87539ca2ab364bf6231393c \
+    --hash=sha256:88b49a3b9ff31e19998750c38e030fc7bb937398b1f78cfa599aaef92d693144 \
+    --hash=sha256:8c4e8c3ce11e1f92f6536ff07154f9d49677ebaaafc32db9db4620bc11ed480f \
+    --hash=sha256:8e06879fc22a25ca47312fbe7c8264eb0b662f6db27cb2d3bbbc74b1df4b9b87 \
+    --hash=sha256:9025b4018f3a1314059769c7bf15441064b2207cb3f065e6ea1e7359cb46db9d \
+    --hash=sha256:93335ca3812df2f366e80509ae119189886b0f3c2b81325d39efdb84a1e2ae93 \
+    --hash=sha256:9778bd8ab0a994ebf6f84c2b949e65736d5575320a17ae8984a77fab08db94cf \
+    --hash=sha256:9e2d922824181480953426608b81967de705c3cef4d1af983af849d7bd619158 \
+    --hash=sha256:a123e330ef0853c6e822384873bef7507557d8e4a082961e1defa947aa59ba84 \
+    --hash=sha256:a904af0a6162c73e3edcb969eeeb53a63ceeb5d8cf642fade7d39e7963a22ddb \
+    --hash=sha256:ad10d3ded218f1039f11a75f8091880239651b52e9bb592ca27de44eed242a48 \
+    --hash=sha256:b424c77b206d63d500bcb69fa55ed8d0e6a3774056bdc4839fc9298a7edca171 \
+    --hash=sha256:b5a6b3ada725cea8a5e634536b1b01c30bcdcd7f9c6fff4151548d5bf6b3a36c \
+    --hash=sha256:ba8062ed2cf21c07a9e295d5b8a2a5ce678b913b45fdf68c32d95d6c1291e0b6 \
+    --hash=sha256:ba9527cdd4c926ed0760bc301f6728ef34d841f405abf9d4f959c478421e4efd \
+    --hash=sha256:bbcb445fa71794da8f178f0f6d66789a28d7319071af7a496d4d507ed566270d \
+    --hash=sha256:bcf3e58998965654fdaff38e58584d8937aa3096ab5354d493c77d1fdd66d7a1 \
+    --hash=sha256:c0ef13eaeee5b615fb07c9a7dadb38eac06a0608b41570d8ade51c56539e509d \
+    --hash=sha256:cabc348d87e913db6ab4aa100f01b08f481097838bdddf7c7a84b7575b7309ca \
+    --hash=sha256:cdb82a876c47801bb54a690c5ae105a46b392ac6099881cdfb9f6e95e4014c6a \
+    --hash=sha256:cfad01eed2c2e0c01fd0ecd2ef42c492f7f93902e39a42fc9ee1692961443a29 \
+    --hash=sha256:d16a81a06776313e817c951135cf7340a3e91e8c1ff2fac444cfd75fffa04afe \
+    --hash=sha256:d8213e09c917a951de9d09ecee036d5c7d36cb6cb7dbaece4c71a60d79fb9798 \
+    --hash=sha256:e07c3764494e3776c602c1e78e298937c3315ccc9043ead7e685b7f2b8d47b3c \
+    --hash=sha256:e17c96c14e19278594aa4841ec148115f9c7615a47382ecb6b82bd8fea3ab0c8 \
+    --hash=sha256:e444a31f8db13eb18ada366ab3cf45fd4b31e4db1236a4448f68778c1d1a5a2f \
+    --hash=sha256:e6a2a455bd412959b57a172ce6328d2dd1f01cb2135efda2e4576e8a23fa3b0f \
+    --hash=sha256:eaa0a10b7f72326f1372a713e73c3f739b524b3af41feb43e4921cb529f5929a \
+    --hash=sha256:eb7972a85c54febfb25b5c4b4f3af4dcc731994c7da0d8a0b4a6eb0640e1d178 \
+    --hash=sha256:ee55d3edf80167e48ea11a923c7386f4669df67d7994554387f84e7d8b0a2bf0 \
+    --hash=sha256:f3818cb119498c0678015754eba762e0d61e5b52d34c8b13d770f0719f7b1d79 \
+    --hash=sha256:f8b3d067f2e40fe93e1ccdd6b2e1d16c43140e76f02fb1319a05cf2b79d99430 \
+    --hash=sha256:fcabf5ff6eea076f859677f5f0b6b5c1a51e70a376b0579e0eadef8db48c6b50
+    # via jinja2
+mccabe==0.7.0 \
+    --hash=sha256:348e0240c33b60bbdf4e523192ef919f28cb2c3d7d5c7794f74009290f236325 \
+    --hash=sha256:6c2d30ab6be0e4a46919781807b4f0d834ebdd6c6e3dca0bda5a15f863427b6e
+    # via pylint
+mock==5.2.0 \
+    --hash=sha256:4e460e818629b4b173f32d08bf30d3af8123afbb8e04bb5707a1fd4799e503f0 \
+    --hash=sha256:7ba87f72ca0e915175596069dbbcc7c75af7b5e9b9bc107ad6349ede0819982f
+    # via -r requirements-actions.in
+msgpack==1.1.0 ; sys_platform != 'win32' \
+    --hash=sha256:06f5fd2f6bb2a7914922d935d3b8bb4a7fff3a9a91cfce6d06c13bc42bec975b \
+    --hash=sha256:071603e2f0771c45ad9bc65719291c568d4edf120b44eb36324dcb02a13bfddf \
+    --hash=sha256:0907e1a7119b337971a689153665764adc34e89175f9a34793307d9def08e6ca \
+    --hash=sha256:0f92a83b84e7c0749e3f12821949d79485971f087604178026085f60ce109330 \
+    --hash=sha256:115a7af8ee9e8cddc10f87636767857e7e3717b7a2e97379dc2054712693e90f \
+    --hash=sha256:13599f8829cfbe0158f6456374e9eea9f44eee08076291771d8ae93eda56607f \
+    --hash=sha256:17fb65dd0bec285907f68b15734a993ad3fc94332b5bb21b0435846228de1f39 \
+    --hash=sha256:2137773500afa5494a61b1208619e3871f75f27b03bcfca7b3a7023284140247 \
+    --hash=sha256:3180065ec2abbe13a4ad37688b61b99d7f9e012a535b930e0e683ad6bc30155b \
+    --hash=sha256:398b713459fea610861c8a7b62a6fec1882759f308ae0795b5413ff6a160cf3c \
+    --hash=sha256:3d364a55082fb2a7416f6c63ae383fbd903adb5a6cf78c5b96cc6316dc1cedc7 \
+    --hash=sha256:3df7e6b05571b3814361e8464f9304c42d2196808e0119f55d0d3e62cd5ea044 \
+    --hash=sha256:41c991beebf175faf352fb940bf2af9ad1fb77fd25f38d9142053914947cdbf6 \
+    --hash=sha256:42f754515e0f683f9c79210a5d1cad631ec3d06cea5172214d2176a42e67e19b \
+    --hash=sha256:452aff037287acb1d70a804ffd022b21fa2bb7c46bee884dbc864cc9024128a0 \
+    --hash=sha256:4676e5be1b472909b2ee6356ff425ebedf5142427842aa06b4dfd5117d1ca8a2 \
+    --hash=sha256:46c34e99110762a76e3911fc923222472c9d681f1094096ac4102c18319e6468 \
+    --hash=sha256:471e27a5787a2e3f974ba023f9e265a8c7cfd373632247deb225617e3100a3c7 \
+    --hash=sha256:4a1964df7b81285d00a84da4e70cb1383f2e665e0f1f2a7027e683956d04b734 \
+    --hash=sha256:4b51405e36e075193bc051315dbf29168d6141ae2500ba8cd80a522964e31434 \
+    --hash=sha256:4d1b7ff2d6146e16e8bd665ac726a89c74163ef8cd39fa8c1087d4e52d3a2325 \
+    --hash=sha256:53258eeb7a80fc46f62fd59c876957a2d0e15e6449a9e71842b6d24419d88ca1 \
+    --hash=sha256:534480ee5690ab3cbed89d4c8971a5c631b69a8c0883ecfea96c19118510c846 \
+    --hash=sha256:58638690ebd0a06427c5fe1a227bb6b8b9fdc2bd07701bec13c2335c82131a88 \
+    --hash=sha256:58dfc47f8b102da61e8949708b3eafc3504509a5728f8b4ddef84bd9e16ad420 \
+    --hash=sha256:59caf6a4ed0d164055ccff8fe31eddc0ebc07cf7326a2aaa0dbf7a4001cd823e \
+    --hash=sha256:5dbad74103df937e1325cc4bfeaf57713be0b4f15e1c2da43ccdd836393e2ea2 \
+    --hash=sha256:5e1da8f11a3dd397f0a32c76165cf0c4eb95b31013a94f6ecc0b280c05c91b59 \
+    --hash=sha256:646afc8102935a388ffc3914b336d22d1c2d6209c773f3eb5dd4d6d3b6f8c1cb \
+    --hash=sha256:64fc9068d701233effd61b19efb1485587560b66fe57b3e50d29c5d78e7fef68 \
+    --hash=sha256:65553c9b6da8166e819a6aa90ad15288599b340f91d18f60b2061f402b9a4915 \
+    --hash=sha256:685ec345eefc757a7c8af44a3032734a739f8c45d1b0ac45efc5d8977aa4720f \
+    --hash=sha256:6ad622bf7756d5a497d5b6836e7fc3752e2dd6f4c648e24b1803f6048596f701 \
+    --hash=sha256:73322a6cc57fcee3c0c57c4463d828e9428275fb85a27aa2aa1a92fdc42afd7b \
+    --hash=sha256:74bed8f63f8f14d75eec75cf3d04ad581da6b914001b474a5d3cd3372c8cc27d \
+    --hash=sha256:79ec007767b9b56860e0372085f8504db5d06bd6a327a335449508bbee9648fa \
+    --hash=sha256:7a946a8992941fea80ed4beae6bff74ffd7ee129a90b4dd5cf9c476a30e9708d \
+    --hash=sha256:7ad442d527a7e358a469faf43fda45aaf4ac3249c8310a82f0ccff9164e5dccd \
+    --hash=sha256:7c9a35ce2c2573bada929e0b7b3576de647b0defbd25f5139dcdaba0ae35a4cc \
+    --hash=sha256:7e7b853bbc44fb03fbdba34feb4bd414322180135e2cb5164f20ce1c9795ee48 \
+    --hash=sha256:879a7b7b0ad82481c52d3c7eb99bf6f0645dbdec5134a4bddbd16f3506947feb \
+    --hash=sha256:8a706d1e74dd3dea05cb54580d9bd8b2880e9264856ce5068027eed09680aa74 \
+    --hash=sha256:8a84efb768fb968381e525eeeb3d92857e4985aacc39f3c47ffd00eb4509315b \
+    --hash=sha256:8cf9e8c3a2153934a23ac160cc4cba0ec035f6867c8013cc6077a79823370346 \
+    --hash=sha256:8da4bf6d54ceed70e8861f833f83ce0814a2b72102e890cbdfe4b34764cdd66e \
+    --hash=sha256:8e59bca908d9ca0de3dc8684f21ebf9a690fe47b6be93236eb40b99af28b6ea6 \
+    --hash=sha256:914571a2a5b4e7606997e169f64ce53a8b1e06f2cf2c3a7273aa106236d43dd5 \
+    --hash=sha256:a51abd48c6d8ac89e0cfd4fe177c61481aca2d5e7ba42044fd218cfd8ea9899f \
+    --hash=sha256:a52a1f3a5af7ba1c9ace055b659189f6c669cf3657095b50f9602af3a3ba0fe5 \
+    --hash=sha256:ad33e8400e4ec17ba782f7b9cf868977d867ed784a1f5f2ab46e7ba53b6e1e1b \
+    --hash=sha256:b4c01941fd2ff87c2a934ee6055bda4ed353a7846b8d4f341c428109e9fcde8c \
+    --hash=sha256:bce7d9e614a04d0883af0b3d4d501171fbfca038f12c77fa838d9f198147a23f \
+    --hash=sha256:c40ffa9a15d74e05ba1fe2681ea33b9caffd886675412612d93ab17b58ea2fec \
+    --hash=sha256:c5a91481a3cc573ac8c0d9aace09345d989dc4a0202b7fcb312c88c26d4e71a8 \
+    --hash=sha256:c921af52214dcbb75e6bdf6a661b23c3e6417f00c603dd2070bccb5c3ef499f5 \
+    --hash=sha256:d46cf9e3705ea9485687aa4001a76e44748b609d260af21c4ceea7f2212a501d \
+    --hash=sha256:d8ce0b22b890be5d252de90d0e0d119f363012027cf256185fc3d474c44b1b9e \
+    --hash=sha256:dd432ccc2c72b914e4cb77afce64aab761c1137cc698be3984eee260bcb2896e \
+    --hash=sha256:e0856a2b7e8dcb874be44fea031d22e5b3a19121be92a1e098f46068a11b0870 \
+    --hash=sha256:e1f3c3d21f7cf67bcf2da8e494d30a75e4cf60041d98b3f79875afb5b96f3a3f \
+    --hash=sha256:f1ba6136e650898082d9d5a5217d5906d1e138024f836ff48691784bbe1adf96 \
+    --hash=sha256:f3e9b4936df53b970513eac1758f3882c88658a220b58dcc1e39606dccaaf01c \
+    --hash=sha256:f80bc7d47f76089633763f952e67f8214cb7b3ee6bfa489b3cb6a84cfac114cd \
+    --hash=sha256:fd2906780f25c8ed5d7b323379f6138524ba793428db5d0e9d226d3fa6aa1788
+    # via python-can
+mypy==1.15.0 \
+    --hash=sha256:1124a18bc11a6a62887e3e137f37f53fbae476dc36c185d549d4f837a2a6a14e \
+    --hash=sha256:171a9ca9a40cd1843abeca0e405bc1940cd9b305eaeea2dda769ba096932bb22 \
+    --hash=sha256:1905f494bfd7d85a23a88c5d97840888a7bd516545fc5aaedff0267e0bb54e2f \
+    --hash=sha256:1fbb8da62dc352133d7d7ca90ed2fb0e9d42bb1a32724c287d3c76c58cbaa9c2 \
+    --hash=sha256:2922d42e16d6de288022e5ca321cd0618b238cfc5570e0263e5ba0a77dbef56f \
+    --hash=sha256:2e2c2e6d3593f6451b18588848e66260ff62ccca522dd231cd4dd59b0160668b \
+    --hash=sha256:2ee2d57e01a7c35de00f4634ba1bbf015185b219e4dc5909e281016df43f5ee5 \
+    --hash=sha256:2f2147ab812b75e5b5499b01ade1f4a81489a147c01585cda36019102538615f \
+    --hash=sha256:404534629d51d3efea5c800ee7c42b72a6554d6c400e6a79eafe15d11341fd43 \
+    --hash=sha256:5469affef548bd1895d86d3bf10ce2b44e33d86923c29e4d675b3e323437ea3e \
+    --hash=sha256:5a95fb17c13e29d2d5195869262f8125dfdb5c134dc8d9a9d0aecf7525b10c2c \
+    --hash=sha256:6983aae8b2f653e098edb77f893f7b6aca69f6cffb19b2cc7443f23cce5f4828 \
+    --hash=sha256:712e962a6357634fef20412699a3655c610110e01cdaa6180acec7fc9f8513ba \
+    --hash=sha256:8023ff13985661b50a5928fc7a5ca15f3d1affb41e5f0a9952cb68ef090b31ee \
+    --hash=sha256:811aeccadfb730024c5d3e326b2fbe9249bb7413553f15499a4050f7c30e801d \
+    --hash=sha256:8f8722560a14cde92fdb1e31597760dc35f9f5524cce17836c0d22841830fd5b \
+    --hash=sha256:93faf3fdb04768d44bf28693293f3904bbb555d076b781ad2530214ee53e3445 \
+    --hash=sha256:973500e0774b85d9689715feeffcc980193086551110fd678ebe1f4342fb7c5e \
+    --hash=sha256:979e4e1a006511dacf628e36fadfecbcc0160a8af6ca7dad2f5025529e082c13 \
+    --hash=sha256:98b7b9b9aedb65fe628c62a6dc57f6d5088ef2dfca37903a7d9ee374d03acca5 \
+    --hash=sha256:aea39e0583d05124836ea645f412e88a5c7d0fd77a6d694b60d9b6b2d9f184fd \
+    --hash=sha256:b9378e2c00146c44793c98b8d5a61039a048e31f429fb0eb546d93f4b000bedf \
+    --hash=sha256:baefc32840a9f00babd83251560e0ae1573e2f9d1b067719479bfb0e987c6357 \
+    --hash=sha256:be68172e9fd9ad8fb876c6389f16d1c1b5f100ffa779f77b1fb2176fcc9ab95b \
+    --hash=sha256:c43a7682e24b4f576d93072216bf56eeff70d9140241f9edec0c104d0c515036 \
+    --hash=sha256:c4bb0e1bd29f7d34efcccd71cf733580191e9a264a2202b0239da95984c5b559 \
+    --hash=sha256:c7be1e46525adfa0d97681432ee9fcd61a3964c2446795714699a998d193f1a3 \
+    --hash=sha256:c9817fa23833ff189db061e6d2eff49b2f3b6ed9856b4a0a73046e41932d744f \
+    --hash=sha256:ce436f4c6d218a070048ed6a44c0bbb10cd2cc5e272b29e7845f6a2f57ee4464 \
+    --hash=sha256:d10d994b41fb3497719bbf866f227b3489048ea4bbbb5015357db306249f7980 \
+    --hash=sha256:e601a7fa172c2131bff456bb3ee08a88360760d0d2f8cbd7a75a65497e2df078 \
+    --hash=sha256:f95579473af29ab73a10bada2f9722856792a36ec5af5399b653aa28360290a5
+    # via -r requirements-actions.in
+mypy-extensions==1.0.0 \
+    --hash=sha256:4392f6c0eb8a5668a69e23d168ffa70f0be9ccfd32b5cc2d26a34ae5b844552d \
+    --hash=sha256:75dbf8955dc00442a438fc4d0666508a9a97b6bd41aa2f0ffe9d2f2725af0782
+    # via mypy
+natsort==8.4.0 \
+    --hash=sha256:45312c4a0e5507593da193dedd04abb1469253b601ecaf63445ad80f0a1ea581 \
+    --hash=sha256:4732914fb471f56b5cce04d7bae6f164a592c7712e1c85f9ef585e197299521c
+    # via -r requirements-actions.in
+packaging==24.2 \
+    --hash=sha256:09abb1bccd265c01f4a3aa3f7a7db064b36514d2cba19a2f694fe6150451a759 \
+    --hash=sha256:c228a6dc5e932d346bc5739379109d49e8853dd8223571c7c5b55260edc0b97f
+    # via
+    #   pyproject-api
+    #   pytest
+    #   python-can
+    #   tox
+    #   west
+pathspec==0.12.1 \
+    --hash=sha256:a0d503e138a4c123b27490a4f7beda6a01c6f288df0e4a8b79c7eb0dc7b4cc08 \
+    --hash=sha256:a482d51503a1ab33b1c67a6c3813a26953dbdc71c31dacaef9a838c4e29f5712
+    # via yamllint
+platformdirs==4.3.7 \
+    --hash=sha256:a03875334331946f13c549dbd8f4bac7a13a50a895a0eb1e8c6a8ace80d40a94 \
+    --hash=sha256:eb437d586b6a0986388f0d6f74aa0cde27b48d0e3d66843640bfb6bdcdb6e351
+    # via
+    #   pylint
+    #   tox
+    #   virtualenv
+pluggy==1.5.0 \
+    --hash=sha256:2cffa88e94fdc978c4c574f15f9e59b7f4201d439195c3715ca9e2486f1d0cf1 \
+    --hash=sha256:44e1ad92c8ca002de6377e165f3e0f1be63266ab4d554740532335b9d75ea669
+    # via
+    #   pytest
+    #   tox
+ply==3.11 \
+    --hash=sha256:00c7c1aaa88358b9c765b6d3000c6eec0ba42abca5351b095321aef446081da3 \
+    --hash=sha256:096f9b8350b65ebd2fd1346b12452efe5b9607f7482813ffca50c22722a807ce
+    # via -r requirements-actions.in
+polib==1.2.0 \
+    --hash=sha256:1c77ee1b81feb31df9bca258cbc58db1bbb32d10214b173882452c73af06d62d \
+    --hash=sha256:f3ef94aefed6e183e342a8a269ae1fc4742ba193186ad76f175938621dbfc26b
+    # via sphinx-lint
+progress==1.6 \
+    --hash=sha256:c9c86e98b5c03fa1fe11e3b67c1feda4788b8d0fe7336c2ff7d5644ccfba34cd
+    # via -r requirements-actions.in
+psutil==7.0.0 \
+    --hash=sha256:101d71dc322e3cffd7cea0650b09b3d08b8e7c4109dd6809fe452dfd00e58b25 \
+    --hash=sha256:1e744154a6580bc968a0195fd25e80432d3afec619daf145b9e5ba16cc1d688e \
+    --hash=sha256:1fcee592b4c6f146991ca55919ea3d1f8926497a713ed7faaf8225e174581e91 \
+    --hash=sha256:39db632f6bb862eeccf56660871433e111b6ea58f2caea825571951d4b6aa3da \
+    --hash=sha256:4b1388a4f6875d7e2aff5c4ca1cc16c545ed41dd8bb596cefea80111db353a34 \
+    --hash=sha256:4cf3d4eb1aa9b348dec30105c55cd9b7d4629285735a102beb4441e38db90553 \
+    --hash=sha256:7be9c3eba38beccb6495ea33afd982a44074b78f28c434a1f51cc07fd315c456 \
+    --hash=sha256:84df4eb63e16849689f76b1ffcb36db7b8de703d1bc1fe41773db487621b6c17 \
+    --hash=sha256:a5f098451abc2828f7dc6b58d44b532b22f2088f4999a937557b603ce72b1993 \
+    --hash=sha256:ba3fcef7523064a6c9da440fc4d6bd07da93ac726b5733c29027d7dc95b39d99
+    # via -r requirements-actions.in
+pyasn1==0.6.1 \
+    --hash=sha256:0d632f46f2ba09143da3a8afe9e33fb6f92fa2320ab7e886e2d0f7672af84629 \
+    --hash=sha256:6f580d2bdd84365380830acf45550f2511469f673cb4a5ae3857a3170128b034
+    # via rsa
+pycparser==2.22 \
+    --hash=sha256:491c8be9c040f5390f5bf44a5b07752bd07f56edf992381b05c701439eec10f6 \
+    --hash=sha256:c3702b6d3dd8c7abc1afa565d7e63d53a1d0bd86cdc24edd75470f4de499cfcc
+    # via cffi
+pyelftools==0.32 \
+    --hash=sha256:013df952a006db5e138b1edf6d8a68ecc50630adbd0d83a2d41e7f846163d738 \
+    --hash=sha256:6de90ee7b8263e740c8715a925382d4099b354f29ac48ea40d840cf7aa14ace5
+    # via -r requirements-actions.in
+pygithub==2.6.1 \
+    --hash=sha256:6f2fa6d076ccae475f9fc392cc6cdbd54db985d4f69b8833a28397de75ed6ca3 \
+    --hash=sha256:b5c035392991cca63959e9453286b41b54d83bf2de2daa7d7ff7e4312cebf3bf
+    # via -r requirements-actions.in
+pygments==2.19.1 \
+    --hash=sha256:61c16d2a8576dc0649d9f39e089b5f02bcd27fba10d8fb4dcc28173f7a45151f \
+    --hash=sha256:9ea1544ad55cecf4b8242fab6dd35a93bbce657034b0611ee383099054ab6d8c
+    # via gcovr
+pyjwt==2.10.1 \
+    --hash=sha256:3cc5772eb20009233caf06e9d8a0577824723b44e6648ee0a2aedb6cf9381953 \
+    --hash=sha256:dcdd193e30abefd5debf142f9adfcdd2b58004e644f25406ffaebd50bd98dacb
+    # via pygithub
+pykwalify==1.8.0 \
+    --hash=sha256:731dfa87338cca9f559d1fca2bdea37299116e3139b73f78ca90a543722d6651 \
+    --hash=sha256:796b2ad3ed4cb99b88308b533fb2f559c30fa6efb4fa9fda11347f483d245884
+    # via
+    #   -r requirements-actions.in
+    #   west
+pylint==3.3.6 \
+    --hash=sha256:8b7c2d3e86ae3f94fb27703d521dd0b9b6b378775991f504d7c3a6275aa0a6a6 \
+    --hash=sha256:b634a041aac33706d56a0d217e6587228c66427e20ec21a019bc4cdee48c040a
+    # via -r requirements-actions.in
+pynacl==1.5.0 \
+    --hash=sha256:06b8f6fa7f5de8d5d2f7573fe8c863c051225a27b61e6860fd047b1775807858 \
+    --hash=sha256:0c84947a22519e013607c9be43706dd42513f9e6ae5d39d3613ca1e142fba44d \
+    --hash=sha256:20f42270d27e1b6a29f54032090b972d97f0a1b0948cc52392041ef7831fee93 \
+    --hash=sha256:401002a4aaa07c9414132aaed7f6836ff98f59277a234704ff66878c2ee4a0d1 \
+    --hash=sha256:52cb72a79269189d4e0dc537556f4740f7f0a9ec41c1322598799b0bdad4ef92 \
+    --hash=sha256:61f642bf2378713e2c2e1de73444a3778e5f0a38be6fee0fe532fe30060282ff \
+    --hash=sha256:8ac7448f09ab85811607bdd21ec2464495ac8b7c66d146bf545b0f08fb9220ba \
+    --hash=sha256:a36d4a9dda1f19ce6e03c9a784a2921a4b726b02e1c736600ca9c22029474394 \
+    --hash=sha256:a422368fc821589c228f4c49438a368831cb5bbc0eab5ebe1d7fac9dded6567b \
+    --hash=sha256:e46dae94e34b085175f8abb3b0aaa7da40767865ac82c928eeb9e57e1ea8a543
+    # via pygithub
+pyproject-api==1.9.0 \
+    --hash=sha256:326df9d68dea22d9d98b5243c46e3ca3161b07a1b9b18e213d1e24fd0e605766 \
+    --hash=sha256:7e8a9854b2dfb49454fae421cb86af43efbb2b2454e5646ffb7623540321ae6e
+    # via tox
+pyserial==3.5 \
+    --hash=sha256:3c77e014170dfffbd816e6ffc205e9842efb10be9f58ec16d3e8675b4925cddb \
+    --hash=sha256:c4451db6ba391ca6ca299fb3ec7bae67a5c55dde170964c7a14ceefec02f2cf0
+    # via -r requirements-actions.in
+pytest==8.3.5 \
+    --hash=sha256:c69214aa47deac29fad6c2a4f590b9c4a9fdb16a403176fe154b79c0b4d4d820 \
+    --hash=sha256:f4efe70cc14e511565ac476b57c279e12a855b11f48f212af1080ef2263d3845
+    # via -r requirements-actions.in
+python-can==4.5.0 \
+    --hash=sha256:1eec66833c1ac76a7e3d636ee0f8b4ba2752e892bab1c56ce74308b2216b5445 \
+    --hash=sha256:d3684cebe5b028a148c1742b3a45cec4fcaf83a7f7c52d0680b2eaeaf52f8eb7
+    # via canopen
+python-dateutil==2.9.0.post0 \
+    --hash=sha256:37dd54208da7e1cd875388217d5e00ebd4179249f90fb72437e91a35459a0ad3 \
+    --hash=sha256:a8b2bc7bffae282281c8140a97d3aa9c14da0b136dfe83f850eea9a5f7470427
+    # via
+    #   arrow
+    #   botocore
+    #   pykwalify
+python-magic==0.4.27 ; sys_platform != 'win32' \
+    --hash=sha256:c1ba14b08e4a5f5c31a302b7721239695b2f0f058d125bd5ce1ee36b9d9d3c3b \
+    --hash=sha256:c212960ad306f700aa0d01e5d7a325d20548ff97eb9920dcd29513174f0294d3
+    # via -r requirements-actions.in
+python-magic-bin==0.4.14 ; sys_platform == 'win32' \
+    --hash=sha256:34a788c03adde7608028203e2dbb208f1f62225ad91518787ae26d603ae68892 \
+    --hash=sha256:7b1743b3dbf16601d6eedf4e7c2c9a637901b0faaf24ad4df4d4527e7d8f66a4 \
+    --hash=sha256:90be6206ad31071a36065a2fc169c5afb5e0355cbe6030e87641c6c62edc2b69
+    # via -r requirements-actions.in
+pyyaml==6.0.2 \
+    --hash=sha256:01179a4a8559ab5de078078f37e5c1a30d76bb88519906844fd7bdea1b7729ff \
+    --hash=sha256:0833f8694549e586547b576dcfaba4a6b55b9e96098b36cdc7ebefe667dfed48 \
+    --hash=sha256:0a9a2848a5b7feac301353437eb7d5957887edbf81d56e903999a75a3d743086 \
+    --hash=sha256:0b69e4ce7a131fe56b7e4d770c67429700908fc0752af059838b1cfb41960e4e \
+    --hash=sha256:0ffe8360bab4910ef1b9e87fb812d8bc0a308b0d0eef8c8f44e0254ab3b07133 \
+    --hash=sha256:11d8f3dd2b9c1207dcaf2ee0bbbfd5991f571186ec9cc78427ba5bd32afae4b5 \
+    --hash=sha256:17e311b6c678207928d649faa7cb0d7b4c26a0ba73d41e99c4fff6b6c3276484 \
+    --hash=sha256:1e2120ef853f59c7419231f3bf4e7021f1b936f6ebd222406c3b60212205d2ee \
+    --hash=sha256:1f71ea527786de97d1a0cc0eacd1defc0985dcf6b3f17bb77dcfc8c34bec4dc5 \
+    --hash=sha256:23502f431948090f597378482b4812b0caae32c22213aecf3b55325e049a6c68 \
+    --hash=sha256:24471b829b3bf607e04e88d79542a9d48bb037c2267d7927a874e6c205ca7e9a \
+    --hash=sha256:29717114e51c84ddfba879543fb232a6ed60086602313ca38cce623c1d62cfbf \
+    --hash=sha256:2e99c6826ffa974fe6e27cdb5ed0021786b03fc98e5ee3c5bfe1fd5015f42b99 \
+    --hash=sha256:39693e1f8320ae4f43943590b49779ffb98acb81f788220ea932a6b6c51004d8 \
+    --hash=sha256:3ad2a3decf9aaba3d29c8f537ac4b243e36bef957511b4766cb0057d32b0be85 \
+    --hash=sha256:3b1fdb9dc17f5a7677423d508ab4f243a726dea51fa5e70992e59a7411c89d19 \
+    --hash=sha256:41e4e3953a79407c794916fa277a82531dd93aad34e29c2a514c2c0c5fe971cc \
+    --hash=sha256:43fa96a3ca0d6b1812e01ced1044a003533c47f6ee8aca31724f78e93ccc089a \
+    --hash=sha256:50187695423ffe49e2deacb8cd10510bc361faac997de9efef88badc3bb9e2d1 \
+    --hash=sha256:5ac9328ec4831237bec75defaf839f7d4564be1e6b25ac710bd1a96321cc8317 \
+    --hash=sha256:5d225db5a45f21e78dd9358e58a98702a0302f2659a3c6cd320564b75b86f47c \
+    --hash=sha256:6395c297d42274772abc367baaa79683958044e5d3835486c16da75d2a694631 \
+    --hash=sha256:688ba32a1cffef67fd2e9398a2efebaea461578b0923624778664cc1c914db5d \
+    --hash=sha256:68ccc6023a3400877818152ad9a1033e3db8625d899c72eacb5a668902e4d652 \
+    --hash=sha256:70b189594dbe54f75ab3a1acec5f1e3faa7e8cf2f1e08d9b561cb41b845f69d5 \
+    --hash=sha256:797b4f722ffa07cc8d62053e4cff1486fa6dc094105d13fea7b1de7d8bf71c9e \
+    --hash=sha256:7c36280e6fb8385e520936c3cb3b8042851904eba0e58d277dca80a5cfed590b \
+    --hash=sha256:7e7401d0de89a9a855c839bc697c079a4af81cf878373abd7dc625847d25cbd8 \
+    --hash=sha256:80bab7bfc629882493af4aa31a4cfa43a4c57c83813253626916b8c7ada83476 \
+    --hash=sha256:82d09873e40955485746739bcb8b4586983670466c23382c19cffecbf1fd8706 \
+    --hash=sha256:8388ee1976c416731879ac16da0aff3f63b286ffdd57cdeb95f3f2e085687563 \
+    --hash=sha256:8824b5a04a04a047e72eea5cec3bc266db09e35de6bdfe34c9436ac5ee27d237 \
+    --hash=sha256:8b9c7197f7cb2738065c481a0461e50ad02f18c78cd75775628afb4d7137fb3b \
+    --hash=sha256:9056c1ecd25795207ad294bcf39f2db3d845767be0ea6e6a34d856f006006083 \
+    --hash=sha256:936d68689298c36b53b29f23c6dbb74de12b4ac12ca6cfe0e047bedceea56180 \
+    --hash=sha256:9b22676e8097e9e22e36d6b7bda33190d0d400f345f23d4065d48f4ca7ae0425 \
+    --hash=sha256:a4d3091415f010369ae4ed1fc6b79def9416358877534caf6a0fdd2146c87a3e \
+    --hash=sha256:a8786accb172bd8afb8be14490a16625cbc387036876ab6ba70912730faf8e1f \
+    --hash=sha256:a9f8c2e67970f13b16084e04f134610fd1d374bf477b17ec1599185cf611d725 \
+    --hash=sha256:bc2fa7c6b47d6bc618dd7fb02ef6fdedb1090ec036abab80d4681424b84c1183 \
+    --hash=sha256:c70c95198c015b85feafc136515252a261a84561b7b1d51e3384e0655ddf25ab \
+    --hash=sha256:cc1c1159b3d456576af7a3e4d1ba7e6924cb39de8f67111c735f6fc832082774 \
+    --hash=sha256:ce826d6ef20b1bc864f0a68340c8b3287705cae2f8b4b1d932177dcc76721725 \
+    --hash=sha256:d584d9ec91ad65861cc08d42e834324ef890a082e591037abe114850ff7bbc3e \
+    --hash=sha256:d7fded462629cfa4b685c5416b949ebad6cec74af5e2d42905d41e257e0869f5 \
+    --hash=sha256:d84a1718ee396f54f3a086ea0a66d8e552b2ab2017ef8b420e92edbc841c352d \
+    --hash=sha256:d8e03406cac8513435335dbab54c0d385e4a49e4945d2909a581c83647ca0290 \
+    --hash=sha256:e10ce637b18caea04431ce14fabcf5c64a1c61ec9c56b071a4b7ca131ca52d44 \
+    --hash=sha256:ec031d5d2feb36d1d1a24380e4db6d43695f3748343d99434e6f5f9156aaa2ed \
+    --hash=sha256:ef6107725bd54b262d6dedcc2af448a266975032bc85ef0172c5f059da6325b4 \
+    --hash=sha256:efdca5630322a10774e8e98e1af481aad470dd62c3170801852d752aa7a783ba \
+    --hash=sha256:f753120cb8181e736c57ef7636e83f31b9c0d1722c516f7e86cf15b7aa57ff12 \
+    --hash=sha256:ff3824dc5261f50c9b0dfb3be22b4567a6f938ccce4587b38952d85fd9e9afe4
+    # via
+    #   -r requirements-actions.in
+    #   awscli
+    #   west
+    #   yamllint
+regex==2024.11.6 \
+    --hash=sha256:02a02d2bb04fec86ad61f3ea7f49c015a0681bf76abb9857f945d26159d2968c \
+    --hash=sha256:02e28184be537f0e75c1f9b2f8847dc51e08e6e171c6bde130b2687e0c33cf60 \
+    --hash=sha256:040df6fe1a5504eb0f04f048e6d09cd7c7110fef851d7c567a6b6e09942feb7d \
+    --hash=sha256:068376da5a7e4da51968ce4c122a7cd31afaaec4fccc7856c92f63876e57b51d \
+    --hash=sha256:06eb1be98df10e81ebaded73fcd51989dcf534e3c753466e4b60c4697a003b67 \
+    --hash=sha256:072623554418a9911446278f16ecb398fb3b540147a7828c06e2011fa531e773 \
+    --hash=sha256:086a27a0b4ca227941700e0b31425e7a28ef1ae8e5e05a33826e17e47fbfdba0 \
+    --hash=sha256:08986dce1339bc932923e7d1232ce9881499a0e02925f7402fb7c982515419ef \
+    --hash=sha256:0a86e7eeca091c09e021db8eb72d54751e527fa47b8d5787caf96d9831bd02ad \
+    --hash=sha256:0c32f75920cf99fe6b6c539c399a4a128452eaf1af27f39bce8909c9a3fd8cbe \
+    --hash=sha256:0d7f453dca13f40a02b79636a339c5b62b670141e63efd511d3f8f73fba162b3 \
+    --hash=sha256:1062b39a0a2b75a9c694f7a08e7183a80c63c0d62b301418ffd9c35f55aaa114 \
+    --hash=sha256:13291b39131e2d002a7940fb176e120bec5145f3aeb7621be6534e46251912c4 \
+    --hash=sha256:149f5008d286636e48cd0b1dd65018548944e495b0265b45e1bffecce1ef7f39 \
+    --hash=sha256:164d8b7b3b4bcb2068b97428060b2a53be050085ef94eca7f240e7947f1b080e \
+    --hash=sha256:167ed4852351d8a750da48712c3930b031f6efdaa0f22fa1933716bfcd6bf4a3 \
+    --hash=sha256:1c4de13f06a0d54fa0d5ab1b7138bfa0d883220965a29616e3ea61b35d5f5fc7 \
+    --hash=sha256:202eb32e89f60fc147a41e55cb086db2a3f8cb82f9a9a88440dcfc5d37faae8d \
+    --hash=sha256:220902c3c5cc6af55d4fe19ead504de80eb91f786dc102fbd74894b1551f095e \
+    --hash=sha256:2b3361af3198667e99927da8b84c1b010752fa4b1115ee30beaa332cabc3ef1a \
+    --hash=sha256:2c89a8cc122b25ce6945f0423dc1352cb9593c68abd19223eebbd4e56612c5b7 \
+    --hash=sha256:2d548dafee61f06ebdb584080621f3e0c23fff312f0de1afc776e2a2ba99a74f \
+    --hash=sha256:2e34b51b650b23ed3354b5a07aab37034d9f923db2a40519139af34f485f77d0 \
+    --hash=sha256:32f9a4c643baad4efa81d549c2aadefaeba12249b2adc5af541759237eee1c54 \
+    --hash=sha256:3a51ccc315653ba012774efca4f23d1d2a8a8f278a6072e29c7147eee7da446b \
+    --hash=sha256:3cde6e9f2580eb1665965ce9bf17ff4952f34f5b126beb509fee8f4e994f143c \
+    --hash=sha256:40291b1b89ca6ad8d3f2b82782cc33807f1406cf68c8d440861da6304d8ffbbd \
+    --hash=sha256:41758407fc32d5c3c5de163888068cfee69cb4c2be844e7ac517a52770f9af57 \
+    --hash=sha256:4181b814e56078e9b00427ca358ec44333765f5ca1b45597ec7446d3a1ef6e34 \
+    --hash=sha256:4f51f88c126370dcec4908576c5a627220da6c09d0bff31cfa89f2523843316d \
+    --hash=sha256:50153825ee016b91549962f970d6a4442fa106832e14c918acd1c8e479916c4f \
+    --hash=sha256:5056b185ca113c88e18223183aa1a50e66507769c9640a6ff75859619d73957b \
+    --hash=sha256:5071b2093e793357c9d8b2929dfc13ac5f0a6c650559503bb81189d0a3814519 \
+    --hash=sha256:525eab0b789891ac3be914d36893bdf972d483fe66551f79d3e27146191a37d4 \
+    --hash=sha256:52fb28f528778f184f870b7cf8f225f5eef0a8f6e3778529bdd40c7b3920796a \
+    --hash=sha256:5478c6962ad548b54a591778e93cd7c456a7a29f8eca9c49e4f9a806dcc5d638 \
+    --hash=sha256:5670bce7b200273eee1840ef307bfa07cda90b38ae56e9a6ebcc9f50da9c469b \
+    --hash=sha256:5704e174f8ccab2026bd2f1ab6c510345ae8eac818b613d7d73e785f1310f839 \
+    --hash=sha256:59dfe1ed21aea057a65c6b586afd2a945de04fc7db3de0a6e3ed5397ad491b07 \
+    --hash=sha256:5e7e351589da0850c125f1600a4c4ba3c722efefe16b297de54300f08d734fbf \
+    --hash=sha256:63b13cfd72e9601125027202cad74995ab26921d8cd935c25f09c630436348ff \
+    --hash=sha256:658f90550f38270639e83ce492f27d2c8d2cd63805c65a13a14d36ca126753f0 \
+    --hash=sha256:684d7a212682996d21ca12ef3c17353c021fe9de6049e19ac8481ec35574a70f \
+    --hash=sha256:69ab78f848845569401469da20df3e081e6b5a11cb086de3eed1d48f5ed57c95 \
+    --hash=sha256:6f44ec28b1f858c98d3036ad5d7d0bfc568bdd7a74f9c24e25f41ef1ebfd81a4 \
+    --hash=sha256:70b7fa6606c2881c1db9479b0eaa11ed5dfa11c8d60a474ff0e095099f39d98e \
+    --hash=sha256:764e71f22ab3b305e7f4c21f1a97e1526a25ebdd22513e251cf376760213da13 \
+    --hash=sha256:7ab159b063c52a0333c884e4679f8d7a85112ee3078fe3d9004b2dd875585519 \
+    --hash=sha256:805e6b60c54bf766b251e94526ebad60b7de0c70f70a4e6210ee2891acb70bf2 \
+    --hash=sha256:8447d2d39b5abe381419319f942de20b7ecd60ce86f16a23b0698f22e1b70008 \
+    --hash=sha256:86fddba590aad9208e2fa8b43b4c098bb0ec74f15718bb6a704e3c63e2cef3e9 \
+    --hash=sha256:89d75e7293d2b3e674db7d4d9b1bee7f8f3d1609428e293771d1a962617150cc \
+    --hash=sha256:93c0b12d3d3bc25af4ebbf38f9ee780a487e8bf6954c115b9f015822d3bb8e48 \
+    --hash=sha256:94d87b689cdd831934fa3ce16cc15cd65748e6d689f5d2b8f4f4df2065c9fa20 \
+    --hash=sha256:9714398225f299aa85267fd222f7142fcb5c769e73d7733344efc46f2ef5cf89 \
+    --hash=sha256:982e6d21414e78e1f51cf595d7f321dcd14de1f2881c5dc6a6e23bbbbd68435e \
+    --hash=sha256:997d6a487ff00807ba810e0f8332c18b4eb8d29463cfb7c820dc4b6e7562d0cf \
+    --hash=sha256:a03e02f48cd1abbd9f3b7e3586d97c8f7a9721c436f51a5245b3b9483044480b \
+    --hash=sha256:a36fdf2af13c2b14738f6e973aba563623cb77d753bbbd8d414d18bfaa3105dd \
+    --hash=sha256:a6ba92c0bcdf96cbf43a12c717eae4bc98325ca3730f6b130ffa2e3c3c723d84 \
+    --hash=sha256:a7c2155f790e2fb448faed6dd241386719802296ec588a8b9051c1f5c481bc29 \
+    --hash=sha256:a93c194e2df18f7d264092dc8539b8ffb86b45b899ab976aa15d48214138e81b \
+    --hash=sha256:abfa5080c374a76a251ba60683242bc17eeb2c9818d0d30117b4486be10c59d3 \
+    --hash=sha256:ac10f2c4184420d881a3475fb2c6f4d95d53a8d50209a2500723d831036f7c45 \
+    --hash=sha256:ad182d02e40de7459b73155deb8996bbd8e96852267879396fb274e8700190e3 \
+    --hash=sha256:b2837718570f95dd41675328e111345f9b7095d821bac435aac173ac80b19983 \
+    --hash=sha256:b489578720afb782f6ccf2840920f3a32e31ba28a4b162e13900c3e6bd3f930e \
+    --hash=sha256:b583904576650166b3d920d2bcce13971f6f9e9a396c673187f49811b2769dc7 \
+    --hash=sha256:b85c2530be953a890eaffde05485238f07029600e8f098cdf1848d414a8b45e4 \
+    --hash=sha256:b97c1e0bd37c5cd7902e65f410779d39eeda155800b65fc4d04cc432efa9bc6e \
+    --hash=sha256:ba9b72e5643641b7d41fa1f6d5abda2c9a263ae835b917348fc3c928182ad467 \
+    --hash=sha256:bb26437975da7dc36b7efad18aa9dd4ea569d2357ae6b783bf1118dabd9ea577 \
+    --hash=sha256:bb8f74f2f10dbf13a0be8de623ba4f9491faf58c24064f32b65679b021ed0001 \
+    --hash=sha256:bde01f35767c4a7899b7eb6e823b125a64de314a8ee9791367c9a34d56af18d0 \
+    --hash=sha256:bec9931dfb61ddd8ef2ebc05646293812cb6b16b60cf7c9511a832b6f1854b55 \
+    --hash=sha256:c36f9b6f5f8649bb251a5f3f66564438977b7ef8386a52460ae77e6070d309d9 \
+    --hash=sha256:cdf58d0e516ee426a48f7b2c03a332a4114420716d55769ff7108c37a09951bf \
+    --hash=sha256:d1cee317bfc014c2419a76bcc87f071405e3966da434e03e13beb45f8aced1a6 \
+    --hash=sha256:d22326fcdef5e08c154280b71163ced384b428343ae16a5ab2b3354aed12436e \
+    --hash=sha256:d3660c82f209655a06b587d55e723f0b813d3a7db2e32e5e7dc64ac2a9e86fde \
+    --hash=sha256:da8f5fc57d1933de22a9e23eec290a0d8a5927a5370d24bda9a6abe50683fe62 \
+    --hash=sha256:df951c5f4a1b1910f1a99ff42c473ff60f8225baa1cdd3539fe2819d9543e9df \
+    --hash=sha256:e5364a4502efca094731680e80009632ad6624084aff9a23ce8c8c6820de3e51 \
+    --hash=sha256:ea1bfda2f7162605f6e8178223576856b3d791109f15ea99a9f95c16a7636fb5 \
+    --hash=sha256:f02f93b92358ee3f78660e43b4b0091229260c5d5c408d17d60bf26b6c900e86 \
+    --hash=sha256:f056bf21105c2515c32372bbc057f43eb02aae2fda61052e2f7622c801f0b4e2 \
+    --hash=sha256:f1ac758ef6aebfc8943560194e9fd0fa18bcb34d89fd8bd2af18183afd8da3a2 \
+    --hash=sha256:f2a19f302cd1ce5dd01a9099aaa19cae6173306d1302a43b627f62e21cf18ac0 \
+    --hash=sha256:f654882311409afb1d780b940234208a252322c24a93b442ca714d119e68086c \
+    --hash=sha256:f65557897fc977a44ab205ea871b690adaef6b9da6afda4790a2484b04293a5f \
+    --hash=sha256:f9d1e379028e0fc2ae3654bac3cbbef81bf3fd571272a42d56c24007979bafb6 \
+    --hash=sha256:fdabbfc59f2c6edba2a6622c647b716e34e8e3867e0ab975412c5c2f79b82da2 \
+    --hash=sha256:fdd6028445d2460f33136c55eeb1f601ab06d74cb3347132e1c24250187500d9 \
+    --hash=sha256:ff590880083d60acc0433f9c3f713c51f7ac6ebb9adf889c79a261ecf541aa91
+    # via sphinx-lint
+requests==2.32.3 \
+    --hash=sha256:55365417734eb18255590a9ff9eb97e9e1da868d4ccd6402399eaf68af20a760 \
+    --hash=sha256:70761cfe03c773ceb22aa2f671b4757976145175cdfca038c02654d061d6dcc6
+    # via pygithub
+rsa==4.7.2 \
+    --hash=sha256:78f9a9bf4e7be0c5ded4583326e7461e3a3c5aae24073648b4bdfa797d78c9d2 \
+    --hash=sha256:9d689e6ca1b3038bc82bf8d23e944b6b6037bc02301a574935b2dd946e0353b9
+    # via awscli
+ruamel-yaml==0.18.10 \
+    --hash=sha256:20c86ab29ac2153f80a428e1254a8adf686d3383df04490514ca3b79a362db58 \
+    --hash=sha256:30f22513ab2301b3d2b577adc121c6471f28734d3d9728581245f1e76468b4f1
+    # via pykwalify
+ruamel-yaml-clib==0.2.12 ; python_full_version < '3.13' and platform_python_implementation == 'CPython' \
+    --hash=sha256:040ae85536960525ea62868b642bdb0c2cc6021c9f9d507810c0c604e66f5a7b \
+    --hash=sha256:0467c5965282c62203273b838ae77c0d29d7638c8a4e3a1c8bdd3602c10904e4 \
+    --hash=sha256:0b7e75b4965e1d4690e93021adfcecccbca7d61c7bddd8e22406ef2ff20d74ef \
+    --hash=sha256:11f891336688faf5156a36293a9c362bdc7c88f03a8a027c2c1d8e0bcde998e5 \
+    --hash=sha256:1492a6051dab8d912fc2adeef0e8c72216b24d57bd896ea607cb90bb0c4981d3 \
+    --hash=sha256:20b0f8dc160ba83b6dcc0e256846e1a02d044e13f7ea74a3d1d56ede4e48c632 \
+    --hash=sha256:22353049ba4181685023b25b5b51a574bce33e7f51c759371a7422dcae5402a6 \
+    --hash=sha256:2c59aa6170b990d8d2719323e628aaf36f3bfbc1c26279c0eeeb24d05d2d11c7 \
+    --hash=sha256:32621c177bbf782ca5a18ba4d7af0f1082a3f6e517ac2a18b3974d4edf349680 \
+    --hash=sha256:3bc2a80e6420ca8b7d3590791e2dfc709c88ab9152c00eeb511c9875ce5778bf \
+    --hash=sha256:3eac5a91891ceb88138c113f9db04f3cebdae277f5d44eaa3651a4f573e6a5da \
+    --hash=sha256:4a6679521a58256a90b0d89e03992c15144c5f3858f40d7c18886023d7943db6 \
+    --hash=sha256:4c8c5d82f50bb53986a5e02d1b3092b03622c02c2eb78e29bec33fd9593bae1a \
+    --hash=sha256:4f6f3eac23941b32afccc23081e1f50612bdbe4e982012ef4f5797986828cd01 \
+    --hash=sha256:5a0e060aace4c24dcaf71023bbd7d42674e3b230f7e7b97317baf1e953e5b519 \
+    --hash=sha256:6442cb36270b3afb1b4951f060eccca1ce49f3d087ca1ca4563a6eb479cb3de6 \
+    --hash=sha256:6c8fbb13ec503f99a91901ab46e0b07ae7941cd527393187039aec586fdfd36f \
+    --hash=sha256:749c16fcc4a2b09f28843cda5a193e0283e47454b63ec4b81eaa2242f50e4ccd \
+    --hash=sha256:7dd5adc8b930b12c8fc5b99e2d535a09889941aa0d0bd06f4749e9a9397c71d2 \
+    --hash=sha256:811ea1594b8a0fb466172c384267a4e5e367298af6b228931f273b111f17ef52 \
+    --hash=sha256:932205970b9f9991b34f55136be327501903f7c66830e9760a8ffb15b07f05cd \
+    --hash=sha256:943f32bc9dedb3abff9879edc134901df92cfce2c3d5c9348f172f62eb2d771d \
+    --hash=sha256:95c3829bb364fdb8e0332c9931ecf57d9be3519241323c5274bd82f709cebc0c \
+    --hash=sha256:96777d473c05ee3e5e3c3e999f5d23c6f4ec5b0c38c098b3a5229085f74236c6 \
+    --hash=sha256:a274fb2cb086c7a3dea4322ec27f4cb5cc4b6298adb583ab0e211a4682f241eb \
+    --hash=sha256:a52d48f4e7bf9005e8f0a89209bf9a73f7190ddf0489eee5eb51377385f59f2a \
+    --hash=sha256:a606ef75a60ecf3d924613892cc603b154178ee25abb3055db5062da811fd969 \
+    --hash=sha256:ab007f2f5a87bd08ab1499bdf96f3d5c6ad4dcfa364884cb4549aa0154b13a28 \
+    --hash=sha256:b82a7c94a498853aa0b272fd5bc67f29008da798d4f93a2f9f289feb8426a58d \
+    --hash=sha256:bb43a269eb827806502c7c8efb7ae7e9e9d0573257a46e8e952f4d4caba4f31e \
+    --hash=sha256:bc5f1e1c28e966d61d2519f2a3d451ba989f9ea0f2307de7bc45baa526de9e45 \
+    --hash=sha256:bd0a08f0bab19093c54e18a14a10b4322e1eacc5217056f3c063bd2f59853ce4 \
+    --hash=sha256:beffaed67936fbbeffd10966a4eb53c402fafd3d6833770516bf7314bc6ffa12 \
+    --hash=sha256:bf165fef1f223beae7333275156ab2022cffe255dcc51c27f066b4370da81e31 \
+    --hash=sha256:cf12567a7b565cbf65d438dec6cfbe2917d3c1bdddfce84a9930b7d35ea59642 \
+    --hash=sha256:d84318609196d6bd6da0edfa25cedfbabd8dbde5140a0a23af29ad4b8f91fb1e \
+    --hash=sha256:d85252669dc32f98ebcd5d36768f5d4faeaeaa2d655ac0473be490ecdae3c285 \
+    --hash=sha256:e143ada795c341b56de9418c58d028989093ee611aa27ffb9b7f609c00d813ed \
+    --hash=sha256:e188d2699864c11c36cdfdada94d781fd5d6b0071cd9c427bceb08ad3d7c70e1 \
+    --hash=sha256:e2f1c3765db32be59d18ab3953f43ab62a761327aafc1594a2a1fbe038b8b8a7 \
+    --hash=sha256:e5b8daf27af0b90da7bb903a876477a9e6d7270be6146906b276605997c7e9a3 \
+    --hash=sha256:e7e3736715fbf53e9be2a79eb4db68e4ed857017344d697e8b9749444ae57475 \
+    --hash=sha256:e8c4ebfcfd57177b572e2040777b8abc537cdef58a2120e830124946aa9b42c5 \
+    --hash=sha256:f66efbc1caa63c088dead1c4170d148eabc9b80d95fb75b6c92ac0aad2437d76 \
+    --hash=sha256:fc4b630cd3fa2cf7fce38afa91d7cfe844a9f75d7f0f36393fa98815e911d987 \
+    --hash=sha256:fd5415dded15c3822597455bc02bcd66e81ef8b7a48cb71a33628fc9fdde39df
+    # via ruamel-yaml
+ruff==0.8.1 \
+    --hash=sha256:2029b8c22da147c50ae577e621a5bfbc5d1fed75d86af53643d7a7aee1d23871 \
+    --hash=sha256:2666520828dee7dfc7e47ee4ea0d928f40de72056d929a7c5292d95071d881d1 \
+    --hash=sha256:288326162804f34088ac007139488dcb43de590a5ccfec3166396530b58fb89d \
+    --hash=sha256:2954cdbe8dfd8ab359d4a30cd971b589d335a44d444b6ca2cb3d1da21b75e4b6 \
+    --hash=sha256:333c57013ef8c97a53892aa56042831c372e0bb1785ab7026187b7abd0135ad5 \
+    --hash=sha256:3583db9a6450364ed5ca3f3b4225958b24f78178908d5c4bc0f46251ccca898f \
+    --hash=sha256:364e6674450cbac8e998f7b30639040c99d81dfb5bbc6dfad69bc7a8f916b3d1 \
+    --hash=sha256:55873cc1a473e5ac129d15eccb3c008c096b94809d693fc7053f588b67822737 \
+    --hash=sha256:93335cd7c0eaedb44882d75a7acb7df4b77cd7cd0d2255c93b28791716e81790 \
+    --hash=sha256:a885d68342a231b5ba4d30b8c6e1b1ee3a65cf37e3d29b3c74069cdf1ee1e3c9 \
+    --hash=sha256:adf314fc458374c25c5c4a4a9270c3e8a6a807b1bec018cfa2813d6546215540 \
+    --hash=sha256:b12c39b9448632284561cbf4191aa1b005882acbc81900ffa9f9f471c8ff7e26 \
+    --hash=sha256:b22346f845fec132aa39cd29acb94451d030c10874408dbf776af3aaeb53284c \
+    --hash=sha256:b2f2f7a7e7648a2bfe6ead4e0a16745db956da0e3a231ad443d2a66a105c04fa \
+    --hash=sha256:b8a4f7385c2285c30f34b200ca5511fcc865f17578383db154e098150ce0a087 \
+    --hash=sha256:cd054486da0c53e41e0086e1730eb77d1f698154f910e0cd9e0d64274979a209 \
+    --hash=sha256:d2c16e3508c8cc73e96aa5127d0df8913d2290098f776416a4b157657bee44c5 \
+    --hash=sha256:fae0805bd514066f20309f6742f6ee7904a773eb9e6c17c45d6b1600ca65c9b5
+    # via -r requirements-actions.in
+s3transfer==0.11.4 \
+    --hash=sha256:559f161658e1cf0a911f45940552c696735f5c74e64362e515f333ebed87d679 \
+    --hash=sha256:ac265fa68318763a03bf2dc4f39d5cbd6a9e178d81cc9483ad27da33637e320d
+    # via awscli
+setuptools==78.1.0 \
+    --hash=sha256:18fd474d4a82a5f83dac888df697af65afa82dec7323d09c3e37d1f14288da54 \
+    --hash=sha256:3e386e96793c8702ae83d17b853fb93d3e09ef82ec62722e61da5cd22376dcd8
+    # via
+    #   -r requirements-actions.in
+    #   west
+sh==1.14.3 ; sys_platform != 'win32' \
+    --hash=sha256:e4045b6c732d9ce75d571c79f5ac2234edd9ae4f5fa9d59b09705082bdca18c7
+    # via gitlint-core
+six==1.17.0 \
+    --hash=sha256:4721f391ed90541fddacab5acf947aa0d3dc7d27b2e1e8eda2be8970586c3274 \
+    --hash=sha256:ff70335d468e7eb6ec65b95b99d3a2836546063f63acc5171de367e834932a81
+    # via
+    #   anytree
+    #   python-dateutil
+smmap==5.0.2 \
+    --hash=sha256:26ea65a03958fa0c8a1c7e8c7a58fdc77221b8910f6be2131affade476898ad5 \
+    --hash=sha256:b30115f0def7d7531d22a0fb6502488d879e75b260a9db4d0819cfb25403af5e
+    # via gitdb
+sphinx-lint==1.0.0 \
+    --hash=sha256:6117a0f340b2dc73eadfc57db7531d4477e0929f92a0c1a2f61e6edbc272f0bc \
+    --hash=sha256:6eafdb44172ce526f405bf36c713eb246f1340ec2d667e7298e2487ed76decd2
+    # via -r requirements-actions.in
+tabulate==0.9.0 \
+    --hash=sha256:0095b12bf5966de529c0feb1fa08671671b3368eec77d7ef7ab114be2c068b3c \
+    --hash=sha256:024ca478df22e9340661486f85298cff5f6dcdba14f3813e8830015b9ed1948f
+    # via -r requirements-actions.in
+tomli==2.2.1 \
+    --hash=sha256:023aa114dd824ade0100497eb2318602af309e5a55595f76b626d6d9f3b7b0a6 \
+    --hash=sha256:02abe224de6ae62c19f090f68da4e27b10af2b93213d36cf44e6e1c5abd19fdd \
+    --hash=sha256:286f0ca2ffeeb5b9bd4fcc8d6c330534323ec51b2f52da063b11c502da16f30c \
+    --hash=sha256:2d0f2fdd22b02c6d81637a3c95f8cd77f995846af7414c5c4b8d0545afa1bc4b \
+    --hash=sha256:33580bccab0338d00994d7f16f4c4ec25b776af3ffaac1ed74e0b3fc95e885a8 \
+    --hash=sha256:400e720fe168c0f8521520190686ef8ef033fb19fc493da09779e592861b78c6 \
+    --hash=sha256:40741994320b232529c802f8bc86da4e1aa9f413db394617b9a256ae0f9a7f77 \
+    --hash=sha256:465af0e0875402f1d226519c9904f37254b3045fc5084697cefb9bdde1ff99ff \
+    --hash=sha256:4a8f6e44de52d5e6c657c9fe83b562f5f4256d8ebbfe4ff922c495620a7f6cea \
+    --hash=sha256:4e340144ad7ae1533cb897d406382b4b6fede8890a03738ff1683af800d54192 \
+    --hash=sha256:678e4fa69e4575eb77d103de3df8a895e1591b48e740211bd1067378c69e8249 \
+    --hash=sha256:6972ca9c9cc9f0acaa56a8ca1ff51e7af152a9f87fb64623e31d5c83700080ee \
+    --hash=sha256:7fc04e92e1d624a4a63c76474610238576942d6b8950a2d7f908a340494e67e4 \
+    --hash=sha256:889f80ef92701b9dbb224e49ec87c645ce5df3fa2cc548664eb8a25e03127a98 \
+    --hash=sha256:8d57ca8095a641b8237d5b079147646153d22552f1c637fd3ba7f4b0b29167a8 \
+    --hash=sha256:8dd28b3e155b80f4d54beb40a441d366adcfe740969820caf156c019fb5c7ec4 \
+    --hash=sha256:9316dc65bed1684c9a98ee68759ceaed29d229e985297003e494aa825ebb0281 \
+    --hash=sha256:a198f10c4d1b1375d7687bc25294306e551bf1abfa4eace6650070a5c1ae2744 \
+    --hash=sha256:a38aa0308e754b0e3c67e344754dff64999ff9b513e691d0e786265c93583c69 \
+    --hash=sha256:a92ef1a44547e894e2a17d24e7557a5e85a9e1d0048b0b5e7541f76c5032cb13 \
+    --hash=sha256:ac065718db92ca818f8d6141b5f66369833d4a80a9d74435a268c52bdfa73140 \
+    --hash=sha256:b82ebccc8c8a36f2094e969560a1b836758481f3dc360ce9a3277c65f374285e \
+    --hash=sha256:c954d2250168d28797dd4e3ac5cf812a406cd5a92674ee4c8f123c889786aa8e \
+    --hash=sha256:cb55c73c5f4408779d0cf3eef9f762b9c9f147a77de7b258bef0a5628adc85cc \
+    --hash=sha256:cd45e1dc79c835ce60f7404ec8119f2eb06d38b1deba146f07ced3bbc44505ff \
+    --hash=sha256:d3f5614314d758649ab2ab3a62d4f2004c825922f9e370b29416484086b264ec \
+    --hash=sha256:d920f33822747519673ee656a4b6ac33e382eca9d331c87770faa3eef562aeb2 \
+    --hash=sha256:db2b95f9de79181805df90bedc5a5ab4c165e6ec3fe99f970d0e302f384ad222 \
+    --hash=sha256:e59e304978767a54663af13c07b3d1af22ddee3bb2fb0618ca1593e4f593a106 \
+    --hash=sha256:e85e99945e688e32d5a35c1ff38ed0b3f41f43fad8df0bdf79f72b2ba7bc5272 \
+    --hash=sha256:ece47d672db52ac607a3d9599a9d48dcb2f2f735c6c2d1f34130085bb12b112a \
+    --hash=sha256:f4039b9cbc3048b2416cc57ab3bda989a6fcf9b36cf8937f01a6e731b64f80d7
+    # via
+    #   -r requirements-actions.in
+    #   mypy
+    #   pylint
+    #   pyproject-api
+    #   pytest
+    #   tox
+tomlkit==0.13.2 \
+    --hash=sha256:7a974427f6e119197f670fbbbeae7bef749a6c14e793db934baefc1b5f03efde \
+    --hash=sha256:fff5fe59a87295b278abd31bec92c15d9bc4a06885ab12bcea52c71119392e79
+    # via pylint
+tox==4.25.0 \
+    --hash=sha256:4dfdc7ba2cc6fdc6688dde1b21e7b46ff6c41795fb54586c91a3533317b5255c \
+    --hash=sha256:dd67f030317b80722cf52b246ff42aafd3ed27ddf331c415612d084304cf5e52
+    # via -r requirements-actions.in
+typing-extensions==4.13.0 \
+    --hash=sha256:0a4ac55a5820789d87e297727d229866c9650f6521b64206413c4fbada24d95b \
+    --hash=sha256:c8dd92cc0d6425a97c18fbb9d1954e5ff92c1ca881a309c45f06ebc0b79058e5
+    # via
+    #   astroid
+    #   mypy
+    #   pygithub
+    #   python-can
+    #   tox
+unidiff==0.7.5 \
+    --hash=sha256:2e5f0162052248946b9f0970a40e9e124236bf86c82b70821143a6fc1dea2574 \
+    --hash=sha256:c93bf2265cc1ba2a520e415ab05da587370bc2a3ae9e0414329f54f0c2fc09e8
+    # via -r requirements-actions.in
+urllib3==2.3.0 \
+    --hash=sha256:1cee9ad369867bfdbbb48b7dd50374c0967a0bb7710050facf0dd6911440e3df \
+    --hash=sha256:f8c5449b3cf0861679ce7e0503c7b44b5ec981bec0d1d3795a07f1ba96f0204d
+    # via
+    #   botocore
+    #   elastic-transport
+    #   pygithub
+    #   requests
+virtualenv==20.30.0 \
+    --hash=sha256:800863162bcaa5450a6e4d721049730e7f2dae07720e0902b0e4040bd6f9ada8 \
+    --hash=sha256:e34302959180fca3af42d1800df014b35019490b119eba981af27f2fa486e5d6
+    # via tox
+west==1.3.0 \
+    --hash=sha256:89320034be87099d16e75f4760ac0d1ed67e8978928e468ab993e3fba0cfe92f \
+    --hash=sha256:b3af425fcce1f88a955942b3573bc877cdc3c3dbab5912434cdf44a473c5695b
+    # via -r requirements-actions.in
+wrapt==1.17.2 \
+    --hash=sha256:08e7ce672e35efa54c5024936e559469436f8b8096253404faeb54d2a878416f \
+    --hash=sha256:0a6e821770cf99cc586d33833b2ff32faebdbe886bd6322395606cf55153246c \
+    --hash=sha256:0b929ac182f5ace000d459c59c2c9c33047e20e935f8e39371fa6e3b85d56f4a \
+    --hash=sha256:129a150f5c445165ff941fc02ee27df65940fcb8a22a61828b1853c98763a64b \
+    --hash=sha256:13e6afb7fe71fe7485a4550a8844cc9ffbe263c0f1a1eea569bc7091d4898555 \
+    --hash=sha256:1473400e5b2733e58b396a04eb7f35f541e1fb976d0c0724d0223dd607e0f74c \
+    --hash=sha256:18983c537e04d11cf027fbb60a1e8dfd5190e2b60cc27bc0808e653e7b218d1b \
+    --hash=sha256:1a7ed2d9d039bd41e889f6fb9364554052ca21ce823580f6a07c4ec245c1f5d6 \
+    --hash=sha256:1e1fe0e6ab7775fd842bc39e86f6dcfc4507ab0ffe206093e76d61cde37225c8 \
+    --hash=sha256:1fb5699e4464afe5c7e65fa51d4f99e0b2eadcc176e4aa33600a3df7801d6662 \
+    --hash=sha256:2696993ee1eebd20b8e4ee4356483c4cb696066ddc24bd70bcbb80fa56ff9061 \
+    --hash=sha256:35621ae4c00e056adb0009f8e86e28eb4a41a4bfa8f9bfa9fca7d343fe94f998 \
+    --hash=sha256:36ccae62f64235cf8ddb682073a60519426fdd4725524ae38874adf72b5f2aeb \
+    --hash=sha256:3cedbfa9c940fdad3e6e941db7138e26ce8aad38ab5fe9dcfadfed9db7a54e62 \
+    --hash=sha256:3d57c572081fed831ad2d26fd430d565b76aa277ed1d30ff4d40670b1c0dd984 \
+    --hash=sha256:3fc7cb4c1c744f8c05cd5f9438a3caa6ab94ce8344e952d7c45a8ed59dd88392 \
+    --hash=sha256:4011d137b9955791f9084749cba9a367c68d50ab8d11d64c50ba1688c9b457f2 \
+    --hash=sha256:40d615e4fe22f4ad3528448c193b218e077656ca9ccb22ce2cb20db730f8d306 \
+    --hash=sha256:410a92fefd2e0e10d26210e1dfb4a876ddaf8439ef60d6434f21ef8d87efc5b7 \
+    --hash=sha256:41388e9d4d1522446fe79d3213196bd9e3b301a336965b9e27ca2788ebd122f3 \
+    --hash=sha256:468090021f391fe0056ad3e807e3d9034e0fd01adcd3bdfba977b6fdf4213ea9 \
+    --hash=sha256:49703ce2ddc220df165bd2962f8e03b84c89fee2d65e1c24a7defff6f988f4d6 \
+    --hash=sha256:4a721d3c943dae44f8e243b380cb645a709ba5bd35d3ad27bc2ed947e9c68192 \
+    --hash=sha256:4afd5814270fdf6380616b321fd31435a462019d834f83c8611a0ce7484c7317 \
+    --hash=sha256:4c82b8785d98cdd9fed4cac84d765d234ed3251bd6afe34cb7ac523cb93e8b4f \
+    --hash=sha256:4db983e7bca53819efdbd64590ee96c9213894272c776966ca6306b73e4affda \
+    --hash=sha256:582530701bff1dec6779efa00c516496968edd851fba224fbd86e46cc6b73563 \
+    --hash=sha256:58455b79ec2661c3600e65c0a716955adc2410f7383755d537584b0de41b1d8a \
+    --hash=sha256:58705da316756681ad3c9c73fd15499aa4d8c69f9fd38dc8a35e06c12468582f \
+    --hash=sha256:5bb1d0dbf99411f3d871deb6faa9aabb9d4e744d67dcaaa05399af89d847a91d \
+    --hash=sha256:5c803c401ea1c1c18de70a06a6f79fcc9c5acfc79133e9869e730ad7f8ad8ef9 \
+    --hash=sha256:5cbabee4f083b6b4cd282f5b817a867cf0b1028c54d445b7ec7cfe6505057cf8 \
+    --hash=sha256:612dff5db80beef9e649c6d803a8d50c409082f1fedc9dbcdfde2983b2025b82 \
+    --hash=sha256:62c2caa1585c82b3f7a7ab56afef7b3602021d6da34fbc1cf234ff139fed3cd9 \
+    --hash=sha256:69606d7bb691b50a4240ce6b22ebb319c1cfb164e5f6569835058196e0f3a845 \
+    --hash=sha256:6d9187b01bebc3875bac9b087948a2bccefe464a7d8f627cf6e48b1bbae30f82 \
+    --hash=sha256:6ed6ffac43aecfe6d86ec5b74b06a5be33d5bb9243d055141e8cabb12aa08125 \
+    --hash=sha256:703919b1633412ab54bcf920ab388735832fdcb9f9a00ae49387f0fe67dad504 \
+    --hash=sha256:766d8bbefcb9e00c3ac3b000d9acc51f1b399513f44d77dfe0eb026ad7c9a19b \
+    --hash=sha256:80dd7db6a7cb57ffbc279c4394246414ec99537ae81ffd702443335a61dbf3a7 \
+    --hash=sha256:8112e52c5822fc4253f3901b676c55ddf288614dc7011634e2719718eaa187dc \
+    --hash=sha256:8c8b293cd65ad716d13d8dd3624e42e5a19cc2a2f1acc74b30c2c13f15cb61a6 \
+    --hash=sha256:8fdbdb757d5390f7c675e558fd3186d590973244fab0c5fe63d373ade3e99d40 \
+    --hash=sha256:91bd7d1773e64019f9288b7a5101f3ae50d3d8e6b1de7edee9c2ccc1d32f0c0a \
+    --hash=sha256:95c658736ec15602da0ed73f312d410117723914a5c91a14ee4cdd72f1d790b3 \
+    --hash=sha256:99039fa9e6306880572915728d7f6c24a86ec57b0a83f6b2491e1d8ab0235b9a \
+    --hash=sha256:9a2bce789a5ea90e51a02dfcc39e31b7f1e662bc3317979aa7e5538e3a034f72 \
+    --hash=sha256:9a7d15bbd2bc99e92e39f49a04653062ee6085c0e18b3b7512a4f2fe91f2d681 \
+    --hash=sha256:9abc77a4ce4c6f2a3168ff34b1da9b0f311a8f1cfd694ec96b0603dff1c79438 \
+    --hash=sha256:9e8659775f1adf02eb1e6f109751268e493c73716ca5761f8acb695e52a756ae \
+    --hash=sha256:9fee687dce376205d9a494e9c121e27183b2a3df18037f89d69bd7b35bcf59e2 \
+    --hash=sha256:a5aaeff38654462bc4b09023918b7f21790efb807f54c000a39d41d69cf552cb \
+    --hash=sha256:a604bf7a053f8362d27eb9fefd2097f82600b856d5abe996d623babd067b1ab5 \
+    --hash=sha256:abbb9e76177c35d4e8568e58650aa6926040d6a9f6f03435b7a522bf1c487f9a \
+    --hash=sha256:acc130bc0375999da18e3d19e5a86403667ac0c4042a094fefb7eec8ebac7cf3 \
+    --hash=sha256:b18f2d1533a71f069c7f82d524a52599053d4c7166e9dd374ae2136b7f40f7c8 \
+    --hash=sha256:b4e42a40a5e164cbfdb7b386c966a588b1047558a990981ace551ed7e12ca9c2 \
+    --hash=sha256:b5e251054542ae57ac7f3fba5d10bfff615b6c2fb09abeb37d2f1463f841ae22 \
+    --hash=sha256:b60fb58b90c6d63779cb0c0c54eeb38941bae3ecf7a73c764c52c88c2dcb9d72 \
+    --hash=sha256:b870b5df5b71d8c3359d21be8f0d6c485fa0ebdb6477dda51a1ea54a9b558061 \
+    --hash=sha256:ba0f0eb61ef00ea10e00eb53a9129501f52385c44853dbd6c4ad3f403603083f \
+    --hash=sha256:bb87745b2e6dc56361bfde481d5a378dc314b252a98d7dd19a651a3fa58f24a9 \
+    --hash=sha256:bb90fb8bda722a1b9d48ac1e6c38f923ea757b3baf8ebd0c82e09c5c1a0e7a04 \
+    --hash=sha256:bc570b5f14a79734437cb7b0500376b6b791153314986074486e0b0fa8d71d98 \
+    --hash=sha256:c86563182421896d73858e08e1db93afdd2b947a70064b813d515d66549e15f9 \
+    --hash=sha256:c958bcfd59bacc2d0249dcfe575e71da54f9dcf4a8bdf89c4cb9a68a1170d73f \
+    --hash=sha256:d18a4865f46b8579d44e4fe1e2bcbc6472ad83d98e22a26c963d46e4c125ef0b \
+    --hash=sha256:d5e2439eecc762cd85e7bd37161d4714aa03a33c5ba884e26c81559817ca0925 \
+    --hash=sha256:e3890b508a23299083e065f435a492b5435eba6e304a7114d2f919d400888cc6 \
+    --hash=sha256:e496a8ce2c256da1eb98bd15803a79bee00fc351f5dfb9ea82594a3f058309e0 \
+    --hash=sha256:e8b2816ebef96d83657b56306152a93909a83f23994f4b30ad4573b00bd11bb9 \
+    --hash=sha256:eaf675418ed6b3b31c7a989fd007fa7c3be66ce14e5c3b27336383604c9da85c \
+    --hash=sha256:ec89ed91f2fa8e3f52ae53cd3cf640d6feff92ba90d62236a81e4e563ac0e991 \
+    --hash=sha256:ecc840861360ba9d176d413a5489b9a0aff6d6303d7e733e2c4623cfa26904a6 \
+    --hash=sha256:f09b286faeff3c750a879d336fb6d8713206fc97af3adc14def0cdd349df6000 \
+    --hash=sha256:f393cda562f79828f38a819f4788641ac7c4085f30f1ce1a68672baa686482bb \
+    --hash=sha256:f917c1180fdb8623c2b75a99192f4025e412597c50b2ac870f156de8fb101119 \
+    --hash=sha256:fc78a84e2dfbc27afe4b2bd7c80c8db9bca75cc5b85df52bfe634596a1da846b \
+    --hash=sha256:ff04ef6eec3eee8a5efef2401495967a916feaa353643defcc03fc74fe213b58
+    # via
+    #   deprecated
+    #   python-can
+xlsxwriter==3.2.2 \
+    --hash=sha256:272ce861e7fa5e82a4a6ebc24511f2cb952fde3461f6c6e1a1e81d3272db1471 \
+    --hash=sha256:befc7f92578a85fed261639fb6cde1fd51b79c5e854040847dde59d4317077dc
+    # via -r requirements-actions.in
+yamllint==1.37.0 \
+    --hash=sha256:c03ab4e79ab4af964c8eb16ac9746880fc76a3bb0ffb14925b9a55220ae7dda0 \
+    --hash=sha256:ead81921d4d87216b2528b7a055664708f9fb8267beb0c427cb706ac6ab93580
+    # via -r requirements-actions.in
diff --git a/scripts/requirements-base.txt b/scripts/requirements-base.txt
index 3938fa7b349..6e3cc0616cf 100644
--- a/scripts/requirements-base.txt
+++ b/scripts/requirements-base.txt
@@ -18,11 +18,12 @@ canopen
 packaging
 progress
 patool
-psutil
+psutil>=5.6.6
 pylink-square
 pyserial
-requests
+requests>=2.32.0
 semver
+tqdm>=4.67.1
 
 # for ram/rom reports
 anytree
diff --git a/scripts/requirements-build-test.txt b/scripts/requirements-build-test.txt
index c0f808880fb..0d540dd05c3 100644
--- a/scripts/requirements-build-test.txt
+++ b/scripts/requirements-build-test.txt
@@ -19,3 +19,6 @@ mypy
 
 # used for mocking functions in pytest
 mock>=4.0.1
+
+# used for JUnit XML parsing in CTest harness
+junitparser
diff --git a/scripts/requirements-compliance.txt b/scripts/requirements-compliance.txt
index bc5de4132b8..077b5287902 100644
--- a/scripts/requirements-compliance.txt
+++ b/scripts/requirements-compliance.txt
@@ -5,11 +5,11 @@
 clang-format>=15.0.0
 gitlint
 junitparser>=2
-lxml
+lxml>=5.3.0
 pykwalify
 pylint>=3
-python-magic
 python-magic-bin; sys_platform == "win32"
+python-magic; sys_platform != "win32"
 ruff==0.8.1
 sphinx-lint
 unidiff
diff --git a/scripts/requirements-extras.txt b/scripts/requirements-extras.txt
index dbd4ee589de..78f1ad7dac8 100644
--- a/scripts/requirements-extras.txt
+++ b/scripts/requirements-extras.txt
@@ -4,7 +4,7 @@
 anytree
 
 # to use in ./scripts for memory footprint, code coverage, etc.
-gitpython
+gitpython>=3.1.41
 
 # helper for developers - check git commit messages
 gitlint
@@ -16,10 +16,7 @@ junit2html
 lpc_checksum
 
 # used by scripts/build/gen_cfb_font_header.py - helper script for user
-Pillow>=10.0
-
-# can be used to sign a Zephyr application binary for consumption by a bootloader
-imgtool>=2.1.0
+Pillow>=10.3.0
 
 # used by scripts/release/bug_bash.py for generating top ten bug squashers
 PyGithub
diff --git a/scripts/requirements-run-test.txt b/scripts/requirements-run-test.txt
index 9aa23847f8a..08ff89b0c54 100644
--- a/scripts/requirements-run-test.txt
+++ b/scripts/requirements-run-test.txt
@@ -12,7 +12,7 @@ tabulate
 cbor>=1.0.0
 
 # use for twister
-psutil
+psutil>=5.6.6
 
 # used for CAN <=> host testing
 python-can>=4.3.0
diff --git a/scripts/schemas/build-schema.yml b/scripts/schemas/build-schema.yml
index 93e78d5bc6b..078cca85782 100644
--- a/scripts/schemas/build-schema.yml
+++ b/scripts/schemas/build-schema.yml
@@ -82,6 +82,19 @@ mapping:
             type: seq
             sequence:
               - type: str
+      llext-edk:
+        type: map
+        mapping:
+          cflags:
+            type: seq
+            sequence:
+              - type: str
+          file:
+            type: str
+          include-dirs:
+            type: seq
+            sequence:
+              - type: str
       sysbuild:
         type: bool
       toolchain:
diff --git a/scripts/schemas/patch-schema.yml b/scripts/schemas/patch-schema.yml
index 201227368e5..f74a589f706 100644
--- a/scripts/schemas/patch-schema.yml
+++ b/scripts/schemas/patch-schema.yml
@@ -11,7 +11,7 @@ schema;patch-schema:
     - type: map
       mapping:
 
-        # The path to the patch file, relative to the root of the module
+        # The path to the patch file, relative to patch-base
         # E.g. zephyr/kernel-pipe-fix-not-k-no-wait-and-ge-min-xfer-bytes.patch
         path:
           required: true
diff --git a/scripts/schemas/twister/test-config-schema.yaml b/scripts/schemas/twister/test-config-schema.yaml
index d8e29204e40..24a92c34361 100644
--- a/scripts/schemas/twister/test-config-schema.yaml
+++ b/scripts/schemas/twister/test-config-schema.yaml
@@ -4,6 +4,15 @@
 
 type: map
 mapping:
+  "options":
+    type: map
+    required: false
+    mapping:
+      "integration_mode":
+        type: seq
+        required: false
+        sequence:
+          - type: str
   "platforms":
     type: map
     required: false
diff --git a/scripts/schemas/twister/testsuite-schema.yaml b/scripts/schemas/twister/testsuite-schema.yaml
index bbbf47b5d92..796c342faa5 100644
--- a/scripts/schemas/twister/testsuite-schema.yaml
+++ b/scripts/schemas/twister/testsuite-schema.yaml
@@ -70,6 +70,9 @@ schema;scenario-schema:
     "extra_sections":
       type: any
       required: false
+    "expect_reboot":
+      type: bool
+      required: false
     "required_snippets":
       type: seq
       required: false
@@ -107,6 +110,23 @@ schema;scenario-schema:
       type: map
       required: false
       mapping:
+        "power_measurements":
+          type: any
+          required: false
+        "shell_commands_file":
+          type: str
+          required: false
+        "shell_commands":
+          type: seq
+          required: false
+          sequence:
+            - type: map
+              mapping:
+                "command":
+                  type: str
+                  required: true
+                "expected":
+                  type: str
         "type":
           type: str
           required: false
@@ -130,6 +150,11 @@ schema;scenario-schema:
           type: str
           enum: ["function", "class", "module", "package", "session"]
           required: false
+        "ctest_args":
+          type: seq
+          required: false
+          sequence:
+            - type: str
         "regex":
           type: seq
           required: false
@@ -146,8 +171,13 @@ schema;scenario-schema:
           required: false
           mapping:
             "regex":
-              type: str
+              type: seq
               required: true
+              sequence:
+                - type: str
+            "merge":
+              type: bool
+              required: false
             "as_json":
               type: seq
               required: false
diff --git a/scripts/set_assignees.py b/scripts/set_assignees.py
index f9fa1769a8d..a428f102cfe 100755
--- a/scripts/set_assignees.py
+++ b/scripts/set_assignees.py
@@ -136,7 +136,13 @@ def process_pr(gh, maintainer_file, number):
             if pr.user.login in area.maintainers:
                 # submitter = assignee, try to pick next area and
                 # assign someone else other than the submitter
-                continue
+                # when there also other maintainers for the area
+                # assign them
+                if len(area.maintainers) > 1:
+                    assignees = area.maintainers.copy()
+                    assignees.remove(pr.user.login)
+                else:
+                    continue
             else:
                 assignees = area.maintainers
 
diff --git a/scripts/tests/twister/conftest.py b/scripts/tests/twister/conftest.py
index 7c91be6ffc5..f45e596f5a0 100644
--- a/scripts/tests/twister/conftest.py
+++ b/scripts/tests/twister/conftest.py
@@ -4,12 +4,13 @@
 # SPDX-License-Identifier: Apache-2.0
 
 '''Common fixtures for use in testing the twister tool.'''
-
+import logging
 import os
 import sys
 import pytest
 
 pytest_plugins = ["pytester"]
+logging.getLogger("twister").setLevel(logging.DEBUG)  # requires for testing twister
 
 ZEPHYR_BASE = os.getenv("ZEPHYR_BASE")
 sys.path.insert(0, os.path.join(ZEPHYR_BASE, "scripts/pylib/twister"))
diff --git a/scripts/tests/twister/pytest_integration/test_harness_pytest.py b/scripts/tests/twister/pytest_integration/test_harness_pytest.py
index 7764b01ec26..1233a732304 100644
--- a/scripts/tests/twister/pytest_integration/test_harness_pytest.py
+++ b/scripts/tests/twister/pytest_integration/test_harness_pytest.py
@@ -18,6 +18,7 @@
 def testinstance() -> TestInstance:
     testsuite = TestSuite('.', 'samples/hello', 'unit.test')
     testsuite.harness_config = {}
+    testsuite.harness = 'pytest'
     testsuite.ignore_faults = False
     testsuite.sysbuild = False
     platform = Platform()
diff --git a/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_1.yaml b/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_1.yaml
index b801812080c..fd48fa43d97 100644
--- a/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_1.yaml
+++ b/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_1.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 256
 flash: 1024
 supported:
diff --git a/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_2.yaml b/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_2.yaml
index 7336ba1c2f4..78f7c3892cc 100644
--- a/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_2.yaml
+++ b/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_2.yaml
@@ -5,7 +5,6 @@ arch: x86
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 256
 flash: 1024
 supported:
diff --git a/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_3.yaml b/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_3.yaml
index 57118726f3c..2897ea8c130 100644
--- a/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_3.yaml
+++ b/scripts/tests/twister/test_data/boards/1_level/2_level/board_config_3.yaml
@@ -5,7 +5,6 @@ arch: arm
 toolchain:
   - zephyr
   - gnuarmemb
-  - xtools
 ram: 256
 flash: 1024
 supported:
diff --git a/scripts/tests/twister/test_harness.py b/scripts/tests/twister/test_harness.py
index 7ff006d9278..3283ff2085a 100644
--- a/scripts/tests/twister/test_harness.py
+++ b/scripts/tests/twister/test_harness.py
@@ -61,26 +61,77 @@ def process_logs(harness, logs):
 
 
 TEST_DATA_RECORDING = [
-    ([""], "^START:(?P<foo>.*):END", [], None),
-    (["START:bar:STOP"], "^START:(?P<foo>.*):END", [], None),
-    (["START:bar:END"], "^START:(?P<foo>.*):END", [{"foo": "bar"}], None),
+    ([""], ["^START:(?P<foo>.*):END"], [], None, None),
+    (["START:bar:STOP"], ["^START:(?P<foo>.*):END"], [], None, None),
+    (["START:bar:END"], ["^START:(?P<foo>.*):END"], [{"foo": "bar"}], None, None),
     (
         ["START:bar:baz:END"],
-        "^START:(?P<foo>.*):(?P<boo>.*):END",
+        ["^START:(?P<foo>.*):(?P<boo>.*):END"],
         [{"foo": "bar", "boo": "baz"}],
         None,
+        None,
+    ),
+    (
+        ["START:bar:END"],
+        ["^(START:(?P<foo>[a-z]+):END)|(START:(?P<boo>[0-9]+):END)"],
+        [{"foo": "bar", "boo": ""}],
+        None,
+        None,
+    ),
+    (
+        ["START:bar:baz:END"],
+        ["^START:(?P<foo>.*):baz:END", "^START:bar:(?P<boo>.*):END"],
+        [{"foo": "bar"}, {"boo": "baz"}],
+        None,
+        None,
+    ),
+    (
+        ["START:bar:END", "START:123:END"],
+        ["^START:(?P<foo>[a-z]+):END", "^START:(?P<boo>[0-9]+):END"],
+        [{"foo": "bar"}, {"boo": "123"}],
+        None,
+        None,
+    ),
+    (
+        ["START:bar:END", "START:123:END"],
+        ["^START:(?P<foo>[a-z]+):END", "^START:(?P<foo>[0-9]+):END"],
+        [{"foo": "bar"}, {"foo": "123"}],
+        None,
+        None,
+    ),
+    (
+        ["START:bar:END", "START:123:END"],
+        ["^START:(?P<foo>[a-z]+):END", "^START:(?P<foo>[0-9]+):END"],
+        [{"foo": ["bar", "123"]}],
+        None,
+        True,
+    ),
+    (
+        ["START:bar:baz:END"],
+        ["^START:(?P<foo>.*):baz:END", "^START:bar:(?P<boo>.*):END"],
+        [{"foo": "bar", "boo": "baz"}],
+        None,
+        True,
+    ),
+    (
+        ["START:bar:baz:END"],
+        ["^START:(?P<foo>.*):baz:END", "^START:bar:(?P<foo>.*):END"],
+        [{"foo": ["bar", "baz"]}],
+        None,
+        True,
     ),
     (
         ["START:bar:baz:END", "START:may:jun:END"],
-        "^START:(?P<foo>.*):(?P<boo>.*):END",
+        ["^START:(?P<foo>.*):(?P<boo>.*):END"],
         [{"foo": "bar", "boo": "baz"}, {"foo": "may", "boo": "jun"}],
         None,
+        None,
     ),
-    (["START:bar:END"], "^START:(?P<foo>.*):END", [{"foo": "bar"}], []),
-    (["START:bar:END"], "^START:(?P<foo>.*):END", [{"foo": "bar"}], ["boo"]),
+    (["START:bar:END"], ["^START:(?P<foo>.*):END"], [{"foo": "bar"}], [], None),
+    (["START:bar:END"], ["^START:(?P<foo>.*):END"], [{"foo": "bar"}], ["boo"], None),
     (
         ["START:bad_json:END"],
-        "^START:(?P<foo>.*):END",
+        ["^START:(?P<foo>.*):END"],
         [
             {
                 "foo": {
@@ -92,37 +143,66 @@ def process_logs(harness, logs):
             }
         ],
         ["foo"],
+        None,
     ),
-    (["START::END"], "^START:(?P<foo>.*):END", [{"foo": {}}], ["foo"]),
+    (["START::END"], ["^START:(?P<foo>.*):END"], [{"foo": {}}], ["foo"], None),
     (
         ['START: {"one":1, "two":2} :END'],
-        "^START:(?P<foo>.*):END",
+        ["^START:(?P<foo>.*):END"],
         [{"foo": {"one": 1, "two": 2}}],
         ["foo"],
+        None,
     ),
     (
         ['START: {"one":1, "two":2} :STOP:oops:END'],
-        "^START:(?P<foo>.*):STOP:(?P<boo>.*):END",
+        ["^START:(?P<foo>.*):STOP:(?P<boo>.*):END"],
         [{"foo": {"one": 1, "two": 2}, "boo": "oops"}],
         ["foo"],
+        None,
     ),
     (
         ['START: {"one":1, "two":2} :STOP:{"oops":0}:END'],
-        "^START:(?P<foo>.*):STOP:(?P<boo>.*):END",
+        ["^START:(?P<foo>.*):STOP:(?P<boo>.*):END"],
         [{"foo": {"one": 1, "two": 2}, "boo": {"oops": 0}}],
         ["foo", "boo"],
+        None,
+    ),
+    (
+        ['START: {"one":1, "two":2} :STOP:{"oops":0}:END'],
+        ["^START:(?P<foo>.*):STOP:.*:END",
+         "^START:.*:STOP:(?P<boo>.*):END"
+        ],
+        [{"foo": {"one": 1, "two": 2}}, {"boo": {"oops": 0}}],
+        ["foo", "boo"],
+        None,
+    ),
+    (
+        ['START: {"one":1, "two":2} :STOP:{"oops":0}:END'],
+        ["^START:(?P<foo>.*):STOP:.*:END",
+         "^START:.*:STOP:(?P<foo>.*):END"
+        ],
+        [{"foo": [{"one": 1, "two": 2}, {"oops": 0}]}],
+        ["foo"],
+        True,
     ),
 ]
 
 
 @pytest.mark.parametrize(
-    "lines, pattern, expected_records, as_json",
+    "lines, patterns, expected_records, as_json, merge",
     TEST_DATA_RECORDING,
     ids=[
         "empty",
         "no match",
         "match 1 field",
         "match 2 fields",
+        "2 or-ed groups one miss",
+        "one line, two patters, match 2 fields -> 2 records",
+        "two lines, two patters -> 2 records",
+        "two lines, two patters same field -> 2 same records",
+        "two lines, two patters same field merge -> 1 records 2 values",
+        "one line, two patters, match 2 fields, merge -> 1 record",
+        "one line, two patters, match 1 field, merge -> 1 record list",
         "match 2 records",
         "as_json empty",
         "as_json no such field",
@@ -131,13 +211,16 @@ def process_logs(harness, logs):
         "simple json",
         "plain field and json field",
         "two json fields",
+        "two json fields in two patterns -> 2 records",
+        "two json fields in two patterns merge -> 1 records 2 items",
     ],
 )
-def test_harness_parse_record(lines, pattern, expected_records, as_json):
+def test_harness_parse_record(lines, patterns, expected_records, as_json, merge):
     harness = Harness()
-    harness.record = {"regex": pattern}
-    harness.record_pattern = re.compile(pattern)
+    harness.record = {"regex": patterns}
+    harness.record_patterns = [re.compile(p) for p in patterns]
 
+    harness.record_merge = merge
     harness.record_as_json = as_json
     if as_json is not None:
         harness.record["as_json"] = as_json
@@ -651,7 +734,7 @@ def test_get_harness(name):
     ),
     (
         True,
-        "not a ztest and no state for dummy.test_id",
+        "dummy.test_id is not a Ztest, status:passed",
         "START - test_testcase",
         [],
         {},
@@ -662,7 +745,7 @@ def test_get_harness(name):
     ),
     (
         False,
-        "not a ztest and no state for dummy.test_id",
+        "dummy.test_id is not a Ztest, status:passed",
         "START - test_testcase",
         [],
         {},
@@ -673,7 +756,7 @@ def test_get_harness(name):
     ),
     (
         True,
-        "not a ztest and no state for dummy.test_id",
+        "dummy.test_id is not a Ztest, status:failed",
         "START - test_testcase",
         [],
         {},
diff --git a/scripts/tests/twister/test_platform.py b/scripts/tests/twister/test_platform.py
index c4b9858d8b1..cdbfd15d20c 100644
--- a/scripts/tests/twister/test_platform.py
+++ b/scripts/tests/twister/test_platform.py
@@ -11,10 +11,13 @@
 import mock
 import pytest
 
+from contextlib import nullcontext
+from pykwalify.errors import SchemaError
+
 ZEPHYR_BASE = os.getenv("ZEPHYR_BASE")
 sys.path.insert(0, os.path.join(ZEPHYR_BASE, "scripts/pylib/twister"))
 
-from twisterlib.platform import Platform, Simulator
+from twisterlib.platform import Platform, Simulator, generate_platforms
 
 
 TESTDATA_1 = [
@@ -129,3 +132,363 @@ def xtest_platform_load(platform_text, expected_data, expected_repr):
             assert att == v
 
     assert platform.__repr__() == expected_repr
+
+
+TESTDATA_2 = [
+    (
+        ['m0'],
+        None,
+        {
+            'p1e1/s1', 'p1e2/s1', 'p2/s1', 'p3@A/s2/c1', 'p3@B/s2/c1',
+        },
+    ),
+    (
+        ['m0', 'm1'],
+        None,
+        {
+            'p1e1/s1', 'p1e2/s1', 'p2/s1', 'p3@A/s2/c1', 'p3@B/s2/c1',
+            'p1e1/s1/v1', 'p1e1/s1/v2', 'p1e2/s1/v1', 'p2/s1/v1',
+        },
+    ),
+    (
+        ['m0', 'm1', 'm2'],
+        None,
+        {
+            'p1e1/s1', 'p1e2/s1', 'p2/s1', 'p3@A/s2/c1', 'p3@B/s2/c1',
+            'p1e1/s1/v1', 'p1e1/s1/v2', 'p1e2/s1/v1', 'p2/s1/v1',
+            'p3@A/s2/c2', 'p3@B/s2/c2', 'p4/s1',
+        },
+    ),
+    (
+        ['m0', 'm3'],
+        Exception("Duplicate platform identifier p1e1/s1 found"),
+        None,
+    ),
+    (
+        ['m0', 'm1', 'm4'],
+        Exception("Duplicate platform identifier p1e2/s1/v1 found"),
+        None,
+    ),
+    (
+        ['m0', 'm5'],
+        SchemaError(), # Unknown message as this is raised externally
+        None,
+    ),
+]
+
+@pytest.mark.parametrize(
+    'roots, expected_exception, expected_platform_names',
+    TESTDATA_2,
+    ids=[
+        'default board root',
+        '1 extra board root',
+        '2 extra board roots',
+        '1 extra board root, duplicate platform',
+        '2 extra board roots, duplicate platform',
+        '1 extra board root, malformed yaml',
+    ]
+)
+def test_generate_platforms(
+    tmp_path,
+    roots,
+    expected_exception,
+    expected_platform_names,
+):
+    tmp_files = {
+        'm0/boards/zephyr/p1/board.yml': """\
+boards:
+  - name: p1e1
+    vendor: zephyr
+    socs:
+      - name: s1
+  - name: p1e2
+    vendor: zephyr
+    socs:
+      - name: s1
+""",
+        'm0/boards/zephyr/p1/twister.yaml': """\
+type: native
+arch: x86
+variants:
+  p1e1:
+    twister: False
+  p1e2:
+    sysbuild: True
+""",
+        'm0/boards/zephyr/p2/board.yml': """\
+boards:
+  - name: p2
+    vendor: zephyr
+    socs:
+      - name: s1
+""",
+        'm0/boards/zephyr/p2/p2.yaml': """\
+identifier: p2/s1
+type: sim
+arch: x86
+vendor: vendor2
+testing:
+  default: True
+""",
+        'm0/boards/arm/p3/board.yml': """\
+board:
+  name: p3
+  vendor: arm
+  revision:
+    format: letter
+    default: "A"
+    revisions:
+      - name: "A"
+      - name: "B"
+  socs:
+    - name: s2
+""",
+        'm0/boards/arm/p3/twister.yaml': """\
+type: unit
+arch: arm
+vendor: vendor3
+sysbuild: True
+variants:
+  p3/s2/c1:
+    testing:
+      timeout_multiplier: 2.71828
+  p3@B/s2/c1:
+    testing:
+      timeout_multiplier: 3.14159
+""",
+        'm0/soc/zephyr/soc.yml': """\
+family:
+  - name: zephyr
+    series:
+      - name: zephyr_testing
+        socs:
+          - name: s1
+          - name: s2
+            cpuclusters:
+              - name: c1
+""",
+        'm1/boards/zephyr/p1e1/board.yml': """\
+board:
+  extend: p1e1
+  variants:
+    - name: v1
+      qualifier: s1
+    - name: v2
+      qualifier: s1
+""",
+        'm1/boards/zephyr/p1e1/twister.yaml': """\
+variants:
+  p1e1/s1/v1:
+    testing:
+      default: True
+""",
+        'm1/boards/zephyr/p1e2/board.yml': """\
+board:
+  extend: p1e2
+  variants:
+    - name: v1
+      qualifier: s1
+""",
+        'm1/boards/zephyr/p2/board.yml': """\
+board:
+  extend: p2
+  variants:
+    - name: v1
+      qualifier: s1
+""",
+        'm1/boards/zephyr/p2/p2_s1_v1.yaml': """\
+identifier: p2/s1/v1
+""",
+        'm2/boards/misc/board.yml': """\
+boards:
+  - extend: p3
+  - name: p4
+    vendor: misc
+    socs:
+      - name: s1
+""",
+        'm2/boards/misc/twister.yaml': """\
+type: qemu
+arch: riscv
+vendor: vendor4
+simulation:
+  - name: qemu
+variants:
+  p3@A/s2/c2:
+    sysbuild: False
+""",
+        'm2/soc/zephyr/soc.yml': """\
+socs:
+  - extend: s2
+    cpuclusters:
+      - name: c2
+""",
+        'm3/boards/zephyr/p1e1/board.yml': """\
+board:
+  extend: p1e1
+""",
+        'm3/boards/zephyr/p1e1/twister.yaml': """\
+variants:
+  p1e1/s1:
+    name: Duplicate Platform
+""",
+        'm4/boards/zephyr/p1e2/board.yml': """\
+board:
+  extend: p2
+""",
+        'm4/boards/zephyr/p1e2/p1e2_s1_v1.yaml': """\
+identifier: p1e2/s1/v1
+""",
+        'm5/boards/zephyr/p2/p2-2.yaml': """\
+testing:
+  ć#@%!#!#^#@%@:1.0
+identifier: p2_2
+type: sim
+arch: x86
+vendor: vendor2
+""",
+        'm5/boards/zephyr/p2/board.yml': """\
+board:
+  extend: p2
+""",
+    }
+
+    for filename, content in tmp_files.items():
+        (tmp_path / filename).parent.mkdir(parents=True, exist_ok=True)
+        (tmp_path / filename).write_text(content)
+
+    roots = list(map(tmp_path.joinpath, roots))
+    with pytest.raises(type(expected_exception)) if \
+          expected_exception else nullcontext() as exception:
+        platforms = list(generate_platforms(board_roots=roots, soc_roots=roots, arch_roots=roots))
+
+    if expected_exception:
+        if expected_exception.args:
+            assert str(expected_exception) == str(exception.value)
+        return
+
+    platform_names = {platform.name for platform in platforms}
+    assert len(platforms) == len(platform_names)
+    assert platform_names == expected_platform_names
+
+    expected_data = {
+        'p1e1/s1': {
+            'aliases': ['p1e1/s1', 'p1e1'],
+            # m0/boards/zephyr/p1/board.yml
+            'vendor': 'zephyr',
+            # m0/boards/zephyr/p1/twister.yaml (base + variant)
+            'twister': False,
+            'arch': 'x86',
+            'type': 'native',
+        },
+        'p1e2/s1': {
+            'aliases': ['p1e2/s1', 'p1e2'],
+            # m0/boards/zephyr/p1/board.yml
+            'vendor': 'zephyr',
+            # m0/boards/zephyr/p1/twister.yaml (base + variant)
+            'sysbuild': True,
+            'arch': 'x86',
+            'type': 'native',
+        },
+        'p1e1/s1/v1': {
+            'aliases': ['p1e1/s1/v1'],
+            # m0/boards/zephyr/p1/board.yml
+            'vendor': 'zephyr',
+            # m0/boards/zephyr/p1/twister.yaml (base)
+            # m1/boards/zephyr/p1e1/twister.yaml (variant)
+            'default': True,
+            'arch': 'x86',
+            'type': 'native',
+        },
+        'p1e1/s1/v2': {
+            'aliases': ['p1e1/s1/v2'],
+            # m0/boards/zephyr/p1/board.yml
+            'vendor': 'zephyr',
+            # m0/boards/zephyr/p1/twister.yaml (base)
+            'arch': 'x86',
+            'type': 'native',
+        },
+        'p1e2/s1/v1': {
+            'aliases': ['p1e2/s1/v1'],
+            # m0/boards/zephyr/p1/board.yml
+            'vendor': 'zephyr',
+            # m0/boards/zephyr/p1/twister.yaml (base)
+            'arch': 'x86',
+            'type': 'native',
+        },
+        'p2/s1': {
+            'aliases': ['p2/s1', 'p2'],
+            # m0/boards/zephyr/p2/board.yml
+            'vendor': 'zephyr',
+            # m0/boards/zephyr/p2/p2.yaml
+            'default': True,
+            'arch': 'x86',
+            'type': 'sim',
+        },
+        'p2/s1/v1': {
+            'aliases': ['p2/s1/v1'],
+            # m0/boards/zephyr/p2/board.yml
+            'vendor': 'zephyr',
+            # m1/boards/zephyr/p2/p2_s1_v1.yaml
+        },
+        'p3@A/s2/c1': {
+            'aliases': ['p3@A/s2/c1', 'p3/s2/c1'],
+            # m0/boards/arm/p3/board.yml
+            'vendor': 'arm',
+            # m0/boards/arm/p3/twister.yaml (base + variant)
+            'sysbuild': True,
+            'timeout_multiplier': 2.71828,
+            'arch': 'arm',
+            'type': 'unit',
+        },
+        'p3@B/s2/c1': {
+            'aliases': ['p3@B/s2/c1'],
+            # m0/boards/arm/p3/board.yml
+            'vendor': 'arm',
+            # m0/boards/arm/p3/twister.yaml (base + variant)
+            'sysbuild': True,
+            'timeout_multiplier': 3.14159,
+            'arch': 'arm',
+            'type': 'unit',
+        },
+        'p3@A/s2/c2': {
+            'aliases': ['p3@A/s2/c2', 'p3/s2/c2'],
+            # m0/boards/arm/p3/board.yml
+            'vendor': 'arm',
+            # m0/boards/arm/p3/twister.yaml (base)
+            # m2/boards/misc/twister.yaml (variant)
+            'sysbuild': False,
+            'arch': 'arm',
+            'type': 'unit',
+        },
+        'p3@B/s2/c2': {
+            'aliases': ['p3@B/s2/c2'],
+            # m0/boards/arm/p3/board.yml
+            'vendor': 'arm',
+            # m0/boards/arm/p3/twister.yaml (base)
+            'sysbuild': True,
+            'arch': 'arm',
+            'type': 'unit',
+        },
+        'p4/s1': {
+            'aliases': ['p4/s1', 'p4'],
+            # m2/boards/misc/board.yml
+            'vendor': 'misc',
+            # m2/boards/misc/twister.yaml (base)
+            'arch': 'riscv',
+            'type': 'qemu',
+            'simulators': [Simulator({'name': 'qemu'})],
+            'simulation': 'qemu',
+        },
+    }
+
+    init_platform = Platform()
+    for platform in platforms:
+        expected_platform_data = expected_data[platform.name]
+        for attr, default in vars(init_platform).items():
+            if attr in {'name', 'normalized_name', 'supported_toolchains'}:
+                continue
+            expected = expected_platform_data.get(attr, default)
+            actual = getattr(platform, attr, None)
+            assert expected == actual, \
+                f"expected '{platform}.{attr}' to be '{expected}', was '{actual}'"
diff --git a/scripts/tests/twister/test_runner.py b/scripts/tests/twister/test_runner.py
index b5eec17b9da..0e6227acefe 100644
--- a/scripts/tests/twister/test_runner.py
+++ b/scripts/tests/twister/test_runner.py
@@ -1245,7 +1245,7 @@ def mock_getsize(filename, *args, **kwargs):
         mock.ANY,
         ['run test: dummy instance name',
          'run status: dummy instance name success'],
-        {'op': 'report', 'test': mock.ANY, 'status': 'success', 'reason': 'OK'},
+        {'op': 'coverage', 'test': mock.ANY, 'status': 'success', 'reason': 'OK'},
         'success',
         'OK',
         0,
@@ -1482,6 +1482,7 @@ def mock_getsize(filename, *args, **kwargs):
 def test_projectbuilder_process(
     caplog,
     mocked_jobserver,
+    tmp_path,
     message,
     instance_status,
     instance_reason,
@@ -1529,6 +1530,9 @@ def mock_determine_testcases(res):
     pb.options.prep_artifacts_for_testing = options_prep_artifacts
     pb.options.runtime_artifact_cleanup = options_runtime_artifacts
     pb.options.cmake_only = options_cmake_only
+    pb.options.outdir = tmp_path
+    pb.options.log_file = None
+    pb.options.log_level = "DEBUG"
 
     pb.cmake = mock.Mock(return_value=cmake_res)
     pb.build = mock.Mock(return_value=build_res)
@@ -2253,7 +2257,7 @@ def test_projectbuilder_build(mocked_jobserver):
         234,
         'native_sim',
         'posix',
-        {'CONFIG_FAKE_ENTROPY_NATIVE_POSIX': 'y'},
+        {'CONFIG_FAKE_ENTROPY_NATIVE_SIM': 'y'},
         'pytest',
         True,
         True,
@@ -2268,7 +2272,7 @@ def test_projectbuilder_build(mocked_jobserver):
         None,
         'native_sim',
         'not posix',
-        {'CONFIG_FAKE_ENTROPY_NATIVE_POSIX': 'y'},
+        {'CONFIG_FAKE_ENTROPY_NATIVE_SIM': 'y'},
         'not pytest',
         False,
         False,
@@ -2283,7 +2287,7 @@ def test_projectbuilder_build(mocked_jobserver):
         234,
         'native_sim',
         'posix',
-        {'CONFIG_FAKE_ENTROPY_NATIVE_POSIX': 'y'},
+        {'CONFIG_FAKE_ENTROPY_NATIVE_SIM': 'y'},
         'pytest',
         False,
         False,
@@ -2407,7 +2411,6 @@ def test_projectbuilder_gather_metrics(
         assert instance_mock.metrics['used_rom'] == 0
         assert instance_mock.metrics['available_rom'] == 0
         assert instance_mock.metrics['available_ram'] == 0
-        assert instance_mock.metrics['unrecognized'] == []
 
 
 TESTDATA_16 = [
@@ -2459,15 +2462,12 @@ def test_projectbuilder_calc_size(
                size_calc_mock.get_available_rom()
         assert instance_mock.metrics['available_ram'] == \
                size_calc_mock.get_available_ram()
-        assert instance_mock.metrics['unrecognized'] == \
-               size_calc_mock.unrecognized_sections()
 
     if expect_zeroes:
         assert instance_mock.metrics['used_ram'] == 0
         assert instance_mock.metrics['used_rom'] == 0
         assert instance_mock.metrics['available_rom'] == 0
         assert instance_mock.metrics['available_ram'] == 0
-        assert instance_mock.metrics['unrecognized'] == []
 
     if expect_calcs or expect_zeroes:
         assert instance_mock.metrics['handler_time'] == \
@@ -2570,8 +2570,7 @@ def iteration_increment(value=1, decrement=False):
     assert tr.instances['dummy instance'].metrics == {
         'k': 'v',
         'k2': 'v2',
-        'handler_time': 30,
-        'unrecognized': []
+        'handler_time': 30
     }
 
     assert results_mock().error == 0
diff --git a/scripts/tests/twister/test_testplan.py b/scripts/tests/twister/test_testplan.py
index 2a006043870..73b2673b08e 100644
--- a/scripts/tests/twister/test_testplan.py
+++ b/scripts/tests/twister/test_testplan.py
@@ -1110,167 +1110,7 @@ def test_testplan_add_configurations(
     expected_platform_names,
     expected_defaults
 ):
-    # tmp_path
-    # └ boards  <- board root
-    #   ├ zephyr
-    #   │ ├ p1
-    #   │ | ├ p1e1.yaml
-    #   │ | └ p1e2.yaml
-    #   │ └ p2
-    #   │   ├ p2.yaml
-    #   │   └ p2-1.yaml <- duplicate
-    #   │   └ p2-2.yaml <- load error
-    #   └ arm
-    #     └ p3
-    #       ├ p3.yaml
-    #       └ p3_B.conf
-    tmp_soc_root_dir = tmp_path / 'soc'
-    tmp_soc_root_dir.mkdir()
-
-    tmp_vend1_dir = tmp_soc_root_dir / 'zephyr'
-    tmp_vend1_dir.mkdir()
-
-    tmp_soc1_dir = tmp_vend1_dir / 's1'
-    tmp_soc1_dir.mkdir()
-
-    soc1_yaml = """\
-family:
-  - name: zephyr
-    series:
-      - name: zephyr_testing
-        socs:
-          - name: unit_testing
-"""
-    soc1_yamlfile = tmp_soc1_dir / 'soc.yml'
-    soc1_yamlfile.write_text(soc1_yaml)
-
-    tmp_board_root_dir = tmp_path / 'boards'
-    tmp_board_root_dir.mkdir()
-
-    tmp_vend1_dir = tmp_board_root_dir / 'zephyr'
-    tmp_vend1_dir.mkdir()
-
-    tmp_p1_dir = tmp_vend1_dir / 'p1'
-    tmp_p1_dir.mkdir()
-
-    p1e1_bs_yaml = """\
-boards:
-
-  - name: p1e1
-    vendor: zephyr
-    socs:
-      - name: unit_testing
-  - name: p1e2
-    vendor: zephyr
-    socs:
-      - name: unit_testing
-"""
-    p1e1_yamlfile = tmp_p1_dir / 'board.yml'
-    p1e1_yamlfile.write_text(p1e1_bs_yaml)
-
-    p1e1_yaml = """\
-identifier: p1e1
-name: Platform 1 Edition 1
-type: native
-arch: x86
-vendor: zephyr
-toolchain:
-  - zephyr
-twister: False
-"""
-    p1e1_yamlfile = tmp_p1_dir / 'p1e1.yaml'
-    p1e1_yamlfile.write_text(p1e1_yaml)
-
-    p1e2_yaml = """\
-identifier: p1e2
-name: Platform 1 Edition 2
-type: native
-arch: x86
-vendor: zephyr
-toolchain:
-  - zephyr
-"""
-    p1e2_yamlfile = tmp_p1_dir / 'p1e2.yaml'
-    p1e2_yamlfile.write_text(p1e2_yaml)
-
-    tmp_p2_dir = tmp_vend1_dir / 'p2'
-    tmp_p2_dir.mkdir()
-
-    p2_bs_yaml = """\
-boards:
-
-  - name: p2
-    vendor: zephyr
-    socs:
-      - name: unit_testing
-  - name: p2_2
-    vendor: zephyr
-    socs:
-      - name: unit_testing
-"""
-    p2_yamlfile = tmp_p2_dir / 'board.yml'
-    p2_yamlfile.write_text(p2_bs_yaml)
-
-    p2_yaml = """\
-identifier: p2/unit_testing
-name: Platform 2
-type: sim
-arch: x86
-vendor: vendor2
-toolchain:
-  - zephyr
-testing:
-  default: True
-"""
-    p2_yamlfile = tmp_p2_dir / 'p2.yaml'
-    p2_yamlfile.write_text(p2_yaml)
-
-
-    p2_2_yaml = """\
-testing:
-  ć#@%!#!#^#@%@:1.0
-identifier: p2_2
-name: Platform 2 2
-type: sim
-arch: x86
-vendor: vendor2
-toolchain:
-  - zephyr
-"""
-    p2_2_yamlfile = tmp_p2_dir / 'p2-2.yaml'
-    p2_2_yamlfile.write_text(p2_2_yaml)
-
-    tmp_vend2_dir = tmp_board_root_dir / 'arm'
-    tmp_vend2_dir.mkdir()
-
-    tmp_p3_dir = tmp_vend2_dir / 'p3'
-    tmp_p3_dir.mkdir()
-
-    p3_bs_yaml = """\
-boards:
-  - name: p3
-    vendor: zephyr
-    socs:
-      - name: unit_testing
-"""
-    p3_yamlfile = tmp_p3_dir / 'board.yml'
-    p3_yamlfile.write_text(p3_bs_yaml)
-
-    p3_yaml = """\
-identifier: p3
-name: Platform 3
-type: unit
-arch: arm
-vendor: vendor3
-toolchain:
-  - zephyr
-testing:
-  default: True
-"""
-    p3_yamlfile = tmp_p3_dir / 'p3.yaml'
-    p3_yamlfile.write_text(p3_yaml)
-
-    env = mock.Mock(board_roots=[tmp_board_root_dir],soc_roots=[tmp_path], arch_roots=[tmp_path])
+    env = mock.Mock(board_roots=[tmp_path / 'boards'], soc_roots=[tmp_path], arch_roots=[tmp_path])
 
     testplan = TestPlan(env=env)
 
@@ -1281,8 +1121,23 @@ def test_testplan_add_configurations(
         }
     }
 
-
-    testplan.add_configurations()
+    def mock_gen_plat(board_roots, soc_roots, arch_roots):
+        assert [tmp_path] == board_roots
+        assert [tmp_path] == soc_roots
+        assert [tmp_path] == arch_roots
+
+        platforms = [
+            mock.Mock(aliases=['p1e1/unit_testing', 'p1e1'], twister=False, default=False),
+            mock.Mock(aliases=['p1e2/unit_testing', 'p1e2'], twister=True, default=False),
+            mock.Mock(aliases=['p2/unit_testing', 'p2'], twister=True, default=True),
+            mock.Mock(aliases=['p3/unit_testing', 'p3'], twister=True, default=True),
+        ]
+        for platform in platforms:
+            type(platform).name = mock.PropertyMock(return_value=platform.aliases[0])
+            yield platform
+
+    with mock.patch('twisterlib.testplan.generate_platforms', mock_gen_plat):
+        testplan.add_configurations()
 
     if expected_defaults is not None:
         print(expected_defaults)
diff --git a/scripts/tests/twister_blackbox/conftest.py b/scripts/tests/twister_blackbox/conftest.py
index d856261f276..0fd73927c6f 100644
--- a/scripts/tests/twister_blackbox/conftest.py
+++ b/scripts/tests/twister_blackbox/conftest.py
@@ -12,6 +12,8 @@
 import pytest
 import sys
 
+logging.getLogger("twister").setLevel("DEBUG")  # requires for testing twister
+
 ZEPHYR_BASE = os.getenv('ZEPHYR_BASE')
 TEST_DATA = os.path.join(ZEPHYR_BASE, 'scripts', 'tests',
                         'twister_blackbox', 'test_data')
@@ -84,4 +86,10 @@ def provide_out(tmp_path, request):
     # After
     # We're operating in temp, so it is not strictly necessary
     # but the files can get large quickly as we do not need them after the test.
+    loggers = [logging.getLogger(name) for name in logging.root.manager.loggerDict]
+    for logg in loggers:
+        handls = logg.handlers[:]
+        for handl in handls:
+            logg.removeHandler(handl)
+            handl.close()
     shutil.rmtree(out_container_path)
diff --git a/scripts/tests/twister_blackbox/test_coverage.py b/scripts/tests/twister_blackbox/test_coverage.py
index 5c1b6cec72d..aeb41e63daf 100644
--- a/scripts/tests/twister_blackbox/test_coverage.py
+++ b/scripts/tests/twister_blackbox/test_coverage.py
@@ -13,8 +13,7 @@
 import sys
 import json
 
-# pylint: disable=duplicate-code
-# pylint: disable=no-name-in-module
+# pylint: disable=duplicate-code, disable=no-name-in-module
 from conftest import TEST_DATA, ZEPHYR_BASE, testsuite_filename_mock, clear_log_in_test
 from twisterlib.testplan import TestPlan
 
@@ -123,7 +122,7 @@ class TestCoverage:
             os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic', 'group2'),
             ['qemu_x86'],
             'gcovr',
-            'Running gcovr -r'
+            'Running: gcovr '
         ),
         (
             os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic', 'group2'),
@@ -136,7 +135,7 @@ class TestCoverage:
         (
             os.path.join(TEST_DATA, 'tests', 'dummy', 'agnostic', 'group2'),
             ['qemu_x86'],
-            ['The specified file does not exist.', r'\[Errno 13\] Permission denied:'],
+            ['GCOVR failed with '],
         )
     ]
     TESTDATA_7 = [
diff --git a/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/test_sample.yaml b/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/test_sample.yaml
index 86b9314f444..4c1d86a7a14 100644
--- a/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/test_sample.yaml
+++ b/scripts/tests/twister_blackbox/test_data/samples/pytest/shell/test_sample.yaml
@@ -4,7 +4,7 @@ tests:
     min_ram: 40
     harness: pytest
     extra_configs:
-      - arch:posix:CONFIG_NATIVE_UART_0_ON_STDINOUT=y
+      - arch:posix:CONFIG_UART_NATIVE_PTY_0_ON_STDINOUT=y
     integration_platforms:
       - native_sim
       - qemu_cortex_m3
diff --git a/scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/Kconfig b/scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/Kconfig
index db9be4ed558..96c1c1960d2 100644
--- a/scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/Kconfig
+++ b/scripts/tests/twister_blackbox/test_data/tests/seed_native_sim/dummy/Kconfig
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 # Copyright (c) 2024 Intel Corporation
 
-config FAKE_ENTROPY_NATIVE_POSIX
+config FAKE_ENTROPY_NATIVE_SIM
 	default y
 
 source "Kconfig.zephyr"
diff --git a/scripts/tests/twister_blackbox/test_outfile.py b/scripts/tests/twister_blackbox/test_outfile.py
index 57a874041cb..590e0c8f58a 100644
--- a/scripts/tests/twister_blackbox/test_outfile.py
+++ b/scripts/tests/twister_blackbox/test_outfile.py
@@ -102,8 +102,8 @@ def test_runtime_artifact_cleanup(self, out_path):
         zephyr_listdir = os.listdir(os.path.join(sample_path, 'zephyr'))
 
         expected_contents = ['CMakeFiles', 'handler.log', 'build.ninja', 'CMakeCache.txt',
-                             'zephyr', 'build.log']
-        expected_zephyr_contents = ['.config']
+                             'zephyr', 'build.log', 'build_info.yml']
+        expected_zephyr_contents = ['.config', 'zephyr.dts']
 
         assert all([content in expected_zephyr_contents for content in zephyr_listdir]), \
                'Cleaned zephyr directory has unexpected files.'
diff --git a/scripts/tests/twister_blackbox/test_output.py b/scripts/tests/twister_blackbox/test_output.py
index a1686b343fb..5babfa96620 100644
--- a/scripts/tests/twister_blackbox/test_output.py
+++ b/scripts/tests/twister_blackbox/test_output.py
@@ -132,7 +132,11 @@ def test_inline_logs(self, out_path):
             r'-- Configuring done \([0-9.]+s\)',
             r'-- Generating done \([0-9.]+s\)',
             # Cache location may vary between CI runs
-            r'^.*-- Cache files will be written to:.*$'
+            r'^.*-- Cache files will be written to:.*$',
+            # List of built C object may differ between runs.
+            # See: Issue #87769.
+            # Probable culprits: the cache mechanism, build error
+            r'^Building C object .*$'
         ]
         for pattern in removal_patterns:
             c_pattern = re.compile(pattern, flags=re.MULTILINE)
diff --git a/scripts/tests/twister_blackbox/test_report.py b/scripts/tests/twister_blackbox/test_report.py
index c2ed41f2747..83d5942c855 100644
--- a/scripts/tests/twister_blackbox/test_report.py
+++ b/scripts/tests/twister_blackbox/test_report.py
@@ -114,8 +114,8 @@ class TestReport:
             os.path.join(TEST_DATA, 'tests', 'one_fail_two_error_one_pass'),
             ['qemu_x86/atom'],
             [r'one_fail_two_error_one_pass.agnostic.group1.subgroup2 on qemu_x86/atom FAILED \(.*\)',
-            r'one_fail_two_error_one_pass.agnostic.group1.subgroup3 on qemu_x86/atom ERROR \(Build failure\)',
-            r'one_fail_two_error_one_pass.agnostic.group1.subgroup4 on qemu_x86/atom ERROR \(Build failure\)'],
+            r'one_fail_two_error_one_pass.agnostic.group1.subgroup3 on qemu_x86/atom ERROR \(Build failure.*\)',
+            r'one_fail_two_error_one_pass.agnostic.group1.subgroup4 on qemu_x86/atom ERROR \(Build failure.*\)'],
         )
     ]
 
diff --git a/scripts/utils/migrate_posix_kconfigs.py b/scripts/utils/migrate_posix_kconfigs.py
index d7667543c24..fdbb768c237 100644
--- a/scripts/utils/migrate_posix_kconfigs.py
+++ b/scripts/utils/migrate_posix_kconfigs.py
@@ -6,7 +6,7 @@
 
 Usage::
 
-    python $ZEPHYR_BASE/scripts/utils/migrate_posix_kconfigs.py -r root_path
+    python $ZEPHYR_BASE/scripts/utils/migrate_posix_kconfigs.py --root root_path --dry-run
 
 The utility will process c, cpp, h, hpp, rst, conf, CMakeLists.txt,
 yml, yaml and Kconfig files.
@@ -85,6 +85,7 @@ def process_file(path):
         with open(path) as f:
             lines = f.readlines()
 
+            lineno = 1
             for line in lines:
                 longest = ""
                 length = 0
@@ -93,17 +94,24 @@ def process_file(path):
                         length = len(m)
                         longest = m
 
+                # TIMER is just way too frequent an occurrence. Skip it.
+                skip = {"TIMER"}
                 if length != 0:
-                    modified = True
-                    line = line.replace(longest, REPLACEMENTS[longest])
-                    msg = MESSAGES.get(longest)
-                    if msg:
-                        print(
-                            f"Notice: {longest} -> {REPLACEMENTS[longest]}: {msg}")
-
+                    if longest in skip:
+                        pass
+                    else:
+                        modified = True
+                        old = line
+                        line = line.replace(longest, REPLACEMENTS[longest])
+                        msg = MESSAGES.get(longest)
+                        if msg:
+                            print(f"{path}:{lineno}:old:{old.strip()}")
+                            print(f"{path}:{lineno}:new:{line.strip()}")
+
+                lineno += 1
                 output.append(line)
 
-        if modified is False:
+        if modified is False or args.dry_run:
             return
 
         with open(path, "w") as f:
@@ -131,6 +139,11 @@ def process_tree(project):
         type=Path,
         required=True,
         help="Zephyr-based project path")
+    parser.add_argument(
+        "-d",
+        "--dry-run",
+        action="store_true",
+        help="log potential changes without modifying files")
     args = parser.parse_args()
 
     process_tree(args.root)
diff --git a/scripts/utils/tls_creds_installer.py b/scripts/utils/tls_creds_installer.py
index 4e3d0d258b3..82788523031 100755
--- a/scripts/utils/tls_creds_installer.py
+++ b/scripts/utils/tls_creds_installer.py
@@ -65,13 +65,28 @@ def write_credential(self, sectag, cred_type, cred_text):
         for c in range(chunks):
             chunk = encoded[c * TLS_CRED_CHUNK_SIZE : (c + 1) * TLS_CRED_CHUNK_SIZE]
             self.write_raw(f"cred buf {chunk}")
-            self.serial_wait_for_response("Stored")
+            result, output = self.serial_wait_for_response("Stored", "RX ring buffer full")
+            if not result:
+                logging.error("Failed to store chunk in the device: unknown error")
+            if output and b"RX ring buffer full" in output:
+                logging.error(f"Failed to store chunk in the device: {output}")
+                return False
+        if not 0 <= cred_type < len(TLS_CRED_TYPES):
+            logger.error(
+                f"Invalid credential type: {cred_type}. Range [0, {len(TLS_CRED_TYPES) - 1}]."
+            )
+            return False
         self.write_raw(f"cred add {sectag} {TLS_CRED_TYPES[cred_type]} DEFAULT bint")
-        result, _ = self.serial_wait_for_response("Added TLS credential")
+        result, _ = self.serial_wait_for_response("Added TLS credential", "already exists")
         time.sleep(1)
         return result
 
     def delete_credential(self, sectag, cred_type):
+        if not 0 <= cred_type < len(TLS_CRED_TYPES):
+            logger.error(
+                f"Invalid credential type: {cred_type}. Range [0, {len(TLS_CRED_TYPES) - 1}]."
+            )
+            return False
         self.write_raw(f'cred del {sectag} {TLS_CRED_TYPES[cred_type]}')
         result, _ = self.serial_wait_for_response(
             "Deleted TLS credential", "There is no TLS credential"
@@ -94,7 +109,11 @@ def check_credential_exists(self, sectag, cred_type, get_hash=True):
             return True, None
 
         data = output.decode().split(",")
-        hash = data[2].strip()
+        logger.debug(f"Cred list output: {data}")
+        if len(data) < 4:
+            logger.error("Invalid output format from device, skipping hash check.")
+            return False, None
+        cred_hash = data[2].strip()
         status_code = data[3].strip()
 
         if status_code != "0":
@@ -102,19 +121,19 @@ def check_credential_exists(self, sectag, cred_type, get_hash=True):
             logger.warning("Device might not support credential digests.")
             return True, None
 
-        return True, hash
+        return True, cred_hash
 
     def calculate_expected_hash(self, cred_text):
-        hash = hashlib.sha256(cred_text.encode('utf-8') + b'\x00')
-        return base64.b64encode(hash.digest()).decode()
+        cred_hash = hashlib.sha256(cred_text.encode('utf-8') + b'\x00')
+        return base64.b64encode(cred_hash.digest()).decode()
 
     def check_cred_command(self):
         logger.info("Checking for 'cred' command existence...")
         self.serial_write_line("cred")
-        result, output = self.serial_wait_for_response(timeout=5, store="cred")
-        logger.debug(f"Output: {output}")
-        logger.debug(f"Result: {result}")
-        # no prompt or promt timedout
+        result, output = self.serial_wait_for_response(
+            "TLS Credentials Commands", "command not found", store="cred"
+        )
+        logger.debug(f"Result: {result}, Output: {output}")
         if not result:
             logger.error("Device did not respond to 'cred' command.")
             return False
@@ -300,20 +319,25 @@ def main(in_args):
         logger.info(f'Deleting sectag {args.sectag}...')
         cred_if.delete_credential(args.sectag, args.cert_type)
 
-    cred_if.write_credential(args.sectag, args.cert_type, dev_bytes)
+    result = cred_if.write_credential(args.sectag, args.cert_type, dev_bytes)
+    if not result:
+        logger.error(f'Failed to write credential for sectag {args.sectag}, it may already exist')
+        sys.exit(5)
     logger.info(f'Writing sectag {args.sectag}...')
-    result, hash = cred_if.check_credential_exists(args.sectag, args.cert_type, args.check_hash)
+    result, cred_hash = cred_if.check_credential_exists(
+        args.sectag, args.cert_type, args.check_hash
+    )
     if args.check_hash:
         logger.debug(f'Checking hash for sectag {args.sectag}...')
     if not result:
         logger.error(f'Failed to check credential existence for sectag {args.sectag}')
         sys.exit(4)
-    if hash:
-        logger.debug(f'Credential hash: {hash}')
+    if cred_hash:
+        logger.debug(f'Credential hash: {cred_hash}')
         expected_hash = cred_if.calculate_expected_hash(dev_bytes)
-        if hash != expected_hash:
+        if cred_hash != expected_hash:
             logger.error(
-                f'Hash mismatch for sectag {args.sectag}. Expected: {expected_hash}, got: {hash}'
+                f'Hash mismatch for sectag {args.sectag}. Exp: {expected_hash}, got: {cred_hash}'
             )
             sys.exit(6)
     logger.info(f'Credential for sectag {args.sectag} written successfully')
diff --git a/scripts/west-commands.yml b/scripts/west-commands.yml
index 68a0951daf8..3096a43881d 100644
--- a/scripts/west-commands.yml
+++ b/scripts/west-commands.yml
@@ -94,3 +94,8 @@ west-commands:
       - name: patch
         class: Patch
         help: manage patches for Zephyr modules
+  - file: scripts/west_commands/gtags.py
+    commands:
+      - name: gtags
+        class: Gtags
+        help: create a GNU global tags file for the current workspace
diff --git a/scripts/west_commands/blobs.py b/scripts/west_commands/blobs.py
index fd124eccc78..618c2489c3b 100644
--- a/scripts/west_commands/blobs.py
+++ b/scripts/west_commands/blobs.py
@@ -120,7 +120,7 @@ def fetch_blob(self, url, path):
 
     # Compare the checksum of a file we've just downloaded
     # to the digest in blob metadata, warn user if they differ.
-    def verify_blob(self, blob):
+    def verify_blob(self, blob) -> bool:
         self.dbg('Verifying blob {module}: {abspath}'.format(**blob))
 
         status = zephyr_module.get_blob_status(blob['abspath'], blob['sha256'])
@@ -140,8 +140,11 @@ def verify_blob(self, blob):
                 Blob:   {blob['path']}
                 URL:    {blob['url']}
                 Info:   {blob['description']}'''))
+            return False
+        return True
 
     def fetch(self, args):
+        bad_checksum_count = 0
         blobs = self.get_blobs(args)
         for blob in blobs:
             if blob['status'] == zephyr_module.BLOB_PRESENT:
@@ -149,7 +152,12 @@ def fetch(self, args):
                 continue
             self.inf('Fetching blob {module}: {abspath}'.format(**blob))
             self.fetch_blob(blob['url'], blob['abspath'])
-            self.verify_blob(blob)
+            if not self.verify_blob(blob):
+                bad_checksum_count += 1
+
+        if bad_checksum_count:
+            self.err(f"{bad_checksum_count} blobs have bad checksums")
+            sys.exit(os.EX_DATAERR)
 
     def clean(self, args):
         blobs = self.get_blobs(args)
diff --git a/scripts/west_commands/boards.py b/scripts/west_commands/boards.py
index 201c3706954..18267999d3a 100644
--- a/scripts/west_commands/boards.py
+++ b/scripts/west_commands/boards.py
@@ -49,6 +49,8 @@ def do_add_parser(self, parser_adder):
 
             - name: board name
             - full_name: board full name (typically, its commercial name)
+            - revision_default: board default revision
+            - revisions: list of board revisions
             - qualifiers: board qualifiers (will be empty for legacy boards)
             - arch: board architecture (deprecated)
                     (arch is ambiguous for boards described in new hw model)
@@ -93,16 +95,32 @@ def do_run(self, args, _):
         for board in list_boards.find_boards(args):
             if name_re is not None and not name_re.search(board.name):
                 continue
+
+            if board.revisions:
+                revisions_list = ' '.join([rev.name for rev in board.revisions])
+            else:
+                revisions_list = 'None'
+
             self.inf(args.format.format(name=board.name, arch=board.arch,
+                                        revision_default=board.revision_default,
+                                        revisions=revisions_list,
                                         dir=board.dir, hwm=board.hwm, qualifiers=''))
 
         for board in list_boards.find_v2_boards(args).values():
             if name_re is not None and not name_re.search(board.name):
                 continue
+
+            if board.revisions:
+                revisions_list = ' '.join([rev.name for rev in board.revisions])
+            else:
+                revisions_list = 'None'
+
             self.inf(
                 args.format.format(
                     name=board.name,
                     full_name=board.full_name,
+                    revision_default=board.revision_default,
+                    revisions=revisions_list,
                     dir=board.dir,
                     hwm=board.hwm,
                     vendor=board.vendor,
diff --git a/scripts/west_commands/completion/west-completion.zsh b/scripts/west_commands/completion/west-completion.zsh
index 0ca7e82b5df..5fdbf23a050 100644
--- a/scripts/west_commands/completion/west-completion.zsh
+++ b/scripts/west_commands/completion/west-completion.zsh
@@ -25,6 +25,7 @@ _west_cmds() {
   local -a zephyr_ext_cmds=(
   'completion[display shell completion scripts]'
   'boards[display information about supported boards]'
+  'shields[display information about supported shields]'
   'build[compile a Zephyr application]'
   'sign[sign a Zephyr binary for bootloader chain-loading]'
   'flash[flash and run a binary on a board]'
@@ -114,6 +115,18 @@ _get_west_boards() {
   _describe 'boards' _west_boards
 }
 
+_get_west_shields() {
+  _west_shields=( $(__west_x shields --format='{name}') )
+  for i in {1..${#_west_shields[@]}}; do
+    local name="${_west_shields[$i]%%|*}"
+    local transformed_shield="${_west_shields[$i]//|//}"
+    _west_shields[$i]="${transformed_shield//,/ ${name}/}"
+  done
+  _west_shields=(${(@s/ /)_west_shields})
+
+  _describe 'shields' _west_shields
+}
+
 _west_init() {
   local -a opts=(
   '(-l --local)'{--mr,--manifest-rev}'[manifest revision]:manifest rev:'
@@ -228,6 +241,16 @@ _west_boards() {
   _arguments -S $opts
 }
 
+_west_shields() {
+  local -a opts=(
+  {-f,--format}'[format string]:format string:'
+  {-n,--name}'[name regex]:regex:'
+  '*--board-root[Add a board root]:board root:_directories'
+  )
+
+  _arguments -S $opts
+}
+
 _west_build() {
   local -a opts=(
   '(-b --board)'{-b,--board}'[board to build for]:board:_get_west_boards'
@@ -243,6 +266,7 @@ _west_build() {
   {-o,--build-opt}'[options to pass to build tool (make or ninja)]:tool opt:'
   '(-n --just-print --dry-run --recon)'{-n,--just-print,--dry-run,--recon}"[just print build commands, don't run them]"
   '(-p --pristine)'{-p,--pristine}'[pristine build setting]:pristine:(auto always never)'
+  '--shield[shield to build for]:shield:_get_west_shields'
   )
   _arguments -S $opts \
       "1:source_dir:_directories"
diff --git a/scripts/west_commands/gtags.py b/scripts/west_commands/gtags.py
new file mode 100644
index 00000000000..ae8ca2327c6
--- /dev/null
+++ b/scripts/west_commands/gtags.py
@@ -0,0 +1,98 @@
+# Copyright (c) 2025 Qualcomm Innovation Center, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+"""gtags.py
+
+A west extension for creating tags files (GTAGS) for GNU Global.
+For more information on Global, see: https://www.gnu.org/software/global
+"""
+
+import argparse
+import os.path
+import subprocess
+import tempfile
+
+from west.commands import WestCommand
+
+
+class Gtags(WestCommand):
+    def __init__(self):
+        super().__init__(
+            "gtags",
+            "create a GNU Global tags file for the current workspace",
+            """\
+Indexes source code files in the west workspace using GNU Global's
+"gtags" tool. For more information on Global and gtags, see:
+
+    https://www.gnu.org/software/global/
+
+The index can be useful to find definitions of functions, etc.,
+especially across repository boundaries. One example is
+finding the definition of a vendor HAL function that is
+provided by a Zephyr module for the HAL.
+
+By default, this west command only indexes files that are
+tracked by git projects defined in the west. Inactive west
+projects are ignored by default. For more information on
+projects etc., see the west documentation.""",
+        )
+
+    def do_add_parser(self, parser_adder):
+        parser = parser_adder.add_parser(
+            self.name,
+            help=self.help,
+            description=self.description,
+            formatter_class=argparse.RawDescriptionHelpFormatter,
+        )
+
+        parser.add_argument(
+            "projects",
+            nargs="*",
+            metavar="PROJECT",
+            help="""Name of west project to index, or
+            its path. May be given more than once. Use
+            "manifest" to refer to the manifest
+            repository""",
+        )
+
+        return parser
+
+    def do_run(self, args, unknown_args):
+        all_files = []
+        for project in self.manifest.get_projects(args.projects):
+            all_files.extend(self.files_in_project(project))
+
+        with tempfile.TemporaryDirectory(suffix="gtags") as d:
+            gtags_files = os.path.join(d, "gtags.files")
+            with open(gtags_files, "w") as f:
+                # Due to what looks like a limitation in GNU Global,
+                # this won't work if there are newlines in file names.
+                # Unlike xargs and other commands, though, gtags
+                # doesn't seem to have a way to accept a NUL-delimited
+                # list of input file; its manpage says file names must
+                # be delimited by newlines.
+                f.write("\n".join(all_files))
+            subprocess.run(
+                # Note that "gtags -f -" and passing files via stdin
+                # could run into issues on windows, and there seem to
+                # be win32 builds of global out there
+                ["gtags", "-f", gtags_files],
+                cwd=self.manifest.topdir,
+                check=True,
+            )
+
+    def files_in_project(self, project):
+        if not project.is_cloned() or not self.manifest.is_active(project):
+            return []
+        ls_files = (
+            project.git(["ls-files", "**"], capture_stdout=True).stdout.decode("utf-8").splitlines()
+        )
+        ret = []
+        for filename in ls_files:
+            absolute = os.path.join(project.abspath, filename)
+            # Filter out directories from the git ls-files output.
+            # There didn't seem to be a way to tell it to do that by
+            # itself.
+            if os.path.isfile(absolute):
+                ret.append(absolute)
+        return ret
diff --git a/scripts/west_commands/patch.py b/scripts/west_commands/patch.py
index 8592d06dbab..618a45bc66a 100644
--- a/scripts/west_commands/patch.py
+++ b/scripts/west_commands/patch.py
@@ -5,19 +5,27 @@
 import argparse
 import hashlib
 import os
+import re
 import shlex
 import subprocess
+import sys
 import textwrap
+import urllib.request
 from pathlib import Path
 
 import pykwalify.core
 import yaml
 from west.commands import WestCommand
 
+sys.path.append(os.fspath(Path(__file__).parent.parent))
+import zephyr_module
+from zephyr_ext_common import ZEPHYR_BASE
+
 try:
+    from yaml import CSafeDumper as SafeDumper
     from yaml import CSafeLoader as SafeLoader
 except ImportError:
-    from yaml import SafeLoader
+    from yaml import SafeDumper, SafeLoader
 
 WEST_PATCH_SCHEMA_PATH = Path(__file__).parents[1] / "schemas" / "patch-schema.yml"
 with open(WEST_PATCH_SCHEMA_PATH) as f:
@@ -26,9 +34,6 @@
 WEST_PATCH_BASE = Path("zephyr") / "patches"
 WEST_PATCH_YAML = Path("zephyr") / "patches.yml"
 
-_WEST_MANIFEST_DIR = Path("WEST_MANIFEST_DIR")
-_WEST_TOPDIR = Path("WEST_TOPDIR")
-
 
 class Patch(WestCommand):
     def __init__(self):
@@ -61,6 +66,11 @@ def do_add_parser(self, parser_adder):
                 Run "west patch list" to list patches.
                 See "west patch list --help" for details.
 
+            Fetching Patches:
+
+                Run "west patch gh-fetch" to fetch patches from Github.
+                See "west patch gh-fetch --help" for details.
+
             YAML File Format:
 
             The patches.yml syntax is described in "scripts/schemas/patch-schema.yml".
@@ -93,17 +103,19 @@ def do_add_parser(self, parser_adder):
         parser.add_argument(
             "-b",
             "--patch-base",
-            help="Directory containing patch files",
+            help=f"""
+                Directory containing patch files (absolute or relative to module dir,
+                default: {WEST_PATCH_BASE})""",
             metavar="DIR",
-            default=_WEST_MANIFEST_DIR / WEST_PATCH_BASE,
             type=Path,
         )
         parser.add_argument(
             "-l",
             "--patch-yml",
-            help="Path to patches.yml file",
+            help=f"""
+                Path to patches.yml file (absolute or relative to module dir,
+                default: {WEST_PATCH_YAML})""",
             metavar="FILE",
-            default=_WEST_MANIFEST_DIR / WEST_PATCH_YAML,
             type=Path,
         )
         parser.add_argument(
@@ -111,20 +123,30 @@ def do_add_parser(self, parser_adder):
             "--west-workspace",
             help="West workspace",
             metavar="DIR",
-            default=_WEST_TOPDIR,
             type=Path,
         )
         parser.add_argument(
-            "-m",
-            "--module",
+            "-sm",
+            "--src-module",
+            dest="src_module",
+            metavar="MODULE",
+            type=str,
+            help="""
+                Zephyr module containing the patch definition (name, absolute path or
+                path relative to west-workspace)""",
+        )
+        parser.add_argument(
+            "-dm",
+            "--dst-module",
             action="append",
-            dest="modules",
-            metavar="DIR",
-            type=Path,
-            help="Zephyr module directory to run the 'patch' command for. "
-            "Option can be passed multiple times. "
-            "If this option is not given, the 'patch' command will run for Zephyr "
-            "and all modules.",
+            dest="dst_modules",
+            metavar="MODULE",
+            type=str,
+            help="""
+                Zephyr module to run the 'patch' command for.
+                Option can be passed multiple times.
+                If this option is not given, the 'patch' command will run for Zephyr
+                and all modules.""",
         )
 
         subparsers = parser.add_subparsers(
@@ -166,6 +188,67 @@ def do_add_parser(self, parser_adder):
             ),
         )
 
+        gh_fetch_arg_parser = subparsers.add_parser(
+            "gh-fetch",
+            help="Fetch patch from Github",
+            formatter_class=argparse.RawDescriptionHelpFormatter,
+            epilog=textwrap.dedent(
+                """
+            Fetching Patches from Github:
+
+                Run "west patch gh-fetch" to fetch a PR from Github and store it as a patch.
+                The meta data is generated and appended to the provided patches.yml file.
+
+                If no patches.yml file exists, it will be created.
+            """
+            ),
+        )
+        gh_fetch_arg_parser.add_argument(
+            "-o",
+            "--owner",
+            action="store",
+            default="zephyrproject-rtos",
+            help="Github repository owner",
+        )
+        gh_fetch_arg_parser.add_argument(
+            "-r",
+            "--repo",
+            action="store",
+            default="zephyr",
+            help="Github repository",
+        )
+        gh_fetch_arg_parser.add_argument(
+            "-pr",
+            "--pull-request",
+            metavar="ID",
+            action="store",
+            required=True,
+            type=int,
+            help="Github Pull Request ID",
+        )
+        gh_fetch_arg_parser.add_argument(
+            "-m",
+            "--module",
+            metavar="DIR",
+            action="store",
+            required=True,
+            type=Path,
+            help="Module path",
+        )
+        gh_fetch_arg_parser.add_argument(
+            "-s",
+            "--split-commits",
+            action="store_true",
+            help="Create patch files for each commit instead of a single patch for the entire PR",
+        )
+        gh_fetch_arg_parser.add_argument(
+            '-t',
+            '--token',
+            metavar='FILE',
+            dest='tokenfile',
+            help='File containing GitHub token (alternatively, use GITHUB_TOKEN env variable)',
+        )
+
         subparsers.add_parser(
             "list",
             help="List patches",
@@ -188,36 +271,64 @@ def filter_args(self, args):
             self.die("could not retrieve manifest path from west configuration")
 
         topdir = Path(self.topdir)
-        manifest_dir = topdir / manifest_path
-
-        if args.patch_base.is_relative_to(_WEST_MANIFEST_DIR):
-            args.patch_base = manifest_dir / args.patch_base.relative_to(_WEST_MANIFEST_DIR)
-        if args.patch_yml.is_relative_to(_WEST_MANIFEST_DIR):
-            args.patch_yml = manifest_dir / args.patch_yml.relative_to(_WEST_MANIFEST_DIR)
-        if args.west_workspace.is_relative_to(_WEST_TOPDIR):
-            args.west_workspace = topdir / args.west_workspace.relative_to(_WEST_TOPDIR)
-
-    def do_run(self, args, _):
-        self.filter_args(args)
 
+        if args.src_module is not None:
+            mod_path = self.get_module_path(args.src_module)
+            if mod_path is None:
+                self.die(f'Source module "{args.src_module}" not found')
+            if args.patch_base is not None and args.patch_base.is_absolute():
+                self.die("patch-base must not be an absolute path in combination with src-module")
+            if args.patch_yml is not None and args.patch_yml.is_absolute():
+                self.die("patch-yml must not be an absolute path in combination with src-module")
+            manifest_dir = topdir / mod_path
+        else:
+            manifest_dir = topdir / manifest_path
+
+        if args.patch_base is None:
+            args.patch_base = manifest_dir / WEST_PATCH_BASE
+        if not args.patch_base.is_absolute():
+            args.patch_base = manifest_dir / args.patch_base
+
+        if args.patch_yml is None:
+            args.patch_yml = manifest_dir / WEST_PATCH_YAML
+        elif not args.patch_yml.is_absolute():
+            args.patch_yml = manifest_dir / args.patch_yml
+
+        if args.west_workspace is None:
+            args.west_workspace = topdir
+        elif not args.west_workspace.is_absolute():
+            args.west_workspace = topdir / args.west_workspace
+
+        if args.dst_modules is not None:
+            args.dst_modules = [self.get_module_path(m) for m in args.dst_modules]
+
+    def load_yml(self, args, allow_missing):
         if not os.path.isfile(args.patch_yml):
-            self.inf(f"no patches to apply: {args.patch_yml} not found")
-            return
+            if not allow_missing:
+                self.inf(f"no patches to apply: {args.patch_yml} not found")
+                return None
 
-        west_config = Path(args.west_workspace) / ".west" / "config"
-        if not os.path.isfile(west_config):
-            self.die(f"{args.west_workspace} is not a valid west workspace")
+            # Return the schema defaults
+            return pykwalify.core.Core(source_data={}, schema_data=patches_schema).validate()
 
         try:
             with open(args.patch_yml) as f:
                 yml = yaml.load(f, Loader=SafeLoader)
-            if not yml:
-                self.inf(f"{args.patch_yml} is empty")
-                return
-            pykwalify.core.Core(source_data=yml, schema_data=patches_schema).validate()
+            return pykwalify.core.Core(source_data=yml, schema_data=patches_schema).validate()
         except (yaml.YAMLError, pykwalify.errors.SchemaError) as e:
             self.die(f"ERROR: Malformed yaml {args.patch_yml}: {e}")
 
+    def do_run(self, args, _):
+        self.filter_args(args)
+
+        west_config = Path(args.west_workspace) / ".west" / "config"
+        if not os.path.isfile(west_config):
+            self.die(f"{args.west_workspace} is not a valid west workspace")
+
+        yml = self.load_yml(args, args.subcommand in ["gh-fetch"])
+        if yml is None:
+            return
+
         if not args.subcommand:
             args.subcommand = "list"
 
@@ -225,11 +336,12 @@ def do_run(self, args, _):
             "apply": self.apply,
             "clean": self.clean,
             "list": self.list,
+            "gh-fetch": self.gh_fetch,
         }
 
-        method[args.subcommand](args, yml, args.modules)
+        method[args.subcommand](args, yml, args.dst_modules)
 
-    def apply(self, args, yml, mods=None):
+    def apply(self, args, yml, dst_mods=None):
         patches = yml.get("patches", [])
         if not patches:
             return
@@ -239,8 +351,11 @@ def apply(self, args, yml, mods=None):
         patched_mods = set()
 
         for patch_info in patches:
-            mod = Path(patch_info["module"])
-            if mods and mod not in mods:
+            mod = self.get_module_path(patch_info["module"])
+            if mod is None:
+                continue
+
+            if dst_mods and mod not in dst_mods:
                 continue
 
             pth = patch_info["path"]
@@ -301,7 +416,7 @@ def apply(self, args, yml, mods=None):
 
         self.die(f"failed to apply patch {failed_patch}")
 
-    def clean(self, args, yml, mods=None):
+    def clean(self, args, yml, dst_mods=None):
         clean_cmd = yml["clean-command"]
         checkout_cmd = yml["checkout-command"]
 
@@ -312,9 +427,14 @@ def clean(self, args, yml, mods=None):
         clean_cmd_list = shlex.split(clean_cmd)
         checkout_cmd_list = shlex.split(checkout_cmd)
 
-        for mod, mod_path in Patch.get_mod_paths(args, yml).items():
-            if mods and mod not in mods:
+        for mod in yml.get("patches", []):
+            m = self.get_module_path(mod.get("module"))
+            if m is None:
                 continue
+            if dst_mods and m not in dst_mods:
+                continue
+            mod_path = Path(args.west_workspace) / m
+
             try:
                 if checkout_cmd:
                     self.dbg(f"Running '{checkout_cmd}' in {mod}.. ", end="")
@@ -338,26 +458,99 @@ def clean(self, args, yml, mods=None):
                 # If this fails for some reason, just log it and continue
                 self.err(f"failed to clean up {mod}: {e}")
 
-    def list(self, args, yml, mods=None):
+    def list(self, args, yml, dst_mods=None):
         patches = yml.get("patches", [])
         if not patches:
             return
 
         for patch_info in patches:
-            if mods and Path(patch_info["module"]) not in mods:
+            if dst_mods and self.get_module_path(patch_info["module"]) not in dst_mods:
                 continue
             self.inf(patch_info)
 
+    def gh_fetch(self, args, yml, mods=None):
+        if mods:
+            self.die(
+                "Module filters are not available for the gh-fetch subcommand, "
+                "pass a single -m/--module argument after the subcommand."
+            )
+
+        try:
+            from github import Auth, Github
+        except ImportError:
+            self.die("PyGithub not found; can be installed with 'pip install PyGithub'")
+
+        gh = Github(auth=Auth.Token(args.tokenfile) if args.tokenfile else None)
+        pr = gh.get_repo(f"{args.owner}/{args.repo}").get_pull(args.pull_request)
+        args.patch_base.mkdir(parents=True, exist_ok=True)
+
+        if args.split_commits:
+            for cm in pr.get_commits():
+                subject = cm.commit.message.splitlines()[0]
+                filename = "-".join(filter(None, re.split("[^a-zA-Z0-9]+", subject))) + ".patch"
+
+                # No patch URL is provided by the API, but appending .patch to the HTML works too
+                urllib.request.urlretrieve(f"{cm.html_url}.patch", args.patch_base / filename)
+
+                patch_info = {
+                    "path": filename,
+                    "sha256sum": self.get_file_sha256sum(args.patch_base / filename),
+                    "module": str(args.module),
+                    "author": cm.commit.author.name or "Hidden",
+                    "email": cm.commit.author.email or "hidden@github.com",
+                    "date": cm.commit.author.date.strftime("%Y-%m-%d"),
+                    "upstreamable": True,
+                    "merge-pr": pr.html_url,
+                    "merge-status": pr.merged,
+                }
+
+                yml.setdefault("patches", []).append(patch_info)
+        else:
+            filename = "-".join(filter(None, re.split("[^a-zA-Z0-9]+", pr.title))) + ".patch"
+            urllib.request.urlretrieve(pr.patch_url, args.patch_base / filename)
+
+            patch_info = {
+                "path": filename,
+                "sha256sum": self.get_file_sha256sum(args.patch_base / filename),
+                "module": str(args.module),
+                "author": pr.user.name or "Hidden",
+                "email": pr.user.email or "hidden@github.com",
+                "date": pr.created_at.strftime("%Y-%m-%d"),
+                "upstreamable": True,
+                "merge-pr": pr.html_url,
+                "merge-status": pr.merged,
+            }
+
+            yml.setdefault("patches", []).append(patch_info)
+
+        args.patch_yml.parent.mkdir(parents=True, exist_ok=True)
+        with open(args.patch_yml, "w") as f:
+            yaml.dump(yml, f, Dumper=SafeDumper)
+
     @staticmethod
-    def get_mod_paths(args, yml):
-        patches = yml.get("patches", [])
-        if not patches:
-            return {}
+    def get_file_sha256sum(filename: Path) -> str:
+        with open(filename, "rb") as fp:
+            digest = hashlib.file_digest(fp, "sha256")
 
-        mod_paths = {}
-        for patch_info in patches:
-            mod = Path(patch_info["module"])
-            mod_path = os.path.realpath(Path(args.west_workspace) / mod)
-            mod_paths[mod] = mod_path
+        return digest.hexdigest()
+
+    def get_module_path(self, module_name_or_path):
+        if module_name_or_path is None:
+            return None
+
+        topdir = Path(self.topdir)
+
+        if Path(module_name_or_path).is_absolute():
+            if Path(module_name_or_path).is_dir():
+                return Path(module_name_or_path).resolve().relative_to(topdir)
+            return None
+
+        if (topdir / module_name_or_path).is_dir():
+            return Path(module_name_or_path)
+
+        all_modules = zephyr_module.parse_modules(ZEPHYR_BASE, self.manifest)
+        for m in all_modules:
+            if m.meta['name'] == module_name_or_path:
+                return Path(m.project).relative_to(topdir)
 
-        return mod_paths
+        return None
diff --git a/scripts/west_commands/run_common.py b/scripts/west_commands/run_common.py
index e5492ad2f7b..b13ca502eb6 100644
--- a/scripts/west_commands/run_common.py
+++ b/scripts/west_commands/run_common.py
@@ -411,11 +411,17 @@ def do_run_common_image(command, user_args, user_runner_args, used_cmds,
 
             i = i - 1
 
+    # Arguments in this order to allow specific to override general:
+    #
+    # - runner-specific runners.yaml arguments
+    # - user-provided command line arguments
+    final_argv = runners_yaml['args'][runner_name] + runner_args
+
     # If flashing multiple images, the runner supports reset after flashing and
     # the board has enabled this functionality, check if the board should be
     # reset or not. If this is not specified in the board/soc file, leave it up to
     # the runner's default configuration to decide if a reset should occur.
-    if runner_cls.capabilities().reset:
+    if runner_cls.capabilities().reset and '--no-reset' not in final_argv:
         if board_image_count is not None:
             reset = True
 
@@ -449,15 +455,9 @@ def do_run_common_image(command, user_args, user_runner_args, used_cmds,
                                         break
 
             if reset:
-                runner_args.append('--reset')
+                final_argv.append('--reset')
             else:
-                runner_args.append('--no-reset')
-
-    # Arguments in this order to allow specific to override general:
-    #
-    # - runner-specific runners.yaml arguments
-    # - user-provided command line arguments
-    final_argv = runners_yaml['args'][runner_name] + runner_args
+                final_argv.append('--no-reset')
 
     # 'user_args' contains parsed arguments which are:
     #
diff --git a/scripts/west_commands/runners/__init__.py b/scripts/west_commands/runners/__init__.py
index 3ed333c24c2..659677ec035 100644
--- a/scripts/west_commands/runners/__init__.py
+++ b/scripts/west_commands/runners/__init__.py
@@ -55,10 +55,12 @@ def _import_runner_module(runner_name):
     'qemu',
     'renode',
     'renode-robot',
+    'rfp',
     'silabs_commander',
     'spi_burn',
     'stm32cubeprogrammer',
     'stm32flash',
+    'sy1xx',
     'teensy',
     'trace32',
     'uf2',
diff --git a/scripts/west_commands/runners/core.py b/scripts/west_commands/runners/core.py
index cf01d2abf45..fb160155a49 100644
--- a/scripts/west_commands/runners/core.py
+++ b/scripts/west_commands/runners/core.py
@@ -268,6 +268,9 @@ class RunnerCaps:
       connected to a single computer, in order to select which one will be used
       with the command provided.
 
+    - mult_dev_ids: whether the runner supports multiple device identifiers
+      for a single operation, allowing for bulk flashing of devices.
+
     - flash_addr: whether the runner supports flashing to an
       arbitrary address. Default is False. If true, the runner
       must honor the --dt-flash option.
@@ -305,6 +308,7 @@ class RunnerCaps:
 
     commands: set[str] = field(default_factory=lambda: set(_RUNNERCAPS_COMMANDS))
     dev_id: bool = False
+    mult_dev_ids: bool = False
     flash_addr: bool = False
     erase: bool = False
     reset: bool = False
@@ -316,6 +320,8 @@ class RunnerCaps:
                        # to allow other commands to use the rtt address
 
     def __post_init__(self):
+        if self.mult_dev_ids and not self.dev_id:
+            raise RuntimeError('dev_id must be set along mult_dev_ids')
         if not self.commands.issubset(_RUNNERCAPS_COMMANDS):
             raise ValueError(f'{self.commands=} contains invalid command')
 
@@ -543,7 +549,9 @@ def add_parser(cls, parser):
         caps = cls.capabilities()
 
         if caps.dev_id:
+            action = 'append' if caps.mult_dev_ids else 'store'
             parser.add_argument('-i', '--dev-id',
+                                action=action,
                                 dest='dev_id',
                                 help=cls.dev_id_help())
         else:
@@ -749,10 +757,13 @@ def thread_info_enabled(self) -> bool:
     @classmethod
     def dev_id_help(cls) -> str:
         ''' Get the ArgParse help text for the --dev-id option.'''
-        return '''Device identifier. Use it to select
+        help = '''Device identifier. Use it to select
                   which debugger, device, node or instance to
                   target when multiple ones are available or
                   connected.'''
+        addendum = '''\nThis option can be present multiple times.''' if \
+                   cls.capabilities().mult_dev_ids else ''
+        return help + addendum
 
     @classmethod
     def extload_help(cls) -> str:
@@ -920,22 +931,27 @@ def ensure_output(self, output_type: str) -> None:
         # RuntimeError avoids a stack trace saved in run_common.
         raise RuntimeError(err)
 
-    def run_telnet_client(self, host: str, port: int) -> None:
+    def run_telnet_client(self, host: str, port: int, active_sock=None) -> None:
         '''
         Run a telnet client for user interaction.
         '''
-        # If a `nc` command is available, run it, as it will provide the best support for
-        # CONFIG_SHELL_VT100_COMMANDS etc.
-        if shutil.which('nc') is not None:
+        # If the caller passed in an active socket, use that
+        if active_sock is not None:
+            sock = active_sock
+        elif shutil.which('nc') is not None:
+            # If a `nc` command is available, run it, as it will provide the
+            # best support for CONFIG_SHELL_VT100_COMMANDS etc.
             client_cmd = ['nc', host, str(port)]
             # Note: netcat (nc) does not handle sigint, so cannot use run_client()
             self.check_call(client_cmd)
             return
+        else:
+            # Start a new socket connection
+            sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
+            sock.connect((host, port))
 
         # Otherwise, use a pure python implementation. This will work well for logging,
         # but input is line based only.
-        sock = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
-        sock.connect((host, port))
         sel = selectors.DefaultSelector()
         sel.register(sys.stdin, selectors.EVENT_READ)
         sel.register(sock, selectors.EVENT_READ)
diff --git a/scripts/west_commands/runners/esp32.py b/scripts/west_commands/runners/esp32.py
index faaa2b047eb..619c16460e8 100644
--- a/scripts/west_commands/runners/esp32.py
+++ b/scripts/west_commands/runners/esp32.py
@@ -19,7 +19,7 @@ def __init__(self, cfg, device, boot_address, part_table_address,
                  app_address, erase=False, reset=False, baud=921600,
                  flash_size='detect', flash_freq='40m', flash_mode='dio',
                  espidf='espidf', bootloader_bin=None, partition_table_bin=None,
-                 no_stub=False):
+                 encrypt=False, no_stub=False):
         super().__init__(cfg)
         self.elf = cfg.elf_file
         self.app_bin = cfg.bin_file
@@ -36,6 +36,7 @@ def __init__(self, cfg, device, boot_address, part_table_address,
         self.espidf = espidf
         self.bootloader_bin = bootloader_bin
         self.partition_table_bin = partition_table_bin
+        self.encrypt = encrypt
         self.no_stub = no_stub
 
     @classmethod
@@ -78,6 +79,8 @@ def do_add_parser(cls, parser):
                             help='Bootloader image to flash')
         parser.add_argument('--esp-flash-partition_table',
                             help='Partition table to flash')
+        parser.add_argument('--esp-encrypt', default=False, action='store_true',
+                            help='Encrypt firmware while flashing (correct efuses required)')
         parser.add_argument('--esp-no-stub', default=False, action='store_true',
                             help='Disable launching the flasher stub, only talk to ROM bootloader')
 
@@ -99,7 +102,7 @@ def do_create(cls, cfg, args):
             flash_freq=args.esp_flash_freq, flash_mode=args.esp_flash_mode,
             espidf=espidf, bootloader_bin=args.esp_flash_bootloader,
             partition_table_bin=args.esp_flash_partition_table,
-            no_stub=args.esp_no_stub)
+            encrypt=args.esp_encrypt, no_stub=args.esp_no_stub)
 
     def do_run(self, command, **kwargs):
         self.require(self.espidf)
@@ -124,6 +127,9 @@ def do_run(self, command, **kwargs):
         cmd_flash.extend(['--flash_freq', self.flash_freq])
         cmd_flash.extend(['--flash_size', self.flash_size])
 
+        if self.encrypt:
+            cmd_flash.extend(['--encrypt'])
+
         if self.bootloader_bin:
             cmd_flash.extend([self.boot_address, self.bootloader_bin])
             if self.partition_table_bin:
diff --git a/scripts/west_commands/runners/intel_adsp.py b/scripts/west_commands/runners/intel_adsp.py
index 3e74746cc2c..02b13fe6491 100644
--- a/scripts/west_commands/runners/intel_adsp.py
+++ b/scripts/west_commands/runners/intel_adsp.py
@@ -90,7 +90,7 @@ def do_run(self, command, **kwargs):
 
     def flash(self, **kwargs):
         'Generate a hash string for appending to the sending ri file'
-        hash_object = hashlib.md5(self.bin_fw.encode())
+        hash_object = hashlib.md5(self.bin_fw.encode(), usedforsecurity=False)
         random_str = f"{random.getrandbits(64)}".encode()
         hash_object.update(random_str)
         send_bin_fw = str(self.bin_fw + "." + hash_object.hexdigest())
diff --git a/scripts/west_commands/runners/jlink.py b/scripts/west_commands/runners/jlink.py
index ed1b942e9b9..5dc4f626ba3 100644
--- a/scripts/west_commands/runners/jlink.py
+++ b/scripts/west_commands/runners/jlink.py
@@ -329,9 +329,7 @@ def do_run(self, command, **kwargs):
                         break
                     except ConnectionRefusedError:
                         time.sleep(0.1)
-                sock.shutdown(socket.SHUT_RDWR)
-                time.sleep(0.1)
-                self.run_telnet_client('localhost', self.rtt_port)
+                self.run_telnet_client('localhost', self.rtt_port, sock)
             except Exception as e:
                 self.logger.error(e)
             finally:
diff --git a/scripts/west_commands/runners/nrf_common.py b/scripts/west_commands/runners/nrf_common.py
index 3ed8fb65a06..af4f8286722 100644
--- a/scripts/west_commands/runners/nrf_common.py
+++ b/scripts/west_commands/runners/nrf_common.py
@@ -79,7 +79,8 @@ class NrfBinaryRunner(ZephyrBinaryRunner):
     '''Runner front-end base class for nrf tools.'''
 
     def __init__(self, cfg, family, softreset, pinreset, dev_id, erase=False,
-                 reset=True, tool_opt=None, force=False, recover=False):
+                 erase_mode=None, ext_erase_mode=None, reset=True,
+                 tool_opt=None, force=False, recover=False):
         super().__init__(cfg)
         self.hex_ = cfg.hex_file
         # The old --nrf-family options takes upper-case family names
@@ -88,6 +89,8 @@ def __init__(self, cfg, family, softreset, pinreset, dev_id, erase=False,
         self.pinreset = pinreset
         self.dev_id = dev_id
         self.erase = bool(erase)
+        self.erase_mode = erase_mode
+        self.ext_erase_mode = ext_erase_mode
         self.reset = bool(reset)
         self.force = force
         self.recover = bool(recover)
@@ -101,12 +104,13 @@ def __init__(self, cfg, family, softreset, pinreset, dev_id, erase=False,
                 self.tool_opt += opts
 
     @classmethod
-    def capabilities(cls):
-        return RunnerCaps(commands={'flash'}, dev_id=True, erase=True,
-                          reset=True, tool_opt=True)
+    def _capabilities(cls, mult_dev_ids=False):
+        return RunnerCaps(commands={'flash'}, dev_id=True,
+                          mult_dev_ids=mult_dev_ids, erase=True, reset=True,
+                          tool_opt=True)
 
     @classmethod
-    def dev_id_help(cls) -> str:
+    def _dev_id_help(cls) -> str:
         return '''Device identifier. Use it to select the J-Link Serial Number
                   of the device connected over USB. '*' matches one or more
                   characters/digits'''
@@ -136,6 +140,14 @@ def do_add_parser(cls, parser):
                             help='''erase all user available non-volatile
                             memory and disable read back protection before
                             flashing (erases flash for both cores on nRF53)''')
+        parser.add_argument('--erase-mode', required=False,
+                            choices=['none', 'ranges', 'all'],
+                            help='Select the type of erase operation for the '
+                                 'internal non-volatile memory')
+        parser.add_argument('--ext-erase-mode', required=False,
+                            choices=['none', 'ranges', 'all'],
+                            help='Select the type of erase operation for the '
+                                 'external non-volatile memory')
 
         parser.set_defaults(reset=True)
 
@@ -146,9 +158,19 @@ def args_from_previous_runner(cls, previous_runner, args):
             args.dev_id = previous_runner.dev_id
 
     def ensure_snr(self):
-        if not self.dev_id or "*" in self.dev_id:
-            self.dev_id = self.get_board_snr(self.dev_id or "*")
-        self.dev_id = self.dev_id.lstrip("0")
+        # dev_id can be None, str or list of str
+        dev_id = self.dev_id
+        if isinstance(dev_id, list):
+            if len(dev_id) == 0:
+                dev_id = None
+            elif len(dev_id) == 1:
+                dev_id = dev_id[0]
+            else:
+                self.dev_id = [d.lstrip("0") for d in dev_id]
+                return
+        if not dev_id or "*" in dev_id:
+            dev_id = self.get_board_snr(dev_id or "*")
+        self.dev_id = dev_id.lstrip("0")
 
     @abc.abstractmethod
     def do_get_boards(self):
@@ -325,6 +347,18 @@ def _get_core(self):
 
         return None
 
+    def _get_erase_mode(self, mode):
+        if not mode:
+            return None
+        elif mode == "none":
+            return "ERASE_NONE"
+        elif mode == "ranges":
+            return "ERASE_RANGES_TOUCHED_BY_FIRMWARE"
+        elif mode == "all":
+            return "ERASE_ALL"
+        else:
+            raise RuntimeError(f"Invalid erase mode: {mode}")
+
     def program_hex(self):
         # Get the command use to actually program self.hex_.
         self.logger.info(f'Flashing file: {self.hex_}')
@@ -405,6 +439,8 @@ def program_hex(self):
         else:
             if self.erase:
                 erase_arg = 'ERASE_ALL'
+            elif self.family == 'nrf54l':
+                erase_arg = self._get_erase_mode(self.erase_mode) or 'ERASE_NONE'
             else:
                 erase_arg = 'ERASE_RANGES_TOUCHED_BY_FIRMWARE'
 
@@ -416,7 +452,17 @@ def program_hex(self):
         if self.family in xip_ranges:
             xip_start, xip_end = xip_ranges[self.family]
             if self.hex_refers_region(xip_start, xip_end):
-                ext_mem_erase_opt = erase_arg
+                # Default to pages for the external memory
+                ext_mem_erase_opt = self._get_erase_mode(self.ext_erase_mode) or \
+                        (erase_arg if erase_arg == 'ERASE_ALL' else \
+                                    'ERASE_RANGES_TOUCHED_BY_FIRMWARE')
+
+        if not ext_mem_erase_opt and self.ext_erase_mode:
+            self.logger.warning('Option --ext-erase-mode ignored, no parts of the '
+                                'image refer to external memory')
+
+        self.logger.debug(f'Erase modes: chip:{erase_arg} ext_mem:'
+                          f'{ext_mem_erase_opt}')
 
         # Temp hack while waiting for NRF54H20_IRON support for Network in nrfutil
         if self.build_conf.get('CONFIG_SOC_NRF54H20_IRON') and core == "Network":
@@ -427,11 +473,12 @@ def program_hex(self):
 
 
     def reset_target(self):
+        sw_reset = "RESET_HARD" if self.family in ('nrf54h', 'nrf92') else "RESET_SYSTEM"
         # Default to soft reset on nRF52 only, because ICs in these series can
         # reconfigure the reset pin as a regular GPIO
-        default = "RESET_SYSTEM" if self.family == 'nrf52' else "RESET_PIN"
-        kind = ("RESET_SYSTEM" if self.softreset else "RESET_PIN" if
-               self.pinreset else default)
+        default = sw_reset if self.family == 'nrf52' else "RESET_PIN"
+        kind = (sw_reset if self.softreset else "RESET_PIN" if
+                self.pinreset else default)
 
         if self.family == 'nrf52' and kind == "RESET_PIN":
             # Write to the UICR enabling nRESET in the corresponding pin
@@ -512,6 +559,20 @@ def do_run(self, command, **kwargs):
             raise RuntimeError('Options --softreset and --pinreset are mutually '
                                'exclusive.')
 
+        if self.erase and self.erase_mode:
+            raise RuntimeError('Options --erase and --erase-mode are mutually '
+                               'exclusive.')
+
+        if self.erase and self.ext_erase_mode:
+            raise RuntimeError('Options --erase and --ext-erase-mode are mutually '
+                               'exclusive.')
+
+        self.ensure_family()
+
+        if self.family != 'nrf54l' and self.erase_mode:
+            raise RuntimeError('Option --erase-mode can only be used with the '
+                               'nRF54L family.')
+
         self.ensure_output('hex')
         if IntelHex is None:
             raise RuntimeError('Python dependency intelhex was missing; '
@@ -522,7 +583,6 @@ def do_run(self, command, **kwargs):
             self.hex_contents.loadfile(self.hex_, format='hex')
 
         self.ensure_snr()
-        self.ensure_family()
 
         self.ops = deque()
 
@@ -534,5 +594,5 @@ def do_run(self, command, **kwargs):
         # All done, now flush any outstanding ops
         self.flush(force=True)
 
-        self.logger.info(f'Board with serial number {self.dev_id} '
-                         'flashed successfully.')
+        self.logger.info(f'Board(s) with serial number(s) {self.dev_id} '
+                          'flashed successfully.')
diff --git a/scripts/west_commands/runners/nrfjprog.py b/scripts/west_commands/runners/nrfjprog.py
index 36461b7236d..fd0a47e5dc4 100644
--- a/scripts/west_commands/runners/nrfjprog.py
+++ b/scripts/west_commands/runners/nrfjprog.py
@@ -18,11 +18,12 @@ class NrfJprogBinaryRunner(NrfBinaryRunner):
     '''Runner front-end for nrfjprog.'''
 
     def __init__(self, cfg, family, softreset, pinreset, dev_id, erase=False,
-                 reset=True, tool_opt=None, force=False, recover=False,
-                 qspi_ini=None):
+                 erase_mode=None, ext_erase_mode=None, reset=True, tool_opt=None,
+                 force=False, recover=False, qspi_ini=None):
 
-        super().__init__(cfg, family, softreset, pinreset, dev_id, erase, reset,
-                         tool_opt, force, recover)
+        super().__init__(cfg, family, softreset, pinreset, dev_id, erase,
+                         erase_mode, ext_erase_mode, reset, tool_opt, force,
+                         recover)
 
         self.qspi_ini = qspi_ini
 
@@ -30,6 +31,14 @@ def __init__(self, cfg, family, softreset, pinreset, dev_id, erase=False,
     def name(cls):
         return 'nrfjprog'
 
+    @classmethod
+    def capabilities(cls):
+        return NrfBinaryRunner._capabilities()
+
+    @classmethod
+    def dev_id_help(cls) -> str:
+        return NrfBinaryRunner._dev_id_help()
+
     @classmethod
     def tool_opt_help(cls) -> str:
         return 'Additional options for nrfjprog, e.g. "--clockspeed"'
@@ -38,9 +47,11 @@ def tool_opt_help(cls) -> str:
     def do_create(cls, cfg, args):
         return NrfJprogBinaryRunner(cfg, args.nrf_family, args.softreset,
                                     args.pinreset, args.dev_id, erase=args.erase,
-                                    reset=args.reset,
-                                    tool_opt=args.tool_opt, force=args.force,
-                                    recover=args.recover, qspi_ini=args.qspi_ini)
+                                    erase_mode=args.erase_mode,
+                                    ext_erase_mode=args.ext_erase_mode,
+                                    reset=args.reset, tool_opt=args.tool_opt,
+                                    force=args.force, recover=args.recover,
+                                    qspi_ini=args.qspi_ini)
     @classmethod
     def do_add_parser(cls, parser):
         super().do_add_parser(parser)
@@ -85,7 +96,7 @@ def do_exec_op(self, op, force=False):
                     cmd.append('--sectoranduicrerase')
                 else:
                     cmd.append('--sectorerase')
-            elif erase == 'NO_ERASE':
+            elif erase == 'ERASE_NONE':
                 pass
             else:
                 raise RuntimeError(f'Invalid erase mode: {erase}')
diff --git a/scripts/west_commands/runners/nrfutil.py b/scripts/west_commands/runners/nrfutil.py
index f937da74c07..e7efda9ac5a 100644
--- a/scripts/west_commands/runners/nrfutil.py
+++ b/scripts/west_commands/runners/nrfutil.py
@@ -17,11 +17,13 @@ class NrfUtilBinaryRunner(NrfBinaryRunner):
     '''Runner front-end for nrfutil.'''
 
     def __init__(self, cfg, family, softreset, pinreset, dev_id, erase=False,
-                 reset=True, tool_opt=None, force=False, recover=False,
-                 suit_starter=False, ext_mem_config_file=None):
+                 erase_mode=None, ext_erase_mode=None, reset=True, tool_opt=None,
+                 force=False, recover=False, suit_starter=False,
+                 ext_mem_config_file=None):
 
-        super().__init__(cfg, family, softreset, pinreset, dev_id, erase, reset,
-                         tool_opt, force, recover)
+        super().__init__(cfg, family, softreset, pinreset, dev_id, erase,
+                         erase_mode, ext_erase_mode, reset, tool_opt, force,
+                         recover)
 
         self.suit_starter = suit_starter
         self.ext_mem_config_file = ext_mem_config_file
@@ -33,6 +35,15 @@ def __init__(self, cfg, family, softreset, pinreset, dev_id, erase=False,
     def name(cls):
         return 'nrfutil'
 
+    @classmethod
+    def capabilities(cls):
+        return NrfBinaryRunner._capabilities(mult_dev_ids=True)
+
+    @classmethod
+    def dev_id_help(cls) -> str:
+        return NrfBinaryRunner._dev_id_help() + \
+               '''.\n This option can be specified multiple times'''
+
     @classmethod
     def tool_opt_help(cls) -> str:
         return 'Additional options for nrfutil, e.g. "--log-level"'
@@ -41,9 +52,10 @@ def tool_opt_help(cls) -> str:
     def do_create(cls, cfg, args):
         return NrfUtilBinaryRunner(cfg, args.nrf_family, args.softreset,
                                    args.pinreset, args.dev_id, erase=args.erase,
-                                   reset=args.reset,
-                                   tool_opt=args.tool_opt, force=args.force,
-                                   recover=args.recover,
+                                   erase_mode=args.erase_mode,
+                                   ext_erase_mode=args.ext_erase_mode,
+                                   reset=args.reset, tool_opt=args.tool_opt,
+                                   force=args.force, recover=args.recover,
                                    suit_starter=args.suit_manifest_starter,
                                    ext_mem_config_file=args.ext_mem_config_file)
 
@@ -57,7 +69,6 @@ def do_add_parser(cls, parser):
                             dest='ext_mem_config_file',
                             help='path to an JSON file with external memory configuration')
 
-
     def _exec(self, args):
         jout_all = []
 
@@ -107,6 +118,12 @@ def _insert_op(self, op):
         self._op_id += 1
         self._ops.append(op)
 
+    def _format_dev_ids(self):
+        if isinstance(self.dev_id, list):
+            return ','.join(self.dev_id)
+        else:
+            return self.dev_id
+
     def _append_batch(self, op, json_file):
         _op = op['operation']
         op_type = _op['type']
@@ -151,7 +168,7 @@ def _exec_batch(self):
             precmd = ['--x-ext-mem-config-file', self.ext_mem_config_file]
 
         self._exec(precmd + ['x-execute-batch', '--batch-path', f'{json_file}',
-                             '--serial-number', f'{self.dev_id}'])
+                             '--serial-number', self._format_dev_ids()])
 
     def do_exec_op(self, op, force=False):
         self.logger.debug(f'Executing op: {op}')
diff --git a/scripts/west_commands/runners/openocd.py b/scripts/west_commands/runners/openocd.py
index d97cec1fe1e..abb4a580928 100644
--- a/scripts/west_commands/runners/openocd.py
+++ b/scripts/west_commands/runners/openocd.py
@@ -9,11 +9,16 @@
 
 import re
 import subprocess
+from os import name as os_name
 from os import path
 from pathlib import Path
 
 from zephyr_ext_common import ZEPHYR_BASE
 
+if os_name != "nt":
+    import sys
+    import termios
+
 try:  # noqa SIM105
     from elftools.elf.elffile import ELFFile
 except ImportError:
@@ -44,8 +49,8 @@ class OpenOcdBinaryRunner(ZephyrBinaryRunner):
     '''Runner front-end for openocd.'''
 
     def __init__(self, cfg, pre_init=None, reset_halt_cmd=DEFAULT_OPENOCD_RESET_HALT_CMD,
-                 pre_load=None, load_cmd=None, verify_cmd=None, post_verify=None,
-                 do_verify=False, do_verify_only=False,
+                 pre_load=None, erase_cmd=None, load_cmd=None, verify_cmd=None,
+                 post_verify=None, do_verify=False, do_verify_only=False, do_erase=False,
                  tui=None, config=None, serial=None, use_elf=None,
                  no_halt=False, no_init=False, no_targets=False,
                  tcl_port=DEFAULT_OPENOCD_TCL_PORT,
@@ -93,11 +98,13 @@ def __init__(self, cfg, pre_init=None, reset_halt_cmd=DEFAULT_OPENOCD_RESET_HALT
         self.pre_init = pre_init or []
         self.reset_halt_cmd = reset_halt_cmd
         self.pre_load = pre_load or []
+        self.erase_cmd = erase_cmd
         self.load_cmd = load_cmd
         self.verify_cmd = verify_cmd
         self.post_verify = post_verify or []
         self.do_verify = do_verify or False
         self.do_verify_only = do_verify_only or False
+        self.do_erase = do_erase or False
         self.tcl_port = tcl_port
         self.telnet_port = telnet_port
         self.gdb_port = gdb_port
@@ -120,7 +127,8 @@ def name(cls):
 
     @classmethod
     def capabilities(cls):
-        return RunnerCaps(commands={'flash', 'debug', 'debugserver', 'attach', 'rtt'}, rtt=True)
+        return RunnerCaps(commands={'flash', 'debug', 'debugserver', 'attach', 'rtt'},
+                          rtt=True, erase=True)
 
     @classmethod
     def do_add_parser(cls, parser):
@@ -142,6 +150,8 @@ def do_add_parser(cls, parser):
         parser.add_argument('--cmd-pre-load', action='append',
                             help='''Command to run before flashing;
                             may be given multiple times''')
+        parser.add_argument('--cmd-erase', action='append',
+                            help='''Command to erase device; may be given multiple times''')
         parser.add_argument('--cmd-load',
                             help='''Command to load/flash binary
                             (required when flashing)''')
@@ -191,9 +201,9 @@ def do_create(cls, cfg, args):
         return OpenOcdBinaryRunner(
             cfg,
             pre_init=args.cmd_pre_init, reset_halt_cmd=args.cmd_reset_halt,
-            pre_load=args.cmd_pre_load, load_cmd=args.cmd_load,
+            pre_load=args.cmd_pre_load, erase_cmd=args.cmd_erase, load_cmd=args.cmd_load,
             verify_cmd=args.cmd_verify, post_verify=args.cmd_post_verify,
-            do_verify=args.verify, do_verify_only=args.verify_only,
+            do_verify=args.verify, do_verify_only=args.verify_only, do_erase=args.erase,
             tui=args.tui, config=args.config, serial=args.serial,
             use_elf=args.use_elf, no_halt=args.no_halt, no_init=args.no_init,
             no_targets=args.no_targets, tcl_port=args.tcl_port,
@@ -222,7 +232,8 @@ def read_version(self):
         out = self.check_output([self.openocd_cmd[0], '--version'],
                                 stderr=subprocess.STDOUT).decode()
 
-        version_match = re.search(r"Open On-Chip Debugger (\d+.\d+.\d+)", out)
+        # Account for version info format of ADI fork of OpenOCD as well
+        version_match = re.search(r"Open On-Chip Debugger.* v?(\d+.\d+.\d+)", out)
         version = version_match.group(1).split('.')
 
         return [to_num(i) for i in version]
@@ -285,8 +296,20 @@ def do_flash(self, **kwargs):
 
         load_image = []
         if not self.do_verify_only:
-            load_image = ['-c', self.reset_halt_cmd,
-                          '-c', self.load_cmd + ' ' + hex_name]
+            # Halt target
+            load_image = ['-c', self.reset_halt_cmd]
+            # Perform any erase operations
+            if self.do_erase:
+                if self.erase_cmd is None:
+                    self.logger.error('--erase not supported for target without --cmd-erase')
+                    return
+                for erase_cmd in self.erase_cmd:
+                    load_image += ["-c", erase_cmd]
+                # Trim the "erase" from "flash write_image erase" since a mass erase is already done
+                if self.load_cmd.endswith(' erase'):
+                    self.load_cmd = self.load_cmd[:-6]
+            # Load image
+            load_image +=['-c', self.load_cmd + ' ' + hex_name]
 
         verify_image = []
         if self.do_verify or self.do_verify_only:
@@ -405,12 +428,29 @@ def do_attach_debug_rtt(self, command, **kwargs):
         elif command == 'rtt':
             self.print_rttserver_message()
             server_proc = self.popen_ignore_int(server_cmd)
+
+            if os_name != 'nt':
+                # Save the terminal settings
+                fd = sys.stdin.fileno()
+                new_term = termios.tcgetattr(fd)
+                old_term = termios.tcgetattr(fd)
+
+                # New terminal setting unbuffered
+                new_term[3] = new_term[3] & ~termios.ICANON & ~termios.ECHO
+                termios.tcsetattr(fd, termios.TCSAFLUSH, new_term)
+            else:
+                fd = None
+                old_term = None
+
             try:
                 # run the binary with gdb, set up the rtt server (runs to completion)
                 subprocess.run(gdb_cmd)
                 # run the rtt client in the foreground
                 self.run_telnet_client('localhost', self.rtt_port)
             finally:
+                if old_term is not None and fd is not None:
+                    termios.tcsetattr(fd, termios.TCSAFLUSH, old_term)
+
                 server_proc.terminate()
                 server_proc.wait()
 
diff --git a/scripts/west_commands/runners/rfp.py b/scripts/west_commands/runners/rfp.py
new file mode 100644
index 00000000000..507c36e3642
--- /dev/null
+++ b/scripts/west_commands/runners/rfp.py
@@ -0,0 +1,120 @@
+# Copyright (c) 2025 Pete Johanson
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# pylint: disable=duplicate-code
+
+'''Runner for rfp.'''
+
+import platform
+import re
+
+from runners.core import RunnerCaps, ZephyrBinaryRunner
+
+if platform.system() == 'Darwin':
+    DEFAULT_RFP_PORT = None
+else:
+    DEFAULT_RFP_PORT = '/dev/ttyACM0'
+
+
+def to_num(number):
+    dev_match = re.search(r"^\d*\+dev", number)
+    dev_version = dev_match is not None
+
+    num_match = re.search(r"^\d*", number)
+    num = int(num_match.group(0))
+
+    if dev_version:
+        num += 1
+
+    return num
+
+
+class RfpBinaryRunner(ZephyrBinaryRunner):
+    '''Runner front-end for rfp.'''
+
+    def __init__(
+        self,
+        cfg,
+        rfp_cli='rfp-cli',
+        device=None,
+        erase=False,
+        verify=False,
+        port=DEFAULT_RFP_PORT,
+        speed=None,
+    ):
+        super().__init__(cfg)
+
+        self.rfp_cmd = [rfp_cli]
+        self.verify = verify
+        self.erase = erase
+        self.port = port
+        self.device = device
+        self.speed = speed
+
+    @classmethod
+    def name(cls):
+        return 'rfp'
+
+    @classmethod
+    def capabilities(cls):
+        return RunnerCaps(commands={'flash'}, erase=True)
+
+    @classmethod
+    def do_add_parser(cls, parser):
+        parser.add_argument(
+            '--rfp-cli', default='rfp-cli', help='path to rfp-cli, default is rfp-cli'
+        )
+        parser.add_argument(
+            '--port',
+            default=DEFAULT_RFP_PORT,
+            help='serial port to use, default is ' + str(DEFAULT_RFP_PORT),
+        )
+        parser.add_argument('--device', help='Specify the device type to pass to rfp-cli')
+        parser.add_argument('--verify', action='store_true', help='if given, verify after flash')
+        parser.add_argument('--speed', help='Specify the serial port speed')
+
+    @classmethod
+    def do_create(cls, cfg, args):
+        return RfpBinaryRunner(
+            cfg,
+            rfp_cli=args.rfp_cli,
+            device=args.device,
+            port=args.port,
+            erase=args.erase,
+            speed=args.speed,
+            verify=args.verify,
+        )
+
+    def do_run(self, command, **kwargs):
+        if command == 'flash':
+            self.do_flash(**kwargs)
+        else:
+            self.logger.error("Unsuppported command")
+
+    def do_flash(self, **kwargs):
+        self.ensure_output('hex')
+
+        hex_name = self.cfg.hex_file
+
+        self.logger.info(f'Flashing file: {hex_name}')
+
+        load_image = ['-run']
+        if self.erase:
+            load_image += ['-erase']
+        else:
+            load_image += ['-noerase']
+
+        if self.verify:
+            load_image += ['-v']
+
+        # Load image
+        load_image += ['-p', '-file', hex_name]
+
+        port = ['-port', self.port]
+        if self.speed:
+            port += ['-s', self.speed]
+        device = ['-device', self.device]
+
+        cmd = self.rfp_cmd + port + device + load_image
+        self.check_call(cmd)
diff --git a/scripts/west_commands/runners/stm32cubeprogrammer.py b/scripts/west_commands/runners/stm32cubeprogrammer.py
index 432d7431b76..1335fa3c66e 100644
--- a/scripts/west_commands/runners/stm32cubeprogrammer.py
+++ b/scripts/west_commands/runners/stm32cubeprogrammer.py
@@ -34,7 +34,10 @@ def __init__(
         port: str,
         frequency: int | None,
         reset_mode: str | None,
+        download_address: int | None,
+        download_modifiers: list[str],
         start_address: int | None,
+        start_modifiers: list[str],
         conn_modifiers: str | None,
         cli: Path | None,
         use_elf: bool,
@@ -46,7 +49,17 @@ def __init__(
 
         self._port = port
         self._frequency = frequency
+
+        self._download_address = download_address
+        self._download_modifiers: list[str] = list()
+        for opts in [shlex.split(opt) for opt in download_modifiers]:
+            self._download_modifiers += opts
+
         self._start_address = start_address
+        self._start_modifiers: list[str] = list()
+        for opts in [shlex.split(opt) for opt in start_modifiers]:
+            self._start_modifiers += opts
+
         self._reset_mode = reset_mode
         self._conn_modifiers = conn_modifiers
         self._cli = (
@@ -133,6 +146,10 @@ def capabilities(cls):
 
     @classmethod
     def do_add_parser(cls, parser):
+        # To accept arguments in hex format, a wrapper lambda around int() must be used.
+        # Wrapping the lambda with functools.wraps() makes it so that 'invalid int value'
+        # is displayed when an invalid value is provided for these arguments.
+        multi_base=functools.wraps(int)(lambda s: int(s, base=0))
         parser.add_argument(
             "--port",
             type=str,
@@ -149,15 +166,32 @@ def do_add_parser(cls, parser):
             choices=["sw", "hw", "core"],
             help="Reset mode",
         )
+        parser.add_argument(
+            "--download-address",
+            type=multi_base,
+            required=False,
+            help="Flashing location address. If present, .bin used instead of .hex"
+        )
+        parser.add_argument(
+            "--download-modifiers",
+            default=[],
+            required=False,
+            action='append',
+            help="Additional options for the --download argument"
+        )
         parser.add_argument(
             "--start-address",
-            # To accept arguments in hex format, a wrapper lambda around int() must be used.
-            # Wrapping the lambda with functools.wraps() makes it so that 'invalid int value'
-            # is displayed when an invalid value is provided for this argument.
-            type=functools.wraps(int)(lambda s: int(s, base=0)),
+            type=multi_base,
             required=False,
             help="Address where execution should begin after flashing"
         )
+        parser.add_argument(
+            "--start-modifiers",
+            default=[],
+            required=False,
+            action='append',
+            help="Additional options for the --start argument"
+        )
         parser.add_argument(
             "--conn-modifiers",
             type=str,
@@ -194,7 +228,10 @@ def do_create(
             port=args.port,
             frequency=args.frequency,
             reset_mode=args.reset_mode,
+            download_address=args.download_address,
+            download_modifiers=args.download_modifiers,
             start_address=args.start_address,
+            start_modifiers=args.start_modifiers,
             conn_modifiers=args.conn_modifiers,
             cli=args.cli,
             use_elf=args.use_elf,
@@ -232,14 +269,32 @@ def flash(self, **kwargs) -> None:
         if self._erase:
             self.check_call(cmd + ["--erase", "all"])
 
-        # flash image and run application
-        dl_file = self.cfg.elf_file if self._use_elf else self.cfg.hex_file
+        # Define binary to be loaded
+        if self._use_elf:
+            # Use elf file if instructed to do so.
+            dl_file = self.cfg.elf_file
+        elif (self.cfg.bin_file is not None and
+               (self._download_address is not None or
+                  (str(self._port).startswith("usb") and self._download_modifiers is not None))):
+            # Use bin file if a binary is available and
+            # --download-address provided
+            # or flashing by dfu (port=usb and download-modifier used)
+            dl_file = self.cfg.bin_file
+        elif self.cfg.hex_file is not None:
+            # Neither --use-elf nor --download-address are present:
+            # default to flashing using hex file.
+            dl_file = self.cfg.hex_file
+
+        # Verify file configuration
         if dl_file is None:
             raise RuntimeError('cannot flash; no download file was specified')
         elif not os.path.isfile(dl_file):
             raise RuntimeError(f'download file {dl_file} does not exist')
 
         flash_and_run_args = ["--download", dl_file]
+        if self._download_address is not None:
+            flash_and_run_args.append(f"0x{self._download_address:X}")
+        flash_and_run_args += self._download_modifiers
 
         # '--start' is needed to start execution after flash.
         # The default start address is the beggining of the flash,
@@ -247,5 +302,6 @@ def flash(self, **kwargs) -> None:
         flash_and_run_args.append("--start")
         if self._start_address is not None:
             flash_and_run_args.append(f"0x{self._start_address:X}")
+        flash_and_run_args += self._start_modifiers
 
         self.check_call(cmd + flash_and_run_args)
diff --git a/scripts/west_commands/runners/sy1xx.py b/scripts/west_commands/runners/sy1xx.py
new file mode 100755
index 00000000000..5cb9719b0ac
--- /dev/null
+++ b/scripts/west_commands/runners/sy1xx.py
@@ -0,0 +1,74 @@
+# Copyright (c) 2025 sensry.io
+# SPDX-License-Identifier: Apache-2.0
+
+'''Runner for Sensry SY1xx Soc Flashing Tool.'''
+
+import importlib.util
+
+from runners.core import RunnerCaps, ZephyrBinaryRunner
+
+
+class Sy1xxBinaryRunner(ZephyrBinaryRunner):
+    '''Runner front-end for Sensry SY1xx Soc'''
+
+    def __init__(self, cfg, dev_id=None):
+        super().__init__(cfg)
+        print(cfg)
+        self.bin_file = cfg.bin_file
+        self.dev_id = dev_id
+
+    @classmethod
+    def name(cls):
+        return 'sy1xx'
+
+    @classmethod
+    def capabilities(cls):
+        return RunnerCaps(commands={'flash'}, dev_id=True)
+
+    @classmethod
+    def do_add_parser(cls, parser):
+        parser.set_defaults(dev_id='/dev/ttyUSB0')
+
+    @classmethod
+    def dev_id_help(cls) -> str:
+        return 'Device identifier such as /dev/ttyUSB0'
+
+    @classmethod
+    def do_create(cls, cfg, args):
+        # make sure the ganymed tools are installed
+        if importlib.util.find_spec('ganymed') is None:
+            raise RuntimeError("ganymed not found; can be installed with 'pip install ganymed'")
+
+        if not hasattr(args, "dev_id") or args.dev_id is None:
+            raise RuntimeError("missing --dev-id argument, such as /dev/ttyUSB0")
+
+        return Sy1xxBinaryRunner(cfg, args.dev_id)
+
+    def do_run(self, command, **kwargs):
+        if command == 'flash':
+            self.flash(**kwargs)
+
+    def flash(self, **kwargs):
+        self.logger.info(f'Flashing file: {self.bin_file} to {self.dev_id}')
+
+        from ganymed.bootloader import Bootloader
+
+        # convert binary to application ganymed-image
+        application_gnm = Bootloader.convert_zephyr_bin(self.bin_file)
+
+        # create the loader
+        flash_loader = Bootloader()
+
+        # connect to serial
+        flash_loader.connect(self.dev_id)
+
+        # set the controller into bootloader mode
+        flash_loader.enter_loading_mode()
+
+        # clear the internal flash
+        flash_loader.clear_mram()
+
+        # write the new binary
+        flash_loader.write_image(application_gnm)
+
+        self.logger.info('Flashing SY1xx finished. You may reset the device.')
diff --git a/scripts/west_commands/runners/xsdb.py b/scripts/west_commands/runners/xsdb.py
index e084a917a0c..7029a3a9354 100644
--- a/scripts/west_commands/runners/xsdb.py
+++ b/scripts/west_commands/runners/xsdb.py
@@ -54,5 +54,5 @@ def do_run(self, command, **kwargs):
         elif self.fsbl:
             cmd = ['xsdb', self.xsdb_cfg_file, self.elf_file, self.fsbl]
         else:
-            cmd = ['xsdb', self.xsdb_cfg_file]
+            cmd = ['xsdb', self.xsdb_cfg_file, self.elf_file]
         self.check_call(cmd)
diff --git a/scripts/west_commands/sdk.py b/scripts/west_commands/sdk.py
index 396edc92282..8a84f063dc9 100755
--- a/scripts/west_commands/sdk.py
+++ b/scripts/west_commands/sdk.py
@@ -4,6 +4,7 @@
 
 import argparse
 import hashlib
+import io
 import os
 import patoolib
 import platform
@@ -14,6 +15,7 @@
 import subprocess
 import tempfile
 import textwrap
+import tqdm
 import zcmake
 from pathlib import Path
 
@@ -313,10 +315,41 @@ def download_and_extract(self, base_dir, dir_name, target_release, req_headers):
                 total_length = int(resp.headers["Content-Length"])
                 count = 0
 
+                class WestLogAdapter(io.StringIO):
+                    buf = []
+                    ctx = None
+
+                    def __init__(self, ctx):
+                        super(__class__, self).__init__()
+                        self.ctx = ctx
+
+                    def write(self, buf):
+                        try:
+                            self.ctx.inf(buf, colorize=False, end='')
+                        except TypeError:
+                            # West v1.1.0 and earlier versions do not support the end parameter.
+                            self.ctx.inf(buf, colorize=False)
+
+                    def flush(self):
+                        pass
+
+                tbar = tqdm.tqdm(
+                    total=total_length,
+                    file=WestLogAdapter(self),
+                    desc=Path(file.name).name,
+                    unit_scale=True,
+                    ncols=shutil.get_terminal_size().columns,
+                    unit="",
+                    bar_format="{desc}: {percentage:3.0f}%|{bar}|   {n_fmt} {rate_fmt}   [{elapsed}]        ",
+                )
+
                 for chunk in resp.iter_content(chunk_size=8192):
+                    tbar.update(len(chunk))
                     file.write(chunk)
                     count = count + len(chunk)
-                    self.inf(f"\r {count}/{total_length}", end="")
+
+                tbar.close()
+
                 self.inf()
                 self.inf(f"Downloaded: {file.name}")
                 file.close()
diff --git a/scripts/west_commands/sign.py b/scripts/west_commands/sign.py
index 3378d584e0b..411563068b0 100644
--- a/scripts/west_commands/sign.py
+++ b/scripts/west_commands/sign.py
@@ -421,6 +421,17 @@ def rimage_config_dir(self):
         self.command.dbg(f'rimage config directory={conf_dir}')
         return conf_dir
 
+    def generate_uuid_registry(self):
+        'Runs the uuid-registry.h generator script'
+
+        generate_cmd = [sys.executable, str(self.sof_src_dir / 'scripts' / 'gen-uuid-reg.py'),
+                        str(self.sof_src_dir / 'uuid-registry.txt'),
+                        str(pathlib.Path('zephyr') / 'include' / 'generated' / 'uuid-registry.h')
+                       ]
+
+        self.command.inf(quote_sh_list(generate_cmd))
+        subprocess.run(generate_cmd, check=True, cwd=self.build_dir)
+
     def preprocess_toml(self, config_dir, toml_basename, subdir):
         'Runs the C pre-processor on config_dir/toml_basename.h'
 
@@ -444,6 +455,9 @@ def preprocess_toml(self, config_dir, toml_basename, subdir):
         preproc_cmd += ['-I', str(self.sof_src_dir / 'src')]
         preproc_cmd += ['-imacros',
                         str(pathlib.Path('zephyr') / 'include' / 'generated' / 'zephyr' / 'autoconf.h')]
+        preproc_cmd += ['-imacros',
+                        str(pathlib.Path('zephyr') / 'include' / 'generated' / 'uuid-registry.h')]
+
         # Need to preprocess the TOML file twice: once with
         # LLEXT_FORCE_ALL_MODULAR defined and once without it
         full_preproc_cmd = preproc_cmd + ['-o', str(subdir / 'rimage_config_full.toml'), '-DLLEXT_FORCE_ALL_MODULAR']
@@ -552,6 +566,7 @@ def sign(self, command, build_dir, build_conf, formats):
         is_sof_build = build_conf.getboolean('CONFIG_SOF')
         if not is_sof_build:
             no_manifest = True
+            self.generate_uuid_registry()
 
         if no_manifest:
             extra_ri_args = [ ]
diff --git a/scripts/west_commands/spdx.py b/scripts/west_commands/spdx.py
index 7a10b441534..d4d366480ac 100644
--- a/scripts/west_commands/spdx.py
+++ b/scripts/west_commands/spdx.py
@@ -74,8 +74,9 @@ def do_run_init(self, args):
         if query_ready:
             self.inf("initialized; run `west build` then run `west spdx`")
         else:
-            self.err("Couldn't create CMake file-based API query directory")
-            self.err("You can manually create an empty file at $BUILDDIR/.cmake/api/v1/query/codemodel-v2")
+            self.die("Couldn't create CMake file-based API query directory\n"
+                     "You can manually create an empty file at "
+                     "$BUILDDIR/.cmake/api/v1/query/codemodel-v2")
 
     def do_run_spdx(self, args):
         if not args.build_dir:
@@ -110,4 +111,5 @@ def do_run_spdx(self, args):
             # create the directory
             os.makedirs(cfg.spdxDir, exist_ok=False)
 
-        makeSPDX(cfg)
+        if not makeSPDX(cfg):
+            self.die("Failed to create SPDX output")
diff --git a/scripts/west_commands/tests/test_imports.py b/scripts/west_commands/tests/test_imports.py
index 3fb08b68a9e..f59ba65daa9 100644
--- a/scripts/west_commands/tests/test_imports.py
+++ b/scripts/west_commands/tests/test_imports.py
@@ -46,10 +46,12 @@ def test_runner_imports():
         'qemu',
         'renode',
         'renode-robot',
+        'rfp',
         'silabs_commander',
         'spi_burn',
         'stm32cubeprogrammer',
         'stm32flash',
+        'sy1xx',
         'teensy',
         'trace32',
         'uf2',
diff --git a/scripts/west_commands/tests/test_rfp.py b/scripts/west_commands/tests/test_rfp.py
new file mode 100644
index 00000000000..26440f8dbc8
--- /dev/null
+++ b/scripts/west_commands/tests/test_rfp.py
@@ -0,0 +1,256 @@
+# Copyright (c) 2025 Pete Johanson
+#
+# SPDX-License-Identifier: Apache-2.0
+
+import argparse
+import os
+from unittest.mock import call, patch
+
+from conftest import RC_KERNEL_HEX
+from runners.rfp import RfpBinaryRunner
+
+TEST_RFP_PORT = 'test-rfp-serial'
+TEST_RFP_PORT_SPEED = '115200'
+TEST_RFP_DEVICE = 'RA'
+TEST_RFP_USR_LOCAL_RFP_CLI = '/usr/local/bin/rfp-cli'
+
+EXPECTED_COMMANDS = [
+    [
+        'rfp-cli',
+        '-port',
+        TEST_RFP_PORT,
+        '-device',
+        TEST_RFP_DEVICE,
+        '-run',
+        '-noerase',
+        '-p',
+        '-file',
+        RC_KERNEL_HEX,
+    ],
+]
+
+EXPECTED_COMMANDS_WITH_SPEED = [
+    [
+        'rfp-cli',
+        '-port',
+        TEST_RFP_PORT,
+        '-s',
+        TEST_RFP_PORT_SPEED,
+        '-device',
+        TEST_RFP_DEVICE,
+        '-run',
+        '-noerase',
+        '-p',
+        '-file',
+        RC_KERNEL_HEX,
+    ],
+]
+
+
+EXPECTED_COMMANDS_WITH_ERASE = [
+    [
+        'rfp-cli',
+        '-port',
+        TEST_RFP_PORT,
+        '-device',
+        TEST_RFP_DEVICE,
+        '-run',
+        '-erase',
+        '-p',
+        '-file',
+        RC_KERNEL_HEX,
+    ],
+]
+
+EXPECTED_COMMANDS_WITH_VERIFY = [
+    [
+        'rfp-cli',
+        '-port',
+        TEST_RFP_PORT,
+        '-device',
+        TEST_RFP_DEVICE,
+        '-run',
+        '-noerase',
+        '-v',
+        '-p',
+        '-file',
+        RC_KERNEL_HEX,
+    ],
+]
+
+EXPECTED_COMMANDS_WITH_RFP_CLI = [
+    [
+        TEST_RFP_USR_LOCAL_RFP_CLI,
+        '-port',
+        TEST_RFP_PORT,
+        '-device',
+        TEST_RFP_DEVICE,
+        '-run',
+        '-noerase',
+        '-p',
+        '-file',
+        RC_KERNEL_HEX,
+    ],
+]
+
+
+def require_patch(program):
+    assert program in ['rfp']
+
+
+os_path_isfile = os.path.isfile
+
+
+def os_path_isfile_patch(filename):
+    if filename == RC_KERNEL_HEX:
+        return True
+    return os_path_isfile(filename)
+
+
+@patch('runners.core.ZephyrBinaryRunner.require', side_effect=require_patch)
+@patch('runners.core.ZephyrBinaryRunner.check_call')
+def test_rfp_init(cc, req, runner_config, tmpdir):
+    """
+    Test commands using a runner created by constructor.
+
+    Input:
+        port=A
+    device=B
+
+    Output:
+        -port A
+        -device B
+    """
+    runner = RfpBinaryRunner(runner_config, port=TEST_RFP_PORT, device=TEST_RFP_DEVICE)
+    with patch('os.path.isfile', side_effect=os_path_isfile_patch):
+        runner.run('flash')
+    assert cc.call_args_list == [call(x) for x in EXPECTED_COMMANDS]
+
+
+@patch('runners.core.ZephyrBinaryRunner.require', side_effect=require_patch)
+@patch('runners.core.ZephyrBinaryRunner.check_call')
+def test_rfp_create(cc, req, runner_config, tmpdir):
+    """
+    Test commands using a runner created from command line parameters.
+
+
+    Input:
+        ---port A
+    --device B
+
+    Output:
+        -port A
+        -device B
+    """
+    args = ['--port', str(TEST_RFP_PORT), "--device", str(TEST_RFP_DEVICE)]
+    parser = argparse.ArgumentParser(allow_abbrev=False)
+    RfpBinaryRunner.add_parser(parser)
+    arg_namespace = parser.parse_args(args)
+    runner = RfpBinaryRunner.create(runner_config, arg_namespace)
+    with patch('os.path.isfile', side_effect=os_path_isfile_patch):
+        runner.run('flash')
+    assert cc.call_args_list == [call(x) for x in EXPECTED_COMMANDS]
+
+
+@patch('runners.core.ZephyrBinaryRunner.require', side_effect=require_patch)
+@patch('runners.core.ZephyrBinaryRunner.check_call')
+def test_rfp_create_with_speed(cc, req, runner_config, tmpdir):
+    """
+    Test commands using a runner created from command line parameters.
+
+    Input:
+        --port
+        --speed
+    --speed
+
+    Output:
+        -s SPEED
+    """
+    args = [
+        '--device',
+        str(TEST_RFP_DEVICE),
+        '--port',
+        str(TEST_RFP_PORT),
+        '--speed',
+        str(TEST_RFP_PORT_SPEED),
+    ]
+    parser = argparse.ArgumentParser(allow_abbrev=False)
+    RfpBinaryRunner.add_parser(parser)
+    arg_namespace = parser.parse_args(args)
+    runner = RfpBinaryRunner.create(runner_config, arg_namespace)
+    with patch('os.path.isfile', side_effect=os_path_isfile_patch):
+        runner.run('flash')
+    assert cc.call_args_list == [call(x) for x in EXPECTED_COMMANDS_WITH_SPEED]
+
+
+@patch('runners.core.ZephyrBinaryRunner.require', side_effect=require_patch)
+@patch('runners.core.ZephyrBinaryRunner.check_call')
+def test_rfp_create_with_erase(cc, req, runner_config, tmpdir):
+    """
+    Test commands using a runner created from command line parameters.
+
+    Input:
+        --erase
+
+    Output:
+        -erase
+    """
+    args = ['--device', str(TEST_RFP_DEVICE), '--port', str(TEST_RFP_PORT), '--erase']
+    parser = argparse.ArgumentParser(allow_abbrev=False)
+    RfpBinaryRunner.add_parser(parser)
+    arg_namespace = parser.parse_args(args)
+    runner = RfpBinaryRunner.create(runner_config, arg_namespace)
+    with patch('os.path.isfile', side_effect=os_path_isfile_patch):
+        runner.run('flash')
+    assert cc.call_args_list == [call(x) for x in EXPECTED_COMMANDS_WITH_ERASE]
+
+
+@patch('runners.core.ZephyrBinaryRunner.require', side_effect=require_patch)
+@patch('runners.core.ZephyrBinaryRunner.check_call')
+def test_rfp_create_with_verify(cc, req, runner_config, tmpdir):
+    """
+    Test commands using a runner created from command line parameters.
+
+    Input:
+        --verify
+
+    Output:
+        -v
+    """
+    args = ['--device', str(TEST_RFP_DEVICE), '--port', str(TEST_RFP_PORT), '--verify']
+    parser = argparse.ArgumentParser(allow_abbrev=False)
+    RfpBinaryRunner.add_parser(parser)
+    arg_namespace = parser.parse_args(args)
+    runner = RfpBinaryRunner.create(runner_config, arg_namespace)
+    with patch('os.path.isfile', side_effect=os_path_isfile_patch):
+        runner.run('flash')
+    assert cc.call_args_list == [call(x) for x in EXPECTED_COMMANDS_WITH_VERIFY]
+
+
+@patch('runners.core.ZephyrBinaryRunner.require', side_effect=require_patch)
+@patch('runners.core.ZephyrBinaryRunner.check_call')
+def test_rfp_create_with_rfp_cli(cc, req, runner_config, tmpdir):
+    """
+    Test commands using a runner created from command line parameters.
+
+    Input:
+        --rfp-cli /usr/local/bin/rfp-cli
+
+    Output:
+        /usr/local/bin/rfp-cli
+    """
+    args = [
+        '--device',
+        str(TEST_RFP_DEVICE),
+        '--port',
+        str(TEST_RFP_PORT),
+        '--rfp-cli',
+        str(TEST_RFP_USR_LOCAL_RFP_CLI),
+    ]
+    parser = argparse.ArgumentParser(allow_abbrev=False)
+    RfpBinaryRunner.add_parser(parser)
+    arg_namespace = parser.parse_args(args)
+    runner = RfpBinaryRunner.create(runner_config, arg_namespace)
+    with patch('os.path.isfile', side_effect=os_path_isfile_patch):
+        runner.run('flash')
+    assert cc.call_args_list == [call(x) for x in EXPECTED_COMMANDS_WITH_RFP_CLI]
diff --git a/scripts/west_commands/tests/test_stm32cubeprogrammer.py b/scripts/west_commands/tests/test_stm32cubeprogrammer.py
index e574fd53276..252ac745bdb 100644
--- a/scripts/west_commands/tests/test_stm32cubeprogrammer.py
+++ b/scripts/west_commands/tests/test_stm32cubeprogrammer.py
@@ -3,14 +3,14 @@
 # SPDX-License-Identifier: Apache-2.0
 
 import argparse
+import os
 from pathlib import Path
 from unittest.mock import patch, call
 
 import pytest
 
 from runners.stm32cubeprogrammer import STM32CubeProgrammerBinaryRunner
-from conftest import RC_KERNEL_HEX, RC_KERNEL_ELF
-
+from conftest import RC_KERNEL_HEX, RC_KERNEL_ELF, RC_KERNEL_BIN
 
 CLI_PATH = Path("STM32_Programmer_CLI")
 """Default CLI path used in tests."""
@@ -64,8 +64,11 @@
         "port": "swd",
         "frequency": None,
         "reset_mode": None,
+        "download_address": None,
         "start_address": None,
         "conn_modifiers": None,
+        "start_modifiers": [],
+        "download_modifiers": [],
         "cli": CLI_PATH,
         "use_elf": False,
         "erase": False,
@@ -88,8 +91,11 @@
         "port": "swd",
         "frequency": None,
         "reset_mode": None,
+        "download_address": None,
         "start_address": 0x8001000,
         "conn_modifiers": None,
+        "start_modifiers": [],
+        "download_modifiers": [],
         "cli": CLI_PATH,
         "use_elf": False,
         "erase": False,
@@ -113,8 +119,11 @@
         "port": "swd",
         "frequency": "4000",
         "reset_mode": None,
+        "download_address": None,
         "start_address": None,
         "conn_modifiers": None,
+        "start_modifiers": [],
+        "download_modifiers": [],
         "cli": CLI_PATH,
         "use_elf": False,
         "erase": False,
@@ -137,8 +146,11 @@
         "port": "swd",
         "frequency": None,
         "reset_mode": "hw",
+        "download_address": None,
         "start_address": None,
         "conn_modifiers": None,
+        "start_modifiers": [],
+        "download_modifiers": [],
         "cli": CLI_PATH,
         "use_elf": False,
         "erase": False,
@@ -161,8 +173,11 @@
         "port": "swd",
         "frequency": None,
         "reset_mode": "sw",
+        "download_address": None,
         "start_address": None,
         "conn_modifiers": None,
+        "start_modifiers": [],
+        "download_modifiers": [],
         "cli": CLI_PATH,
         "use_elf": False,
         "erase": False,
@@ -185,8 +200,11 @@
         "port": "swd",
         "frequency": None,
         "reset_mode": "core",
+        "download_address": None,
         "start_address": None,
         "conn_modifiers": None,
+        "start_modifiers": [],
+        "download_modifiers": [],
         "cli": CLI_PATH,
         "use_elf": False,
         "erase": False,
@@ -209,8 +227,11 @@
         "port": "swd",
         "frequency": None,
         "reset_mode": None,
+        "download_address": None,
         "start_address": None,
         "conn_modifiers": "br=115200 sn=TEST",
+        "start_modifiers": [],
+        "download_modifiers": [],
         "cli": CLI_PATH,
         "use_elf": False,
         "erase": False,
@@ -233,8 +254,11 @@
         "port": "swd",
         "frequency": None,
         "reset_mode": None,
+        "download_address": None,
         "start_address": None,
         "conn_modifiers": None,
+        "start_modifiers": [],
+        "download_modifiers": [],
         "cli": CLI_PATH,
         "use_elf": True,
         "erase": False,
@@ -257,8 +281,11 @@
         "port": "swd",
         "frequency": None,
         "reset_mode": None,
+        "download_address": None,
         "start_address": None,
         "conn_modifiers": None,
+        "start_modifiers": [],
+        "download_modifiers": [],
         "cli": CLI_PATH,
         "use_elf": False,
         "erase": True,
@@ -282,8 +309,11 @@
         "port": "swd",
         "frequency": None,
         "reset_mode": None,
+        "download_address": None,
         "start_address": None,
         "conn_modifiers": None,
+        "start_modifiers": [],
+        "download_modifiers": [],
         "cli": CLI_PATH,
         "use_elf": False,
         "erase": False,
@@ -307,8 +337,11 @@
         "port": "swd",
         "frequency": None,
         "reset_mode": None,
+        "download_address": None,
         "start_address": None,
         "conn_modifiers": None,
+        "start_modifiers": [],
+        "download_modifiers": [],
         "cli": None,
         "use_elf": False,
         "erase": False,
@@ -331,8 +364,11 @@
         "port": "swd",
         "frequency": None,
         "reset_mode": None,
+        "download_address": None,
         "start_address": None,
         "conn_modifiers": None,
+        "start_modifiers": [],
+        "download_modifiers": [],
         "cli": None,
         "use_elf": False,
         "erase": False,
@@ -355,8 +391,11 @@
         "port": "swd",
         "frequency": None,
         "reset_mode": None,
+        "download_address": None,
         "start_address": None,
         "conn_modifiers": None,
+        "start_modifiers": [],
+        "download_modifiers": [],
         "cli": None,
         "use_elf": False,
         "erase": False,
@@ -375,9 +414,45 @@
             ],
         ],
     },
+    {
+        "port": "swd",
+        "frequency": None,
+        "reset_mode": None,
+        "download_address": 0x80000000,
+        "start_address": None,
+        "conn_modifiers": None,
+        "start_modifiers": ["noack"],
+        "download_modifiers": ["0x1"],
+        "cli": CLI_PATH,
+        "use_elf": False,
+        "erase": False,
+        "extload": None,
+        "tool_opt": [],
+        "system": "",
+        "cli_path": str(CLI_PATH),
+        "calls": [
+            [
+                str(CLI_PATH),
+                "--connect",
+                "port=swd",
+                "--download",
+                RC_KERNEL_BIN,
+                "0x80000000",
+                "0x1",
+                "--start",
+                "noack",
+            ],
+        ],
+    },
 )
 """Test cases."""
 
+os_path_isfile = os.path.isfile
+
+def os_path_isfile_patch(filename):
+    if filename == RC_KERNEL_BIN:
+        return True
+    return os_path_isfile(filename)
 
 @pytest.mark.parametrize("tc", TEST_CASES)
 @patch("runners.stm32cubeprogrammer.platform.system")
@@ -386,7 +461,9 @@
 @patch.dict("runners.stm32cubeprogrammer.os.environ", ENVIRON)
 @patch("runners.core.ZephyrBinaryRunner.require")
 @patch("runners.stm32cubeprogrammer.STM32CubeProgrammerBinaryRunner.check_call")
+@patch("os.path.isfile", side_effect=os_path_isfile_patch)
 def test_stm32cubeprogrammer_init(
+    os_path_isfile_patch,
     check_call, require, path_exists, path_home, system, tc, runner_config
 ):
     """Tests that ``STM32CubeProgrammerBinaryRunner`` class can be initialized
@@ -400,7 +477,10 @@ def test_stm32cubeprogrammer_init(
         port=tc["port"],
         frequency=tc["frequency"],
         reset_mode=tc["reset_mode"],
+        download_address=tc["download_address"],
+        download_modifiers=tc["download_modifiers"],
         start_address=tc["start_address"],
+        start_modifiers=tc["start_modifiers"],
         conn_modifiers=tc["conn_modifiers"],
         cli=tc["cli"],
         use_elf=tc["use_elf"],
@@ -422,7 +502,9 @@ def test_stm32cubeprogrammer_init(
 @patch.dict("runners.stm32cubeprogrammer.os.environ", ENVIRON)
 @patch("runners.core.ZephyrBinaryRunner.require")
 @patch("runners.stm32cubeprogrammer.STM32CubeProgrammerBinaryRunner.check_call")
+@patch("os.path.isfile", side_effect=os_path_isfile_patch)
 def test_stm32cubeprogrammer_create(
+    os_path_isfile_patch,
     check_call, require, path_exists, path_home, system, tc, runner_config
 ):
     """Tests that ``STM32CubeProgrammerBinaryRunner`` class can be created using
@@ -436,6 +518,8 @@ def test_stm32cubeprogrammer_create(
         args.extend(["--frequency", tc["frequency"]])
     if tc["reset_mode"]:
         args.extend(["--reset-mode", tc["reset_mode"]])
+    if tc["download_address"]:
+        args.extend(["--download-address", str(tc["download_address"])])
     if tc["start_address"]:
         args.extend(["--start-address", str(tc["start_address"])])
     if tc["conn_modifiers"]:
@@ -450,6 +534,10 @@ def test_stm32cubeprogrammer_create(
         args.extend(["--extload", tc["extload"]])
     if tc["tool_opt"]:
         args.extend(["--tool-opt", " " + tc["tool_opt"][0]])
+    if tc["download_modifiers"]:
+        args.extend(["--download-modifiers", " " + tc["download_modifiers"][0]])
+    if tc["start_modifiers"]:
+        args.extend(["--start-modifiers", " " + tc["start_modifiers"][0]])
 
     parser = argparse.ArgumentParser(allow_abbrev=False)
     STM32CubeProgrammerBinaryRunner.add_parser(parser)
diff --git a/scripts/west_commands/tests/test_xsdb.py b/scripts/west_commands/tests/test_xsdb.py
index ca97e7ad511..0711da5f38e 100644
--- a/scripts/west_commands/tests/test_xsdb.py
+++ b/scripts/west_commands/tests/test_xsdb.py
@@ -13,13 +13,13 @@
         "config": None,
         "bitstream": None,
         "fsbl": None,
-        "expected_cmd": ["xsdb", "default_cfg_path"],
+        "expected_cmd": ["xsdb", "default_cfg_path", RC_KERNEL_ELF],
     },
     {
         "config": "custom_cfg_path",
         "bitstream": None,
         "fsbl": None,
-        "expected_cmd": ["xsdb", "custom_cfg_path"],
+        "expected_cmd": ["xsdb", "custom_cfg_path", RC_KERNEL_ELF],
     },
     {
         "config": None,
diff --git a/scripts/west_commands/zspdx/scanner.py b/scripts/west_commands/zspdx/scanner.py
index cf6e71a0f23..21975242acd 100644
--- a/scripts/west_commands/zspdx/scanner.py
+++ b/scripts/west_commands/zspdx/scanner.py
@@ -115,7 +115,7 @@ def calculateVerificationCode(pkg):
     hashes.sort()
     filelist = "".join(hashes)
 
-    hSHA1 = hashlib.sha1()
+    hSHA1 = hashlib.sha1(usedforsecurity=False)
     hSHA1.update(filelist.encode('utf-8'))
     return hSHA1.hexdigest()
 
diff --git a/scripts/west_commands/zspdx/util.py b/scripts/west_commands/zspdx/util.py
index e02a981b602..05cfbdcd436 100644
--- a/scripts/west_commands/zspdx/util.py
+++ b/scripts/west_commands/zspdx/util.py
@@ -16,9 +16,9 @@ def getHashes(filePath):
     Returns: tuple of (SHA1, SHA256, MD5) hashes for filePath, or
              None if file is not found.
     """
-    hSHA1 = hashlib.sha1()
+    hSHA1 = hashlib.sha1(usedforsecurity=False)
     hSHA256 = hashlib.sha256()
-    hMD5 = hashlib.md5()
+    hMD5 = hashlib.md5(usedforsecurity=False)
 
     log.dbg(f"  - getting hashes for {filePath}")
 
diff --git a/scripts/west_commands/zspdx/walker.py b/scripts/west_commands/zspdx/walker.py
index eaa8c5dadc2..196c68228fe 100644
--- a/scripts/west_commands/zspdx/walker.py
+++ b/scripts/west_commands/zspdx/walker.py
@@ -77,12 +77,12 @@ def _build_purl(self, url, version=None):
 
         purl = None
         # This is designed to match repository with the following url pattern:
-        # '<protocol><base_url>/<namespace>/<package>
-        COMMON_GIT_URL_REGEX=r'((git@|http(s)?:\/\/)(?P<base_url>[\w\.@]+)(\/|:))(?P<namespace>[\w,\-,\_]+)\/(?P<package>[\w,\-,\_]+)(.git){0,1}((\/){0,1})$'
+        # '<protocol><type>/<namespace>/<package>
+        COMMON_GIT_URL_REGEX=r'((git@|http(s)?:\/\/)(?P<type>[\w\.@]+)(\.\w+)(\/|:))(?P<namespace>[\w,\-,\_\/]+)\/(?P<package>[\w,\-,\_]+)(.git){0,1}((\/){0,1})$'
 
         match = re.fullmatch(COMMON_GIT_URL_REGEX, url)
         if match:
-            purl = f'pkg:{match.group("base_url")}/{match.group("namespace")}/{match.group("package")}'
+            purl = f'pkg:{match.group("type")}/{match.group("namespace")}/{match.group("package")}'
 
         if purl and (version or len(version) > 0):
             purl += f'@{version}'
diff --git a/share/sysbuild/Kconfig b/share/sysbuild/Kconfig
index 69f2d4cd396..e2076941380 100644
--- a/share/sysbuild/Kconfig
+++ b/share/sysbuild/Kconfig
@@ -1,8 +1,35 @@
-# Copyright (c) 2021 Nordic Semiconductor
+# Copyright (c) 2021-2023 Nordic Semiconductor
 #
 # SPDX-License-Identifier: Apache-2.0
 
-rsource "Kconfig.$(HWM_SCHEME)"
+config BOARD
+	string
+	default "$(BOARD)"
+	help
+	  This option holds the name of the board and is used to locate the files
+	  related to the board in the source tree (under boards/).
+	  The Board is the first location where we search for a linker.ld file,
+	  if not found we look for the linker file in
+	  soc/<arch>/<family>/<series>
+
+config BOARD_REVISION
+	def_string "$(BOARD_REVISION)"
+	help
+	  If the BOARD has a revision field set, this is the revision.
+	  Otherwise, it is the empty string. For example, if BOARD is
+	  "plank@foo", this option will be "foo". If BOARD is "plank",
+	  this option will be the empty string.
+
+config BOARD_DEPRECATED_RELEASE
+	string
+	help
+	  This hidden option is set in the board configuration and indicates
+	  the Zephyr release that the board configuration will be removed.
+	  When set, any build for that board will generate a clearly visible
+	  deprecation warning.
+
+source "boards/Kconfig.v2"
+source "soc/Kconfig.v2"
 
 comment "Sysbuild image configuration"
 
diff --git a/share/sysbuild/Kconfig.v1 b/share/sysbuild/Kconfig.v1
deleted file mode 100644
index 58191354bb7..00000000000
--- a/share/sysbuild/Kconfig.v1
+++ /dev/null
@@ -1,5 +0,0 @@
-# Copyright (c) 2023 Nordic Semiconductor
-#
-# SPDX-License-Identifier: Apache-2.0
-
-# Intentionally left empty as sysbuild Kconfig doesn't support hw model v1.
diff --git a/share/sysbuild/Kconfig.v2 b/share/sysbuild/Kconfig.v2
index c8261b08616..424117c5794 100644
--- a/share/sysbuild/Kconfig.v2
+++ b/share/sysbuild/Kconfig.v2
@@ -28,5 +28,5 @@ config BOARD_DEPRECATED_RELEASE
 	  When set, any build for that board will generate a clearly visible
 	  deprecation warning.
 
-source "boards/Kconfig.$(HWM_SCHEME)"
-source "soc/Kconfig.$(HWM_SCHEME)"
+source "boards/Kconfig.v2"
+source "soc/Kconfig.v2"
diff --git a/share/sysbuild/cmake/modules/sysbuild_extensions.cmake b/share/sysbuild/cmake/modules/sysbuild_extensions.cmake
index 47a7ce2c939..4f5be601694 100644
--- a/share/sysbuild/cmake/modules/sysbuild_extensions.cmake
+++ b/share/sysbuild/cmake/modules/sysbuild_extensions.cmake
@@ -216,7 +216,7 @@ endfunction()
 #                             and debugging.
 #
 function(ExternalZephyrProject_Add)
-  set(app_types MAIN BOOTLOADER)
+  set(app_types MAIN BOOTLOADER FIRMWARE_LOADER)
   cmake_parse_arguments(ZBUILD "" "APPLICATION;BOARD;BOARD_REVISION;SOURCE_DIR;APP_TYPE;BUILD_ONLY" "" ${ARGN})
 
   if(ZBUILD_UNPARSED_ARGUMENTS)
@@ -397,23 +397,17 @@ function(ExternalZephyrProject_Add)
     # The sysbuild BOARD is exported through sysbuild cache, and will be used
     # unless <image>_BOARD is defined.
     if(DEFINED ZBUILD_BOARD_REVISION)
-      # Use provided board revision
-      if(ZBUILD_BOARD MATCHES "/")
-        # HWMv2 requires adding version to the board, split elements up, attach version, then
-        # reassemble into a complete string
-        string(REPLACE "/" ";" split_board_qualifiers "${ZBUILD_BOARD}")
-        list(GET split_board_qualifiers 0 target_board)
-        set(target_board ${target_board}@${ZBUILD_BOARD_REVISION})
-        list(REMOVE_AT split_board_qualifiers 0)
-        list(PREPEND split_board_qualifiers ${target_board})
-        string(REPLACE ";" "/" board_qualifiers "${split_board_qualifiers}")
-        set_target_properties(${ZBUILD_APPLICATION} PROPERTIES BOARD ${board_qualifiers})
-        set(split_board_qualifiers)
-        set(board_qualifiers)
-      else()
-        # Legacy HWMv1 support, version goes at end
-        set_target_properties(${ZBUILD_APPLICATION} PROPERTIES BOARD ${ZBUILD_BOARD}@${ZBUILD_BOARD_REVISION})
-      endif()
+      # Use provided board revision, HWMv2 requires adding version to the board, split elements
+      # up, attach version, then reassemble into a complete string
+      string(REPLACE "/" ";" split_board_qualifiers "${ZBUILD_BOARD}")
+      list(GET split_board_qualifiers 0 target_board)
+      set(target_board ${target_board}@${ZBUILD_BOARD_REVISION})
+      list(REMOVE_AT split_board_qualifiers 0)
+      list(PREPEND split_board_qualifiers ${target_board})
+      string(REPLACE ";" "/" board_qualifiers "${split_board_qualifiers}")
+      set_target_properties(${ZBUILD_APPLICATION} PROPERTIES BOARD ${board_qualifiers})
+      set(split_board_qualifiers)
+      set(board_qualifiers)
     else()
       set_target_properties(${ZBUILD_APPLICATION} PROPERTIES BOARD ${ZBUILD_BOARD})
     endif()
diff --git a/share/sysbuild/image_configurations/BOOTLOADER_image_default.cmake b/share/sysbuild/image_configurations/BOOTLOADER_image_default.cmake
index 8485cd77d59..9125de71fac 100644
--- a/share/sysbuild/image_configurations/BOOTLOADER_image_default.cmake
+++ b/share/sysbuild/image_configurations/BOOTLOADER_image_default.cmake
@@ -6,16 +6,20 @@
 # on Zephyr MCUboot / bootloader image.
 
 set(bootmodes CONFIG_SINGLE_APPLICATION_SLOT
+              CONFIG_BOOT_SWAP_USING_OFFSET
               CONFIG_BOOT_SWAP_USING_SCRATCH
               CONFIG_BOOT_UPGRADE_ONLY
               CONFIG_BOOT_SWAP_USING_MOVE
               CONFIG_BOOT_DIRECT_XIP
               CONFIG_BOOT_RAM_LOAD
-              CONFIG_BOOT_FIRMWARE_LOADER)
+              CONFIG_BOOT_FIRMWARE_LOADER
+              CONFIG_SINGLE_APPLICATION_SLOT_RAM_LOAD)
 
 if(SB_CONFIG_MCUBOOT_MODE_SINGLE_APP)
   set(bootmode CONFIG_SINGLE_APPLICATION_SLOT)
-elseif(SB_CONFIG_MCUBOOT_MODE_SWAP_WITHOUT_SCRATCH)
+elseif(SB_CONFIG_MCUBOOT_MODE_SWAP_USING_OFFSET)
+  set(bootmode CONFIG_BOOT_SWAP_USING_OFFSET)
+elseif(SB_CONFIG_MCUBOOT_MODE_SWAP_WITHOUT_SCRATCH OR SB_CONFIG_MCUBOOT_MODE_SWAP_USING_MOVE)
   set(bootmode CONFIG_BOOT_SWAP_USING_MOVE)
 elseif(SB_CONFIG_MCUBOOT_MODE_SWAP_SCRATCH)
   set(bootmode CONFIG_BOOT_SWAP_USING_SCRATCH)
@@ -25,8 +29,17 @@ elseif(SB_CONFIG_MCUBOOT_MODE_DIRECT_XIP OR SB_CONFIG_MCUBOOT_MODE_DIRECT_XIP_WI
   set(bootmode CONFIG_BOOT_DIRECT_XIP)
 elseif(SB_CONFIG_MCUBOOT_MODE_RAM_LOAD)
   set(bootmode CONFIG_BOOT_RAM_LOAD)
+elseif(SB_CONFIG_MCUBOOT_MODE_SINGLE_APP_RAM_LOAD)
+  set(bootmode CONFIG_SINGLE_APPLICATION_SLOT_RAM_LOAD)
 elseif(SB_CONFIG_MCUBOOT_MODE_FIRMWARE_UPDATER)
   set(bootmode CONFIG_BOOT_FIRMWARE_LOADER)
+
+  if(SB_CONFIG_MCUBOOT_MODE_FIRMWARE_UPDATER_BOOT_MODE_ENTRANCE)
+    set_config_bool(${ZCMAKE_APPLICATION} CONFIG_RETAINED_MEM y)
+    set_config_bool(${ZCMAKE_APPLICATION} CONFIG_RETENTION y)
+    set_config_bool(${ZCMAKE_APPLICATION} CONFIG_RETENTION_BOOT_MODE y)
+    set_config_bool(${ZCMAKE_APPLICATION} CONFIG_BOOT_FIRMWARE_LOADER_BOOT_MODE y)
+  endif()
 endif()
 
 foreach(loopbootmode ${bootmodes})
diff --git a/share/sysbuild/image_configurations/FIRMWARE_LOADER_image_default.cmake b/share/sysbuild/image_configurations/FIRMWARE_LOADER_image_default.cmake
new file mode 100644
index 00000000000..c4edc7e3daf
--- /dev/null
+++ b/share/sysbuild/image_configurations/FIRMWARE_LOADER_image_default.cmake
@@ -0,0 +1,22 @@
+# Copyright (c) 2025 Nordic Semiconductor
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# This sysbuild CMake file sets the sysbuild controlled settings as properties
+# on a firmware updater image.
+
+set_config_bool(${ZCMAKE_APPLICATION} CONFIG_BOOTLOADER_MCUBOOT "${SB_CONFIG_BOOTLOADER_MCUBOOT}")
+set_config_string(${ZCMAKE_APPLICATION} CONFIG_MCUBOOT_SIGNATURE_KEY_FILE
+                  "${SB_CONFIG_BOOT_SIGNATURE_KEY_FILE}"
+)
+set_config_string(${ZCMAKE_APPLICATION} CONFIG_MCUBOOT_ENCRYPTION_KEY_FILE
+                  "${SB_CONFIG_BOOT_ENCRYPTION_KEY_FILE}"
+)
+
+if("${SB_CONFIG_SIGNATURE_TYPE}" STREQUAL "NONE")
+  set_config_bool(${ZCMAKE_APPLICATION} CONFIG_MCUBOOT_GENERATE_UNSIGNED_IMAGE y)
+else()
+  set_config_bool(${ZCMAKE_APPLICATION} CONFIG_MCUBOOT_GENERATE_UNSIGNED_IMAGE n)
+endif()
+
+set_config_bool(${ZCMAKE_APPLICATION} CONFIG_MCUBOOT_BOOTLOADER_MODE_FIRMWARE_UPDATER y)
diff --git a/share/sysbuild/image_configurations/MAIN_image_default.cmake b/share/sysbuild/image_configurations/MAIN_image_default.cmake
index cd447a29d0c..a6c29c8d756 100644
--- a/share/sysbuild/image_configurations/MAIN_image_default.cmake
+++ b/share/sysbuild/image_configurations/MAIN_image_default.cmake
@@ -22,8 +22,10 @@ if(SB_CONFIG_BOOTLOADER_MCUBOOT)
 
   if(SB_CONFIG_MCUBOOT_MODE_SINGLE_APP)
     set_config_bool(${ZCMAKE_APPLICATION} CONFIG_MCUBOOT_BOOTLOADER_MODE_SINGLE_APP y)
-  elseif(SB_CONFIG_MCUBOOT_MODE_SWAP_WITHOUT_SCRATCH)
-    set_config_bool(${ZCMAKE_APPLICATION} CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_WITHOUT_SCRATCH y)
+  elseif(SB_CONFIG_MCUBOOT_MODE_SWAP_USING_OFFSET)
+    set_config_bool(${ZCMAKE_APPLICATION} CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_USING_OFFSET y)
+  elseif(SB_CONFIG_MCUBOOT_MODE_SWAP_WITHOUT_SCRATCH OR SB_CONFIG_MCUBOOT_MODE_SWAP_USING_MOVE)
+    set_config_bool(${ZCMAKE_APPLICATION} CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_USING_MOVE y)
   elseif(SB_CONFIG_MCUBOOT_MODE_SWAP_SCRATCH)
     set_config_bool(${ZCMAKE_APPLICATION} CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_SCRATCH y)
   elseif(SB_CONFIG_MCUBOOT_MODE_OVERWRITE_ONLY)
@@ -37,7 +39,16 @@ if(SB_CONFIG_BOOTLOADER_MCUBOOT)
     set_config_bool(${ZCMAKE_APPLICATION} CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD y)
     set_config_bool(${ZCMAKE_APPLICATION} CONFIG_XIP n)
     set_config_int(${ZCMAKE_APPLICATION} CONFIG_FLASH_SIZE 0)
+  elseif(SB_CONFIG_MCUBOOT_MODE_SINGLE_APP_RAM_LOAD)
+    set_config_bool(${ZCMAKE_APPLICATION} CONFIG_MCUBOOT_BOOTLOADER_MODE_SINGLE_APP_RAM_LOAD y)
   elseif(SB_CONFIG_MCUBOOT_MODE_FIRMWARE_UPDATER)
     set_config_bool(${ZCMAKE_APPLICATION} CONFIG_MCUBOOT_BOOTLOADER_MODE_FIRMWARE_UPDATER y)
+
+    if(SB_CONFIG_MCUBOOT_MODE_FIRMWARE_UPDATER_BOOT_MODE_ENTRANCE)
+      set_config_bool(${ZCMAKE_APPLICATION} CONFIG_REBOOT y)
+      set_config_bool(${ZCMAKE_APPLICATION} CONFIG_RETAINED_MEM y)
+      set_config_bool(${ZCMAKE_APPLICATION} CONFIG_RETENTION y)
+      set_config_bool(${ZCMAKE_APPLICATION} CONFIG_RETENTION_BOOT_MODE y)
+    endif()
   endif()
 endif()
diff --git a/share/sysbuild/images/CMakeLists.txt b/share/sysbuild/images/CMakeLists.txt
index 1d9e381fa5c..b6276a311c4 100644
--- a/share/sysbuild/images/CMakeLists.txt
+++ b/share/sysbuild/images/CMakeLists.txt
@@ -12,6 +12,7 @@ ExternalZephyrProject_Add(
 
 # This allows for MCUboot to be included.
 sysbuild_add_subdirectory(bootloader)
+sysbuild_add_subdirectory(firmware_loader)
 
 # Include zephyr modules generated sysbuild CMake file.
 foreach(SYSBUILD_CURRENT_MODULE_NAME ${SYSBUILD_MODULE_NAMES})
diff --git a/share/sysbuild/images/Kconfig b/share/sysbuild/images/Kconfig
index 616b0a7c23d..f247a0bd64a 100644
--- a/share/sysbuild/images/Kconfig
+++ b/share/sysbuild/images/Kconfig
@@ -3,3 +3,4 @@
 # SPDX-License-Identifier: Apache-2.0
 
 rsource "bootloader/Kconfig"
+rsource "firmware_loader/Kconfig"
diff --git a/share/sysbuild/images/bootloader/Kconfig b/share/sysbuild/images/bootloader/Kconfig
index df97b18e3e6..7a416f2fe23 100644
--- a/share/sysbuild/images/bootloader/Kconfig
+++ b/share/sysbuild/images/bootloader/Kconfig
@@ -32,7 +32,7 @@ if BOOTLOADER_MCUBOOT
 
 choice MCUBOOT_MODE
 	prompt "Mode of operation"
-	default MCUBOOT_MODE_SWAP_WITHOUT_SCRATCH
+	default MCUBOOT_MODE_SWAP_USING_MOVE
 	help
 	  The operating mode of MCUboot (which will also be propagated to the application).
 
@@ -43,13 +43,27 @@ config MCUBOOT_MODE_SINGLE_APP
 	  slots. In this mode application is not able to DFU its own update to secondary slot and
 	  all updates need to be performed using MCUboot serial recovery.
 
-config MCUBOOT_MODE_SWAP_WITHOUT_SCRATCH
-	bool "Swap without scratch (swap using move)"
+config MCUBOOT_MODE_SWAP_USING_OFFSET
+	bool "Swap using offset"
+	select EXPERIMENTAL
 	help
 	  MCUboot expects slot0_partition and slot1_partition to be present in DT and application
 	  will boot from slot0_partition. MCUBOOT_BOOTLOADER_NO_DOWNGRADE should also be selected
 	  in main application if MCUboot has been built with MCUBOOT_DOWNGRADE_PREVENTION.
 
+config MCUBOOT_MODE_SWAP_USING_MOVE
+	bool "Swap using move"
+	help
+	  MCUboot expects slot0_partition and slot1_partition to be present in DT and application
+	  will boot from slot0_partition. MCUBOOT_BOOTLOADER_NO_DOWNGRADE should also be selected
+	  in main application if MCUboot has been built with MCUBOOT_DOWNGRADE_PREVENTION.
+
+config MCUBOOT_MODE_SWAP_WITHOUT_SCRATCH
+	bool "Swap without scratch (swap using move) [DEPRECATED]"
+	select DEPRECATED
+	help
+	  This Kconfig is deprecated, use MCUBOOT_MODE_SWAP_USING_MOVE instead.
+
 config MCUBOOT_MODE_SWAP_SCRATCH
 	bool "Swap using scratch"
 	help
@@ -112,14 +126,35 @@ config MCUBOOT_MODE_FIRMWARE_UPDATER
 	  mechanism defined for entering the slot1_partition which is a dedicated firmware updater
 	  application used to update the slot0_partition application.
 
+config MCUBOOT_MODE_SINGLE_APP_RAM_LOAD
+	bool "Single app RAM load mode"
+	help
+	  MCUboot can load the image to RAM from an arbitrary location. In this mode,
+	  MCUboot will copy the image to RAM and begin execution from there. The image
+	  must be linked to execute from RAM, the address that it is copied to is
+	  specified using the load-addr argument when running imgtool.
+	  Note that while not used directly, a slot0_partition must be defined in the
+	  DT, as it is used to get information about size of the image to be loaded.
+	  This option automatically selects MCUBOOT_BOOTLOADER_NO_DOWNGRADE as it is
+	  not possible to swap back to older version of the application. In fact, none
+	  of the swap operations are supported in this mode.
+
 endchoice
 
+config MCUBOOT_MODE_FIRMWARE_UPDATER_BOOT_MODE_ENTRANCE
+	bool "Firmware updater retention boot mode entrance"
+	depends on MCUBOOT_MODE_FIRMWARE_UPDATER
+	help
+	  Will enable retained memory, retention and the boot mode module in MCUboot and the main
+	  application so that it can be used to force booting the firmware loader application
+	  image. This needs the ``zephyr,boot-mode`` chosen node to be correctly configured.
+
 config SIGNATURE_TYPE
 	string
-	default NONE if BOOT_SIGNATURE_TYPE_NONE
-	default RSA  if BOOT_SIGNATURE_TYPE_RSA
-	default ECDSA_P256 if BOOT_SIGNATURE_TYPE_ECDSA_P256
-	default ED25519 if BOOT_SIGNATURE_TYPE_ED25519
+	default "NONE" if BOOT_SIGNATURE_TYPE_NONE
+	default "RSA" if BOOT_SIGNATURE_TYPE_RSA
+	default "ECDSA_P256" if BOOT_SIGNATURE_TYPE_ECDSA_P256
+	default "ED25519" if BOOT_SIGNATURE_TYPE_ED25519
 
 choice BOOT_SIGNATURE_TYPE
 	prompt "Signature type"
diff --git a/share/sysbuild/images/firmware_loader/CMakeLists.txt b/share/sysbuild/images/firmware_loader/CMakeLists.txt
new file mode 100644
index 00000000000..21fbf62b118
--- /dev/null
+++ b/share/sysbuild/images/firmware_loader/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Nordic Semiconductor
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if(SB_CONFIG_FIRMWARE_LOADER_IMAGE_PATH)
+  ExternalZephyrProject_Add(
+    APPLICATION ${SB_CONFIG_FIRMWARE_LOADER_IMAGE_NAME}
+    SOURCE_DIR ${SB_CONFIG_FIRMWARE_LOADER_IMAGE_PATH}
+    APP_TYPE FIRMWARE_LOADER
+  )
+endif()
diff --git a/share/sysbuild/images/firmware_loader/Kconfig b/share/sysbuild/images/firmware_loader/Kconfig
new file mode 100644
index 00000000000..a5c4283ad5c
--- /dev/null
+++ b/share/sysbuild/images/firmware_loader/Kconfig
@@ -0,0 +1,37 @@
+# Copyright (c) 2025 Nordic Semiconductor
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SUPPORT_FIRMWARE_LOADER_SMP_SVR
+	bool
+	default y
+
+choice FIRMWARE_LOADER
+	prompt "Firmware loader image"
+	default FIRMWARE_LOADER_IMAGE_NONE
+	depends on MCUBOOT_MODE_FIRMWARE_UPDATER
+
+config FIRMWARE_LOADER_IMAGE_NONE
+	bool "None"
+	help
+	  Do not Include a firmware loader image in the build.
+
+config FIRMWARE_LOADER_IMAGE_SMP_SVR
+	bool "smp_svr"
+	depends on SUPPORT_FIRMWARE_LOADER_SMP_SVR
+	help
+	  Include the MCUmgr ``smp_svr`` sample as the firmware loader image to use.
+
+endchoice
+
+config FIRMWARE_LOADER_IMAGE_NAME
+	string
+	default "smp_svr" if FIRMWARE_LOADER_IMAGE_SMP_SVR
+	help
+	  Name of firmware loader image.
+
+config FIRMWARE_LOADER_IMAGE_PATH
+	string
+	default "${ZEPHYR_BASE}/samples/subsys/mgmt/mcumgr/smp_svr" if FIRMWARE_LOADER_IMAGE_SMP_SVR
+	help
+	  Source directory of firmware loader image.
diff --git a/snippets/nordic-flpr/snippet.yml b/snippets/nordic-flpr/snippet.yml
index de84bffd093..e6f6a41e252 100644
--- a/snippets/nordic-flpr/snippet.yml
+++ b/snippets/nordic-flpr/snippet.yml
@@ -9,9 +9,9 @@ boards:
   /.*/nrf54h20/cpuapp/:
     append:
       EXTRA_DTC_OVERLAY_FILE: soc/nrf54h20_cpuapp.overlay
-  /.*/nrf54l20/cpuapp/:
-    append:
-      EXTRA_DTC_OVERLAY_FILE: soc/nrf54l20_cpuapp.overlay
   /.*/nrf54l09/cpuapp/:
     append:
       EXTRA_DTC_OVERLAY_FILE: soc/nrf54l09_cpuapp.overlay
+  /.*/nrf54l20/cpuapp/:
+    append:
+      EXTRA_DTC_OVERLAY_FILE: soc/nrf54l20_cpuapp.overlay
diff --git a/snippets/usbip-native-sim/README.rst b/snippets/usbip-native-sim/README.rst
new file mode 100644
index 00000000000..c082445e190
--- /dev/null
+++ b/snippets/usbip-native-sim/README.rst
@@ -0,0 +1,17 @@
+.. _snippet-usbip-native-sim:
+
+USB/IP on Native Simulator Snippet (usbip-native-sim)
+#####################################################
+
+.. code-block:: console
+
+   west build -S usbip-native-sim [...]
+
+Overview
+********
+
+This snippet allows to configure USB device samples with USB/IP support on a
+native simulator. When building samples with this snippet, you need to provide
+samples DTC overlays using the EXTRA_DTC_OVERLAY_FILE argument.
+
+This snippet is experimental, the behavior may change without notice.
diff --git a/snippets/usbip-native-sim/snippet.yml b/snippets/usbip-native-sim/snippet.yml
new file mode 100644
index 00000000000..794930c0596
--- /dev/null
+++ b/snippets/usbip-native-sim/snippet.yml
@@ -0,0 +1,4 @@
+name: usbip-native-sim
+append:
+  EXTRA_CONF_FILE: usbip-native-sim.conf
+  EXTRA_DTC_OVERLAY_FILE: usbip-native-sim.overlay
diff --git a/snippets/usbip-native-sim/usbip-native-sim.conf b/snippets/usbip-native-sim/usbip-native-sim.conf
new file mode 100644
index 00000000000..74bad457277
--- /dev/null
+++ b/snippets/usbip-native-sim/usbip-native-sim.conf
@@ -0,0 +1,21 @@
+CONFIG_NETWORKING=y
+CONFIG_NET_IPV4=y
+CONFIG_NET_TCP=y
+CONFIG_NET_SOCKETS=y
+
+# Network address config
+CONFIG_NET_CONFIG_SETTINGS=y
+CONFIG_NET_CONFIG_NEED_IPV4=y
+CONFIG_NET_CONFIG_MY_IPV4_ADDR="192.0.2.1"
+CONFIG_NET_CONFIG_PEER_IPV4_ADDR="192.0.2.2"
+
+CONFIG_NET_LOG=y
+
+CONFIG_USB_HOST_STACK=y
+CONFIG_USBH_LOG_LEVEL_WRN=y
+CONFIG_UHC_DRIVER_LOG_LEVEL_WRN=y
+CONFIG_USBIP=y
+CONFIG_USBIP_LOG_LEVEL_WRN=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000000
+CONFIG_UHC_BUF_COUNT=32
+CONFIG_UHC_XFER_COUNT=32
diff --git a/snippets/usbip-native-sim/usbip-native-sim.overlay b/snippets/usbip-native-sim/usbip-native-sim.overlay
new file mode 100644
index 00000000000..d206391f3cd
--- /dev/null
+++ b/snippets/usbip-native-sim/usbip-native-sim.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &zephyr_udc0;
+
+/ {
+	zephyr_uhc0: uhc_vrt0 {
+		compatible = "zephyr,uhc-virtual";
+
+		zephyr_udc0: udc_vrt0 {
+			compatible = "zephyr,udc-virtual";
+			num-bidir-endpoints = <8>;
+			maximum-speed = "high-speed";
+		};
+	};
+};
diff --git a/snippets/wifi-ip/README.rst b/snippets/wifi-ip/README.rst
new file mode 100644
index 00000000000..b9d6808ce85
--- /dev/null
+++ b/snippets/wifi-ip/README.rst
@@ -0,0 +1,28 @@
+.. _snippet-wifi-ip:
+
+Wi-Fi IPv4 and IPv6 Snippet (wifi-ip)
+#####################################
+
+.. code-block:: console
+
+   west build -S wifi-ip [...]
+
+Overview
+********
+
+This snippet enables IPv4 and IPv6 Wi-Fi support in supported networking samples.
+The sample execution is postponed until Wi-Fi connectivity is established.
+
+Use Wi-Fi shell to connect to the Wi-Fi network:
+
+.. code-block:: console
+
+   wifi connect -s <SSID> -k <key_management> -p <passphrase>
+
+Requirements
+************
+
+Hardware support for:
+
+- :kconfig:option:`CONFIG_WIFI`
+- :kconfig:option:`CONFIG_WIFI_USE_NATIVE_NETWORKING`
diff --git a/snippets/wifi-ip/snippet.yml b/snippets/wifi-ip/snippet.yml
new file mode 100644
index 00000000000..0c4b0759b60
--- /dev/null
+++ b/snippets/wifi-ip/snippet.yml
@@ -0,0 +1,3 @@
+name: wifi-ip
+append:
+  EXTRA_CONF_FILE: wifi-ip.conf
diff --git a/snippets/wifi-ip/wifi-ip.conf b/snippets/wifi-ip/wifi-ip.conf
new file mode 100644
index 00000000000..788715d59b7
--- /dev/null
+++ b/snippets/wifi-ip/wifi-ip.conf
@@ -0,0 +1,32 @@
+# Wi-Fi
+CONFIG_WIFI=y
+CONFIG_NET_L2_ETHERNET=y
+CONFIG_WIFI_NM_WPA_SUPPLICANT=y
+
+# Make sure there is enough resources for supplicant and most of the samples
+CONFIG_MAIN_STACK_SIZE=2048
+CONFIG_ZVFS_OPEN_MAX=24
+CONFIG_NET_MAX_CONN=10
+CONFIG_ZVFS_POLL_MAX=10
+
+# Enable both IPv4 and IPv6
+CONFIG_NET_IPV6=y
+CONFIG_NET_IPV4=y
+
+# DHCPv4 and DHCPv6 are enabled
+CONFIG_NET_DHCPV4=y
+CONFIG_NET_DHCPV6=y
+CONFIG_NET_CONFIG_MY_IPV4_ADDR=""
+CONFIG_NET_CONFIG_MY_IPV6_ADDR=""
+CONFIG_NET_CONFIG_INIT_TIMEOUT=0
+
+# DNS
+CONFIG_DNS_RESOLVER=y
+
+# Connection manager
+CONFIG_NET_CONNECTION_MANAGER=y
+
+# Wi-Fi shell
+CONFIG_NET_SHELL=y
+CONFIG_NET_L2_WIFI_SHELL=y
+CONFIG_SHELL_STACK_SIZE=5200
diff --git a/snippets/wifi-ipv6/README.rst b/snippets/wifi-ipv6/README.rst
new file mode 100644
index 00000000000..1675c493c63
--- /dev/null
+++ b/snippets/wifi-ipv6/README.rst
@@ -0,0 +1,28 @@
+.. _snippet-wifi-ipv6:
+
+Wi-Fi IPv6 Snippet (wifi-ipv6)
+##############################
+
+.. code-block:: console
+
+   west build -S wifi-ipv6 [...]
+
+Overview
+********
+
+This snippet enables IPv6 Wi-Fi support in supported networking samples.
+The sample execution is postponed until Wi-Fi connectivity is established.
+
+Use Wi-Fi shell to connect to the Wi-Fi network:
+
+.. code-block:: console
+
+   wifi connect -s <SSID> -k <key_management> -p <passphrase>
+
+Requirements
+************
+
+Hardware support for:
+
+- :kconfig:option:`CONFIG_WIFI`
+- :kconfig:option:`CONFIG_WIFI_USE_NATIVE_NETWORKING`
diff --git a/snippets/wifi-ipv6/snippet.yml b/snippets/wifi-ipv6/snippet.yml
new file mode 100644
index 00000000000..88983250c94
--- /dev/null
+++ b/snippets/wifi-ipv6/snippet.yml
@@ -0,0 +1,3 @@
+name: wifi-ipv6
+append:
+  EXTRA_CONF_FILE: wifi-ipv6.conf
diff --git a/snippets/wifi-ipv6/wifi-ipv6.conf b/snippets/wifi-ipv6/wifi-ipv6.conf
new file mode 100644
index 00000000000..f4ea1214ece
--- /dev/null
+++ b/snippets/wifi-ipv6/wifi-ipv6.conf
@@ -0,0 +1,31 @@
+# Wi-Fi
+CONFIG_WIFI=y
+CONFIG_NET_L2_ETHERNET=y
+CONFIG_WIFI_NM_WPA_SUPPLICANT=y
+
+# Make sure there is enough resources for supplicant and most of the samples
+CONFIG_MAIN_STACK_SIZE=2048
+CONFIG_ZVFS_OPEN_MAX=24
+CONFIG_NET_MAX_CONN=10
+CONFIG_ZVFS_POLL_MAX=10
+
+# IPv6 only for now
+CONFIG_NET_IPV6=y
+CONFIG_NET_CONFIG_NEED_IPV4=n
+CONFIG_NET_IPV4=n
+
+# DHCPv6
+CONFIG_NET_DHCPV6=y
+CONFIG_NET_CONFIG_MY_IPV6_ADDR=""
+CONFIG_NET_CONFIG_INIT_TIMEOUT=0
+
+# DNS
+CONFIG_DNS_RESOLVER=y
+
+# Connection manager
+CONFIG_NET_CONNECTION_MANAGER=y
+
+# Wi-Fi shell
+CONFIG_NET_SHELL=y
+CONFIG_NET_L2_WIFI_SHELL=y
+CONFIG_SHELL_STACK_SIZE=5200
diff --git a/soc/CMakeLists.txt b/soc/CMakeLists.txt
index 7cd3f1af754..5240a3332ca 100644
--- a/soc/CMakeLists.txt
+++ b/soc/CMakeLists.txt
@@ -11,48 +11,30 @@ unset(_SOC_IS_IN_TREE)
 
 add_subdirectory(common)
 
-if(HWMv1)
-  message(DEPRECATION "
-          ---------------------------------------------------------------------
-          --- WARNING: Functionality to describe SoCs in HWMv1 is           ---
-          --- deprecated and should be replaced with HWMv2, including       ---
-          --- boards. HWMv1 SoCs support remains only to ease the migration ---
-          --- of out-of-tree SoCs and associated boards. It will not be     ---
-          --- possible to build using HWMv1 SoCs at all in future releases. ---
-          ---------------------------------------------------------------------"
-         )
+# Below is inclusion of HWMv2 SoC CMake lists.
+string(TOUPPER SOC_FAMILY_${SOC_FAMILY}_DIR family_setting_dir)
+string(TOUPPER SOC_SERIES_${SOC_SERIES}_DIR series_setting_dir)
+string(TOUPPER SOC_${SOC_NAME}_DIR soc_setting_dir)
 
-  if(EXISTS ${SOC_DIR}/${ARCH}/CMakeLists.txt)
-    add_subdirectory(${SOC_DIR}/${ARCH} soc/${ARCH})
-  else()
-    add_subdirectory(${SOC_DIR}/${ARCH}/${SOC_PATH} soc/${ARCH}/${SOC_PATH})
-  endif()
-elseif(HWMv2)
-  # Below is inclusion of HWMv2 SoC CMake lists.
-  string(TOUPPER SOC_FAMILY_${SOC_FAMILY}_DIR family_setting_dir)
-  string(TOUPPER SOC_SERIES_${SOC_SERIES}_DIR series_setting_dir)
-  string(TOUPPER SOC_${SOC_NAME}_DIR soc_setting_dir)
+if(DEFINED ${soc_setting_dir})
+  add_subdirectory(${${soc_setting_dir}} soc/${SOC_NAME})
+elseif(DEFINED ${series_setting_dir})
+  add_subdirectory(${${series_setting_dir}} soc/${SOC_SERIES})
+elseif(DEFINED ${family_setting_dir})
+  add_subdirectory(${${family_setting_dir}} soc/${SOC_FAMILY})
+else()
+  message(FATAL_ERROR "No CMakeLists.txt file found for SoC: ${SOC_NAME}, "
+                      "series: ${SOC_SERIES}, family: ${SOC_FAMILY}")
+endif()
 
-  if(DEFINED ${soc_setting_dir})
-    add_subdirectory(${${soc_setting_dir}} soc/${SOC_NAME})
-  elseif(DEFINED ${series_setting_dir})
-    add_subdirectory(${${series_setting_dir}} soc/${SOC_SERIES})
-  elseif(DEFINED ${family_setting_dir})
-    add_subdirectory(${${family_setting_dir}} soc/${SOC_FAMILY})
-  else()
-    message(FATAL_ERROR "No CMakeLists.txt file found for SoC: ${SOC_NAME}, "
-                        "series: ${SOC_SERIES}, family: ${SOC_FAMILY}")
+# Include all SoC roots except Zephyr, as we are already in the Zephyr SoC root.
+set(local_soc_root ${SOC_ROOT})
+list(REMOVE_ITEM local_soc_root ${ZEPHYR_BASE})
+foreach(root ${local_soc_root})
+  cmake_path(GET root FILENAME name)
+  # A SoC root for HWMv1 may not contain a CMakeLists.txt file on this so
+  # let's check for existence before including.
+  if(EXISTS ${root}/soc/CMakeLists.txt)
+    add_subdirectory(${root}/soc soc/${name})
   endif()
-
-  # Include all SoC roots except Zephyr, as we are already in the Zephyr SoC root.
-  set(local_soc_root ${SOC_ROOT})
-  list(REMOVE_ITEM local_soc_root ${ZEPHYR_BASE})
-  foreach(root ${local_soc_root})
-    cmake_path(GET root FILENAME name)
-    # A SoC root for HWMv1 may not contain a CMakeLists.txt file on this so
-    # let's check for existence before including.
-    if(EXISTS ${root}/soc/CMakeLists.txt)
-      add_subdirectory(${root}/soc soc/${name})
-    endif()
-  endforeach()
-endif()
+endforeach()
diff --git a/soc/Kconfig b/soc/Kconfig
index af32c5c5cf3..a1ea1f97896 100644
--- a/soc/Kconfig
+++ b/soc/Kconfig
@@ -3,11 +3,9 @@
 # Only v1 model has choice for SoC selection, therefore the optional source
 # Sourced here and not in Kconfig.v1 to keep current SoC/CPU selection menu
 # side-by-side with "Hardware Configuration" in the menu structure.
-orsource "Kconfig.$(HWM_SCHEME).choice"
-
 menu "Hardware Configuration"
 
-rsource "Kconfig.$(HWM_SCHEME)"
+rsource "Kconfig.v2"
 
 # Source Zephyr Kconfig specifics from SoC roots.
 osource "$(KCONFIG_BINARY_DIR)/soc/Kconfig"
diff --git a/soc/Kconfig.v1 b/soc/Kconfig.v1
deleted file mode 100644
index bd7f66d77bc..00000000000
--- a/soc/Kconfig.v1
+++ /dev/null
@@ -1,25 +0,0 @@
-# Copyright (c) 2023 Nordic Semiconductor ASA
-
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC
-	string
-	help
-	  SoC name. The value of this setting must be defined by the selected
-	  SoC for hw model v2.
-
-config SOC_SERIES
-	string
-	help
-	  SoC series. The value of this setting must be defined by the selected
-	  SoC if the SoC belongs to a common series.
-
-config SOC_FAMILY
-	string
-	help
-	  SoC family. The value of this setting must be defined by the selected
-	  SoC if the SoC belongs to a SoC family. Usually a SoC family also
-	  indicates the vendor of the SoC.
-
-# This loads custom SoC root Kconfig (only available if custom SoC root are defined)
-osource "$(KCONFIG_BINARY_DIR)/soc/Kconfig.soc.arch"
diff --git a/soc/Kconfig.v1.choice b/soc/Kconfig.v1.choice
deleted file mode 100644
index e96dd15bedd..00000000000
--- a/soc/Kconfig.v1.choice
+++ /dev/null
@@ -1,11 +0,0 @@
-# Copyright (c) 2023 Nordic Semiconductor ASA
-
-# SPDX-License-Identifier: Apache-2.0
-
-choice
-	prompt "SoC/CPU/Configuration Selection"
-
-# This loads custom SoC root Kconfig (only available if custom SoC root are defined)
-osource "$(KCONFIG_BINARY_DIR)/soc/Kconfig.soc.choice"
-
-endchoice
diff --git a/soc/adi/max32/CMakeLists.txt b/soc/adi/max32/CMakeLists.txt
index 41041da7e08..b398dcd8d8f 100644
--- a/soc/adi/max32/CMakeLists.txt
+++ b/soc/adi/max32/CMakeLists.txt
@@ -1,4 +1,4 @@
-# Copyright (c) 2023-2024 Analog Devices, Inc.
+# Copyright (c) 2023-2025 Analog Devices, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_include_directories(${ZEPHYR_BASE}/drivers)
@@ -6,6 +6,8 @@ zephyr_include_directories(common)
 zephyr_sources(soc.c)
 
 zephyr_linker_sources_ifdef(CONFIG_SOC_FLASH_MAX32 SECTIONS flash.ld)
-zephyr_linker_sources_ifdef(CONFIG_SOC_MAX78002 SECTIONS max78002.ld)
+if(CONFIG_SOC_MAX78000 OR CONFIG_SOC_MAX78002)
+  zephyr_linker_sources(SECTIONS max7800x.ld)
+endif()
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/adi/max32/Kconfig b/soc/adi/max32/Kconfig
index b2bdc351518..2bddfc6e556 100644
--- a/soc/adi/max32/Kconfig
+++ b/soc/adi/max32/Kconfig
@@ -1,44 +1,35 @@
 # Analog Devices MAX32xxx MCU family
 
-# Copyright (c) 2023-2024 Analog Devices, Inc.
+# Copyright (c) 2023-2025 Analog Devices, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_FAMILY_MAX32
-	select ARM
-	select CPU_HAS_ARM_MPU
-	select CPU_HAS_FPU
-	select CPU_CORTEX_M_HAS_SYSTICK
 	select CLOCK_CONTROL
 	select BUILD_OUTPUT_HEX
 	select SOC_EARLY_INIT_HOOK
 	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
 
-config SOC_MAX32655
-	select CPU_CORTEX_M4
-
-config SOC_MAX32662
-	select CPU_CORTEX_M4
-
-config SOC_MAX32666
-	select CPU_CORTEX_M4
-
-config SOC_MAX32670
+config SOC_FAMILY_MAX32_M4
+	select ARM
 	select CPU_CORTEX_M4
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
 
-config SOC_MAX32672
-	select CPU_CORTEX_M4
+config SOC_MAX32655_M4
+	select MAX32_HAS_SECONDARY_RV32
 
-config SOC_MAX32675
-	select CPU_CORTEX_M4
+config SOC_MAX32680_M4
+	select MAX32_HAS_SECONDARY_RV32
 
-config SOC_MAX32680
-	select CPU_CORTEX_M4
+config SOC_MAX32690_M4
+	select MAX32_HAS_SECONDARY_RV32
 
-config SOC_MAX32690
-	select CPU_CORTEX_M4
+config SOC_MAX78000_M4
+	select MAX32_HAS_SECONDARY_RV32
 
 config SOC_MAX78002_M4
-	select CPU_CORTEX_M4
+	select MAX32_HAS_SECONDARY_RV32
 
 if SOC_FAMILY_MAX32
 
@@ -52,4 +43,18 @@ config MAX32_ON_ENTER_CPU_IDLE_HOOK
 	  If needed, this hook can be used to prevent the CPU from actually
 	  entering sleep by skipping the WFE/WFI instruction.
 
+config MAX32_HAS_SECONDARY_RV32
+	bool
+
+config MAX32_SECONDARY_RV32
+	bool "Secondary RISC-V core enable"
+	depends on MAX32_HAS_SECONDARY_RV32
+
+DT_CHOSEN_Z_CODE_RV32_PARTITION := zephyr,code-rv32-partition
+
+config MAX32_SECONDARY_RV32_BOOT_ADDRESS
+	hex "Secondary RISC-V core boot address"
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_RV32_PARTITION))
+	depends on MAX32_SECONDARY_RV32
+
 endif # SOC_FAMILY_MAX32
diff --git a/soc/adi/max32/Kconfig.defconfig b/soc/adi/max32/Kconfig.defconfig
index 5a5fd567fc8..5b3e7d1e519 100644
--- a/soc/adi/max32/Kconfig.defconfig
+++ b/soc/adi/max32/Kconfig.defconfig
@@ -7,7 +7,4 @@ if SOC_FAMILY_MAX32
 
 rsource "Kconfig.defconfig.max*"
 
-config SRAM_VECTOR_TABLE
-	default y
-
 endif # SOC_FAMILY_MAX32
diff --git a/soc/adi/max32/Kconfig.defconfig.max32650 b/soc/adi/max32/Kconfig.defconfig.max32650
new file mode 100644
index 00000000000..9c8608b1b77
--- /dev/null
+++ b/soc/adi/max32/Kconfig.defconfig.max32650
@@ -0,0 +1,14 @@
+# Analog Devices MAX32650 MCU
+
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MAX32650
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
+
+config NUM_IRQS
+	default 80
+
+endif # SOC_MAX32650
diff --git a/soc/adi/max32/Kconfig.defconfig.max32660 b/soc/adi/max32/Kconfig.defconfig.max32660
new file mode 100644
index 00000000000..29848d44d1d
--- /dev/null
+++ b/soc/adi/max32/Kconfig.defconfig.max32660
@@ -0,0 +1,14 @@
+# Analog Devices MAX32660 MCU
+
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MAX32660
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
+
+config NUM_IRQS
+	default 55
+
+endif # SOC_MAX32660
diff --git a/soc/adi/max32/Kconfig.defconfig.max78000 b/soc/adi/max32/Kconfig.defconfig.max78000
new file mode 100644
index 00000000000..8643911a766
--- /dev/null
+++ b/soc/adi/max32/Kconfig.defconfig.max78000
@@ -0,0 +1,14 @@
+# Analog Devices MAX78000 MCU
+
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MAX78000
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
+
+config NUM_IRQS
+	default 119
+
+endif # SOC_MAX78000
diff --git a/soc/adi/max32/Kconfig.soc b/soc/adi/max32/Kconfig.soc
index 130d9b88b1f..e0be0041b4b 100644
--- a/soc/adi/max32/Kconfig.soc
+++ b/soc/adi/max32/Kconfig.soc
@@ -1,72 +1,94 @@
 # Analog Devices MAX32xxx MCU family
 
-# Copyright (c) 2023-2024 Analog Devices, Inc.
+# Copyright (c) 2023-2025 Analog Devices, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_FAMILY_MAX32
 	bool
 
+config SOC_FAMILY_MAX32_M4
+	bool
+	select SOC_FAMILY_MAX32
+
 config SOC_FAMILY
 	default "max32" if SOC_FAMILY_MAX32
 
+config SOC_MAX32650
+	bool
+	select SOC_FAMILY_MAX32_M4
+
 config SOC_MAX32655
 	bool
-	select SOC_FAMILY_MAX32
 
 config SOC_MAX32655_M4
 	bool
 	select SOC_MAX32655
+	select SOC_FAMILY_MAX32_M4
+
+config SOC_MAX32660
+	bool
+	select SOC_FAMILY_MAX32_M4
 
 config SOC_MAX32662
 	bool
-	select SOC_FAMILY_MAX32
+	select SOC_FAMILY_MAX32_M4
 
 config SOC_MAX32666
 	bool
-	select SOC_FAMILY_MAX32
 
 config SOC_MAX32666_CPU0
 	bool
 	select SOC_MAX32666
+	select SOC_FAMILY_MAX32_M4
 
 config SOC_MAX32670
 	bool
-	select SOC_FAMILY_MAX32
+	select SOC_FAMILY_MAX32_M4
 
 config SOC_MAX32672
 	bool
-	select SOC_FAMILY_MAX32
+	select SOC_FAMILY_MAX32_M4
 
 config SOC_MAX32675
 	bool
-	select SOC_FAMILY_MAX32
+	select SOC_FAMILY_MAX32_M4
 
 config SOC_MAX32680
 	bool
-	select SOC_FAMILY_MAX32
 
 config SOC_MAX32680_M4
 	bool
 	select SOC_MAX32680
+	select SOC_FAMILY_MAX32_M4
 
 config SOC_MAX32690
 	bool
-	select SOC_FAMILY_MAX32
 
 config SOC_MAX32690_M4
 	bool
 	select SOC_MAX32690
+	select SOC_FAMILY_MAX32_M4
+
+config SOC_MAX78000
+	bool
+
+config SOC_MAX78000_M4
+	bool
+	select SOC_MAX78000
+	select SOC_FAMILY_MAX32_M4
 
 config SOC_MAX78002
 	bool
-	select SOC_FAMILY_MAX32
 
 config SOC_MAX78002_M4
 	bool
 	select SOC_MAX78002
+	select SOC_FAMILY_MAX32_M4
 
 config SOC
+	default "max32650" if SOC_MAX32650
 	default "max32655" if SOC_MAX32655
+	default "max32660" if SOC_MAX32660
 	default "max32662" if SOC_MAX32662
 	default "max32666" if SOC_MAX32666
 	default "max32670" if SOC_MAX32670
@@ -74,4 +96,5 @@ config SOC
 	default "max32675" if SOC_MAX32675
 	default "max32680" if SOC_MAX32680
 	default "max32690" if SOC_MAX32690
+	default "max78000" if SOC_MAX78000
 	default "max78002" if SOC_MAX78002
diff --git a/soc/adi/max32/max78002.ld b/soc/adi/max32/max7800x.ld
similarity index 100%
rename from soc/adi/max32/max78002.ld
rename to soc/adi/max32/max7800x.ld
diff --git a/soc/adi/max32/soc.c b/soc/adi/max32/soc.c
index c509e8e5cf3..fc24e6e1d82 100644
--- a/soc/adi/max32/soc.c
+++ b/soc/adi/max32/soc.c
@@ -14,6 +14,10 @@
 
 #include <wrap_max32_sys.h>
 
+#ifdef CONFIG_MAX32_SECONDARY_RV32
+#include <fcr_regs.h>
+#endif
+
 #if defined(CONFIG_MAX32_ON_ENTER_CPU_IDLE_HOOK)
 bool z_arm_on_enter_cpu_idle(void)
 {
@@ -31,4 +35,10 @@ void soc_early_init_hook(void)
 {
 	/* Apply device related preinit configuration */
 	max32xx_system_init();
+
+#ifdef CONFIG_MAX32_SECONDARY_RV32
+	MXC_FCR->urvbootaddr = CONFIG_MAX32_SECONDARY_RV32_BOOT_ADDRESS;
+	MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CPU1);
+	MXC_GCR->rst1 |= MXC_F_GCR_RST1_CPU1;
+#endif /* CONFIG_MAX32_SECONDARY_RV32 */
 }
diff --git a/soc/adi/max32/soc.yml b/soc/adi/max32/soc.yml
index 3f164890071..3bf7288d120 100644
--- a/soc/adi/max32/soc.yml
+++ b/soc/adi/max32/soc.yml
@@ -1,12 +1,14 @@
-# Copyright (c) 2023-2024 Analog Devices, Inc.
+# Copyright (c) 2023-2025 Analog Devices, Inc.
 # SPDX-License-Identifier: Apache-2.0
 
 family:
 - name: max32
   socs:
+  - name: max32650
   - name: max32655
     cpuclusters:
     - name: m4
+  - name: max32660
   - name: max32662
   - name: max32666
     cpuclusters:
@@ -20,6 +22,9 @@ family:
   - name: max32690
     cpuclusters:
     - name: m4
+  - name: max78000
+    cpuclusters:
+    - name: m4
   - name: max78002
     cpuclusters:
     - name: m4
diff --git a/soc/ambiq/CMakeLists.txt b/soc/ambiq/CMakeLists.txt
index 7afff4e7ec8..a4e7a49cec9 100644
--- a/soc/ambiq/CMakeLists.txt
+++ b/soc/ambiq/CMakeLists.txt
@@ -5,3 +5,15 @@
 add_subdirectory(${SOC_SERIES})
 
 zephyr_include_directories(.)
+
+if(CONFIG_SOC_AMBIQ_BT_SUPPORTED)
+  if(CONFIG_SOC_APOLLO4P)
+    if(CONFIG_AMBIQ_COMPONENT_USE_BT)
+      message(FATAL_ERROR "AMBIQ_COMPONENT_USE_BT is set to ${CONFIG_AMBIQ_COMPONENT_USE_BT} \
+for not supported SoC ${CONFIG_SOC}")
+    else()
+      message(WARNING "SOC_AMBIQ_BT_SUPPORTED is set to ${CONFIG_SOC_AMBIQ_BT_SUPPORTED} \
+for not supported SoC ${CONFIG_SOC}")
+    endif()
+  endif()
+endif()
diff --git a/soc/ambiq/Kconfig.soc b/soc/ambiq/Kconfig.soc
index ba6d5302abb..05104f833ba 100644
--- a/soc/ambiq/Kconfig.soc
+++ b/soc/ambiq/Kconfig.soc
@@ -8,4 +8,7 @@ config SOC_FAMILY_AMBIQ
 config SOC_FAMILY
 	default "ambiq" if SOC_FAMILY_AMBIQ
 
+config SOC_AMBIQ_BT_SUPPORTED
+	bool
+
 rsource "*/Kconfig.soc"
diff --git a/soc/ambiq/apollo3x/Kconfig.soc b/soc/ambiq/apollo3x/Kconfig.soc
index 6a681417993..d4990b385e0 100644
--- a/soc/ambiq/apollo3x/Kconfig.soc
+++ b/soc/ambiq/apollo3x/Kconfig.soc
@@ -11,12 +11,14 @@ config SOC_SERIES_APOLLO3X
 config SOC_APOLLO3P_BLUE
 	bool
 	select SOC_SERIES_APOLLO3X
+	select SOC_AMBIQ_BT_SUPPORTED
 	help
 	  Apollo3P Blue
 
 config SOC_APOLLO3_BLUE
 	bool
 	select SOC_SERIES_APOLLO3X
+	select SOC_AMBIQ_BT_SUPPORTED
 	help
 	  Apollo3 Blue
 
diff --git a/soc/ambiq/apollo3x/pinctrl_soc.h b/soc/ambiq/apollo3x/pinctrl_soc.h
index 1aa6a32d81f..f3f562ae802 100644
--- a/soc/ambiq/apollo3x/pinctrl_soc.h
+++ b/soc/ambiq/apollo3x/pinctrl_soc.h
@@ -33,12 +33,14 @@ struct apollo3_pinctrl_soc_pin {
 	uint32_t bias_pull_down: 1;
 	/** pullup resistor value */
 	uint32_t ambiq_pull_up_ohms: 3;
-	/** IOM nCE module select */
-	uint32_t iom_nce: 2;
+	/** nCE module select */
+	uint32_t nce: 2;
 	/** IOM or MSPI */
 	uint32_t iom_mspi: 1;
 	/** IOM/MSPI instance number */
 	uint32_t iom_num: 3;
+	/** nCE module polarity */
+	uint32_t nce_pol: 1;
 };
 
 typedef struct apollo3_pinctrl_soc_pin pinctrl_soc_pin_t;
@@ -62,9 +64,10 @@ typedef struct apollo3_pinctrl_soc_pin pinctrl_soc_pin_t;
 		DT_PROP(node_id, bias_pull_up),                                                    \
 		DT_PROP(node_id, bias_pull_down),                                                  \
 		DT_ENUM_IDX(node_id, ambiq_pull_up_ohms),                                          \
-		DT_PROP(node_id, ambiq_iom_nce_module),                                            \
+		DT_PROP(node_id, ambiq_nce_src),                                                   \
 		DT_PROP(node_id, ambiq_iom_mspi),                                                  \
 		DT_PROP(node_id, ambiq_iom_num),                                                   \
+		DT_PROP(node_id, ambiq_nce_pol),                                                   \
 	},
 
 /**
diff --git a/soc/ambiq/apollo3x/power.c b/soc/ambiq/apollo3x/power.c
index d41dd20c996..e33d2197550 100644
--- a/soc/ambiq/apollo3x/power.c
+++ b/soc/ambiq/apollo3x/power.c
@@ -12,9 +12,6 @@
 #include <zephyr/pm/pm.h>
 #include <zephyr/init.h>
 
-/* ambiq-sdk includes */
-#include <am_mcu_apollo.h>
-
 LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
 
 void pm_state_set(enum pm_state state, uint8_t substate_id)
diff --git a/soc/ambiq/apollo3x/soc.c b/soc/ambiq/apollo3x/soc.c
index 33bf6568d37..557597f7206 100644
--- a/soc/ambiq/apollo3x/soc.c
+++ b/soc/ambiq/apollo3x/soc.c
@@ -5,8 +5,10 @@
  */
 
 #include <zephyr/init.h>
+#include <zephyr/logging/log.h>
+#include <soc.h>
 
-#include <am_mcu_apollo.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
 
 extern void ambiq_power_init(void);
 
diff --git a/soc/ambiq/apollo3x/soc.h b/soc/ambiq/apollo3x/soc.h
index ae9b7e597df..1489a277e24 100644
--- a/soc/ambiq/apollo3x/soc.h
+++ b/soc/ambiq/apollo3x/soc.h
@@ -7,10 +7,6 @@
 #ifndef __SOC_H__
 #define __SOC_H__
 
-#if defined(CONFIG_SOC_APOLLO3P_BLUE)
-#include <apollo3p.h>
-#elif defined(CONFIG_SOC_APOLLO3_BLUE)
-#include <apollo3.h>
-#endif
+#include <am_mcu_apollo.h>
 
 #endif /* __SOC_H__ */
diff --git a/soc/ambiq/apollo4x/Kconfig.soc b/soc/ambiq/apollo4x/Kconfig.soc
index fe06f28a7a8..b0b6e7c30c4 100644
--- a/soc/ambiq/apollo4x/Kconfig.soc
+++ b/soc/ambiq/apollo4x/Kconfig.soc
@@ -18,6 +18,7 @@ config SOC_APOLLO4P
 config SOC_APOLLO4P_BLUE
 	bool
 	select SOC_SERIES_APOLLO4X
+	select SOC_AMBIQ_BT_SUPPORTED
 	help
 	  Apollo4 Blue Plus
 
diff --git a/soc/ambiq/apollo4x/pinctrl_soc.h b/soc/ambiq/apollo4x/pinctrl_soc.h
index 869101ed2b5..34cc43ca863 100644
--- a/soc/ambiq/apollo4x/pinctrl_soc.h
+++ b/soc/ambiq/apollo4x/pinctrl_soc.h
@@ -35,10 +35,12 @@ struct apollo4_pinctrl_soc_pin {
 	uint32_t bias_pull_down : 1;
 	/** pullup resistor value */
 	uint32_t ambiq_pull_up_ohms : 3;
-	/** IOM nCE module select */
-	uint32_t iom_nce : 6;
-	/** IOM interrupt direction */
-	uint32_t interrupt_direction: 2;
+	/** nCE module select */
+	uint32_t nce : 6;
+	/** nCE module polarity */
+	uint32_t nce_pol: 1;
+	/** SDIF CD WP pad select */
+	uint32_t sdif_cdwp: 2;
 };
 
 typedef struct apollo4_pinctrl_soc_pin pinctrl_soc_pin_t;
@@ -63,8 +65,9 @@ typedef struct apollo4_pinctrl_soc_pin pinctrl_soc_pin_t;
 		DT_PROP(node_id, bias_pull_up),                                                    \
 		DT_PROP(node_id, bias_pull_down),                                                  \
 		DT_ENUM_IDX(node_id, ambiq_pull_up_ohms),                                          \
-		DT_PROP(node_id, ambiq_iom_nce_module),                                            \
-		DT_PROP(node_id, ambiq_interrupt_direction),                                       \
+		DT_PROP(node_id, ambiq_nce_src),                                                   \
+		DT_PROP(node_id, ambiq_nce_pol),                                                   \
+		DT_PROP(node_id, ambiq_sdif_cdwp),                                                 \
 	},
 
 /**
diff --git a/soc/ambiq/apollo4x/power.c b/soc/ambiq/apollo4x/power.c
index b799f29c224..87bff5b3d22 100644
--- a/soc/ambiq/apollo4x/power.c
+++ b/soc/ambiq/apollo4x/power.c
@@ -12,9 +12,6 @@
 #include <zephyr/pm/pm.h>
 #include <zephyr/init.h>
 
-/* ambiq-sdk includes */
-#include <am_mcu_apollo.h>
-
 LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
 
 void pm_state_set(enum pm_state state, uint8_t substate_id)
diff --git a/soc/ambiq/apollo4x/soc.c b/soc/ambiq/apollo4x/soc.c
index 5338a2e2f5f..54daff08fc1 100644
--- a/soc/ambiq/apollo4x/soc.c
+++ b/soc/ambiq/apollo4x/soc.c
@@ -5,8 +5,10 @@
  */
 
 #include <zephyr/init.h>
+#include <zephyr/logging/log.h>
+#include <soc.h>
 
-#include <am_mcu_apollo.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
 
 extern void ambiq_power_init(void);
 void soc_early_init_hook(void)
diff --git a/soc/ambiq/apollo4x/soc.h b/soc/ambiq/apollo4x/soc.h
index dfa86b20146..d9c79596d42 100644
--- a/soc/ambiq/apollo4x/soc.h
+++ b/soc/ambiq/apollo4x/soc.h
@@ -7,6 +7,6 @@
 #ifndef __SOC_H__
 #define __SOC_H__
 
-#include <apollo4p.h>
+#include <am_mcu_apollo.h>
 
 #endif /* __SOC_H__ */
diff --git a/soc/ambiq/apollo5x/CMakeLists.txt b/soc/ambiq/apollo5x/CMakeLists.txt
new file mode 100644
index 00000000000..f4af65d8794
--- /dev/null
+++ b/soc/ambiq/apollo5x/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Ambiq Micro Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_sources(soc.c)
+zephyr_include_directories(.)
+zephyr_sources_ifdef(CONFIG_PM power.c)
+zephyr_include_directories(${ZEPHYR_BASE}/soc/arm/common/cortex_m)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/ambiq/apollo5x/Kconfig b/soc/ambiq/apollo5x/Kconfig
new file mode 100644
index 00000000000..45bd4c8ae14
--- /dev/null
+++ b/soc/ambiq/apollo5x/Kconfig
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2025 Ambiq Micro Inc.
+
+config SOC_SERIES_APOLLO5X
+	select ARM
+	select CPU_CORTEX_M55
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_CORTEX_M_HAS_VTOR
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
+	select ARMV8_1_M_MVEI
+	select ARMV8_1_M_MVEF
+	select ARMV8_1_M_PMU
+	select HAS_SWO
+	select AMBIQ_HAL
+	select HAS_PM
+	select SOC_EARLY_INIT_HOOK
+	select REQUIRES_FULL_LIBC
diff --git a/soc/ambiq/apollo5x/Kconfig.defconfig b/soc/ambiq/apollo5x/Kconfig.defconfig
new file mode 100644
index 00000000000..5803b2ea240
--- /dev/null
+++ b/soc/ambiq/apollo5x/Kconfig.defconfig
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2025 Ambiq Micro Inc.
+
+if SOC_SERIES_APOLLO5X
+
+rsource "Kconfig.defconfig.apollo5*"
+
+config CACHE_MANAGEMENT
+	default y
+
+config AMBIQ_CACHEABLE_DMA_BUFFER_ALIGNMENT
+	int
+	default DCACHE_LINE_SIZE
+
+# Need to enlarge the IDLE stack size because the power
+# management operations are executed in the idle task
+config IDLE_STACK_SIZE
+	default 2048 if PM
+
+endif # SOC_SERIES_APOLLO5X
diff --git a/soc/ambiq/apollo5x/Kconfig.defconfig.apollo510 b/soc/ambiq/apollo5x/Kconfig.defconfig.apollo510
new file mode 100644
index 00000000000..09ac0c95c4a
--- /dev/null
+++ b/soc/ambiq/apollo5x/Kconfig.defconfig.apollo510
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2025 Ambiq Micro Inc.
+
+if SOC_APOLLO510
+
+config NUM_IRQS
+    default 134
+
+endif # SOC_APOLLO510
diff --git a/soc/ambiq/apollo5x/Kconfig.soc b/soc/ambiq/apollo5x/Kconfig.soc
new file mode 100644
index 00000000000..52d9fc8206f
--- /dev/null
+++ b/soc/ambiq/apollo5x/Kconfig.soc
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2025 Ambiq Micro Inc.
+
+config SOC_SERIES_APOLLO5X
+	bool
+	select SOC_FAMILY_AMBIQ
+	help
+	  Apollo5 Series MCU
+
+config SOC_APOLLO510
+    bool
+	select SOC_SERIES_APOLLO5X
+
+config ARMV8_1_M_PMU_EVENTCNT
+    int
+    default 8
+
+config SOC_SERIES
+	default "apollo5x" if SOC_SERIES_APOLLO5X
+
+config SOC
+	default "apollo510" if SOC_APOLLO510
diff --git a/soc/ambiq/apollo5x/pinctrl_soc.h b/soc/ambiq/apollo5x/pinctrl_soc.h
new file mode 100644
index 00000000000..1feb8d56e92
--- /dev/null
+++ b/soc/ambiq/apollo5x/pinctrl_soc.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2025 Ambiq Micro Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_ARM_AMBIQ_APOLLO5_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_ARM_AMBIQ_APOLLO5_PINCTRL_SOC_H_
+
+#include <zephyr/dt-bindings/pinctrl/ambiq-apollo5-pinctrl.h>
+
+/**
+ * @brief Type to hold a pin's pinctrl configuration.
+ */
+struct apollo5_pinctrl_soc_pin {
+	/** Pin number 0..223 */
+	uint64_t pin_num: 8;
+	/** Alternative function (UART, SPI, etc.) */
+	uint64_t alt_func: 4;
+	/** Enable the pin as an input */
+	uint64_t input_enable: 1;
+	/** Drive strength, relative to full-driver strength */
+	uint64_t drive_strength: 3;
+	/** Drive actively high or low */
+	uint64_t push_pull: 1;
+	/** Drive with open drain */
+	uint64_t open_drain: 1;
+	/** High impedance mode */
+	uint64_t tristate: 1;
+	/** Enable the internal pull up resistor */
+	uint64_t bias_pull_up: 1;
+	/** Enable the internal pull down resistor */
+	uint64_t bias_pull_down: 1;
+	/** pullup resistor value */
+	uint64_t ambiq_pull_up_ohms: 3;
+	/** nCE module select */
+	uint64_t nce: 6;
+	/** nCE module polarity */
+	uint64_t nce_pol: 1;
+	/** SDIF CD WP pad select */
+	uint64_t sdif_cdwp: 3;
+};
+
+typedef struct apollo5_pinctrl_soc_pin pinctrl_soc_pin_t;
+
+/**
+ * @brief Utility macro to initialize each pin.
+ *
+ * @param node_id Node identifier.
+ * @param prop Property name.
+ * @param idx Property entry index.
+ */
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx)                                       \
+	{                                                                                      \
+		APOLLO5_GET_PIN_NUM(DT_PROP_BY_IDX(node_id, prop, idx)),                           \
+		APOLLO5_GET_PIN_ALT_FUNC(DT_PROP_BY_IDX(node_id, prop, idx)),                      \
+		DT_PROP(node_id, input_enable),                                                    \
+		DT_ENUM_IDX(node_id, drive_strength),                                              \
+		DT_PROP(node_id, drive_push_pull),                                                 \
+		DT_PROP(node_id, drive_open_drain),                                                \
+		DT_PROP(node_id, bias_high_impedance),                                             \
+		DT_PROP(node_id, bias_pull_up),                                                    \
+		DT_PROP(node_id, bias_pull_down),                                                  \
+		DT_ENUM_IDX(node_id, ambiq_pull_up_ohms),                                          \
+		DT_PROP(node_id, ambiq_nce_src),                                                   \
+		DT_PROP(node_id, ambiq_nce_pol),                                                   \
+		DT_PROP(node_id, ambiq_sdif_cdwp),                                                 \
+	},
+
+/**
+ * @brief Utility macro to initialize state pins contained in a given property.
+ *
+ * @param node_id Node identifier.
+ * @param prop Property name describing state pins.
+ */
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)                                \
+        {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop),                      \
+                    DT_FOREACH_PROP_ELEM, pinmux,                               \
+                    Z_PINCTRL_STATE_PIN_INIT)}
+
+#define APOLLO5_GET_PIN_NUM(pinctrl)                                            \
+        (((pinctrl) >> APOLLO5_PIN_NUM_POS) & APOLLO5_PIN_NUM_MASK)
+#define APOLLO5_GET_PIN_ALT_FUNC(pinctrl)                                       \
+        (((pinctrl) >> APOLLO5_ALT_FUNC_POS) & APOLLO5_ALT_FUNC_MASK)
+
+
+#endif /* ZEPHYR_SOC_ARM_AMBIQ_APOLLO5_PINCTRL_SOC_H_ */
diff --git a/soc/ambiq/apollo5x/power.c b/soc/ambiq/apollo5x/power.c
new file mode 100644
index 00000000000..131afcb4997
--- /dev/null
+++ b/soc/ambiq/apollo5x/power.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2025 Ambiq LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc.h>
+
+#include <zephyr/drivers/interrupt_controller/gic.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/pm/pm.h>
+#include <zephyr/init.h>
+
+LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
+
+void pm_state_set(enum pm_state state, uint8_t substate_id)
+{
+	ARG_UNUSED(substate_id);
+
+	__disable_irq();
+	__set_BASEPRI(0);
+
+	switch (state) {
+	case PM_STATE_SUSPEND_TO_IDLE: {
+		/* Put ARM core to normal sleep. */
+		am_hal_sysctrl_sleep(AM_HAL_SYSCTRL_SLEEP_NORMAL);
+		break;
+	}
+	case PM_STATE_SUSPEND_TO_RAM: {
+		/* Put ARM core to deep sleep. */
+		/* Cotex-m: power down, register value preserve.*/
+		/* Cache: power down*/
+		/* MRAM: power down*/
+		/* ITCM + DTCM: retention, active on request*/
+		/* Sram: retention, active on request*/
+		am_hal_sysctrl_sleep(AM_HAL_SYSCTRL_SLEEP_DEEP);
+		break;
+	}
+	default: {
+		LOG_DBG("Unsupported power state %u", state);
+		break;
+	}
+	}
+}
+
+/**
+ * @brief PM State Exit Post Operations
+ *
+ * For PM_STATE_SUSPEND_TO_IDLE:
+ *   Nothing is needed after soc woken up.
+ *
+ * For PM_STATE_SUSPEND_TO_RAM:
+ *   Flash, cache, sram automatically switch
+ *   to active state on wake up
+ *
+ * @param state PM State
+ * @param substate_id Unused
+ *
+ */
+void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
+{
+	ARG_UNUSED(substate_id);
+
+	__enable_irq();
+	irq_unlock(0);
+}
diff --git a/soc/ambiq/apollo5x/soc.c b/soc/ambiq/apollo5x/soc.c
new file mode 100644
index 00000000000..1bad5a03c88
--- /dev/null
+++ b/soc/ambiq/apollo5x/soc.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2025 Ambiq Micro Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/init.h>
+#include <zephyr/cache.h>
+#include <zephyr/logging/log.h>
+#include "soc.h"
+
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#define SCRATCH0_OEM_RCV_RETRY_MAGIC 0xA86
+
+void soc_early_init_hook(void)
+{
+	/* Enable Loop and branch info cache */
+	SCB->CCR |= SCB_CCR_LOB_Msk;
+	__DSB();
+	__ISB();
+
+	if ((MCUCTRL->SCRATCH0 >> 20) == SCRATCH0_OEM_RCV_RETRY_MAGIC) {
+		/*
+		 * Clear the scratch register
+		 */
+		MCUCTRL->SCRATCH0 = 0x00;
+	}
+
+	/* Internal timer15 for SPOT manager */
+	IRQ_CONNECT(82, 0, hal_internal_timer_isr, 0, 0);
+
+	/* Initialize for low power in the power control block */
+	am_hal_pwrctrl_low_power_init();
+
+	/* Enable SIMOBUCK for the apollo5 Family */
+	am_hal_pwrctrl_control(AM_HAL_PWRCTRL_CONTROL_SIMOBUCK_INIT, NULL);
+
+	/*
+	 * Set default temperature for spotmgr to room temperature
+	 */
+	am_hal_pwrctrl_temp_thresh_t dummy[32];
+	am_hal_pwrctrl_temp_update(25.0f, dummy);
+
+	/* Enable Icache*/
+	sys_cache_instr_enable();
+
+	/* Enable Dcache */
+	sys_cache_data_enable();
+}
diff --git a/soc/ambiq/apollo5x/soc.h b/soc/ambiq/apollo5x/soc.h
new file mode 100644
index 00000000000..a41e87b5df2
--- /dev/null
+++ b/soc/ambiq/apollo5x/soc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Ambiq Micro Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __SOC_H__
+#define __SOC_H__
+
+#include <am_mcu_apollo.h>
+
+#endif /* __SOC_H__ */
diff --git a/soc/ambiq/soc.yml b/soc/ambiq/soc.yml
index b0a471d1fd5..2ac2fa56b8a 100644
--- a/soc/ambiq/soc.yml
+++ b/soc/ambiq/soc.yml
@@ -9,3 +9,6 @@ family:
     socs:
     - name: apollo3_blue
     - name: apollo3p_blue
+  - name: apollo5x
+    socs:
+    - name: apollo510
diff --git a/soc/amd/acp_6_0/Kconfig.soc b/soc/amd/acp_6_0/Kconfig.soc
index 89f5a09f2f7..321c4416d31 100644
--- a/soc/amd/acp_6_0/Kconfig.soc
+++ b/soc/amd/acp_6_0/Kconfig.soc
@@ -3,11 +3,10 @@
 
 config SOC_ACP_6_0
 	bool
-	default "BOARD_ACP_6_0_ADSP"
 
 config SOC
 	default "acp_6_0" if SOC_ACP_6_0
 
 config SOC_TOOLCHAIN_NAME
 	string
-	default "amd_acp_6_0_adsp"
+	default "amd_acp_6_0_adsp" if SOC_ACP_6_0
diff --git a/soc/andestech/ae350/linker.ld b/soc/andestech/ae350/linker.ld
index 4c94c705212..ae10cab3ccd 100644
--- a/soc/andestech/ae350/linker.ld
+++ b/soc/andestech/ae350/linker.ld
@@ -405,6 +405,15 @@ GROUP_END(DTCM)
 	KEEP(*(.gnu.attributes))
 	}
 
+/* Output section descriptions are needed for these sections to suppress
+ * warnings when "--orphan-handling=warn" is set for lld.
+ */
+#if defined(CONFIG_LLVM_USE_LLD)
+    SECTION_PROLOGUE(.symtab, 0,) { *(.symtab) }
+    SECTION_PROLOGUE(.strtab, 0,) { *(.strtab) }
+    SECTION_PROLOGUE(.shstrtab, 0,) { *(.shstrtab) }
+#endif
+
     /* Sections generated from 'zephyr,memory-region' nodes */
     LINKER_DT_SECTIONS()
 
diff --git a/soc/antmicro/myra/Kconfig b/soc/antmicro/myra/Kconfig
new file mode 100644
index 00000000000..5dd9da98770
--- /dev/null
+++ b/soc/antmicro/myra/Kconfig
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_MYRA
+	select SOC_STM32G491XX
diff --git a/soc/antmicro/myra/Kconfig.soc b/soc/antmicro/myra/Kconfig.soc
new file mode 100644
index 00000000000..adc05f48a5a
--- /dev/null
+++ b/soc/antmicro/myra/Kconfig.soc
@@ -0,0 +1,18 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+# The Myra is technically a SiP (System-in-Package) that consists of
+# the STM32G491REI6 MCU and additional components like FRAM. So for
+# Antmicro Myra SiP Baseboard the STM32G491XX SoC is to be indicated as
+# the build target, but since the Myra SiP is what a user can actually
+# see on a board, using only STM32G491XX in the Zephyr build
+# infrastructure might be confusing. That's why in the top level of SoC
+# definitions (for user-configurable options in Kconfig, for example)
+# the Myra term is used and STM32G491XX underneath.
+config SOC_MYRA
+	bool
+	help
+	  Antmicro Myra System-in-Package
+
+config SOC
+	default "myra" if SOC_MYRA
diff --git a/soc/antmicro/myra/soc.yml b/soc/antmicro/myra/soc.yml
new file mode 100644
index 00000000000..a36bf71cc87
--- /dev/null
+++ b/soc/antmicro/myra/soc.yml
@@ -0,0 +1,2 @@
+socs:
+  - name: myra
diff --git a/soc/arm/beetle/pinctrl_soc.h b/soc/arm/beetle/pinctrl_soc.h
new file mode 100644
index 00000000000..b515a8a0255
--- /dev/null
+++ b/soc/arm/beetle/pinctrl_soc.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/arm-v2m_beetle-pinctrl.h>
+
+/**
+ * @brief Type to hold a pin's pinctrl configuration.
+ */
+struct beetle_pinctrl_soc_pin {
+	/** Pin number 0..52 */
+	uint32_t pin_num : 6;
+	/** Alternative function (UART, SPI, etc.) */
+	uint32_t alt_func : 3;
+	/** Enable the pin as an input */
+	uint32_t input_enable : 1;
+};
+
+typedef struct beetle_pinctrl_soc_pin pinctrl_soc_pin_t;
+
+/**
+ * @brief Utility macro to initialize each pin.
+ *
+ * @param node_id Node identifier.
+ * @param prop Property name.
+ * @param idx Property entry index.
+ */
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx)				\
+	{									\
+		BEETLE_GET_PIN_NUM(DT_PROP_BY_IDX(node_id, prop, idx)),		\
+		BEETLE_GET_PIN_ALT_FUNC(DT_PROP_BY_IDX(node_id, prop, idx)),	\
+		DT_PROP(node_id, input_enable),					\
+	},
+
+/**
+ * @brief Utility macro to initialize state pins contained in a given property.
+ *
+ * @param node_id Node identifier.
+ * @param prop Property name describing state pins.
+ */
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)				\
+	{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop),			\
+				DT_FOREACH_PROP_ELEM, pinmux,			\
+				Z_PINCTRL_STATE_PIN_INIT)}
+
+#define BEETLE_GET_PIN_NUM(pinctrl) \
+	(((pinctrl) >> V2M_BEETLE_EXP_NUM_POS) & V2M_BEETLE_EXP_NUM_MASK)
+#define BEETLE_GET_PIN_ALT_FUNC(pinctrl) \
+	(((pinctrl) >> V2M_BEETLE_ALT_FUNC_POS) & V2M_BEETLE_ALT_FUNC_MASK)
diff --git a/soc/arm/mps2/Kconfig b/soc/arm/mps2/Kconfig
index 248be2250a2..2c999393a77 100644
--- a/soc/arm/mps2/Kconfig
+++ b/soc/arm/mps2/Kconfig
@@ -1,4 +1,5 @@
 # Copyright (c) 2017-2019 Linaro Limited
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_MPS2
@@ -9,10 +10,25 @@ config SOC_MPS2_AN521
 	select CPU_CORTEX_M33
 	select CPU_HAS_ARM_MPU
 
+config SOC_MPS2_AN383
+	select CPU_CORTEX_M0PLUS
+	select CPU_HAS_ARM_MPU
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_CORTEX_M_HAS_VTOR
+
 config SOC_MPS2_AN385
 	select CPU_CORTEX_M3
 	select CPU_HAS_ARM_MPU
 
+config SOC_MPS2_AN386
+	select CPU_CORTEX_M4
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_VFP
+
+config SOC_MPS2_AN500
+	select CPU_CORTEX_M7
+	select CPU_HAS_ARM_MPU
+
 config SOC_MPS2_AN521_CPU0
 	select CPU_HAS_ARM_SAU
 
diff --git a/soc/arm/mps2/Kconfig.defconfig.an383 b/soc/arm/mps2/Kconfig.defconfig.an383
new file mode 100644
index 00000000000..0d59cb09d26
--- /dev/null
+++ b/soc/arm/mps2/Kconfig.defconfig.an383
@@ -0,0 +1,9 @@
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MPS2_AN383
+
+config NUM_IRQS
+	default 32
+
+endif
diff --git a/soc/arm/mps2/Kconfig.defconfig.an386 b/soc/arm/mps2/Kconfig.defconfig.an386
new file mode 100644
index 00000000000..9c75afbef8b
--- /dev/null
+++ b/soc/arm/mps2/Kconfig.defconfig.an386
@@ -0,0 +1,9 @@
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MPS2_AN386
+
+config NUM_IRQS
+	default 32
+
+endif
diff --git a/soc/arm/mps2/Kconfig.defconfig.an500 b/soc/arm/mps2/Kconfig.defconfig.an500
new file mode 100644
index 00000000000..8cf914f573a
--- /dev/null
+++ b/soc/arm/mps2/Kconfig.defconfig.an500
@@ -0,0 +1,9 @@
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MPS2_AN500
+
+config NUM_IRQS
+	default 32
+
+endif
diff --git a/soc/arm/mps2/Kconfig.soc b/soc/arm/mps2/Kconfig.soc
index bc9fa98fdcc..42ba48639bb 100644
--- a/soc/arm/mps2/Kconfig.soc
+++ b/soc/arm/mps2/Kconfig.soc
@@ -1,4 +1,5 @@
 # Copyright (c) 2017-2019 Linaro Limited
+# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_MPS2
@@ -7,12 +8,30 @@ config SOC_SERIES_MPS2
 	help
 	  Enable support for ARM MPS2 MCU Series
 
+config SOC_MPS2_AN383
+	bool
+	select SOC_SERIES_MPS2
+	help
+	  ARM Cortex-M0+ SMM on V2M-MPS2 (Application Note AN383)
+
 config SOC_MPS2_AN385
 	bool
 	select SOC_SERIES_MPS2
 	help
 	  ARM Cortex-M3 SMM on V2M-MPS2 (Application Note AN385)
 
+config SOC_MPS2_AN386
+	bool
+	select SOC_SERIES_MPS2
+	help
+	  ARM Cortex-M4 SMM on V2M-MPS2 (Application Note AN386)
+
+config SOC_MPS2_AN500
+	bool
+	select SOC_SERIES_MPS2
+	help
+	  ARM Cortex-M7 SMM on V2M-MPS2+ (Application Note AN500)
+
 config SOC_MPS2_AN521
 	bool
 	select SOC_SERIES_MPS2
@@ -33,5 +52,8 @@ config SOC_SERIES
 	default "mps2" if SOC_SERIES_MPS2
 
 config SOC
+	default "an383" if SOC_MPS2_AN383
 	default "an385" if SOC_MPS2_AN385
+	default "an386" if SOC_MPS2_AN386
+	default "an500" if SOC_MPS2_AN500
 	default "an521" if SOC_MPS2_AN521
diff --git a/soc/arm/mps2/pinctrl_soc.h b/soc/arm/mps2/pinctrl_soc.h
new file mode 100644
index 00000000000..b3ab8b95a58
--- /dev/null
+++ b/soc/arm/mps2/pinctrl_soc.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/arm-mps2-pinctrl.h>
+
+/**
+ * @brief Type to hold a pin's pinctrl configuration.
+ */
+struct mps2_pinctrl_soc_pin {
+	/** Pin number 0..52 */
+	uint32_t pin_num : 6;
+	/** Alternative function (UART, SPI, etc.) */
+	uint32_t alt_func : 2;
+	/** Enable the pin as an input */
+	uint32_t input_enable : 1;
+};
+
+typedef struct mps2_pinctrl_soc_pin pinctrl_soc_pin_t;
+
+/**
+ * @brief Utility macro to initialize each pin.
+ *
+ * @param node_id Node identifier.
+ * @param prop Property name.
+ * @param idx Property entry index.
+ */
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx)				\
+	{									\
+		MPS2_GET_PIN_NUM(DT_PROP_BY_IDX(node_id, prop, idx)),		\
+		MPS2_GET_PIN_ALT_FUNC(DT_PROP_BY_IDX(node_id, prop, idx)),	\
+		DT_PROP(node_id, input_enable),					\
+	},
+
+/**
+ * @brief Utility macro to initialize state pins contained in a given property.
+ *
+ * @param node_id Node identifier.
+ * @param prop Property name describing state pins.
+ */
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)				\
+	{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop),			\
+				DT_FOREACH_PROP_ELEM, pinmux,			\
+				Z_PINCTRL_STATE_PIN_INIT)}
+
+#define MPS2_GET_PIN_NUM(pinctrl) \
+	(((pinctrl) >> MPS2_EXP_NUM_POS) & MPS2_EXP_NUM_MASK)
+#define MPS2_GET_PIN_ALT_FUNC(pinctrl) \
+	(((pinctrl) >> MPS2_ALT_FUNC_POS) & MPS2_ALT_FUNC_MASK)
diff --git a/soc/arm/mps2/soc.c b/soc/arm/mps2/soc.c
index 343330d4515..a45e1815f3d 100644
--- a/soc/arm/mps2/soc.c
+++ b/soc/arm/mps2/soc.c
@@ -7,40 +7,24 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/drivers/gpio/gpio_mmio32.h>
 #include <soc.h>
 #include <zephyr/linker/linker-defs.h>
 
-
-/* Setup GPIO drivers for accessing FPGAIO registers */
-#define FPGAIO_NODE(n) DT_INST(n, arm_mps2_fpgaio_gpio)
-#define FPGAIO_INIT(n)						\
-	GPIO_MMIO32_INIT(FPGAIO_NODE(n),			\
-			DT_REG_ADDR(FPGAIO_NODE(n)),		\
-			BIT_MASK(DT_PROP(FPGAIO_NODE(n), ngpios)))
-
-/* We expect there to be 3 arm,mps2-fpgaio-gpio devices:
- * led0, button, and misc
- */
-FPGAIO_INIT(0);
-FPGAIO_INIT(1);
-FPGAIO_INIT(2);
-
 /* (Secure System Control) Base Address */
-#define SSE_200_SYSTEM_CTRL_S_BASE	(0x50021000UL)
-#define SSE_200_SYSTEM_CTRL_INITSVTOR1	(SSE_200_SYSTEM_CTRL_S_BASE + 0x114)
-#define SSE_200_SYSTEM_CTRL_CPU_WAIT	(SSE_200_SYSTEM_CTRL_S_BASE + 0x118)
-#define SSE_200_CPU_ID_UNIT_BASE	(0x5001F000UL)
+#define SSE_200_SYSTEM_CTRL_S_BASE     (0x50021000UL)
+#define SSE_200_SYSTEM_CTRL_INITSVTOR1 (SSE_200_SYSTEM_CTRL_S_BASE + 0x114)
+#define SSE_200_SYSTEM_CTRL_CPU_WAIT   (SSE_200_SYSTEM_CTRL_S_BASE + 0x118)
+#define SSE_200_CPU_ID_UNIT_BASE       (0x5001F000UL)
 
 /* The base address that the application image will start at on the secondary
  * (non-TrustZone) Cortex-M33 mcu.
  */
-#define CPU1_FLASH_ADDRESS      (0x38B000)
+#define CPU1_FLASH_ADDRESS (0x38B000)
 
 /* The memory map offset for the application image, which is used
  * to determine the location of the reset vector at startup.
  */
-#define CPU1_FLASH_OFFSET       (0x10000000)
+#define CPU1_FLASH_OFFSET (0x10000000)
 
 /**
  * @brief Wake up CPU 1 from another CPU, this is platform specific.
@@ -49,9 +33,7 @@ void wakeup_cpu1(void)
 {
 	/* Set the Initial Secure Reset Vector Register for CPU 1 */
 	*(uint32_t *)(SSE_200_SYSTEM_CTRL_INITSVTOR1) =
-		(uint32_t)_vector_start +
-		CPU1_FLASH_ADDRESS -
-		CPU1_FLASH_OFFSET;
+		(uint32_t)_vector_start + CPU1_FLASH_ADDRESS - CPU1_FLASH_OFFSET;
 
 	/* Set the CPU Boot wait control after reset */
 	*(uint32_t *)(SSE_200_SYSTEM_CTRL_CPU_WAIT) = 0;
diff --git a/soc/arm/mps3/CMakeLists.txt b/soc/arm/mps3/CMakeLists.txt
index 3cf33caa58d..bd8fb92d780 100644
--- a/soc/arm/mps3/CMakeLists.txt
+++ b/soc/arm/mps3/CMakeLists.txt
@@ -1,10 +1,6 @@
 # Copyright (c) 2021 Linaro Limited
 # SPDX-License-Identifier: Apache-2.0
 
-zephyr_sources(
-  soc.c
-  )
-
 zephyr_include_directories(.)
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/arm/mps3/Kconfig b/soc/arm/mps3/Kconfig
index 304e8065fcb..732cbb5811a 100644
--- a/soc/arm/mps3/Kconfig
+++ b/soc/arm/mps3/Kconfig
@@ -1,5 +1,5 @@
 # Copyright (c) 2017-2021 Linaro Limited
-# Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
+# Copyright 2024-2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_MPS3
@@ -15,6 +15,7 @@ config SOC_MPS3_CORSTONE300
 	select ARMV8_1_M_MVEI
 	select ARMV8_1_M_MVEF
 	select ARMV8_1_M_PMU
+	select ARM_MPU_PXN if ARM_MPU
 
 config SOC_MPS3_CORSTONE310
 	select CPU_CORTEX_M85
@@ -25,6 +26,7 @@ config SOC_MPS3_CORSTONE310
 	select ARMV8_1_M_MVEI
 	select ARMV8_1_M_MVEF
 	select ARMV8_1_M_PMU
+	select ARM_MPU_PXN if ARM_MPU
 
 config ARMV8_1_M_PMU_EVENTCNT
 	int
diff --git a/soc/arm/mps3/pinctrl_soc.h b/soc/arm/mps3/pinctrl_soc.h
new file mode 100644
index 00000000000..96050defc7f
--- /dev/null
+++ b/soc/arm/mps3/pinctrl_soc.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/arm-mps3-pinctrl.h>
+
+/**
+ * @brief Type to hold a pin's pinctrl configuration.
+ */
+struct mps3_pinctrl_soc_pin {
+	/** Pin number 0..52 */
+	uint32_t pin_num : 6;
+	/** Alternative function (UART, SPI, etc.) */
+	uint32_t alt_func : 3;
+	/** Enable the pin as an input */
+	uint32_t input_enable : 1;
+};
+
+typedef struct mps3_pinctrl_soc_pin pinctrl_soc_pin_t;
+
+/**
+ * @brief Utility macro to initialize each pin.
+ *
+ * @param node_id Node identifier.
+ * @param prop Property name.
+ * @param idx Property entry index.
+ */
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx)				\
+	{									\
+		MPS3_GET_PIN_NUM(DT_PROP_BY_IDX(node_id, prop, idx)),		\
+		MPS3_GET_PIN_ALT_FUNC(DT_PROP_BY_IDX(node_id, prop, idx)),	\
+		DT_PROP(node_id, input_enable),					\
+	},
+
+/**
+ * @brief Utility macro to initialize state pins contained in a given property.
+ *
+ * @param node_id Node identifier.
+ * @param prop Property name describing state pins.
+ */
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)				\
+	{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop),			\
+				DT_FOREACH_PROP_ELEM, pinmux,			\
+				Z_PINCTRL_STATE_PIN_INIT)}
+
+#define MPS3_GET_PIN_NUM(pinctrl)				\
+	(((pinctrl) >> MPS3_EXP_NUM_POS) & MPS3_EXP_NUM_MASK)
+#define MPS3_GET_PIN_ALT_FUNC(pinctrl)				\
+	(((pinctrl) >> MPS3_ALT_FUNC_POS) & MPS3_ALT_FUNC_MASK)
diff --git a/soc/arm/mps3/soc.c b/soc/arm/mps3/soc.c
deleted file mode 100644
index e51a9ba5c59..00000000000
--- a/soc/arm/mps3/soc.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (c) 2021 Linaro Limited
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/drivers/gpio/gpio_mmio32.h>
-#include <soc.h>
-#include <zephyr/linker/linker-defs.h>
-
-
-/* Setup GPIO drivers for accessing FPGAIO registers */
-#define FPGAIO_NODE(n) DT_INST(n, arm_mps3_fpgaio_gpio)
-#define FPGAIO_INIT(n)						\
-	GPIO_MMIO32_INIT(FPGAIO_NODE(n),			\
-			DT_REG_ADDR(FPGAIO_NODE(n)),		\
-			BIT_MASK(DT_PROP(FPGAIO_NODE(n), ngpios)))
-
-/* We expect there to be 3 arm,mps3-fpgaio-gpio devices:
- * led0, button, and misc
- */
-FPGAIO_INIT(0);
-FPGAIO_INIT(1);
-FPGAIO_INIT(2);
diff --git a/soc/arm/soc.yml b/soc/arm/soc.yml
index 4f1f01726de..866f34dafd4 100644
--- a/soc/arm/soc.yml
+++ b/soc/arm/soc.yml
@@ -3,7 +3,10 @@ family:
   series:
   - name: mps2
     socs:
+    - name: an383
     - name: an385
+    - name: an386
+    - name: an500
     - name: an521
       cpuclusters:
       - name: cpu0
diff --git a/soc/atmel/sam/common/Kconfig b/soc/atmel/sam/common/Kconfig
index e9709351f5c..e6c4e2744d1 100644
--- a/soc/atmel/sam/common/Kconfig
+++ b/soc/atmel/sam/common/Kconfig
@@ -32,13 +32,25 @@ config SOC_ATMEL_SAM_EXT_MAINCK
 
 	  Says n here will use the internal fast RC oscillator running at 12 MHz.
 
+config SOC_ATMEL_SAM_EXT_MAINCK_BYPASS
+	bool "Use bypass mode for external crystal oscillator"
+	depends on SOC_ATMEL_SAM_EXT_MAINCK
+	help
+	  When bypass mode is enabled, the external crystal oscillator is bypassed,
+	  and the main clock is directly driven by an external clock signal.
+
+	  Says y here if you want to use an external clock signal directly instead
+	  of the crystal oscillator.
+
+	  Says n here to use the external crystal oscillator normally.
+
 menu "PLL A"
 
 config SOC_ATMEL_SAM_PLLA_MULA
 	int "PLL MULA"
 	default  6 if SOC_SERIES_SAM3X
 	default  9 if SOC_SERIES_SAM4S  || SOC_SERIES_SAM4E
-	default 24 if SOC_SERIES_SAME70 || SOC_SERIES_SAMV71
+	default 24 if SOC_SERIES_SAMX7X
 	range 1 62
 	help
 	  This is the multiplier (MULA) used by the PLL.
@@ -65,7 +77,7 @@ config SOC_ATMEL_SAM_PLLA_DIVA
 
 config SOC_ATMEL_SAM_MDIV
 	int "MDIV"
-	depends on SOC_SERIES_SAME70 || SOC_SERIES_SAMV71
+	depends on SOC_SERIES_SAMX7X
 	default 2
 	range 1 4
 	help
diff --git a/soc/atmel/sam/common/pwm_fixup.h b/soc/atmel/sam/common/pwm_fixup.h
deleted file mode 100644
index b2a038f8e86..00000000000
--- a/soc/atmel/sam/common/pwm_fixup.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2021 Linaro Limited
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _ATMEL_SAM_PWM_FIXUP_H_
-#define _ATMEL_SAM_PWM_FIXUP_H_
-
-/* The SAMV71 HALs change the name of the field, so we need to
- * define it this way to match how the other SoC variants name it
- */
-#if defined(CONFIG_SOC_SERIES_SAMV71)
-#define PWM_CH_NUM PwmChNum
-#endif
-
-#endif /* _ATMEL_SAM_PWM_FIXUP_H_ */
diff --git a/soc/atmel/sam/common/soc_pmc.h b/soc/atmel/sam/common/soc_pmc.h
index 3be251a3d09..dc730faa026 100644
--- a/soc/atmel/sam/common/soc_pmc.h
+++ b/soc/atmel/sam/common/soc_pmc.h
@@ -119,7 +119,7 @@ static ALWAYS_INLINE void soc_pmc_mck_set_prescaler(uint32_t prescaler)
 	}
 }
 
-#if defined(CONFIG_SOC_SERIES_SAME70) || defined(CONFIG_SOC_SERIES_SAMV71)
+#ifdef CONFIG_SOC_SERIES_SAMX7X
 
 /**
  * @brief Set the divider of the Master clock.
@@ -155,7 +155,7 @@ static ALWAYS_INLINE void soc_pmc_mck_set_divider(uint32_t divider)
 	}
 }
 
-#endif /* CONFIG_SOC_SERIES_SAME70 || CONFIG_SOC_SERIES_SAMV71 */
+#endif /* CONFIG_SOC_SERIES_SAMX7X */
 
 /**
  * @brief Set the source of the Master clock.
diff --git a/soc/atmel/sam/sam4l/soc.c b/soc/atmel/sam/sam4l/soc.c
index 3836d99723e..ae34131515a 100644
--- a/soc/atmel/sam/sam4l/soc.c
+++ b/soc/atmel/sam/sam4l/soc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
+ * Copyright (c) 2020-2025 Gerson Fernando Budke <nandojve@gmail.com>
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -16,33 +16,6 @@
 #include <soc.h>
 #include <zephyr/sys/util.h>
 
-/** Watchdog control register first write keys */
-#define WDT_FIRST_KEY     0x55ul
-/** Watchdog control register second write keys */
-#define WDT_SECOND_KEY    0xAAul
-
-/**
- * @brief Sets the WatchDog Timer Control register to the \a ctrl value thanks
- *        to the WatchDog Timer key.
- *
- * @param ctrl  Value to set the WatchDog Timer Control register to.
- */
-static ALWAYS_INLINE void wdt_set_ctrl(uint32_t ctrl)
-{
-	volatile uint32_t dly;
-
-	/** Calculate delay for internal synchronization
-	 *    see 45.1.3 WDT errata
-	 */
-	dly = DIV_ROUND_UP(48000000 * 2, 115000);
-	dly >>= 3; /* ~8 cycles for one while loop */
-	while (dly--) {
-		;
-	}
-	WDT->CTRL = ctrl | WDT_CTRL_KEY(WDT_FIRST_KEY);
-	WDT->CTRL = ctrl | WDT_CTRL_KEY(WDT_SECOND_KEY);
-}
-
 #define XTAL_FREQ 12000000
 #define NR_PLLS 1
 #define PLL_MAX_STARTUP_CYCLES (SCIF_PLL_PLLCOUNT_Msk >> SCIF_PLL_PLLCOUNT_Pos)
@@ -83,6 +56,19 @@ static inline bool osc_is_ready(uint8_t id)
 	}
 }
 
+/**
+ * Enable Backup System Control Oscilator RC32K
+ */
+static inline void osc_priv_enable_rc32k(void)
+{
+	uint32_t temp = BSCIF->RC32KCR;
+	uint32_t addr = (uint32_t)&BSCIF->RC32KCR - (uint32_t)BSCIF;
+
+	BSCIF->UNLOCK = BSCIF_UNLOCK_KEY(0xAAu)
+		      | BSCIF_UNLOCK_ADDR(addr);
+	BSCIF->RC32KCR = temp | BSCIF_RC32KCR_EN32K | BSCIF_RC32KCR_EN;
+}
+
 /**
  * The PLL options #PLL_OPT_VCO_RANGE_HIGH and #PLL_OPT_OUTPUT_DIV will
  * be set automatically based on the calculated target frequency.
@@ -180,6 +166,8 @@ static inline void flashcalw_issue_command(uint32_t command, int page_number)
  */
 static ALWAYS_INLINE void clock_init(void)
 {
+	uint32_t gen_clk_conf;
+
 	/* Disable PicoCache and Enable HRAMC1 as extended RAM */
 	soc_pmc_peripheral_enable(
 		PM_CLOCK_MASK(PM_CLK_GRP_HSB, SYSCLK_HRAMC1_DATA));
@@ -251,17 +239,28 @@ static ALWAYS_INLINE void clock_init(void)
 	PM->UNLOCK = PM_UNLOCK_KEY(0xAAu) |
 		     PM_UNLOCK_ADDR((uint32_t)&PM->MCCTRL - (uint32_t)PM);
 	PM->MCCTRL = OSC_SRC_PLL0;
-}
 
-void soc_reset_hook(void)
-{
-#if defined(CONFIG_WDT_DISABLE_AT_BOOT)
-	wdt_set_ctrl(WDT->CTRL & ~WDT_CTRL_EN);
-	while (WDT->CTRL & WDT_CTRL_EN) {
+	/** Enable RC32K Oscilator */
+	osc_priv_enable_rc32k();
+	while (!osc_is_ready(OSC_ID_RC32K)) {
 		;
 	}
-#endif
 
+	/** Enable Generic Clock 5
+	 *   Source: RC32K
+	 *      Div: 32
+	 *      Clk: 1024 Hz
+	 *  The GCLK-5 can be used by GLOC, TC0 and RC32KIFB_REF
+	 */
+	gen_clk_conf = SCIF_GCCTRL_RESETVALUE;
+	gen_clk_conf |= SCIF_GCCTRL_OSCSEL(GEN_CLK_SRC_RC32K);
+	gen_clk_conf |= SCIF_GCCTRL_DIVEN;
+	gen_clk_conf |= SCIF_GCCTRL_DIV(((32 + 1) / 2) - 1);
+	SCIF->GCCTRL[GEN_CLK_TC0_GLOC_RC32] = gen_clk_conf | SCIF_GCCTRL_CEN;
+}
+
+void soc_reset_hook(void)
+{
 	/* Setup system clocks. */
 	clock_init();
 }
diff --git a/soc/atmel/sam/sam4l/soc.h b/soc/atmel/sam/sam4l/soc.h
index 329178aa288..09180c6e2b6 100644
--- a/soc/atmel/sam/sam4l/soc.h
+++ b/soc/atmel/sam/sam4l/soc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020-2024 Gerson Fernando Budke <nandojve@gmail.com>
+ * Copyright (c) 2020-2025 Gerson Fernando Budke <nandojve@gmail.com>
  * SPDX-License-Identifier: Apache-2.0
  */
 
@@ -66,6 +66,9 @@
 /** Master Clock (MCK) Frequency */
 #define SOC_ATMEL_SAM_MCK_FREQ_HZ       SOC_ATMEL_SAM_HCLK_FREQ_HZ
 
+#define SOC_ATMEL_SAM_RCSYS_NOMINAL_HZ	115000
+#define SOC_ATMEL_SAM_RC32K_NOMINAL_HZ	32768
+
 /** Oscillator identifiers
  *    External Oscillator 0
  *    External 32 kHz oscillator
@@ -205,18 +208,64 @@
  *   10- ADCIFE
  *   11- Master generic clock. Can be used as source for other generic clocks.
  */
-#define GEN_CLK_DFLL_REF	0
-#define GEN_CLK_DFLL_DITHER	1
-#define GEN_CLK_AST		2
-#define GEN_CLK_CATB		3
-#define GEN_CLK_AESA		4
-#define GEN_CLK_GLOC		5
-#define GEN_CLK_ABDACB		6
-#define GEN_CLK_USBC		7
-#define GEN_CLK_TC1_PEVC0	8
-#define GEN_CLK_PLL0_PEVC1	9
-#define GEN_CLK_ADCIFE		10
-#define GEN_CLK_MASTER_GEN	11
+#define GEN_CLK_DFLL_REF        0
+#define GEN_CLK_DFLL_DITHER     1
+#define GEN_CLK_AST             2
+#define GEN_CLK_CATB            3
+#define GEN_CLK_AESA            4
+#define GEN_CLK_TC0_GLOC_RC32   5
+#define GEN_CLK_ABDACB          6
+#define GEN_CLK_USBC            7
+#define GEN_CLK_TC1_PEVC0       8
+#define GEN_CLK_PLL0_PEVC1      9
+#define GEN_CLK_ADCIFE          10
+#define GEN_CLK_MASTER_GEN      11
+
+/**
+ *    0-  System RC oscillator
+ *    1-  32 kHz oscillator
+ *    2-  DFLL
+ *    3-  Oscillator 0
+ *    4-  80 MHz RC oscillator
+ *    5-  4-8-12 MHz RC oscillator
+ *    6-  1 MHz RC oscillator
+ *    7-  CPU clock
+ *    8-  High Speed Bus clock
+ *    9-  Peripheral Bus A clock
+ *    10- Peripheral Bus B clock
+ *    11- Peripheral Bus C clock
+ *    12- Peripheral Bus D clock
+ *    13- 32 kHz RC oscillator
+ *    15- 1 kHz output from OSC32K
+ *    16- PLL0
+ *    17- High resolution prescaler
+ *    18- Fractional prescaler
+ *    19- GCLKIN0
+ *    20- GCLKIN1
+ *    21- GCLK11
+ */
+
+#define GEN_CLK_SRC_RCSYS	0
+#define GEN_CLK_SRC_OSC32K	1
+#define GEN_CLK_SRC_DFLL	2
+#define GEN_CLK_SRC_OSC0	3
+#define GEN_CLK_SRC_RC80M	4
+#define GEN_CLK_SRC_RCFAST	5
+#define GEN_CLK_SRC_RC1M	6
+#define GEN_CLK_SRC_CLK_CPU	7
+#define GEN_CLK_SRC_CLK_HSB	8
+#define GEN_CLK_SRC_CLK_PBA	9
+#define GEN_CLK_SRC_CLK_PBB	10
+#define GEN_CLK_SRC_CLK_PBC	11
+#define GEN_CLK_SRC_CLK_PBD	12
+#define GEN_CLK_SRC_RC32K	13
+#define GEN_CLK_SRC_CLK_1K	15
+#define GEN_CLK_SRC_PLL0	16
+#define GEN_CLK_SRC_HRPCLK	17
+#define GEN_CLK_SRC_FPCLK	18
+#define GEN_CLK_SRC_GCLKIN0	19
+#define GEN_CLK_SRC_GCLKIN1	20
+#define GEN_CLK_SRC_GCLK11	21
 
 #endif /* !_ASMLANGUAGE */
 
diff --git a/soc/atmel/sam/same70/Kconfig b/soc/atmel/sam/same70/Kconfig
deleted file mode 100644
index a41b5e4e587..00000000000
--- a/soc/atmel/sam/same70/Kconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-# Atmel SAM E70 MCU series
-
-# Copyright (c) 2016 Piotr Mienkowski
-# Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_SAME70
-	select ARM
-	select CPU_CORTEX_M7
-	select CPU_CORTEX_M_HAS_DWT
-	select CPU_HAS_ARM_MPU
-	select CPU_HAS_FPU_DOUBLE_PRECISION
-	select CPU_HAS_ICACHE
-	select CPU_HAS_DCACHE
-	select INIT_ARCH_HW_AT_BOOT
-	select SOC_RESET_HOOK
-	select HAS_SWO
-	select XIP
-	select HAS_POWEROFF
-	select SOC_EARLY_INIT_HOOK
diff --git a/soc/atmel/sam/same70/Kconfig.defconfig b/soc/atmel/sam/same70/Kconfig.defconfig
deleted file mode 100644
index 6d2a78218c2..00000000000
--- a/soc/atmel/sam/same70/Kconfig.defconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# Atmel SAM E70 MCU series configuration options
-
-# Copyright (c) 2016 Piotr Mienkowski
-# Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_SAME70
-
-config NUM_IRQS
-	default 74 if SOC_ATMEL_SAME70_REVB
-	default 71
-
-endif # SOC_SERIES_SAME70
diff --git a/soc/atmel/sam/same70/Kconfig.soc b/soc/atmel/sam/same70/Kconfig.soc
deleted file mode 100644
index 1cef18f21f1..00000000000
--- a/soc/atmel/sam/same70/Kconfig.soc
+++ /dev/null
@@ -1,122 +0,0 @@
-# Atmel SAM E70 MCU series
-
-# Copyright (c) 2016 Piotr Mienkowski
-# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_SAME70
-	bool
-	select SOC_FAMILY_ATMEL_SAM
-	help
-	  Enable support for Atmel SAM E70 ARM Cortex-M7 Microcontrollers.
-	  Part No.: SAME70J19, SAME70J20, SAME70J21, SAME70N19, SAME70N20,
-	  SAME70N21, SAME70Q19, SAME70Q20, SAME70Q21, SAME70J19B, SAME70J20B,
-	  SAME70J21B, SAME70N19B, SAME70N20B, SAME70N21B, SAME70Q19B,
-	  SAME70Q20B, SAME70Q21B
-
-config SOC_ATMEL_SAME70_REVB
-	bool
-
-config SOC_SERIES
-	default "same70" if SOC_SERIES_SAME70
-
-config SOC_SAME70J19
-	bool
-	select SOC_SERIES_SAME70
-
-config SOC_SAME70J20
-	bool
-	select SOC_SERIES_SAME70
-
-config SOC_SAME70J21
-	bool
-	select SOC_SERIES_SAME70
-
-config SOC_SAME70N19
-	bool
-	select SOC_SERIES_SAME70
-
-config SOC_SAME70N20
-	bool
-	select SOC_SERIES_SAME70
-
-config SOC_SAME70N21
-	bool
-	select SOC_SERIES_SAME70
-
-config SOC_SAME70Q19
-	bool
-	select SOC_SERIES_SAME70
-
-config SOC_SAME70Q20
-	bool
-	select SOC_SERIES_SAME70
-
-config SOC_SAME70Q21
-	bool
-	select SOC_SERIES_SAME70
-
-config SOC_SAME70J19B
-	bool
-	select SOC_SERIES_SAME70
-	select SOC_ATMEL_SAME70_REVB
-
-config SOC_SAME70J20B
-	bool
-	select SOC_SERIES_SAME70
-	select SOC_ATMEL_SAME70_REVB
-
-config SOC_SAME70J21B
-	bool
-	select SOC_SERIES_SAME70
-	select SOC_ATMEL_SAME70_REVB
-
-config SOC_SAME70N19B
-	bool
-	select SOC_SERIES_SAME70
-	select SOC_ATMEL_SAME70_REVB
-
-config SOC_SAME70N20B
-	bool
-	select SOC_SERIES_SAME70
-	select SOC_ATMEL_SAME70_REVB
-
-config SOC_SAME70N21B
-	bool
-	select SOC_SERIES_SAME70
-	select SOC_ATMEL_SAME70_REVB
-
-config SOC_SAME70Q19B
-	bool
-	select SOC_SERIES_SAME70
-	select SOC_ATMEL_SAME70_REVB
-
-config SOC_SAME70Q20B
-	bool
-	select SOC_SERIES_SAME70
-	select SOC_ATMEL_SAME70_REVB
-
-config SOC_SAME70Q21B
-	bool
-	select SOC_SERIES_SAME70
-	select SOC_ATMEL_SAME70_REVB
-
-config SOC
-	default "same70j19" if SOC_SAME70J19
-	default "same70j20" if SOC_SAME70J20
-	default "same70j21" if SOC_SAME70J21
-	default "same70n19" if SOC_SAME70N19
-	default "same70n20" if SOC_SAME70N20
-	default "same70n21" if SOC_SAME70N21
-	default "same70q19" if SOC_SAME70Q19
-	default "same70q20" if SOC_SAME70Q20
-	default "same70q21" if SOC_SAME70Q21
-	default "same70j19b" if SOC_SAME70J19B
-	default "same70j20b" if SOC_SAME70J20B
-	default "same70j21b" if SOC_SAME70J21B
-	default "same70n19b" if SOC_SAME70N19B
-	default "same70n20b" if SOC_SAME70N20B
-	default "same70n21b" if SOC_SAME70N21B
-	default "same70q19b" if SOC_SAME70Q19B
-	default "same70q20b" if SOC_SAME70Q20B
-	default "same70q21b" if SOC_SAME70Q21B
diff --git a/soc/atmel/sam/same70/soc.c b/soc/atmel/sam/same70/soc.c
deleted file mode 100644
index fdadb506dc5..00000000000
--- a/soc/atmel/sam/same70/soc.c
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * Copyright (c) 2016 Piotr Mienkowski
- * Copyright (c) 2023-2024 Gerson Fernando Budke <nandojve@gmail.com>
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/** @file
- * @brief Atmel SAM E70 MCU initialization code
- *
- * This file provides routines to initialize and support board-level hardware
- * for the Atmel SAM E70 MCU.
- */
-
-#include <zephyr/kernel.h>
-#include <zephyr/device.h>
-#include <zephyr/init.h>
-#include <zephyr/cache.h>
-#include <zephyr/arch/cache.h>
-#include <soc.h>
-#include <soc_pmc.h>
-#include <soc_supc.h>
-#include <cmsis_core.h>
-#include <zephyr/logging/log.h>
-
-#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
-LOG_MODULE_REGISTER(soc);
-
-/**
- * @brief Setup various clocks on SoC at boot time.
- *
- * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
- * It is assumed that the relevant registers are at their reset value.
- */
-static ALWAYS_INLINE void clock_init(void)
-{
-	/* Switch the main clock to the internal OSC with 12MHz */
-	soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ);
-
-	/* Switch MCK (Master Clock) to the main clock */
-	soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK);
-
-	EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE;
-
-	soc_pmc_enable_clock_failure_detector();
-
-	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) {
-		soc_supc_slow_clock_select_crystal_osc();
-	}
-
-
-	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
-		/*
-		 * Setup main external crystal oscillator.
-		 */
-
-		/* We select maximum setup time.
-		 * While start up time could be shortened
-		 * this optimization is not deemed
-		 * critical now.
-		 */
-		soc_pmc_switch_mainck_to_xtal(false, 0xff);
-	}
-
-	/*
-	 * Set FWS (Flash Wait State) value before increasing Master Clock
-	 * (MCK) frequency.
-	 * TODO: set FWS based on the actual MCK frequency and VDDIO value
-	 * rather than maximum supported 150 MHz at standard VDDIO=2.7V
-	 */
-	EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE;
-
-	/*
-	 * Setup PLLA
-	 */
-
-	/*
-	 * PLL clock = Main * (MULA + 1) / DIVA
-	 *
-	 * By default, MULA == 24, DIVA == 1.
-	 * With main crystal running at 12 MHz,
-	 * PLL = 12 * (24 + 1) / 1 = 300 MHz
-	 *
-	 * With Processor Clock prescaler at 1
-	 * Processor Clock (HCLK)=300 MHz.
-	 */
-	soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu,
-			      CONFIG_SOC_ATMEL_SAM_PLLA_DIVA);
-
-
-	soc_pmc_enable_upllck(0x3Fu);
-
-	/*
-	 * Final setup of the Master Clock
-	 */
-
-	/* Setting PLLA as MCK, first prescaler, then divider and source last */
-	soc_pmc_mck_set_prescaler(1);
-	soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAM_MDIV);
-	soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
-
-
-	/* Disable internal fast RC if we have an external crystal oscillator */
-	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
-		soc_pmc_osc_disable_fastrc();
-	}
-}
-
-void soc_reset_hook(void)
-{
-	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
-		/*
-		 * Instruct CPU to enter Wait mode instead of Sleep mode to
-		 * keep Processor Clock (HCLK) and thus be able to debug
-		 * CPU using JTAG.
-		 */
-		soc_pmc_enable_waitmode();
-	}
-
-	/*
-	 * DTCM is enabled by default at reset, therefore we have to disable
-	 * it first to get the caches into a state where then the
-	 * sys_cache*-functions can enable them, if requested by the
-	 * configuration.
-	 */
-	SCB_InvalidateDCache();
-	SCB_DisableDCache();
-
-	/*
-	 * Enable the caches only if configured to do so.
-	 */
-	sys_cache_instr_enable();
-	sys_cache_data_enable();
-
-	/* Setup system clocks */
-	clock_init();
-}
-
-extern void atmel_same70_config(void);
-/**
- * @brief Perform basic hardware initialization at boot.
- *
- * This needs to be run at the very beginning.
- */
-void soc_early_init_hook(void)
-{
-	/* Check that the CHIP CIDR matches the HAL one */
-	if (CHIPID->CHIPID_CIDR != CHIP_CIDR) {
-		LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x",
-			(uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR);
-	}
-	atmel_same70_config();
-}
diff --git a/soc/atmel/sam/same70/soc.h b/soc/atmel/sam/same70/soc.h
deleted file mode 100644
index 92cec70d926..00000000000
--- a/soc/atmel/sam/same70/soc.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * Copyright (c) 2016 Piotr Mienkowski
- * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/** @file
- * @brief Register access macros for the Atmel SAM E70 MCU.
- *
- * This file provides register access macros for the Atmel SAM E70 MCU, HAL
- * drivers for core peripherals as well as symbols specific to Atmel SAM family.
- */
-
-#ifndef _SOC_ATMEL_SAM_SAME70_SOC_H_
-#define _SOC_ATMEL_SAM_SAME70_SOC_H_
-
-#include <zephyr/sys/util.h>
-
-#ifndef _ASMLANGUAGE
-
-#define DONT_USE_CMSIS_INIT
-#define DONT_USE_PREDEFINED_CORE_HANDLERS
-#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
-
-#if defined(CONFIG_SOC_SAME70J19)
-#include <same70j19.h>
-#elif defined(CONFIG_SOC_SAME70J20)
-#include <same70j20.h>
-#elif defined(CONFIG_SOC_SAME70J21)
-#include <same70j21.h>
-#elif defined(CONFIG_SOC_SAME70N19)
-#include <same70n19.h>
-#elif defined(CONFIG_SOC_SAME70N20)
-#include <same70n20.h>
-#elif defined(CONFIG_SOC_SAME70N21)
-#include <same70n21.h>
-#elif defined(CONFIG_SOC_SAME70Q19)
-#include <same70q19.h>
-#elif defined(CONFIG_SOC_SAME70Q20)
-#include <same70q20.h>
-#elif defined(CONFIG_SOC_SAME70Q21)
-#include <same70q21.h>
-#elif defined(CONFIG_SOC_SAME70J19B)
-#include <same70j19b.h>
-#elif defined(CONFIG_SOC_SAME70J20B)
-#include <same70j20b.h>
-#elif defined(CONFIG_SOC_SAME70J21B)
-#include <same70j21b.h>
-#elif defined(CONFIG_SOC_SAME70N19B)
-#include <same70n19b.h>
-#elif defined(CONFIG_SOC_SAME70N20B)
-#include <same70n20b.h>
-#elif defined(CONFIG_SOC_SAME70N21B)
-#include <same70n21b.h>
-#elif defined(CONFIG_SOC_SAME70Q19B)
-#include <same70q19b.h>
-#elif defined(CONFIG_SOC_SAME70Q20B)
-#include <same70q20b.h>
-#elif defined(CONFIG_SOC_SAME70Q21B)
-#include <same70q21b.h>
-#else
-  #error Library does not support the specified device.
-#endif
-
-#include "../common/soc_pmc.h"
-#include "../common/soc_gpio.h"
-#include "../common/soc_supc.h"
-#include "../common/atmel_sam_dt.h"
-
-/** Processor Clock (HCLK) Frequency */
-#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ
-
-/** Master Clock (MCK) Frequency */
-#define SOC_ATMEL_SAM_MCK_FREQ_HZ \
-	(SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAM_MDIV)
-
-/** UTMI PLL clock (UPLLCK) Frequency */
-#define SOC_ATMEL_SAM_UPLLCK_FREQ_HZ MHZ(480)
-
-#endif /* _ASMLANGUAGE */
-
-#endif /* _SOC_ATMEL_SAM_SAME70_SOC_H_ */
diff --git a/soc/atmel/sam/same70/soc_config.c b/soc/atmel/sam/same70/soc_config.c
deleted file mode 100644
index c390235c759..00000000000
--- a/soc/atmel/sam/same70/soc_config.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (c) 2016 Piotr Mienkowski
- * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/** @file
- * @brief System module to support early Atmel SAM E70 MCU configuration
- */
-
-#include <zephyr/device.h>
-#include <zephyr/init.h>
-#include <soc.h>
-#include <zephyr/arch/cpu.h>
-
-/**
- * @brief Perform SoC configuration at boot.
- *
- * This should be run early during the boot process but after basic hardware
- * initialization is done.
- */
-void atmel_same70_config(void)
-{
-	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_DISABLE_ERASE_PIN)) {
-		/* Disable ERASE function on PB12 pin, this is controlled
-		 * by Bus Matrix
-		 */
-		MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12;
-	}
-
-	/* In Cortex-M based SoCs JTAG interface can be used to perform
-	 * IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug
-	 * interface therefore there is no harm done by disabling the JTAG TDI
-	 * pin by default.
-	 */
-	/* Disable TDI function on PB4 pin, this is controlled by Bus Matrix */
-	MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4;
-
-	if (IS_ENABLED(CONFIG_LOG_BACKEND_SWO)) {
-		/* Disable PCK3 clock used by ETM module */
-		PMC->PMC_SCDR = PMC_SCDR_PCK3;
-		while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) {
-			;
-		}
-		/* Select PLLA clock as PCK3 clock */
-		PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK;
-		/* Enable PCK3 clock */
-		PMC->PMC_SCER = PMC_SCER_PCK3;
-		/* Wait for PCK3 setup to complete */
-		while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) {
-			;
-		}
-		/* Enable TDO/TRACESWO function on PB5 pin */
-		MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5;
-	} else {
-		/* Disable TDO/TRACESWO function on PB5 pin */
-		MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5;
-	}
-
-}
diff --git a/soc/atmel/sam/samv71/CMakeLists.txt b/soc/atmel/sam/samv71/CMakeLists.txt
deleted file mode 100644
index 2ed685c2f6f..00000000000
--- a/soc/atmel/sam/samv71/CMakeLists.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_include_directories(.)
-
-zephyr_sources(
-  soc.c
-  soc_config.c
-  )
-
-set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/atmel/sam/samv71/Kconfig b/soc/atmel/sam/samv71/Kconfig
deleted file mode 100644
index c1dcc0c4e34..00000000000
--- a/soc/atmel/sam/samv71/Kconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-# Atmel SAM V71 MCU series
-
-# Copyright (c) 2016 Piotr Mienkowski
-# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_SAMV71
-	select ARM
-	select CPU_CORTEX_M7
-	select CPU_CORTEX_M_HAS_DWT
-	select CPU_HAS_ARM_MPU
-	select CPU_HAS_FPU_DOUBLE_PRECISION
-	select CPU_HAS_ICACHE
-	select CPU_HAS_DCACHE
-	select INIT_ARCH_HW_AT_BOOT
-	select SOC_RESET_HOOK
-	select HAS_SWO
-	select XIP
-	select HAS_POWEROFF
-	select SOC_EARLY_INIT_HOOK
diff --git a/soc/atmel/sam/samv71/Kconfig.defconfig b/soc/atmel/sam/samv71/Kconfig.defconfig
deleted file mode 100644
index 2eefe71ec55..00000000000
--- a/soc/atmel/sam/samv71/Kconfig.defconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# Atmel SAM V71 MCU series configuration options
-
-# Copyright (c) 2016 Piotr Mienkowski
-# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_SAMV71
-
-config NUM_IRQS
-	default 74 if SOC_ATMEL_SAMV71_REVB
-	default 71
-
-endif # SOC_SERIES_SAMV71
diff --git a/soc/atmel/sam/samv71/Kconfig.soc b/soc/atmel/sam/samv71/Kconfig.soc
deleted file mode 100644
index 180ed60c49d..00000000000
--- a/soc/atmel/sam/samv71/Kconfig.soc
+++ /dev/null
@@ -1,122 +0,0 @@
-# Atmel SAM V71 MCU series
-
-# Copyright (c) 2016 Piotr Mienkowski
-# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_SAMV71
-	bool
-	select SOC_FAMILY_ATMEL_SAM
-	help
-	  Enable support for Atmel SAM V71 ARM Cortex-M7 Microcontrollers.
-	  Part No.: SAMV71J19, SAMV71J20, SAMV71J21, SAMV71N19, SAMV71N20,
-	  SAMV71N21, SAMV71Q19, SAMV71Q20, SAMV71Q21, SAMV71J19B, SAMV71J20B,
-	  SAMV71J21B, SAMV71N19B, SAMV71N20B, SAMV71N21B, SAMV71Q19B,
-	  SAMV71Q20B, SAMV71Q21B
-
-config SOC_ATMEL_SAMV71_REVB
-	bool
-
-config SOC_SERIES
-	default "samv71" if SOC_SERIES_SAMV71
-
-config SOC_SAMV71J19
-	bool
-	select SOC_SERIES_SAMV71
-
-config SOC_SAMV71J20
-	bool
-	select SOC_SERIES_SAMV71
-
-config SOC_SAMV71J21
-	bool
-	select SOC_SERIES_SAMV71
-
-config SOC_SAMV71N19
-	bool
-	select SOC_SERIES_SAMV71
-
-config SOC_SAMV71N20
-	bool
-	select SOC_SERIES_SAMV71
-
-config SOC_SAMV71N21
-	bool
-	select SOC_SERIES_SAMV71
-
-config SOC_SAMV71Q19
-	bool
-	select SOC_SERIES_SAMV71
-
-config SOC_SAMV71Q20
-	bool
-	select SOC_SERIES_SAMV71
-
-config SOC_SAMV71Q21
-	bool
-	select SOC_SERIES_SAMV71
-
-config SOC_SAMV71J19B
-	bool
-	select SOC_SERIES_SAMV71
-	select SOC_ATMEL_SAMV71_REVB
-
-config SOC_SAMV71J20B
-	bool
-	select SOC_SERIES_SAMV71
-	select SOC_ATMEL_SAMV71_REVB
-
-config SOC_SAMV71J21B
-	bool
-	select SOC_SERIES_SAMV71
-	select SOC_ATMEL_SAMV71_REVB
-
-config SOC_SAMV71N19B
-	bool
-	select SOC_SERIES_SAMV71
-	select SOC_ATMEL_SAMV71_REVB
-
-config SOC_SAMV71N20B
-	bool
-	select SOC_SERIES_SAMV71
-	select SOC_ATMEL_SAMV71_REVB
-
-config SOC_SAMV71N21B
-	bool
-	select SOC_SERIES_SAMV71
-	select SOC_ATMEL_SAMV71_REVB
-
-config SOC_SAMV71Q19B
-	bool
-	select SOC_SERIES_SAMV71
-	select SOC_ATMEL_SAMV71_REVB
-
-config SOC_SAMV71Q20B
-	bool
-	select SOC_SERIES_SAMV71
-	select SOC_ATMEL_SAMV71_REVB
-
-config SOC_SAMV71Q21B
-	bool
-	select SOC_SERIES_SAMV71
-	select SOC_ATMEL_SAMV71_REVB
-
-config SOC
-	default "samv71j19" if SOC_SAMV71J19
-	default "samv71j20" if SOC_SAMV71J20
-	default "samv71j21" if SOC_SAMV71J21
-	default "samv71n19" if SOC_SAMV71N19
-	default "samv71n20" if SOC_SAMV71N20
-	default "samv71n21" if SOC_SAMV71N21
-	default "samv71q19" if SOC_SAMV71Q19
-	default "samv71q20" if SOC_SAMV71Q20
-	default "samv71q21" if SOC_SAMV71Q21
-	default "samv71j19b" if SOC_SAMV71J19B
-	default "samv71j20b" if SOC_SAMV71J20B
-	default "samv71j21b" if SOC_SAMV71J21B
-	default "samv71n19b" if SOC_SAMV71N19B
-	default "samv71n20b" if SOC_SAMV71N20B
-	default "samv71n21b" if SOC_SAMV71N21B
-	default "samv71q19b" if SOC_SAMV71Q19B
-	default "samv71q20b" if SOC_SAMV71Q20B
-	default "samv71q21b" if SOC_SAMV71Q21B
diff --git a/soc/atmel/sam/samv71/soc.c b/soc/atmel/sam/samv71/soc.c
deleted file mode 100644
index a69713167f7..00000000000
--- a/soc/atmel/sam/samv71/soc.c
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * Copyright (c) 2016 Piotr Mienkowski
- * Copyright (c) 2019-2023 Gerson Fernando Budke <nandojve@gmail.com>
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/** @file
- * @brief Atmel SAM V71 MCU initialization code
- *
- * This file provides routines to initialize and support board-level hardware
- * for the Atmel SAM V71 MCU.
- */
-
-#include <zephyr/kernel.h>
-#include <zephyr/device.h>
-#include <zephyr/init.h>
-#include <zephyr/cache.h>
-#include <zephyr/arch/cache.h>
-#include <soc.h>
-#include <cmsis_core.h>
-#include <zephyr/logging/log.h>
-
-#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
-LOG_MODULE_REGISTER(soc);
-
-/**
- * @brief Setup various clocks on SoC at boot time.
- *
- * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
- * It is assumed that the relevant registers are at their reset value.
- */
-static ALWAYS_INLINE void clock_init(void)
-{
-	/* Switch the main clock to the internal OSC with 12MHz */
-	soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ);
-
-	/* Switch MCK (Master Clock) to the main clock */
-	soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK);
-
-	EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE;
-
-	soc_pmc_enable_clock_failure_detector();
-
-	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) {
-		soc_supc_slow_clock_select_crystal_osc();
-	}
-
-
-	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
-		/*
-		 * Setup main external crystal oscillator.
-		 */
-
-		/* We select maximum setup time.
-		 * While start up time could be shortened
-		 * this optimization is not deemed
-		 * critical now.
-		 */
-		soc_pmc_switch_mainck_to_xtal(false, 0xff);
-	}
-
-	/*
-	 * Set FWS (Flash Wait State) value before increasing Master Clock
-	 * (MCK) frequency.
-	 * TODO: set FWS based on the actual MCK frequency and VDDIO value
-	 * rather than maximum supported 150 MHz at standard VDDIO=2.7V
-	 */
-	EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE;
-
-	/*
-	 * Setup PLLA
-	 */
-
-	/*
-	 * PLL clock = Main * (MULA + 1) / DIVA
-	 *
-	 * By default, MULA == 24, DIVA == 1.
-	 * With main crystal running at 12 MHz,
-	 * PLL = 12 * (24 + 1) / 1 = 300 MHz
-	 *
-	 * With Processor Clock prescaler at 1
-	 * Processor Clock (HCLK)=300 MHz.
-	 */
-	soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu,
-			      CONFIG_SOC_ATMEL_SAM_PLLA_DIVA);
-
-
-	soc_pmc_enable_upllck(0x3Fu);
-
-	/*
-	 * Final setup of the Master Clock
-	 */
-
-	/* Setting PLLA as MCK, first prescaler, then divider and source last */
-	soc_pmc_mck_set_prescaler(1);
-	soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAM_MDIV);
-	soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
-
-	/* Disable internal fast RC if we have an external crystal oscillator */
-	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
-		soc_pmc_osc_disable_fastrc();
-	}
-}
-
-void soc_reset_hook(void)
-{
-	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
-		/*
-		 * Instruct CPU to enter Wait mode instead of Sleep mode to
-		 * keep Processor Clock (HCLK) and thus be able to debug
-		 * CPU using JTAG.
-		 */
-		soc_pmc_enable_waitmode();
-	}
-
-	/*
-	 * DTCM is enabled by default at reset, therefore we have to disable
-	 * it first to get the caches into a state where then the
-	 * sys_cache*-functions can enable them, if requested by the
-	 * configuration.
-	 */
-	SCB_InvalidateDCache();
-	SCB_DisableDCache();
-
-	/*
-	 * Enable the caches only if configured to do so.
-	 */
-	sys_cache_instr_enable();
-	sys_cache_data_enable();
-
-	/* Setup system clocks */
-	clock_init();
-}
-
-extern void atmel_samv71_config(void);
-/**
- * @brief Perform basic hardware initialization at boot.
- *
- * This needs to be run at the very beginning.
- */
-void soc_early_init_hook(void)
-{
-	/* Check that the CHIP CIDR matches the HAL one */
-	if (CHIPID->CHIPID_CIDR != CHIP_CIDR) {
-		LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x",
-			(uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR);
-	}
-	atmel_samv71_config();
-}
diff --git a/soc/atmel/sam/samv71/soc.h b/soc/atmel/sam/samv71/soc.h
deleted file mode 100644
index 8b54125bce5..00000000000
--- a/soc/atmel/sam/samv71/soc.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright (c) 2016 Piotr Mienkowski
- * Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/** @file
- * @brief Register access macros for the Atmel SAM V71 MCU.
- *
- * This file provides register access macros for the Atmel SAM V71 MCU, HAL
- * drivers for core peripherals as well as symbols specific to Atmel SAM family.
- */
-
-#ifndef _SOC_ATMEL_SAM_SAMV71_SOC_H_
-#define _SOC_ATMEL_SAM_SAMV71_SOC_H_
-
-#include <zephyr/sys/util.h>
-
-#ifndef _ASMLANGUAGE
-
-#define DONT_USE_CMSIS_INIT
-#define DONT_USE_PREDEFINED_CORE_HANDLERS
-#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
-
-#if defined(CONFIG_SOC_SAMV71J19)
-#include <samv71j19.h>
-#elif defined(CONFIG_SOC_SAMV71J20)
-#include <samv71j20.h>
-#elif defined(CONFIG_SOC_SAMV71J21)
-#include <samv71j21.h>
-#elif defined(CONFIG_SOC_SAMV71N19)
-#include <samv71n19.h>
-#elif defined(CONFIG_SOC_SAMV71N20)
-#include <samv71n20.h>
-#elif defined(CONFIG_SOC_SAMV71N21)
-#include <samv71n21.h>
-#elif defined(CONFIG_SOC_SAMV71Q19)
-#include <samv71q19.h>
-#elif defined(CONFIG_SOC_SAMV71Q20)
-#include <samv71q20.h>
-#elif defined(CONFIG_SOC_SAMV71Q21)
-#include <samv71q21.h>
-#elif defined(CONFIG_SOC_SAMV71J19B)
-#include <samv71j19b.h>
-#elif defined(CONFIG_SOC_SAMV71J20B)
-#include <samv71j20b.h>
-#elif defined(CONFIG_SOC_SAMV71J21B)
-#include <samv71j21b.h>
-#elif defined(CONFIG_SOC_SAMV71N19B)
-#include <samv71n19b.h>
-#elif defined(CONFIG_SOC_SAMV71N20B)
-#include <samv71n20b.h>
-#elif defined(CONFIG_SOC_SAMV71N21B)
-#include <samv71n21b.h>
-#elif defined(CONFIG_SOC_SAMV71Q19B)
-#include <samv71q19b.h>
-#elif defined(CONFIG_SOC_SAMV71Q20B)
-#include <samv71q20b.h>
-#elif defined(CONFIG_SOC_SAMV71Q21B)
-#include <samv71q21b.h>
-#else
-  #error Library does not support the specified device.
-#endif
-
-#include "../common/soc_pmc.h"
-#include "../common/soc_gpio.h"
-#include "../common/soc_supc.h"
-#include "../common/atmel_sam_dt.h"
-
-/** Processor Clock (HCLK) Frequency */
-#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ
-
-/** Master Clock (MCK) Frequency */
-#define SOC_ATMEL_SAM_MCK_FREQ_HZ \
-	(SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAM_MDIV)
-
-/** UTMI PLL clock (UPLLCK) Frequency */
-#define SOC_ATMEL_SAM_UPLLCK_FREQ_HZ MHZ(480)
-
-#endif /* _ASMLANGUAGE */
-
-#include "pwm_fixup.h"
-
-#endif /* _SOC_ATMEL_SAM_SAMV71_SOC_H_ */
diff --git a/soc/atmel/sam/samv71/soc_config.c b/soc/atmel/sam/samv71/soc_config.c
deleted file mode 100644
index 85a07e6b6b1..00000000000
--- a/soc/atmel/sam/samv71/soc_config.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (c) 2016 Piotr Mienkowski
- * Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/** @file
- * @brief System module to support early Atmel SAM V71 MCU configuration
- */
-
-#include <zephyr/device.h>
-#include <zephyr/init.h>
-#include <soc.h>
-#include <zephyr/arch/cpu.h>
-
-/**
- * @brief Perform SoC configuration at boot.
- *
- * This should be run early during the boot process but after basic hardware
- * initialization is done.
- */
-void atmel_samv71_config(void)
-{
-	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_DISABLE_ERASE_PIN)) {
-		/* Disable ERASE function on PB12 pin, this is controlled
-		 * by Bus Matrix
-		 */
-		MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12;
-	}
-
-	/* In Cortex-M based SoCs JTAG interface can be used to perform
-	 * IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug
-	 * interface therefore there is no harm done by disabling the JTAG TDI
-	 * pin by default.
-	 */
-	/* Disable TDI function on PB4 pin, this is controlled by Bus Matrix
-	 */
-	MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4;
-
-	if (IS_ENABLED(CONFIG_LOG_BACKEND_SWO)) {
-		/* Disable PCK3 clock used by ETM module */
-		PMC->PMC_SCDR = PMC_SCDR_PCK3;
-		while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) {
-			;
-		}
-		/* Select PLLA clock as PCK3 clock */
-		PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK;
-		/* Enable PCK3 clock */
-		PMC->PMC_SCER = PMC_SCER_PCK3;
-		/* Wait for PCK3 setup to complete */
-		while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) {
-			;
-		}
-		/* Enable TDO/TRACESWO function on PB5 pin */
-		MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5;
-	} else {
-		/* Disable TDO/TRACESWO function on PB5 pin */
-		MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5;
-	}
-}
diff --git a/soc/atmel/sam/same70/CMakeLists.txt b/soc/atmel/sam/samx7x/CMakeLists.txt
similarity index 100%
rename from soc/atmel/sam/same70/CMakeLists.txt
rename to soc/atmel/sam/samx7x/CMakeLists.txt
diff --git a/soc/atmel/sam/samx7x/Kconfig b/soc/atmel/sam/samx7x/Kconfig
new file mode 100644
index 00000000000..cd685170db9
--- /dev/null
+++ b/soc/atmel/sam/samx7x/Kconfig
@@ -0,0 +1,20 @@
+# Atmel SAM E70/S70/V70/V71 MCU series
+
+# Copyright (c) 2016 Piotr Mienkowski
+# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_SAMX7X
+	select ARM
+	select CPU_CORTEX_M7
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU_DOUBLE_PRECISION
+	select CPU_HAS_ICACHE
+	select CPU_HAS_DCACHE
+	select INIT_ARCH_HW_AT_BOOT
+	select SOC_RESET_HOOK
+	select HAS_SWO
+	select XIP
+	select HAS_POWEROFF
+	select SOC_EARLY_INIT_HOOK
diff --git a/soc/atmel/sam/samx7x/Kconfig.defconfig b/soc/atmel/sam/samx7x/Kconfig.defconfig
new file mode 100644
index 00000000000..7c9de5a3e81
--- /dev/null
+++ b/soc/atmel/sam/samx7x/Kconfig.defconfig
@@ -0,0 +1,14 @@
+# Atmel SAM E70/S70/V70/V71 MCU series configuration options
+
+# Copyright (c) 2016 Piotr Mienkowski
+# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_SAMX7X
+
+config NUM_IRQS
+	default 74 if SOC_ATMEL_SAME70_REVB
+	default 74 if SOC_ATMEL_SAMV71_REVB
+	default 71
+
+endif # SOC_SERIES_SAMX7X
diff --git a/soc/atmel/sam/samx7x/Kconfig.soc b/soc/atmel/sam/samx7x/Kconfig.soc
new file mode 100644
index 00000000000..296cc75e006
--- /dev/null
+++ b/soc/atmel/sam/samx7x/Kconfig.soc
@@ -0,0 +1,17 @@
+# Atmel SAM E70/S70/V70/V71 MCU series
+
+# Copyright (c) 2016 Piotr Mienkowski
+# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
+# Copyright (c) 2024 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_SAMX7X
+	bool
+	select SOC_FAMILY_ATMEL_SAM
+	help
+	  Enable support for Atmel SAM E70/S70/V70/V71 ARM Cortex-M7 Microcontrollers.
+
+config SOC_SERIES
+	default "samx7x" if SOC_SERIES_SAMX7X
+
+rsource "Kconfig.soc.sam*"
diff --git a/soc/atmel/sam/samx7x/Kconfig.soc.same70 b/soc/atmel/sam/samx7x/Kconfig.soc.same70
new file mode 100644
index 00000000000..341bf827b28
--- /dev/null
+++ b/soc/atmel/sam/samx7x/Kconfig.soc.same70
@@ -0,0 +1,106 @@
+# Atmel SAM E70 MCU series
+
+# Copyright (c) 2016 Piotr Mienkowski
+# Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
+# Copyright (c) 2024 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_ATMEL_SAME70
+	select SOC_SERIES_SAMX7X
+	bool
+
+config SOC_ATMEL_SAME70_REVB
+	select SOC_SERIES_SAMX7X
+	bool
+
+config SOC_SAME70J19
+	bool
+	select SOC_ATMEL_SAME70
+
+config SOC_SAME70J20
+	bool
+	select SOC_ATMEL_SAME70
+
+config SOC_SAME70J21
+	bool
+	select SOC_ATMEL_SAME70
+
+config SOC_SAME70N19
+	bool
+	select SOC_ATMEL_SAME70
+
+config SOC_SAME70N20
+	bool
+	select SOC_ATMEL_SAME70
+
+config SOC_SAME70N21
+	bool
+	select SOC_ATMEL_SAME70
+
+config SOC_SAME70Q19
+	bool
+	select SOC_ATMEL_SAME70
+
+config SOC_SAME70Q20
+	bool
+	select SOC_ATMEL_SAME70
+
+config SOC_SAME70Q21
+	bool
+	select SOC_ATMEL_SAME70
+
+config SOC_SAME70J19B
+	bool
+	select SOC_ATMEL_SAME70_REVB
+
+config SOC_SAME70J20B
+	bool
+	select SOC_ATMEL_SAME70_REVB
+
+config SOC_SAME70J21B
+	bool
+	select SOC_ATMEL_SAME70_REVB
+
+config SOC_SAME70N19B
+	bool
+	select SOC_ATMEL_SAME70_REVB
+
+config SOC_SAME70N20B
+	bool
+	select SOC_ATMEL_SAME70_REVB
+
+config SOC_SAME70N21B
+	bool
+	select SOC_ATMEL_SAME70_REVB
+
+config SOC_SAME70Q19B
+	bool
+	select SOC_ATMEL_SAME70_REVB
+
+config SOC_SAME70Q20B
+	bool
+	select SOC_ATMEL_SAME70_REVB
+
+config SOC_SAME70Q21B
+	bool
+	select SOC_ATMEL_SAME70_REVB
+
+config SOC
+	default "same70j19" if SOC_SAME70J19
+	default "same70j20" if SOC_SAME70J20
+	default "same70j21" if SOC_SAME70J21
+	default "same70n19" if SOC_SAME70N19
+	default "same70n20" if SOC_SAME70N20
+	default "same70n21" if SOC_SAME70N21
+	default "same70q19" if SOC_SAME70Q19
+	default "same70q20" if SOC_SAME70Q20
+	default "same70q21" if SOC_SAME70Q21
+	default "same70j19b" if SOC_SAME70J19B
+	default "same70j20b" if SOC_SAME70J20B
+	default "same70j21b" if SOC_SAME70J21B
+	default "same70n19b" if SOC_SAME70N19B
+	default "same70n20b" if SOC_SAME70N20B
+	default "same70n21b" if SOC_SAME70N21B
+	default "same70q19b" if SOC_SAME70Q19B
+	default "same70q20b" if SOC_SAME70Q20B
+	default "same70q21b" if SOC_SAME70Q21B
diff --git a/soc/atmel/sam/samx7x/Kconfig.soc.samv71 b/soc/atmel/sam/samx7x/Kconfig.soc.samv71
new file mode 100644
index 00000000000..9a1b59dcb81
--- /dev/null
+++ b/soc/atmel/sam/samx7x/Kconfig.soc.samv71
@@ -0,0 +1,106 @@
+# Atmel SAM V71 MCU series
+
+# Copyright (c) 2016 Piotr Mienkowski
+# Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
+# Copyright (c) 2024 Henrik Brix Andersen <henrik@brixandersen.dk>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_ATMEL_SAMV71
+	bool
+	select SOC_SERIES_SAMX7X
+
+config SOC_ATMEL_SAMV71_REVB
+	bool
+	select SOC_SERIES_SAMX7X
+
+config SOC_SAMV71J19
+	bool
+	select SOC_ATMEL_SAMV71
+
+config SOC_SAMV71J20
+	bool
+	select SOC_ATMEL_SAMV71
+
+config SOC_SAMV71J21
+	bool
+	select SOC_ATMEL_SAMV71
+
+config SOC_SAMV71N19
+	bool
+	select SOC_ATMEL_SAMV71
+
+config SOC_SAMV71N20
+	bool
+	select SOC_ATMEL_SAMV71
+
+config SOC_SAMV71N21
+	bool
+	select SOC_ATMEL_SAMV71
+
+config SOC_SAMV71Q19
+	bool
+	select SOC_ATMEL_SAMV71
+
+config SOC_SAMV71Q20
+	bool
+	select SOC_ATMEL_SAMV71
+
+config SOC_SAMV71Q21
+	bool
+	select SOC_ATMEL_SAMV71
+
+config SOC_SAMV71J19B
+	bool
+	select SOC_ATMEL_SAMV71_REVB
+
+config SOC_SAMV71J20B
+	bool
+	select SOC_ATMEL_SAMV71_REVB
+
+config SOC_SAMV71J21B
+	bool
+	select SOC_ATMEL_SAMV71_REVB
+
+config SOC_SAMV71N19B
+	bool
+	select SOC_ATMEL_SAMV71_REVB
+
+config SOC_SAMV71N20B
+	bool
+	select SOC_ATMEL_SAMV71_REVB
+
+config SOC_SAMV71N21B
+	bool
+	select SOC_ATMEL_SAMV71_REVB
+
+config SOC_SAMV71Q19B
+	bool
+	select SOC_ATMEL_SAMV71_REVB
+
+config SOC_SAMV71Q20B
+	bool
+	select SOC_ATMEL_SAMV71_REVB
+
+config SOC_SAMV71Q21B
+	bool
+	select SOC_ATMEL_SAMV71_REVB
+
+config SOC
+	default "samv71j19" if SOC_SAMV71J19
+	default "samv71j20" if SOC_SAMV71J20
+	default "samv71j21" if SOC_SAMV71J21
+	default "samv71n19" if SOC_SAMV71N19
+	default "samv71n20" if SOC_SAMV71N20
+	default "samv71n21" if SOC_SAMV71N21
+	default "samv71q19" if SOC_SAMV71Q19
+	default "samv71q20" if SOC_SAMV71Q20
+	default "samv71q21" if SOC_SAMV71Q21
+	default "samv71j19b" if SOC_SAMV71J19B
+	default "samv71j20b" if SOC_SAMV71J20B
+	default "samv71j21b" if SOC_SAMV71J21B
+	default "samv71n19b" if SOC_SAMV71N19B
+	default "samv71n20b" if SOC_SAMV71N20B
+	default "samv71n21b" if SOC_SAMV71N21B
+	default "samv71q19b" if SOC_SAMV71Q19B
+	default "samv71q20b" if SOC_SAMV71Q20B
+	default "samv71q21b" if SOC_SAMV71Q21B
diff --git a/soc/atmel/sam/samx7x/soc.c b/soc/atmel/sam/samx7x/soc.c
new file mode 100644
index 00000000000..60586491710
--- /dev/null
+++ b/soc/atmel/sam/samx7x/soc.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2016 Piotr Mienkowski
+ * Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/** @file
+ * @brief Atmel SAM E70/S70/V70/V71 MCU series initialization code
+ *
+ * This file provides routines to initialize and support board-level hardware
+ * for the Atmel SAM E70/S70/V70/V71 MCU series.
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/cache.h>
+#include <zephyr/arch/cache.h>
+#include <soc.h>
+#include <soc_pmc.h>
+#include <soc_supc.h>
+#include <cmsis_core.h>
+#include <zephyr/logging/log.h>
+
+#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
+LOG_MODULE_REGISTER(soc);
+
+/**
+ * @brief Setup various clocks on SoC at boot time.
+ *
+ * Setup Slow, Main, PLLA, Processor and Master clocks during the device boot.
+ * It is assumed that the relevant registers are at their reset value.
+ */
+static ALWAYS_INLINE void clock_init(void)
+{
+	/* Switch the main clock to the internal OSC with 12MHz */
+	soc_pmc_switch_mainck_to_fastrc(SOC_PMC_FAST_RC_FREQ_12MHZ);
+
+	/* Switch MCK (Master Clock) to the main clock */
+	soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_MAIN_CLK);
+
+	EFC->EEFC_FMR = EEFC_FMR_FWS(0) | EEFC_FMR_CLOE;
+
+	soc_pmc_enable_clock_failure_detector();
+
+	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_SLCK)) {
+		soc_supc_slow_clock_select_crystal_osc();
+	}
+
+	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
+		/*
+		 * Setup main external crystal oscillator.
+		 */
+
+		/* We select maximum setup time.
+		 * While start up time could be shortened
+		 * this optimization is not deemed
+		 * critical now.
+		 */
+		bool bypass = IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK_BYPASS);
+
+		soc_pmc_switch_mainck_to_xtal(bypass, 0xff);
+	}
+
+	/*
+	 * Set FWS (Flash Wait State) value before increasing Master Clock
+	 * (MCK) frequency.
+	 * TODO: set FWS based on the actual MCK frequency and VDDIO value
+	 * rather than maximum supported 150 MHz at standard VDDIO=2.7V
+	 */
+	EFC->EEFC_FMR = EEFC_FMR_FWS(5) | EEFC_FMR_CLOE;
+
+	/*
+	 * Setup PLLA
+	 */
+
+	/*
+	 * PLL clock = Main * (MULA + 1) / DIVA
+	 *
+	 * By default, MULA == 24, DIVA == 1.
+	 * With main crystal running at 12 MHz,
+	 * PLL = 12 * (24 + 1) / 1 = 300 MHz
+	 *
+	 * With Processor Clock prescaler at 1
+	 * Processor Clock (HCLK)=300 MHz.
+	 */
+	soc_pmc_enable_pllack(CONFIG_SOC_ATMEL_SAM_PLLA_MULA, 0x3Fu,
+			      CONFIG_SOC_ATMEL_SAM_PLLA_DIVA);
+
+	soc_pmc_enable_upllck(0x3Fu);
+
+	/*
+	 * Final setup of the Master Clock
+	 */
+
+	/* Setting PLLA as MCK, first prescaler, then divider and source last */
+	soc_pmc_mck_set_prescaler(1);
+	soc_pmc_mck_set_divider(CONFIG_SOC_ATMEL_SAM_MDIV);
+	soc_pmc_mck_set_source(SOC_PMC_MCK_SRC_PLLA_CLK);
+
+	/* Disable internal fast RC if we have an external crystal oscillator */
+	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_EXT_MAINCK)) {
+		soc_pmc_osc_disable_fastrc();
+	}
+}
+
+void soc_reset_hook(void)
+{
+	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_WAIT_MODE)) {
+		/*
+		 * Instruct CPU to enter Wait mode instead of Sleep mode to
+		 * keep Processor Clock (HCLK) and thus be able to debug
+		 * CPU using JTAG.
+		 */
+		soc_pmc_enable_waitmode();
+	}
+
+	/*
+	 * DTCM is enabled by default at reset, therefore we have to disable
+	 * it first to get the caches into a state where then the
+	 * sys_cache*-functions can enable them, if requested by the
+	 * configuration.
+	 */
+	SCB_InvalidateDCache();
+	SCB_DisableDCache();
+
+	/*
+	 * Enable the caches only if configured to do so.
+	 */
+	sys_cache_instr_enable();
+	sys_cache_data_enable();
+
+	/* Setup system clocks */
+	clock_init();
+}
+
+extern void atmel_samx7x_config(void);
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run at the very beginning.
+ */
+void soc_early_init_hook(void)
+{
+	/* Check that the CHIP CIDR matches the HAL one */
+	if (CHIPID->CHIPID_CIDR != CHIP_CIDR) {
+		LOG_WRN("CIDR mismatch: chip = 0x%08x vs HAL = 0x%08x",
+			(uint32_t)CHIPID->CHIPID_CIDR, (uint32_t)CHIP_CIDR);
+	}
+
+	atmel_samx7x_config();
+}
diff --git a/soc/atmel/sam/samx7x/soc.h b/soc/atmel/sam/samx7x/soc.h
new file mode 100644
index 00000000000..ddd3d5a2e31
--- /dev/null
+++ b/soc/atmel/sam/samx7x/soc.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2016 Piotr Mienkowski
+ * Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/** @file
+ * @brief Register access macros for the Atmel SAM E70/S70/V70/V71 MCU series.
+ *
+ * This file provides register access macros for the Atmel SAM E70/S70/V70/V71 MCU series, HAL
+ * drivers for core peripherals as well as symbols specific to this Atmel SAM family.
+ */
+
+#ifndef _SOC_ATMEL_SAM_SAMX7X_SOC_H_
+#define _SOC_ATMEL_SAM_SAMX7X_SOC_H_
+
+#include <zephyr/sys/util.h>
+
+#ifndef _ASMLANGUAGE
+
+#define DONT_USE_CMSIS_INIT
+#define DONT_USE_PREDEFINED_CORE_HANDLERS
+#define DONT_USE_PREDEFINED_PERIPHERALS_HANDLERS
+
+#if defined(CONFIG_SOC_SAME70J19)
+#include <same70j19.h>
+#elif defined(CONFIG_SOC_SAME70J20)
+#include <same70j20.h>
+#elif defined(CONFIG_SOC_SAME70J21)
+#include <same70j21.h>
+#elif defined(CONFIG_SOC_SAME70N19)
+#include <same70n19.h>
+#elif defined(CONFIG_SOC_SAME70N20)
+#include <same70n20.h>
+#elif defined(CONFIG_SOC_SAME70N21)
+#include <same70n21.h>
+#elif defined(CONFIG_SOC_SAME70Q19)
+#include <same70q19.h>
+#elif defined(CONFIG_SOC_SAME70Q20)
+#include <same70q20.h>
+#elif defined(CONFIG_SOC_SAME70Q21)
+#include <same70q21.h>
+#elif defined(CONFIG_SOC_SAME70J19B)
+#include <same70j19b.h>
+#elif defined(CONFIG_SOC_SAME70J20B)
+#include <same70j20b.h>
+#elif defined(CONFIG_SOC_SAME70J21B)
+#include <same70j21b.h>
+#elif defined(CONFIG_SOC_SAME70N19B)
+#include <same70n19b.h>
+#elif defined(CONFIG_SOC_SAME70N20B)
+#include <same70n20b.h>
+#elif defined(CONFIG_SOC_SAME70N21B)
+#include <same70n21b.h>
+#elif defined(CONFIG_SOC_SAME70Q19B)
+#include <same70q19b.h>
+#elif defined(CONFIG_SOC_SAME70Q20B)
+#include <same70q20b.h>
+#elif defined(CONFIG_SOC_SAME70Q21B)
+#include <same70q21b.h>
+#elif defined(CONFIG_SOC_SAMV71J19)
+#include <samv71j19.h>
+#elif defined(CONFIG_SOC_SAMV71J20)
+#include <samv71j20.h>
+#elif defined(CONFIG_SOC_SAMV71J21)
+#include <samv71j21.h>
+#elif defined(CONFIG_SOC_SAMV71N19)
+#include <samv71n19.h>
+#elif defined(CONFIG_SOC_SAMV71N20)
+#include <samv71n20.h>
+#elif defined(CONFIG_SOC_SAMV71N21)
+#include <samv71n21.h>
+#elif defined(CONFIG_SOC_SAMV71Q19)
+#include <samv71q19.h>
+#elif defined(CONFIG_SOC_SAMV71Q20)
+#include <samv71q20.h>
+#elif defined(CONFIG_SOC_SAMV71Q21)
+#include <samv71q21.h>
+#elif defined(CONFIG_SOC_SAMV71J19B)
+#include <samv71j19b.h>
+#elif defined(CONFIG_SOC_SAMV71J20B)
+#include <samv71j20b.h>
+#elif defined(CONFIG_SOC_SAMV71J21B)
+#include <samv71j21b.h>
+#elif defined(CONFIG_SOC_SAMV71N19B)
+#include <samv71n19b.h>
+#elif defined(CONFIG_SOC_SAMV71N20B)
+#include <samv71n20b.h>
+#elif defined(CONFIG_SOC_SAMV71N21B)
+#include <samv71n21b.h>
+#elif defined(CONFIG_SOC_SAMV71Q19B)
+#include <samv71q19b.h>
+#elif defined(CONFIG_SOC_SAMV71Q20B)
+#include <samv71q20b.h>
+#elif defined(CONFIG_SOC_SAMV71Q21B)
+#include <samv71q21b.h>
+#else
+  #error Library does not support the specified device.
+#endif
+
+#include "../common/soc_pmc.h"
+#include "../common/soc_gpio.h"
+#include "../common/soc_supc.h"
+#include "../common/atmel_sam_dt.h"
+
+/** Processor Clock (HCLK) Frequency */
+#define SOC_ATMEL_SAM_HCLK_FREQ_HZ ATMEL_SAM_DT_CPU_CLK_FREQ_HZ
+
+/** Master Clock (MCK) Frequency */
+#define SOC_ATMEL_SAM_MCK_FREQ_HZ \
+	(SOC_ATMEL_SAM_HCLK_FREQ_HZ / CONFIG_SOC_ATMEL_SAM_MDIV)
+
+/** UTMI PLL clock (UPLLCK) Frequency */
+#define SOC_ATMEL_SAM_UPLLCK_FREQ_HZ MHZ(480)
+
+#endif /* _ASMLANGUAGE */
+
+#endif /* _SOC_ATMEL_SAM_SAMX7X_SOC_H_ */
diff --git a/soc/atmel/sam/samx7x/soc_config.c b/soc/atmel/sam/samx7x/soc_config.c
new file mode 100644
index 00000000000..613a88e1ace
--- /dev/null
+++ b/soc/atmel/sam/samx7x/soc_config.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2016 Piotr Mienkowski
+ * Copyright (c) 2019-2024 Gerson Fernando Budke <nandojve@gmail.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/** @file
+ * @brief System module to support early Atmel SAM E70/S70/V70/V71 MCU series configuration
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <soc.h>
+#include <zephyr/arch/cpu.h>
+
+/**
+ * @brief Perform SoC configuration at boot.
+ *
+ * This should be run early during the boot process but after basic hardware
+ * initialization is done.
+ */
+void atmel_samx7x_config(void)
+{
+	if (IS_ENABLED(CONFIG_SOC_ATMEL_SAM_DISABLE_ERASE_PIN)) {
+		/* Disable ERASE function on PB12 pin, this is controlled
+		 * by Bus Matrix
+		 */
+		MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO12;
+	}
+
+	/* In Cortex-M based SoCs JTAG interface can be used to perform
+	 * IEEE1149.1 JTAG Boundary scan only. It can not be used as a debug
+	 * interface therefore there is no harm done by disabling the JTAG TDI
+	 * pin by default.
+	 */
+	/* Disable TDI function on PB4 pin, this is controlled by Bus Matrix
+	 */
+	MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO4;
+
+	if (IS_ENABLED(CONFIG_LOG_BACKEND_SWO)) {
+		/* Disable PCK3 clock used by ETM module */
+		PMC->PMC_SCDR = PMC_SCDR_PCK3;
+		while ((PMC->PMC_SCSR) & PMC_SCSR_PCK3) {
+			;
+		}
+		/* Select PLLA clock as PCK3 clock */
+		PMC->PMC_PCK[3] = PMC_MCKR_CSS_PLLA_CLK;
+		/* Enable PCK3 clock */
+		PMC->PMC_SCER = PMC_SCER_PCK3;
+		/* Wait for PCK3 setup to complete */
+		while (!((PMC->PMC_SR) & PMC_SR_PCKRDY3)) {
+			;
+		}
+		/* Enable TDO/TRACESWO function on PB5 pin */
+		MATRIX->CCFG_SYSIO &= ~CCFG_SYSIO_SYSIO5;
+	} else {
+		/* Disable TDO/TRACESWO function on PB5 pin */
+		MATRIX->CCFG_SYSIO |= CCFG_SYSIO_SYSIO5;
+	}
+}
diff --git a/soc/atmel/sam0/common/Kconfig.samd2x b/soc/atmel/sam0/common/Kconfig.samd2x
index f23b6557963..11f76f608a1 100644
--- a/soc/atmel/sam0/common/Kconfig.samd2x
+++ b/soc/atmel/sam0/common/Kconfig.samd2x
@@ -1,3 +1,4 @@
+# Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_SERIES_SAMD20 || SOC_SERIES_SAMD21 || SOC_SERIES_SAMR21
@@ -35,6 +36,21 @@ config SOC_ATMEL_SAMD_XOSC32K_CRYSTAL
 	  Enable the crystal oscillator (if disabled, expect a clock signal on
 	  XIN32).
 
+DT_ATMEL_RTC := $(dt_nodelabel_path,rtc)
+DT_ATMEL_RTC_COUNTER_CLOCK_MODE := $(dt_node_str_prop_equals,$(DT_ATMEL_RTC),counter-mode,clock)
+
+config SOC_ATMEL_SAMD_XOSC32K_PRESCALER
+	int "XOSC32 Generic Clock Prescaler"
+	range 1 512
+	default 32 if "$(DT_ATMEL_RTC_COUNTER_CLOCK_MODE)"
+	default 1
+	depends on SOC_ATMEL_SAMD_XOSC32K
+	help
+	  Configure the prescaler for the generic clock output
+	  connected on the xosc32. When using RTC in calendar mode
+	  the GCLK should be divided by 32 to RTC receive the
+	  1024 Hz reference clock.
+
 config SOC_ATMEL_SAMD_XOSC
 	bool "External 0.4..32 MHz clock source"
 	help
diff --git a/soc/atmel/sam0/common/Kconfig.samd5x b/soc/atmel/sam0/common/Kconfig.samd5x
index 969887e99da..e18616862e1 100644
--- a/soc/atmel/sam0/common/Kconfig.samd5x
+++ b/soc/atmel/sam0/common/Kconfig.samd5x
@@ -1,4 +1,5 @@
 # Copyright (c) 2019 ML!PA Consulting GmbH
+# Copyright (c) 2024-2025 Gerson Fernando Budke <nandojve@gmail.com>
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_SERIES_SAMD51 || SOC_SERIES_SAME51 || SOC_SERIES_SAME53 || SOC_SERIES_SAME54
@@ -18,6 +19,34 @@ config SOC_ATMEL_SAMD5X_XOSC32K_STARTUP
 	help
 	  Selects the startup time for the external 32 kHz crystal oscillator.
 
+config SOC_ATMEL_SAMD5X_XOSC32K_CRYSTAL
+	bool "External 32.768 kHz clock is a crystal oscillator"
+	depends on SOC_ATMEL_SAMD5X_XOSC32K
+	default y
+	help
+	  Enable the crystal oscillator (if disabled, expect a clock
+	  signal on XIN32).
+
+config SOC_ATMEL_SAMD5X_XOSC32K_GAIN_HS
+	bool "XOSC32 High Speed gain"
+	depends on SOC_ATMEL_SAMD5X_XOSC32K
+	help
+	  When this option is selected the gain is set High Speed
+	  instead standard.
+
+DT_ATMEL_RTC := $(dt_nodelabel_path,rtc)
+DT_ATMEL_RTC_COUNTER_CLOCK_MODE := $(dt_node_str_prop_equals,$(DT_ATMEL_RTC),counter-mode,clock)
+
+config SOC_ATMEL_SAMD5X_OSC32K_PRESCALER
+	int "XOSC32 Generic Clock Prescaler"
+	range 1 512
+	default 32 if "$(DT_ATMEL_RTC_COUNTER_CLOCK_MODE)"
+	default 1
+	help
+	  Configure the prescaler for the generic clock output connected on the
+	  xosc32 or osculp32k. When using RTC in calendar mode the GCLK should
+	  be divided by 32 to RTC receive the 1024 Hz reference clock.
+
 choice
 	prompt "Main clock source"
 	default SOC_ATMEL_SAMD5X_DEFAULT_AS_MAIN
diff --git a/soc/atmel/sam0/common/atmel_sam0_dt.h b/soc/atmel/sam0/common/atmel_sam0_dt.h
index f803596c872..2c86808a9a1 100644
--- a/soc/atmel/sam0/common/atmel_sam0_dt.h
+++ b/soc/atmel/sam0/common/atmel_sam0_dt.h
@@ -1,6 +1,6 @@
 /*
- * Copyright (c) 2020 Linaro Ltd.
- * Copyright (c) 2021 Gerson Fernando Budke
+ * Copyright (c) 2020, Linaro Ltd.
+ * Copyright (c) 2021-2024, Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,12 +12,30 @@
 #ifndef _ATMEL_SAM0_DT_H_
 #define _ATMEL_SAM0_DT_H_
 
-/* Helper macro to get MCLK register address for corresponding
- * that has corresponding clock enable bit.
+/* clang-format off */
+
+#define ATMEL_SAM0_DT_INST_CELL_REG_ADDR_OFFSET(n, cell)		\
+	(volatile uint32_t *)						\
+	(DT_REG_ADDR(DT_INST_PHANDLE_BY_NAME(n, clocks, cell)) +	\
+	 DT_INST_CLOCKS_CELL_BY_NAME(n, cell, offset))
+
+#define ATMEL_SAM0_DT_INST_CELL_PERIPH_MASK(n, name, cell)		\
+	BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, name, cell))
+
+/* Helper macro to get register address that control peripheral clock
+ * enable bit.
  */
-#define MCLK_MASK_DT_INT_REG_ADDR(n) \
-	(DT_REG_ADDR(DT_INST_PHANDLE_BY_NAME(n, clocks, mclk)) + \
-	 DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, offset))
+#define ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n)			\
+	COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(mclk)),	\
+		(ATMEL_SAM0_DT_INST_CELL_REG_ADDR_OFFSET(n, mclk)),	\
+		(ATMEL_SAM0_DT_INST_CELL_REG_ADDR_OFFSET(n, pm)))
+
+/* Helper macro to get peripheral clock bit mask.
+ */
+#define ATMEL_SAM0_DT_INST_MCLK_PM_PERIPH_MASK(n, cell)			\
+	COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(mclk)),	\
+		(ATMEL_SAM0_DT_INST_CELL_PERIPH_MASK(n, mclk, cell)),	\
+		(ATMEL_SAM0_DT_INST_CELL_PERIPH_MASK(n, pm, cell)))
 
 /* Helper macros for use with ATMEL SAM0 DMAC controller
  * return 0xff as default value if there is no 'dmas' property
@@ -48,4 +66,340 @@
 #define ATMEL_SAM0_DT_CPU_CLK_FREQ_HZ \
 	DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
 
+/**
+ * @brief Test if a node has a atmel,assigned-clocks phandle-array property at
+ * a given index.
+ *
+ * This expands to 1 if the given index is valid atmel,assigned-clocks property
+ * phandle-array index. Otherwise, it expands to 0.
+ *
+ * Example devicetree fragment:
+ *
+ *     n1: node-1 {
+ *             atmel,assigned-clocks = <...>, <...>;
+ *     };
+ *
+ *     n2: node-2 {
+ *             atmel,assigned-clocks = <...>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     ATMEL_SAM0_DT_ASSIGNED_CLOCKS_HAS_IDX(DT_NODELABEL(n1), 0) // 1
+ *     ATMEL_SAM0_DT_ASSIGNED_CLOCKS_HAS_IDX(DT_NODELABEL(n1), 1) // 1
+ *     ATMEL_SAM0_DT_ASSIGNED_CLOCKS_HAS_IDX(DT_NODELABEL(n1), 2) // 0
+ *     ATMEL_SAM0_DT_ASSIGNED_CLOCKS_HAS_IDX(DT_NODELABEL(n2), 1) // 0
+ *
+ * @param node_id node identifier; may or may not have any atmel,assigned-clocks
+ *		  property
+ * @param idx index of a atmel,assigned-clocks property phandle-array whose
+ *            existence to check
+ * @return 1 if the index exists, 0 otherwise
+ */
+#define ATMEL_SAM0_DT_ASSIGNED_CLOCKS_HAS_IDX(node_id, idx) \
+	DT_PROP_HAS_IDX(node_id, atmel_assigned_clocks, idx)
+
+/**
+ * @brief Test if a node has a clock-names array property holds a given name
+ *
+ * This expands to 1 if the name is available as atmel,assigned-clocks-name array
+ * property cell. Otherwise, it expands to 0.
+ *
+ * Example devicetree fragment:
+ *
+ *     n1: node-1 {
+ *             atmel,assigned-clocks = <...>, <...>;
+ *             atmel,assigned-clock-names = "alpha", "beta";
+ *     };
+ *
+ *     n2: node-2 {
+ *             atmel,assigned-clocks = <...>;
+ *             atmel,assigned-clock-names = "alpha";
+ *     };
+ *
+ * Example usage:
+ *
+ *     ATMEL_SAM0_DT_ASSIGNED_CLOCKS_HAS_NAME(DT_NODELABEL(n1), alpha) // 1
+ *     ATMEL_SAM0_DT_ASSIGNED_CLOCKS_HAS_NAME(DT_NODELABEL(n1), beta)  // 1
+ *     ATMEL_SAM0_DT_ASSIGNED_CLOCKS_HAS_NAME(DT_NODELABEL(n2), beta)  // 0
+ *
+ * @param node_id node identifier; may or may not have any clock-names property.
+ * @param name lowercase-and-underscores clock-names cell value name to check
+ * @return 1 if the atmel,assigned-clock name exists, 0 otherwise
+ */
+#define ATMEL_SAM0_DT_ASSIGNED_CLOCKS_HAS_NAME(node_id, name) \
+	DT_PROP_HAS_NAME(node_id, atmel_assigned_clocks, name)
+
+/**
+ * @brief Get the number of elements in a atmel,assigned-clocks property
+ *
+ * Example devicetree fragment:
+ *
+ *     n1: node-1 {
+ *             atmel,assigned-clocks = <&foo>, <&bar>;
+ *     };
+ *
+ *     n2: node-2 {
+ *             atmel,assigned-clocks = <&foo>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     ATMEL_SAM0_DT_NUM_ASSIGNED_CLOCKS(DT_NODELABEL(n1)) // 2
+ *     ATMEL_SAM0_DT_NUM_ASSIGNED_CLOCKS(DT_NODELABEL(n2)) // 1
+ *
+ * @param node_id node identifier with a atmel,assigned-clocks property
+ * @return number of elements in the property
+ */
+#define ATMEL_SAM0_DT_NUM_ASSIGNED_CLOCKS(node_id) \
+	DT_PROP_LEN(node_id, atmel_assigned_clocks)
+
+
+/**
+ * @brief Get the node identifier for the controller phandle from a
+ *        "atmel,assigned-clocks" phandle-array property at an index
+ *
+ * Example devicetree fragment:
+ *
+ *     clk1: clock-controller@... { ... };
+ *
+ *     clk2: clock-controller@... { ... };
+ *
+ *     n: node {
+ *             atmel,assigned-clocks = <&clk1 10 20>, <&clk2 30 40>;
+ *     };
+ *
+ * Example usage:
+ *
+ *     ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(n), 0)) // DT_NODELABEL(clk1)
+ *     ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CTLR_BY_IDX(DT_NODELABEL(n), 1)) // DT_NODELABEL(clk2)
+ *
+ * @param node_id node identifier
+ * @param idx logical index into "atmel,assigned-clocks"
+ * @return the node identifier for the clock controller referenced at index "idx"
+ * @see DT_PHANDLE_BY_IDX()
+ */
+#define ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CTLR_BY_IDX(node_id, idx) \
+	DT_PHANDLE_BY_IDX(node_id, atmel_assigned_clocks, idx)
+
+/**
+ * @brief Equivalent to ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CTLR_BY_IDX(node_id, 0)
+ * @param node_id node identifier
+ * @return a node identifier for the atmel,assigned-clocks controller at index 0
+ *         in "atmel,assigned-clocks"
+ * @see ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CTLR_BY_IDX()
+ */
+#define ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CTLR(node_id) \
+	ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CTLR_BY_IDX(node_id, 0)
+
+/**
+ * @brief Get the node identifier for the controller phandle from a
+ *        atmel,assigned-clocks phandle-array property by name
+ *
+ * Example devicetree fragment:
+ *
+ *     clk1: clock-controller@... { ... };
+ *
+ *     clk2: clock-controller@... { ... };
+ *
+ *     n: node {
+ *             atmel,assigned-clocks = <&clk1 10 20>, <&clk2 30 40>;
+ *             atmel,assigned-clock-names = "alpha", "beta";
+ *     };
+ *
+ * Example usage:
+ *
+ *     ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CTLR_BY_NAME(DT_NODELABEL(n), beta) // DT_NODELABEL(clk2)
+ *
+ * @param node_id node identifier
+ * @param name lowercase-and-underscores name of a atmel,assigned-clocks element
+ *             as defined by the node's clock-names property
+ * @return the node identifier for the clock controller referenced by name
+ * @see DT_PHANDLE_BY_NAME()
+ */
+#define ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CTLR_BY_NAME(node_id, name) \
+	DT_PHANDLE_BY_NAME(node_id, atmel_assigned_clocks, name)
+
+/**
+ * @brief Get a atmel,assigned-clock specifier's cell value at an index
+ *
+ * Example devicetree fragment:
+ *
+ *     clk1: clock-controller@... {
+ *             compatible = "vnd,clock";
+ *             #atmel,assigned-clock-cells = < 2 >;
+ *     };
+ *
+ *     n: node {
+ *             atmel,assigned-clocks = < &clk1 10 20 >, < &clk1 30 40 >;
+ *     };
+ *
+ * Bindings fragment for the vnd,clock compatible:
+ *
+ *     atmel,assigned-clock-cells:
+ *       - bus
+ *       - bits
+ *
+ * Example usage:
+ *
+ *     ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CELL_BY_IDX(DT_NODELABEL(n), 0, bus) // 10
+ *     ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CELL_BY_IDX(DT_NODELABEL(n), 1, bits) // 40
+ *
+ * @param node_id node identifier for a node with a atmel,assigned-clocks property
+ * @param idx logical index into atmel,assigned-clocks property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value at index "idx"
+ * @see DT_PHA_BY_IDX()
+ */
+#define ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CELL_BY_IDX(node_id, idx, cell) \
+	DT_PHA_BY_IDX(node_id, atmel_assigned_clocks, idx, cell)
+
+/**
+ * @brief Get a atmel,assigned-clock specifier's cell value by name
+ *
+ * Example devicetree fragment:
+ *
+ *     clk1: clock-controller@... {
+ *             compatible = "vnd,clock";
+ *             #atmel,assigned-clock-cells = < 2 >;
+ *     };
+ *
+ *     n: node {
+ *             atmel,assigned-clocks = < &clk1 10 20 >, < &clk1 30 40 >;
+ *             clock-names = "alpha", "beta";
+ *     };
+ *
+ * Bindings fragment for the vnd,clock compatible:
+ *
+ *     atmel,assigned-clock-cells:
+ *       - bus
+ *       - bits
+ *
+ * Example usage:
+ *
+ *     ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CELL_BY_NAME(DT_NODELABEL(n), alpha, bus) // 10
+ *     ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CELL_BY_NAME(DT_NODELABEL(n), beta, bits) // 40
+ *
+ * @param node_id node identifier for a node with a atmel,assigned-clocks property
+ * @param name lowercase-and-underscores name of a atmel,assigned-clocks element
+ *             as defined by the node's clock-names property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value in the specifier at the named element
+ * @see DT_PHA_BY_NAME()
+ */
+#define ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CELL_BY_NAME(node_id, name, cell) \
+	DT_PHA_BY_NAME(node_id, atmel_assigned_clocks, name, cell)
+
+/**
+ * @brief Equivalent to ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CELL_BY_IDX(node_id, 0, cell)
+ * @param node_id node identifier for a node with a atmel,assigned-clocks property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value at index 0
+ * @see ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CELL_BY_IDX()
+ */
+#define ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CELL(node_id, cell) \
+	ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CELL_BY_IDX(node_id, 0, cell)
+
+/**
+ * @brief Equivalent to ATMEL_SAM0_DT_ASSIGNED_CLOCKS_HAS_IDX(DT_DRV_INST(inst), idx)
+ * @param inst DT_DRV_COMPAT instance number; may or may not have any
+ *             atmel,assigned-clocks property
+ * @param idx index of a atmel,assigned-clocks property phandle-array whose existence
+ *            to check
+ * @return 1 if the index exists, 0 otherwise
+ */
+#define ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_HAS_IDX(inst, idx) \
+	DT_ASSIGNED_CLOCKS_HAS_IDX(DT_DRV_INST(inst), idx)
+
+/**
+ * @brief Equivalent to DT_CLOCK_HAS_NAME(DT_DRV_INST(inst), name)
+ * @param inst DT_DRV_COMPAT instance number; may or may not have any
+ *             atmel,clock-names property.
+ * @param name lowercase-and-underscores clock-names cell value name to check
+ * @return 1 if the atmel,assigned-clock name exists, 0 otherwise
+ */
+#define ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_HAS_NAME(inst, name) \
+	ATMEL_SAM0_DT_ASSIGNED_CLOCKS_HAS_NAME(DT_DRV_INST(inst), name)
+
+/**
+ * @brief Equivalent to ATMEL_SAM0_DT_NUM_ASSIGNED_CLOCKS(DT_DRV_INST(inst))
+ * @param inst instance number
+ * @return number of elements in the atmel,assigned-clocks property
+ */
+#define ATMEL_SAM0_DT_INST_NUM_ASSIGNED_CLOCKS(inst) \
+	ATMEL_SAM0_DT_NUM_ASSIGNED_CLOCKS(DT_DRV_INST(inst))
+
+/**
+ * @brief Get the node identifier for the controller phandle from a
+ *        "atmel,assigned-clocks" phandle-array property at an index
+ *
+ * @param inst instance number
+ * @param idx logical index into "atmel,assigned-clocks"
+ * @return the node identifier for the clock controller referenced at
+ *         index "idx"
+ * @see ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CTLR_BY_IDX()
+ */
+#define ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CTLR_BY_IDX(inst, idx) \
+	ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CTLR_BY_IDX(DT_DRV_INST(inst), idx)
+
+/**
+ * @brief Equivalent to ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CTLR_BY_IDX(inst, 0)
+ * @param inst instance number
+ * @return a node identifier for the atmel,assigned-clocks controller at index 0
+ *         in "atmel,assigned-clocks"
+ * @see ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CTLR()
+ */
+#define ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CTLR(inst) \
+	ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CTLR_BY_IDX(inst, 0)
+
+/**
+ * @brief Get the node identifier for the controller phandle from a
+ *        atmel,assigned-clocks phandle-array property by name
+ *
+ * @param inst instance number
+ * @param name lowercase-and-underscores name of a atmel,assigned-clocks element
+ *             as defined by the node's atmel,assigned-clock-names property
+ * @return the node identifier for the clock controller referenced by
+ *         the named element
+ * @see ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CTLR_BY_NAME()
+ */
+#define ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CTLR_BY_NAME(inst, name) \
+	ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CTLR_BY_NAME(DT_DRV_INST(inst), name)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's atmel,assigned-clock specifier's cell
+ *        value at an index
+ * @param inst DT_DRV_COMPAT instance number
+ * @param idx logical index into atmel,assigned-clocks property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value at index "idx"
+ * @see ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CELL_BY_IDX()
+ */
+#define ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_IDX(inst, idx, cell) \
+	ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CELL_BY_IDX(DT_DRV_INST(inst), idx, cell)
+
+/**
+ * @brief Get a DT_DRV_COMPAT instance's atmel,assigned-clock specifier's cell
+ *        value by name
+ * @param inst DT_DRV_COMPAT instance number
+ * @param name lowercase-and-underscores name of a atmel,assigned-clocks element
+ *             as defined by the node's atmel,assigned-clock-names property
+ * @param cell lowercase-and-underscores cell name
+ * @return the cell value in the specifier at the named element
+ * @see ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CELL_BY_NAME()
+ */
+#define ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_NAME(inst, name, cell) \
+	ATMEL_SAM0_DT_ASSIGNED_CLOCKS_CELL_BY_NAME(DT_DRV_INST(inst), name, cell)
+
+/**
+ * @brief Equivalent to ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_IDX(inst, 0, cell)
+ * @param inst DT_DRV_COMPAT instance number
+ * @param cell lowercase-and-underscores cell name
+ * @return the value of the cell inside the specifier at index 0
+ */
+#define ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL(inst, cell) \
+	ATMEL_SAM0_DT_INST_ASSIGNED_CLOCKS_CELL_BY_IDX(inst, 0, cell)
+
+/* clang-format on */
+
 #endif /* _ATMEL_SAM0_SOC_DT_H_ */
diff --git a/soc/atmel/sam0/common/soc_samc2x.c b/soc/atmel/sam0/common/soc_samc2x.c
index 1581b62eef2..bfcb111b0c2 100644
--- a/soc/atmel/sam0/common/soc_samc2x.c
+++ b/soc/atmel/sam0/common/soc_samc2x.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2022 Kamil Serwus
- * Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
+ * Copyright (c) 2023-2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,11 +10,19 @@
  * @brief Atmel SAMC MCU series initialization code
  */
 
+/* GCLK Gen 0 -> GCLK_MAIN @ OSC48M
+ * GCLK Gen 2 -> WDT       @ reserved
+ * GCLK Gen 0 -> ADC       @ OSC48M
+ * GCLK Gen 4 -> RTC       @ reserved
+ */
+
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
 #include <soc.h>
 
+/* clang-format off */
+
 static void flash_waitstates_init(void)
 {
 	/* Two wait state at 48 MHz. */
@@ -50,3 +58,5 @@ void soc_reset_hook(void)
 	mclk_init();
 	gclks_init();
 }
+
+/* clang-format on */
diff --git a/soc/atmel/sam0/common/soc_samd2x.c b/soc/atmel/sam0/common/soc_samd2x.c
index f915459a576..f332100bf64 100644
--- a/soc/atmel/sam0/common/soc_samd2x.c
+++ b/soc/atmel/sam0/common/soc_samd2x.c
@@ -1,7 +1,7 @@
 /*
  * Copyright (c) 2017 Google LLC.
  * Copyright (c) 2023 Ionut Catalin Pavel <iocapa@iocapa.com>
- * Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
+ * Copyright (c) 2023-2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,6 +20,7 @@
  * GCLK Gen 1 -> DFLL48M (variable)
  * GCLK Gen 2 -> WDT @ 32768 Hz
  * GCLK Gen 3 -> ADC @ 8 MHz
+ * GCLK Gen 4 -> RTC @ xtal 32768 Hz
  */
 
 #include <zephyr/device.h>
@@ -29,6 +30,8 @@
 #include <soc.h>
 #include <cmsis_core.h>
 
+/* clang-format off */
+
 /**
  * Fix different naming conventions for SAMD20
  */
@@ -38,6 +41,23 @@
 #define FUSES_OSC32K_CAL_Msk		FUSES_OSC32KCAL_Msk
 #endif
 
+static void gclk_connect(uint8_t gclk, uint32_t src, uint32_t div, uint32_t flags)
+{
+	GCLK->GENDIV.reg = GCLK_GENDIV_ID(gclk)
+			 | GCLK_GENDIV_DIV(div);
+
+	while (GCLK->STATUS.bit.SYNCBUSY) {
+	}
+
+	GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk)
+			  | GCLK_GENCTRL_GENEN
+			  | src
+			  | flags;
+
+	while (GCLK->STATUS.bit.SYNCBUSY) {
+	}
+}
+
 static inline void osc8m_init(void)
 {
 	uint32_t reg;
@@ -57,19 +77,7 @@ static inline void osc8m_init(void)
 	/* Use 8Mhz clock as gclk_main to allow switching between clocks
 	 * when using bootloaders
 	 */
-	GCLK->GENDIV.reg = GCLK_GENDIV_ID(0)
-			 | GCLK_GENDIV_DIV(0);
-
-	while (GCLK->STATUS.bit.SYNCBUSY) {
-	}
-
-	GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(0)
-			  | GCLK_GENCTRL_SRC_OSC8M
-			  | GCLK_GENCTRL_IDC
-			  | GCLK_GENCTRL_GENEN;
-
-	while (GCLK->STATUS.bit.SYNCBUSY) {
-	}
+	gclk_connect(0, GCLK_GENCTRL_SRC_OSC8M, 0, 0);
 }
 
 #if !CONFIG_SOC_ATMEL_SAMD_OSC32K || CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN
@@ -149,28 +157,17 @@ static inline void dfll48m_init(void)
 {
 	uint32_t fcal, ccal;
 
-	GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(1)
+	gclk_connect(1,
 #if CONFIG_SOC_ATMEL_SAMD_OSC32K_AS_MAIN
-			  | GCLK_GENCTRL_SRC_OSC32K
+			  GCLK_GENCTRL_SRC_OSC32K,
 #elif CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN
-			  | GCLK_GENCTRL_SRC_XOSC32K
+			  GCLK_GENCTRL_SRC_XOSC32K,
 #elif CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN
-			  | GCLK_GENCTRL_SRC_OSC8M
+			  GCLK_GENCTRL_SRC_OSC8M,
 #elif CONFIG_SOC_ATMEL_SAMD_XOSC_AS_MAIN
-			  | GCLK_GENCTRL_SRC_XOSC
+			  GCLK_GENCTRL_SRC_XOSC,
 #endif
-			  | GCLK_GENCTRL_IDC
-			  | GCLK_GENCTRL_RUNSTDBY
-			  | GCLK_GENCTRL_GENEN;
-
-	while (GCLK->STATUS.bit.SYNCBUSY) {
-	}
-
-	GCLK->GENDIV.reg = GCLK_GENDIV_ID(1)
-			 | GCLK_GENDIV_DIV(SOC_ATMEL_SAM0_GCLK1_DIV);
-
-	while (GCLK->STATUS.bit.SYNCBUSY) {
-	}
+		SOC_ATMEL_SAM0_GCLK1_DIV, GCLK_GENCTRL_RUNSTDBY);
 
 	/* Route multiplexer 0 to DFLL48M */
 	GCLK->CLKCTRL.reg = GCLK_CLKCTRL_ID(0)
@@ -222,19 +219,7 @@ static inline void flash_waitstates_init(void)
 #else
 static inline void gclk_main_configure(void)
 {
-	GCLK->GENDIV.reg = GCLK_GENDIV_ID(0)
-			 | GCLK_GENDIV_DIV(SOC_ATMEL_SAM0_GCLK0_DIV);
-
-	while (GCLK->STATUS.bit.SYNCBUSY) {
-	}
-
-	GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(0)
-			  | GCLK_GENCTRL_SRC_DFLL48M
-			  | GCLK_GENCTRL_IDC
-			  | GCLK_GENCTRL_GENEN;
-
-	while (GCLK->STATUS.bit.SYNCBUSY) {
-	}
+	gclk_connect(0, GCLK_GENCTRL_SRC_DFLL48M, SOC_ATMEL_SAM0_GCLK0_DIV, 0);
 }
 #endif
 
@@ -243,19 +228,16 @@ static inline void gclk_main_configure(void)
 #else
 static inline void gclk_adc_configure(void)
 {
-	GCLK->GENDIV.reg = GCLK_GENDIV_ID(3)
-			 | GCLK_GENDIV_DIV(SOC_ATMEL_SAM0_GCLK3_DIV);
-
-	while (GCLK->STATUS.bit.SYNCBUSY) {
-	}
-
-	GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(3)
-			  | GCLK_GENCTRL_SRC_DFLL48M
-			  | GCLK_GENCTRL_IDC
-			  | GCLK_GENCTRL_GENEN;
+	gclk_connect(3, GCLK_GENCTRL_SRC_DFLL48M, SOC_ATMEL_SAM0_GCLK3_DIV, 0);
+}
+#endif
 
-	while (GCLK->STATUS.bit.SYNCBUSY) {
-	}
+#if !CONFIG_RTC_ATMEL_SAM0 || CONFIG_SOC_ATMEL_SAMD_DEFAULT_AS_MAIN
+#define gclk_rtc_configure()
+#else
+static inline void gclk_rtc_configure(void)
+{
+	gclk_connect(4, GCLK_GENCTRL_SRC_XOSC32K, CONFIG_SOC_ATMEL_SAMD_XOSC32K_PRESCALER, 0);
 }
 #endif
 
@@ -264,16 +246,7 @@ static inline void gclk_adc_configure(void)
 #else
 static inline void gclk_wdt_configure(void)
 {
-	GCLK->GENDIV.reg = GCLK_GENDIV_ID(2)
-			 | GCLK_GENDIV_DIV(4);
-
-	GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(2)
-			  | GCLK_GENCTRL_GENEN
-			  | GCLK_GENCTRL_SRC_OSCULP32K
-			  | GCLK_GENCTRL_DIVSEL;
-
-	while (GCLK->STATUS.bit.SYNCBUSY) {
-	}
+	gclk_connect(2, GCLK_GENCTRL_SRC_OSCULP32K, 4, GCLK_GENCTRL_DIVSEL);
 }
 #endif
 
@@ -296,6 +269,9 @@ void soc_reset_hook(void)
 	flash_waitstates_init();
 	gclk_main_configure();
 	gclk_adc_configure();
+	gclk_rtc_configure();
 	gclk_wdt_configure();
 	osc8m_disable();
 }
+
+/* clang-format on */
diff --git a/soc/atmel/sam0/common/soc_samd5x.c b/soc/atmel/sam0/common/soc_samd5x.c
index a12d3891ea8..77ac12e1d13 100644
--- a/soc/atmel/sam0/common/soc_samd5x.c
+++ b/soc/atmel/sam0/common/soc_samd5x.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2019 ML!PA Consulting GmbH
- * Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
+ * Copyright (c) 2023-2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -10,30 +10,57 @@
  * @brief Atmel SAMD MCU series initialization code
  */
 
+/* The CPU clock will be configured to the DT requested value,
+ * and run via DFLL48M.
+ *
+ * Reference -> GCLK Gen 1 -> DFLL48M -> GCLK Gen 0 -> GCLK_MAIN
+ *
+ * GCLK Gen 0 -> GCLK_MAIN @ DPLL0
+ * GCLK Gen 1 -> DFLL48M @ 32768 Hz
+ * GCLK Gen 2 -> USB @ DFLL48M
+ * GCLK Gen 3 -> ADC @ reserved
+ * GCLK Gen 4 -> RTC @ xtal 32768 Hz
+ */
+
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
 #include <soc.h>
 
+/* clang-format off */
+
 #define SAM0_DFLL_FREQ_HZ		(48000000U)
 #define SAM0_DPLL_FREQ_MIN_HZ		(96000000U)
 #define SAM0_DPLL_FREQ_MAX_HZ		(200000000U)
 #define SAM0_XOSC32K_STARTUP_TIME	CONFIG_SOC_ATMEL_SAMD5X_XOSC32K_STARTUP
 
-#if CONFIG_SOC_ATMEL_SAMD5X_XOSC32K_AS_MAIN
-static void osc32k_init(void)
+#if !CONFIG_SOC_ATMEL_SAMD5X_XOSC32K
+#define xosc32k_init()
+#else
+static inline void xosc32k_init(void)
 {
 	OSC32KCTRL->XOSC32K.reg = OSC32KCTRL_XOSC32K_ENABLE
+#if CONFIG_SOC_ATMEL_SAMD5X_XOSC32K_CRYSTAL
 				| OSC32KCTRL_XOSC32K_XTALEN
+#endif
+#if CONFIG_SOC_ATMEL_SAMD5X_XOSC32K_GAIN_HS
+				| OSC32KCTRL_XOSC32K_CGM_HS
+#else
 				| OSC32KCTRL_XOSC32K_CGM_XT
+#endif
 				| OSC32KCTRL_XOSC32K_EN32K
+				| OSC32KCTRL_XOSC32K_EN1K
 				| OSC32KCTRL_XOSC32K_RUNSTDBY
-				| OSC32KCTRL_XOSC32K_STARTUP(SAM0_XOSC32K_STARTUP_TIME)
-				;
+				| OSC32KCTRL_XOSC32K_STARTUP(SAM0_XOSC32K_STARTUP_TIME);
 
 	while (!OSC32KCTRL->STATUS.bit.XOSC32KRDY) {
 	}
+}
+#endif
 
+#if CONFIG_SOC_ATMEL_SAMD5X_XOSC32K_AS_MAIN
+static void osc32k_init(void)
+{
 	GCLK->GENCTRL[1].reg = GCLK_GENCTRL_SRC(GCLK_SOURCE_XOSC32K)
 			     | GCLK_GENCTRL_RUNSTDBY | GCLK_GENCTRL_GENEN;
 
@@ -132,6 +159,7 @@ void soc_reset_hook(void)
 	CMCC->CTRL.bit.CEN = 0;
 
 	gclk_reset();
+	xosc32k_init();
 	osc32k_init();
 	dfll_init();
 	dpll_init(0, dfll_div * CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
@@ -141,4 +169,15 @@ void soc_reset_hook(void)
 
 	/* connect GCLK2 to 48 MHz DFLL for USB */
 	gclk_connect(2, GCLK_SOURCE_DFLL48M, 0);
+
+	/* connect GCLK4 to xosc32k for RTC. The output is 1024 Hz*/
+	gclk_connect(4,
+#if CONFIG_SOC_ATMEL_SAMD5X_XOSC32K
+		     GCLK_SOURCE_XOSC32K,
+#else
+		     GCLK_SOURCE_OSCULP32K,
+#endif
+		     CONFIG_SOC_ATMEL_SAMD5X_OSC32K_PRESCALER);
 }
+
+/* clang-format on */
diff --git a/soc/atmel/sam0/common/soc_saml2x.c b/soc/atmel/sam0/common/soc_saml2x.c
index 3dd657a52f2..d65831f785a 100644
--- a/soc/atmel/sam0/common/soc_saml2x.c
+++ b/soc/atmel/sam0/common/soc_saml2x.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2021 Argentum Systems Ltd.
- * Copyright (c) 2023 Gerson Fernando Budke <nandojve@gmail.com>
+ * Copyright (c) 2023-2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,6 +16,8 @@
 #include <soc.h>
 #include <cmsis_core.h>
 
+/* clang-format off */
+
 /* the SAML21 currently operates only in Performance Level 2... sleep
  * and low-power operation are not currently supported by the BSP
  *
@@ -27,6 +29,7 @@
  * GCLK Gen 1 -> DFLL48M (variable)
  * GCLK Gen 2 -> USB @ 48 MHz
  * GCLK Gen 3 -> ADC @ 24 MHz (further /2 in the ADC peripheral)
+ * GCLK Gen 4 -> RTC @ reserved
  */
 
 static inline void gclk_reset(void)
@@ -57,6 +60,7 @@ static inline void osc32k_init(void)
 		| !OSC32KCTRL_OSC32K_ONDEMAND
 		|  OSC32KCTRL_OSC32K_RUNSTDBY
 		|  OSC32KCTRL_OSC32K_EN32K
+		|  OSC32KCTRL_OSC32K_EN1K
 		|  OSC32KCTRL_OSC32K_ENABLE;
 
 	/* wait for ready */
@@ -75,6 +79,7 @@ static inline void xosc32k_init(void)
 		| !OSC32KCTRL_XOSC32K_ONDEMAND
 		|  OSC32KCTRL_XOSC32K_RUNSTDBY
 		|  OSC32KCTRL_XOSC32K_EN32K
+		|  OSC32KCTRL_XOSC32K_EN1K
 #if CONFIG_SOC_ATMEL_SAML_XOSC32K_CRYSTAL
 		|  OSC32KCTRL_XOSC32K_XTALEN
 #endif
@@ -266,3 +271,5 @@ void soc_reset_hook(void)
 	gclk_usb_configure();
 	gclk_adc_configure();
 }
+
+/* clang-format on */
diff --git a/soc/bouffalolab/CMakeLists.txt b/soc/bouffalolab/CMakeLists.txt
new file mode 100644
index 00000000000..435b5b79480
--- /dev/null
+++ b/soc/bouffalolab/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2021-2025 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(common)
+add_subdirectory(${SOC_SERIES})
diff --git a/soc/bouffalolab/Kconfig b/soc/bouffalolab/Kconfig
new file mode 100644
index 00000000000..b15605c00f3
--- /dev/null
+++ b/soc/bouffalolab/Kconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2021-2025 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_BOUFFALOLAB_BFLB
+	select HAS_BFLB_HAL
+
+if SOC_FAMILY_BOUFFALOLAB_BFLB
+
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_BOUFFALOLAB_BFLB
diff --git a/soc/bouffalolab/Kconfig.defconfig b/soc/bouffalolab/Kconfig.defconfig
new file mode 100644
index 00000000000..b8e9852b6f9
--- /dev/null
+++ b/soc/bouffalolab/Kconfig.defconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2021-2025 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_BOUFFALOLAB_BFLB
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+rsource "*/Kconfig.defconfig"
+
+endif # SOC_FAMILY_BOUFFALOLAB_BFLB
diff --git a/soc/bouffalolab/Kconfig.soc b/soc/bouffalolab/Kconfig.soc
new file mode 100644
index 00000000000..e3841e277bd
--- /dev/null
+++ b/soc/bouffalolab/Kconfig.soc
@@ -0,0 +1,11 @@
+# Copyright (c) 2021-2025 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_BOUFFALOLAB_BFLB
+	bool
+
+config SOC_FAMILY
+	default "bouffalolab_bflb" if SOC_FAMILY_BOUFFALOLAB_BFLB
+
+rsource "*/Kconfig.soc"
diff --git a/soc/bouffalolab/bl60x/CMakeLists.txt b/soc/bouffalolab/bl60x/CMakeLists.txt
new file mode 100644
index 00000000000..c5437820149
--- /dev/null
+++ b/soc/bouffalolab/bl60x/CMakeLists.txt
@@ -0,0 +1,13 @@
+# Copyright (c) 2021-2025 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+zephyr_sources(soc.c)
+
+zephyr_linker_sources_ifdef(CONFIG_SOC_SERIES_BL60X RODATA rodata.ld)
+
+set(SOC_LINKER_SCRIPT
+  ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld
+  CACHE INTERNAL ""
+  )
diff --git a/soc/bouffalolab/bl60x/Kconfig b/soc/bouffalolab/bl60x/Kconfig
new file mode 100644
index 00000000000..fa9b22d1f57
--- /dev/null
+++ b/soc/bouffalolab/bl60x/Kconfig
@@ -0,0 +1,18 @@
+# Copyright (c) 2021-2025 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_BL60X
+	select RISCV
+	select RISCV_MACHINE_TIMER
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_C
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
+	select ATOMIC_OPERATIONS_C
+	select CPU_HAS_FPU
+	select INCLUDE_RESET_VECTOR
+	select SOC_EARLY_INIT_HOOK
+	select XIP
diff --git a/soc/bouffalolab/bl60x/Kconfig.defconfig b/soc/bouffalolab/bl60x/Kconfig.defconfig
new file mode 100644
index 00000000000..08653e3e458
--- /dev/null
+++ b/soc/bouffalolab/bl60x/Kconfig.defconfig
@@ -0,0 +1,10 @@
+# Copyright (c) 2021-2025 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_BL60X
+
+config NUM_IRQS
+	default 80
+
+endif # SOC_SERIES_BL60X
diff --git a/soc/bouffalolab/bl60x/Kconfig.soc b/soc/bouffalolab/bl60x/Kconfig.soc
new file mode 100644
index 00000000000..69c234b1d33
--- /dev/null
+++ b/soc/bouffalolab/bl60x/Kconfig.soc
@@ -0,0 +1,49 @@
+# Copyright (c) 2021-2025 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_BL60X
+	bool
+	select SOC_FAMILY_BOUFFALOLAB_BFLB
+	help
+	  Enable support for BouffaloLab BL6xx MCU series
+
+config SOC_SERIES
+	default "bl60x" if SOC_SERIES_BL60X
+
+config SOC_BL602C00Q2I
+	bool
+	select SOC_SERIES_BL60X
+
+config SOC_BL602C20Q2I
+	bool
+	select SOC_SERIES_BL60X
+
+config SOC_BL602C20Q2IS
+	bool
+	select SOC_SERIES_BL60X
+
+config SOC_BL602C40Q2IS
+	bool
+	select SOC_SERIES_BL60X
+
+config SOC_BL602l10Q2H
+	bool
+	select SOC_SERIES_BL60X
+
+config SOC_BL602l20Q2H
+	bool
+	select SOC_SERIES_BL60X
+
+config SOC_BL604E20Q2I
+	bool
+	select SOC_SERIES_BL60X
+
+config SOC
+	default "bl602c00q2i"  if SOC_BL602C00Q2I
+	default "bl602c20q2i"  if SOC_BL602C20Q2I
+	default "bl602c20q2is" if SOC_BL602C20Q2IS
+	default "bl602c40q2is" if SOC_BL602C40Q2IS
+	default "bl602l10q2h"  if SOC_BL602l10Q2H
+	default "bl602l20q2h"  if SOC_BL602l20Q2H
+	default "bl604e20q2i"  if SOC_BL604E20Q2I
diff --git a/soc/bouffalolab/bl60x/rodata.ld b/soc/bouffalolab/bl60x/rodata.ld
new file mode 100644
index 00000000000..9cd607d3d99
--- /dev/null
+++ b/soc/bouffalolab/bl60x/rodata.ld
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2021-2025 ATL Electronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+KEEP(*(SORT_NONE( EXCLUDE_FILE( *bl602_glb.o			\
+				*bl602_pds.o			\
+				*bl602_common.o			\
+				*bl602_sf_cfg.o			\
+				*bl602_sf_cfg_ext*.o*		\
+				*bl602_sf_ctrl.o		\
+				*bl602_sflash.o			\
+				*bl602_sflash_ext*.o*		\
+				*bl602_xip_sflash.o		\
+				*bl602_xip_sflash_ext*.o*	\
+				*bl602_ef_ctrl.o) .rodata*)))
diff --git a/soc/bouffalolab/bl60x/soc.c b/soc/bouffalolab/bl60x/soc.c
new file mode 100644
index 00000000000..96f7bdfecc7
--- /dev/null
+++ b/soc/bouffalolab/bl60x/soc.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2021-2025 ATL Electronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Bouffalo Lab RISC-V MCU series initialization code
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/irq.h>
+
+#include <bflb_hbn.h>
+#include <bflb_glb.h>
+#include <clic.h>
+
+#define ROOT_FCLK_DIV       (0)
+#define ROOT_BCLK_DIV       (1)
+#define ROOT_UART_CLOCK_DIV (0)
+
+static void system_bor_init(void)
+{
+	HBN_BOR_CFG_Type borCfg = { 1 /* pu_bor */,  0 /* irq_bor_en */,
+				    1 /* bor_vth */, 1 /* bor_sel */ };
+	HBN_Set_BOR_Cfg(&borCfg);
+}
+
+static uint32_t mtimer_get_clk_src_div(void)
+{
+	return ((SystemCoreClockGet() / (GLB_Get_BCLK_Div() + 1))
+		/ 1000 / 1000 - 1);
+}
+
+static void system_clock_init(void)
+{
+	GLB_Set_System_CLK(GLB_PLL_XTAL_40M, GLB_SYS_CLK_PLL160M);
+	GLB_Set_System_CLK_Div(ROOT_FCLK_DIV, ROOT_BCLK_DIV);
+	GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div());
+}
+
+static void peripheral_clock_init(void)
+{
+	GLB_Set_UART_CLK(1, HBN_UART_CLK_160M, ROOT_UART_CLOCK_DIV);
+}
+
+void soc_early_init_hook(void)
+{
+	uint32_t key;
+	uint32_t *p;
+	uint32_t i = 0;
+	uint32_t tmp = 0;
+
+	key = irq_lock();
+
+	__disable_irq();
+
+	/* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */
+	tmp = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+	tmp = BL_CLR_REG_BIT(tmp, HBN_REG_EN_HW_PU_PD);
+	BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmp);
+
+	/* GLB_Set_EM_Sel(GLB_EM_0KB); */
+	tmp = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
+	tmp = BL_SET_REG_BITS_VAL(tmp, GLB_EM_SEL, GLB_EM_0KB);
+	BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmp);
+
+	/* Fix 26M xtal clkpll_sdmin */
+	tmp = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM);
+
+	if (BL_GET_REG_BITS_VAL(tmp, PDS_CLKPLL_SDMIN) == 0x49D39D) {
+		tmp = BL_SET_REG_BITS_VAL(tmp, PDS_CLKPLL_SDMIN, 0x49D89E);
+		BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmp);
+	}
+
+	/* Restore default setting*/
+
+	/* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */
+	tmp = BL_RD_REG(GLB_BASE, GLB_PARM);
+	tmp = BL_SET_REG_BITS_VAL(tmp, GLB_UART_SWAP_SET, UART_SIG_SWAP_NONE);
+	BL_WR_REG(GLB_BASE, GLB_PARM, tmp);
+
+	/* GLB_JTAG_Sig_Swap_Set(JTAG_SIG_SWAP_NONE); */
+	tmp = BL_RD_REG(GLB_BASE, GLB_PARM);
+	tmp = BL_SET_REG_BITS_VAL(tmp, GLB_JTAG_SWAP_SET, JTAG_SIG_SWAP_NONE);
+	BL_WR_REG(GLB_BASE, GLB_PARM, tmp);
+
+	/* CLear all interrupt */
+	p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIE);
+
+	for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
+		p[i] = 0;
+	}
+
+	p = (uint32_t *)(CLIC_HART0_ADDR + CLIC_INTIP);
+
+	for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
+		p[i] = 0;
+	}
+
+	/* init bor for all platform */
+	system_bor_init();
+	/* global IRQ enable */
+	__enable_irq();
+
+	system_clock_init();
+	peripheral_clock_init();
+
+	irq_unlock(key);
+}
+
+/* identify flash config automatically */
+extern BL_Err_Type flash_init(void);
+
+void System_Post_Init(void)
+{
+	PDS_Trim_RC32M();
+	HBN_Trim_RC32K();
+	flash_init();
+}
diff --git a/soc/bouffalolab/bl60x/soc.h b/soc/bouffalolab/bl60x/soc.h
new file mode 100644
index 00000000000..c2442059359
--- /dev/null
+++ b/soc/bouffalolab/bl60x/soc.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2021-2025 ATL Electronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Board configuration macros
+ *
+ * This header file is used to specify and describe board-level aspects
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+#include <zephyr/sys/util.h>
+#include <../common/soc_common.h>
+
+#ifndef _ASMLANGUAGE
+
+/* Add include for DTS generated information */
+#include <zephyr/devicetree.h>
+
+#if defined(CONFIG_SOC_SERIES_BL60X)
+#include <bl602.h>
+#else
+#error Library does not support the specified device.
+#endif
+
+/* clang-format off */
+
+/* RISC-V Machine Timer configuration */
+#define RISCV_MTIME_BASE                  0x0200BFF8
+#define RISCV_MTIMECMP_BASE               0x02004000
+
+/* lib-c hooks required RAM defined variables */
+#define RISCV_RAM_BASE                    DT_SRAM_BASE_ADDRESS
+#define RISCV_RAM_SIZE                    KB(DT_SRAM_SIZE)
+
+#define SOC_BOUFFALOLAB_BL_PLL160_FREQ_HZ (160000000)
+#define SOC_BOUFFALOLAB_BL_HCLK_FREQ_HZ	\
+		DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
+
+/* clang-format on */
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _SOC__H_ */
diff --git a/soc/bouffalolab/common/CMakeLists.txt b/soc/bouffalolab/common/CMakeLists.txt
new file mode 100644
index 00000000000..2675509dd81
--- /dev/null
+++ b/soc/bouffalolab/common/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright (c) 2021-2025 ATL Electronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+  soc_irq.S
+  soc_common_irq.c
+  vector.S
+  )
diff --git a/soc/bouffalolab/common/clic.h b/soc/bouffalolab/common/clic.h
new file mode 100644
index 00000000000..7328a46257c
--- /dev/null
+++ b/soc/bouffalolab/common/clic.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2021-2025 ATL Electronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SIFIVE_CLIC_H
+#define _SIFIVE_CLIC_H
+
+#define CLIC_CTRL_ADDR    (DT_REG_ADDR(DT_NODELABEL(clic)))
+#define CLIC_HART0_OFFSET (0x800000U)
+#define CLIC_HART0_ADDR   (CLIC_CTRL_ADDR + CLIC_HART0_OFFSET)
+
+#define CLIC_MSIP          0x0000
+#define CLIC_MSIP_size     0x4
+#define CLIC_MTIMECMP      0x4000
+#define CLIC_MTIMECMP_size 0x8
+#define CLIC_MTIME         0xBFF8
+#define CLIC_MTIME_size    0x8
+
+#define CLIC_INTIP  0x000
+#define CLIC_INTIE  0x400
+#define CLIC_INTCFG 0x800
+#define CLIC_CFG    0xc00
+
+#endif /* _SIFIVE_CLIC_H */
diff --git a/soc/bouffalolab/common/pinctrl_soc.h b/soc/bouffalolab/common/pinctrl_soc.h
new file mode 100644
index 00000000000..47077710a87
--- /dev/null
+++ b/soc/bouffalolab/common/pinctrl_soc.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * Bouffalo Lab SoC specific helpers for pinctrl driver
+ */
+
+#ifndef ZEPHYR_SOC_RISCV_BFLB_COMMON_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_RISCV_BFLB_COMMON_PINCTRL_SOC_H_
+
+#include <zephyr/drivers/pinctrl/pinctrl_soc_bflb_common.h>
+
+#endif /* ZEPHYR_SOC_RISCV_BFLB_COMMON_PINCTRL_SOC_H_ */
diff --git a/soc/bouffalolab/common/soc_common.h b/soc/bouffalolab/common/soc_common.h
new file mode 100644
index 00000000000..534f4175e24
--- /dev/null
+++ b/soc/bouffalolab/common/soc_common.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file interrupt management code for riscv SOCs supporting the SiFive clic
+ */
+
+#ifndef __SOC_COMMON_H_
+#define __SOC_COMMON_H_
+
+/* clang-format off */
+
+/* IRQ numbers */
+#define RISCV_MACHINE_SOFT_IRQ       3  /* Machine Software Interrupt */
+#define RISCV_MACHINE_TIMER_IRQ      7  /* Machine Timer Interrupt */
+#define RISCV_MACHINE_EXT_IRQ        11 /* Machine External Interrupt */
+
+/* ECALL Exception numbers */
+#define SOC_MCAUSE_ECALL_EXP         11 /* Machine ECALL instruction */
+#define SOC_MCAUSE_USER_ECALL_EXP    8  /* User ECALL instruction */
+
+/* SOC-specific MCAUSE bitfields */
+#ifdef CONFIG_64BIT
+/* Interrupt Mask */
+#define SOC_MCAUSE_IRQ_MASK          (1 << 63)
+/* Exception code Mask */
+#define SOC_MCAUSE_EXP_MASK          0x7FFFFFFFFFFFFFFF
+#else
+/* Interrupt Mask */
+#define SOC_MCAUSE_IRQ_MASK          (1 << 31)
+/* Exception code Mask */
+#define SOC_MCAUSE_EXP_MASK          0x7FFFFFFF
+#endif
+
+/* SOC-Specific EXIT ISR command */
+#define SOC_ERET                     mret
+
+/* CLINT Base Address */
+
+#define CLIC_TIMER_ENABLE_ADDRESS    (0x02800407)
+
+/* In mstatus register */
+
+#define SOC_MIE_MSIE                 (0x1 << 3) /* Machine Software Interrupt Enable */
+
+/* IRQ 0-15 : (exception:interrupt=0) */
+
+#define SOC_IRQ_IAMISALIGNED	     (0)	/* Instruction Address Misaligned */
+#define SOC_IRQ_IAFAULT		     (1)	/* Instruction Address Fault */
+#define SOC_IRQ_IINSTRUCTION	     (2)	/* Illegal Instruction */
+#define SOC_IRQ_BPOINT		     (3)	/* Break Point */
+#define SOC_IRQ_LAMISALIGNED	     (4)	/* Load Address Misaligned */
+#define SOC_IRQ_LAFAULT		     (5)	/* Load Access Fault */
+#define SOC_IRQ_SAMISALIGNED	     (6)	/* Store/AMO Address Misaligned */
+#define SOC_IRQ_SAFAULT		     (7)	/* Store/AMO Access Fault */
+#define SOC_IRQ_ECALLU		     (8)	/* Environment Call from U-mode */
+						/* 9-10: Reserved */
+#define SOC_IRQ_ECALLM		     (11)	/* Environment Call from M-mode */
+						/* 12-15: Reserved */
+						/* IRQ 16- : (async event:interrupt=1) */
+#define SOC_IRQ_NUM_BASE	     (16)
+#define SOC_IRQ_ASYNC		     (16)
+
+/* Machine Software Int */
+#define SOC_IRQ_MSOFT		     (SOC_IRQ_ASYNC + RISCV_MACHINE_SOFT_IRQ)
+/* Machine Timer Int */
+#define SOC_IRQ_MTIMER		     (SOC_IRQ_ASYNC + RISCV_MACHINE_TIMER_IRQ)
+/* Machine External Int */
+#define SOC_IRQ_MEXT		     (SOC_IRQ_ASYNC + RISCV_MACHINE_EXT_IRQ)
+
+/* Machine Global External Interrupt */
+#define SOC_NR_MGEI_IRQS	     (64)
+
+/* Total number of IRQs */
+#define SOC_NR_IRQS		     (SOC_NR_MGEI_IRQS + SOC_IRQ_NUM_BASE)
+
+/* clang-format on */
+
+#endif /* __SOC_COMMON_H_ */
diff --git a/soc/bouffalolab/common/soc_common_irq.c b/soc/bouffalolab/common/soc_common_irq.c
new file mode 100644
index 00000000000..82dacbcc4c6
--- /dev/null
+++ b/soc/bouffalolab/common/soc_common_irq.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief interrupt management code for riscv SOCs supporting the SiFive clic
+ */
+#include <zephyr/irq.h>
+#include <soc.h>
+#include <clic.h>
+
+/* clang-format off */
+
+static void clic_irq_enable(unsigned int irq)
+{
+	*(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + irq) = 1;
+}
+
+static void clic_irq_disable(unsigned int irq)
+{
+	*(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + irq) = 0;
+}
+
+void arch_irq_enable(unsigned int irq)
+{
+	uint32_t mie;
+
+	if (irq == SOC_IRQ_MSOFT) {
+
+		/* Read mstatus & set machine software interrupt enable in mie */
+
+		__asm__ volatile("csrrs %0, mie, %1"
+				 : "=r"(mie)
+				 : "r"(BIT(RISCV_MACHINE_SOFT_IRQ)));
+
+	} else if (irq == SOC_IRQ_MTIMER) {
+		*(volatile uint8_t *)CLIC_TIMER_ENABLE_ADDRESS = 1;
+
+		/* Read mstatus & set machine timer interrupt enable in mie */
+		__asm__ volatile("csrrs %0, mie, %1"
+				 : "=r"(mie)
+				 : "r"(BIT(RISCV_MACHINE_TIMER_IRQ)
+				     | BIT(RISCV_MACHINE_EXT_IRQ)));
+	} else {
+		clic_irq_enable(irq - SOC_IRQ_ASYNC);
+	}
+}
+
+void arch_irq_disable(unsigned int irq)
+{
+	uint32_t mie;
+
+	if (irq == SOC_IRQ_MSOFT) {
+
+		/* Read mstatus & set machine software interrupt enable in mie */
+
+		__asm__ volatile("csrrc %0, mie, %1"
+				 : "=r"(mie)
+				 : "r"(BIT(RISCV_MACHINE_SOFT_IRQ)));
+
+	} else if (irq == SOC_IRQ_MTIMER) {
+		*(volatile uint8_t *)CLIC_TIMER_ENABLE_ADDRESS = 0;
+
+		/* Read mstatus & set machine timer interrupt enable in mie */
+		__asm__ volatile("csrrc %0, mie, %1"
+				 : "=r"(mie)
+				 : "r"(BIT(RISCV_MACHINE_TIMER_IRQ)
+				     | BIT(RISCV_MACHINE_EXT_IRQ)));
+	} else {
+		clic_irq_disable(irq - SOC_IRQ_ASYNC);
+	}
+}
+
+void arch_irq_priority_set(unsigned int irq, unsigned int prio)
+{
+	ARG_UNUSED(irq);
+	ARG_UNUSED(prio);
+}
+
+int arch_irq_is_enabled(unsigned int irq)
+{
+	uint32_t mie;
+
+	/* Enable MEIE (machine external interrupt enable) */
+	__asm__ volatile("csrrs %0, mie, %1"
+			 : "=r"(mie)
+			 : "r"(BIT(RISCV_MACHINE_EXT_IRQ)));
+
+	/* Read mstatus & set machine interrupt enable (MIE) in mstatus */
+	__asm__ volatile("csrrs %0, mstatus, %1"
+			 : "=r"(mie)
+			 : "r"(MSTATUS_MIE));
+
+	return !!(mie & SOC_MIE_MSIE);
+}
+
+/* clang-format on */
diff --git a/soc/bouffalolab/common/soc_irq.S b/soc/bouffalolab/common/soc_irq.S
new file mode 100644
index 00000000000..b2fabf12035
--- /dev/null
+++ b/soc/bouffalolab/common/soc_irq.S
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * common interrupt management code for riscv SOCs supporting the riscv
+ * privileged architecture specification
+ */
+#include <zephyr/kernel_structs.h>
+#include <offsets.h>
+#include <zephyr/toolchain.h>
+#include <zephyr/linker/sections.h>
+#include <soc.h>
+
+/* exports */
+GTEXT(__soc_handle_irq)
+
+/*
+ * SOC-specific function to handle pending IRQ number generating the interrupt.
+ * Exception number is given as parameter via register a0.
+ */
+SECTION_FUNC(exception.other, __soc_handle_irq)
+	/* Clear exception number from CSR mip register */
+	li t1, 1
+	sll t0, t1, a0
+	csrrc t1, mip, t0
+
+	/* Return */
+	jalr x0, ra
+
+/*
+ * __soc_is_irq is defined as .weak to allow re-implementation by
+ * SOCs that does not truly follow the riscv privilege specification.
+ */
+WTEXT(__soc_is_irq)
+
+/*
+ * SOC-specific function to determine if the exception is the result of a
+ * an interrupt or an exception
+ * return 1 (interrupt) or 0 (exception)
+ *
+ */
+SECTION_FUNC(exception.other, __soc_is_irq)
+	/* Read mcause and check if interrupt bit is set */
+	csrr t0, mcause
+	li t1, SOC_MCAUSE_IRQ_MASK
+	and t0, t0, t1
+
+	/* If interrupt bit is not set, return with 0 */
+	addi a0, x0, 0
+	beqz t0, not_interrupt
+	addi a0, a0, 1
+
+not_interrupt:
+	/* return */
+	jalr x0, ra
diff --git a/soc/bouffalolab/common/vector.S b/soc/bouffalolab/common/vector.S
new file mode 100644
index 00000000000..898856f36e8
--- /dev/null
+++ b/soc/bouffalolab/common/vector.S
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2021-2025 Gerson Fernando Budke <nandojve@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/toolchain.h>
+#include <zephyr/arch/riscv/csr.h>
+
+/* exports */
+GTEXT(__start)
+
+/* imports */
+GTEXT(__initialize)
+GTEXT(_isr_wrapper)
+
+SECTION_FUNC(vectors, __start)
+	.cfi_startproc
+
+	.option norvc
+
+	/* Inform the debugger that there is nowhere to backtrace */
+	.cfi_undefined ra
+
+	/* Disable interrupts */
+	li t0, MSTATUS_MIE
+	csrc mstatus, t0
+
+	/*
+	 * Set mtvec (Machine Trap-Vector Base-Address Register)
+	 *	CLINT Direct mode
+	 */
+	la t0, _isr_wrapper
+	csrw mtvec, t0
+
+	/* Jump to __initialize */
+	tail __initialize
+
+	.cfi_endproc
diff --git a/soc/bouffalolab/soc.yml b/soc/bouffalolab/soc.yml
new file mode 100644
index 00000000000..8aafe0d4367
--- /dev/null
+++ b/soc/bouffalolab/soc.yml
@@ -0,0 +1,13 @@
+family:
+- name: bouffalolab_bflb
+  series:
+  - name: bl60x
+    socs:
+    - name: bl602c00q2i
+    - name: bl602c20q2i
+    - name: bl602c20q2is
+    - name: bl602c40q2is
+    - name: bl602l10q2h
+    - name: bl602l20q2h
+    - name: bl604e20q2i
+vendor: bflb
diff --git a/soc/cdns/dc233c/Kconfig b/soc/cdns/dc233c/Kconfig
index c0becdd0ba4..df5f3ab2e64 100644
--- a/soc/cdns/dc233c/Kconfig
+++ b/soc/cdns/dc233c/Kconfig
@@ -13,4 +13,3 @@ config SOC_XTENSA_DC233C
 	select ARCH_HAS_USERSPACE if XTENSA_MMU
 	select ARCH_SUPPORTS_COREDUMP
 	select ARCH_SUPPORTS_COREDUMP_PRIV_STACKS
-	select XTENSA_INVALIDATE_MEM_DOMAIN_TLB_ON_SWAP if XTENSA_MMU
diff --git a/soc/cdns/dc233c/include/xtensa-dc233c.ld b/soc/cdns/dc233c/include/xtensa-dc233c.ld
index fee4ace0282..83ab002e976 100644
--- a/soc/cdns/dc233c/include/xtensa-dc233c.ld
+++ b/soc/cdns/dc233c/include/xtensa-dc233c.ld
@@ -162,7 +162,6 @@ SECTIONS
 
     /* Userspace related stuff */
     LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,userspace.S.obj,xtensa_do_syscall)
-    LIB_OBJ_FUNC_IN_SECT(libarch__xtensa__core.a,ptables.c.obj,xtensa_swap_update_page_tables)
 
     /* Below are to speed up execution by avoiding TLB misses
      * on frequently used functions.
diff --git a/soc/cdns/sample_controller32/Kconfig.defconfig b/soc/cdns/sample_controller32/Kconfig.defconfig
new file mode 100644
index 00000000000..70a570f9624
--- /dev/null
+++ b/soc/cdns/sample_controller32/Kconfig.defconfig
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_XTENSA_SAMPLE_CONTROLLER32
+
+# CONFIG_PRIVILEGED_STACK_SIZE must be aligned as specified by XCHAL_MPU_ALIGN.
+# For `sample_controller32`, that value is equal to 4096
+config PRIVILEGED_STACK_SIZE
+	default 4096 if XTENSA_MPU
+
+endif # SOC_XTENSA_SAMPLE_CONTROLLER32
diff --git a/soc/common/riscv-privileged/vector.S b/soc/common/riscv-privileged/vector.S
index 7230561a340..1cd5a18b07c 100644
--- a/soc/common/riscv-privileged/vector.S
+++ b/soc/common/riscv-privileged/vector.S
@@ -27,6 +27,10 @@ SECTION_FUNC(vectors, __start)
 
 	.option norvc;
 
+#if defined(CONFIG_SOC_RESET_HOOK)
+	call soc_reset_hook
+#endif
+
 #if defined(CONFIG_RISCV_VECTORED_MODE)
 #if defined(CONFIG_RISCV_HAS_CLIC)
 
diff --git a/soc/ene/kb1200/reg/fsmbm.h b/soc/ene/kb1200/reg/fsmbm.h
index 33f96ae0c0e..129fbae71b4 100644
--- a/soc/ene/kb1200/reg/fsmbm.h
+++ b/soc/ene/kb1200/reg/fsmbm.h
@@ -58,28 +58,27 @@ struct fsmbm_regs {
 #define FSMBM_SMBUS_BUSY                0x1A
 #define FSMBM_STOP_FAIL                 0x1E
 #define FSMBM_PEC_ERROR                 0x1F
+#define FSMBM_SDA_TIMEOUT               0x80
+#define FSMBM_MAX_TIMEOUT               200         /* Unit: ms */
+
 /* Packet Form */
-#define ___NONE                         0x00
-#define ___STOP                         0x01
-#define __PEC_                          0x02
-#define __PEC_STOP                      0x03
-#define _CNT__                          0x04
-#define _CNT__STOP                      0x05
-#define _CNT_PEC_                       0x06
-#define _CNT_PEC_STOP                   0x07
-#define CMD___                          0x08
-#define CMD___STOP                      0x09
-#define CMD__PEC_                       0x0A
-#define CMD__PEC_STOP                   0x0B
-#define CMD_CNT__                       0x0C
-#define CMD_CNT__STOP                   0x0D
-#define CMD_CNT_PEC_                    0x0E
-#define CMD_CNT_PEC_STOP                0x0F
+#define FRT_NONE                        0x00
+#define FRT_STOP                        0x01
+#define FRT_PEC                         0x02
+#define FRT_CNT                         0x04
+#define FRT_CMD                         0x08
+#define FRT_PEC_STOP                    (FRT_PEC | FRT_STOP)
+#define FRT_CNT_STOP                    (FRT_CNT | FRT_STOP)
+#define FRT_CNT_PEC                     (FRT_CNT | FRT_PEC)
+#define FRT_CNT_PEC_STOP                (FRT_CNT | FRT_PEC | FRT_STOP)
+#define FRT_CMD_STOP                    (FRT_CMD | FRT_STOP)
+#define FRT_CMD_PEC                     (FRT_CMD | FRT_PEC)
+#define FRT_CMD_PEC_STOP                (FRT_CMD | FRT_PEC | FRT_STOP)
+#define FRT_CMD_CNT                     (FRT_CMD | FRT_CNT)
+#define FRT_CMD_CNT_STOP                (FRT_CMD | FRT_CNT | FRT_STOP)
+#define FRT_CMD_CNT_PEC                 (FRT_CMD | FRT_CNT | FRT_PEC)
+#define FRT_CMD_CNT_PEC_STOP            (FRT_CMD | FRT_CNT | FRT_PEC | FRT_STOP)
 
-#define FLEXIBLE_CMD                    0x08
-#define FLEXIBLE_CNT                    0x04
-#define FLEXIBLE_PEC                    0x02
-#define FLEXIBLE_STOP                   0x01
 /* HW */
 #define FSMBM_BUFFER_SIZE               0x20
 #define FSMBM_MAXCNT                    0xFF
@@ -109,6 +108,7 @@ struct fsmbm_regs {
 #define FSMBM_CLK_10K                   0x6363
 /* Other(non 50% Duty Cycle) */
 #define FSMBM_CLK_400K                  0x0102
+#define FSMBM_CLK_666K                  0x0001
 
 #define FSMBM_COMPLETE_EVENT            0x01
 #define FSMBM_HOST_NOTIFY_EVENT         0x02
diff --git a/soc/espressif/Kconfig b/soc/espressif/Kconfig
index 1efa0169ee6..483ac468b67 100644
--- a/soc/espressif/Kconfig
+++ b/soc/espressif/Kconfig
@@ -35,6 +35,12 @@ endmenu
 
 menu "RTC Clock Config"
 
+config RESERVE_RTC_MEM
+	int
+	default 0
+	help
+	  This option reserves an area in RTC FAST memory.
+
 config RTC_CLK_CAL_CYCLES
 	int "Number of cycles for RTC_SLOW_CLK calibration"
 	default 3000
@@ -56,4 +62,6 @@ config RTC_CLK_CAL_CYCLES
 	    If the crystal could not start, it will be switched to internal RC.
 endmenu
 
+rsource "Kconfig.ulp"
+
 endif # SOC_FAMILY_ESPRESSIF_ESP32
diff --git a/soc/espressif/Kconfig.ulp b/soc/espressif/Kconfig.ulp
new file mode 100644
index 00000000000..55d50fc7284
--- /dev/null
+++ b/soc/espressif/Kconfig.ulp
@@ -0,0 +1,87 @@
+# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+menu "Ultra Low Power (ULP) Coprocessor"
+
+config ULP_COPROC_ENABLED
+	bool "Ultra Low Power (ULP) Coprocessor"
+	default y if SOC_ESP32C6_LPCORE
+	select SOC_LATE_INIT_HOOK if SOC_ESP32C6_HPCORE
+	help
+	  Enable this feature if you plan to use the ULP Coprocessor.
+	  Once this option is enabled, further ULP co-processor configuration will appear in the menu.
+
+choice ULP_COPROC_TYPE
+	prompt "ULP Coprocessor type"
+	depends on ULP_COPROC_ENABLED
+	default ULP_COPROC_TYPE_LP_CORE if SOC_SERIES_ESP32C6
+	help
+	  Choose the ULP Coprocessor type: ULP FSM (Finite State Machine) or ULP RISC-V.
+
+config ULP_COPROC_TYPE_FSM
+	bool "ULP FSM (Finite State Machine)"
+	depends on SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
+
+config ULP_COPROC_TYPE_RISCV
+	bool "ULP RISC-V"
+	depends on SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
+
+config ULP_COPROC_TYPE_LP_CORE
+	bool "LP core RISC-V"
+	depends on SOC_SERIES_ESP32C6
+endchoice
+
+menu "ULP RISC-V Settings"
+	depends on ULP_COPROC_TYPE_RISCV
+
+config ULP_RISCV_INTERRUPT_ENABLE
+	bool "ULP RISC-V interrupts"
+	help
+	  Turn on this setting to enabled interrupts on the ULP RISC-V core.
+
+endmenu
+
+menu "ULP Debugging Options"
+
+config ULP_PANIC_OUTPUT_ENABLE
+	bool "Panic handler outputs to LP UART"
+	depends on ULP_COPROC_TYPE_LP_CORE
+	help
+	  Set this option to enable panic handler functionality. If this option is
+	  enabled then the LP Core will output a panic dump over LP UART,
+	  similar to what the main core does. Output depends on LP UART already being
+	  initialized and configured.
+	  Disabling this option will reduce the LP core binary size by not
+	  linking in panic handler functionality.
+
+config ULP_HP_UART_CONSOLE_PRINT
+	bool "Route lp_core_printf to the console HP-UART"
+	depends on ULP_COPROC_TYPE_LP_CORE
+	help
+	  Set this option to route lp_core_printf to the console HP-UART.
+	  This allows you to easily view print outputs from the LP core, without
+	  having to connect to the LP-UART. This option comes with the following
+	  limitations:
+
+	  1. There is no mutual exclusion between the HP-Core and the LP-Core accessing
+	  the HP-UART, which means that if both cores are logging heavily the output
+	  strings might get mangled together.
+	  2. The HP-UART can only work while the HP-Core is running, which means that
+	  if the HP-Core is in deep sleep, the LP-Core will not be able to print to the
+	  console HP-UART.
+
+	  Due to these limitations it is only recommended to use this option for easy debugging.
+	  For more serious use-cases you should use the LP-UART.
+
+config ULP_NORESET_UNDER_DEBUG
+	bool "Avoid resetting LP core when debugger is attached"
+	depends on ULP_COPROC_TYPE_LP_CORE
+	default y
+	help
+	  Enable this feature to avoid resetting LP core in sleep mode when debugger is attached,
+	  otherwise configured HW breakpoints and dcsr.ebreak* bits will be missed.
+	  This is a workaround until it will be fixed in HW.
+
+endmenu
+
+endmenu  # Ultra Low Power (ULP) Coprocessor
diff --git a/soc/espressif/common/CMakeLists.txt b/soc/espressif/common/CMakeLists.txt
index 4cd6217126a..ab9558b9d18 100644
--- a/soc/espressif/common/CMakeLists.txt
+++ b/soc/espressif/common/CMakeLists.txt
@@ -4,6 +4,84 @@
 zephyr_include_directories(include)
 
 if(NOT CONFIG_MCUBOOT AND NOT CONFIG_SOC_ESP32_APPCPU AND NOT CONFIG_SOC_ESP32S3_APPCPU)
-  zephyr_sources_ifdef(CONFIG_ESP_HEAP_RUNTIME esp_heap_runtime.c)
   zephyr_sources_ifdef(CONFIG_ESP_SPIRAM esp_psram.c)
 endif()
+
+# Get flash size to use in esptool as string
+math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000")
+
+# Get UART baudrate from DT
+dt_chosen(dts_shell_uart PROPERTY "zephyr,shell-uart")
+if(DEFINED dts_shell_uart AND dts_shell_uart)
+  dt_prop(monitor_baud PATH ${dts_shell_uart} PROPERTY "current-speed")
+endif()
+
+message("-- Espressif HAL path: ${ESP_IDF_PATH}")
+
+if((CONFIG_ESP_SIMPLE_BOOT OR CONFIG_MCUBOOT) AND NOT CONFIG_SOC_ESP32C6_LPCORE)
+  if(CONFIG_BUILD_OUTPUT_BIN)
+    set(ESPTOOL_PY ${ESP_IDF_PATH}/tools/esptool_py/esptool.py)
+    message("-- Use the esptool.py: ${ESPTOOL_PY}")
+
+    set(ELF2IMAGE_ARG "")
+    if(NOT CONFIG_MCUBOOT)
+      set(ELF2IMAGE_ARG "--ram-only-header")
+    endif()
+
+    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+      COMMAND ${PYTHON_EXECUTABLE} ${ESPTOOL_PY}
+      ARGS --chip ${CONFIG_SOC} elf2image ${ELF2IMAGE_ARG}
+      --flash_mode dio
+      --flash_freq ${CONFIG_ESPTOOLPY_FLASHFREQ}
+      --flash_size ${esptoolpy_flashsize}MB
+      -o ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_BIN_NAME}
+      ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME})
+  endif()
+endif()
+
+set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
+
+# Select the image origin depending on the boot configuration
+if(CONFIG_SOC_ESP32_APPCPU OR CONFIG_SOC_ESP32S3_APPCPU)
+  dt_nodelabel(dts_partition_path NODELABEL "slot0_appcpu_partition")
+elseif(CONFIG_SOC_ESP32C6_LPCORE)
+  dt_nodelabel(dts_partition_path NODELABEL "slot0_lpcore_partition")
+elseif(CONFIG_MCUBOOT OR CONFIG_ESP_SIMPLE_BOOT)
+  dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
+else()
+  dt_nodelabel(dts_partition_path NODELABEL "slot0_partition")
+endif()
+
+dt_reg_addr(image_off PATH ${dts_partition_path})
+board_runner_args(esp32 "--esp-app-address=${image_off}")
+board_runner_args(esp32 "--esp-flash-size=${esptoolpy_flashsize}MB")
+board_runner_args(esp32 "--esp-flash-freq=${CONFIG_ESPTOOLPY_FLASHFREQ}")
+board_runner_args(esp32 "--esp-flash-mode=${CONFIG_ESPTOOLPY_FLASHMODE}")
+board_finalize_runner_args(esp32 "--esp-monitor-baud=${monitor_baud}")
+
+message("-- Image partition ${dts_partition_path}")
+
+# Look for cross references between bootloader sections
+if(CONFIG_MCUBOOT)
+    message("check_callgraph using: ${ESP_IDF_PATH}/tools/ci/check_callgraph.py")
+    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+      COMMAND
+        ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/ci/check_callgraph.py
+      ARGS
+        --rtl-dirs ${CMAKE_BINARY_DIR}/zephyr
+        --elf-file ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
+        find-refs
+        --from-section='.iram0.loader_text'
+        --to-section='.iram0.text'
+        --exit-code)
+endif()
+
+if(CONFIG_MCUBOOT)
+  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/../${CONFIG_SOC}/mcuboot.ld CACHE INTERNAL "")
+elseif(CONFIG_SOC_ESP32_APPCPU OR CONFIG_SOC_ESP32S3_APPCPU)
+  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/../${CONFIG_SOC}/default_appcpu.ld CACHE INTERNAL "")
+elseif(CONFIG_SOC_ESP32C6_LPCORE)
+  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/../${CONFIG_SOC}/default_lpcore.ld CACHE INTERNAL "")
+else()
+  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/../${CONFIG_SOC}/default.ld CACHE INTERNAL "")
+endif()
diff --git a/soc/espressif/common/Kconfig b/soc/espressif/common/Kconfig
index e33aa2e0f38..555085435c3 100644
--- a/soc/espressif/common/Kconfig
+++ b/soc/espressif/common/Kconfig
@@ -24,14 +24,6 @@ config ESP_SIMPLE_BOOT
 	  Please note that this method brings the system up with all memories set-up, but
 	  all other features, such as secure boot OTA or slots management are not available.
 
-config ESP_HEAP_RUNTIME
-	bool
-	default y
-	help
-	  Enabling this will allocate SRAM area starting from the last linked data at the symbolic `_end`,
-	  ending at the last memory location that can be safely accessed (depending on a boot mode).
-	  This is a memory pool used in runtime to create a new heap memory.
-
 config ESP32_TIMER_TASK_STACK_SIZE
 	int "Stack size of the high resolution ESP Timer"
 	default 4096
@@ -56,9 +48,20 @@ config ESP32_PHY_MAX_TX_POWER
 	  Set maximum transmit power for Wi-Fi radio. Actual transmit power for high
 	  data rates may be lower than this setting.
 
+config ESP32_SW_COEXIST_ENABLE
+	bool "Software controls Wi-Fi/Bluetooth coexistence"
+	default y if (BT_ESP32 && WIFI_ESP32)
+	help
+	  If enabled, Wi-Fi & Bluetooth coexistence is controlled by software rather than hardware.
+	  Recommended for heavy traffic scenarios. Both coexistence configuration options are
+	  automatically managed, no user intervention is required.
+	  If only Bluetooth is used, it is recommended to disable this option to reduce binary file
+	  size.
+
 endif
 
 rsource "Kconfig.amp"
+rsource "Kconfig.console"
 rsource "Kconfig.spiram"
 rsource "Kconfig.esptool"
 rsource "Kconfig.flash"
diff --git a/soc/espressif/common/Kconfig.amp b/soc/espressif/common/Kconfig.amp
index 236f48c3ad6..cce7c866928 100644
--- a/soc/espressif/common/Kconfig.amp
+++ b/soc/espressif/common/Kconfig.amp
@@ -23,4 +23,16 @@ config ESP_APPCPU_DRAM_SIZE
 	help
 	  Defines APPCPU DRAM area size in bytes.
 
+config ESP_APPCPU_IROM_SIZE
+	hex "ESP32* APPCPU IROM size"
+	default 0x100000
+	help
+	  Defines APPCPU IROM area size in bytes.
+
+config ESP_APPCPU_DROM_SIZE
+	hex "ESP32* APPCPU DRAM size"
+	default 0x100000
+	help
+	  Defines APPCPU DROM area size in bytes.
+
 endmenu # AMP config
diff --git a/soc/espressif/common/Kconfig.console b/soc/espressif/common/Kconfig.console
new file mode 100644
index 00000000000..b6c9b9f0343
--- /dev/null
+++ b/soc/espressif/common/Kconfig.console
@@ -0,0 +1,79 @@
+# Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_ESPRESSIF_ESP32
+
+DT_CHOSEN_Z_CONSOLE := zephyr,console
+
+if !$(dt_chosen_enabled,$(DT_CHOSEN_Z_CONSOLE))
+
+config ESP_CONSOLE_UART_NUM
+	int
+	default -1
+
+config ESP_CONSOLE_UART_BAUDRATE
+	int
+	default 0
+
+endif # !$(dt_chosen_enabled,$(DT_CHOSEN_Z_CONSOLE))
+
+if $(dt_chosen_enabled,$(DT_CHOSEN_Z_CONSOLE))
+
+if $(dt_nodelabel_enabled,uart0)
+	ESP32_UART0_NODE_PATH := $(dt_nodelabel_path,uart0)
+	ESP32_UART0_CURR_SPEED := $(dt_node_int_prop_int,$(ESP32_UART0_NODE_PATH),current-speed)
+endif # $(dt_nodelabel_enabled,uart0)
+
+if $(dt_nodelabel_enabled,uart1)
+	ESP32_UART1_NODE_PATH := $(dt_nodelabel_path,uart1)
+	ESP32_UART1_CURR_SPEED := $(dt_node_int_prop_int,$(ESP32_UART1_NODE_PATH),current-speed)
+endif # $(dt_nodelabel_enabled,uart1)
+
+if $(dt_nodelabel_enabled,uart2)
+	ESP32_UART2_NODE_PATH := $(dt_nodelabel_path,uart2)
+	ESP32_UART2_CURR_SPEED := $(dt_node_int_prop_int,$(ESP32_UART2_NODE_PATH),current-speed)
+endif # $(dt_nodelabel_enabled,uart2)
+
+if $(dt_nodelabel_enabled,usb_serial)
+	ESP32_USB_SERIAL_CURR_SPEED := 1
+
+config ESP_ROM_USB_SERIAL_DEVICE_NUM
+	int
+	default 4 if SOC_SERIES_ESP32S3
+	default 3
+
+endif # $(dt_nodelabel_enabled,usb_serial)
+
+config ESP_CONSOLE_UART
+	bool
+	default y if $(dt_nodelabel_enabled,uart0) && $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CONSOLE)) = $(dt_nodelabel_reg_addr_hex,uart0) || \
+		     $(dt_nodelabel_enabled,uart1) && $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CONSOLE)) = $(dt_nodelabel_reg_addr_hex,uart1) || \
+		     $(dt_nodelabel_enabled,uart2) && $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CONSOLE)) = $(dt_nodelabel_reg_addr_hex,uart2)
+
+config ESP_CONSOLE_USB_SERIAL_JTAG
+	bool
+	default y if $(dt_nodelabel_enabled,usb_serial) && $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CONSOLE)) = $(dt_nodelabel_reg_addr_hex,usb_serial)
+
+config ESP_CONSOLE_UART_NUM
+	int
+	default 0 if $(dt_nodelabel_enabled,uart0) && $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CONSOLE)) = $(dt_nodelabel_reg_addr_hex,uart0)
+	default 1 if $(dt_nodelabel_enabled,uart1) && $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CONSOLE)) = $(dt_nodelabel_reg_addr_hex,uart1)
+	default 2 if $(dt_nodelabel_enabled,uart2) && $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CONSOLE)) = $(dt_nodelabel_reg_addr_hex,uart2)
+	default ESP_ROM_USB_SERIAL_DEVICE_NUM if $(dt_nodelabel_enabled,usb_serial) && $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CONSOLE)) = $(dt_nodelabel_reg_addr_hex,usb_serial)
+	default -1
+
+config ESP_CONSOLE_UART_BAUDRATE
+	int
+	default $(ESP32_UART0_CURR_SPEED) if $(dt_nodelabel_enabled,uart0) && $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CONSOLE)) = $(dt_nodelabel_reg_addr_hex,uart0)
+	default $(ESP32_UART1_CURR_SPEED) if $(dt_nodelabel_enabled,uart1) && $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CONSOLE)) = $(dt_nodelabel_reg_addr_hex,uart1)
+	default $(ESP32_UART2_CURR_SPEED) if $(dt_nodelabel_enabled,uart2) && $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CONSOLE)) = $(dt_nodelabel_reg_addr_hex,uart2)
+	default $(ESP32_USB_SERIAL_CURR_SPEED) if $(dt_nodelabel_enabled,usb_serial) && $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CONSOLE)) = $(dt_nodelabel_reg_addr_hex,usb_serial)
+	default 0
+
+config ESP_CONSOLE
+	bool
+	default y if ESP_CONSOLE_UART || ESP_CONSOLE_USB_SERIAL_JTAG
+
+endif # $(dt_chosen_enabled,$(DT_CHOSEN_Z_CONSOLE))
+
+endif # SOC_FAMILY_ESPRESSIF_ESP32
diff --git a/soc/espressif/common/Kconfig.defconfig b/soc/espressif/common/Kconfig.defconfig
index 9e33c4ff7ea..bcc34a1a52c 100644
--- a/soc/espressif/common/Kconfig.defconfig
+++ b/soc/espressif/common/Kconfig.defconfig
@@ -4,7 +4,7 @@
 if SOC_SERIES_ESP32C2 || SOC_SERIES_ESP32C3 || SOC_SERIES_ESP32C6
 
 config GEN_ISR_TABLES
-	default y
+	default y if !SOC_ESP32C6_LPCORE
 
 config GEN_SW_ISR_TABLE
 	default y
@@ -13,7 +13,7 @@ config GEN_IRQ_VECTOR_TABLE
 	default n
 
 config DYNAMIC_INTERRUPTS
-	default y
+	default y if !SOC_ESP32C6_LPCORE
 
 config ISR_STACK_SIZE
 	default 2048
diff --git a/soc/espressif/common/Kconfig.spiram b/soc/espressif/common/Kconfig.spiram
index 94dcf9a1676..1222b9261d9 100644
--- a/soc/espressif/common/Kconfig.spiram
+++ b/soc/espressif/common/Kconfig.spiram
@@ -3,6 +3,8 @@
 
 if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S2 || SOC_SERIES_ESP32S3
 
+ESP32_PSRAM0_NODE_PATH := $(dt_nodelabel_path,psram0)
+
 config ESP_SPIRAM
 	bool "Support for external, SPI-connected RAM"
 	default n if MCUBOOT
@@ -15,14 +17,6 @@ config ESP_SPIRAM
 menu "SPI RAM config"
 	depends on ESP_SPIRAM
 
-config ESP_HEAP_SEARCH_ALL_REGIONS
-	bool "Search for all available heap regions"
-	default y
-	help
-	  This configuration enables searching all available heap
-	  regions. If the region of desired capability is exhausted,
-	  memory will be allocated from other available region.
-
 config ESP_SPIRAM_HEAP_SIZE
 	int "Size of SPIRAM heap"
 	default 262134 if SYS_HEAP_SMALL_ONLY
@@ -56,26 +50,26 @@ choice SPIRAM_TYPE
 
 config SPIRAM_TYPE_ESPPSRAM16
 	bool "ESP-PSRAM16 or APS1604"
-	depends on SPIRAM_MODE_QUAD
+	depends on SPIRAM_MODE_QUAD && (ESP_SPIRAM_SIZE = 2097152)
 
 config SPIRAM_TYPE_ESPPSRAM32
 	bool "ESP-PSRAM32 or IS25WP032"
-	depends on SPIRAM_MODE_QUAD
+	depends on SPIRAM_MODE_QUAD && (ESP_SPIRAM_SIZE = 4194304)
 
 config SPIRAM_TYPE_ESPPSRAM64
 	bool "ESP-PSRAM64, LY68L6400 or APS6408"
+	depends on (ESP_SPIRAM_SIZE = 8388608)
 
 endchoice # SPIRAM_TYPE
 
 config ESP_SPIRAM_SIZE
 	int "Size of SPIRAM part"
-	default 2097152 if SPIRAM_TYPE_ESPPSRAM16
-	default 4194304 if SPIRAM_TYPE_ESPPSRAM32
-	default 8388608 if SPIRAM_TYPE_ESPPSRAM64
+	default $(dt_node_int_prop_int,$(ESP32_PSRAM0_NODE_PATH),size) if $(dt_nodelabel_enabled,psram0)
+	default 0
 	help
 	  Specify size of SPIRAM part.
-	  NOTE: If SPIRAM size is greater than 4MB, only
-	  lower 4MB can be allocated using k_malloc().
+	  NOTE: In ESP32, if SPIRAM size is greater than 4MB,
+	  only lower 4MB can be allocated using k_malloc().
 
 choice SPIRAM_SPEED
 	prompt "Set RAM clock speed"
diff --git a/soc/espressif/common/esp_heap_runtime.c b/soc/espressif/common/esp_heap_runtime.c
deleted file mode 100644
index 210e714c792..00000000000
--- a/soc/espressif/common/esp_heap_runtime.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <stddef.h>
-#include <stdint.h>
-#include <string.h>
-#include <zephyr/types.h>
-#include <zephyr/kernel.h>
-#include <soc.h>
-#include <esp_err.h>
-#include <esp_heap_runtime.h>
-#include "esp_log.h"
-
-#define TAG "heap_runtime"
-
-/* ESP dynamic pool heap */
-extern unsigned int z_mapped_end;
-extern unsigned int _heap_sentry;
-static void *esp_heap_runtime_init_mem = &z_mapped_end;
-
-#define ESP_HEAP_RUNTIME_MAX_SIZE ((uintptr_t)&_heap_sentry - (uintptr_t)&z_mapped_end)
-
-static struct k_heap esp_heap_runtime;
-
-static int esp_heap_runtime_init(void)
-{
-	ESP_EARLY_LOGI(TAG, "ESP heap runtime init at 0x%x size %d kB.\n",
-		       esp_heap_runtime_init_mem, ESP_HEAP_RUNTIME_MAX_SIZE / 1024);
-
-	k_heap_init(&esp_heap_runtime, esp_heap_runtime_init_mem, ESP_HEAP_RUNTIME_MAX_SIZE);
-
-#if defined(CONFIG_WIFI_ESP32) && defined(CONFIG_BT_ESP32)
-	assert(ESP_HEAP_RUNTIME_MAX_SIZE > 65535);
-#elif defined(CONFIG_WIFI_ESP32)
-	assert(ESP_HEAP_RUNTIME_MAX_SIZE > 51200);
-#elif defined(CONFIG_BT_ESP32)
-	assert(ESP_HEAP_RUNTIME_MAX_SIZE > 40960);
-#endif
-
-	return 0;
-}
-
-void *esp_heap_runtime_malloc(size_t size)
-{
-	return k_heap_alloc(&esp_heap_runtime, size, K_NO_WAIT);
-}
-
-void *esp_heap_runtime_calloc(size_t n, size_t size)
-{
-	size_t sz;
-
-	if (__builtin_mul_overflow(n, size, &sz)) {
-		return NULL;
-	}
-	void *ptr = k_heap_alloc(&esp_heap_runtime, sz, K_NO_WAIT);
-
-	if (ptr) {
-		memset(ptr, 0, sz);
-	}
-
-	return ptr;
-}
-
-void *esp_heap_runtime_realloc(void *ptr, size_t bytes)
-{
-	return k_heap_realloc(&esp_heap_runtime, ptr, bytes, K_NO_WAIT);
-}
-
-void esp_heap_runtime_free(void *mem)
-{
-	k_heap_free(&esp_heap_runtime, mem);
-}
-
-SYS_INIT(esp_heap_runtime_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
diff --git a/soc/espressif/common/esp_psram.c b/soc/espressif/common/esp_psram.c
index 37e814fcc76..aa3b01c8b93 100644
--- a/soc/espressif/common/esp_psram.c
+++ b/soc/espressif/common/esp_psram.c
@@ -10,22 +10,19 @@
 #include <esp_private/esp_psram_extram.h>
 #include <zephyr/multi_heap/shared_multi_heap.h>
 
-#define PSRAM_ADDR (DT_REG_ADDR(DT_NODELABEL(psram0)))
-
-extern int _spiram_heap_start;
 extern int _ext_ram_bss_start;
 extern int _ext_ram_bss_end;
+extern int _ext_ram_heap_start;
 
 struct shared_multi_heap_region smh_psram = {
-	.addr = (uintptr_t)&_spiram_heap_start,
-	.size = CONFIG_ESP_SPIRAM_SIZE,
+	.addr = (uintptr_t)&_ext_ram_heap_start,
+	.size = CONFIG_ESP_SPIRAM_HEAP_SIZE,
 	.attr = SMH_REG_ATTR_EXTERNAL,
 };
 
 int esp_psram_smh_init(void)
 {
 	shared_multi_heap_pool_init();
-	smh_psram.size = CONFIG_ESP_SPIRAM_SIZE - ((int)&_spiram_heap_start - PSRAM_ADDR);
 	return shared_multi_heap_add(&smh_psram, NULL);
 }
 
diff --git a/soc/espressif/common/include/esp_heap_runtime.h b/soc/espressif/common/include/esp_heap_runtime.h
deleted file mode 100644
index 11f7139b715..00000000000
--- a/soc/espressif/common/include/esp_heap_runtime.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @brief Allocate memory from the esp_heap_runtime.
- *
- * @param size Amount of memory requested (in bytes).
- *
- * @return Address of the allocated memory if successful; otherwise NULL.
- */
-void *esp_heap_runtime_malloc(size_t size);
-
-/**
- * @brief Allocate memory from esp_heap_runtime, array style
- *
- * @param n Number of elements in the requested array
- * @param size Size of each array element (in bytes).
- *
- * @return Address of the allocated memory if successful; otherwise NULL.
- */
-void *esp_heap_runtime_calloc(size_t n, size_t size);
-
-/**
- * @brief Reallocate memory from a esp_heap_runtime
- *
- * @param ptr Original pointer returned from a previous allocation
- * @param bytes Desired size of block to allocate
- *
- * @return Pointer to memory the caller can now use, or NULL
- */
-void *esp_heap_runtime_realloc(void *ptr, size_t bytes);
-
-/**
- * @brief Free memory allocated from esp_heap_runtime.
- *
- * If @a ptr is NULL, no operation is performed.
- *
- * @param ptr Pointer to previously allocated memory.
- */
-void esp_heap_runtime_free(void *mem);
diff --git a/soc/espressif/common/include/hw_init.h b/soc/espressif/common/include/hw_init.h
index 1c318fdb826..3c7cf807b6d 100644
--- a/soc/espressif/common/include/hw_init.h
+++ b/soc/espressif/common/include/hw_init.h
@@ -7,6 +7,17 @@
 #ifndef _SOC_ESPRESSIF_COMMON_HW_INIT_H_
 #define _SOC_ESPRESSIF_COMMON_HW_INIT_H_
 
+struct rom_segments {
+	unsigned int irom_map_addr;     /* Mapped address (VMA) for IROM region */
+	unsigned int irom_flash_offset; /* Flash offset (LMA) for IROM region */
+	unsigned int irom_size;         /* Size of IROM region */
+	unsigned int drom_map_addr;     /* Mapped address (VMA) for DROM region */
+	unsigned int drom_flash_offset; /* Flash offset (LMA) for DROM region */
+	unsigned int drom_size;         /* Size of DROM region */
+};
+
+void map_rom_segments(int core, struct rom_segments *map);
+
 int hardware_init(void);
 
 #endif /* _SOC_ESPRESSIF_COMMON_HW_INIT_H_ */
diff --git a/soc/espressif/common/loader.c b/soc/espressif/common/loader.c
index 792eb959608..624fa987542 100644
--- a/soc/espressif/common/loader.c
+++ b/soc/espressif/common/loader.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -21,9 +21,11 @@
 #include <esp_log.h>
 #include <bootloader_clock.h>
 #include <bootloader_common.h>
-
 #include <esp_cpu.h>
 
+#include <zephyr/linker/linker-defs.h>
+#include <kernel_internal.h>
+
 #if CONFIG_SOC_SERIES_ESP32C6
 #include <soc/hp_apm_reg.h>
 #include <soc/lp_apm_reg.h>
@@ -48,21 +50,36 @@
 #include "soc_init.h"
 #include "soc_random.h"
 
+#if defined(CONFIG_SOC_ESP32S3_APPCPU) || defined(CONFIG_SOC_ESP32_APPCPU)
+#error "APPCPU does not need this file!"
+#endif
+
 #define TAG "boot"
 
 #define CHECKSUM_ALIGN 16
-#define IS_PADD(addr)  (addr == 0)
-#define IS_DRAM(addr)  (addr >= SOC_DRAM_LOW && addr < SOC_DRAM_HIGH)
-#define IS_IRAM(addr)  (addr >= SOC_IRAM_LOW && addr < SOC_IRAM_HIGH)
-#define IS_IROM(addr)  (addr >= SOC_IROM_LOW && addr < SOC_IROM_HIGH)
-#define IS_DROM(addr)  (addr >= SOC_DROM_LOW && addr < SOC_DROM_HIGH)
-#define IS_SRAM(addr)  (IS_IRAM(addr) || IS_DRAM(addr))
-#define IS_MMAP(addr)  (IS_IROM(addr) || IS_DROM(addr))
-#define IS_NONE(addr)                                                                              \
-	(!IS_IROM(addr) && !IS_DROM(addr) && !IS_IRAM(addr) && !IS_DRAM(addr) && !IS_PADD(addr))
+#define IS_PADD(addr) (addr == 0)
+#define IS_DRAM(addr) (addr >= SOC_DRAM_LOW && addr < SOC_DRAM_HIGH)
+#define IS_IRAM(addr) (addr >= SOC_IRAM_LOW && addr < SOC_IRAM_HIGH)
+#define IS_IROM(addr) (addr >= SOC_IROM_LOW && addr < SOC_IROM_HIGH)
+#define IS_DROM(addr) (addr >= SOC_DROM_LOW && addr < SOC_DROM_HIGH)
+#ifdef SOC_RTC_MEM_SUPPORTED
+#define IS_RTC(addr) (addr >= SOC_RTC_DRAM_LOW && addr < SOC_RTC_DRAM_HIGH)
+#else
+#define IS_RTC(addr) 0
+#endif
+#define IS_SRAM(addr) (IS_IRAM(addr) || IS_DRAM(addr))
+#define IS_MMAP(addr) (IS_IROM(addr) || IS_DROM(addr))
+#define IS_NONE(addr) (!IS_IROM(addr) && !IS_DROM(addr) \
+			&& !IS_IRAM(addr) && !IS_DRAM(addr) && !IS_PADD(addr) && !IS_RTC(addr))
 
 #define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used))
 
+#if !defined(CONFIG_SOC_ESP32_APPCPU) && !defined(CONFIG_SOC_ESP32S3_APPCPU)
+#define PART_OFFSET FIXED_PARTITION_OFFSET(slot0_partition)
+#else
+#define PART_OFFSET FIXED_PARTITION_OFFSET(slot0_appcpu_partition)
+#endif
+
 void __start(void);
 static HDR_ATTR void (*_entry_point)(void) = &__start;
 
@@ -71,34 +88,28 @@ extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr;
 extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr;
 
 #ifndef CONFIG_MCUBOOT
-static uint32_t _app_irom_start =
-	(FIXED_PARTITION_OFFSET(slot0_partition) + (uint32_t)&_image_irom_start);
-static uint32_t _app_irom_size = (uint32_t)&_image_irom_size;
 
-static uint32_t _app_drom_start =
-	(FIXED_PARTITION_OFFSET(slot0_partition) + (uint32_t)&_image_drom_start);
-static uint32_t _app_drom_size = (uint32_t)&_image_drom_size;
-#endif
-
-static uint32_t _app_irom_vaddr = ((uint32_t)&_image_irom_vaddr);
-static uint32_t _app_drom_vaddr = ((uint32_t)&_image_drom_vaddr);
+extern uint32_t _libc_heap_size;
+static uint32_t libc_heap_size = (uint32_t)&_libc_heap_size;
 
-#ifndef CONFIG_BOOTLOADER_MCUBOOT
-static int spi_flash_read(uint32_t address, void *buffer, size_t length)
-{
-	return esp_flash_read(NULL, buffer, address, length);
-}
-#endif /* CONFIG_BOOTLOADER_MCUBOOT */
+static struct rom_segments map = {
+	.irom_map_addr = (uint32_t)&_image_irom_vaddr,
+	.irom_flash_offset = PART_OFFSET + (uint32_t)&_image_irom_start,
+	.irom_size = (uint32_t)&_image_irom_size,
+	.drom_map_addr = ((uint32_t)&_image_drom_vaddr),
+	.drom_flash_offset = PART_OFFSET + (uint32_t)&_image_drom_start,
+	.drom_size = (uint32_t)&_image_drom_size,
+};
 
-void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, uint32_t app_drom_size,
-		      uint32_t app_irom_start, uint32_t app_irom_vaddr, uint32_t app_irom_size)
+void map_rom_segments(int core, struct rom_segments *map)
 {
-	uint32_t app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK;
-	uint32_t app_irom_vaddr_aligned = app_irom_vaddr & MMU_FLASH_MASK;
+	uint32_t app_irom_vaddr_align = map->irom_map_addr & MMU_FLASH_MASK;
+	uint32_t app_irom_start_align = map->irom_flash_offset & MMU_FLASH_MASK;
 
-	uint32_t app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK;
-	uint32_t app_drom_vaddr_aligned = app_drom_vaddr & MMU_FLASH_MASK;
+	uint32_t app_drom_vaddr_align = map->drom_map_addr & MMU_FLASH_MASK;
+	uint32_t app_drom_start_align = map->drom_flash_offset & MMU_FLASH_MASK;
 
+	/* Traverse segments to fix flash offset changes due to post-build processing */
 #ifndef CONFIG_BOOTLOADER_MCUBOOT
 	esp_image_segment_header_t WORD_ALIGNED_ATTR segment_hdr;
 	size_t offset = FIXED_PARTITION_OFFSET(boot_partition);
@@ -110,7 +121,8 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, uint32_t
 
 	while (segments++ < 16) {
 
-		if (spi_flash_read(offset, &segment_hdr, sizeof(esp_image_segment_header_t)) != 0) {
+		if (esp_rom_flash_read(offset, &segment_hdr,
+					      sizeof(esp_image_segment_header_t), true) != 0) {
 			ESP_EARLY_LOGE(TAG, "Failed to read segment header at %x", offset);
 			abort();
 		}
@@ -122,29 +134,29 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, uint32_t
 		}
 
 		ESP_EARLY_LOGI(TAG, "%s: lma 0x%08x vma 0x%08x len 0x%-6x (%u)",
-			       IS_NONE(segment_hdr.load_addr) ? "???"
-			       : IS_MMAP(segment_hdr.load_addr)
-				       ? IS_IROM(segment_hdr.load_addr) ? "IMAP" : "DMAP"
-			       : IS_PADD(segment_hdr.load_addr) ? "padd"
-			       : IS_DRAM(segment_hdr.load_addr) ? "DRAM"
-								: "IRAM",
-			       offset + sizeof(esp_image_segment_header_t), segment_hdr.load_addr,
-			       segment_hdr.data_len, segment_hdr.data_len);
+			IS_NONE(segment_hdr.load_addr) ? "???" :
+			 IS_MMAP(segment_hdr.load_addr) ?
+			  IS_IROM(segment_hdr.load_addr) ? "IMAP" : "DMAP" :
+			    IS_DRAM(segment_hdr.load_addr) ? "DRAM" :
+				IS_RTC(segment_hdr.load_addr) ? "RTC" : "IRAM",
+			offset + sizeof(esp_image_segment_header_t),
+			segment_hdr.load_addr, segment_hdr.data_len, segment_hdr.data_len);
 
 		/* Fix drom and irom produced be the linker, as it could
 		 * be invalidated by the elf2image and flash load offset
 		 */
-		if (segment_hdr.load_addr == _app_drom_vaddr) {
-			app_drom_start = offset + sizeof(esp_image_segment_header_t);
-			app_drom_start_aligned = app_drom_start & MMU_FLASH_MASK;
+		if (segment_hdr.load_addr == map->drom_map_addr) {
+			map->drom_flash_offset = offset + sizeof(esp_image_segment_header_t);
+			app_drom_start_align = map->drom_flash_offset & MMU_FLASH_MASK;
 		}
-		if (segment_hdr.load_addr == _app_irom_vaddr) {
-			app_irom_start = offset + sizeof(esp_image_segment_header_t);
-			app_irom_start_aligned = app_irom_start & MMU_FLASH_MASK;
+		if (segment_hdr.load_addr == map->irom_map_addr) {
+			map->irom_flash_offset = offset + sizeof(esp_image_segment_header_t);
+			app_irom_start_align = map->irom_flash_offset & MMU_FLASH_MASK;
 		}
-		if (IS_SRAM(segment_hdr.load_addr)) {
+		if (IS_SRAM(segment_hdr.load_addr) || IS_RTC(segment_hdr.load_addr)) {
 			ram_segments++;
 		}
+
 		offset += sizeof(esp_image_segment_header_t) + segment_hdr.data_len;
 
 		if (ram_segments == bootloader_image_hdr.segment_count && !checksum) {
@@ -161,8 +173,8 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, uint32_t
 #endif /* !CONFIG_BOOTLOADER_MCUBOOT */
 
 #if CONFIG_SOC_SERIES_ESP32
-	Cache_Read_Disable(0);
-	Cache_Flush(0);
+	Cache_Read_Disable(core);
+	Cache_Flush(core);
 #else
 	cache_hal_disable(CACHE_TYPE_ALL);
 #endif /* CONFIG_SOC_SERIES_ESP32 */
@@ -170,56 +182,56 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, uint32_t
 	/* Clear the MMU entries that are already set up,
 	 * so the new app only has the mappings it creates.
 	 */
-	mmu_hal_unmap_all();
+	if (core == 0) {
+		mmu_hal_unmap_all();
+	}
 
 #if CONFIG_SOC_SERIES_ESP32
 	int rc = 0;
 	uint32_t drom_page_count =
-		(app_drom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE;
+		(map->drom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE;
 
-	rc |= cache_flash_mmu_set(0, 0, app_drom_vaddr_aligned, app_drom_start_aligned, 64,
-				  drom_page_count);
-	rc |= cache_flash_mmu_set(1, 0, app_drom_vaddr_aligned, app_drom_start_aligned, 64,
+	rc |= cache_flash_mmu_set(core, 0, app_drom_vaddr_align, app_drom_start_align, 64,
 				  drom_page_count);
 
 	uint32_t irom_page_count =
-		(app_irom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE;
+		(map->irom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE;
 
-	rc |= cache_flash_mmu_set(0, 0, app_irom_vaddr_aligned, app_irom_start_aligned, 64,
-				  irom_page_count);
-	rc |= cache_flash_mmu_set(1, 0, app_irom_vaddr_aligned, app_irom_start_aligned, 64,
+	rc |= cache_flash_mmu_set(core, 0, app_irom_vaddr_align, app_irom_start_align, 64,
 				  irom_page_count);
 	if (rc != 0) {
-		ESP_EARLY_LOGE(TAG, "Failed to setup XIP, aborting");
+		ESP_EARLY_LOGE(TAG, "Failed to setup flash cache (e=0x%X). Aborting!", rc);
 		abort();
 	}
 #else
 	uint32_t actual_mapped_len = 0;
 
-	mmu_hal_map_region(0, MMU_TARGET_FLASH0, app_drom_vaddr_aligned, app_drom_start_aligned,
-			   app_drom_size, &actual_mapped_len);
+	mmu_hal_map_region(core, MMU_TARGET_FLASH0, app_drom_vaddr_align, app_drom_start_align,
+			   map->drom_size, &actual_mapped_len);
 
-	mmu_hal_map_region(0, MMU_TARGET_FLASH0, app_irom_vaddr_aligned, app_irom_start_aligned,
-			   app_irom_size, &actual_mapped_len);
+	mmu_hal_map_region(core, MMU_TARGET_FLASH0, app_irom_vaddr_align, app_irom_start_align,
+			   map->irom_size, &actual_mapped_len);
 #endif /* CONFIG_SOC_SERIES_ESP32 */
 
 	/* ----------------------Enable corresponding buses---------------- */
-	cache_bus_mask_t bus_mask = cache_ll_l1_get_bus(0, app_drom_vaddr_aligned, app_drom_size);
+	cache_bus_mask_t bus_mask;
+
+	bus_mask = cache_ll_l1_get_bus(core, app_drom_vaddr_align, map->drom_size);
+	cache_ll_l1_enable_bus(core, bus_mask);
+	bus_mask = cache_ll_l1_get_bus(core, app_irom_vaddr_align, map->irom_size);
+	cache_ll_l1_enable_bus(core, bus_mask);
 
-	cache_ll_l1_enable_bus(0, bus_mask);
-	bus_mask = cache_ll_l1_get_bus(0, app_irom_vaddr_aligned, app_irom_size);
-	cache_ll_l1_enable_bus(0, bus_mask);
 #if CONFIG_MP_MAX_NUM_CPUS > 1
-	bus_mask = cache_ll_l1_get_bus(1, app_drom_vaddr_aligned, app_drom_size);
+	bus_mask = cache_ll_l1_get_bus(1, app_drom_vaddr_align, map->drom_size);
 	cache_ll_l1_enable_bus(1, bus_mask);
-	bus_mask = cache_ll_l1_get_bus(1, app_irom_vaddr_aligned, app_irom_size);
+	bus_mask = cache_ll_l1_get_bus(1, app_irom_vaddr_align, map->irom_size);
 	cache_ll_l1_enable_bus(1, bus_mask);
 #endif
 
 	/* ----------------------Enable Cache---------------- */
 #if CONFIG_SOC_SERIES_ESP32
 	/* Application will need to do Cache_Flush(1) and Cache_Read_Enable(1) */
-	Cache_Read_Enable(0);
+	Cache_Read_Enable(core);
 #else
 	cache_hal_enable(CACHE_TYPE_ALL);
 #endif /* CONFIG_SOC_SERIES_ESP32 */
@@ -227,25 +239,25 @@ void map_rom_segments(uint32_t app_drom_start, uint32_t app_drom_vaddr, uint32_t
 #if !defined(CONFIG_SOC_SERIES_ESP32) && !defined(CONFIG_SOC_SERIES_ESP32S2)
 	/* Configure the Cache MMU size for instruction and rodata in flash. */
 	uint32_t cache_mmu_irom_size =
-		((app_irom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE) *
+		((map->irom_size + CONFIG_MMU_PAGE_SIZE - 1) / CONFIG_MMU_PAGE_SIZE) *
 		sizeof(uint32_t);
 
 	/* Split the cache usage by the segment sizes */
 	Cache_Set_IDROM_MMU_Size(cache_mmu_irom_size, CACHE_DROM_MMU_MAX_END - cache_mmu_irom_size);
 #endif
-	/* Show map segments continue using same log format as during MCUboot phase */
-	ESP_EARLY_LOGI(TAG, "%s segment: paddr=%08xh, vaddr=%08xh, size=%05Xh (%6d) map", "DROM",
-		       app_drom_start_aligned, app_drom_vaddr_aligned, app_drom_size,
-		       app_drom_size);
-	ESP_EARLY_LOGI(TAG, "%s segment: paddr=%08xh, vaddr=%08xh, size=%05Xh (%6d) map", "IROM",
-		       app_irom_start_aligned, app_irom_vaddr_aligned, app_irom_size,
-		       app_irom_size);
-	esp_rom_uart_tx_wait_idle(0);
 }
+#endif /* !CONFIG_MCUBOOT */
 
 void __start(void)
 {
 #ifdef CONFIG_RISCV_GP
+
+	__asm__ __volatile__("la t0, _vector_table\n"
+			     "csrw mtvec, t0\n");
+
+	/* Disable normal interrupts. */
+	csr_read_clear(mstatus, MSTATUS_MIE);
+
 	/* Configure the global pointer register
 	 * (This should be the first thing startup does, as any other piece of code could be
 	 * relaxed by the linker to access something relative to __global_pointer$)
@@ -254,30 +266,61 @@ void __start(void)
 			     ".option norelax\n"
 			     "la gp, __global_pointer$\n"
 			     ".option pop");
+
+	z_bss_zero();
+
+#else /* xtensa */
+
+	extern uint32_t _init_start;
+
+	/* Move the exception vector table to IRAM. */
+	__asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start));
+
+	z_bss_zero();
+
+	__asm__ __volatile__("" : : "g"(&__bss_start) : "memory");
+
+	/* Disable normal interrupts. */
+	__asm__ __volatile__("wsr %0, PS" : : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE));
+
+	/* Initialize the architecture CPU pointer.  Some of the
+	 * initialization code wants a valid arch_current_thread() before
+	 * arch_kernel_init() is invoked.
+	 */
+	__asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0]));
+
 #endif /* CONFIG_RISCV_GP */
 
-#ifndef CONFIG_BOOTLOADER_MCUBOOT
-	/* Init fundamental components */
+/* Initialize hardware only during 1st boot  */
+#if defined(CONFIG_MCUBOOT) || defined(CONFIG_ESP_SIMPLE_BOOT)
 	if (hardware_init()) {
 		ESP_EARLY_LOGE(TAG, "HW init failed, aborting");
 		abort();
 	}
 #endif
 
-#if !defined(CONFIG_SOC_ESP32_APPCPU) && !defined(CONFIG_SOC_ESP32S3_APPCPU) && \
-	!defined(CONFIG_MCUBOOT)
-	map_rom_segments(_app_drom_start, _app_drom_vaddr, _app_drom_size, _app_irom_start,
-			 _app_irom_vaddr, _app_irom_size);
-#endif
-#ifndef CONFIG_SOC_SERIES_ESP32C2
+#if defined(CONFIG_ESP_SIMPLE_BOOT) || defined(CONFIG_BOOTLOADER_MCUBOOT)
+	map_rom_segments(0, &map);
+
+	/* Show map segments continue using same log format as during MCUboot phase */
+	ESP_EARLY_LOGI(TAG, "%s segment: paddr=%08xh, vaddr=%08xh, size=%05Xh (%6d) map", "IROM",
+		       map.irom_flash_offset, map.irom_map_addr, map.irom_size, map.irom_size);
+	ESP_EARLY_LOGI(TAG, "%s segment: paddr=%08xh, vaddr=%08xh, size=%05Xh (%6d) map", "DROM",
+		       map.drom_flash_offset, map.drom_map_addr, map.drom_size, map.drom_size);
+	esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+
 	/* Disable RNG entropy source as it was already used */
 	soc_random_disable();
-#endif /* CONFIG_SOC_SERIES_ESP32C2 */
-#if defined(CONFIG_SOC_SERIES_ESP32S3) || defined(CONFIG_SOC_SERIES_ESP32C3)
+
 	/* Disable glitch detection as it can be falsely triggered by EMI interference */
-	ESP_EARLY_LOGI(TAG, "Disabling glitch detection");
 	ana_clock_glitch_reset_config(false);
-#endif /* CONFIG_SOC_SERIES_ESP32S2 */
-	ESP_EARLY_LOGI(TAG, "Jumping to the main image...");
-	__esp_platform_start();
+
+	ESP_EARLY_LOGI(TAG, "libc heap size %d kB.", libc_heap_size / 1024);
+
+	__esp_platform_app_start();
+#endif /* CONFIG_ESP_SIMPLE_BOOT || CONFIG_BOOTLOADER_MCUBOOT */
+
+#if defined(CONFIG_MCUBOOT)
+	__esp_platform_mcuboot_start();
+#endif
 }
diff --git a/soc/espressif/esp32/CMakeLists.txt b/soc/espressif/esp32/CMakeLists.txt
index 5ccc92b682a..36484e5875e 100644
--- a/soc/espressif/esp32/CMakeLists.txt
+++ b/soc/espressif/esp32/CMakeLists.txt
@@ -22,84 +22,3 @@ zephyr_library_sources_ifdef(CONFIG_GDBSTUB gdbstub.c)
 
 zephyr_library_sources_ifdef(CONFIG_PM power.c)
 zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
-
-# get flash size to use in esptool as string
-math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000")
-
-# Get UART baudrate from DT
-dt_chosen(dts_shell_uart PROPERTY "zephyr,shell-uart")
-if(${dts_shell_uart})
-  dt_prop(monitor_baud PATH ${dts_shell_uart} PROPERTY "current-speed")
-endif()
-
-board_runner_args(esp32 "--esp-monitor-baud=${monitor_baud}")
-
-message("-- Espressif HAL path: ${ESP_IDF_PATH}")
-
-# Select image processing
-
-if(CONFIG_ESP_SIMPLE_BOOT OR CONFIG_MCUBOOT)
-
-  if(CONFIG_BUILD_OUTPUT_BIN)
-
-    set(ESPTOOL_PY ${ESP_IDF_PATH}/tools/esptool_py/esptool.py)
-    message("-- Use the esptool.py: ${ESPTOOL_PY}")
-
-    set(ELF2IMAGE_ARG "")
-    if(NOT CONFIG_MCUBOOT)
-      set(ELF2IMAGE_ARG "--ram-only-header")
-    endif()
-
-    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-      COMMAND ${PYTHON_EXECUTABLE} ${ESPTOOL_PY}
-      ARGS --chip ${CONFIG_SOC} elf2image ${ELF2IMAGE_ARG}
-      --flash_mode dio --flash_freq 40m
-      --flash_size ${esptoolpy_flashsize}MB
-      -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
-      ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
-
-  endif()
-
-endif()
-
-set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
-
-  # Select the image origin depending on the boot configuration
-if(CONFIG_SOC_ESP32_APPCPU)
-  dt_nodelabel(dts_partition_path NODELABEL "slot0_appcpu_partition")
-elseif(CONFIG_MCUBOOT)
-  dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
-elseif(CONFIG_ESP_SIMPLE_BOOT)
-  dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
-else()
-  dt_nodelabel(dts_partition_path NODELABEL "slot0_partition")
-endif()
-
-dt_reg_addr(image_off PATH ${dts_partition_path})
-board_finalize_runner_args(esp32 "--esp-app-address=${image_off}")
-
-message("-- Image partition ${dts_partition_path}")
-
-# Look for cross references between bootloader sections
-if(CONFIG_MCUBOOT)
-
-    message("check_callgraph using: ${ESP_IDF_PATH}/tools/ci/check_callgraph.py")
-    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-      COMMAND
-        ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/ci/check_callgraph.py
-      ARGS
-        --rtl-dirs ${CMAKE_BINARY_DIR}/zephyr
-        --elf-file ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf
-        find-refs
-        --from-section='.iram0.loader_text'
-        --to-section='.iram0.text'
-        --exit-code)
-endif()
-
-if(CONFIG_MCUBOOT)
-  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
-elseif(CONFIG_SOC_ESP32_APPCPU)
-  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default_appcpu.ld CACHE INTERNAL "")
-else()
-  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "")
-endif()
diff --git a/soc/espressif/esp32/Kconfig b/soc/espressif/esp32/Kconfig
index 17d67408c09..3457b3818cb 100644
--- a/soc/espressif/esp32/Kconfig
+++ b/soc/espressif/esp32/Kconfig
@@ -20,16 +20,13 @@ config ESP32_BT_RESERVE_DRAM
 	default 0xdb5c if BT
 	default 0
 
-config ESP_HEAP_MEM_POOL_REGION_1_SIZE
-	int "Internal DRAM region 1 mempool size"
-	default 0 if MCUBOOT
-	default 1024 if SOC_ESP32_PROCPU
-	default 49152
+config ESP32_REGION_1_NOINIT
+	bool "Use DRAM region 1 to spill noinit section"
+	default n
 	help
 	  ESP32 has two banks of size 192K and 128K which can be used
-	  as DRAM, system heap allocates area from region 0.
-	  This configuration can be used to add memory from region 1
-	  to heap and can be allocated using k_malloc.
+	  as DRAM. Enabling this option would allocate .noinit sections
+	  in the DRAM region 1, instead of default region 0.
 
 config ESP32_DEEP_SLEEP_WAKEUP_DELAY
 	int "Extra delay in deep sleep wake stub (in us)"
diff --git a/soc/espressif/esp32/Kconfig.defconfig b/soc/espressif/esp32/Kconfig.defconfig
index 8c43bcf5717..75d3ac95ea8 100644
--- a/soc/espressif/esp32/Kconfig.defconfig
+++ b/soc/espressif/esp32/Kconfig.defconfig
@@ -12,6 +12,9 @@ config FLASH_BASE_ADDRESS
 config BOOTLOADER_MCUBOOT
 	default y if SOC_ESP32_APPCPU
 
+config MAIN_STACK_SIZE
+	default 2048
+
 if SMP
 
 config SCHED_IPI_SUPPORTED
diff --git a/soc/espressif/esp32/default.ld b/soc/espressif/esp32/default.ld
index 4c18043ca33..e4e95668004 100644
--- a/soc/espressif/esp32/default.ld
+++ b/soc/espressif/esp32/default.ld
@@ -13,23 +13,40 @@
 #include "memory.h"
 
 /* User available SRAM memory segments */
-procpu_iram_end = USER_IRAM_END - APPCPU_SRAM_SIZE;
-procpu_iram_org = SRAM0_IRAM_START + SRAM0_CACHE_SIZE;
-procpu_iram_len = procpu_iram_end - procpu_iram_org;
+procpu_iram0_end = USER_IRAM_END - APPCPU_SRAM_SIZE;
+procpu_iram0_org = SRAM0_IRAM_START + SRAM0_CACHE_SIZE;
+procpu_iram0_len = procpu_iram0_end - procpu_iram0_org;
 
-procpu_dram_end = SRAM2_DRAM_END;
-procpu_dram_org = SRAM2_DRAM_USER_START + CONFIG_ESP32_BT_RESERVE_DRAM;
-procpu_dram_len = SRAM2_DRAM_USER_SIZE - CONFIG_ESP32_BT_RESERVE_DRAM;
+procpu_dram0_end = SRAM2_DRAM_END;
+procpu_dram0_org = SRAM2_DRAM_USER_START + CONFIG_ESP32_BT_RESERVE_DRAM;
+procpu_dram0_len = SRAM2_DRAM_USER_SIZE - CONFIG_ESP32_BT_RESERVE_DRAM;
 
-user_dram_2_seg_org = SRAM1_DRAM_USER_START;
-user_dram_2_seg_len = SRAM1_USER_SIZE;
+procpu_dram1_org = SRAM1_DRAM_USER_START;
+procpu_dram1_len = SRAM1_DRAM_USER_SIZE;
+
+procpu_irom_org = ICACHE0_START;
+procpu_irom_len = ICACHE0_SIZE;
+procpu_drom_org = DCACHE0_START;
+procpu_drom_len = DCACHE0_SIZE;
+
+#ifdef CONFIG_ESP_SPIRAM
+procpu_ext_ram_org = DCACHE1_START;
+procpu_ext_ram_len = DCACHE1_SIZE;
+#endif
 
 /* Aliases */
-#define FLASH_CODE_REGION   irom0_0_seg
-#define RODATA_REGION       drom0_0_seg
-#define IRAM_REGION         iram0_0_seg
-#define DRAM_REGION         dram0_0_seg
-#define RAMABLE_REGION      dram0_0_seg
+#define FLASH_CODE_REGION irom0_0_seg
+#define RODATA_REGION     drom0_0_seg
+#define IRAM_REGION       iram0_0_seg
+#define DRAM_REGION       dram0_0_seg
+#define RAMABLE_REGION    dram0_0_seg
+
+#ifndef CONFIG_ESP32_REGION_1_NOINIT
+#define RAMABLE_REGION_2  dram0_0_seg
+#else
+#define RAMABLE_REGION_2  dram1_0_seg
+#endif
+
 #define ROMABLE_REGION      FLASH
 
 #undef GROUP_DATA_LINK_IN
@@ -54,25 +71,39 @@ MEMORY
 {
 #ifdef CONFIG_BOOTLOADER_MCUBOOT
   mcuboot_hdr (R): org = 0x0,  len = 0x20
-  metadata (R):    org = 0x20, len = 0x20
-  FLASH (R):       org = 0x40, len = FLASH_SIZE - 0x40
+  metadata (R):    org = 0x20, len = 0x60
+  FLASH (R):       org = 0x80, len = FLASH_SIZE - 0x80
 #else
   /* Make safety margin in the FLASH memory size so the
-   * (esp_img_header + (n*esp_seg_headers)) would fit */
+   * (esp_img_header + (n*esp_seg_headers)) would fit
+   */
   FLASH (R):       org = 0x0,  len = FLASH_SIZE - 0x100
 #endif /* CONFIG_BOOTLOADER_MCUBOOT */
 
-  iram0_0_seg(RX): org = procpu_iram_org, len = procpu_iram_len
-  dram0_0_seg(RW): org = procpu_dram_org, len = procpu_dram_len
+  iram0_0_seg(RX): org = procpu_iram0_org, len = procpu_iram0_len
+  dram0_0_seg(RW): org = procpu_dram0_org, len = procpu_dram0_len
+  dram1_0_seg(RW): org = procpu_dram1_org, len = procpu_dram1_len
 
-  irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
-  drom0_0_seg(R):  org = DROM_SEG_ORG, len = DROM_SEG_LEN
+  irom0_0_seg(RX): org = procpu_irom_org, len = procpu_irom_len
+  drom0_0_seg(R):  org = procpu_drom_org, len = procpu_drom_len
 
   rtc_iram_seg(RWX): org = 0x400c0000, len = 0x2000
-  rtc_slow_seg(RW):  org = 0x50000000, len = 0x1000
+  rtc_slow_seg(RW):  org = 0x50000000, len = 0x2000 - CONFIG_RESERVE_RTC_MEM
+  rtc_data_seg(RW):  org = 0x3ff80000, len = 0x2000
+
+  /* We reduced the size of rtc_slow_seg by CONFIG_RESERVE_RTC_MEM value.
+   *  It reserves the amount of RTC slow memory that we use for this memory segment.
+   *  This segment is intended for keeping rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
+   *  The aim of this is to keep data that will not be moved around and have a fixed address.
+   *  org = 0x50000000 + 0x2000 - CONFIG_RESERVE_RTC_MEM
+   */
+#if (CONFIG_RESERVE_RTC_MEM > 0)
+  rtc_slow_reserved_seg(RW): org = 0x50000000 + 0x2000 - CONFIG_RESERVE_RTC_MEM,
+                             len = CONFIG_RESERVE_RTC_MEM
+#endif
 
 #ifdef CONFIG_ESP_SPIRAM
-  ext_ram_seg(RW): org = 0x3f800000, len = CONFIG_ESP_SPIRAM_SIZE
+  ext_ram_seg(RW): org = procpu_ext_ram_org, len = procpu_ext_ram_len
 #endif /* CONFIG_ESP_SPIRAM */
 
 #ifdef CONFIG_GEN_ISR_TABLES
@@ -88,7 +119,9 @@ _rom_store_table = 0;
 PROVIDE(_memmap_vecbase_reset = 0x40000450);
 PROVIDE(_memmap_reset_vector = 0x40000400);
 
+/* Heap size calculations for PROCPU is also valid for AMP scenario */
 _heap_sentry = SRAM2_DRAM_END;
+_libc_heap_size = _heap_sentry - _end;
 
 SECTIONS
 {
@@ -126,6 +159,42 @@ SECTIONS
     LONG(ADDR(.dram0.data))
     LONG(LOADADDR(.dram0.data))
     LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data))
+
+    /* RTC_IRAM metadata:
+     * 8. Destination address (VMA) for RTC_IRAM region
+     * 9. Flash offset (LMA) for start of RTC_IRAM region
+     * 10. Size of RTC_IRAM region
+     */
+    LONG(ADDR(.rtc.text))
+    LONG(LOADADDR(.rtc.text))
+    LONG(SIZEOF(.rtc.text))
+
+    /* RTC_DRAM metadata:
+     * 11. Destination address (VMA) for RTC_DRAM region
+     * 12. Flash offset (LMA) for start of RTC_DRAM region
+     * 13. Size of RTC_DRAM region
+     */
+    LONG(ADDR(.rtc.data))
+    LONG(LOADADDR(.rtc.data))
+    LONG(SIZEOF(.rtc.data))
+
+    /* IROM metadata:
+     * 14. Destination address (VMA) for IROM region
+     * 15. Flash offset (LMA) for start of IROM region
+     * 16. Size of IROM region
+     */
+    LONG(ADDR(.flash.text))
+    LONG(LOADADDR(.flash.text))
+    LONG(SIZEOF(.flash.text))
+
+    /* DROM metadata:
+     * 17. Destination address (VMA) for DROM region
+     * 18. Flash offset (LMA) for start of DROM region
+     * 19. Size of DROM region
+     */
+    LONG(ADDR(.flash.rodata))
+    LONG(LOADADDR(.flash.rodata))
+    LONG(LOADADDR(.flash.rodata_end) - LOADADDR(.flash.rodata))
   } > metadata
 #endif /* CONFIG_BOOTLOADER_MCUBOOT */
 
@@ -137,38 +206,62 @@ SECTIONS
 
   /* --- RTC BEGIN --- */
 
-  /* RTC fast memory holds RTC wake stub code,
-   * including from any source file named rtc_wake_stub*.c
-   */
   .rtc.text :
   {
     . = ALIGN(4);
-    *(.rtc.literal .rtc.text)
-    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)
+    *(.rtc.literal .rtc.literal.*)
+    *(.rtc.text .rtc.text.*)
+    . = ALIGN(4);
   } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)
 
-  /* RTC slow memory holds RTC wake stub
-   * data/rodata, including from any source file
-   * named rtc_wake_stub*.c
-   */
+  /*
+    This section is required to skip rtc.text area because rtc_iram_seg and
+    rtc_data_seg reflect the same address space on different buses.
+  */
+  .rtc.dummy :
+  {
+    . = SIZEOF(.rtc.text);
+  } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION)
+
+  /* This section located in RTC FAST Memory area.
+     It holds data marked with RTC_FAST_ATTR attribute.
+     See the file "esp_attr.h" for more information.
+  */
+  .rtc.force_fast :
+  {
+    . = ALIGN(4);
+    *(.rtc.force_fast .rtc.force_fast.*)
+    . = ALIGN(4);
+  } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION)
+
+  /* RTC data section holds RTC wake stub
+     data/rodata, including from any source file
+     named rtc_wake_stub*.c and the data marked with
+     RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
+  */
   .rtc.data :
   {
+    . = ALIGN(4);
     _rtc_data_start = ABSOLUTE(.);
-    *(.rtc.data)
-    *(.rtc.rodata)
-    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)
-    _rtc_data_end = ABSOLUTE(.);
+    *(.rtc.data .rtc.data.*)
+    *(.rtc.rodata .rtc.rodata.*)
+    . = ALIGN(4);
   } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)
 
-  /* RTC bss, from any source file named rtc_wake_stub*.c */
   .rtc.bss (NOLOAD) :
   {
     _rtc_bss_start = ABSOLUTE(.);
-    *rtc_wake_stub*.o(.bss .bss.*)
-    *rtc_wake_stub*.o(COMMON)
+    *(.rtc.bss .rtc.bss.*)
     _rtc_bss_end = ABSOLUTE(.);
   } GROUP_LINK_IN(rtc_slow_seg)
 
+  .rtc_noinit (NOLOAD) :
+  {
+    . = ALIGN(4);
+    *(.rtc_noinit .rtc_noinit.*)
+    . = ALIGN(4) ;
+ } GROUP_LINK_IN(rtc_slow_seg)
+
   /* This section located in RTC SLOW Memory area.
    * It holds data marked with RTC_SLOW_ATTR attribute.
    * See the file "esp_attr.h" for more information.
@@ -176,15 +269,27 @@ SECTIONS
   .rtc.force_slow :
   {
     . = ALIGN(4);
-    _rtc_force_slow_start = ABSOLUTE(.);
     *(.rtc.force_slow .rtc.force_slow.*)
     . = ALIGN(4) ;
     _rtc_force_slow_end = ABSOLUTE(.);
-  } > rtc_slow_seg
+  } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)
 
-  /* Get size of rtc slow data */
   _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start);
 
+  /**
+   * This section holds RTC SLOW data that should have fixed addresses.
+   * The data are not initialized at power-up and are retained during deep sleep.
+   */
+#if (CONFIG_RESERVE_RTC_MEM > 0)
+  .rtc_slow_reserved (NOLOAD) :
+  {
+    . = ALIGN(4);
+    _rtc_slow_reserved_start = ABSOLUTE(.);
+    *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
+    _rtc_slow_reserved_end = ABSOLUTE(.);
+  } GROUP_LINK_IN(rtc_slow_reserved_seg)
+#endif
+
   /* --- RTC END --- */
 
   /* --- IRAM BEGIN --- */
@@ -269,6 +374,7 @@ SECTIONS
     *libzephyr.a:esp_psram_impl_quad.*(.literal .literal.* .text .text.*)
 
     /* [mapping:hal] */
+    *libzephyr.a:efuse_hal.*(.literal .literal.* .text .text.*)
     *libzephyr.a:mmu_hal.*(.literal .literal.* .text .text.*)
     *libzephyr.a:cache_utils.*(.literal .text .literal.* .text.*)
     *libzephyr.a:cache_esp32.*(.literal .text .literal.* .text.*)
@@ -304,6 +410,7 @@ SECTIONS
     *libzephyr.a:spi_flash_wrap.*(.literal .literal.* .text .text.*)
     *libzephyr.a:spi_flash_hpm_enable.*(.literal .literal.* .text .text.*)
     *libzephyr.a:flash_ops.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:flash_qio_mode.*(.literal .literal.* .text .text.*)
 
     /* [mapping:esp_system] */
     *libzephyr.a:esp_err.*(.literal .literal.* .text .text.*)
@@ -329,6 +436,7 @@ SECTIONS
     *libzephyr.a:mspi_timing_config.*(.literal .literal.* .text .text.*)
     *libzephyr.a:mspi_timing_tuning.*(.literal .literal.* .text .text.*)
     *libzephyr.a:periph_ctrl.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
     *(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable)
 
     *libzephyr.a:esp_system_chip.*(.literal.esp_system_abort .text.esp_system_abort)
@@ -357,6 +465,7 @@ SECTIONS
 #if defined(CONFIG_ESP32_WIFI_IRAM_OPT)
     *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiextrairam .wifiextrairam.*)
     *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.* .wifiextrairam .wifiextrairam.*)
+    *libcoexist.a:(.wifi_slp_iram  .wifi_slp_iram.* .coexiram .coexiram.* .coexsleepiram .coexsleepiram.*)
 
     /* [mapping:esp_wifi] */
     *(.literal.wifi_clock_enable_wrapper .text.wifi_clock_enable_wrapper)
@@ -404,7 +513,6 @@ SECTIONS
     *libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
     *libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
 
-    *libzephyr.a:efuse_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*)
     *libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*)
     *libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*)
@@ -506,6 +614,7 @@ SECTIONS
     *libzephyr.a:esp_psram_impl_quad.*(.rodata .rodata.*)
 
     /* [mapping:hal] */
+    *libzephyr.a:efuse_hal.*(.rodata .rodata.*)
     *libzephyr.a:mmu_hal.*(.rodata .rodata.*)
     *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.*)
     *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.*)
@@ -543,6 +652,7 @@ SECTIONS
     *libzephyr.a:spi_flash_wrap.*(.rodata .rodata.*)
     *libzephyr.a:spi_flash_hpm_enable.*(.rodata .rodata.*)
     *libzephyr.a:flash_ops.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
+    *libzephyr.a:flash_qio_mode.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
 
     /* [mapping:esp_mm] */
     *libzephyr.a:esp_cache.*(.rodata .rodata.*)
@@ -613,7 +723,6 @@ SECTIONS
     *libzephyr.a:esp_clk.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
     *libzephyr.a:rtc_clk_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
     *libzephyr.a:rtc_time.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
-    *libzephyr.a:efuse_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
     *libzephyr.a:cpu_region_protect.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
 
     *libzephyr.a:periph_ctrl.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
@@ -701,7 +810,7 @@ SECTIONS
 #endif /* CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM */
     __dram_noinit_end = ABSOLUTE(.);
     . = ALIGN (4);
-  } GROUP_LINK_IN(RAMABLE_REGION)
+  } GROUP_LINK_IN(RAMABLE_REGION_2)
 
   /* Provide total SRAM usage, including IRAM and DRAM */
   _image_ram_start = _dram_data_start;
@@ -714,8 +823,9 @@ SECTIONS
 
   /* --- SPIRAM BEGIN --- */
 
+  /* The SPIRAM section needs to be spilled before the dram0.noinit */
 #ifdef CONFIG_ESP_SPIRAM
-  .ext_ram.bss (NOLOAD):
+  .ext_ram (NOLOAD):
   {
     _ext_ram_start = ABSOLUTE(.);
     _ext_ram_noinit_start = ABSOLUTE(.);
@@ -726,7 +836,9 @@ SECTIONS
     *libsubsys__net__lib__config.a:(.noinit .noinit.*)
     *libsubsys__net__ip.a:(.noinit .noinit.*)
     *libsubsys__net.a:(.noinit .noinit.*)
-#endif /* CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM */
+#endif
+    . = ALIGN(16);
+    *(.ext_ram_noinit*)
     . = ALIGN(16);
     _ext_ram_noinit_end = ABSOLUTE(.);
 
@@ -735,9 +847,10 @@ SECTIONS
     . = ALIGN(16);
     _ext_ram_bss_end = ABSOLUTE(.);
 
-    _spiram_heap_start = ABSOLUTE(.);
+    _ext_ram_heap_start = ABSOLUTE(.);
     . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE;
-    . = ALIGN(4);
+    . = ALIGN(16);
+    _ext_ram_heap_end = ABSOLUTE(.);
 
     _ext_ram_end = ABSOLUTE(.);
   } GROUP_LINK_IN(ext_ram_seg)
@@ -855,6 +968,7 @@ SECTIONS
 #ifndef CONFIG_ESP32_WIFI_IRAM_OPT
     *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiextrairam .wifiextrairam.*)
     *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.* .wifiextrairam .wifiextrairam.*)
+    *libcoexist.a:(.wifi_slp_iram  .wifi_slp_iram.* .coexiram .coexiram.* .coexsleepiram .coexsleepiram.*)
 #endif
 
 #ifndef CONFIG_ESP32_WIFI_RX_IRAM_OPT
diff --git a/soc/espressif/esp32/default_appcpu.ld b/soc/espressif/esp32/default_appcpu.ld
index 4761120afa6..71c640df534 100644
--- a/soc/espressif/esp32/default_appcpu.ld
+++ b/soc/espressif/esp32/default_appcpu.ld
@@ -72,7 +72,9 @@ _rom_store_table = 0;
 PROVIDE(_memmap_vecbase_reset = 0x40000450);
 PROVIDE(_memmap_reset_vector = 0x40000400);
 
+/* Heap size calculations for APPCPU */
 _heap_sentry = BOOTLOADER_DRAM_SEG_START + APPCPU_DRAM_SIZE;
+_libc_heap_size = _heap_sentry - _end;
 
 SECTIONS
 {
diff --git a/soc/espressif/esp32/esp32-mp.c b/soc/espressif/esp32/esp32-mp.c
index 8733e33340c..55bc5fd028e 100644
--- a/soc/espressif/esp32/esp32-mp.c
+++ b/soc/espressif/esp32/esp32-mp.c
@@ -453,4 +453,10 @@ int esp_appcpu_init(void)
 
 	return 0;
 }
+
+#if !defined(CONFIG_MCUBOOT)
+extern int esp_appcpu_init(void);
+SYS_INIT(esp_appcpu_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+#endif
+
 #endif /* CONFIG_SOC_ENABLE_APPCPU */
diff --git a/soc/espressif/esp32/hw_init.c b/soc/espressif/esp32/hw_init.c
index 8ff2a3f684b..0282f170642 100644
--- a/soc/espressif/esp32/hw_init.c
+++ b/soc/espressif/esp32/hw_init.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -51,18 +51,14 @@ int hardware_init(void)
 
 	bootloader_clock_configure();
 
+#ifdef CONFIG_ESP_CONSOLE
 	/* initialize console, from now on, we can log */
 	esp_console_init();
 	print_banner();
-
-	spi_flash_init_chip_state();
-	err = esp_flash_init_default_chip();
-	if (err != 0) {
-		ESP_EARLY_LOGE(TAG, "Failed to init flash chip, error %d", err);
-		return err;
-	}
+#endif /* CONFIG_ESP_CONSOLE */
 
 	reset_mmu();
+
 	flash_update_id();
 
 	err = bootloader_flash_xmc_startup();
@@ -88,6 +84,7 @@ int hardware_init(void)
 
 	check_wdt_reset();
 	config_wdt();
+
 	soc_random_enable();
 
 	return 0;
diff --git a/soc/espressif/esp32/mcuboot.ld b/soc/espressif/esp32/mcuboot.ld
index b880e2c7b34..6b321111a0e 100644
--- a/soc/espressif/esp32/mcuboot.ld
+++ b/soc/espressif/esp32/mcuboot.ld
@@ -44,28 +44,17 @@ SECTIONS
     *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
 
     *libarch__xtensa__core.a:xtensa_asm2_util.*(.literal .text .literal.* .text.*)
-    *liblib__libc__common.a:abort.*(.literal .text .literal.* .text.*)
-    *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)
     *libarch__common.a:dynamic_isr.*(.literal .text .literal.* .text.*)
     *libarch__common.a:sw_isr_common.*(.literal .text .literal.* .text.*)
 
     *libapp.a:flash_map_extended.*(.literal .text .literal.* .text.*)
-    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)
     *libzephyr.a:cbprintf_nano.*(.literal .text .literal.* .text.*)
     *libzephyr.a:cpu.*(.literal .text .literal.* .text.*)
     *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:flash_map.*(.literal .text .literal.* .text.*)
     *libzephyr.a:esp_rom_spiflash.*(.literal .text .literal.* .text.*)
-
-    *libzephyr.a:heap.*(.literal .text .literal.* .text.*)
-
-    *libkernel.a:kheap.*(.literal .text .literal.* .text.*)
-    *libkernel.a:mempool.*(.literal .text .literal.* .text.*)
     *libkernel.a:device.*(.literal .text .literal.* .text.*)
-    *libkernel.a:timeout.*(.literal .text .literal.* .text.*)
-
     *libzephyr.a:esp_loader.*(.literal .text .literal.* .text.*)
-    *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
 
     *(.literal.esp_intr_disable .literal.esp_intr_disable.* .text.esp_intr_disable .text.esp_intr_disable.*)
     *(.literal.default_intr_handler .text.default_intr_handler .iram1.*.default_intr_handler)
diff --git a/soc/espressif/esp32/memory.h b/soc/espressif/esp32/memory.h
index 67da219f2d1..f03dc9d804f 100644
--- a/soc/espressif/esp32/memory.h
+++ b/soc/espressif/esp32/memory.h
@@ -16,7 +16,7 @@
 #define SRAM1_DRAM_END        (SRAM1_DRAM_START + SRAM1_SIZE)
 #define SRAM1_RESERVED_SIZE   0x8000
 #define SRAM1_DRAM_USER_START (SRAM1_DRAM_START + SRAM1_RESERVED_SIZE)
-#define SRAM1_USER_SIZE       (0x40000000 - SRAM1_DRAM_USER_START)
+#define SRAM1_DRAM_USER_SIZE  (0x40000000 - SRAM1_DRAM_USER_START)
 
 /* SRAM2 (200kB) data memory */
 #define SRAM2_DRAM_START      DT_REG_ADDR(DT_NODELABEL(sram2))
@@ -87,16 +87,19 @@
 
 #define APPCPU_SRAM_SIZE (APPCPU_IRAM_SIZE + APPCPU_DRAM_SIZE)
 
+/* Cached memories */
+#define ICACHE0_START DT_REG_ADDR(DT_NODELABEL(icache0))
+#define ICACHE0_SIZE  DT_REG_SIZE(DT_NODELABEL(icache0))
+#define DCACHE0_START DT_REG_ADDR(DT_NODELABEL(dcache0))
+#define DCACHE0_SIZE  DT_REG_SIZE(DT_NODELABEL(dcache0))
+#define DCACHE1_START DT_REG_ADDR(DT_NODELABEL(dcache1))
+#define DCACHE1_SIZE  DT_REG_SIZE(DT_NODELABEL(dcache1))
+
+#define CACHE_ALIGN        CONFIG_MMU_PAGE_SIZE
+
 /* Flash */
 #ifdef CONFIG_FLASH_SIZE
 #define FLASH_SIZE          CONFIG_FLASH_SIZE
 #else
 #define FLASH_SIZE          0x400000
 #endif
-
-/* Cached memories */
-#define CACHE_ALIGN        CONFIG_MMU_PAGE_SIZE
-#define IROM_SEG_ORG       0x400d0000
-#define IROM_SEG_LEN       (FLASH_SIZE - 0x1000)
-#define DROM_SEG_ORG       0x3f400000
-#define DROM_SEG_LEN       (FLASH_SIZE - 0x1000)
diff --git a/soc/espressif/esp32/soc.c b/soc/espressif/esp32/soc.c
index ec1fc8c8bab..69c359a92f9 100644
--- a/soc/espressif/esp32/soc.c
+++ b/soc/espressif/esp32/soc.c
@@ -1,109 +1,34 @@
 /*
  * Copyright (c) 2017 Intel Corporation
+ * Copyright (c) 2025 Espressif Systems (Shanghai) CO LTD.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/* Include esp-idf headers first to avoid redefining BIT() macro */
 #include <soc.h>
-#include <soc/rtc_cntl_reg.h>
-#include <soc/timer_group_reg.h>
-#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
-#include <xtensa/config/core-isa.h>
-#include <xtensa/corebits.h>
-#include <esp_private/spi_flash_os.h>
-#include <esp_private/esp_mmu_map_private.h>
-#include <esp_flash_internal.h>
-#if CONFIG_ESP_SPIRAM
-#include "psram.h"
-#endif
-
-#include <zephyr/kernel_structs.h>
-#include <string.h>
-#include <zephyr/toolchain.h>
-#include <zephyr/types.h>
-#include <zephyr/linker/linker-defs.h>
-#include <kernel_internal.h>
-
+#include <soc_init.h>
+#include <flash_init.h>
+#include <esp_private/cache_utils.h>
 #include <esp_private/system_internal.h>
-#include <esp32/rom/cache.h>
-#include <esp_cpu.h>
-#include <hal/soc_hal.h>
-#include <hal/cpu_hal.h>
-#include <soc/gpio_periph.h>
-#include <esp_err.h>
 #include <esp_timer.h>
-#include <hal/wdt_hal.h>
-#include <esp_app_format.h>
-
-#ifndef CONFIG_SOC_ENABLE_APPCPU
-#include "esp_clk_internal.h"
-#endif /* CONFIG_SOC_ENABLE_APPCPU */
-
+#include <psram.h>
+#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
 #include <zephyr/sys/printk.h>
-#include "esp_log.h"
-
-#define TAG "boot.esp32"
 
 extern void z_prep_c(void);
 extern void esp_reset_reason_init(void);
-extern int esp_appcpu_init(void);
 
-/*
- * This is written in C rather than assembly since, during the port bring up,
- * Zephyr is being booted by the Espressif bootloader.  With it, the C stack
- * is already set up.
- */
-void IRAM_ATTR __esp_platform_start(void)
+void IRAM_ATTR __esp_platform_app_start(void)
 {
-	extern uint32_t _init_start;
-
-	/* Move the exception vector table to IRAM. */
-	__asm__ __volatile__ ("wsr %0, vecbase" : : "r"(&_init_start));
-
-	z_bss_zero();
-
-	__asm__ __volatile__ ("" : : "g"(&__bss_start) : "memory");
-
-	/* Disable normal interrupts. */
-	__asm__ __volatile__ ("wsr %0, PS" : : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE));
-
-	/* Initialize the architecture CPU pointer.  Some of the
-	 * initialization code wants a valid _current before
-	 * z_prep_c() is invoked.
-	 */
-	__asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0]));
-
 	esp_reset_reason_init();
 
-#ifndef CONFIG_MCUBOOT
-	/* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check
-	 * on startup sequence related issues in application. Hence disable that
-	 * as we are about to start Zephyr environment.
-	 */
-	wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
-
-	wdt_hal_write_protect_disable(&rtc_wdt_ctx);
-	wdt_hal_disable(&rtc_wdt_ctx);
-	wdt_hal_write_protect_enable(&rtc_wdt_ctx);
-
 	esp_timer_early_init();
 
-	esp_mspi_pin_init();
-
-	esp_flash_app_init();
-
-	esp_mmu_map_init();
+	esp_flash_config();
 
 #if CONFIG_ESP_SPIRAM
 	esp_init_psram();
-#endif /* CONFIG_ESP_SPIRAM */
 
-#endif /* !CONFIG_MCUBOOT */
-
-	esp_intr_initialize();
-
-#if CONFIG_ESP_SPIRAM
 	/* Init Shared Multi Heap for PSRAM */
 	int err = esp_psram_smh_init();
 
@@ -118,6 +43,14 @@ void IRAM_ATTR __esp_platform_start(void)
 	CODE_UNREACHABLE;
 }
 
+void IRAM_ATTR __esp_platform_mcuboot_start(void)
+{
+	/* Start Zephyr */
+	z_prep_c();
+
+	CODE_UNREACHABLE;
+}
+
 /* Boot-time static default printk handler, possibly to be overridden later. */
 int IRAM_ATTR arch_printk_char_out(int c)
 {
@@ -130,10 +63,5 @@ int IRAM_ATTR arch_printk_char_out(int c)
 
 void sys_arch_reboot(int type)
 {
-	esp_restart_noos();
+	esp_restart();
 }
-
-#if defined(CONFIG_SOC_ENABLE_APPCPU) && !defined(CONFIG_MCUBOOT)
-extern int esp_appcpu_init(void);
-SYS_INIT(esp_appcpu_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
-#endif
diff --git a/soc/espressif/esp32/soc.h b/soc/espressif/esp32/soc.h
index e2ea8cc50b7..6958a25fbd0 100644
--- a/soc/espressif/esp32/soc.h
+++ b/soc/espressif/esp32/soc.h
@@ -20,7 +20,8 @@
 #include <xtensa/core-macros.h>
 #include <esp_private/esp_clk.h>
 
-void __esp_platform_start(void);
+void __esp_platform_mcuboot_start(void);
+void __esp_platform_app_start(void);
 
 static inline void esp32_set_mask32(uint32_t v, uint32_t mem_addr)
 {
diff --git a/soc/espressif/esp32/soc_appcpu.c b/soc/espressif/esp32/soc_appcpu.c
index 82c8ef1ad65..32305009336 100644
--- a/soc/espressif/esp32/soc_appcpu.c
+++ b/soc/espressif/esp32/soc_appcpu.c
@@ -87,8 +87,6 @@ void IRAM_ATTR __appcpu_start(void)
 
 	core_intr_matrix_clear();
 
-	esp_intr_initialize();
-
 	/* Start Zephyr */
 	z_prep_c();
 
@@ -104,5 +102,5 @@ int IRAM_ATTR arch_printk_char_out(int c)
 
 void sys_arch_reboot(int type)
 {
-	esp_restart_noos();
+	esp_restart();
 }
diff --git a/soc/espressif/esp32c2/CMakeLists.txt b/soc/espressif/esp32c2/CMakeLists.txt
index 2d70c8cd7de..0248ccef51e 100644
--- a/soc/espressif/esp32c2/CMakeLists.txt
+++ b/soc/espressif/esp32c2/CMakeLists.txt
@@ -3,7 +3,6 @@
 zephyr_sources(
   vectors.S
   soc_irq.S
-  soc_irq.c
   soc.c
   ../common/loader.c
   )
@@ -11,71 +10,3 @@ zephyr_sources(
 zephyr_include_directories(.)
 
 zephyr_sources_ifndef(CONFIG_BOOTLOADER_MCUBOOT hw_init.c)
-
-# get flash size to use in esptool as string
-math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000")
-
-if(NOT CONFIG_BOOTLOADER_MCUBOOT)
-
-  if(CONFIG_BUILD_OUTPUT_BIN)
-    # make ESP ROM loader compatible image
-    message("ESP-IDF path: ${ESP_IDF_PATH}")
-
-    set(ESPTOOL_PY ${ESP_IDF_PATH}/tools/esptool_py/esptool.py)
-    message("esptool path: ${ESPTOOL_PY}")
-
-    set(ELF2IMAGE_ARG "")
-    if(NOT CONFIG_MCUBOOT)
-      set(ELF2IMAGE_ARG "--ram-only-header")
-    endif()
-
-    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-      COMMAND ${PYTHON_EXECUTABLE} ${ESPTOOL_PY}
-      ARGS --chip esp32c2 elf2image ${ELF2IMAGE_ARG}
-      --flash_mode dio --flash_freq 60m --flash_size ${esptoolpy_flashsize}MB
-      -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
-      ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
-  endif()
-
-endif()
-
-# get code-partition slot0 address
-dt_nodelabel(dts_partition_path NODELABEL "slot0_partition")
-dt_reg_addr(img_0_off PATH ${dts_partition_path})
-
-# get code-partition boot address
-dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
-dt_reg_addr(boot_off PATH ${dts_partition_path})
-
-# get UART baudrate from DT
-dt_chosen(dts_shell_uart PROPERTY "zephyr,shell-uart")
-dt_prop(monitor_baud PATH ${dts_shell_uart} PROPERTY "current-speed")
-
-# C2 uses specific values for flash frequency and UART baudrate
-board_runner_args(esp32 "--esp-flash-freq=60m")
-board_runner_args(esp32 "--esp-monitor-baud=${monitor_baud}")
-
-if(CONFIG_BOOTLOADER_MCUBOOT)
-  board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}")
-else()
-  board_finalize_runner_args(esp32 "--esp-app-address=${boot_off}")
-endif()
-
-if(CONFIG_MCUBOOT)
-    # search from cross references between bootloader sections
-    message("check_callgraph using: ${ESP_IDF_PATH}/tools/ci/check_callgraph.py")
-    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-      COMMAND
-        ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/ci/check_callgraph.py
-      ARGS
-        --rtl-dirs ${CMAKE_BINARY_DIR}/zephyr
-	--elf-file ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf
-        find-refs --from-section=.iram0.iram_loader --to-section=.iram0.text
-        --exit-code)
-endif()
-
-if(CONFIG_MCUBOOT)
-  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
-else()
-  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "")
-endif()
diff --git a/soc/espressif/esp32c2/Kconfig b/soc/espressif/esp32c2/Kconfig
index a0e6c98e31a..1e7f41e8b74 100644
--- a/soc/espressif/esp32c2/Kconfig
+++ b/soc/espressif/esp32c2/Kconfig
@@ -15,6 +15,11 @@ config SOC_SERIES_ESP32C2
 
 if SOC_SERIES_ESP32C2
 
+config SOC_ESP32C2_REV_2_0
+	bool "SOC is revision v2.0 (ECO4)"
+	help
+	  ESP32-C2 revision v2.0 has updated ROM functions.
+
 config MAC_BB_PD
 	bool "Power down MAC and baseband of Wi-Fi and Bluetooth when PHY is disabled"
 	depends on SOC_SERIES_ESP32C2 && TICKLESS_KERNEL
diff --git a/soc/espressif/esp32c2/Kconfig.defconfig b/soc/espressif/esp32c2/Kconfig.defconfig
index 36604de6fe4..59ec24263c5 100644
--- a/soc/espressif/esp32c2/Kconfig.defconfig
+++ b/soc/espressif/esp32c2/Kconfig.defconfig
@@ -1,12 +1,10 @@
-# ESP32C2 SoC configuration
-
-# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_SERIES_ESP32C2
 
 config NUM_IRQS
-	default 43
+	default 32
 
 config FLASH_SIZE
 	default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0)
@@ -14,4 +12,7 @@ config FLASH_SIZE
 config FLASH_BASE_ADDRESS
 	default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0)
 
+config MAIN_STACK_SIZE
+	default 2048
+
 endif # SOC_SERIES_ESP32C2
diff --git a/soc/espressif/esp32c2/default.ld b/soc/espressif/esp32c2/default.ld
index 8febd61ec62..53d7a72bac8 100644
--- a/soc/espressif/esp32c2/default.ld
+++ b/soc/espressif/esp32c2/default.ld
@@ -59,8 +59,8 @@ MEMORY
 {
 #ifdef CONFIG_BOOTLOADER_MCUBOOT
   mcuboot_hdr (R): org = 0x0,  len = 0x20
-  metadata (R):    org = 0x20, len = 0x20
-  FLASH (R):       org = 0x40, len = FLASH_SIZE - 0x40
+  metadata (R):    org = 0x20, len = 0x60
+  FLASH (R):       org = 0x80, len = FLASH_SIZE - 0x80
 #else
   /* Make safety margin in the FLASH memory size so the
    * (esp_img_header + (n*esp_seg_headers)) would fit */
@@ -85,8 +85,9 @@ _rom_store_table = 0;
 
 _iram_dram_offset = IRAM_DRAM_OFFSET;
 
-/* Used as a pointer to the heap end */
+/* Heap size calculations */
 _heap_sentry = DRAM_RESERVED_START;
+_libc_heap_size = _heap_sentry - _end;
 
 SECTIONS
 {
@@ -124,6 +125,42 @@ SECTIONS
     LONG(ADDR(.dram0.data))
     LONG(LOADADDR(.dram0.data))
     LONG(LOADADDR(.dram0.end) - LOADADDR(.dram0.data))
+
+    /* LP_IRAM metadata - There is no RTC/LP memory!
+     * 8. Destination address (VMA) for LP_IRAM region
+     * 9. Flash offset (LMA) for start of LP_IRAM region
+     * 10. Size of LP_IRAM region
+     */
+    LONG(0x0)
+    LONG(0x0)
+    LONG(0x0)
+
+    /* LP_DRAM metadata - There is no RTC/LP memory!
+     * 11. Destination address (VMA) for LP_DRAM region
+     * 12. Flash offset (LMA) for start of LP_DRAM region
+     * 13. Size of LP_DRAM region
+     */
+    LONG(0x0)
+    LONG(0x0)
+    LONG(0x0)
+
+    /* IROM metadata:
+     * 14. Destination address (VMA) for IROM region
+     * 15. Flash offset (LMA) for start of IROM region
+     * 16. Size of IROM region
+     */
+    LONG(ADDR(.flash.text))
+    LONG(LOADADDR(.flash.text))
+    LONG(SIZEOF(.flash.text))
+
+    /* DROM metadata:
+     * 17. Destination address (VMA) for DROM region
+     * 18. Flash offset (LMA) for start of DROM region
+     * 19. Size of DROM region
+     */
+    LONG(ADDR(.flash.rodata))
+    LONG(LOADADDR(.flash.rodata))
+    LONG(LOADADDR(.flash.rodata_end) - LOADADDR(.flash.rodata))
   } > metadata
 #endif /* CONFIG_BOOTLOADER_MCUBOOT */
 
@@ -175,6 +212,7 @@ SECTIONS
     *libzephyr.a:console_init.*(.literal .text .literal.* .text.*)
     *libzephyr.a:soc_init.*(.literal .text .literal.* .text.*)
     *libzephyr.a:hw_init.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:soc_random.*(.literal .text .literal.* .text.*)
     *libarch__riscv__core.a:(.literal .text .literal.* .text.*)
     *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*)
     *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*)
@@ -198,11 +236,13 @@ SECTIONS
     *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)
     *liblib__libc__picolib.a:string.*(.literal .text .literal.* .text.*)
     *libzephyr.a:periph_ctrl.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
     *libgcov.a:(.literal .text .literal.* .text.*)
     *libphy.a:( .phyiram .phyiram.*)
     *libc.a:*(.literal .text .literal.* .text.*)
 
     /* [mapping:hal] */
+    *libzephyr.a:efuse_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*)
     *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .text .literal.* .text.*)
@@ -282,7 +322,7 @@ SECTIONS
 #if defined(CONFIG_ESP32_WIFI_IRAM_OPT)
     *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiextrairam .wifiextrairam.*)
     *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiextrairam .wifiextrairam.*)
-    *libcoexist.a:(.wifi_slp_iram .wifi_slp_iram.*)
+    *libcoexist.a:(.wifi_slp_iram  .wifi_slp_iram.* .coexiram .coexiram.* .coexsleepiram .coexsleepiram.*)
 
     /* [mapping:esp_wifi] */
     *(.literal.wifi_clock_enable_wrapper .text.wifi_clock_enable_wrapper)
@@ -320,7 +360,6 @@ SECTIONS
 
     *libzephyr.a:esp_image_format.*(.literal .text .literal.* .text.*)
     *libzephyr.a:flash_ops.*(.literal .text .literal.* .text.*)
-    *libzephyr.a:flash_ops_esp32c2.*(.literal .text .literal.* .text.*)
     *libzephyr.a:flash_encrypt.*(.literal .text .literal.* .text.*)
     *libzephyr.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
     *libzephyr.a:flash_partitions.*(.literal .text .literal.* .text.*)
@@ -426,9 +465,11 @@ SECTIONS
     *libzephyr.a:console_init.*(.rodata .rodata.*)
     *libzephyr.a:soc_init.*(.rodata .rodata.*)
     *libzephyr.a:hw_init.*(.rodata .rodata.*)
+    *libzephyr.a:soc_random.*(.rodata .rodata.*)
     *libzephyr.a:cache_utils.*(.rodata .rodata.* .srodata .srodata.*)
 
     /* [mapping:hal] */
+    *libzephyr.a:efuse_hal.*(.rodata .rodata.* .srodata .srodata.*)
     *libzephyr.a:mmu_hal.*(.rodata .rodata.* .srodata .srodata.*)
     *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.* .srodata .srodata.*)
     *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.* .srodata .srodata.*)
@@ -615,6 +656,7 @@ SECTIONS
 #if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)
     *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiextrairam .wifiextrairam.*)
     *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiextrairam .wifiextrairam.*)
+    *libcoexist.a:(.wifi_slp_iram  .wifi_slp_iram.* .coexiram .coexiram.* .coexsleepiram .coexsleepiram.*)
 #endif /* CONFIG_ESP32_WIFI_IRAM_OPT */
 
 #if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)
diff --git a/soc/espressif/esp32c2/hw_init.c b/soc/espressif/esp32c2/hw_init.c
index 3a57704040d..7ca871282da 100644
--- a/soc/espressif/esp32c2/hw_init.c
+++ b/soc/espressif/esp32c2/hw_init.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -36,34 +36,18 @@ int hardware_init(void)
 #ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
 	esp_cpu_configure_region_protection();
 #endif
-#if CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V
-	rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
-
-	if (cfg.enable == 1 && cfg.tieh == RTC_VDDSDIO_TIEH_1_8V) {
-		cfg.drefh = 3;
-		cfg.drefm = 3;
-		cfg.drefl = 3;
-		cfg.force = 1;
-		rtc_vddsdio_set_config(cfg);
-		esp_rom_delay_us(10);
-	}
-#endif /* CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V */
 
 	bootloader_clock_configure();
 
+#ifdef CONFIG_ESP_CONSOLE
 	/* initialize console, from now on, we can log */
 	esp_console_init();
 	print_banner();
-
-	spi_flash_init_chip_state();
-	err = esp_flash_init_default_chip();
-	if (err != 0) {
-		ESP_EARLY_LOGE(TAG, "Failed to init flash chip, error %d", err);
-		return err;
-	}
+#endif /* CONFIG_ESP_CONSOLE */
 
 	cache_hal_init();
 	mmu_hal_init();
+
 	flash_update_id();
 
 	err = bootloader_flash_xmc_startup();
@@ -90,5 +74,7 @@ int hardware_init(void)
 	check_wdt_reset();
 	config_wdt();
 
+	soc_random_enable();
+
 	return 0;
 }
diff --git a/soc/espressif/esp32c2/mcuboot.ld b/soc/espressif/esp32c2/mcuboot.ld
index 54aff6076c4..595fce23789 100644
--- a/soc/espressif/esp32c2/mcuboot.ld
+++ b/soc/espressif/esp32c2/mcuboot.ld
@@ -44,22 +44,14 @@ SECTIONS
     _loader_text_start = ABSOLUTE(.);
     *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
 
-    /* TODO: cross-segments calls in the libzephyr.a:device.* */
-
     *libapp.a:flash_map_extended.*(.literal .text .literal.* .text.*)
     *libzephyr.a:cbprintf_nano.*(.literal .text .literal.* .text.*)
     *libzephyr.a:cpu.*(.literal .text .literal.* .text.*)
     *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:flash_map.*(.literal .text .literal.* .text.*)
     *libzephyr.a:esp_rom_spiflash.*(.literal .text .literal.* .text.*)
-
-    *libzephyr.a:heap.*(.literal .text .literal.* .text.*)
-
-    *libkernel.a:kheap.*(.literal .text .literal.* .text.*)
-    *libkernel.a:mempool.*(.literal .text .literal.* .text.*)
-
+    *libkernel.a:device.*(.literal .text .literal.* .text.*)
     *libzephyr.a:esp_loader.*(.literal .text .literal.* .text.*)
-    *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
 
     *(.literal.esp_intr_disable .literal.esp_intr_disable.* .text.esp_intr_disable .text.esp_intr_disable.*)
     *(.literal.default_intr_handler .text.default_intr_handler .iram1.*.default_intr_handler)
diff --git a/soc/espressif/esp32c2/soc.c b/soc/espressif/esp32c2/soc.c
index 9ed4bbcb437..5d0df3e0360 100644
--- a/soc/espressif/esp32c2/soc.c
+++ b/soc/espressif/esp32c2/soc.c
@@ -1,85 +1,37 @@
 /*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/* Include esp-idf headers first to avoid redefining BIT() macro */
-#include <soc/rtc_cntl_reg.h>
-#include <soc/timer_group_reg.h>
-#include <soc/ext_mem_defs.h>
-#include <soc/gpio_reg.h>
-#include <soc/syscon_reg.h>
-#include <soc/system_reg.h>
-#include "hal/wdt_hal.h"
-#include "esp_cpu.h"
-#include "hal/soc_hal.h"
-#include "hal/cpu_hal.h"
-#include "esp_timer.h"
-#include "esp_private/system_internal.h"
-#include "esp_clk_internal.h"
-#include <soc/interrupt_reg.h>
-#include <esp_private/spi_flash_os.h>
-#include "esp_private/esp_mmu_map_private.h"
-#include <esp_flash_internal.h>
-
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-
+#include <soc.h>
+#include <soc_init.h>
+#include <flash_init.h>
+#include <esp_private/cache_utils.h>
+#include <esp_private/system_internal.h>
+#include <esp_timer.h>
+#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
 #include <zephyr/kernel_structs.h>
 #include <kernel_internal.h>
-#include <string.h>
-#include <zephyr/toolchain.h>
-#include <soc.h>
 
 extern void esp_reset_reason_init(void);
 
-/*
- * This is written in C rather than assembly since, during the port bring up,
- * Zephyr is being booted by the Espressif bootloader.  With it, the C stack
- * is already set up.
- */
-void __attribute__((section(".iram1"))) __esp_platform_start(void)
+void IRAM_ATTR __esp_platform_app_start(void)
 {
-	__asm__ __volatile__("la t0, _esp32c2_vector_table\n"
-						"csrw mtvec, t0\n");
-
-	z_bss_zero();
-
-	/* Disable normal interrupts. */
-	csr_read_clear(mstatus, MSTATUS_MIE);
-
 	esp_reset_reason_init();
 
-#ifndef CONFIG_MCUBOOT
-	/* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence
-	 * related issues in application. Hence disable that as we are about to start
-	 * Zephyr environment.
-	 */
-	wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
-
-	wdt_hal_write_protect_disable(&rtc_wdt_ctx);
-	wdt_hal_disable(&rtc_wdt_ctx);
-	wdt_hal_write_protect_enable(&rtc_wdt_ctx);
-
-	/* Enable wireless phy subsystem clock,
-	 * This needs to be done before the kernel starts
-	 */
-	REG_CLR_BIT(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_SDIOSLAVE_EN);
-	SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
-
 	esp_timer_early_init();
 
-	esp_mspi_pin_init();
-
-	esp_flash_app_init();
+	esp_flash_config();
 
-	esp_mmu_map_init();
-
-#endif /* !CONFIG_MCUBOOT */
+	/* Start Zephyr */
+	z_cstart();
 
-	/*Initialize the esp32c2 interrupt controller */
-	esp_intr_initialize();
+	CODE_UNREACHABLE;
+}
 
+void IRAM_ATTR __esp_platform_mcuboot_start(void)
+{
 	/* Start Zephyr */
 	z_cstart();
 
@@ -98,5 +50,5 @@ int IRAM_ATTR arch_printk_char_out(int c)
 
 void sys_arch_reboot(int type)
 {
-	esp_restart_noos();
+	esp_restart();
 }
diff --git a/soc/espressif/esp32c2/soc.h b/soc/espressif/esp32c2/soc.h
index da96d9faf83..66a098444b2 100644
--- a/soc/espressif/esp32c2/soc.h
+++ b/soc/espressif/esp32c2/soc.h
@@ -18,7 +18,8 @@
 
 #ifndef _ASMLANGUAGE
 
-void __esp_platform_start(void);
+void __esp_platform_mcuboot_start(void);
+void __esp_platform_app_start(void);
 
 static inline uint32_t esp_core_id(void)
 {
diff --git a/soc/espressif/esp32c2/soc_irq.S b/soc/espressif/esp32c2/soc_irq.S
index b970b84ffa3..7e41a1f961e 100644
--- a/soc/espressif/esp32c2/soc_irq.S
+++ b/soc/espressif/esp32c2/soc_irq.S
@@ -1,4 +1,4 @@
-/* Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+/* Copyright 2021-2025 Espressif Systems (Shanghai) PTE LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,13 +8,8 @@
 
 /* Exports */
 GTEXT(__soc_handle_irq)
-GTEXT(soc_intr_get_next_source)
 
 SECTION_FUNC(exception.other, __soc_handle_irq)
-	addi sp, sp,-4
-	sw  ra, 0x00(sp)
-	la t1, soc_intr_get_next_source
-	jalr ra, t1, 0
-	lw  ra, 0x00(sp)
-	addi sp, sp, 4
+
+	/* int status clearing is done at ISR */
 	ret
diff --git a/soc/espressif/esp32c2/soc_irq.c b/soc/espressif/esp32c2/soc_irq.c
deleted file mode 100644
index 713dfc936eb..00000000000
--- a/soc/espressif/esp32c2/soc_irq.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <soc/rtc_cntl_reg.h>
-#include <soc/timer_group_reg.h>
-#include <soc/ext_mem_defs.h>
-#include <soc/gpio_reg.h>
-#include <soc/syscon_reg.h>
-#include <soc/system_reg.h>
-#include <riscv/interrupt.h>
-#include <soc/interrupt_reg.h>
-#include <soc/periph_defs.h>
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-
-#include <zephyr/kernel_structs.h>
-#include <string.h>
-#include <zephyr/toolchain.h>
-#include <soc.h>
-#include <zephyr/arch/riscv/arch.h>
-
-#define ESP32C2_INTSTATUS_SLOT1_THRESHOLD	32
-
-void arch_irq_enable(unsigned int irq)
-{
-	esp_intr_enable(irq);
-}
-
-void arch_irq_disable(unsigned int irq)
-{
-	esp_intr_disable(irq);
-}
-
-int arch_irq_is_enabled(unsigned int irq)
-{
-	bool res = false;
-	uint32_t key = irq_lock();
-
-	if (irq < 32) {
-		res = esp_intr_get_enabled_intmask(0) & BIT(irq);
-	} else {
-		res = esp_intr_get_enabled_intmask(1) & BIT(irq - 32);
-	}
-
-	irq_unlock(key);
-
-	return res;
-}
-
-uint32_t soc_intr_get_next_source(void)
-{
-	uint32_t status;
-	uint32_t source;
-
-	status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_REG_0_REG) &
-		esp_intr_get_enabled_intmask(0);
-
-	if (status) {
-		source = __builtin_ffs(status) - 1;
-	} else {
-		status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_REG_1_REG) &
-			esp_intr_get_enabled_intmask(1);
-		source = (__builtin_ffs(status) - 1 + ESP32C2_INTSTATUS_SLOT1_THRESHOLD);
-	}
-
-	return source;
-}
diff --git a/soc/espressif/esp32c2/vectors.S b/soc/espressif/esp32c2/vectors.S
index e8f8f0213be..272ab653a5f 100644
--- a/soc/espressif/esp32c2/vectors.S
+++ b/soc/espressif/esp32c2/vectors.S
@@ -1,4 +1,4 @@
-/* Copyright 2024 Espressif Systems (Shanghai) PTE LTD
+/* Copyright 2020-2025 Espressif Systems (Shanghai) PTE LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,12 +22,12 @@ GTEXT(_isr_wrapper)
 	 * only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
 	 */
 
-	.global  _esp32c2_vector_table
+	.global  _vector_table
 	.section .exception_vectors.text
 	.balign   0x100
-	.type     _esp32c2_vector_table, @function
+	.type     _vector_table, @function
 
-_esp32c2_vector_table:
+_vector_table:
 	.option push
 	.option norvc
 	.rept (32)
diff --git a/soc/espressif/esp32c3/CMakeLists.txt b/soc/espressif/esp32c3/CMakeLists.txt
index bfec91fbc4c..980863025ef 100644
--- a/soc/espressif/esp32c3/CMakeLists.txt
+++ b/soc/espressif/esp32c3/CMakeLists.txt
@@ -3,7 +3,6 @@
 zephyr_sources(
   vectors.S
   soc_irq.S
-  soc_irq.c
   soc.c
   ../common/loader.c
   )
@@ -14,63 +13,3 @@ zephyr_sources_ifndef(CONFIG_BOOTLOADER_MCUBOOT hw_init.c)
 
 zephyr_library_sources_ifdef(CONFIG_PM power.c)
 zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
-
-# get flash size to use in esptool as string
-math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000")
-
-if(NOT CONFIG_BOOTLOADER_MCUBOOT)
-
-  if(CONFIG_BUILD_OUTPUT_BIN)
-    # make ESP ROM loader compatible image
-    message("ESP-IDF path: ${ESP_IDF_PATH}")
-
-    set(ESPTOOL_PY ${ESP_IDF_PATH}/tools/esptool_py/esptool.py)
-    message("esptool path: ${ESPTOOL_PY}")
-
-    set(ELF2IMAGE_ARG "")
-    if(NOT CONFIG_MCUBOOT)
-      set(ELF2IMAGE_ARG "--ram-only-header")
-    endif()
-
-    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-      COMMAND ${PYTHON_EXECUTABLE} ${ESPTOOL_PY}
-      ARGS --chip esp32c3 elf2image ${ELF2IMAGE_ARG}
-      --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB
-      -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
-      ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
-  endif()
-
-endif()
-
-# get code-partition slot0 address
-dt_nodelabel(dts_partition_path NODELABEL "slot0_partition")
-dt_reg_addr(img_0_off PATH ${dts_partition_path})
-
-# get code-partition boot address
-dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
-dt_reg_addr(boot_off PATH ${dts_partition_path})
-
-if(CONFIG_BOOTLOADER_MCUBOOT)
-  board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}")
-else()
-  board_finalize_runner_args(esp32 "--esp-app-address=${boot_off}")
-endif()
-
-if(CONFIG_MCUBOOT)
-    # search from cross references between bootloader sections
-    message("check_callgraph using: ${ESP_IDF_PATH}/tools/ci/check_callgraph.py")
-    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-      COMMAND
-        ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/ci/check_callgraph.py
-      ARGS
-        --rtl-dirs ${CMAKE_BINARY_DIR}/zephyr
-	--elf-file ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf
-        find-refs --from-section=.iram0.iram_loader --to-section=.iram0.text
-        --exit-code)
-endif()
-
-if(CONFIG_MCUBOOT)
-  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
-else()
-  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "")
-endif()
diff --git a/soc/espressif/esp32c3/Kconfig.defconfig b/soc/espressif/esp32c3/Kconfig.defconfig
index 43d1d471ab6..dfa777ae547 100644
--- a/soc/espressif/esp32c3/Kconfig.defconfig
+++ b/soc/espressif/esp32c3/Kconfig.defconfig
@@ -1,10 +1,10 @@
-# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+# Copyright (c) 2023-2025 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_SERIES_ESP32C3
 
 config NUM_IRQS
-	default 62
+	default 32
 
 config FLASH_SIZE
 	default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0)
@@ -12,4 +12,7 @@ config FLASH_SIZE
 config FLASH_BASE_ADDRESS
 	default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0)
 
+config MAIN_STACK_SIZE
+	default 2048
+
 endif # SOC_SERIES_ESP32C3
diff --git a/soc/espressif/esp32c3/default.ld b/soc/espressif/esp32c3/default.ld
index 5edb5047f2b..2e0e723a223 100644
--- a/soc/espressif/esp32c3/default.ld
+++ b/soc/espressif/esp32c3/default.ld
@@ -59,8 +59,8 @@ MEMORY
 {
 #ifdef CONFIG_BOOTLOADER_MCUBOOT
   mcuboot_hdr (R): org = 0x0,  len = 0x20
-  metadata (R):    org = 0x20, len = 0x20
-  FLASH (R):       org = 0x40, len = FLASH_SIZE - 0x40
+  metadata (R):    org = 0x20, len = 0x60
+  FLASH (R):       org = 0x80, len = FLASH_SIZE - 0x80
 #else
   /* Make safety margin in the FLASH memory size so the
    * (esp_img_header + (n*esp_seg_headers)) would fit */
@@ -73,19 +73,24 @@ MEMORY
   irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
   drom0_0_seg (R): org = DROM_SEG_ORG, len = DROM_SEG_LEN
 
-  rtc_iram_seg(RWX): org = 0x50000000, len = 0x2000
+  rtc_iram_seg(RWX): org = 0x50000000, len = 0x2000 - CONFIG_RESERVE_RTC_MEM
+
+  /* We reduced the size of rtc_iram_seg by CONFIG_RESERVE_RTC_MEM value.
+     It reserves the amount of RTC fast memory that we use for this memory segment.
+     This segment is intended for keeping:
+       - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
+     The aim of this is to keep data that will not be moved around and have a fixed address.
+  */
+#if (CONFIG_RESERVE_RTC_MEM > 0)
+  rtc_reserved_seg(RW): org = 0x50000000 + 0x2000 - CONFIG_RESERVE_RTC_MEM,
+                        len = CONFIG_RESERVE_RTC_MEM
+#endif
 
 #ifdef CONFIG_GEN_ISR_TABLES
   IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
 #endif
 }
 
-/* The line below defines location alias for .rtc.data section
- * As C3 only has RTC fast memory, this is not configurable like
- * on other targets.
- */
-REGION_ALIAS("rtc_slow_seg", rtc_iram_seg);
-
 /*  Default entry point:  */
 ENTRY(CONFIG_KERNEL_ENTRY)
 
@@ -93,8 +98,9 @@ _rom_store_table = 0;
 
 _iram_dram_offset = IRAM_DRAM_OFFSET;
 
-/* Stack sentry */
+/* Heap size calculations */
 _heap_sentry = DRAM_RESERVED_START;
+_libc_heap_size = _heap_sentry - _end;
 
 SECTIONS
 {
@@ -132,17 +138,45 @@ SECTIONS
     LONG(ADDR(.dram0.data))
     LONG(LOADADDR(.dram0.data))
     LONG(LOADADDR(.dram0.end) - LOADADDR(.dram0.data))
+
+    /* RTC_IRAM metadata:
+     * 8. Destination address (VMA) for RTC_IRAM region
+     * 9. Flash offset (LMA) for start of RTC_IRAM region
+     * 10. Size of RTC_IRAM region
+     */
+    LONG(ADDR(.rtc.text))
+    LONG(LOADADDR(.rtc.text))
+    LONG(SIZEOF(.rtc.text))
+
+    /* RTC_DRAM metadata:
+     * 11. Destination address (VMA) for RTC_DRAM region
+     * 12. Flash offset (LMA) for start of RTC_DRAM region
+     * 13. Size of RTC_DRAM region
+     */
+    LONG(ADDR(.rtc.data))
+    LONG(LOADADDR(.rtc.data))
+    LONG(SIZEOF(.rtc.data))
+
+    /* IROM metadata:
+     * 14. Destination address (VMA) for IROM region
+     * 15. Flash offset (LMA) for start of IROM region
+     * 16. Size of IROM region
+     */
+    LONG(ADDR(.flash.text))
+    LONG(LOADADDR(.flash.text))
+    LONG(SIZEOF(.flash.text))
+
+    /* DROM metadata:
+     * 17. Destination address (VMA) for DROM region
+     * 18. Flash offset (LMA) for start of DROM region
+     * 19. Size of DROM region
+     */
+    LONG(ADDR(.flash.rodata))
+    LONG(LOADADDR(.flash.rodata))
+    LONG(LOADADDR(.flash.rodata_end) - LOADADDR(.flash.rodata))
   } > metadata
 #endif /* CONFIG_BOOTLOADER_MCUBOOT */
 
-  iram_vma = ADDR(.iram0.text);
-  iram_lma = LOADADDR(.iram0.text);
-  iram_size_field = LOADADDR(.iram0.data) - LOADADDR(.iram0.text);
-
-  dram_vma = ADDR(.dram0.data);
-  dram_lma = LOADADDR(.dram0.data);
-  dram_size_field = LOADADDR(.dram0.end) - LOADADDR(.dram0.data);
-
   #include <zephyr/linker/rel-sections.ld>
 
 #ifdef CONFIG_LLEXT
@@ -151,38 +185,61 @@ SECTIONS
 
   /* --- START OF RTC --- */
 
+  /* RTC fast memory holds RTC wake stub code */
   .rtc.text :
   {
     . = ALIGN(4);
-    *(.rtc.literal .rtc.text)
-    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)
+    *(.rtc.literal .rtc.literal.*)
+    *(.rtc.text .rtc.text.*)
+    . = ALIGN(4);
   } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)
 
-  /* This section is required to skip rtc.text area because the text and
-   * data segments reflect the same address space on different buses.
+  /**
+   * This section located in RTC FAST Memory area.
+   * It holds data marked with RTC_FAST_ATTR attribute.
+   * See the file "esp_attr.h" for more information.
    */
-  .rtc.dummy (NOLOAD):
+  .rtc.force_fast :
   {
-    . = SIZEOF(.rtc.text);
-  } GROUP_LINK_IN(rtc_iram_seg)
+    . = ALIGN(4);
+    *(.rtc.force_fast .rtc.force_fast.*)
+    . = ALIGN(4);
+  } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)
 
+  /**
+   * RTC data section holds data marked with
+   * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
+   * See the file "esp_attr.h" for more information.
+   */
   .rtc.data :
   {
+    . = ALIGN(4);
     _rtc_data_start = ABSOLUTE(.);
-    *(.rtc.data)
-    *(.rtc.rodata)
-    *rtc_wake_stub*.o(.data .rodata .data.* .rodata.* .bss .bss.*)
-    _rtc_data_end = ABSOLUTE(.);
+    *(.rtc.data .rtc.data.*)
+    *(.rtc.rodata .rtc.rodata.*)
+    . = ALIGN(4);
   } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)
 
   .rtc.bss (NOLOAD) :
   {
     _rtc_bss_start = ABSOLUTE(.);
-    *rtc_wake_stub*.o(.bss .bss.*)
-    *rtc_wake_stub*.o(COMMON)
+    *(.rtc.bss .rtc.bss.*)
     _rtc_bss_end = ABSOLUTE(.);
   } GROUP_LINK_IN(rtc_iram_seg)
 
+  /**
+   * This section holds data that should not be initialized at power up
+   * and will be retained during deep sleep.
+   * User data marked with RTC_NOINIT_ATTR will be placed
+   * into this section. See the file "esp_attr.h" for more information.
+   */
+  .rtc_noinit (NOLOAD) :
+  {
+    . = ALIGN(4);
+    *(.rtc_noinit .rtc_noinit.*)
+    . = ALIGN(4);
+  } GROUP_LINK_IN(rtc_iram_seg)
+
   /* This section located in RTC SLOW Memory area.
    * It holds data marked with RTC_SLOW_ATTR attribute.
    * See the file "esp_attr.h" for more information.
@@ -190,15 +247,28 @@ SECTIONS
   .rtc.force_slow :
   {
     . = ALIGN(4);
-    _rtc_force_slow_start = ABSOLUTE(.);
     *(.rtc.force_slow .rtc.force_slow.*)
-    . = ALIGN(4) ;
+    . = ALIGN(4);
     _rtc_force_slow_end = ABSOLUTE(.);
-  } > rtc_slow_seg
+  } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)
 
   /* Get size of rtc slow data */
   _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start);
 
+ /**
+   * This section holds RTC data that should have fixed addresses.
+   * The data are not initialized at power-up and are retained during deep sleep.
+   */
+#if (CONFIG_RESERVE_RTC_MEM > 0)
+  .rtc_reserved (NOLOAD) :
+  {
+    . = ALIGN(4);
+    _rtc_reserved_start = ABSOLUTE(.);
+    *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
+    _rtc_reserved_end = ABSOLUTE(.);
+  } GROUP_LINK_IN(rtc_reserved_seg)
+#endif
+
   /* --- END OF RTC --- */
 
   /* --- START OF IRAM --- */
@@ -260,11 +330,13 @@ SECTIONS
     *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)
     *liblib__libc__picolib.a:string.*(.literal .text .literal.* .text.*)
     *libzephyr.a:periph_ctrl.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
     *libgcov.a:(.literal .text .literal.* .text.*)
     *libphy.a:( .phyiram .phyiram.*)
     *libc.a:*(.literal .text .literal.* .text.*)
 
     /* [mapping:hal] */
+    *libzephyr.a:efuse_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*)
     *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .text .literal.* .text.*)
@@ -343,7 +415,7 @@ SECTIONS
 #if defined(CONFIG_ESP32_WIFI_IRAM_OPT)
     *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiextrairam .wifiextrairam.*)
     *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiextrairam .wifiextrairam.*)
-    *libcoexist.a:(.wifi_slp_iram .wifi_slp_iram.*)
+    *libcoexist.a:(.wifi_slp_iram  .wifi_slp_iram.* .coexiram .coexiram.* .coexsleepiram .coexsleepiram.*)
 
     /* [mapping:esp_wifi] */
     *(.literal.wifi_clock_enable_wrapper .text.wifi_clock_enable_wrapper)
@@ -490,6 +562,7 @@ SECTIONS
     *libzephyr.a:cache_utils.*(.rodata .rodata.* .srodata .srodata.*)
 
     /* [mapping:hal] */
+    *libzephyr.a:efuse_hal.*(.rodata .rodata.* .srodata .srodata.*)
     *libzephyr.a:mmu_hal.*(.rodata .rodata.* .srodata .srodata.*)
     *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.* .srodata .srodata.*)
     *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.* .srodata .srodata.*)
@@ -681,6 +754,7 @@ SECTIONS
 #if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)
     *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiextrairam .wifiextrairam.*)
     *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiextrairam .wifiextrairam.*)
+    *libcoexist.a:(.wifi_slp_iram  .wifi_slp_iram.* .coexiram .coexiram.* .coexsleepiram .coexsleepiram.*)
 #endif /* CONFIG_ESP32_WIFI_IRAM_OPT */
 
 #if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)
diff --git a/soc/espressif/esp32c3/hw_init.c b/soc/espressif/esp32c3/hw_init.c
index 37aacd3bbbd..f3ecc5f4f6a 100644
--- a/soc/espressif/esp32c3/hw_init.c
+++ b/soc/espressif/esp32c3/hw_init.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -38,34 +38,18 @@ int hardware_init(void)
 #ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
 	esp_cpu_configure_region_protection();
 #endif
-#if CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V
-	rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
-
-	if (cfg.enable == 1 && cfg.tieh == RTC_VDDSDIO_TIEH_1_8V) {
-		cfg.drefh = 3;
-		cfg.drefm = 3;
-		cfg.drefl = 3;
-		cfg.force = 1;
-		rtc_vddsdio_set_config(cfg);
-		esp_rom_delay_us(10);
-	}
-#endif /* CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V */
 
 	bootloader_clock_configure();
 
+#ifdef CONFIG_ESP_CONSOLE
 	/* initialize console, from now on, we can log */
 	esp_console_init();
 	print_banner();
-
-	spi_flash_init_chip_state();
-	err = esp_flash_init_default_chip();
-	if (err != 0) {
-		ESP_EARLY_LOGE(TAG, "Failed to init flash chip, error %d", err);
-		return err;
-	}
+#endif /* CONFIG_ESP_CONSOLE */
 
 	cache_hal_init();
 	mmu_hal_init();
+
 	flash_update_id();
 
 	err = bootloader_flash_xmc_startup();
diff --git a/soc/espressif/esp32c3/mcuboot.ld b/soc/espressif/esp32c3/mcuboot.ld
index cbc727faf0b..b4dee564e91 100644
--- a/soc/espressif/esp32c3/mcuboot.ld
+++ b/soc/espressif/esp32c3/mcuboot.ld
@@ -44,22 +44,14 @@ SECTIONS
     _loader_text_start = ABSOLUTE(.);
     *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
 
-    /* TODO: cross-segments calls in the libzephyr.a:device.* */
-
     *libapp.a:flash_map_extended.*(.literal .text .literal.* .text.*)
     *libzephyr.a:cbprintf_nano.*(.literal .text .literal.* .text.*)
     *libzephyr.a:cpu.*(.literal .text .literal.* .text.*)
     *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:flash_map.*(.literal .text .literal.* .text.*)
     *libzephyr.a:esp_rom_spiflash.*(.literal .text .literal.* .text.*)
-
-    *libzephyr.a:heap.*(.literal .text .literal.* .text.*)
-
-    *libkernel.a:kheap.*(.literal .text .literal.* .text.*)
-    *libkernel.a:mempool.*(.literal .text .literal.* .text.*)
-
+    *libkernel.a:device.*(.literal .text .literal.* .text.*)
     *libzephyr.a:esp_loader.*(.literal .text .literal.* .text.*)
-    *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
 
     *(.literal.esp_intr_disable .literal.esp_intr_disable.* .text.esp_intr_disable .text.esp_intr_disable.*)
     *(.literal.default_intr_handler .text.default_intr_handler .iram1.*.default_intr_handler)
diff --git a/soc/espressif/esp32c3/memory.h b/soc/espressif/esp32c3/memory.h
index 87a832169fc..07eab679ad3 100644
--- a/soc/espressif/esp32c3/memory.h
+++ b/soc/espressif/esp32c3/memory.h
@@ -47,7 +47,7 @@
 #define BOOTLOADER_STACK_OVERHEAD      0x0
 /* These lengths can be adjusted, if necessary: */
 #define BOOTLOADER_DRAM_SEG_LEN        0x9800
-#define BOOTLOADER_IRAM_SEG_LEN        0x9800
+#define BOOTLOADER_IRAM_SEG_LEN        0x9C00
 #define BOOTLOADER_IRAM_LOADER_SEG_LEN 0x1400
 
 /* Start of the lower region is determined by region size and the end of the higher region */
diff --git a/soc/espressif/esp32c3/soc.c b/soc/espressif/esp32c3/soc.c
index aa21357e728..485891e2c6c 100644
--- a/soc/espressif/esp32c3/soc.c
+++ b/soc/espressif/esp32c3/soc.c
@@ -1,85 +1,38 @@
 /*
  * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2025 Espressif Systems (Shanghai) CO LTD.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/* Include esp-idf headers first to avoid redefining BIT() macro */
-#include <soc/rtc_cntl_reg.h>
-#include <soc/timer_group_reg.h>
-#include <soc/ext_mem_defs.h>
-#include <soc/gpio_reg.h>
-#include <soc/syscon_reg.h>
-#include <soc/system_reg.h>
-#include "hal/wdt_hal.h"
-#include "esp_cpu.h"
-#include "hal/soc_hal.h"
-#include "hal/cpu_hal.h"
-#include "esp_timer.h"
-#include "esp_private/system_internal.h"
-#include "esp_clk_internal.h"
-#include <soc/interrupt_reg.h>
-#include <esp_private/spi_flash_os.h>
-#include "esp_private/esp_mmu_map_private.h"
-#include <esp_flash_internal.h>
-
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-
+#include <soc.h>
+#include <soc_init.h>
+#include <flash_init.h>
+#include <esp_private/cache_utils.h>
+#include <esp_private/system_internal.h>
+#include <esp_timer.h>
+#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
 #include <zephyr/kernel_structs.h>
 #include <kernel_internal.h>
-#include <string.h>
-#include <zephyr/toolchain.h>
-#include <soc.h>
 
 extern void esp_reset_reason_init(void);
 
-/*
- * This is written in C rather than assembly since, during the port bring up,
- * Zephyr is being booted by the Espressif bootloader.  With it, the C stack
- * is already set up.
- */
-void __attribute__((section(".iram1"))) __esp_platform_start(void)
+void IRAM_ATTR __esp_platform_app_start(void)
 {
-	__asm__ __volatile__("la t0, _esp32c3_vector_table\n"
-						"csrw mtvec, t0\n");
-
-	z_bss_zero();
-
-	/* Disable normal interrupts. */
-	csr_read_clear(mstatus, MSTATUS_MIE);
-
 	esp_reset_reason_init();
 
-#ifndef CONFIG_MCUBOOT
-	/* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence
-	 * related issues in application. Hence disable that as we are about to start
-	 * Zephyr environment.
-	 */
-	wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
-
-	wdt_hal_write_protect_disable(&rtc_wdt_ctx);
-	wdt_hal_disable(&rtc_wdt_ctx);
-	wdt_hal_write_protect_enable(&rtc_wdt_ctx);
-
-	/* Enable wireless phy subsystem clock,
-	 * This needs to be done before the kernel starts
-	 */
-	REG_CLR_BIT(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_SDIOSLAVE_EN);
-	SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_EN);
-
 	esp_timer_early_init();
 
-	esp_mspi_pin_init();
-
-	esp_flash_app_init();
+	esp_flash_config();
 
-	esp_mmu_map_init();
-
-#endif /* !CONFIG_MCUBOOT */
+	/* Start Zephyr */
+	z_cstart();
 
-	/*Initialize the esp32c3 interrupt controller */
-	esp_intr_initialize();
+	CODE_UNREACHABLE;
+}
 
+void IRAM_ATTR __esp_platform_mcuboot_start(void)
+{
 	/* Start Zephyr */
 	z_cstart();
 
@@ -98,5 +51,5 @@ int IRAM_ATTR arch_printk_char_out(int c)
 
 void sys_arch_reboot(int type)
 {
-	esp_restart_noos();
+	esp_restart();
 }
diff --git a/soc/espressif/esp32c3/soc.h b/soc/espressif/esp32c3/soc.h
index 73e2fbfee1e..192d0aaf6fc 100644
--- a/soc/espressif/esp32c3/soc.h
+++ b/soc/espressif/esp32c3/soc.h
@@ -18,7 +18,8 @@
 
 #ifndef _ASMLANGUAGE
 
-void __esp_platform_start(void);
+void __esp_platform_mcuboot_start(void);
+void __esp_platform_app_start(void);
 
 static inline uint32_t esp_core_id(void)
 {
diff --git a/soc/espressif/esp32c3/soc_irq.S b/soc/espressif/esp32c3/soc_irq.S
index 0a9e917f508..7e41a1f961e 100644
--- a/soc/espressif/esp32c3/soc_irq.S
+++ b/soc/espressif/esp32c3/soc_irq.S
@@ -1,4 +1,4 @@
-/* Copyright 2021 Espressif Systems (Shanghai) PTE LTD
+/* Copyright 2021-2025 Espressif Systems (Shanghai) PTE LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,13 +8,8 @@
 
 /* Exports */
 GTEXT(__soc_handle_irq)
-GTEXT(soc_intr_get_next_source)
 
 SECTION_FUNC(exception.other, __soc_handle_irq)
-	addi sp, sp,-4
-	sw  ra, 0x00(sp)
-	la t1, soc_intr_get_next_source
-	jalr ra, t1, 0
-	lw  ra, 0x00(sp)
-	addi sp, sp, 4
+
+	/* int status clearing is done at ISR */
 	ret
diff --git a/soc/espressif/esp32c3/soc_irq.c b/soc/espressif/esp32c3/soc_irq.c
deleted file mode 100644
index 6511901a0d4..00000000000
--- a/soc/espressif/esp32c3/soc_irq.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <soc/rtc_cntl_reg.h>
-#include <soc/timer_group_reg.h>
-#include <soc/ext_mem_defs.h>
-#include <soc/gpio_reg.h>
-#include <soc/syscon_reg.h>
-#include <soc/system_reg.h>
-#include <riscv/interrupt.h>
-#include <soc/interrupt_reg.h>
-#include <soc/periph_defs.h>
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-
-#include <zephyr/kernel_structs.h>
-#include <string.h>
-#include <zephyr/toolchain.h>
-#include <soc.h>
-#include <zephyr/arch/riscv/arch.h>
-
-#define ESP32C3_INTSTATUS_SLOT1_THRESHOLD	32
-
-void arch_irq_enable(unsigned int irq)
-{
-	esp_intr_enable(irq);
-}
-
-void arch_irq_disable(unsigned int irq)
-{
-	esp_intr_disable(irq);
-}
-
-int arch_irq_is_enabled(unsigned int irq)
-{
-	bool res = false;
-	uint32_t key = irq_lock();
-
-	if (irq < 32) {
-		res = esp_intr_get_enabled_intmask(0) & BIT(irq);
-	} else {
-		res = esp_intr_get_enabled_intmask(1) & BIT(irq - 32);
-	}
-
-	irq_unlock(key);
-
-	return res;
-}
-
-uint32_t soc_intr_get_next_source(void)
-{
-	uint32_t status;
-	uint32_t source;
-
-	status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_0_REG) &
-		esp_intr_get_enabled_intmask(0);
-
-	if (status) {
-		source = __builtin_ffs(status) - 1;
-	} else {
-		status = REG_READ(INTERRUPT_CORE0_INTR_STATUS_1_REG) &
-			esp_intr_get_enabled_intmask(1);
-		source = (__builtin_ffs(status) - 1 + ESP32C3_INTSTATUS_SLOT1_THRESHOLD);
-	}
-
-	return source;
-}
diff --git a/soc/espressif/esp32c3/vectors.S b/soc/espressif/esp32c3/vectors.S
index 570740469eb..272ab653a5f 100644
--- a/soc/espressif/esp32c3/vectors.S
+++ b/soc/espressif/esp32c3/vectors.S
@@ -1,4 +1,4 @@
-/* Copyright 2020 Espressif Systems (Shanghai) PTE LTD
+/* Copyright 2020-2025 Espressif Systems (Shanghai) PTE LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,12 +22,12 @@ GTEXT(_isr_wrapper)
 	 * only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
 	 */
 
-  .global  _esp32c3_vector_table
- 	.section .exception_vectors.text
-  .balign   0x100
-	.type     _esp32c3_vector_table, @function
+	.global  _vector_table
+	.section .exception_vectors.text
+	.balign   0x100
+	.type     _vector_table, @function
 
-_esp32c3_vector_table:
+_vector_table:
 	.option push
 	.option norvc
 	.rept (32)
diff --git a/soc/espressif/esp32c6/CMakeLists.txt b/soc/espressif/esp32c6/CMakeLists.txt
index 6bd5b99e6ff..9101292b406 100644
--- a/soc/espressif/esp32c6/CMakeLists.txt
+++ b/soc/espressif/esp32c6/CMakeLists.txt
@@ -1,76 +1,24 @@
 # SPDX-License-Identifier: Apache-2.0
 
-zephyr_sources(
+zephyr_sources_ifdef(CONFIG_SOC_ESP32C6_HPCORE
   vectors.S
   soc_irq.S
-  soc_irq.c
   soc.c
   ../common/loader.c
   )
 
-zephyr_include_directories(.)
-
-zephyr_sources_ifndef(CONFIG_BOOTLOADER_MCUBOOT hw_init.c)
-
-zephyr_library_sources_ifdef(CONFIG_PM power.c)
-zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
-
-# get flash size to use in esptool as string
-math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000")
-
-if(NOT CONFIG_BOOTLOADER_MCUBOOT)
-
-  if(CONFIG_BUILD_OUTPUT_BIN)
-    # make ESP ROM loader compatible image
-    message("ESP-IDF path: ${ESP_IDF_PATH}")
-
-    set(ESPTOOL_PY ${ESP_IDF_PATH}/tools/esptool_py/esptool.py)
-    message("esptool path: ${ESPTOOL_PY}")
-
-    set(ELF2IMAGE_ARG "")
-    if(NOT CONFIG_MCUBOOT)
-      set(ELF2IMAGE_ARG "--ram-only-header")
-    endif()
-
-    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-      COMMAND ${PYTHON_EXECUTABLE} ${ESPTOOL_PY}
-      ARGS --chip esp32c6 elf2image ${ELF2IMAGE_ARG}
-      --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB
-      -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
-      ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
-  endif()
-
-endif()
-
-# get code-partition slot0 address
-dt_nodelabel(dts_partition_path NODELABEL "slot0_partition")
-dt_reg_addr(img_0_off PATH ${dts_partition_path})
-
-# get code-partition boot address
-dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
-dt_reg_addr(boot_off PATH ${dts_partition_path})
-
-if(CONFIG_BOOTLOADER_MCUBOOT)
-  board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}")
-else()
-  board_finalize_runner_args(esp32 "--esp-app-address=${boot_off}")
-endif()
+zephyr_sources_ifdef(CONFIG_SOC_ESP32C6_LPCORE
+  vector_table_lpcore.S
+  vectors_lpcore.S
+  start_lpcore.S
+  soc_lpcore.c
+  )
 
-if(CONFIG_MCUBOOT)
-    # search from cross references between bootloader sections
-    message("check_callgraph using: ${ESP_IDF_PATH}/tools/ci/check_callgraph.py")
-    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-      COMMAND
-        ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/ci/check_callgraph.py
-      ARGS
-        --rtl-dirs ${CMAKE_BINARY_DIR}/zephyr
-        --elf-file ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf
-        find-refs --from-section=.iram0.iram_loader --to-section=.iram0.text
-        --exit-code)
-endif()
+zephyr_include_directories(.)
 
-if(CONFIG_MCUBOOT)
-  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
-else()
-  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "")
+if(CONFIG_SOC_ESP32C6_HPCORE)
+  zephyr_sources_ifndef(CONFIG_BOOTLOADER_MCUBOOT hw_init.c)
+  zephyr_library_sources_ifdef(CONFIG_PM power.c)
+  zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
+  zephyr_sources_ifdef(CONFIG_ULP_COPROC_ENABLED hpcore_init_ulp.c)
 endif()
diff --git a/soc/espressif/esp32c6/Kconfig b/soc/espressif/esp32c6/Kconfig
index 3908eb4ee1e..706bbc86ac9 100644
--- a/soc/espressif/esp32c6/Kconfig
+++ b/soc/espressif/esp32c6/Kconfig
@@ -4,14 +4,15 @@
 config SOC_SERIES_ESP32C6
 	select RISCV
 	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
-	select DYNAMIC_INTERRUPTS
-	select CLOCK_CONTROL
-	select PINCTRL
+	select DYNAMIC_INTERRUPTS if SOC_ESP32C6_HPCORE
+	select CLOCK_CONTROL if SOC_ESP32C6_HPCORE
+	select PINCTRL if SOC_ESP32C6_HPCORE
 	select RISCV_ISA_RV32I
 	select RISCV_ISA_EXT_A
 	select RISCV_ISA_EXT_M
 	select RISCV_ISA_EXT_C
 	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
 	select HAS_ESPRESSIF_HAL
 	select HAS_PM
 	select HAS_POWEROFF
diff --git a/soc/espressif/esp32c6/Kconfig.defconfig b/soc/espressif/esp32c6/Kconfig.defconfig
index feb27615d9f..ac076779842 100644
--- a/soc/espressif/esp32c6/Kconfig.defconfig
+++ b/soc/espressif/esp32c6/Kconfig.defconfig
@@ -1,12 +1,10 @@
-# ESP32C6 board configuration
-
-# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+# Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd.
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_SERIES_ESP32C6
 
 config NUM_IRQS
-	default 77
+	default 32
 
 config FLASH_SIZE
 	default $(dt_node_reg_size_int,/soc/flash-controller@60002000/flash@0,0)
@@ -14,4 +12,29 @@ config FLASH_SIZE
 config FLASH_BASE_ADDRESS
 	default $(dt_node_reg_addr_hex,/soc/flash-controller@60002000/flash@0)
 
+config MAIN_STACK_SIZE
+	default 2048
+
 endif # SOC_SERIES_ESP32C6
+
+if SOC_ESP32C6_LPCORE
+
+config GEN_ISR_TABLES
+	default n
+
+config SYS_CLOCK_EXISTS
+	default n
+
+config KERNEL_MEM_POOL
+	default n
+
+config COMMON_LIBC_MALLOC_ARENA_SIZE
+	default 0
+
+config MULTITHREADING
+	default n
+
+config NUM_PREEMPT_PRIORITIES
+	default 0
+
+endif
diff --git a/soc/espressif/esp32c6/Kconfig.soc b/soc/espressif/esp32c6/Kconfig.soc
index 0fe5f8faa05..285478169f6 100644
--- a/soc/espressif/esp32c6/Kconfig.soc
+++ b/soc/espressif/esp32c6/Kconfig.soc
@@ -17,6 +17,16 @@ config SOC_ESP32C6
 	bool
 	select SOC_SERIES_ESP32C6
 
+config SOC_ESP32C6_HPCORE
+	bool
+	help
+	  This hidden configuration defines that build is targeted for HP CORE.
+
+config SOC_ESP32C6_LPCORE
+	bool
+	help
+	  This hidden configuration defines that build is targeted for LP CORE.
+
 config SOC_SERIES
 	default "esp32c6" if SOC_SERIES_ESP32C6
 
diff --git a/soc/espressif/esp32c6/default.ld b/soc/espressif/esp32c6/default.ld
index 9716efc2993..348ffed3628 100644
--- a/soc/espressif/esp32c6/default.ld
+++ b/soc/espressif/esp32c6/default.ld
@@ -48,16 +48,13 @@ user_sram_size = (user_sram_end - user_sram_org);
 #undef SECTION_PROLOGUE
 #define SECTION_PROLOGUE SECTION_DATA_PROLOGUE
 
-/* TODO: add RTC support */
-#define RESERVE_RTC_MEM 0
-
 /* Global symbols required for espressif hal build */
 MEMORY
 {
 #ifdef CONFIG_BOOTLOADER_MCUBOOT
   mcuboot_hdr (R): org = 0x0,  len = 0x20
-  metadata (R):    org = 0x20, len = 0x20
-  FLASH (R):       org = 0x40, len = FLASH_SIZE - 0x40
+  metadata (R):    org = 0x20, len = 0x60
+  FLASH (R):       org = 0x80, len = FLASH_SIZE - 0x80
 #else
   /* Make safety margin in the FLASH memory size so the
    * (esp_img_header + (n*esp_seg_headers)) would fit */
@@ -69,11 +66,24 @@ MEMORY
   irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
   drom0_0_seg(R):  org = DROM_SEG_ORG, len = DROM_SEG_LEN
 
+#if CONFIG_ULP_COPROC_ENABLED
+  lp_ram_seg(RW):    org = LPSRAM_IRAM_START + ULP_COPROC_RESERVE_MEM,
+                     len = LPSRAM_SIZE - ULP_COPROC_RESERVE_MEM - CONFIG_RESERVE_RTC_MEM
+#else
   lp_ram_seg(RW):    org = LPSRAM_IRAM_START,
-                     len = 0x2000 - RESERVE_RTC_MEM
-
-  lp_reserved_seg(RW) :  org = LPSRAM_IRAM_START + 0x2000 - RESERVE_RTC_MEM,
-                         len = RESERVE_RTC_MEM
+                     len = 0x4000 - CONFIG_RESERVE_RTC_MEM
+#endif
+  /* We reduced the size of lp_ram_seg by CONFIG_RESERVE_RTC_MEM value.
+     It reserves the amount of LP memory that we use for this memory segment.
+     This segment is intended for keeping:
+       - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
+       - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
+     The aim of this is to keep data that will not be moved around and have a fixed address.
+  */
+#if (CONFIG_RESERVE_RTC_MEM > 0)
+  lp_reserved_seg(RW) :  org = LPSRAM_IRAM_START + 0x4000 - CONFIG_RESERVE_RTC_MEM,
+                         len = CONFIG_RESERVE_RTC_MEM
+#endif
 
 #ifdef CONFIG_GEN_ISR_TABLES
   IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
@@ -90,12 +100,13 @@ REGION_ALIAS("rtc_iram_seg", lp_ram_seg );
 REGION_ALIAS("rtc_data_seg", rtc_iram_seg );
 REGION_ALIAS("rtc_slow_seg", rtc_iram_seg );
 REGION_ALIAS("rtc_data_location", rtc_iram_seg );
-REGION_ALIAS("rtc_reserved_seg", lp_reserved_seg );
 
 /*  Default entry point:  */
 ENTRY(CONFIG_KERNEL_ENTRY)
 
+/* Heap size calculations */
 _heap_sentry = DRAM_RESERVED_START;
+_libc_heap_size = _heap_sentry - _end;
 
 SECTIONS
 {
@@ -133,6 +144,42 @@ SECTIONS
     LONG(ADDR(.dram0.data))
     LONG(LOADADDR(.dram0.data))
     LONG(LOADADDR(.dram0.end) - LOADADDR(.dram0.data))
+
+    /* LP_IRAM metadata:
+     * 8. Destination address (VMA) for LP_IRAM region
+     * 9. Flash offset (LMA) for start of LP_IRAM region
+     * 10. Size of LP_IRAM region
+     */
+    LONG(ADDR(.rtc.text))
+    LONG(LOADADDR(.rtc.text))
+    LONG(SIZEOF(.rtc.text))
+
+    /* LP_DATA metadata:
+     * 11. Destination address (VMA) for LP_DRAM region
+     * 12. Flash offset (LMA) for start of LP_DRAM region
+     * 13. Size of LP_DRAM region
+     */
+    LONG(ADDR(.rtc.data))
+    LONG(LOADADDR(.rtc.data))
+    LONG(SIZEOF(.rtc.data))
+
+    /* IROM metadata:
+     * 14. Destination address (VMA) for IROM region
+     * 15. Flash offset (LMA) for start of IROM region
+     * 16. Size of IROM region
+     */
+    LONG(ADDR(.flash.text))
+    LONG(LOADADDR(.flash.text))
+    LONG(SIZEOF(.flash.text))
+
+    /* DROM metadata:
+     * 17. Destination address (VMA) for DROM region
+     * 18. Flash offset (LMA) for start of DROM region
+     * 19. Size of DROM region
+     */
+    LONG(ADDR(.flash.rodata))
+    LONG(LOADADDR(.flash.rodata))
+    LONG(LOADADDR(.flash.rodata_end) - LOADADDR(.flash.rodata))
   } > metadata
 #endif /* CONFIG_BOOTLOADER_MCUBOOT */
 
@@ -143,19 +190,16 @@ SECTIONS
 #endif
 
   /* --- START OF RTC --- */
-
   .rtc.text :
   {
     . = ALIGN(4);
     _rtc_fast_start = ABSOLUTE(.);
     _rtc_text_start = ABSOLUTE(.);
     *(.rtc.entry.text)
-    *(.rtc.literal .rtc.text)
-    *rtc_wake_stub*.o(.literal .text .literal.* .text.*)
+    *(.rtc.literal .rtc.literal.* .rtc.text .rtc.text.*)
     . = ALIGN(4);
-
     _rtc_text_end = ABSOLUTE(.);
-  } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)
+  } GROUP_DATA_LINK_IN(lp_ram_seg, ROMABLE_REGION)
 
   /* This section located in RTC FAST Memory area.
    * It holds data marked with RTC_FAST_ATTR attribute.
@@ -167,9 +211,9 @@ SECTIONS
     _rtc_force_fast_start = ABSOLUTE(.);
 
     *(.rtc.force_fast .rtc.force_fast.*)
-    . = ALIGN(4) ;
+    . = ALIGN(4);
     _rtc_force_fast_end = ABSOLUTE(.);
-  } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION)
+  } GROUP_DATA_LINK_IN(lp_ram_seg, ROMABLE_REGION)
 
   /* RTC data section holds data marked with
    * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
@@ -177,34 +221,31 @@ SECTIONS
   .rtc.data :
   {
     _rtc_data_start = ABSOLUTE(.);
-    *(.rtc.data)
-    *(.rtc.rodata)
+    *(.rtc.data .rtc.data.*)
+    *(.rtc.rodata .rtc.rodata.*)
     _rtc_data_end = ABSOLUTE(.);
-  } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)
+  } GROUP_DATA_LINK_IN(lp_ram_seg, ROMABLE_REGION)
 
   .rtc.bss (NOLOAD) :
   {
     _rtc_bss_start = ABSOLUTE(.);
-
-    *(.rtc.data)
-    *(.rtc.rodata)
-
+    *(.rtc.bss .rtc.bss.*)
     _rtc_bss_end = ABSOLUTE(.);
-  } GROUP_LINK_IN(rtc_iram_seg)
+  } GROUP_LINK_IN(lp_ram_seg)
 
   /* This section holds data that should not be initialized at power up
    * and will be retained during deep sleep.
    * User data marked with RTC_NOINIT_ATTR will be placed
    * into this section. See the file "esp_attr.h" for more information.
    */
-  .rtc_noinit (NOLOAD):
+  .rtc_noinit (NOLOAD) :
   {
     . = ALIGN(4);
     _rtc_noinit_start = ABSOLUTE(.);
     *(.rtc_noinit .rtc_noinit.*)
     . = ALIGN(4) ;
     _rtc_noinit_end = ABSOLUTE(.);
-  } GROUP_LINK_IN(rtc_slow_seg)
+  } GROUP_LINK_IN(lp_ram_seg)
 
   /* This section located in RTC SLOW Memory area.
    * It holds data marked with RTC_SLOW_ATTR attribute.
@@ -217,24 +258,21 @@ SECTIONS
     *(.rtc.force_slow .rtc.force_slow.*)
     . = ALIGN(4);
     _rtc_force_slow_end = ABSOLUTE(.);
-  } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)
+  } GROUP_DATA_LINK_IN(lp_ram_seg, ROMABLE_REGION)
 
   /**
    * This section holds RTC data that should have fixed addresses.
    * The data are not initialized at power-up and are retained during deep sleep.
    */
-  .rtc_reserved (NOLOAD):
+#if (CONFIG_RESERVE_RTC_MEM > 0)
+  .rtc_reserved (NOLOAD) :
   {
     . = ALIGN(4);
     _rtc_reserved_start = ABSOLUTE(.);
-    /* New data can only be added here to ensure existing data are not moved.
-       Because data have adhered to the end of the segment and code is relied on it.
-       >> put new data here << */
-
     *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
-    KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*))
     _rtc_reserved_end = ABSOLUTE(.);
-  } GROUP_LINK_IN(rtc_reserved_seg)
+  } GROUP_LINK_IN(lp_reserved_seg)
+#endif
 
   /* Get size of rtc slow data based on rtc_data_location alias */
   _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start);
@@ -304,11 +342,13 @@ SECTIONS
     *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)
     *liblib__libc__picolib.a:string.*(.literal .text .literal.* .text.*)
     *libzephyr.a:periph_ctrl.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
     *libgcov.a:(.literal .text .literal.* .text.*)
     *libphy.a:( .phyiram .phyiram.*)
     *libc.a:*(.literal .text .literal.* .text.*)
 
     /* [mapping:hal] */
+    *libzephyr.a:efuse_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*)
     *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .text .literal.* .text.*)
@@ -386,7 +426,6 @@ SECTIONS
     *libzephyr.a:esp_rom_systimer.*(.literal .literal.* .text .text.*)
     *libzephyr.a:esp_rom_wdt.*(.literal .literal.* .text .text.*)
     *libzephyr.a:esp_rom_hp_regi2c_esp32c6.*(.literal .literal.* .text .text.*)
-    *libzephyr.a:efuse_hal.*(.literal .literal.* .text .text.*)
 
     /* [mapping:esp_mm] */
     *libzephyr.a:esp_cache.*(.literal .literal.* .text .text.*)
@@ -395,7 +434,7 @@ SECTIONS
 #if defined(CONFIG_ESP32_WIFI_IRAM_OPT)
     *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiextrairam .wifiextrairam.* .wifi_extra_iram.*)
     *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiextrairam .wifiextrairam.* .wifi_extra_iram.*)
-    *libcoexist.a:(.wifi_slp_iram .wifi_slp_iram.*)
+    *libcoexist.a:(.wifi_slp_iram  .wifi_slp_iram.* .coexiram .coexiram.* .coexsleepiram .coexsleepiram.*)
 
     /* [mapping:esp_wifi] */
     *(.literal.wifi_clock_enable_wrapper .text.wifi_clock_enable_wrapper)
@@ -451,8 +490,6 @@ SECTIONS
     *libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
     *libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
 
-    *libzephyr.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
-
     *libzephyr.a:cpu_region_protect.*(.literal .text .literal.* .text.*)
 
     /* TODO: optimise */
@@ -537,6 +574,7 @@ SECTIONS
     *libzephyr.a:cache_utils.*(.rodata .rodata.* .srodata .srodata.*)
 
     /* [mapping:hal] */
+    *libzephyr.a:efuse_hal.*(.rodata .rodata.* .srodata .srodata.*)
     *libzephyr.a:mmu_hal.*(.rodata .rodata.* .srodata .srodata.*)
     *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.* .srodata .srodata.*)
     *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.* .srodata .srodata.*)
@@ -612,7 +650,6 @@ SECTIONS
     *libzephyr.a:esp_rom_efuse.*(.rodata .rodata.* .srodata .srodata.*)
     *libzephyr.a:esp_rom_systimer.*(.rodata .rodata.* .srodata .srodata.*)
     *libzephyr.a:esp_rom_hp_regi2c_esp32c6.*(.rodata .rodata.* .srodata .srodata.*)
-    *libzephyr.a:efuse_hal.*(.rodata .rodata.* .srodata .srodata.*)
 
     . = ALIGN(4);
     #include <snippets-rwdata.ld>
@@ -743,6 +780,7 @@ SECTIONS
 #if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)
     *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiextrairam .wifiextrairam.* .wifi_extra_iram.*)
     *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiextrairam .wifiextrairam.* .wifi_extra_iram.*)
+    *libcoexist.a:(.wifi_slp_iram  .wifi_slp_iram.* .coexiram .coexiram.* .coexsleepiram .coexsleepiram.*)
 #endif /* CONFIG_ESP32_WIFI_IRAM_OPT */
 
 #if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)
diff --git a/soc/espressif/esp32c6/default_lpcore.ld b/soc/espressif/esp32c6/default_lpcore.ld
new file mode 100644
index 00000000000..2730eaffbb4
--- /dev/null
+++ b/soc/espressif/esp32c6/default_lpcore.ld
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/devicetree.h>
+#include <zephyr/linker/sections.h>
+#include <zephyr/linker/linker-defs.h>
+#include <zephyr/linker/linker-tool.h>
+
+#include "memory.h"
+
+#define ALIGN_DOWN(SIZE, AL)   (SIZE & ~(AL - 1))
+/* Ensure the end where the shared memory starts is aligned to 8 bytes
+   if updating this also update the same in ulp_lp_core_memory_shared.c
+ */
+#define ALIGNED_COPROC_MEM ALIGN_DOWN(ULP_COPROC_RESERVE_MEM, 0x8)
+
+#define RODATA_REGION      ram
+#define RAMABLE_REGION     ram
+#define ROMABLE_REGION     ram
+
+/* User available memory segments  */
+_aligned_coproc_mem = ALIGNED_COPROC_MEM;
+_vector_table_org = LPSRAM_IRAM_START;
+_vector_table_len = 0x80;
+_ram_org = _vector_table_org + _vector_table_len;
+_ram_len = _aligned_coproc_mem - _vector_table_len - ULP_SHARED_MEM;
+_shared_mem_org = _ram_org + _ram_len;
+_shared_mem_len = ULP_SHARED_MEM;
+
+ENTRY(reset_vector)
+
+MEMORY
+{
+    /*first 128byte for exception/interrupt vectors*/
+    vector_table(RX) :   ORIGIN = _vector_table_org , LENGTH = _vector_table_len
+    ram(RWX) :           ORIGIN = _ram_org, LENGTH = _ram_len
+    shared_mem_ram(RW) : ORIGIN = _shared_mem_org, LENGTH = _shared_mem_len
+}
+
+SECTIONS
+{
+    .vector.text :
+    {
+        __mtvec_base = .;
+        KEEP (*(.init.vector .init.vector.*))
+    } > vector_table
+
+    . = ORIGIN(ram);
+
+    .text ALIGN(4):
+    {
+        *(.text.vectors) /* Default reset vector must link to offset 0x80 */
+        __text_region_start = ABSOLUTE(.);
+        *(.text)
+        *(.text*)
+        *(.iram1)
+        *(.iram1.*)
+        __text_region_end = ABSOLUTE(.);
+    } >ram
+
+  #include <zephyr/linker/rel-sections.ld>
+
+    .rodata ALIGN(4):
+    {
+        __rodata_region_start = ABSOLUTE(.);
+        *(.rodata .srodata)
+        *(.rodata* .srodata*)
+        __rodata_region_end = .;
+
+    } > ram
+
+#include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
+
+    .rodata.end ALIGN(4):
+    {
+        _rodata_reserved_end = ABSOLUTE(.);
+    } > ram
+
+    .data ALIGN(4):
+    {
+        _image_ram_start = ABSOLUTE(.);
+        *(.data)
+        *(.data*)
+        *(.sdata)
+        *(.sdata*)
+
+    } > ram
+
+  #include <snippets-data-sections.ld>
+  #include <zephyr/linker/common-ram.ld>
+  #include <snippets-ram-sections.ld>
+
+    .data.end ALIGN(4):
+    {
+        _image_ram_end = ABSOLUTE(.);
+    } > ram
+
+    .data.noinit (NOLOAD):
+    {
+        . = ALIGN(4);
+        *(.noinit)
+        *(.noinit.*)
+        . = ALIGN(4);
+    } > ram
+
+    .bss ALIGN(4) :
+    {
+        __bss_start = .;
+        *(.bss)
+        *(.bss*)
+        *(.sbss)
+        *(.sbss*)
+        PROVIDE(end = .);
+        __bss_end = .;
+        _heap_sentry = .;
+    } >ram
+
+#include <zephyr/linker/ram-end.ld>
+
+    __stack_top = ORIGIN(ram) + LENGTH(ram);
+
+#include <zephyr/linker/debug-sections.ld>
+    SECTION_PROLOGUE(.riscv.attributes, 0,)
+    {
+    KEEP(*(.riscv.attributes))
+    KEEP(*(.gnu.attributes))
+    }
+
+    . = ORIGIN(shared_mem_ram);
+    .shared_mem (ALIGN(4)) :
+    {
+        KEEP(*(.shared_mem))
+    } > shared_mem_ram
+}
diff --git a/soc/espressif/esp32c6/hpcore_init_ulp.c b/soc/espressif/esp32c6/hpcore_init_ulp.c
new file mode 100644
index 00000000000..6ba9ed64317
--- /dev/null
+++ b/soc/espressif/esp32c6/hpcore_init_ulp.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include "bootloader_flash_priv.h"
+#include <zephyr/storage/flash_map.h>
+#include "ulp_lp_core.h"
+#include "lp_core_uart.h"
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+void IRAM_ATTR lp_core_image_init(void)
+{
+	const uint32_t lpcore_img_off = FIXED_PARTITION_OFFSET(slot0_lpcore_partition);
+	const uint32_t lpcore_img_size = 0x4000;
+	int ret = 0;
+
+	LOG_INF("Getting LPU image at %p, size %d", (void *)lpcore_img_off, lpcore_img_size);
+
+	const uint8_t *data = (const uint8_t *)bootloader_mmap(lpcore_img_off, lpcore_img_size);
+
+	ret = ulp_lp_core_load_binary(data, lpcore_img_size);
+	if (ret) {
+		LOG_ERR("Failed to load LP core image: %d", ret);
+	}
+
+	LOG_INF("LP core image loaded");
+
+	/* Set LP core wakeup source as the HP CPU */
+	ulp_lp_core_cfg_t cfg = {
+		.wakeup_source = ULP_LP_CORE_WAKEUP_SOURCE_HP_CPU,
+	};
+
+	ret = ulp_lp_core_run(&cfg);
+	if (ret) {
+		LOG_ERR("Failed to start LP core: %d", ret);
+	}
+}
+
+void soc_late_init_hook(void)
+{
+	lp_core_image_init();
+}
diff --git a/soc/espressif/esp32c6/hw_init.c b/soc/espressif/esp32c6/hw_init.c
index e4fc9b34d9e..3eaf036e68e 100644
--- a/soc/espressif/esp32c6/hw_init.c
+++ b/soc/espressif/esp32c6/hw_init.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -54,31 +54,14 @@ int hardware_init(void)
 #ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
 	esp_cpu_configure_region_protection();
 #endif
-#if CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V
-	rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
-
-	if (cfg.enable == 1 && cfg.tieh == RTC_VDDSDIO_TIEH_1_8V) {
-		cfg.drefh = 3;
-		cfg.drefm = 3;
-		cfg.drefl = 3;
-		cfg.force = 1;
-		rtc_vddsdio_set_config(cfg);
-		esp_rom_delay_us(10);
-	}
-#endif /* CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V */
 
 	bootloader_clock_configure();
 
+#ifdef CONFIG_ESP_CONSOLE
 	/* initialize console, from now on, we can log */
 	esp_console_init();
 	print_banner();
-
-	spi_flash_init_chip_state();
-	err = esp_flash_init_default_chip();
-	if (err != 0) {
-		ESP_EARLY_LOGE(TAG, "Failed to init flash chip, error %d", err);
-		return err;
-	}
+#endif /* CONFIG_ESP_CONSOLE */
 
 	cache_hal_init();
 	mmu_hal_init();
diff --git a/soc/espressif/esp32c6/mcuboot.ld b/soc/espressif/esp32c6/mcuboot.ld
index 8c76315ffe3..da247e2241b 100644
--- a/soc/espressif/esp32c6/mcuboot.ld
+++ b/soc/espressif/esp32c6/mcuboot.ld
@@ -50,14 +50,8 @@ SECTIONS
     *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:flash_map.*(.literal .text .literal.* .text.*)
     *libzephyr.a:esp_rom_spiflash.*(.literal .text .literal.* .text.*)
-
-    *libzephyr.a:heap.*(.literal .text .literal.* .text.*)
-
-    *libkernel.a:kheap.*(.literal .text .literal.* .text.*)
-    *libkernel.a:mempool.*(.literal .text .literal.* .text.*)
-
+    *libkernel.a:device.*(.literal .text .literal.* .text.*)
     *libzephyr.a:esp_loader.*(.literal .text .literal.* .text.*)
-    *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
 
     *(.literal.esp_intr_disable .literal.esp_intr_disable.* .text.esp_intr_disable .text.esp_intr_disable.*)
     *(.literal.default_intr_handler .text.default_intr_handler .iram1.*.default_intr_handler)
diff --git a/soc/espressif/esp32c6/memory.h b/soc/espressif/esp32c6/memory.h
index 455c62aba03..c9f5dd85302 100644
--- a/soc/espressif/esp32c6/memory.h
+++ b/soc/espressif/esp32c6/memory.h
@@ -5,15 +5,18 @@
 #pragma once
 
 /* LP-SRAM (16kB) memory */
-#define LPSRAM_IRAM_START  DT_REG_ADDR(DT_NODELABEL(sramlp))
-#define LPSRAM_SIZE        DT_REG_SIZE(DT_NODELABEL(sramlp))
+#define LPSRAM_IRAM_START      DT_REG_ADDR(DT_NODELABEL(sramlp))
+#define LPSRAM_SIZE            DT_REG_SIZE(DT_NODELABEL(sramlp))
+#define ULP_SHARED_MEM         DT_REG_SIZE(DT_NODELABEL(shmlp))
+#define ULP_COPROC_RESERVE_MEM (0x4000)
+
 /* HP-SRAM (512kB) memory */
-#define HPSRAM_START       DT_REG_ADDR(DT_NODELABEL(sramhp))
-#define HPSRAM_SIZE        DT_REG_SIZE(DT_NODELABEL(sramhp))
-#define HPSRAM_DRAM_START  HPSRAM_START
-#define HPSRAM_IRAM_START  HPSRAM_START
+#define HPSRAM_START          DT_REG_ADDR(DT_NODELABEL(sramhp))
+#define HPSRAM_SIZE           DT_REG_SIZE(DT_NODELABEL(sramhp))
+#define HPSRAM_DRAM_START     HPSRAM_START
+#define HPSRAM_IRAM_START     HPSRAM_START
 /* ICache size is fixed to 32KB on ESP32-C6 */
-#define ICACHE_SIZE        0x8000
+#define ICACHE_SIZE           0x8000
 
 /** Simplified memory map for the bootloader.
  *  Make sure the bootloader can load into main memory without overwriting itself.
@@ -27,13 +30,13 @@
  *  buffers area (0x4087c610).
  */
 
-#define DRAM_BUFFERS_START       0x4086ad08
-#define DRAM_BUFFERS_END         0x4087c610
-#define DRAM_STACK_START         DRAM_BUFFERS_END
-#define DRAM_ROM_BSS_DATA_START  0x4087e610
+#define DRAM_BUFFERS_START      0x4086ad08
+#define DRAM_BUFFERS_END        0x4087c610
+#define DRAM_STACK_START        DRAM_BUFFERS_END
+#define DRAM_ROM_BSS_DATA_START 0x4087e610
 
 /* Set the limit for the application runtime dynamic allocations */
-#define DRAM_RESERVED_START      DRAM_BUFFERS_END
+#define DRAM_RESERVED_START DRAM_BUFFERS_END
 
 /* For safety margin between bootloader data section and startup stacks */
 #define BOOTLOADER_STACK_OVERHEAD      0x0
@@ -49,14 +52,14 @@
 
 /* Start of the lower region is determined by region size and the end of the higher region */
 #define BOOTLOADER_IRAM_LOADER_SEG_START (BOOTLOADER_USER_SRAM_END - BOOTLOADER_IRAM_LOADER_SEG_LEN)
-#define BOOTLOADER_IRAM_SEG_START (BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN)
-#define BOOTLOADER_DRAM_SEG_START (BOOTLOADER_IRAM_SEG_START - BOOTLOADER_DRAM_SEG_LEN)
+#define BOOTLOADER_IRAM_SEG_START       (BOOTLOADER_IRAM_LOADER_SEG_START - BOOTLOADER_IRAM_SEG_LEN)
+#define BOOTLOADER_DRAM_SEG_START        (BOOTLOADER_IRAM_SEG_START - BOOTLOADER_DRAM_SEG_LEN)
 
 /* Flash */
 #ifdef CONFIG_FLASH_SIZE
-#define FLASH_SIZE         CONFIG_FLASH_SIZE
+#define FLASH_SIZE CONFIG_FLASH_SIZE
 #else
-#define FLASH_SIZE         0x400000
+#define FLASH_SIZE 0x400000
 #endif
 
 /* Cached memory */
diff --git a/soc/espressif/esp32c6/soc.c b/soc/espressif/esp32c6/soc.c
index 1c8877d8541..fb02f77c3b4 100644
--- a/soc/espressif/esp32c6/soc.c
+++ b/soc/espressif/esp32c6/soc.c
@@ -1,75 +1,37 @@
 /*
- * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2023-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/* Include esp-idf headers first to avoid redefining BIT() macro */
-#include <soc/timer_group_reg.h>
-#include <soc/ext_mem_defs.h>
-#include <soc/gpio_reg.h>
-#include <soc/system_reg.h>
-#include "hal/wdt_hal.h"
-#include "esp_cpu.h"
-#include "hal/soc_hal.h"
-#include "hal/cpu_hal.h"
-#include "esp_timer.h"
-#include "esp_private/system_internal.h"
-#include "esp_clk_internal.h"
-#include <soc/interrupt_reg.h>
-#include <esp_private/spi_flash_os.h>
-#include "esp_private/esp_mmu_map_private.h"
-#include <esp_flash_internal.h>
-
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-
+#include <soc.h>
+#include <soc_init.h>
+#include <flash_init.h>
+#include <esp_private/cache_utils.h>
+#include <esp_private/system_internal.h>
+#include <esp_timer.h>
+#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
 #include <zephyr/kernel_structs.h>
 #include <kernel_internal.h>
-#include <string.h>
-#include <zephyr/toolchain/gcc.h>
-#include <soc.h>
-
-/*
- * This is written in C rather than assembly since, during the port bring up,
- * Zephyr is being booted by the Espressif bootloader.  With it, the C stack
- * is already set up.
- */
-void IRAM_ATTR __esp_platform_start(void)
-{
-	__asm__ __volatile__("la t0, _esp32c6_vector_table\n"
-						"csrw mtvec, t0\n");
 
-	z_bss_zero();
-
-	/* Disable normal interrupts. */
-	csr_read_clear(mstatus, MSTATUS_MIE);
+extern void esp_reset_reason_init(void);
 
+void IRAM_ATTR __esp_platform_app_start(void)
+{
 	esp_reset_reason_init();
 
-#ifndef CONFIG_MCUBOOT
-	/* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence
-	 * related issues in application. Hence disable that as we are about to start
-	 * Zephyr environment.
-	 */
-	wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &LP_WDT};
-
-	wdt_hal_write_protect_disable(&rtc_wdt_ctx);
-	wdt_hal_disable(&rtc_wdt_ctx);
-	wdt_hal_write_protect_enable(&rtc_wdt_ctx);
-
 	esp_timer_early_init();
 
-	esp_mspi_pin_init();
-
-	esp_flash_app_init();
+	esp_flash_config();
 
-	esp_mmu_map_init();
-
-#endif /* !CONFIG_MCUBOOT */
+	/* Start Zephyr */
+	z_cstart();
 
-	/*Initialize the esp32c6 interrupt controller */
-	esp_intr_initialize();
+	CODE_UNREACHABLE;
+}
 
+void IRAM_ATTR __esp_platform_mcuboot_start(void)
+{
 	/* Start Zephyr */
 	z_cstart();
 
@@ -88,5 +50,5 @@ int IRAM_ATTR arch_printk_char_out(int c)
 
 void sys_arch_reboot(int type)
 {
-	esp_restart_noos();
+	esp_restart();
 }
diff --git a/soc/espressif/esp32c6/soc.h b/soc/espressif/esp32c6/soc.h
index bfa56449777..4cbae497835 100644
--- a/soc/espressif/esp32c6/soc.h
+++ b/soc/espressif/esp32c6/soc.h
@@ -27,7 +27,8 @@
 
 #ifndef _ASMLANGUAGE
 
-void __esp_platform_start(void);
+void __esp_platform_mcuboot_start(void);
+void __esp_platform_app_start(void);
 
 static inline uint32_t esp_core_id(void)
 {
diff --git a/soc/espressif/esp32c6/soc_irq.S b/soc/espressif/esp32c6/soc_irq.S
index c1ad164c153..7e41a1f961e 100644
--- a/soc/espressif/esp32c6/soc_irq.S
+++ b/soc/espressif/esp32c6/soc_irq.S
@@ -1,26 +1,15 @@
-/* Copyright 2021 Espressif Systems (Shanghai) PTE LTD
+/* Copyright 2021-2025 Espressif Systems (Shanghai) PTE LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <offsets.h>
+#include <zephyr/offsets.h>
 #include <zephyr/toolchain.h>
 
 /* Exports */
-GTEXT(__soc_is_irq)
 GTEXT(__soc_handle_irq)
-GTEXT(soc_intr_get_next_source)
-
-SECTION_FUNC(exception.other, __soc_is_irq)
-	csrr a0, mcause
-	srli a0, a0, 31
-	ret
 
 SECTION_FUNC(exception.other, __soc_handle_irq)
-	addi sp, sp,-4
-	sw  ra, 0x00(sp)
-	la t1, soc_intr_get_next_source
-	jalr ra, t1, 0
-	lw  ra, 0x00(sp)
-	addi sp, sp, 4
+
+	/* int status clearing is done at ISR */
 	ret
diff --git a/soc/espressif/esp32c6/soc_irq.c b/soc/espressif/esp32c6/soc_irq.c
deleted file mode 100644
index 6a452ec78b9..00000000000
--- a/soc/espressif/esp32c6/soc_irq.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <soc/timer_group_reg.h>
-#include <soc/ext_mem_defs.h>
-#include <soc/gpio_reg.h>
-#include <soc/system_reg.h>
-#include <riscv/interrupt.h>
-#include <soc/interrupt_reg.h>
-#include <soc/periph_defs.h>
-#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
-
-#include <zephyr/kernel_structs.h>
-#include <string.h>
-#include <zephyr/toolchain/gcc.h>
-#include <soc.h>
-#include <zephyr/arch/riscv/arch.h>
-
-#define ESP32C6_INTSTATUS_REG1_THRESHOLD	32
-#define ESP32C6_INTSTATUS_REG2_THRESHOLD	64
-
-void arch_irq_enable(unsigned int irq)
-{
-	esp_intr_enable(irq);
-}
-
-void arch_irq_disable(unsigned int irq)
-{
-	esp_intr_disable(irq);
-}
-
-int arch_irq_is_enabled(unsigned int irq)
-{
-	bool res = false;
-	uint32_t key = irq_lock();
-
-	if (irq < 32) {
-		res = esp_intr_get_enabled_intmask(0) & BIT(irq);
-	} else if (irq < 64) {
-		res = esp_intr_get_enabled_intmask(1) & BIT(irq - 32);
-	} else {
-		res = esp_intr_get_enabled_intmask(2) & BIT(irq - 64);
-	}
-
-	irq_unlock(key);
-
-	return res;
-}
-
-uint32_t soc_intr_get_next_source(void)
-{
-	uint32_t status;
-	uint32_t source;
-
-	/* Status register for interrupt sources 0 ~ 31 */
-	status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_0_REG) &
-		esp_intr_get_enabled_intmask(0);
-
-	if (status) {
-		source = __builtin_ffs(status) - 1;
-		goto ret;
-	}
-
-	/* Status register for interrupt sources 32 ~ 63 */
-	status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_1_REG) &
-		esp_intr_get_enabled_intmask(1);
-
-	if (status) {
-		source = (__builtin_ffs(status) - 1 + ESP32C6_INTSTATUS_REG1_THRESHOLD);
-		goto ret;
-	}
-
-	/* Status register for interrupt sources 64 ~ 76 */
-	status = REG_READ(INTMTX_CORE0_INT_STATUS_REG_2_REG) &
-		esp_intr_get_enabled_intmask(2);
-
-	source = (__builtin_ffs(status) - 1 + ESP32C6_INTSTATUS_REG2_THRESHOLD);
-
-ret:
-	return source;
-}
diff --git a/soc/espressif/esp32c6/soc_lpcore.c b/soc/espressif/esp32c6/soc_lpcore.c
new file mode 100644
index 00000000000..e2e5a5d2b53
--- /dev/null
+++ b/soc/espressif/esp32c6/soc_lpcore.c
@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/soc_caps.h"
+#include "esp_rom_caps.h"
+#include "rom/ets_sys.h"
+#include "ulp_lp_core_utils.h"
+#include "ulp_lp_core_lp_timer_shared.h"
+#include "ulp_lp_core_memory_shared.h"
+#include "ulp_lp_core_print.h"
+#include <soc.h>
+#include <kernel_internal.h>
+
+extern void main(void);
+
+/* Initialize lp core related system functions before calling user's main*/
+void lp_core_startup(void)
+{
+#if CONFIG_ULP_HP_UART_CONSOLE_PRINT && ESP_ROM_HAS_LP_ROM
+	ets_install_putc1(lp_core_print_char);
+#endif
+
+	ulp_lp_core_update_wakeup_cause();
+
+	/* Start Zephyr */
+	z_cstart();
+
+	CODE_UNREACHABLE;
+}
diff --git a/soc/espressif/esp32c6/start_lpcore.S b/soc/espressif/esp32c6/start_lpcore.S
new file mode 100644
index 00000000000..b30015b09b7
--- /dev/null
+++ b/soc/espressif/esp32c6/start_lpcore.S
@@ -0,0 +1,25 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+	.section .text.vectors
+	.global reset_vector
+
+/* The reset vector, jumps to startup code */
+reset_vector:
+
+	/* _vector_table: Only 256-byte aligned addresses are allowed */
+	la      t0, _vector_table
+	csrw    mtvec, t0
+
+	j __start
+
+__start:
+
+	/* setup the stack pointer */
+	la sp, __stack_top
+	call lp_core_startup
+loop:
+	j loop
diff --git a/soc/espressif/esp32c6/vector_table_lpcore.S b/soc/espressif/esp32c6/vector_table_lpcore.S
new file mode 100644
index 00000000000..3fe3f5a308f
--- /dev/null
+++ b/soc/espressif/esp32c6/vector_table_lpcore.S
@@ -0,0 +1,22 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+	.section	.init.vector,"ax"
+
+	.global _vector_table
+	.type _vector_table, @function
+_vector_table:
+	.option push
+	.option norvc
+
+	.rept 30
+	j _panic_handler
+	.endr
+	j _interrupt_handler // All interrupts are routed to mtvec + 4*30, i.e. the 31st entry
+	j _panic_handler
+
+	.option pop
+	.size _vector_table, .-_vector_table
diff --git a/soc/espressif/esp32c6/vectors.S b/soc/espressif/esp32c6/vectors.S
index d248c0b49b5..272ab653a5f 100644
--- a/soc/espressif/esp32c6/vectors.S
+++ b/soc/espressif/esp32c6/vectors.S
@@ -1,4 +1,4 @@
-/* Copyright 2023 Espressif Systems (Shanghai) PTE LTD
+/* Copyright 2020-2025 Espressif Systems (Shanghai) PTE LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,12 +22,12 @@ GTEXT(_isr_wrapper)
 	 * only uses the 24 MSBs of the MTVEC, i.e. (MTVEC & 0xffffff00).
 	 */
 
-	.global  _esp32c6_vector_table
+	.global  _vector_table
 	.section .exception_vectors.text
 	.balign   0x100
-	.type     _esp32c6_vector_table, @function
+	.type     _vector_table, @function
 
-_esp32c6_vector_table:
+_vector_table:
 	.option push
 	.option norvc
 	.rept (32)
diff --git a/soc/espressif/esp32c6/vectors_lpcore.S b/soc/espressif/esp32c6/vectors_lpcore.S
new file mode 100644
index 00000000000..360977cadd1
--- /dev/null
+++ b/soc/espressif/esp32c6/vectors_lpcore.S
@@ -0,0 +1,142 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "riscv/rvruntime-frames.h"
+#include <soc/soc_caps.h>
+
+	.equ SAVE_REGS, 32
+	.equ CONTEXT_SIZE, (SAVE_REGS * 4)
+/* Macro which first allocates space on the stack to save general
+ * purpose registers, and then save them. GP register is excluded.
+ * The default size allocated on the stack is CONTEXT_SIZE, but it
+ * can be overridden. */
+.macro save_general_regs cxt_size=CONTEXT_SIZE
+	addi sp, sp, -\cxt_size
+	sw   ra, RV_STK_RA(sp)
+	sw   tp, RV_STK_TP(sp)
+	sw   t0, RV_STK_T0(sp)
+	sw   t1, RV_STK_T1(sp)
+	sw   t2, RV_STK_T2(sp)
+	sw   s0, RV_STK_S0(sp)
+	sw   s1, RV_STK_S1(sp)
+	sw   a0, RV_STK_A0(sp)
+	sw   a1, RV_STK_A1(sp)
+	sw   a2, RV_STK_A2(sp)
+	sw   a3, RV_STK_A3(sp)
+	sw   a4, RV_STK_A4(sp)
+	sw   a5, RV_STK_A5(sp)
+	sw   a6, RV_STK_A6(sp)
+	sw   a7, RV_STK_A7(sp)
+	sw   s2, RV_STK_S2(sp)
+	sw   s3, RV_STK_S3(sp)
+	sw   s4, RV_STK_S4(sp)
+	sw   s5, RV_STK_S5(sp)
+	sw   s6, RV_STK_S6(sp)
+	sw   s7, RV_STK_S7(sp)
+	sw   s8, RV_STK_S8(sp)
+	sw   s9, RV_STK_S9(sp)
+	sw   s10, RV_STK_S10(sp)
+	sw   s11, RV_STK_S11(sp)
+	sw   t3, RV_STK_T3(sp)
+	sw   t4, RV_STK_T4(sp)
+	sw   t5, RV_STK_T5(sp)
+	sw   t6, RV_STK_T6(sp)
+.endm
+
+.macro save_mepc
+	csrr t0, mepc
+	sw   t0, RV_STK_MEPC(sp)
+.endm
+
+/* Restore the general purpose registers (excluding gp) from the context on
+ * the stack. The context is then deallocated. The default size is CONTEXT_SIZE
+ * but it can be overridden. */
+.macro restore_general_regs cxt_size=CONTEXT_SIZE
+	lw   ra, RV_STK_RA(sp)
+	lw   tp, RV_STK_TP(sp)
+	lw   t0, RV_STK_T0(sp)
+	lw   t1, RV_STK_T1(sp)
+	lw   t2, RV_STK_T2(sp)
+	lw   s0, RV_STK_S0(sp)
+	lw   s1, RV_STK_S1(sp)
+	lw   a0, RV_STK_A0(sp)
+	lw   a1, RV_STK_A1(sp)
+	lw   a2, RV_STK_A2(sp)
+	lw   a3, RV_STK_A3(sp)
+	lw   a4, RV_STK_A4(sp)
+	lw   a5, RV_STK_A5(sp)
+	lw   a6, RV_STK_A6(sp)
+	lw   a7, RV_STK_A7(sp)
+	lw   s2, RV_STK_S2(sp)
+	lw   s3, RV_STK_S3(sp)
+	lw   s4, RV_STK_S4(sp)
+	lw   s5, RV_STK_S5(sp)
+	lw   s6, RV_STK_S6(sp)
+	lw   s7, RV_STK_S7(sp)
+	lw   s8, RV_STK_S8(sp)
+	lw   s9, RV_STK_S9(sp)
+	lw   s10, RV_STK_S10(sp)
+	lw   s11, RV_STK_S11(sp)
+	lw   t3, RV_STK_T3(sp)
+	lw   t4, RV_STK_T4(sp)
+	lw   t5, RV_STK_T5(sp)
+	lw   t6, RV_STK_T6(sp)
+	addi sp,sp, \cxt_size
+.endm
+
+.macro restore_mepc
+	lw      t0, RV_STK_MEPC(sp)
+	csrw    mepc, t0
+.endm
+
+
+/* _panic_handler: handle all exception */
+	.section	.text.handlers,"ax"
+	.global _panic_handler
+	.type _panic_handler, @function
+_panic_handler:
+	save_general_regs RV_STK_FRMSZ
+	save_mepc
+
+	addi  t0, sp, RV_STK_FRMSZ /* Restore sp with the value when trap happened */
+
+	/* Save CSRs */
+	sw    t0, RV_STK_SP(sp)
+	csrr  t0, mstatus
+	sw    t0, RV_STK_MSTATUS(sp)
+	csrr  t0, mcause
+	sw    t0, RV_STK_MCAUSE(sp)
+	csrr  t0, mtvec
+	sw    t0, RV_STK_MTVEC(sp)
+	csrr  t0, mhartid
+	sw    t0, RV_STK_MHARTID(sp)
+	csrr  t0, mtval
+	sw    t0, RV_STK_MTVAL(sp)
+
+	csrr	a1, mcause		/* Exception cause */
+
+	mv	a0, sp			/* RvExcFrame *regs */
+	call ulp_lp_core_panic_handler
+_end:
+	j _end /* loop forever */
+
+
+/* _interrupt_handler: handle all interrupt */
+	.section	.text.handlers,"ax"
+	.global _interrupt_handler
+	.type _interrupt_handler, @function
+_interrupt_handler:
+	/* Save registers & mepc to stack */
+	save_general_regs
+	save_mepc
+
+	call ulp_lp_core_intr_handler
+
+	/* Restore registers & mepc from stack */
+	restore_mepc
+	restore_general_regs
+	/* Exit, this will also re-enable the interrupts */
+	mret
diff --git a/soc/espressif/esp32s2/CMakeLists.txt b/soc/espressif/esp32s2/CMakeLists.txt
index ef1d907a64c..6cae59aed5b 100644
--- a/soc/espressif/esp32s2/CMakeLists.txt
+++ b/soc/espressif/esp32s2/CMakeLists.txt
@@ -14,64 +14,3 @@ zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c)
 
 zephyr_library_sources_ifdef(CONFIG_PM power.c)
 zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
-
-# get flash size to use in esptool as string
-math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000")
-
-if(NOT CONFIG_BOOTLOADER_MCUBOOT)
-
-  if(CONFIG_BUILD_OUTPUT_BIN)
-    # make ESP ROM loader compatible image
-    message("ESP-IDF path: ${ESP_IDF_PATH}")
-
-    set(ESPTOOL_PY ${ESP_IDF_PATH}/tools/esptool_py/esptool.py)
-    message("esptool path: ${ESPTOOL_PY}")
-
-    set(ELF2IMAGE_ARG "")
-    if(NOT CONFIG_MCUBOOT)
-      set(ELF2IMAGE_ARG "--ram-only-header")
-    endif()
-
-    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-      COMMAND ${PYTHON_EXECUTABLE} ${ESPTOOL_PY}
-      ARGS --chip esp32s2 elf2image ${ELF2IMAGE_ARG}
-      --flash_mode dio --flash_freq 40m
-      --flash_size ${esptoolpy_flashsize}MB
-      -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
-      ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
-  endif()
-
-endif()
-
-# Get code-partition boot address
-dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
-dt_reg_addr(boot_off PATH ${dts_partition_path})
-
-# Get code-partition slot0 address
-dt_nodelabel(dts_partition_path NODELABEL "slot0_partition")
-dt_reg_addr(img_0_off PATH ${dts_partition_path})
-
-if(CONFIG_BOOTLOADER_MCUBOOT)
-  board_finalize_runner_args(esp32 "--esp-app-address=${img_0_off}")
-else()
-  board_finalize_runner_args(esp32 "--esp-app-address=${boot_off}")
-endif()
-
-if(CONFIG_MCUBOOT)
-    # search from cross references between bootloader sections
-    message("check_callgraph using: ${ESP_IDF_PATH}/tools/ci/check_callgraph.py")
-    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-      COMMAND
-        ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/ci/check_callgraph.py
-      ARGS
-        --rtl-dirs ${CMAKE_BINARY_DIR}/zephyr
-	--elf-file ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf
-        find-refs --from-section=.iram0.iram_loader --to-section=.iram0.text
-        --exit-code)
-endif()
-
-if(CONFIG_MCUBOOT)
-  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
-else()
-  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "")
-endif()
diff --git a/soc/espressif/esp32s2/Kconfig.defconfig b/soc/espressif/esp32s2/Kconfig.defconfig
index ec58addff67..d79c78ba972 100644
--- a/soc/espressif/esp32s2/Kconfig.defconfig
+++ b/soc/espressif/esp32s2/Kconfig.defconfig
@@ -9,4 +9,7 @@ config FLASH_SIZE
 config FLASH_BASE_ADDRESS
 	default $(dt_node_reg_addr_hex,/soc/flash-controller@3f402000/flash@0)
 
+config MAIN_STACK_SIZE
+	default 2048
+
 endif # SOC_SERIES_ESP32S2
diff --git a/soc/espressif/esp32s2/default.ld b/soc/espressif/esp32s2/default.ld
index eaaeee11b03..623e061f8a9 100644
--- a/soc/espressif/esp32s2/default.ld
+++ b/soc/espressif/esp32s2/default.ld
@@ -23,12 +23,22 @@ user_iram_end = BOOTLOADER_IRAM_LOADER_SEG_START;
 #endif
 
 /* User available SRAM memory segments */
-user_iram_seg_org = SRAM_IRAM_START + SRAM_CACHE_SIZE;
-user_dram_seg_org = SRAM_DRAM_START + SRAM_CACHE_SIZE;
+user_iram_org = SRAM_IRAM_START + SRAM_CACHE_SIZE;
+user_dram_org = SRAM_DRAM_START + SRAM_CACHE_SIZE;
 user_dram_end = user_iram_end - IRAM_DRAM_OFFSET;
-user_sram_size = (user_dram_end - user_dram_seg_org);
-user_iram_seg_len = user_sram_size;
-user_dram_seg_len = user_sram_size;
+user_sram_size = (user_dram_end - user_dram_org);
+user_iram_len = user_sram_size;
+user_dram_len = user_sram_size;
+
+user_irom_org = ICACHE0_START;
+user_irom_len = ICACHE0_SIZE;
+user_drom_org = DCACHE0_START;
+user_drom_len = DCACHE0_SIZE;
+
+#if defined(CONFIG_ESP_SPIRAM)
+ext_ram_org = DCACHE1_START;
+ext_ram_len = DCACHE1_SIZE;
+#endif
 
 /* Aliases */
 #define FLASH_CODE_REGION irom0_0_seg
@@ -55,40 +65,42 @@ user_dram_seg_len = user_sram_size;
 #undef SECTION_PROLOGUE
 #define SECTION_PROLOGUE SECTION_DATA_PROLOGUE
 
-#define RESERVE_RTC_MEM 0
-
 MEMORY
 {
 #ifdef CONFIG_BOOTLOADER_MCUBOOT
   mcuboot_hdr (R): org = 0x0, len = 0x20
-  metadata (R):    org = 0x20, len = 0x20
-  FLASH (R):       org = 0x40, len = FLASH_SIZE
+  metadata (R):    org = 0x20, len = 0x60
+  FLASH (R):       org = 0x80, len = FLASH_SIZE - 0x80
 #else
   /* Make safety margin in the FLASH memory size so the
    * (esp_img_header + (n*esp_seg_headers)) would fit */
   FLASH (R): org = 0x0, len = FLASH_SIZE - 0x100
 #endif
 
-  iram0_0_seg(RX): org = user_iram_seg_org, len = user_iram_seg_len
-  dram0_0_seg(RW): org = user_dram_seg_org, len = user_dram_seg_len
+  iram0_0_seg(RX): org = user_iram_org, len = user_iram_len
+  dram0_0_seg(RW): org = user_dram_org, len = user_dram_len
 
-  irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
-  drom0_0_seg(R):  org = DROM_SEG_ORG, len = DROM_SEG_LEN
+  irom0_0_seg(RX): org = user_irom_org, len = user_irom_len
+  drom0_0_seg(R):  org = user_drom_org, len = user_drom_len
 
-  rtc_iram_seg(RWX): org = 0x40070000, len = 0x2000 - RESERVE_RTC_MEM
+  rtc_iram_seg(RWX): org = 0x40070000, len = 0x2000 - CONFIG_RESERVE_RTC_MEM
   rtc_slow_seg(RW):  org = 0x50000000, len = 0x2000
-  /* RTC fast memory (same block as above, rtc_iram_seg), viewed from data bus */
-  rtc_data_seg(RW) : org = 0x3ff9e000, len = 0x2000 - RESERVE_RTC_MEM
-  /* We reduced the size of rtc_data_seg and rtc_iram_seg by RESERVE_RTC_MEM value.
-   * It reserves the amount of RTC fast memory that we use for this memory segment.
-   * This segment is intended for keeping:
-   *  - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
-   *  - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
-   * The aim of this is to keep data that will not be moved around and have a fixed address.
-   */
-  rtc_reserved_seg(RW) : org = 0x3ff9e000 + 0x2000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM
+  rtc_data_seg(RW) : org = 0x3ff9e000, len = 0x2000 - CONFIG_RESERVE_RTC_MEM
+
+  /* We reduced the size of rtc_data_seg and rtc_iram_seg by CONFIG_RESERVE_RTC_MEM value.
+     It reserves the amount of RTC fast memory that we use for this memory segment.
+     This segment is intended for keeping:
+       - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
+       - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
+     The aim of this is to keep data that will not be moved around and have a fixed address.
+  */
+#if (CONFIG_RESERVE_RTC_MEM > 0)
+  rtc_reserved_seg(RW): org = 0x3ff9e000 + 0x2000 - CONFIG_RESERVE_RTC_MEM,
+                        len = CONFIG_RESERVE_RTC_MEM
+#endif
+
 #ifdef CONFIG_ESP_SPIRAM
-  ext_data_ram_seg(RW): org = 0x3f800000, len = CONFIG_ESP_SPIRAM_SIZE /* OR 0x780000 */
+  ext_ram_seg(RW): org = ext_ram_org, len = ext_ram_len
 #endif /* CONFIG_ESP_SPIRAM */
 
 #ifdef CONFIG_GEN_ISR_TABLES
@@ -103,6 +115,7 @@ _rom_store_table = 0;
 
 /* Used as a pointer to the heap end */
 _heap_sentry = DRAM_RESERVED_START;
+_libc_heap_size = _heap_sentry - _end;
 
 SECTIONS
 {
@@ -142,6 +155,42 @@ SECTIONS
     LONG(ADDR(.dram0.data))
     LONG(LOADADDR(.dram0.data))
     LONG(LOADADDR(.dram0.data_end) - LOADADDR(.dram0.data))
+
+    /* RTC_IRAM metadata:
+     * 8. Destination address (VMA) for RTC_IRAM region
+     * 9. Flash offset (LMA) for start of RTC_IRAM region
+     * 10. Size of RTC_IRAM region
+     */
+    LONG(ADDR(.rtc.text))
+    LONG(LOADADDR(.rtc.text))
+    LONG(SIZEOF(.rtc.text))
+
+    /* RTC_DRAM metadata:
+     * 11. Destination address (VMA) for RTC_DRAM region
+     * 12. Flash offset (LMA) for start of RTC_DRAM region
+     * 13. Size of RTC_DRAM region
+     */
+    LONG(ADDR(.rtc.data))
+    LONG(LOADADDR(.rtc.data))
+    LONG(SIZEOF(.rtc.data))
+
+    /* IROM metadata:
+     * 14. Destination address (VMA) for IROM region
+     * 15. Flash offset (LMA) for start of IROM region
+     * 16. Size of IROM region
+     */
+    LONG(ADDR(.flash.text))
+    LONG(LOADADDR(.flash.text))
+    LONG(SIZEOF(.flash.text))
+
+    /* DROM metadata:
+     * 17. Destination address (VMA) for DROM region
+     * 18. Flash offset (LMA) for start of DROM region
+     * 19. Size of DROM region
+     */
+    LONG(ADDR(.flash.rodata))
+    LONG(LOADADDR(.flash.rodata))
+    LONG(LOADADDR(.flash.rodata_end) - LOADADDR(.flash.rodata))
   } > metadata
 #endif /* CONFIG_BOOTLOADER_MCUBOOT */
 
@@ -154,128 +203,90 @@ SECTIONS
 
   /* --- START OF RTC --- */
 
-  /* RTC fast memory holds RTC wake stub code,
-   * including from any source file named rtc_wake_stub*.c
-   */
   .rtc.text :
   {
-    _rtc_text_start = ABSOLUTE(.);
     . = ALIGN(4);
-
-    _rtc_code_start = .;
-
-    /* mapping[rtc_text] */
-
-    *rtc_wake_stub*.*(.literal .text .literal.* .text.*)
-    _rtc_code_end = .;
-
-    /* possibly align + add 16B for CPU dummy speculative instr. fetch */
-    . = ((_rtc_code_end - _rtc_code_start) == 0) ? ALIGN(0) : ALIGN(4) + 16;
-
-    _rtc_text_end = ABSOLUTE(.);
+    *(.rtc.literal .rtc.literal.*)
+    *(.rtc.text .rtc.text.*)
+    . = ALIGN(4);
   } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)
 
   /*
-   * This section is required to skip rtc.text area because rtc_iram_seg and
-   * rtc_data_seg are reflect the same address space on different buses.
-   */
+    This section is required to skip rtc.text area because rtc_iram_seg and
+    rtc_data_seg reflect the same address space on different buses.
+  */
   .rtc.dummy :
   {
-    _rtc_dummy_start = ABSOLUTE(.);
-    _rtc_fast_start = ABSOLUTE(.);
     . = SIZEOF(.rtc.text);
-    _rtc_dummy_end = ABSOLUTE(.);
-  } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)
+  } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION)
 
   /* This section located in RTC FAST Memory area.
-   *  It holds data marked with RTC_FAST_ATTR attribute.
-   *  See the file "esp_attr.h" for more information.
-   */
+     It holds data marked with RTC_FAST_ATTR attribute.
+     See the file "esp_attr.h" for more information.
+  */
   .rtc.force_fast :
   {
     . = ALIGN(4);
-    _rtc_force_fast_start = ABSOLUTE(.);
-
-    /* mapping[rtc_force_fast] */
-
     *(.rtc.force_fast .rtc.force_fast.*)
-    . = ALIGN(4) ;
-    _rtc_force_fast_end = ABSOLUTE(.);
-  } > rtc_data_seg
+    . = ALIGN(4);
+  } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION)
 
   /* RTC data section holds RTC wake stub
-   *  data/rodata, including from any source file
-   *  named rtc_wake_stub*.c and the data marked with
-   *  RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
-   */
+     data/rodata, including from any source file
+     named rtc_wake_stub*.c and the data marked with
+     RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
+  */
   .rtc.data :
   {
+    . = ALIGN(4);
     _rtc_data_start = ABSOLUTE(.);
+    *(.rtc.data .rtc.data.*)
+    *(.rtc.rodata .rtc.rodata.*)
+    . = ALIGN(4);
+  } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)
 
-    /* mapping[rtc_data] */
-
-    *rtc_wake_stub*.*(.data .rodata .data.* .rodata.*)
-    _rtc_data_end = ABSOLUTE(.);
-  } > rtc_data_seg
-
-  /* RTC bss, from any source file named rtc_wake_stub*.c */
   .rtc.bss (NOLOAD) :
   {
     _rtc_bss_start = ABSOLUTE(.);
-    *rtc_wake_stub*.*(.bss .bss.*)
-    *rtc_wake_stub*.*(COMMON)
-
-    /* mapping[rtc_bss] */
-
+    *(.rtc.bss .rtc.bss.*)
     _rtc_bss_end = ABSOLUTE(.);
-  } > rtc_data_seg
+  } GROUP_LINK_IN(rtc_slow_seg)
 
-  /* This section holds data that should not be initialized at power up
-   *  and will be retained during deep sleep.
-   *  User data marked with RTC_NOINIT_ATTR will be placed
-   *  into this section. See the file "esp_attr.h" for more information.
-   */
-  .rtc_noinit (NOLOAD):
+  .rtc_noinit (NOLOAD) :
   {
     . = ALIGN(4);
-    _rtc_noinit_start = ABSOLUTE(.);
     *(.rtc_noinit .rtc_noinit.*)
     . = ALIGN(4) ;
-    _rtc_noinit_end = ABSOLUTE(.);
-  } > rtc_data_seg
+  } GROUP_LINK_IN(rtc_slow_seg)
 
   /* This section located in RTC SLOW Memory area.
-   *  It holds data marked with RTC_SLOW_ATTR attribute.
-   *  See the file "esp_attr.h" for more information.
+   * It holds data marked with RTC_SLOW_ATTR attribute.
+   * See the file "esp_attr.h" for more information.
    */
   .rtc.force_slow :
   {
     . = ALIGN(4);
-    _rtc_force_slow_start = ABSOLUTE(.);
     *(.rtc.force_slow .rtc.force_slow.*)
-    . = ALIGN(4) ;
+    . = ALIGN(4);
     _rtc_force_slow_end = ABSOLUTE(.);
-  } > rtc_slow_seg
+  } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)
+
+  /* Get size of rtc slow data */
+  _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start);
 
   /**
    * This section holds RTC data that should have fixed addresses.
    * The data are not initialized at power-up and are retained during deep sleep.
    */
-  .rtc_reserved (NOLOAD):
+#if (CONFIG_RESERVE_RTC_MEM > 0)
+  .rtc_reserved (NOLOAD) :
   {
     . = ALIGN(4);
     _rtc_reserved_start = ABSOLUTE(.);
-    /* New data can only be added here to ensure existing data are not moved.
-       Because data have adhered to the end of the segment and code is relied on it.
-       >> put new data here << */
-
     *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
-    KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*))
     _rtc_reserved_end = ABSOLUTE(.);
-  } > rtc_reserved_seg
-
-  /* Get size of rtc slow data */
-  _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start);
+  } GROUP_LINK_IN(rtc_reserved_seg)
+#endif
 
   /* --- END OF RTC --- */
 
@@ -367,6 +378,7 @@ SECTIONS
     *libzephyr.a:esp_psram_impl_octal.*(.literal .literal.* .text .text.*)
 
     /* [mapping:hal] */
+    *libzephyr.a:efuse_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:cache_utils.*(.literal .text .literal.* .text.*)
@@ -428,6 +440,7 @@ SECTIONS
     *libzephyr.a:mspi_timing_config.*(.literal .literal.* .text .text.*)
     *libzephyr.a:mspi_timing_tuning.*(.literal .literal.* .text .text.*)
     *libzephyr.a:periph_ctrl.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
     *(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable)
 
     /* [mapping:soc_pm] */
@@ -449,7 +462,7 @@ SECTIONS
 #if defined(CONFIG_ESP32_WIFI_IRAM_OPT)
     *libnet80211.a:(.wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiextrairam .wifiextrairam.*)
     *libpp.a:(.wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.* .wifiextrairam .wifiextrairam.*)
-    *libcoexist.a:(.wifi_slp_iram  .wifi_slp_iram.*)
+    *libcoexist.a:(.wifi_slp_iram  .wifi_slp_iram.* .coexiram .coexiram.* .coexsleepiram .coexsleepiram.*)
 
     /* [mapping:esp_wifi] */
     *(.literal.wifi_clock_enable_wrapper .text.wifi_clock_enable_wrapper)
@@ -499,7 +512,6 @@ SECTIONS
     *libzephyr.a:secure_boot.*(.literal .text .literal.* .text.*)
     *libzephyr.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
     *libzephyr.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
-    *libzephyr.a:efuse_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:esp_efuse_table.*(.literal .text .literal.* .text.*)
     *libzephyr.a:esp_efuse_fields.*(.literal .text .literal.* .text.*)
     *libzephyr.a:esp_efuse_api.*(.literal .text .literal.* .text.*)
@@ -550,7 +562,7 @@ SECTIONS
     /* This section is required to skip .iram0.text area because iram0_0_seg and
      * dram0_0_seg reflect the same address space on different buses.
      */
-    . = ORIGIN(dram0_0_seg) + MAX(_iram_end, user_iram_seg_org) - user_iram_seg_org;
+    . = ORIGIN(dram0_0_seg) + MAX(_iram_end, user_iram_org) - user_iram_org;
     . = ALIGN(4) + 16;
   } GROUP_LINK_IN(RAMABLE_REGION)
 
@@ -608,6 +620,7 @@ SECTIONS
     *libzephyr.a:esp_psram_impl_quad.*(.rodata .rodata.*)
 
     /* [mapping:hal] */
+    *libzephyr.a:efuse_hal.*(.rodata .rodata.*)
     *libzephyr.a:mmu_hal.*(.rodata .rodata.*)
     *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.*)
     *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.*)
@@ -725,8 +738,6 @@ SECTIONS
     *libzephyr.a:esp_flash_api.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
     *libzephyr.a:esp_flash_spi_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
 
-    *libzephyr.a:efuse_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
-
     . = ALIGN(4);
     _loader_data_end = ABSOLUTE(.);
   } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
@@ -779,30 +790,35 @@ SECTIONS
 
 #ifdef CONFIG_ESP_SPIRAM
   /* This section holds .ext_ram.bss data, and will be put in PSRAM */
-  .ext_ram.bss (NOLOAD):
+  .ext_ram (NOLOAD):
   {
-    _ext_ram_data_start = ABSOLUTE(.);
-    _ext_ram_bss_start = ABSOLUTE(.);
-    *(.ext_ram.bss*)
-    . = ALIGN(4);
-    _ext_ram_bss_end = ABSOLUTE(.);
-  } > ext_data_ram_seg
+    _ext_ram_start = ABSOLUTE(.);
+    _ext_ram_noinit_start = ABSOLUTE(.);
 
-  .ext_ram_noinit (NOLOAD) :
-  {
 #ifdef CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM
     *libdrivers__wifi.a:(.noinit .noinit.*)
     *libsubsys__net__l2__ethernet.a:(.noinit .noinit.*)
     *libsubsys__net__lib__config.a:(.noinit .noinit.*)
     *libsubsys__net__ip.a:(.noinit .noinit.*)
     *libsubsys__net.a:(.noinit .noinit.*)
-#endif /* CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM */
+#endif
+    . = ALIGN(16);
+    *(.ext_ram_noinit*)
+    . = ALIGN(16);
+    _ext_ram_noinit_end = ABSOLUTE(.);
 
-    _spiram_heap_start = ABSOLUTE(.);
+    _ext_ram_bss_start = ABSOLUTE(.);
+    *(.ext_ram.bss*)
+    . = ALIGN(16);
+    _ext_ram_bss_end = ABSOLUTE(.);
+
+    _ext_ram_heap_start = ABSOLUTE(.);
     . += CONFIG_ESP_SPIRAM_HEAP_SIZE;
+    . = ALIGN(16);
+    _ext_ram_heap_end = ABSOLUTE(.);
 
-    _ext_ram_data_end = ABSOLUTE(.);
-  } > ext_data_ram_seg
+    _ext_ram_end = ABSOLUTE(.);
+  } GROUP_LINK_IN(ext_ram_seg)
 #endif /* CONFIG_ESP_SPIRAM */
 
   .dram0.noinit (NOLOAD) :
@@ -843,7 +859,7 @@ SECTIONS
 #if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)
     *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiextrairam .wifiextrairam.*)
     *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.* .wifiextrairam .wifiextrairam.*)
-
+    *libcoexist.a:(.wifi_slp_iram  .wifi_slp_iram.* .coexiram .coexiram.* .coexsleepiram .coexsleepiram.*)
 #endif
 
 #if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)
@@ -1002,6 +1018,6 @@ SECTIONS
   /* --- XTENSA GLUE AND DEBUG END --- */
 
 #ifdef CONFIG_ESP_SPIRAM
-ASSERT(((_ext_ram_data_end - _ext_ram_data_start) <= CONFIG_ESP_SPIRAM_SIZE),
+ASSERT(((_ext_ram_end - _ext_ram_start) <= CONFIG_ESP_SPIRAM_SIZE),
           "External SPIRAM overflowed.")
 #endif /* CONFIG_ESP_SPIRAM */
diff --git a/soc/espressif/esp32s2/hw_init.c b/soc/espressif/esp32s2/hw_init.c
index e5381245559..abed31dd220 100644
--- a/soc/espressif/esp32s2/hw_init.c
+++ b/soc/espressif/esp32s2/hw_init.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -36,33 +36,17 @@ int hardware_init(void)
 #ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
 	esp_cpu_configure_region_protection();
 #endif
-#if CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V
-	rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
-
-	if (cfg.enable == 1 && cfg.tieh == RTC_VDDSDIO_TIEH_1_8V) {
-		cfg.drefh = 3;
-		cfg.drefm = 3;
-		cfg.drefl = 3;
-		cfg.force = 1;
-		rtc_vddsdio_set_config(cfg);
-		esp_rom_delay_us(10);
-	}
-#endif /* CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V */
 
 	bootloader_clock_configure();
 
+#ifdef CONFIG_ESP_CONSOLE
 	/* initialize console, from now on, we can log */
 	esp_console_init();
 	print_banner();
-
-	spi_flash_init_chip_state();
-	err = esp_flash_init_default_chip();
-	if (err != 0) {
-		ESP_EARLY_LOGE(TAG, "Failed to init flash chip, error %d", err);
-		return err;
-	}
+#endif /* CONFIG_ESP_CONSOLE */
 
 	cache_hal_init();
+
 	mmu_hal_init();
 
 	/* Workaround: normal ROM bootloader exits with DROM0 cache unmasked, but 2nd bootloader
diff --git a/soc/espressif/esp32s2/mcuboot.ld b/soc/espressif/esp32s2/mcuboot.ld
index bf14afeb6a3..b14ad89af4a 100644
--- a/soc/espressif/esp32s2/mcuboot.ld
+++ b/soc/espressif/esp32s2/mcuboot.ld
@@ -44,28 +44,17 @@ SECTIONS
     *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
 
     *libarch__xtensa__core.a:xtensa_asm2_util.*(.literal .text .literal.* .text.*)
-    *liblib__libc__common.a:abort.*(.literal .text .literal.* .text.*)
-    *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)
     *libarch__common.a:dynamic_isr.*(.literal .text .literal.* .text.*)
     *libarch__common.a:sw_isr_common.*(.literal .text .literal.* .text.*)
 
     *libapp.a:flash_map_extended.*(.literal .text .literal.* .text.*)
-    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)
     *libzephyr.a:cbprintf_nano.*(.literal .text .literal.* .text.*)
     *libzephyr.a:cpu.*(.literal .text .literal.* .text.*)
     *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:flash_map.*(.literal .text .literal.* .text.*)
     *libzephyr.a:esp_rom_spiflash.*(.literal .text .literal.* .text.*)
-    *libzephyr.a:heap.*(.literal .text .literal.* .text.*)
-    *libkernel.a:kheap.*(.literal .text .literal.* .text.*)
-    *libkernel.a:mempool.*(.literal .text .literal.* .text.*)
     *libkernel.a:device.*(.literal .text .literal.* .text.*)
-    *libkernel.a:timeout.*(.literal .text .literal.* .text.*)
     *libzephyr.a:esp_loader.*(.literal .text .literal.* .text.*)
-    *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
-    *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*)
-    *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*)
-    *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*)
 
     *(.literal.esp_intr_disable .literal.esp_intr_disable.* .text.esp_intr_disable .text.esp_intr_disable.*)
     *(.literal.default_intr_handler .text.default_intr_handler .iram1.*.default_intr_handler)
diff --git a/soc/espressif/esp32s2/memory.h b/soc/espressif/esp32s2/memory.h
index 4b6e8a17c36..92d49dd3dc4 100644
--- a/soc/espressif/esp32s2/memory.h
+++ b/soc/espressif/esp32s2/memory.h
@@ -53,16 +53,19 @@
 #define BOOTLOADER_DRAM_SEG_START \
 	(BOOTLOADER_IRAM_SEG_START - BOOTLOADER_DRAM_SEG_LEN - IRAM_DRAM_OFFSET)
 
+/* Cached memories */
+#define ICACHE0_START DT_REG_ADDR(DT_NODELABEL(icache0))
+#define ICACHE0_SIZE  DT_REG_SIZE(DT_NODELABEL(icache0))
+#define DCACHE0_START DT_REG_ADDR(DT_NODELABEL(dcache0))
+#define DCACHE0_SIZE  DT_REG_SIZE(DT_NODELABEL(dcache0))
+#define DCACHE1_START DT_REG_ADDR(DT_NODELABEL(dcache1))
+#define DCACHE1_SIZE  DT_REG_SIZE(DT_NODELABEL(dcache1))
+
+#define CACHE_ALIGN       CONFIG_MMU_PAGE_SIZE
+
 /* Flash */
 #ifdef CONFIG_FLASH_SIZE
 #define FLASH_SIZE        CONFIG_FLASH_SIZE
 #else
 #define FLASH_SIZE        0x400000
 #endif
-
-/* Cached memories */
-#define CACHE_ALIGN       CONFIG_MMU_PAGE_SIZE
-#define IROM_SEG_ORG      0x40080000
-#define IROM_SEG_LEN      0x780000
-#define DROM_SEG_ORG      0x3f000000
-#define DROM_SEG_LEN      FLASH_SIZE
diff --git a/soc/espressif/esp32s2/soc.c b/soc/espressif/esp32s2/soc.c
index 02a6d1b4dc6..bbb4fa973c5 100644
--- a/soc/espressif/esp32s2/soc.c
+++ b/soc/espressif/esp32s2/soc.c
@@ -1,85 +1,24 @@
 /*
- * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2021-2025 Espressif Systems (Shanghai) Co., Ltd.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/* Include esp-idf headers first to avoid redefining BIT() macro */
-#include "soc.h"
-#include <soc/rtc_cntl_reg.h>
-#include <soc/timer_group_reg.h>
-#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
-#include <xtensa/config/core-isa.h>
-#include <xtensa/corebits.h>
-#include <esp_private/spi_flash_os.h>
-#include <esp_private/esp_mmu_map_private.h>
-#include <esp_flash_internal.h>
-#if CONFIG_ESP_SPIRAM
-#include "psram.h"
-#endif
-
-#include <zephyr/kernel_structs.h>
-#include <kernel_internal.h>
-#include <string.h>
-#include <zephyr/toolchain.h>
-#include <zephyr/types.h>
-
+#include <soc.h>
+#include <soc_init.h>
+#include <flash_init.h>
+#include <esp_private/cache_utils.h>
 #include <esp_private/system_internal.h>
-#include <esp32s2/rom/cache.h>
-#include <soc/gpio_periph.h>
-#include <esp_cpu.h>
-#include <hal/cpu_hal.h>
-#include <hal/soc_hal.h>
-#include <hal/wdt_hal.h>
 #include <esp_timer.h>
-#include <esp_err.h>
-#include <esp_clk_internal.h>
+#include <psram.h>
+#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
 #include <zephyr/sys/printk.h>
-#include "esp_log.h"
-
-#define TAG "boot.esp32s2"
 
-extern void rtc_clk_cpu_freq_set_xtal(void);
-extern void esp_reset_reason_init(void);
 extern void z_prep_c(void);
+extern void esp_reset_reason_init(void);
 
-/*
- * This is written in C rather than assembly since, during the port bring up,
- * Zephyr is being booted by the Espressif bootloader.  With it, the C stack
- * is already set up.
- */
-void __attribute__((section(".iram1"))) __esp_platform_start(void)
+void IRAM_ATTR __esp_platform_app_start(void)
 {
-	extern uint32_t _init_start;
-
-	/* Move the exception vector table to IRAM. */
-	__asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start));
-
-	/* Zero out BSS */
-	z_bss_zero();
-
-	/* Disable normal interrupts. */
-	__asm__ __volatile__("wsr %0, PS" : : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE));
-
-	/* Initialize the architecture CPU pointer.  Some of the
-	 * initialization code wants a valid _current before
-	 * arch_kernel_init() is invoked.
-	 */
-	__asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0]));
-
-	esp_reset_reason_init();
-
-#ifndef CONFIG_MCUBOOT
-	/* ESP-IDF 2nd stage bootloader enables RTC WDT to check on startup sequence
-	 * related issues in application. Hence disable that as we are about to start
-	 * Zephyr environment.
-	 */
-	wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
-
-	wdt_hal_write_protect_disable(&rtc_wdt_ctx);
-	wdt_hal_disable(&rtc_wdt_ctx);
-	wdt_hal_write_protect_enable(&rtc_wdt_ctx);
-
 	/*
 	 * Configure the mode of instruction cache :
 	 * cache size, cache associated ways, cache line size.
@@ -96,23 +35,15 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void)
 	esp_config_data_cache_mode();
 	esp_rom_Cache_Enable_DCache(0);
 
-	esp_timer_early_init();
-
-	esp_mspi_pin_init();
+	esp_reset_reason_init();
 
-	esp_flash_app_init();
+	esp_timer_early_init();
 
-	esp_mmu_map_init();
+	esp_flash_config();
 
 #if CONFIG_ESP_SPIRAM
 	esp_init_psram();
-#endif /* CONFIG_ESP_SPIRAM */
-
-#endif /* !CONFIG_MCUBOOT */
 
-	esp_intr_initialize();
-
-#if CONFIG_ESP_SPIRAM
 	/* Init Shared Multi Heap for PSRAM */
 	int err = esp_psram_smh_init();
 
@@ -127,6 +58,14 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void)
 	CODE_UNREACHABLE;
 }
 
+void IRAM_ATTR __esp_platform_mcuboot_start(void)
+{
+	/* Start Zephyr */
+	z_prep_c();
+
+	CODE_UNREACHABLE;
+}
+
 /* Boot-time static default printk handler, possibly to be overridden later. */
 int IRAM_ATTR arch_printk_char_out(int c)
 {
@@ -139,5 +78,5 @@ int IRAM_ATTR arch_printk_char_out(int c)
 
 void sys_arch_reboot(int type)
 {
-	esp_restart_noos();
+	esp_restart();
 }
diff --git a/soc/espressif/esp32s2/soc.h b/soc/espressif/esp32s2/soc.h
index 2edd0d12cc9..9a5c5e97959 100644
--- a/soc/espressif/esp32s2/soc.h
+++ b/soc/espressif/esp32s2/soc.h
@@ -22,7 +22,8 @@
 #include <zephyr/arch/xtensa/arch.h>
 #include <stdlib.h>
 
-void __esp_platform_start(void);
+void __esp_platform_mcuboot_start(void);
+void __esp_platform_app_start(void);
 
 static inline uint32_t esp_core_id(void)
 {
diff --git a/soc/espressif/esp32s3/CMakeLists.txt b/soc/espressif/esp32s3/CMakeLists.txt
index 844aee7ebc3..48c6936487b 100644
--- a/soc/espressif/esp32s3/CMakeLists.txt
+++ b/soc/espressif/esp32s3/CMakeLists.txt
@@ -26,84 +26,3 @@ zephyr_library_sources_ifdef(CONFIG_NEWLIB_LIBC newlib_fix.c)
 # Power Management
 zephyr_library_sources_ifdef(CONFIG_PM power.c)
 zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
-
-# Get flash size to use in esptool as string
-math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000")
-
-# Get UART baudrate from DT
-dt_chosen(dts_shell_uart PROPERTY "zephyr,shell-uart")
-if(${dts_shell_uart})
-  dt_prop(monitor_baud PATH ${dts_shell_uart} PROPERTY "current-speed")
-endif()
-
-board_runner_args(esp32 "--esp-monitor-baud=${monitor_baud}")
-
-message("-- Espressif HAL path: ${ESP_IDF_PATH}")
-
-# Select image processing
-
-if(CONFIG_ESP_SIMPLE_BOOT OR CONFIG_MCUBOOT)
-
-  if(CONFIG_BUILD_OUTPUT_BIN)
-
-    set(ESPTOOL_PY ${ESP_IDF_PATH}/tools/esptool_py/esptool.py)
-    message("-- Use the esptool.py: ${ESPTOOL_PY}")
-
-    set(ELF2IMAGE_ARG "")
-    if(NOT CONFIG_MCUBOOT)
-      set(ELF2IMAGE_ARG "--ram-only-header")
-    endif()
-
-    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-      COMMAND ${PYTHON_EXECUTABLE} ${ESPTOOL_PY}
-      ARGS --chip ${CONFIG_SOC} elf2image ${ELF2IMAGE_ARG}
-      --flash_mode dio --flash_freq 40m
-      --flash_size ${esptoolpy_flashsize}MB
-      -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin
-      ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf)
-
-  endif()
-
-endif()
-
-set_property(TARGET bintools PROPERTY disassembly_flag_inline_source)
-
-# Select the image origin depending on the boot configuration
-if(CONFIG_SOC_ESP32S3_APPCPU)
-  dt_nodelabel(dts_partition_path NODELABEL "slot0_appcpu_partition")
-elseif(CONFIG_MCUBOOT)
-  dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
-elseif(CONFIG_ESP_SIMPLE_BOOT)
-  dt_nodelabel(dts_partition_path NODELABEL "boot_partition")
-else()
-  dt_nodelabel(dts_partition_path NODELABEL "slot0_partition")
-endif()
-
-dt_reg_addr(image_off PATH ${dts_partition_path})
-board_finalize_runner_args(esp32 "--esp-app-address=${image_off}")
-
-message("-- Image partition ${dts_partition_path}")
-
-# Look for cross references between bootloader sections
-if(CONFIG_MCUBOOT)
-
-    message("check_callgraph using: ${ESP_IDF_PATH}/tools/ci/check_callgraph.py")
-    set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
-      COMMAND
-        ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/ci/check_callgraph.py
-      ARGS
-        --rtl-dirs ${CMAKE_BINARY_DIR}/zephyr
-        --elf-file ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf
-        find-refs
-        --from-section='.iram0.loader_text'
-        --to-section='.iram0.text'
-        --exit-code)
-endif()
-
-if(CONFIG_MCUBOOT)
-  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/mcuboot.ld CACHE INTERNAL "")
-elseif(CONFIG_SOC_ESP32S3_APPCPU)
-  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default_appcpu.ld CACHE INTERNAL "")
-else()
-  set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/default.ld CACHE INTERNAL "")
-endif()
diff --git a/soc/espressif/esp32s3/Kconfig.defconfig b/soc/espressif/esp32s3/Kconfig.defconfig
index 110471dba62..171e1f8adce 100644
--- a/soc/espressif/esp32s3/Kconfig.defconfig
+++ b/soc/espressif/esp32s3/Kconfig.defconfig
@@ -12,4 +12,7 @@ config FLASH_BASE_ADDRESS
 config BOOTLOADER_MCUBOOT
 	default y if SOC_ESP32S3_APPCPU
 
+config MAIN_STACK_SIZE
+	default 4096
+
 endif # SOC_SERIES_ESP32S3
diff --git a/soc/espressif/esp32s3/default.ld b/soc/espressif/esp32s3/default.ld
index 5a193ba11e0..bba2fc40c4a 100644
--- a/soc/espressif/esp32s3/default.ld
+++ b/soc/espressif/esp32s3/default.ld
@@ -20,12 +20,31 @@ procpu_iram_len = procpu_iram_end - procpu_iram_org;
 procpu_dram_org = SRAM1_DRAM_START;
 procpu_dram_len = procpu_dram_end - procpu_dram_org;
 
+/* User available ROM memory segments */
+procpu_irom_end = ICACHE0_START + ICACHE0_SIZE - APPCPU_ROM_SIZE;
+procpu_drom_end = DCACHE0_START + DCACHE0_SIZE - APPCPU_ROM_SIZE;
+
+procpu_irom_org = ICACHE0_START;
+procpu_irom_len = ICACHE0_SIZE - APPCPU_ROM_SIZE;
+
+procpu_drom_org = DCACHE0_START;
+procpu_drom_len = DCACHE0_SIZE - APPCPU_ROM_SIZE;
+
+#if defined(CONFIG_ESP_SPIRAM)
+procpu_ext_dram_org = procpu_drom_org;
+procpu_ext_dram_len = CONFIG_ESP_SPIRAM_SIZE;
+procpu_ext_iram_org = procpu_irom_org;
+procpu_ext_iram_len = CONFIG_ESP_SPIRAM_SIZE;
+#endif
+
 /* Aliases */
-#define FLASH_CODE_REGION  irom0_0_seg
-#define RODATA_REGION      drom0_0_seg
-#define IRAM_REGION        iram0_0_seg
-#define RAMABLE_REGION     dram0_0_seg
-#define ROMABLE_REGION     FLASH
+#define FLASH_CODE_REGION irom0_0_seg
+#define RODATA_REGION     drom0_0_seg
+#define IRAM_REGION       iram0_0_seg
+#define RAMABLE_REGION    dram0_0_seg
+#define EXT_DRAM_REGION   ext_dram_seg
+#define EXT_IRAM_REGION   ext_iram_seg
+#define ROMABLE_REGION    FLASH
 
 /* Zephyr macro re-definitions */
 #undef GROUP_DATA_LINK_IN
@@ -49,41 +68,48 @@ procpu_dram_len = procpu_dram_end - procpu_dram_org;
 MEMORY
 {
 #ifdef CONFIG_BOOTLOADER_MCUBOOT
-  mcuboot_hdr (R):  org = 0x0,  len = 0x20
-  metadata (R):     org = 0x20, len = 0x20
-  FLASH (R):        org = 0x40, len = FLASH_SIZE - 0x40
+  mcuboot_hdr (R): org = 0x0,  len = 0x20
+  metadata (R):    org = 0x20, len = 0x60
+  FLASH (R):       org = 0x80, len = FLASH_SIZE - 0x80
 #else
   /* Make safety margin in the FLASH memory size so the
-   * (esp_img_header + (n*esp_seg_headers)) would fit */
-  FLASH (R):        org = 0x0, len = FLASH_SIZE - 0x100
+   * (esp_img_header + (n*esp_seg_headers)) would fit
+   */
+  FLASH (R):       org = 0x0, len = FLASH_SIZE - 0x100
 #endif /* CONFIG_BOOTLOADER_MCUBOOT */
 
   iram0_0_seg(RX): org = procpu_iram_org, len = procpu_iram_len
   dram0_0_seg(RW): org = procpu_dram_org, len = procpu_dram_len
 
-  irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
-  drom0_0_seg(R):  org = DROM_SEG_ORG, len = DROM_SEG_LEN
+  irom0_0_seg(RX): org = procpu_irom_org, len = procpu_irom_len
+  drom0_0_seg(R):  org = procpu_drom_org, len = procpu_drom_len
 
   /* The `ext_ram_seg` and `drom0_0_seg` share the same bus and the address region.
    * A dummy section is used to avoid overlap. See `.ext_ram.dummy` in `sections.ld.in`
    */
 #if defined(CONFIG_ESP_SPIRAM)
-  /* `ext_[id]ram_seg` and `drom0_0_seg` share the same bus and the address region.
+  /* `ext_dram_seg` and `drom0_0_seg` share the same bus and the address region.
    * A dummy section is used to avoid overlap. See `.ext_ram.dummy` */
-  ext_dram_seg(RW): org = DROM_SEG_ORG, len = (CONFIG_ESP_SPIRAM_SIZE)
-  ext_iram_seg(RX): org = IROM_SEG_ORG, len = (CONFIG_ESP_SPIRAM_SIZE)
+  ext_dram_seg(RW): org = procpu_ext_dram_org, len = procpu_ext_dram_len
+  ext_iram_seg(RX): org = procpu_ext_iram_org, len = procpu_ext_iram_len
 #endif
 
-  /* RTC fast memory (executable). Persists over deep sleep.
-   */
-  rtc_iram_seg(RWX): org = 0x600fe000, len = 0x2000
+  /* RTC fast memory (executable). Persists over deep sleep. */
+  rtc_iram_seg(RWX): org = 0x600fe000, len = 0x2000 - CONFIG_RESERVE_RTC_MEM
 
-  /* RTC fast memory (same block as above), viewed from data bus
+  /* We reduced the size of rtc_iram_seg by CONFIG_RESERVE_RTC_MEM value.
+   * It reserves the amount of RTC fast memory that we use for this memory segment.
+   * This segment is intended for keeping:
+   *   - (lower addr) rtc timer data (s_rtc_timer_retain_mem, see esp_clk.c files).
+   *   - (higher addr) bootloader rtc data (s_bootloader_retain_mem, when a Kconfig option is on).
+   * The aim of this is to keep data that will not be moved around and have a fixed address.
    */
-  rtc_data_seg(RW): org = 0x600fe000, len = 0x2000
+#if (CONFIG_RESERVE_RTC_MEM > 0)
+  rtc_reserved_seg(RW): org = 0x600fe000 + 0x2000 - CONFIG_RESERVE_RTC_MEM,
+                        len = CONFIG_RESERVE_RTC_MEM
+#endif
 
-  /* RTC slow memory (data accessible). Persists over deep sleep.
-   */
+  /* RTC slow memory (data accessible). Persists over deep sleep. */
   rtc_slow_seg(RW): org = 0x50000000, len = 0x2000
 
 #ifdef CONFIG_GEN_ISR_TABLES
@@ -94,13 +120,15 @@ MEMORY
 /*  Default entry point:  */
 ENTRY(CONFIG_KERNEL_ENTRY)
 
-/* Used as a pointer to the heap end */
+/* Heap size calculations differs between the APPCPU and PROCPU */
 #ifdef CONFIG_SOC_ENABLE_APPCPU
 _heap_sentry = procpu_dram_end;
 #else
 _heap_sentry = DRAM_RESERVED_START;
 #endif
 
+_libc_heap_size = _heap_sentry - _end;
+
 SECTIONS
 {
   _iram_dram_offset = IRAM_DRAM_OFFSET;
@@ -139,7 +167,43 @@ SECTIONS
      */
     LONG(ADDR(.dram0.data))
     LONG(LOADADDR(.dram0.data))
-    LONG(LOADADDR(.dram0.end) + SIZEOF(.dram0.end) - LOADADDR(.dram0.data))
+    LONG(LOADADDR(.dram0.data_end) + SIZEOF(.dram0.data_end) - LOADADDR(.dram0.data))
+
+    /* RTC_IRAM metadata:
+     * 8. Destination address (VMA) for RTC_IRAM region
+     * 9. Flash offset (LMA) for start of RTC_IRAM region
+     * 10. Size of RTC_IRAM region
+     */
+    LONG(ADDR(.rtc.text))
+    LONG(LOADADDR(.rtc.text))
+    LONG(SIZEOF(.rtc.text))
+
+    /* RTC_DRAM metadata:
+     * 11. Destination address (VMA) for RTC_DRAM region
+     * 12. Flash offset (LMA) for start of RTC_DRAM region
+     * 13. Size of RTC_DRAM region
+     */
+    LONG(ADDR(.rtc.data))
+    LONG(LOADADDR(.rtc.data))
+    LONG(SIZEOF(.rtc.data))
+
+    /* IROM metadata:
+     * 14. Destination address (VMA) for IROM region
+     * 15. Flash offset (LMA) for start of IROM region
+     * 16. Size of IROM region
+     */
+    LONG(ADDR(.flash.text))
+    LONG(LOADADDR(.flash.text))
+    LONG(SIZEOF(.flash.text))
+
+    /* DROM metadata:
+     * 17. Destination address (VMA) for DROM region
+     * 18. Flash offset (LMA) for start of DROM region
+     * 19. Size of DROM region
+     */
+    LONG(ADDR(.flash.rodata))
+    LONG(LOADADDR(.flash.rodata))
+    LONG(LOADADDR(.flash.rodata_end) - LOADADDR(.flash.rodata))
   } > metadata
 #endif /* CONFIG_BOOTLOADER_MCUBOOT */
 
@@ -156,11 +220,13 @@ SECTIONS
   .rtc.text :
   {
     . = ALIGN(4);
-    _rtc_fast_start = ABSOLUTE(.);
     _rtc_text_start = ABSOLUTE(.);
-    *(.rtc.entry.literal .rtc.text)
+    _rtc_fast_start = ABSOLUTE(.);
+    *(.rtc.literal .rtc.literal.*)
+    *(.rtc.text .rtc.text.*)
+    *(.rtc.entry.literal)
     *(.rtc.entry.text)
-    _rtc_text_end = ABSOLUTE(.);
+    . = ALIGN(4);
   } GROUP_DATA_LINK_IN(rtc_iram_seg, ROMABLE_REGION)
 
   /* This section located in RTC FAST Memory area.
@@ -171,30 +237,27 @@ SECTIONS
   {
     . = ALIGN(4);
     _rtc_force_fast_start = ABSOLUTE(.);
-
     *(.rtc.force_fast .rtc.force_fast.*)
-    . = ALIGN(4) ;
+    . = ALIGN(4);
     _rtc_force_fast_end = ABSOLUTE(.);
-  } GROUP_DATA_LINK_IN(rtc_data_seg, ROMABLE_REGION)
+  } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)
 
   /* RTC data section holds data marked with
    * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
    */
   .rtc.data :
   {
+  . = ALIGN(4);
     _rtc_data_start = ABSOLUTE(.);
-    *(.rtc.data)
-    *(.rtc.rodata)
+    *(.rtc.data .rtc.data.*)
+    *(.rtc.rodata .rtc.rodata.*)
     _rtc_data_end = ABSOLUTE(.);
   } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)
 
   .rtc.bss (NOLOAD) :
   {
     _rtc_bss_start = ABSOLUTE(.);
-
-    *(.rtc.data)
-    *(.rtc.rodata)
-
+    *(.rtc.bss .rtc.bss.*)
     _rtc_bss_end = ABSOLUTE(.);
   } GROUP_LINK_IN(rtc_slow_seg)
 
@@ -203,13 +266,11 @@ SECTIONS
    * User data marked with RTC_NOINIT_ATTR will be placed
    * into this section. See the file "esp_attr.h" for more information.
    */
-  .rtc_noinit (NOLOAD):
+  .rtc_noinit (NOLOAD) :
   {
     . = ALIGN(4);
-    _rtc_noinit_start = ABSOLUTE(.);
     *(.rtc_noinit .rtc_noinit.*)
     . = ALIGN(4) ;
-    _rtc_noinit_end = ABSOLUTE(.);
   } GROUP_LINK_IN(rtc_slow_seg)
 
   /* This section located in RTC SLOW Memory area.
@@ -225,13 +286,24 @@ SECTIONS
     _rtc_force_slow_end = ABSOLUTE(.);
   } GROUP_DATA_LINK_IN(rtc_slow_seg, ROMABLE_REGION)
 
+ /**
+   * This section holds RTC data that should have fixed addresses.
+   * The data are not initialized at power-up and are retained during deep sleep.
+   */
+#if (CONFIG_RESERVE_RTC_MEM > 0)
+  .rtc_reserved (NOLOAD) :
+  {
+    . = ALIGN(4);
+    _rtc_reserved_start = ABSOLUTE(.);
+    *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
+    _rtc_reserved_end = ABSOLUTE(.);
+  } GROUP_LINK_IN(rtc_reserved_seg)
+#endif
+
   /* Get size of rtc slow data based on rtc_data_location alias */
   _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start);
   _rtc_fast_length = (_rtc_force_fast_end - _rtc_fast_start);
 
-  ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)), "RTC_SLOW segment data does not fit.")
-  ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)), "RTC_FAST segment data does not fit.")
-
   /* --- END OF RTC --- */
 
   /* --- START OF IRAM --- */
@@ -326,6 +398,7 @@ SECTIONS
     *libzephyr.a:esp_psram_impl_octal.*(.literal .literal.* .text .text.*)
 
     /* [mapping:hal] */
+    *libzephyr.a:efuse_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:spi_flash_hal_iram.*(.literal .text .literal.* .text.*)
     *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .text .literal.* .text.*)
@@ -385,6 +458,7 @@ SECTIONS
     *libzephyr.a:systimer.*(.literal .literal.* .text .text.*)
     *libzephyr.a:mspi_timing_config.*(.literal .literal.* .text .text.*)
     *libzephyr.a:mspi_timing_tuning.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
     *(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable)
 
     /* [mapping:soc_pm] */
@@ -404,7 +478,7 @@ SECTIONS
 #if defined(CONFIG_ESP32_WIFI_IRAM_OPT)
     *libnet80211.a:(.wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiextrairam .wifiextrairam.*)
     *libpp.a:(.wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.* .wifiextrairam .wifiextrairam.*)
-    *libcoexist.a:(.wifi_slp_iram  .wifi_slp_iram.*)
+    *libcoexist.a:(.wifi_slp_iram  .wifi_slp_iram.* .coexiram .coexiram.* .coexsleepiram .coexsleepiram.*)
 
     /* [mapping:esp_wifi] */
     *(.literal.wifi_clock_enable_wrapper .text.wifi_clock_enable_wrapper)
@@ -505,8 +579,8 @@ SECTIONS
     /* Spacer section is required to skip .iram0.text area because
      * iram0_0_seg and dram0_0_seg reflect the same address space on different buses.
      */
-    . = ORIGIN(dram0_0_seg) + MAX(_iram_end, SRAM1_IRAM_START) - SRAM1_IRAM_START;
-    . = ALIGN(4) + 16;
+    . = ORIGIN(dram0_0_seg) + (MAX(_iram_end, SRAM1_IRAM_START) - SRAM1_IRAM_START);
+    . = ALIGN(16);
   } GROUP_LINK_IN(RAMABLE_REGION)
 
   .dram0.data :
@@ -567,6 +641,7 @@ SECTIONS
     *libzephyr.a:esp_psram_impl_quad.*(.rodata .rodata.*)
 
     /* [mapping:hal] */
+    *libzephyr.a:efuse_hal.*(.rodata .rodata.*)
     *libzephyr.a:mmu_hal.*(.rodata .rodata.*)
     *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.*)
     *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.*)
@@ -699,7 +774,7 @@ SECTIONS
   #include <zephyr/linker/common-rom/common-rom-logging.ld>
   #pragma pop_macro("GROUP_ROM_LINK_IN")
 
-  .dram0.end :
+  .dram0.data_end :
   {
     __data_end = ABSOLUTE(.);
     _data_end = ABSOLUTE(.);
@@ -794,6 +869,7 @@ SECTIONS
 #if !defined(CONFIG_ESP32_WIFI_IRAM_OPT)
     *libnet80211.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiextrairam .wifiextrairam.*)
     *libpp.a:( .wifi0iram  .wifi0iram.* .wifislpiram .wifislpiram.* .wifiorslpiram .wifiorslpiram.* .wifiextrairam .wifiextrairam.*)
+    *libcoexist.a:(.wifi_slp_iram  .wifi_slp_iram.* .coexiram .coexiram.* .coexsleepiram .coexsleepiram.*)
 #endif
 
 #if !defined(CONFIG_ESP32_WIFI_RX_IRAM_OPT)
@@ -912,22 +988,17 @@ SECTIONS
 
   /* --- START OF SPIRAM --- */
 
-  /**
-   * This section is required to skip flash rodata sections, because `ext_ram_seg`
-   * and `drom0_0_seg` are on the same bus
-   */
 #if defined(CONFIG_ESP_SPIRAM)
-
-  /* This section is required to skip flash rodata sections, because `ext_[id]ram_seg`
+  /* This section is required to skip flash rodata sections, because SPIRAM
    * and `drom0_0_seg` are on the same bus */
   .ext_ram.dummy (NOLOAD):
   {
     . = ADDR(.flash.rodata_end) - ORIGIN(ext_dram_seg);
     . = ALIGN (CACHE_ALIGN);
-  } GROUP_LINK_IN(ext_dram_seg)
+  } GROUP_LINK_IN(EXT_DRAM_REGION)
 
   /* This section holds .ext_ram.bss data, and will be put in PSRAM */
-  .ext_ram.bss (NOLOAD) :
+  .ext_ram.data (NOLOAD) :
   {
     _ext_ram_start = ABSOLUTE(.);
     _ext_ram_noinit_start = ABSOLUTE(.);
@@ -938,7 +1009,9 @@ SECTIONS
     *libsubsys__net__lib__config.a:(.noinit .noinit.*)
     *libsubsys__net__ip.a:(.noinit .noinit.*)
     *libsubsys__net.a:(.noinit .noinit.*)
-#endif /* CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM */
+#endif
+    . = ALIGN(16);
+    *(.ext_ram_noinit.*)
     . = ALIGN(16);
     _ext_ram_noinit_end = ABSOLUTE(.);
 
@@ -947,13 +1020,13 @@ SECTIONS
     . = ALIGN(16);
     _ext_ram_bss_end = ABSOLUTE(.);
 
-    _spiram_heap_start = ABSOLUTE(.);
-    . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE - (_spiram_heap_start - _ext_ram_bss_start);
-    . = ALIGN(4);
+    _ext_ram_heap_start = ABSOLUTE(.);
+    . += CONFIG_ESP_SPIRAM_HEAP_SIZE;
+    . = ALIGN(16);
+    _ext_ram_heap_end = ABSOLUTE(.);
 
     _ext_ram_end = ABSOLUTE(.);
-  } GROUP_LINK_IN(ext_dram_seg)
-
+  } GROUP_LINK_IN(EXT_DRAM_REGION)
 #endif /* CONFIG_ESP_SPIRAM */
 
   /* --- END OF SPIRAM --- */
diff --git a/soc/espressif/esp32s3/default_appcpu.ld b/soc/espressif/esp32s3/default_appcpu.ld
index 37b648be039..ef11fccb218 100644
--- a/soc/espressif/esp32s3/default_appcpu.ld
+++ b/soc/espressif/esp32s3/default_appcpu.ld
@@ -24,11 +24,19 @@ appcpu_dram_org = appcpu_dram_end - APPCPU_SRAM_SIZE;
 appcpu_iram_len = APPCPU_SRAM_SIZE;
 appcpu_dram_len = APPCPU_SRAM_SIZE;
 
+/* User available ROM memory segments */
+appcpu_irom_org = (ICACHE0_START + ICACHE0_SIZE) - APPCPU_ROM_SIZE;
+appcpu_drom_org = (DCACHE0_START + DCACHE0_SIZE) - APPCPU_ROM_SIZE;
+
+appcpu_irom_len = APPCPU_ROM_SIZE;
+appcpu_drom_len = APPCPU_ROM_SIZE;
+
 /* Aliases */
-#define ROMABLE_REGION   FLASH
-#define RODATA_REGION    dram0_1_seg /* drom0_1_seg */
-#define RAMABLE_REGION   dram0_1_seg
-#define IRAM_REGION      iram0_1_seg
+#define FLASH_CODE_REGION irom0_1_seg
+#define RODATA_REGION     drom0_1_seg
+#define IRAM_REGION       iram0_1_seg
+#define RAMABLE_REGION    dram0_1_seg
+#define ROMABLE_REGION    FLASH
 
 /* Zephyr macro re-definitions */
 #undef GROUP_DATA_LINK_IN
@@ -51,13 +59,16 @@ appcpu_dram_len = APPCPU_SRAM_SIZE;
 
 MEMORY
 {
-  mcuboot_hdr (R):  org = 0x0,  len = 0x20
-  metadata (R):     org = 0x20, len = 0x20
-  FLASH (R):        org = 0x40, len = FLASH_SIZE - 0x40
+  mcuboot_hdr (R): org = 0x0,  len = 0x20
+  metadata (R):    org = 0x20, len = 0x60
+  FLASH (R):       org = 0x80, len = FLASH_SIZE - 0x80
 
   iram0_1_seg(RX): org = appcpu_iram_org, len = appcpu_iram_len
   dram0_1_seg(RW): org = appcpu_dram_org, len = appcpu_dram_len
 
+  irom0_1_seg(RX): org = appcpu_irom_org, len = appcpu_irom_len
+  drom0_1_seg(R):  org = appcpu_drom_org, len = appcpu_drom_len
+
 #ifdef CONFIG_GEN_ISR_TABLES
   IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000
 #endif
@@ -66,8 +77,9 @@ MEMORY
 /*  Default entry point:  */
 ENTRY(__appcpu_start)
 
-/* Used as a pointer to the heap end */
+/* Heap size calculations for APPCPU */
 _heap_sentry = DRAM_RESERVED_START;
+_libc_heap_size = _heap_sentry - _end;
 
 SECTIONS
 {
@@ -105,6 +117,42 @@ SECTIONS
     LONG(ADDR(.dram0.data))
     LONG(LOADADDR(.dram0.data))
     LONG(_data_end - _data_start)
+
+    /* RTC_IRAM metadata:
+     * 8. Destination address (VMA) for RTC_IRAM region
+     * 9. Flash offset (LMA) for start of RTC_IRAM region
+     * 10. Size of RTC_IRAM region
+     */
+    LONG(0);
+    LONG(0);
+    LONG(0);
+
+    /* RTC_DRAM metadata:
+     * 11. Destination address (VMA) for RTC_DRAM region
+     * 12. Flash offset (LMA) for start of RTC_DRAM region
+     * 13. Size of RTC_DRAM region
+     */
+    LONG(0);
+    LONG(0);
+    LONG(0);
+
+    /* IROM metadata:
+     * 14. Destination address (VMA) for IROM region
+     * 15. Flash offset (LMA) for start of IROM region
+     * 16. Size of IROM region
+     */
+    LONG(_image_irom_vaddr);
+    LONG(_image_irom_start);
+    LONG(_image_irom_size);
+
+    /* DROM metadata:
+     * 17. Destination address (VMA) for DROM region
+     * 18. Flash offset (LMA) for start of DROM region
+     * 19. Size of DROM region
+     */
+    LONG(_image_drom_vaddr);
+    LONG(_image_drom_start);
+    LONG(_image_drom_size);
   } > metadata
 
   #include <zephyr/linker/rel-sections.ld>
@@ -158,21 +206,18 @@ SECTIONS
 
   .iram0.text : ALIGN(4)
   {
+    /* Code marked as running out of IRAM */
     _iram_text_start = ABSOLUTE(.);
     *(.iram1 .iram1.*)
     *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
-    *libesp32.a:panic.*(.literal .text .literal.* .text.*)
-    *librtc.a:(.literal .text .literal.* .text.*)
     *libarch__xtensa__core.a:(.literal .text .literal.* .text.*)
     *libkernel.a:(.literal .text .literal.* .text.*)
-    *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*)
-    *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*)
     *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:cbprintf_packaged.*(.literal .text .literal.* .text.*)
     *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*)
     *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*)
     *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*)
     *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)
-    *libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:log_core.*(.literal .text .literal.* .text.*)
     *libzephyr.a:cbprintf_complete.*(.literal .text .literal.* .text.*)
     *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)
@@ -181,50 +226,138 @@ SECTIONS
     *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out)
     *libzephyr.a:log_output.*(.literal .text .literal.* .text.*)
     *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:log_minimal.*(.literal .literal.* .text .text.*)
     *libzephyr.a:loader.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:flash_init.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:soc_flash_init.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:console_init.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:soc_init.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:hw_init.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:soc_random.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:esp_mmu_map.*(.literal .literal.* .text .text.*)
+    *libdrivers__interrupt_controller.a:(.literal .literal.* .text .text.*)
     *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*)
     *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*)
-    *libc.a:*(.literal .text .literal.* .text.*)
+    *liblib__libc__picolibc.a:string.*(.literal .text .literal.* .text.*)
     *libphy.a:(.phyiram .phyiram.*)
     *libgcov.a:(.literal .text .literal.* .text.*)
 
+    /* APPCPU_ENABLED */
+    *libzephyr.a:bootloader_flash.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:flash_mmap.*(.literal .text .literal.* .text.*)
+
+    /* [mapping:esp_psram] */
+    *libzephyr.a:mmu_psram_flash.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:esp_psram_impl_quad.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:esp_psram_impl_octal.*(.literal .literal.* .text .text.*)
+
+    /* [mapping:hal] */
+    *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:spi_flash_hal_iram.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:ledc_hal_iram.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:i2c_hal_iram.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:systimer_hal.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:spi_flash_hal_gpspi.*(.literal .text .literal.* .text.*)
+
+    /* [mapping:soc] */
+    *libzephyr.a:lldesc.*(.literal .literal.* .text .text.*)
+
+    /* [mapping:log] */
+    *(.literal.esp_log_write .text.esp_log_write)
+    *(.literal.esp_log_timestamp .text.esp_log_timestamp)
+    *(.literal.esp_log_early_timestamp .text.esp_log_early_timestamp)
+    *(.literal.esp_log_impl_lock .text.esp_log_impl_lock)
+    *(.literal.esp_log_impl_lock_timeout .text.esp_log_impl_lock_timeout)
+    *(.literal.esp_log_impl_unlock .text.esp_log_impl_unlock)
+
+    /* [mapping:spi_flash] */
+    *libzephyr.a:spi_flash_chip_boya.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:spi_flash_chip_gd.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:spi_flash_chip_generic.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:spi_flash_chip_issi.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:spi_flash_chip_mxic.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:spi_flash_chip_mxic_opi.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:spi_flash_chip_th.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:spi_flash_chip_winbond.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:memspi_host_driver.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:flash_brownout_hook.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:spi_flash_wrap.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:spi_flash_hpm_enable.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:spi_flash_oct_flash_init.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:flash_ops.*(.literal .literal.* .text .text.*)
+
+    /* [mapping:esp_system] */
+    *libzephyr.a:esp_err.*(.literal .literal.* .text .text.*)
+    *(.literal.esp_system_abort .text.esp_system_abort)
+
+    /* [mapping:esp_hw_support] */
+    *(.literal.esp_cpu_stall .text.esp_cpu_stall)
+    *(.literal.esp_cpu_unstall .text.esp_cpu_unstall)
+    *(.literal.esp_cpu_reset .text.esp_cpu_reset)
+    *(.literal.esp_cpu_wait_for_intr .text.esp_cpu_wait_for_intr)
+    *(.literal.esp_cpu_compare_and_set .text.esp_cpu_compare_and_set)
+    *(.literal.esp_gpio_reserve_pins .text.esp_gpio_reserve_pins)
+    *(.literal.esp_gpio_is_pin_reserved .text.esp_gpio_is_pin_reserved)
+    *(.literal.rtc_vddsdio_get_config .text.rtc_vddsdio_get_config)
+    *(.literal.rtc_vddsdio_set_config .text.rtc_vddsdio_set_config)
+    *libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:rtc_clk_init.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:systimer.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:mspi_timing_config.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:mspi_timing_tuning.*(.literal .literal.* .text .text.*)
+    *(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable)
+
+    /* [mapping:soc_pm] */
+    *(.literal.GPIO_HOLD_MASK .text.GPIO_HOLD_MASK)
+
+    /* [mapping:esp_rom] */
+    *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:cache_utils.*(.literal .text .literal.* .text.*)
+    *libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:esp_rom_systimer.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:esp_rom_wdt.*(.literal .literal.* .text .text.*)
+    *libzephyr.a:esp_rom_efuse.*(.literal .literal.* .text .text.*)
+
+    /* [mapping:esp_mm] */
+    *libzephyr.a:esp_cache.*(.literal .literal.* .text .text.*)
+
     . = ALIGN(16);
 
   } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
 
-  .flash.text : ALIGN(16)
+  /* Marks the end of IRAM code segment */
+  .iram0.text_end (NOLOAD) :
   {
-    _stext = .;
-    _text_start = ABSOLUTE(.);
-
-    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
-    *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
-    *(.fini.literal)
-    *(.fini)
-    *(.gnu.version)
-    *(.literal .text .literal.* .text.*)
-
-    /* CPU will try to prefetch up to 16 bytes of
-     * of instructions. This means that any configuration (e.g. MMU, PMS) must allow
-     * safe access to up to 16 bytes after the last real instruction, add
-     * dummy bytes to ensure this
-     */
-    . += 16;
-
-    _text_end = ABSOLUTE(.);
-    _etext = .;
+    /* ESP32-S3 memprot requires 16B padding for possible CPU prefetch and 256B alignment for PMS split lines */
+    . = ALIGN(4) + 16;
+    _iram_text_end = ABSOLUTE(.);
+  } GROUP_LINK_IN(IRAM_REGION)
 
-    /* Similar to _iram_start, this symbol goes here so it is
-     * resolved by addr2line in preference to the first symbol in
-     * the flash.text segment.
-     */
+  .iram0.data :
+  {
     . = ALIGN(4);
-    _flash_cache_start = ABSOLUTE(0);
+    _iram_data_start = ABSOLUTE(.);
+    *(.iram.data)
+    *(.iram.data*)
+    _iram_data_end = ABSOLUTE(.);
+  } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
 
+  .iram0.bss (NOLOAD) :
+  {
+    . = ALIGN(4);
+    _iram_bss_start = ABSOLUTE(.);
+    *(.iram.bss)
+    *(.iram.bss*)
+    _iram_bss_end = ABSOLUTE(.);
     . = ALIGN(4);
     _iram_end = ABSOLUTE(.);
-
-  } GROUP_DATA_LINK_IN(IRAM_REGION, ROMABLE_REGION)
+  } GROUP_LINK_IN(IRAM_REGION)
 
   /* --- END OF IRAM --- */
 
@@ -232,15 +365,21 @@ SECTIONS
 
   .dram0.dummy (NOLOAD):
   {
-    . = ORIGIN(dram0_1_seg) + MAX(_iram_end, appcpu_iram_org) - appcpu_iram_org;
+    . = ORIGIN(dram0_1_seg) + (MAX(_iram_end, _init_start) - _init_start);
     . = ALIGN(16);
   } GROUP_LINK_IN(RAMABLE_REGION)
 
   .dram0.data :
   {
     . = ALIGN (8);
-    __data_start = ABSOLUTE(.);
     _data_start = ABSOLUTE(.);
+    __data_start = ABSOLUTE(.);
+
+    /*  bluetooth library requires this symbol to be defined */
+    _btdm_data_start = ABSOLUTE(.);
+    *libbtdm_app.a:(.data .data.*)
+    . = ALIGN (4);
+    _btdm_data_end = ABSOLUTE(.);
 
     *(.data)
     *(.data.*)
@@ -252,20 +391,126 @@ SECTIONS
     *(.sdata2)
     *(.sdata2.*)
     *(.gnu.linkonce.s2.*)
+    *(.srodata)
+    *(.srodata.*)
     /* rodata for panic handler(libarch__xtensa__core.a) and all
      * dependent functions should be placed in DRAM to avoid issue
      * when flash cache is disabled */
     *libarch__xtensa__core.a:(.rodata .rodata.*)
     *libkernel.a:fatal.*(.rodata .rodata.*)
     *libkernel.a:init.*(.rodata .rodata.*)
-    *libzephyr.a:cbprintf_complete*(.rodata .rodata.*)
-    *libzephyr.a:systimer_hal.*(.rodata .rodata.*)
+    *libzephyr.a:cbprintf_complete.*(.rodata .rodata.*)
     *libzephyr.a:log_core.*(.rodata .rodata.*)
     *libzephyr.a:log_backend_uart.*(.rodata .rodata.*)
     *libzephyr.a:log_output.*(.rodata .rodata.*)
+    *libzephyr.a:log_minimal.*(.rodata .rodata.*)
     *libzephyr.a:loader.*(.rodata .rodata.*)
+    *libzephyr.a:flash_init.*(.rodata .rodata.*)
+    *libzephyr.a:soc_flash_init.*(.rodata .rodata.*)
+    *libzephyr.a:console_init.*(.rodata .rodata.*)
+    *libzephyr.a:soc_init.*(.rodata .rodata.*)
+    *libzephyr.a:hw_init.*(.rodata .rodata.*)
+    *libzephyr.a:soc_random.*(.rodata .rodata.*)
     *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*)
-    *libdrivers__flash.a:flash_esp32.*(.rodata  .rodata.*)
+    *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*)
+    *libzephyr.a:esp_mmu_map.*(.rodata .rodata.*)
+    *libdrivers__interrupt_controller.a:(.rodata .rodata.*)
+
+    /* APPCPU_ENABLE */
+    *libzephyr.a:esp32s3-mp.*(.rodata .rodata.*)
+    *libzephyr.a:bootloader_flash.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
+    *libzephyr.a:flash_mmap.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*)
+
+    /* [mapping:esp_psram] */
+    *libzephyr.a:mmu_psram_flash.*(.rodata .rodata.*)
+    *libzephyr.a:esp_psram_impl_octal.*(.rodata .rodata.*)
+    *libzephyr.a:esp_psram_impl_quad.*(.rodata .rodata.*)
+
+    /* [mapping:hal] */
+    *libzephyr.a:mmu_hal.*(.rodata .rodata.*)
+    *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.*)
+    *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.*)
+    *libzephyr.a:cache_hal.*(.rodata .rodata.*)
+    *libzephyr.a:ledc_hal_iram.*(.rodata .rodata.*)
+    *libzephyr.a:i2c_hal_iram.*(.rodata .rodata.*)
+    *libzephyr.a:wdt_hal_iram.*(.rodata .rodata.*)
+    *libzephyr.a:systimer_hal.*(.rodata .rodata.*)
+    *libzephyr.a:spi_flash_hal_gpspi.*(.rodata .rodata.*)
+
+    /* [mapping:soc] */
+    *libzephyr.a:lldesc.*(.rodata .rodata.*)
+
+    /* [mapping:log] */
+    *(.rodata.esp_log_write)
+    *(.rodata.esp_log_timestamp)
+    *(.rodata.esp_log_early_timestamp)
+    *(.rodata.esp_log_impl_lock)
+    *(.rodata.esp_log_impl_lock_timeout)
+    *(.rodata.esp_log_impl_unlock)
+
+    /* [mapping:spi_flash] */
+    *libzephyr.a:spi_flash_chip_boya.*(.rodata .rodata.*)
+    *libzephyr.a:spi_flash_chip_gd.*(.rodata .rodata.*)
+    *libzephyr.a:spi_flash_chip_generic.*(.rodata .rodata.*)
+    *libzephyr.a:spi_flash_chip_issi.*(.rodata .rodata.*)
+    *libzephyr.a:spi_flash_chip_mxic.*(.rodata .rodata.*)
+    *libzephyr.a:spi_flash_chip_mxic_opi.*(.rodata .rodata.*)
+    *libzephyr.a:spi_flash_chip_th.*(.rodata .rodata.*)
+    *libzephyr.a:spi_flash_chip_winbond.*(.rodata .rodata.*)
+    *libzephyr.a:memspi_host_driver.*(.rodata .rodata.*)
+    *libzephyr.a:flash_brownout_hook.*(.rodata .rodata.*)
+    *libzephyr.a:spi_flash_wrap.*(.rodata .rodata.*)
+    *libzephyr.a:spi_flash_hpm_enable.*(.rodata .rodata.*)
+    *libzephyr.a:spi_flash_oct_flash_init.*(.rodata .rodata.*)
+    *libzephyr.a:flash_qio_mode.*(.rodata .rodata.*)
+    *libzephyr.a:flash_ops.*(.rodata .rodata.*)
+
+    /* [mapping:esp_mm] */
+    *libzephyr.a:esp_cache.*(.rodata .rodata.*)
+
+    /* [mapping:esp_hw_support] */
+    *(.rodata.esp_cpu_stall)
+    *(.rodata.esp_cpu_unstall)
+    *(.rodata.esp_cpu_reset)
+    *(.rodata.esp_cpu_wait_for_intr)
+    *(.rodata.esp_cpu_compare_and_set)
+    *(.rodata.esp_gpio_reserve_pins)
+    *(.rodata.esp_gpio_is_pin_reserved)
+    *(.rodata.rtc_vddsdio_get_config)
+    *(.rodata.rtc_vddsdio_set_config)
+    *libzephyr.a:esp_memory_utils.*(.rodata .rodata.*)
+    *libzephyr.a:rtc_clk.*(.rodata .rodata.*)
+    *libzephyr.a:rtc_clk_init.*(.rodata .rodata.*)
+    *libzephyr.a:systimer.*(.rodata .rodata.*)
+    *libzephyr.a:mspi_timing_config.*(.rodata .rodata.*)
+    *libzephyr.a:mspi_timing_tuning.*(.rodata .rodata.*)
+    *(.rodata.sar_periph_ctrl_power_enable)
+
+    /* [mapping:soc_pm] */
+    *(.rodata.GPIO_HOLD_MASK)
+
+    /* [mapping:esp_rom] */
+    *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.rodata .rodata.*)
+    *libzephyr.a:cache_utils.*(.rodata .rodata.*)
+    *libzephyr.a:esp_rom_spiflash.*(.rodata .rodata.*)
+    *libzephyr.a:esp_rom_systimer.*(.rodata .rodata.*)
+    *libzephyr.a:esp_rom_wdt.*(.rodata .rodata.*)
+    *libzephyr.a:esp_rom_efuse.*(.rodata .rodata.*)
+
+    /* [mapping:esp_system] */
+    *libzephyr.a:esp_err.*(.rodata .rodata.*)
+    *(.rodata.esp_system_abort)
+
+#if defined(CONFIG_ESP32_WIFI_IRAM_OPT)
+    /* [mapping:esp_wifi] */
+    *(.rodata.wifi_clock_enable_wrapper)
+    *(.rodata.wifi_clock_disable_wrapper)
+
+    /* [mapping:esp_phy] */
+    *(.rodata.esp_phy_enable)
+    *(.rodata.esp_phy_disable)
+    *(.rodata.esp_wifi_bt_power_domain_off)
+#endif
 
     . = ALIGN(4);
     #include <snippets-rwdata.ld>
@@ -273,7 +518,7 @@ SECTIONS
 
     KEEP(*(.jcr))
     *(.dram1 .dram1.*)
-    . = ALIGN(16);
+    . = ALIGN(4);
 
   } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
 
@@ -282,9 +527,135 @@ SECTIONS
   #include <snippets-ram-sections.ld>
   #include <zephyr/linker/cplusplus-ram.ld>
   #include <zephyr/linker/kobject-data.ld>
+
+  /* logging sections should be placed in RAM area to avoid flash cache disabled issues */
+  #pragma push_macro("GROUP_ROM_LINK_IN")
+  #undef GROUP_ROM_LINK_IN
+  #define GROUP_ROM_LINK_IN GROUP_DATA_LINK_IN
   #include <zephyr/linker/common-rom/common-rom-logging.ld>
+  #pragma pop_macro("GROUP_ROM_LINK_IN")
+
+  .dram0.data_end :
+  {
+    __data_end = ABSOLUTE(.);
+    _data_end = ABSOLUTE(.);
+  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
+
+  .dram0.noinit (NOLOAD):
+  {
+    . = ALIGN(8);
+    *(.noinit)
+    *(.noinit.*)
+    . = ALIGN(8) ;
+  } GROUP_LINK_IN(RAMABLE_REGION)
+
+  /* Shared RAM */
+  .dram0.bss (NOLOAD) :
+  {
+    . = ALIGN (8);
+    _bss_start = ABSOLUTE(.); /* required by bluetooth library */
+    __bss_start = ABSOLUTE(.);
+
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(.bss.*)
+    *(.share.mem)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    __bss_end = ABSOLUTE(.);
+  } GROUP_LINK_IN(RAMABLE_REGION)
+
+  /* Provide total SRAM usage, including IRAM and DRAM */
+  _image_ram_start = _init_start - IRAM_DRAM_OFFSET;
+  #include <zephyr/linker/ram-end.ld>
+
+  ASSERT(((__bss_end - ORIGIN(dram0_1_seg)) <= LENGTH(dram0_1_seg)), "DRAM segment data does not fit.")
 
-  .dram0.rodata : ALIGN(4)
+  /* --- END OF DRAM --- */
+
+  /* --- START OF IROM --- */
+
+  /* Symbols used during the application memory mapping */
+  _image_irom_start = LOADADDR(.flash.text);
+  _image_irom_size = LOADADDR(.flash.text) + SIZEOF(.flash.text) - _image_irom_start;
+  _image_irom_vaddr = ADDR(.flash.text);
+
+  /* Align next section to 64k to allow mapping */
+  .flash.text_dummy (NOLOAD) :
+  {
+    . = ALIGN(CACHE_ALIGN);
+  } GROUP_LINK_IN(ROMABLE_REGION)
+
+  .flash.text : ALIGN(16)
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+
+    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+    *(.literal .text .literal.* .text.*)
+
+    /* CPU will try to prefetch up to 16 bytes of
+     * of instructions. This means that any configuration (e.g. MMU, PMS) must allow
+     * safe access to up to 16 bytes after the last real instruction, add
+     * dummy bytes to ensure this
+     */
+    . += 16;
+
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+
+    /* Similar to _iram_start, this symbol goes here so it is
+     * resolved by addr2line in preference to the first symbol in
+     * the flash.text segment.
+     */
+    . = ALIGN(4);
+    _flash_cache_start = ABSOLUTE(0);
+
+    . = ALIGN(4);
+
+  } GROUP_DATA_LINK_IN(FLASH_CODE_REGION, ROMABLE_REGION)
+
+  /* --- END OF IROM --- */
+
+  /* --- START OF DROM --- */
+
+  /* This dummy section represents the .flash.text section but in default_rodata_seg.
+   * Thus, it must have its alignment and (at least) its size.
+   */
+  .cache.rodata_dummy (NOLOAD):
+  {
+    _cache_rodata_dummy_start = ABSOLUTE(.);
+    . += SIZEOF(.flash.text);
+    . = ALIGN(CACHE_ALIGN);
+    _cache_rodata_dummy_end = ABSOLUTE(.);
+  } GROUP_LINK_IN(RODATA_REGION)
+
+  .flash.rodata_dummy (NOLOAD):
+  {
+    _flash_rodata_dummy_start = ABSOLUTE(.);
+    . += SIZEOF(.flash.text);
+    . = ALIGN(CACHE_ALIGN);
+    _flash_rodata_dummy_end = ABSOLUTE(.);
+  } GROUP_LINK_IN(ROMABLE_REGION)
+
+  _image_drom_start = LOADADDR(.flash.rodata);
+  _image_drom_size = LOADADDR(.flash.rodata_end) + SIZEOF(.flash.rodata_end) - _image_drom_start;
+  _image_drom_vaddr = ADDR(.flash.rodata);
+
+  .flash.rodata : ALIGN(4)
   {
     _rodata_start = ABSOLUTE(.);
 
@@ -296,28 +667,9 @@ SECTIONS
     #include <snippets-rodata.ld>
 
     . = ALIGN(4);
-    *(EXCLUDE_FILE (
-        *libarch__xtensa__core.a:*
-        *libkernel.a:fatal.*
-        *libkernel.a:init.*
-        *libzephyr.a:cbprintf_complete*
-        *libzephyr.a:log_core.*
-        *libzephyr.a:log_backend_uart.*
-        *libzephyr.a:log_output.*
-        *libzephyr.a:loader.*
-        *libdrivers__serial.a:uart_esp32.*) .rodata)
-
-    *(EXCLUDE_FILE (
-        *libarch__xtensa__core.a:*
-        *libkernel.a:fatal.*
-        *libkernel.a:init.*
-        *libzephyr.a:cbprintf_complete*
-        *libzephyr.a:log_core.*
-        *libzephyr.a:log_backend_uart.*
-        *libzephyr.a:log_output.*
-        *libzephyr.a:loader.*
-        *libdrivers__serial.a:uart_esp32.*) .rodata.*)
 
+    *(.rodata)
+    *(.rodata.*)
     . = ALIGN(4);
 
     *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
@@ -358,12 +710,9 @@ SECTIONS
     *(.rodata_wlog)
     *(.rodata_wlog*)
     _thread_local_end = ABSOLUTE(.);
-    _rodata_reserved_end = ABSOLUTE(.);
     . = ALIGN(4);
-  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
+  } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
 
-  /* Flash segments (rodata and text) should be mapped in virtual address space by providing VMA.
-   * Executing directly from LMA is not possible. */
   #include <zephyr/linker/cplusplus-rom.ld>
   #include <zephyr/linker/common-rom/common-rom-init.ld>
   #include <zephyr/linker/common-rom/common-rom-kernel-devices.ld>
@@ -377,58 +726,16 @@ SECTIONS
 
   /* Create an explicit section at the end of all the data that shall be mapped into drom.
    * This is used to calculate the size of the _image_drom_size variable */
-  .dram0.rodata_end : ALIGN(16)
+  .flash.rodata_end : ALIGN(16)
   {
     . = ALIGN(16);
+    _rodata_reserved_end = ABSOLUTE(.);
     _image_rodata_end = ABSOLUTE(.);
-  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
-
-  .dram0.end :
-  {
-    __data_end = ABSOLUTE(.);
-    _data_end = ABSOLUTE(.);
-  } GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
+  } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION)
 
-  .dram0.noinit (NOLOAD):
-  {
-    . = ALIGN(8);
-    *(.noinit)
-    *(.noinit.*)
-    . = ALIGN(8) ;
-  } GROUP_LINK_IN(RAMABLE_REGION)
+  /* --- END OF DROM --- */
 
-  /* Shared RAM */
-  .dram0.bss (NOLOAD) :
-  {
-    . = ALIGN (8);
-    _bss_start = ABSOLUTE(.); /* required by bluetooth library */
-    __bss_start = ABSOLUTE(.);
-
-    *(.dynsbss)
-    *(.sbss)
-    *(.sbss.*)
-    *(.gnu.linkonce.sb.*)
-    *(.scommon)
-    *(.sbss2)
-    *(.sbss2.*)
-    *(.gnu.linkonce.sb2.*)
-    *(.dynbss)
-    *(.bss)
-    *(.bss.*)
-    *(.share.mem)
-    *(.gnu.linkonce.b.*)
-    *(COMMON)
-    . = ALIGN (8);
-    __bss_end = ABSOLUTE(.);
-  } GROUP_LINK_IN(RAMABLE_REGION)
-
-  /* Provide total SRAM usage, including IRAM and DRAM */
-  _image_ram_start = _init_start - IRAM_DRAM_OFFSET;
-  #include <zephyr/linker/ram-end.ld>
-
-  ASSERT(((__bss_end - ORIGIN(dram0_1_seg)) <= LENGTH(dram0_1_seg)), "DRAM segment data does not fit.")
-
-  /* --- END OF DRAM --- */
+  /* --- XTENSA GLUE AND DEBUG BEGIN --- */
 
 #ifdef CONFIG_GEN_ISR_TABLES
 #include <zephyr/linker/intlist.ld>
@@ -471,5 +778,10 @@ SECTIONS
   }
 }
 
+  /* --- XTENSA GLUE AND DEBUG END --- */
+
 ASSERT(((_iram_end - ORIGIN(iram0_1_seg)) <= LENGTH(iram0_1_seg)),
           "IRAM0 segment data does not fit.")
+
+ASSERT(((_end - ORIGIN(dram0_1_seg)) <= LENGTH(dram0_1_seg)),
+          "DRAM segment data does not fit.")
diff --git a/soc/espressif/esp32s3/esp32s3-mp.c b/soc/espressif/esp32s3/esp32s3-mp.c
index a174db1e23c..fadbd922418 100644
--- a/soc/espressif/esp32s3/esp32s3-mp.c
+++ b/soc/espressif/esp32s3/esp32s3-mp.c
@@ -12,11 +12,15 @@
 #include <zephyr/drivers/interrupt_controller/intc_esp32.h>
 
 #include <soc.h>
+#include <esp_log.h>
 #include <esp_cpu.h>
 #include "esp_rom_uart.h"
 
 #include "esp_mcuboot_image.h"
 #include "esp_memory_utils.h"
+#include "hw_init.h"
+
+#define TAG "amp"
 
 /* AMP support */
 #ifdef CONFIG_SOC_ENABLE_APPCPU
@@ -47,7 +51,7 @@ static int load_segment(uint32_t src_addr, uint32_t src_len, uint32_t dst_addr)
 	const uint32_t *data = (const uint32_t *)sys_mmap(src_addr, src_len);
 
 	if (!data) {
-		ets_printf("%s: mmap failed", __func__);
+		ESP_EARLY_LOGE(TAG, "%s: mmap failed", __func__);
 		return -1;
 	}
 
@@ -64,12 +68,12 @@ static int load_segment(uint32_t src_addr, uint32_t src_len, uint32_t dst_addr)
 
 int IRAM_ATTR esp_appcpu_image_load(unsigned int hdr_offset, unsigned int *entry_addr)
 {
-	const uint32_t img_off = FIXED_PARTITION_OFFSET(slot0_appcpu_partition);
+	const uint32_t fa_offset = FIXED_PARTITION_OFFSET(slot0_appcpu_partition);
 	const uint32_t fa_size = FIXED_PARTITION_SIZE(slot0_appcpu_partition);
 	const uint8_t fa_id = FIXED_PARTITION_ID(slot0_appcpu_partition);
 
 	if (entry_addr == NULL) {
-		ets_printf("Can't return the entry address. Aborting!\n");
+		ESP_EARLY_LOGE(TAG, "Can't return the entry address. Aborting!");
 		abort();
 		return -1;
 	}
@@ -77,7 +81,7 @@ int IRAM_ATTR esp_appcpu_image_load(unsigned int hdr_offset, unsigned int *entry
 	uint32_t mcuboot_header[8] = {0};
 	esp_image_load_header_t image_header = {0};
 
-	const uint32_t *data = (const uint32_t *)sys_mmap(img_off, 0x40);
+	const uint32_t *data = (const uint32_t *)sys_mmap(fa_offset, 0x80);
 
 	memcpy((void *)&mcuboot_header, data, sizeof(mcuboot_header));
 	memcpy((void *)&image_header, data + (hdr_offset / sizeof(uint32_t)),
@@ -86,49 +90,69 @@ int IRAM_ATTR esp_appcpu_image_load(unsigned int hdr_offset, unsigned int *entry
 	sys_munmap(data);
 
 	if (image_header.header_magic == ESP_LOAD_HEADER_MAGIC) {
-		ets_printf("APPCPU image, area id: %d, offset: 0x%x, hdr.off: 0x%x, size: %d kB\n",
-			   fa_id, img_off, hdr_offset, fa_size / 1024);
+		ESP_EARLY_LOGI(TAG,
+			"APPCPU image, area id: %d, offset: 0x%x, hdr.off: 0x%x, size: %d kB",
+			fa_id, fa_offset, hdr_offset, fa_size / 1024);
 	} else if ((image_header.header_magic & 0xff) == 0xE9) {
-		ets_printf("ESP image format is not supported\n");
+		ESP_EARLY_LOGE(TAG, "ESP image format is not supported");
 		abort();
 	} else {
-		ets_printf("Unknown or empty image detected. Aborting!\n");
+		ESP_EARLY_LOGE(TAG, "Unknown or empty image detected. Aborting!");
 		abort();
 	}
 
 	if (!esp_ptr_in_iram((void *)image_header.iram_dest_addr) ||
 	    !esp_ptr_in_iram((void *)(image_header.iram_dest_addr + image_header.iram_size))) {
-		ets_printf("IRAM region in load header is not valid. Aborting");
+		ESP_EARLY_LOGE(TAG, "IRAM region in load header is not valid. Aborting");
 		abort();
 	}
 
 	if (!esp_ptr_in_dram((void *)image_header.dram_dest_addr) ||
 	    !esp_ptr_in_dram((void *)(image_header.dram_dest_addr + image_header.dram_size))) {
-		ets_printf("DRAM region in load header is not valid. Aborting");
+		ESP_EARLY_LOGE(TAG, "DRAM region in load header is not valid. Aborting");
 		abort();
 	}
 
 	if (!esp_ptr_in_iram((void *)image_header.entry_addr)) {
-		ets_printf("Application entry point (%xh) is not in IRAM. Aborting",
+		ESP_EARLY_LOGE(TAG, "Application entry point (%xh) is not in IRAM. Aborting",
 			   image_header.entry_addr);
 		abort();
 	}
 
-	ets_printf("IRAM segment: paddr=%08xh, vaddr=%08xh, size=%05xh (%6d) load\n",
-		   (img_off + image_header.iram_flash_offset), image_header.iram_dest_addr,
+	ESP_EARLY_LOGI(TAG, "IRAM segment: paddr=%08xh, vaddr=%08xh, size=%05xh (%6d) load",
+		   (fa_offset + image_header.iram_flash_offset), image_header.iram_dest_addr,
 		   image_header.iram_size, image_header.iram_size);
 
-	load_segment(img_off + image_header.iram_flash_offset, image_header.iram_size,
+	load_segment(fa_offset + image_header.iram_flash_offset, image_header.iram_size,
 		     image_header.iram_dest_addr);
 
-	ets_printf("DRAM segment: paddr=%08xh, vaddr=%08xh, size=%05xh (%6d) load\n",
-		   (img_off + image_header.dram_flash_offset), image_header.dram_dest_addr,
+	ESP_EARLY_LOGI(TAG, "DRAM segment: paddr=%08xh, vaddr=%08xh, size=%05xh (%6d) load",
+		   (fa_offset + image_header.dram_flash_offset), image_header.dram_dest_addr,
 		   image_header.dram_size, image_header.dram_size);
 
-	load_segment(img_off + image_header.dram_flash_offset, image_header.dram_size,
+	load_segment(fa_offset + image_header.dram_flash_offset, image_header.dram_size,
 		     image_header.dram_dest_addr);
 
-	ets_printf("Application start=%xh\n\n", image_header.entry_addr);
+	ESP_EARLY_LOGI(TAG, "IROM segment: paddr=%08xh, vaddr=%08xh, size=%05xh (%6d) map",
+		   (fa_offset + image_header.irom_flash_offset), image_header.irom_map_addr,
+		   image_header.irom_size, image_header.irom_size);
+
+	ESP_EARLY_LOGI(TAG, "DROM segment: paddr=%08xh, vaddr=%08xh, size=%05xh (%6d) map",
+		   (fa_offset + image_header.drom_flash_offset), image_header.drom_map_addr,
+		   image_header.drom_size, image_header.drom_size);
+
+	struct rom_segments rom = {
+		image_header.drom_map_addr,
+		image_header.drom_flash_offset + fa_offset,
+		image_header.drom_size,
+		image_header.irom_map_addr,
+		image_header.irom_flash_offset + fa_offset,
+		image_header.irom_size,
+	};
+
+	map_rom_segments(1, &rom);
+
+	ESP_EARLY_LOGI(TAG, "Application start=%xh\n\n", image_header.entry_addr);
 	esp_rom_uart_tx_wait_idle(0);
 
 	assert(entry_addr != NULL);
@@ -167,4 +191,10 @@ int esp_appcpu_init(void)
 
 	return 0;
 }
+
+#if !defined(CONFIG_MCUBOOT)
+extern int esp_appcpu_init(void);
+SYS_INIT(esp_appcpu_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+#endif
+
 #endif /* CONFIG_SOC_ENABLE_APPCPU */
diff --git a/soc/espressif/esp32s3/hw_init.c b/soc/espressif/esp32s3/hw_init.c
index 97ffb0ef826..a53f7753148 100644
--- a/soc/espressif/esp32s3/hw_init.c
+++ b/soc/espressif/esp32s3/hw_init.c
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -42,33 +42,17 @@ int hardware_init(void)
 #ifdef CONFIG_BOOTLOADER_REGION_PROTECTION_ENABLE
 	esp_cpu_configure_region_protection();
 #endif
-#if CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V
-	rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
-
-	if (cfg.enable == 1 && cfg.tieh == RTC_VDDSDIO_TIEH_1_8V) {
-		cfg.drefh = 3;
-		cfg.drefm = 3;
-		cfg.drefl = 3;
-		cfg.force = 1;
-		rtc_vddsdio_set_config(cfg);
-		esp_rom_delay_us(10);
-	}
-#endif /* CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V */
 
 	bootloader_clock_configure();
 
+#ifdef CONFIG_ESP_CONSOLE
 	/* initialize console, from now on, we can log */
 	esp_console_init();
 	print_banner();
-
-	spi_flash_init_chip_state();
-	err = esp_flash_init_default_chip();
-	if (err != 0) {
-		ESP_EARLY_LOGE(TAG, "Failed to init flash chip, error %d", err);
-		return err;
-	}
+#endif /* CONFIG_ESP_CONSOLE */
 
 	cache_hal_init();
+
 	mmu_hal_init();
 
 	flash_update_id();
@@ -95,6 +79,7 @@ int hardware_init(void)
 	}
 
 	check_wdt_reset();
+
 	config_wdt();
 
 	soc_random_enable();
diff --git a/soc/espressif/esp32s3/mcuboot.ld b/soc/espressif/esp32s3/mcuboot.ld
index f0fb717d5d9..7c5271ae50f 100644
--- a/soc/espressif/esp32s3/mcuboot.ld
+++ b/soc/espressif/esp32s3/mcuboot.ld
@@ -47,28 +47,17 @@ SECTIONS
     *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
 
     *libarch__xtensa__core.a:xtensa_asm2_util.*(.literal .text .literal.* .text.*)
-    *liblib__libc__common.a:abort.*(.literal .text .literal.* .text.*)
-    *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*)
     *libarch__common.a:dynamic_isr.*(.literal .text .literal.* .text.*)
     *libarch__common.a:sw_isr_common.*(.literal .text .literal.* .text.*)
 
     *libapp.a:flash_map_extended.*(.literal .text .literal.* .text.*)
-    *libzephyr.a:printk.*(.literal.printk .literal.vprintk .literal.char_out .text.printk .text.vprintk .text.char_out)
     *libzephyr.a:cbprintf_nano.*(.literal .text .literal.* .text.*)
     *libzephyr.a:cpu.*(.literal .text .literal.* .text.*)
     *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
     *libzephyr.a:flash_map.*(.literal .text .literal.* .text.*)
     *libzephyr.a:esp_rom_spiflash.*(.literal .text .literal.* .text.*)
-
-    *libzephyr.a:heap.*(.literal .text .literal.* .text.*)
-
-    *libkernel.a:kheap.*(.literal .text .literal.* .text.*)
-    *libkernel.a:mempool.*(.literal .text .literal.* .text.*)
     *libkernel.a:device.*(.literal .text .literal.* .text.*)
-    *libkernel.a:timeout.*(.literal .text .literal.* .text.*)
-
     *libzephyr.a:esp_loader.*(.literal .text .literal.* .text.*)
-    *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*)
 
     *(.literal.esp_intr_disable .literal.esp_intr_disable.* .text.esp_intr_disable .text.esp_intr_disable.*)
     *(.literal.default_intr_handler .text.default_intr_handler .iram1.*.default_intr_handler)
diff --git a/soc/espressif/esp32s3/memory.h b/soc/espressif/esp32s3/memory.h
index e435abe95a7..98885425053 100644
--- a/soc/espressif/esp32s3/memory.h
+++ b/soc/espressif/esp32s3/memory.h
@@ -78,31 +78,37 @@
 #define USER_IRAM_END (USER_DRAM_END + IRAM_DRAM_OFFSET)
 
 /* AMP */
-#if defined(CONFIG_SOC_ENABLE_APPCPU) || defined(CONFIG_SOC_ESP32S3_APPCPU)
+#if (defined(CONFIG_SOC_ENABLE_APPCPU) || defined(CONFIG_SOC_ESP32S3_APPCPU))
 #define APPCPU_IRAM_SIZE CONFIG_ESP_APPCPU_IRAM_SIZE
 #define APPCPU_DRAM_SIZE CONFIG_ESP_APPCPU_DRAM_SIZE
 #define AMP_COMM_SIZE DT_REG_SIZE(DT_NODELABEL(ipmmem0)) + DT_REG_SIZE(DT_NODELABEL(shm0)) +       \
 		      DT_REG_SIZE(DT_NODELABEL(ipm0)) + DT_REG_SIZE(DT_NODELABEL(mbox0))
 #undef DRAM_RESERVED_START
 #define DRAM_RESERVED_START 0x3fce5000
+#define APPCPU_IROM_SIZE CONFIG_ESP_APPCPU_IROM_SIZE
+#define APPCPU_DROM_SIZE CONFIG_ESP_APPCPU_DROM_SIZE
 #else
 #define APPCPU_IRAM_SIZE 0
 #define APPCPU_DRAM_SIZE 0
 #define AMP_COMM_SIZE    0
+#define APPCPU_IROM_SIZE 0
+#define APPCPU_DROM_SIZE 0
 #endif
 
 #define APPCPU_SRAM_SIZE (APPCPU_IRAM_SIZE + APPCPU_DRAM_SIZE)
+#define APPCPU_ROM_SIZE (APPCPU_IROM_SIZE + APPCPU_DROM_SIZE)
 
-/* Flash */
+/* Cached memory */
+#define ICACHE0_START DT_REG_ADDR(DT_NODELABEL(icache0))
+#define ICACHE0_SIZE  DT_REG_SIZE(DT_NODELABEL(icache0))
+#define DCACHE0_START DT_REG_ADDR(DT_NODELABEL(dcache0))
+#define DCACHE0_SIZE  DT_REG_SIZE(DT_NODELABEL(dcache0))
+
+#define CACHE_ALIGN   CONFIG_MMU_PAGE_SIZE
+
+/* Flash memory */
 #ifdef CONFIG_FLASH_SIZE
 #define FLASH_SIZE         CONFIG_FLASH_SIZE
 #else
 #define FLASH_SIZE         0x800000
 #endif
-
-/* Cached memory */
-#define CACHE_ALIGN        CONFIG_MMU_PAGE_SIZE
-#define IROM_SEG_ORG       0x42000000
-#define IROM_SEG_LEN       FLASH_SIZE
-#define DROM_SEG_ORG       0x3c000000
-#define DROM_SEG_LEN       FLASH_SIZE
diff --git a/soc/espressif/esp32s3/soc.c b/soc/espressif/esp32s3/soc.c
index 763ba341940..4e7f9bffc44 100644
--- a/soc/espressif/esp32s3/soc.c
+++ b/soc/espressif/esp32s3/soc.c
@@ -1,66 +1,23 @@
 /*
  * Copyright (c) 2017 Intel Corporation
+ * Copyright (c) 2025 Espressif Systems (Shanghai) CO LTD.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/* Include esp-idf headers first to avoid redefining BIT() macro */
 #include <soc.h>
-#include <soc/rtc_cntl_reg.h>
-#include <soc/timer_group_reg.h>
-#include <soc/ext_mem_defs.h>
-#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
-#include <xtensa/config/core-isa.h>
-#include <xtensa/corebits.h>
-#include <esp_private/spi_flash_os.h>
-#include <esp_private/esp_mmu_map_private.h>
-#include <esp_private/mspi_timing_tuning.h>
-#include <esp_flash_internal.h>
+#include <soc_init.h>
+#include <flash_init.h>
 #include <esp_private/cache_utils.h>
-#include <sdkconfig.h>
-
-#if CONFIG_ESP_SPIRAM
-#include "psram.h"
-#endif
-
-#include <zephyr/kernel_structs.h>
-#include <zephyr/toolchain.h>
-#include <zephyr/types.h>
-#include <zephyr/linker/linker-defs.h>
-#include <kernel_internal.h>
-#include <zephyr/sys/util.h>
-
 #include <esp_private/system_internal.h>
-#include <esp32s3/rom/cache.h>
-#include <esp32s3/rom/rtc.h>
-#include <soc/syscon_reg.h>
-#include <hal/soc_hal.h>
-#include <hal/wdt_hal.h>
-#include <hal/cpu_hal.h>
-#include <esp_cpu.h>
-#include <soc/gpio_periph.h>
-#include <esp_err.h>
 #include <esp_timer.h>
-#include <esp_clk_internal.h>
-#include <esp_app_format.h>
-
+#include <psram.h>
+#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
 #include <zephyr/sys/printk.h>
-#include "esp_log.h"
-
-#include <zephyr/drivers/flash.h>
-#include <zephyr/storage/flash_map.h>
-
-#define TAG "boot.esp32s3"
 
 extern void z_prep_c(void);
 extern void esp_reset_reason_init(void);
-extern int esp_appcpu_init(void);
 
-#ifndef CONFIG_MCUBOOT
-/*
- * This function is a container for SoC patches
- * that needs to be applied during the startup.
- */
 static void IRAM_ATTR esp_errata(void)
 {
 	/* Handle the clock gating fix */
@@ -77,32 +34,9 @@ static void IRAM_ATTR esp_errata(void)
 	Cache_Occupy_Addr(SOC_DROM_LOW, 0x4000);
 #endif
 }
-#endif /* CONFIG_MCUBOOT */
 
-/*
- * This is written in C rather than assembly since, during the port bring up,
- * Zephyr is being booted by the Espressif bootloader.  With it, the C stack
- * is already set up.
- */
-void IRAM_ATTR __esp_platform_start(void)
+void IRAM_ATTR __esp_platform_app_start(void)
 {
-	extern uint32_t _init_start;
-
-	/* Move the exception vector table to IRAM. */
-	__asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start));
-
-	z_bss_zero();
-
-	/* Disable normal interrupts. */
-	__asm__ __volatile__("wsr %0, PS" : : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE));
-
-	/* Initialize the architecture CPU pointer.  Some of the
-	 * initialization code wants a valid _current before
-	 * arch_kernel_init() is invoked.
-	 */
-	__asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0]));
-
-#ifndef CONFIG_MCUBOOT
 	/* Configure the mode of instruction cache : cache size, cache line size. */
 	esp_config_instruction_cache_mode();
 
@@ -114,38 +48,15 @@ void IRAM_ATTR __esp_platform_start(void)
 	/* Apply SoC patches */
 	esp_errata();
 
-	/* ESP-IDF/MCUboot 2nd stage bootloader enables RTC WDT to check on startup sequence
-	 * related issues in application. Hence disable that as we are about to start
-	 * Zephyr environment.
-	 */
-	wdt_hal_context_t rtc_wdt_ctx = {.inst = WDT_RWDT, .rwdt_dev = &RTCCNTL};
-
-	wdt_hal_write_protect_disable(&rtc_wdt_ctx);
-	wdt_hal_disable(&rtc_wdt_ctx);
-	wdt_hal_write_protect_enable(&rtc_wdt_ctx);
-
 	esp_reset_reason_init();
 
 	esp_timer_early_init();
 
-	esp_mspi_pin_init();
-
-	esp_flash_app_init();
-
-	mspi_timing_flash_tuning();
-
-	esp_mmu_map_init();
+	esp_flash_config();
 
 #if CONFIG_ESP_SPIRAM
 	esp_init_psram();
-#endif /* CONFIG_ESP_SPIRAM */
-
-#endif /* !CONFIG_MCUBOOT */
 
-	esp_intr_initialize();
-
-#if CONFIG_ESP_SPIRAM
-	/* Init Shared Multi Heap for PSRAM */
 	int err = esp_psram_smh_init();
 
 	if (err) {
@@ -159,6 +70,14 @@ void IRAM_ATTR __esp_platform_start(void)
 	CODE_UNREACHABLE;
 }
 
+void IRAM_ATTR __esp_platform_mcuboot_start(void)
+{
+	/* Start Zephyr */
+	z_prep_c();
+
+	CODE_UNREACHABLE;
+}
+
 /* Boot-time static default printk handler, possibly to be overridden later. */
 int IRAM_ATTR arch_printk_char_out(int c)
 {
@@ -171,10 +90,5 @@ int IRAM_ATTR arch_printk_char_out(int c)
 
 void sys_arch_reboot(int type)
 {
-	esp_restart_noos();
+	esp_restart();
 }
-
-#if defined(CONFIG_SOC_ENABLE_APPCPU) && !defined(CONFIG_MCUBOOT)
-extern int esp_appcpu_init(void);
-SYS_INIT(esp_appcpu_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
-#endif
diff --git a/soc/espressif/esp32s3/soc.h b/soc/espressif/esp32s3/soc.h
index 1d6d2204cf4..f74376cc5ba 100644
--- a/soc/espressif/esp32s3/soc.h
+++ b/soc/espressif/esp32s3/soc.h
@@ -25,7 +25,8 @@
 #include <xtensa/core-macros.h>
 #include <esp_private/esp_clk.h>
 
-void __esp_platform_start(void);
+void __esp_platform_mcuboot_start(void);
+void __esp_platform_app_start(void);
 
 static inline void esp32_set_mask32(uint32_t v, uint32_t mem_addr)
 {
diff --git a/soc/espressif/esp32s3/soc_appcpu.c b/soc/espressif/esp32s3/soc_appcpu.c
index a03304c8751..517b1e187d7 100644
--- a/soc/espressif/esp32s3/soc_appcpu.c
+++ b/soc/espressif/esp32s3/soc_appcpu.c
@@ -72,8 +72,6 @@ void IRAM_ATTR __appcpu_start(void)
 
 	core_intr_matrix_clear();
 
-	esp_intr_initialize();
-
 	/* Start Zephyr */
 	z_prep_c();
 
@@ -89,5 +87,5 @@ int IRAM_ATTR arch_printk_char_out(int c)
 
 void sys_arch_reboot(int type)
 {
-	esp_restart_noos();
+	esp_restart();
 }
diff --git a/soc/espressif/soc.yml b/soc/espressif/soc.yml
index 1ec21c88aae..cd20df8a60b 100644
--- a/soc/espressif/soc.yml
+++ b/soc/espressif/soc.yml
@@ -25,3 +25,6 @@ family:
   - name: esp32c6
     socs:
     - name: esp32c6
+      cpuclusters:
+      - name: hpcore
+      - name: lpcore
diff --git a/soc/gd/gd32/gd32vf103/CMakeLists.txt b/soc/gd/gd32/gd32vf103/CMakeLists.txt
index 6778c0a4f1b..649c118de67 100644
--- a/soc/gd/gd32/gd32vf103/CMakeLists.txt
+++ b/soc/gd/gd32/gd32vf103/CMakeLists.txt
@@ -3,6 +3,7 @@
 
 zephyr_sources(entry.S)
 zephyr_sources(soc.c)
+zephyr_sources(soc_irq.S)
 
 zephyr_include_directories(.)
 
diff --git a/soc/gd/gd32/gd32vf103/Kconfig b/soc/gd/gd32/gd32vf103/Kconfig
index b14bddbd46a..99f60cd6ab8 100644
--- a/soc/gd/gd32/gd32vf103/Kconfig
+++ b/soc/gd/gd32/gd32vf103/Kconfig
@@ -14,6 +14,7 @@ config SOC_SERIES_GD32VF103
 	select RISCV_ISA_EXT_ZIFENCEI
 	select RISCV_HAS_CLIC
 	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
+	select RISCV_SOC_CONTEXT_SAVE
 	select ATOMIC_OPERATIONS_C
 	select INCLUDE_RESET_VECTOR
 	select GD32_HAS_AFIO_PINMUX
diff --git a/soc/gd/gd32/gd32vf103/soc_context.h b/soc/gd/gd32/gd32vf103/soc_context.h
new file mode 100644
index 00000000000..51a082aa0bf
--- /dev/null
+++ b/soc/gd/gd32/gd32vf103/soc_context.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Andes Technology Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef SOC_RISCV_GD32_GD32VF103_SOC_CONTEXT_H
+#define SOC_RISCV_GD32_GD32VF103_SOC_CONTEXT_H
+
+#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
+
+	#define SOC_ESF_MEMBERS
+
+	#define SOC_ESF_INIT
+
+#endif  /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
+
+#endif  /* SOC_RISCV_GD32_GD32VF103_SOC_CONTEXT_H */
diff --git a/soc/gd/gd32/gd32vf103/soc_irq.S b/soc/gd/gd32/gd32vf103/soc_irq.S
new file mode 100644
index 00000000000..fe0248dad16
--- /dev/null
+++ b/soc/gd/gd32/gd32vf103/soc_irq.S
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2024 Andes Technology Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/offsets.h>
+#include <zephyr/toolchain.h>
+#include <zephyr/arch/riscv/irq.h>
+
+/* Exports */
+#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
+GTEXT(__soc_save_context)
+GTEXT(__soc_restore_context)
+#endif
+
+#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
+
+SECTION_FUNC(exception.other, __soc_save_context)
+
+	ret
+
+SECTION_FUNC(exception.other, __soc_restore_context)
+
+	/*
+	 * For Nuclei ECLIC, the interrupt level (mintstatus.MIL) is restored
+	 * from the previous interrupt level (mcause.MPIL) only if
+	 * mcause.interrupt is set when executing MRET.
+	 * Always set the next context's mcause.interrupt to ensure the
+	 * interrupt level is restored correctly after MRET.
+	 */
+	addi a0, a0, -__struct_arch_esf_soc_context_OFFSET
+	lw t0, __struct_arch_esf_mcause_OFFSET(a0)
+	li t1, 1 << RISCV_MCAUSE_IRQ_POS
+	or t0, t0, t1
+	sw t0, __struct_arch_esf_mcause_OFFSET(a0)
+
+	ret
+
+#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
diff --git a/soc/gd/gd32/gd32vf103/soc_offsets.h b/soc/gd/gd32/gd32vf103/soc_offsets.h
new file mode 100644
index 00000000000..7322e91b81d
--- /dev/null
+++ b/soc/gd/gd32/gd32vf103/soc_offsets.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 Andes Technology Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef SOC_RISCV_GD32_GD32VF103_SOC_OFFSETS_H_
+#define SOC_RISCV_GD32_GD32VF103_SOC_OFFSETS_H_
+
+#ifdef CONFIG_RISCV_SOC_OFFSETS
+
+	#define GEN_SOC_OFFSET_SYMS()
+
+#endif  /* CONFIG_RISCV_SOC_OFFSETS */
+
+#endif  /* SOC_RISCV_GD32_GD32VF103_SOC_OFFSETS_H_*/
diff --git a/soc/infineon/cat1a/Kconfig b/soc/infineon/cat1a/Kconfig
index c69e8f5e0bd..c257f5195e9 100644
--- a/soc/infineon/cat1a/Kconfig
+++ b/soc/infineon/cat1a/Kconfig
@@ -12,11 +12,13 @@ config SOC_FAMILY_PSOC6
 	select DYNAMIC_INTERRUPTS
 	select CPU_HAS_FPU
 	select SOC_FAMILY_INFINEON_CAT1
+	select BUILD_OUTPUT_HEX
 
 config SOC_FAMILY_PSOC6_LEGACY
 	select ARM
 	select HAS_CYPRESS_DRIVERS
 	select CPU_CORTEX_M_HAS_SYSTICK
+	select BUILD_OUTPUT_HEX
 	select CPU_HAS_ARM_MPU
 
 config SOC_FAMILY_PSOC6_LEGACY_M4
diff --git a/soc/infineon/cat1a/psoc6_01/Kconfig.defconfig b/soc/infineon/cat1a/psoc6_01/Kconfig.defconfig
index acfefd580e2..030ff86c57c 100644
--- a/soc/infineon/cat1a/psoc6_01/Kconfig.defconfig
+++ b/soc/infineon/cat1a/psoc6_01/Kconfig.defconfig
@@ -13,6 +13,12 @@ config NUM_IRQS
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 100000000
 
+config MAIN_STACK_SIZE
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 1024 if PM
+
 # add additional die specific params
 
 endif # SOC_DIE_PSOC6_01
diff --git a/soc/infineon/cat1a/psoc6_02/Kconfig.defconfig b/soc/infineon/cat1a/psoc6_02/Kconfig.defconfig
index e88081ea213..e5620c9ef95 100644
--- a/soc/infineon/cat1a/psoc6_02/Kconfig.defconfig
+++ b/soc/infineon/cat1a/psoc6_02/Kconfig.defconfig
@@ -16,6 +16,12 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config BUILD_OUTPUT_HEX
 	default y
 
+config MAIN_STACK_SIZE
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 1024 if PM
+
 # add additional die specific params
 
 endif # SOC_DIE_PSOC6_02
diff --git a/soc/infineon/cat1a/psoc6_03/Kconfig.defconfig b/soc/infineon/cat1a/psoc6_03/Kconfig.defconfig
index 1516df04b33..8ea4139ef3d 100644
--- a/soc/infineon/cat1a/psoc6_03/Kconfig.defconfig
+++ b/soc/infineon/cat1a/psoc6_03/Kconfig.defconfig
@@ -13,6 +13,12 @@ config NUM_IRQS
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 100000000
 
+config MAIN_STACK_SIZE
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 1024 if PM
+
 # add additional die specific params
 
 endif # SOC_DIE_PSOC6_03
diff --git a/soc/infineon/cat1a/psoc6_04/Kconfig.defconfig b/soc/infineon/cat1a/psoc6_04/Kconfig.defconfig
index 3ebc2882b79..7c05e248055 100644
--- a/soc/infineon/cat1a/psoc6_04/Kconfig.defconfig
+++ b/soc/infineon/cat1a/psoc6_04/Kconfig.defconfig
@@ -13,6 +13,12 @@ config NUM_IRQS
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 100000000
 
+config MAIN_STACK_SIZE
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 1024 if PM
+
 # add additional die specific params
 
 endif # SOC_DIE_PSOC6_04
diff --git a/soc/infineon/cat1b/cyw20829/CMakeLists.txt b/soc/infineon/cat1b/cyw20829/CMakeLists.txt
index 464a3f44a30..5bbff012c05 100644
--- a/soc/infineon/cat1b/cyw20829/CMakeLists.txt
+++ b/soc/infineon/cat1b/cyw20829/CMakeLists.txt
@@ -3,6 +3,7 @@
 
 zephyr_sources(soc.c)
 zephyr_sources(app_header.c)
+zephyr_sources(mpu_regions.c)
 zephyr_include_directories(.)
 
 zephyr_sources_ifdef(CONFIG_PM power.c)
diff --git a/soc/infineon/cat1b/cyw20829/Kconfig b/soc/infineon/cat1b/cyw20829/Kconfig
index 85ec200be8e..f4e960d65c4 100644
--- a/soc/infineon/cat1b/cyw20829/Kconfig
+++ b/soc/infineon/cat1b/cyw20829/Kconfig
@@ -8,8 +8,11 @@
 config SOC_SERIES_CYW20829
 	select ARM
 	select CPU_HAS_ARM_MPU
+	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
 	select CPU_CORTEX_M33
-	select CPU_HAS_FPU
 	select DYNAMIC_INTERRUPTS
 	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
 	select HAS_PM
+	select BUILD_OUTPUT_HEX
+	select BUILD_OUTPUT_BIN
+	select SOC_EARLY_INIT_HOOK
diff --git a/soc/infineon/cat1b/cyw20829/Kconfig.defconfig b/soc/infineon/cat1b/cyw20829/Kconfig.defconfig
index 78b2cdd8956..b28a10847ca 100644
--- a/soc/infineon/cat1b/cyw20829/Kconfig.defconfig
+++ b/soc/infineon/cat1b/cyw20829/Kconfig.defconfig
@@ -22,6 +22,12 @@ config BUILD_OUTPUT_ADJUST_LMA
 	depends on XIP
 	default "0x60000000 - $(dt_node_reg_addr_hex,$(dt_nodelabel_path,flash0))"
 
+config MAIN_STACK_SIZE
+	default 2048
+
+config IDLE_STACK_SIZE
+	default 1024 if PM
+
 # add additional die specific params
 
 endif # SOC_DIE_CYW20829
diff --git a/soc/infineon/cat1b/cyw20829/mpu_regions.c b/soc/infineon/cat1b/cyw20829/mpu_regions.c
new file mode 100644
index 00000000000..e0bbc719847
--- /dev/null
+++ b/soc/infineon/cat1b/cyw20829/mpu_regions.c
@@ -0,0 +1,34 @@
+/* Copyright 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
+
+#define BOOTSTRAP_RAM_BASE_ADDRESS DT_REG_ADDR(DT_NODELABEL(sram_bootstrap))
+#define BOOTSTRAP_RAM_SIZE         DT_REG_SIZE(DT_NODELABEL(sram_bootstrap))
+
+#define REGION_BOOTSTRAP_RAM_ATTR(base, size)                                                 \
+	{                                                                                       \
+		.rbar = FULL_ACCESS_Msk | NON_SHAREABLE_Msk,                                     \
+		.mair_idx = MPU_MAIR_INDEX_SRAM,                                                 \
+		.r_limit = REGION_LIMIT_ADDR(base, size),                                        \
+	}
+
+static const struct arm_mpu_region mpu_regions[] = {
+	MPU_REGION_ENTRY("FLASH", CONFIG_FLASH_BASE_ADDRESS,
+			 REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, CONFIG_FLASH_SIZE * 1024)),
+
+	MPU_REGION_ENTRY("SRAM", CONFIG_SRAM_BASE_ADDRESS,
+			 REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, CONFIG_SRAM_SIZE * 1024)),
+
+	MPU_REGION_ENTRY("BOOTSTRAP_RAM", BOOTSTRAP_RAM_BASE_ADDRESS,
+			 REGION_BOOTSTRAP_RAM_ATTR(BOOTSTRAP_RAM_BASE_ADDRESS, BOOTSTRAP_RAM_SIZE)),
+};
+
+const struct arm_mpu_config mpu_config = {
+	.num_regions = ARRAY_SIZE(mpu_regions),
+	.mpu_regions = mpu_regions,
+};
diff --git a/soc/infineon/cat1b/cyw20829/soc.c b/soc/infineon/cat1b/cyw20829/soc.c
index 3a55e035c79..2ec0cd8ab10 100644
--- a/soc/infineon/cat1b/cyw20829/soc.c
+++ b/soc/infineon/cat1b/cyw20829/soc.c
@@ -85,22 +85,16 @@ void disable_mpu_rasr_xn(void)
 }
 #endif /* CONFIG_ARM_MPU */
 
-static int init_cycfg_platform_wrapper(void)
+void soc_early_init_hook(void)
 {
 #ifdef CONFIG_ARM_MPU
 	disable_mpu_rasr_xn();
-#endif	/* CONFIG_ARM_MPU */
+#endif /* CONFIG_ARM_MPU */
 
 	/* Initializes the system */
 	SystemInit();
-	return 0;
-}
-
-SYS_INIT(init_cycfg_platform_wrapper, PRE_KERNEL_1, 0);
 
 #ifdef CONFIG_PM
-void soc_early_init_hook(void)
-{
 	ifx_pm_init();
-}
 #endif
+}
diff --git a/soc/intel/intel_adsp/ace/CMakeLists.txt b/soc/intel/intel_adsp/ace/CMakeLists.txt
index 519275d9047..9aebd85c43c 100644
--- a/soc/intel/intel_adsp/ace/CMakeLists.txt
+++ b/soc/intel/intel_adsp/ace/CMakeLists.txt
@@ -18,6 +18,10 @@ zephyr_include_directories(include)
 zephyr_include_directories(include/${CONFIG_SOC})
 zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget.c)
 zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_COMM_WIDGET comm_widget_messages.c)
+zephyr_library_sources_ifdef(
+  CONFIG_SOC_SERIES_INTEL_ADSP_ACE_CUSTOM_MORE_SPIN_RELAX_NOPS
+  spin_relax.c
+)
 
 if (CONFIG_XTENSA_MMU)
   zephyr_library_sources_ifdef(CONFIG_SOC_INTEL_ACE30 mmu_ace30.c)
diff --git a/soc/intel/intel_adsp/ace/Kconfig b/soc/intel/intel_adsp/ace/Kconfig
index e38ebdeb9c5..f4c7903e7a0 100644
--- a/soc/intel/intel_adsp/ace/Kconfig
+++ b/soc/intel/intel_adsp/ace/Kconfig
@@ -31,3 +31,24 @@ config SRAM_RETENTION_MODE
 	  When this option is enabled, the SRAM retention mode will be
 	  activated during the firmware boot-up process. If disabled,
 	  the retention mode will not be activated.
+
+config SOC_SERIES_INTEL_ADSP_ACE_CUSTOM_MORE_SPIN_RELAX_NOPS
+	bool "Use Intel Audio DSP specific arch_spin_relax() with more NOPs"
+	depends on !XTENSA_MORE_SPIN_RELAX_NOPS
+	default y if SMP && MP_MAX_NUM_CPUS > 1
+	help
+	  Add some NOPs after failure to lock a spinlock. This gives
+	  the bus extra time to synchronize the RCW transaction
+	  among CPUs.
+
+config SOC_SERIES_INTEL_ADSP_ACE_NUM_SPIN_RELAX_NOPS
+	int "Number of NOPs to be used in Intel Audio DSP specific arch_spin_relax()"
+	depends on SOC_SERIES_INTEL_ADSP_ACE_CUSTOM_MORE_SPIN_RELAX_NOPS
+	default 32 if MP_MAX_NUM_CPUS = 1
+	default 64 if MP_MAX_NUM_CPUS = 2
+	default 96 if MP_MAX_NUM_CPUS = 3
+	default 128 if MP_MAX_NUM_CPUS = 4
+	default 160 if MP_MAX_NUM_CPUS = 5
+	help
+	  Specify the number of NOPs in Intel Audio DSP specific
+	  arch_spin_relax().
diff --git a/soc/intel/intel_adsp/ace/Kconfig.defconfig.series b/soc/intel/intel_adsp/ace/Kconfig.defconfig.series
index 1c4ea73ae0d..36b512d27cb 100644
--- a/soc/intel/intel_adsp/ace/Kconfig.defconfig.series
+++ b/soc/intel/intel_adsp/ace/Kconfig.defconfig.series
@@ -23,7 +23,7 @@ config MULTI_LEVEL_INTERRUPTS
 	default y
 
 config MAX_IRQ_PER_AGGREGATOR
-	default 29
+	default 30
 
 config NUM_2ND_LEVEL_AGGREGATORS
 	default 1
@@ -57,20 +57,6 @@ config LOG_BACKEND_ADSP
 
 endif # LOG
 
-config XTENSA_MORE_SPIN_RELAX_NOPS
-	default y if SMP && MP_MAX_NUM_CPUS > 1
-
-if XTENSA_MORE_SPIN_RELAX_NOPS
-
-config XTENSA_NUM_SPIN_RELAX_NOPS
-	default 32 if MP_MAX_NUM_CPUS = 1
-	default 64 if MP_MAX_NUM_CPUS = 2
-	default 96 if MP_MAX_NUM_CPUS = 3
-	default 128 if MP_MAX_NUM_CPUS = 4
-	default 160 if MP_MAX_NUM_CPUS = 5
-
-endif # XTENSA_MORE_SPIN_RELAX_NOPS
-
 if KERNEL_VM_SUPPORT
 
 config KERNEL_VM_SIZE
diff --git a/soc/intel/intel_adsp/ace/ace-link.ld b/soc/intel/intel_adsp/ace/ace-link.ld
index 2a220746b5d..aa92a212ea0 100644
--- a/soc/intel/intel_adsp/ace/ace-link.ld
+++ b/soc/intel/intel_adsp/ace/ace-link.ld
@@ -175,11 +175,14 @@ SECTIONS {
 
   /* Cold code in IMR memory */
   .cold : ALIGN(4096) {
+    __cold_start = .;
     *(.cold .cold.* )
+    __cold_end = .;
   } >imr
 
   /* Cold data. */
   .coldrodata : ALIGN(4096) {
+    __coldrodata_start = .;
     *(.coldrodata .coldrodata.*)
     _imr_end = .;
   } >imr
@@ -294,6 +297,8 @@ SECTIONS {
 
     *libarch__xtensa__core.a:userspace.S.obj(.literal.xtensa_do_syscall)
     *libarch__xtensa__core.a:userspace.S.obj(.text.xtensa_do_syscall)
+    *libarch__xtensa__core.a:ptables.c.obj(.literal.xtensa_swap_update_page_tables)
+    *libarch__xtensa__core.a:ptables.c.obj(.text.xtensa_swap_update_page_tables)
 
 #ifdef CONFIG_XTENSA_SYSCALL_USE_HELPER
     *libarch__xtensa__core.a:syscall_helper.c.obj(.text.xtensa_syscall_helper*)
@@ -500,6 +505,24 @@ SECTIONS {
   .bss SEGSTART_UNCACHED (NOLOAD) :
   {
     _bss_start = .;
+
+#if defined(CONFIG_ZTEST) && defined(CONFIG_SIMULATOR_XTENSA)
+    /* For some weird unknown reasons, the simulator really do not
+     * like these cpuhold_* variables to be tightly packed together.
+     * This results in cpuhold_spawned not being updated, and we
+     * will be stuck in the while loop for it to be set.
+     * Workaround by explicitly aligning these variables.
+     */
+    . = ALIGN(16);
+    *:ztest.c.obj(.bss.cpuhold_sem)
+    . = ALIGN(16);
+    *:ztest.c.obj(.bss.cpuhold_active)
+    . = ALIGN(16);
+    *:ztest.c.obj(.bss.cpuhold_spawned)
+    . = ALIGN(16);
+    *:ztest.c.obj(.bss.cpuhold_pool_items)
+#endif /* CONFIG_ZTEST && CONFIG_SIMULATOR_XTENSA */
+
     *(.dynsbss)
     *(.sbss)
     *(.sbss.*)
diff --git a/soc/intel/intel_adsp/ace/include/ace30/adsp_interrupt.h b/soc/intel/intel_adsp/ace/include/ace30/adsp_interrupt.h
index b34a3fc9f1c..9a6848b9af4 100644
--- a/soc/intel/intel_adsp/ace/include/ace30/adsp_interrupt.h
+++ b/soc/intel/intel_adsp/ace/include/ace30/adsp_interrupt.h
@@ -36,6 +36,7 @@
 #define ACE_INTL_DTF      26
 #define ACE_INTL_FLV      27
 #define ACE_INTL_DPDMA    28
+#define ACE_INTL_MIC_PRIV 29
 
 /* Device interrupt control for the low priority interrupts.  It
  * provides per-core masking and status checking: ACE_DINT is an array
diff --git a/soc/intel/intel_adsp/ace/include/adsp_memory.h b/soc/intel/intel_adsp/ace/include/adsp_memory.h
index 1a643b0c42d..b4271da1368 100644
--- a/soc/intel/intel_adsp/ace/include/adsp_memory.h
+++ b/soc/intel/intel_adsp/ace/include/adsp_memory.h
@@ -68,6 +68,13 @@
 #define IMR_BOOT_LDR_STACK_BASE		(IMR_BOOT_LDR_BSS_BASE + IMR_BOOT_LDR_BSS_SIZE)
 #define IMR_BOOT_LDR_STACK_SIZE		0x1000
 
+/* ROM_EXT sections, used only for MMU mapping */
+#define IMR_ROM_EXT_OFFSET		0xB000
+#define IMR_ROM_EXT_CODE_BASE		(L3_MEM_BASE_ADDR + IMR_ROM_EXT_OFFSET)
+#define IMR_ROM_EXT_CODE_SIZE		0xD000
+#define IMR_ROM_EXT_DATABSS_BASE	(IMR_ROM_EXT_CODE_BASE + IMR_ROM_EXT_CODE_SIZE)
+#define IMR_ROM_EXT_DATABSS_SIZE	0x18000
+
 /* position of L3 heap, size of L3 heap - till end of the L3 memory */
 /* !!! FIXME: L3 heap base MUST be automatically calculated. !!! */
 #define IMR_L3_HEAP_BASE		(IMR_BOOT_LDR_STACK_BASE + IMR_BOOT_LDR_STACK_SIZE)
diff --git a/soc/intel/intel_adsp/ace/mmu_ace30.c b/soc/intel/intel_adsp/ace/mmu_ace30.c
index a59b231fbe3..ed233ddf862 100644
--- a/soc/intel/intel_adsp/ace/mmu_ace30.c
+++ b/soc/intel/intel_adsp/ace/mmu_ace30.c
@@ -19,6 +19,10 @@ extern char __common_rom_region_start[];
 extern char __common_rom_region_end[];
 extern char __common_ram_region_start[];
 extern char __common_ram_region_end[];
+extern char __cold_start[];
+extern char __cold_end[];
+extern char __coldrodata_start[];
+
 
 const struct xtensa_mmu_range xtensa_soc_mmu_ranges[] = {
 	{
@@ -71,6 +75,18 @@ const struct xtensa_mmu_range xtensa_soc_mmu_ranges[] = {
 		.name = "win3",
 	},
 	/* Map IMR */
+	{
+		.start = (uint32_t)IMR_ROM_EXT_CODE_BASE,
+		.end   = (uint32_t)(IMR_ROM_EXT_CODE_BASE + IMR_ROM_EXT_CODE_SIZE),
+		.attrs = XTENSA_MMU_PERM_X,
+		.name = "IMR_rom_ext_code",
+	},
+	{
+		.start = (uint32_t)IMR_ROM_EXT_DATABSS_BASE,
+		.end   = (uint32_t)(IMR_ROM_EXT_DATABSS_BASE + IMR_ROM_EXT_DATABSS_SIZE),
+		.attrs = XTENSA_MMU_PERM_W,
+		.name = "IMR_rom_ext_data_bss",
+	},
 	{
 		.start = (uint32_t)(IMR_BOOT_LDR_MANIFEST_BASE - IMR_BOOT_LDR_MANIFEST_SIZE),
 		.end   = (uint32_t)IMR_BOOT_LDR_MANIFEST_BASE,
@@ -106,6 +122,17 @@ const struct xtensa_mmu_range xtensa_soc_mmu_ranges[] = {
 		.attrs = XTENSA_MMU_PERM_W | XTENSA_MMU_CACHED_WB,
 		.name = "imr layout",
 	},
+	{
+		.start = (uint32_t)__cold_start,
+		.end   = (uint32_t)__cold_end,
+		.attrs = XTENSA_MMU_PERM_X,
+		.name = "imr cold",
+	},
+	{
+		.start = (uint32_t)__coldrodata_start,
+		.end   = (uint32_t)_imr_end,
+		.name = "imr coldrodata",
+	},
 	{
 		.start = (uint32_t)IMR_L3_HEAP_BASE,
 		.end   = (uint32_t)(IMR_L3_HEAP_BASE + IMR_L3_HEAP_SIZE),
@@ -133,7 +160,7 @@ const struct xtensa_mmu_range xtensa_soc_mmu_ranges[] = {
 	},
 	{
 		/* FIXME: definitely need more refinements... */
-		.start = (uint32_t)0x170000,
+		.start = (uint32_t)0x160000,
 		.end   = (uint32_t)0x180000,
 		.attrs = XTENSA_MMU_PERM_W,
 		.name = "hwreg1",
diff --git a/soc/intel/intel_adsp/ace/power.c b/soc/intel/intel_adsp/ace/power.c
index ed133b8eedd..34684e6756c 100644
--- a/soc/intel/intel_adsp/ace/power.c
+++ b/soc/intel/intel_adsp/ace/power.c
@@ -340,7 +340,7 @@ void pm_state_set(enum pm_state state, uint8_t substate_id)
 			sys_cache_data_flush_range((void *)imr_layout, sizeof(*imr_layout));
 #endif /* CONFIG_ADSP_IMR_CONTEXT_SAVE */
 			/* do power down - this function won't return */
-			power_down(true, CONFIG_ADSP_POWER_DOWN_HPSRAM, true);
+			power_down(true, IS_ENABLED(CONFIG_ADSP_POWER_DOWN_HPSRAM), true);
 		} else {
 			power_gate_entry(cpu);
 		}
diff --git a/soc/intel/intel_adsp/ace/spin_relax.c b/soc/intel/intel_adsp/ace/spin_relax.c
new file mode 100644
index 00000000000..073deb5a6d0
--- /dev/null
+++ b/soc/intel/intel_adsp/ace/spin_relax.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+
+#include <zephyr/toolchain.h>
+#include <zephyr/sys/util_macro.h>
+
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE_NUM_SPIN_RELAX_NOPS
+void arch_spin_relax(void)
+{
+	register uint32_t remaining = CONFIG_SOC_SERIES_INTEL_ADSP_ACE_NUM_SPIN_RELAX_NOPS;
+
+	while (remaining > 0) {
+#if (CONFIG_SOC_SERIES_INTEL_ADSP_ACE_NUM_SPIN_RELAX_NOPS % 4) == 0
+		remaining -= 4;
+
+		/*
+		 * Note the xcc/xt-clang likes to "truncate"
+		 * continuous NOPs to max 4 NOPs. So this is
+		 * the most we can do in one loop.
+		 */
+		__asm__("nop.n; nop.n; nop.n; nop.n;");
+#else
+		remaining--;
+		__asm__("nop.n");
+#endif
+	}
+}
+#endif /* CONFIG_SOC_SERIES_INTEL_ADSP_ACE_NUM_SPIN_RELAX_NOPS */
diff --git a/soc/intel/intel_adsp/tools/cavstool_client.py b/soc/intel/intel_adsp/tools/cavstool_client.py
index fe4adc0b8b1..76e6d5d2208 100755
--- a/soc/intel/intel_adsp/tools/cavstool_client.py
+++ b/soc/intel/intel_adsp/tools/cavstool_client.py
@@ -62,7 +62,8 @@ def uploading(self, filename):
         fname = os.path.basename(filename)
         fsize = os.path.getsize(filename)
 
-        md5_tx = hashlib.md5(open(filename,'rb').read()).hexdigest()
+        md5_tx = hashlib.md5(open(filename,'rb').read(),
+                             usedforsecurity=False).hexdigest()
 
         # Pack the header and the expecting packed size is 78 bytes.
         # The header by convention includes:
diff --git a/soc/intel/intel_adsp/tools/remote-fw-service.py b/soc/intel/intel_adsp/tools/remote-fw-service.py
index 1d68a7db2a1..276f2323f86 100755
--- a/soc/intel/intel_adsp/tools/remote-fw-service.py
+++ b/soc/intel/intel_adsp/tools/remote-fw-service.py
@@ -77,7 +77,7 @@ def receive_fw(self):
             return None
 
         # Check the MD5 of the firmware
-        md5_rx = hashlib.md5(total).hexdigest()
+        md5_rx = hashlib.md5(total, usedforsecurity=False).hexdigest()
         md5_tx = md5_tx_b.decode('utf-8')
 
         if md5_tx != md5_rx:
diff --git a/soc/intel/intel_ish/Kconfig b/soc/intel/intel_ish/Kconfig
index 084fb45b70f..82232a20104 100644
--- a/soc/intel/intel_ish/Kconfig
+++ b/soc/intel/intel_ish/Kconfig
@@ -6,10 +6,10 @@
 
 config SOC_FAMILY_INTEL_ISH
 	select X86
+	select CPU_LAKEMONT_VALUE
 	select X86_NO_SPECULATIVE_VULNERABILITIES
 	select IOAPIC
 	select LOAPIC
-	select CPU_HAS_FPU
 	select INTEL_HAL
 	select HAS_PM
 	select HAS_COVERAGE_SUPPORT
diff --git a/soc/intel/lakemont/Kconfig b/soc/intel/lakemont/Kconfig
index 42727fddd5a..48614d4297f 100644
--- a/soc/intel/lakemont/Kconfig
+++ b/soc/intel/lakemont/Kconfig
@@ -4,7 +4,7 @@
 
 config SOC_LAKEMONT
 	select X86
-	select CPU_LAKEMONT
+	select CPU_LAKEMONT_PERF
 	select X86_MMU if FPU
 	select X86_SSE if FPU
 	select X86_SSE2 if FPU
diff --git a/soc/intel/raptor_lake/soc_gpio.h b/soc/intel/raptor_lake/soc_gpio.h
index 6901cab9221..79db43a7e7d 100644
--- a/soc/intel/raptor_lake/soc_gpio.h
+++ b/soc/intel/raptor_lake/soc_gpio.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023, Intel Corporation
+ * Copyright (c) 2023-2025, Intel Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -15,7 +15,7 @@
 #ifndef __SOC_GPIO_H_
 #define __SOC_GPIO_H_
 
-#if defined(CONFIG_BOARD_INTEL_RPL_S_CRB)
+#if defined(CONFIG_BOARD_INTEL_RPL_S_CRB) || defined(CONFIG_BOARD_INTEL_BTL_S_CRB)
 #define GPIO_INTEL_NR_SUBDEVS		13
 #define REG_PAD_OWNER_BASE		0x00A0
 #define REG_GPI_INT_STS_BASE		0x0200
diff --git a/soc/ite/ec/Kconfig.defconfig b/soc/ite/ec/Kconfig.defconfig
index 646437f9c53..2030dc8a68c 100644
--- a/soc/ite/ec/Kconfig.defconfig
+++ b/soc/ite/ec/Kconfig.defconfig
@@ -5,4 +5,8 @@ if SOC_FAMILY_ITE_EC
 
 rsource "*/Kconfig.defconfig.series"
 
+choice PM_POLICY
+	default PM_POLICY_CUSTOM if SOC_FAMILY_ITE_EC
+endchoice
+
 endif # SOC_FAMILY_ITE_EC
diff --git a/soc/ite/ec/common/CMakeLists.txt b/soc/ite/ec/common/CMakeLists.txt
index 120b54fe2d7..39f3ded8328 100644
--- a/soc/ite/ec/common/CMakeLists.txt
+++ b/soc/ite/ec/common/CMakeLists.txt
@@ -1,10 +1,8 @@
 zephyr_include_directories(.)
 
 zephyr_sources(
-  check_regs.c
   soc_irq.S
   soc_common_irq.c
-  vector.S
   )
 
 zephyr_sources_ifdef(CONFIG_PM power.c)
diff --git a/soc/ite/ec/common/chip_chipregs.h b/soc/ite/ec/common/chip_chipregs.h
deleted file mode 100644
index 08e15aeebba..00000000000
--- a/soc/ite/ec/common/chip_chipregs.h
+++ /dev/null
@@ -1,2275 +0,0 @@
-/*
- * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef CHIP_CHIPREGS_H
-#define CHIP_CHIPREGS_H
-
-#include <zephyr/sys/util.h>
-
-#define EC_REG_BASE_ADDR 0x00f00000
-
-#ifdef _ASMLANGUAGE
-#define ECREG(x)        x
-#else
-
-/*
- * Macros for hardware registers access.
- */
-#define ECREG(x)		(*((volatile unsigned char *)(x)))
-#define ECREG_u16(x)		(*((volatile unsigned short *)(x)))
-#define ECREG_u32(x)		(*((volatile unsigned long  *)(x)))
-
-/*
- * MASK operation macros
- */
-#define SET_MASK(reg, bit_mask)			((reg) |= (bit_mask))
-#define CLEAR_MASK(reg, bit_mask)		((reg) &= (~(bit_mask)))
-#define IS_MASK_SET(reg, bit_mask)		(((reg) & (bit_mask)) != 0)
-#endif /* _ASMLANGUAGE */
-
-#ifndef REG_BASE_ADDR
-#define REG_BASE_ADDR				EC_REG_BASE_ADDR
-#endif
-
-/* Common definition */
-/*
- * EC clock frequency (PWM and tachometer driver need it to reply
- * to api or calculate RPM)
- */
-#ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ
-#define EC_FREQ			MHZ(24)
-#else
-#define EC_FREQ			MHZ(8)
-
-#endif
-
-/* --- General Control (GCTRL) --- */
-#define IT8XXX2_GCTRL_BASE      0x00F02000
-#define IT8XXX2_GCTRL_EIDSR     ECREG(IT8XXX2_GCTRL_BASE + 0x31)
-#define IT8XXX2_GCTRL_PMER3     ECREG(IT8XXX2_GCTRL_BASE + 0x46)
-/* RISC-V JTAG Debug Interface Enable */
-#define IT8XXX2_GCTRL_JTAGEN    BIT(1)
-/* RISC-V JTAG Debug Interface Selection */
-#define IT8XXX2_GCTRL_JTAGSEL   BIT(0)
-#define IT8XXX2_GCTRL_JTAG      (IT8XXX2_GCTRL_JTAGEN | IT8XXX2_GCTRL_JTAGSEL)
-
-#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
-#define IT8XXX2_JTAG_PINS_BASE  ECREG(0xF01660)
-#define IT8XXX2_JTAG_VOLT_SET   ECREG(0xF01648)
-#elif CONFIG_SOC_IT8XXX2_REG_SET_V1
-#define IT8XXX2_JTAG_PINS_BASE  ECREG(0xF01610)
-#define IT8XXX2_JTAG_VOLT_SET   ECREG(0xF016e9)
-#endif
-
-#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
-/* --- External GPIO Control (EGPIO) --- */
-#define IT8XXX2_EGPIO_BASE      0x00F02100
-#define IT8XXX2_EGPIO_EGCR      ECREG(IT8XXX2_EGPIO_BASE + 0x04)
-
-/* EGPIO register fields */
-/*
- * 0x04: External GPIO Control
- * BIT(4): EXGPIO EGAD Pin Output Driving Disable
- */
-#define IT8XXX2_EGPIO_EEPODD    BIT(4)
-#endif
-
-/**
- *
- * (11xxh) Interrupt controller (INTC)
- *
- */
-#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
-#define ISR0			ECREG(EC_REG_BASE_ADDR + 0x3F00)
-#define ISR1			ECREG(EC_REG_BASE_ADDR + 0x3F01)
-#define ISR2			ECREG(EC_REG_BASE_ADDR + 0x3F02)
-#define ISR3			ECREG(EC_REG_BASE_ADDR + 0x3F03)
-#define ISR4			ECREG(EC_REG_BASE_ADDR + 0x3F14)
-#define ISR5			ECREG(EC_REG_BASE_ADDR + 0x3F18)
-#define ISR6			ECREG(EC_REG_BASE_ADDR + 0x3F1C)
-#define ISR7			ECREG(EC_REG_BASE_ADDR + 0x3F20)
-#define ISR8			ECREG(EC_REG_BASE_ADDR + 0x3F24)
-#define ISR9			ECREG(EC_REG_BASE_ADDR + 0x3F28)
-#define ISR10			ECREG(EC_REG_BASE_ADDR + 0x3F2C)
-#define ISR11			ECREG(EC_REG_BASE_ADDR + 0x3F30)
-#define ISR12			ECREG(EC_REG_BASE_ADDR + 0x3F34)
-#define ISR13			ECREG(EC_REG_BASE_ADDR + 0x3F38)
-#define ISR14			ECREG(EC_REG_BASE_ADDR + 0x3F3C)
-#define ISR15			ECREG(EC_REG_BASE_ADDR + 0x3F40)
-#define ISR16			ECREG(EC_REG_BASE_ADDR + 0x3F44)
-#define ISR17			ECREG(EC_REG_BASE_ADDR + 0x3F48)
-#define ISR18			ECREG(EC_REG_BASE_ADDR + 0x3F4C)
-#define ISR19			ECREG(EC_REG_BASE_ADDR + 0x3F50)
-#define ISR20			ECREG(EC_REG_BASE_ADDR + 0x3F54)
-#define ISR21			ECREG(EC_REG_BASE_ADDR + 0x3F58)
-#define ISR22			ECREG(EC_REG_BASE_ADDR + 0x3F5C)
-#define ISR23			ECREG(EC_REG_BASE_ADDR + 0x3F90)
-
-#define IER0			ECREG(EC_REG_BASE_ADDR + 0x3F04)
-#define IER1			ECREG(EC_REG_BASE_ADDR + 0x3F05)
-#define IER2			ECREG(EC_REG_BASE_ADDR + 0x3F06)
-#define IER3			ECREG(EC_REG_BASE_ADDR + 0x3F07)
-#define IER4			ECREG(EC_REG_BASE_ADDR + 0x3F15)
-#define IER5			ECREG(EC_REG_BASE_ADDR + 0x3F19)
-#define IER6			ECREG(EC_REG_BASE_ADDR + 0x3F1D)
-#define IER7			ECREG(EC_REG_BASE_ADDR + 0x3F21)
-#define IER8			ECREG(EC_REG_BASE_ADDR + 0x3F25)
-#define IER9			ECREG(EC_REG_BASE_ADDR + 0x3F29)
-#define IER10			ECREG(EC_REG_BASE_ADDR + 0x3F2D)
-#define IER11			ECREG(EC_REG_BASE_ADDR + 0x3F31)
-#define IER12			ECREG(EC_REG_BASE_ADDR + 0x3F35)
-#define IER13			ECREG(EC_REG_BASE_ADDR + 0x3F39)
-#define IER14			ECREG(EC_REG_BASE_ADDR + 0x3F3D)
-#define IER15			ECREG(EC_REG_BASE_ADDR + 0x3F41)
-#define IER16			ECREG(EC_REG_BASE_ADDR + 0x3F45)
-#define IER17			ECREG(EC_REG_BASE_ADDR + 0x3F49)
-#define IER18			ECREG(EC_REG_BASE_ADDR + 0x3F4D)
-#define IER19			ECREG(EC_REG_BASE_ADDR + 0x3F51)
-#define IER20			ECREG(EC_REG_BASE_ADDR + 0x3F55)
-#define IER21			ECREG(EC_REG_BASE_ADDR + 0x3F59)
-#define IER22			ECREG(EC_REG_BASE_ADDR + 0x3F5D)
-#define IER23			ECREG(EC_REG_BASE_ADDR + 0x3F91)
-
-#define IELMR0			ECREG(EC_REG_BASE_ADDR + 0x3F08)
-#define IELMR1			ECREG(EC_REG_BASE_ADDR + 0x3F09)
-#define IELMR2			ECREG(EC_REG_BASE_ADDR + 0x3F0A)
-#define IELMR3			ECREG(EC_REG_BASE_ADDR + 0x3F0B)
-#define IELMR4			ECREG(EC_REG_BASE_ADDR + 0x3F16)
-#define IELMR5			ECREG(EC_REG_BASE_ADDR + 0x3F1A)
-#define IELMR6			ECREG(EC_REG_BASE_ADDR + 0x3F1E)
-#define IELMR7			ECREG(EC_REG_BASE_ADDR + 0x3F22)
-#define IELMR8			ECREG(EC_REG_BASE_ADDR + 0x3F26)
-#define IELMR9			ECREG(EC_REG_BASE_ADDR + 0x3F2A)
-#define IELMR10			ECREG(EC_REG_BASE_ADDR + 0x3F2E)
-#define IELMR11			ECREG(EC_REG_BASE_ADDR + 0x3F32)
-#define IELMR12			ECREG(EC_REG_BASE_ADDR + 0x3F36)
-#define IELMR13			ECREG(EC_REG_BASE_ADDR + 0x3F3A)
-#define IELMR14			ECREG(EC_REG_BASE_ADDR + 0x3F3E)
-#define IELMR15			ECREG(EC_REG_BASE_ADDR + 0x3F42)
-#define IELMR16			ECREG(EC_REG_BASE_ADDR + 0x3F46)
-#define IELMR17			ECREG(EC_REG_BASE_ADDR + 0x3F4A)
-#define IELMR18			ECREG(EC_REG_BASE_ADDR + 0x3F4E)
-#define IELMR19			ECREG(EC_REG_BASE_ADDR + 0x3F52)
-#define IELMR20			ECREG(EC_REG_BASE_ADDR + 0x3F56)
-#define IELMR21			ECREG(EC_REG_BASE_ADDR + 0x3F5A)
-#define IELMR22			ECREG(EC_REG_BASE_ADDR + 0x3F5E)
-#define IELMR23			ECREG(EC_REG_BASE_ADDR + 0x3F92)
-
-#define IPOLR0			ECREG(EC_REG_BASE_ADDR + 0x3F0C)
-#define IPOLR1			ECREG(EC_REG_BASE_ADDR + 0x3F0D)
-#define IPOLR2			ECREG(EC_REG_BASE_ADDR + 0x3F0E)
-#define IPOLR3			ECREG(EC_REG_BASE_ADDR + 0x3F0F)
-#define IPOLR4			ECREG(EC_REG_BASE_ADDR + 0x3F17)
-#define IPOLR5			ECREG(EC_REG_BASE_ADDR + 0x3F1B)
-#define IPOLR6			ECREG(EC_REG_BASE_ADDR + 0x3F1F)
-#define IPOLR7			ECREG(EC_REG_BASE_ADDR + 0x3F23)
-#define IPOLR8			ECREG(EC_REG_BASE_ADDR + 0x3F27)
-#define IPOLR9			ECREG(EC_REG_BASE_ADDR + 0x3F2B)
-#define IPOLR10			ECREG(EC_REG_BASE_ADDR + 0x3F2F)
-#define IPOLR11			ECREG(EC_REG_BASE_ADDR + 0x3F33)
-#define IPOLR12			ECREG(EC_REG_BASE_ADDR + 0x3F37)
-#define IPOLR13			ECREG(EC_REG_BASE_ADDR + 0x3F3B)
-#define IPOLR14			ECREG(EC_REG_BASE_ADDR + 0x3F3F)
-#define IPOLR15			ECREG(EC_REG_BASE_ADDR + 0x3F43)
-#define IPOLR16			ECREG(EC_REG_BASE_ADDR + 0x3F47)
-#define IPOLR17			ECREG(EC_REG_BASE_ADDR + 0x3F4B)
-#define IPOLR18			ECREG(EC_REG_BASE_ADDR + 0x3F4F)
-#define IPOLR19			ECREG(EC_REG_BASE_ADDR + 0x3F53)
-#define IPOLR20			ECREG(EC_REG_BASE_ADDR + 0x3F57)
-#define IPOLR21			ECREG(EC_REG_BASE_ADDR + 0x3F5B)
-#define IPOLR22			ECREG(EC_REG_BASE_ADDR + 0x3F5F)
-#define IPOLR23			ECREG(EC_REG_BASE_ADDR + 0x3F93)
-#endif
-#define IVECT			ECREG(EC_REG_BASE_ADDR + 0x3F10)
-
-
-/*
- * TODO: use pinctrl node instead of following register declarations
- *       to fix in tcpm\it83xx_pd.h.
- */
-/* GPIO control register */
-#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
-#define GPCRF4			ECREG(EC_REG_BASE_ADDR + 0x163C)
-#define GPCRF5			ECREG(EC_REG_BASE_ADDR + 0x163D)
-#define GPCRH1			ECREG(EC_REG_BASE_ADDR + 0x1649)
-#define GPCRH2			ECREG(EC_REG_BASE_ADDR + 0x164A)
-#elif CONFIG_SOC_IT8XXX2_REG_SET_V2
-#define GPCRF4			ECREG(EC_REG_BASE_ADDR + 0x168C)
-#define GPCRF5			ECREG(EC_REG_BASE_ADDR + 0x168D)
-#define GPCRH1			ECREG(EC_REG_BASE_ADDR + 0x1699)
-#define GPCRH2			ECREG(EC_REG_BASE_ADDR + 0x169A)
-#endif
-
-/*
- * IT8XXX2 register structure size/offset checking macro function to mitigate
- * the risk of unexpected compiling results.
- */
-#define IT8XXX2_REG_SIZE_CHECK(reg_def, size) \
-	BUILD_ASSERT(sizeof(struct reg_def) == size, \
-		"Failed in size check of register structure!")
-#define IT8XXX2_REG_OFFSET_CHECK(reg_def, member, offset) \
-	BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \
-		"Failed in offset check of register structure member!")
-
-/**
- *
- * (18xxh) PWM & SmartAuto Fan Control (PWM)
- *
- */
-#ifndef __ASSEMBLER__
-struct pwm_it8xxx2_regs {
-	/* 0x000: Channel0 Clock Prescaler */
-	volatile uint8_t C0CPRS;
-	/* 0x001: Cycle Time0 */
-	volatile uint8_t CTR;
-	/* 0x002~0x00A: Reserved1 */
-	volatile uint8_t Reserved1[9];
-	/* 0x00B: Prescaler Clock Frequency Select */
-	volatile uint8_t PCFSR;
-	/* 0x00C~0x00F: Reserved2 */
-	volatile uint8_t Reserved2[4];
-	/* 0x010: Cycle Time1 MSB */
-	volatile uint8_t CTR1M;
-	/* 0x011~0x022: Reserved3 */
-	volatile uint8_t Reserved3[18];
-	/* 0x023: PWM Clock Control */
-	volatile uint8_t ZTIER;
-	/* 0x024~0x026: Reserved4 */
-	volatile uint8_t Reserved4[3];
-	/* 0x027: Channel4 Clock Prescaler */
-	volatile uint8_t C4CPRS;
-	/* 0x028: Channel4 Clock Prescaler MSB */
-	volatile uint8_t C4MCPRS;
-	/* 0x029~0x02A: Reserved5 */
-	volatile uint8_t Reserved5[2];
-	/* 0x02B: Channel6 Clock Prescaler */
-	volatile uint8_t C6CPRS;
-	/* 0x02C: Channel6 Clock Prescaler MSB */
-	volatile uint8_t C6MCPRS;
-	/* 0x02D: Channel7 Clock Prescaler */
-	volatile uint8_t C7CPRS;
-	/* 0x02E: Channel7 Clock Prescaler MSB */
-	volatile uint8_t C7MCPRS;
-	/* 0x02F~0x040: Reserved6 */
-	volatile uint8_t reserved6[18];
-	/* 0x041: Cycle Time1 */
-	volatile uint8_t CTR1;
-	/* 0x042: Cycle Time2 */
-	volatile uint8_t CTR2;
-	/* 0x043: Cycle Time3 */
-	volatile uint8_t CTR3;
-	/* 0x044~0x048: Reserved7 */
-	volatile uint8_t reserved7[5];
-	/* 0x049: PWM Output Open-Drain Enable */
-	volatile uint8_t PWMODENR;
-};
-#endif /* !__ASSEMBLER__ */
-
-/* PWM register fields */
-/* 0x023: PWM Clock Control */
-#define IT8XXX2_PWM_PCCE		BIT(1)
-/* 0x048: Tachometer Switch Control */
-#define IT8XXX2_PWM_T0DVS		BIT(3)
-#define IT8XXX2_PWM_T0CHSEL		BIT(2)
-#define IT8XXX2_PWM_T1DVS		BIT(1)
-#define IT8XXX2_PWM_T1CHSEL		BIT(0)
-
-
-/* --- Wake-Up Control (WUC) --- */
-#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
-#define IT8XXX2_WUC_BASE   0x00F01B00
-
-/* TODO: should a defined interface for configuring wake-up interrupts */
-#define IT8XXX2_WUC_WUEMR1 (IT8XXX2_WUC_BASE + 0x00)
-#define IT8XXX2_WUC_WUEMR5 (IT8XXX2_WUC_BASE + 0x0c)
-#define IT8XXX2_WUC_WUESR1 (IT8XXX2_WUC_BASE + 0x04)
-#define IT8XXX2_WUC_WUESR5 (IT8XXX2_WUC_BASE + 0x0d)
-#define IT8XXX2_WUC_WUBEMR1 (IT8XXX2_WUC_BASE + 0x3c)
-#define IT8XXX2_WUC_WUBEMR5 (IT8XXX2_WUC_BASE + 0x0f)
-#endif
-
-/**
- *
- * (1Dxxh) Keyboard Matrix Scan control (KSCAN)
- *
- */
-#ifndef __ASSEMBLER__
-struct kscan_it8xxx2_regs {
-	/* 0x000: Keyboard Scan Out */
-	volatile uint8_t KBS_KSOL;
-	/* 0x001: Keyboard Scan Out */
-	volatile uint8_t KBS_KSOH1;
-	/* 0x002: Keyboard Scan Out Control */
-	volatile uint8_t KBS_KSOCTRL;
-	/* 0x003: Keyboard Scan Out */
-	volatile uint8_t KBS_KSOH2;
-	/* 0x004: Keyboard Scan In */
-	volatile uint8_t KBS_KSI;
-	/* 0x005: Keyboard Scan In Control */
-	volatile uint8_t KBS_KSICTRL;
-	/* 0x006: Keyboard Scan In [7:0] GPIO Control */
-	volatile uint8_t KBS_KSIGCTRL;
-	/* 0x007: Keyboard Scan In [7:0] GPIO Output Enable */
-	volatile uint8_t KBS_KSIGOEN;
-	/* 0x008: Keyboard Scan In [7:0] GPIO Data */
-	volatile uint8_t KBS_KSIGDAT;
-	/* 0x009: Keyboard Scan In [7:0] GPIO Data Mirror */
-	volatile uint8_t KBS_KSIGDMRR;
-	/* 0x00A: Keyboard Scan Out [15:8] GPIO Control */
-	volatile uint8_t KBS_KSOHGCTRL;
-	/* 0x00B: Keyboard Scan Out [15:8] GPIO Output Enable */
-	volatile uint8_t KBS_KSOHGOEN;
-	/* 0x00C: Keyboard Scan Out [15:8] GPIO Data Mirror */
-	volatile uint8_t KBS_KSOHGDMRR;
-	/* 0x00D: Keyboard Scan Out [7:0] GPIO Control */
-	volatile uint8_t KBS_KSOLGCTRL;
-	/* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */
-	volatile uint8_t KBS_KSOLGOEN;
-};
-#endif /* !__ASSEMBLER__ */
-
-/* KBS register fields */
-/* 0x002: Keyboard Scan Out Control */
-#define IT8XXX2_KBS_KSOPU	BIT(2)
-#define IT8XXX2_KBS_KSOOD	BIT(0)
-/* 0x005: Keyboard Scan In Control */
-#define IT8XXX2_KBS_KSIPU	BIT(2)
-/* 0x00D: Keyboard Scan Out [7:0] GPIO Control */
-#define IT8XXX2_KBS_KSO2GCTRL	BIT(2)
-/* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */
-#define IT8XXX2_KBS_KSO2GOEN	BIT(2)
-
-
-/**
- *
- * (1Fxxh) External Timer & External Watchdog (ETWD)
- *
- */
-#define WDT_IT8XXX2_REGS_BASE \
-	((struct wdt_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(twd0)))
-
-#ifndef __ASSEMBLER__
-struct wdt_it8xxx2_regs {
-	/* 0x000: Reserved1 */
-	volatile uint8_t reserved1;
-	/* 0x001: External Timer1/WDT Configuration */
-	volatile uint8_t ETWCFG;
-	/* 0x002: External Timer1 Prescaler */
-	volatile uint8_t ET1PSR;
-	/* 0x003: External Timer1 Counter High Byte */
-	volatile uint8_t ET1CNTLHR;
-	/* 0x004: External Timer1 Counter Low Byte */
-	volatile uint8_t ET1CNTLLR;
-	/* 0x005: External Timer1/WDT Control */
-	volatile uint8_t ETWCTRL;
-	/* 0x006: External WDT Counter Low Byte */
-	volatile uint8_t EWDCNTLR;
-	/* 0x007: External WDT Key */
-	volatile uint8_t EWDKEYR;
-	/* 0x008: Reserved2 */
-	volatile uint8_t reserved2;
-	/* 0x009: External WDT Counter High Byte */
-	volatile uint8_t EWDCNTHR;
-	/* 0x00A: External Timer2 Prescaler */
-	volatile uint8_t ET2PSR;
-	/* 0x00B: External Timer2 Counter High Byte */
-	volatile uint8_t ET2CNTLHR;
-	/* 0x00C: External Timer2 Counter Low Byte */
-	volatile uint8_t ET2CNTLLR;
-	/* 0x00D: Reserved3 */
-	volatile uint8_t reserved3;
-	/* 0x00E: External Timer2 Counter High Byte2 */
-	volatile uint8_t ET2CNTLH2R;
-};
-#endif /* !__ASSEMBLER__ */
-
-/* WDT register fields */
-/* 0x001: External Timer1/WDT Configuration */
-#define IT8XXX2_WDT_EWDKEYEN		BIT(5)
-#define IT8XXX2_WDT_EWDSRC		BIT(4)
-#define IT8XXX2_WDT_LEWDCNTL		BIT(3)
-#define IT8XXX2_WDT_LET1CNTL		BIT(2)
-#define IT8XXX2_WDT_LET1PS		BIT(1)
-#define IT8XXX2_WDT_LETWCFG		BIT(0)
-/* 0x002: External Timer1 Prescaler */
-#define IT8XXX2_WDT_ETPS_32P768_KHZ	0x00
-#define IT8XXX2_WDT_ETPS_1P024_KHZ	0x01
-#define IT8XXX2_WDT_ETPS_32_HZ		0x02
-/* 0x005: External Timer1/WDT Control */
-#define IT8XXX2_WDT_EWDSCEN		BIT(5)
-#define IT8XXX2_WDT_EWDSCMS		BIT(4)
-#define IT8XXX2_WDT_ET2TC		BIT(3)
-#define IT8XXX2_WDT_ET2RST		BIT(2)
-#define IT8XXX2_WDT_ET1TC		BIT(1)
-#define IT8XXX2_WDT_ET1RST		BIT(0)
-
-/* External Timer register fields */
-/* External Timer 3~8 control */
-#define IT8XXX2_EXT_ETX_COMB_RST_EN	(IT8XXX2_EXT_ETXCOMB | \
-					 IT8XXX2_EXT_ETXRST | \
-					 IT8XXX2_EXT_ETXEN)
-#define IT8XXX2_EXT_ETXCOMB		BIT(3)
-#define IT8XXX2_EXT_ETXRST		BIT(1)
-#define IT8XXX2_EXT_ETXEN		BIT(0)
-
-/* Control external timer3~8 */
-#define IT8XXX2_EXT_TIMER_BASE  DT_REG_ADDR(DT_NODELABEL(timer))  /*0x00F01F10*/
-#define IT8XXX2_EXT_CTRLX(n)    ECREG(IT8XXX2_EXT_TIMER_BASE + (n << 3))
-#define IT8XXX2_EXT_PSRX(n)     ECREG(IT8XXX2_EXT_TIMER_BASE + 0x01 + (n << 3))
-#define IT8XXX2_EXT_CNTX(n)     ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x04 + \
-					(n << 3))
-#define IT8XXX2_EXT_CNTOX(n)    ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x38 + \
-					(n << 2))
-
-/* Free run timer configurations */
-#define FREE_RUN_TIMER          EXT_TIMER_4
-#define FREE_RUN_TIMER_IRQ      DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, irq)
-/* Free run timer configurations */
-#define FREE_RUN_TIMER_FLAG     DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, flags)
-/* Free run timer max count is 36.4 hr (base on clock source 32768Hz) */
-#define FREE_RUN_TIMER_MAX_CNT  0xFFFFFFFFUL
-
-#ifndef __ASSEMBLER__
-enum ext_clk_src_sel {
-	EXT_PSR_32P768K = 0,
-	EXT_PSR_1P024K,
-	EXT_PSR_32,
-	EXT_PSR_EC_CLK,
-};
-/*
- * 24-bit timers: external timer 3, 5, and 7
- * 32-bit timers: external timer 4, 6, and 8
- */
-enum ext_timer_idx {
-	EXT_TIMER_3 = 0,	/* Event timer */
-	EXT_TIMER_4,		/* Free run timer */
-	EXT_TIMER_5,		/* Busy wait low timer */
-	EXT_TIMER_6,		/* Busy wait high timer */
-	EXT_TIMER_7,
-	EXT_TIMER_8,
-};
-#endif
-
-
-/*
- *
- * (2Cxxh) Platform Environment Control Interface (PECI)
- *
- */
-#ifndef __ASSEMBLER__
-struct peci_it8xxx2_regs {
-	/* 0x00: Host Status */
-	volatile uint8_t HOSTAR;
-	/* 0x01: Host Control */
-	volatile uint8_t HOCTLR;
-	/* 0x02: Host Command */
-	volatile uint8_t HOCMDR;
-	/* 0x03: Host Target Address */
-	volatile uint8_t HOTRADDR;
-	/* 0x04: Host Write Length */
-	volatile uint8_t HOWRLR;
-	/* 0x05: Host Read Length */
-	volatile uint8_t HORDLR;
-	/* 0x06: Host Write Data */
-	volatile uint8_t HOWRDR;
-	/* 0x07: Host Read Data */
-	volatile uint8_t HORDDR;
-	/* 0x08: Host Control 2 */
-	volatile uint8_t HOCTL2R;
-	/* 0x09: Received Write FCS value */
-	volatile uint8_t RWFCSV;
-	/* 0x0A: Received Read FCS value */
-	volatile uint8_t RRFCSV;
-	/* 0x0B: Write FCS Value */
-	volatile uint8_t WFCSV;
-	/* 0x0C: Read FCS Value */
-	volatile uint8_t RFCSV;
-	/* 0x0D: Assured Write FCS Value */
-	volatile uint8_t AWFCSV;
-	/* 0x0E: Pad Control */
-	volatile uint8_t PADCTLR;
-};
-#endif /* !__ASSEMBLER__ */
-
-/**
- *
- * (2Fxxh) USB Device Controller (USBDC) Registers
- *
- */
-#define EP_EXT_REGS_9X        1
-#define EP_EXT_REGS_BX        2
-#define EP_EXT_REGS_DX        3
-
-#ifndef __ASSEMBLER__
-
-/* EP0 to EP15 Enumeration */
-enum usb_dc_endpoints {
-	EP0,
-	EP1,
-	EP2,
-	EP3,
-	EP4,
-	EP5,
-	EP6,
-	EP7,
-	EP8,
-	EP9,
-	EP10,
-	EP11,
-	EP12,
-	EP13,
-	EP14,
-	EP15,
-	MAX_NUM_ENDPOINTS
-};
-
-union ep_ctrl_reg {
-	volatile uint8_t value;
-	struct {
-		volatile uint8_t enable_bit: 1;
-		volatile uint8_t ready_bit: 1;
-		volatile uint8_t outdata_sequence_bit: 1;
-		volatile uint8_t send_stall_bit: 1;
-		volatile uint8_t iso_enable_bit: 1;
-		volatile uint8_t direction_bit: 1;
-		volatile uint8_t reserved: 2;
-	} __packed fields;
-} __packed;
-
-struct it82xx2_usb_ep_regs {
-	union ep_ctrl_reg ep_ctrl;
-	volatile uint8_t ep_status;
-	volatile uint8_t ep_transtype_sts;
-	volatile uint8_t ep_nak_transtype_sts;
-};
-
-/* Reserved EP Extended Registers */
-struct ep_ext_regs_7x {
-	/* 0x75 Reserved */
-	volatile uint8_t ep_ext_ctrl_75;
-	/* 0x76 Reserved */
-	volatile uint8_t ep_ext_ctrl_76;
-	/* 0x77 Reserved */
-	volatile uint8_t ep_ext_ctrl_77;
-	/* 0x78 Reserved */
-	volatile uint8_t ep_ext_ctrl_78;
-	/* 0x79 Reserved */
-	volatile uint8_t ep_ext_ctrl_79;
-	/* 0x7A Reserved */
-	volatile uint8_t ep_ext_ctrl_7a;
-	/* 0x7B Reserved */
-	volatile uint8_t ep_ext_ctrl_7b;
-	/* 0x7C Reserved */
-	volatile uint8_t ep_ext_ctrl_7c;
-	/* 0x7D Reserved */
-	volatile uint8_t ep_ext_ctrl_7d;
-	/* 0x7E Reserved */
-	volatile uint8_t ep_ext_ctrl_7e;
-	/* 0x7F Reserved */
-	volatile uint8_t ep_ext_ctrl_7f;
-};
-
-/* From 98h to 9Dh, the EP45/67/89/1011/1213/1415 Extended Control Registers
- * are defined, and their bits definitions are as follows:
- *
- * Bit    Description
- *  7     Reserved
- *  6     EPPOINT5_ISO_ENABLE
- *  5     EPPOINT5_SEND_STALL
- *  4     EPPOINT5_OUT_DATA_SEQUENCE
- *  3     Reserved
- *  2     EPPOINT4_ISO_ENABLE
- *  1     EPPOINT4_SEND_STALL
- *  0     EPPOINT4_OUT_DATA_SEQUENCE
- *
- * Apparently, we can tell that the EP4 and EP5 share the same register, and
- * the EP6 and EP7 share the same one, and the rest EPs are defined in the
- * same way.
- */
-union epn0n1_extend_ctrl_reg {
-	volatile uint8_t value;
-	struct {
-		volatile uint8_t epn0_outdata_sequence_bit: 1;
-		volatile uint8_t epn0_send_stall_bit: 1;
-		volatile uint8_t epn0_iso_enable_bit: 1;
-		volatile uint8_t reserved0: 1;
-		volatile uint8_t epn1_outdata_sequence_bit: 1;
-		volatile uint8_t epn1_send_stall_bit: 1;
-		volatile uint8_t epn1_iso_enable_bit: 1;
-		volatile uint8_t reserved1: 1;
-	} __packed fields;
-} __packed;
-
-struct ep_ext_regs_9x {
-	/* 0x95 Reserved */
-	volatile uint8_t ep_ext_ctrl_95;
-	/* 0x96 Reserved */
-	volatile uint8_t ep_ext_ctrl_96;
-	/* 0x97 Reserved */
-	volatile uint8_t ep_ext_ctrl_97;
-	/* 0x98 ~ 0x9D EP45/67/89/1011/1213/1415 Extended Control Registers */
-	union epn0n1_extend_ctrl_reg epn0n1_ext_ctrl[6];
-	/* 0x9E Reserved */
-	volatile uint8_t ep_ext_ctrl_9e;
-	/* 0x9F Reserved */
-	volatile uint8_t ep_ext_ctrl_9f;
-};
-
-/* From BXh to BDh are EP FIFO 1-3 Control 0/1 Registers, and their
- * definitions as follows:
- * B8h: EP_FIFO1_CONTROL0_REG
- * B9h: EP_FIFO1_CONTROL1_REG
- * BAh: EP_FIFO2_CONTROL0_REG
- * BBh: EP_FIFO2_CONTROL1_REG
- * BCh: EP_FIFO3_CONTROL0_REG
- * BDh: EP_FIFO3_CONTROL1_REG
- *
- * For each one, its bits definitions are as follows:
- * (take EP_FIFO1_CONTROL1_REG as example, which controls from EP8 to EP15)
- *
- * Bit  Description
- *
- *  7   EP15 select FIFO1 as data buffer
- *  6   EP14 select FIFO1 as data buffer
- *  5   EP13 select FIFO1 as data buffer
- *  4   EP12 select FIFO1 as data buffer
- *  3   EP11 select FIFO1 as data buffer
- *  2   EP10 select FIFO1 as data buffer
- *  1   EP9 select FIFO1 as data buffer
- *  0   EP8 select FIFO1 as data buffer
- *
- *  1: Select
- *  0: Not select
- */
-struct ep_ext_regs_bx {
-	/* 0xB5 Reserved */
-	volatile uint8_t ep_ext_ctrl_b5;
-	/* 0xB6 Reserved */
-	volatile uint8_t ep_ext_ctrl_b6;
-	/* 0xB7 Reserved */
-	volatile uint8_t ep_ext_ctrl_b7;
-	/* 0xB8 ~ 0xBD EP FIFO 1-3 Control 0/1 Registers */
-	volatile uint8_t ep_fifo_ctrl[6];
-	/* 0xBE Reserved */
-	volatile uint8_t ep_ext_ctrl_be;
-	/* 0xBF Reserved */
-	volatile uint8_t ep_ext_ctrl_bf;
-};
-
-
-/* From D6h to DDh are EP Extended Control Registers, and their
- * definitions as follows:
- * D6h: EP0_EXT_CTRL1
- * D7h: EP0_EXT_CTRL2
- * D8h: EP1_EXT_CTRL1
- * D9h: EP1_EXT_CTRL2
- * DAh: EP2_EXT_CTRL1
- * DBh: EP2_EXT_CTRL2
- * DCh: EP3_EXT_CTRL1
- * DDh: EP3_EXT_CTRL2
- *
- * We classify them into 4 groups which each of them contains Control 1 and 2
- * according to the EP number as follows:
- */
-union epn_extend_ctrl1_reg {
-	volatile uint8_t value;
-	struct {
-		volatile uint8_t epn0_enable_bit: 1;
-		volatile uint8_t epn0_direction_bit: 1;
-		volatile uint8_t epn3_enable_bit: 1;
-		volatile uint8_t epn3_direction_bit: 1;
-		volatile uint8_t epn6_enable_bit: 1;
-		volatile uint8_t epn6_direction_bit: 1;
-		volatile uint8_t epn9_enable_bit: 1;
-		volatile uint8_t epn9_direction_bit: 1;
-	} __packed fields;
-} __packed;
-
-struct epn_ext_ctrl_regs {
-	/* 0xD6/0xD8/0xDA/0xDC EPN Extended Control1 Register */
-	union epn_extend_ctrl1_reg epn_ext_ctrl1;
-	/* 0xD7/0xD9/0xDB/0xDD EPB Extended Control2 Register */
-	volatile uint8_t epn_ext_ctrl2;
-};
-
-struct ep_ext_regs_dx {
-	/* 0xD5 Reserved */
-	volatile uint8_t ep_ext_ctrl_d5;
-	/* 0xD6 ~ 0xDD EPN Extended Control 1/2 Registers */
-	struct epn_ext_ctrl_regs epn_ext_ctrl[4];
-	/* 0xDE Reserved */
-	volatile uint8_t ep_ext_ctrl_de;
-	/* 0xDF Reserved */
-	volatile uint8_t ep_ext_ctrl_df;
-};
-
-
-/* The USB EPx FIFO Registers Definitions
- * EP0: 60h ~ 74h
- * EP1: 80h ~ 94h
- * EP2: A0h ~ B4h
- * EP3: C0h ~ D4h (D6h to DDh will be defined as marcos for usage)
- */
-struct it82xx2_usb_ep_fifo_regs {
-	/* 0x60 + ep * 0x20 : EP RX FIFO Data Register  */
-	volatile uint8_t ep_rx_fifo_data;
-	/* 0x61 + ep * 0x20 : EP RX FIFO DMA Count Register */
-	volatile uint8_t ep_rx_fifo_dma_count;
-	/* 0x62 + ep * 0x20 : EP RX FIFO Data Count MSB */
-	volatile uint8_t ep_rx_fifo_dcnt_msb;
-	/* 0x63 + ep * 0x20 : EP RX FIFO Data Count LSB */
-	volatile uint8_t ep_rx_fifo_dcnt_lsb;
-	/* 0x64 + ep * 0x20  : EP RX FIFO Control Register */
-	volatile uint8_t ep_rx_fifo_ctrl;
-	/* (0x65 ~ 0x6F) + ep * 0x20 */
-	volatile uint8_t reserved_65_6f_add_20[11];
-	/* 0x70 + ep * 0x20 : EP TX FIFO Data Register  */
-	volatile uint8_t ep_tx_fifo_data;
-	/* (0x71 ~ 0x73) + ep * 0x20 */
-	volatile uint8_t reserved_71_73_add_20[3];
-	/* 0x74 + ep * 0x20 : EP TX FIFO Control Register */
-	volatile uint8_t ep_tx_fifo_ctrl;
-	/* (0x75 ~ 0x7F) + ep * 0x20 */
-	union {
-		struct ep_ext_regs_7x ep_res;
-		struct ep_ext_regs_9x ext_4_15;
-		struct ep_ext_regs_bx fifo_ctrl;
-		struct ep_ext_regs_dx ext_0_3;
-	};
-
-};
-
-/* USB Control registers */
-#define USB_IT82XX2_REGS_BASE \
-	((struct usb_it82xx2_regs *)DT_REG_ADDR(DT_NODELABEL(usb0)))
-
-/* Bit definitions of the register Port0/Port1 MISC Control: 0XE4/0xE8 */
-#define PULL_DOWN_EN	BIT(4)
-
-struct usb_it82xx2_regs {
-	/* 0x00:  Host TX Contrl Register */
-	volatile uint8_t host_tx_ctrl;
-	/* 0x01:  Host TX Transaction Type Register */
-	volatile uint8_t host_tx_trans_type;
-	/* 0x02:  Host TX Line Control Register */
-	volatile uint8_t host_tx_line_ctrl;
-	/* 0x03:  Host TX SOF Enable Register */
-	volatile uint8_t host_tx_sof_enable;
-	/* 0x04:  Host TX Address Register */
-	volatile uint8_t host_tx_addr;
-	/* 0x05:  Host TX EP Number Register */
-	volatile uint8_t host_tx_endp;
-	/* 0x06:  Host Frame Number MSP Register */
-	volatile uint8_t host_frame_num_msp;
-	/* 0x07:  Host Frame Number LSP Register */
-	volatile uint8_t host_frame_num_lsp;
-	/* 0x08:  Host Interrupt Status Register */
-	volatile uint8_t host_interrupt_status;
-	/* 0x09:  Host Interrupt Mask Register */
-	volatile uint8_t host_interrupt_mask;
-	/* 0x0A:  Host RX Status Register */
-	volatile uint8_t host_rx_status;
-	/* 0x0B:  Host RX PID Register */
-	volatile uint8_t host_rx_pid;
-	/* 0x0C:  MISC Control Register */
-	volatile uint8_t misc_control;
-	/* 0x0D:  MISC Status Register */
-	volatile uint8_t misc_status;
-	/* 0x0E:  Host RX Connect State Register */
-	volatile uint8_t host_rx_connect_state;
-	/* 0x0F:  Host SOF Timer MSB Register */
-	volatile uint8_t host_sof_timer_msb;
-	/* 0x10 ~ 0x1F:  Reserved Registers 10h - 1Fh */
-	volatile uint8_t reserved_10_1f[16];
-	/* 0x20:  Host RX FIFO Data Port Register */
-	volatile uint8_t host_rx_fifo_data;
-	/* 0x21:  Host RX FIFO DMA Input Data Count Register */
-	volatile uint8_t host_rx_fifo_dma_data_count;
-	/* 0x22:  Host TX FIFO Data Count MSB Register */
-	volatile uint8_t host_rx_fifo_data_count_msb;
-	/* 0x23:  Host TX FIFO Data Count LSB Register */
-	volatile uint8_t host_rx_fifo_data_count_lsb;
-	/* 0x24:  Host RX FIFO Data Port Register */
-	volatile uint8_t host_rx_fifo_control;
-	/* 0x25 ~ 0x2F:  Reserved Registers 25h - 2Fh */
-	volatile uint8_t reserved_25_2f[11];
-	/* 0x30:  Host TX FIFO Data Port Register */
-	volatile uint8_t host_tx_fifo_data;
-	/* 0x31 ~ 0x3F:  Reserved Registers 31h - 3Fh */
-	volatile uint8_t reserved_31_3f[15];
-	/* 0x40 ~ 0x4F: Endpoint Registers 40h - 4Fh */
-	struct it82xx2_usb_ep_regs usb_ep_regs[4];
-	/* 0x50:  Device Controller Control Register */
-	volatile uint8_t dc_control;
-	/* 0x51:  Device Controller LINE Status Register */
-	volatile uint8_t dc_line_status;
-	/* 0x52:  Device Controller Interrupt Status Register */
-	volatile uint8_t dc_interrupt_status;
-	/* 0x53:  Device Controller Interrupt Mask Register */
-	volatile uint8_t dc_interrupt_mask;
-	/* 0x54:  Device Controller Address Register */
-	volatile uint8_t dc_address;
-	/* 0x55:  Device Controller Frame Number MSP Register */
-	volatile uint8_t dc_frame_num_msp;
-	/* 0x56:  Device Controller Frame Number LSP Register */
-	volatile uint8_t dc_frame_num_lsp;
-	/* 0x57 ~ 0x5F:  Reserved Registers 57h - 5Fh */
-	volatile uint8_t reserved_57_5f[9];
-	/* 0x60 ~ 0xDF: EP FIFO Registers 60h - DFh */
-	struct it82xx2_usb_ep_fifo_regs fifo_regs[4];
-	/* 0xE0:  Host/Device Control Register */
-	volatile uint8_t host_device_control;
-	/* 0xE1 ~ 0xE3:  Reserved Registers E1h - E3h */
-	volatile uint8_t reserved_e1_e3[3];
-	/* 0xE4:  Port0 MISC Control Register */
-	volatile uint8_t port0_misc_control;
-	/* 0xE5 ~ 0xE7:  Reserved Registers E5h - E7h */
-	volatile uint8_t reserved_e5_e7[3];
-	/* 0xE8:  Port1 MISC Control Register */
-	volatile uint8_t port1_misc_control;
-};
-#endif /* #ifndef __ASSEMBLER__ */
-
-/**
- *
- * (37xxh, 38xxh) USBPD Controller
- *
- */
-#ifndef __ASSEMBLER__
-struct usbpd_it8xxx2_regs {
-	/* 0x000~0x003: Reserved1 */
-	volatile uint8_t Reserved1[4];
-	/* 0x004: CC General Configuration */
-	volatile uint8_t CCGCR;
-	/* 0x005: CC Channel Setting */
-	volatile uint8_t CCCSR;
-	/* 0x006: CC Pad Setting */
-	volatile uint8_t CCPSR;
-};
-#endif /* !__ASSEMBLER__ */
-
-/* USBPD controller register fields */
-/* 0x004: CC General Configuration */
-#define IT8XXX2_USBPD_DISABLE_CC			BIT(7)
-#define IT8XXX2_USBPD_DISABLE_CC_VOL_DETECTOR		BIT(6)
-#define IT8XXX2_USBPD_CC_SELECT_RP_RESERVED		(BIT(3) | BIT(2) | BIT(1))
-#define IT8XXX2_USBPD_CC_SELECT_RP_DEF			(BIT(3) | BIT(2))
-#define IT8XXX2_USBPD_CC_SELECT_RP_1A5			BIT(3)
-#define IT8XXX2_USBPD_CC_SELECT_RP_3A0			BIT(2)
-#define IT8XXX2_USBPD_CC1_CC2_SELECTION			BIT(0)
-/* 0x005: CC Channel Setting */
-#define IT8XXX2_USBPD_CC2_DISCONNECT			BIT(7)
-#define IT8XXX2_USBPD_CC2_DISCONNECT_5_1K_TO_GND	BIT(6)
-#define IT8XXX2_USBPD_CC1_DISCONNECT			BIT(3)
-#define IT8XXX2_USBPD_CC1_DISCONNECT_5_1K_TO_GND	BIT(2)
-#define IT8XXX2_USBPD_CC1_CC2_RP_RD_SELECT		(BIT(1) | BIT(5))
-/* 0x006: CC Pad Setting */
-#define IT8XXX2_USBPD_DISCONNECT_5_1K_CC2_DB		BIT(6)
-#define IT8XXX2_USBPD_DISCONNECT_POWER_CC2		BIT(5)
-#define IT8XXX2_USBPD_DISCONNECT_5_1K_CC1_DB		BIT(2)
-#define IT8XXX2_USBPD_DISCONNECT_POWER_CC1		BIT(1)
-
-
-/**
- *
- * (10xxh) Shared Memory Flash Interface Bridge (SMFI) registers
- *
- */
-#ifndef __ASSEMBLER__
-struct smfi_it8xxx2_regs {
-	volatile uint8_t reserved1[59];
-	/* 0x3B: EC-Indirect memory address 0 */
-	volatile uint8_t SMFI_ECINDAR0;
-	/* 0x3C: EC-Indirect memory address 1 */
-	volatile uint8_t SMFI_ECINDAR1;
-	/* 0x3D: EC-Indirect memory address 2 */
-	volatile uint8_t SMFI_ECINDAR2;
-	/* 0x3E: EC-Indirect memory address 3 */
-	volatile uint8_t SMFI_ECINDAR3;
-	/* 0x3F: EC-Indirect memory data */
-	volatile uint8_t SMFI_ECINDDR;
-	/* 0x40: Scratch SRAM 0 address low byte */
-	volatile uint8_t SMFI_SCAR0L;
-	/* 0x41: Scratch SRAM 0 address middle byte */
-	volatile uint8_t SMFI_SCAR0M;
-	/* 0x42: Scratch SRAM 0 address high byte */
-	volatile uint8_t SMFI_SCAR0H;
-	volatile uint8_t reserved1_1[23];
-	/* 0x5A: Host RAM Window Control */
-	volatile uint8_t SMFI_HRAMWC;
-	/* 0x5B: Host RAM Window 0 Base Address [11:4] */
-	volatile uint8_t SMFI_HRAMW0BA;
-	/* 0x5C: Host RAM Window 1 Base Address [11:4] */
-	volatile uint8_t SMFI_HRAMW1BA;
-	/* 0x5D: Host RAM Window 0 Access Allow Size */
-	volatile uint8_t SMFI_HRAMW0AAS;
-	/* 0x5E: Host RAM Window 1 Access Allow Size */
-	volatile uint8_t SMFI_HRAMW1AAS;
-	volatile uint8_t reserved2[67];
-	/* 0xA2: Flash control 6 */
-	volatile uint8_t SMFI_FLHCTRL6R;
-	volatile uint8_t reserved3[46];
-};
-#endif /* !__ASSEMBLER__ */
-
-/* SMFI register fields */
-/* EC-Indirect read internal flash */
-#define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6)
-/* Enable EC-indirect page program command */
-#define IT8XXX2_SMFI_MASK_ECINDPP BIT(3)
-/* Scratch SRAM 0 address(BIT(19)) */
-#define IT8XXX2_SMFI_SC0A19 BIT(7)
-/* Scratch SRAM enable */
-#define IT8XXX2_SMFI_SCAR0H_ENABLE BIT(3)
-
-/* H2RAM Path Select. 1b: H2RAM through LPC IO cycle. */
-#define SMFI_H2RAMPS           BIT(4)
-/* H2RAM Window 1 Enable */
-#define SMFI_H2RAMW1E          BIT(1)
-/* H2RAM Window 0 Enable */
-#define SMFI_H2RAMW0E          BIT(0)
-
-/* Host RAM Window x Write Protect Enable (All protected) */
-#define SMFI_HRAMWXWPE_ALL     (BIT(5) | BIT(4))
-
-
-/**
- *
- * (16xxh) General Purpose I/O Port (GPIO) registers
- *
- */
-#define GPIO_IT8XXX2_REG_BASE \
-	((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr)))
-
-#ifndef __ASSEMBLER__
-#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
-struct gpio_it8xxx2_regs {
-	/* 0x00: General Control */
-	volatile uint8_t GPIO_GCR;
-	/* 0x01-D0: Reserved1 */
-	volatile uint8_t reserved1[208];
-	/* 0xD1: General Control 25 */
-	volatile uint8_t GPIO_GCR25;
-	/* 0xD2: General Control 26 */
-	volatile uint8_t GPIO_GCR26;
-	/* 0xD3: General Control 27 */
-	volatile uint8_t GPIO_GCR27;
-	/* 0xD4: General Control 28 */
-	volatile uint8_t GPIO_GCR28;
-	/* 0xD5: General Control 31 */
-	volatile uint8_t GPIO_GCR31;
-	/* 0xD6: General Control 32 */
-	volatile uint8_t GPIO_GCR32;
-	/* 0xD7: General Control 33 */
-	volatile uint8_t GPIO_GCR33;
-	/* 0xD8-0xDF: Reserved2 */
-	volatile uint8_t reserved2[8];
-	/* 0xE0: General Control 16 */
-	volatile uint8_t GPIO_GCR16;
-	/* 0xE1: General Control 17 */
-	volatile uint8_t GPIO_GCR17;
-	/* 0xE2: General Control 18 */
-	volatile uint8_t GPIO_GCR18;
-	/* 0xE3: Reserved3 */
-	volatile uint8_t reserved3;
-	/* 0xE4: General Control 19 */
-	volatile uint8_t GPIO_GCR19;
-	/* 0xE5: General Control 20 */
-	volatile uint8_t GPIO_GCR20;
-	/* 0xE6: General Control 21 */
-	volatile uint8_t GPIO_GCR21;
-	/* 0xE7: General Control 22 */
-	volatile uint8_t GPIO_GCR22;
-	/* 0xE8: General Control 23 */
-	volatile uint8_t GPIO_GCR23;
-	/* 0xE9: General Control 24 */
-	volatile uint8_t GPIO_GCR24;
-	/* 0xEA-0xEC: Reserved4 */
-	volatile uint8_t reserved4[3];
-	/* 0xED: General Control 30 */
-	volatile uint8_t GPIO_GCR30;
-	/* 0xEE: General Control 29 */
-	volatile uint8_t GPIO_GCR29;
-	/* 0xEF: Reserved5 */
-	volatile uint8_t reserved5;
-	/* 0xF0: General Control 1 */
-	volatile uint8_t GPIO_GCR1;
-	/* 0xF1: General Control 2 */
-	volatile uint8_t GPIO_GCR2;
-	/* 0xF2: General Control 3 */
-	volatile uint8_t GPIO_GCR3;
-	/* 0xF3: General Control 4 */
-	volatile uint8_t GPIO_GCR4;
-	/* 0xF4: General Control 5 */
-	volatile uint8_t GPIO_GCR5;
-	/* 0xF5: General Control 6 */
-	volatile uint8_t GPIO_GCR6;
-	/* 0xF6: General Control 7 */
-	volatile uint8_t GPIO_GCR7;
-	/* 0xF7: General Control 8 */
-	volatile uint8_t GPIO_GCR8;
-	/* 0xF8: General Control 9 */
-	volatile uint8_t GPIO_GCR9;
-	/* 0xF9: General Control 10 */
-	volatile uint8_t GPIO_GCR10;
-	/* 0xFA: General Control 11 */
-	volatile uint8_t GPIO_GCR11;
-	/* 0xFB: General Control 12 */
-	volatile uint8_t GPIO_GCR12;
-	/* 0xFC: General Control 13 */
-	volatile uint8_t GPIO_GCR13;
-	/* 0xFD: General Control 14 */
-	volatile uint8_t GPIO_GCR14;
-	/* 0xFE: General Control 15 */
-	volatile uint8_t GPIO_GCR15;
-	/* 0xFF: Power Good Watch Control */
-	volatile uint8_t GPIO_PGWCR;
-};
-#elif CONFIG_SOC_IT8XXX2_REG_SET_V2
-struct gpio_it8xxx2_regs {
-	/* 0x00: General Control */
-	volatile uint8_t GPIO_GCR;
-	/* 0x01-0x0F: Reserved1 */
-	volatile uint8_t reserved1[15];
-	/* 0x10: General Control 1 */
-	volatile uint8_t GPIO_GCR1;
-	/* 0x11: General Control 2 */
-	volatile uint8_t GPIO_GCR2;
-	/* 0x12: General Control 3 */
-	volatile uint8_t GPIO_GCR3;
-	/* 0x13: General Control 4 */
-	volatile uint8_t GPIO_GCR4;
-	/* 0x14: General Control 5 */
-	volatile uint8_t GPIO_GCR5;
-	/* 0x15: General Control 6 */
-	volatile uint8_t GPIO_GCR6;
-	/* 0x16: General Control 7 */
-	volatile uint8_t GPIO_GCR7;
-	/* 0x17: General Control 8 */
-	volatile uint8_t GPIO_GCR8;
-	/* 0x18: General Control 9 */
-	volatile uint8_t GPIO_GCR9;
-	/* 0x19: General Control 10 */
-	volatile uint8_t GPIO_GCR10;
-	/* 0x1A: General Control 11 */
-	volatile uint8_t GPIO_GCR11;
-	/* 0x1B: General Control 12 */
-	volatile uint8_t GPIO_GCR12;
-	/* 0x1C: General Control 13 */
-	volatile uint8_t GPIO_GCR13;
-	/* 0x1D: General Control 14 */
-	volatile uint8_t GPIO_GCR14;
-	/* 0x1E: General Control 15 */
-	volatile uint8_t GPIO_GCR15;
-	/* 0x1F: Power Good Watch Control */
-	volatile uint8_t GPIO_PGWCR;
-	/* 0x20: General Control 16 */
-	volatile uint8_t GPIO_GCR16;
-	/* 0x21: General Control 17 */
-	volatile uint8_t GPIO_GCR17;
-	/* 0x22: General Control 18 */
-	volatile uint8_t GPIO_GCR18;
-	/* 0x23: Reserved2 */
-	volatile uint8_t reserved2;
-	/* 0x24: General Control 19 */
-	volatile uint8_t GPIO_GCR19;
-	/* 0x25: Reserved3 */
-	volatile uint8_t reserved3;
-	/* 0x26: General Control 21 */
-	volatile uint8_t GPIO_GCR21;
-	/* 0x27-0x28: Reserved4 */
-	volatile uint8_t reserved4[2];
-	/* 0x29: General Control 24 */
-	volatile uint8_t GPIO_GCR24;
-	/* 0x2A-0x2C: Reserved5 */
-	volatile uint8_t reserved5[3];
-	/* 0x2D: General Control 30 */
-	volatile uint8_t GPIO_GCR30;
-	/* 0x2E: General Control 29 */
-	volatile uint8_t GPIO_GCR29;
-};
-
-/* GPIO register fields */
-/* 0x16: General Control 7 */
-#define IT8XXX2_GPIO_SMB2PS                BIT(7)
-#define IT8XXX2_GPIO_SMB3PS                BIT(6)
-#define IT8XXX2_GPIO_SMB5PS                BIT(5)
-
-#endif
-#endif /* !__ASSEMBLER__ */
-
-/* GPIO register fields */
-/* 0x00: General Control */
-#define IT8XXX2_GPIO_LPCRSTEN              (BIT(2) | BIT(1))
-#define IT8XXX2_GPIO_GCR_ESPI_RST_D2       0x2
-#define IT8XXX2_GPIO_GCR_ESPI_RST_POS      1
-#define IT8XXX2_GPIO_GCR_ESPI_RST_EN_MASK  (0x3 << IT8XXX2_GPIO_GCR_ESPI_RST_POS)
-/* 0xF0: General Control 1 */
-#define IT8XXX2_GPIO_U2CTRL_SIN1_SOUT1_EN  BIT(2)
-#define IT8XXX2_GPIO_U1CTRL_SIN0_SOUT0_EN  BIT(0)
-/* 0xE6: General Control 21 */
-#define IT8XXX2_GPIO_GPH1VS                BIT(1)
-#define IT8XXX2_GPIO_GPH2VS                BIT(0)
-
-#define KSIX_KSOX_KBS_GPIO_MODE     BIT(7)
-#define KSIX_KSOX_GPIO_OUTPUT       BIT(6)
-#define KSIX_KSOX_GPIO_PULLUP       BIT(2)
-#define KSIX_KSOX_GPIO_PULLDOWN     BIT(1)
-
-#define GPCR_PORT_PIN_MODE_INPUT    BIT(7)
-#define GPCR_PORT_PIN_MODE_OUTPUT   BIT(6)
-#define GPCR_PORT_PIN_MODE_PULLUP   BIT(2)
-#define GPCR_PORT_PIN_MODE_PULLDOWN BIT(1)
-
-/*
- * If both PULLUP and PULLDOWN are set to 1b, the corresponding port would be
- * configured as tri-state.
- */
-#define GPCR_PORT_PIN_MODE_TRISTATE	(GPCR_PORT_PIN_MODE_INPUT |  \
-					 GPCR_PORT_PIN_MODE_PULLUP | \
-					 GPCR_PORT_PIN_MODE_PULLDOWN)
-
-/* --- GPIO --- */
-#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
-#define IT8XXX2_GPIO_BASE  0x00F01600
-
-#define IT8XXX2_GPIO_GCRX(offset) ECREG(IT8XXX2_GPIO_BASE + (offset))
-#define IT8XXX2_GPIO_GCR25_OFFSET 0xd1
-#define IT8XXX2_GPIO_GCR26_OFFSET 0xd2
-#define IT8XXX2_GPIO_GCR27_OFFSET 0xd3
-#define IT8XXX2_GPIO_GCR28_OFFSET 0xd4
-#define IT8XXX2_GPIO_GCR31_OFFSET 0xd5
-#define IT8XXX2_GPIO_GCR32_OFFSET 0xd6
-#define IT8XXX2_GPIO_GCR33_OFFSET 0xd7
-#define IT8XXX2_GPIO_GCR19_OFFSET 0xe4
-#define IT8XXX2_GPIO_GCR20_OFFSET 0xe5
-#define IT8XXX2_GPIO_GCR21_OFFSET 0xe6
-#define IT8XXX2_GPIO_GCR22_OFFSET 0xe7
-#define IT8XXX2_GPIO_GCR23_OFFSET 0xe8
-#define IT8XXX2_GPIO_GCR24_OFFSET 0xe9
-#define IT8XXX2_GPIO_GCR30_OFFSET 0xed
-#define IT8XXX2_GPIO_GCR29_OFFSET 0xee
-#endif
-
-/*
- * TODO: use pinctrl node instead of following register declarations
- *       to fix in tcpm\it83xx_pd.h.
- */
-#define IT8XXX2_GPIO2_BASE 0x00F03E00
-
-#define IT8XXX2_GPIO_GPCRP0     ECREG(IT8XXX2_GPIO2_BASE + 0x18)
-#define IT8XXX2_GPIO_GPCRP1     ECREG(IT8XXX2_GPIO2_BASE + 0x19)
-
-
-/**
- *
- * (19xxh) Analog to Digital Converter (ADC) registers
- *
- */
-#ifndef __ASSEMBLER__
-
-/* Data structure to define ADC channel 13-16 control registers. */
-struct adc_vchs_ctrl_t {
-	/* 0x60: Voltage Channel Control */
-	volatile uint8_t VCHCTL;
-	/* 0x61: Voltage Channel Data Buffer MSB */
-	volatile uint8_t VCHDATM;
-	/* 0x62: Voltage Channel Data Buffer LSB */
-	volatile uint8_t VCHDATL;
-};
-
-struct adc_it8xxx2_regs {
-	/* 0x00: ADC Status */
-	volatile uint8_t ADCSTS;
-	/* 0x01: ADC Configuration */
-	volatile uint8_t ADCCFG;
-	/* 0x02: ADC Clock Control */
-	volatile uint8_t ADCCTL;
-	/* 0x03: General Control */
-	volatile uint8_t ADCGCR;
-	/* 0x04: Voltage Channel 0 Control */
-	volatile uint8_t VCH0CTL;
-	/* 0x05: Calibration Data Control */
-	volatile uint8_t KDCTL;
-	/* 0x06-0x17: Reserved1 */
-	volatile uint8_t reserved1[18];
-	/* 0x18: Voltage Channel 0 Data Buffer LSB */
-	volatile uint8_t VCH0DATL;
-	/* 0x19: Voltage Channel 0 Data Buffer MSB */
-	volatile uint8_t VCH0DATM;
-	/* 0x1a-0x43: Reserved2 */
-	volatile uint8_t reserved2[42];
-	/* 0x44: ADC Data Valid Status */
-	volatile uint8_t ADCDVSTS;
-	/* 0x45-0x54: Reserved2-1 */
-	volatile uint8_t reserved2_1[16];
-	/* 0x55: ADC Input Voltage Mapping Full-Scale Code Selection 1 */
-	volatile uint8_t ADCIVMFSCS1;
-	/* 0x56: ADC Input Voltage Mapping Full-Scale Code Selection 2 */
-	volatile uint8_t ADCIVMFSCS2;
-	/* 0x57: ADC Input Voltage Mapping Full-Scale Code Selection 3 */
-	volatile uint8_t ADCIVMFSCS3;
-	/* 0x58-0x5f: Reserved3 */
-	volatile uint8_t reserved3[8];
-	/* 0x60-0x6b: ADC channel 13~16 controller */
-	struct adc_vchs_ctrl_t adc_vchs_ctrl[4];
-	/* 0x6c: ADC Data Valid Status 2 */
-	volatile uint8_t ADCDVSTS2;
-	/* 0x6d-0xef: Reserved4 */
-	volatile uint8_t reserved4[131];
-	/* 0xf0: ADC Clock Control Register 1 */
-	volatile uint8_t ADCCTL1;
-};
-#endif /* !__ASSEMBLER__ */
-
-/* ADC conversion time select 1 */
-#define IT8XXX2_ADC_ADCCTS1			BIT(7)
-/* Analog accuracy initialization */
-#define IT8XXX2_ADC_AINITB			BIT(3)
-/* ADC conversion time select 0 */
-#define IT8XXX2_ADC_ADCCTS0			BIT(5)
-/* ADC module enable */
-#define IT8XXX2_ADC_ADCEN			BIT(0)
-/* ADC data buffer keep enable */
-#define IT8XXX2_ADC_DBKEN			BIT(7)
-/* W/C data valid flag */
-#define IT8XXX2_ADC_DATVAL			BIT(7)
-/* Data valid interrupt of adc */
-#define IT8XXX2_ADC_INTDVEN			BIT(5)
-/* Voltage channel enable (Channel 4~7 and 13~16) */
-#define IT8XXX2_ADC_VCHEN			BIT(4)
-/* Automatic hardware calibration enable */
-#define IT8XXX2_ADC_AHCE			BIT(7)
-/* 0x046, 0x049, 0x04c, 0x06e, 0x071, 0x074: Voltage comparator x control */
-#define IT8XXX2_VCMP_CMPEN			BIT(7)
-#define IT8XXX2_VCMP_CMPINTEN			BIT(6)
-#define IT8XXX2_VCMP_GREATER_THRESHOLD		BIT(5)
-#define IT8XXX2_VCMP_EDGE_TRIGGER		BIT(4)
-#define IT8XXX2_VCMP_GPIO_ACTIVE_LOW		BIT(3)
-/* 0x077~0x07c: Voltage comparator x channel select MSB */
-#define IT8XXX2_VCMP_VCMPXCSELM			BIT(0)
-
-/**
- *
- * (1Exxh) Clock and Power Management (ECPM) registers
- *
- */
-#define IT8XXX2_ECPM_BASE  0x00F01E00
-
-#ifndef __ASSEMBLER__
-enum chip_pll_mode {
-	CHIP_PLL_DOZE = 0,
-	CHIP_PLL_SLEEP = 1,
-	CHIP_PLL_DEEP_DOZE = 3,
-};
-#endif
-/*
- * TODO: use ecpm_it8xxx2_regs instead of following register declarations
- *       to fix in soc.c.
- */
-#define IT8XXX2_ECPM_PLLCTRL    ECREG(IT8XXX2_ECPM_BASE + 0x03)
-#define IT8XXX2_ECPM_AUTOCG     ECREG(IT8XXX2_ECPM_BASE + 0x04)
-#define IT8XXX2_ECPM_CGCTRL3R   ECREG(IT8XXX2_ECPM_BASE + 0x05)
-#define IT8XXX2_ECPM_PLLFREQR   ECREG(IT8XXX2_ECPM_BASE + 0x06)
-#define IT8XXX2_ECPM_PLLCSS     ECREG(IT8XXX2_ECPM_BASE + 0x08)
-#define IT8XXX2_ECPM_SCDCR0     ECREG(IT8XXX2_ECPM_BASE + 0x0c)
-#define IT8XXX2_ECPM_SCDCR1     ECREG(IT8XXX2_ECPM_BASE + 0x0d)
-#define IT8XXX2_ECPM_SCDCR2     ECREG(IT8XXX2_ECPM_BASE + 0x0e)
-#define IT8XXX2_ECPM_SCDCR3     ECREG(IT8XXX2_ECPM_BASE + 0x0f)
-#define IT8XXX2_ECPM_SCDCR4     ECREG(IT8XXX2_ECPM_BASE + 0x10)
-#define IT8XXX2_ECPM_PFACC0R    ECREG(IT8XXX2_ECPM_BASE + 0x20)
-#define IT8XXX2_ECPM_PFACC1R    ECREG(IT8XXX2_ECPM_BASE + 0x21)
-#define IT8XXX2_ECPM_PFACC2R    ECREG(IT8XXX2_ECPM_BASE + 0x40)
-#define IT8XXX2_ECPM_LCOTF2     ECREG(IT8XXX2_ECPM_BASE + 0x54)
-#define IT8XXX2_ECPM_LCOCR      ECREG(IT8XXX2_ECPM_BASE + 0x55)
-#define IT8XXX2_ECPM_LCOCR1     ECREG(IT8XXX2_ECPM_BASE + 0x57)
-
-/*
- * The count number of the counter for 25 ms register.
- * The 25 ms register is calculated by (count number *1.024 kHz).
- */
-
-#define I2C_CLK_LOW_TIMEOUT		255 /* ~=249 ms */
-
-/**
- *
- * (1Cxxh) SMBus Interface (SMB) registers
- *
- */
-#define IT8XXX2_SMB_BASE            0x00F01C00
-#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
-#define IT8XXX2_SMB_4P7USL          ECREG(IT8XXX2_SMB_BASE + 0x00)
-#define IT8XXX2_SMB_4P0USL          ECREG(IT8XXX2_SMB_BASE + 0x01)
-#define IT8XXX2_SMB_300NS           ECREG(IT8XXX2_SMB_BASE + 0x02)
-#define IT8XXX2_SMB_250NS           ECREG(IT8XXX2_SMB_BASE + 0x03)
-#define IT8XXX2_SMB_25MS            ECREG(IT8XXX2_SMB_BASE + 0x04)
-#define IT8XXX2_SMB_45P3USL         ECREG(IT8XXX2_SMB_BASE + 0x05)
-#define IT8XXX2_SMB_45P3USH         ECREG(IT8XXX2_SMB_BASE + 0x06)
-#define IT8XXX2_SMB_4P7A4P0H        ECREG(IT8XXX2_SMB_BASE + 0x07)
-#define IT8XXX2_SMB_SLVISELR        ECREG(IT8XXX2_SMB_BASE + 0x08)
-#define IT8XXX2_SMB_SCLKTS(ch)      ECREG(IT8XXX2_SMB_BASE + 0x09 + ch)
-#define IT8XXX2_SMB_MSTFCTRL1       ECREG(IT8XXX2_SMB_BASE + 0x0D)
-#define IT8XXX2_SMB_MSTFSTS1        ECREG(IT8XXX2_SMB_BASE + 0x0E)
-#define IT8XXX2_SMB_MSTFCTRL2       ECREG(IT8XXX2_SMB_BASE + 0x0F)
-#define IT8XXX2_SMB_MSTFSTS2        ECREG(IT8XXX2_SMB_BASE + 0x10)
-#define IT8XXX2_SMB_SMB45CHS        ECREG(IT8XXX2_SMB_BASE + 0x11)
-#define IT8XXX2_SMB_I2CW2RF         ECREG(IT8XXX2_SMB_BASE + 0x12)
-#define IT8XXX2_SMB_IWRFISTA        ECREG(IT8XXX2_SMB_BASE + 0x13)
-#define IT8XXX2_SMB_SMB01CHS        ECREG(IT8XXX2_SMB_BASE + 0x20)
-#define IT8XXX2_SMB_SMB23CHS        ECREG(IT8XXX2_SMB_BASE + 0x21)
-#define IT8XXX2_SMB_SFFCTL          ECREG(IT8XXX2_SMB_BASE + 0x55)
-#define IT8XXX2_SMB_HOSTA(base)     ECREG(base + 0x00)
-#define IT8XXX2_SMB_HOCTL(base)     ECREG(base + 0x01)
-#define IT8XXX2_SMB_HOCMD(base)     ECREG(base + 0x02)
-#define IT8XXX2_SMB_TRASLA(base)    ECREG(base + 0x03)
-#define IT8XXX2_SMB_D0REG(base)     ECREG(base + 0x04)
-#define IT8XXX2_SMB_D1REG(base)     ECREG(base + 0x05)
-#define IT8XXX2_SMB_HOBDB(base)     ECREG(base + 0x06)
-#define IT8XXX2_SMB_PECERC(base)    ECREG(base + 0x07)
-#define IT8XXX2_SMB_SMBPCTL(base)   ECREG(base + 0x0A)
-#define IT8XXX2_SMB_HOCTL2(base)    ECREG(base + 0x10)
-#elif CONFIG_SOC_IT8XXX2_REG_SET_V2
-#define IT8XXX2_SMB_SLVISEL         ECREG(IT8XXX2_SMB_BASE + 0x08)
-#define IT8XXX2_SMB_SMB01CHS        ECREG(IT8XXX2_SMB_BASE + 0x09)
-#define IT8XXX2_SMB_SMB23CHS        ECREG(IT8XXX2_SMB_BASE + 0x0A)
-#define IT8XXX2_SMB_SMB45CHS        ECREG(IT8XXX2_SMB_BASE + 0x0B)
-#define IT8XXX2_SMB_SCLKTS_BRGS     ECREG(IT8XXX2_SMB_BASE + 0x80)
-#define IT8XXX2_SMB_SCLKTS_BRGM     ECREG(IT8XXX2_SMB_BASE + 0x81)
-#define IT8XXX2_SMB_CHSBRG          ECREG(IT8XXX2_SMB_BASE + 0x82)
-#define IT8XXX2_SMB_CHSMOT          ECREG(IT8XXX2_SMB_BASE + 0x83)
-
-/* SMBus register fields */
-/* 0x80: SMCLK Timing Setting Register Bridge Slave */
-#define IT8XXX2_SMB_PREDEN            BIT(7)
-#endif
-
-/**
- * Enhanced SMBus/I2C Interface
- * Ch_D: 0x00F03680, Ch_E: 0x00F03500, Ch_F: 0x00F03580
- * Ch_D: ch = 0x03, Ch_E: ch = 0x00, Ch_F: ch = 0x01
- */
-#define IT8XXX2_I2C_DRR(base)         ECREG(base + 0x00)
-#define IT8XXX2_I2C_PSR(base)         ECREG(base + 0x01)
-#define IT8XXX2_I2C_HSPR(base)        ECREG(base + 0x02)
-#define IT8XXX2_I2C_STR(base)         ECREG(base + 0x03)
-#define IT8XXX2_I2C_DHTR(base)        ECREG(base + 0x04)
-#define IT8XXX2_I2C_TOR(base)         ECREG(base + 0x05)
-#define IT8XXX2_I2C_DTR(base)         ECREG(base + 0x08)
-#define IT8XXX2_I2C_CTR(base)         ECREG(base + 0x09)
-#define IT8XXX2_I2C_CTR1(base)        ECREG(base + 0x0A)
-#define IT8XXX2_I2C_BYTE_CNT_H(base)  ECREG(base + 0x0B)
-#define IT8XXX2_I2C_BYTE_CNT_L(base)  ECREG(base + 0x0C)
-#define IT8XXX2_I2C_IRQ_ST(base)      ECREG(base + 0x0D)
-#define IT8XXX2_I2C_IDR(base)         ECREG(base + 0x06)
-#define IT8XXX2_I2C_TOS(base)         ECREG(base + 0x07)
-#define IT8XXX2_I2C_SLV_NUM_H(base)   ECREG(base + 0x10)
-#define IT8XXX2_I2C_SLV_NUM_L(base)   ECREG(base + 0x11)
-#define IT8XXX2_I2C_STR2(base)        ECREG(base + 0x12)
-#define IT8XXX2_I2C_NST(base)         ECREG(base + 0x13)
-#define IT8XXX2_I2C_TO_ARB_ST(base)   ECREG(base + 0x18)
-#define IT8XXX2_I2C_ERR_ST(base)      ECREG(base + 0x19)
-#define IT8XXX2_I2C_FST(base)         ECREG(base + 0x1B)
-#define IT8XXX2_I2C_EM(base)          ECREG(base + 0x1C)
-#define IT8XXX2_I2C_MODE_SEL(base)    ECREG(base + 0x1D)
-#define IT8XXX2_I2C_IDR2(base)        ECREG(base + 0x1F)
-#define IT8XXX2_I2C_CTR2(base)        ECREG(base + 0x20)
-#define IT8XXX2_I2C_RAMHA(base)       ECREG(base + 0x23)
-#define IT8XXX2_I2C_RAMLA(base)       ECREG(base + 0x24)
-#define IT8XXX2_I2C_RAMHA2(base)      ECREG(base + 0x2C)
-#define IT8XXX2_I2C_RAMLA2(base)      ECREG(base + 0x2D)
-#define IT8XXX2_I2C_CMD_ADDH(base)    ECREG(base + 0x25)
-#define IT8XXX2_I2C_CMD_ADDL(base)    ECREG(base + 0x26)
-#define IT8XXX2_I2C_RAMH2A(base)      ECREG(base + 0x50)
-#define IT8XXX2_I2C_CMD_ADDH2(base)   ECREG(base + 0x52)
-
-/* SMBus/I2C register fields */
-/* 0x09-0xB: SMCLK Timing Setting */
-#define IT8XXX2_SMB_SMCLKS_1M         4
-#define IT8XXX2_SMB_SMCLKS_400K       3
-#define IT8XXX2_SMB_SMCLKS_100K       2
-#define IT8XXX2_SMB_SMCLKS_50K        1
-
-/* 0x0E: SMBus FIFO Status 1 */
-#define IT8XXX2_SMB_FIFO1_EMPTY       BIT(7)
-#define IT8XXX2_SMB_FIFO1_FULL        BIT(6)
-/* 0x0D: SMBus FIFO Control 1 */
-/* 0x0F: SMBus FIFO Control 2 */
-#define IT8XXX2_SMB_BLKDS             BIT(4)
-#define IT8XXX2_SMB_FFEN              BIT(3)
-#define IT8XXX2_SMB_FFCHSEL2_B        0
-#define IT8XXX2_SMB_FFCHSEL2_C        BIT(0)
-/* 0x10: SMBus FIFO Status 2 */
-#define IT8XXX2_SMB_FIFO2_EMPTY       BIT(7)
-#define IT8XXX2_SMB_FIFO2_FULL        BIT(6)
-/* 0x12: I2C Wr To Rd FIFO */
-#define IT8XXX2_SMB_MAIF              BIT(7)
-#define IT8XXX2_SMB_MBCIF             BIT(6)
-#define IT8XXX2_SMB_MCIFI             BIT(2)
-#define IT8XXX2_SMB_MBIFI             BIT(1)
-#define IT8XXX2_SMB_MAIFI             BIT(0)
-/* 0x13: I2C Wr To Rd FIFO Interrupt Status */
-#define IT8XXX2_SMB_MCIFID            BIT(2)
-#define IT8XXX2_SMB_MAIFID            BIT(0)
-/* 0x41 0x81 0xC1: Host Control */
-#define IT8XXX2_SMB_SRT               BIT(6)
-#define IT8XXX2_SMB_LABY              BIT(5)
-#define IT8XXX2_SMB_SMCD_EXTND        BIT(4) | BIT(3) | BIT(2)
-#define IT8XXX2_SMB_KILL              BIT(1)
-#define IT8XXX2_SMB_INTREN            BIT(0)
-/* 0x43 0x83 0xC3: Transmit Slave Address */
-#define IT8XXX2_SMB_DIR               BIT(0)
-/* 0x4A 0x8A 0xCA: SMBus Pin Control */
-#define IT8XXX2_SMB_SMBDCS            BIT(1)
-#define IT8XXX2_SMB_SMBCS             BIT(0)
-/* 0x50 0x90 0xD0: Host Control 2 */
-#define IT8XXX2_SMB_SMD_TO_EN         BIT(4)
-#define IT8XXX2_SMB_I2C_SW_EN         BIT(3)
-#define IT8XXX2_SMB_I2C_SW_WAIT       BIT(2)
-#define IT8XXX2_SMB_I2C_EN            BIT(1)
-#define IT8XXX2_SMB_SMHEN             BIT(0)
-/* 0x55: Slave A FIFO Control */
-#define IT8XXX2_SMB_HSAPE             BIT(1)
-/* 0x03: Status Register */
-#define IT8XXX2_I2C_BYTE_DONE         BIT(7)
-#define IT8XXX2_I2C_RW                BIT(2)
-#define IT8XXX2_I2C_INT_PEND          BIT(1)
-/* 0x04: Data Hold Time */
-#define IT8XXX2_I2C_SOFT_RST          BIT(7)
-/* 0x07: Time Out Status */
-#define IT8XXX2_I2C_CLK_STRETCH       BIT(7)
-#define IT8XXX2_I2C_SCL_IN            BIT(2)
-#define IT8XXX2_I2C_SDA_IN            BIT(0)
-/* 0x09: Control Register */
-#define IT8XXX2_I2C_INT_EN            BIT(6)
-#define IT8XXX2_I2C_ACK               BIT(3)
-#define IT8XXX2_I2C_HALT              BIT(0)
-/* 0x0A: Control 1 */
-#define IT8XXX2_I2C_COMQ_EN           BIT(7)
-#define IT8XXX2_I2C_MDL_EN            BIT(1)
-/* 0x0C: Byte count */
-#define IT8XXX2_I2C_DMA_ADDR_RELOAD   BIT(5)
-#define IT8XXX2_I2C_BYTE_CNT_ENABLE   BIT(3)
-/* 0x0D: Interrupt Status */
-#define IT8XXX2_I2C_CNT_HOLD          BIT(4)
-#define IT8XXX2_I2C_IDW_CLR           BIT(3)
-#define IT8XXX2_I2C_IDR_CLR           BIT(2)
-#define IT8XXX2_I2C_SLVDATAFLG        BIT(1)
-#define IT8XXX2_I2C_P_CLR             BIT(0)
-/* 0x13: Nack Status */
-#define IT8XXX2_I2C_NST_CNS           BIT(7)
-#define IT8XXX2_I2C_NST_ID_NACK       BIT(3)
-/* 0x18: Timeout and Arbiter Status */
-#define IT8XXX2_I2C_SCL_TIMEOUT_EN    BIT(7)
-#define IT8XXX2_I2C_SDA_TIMEOUT_EN    BIT(6)
-/* 0x19: Error Status */
-#define IT8XXX2_I2C_ERR_ST_DEV1_EIRQ  BIT(0)
-/* 0x1B: Finish Status */
-#define IT8XXX2_I2C_FST_DEV1_IRQ      BIT(4)
-/* 0x1C: Error Mask */
-#define IT8XXX2_I2C_EM_DEV1_IRQ       BIT(4)
-
-/*
- * TODO: use gctrl_it8xxx2_regs instead of following register declarations
- *       to fix in cros_flash_it8xxx2.c, cros_shi_it8xxx2.c and tcpm\it8xxx2.c.
- */
-/* --- General Control (GCTRL) --- */
-#define IT83XX_GCTRL_BASE 0x00F02000
-
-#define IT83XX_GCTRL_CHIPID1         ECREG(IT83XX_GCTRL_BASE + 0x85)
-#define IT83XX_GCTRL_CHIPID2         ECREG(IT83XX_GCTRL_BASE + 0x86)
-#define IT83XX_GCTRL_CHIPVER         ECREG(IT83XX_GCTRL_BASE + 0x02)
-#define IT83XX_GCTRL_MCCR3           ECREG(IT83XX_GCTRL_BASE + 0x20)
-#define IT83XX_GCTRL_SPISLVPFE             BIT(6)
-#define IT83XX_GCTRL_EWPR0PFH(i)     ECREG(IT83XX_GCTRL_BASE + 0x60 + i)
-#define IT83XX_GCTRL_EWPR0PFD(i)     ECREG(IT83XX_GCTRL_BASE + 0xA0 + i)
-#define IT83XX_GCTRL_EWPR0PFEC(i)    ECREG(IT83XX_GCTRL_BASE + 0xC0 + i)
-
-/*
- * TODO: use spisc_it8xxx2_regs instead of following register declarations
- *       to fix in cros_shi_it8xxx2.c.
- */
-/* Serial Peripheral Interface (SPI) */
-#define IT83XX_SPI_BASE  0x00F03A00
-
-#define IT83XX_SPI_SPISGCR           ECREG(IT83XX_SPI_BASE + 0x00)
-#define IT83XX_SPI_SPISCEN                 BIT(0)
-#define IT83XX_SPI_TXRXFAR           ECREG(IT83XX_SPI_BASE + 0x01)
-#define IT83XX_SPI_CPURXF2A                BIT(4)
-#define IT83XX_SPI_CPURXF1A                BIT(3)
-#define IT83XX_SPI_CPUTFA                  BIT(1)
-#define IT83XX_SPI_TXFCR             ECREG(IT83XX_SPI_BASE + 0x02)
-#define IT83XX_SPI_TXFCMR                  BIT(2)
-#define IT83XX_SPI_TXFR                    BIT(1)
-#define IT83XX_SPI_TXFS                    BIT(0)
-#define IT83XX_SPI_GCR2              ECREG(IT83XX_SPI_BASE + 0x03)
-#define IT83XX_SPI_RXF2OC                  BIT(4)
-#define IT83XX_SPI_RXF1OC                  BIT(3)
-#define IT83XX_SPI_RXFAR                   BIT(0)
-#define IT83XX_SPI_IMR               ECREG(IT83XX_SPI_BASE + 0x04)
-#define IT83XX_SPI_RX_FIFO_FULL            BIT(7)
-#define IT83XX_SPI_RX_REACH                BIT(5)
-#define IT83XX_SPI_EDIM                    BIT(2)
-#define IT83XX_SPI_ISR               ECREG(IT83XX_SPI_BASE + 0x05)
-#define IT83XX_SPI_TXFSR             ECREG(IT83XX_SPI_BASE + 0x06)
-#define IT83XX_SPI_ENDDETECTINT            BIT(2)
-#define IT83XX_SPI_RXFSR             ECREG(IT83XX_SPI_BASE + 0x07)
-#define IT83XX_SPI_RXFFSM                  (BIT(4) | BIT(3))
-#define IT83XX_SPI_RXF2FS                  BIT(2)
-#define IT83XX_SPI_RXF1FS                  BIT(1)
-#define IT83XX_SPI_SPISRDR           ECREG(IT83XX_SPI_BASE + 0x0b)
-#define IT83XX_SPI_CPUWTFDB0         ECREG_u32(IT83XX_SPI_BASE + 0x08)
-#define IT83XX_SPI_FCR               ECREG(IT83XX_SPI_BASE + 0x09)
-#define IT83XX_SPI_SPISRTXF                BIT(2)
-#define IT83XX_SPI_RXFR                    BIT(1)
-#define IT83XX_SPI_RXFCMR                  BIT(0)
-#define IT83XX_SPI_RXFRDRB0          ECREG_u32(IT83XX_SPI_BASE + 0x0C)
-#define IT83XX_SPI_FTCB0R            ECREG(IT83XX_SPI_BASE + 0x18)
-#define IT83XX_SPI_FTCB1R            ECREG(IT83XX_SPI_BASE + 0x19)
-#define IT83XX_SPI_TCCB0             ECREG(IT83XX_SPI_BASE + 0x1A)
-#define IT83XX_SPI_TCCB1             ECREG(IT83XX_SPI_BASE + 0x1B)
-#define IT83XX_SPI_HPR2              ECREG(IT83XX_SPI_BASE + 0x1E)
-#define IT83XX_SPI_EMMCBMR           ECREG(IT83XX_SPI_BASE + 0x21)
-#define IT83XX_SPI_EMMCABM                 BIT(1) /* eMMC Alternative Boot Mode */
-#define IT83XX_SPI_RX_VLISMR         ECREG(IT83XX_SPI_BASE + 0x26)
-#define IT83XX_SPI_RVLIM                   BIT(0)
-#define IT83XX_SPI_RX_VLISR          ECREG(IT83XX_SPI_BASE + 0x27)
-#define IT83XX_SPI_RVLI                    BIT(0)
-
-/**
- *
- * (20xxh) General Control (GCTRL) registers
- *
- */
-#define GCTRL_IT8XXX2_REGS_BASE \
-	((struct gctrl_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gctrl)))
-
-#ifndef __ASSEMBLER__
-struct gctrl_it8xxx2_regs {
-	/* 0x00-0x01: Reserved_00_01 */
-	volatile uint8_t reserved_00_01[2];
-	/* 0x02: Chip Version */
-	volatile uint8_t GCTRL_ECHIPVER;
-	/* 0x03: DBGR Operate Status */
-	volatile uint8_t GCTRL_DBGROS;
-	/* 0x04-0x05: Reserved_04_05 */
-	volatile uint8_t reserved_04_05[2];
-	/* 0x06: Reset Status */
-	volatile uint8_t GCTRL_RSTS;
-	/* 0x07-0x09: Reserved_07_09 */
-	volatile uint8_t reserved_07_09[3];
-	/* 0x0A: Base Address Select */
-	volatile uint8_t GCTRL_BADRSEL;
-	/* 0x0B: Wait Next Clock Rising */
-	volatile uint8_t GCTRL_WNCKR;
-	/* 0x0C: reserved_0c */
-	volatile uint8_t reserved_0c;
-	/* 0x0D: Special Control 1 */
-	volatile uint8_t GCTRL_SPCTRL1;
-	/* 0x0E-0x0F: reserved_0e_0f */
-	volatile uint8_t reserved_0e_0f[2];
-	/* 0x10: Reset Control DMM */
-	volatile uint8_t GCTRL_RSTDMMC;
-	/* 0x11: Reset Control 4 */
-	volatile uint8_t GCTRL_RSTC4;
-	/* 0x12-0x1B: reserved_12_1b */
-	volatile uint8_t reserved_12_1b[10];
-	/* 0x1C: Special Control 4 */
-	volatile uint8_t GCTRL_SPCTRL4;
-	/* 0x1D-0x1F: reserved_1d_1f */
-	volatile uint8_t reserved_1d_1f[3];
-	/* 0x20: Memory Controller Configuration 3 */
-	volatile uint8_t GCTRL_MCCR3;
-	/* 0x21: Reset Control 5 */
-	volatile uint8_t GCTRL_RSTC5;
-	/* 0x22-0x2F: reserved_22_2f */
-	volatile uint8_t reserved_22_2f[14];
-	/* 0x30: Memory Controller Configuration */
-	volatile uint8_t GCTRL_MCCR;
-	/* 0x31: Externel ILM/DLM Size */
-	volatile uint8_t GCTRL_EIDSR;
-	/* 0x32: Reserved_32 */
-	volatile uint8_t reserved_32;
-	/* 0x33: Pin Multi-function Enable 2 */
-	volatile uint8_t gctrl_pmer2;
-	/* 0x34-0x36: Reserved_34_36 */
-	volatile uint8_t reserved_34_36[3];
-	/* 0x37: Eflash Protect Lock */
-	volatile uint8_t GCTRL_EPLR;
-	/* 0x38-0x40: Reserved_38_40 */
-	volatile uint8_t reserved_38_40[9];
-	/* 0x41: Interrupt Vector Table Base Address */
-	volatile uint8_t GCTRL_IVTBAR;
-	/* 0x42-0x43: Reserved_42_43 */
-	volatile uint8_t reserved_42_43[2];
-	/* 0x44: Memory Controller Configuration 2 */
-	volatile uint8_t GCTRL_MCCR2;
-	/* 0x45: Reserved_45 */
-	volatile uint8_t reserved_45;
-	/* 0x46: Pin Multi-function Enable 3 */
-	volatile uint8_t GCTRL_PMER3;
-	/* 0x47-0x4A: reserved_47_4a */
-	volatile uint8_t reserved_47_4a[4];
-	/* 0x4B: ETWD and UART Control */
-	volatile uint8_t GCTRL_ETWDUARTCR;
-	/* 0x4C: Wakeup MCU Control */
-	volatile uint8_t GCTRL_WMCR;
-	/* 0x4D-0x4F: reserved_4d_4f */
-	volatile uint8_t reserved_4d_4f[3];
-	/* 0x50: Port 80h/81h Status Register */
-	volatile uint8_t GCTRL_P80H81HSR;
-	/* 0x51: Port 80h Data Register */
-	volatile uint8_t GCTRL_P80HDR;
-	/* 0x52: Port 81h Data Register */
-	volatile uint8_t GCTRL_P81HDR;
-	/* 0x53: H2RAM Offset Register */
-	volatile uint8_t GCTRL_H2ROFSR;
-	/* 0x54-0x5C: reserved_54_5c */
-	volatile uint8_t reserved_54_5c[9];
-	/* 0x5D: RISCV ILM Configuration 0 */
-	volatile uint8_t GCTRL_RVILMCR0;
-	/* 0x5E-0x84: reserved_5e_84 */
-	volatile uint8_t reserved_5e_84[39];
-	/* 0x85: Chip ID Byte 1 */
-	volatile uint8_t GCTRL_ECHIPID1;
-	/* 0x86: Chip ID Byte 2 */
-	volatile uint8_t GCTRL_ECHIPID2;
-	/* 0x87: Chip ID Byte 3 */
-	volatile uint8_t GCTRL_ECHIPID3;
-};
-#endif /* !__ASSEMBLER__ */
-
-/* GCTRL register fields */
-/* 0x03: DBGR Operate Status */
-#define IT8XXX2_GCTRL_SMB_DBGR		BIT(0)
-/* 0x06: Reset Status */
-#define IT8XXX2_GCTRL_LRS		(BIT(1) | BIT(0))
-#define IT8XXX2_GCTRL_IWDTR		BIT(1)
-/* 0x0B: Wait Next 65K Rising */
-#define IT8XXX2_GCTRL_WN65K		0x00
-/* 0x10: Reset Control DMM */
-#define IT8XXX2_GCTRL_UART1SD		BIT(3)
-#define IT8XXX2_GCTRL_UART2SD		BIT(2)
-/* 0x11: Reset Control 4 */
-#define IT8XXX2_GCTRL_RPECI		BIT(4)
-#define IT8XXX2_GCTRL_RUART2		BIT(2)
-#define IT8XXX2_GCTRL_RUART1		BIT(1)
-/* 0x1C: Special Control 4 */
-#define IT8XXX2_GCTRL_LRSIWR		BIT(2)
-#define IT8XXX2_GCTRL_LRSIPWRSWTR	BIT(1)
-#define IT8XXX2_GCTRL_LRSIPGWR		BIT(0)
-/* 0x20: Memory Controller Configuration 3 */
-#define IT8XXX2_GCTRL_SPISLVPFE		BIT(6)
-/* 0x30: Memory Controller Configuration */
-#define IT8XXX2_GCTRL_USB_DEBUG_EN      BIT(7)
-#define IT8XXX2_GCTRL_ICACHE_RESET	BIT(4)
-/* 0x37: Eflash Protect Lock */
-#define IT8XXX2_GCTRL_EPLR_ENABLE	BIT(0)
-/* 0x46: Pin Multi-function Enable 3 */
-#define IT8XXX2_GCTRL_SMB3PSEL		BIT(6)
-#define IT8XXX2_GCTRL_SRAM_CRYPTO_USED	BIT(5)
-/* 0x4B: ETWD and UART Control */
-#define IT8XXX2_GCTRL_ETWD_HW_RST_EN	BIT(0)
-/* 0x5D: RISCV ILM Configuration 0 */
-#define IT8XXX2_GCTRL_ILM0_ENABLE	BIT(0)
-/* Accept Port 80h Cycle */
-#define IT8XXX2_GCTRL_ACP80		BIT(6)
-/* Accept Port 81h Cycle */
-#define IT8XXX2_GCTRL_ACP81		BIT(3)
-/* USB Debug Enable */
-#define IT8XXX2_GCTRL_MCCR_USB_EN	BIT(7)
-/* USB Pad Power-On Enable */
-#define IT8XXX2_GCTRL_PMER2_USB_PAD_EN	BIT(7)
-
-/*
- * VCC Detector Option.
- * bit[7-6] = 1: The VCC power status is treated as power-on.
- * The VCC supply of eSPI and related functions (EC2I, KBC, PMC and
- * PECI). It means VCC should be logic high before using these
- * functions, or firmware treats VCC logic high.
- */
-#define IT8XXX2_GCTRL_VCCDO_MASK	(BIT(6) | BIT(7))
-#define IT8XXX2_GCTRL_VCCDO_VCC_ON	BIT(6)
-/*
- * bit[3] = 0: The reset source of PNPCFG is RSTPNP bit in RSTCH
- * register and WRST#.
- */
-#define IT8XXX2_GCTRL_HGRST		BIT(3)
-/* bit[2] = 1: Enable global reset. */
-#define IT8XXX2_GCTRL_GRST		BIT(2)
-
-/**
- *
- * (22xxh) Battery-backed SRAM (BRAM) registers
- *
- */
-#ifndef __ASSEMBLER__
-/* Battery backed RAM indices. */
-#define BRAM_MAGIC_FIELD_OFFSET 0xbc
-enum bram_indices {
-
-	/* This field is used to indicate BRAM is valid or not. */
-	BRAM_IDX_VALID_FLAGS0 = BRAM_MAGIC_FIELD_OFFSET,
-	BRAM_IDX_VALID_FLAGS1,
-	BRAM_IDX_VALID_FLAGS2,
-	BRAM_IDX_VALID_FLAGS3
-};
-#endif /* !__ASSEMBLER__ */
-
-#ifndef __ASSEMBLER__
-/*
- * EC2I bridge registers
- */
-struct ec2i_regs {
-	/* 0x00: Indirect Host I/O Address Register */
-	volatile uint8_t IHIOA;
-	/* 0x01: Indirect Host Data Register */
-	volatile uint8_t IHD;
-	/* 0x02: Lock Super I/O Host Access Register */
-	volatile uint8_t LSIOHA;
-	/* 0x03: Super I/O Access Lock Violation Register */
-	volatile uint8_t SIOLV;
-	/* 0x04: EC to I-Bus Modules Access Enable Register */
-	volatile uint8_t IBMAE;
-	/* 0x05: I-Bus Control Register */
-	volatile uint8_t IBCTL;
-};
-
-/* Index list of the host interface registers of PNPCFG */
-enum host_pnpcfg_index {
-	/* Logical Device Number */
-	HOST_INDEX_LDN = 0x07,
-	/* Chip ID Byte 1 */
-	HOST_INDEX_CHIPID1 = 0x20,
-	/* Chip ID Byte 2 */
-	HOST_INDEX_CHIPID2 = 0x21,
-	/* Chip Version */
-	HOST_INDEX_CHIPVER = 0x22,
-	/* Super I/O Control */
-	HOST_INDEX_SIOCTRL = 0x23,
-	/* Super I/O IRQ Configuration */
-	HOST_INDEX_SIOIRQ = 0x25,
-	/* Super I/O General Purpose */
-	HOST_INDEX_SIOGP = 0x26,
-	/* Super I/O Power Mode */
-	HOST_INDEX_SIOPWR = 0x2D,
-	/* Depth 2 I/O Address */
-	HOST_INDEX_D2ADR = 0x2E,
-	/* Depth 2 I/O Data */
-	HOST_INDEX_D2DAT = 0x2F,
-	/* Logical Device Activate Register */
-	HOST_INDEX_LDA = 0x30,
-	/* I/O Port Base Address Bits [15:8] for Descriptor 0 */
-	HOST_INDEX_IOBAD0_MSB = 0x60,
-	/* I/O Port Base Address Bits [7:0] for Descriptor 0 */
-	HOST_INDEX_IOBAD0_LSB = 0x61,
-	/* I/O Port Base Address Bits [15:8] for Descriptor 1 */
-	HOST_INDEX_IOBAD1_MSB = 0x62,
-	/* I/O Port Base Address Bits [7:0] for Descriptor 1 */
-	HOST_INDEX_IOBAD1_LSB = 0x63,
-	/* Interrupt Request Number and Wake-Up on IRQ Enabled */
-	HOST_INDEX_IRQNUMX = 0x70,
-	/* Interrupt Request Type Select */
-	HOST_INDEX_IRQTP = 0x71,
-	/* DMA Channel Select 0 */
-	HOST_INDEX_DMAS0 = 0x74,
-	/* DMA Channel Select 1 */
-	HOST_INDEX_DMAS1 = 0x75,
-	/* Device Specific Logical Device Configuration 1 to 10 */
-	HOST_INDEX_DSLDC1 = 0xF0,
-	HOST_INDEX_DSLDC2 = 0xF1,
-	HOST_INDEX_DSLDC3 = 0xF2,
-	HOST_INDEX_DSLDC4 = 0xF3,
-	HOST_INDEX_DSLDC5 = 0xF4,
-	HOST_INDEX_DSLDC6 = 0xF5,
-	HOST_INDEX_DSLDC7 = 0xF6,
-	HOST_INDEX_DSLDC8 = 0xF7,
-	HOST_INDEX_DSLDC9 = 0xF8,
-	HOST_INDEX_DSLDC10 = 0xF9,
-};
-
-/* List of logical device number (LDN) assignments */
-enum logical_device_number {
-	/* Serial Port 1 */
-	LDN_UART1 = 0x01,
-	/* Serial Port 2 */
-	LDN_UART2 = 0x02,
-	/* System Wake-Up Control */
-	LDN_SWUC = 0x04,
-	/* KBC/Mouse Interface */
-	LDN_KBC_MOUSE = 0x05,
-	/* KBC/Keyboard Interface */
-	LDN_KBC_KEYBOARD = 0x06,
-	/* Consumer IR */
-	LDN_CIR = 0x0A,
-	/* Shared Memory/Flash Interface */
-	LDN_SMFI = 0x0F,
-	/* RTC-like Timer */
-	LDN_RTCT = 0x10,
-	/* Power Management I/F Channel 1 */
-	LDN_PMC1 = 0x11,
-	/* Power Management I/F Channel 2 */
-	LDN_PMC2 = 0x12,
-	/* Serial Peripheral Interface */
-	LDN_SSPI = 0x13,
-	/* Platform Environment Control Interface */
-	LDN_PECI = 0x14,
-	/* Power Management I/F Channel 3 */
-	LDN_PMC3 = 0x17,
-	/* Power Management I/F Channel 4 */
-	LDN_PMC4 = 0x18,
-	/* Power Management I/F Channel 5 */
-	LDN_PMC5 = 0x19,
-};
-
-/* Structure for initializing PNPCFG via ec2i. */
-struct ec2i_t {
-	/* index port */
-	enum host_pnpcfg_index index_port;
-	/* data port */
-	uint8_t data_port;
-};
-
-/* EC2I access index/data port */
-enum ec2i_access {
-	/* index port */
-	EC2I_ACCESS_INDEX = 0,
-	/* data port */
-	EC2I_ACCESS_DATA = 1,
-};
-
-/* EC to I-Bus Access Enabled */
-#define EC2I_IBCTL_CSAE  BIT(0)
-/* EC Read from I-Bus */
-#define EC2I_IBCTL_CRIB  BIT(1)
-/* EC Write to I-Bus */
-#define EC2I_IBCTL_CWIB  BIT(2)
-#define EC2I_IBCTL_CRWIB (EC2I_IBCTL_CRIB | EC2I_IBCTL_CWIB)
-
-/* PNPCFG Register EC Access Enable */
-#define EC2I_IBMAE_CFGAE BIT(0)
-
-/*
- * KBC registers
- */
-struct kbc_regs {
-	/* 0x00: KBC Host Interface Control Register */
-	volatile uint8_t KBHICR;
-	/* 0x01: Reserved1 */
-	volatile uint8_t reserved1;
-	/* 0x02: KBC Interrupt Control Register */
-	volatile uint8_t KBIRQR;
-	/* 0x03: Reserved2 */
-	volatile uint8_t reserved2;
-	/* 0x04: KBC Host Interface Keyboard/Mouse Status Register */
-	volatile uint8_t KBHISR;
-	/* 0x05: Reserved3 */
-	volatile uint8_t reserved3;
-	/* 0x06: KBC Host Interface Keyboard Data Output Register */
-	volatile uint8_t KBHIKDOR;
-	/* 0x07: Reserved4 */
-	volatile uint8_t reserved4;
-	/* 0x08: KBC Host Interface Mouse Data Output Register */
-	volatile uint8_t KBHIMDOR;
-	/* 0x09: Reserved5 */
-	volatile uint8_t reserved5;
-	/* 0x0a: KBC Host Interface Keyboard/Mouse Data Input Register */
-	volatile uint8_t KBHIDIR;
-};
-
-/* Output Buffer Full */
-#define KBC_KBHISR_OBF      BIT(0)
-/* Input Buffer Full */
-#define KBC_KBHISR_IBF      BIT(1)
-/* A2 Address (A2) */
-#define KBC_KBHISR_A2_ADDR  BIT(3)
-#define KBC_KBHISR_STS_MASK (KBC_KBHISR_OBF | KBC_KBHISR_IBF \
-						| KBC_KBHISR_A2_ADDR)
-
-/* Clear Output Buffer Full */
-#define KBC_KBHICR_COBF      BIT(6)
-/* IBF/OBF Clear Mode Enable */
-#define KBC_KBHICR_IBFOBFCME BIT(5)
-/* Input Buffer Full CPU Interrupt Enable */
-#define KBC_KBHICR_IBFCIE    BIT(3)
-/* Output Buffer Empty CPU Interrupt Enable */
-#define KBC_KBHICR_OBECIE    BIT(2)
-/* Output Buffer Full Mouse Interrupt Enable */
-#define KBC_KBHICR_OBFMIE    BIT(1)
-/* Output Buffer Full Keyboard Interrupt Enable */
-#define KBC_KBHICR_OBFKIE    BIT(0)
-
-/*
- * PMC registers
- */
-struct pmc_regs {
-	/* 0x00: Host Interface PM Channel 1 Status */
-	volatile uint8_t PM1STS;
-	/* 0x01: Host Interface PM Channel 1 Data Out Port */
-	volatile uint8_t PM1DO;
-	/* 0x02: Host Interface PM Channel 1 Data Out Port with SCI# */
-	volatile uint8_t PM1DOSCI;
-	/* 0x03: Host Interface PM Channel 1 Data Out Port with SMI# */
-	volatile uint8_t PM1DOSMI;
-	/* 0x04: Host Interface PM Channel 1 Data In Port */
-	volatile uint8_t PM1DI;
-	/* 0x05: Host Interface PM Channel 1 Data In Port with SCI# */
-	volatile uint8_t PM1DISCI;
-	/* 0x06: Host Interface PM Channel 1 Control */
-	volatile uint8_t PM1CTL;
-	/* 0x07: Host Interface PM Channel 1 Interrupt Control */
-	volatile uint8_t PM1IC;
-	/* 0x08: Host Interface PM Channel 1 Interrupt Enable */
-	volatile uint8_t PM1IE;
-	/* 0x09-0x0f: Reserved1 */
-	volatile uint8_t reserved1[7];
-	/* 0x10: Host Interface PM Channel 2 Status */
-	volatile uint8_t PM2STS;
-	/* 0x11: Host Interface PM Channel 2 Data Out Port */
-	volatile uint8_t PM2DO;
-	/* 0x12: Host Interface PM Channel 2 Data Out Port with SCI# */
-	volatile uint8_t PM2DOSCI;
-	/* 0x13: Host Interface PM Channel 2 Data Out Port with SMI# */
-	volatile uint8_t PM2DOSMI;
-	/* 0x14: Host Interface PM Channel 2 Data In Port */
-	volatile uint8_t PM2DI;
-	/* 0x15: Host Interface PM Channel 2 Data In Port with SCI# */
-	volatile uint8_t PM2DISCI;
-	/* 0x16: Host Interface PM Channel 2 Control */
-	volatile uint8_t PM2CTL;
-	/* 0x17: Host Interface PM Channel 2 Interrupt Control */
-	volatile uint8_t PM2IC;
-	/* 0x18: Host Interface PM Channel 2 Interrupt Enable */
-	volatile uint8_t PM2IE;
-	/* 0x19: Mailbox Control */
-	volatile uint8_t MBXCTRL;
-	/* 0x1a-0x1f: Reserved2 */
-	volatile uint8_t reserved2[6];
-	/* 0x20-0xff: Reserved3 */
-	volatile uint8_t reserved3[0xe0];
-};
-
-/* Input Buffer Full Interrupt Enable */
-#define PMC_PM1CTL_IBFIE    BIT(0)
-/* Output Buffer Full */
-#define PMC_PM1STS_OBF      BIT(0)
-/* Input Buffer Full */
-#define PMC_PM1STS_IBF      BIT(1)
-/* General Purpose Flag */
-#define PMC_PM1STS_GPF      BIT(2)
-/* A2 Address (A2) */
-#define PMC_PM1STS_A2_ADDR  BIT(3)
-
-/* PMC2 Input Buffer Full Interrupt Enable */
-#define PMC_PM2CTL_IBFIE    BIT(0)
-/* General Purpose Flag */
-#define PMC_PM2STS_GPF      BIT(2)
-
-/*
- * Dedicated Interrupt
- * 0b:
- * INT3: PMC Output Buffer Empty Int
- * INT25: PMC Input Buffer Full Int
- * 1b:
- * INT3: PMC1 Output Buffer Empty Int
- * INT25: PMC1 Input Buffer Full Int
- * INT26: PMC2 Output Buffer Empty Int
- * INT27: PMC2 Input Buffer Full Int
- */
-#define PMC_MBXCTRL_DINT    BIT(5)
-
-/*
- * eSPI slave registers
- */
-struct espi_slave_regs {
-	/* 0x00-0x03: Reserved1 */
-	volatile uint8_t reserved1[4];
-
-	/* 0x04: General Capabilities and Configuration 0 */
-	volatile uint8_t GCAPCFG0;
-	/* 0x05: General Capabilities and Configuration 1 */
-	volatile uint8_t GCAPCFG1;
-	/* 0x06: General Capabilities and Configuration 2 */
-	volatile uint8_t GCAPCFG2;
-	/* 0x07: General Capabilities and Configuration 3 */
-	volatile uint8_t GCAPCFG3;
-
-	/* Channel 0 (Peripheral Channel) Capabilities and Configurations */
-	/* 0x08: Channel 0 Capabilities and Configuration 0 */
-	volatile uint8_t CH_PC_CAPCFG0;
-	/* 0x09: Channel 0 Capabilities and Configuration 1 */
-	volatile uint8_t CH_PC_CAPCFG1;
-	/* 0x0A: Channel 0 Capabilities and Configuration 2 */
-	volatile uint8_t CH_PC_CAPCFG2;
-	/* 0x0B: Channel 0 Capabilities and Configuration 3 */
-	volatile uint8_t CH_PC_CAPCFG3;
-
-	/* Channel 1 (Virtual Wire Channel) Capabilities and Configurations */
-	/* 0x0C: Channel 1 Capabilities and Configuration 0 */
-	volatile uint8_t CH_VW_CAPCFG0;
-	/* 0x0D: Channel 1 Capabilities and Configuration 1 */
-	volatile uint8_t CH_VW_CAPCFG1;
-	/* 0x0E: Channel 1 Capabilities and Configuration 2 */
-	volatile uint8_t CH_VW_CAPCFG2;
-	/* 0x0F: Channel 1 Capabilities and Configuration 3 */
-	volatile uint8_t CH_VW_CAPCFG3;
-
-	/* Channel 2 (OOB Message Channel) Capabilities and Configurations */
-	/* 0x10: Channel 2 Capabilities and Configuration 0 */
-	volatile uint8_t CH_OOB_CAPCFG0;
-	/* 0x11: Channel 2 Capabilities and Configuration 1 */
-	volatile uint8_t CH_OOB_CAPCFG1;
-	/* 0x12: Channel 2 Capabilities and Configuration 2 */
-	volatile uint8_t CH_OOB_CAPCFG2;
-	/* 0x13: Channel 2 Capabilities and Configuration 3 */
-	volatile uint8_t CH_OOB_CAPCFG3;
-
-	/* Channel 3 (Flash Access Channel) Capabilities and Configurations */
-	/* 0x14: Channel 3 Capabilities and Configuration 0 */
-	volatile uint8_t CH_FLASH_CAPCFG0;
-	/* 0x15: Channel 3 Capabilities and Configuration 1 */
-	volatile uint8_t CH_FLASH_CAPCFG1;
-	/* 0x16: Channel 3 Capabilities and Configuration 2 */
-	volatile uint8_t CH_FLASH_CAPCFG2;
-	/* 0x17: Channel 3 Capabilities and Configuration 3 */
-	volatile uint8_t CH_FLASH_CAPCFG3;
-	/* Channel 3 Capabilities and Configurations 2 */
-	/* 0x18: Channel 3 Capabilities and Configuration 2-0 */
-	volatile uint8_t CH_FLASH_CAPCFG2_0;
-	/* 0x19: Channel 3 Capabilities and Configuration 2-1 */
-	volatile uint8_t CH_FLASH_CAPCFG2_1;
-	/* 0x1A: Channel 3 Capabilities and Configuration 2-2 */
-	volatile uint8_t CH_FLASH_CAPCFG2_2;
-	/* 0x1B: Channel 3 Capabilities and Configuration 2-3 */
-	volatile uint8_t CH_FLASH_CAPCFG2_3;
-
-	/* 0x1c-0x1f: Reserved2 */
-	volatile uint8_t reserved2[4];
-	/* 0x20-0x8f: Reserved3 */
-	volatile uint8_t reserved3[0x70];
-
-	/* 0x90: eSPI PC Control 0 */
-	volatile uint8_t ESPCTRL0;
-	/* 0x91: eSPI PC Control 1 */
-	volatile uint8_t ESPCTRL1;
-	/* 0x92: eSPI PC Control 2 */
-	volatile uint8_t ESPCTRL2;
-	/* 0x93: eSPI PC Control 3 */
-	volatile uint8_t ESPCTRL3;
-	/* 0x94: eSPI PC Control 4 */
-	volatile uint8_t ESPCTRL4;
-	/* 0x95: eSPI PC Control 5 */
-	volatile uint8_t ESPCTRL5;
-	/* 0x96: eSPI PC Control 6 */
-	volatile uint8_t ESPCTRL6;
-	/* 0x97: eSPI PC Control 7 */
-	volatile uint8_t ESPCTRL7;
-	/* 0x98-0x9f: Reserved4 */
-	volatile uint8_t reserved4[8];
-
-	/* 0xa0: eSPI General Control 0 */
-	volatile uint8_t ESGCTRL0;
-	/* 0xa1: eSPI General Control 1 */
-	volatile uint8_t ESGCTRL1;
-	/* 0xa2: eSPI General Control 2 */
-	volatile uint8_t ESGCTRL2;
-	/* 0xa3: eSPI General Control 3 */
-	volatile uint8_t ESGCTRL3;
-	/* 0xa4-0xaf: Reserved5 */
-	volatile uint8_t reserved5[12];
-
-	/* 0xb0: eSPI Upstream Control 0 */
-	volatile uint8_t ESUCTRL0;
-	/* 0xb1: eSPI Upstream Control 1 */
-	volatile uint8_t ESUCTRL1;
-	/* 0xb2: eSPI Upstream Control 2 */
-	volatile uint8_t ESUCTRL2;
-	/* 0xb3: eSPI Upstream Control 3 */
-	volatile uint8_t ESUCTRL3;
-	/* 0xb4-0xb5: Reserved6 */
-	volatile uint8_t reserved6[2];
-	/* 0xb6: eSPI Upstream Control 6 */
-	volatile uint8_t ESUCTRL6;
-	/* 0xb7: eSPI Upstream Control 7 */
-	volatile uint8_t ESUCTRL7;
-	/* 0xb8: eSPI Upstream Control 8 */
-	volatile uint8_t ESUCTRL8;
-	/* 0xb9-0xbf: Reserved7 */
-	volatile uint8_t reserved7[7];
-
-	/* 0xc0: eSPI OOB Control 0 */
-	volatile uint8_t ESOCTRL0;
-	/* 0xc1: eSPI OOB Control 1 */
-	volatile uint8_t ESOCTRL1;
-	/* 0xc2-0xc3: Reserved8 */
-	volatile uint8_t reserved8[2];
-	/* 0xc4: eSPI OOB Control 4 */
-	volatile uint8_t ESOCTRL4;
-	/* 0xc5-0xcf: Reserved9 */
-	volatile uint8_t reserved9[11];
-
-	/* 0xd0: eSPI SAFS Control 0 */
-	volatile uint8_t ESPISAFSC0;
-	/* 0xd1: eSPI SAFS Control 1 */
-	volatile uint8_t ESPISAFSC1;
-	/* 0xd2: eSPI SAFS Control 2 */
-	volatile uint8_t ESPISAFSC2;
-	/* 0xd3: eSPI SAFS Control 3 */
-	volatile uint8_t ESPISAFSC3;
-	/* 0xd4: eSPI SAFS Control 4 */
-	volatile uint8_t ESPISAFSC4;
-	/* 0xd5: eSPI SAFS Control 5 */
-	volatile uint8_t ESPISAFSC5;
-	/* 0xd6: eSPI SAFS Control 6 */
-	volatile uint8_t ESPISAFSC6;
-	/* 0xd7: eSPI SAFS Control 7 */
-	volatile uint8_t ESPISAFSC7;
-};
-
-/*
- * eSPI VW registers
- */
-struct espi_vw_regs {
-	/* 0x00-0x7f: VW index */
-	volatile uint8_t VW_INDEX[0x80];
-	/* 0x80-0x8f: Reserved1 */
-	volatile uint8_t reserved1[0x10];
-	/* 0x90: VW Contrl 0 */
-	volatile uint8_t VWCTRL0;
-	/* 0x91: VW Contrl 1 */
-	volatile uint8_t VWCTRL1;
-	/* 0x92: VW Contrl 2 */
-	volatile uint8_t VWCTRL2;
-	/* 0x93: VW Contrl 3 */
-	volatile uint8_t VWCTRL3;
-	/* 0x94: Reserved2 */
-	volatile uint8_t reserved2;
-	/* 0x95: VW Contrl 5 */
-	volatile uint8_t VWCTRL5;
-	/* 0x96: VW Contrl 6 */
-	volatile uint8_t VWCTRL6;
-	/* 0x97: VW Contrl 7 */
-	volatile uint8_t VWCTRL7;
-	/* 0x98-0x99: Reserved3 */
-	volatile uint8_t reserved3[2];
-};
-
-#define ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE 80
-/*
- * eSPI Queue 0 registers
- */
-struct espi_queue0_regs {
-	/* 0x00-0x3f: PUT_PC Data Byte 0-63 */
-	volatile uint8_t PUT_PC_DATA[0x40];
-	/* 0x40-0x7f: Reserved1 */
-	volatile uint8_t reserved1[0x40];
-	/* 0x80-0xcf: PUT_OOB Data Byte 0-79 */
-	volatile uint8_t PUT_OOB_DATA[ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE];
-};
-
-/*
- * eSPI Queue 1 registers
- */
-struct espi_queue1_regs {
-	/* 0x00-0x4f: Upstream Data Byte 0-79 */
-	volatile uint8_t UPSTREAM_DATA[ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE];
-	/* 0x50-0x7f: Reserved1 */
-	volatile uint8_t reserved1[0x30];
-	/* 0x80-0xbf: PUT_FLASH_NP Data Byte 0-63 */
-	volatile uint8_t PUT_FLASH_NP_DATA[0x40];
-};
-
-#endif /* !__ASSEMBLER__ */
-
-
-/**
- *
- * (3Axxh) SPI Slave Controller (SPISC) registers
- *
- */
-#ifndef __ASSEMBLER__
-struct spisc_it8xxx2_regs {
-	/* 0x00: SPI Slave General Control */
-	volatile uint8_t SPISC_SPISGCR;
-	/* 0x01: Tx/Rx FIFO Access */
-	volatile uint8_t SPISC_TXRXFAR;
-	/* 0x02: Tx FIFO Control */
-	volatile uint8_t SPISC_TXFCR;
-	/* 0x03: SPI Slave General Control 2 */
-	volatile uint8_t SPISC_SPISGCR2;
-	/* 0x04: Interrupt Mask */
-	volatile uint8_t SPISC_IMR;
-	/* 0x05: Interrupt Status */
-	volatile uint8_t SPISC_ISR;
-	/* 0x06: Tx FIFO Status */
-	volatile uint8_t SPISC_TXFSR;
-	/* 0x07: Rx FIFO Status */
-	volatile uint8_t SPISC_RXFSR;
-	/* 0x08: CPU Write Tx FIFO Data Byte0 */
-	volatile uint8_t SPISC_CPUWTXFDB0R;
-	/* 0x09: FIFO Control / CPU Write Tx FIFO Data Byte1 */
-	volatile uint8_t SPISC_FCR;
-	/* 0x0A: CPU Write Tx FIFO Data Byte2 */
-	volatile uint8_t SPISC_CPUWTXFDB2R;
-	/* 0x0B: SPI Slave Response Data / CPU Write Tx FIFO Data Byte3 */
-	volatile uint8_t SPISC_SPISRDR;
-	/* 0x0C: Rx FIFO Readout Data Byte0 */
-	volatile uint8_t SPISC_RXFRDRB0;
-	/* 0x0D: Rx FIFO Readout Data Byte1 */
-	volatile uint8_t SPISC_RXFRDRB1;
-	/* 0x0E: Rx FIFO Readout Data Byte2 */
-	volatile uint8_t SPISC_RXFRDRB2;
-	/* 0x0F: Rx FIFO Readout Data Byte3 */
-	volatile uint8_t SPISC_RXFRDRB3;
-	/* 0x10-0x17: Reserved1 */
-	volatile uint8_t reserved1[8];
-	/* 0x18: FIFO Target Count Byte0 */
-	volatile uint8_t SPISC_FTCB0R;
-	/* 0x19: FIFO Target Count Byte1 */
-	volatile uint8_t SPISC_FTCB1R;
-	/* 0x1A: Target Count Capture Byte0 */
-	volatile uint8_t SPISC_TCCB0;
-	/* 0x1B: Target Count Capture Byte1 */
-	volatile uint8_t SPISC_TCCB1;
-	/* 0x1C-0x1D: Reserved2 */
-	volatile uint8_t reserved2[2];
-	/* 0x1E: Hardware Parsing 2 */
-	volatile uint8_t SPISC_HPR2;
-	/* 0x1F-0x25: Reserved3 */
-	volatile uint8_t reserved3[7];
-	/* 0x26: Rx Valid Length Interrupt Status Mask */
-	volatile uint8_t SPISC_RXVLISMR;
-	/* 0x27: Rx Valid Length Interrupt Status */
-	volatile uint8_t SPISC_RXVLISR;
-};
-#endif /* !__ASSEMBLER__ */
-
-/* SPISC register fields */
-/* 0x00: SPI Slave General Control */
-#define IT8XXX2_SPISC_SPISCEN		BIT(0)
-/* 0x01: Tx/Rx FIFO Access */
-#define IT8XXX2_SPISC_CPURXF1A		BIT(3)
-#define IT8XXX2_SPISC_CPUTFA		BIT(1)
-/* 0x02: Tx FIFO Control */
-#define IT8XXX2_SPISC_TXFCMR		BIT(2)
-#define IT8XXX2_SPISC_TXFR		BIT(1)
-#define IT8XXX2_SPISC_TXFS		BIT(0)
-/* 0x03: SPI Slave General Control 2 */
-#define IT8XXX2_SPISC_RXF2OC		BIT(4)
-#define IT8XXX2_SPISC_RXF1OC		BIT(3)
-#define IT8XXX2_SPISC_RXFAR		BIT(0)
-/* 0x04: Interrupt Mask */
-#define IT8XXX2_SPISC_EDIM		BIT(2)
-/* 0x06: Tx FIFO Status */
-#define IT8XXX2_SPISC_ENDDETECTINT	BIT(2)
-/* 0x09: FIFO Control */
-#define IT8XXX2_SPISC_SPISRTXF		BIT(2)
-#define IT8XXX2_SPISC_RXFR		BIT(1)
-#define IT8XXX2_SPISC_RXFCMR		BIT(0)
-/* 0x26: Rx Valid Length Interrupt Status Mask */
-#define IT8XXX2_SPISC_RVLIM		BIT(0)
-/* 0x27: Rx Valid Length Interrupt Status */
-#define IT8XXX2_SPISC_RVLI		BIT(0)
-
-#endif /* CHIP_CHIPREGS_H */
diff --git a/soc/ite/ec/common/soc_common.h b/soc/ite/ec/common/soc_common.h
index b7e0cdd5e55..31e1d8a9553 100644
--- a/soc/ite/ec/common/soc_common.h
+++ b/soc/ite/ec/common/soc_common.h
@@ -16,6 +16,11 @@
 
 #ifndef _ASMLANGUAGE
 
+struct ite_clk_cfg {
+	uint8_t ctrl;
+	uint8_t bits;
+};
+
 #ifdef CONFIG_HAS_ITE_INTC
 /*
  * Save current interrupt state of soc-level into ier_setting[] with
@@ -43,11 +48,10 @@ uint32_t chip_get_pll_freq(void);
 void chip_pll_ctrl(enum chip_pll_mode mode);
 void riscv_idle(enum chip_pll_mode mode, unsigned int key);
 
-#ifdef CONFIG_SOC_IT8XXX2_CPU_IDLE_GATING
+/* Functions for managing the CPU idle state */
 void chip_permit_idle(void);
 void chip_block_idle(void);
 bool cpu_idle_not_allowed(void);
-#endif
 
 #endif /* !_ASMLANGUAGE */
 
diff --git a/soc/ite/ec/it51xxx/CMakeLists.txt b/soc/ite/ec/it51xxx/CMakeLists.txt
new file mode 100644
index 00000000000..94ad7b7a0df
--- /dev/null
+++ b/soc/ite/ec/it51xxx/CMakeLists.txt
@@ -0,0 +1,8 @@
+zephyr_sources(soc.c vector.S)
+zephyr_include_directories(.)
+
+zephyr_sources_ifdef(CONFIG_SOC_IT51XXX_USE_ILM ../it8xxx2/ilm.c ilm_wrapper.c)
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld
+    CACHE INTERNAL "SoC Linker script ${SOC_NAME}"
+)
diff --git a/soc/ite/ec/it51xxx/Kconfig b/soc/ite/ec/it51xxx/Kconfig
new file mode 100644
index 00000000000..1b910657b69
--- /dev/null
+++ b/soc/ite/ec/it51xxx/Kconfig
@@ -0,0 +1,47 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_IT51XXX
+	select HAS_PM
+	select ARCH_HAS_CUSTOM_CPU_IDLE
+	select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
+	select SOC_PREP_HOOK
+
+if SOC_SERIES_IT51XXX
+
+config SOC_IT51XXX
+	select RISCV
+	select ATOMIC_OPERATIONS_C
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_C if !SOC_IT51526AW
+	select RISCV_ISA_EXT_ZBA
+	select RISCV_ISA_EXT_ZBB
+	select RISCV_ISA_EXT_ZBS
+	select FLASH
+	imply XIP
+
+config SOC_IT51XXX_CPU_IDLE_GATING
+	bool
+	help
+	  This option determines whether the entering CPU idle mode can be
+	  gated by individual drivers. When this option is disabled, CPU idle
+	  mode is always permitted.
+
+config SOC_IT51XXX_USE_ILM
+	bool
+	default y
+	help
+	  If enabled, Instruction Local Memory (ILM) will be configured to execute
+	  code placed in the .__ram_code section out of RAM. This consumes RAM in
+	  blocks of 4 kilobytes, but performance of code in ILM is much more
+	  predictable than executing from Flash directly, and some code (such as code
+	  that writes to the internal Flash) must execute out of RAM.
+
+config ILM_MAX_SIZE
+	int "ILM Size in kB"
+	default 4
+
+endif # SOC_SERIES_IT51XXX
diff --git a/soc/ite/ec/it51xxx/Kconfig.defconfig.series b/soc/ite/ec/it51xxx/Kconfig.defconfig.series
new file mode 100644
index 00000000000..5e705263429
--- /dev/null
+++ b/soc/ite/ec/it51xxx/Kconfig.defconfig.series
@@ -0,0 +1,40 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_IT51XXX
+
+config ARCH_HAS_CUSTOM_BUSY_WAIT
+	default y
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 4096
+
+config UART_NS16550_WA_ISR_REENABLE_INTERRUPT
+	default y
+	depends on UART_NS16550
+
+config FLASH_INIT_PRIORITY
+	default 0
+
+config NUM_IRQS
+	default 225
+
+config DYNAMIC_INTERRUPTS
+	default y
+
+config GEN_ISR_TABLES
+	default y
+
+config GEN_IRQ_START_VECTOR
+	default 0
+
+config GEN_SW_ISR_TABLE
+	default y
+
+config RISCV_SOC_INTERRUPT_INIT
+	default y
+
+endif # SOC_SERIES_IT51XXX
diff --git a/soc/ite/ec/it51xxx/Kconfig.soc b/soc/ite/ec/it51xxx/Kconfig.soc
new file mode 100644
index 00000000000..dccc1678d27
--- /dev/null
+++ b/soc/ite/ec/it51xxx/Kconfig.soc
@@ -0,0 +1,22 @@
+# Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_IT51XXX
+	bool
+	select SOC_FAMILY_ITE_EC
+	help
+	  Enable support for ITE IT51XXX
+
+config SOC_IT51XXX
+	bool
+	select SOC_SERIES_IT51XXX
+
+config SOC_IT51526AW
+	bool
+	select SOC_IT51XXX
+
+config SOC_SERIES
+	default "it51xxx" if SOC_SERIES_IT51XXX
+
+config SOC
+	default "it51526aw" if SOC_IT51526AW
diff --git a/soc/ite/ec/it51xxx/chip_chipregs.h b/soc/ite/ec/it51xxx/chip_chipregs.h
new file mode 100644
index 00000000000..10f13429566
--- /dev/null
+++ b/soc/ite/ec/it51xxx/chip_chipregs.h
@@ -0,0 +1,326 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef CHIP_CHIPREGS_H
+#define CHIP_CHIPREGS_H
+
+#include <zephyr/sys/util.h>
+
+#define IT51XXX_EC_FREQ KHZ(9200)
+
+#ifdef _ASMLANGUAGE
+#define ECREG(x) x
+#else
+
+/*
+ * Macros for hardware registers access.
+ */
+#define ECREG(x)     (*((volatile unsigned char *)(x)))
+#define ECREG_u16(x) (*((volatile unsigned short *)(x)))
+#define ECREG_u32(x) (*((volatile unsigned long *)(x)))
+
+#endif /* _ASMLANGUAGE */
+
+/**
+ *
+ * (10xxh) Shared Memory Flash Interface Bridge (SMFI) registers
+ *
+ */
+#ifndef __ASSEMBLER__
+struct smfi_it51xxx_regs {
+	volatile uint8_t reserved1[59];
+	/* 0x3B: EC-Indirect memory address 0 */
+	volatile uint8_t SMFI_ECINDAR0;
+	/* 0x3C: EC-Indirect memory address 1 */
+	volatile uint8_t SMFI_ECINDAR1;
+	/* 0x3D: EC-Indirect memory address 2 */
+	volatile uint8_t SMFI_ECINDAR2;
+	/* 0x3E: EC-Indirect memory address 3 */
+	volatile uint8_t SMFI_ECINDAR3;
+	/* 0x3F: EC-Indirect memory data */
+	volatile uint8_t SMFI_ECINDDR;
+	/* 0x40: Scratch SRAM 0 address low byte */
+	volatile uint8_t SMFI_SCAR0L;
+	/* 0x41: Scratch SRAM 0 address middle byte */
+	volatile uint8_t SMFI_SCAR0M;
+	/* 0x42: Scratch SRAM 0 address high byte */
+	volatile uint8_t SMFI_SCAR0H;
+	volatile uint8_t reserved1_1[23];
+	/* 0x5A: Host RAM Window Control */
+	volatile uint8_t SMFI_HRAMWC;
+	/* 0x5B: Host RAM Window 0 Base Address [11:4] */
+	volatile uint8_t SMFI_HRAMW0BA;
+	/* 0x5C: Host RAM Window 1 Base Address [11:4] */
+	volatile uint8_t SMFI_HRAMW1BA;
+	/* 0x5D: Host RAM Window 0 Access Allow Size */
+	volatile uint8_t SMFI_HRAMW0AAS;
+	/* 0x5E: Host RAM Window 1 Access Allow Size */
+	volatile uint8_t SMFI_HRAMW1AAS;
+	volatile uint8_t reserved_5f_80[34];
+	/* 0x81: Flash control 6 */
+	volatile uint8_t SMFI_FLHCTRL6R;
+};
+#endif /* !__ASSEMBLER__ */
+
+/* SMFI register fields */
+/* EC-Indirect read internal flash */
+#define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6)
+/* Enable EC-indirect page program command */
+#define IT51XXX_SMFI_MASK_ECINDPP       BIT(3)
+#define ITE_EC_SMFI_MASK_ECINDPP        IT51XXX_SMFI_MASK_ECINDPP
+/* 0x42: Scratch SRAM 0 address high byte */
+#define SCARH_ENABLE                    BIT(7)
+#define SCARH_ADDR_BIT19                BIT(3)
+
+/**
+ *
+ * (16xxh) General Purpose I/O Port (GPIO) registers
+ *
+ */
+#define GPIO_IT51XXX_REGS_BASE ((struct gpio_it51xxx_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr)))
+
+#ifndef __ASSEMBLER__
+struct gpio_it51xxx_regs {
+	/* 0x00: General Control */
+	volatile uint8_t GPIO_GCR;
+	/* 0x01-CF: Reserved_01_cf */
+	volatile uint8_t reserved_01_cf[207];
+	/* 0xD0: General Control 31 */
+	volatile uint8_t GPIO_GCR31;
+	/* 0xD1: General Control 32 */
+	volatile uint8_t GPIO_GCR32;
+	/* 0xD2: Reserved_d2 */
+	volatile uint8_t reserved_d2[1];
+	/* 0xD3: General Control 34 */
+	volatile uint8_t GPIO_GCR34;
+	/* 0xD4: GPA Voltage Selection */
+	volatile uint8_t GPIO_GPAVSR;
+	/* 0xD5: GPB Voltage Selection */
+	volatile uint8_t GPIO_GPBVSR;
+	/* 0xD6: GPC Voltage Selection */
+	volatile uint8_t GPIO_GPCVSR;
+	/* 0xD7: GPD Voltage Selection */
+	volatile uint8_t GPIO_GPDVSR;
+	/* 0xD8: GPE Voltage Selection */
+	volatile uint8_t GPIO_GPEVSR;
+	/* 0xD9: GPF Voltage Selection */
+	volatile uint8_t GPIO_GPFVSR;
+	/* 0xDA: GPG Voltage Selection */
+	volatile uint8_t GPIO_GPGVSR;
+	/* 0xDB: GPH Voltage Selection */
+	volatile uint8_t GPIO_GPHVSR;
+	/* 0xDC: GPI Voltage Selection */
+	volatile uint8_t GPIO_GPIVSR;
+	/* 0xDD: GPJ Voltage Selection */
+	volatile uint8_t GPIO_GPJVSR;
+	/* 0xDE: GP I3C Control */
+	volatile uint8_t GPIO_GPI3CCR;
+	/* 0xDF: Reserved_df */
+	volatile uint8_t reserved_df[1];
+	/* 0xE0: General Control 16 */
+	volatile uint8_t GPIO_GCR16;
+	/* 0xE1: General Control 17 */
+	volatile uint8_t GPIO_GCR17;
+	/* 0xE2: General Control 18 */
+	volatile uint8_t GPIO_GCR18;
+	/* 0xE3: Reserved_e3 */
+	volatile uint8_t reserved_e3;
+	/* 0xE4: General Control 19 */
+	volatile uint8_t GPIO_GCR19;
+	/* 0xE5: General Control 20 */
+	volatile uint8_t GPIO_GCR20;
+	/* 0xE6: General Control 21 */
+	volatile uint8_t GPIO_GCR21;
+	/* 0xE7: General Control 22 */
+	volatile uint8_t GPIO_GCR22;
+	/* 0xE8: Reserved_e8 */
+	volatile uint8_t reserved_e8[1];
+	/* 0xE9: General Control 24 */
+	volatile uint8_t GPIO_GCR24;
+	/* 0xEA: General Control 25 */
+	volatile uint8_t GPIO_GCR25;
+	/* 0xEB: General Control 26 */
+	volatile uint8_t GPIO_GCR26;
+	/* 0xEC: Reserved_ec */
+	volatile uint8_t reserved_ec[1];
+	/* 0xED: General Control 28 */
+	volatile uint8_t GPIO_GCR28;
+	/* 0xEE-0xEF: Reserved_ee_ef */
+	volatile uint8_t reserved_ee_ef[2];
+	/* 0xF0: General Control 1 */
+	volatile uint8_t GPIO_GCR1;
+	/* 0xF1: General Control 2 */
+	volatile uint8_t GPIO_GCR2;
+	/* 0xF2: General Control 3 */
+	volatile uint8_t GPIO_GCR3;
+	/* 0xF3: General Control 4 */
+	volatile uint8_t GPIO_GCR4;
+	/* 0xF4: General Control 5 */
+	volatile uint8_t GPIO_GCR5;
+	/* 0xF5: General Control 6 */
+	volatile uint8_t GPIO_GCR6;
+	/* 0xF6: General Control 7 */
+	volatile uint8_t GPIO_GCR7;
+	/* 0xF7: General Control 8 */
+	volatile uint8_t GPIO_GCR8;
+	/* 0xF8: General Control 9 */
+	volatile uint8_t GPIO_GCR9;
+	/* 0xF9: General Control 10 */
+	volatile uint8_t GPIO_GCR10;
+	/* 0xFA: General Control 11 */
+	volatile uint8_t GPIO_GCR11;
+	/* 0xFB: General Control 12 */
+	volatile uint8_t GPIO_GCR12;
+	/* 0xFC: General Control 13 */
+	volatile uint8_t GPIO_GCR13;
+	/* 0xFD: General Control 14 */
+	volatile uint8_t GPIO_GCR14;
+	/* 0xFE: General Control 15 */
+	volatile uint8_t GPIO_GCR15;
+	/* 0xFF: Power Good Watch Control */
+	volatile uint8_t GPIO_PGWCR;
+};
+#endif /* !__ASSEMBLER__ */
+
+/* GPIO register fields */
+/* 0x00: General Control */
+#define IT51XXX_GPIO_LPCRSTEN             (BIT(2) | BIT(1))
+#define ITE_EC_GPIO_LPCRSTEN              IT51XXX_GPIO_LPCRSTEN
+#define IT51XXX_GPIO_GCR_ESPI_RST_D2      0x2
+#define IT51XXX_GPIO_GCR_ESPI_RST_POS     1
+#define IT51XXX_GPIO_GCR_ESPI_RST_EN_MASK (0x3 << IT51XXX_GPIO_GCR_ESPI_RST_POS)
+/* 0xF0: General Control 1 */
+#define IT51XXX_GPIO_U2CTRL_SIN1_SOUT1_EN BIT(2)
+#define IT51XXX_GPIO_U1CTRL_SIN0_SOUT0_EN BIT(0)
+/* 0xE6: General Control 21 */
+#define IT51XXX_GPIO_GPH1VS               BIT(1)
+#define IT51XXX_GPIO_GPH2VS               BIT(0)
+
+#define KSIX_KSOX_KBS_GPIO_MODE BIT(7)
+#define KSIX_KSOX_GPIO_OUTPUT   BIT(6)
+#define KSIX_KSOX_GPIO_PULLUP   BIT(2)
+#define KSIX_KSOX_GPIO_PULLDOWN BIT(1)
+
+#define GPCR_PORT_PIN_MODE_INPUT    BIT(7)
+#define GPCR_PORT_PIN_MODE_OUTPUT   BIT(6)
+#define GPCR_PORT_PIN_MODE_PULLUP   BIT(2)
+#define GPCR_PORT_PIN_MODE_PULLDOWN BIT(1)
+
+/*
+ * If both PULLUP and PULLDOWN are set to 1b, the corresponding port would be
+ * configured as tri-state.
+ */
+#define GPCR_PORT_PIN_MODE_TRISTATE                                                                \
+	(GPCR_PORT_PIN_MODE_INPUT | GPCR_PORT_PIN_MODE_PULLUP | GPCR_PORT_PIN_MODE_PULLDOWN)
+
+/**
+ *
+ * (1Exxh) PLL Control Mode
+ *
+ */
+#ifndef __ASSEMBLER__
+enum chip_pll_mode {
+	CHIP_PLL_DOZE = 0,
+	CHIP_PLL_SLEEP = 1,
+	CHIP_PLL_DEEP_DOZE = 3,
+};
+#endif
+
+/**
+ *
+ * (20xxh) General Control (GCTRL) registers
+ *
+ */
+#define GCTRL_IT51XXX_REGS_BASE ((struct gctrl_it51xxx_regs *)DT_REG_ADDR(DT_NODELABEL(gctrl)))
+
+#ifndef __ASSEMBLER__
+struct gctrl_it51xxx_regs {
+	/* 0x00-0x01: Reserved_00_01 */
+	volatile uint8_t reserved_00_01[2];
+	/* 0x02: Chip Version */
+	volatile uint8_t GCTRL_ECHIPVER;
+	/* 0x03-0x05: Reserved_03_05 */
+	volatile uint8_t reserved_03_05[3];
+	/* 0x06: Reset Status */
+	volatile uint8_t GCTRL_RSTS;
+	/* 0x07-0x09: Reserved_07_09 */
+	volatile uint8_t reserved_07_09[3];
+	/* 0x0A: Base Address Select */
+	volatile uint8_t GCTRL_BADRSEL;
+	/* 0x0B: Wait Next Clock Rising */
+	volatile uint8_t GCTRL_WNCKR;
+	/* 0x0C: Special Control 5 */
+	volatile uint8_t GCTRL_SPCTRL5;
+	/* 0x0D: Special Control 1 */
+	volatile uint8_t GCTRL_SPCTRL1;
+	/* 0x0E-0x0F: reserved_0e_0f */
+	volatile uint8_t reserved_0e_0f[2];
+	/* 0x10: Reset Control DMM */
+	volatile uint8_t GCTRL_RSTDMMC;
+	/* 0x11: Reset Control 4 */
+	volatile uint8_t GCTRL_RSTC4;
+	/* 0x12-0x1B: reserved_12_1b */
+	volatile uint8_t reserved_12_1b[10];
+	/* 0x1C: Special Control 4 */
+	volatile uint8_t GCTRL_SPCTRL4;
+	/* 0x1D-0x1F: reserved_1d_1f */
+	volatile uint8_t reserved_1d_1f[3];
+	/* 0x20: Reset Control 5 */
+	volatile uint8_t GCTRL_RSTC5;
+	/* 0x21-0x37: reserved_21_37 */
+	volatile uint8_t reserved_21_37[23];
+	/* 0x38: Special Control 9 */
+	volatile uint8_t GCTRL_SPCTRL9;
+	/* 0x39-0x46: reserved_39_46 */
+	volatile uint8_t reserved_39_46[14];
+	/* 0x47: Scratch SRAM0 Base Address */
+	volatile uint8_t GCTRL_SCR0BAR;
+	/* 0x48: Scratch ROM 0 Size */
+	volatile uint8_t GCTRL_SCR0SZR;
+	/* 0x49-0x84: reserved_49_84 */
+	volatile uint8_t reserved_49_84[60];
+	/* 0x85: Chip ID Byte 1 */
+	volatile uint8_t GCTRL_ECHIPID1;
+	/* 0x86: Chip ID Byte 2 */
+	volatile uint8_t GCTRL_ECHIPID2;
+	/* 0x87: Chip ID Byte 3 */
+	volatile uint8_t GCTRL_ECHIPID3;
+};
+#endif /* !__ASSEMBLER__ */
+
+/* GCTRL register fields */
+/* 0x06: Reset Status */
+#define IT51XXX_GCTRL_LRS         (BIT(1) | BIT(0))
+#define IT51XXX_GCTRL_IWDTR       BIT(1)
+/* 0x0B: Wait Next 65K Rising */
+#define IT51XXX_GCTRL_WN65K       0x00
+/* 0x10: Reset Control DMM */
+#define IT51XXX_GCTRL_UART1SD     BIT(3)
+#define IT51XXX_GCTRL_UART2SD     BIT(2)
+/* 0x11: Reset Control 4 */
+#define IT51XXX_GCTRL_RPECI       BIT(4)
+#define IT51XXX_GCTRL_RUART       BIT(2)
+/* 0x1C: Special Control 4 */
+#define IT51XXX_GCTRL_LRSIWR      BIT(2)
+#define IT51XXX_GCTRL_LRSIPWRSWTR BIT(1)
+#define IT51XXX_GCTRL_LRSIPGWR    BIT(0)
+/* 0x38: Special Control 9 */
+#define IT51XXX_GCTRL_ALTIE       BIT(4)
+/* 0x47: Scratch SRAM0 Base Address */
+#define IT51XXX_SEL_SRAM0_BASE_4K 0x04
+/* 0x48: Scratch ROM 0 Size */
+#define IT51XXX_GCTRL_SCRSIZE_4K  0x03
+
+/* Alias gpio_ite_ec_regs to gpio_it51xxx_regs for compatibility */
+#define gpio_ite_ec_regs       gpio_it51xxx_regs
+#define GPIO_ITE_EC_REGS_BASE  GPIO_IT51XXX_REGS_BASE
+/* Alias smfi_ite_ec_regs to smfi_it51xxx_regs for compatibility */
+#define smfi_ite_ec_regs       smfi_it51xxx_regs
+/* Alias gctrl_ite_ec_regs to gctrl_it51xxx_regs for compatibility */
+#define gctrl_ite_ec_regs      gctrl_it51xxx_regs
+#define GCTRL_ITE_EC_REGS_BASE GCTRL_IT51XXX_REGS_BASE
+
+#endif /* CHIP_CHIPREGS_H */
diff --git a/soc/ite/ec/it51xxx/ilm.h b/soc/ite/ec/it51xxx/ilm.h
new file mode 100644
index 00000000000..40f3e57d110
--- /dev/null
+++ b/soc/ite/ec/it51xxx/ilm.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+
+/* Places code in the section that gets mapped into ILM */
+#define __soc_ram_code __attribute__((section(".__ram_code")))
+
+#ifndef _ASMLANGUAGE
+void custom_reset_instr_cache(void);
+bool it8xxx2_is_ilm_configured(void);
+
+#endif
diff --git a/soc/ite/ec/it51xxx/ilm_wrapper.c b/soc/ite/ec/it51xxx/ilm_wrapper.c
new file mode 100644
index 00000000000..668b2a4d127
--- /dev/null
+++ b/soc/ite/ec/it51xxx/ilm_wrapper.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <ilm.h>
+#include <soc_common.h>
+#include <zephyr/kernel.h>
+
+void __soc_ram_code custom_reset_instr_cache(void)
+{
+	/* Make sure the I-Cache is reset */
+	__asm__ volatile("fence.i" ::: "memory");
+}
diff --git a/soc/ite/ec/it51xxx/linker.ld b/soc/ite/ec/it51xxx/linker.ld
new file mode 100644
index 00000000000..ec3feb5ee8a
--- /dev/null
+++ b/soc/ite/ec/it51xxx/linker.ld
@@ -0,0 +1,493 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc.h>
+#include <zephyr/devicetree.h>
+
+#include <zephyr/linker/sections.h>
+#include <zephyr/linker/devicetree_regions.h>
+
+#include <zephyr/linker/linker-defs.h>
+#include <zephyr/linker/linker-tool.h>
+
+#ifdef CONFIG_XIP
+#define ROMABLE_REGION              ROM
+#else
+#define ROMABLE_REGION              RAM
+#endif
+#define RAMABLE_REGION              RAM
+
+#define _EXCEPTION_SECTION_NAME     exceptions
+#define _RESET_SECTION_NAME         reset
+
+#if defined(CONFIG_ROM_END_OFFSET)
+#define ROM_END_OFFSET CONFIG_ROM_END_OFFSET
+#else
+#define ROM_END_OFFSET 0
+#endif
+
+#if defined(CONFIG_FLASH_LOAD_OFFSET)
+#define FLASH_LOAD_OFFSET CONFIG_FLASH_LOAD_OFFSET
+#else
+#define FLASH_LOAD_OFFSET 0
+#endif
+
+#ifdef CONFIG_XIP
+
+#if CONFIG_FLASH_LOAD_SIZE > 0
+#define ROM_SIZE (CONFIG_FLASH_LOAD_SIZE - ROM_END_OFFSET)
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_CHOSEN(zephyr_flash), soc_nv_flash, okay)
+#define ROM_BASE (DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) + FLASH_LOAD_OFFSET)
+#ifndef ROM_SIZE
+#define ROM_SIZE (DT_REG_SIZE(DT_CHOSEN(zephyr_flash)) - ROM_END_OFFSET)
+#endif
+
+#elif DT_NODE_HAS_COMPAT(DT_CHOSEN(zephyr_flash), jedec_spi_nor)
+/* For jedec,spi-nor we expect the spi controller to memory map the flash
+ * and for that mapping to be on the register with the name flash_mmap and if a register with that
+ * name doesn't exists, we expect it to be in the second register property of the spi controller.
+ */
+#define SPI_CTRL DT_PARENT(DT_CHOSEN(zephyr_flash))
+#define FLASH_MMAP_NAME flash_mmap
+#define ROM_BASE                                                                                   \
+	(DT_REG_ADDR_BY_NAME_OR(SPI_CTRL, FLASH_MMAP_NAME, DT_REG_ADDR_BY_IDX(SPI_CTRL, 1)) +      \
+	 FLASH_LOAD_OFFSET)
+#ifndef ROM_SIZE
+#define ROM_SIZE                                                                                   \
+	(DT_REG_SIZE_BY_NAME_OR(SPI_CTRL, FLASH_MMAP_NAME, DT_REG_SIZE_BY_IDX(SPI_CTRL, 1)) -      \
+	 ROM_END_OFFSET)
+#endif
+
+#else /* Use Kconfig to cover the remaining cases */
+#define ROM_BASE (CONFIG_FLASH_BASE_ADDRESS + FLASH_LOAD_OFFSET)
+#ifndef ROM_SIZE
+#define ROM_SIZE (CONFIG_FLASH_SIZE * 1024 - FLASH_LOAD_OFFSET - ROM_END_OFFSET)
+#endif
+
+#endif /* DT_NODE_HAS_COMPAT_STATUS */
+
+#else /* CONFIG_XIP */
+#define ROM_BASE CONFIG_SRAM_BASE_ADDRESS
+#define ROM_SIZE (KB(CONFIG_SRAM_SIZE) - ROM_END_OFFSET)
+#endif /* CONFIG_XIP */
+
+#define RAM_BASE CONFIG_SRAM_BASE_ADDRESS
+#define RAM_SIZE KB(CONFIG_SRAM_SIZE)
+
+#ifdef CONFIG_RISCV_PMP
+	#define MPU_MIN_SIZE CONFIG_PMP_GRANULARITY
+	#define MPU_MIN_SIZE_ALIGN . = ALIGN(MPU_MIN_SIZE);
+	#if defined(CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT)
+		#define MPU_ALIGN(region_size) \
+			. = ALIGN(MPU_MIN_SIZE); \
+			. = ALIGN( 1 << LOG2CEIL(region_size))
+	#else
+		#define MPU_ALIGN(region_size) \
+			. = ALIGN(MPU_MIN_SIZE)
+	#endif
+#else
+	#define MPU_MIN_SIZE_ALIGN
+	#define MPU_ALIGN(region_size) . = ALIGN(4)
+#endif
+
+#include <zephyr/linker/linker-devnull.h>
+
+MEMORY
+{
+#ifdef CONFIG_XIP
+    ROM (rx)  : ORIGIN = ROM_BASE, LENGTH = ROM_SIZE
+#endif
+    RAM (rwx) : ORIGIN = RAM_BASE, LENGTH = RAM_SIZE
+
+#if defined(CONFIG_LINKER_DEVNULL_MEMORY)
+    DEVNULL_ROM (rx) : ORIGIN = DEVNULL_ADDR, LENGTH = DEVNULL_SIZE
+#endif
+
+    LINKER_DT_REGIONS()
+
+    /* Used by and documented in include/linker/intlist.ld */
+    IDT_LIST  (wx)      : ORIGIN = 0xFFFFF7FF, LENGTH = 2K
+}
+
+ENTRY(CONFIG_KERNEL_ENTRY)
+
+SECTIONS
+    {
+
+#include <zephyr/linker/rel-sections.ld>
+
+#ifdef CONFIG_LLEXT
+#include <zephyr/linker/llext-sections.ld>
+#endif
+
+    /*
+     * The .plt and .iplt are here according to
+     * 'riscv32-zephyr-elf-ld --verbose', before text section.
+     */
+    SECTION_PROLOGUE(.plt,,)
+	{
+		*(.plt)
+	}
+
+    SECTION_PROLOGUE(.iplt,,)
+	{
+		*(.iplt)
+	}
+
+    GROUP_START(ROMABLE_REGION)
+    __rom_region_start = ROM_BASE;
+
+    SECTION_PROLOGUE(rom_start,,)
+    {
+		. = ALIGN(16);
+/* Located in generated directory. This file is populated by calling
+ * zephyr_linker_sources(ROM_START ...).
+ */
+#include <snippets-rom-start.ld>
+    } GROUP_LINK_IN(ROMABLE_REGION)
+
+#ifdef CONFIG_CODE_DATA_RELOCATION
+#include <linker_relocate.ld>
+#endif
+
+    SECTION_PROLOGUE(_RESET_SECTION_NAME,,)
+    {
+		KEEP(*(.reset.*))
+    } GROUP_LINK_IN(ROMABLE_REGION)
+
+    SECTION_PROLOGUE(_EXCEPTION_SECTION_NAME,,)
+    {
+		. = ALIGN(256);
+		 KEEP(*(".exception.entry.*"))
+		 *(".exception.other.*")
+    } GROUP_LINK_IN(ROMABLE_REGION)
+
+    SECTION_PROLOGUE(_TEXT_SECTION_NAME,,)
+	{
+		. = ALIGN(4);
+		KEEP(*(.openocd_debug))
+		KEEP(*(".openocd_debug.*"))
+
+		__text_region_start = .;
+
+		*(.text)
+		*(".text.*")
+		*(.gnu.linkonce.t.*)
+#include <zephyr/linker/kobject-text.ld>
+		. = ALIGN(0x1000);
+		/* Mapping base address must be 4k-aligned */
+		__ilm_flash_start = .;
+		/* Specially-tagged functions in SoC sources */
+		KEEP(*(.__ram_code))
+		*(.__ram_code.*)
+		__ilm_flash_end = .;
+		/* ILM mapping is always a multiple of 4k size; ensure following
+		 * sections won't incorrectly redirect to RAM. */
+		. = ALIGN(0x1000);
+
+	} GROUP_LINK_IN(ROMABLE_REGION)
+
+    __text_region_end = .;
+
+	__rodata_region_start = .;
+#include <zephyr/linker/common-rom.ld>
+/* Located in generated directory. This file is populated by calling
+ * zephyr_linker_sources(ROM_SECTIONS ...). Useful for grouping iterable RO structs.
+ */
+#include <snippets-rom-sections.ld>
+#include <zephyr/linker/thread-local-storage.ld>
+
+    SECTION_PROLOGUE(_RODATA_SECTION_NAME,,)
+	{
+		 . = ALIGN(4);
+		 *(.srodata)
+		 *(".srodata.*")
+		 *(.rodata)
+		 *(".rodata.*")
+		 *(.gnu.linkonce.r.*)
+		 *(.sdata2 .sdata2.* .gnu.linkonce.s2.*)
+
+/* Located in generated directory. This file is populated by the
+ * zephyr_linker_sources() Cmake function.
+ */
+#include <snippets-rodata.ld>
+#include <zephyr/linker/kobject-rom.ld>
+	. = ALIGN(4);
+	} GROUP_LINK_IN(ROMABLE_REGION)
+
+#include <zephyr/linker/cplusplus-rom.ld>
+	__rodata_region_end = .;
+
+	/* For non-XIP system, __rom_region_end symbol should be set to
+	 * the end of common ROMABLE_REGIONs (text and rodata) instead of
+	 * the linker script end, so it wouldn't mistakenly contain
+	 * RAMABLE_REGION in it.
+	 */
+#ifndef CONFIG_XIP
+#ifdef CONFIG_RISCV_PMP
+	SECTION_PROLOGUE(rom_mpu_padding,,)
+	{
+		MPU_ALIGN(__rodata_region_end - __rom_region_start);
+#ifdef CONFIG_QEMU_TARGET
+		/*
+		 * QEMU doesn't vet each instruction fetch individually.
+		 * Instead, it grabs a whole page and perform dynamic
+		 * translation on it in a batch. It therefore validates
+		 * PMP permissions using page-sized and -aligned chunks.
+		 */
+		. = ALIGN(0x1000);
+#endif
+	} GROUP_LINK_IN(ROMABLE_REGION)
+#endif /* CONFIG_RISCV_PMP */
+
+	__rom_region_end = .;
+	__rom_region_size = __rom_region_end - __rom_region_start;
+#endif /* CONFIG_XIP */
+    GROUP_END(ROMABLE_REGION)
+
+    GROUP_START(RAMABLE_REGION)
+
+	. = RAM_BASE;
+
+    /* Claim RAM for ILM mappings; must be 4k-aligned and each mapping is 4k in size */
+    SECTION_PROLOGUE(ilm_ram,(NOLOAD),ALIGN(0x1000))
+	{
+		/* On IT51XXX chip, scratch RAM must start at RAM_BASE+0x1000 */
+		. += 0x1000;
+		__ilm_ram_start = .;
+		. += __ilm_flash_end - __ilm_flash_start;
+		__ilm_ram_end = .;
+		/* Aligning 4k ensures ILM doesn't overwritte RAM. */
+		. = ALIGN(0x1000);
+	} GROUP_LINK_IN(RAMABLE_REGION)
+
+	_image_ram_start = .;
+/* Located in generated directory. This file is populated by the
+ * zephyr_linker_sources() Cmake function.
+ */
+#include <snippets-ram-sections.ld>
+
+#if defined(CONFIG_USERSPACE)
+#define APP_SHARED_ALIGN MPU_MIN_SIZE_ALIGN
+#define SMEM_PARTITION_ALIGN MPU_ALIGN
+
+#include <app_smem.ld>
+
+	_app_smem_size = _app_smem_end - _app_smem_start;
+	_app_smem_rom_start = LOADADDR(_APP_SMEM_SECTION_NAME);
+#endif /* CONFIG_USERSPACE */
+
+    SECTION_DATA_PROLOGUE(_BSS_SECTION_NAME,(NOLOAD),)
+	{
+		MPU_MIN_SIZE_ALIGN
+		/*
+		 * For performance, BSS section is assumed to be 4 byte aligned and
+		 * a multiple of 4 bytes
+		 */
+		 . = ALIGN(4);
+		 __bss_start = .;
+		__kernel_ram_start = .;
+		 *(.sbss)
+		 *(".sbss.*")
+		 *(.bss)
+		 *(".bss.*")
+		 COMMON_SYMBOLS
+
+#ifdef CONFIG_CODE_DATA_RELOCATION
+#include <linker_sram_bss_relocate.ld>
+#endif
+
+		 /*
+		  * As memory is cleared in words only, it is simpler to ensure the BSS
+		  * section ends on a 4 byte boundary. This wastes a maximum of 3 bytes.
+		  */
+		  __bss_end = ALIGN(4);
+	}  GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+#include <zephyr/linker/common-noinit.ld>
+
+    SECTION_DATA_PROLOGUE(_DATA_SECTION_NAME,,)
+	{
+		 . = ALIGN(4);
+		/* _image_ram_start = .; */
+		 __data_region_start = .;
+		 __data_start = .;
+
+		 *(.data)
+		 *(".data.*")
+
+#ifdef CONFIG_RISCV_GP
+		/*
+		 * RISC-V architecture has 12-bit signed immediate offsets in the
+		 * instructions. If we can put the most commonly accessed globals
+		 * in a special 4K span of memory addressed by the GP register, then
+		 * we can access those values in a single instruction, saving both
+		 * codespace and runtime.
+		 *
+		 * Since these immediate offsets are signed, place gp 0x800 past the
+		 * beginning of .sdata so that we can use both positive and negative
+		 * offsets.
+		 */
+		 . = ALIGN(8);
+		 PROVIDE (__global_pointer$ = . + 0x800);
+#endif
+
+		 *(.sdata .sdata.* .gnu.linkonce.s.*)
+
+/* Located in generated directory. This file is populated by the
+ * zephyr_linker_sources() Cmake function.
+ */
+#include <snippets-rwdata.ld>
+
+#ifdef CONFIG_CODE_DATA_RELOCATION
+#include <linker_sram_data_relocate.ld>
+#endif
+
+		 __data_end = .;
+
+	}  GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)
+	__data_size = __data_end - __data_start;
+	__data_load_start = LOADADDR(_DATA_SECTION_NAME);
+
+	__data_region_load_start = LOADADDR(_DATA_SECTION_NAME);
+
+#include <zephyr/linker/common-ram.ld>
+#include <zephyr/linker/kobject-data.ld>
+#include <zephyr/linker/cplusplus-ram.ld>
+
+/* Located in generated directory. This file is populated by the
+ * zephyr_linker_sources() Cmake function.
+ */
+#include <snippets-data-sections.ld>
+
+    __data_region_end = .;
+
+	__kernel_ram_end = .;
+	__kernel_ram_size = __kernel_ram_end - __kernel_ram_start;
+
+#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_itcm), okay)
+GROUP_START(ITCM)
+
+	SECTION_PROLOGUE(_ITCM_SECTION_NAME,,SUBALIGN(8))
+	{
+		__itcm_start = .;
+		*(.itcm)
+		*(".itcm.*")
+
+/* Located in generated directory. This file is populated by the
+ * zephyr_linker_sources() Cmake function. */
+#include <snippets-itcm-section.ld>
+
+		__itcm_end = .;
+	} GROUP_LINK_IN(ITCM AT> ROMABLE_REGION)
+
+	__itcm_size = __itcm_end - __itcm_start;
+	__itcm_load_start = LOADADDR(_ITCM_SECTION_NAME);
+
+GROUP_END(ITCM)
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_CHOSEN(zephyr_dtcm), okay)
+GROUP_START(DTCM)
+
+	SECTION_PROLOGUE(_DTCM_BSS_SECTION_NAME, (NOLOAD),SUBALIGN(8))
+	{
+		__dtcm_start = .;
+		__dtcm_bss_start = .;
+		*(.dtcm_bss)
+		*(".dtcm_bss.*")
+		__dtcm_bss_end = .;
+	} GROUP_LINK_IN(DTCM)
+
+	SECTION_PROLOGUE(_DTCM_NOINIT_SECTION_NAME, (NOLOAD),SUBALIGN(8))
+	{
+		__dtcm_noinit_start = .;
+		*(.dtcm_noinit)
+		*(".dtcm_noinit.*")
+		__dtcm_noinit_end = .;
+	} GROUP_LINK_IN(DTCM)
+
+	SECTION_PROLOGUE(_DTCM_DATA_SECTION_NAME,,SUBALIGN(8))
+	{
+		__dtcm_data_start = .;
+		*(.dtcm_data)
+		*(".dtcm_data.*")
+
+/* Located in generated directory. This file is populated by the
+ * zephyr_linker_sources() Cmake function. */
+#include <snippets-dtcm-section.ld>
+
+		__dtcm_data_end = .;
+	} GROUP_LINK_IN(DTCM AT> ROMABLE_REGION)
+
+	__dtcm_end = .;
+
+	__dtcm_data_load_start = LOADADDR(_DTCM_DATA_SECTION_NAME);
+
+GROUP_END(DTCM)
+#endif
+
+/* Located in generated directory. This file is populated by the
+ * zephyr_linker_sources() Cmake function.
+ */
+#include <snippets-sections.ld>
+
+#define LAST_RAM_ALIGN MPU_MIN_SIZE_ALIGN
+
+#include <zephyr/linker/ram-end.ld>
+
+    GROUP_END(RAMABLE_REGION)
+
+#include <zephyr/linker/debug-sections.ld>
+
+    /DISCARD/ : { *(.note.GNU-stack) }
+
+    SECTION_PROLOGUE(.riscv.attributes, 0,)
+	{
+	KEEP(*(.riscv.attributes))
+	KEEP(*(.gnu.attributes))
+	}
+
+/* Output section descriptions are needed for these sections to suppress
+ * warnings when "--orphan-handling=warn" is set for lld.
+ */
+#if defined(CONFIG_LLVM_USE_LLD)
+    SECTION_PROLOGUE(.symtab, 0,) { *(.symtab) }
+    SECTION_PROLOGUE(.strtab, 0,) { *(.strtab) }
+    SECTION_PROLOGUE(.shstrtab, 0,) { *(.shstrtab) }
+#endif
+
+    /* Sections generated from 'zephyr,memory-region' nodes */
+    LINKER_DT_SECTIONS()
+
+/* Because ROMABLE_REGION != RAMABLE_REGION in XIP-system, it is valid
+ * to set __rom_region_end symbol at the end of linker script and
+ * doesn't mistakenly contain the RAMABLE_REGION in it.
+ */
+#ifdef CONFIG_XIP
+/* Must be last in romable region */
+SECTION_PROLOGUE(.last_section,,)
+{
+#ifdef CONFIG_LINKER_LAST_SECTION_ID
+  /* Fill last section with a word to ensure location counter and actual rom
+   * region data usage match. */
+  LONG(CONFIG_LINKER_LAST_SECTION_ID_PATTERN)
+  /* __rom_region_size is used when configuring the PMP entry of the ROM region.
+   * Addresses (pmpaddr) in PMP registers need to be aligned to 4. Align
+   * __rom_region_size to 4 to meet that requirement. */
+  MPU_MIN_SIZE_ALIGN
+#endif
+} GROUP_LINK_IN(ROMABLE_REGION)
+
+/* To provide the image size as a const expression,
+ * calculate this value here. */
+__rom_region_end = LOADADDR(.last_section) + SIZEOF(.last_section);
+__rom_region_size = __rom_region_end - __rom_region_start;
+#endif
+
+}
diff --git a/soc/ite/ec/it51xxx/soc.c b/soc/ite/ec/it51xxx/soc.c
new file mode 100644
index 00000000000..df691a0784b
--- /dev/null
+++ b/soc/ite/ec/it51xxx/soc.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc_common.h>
+#include <zephyr/kernel.h>
+
+static mm_reg_t ecpm_base = DT_REG_ADDR(DT_NODELABEL(ecpm));
+/* it51xxx ECPM registers definition */
+/* 0x03: PLL Control */
+#define ECPM_PLLCTRL 0x03
+
+void chip_pll_ctrl(enum chip_pll_mode mode)
+{
+	volatile uint8_t _pll_ctrl __unused;
+
+	sys_write8(mode, ecpm_base + ECPM_PLLCTRL);
+	/*
+	 * for deep doze / sleep mode
+	 * This load operation will ensure PLL setting is taken into
+	 * control register before wait for interrupt instruction.
+	 */
+	_pll_ctrl = sys_read8(ecpm_base + ECPM_PLLCTRL);
+}
+
+#ifdef CONFIG_SOC_IT51XXX_CPU_IDLE_GATING
+/* Preventing CPU going into idle mode during command queue. */
+static atomic_t cpu_idle_disabled;
+
+void chip_permit_idle(void)
+{
+	atomic_dec(&cpu_idle_disabled);
+}
+
+void chip_block_idle(void)
+{
+	atomic_inc(&cpu_idle_disabled);
+}
+
+bool cpu_idle_not_allowed(void)
+{
+	return atomic_get(&cpu_idle_disabled);
+}
+#endif
+
+/* The routine must be called with interrupts locked */
+void riscv_idle(enum chip_pll_mode mode, unsigned int key)
+{
+	/*
+	 * The routine is called with interrupts locked (in kernel/idle()).
+	 * But on kernel/context test_kernel_cpu_idle test, the routine will be
+	 * called without interrupts locked. Hence we disable M-mode external
+	 * interrupt here to protect the below content.
+	 */
+	csr_clear(mie, MIP_MEIP);
+	sys_trace_idle();
+
+	/* Chip doze after wfi instruction */
+	chip_pll_ctrl(mode);
+
+	/* Wait for interrupt */
+	__asm__ volatile("wfi");
+
+	/*
+	 * Enable M-mode external interrupt
+	 * An interrupt can not be fired yet until we enable global interrupt
+	 */
+	csr_set(mie, MIP_MEIP);
+
+	/* Restore global interrupt lockout state */
+	irq_unlock(key);
+}
+
+void arch_cpu_idle(void)
+{
+#ifdef CONFIG_SOC_IT51XXX_CPU_IDLE_GATING
+	/*
+	 * The EC processor(CPU) cannot be in the k_cpu_idle() during
+	 * the transactions with the CQ mode(DMA mode). Otherwise,
+	 * the EC processor would be clock gated.
+	 */
+	if (cpu_idle_not_allowed()) {
+		/* Restore global interrupt lockout state */
+		irq_unlock(MSTATUS_IEN);
+	} else {
+#endif
+		riscv_idle(CHIP_PLL_DOZE, MSTATUS_IEN);
+#ifdef CONFIG_SOC_IT51XXX_CPU_IDLE_GATING
+	}
+#endif
+}
+
+void arch_cpu_atomic_idle(unsigned int key)
+{
+	riscv_idle(CHIP_PLL_DOZE, key);
+}
+
+void soc_prep_hook(void)
+{
+	struct gpio_ite_ec_regs *const gpio_regs = GPIO_ITE_EC_REGS_BASE;
+	struct gctrl_ite_ec_regs *const gctrl_regs = GCTRL_ITE_EC_REGS_BASE;
+
+	/* Scratch SRAM0 uses the 4KB based form 0x801000h */
+	gctrl_regs->GCTRL_SCR0BAR = IT51XXX_SEL_SRAM0_BASE_4K;
+
+	/* bit4: wake up CPU if it is in low power mode and an interrupt is pending. */
+	gctrl_regs->GCTRL_SPCTRL9 |= IT51XXX_GCTRL_ALTIE;
+
+	/* UART1 and UART2 board init */
+	/* bit3: UART1 and UART2 belong to the EC side. */
+	gctrl_regs->GCTRL_RSTDMMC |= IT51XXX_GCTRL_UART1SD | IT51XXX_GCTRL_UART2SD;
+	/* Reset UART before config it */
+	gctrl_regs->GCTRL_RSTC4 = IT51XXX_GCTRL_RUART;
+	/* Switch UART1 and UART2 on without hardware flow control */
+	gpio_regs->GPIO_GCR1 |=
+		IT51XXX_GPIO_U1CTRL_SIN0_SOUT0_EN | IT51XXX_GPIO_U2CTRL_SIN1_SOUT1_EN;
+}
diff --git a/soc/ite/ec/it51xxx/soc.h b/soc/ite/ec/it51xxx/soc.h
new file mode 100644
index 00000000000..869206638dc
--- /dev/null
+++ b/soc/ite/ec/it51xxx/soc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __RISCV_ITE_SOC_H_
+#define __RISCV_ITE_SOC_H_
+
+#include <soc_common.h>
+
+#endif /* __RISCV_ITE_SOC_H_ */
diff --git a/soc/ite/ec/it51xxx/vector.S b/soc/ite/ec/it51xxx/vector.S
new file mode 100644
index 00000000000..74d33f894c7
--- /dev/null
+++ b/soc/ite/ec/it51xxx/vector.S
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/toolchain.h>
+
+/* exports */
+GTEXT(__start)
+
+/* imports */
+GTEXT(__initialize)
+GTEXT(_isr_wrapper)
+
+SECTION_FUNC(vectors, __start)
+#ifdef CONFIG_RISCV_GP
+	.option push
+	.option norelax
+	/* Configure the GP register */
+	la gp, __global_pointer$
+	.option pop
+#endif
+
+	.option norvc;
+	/*
+	 * Set mtvec (Machine Trap-Vector Base-Address Register)
+	 * to _isr_wrapper.
+	 */
+	la t0, _isr_wrapper
+	csrw mtvec, t0
+	csrwi mie, 0
+	/* Jump to __initialize */
+	tail __initialize
+
+/*
+ * eflash signature used to enable specific function after power-on reset.
+ * (HW mechanism)
+ * The content of 16-bytes must be the following and at offset 0x40 of binary.
+ * ----------------------------------------------------------------------------
+ * 1st 2nd 3rd 4th 5th 6th 7th    8th    9th 10th 11th 12th 13th 14th 15th 16th
+ * ----------------------------------------------------------------------------
+ * A5h A5h A5h A5h A5h A5h [host] [flag] 85h  12h  5Ah  5Ah  AAh  AAh  55h  55h
+ * ----------------------------------------------------------------------------
+ * 7th [host]: A4h = enable eSPI, A5h = enable LPC
+ */
+.org 0x40
+.balign 16
+.global eflash_sig
+eflash_sig:
+.byte 0xA5, 0xA5, 0xA5, 0xA5, 0xA5, 0xA5
+/* Enable eSPI */
+.byte 0xA4
+/* Flag of signature. Enable internal clock generator */
+.byte 0xB4
+.byte 0x85, 0x12, 0x5A, 0x5A, 0xAA, 0xAA, 0x55, 0x55
diff --git a/soc/ite/ec/it8xxx2/CMakeLists.txt b/soc/ite/ec/it8xxx2/CMakeLists.txt
index 425642c1727..9d101f2b83a 100644
--- a/soc/ite/ec/it8xxx2/CMakeLists.txt
+++ b/soc/ite/ec/it8xxx2/CMakeLists.txt
@@ -1,4 +1,4 @@
-zephyr_sources(soc.c)
+zephyr_sources(soc.c check_regs.c vector.S)
 zephyr_include_directories(.)
 
 zephyr_library_sources_ifndef(CONFIG_RISCV_ISA_EXT_M __arithmetic.S)
diff --git a/soc/ite/ec/it8xxx2/Kconfig b/soc/ite/ec/it8xxx2/Kconfig
index 739278e97f9..c959e886d27 100644
--- a/soc/ite/ec/it8xxx2/Kconfig
+++ b/soc/ite/ec/it8xxx2/Kconfig
@@ -7,6 +7,7 @@ config SOC_SERIES_IT8XXX2
 	select ARCH_HAS_CUSTOM_CPU_IDLE
 	select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
 	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
+	select SOC_PREP_HOOK
 
 if SOC_SERIES_IT8XXX2
 
diff --git a/soc/ite/ec/common/check_regs.c b/soc/ite/ec/it8xxx2/check_regs.c
similarity index 94%
rename from soc/ite/ec/common/check_regs.c
rename to soc/ite/ec/it8xxx2/check_regs.c
index 2fb6dcb4128..5c0a74891ce 100644
--- a/soc/ite/ec/common/check_regs.c
+++ b/soc/ite/ec/it8xxx2/check_regs.c
@@ -165,30 +165,23 @@ IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_rx_connect_state, 0x0E);
 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_sof_timer_msb, 0x0F);
 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[0].ep_ctrl, 0x40);
 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[0].ep_status, 0x41);
-IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
-	usb_ep_regs[EP0].ep_transtype_sts, 0x42);
-IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
-	usb_ep_regs[EP0].ep_nak_transtype_sts, 0x43);
+IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[EP0].ep_transtype_sts, 0x42);
+IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[EP0].ep_nak_transtype_sts, 0x43);
 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[3].ep_ctrl, 0x4C);
 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[3].ep_status, 0x4D);
-IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
-	usb_ep_regs[EP3].ep_transtype_sts, 0x4E);
-IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
-	usb_ep_regs[EP3].ep_nak_transtype_sts, 0x4F);
+IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[EP3].ep_transtype_sts, 0x4E);
+IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, usb_ep_regs[EP3].ep_nak_transtype_sts, 0x4F);
 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, dc_control, 0x50);
 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, dc_frame_num_lsp, 0x56);
 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[0].ep_rx_fifo_data, 0x60);
 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[0].ep_tx_fifo_ctrl, 0x74);
-IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
-	fifo_regs[EP_EXT_REGS_9X].ext_4_15.epn0n1_ext_ctrl, 0x98);
-IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
-	fifo_regs[EP_EXT_REGS_BX].fifo_ctrl.ep_fifo_ctrl, 0xB8);
-IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs,
-	fifo_regs[EP_EXT_REGS_DX].ext_0_3.epn_ext_ctrl, 0xD6);
+IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[EP_EXT_REGS_9X].ext_4_15.epn0n1_ext_ctrl,
+			 0x98);
+IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[EP_EXT_REGS_BX].fifo_ctrl.ep_fifo_ctrl, 0xB8);
+IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, fifo_regs[EP_EXT_REGS_DX].ext_0_3.epn_ext_ctrl, 0xD6);
 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, host_device_control, 0xE0);
 IT8XXX2_REG_OFFSET_CHECK(usb_it82xx2_regs, port1_misc_control, 0xE8);
 
-
 /* KSCAN register structure check */
 IT8XXX2_REG_SIZE_CHECK(kscan_it8xxx2_regs, 0x0F);
 IT8XXX2_REG_OFFSET_CHECK(kscan_it8xxx2_regs, KBS_KSOL, 0x00);
diff --git a/soc/ite/ec/it8xxx2/chip_chipregs.h b/soc/ite/ec/it8xxx2/chip_chipregs.h
new file mode 100644
index 00000000000..d7c9c1ca27e
--- /dev/null
+++ b/soc/ite/ec/it8xxx2/chip_chipregs.h
@@ -0,0 +1,2270 @@
+/*
+ * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef CHIP_CHIPREGS_H
+#define CHIP_CHIPREGS_H
+
+#include <zephyr/sys/util.h>
+
+#define EC_REG_BASE_ADDR 0x00f00000
+
+#ifdef _ASMLANGUAGE
+#define ECREG(x) x
+#else
+
+/*
+ * Macros for hardware registers access.
+ */
+#define ECREG(x)                   (*((volatile unsigned char *)(x)))
+#define ECREG_u16(x)               (*((volatile unsigned short *)(x)))
+#define ECREG_u32(x)               (*((volatile unsigned long *)(x)))
+
+/*
+ * MASK operation macros
+ */
+#define SET_MASK(reg, bit_mask)    ((reg) |= (bit_mask))
+#define CLEAR_MASK(reg, bit_mask)  ((reg) &= (~(bit_mask)))
+#define IS_MASK_SET(reg, bit_mask) (((reg) & (bit_mask)) != 0)
+#endif /* _ASMLANGUAGE */
+
+#ifndef REG_BASE_ADDR
+#define REG_BASE_ADDR EC_REG_BASE_ADDR
+#endif
+
+/* Common definition */
+/*
+ * EC clock frequency (PWM and tachometer driver need it to reply
+ * to api or calculate RPM)
+ */
+#ifdef CONFIG_SOC_IT8XXX2_EC_BUS_24MHZ
+#define EC_FREQ MHZ(24)
+#else
+#define EC_FREQ MHZ(8)
+
+#endif
+
+/* --- General Control (GCTRL) --- */
+#define IT8XXX2_GCTRL_BASE    0x00F02000
+#define IT8XXX2_GCTRL_EIDSR   ECREG(IT8XXX2_GCTRL_BASE + 0x31)
+#define IT8XXX2_GCTRL_PMER3   ECREG(IT8XXX2_GCTRL_BASE + 0x46)
+/* RISC-V JTAG Debug Interface Enable */
+#define IT8XXX2_GCTRL_JTAGEN  BIT(1)
+/* RISC-V JTAG Debug Interface Selection */
+#define IT8XXX2_GCTRL_JTAGSEL BIT(0)
+#define IT8XXX2_GCTRL_JTAG    (IT8XXX2_GCTRL_JTAGEN | IT8XXX2_GCTRL_JTAGSEL)
+
+#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
+#define IT8XXX2_JTAG_PINS_BASE ECREG(0xF01660)
+#define IT8XXX2_JTAG_VOLT_SET  ECREG(0xF01648)
+#elif CONFIG_SOC_IT8XXX2_REG_SET_V1
+#define IT8XXX2_JTAG_PINS_BASE ECREG(0xF01610)
+#define IT8XXX2_JTAG_VOLT_SET  ECREG(0xF016e9)
+#endif
+
+#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
+/* --- External GPIO Control (EGPIO) --- */
+#define IT8XXX2_EGPIO_BASE 0x00F02100
+#define IT8XXX2_EGPIO_EGCR ECREG(IT8XXX2_EGPIO_BASE + 0x04)
+
+/* EGPIO register fields */
+/*
+ * 0x04: External GPIO Control
+ * BIT(4): EXGPIO EGAD Pin Output Driving Disable
+ */
+#define IT8XXX2_EGPIO_EEPODD BIT(4)
+#endif
+
+/**
+ *
+ * (11xxh) Interrupt controller (INTC)
+ *
+ */
+#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
+#define ISR0  ECREG(EC_REG_BASE_ADDR + 0x3F00)
+#define ISR1  ECREG(EC_REG_BASE_ADDR + 0x3F01)
+#define ISR2  ECREG(EC_REG_BASE_ADDR + 0x3F02)
+#define ISR3  ECREG(EC_REG_BASE_ADDR + 0x3F03)
+#define ISR4  ECREG(EC_REG_BASE_ADDR + 0x3F14)
+#define ISR5  ECREG(EC_REG_BASE_ADDR + 0x3F18)
+#define ISR6  ECREG(EC_REG_BASE_ADDR + 0x3F1C)
+#define ISR7  ECREG(EC_REG_BASE_ADDR + 0x3F20)
+#define ISR8  ECREG(EC_REG_BASE_ADDR + 0x3F24)
+#define ISR9  ECREG(EC_REG_BASE_ADDR + 0x3F28)
+#define ISR10 ECREG(EC_REG_BASE_ADDR + 0x3F2C)
+#define ISR11 ECREG(EC_REG_BASE_ADDR + 0x3F30)
+#define ISR12 ECREG(EC_REG_BASE_ADDR + 0x3F34)
+#define ISR13 ECREG(EC_REG_BASE_ADDR + 0x3F38)
+#define ISR14 ECREG(EC_REG_BASE_ADDR + 0x3F3C)
+#define ISR15 ECREG(EC_REG_BASE_ADDR + 0x3F40)
+#define ISR16 ECREG(EC_REG_BASE_ADDR + 0x3F44)
+#define ISR17 ECREG(EC_REG_BASE_ADDR + 0x3F48)
+#define ISR18 ECREG(EC_REG_BASE_ADDR + 0x3F4C)
+#define ISR19 ECREG(EC_REG_BASE_ADDR + 0x3F50)
+#define ISR20 ECREG(EC_REG_BASE_ADDR + 0x3F54)
+#define ISR21 ECREG(EC_REG_BASE_ADDR + 0x3F58)
+#define ISR22 ECREG(EC_REG_BASE_ADDR + 0x3F5C)
+#define ISR23 ECREG(EC_REG_BASE_ADDR + 0x3F90)
+
+#define IER0  ECREG(EC_REG_BASE_ADDR + 0x3F04)
+#define IER1  ECREG(EC_REG_BASE_ADDR + 0x3F05)
+#define IER2  ECREG(EC_REG_BASE_ADDR + 0x3F06)
+#define IER3  ECREG(EC_REG_BASE_ADDR + 0x3F07)
+#define IER4  ECREG(EC_REG_BASE_ADDR + 0x3F15)
+#define IER5  ECREG(EC_REG_BASE_ADDR + 0x3F19)
+#define IER6  ECREG(EC_REG_BASE_ADDR + 0x3F1D)
+#define IER7  ECREG(EC_REG_BASE_ADDR + 0x3F21)
+#define IER8  ECREG(EC_REG_BASE_ADDR + 0x3F25)
+#define IER9  ECREG(EC_REG_BASE_ADDR + 0x3F29)
+#define IER10 ECREG(EC_REG_BASE_ADDR + 0x3F2D)
+#define IER11 ECREG(EC_REG_BASE_ADDR + 0x3F31)
+#define IER12 ECREG(EC_REG_BASE_ADDR + 0x3F35)
+#define IER13 ECREG(EC_REG_BASE_ADDR + 0x3F39)
+#define IER14 ECREG(EC_REG_BASE_ADDR + 0x3F3D)
+#define IER15 ECREG(EC_REG_BASE_ADDR + 0x3F41)
+#define IER16 ECREG(EC_REG_BASE_ADDR + 0x3F45)
+#define IER17 ECREG(EC_REG_BASE_ADDR + 0x3F49)
+#define IER18 ECREG(EC_REG_BASE_ADDR + 0x3F4D)
+#define IER19 ECREG(EC_REG_BASE_ADDR + 0x3F51)
+#define IER20 ECREG(EC_REG_BASE_ADDR + 0x3F55)
+#define IER21 ECREG(EC_REG_BASE_ADDR + 0x3F59)
+#define IER22 ECREG(EC_REG_BASE_ADDR + 0x3F5D)
+#define IER23 ECREG(EC_REG_BASE_ADDR + 0x3F91)
+
+#define IELMR0  ECREG(EC_REG_BASE_ADDR + 0x3F08)
+#define IELMR1  ECREG(EC_REG_BASE_ADDR + 0x3F09)
+#define IELMR2  ECREG(EC_REG_BASE_ADDR + 0x3F0A)
+#define IELMR3  ECREG(EC_REG_BASE_ADDR + 0x3F0B)
+#define IELMR4  ECREG(EC_REG_BASE_ADDR + 0x3F16)
+#define IELMR5  ECREG(EC_REG_BASE_ADDR + 0x3F1A)
+#define IELMR6  ECREG(EC_REG_BASE_ADDR + 0x3F1E)
+#define IELMR7  ECREG(EC_REG_BASE_ADDR + 0x3F22)
+#define IELMR8  ECREG(EC_REG_BASE_ADDR + 0x3F26)
+#define IELMR9  ECREG(EC_REG_BASE_ADDR + 0x3F2A)
+#define IELMR10 ECREG(EC_REG_BASE_ADDR + 0x3F2E)
+#define IELMR11 ECREG(EC_REG_BASE_ADDR + 0x3F32)
+#define IELMR12 ECREG(EC_REG_BASE_ADDR + 0x3F36)
+#define IELMR13 ECREG(EC_REG_BASE_ADDR + 0x3F3A)
+#define IELMR14 ECREG(EC_REG_BASE_ADDR + 0x3F3E)
+#define IELMR15 ECREG(EC_REG_BASE_ADDR + 0x3F42)
+#define IELMR16 ECREG(EC_REG_BASE_ADDR + 0x3F46)
+#define IELMR17 ECREG(EC_REG_BASE_ADDR + 0x3F4A)
+#define IELMR18 ECREG(EC_REG_BASE_ADDR + 0x3F4E)
+#define IELMR19 ECREG(EC_REG_BASE_ADDR + 0x3F52)
+#define IELMR20 ECREG(EC_REG_BASE_ADDR + 0x3F56)
+#define IELMR21 ECREG(EC_REG_BASE_ADDR + 0x3F5A)
+#define IELMR22 ECREG(EC_REG_BASE_ADDR + 0x3F5E)
+#define IELMR23 ECREG(EC_REG_BASE_ADDR + 0x3F92)
+
+#define IPOLR0  ECREG(EC_REG_BASE_ADDR + 0x3F0C)
+#define IPOLR1  ECREG(EC_REG_BASE_ADDR + 0x3F0D)
+#define IPOLR2  ECREG(EC_REG_BASE_ADDR + 0x3F0E)
+#define IPOLR3  ECREG(EC_REG_BASE_ADDR + 0x3F0F)
+#define IPOLR4  ECREG(EC_REG_BASE_ADDR + 0x3F17)
+#define IPOLR5  ECREG(EC_REG_BASE_ADDR + 0x3F1B)
+#define IPOLR6  ECREG(EC_REG_BASE_ADDR + 0x3F1F)
+#define IPOLR7  ECREG(EC_REG_BASE_ADDR + 0x3F23)
+#define IPOLR8  ECREG(EC_REG_BASE_ADDR + 0x3F27)
+#define IPOLR9  ECREG(EC_REG_BASE_ADDR + 0x3F2B)
+#define IPOLR10 ECREG(EC_REG_BASE_ADDR + 0x3F2F)
+#define IPOLR11 ECREG(EC_REG_BASE_ADDR + 0x3F33)
+#define IPOLR12 ECREG(EC_REG_BASE_ADDR + 0x3F37)
+#define IPOLR13 ECREG(EC_REG_BASE_ADDR + 0x3F3B)
+#define IPOLR14 ECREG(EC_REG_BASE_ADDR + 0x3F3F)
+#define IPOLR15 ECREG(EC_REG_BASE_ADDR + 0x3F43)
+#define IPOLR16 ECREG(EC_REG_BASE_ADDR + 0x3F47)
+#define IPOLR17 ECREG(EC_REG_BASE_ADDR + 0x3F4B)
+#define IPOLR18 ECREG(EC_REG_BASE_ADDR + 0x3F4F)
+#define IPOLR19 ECREG(EC_REG_BASE_ADDR + 0x3F53)
+#define IPOLR20 ECREG(EC_REG_BASE_ADDR + 0x3F57)
+#define IPOLR21 ECREG(EC_REG_BASE_ADDR + 0x3F5B)
+#define IPOLR22 ECREG(EC_REG_BASE_ADDR + 0x3F5F)
+#define IPOLR23 ECREG(EC_REG_BASE_ADDR + 0x3F93)
+#endif
+#define IVECT ECREG(EC_REG_BASE_ADDR + 0x3F10)
+
+/*
+ * TODO: use pinctrl node instead of following register declarations
+ *       to fix in tcpm\it83xx_pd.h.
+ */
+/* GPIO control register */
+#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
+#define IT8XXX2_GPIO_GPCRB3 ECREG(EC_REG_BASE_ADDR + 0x161B)
+#define IT8XXX2_GPIO_GPCRB4 ECREG(EC_REG_BASE_ADDR + 0x161C)
+#define GPCRF4              ECREG(EC_REG_BASE_ADDR + 0x163C)
+#define GPCRF5              ECREG(EC_REG_BASE_ADDR + 0x163D)
+#define GPCRH1              ECREG(EC_REG_BASE_ADDR + 0x1649)
+#define GPCRH2              ECREG(EC_REG_BASE_ADDR + 0x164A)
+#elif CONFIG_SOC_IT8XXX2_REG_SET_V2
+#define GPCRF4 ECREG(EC_REG_BASE_ADDR + 0x168C)
+#define GPCRF5 ECREG(EC_REG_BASE_ADDR + 0x168D)
+#define GPCRH1 ECREG(EC_REG_BASE_ADDR + 0x1699)
+#define GPCRH2 ECREG(EC_REG_BASE_ADDR + 0x169A)
+#endif
+
+/*
+ * IT8XXX2 register structure size/offset checking macro function to mitigate
+ * the risk of unexpected compiling results.
+ */
+#define IT8XXX2_REG_SIZE_CHECK(reg_def, size)                                                      \
+	BUILD_ASSERT(sizeof(struct reg_def) == size, "Failed in size check of register "           \
+						     "structure!")
+#define IT8XXX2_REG_OFFSET_CHECK(reg_def, member, offset)                                          \
+	BUILD_ASSERT(offsetof(struct reg_def, member) == offset,                                   \
+		     "Failed in offset check of register structure member!")
+
+/**
+ *
+ * (18xxh) PWM & SmartAuto Fan Control (PWM)
+ *
+ */
+#ifndef __ASSEMBLER__
+struct pwm_it8xxx2_regs {
+	/* 0x000: Channel0 Clock Prescaler */
+	volatile uint8_t C0CPRS;
+	/* 0x001: Cycle Time0 */
+	volatile uint8_t CTR;
+	/* 0x002~0x00A: Reserved1 */
+	volatile uint8_t Reserved1[9];
+	/* 0x00B: Prescaler Clock Frequency Select */
+	volatile uint8_t PCFSR;
+	/* 0x00C~0x00F: Reserved2 */
+	volatile uint8_t Reserved2[4];
+	/* 0x010: Cycle Time1 MSB */
+	volatile uint8_t CTR1M;
+	/* 0x011~0x022: Reserved3 */
+	volatile uint8_t Reserved3[18];
+	/* 0x023: PWM Clock Control */
+	volatile uint8_t ZTIER;
+	/* 0x024~0x026: Reserved4 */
+	volatile uint8_t Reserved4[3];
+	/* 0x027: Channel4 Clock Prescaler */
+	volatile uint8_t C4CPRS;
+	/* 0x028: Channel4 Clock Prescaler MSB */
+	volatile uint8_t C4MCPRS;
+	/* 0x029~0x02A: Reserved5 */
+	volatile uint8_t Reserved5[2];
+	/* 0x02B: Channel6 Clock Prescaler */
+	volatile uint8_t C6CPRS;
+	/* 0x02C: Channel6 Clock Prescaler MSB */
+	volatile uint8_t C6MCPRS;
+	/* 0x02D: Channel7 Clock Prescaler */
+	volatile uint8_t C7CPRS;
+	/* 0x02E: Channel7 Clock Prescaler MSB */
+	volatile uint8_t C7MCPRS;
+	/* 0x02F~0x040: Reserved6 */
+	volatile uint8_t reserved6[18];
+	/* 0x041: Cycle Time1 */
+	volatile uint8_t CTR1;
+	/* 0x042: Cycle Time2 */
+	volatile uint8_t CTR2;
+	/* 0x043: Cycle Time3 */
+	volatile uint8_t CTR3;
+	/* 0x044~0x048: Reserved7 */
+	volatile uint8_t reserved7[5];
+	/* 0x049: PWM Output Open-Drain Enable */
+	volatile uint8_t PWMODENR;
+};
+#endif /* !__ASSEMBLER__ */
+
+/* PWM register fields */
+/* 0x023: PWM Clock Control */
+#define IT8XXX2_PWM_PCCE    BIT(1)
+/* 0x048: Tachometer Switch Control */
+#define IT8XXX2_PWM_T0DVS   BIT(3)
+#define IT8XXX2_PWM_T0CHSEL BIT(2)
+#define IT8XXX2_PWM_T1DVS   BIT(1)
+#define IT8XXX2_PWM_T1CHSEL BIT(0)
+
+/* --- Wake-Up Control (WUC) --- */
+#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
+#define IT8XXX2_WUC_BASE 0x00F01B00
+
+/* TODO: should a defined interface for configuring wake-up interrupts */
+#define IT8XXX2_WUC_WUEMR1  (IT8XXX2_WUC_BASE + 0x00)
+#define IT8XXX2_WUC_WUEMR5  (IT8XXX2_WUC_BASE + 0x0c)
+#define IT8XXX2_WUC_WUESR1  (IT8XXX2_WUC_BASE + 0x04)
+#define IT8XXX2_WUC_WUESR5  (IT8XXX2_WUC_BASE + 0x0d)
+#define IT8XXX2_WUC_WUBEMR1 (IT8XXX2_WUC_BASE + 0x3c)
+#define IT8XXX2_WUC_WUBEMR5 (IT8XXX2_WUC_BASE + 0x0f)
+#endif
+
+/**
+ *
+ * (1Dxxh) Keyboard Matrix Scan control (KSCAN)
+ *
+ */
+#ifndef __ASSEMBLER__
+struct kscan_it8xxx2_regs {
+	/* 0x000: Keyboard Scan Out */
+	volatile uint8_t KBS_KSOL;
+	/* 0x001: Keyboard Scan Out */
+	volatile uint8_t KBS_KSOH1;
+	/* 0x002: Keyboard Scan Out Control */
+	volatile uint8_t KBS_KSOCTRL;
+	/* 0x003: Keyboard Scan Out */
+	volatile uint8_t KBS_KSOH2;
+	/* 0x004: Keyboard Scan In */
+	volatile uint8_t KBS_KSI;
+	/* 0x005: Keyboard Scan In Control */
+	volatile uint8_t KBS_KSICTRL;
+	/* 0x006: Keyboard Scan In [7:0] GPIO Control */
+	volatile uint8_t KBS_KSIGCTRL;
+	/* 0x007: Keyboard Scan In [7:0] GPIO Output Enable */
+	volatile uint8_t KBS_KSIGOEN;
+	/* 0x008: Keyboard Scan In [7:0] GPIO Data */
+	volatile uint8_t KBS_KSIGDAT;
+	/* 0x009: Keyboard Scan In [7:0] GPIO Data Mirror */
+	volatile uint8_t KBS_KSIGDMRR;
+	/* 0x00A: Keyboard Scan Out [15:8] GPIO Control */
+	volatile uint8_t KBS_KSOHGCTRL;
+	/* 0x00B: Keyboard Scan Out [15:8] GPIO Output Enable */
+	volatile uint8_t KBS_KSOHGOEN;
+	/* 0x00C: Keyboard Scan Out [15:8] GPIO Data Mirror */
+	volatile uint8_t KBS_KSOHGDMRR;
+	/* 0x00D: Keyboard Scan Out [7:0] GPIO Control */
+	volatile uint8_t KBS_KSOLGCTRL;
+	/* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */
+	volatile uint8_t KBS_KSOLGOEN;
+};
+#endif /* !__ASSEMBLER__ */
+
+/* KBS register fields */
+/* 0x002: Keyboard Scan Out Control */
+#define IT8XXX2_KBS_KSOPU     BIT(2)
+#define IT8XXX2_KBS_KSOOD     BIT(0)
+/* 0x005: Keyboard Scan In Control */
+#define IT8XXX2_KBS_KSIPU     BIT(2)
+/* 0x00D: Keyboard Scan Out [7:0] GPIO Control */
+#define IT8XXX2_KBS_KSO2GCTRL BIT(2)
+/* 0x00E: Keyboard Scan Out [7:0] GPIO Output Enable */
+#define IT8XXX2_KBS_KSO2GOEN  BIT(2)
+
+/**
+ *
+ * (1Fxxh) External Timer & External Watchdog (ETWD)
+ *
+ */
+#define WDT_IT8XXX2_REGS_BASE ((struct wdt_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(twd0)))
+
+#ifndef __ASSEMBLER__
+struct wdt_it8xxx2_regs {
+	/* 0x000: Reserved1 */
+	volatile uint8_t reserved1;
+	/* 0x001: External Timer1/WDT Configuration */
+	volatile uint8_t ETWCFG;
+	/* 0x002: External Timer1 Prescaler */
+	volatile uint8_t ET1PSR;
+	/* 0x003: External Timer1 Counter High Byte */
+	volatile uint8_t ET1CNTLHR;
+	/* 0x004: External Timer1 Counter Low Byte */
+	volatile uint8_t ET1CNTLLR;
+	/* 0x005: External Timer1/WDT Control */
+	volatile uint8_t ETWCTRL;
+	/* 0x006: External WDT Counter Low Byte */
+	volatile uint8_t EWDCNTLR;
+	/* 0x007: External WDT Key */
+	volatile uint8_t EWDKEYR;
+	/* 0x008: Reserved2 */
+	volatile uint8_t reserved2;
+	/* 0x009: External WDT Counter High Byte */
+	volatile uint8_t EWDCNTHR;
+	/* 0x00A: External Timer2 Prescaler */
+	volatile uint8_t ET2PSR;
+	/* 0x00B: External Timer2 Counter High Byte */
+	volatile uint8_t ET2CNTLHR;
+	/* 0x00C: External Timer2 Counter Low Byte */
+	volatile uint8_t ET2CNTLLR;
+	/* 0x00D: Reserved3 */
+	volatile uint8_t reserved3;
+	/* 0x00E: External Timer2 Counter High Byte2 */
+	volatile uint8_t ET2CNTLH2R;
+};
+#endif /* !__ASSEMBLER__ */
+
+/* WDT register fields */
+/* 0x001: External Timer1/WDT Configuration */
+#define IT8XXX2_WDT_EWDKEYEN        BIT(5)
+#define IT8XXX2_WDT_EWDSRC          BIT(4)
+#define IT8XXX2_WDT_LEWDCNTL        BIT(3)
+#define IT8XXX2_WDT_LET1CNTL        BIT(2)
+#define IT8XXX2_WDT_LET1PS          BIT(1)
+#define IT8XXX2_WDT_LETWCFG         BIT(0)
+/* 0x002: External Timer1 Prescaler */
+#define IT8XXX2_WDT_ETPS_32P768_KHZ 0x00
+#define IT8XXX2_WDT_ETPS_1P024_KHZ  0x01
+#define IT8XXX2_WDT_ETPS_32_HZ      0x02
+/* 0x005: External Timer1/WDT Control */
+#define IT8XXX2_WDT_EWDSCEN         BIT(5)
+#define IT8XXX2_WDT_EWDSCMS         BIT(4)
+#define IT8XXX2_WDT_ET2TC           BIT(3)
+#define IT8XXX2_WDT_ET2RST          BIT(2)
+#define IT8XXX2_WDT_ET1TC           BIT(1)
+#define IT8XXX2_WDT_ET1RST          BIT(0)
+
+/* External Timer register fields */
+/* External Timer 3~8 control */
+#define IT8XXX2_EXT_ETX_COMB_RST_EN (IT8XXX2_EXT_ETXCOMB | IT8XXX2_EXT_ETXRST | IT8XXX2_EXT_ETXEN)
+#define IT8XXX2_EXT_ETXCOMB         BIT(3)
+#define IT8XXX2_EXT_ETXRST          BIT(1)
+#define IT8XXX2_EXT_ETXEN           BIT(0)
+
+/* Control external timer3~8 */
+#define IT8XXX2_EXT_TIMER_BASE DT_REG_ADDR(DT_NODELABEL(timer)) /*0x00F01F10*/
+#define IT8XXX2_EXT_CTRLX(n)   ECREG(IT8XXX2_EXT_TIMER_BASE + (n << 3))
+#define IT8XXX2_EXT_PSRX(n)    ECREG(IT8XXX2_EXT_TIMER_BASE + 0x01 + (n << 3))
+#define IT8XXX2_EXT_CNTX(n)    ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x04 + (n << 3))
+#define IT8XXX2_EXT_CNTOX(n)   ECREG_u32(IT8XXX2_EXT_TIMER_BASE + 0x38 + (n << 2))
+
+/* Free run timer configurations */
+#define FREE_RUN_TIMER         EXT_TIMER_4
+#define FREE_RUN_TIMER_IRQ     DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, irq)
+/* Free run timer configurations */
+#define FREE_RUN_TIMER_FLAG    DT_IRQ_BY_IDX(DT_NODELABEL(timer), 1, flags)
+/* Free run timer max count is 36.4 hr (base on clock source 32768Hz) */
+#define FREE_RUN_TIMER_MAX_CNT 0xFFFFFFFFUL
+
+#ifndef __ASSEMBLER__
+enum ext_clk_src_sel {
+	EXT_PSR_32P768K = 0,
+	EXT_PSR_1P024K,
+	EXT_PSR_32,
+	EXT_PSR_EC_CLK,
+};
+/*
+ * 24-bit timers: external timer 3, 5, and 7
+ * 32-bit timers: external timer 4, 6, and 8
+ */
+enum ext_timer_idx {
+	EXT_TIMER_3 = 0, /* Event timer */
+	EXT_TIMER_4,     /* Free run timer */
+	EXT_TIMER_5,     /* Busy wait low timer */
+	EXT_TIMER_6,     /* Busy wait high timer */
+	EXT_TIMER_7,
+	EXT_TIMER_8,
+};
+#endif
+
+/*
+ *
+ * (2Cxxh) Platform Environment Control Interface (PECI)
+ *
+ */
+#ifndef __ASSEMBLER__
+struct peci_it8xxx2_regs {
+	/* 0x00: Host Status */
+	volatile uint8_t HOSTAR;
+	/* 0x01: Host Control */
+	volatile uint8_t HOCTLR;
+	/* 0x02: Host Command */
+	volatile uint8_t HOCMDR;
+	/* 0x03: Host Target Address */
+	volatile uint8_t HOTRADDR;
+	/* 0x04: Host Write Length */
+	volatile uint8_t HOWRLR;
+	/* 0x05: Host Read Length */
+	volatile uint8_t HORDLR;
+	/* 0x06: Host Write Data */
+	volatile uint8_t HOWRDR;
+	/* 0x07: Host Read Data */
+	volatile uint8_t HORDDR;
+	/* 0x08: Host Control 2 */
+	volatile uint8_t HOCTL2R;
+	/* 0x09: Received Write FCS value */
+	volatile uint8_t RWFCSV;
+	/* 0x0A: Received Read FCS value */
+	volatile uint8_t RRFCSV;
+	/* 0x0B: Write FCS Value */
+	volatile uint8_t WFCSV;
+	/* 0x0C: Read FCS Value */
+	volatile uint8_t RFCSV;
+	/* 0x0D: Assured Write FCS Value */
+	volatile uint8_t AWFCSV;
+	/* 0x0E: Pad Control */
+	volatile uint8_t PADCTLR;
+};
+#endif /* !__ASSEMBLER__ */
+
+/**
+ *
+ * (2Fxxh) USB Device Controller (USBDC) Registers
+ *
+ */
+#define EP_EXT_REGS_9X 1
+#define EP_EXT_REGS_BX 2
+#define EP_EXT_REGS_DX 3
+
+#ifndef __ASSEMBLER__
+
+/* EP0 to EP15 Enumeration */
+enum usb_dc_endpoints {
+	EP0,
+	EP1,
+	EP2,
+	EP3,
+	EP4,
+	EP5,
+	EP6,
+	EP7,
+	EP8,
+	EP9,
+	EP10,
+	EP11,
+	EP12,
+	EP13,
+	EP14,
+	EP15,
+	MAX_NUM_ENDPOINTS
+};
+
+union ep_ctrl_reg {
+	volatile uint8_t value;
+	struct {
+		volatile uint8_t enable_bit: 1;
+		volatile uint8_t ready_bit: 1;
+		volatile uint8_t outdata_sequence_bit: 1;
+		volatile uint8_t send_stall_bit: 1;
+		volatile uint8_t iso_enable_bit: 1;
+		volatile uint8_t direction_bit: 1;
+		volatile uint8_t reserved: 2;
+	} __packed fields;
+} __packed;
+
+struct it82xx2_usb_ep_regs {
+	union ep_ctrl_reg ep_ctrl;
+	volatile uint8_t ep_status;
+	volatile uint8_t ep_transtype_sts;
+	volatile uint8_t ep_nak_transtype_sts;
+};
+
+/* Reserved EP Extended Registers */
+struct ep_ext_regs_7x {
+	/* 0x75 Reserved */
+	volatile uint8_t ep_ext_ctrl_75;
+	/* 0x76 Reserved */
+	volatile uint8_t ep_ext_ctrl_76;
+	/* 0x77 Reserved */
+	volatile uint8_t ep_ext_ctrl_77;
+	/* 0x78 Reserved */
+	volatile uint8_t ep_ext_ctrl_78;
+	/* 0x79 Reserved */
+	volatile uint8_t ep_ext_ctrl_79;
+	/* 0x7A Reserved */
+	volatile uint8_t ep_ext_ctrl_7a;
+	/* 0x7B Reserved */
+	volatile uint8_t ep_ext_ctrl_7b;
+	/* 0x7C Reserved */
+	volatile uint8_t ep_ext_ctrl_7c;
+	/* 0x7D Reserved */
+	volatile uint8_t ep_ext_ctrl_7d;
+	/* 0x7E Reserved */
+	volatile uint8_t ep_ext_ctrl_7e;
+	/* 0x7F Reserved */
+	volatile uint8_t ep_ext_ctrl_7f;
+};
+
+/* From 98h to 9Dh, the EP45/67/89/1011/1213/1415 Extended Control Registers
+ * are defined, and their bits definitions are as follows:
+ *
+ * Bit    Description
+ *  7     Reserved
+ *  6     EPPOINT5_ISO_ENABLE
+ *  5     EPPOINT5_SEND_STALL
+ *  4     EPPOINT5_OUT_DATA_SEQUENCE
+ *  3     Reserved
+ *  2     EPPOINT4_ISO_ENABLE
+ *  1     EPPOINT4_SEND_STALL
+ *  0     EPPOINT4_OUT_DATA_SEQUENCE
+ *
+ * Apparently, we can tell that the EP4 and EP5 share the same register, and
+ * the EP6 and EP7 share the same one, and the rest EPs are defined in the
+ * same way.
+ */
+union epn0n1_extend_ctrl_reg {
+	volatile uint8_t value;
+	struct {
+		volatile uint8_t epn0_outdata_sequence_bit: 1;
+		volatile uint8_t epn0_send_stall_bit: 1;
+		volatile uint8_t epn0_iso_enable_bit: 1;
+		volatile uint8_t reserved0: 1;
+		volatile uint8_t epn1_outdata_sequence_bit: 1;
+		volatile uint8_t epn1_send_stall_bit: 1;
+		volatile uint8_t epn1_iso_enable_bit: 1;
+		volatile uint8_t reserved1: 1;
+	} __packed fields;
+} __packed;
+
+struct ep_ext_regs_9x {
+	/* 0x95 Reserved */
+	volatile uint8_t ep_ext_ctrl_95;
+	/* 0x96 Reserved */
+	volatile uint8_t ep_ext_ctrl_96;
+	/* 0x97 Reserved */
+	volatile uint8_t ep_ext_ctrl_97;
+	/* 0x98 ~ 0x9D EP45/67/89/1011/1213/1415 Extended Control Registers */
+	union epn0n1_extend_ctrl_reg epn0n1_ext_ctrl[6];
+	/* 0x9E Reserved */
+	volatile uint8_t ep_ext_ctrl_9e;
+	/* 0x9F Reserved */
+	volatile uint8_t ep_ext_ctrl_9f;
+};
+
+/* From BXh to BDh are EP FIFO 1-3 Control 0/1 Registers, and their
+ * definitions as follows:
+ * B8h: EP_FIFO1_CONTROL0_REG
+ * B9h: EP_FIFO1_CONTROL1_REG
+ * BAh: EP_FIFO2_CONTROL0_REG
+ * BBh: EP_FIFO2_CONTROL1_REG
+ * BCh: EP_FIFO3_CONTROL0_REG
+ * BDh: EP_FIFO3_CONTROL1_REG
+ *
+ * For each one, its bits definitions are as follows:
+ * (take EP_FIFO1_CONTROL1_REG as example, which controls from EP8 to EP15)
+ *
+ * Bit  Description
+ *
+ *  7   EP15 select FIFO1 as data buffer
+ *  6   EP14 select FIFO1 as data buffer
+ *  5   EP13 select FIFO1 as data buffer
+ *  4   EP12 select FIFO1 as data buffer
+ *  3   EP11 select FIFO1 as data buffer
+ *  2   EP10 select FIFO1 as data buffer
+ *  1   EP9 select FIFO1 as data buffer
+ *  0   EP8 select FIFO1 as data buffer
+ *
+ *  1: Select
+ *  0: Not select
+ */
+struct ep_ext_regs_bx {
+	/* 0xB5 Reserved */
+	volatile uint8_t ep_ext_ctrl_b5;
+	/* 0xB6 Reserved */
+	volatile uint8_t ep_ext_ctrl_b6;
+	/* 0xB7 Reserved */
+	volatile uint8_t ep_ext_ctrl_b7;
+	/* 0xB8 ~ 0xBD EP FIFO 1-3 Control 0/1 Registers */
+	volatile uint8_t ep_fifo_ctrl[6];
+	/* 0xBE Reserved */
+	volatile uint8_t ep_ext_ctrl_be;
+	/* 0xBF Reserved */
+	volatile uint8_t ep_ext_ctrl_bf;
+};
+
+/* From D6h to DDh are EP Extended Control Registers, and their
+ * definitions as follows:
+ * D6h: EP0_EXT_CTRL1
+ * D7h: EP0_EXT_CTRL2
+ * D8h: EP1_EXT_CTRL1
+ * D9h: EP1_EXT_CTRL2
+ * DAh: EP2_EXT_CTRL1
+ * DBh: EP2_EXT_CTRL2
+ * DCh: EP3_EXT_CTRL1
+ * DDh: EP3_EXT_CTRL2
+ *
+ * We classify them into 4 groups which each of them contains Control 1 and 2
+ * according to the EP number as follows:
+ */
+union epn_extend_ctrl1_reg {
+	volatile uint8_t value;
+	struct {
+		volatile uint8_t epn0_enable_bit: 1;
+		volatile uint8_t epn0_direction_bit: 1;
+		volatile uint8_t epn3_enable_bit: 1;
+		volatile uint8_t epn3_direction_bit: 1;
+		volatile uint8_t epn6_enable_bit: 1;
+		volatile uint8_t epn6_direction_bit: 1;
+		volatile uint8_t epn9_enable_bit: 1;
+		volatile uint8_t epn9_direction_bit: 1;
+	} __packed fields;
+} __packed;
+
+struct epn_ext_ctrl_regs {
+	/* 0xD6/0xD8/0xDA/0xDC EPN Extended Control1 Register */
+	union epn_extend_ctrl1_reg epn_ext_ctrl1;
+	/* 0xD7/0xD9/0xDB/0xDD EPB Extended Control2 Register */
+	volatile uint8_t epn_ext_ctrl2;
+};
+
+struct ep_ext_regs_dx {
+	/* 0xD5 Reserved */
+	volatile uint8_t ep_ext_ctrl_d5;
+	/* 0xD6 ~ 0xDD EPN Extended Control 1/2 Registers */
+	struct epn_ext_ctrl_regs epn_ext_ctrl[4];
+	/* 0xDE Reserved */
+	volatile uint8_t ep_ext_ctrl_de;
+	/* 0xDF Reserved */
+	volatile uint8_t ep_ext_ctrl_df;
+};
+
+/* The USB EPx FIFO Registers Definitions
+ * EP0: 60h ~ 74h
+ * EP1: 80h ~ 94h
+ * EP2: A0h ~ B4h
+ * EP3: C0h ~ D4h (D6h to DDh will be defined as marcos for usage)
+ */
+struct it82xx2_usb_ep_fifo_regs {
+	/* 0x60 + ep * 0x20 : EP RX FIFO Data Register  */
+	volatile uint8_t ep_rx_fifo_data;
+	/* 0x61 + ep * 0x20 : EP RX FIFO DMA Count Register */
+	volatile uint8_t ep_rx_fifo_dma_count;
+	/* 0x62 + ep * 0x20 : EP RX FIFO Data Count MSB */
+	volatile uint8_t ep_rx_fifo_dcnt_msb;
+	/* 0x63 + ep * 0x20 : EP RX FIFO Data Count LSB */
+	volatile uint8_t ep_rx_fifo_dcnt_lsb;
+	/* 0x64 + ep * 0x20  : EP RX FIFO Control Register */
+	volatile uint8_t ep_rx_fifo_ctrl;
+	/* (0x65 ~ 0x6F) + ep * 0x20 */
+	volatile uint8_t reserved_65_6f_add_20[11];
+	/* 0x70 + ep * 0x20 : EP TX FIFO Data Register  */
+	volatile uint8_t ep_tx_fifo_data;
+	/* (0x71 ~ 0x73) + ep * 0x20 */
+	volatile uint8_t reserved_71_73_add_20[3];
+	/* 0x74 + ep * 0x20 : EP TX FIFO Control Register */
+	volatile uint8_t ep_tx_fifo_ctrl;
+	/* (0x75 ~ 0x7F) + ep * 0x20 */
+	union {
+		struct ep_ext_regs_7x ep_res;
+		struct ep_ext_regs_9x ext_4_15;
+		struct ep_ext_regs_bx fifo_ctrl;
+		struct ep_ext_regs_dx ext_0_3;
+	};
+};
+
+/* USB Control registers */
+#define USB_IT82XX2_REGS_BASE ((struct usb_it82xx2_regs *)DT_REG_ADDR(DT_NODELABEL(usb0)))
+
+/* Bit definitions of the register Port0/Port1 MISC Control: 0XE4/0xE8 */
+#define PULL_DOWN_EN BIT(4)
+
+struct usb_it82xx2_regs {
+	/* 0x00:  Host TX Contrl Register */
+	volatile uint8_t host_tx_ctrl;
+	/* 0x01:  Host TX Transaction Type Register */
+	volatile uint8_t host_tx_trans_type;
+	/* 0x02:  Host TX Line Control Register */
+	volatile uint8_t host_tx_line_ctrl;
+	/* 0x03:  Host TX SOF Enable Register */
+	volatile uint8_t host_tx_sof_enable;
+	/* 0x04:  Host TX Address Register */
+	volatile uint8_t host_tx_addr;
+	/* 0x05:  Host TX EP Number Register */
+	volatile uint8_t host_tx_endp;
+	/* 0x06:  Host Frame Number MSP Register */
+	volatile uint8_t host_frame_num_msp;
+	/* 0x07:  Host Frame Number LSP Register */
+	volatile uint8_t host_frame_num_lsp;
+	/* 0x08:  Host Interrupt Status Register */
+	volatile uint8_t host_interrupt_status;
+	/* 0x09:  Host Interrupt Mask Register */
+	volatile uint8_t host_interrupt_mask;
+	/* 0x0A:  Host RX Status Register */
+	volatile uint8_t host_rx_status;
+	/* 0x0B:  Host RX PID Register */
+	volatile uint8_t host_rx_pid;
+	/* 0x0C:  MISC Control Register */
+	volatile uint8_t misc_control;
+	/* 0x0D:  MISC Status Register */
+	volatile uint8_t misc_status;
+	/* 0x0E:  Host RX Connect State Register */
+	volatile uint8_t host_rx_connect_state;
+	/* 0x0F:  Host SOF Timer MSB Register */
+	volatile uint8_t host_sof_timer_msb;
+	/* 0x10 ~ 0x1F:  Reserved Registers 10h - 1Fh */
+	volatile uint8_t reserved_10_1f[16];
+	/* 0x20:  Host RX FIFO Data Port Register */
+	volatile uint8_t host_rx_fifo_data;
+	/* 0x21:  Host RX FIFO DMA Input Data Count Register */
+	volatile uint8_t host_rx_fifo_dma_data_count;
+	/* 0x22:  Host TX FIFO Data Count MSB Register */
+	volatile uint8_t host_rx_fifo_data_count_msb;
+	/* 0x23:  Host TX FIFO Data Count LSB Register */
+	volatile uint8_t host_rx_fifo_data_count_lsb;
+	/* 0x24:  Host RX FIFO Data Port Register */
+	volatile uint8_t host_rx_fifo_control;
+	/* 0x25 ~ 0x2F:  Reserved Registers 25h - 2Fh */
+	volatile uint8_t reserved_25_2f[11];
+	/* 0x30:  Host TX FIFO Data Port Register */
+	volatile uint8_t host_tx_fifo_data;
+	/* 0x31 ~ 0x3F:  Reserved Registers 31h - 3Fh */
+	volatile uint8_t reserved_31_3f[15];
+	/* 0x40 ~ 0x4F: Endpoint Registers 40h - 4Fh */
+	struct it82xx2_usb_ep_regs usb_ep_regs[4];
+	/* 0x50:  Device Controller Control Register */
+	volatile uint8_t dc_control;
+	/* 0x51:  Device Controller LINE Status Register */
+	volatile uint8_t dc_line_status;
+	/* 0x52:  Device Controller Interrupt Status Register */
+	volatile uint8_t dc_interrupt_status;
+	/* 0x53:  Device Controller Interrupt Mask Register */
+	volatile uint8_t dc_interrupt_mask;
+	/* 0x54:  Device Controller Address Register */
+	volatile uint8_t dc_address;
+	/* 0x55:  Device Controller Frame Number MSP Register */
+	volatile uint8_t dc_frame_num_msp;
+	/* 0x56:  Device Controller Frame Number LSP Register */
+	volatile uint8_t dc_frame_num_lsp;
+	/* 0x57 ~ 0x5F:  Reserved Registers 57h - 5Fh */
+	volatile uint8_t reserved_57_5f[9];
+	/* 0x60 ~ 0xDF: EP FIFO Registers 60h - DFh */
+	struct it82xx2_usb_ep_fifo_regs fifo_regs[4];
+	/* 0xE0:  Host/Device Control Register */
+	volatile uint8_t host_device_control;
+	/* 0xE1 ~ 0xE3:  Reserved Registers E1h - E3h */
+	volatile uint8_t reserved_e1_e3[3];
+	/* 0xE4:  Port0 MISC Control Register */
+	volatile uint8_t port0_misc_control;
+	/* 0xE5 ~ 0xE7:  Reserved Registers E5h - E7h */
+	volatile uint8_t reserved_e5_e7[3];
+	/* 0xE8:  Port1 MISC Control Register */
+	volatile uint8_t port1_misc_control;
+};
+#endif /* #ifndef __ASSEMBLER__ */
+
+/**
+ *
+ * (37xxh, 38xxh) USBPD Controller
+ *
+ */
+#ifndef __ASSEMBLER__
+struct usbpd_it8xxx2_regs {
+	/* 0x000~0x003: Reserved1 */
+	volatile uint8_t Reserved1[4];
+	/* 0x004: CC General Configuration */
+	volatile uint8_t CCGCR;
+	/* 0x005: CC Channel Setting */
+	volatile uint8_t CCCSR;
+	/* 0x006: CC Pad Setting */
+	volatile uint8_t CCPSR;
+};
+#endif /* !__ASSEMBLER__ */
+
+/* USBPD controller register fields */
+/* 0x004: CC General Configuration */
+#define IT8XXX2_USBPD_DISABLE_CC                 BIT(7)
+#define IT8XXX2_USBPD_DISABLE_CC_VOL_DETECTOR    BIT(6)
+#define IT8XXX2_USBPD_CC_SELECT_RP_RESERVED      (BIT(3) | BIT(2) | BIT(1))
+#define IT8XXX2_USBPD_CC_SELECT_RP_DEF           (BIT(3) | BIT(2))
+#define IT8XXX2_USBPD_CC_SELECT_RP_1A5           BIT(3)
+#define IT8XXX2_USBPD_CC_SELECT_RP_3A0           BIT(2)
+#define IT8XXX2_USBPD_CC1_CC2_SELECTION          BIT(0)
+/* 0x005: CC Channel Setting */
+#define IT8XXX2_USBPD_CC2_DISCONNECT             BIT(7)
+#define IT8XXX2_USBPD_CC2_DISCONNECT_5_1K_TO_GND BIT(6)
+#define IT8XXX2_USBPD_CC1_DISCONNECT             BIT(3)
+#define IT8XXX2_USBPD_CC1_DISCONNECT_5_1K_TO_GND BIT(2)
+#define IT8XXX2_USBPD_CC1_CC2_RP_RD_SELECT       (BIT(1) | BIT(5))
+/* 0x006: CC Pad Setting */
+#define IT8XXX2_USBPD_DISCONNECT_5_1K_CC2_DB     BIT(6)
+#define IT8XXX2_USBPD_DISCONNECT_POWER_CC2       BIT(5)
+#define IT8XXX2_USBPD_DISCONNECT_5_1K_CC1_DB     BIT(2)
+#define IT8XXX2_USBPD_DISCONNECT_POWER_CC1       BIT(1)
+
+/**
+ *
+ * (10xxh) Shared Memory Flash Interface Bridge (SMFI) registers
+ *
+ */
+#ifndef __ASSEMBLER__
+struct smfi_it8xxx2_regs {
+	volatile uint8_t reserved1[59];
+	/* 0x3B: EC-Indirect memory address 0 */
+	volatile uint8_t SMFI_ECINDAR0;
+	/* 0x3C: EC-Indirect memory address 1 */
+	volatile uint8_t SMFI_ECINDAR1;
+	/* 0x3D: EC-Indirect memory address 2 */
+	volatile uint8_t SMFI_ECINDAR2;
+	/* 0x3E: EC-Indirect memory address 3 */
+	volatile uint8_t SMFI_ECINDAR3;
+	/* 0x3F: EC-Indirect memory data */
+	volatile uint8_t SMFI_ECINDDR;
+	/* 0x40: Scratch SRAM 0 address low byte */
+	volatile uint8_t SMFI_SCAR0L;
+	/* 0x41: Scratch SRAM 0 address middle byte */
+	volatile uint8_t SMFI_SCAR0M;
+	/* 0x42: Scratch SRAM 0 address high byte */
+	volatile uint8_t SMFI_SCAR0H;
+	volatile uint8_t reserved1_1[23];
+	/* 0x5A: Host RAM Window Control */
+	volatile uint8_t SMFI_HRAMWC;
+	/* 0x5B: Host RAM Window 0 Base Address [11:4] */
+	volatile uint8_t SMFI_HRAMW0BA;
+	/* 0x5C: Host RAM Window 1 Base Address [11:4] */
+	volatile uint8_t SMFI_HRAMW1BA;
+	/* 0x5D: Host RAM Window 0 Access Allow Size */
+	volatile uint8_t SMFI_HRAMW0AAS;
+	/* 0x5E: Host RAM Window 1 Access Allow Size */
+	volatile uint8_t SMFI_HRAMW1AAS;
+	volatile uint8_t reserved2[67];
+	/* 0xA2: Flash control 6 */
+	volatile uint8_t SMFI_FLHCTRL6R;
+	volatile uint8_t reserved3[46];
+};
+#endif /* !__ASSEMBLER__ */
+
+/* SMFI register fields */
+/* EC-Indirect read internal flash */
+#define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6)
+/* Enable EC-indirect page program command */
+#define IT8XXX2_SMFI_MASK_ECINDPP       BIT(3)
+#define ITE_EC_SMFI_MASK_ECINDPP        IT8XXX2_SMFI_MASK_ECINDPP
+/* Scratch SRAM 0 address(BIT(19)) */
+#define IT8XXX2_SMFI_SC0A19             BIT(7)
+/* Scratch SRAM enable */
+#define IT8XXX2_SMFI_SCAR0H_ENABLE      BIT(3)
+
+/* H2RAM Path Select. 1b: H2RAM through LPC IO cycle. */
+#define SMFI_H2RAMPS  BIT(4)
+/* H2RAM Window 1 Enable */
+#define SMFI_H2RAMW1E BIT(1)
+/* H2RAM Window 0 Enable */
+#define SMFI_H2RAMW0E BIT(0)
+
+/* Host RAM Window x Write Protect Enable (All protected) */
+#define SMFI_HRAMWXWPE_ALL (BIT(5) | BIT(4))
+/* 0x42: Scratch SRAM 0 address high byte */
+#define SCARH_ADDR_BIT19   BIT(7)
+#define SCARH_ENABLE       BIT(3)
+
+/**
+ *
+ * (16xxh) General Purpose I/O Port (GPIO) registers
+ *
+ */
+#define GPIO_IT8XXX2_REG_BASE ((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr)))
+
+#ifndef __ASSEMBLER__
+#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
+struct gpio_it8xxx2_regs {
+	/* 0x00: General Control */
+	volatile uint8_t GPIO_GCR;
+	/* 0x01-D0: Reserved1 */
+	volatile uint8_t reserved1[208];
+	/* 0xD1: General Control 25 */
+	volatile uint8_t GPIO_GCR25;
+	/* 0xD2: General Control 26 */
+	volatile uint8_t GPIO_GCR26;
+	/* 0xD3: General Control 27 */
+	volatile uint8_t GPIO_GCR27;
+	/* 0xD4: General Control 28 */
+	volatile uint8_t GPIO_GCR28;
+	/* 0xD5: General Control 31 */
+	volatile uint8_t GPIO_GCR31;
+	/* 0xD6: General Control 32 */
+	volatile uint8_t GPIO_GCR32;
+	/* 0xD7: General Control 33 */
+	volatile uint8_t GPIO_GCR33;
+	/* 0xD8-0xDF: Reserved2 */
+	volatile uint8_t reserved2[8];
+	/* 0xE0: General Control 16 */
+	volatile uint8_t GPIO_GCR16;
+	/* 0xE1: General Control 17 */
+	volatile uint8_t GPIO_GCR17;
+	/* 0xE2: General Control 18 */
+	volatile uint8_t GPIO_GCR18;
+	/* 0xE3: Reserved3 */
+	volatile uint8_t reserved3;
+	/* 0xE4: General Control 19 */
+	volatile uint8_t GPIO_GCR19;
+	/* 0xE5: General Control 20 */
+	volatile uint8_t GPIO_GCR20;
+	/* 0xE6: General Control 21 */
+	volatile uint8_t GPIO_GCR21;
+	/* 0xE7: General Control 22 */
+	volatile uint8_t GPIO_GCR22;
+	/* 0xE8: General Control 23 */
+	volatile uint8_t GPIO_GCR23;
+	/* 0xE9: General Control 24 */
+	volatile uint8_t GPIO_GCR24;
+	/* 0xEA-0xEC: Reserved4 */
+	volatile uint8_t reserved4[3];
+	/* 0xED: General Control 30 */
+	volatile uint8_t GPIO_GCR30;
+	/* 0xEE: General Control 29 */
+	volatile uint8_t GPIO_GCR29;
+	/* 0xEF: Reserved5 */
+	volatile uint8_t reserved5;
+	/* 0xF0: General Control 1 */
+	volatile uint8_t GPIO_GCR1;
+	/* 0xF1: General Control 2 */
+	volatile uint8_t GPIO_GCR2;
+	/* 0xF2: General Control 3 */
+	volatile uint8_t GPIO_GCR3;
+	/* 0xF3: General Control 4 */
+	volatile uint8_t GPIO_GCR4;
+	/* 0xF4: General Control 5 */
+	volatile uint8_t GPIO_GCR5;
+	/* 0xF5: General Control 6 */
+	volatile uint8_t GPIO_GCR6;
+	/* 0xF6: General Control 7 */
+	volatile uint8_t GPIO_GCR7;
+	/* 0xF7: General Control 8 */
+	volatile uint8_t GPIO_GCR8;
+	/* 0xF8: General Control 9 */
+	volatile uint8_t GPIO_GCR9;
+	/* 0xF9: General Control 10 */
+	volatile uint8_t GPIO_GCR10;
+	/* 0xFA: General Control 11 */
+	volatile uint8_t GPIO_GCR11;
+	/* 0xFB: General Control 12 */
+	volatile uint8_t GPIO_GCR12;
+	/* 0xFC: General Control 13 */
+	volatile uint8_t GPIO_GCR13;
+	/* 0xFD: General Control 14 */
+	volatile uint8_t GPIO_GCR14;
+	/* 0xFE: General Control 15 */
+	volatile uint8_t GPIO_GCR15;
+	/* 0xFF: Power Good Watch Control */
+	volatile uint8_t GPIO_PGWCR;
+};
+#elif CONFIG_SOC_IT8XXX2_REG_SET_V2
+struct gpio_it8xxx2_regs {
+	/* 0x00: General Control */
+	volatile uint8_t GPIO_GCR;
+	/* 0x01-0x0F: Reserved1 */
+	volatile uint8_t reserved1[15];
+	/* 0x10: General Control 1 */
+	volatile uint8_t GPIO_GCR1;
+	/* 0x11: General Control 2 */
+	volatile uint8_t GPIO_GCR2;
+	/* 0x12: General Control 3 */
+	volatile uint8_t GPIO_GCR3;
+	/* 0x13: General Control 4 */
+	volatile uint8_t GPIO_GCR4;
+	/* 0x14: General Control 5 */
+	volatile uint8_t GPIO_GCR5;
+	/* 0x15: General Control 6 */
+	volatile uint8_t GPIO_GCR6;
+	/* 0x16: General Control 7 */
+	volatile uint8_t GPIO_GCR7;
+	/* 0x17: General Control 8 */
+	volatile uint8_t GPIO_GCR8;
+	/* 0x18: General Control 9 */
+	volatile uint8_t GPIO_GCR9;
+	/* 0x19: General Control 10 */
+	volatile uint8_t GPIO_GCR10;
+	/* 0x1A: General Control 11 */
+	volatile uint8_t GPIO_GCR11;
+	/* 0x1B: General Control 12 */
+	volatile uint8_t GPIO_GCR12;
+	/* 0x1C: General Control 13 */
+	volatile uint8_t GPIO_GCR13;
+	/* 0x1D: General Control 14 */
+	volatile uint8_t GPIO_GCR14;
+	/* 0x1E: General Control 15 */
+	volatile uint8_t GPIO_GCR15;
+	/* 0x1F: Power Good Watch Control */
+	volatile uint8_t GPIO_PGWCR;
+	/* 0x20: General Control 16 */
+	volatile uint8_t GPIO_GCR16;
+	/* 0x21: General Control 17 */
+	volatile uint8_t GPIO_GCR17;
+	/* 0x22: General Control 18 */
+	volatile uint8_t GPIO_GCR18;
+	/* 0x23: Reserved2 */
+	volatile uint8_t reserved2;
+	/* 0x24: General Control 19 */
+	volatile uint8_t GPIO_GCR19;
+	/* 0x25: Reserved3 */
+	volatile uint8_t reserved3;
+	/* 0x26: General Control 21 */
+	volatile uint8_t GPIO_GCR21;
+	/* 0x27-0x28: Reserved4 */
+	volatile uint8_t reserved4[2];
+	/* 0x29: General Control 24 */
+	volatile uint8_t GPIO_GCR24;
+	/* 0x2A-0x2C: Reserved5 */
+	volatile uint8_t reserved5[3];
+	/* 0x2D: General Control 30 */
+	volatile uint8_t GPIO_GCR30;
+	/* 0x2E: General Control 29 */
+	volatile uint8_t GPIO_GCR29;
+};
+
+/* GPIO register fields */
+/* 0x16: General Control 7 */
+#define IT8XXX2_GPIO_SMB2PS BIT(7)
+#define IT8XXX2_GPIO_SMB3PS BIT(6)
+#define IT8XXX2_GPIO_SMB5PS BIT(5)
+
+#endif
+#endif /* !__ASSEMBLER__ */
+
+/* GPIO register fields */
+/* 0x00: General Control */
+#define IT8XXX2_GPIO_LPCRSTEN             (BIT(2) | BIT(1))
+#define ITE_EC_GPIO_LPCRSTEN              IT8XXX2_GPIO_LPCRSTEN
+#define IT8XXX2_GPIO_GCR_ESPI_RST_D2      0x2
+#define IT8XXX2_GPIO_GCR_ESPI_RST_POS     1
+#define IT8XXX2_GPIO_GCR_ESPI_RST_EN_MASK (0x3 << IT8XXX2_GPIO_GCR_ESPI_RST_POS)
+/* 0xF0: General Control 1 */
+#define IT8XXX2_GPIO_U2CTRL_SIN1_SOUT1_EN BIT(2)
+#define IT8XXX2_GPIO_U1CTRL_SIN0_SOUT0_EN BIT(0)
+/* 0xE6: General Control 21 */
+#define IT8XXX2_GPIO_GPH1VS               BIT(1)
+#define IT8XXX2_GPIO_GPH2VS               BIT(0)
+
+#define KSIX_KSOX_KBS_GPIO_MODE BIT(7)
+#define KSIX_KSOX_GPIO_OUTPUT   BIT(6)
+#define KSIX_KSOX_GPIO_PULLUP   BIT(2)
+#define KSIX_KSOX_GPIO_PULLDOWN BIT(1)
+
+#define GPCR_PORT_PIN_MODE_INPUT    BIT(7)
+#define GPCR_PORT_PIN_MODE_OUTPUT   BIT(6)
+#define GPCR_PORT_PIN_MODE_PULLUP   BIT(2)
+#define GPCR_PORT_PIN_MODE_PULLDOWN BIT(1)
+
+/*
+ * If both PULLUP and PULLDOWN are set to 1b, the corresponding port would be
+ * configured as tri-state.
+ */
+#define GPCR_PORT_PIN_MODE_TRISTATE                                                                \
+	(GPCR_PORT_PIN_MODE_INPUT | GPCR_PORT_PIN_MODE_PULLUP | GPCR_PORT_PIN_MODE_PULLDOWN)
+
+/* --- GPIO --- */
+#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
+#define IT8XXX2_GPIO_BASE 0x00F01600
+
+#define IT8XXX2_GPIO_GCRX(offset) ECREG(IT8XXX2_GPIO_BASE + (offset))
+#define IT8XXX2_GPIO_GCR25_OFFSET 0xd1
+#define IT8XXX2_GPIO_GCR26_OFFSET 0xd2
+#define IT8XXX2_GPIO_GCR27_OFFSET 0xd3
+#define IT8XXX2_GPIO_GCR28_OFFSET 0xd4
+#define IT8XXX2_GPIO_GCR31_OFFSET 0xd5
+#define IT8XXX2_GPIO_GCR32_OFFSET 0xd6
+#define IT8XXX2_GPIO_GCR33_OFFSET 0xd7
+#define IT8XXX2_GPIO_GCR19_OFFSET 0xe4
+#define IT8XXX2_GPIO_GCR20_OFFSET 0xe5
+#define IT8XXX2_GPIO_GCR21_OFFSET 0xe6
+#define IT8XXX2_GPIO_GCR22_OFFSET 0xe7
+#define IT8XXX2_GPIO_GCR23_OFFSET 0xe8
+#define IT8XXX2_GPIO_GCR24_OFFSET 0xe9
+#define IT8XXX2_GPIO_GCR30_OFFSET 0xed
+#define IT8XXX2_GPIO_GCR29_OFFSET 0xee
+#endif
+
+/*
+ * TODO: use pinctrl node instead of following register declarations
+ *       to fix in tcpm\it83xx_pd.h.
+ */
+#define IT8XXX2_GPIO2_BASE 0x00F03E00
+
+#define IT8XXX2_GPIO_GPCRP0 ECREG(IT8XXX2_GPIO2_BASE + 0x18)
+#define IT8XXX2_GPIO_GPCRP1 ECREG(IT8XXX2_GPIO2_BASE + 0x19)
+
+/**
+ *
+ * (19xxh) Analog to Digital Converter (ADC) registers
+ *
+ */
+#ifndef __ASSEMBLER__
+
+/* Data structure to define ADC channel 13-16 control registers. */
+struct adc_vchs_ctrl_t {
+	/* 0x60: Voltage Channel Control */
+	volatile uint8_t VCHCTL;
+	/* 0x61: Voltage Channel Data Buffer MSB */
+	volatile uint8_t VCHDATM;
+	/* 0x62: Voltage Channel Data Buffer LSB */
+	volatile uint8_t VCHDATL;
+};
+
+struct adc_it8xxx2_regs {
+	/* 0x00: ADC Status */
+	volatile uint8_t ADCSTS;
+	/* 0x01: ADC Configuration */
+	volatile uint8_t ADCCFG;
+	/* 0x02: ADC Clock Control */
+	volatile uint8_t ADCCTL;
+	/* 0x03: General Control */
+	volatile uint8_t ADCGCR;
+	/* 0x04: Voltage Channel 0 Control */
+	volatile uint8_t VCH0CTL;
+	/* 0x05: Calibration Data Control */
+	volatile uint8_t KDCTL;
+	/* 0x06-0x17: Reserved1 */
+	volatile uint8_t reserved1[18];
+	/* 0x18: Voltage Channel 0 Data Buffer LSB */
+	volatile uint8_t VCH0DATL;
+	/* 0x19: Voltage Channel 0 Data Buffer MSB */
+	volatile uint8_t VCH0DATM;
+	/* 0x1a-0x43: Reserved2 */
+	volatile uint8_t reserved2[42];
+	/* 0x44: ADC Data Valid Status */
+	volatile uint8_t ADCDVSTS;
+	/* 0x45-0x54: Reserved2-1 */
+	volatile uint8_t reserved2_1[16];
+	/* 0x55: ADC Input Voltage Mapping Full-Scale Code Selection 1 */
+	volatile uint8_t ADCIVMFSCS1;
+	/* 0x56: ADC Input Voltage Mapping Full-Scale Code Selection 2 */
+	volatile uint8_t ADCIVMFSCS2;
+	/* 0x57: ADC Input Voltage Mapping Full-Scale Code Selection 3 */
+	volatile uint8_t ADCIVMFSCS3;
+	/* 0x58-0x5f: Reserved3 */
+	volatile uint8_t reserved3[8];
+	/* 0x60-0x6b: ADC channel 13~16 controller */
+	struct adc_vchs_ctrl_t adc_vchs_ctrl[4];
+	/* 0x6c: ADC Data Valid Status 2 */
+	volatile uint8_t ADCDVSTS2;
+	/* 0x6d-0xef: Reserved4 */
+	volatile uint8_t reserved4[131];
+	/* 0xf0: ADC Clock Control Register 1 */
+	volatile uint8_t ADCCTL1;
+};
+#endif /* !__ASSEMBLER__ */
+
+/* ADC conversion time select 1 */
+#define IT8XXX2_ADC_ADCCTS1            BIT(7)
+/* Analog accuracy initialization */
+#define IT8XXX2_ADC_AINITB             BIT(3)
+/* ADC conversion time select 0 */
+#define IT8XXX2_ADC_ADCCTS0            BIT(5)
+/* ADC module enable */
+#define IT8XXX2_ADC_ADCEN              BIT(0)
+/* ADC data buffer keep enable */
+#define IT8XXX2_ADC_DBKEN              BIT(7)
+/* W/C data valid flag */
+#define IT8XXX2_ADC_DATVAL             BIT(7)
+/* Data valid interrupt of adc */
+#define IT8XXX2_ADC_INTDVEN            BIT(5)
+/* Voltage channel enable (Channel 4~7 and 13~16) */
+#define IT8XXX2_ADC_VCHEN              BIT(4)
+/* Automatic hardware calibration enable */
+#define IT8XXX2_ADC_AHCE               BIT(7)
+/* 0x046, 0x049, 0x04c, 0x06e, 0x071, 0x074: Voltage comparator x control */
+#define IT8XXX2_VCMP_CMPEN             BIT(7)
+#define IT8XXX2_VCMP_CMPINTEN          BIT(6)
+#define IT8XXX2_VCMP_GREATER_THRESHOLD BIT(5)
+#define IT8XXX2_VCMP_EDGE_TRIGGER      BIT(4)
+#define IT8XXX2_VCMP_GPIO_ACTIVE_LOW   BIT(3)
+/* 0x077~0x07c: Voltage comparator x channel select MSB */
+#define IT8XXX2_VCMP_VCMPXCSELM        BIT(0)
+
+/**
+ *
+ * (1Exxh) Clock and Power Management (ECPM) registers
+ *
+ */
+#define IT8XXX2_ECPM_BASE 0x00F01E00
+
+#ifndef __ASSEMBLER__
+enum chip_pll_mode {
+	CHIP_PLL_DOZE = 0,
+	CHIP_PLL_SLEEP = 1,
+	CHIP_PLL_DEEP_DOZE = 3,
+};
+#endif
+/*
+ * TODO: use ecpm_it8xxx2_regs instead of following register declarations
+ *       to fix in soc.c.
+ */
+#define IT8XXX2_ECPM_PLLCTRL  ECREG(IT8XXX2_ECPM_BASE + 0x03)
+#define IT8XXX2_ECPM_AUTOCG   ECREG(IT8XXX2_ECPM_BASE + 0x04)
+#define IT8XXX2_ECPM_CGCTRL3R ECREG(IT8XXX2_ECPM_BASE + 0x05)
+#define IT8XXX2_ECPM_PLLFREQR ECREG(IT8XXX2_ECPM_BASE + 0x06)
+#define IT8XXX2_ECPM_PLLCSS   ECREG(IT8XXX2_ECPM_BASE + 0x08)
+#define IT8XXX2_ECPM_SCDCR0   ECREG(IT8XXX2_ECPM_BASE + 0x0c)
+#define IT8XXX2_ECPM_SCDCR1   ECREG(IT8XXX2_ECPM_BASE + 0x0d)
+#define IT8XXX2_ECPM_SCDCR2   ECREG(IT8XXX2_ECPM_BASE + 0x0e)
+#define IT8XXX2_ECPM_SCDCR3   ECREG(IT8XXX2_ECPM_BASE + 0x0f)
+#define IT8XXX2_ECPM_SCDCR4   ECREG(IT8XXX2_ECPM_BASE + 0x10)
+#define IT8XXX2_ECPM_PFACC0R  ECREG(IT8XXX2_ECPM_BASE + 0x20)
+#define IT8XXX2_ECPM_PFACC1R  ECREG(IT8XXX2_ECPM_BASE + 0x21)
+#define IT8XXX2_ECPM_PFACC2R  ECREG(IT8XXX2_ECPM_BASE + 0x40)
+#define IT8XXX2_ECPM_LCOTF2   ECREG(IT8XXX2_ECPM_BASE + 0x54)
+#define IT8XXX2_ECPM_LCOCR    ECREG(IT8XXX2_ECPM_BASE + 0x55)
+#define IT8XXX2_ECPM_LCOCR1   ECREG(IT8XXX2_ECPM_BASE + 0x57)
+
+/*
+ * The count number of the counter for 25 ms register.
+ * The 25 ms register is calculated by (count number *1.024 kHz).
+ */
+
+#define I2C_CLK_LOW_TIMEOUT 255 /* ~=249 ms */
+
+/**
+ *
+ * (1Cxxh) SMBus Interface (SMB) registers
+ *
+ */
+#define IT8XXX2_SMB_BASE 0x00F01C00
+#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
+#define IT8XXX2_SMB_4P7USL        ECREG(IT8XXX2_SMB_BASE + 0x00)
+#define IT8XXX2_SMB_4P0USL        ECREG(IT8XXX2_SMB_BASE + 0x01)
+#define IT8XXX2_SMB_300NS         ECREG(IT8XXX2_SMB_BASE + 0x02)
+#define IT8XXX2_SMB_250NS         ECREG(IT8XXX2_SMB_BASE + 0x03)
+#define IT8XXX2_SMB_25MS          ECREG(IT8XXX2_SMB_BASE + 0x04)
+#define IT8XXX2_SMB_45P3USL       ECREG(IT8XXX2_SMB_BASE + 0x05)
+#define IT8XXX2_SMB_45P3USH       ECREG(IT8XXX2_SMB_BASE + 0x06)
+#define IT8XXX2_SMB_4P7A4P0H      ECREG(IT8XXX2_SMB_BASE + 0x07)
+#define IT8XXX2_SMB_SLVISELR      ECREG(IT8XXX2_SMB_BASE + 0x08)
+#define IT8XXX2_SMB_SCLKTS(ch)    ECREG(IT8XXX2_SMB_BASE + 0x09 + ch)
+#define IT8XXX2_SMB_MSTFCTRL1     ECREG(IT8XXX2_SMB_BASE + 0x0D)
+#define IT8XXX2_SMB_MSTFSTS1      ECREG(IT8XXX2_SMB_BASE + 0x0E)
+#define IT8XXX2_SMB_MSTFCTRL2     ECREG(IT8XXX2_SMB_BASE + 0x0F)
+#define IT8XXX2_SMB_MSTFSTS2      ECREG(IT8XXX2_SMB_BASE + 0x10)
+#define IT8XXX2_SMB_SMB45CHS      ECREG(IT8XXX2_SMB_BASE + 0x11)
+#define IT8XXX2_SMB_I2CW2RF       ECREG(IT8XXX2_SMB_BASE + 0x12)
+#define IT8XXX2_SMB_IWRFISTA      ECREG(IT8XXX2_SMB_BASE + 0x13)
+#define IT8XXX2_SMB_SMB01CHS      ECREG(IT8XXX2_SMB_BASE + 0x20)
+#define IT8XXX2_SMB_SMB23CHS      ECREG(IT8XXX2_SMB_BASE + 0x21)
+#define IT8XXX2_SMB_SFFCTL        ECREG(IT8XXX2_SMB_BASE + 0x55)
+#define IT8XXX2_SMB_HOSTA(base)   ECREG(base + 0x00)
+#define IT8XXX2_SMB_HOCTL(base)   ECREG(base + 0x01)
+#define IT8XXX2_SMB_HOCMD(base)   ECREG(base + 0x02)
+#define IT8XXX2_SMB_TRASLA(base)  ECREG(base + 0x03)
+#define IT8XXX2_SMB_D0REG(base)   ECREG(base + 0x04)
+#define IT8XXX2_SMB_D1REG(base)   ECREG(base + 0x05)
+#define IT8XXX2_SMB_HOBDB(base)   ECREG(base + 0x06)
+#define IT8XXX2_SMB_PECERC(base)  ECREG(base + 0x07)
+#define IT8XXX2_SMB_SMBPCTL(base) ECREG(base + 0x0A)
+#define IT8XXX2_SMB_HOCTL2(base)  ECREG(base + 0x10)
+#elif CONFIG_SOC_IT8XXX2_REG_SET_V2
+#define IT8XXX2_SMB_SLVISEL     ECREG(IT8XXX2_SMB_BASE + 0x08)
+#define IT8XXX2_SMB_SMB01CHS    ECREG(IT8XXX2_SMB_BASE + 0x09)
+#define IT8XXX2_SMB_SMB23CHS    ECREG(IT8XXX2_SMB_BASE + 0x0A)
+#define IT8XXX2_SMB_SMB45CHS    ECREG(IT8XXX2_SMB_BASE + 0x0B)
+#define IT8XXX2_SMB_SCLKTS_BRGS ECREG(IT8XXX2_SMB_BASE + 0x80)
+#define IT8XXX2_SMB_SCLKTS_BRGM ECREG(IT8XXX2_SMB_BASE + 0x81)
+#define IT8XXX2_SMB_CHSBRG      ECREG(IT8XXX2_SMB_BASE + 0x82)
+#define IT8XXX2_SMB_CHSMOT      ECREG(IT8XXX2_SMB_BASE + 0x83)
+
+/* SMBus register fields */
+/* 0x80: SMCLK Timing Setting Register Bridge Slave */
+#define IT8XXX2_SMB_PREDEN      BIT(7)
+#endif
+
+/**
+ * Enhanced SMBus/I2C Interface
+ * Ch_D: 0x00F03680, Ch_E: 0x00F03500, Ch_F: 0x00F03580
+ * Ch_D: ch = 0x03, Ch_E: ch = 0x00, Ch_F: ch = 0x01
+ */
+#define IT8XXX2_I2C_DRR(base)        ECREG(base + 0x00)
+#define IT8XXX2_I2C_PSR(base)        ECREG(base + 0x01)
+#define IT8XXX2_I2C_HSPR(base)       ECREG(base + 0x02)
+#define IT8XXX2_I2C_STR(base)        ECREG(base + 0x03)
+#define IT8XXX2_I2C_DHTR(base)       ECREG(base + 0x04)
+#define IT8XXX2_I2C_TOR(base)        ECREG(base + 0x05)
+#define IT8XXX2_I2C_DTR(base)        ECREG(base + 0x08)
+#define IT8XXX2_I2C_CTR(base)        ECREG(base + 0x09)
+#define IT8XXX2_I2C_CTR1(base)       ECREG(base + 0x0A)
+#define IT8XXX2_I2C_BYTE_CNT_H(base) ECREG(base + 0x0B)
+#define IT8XXX2_I2C_BYTE_CNT_L(base) ECREG(base + 0x0C)
+#define IT8XXX2_I2C_IRQ_ST(base)     ECREG(base + 0x0D)
+#define IT8XXX2_I2C_IDR(base)        ECREG(base + 0x06)
+#define IT8XXX2_I2C_TOS(base)        ECREG(base + 0x07)
+#define IT8XXX2_I2C_SLV_NUM_H(base)  ECREG(base + 0x10)
+#define IT8XXX2_I2C_SLV_NUM_L(base)  ECREG(base + 0x11)
+#define IT8XXX2_I2C_STR2(base)       ECREG(base + 0x12)
+#define IT8XXX2_I2C_NST(base)        ECREG(base + 0x13)
+#define IT8XXX2_I2C_TO_ARB_ST(base)  ECREG(base + 0x18)
+#define IT8XXX2_I2C_ERR_ST(base)     ECREG(base + 0x19)
+#define IT8XXX2_I2C_FST(base)        ECREG(base + 0x1B)
+#define IT8XXX2_I2C_EM(base)         ECREG(base + 0x1C)
+#define IT8XXX2_I2C_MODE_SEL(base)   ECREG(base + 0x1D)
+#define IT8XXX2_I2C_IDR2(base)       ECREG(base + 0x1F)
+#define IT8XXX2_I2C_CTR2(base)       ECREG(base + 0x20)
+#define IT8XXX2_I2C_RAMHA(base)      ECREG(base + 0x23)
+#define IT8XXX2_I2C_RAMLA(base)      ECREG(base + 0x24)
+#define IT8XXX2_I2C_RAMHA2(base)     ECREG(base + 0x2C)
+#define IT8XXX2_I2C_RAMLA2(base)     ECREG(base + 0x2D)
+#define IT8XXX2_I2C_CMD_ADDH(base)   ECREG(base + 0x25)
+#define IT8XXX2_I2C_CMD_ADDL(base)   ECREG(base + 0x26)
+#define IT8XXX2_I2C_RAMH2A(base)     ECREG(base + 0x50)
+#define IT8XXX2_I2C_CMD_ADDH2(base)  ECREG(base + 0x52)
+
+/* SMBus/I2C register fields */
+/* 0x09-0xB: SMCLK Timing Setting */
+#define IT8XXX2_SMB_SMCLKS_1M   4
+#define IT8XXX2_SMB_SMCLKS_400K 3
+#define IT8XXX2_SMB_SMCLKS_100K 2
+#define IT8XXX2_SMB_SMCLKS_50K  1
+
+/* 0x0E: SMBus FIFO Status 1 */
+#define IT8XXX2_SMB_FIFO1_EMPTY      BIT(7)
+#define IT8XXX2_SMB_FIFO1_FULL       BIT(6)
+/* 0x0D: SMBus FIFO Control 1 */
+/* 0x0F: SMBus FIFO Control 2 */
+#define IT8XXX2_SMB_BLKDS            BIT(4)
+#define IT8XXX2_SMB_FFEN             BIT(3)
+#define IT8XXX2_SMB_FFCHSEL2_B       0
+#define IT8XXX2_SMB_FFCHSEL2_C       BIT(0)
+/* 0x10: SMBus FIFO Status 2 */
+#define IT8XXX2_SMB_FIFO2_EMPTY      BIT(7)
+#define IT8XXX2_SMB_FIFO2_FULL       BIT(6)
+/* 0x12: I2C Wr To Rd FIFO */
+#define IT8XXX2_SMB_MAIF             BIT(7)
+#define IT8XXX2_SMB_MBCIF            BIT(6)
+#define IT8XXX2_SMB_MCIFI            BIT(2)
+#define IT8XXX2_SMB_MBIFI            BIT(1)
+#define IT8XXX2_SMB_MAIFI            BIT(0)
+/* 0x13: I2C Wr To Rd FIFO Interrupt Status */
+#define IT8XXX2_SMB_MCIFID           BIT(2)
+#define IT8XXX2_SMB_MAIFID           BIT(0)
+/* 0x41 0x81 0xC1: Host Control */
+#define IT8XXX2_SMB_SRT              BIT(6)
+#define IT8XXX2_SMB_LABY             BIT(5)
+#define IT8XXX2_SMB_SMCD_EXTND       BIT(4) | BIT(3) | BIT(2)
+#define IT8XXX2_SMB_KILL             BIT(1)
+#define IT8XXX2_SMB_INTREN           BIT(0)
+/* 0x43 0x83 0xC3: Transmit Slave Address */
+#define IT8XXX2_SMB_DIR              BIT(0)
+/* 0x4A 0x8A 0xCA: SMBus Pin Control */
+#define IT8XXX2_SMB_SMBDCS           BIT(1)
+#define IT8XXX2_SMB_SMBCS            BIT(0)
+/* 0x50 0x90 0xD0: Host Control 2 */
+#define IT8XXX2_SMB_SMD_TO_EN        BIT(4)
+#define IT8XXX2_SMB_I2C_SW_EN        BIT(3)
+#define IT8XXX2_SMB_I2C_SW_WAIT      BIT(2)
+#define IT8XXX2_SMB_I2C_EN           BIT(1)
+#define IT8XXX2_SMB_SMHEN            BIT(0)
+/* 0x55: Slave A FIFO Control */
+#define IT8XXX2_SMB_HSAPE            BIT(1)
+/* 0x03: Status Register */
+#define IT8XXX2_I2C_BYTE_DONE        BIT(7)
+#define IT8XXX2_I2C_RW               BIT(2)
+#define IT8XXX2_I2C_INT_PEND         BIT(1)
+/* 0x04: Data Hold Time */
+#define IT8XXX2_I2C_SOFT_RST         BIT(7)
+/* 0x07: Time Out Status */
+#define IT8XXX2_I2C_CLK_STRETCH      BIT(7)
+#define IT8XXX2_I2C_SCL_IN           BIT(2)
+#define IT8XXX2_I2C_SDA_IN           BIT(0)
+/* 0x09: Control Register */
+#define IT8XXX2_I2C_INT_EN           BIT(6)
+#define IT8XXX2_I2C_ACK              BIT(3)
+#define IT8XXX2_I2C_HALT             BIT(0)
+/* 0x0A: Control 1 */
+#define IT8XXX2_I2C_COMQ_EN          BIT(7)
+#define IT8XXX2_I2C_MDL_EN           BIT(1)
+/* 0x0C: Byte count */
+#define IT8XXX2_I2C_DMA_ADDR_RELOAD  BIT(5)
+#define IT8XXX2_I2C_BYTE_CNT_ENABLE  BIT(3)
+/* 0x0D: Interrupt Status */
+#define IT8XXX2_I2C_CNT_HOLD         BIT(4)
+#define IT8XXX2_I2C_IDW_CLR          BIT(3)
+#define IT8XXX2_I2C_IDR_CLR          BIT(2)
+#define IT8XXX2_I2C_SLVDATAFLG       BIT(1)
+#define IT8XXX2_I2C_P_CLR            BIT(0)
+/* 0x13: Nack Status */
+#define IT8XXX2_I2C_NST_CNS          BIT(7)
+#define IT8XXX2_I2C_NST_ID_NACK      BIT(3)
+/* 0x18: Timeout and Arbiter Status */
+#define IT8XXX2_I2C_SCL_TIMEOUT_EN   BIT(7)
+#define IT8XXX2_I2C_SDA_TIMEOUT_EN   BIT(6)
+/* 0x19: Error Status */
+#define IT8XXX2_I2C_ERR_ST_DEV1_EIRQ BIT(0)
+/* 0x1B: Finish Status */
+#define IT8XXX2_I2C_FST_DEV1_IRQ     BIT(4)
+/* 0x1C: Error Mask */
+#define IT8XXX2_I2C_EM_DEV1_IRQ      BIT(4)
+
+/*
+ * TODO: use gctrl_ite_ec_regs instead of following register declarations
+ *       to fix in cros_flash_it8xxx2.c, cros_shi_it8xxx2.c and tcpm\it8xxx2.c.
+ */
+/* --- General Control (GCTRL) --- */
+#define IT83XX_GCTRL_BASE 0x00F02000
+
+#define IT83XX_GCTRL_CHIPID1      ECREG(IT83XX_GCTRL_BASE + 0x85)
+#define IT83XX_GCTRL_CHIPID2      ECREG(IT83XX_GCTRL_BASE + 0x86)
+#define IT83XX_GCTRL_CHIPVER      ECREG(IT83XX_GCTRL_BASE + 0x02)
+#define IT83XX_GCTRL_MCCR3        ECREG(IT83XX_GCTRL_BASE + 0x20)
+#define IT83XX_GCTRL_SPISLVPFE    BIT(6)
+#define IT83XX_GCTRL_EWPR0PFH(i)  ECREG(IT83XX_GCTRL_BASE + 0x60 + i)
+#define IT83XX_GCTRL_EWPR0PFD(i)  ECREG(IT83XX_GCTRL_BASE + 0xA0 + i)
+#define IT83XX_GCTRL_EWPR0PFEC(i) ECREG(IT83XX_GCTRL_BASE + 0xC0 + i)
+
+/*
+ * TODO: use spisc_it8xxx2_regs instead of following register declarations
+ *       to fix in cros_shi_it8xxx2.c.
+ */
+/* Serial Peripheral Interface (SPI) */
+#define IT83XX_SPI_BASE 0x00F03A00
+
+#define IT83XX_SPI_SPISGCR      ECREG(IT83XX_SPI_BASE + 0x00)
+#define IT83XX_SPI_SPISCEN      BIT(0)
+#define IT83XX_SPI_TXRXFAR      ECREG(IT83XX_SPI_BASE + 0x01)
+#define IT83XX_SPI_CPURXF2A     BIT(4)
+#define IT83XX_SPI_CPURXF1A     BIT(3)
+#define IT83XX_SPI_CPUTFA       BIT(1)
+#define IT83XX_SPI_TXFCR        ECREG(IT83XX_SPI_BASE + 0x02)
+#define IT83XX_SPI_TXFCMR       BIT(2)
+#define IT83XX_SPI_TXFR         BIT(1)
+#define IT83XX_SPI_TXFS         BIT(0)
+#define IT83XX_SPI_GCR2         ECREG(IT83XX_SPI_BASE + 0x03)
+#define IT83XX_SPI_RXF2OC       BIT(4)
+#define IT83XX_SPI_RXF1OC       BIT(3)
+#define IT83XX_SPI_RXFAR        BIT(0)
+#define IT83XX_SPI_IMR          ECREG(IT83XX_SPI_BASE + 0x04)
+#define IT83XX_SPI_RX_FIFO_FULL BIT(7)
+#define IT83XX_SPI_RX_REACH     BIT(5)
+#define IT83XX_SPI_EDIM         BIT(2)
+#define IT83XX_SPI_ISR          ECREG(IT83XX_SPI_BASE + 0x05)
+#define IT83XX_SPI_TXFSR        ECREG(IT83XX_SPI_BASE + 0x06)
+#define IT83XX_SPI_ENDDETECTINT BIT(2)
+#define IT83XX_SPI_RXFSR        ECREG(IT83XX_SPI_BASE + 0x07)
+#define IT83XX_SPI_RXFFSM       (BIT(4) | BIT(3))
+#define IT83XX_SPI_RXF2FS       BIT(2)
+#define IT83XX_SPI_RXF1FS       BIT(1)
+#define IT83XX_SPI_SPISRDR      ECREG(IT83XX_SPI_BASE + 0x0b)
+#define IT83XX_SPI_CPUWTFDB0    ECREG_u32(IT83XX_SPI_BASE + 0x08)
+#define IT83XX_SPI_FCR          ECREG(IT83XX_SPI_BASE + 0x09)
+#define IT83XX_SPI_SPISRTXF     BIT(2)
+#define IT83XX_SPI_RXFR         BIT(1)
+#define IT83XX_SPI_RXFCMR       BIT(0)
+#define IT83XX_SPI_RXFRDRB0     ECREG_u32(IT83XX_SPI_BASE + 0x0C)
+#define IT83XX_SPI_FTCB0R       ECREG(IT83XX_SPI_BASE + 0x18)
+#define IT83XX_SPI_FTCB1R       ECREG(IT83XX_SPI_BASE + 0x19)
+#define IT83XX_SPI_TCCB0        ECREG(IT83XX_SPI_BASE + 0x1A)
+#define IT83XX_SPI_TCCB1        ECREG(IT83XX_SPI_BASE + 0x1B)
+#define IT83XX_SPI_HPR2         ECREG(IT83XX_SPI_BASE + 0x1E)
+#define IT83XX_SPI_EMMCBMR      ECREG(IT83XX_SPI_BASE + 0x21)
+#define IT83XX_SPI_EMMCABM      BIT(1) /* eMMC Alternative Boot Mode */
+#define IT83XX_SPI_RX_VLISMR    ECREG(IT83XX_SPI_BASE + 0x26)
+#define IT83XX_SPI_RVLIM        BIT(0)
+#define IT83XX_SPI_RX_VLISR     ECREG(IT83XX_SPI_BASE + 0x27)
+#define IT83XX_SPI_RVLI         BIT(0)
+
+/**
+ *
+ * (20xxh) General Control (GCTRL) registers
+ *
+ */
+#define GCTRL_IT8XXX2_REGS_BASE ((struct gctrl_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gctrl)))
+
+#ifndef __ASSEMBLER__
+struct gctrl_it8xxx2_regs {
+	/* 0x00-0x01: Reserved_00_01 */
+	volatile uint8_t reserved_00_01[2];
+	/* 0x02: Chip Version */
+	volatile uint8_t GCTRL_ECHIPVER;
+	/* 0x03: DBGR Operate Status */
+	volatile uint8_t GCTRL_DBGROS;
+	/* 0x04-0x05: Reserved_04_05 */
+	volatile uint8_t reserved_04_05[2];
+	/* 0x06: Reset Status */
+	volatile uint8_t GCTRL_RSTS;
+	/* 0x07-0x09: Reserved_07_09 */
+	volatile uint8_t reserved_07_09[3];
+	/* 0x0A: Base Address Select */
+	volatile uint8_t GCTRL_BADRSEL;
+	/* 0x0B: Wait Next Clock Rising */
+	volatile uint8_t GCTRL_WNCKR;
+	/* 0x0C: reserved_0c */
+	volatile uint8_t reserved_0c;
+	/* 0x0D: Special Control 1 */
+	volatile uint8_t GCTRL_SPCTRL1;
+	/* 0x0E-0x0F: reserved_0e_0f */
+	volatile uint8_t reserved_0e_0f[2];
+	/* 0x10: Reset Control DMM */
+	volatile uint8_t GCTRL_RSTDMMC;
+	/* 0x11: Reset Control 4 */
+	volatile uint8_t GCTRL_RSTC4;
+	/* 0x12-0x1B: reserved_12_1b */
+	volatile uint8_t reserved_12_1b[10];
+	/* 0x1C: Special Control 4 */
+	volatile uint8_t GCTRL_SPCTRL4;
+	/* 0x1D-0x1F: reserved_1d_1f */
+	volatile uint8_t reserved_1d_1f[3];
+	/* 0x20: Memory Controller Configuration 3 */
+	volatile uint8_t GCTRL_MCCR3;
+	/* 0x21: Reset Control 5 */
+	volatile uint8_t GCTRL_RSTC5;
+	/* 0x22-0x2F: reserved_22_2f */
+	volatile uint8_t reserved_22_2f[14];
+	/* 0x30: Memory Controller Configuration */
+	volatile uint8_t GCTRL_MCCR;
+	/* 0x31: Externel ILM/DLM Size */
+	volatile uint8_t GCTRL_EIDSR;
+	/* 0x32: Reserved_32 */
+	volatile uint8_t reserved_32;
+	/* 0x33: Pin Multi-function Enable 2 */
+	volatile uint8_t gctrl_pmer2;
+	/* 0x34-0x36: Reserved_34_36 */
+	volatile uint8_t reserved_34_36[3];
+	/* 0x37: Eflash Protect Lock */
+	volatile uint8_t GCTRL_EPLR;
+	/* 0x38-0x40: Reserved_38_40 */
+	volatile uint8_t reserved_38_40[9];
+	/* 0x41: Interrupt Vector Table Base Address */
+	volatile uint8_t GCTRL_IVTBAR;
+	/* 0x42-0x43: Reserved_42_43 */
+	volatile uint8_t reserved_42_43[2];
+	/* 0x44: Memory Controller Configuration 2 */
+	volatile uint8_t GCTRL_MCCR2;
+	/* 0x45: Reserved_45 */
+	volatile uint8_t reserved_45;
+	/* 0x46: Pin Multi-function Enable 3 */
+	volatile uint8_t GCTRL_PMER3;
+	/* 0x47-0x4A: reserved_47_4a */
+	volatile uint8_t reserved_47_4a[4];
+	/* 0x4B: ETWD and UART Control */
+	volatile uint8_t GCTRL_ETWDUARTCR;
+	/* 0x4C: Wakeup MCU Control */
+	volatile uint8_t GCTRL_WMCR;
+	/* 0x4D-0x4F: reserved_4d_4f */
+	volatile uint8_t reserved_4d_4f[3];
+	/* 0x50: Port 80h/81h Status Register */
+	volatile uint8_t GCTRL_P80H81HSR;
+	/* 0x51: Port 80h Data Register */
+	volatile uint8_t GCTRL_P80HDR;
+	/* 0x52: Port 81h Data Register */
+	volatile uint8_t GCTRL_P81HDR;
+	/* 0x53: H2RAM Offset Register */
+	volatile uint8_t GCTRL_H2ROFSR;
+	/* 0x54-0x5C: reserved_54_5c */
+	volatile uint8_t reserved_54_5c[9];
+	/* 0x5D: RISCV ILM Configuration 0 */
+	volatile uint8_t GCTRL_RVILMCR0;
+	/* 0x5E-0x84: reserved_5e_84 */
+	volatile uint8_t reserved_5e_84[39];
+	/* 0x85: Chip ID Byte 1 */
+	volatile uint8_t GCTRL_ECHIPID1;
+	/* 0x86: Chip ID Byte 2 */
+	volatile uint8_t GCTRL_ECHIPID2;
+	/* 0x87: Chip ID Byte 3 */
+	volatile uint8_t GCTRL_ECHIPID3;
+};
+#endif /* !__ASSEMBLER__ */
+
+/* GCTRL register fields */
+/* 0x03: DBGR Operate Status */
+#define IT8XXX2_GCTRL_SMB_DBGR         BIT(0)
+/* 0x06: Reset Status */
+#define IT8XXX2_GCTRL_LRS              (BIT(1) | BIT(0))
+#define IT8XXX2_GCTRL_IWDTR            BIT(1)
+/* 0x0B: Wait Next 65K Rising */
+#define IT8XXX2_GCTRL_WN65K            0x00
+/* 0x10: Reset Control DMM */
+#define IT8XXX2_GCTRL_UART1SD          BIT(3)
+#define IT8XXX2_GCTRL_UART2SD          BIT(2)
+/* 0x11: Reset Control 4 */
+#define IT8XXX2_GCTRL_RPECI            BIT(4)
+#define IT8XXX2_GCTRL_RUART2           BIT(2)
+#define IT8XXX2_GCTRL_RUART1           BIT(1)
+/* 0x1C: Special Control 4 */
+#define IT8XXX2_GCTRL_LRSIWR           BIT(2)
+#define IT8XXX2_GCTRL_LRSIPWRSWTR      BIT(1)
+#define IT8XXX2_GCTRL_LRSIPGWR         BIT(0)
+/* 0x20: Memory Controller Configuration 3 */
+#define IT8XXX2_GCTRL_SPISLVPFE        BIT(6)
+/* 0x30: Memory Controller Configuration */
+#define IT8XXX2_GCTRL_USB_DEBUG_EN     BIT(7)
+#define IT8XXX2_GCTRL_ICACHE_RESET     BIT(4)
+/* 0x37: Eflash Protect Lock */
+#define IT8XXX2_GCTRL_EPLR_ENABLE      BIT(0)
+/* 0x46: Pin Multi-function Enable 3 */
+#define IT8XXX2_GCTRL_SMB3PSEL         BIT(6)
+#define IT8XXX2_GCTRL_SRAM_CRYPTO_USED BIT(5)
+/* 0x4B: ETWD and UART Control */
+#define IT8XXX2_GCTRL_ETWD_HW_RST_EN   BIT(0)
+/* 0x5D: RISCV ILM Configuration 0 */
+#define IT8XXX2_GCTRL_ILM0_ENABLE      BIT(0)
+/* Accept Port 80h Cycle */
+#define IT8XXX2_GCTRL_ACP80            BIT(6)
+/* Accept Port 81h Cycle */
+#define IT8XXX2_GCTRL_ACP81            BIT(3)
+/* USB Debug Enable */
+#define IT8XXX2_GCTRL_MCCR_USB_EN      BIT(7)
+/* USB Pad Power-On Enable */
+#define IT8XXX2_GCTRL_PMER2_USB_PAD_EN BIT(7)
+
+/*
+ * VCC Detector Option.
+ * bit[7-6] = 1: The VCC power status is treated as power-on.
+ * The VCC supply of eSPI and related functions (EC2I, KBC, PMC and
+ * PECI). It means VCC should be logic high before using these
+ * functions, or firmware treats VCC logic high.
+ */
+#define IT8XXX2_GCTRL_VCCDO_MASK   (BIT(6) | BIT(7))
+#define IT8XXX2_GCTRL_VCCDO_VCC_ON BIT(6)
+/*
+ * bit[3] = 0: The reset source of PNPCFG is RSTPNP bit in RSTCH
+ * register and WRST#.
+ */
+#define IT8XXX2_GCTRL_HGRST        BIT(3)
+/* bit[2] = 1: Enable global reset. */
+#define IT8XXX2_GCTRL_GRST         BIT(2)
+
+/**
+ *
+ * (22xxh) Battery-backed SRAM (BRAM) registers
+ *
+ */
+#ifndef __ASSEMBLER__
+/* Battery backed RAM indices. */
+#define BRAM_MAGIC_FIELD_OFFSET 0xbc
+enum bram_indices {
+
+	/* This field is used to indicate BRAM is valid or not. */
+	BRAM_IDX_VALID_FLAGS0 = BRAM_MAGIC_FIELD_OFFSET,
+	BRAM_IDX_VALID_FLAGS1,
+	BRAM_IDX_VALID_FLAGS2,
+	BRAM_IDX_VALID_FLAGS3
+};
+#endif /* !__ASSEMBLER__ */
+
+#ifndef __ASSEMBLER__
+/*
+ * EC2I bridge registers
+ */
+struct ec2i_regs {
+	/* 0x00: Indirect Host I/O Address Register */
+	volatile uint8_t IHIOA;
+	/* 0x01: Indirect Host Data Register */
+	volatile uint8_t IHD;
+	/* 0x02: Lock Super I/O Host Access Register */
+	volatile uint8_t LSIOHA;
+	/* 0x03: Super I/O Access Lock Violation Register */
+	volatile uint8_t SIOLV;
+	/* 0x04: EC to I-Bus Modules Access Enable Register */
+	volatile uint8_t IBMAE;
+	/* 0x05: I-Bus Control Register */
+	volatile uint8_t IBCTL;
+};
+
+/* Index list of the host interface registers of PNPCFG */
+enum host_pnpcfg_index {
+	/* Logical Device Number */
+	HOST_INDEX_LDN = 0x07,
+	/* Chip ID Byte 1 */
+	HOST_INDEX_CHIPID1 = 0x20,
+	/* Chip ID Byte 2 */
+	HOST_INDEX_CHIPID2 = 0x21,
+	/* Chip Version */
+	HOST_INDEX_CHIPVER = 0x22,
+	/* Super I/O Control */
+	HOST_INDEX_SIOCTRL = 0x23,
+	/* Super I/O IRQ Configuration */
+	HOST_INDEX_SIOIRQ = 0x25,
+	/* Super I/O General Purpose */
+	HOST_INDEX_SIOGP = 0x26,
+	/* Super I/O Power Mode */
+	HOST_INDEX_SIOPWR = 0x2D,
+	/* Depth 2 I/O Address */
+	HOST_INDEX_D2ADR = 0x2E,
+	/* Depth 2 I/O Data */
+	HOST_INDEX_D2DAT = 0x2F,
+	/* Logical Device Activate Register */
+	HOST_INDEX_LDA = 0x30,
+	/* I/O Port Base Address Bits [15:8] for Descriptor 0 */
+	HOST_INDEX_IOBAD0_MSB = 0x60,
+	/* I/O Port Base Address Bits [7:0] for Descriptor 0 */
+	HOST_INDEX_IOBAD0_LSB = 0x61,
+	/* I/O Port Base Address Bits [15:8] for Descriptor 1 */
+	HOST_INDEX_IOBAD1_MSB = 0x62,
+	/* I/O Port Base Address Bits [7:0] for Descriptor 1 */
+	HOST_INDEX_IOBAD1_LSB = 0x63,
+	/* Interrupt Request Number and Wake-Up on IRQ Enabled */
+	HOST_INDEX_IRQNUMX = 0x70,
+	/* Interrupt Request Type Select */
+	HOST_INDEX_IRQTP = 0x71,
+	/* DMA Channel Select 0 */
+	HOST_INDEX_DMAS0 = 0x74,
+	/* DMA Channel Select 1 */
+	HOST_INDEX_DMAS1 = 0x75,
+	/* Device Specific Logical Device Configuration 1 to 10 */
+	HOST_INDEX_DSLDC1 = 0xF0,
+	HOST_INDEX_DSLDC2 = 0xF1,
+	HOST_INDEX_DSLDC3 = 0xF2,
+	HOST_INDEX_DSLDC4 = 0xF3,
+	HOST_INDEX_DSLDC5 = 0xF4,
+	HOST_INDEX_DSLDC6 = 0xF5,
+	HOST_INDEX_DSLDC7 = 0xF6,
+	HOST_INDEX_DSLDC8 = 0xF7,
+	HOST_INDEX_DSLDC9 = 0xF8,
+	HOST_INDEX_DSLDC10 = 0xF9,
+};
+
+/* List of logical device number (LDN) assignments */
+enum logical_device_number {
+	/* Serial Port 1 */
+	LDN_UART1 = 0x01,
+	/* Serial Port 2 */
+	LDN_UART2 = 0x02,
+	/* System Wake-Up Control */
+	LDN_SWUC = 0x04,
+	/* KBC/Mouse Interface */
+	LDN_KBC_MOUSE = 0x05,
+	/* KBC/Keyboard Interface */
+	LDN_KBC_KEYBOARD = 0x06,
+	/* Consumer IR */
+	LDN_CIR = 0x0A,
+	/* Shared Memory/Flash Interface */
+	LDN_SMFI = 0x0F,
+	/* RTC-like Timer */
+	LDN_RTCT = 0x10,
+	/* Power Management I/F Channel 1 */
+	LDN_PMC1 = 0x11,
+	/* Power Management I/F Channel 2 */
+	LDN_PMC2 = 0x12,
+	/* Serial Peripheral Interface */
+	LDN_SSPI = 0x13,
+	/* Platform Environment Control Interface */
+	LDN_PECI = 0x14,
+	/* Power Management I/F Channel 3 */
+	LDN_PMC3 = 0x17,
+	/* Power Management I/F Channel 4 */
+	LDN_PMC4 = 0x18,
+	/* Power Management I/F Channel 5 */
+	LDN_PMC5 = 0x19,
+};
+
+/* Structure for initializing PNPCFG via ec2i. */
+struct ec2i_t {
+	/* index port */
+	enum host_pnpcfg_index index_port;
+	/* data port */
+	uint8_t data_port;
+};
+
+/* EC2I access index/data port */
+enum ec2i_access {
+	/* index port */
+	EC2I_ACCESS_INDEX = 0,
+	/* data port */
+	EC2I_ACCESS_DATA = 1,
+};
+
+/* EC to I-Bus Access Enabled */
+#define EC2I_IBCTL_CSAE  BIT(0)
+/* EC Read from I-Bus */
+#define EC2I_IBCTL_CRIB  BIT(1)
+/* EC Write to I-Bus */
+#define EC2I_IBCTL_CWIB  BIT(2)
+#define EC2I_IBCTL_CRWIB (EC2I_IBCTL_CRIB | EC2I_IBCTL_CWIB)
+
+/* PNPCFG Register EC Access Enable */
+#define EC2I_IBMAE_CFGAE BIT(0)
+
+/*
+ * KBC registers
+ */
+struct kbc_regs {
+	/* 0x00: KBC Host Interface Control Register */
+	volatile uint8_t KBHICR;
+	/* 0x01: Reserved1 */
+	volatile uint8_t reserved1;
+	/* 0x02: KBC Interrupt Control Register */
+	volatile uint8_t KBIRQR;
+	/* 0x03: Reserved2 */
+	volatile uint8_t reserved2;
+	/* 0x04: KBC Host Interface Keyboard/Mouse Status Register */
+	volatile uint8_t KBHISR;
+	/* 0x05: Reserved3 */
+	volatile uint8_t reserved3;
+	/* 0x06: KBC Host Interface Keyboard Data Output Register */
+	volatile uint8_t KBHIKDOR;
+	/* 0x07: Reserved4 */
+	volatile uint8_t reserved4;
+	/* 0x08: KBC Host Interface Mouse Data Output Register */
+	volatile uint8_t KBHIMDOR;
+	/* 0x09: Reserved5 */
+	volatile uint8_t reserved5;
+	/* 0x0a: KBC Host Interface Keyboard/Mouse Data Input Register */
+	volatile uint8_t KBHIDIR;
+};
+
+/* Output Buffer Full */
+#define KBC_KBHISR_OBF      BIT(0)
+/* Input Buffer Full */
+#define KBC_KBHISR_IBF      BIT(1)
+/* A2 Address (A2) */
+#define KBC_KBHISR_A2_ADDR  BIT(3)
+#define KBC_KBHISR_STS_MASK (KBC_KBHISR_OBF | KBC_KBHISR_IBF | KBC_KBHISR_A2_ADDR)
+
+/* Clear Output Buffer Full */
+#define KBC_KBHICR_COBF      BIT(6)
+/* IBF/OBF Clear Mode Enable */
+#define KBC_KBHICR_IBFOBFCME BIT(5)
+/* Input Buffer Full CPU Interrupt Enable */
+#define KBC_KBHICR_IBFCIE    BIT(3)
+/* Output Buffer Empty CPU Interrupt Enable */
+#define KBC_KBHICR_OBECIE    BIT(2)
+/* Output Buffer Full Mouse Interrupt Enable */
+#define KBC_KBHICR_OBFMIE    BIT(1)
+/* Output Buffer Full Keyboard Interrupt Enable */
+#define KBC_KBHICR_OBFKIE    BIT(0)
+
+/*
+ * PMC registers
+ */
+struct pmc_regs {
+	/* 0x00: Host Interface PM Channel 1 Status */
+	volatile uint8_t PM1STS;
+	/* 0x01: Host Interface PM Channel 1 Data Out Port */
+	volatile uint8_t PM1DO;
+	/* 0x02: Host Interface PM Channel 1 Data Out Port with SCI# */
+	volatile uint8_t PM1DOSCI;
+	/* 0x03: Host Interface PM Channel 1 Data Out Port with SMI# */
+	volatile uint8_t PM1DOSMI;
+	/* 0x04: Host Interface PM Channel 1 Data In Port */
+	volatile uint8_t PM1DI;
+	/* 0x05: Host Interface PM Channel 1 Data In Port with SCI# */
+	volatile uint8_t PM1DISCI;
+	/* 0x06: Host Interface PM Channel 1 Control */
+	volatile uint8_t PM1CTL;
+	/* 0x07: Host Interface PM Channel 1 Interrupt Control */
+	volatile uint8_t PM1IC;
+	/* 0x08: Host Interface PM Channel 1 Interrupt Enable */
+	volatile uint8_t PM1IE;
+	/* 0x09-0x0f: Reserved1 */
+	volatile uint8_t reserved1[7];
+	/* 0x10: Host Interface PM Channel 2 Status */
+	volatile uint8_t PM2STS;
+	/* 0x11: Host Interface PM Channel 2 Data Out Port */
+	volatile uint8_t PM2DO;
+	/* 0x12: Host Interface PM Channel 2 Data Out Port with SCI# */
+	volatile uint8_t PM2DOSCI;
+	/* 0x13: Host Interface PM Channel 2 Data Out Port with SMI# */
+	volatile uint8_t PM2DOSMI;
+	/* 0x14: Host Interface PM Channel 2 Data In Port */
+	volatile uint8_t PM2DI;
+	/* 0x15: Host Interface PM Channel 2 Data In Port with SCI# */
+	volatile uint8_t PM2DISCI;
+	/* 0x16: Host Interface PM Channel 2 Control */
+	volatile uint8_t PM2CTL;
+	/* 0x17: Host Interface PM Channel 2 Interrupt Control */
+	volatile uint8_t PM2IC;
+	/* 0x18: Host Interface PM Channel 2 Interrupt Enable */
+	volatile uint8_t PM2IE;
+	/* 0x19: Mailbox Control */
+	volatile uint8_t MBXCTRL;
+	/* 0x1a-0x1f: Reserved2 */
+	volatile uint8_t reserved2[6];
+	/* 0x20-0xff: Reserved3 */
+	volatile uint8_t reserved3[0xe0];
+};
+
+/* Input Buffer Full Interrupt Enable */
+#define PMC_PM1CTL_IBFIE   BIT(0)
+/* Output Buffer Full */
+#define PMC_PM1STS_OBF     BIT(0)
+/* Input Buffer Full */
+#define PMC_PM1STS_IBF     BIT(1)
+/* General Purpose Flag */
+#define PMC_PM1STS_GPF     BIT(2)
+/* A2 Address (A2) */
+#define PMC_PM1STS_A2_ADDR BIT(3)
+
+/* PMC2 Input Buffer Full Interrupt Enable */
+#define PMC_PM2CTL_IBFIE BIT(0)
+/* General Purpose Flag */
+#define PMC_PM2STS_GPF   BIT(2)
+
+/*
+ * Dedicated Interrupt
+ * 0b:
+ * INT3: PMC Output Buffer Empty Int
+ * INT25: PMC Input Buffer Full Int
+ * 1b:
+ * INT3: PMC1 Output Buffer Empty Int
+ * INT25: PMC1 Input Buffer Full Int
+ * INT26: PMC2 Output Buffer Empty Int
+ * INT27: PMC2 Input Buffer Full Int
+ */
+#define PMC_MBXCTRL_DINT BIT(5)
+
+/*
+ * eSPI slave registers
+ */
+struct espi_slave_regs {
+	/* 0x00-0x03: Reserved1 */
+	volatile uint8_t reserved1[4];
+
+	/* 0x04: General Capabilities and Configuration 0 */
+	volatile uint8_t GCAPCFG0;
+	/* 0x05: General Capabilities and Configuration 1 */
+	volatile uint8_t GCAPCFG1;
+	/* 0x06: General Capabilities and Configuration 2 */
+	volatile uint8_t GCAPCFG2;
+	/* 0x07: General Capabilities and Configuration 3 */
+	volatile uint8_t GCAPCFG3;
+
+	/* Channel 0 (Peripheral Channel) Capabilities and Configurations */
+	/* 0x08: Channel 0 Capabilities and Configuration 0 */
+	volatile uint8_t CH_PC_CAPCFG0;
+	/* 0x09: Channel 0 Capabilities and Configuration 1 */
+	volatile uint8_t CH_PC_CAPCFG1;
+	/* 0x0A: Channel 0 Capabilities and Configuration 2 */
+	volatile uint8_t CH_PC_CAPCFG2;
+	/* 0x0B: Channel 0 Capabilities and Configuration 3 */
+	volatile uint8_t CH_PC_CAPCFG3;
+
+	/* Channel 1 (Virtual Wire Channel) Capabilities and Configurations */
+	/* 0x0C: Channel 1 Capabilities and Configuration 0 */
+	volatile uint8_t CH_VW_CAPCFG0;
+	/* 0x0D: Channel 1 Capabilities and Configuration 1 */
+	volatile uint8_t CH_VW_CAPCFG1;
+	/* 0x0E: Channel 1 Capabilities and Configuration 2 */
+	volatile uint8_t CH_VW_CAPCFG2;
+	/* 0x0F: Channel 1 Capabilities and Configuration 3 */
+	volatile uint8_t CH_VW_CAPCFG3;
+
+	/* Channel 2 (OOB Message Channel) Capabilities and Configurations */
+	/* 0x10: Channel 2 Capabilities and Configuration 0 */
+	volatile uint8_t CH_OOB_CAPCFG0;
+	/* 0x11: Channel 2 Capabilities and Configuration 1 */
+	volatile uint8_t CH_OOB_CAPCFG1;
+	/* 0x12: Channel 2 Capabilities and Configuration 2 */
+	volatile uint8_t CH_OOB_CAPCFG2;
+	/* 0x13: Channel 2 Capabilities and Configuration 3 */
+	volatile uint8_t CH_OOB_CAPCFG3;
+
+	/* Channel 3 (Flash Access Channel) Capabilities and Configurations */
+	/* 0x14: Channel 3 Capabilities and Configuration 0 */
+	volatile uint8_t CH_FLASH_CAPCFG0;
+	/* 0x15: Channel 3 Capabilities and Configuration 1 */
+	volatile uint8_t CH_FLASH_CAPCFG1;
+	/* 0x16: Channel 3 Capabilities and Configuration 2 */
+	volatile uint8_t CH_FLASH_CAPCFG2;
+	/* 0x17: Channel 3 Capabilities and Configuration 3 */
+	volatile uint8_t CH_FLASH_CAPCFG3;
+	/* Channel 3 Capabilities and Configurations 2 */
+	/* 0x18: Channel 3 Capabilities and Configuration 2-0 */
+	volatile uint8_t CH_FLASH_CAPCFG2_0;
+	/* 0x19: Channel 3 Capabilities and Configuration 2-1 */
+	volatile uint8_t CH_FLASH_CAPCFG2_1;
+	/* 0x1A: Channel 3 Capabilities and Configuration 2-2 */
+	volatile uint8_t CH_FLASH_CAPCFG2_2;
+	/* 0x1B: Channel 3 Capabilities and Configuration 2-3 */
+	volatile uint8_t CH_FLASH_CAPCFG2_3;
+
+	/* 0x1c-0x1f: Reserved2 */
+	volatile uint8_t reserved2[4];
+	/* 0x20-0x8f: Reserved3 */
+	volatile uint8_t reserved3[0x70];
+
+	/* 0x90: eSPI PC Control 0 */
+	volatile uint8_t ESPCTRL0;
+	/* 0x91: eSPI PC Control 1 */
+	volatile uint8_t ESPCTRL1;
+	/* 0x92: eSPI PC Control 2 */
+	volatile uint8_t ESPCTRL2;
+	/* 0x93: eSPI PC Control 3 */
+	volatile uint8_t ESPCTRL3;
+	/* 0x94: eSPI PC Control 4 */
+	volatile uint8_t ESPCTRL4;
+	/* 0x95: eSPI PC Control 5 */
+	volatile uint8_t ESPCTRL5;
+	/* 0x96: eSPI PC Control 6 */
+	volatile uint8_t ESPCTRL6;
+	/* 0x97: eSPI PC Control 7 */
+	volatile uint8_t ESPCTRL7;
+	/* 0x98-0x9f: Reserved4 */
+	volatile uint8_t reserved4[8];
+
+	/* 0xa0: eSPI General Control 0 */
+	volatile uint8_t ESGCTRL0;
+	/* 0xa1: eSPI General Control 1 */
+	volatile uint8_t ESGCTRL1;
+	/* 0xa2: eSPI General Control 2 */
+	volatile uint8_t ESGCTRL2;
+	/* 0xa3: eSPI General Control 3 */
+	volatile uint8_t ESGCTRL3;
+	/* 0xa4-0xaf: Reserved5 */
+	volatile uint8_t reserved5[12];
+
+	/* 0xb0: eSPI Upstream Control 0 */
+	volatile uint8_t ESUCTRL0;
+	/* 0xb1: eSPI Upstream Control 1 */
+	volatile uint8_t ESUCTRL1;
+	/* 0xb2: eSPI Upstream Control 2 */
+	volatile uint8_t ESUCTRL2;
+	/* 0xb3: eSPI Upstream Control 3 */
+	volatile uint8_t ESUCTRL3;
+	/* 0xb4-0xb5: Reserved6 */
+	volatile uint8_t reserved6[2];
+	/* 0xb6: eSPI Upstream Control 6 */
+	volatile uint8_t ESUCTRL6;
+	/* 0xb7: eSPI Upstream Control 7 */
+	volatile uint8_t ESUCTRL7;
+	/* 0xb8: eSPI Upstream Control 8 */
+	volatile uint8_t ESUCTRL8;
+	/* 0xb9-0xbf: Reserved7 */
+	volatile uint8_t reserved7[7];
+
+	/* 0xc0: eSPI OOB Control 0 */
+	volatile uint8_t ESOCTRL0;
+	/* 0xc1: eSPI OOB Control 1 */
+	volatile uint8_t ESOCTRL1;
+	/* 0xc2-0xc3: Reserved8 */
+	volatile uint8_t reserved8[2];
+	/* 0xc4: eSPI OOB Control 4 */
+	volatile uint8_t ESOCTRL4;
+	/* 0xc5-0xcf: Reserved9 */
+	volatile uint8_t reserved9[11];
+
+	/* 0xd0: eSPI SAFS Control 0 */
+	volatile uint8_t ESPISAFSC0;
+	/* 0xd1: eSPI SAFS Control 1 */
+	volatile uint8_t ESPISAFSC1;
+	/* 0xd2: eSPI SAFS Control 2 */
+	volatile uint8_t ESPISAFSC2;
+	/* 0xd3: eSPI SAFS Control 3 */
+	volatile uint8_t ESPISAFSC3;
+	/* 0xd4: eSPI SAFS Control 4 */
+	volatile uint8_t ESPISAFSC4;
+	/* 0xd5: eSPI SAFS Control 5 */
+	volatile uint8_t ESPISAFSC5;
+	/* 0xd6: eSPI SAFS Control 6 */
+	volatile uint8_t ESPISAFSC6;
+	/* 0xd7: eSPI SAFS Control 7 */
+	volatile uint8_t ESPISAFSC7;
+};
+
+/*
+ * eSPI VW registers
+ */
+struct espi_vw_regs {
+	/* 0x00-0x7f: VW index */
+	volatile uint8_t VW_INDEX[0x80];
+	/* 0x80-0x8f: Reserved1 */
+	volatile uint8_t reserved1[0x10];
+	/* 0x90: VW Contrl 0 */
+	volatile uint8_t VWCTRL0;
+	/* 0x91: VW Contrl 1 */
+	volatile uint8_t VWCTRL1;
+	/* 0x92: VW Contrl 2 */
+	volatile uint8_t VWCTRL2;
+	/* 0x93: VW Contrl 3 */
+	volatile uint8_t VWCTRL3;
+	/* 0x94: Reserved2 */
+	volatile uint8_t reserved2;
+	/* 0x95: VW Contrl 5 */
+	volatile uint8_t VWCTRL5;
+	/* 0x96: VW Contrl 6 */
+	volatile uint8_t VWCTRL6;
+	/* 0x97: VW Contrl 7 */
+	volatile uint8_t VWCTRL7;
+	/* 0x98-0x99: Reserved3 */
+	volatile uint8_t reserved3[2];
+};
+
+#define ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE 80
+/*
+ * eSPI Queue 0 registers
+ */
+struct espi_queue0_regs {
+	/* 0x00-0x3f: PUT_PC Data Byte 0-63 */
+	volatile uint8_t PUT_PC_DATA[0x40];
+	/* 0x40-0x7f: Reserved1 */
+	volatile uint8_t reserved1[0x40];
+	/* 0x80-0xcf: PUT_OOB Data Byte 0-79 */
+	volatile uint8_t PUT_OOB_DATA[ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE];
+};
+
+/*
+ * eSPI Queue 1 registers
+ */
+struct espi_queue1_regs {
+	/* 0x00-0x4f: Upstream Data Byte 0-79 */
+	volatile uint8_t UPSTREAM_DATA[ESPI_IT8XXX2_OOB_MAX_PAYLOAD_SIZE];
+	/* 0x50-0x7f: Reserved1 */
+	volatile uint8_t reserved1[0x30];
+	/* 0x80-0xbf: PUT_FLASH_NP Data Byte 0-63 */
+	volatile uint8_t PUT_FLASH_NP_DATA[0x40];
+};
+
+#endif /* !__ASSEMBLER__ */
+
+/**
+ *
+ * (3Axxh) SPI Slave Controller (SPISC) registers
+ *
+ */
+#ifndef __ASSEMBLER__
+struct spisc_it8xxx2_regs {
+	/* 0x00: SPI Slave General Control */
+	volatile uint8_t SPISC_SPISGCR;
+	/* 0x01: Tx/Rx FIFO Access */
+	volatile uint8_t SPISC_TXRXFAR;
+	/* 0x02: Tx FIFO Control */
+	volatile uint8_t SPISC_TXFCR;
+	/* 0x03: SPI Slave General Control 2 */
+	volatile uint8_t SPISC_SPISGCR2;
+	/* 0x04: Interrupt Mask */
+	volatile uint8_t SPISC_IMR;
+	/* 0x05: Interrupt Status */
+	volatile uint8_t SPISC_ISR;
+	/* 0x06: Tx FIFO Status */
+	volatile uint8_t SPISC_TXFSR;
+	/* 0x07: Rx FIFO Status */
+	volatile uint8_t SPISC_RXFSR;
+	/* 0x08: CPU Write Tx FIFO Data Byte0 */
+	volatile uint8_t SPISC_CPUWTXFDB0R;
+	/* 0x09: FIFO Control / CPU Write Tx FIFO Data Byte1 */
+	volatile uint8_t SPISC_FCR;
+	/* 0x0A: CPU Write Tx FIFO Data Byte2 */
+	volatile uint8_t SPISC_CPUWTXFDB2R;
+	/* 0x0B: SPI Slave Response Data / CPU Write Tx FIFO Data Byte3 */
+	volatile uint8_t SPISC_SPISRDR;
+	/* 0x0C: Rx FIFO Readout Data Byte0 */
+	volatile uint8_t SPISC_RXFRDRB0;
+	/* 0x0D: Rx FIFO Readout Data Byte1 */
+	volatile uint8_t SPISC_RXFRDRB1;
+	/* 0x0E: Rx FIFO Readout Data Byte2 */
+	volatile uint8_t SPISC_RXFRDRB2;
+	/* 0x0F: Rx FIFO Readout Data Byte3 */
+	volatile uint8_t SPISC_RXFRDRB3;
+	/* 0x10-0x17: Reserved1 */
+	volatile uint8_t reserved1[8];
+	/* 0x18: FIFO Target Count Byte0 */
+	volatile uint8_t SPISC_FTCB0R;
+	/* 0x19: FIFO Target Count Byte1 */
+	volatile uint8_t SPISC_FTCB1R;
+	/* 0x1A: Target Count Capture Byte0 */
+	volatile uint8_t SPISC_TCCB0;
+	/* 0x1B: Target Count Capture Byte1 */
+	volatile uint8_t SPISC_TCCB1;
+	/* 0x1C-0x1D: Reserved2 */
+	volatile uint8_t reserved2[2];
+	/* 0x1E: Hardware Parsing 2 */
+	volatile uint8_t SPISC_HPR2;
+	/* 0x1F-0x25: Reserved3 */
+	volatile uint8_t reserved3[7];
+	/* 0x26: Rx Valid Length Interrupt Status Mask */
+	volatile uint8_t SPISC_RXVLISMR;
+	/* 0x27: Rx Valid Length Interrupt Status */
+	volatile uint8_t SPISC_RXVLISR;
+};
+#endif /* !__ASSEMBLER__ */
+
+/* SPISC register fields */
+/* 0x00: SPI Slave General Control */
+#define IT8XXX2_SPISC_SPISCEN      BIT(0)
+/* 0x01: Tx/Rx FIFO Access */
+#define IT8XXX2_SPISC_CPURXF1A     BIT(3)
+#define IT8XXX2_SPISC_CPUTFA       BIT(1)
+/* 0x02: Tx FIFO Control */
+#define IT8XXX2_SPISC_TXFCMR       BIT(2)
+#define IT8XXX2_SPISC_TXFR         BIT(1)
+#define IT8XXX2_SPISC_TXFS         BIT(0)
+/* 0x03: SPI Slave General Control 2 */
+#define IT8XXX2_SPISC_RXF2OC       BIT(4)
+#define IT8XXX2_SPISC_RXF1OC       BIT(3)
+#define IT8XXX2_SPISC_RXFAR        BIT(0)
+/* 0x04: Interrupt Mask */
+#define IT8XXX2_SPISC_EDIM         BIT(2)
+/* 0x06: Tx FIFO Status */
+#define IT8XXX2_SPISC_ENDDETECTINT BIT(2)
+/* 0x09: FIFO Control */
+#define IT8XXX2_SPISC_SPISRTXF     BIT(2)
+#define IT8XXX2_SPISC_RXFR         BIT(1)
+#define IT8XXX2_SPISC_RXFCMR       BIT(0)
+/* 0x26: Rx Valid Length Interrupt Status Mask */
+#define IT8XXX2_SPISC_RVLIM        BIT(0)
+/* 0x27: Rx Valid Length Interrupt Status */
+#define IT8XXX2_SPISC_RVLI         BIT(0)
+
+/* Alias gpio_ite_ec_regs to gpio_it8xxx2_regs for compatibility */
+#define gpio_ite_ec_regs       gpio_it8xxx2_regs
+#define GPIO_ITE_EC_REGS_BASE  GPIO_IT8XXX2_REG_BASE
+/* Alias smfi_ite_ec_regs to smfi_it8xxx2_regs for compatibility */
+#define smfi_ite_ec_regs       smfi_it8xxx2_regs
+/* Alias gctrl_ite_ec_regs to  gctrl_it8xxx2_regs for compatibility */
+#define gctrl_ite_ec_regs      gctrl_it8xxx2_regs
+#define GCTRL_ITE_EC_REGS_BASE GCTRL_IT8XXX2_REGS_BASE
+
+#endif /* CHIP_CHIPREGS_H */
diff --git a/soc/ite/ec/it8xxx2/ilm.c b/soc/ite/ec/it8xxx2/ilm.c
index f586e38dd45..3bd76114bd5 100644
--- a/soc/ite/ec/it8xxx2/ilm.c
+++ b/soc/ite/ec/it8xxx2/ilm.c
@@ -3,6 +3,7 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <soc_common.h>
 #include <stdbool.h>
 #include <stdint.h>
 
@@ -46,9 +47,6 @@ BUILD_ASSERT((ILM_BLOCK_SIZE & (ILM_BLOCK_SIZE - 1)) == 0, "ILM_BLOCK_SIZE must
 
 #define ILM_NODE DT_NODELABEL(ilm)
 
-#define SCARH_ENABLE	 BIT(3)
-#define SCARH_ADDR_BIT19 BIT(7)
-
 /*
  * SCAR registers contain 20-bit addresses in three registers, with one set
  * of SCAR registers for each ILM block that may be configured.
@@ -82,8 +80,13 @@ static int it8xxx2_configure_ilm_block(const struct ilm_config *const config, vo
 	if ((uintptr_t)ram_addr < RAM_BASE) {
 		return -EFAULT; /* Not in RAM */
 	}
-	const int dirmap_index = ((uintptr_t)ram_addr - RAM_BASE) / ILM_BLOCK_SIZE;
 
+#ifdef CONFIG_SOC_IT51XXX
+	/* Since IT51XXX only supports one 4KB ILM block (SCAR0), set dirmap_index to 0 directly. */
+	const int dirmap_index = 0;
+#else
+	const int dirmap_index = ((uintptr_t)ram_addr - RAM_BASE) / ILM_BLOCK_SIZE;
+#endif
 	if (dirmap_index >= ARRAY_SIZE(config->scar_regs)) {
 		return -EFAULT; /* Past the end of RAM */
 	}
@@ -103,8 +106,10 @@ static int it8xxx2_configure_ilm_block(const struct ilm_config *const config, vo
 
 	int irq_key = irq_lock();
 
+#if !defined(CONFIG_SOC_IT51XXX)
 	/* Ensure scratch RAM for block data access is enabled */
 	scar->h = SCARH_ENABLE;
+#endif
 	/* Copy block contents from flash into RAM */
 	memcpy(ram_addr, flash_addr, copy_sz);
 	/* Program SCAR */
@@ -118,6 +123,11 @@ static int it8xxx2_configure_ilm_block(const struct ilm_config *const config, vo
 	}
 	scar->h = scarh_value;
 
+#ifdef CONFIG_SOC_IT51XXX
+	struct gctrl_it51xxx_regs *const gctrl_regs = GCTRL_IT51XXX_REGS_BASE;
+	/* Scratch ROM0 is 4kb size */
+	gctrl_regs->GCTRL_SCR0SZR = IT51XXX_GCTRL_SCRSIZE_4K;
+#endif
 	irq_unlock(irq_key);
 	return 0;
 }
@@ -158,51 +168,41 @@ static int it8xxx2_ilm_init(const struct device *dev)
 #define SCAR_REG(n) (volatile struct scar_reg *)DT_REG_ADDR_BY_IDX(ILM_NODE, n)
 
 static const struct ilm_config ilm_config = {
-	.scar_regs = {
-		/* SCAR0 SRAM 4KB */
-		SCAR_REG(0),
-		SCAR_REG(1),
-		SCAR_REG(2),
-		SCAR_REG(3),
-		SCAR_REG(4),
-		SCAR_REG(5),
-		SCAR_REG(6),
-		SCAR_REG(7),
-		SCAR_REG(8),
-		SCAR_REG(9),
-		SCAR_REG(10),
-		SCAR_REG(11),
-		SCAR_REG(12),
-		SCAR_REG(13),
-		SCAR_REG(14),
-		/*
-		 * Except for CONFIG_SOC_IT81202CX and CONFIG_SOC_IT81302CX
-		 * maximum ILM size are 60KB, the ILM size of other varients
-		 * are equal to the SRAM size.
-		 */
+	.scar_regs = {/* SCAR0 SRAM 4KB */
+		      SCAR_REG(0),
+#if (CONFIG_ILM_MAX_SIZE > 4)
+		      SCAR_REG(1), SCAR_REG(2), SCAR_REG(3), SCAR_REG(4), SCAR_REG(5), SCAR_REG(6),
+		      SCAR_REG(7), SCAR_REG(8), SCAR_REG(9), SCAR_REG(10), SCAR_REG(11),
+		      SCAR_REG(12), SCAR_REG(13), SCAR_REG(14),
+#endif
+/*
+ * Except for CONFIG_SOC_IT81202CX and CONFIG_SOC_IT81302CX
+ * maximum ILM size are 60KB, the ILM size of other variants
+ * are equal to the SRAM size.
+ */
 #if (CONFIG_ILM_MAX_SIZE == 256)
-		/* SCAR15 SRAM 4KB */
-		SCAR_REG(15),
-		/* SCAR16 SRAM 16KB */
-		SCAR_REG(16), SCAR_REG(16), SCAR_REG(16), SCAR_REG(16),
-		/* SCAR17 SRAM 16KB */
-		SCAR_REG(17), SCAR_REG(17), SCAR_REG(17), SCAR_REG(17),
-		/* SCAR18 SRAM 16KB */
-		SCAR_REG(18), SCAR_REG(18), SCAR_REG(18), SCAR_REG(18),
-		/* SCAR19 SRAM 16KB */
-		SCAR_REG(19), SCAR_REG(19), SCAR_REG(19), SCAR_REG(19),
-		/* SCAR20 SRAM 32KB */
-		SCAR_REG(20), SCAR_REG(20), SCAR_REG(20), SCAR_REG(20),
-		SCAR_REG(20), SCAR_REG(20), SCAR_REG(20), SCAR_REG(20),
-		/* SCAR21 SRAM 32KB */
-		SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), SCAR_REG(21),
-		SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), SCAR_REG(21),
-		/* SCAR22 SRAM 32KB */
-		SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), SCAR_REG(22),
-		SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), SCAR_REG(22),
-		/* SCAR23 SRAM 32KB */
-		SCAR_REG(23), SCAR_REG(23), SCAR_REG(23), SCAR_REG(23),
-		SCAR_REG(23), SCAR_REG(23), SCAR_REG(23), SCAR_REG(23)
+		      /* SCAR15 SRAM 4KB */
+		      SCAR_REG(15),
+		      /* SCAR16 SRAM 16KB */
+		      SCAR_REG(16), SCAR_REG(16), SCAR_REG(16), SCAR_REG(16),
+		      /* SCAR17 SRAM 16KB */
+		      SCAR_REG(17), SCAR_REG(17), SCAR_REG(17), SCAR_REG(17),
+		      /* SCAR18 SRAM 16KB */
+		      SCAR_REG(18), SCAR_REG(18), SCAR_REG(18), SCAR_REG(18),
+		      /* SCAR19 SRAM 16KB */
+		      SCAR_REG(19), SCAR_REG(19), SCAR_REG(19), SCAR_REG(19),
+		      /* SCAR20 SRAM 32KB */
+		      SCAR_REG(20), SCAR_REG(20), SCAR_REG(20), SCAR_REG(20), SCAR_REG(20),
+		      SCAR_REG(20), SCAR_REG(20), SCAR_REG(20),
+		      /* SCAR21 SRAM 32KB */
+		      SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), SCAR_REG(21), SCAR_REG(21),
+		      SCAR_REG(21), SCAR_REG(21), SCAR_REG(21),
+		      /* SCAR22 SRAM 32KB */
+		      SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), SCAR_REG(22), SCAR_REG(22),
+		      SCAR_REG(22), SCAR_REG(22), SCAR_REG(22),
+		      /* SCAR23 SRAM 32KB */
+		      SCAR_REG(23), SCAR_REG(23), SCAR_REG(23), SCAR_REG(23), SCAR_REG(23),
+		      SCAR_REG(23), SCAR_REG(23), SCAR_REG(23)
 #endif
 	}};
 BUILD_ASSERT(ARRAY_SIZE(ilm_config.scar_regs) * ILM_BLOCK_SIZE == KB(CONFIG_ILM_MAX_SIZE),
diff --git a/soc/ite/ec/it8xxx2/linker.ld b/soc/ite/ec/it8xxx2/linker.ld
index b5b0f686d73..3d46d9e00e2 100644
--- a/soc/ite/ec/it8xxx2/linker.ld
+++ b/soc/ite/ec/it8xxx2/linker.ld
@@ -131,9 +131,9 @@ SECTIONS
     } GROUP_LINK_IN(ROMABLE_REGION)
 
 #ifdef CONFIG_SOC_IT8XXX2_JTAG_DEBUG_INTERFACE
-#define JTAG_DEBUG_RESERVED_ADDR_START 0x80000800
-#define JTAG_DEBUG_RESERVED_ADDR_END 0x800008FF
-	/* The CPU address from 0x80000800 to 0x800008FF is reserved for JTAG
+#define JTAG_DEBUG_RESERVED_ADDR_START (ROM_BASE + 0x800)
+#define JTAG_DEBUG_RESERVED_ADDR_END (ROM_BASE + 0x8FF)
+	/* The flash range at offset 0x800 to 0x8FF is reserved for JTAG
 	 * debug usage. */
 	SECTION_PROLOGUE(jtag_dbg,,)
 	{
diff --git a/soc/ite/ec/it8xxx2/soc.c b/soc/ite/ec/it8xxx2/soc.c
index 73768c7ab83..e8a9b7fb3d7 100644
--- a/soc/ite/ec/it8xxx2/soc.c
+++ b/soc/ite/ec/it8xxx2/soc.c
@@ -369,6 +369,18 @@ void arch_cpu_atomic_idle(unsigned int key)
 	riscv_idle(CHIP_PLL_DOZE, key);
 }
 
+void soc_prep_hook(void)
+{
+#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V1
+	/*
+	 * Disables the I2C0 alternate function before executing the PLL sequence change
+	 * to ensure that the EC can enter sleep mode successfully.
+	 */
+	IT8XXX2_GPIO_GPCRB3 = GPCR_PORT_PIN_MODE_INPUT;
+	IT8XXX2_GPIO_GPCRB4 = GPCR_PORT_PIN_MODE_INPUT;
+#endif
+}
+
 static int ite_it8xxx2_init(void)
 {
 	struct gpio_it8xxx2_regs *const gpio_regs = GPIO_IT8XXX2_REG_BASE;
diff --git a/soc/ite/ec/common/vector.S b/soc/ite/ec/it8xxx2/vector.S
similarity index 100%
rename from soc/ite/ec/common/vector.S
rename to soc/ite/ec/it8xxx2/vector.S
diff --git a/soc/ite/ec/soc.yml b/soc/ite/ec/soc.yml
index b73270535f9..b0cba7d8eae 100644
--- a/soc/ite/ec/soc.yml
+++ b/soc/ite/ec/soc.yml
@@ -15,3 +15,8 @@ family:
           - name: it82302ax
           - name: it82202bw
           - name: it82302bw
+  - name: ite_ec
+    series:
+      - name: it51xxx
+        socs:
+          - name: it51526aw
diff --git a/soc/lowrisc/opentitan/Kconfig.defconfig b/soc/lowrisc/opentitan/Kconfig.defconfig
index 7cbedf1f60b..94c92d69c41 100644
--- a/soc/lowrisc/opentitan/Kconfig.defconfig
+++ b/soc/lowrisc/opentitan/Kconfig.defconfig
@@ -18,4 +18,9 @@ config 2ND_LVL_INTR_00_OFFSET
 config NUM_IRQS
 	default 256
 
+# The OpenTitan SoC requires a manifest in front of the
+# application binary.
+config ROM_START_OFFSET
+	default 0x400
+
 endif # SOC_OPENTITAN
diff --git a/soc/lowrisc/opentitan/rom_header.S b/soc/lowrisc/opentitan/rom_header.S
index e7b41235dab..2303614c4dc 100644
--- a/soc/lowrisc/opentitan/rom_header.S
+++ b/soc/lowrisc/opentitan/rom_header.S
@@ -17,7 +17,7 @@ GTEXT(__rom_header)
  * 0x6c47 (minor).  The manifest format is documented here:
  * https://github.com/lowRISC/opentitan/blob/689a163294e1791bd30cfe096decf7f9233abad4/sw/host/opentitanlib/src/image/manifest.rs#L205
  */
-SECTION_FUNC(rom_header, __rom_header)
+SECTION_VAR(rom_header, __rom_header)
 	.rept(225)
 	.word 0
 	.endr
diff --git a/soc/mediatek/mt8xxx/mt8196/Kconfig.defconfig b/soc/mediatek/mt8xxx/mt8196/Kconfig.defconfig
index e406dce76a5..67c58defefc 100644
--- a/soc/mediatek/mt8xxx/mt8196/Kconfig.defconfig
+++ b/soc/mediatek/mt8xxx/mt8196/Kconfig.defconfig
@@ -3,9 +3,6 @@
 
 if SOC_MT8196
 
-config LEGACY_MULTI_LEVEL_TABLE_GENERATION
-	default n
-
 config NUM_2ND_LEVEL_AGGREGATORS
 	default 2
 
diff --git a/soc/mediatek/mt8xxx/mtk_adsp_load.py b/soc/mediatek/mt8xxx/mtk_adsp_load.py
index 03efcd2f1cc..42127b75ec5 100755
--- a/soc/mediatek/mt8xxx/mtk_adsp_load.py
+++ b/soc/mediatek/mt8xxx/mtk_adsp_load.py
@@ -277,7 +277,13 @@ def find_winstream(maps):
     magic = b'\x74\x5f\x6a\xd0\x79\xe2\x4f\x00\xcd\xb8\xbd\xf9'
     for m in maps:
         if "dram" in m:
-            magoff = maps[m].find(magic)
+            # Some python versions produce bus errors (!) on the
+            # hardware when finding a 12 byte substring (maybe a SIMD
+            # load that the hardware doesn't like?).  Do it in two
+            # chunks.
+            magoff = maps[m].find(magic[0:8])
+            if magoff >= 0:
+                magoff = maps[m].find(magic[8:], magoff) - 8
             if magoff >= 0:
                 addr = le4(maps[m][magoff + 12 : magoff + 16])
                 return addr
diff --git a/soc/mediatek/mt8xxx/soc.c b/soc/mediatek/mt8xxx/soc.c
index 2b375ccf395..330a247bbe9 100644
--- a/soc/mediatek/mt8xxx/soc.c
+++ b/soc/mediatek/mt8xxx/soc.c
@@ -197,7 +197,6 @@ static void enable_mpu(void)
 		{ 0x10000000, 0x06f00 },          /* MMIO registers */
 		{ 0x1d000000, 0x06000 },          /* inaccessible */
 		{ SRAM_START, 0xf7f00 },          /* cached SRAM */
-		{ (uint32_t)&_mtk_adsp_sram_end, 0x06f00 }, /* uncached SRAM */
 		{ SRAM_END,   0x06000 },          /* inaccessible */
 		{ DRAM_START, 0xf7f00 },          /* cached DRAM */
 		{ (uint32_t)&_mtk_adsp_dram_end, 0x06f00 }, /* uncached DRAM */
diff --git a/soc/microchip/mec/mec15xx/Kconfig b/soc/microchip/mec/mec15xx/Kconfig
index 510fbd898ea..9a22e03cdc1 100644
--- a/soc/microchip/mec/mec15xx/Kconfig
+++ b/soc/microchip/mec/mec15xx/Kconfig
@@ -16,9 +16,6 @@ config SOC_MEC1501_HSZ
 
 if SOC_SERIES_MEC15XX
 
-config RTOS_TIMER
-	bool "MEC1501 RTOS timer"
-
 config SOC_MEC1501_PROC_CLK_DIV
 	int "PROC_CLK_DIV"
 	default 1
diff --git a/soc/microchip/mec/mec15xx/Kconfig.defconfig.series b/soc/microchip/mec/mec15xx/Kconfig.defconfig.series
index d12e7023128..ba99d185091 100644
--- a/soc/microchip/mec/mec15xx/Kconfig.defconfig.series
+++ b/soc/microchip/mec/mec15xx/Kconfig.defconfig.series
@@ -13,7 +13,16 @@ config NUM_IRQS
 
 rsource "Kconfig.defconfig.mec1501*"
 
-if RTOS_TIMER
+config CORTEX_M_SYSTICK
+	depends on !MCHP_XEC_RTOS_TIMER
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if CORTEX_M_SYSTICK
+	default $(dt_node_int_prop_int,/soc/timer@40007400,clock-frequency) if MCHP_XEC_RTOS_TIMER
+
+if MCHP_XEC_RTOS_TIMER
+config SYS_CLOCK_TICKS_PER_SEC
+	default $(dt_node_int_prop_int,/soc/timer@40007400,clock-frequency)
 
 config SOC_HAS_TIMING_FUNCTIONS
 	default y if !CORTEX_M_DWT
@@ -21,9 +30,6 @@ config SOC_HAS_TIMING_FUNCTIONS
 config ARCH_HAS_CUSTOM_BUSY_WAIT
 	default y
 
-endif # RTOS_TIMER
-
-config CORTEX_M_SYSTICK
-	depends on !RTOS_TIMER
+endif # MCHP_XEC_RTOS_TIMER
 
 endif # SOC_SERIES_MEC15XX
diff --git a/soc/microchip/mec/mec172x/Kconfig b/soc/microchip/mec/mec172x/Kconfig
index 85f579ec776..2a7589be700 100644
--- a/soc/microchip/mec/mec172x/Kconfig
+++ b/soc/microchip/mec/mec172x/Kconfig
@@ -15,9 +15,6 @@ config SOC_SERIES_MEC172X
 
 if SOC_SERIES_MEC172X
 
-config RTOS_TIMER
-	bool "MEC172x RTOS Timer(32KHz) as kernel timer"
-
 choice
 	prompt "MEC172x debug interface general configuration"
 	default SOC_MEC172X_DEBUG_WITHOUT_TRACING
diff --git a/soc/microchip/mec/mec172x/Kconfig.defconfig.series b/soc/microchip/mec/mec172x/Kconfig.defconfig.series
index 016d13b6818..b64aeb2e022 100644
--- a/soc/microchip/mec/mec172x/Kconfig.defconfig.series
+++ b/soc/microchip/mec/mec172x/Kconfig.defconfig.series
@@ -13,7 +13,16 @@ config NUM_IRQS
 
 rsource "Kconfig.defconfig.mec172x*"
 
-if RTOS_TIMER
+config CORTEX_M_SYSTICK
+	depends on !MCHP_XEC_RTOS_TIMER
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if CORTEX_M_SYSTICK
+	default $(dt_node_int_prop_int,/soc/timer@40007400,clock-frequency) if MCHP_XEC_RTOS_TIMER
+
+if MCHP_XEC_RTOS_TIMER
+config SYS_CLOCK_TICKS_PER_SEC
+	default $(dt_node_int_prop_int,/soc/timer@40007400,clock-frequency)
 
 config SOC_HAS_TIMING_FUNCTIONS
 	default y if !CORTEX_M_DWT
@@ -21,10 +30,7 @@ config SOC_HAS_TIMING_FUNCTIONS
 config ARCH_HAS_CUSTOM_BUSY_WAIT
 	default y
 
-endif # RTOS_TIMER
-
-config CORTEX_M_SYSTICK
-	depends on !RTOS_TIMER
+endif # MCHP_XEC_RTOS_TIMER
 
 config PS2_XEC
 	default y
diff --git a/soc/microchip/mec/mec172x/device_power.c b/soc/microchip/mec/mec172x/device_power.c
index eab5bfb0419..d6a627efdc6 100644
--- a/soc/microchip/mec/mec172x/device_power.c
+++ b/soc/microchip/mec/mec172x/device_power.c
@@ -92,10 +92,10 @@ void soc_deep_sleep_non_wake_dis(void)
 /* When MEC172x drivers are power-aware this should be move there */
 void soc_deep_sleep_wake_en(void)
 {
-#if defined(CONFIG_KSCAN) ||	\
+#if defined(INPUT_XEC_KBD) ||	\
 	(!defined(CONFIG_PM_DEVICE) && DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(ps2_0)))
 	struct ecia_named_regs *regs = ECIA_XEC_REG_BASE;
-#if defined(CONFIG_KSCAN)
+#if defined(INPUT_XEC_KBD)
 	/* Enable PLL wake via KSCAN  */
 	regs->GIRQ21.SRC = MCHP_KEYSCAN_GIRQ_BIT;
 	regs->GIRQ21.EN_SET = MCHP_KEYSCAN_GIRQ_BIT;
diff --git a/soc/microchip/mec/mec174x/Kconfig b/soc/microchip/mec/mec174x/Kconfig
index eeb77525d72..bdee97015bc 100644
--- a/soc/microchip/mec/mec174x/Kconfig
+++ b/soc/microchip/mec/mec174x/Kconfig
@@ -11,12 +11,8 @@ config SOC_SERIES_MEC174X
 	select CPU_HAS_ARM_MPU
 	select HAS_SWO
 	select HAS_MEC5_HAL
-	select HAS_PM
 	select SOC_PREP_HOOK
 
 if SOC_SERIES_MEC174X
 
-config RTOS_TIMER
-	bool "MEC174x RTOS Timer(32KHz) as kernel timer"
-
 endif # SOC_SERIES_MEC174X
diff --git a/soc/microchip/mec/mec174x/Kconfig.defconfig.series b/soc/microchip/mec/mec174x/Kconfig.defconfig.series
index f434af93409..2b750776fe9 100644
--- a/soc/microchip/mec/mec174x/Kconfig.defconfig.series
+++ b/soc/microchip/mec/mec174x/Kconfig.defconfig.series
@@ -12,6 +12,15 @@ config NUM_IRQS
 	default 194
 
 config CORTEX_M_SYSTICK
-	depends on !RTOS_TIMER
+	depends on !MCHP_MEC5_KTIMER
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if CORTEX_M_SYSTICK
+	default $(dt_node_int_prop_int,/soc/timer@40007400,clock-frequency) if MCHP_MEC5_KTIMER
+
+if MCHP_MEC5_KTIMER
+config SYS_CLOCK_TICKS_PER_SEC
+	default $(dt_node_int_prop_int,/soc/timer@40007400,clock-frequency)
+endif # MCHP_MEC5_KTIMER
 
 endif # SOC_SERIES_MEC174X
diff --git a/soc/microchip/mec/mec175x/Kconfig b/soc/microchip/mec/mec175x/Kconfig
index 5670fe72540..e2136d7a2df 100644
--- a/soc/microchip/mec/mec175x/Kconfig
+++ b/soc/microchip/mec/mec175x/Kconfig
@@ -11,12 +11,8 @@ config SOC_SERIES_MEC175X
 	select CPU_HAS_ARM_MPU
 	select HAS_SWO
 	select HAS_MEC5_HAL
-	select HAS_PM
 	select SOC_PREP_HOOK
 
 if SOC_SERIES_MEC175X
 
-config RTOS_TIMER
-	bool "MEC175x RTOS Timer(32KHz) as kernel timer"
-
 endif # SOC_SERIES_MEC175X
diff --git a/soc/microchip/mec/mec175x/Kconfig.defconfig.series b/soc/microchip/mec/mec175x/Kconfig.defconfig.series
index 01abcebfe87..e32cacf68cd 100644
--- a/soc/microchip/mec/mec175x/Kconfig.defconfig.series
+++ b/soc/microchip/mec/mec175x/Kconfig.defconfig.series
@@ -12,6 +12,15 @@ config NUM_IRQS
 	default 198
 
 config CORTEX_M_SYSTICK
-	depends on !RTOS_TIMER
+	depends on !MCHP_MEC5_KTIMER
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if CORTEX_M_SYSTICK
+	default $(dt_node_int_prop_int,/soc/timer@40007400,clock-frequency) if MCHP_MEC5_KTIMER
+
+if MCHP_MEC5_KTIMER
+config SYS_CLOCK_TICKS_PER_SEC
+	default $(dt_node_int_prop_int,/soc/timer@40007400,clock-frequency)
+endif # MCHP_MEC5_KTIMER
 
 endif # SOC_SERIES_MEC175X
diff --git a/soc/microchip/mec/mech172x/Kconfig b/soc/microchip/mec/mech172x/Kconfig
index d58d267e9cc..7154644bf1f 100644
--- a/soc/microchip/mec/mech172x/Kconfig
+++ b/soc/microchip/mec/mech172x/Kconfig
@@ -11,12 +11,8 @@ config SOC_SERIES_MECH172X
 	select CPU_HAS_ARM_MPU
 	select HAS_SWO
 	select HAS_MEC5_HAL
-	select HAS_PM
 	select SOC_PREP_HOOK
 
 if SOC_SERIES_MECH172X
 
-config RTOS_TIMER
-	bool "MECH172x RTOS Timer(32KHz) as kernel timer"
-
 endif # SOC_SERIES_MECH172X
diff --git a/soc/microchip/mec/mech172x/Kconfig.defconfig.series b/soc/microchip/mec/mech172x/Kconfig.defconfig.series
index cec629c0e47..ddb1a4a2850 100644
--- a/soc/microchip/mec/mech172x/Kconfig.defconfig.series
+++ b/soc/microchip/mec/mech172x/Kconfig.defconfig.series
@@ -12,6 +12,15 @@ config NUM_IRQS
 	default 181
 
 config CORTEX_M_SYSTICK
-	depends on !RTOS_TIMER
+	depends on !MCHP_MEC5_KTIMER
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if CORTEX_M_SYSTICK
+	default $(dt_node_int_prop_int,/soc/timer@40007400,clock-frequency) if MCHP_MEC5_KTIMER
+
+if MCHP_MEC5_KTIMER
+config SYS_CLOCK_TICKS_PER_SEC
+	default $(dt_node_int_prop_int,/soc/timer@40007400,clock-frequency)
+endif # MCHP_MEC5_KTIMER
 
 endif # SOC_SERIES_MECH172X
diff --git a/soc/microchip/miv/polarfire/Kconfig.defconfig b/soc/microchip/miv/polarfire/Kconfig.defconfig
index 26b0f2c9a25..927ced7e08a 100644
--- a/soc/microchip/miv/polarfire/Kconfig.defconfig
+++ b/soc/microchip/miv/polarfire/Kconfig.defconfig
@@ -23,6 +23,6 @@ config MAX_IRQ_PER_AGGREGATOR
 	default 186
 
 config NUM_IRQS
-	default 186
+	default 199
 
 endif # SOC_SERIES_POLARFIRE
diff --git a/soc/neorv32/CMakeLists.txt b/soc/neorv32/CMakeLists.txt
index 42731316d84..ffbadbff494 100644
--- a/soc/neorv32/CMakeLists.txt
+++ b/soc/neorv32/CMakeLists.txt
@@ -7,4 +7,4 @@ zephyr_sources(
   soc.c
 )
 
-set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
diff --git a/soc/neorv32/Kconfig b/soc/neorv32/Kconfig
index d0b2a04967b..bba678a61c7 100644
--- a/soc/neorv32/Kconfig
+++ b/soc/neorv32/Kconfig
@@ -1,37 +1,34 @@
-# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
+# Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_NEORV32
 	select RISCV
-	select RISCV_ISA_RV32I
-	select RISCV_ISA_EXT_M
-	select RISCV_ISA_EXT_A
-	select RISCV_ISA_EXT_ZICSR
-	select RISCV_ISA_EXT_ZIFENCEI
 	select RISCV_PRIVILEGED
 	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
 	imply XIP
 
 if SOC_NEORV32
 
-config SOC_NEORV32_V1_8_6
-	bool "v1.8.6"
-	# NEORV32 RISC-V ISA A extension implements only LR/SC, not AMO
-	select ATOMIC_OPERATIONS_C
-
 config SOC_NEORV32_VERSION
 	hex
-	default 0x01080600 if SOC_NEORV32_V1_8_6
+	default 0x01110200
 	help
 	  The targeted NEORV32 version as BCD-coded number. The format is
 	  identical to that of the NEORV32 Machine implementation ID (mimpid)
 	  register.
 
-config SOC_NEORV32_ISA_C
-	bool "RISC-V ISA Extension \"C\""
-	select RISCV_ISA_EXT_C
+config SOC_NEORV32_READ_FREQUENCY_AT_RUNTIME
+	bool "Read the NEORV32 clock frequency at runtime"
+	default y
+	depends on !$(dt_node_has_prop,/cpus/cpu@0,clock-frequency)
+	depends on SYS_CLOCK_EXISTS
+	select SOC_EARLY_INIT_HOOK
+	select TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
 	help
-	  Enable this if the NEORV32 CPU implementation supports the RISC-V ISA
-	  "C" extension (Compressed Instructions).
+	  If enabled, the NEORV32 clock frequency will be read from SYSINFO during boot. This
+	  results in small overhead, which can be avoided by setting the clock-frequency property of
+	  the cpu@0 devicetree node if the frequency is known at build-time.
 
 endif # SOC_NEORV32
diff --git a/soc/neorv32/Kconfig.defconfig b/soc/neorv32/Kconfig.defconfig
index 3608ae244a0..db169985f45 100644
--- a/soc/neorv32/Kconfig.defconfig
+++ b/soc/neorv32/Kconfig.defconfig
@@ -1,10 +1,10 @@
-# Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
+# Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_NEORV32
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if RISCV_MACHINE_TIMER
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if !SOC_NEORV32_READ_FREQUENCY_AT_RUNTIME
 
 config NUM_IRQS
 	default 32
@@ -12,12 +12,4 @@ config NUM_IRQS
 config SYSCON
 	default y
 
-config SERIAL_INIT_PRIORITY
-	default 55
-	depends on SERIAL
-
-config ENTROPY_INIT_PRIORITY
-	default 55
-	depends on ENTROPY_GENERATOR
-
 endif # SOC_NEORV32
diff --git a/soc/neorv32/Kconfig.soc b/soc/neorv32/Kconfig.soc
index 37a28ec7b44..8350679b5e8 100644
--- a/soc/neorv32/Kconfig.soc
+++ b/soc/neorv32/Kconfig.soc
@@ -8,15 +8,9 @@ config SOC_NEORV32
 
 	  The NEORV32 CPU implementation must have the following RISC-V ISA
 	  extensions enabled in order to support Zephyr:
-	  - M (Integer Multiplication and Division)
-	  - Zicsr (Control and Status Register (CSR) Instructions)
-
-	  The following NEORV32 CPU ISA extensions are not currently supported
-	  by Zephyr and can safely be disabled:
-	  - A (Atomic Instructions)
-	  - E (Embedded, only 16 integer registers)
-	  - Zbb (Basic Bit Manipulation)
-	  - Zfinx (Floating Point in Integer Registers)
+	  - Zicsr (always enabled)
+	  - Zifencei (always enabled)
+	  - Zicntr
 
 config SOC
 	default "neorv32" if SOC_NEORV32
diff --git a/soc/neorv32/linker.ld b/soc/neorv32/linker.ld
deleted file mode 100644
index 24a138865ca..00000000000
--- a/soc/neorv32/linker.ld
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/linker/linker-tool.h>
-
-MEMORY
-{
-	IO (rw) : ORIGIN = 0xFFFFFE00, LENGTH = 512
-}
-
-SECTIONS
-{
-	SECTION_PROLOGUE(io, (NOLOAD),)
-	{
-		PROVIDE(__io_start = ORIGIN(IO));
-		PROVIDE(__io_end   = ORIGIN(IO) + LENGTH(IO));
-	} GROUP_LINK_IN(IO)
-}
-
-#include <zephyr/arch/riscv/common/linker.ld>
diff --git a/soc/neorv32/reset.S b/soc/neorv32/reset.S
index ca91f0376b1..005835f8e9a 100644
--- a/soc/neorv32/reset.S
+++ b/soc/neorv32/reset.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
+ * Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,9 +13,6 @@ GTEXT(__reset)
 GTEXT(__initialize)
 
 SECTION_FUNC(reset, __reset)
-	/* Zerorize zero register */
-	lui x0, 0
-
 	/* Disable interrupts */
 	csrw mstatus, x0
 	csrw mie, x0
@@ -26,7 +23,7 @@ SECTION_FUNC(reset, __reset)
 #endif /* CONFIG_USERSPACE */
 
 	/* Allow mcycle and minstret counters to increment */
-	li x11, ~2
+	li x11, ~5
 	csrw mcountinhibit, x11
 
 	/* Zerorize counters */
@@ -35,39 +32,5 @@ SECTION_FUNC(reset, __reset)
 	csrw minstret, x0
 	csrw minstreth, x0
 
-	/*
-	 * Simplify dummy machine trap code by not having to decode
-	 * instruction width.
-	 */
-	.option push
-	.option norvc
-
-	/*
-	 * Temporarily setup a dummy machine trap vector to catch (and ignore)
-	 * Store Access faults due to unimplemented peripherals.
-	 */
-	csrr x6, mtvec
-	la x7, __dummy_trap_handler
-	csrw mtvec, x7
-
-	/* Attempt to zerorize all IO peripheral registers */
-	la x8, __io_start
-	la x9, __io_end
-1:	sw x0, 0(x8)
-	addi x8, x8, 4
-	bne x8, x9, 1b
-
-	/* Restore previous machine trap vector */
-	csrw mtvec, x6
-
-	.option pop
-
 	/* Jump to __initialize */
 	call __initialize
-
-.balign 4
-SECTION_FUNC(reset, __dummy_trap_handler)
-	csrr x5, mepc
-	addi x5, x5, 4
-	csrw mepc, x5
-	mret
diff --git a/soc/neorv32/soc.c b/soc/neorv32/soc.c
index 2a72eed16d9..ba80b2e717a 100644
--- a/soc/neorv32/soc.c
+++ b/soc/neorv32/soc.c
@@ -7,11 +7,22 @@
 #include <zephyr/irq.h>
 #include <soc.h>
 
-#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
+#ifdef CONFIG_SOC_NEORV32_READ_FREQUENCY_AT_RUNTIME
+extern unsigned int z_clock_hw_cycles_per_sec;
+
+void soc_early_init_hook(void)
+{
+	uint32_t base = DT_REG_ADDR(DT_NODELABEL(sysinfo));
+
+	z_clock_hw_cycles_per_sec = sys_read32(base + NEORV32_SYSINFO_CLK);
+}
+#endif /* CONFIG_SOC_NEORV32_READ_FREQUENCY_AT_RUNTIME */
+
+#ifdef CONFIG_RISCV_SOC_INTERRUPT_INIT
 void soc_interrupt_init(void)
 {
 	(void)arch_irq_lock();
 
 	csr_write(mie, 0);
 }
-#endif
+#endif /* CONFIG_RISCV_SOC_INTERRUPT_INIT */
diff --git a/soc/neorv32/soc.h b/soc/neorv32/soc.h
index a97daa0fc15..1e31ec1e6d0 100644
--- a/soc/neorv32/soc.h
+++ b/soc/neorv32/soc.h
@@ -1,56 +1,60 @@
 /*
- * Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
+ * Copyright (c) 2021,2025 Henrik Brix Andersen <henrik@brixandersen.dk>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#ifndef RISCV_NEORV32_SOC_H
-#define RISCV_NEORV32_SOC_H
+#ifndef _NEORV32_SOC_H
+#define _NEORV32_SOC_H
 
 /* System information (SYSINFO) register offsets */
 #define NEORV32_SYSINFO_CLK         0x00U
-#define NEORV32_SYSINFO_CPU         0x04U
-#define NEORV32_SYSINFO_FEATURES    0x08U
+#define NEORV32_SYSINFO_MISC        0x04U
+#define NEORV32_SYSINFO_SOC         0x08U
 #define NEORV32_SYSINFO_CACHE       0x0cU
-#define NEORV32_SYSINFO_ISPACE_BASE 0xf0U
-#define NEORV32_SYSINFO_IMEM_SIZE   0xf4U
-#define NEORV32_SYSINFO_DSPACE_BASE 0xf8U
-#define NEORV32_SYSINFO_DMEM_SIZE   0xfcU
 
-/* System information (SYSINFO) CPU register bits */
-#define NEORV32_SYSINFO_CPU_ZICSR     BIT(0)
-#define NEORV32_SYSINFO_CPU_ZIFENCEI  BIT(1)
-#define NEORV32_SYSINFO_CPU_ZMMUL     BIT(2)
-#define NEORV32_SYSINFO_CPU_ZBB       BIT(3)
-#define NEORV32_SYSINFO_CPU_ZFINX     BIT(5)
-#define NEORV32_SYSINFO_CPU_ZXSCNT    BIT(6)
-#define NEORV32_SYSINFO_CPU_ZXNOCNT   BIT(7)
-#define NEORV32_SYSINFO_CPU_PMP       BIT(8)
-#define NEORV32_SYSINFO_CPU_HPM       BIT(9)
-#define NEORV32_SYSINFO_CPU_DEBUGMODE BIT(10)
-#define NEORV32_SYSINFO_CPU_FASTMUL   BIT(30)
-#define NEORV32_SYSINFO_CPU_FASTSHIFT BIT(31)
+/* System information (SYSINFO) MISC register bits */
+#define NEORV32_SYSINFO_MISC_IMEM GENMASK(7, 0)
+#define NEORV32_SYSINFO_MISC_DMEM GENMASK(15, 8)
+#define NEORV32_SYSINFO_MISC_HART GENMASK(23, 16)
+#define NEORV32_SYSINFO_MISC_BOOT GENMASK(31, 24)
 
-/* System information (SYSINFO) FEATURES register bits */
-#define NEORV32_SYSINFO_FEATURES_BOOTLOADER     BIT(0)
-#define NEORV32_SYSINFO_FEATURES_MEM_EXT        BIT(1)
-#define NEORV32_SYSINFO_FEATURES_MEM_INT_IMEM   BIT(2)
-#define NEORV32_SYSINFO_FEATURES_MEM_INT_DMEM   BIT(3)
-#define NEORV32_SYSINFO_FEATURES_MEM_EXT_ENDIAN BIT(4)
-#define NEORV32_SYSINFO_FEATURES_ICACHE         BIT(5)
-#define NEORV32_SYSINFO_FEATURES_OCD            BIT(14)
-#define NEORV32_SYSINFO_FEATURES_HW_RESET       BIT(15)
-#define NEORV32_SYSINFO_FEATURES_IO_GPIO        BIT(16)
-#define NEORV32_SYSINFO_FEATURES_IO_MTIME       BIT(17)
-#define NEORV32_SYSINFO_FEATURES_IO_UART0       BIT(18)
-#define NEORV32_SYSINFO_FEATURES_IO_SPI         BIT(19)
-#define NEORV32_SYSINFO_FEATURES_IO_TWI         BIT(20)
-#define NEORV32_SYSINFO_FEATURES_IO_PWM         BIT(21)
-#define NEORV32_SYSINFO_FEATURES_IO_WDT         BIT(22)
-#define NEORV32_SYSINFO_FEATURES_IO_CFS         BIT(23)
-#define NEORV32_SYSINFO_FEATURES_IO_TRNG        BIT(24)
-#define NEORV32_SYSINFO_FEATURES_IO_SLINK       BIT(25)
-#define NEORV32_SYSINFO_FEATURES_IO_UART1       BIT(26)
-#define NEORV32_SYSINFO_FEATURES_IO_NEOLED      BIT(27)
+/* System information (SYSINFO) SOC register bits */
+#define NEORV32_SYSINFO_SOC_BOOTLOADER   BIT(0)
+#define NEORV32_SYSINFO_SOC_XBUS         BIT(1)
+#define NEORV32_SYSINFO_SOC_MEM_INT_IMEM BIT(2)
+#define NEORV32_SYSINFO_SOC_MEM_INT_DMEM BIT(3)
+#define NEORV32_SYSINFO_SOC_OCD          BIT(4)
+#define NEORV32_SYSINFO_SOC_ICACHE       BIT(5)
+#define NEORV32_SYSINFO_SOC_DCACHE       BIT(6)
+#define NEORV32_SYSINFO_SOC_XBUS_CACHE   BIT(8)
+#define NEORV32_SYSINFO_SOC_OCD_AUTH     BIT(11)
+#define NEORV32_SYSINFO_SOC_IMEM_ROM     BIT(12)
+#define NEORV32_SYSINFO_SOC_IO_TWD       BIT(13)
+#define NEORV32_SYSINFO_SOC_IO_DMA       BIT(14)
+#define NEORV32_SYSINFO_SOC_IO_GPIO      BIT(15)
+#define NEORV32_SYSINFO_SOC_IO_CLINT     BIT(16)
+#define NEORV32_SYSINFO_SOC_IO_UART0     BIT(17)
+#define NEORV32_SYSINFO_SOC_IO_SPI       BIT(18)
+#define NEORV32_SYSINFO_SOC_IO_TWI       BIT(19)
+#define NEORV32_SYSINFO_SOC_IO_PWM       BIT(20)
+#define NEORV32_SYSINFO_SOC_IO_WDT       BIT(21)
+#define NEORV32_SYSINFO_SOC_IO_CFS       BIT(22)
+#define NEORV32_SYSINFO_SOC_IO_TRNG      BIT(23)
+#define NEORV32_SYSINFO_SOC_IO_SDI       BIT(24)
+#define NEORV32_SYSINFO_SOC_IO_UART1     BIT(25)
+#define NEORV32_SYSINFO_SOC_IO_NEOLED    BIT(26)
+#define NEORV32_SYSINFO_SOC_IO_GPTMR     BIT(28)
+#define NEORV32_SYSINFO_SOC_IO_SLINK     BIT(29)
+#define NEORV32_SYSINFO_SOC_IO_ONEWIRE   BIT(30)
+#define NEORV32_SYSINFO_SOC_IO_CRC       BIT(31)
 
-#endif /* RISCV_NEORV32_SOC_H */
+/* System information (SYSINFO) CACHE register bits */
+#define NEORV32_SYSINFO_CACHE_INST_BLOCK_SIZE GENMASK(3, 0)
+#define NEORV32_SYSINFO_CACHE_INST_NUM_BLOCKS GENMASK(7, 4)
+#define NEORV32_SYSINFO_CACHE_DATA_BLOCK_SIZE GENMASK(11, 8)
+#define NEORV32_SYSINFO_CACHE_DATA_NUM_BLOCKS GENMASK(15, 12)
+#define NEORV32_SYSINFO_CACHE_XBUS_BLOCK_SIZE GENMASK(27, 24)
+#define NEORV32_SYSINFO_CACHE_XBUS_NUM_BLOCKS GENMASK(31, 28)
+
+#endif /* _NEORV32_SOC_H */
diff --git a/soc/neorv32/soc_irq.S b/soc/neorv32/soc_irq.S
index b82043d3434..4feae840000 100644
--- a/soc/neorv32/soc_irq.S
+++ b/soc/neorv32/soc_irq.S
@@ -13,16 +13,4 @@ GTEXT(__soc_handle_irq)
  * Exception number is given as parameter via register a0.
  */
 SECTION_FUNC(exception.other, __soc_handle_irq)
-	/*
-	 * The MIP CSR on the NEORV32 is read-only and can thus not be used for
-	 * clearing a pending IRQ. Instead we disable the IRQ in the MIE CSR and
-	 * re-enable it (if it was enabled when clearing).
-	 */
-	li t1, 1
-	sll t0, t1, a0
-	csrrc t2, mie, t0
-	and t1, t2, t0
-	csrrs t2, mie, t1
-
-	/* Return */
 	ret
diff --git a/soc/nordic/Kconfig b/soc/nordic/Kconfig
index e1e8982e27d..f510c1ec391 100644
--- a/soc/nordic/Kconfig
+++ b/soc/nordic/Kconfig
@@ -8,7 +8,7 @@
 
 config SOC_FAMILY_NORDIC_NRF
 	select SOC_COMPATIBLE_NRF
-	select SOC_RESET_HOOK if ARM
+	select SOC_RESET_HOOK
 	select CMSIS_CORE_HAS_SYSTEM_CORE_CLOCK if ARM
 
 if SOC_FAMILY_NORDIC_NRF
@@ -197,9 +197,4 @@ config NRF_PLATFORM_HALTIUM
 	  this option. This allows to easily enable common functionality on
 	  SoCs based on the Haltium platform.
 
-config DEPRECATED_UART_NRFX_UARTE_LEGACY_SHIM
-	bool
-	default y if !UART_NRFX_UARTE_LEGACY_SHIM
-	select DEPRECATED
-
 endif # SOC_FAMILY_NORDIC_NRF
diff --git a/soc/nordic/Kconfig.defconfig b/soc/nordic/Kconfig.defconfig
index efa122aa5b5..3e819b9ad59 100644
--- a/soc/nordic/Kconfig.defconfig
+++ b/soc/nordic/Kconfig.defconfig
@@ -11,7 +11,7 @@ rsource "*/Kconfig.defconfig"
 # based on the Haltium platform SoCs where clock control is not needed
 # for the system timer
 config CLOCK_CONTROL
-	default y if SYS_CLOCK_EXISTS && !NRF_PLATFORM_HALTIUM
+	default y if SYS_CLOCK_EXISTS && !NRF_PLATFORM_HALTIUM && !RISCV_CORE_NORDIC_VPR
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 1000000 if NRF_GRTC_TIMER
diff --git a/soc/nordic/common/CMakeLists.txt b/soc/nordic/common/CMakeLists.txt
index 7d71f62a4c5..ac75d083869 100644
--- a/soc/nordic/common/CMakeLists.txt
+++ b/soc/nordic/common/CMakeLists.txt
@@ -3,13 +3,11 @@
 
 add_subdirectory_ifdef(CONFIG_RISCV_CORE_NORDIC_VPR vpr)
 
-if(CONFIG_ARM)
-  # Let SystemInit() be called in place of soc_reset_hook() by default.
-  zephyr_linker_symbol(SYMBOL soc_reset_hook EXPR "@SystemInit@")
+# Let SystemInit() be called in place of soc_reset_hook() by default.
+zephyr_linker_symbol(SYMBOL soc_reset_hook EXPR "@SystemInit@")
 
-  # This file is used when the CMake linker script generator is disabled.
-  zephyr_linker_sources(SECTIONS arm_platform_init.ld)
-endif()
+# This file is used when the CMake linker script generator is disabled.
+zephyr_linker_sources(SECTIONS platform_init.ld)
 
 # TF-M provides its own reboot sequence
 if(NOT CONFIG_TFM_PARTITION_PLATFORM)
diff --git a/soc/nordic/common/arm_platform_init.ld b/soc/nordic/common/platform_init.ld
similarity index 100%
rename from soc/nordic/common/arm_platform_init.ld
rename to soc/nordic/common/platform_init.ld
diff --git a/soc/nordic/common/vpr/CMakeLists.txt b/soc/nordic/common/vpr/CMakeLists.txt
index cf14c817a1b..5a4fe40dbcf 100644
--- a/soc/nordic/common/vpr/CMakeLists.txt
+++ b/soc/nordic/common/vpr/CMakeLists.txt
@@ -3,6 +3,7 @@
 
 zephyr_include_directories(.)
 
-zephyr_library_sources(soc_context.S soc_idle.c soc_init.c)
+zephyr_library_sources(soc_context.S soc_init.c)
+zephyr_library_sources_ifdef(CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE soc_idle.c)
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
diff --git a/soc/nordic/common/vpr/Kconfig b/soc/nordic/common/vpr/Kconfig
index 45f2489dd57..bdcf9236fac 100644
--- a/soc/nordic/common/vpr/Kconfig
+++ b/soc/nordic/common/vpr/Kconfig
@@ -12,11 +12,12 @@ config RISCV_CORE_NORDIC_VPR
 	select RISCV_ISA_EXT_C
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_SOC_HAS_ISR_STACKING
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	select RISCV_HAS_CLIC
 	select RISCV_SOC_CONTEXT_SAVE
 	select HAS_FLASH_LOAD_OFFSET
-	select ARCH_HAS_CUSTOM_CPU_IDLE
-	select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
+	select ARCH_HAS_CUSTOM_CPU_IDLE if !SOC_SERIES_NRF54LX
+	select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE if !SOC_SERIES_NRF54LX
 	select INCLUDE_RESET_VECTOR
 	imply XIP
 	help
diff --git a/soc/nordic/common/vpr/soc_context.h b/soc/nordic/common/vpr/soc_context.h
index 9735057e792..2aba882afd7 100644
--- a/soc/nordic/common/vpr/soc_context.h
+++ b/soc/nordic/common/vpr/soc_context.h
@@ -8,14 +8,9 @@
 
 #define SOC_ESF_MEMBERS						\
 	unsigned long minttresh;				\
-	unsigned long sp_align;					\
-	unsigned long padding0;					\
-	unsigned long padding1;					\
-	unsigned long padding2
+	unsigned long sp_align;
 
 #define SOC_ESF_INIT						\
-	0,							\
-	0,							\
 	0,							\
 	0
 
diff --git a/soc/nordic/common/vpr/soc_isr_stacking.h b/soc/nordic/common/vpr/soc_isr_stacking.h
index 55733733539..c5f0e7b2762 100644
--- a/soc/nordic/common/vpr/soc_isr_stacking.h
+++ b/soc/nordic/common/vpr/soc_isr_stacking.h
@@ -20,7 +20,6 @@
 	struct arch_esf {                                                                          \
 		unsigned long s0;                                                                  \
 		unsigned long mstatus;                                                             \
-		unsigned long tp;                                                                  \
 		struct soc_esf soc_context;                                                        \
                                                                                                    \
 		unsigned long t2;                                                                  \
@@ -43,7 +42,6 @@
 	struct arch_esf {                                                                          \
 		unsigned long s0;                                                                  \
 		unsigned long mstatus;                                                             \
-		unsigned long tp;                                                                  \
 		struct soc_esf soc_context;                                                        \
                                                                                                    \
 		unsigned long ra;                                                                  \
@@ -86,7 +84,7 @@
  * Size of the SW managed part of the ESF in case of interrupt
  *   sizeof(__padding) + ... + sizeof(soc_context)
  */
-#define ESF_SW_IRQ_SIZEOF (0x20)
+#define ESF_SW_IRQ_SIZEOF (0x10)
 
 /*
  * VPR needs aligned(8) SP when doing HW stacking, if this condition is not fulfilled it will move
diff --git a/soc/nordic/nrf53/nrf53_cpunet_mgmt.c b/soc/nordic/nrf53/nrf53_cpunet_mgmt.c
index f7d2b54f3d6..9c869a2ecc0 100644
--- a/soc/nordic/nrf53/nrf53_cpunet_mgmt.c
+++ b/soc/nordic/nrf53/nrf53_cpunet_mgmt.c
@@ -15,14 +15,41 @@
 #include <zephyr/sys/__assert.h>
 #include <zephyr/sys/notify.h>
 #include <zephyr/sys/onoff.h>
+#include <soc_secure.h>
 
 #include <hal/nrf_reset.h>
 #include <hal/nrf_spu.h>
 
 static struct onoff_manager cpunet_mgr;
 
+#ifdef CONFIG_SOC_NRF_GPIO_FORWARDER_FOR_NRF5340
+
+#define GPIOS_PSEL_BY_IDX(node_id, prop, idx) \
+	NRF_DT_GPIOS_TO_PSEL_BY_IDX(node_id, prop, idx),
+#define ALL_GPIOS_IN_NODE(node_id) \
+	DT_FOREACH_PROP_ELEM(node_id, gpios, GPIOS_PSEL_BY_IDX)
+#define ALL_GPIOS_IN_FORWARDER(node_id) \
+	DT_FOREACH_CHILD(node_id, ALL_GPIOS_IN_NODE)
+
+static void assign_pins(nrf_gpio_pin_sel_t sel)
+{
+	static const uint8_t forwarded_psels[] = {
+		DT_FOREACH_STATUS_OKAY(nordic_nrf_gpio_forwarder, ALL_GPIOS_IN_FORWARDER)
+	};
+
+	for (int i = 0; i < ARRAY_SIZE(forwarded_psels); i++) {
+		soc_secure_gpio_pin_mcu_select(forwarded_psels[i], sel);
+	}
+}
+#endif /* CONFIG_SOC_NRF_GPIO_FORWARDER_FOR_NRF5340 */
+
 static void onoff_start(struct onoff_manager *mgr, onoff_notify_fn notify)
 {
+#ifdef CONFIG_SOC_NRF_GPIO_FORWARDER_FOR_NRF5340
+	/* Forward assigned pins to the network core. */
+	assign_pins(NRF_GPIO_PIN_SEL_NETWORK);
+#endif
+
 	nrf_reset_network_force_off(NRF_RESET, false);
 
 	notify(mgr, 0);
@@ -32,6 +59,11 @@ static void onoff_stop(struct onoff_manager *mgr, onoff_notify_fn notify)
 {
 	nrf_reset_network_force_off(NRF_RESET, true);
 
+#ifdef CONFIG_SOC_NRF_GPIO_FORWARDER_FOR_NRF5340
+	/* Assign pins back to app core. */
+	assign_pins(NRF_GPIO_PIN_SEL_APP);
+#endif
+
 	notify(mgr, 0);
 }
 
diff --git a/soc/nordic/nrf53/soc.c b/soc/nordic/nrf53/soc.c
index cbdb8e04fe0..c9fb9adc4f4 100644
--- a/soc/nordic/nrf53/soc.c
+++ b/soc/nordic/nrf53/soc.c
@@ -47,15 +47,6 @@
 #define RTC1_PRETICK_SELECTED_CC_MASK   BIT_MASK(CONFIG_NRF_RTC_TIMER_USER_CHAN_COUNT + 1U)
 #define RTC0_PRETICK_SELECTED_CC_MASK	BIT_MASK(NRF_RTC_CC_COUNT_MAX)
 
-#if defined(CONFIG_SOC_NRF_GPIO_FORWARDER_FOR_NRF5340)
-#define GPIOS_PSEL_BY_IDX(node_id, prop, idx) \
-	NRF_DT_GPIOS_TO_PSEL_BY_IDX(node_id, prop, idx),
-#define ALL_GPIOS_IN_NODE(node_id) \
-	DT_FOREACH_PROP_ELEM(node_id, gpios, GPIOS_PSEL_BY_IDX)
-#define ALL_GPIOS_IN_FORWARDER(node_id) \
-	DT_FOREACH_CHILD(node_id, ALL_GPIOS_IN_NODE)
-#endif
-
 #ifdef CONFIG_SOC_NRF5340_CPUAPP
 #define LFXO_NODE DT_NODELABEL(lfxo)
 #define HFXO_NODE DT_NODELABEL(hfxo)
@@ -562,17 +553,6 @@ static int nordicsemi_nrf53_init(void)
 	nrf_regulators_vreg_enable_set(NRF_REGULATORS, NRF_REGULATORS_VREG_HIGH, true);
 #endif
 
-#if defined(CONFIG_SOC_NRF_GPIO_FORWARDER_FOR_NRF5340)
-	static const uint8_t forwarded_psels[] = {
-		DT_FOREACH_STATUS_OKAY(nordic_nrf_gpio_forwarder, ALL_GPIOS_IN_FORWARDER)
-	};
-
-	for (int i = 0; i < ARRAY_SIZE(forwarded_psels); i++) {
-		soc_secure_gpio_pin_mcu_select(forwarded_psels[i], NRF_GPIO_PIN_SEL_NETWORK);
-	}
-
-#endif
-
 	return 0;
 }
 
diff --git a/soc/nordic/nrf54h/Kconfig b/soc/nordic/nrf54h/Kconfig
index 57961c1b98f..89fa83ef869 100644
--- a/soc/nordic/nrf54h/Kconfig
+++ b/soc/nordic/nrf54h/Kconfig
@@ -14,6 +14,7 @@ config SOC_NRF54H20_CPUAPP_COMMON
 	select ARM
 	select ARMV8_M_DSP
 	select CPU_CORTEX_M33
+	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_ARM_SAU
 	select CPU_HAS_DCACHE
@@ -43,6 +44,7 @@ config SOC_NRF54H20_CPURAD_COMMON
 	select ARM
 	select ARMV8_M_DSP
 	select CPU_CORTEX_M33
+	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_ARM_SAU
 	select CPU_HAS_DCACHE
diff --git a/soc/nordic/nrf54h/power.c b/soc/nordic/nrf54h/power.c
index 97f01c5b8dc..e1263be0d0e 100644
--- a/soc/nordic/nrf54h/power.c
+++ b/soc/nordic/nrf54h/power.c
@@ -184,17 +184,21 @@ void pm_state_set(enum pm_state state, uint8_t substate_id)
 {
 	if (state == PM_STATE_SUSPEND_TO_IDLE) {
 		__disable_irq();
+		sys_trace_idle();
 		s2idle_enter(substate_id);
 		/* Resume here. */
 		s2idle_exit(substate_id);
+		sys_trace_idle_exit();
 		__enable_irq();
 	}
 #if defined(CONFIG_PM_S2RAM)
 	else if (state == PM_STATE_SUSPEND_TO_RAM) {
 		__disable_irq();
+		sys_trace_idle();
 		s2ram_enter();
 		/* On resuming or error we return exactly *HERE* */
 		s2ram_exit();
+		sys_trace_idle_exit();
 		__enable_irq();
 	}
 #endif
diff --git a/soc/nordic/nrf54h/soc.c b/soc/nordic/nrf54h/soc.c
index 43c84e1b9a7..6dc8100e00c 100644
--- a/soc/nordic/nrf54h/soc.c
+++ b/soc/nordic/nrf54h/soc.c
@@ -18,6 +18,7 @@
 #include <hal/nrf_lrcconf.h>
 #include <hal/nrf_spu.h>
 #include <hal/nrf_memconf.h>
+#include <hal/nrf_nfct.h>
 #include <soc/nrfx_coredep.h>
 #include <soc_lrcconf.h>
 #include <dmm.h>
@@ -151,6 +152,11 @@ static int nordicsemi_nrf54h_init(void)
 	nrf_spu_periph_perm_dmasec_set(spu, nrf_address_slave_get(ccm030_addr), true);
 #endif
 
+	if (DT_NODE_HAS_STATUS(DT_NODELABEL(nfct), disabled) &&
+	    DT_PROP_OR(DT_NODELABEL(nfct), nfct_pins_as_gpios, 0)) {
+		nrf_nfct_pad_config_enable_set(NRF_NFCT, false);
+	}
+
 	return 0;
 }
 
diff --git a/soc/nordic/nrf54l/Kconfig b/soc/nordic/nrf54l/Kconfig
index 8f7297b75fe..69f075333b8 100644
--- a/soc/nordic/nrf54l/Kconfig
+++ b/soc/nordic/nrf54l/Kconfig
@@ -14,6 +14,7 @@ config SOC_NRF54L_CPUAPP_COMMON
 	select ARM
 	select ARMV8_M_DSP
 	select CPU_CORTEX_M33
+	select CPU_CORTEX_M_HAS_DWT
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_ICACHE
 	select CPU_HAS_ARM_SAU
diff --git a/soc/nordic/nrf54l/Kconfig.defconfig b/soc/nordic/nrf54l/Kconfig.defconfig
index b6ba2a07a87..03a93d4cda8 100644
--- a/soc/nordic/nrf54l/Kconfig.defconfig
+++ b/soc/nordic/nrf54l/Kconfig.defconfig
@@ -12,9 +12,26 @@ if ARM
 config CORTEX_M_SYSTICK
 	default !NRF_GRTC_TIMER
 
+# Start SYSCOUNTER on driver init
+config NRF_GRTC_START_SYSCOUNTER
+	default NRF_GRTC_TIMER
+
 config CACHE_NRF_CACHE
 	default y if EXTERNAL_CACHE
 
+config CACHE_MANAGEMENT
+	default y
+
+choice CACHE_TYPE
+	default EXTERNAL_CACHE
+endchoice
+
+# MPU-based null-pointer dereferencing detection cannot
+# be applied as the (0x0 - 0x400) is unmapped for this target.
+choice NULL_POINTER_EXCEPTION_DETECTION
+	default NULL_POINTER_EXCEPTION_DETECTION_NONE
+endchoice
+
 endif # ARM
 
 if RISCV
diff --git a/soc/nordic/nrf54l/Kconfig.defconfig.nrf54l20_enga_cpuflpr b/soc/nordic/nrf54l/Kconfig.defconfig.nrf54l20_enga_cpuflpr
index 4da2c703660..dd8fed9db58 100644
--- a/soc/nordic/nrf54l/Kconfig.defconfig.nrf54l20_enga_cpuflpr
+++ b/soc/nordic/nrf54l/Kconfig.defconfig.nrf54l20_enga_cpuflpr
@@ -6,6 +6,6 @@
 if SOC_NRF54L20_ENGA_CPUFLPR
 
 config NUM_IRQS
-	default 287
+	default 306
 
 endif # SOC_NRF54L20_ENGA_CPUFLPR
diff --git a/soc/nordic/nrf54l/soc.c b/soc/nordic/nrf54l/soc.c
index 475615271cf..737a0fbaa97 100644
--- a/soc/nordic/nrf54l/soc.c
+++ b/soc/nordic/nrf54l/soc.c
@@ -61,7 +61,7 @@ static inline void power_and_clock_configuration(void)
 	int32_t slope_k = (int32_t)(slope_field_k ^ slope_sign_k) - (int32_t)slope_sign_k;
 
 	/* As specified in the nRF54L15 PS:
-	 * CAPVALUE = round( (CAPACITANCE - 4) * (FICR->XOSC32KTRIM.SLOPE + 0.765625 * 2^9)/(2^9)
+	 * CAPVALUE = round( (2*CAPACITANCE - 12) * (FICR->XOSC32KTRIM.SLOPE + 0.765625 * 2^9)/(2^9)
 	 *            + FICR->XOSC32KTRIM.OFFSET/(2^6) );
 	 * where CAPACITANCE is the desired capacitor value in pF, holding any
 	 * value between 4 pF and 18 pF in 0.5 pF steps.
@@ -82,7 +82,7 @@ static inline void power_and_clock_configuration(void)
 	 * offset_k should be divided by 2^6, but to add it to value shifted by 2^9 we have to
 	 * multiply it be 2^3.
 	 */
-	uint32_t mid_val = (cap_val_encoded - 4UL) * (uint32_t)(slope_k + 392UL)
+	uint32_t mid_val = (2UL * cap_val_encoded - 12UL) * (uint32_t)(slope_k + 392UL)
 			   + (offset_k << 3UL);
 
 	/* Get integer part of the INTCAP code */
diff --git a/soc/nuvoton/npcx/Kconfig.soc b/soc/nuvoton/npcx/Kconfig.soc
index 1c8002f8553..be440875878 100644
--- a/soc/nuvoton/npcx/Kconfig.soc
+++ b/soc/nuvoton/npcx/Kconfig.soc
@@ -9,4 +9,17 @@ config SOC_FAMILY_NPCX
 config SOC_FAMILY
 	default "nuvoton_npcx" if SOC_FAMILY_NPCX
 
+config NPCX_SOC_VARIANT_NPCXN
+	bool
+	select SOC_FAMILY_NPCX
+
+config NPCX_SOC_VARIANT_NPCKN
+	bool
+	select SOC_FAMILY_NPCX
+
+config NPCX_SOC_VARIANT
+	string
+	default "npcxn" if NPCX_SOC_VARIANT_NPCXN
+	default "npckn" if NPCX_SOC_VARIANT_NPCKN
+
 rsource "*/Kconfig.soc"
diff --git a/soc/nuvoton/npcx/common/CMakeLists.txt b/soc/nuvoton/npcx/common/CMakeLists.txt
index 86780d1ad68..8b883247136 100644
--- a/soc/nuvoton/npcx/common/CMakeLists.txt
+++ b/soc/nuvoton/npcx/common/CMakeLists.txt
@@ -1,11 +1,13 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_include_directories(.)
+
 zephyr_sources_ifdef(CONFIG_PM power.c)
 zephyr_sources(
   scfg.c
-  registers.c
+  ${CONFIG_NPCX_SOC_VARIANT}/registers.c
 )
+zephyr_include_directories(${CONFIG_NPCX_SOC_VARIANT}/include)
 
 # Check for disabling header CRC.
 if (NOT DEFINED CONFIG_NPCX_HEADER_ENABLE_HEADER_CRC)
diff --git a/soc/nuvoton/npcx/common/npcxn/include/clock_def.h b/soc/nuvoton/npcx/common/npcxn/include/clock_def.h
new file mode 100644
index 00000000000..249c613ce70
--- /dev/null
+++ b/soc/nuvoton/npcx/common/npcxn/include/clock_def.h
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2020 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _NUVOTON_NPCX_CLOCK_DEF_H_
+#define _NUVOTON_NPCX_CLOCK_DEF_H_
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <zephyr/devicetree.h>
+#include <soc_clock.h>
+
+/* FMUL clock */
+#if (OFMCLK > (MAX_OFMCLK / 2))
+#define FMCLK (OFMCLK / 2) /* FMUL clock = OFMCLK/2 */
+#else
+#define FMCLK OFMCLK /* FMUL clock = OFMCLK */
+#endif
+
+/* APBs source clock */
+#define APBSRC_CLK OFMCLK
+
+/* AHB6 clock */
+#if (CORE_CLK > (MAX_OFMCLK / 2))
+#define AHB6DIV_VAL 1 /* AHB6_CLK = CORE_CLK/2 */
+#else
+#define AHB6DIV_VAL 0 /* AHB6_CLK = CORE_CLK */
+#endif
+
+/* FIU clock divider */
+#if (CORE_CLK > (MAX_OFMCLK / 2))
+#define FIUDIV_VAL 1 /* FIU_CLK = CORE_CLK/2 */
+#else
+#define FIUDIV_VAL 0 /* FIU_CLK = CORE_CLK */
+#endif
+
+#if defined(CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1)
+#if (CORE_CLK > (MAX_OFMCLK / 2))
+#define FIU1DIV_VAL 1 /* FIU1_CLK = CORE_CLK/2 */
+#else
+#define FIU1DIV_VAL 0 /* FIU1_CLK = CORE_CLK */
+#endif
+#endif /* CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1 */
+
+/* I3C clock divider */
+#if (OFMCLK == MHZ(120)) /* MCLkD must between 40 mhz to 50 mhz*/
+#define MCLKD_SL 2       /* I3C_CLK = (MCLK / 3) */
+#elif (OFMCLK <= MHZ(100) && OFMCLK >= MHZ(80))
+#define MCLKD_SL 1 /* I3C_CLK = (MCLK / 2) */
+#else
+#define MCLKD_SL 0 /* I3C_CLK = MCLK */
+#endif
+
+/* Get APB clock freq */
+#define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))
+
+/*
+ * Frequency multiplier M/N value definitions according to the requested
+ * OFMCLK (Unit:Hz).
+ */
+#if (OFMCLK > (MAX_OFMCLK / 2))
+#define HFCGN_VAL 0x82 /* Set XF_RANGE as 1 */
+#else
+#define HFCGN_VAL 0x02
+#endif
+#if (OFMCLK == 120000000)
+#define HFCGMH_VAL 0x0E
+#define HFCGML_VAL 0x4E
+#elif (OFMCLK == 100000000)
+#define HFCGMH_VAL 0x0B
+#define HFCGML_VAL 0xEC
+#elif (OFMCLK == 96000000)
+#define HFCGMH_VAL 0x0B
+#define HFCGML_VAL 0x72
+#elif (OFMCLK == 90000000)
+#define HFCGMH_VAL 0x0A
+#define HFCGML_VAL 0xBA
+#elif (OFMCLK == 80000000)
+#define HFCGMH_VAL 0x09
+#define HFCGML_VAL 0x89
+#elif (OFMCLK == 66000000)
+#define HFCGMH_VAL 0x07
+#define HFCGML_VAL 0xDE
+#elif (OFMCLK == 50000000)
+#define HFCGMH_VAL 0x0B
+#define HFCGML_VAL 0xEC
+#elif (OFMCLK == 48000000)
+#define HFCGMH_VAL 0x0B
+#define HFCGML_VAL 0x72
+#else
+#error "Unsupported OFMCLK Frequency"
+#endif
+
+/* Clock prescaler configurations in different series */
+#define VAL_HFCGP ((FPRED_VAL << 4) | AHB6DIV_VAL)
+#if defined(FIU1DIV_VAL)
+#define VAL_HFCBCD ((FIU1DIV_VAL << 4) | (FIUDIV_VAL << 2))
+#else
+#define VAL_HFCBCD (FIUDIV_VAL << 4)
+#endif /* FIU1DIV_VAL */
+#define VAL_HFCBCD1 (APB1DIV_VAL | (APB2DIV_VAL << 4))
+#if defined(APB4DIV_VAL)
+#define VAL_HFCBCD2 (APB3DIV_VAL | (APB4DIV_VAL << 4))
+#else
+#define VAL_HFCBCD2 APB3DIV_VAL
+#endif /* APB4DIV_VAL */
+/* I3C1~I3C3 share the same configuration */
+#define VAL_HFCBCD3 MCLKD_SL
+
+#endif /* _NUVOTON_NPCX_CLOCK_DEF_H_ */
diff --git a/soc/nuvoton/npcx/common/npcxn/include/reg_def.h b/soc/nuvoton/npcx/common/npcxn/include/reg_def.h
new file mode 100644
index 00000000000..4ce9c0a9986
--- /dev/null
+++ b/soc/nuvoton/npcx/common/npcxn/include/reg_def.h
@@ -0,0 +1,2191 @@
+/*
+ * Copyright (c) 2025 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _NUVOTON_NPCX_REG_DEF_H
+#define _NUVOTON_NPCX_REG_DEF_H
+
+#include <reg_access.h>
+
+/*
+ * Core Domain Clock Generator (CDCG) device registers
+ */
+struct cdcg_reg {
+	/* High Frequency Clock Generator (HFCG) registers */
+	/* 0x000: HFCG Control */
+	volatile uint8_t HFCGCTRL;
+	volatile uint8_t reserved1;
+	/* 0x002: HFCG M Low Byte Value */
+	volatile uint8_t HFCGML;
+	volatile uint8_t reserved2;
+	/* 0x004: HFCG M High Byte Value */
+	volatile uint8_t HFCGMH;
+	volatile uint8_t reserved3;
+	/* 0x006: HFCG N Value */
+	volatile uint8_t HFCGN;
+	volatile uint8_t reserved4;
+	/* 0x008: HFCG Prescaler */
+	volatile uint8_t HFCGP;
+	volatile uint8_t reserved5[7];
+	/* 0x010: HFCG Bus Clock Dividers */
+	volatile uint8_t HFCBCD;
+	volatile uint8_t reserved6;
+	/* 0x012: HFCG Bus Clock Dividers */
+	volatile uint8_t HFCBCD1;
+	volatile uint8_t reserved7;
+	/* 0x014: HFCG Bus Clock Dividers */
+	volatile uint8_t HFCBCD2;
+	volatile uint8_t reserved12[8];
+	/* 0x01d: HFCG Bus Clock Dividers */
+	volatile uint8_t HFCBCD3;
+	volatile uint8_t reserved8[226];
+
+	/* Low Frequency Clock Generator (LFCG) registers */
+	/* 0x100: LFCG Control */
+	volatile uint8_t LFCGCTL;
+	volatile uint8_t reserved9;
+	/* 0x102: High-Frequency Reference Divisor I */
+	volatile uint16_t HFRDI;
+	/* 0x104: High-Frequency Reference Divisor F */
+	volatile uint16_t HFRDF;
+	/* 0x106: FRCLK Clock Divisor */
+	volatile uint16_t FRCDIV;
+	/* 0x108: Divisor Correction Value 1 */
+	volatile uint16_t DIVCOR1;
+	/* 0x10A: Divisor Correction Value 2 */
+	volatile uint16_t DIVCOR2;
+	volatile uint8_t reserved10[8];
+	/* 0x114: LFCG Control 2 */
+	volatile uint8_t LFCGCTL2;
+	volatile uint8_t reserved11;
+};
+
+/* CDCG register fields */
+#define NPCX_HFCGCTRL_LOAD     0
+#define NPCX_HFCGCTRL_LOCK     2
+#define NPCX_HFCGCTRL_CLK_CHNG 7
+
+#define NPCX_LFCGCTL2_XT_OSC_SL_EN 6
+
+/*
+ * Power Management Controller (PMC) device registers
+ */
+struct pmc_reg {
+	/* 0x000: Power Management Controller */
+	volatile uint8_t PMCSR;
+	volatile uint8_t reserved1[2];
+	/* 0x003: Enable in Sleep Control */
+	volatile uint8_t ENIDL_CTL;
+	/* 0x004: Disable in Idle Control */
+	volatile uint8_t DISIDL_CTL;
+	/* 0x005: Disable in Idle Control 1 */
+	volatile uint8_t DISIDL_CTL1;
+	volatile uint8_t reserved2[2];
+	/* 0x008 - 0D: Power-Down Control 1 - 6 */
+	volatile uint8_t PWDWN_CTL1[6];
+	volatile uint8_t reserved3[18];
+	/* 0x020 - 21: Power-Down Control 1 - 2 */
+	volatile uint8_t RAM_PD[2];
+	volatile uint8_t reserved4[2];
+	/* 0x024: Power-Down Control 7 */
+	volatile uint8_t PWDWN_CTL7[1];
+};
+
+/* PMC internal inline functions for multi-registers */
+static inline uint32_t npcx_pwdwn_ctl_offset(uint32_t ctl_no)
+{
+	if (ctl_no < 6) {
+		return 0x008 + ctl_no;
+	} else {
+		return 0x024 + ctl_no - 6;
+	}
+}
+
+/* Macro functions for PMC multi-registers */
+#define NPCX_PWDWN_CTL(base, n) (*(volatile uint8_t *)(base + npcx_pwdwn_ctl_offset(n)))
+
+/* PMC register fields */
+#define NPCX_PMCSR_DI_INSTW        0
+#define NPCX_PMCSR_DHF             1
+#define NPCX_PMCSR_IDLE            2
+#define NPCX_PMCSR_NWBI            3
+#define NPCX_PMCSR_OHFC            6
+#define NPCX_PMCSR_OLFC            7
+#define NPCX_DISIDL_CTL_RAM_DID    5
+#define NPCX_ENIDL_CTL_ADC_LFSL    7
+#define NPCX_ENIDL_CTL_LP_WK_CTL   6
+#define NPCX_ENIDL_CTL_PECI_ENI    2
+#define NPCX_ENIDL_CTL_ADC_ACC_DIS 1
+
+/* Macro functions for Development and Debugger Interface (DDI) registers */
+#define NPCX_DBGCTRL(base)   (*(volatile uint8_t *)(base + 0x004))
+#define NPCX_DBGFRZEN1(base) (*(volatile uint8_t *)(base + 0x006))
+#define NPCX_DBGFRZEN2(base) (*(volatile uint8_t *)(base + 0x007))
+#define NPCX_DBGFRZEN3(base) (*(volatile uint8_t *)(base + 0x008))
+#define NPCX_DBGFRZEN4(base) (*(volatile uint8_t *)(base + 0x009))
+
+/* DDI register fields */
+#define NPCX_DBGCTRL_CCDEV_SEL      FIELD(6, 2)
+#define NPCX_DBGCTRL_CCDEV_DIR      5
+#define NPCX_DBGCTRL_SEQ_WK_EN      4
+#define NPCX_DBGCTRL_FRCLK_SEL_DIS  3
+#define NPCX_DBGFRZEN1_SPIFEN       7
+#define NPCX_DBGFRZEN1_HIFEN        6
+#define NPCX_DBGFRZEN1_ESPISEN      5
+#define NPCX_DBGFRZEN1_UART1FEN     4
+#define NPCX_DBGFRZEN1_SMB3FEN      3
+#define NPCX_DBGFRZEN1_SMB2FEN      2
+#define NPCX_DBGFRZEN1_MFT2FEN      1
+#define NPCX_DBGFRZEN1_MFT1FEN      0
+#define NPCX_DBGFRZEN2_ITIM6FEN     7
+#define NPCX_DBGFRZEN2_ITIM5FEN     6
+#define NPCX_DBGFRZEN2_ITIM4FEN     5
+#define NPCX_DBGFRZEN2_ITIM64FEN    3
+#define NPCX_DBGFRZEN2_SMB1FEN      2
+#define NPCX_DBGFRZEN2_SMB0FEN      1
+#define NPCX_DBGFRZEN2_MFT3FEN      0
+#define NPCX_DBGFRZEN3_GLBL_FRZ_DIS 7
+#define NPCX_DBGFRZEN3_ITIM3FEN     6
+#define NPCX_DBGFRZEN3_ITIM2FEN     5
+#define NPCX_DBGFRZEN3_ITIM1FEN     4
+#define NPCX_DBGFRZEN3_I3CFEN       2
+#define NPCX_DBGFRZEN3_SMB4FEN      1
+#define NPCX_DBGFRZEN3_SHMFEN       0
+#define NPCX_DBGFRZEN4_UART2FEN     6
+#define NPCX_DBGFRZEN4_UART3FEN     5
+#define NPCX_DBGFRZEN4_UART4FEN     4
+#define NPCX_DBGFRZEN4_LCTFEN       3
+#define NPCX_DBGFRZEN4_SMB7FEN      2
+#define NPCX_DBGFRZEN4_SMB6FEN      1
+#define NPCX_DBGFRZEN4_SMB5FEN      0
+
+/*
+ * System Configuration (SCFG) device registers
+ */
+struct scfg_reg {
+	/* 0x000: Device Control */
+	volatile uint8_t DEVCNT;
+	/* 0x001: Straps Status */
+	volatile uint8_t STRPST;
+	/* 0x002: Reset Control and Status */
+	volatile uint8_t RSTCTL;
+	volatile uint8_t reserved1;
+	/* 0x004: Device Control 3*/
+	volatile uint8_t DEV_CTL3;
+	volatile uint8_t reserved2;
+	/* 0x006: Device Control 4 */
+	volatile uint8_t DEV_CTL4;
+	volatile uint8_t reserved3[9];
+	/* 0x010 - 1F: Device Alternate Function 0 - F */
+	volatile uint8_t DEVALT0[16];
+	volatile uint8_t reserved4[6];
+	/* 0x026: Low-Voltage GPIO Pins Control 5 */
+	volatile uint8_t LV_GPIO_CTL5[1];
+	volatile uint8_t reserved5;
+	/* 0x028: Pull-Up/Pull-Down Enable 0 */
+	volatile uint8_t PUPD_EN0;
+	/* 0x029: Pull-Up/Pull-Down Enable 1 */
+	volatile uint8_t PUPD_EN1;
+	/* 0x02A - 2E: Low-Voltage GPIO Pins Control 0 - 4 */
+	volatile uint8_t LV_GPIO_CTL0[5];
+};
+
+/* Macro functions for SCFG multi-registers */
+#define NPCX_DEV_CTL(base, n)     (*(volatile uint8_t *)(base + n))
+#define NPCX_DEVALT(base, n)      (*(volatile uint8_t *)(base + NPCX_DEVALT_OFFSET(n)))
+#define NPCX_DEVALT_LK(base, n)   (*(volatile uint8_t *)(base + NPCX_DEVALT_LK_OFFSET(n)))
+#define NPCX_PUPD_EN(base, n)     (*(volatile uint8_t *)(base + NPCX_PUPD_EN_OFFSET(n)))
+#define NPCX_LV_GPIO_CTL(base, n) (*(volatile uint8_t *)(base + NPCX_LV_GPIO_CTL_OFFSET(n)))
+
+#define NPCX_JEN_CTL1_OFFSET 0x120
+#define NPCX_JEN_CTL1(base)  (*(volatile uint8_t *)(base + (NPCX_JEN_CTL1_OFFSET)))
+
+#define NPCX_JEN_CTL1_JEN_EN      FIELD(0, 4)
+#define NPCX_JEN_CTL1_JEN_HEN     FIELD(4, 4)
+#define NPCX_JEN_CTL1_JEN_ENABLE  0x9
+#define NPCX_JEN_CTL1_JEN_DISABLE 0x6
+
+/* SCFG register fields */
+#define NPCX_DEVCNT_F_SPI_TRIS         6
+#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD  FIELD(2, 2)
+#define NPCX_DEVCNT_JEN1_HEN           5
+#define NPCX_DEVCNT_JEN0_HEN           4
+#define NPCX_STRPST_TRIST              1
+#define NPCX_STRPST_TEST               2
+#define NPCX_STRPST_JEN1               4
+#define NPCX_STRPST_JEN0               5
+#define NPCX_STRPST_SPI_COMP           7
+#define NPCX_RSTCTL_VCC1_RST_STS       0
+#define NPCX_RSTCTL_DBGRST_STS         1
+#define NPCX_RSTCTL_VCC1_RST_SCRATCH   3
+#define NPCX_RSTCTL_LRESET_PLTRST_MODE 5
+#define NPCX_RSTCTL_HIPRST_MODE        6
+#define NPCX_DEV_CTL3_RNGINT_MD        1
+#define NPCX_DEV_CTL3_FVCC1_PURST_EN   2
+#define NPCX_DEV_CTL3_I3C1_MS          3
+#define NPCX_DEV_CTL3_I3C2_MS          4
+#define NPCX_DEV_CTL3_I3C3_MS          5
+#define NPCX_DEV_CTL3_SIO_CLK_SEL      FIELD(6, 2)
+#define NPCX_DEV_CTL4_F_SPI_SLLK       2
+#define NPCX_DEV_CTL4_SPI_SP_SEL       4
+#define NPCX_DEV_CTL4_WP_IF            5
+#define NPCX_DEV_CTL4_VCC1_RST_LK      6
+#define NPCX_DEVPU0_I2C0_0_PUE         0
+#define NPCX_DEVPU0_I2C0_1_PUE         1
+#define NPCX_DEVPU0_I2C1_0_PUE         2
+#define NPCX_DEVPU0_I2C2_0_PUE         4
+#define NPCX_DEVPU0_I2C3_0_PUE         6
+#define NPCX_DEVPU1_F_SPI_PUD_EN       7
+
+#if defined(CONFIG_SOC_SERIES_NPCX4)
+/* I3C module controller, target mode for the MDMA module operation */
+#define NPCX_DEV_CTL3_I3C_MODE_BIT(inst_id) BIT(inst_id + 3)
+#endif /* End of CONFIG_SOC_SERIES_NPCX4 */
+
+/* Supported host interface type for HIF_TYP_SEL FILED in DEVCNT register. */
+enum npcx_hif_type {
+	NPCX_HIF_TYPE_NONE,
+	NPCX_HIF_TYPE_LPC,
+	NPCX_HIF_TYPE_ESPI_SHI,
+};
+
+/* Supported VOSCCLK frequency for SIO_CLK_SEL FILED in DEV_CTL3 register. */
+enum npcx_voscclk_type {
+	NPCX_VOSCCLK_96MHz,
+	NPCX_VOSCCLK_100MHz,
+	NPCX_VOSCCLK_120MHz,
+	NPCX_VOSCCLK_90MHz,
+};
+
+/*
+ * System Glue (GLUE) device registers
+ */
+struct glue_reg {
+	volatile uint8_t reserved1[2];
+	/* 0x002: SMBus Start Bit Detection */
+	volatile uint8_t SMB_SBD;
+	/* 0x003: SMBus Event Enable */
+	volatile uint8_t SMB_EEN;
+	volatile uint8_t reserved2[12];
+	/* 0x010: Simple Debug Port Data 0 */
+	volatile uint8_t SDPD0;
+	volatile uint8_t reserved3;
+	/* 0x012: Simple Debug Port Data 1 */
+	volatile uint8_t SDPD1;
+	volatile uint8_t reserved4;
+	/* 0x014: Simple Debug Port Control and Status */
+	volatile uint8_t SDP_CTS;
+	volatile uint8_t reserved5[12];
+	/* 0x021: SMBus Bus Select */
+	volatile uint8_t SMB_SEL;
+	volatile uint8_t reserved6[5];
+	/* 0x027: PSL Control and Status */
+	volatile uint8_t PSL_CTS;
+};
+
+/* GLUE register fields */
+/* PSL input detection mode is configured by bits 7:4 of PSL_CTS */
+#define NPCX_PSL_CTS_MODE_BIT(bit)  BIT(bit + 4)
+/* PSL input assertion events are reported by bits 3:0 of PSL_CTS */
+#define NPCX_PSL_CTS_EVENT_BIT(bit) BIT(bit)
+
+/*
+ * Universal Asynchronous Receiver-Transmitter (UART) device registers
+ */
+struct uart_reg {
+	/* 0x000: Transmit Data Buffer */
+	volatile uint8_t UTBUF;
+	volatile uint8_t reserved1;
+	/* 0x002: Receive Data Buffer */
+	volatile uint8_t URBUF;
+	volatile uint8_t reserved2;
+	/* 0x004: Interrupt Control */
+	volatile uint8_t UICTRL;
+	volatile uint8_t reserved3;
+	/* 0x006: Status */
+	volatile uint8_t USTAT;
+	volatile uint8_t reserved4;
+	/* 0x008: Frame Select */
+	volatile uint8_t UFRS;
+	volatile uint8_t reserved5;
+	/* 0x00A: Mode Select */
+	volatile uint8_t UMDSL;
+	volatile uint8_t reserved6;
+	/* 0x00C: Baud Rate Divisor */
+	volatile uint8_t UBAUD;
+	volatile uint8_t reserved7;
+	/* 0x00E: Baud Rate Prescaler */
+	volatile uint8_t UPSR;
+	volatile uint8_t reserved8[17];
+	/* 0x020: FIFO Mode Transmit Status */
+	volatile uint8_t UFTSTS;
+	volatile uint8_t reserved9;
+	/* 0x022: FIFO Mode Receive Status */
+	volatile uint8_t UFRSTS;
+	volatile uint8_t reserved10;
+	/* 0x024: FIFO Mode Transmit Control */
+	volatile uint8_t UFTCTL;
+	volatile uint8_t reserved11;
+	/* 0x026: FIFO Mode Receive Control */
+	volatile uint8_t UFRCTL;
+};
+
+/* UART register fields */
+#define NPCX_UICTRL_TBE      0
+#define NPCX_UICTRL_RBF      1
+#define NPCX_UICTRL_ETI      5
+#define NPCX_UICTRL_ERI      6
+#define NPCX_UICTRL_EEI      7
+#define NPCX_USTAT_PE        0
+#define NPCX_USTAT_FE        1
+#define NPCX_USTAT_DOE       2
+#define NPCX_USTAT_ERR       3
+#define NPCX_USTAT_BKD       4
+#define NPCX_USTAT_RB9       5
+#define NPCX_USTAT_XMIP      6
+#define NPCX_UFRS_CHAR_FIELD FIELD(0, 2)
+#define NPCX_UFRS_STP        2
+#define NPCX_UFRS_XB9        3
+#define NPCX_UFRS_PSEL_FIELD FIELD(4, 2)
+#define NPCX_UFRS_PEN        6
+#define NPCX_UMDSL_FIFO_MD   0
+#define NPCX_UMDSL_ETD       4
+#define NPCX_UMDSL_ERD       5
+
+#define NPCX_UFTSTS_TEMPTY_LVL       FIELD(0, 5)
+#define NPCX_UFTSTS_TEMPTY_LVL_STS   5
+#define NPCX_UFTSTS_TFIFO_EMPTY_STS  6
+#define NPCX_UFTSTS_NXMIP            7
+#define NPCX_UFRSTS_RFULL_LVL_STS    5
+#define NPCX_UFRSTS_RFIFO_NEMPTY_STS 6
+#define NPCX_UFRSTS_ERR              7
+#define NPCX_UFTCTL_TEMPTY_LVL_SEL   FIELD(0, 5)
+#define NPCX_UFTCTL_TEMPTY_LVL_EN    5
+#define NPCX_UFTCTL_TEMPTY_EN        6
+#define NPCX_UFTCTL_NXMIP_EN         7
+#define NPCX_UFRCTL_RFULL_LVL_SEL    FIELD(0, 5)
+#define NPCX_UFRCTL_RFULL_LVL_EN     5
+#define NPCX_UFRCTL_RNEMPTY_EN       6
+#define NPCX_UFRCTL_ERR_EN           7
+
+/* Macro functions for MIWU multi-registers */
+#define NPCX_WKEDG(base, group)  (*(volatile uint8_t *)(base + NPCX_WKEDG_OFFSET(group)))
+#define NPCX_WKAEDG(base, group) (*(volatile uint8_t *)(base + NPCX_WKAEDG_OFFSET(group)))
+#define NPCX_WKPND(base, group)  (*(volatile uint8_t *)(base + NPCX_WKPND_OFFSET(group)))
+#define NPCX_WKPCL(base, group)  (*(volatile uint8_t *)(base + NPCX_WKPCL_OFFSET(group)))
+#define NPCX_WKEN(base, group)   (*(volatile uint8_t *)(base + NPCX_WKEN_OFFSET(group)))
+#define NPCX_WKINEN(base, group) (*(volatile uint8_t *)(base + NPCX_WKINEN_OFFSET(group)))
+#define NPCX_WKMOD(base, group)  (*(volatile uint8_t *)(base + NPCX_WKMOD_OFFSET(group)))
+#define NPCX_WKST(base, group)   (*(volatile uint8_t *)(base + NPCX_WKST_OFFSET(group)))
+
+/*
+ * General-Purpose I/O (GPIO) device registers
+ */
+struct gpio_reg {
+	/* 0x000: Port GPIOx Data Out */
+	volatile uint8_t PDOUT;
+	/* 0x001: Port GPIOx Data In */
+	volatile uint8_t PDIN;
+	/* 0x002: Port GPIOx Direction */
+	volatile uint8_t PDIR;
+	/* 0x003: Port GPIOx Pull-Up or Pull-Down Enable */
+	volatile uint8_t PPULL;
+	/* 0x004: Port GPIOx Pull-Up/Down Selection */
+	volatile uint8_t PPUD;
+	/* 0x005: Port GPIOx Drive Enable by VDD Present */
+	volatile uint8_t PENVDD;
+	/* 0x006: Port GPIOx Output Type */
+	volatile uint8_t PTYPE;
+	/* 0x007: Port GPIOx Lock Control */
+	volatile uint8_t PLOCK_CTL;
+};
+
+/*
+ * Pulse Width Modulator (PWM) device registers
+ */
+struct pwm_reg {
+	/* 0x000: Clock Prescaler */
+	volatile uint16_t PRSC;
+	/* 0x002: Cycle Time */
+	volatile uint16_t CTR;
+	/* 0x004: PWM Control */
+	volatile uint8_t PWMCTL;
+	volatile uint8_t reserved1;
+	/* 0x006: Duty Cycle */
+	volatile uint16_t DCR;
+	volatile uint8_t reserved2[4];
+	/* 0x00C: PWM Control Extended */
+	volatile uint8_t PWMCTLEX;
+	volatile uint8_t reserved3;
+};
+
+/* PWM register fields */
+#define NPCX_PWMCTL_INVP            0
+#define NPCX_PWMCTL_CKSEL           1
+#define NPCX_PWMCTL_HB_DC_CTL_FIELD FIELD(2, 2)
+#define NPCX_PWMCTL_PWR             7
+#define NPCX_PWMCTLEX_FCK_SEL_FIELD FIELD(4, 2)
+#define NPCX_PWMCTLEX_OD_OUT        7
+
+/*
+ * Analog-To-Digital Converter (ADC) device registers
+ */
+struct adc_reg {
+	/* 0x000: ADC Status */
+	volatile uint16_t ADCSTS;
+	/* 0x002: ADC Configuration */
+	volatile uint16_t ADCCNF;
+	/* 0x004: ADC Timing Control */
+	volatile uint16_t ATCTL;
+	/* 0x006: ADC Single Channel Address */
+	volatile uint16_t ASCADD;
+	/* 0x008: ADC Scan Channels Select */
+	volatile uint16_t ADCCS;
+	/* 0x00A: ADC Scan Channels Select 2 */
+	volatile uint16_t ADCCS2;
+	volatile uint8_t reserved1[14];
+	/* 0x01A:  Threshold Status */
+	volatile uint16_t THRCTS;
+	volatile uint8_t reserved2[4];
+	/* 0x020: Internal register 1 for ADC Speed */
+	volatile uint16_t ADCCNF2;
+	/* 0x022: Internal register 2 for ADC Speed */
+	volatile uint16_t GENDLY;
+	volatile uint8_t reserved3[2];
+	/* 0x026: Internal register 3 for ADC Speed */
+	volatile uint16_t MEAST;
+};
+
+/* ADC internal inline functions for multi-registers */
+#define CHNDAT(base, ch)   (*(volatile uint16_t *)((base) + NPCX_CHNDAT_OFFSET(ch)))
+#define THRCTL(base, ctrl) (*(volatile uint16_t *)(base + NPCX_THRCTL_OFFSET(ctrl)))
+
+/* ADC register fields */
+#define NPCX_ATCTL_SCLKDIV_FIELD FIELD(0, 6)
+#define NPCX_ATCTL_DLY_FIELD     FIELD(8, 3)
+#define NPCX_ASCADD_SADDR_FIELD  FIELD(0, 5)
+#define NPCX_ADCSTS_EOCEV        0
+#define NPCX_ADCSTS_EOCCEV       1
+#define NPCX_ADCCNF_ADCEN        0
+#define NPCX_ADCCNF_ADCMD_FIELD  FIELD(1, 2)
+#define NPCX_ADCCNF_ADCRPTC      3
+#define NPCX_ADCCNF_START        4
+#define NPCX_ADCCNF_ADCTTE       5
+#define NPCX_ADCCNF_INTECEN      6
+#define NPCX_ADCCNF_INTECCEN     7
+#define NPCX_ADCCNF_INTETCEN     8
+#define NPCX_ADCCNF_INTOVFEN     9
+#define NPCX_ADCCNF_STOP         11
+#define NPCX_CHNDAT_CHDAT_FIELD  FIELD(0, 10)
+#define NPCX_CHNDAT_NEW          15
+#define NPCX_THRCTS_ADC_WKEN     15
+#define NPCX_THRCTS_THR3_IEN     10
+#define NPCX_THRCTS_THR2_IEN     9
+#define NPCX_THRCTS_THR1_IEN     8
+#define NPCX_THRCTS_ADC_EVENT    7
+#define NPCX_THRCTS_THR3_STS     2
+#define NPCX_THRCTS_THR2_STS     1
+#define NPCX_THRCTS_THR1_STS     0
+#define NPCX_THR_DCTL_THRD_EN    15
+#define NPCX_THR_DCTL_THR_DVAL   FIELD(0, 10)
+
+/*
+ * Timer Watchdog (TWD) device registers
+ */
+struct twd_reg {
+	/* 0x000: Timer and Watchdog Configuration */
+	volatile uint8_t TWCFG;
+	volatile uint8_t reserved1;
+	/* 0x002: Timer and Watchdog Clock Prescaler */
+	volatile uint8_t TWCP;
+	volatile uint8_t reserved2;
+	/* 0x004: TWD Timer 0 */
+	volatile uint16_t TWDT0;
+	/* 0x006: TWDT0 Control and Status */
+	volatile uint8_t T0CSR;
+	volatile uint8_t reserved3;
+	/* 0x008: Watchdog Count */
+	volatile uint8_t WDCNT;
+	volatile uint8_t reserved4;
+	/* 0x00A: Watchdog Service Data Match */
+	volatile uint8_t WDSDM;
+	volatile uint8_t reserved5;
+	/* 0x00C: TWD Timer 0 Counter */
+	volatile uint16_t TWMT0;
+	/* 0x00E: Watchdog Counter */
+	volatile uint8_t TWMWD;
+	volatile uint8_t reserved6;
+	/* 0x010: Watchdog Clock Prescaler */
+	volatile uint8_t WDCP;
+	volatile uint8_t reserved7;
+};
+
+/* TWD register fields */
+#define NPCX_TWCFG_LTWCFG    0
+#define NPCX_TWCFG_LTWCP     1
+#define NPCX_TWCFG_LTWDT0    2
+#define NPCX_TWCFG_LWDCNT    3
+#define NPCX_TWCFG_WDCT0I    4
+#define NPCX_TWCFG_WDSDME    5
+#define NPCX_T0CSR_RST       0
+#define NPCX_T0CSR_TC        1
+#define NPCX_T0CSR_WDLTD     3
+#define NPCX_T0CSR_WDRST_STS 4
+#define NPCX_T0CSR_WD_RUN    5
+#define NPCX_T0CSR_TESDIS    7
+
+/*
+ * Enhanced Serial Peripheral Interface (eSPI) device registers
+ */
+struct espi_reg {
+	/* 0x000: eSPI Identification */
+	volatile uint32_t ESPIID;
+	/* 0x004: eSPI Configuration */
+	volatile uint32_t ESPICFG;
+	/* 0x008: eSPI Status */
+	volatile uint32_t ESPISTS;
+	/* 0x00C: eSPI Interrupt Enable */
+	volatile uint32_t ESPIIE;
+	/* 0x010: eSPI Wake-Up Enable */
+	volatile uint32_t ESPIWE;
+	/* 0x014: Virtual Wire Register Index */
+	volatile uint32_t VWREGIDX;
+	/* 0x018: Virtual Wire Register Data */
+	volatile uint32_t VWREGDATA;
+	/* 0x01C: OOB Receive Buffer Read Head */
+	volatile uint32_t OOBRXRDHEAD;
+	/* 0x020: OOB Transmit Buffer Write Head */
+	volatile uint32_t OOBTXWRHEAD;
+	/* 0x024: OOB Channel Control */
+	volatile uint32_t OOBCTL;
+	/* 0x028: Flash Receive Buffer Read Head */
+	volatile uint32_t FLASHRXRDHEAD;
+	/* 0x02C: Flash Transmit Buffer Write Head */
+	volatile uint32_t FLASHTXWRHEAD;
+	volatile uint32_t reserved1;
+	/* 0x034: Flash Channel Configuration */
+	volatile uint32_t FLASHCFG;
+	/* 0x038: Flash Channel Control */
+	volatile uint32_t FLASHCTL;
+	/* 0x03C: eSPI Error Status */
+	volatile uint32_t ESPIERR;
+	/* 0x040: Peripheral Bus Master Receive Buffer Read Head */
+	volatile uint32_t PBMRXRDHEAD;
+	/* 0x044: Peripheral Bus Master Transmit Buffer Write Head */
+	volatile uint32_t PBMTXWRHEAD;
+	/* 0x048: Peripheral Channel Configuration */
+	volatile uint32_t PERCFG;
+	/* 0x04C: Peripheral Channel Control */
+	volatile uint32_t PERCTL;
+	/* 0x050: Status Image Register */
+	volatile uint16_t STATUS_IMG;
+	volatile uint16_t reserved2[79];
+	/* 0x0F0: NPCX specific eSPI Register1 */
+	volatile uint8_t NPCX_ONLY_ESPI_REG1;
+	/* 0x0F1: NPCX specific eSPI Register2 */
+	volatile uint8_t NPCX_ONLY_ESPI_REG2;
+	volatile uint16_t reserved3[7];
+	/* 0x100 - 127: Virtual Wire Event Slave-to-Master 0 - 9 */
+	volatile uint32_t VWEVSM[10];
+	volatile uint32_t reserved4[6];
+	/* 0x140 - 16F: Virtual Wire Event Master-to-Slave 0 - 11 */
+	volatile uint32_t VWEVMS[12];
+	volatile uint32_t reserved5[4];
+	/* 0x180 - 1BF: Virtual Wire GPIO Event Master-to-Slave 0 - 15 */
+	volatile uint32_t VWGPSM[16];
+	volatile uint32_t reserved6[79];
+	/* 0x2FC: Virtual Wire Channel Control */
+	volatile uint32_t VWCTL;
+	/* 0x300 - 34F: OOB Receive Buffer 0 - 19 */
+	volatile uint32_t OOBRXBUF[20];
+	volatile uint32_t reserved7[12];
+	/* 0x380 - 3CF: OOB Transmit Buffer 0-19 */
+	volatile uint32_t OOBTXBUF[20];
+	volatile uint32_t reserved8[11];
+	/* 0x3FC: OOB Channel Control used in 'direct' mode */
+	volatile uint32_t OOBCTL_DIRECT;
+	/* 0x400 - 443: Flash Receive Buffer 0-17 */
+	volatile uint32_t FLASHRXBUF[18];
+	volatile uint32_t reserved9[14];
+	/* 0x480 - 497: Flash Transmit Buffer 0-16 */
+	volatile uint32_t FLASHTXBUF[17];
+	volatile uint32_t reserved10[14];
+	/* 0x4FC: Flash Channel Control used in 'direct' mode */
+	volatile uint32_t FLASHCTL_DIRECT;
+	volatile uint32_t reserved12[64];
+	/* 0x600 - 63F */
+	volatile uint32_t FLASH_PRTR_BADDR[16];
+	/* 0x640 - 67F */
+	volatile uint32_t FLASH_PRTR_HADDR[16];
+	/* 0x680 - 6BF */
+	volatile uint32_t FLASH_RGN_TAG_OVR[16];
+	volatile uint32_t reserved13[80];
+	/* 0x800 */
+	volatile uint32_t FLASH_RPMC_CFG_1;
+	/* 0x804 */
+	volatile uint32_t FLASH_RPMC_CFG_2;
+	/* 0x808 */
+	volatile uint32_t RMAP_FLASH_OFFS;
+	/* 0x80C */
+	volatile uint32_t RMAP_DST_BASE;
+	/* 0x810 */
+	volatile uint32_t RMAP_WIN_SIZE;
+	/* 0x814 */
+	volatile uint32_t FLASHBASE;
+	volatile uint32_t reserved14[58];
+};
+
+/* eSPI register fields */
+#define NPCX_ESPICFG_PCHANEN             0
+#define NPCX_ESPICFG_VWCHANEN            1
+#define NPCX_ESPICFG_OOBCHANEN           2
+#define NPCX_ESPICFG_FLASHCHANEN         3
+#define NPCX_ESPICFG_HPCHANEN            4
+#define NPCX_ESPICFG_HVWCHANEN           5
+#define NPCX_ESPICFG_HOOBCHANEN          6
+#define NPCX_ESPICFG_HFLASHCHANEN        7
+#define NPCX_ESPICFG_CHANS_FIELD         FIELD(0, 4)
+#define NPCX_ESPICFG_HCHANS_FIELD        FIELD(4, 4)
+#define NPCX_ESPICFG_IOMODE_FIELD        FIELD(8, 2)
+#define NPCX_ESPICFG_MAXFREQ_FIELD       FIELD(10, 3)
+#define NPCX_ESPICFG_FLCHANMODE          16
+#define NPCX_ESPICFG_PCCHN_SUPP          24
+#define NPCX_ESPICFG_VWCHN_SUPP          25
+#define NPCX_ESPICFG_OOBCHN_SUPP         26
+#define NPCX_ESPICFG_FLASHCHN_SUPP       27
+#define NPCX_ESPIIE_IBRSTIE              0
+#define NPCX_ESPIIE_CFGUPDIE             1
+#define NPCX_ESPIIE_BERRIE               2
+#define NPCX_ESPIIE_OOBRXIE              3
+#define NPCX_ESPIIE_FLASHRXIE            4
+#define NPCX_ESPIIE_FLNACSIE             5
+#define NPCX_ESPIIE_PERACCIE             6
+#define NPCX_ESPIIE_DFRDIE               7
+#define NPCX_ESPIIE_VWUPDIE              8
+#define NPCX_ESPIIE_ESPIRSTIE            9
+#define NPCX_ESPIIE_PLTRSTIE             10
+#define NPCX_ESPIIE_AMERRIE              15
+#define NPCX_ESPIIE_AMDONEIE             16
+#define NPCX_ESPIIE_BMTXDONEIE           19
+#define NPCX_ESPIIE_PBMRXIE              20
+#define NPCX_ESPIIE_PMSGRXIE             21
+#define NPCX_ESPIIE_BMBURSTERRIE         22
+#define NPCX_ESPIIE_BMBURSTDONEIE        23
+#define NPCX_ESPIWE_IBRSTWE              0
+#define NPCX_ESPIWE_CFGUPDWE             1
+#define NPCX_ESPIWE_BERRWE               2
+#define NPCX_ESPIWE_OOBRXWE              3
+#define NPCX_ESPIWE_FLASHRXWE            4
+#define NPCX_ESPIWE_FLNACSWE             5
+#define NPCX_ESPIWE_PERACCWE             6
+#define NPCX_ESPIWE_DFRDWE               7
+#define NPCX_ESPIWE_VWUPDWE              8
+#define NPCX_ESPIWE_ESPIRSTWE            9
+#define NPCX_ESPIWE_PBMRXWE              20
+#define NPCX_ESPIWE_PMSGRXWE             21
+#define NPCX_ESPISTS_IBRST               0
+#define NPCX_ESPISTS_CFGUPD              1
+#define NPCX_ESPISTS_BERR                2
+#define NPCX_ESPISTS_OOBRX               3
+#define NPCX_ESPISTS_FLASHRX             4
+#define NPCX_ESPISTS_FLNACS              5
+#define NPCX_ESPISTS_PERACC              6
+#define NPCX_ESPISTS_DFRD                7
+#define NPCX_ESPISTS_VWUPD               8
+#define NPCX_ESPISTS_ESPIRST             9
+#define NPCX_ESPISTS_PLTRST              10
+#define NPCX_ESPISTS_FLAUTORDREQ         14
+#define NPCX_ESPISTS_AMERR               15
+#define NPCX_ESPISTS_AMDONE              16
+#define NPCX_ESPISTS_VWUPDW              17
+#define NPCX_ESPISTS_BMTXDONE            19
+#define NPCX_ESPISTS_PBMRX               20
+#define NPCX_ESPISTS_PMSGRX              21
+#define NPCX_ESPISTS_BMBURSTERR          22
+#define NPCX_ESPISTS_BMBURSTDONE         23
+#define NPCX_ESPISTS_ESPIRST_LVL         24
+#define NPCX_ESPISTS_AUTO_RD_DIS_STS     29
+#define NPCX_VWSWIRQ_IRQ_NUM             FIELD(0, 7)
+#define NPCX_VWSWIRQ_IRQ_LVL             7
+#define NPCX_VWSWIRQ_INDEX               FIELD(8, 7)
+#define NPCX_VWSWIRQ_INDEX_EN            15
+#define NPCX_VWSWIRQ_DIRTY               16
+#define NPCX_VWSWIRQ_ENPLTRST            17
+#define NPCX_VWSWIRQ_ENCDRST             19
+#define NPCX_VWSWIRQ_EDGE_IRQ            28
+#define NPCX_VWEVMS_WIRE                 FIELD(0, 4)
+#define NPCX_VWEVMS_VALID                FIELD(4, 4)
+#define NPCX_VWEVMS_INDEX                FIELD(8, 7)
+#define NPCX_VWEVMS_INDEX_EN             15
+#define NPCX_VWEVMS_IE                   18
+#define NPCX_VWEVMS_ENESPIRST            19
+#define NPCX_VWEVMS_WE                   20
+#define NPCX_VWEVSM_WIRE                 FIELD(0, 4)
+#define NPCX_VWEVSM_VALID                FIELD(4, 4)
+#define NPCX_VWEVSM_INDEX                FIELD(8, 7)
+#define NPCX_VWEVSM_INDEX_EN             15
+#define NPCX_VWEVSM_BIT_VALID(n)         (4+n)
+#define NPCX_VWEVSM_DIRTY                16
+#define NPCX_VWEVSM_HW_WIRE              FIELD(24, 4)
+#define NPCX_VWGPSM_INDEX_EN             15
+#define NPCX_OOBCTL_OOB_FREE             0
+#define NPCX_OOBCTL_OOB_AVAIL            1
+#define NPCX_OOBCTL_RSTBUFHEADS          2
+#define NPCX_OOBCTL_OOBPLSIZE            FIELD(10, 3)
+#define NPCX_FLASHCFG_FLASHBLERSSIZE     FIELD(7, 3)
+#define NPCX_FLASHCFG_FLASHPLSIZE        FIELD(10, 3)
+#define NPCX_FLASHCFG_FLASHREQSIZE       FIELD(13, 3)
+#define NPCX_FLASHCFG_FLCAPA             FIELD(24, 2)
+#define NPCX_FLASHCFG_TRGFLEBLKSIZE      FIELD(16, 8)
+#define NPCX_FLASHCFG_FLREQSUP           FIELD(0, 3)
+#define NPCX_FLASHCTL_FLASH_NP_FREE      0
+#define NPCX_FLASHCTL_FLASH_TX_AVAIL     1
+#define NPCX_FLASHCTL_STRPHDR            2
+#define NPCX_FLASHCTL_DMATHRESH          FIELD(3, 2)
+#define NPCX_FLASHCTL_AMTSIZE            FIELD(5, 8)
+#define NPCX_FLASHCTL_RSTBUFHEADS        13
+#define NPCX_FLASHCTL_CRCEN              14
+#define NPCX_FLASHCTL_CHKSUMSEL          15
+#define NPCX_FLASHCTL_AMTEN              16
+#define NPCX_FLASHCTL_SAF_AUTO_READ      18
+#define NPCX_FLASHCTL_AUTO_RD_DIS_CTL    19
+#define NPCX_FLASHCTL_BLK_FLASH_NP_FREE  20
+#define NPCX_FLASHBASE_FLBASE_ADDR       FIELD(12, 15)
+#define NPCX_FLASH_PRTR_BADDR            FIELD(12, 15)
+#define NPCX_FRGN_WPR                    29
+#define SAF_PROT_LCK                     31
+#define NPCX_FRGN_RPR                    30
+#define NPCX_FLASH_PRTR_HADDR            FIELD(12, 15)
+#define NPCX_FLASH_TAG_OVR_RPR           FIELD(16, 16)
+#define NPCX_FLASH_TAG_OVR_WPR           FIELD(0, 16)
+#define NPCX_FLASH_RPMC_CFG1_CNTR        FIELD(0, 4)
+#define NPCX_FLASH_RPMC_CFG1_OP1         FIELD(4, 8)
+#define NPCX_FLASH_RPMC_CFG1_TRGRPMCSUP  FIELD(26, 6)
+#define NPCX_ONLY_ESPI_REG1_UNLOCK_REG2         0x55
+#define NPCX_ONLY_ESPI_REG1_LOCK_REG2           0
+#define NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG    4
+
+/*
+ * Mobile System Wake-Up Control (MSWC) device registers
+ */
+struct mswc_reg {
+	/* 0x000: MSWC Control Status 1 */
+	volatile uint8_t MSWCTL1;
+	volatile uint8_t reserved1;
+	/* 0x002: MSWC Control Status 2 */
+	volatile uint8_t MSWCTL2;
+	volatile uint8_t reserved2[5];
+	/* 0x008: Host Configuration Base Address Low */
+	volatile uint8_t HCBAL;
+	volatile uint8_t reserved3;
+	/* 0x00A: Host Configuration Base Address High */
+	volatile uint8_t HCBAH;
+	volatile uint8_t reserved4;
+	/* 0X00C: MSWC INTERRUPT ENABLE 2 */
+	volatile uint8_t MSIEN2;
+	volatile uint8_t reserved5;
+	/* 0x00E: MSWC Host Event Status 0 */
+	volatile uint8_t MSHES0;
+	volatile uint8_t reserved6;
+	/* 0x010: MSWC Host Event Interrupt Enable */
+	volatile uint8_t MSHEIE0;
+	volatile uint8_t reserved7;
+	/* 0x012: Host Control */
+	volatile uint8_t HOST_CTL;
+	volatile uint8_t reserved8;
+	/* 0x014: SMI Pulse Length */
+	volatile uint8_t SMIP_LEN;
+	volatile uint8_t reserved9;
+	/* 0x016: SCI Pulse Length */
+	volatile uint8_t SCIP_LEN;
+	volatile uint8_t reserved10[5];
+	/* 0x01C: SRID Core Access */
+	volatile uint8_t SRID_CR;
+	volatile uint8_t reserved11[3];
+	/* 0x020: SID Core Access */
+	volatile uint8_t SID_CR;
+	volatile uint8_t reserved12;
+	/* 0x022: DEVICE_ID Core Access */
+	volatile uint8_t DEVICE_ID_CR;
+	volatile uint8_t reserved13[5];
+	/* 0x028: Chip Revision Core Access */
+	volatile uint8_t CHPREV_CR;
+	volatile uint8_t reserved14[5];
+	/* 0x02E: Virtual Wire Sleep States */
+	volatile uint8_t VW_SLPST1;
+	volatile uint8_t reserved15;
+};
+
+/* MSWC register fields */
+#define NPCX_MSWCTL1_HRSTOB     0
+#define NPCS_MSWCTL1_HWPRON     1
+#define NPCX_MSWCTL1_PLTRST_ACT 2
+#define NPCX_MSWCTL1_VHCFGA     3
+#define NPCX_MSWCTL1_HCFGLK     4
+#define NPCX_MSWCTL1_PWROFFB    6
+#define NPCX_MSWCTL1_A20MB      7
+
+/*
+ * Shared Memory (SHM) device registers
+ */
+struct shm_reg {
+	/* 0x000: Shared Memory Core Status */
+	volatile uint8_t SMC_STS;
+	/* 0x001: Shared Memory Core Control */
+	volatile uint8_t SMC_CTL;
+	/* 0x002: Shared Memory Host Control */
+	volatile uint8_t SHM_CTL;
+	volatile uint8_t reserved1[2];
+	/* 0x005: Indirect Memory Access Window Size */
+	volatile uint8_t IMA_WIN_SIZE;
+	volatile uint8_t reserved2;
+	/* 0x007: Shared Access Windows Size */
+	volatile uint8_t WIN_SIZE;
+	/* 0x008: Shared Access Window 1, Semaphore */
+	volatile uint8_t SHAW1_SEM;
+	/* 0x009: Shared Access Window 2, Semaphore */
+	volatile uint8_t SHAW2_SEM;
+	volatile uint8_t reserved3;
+	/* 0x00B: Indirect Memory Access, Semaphore */
+	volatile uint8_t IMA_SEM;
+	volatile uint8_t reserved4[2];
+	/* 0x00E: Shared Memory Configuration */
+	volatile uint16_t SHCFG;
+	/* 0x010: Shared Access Window 1 Write Protect */
+	volatile uint8_t WIN1_WR_PROT;
+	/* 0x011: Shared Access Window 1 Read Protect */
+	volatile uint8_t WIN1_RD_PROT;
+	/* 0x012: Shared Access Window 2 Write Protect */
+	volatile uint8_t WIN2_WR_PROT;
+	/* 0x013: Shared Access Window 2 Read Protect */
+	volatile uint8_t WIN2_RD_PROT;
+	volatile uint8_t reserved5[2];
+	/* 0x016: Indirect Memory Access Write Protect */
+	volatile uint8_t IMA_WR_PROT;
+	/* 0x017: Indirect Memory Access Read Protect */
+	volatile uint8_t IMA_RD_PROT;
+	volatile uint8_t reserved6[8];
+	/* 0x020: Shared Access Window 1 Base */
+	volatile uint32_t WIN_BASE1;
+	/* 0x024: Shared Access Window 2 Base */
+	volatile uint32_t WIN_BASE2;
+	volatile uint32_t reserved7;
+	/* 0x02C: Indirect Memory Access Base */
+	volatile uint32_t IMA_BASE;
+	volatile uint8_t reserved8[10];
+	/* 0x03A: Reset Configuration */
+	volatile uint8_t RST_CFG;
+	volatile uint8_t reserved9[5];
+	/* 0x040: Debug Port 80 Buffered Data */
+	volatile uint16_t DP80BUF;
+	/* 0x042: Debug Port 80 Status */
+	volatile uint8_t DP80STS;
+	volatile uint8_t reserved10;
+	/* 0x044: Debug Port 80 Control */
+	volatile uint8_t DP80CTL;
+	volatile uint8_t reserved11[3];
+	/* 0x048: Host_Offset in Windows 1, 2 Status */
+	volatile uint8_t HOFS_STS;
+	/* 0x049: Host_Offset in Windows 1, 2 Control */
+	volatile uint8_t HOFS_CTL;
+	/* 0x04A: Core_Offset in Window 2 Address */
+	volatile uint16_t COFS2;
+	/* 0x04C: Core_Offset in Window 1 Address */
+	volatile uint16_t COFS1;
+	volatile uint16_t reserved12;
+};
+
+/* SHM register fields */
+#define NPCX_SMC_STS_HRERR             0
+#define NPCX_SMC_STS_HWERR             1
+#define NPCX_SMC_STS_HSEM1W            4
+#define NPCX_SMC_STS_HSEM2W            5
+#define NPCX_SMC_STS_SHM_ACC           6
+#define NPCX_SMC_CTL_HERR_IE           2
+#define NPCX_SMC_CTL_HSEM1_IE          3
+#define NPCX_SMC_CTL_HSEM2_IE          4
+#define NPCX_SMC_CTL_ACC_IE            5
+#define NPCX_SMC_CTL_PREF_EN           6
+#define NPCX_SMC_CTL_HOSTWAIT          7
+#define NPCX_FLASH_SIZE_STALL_HOST     6
+#define NPCX_FLASH_SIZE_RD_BURST       7
+#define NPCX_WIN_SIZE_RWIN1_SIZE_FIELD FIELD(0, 4)
+#define NPCX_WIN_SIZE_RWIN2_SIZE_FIELD FIELD(4, 4)
+#define NPCX_WIN_PROT_RW1L_RP          0
+#define NPCX_WIN_PROT_RW1L_WP          1
+#define NPCX_WIN_PROT_RW1H_RP          2
+#define NPCX_WIN_PROT_RW1H_WP          3
+#define NPCX_WIN_PROT_RW2L_RP          4
+#define NPCX_WIN_PROT_RW2L_WP          5
+#define NPCX_WIN_PROT_RW2H_RP          6
+#define NPCX_WIN_PROT_RW2H_WP          7
+#define NPCX_PWIN_SIZEI_RPROT          13
+#define NPCX_PWIN_SIZEI_WPROT          14
+#define NPCX_CSEM2                     6
+#define NPCX_CSEM3                     7
+#define NPCX_DP80STS_FWR               5
+#define NPCX_DP80STS_FNE               6
+#define NPCX_DP80STS_FOR               7
+#define NPCX_DP80CTL_DP80EN            0
+#define NPCX_DP80CTL_SYNCEN            1
+#define NPCX_DP80CTL_ADV               2
+#define NPCX_DP80CTL_RAA               3
+#define NPCX_DP80CTL_RFIFO             4
+#define NPCX_DP80CTL_CIEN              5
+#define NPCX_DP80CTL_DP80_HF_CFG       7
+#define NPCX_DP80BUF_OFFS_FIELD        FIELD(8, 3)
+
+/*
+ * Keyboard and Mouse Controller (KBC) device registers
+ */
+struct kbc_reg {
+	/* 0x000h: Host Interface Control */
+	volatile uint8_t HICTRL;
+	volatile uint8_t reserved1;
+	/* 0x002h: Host Interface IRQ Control */
+	volatile uint8_t HIIRQC;
+	volatile uint8_t reserved2;
+	/* 0x004h: Host Interface Keyboard/Mouse Status */
+	volatile uint8_t HIKMST;
+	volatile uint8_t reserved3;
+	/* 0x006h: Host Interface Keyboard Data Out Buffer */
+	volatile uint8_t HIKDO;
+	volatile uint8_t reserved4;
+	/* 0x008h: Host Interface Mouse Data Out Buffer */
+	volatile uint8_t HIMDO;
+	volatile uint8_t reserved5;
+	/* 0x00Ah: Host Interface Keyboard/Mouse Data In Buffer */
+	volatile uint8_t HIKMDI;
+	/* 0x00Bh: Host Interface Keyboard/Mouse Shadow Data In Buffer */
+	volatile uint8_t SHIKMDI;
+};
+
+/* KBC register field */
+#define NPCX_HICTRL_OBFKIE  0
+#define NPCX_HICTRL_OBFMIE  1
+#define NPCX_HICTRL_OBECIE  2
+#define NPCX_HICTRL_IBFCIE  3
+#define NPCX_HICTRL_PMIHIE  4
+#define NPCX_HICTRL_PMIOCIE 5
+#define NPCX_HICTRL_PMICIE  6
+#define NPCX_HICTRL_FW_OBF  7
+#define NPCX_HIKMST_OBF     0
+#define NPCX_HIKMST_IBF     1
+#define NPCX_HIKMST_F0      2
+#define NPCX_HIKMST_A2      3
+#define NPCX_HIKMST_ST0     4
+#define NPCX_HIKMST_ST1     5
+#define NPCX_HIKMST_ST2     6
+#define NPCX_HIKMST_ST3     7
+
+/*
+ * Power Management Channel (PMCH) device registers
+ */
+
+struct pmch_reg {
+	/* 0x000: Host Interface PM Status */
+	volatile uint8_t HIPMST;
+	volatile uint8_t reserved1;
+	/* 0x002: Host Interface PM Data Out Buffer */
+	volatile uint8_t HIPMDO;
+	volatile uint8_t reserved2;
+	/* 0x004: Host Interface PM Data In Buffer */
+	volatile uint8_t HIPMDI;
+	/* 0x005: Host Interface PM Shadow Data In Buffer */
+	volatile uint8_t SHIPMDI;
+	/* 0x006: Host Interface PM Data Out Buffer with SCI */
+	volatile uint8_t HIPMDOC;
+	volatile uint8_t reserved3;
+	/* 0x008: Host Interface PM Data Out Buffer with SMI */
+	volatile uint8_t HIPMDOM;
+	volatile uint8_t reserved4;
+	/* 0x00A: Host Interface PM Data In Buffer with SCI */
+	volatile uint8_t HIPMDIC;
+	volatile uint8_t reserved5;
+	/* 0x00C: Host Interface PM Control */
+	volatile uint8_t HIPMCTL;
+	/* 0x00D: Host Interface PM Control 2 */
+	volatile uint8_t HIPMCTL2;
+	/* 0x00E: Host Interface PM Interrupt Control */
+	volatile uint8_t HIPMIC;
+	volatile uint8_t reserved6;
+	/* 0x010: Host Interface PM Interrupt Enable */
+	volatile uint8_t HIPMIE;
+	volatile uint8_t reserved7;
+};
+
+/* PMCH register field */
+#define NPCX_HIPMIE_SCIE    1
+#define NPCX_HIPMIE_SMIE    2
+#define NPCX_HIPMCTL_IBFIE  0
+#define NPCX_HIPMCTL_OBEIE  1
+#define NPCX_HIPMCTL_SCIPOL 6
+#define NPCX_HIPMST_OBF     0
+#define NPCX_HIPMST_IBF     1
+#define NPCX_HIPMST_F0      2
+#define NPCX_HIPMST_CMD     3
+#define NPCX_HIPMST_ST0     4
+#define NPCX_HIPMST_ST1     5
+#define NPCX_HIPMST_ST2     6
+#define NPCX_HIPMIC_SMIB    1
+#define NPCX_HIPMIC_SCIB    2
+#define NPCX_HIPMIC_SMIPOL  6
+
+/*
+ * Core Access to Host (C2H) device registers
+ */
+struct c2h_reg {
+	/* 0x000: Indirect Host I/O Address */
+	volatile uint16_t IHIOA;
+	/* 0x002: Indirect Host Data */
+	volatile uint8_t IHD;
+	volatile uint8_t reserved1;
+	/* 0x004: Lock Host Access */
+	volatile uint16_t LKSIOHA;
+	/* 0x006: Access Lock Violation */
+	volatile uint16_t SIOLV;
+	/* 0x008: Core-to-Host Modules Access Enable */
+	volatile uint16_t CRSMAE;
+	/* 0x00A: Module Control */
+	volatile uint8_t SIBCTRL;
+	volatile uint8_t reserved3;
+};
+
+/* C2H register fields */
+#define NPCX_LKSIOHA_LKCFG   0
+#define NPCX_LKSIOHA_LKSPHA  2
+#define NPCX_LKSIOHA_LKHIKBD 11
+#define NPCX_CRSMAE_CFGAE    0
+#define NPCX_CRSMAE_HIKBDAE  11
+#define NPCX_SIOLV_SPLV      2
+#define NPCX_SIBCTRL_CSAE    0
+#define NPCX_SIBCTRL_CSRD    1
+#define NPCX_SIBCTRL_CSWR    2
+
+/*
+ * SMBUS (SMB) device registers
+ */
+struct smb_reg {
+	/* 0x000: SMB Serial Data */
+	volatile uint8_t SMBSDA;
+	volatile uint8_t reserved1;
+	/* 0x002: SMB Status */
+	volatile uint8_t SMBST;
+	volatile uint8_t reserved2;
+	/* 0x004: SMB Control Status */
+	volatile uint8_t SMBCST;
+	volatile uint8_t reserved3;
+	/* 0x006: SMB Control 1 */
+	volatile uint8_t SMBCTL1;
+	volatile uint8_t reserved4;
+	/* 0x008: SMB Own Address */
+	volatile uint8_t SMBADDR1;
+	volatile uint8_t reserved5;
+	/* 0x00A: SMB Control 2 */
+	volatile uint8_t SMBCTL2;
+	volatile uint8_t reserved6;
+	/* 0x00C: SMB Own Address */
+	volatile uint8_t SMBADDR2;
+	volatile uint8_t reserved7;
+	/* 0x00E: SMB Control 3 */
+	volatile uint8_t SMBCTL3;
+	/* 0x00F: SMB Bus Timeout */
+	volatile uint8_t SMBT_OUT;
+	union {
+		/* Bank 0 */
+		struct {
+			/* 0x010: SMB Own Address 3 */
+			volatile uint8_t SMBADDR3;
+			/* 0x011: SMB Own Address 7 */
+			volatile uint8_t SMBADDR7;
+			/* 0x012: SMB Own Address 4 */
+			volatile uint8_t SMBADDR4;
+			/* 0x013: SMB Own Address 8 */
+			volatile uint8_t SMBADDR8;
+			/* 0x014: SMB Own Address 5 */
+			volatile uint8_t SMBADDR5;
+			volatile uint8_t reserved8;
+			/* 0x016: SMB Own Address 6 */
+			volatile uint8_t SMBADDR6;
+			volatile uint8_t reserved9;
+			/* 0x018: SMB Control Status 2 */
+			volatile uint8_t SMBCST2;
+			/* 0x019: SMB Control Status 3 */
+			volatile uint8_t SMBCST3;
+			/* 0x01A: SMB Control 4 */
+			volatile uint8_t SMBCTL4;
+			volatile uint8_t reserved10;
+			/* 0x01C: SMB SCL Low Time */
+			volatile uint8_t SMBSCLLT;
+			/* 0x01D: SMB FIFO Control */
+			volatile uint8_t SMBFIF_CTL;
+			/* 0x01E: SMB SCL High Time */
+			volatile uint8_t SMBSCLHT;
+			volatile uint8_t reserved11;
+		};
+		/* Bank 1 */
+		struct {
+			/* 0x010: SMB FIFO Control */
+			volatile uint8_t SMBFIF_CTS;
+			volatile uint8_t reserved12;
+			/* 0x012: SMB Tx-FIFO Control */
+			volatile uint8_t SMBTXF_CTL;
+			volatile uint8_t reserved13;
+			/* 0x014: SMB Bus Timeout */
+			volatile uint8_t SMB_T_OUT;
+			volatile uint8_t reserved14[3];
+			/* 0x018: SMB Control Status 2 (FIFO) */
+			volatile uint8_t SMBCST2_FIFO;
+			/* 0x019: SMB Control Status 3 (FIFO) */
+			volatile uint8_t SMBCST3_FIFO;
+			/* 0x01A: SMB Tx-FIFO Status */
+			volatile uint8_t SMBTXF_STS;
+			volatile uint8_t reserved15;
+			/* 0x01C: SMB Rx-FIFO Status */
+			volatile uint8_t SMBRXF_STS;
+			volatile uint8_t reserved16;
+			/* 0x01E: SMB Rx-FIFO Control */
+			volatile uint8_t SMBRXF_CTL;
+			volatile uint8_t reserved17[1];
+		};
+	};
+};
+
+/* SMB register fields */
+#define NPCX_SMBST_XMIT              0
+#define NPCX_SMBST_MASTER            1
+#define NPCX_SMBST_NMATCH            2
+#define NPCX_SMBST_STASTR            3
+#define NPCX_SMBST_NEGACK            4
+#define NPCX_SMBST_BER               5
+#define NPCX_SMBST_SDAST             6
+#define NPCX_SMBST_SLVSTP            7
+#define NPCX_SMBCST_BUSY             0
+#define NPCX_SMBCST_BB               1
+#define NPCX_SMBCST_MATCH            2
+#define NPCX_SMBCST_GCMATCH          3
+#define NPCX_SMBCST_TSDA             4
+#define NPCX_SMBCST_TGSCL            5
+#define NPCX_SMBCST_MATCHAF          6
+#define NPCX_SMBCST_ARPMATCH         7
+#define NPCX_SMBCST2_MATCHA1F        0
+#define NPCX_SMBCST2_MATCHA2F        1
+#define NPCX_SMBCST2_MATCHA3F        2
+#define NPCX_SMBCST2_MATCHA4F        3
+#define NPCX_SMBCST2_MATCHA5F        4
+#define NPCX_SMBCST2_MATCHA6F        5
+#define NPCX_SMBCST2_MATCHA7F        6
+#define NPCX_SMBCST2_INTSTS          7
+#define NPCX_SMBCST3_MATCHA8F        0
+#define NPCX_SMBCST3_MATCHA9F        1
+#define NPCX_SMBCST3_MATCHA10F       2
+#define NPCX_SMBCTL1_START           0
+#define NPCX_SMBCTL1_STOP            1
+#define NPCX_SMBCTL1_INTEN           2
+#define NPCX_SMBCTL1_ACK             4
+#define NPCX_SMBCTL1_GCMEN           5
+#define NPCX_SMBCTL1_NMINTE          6
+#define NPCX_SMBCTL1_STASTRE         7
+#define NPCX_SMBCTL2_ENABLE          0
+#define NPCX_SMBCTL2_SCLFRQ0_6_FIELD FIELD(1, 7)
+#define NPCX_SMBCTL3_ARPMEN          2
+#define NPCX_SMBCTL3_SCLFRQ7_8_FIELD FIELD(0, 2)
+#define NPCX_SMBCTL3_IDL_START       3
+#define NPCX_SMBCTL3_400K            4
+#define NPCX_SMBCTL3_BNK_SEL         5
+#define NPCX_SMBCTL3_SDA_LVL         6
+#define NPCX_SMBCTL3_SCL_LVL         7
+#define NPCX_SMBCTL4_HLDT_FIELD      FIELD(0, 6)
+#define NPCX_SMBCTL4_LVL_WE          7
+#define NPCX_SMBADDR1_SAEN           7
+#define NPCX_SMBADDR2_SAEN           7
+#define NPCX_SMBADDR3_SAEN           7
+#define NPCX_SMBADDR4_SAEN           7
+#define NPCX_SMBADDR5_SAEN           7
+#define NPCX_SMBADDR6_SAEN           7
+#define NPCX_SMBADDR7_SAEN           7
+#define NPCX_SMBADDR8_SAEN           7
+#define NPCX_SMBSEL_SMB4SEL          4
+#define NPCX_SMBSEL_SMB5SEL          5
+#define NPCX_SMBSEL_SMB6SEL          6
+#define NPCX_SMBFIF_CTS_RXF_TXE      1
+#define NPCX_SMBFIF_CTS_CLR_FIFO     6
+#define NPCX_SMBFIF_CTL_FIFO_EN      4
+#define NPCX_SMBRXF_STS_RX_THST      6
+
+/* RX FIFO threshold */
+#define NPCX_SMBRXF_CTL_RX_THR FIELD(0, 6)
+#define NPCX_SMBRXF_CTL_LAST   7
+
+/*
+ * Internal 32-bit Timer (ITIM32) device registers
+ */
+struct itim32_reg {
+	volatile uint8_t reserved1;
+	/* 0x001: Internal 32-bit Timer Prescaler */
+	volatile uint8_t ITPRE32;
+	volatile uint8_t reserved2[2];
+	/* 0x004: Internal 32-bit Timer Control and Status */
+	volatile uint8_t ITCTS32;
+	volatile uint8_t reserved3[3];
+	/* 0x008: Internal 32-Bit Timer Counter */
+	volatile uint32_t ITCNT32;
+};
+
+/*
+ * Internal 64-bit Timer (ITIM54) device registers
+ */
+struct itim64_reg {
+	volatile uint8_t reserved1;
+	/* 0x001: Internal 64-bit Timer Prescaler */
+	volatile uint8_t ITPRE64;
+	volatile uint8_t reserved2[2];
+	/* 0x004: Internal 64-bit Timer Control and Status */
+	volatile uint8_t ITCTS64;
+	volatile uint8_t reserved3[3];
+	/* 0x008: Internal 32-Bit Timer Counter */
+	volatile uint32_t ITCNT64L;
+	/* 0x00C: Internal 32-Bit Timer Counter */
+	volatile uint32_t ITCNT64H;
+};
+
+/* ITIM register fields */
+#define NPCX_ITCTSXX_TO_STS 0
+#define NPCX_ITCTSXX_TO_IE  2
+#define NPCX_ITCTSXX_TO_WUE 3
+#define NPCX_ITCTSXX_CKSEL  4
+#define NPCX_ITCTSXX_ITEN   7
+
+/*
+ * Tachometer (TACH) Sensor device registers
+ */
+struct tach_reg {
+	/* 0x000: Timer/Counter 1 */
+	volatile uint16_t TCNT1;
+	/* 0x002: Reload/Capture A */
+	volatile uint16_t TCRA;
+	/* 0x004: Reload/Capture B */
+	volatile uint16_t TCRB;
+	/* 0x006: Timer/Counter 2 */
+	volatile uint16_t TCNT2;
+	/* 0x008: Clock Prescaler */
+	volatile uint8_t TPRSC;
+	volatile uint8_t reserved1;
+	/* 0x00A: Clock Unit Control */
+	volatile uint8_t TCKC;
+	volatile uint8_t reserved2;
+	/* 0x00C: Timer Mode Control */
+	volatile uint8_t TMCTRL;
+	volatile uint8_t reserved3;
+	/* 0x00E: Timer Event Control */
+	volatile uint8_t TECTRL;
+	volatile uint8_t reserved4;
+	/* 0x010: Timer Event Clear */
+	volatile uint8_t TECLR;
+	volatile uint8_t reserved5;
+	/* 0x012: Timer Interrupt Enable */
+	volatile uint8_t TIEN;
+	volatile uint8_t reserved6;
+	/* 0x014: Compare A */
+	volatile uint16_t TCPA;
+	/* 0x016: Compare B */
+	volatile uint16_t TCPB;
+	/* 0x018: Compare Configuration */
+	volatile uint8_t TCPCFG;
+	volatile uint8_t reserved7;
+	/* 0x01A: Timer Wake-Up Enable */
+	volatile uint8_t TWUEN;
+	volatile uint8_t reserved8;
+	/* 0x01C: Timer Configuration */
+	volatile uint8_t TCFG;
+	volatile uint8_t reserved9;
+};
+
+/* TACH register fields */
+#define NPCX_TCKC_LOW_PWR       7
+#define NPCX_TCKC_PLS_ACC_CLK   6
+#define NPCX_TCKC_C1CSEL_FIELD  FIELD(0, 3)
+#define NPCX_TCKC_C2CSEL_FIELD  FIELD(3, 3)
+#define NPCX_TMCTRL_MDSEL_FIELD FIELD(0, 3)
+#define NPCX_TMCTRL_TAEN        5
+#define NPCX_TMCTRL_TBEN        6
+#define NPCX_TMCTRL_TAEDG       3
+#define NPCX_TMCTRL_TBEDG       4
+#define NPCX_TCFG_TADBEN        6
+#define NPCX_TCFG_TBDBEN        7
+#define NPCX_TECTRL_TAPND       0
+#define NPCX_TECTRL_TBPND       1
+#define NPCX_TECTRL_TCPND       2
+#define NPCX_TECTRL_TDPND       3
+#define NPCX_TECLR_TACLR        0
+#define NPCX_TECLR_TBCLR        1
+#define NPCX_TECLR_TCCLR        2
+#define NPCX_TECLR_TDCLR        3
+#define NPCX_TIEN_TAIEN         0
+#define NPCX_TIEN_TBIEN         1
+#define NPCX_TIEN_TCIEN         2
+#define NPCX_TIEN_TDIEN         3
+#define NPCX_TWUEN_TAWEN        0
+#define NPCX_TWUEN_TBWEN        1
+#define NPCX_TWUEN_TCWEN        2
+#define NPCX_TWUEN_TDWEN        3
+
+/* Debug Interface registers */
+struct dbg_reg {
+	/* 0x000: Debug Control */
+	volatile uint8_t DBGCTRL;
+	volatile uint8_t reserved1;
+	/* 0x002: Debug Freeze Enable 1 */
+	volatile uint8_t DBGFRZEN1;
+	/* 0x003: Debug Freeze Enable 2 */
+	volatile uint8_t DBGFRZEN2;
+	/* 0x004: Debug Freeze Enable 3 */
+	volatile uint8_t DBGFRZEN3;
+	/* 0x005: Debug Freeze Enable 4 */
+	volatile uint8_t DBGFRZEN4;
+};
+/* Debug Interface registers fields */
+#define NPCX_DBGFRZEN3_GLBL_FRZ_DIS 7
+
+/* PS/2 Interface registers */
+struct ps2_reg {
+	/* 0x000: PS/2 Data */
+	volatile uint8_t PSDAT;
+	volatile uint8_t reserved1;
+	/* 0x002: PS/2 Status */
+	volatile uint8_t PSTAT;
+	volatile uint8_t reserved2;
+	/* 0x004: PS/2 Control */
+	volatile uint8_t PSCON;
+	volatile uint8_t reserved3;
+	/* 0x006: PS/2 Output Signal */
+	volatile uint8_t PSOSIG;
+	volatile uint8_t reserved4;
+	/* 0x008: PS/2 Input Signal */
+	volatile uint8_t PSISIG;
+	volatile uint8_t reserved5;
+	/* 0x00A: PS/2 Interrupt Enable */
+	volatile uint8_t PSIEN;
+	volatile uint8_t reserved6;
+};
+
+/* PS/2 Interface registers fields */
+#define NPCX_PSTAT_SOT   0
+#define NPCX_PSTAT_EOT   1
+#define NPCX_PSTAT_PERR  2
+#define NPCX_PSTAT_ACH   FIELD(3, 3)
+#define NPCX_PSTAT_RFERR 6
+
+#define NPCX_PSCON_EN    0
+#define NPCX_PSCON_XMT   1
+#define NPCX_PSCON_HDRV  FIELD(2, 2)
+#define NPCX_PSCON_IDB   FIELD(4, 3)
+#define NPCX_PSCON_WPUED 7
+
+#define NPCX_PSOSIG_WDAT0   0
+#define NPCX_PSOSIG_WDAT1   1
+#define NPCX_PSOSIG_WDAT2   2
+#define NPCX_PSOSIG_CLK0    3
+#define NPCX_PSOSIG_CLK1    4
+#define NPCX_PSOSIG_CLK2    5
+#define NPCX_PSOSIG_WDAT3   6
+#define NPCX_PSOSIG_CLK3    7
+#define NPCX_PSOSIG_CLK(n)  (((n) < 3) ? ((n) + 3) : 7)
+#define NPCX_PSOSIG_WDAT(n) (((n) < 3) ? ((n) + 0) : 6)
+#define NPCX_PSOSIG_CLK_MASK_ALL                                                                   \
+	(BIT(NPCX_PSOSIG_CLK0) | BIT(NPCX_PSOSIG_CLK1) | BIT(NPCX_PSOSIG_CLK2) |                   \
+	 BIT(NPCX_PSOSIG_CLK3))
+
+#define NPCX_PSIEN_SOTIE       0
+#define NPCX_PSIEN_EOTIE       1
+#define NPCX_PSIEN_PS2_WUE     4
+#define NPCX_PSIEN_PS2_CLK_SEL 7
+
+/* Flash Interface Unit (FIU) device registers */
+struct fiu_reg {
+	volatile uint8_t reserved1;
+	/* 0x001: Burst Configuration */
+	volatile uint8_t BURST_CFG;
+	/* 0x002: FIU Response Configuration */
+	volatile uint8_t RESP_CFG;
+	volatile uint8_t reserved2[17];
+	/* 0x014: SPI Flash Configuration */
+	volatile uint8_t SPI_FL_CFG;
+	volatile uint8_t reserved3;
+	/* 0x016: UMA Code Byte */
+	volatile uint8_t UMA_CODE;
+	/* 0x017: UMA Address Byte 0 */
+	volatile uint8_t UMA_AB0;
+	/* 0x018: UMA Address Byte 1 */
+	volatile uint8_t UMA_AB1;
+	/* 0x019: UMA Address Byte 2 */
+	volatile uint8_t UMA_AB2;
+	/* 0x01A: UMA Data Byte 0 */
+	volatile uint8_t UMA_DB0;
+	/* 0x01B: UMA Data Byte 1 */
+	volatile uint8_t UMA_DB1;
+	/* 0x01C: UMA Data Byte 2 */
+	volatile uint8_t UMA_DB2;
+	/* 0x01D: UMA Data Byte 3 */
+	volatile uint8_t UMA_DB3;
+	/* 0x01E: UMA Control and Status */
+	volatile uint8_t UMA_CTS;
+	/* 0x01F: UMA Extended Control and Status */
+	volatile uint8_t UMA_ECTS;
+	/* 0x020: UMA Data Bytes 0-3 */
+	volatile uint32_t UMA_DB0_3;
+	volatile uint8_t reserved4[2];
+	/* 0x026: CRC Control Register */
+	volatile uint8_t CRCCON;
+	/* 0x027: CRC Entry Register */
+	volatile uint8_t CRCENT;
+	/* 0x028: CRC Initialization and Result Register */
+	volatile uint32_t CRCRSLT;
+	volatile uint8_t reserved5[4];
+	/* 0x030: FIU Read Command */
+	volatile uint8_t FIU_RD_CMD;
+	volatile uint8_t reserved6;
+	/* 0x032: FIU Dummy Cycles */
+	volatile uint8_t FIU_DMM_CYC;
+	/* 0x033: FIU Extended Configuration */
+	volatile uint8_t FIU_EXT_CFG;
+#if defined(CONFIG_SOC_SERIES_NPCX9)
+	/* 0x034: UMA address byte 0-3 */
+	volatile uint32_t UMA_AB0_3;
+	/* 0x038-0x3C */
+	volatile uint8_t reserved8[5];
+	/* 0x03D: SPI Device */
+	volatile uint8_t SPI1_DEV;
+	/* 0x03E-0x3F */
+	volatile uint8_t reserved9[2];
+#elif defined(CONFIG_SOC_SERIES_NPCX4)
+	/* 0x034: UMA address byte 0-3 */
+	volatile uint32_t UMA_AB0_3;
+	/* 0x038-0x3B */
+	volatile uint8_t reserved8[4];
+	/* 0x03C: SPI Device */
+	volatile uint8_t SPI_DEV;
+	/* 0x03D */
+	volatile uint8_t reserved9;
+	/* 0x03E */
+	volatile uint8_t SPI_DEV_SIZE;
+	/* 0x03F */
+	volatile uint8_t reserved10;
+#endif
+};
+
+/* FIU register fields */
+#define NPCX_BURST_CFG_SPI_DEV_SEL     FIELD(4, 2)
+#define NPCX_RESP_CFG_IAD_EN           0
+#define NPCX_RESP_CFG_DEV_SIZE_EX      2
+#define NPCX_RESP_CFG_QUAD_EN          3
+#define NPCX_SPI_FL_CFG_RD_MODE        FIELD(6, 2)
+#define NPCX_UMA_CTS_A_SIZE            3
+#define NPCX_UMA_CTS_C_SIZE            4
+#define NPCX_UMA_CTS_RD_WR             5
+#define NPCX_UMA_CTS_DEV_NUM           6
+#define NPCX_UMA_CTS_EXEC_DONE         7
+#define NPCX_UMA_ECTS_SW_CS0           0
+#define NPCX_UMA_ECTS_SW_CS1           1
+#define NPCX_UMA_ECTS_SEC_CS           2
+#define NPCX_UMA_ECTS_UMA_LOCK         3
+#define NPCX_UMA_ECTS_UMA_ADDR_SIZE    FIELD(4, 3)
+#define NPCX_SPI1_DEV_FOUR_BADDR_CS10  6
+#define NPCX_SPI1_DEV_FOUR_BADDR_CS11  7
+#define NPCX_SPI1_DEV_SPI1_LO_DEV_SIZE FIELD(0, 4)
+#define NPCX_FIU_EXT_CFG_SET_DMM_EN    2
+#define NPCX_FIU_EXT_CFG_SET_CMD_EN    1
+#define NPCX_SPI_DEV_NADDRB            FIELD(5, 3)
+
+#define NPCX_MSR_IE_CFG_UMA_BLOCK 3
+
+/* UMA fields selections */
+#define UMA_FLD_ADDR   BIT(NPCX_UMA_CTS_A_SIZE)  /* 3-bytes ADR field */
+#define UMA_FLD_NO_CMD BIT(NPCX_UMA_CTS_C_SIZE)  /* No 1-Byte CMD field */
+#define UMA_FLD_WRITE  BIT(NPCX_UMA_CTS_RD_WR)   /* Write transaction */
+#define UMA_FLD_SHD_SL BIT(NPCX_UMA_CTS_DEV_NUM) /* Shared flash selected */
+#define UMA_FLD_EXEC   BIT(NPCX_UMA_CTS_EXEC_DONE)
+
+#define UMA_FIELD_DATA_1 0x01
+#define UMA_FIELD_DATA_2 0x02
+#define UMA_FIELD_DATA_3 0x03
+#define UMA_FIELD_DATA_4 0x04
+
+/* UMA code for transaction */
+#define UMA_CODE_CMD_ONLY       (UMA_FLD_EXEC | UMA_FLD_SHD_SL)
+#define UMA_CODE_CMD_ADR        (UMA_FLD_EXEC | UMA_FLD_ADDR | UMA_FLD_SHD_SL)
+#define UMA_CODE_CMD_RD_BYTE(n) (UMA_FLD_EXEC | UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
+#define UMA_CODE_RD_BYTE(n)                                                                        \
+	(UMA_FLD_EXEC | UMA_FLD_NO_CMD | UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
+#define UMA_CODE_CMD_WR_ONLY    (UMA_FLD_EXEC | UMA_FLD_WRITE | UMA_FLD_SHD_SL)
+#define UMA_CODE_CMD_WR_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_WRITE | UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
+#define UMA_CODE_CMD_WR_ADR     (UMA_FLD_EXEC | UMA_FLD_WRITE | UMA_FLD_ADDR | UMA_FLD_SHD_SL)
+
+#define UMA_CODE_CMD_ADR_WR_BYTE(n)                                                                \
+	(UMA_FLD_EXEC | UMA_FLD_WRITE | UMA_FLD_ADDR | UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
+
+/* Platform Environment Control Interface (PECI) device registers */
+struct peci_reg {
+	/* 0x000: PECI Control Status */
+	volatile uint8_t PECI_CTL_STS;
+	/* 0x001: PECI Read Length */
+	volatile uint8_t PECI_RD_LENGTH;
+	/* 0x002: PECI Address */
+	volatile uint8_t PECI_ADDR;
+	/* 0x003: PECI Command */
+	volatile uint8_t PECI_CMD;
+	/* 0x004: PECI Control 2 */
+	volatile uint8_t PECI_CTL2;
+	/* 0x005: PECI Index */
+	volatile uint8_t PECI_INDEX;
+	/* 0x006: PECI Index Data */
+	volatile uint8_t PECI_IDATA;
+	/* 0x007: PECI Write Length */
+	volatile uint8_t PECI_WR_LENGTH;
+	volatile uint8_t reserved1[3];
+	/* 0x00B: PECI Write FCS */
+	volatile uint8_t PECI_WR_FCS;
+	/* 0x00C: PECI Read FCS */
+	volatile uint8_t PECI_RD_FCS;
+	/* 0x00D: PECI Assured Write FCS */
+	volatile uint8_t PECI_AW_FCS;
+	volatile uint8_t reserved2;
+	/* 0x00F: PECI Transfer Rate */
+	volatile uint8_t PECI_RATE;
+	/* 0x010 - 0x04F: PECI Data In/Out */
+	union {
+		volatile uint8_t PECI_DATA_IN[64];
+		volatile uint8_t PECI_DATA_OUT[64];
+	};
+};
+
+/* PECI register fields */
+#define NPCX_PECI_CTL_STS_START_BUSY     0
+#define NPCX_PECI_CTL_STS_DONE           1
+#define NPCX_PECI_CTL_STS_CRC_ERR        3
+#define NPCX_PECI_CTL_STS_ABRT_ERR       4
+#define NPCX_PECI_CTL_STS_AWFCS_EB       5
+#define NPCX_PECI_CTL_STS_DONE_EN        6
+#define NPCX_PECI_RATE_MAX_BIT_RATE      FIELD(0, 5)
+#define NPCX_PECI_RATE_MAX_BIT_RATE_MASK 0x1F
+/* The minimal valid value of NPCX_PECI_RATE_MAX_BIT_RATE field */
+#define PECI_MAX_BIT_RATE_VALID_MIN      0x05
+#define PECI_HIGH_SPEED_MIN_VAL          0x07
+
+#define NPCX_PECI_RATE_EHSP 6
+
+/* KBS (Keyboard Scan) device registers */
+struct kbs_reg {
+	volatile uint8_t reserved1[4];
+	/* 0x004: Keyboard Scan In */
+	volatile uint8_t KBSIN;
+	/* 0x005: Keyboard Scan In Pull-Up Enable */
+	volatile uint8_t KBSINPU;
+	/* 0x006: Keyboard Scan Out 0 */
+	volatile uint16_t KBSOUT0;
+	/* 0x008: Keyboard Scan Out 1 */
+	volatile uint16_t KBSOUT1;
+	/* 0x00A: Keyboard Scan Buffer Index */
+	volatile uint8_t KBS_BUF_INDX;
+	/* 0x00B: Keyboard Scan Buffer Data */
+	volatile uint8_t KBS_BUF_DATA;
+	/* 0x00C: Keyboard Scan Event */
+	volatile uint8_t KBSEVT;
+	/* 0x00D: Keyboard Scan Control */
+	volatile uint8_t KBSCTL;
+	/* 0x00E: Keyboard Scan Configuration Index */
+	volatile uint8_t KBS_CFG_INDX;
+	/* 0x00F: Keyboard Scan Configuration Data */
+	volatile uint8_t KBS_CFG_DATA;
+};
+
+/* KBS register fields */
+#define NPCX_KBSBUFINDX          0
+#define NPCX_KBSEVT_KBSDONE      0
+#define NPCX_KBSEVT_KBSERR       1
+#define NPCX_KBSCTL_START        0
+#define NPCX_KBSCTL_KBSMODE      1
+#define NPCX_KBSCTL_KBSIEN       2
+#define NPCX_KBSCTL_KBSINC       3
+#define NPCX_KBSCTL_KBHDRV_FIELD FIELD(6, 2)
+#define NPCX_KBSCFGINDX          0
+/* Index of 'Automatic Scan' configuration register */
+#define KBS_CFG_INDX_DLY1        0 /* Keyboard Scan Delay T1 Byte */
+#define KBS_CFG_INDX_DLY2        1 /* Keyboard Scan Delay T2 Byte */
+#define KBS_CFG_INDX_RTYTO       2 /* Keyboard Scan Retry Timeout */
+#define KBS_CFG_INDX_CNUM        3 /* Keyboard Scan Columns Number */
+#define KBS_CFG_INDX_CDIV        4 /* Keyboard Scan Clock Divisor */
+
+/* SHI (Serial Host Interface) registers */
+struct shi_reg {
+	volatile uint8_t reserved1;
+	/* 0x001: SHI Configuration 1 */
+	volatile uint8_t SHICFG1;
+	/* 0x002: SHI Configuration 2 */
+	volatile uint8_t SHICFG2;
+	volatile uint8_t reserved2[2];
+	/* 0x005: Event Enable */
+	volatile uint8_t EVENABLE;
+	/* 0x006: Event Status */
+	volatile uint8_t EVSTAT;
+	/* 0x007: SHI Capabilities */
+	volatile uint8_t CAPABILITY;
+	/* 0x008: Status */
+	volatile uint8_t STATUS;
+	volatile uint8_t reserved3;
+	/* 0x00A: Input Buffer Status */
+	volatile uint8_t IBUFSTAT;
+	/* 0x00B: Output Buffer Status */
+	volatile uint8_t OBUFSTAT;
+	/* 0x00C: SHI Configuration 3 */
+	volatile uint8_t SHICFG3;
+	/* 0x00D: SHI Configuration 4 */
+	volatile uint8_t SHICFG4;
+	/* 0x00E: SHI Configuration 5 */
+	volatile uint8_t SHICFG5;
+	/* 0x00F: Event Status 2 */
+	volatile uint8_t EVSTAT2;
+	/* 0x010: Event Enable 2 */
+	volatile uint8_t EVENABLE2;
+	/* 0x011: SHI Configuration 6 - only in chips which support enhanced buffer mode */
+	volatile uint8_t SHICFG6;
+	/* 0x012: Single Byte Output Buffer - only in chips which support enhanced buffer mode */
+	volatile uint8_t SBOBUF;
+	volatile uint8_t reserved4[13];
+	/* 0x20~0x9F: Output Buffer */
+	volatile uint8_t OBUF[128];
+	/* 0xA0~0x11F: Input Buffer */
+	volatile uint8_t IBUF[128];
+};
+
+/* SHI register fields */
+#define NPCX_SHICFG1_EN          0
+#define NPCX_SHICFG1_MODE        1
+#define NPCX_SHICFG1_WEN         2
+#define NPCX_SHICFG1_AUTIBF      3
+#define NPCX_SHICFG1_AUTOBE      4
+#define NPCX_SHICFG1_DAS         5
+#define NPCX_SHICFG1_CPOL        6
+#define NPCX_SHICFG1_IWRAP       7
+#define NPCX_SHICFG2_SIMUL       0
+#define NPCX_SHICFG2_BUSY        1
+#define NPCX_SHICFG2_ONESHOT     2
+#define NPCX_SHICFG2_SLWU        3
+#define NPCX_SHICFG2_REEN        4
+#define NPCX_SHICFG2_RESTART     5
+#define NPCX_SHICFG2_REEVEN      6
+#define NPCX_EVENABLE_OBEEN      0
+#define NPCX_EVENABLE_OBHEEN     1
+#define NPCX_EVENABLE_IBFEN      2
+#define NPCX_EVENABLE_IBHFEN     3
+#define NPCX_EVENABLE_EOREN      4
+#define NPCX_EVENABLE_EOWEN      5
+#define NPCX_EVENABLE_STSREN     6
+#define NPCX_EVENABLE_IBOREN     7
+#define NPCX_EVSTAT_OBE          0
+#define NPCX_EVSTAT_OBHE         1
+#define NPCX_EVSTAT_IBF          2
+#define NPCX_EVSTAT_IBHF         3
+#define NPCX_EVSTAT_EOR          4
+#define NPCX_EVSTAT_EOW          5
+#define NPCX_EVSTAT_STSR         6
+#define NPCX_EVSTAT_IBOR         7
+#define NPCX_STATUS_OBES         6
+#define NPCX_STATUS_IBFS         7
+#define NPCX_SHICFG3_OBUFLVLDIS  7
+#define NPCX_SHICFG4_IBUFLVLDIS  7
+#define NPCX_SHICFG5_IBUFLVL2    FIELD(0, 6)
+#define NPCX_SHICFG5_IBUFLVL2DIS 7
+#define NPCX_EVSTAT2_IBHF2       0
+#define NPCX_EVSTAT2_CSNRE       1
+#define NPCX_EVSTAT2_CSNFE       2
+#define NPCX_EVENABLE2_IBHF2EN   0
+#define NPCX_EVENABLE2_CSNREEN   1
+#define NPCX_EVENABLE2_CSNFEEN   2
+#define NPCX_SHICFG6_EBUFMD      0
+#define NPCX_SHICFG6_OBUF_SL     1
+
+#define IBF_IBHF_EN_MASK (BIT(NPCX_EVENABLE_IBFEN) | BIT(NPCX_EVENABLE_IBHFEN))
+
+/* SPIP (SPI Peripheral Interface) registers */
+struct spip_reg {
+	/* 0x000: SPIP Data In/Out */
+	volatile uint16_t SPIP_DATA;
+	/* 0x002: SPIP Control 1 */
+	volatile uint16_t SPIP_CTL1;
+	/* 0x004: SPIP Status */
+	volatile uint8_t SPIP_STAT;
+	volatile uint8_t reserved1;
+};
+
+#define NPCX_SPIP_CTL1_SPIEN 0
+#define NPCX_SPIP_CTL1_MOD   2
+#define NPCX_SPIP_CTL1_EIR   5
+#define NPCX_SPIP_CTL1_EIW   6
+#define NPCX_SPIP_CTL1_SCM   7
+#define NPCX_SPIP_CTL1_SCIDL 8
+#define NPCX_SPIP_CTL1_SCDV  FIELD(9, 7)
+#define NPCX_SPIP_STAT_BSY   0
+#define NPCX_SPIP_STAT_RBF   1
+
+/* Software-triggered Pheripheral Reset Controller Register */
+struct swrst_reg {
+	/* 0x000: Software Reset Trigger */
+	volatile uint16_t SWRST_TRG;
+	volatile uint8_t reserved1[2];
+	volatile uint32_t SWRST_CTL[4];
+};
+
+/* Improved Inter Integrated Circuit  (I3C) device registers */
+struct i3c_reg {
+	/* 0x000: Controller Configuration */
+	volatile uint32_t MCONFIG;
+	/* 0x004: Target Configuration */
+	volatile uint32_t CONFIG;
+	/* 0x008: Target Status */
+	volatile uint32_t STATUS;
+	/* 0x00C: Target Control  */
+	volatile uint32_t CTRL;
+	/* 0x010: Target Interrupt Enable Set  */
+	volatile uint32_t INTSET;
+	/* 0x014: Target Interrupt Enable Clear */
+	volatile uint32_t INTCLR;
+	/* 0x018: Target Interrupt Masked */
+	volatile uint32_t INTMASKED;
+	/* 0x01C: Target Error and Warning */
+	volatile uint32_t ERRWARN;
+	/* 0x020: Target DMA Control */
+	volatile uint32_t DMACTRL;
+	/* 0x024-0x02B: reserved */
+	volatile uint32_t reserved0[2];
+	/* 0x02C: Target Data Control */
+	volatile uint32_t DATACTRL;
+	/* 0x030: Target Write Byte Data */
+	volatile uint32_t WDATAB;
+	/* 0x034: Target Write Byte Data as End */
+	volatile uint32_t WDATABE;
+	/* 0x038: Target Write Half-Word Data */
+	volatile uint32_t WDATAH;
+	/* 0x03C: Target Write Half-Word Data as End */
+	volatile uint32_t WDATAHE;
+	/* 0x040: Target Read Byte Data */
+	volatile uint32_t RDATAB;
+	/* 0x044: reserved */
+	volatile uint32_t reserved1;
+	/* 0x048: Target Read Half-Word Data */
+	volatile uint32_t RDATAH;
+	/* 0x04C-0x05B: reserved */
+	volatile uint32_t reserved2[4];
+	/* 0x05C: Target Capabilities 2 */
+	volatile uint32_t CCAPABILITIES2;
+	/* 0x060: Target Capabilities */
+	volatile uint32_t CCAPABILITIES;
+	/* 0x064: Target Dynamic Address */
+	volatile uint32_t DYNADDR;
+	/* 0x068: Target Maximum Limits */
+	volatile uint32_t MAXLIMITS;
+	/* 0x06C: Target Part Number */
+	volatile uint32_t PARTNO;
+	/* 0x070: Target ID Extension */
+	volatile uint32_t IDEXT;
+	/* 0x074: Target Vendor ID */
+	volatile uint32_t VENDORID;
+	/* 0x078: Target Timing Control Clock */
+	volatile uint32_t TCCLOCK;
+	/* 0x07C: Target Matching Address Index */
+	volatile uint32_t MSGLAST;
+	/* 0x080: reserved */
+	volatile uint32_t reserved3;
+	/* 0x084: Controller Control  */
+	volatile uint32_t MCTRL;
+	/* 0x088: Controller Status */
+	volatile uint32_t MSTATUS;
+	/* 0x08C: IBI Registry and Rules */
+	volatile uint32_t IBIRULES;
+	/* 0x090: Controller Interrupt Enable Set  */
+	volatile uint32_t MINTSET;
+	/* 0x094: Controller Interrupt Enable Clear */
+	volatile uint32_t MINTCLR;
+	/* 0x098: Controller Interrupt Masked */
+	volatile uint32_t MINTMASKED;
+	/* 0x09C: Controller Error and Warning */
+	volatile uint32_t MERRWARN;
+	/* 0x0A0: Controller DMA Control */
+	volatile uint32_t MDMACTRL;
+	/* 0x0A0-0x0AB: reserved */
+	volatile uint32_t reserved4[2];
+	/* 0x0AC: Controller Data Control */
+	volatile uint32_t MDATACTRL;
+	/* 0x0B0: Controller Write Byte Data */
+	volatile uint32_t MWDATAB;
+	/* 0x0B4: Controller Write Byte Data as End */
+	volatile uint32_t MWDATABE;
+	/* 0x0B8: Controller Write Half-Word Data */
+	volatile uint32_t MWDATAH;
+	/* 0x0BC: Controller Write Half-Word Data as End */
+	volatile uint32_t MWDATAHE;
+	/* 0x0C0: Controller Read Byte Data */
+	volatile uint32_t MRDATAB;
+	/* 0x0C4: reserved */
+	volatile uint32_t reserved5;
+	/* 0x0C8: Controller Read Half-Word Data */
+	volatile uint32_t MRDATAH;
+	/* 0x0CC-0x0D7: reserved */
+	volatile uint32_t reserved6[3];
+	/* 0x0D8: Start or Continue DDR Message */
+	volatile uint32_t MWMSG_DDR;
+	/* 0x0DC: Read DDR Message Data */
+	volatile uint32_t MRMSG_DDR;
+	/* 0x0E0: reserved */
+	volatile uint32_t reserved7;
+	/* 0x0E4: Controller Dynamic Address */
+	volatile uint32_t MDYNADDR;
+	/* 0x0E8-0x0FF reserved */
+	volatile uint32_t reserved8[6];
+	/* 0x100: Target Reset Recovery Time */
+	volatile uint32_t RSTACTTIME;
+	/* 0x104: reserved */
+	volatile uint32_t reserved9;
+	/* 0x108: Target HDR Command Byte */
+	volatile uint32_t HDRCMD;
+	/* 0x10C-0x113: reserved */
+	volatile uint32_t reserved10[2];
+	/* 0x114: Target Group Definition */
+	volatile uint32_t GROUPDEF;
+	/* 0x118: reserved */
+	volatile uint32_t reserved11;
+	/* 0x11C: Target Map Control 0 */
+	volatile uint32_t MAPCTRL0;
+	/* 0x120: Target Map Control 1 */
+	volatile uint32_t MAPCTRL1;
+	/* 0x124: Target Map Control 2 */
+	volatile uint32_t MAPCTRL2;
+	/* 0x128: Target Map Control 3 */
+	volatile uint32_t MAPCTRL3;
+	/* 0x12C: Target Map Control 4 */
+	volatile uint32_t MAPCTRL4;
+	/* 0x130: Target Map Control 5 */
+	volatile uint32_t MAPCTRL5;
+	/* 0x134: Target Map Control 6 */
+	volatile uint32_t MAPCTRL6;
+	/* 0x138: Target Map Control 7 */
+	volatile uint32_t MAPCTRL7;
+	/* 0x13C: Target Map Control 8 */
+	volatile uint32_t MAPCTRL8;
+	/* 0x140: Target Extended IBI Data 1 */
+	volatile uint32_t IBIEXT1;
+	/* 0x144: Target Extended IBI Data 2 */
+	volatile uint32_t IBIEXT2;
+};
+
+/* I3C controller register fields */
+#define NPCX_I3C_MCONFIG_CTRENA      FIELD(0, 2)
+#define NPCX_I3C_MCONFIG_DISTO       3
+#define NPCX_I3C_MCONFIG_HKEEP       FIELD(4, 2) /* Must be '11' */
+#define NPCX_I3C_MCONFIG_ODSTOP      6
+#define NPCX_I3C_MCONFIG_PPBAUD      FIELD(8, 4)
+#define NPCX_I3C_MCONFIG_PPLOW       FIELD(12, 4)
+#define NPCX_I3C_MCONFIG_ODBAUD      FIELD(16, 8)
+#define NPCX_I3C_MCONFIG_ODHPP       24
+#define NPCX_I3C_MCONFIG_SKEW        FIELD(25, 3)
+#define NPCX_I3C_MCONFIG_I2CBAUD     FIELD(28, 4)
+#define NPCX_I3C_MCTRL_REQUEST       FIELD(0, 3)
+#define NPCX_I3C_MCTRL_TYPE          FIELD(4, 2)
+#define NPCX_I3C_MCTRL_IBIRESP       FIELD(6, 2)
+#define NPCX_I3C_MCTRL_DIR           8
+#define NPCX_I3C_MCTRL_ADDR          FIELD(9, 7)
+#define NPCX_I3C_MCTRL_RDTERM        FIELD(16, 8)
+#define NPCX_I3C_MSTATUS_STATE       FIELD(0, 3)
+#define NPCX_I3C_MSTATUS_BETWEEN     4
+#define NPCX_I3C_MSTATUS_NACKED      5
+#define NPCX_I3C_MSTATUS_IBITYPE     FIELD(6, 2)
+#define NPCX_I3C_MSTATUS_TGTSTART    8
+#define NPCX_I3C_MSTATUS_MCTRLDONE   9
+#define NPCX_I3C_MSTATUS_COMPLETE    10
+#define NPCX_I3C_MSTATUS_RXPEND      11
+#define NPCX_I3C_MSTATUS_TXNOTFULL   12
+#define NPCX_I3C_MSTATUS_IBIWON      13
+#define NPCX_I3C_MSTATUS_ERRWARN     15
+#define NPCX_I3C_MSTATUS_NOWCNTLR    19
+#define NPCX_I3C_MSTATUS_IBIADDR     FIELD(24, 7)
+#define NPCX_I3C_IBIRULES_MSB0       30
+#define NPCX_I3C_IBIRULES_NOBYTE     31
+#define NPCX_I3C_MINTSET_TGTSTART    8
+#define NPCX_I3C_MINTSET_MCTRLDONE   9
+#define NPCX_I3C_MINTSET_COMPLETE    10
+#define NPCX_I3C_MINTSET_RXPEND      11
+#define NPCX_I3C_MINTSET_TXNOTFULL   12
+#define NPCX_I3C_MINTSET_IBIWON      13
+#define NPCX_I3C_MINTSET_ERRWARN     15
+#define NPCX_I3C_MINTSET_NOWCNTLR    19
+#define NPCX_I3C_MINTCLR_TGTSTART    8
+#define NPCX_I3C_MINTCLR_MCTRLDONE   9
+#define NPCX_I3C_MINTCLR_COMPLETE    10
+#define NPCX_I3C_MINTCLR_RXPEND      11
+#define NPCX_I3C_MINTCLR_TXNOTFULL   12
+#define NPCX_I3C_MINTCLR_IBIWON      13
+#define NPCX_I3C_MINTCLR_ERRWARN     15
+#define NPCX_I3C_MINTCLR_NOWCNTLR    19
+#define NPCX_I3C_MINTMASKED_NOWCNTLR 19
+#define NPCX_I3C_MDATACTRL_FLUSHTB   0
+#define NPCX_I3C_MDATACTRL_FLUSHFB   1
+#define NPCX_I3C_MDATACTRL_UNLOCK    3
+#define NPCX_I3C_MDATACTRL_TXTRIG    FIELD(4, 2)
+#define NPCX_I3C_MDATACTRL_RXTRIG    FIELD(6, 2)
+#define NPCX_I3C_MDATACTRL_TXCOUNT   FIELD(16, 5)
+#define NPCX_I3C_MDATACTRL_RXCOUNT   FIELD(24, 5)
+#define NPCX_I3C_MDATACTRL_TXFULL    30
+#define NPCX_I3C_MDATACTRL_RXEMPTY   31
+#define NPCX_I3C_MERRWARN_NACK       2
+#define NPCX_I3C_MERRWARN_WRABT      3
+#define NPCX_I3C_MERRWARN_TERM       4
+#define NPCX_I3C_MERRWARN_HPAR       9
+#define NPCX_I3C_MERRWARN_HCRC       10
+#define NPCX_I3C_MERRWARN_OREAD      16
+#define NPCX_I3C_MERRWARN_OWRITE     17
+#define NPCX_I3C_MERRWARN_MSGERR     18
+#define NPCX_I3C_MERRWARN_INVERQ     19
+#define NPCX_I3C_MERRWARN_TIMEOUT    20
+#define NPCX_I3C_MDMACTRL_DMAFB      FIELD(0, 2)
+#define NPCX_I3C_MDMACTRL_DMATB      FIELD(2, 2)
+
+/* I3C target register fields */
+#define NPCX_I3C_CONFIG_TGTENA          0
+#define NPCX_I3C_CONFIG_MATCHSS         2
+#define NPCX_I3C_CONFIG_S0IGNORE        3
+#define NPCX_I3C_CONFIG_IDRAND          8
+#define NPCX_I3C_CONFIG_OFFLINE         9
+#define NPCX_I3C_CONFIG_HDRCMD          FIELD(10, 2)
+#define NPCX_I3C_CONFIG_BAMATCH         FIELD(16, 7)
+#define NPCX_I3C_CONFIG_SADDR           FIELD(25, 7)
+#define NPCX_I3C_STATUS_STNOTSTOP       0
+#define NPCX_I3C_STATUS_STMSG           1
+#define NPCX_I3C_STATUS_STCCCH          2
+#define NPCX_I3C_STATUS_STREQRD         3
+#define NPCX_I3C_STATUS_STREQWR         4
+#define NPCX_I3C_STATUS_STDAA           5
+#define NPCX_I3C_STATUS_STHDR           6
+#define NPCX_I3C_STATUS_START           8
+#define NPCX_I3C_STATUS_MATCHED         9
+#define NPCX_I3C_STATUS_STOP            10
+#define NPCX_I3C_STATUS_RXPEND          11
+#define NPCX_I3C_STATUS_TXNOTFULL       12
+#define NPCX_I3C_STATUS_DACHG           13
+#define NPCX_I3C_STATUS_CCC             14
+#define NPCX_I3C_STATUS_ERRWARN         15
+#define NPCX_I3C_STATUS_HDRMATCH        16
+#define NPCX_I3C_STATUS_CHANDLED        17
+#define NPCX_I3C_STATUS_EVENT           18
+#define NPCX_I3C_STATUS_TGTRST          19
+#define NPCX_I3C_STATUS_EVDET           FIELD(20, 2)
+#define NPCX_I3C_STATUS_IBIDIS          24
+#define NPCX_I3C_STATUS_MRDIS           25
+#define NPCX_I3C_STATUS_HJDIS           27
+#define NPCX_I3C_STATUS_ACTSTATE        FIELD(28, 2)
+#define NPCX_I3C_STATUS_TIMECTRL        FIELD(30, 2)
+#define NPCX_I3C_CTRL_EVENT             FIELD(0, 2)
+#define NPCX_I3C_CTRL_EXTDATA           3
+#define NPCX_I3C_CTRL_MAPIDX            FIELD(4, 4)
+#define NPCX_I3C_CTRL_IBIDATA           FIELD(8, 8)
+#define NPCX_I3C_CTRL_PENDINT           FIELD(16, 4)
+#define NPCX_I3C_CTRL_ACTSTATE          FIELD(20, 2)
+#define NPCX_I3C_CTRL_VENDINFO          FIELD(24, 8)
+#define NPCX_I3C_INTSET_START           8
+#define NPCX_I3C_INTSET_MATCHED         9
+#define NPCX_I3C_INTSET_STOP            10
+#define NPCX_I3C_INTSET_RXPEND          11
+#define NPCX_I3C_INTSET_TXNOTFULL       12
+#define NPCX_I3C_INTSET_DACHG           13
+#define NPCX_I3C_INTSET_CCC             14
+#define NPCX_I3C_INTSET_ERRWARN         15
+#define NPCX_I3C_INTSET_HDRMATCH        16
+#define NPCX_I3C_INTSET_CHANDLED        17
+#define NPCX_I3C_INTSET_EVENT           18
+#define NPCX_I3C_INTSET_TGTRST          19
+#define NPCX_I3C_INTCLR_START           8
+#define NPCX_I3C_INTCLR_MATCHED         9
+#define NPCX_I3C_INTCLR_STOP            10
+#define NPCX_I3C_INTCLR_RXPEND          11
+#define NPCX_I3C_INTCLR_TXNOTFULL       12
+#define NPCX_I3C_INTCLR_DACHG           13
+#define NPCX_I3C_INTCLR_CCC             14
+#define NPCX_I3C_INTCLR_ERRWARN         15
+#define NPCX_I3C_INTCLR_HDRMATCH        16
+#define NPCX_I3C_INTCLR_CHANDLED        17
+#define NPCX_I3C_INTCLR_EVENT           18
+#define NPCX_I3C_INTCLR_TGTRST          19
+#define NPCX_I3C_INTMASKED_START        8
+#define NPCX_I3C_INTMASKED_MATCHED      9
+#define NPCX_I3C_INTMASKED_STOP         10
+#define NPCX_I3C_INTMASKED_RXPEND       11
+#define NPCX_I3C_INTMASKED_TXNOTFULL    12
+#define NPCX_I3C_INTMASKED_DACHG        13
+#define NPCX_I3C_INTMASKED_CCC          14
+#define NPCX_I3C_INTMASKED_ERRWARN      15
+#define NPCX_I3C_INTMASKED_HDRMATCH     16
+#define NPCX_I3C_INTMASKED_CHANDLED     17
+#define NPCX_I3C_INTMASKED_EVENT        18
+#define NPCX_I3C_INTMASKED_TGTRST       19
+#define NPCX_I3C_ERRWARN_ORUN           0
+#define NPCX_I3C_ERRWARN_URUN           1
+#define NPCX_I3C_ERRWARN_URUNNACK       2
+#define NPCX_I3C_ERRWARN_TERM           3
+#define NPCX_I3C_ERRWARN_INVSTART       4
+#define NPCX_I3C_ERRWARN_SPAR           8
+#define NPCX_I3C_ERRWARN_HPAR           9
+#define NPCX_I3C_ERRWARN_HCRC           10
+#define NPCX_I3C_ERRWARN_S0S1           11
+#define NPCX_I3C_ERRWARN_OREAD          16
+#define NPCX_I3C_ERRWARN_OWRITE         17
+#define NPCX_I3C_DMACTRL_DMAFB          FIELD(0, 2)
+#define NPCX_I3C_DMACTRL_DMATB          FIELD(2, 2)
+#define NPCX_I3C_DATACTRL_FLUSHTB       0
+#define NPCX_I3C_DATACTRL_FLUSHFB       1
+#define NPCX_I3C_DATACTRL_UNLOCK        3
+#define NPCX_I3C_DATACTRL_TXTRIG        FIELD(4, 2)
+#define NPCX_I3C_DATACTRL_RXTRIG        FIELD(6, 2)
+#define NPCX_I3C_DATACTRL_TXCOUNT       FIELD(16, 6)
+#define NPCX_I3C_DATACTRL_RXCOUNT       FIELD(24, 6)
+#define NPCX_I3C_DATACTRL_TXFULL        30
+#define NPCX_I3C_DATACTRL_RXEMPTY       31
+#define NPCX_I3C_WDATAB_DATA            FIELD(0, 8)
+#define NPCX_I3C_WDATAB_END_B           8
+#define NPCX_I3C_WDATAB_END_A           16
+#define NPCX_I3C_WDATABE_DATA           FIELD(0, 8)
+#define NPCX_I3C_WDATAH_DATA0           FIELD(0, 8)
+#define NPCX_I3C_WDATAH_DATA1           FIELD(8, 8)
+#define NPCX_I3C_WDATAH_END             16
+#define NPCX_I3C_WDATAHE_DATA0          FIELD(0, 8)
+#define NPCX_I3C_WDATAHE_DATA1          FIELD(8, 8)
+#define NPCX_I3C_RDATAB_DATA            FIELD(0, 8)
+#define NPCX_I3C_RDATAH_DATA0           FIELD(0, 8)
+#define NPCX_I3C_RDATAH_DATA1           FIELD(8, 8)
+#define NPCX_I3C_CAPABILITIES2_MAPCNT   FIELD(0, 4)
+#define NPCX_I3C_CAPABILITIES2_I2C10B   4
+#define NPCX_I3C_CAPABILITIES2_I2CRST   5
+#define NPCX_I3C_CAPABILITIES2_I2CDEVID 6
+#define NPCX_I3C_CAPABILITIES2_DATA32   7
+#define NPCX_I3C_CAPABILITIES2_IBIEXT   8
+#define NPCX_I3C_CAPABILITIES2_IBIXREG  9
+#define NPCX_I3C_CAPABILITIES2_SMLANE   FIELD(12, 2)
+#define NPCX_I3C_CAPABILITIES2_V1_1     16
+#define NPCX_I3C_CAPABILITIES2_TGTRST   17
+#define NPCX_I3C_CAPABILITIES2_GROUP    FIELD(18, 2)
+#define NPCX_I3C_CAPABILITIES2_AASA     21
+#define NPCX_I3C_CAPABILITIES2_SSTSUB   22
+#define NPCX_I3C_CAPABILITIES2_SSTWR    23
+#define NPCX_I3C_CAPABILITIES_IDENA     FIELD(0, 2)
+#define NPCX_I3C_CAPABILITIES_IDREG     FIELD(2, 4)
+#define NPCX_I3C_CAPABILITIES_HDRSUPP   FIELD(6, 3)
+#define NPCX_I3C_CAPABILITIES_CNTLR     9
+#define NPCX_I3C_CAPABILITIES_SADDR     FIELD(10, 2)
+#define NPCX_I3C_CAPABILITIES_CCCHANDLE FIELD(12, 4)
+#define NPCX_I3C_CAPABILITIES_IBI_MR_HJ FIELD(16, 5)
+#define NPCX_I3C_CAPABILITIES_TIMECTRL  21
+#define NPCX_I3C_CAPABILITIES_EXTFIFO   FIELD(23, 3)
+#define NPCX_I3C_CAPABILITIES_FIFOTX    FIELD(26, 2)
+#define NPCX_I3C_CAPABILITIES_FIFORX    FIELD(28, 2)
+#define NPCX_I3C_CAPABILITIES_INT       30
+#define NPCX_I3C_CAPABILITIES_DMA       31
+#define NPCX_I3C_DYNADDR_DAVALID        0
+#define NPCX_I3C_DYNADDR_DADDR          FIELD(1, 7)
+#define NPCX_I3C_DYNADDR_CAUSE          FIELD(8, 3)
+#define NPCX_I3C_MAXLIMITS_MAXRD        FIELD(0, 12)
+#define NPCX_I3C_MAXLIMITS_MAXWR        FIELD(16, 12)
+#define NPCX_I3C_IDEXT_DCR              FIELD(8, 8)
+#define NPCX_I3C_IDEXT_BCR              FIELD(16, 8)
+#define NPCX_I3C_VENDORID_VID           FIELD(0, 15)
+#define NPCX_I3C_TCCLOCK_ACCURACY       FIELD(0, 8)
+#define NPCX_I3C_TCCLOCK_FREQ           FIELD(8, 8)
+#define NPCX_I3C_MSGLAST_MAPLAST        FIELD(0, 4)
+#define NPCX_I3C_MSGLAST_LASTSTATIC     4
+#define NPCX_I3C_MSGLAST_LASTGROUP      5
+#define NPCX_I3C_MSGLAST_LASTMODE       FIELD(6, 2)
+#define NPCX_I3C_MSGLAST_MAPLASTM1      FIELD(8, 4)
+#define NPCX_I3C_MSGLAST_LASTGROUPM1    13
+#define NPCX_I3C_MSGLAST_LASTMODE1      FIELD(14, 2)
+#define NPCX_I3C_MSGLAST_MAPLASTM2      FIELD(16, 4)
+#define NPCX_I3C_MSGLAST_LASTGROUPM2    21
+#define NPCX_I3C_MSGLAST_LASTMODE2      FIELD(22, 2)
+#define NPCX_I3C_RSTACTTIME_PERRSTTIM   FIELD(0, 8)
+#define NPCX_I3C_RSTACTTIME_SYSRSTTIM   FIELD(8, 8)
+#define NPCX_I3C_HDRCMD_CMD0            FIELD(0, 8)
+#define NPCX_I3C_HDRCMD_OVFL            30
+#define NPCX_I3C_HDRCMD_NEWCMD          31
+#define NPCX_I3C_GROUPDEF_GRP0ENA       0
+#define NPCX_I3C_GROUPDEF_GRP0DA        FIELD(1, 7)
+#define NPCX_I3C_GROUPDEF_GRP1ENA       8
+#define NPCX_I3C_GROUPDEF_GRP1DA        FIELD(9, 7)
+#define NPCX_I3C_GROUPDEF_GRP2ENA       16
+#define NPCX_I3C_GROUPDEF_GRP2DA        FIELD(17, 7)
+#define NPCX_I3C_MAPCTRL0_ENA           0
+#define NPCX_I3C_MAPCTRL0_DA            FIELD(1, 7)
+#define NPCX_I3C_MAPCTRL0_CAUSE         FIELD(8, 3)
+#define NPCX_I3C_MAPCTRLn_ENA           0
+#define NPCX_I3C_MAPCTRLn_ADDR          FIELD(1, 7)
+#define NPCX_I3C_MAPCTRLn_MAPSA         8
+#define NPCX_I3C_MAPCTRLn_NACK          12
+#define NPCX_I3C_MAPCTRLn_AUTO          13
+#define NPCX_I3C_MAPCTRLn_SLOT_PID      FIELD(14, 5)
+#define NPCX_I3C_IBIEXT1_CNT            FIELD(0, 3)
+#define NPCX_I3C_IBIEXT1_EXT1           FIELD(8, 8)
+#define NPCX_I3C_IBIEXT1_EXT2           FIELD(16, 8)
+#define NPCX_I3C_IBIEXT1_EXT3           FIELD(24, 8)
+#define NPCX_I3C_IBIEXT2_EXT4           FIELD(0, 8)
+#define NPCX_I3C_IBIEXT2_EXT5           FIELD(8, 8)
+#define NPCX_I3C_IBIEXT2_EXT6           FIELD(16, 8)
+#define NPCX_I3C_IBIEXT2_EXT7           FIELD(24, 8)
+
+/* MDMA Controller registers */
+struct mdma_reg {
+	/* Channel 0 */
+	/* 0x000: Channel 0 Control */
+	volatile uint32_t MDMA_CTL0;
+	/* 0x004: Channel 0 Source Base Address */
+	volatile uint32_t MDMA_SRCB0;
+	/* 0x008: Channel 0 Destination Base Address */
+	volatile uint32_t MDMA_DSTB0;
+	/* 0x00C: Channel 0 Transfer Count */
+	volatile uint32_t MDMA_TCNT0;
+	/* 0x010: reserved1 */
+	volatile uint32_t reserved1;
+	/* 0x014: Channel 0 Current Destination */
+	volatile uint32_t MDMA_CDST0;
+	/* 0x018: Channel 0 Current Transfer Count */
+	volatile uint32_t MDMA_CTCNT0;
+	/* 0x01C: reserved2 */
+	volatile uint32_t reserved2;
+
+	/* Channel 1 */
+	/* 0x020: Channel 1 Control */
+	volatile uint32_t MDMA_CTL1;
+	/* 0x024: Channel 1 Source Base Address */
+	volatile uint32_t MDMA_SRCB1;
+	/* 0x028: Channel 1 Destination Base Address */
+	volatile uint32_t MDMA_DSTB1;
+	/* 0x02C: Channel 1 Transfer Count */
+	volatile uint32_t MDMA_TCNT1;
+	/* 0x030: Channel 1 Current Source */
+	volatile uint32_t MDMA_CSRC1;
+	/* 0x034: reserved3 */
+	volatile uint32_t reserved3;
+	/* 0x038: Channel 1 Current Transfer Count */
+	volatile uint32_t MDMA_CTCNT1;
+};
+
+/* MDMA register fields */
+#define NPCX_MDMA_CTL_MDMAEN 0
+#define NPCX_MDMA_CTL_MPD    1
+#define NPCX_MDMA_CTL_SIEN   8
+#define NPCX_MDMA_CTL_MPS    14
+#define NPCX_MDMA_CTL_TC     18
+
+/* Channel 0/1 Transfer Count Register (MDMA_TCNT0/MDMA_TCNT1) */
+#define NPCX_MDMA_TCNT_TFR_CNT FIELD(0, 13)
+
+/* Channel 0/1 Current Transfer Count Register (MDMA_CTCNT0/MDMA_CTCNT1) */
+#define NPCX_MDMA_CTCNT_CURRENT_TFR_CNT FIELD(0, 13)
+
+#endif /* _NUVOTON_NPCX_REG_DEF_H */
diff --git a/soc/nuvoton/npcx/common/registers.c b/soc/nuvoton/npcx/common/npcxn/registers.c
similarity index 99%
rename from soc/nuvoton/npcx/common/registers.c
rename to soc/nuvoton/npcx/common/npcxn/registers.c
index e54775bc647..5483fc978b9 100644
--- a/soc/nuvoton/npcx/common/registers.c
+++ b/soc/nuvoton/npcx/common/npcxn/registers.c
@@ -6,6 +6,7 @@
 
 #include <zephyr/device.h>
 #include <soc.h>
+#include "reg_def.h"
 
 /* CDCG register structure check */
 NPCX_REG_SIZE_CHECK(cdcg_reg, 0x116);
diff --git a/soc/nuvoton/npcx/common/power.c b/soc/nuvoton/npcx/common/power.c
index ea36d4b37f7..8c909a50fb9 100644
--- a/soc/nuvoton/npcx/common/power.c
+++ b/soc/nuvoton/npcx/common/power.c
@@ -199,7 +199,7 @@ static void npcx_power_enter_system_sleep(int slp_mode, int wk_mode)
 }
 
 /* Invoke when enter "Suspend/Low Power" mode. */
-void pm_state_set(enum pm_state state, uint8_t substate_id)
+__weak void pm_state_set(enum pm_state state, uint8_t substate_id)
 {
 	if (state != PM_STATE_SUSPEND_TO_IDLE) {
 		LOG_DBG("Unsupported power state %u", state);
@@ -228,7 +228,7 @@ void pm_state_set(enum pm_state state, uint8_t substate_id)
 }
 
 /* Handle soc specific activity after exiting "Suspend/Low Power" mode. */
-void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
+__weak void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 {
 	if (state != PM_STATE_SUSPEND_TO_IDLE) {
 		LOG_DBG("Unsupported power state %u", state);
diff --git a/soc/nuvoton/npcx/common/reg/reg_access.h b/soc/nuvoton/npcx/common/reg/reg_access.h
deleted file mode 100644
index ae1d6a61694..00000000000
--- a/soc/nuvoton/npcx/common/reg/reg_access.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Copyright (c) 2020 Nuvoton Technology Corporation.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _NUVOTON_NPCX_REG_ACCESS_H
-#define _NUVOTON_NPCX_REG_ACCESS_H
-
-/*
- * NPCX register bit/field access operations
- */
-#define IS_BIT_SET(reg, bit)        (((reg >> bit) & (0x1)) != 0)
-
-#define GET_POS_FIELD(pos, size)    pos
-#define GET_SIZE_FIELD(pos, size)   size
-#define FIELD_POS(field)            GET_POS_##field
-#define FIELD_SIZE(field)           GET_SIZE_##field
-
-#define GET_FIELD(reg, field) \
-	_GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field))
-#define _GET_FIELD_(reg, f_pos, f_size) (((reg)>>(f_pos)) & ((1<<(f_size))-1))
-
-#define SET_FIELD(reg, field, value) \
-	_SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value)
-#define _SET_FIELD_(reg, f_pos, f_size, value) \
-	((reg) = ((reg) & (~(((1 << (f_size))-1) << (f_pos)))) \
-			| ((value) << (f_pos)))
-
-#define GET_FIELD_POS(field) \
-	_GET_FIELD_POS_(FIELD_POS(field))
-#define _GET_FIELD_POS_(f_ops) f_ops
-
-#define GET_FIELD_SZ(field) \
-	_GET_FIELD_SZ_(FIELD_SIZE(field))
-#define _GET_FIELD_SZ_(f_ops) f_ops
-
-#endif /* _NUVOTON_NPCX_REG_ACCESS_H */
diff --git a/soc/nuvoton/npcx/common/reg/reg_def.h b/soc/nuvoton/npcx/common/reg/reg_def.h
deleted file mode 100644
index b35089f65b6..00000000000
--- a/soc/nuvoton/npcx/common/reg/reg_def.h
+++ /dev/null
@@ -1,2252 +0,0 @@
-/*
- * Copyright (c) 2020 Nuvoton Technology Corporation.
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _NUVOTON_NPCX_REG_DEF_H
-#define _NUVOTON_NPCX_REG_DEF_H
-
-#include <stdint.h>
-
-#include <zephyr/devicetree.h>
-#include <zephyr/sys/__assert.h>
-#include <zephyr/sys/util_macro.h>
-#include <zephyr/toolchain.h>
-
-/*
- * NPCX register structure size/offset checking macro function to mitigate
- * the risk of unexpected compiling results. All addresses of NPCX registers
- * must meet the alignment requirement of cortex-m4.
- * DO NOT use 'packed' attribute if module contains different length ie.
- * 8/16/32 bits registers.
- */
-#define NPCX_REG_SIZE_CHECK(reg_def, size) \
-	BUILD_ASSERT(sizeof(struct reg_def) == size, \
-		"Failed in size check of register structure!")
-#define NPCX_REG_OFFSET_CHECK(reg_def, member, offset) \
-	BUILD_ASSERT(offsetof(struct reg_def, member) == offset, \
-		"Failed in offset check of register structure member!")
-
-/*
- * NPCX register access checking via structure macro function to mitigate the
- * risk of unexpected compiling results if module contains different length
- * registers. For example, a word register access might break into two byte
- * register accesses by adding 'packed' attribute.
- *
- * For example, add this macro for word register 'PRSC' of PWM module in its
- * device init function for checking violation. Once it occurred, core will be
- * stalled forever and easy to find out what happens.
- */
-#define NPCX_REG_WORD_ACCESS_CHECK(reg, val) { \
-		uint16_t placeholder = reg; \
-		reg = val; \
-		__ASSERT(reg == val, "16-bit reg access failed!"); \
-		reg = placeholder; \
-	}
-#define NPCX_REG_DWORD_ACCESS_CHECK(reg, val) { \
-		uint32_t placeholder = reg; \
-		reg = val; \
-		__ASSERT(reg == val, "32-bit reg access failed!"); \
-		reg = placeholder; \
-	}
-/*
- * Core Domain Clock Generator (CDCG) device registers
- */
-struct cdcg_reg {
-	/* High Frequency Clock Generator (HFCG) registers */
-	/* 0x000: HFCG Control */
-	volatile uint8_t HFCGCTRL;
-	volatile uint8_t reserved1;
-	/* 0x002: HFCG M Low Byte Value */
-	volatile uint8_t HFCGML;
-	volatile uint8_t reserved2;
-	/* 0x004: HFCG M High Byte Value */
-	volatile uint8_t HFCGMH;
-	volatile uint8_t reserved3;
-	/* 0x006: HFCG N Value */
-	volatile uint8_t HFCGN;
-	volatile uint8_t reserved4;
-	/* 0x008: HFCG Prescaler */
-	volatile uint8_t HFCGP;
-	volatile uint8_t reserved5[7];
-	/* 0x010: HFCG Bus Clock Dividers */
-	volatile uint8_t HFCBCD;
-	volatile uint8_t reserved6;
-	/* 0x012: HFCG Bus Clock Dividers */
-	volatile uint8_t HFCBCD1;
-	volatile uint8_t reserved7;
-	/* 0x014: HFCG Bus Clock Dividers */
-	volatile uint8_t HFCBCD2;
-	volatile uint8_t reserved12[8];
-	/* 0x01d: HFCG Bus Clock Dividers */
-	volatile uint8_t HFCBCD3;
-	volatile uint8_t reserved8[226];
-
-	/* Low Frequency Clock Generator (LFCG) registers */
-	/* 0x100: LFCG Control */
-	volatile uint8_t  LFCGCTL;
-	volatile uint8_t reserved9;
-	/* 0x102: High-Frequency Reference Divisor I */
-	volatile uint16_t HFRDI;
-	/* 0x104: High-Frequency Reference Divisor F */
-	volatile uint16_t HFRDF;
-	/* 0x106: FRCLK Clock Divisor */
-	volatile uint16_t FRCDIV;
-	/* 0x108: Divisor Correction Value 1 */
-	volatile uint16_t DIVCOR1;
-	/* 0x10A: Divisor Correction Value 2 */
-	volatile uint16_t DIVCOR2;
-	volatile uint8_t reserved10[8];
-	/* 0x114: LFCG Control 2 */
-	volatile uint8_t  LFCGCTL2;
-	volatile uint8_t  reserved11;
-};
-
-/* CDCG register fields */
-#define NPCX_HFCGCTRL_LOAD                    0
-#define NPCX_HFCGCTRL_LOCK                    2
-#define NPCX_HFCGCTRL_CLK_CHNG                7
-
-#define NPCX_LFCGCTL2_XT_OSC_SL_EN            6
-
-/*
- * Power Management Controller (PMC) device registers
- */
-struct pmc_reg {
-	/* 0x000: Power Management Controller */
-	volatile uint8_t PMCSR;
-	volatile uint8_t reserved1[2];
-	/* 0x003: Enable in Sleep Control */
-	volatile uint8_t ENIDL_CTL;
-	/* 0x004: Disable in Idle Control */
-	volatile uint8_t DISIDL_CTL;
-	/* 0x005: Disable in Idle Control 1 */
-	volatile uint8_t DISIDL_CTL1;
-	volatile uint8_t reserved2[2];
-	/* 0x008 - 0D: Power-Down Control 1 - 6 */
-	volatile uint8_t PWDWN_CTL1[6];
-	volatile uint8_t reserved3[18];
-	/* 0x020 - 21: Power-Down Control 1 - 2 */
-	volatile uint8_t RAM_PD[2];
-	volatile uint8_t reserved4[2];
-	/* 0x024: Power-Down Control 7 */
-	volatile uint8_t PWDWN_CTL7[1];
-};
-
-/* PMC internal inline functions for multi-registers */
-static inline uint32_t npcx_pwdwn_ctl_offset(uint32_t ctl_no)
-{
-	if (ctl_no < 6) {
-		return 0x008 + ctl_no;
-	} else {
-		return 0x024 + ctl_no - 6;
-	}
-}
-
-/* Macro functions for PMC multi-registers */
-#define NPCX_PWDWN_CTL(base, n) (*(volatile uint8_t *)(base + \
-						npcx_pwdwn_ctl_offset(n)))
-
-/* PMC register fields */
-#define NPCX_PMCSR_DI_INSTW                   0
-#define NPCX_PMCSR_DHF                        1
-#define NPCX_PMCSR_IDLE                       2
-#define NPCX_PMCSR_NWBI                       3
-#define NPCX_PMCSR_OHFC                       6
-#define NPCX_PMCSR_OLFC                       7
-#define NPCX_DISIDL_CTL_RAM_DID               5
-#define NPCX_ENIDL_CTL_ADC_LFSL               7
-#define NPCX_ENIDL_CTL_LP_WK_CTL              6
-#define NPCX_ENIDL_CTL_PECI_ENI               2
-#define NPCX_ENIDL_CTL_ADC_ACC_DIS            1
-
-/* Macro functions for Development and Debugger Interface (DDI) registers */
-#define NPCX_DBGCTRL(base)   (*(volatile uint8_t *)(base + 0x004))
-#define NPCX_DBGFRZEN1(base) (*(volatile uint8_t *)(base + 0x006))
-#define NPCX_DBGFRZEN2(base) (*(volatile uint8_t *)(base + 0x007))
-#define NPCX_DBGFRZEN3(base) (*(volatile uint8_t *)(base + 0x008))
-#define NPCX_DBGFRZEN4(base) (*(volatile uint8_t *)(base + 0x009))
-
-/* DDI register fields */
-#define NPCX_DBGCTRL_CCDEV_SEL		FIELD(6, 2)
-#define NPCX_DBGCTRL_CCDEV_DIR		5
-#define NPCX_DBGCTRL_SEQ_WK_EN		4
-#define NPCX_DBGCTRL_FRCLK_SEL_DIS	3
-#define NPCX_DBGFRZEN1_SPIFEN		7
-#define NPCX_DBGFRZEN1_HIFEN		6
-#define NPCX_DBGFRZEN1_ESPISEN		5
-#define NPCX_DBGFRZEN1_UART1FEN		4
-#define NPCX_DBGFRZEN1_SMB3FEN		3
-#define NPCX_DBGFRZEN1_SMB2FEN		2
-#define NPCX_DBGFRZEN1_MFT2FEN		1
-#define NPCX_DBGFRZEN1_MFT1FEN		0
-#define NPCX_DBGFRZEN2_ITIM6FEN		7
-#define NPCX_DBGFRZEN2_ITIM5FEN		6
-#define NPCX_DBGFRZEN2_ITIM4FEN		5
-#define NPCX_DBGFRZEN2_ITIM64FEN	3
-#define NPCX_DBGFRZEN2_SMB1FEN		2
-#define NPCX_DBGFRZEN2_SMB0FEN		1
-#define NPCX_DBGFRZEN2_MFT3FEN		0
-#define NPCX_DBGFRZEN3_GLBL_FRZ_DIS	7
-#define NPCX_DBGFRZEN3_ITIM3FEN		6
-#define NPCX_DBGFRZEN3_ITIM2FEN		5
-#define NPCX_DBGFRZEN3_ITIM1FEN		4
-#define NPCX_DBGFRZEN3_I3CFEN		2
-#define NPCX_DBGFRZEN3_SMB4FEN		1
-#define NPCX_DBGFRZEN3_SHMFEN		0
-#define NPCX_DBGFRZEN4_UART2FEN		6
-#define NPCX_DBGFRZEN4_UART3FEN		5
-#define NPCX_DBGFRZEN4_UART4FEN		4
-#define NPCX_DBGFRZEN4_LCTFEN		3
-#define NPCX_DBGFRZEN4_SMB7FEN		2
-#define NPCX_DBGFRZEN4_SMB6FEN		1
-#define NPCX_DBGFRZEN4_SMB5FEN		0
-
-/*
- * System Configuration (SCFG) device registers
- */
-struct scfg_reg {
-	/* 0x000: Device Control */
-	volatile uint8_t DEVCNT;
-	/* 0x001: Straps Status */
-	volatile uint8_t STRPST;
-	/* 0x002: Reset Control and Status */
-	volatile uint8_t RSTCTL;
-	volatile uint8_t reserved1;
-	/* 0x004: Device Control 3*/
-	volatile uint8_t DEV_CTL3;
-	volatile uint8_t reserved2;
-	/* 0x006: Device Control 4 */
-	volatile uint8_t DEV_CTL4;
-	volatile uint8_t reserved3[9];
-	/* 0x010 - 1F: Device Alternate Function 0 - F */
-	volatile uint8_t DEVALT0[16];
-	volatile uint8_t reserved4[6];
-	/* 0x026: Low-Voltage GPIO Pins Control 5 */
-	volatile uint8_t LV_GPIO_CTL5[1];
-	volatile uint8_t reserved5;
-	/* 0x028: Pull-Up/Pull-Down Enable 0 */
-	volatile uint8_t PUPD_EN0;
-	/* 0x029: Pull-Up/Pull-Down Enable 1 */
-	volatile uint8_t PUPD_EN1;
-	/* 0x02A - 2E: Low-Voltage GPIO Pins Control 0 - 4 */
-	volatile uint8_t LV_GPIO_CTL0[5];
-};
-
-/* Macro functions for SCFG multi-registers */
-#define NPCX_DEV_CTL(base, n) \
-	(*(volatile uint8_t *)(base + n))
-#define NPCX_DEVALT(base, n) \
-	(*(volatile uint8_t *)(base + NPCX_DEVALT_OFFSET(n)))
-#define NPCX_DEVALT_LK(base, n) \
-	(*(volatile uint8_t *)(base + NPCX_DEVALT_LK_OFFSET(n)))
-#define NPCX_PUPD_EN(base, n) \
-	(*(volatile uint8_t *)(base + NPCX_PUPD_EN_OFFSET(n)))
-#define NPCX_LV_GPIO_CTL(base, n) \
-	(*(volatile uint8_t *)(base + NPCX_LV_GPIO_CTL_OFFSET(n)))
-
-#define NPCX_JEN_CTL1_OFFSET 0x120
-#define NPCX_JEN_CTL1(base) (*(volatile uint8_t *)(base + (NPCX_JEN_CTL1_OFFSET)))
-
-#define NPCX_JEN_CTL1_JEN_EN       FIELD(0, 4)
-#define NPCX_JEN_CTL1_JEN_HEN      FIELD(4, 4)
-#define NPCX_JEN_CTL1_JEN_ENABLE   0x9
-#define NPCX_JEN_CTL1_JEN_DISABLE  0x6
-
-/* SCFG register fields */
-#define NPCX_DEVCNT_F_SPI_TRIS                6
-#define NPCX_DEVCNT_HIF_TYP_SEL_FIELD         FIELD(2, 2)
-#define NPCX_DEVCNT_JEN1_HEN                  5
-#define NPCX_DEVCNT_JEN0_HEN                  4
-#define NPCX_STRPST_TRIST                     1
-#define NPCX_STRPST_TEST                      2
-#define NPCX_STRPST_JEN1                      4
-#define NPCX_STRPST_JEN0                      5
-#define NPCX_STRPST_SPI_COMP                  7
-#define NPCX_RSTCTL_VCC1_RST_STS              0
-#define NPCX_RSTCTL_DBGRST_STS                1
-#define NPCX_RSTCTL_VCC1_RST_SCRATCH          3
-#define NPCX_RSTCTL_LRESET_PLTRST_MODE        5
-#define NPCX_RSTCTL_HIPRST_MODE               6
-#define NPCX_DEV_CTL3_RNGINT_MD               1
-#define NPCX_DEV_CTL3_FVCC1_PURST_EN          2
-#define NPCX_DEV_CTL3_I3C1_MS                 3
-#define NPCX_DEV_CTL3_I3C2_MS                 4
-#define NPCX_DEV_CTL3_I3C3_MS                 5
-#define NPCX_DEV_CTL3_SIO_CLK_SEL             FIELD(6, 2)
-#define NPCX_DEV_CTL4_F_SPI_SLLK              2
-#define NPCX_DEV_CTL4_SPI_SP_SEL              4
-#define NPCX_DEV_CTL4_WP_IF                   5
-#define NPCX_DEV_CTL4_VCC1_RST_LK             6
-#define NPCX_DEVPU0_I2C0_0_PUE                0
-#define NPCX_DEVPU0_I2C0_1_PUE                1
-#define NPCX_DEVPU0_I2C1_0_PUE                2
-#define NPCX_DEVPU0_I2C2_0_PUE                4
-#define NPCX_DEVPU0_I2C3_0_PUE                6
-#define NPCX_DEVPU1_F_SPI_PUD_EN              7
-
-#if defined(CONFIG_SOC_SERIES_NPCX4)
-/* I3C module controller, target mode for the MDMA module operation */
-#define NPCX_DEV_CTL3_I3C_MODE_BIT(inst_id) BIT(inst_id + 3)
-#endif /* End of CONFIG_SOC_SERIES_NPCX4 */
-
-/* Supported host interface type for HIF_TYP_SEL FILED in DEVCNT register. */
-enum npcx_hif_type {
-	NPCX_HIF_TYPE_NONE,
-	NPCX_HIF_TYPE_LPC,
-	NPCX_HIF_TYPE_ESPI_SHI,
-};
-
-/* Supported VOSCCLK frequency for SIO_CLK_SEL FILED in DEV_CTL3 register. */
-enum npcx_voscclk_type {
-	NPCX_VOSCCLK_96MHz,
-	NPCX_VOSCCLK_100MHz,
-	NPCX_VOSCCLK_120MHz,
-	NPCX_VOSCCLK_90MHz,
-};
-
-/*
- * System Glue (GLUE) device registers
- */
-struct glue_reg {
-	volatile uint8_t reserved1[2];
-	/* 0x002: SMBus Start Bit Detection */
-	volatile uint8_t SMB_SBD;
-	/* 0x003: SMBus Event Enable */
-	volatile uint8_t SMB_EEN;
-	volatile uint8_t reserved2[12];
-	/* 0x010: Simple Debug Port Data 0 */
-	volatile uint8_t SDPD0;
-	volatile uint8_t reserved3;
-	/* 0x012: Simple Debug Port Data 1 */
-	volatile uint8_t SDPD1;
-	volatile uint8_t reserved4;
-	/* 0x014: Simple Debug Port Control and Status */
-	volatile uint8_t SDP_CTS;
-	volatile uint8_t reserved5[12];
-	/* 0x021: SMBus Bus Select */
-	volatile uint8_t SMB_SEL;
-	volatile uint8_t reserved6[5];
-	/* 0x027: PSL Control and Status */
-	volatile uint8_t PSL_CTS;
-};
-
-/* GLUE register fields */
-/* PSL input detection mode is configured by bits 7:4 of PSL_CTS */
-#define NPCX_PSL_CTS_MODE_BIT(bit) BIT(bit + 4)
-/* PSL input assertion events are reported by bits 3:0 of PSL_CTS */
-#define NPCX_PSL_CTS_EVENT_BIT(bit) BIT(bit)
-
-/*
- * Universal Asynchronous Receiver-Transmitter (UART) device registers
- */
-struct uart_reg {
-	/* 0x000: Transmit Data Buffer */
-	volatile uint8_t UTBUF;
-	volatile uint8_t reserved1;
-	/* 0x002: Receive Data Buffer */
-	volatile uint8_t URBUF;
-	volatile uint8_t reserved2;
-	/* 0x004: Interrupt Control */
-	volatile uint8_t UICTRL;
-	volatile uint8_t reserved3;
-	/* 0x006: Status */
-	volatile uint8_t USTAT;
-	volatile uint8_t reserved4;
-	/* 0x008: Frame Select */
-	volatile uint8_t UFRS;
-	volatile uint8_t reserved5;
-	/* 0x00A: Mode Select */
-	volatile uint8_t UMDSL;
-	volatile uint8_t reserved6;
-	/* 0x00C: Baud Rate Divisor */
-	volatile uint8_t UBAUD;
-	volatile uint8_t reserved7;
-	/* 0x00E: Baud Rate Prescaler */
-	volatile uint8_t UPSR;
-	volatile uint8_t reserved8[17];
-	/* 0x020: FIFO Mode Transmit Status */
-	volatile uint8_t UFTSTS;
-	volatile uint8_t reserved9;
-	/* 0x022: FIFO Mode Receive Status */
-	volatile uint8_t UFRSTS;
-	volatile uint8_t reserved10;
-	/* 0x024: FIFO Mode Transmit Control */
-	volatile uint8_t UFTCTL;
-	volatile uint8_t reserved11;
-	/* 0x026: FIFO Mode Receive Control */
-	volatile uint8_t UFRCTL;
-};
-
-/* UART register fields */
-#define NPCX_UICTRL_TBE                       0
-#define NPCX_UICTRL_RBF                       1
-#define NPCX_UICTRL_ETI                       5
-#define NPCX_UICTRL_ERI                       6
-#define NPCX_UICTRL_EEI                       7
-#define NPCX_USTAT_PE                         0
-#define NPCX_USTAT_FE                         1
-#define NPCX_USTAT_DOE                        2
-#define NPCX_USTAT_ERR                        3
-#define NPCX_USTAT_BKD                        4
-#define NPCX_USTAT_RB9                        5
-#define NPCX_USTAT_XMIP                       6
-#define NPCX_UFRS_CHAR_FIELD                  FIELD(0, 2)
-#define NPCX_UFRS_STP                         2
-#define NPCX_UFRS_XB9                         3
-#define NPCX_UFRS_PSEL_FIELD                  FIELD(4, 2)
-#define NPCX_UFRS_PEN                         6
-#define NPCX_UMDSL_FIFO_MD                    0
-#define NPCX_UMDSL_ETD                        4
-#define NPCX_UMDSL_ERD                        5
-
-#define NPCX_UFTSTS_TEMPTY_LVL                FIELD(0, 5)
-#define NPCX_UFTSTS_TEMPTY_LVL_STS            5
-#define NPCX_UFTSTS_TFIFO_EMPTY_STS           6
-#define NPCX_UFTSTS_NXMIP                     7
-#define NPCX_UFRSTS_RFULL_LVL_STS             5
-#define NPCX_UFRSTS_RFIFO_NEMPTY_STS          6
-#define NPCX_UFRSTS_ERR                       7
-#define NPCX_UFTCTL_TEMPTY_LVL_SEL            FIELD(0, 5)
-#define NPCX_UFTCTL_TEMPTY_LVL_EN             5
-#define NPCX_UFTCTL_TEMPTY_EN                 6
-#define NPCX_UFTCTL_NXMIP_EN                  7
-#define NPCX_UFRCTL_RFULL_LVL_SEL             FIELD(0, 5)
-#define NPCX_UFRCTL_RFULL_LVL_EN              5
-#define NPCX_UFRCTL_RNEMPTY_EN                6
-#define NPCX_UFRCTL_ERR_EN                    7
-
-/* Macro functions for MIWU multi-registers */
-#define NPCX_WKEDG(base, group) \
-	(*(volatile uint8_t *)(base +  NPCX_WKEDG_OFFSET(group)))
-#define NPCX_WKAEDG(base, group) \
-	(*(volatile uint8_t *)(base + NPCX_WKAEDG_OFFSET(group)))
-#define NPCX_WKPND(base, group) \
-	(*(volatile uint8_t *)(base + NPCX_WKPND_OFFSET(group)))
-#define NPCX_WKPCL(base, group) \
-	(*(volatile uint8_t *)(base + NPCX_WKPCL_OFFSET(group)))
-#define NPCX_WKEN(base, group) \
-	(*(volatile uint8_t *)(base + NPCX_WKEN_OFFSET(group)))
-#define NPCX_WKINEN(base, group) \
-	(*(volatile uint8_t *)(base + NPCX_WKINEN_OFFSET(group)))
-#define NPCX_WKMOD(base, group) \
-	(*(volatile uint8_t *)(base + NPCX_WKMOD_OFFSET(group)))
-#define NPCX_WKST(base, group) \
-	(*(volatile uint8_t *)(base + NPCX_WKST_OFFSET(group)))
-
-/*
- * General-Purpose I/O (GPIO) device registers
- */
-struct gpio_reg {
-	/* 0x000: Port GPIOx Data Out */
-	volatile uint8_t PDOUT;
-	/* 0x001: Port GPIOx Data In */
-	volatile uint8_t PDIN;
-	/* 0x002: Port GPIOx Direction */
-	volatile uint8_t PDIR;
-	/* 0x003: Port GPIOx Pull-Up or Pull-Down Enable */
-	volatile uint8_t PPULL;
-	/* 0x004: Port GPIOx Pull-Up/Down Selection */
-	volatile uint8_t PPUD;
-	/* 0x005: Port GPIOx Drive Enable by VDD Present */
-	volatile uint8_t PENVDD;
-	/* 0x006: Port GPIOx Output Type */
-	volatile uint8_t PTYPE;
-	/* 0x007: Port GPIOx Lock Control */
-	volatile uint8_t PLOCK_CTL;
-};
-
-/*
- * Pulse Width Modulator (PWM) device registers
- */
-struct pwm_reg {
-	/* 0x000: Clock Prescaler */
-	volatile uint16_t PRSC;
-	/* 0x002: Cycle Time */
-	volatile uint16_t CTR;
-	/* 0x004: PWM Control */
-	volatile uint8_t PWMCTL;
-	volatile uint8_t reserved1;
-	/* 0x006: Duty Cycle */
-	volatile uint16_t DCR;
-	volatile uint8_t reserved2[4];
-	/* 0x00C: PWM Control Extended */
-	volatile uint8_t PWMCTLEX;
-	volatile uint8_t reserved3;
-};
-
-/* PWM register fields */
-#define NPCX_PWMCTL_INVP                      0
-#define NPCX_PWMCTL_CKSEL                     1
-#define NPCX_PWMCTL_HB_DC_CTL_FIELD           FIELD(2, 2)
-#define NPCX_PWMCTL_PWR                       7
-#define NPCX_PWMCTLEX_FCK_SEL_FIELD           FIELD(4, 2)
-#define NPCX_PWMCTLEX_OD_OUT                  7
-
-/*
- * Analog-To-Digital Converter (ADC) device registers
- */
-struct adc_reg {
-	/* 0x000: ADC Status */
-	volatile uint16_t ADCSTS;
-	/* 0x002: ADC Configuration */
-	volatile uint16_t ADCCNF;
-	/* 0x004: ADC Timing Control */
-	volatile uint16_t ATCTL;
-	/* 0x006: ADC Single Channel Address */
-	volatile uint16_t ASCADD;
-	/* 0x008: ADC Scan Channels Select */
-	volatile uint16_t ADCCS;
-	/* 0x00A: ADC Scan Channels Select 2 */
-	volatile uint16_t ADCCS2;
-	volatile uint8_t reserved1[14];
-	/* 0x01A:  Threshold Status */
-	volatile uint16_t THRCTS;
-	volatile uint8_t reserved2[4];
-	/* 0x020: Internal register 1 for ADC Speed */
-	volatile uint16_t ADCCNF2;
-	/* 0x022: Internal register 2 for ADC Speed */
-	volatile uint16_t GENDLY;
-	volatile uint8_t reserved3[2];
-	/* 0x026: Internal register 3 for ADC Speed */
-	volatile uint16_t MEAST;
-};
-
-/* ADC internal inline functions for multi-registers */
-#define CHNDAT(base, ch) \
-	(*(volatile uint16_t *)((base) + NPCX_CHNDAT_OFFSET(ch)))
-#define THRCTL(base, ctrl) \
-	(*(volatile uint16_t *)(base + NPCX_THRCTL_OFFSET(ctrl)))
-
-/* ADC register fields */
-#define NPCX_ATCTL_SCLKDIV_FIELD              FIELD(0, 6)
-#define NPCX_ATCTL_DLY_FIELD                  FIELD(8, 3)
-#define NPCX_ASCADD_SADDR_FIELD               FIELD(0, 5)
-#define NPCX_ADCSTS_EOCEV                     0
-#define NPCX_ADCSTS_EOCCEV                    1
-#define NPCX_ADCCNF_ADCEN                     0
-#define NPCX_ADCCNF_ADCMD_FIELD               FIELD(1, 2)
-#define NPCX_ADCCNF_ADCRPTC                   3
-#define NPCX_ADCCNF_START                     4
-#define NPCX_ADCCNF_ADCTTE                    5
-#define NPCX_ADCCNF_INTECEN                   6
-#define NPCX_ADCCNF_INTECCEN                  7
-#define NPCX_ADCCNF_INTETCEN                  8
-#define NPCX_ADCCNF_INTOVFEN                  9
-#define NPCX_ADCCNF_STOP                      11
-#define NPCX_CHNDAT_CHDAT_FIELD               FIELD(0, 10)
-#define NPCX_CHNDAT_NEW                       15
-#define NPCX_THRCTS_ADC_WKEN                  15
-#define NPCX_THRCTS_THR3_IEN                  10
-#define NPCX_THRCTS_THR2_IEN                  9
-#define NPCX_THRCTS_THR1_IEN                  8
-#define NPCX_THRCTS_ADC_EVENT                 7
-#define NPCX_THRCTS_THR3_STS                  2
-#define NPCX_THRCTS_THR2_STS                  1
-#define NPCX_THRCTS_THR1_STS                  0
-#define NPCX_THR_DCTL_THRD_EN                 15
-#define NPCX_THR_DCTL_THR_DVAL                FIELD(0, 10)
-
-/*
- * Timer Watchdog (TWD) device registers
- */
-struct twd_reg {
-	/* 0x000: Timer and Watchdog Configuration */
-	volatile uint8_t TWCFG;
-	volatile uint8_t reserved1;
-	/* 0x002: Timer and Watchdog Clock Prescaler */
-	volatile uint8_t TWCP;
-	volatile uint8_t reserved2;
-	/* 0x004: TWD Timer 0 */
-	volatile uint16_t TWDT0;
-	/* 0x006: TWDT0 Control and Status */
-	volatile uint8_t T0CSR;
-	volatile uint8_t reserved3;
-	/* 0x008: Watchdog Count */
-	volatile uint8_t WDCNT;
-	volatile uint8_t reserved4;
-	/* 0x00A: Watchdog Service Data Match */
-	volatile uint8_t WDSDM;
-	volatile uint8_t reserved5;
-	/* 0x00C: TWD Timer 0 Counter */
-	volatile uint16_t TWMT0;
-	/* 0x00E: Watchdog Counter */
-	volatile uint8_t TWMWD;
-	volatile uint8_t reserved6;
-	/* 0x010: Watchdog Clock Prescaler */
-	volatile uint8_t WDCP;
-	volatile uint8_t reserved7;
-};
-
-/* TWD register fields */
-#define NPCX_TWCFG_LTWCFG                      0
-#define NPCX_TWCFG_LTWCP                       1
-#define NPCX_TWCFG_LTWDT0                      2
-#define NPCX_TWCFG_LWDCNT                      3
-#define NPCX_TWCFG_WDCT0I                      4
-#define NPCX_TWCFG_WDSDME                      5
-#define NPCX_T0CSR_RST                         0
-#define NPCX_T0CSR_TC                          1
-#define NPCX_T0CSR_WDLTD                       3
-#define NPCX_T0CSR_WDRST_STS                   4
-#define NPCX_T0CSR_WD_RUN                      5
-#define NPCX_T0CSR_TESDIS                      7
-
-/*
- * Enhanced Serial Peripheral Interface (eSPI) device registers
- */
-struct espi_reg {
-	/* 0x000: eSPI Identification */
-	volatile uint32_t ESPIID;
-	/* 0x004: eSPI Configuration */
-	volatile uint32_t ESPICFG;
-	/* 0x008: eSPI Status */
-	volatile uint32_t ESPISTS;
-	/* 0x00C: eSPI Interrupt Enable */
-	volatile uint32_t ESPIIE;
-	/* 0x010: eSPI Wake-Up Enable */
-	volatile uint32_t ESPIWE;
-	/* 0x014: Virtual Wire Register Index */
-	volatile uint32_t VWREGIDX;
-	/* 0x018: Virtual Wire Register Data */
-	volatile uint32_t VWREGDATA;
-	/* 0x01C: OOB Receive Buffer Read Head */
-	volatile uint32_t OOBRXRDHEAD;
-	/* 0x020: OOB Transmit Buffer Write Head */
-	volatile uint32_t OOBTXWRHEAD;
-	/* 0x024: OOB Channel Control */
-	volatile uint32_t OOBCTL;
-	/* 0x028: Flash Receive Buffer Read Head */
-	volatile uint32_t FLASHRXRDHEAD;
-	/* 0x02C: Flash Transmit Buffer Write Head */
-	volatile uint32_t FLASHTXWRHEAD;
-	volatile uint32_t reserved1;
-	/* 0x034: Flash Channel Configuration */
-	volatile uint32_t FLASHCFG;
-	/* 0x038: Flash Channel Control */
-	volatile uint32_t FLASHCTL;
-	/* 0x03C: eSPI Error Status */
-	volatile uint32_t ESPIERR;
-	/* 0x040: Peripheral Bus Master Receive Buffer Read Head */
-	volatile uint32_t PBMRXRDHEAD;
-	/* 0x044: Peripheral Bus Master Transmit Buffer Write Head */
-	volatile uint32_t PBMTXWRHEAD;
-	/* 0x048: Peripheral Channel Configuration */
-	volatile uint32_t PERCFG;
-	/* 0x04C: Peripheral Channel Control */
-	volatile uint32_t PERCTL;
-	/* 0x050: Status Image Register */
-	volatile uint16_t STATUS_IMG;
-	volatile uint16_t reserved2[79];
-	/* 0x0F0: NPCX specific eSPI Register1 */
-	volatile uint8_t NPCX_ONLY_ESPI_REG1;
-	/* 0x0F1: NPCX specific eSPI Register2 */
-	volatile uint8_t NPCX_ONLY_ESPI_REG2;
-	volatile uint16_t reserved3[7];
-	/* 0x100 - 127: Virtual Wire Event Slave-to-Master 0 - 9 */
-	volatile uint32_t VWEVSM[10];
-	volatile uint32_t reserved4[6];
-	/* 0x140 - 16F: Virtual Wire Event Master-to-Slave 0 - 11 */
-	volatile uint32_t VWEVMS[12];
-	volatile uint32_t reserved5[4];
-	/* 0x180 - 1BF: Virtual Wire GPIO Event Master-to-Slave 0 - 15 */
-	volatile uint32_t VWGPSM[16];
-	volatile uint32_t reserved6[79];
-	/* 0x2FC: Virtual Wire Channel Control */
-	volatile uint32_t VWCTL;
-	/* 0x300 - 34F: OOB Receive Buffer 0 - 19 */
-	volatile uint32_t OOBRXBUF[20];
-	volatile uint32_t reserved7[12];
-	/* 0x380 - 3CF: OOB Transmit Buffer 0-19 */
-	volatile uint32_t OOBTXBUF[20];
-	volatile uint32_t reserved8[11];
-	/* 0x3FC: OOB Channel Control used in 'direct' mode */
-	volatile uint32_t OOBCTL_DIRECT;
-	/* 0x400 - 443: Flash Receive Buffer 0-17 */
-	volatile uint32_t FLASHRXBUF[18];
-	volatile uint32_t reserved9[14];
-	/* 0x480 - 497: Flash Transmit Buffer 0-16 */
-	volatile uint32_t FLASHTXBUF[17];
-	volatile uint32_t reserved10[14];
-	/* 0x4FC: Flash Channel Control used in 'direct' mode */
-	volatile uint32_t FLASHCTL_DIRECT;
-	volatile uint32_t reserved12[64];
-	/* 0x600 - 63F */
-	volatile uint32_t FLASH_PRTR_BADDR[16];
-	/* 0x640 - 67F */
-	volatile uint32_t FLASH_PRTR_HADDR[16];
-	/* 0x680 - 6BF */
-	volatile uint32_t FLASH_RGN_TAG_OVR[16];
-	volatile uint32_t reserved13[80];
-	/* 0x800 */
-	volatile uint32_t FLASH_RPMC_CFG_1;
-	/* 0x804 */
-	volatile uint32_t FLASH_RPMC_CFG_2;
-	/* 0x808 */
-	volatile uint32_t RMAP_FLASH_OFFS;
-	/* 0x80C */
-	volatile uint32_t RMAP_DST_BASE;
-	/* 0x810 */
-	volatile uint32_t RMAP_WIN_SIZE;
-	/* 0x814 */
-	volatile uint32_t FLASHBASE;
-	volatile uint32_t reserved14[58];
-};
-
-/* eSPI register fields */
-#define NPCX_ESPICFG_PCHANEN             0
-#define NPCX_ESPICFG_VWCHANEN            1
-#define NPCX_ESPICFG_OOBCHANEN           2
-#define NPCX_ESPICFG_FLASHCHANEN         3
-#define NPCX_ESPICFG_HPCHANEN            4
-#define NPCX_ESPICFG_HVWCHANEN           5
-#define NPCX_ESPICFG_HOOBCHANEN          6
-#define NPCX_ESPICFG_HFLASHCHANEN        7
-#define NPCX_ESPICFG_CHANS_FIELD         FIELD(0, 4)
-#define NPCX_ESPICFG_HCHANS_FIELD        FIELD(4, 4)
-#define NPCX_ESPICFG_IOMODE_FIELD        FIELD(8, 2)
-#define NPCX_ESPICFG_MAXFREQ_FIELD       FIELD(10, 3)
-#define NPCX_ESPICFG_FLCHANMODE          16
-#define NPCX_ESPICFG_PCCHN_SUPP          24
-#define NPCX_ESPICFG_VWCHN_SUPP          25
-#define NPCX_ESPICFG_OOBCHN_SUPP         26
-#define NPCX_ESPICFG_FLASHCHN_SUPP       27
-#define NPCX_ESPIIE_IBRSTIE              0
-#define NPCX_ESPIIE_CFGUPDIE             1
-#define NPCX_ESPIIE_BERRIE               2
-#define NPCX_ESPIIE_OOBRXIE              3
-#define NPCX_ESPIIE_FLASHRXIE            4
-#define NPCX_ESPIIE_FLNACSIE             5
-#define NPCX_ESPIIE_PERACCIE             6
-#define NPCX_ESPIIE_DFRDIE               7
-#define NPCX_ESPIIE_VWUPDIE              8
-#define NPCX_ESPIIE_ESPIRSTIE            9
-#define NPCX_ESPIIE_PLTRSTIE             10
-#define NPCX_ESPIIE_AMERRIE              15
-#define NPCX_ESPIIE_AMDONEIE             16
-#define NPCX_ESPIIE_BMTXDONEIE           19
-#define NPCX_ESPIIE_PBMRXIE              20
-#define NPCX_ESPIIE_PMSGRXIE             21
-#define NPCX_ESPIIE_BMBURSTERRIE         22
-#define NPCX_ESPIIE_BMBURSTDONEIE        23
-#define NPCX_ESPIWE_IBRSTWE              0
-#define NPCX_ESPIWE_CFGUPDWE             1
-#define NPCX_ESPIWE_BERRWE               2
-#define NPCX_ESPIWE_OOBRXWE              3
-#define NPCX_ESPIWE_FLASHRXWE            4
-#define NPCX_ESPIWE_FLNACSWE             5
-#define NPCX_ESPIWE_PERACCWE             6
-#define NPCX_ESPIWE_DFRDWE               7
-#define NPCX_ESPIWE_VWUPDWE              8
-#define NPCX_ESPIWE_ESPIRSTWE            9
-#define NPCX_ESPIWE_PBMRXWE              20
-#define NPCX_ESPIWE_PMSGRXWE             21
-#define NPCX_ESPISTS_IBRST               0
-#define NPCX_ESPISTS_CFGUPD              1
-#define NPCX_ESPISTS_BERR                2
-#define NPCX_ESPISTS_OOBRX               3
-#define NPCX_ESPISTS_FLASHRX             4
-#define NPCX_ESPISTS_FLNACS              5
-#define NPCX_ESPISTS_PERACC              6
-#define NPCX_ESPISTS_DFRD                7
-#define NPCX_ESPISTS_VWUPD               8
-#define NPCX_ESPISTS_ESPIRST             9
-#define NPCX_ESPISTS_PLTRST              10
-#define NPCX_ESPISTS_AMERR               15
-#define NPCX_ESPISTS_AMDONE              16
-#define NPCX_ESPISTS_VWUPDW              17
-#define NPCX_ESPISTS_BMTXDONE            19
-#define NPCX_ESPISTS_PBMRX               20
-#define NPCX_ESPISTS_PMSGRX              21
-#define NPCX_ESPISTS_BMBURSTERR          22
-#define NPCX_ESPISTS_BMBURSTDONE         23
-#define NPCX_ESPISTS_ESPIRST_LVL         24
-#define NPCX_VWSWIRQ_IRQ_NUM             FIELD(0, 7)
-#define NPCX_VWSWIRQ_IRQ_LVL             7
-#define NPCX_VWSWIRQ_INDEX               FIELD(8, 7)
-#define NPCX_VWSWIRQ_INDEX_EN            15
-#define NPCX_VWSWIRQ_DIRTY               16
-#define NPCX_VWSWIRQ_ENPLTRST            17
-#define NPCX_VWSWIRQ_ENCDRST             19
-#define NPCX_VWSWIRQ_EDGE_IRQ            28
-#define NPCX_VWEVMS_WIRE                 FIELD(0, 4)
-#define NPCX_VWEVMS_VALID                FIELD(4, 4)
-#define NPCX_VWEVMS_INDEX                FIELD(8, 7)
-#define NPCX_VWEVMS_INDEX_EN             15
-#define NPCX_VWEVMS_IE                   18
-#define NPCX_VWEVMS_WE                   20
-#define NPCX_VWEVSM_WIRE                 FIELD(0, 4)
-#define NPCX_VWEVSM_VALID                FIELD(4, 4)
-#define NPCX_VWEVSM_INDEX                FIELD(8, 7)
-#define NPCX_VWEVSM_INDEX_EN             15
-#define NPCX_VWEVSM_BIT_VALID(n)         (4+n)
-#define NPCX_VWEVSM_HW_WIRE              FIELD(24, 4)
-#define NPCX_VWGPSM_INDEX_EN             15
-#define NPCX_OOBCTL_OOB_FREE             0
-#define NPCX_OOBCTL_OOB_AVAIL            1
-#define NPCX_OOBCTL_RSTBUFHEADS          2
-#define NPCX_OOBCTL_OOBPLSIZE            FIELD(10, 3)
-#define NPCX_FLASHCFG_FLASHBLERSSIZE     FIELD(7, 3)
-#define NPCX_FLASHCFG_FLASHPLSIZE        FIELD(10, 3)
-#define NPCX_FLASHCFG_FLASHREQSIZE       FIELD(13, 3)
-#define NPCX_FLASHCFG_FLCAPA             FIELD(24, 2)
-#define NPCX_FLASHCFG_TRGFLEBLKSIZE      FIELD(16, 8)
-#define NPCX_FLASHCFG_FLREQSUP           FIELD(0, 3)
-#define NPCX_FLASHCTL_FLASH_NP_FREE      0
-#define NPCX_FLASHCTL_FLASH_TX_AVAIL     1
-#define NPCX_FLASHCTL_STRPHDR            2
-#define NPCX_FLASHCTL_DMATHRESH          FIELD(3, 2)
-#define NPCX_FLASHCTL_AMTSIZE            FIELD(5, 8)
-#define NPCX_FLASHCTL_RSTBUFHEADS        13
-#define NPCX_FLASHCTL_CRCEN              14
-#define NPCX_FLASHCTL_CHKSUMSEL          15
-#define NPCX_FLASHCTL_AMTEN              16
-#define NPCX_FLASHCTL_SAF_AUTO_READ      18
-#define NPCX_FLASHCTL_AUTO_RD_DIS_CTL    19
-#define NPCX_FLASHCTL_BLK_FLASH_NP_FREE  20
-#define NPCX_FLASHBASE_FLBASE_ADDR       FIELD(12, 15)
-#define NPCX_FLASH_PRTR_BADDR            FIELD(12, 15)
-#define NPCX_FRGN_WPR                    29
-#define SAF_PROT_LCK                     31
-#define NPCX_FRGN_RPR                    30
-#define NPCX_FLASH_PRTR_HADDR            FIELD(12, 15)
-#define NPCX_FLASH_TAG_OVR_RPR           FIELD(16, 16)
-#define NPCX_FLASH_TAG_OVR_WPR           FIELD(0, 16)
-#define NPCX_FLASH_RPMC_CFG1_CNTR        FIELD(0, 4)
-#define NPCX_FLASH_RPMC_CFG1_OP1         FIELD(4, 8)
-#define NPCX_FLASH_RPMC_CFG1_TRGRPMCSUP  FIELD(26, 6)
-#define NPCX_ONLY_ESPI_REG1_UNLOCK_REG2         0x55
-#define NPCX_ONLY_ESPI_REG1_LOCK_REG2           0
-#define NPCX_ONLY_ESPI_REG2_TRANS_END_CONFIG    4
-
-/*
- * Mobile System Wake-Up Control (MSWC) device registers
- */
-struct mswc_reg {
-	/* 0x000: MSWC Control Status 1 */
-	volatile uint8_t MSWCTL1;
-	volatile uint8_t reserved1;
-	/* 0x002: MSWC Control Status 2 */
-	volatile uint8_t MSWCTL2;
-	volatile uint8_t reserved2[5];
-	/* 0x008: Host Configuration Base Address Low */
-	volatile uint8_t HCBAL;
-	volatile uint8_t reserved3;
-	/* 0x00A: Host Configuration Base Address High */
-	volatile uint8_t HCBAH;
-	volatile uint8_t reserved4;
-	/* 0X00C: MSWC INTERRUPT ENABLE 2 */
-	volatile uint8_t MSIEN2;
-	volatile uint8_t reserved5;
-	/* 0x00E: MSWC Host Event Status 0 */
-	volatile uint8_t MSHES0;
-	volatile uint8_t reserved6;
-	/* 0x010: MSWC Host Event Interrupt Enable */
-	volatile uint8_t MSHEIE0;
-	volatile uint8_t reserved7;
-	/* 0x012: Host Control */
-	volatile uint8_t HOST_CTL;
-	volatile uint8_t reserved8;
-	/* 0x014: SMI Pulse Length */
-	volatile uint8_t SMIP_LEN;
-	volatile uint8_t reserved9;
-	/* 0x016: SCI Pulse Length */
-	volatile uint8_t SCIP_LEN;
-	volatile uint8_t reserved10[5];
-	/* 0x01C: SRID Core Access */
-	volatile uint8_t SRID_CR;
-	volatile uint8_t reserved11[3];
-	/* 0x020: SID Core Access */
-	volatile uint8_t SID_CR;
-	volatile uint8_t reserved12;
-	/* 0x022: DEVICE_ID Core Access */
-	volatile uint8_t DEVICE_ID_CR;
-	volatile uint8_t reserved13[5];
-	/* 0x028: Chip Revision Core Access */
-	volatile uint8_t CHPREV_CR;
-	volatile uint8_t reserved14[5];
-	/* 0x02E: Virtual Wire Sleep States */
-	volatile uint8_t VW_SLPST1;
-	volatile uint8_t reserved15;
-};
-
-/* MSWC register fields */
-#define NPCX_MSWCTL1_HRSTOB              0
-#define NPCS_MSWCTL1_HWPRON              1
-#define NPCX_MSWCTL1_PLTRST_ACT          2
-#define NPCX_MSWCTL1_VHCFGA              3
-#define NPCX_MSWCTL1_HCFGLK              4
-#define NPCX_MSWCTL1_PWROFFB             6
-#define NPCX_MSWCTL1_A20MB               7
-
-/*
- * Shared Memory (SHM) device registers
- */
-struct shm_reg {
-	/* 0x000: Shared Memory Core Status */
-	volatile uint8_t SMC_STS;
-	/* 0x001: Shared Memory Core Control */
-	volatile uint8_t SMC_CTL;
-	/* 0x002: Shared Memory Host Control */
-	volatile uint8_t SHM_CTL;
-	volatile uint8_t reserved1[2];
-	/* 0x005: Indirect Memory Access Window Size */
-	volatile uint8_t IMA_WIN_SIZE;
-	volatile uint8_t reserved2;
-	/* 0x007: Shared Access Windows Size */
-	volatile uint8_t WIN_SIZE;
-	/* 0x008: Shared Access Window 1, Semaphore */
-	volatile uint8_t SHAW1_SEM;
-	/* 0x009: Shared Access Window 2, Semaphore */
-	volatile uint8_t SHAW2_SEM;
-	volatile uint8_t reserved3;
-	/* 0x00B: Indirect Memory Access, Semaphore */
-	volatile uint8_t IMA_SEM;
-	volatile uint8_t reserved4[2];
-	/* 0x00E: Shared Memory Configuration */
-	volatile uint16_t SHCFG;
-	/* 0x010: Shared Access Window 1 Write Protect */
-	volatile uint8_t WIN1_WR_PROT;
-	/* 0x011: Shared Access Window 1 Read Protect */
-	volatile uint8_t WIN1_RD_PROT;
-	/* 0x012: Shared Access Window 2 Write Protect */
-	volatile uint8_t WIN2_WR_PROT;
-	/* 0x013: Shared Access Window 2 Read Protect */
-	volatile uint8_t WIN2_RD_PROT;
-	volatile uint8_t reserved5[2];
-	/* 0x016: Indirect Memory Access Write Protect */
-	volatile uint8_t IMA_WR_PROT;
-	/* 0x017: Indirect Memory Access Read Protect */
-	volatile uint8_t IMA_RD_PROT;
-	volatile uint8_t reserved6[8];
-	/* 0x020: Shared Access Window 1 Base */
-	volatile uint32_t WIN_BASE1;
-	/* 0x024: Shared Access Window 2 Base */
-	volatile uint32_t WIN_BASE2;
-	volatile uint32_t reserved7;
-	/* 0x02C: Indirect Memory Access Base */
-	volatile uint32_t IMA_BASE;
-	volatile uint8_t reserved8[10];
-	/* 0x03A: Reset Configuration */
-	volatile uint8_t RST_CFG;
-	volatile uint8_t reserved9[5];
-	/* 0x040: Debug Port 80 Buffered Data */
-	volatile uint16_t DP80BUF;
-	/* 0x042: Debug Port 80 Status */
-	volatile uint8_t DP80STS;
-	volatile uint8_t reserved10;
-	/* 0x044: Debug Port 80 Control */
-	volatile uint8_t DP80CTL;
-	volatile uint8_t reserved11[3];
-	/* 0x048: Host_Offset in Windows 1, 2 Status */
-	volatile uint8_t HOFS_STS;
-	/* 0x049: Host_Offset in Windows 1, 2 Control */
-	volatile uint8_t HOFS_CTL;
-	/* 0x04A: Core_Offset in Window 2 Address */
-	volatile uint16_t COFS2;
-	/* 0x04C: Core_Offset in Window 1 Address */
-	volatile uint16_t COFS1;
-	volatile uint16_t reserved12;
-};
-
-/* SHM register fields */
-#define NPCX_SMC_STS_HRERR               0
-#define NPCX_SMC_STS_HWERR               1
-#define NPCX_SMC_STS_HSEM1W              4
-#define NPCX_SMC_STS_HSEM2W              5
-#define NPCX_SMC_STS_SHM_ACC             6
-#define NPCX_SMC_CTL_HERR_IE             2
-#define NPCX_SMC_CTL_HSEM1_IE            3
-#define NPCX_SMC_CTL_HSEM2_IE            4
-#define NPCX_SMC_CTL_ACC_IE              5
-#define NPCX_SMC_CTL_PREF_EN             6
-#define NPCX_SMC_CTL_HOSTWAIT            7
-#define NPCX_FLASH_SIZE_STALL_HOST       6
-#define NPCX_FLASH_SIZE_RD_BURST         7
-#define NPCX_WIN_SIZE_RWIN1_SIZE_FIELD   FIELD(0, 4)
-#define NPCX_WIN_SIZE_RWIN2_SIZE_FIELD   FIELD(4, 4)
-#define NPCX_WIN_PROT_RW1L_RP            0
-#define NPCX_WIN_PROT_RW1L_WP            1
-#define NPCX_WIN_PROT_RW1H_RP            2
-#define NPCX_WIN_PROT_RW1H_WP            3
-#define NPCX_WIN_PROT_RW2L_RP            4
-#define NPCX_WIN_PROT_RW2L_WP            5
-#define NPCX_WIN_PROT_RW2H_RP            6
-#define NPCX_WIN_PROT_RW2H_WP            7
-#define NPCX_PWIN_SIZEI_RPROT            13
-#define NPCX_PWIN_SIZEI_WPROT            14
-#define NPCX_CSEM2                       6
-#define NPCX_CSEM3                       7
-#define NPCX_DP80STS_FWR                 5
-#define NPCX_DP80STS_FNE                 6
-#define NPCX_DP80STS_FOR                 7
-#define NPCX_DP80CTL_DP80EN              0
-#define NPCX_DP80CTL_SYNCEN              1
-#define NPCX_DP80CTL_ADV                 2
-#define NPCX_DP80CTL_RAA                 3
-#define NPCX_DP80CTL_RFIFO               4
-#define NPCX_DP80CTL_CIEN                5
-#define NPCX_DP80CTL_DP80_HF_CFG         7
-#define NPCX_DP80BUF_OFFS_FIELD          FIELD(8, 3)
-
-/*
- * Keyboard and Mouse Controller (KBC) device registers
- */
-struct kbc_reg {
-	/* 0x000h: Host Interface Control */
-	volatile uint8_t HICTRL;
-	volatile uint8_t reserved1;
-	/* 0x002h: Host Interface IRQ Control */
-	volatile uint8_t HIIRQC;
-	volatile uint8_t reserved2;
-	/* 0x004h: Host Interface Keyboard/Mouse Status */
-	volatile uint8_t HIKMST;
-	volatile uint8_t reserved3;
-	/* 0x006h: Host Interface Keyboard Data Out Buffer */
-	volatile uint8_t HIKDO;
-	volatile uint8_t reserved4;
-	/* 0x008h: Host Interface Mouse Data Out Buffer */
-	volatile uint8_t HIMDO;
-	volatile uint8_t reserved5;
-	/* 0x00Ah: Host Interface Keyboard/Mouse Data In Buffer */
-	volatile uint8_t HIKMDI;
-	/* 0x00Bh: Host Interface Keyboard/Mouse Shadow Data In Buffer */
-	volatile uint8_t SHIKMDI;
-};
-
-/* KBC register field */
-#define NPCX_HICTRL_OBFKIE               0
-#define NPCX_HICTRL_OBFMIE               1
-#define NPCX_HICTRL_OBECIE               2
-#define NPCX_HICTRL_IBFCIE               3
-#define NPCX_HICTRL_PMIHIE               4
-#define NPCX_HICTRL_PMIOCIE              5
-#define NPCX_HICTRL_PMICIE               6
-#define NPCX_HICTRL_FW_OBF               7
-#define NPCX_HIKMST_OBF                  0
-#define NPCX_HIKMST_IBF                  1
-#define NPCX_HIKMST_F0                   2
-#define NPCX_HIKMST_A2                   3
-#define NPCX_HIKMST_ST0                  4
-#define NPCX_HIKMST_ST1                  5
-#define NPCX_HIKMST_ST2                  6
-#define NPCX_HIKMST_ST3                  7
-
-/*
- * Power Management Channel (PMCH) device registers
- */
-
-struct pmch_reg {
-	/* 0x000: Host Interface PM Status */
-	volatile uint8_t HIPMST;
-	volatile uint8_t reserved1;
-	/* 0x002: Host Interface PM Data Out Buffer */
-	volatile uint8_t HIPMDO;
-	volatile uint8_t reserved2;
-	/* 0x004: Host Interface PM Data In Buffer */
-	volatile uint8_t HIPMDI;
-	/* 0x005: Host Interface PM Shadow Data In Buffer */
-	volatile uint8_t SHIPMDI;
-	/* 0x006: Host Interface PM Data Out Buffer with SCI */
-	volatile uint8_t HIPMDOC;
-	volatile uint8_t reserved3;
-	/* 0x008: Host Interface PM Data Out Buffer with SMI */
-	volatile uint8_t HIPMDOM;
-	volatile uint8_t reserved4;
-	/* 0x00A: Host Interface PM Data In Buffer with SCI */
-	volatile uint8_t HIPMDIC;
-	volatile uint8_t reserved5;
-	/* 0x00C: Host Interface PM Control */
-	volatile uint8_t HIPMCTL;
-	/* 0x00D: Host Interface PM Control 2 */
-	volatile uint8_t HIPMCTL2;
-	/* 0x00E: Host Interface PM Interrupt Control */
-	volatile uint8_t HIPMIC;
-	volatile uint8_t reserved6;
-	/* 0x010: Host Interface PM Interrupt Enable */
-	volatile uint8_t HIPMIE;
-	volatile uint8_t reserved7;
-};
-
-/* PMCH register field */
-#define NPCX_HIPMIE_SCIE                 1
-#define NPCX_HIPMIE_SMIE                 2
-#define NPCX_HIPMCTL_IBFIE               0
-#define NPCX_HIPMCTL_OBEIE               1
-#define NPCX_HIPMCTL_SCIPOL              6
-#define NPCX_HIPMST_OBF                  0
-#define NPCX_HIPMST_IBF                  1
-#define NPCX_HIPMST_F0                   2
-#define NPCX_HIPMST_CMD                  3
-#define NPCX_HIPMST_ST0                  4
-#define NPCX_HIPMST_ST1                  5
-#define NPCX_HIPMST_ST2                  6
-#define NPCX_HIPMIC_SMIB                 1
-#define NPCX_HIPMIC_SCIB                 2
-#define NPCX_HIPMIC_SMIPOL               6
-
-/*
- * Core Access to Host (C2H) device registers
- */
-struct c2h_reg {
-	/* 0x000: Indirect Host I/O Address */
-	volatile uint16_t IHIOA;
-	/* 0x002: Indirect Host Data */
-	volatile uint8_t IHD;
-	volatile uint8_t reserved1;
-	/* 0x004: Lock Host Access */
-	volatile uint16_t LKSIOHA;
-	/* 0x006: Access Lock Violation */
-	volatile uint16_t SIOLV;
-	/* 0x008: Core-to-Host Modules Access Enable */
-	volatile uint16_t CRSMAE;
-	/* 0x00A: Module Control */
-	volatile uint8_t SIBCTRL;
-	volatile uint8_t reserved3;
-};
-
-/* C2H register fields */
-#define NPCX_LKSIOHA_LKCFG               0
-#define NPCX_LKSIOHA_LKSPHA              2
-#define NPCX_LKSIOHA_LKHIKBD             11
-#define NPCX_CRSMAE_CFGAE                0
-#define NPCX_CRSMAE_HIKBDAE              11
-#define NPCX_SIOLV_SPLV                  2
-#define NPCX_SIBCTRL_CSAE                0
-#define NPCX_SIBCTRL_CSRD                1
-#define NPCX_SIBCTRL_CSWR                2
-
-/*
- * SMBUS (SMB) device registers
- */
-struct smb_reg {
-	/* 0x000: SMB Serial Data */
-	volatile uint8_t SMBSDA;
-	volatile uint8_t reserved1;
-	/* 0x002: SMB Status */
-	volatile uint8_t SMBST;
-	volatile uint8_t reserved2;
-	/* 0x004: SMB Control Status */
-	volatile uint8_t SMBCST;
-	volatile uint8_t reserved3;
-	/* 0x006: SMB Control 1 */
-	volatile uint8_t SMBCTL1;
-	volatile uint8_t reserved4;
-	/* 0x008: SMB Own Address */
-	volatile uint8_t SMBADDR1;
-	volatile uint8_t reserved5;
-	/* 0x00A: SMB Control 2 */
-	volatile uint8_t SMBCTL2;
-	volatile uint8_t reserved6;
-	/* 0x00C: SMB Own Address */
-	volatile uint8_t SMBADDR2;
-	volatile uint8_t reserved7;
-	/* 0x00E: SMB Control 3 */
-	volatile uint8_t SMBCTL3;
-	/* 0x00F: SMB Bus Timeout */
-	volatile uint8_t SMBT_OUT;
-	union {
-		/* Bank 0 */
-		struct {
-			/* 0x010: SMB Own Address 3 */
-			volatile uint8_t SMBADDR3;
-			/* 0x011: SMB Own Address 7 */
-			volatile uint8_t SMBADDR7;
-			/* 0x012: SMB Own Address 4 */
-			volatile uint8_t SMBADDR4;
-			/* 0x013: SMB Own Address 8 */
-			volatile uint8_t SMBADDR8;
-			/* 0x014: SMB Own Address 5 */
-			volatile uint8_t SMBADDR5;
-			volatile uint8_t reserved8;
-			/* 0x016: SMB Own Address 6 */
-			volatile uint8_t SMBADDR6;
-			volatile uint8_t reserved9;
-			/* 0x018: SMB Control Status 2 */
-			volatile uint8_t SMBCST2;
-			/* 0x019: SMB Control Status 3 */
-			volatile uint8_t SMBCST3;
-			/* 0x01A: SMB Control 4 */
-			volatile uint8_t SMBCTL4;
-			volatile uint8_t reserved10;
-			/* 0x01C: SMB SCL Low Time */
-			volatile uint8_t SMBSCLLT;
-			/* 0x01D: SMB FIFO Control */
-			volatile uint8_t SMBFIF_CTL;
-			/* 0x01E: SMB SCL High Time */
-			volatile uint8_t SMBSCLHT;
-			volatile uint8_t reserved11;
-		};
-		/* Bank 1 */
-		struct {
-			/* 0x010: SMB FIFO Control */
-			volatile uint8_t SMBFIF_CTS;
-			volatile uint8_t reserved12;
-			/* 0x012: SMB Tx-FIFO Control */
-			volatile uint8_t SMBTXF_CTL;
-			volatile uint8_t reserved13;
-			/* 0x014: SMB Bus Timeout */
-			volatile uint8_t SMB_T_OUT;
-			volatile uint8_t reserved14[3];
-			/* 0x018: SMB Control Status 2 (FIFO) */
-			volatile uint8_t SMBCST2_FIFO;
-			/* 0x019: SMB Control Status 3 (FIFO) */
-			volatile uint8_t SMBCST3_FIFO;
-			/* 0x01A: SMB Tx-FIFO Status */
-			volatile uint8_t SMBTXF_STS;
-			volatile uint8_t reserved15;
-			/* 0x01C: SMB Rx-FIFO Status */
-			volatile uint8_t SMBRXF_STS;
-			volatile uint8_t reserved16;
-			/* 0x01E: SMB Rx-FIFO Control */
-			volatile uint8_t SMBRXF_CTL;
-			volatile uint8_t reserved17[1];
-		};
-	};
-};
-
-/* SMB register fields */
-#define NPCX_SMBST_XMIT                  0
-#define NPCX_SMBST_MASTER                1
-#define NPCX_SMBST_NMATCH                2
-#define NPCX_SMBST_STASTR                3
-#define NPCX_SMBST_NEGACK                4
-#define NPCX_SMBST_BER                   5
-#define NPCX_SMBST_SDAST                 6
-#define NPCX_SMBST_SLVSTP                7
-#define NPCX_SMBCST_BUSY                 0
-#define NPCX_SMBCST_BB                   1
-#define NPCX_SMBCST_MATCH                2
-#define NPCX_SMBCST_GCMATCH              3
-#define NPCX_SMBCST_TSDA                 4
-#define NPCX_SMBCST_TGSCL                5
-#define NPCX_SMBCST_MATCHAF              6
-#define NPCX_SMBCST_ARPMATCH             7
-#define NPCX_SMBCST2_MATCHA1F            0
-#define NPCX_SMBCST2_MATCHA2F            1
-#define NPCX_SMBCST2_MATCHA3F            2
-#define NPCX_SMBCST2_MATCHA4F            3
-#define NPCX_SMBCST2_MATCHA5F            4
-#define NPCX_SMBCST2_MATCHA6F            5
-#define NPCX_SMBCST2_MATCHA7F            6
-#define NPCX_SMBCST2_INTSTS              7
-#define NPCX_SMBCST3_MATCHA8F            0
-#define NPCX_SMBCST3_MATCHA9F            1
-#define NPCX_SMBCST3_MATCHA10F           2
-#define NPCX_SMBCTL1_START               0
-#define NPCX_SMBCTL1_STOP                1
-#define NPCX_SMBCTL1_INTEN               2
-#define NPCX_SMBCTL1_ACK                 4
-#define NPCX_SMBCTL1_GCMEN               5
-#define NPCX_SMBCTL1_NMINTE              6
-#define NPCX_SMBCTL1_STASTRE             7
-#define NPCX_SMBCTL2_ENABLE              0
-#define NPCX_SMBCTL2_SCLFRQ0_6_FIELD     FIELD(1, 7)
-#define NPCX_SMBCTL3_ARPMEN              2
-#define NPCX_SMBCTL3_SCLFRQ7_8_FIELD     FIELD(0, 2)
-#define NPCX_SMBCTL3_IDL_START           3
-#define NPCX_SMBCTL3_400K                4
-#define NPCX_SMBCTL3_BNK_SEL             5
-#define NPCX_SMBCTL3_SDA_LVL             6
-#define NPCX_SMBCTL3_SCL_LVL             7
-#define NPCX_SMBCTL4_HLDT_FIELD          FIELD(0, 6)
-#define NPCX_SMBCTL4_LVL_WE              7
-#define NPCX_SMBADDR1_SAEN               7
-#define NPCX_SMBADDR2_SAEN               7
-#define NPCX_SMBADDR3_SAEN               7
-#define NPCX_SMBADDR4_SAEN               7
-#define NPCX_SMBADDR5_SAEN               7
-#define NPCX_SMBADDR6_SAEN               7
-#define NPCX_SMBADDR7_SAEN               7
-#define NPCX_SMBADDR8_SAEN               7
-#define NPCX_SMBSEL_SMB4SEL              4
-#define NPCX_SMBSEL_SMB5SEL              5
-#define NPCX_SMBSEL_SMB6SEL              6
-#define NPCX_SMBFIF_CTS_RXF_TXE          1
-#define NPCX_SMBFIF_CTS_CLR_FIFO         6
-#define NPCX_SMBFIF_CTL_FIFO_EN          4
-#define NPCX_SMBRXF_STS_RX_THST          6
-
-/* RX FIFO threshold */
-#define NPCX_SMBRXF_CTL_RX_THR           FIELD(0, 6)
-#define NPCX_SMBRXF_CTL_LAST             7
-
-/*
- * Internal 32-bit Timer (ITIM32) device registers
- */
-struct itim32_reg {
-	volatile uint8_t reserved1;
-	/* 0x001: Internal 32-bit Timer Prescaler */
-	volatile uint8_t ITPRE32;
-	volatile uint8_t reserved2[2];
-	/* 0x004: Internal 32-bit Timer Control and Status */
-	volatile uint8_t ITCTS32;
-	volatile uint8_t reserved3[3];
-	/* 0x008: Internal 32-Bit Timer Counter */
-	volatile uint32_t ITCNT32;
-};
-
-/*
- * Internal 64-bit Timer (ITIM54) device registers
- */
-struct itim64_reg {
-	volatile uint8_t reserved1;
-	/* 0x001: Internal 64-bit Timer Prescaler */
-	volatile uint8_t ITPRE64;
-	volatile uint8_t reserved2[2];
-	/* 0x004: Internal 64-bit Timer Control and Status */
-	volatile uint8_t ITCTS64;
-	volatile uint8_t reserved3[3];
-	/* 0x008: Internal 32-Bit Timer Counter */
-	volatile uint32_t ITCNT64L;
-	/* 0x00C: Internal 32-Bit Timer Counter */
-	volatile uint32_t ITCNT64H;
-};
-
-/* ITIM register fields */
-#define NPCX_ITCTSXX_TO_STS              0
-#define NPCX_ITCTSXX_TO_IE               2
-#define NPCX_ITCTSXX_TO_WUE              3
-#define NPCX_ITCTSXX_CKSEL               4
-#define NPCX_ITCTSXX_ITEN                7
-
-/*
- * Tachometer (TACH) Sensor device registers
- */
-struct tach_reg {
-	/* 0x000: Timer/Counter 1 */
-	volatile uint16_t TCNT1;
-	/* 0x002: Reload/Capture A */
-	volatile uint16_t TCRA;
-	/* 0x004: Reload/Capture B */
-	volatile uint16_t TCRB;
-	/* 0x006: Timer/Counter 2 */
-	volatile uint16_t TCNT2;
-	/* 0x008: Clock Prescaler */
-	volatile uint8_t TPRSC;
-	volatile uint8_t reserved1;
-	/* 0x00A: Clock Unit Control */
-	volatile uint8_t TCKC;
-	volatile uint8_t reserved2;
-	/* 0x00C: Timer Mode Control */
-	volatile uint8_t TMCTRL;
-	volatile uint8_t reserved3;
-	/* 0x00E: Timer Event Control */
-	volatile uint8_t TECTRL;
-	volatile uint8_t reserved4;
-	/* 0x010: Timer Event Clear */
-	volatile uint8_t TECLR;
-	volatile uint8_t reserved5;
-	/* 0x012: Timer Interrupt Enable */
-	volatile uint8_t TIEN;
-	volatile uint8_t reserved6;
-	/* 0x014: Compare A */
-	volatile uint16_t TCPA;
-	/* 0x016: Compare B */
-	volatile uint16_t TCPB;
-	/* 0x018: Compare Configuration */
-	volatile uint8_t TCPCFG;
-	volatile uint8_t reserved7;
-	/* 0x01A: Timer Wake-Up Enable */
-	volatile uint8_t TWUEN;
-	volatile uint8_t reserved8;
-	/* 0x01C: Timer Configuration */
-	volatile uint8_t TCFG;
-	volatile uint8_t reserved9;
-};
-
-/* TACH register fields */
-#define NPCX_TCKC_LOW_PWR                7
-#define NPCX_TCKC_PLS_ACC_CLK            6
-#define NPCX_TCKC_C1CSEL_FIELD           FIELD(0, 3)
-#define NPCX_TCKC_C2CSEL_FIELD           FIELD(3, 3)
-#define NPCX_TMCTRL_MDSEL_FIELD          FIELD(0, 3)
-#define NPCX_TMCTRL_TAEN                 5
-#define NPCX_TMCTRL_TBEN                 6
-#define NPCX_TMCTRL_TAEDG                3
-#define NPCX_TMCTRL_TBEDG                4
-#define NPCX_TCFG_TADBEN                 6
-#define NPCX_TCFG_TBDBEN                 7
-#define NPCX_TECTRL_TAPND                0
-#define NPCX_TECTRL_TBPND                1
-#define NPCX_TECTRL_TCPND                2
-#define NPCX_TECTRL_TDPND                3
-#define NPCX_TECLR_TACLR                 0
-#define NPCX_TECLR_TBCLR                 1
-#define NPCX_TECLR_TCCLR                 2
-#define NPCX_TECLR_TDCLR                 3
-#define NPCX_TIEN_TAIEN                  0
-#define NPCX_TIEN_TBIEN                  1
-#define NPCX_TIEN_TCIEN                  2
-#define NPCX_TIEN_TDIEN                  3
-#define NPCX_TWUEN_TAWEN                 0
-#define NPCX_TWUEN_TBWEN                 1
-#define NPCX_TWUEN_TCWEN                 2
-#define NPCX_TWUEN_TDWEN                 3
-
-/* Debug Interface registers */
-struct dbg_reg {
-	/* 0x000: Debug Control */
-	volatile uint8_t DBGCTRL;
-	volatile uint8_t reserved1;
-	/* 0x002: Debug Freeze Enable 1 */
-	volatile uint8_t DBGFRZEN1;
-	/* 0x003: Debug Freeze Enable 2 */
-	volatile uint8_t DBGFRZEN2;
-	/* 0x004: Debug Freeze Enable 3 */
-	volatile uint8_t DBGFRZEN3;
-	/* 0x005: Debug Freeze Enable 4 */
-	volatile uint8_t DBGFRZEN4;
-};
-/* Debug Interface registers fields */
-#define NPCX_DBGFRZEN3_GLBL_FRZ_DIS      7
-
-/* PS/2 Interface registers */
-struct ps2_reg {
-	/* 0x000: PS/2 Data */
-	volatile uint8_t PSDAT;
-	volatile uint8_t reserved1;
-	/* 0x002: PS/2 Status */
-	volatile uint8_t PSTAT;
-	volatile uint8_t reserved2;
-	/* 0x004: PS/2 Control */
-	volatile uint8_t PSCON;
-	volatile uint8_t reserved3;
-	/* 0x006: PS/2 Output Signal */
-	volatile uint8_t PSOSIG;
-	volatile uint8_t reserved4;
-	/* 0x008: PS/2 Input Signal */
-	volatile uint8_t PSISIG;
-	volatile uint8_t reserved5;
-	/* 0x00A: PS/2 Interrupt Enable */
-	volatile uint8_t PSIEN;
-	volatile uint8_t reserved6;
-};
-
-/* PS/2 Interface registers fields */
-#define NPCX_PSTAT_SOT                   0
-#define NPCX_PSTAT_EOT                   1
-#define NPCX_PSTAT_PERR                  2
-#define NPCX_PSTAT_ACH                   FIELD(3, 3)
-#define NPCX_PSTAT_RFERR                 6
-
-#define NPCX_PSCON_EN                    0
-#define NPCX_PSCON_XMT                   1
-#define NPCX_PSCON_HDRV                  FIELD(2, 2)
-#define NPCX_PSCON_IDB                   FIELD(4, 3)
-#define NPCX_PSCON_WPUED                 7
-
-#define NPCX_PSOSIG_WDAT0                0
-#define NPCX_PSOSIG_WDAT1                1
-#define NPCX_PSOSIG_WDAT2                2
-#define NPCX_PSOSIG_CLK0                 3
-#define NPCX_PSOSIG_CLK1                 4
-#define NPCX_PSOSIG_CLK2                 5
-#define NPCX_PSOSIG_WDAT3                6
-#define NPCX_PSOSIG_CLK3                 7
-#define NPCX_PSOSIG_CLK(n)               (((n) < 3) ? ((n) + 3) : 7)
-#define NPCX_PSOSIG_WDAT(n)              (((n) < 3) ? ((n) + 0) : 6)
-#define NPCX_PSOSIG_CLK_MASK_ALL \
-					 (BIT(NPCX_PSOSIG_CLK0) | \
-					  BIT(NPCX_PSOSIG_CLK1) | \
-					  BIT(NPCX_PSOSIG_CLK2) | \
-					  BIT(NPCX_PSOSIG_CLK3))
-
-#define NPCX_PSIEN_SOTIE                 0
-#define NPCX_PSIEN_EOTIE                 1
-#define NPCX_PSIEN_PS2_WUE               4
-#define NPCX_PSIEN_PS2_CLK_SEL           7
-
-/* Flash Interface Unit (FIU) device registers */
-struct fiu_reg {
-	volatile uint8_t reserved1;
-	/* 0x001: Burst Configuration */
-	volatile uint8_t BURST_CFG;
-	/* 0x002: FIU Response Configuration */
-	volatile uint8_t RESP_CFG;
-	volatile uint8_t reserved2[17];
-	/* 0x014: SPI Flash Configuration */
-	volatile uint8_t SPI_FL_CFG;
-	volatile uint8_t reserved3;
-	/* 0x016: UMA Code Byte */
-	volatile uint8_t UMA_CODE;
-	/* 0x017: UMA Address Byte 0 */
-	volatile uint8_t UMA_AB0;
-	/* 0x018: UMA Address Byte 1 */
-	volatile uint8_t UMA_AB1;
-	/* 0x019: UMA Address Byte 2 */
-	volatile uint8_t UMA_AB2;
-	/* 0x01A: UMA Data Byte 0 */
-	volatile uint8_t UMA_DB0;
-	/* 0x01B: UMA Data Byte 1 */
-	volatile uint8_t UMA_DB1;
-	/* 0x01C: UMA Data Byte 2 */
-	volatile uint8_t UMA_DB2;
-	/* 0x01D: UMA Data Byte 3 */
-	volatile uint8_t UMA_DB3;
-	/* 0x01E: UMA Control and Status */
-	volatile uint8_t UMA_CTS;
-	/* 0x01F: UMA Extended Control and Status */
-	volatile uint8_t UMA_ECTS;
-	/* 0x020: UMA Data Bytes 0-3 */
-	volatile uint32_t UMA_DB0_3;
-	volatile uint8_t reserved4[2];
-	/* 0x026: CRC Control Register */
-	volatile uint8_t CRCCON;
-	/* 0x027: CRC Entry Register */
-	volatile uint8_t CRCENT;
-	/* 0x028: CRC Initialization and Result Register */
-	volatile uint32_t CRCRSLT;
-	volatile uint8_t reserved5[4];
-	/* 0x030: FIU Read Command */
-	volatile uint8_t FIU_RD_CMD;
-	volatile uint8_t reserved6;
-	/* 0x032: FIU Dummy Cycles */
-	volatile uint8_t FIU_DMM_CYC;
-	/* 0x033: FIU Extended Configuration */
-	volatile uint8_t FIU_EXT_CFG;
-#if defined(CONFIG_SOC_SERIES_NPCX9)
-	/* 0x034: UMA address byte 0-3 */
-	volatile uint32_t UMA_AB0_3;
-	/* 0x038-0x3C */
-	volatile uint8_t reserved8[5];
-	/* 0x03D: SPI Device */
-	volatile uint8_t SPI1_DEV;
-	/* 0x03E-0x3F */
-	volatile uint8_t reserved9[2];
-#elif defined(CONFIG_SOC_SERIES_NPCX4)
-	/* 0x034: UMA address byte 0-3 */
-	volatile uint32_t UMA_AB0_3;
-	/* 0x038-0x3B */
-	volatile uint8_t reserved8[4];
-	/* 0x03C: SPI Device */
-	volatile uint8_t SPI_DEV;
-	/* 0x03D */
-	volatile uint8_t reserved9;
-	/* 0x03E */
-	volatile uint8_t SPI_DEV_SIZE;
-	/* 0x03F */
-	volatile uint8_t reserved10;
-#endif
-};
-
-/* FIU register fields */
-#define NPCX_BURST_CFG_SPI_DEV_SEL       FIELD(4, 2)
-#define NPCX_RESP_CFG_IAD_EN             0
-#define NPCX_RESP_CFG_DEV_SIZE_EX        2
-#define NPCX_RESP_CFG_QUAD_EN            3
-#define NPCX_SPI_FL_CFG_RD_MODE          FIELD(6, 2)
-#define NPCX_UMA_CTS_A_SIZE              3
-#define NPCX_UMA_CTS_C_SIZE              4
-#define NPCX_UMA_CTS_RD_WR               5
-#define NPCX_UMA_CTS_DEV_NUM             6
-#define NPCX_UMA_CTS_EXEC_DONE           7
-#define NPCX_UMA_ECTS_SW_CS0             0
-#define NPCX_UMA_ECTS_SW_CS1             1
-#define NPCX_UMA_ECTS_SEC_CS             2
-#define NPCX_UMA_ECTS_UMA_LOCK           3
-#define NPCX_UMA_ECTS_UMA_ADDR_SIZE      FIELD(4, 3)
-#define NPCX_SPI1_DEV_FOUR_BADDR_CS10    6
-#define NPCX_SPI1_DEV_FOUR_BADDR_CS11    7
-#define NPCX_SPI1_DEV_SPI1_LO_DEV_SIZE   FIELD(0, 4)
-#define NPCX_FIU_EXT_CFG_SET_DMM_EN      2
-#define NPCX_FIU_EXT_CFG_SET_CMD_EN      1
-#define NPCX_SPI_DEV_NADDRB              FIELD(5, 3)
-
-#define NPCX_MSR_IE_CFG_UMA_BLOCK        3
-
-/* UMA fields selections */
-#define UMA_FLD_ADDR     BIT(NPCX_UMA_CTS_A_SIZE)  /* 3-bytes ADR field */
-#define UMA_FLD_NO_CMD   BIT(NPCX_UMA_CTS_C_SIZE)  /* No 1-Byte CMD field */
-#define UMA_FLD_WRITE    BIT(NPCX_UMA_CTS_RD_WR)   /* Write transaction */
-#define UMA_FLD_SHD_SL   BIT(NPCX_UMA_CTS_DEV_NUM) /* Shared flash selected */
-#define UMA_FLD_EXEC     BIT(NPCX_UMA_CTS_EXEC_DONE)
-
-#define UMA_FIELD_DATA_1 0x01
-#define UMA_FIELD_DATA_2 0x02
-#define UMA_FIELD_DATA_3 0x03
-#define UMA_FIELD_DATA_4 0x04
-
-/* UMA code for transaction */
-#define UMA_CODE_CMD_ONLY       (UMA_FLD_EXEC | UMA_FLD_SHD_SL)
-#define UMA_CODE_CMD_ADR        (UMA_FLD_EXEC | UMA_FLD_ADDR | \
-					UMA_FLD_SHD_SL)
-#define UMA_CODE_CMD_RD_BYTE(n) (UMA_FLD_EXEC | UMA_FIELD_DATA_##n | \
-					UMA_FLD_SHD_SL)
-#define UMA_CODE_RD_BYTE(n)     (UMA_FLD_EXEC | UMA_FLD_NO_CMD | \
-					UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
-#define UMA_CODE_CMD_WR_ONLY    (UMA_FLD_EXEC | UMA_FLD_WRITE | \
-					UMA_FLD_SHD_SL)
-#define UMA_CODE_CMD_WR_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_WRITE | \
-					UMA_FIELD_DATA_##n | UMA_FLD_SHD_SL)
-#define UMA_CODE_CMD_WR_ADR     (UMA_FLD_EXEC | UMA_FLD_WRITE | UMA_FLD_ADDR | \
-				UMA_FLD_SHD_SL)
-
-#define UMA_CODE_CMD_ADR_WR_BYTE(n) (UMA_FLD_EXEC | UMA_FLD_WRITE | \
-					UMA_FLD_ADDR | UMA_FIELD_DATA_##n | \
-					UMA_FLD_SHD_SL)
-
-/* Platform Environment Control Interface (PECI) device registers */
-struct peci_reg {
-	/* 0x000: PECI Control Status */
-	volatile uint8_t PECI_CTL_STS;
-	/* 0x001: PECI Read Length */
-	volatile uint8_t PECI_RD_LENGTH;
-	/* 0x002: PECI Address */
-	volatile uint8_t PECI_ADDR;
-	/* 0x003: PECI Command */
-	volatile uint8_t PECI_CMD;
-	/* 0x004: PECI Control 2 */
-	volatile uint8_t PECI_CTL2;
-	/* 0x005: PECI Index */
-	volatile uint8_t PECI_INDEX;
-	/* 0x006: PECI Index Data */
-	volatile uint8_t PECI_IDATA;
-	/* 0x007: PECI Write Length */
-	volatile uint8_t PECI_WR_LENGTH;
-	volatile uint8_t reserved1[3];
-	/* 0x00B: PECI Write FCS */
-	volatile uint8_t PECI_WR_FCS;
-	/* 0x00C: PECI Read FCS */
-	volatile uint8_t PECI_RD_FCS;
-	/* 0x00D: PECI Assured Write FCS */
-	volatile uint8_t PECI_AW_FCS;
-	volatile uint8_t reserved2;
-	/* 0x00F: PECI Transfer Rate */
-	volatile uint8_t PECI_RATE;
-	/* 0x010 - 0x04F: PECI Data In/Out */
-	union {
-		volatile uint8_t PECI_DATA_IN[64];
-		volatile uint8_t PECI_DATA_OUT[64];
-	};
-};
-
-/* PECI register fields */
-#define NPCX_PECI_CTL_STS_START_BUSY     0
-#define NPCX_PECI_CTL_STS_DONE           1
-#define NPCX_PECI_CTL_STS_CRC_ERR        3
-#define NPCX_PECI_CTL_STS_ABRT_ERR       4
-#define NPCX_PECI_CTL_STS_AWFCS_EB       5
-#define NPCX_PECI_CTL_STS_DONE_EN        6
-#define NPCX_PECI_RATE_MAX_BIT_RATE      FIELD(0, 5)
-#define NPCX_PECI_RATE_MAX_BIT_RATE_MASK 0x1F
-/* The minimal valid value of NPCX_PECI_RATE_MAX_BIT_RATE field */
-#define PECI_MAX_BIT_RATE_VALID_MIN      0x05
-#define PECI_HIGH_SPEED_MIN_VAL          0x07
-
-#define NPCX_PECI_RATE_EHSP              6
-
-/* KBS (Keyboard Scan) device registers */
-struct kbs_reg {
-	volatile uint8_t reserved1[4];
-	/* 0x004: Keyboard Scan In */
-	volatile uint8_t KBSIN;
-	/* 0x005: Keyboard Scan In Pull-Up Enable */
-	volatile uint8_t KBSINPU;
-	/* 0x006: Keyboard Scan Out 0 */
-	volatile uint16_t KBSOUT0;
-	/* 0x008: Keyboard Scan Out 1 */
-	volatile uint16_t KBSOUT1;
-	/* 0x00A: Keyboard Scan Buffer Index */
-	volatile uint8_t KBS_BUF_INDX;
-	/* 0x00B: Keyboard Scan Buffer Data */
-	volatile uint8_t KBS_BUF_DATA;
-	/* 0x00C: Keyboard Scan Event */
-	volatile uint8_t KBSEVT;
-	/* 0x00D: Keyboard Scan Control */
-	volatile uint8_t KBSCTL;
-	/* 0x00E: Keyboard Scan Configuration Index */
-	volatile uint8_t KBS_CFG_INDX;
-	/* 0x00F: Keyboard Scan Configuration Data */
-	volatile uint8_t KBS_CFG_DATA;
-};
-
-/* KBS register fields */
-#define NPCX_KBSBUFINDX                  0
-#define NPCX_KBSEVT_KBSDONE              0
-#define NPCX_KBSEVT_KBSERR               1
-#define NPCX_KBSCTL_START                0
-#define NPCX_KBSCTL_KBSMODE              1
-#define NPCX_KBSCTL_KBSIEN               2
-#define NPCX_KBSCTL_KBSINC               3
-#define NPCX_KBSCTL_KBHDRV_FIELD         FIELD(6, 2)
-#define NPCX_KBSCFGINDX                  0
-/* Index of 'Automatic Scan' configuration register */
-#define KBS_CFG_INDX_DLY1                0 /* Keyboard Scan Delay T1 Byte */
-#define KBS_CFG_INDX_DLY2                1 /* Keyboard Scan Delay T2 Byte */
-#define KBS_CFG_INDX_RTYTO               2 /* Keyboard Scan Retry Timeout */
-#define KBS_CFG_INDX_CNUM                3 /* Keyboard Scan Columns Number */
-#define KBS_CFG_INDX_CDIV                4 /* Keyboard Scan Clock Divisor */
-
-/* SHI (Serial Host Interface) registers */
-struct shi_reg {
-	volatile uint8_t reserved1;
-	/* 0x001: SHI Configuration 1 */
-	volatile uint8_t SHICFG1;
-	/* 0x002: SHI Configuration 2 */
-	volatile uint8_t SHICFG2;
-	volatile uint8_t reserved2[2];
-	/* 0x005: Event Enable */
-	volatile uint8_t EVENABLE;
-	/* 0x006: Event Status */
-	volatile uint8_t EVSTAT;
-	/* 0x007: SHI Capabilities */
-	volatile uint8_t CAPABILITY;
-	/* 0x008: Status */
-	volatile uint8_t STATUS;
-	volatile uint8_t reserved3;
-	/* 0x00A: Input Buffer Status */
-	volatile uint8_t IBUFSTAT;
-	/* 0x00B: Output Buffer Status */
-	volatile uint8_t OBUFSTAT;
-	/* 0x00C: SHI Configuration 3 */
-	volatile uint8_t SHICFG3;
-	/* 0x00D: SHI Configuration 4 */
-	volatile uint8_t SHICFG4;
-	/* 0x00E: SHI Configuration 5 */
-	volatile uint8_t SHICFG5;
-	/* 0x00F: Event Status 2 */
-	volatile uint8_t EVSTAT2;
-	/* 0x010: Event Enable 2 */
-	volatile uint8_t EVENABLE2;
-	/* 0x011: SHI Configuration 6 - only in chips which support enhanced buffer mode */
-	volatile uint8_t SHICFG6;
-	/* 0x012: Single Byte Output Buffer - only in chips which support enhanced buffer mode */
-	volatile uint8_t SBOBUF;
-	volatile uint8_t reserved4[13];
-	/* 0x20~0x9F: Output Buffer */
-	volatile uint8_t OBUF[128];
-	/* 0xA0~0x11F: Input Buffer */
-	volatile uint8_t IBUF[128];
-};
-
-/* SHI register fields */
-#define NPCX_SHICFG1_EN                  0
-#define NPCX_SHICFG1_MODE                1
-#define NPCX_SHICFG1_WEN                 2
-#define NPCX_SHICFG1_AUTIBF              3
-#define NPCX_SHICFG1_AUTOBE              4
-#define NPCX_SHICFG1_DAS                 5
-#define NPCX_SHICFG1_CPOL                6
-#define NPCX_SHICFG1_IWRAP               7
-#define NPCX_SHICFG2_SIMUL               0
-#define NPCX_SHICFG2_BUSY                1
-#define NPCX_SHICFG2_ONESHOT             2
-#define NPCX_SHICFG2_SLWU                3
-#define NPCX_SHICFG2_REEN                4
-#define NPCX_SHICFG2_RESTART             5
-#define NPCX_SHICFG2_REEVEN              6
-#define NPCX_EVENABLE_OBEEN              0
-#define NPCX_EVENABLE_OBHEEN             1
-#define NPCX_EVENABLE_IBFEN              2
-#define NPCX_EVENABLE_IBHFEN             3
-#define NPCX_EVENABLE_EOREN              4
-#define NPCX_EVENABLE_EOWEN              5
-#define NPCX_EVENABLE_STSREN             6
-#define NPCX_EVENABLE_IBOREN             7
-#define NPCX_EVSTAT_OBE                  0
-#define NPCX_EVSTAT_OBHE                 1
-#define NPCX_EVSTAT_IBF                  2
-#define NPCX_EVSTAT_IBHF                 3
-#define NPCX_EVSTAT_EOR                  4
-#define NPCX_EVSTAT_EOW                  5
-#define NPCX_EVSTAT_STSR                 6
-#define NPCX_EVSTAT_IBOR                 7
-#define NPCX_STATUS_OBES                 6
-#define NPCX_STATUS_IBFS                 7
-#define NPCX_SHICFG3_OBUFLVLDIS          7
-#define NPCX_SHICFG4_IBUFLVLDIS          7
-#define NPCX_SHICFG5_IBUFLVL2            FIELD(0, 6)
-#define NPCX_SHICFG5_IBUFLVL2DIS         7
-#define NPCX_EVSTAT2_IBHF2               0
-#define NPCX_EVSTAT2_CSNRE               1
-#define NPCX_EVSTAT2_CSNFE               2
-#define NPCX_EVENABLE2_IBHF2EN           0
-#define NPCX_EVENABLE2_CSNREEN           1
-#define NPCX_EVENABLE2_CSNFEEN           2
-#define NPCX_SHICFG6_EBUFMD              0
-#define NPCX_SHICFG6_OBUF_SL             1
-
-#define IBF_IBHF_EN_MASK                 (BIT(NPCX_EVENABLE_IBFEN) | BIT(NPCX_EVENABLE_IBHFEN))
-
-/* SPIP (SPI Peripheral Interface) registers */
-struct spip_reg {
-	/* 0x000: SPIP Data In/Out */
-	volatile uint16_t SPIP_DATA;
-	/* 0x002: SPIP Control 1 */
-	volatile uint16_t SPIP_CTL1;
-	/* 0x004: SPIP Status */
-	volatile uint8_t SPIP_STAT;
-	volatile uint8_t reserved1;
-};
-
-#define NPCX_SPIP_CTL1_SPIEN            0
-#define NPCX_SPIP_CTL1_MOD              2
-#define NPCX_SPIP_CTL1_EIR              5
-#define NPCX_SPIP_CTL1_EIW              6
-#define NPCX_SPIP_CTL1_SCM              7
-#define NPCX_SPIP_CTL1_SCIDL            8
-#define NPCX_SPIP_CTL1_SCDV             FIELD(9, 7)
-#define NPCX_SPIP_STAT_BSY              0
-#define NPCX_SPIP_STAT_RBF              1
-
-/* Software-triggered Pheripheral Reset Controller Register */
-struct swrst_reg {
-	/* 0x000: Software Reset Trigger */
-	volatile uint16_t SWRST_TRG;
-	volatile uint8_t reserved1[2];
-	volatile uint32_t SWRST_CTL[4];
-};
-
-/* Improved Inter Integrated Circuit  (I3C) device registers */
-struct i3c_reg {
-	/* 0x000: Controller Configuration */
-	volatile uint32_t MCONFIG;
-	/* 0x004: Target Configuration */
-	volatile uint32_t CONFIG;
-	/* 0x008: Target Status */
-	volatile uint32_t STATUS;
-	/* 0x00C: Target Control  */
-	volatile uint32_t CTRL;
-	/* 0x010: Target Interrupt Enable Set  */
-	volatile uint32_t INTSET;
-	/* 0x014: Target Interrupt Enable Clear */
-	volatile uint32_t INTCLR;
-	/* 0x018: Target Interrupt Masked */
-	volatile uint32_t INTMASKED;
-	/* 0x01C: Target Error and Warning */
-	volatile uint32_t ERRWARN;
-	/* 0x020: Target DMA Control */
-	volatile uint32_t DMACTRL;
-	/* 0x024-0x02B: reserved */
-	volatile uint32_t reserved0[2];
-	/* 0x02C: Target Data Control */
-	volatile uint32_t DATACTRL;
-	/* 0x030: Target Write Byte Data */
-	volatile uint32_t WDATAB;
-	/* 0x034: Target Write Byte Data as End */
-	volatile uint32_t WDATABE;
-	/* 0x038: Target Write Half-Word Data */
-	volatile uint32_t WDATAH;
-	/* 0x03C: Target Write Half-Word Data as End */
-	volatile uint32_t WDATAHE;
-	/* 0x040: Target Read Byte Data */
-	volatile uint32_t RDATAB;
-	/* 0x044: reserved */
-	volatile uint32_t reserved1;
-	/* 0x048: Target Read Half-Word Data */
-	volatile uint32_t RDATAH;
-	/* 0x04C-0x05B: reserved */
-	volatile uint32_t reserved2[4];
-	/* 0x05C: Target Capabilities 2 */
-	volatile uint32_t CCAPABILITIES2;
-	/* 0x060: Target Capabilities */
-	volatile uint32_t CCAPABILITIES;
-	/* 0x064: Target Dynamic Address */
-	volatile uint32_t DYNADDR;
-	/* 0x068: Target Maximum Limits */
-	volatile uint32_t MAXLIMITS;
-	/* 0x06C: Target Part Number */
-	volatile uint32_t PARTNO;
-	/* 0x070: Target ID Extension */
-	volatile uint32_t IDEXT;
-	/* 0x074: Target Vendor ID */
-	volatile uint32_t VENDORID;
-	/* 0x078: Target Timing Control Clock */
-	volatile uint32_t TCCLOCK;
-	/* 0x07C: Target Matching Address Index */
-	volatile uint32_t MSGLAST;
-	/* 0x080: reserved */
-	volatile uint32_t reserved3;
-	/* 0x084: Controller Control  */
-	volatile uint32_t MCTRL;
-	/* 0x088: Controller Status */
-	volatile uint32_t MSTATUS;
-	/* 0x08C: IBI Registry and Rules */
-	volatile uint32_t IBIRULES;
-	/* 0x090: Controller Interrupt Enable Set  */
-	volatile uint32_t MINTSET;
-	/* 0x094: Controller Interrupt Enable Clear */
-	volatile uint32_t MINTCLR;
-	/* 0x098: Controller Interrupt Masked */
-	volatile uint32_t MINTMASKED;
-	/* 0x09C: Controller Error and Warning */
-	volatile uint32_t MERRWARN;
-	/* 0x0A0: Controller DMA Control */
-	volatile uint32_t MDMACTRL;
-	/* 0x0A0-0x0AB: reserved */
-	volatile uint32_t reserved4[2];
-	/* 0x0AC: Controller Data Control */
-	volatile uint32_t MDATACTRL;
-	/* 0x0B0: Controller Write Byte Data */
-	volatile uint32_t MWDATAB;
-	/* 0x0B4: Controller Write Byte Data as End */
-	volatile uint32_t MWDATABE;
-	/* 0x0B8: Controller Write Half-Word Data */
-	volatile uint32_t MWDATAH;
-	/* 0x0BC: Controller Write Half-Word Data as End */
-	volatile uint32_t MWDATAHE;
-	/* 0x0C0: Controller Read Byte Data */
-	volatile uint32_t MRDATAB;
-	/* 0x0C4: reserved */
-	volatile uint32_t reserved5;
-	/* 0x0C8: Controller Read Half-Word Data */
-	volatile uint32_t MRDATAH;
-	/* 0x0CC-0x0D7: reserved */
-	volatile uint32_t reserved6[3];
-	/* 0x0D8: Start or Continue DDR Message */
-	volatile uint32_t MWMSG_DDR;
-	/* 0x0DC: Read DDR Message Data */
-	volatile uint32_t MRMSG_DDR;
-	/* 0x0E0: reserved */
-	volatile uint32_t reserved7;
-	/* 0x0E4: Controller Dynamic Address */
-	volatile uint32_t MDYNADDR;
-	/* 0x0E8-0x0FF reserved */
-	volatile uint32_t reserved8[6];
-	/* 0x100: Target Reset Recovery Time */
-	volatile uint32_t RSTACTTIME;
-	/* 0x104: reserved */
-	volatile uint32_t reserved9;
-	/* 0x108: Target HDR Command Byte */
-	volatile uint32_t HDRCMD;
-	/* 0x10C-0x113: reserved */
-	volatile uint32_t reserved10[2];
-	/* 0x114: Target Group Definition */
-	volatile uint32_t GROUPDEF;
-	/* 0x118: reserved */
-	volatile uint32_t reserved11;
-	/* 0x11C: Target Map Control 0 */
-	volatile uint32_t MAPCTRL0;
-	/* 0x120: Target Map Control 1 */
-	volatile uint32_t MAPCTRL1;
-	/* 0x124: Target Map Control 2 */
-	volatile uint32_t MAPCTRL2;
-	/* 0x128: Target Map Control 3 */
-	volatile uint32_t MAPCTRL3;
-	/* 0x12C: Target Map Control 4 */
-	volatile uint32_t MAPCTRL4;
-	/* 0x130: Target Map Control 5 */
-	volatile uint32_t MAPCTRL5;
-	/* 0x134: Target Map Control 6 */
-	volatile uint32_t MAPCTRL6;
-	/* 0x138: Target Map Control 7 */
-	volatile uint32_t MAPCTRL7;
-	/* 0x13C: Target Map Control 8 */
-	volatile uint32_t MAPCTRL8;
-	/* 0x140: Target Extended IBI Data 1 */
-	volatile uint32_t IBIEXT1;
-	/* 0x144: Target Extended IBI Data 2 */
-	volatile uint32_t IBIEXT2;
-};
-
-/* I3C controller register fields */
-#define NPCX_I3C_MCONFIG_CTRENA         FIELD(0, 2)
-#define NPCX_I3C_MCONFIG_DISTO          3
-#define NPCX_I3C_MCONFIG_HKEEP          FIELD(4, 2) /* Must be '11' */
-#define NPCX_I3C_MCONFIG_ODSTOP         6
-#define NPCX_I3C_MCONFIG_PPBAUD         FIELD(8, 4)
-#define NPCX_I3C_MCONFIG_PPLOW          FIELD(12, 4)
-#define NPCX_I3C_MCONFIG_ODBAUD         FIELD(16, 8)
-#define NPCX_I3C_MCONFIG_ODHPP          24
-#define NPCX_I3C_MCONFIG_SKEW           FIELD(25, 3)
-#define NPCX_I3C_MCONFIG_I2CBAUD        FIELD(28, 4)
-#define NPCX_I3C_MCTRL_REQUEST          FIELD(0, 3)
-#define NPCX_I3C_MCTRL_TYPE             FIELD(4, 2)
-#define NPCX_I3C_MCTRL_IBIRESP          FIELD(6, 2)
-#define NPCX_I3C_MCTRL_DIR              8
-#define NPCX_I3C_MCTRL_ADDR             FIELD(9, 7)
-#define NPCX_I3C_MCTRL_RDTERM           FIELD(16, 8)
-#define NPCX_I3C_MSTATUS_STATE          FIELD(0, 3)
-#define NPCX_I3C_MSTATUS_BETWEEN        4
-#define NPCX_I3C_MSTATUS_NACKED         5
-#define NPCX_I3C_MSTATUS_IBITYPE        FIELD(6, 2)
-#define NPCX_I3C_MSTATUS_TGTSTART       8
-#define NPCX_I3C_MSTATUS_MCTRLDONE      9
-#define NPCX_I3C_MSTATUS_COMPLETE       10
-#define NPCX_I3C_MSTATUS_RXPEND         11
-#define NPCX_I3C_MSTATUS_TXNOTFULL      12
-#define NPCX_I3C_MSTATUS_IBIWON         13
-#define NPCX_I3C_MSTATUS_ERRWARN        15
-#define NPCX_I3C_MSTATUS_NOWCNTLR       19
-#define NPCX_I3C_MSTATUS_IBIADDR        FIELD(24, 7)
-#define NPCX_I3C_IBIRULES_MSB0          30
-#define NPCX_I3C_IBIRULES_NOBYTE        31
-#define NPCX_I3C_MINTSET_TGTSTART       8
-#define NPCX_I3C_MINTSET_MCTRLDONE      9
-#define NPCX_I3C_MINTSET_COMPLETE       10
-#define NPCX_I3C_MINTSET_RXPEND         11
-#define NPCX_I3C_MINTSET_TXNOTFULL      12
-#define NPCX_I3C_MINTSET_IBIWON         13
-#define NPCX_I3C_MINTSET_ERRWARN        15
-#define NPCX_I3C_MINTSET_NOWCNTLR       19
-#define NPCX_I3C_MINTCLR_TGTSTART       8
-#define NPCX_I3C_MINTCLR_MCTRLDONE      9
-#define NPCX_I3C_MINTCLR_COMPLETE       10
-#define NPCX_I3C_MINTCLR_RXPEND         11
-#define NPCX_I3C_MINTCLR_TXNOTFULL      12
-#define NPCX_I3C_MINTCLR_IBIWON         13
-#define NPCX_I3C_MINTCLR_ERRWARN        15
-#define NPCX_I3C_MINTCLR_NOWCNTLR       19
-#define NPCX_I3C_MINTMASKED_NOWCNTLR    19
-#define NPCX_I3C_MDATACTRL_FLUSHTB      0
-#define NPCX_I3C_MDATACTRL_FLUSHFB      1
-#define NPCX_I3C_MDATACTRL_UNLOCK       3
-#define NPCX_I3C_MDATACTRL_TXTRIG       FIELD(4, 2)
-#define NPCX_I3C_MDATACTRL_RXTRIG       FIELD(6, 2)
-#define NPCX_I3C_MDATACTRL_TXCOUNT      FIELD(16, 5)
-#define NPCX_I3C_MDATACTRL_RXCOUNT      FIELD(24, 5)
-#define NPCX_I3C_MDATACTRL_TXFULL       30
-#define NPCX_I3C_MDATACTRL_RXEMPTY      31
-#define NPCX_I3C_MERRWARN_NACK          2
-#define NPCX_I3C_MERRWARN_WRABT         3
-#define NPCX_I3C_MERRWARN_TERM          4
-#define NPCX_I3C_MERRWARN_HPAR          9
-#define NPCX_I3C_MERRWARN_HCRC          10
-#define NPCX_I3C_MERRWARN_OREAD         16
-#define NPCX_I3C_MERRWARN_OWRITE        17
-#define NPCX_I3C_MERRWARN_MSGERR        18
-#define NPCX_I3C_MERRWARN_INVERQ        19
-#define NPCX_I3C_MERRWARN_TIMEOUT       20
-#define NPCX_I3C_MDMACTRL_DMAFB         FIELD(0, 2)
-#define NPCX_I3C_MDMACTRL_DMATB         FIELD(2, 2)
-
-/* I3C target register fields */
-#define NPCX_I3C_CONFIG_TGTENA          0
-#define NPCX_I3C_CONFIG_MATCHSS         2
-#define NPCX_I3C_CONFIG_S0IGNORE        3
-#define NPCX_I3C_CONFIG_IDRAND          8
-#define NPCX_I3C_CONFIG_OFFLINE         9
-#define NPCX_I3C_CONFIG_HDRCMD          FIELD(10, 2)
-#define NPCX_I3C_CONFIG_BAMATCH         FIELD(16, 7)
-#define NPCX_I3C_CONFIG_SADDR           FIELD(25, 7)
-#define NPCX_I3C_STATUS_STNOTSTOP       0
-#define NPCX_I3C_STATUS_STMSG           1
-#define NPCX_I3C_STATUS_STCCCH          2
-#define NPCX_I3C_STATUS_STREQRD         3
-#define NPCX_I3C_STATUS_STREQWR         4
-#define NPCX_I3C_STATUS_STDAA           5
-#define NPCX_I3C_STATUS_STHDR           6
-#define NPCX_I3C_STATUS_START           8
-#define NPCX_I3C_STATUS_MATCHED         9
-#define NPCX_I3C_STATUS_STOP            10
-#define NPCX_I3C_STATUS_RXPEND          11
-#define NPCX_I3C_STATUS_TXNOTFULL       12
-#define NPCX_I3C_STATUS_DACHG           13
-#define NPCX_I3C_STATUS_CCC             14
-#define NPCX_I3C_STATUS_ERRWARN         15
-#define NPCX_I3C_STATUS_HDRMATCH        16
-#define NPCX_I3C_STATUS_CHANDLED        17
-#define NPCX_I3C_STATUS_EVENT           18
-#define NPCX_I3C_STATUS_TGTRST          19
-#define NPCX_I3C_STATUS_EVDET           FIELD(20, 2)
-#define NPCX_I3C_STATUS_IBIDIS          24
-#define NPCX_I3C_STATUS_MRDIS           25
-#define NPCX_I3C_STATUS_HJDIS           27
-#define NPCX_I3C_STATUS_ACTSTATE        FIELD(28, 2)
-#define NPCX_I3C_STATUS_TIMECTRL        FIELD(30, 2)
-#define NPCX_I3C_CTRL_EVENT             FIELD(0, 2)
-#define NPCX_I3C_CTRL_EXTDATA           3
-#define NPCX_I3C_CTRL_MAPIDX            FIELD(4, 4)
-#define NPCX_I3C_CTRL_IBIDATA           FIELD(8, 8)
-#define NPCX_I3C_CTRL_PENDINT           FIELD(16, 4)
-#define NPCX_I3C_CTRL_ACTSTATE          FIELD(20, 2)
-#define NPCX_I3C_CTRL_VENDINFO          FIELD(24, 8)
-#define NPCX_I3C_INTSET_START           8
-#define NPCX_I3C_INTSET_MATCHED         9
-#define NPCX_I3C_INTSET_STOP            10
-#define NPCX_I3C_INTSET_RXPEND          11
-#define NPCX_I3C_INTSET_TXNOTFULL       12
-#define NPCX_I3C_INTSET_DACHG           13
-#define NPCX_I3C_INTSET_CCC             14
-#define NPCX_I3C_INTSET_ERRWARN         15
-#define NPCX_I3C_INTSET_HDRMATCH        16
-#define NPCX_I3C_INTSET_CHANDLED        17
-#define NPCX_I3C_INTSET_EVENT           18
-#define NPCX_I3C_INTSET_TGTRST          19
-#define NPCX_I3C_INTCLR_START           8
-#define NPCX_I3C_INTCLR_MATCHED         9
-#define NPCX_I3C_INTCLR_STOP            10
-#define NPCX_I3C_INTCLR_RXPEND          11
-#define NPCX_I3C_INTCLR_TXNOTFULL       12
-#define NPCX_I3C_INTCLR_DACHG           13
-#define NPCX_I3C_INTCLR_CCC             14
-#define NPCX_I3C_INTCLR_ERRWARN         15
-#define NPCX_I3C_INTCLR_HDRMATCH        16
-#define NPCX_I3C_INTCLR_CHANDLED        17
-#define NPCX_I3C_INTCLR_EVENT           18
-#define NPCX_I3C_INTCLR_TGTRST          19
-#define NPCX_I3C_INTMASKED_START        8
-#define NPCX_I3C_INTMASKED_MATCHED      9
-#define NPCX_I3C_INTMASKED_STOP         10
-#define NPCX_I3C_INTMASKED_RXPEND       11
-#define NPCX_I3C_INTMASKED_TXNOTFULL    12
-#define NPCX_I3C_INTMASKED_DACHG        13
-#define NPCX_I3C_INTMASKED_CCC          14
-#define NPCX_I3C_INTMASKED_ERRWARN      15
-#define NPCX_I3C_INTMASKED_HDRMATCH     16
-#define NPCX_I3C_INTMASKED_CHANDLED     17
-#define NPCX_I3C_INTMASKED_EVENT        18
-#define NPCX_I3C_INTMASKED_TGTRST       19
-#define NPCX_I3C_ERRWARN_ORUN           0
-#define NPCX_I3C_ERRWARN_URUN           1
-#define NPCX_I3C_ERRWARN_URUNNACK       2
-#define NPCX_I3C_ERRWARN_TERM           3
-#define NPCX_I3C_ERRWARN_INVSTART       4
-#define NPCX_I3C_ERRWARN_SPAR           8
-#define NPCX_I3C_ERRWARN_HPAR           9
-#define NPCX_I3C_ERRWARN_HCRC           10
-#define NPCX_I3C_ERRWARN_S0S1           11
-#define NPCX_I3C_ERRWARN_OREAD          16
-#define NPCX_I3C_ERRWARN_OWRITE         17
-#define NPCX_I3C_DMACTRL_DMAFB          FIELD(0, 2)
-#define NPCX_I3C_DMACTRL_DMATB          FIELD(2, 2)
-#define NPCX_I3C_DATACTRL_FLUSHTB       0
-#define NPCX_I3C_DATACTRL_FLUSHFB       1
-#define NPCX_I3C_DATACTRL_UNLOCK        3
-#define NPCX_I3C_DATACTRL_TXTRIG        FIELD(4, 2)
-#define NPCX_I3C_DATACTRL_RXTRIG        FIELD(6, 2)
-#define NPCX_I3C_DATACTRL_TXCOUNT       FIELD(16, 6)
-#define NPCX_I3C_DATACTRL_RXCOUNT       FIELD(24, 6)
-#define NPCX_I3C_DATACTRL_TXFULL        30
-#define NPCX_I3C_DATACTRL_RXEMPTY       31
-#define NPCX_I3C_WDATAB_DATA            FIELD(0, 8)
-#define NPCX_I3C_WDATAB_END_B           8
-#define NPCX_I3C_WDATAB_END_A           16
-#define NPCX_I3C_WDATABE_DATA           FIELD(0, 8)
-#define NPCX_I3C_WDATAH_DATA0           FIELD(0, 8)
-#define NPCX_I3C_WDATAH_DATA1           FIELD(8, 8)
-#define NPCX_I3C_WDATAH_END             16
-#define NPCX_I3C_WDATAHE_DATA0          FIELD(0, 8)
-#define NPCX_I3C_WDATAHE_DATA1          FIELD(8, 8)
-#define NPCX_I3C_RDATAB_DATA            FIELD(0, 8)
-#define NPCX_I3C_RDATAH_DATA0           FIELD(0, 8)
-#define NPCX_I3C_RDATAH_DATA1           FIELD(8, 8)
-#define NPCX_I3C_CAPABILITIES2_MAPCNT   FIELD(0, 4)
-#define NPCX_I3C_CAPABILITIES2_I2C10B   4
-#define NPCX_I3C_CAPABILITIES2_I2CRST   5
-#define NPCX_I3C_CAPABILITIES2_I2CDEVID 6
-#define NPCX_I3C_CAPABILITIES2_DATA32   7
-#define NPCX_I3C_CAPABILITIES2_IBIEXT   8
-#define NPCX_I3C_CAPABILITIES2_IBIXREG  9
-#define NPCX_I3C_CAPABILITIES2_SMLANE   FIELD(12, 2)
-#define NPCX_I3C_CAPABILITIES2_V1_1     16
-#define NPCX_I3C_CAPABILITIES2_TGTRST   17
-#define NPCX_I3C_CAPABILITIES2_GROUP    FIELD(18, 2)
-#define NPCX_I3C_CAPABILITIES2_AASA     21
-#define NPCX_I3C_CAPABILITIES2_SSTSUB   22
-#define NPCX_I3C_CAPABILITIES2_SSTWR    23
-#define NPCX_I3C_CAPABILITIES_IDENA     FIELD(0, 2)
-#define NPCX_I3C_CAPABILITIES_IDREG     FIELD(2, 4)
-#define NPCX_I3C_CAPABILITIES_HDRSUPP   FIELD(6, 3)
-#define NPCX_I3C_CAPABILITIES_CNTLR     9
-#define NPCX_I3C_CAPABILITIES_SADDR     FIELD(10, 2)
-#define NPCX_I3C_CAPABILITIES_CCCHANDLE FIELD(12, 4)
-#define NPCX_I3C_CAPABILITIES_IBI_MR_HJ FIELD(16, 5)
-#define NPCX_I3C_CAPABILITIES_TIMECTRL  21
-#define NPCX_I3C_CAPABILITIES_EXTFIFO   FIELD(23, 3)
-#define NPCX_I3C_CAPABILITIES_FIFOTX    FIELD(26, 2)
-#define NPCX_I3C_CAPABILITIES_FIFORX    FIELD(28, 2)
-#define NPCX_I3C_CAPABILITIES_INT       30
-#define NPCX_I3C_CAPABILITIES_DMA       31
-#define NPCX_I3C_DYNADDR_DAVALID        0
-#define NPCX_I3C_DYNADDR_DADDR          FIELD(1, 7)
-#define NPCX_I3C_DYNADDR_CAUSE          FIELD(8, 3)
-#define NPCX_I3C_MAXLIMITS_MAXRD        FIELD(0, 12)
-#define NPCX_I3C_MAXLIMITS_MAXWR        FIELD(16, 12)
-#define NPCX_I3C_IDEXT_DCR              FIELD(8, 8)
-#define NPCX_I3C_IDEXT_BCR              FIELD(16, 8)
-#define NPCX_I3C_VENDORID_VID           FIELD(0, 15)
-#define NPCX_I3C_TCCLOCK_ACCURACY       FIELD(0, 8)
-#define NPCX_I3C_TCCLOCK_FREQ           FIELD(8, 8)
-#define NPCX_I3C_MSGLAST_MAPLAST        FIELD(0, 4)
-#define NPCX_I3C_MSGLAST_LASTSTATIC     4
-#define NPCX_I3C_MSGLAST_LASTGROUP      5
-#define NPCX_I3C_MSGLAST_LASTMODE       FIELD(6, 2)
-#define NPCX_I3C_MSGLAST_MAPLASTM1      FIELD(8, 4)
-#define NPCX_I3C_MSGLAST_LASTGROUPM1    13
-#define NPCX_I3C_MSGLAST_LASTMODE1      FIELD(14, 2)
-#define NPCX_I3C_MSGLAST_MAPLASTM2      FIELD(16, 4)
-#define NPCX_I3C_MSGLAST_LASTGROUPM2    21
-#define NPCX_I3C_MSGLAST_LASTMODE2      FIELD(22, 2)
-#define NPCX_I3C_RSTACTTIME_PERRSTTIM   FIELD(0, 8)
-#define NPCX_I3C_RSTACTTIME_SYSRSTTIM   FIELD(8, 8)
-#define NPCX_I3C_HDRCMD_CMD0            FIELD(0, 8)
-#define NPCX_I3C_HDRCMD_OVFL            30
-#define NPCX_I3C_HDRCMD_NEWCMD          31
-#define NPCX_I3C_GROUPDEF_GRP0ENA       0
-#define NPCX_I3C_GROUPDEF_GRP0DA        FIELD(1, 7)
-#define NPCX_I3C_GROUPDEF_GRP1ENA       8
-#define NPCX_I3C_GROUPDEF_GRP1DA        FIELD(9, 7)
-#define NPCX_I3C_GROUPDEF_GRP2ENA       16
-#define NPCX_I3C_GROUPDEF_GRP2DA        FIELD(17, 7)
-#define NPCX_I3C_MAPCTRL0_ENA           0
-#define NPCX_I3C_MAPCTRL0_DA            FIELD(1, 7)
-#define NPCX_I3C_MAPCTRL0_CAUSE         FIELD(8, 3)
-#define NPCX_I3C_MAPCTRLn_ENA           0
-#define NPCX_I3C_MAPCTRLn_ADDR          FIELD(1, 7)
-#define NPCX_I3C_MAPCTRLn_MAPSA         8
-#define NPCX_I3C_MAPCTRLn_NACK          12
-#define NPCX_I3C_MAPCTRLn_AUTO          13
-#define NPCX_I3C_MAPCTRLn_SLOT_PID      FIELD(14, 5)
-#define NPCX_I3C_IBIEXT1_CNT            FIELD(0, 3)
-#define NPCX_I3C_IBIEXT1_EXT1           FIELD(8, 8)
-#define NPCX_I3C_IBIEXT1_EXT2           FIELD(16, 8)
-#define NPCX_I3C_IBIEXT1_EXT3           FIELD(24, 8)
-#define NPCX_I3C_IBIEXT2_EXT4           FIELD(0, 8)
-#define NPCX_I3C_IBIEXT2_EXT5           FIELD(8, 8)
-#define NPCX_I3C_IBIEXT2_EXT6           FIELD(16, 8)
-#define NPCX_I3C_IBIEXT2_EXT7           FIELD(24, 8)
-
-/* MDMA Controller registers */
-struct mdma_reg {
-	/* Channel 0 */
-	/* 0x000: Channel 0 Control */
-	volatile uint32_t MDMA_CTL0;
-	/* 0x004: Channel 0 Source Base Address */
-	volatile uint32_t MDMA_SRCB0;
-	/* 0x008: Channel 0 Destination Base Address */
-	volatile uint32_t MDMA_DSTB0;
-	/* 0x00C: Channel 0 Transfer Count */
-	volatile uint32_t MDMA_TCNT0;
-	/* 0x010: reserved1 */
-	volatile uint32_t reserved1;
-	/* 0x014: Channel 0 Current Destination */
-	volatile uint32_t MDMA_CDST0;
-	/* 0x018: Channel 0 Current Transfer Count */
-	volatile uint32_t MDMA_CTCNT0;
-	/* 0x01C: reserved2 */
-	volatile uint32_t reserved2;
-
-	/* Channel 1 */
-	/* 0x020: Channel 1 Control */
-	volatile uint32_t MDMA_CTL1;
-	/* 0x024: Channel 1 Source Base Address */
-	volatile uint32_t MDMA_SRCB1;
-	/* 0x028: Channel 1 Destination Base Address */
-	volatile uint32_t MDMA_DSTB1;
-	/* 0x02C: Channel 1 Transfer Count */
-	volatile uint32_t MDMA_TCNT1;
-	/* 0x030: Channel 1 Current Source */
-	volatile uint32_t MDMA_CSRC1;
-	/* 0x034: reserved3 */
-	volatile uint32_t reserved3;
-	/* 0x038: Channel 1 Current Transfer Count */
-	volatile uint32_t MDMA_CTCNT1;
-};
-
-/* MDMA register fields */
-#define NPCX_MDMA_CTL_MDMAEN 0
-#define NPCX_MDMA_CTL_MPD    1
-#define NPCX_MDMA_CTL_SIEN   8
-#define NPCX_MDMA_CTL_MPS    14
-#define NPCX_MDMA_CTL_TC     18
-
-/* Channel 0/1 Transfer Count Register (MDMA_TCNT0/MDMA_TCNT1) */
-#define NPCX_MDMA_TCNT_TFR_CNT FIELD(0, 13)
-
-/* Channel 0/1 Current Transfer Count Register (MDMA_CTCNT0/MDMA_CTCNT1) */
-#define NPCX_MDMA_CTCNT_CURRENT_TFR_CNT FIELD(0, 13)
-
-#endif /* _NUVOTON_NPCX_REG_DEF_H */
diff --git a/soc/nuvoton/npcx/common/reg_access.h b/soc/nuvoton/npcx/common/reg_access.h
new file mode 100644
index 00000000000..69e7e000329
--- /dev/null
+++ b/soc/nuvoton/npcx/common/reg_access.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2020 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _NUVOTON_NPCX_REG_ACCESS_H
+#define _NUVOTON_NPCX_REG_ACCESS_H
+
+/*
+ * NPCX register structure size/offset checking macro function to mitigate
+ * the risk of unexpected compiling results. All addresses of NPCX registers
+ * must meet the alignment requirement of cortex-m4.
+ * DO NOT use 'packed' attribute if module contains different length ie.
+ * 8/16/32 bits registers.
+ */
+#define NPCX_REG_SIZE_CHECK(reg_def, size)                                                         \
+	BUILD_ASSERT(sizeof(struct reg_def) == size, "Failed in size check of register "           \
+						     "structure!")
+#define NPCX_REG_OFFSET_CHECK(reg_def, member, offset)                                             \
+	BUILD_ASSERT(offsetof(struct reg_def, member) == offset,                                   \
+		     "Failed in offset check of register structure member!")
+
+/*
+ * NPCX register access checking via structure macro function to mitigate the
+ * risk of unexpected compiling results if module contains different length
+ * registers. For example, a word register access might break into two byte
+ * register accesses by adding 'packed' attribute.
+ *
+ * For example, add this macro for word register 'PRSC' of PWM module in its
+ * device init function for checking violation. Once it occurred, core will be
+ * stalled forever and easy to find out what happens.
+ */
+#define NPCX_REG_WORD_ACCESS_CHECK(reg, val)                                                       \
+	{                                                                                          \
+		uint16_t placeholder = reg;                                                        \
+		reg = val;                                                                         \
+		__ASSERT(reg == val, "16-bit reg access failed!");                                 \
+		reg = placeholder;                                                                 \
+	}
+#define NPCX_REG_DWORD_ACCESS_CHECK(reg, val)                                                      \
+	{                                                                                          \
+		uint32_t placeholder = reg;                                                        \
+		reg = val;                                                                         \
+		__ASSERT(reg == val, "32-bit reg access failed!");                                 \
+		reg = placeholder;                                                                 \
+	}
+
+/*
+ * NPCX register bit/field access operations
+ */
+
+#define GET_POS_FIELD(pos, size)  pos
+#define GET_SIZE_FIELD(pos, size) size
+#define FIELD_POS(field)          GET_POS_##field
+#define FIELD_SIZE(field)         GET_SIZE_##field
+
+#define GET_FIELD(reg, field)           _GET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field))
+#define _GET_FIELD_(reg, f_pos, f_size) (((reg) >> (f_pos)) & ((1 << (f_size)) - 1))
+
+#define SET_FIELD(reg, field, value) _SET_FIELD_(reg, FIELD_POS(field), FIELD_SIZE(field), value)
+#define _SET_FIELD_(reg, f_pos, f_size, value)                                                     \
+	((reg) = ((reg) & (~(((1 << (f_size)) - 1) << (f_pos)))) | ((value) << (f_pos)))
+
+#define GET_FIELD_POS(field)   _GET_FIELD_POS_(FIELD_POS(field))
+#define _GET_FIELD_POS_(f_ops) f_ops
+
+#define GET_FIELD_SZ(field)   _GET_FIELD_SZ_(FIELD_SIZE(field))
+#define _GET_FIELD_SZ_(f_ops) f_ops
+
+#endif /* _NUVOTON_NPCX_REG_ACCESS_H */
diff --git a/soc/nuvoton/npcx/common/scfg.c b/soc/nuvoton/npcx/common/scfg.c
index b57476225bb..b29d7356b55 100644
--- a/soc/nuvoton/npcx/common/scfg.c
+++ b/soc/nuvoton/npcx/common/scfg.c
@@ -105,6 +105,35 @@ void npcx_pinctrl_i2c_port_sel(int controller, int port)
 	}
 }
 
+void npcx_i2c_target_start_wk_enable(int controller, bool enable)
+{
+	struct glue_reg *const inst_glue = HAL_GLUE_INST();
+
+	if (enable) {
+		/* Clear Start condition detection status */
+		inst_glue->SMB_SBD |= BIT(controller);
+		/* Enable wake up event assertion */
+		inst_glue->SMB_EEN |= BIT(controller);
+	} else {
+		/* Disable wake up event assertion */
+		inst_glue->SMB_EEN &= ~BIT(controller);
+	}
+}
+
+void npcx_i2c_target_clear_detection_event(void)
+{
+	struct glue_reg *const inst_glue = HAL_GLUE_INST();
+	uint8_t een = inst_glue->SMB_EEN;
+	uint8_t sbd = inst_glue->SMB_SBD;
+
+	/* Clear Start condition detection status */
+	for (uint8_t i = 0; i < 8; i++) {
+		if ((een & BIT(i)) != 0 && (sbd & BIT(i)) != 0) {
+			inst_glue->SMB_SBD |= BIT(i);
+		}
+	}
+}
+
 int npcx_pinctrl_flash_write_protect_set(void)
 {
 	struct scfg_reg *inst_scfg = HAL_SFCG_INST();
diff --git a/soc/nuvoton/npcx/common/soc_clock.h b/soc/nuvoton/npcx/common/soc_clock.h
index 4ec4c591b04..314a7b5b902 100644
--- a/soc/nuvoton/npcx/common/soc_clock.h
+++ b/soc/nuvoton/npcx/common/soc_clock.h
@@ -26,16 +26,16 @@ extern "C" {
  * register/bit to turn on/off its source clock.
  */
 struct npcx_clk_cfg {
-	uint16_t bus:8;
-	uint16_t ctrl:5;
-	uint16_t bit:3;
+	uint16_t bus: 8;
+	uint16_t ctrl: 5;
+	uint16_t bit: 3;
 };
 
 /* Clock settings from pcc node */
 /* Target OFMCLK freq */
-#define OFMCLK DT_PROP(DT_NODELABEL(pcc), clock_frequency)
+#define OFMCLK      DT_PROP(DT_NODELABEL(pcc), clock_frequency)
 /* Core clock prescaler */
-#define FPRED_VAL (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
+#define FPRED_VAL   (DT_PROP(DT_NODELABEL(pcc), core_prescaler) - 1)
 /* APB1 clock divider */
 #define APB1DIV_VAL (DT_PROP(DT_NODELABEL(pcc), apb1_prescaler) - 1)
 /* APB2 clock divider */
@@ -53,8 +53,8 @@ struct npcx_clk_cfg {
 
 /* Construct a uint8_t array from 'pwdwn-ctl-val' prop for PWDWN_CTL initialization. */
 #define NPCX_PWDWN_CTL_ITEMS_INIT(node, prop, idx) DT_PROP_BY_IDX(node, prop, idx),
-#define NPCX_PWDWN_CTL_INIT DT_FOREACH_PROP_ELEM(DT_NODELABEL(pcc), \
-				pwdwn_ctl_val, NPCX_PWDWN_CTL_ITEMS_INIT)
+#define NPCX_PWDWN_CTL_INIT                                                                        \
+	DT_FOREACH_PROP_ELEM(DT_NODELABEL(pcc), pwdwn_ctl_val, NPCX_PWDWN_CTL_ITEMS_INIT)
 
 /*
  * NPCX7 and later series clock tree macros:
@@ -71,105 +71,7 @@ struct npcx_clk_cfg {
 /* Core domain clock */
 #define CORE_CLK (OFMCLK / DT_PROP(DT_NODELABEL(pcc), core_prescaler))
 /* Low Frequency clock */
-#define LFCLK 32768
-
-/* FMUL clock */
-#if (OFMCLK > (MAX_OFMCLK / 2))
-#define FMCLK (OFMCLK / 2) /* FMUL clock = OFMCLK/2 */
-#else
-#define FMCLK OFMCLK /* FMUL clock = OFMCLK */
-#endif
-
-/* APBs source clock */
-#define APBSRC_CLK OFMCLK
-
-/* AHB6 clock */
-#if (CORE_CLK > (MAX_OFMCLK / 2))
-#define AHB6DIV_VAL 1 /* AHB6_CLK = CORE_CLK/2 */
-#else
-#define AHB6DIV_VAL 0 /* AHB6_CLK = CORE_CLK */
-#endif
-
-/* FIU clock divider */
-#if (CORE_CLK > (MAX_OFMCLK / 2))
-#define FIUDIV_VAL 1 /* FIU_CLK = CORE_CLK/2 */
-#else
-#define FIUDIV_VAL 0 /* FIU_CLK = CORE_CLK */
-#endif
-
-#if defined(CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1)
-#if (CORE_CLK > (MAX_OFMCLK / 2))
-#define FIU1DIV_VAL 1 /* FIU1_CLK = CORE_CLK/2 */
-#else
-#define FIU1DIV_VAL 0 /* FIU1_CLK = CORE_CLK */
-#endif
-#endif /* CONFIG_CLOCK_CONTROL_NPCX_SUPP_FIU1 */
-
-/* I3C clock divider */
-#if (OFMCLK == MHZ(120)) /* MCLkD must between 40 mhz to 50 mhz*/
-#define MCLKD_SL 2    /* I3C_CLK = (MCLK / 3) */
-#elif (OFMCLK <= MHZ(100) && OFMCLK >= MHZ(80))
-#define MCLKD_SL 1    /* I3C_CLK = (MCLK / 2) */
-#else
-#define MCLKD_SL 0    /* I3C_CLK = MCLK */
-#endif
-
-
-/* Get APB clock freq */
-#define NPCX_APB_CLOCK(no) (APBSRC_CLK / (APB##no##DIV_VAL + 1))
-
-/*
- * Frequency multiplier M/N value definitions according to the requested
- * OFMCLK (Unit:Hz).
- */
-#if (OFMCLK > (MAX_OFMCLK / 2))
-#define HFCGN_VAL    0x82 /* Set XF_RANGE as 1 */
-#else
-#define HFCGN_VAL    0x02
-#endif
-#if   (OFMCLK == 120000000)
-#define HFCGMH_VAL   0x0E
-#define HFCGML_VAL   0x4E
-#elif (OFMCLK == 100000000)
-#define HFCGMH_VAL   0x0B
-#define HFCGML_VAL   0xEC
-#elif (OFMCLK == 96000000)
-#define HFCGMH_VAL   0x0B
-#define HFCGML_VAL   0x72
-#elif (OFMCLK == 90000000)
-#define HFCGMH_VAL   0x0A
-#define HFCGML_VAL   0xBA
-#elif (OFMCLK == 80000000)
-#define HFCGMH_VAL   0x09
-#define HFCGML_VAL   0x89
-#elif (OFMCLK == 66000000)
-#define HFCGMH_VAL   0x07
-#define HFCGML_VAL   0xDE
-#elif (OFMCLK == 50000000)
-#define HFCGMH_VAL   0x0B
-#define HFCGML_VAL   0xEC
-#elif (OFMCLK == 48000000)
-#define HFCGMH_VAL   0x0B
-#define HFCGML_VAL   0x72
-#else
-#error "Unsupported OFMCLK Frequency"
-#endif
-
-/* Clock prescaler configurations in different series */
-#define VAL_HFCGP   ((FPRED_VAL << 4) | AHB6DIV_VAL)
-#if defined(FIU1DIV_VAL)
-#define VAL_HFCBCD  ((FIU1DIV_VAL << 4) | (FIUDIV_VAL << 2))
-#else
-#define VAL_HFCBCD  (FIUDIV_VAL << 4)
-#endif /* FIU1DIV_VAL */
-#define VAL_HFCBCD1 (APB1DIV_VAL | (APB2DIV_VAL << 4))
-#if defined(APB4DIV_VAL)
-#define VAL_HFCBCD2 (APB3DIV_VAL | (APB4DIV_VAL << 4))
-#else
-#define VAL_HFCBCD2 APB3DIV_VAL
-#endif /* APB4DIV_VAL */
-/* I3C1~I3C3 share the same configuration */
-#define VAL_HFCBCD3 MCLKD_SL
+#define LFCLK    32768
 
 /**
  * @brief Function to notify clock driver that backup the counter value of
diff --git a/soc/nuvoton/npcx/common/soc_espi_taf.h b/soc/nuvoton/npcx/common/soc_espi_taf.h
index f4a80a22896..4169f2c6ee5 100644
--- a/soc/nuvoton/npcx/common/soc_espi_taf.h
+++ b/soc/nuvoton/npcx/common/soc_espi_taf.h
@@ -151,6 +151,8 @@ struct npcx_taf_head {
 
 int npcx_init_taf(const struct device *dev, sys_slist_t *callbacks);
 
+int espi_taf_npcx_block(const struct device *dev, bool en_block);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/soc/nuvoton/npcx/common/soc_pins.h b/soc/nuvoton/npcx/common/soc_pins.h
index 143aad6b58d..3f057266fa0 100644
--- a/soc/nuvoton/npcx/common/soc_pins.h
+++ b/soc/nuvoton/npcx/common/soc_pins.h
@@ -9,7 +9,7 @@
 
 #include <stdint.h>
 
-#include "reg/reg_def.h"
+#include "reg_def.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -94,6 +94,20 @@ void npcx_host_interface_sel(enum npcx_hif_type hif_type);
  */
 void npcx_i3c_target_sel(uint8_t module, bool enable);
 
+/**
+ * @brief Enable smb controller wake up event detection in target mode
+ *
+ * @param controller i2c controller device
+ * @param enable True to enable wake up event detection, false to disable.
+ */
+void npcx_i2c_target_start_wk_enable(int controller, bool enable);
+
+/**
+ * @brief Clear  wake up event detection status in target mode
+ *
+ */
+void npcx_i2c_target_clear_detection_event(void);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/soc/nuvoton/npcx/npcx4/Kconfig.defconfig b/soc/nuvoton/npcx/npcx4/Kconfig.defconfig
index 330f309e1a2..d30b62f3afe 100644
--- a/soc/nuvoton/npcx/npcx4/Kconfig.defconfig
+++ b/soc/nuvoton/npcx/npcx4/Kconfig.defconfig
@@ -6,7 +6,7 @@
 if SOC_SERIES_NPCX4
 
 config NUM_IRQS
-	default 128
+	default 86
 
 config CORTEX_M_SYSTICK
 	default !NPCX_ITIM_TIMER
diff --git a/soc/nuvoton/npcx/npcx4/Kconfig.soc b/soc/nuvoton/npcx/npcx4/Kconfig.soc
index e825bc7fc6f..940bf6c3bad 100644
--- a/soc/nuvoton/npcx/npcx4/Kconfig.soc
+++ b/soc/nuvoton/npcx/npcx4/Kconfig.soc
@@ -5,7 +5,7 @@
 
 config SOC_SERIES_NPCX4
 	bool
-	select SOC_FAMILY_NPCX
+	select NPCX_SOC_VARIANT_NPCXN
 	help
 	  Enable support for Nuvoton NPCX4 series
 
diff --git a/soc/nuvoton/npcx/npcx4/soc.h b/soc/nuvoton/npcx/npcx4/soc.h
index 4ada738102c..5f92e153c46 100644
--- a/soc/nuvoton/npcx/npcx4/soc.h
+++ b/soc/nuvoton/npcx/npcx4/soc.h
@@ -38,6 +38,7 @@
 
 /* NPCX4 FIU register fields */
 #define NPCX_FIU_EXT_CFG_SPI1_2DEV	6
+#define NPCX_FIU_EXT_CFG_LOW_DEV_NUM	7
 
 /* NPCX4 supported group mask of DEVALT_LK */
 #define NPCX_DEVALT_LK_GROUP_MASK \
@@ -49,10 +50,9 @@
 /* NPCX4 Clock Configuration */
 #define MAX_OFMCLK 120000000
 
-#include <reg/reg_access.h>
-#include <reg/reg_def.h>
+#include "reg_def.h"
+#include "clock_def.h"
 #include <soc_dt.h>
-#include <soc_clock.h>
 #include <soc_espi_taf.h>
 #include <soc_pins.h>
 #include <soc_power.h>
diff --git a/soc/nuvoton/npcx/npcx7/Kconfig.soc b/soc/nuvoton/npcx/npcx7/Kconfig.soc
index ca2bb268d23..ea7ac6f3479 100644
--- a/soc/nuvoton/npcx/npcx7/Kconfig.soc
+++ b/soc/nuvoton/npcx/npcx7/Kconfig.soc
@@ -5,7 +5,7 @@
 
 config SOC_SERIES_NPCX7
 	bool
-	select SOC_FAMILY_NPCX
+	select NPCX_SOC_VARIANT_NPCXN
 	help
 	  Enable support for Nuvoton NPCX7 series
 
diff --git a/soc/nuvoton/npcx/npcx7/soc.h b/soc/nuvoton/npcx/npcx7/soc.h
index 9b523ce1b8f..782db67bbad 100644
--- a/soc/nuvoton/npcx/npcx7/soc.h
+++ b/soc/nuvoton/npcx/npcx7/soc.h
@@ -42,10 +42,9 @@
 /* NPCX7 Clock configuration */
 #define MAX_OFMCLK 100000000
 
-#include <reg/reg_access.h>
-#include <reg/reg_def.h>
+#include "reg_def.h"
+#include "clock_def.h"
 #include <soc_dt.h>
-#include <soc_clock.h>
 #include <soc_pins.h>
 #include <soc_power.h>
 
diff --git a/soc/nuvoton/npcx/npcx9/Kconfig.soc b/soc/nuvoton/npcx/npcx9/Kconfig.soc
index c7abe79ffd4..3dc775d05b3 100644
--- a/soc/nuvoton/npcx/npcx9/Kconfig.soc
+++ b/soc/nuvoton/npcx/npcx9/Kconfig.soc
@@ -5,7 +5,7 @@
 
 config SOC_SERIES_NPCX9
 	bool
-	select SOC_FAMILY_NPCX
+	select NPCX_SOC_VARIANT_NPCXN
 	help
 	  Enable support for Nuvoton NPCX9 series
 
diff --git a/soc/nuvoton/npcx/npcx9/soc.h b/soc/nuvoton/npcx/npcx9/soc.h
index 2ce745650fb..566890ce952 100644
--- a/soc/nuvoton/npcx/npcx9/soc.h
+++ b/soc/nuvoton/npcx/npcx9/soc.h
@@ -47,10 +47,9 @@
 /* NPCX9 Clock configuration and limitation */
 #define MAX_OFMCLK 100000000
 
-#include <reg/reg_access.h>
-#include <reg/reg_def.h>
+#include "reg_def.h"
+#include "clock_def.h"
 #include <soc_dt.h>
-#include <soc_clock.h>
 #include <soc_pins.h>
 #include <soc_power.h>
 
diff --git a/soc/nuvoton/numaker/m55m1x/CMakeLists.txt b/soc/nuvoton/numaker/m55m1x/CMakeLists.txt
new file mode 100644
index 00000000000..c8a814f0ce5
--- /dev/null
+++ b/soc/nuvoton/numaker/m55m1x/CMakeLists.txt
@@ -0,0 +1,14 @@
+# Copyright (c) 2025 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(soc.c)
+
+zephyr_include_directories(.)
+
+zephyr_library_sources_ifdef(CONFIG_POWEROFF poweroff.c)
+
+zephyr_sources_ifdef(CONFIG_ARM_MPU mpu_regions.c)
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/nuvoton/numaker/m55m1x/Kconfig b/soc/nuvoton/numaker/m55m1x/Kconfig
new file mode 100644
index 00000000000..c97e9fbadb8
--- /dev/null
+++ b/soc/nuvoton/numaker/m55m1x/Kconfig
@@ -0,0 +1,24 @@
+# Copyright (c) 2025 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_M55M1X
+	select ARM
+	select CPU_CORTEX_M55
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_CORTEX_M_HAS_VTOR
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
+	select CPU_CORTEX_M_HAS_DWT
+	select ARMV8_1_M_PMU
+	select SOC_EARLY_INIT_HOOK
+	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
+	select HAS_POWEROFF
+
+config ARMV8_1_M_PMU_EVENTCNT
+	int
+	default 8 if SOC_SERIES_M55M1X
+
+config SOC_M55M1XXX
+	select HAS_NUMAKER_HAL
diff --git a/soc/nuvoton/numaker/m55m1x/Kconfig.defconfig b/soc/nuvoton/numaker/m55m1x/Kconfig.defconfig
new file mode 100644
index 00000000000..71e688e8cdd
--- /dev/null
+++ b/soc/nuvoton/numaker/m55m1x/Kconfig.defconfig
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_M55M1X
+
+rsource "Kconfig.defconfig.m55m1*"
+
+endif # SOC_SERIES_M55M1X
diff --git a/soc/nuvoton/numaker/m55m1x/Kconfig.defconfig.m55m1xxx b/soc/nuvoton/numaker/m55m1x/Kconfig.defconfig.m55m1xxx
new file mode 100644
index 00000000000..53f6d9d01e2
--- /dev/null
+++ b/soc/nuvoton/numaker/m55m1x/Kconfig.defconfig.m55m1xxx
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_M55M1XXX
+
+config NUM_IRQS
+	default 161
+
+endif # SOC_M55M1XXX
diff --git a/soc/nuvoton/numaker/m55m1x/Kconfig.soc b/soc/nuvoton/numaker/m55m1x/Kconfig.soc
new file mode 100644
index 00000000000..c533dc57a4c
--- /dev/null
+++ b/soc/nuvoton/numaker/m55m1x/Kconfig.soc
@@ -0,0 +1,19 @@
+# Copyright (c) 2025 Nuvoton Technology Corporation.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_M55M1X
+	bool
+	select SOC_FAMILY_NUMAKER
+	help
+	  Enable support for Nuvoton M55M1X MCU series
+
+config SOC_M55M1XXX
+	bool
+	select SOC_SERIES_M55M1X
+
+config SOC_SERIES
+	default "m55m1x" if SOC_SERIES_M55M1X
+
+config SOC
+	default "m55m1xxx" if SOC_M55M1XXX
diff --git a/soc/nuvoton/numaker/m55m1x/mpu_regions.c b/soc/nuvoton/numaker/m55m1x/mpu_regions.c
new file mode 100644
index 00000000000..33e59b71fba
--- /dev/null
+++ b/soc/nuvoton/numaker/m55m1x/mpu_regions.c
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2021 The Chromium OS Authors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
+
+static const struct arm_mpu_region mpu_regions[] = {
+	MPU_REGION_ENTRY("FLASH",
+			 CONFIG_FLASH_BASE_ADDRESS,
+			 REGION_FLASH_ATTR(CONFIG_FLASH_BASE_ADDRESS, CONFIG_FLASH_SIZE * 1024)),
+
+	MPU_REGION_ENTRY("SRAM",
+			 CONFIG_SRAM_BASE_ADDRESS,
+			 REGION_RAM_ATTR(CONFIG_SRAM_BASE_ADDRESS, CONFIG_SRAM_SIZE * 1024)),
+
+#if DT_NODE_EXISTS(DT_NODELABEL(itcm))
+	MPU_REGION_ENTRY("ITCM",
+			 DT_REG_ADDR(DT_NODELABEL(itcm)),
+			 REGION_RAM_ATTR(DT_REG_ADDR(DT_NODELABEL(itcm)),
+			 DT_REG_SIZE(DT_NODELABEL(itcm)))),
+#endif
+
+#if DT_NODE_EXISTS(DT_NODELABEL(dtcm))
+	MPU_REGION_ENTRY("DTCM",
+			 DT_REG_ADDR(DT_NODELABEL(dtcm)),
+			 REGION_RAM_ATTR(DT_REG_ADDR(DT_NODELABEL(dtcm)),
+			 DT_REG_SIZE(DT_NODELABEL(dtcm)))),
+#endif
+};
+
+const struct arm_mpu_config mpu_config = {
+	.num_regions = ARRAY_SIZE(mpu_regions),
+	.mpu_regions = mpu_regions,
+};
diff --git a/soc/nuvoton/numaker/m55m1x/poweroff.c b/soc/nuvoton/numaker/m55m1x/poweroff.c
new file mode 100644
index 00000000000..232da98fcab
--- /dev/null
+++ b/soc/nuvoton/numaker/m55m1x/poweroff.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2025 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/poweroff.h>
+#include <NuMicro.h>
+
+void z_sys_poweroff(void)
+{
+	SYS_UnlockReg();
+
+	/* Select Power-down mode */
+	PMC_SetPowerDownMode(DT_PROP_OR(DT_NODELABEL(scc), powerdown_mode, PMC_SPD0),
+			     PMC_PLCTL_PLSEL_PL0);
+
+	/* Clear all wake-up flag */
+	PMC->INTSTS |= PMC_INTSTS_CLRWK_Msk;
+
+	/* Enter to Power-down mode */
+	PMC_PowerDown();
+
+	k_cpu_idle();
+
+	CODE_UNREACHABLE;
+}
diff --git a/soc/nuvoton/numaker/m55m1x/sections.ld b/soc/nuvoton/numaker/m55m1x/sections.ld
new file mode 100644
index 00000000000..b60f3fcc0f5
--- /dev/null
+++ b/soc/nuvoton/numaker/m55m1x/sections.ld
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2020 Mario Jaun
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#if DT_NODE_EXISTS(DT_NODELABEL(dtcm))
+.dtcm_noinit (NOLOAD) : SUBALIGN(4)
+ {
+  __dtcm_noinit_start = .;
+  *(.dtcm_noinit)
+  *(".dtcm_noinit.*")
+  *(".kernel_noinit.*")
+  *(".noinit.*kernel/init.*")
+  *(".noinit.*kernel/mempool.*")
+  __dtcm_noinit_end = .;
+ } > DTCM
+#endif
diff --git a/soc/nuvoton/numaker/m55m1x/soc.c b/soc/nuvoton/numaker/m55m1x/soc.c
new file mode 100644
index 00000000000..19722c9058c
--- /dev/null
+++ b/soc/nuvoton/numaker/m55m1x/soc.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2025 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/init.h>
+#include <zephyr/cache.h>
+#include <zephyr/drivers/clock_control/clock_control_numaker.h>
+/* Hardware and starter kit includes. */
+#include <NuMicro.h>
+
+static void memory_setup(void)
+{
+	/* Enable SRAM1/2 functions are only available in secure mode. */
+	if (SCU_IS_CPU_NS(SCU_NS) == 0) {
+		uint32_t wait_cnt;
+
+		/* To assign __HIRC value directly before BSS initialization. */
+		SystemCoreClock = __HIRC;
+		wait_cnt = SystemCoreClock;
+
+		/* Unlock protected registers */
+		do {
+			SYS->REGLCTL = 0x59UL;
+			SYS->REGLCTL = 0x16UL;
+			SYS->REGLCTL = 0x88UL;
+		} while (SYS->REGLCTL == 0UL);
+
+		/* Switch SRAM1 to normal power mode */
+		if (PMC->SYSRB1PC != 0) {
+			PMC->SYSRB1PC = 0;
+		}
+
+		/* Switch SRAM2 to normal power mode */
+		if (PMC->SYSRB2PC != 0) {
+			PMC->SYSRB2PC = 0;
+		}
+
+		/* Wait SRAM1/2 power mode change finish */
+		while (1) {
+			if ((PMC->SYSRB1PC & PMC_SYSRB1PC_PCBUSY_Msk) == 0 &&
+			    (PMC->SYSRB2PC & PMC_SYSRB2PC_PCBUSY_Msk) == 0) {
+				break;
+			}
+
+			if (wait_cnt-- == 0) {
+				break;
+			}
+		}
+
+		/* Enable SRAM1/2 clock */
+		CLK->SRAMCTL |= (CLK_SRAMCTL_SRAM1CKEN_Msk | CLK_SRAMCTL_SRAM2CKEN_Msk);
+	}
+
+#if (defined(__FPU_PRESENT) && (__FPU_PRESENT == 1U))
+	/* Enable CP10 & CP11 Full Access */
+	SCB->CPACR |= ((3U << 10U * 2U) | (3U << 11U * 2U));
+
+	/* Set low-power state for PDEPU
+	 * 0b00  | ON, PDEPU is not in low-power state
+	 * 0b01  | ON, but the clock is off
+	 * 0b10  | RET(ention)
+	 * 0b11  | OFF
+	 * Clear ELPSTATE, value is 0b11 on Cold reset
+	 */
+	PWRMODCTL->CPDLPSTATE &= ~(PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk <<
+				   PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos);
+
+	/* PDEPU ON with clock off, value is 0b01 */
+	PWRMODCTL->CPDLPSTATE |= 0x1 << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos;
+#endif
+
+	/* Enable only if configured to do so. */
+	SCB_InvalidateICache();
+	sys_cache_instr_enable();
+
+	/* Enable d-cache only if configured to do so. */
+	SCB_InvalidateDCache();
+	sys_cache_data_enable();
+}
+
+void soc_early_init_hook(void)
+{
+	/* To ensure H/W I/O buffer with correct init data in SRAM,
+	 * to clean D-Cache here to let all .bss & .data flush to SRAM.
+	 */
+#ifdef CONFIG_DCACHE
+	SCB_CleanDCache();
+#endif
+
+	SystemInit();
+}
+
+void soc_reset_hook(void)
+{
+	memory_setup();
+
+	/* Unlock protected registers */
+	SYS_UnlockReg();
+
+	/* Release GPIO hold status */
+	PMC_RELEASE_GPIO();
+
+	/*
+	 * -------------------
+	 * Init System Clock
+	 * -------------------
+	 */
+
+#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hxt)
+	/* Enable/disable 4~24 MHz external crystal oscillator (HXT) */
+	if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_ENABLE) {
+		CLK_EnableXtalRC(CLK_SRCCTL_HXTEN_Msk);
+		/* Wait for HXT clock ready */
+		CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
+	} else if (DT_ENUM_IDX(DT_NODELABEL(scc), hxt) == NUMAKER_SCC_CLKSW_DISABLE) {
+		CLK_DisableXtalRC(CLK_SRCCTL_HXTEN_Msk);
+	}
+#endif
+
+#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), lxt)
+	/* Enable/disable 32.768 kHz low-speed external crystal oscillator (LXT) */
+	if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_ENABLE) {
+		CLK_EnableXtalRC(CLK_SRCCTL_LXTEN_Msk);
+		/* Wait for LXT clock ready */
+		CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
+	} else if (DT_ENUM_IDX(DT_NODELABEL(scc), lxt) == NUMAKER_SCC_CLKSW_DISABLE) {
+		CLK_DisableXtalRC(CLK_SRCCTL_LXTEN_Msk);
+	}
+#endif
+
+	/* Enable 12 MHz high-speed internal RC oscillator (HIRC) */
+	CLK_EnableXtalRC(CLK_SRCCTL_HIRCEN_Msk);
+	/* Wait for HIRC clock ready */
+	CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
+
+	/* Enable 32 KHz low-speed internal RC oscillator (LIRC) */
+	CLK_EnableXtalRC(CLK_SRCCTL_LIRCEN_Msk);
+	/* Wait for LIRC clock ready */
+	CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
+
+#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), hirc48)
+	/* Enable/disable 48 MHz high-speed internal RC oscillator (HIRC48) */
+	if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48) == NUMAKER_SCC_CLKSW_ENABLE) {
+		CLK_EnableXtalRC(CLK_SRCCTL_HIRC48MEN_Msk);
+		/* Wait for HIRC48 clock ready */
+		CLK_WaitClockReady(CLK_STATUS_HIRC48MSTB_Msk);
+	} else if (DT_ENUM_IDX(DT_NODELABEL(scc), hirc48) == NUMAKER_SCC_CLKSW_DISABLE) {
+		CLK_DisableXtalRC(CLK_SRCCTL_HIRC48MEN_Msk);
+	}
+#endif
+
+#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), clk_pclkdiv)
+	/* Set CLK_PCLKDIV register on request */
+	CLK->PCLKDIV = DT_PROP(DT_NODELABEL(scc), clk_pclkdiv);
+#endif
+
+#if DT_NODE_HAS_PROP(DT_NODELABEL(scc), core_clock)
+	/* Set core clock (HCLK) on request */
+	CLK_SetCoreClock(DT_PROP(DT_NODELABEL(scc), core_clock));
+#endif
+
+	/*
+	 * Update System Core Clock
+	 * User can use SystemCoreClockUpdate() to calculate SystemCoreClock.
+	 */
+	SystemCoreClockUpdate();
+
+	/* Lock protected registers */
+	SYS_LockReg();
+}
diff --git a/soc/nuvoton/numaker/m55m1x/soc.h b/soc/nuvoton/numaker/m55m1x/soc.h
new file mode 100644
index 00000000000..7582578c581
--- /dev/null
+++ b/soc/nuvoton/numaker/m55m1x/soc.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Nuvoton Technology Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_ARM_NUVOTON_M55M1X_SOC_H_
+#define ZEPHYR_SOC_ARM_NUVOTON_M55M1X_SOC_H_
+
+/* Hardware and starter kit includes. */
+#include <NuMicro.h>
+
+#endif /* ZEPHYR_SOC_ARM_NUVOTON_M55M1X_SOC_H_*/
diff --git a/soc/nuvoton/numaker/soc.yml b/soc/nuvoton/numaker/soc.yml
index ec1059c497f..e4bf9ad4f49 100644
--- a/soc/nuvoton/numaker/soc.yml
+++ b/soc/nuvoton/numaker/soc.yml
@@ -7,3 +7,6 @@ family:
   - name: m2l31x
     socs:
     - name: m2l31xxx
+  - name: m55m1x
+    socs:
+    - name: m55m1xxx
diff --git a/soc/nxp/common/Kconfig.xspi_xip b/soc/nxp/common/Kconfig.xspi_xip
new file mode 100644
index 00000000000..d087e8b2d2e
--- /dev/null
+++ b/soc/nxp/common/Kconfig.xspi_xip
@@ -0,0 +1,42 @@
+# Copyright 2024 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+DT_CHOSEN_Z_FLASH := zephyr,flash
+DT_COMPAT_XSPI := nxp,xspi
+
+DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
+DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))
+
+DT_FLASH_PARENT_IS_XSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_XSPI))
+DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \
+		if $(DT_FLASH_PARENT_IS_XSPI)
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+config FLASH_SIZE
+	default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb)
+
+config FLASH_MCUX_XSPI_XIP
+	bool
+	default $(DT_FLASH_PARENT_IS_XSPI)
+	select XIP
+	help
+	  Allows the soc to safely initialize the clocks for the
+	  XSpi when planning to execute code in XSpi Memory.
+
+if FLASH_MCUX_XSPI_XIP
+
+config CODE_DATA_RELOCATION_SRAM
+	default y
+
+config FLASH_MCUX_XSPI_XIP_MEM
+	string
+	prompt "Xspi drivers memory location"
+	default "RAM"
+	help
+	  Select the location to run the XSPI drivers when using
+	  the flash API.
+
+endif
diff --git a/soc/nxp/imx/imx6sx/soc.c b/soc/nxp/imx/imx6sx/soc.c
index 516c2e9bcf6..9377d2fd943 100644
--- a/soc/nxp/imx/imx6sx/soc.c
+++ b/soc/nxp/imx/imx6sx/soc.c
@@ -183,7 +183,7 @@ static void SOC_CacheInit(void)
 }
 
 /* Initialize clock. */
-static void SOC_ClockInit(void)
+void __weak SOC_ClockInit(void)
 {
 	/* OSC/PLL is already initialized by Cortex-A9 core */
 
diff --git a/soc/nxp/imx/imx7d/soc.c b/soc/nxp/imx/imx7d/soc.c
index 780c405a0bb..7b983897625 100644
--- a/soc/nxp/imx/imx7d/soc.c
+++ b/soc/nxp/imx/imx7d/soc.c
@@ -11,7 +11,7 @@
 #include "wdog_imx.h"
 
 /* Initialize clock. */
-void SOC_ClockInit(void)
+__weak void SOC_ClockInit(void)
 {
 	/* OSC/PLL is already initialized by Cortex-A7 (u-boot) */
 
diff --git a/soc/nxp/imx/imx8m/Kconfig b/soc/nxp/imx/imx8m/Kconfig
index 66b08e44700..6aa1acc6fe0 100644
--- a/soc/nxp/imx/imx8m/Kconfig
+++ b/soc/nxp/imx/imx8m/Kconfig
@@ -93,6 +93,9 @@ config SOC_MIMX8MQ6_M4
 config MCUX_CORE_SUFFIX
 	default "_ca53" if SOC_MIMX8MM6_A53 || SOC_MIMX8MN6_A53 || SOC_MIMX8ML8_A53
 	default "_dsp" if SOC_MIMX8ML8_ADSP
+	default "_cm4" if SOC_MIMX8MM6_M4
+	default "_cm7" if SOC_MIMX8ML8_M7
+	default "_cm4" if SOC_MIMX8MQ6_M4
 
 if SOC_MIMX8ML8_M7
 
diff --git a/soc/nxp/imx/imx8m/a53/pinctrl_soc.h b/soc/nxp/imx/imx8m/a53/pinctrl_soc.h
index 51e9e58b2f2..a1286f6f180 100644
--- a/soc/nxp/imx/imx8m/a53/pinctrl_soc.h
+++ b/soc/nxp/imx/imx8m/a53/pinctrl_soc.h
@@ -19,11 +19,18 @@ extern "C" {
 #define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT
 #define MCUX_IMX_BIAS_PULL_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT
 #define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT
-#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT
-#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT
 #define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
 #define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
 
+#if defined(CONFIG_SOC_MIMX8MM6_A53) || defined(CONFIG_SOC_MIMX8MN6_A53)
+/* fixed for DSE and FSEL for as there is one bit not used in these field */
+#define MCUX_IMX_SLEW_RATE_SHIFT (IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT + 1)
+#define MCUX_IMX_DRIVE_STRENGTH_SHIFT (IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT + 1)
+#else
+#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT
+#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT
+#endif
+
 #define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id)							\
 	((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) |	\
 	 (DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) |			\
diff --git a/soc/nxp/imx/imx8m/a53/soc.c b/soc/nxp/imx/imx8m/a53/soc.c
index a110213e2b6..7ad3b444ff5 100644
--- a/soc/nxp/imx/imx8m/a53/soc.c
+++ b/soc/nxp/imx/imx8m/a53/soc.c
@@ -45,6 +45,12 @@ static void soc_rdc_init(void)
 	periphConfig.policy = RDC_DT_VAL(enet);
 	RDC_SetPeriphAccessConfig(rdc_inst, &periphConfig);
 #endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c3)) && DT_NODE_HAS_PROP(DT_NODELABEL(i2c3), rdc)
+	periphConfig.periph = kRDC_Periph_I2C3;
+	periphConfig.policy = RDC_DT_VAL(i2c3);
+	RDC_SetPeriphAccessConfig(rdc_inst, &periphConfig);
+#endif
 }
 #else
 
@@ -52,7 +58,19 @@ static void soc_rdc_init(void)
 
 #endif
 
+__weak void soc_clock_init(void)
+{
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c3))
+	/* Set I2C source to SysPLL1 Div5 160MHZ */
+	CLOCK_SetRootMux(kCLOCK_RootI2c3, kCLOCK_I2cRootmuxSysPll1Div5);
+	/* Set root clock to 160MHZ / 10 = 16MHZ */
+	CLOCK_SetRootDivider(kCLOCK_RootI2c3, 1U, 10U);
+	CLOCK_EnableClock(kCLOCK_I2c3);
+#endif
+}
+
 void soc_prep_hook(void)
 {
 	soc_rdc_init();
+	soc_clock_init();
 }
diff --git a/soc/nxp/imx/imx8m/m4_mini/pinctrl_soc.h b/soc/nxp/imx/imx8m/m4_mini/pinctrl_soc.h
index ceb9d33eff0..754bf5826b6 100644
--- a/soc/nxp/imx/imx8m/m4_mini/pinctrl_soc.h
+++ b/soc/nxp/imx/imx8m/m4_mini/pinctrl_soc.h
@@ -19,8 +19,9 @@ extern "C" {
 #define MCUX_IMX_BIAS_PULL_UP_SHIFT IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT
 #define MCUX_IMX_BIAS_PULL_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_PE_SHIFT
 #define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT
-#define MCUX_IMX_SLEW_RATE_SHIFT IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT
-#define MCUX_IMX_DRIVE_STRENGTH_SHIFT IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT
+/* fixed for DSE and FSEL for as there is one bit not used in these field */
+#define MCUX_IMX_SLEW_RATE_SHIFT (IOMUXC_SW_PAD_CTL_PAD_FSEL_SHIFT + 1)
+#define MCUX_IMX_DRIVE_STRENGTH_SHIFT (IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT + 1)
 #define MCUX_IMX_INPUT_ENABLE_SHIFT 31 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
 #define MCUX_IMX_INPUT_ENABLE(x) ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
 
diff --git a/soc/nxp/imx/imx8m/m4_mini/soc.c b/soc/nxp/imx/imx8m/m4_mini/soc.c
index e9404f7b17f..6b01301c4bf 100644
--- a/soc/nxp/imx/imx8m/m4_mini/soc.c
+++ b/soc/nxp/imx/imx8m/m4_mini/soc.c
@@ -71,7 +71,7 @@ static const ccm_analog_frac_pll_config_t g_audioPll2Config = {
 	.postDiv = 1U, /* AUDIO PLL2 frequency  = 722534399HZ */
 };
 
-static void SOC_ClockInit(void)
+__weak void SOC_ClockInit(void)
 {
 	/*
 	 * Switch AHB NOC root to 24M first in order to configure
diff --git a/soc/nxp/imx/imx8m/m4_quad/soc.c b/soc/nxp/imx/imx8m/m4_quad/soc.c
index eea984fc172..c46b51a631a 100644
--- a/soc/nxp/imx/imx8m/m4_quad/soc.c
+++ b/soc/nxp/imx/imx8m/m4_quad/soc.c
@@ -46,7 +46,7 @@ static void SOC_RdcInit(void)
 	CLOCK_ControlGate(kCLOCK_VideoPll2Gate, kCLOCK_ClockNeededAll);
 }
 
-static void SOC_ClockInit(void)
+__weak void SOC_ClockInit(void)
 {
 	/*
 	 * Switch AHB NOC root to 25M first in order to configure
diff --git a/soc/nxp/imx/imx8m/m7/soc.c b/soc/nxp/imx/imx8m/m7/soc.c
index 7cd42b3bb5d..4a28224a2c2 100644
--- a/soc/nxp/imx/imx8m/m7/soc.c
+++ b/soc/nxp/imx/imx8m/m7/soc.c
@@ -80,7 +80,7 @@ const ccm_analog_integer_pll_config_t g_sysPll3Config = {
 	.postDiv = 2U, /*!< SYSTEM PLL3 frequency  = 600MHZ */
 };
 
-static void SOC_ClockInit(void)
+__weak void SOC_ClockInit(void)
 {
 	/*
 	 * The following steps just show how to configure the PLL clock sources using the clock
diff --git a/soc/nxp/imx/imx8ulp/adsp/linker.ld b/soc/nxp/imx/imx8ulp/adsp/linker.ld
index 45283cce03c..2f957819ae3 100644
--- a/soc/nxp/imx/imx8ulp/adsp/linker.ld
+++ b/soc/nxp/imx/imx8ulp/adsp/linker.ld
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023 NXP
+ * Copyright 2023-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -172,6 +172,13 @@ EXTERN(ext_man_fw_ver)
 SECTIONS
 {
 
+#ifdef CONFIG_OPENAMP_RSC_TABLE
+    SECTION_PROLOGUE(.resource_table,, SUBALIGN(4))
+    {
+      KEEP(*(.resource_table*))
+    } GROUP_LINK_IN(ROMABLE_REGION)
+#endif
+
 #include <zephyr/linker/rel-sections.ld>
 
 #ifdef CONFIG_LLEXT
diff --git a/soc/nxp/imx/imx9/CMakeLists.txt b/soc/nxp/imx/imx9/CMakeLists.txt
index 369519ad7b3..7c0803be807 100644
--- a/soc/nxp/imx/imx9/CMakeLists.txt
+++ b/soc/nxp/imx/imx9/CMakeLists.txt
@@ -1,7 +1,9 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
-if(CONFIG_SOC_MIMX9352)
+if(CONFIG_SOC_MIMX9131)
+  add_subdirectory(imx91)
+elseif(CONFIG_SOC_MIMX9352)
   add_subdirectory(imx93)
 elseif(CONFIG_SOC_MIMX9596)
   add_subdirectory(imx95)
diff --git a/soc/nxp/imx/imx9/imx91/CMakeLists.txt b/soc/nxp/imx/imx9/imx91/CMakeLists.txt
new file mode 100644
index 00000000000..4d342af6f13
--- /dev/null
+++ b/soc/nxp/imx/imx9/imx91/CMakeLists.txt
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+zephyr_compile_options(-Wno-misleading-indentation)
+
+zephyr_include_directories(.)
+
+zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/nxp/imx/imx9/imx91/Kconfig b/soc/nxp/imx/imx9/imx91/Kconfig
new file mode 100644
index 00000000000..a528effa490
--- /dev/null
+++ b/soc/nxp/imx/imx9/imx91/Kconfig
@@ -0,0 +1,12 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_MIMX9131
+	select ARM64
+	select CPU_CORTEX_A55
+	select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
+	select HAS_MCUX if CLOCK_CONTROL
+	select HAS_MCUX_CCM_REV2 if CLOCK_CONTROL
+	select HAS_MCUX_IOMUXC if PINCTRL
+	select HAS_MCUX_CACHE
+	select KERNEL_DIRECT_MAP if HAS_MCUX
diff --git a/soc/nxp/imx/imx9/imx91/Kconfig.defconfig b/soc/nxp/imx/imx9/imx91/Kconfig.defconfig
new file mode 100644
index 00000000000..1f176ff4748
--- /dev/null
+++ b/soc/nxp/imx/imx9/imx91/Kconfig.defconfig
@@ -0,0 +1,8 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_IMX9
+
+rsource "Kconfig.defconfig.*"
+
+endif # SOC_SERIES_IMX9
diff --git a/soc/nxp/imx/imx9/imx91/Kconfig.defconfig.mimx91 b/soc/nxp/imx/imx9/imx91/Kconfig.defconfig.mimx91
new file mode 100644
index 00000000000..748117545f0
--- /dev/null
+++ b/soc/nxp/imx/imx9/imx91/Kconfig.defconfig.mimx91
@@ -0,0 +1,21 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MIMX9131
+
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_Z_FLASH := zephyr,flash
+
+config FLASH_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+config NUM_IRQS
+	default 300
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 24000000
+
+endif
diff --git a/soc/nxp/imx/imx9/imx91/Kconfig.soc b/soc/nxp/imx/imx9/imx91/Kconfig.soc
new file mode 100644
index 00000000000..a3a063740cd
--- /dev/null
+++ b/soc/nxp/imx/imx9/imx91/Kconfig.soc
@@ -0,0 +1,21 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_MIMX9131
+	bool
+	select SOC_SERIES_IMX9
+	help
+	  NXP i.MX91
+
+config SOC_PART_NUMBER_MIMX9131CVVXJ
+	bool
+
+config SOC_PART_NUMBER_MIMX9131DVVXJ
+	bool
+
+config SOC_PART_NUMBER
+	default "MIMX9131CVVXJ" if SOC_PART_NUMBER_MIMX9131CVVXJ
+	default "MIMX9131DVVXJ" if SOC_PART_NUMBER_MIMX9131DVVXJ
+
+config SOC
+	default "mimx9131" if SOC_MIMX9131
diff --git a/soc/nxp/imx/imx9/imx91/mmu_regions.c b/soc/nxp/imx/imx9/imx91/mmu_regions.c
new file mode 100644
index 00000000000..62f04672b66
--- /dev/null
+++ b/soc/nxp/imx/imx9/imx91/mmu_regions.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm64/arm_mmu.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/util.h>
+
+static const struct arm_mmu_region mmu_regions[] = {
+	MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 0),
+			      DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 0),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
+
+	MMU_REGION_FLAT_ENTRY("GIC", DT_REG_ADDR_BY_IDX(DT_NODELABEL(gic), 1),
+			      DT_REG_SIZE_BY_IDX(DT_NODELABEL(gic), 1),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
+
+	MMU_REGION_FLAT_ENTRY("CCM", DT_REG_ADDR(DT_NODELABEL(ccm)), DT_REG_SIZE(DT_NODELABEL(ccm)),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
+
+	MMU_REGION_FLAT_ENTRY("ANA_PLL", DT_REG_ADDR(DT_NODELABEL(ana_pll)),
+			      DT_REG_SIZE(DT_NODELABEL(ana_pll)),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
+
+	MMU_REGION_FLAT_ENTRY("IOMUXC", DT_REG_ADDR(DT_NODELABEL(iomuxc)),
+			      DT_REG_SIZE(DT_NODELABEL(iomuxc)),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS),
+
+	MMU_REGION_DT_COMPAT_FOREACH_FLAT_ENTRY(nxp_lpuart,
+						(MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_NS))
+};
+
+const struct arm_mmu_config mmu_config = {
+	.num_regions = ARRAY_SIZE(mmu_regions),
+	.mmu_regions = mmu_regions,
+};
diff --git a/soc/nxp/imx/imx9/imx91/pinctrl_soc.h b/soc/nxp/imx/imx9/imx91/pinctrl_soc.h
new file mode 100644
index 00000000000..b168d6457ae
--- /dev/null
+++ b/soc/nxp/imx/imx9/imx91/pinctrl_soc.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_ARM64_NXP_IMX9_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_ARM64_NXP_IMX9_PINCTRL_SOC_H_
+
+#include <zephyr/devicetree.h>
+#include <zephyr/types.h>
+#include "fsl_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC1_SW_PAD_CTL_PAD_HYS_SHIFT
+#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT     IOMUXC1_SW_PAD_CTL_PAD_OD_SHIFT
+#define MCUX_IMX_BIAS_PULL_DOWN_SHIFT       IOMUXC1_SW_PAD_CTL_PAD_PD_SHIFT
+#define MCUX_IMX_BIAS_PULL_UP_SHIFT         IOMUXC1_SW_PAD_CTL_PAD_PU_SHIFT
+#define MCUX_IMX_SLEW_RATE_SHIFT            IOMUXC1_SW_PAD_CTL_PAD_FSEL1_SHIFT
+#define MCUX_IMX_DRIVE_STRENGTH_SHIFT       IOMUXC1_SW_PAD_CTL_PAD_DSE_SHIFT
+#define MCUX_IMX_INPUT_ENABLE_SHIFT         23 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
+#define MCUX_IMX_INPUT_ENABLE(x)            ((x >> MCUX_IMX_INPUT_ENABLE_SHIFT) & 0x1)
+
+#define Z_PINCTRL_MCUX_IMX_PINCFG_INIT(node_id)                                                    \
+	((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) |         \
+	 (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) |                 \
+	 (DT_PROP(node_id, bias_pull_down) << MCUX_IMX_BIAS_PULL_DOWN_SHIFT) |                     \
+	 (DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) |                         \
+	 (DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) |                           \
+	 ((~(0xffffffff << DT_ENUM_IDX(node_id, drive_strength)))                                  \
+	  << MCUX_IMX_DRIVE_STRENGTH_SHIFT) |                                                      \
+	 (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT))
+
+/* This struct must be present. It is used by the mcux gpio driver */
+struct pinctrl_soc_pinmux {
+	uint32_t mux_register;    /*!< IOMUXC SW_PAD_MUX register */
+	uint32_t config_register; /*!< IOMUXC SW_PAD_CTL register */
+	uint32_t input_register;  /*!< IOMUXC SELECT_INPUT DAISY register */
+	uint8_t mux_mode: 4;      /*!< Mux value for SW_PAD_MUX register */
+	uint32_t input_daisy: 4;  /*!< Mux value for SELECT_INPUT_DAISY register */
+};
+
+struct pinctrl_soc_pin {
+	struct pinctrl_soc_pinmux pinmux;
+	uint32_t pin_ctrl_flags; /*!< value to write to IOMUXC_SW_PAD_CTL register */
+};
+
+typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
+
+/* This definition must be present. It is used by the mcux gpio driver */
+#define MCUX_IMX_PINMUX(node_id)                                                                   \
+	{                                                                                          \
+		.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0),                                \
+		.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4),                             \
+		.input_register = DT_PROP_BY_IDX(node_id, pinmux, 2),                              \
+		.mux_mode = DT_PROP_BY_IDX(node_id, pinmux, 1),                                    \
+		.input_daisy = DT_PROP_BY_IDX(node_id, pinmux, 3),                                 \
+	}
+
+#define Z_PINCTRL_PINMUX(group_id, pin_prop, idx)                                                  \
+	MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
+
+#define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx)                                          \
+	{                                                                                          \
+		.pinmux = Z_PINCTRL_PINMUX(group_id, pin_prop, idx),                               \
+		.pin_ctrl_flags = Z_PINCTRL_MCUX_IMX_PINCFG_INIT(group_id),                        \
+	},
+
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)                                                   \
+	{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux,           \
+				Z_PINCTRL_STATE_PIN_INIT)};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_SOC_ARM64_NXP_IMX9_PINCTRL_SOC_H_ */
diff --git a/soc/nxp/imx/imx9/imx93/CMakeLists.txt b/soc/nxp/imx/imx9/imx93/CMakeLists.txt
index 59bd50b2d3e..1d511e7d5ff 100644
--- a/soc/nxp/imx/imx9/imx93/CMakeLists.txt
+++ b/soc/nxp/imx/imx9/imx93/CMakeLists.txt
@@ -10,5 +10,6 @@ if(CONFIG_SOC_MIMX9352_A55)
 elseif(CONFIG_SOC_MIMX9352_M33)
   zephyr_include_directories(.)
   zephyr_include_directories(m33)
+  zephyr_sources(m33/soc.c)
   set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
 endif()
diff --git a/soc/nxp/imx/imx9/imx93/Kconfig b/soc/nxp/imx/imx9/imx93/Kconfig
index 87de1fbcf92..f17c1378911 100644
--- a/soc/nxp/imx/imx9/imx93/Kconfig
+++ b/soc/nxp/imx/imx9/imx93/Kconfig
@@ -21,6 +21,7 @@ config SOC_MIMX9352_M33
 	select HAS_MCUX
 	select HAS_MCUX_IOMUXC if PINCTRL
 	select HAS_MCUX_CACHE
+	select SOC_EARLY_INIT_HOOK
 
 config MCUX_CORE_SUFFIX
 	default "_ca55" if SOC_MIMX9352_A55
diff --git a/soc/nxp/imx/imx9/imx93/m33/soc.c b/soc/nxp/imx/imx9/imx93/m33/soc.c
new file mode 100644
index 00000000000..ef61a7cb7fb
--- /dev/null
+++ b/soc/nxp/imx/imx9/imx93/m33/soc.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <soc.h>
+
+#ifdef CONFIG_SOC_EARLY_INIT_HOOK
+void soc_early_init_hook(void)
+{
+	/* Configure secure access to pin registers */
+	GPIO1->PCNS = 0x0;
+	GPIO2->PCNS = 0x0;
+	GPIO3->PCNS = 0x0;
+	GPIO4->PCNS = 0x0;
+}
+#endif
diff --git a/soc/nxp/imx/imx9/imx93/pinctrl_soc.h b/soc/nxp/imx/imx9/imx93/pinctrl_soc.h
index 91d06ea9681..c03a5a045f5 100644
--- a/soc/nxp/imx/imx9/imx93/pinctrl_soc.h
+++ b/soc/nxp/imx/imx9/imx93/pinctrl_soc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2023, NXP
+ * Copyright 2022-2023, 2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -30,7 +30,8 @@ extern "C" {
 	 (DT_PROP(node_id, bias_pull_down) << MCUX_IMX_BIAS_PULL_DOWN_SHIFT) |                     \
 	 (DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) |                         \
 	 (DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) |                           \
-	 ((~(0xff << DT_ENUM_IDX(node_id, drive_strength))) << MCUX_IMX_DRIVE_STRENGTH_SHIFT) |    \
+	 ((~(0xffffffff << DT_ENUM_IDX(node_id, drive_strength)))                                  \
+	  << MCUX_IMX_DRIVE_STRENGTH_SHIFT) |                                                      \
 	 (DT_PROP(node_id, input_enable) << MCUX_IMX_INPUT_ENABLE_SHIFT))
 
 /* This struct must be present. It is used by the mcux gpio driver */
diff --git a/soc/nxp/imx/imx9/imx95/Kconfig b/soc/nxp/imx/imx9/imx95/Kconfig
index 6b4e22b89ff..60d1f424b0a 100644
--- a/soc/nxp/imx/imx9/imx95/Kconfig
+++ b/soc/nxp/imx/imx9/imx95/Kconfig
@@ -12,6 +12,7 @@ config SOC_MIMX9596_M7
 	select ARM_MPU
 	select SOC_LATE_INIT_HOOK
 	select HAS_MCUX
+	select HAS_MCUX_CACHE
 
 config SOC_MIMX9596_A55
 	select ARM64
diff --git a/soc/nxp/imx/imx9/imx95/Kconfig.defconfig.mimx95.m7 b/soc/nxp/imx/imx9/imx95/Kconfig.defconfig.mimx95.m7
index 4265f5233b4..ee356a0ead0 100644
--- a/soc/nxp/imx/imx9/imx95/Kconfig.defconfig.mimx95.m7
+++ b/soc/nxp/imx/imx9/imx95/Kconfig.defconfig.mimx95.m7
@@ -11,8 +11,36 @@ config FLASH_SIZE
 config FLASH_BASE_ADDRESS
 	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
 
+# multi-level interrupts
+config MULTI_LEVEL_INTERRUPTS
+	default y
+
+config 1ST_LEVEL_INTERRUPT_BITS
+	default 8
+
+config MAX_IRQ_PER_AGGREGATOR
+	default 16
+
+config 2ND_LEVEL_INTERRUPTS
+	default y
+
+config 2ND_LVL_ISR_TBL_OFFSET
+	default 234
+
+config NUM_2ND_LEVEL_AGGREGATORS
+	default 1
+
+config 2ND_LEVEL_INTERRUPT_BITS
+	default 8
+
+config 2ND_LVL_INTR_00_OFFSET
+	default 224
+
+config 3RD_LEVEL_INTERRUPTS
+	default n
+
 config NUM_IRQS
-	default 230
+	default 250 # 2ND_LVL_ISR_TBL_OFFSET + MAX_IRQ_PER_AGGREGATOR * NUM_2ND_LEVEL_AGGREGATORS
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 800000000
@@ -20,4 +48,7 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config CACHE_MANAGEMENT
 	default y
 
+config ETH_NXP_IMX_MSGINTR
+	default 2
+
 endif # SOC_MIMX9596_M7
diff --git a/soc/nxp/imx/imx9/imx95/m7/CMakeLists.txt b/soc/nxp/imx/imx9/imx95/m7/CMakeLists.txt
index 0eedd7f7d40..68ee8d2bc0e 100644
--- a/soc/nxp/imx/imx9/imx95/m7/CMakeLists.txt
+++ b/soc/nxp/imx/imx9/imx95/m7/CMakeLists.txt
@@ -5,4 +5,4 @@ zephyr_include_directories(.)
 zephyr_library()
 zephyr_library_sources(soc.c)
 
-set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")
diff --git a/soc/nxp/imx/imx9/imx95/m7/linker.ld b/soc/nxp/imx/imx9/imx95/m7/linker.ld
new file mode 100644
index 00000000000..280416c0cc0
--- /dev/null
+++ b/soc/nxp/imx/imx9/imx95/m7/linker.ld
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm/cortex_m/scripts/linker.ld>
+
+SECTIONS
+{
+#ifdef CONFIG_OPENAMP_RSC_TABLE
+	SECTION_PROLOGUE(.resource_table,, SUBALIGN(4))
+	{
+		KEEP(*(.resource_table*))
+	} GROUP_LINK_IN(ROMABLE_REGION)
+#endif
+}
diff --git a/soc/nxp/imx/imx9/imx95/m7/soc.c b/soc/nxp/imx/imx9/imx95/m7/soc.c
index 7100428a149..db60e45170e 100644
--- a/soc/nxp/imx/imx9/imx95/m7/soc.c
+++ b/soc/nxp/imx/imx9/imx95/m7/soc.c
@@ -5,6 +5,19 @@
  */
 
 #include <zephyr/cache.h>
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/firmware/scmi/clk.h>
+#include <zephyr/drivers/firmware/scmi/nxp/cpu.h>
+#include <zephyr/drivers/firmware/scmi/power.h>
+#include <zephyr/dt-bindings/clock/imx95_clock.h>
+#include <zephyr/dt-bindings/power/imx95_power.h>
+#include <soc.h>
+
+/* SCMI power domain states */
+#define POWER_DOMAIN_STATE_ON  0x00000000
+#define POWER_DOMAIN_STATE_OFF 0x40000000
 
 void soc_late_init_hook(void)
 {
@@ -13,3 +26,71 @@ void soc_late_init_hook(void)
 	sys_cache_instr_enable();
 #endif /* CONFIG_CACHE_MANAGEMENT */
 }
+
+static int soc_init(void)
+{
+	int ret = 0;
+#if defined(CONFIG_NXP_SCMI_CPU_DOMAIN_HELPERS)
+	struct scmi_cpu_sleep_mode_config cpu_cfg = {0};
+#endif /* CONFIG_NXP_SCMI_CPU_DOMAIN_HELPERS */
+
+#if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0)
+	const struct device *clk_dev = DEVICE_DT_GET(DT_NODELABEL(scmi_clk));
+	struct scmi_protocol *proto = clk_dev->data;
+	struct scmi_clock_rate_config clk_cfg = {0};
+	struct scmi_power_state_config pwr_cfg = {0};
+	uint32_t power_state = POWER_DOMAIN_STATE_OFF;
+	uint64_t enetref_clk = 250000000; /* 250 MHz*/
+
+	/* Power up NETCMIX */
+	pwr_cfg.domain_id = IMX95_PD_NETC;
+	pwr_cfg.power_state = POWER_DOMAIN_STATE_ON;
+
+	ret = scmi_power_state_set(&pwr_cfg);
+	if (ret) {
+		return ret;
+	}
+
+	while (power_state != POWER_DOMAIN_STATE_ON) {
+		ret = scmi_power_state_get(IMX95_PD_NETC, &power_state);
+		if (ret) {
+			return ret;
+		}
+	}
+
+	/* ENETREF clock init */
+	ret = scmi_clock_parent_set(proto, IMX95_CLK_ENETREF, IMX95_CLK_SYSPLL1_PFD0);
+	if (ret) {
+		return ret;
+	}
+
+	clk_cfg.flags = SCMI_CLK_RATE_SET_FLAGS_ROUNDS_AUTO;
+	clk_cfg.clk_id = IMX95_CLK_ENETREF;
+	clk_cfg.rate[0] = enetref_clk & 0xffffffff;
+	clk_cfg.rate[1] = (enetref_clk >> 32) & 0xffffffff;
+
+	ret = scmi_clock_rate_set(proto, &clk_cfg);
+	if (ret) {
+		return ret;
+	}
+#endif
+
+#if defined(CONFIG_NXP_SCMI_CPU_DOMAIN_HELPERS)
+	cpu_cfg.cpu_id = CPU_IDX_M7P;
+	cpu_cfg.sleep_mode = CPU_SLEEP_MODE_RUN;
+
+	ret = scmi_cpu_sleep_mode_set(&cpu_cfg);
+	if (ret) {
+		return ret;
+	}
+#endif /* CONFIG_NXP_SCMI_CPU_DOMAIN_HELPERS */
+
+	return ret;
+}
+
+/*
+ * Because platform is using ARM SCMI, drivers like scmi, mbox etc. are
+ * initialized during PRE_KERNEL_1. Common init hooks is not able to use.
+ * SoC early init and board early init could be run during PRE_KERNEL_2 instead.
+ */
+SYS_INIT(soc_init, PRE_KERNEL_2, 0);
diff --git a/soc/nxp/imx/imx9/imx95/pinctrl_soc.h b/soc/nxp/imx/imx9/imx95/pinctrl_soc.h
index 08fd4099550..6065a5c8a34 100644
--- a/soc/nxp/imx/imx9/imx95/pinctrl_soc.h
+++ b/soc/nxp/imx/imx9/imx95/pinctrl_soc.h
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -27,23 +27,24 @@ extern "C" {
 #define IOMUXC_CFGREG   (IOMUXC_BASE + 0x204)
 #define IOMUXC_DAISYREG (IOMUXC_BASE + 0x408)
 
-#define IOMUXC_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT
-#define IOMUXC_DRIVE_OPEN_DRAIN_SHIFT     IOMUXC_SW_PAD_CTL_PAD_OD_SHIFT
-#define IOMUXC_BIAS_PULL_DOWN_SHIFT       IOMUXC_SW_PAD_CTL_PAD_PD_SHIFT
-#define IOMUXC_BIAS_PULL_UP_SHIFT         IOMUXC_SW_PAD_CTL_PAD_PU_SHIFT
-#define IOMUXC_SLEW_RATE_SHIFT            IOMUXC_SW_PAD_CTL_PAD_FSEL1_SHIFT
-#define IOMUXC_DRIVE_STRENGTH_SHIFT       IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT
+#define MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT IOMUXC_SW_PAD_CTL_PAD_HYS_SHIFT
+#define MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT     IOMUXC_SW_PAD_CTL_PAD_OD_SHIFT
+#define MCUX_IMX_BIAS_PULL_DOWN_SHIFT       IOMUXC_SW_PAD_CTL_PAD_PD_SHIFT
+#define MCUX_IMX_BIAS_PULL_UP_SHIFT         IOMUXC_SW_PAD_CTL_PAD_PU_SHIFT
+#define MCUX_IMX_SLEW_RATE_SHIFT            IOMUXC_SW_PAD_CTL_PAD_FSEL1_SHIFT
+#define MCUX_IMX_DRIVE_STRENGTH_SHIFT       IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT
 
 #define IOMUXC_INPUT_ENABLE_SHIFT 23 /* Shift to a bit not used by IOMUXC_SW_PAD_CTL */
 #define IOMUXC_INPUT_ENABLE(x)    ((x >> IOMUXC_INPUT_ENABLE_SHIFT) & 0x1)
 
 #define Z_PINCTRL_IOMUXC_PINCFG_INIT(node_id)                                                      \
-	((DT_PROP(node_id, input_schmitt_enable) << IOMUXC_INPUT_SCHMITT_ENABLE_SHIFT) |           \
-	 (DT_PROP(node_id, drive_open_drain) << IOMUXC_DRIVE_OPEN_DRAIN_SHIFT) |                   \
-	 (DT_PROP(node_id, bias_pull_down) << IOMUXC_BIAS_PULL_DOWN_SHIFT) |                       \
-	 (DT_PROP(node_id, bias_pull_up) << IOMUXC_BIAS_PULL_UP_SHIFT) |                           \
-	 (DT_ENUM_IDX(node_id, slew_rate) << IOMUXC_SLEW_RATE_SHIFT) |                             \
-	 ((~(0xff << DT_ENUM_IDX(node_id, drive_strength))) << IOMUXC_DRIVE_STRENGTH_SHIFT) |      \
+	((DT_PROP(node_id, input_schmitt_enable) << MCUX_IMX_INPUT_SCHMITT_ENABLE_SHIFT) |         \
+	 (DT_PROP(node_id, drive_open_drain) << MCUX_IMX_DRIVE_OPEN_DRAIN_SHIFT) |                 \
+	 (DT_PROP(node_id, bias_pull_down) << MCUX_IMX_BIAS_PULL_DOWN_SHIFT) |                     \
+	 (DT_PROP(node_id, bias_pull_up) << MCUX_IMX_BIAS_PULL_UP_SHIFT) |                         \
+	 (DT_ENUM_IDX(node_id, slew_rate) << MCUX_IMX_SLEW_RATE_SHIFT) |                           \
+	 ((~(0xffffffff << DT_ENUM_IDX(node_id, drive_strength)))                                  \
+	  << MCUX_IMX_DRIVE_STRENGTH_SHIFT) |                                                      \
 	 (DT_PROP(node_id, input_enable) << IOMUXC_INPUT_ENABLE_SHIFT))
 
 /* This struct must be present. It is used by the mcux gpio driver */
@@ -63,7 +64,7 @@ struct pinctrl_soc_pin {
 typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
 
 /* This definition must be present. It is used by the mcux gpio driver */
-#define IOMUXC_PINMUX(node_id)                                                                     \
+#define MCUX_IMX_PINMUX(node_id)                                                                   \
 	{                                                                                          \
 		.mux_register = DT_PROP_BY_IDX(node_id, pinmux, 0),                                \
 		.config_register = DT_PROP_BY_IDX(node_id, pinmux, 4),                             \
@@ -73,7 +74,7 @@ typedef struct pinctrl_soc_pin pinctrl_soc_pin_t;
 	}
 
 #define Z_PINCTRL_PINMUX(group_id, pin_prop, idx)                                                  \
-	IOMUXC_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
+	MCUX_IMX_PINMUX(DT_PHANDLE_BY_IDX(group_id, pin_prop, idx))
 
 #define Z_PINCTRL_STATE_PIN_INIT(group_id, pin_prop, idx)                                          \
 	{                                                                                          \
diff --git a/soc/nxp/imx/imx9/imx95/scmi_cpu_soc.h b/soc/nxp/imx/imx9/imx95/scmi_cpu_soc.h
new file mode 100644
index 00000000000..ac23b1fd8b9
--- /dev/null
+++ b/soc/nxp/imx/imx9/imx95/scmi_cpu_soc.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_NXP_IMX95_SCMI_CPU_SOC_H_
+#define ZEPHYR_NXP_IMX95_SCMI_CPU_SOC_H_
+
+#define CPU_IDX_M33P        0U
+#define CPU_IDX_M7P         1U
+#define CPU_IDX_A55C0       2U
+#define CPU_IDX_A55C1       3U
+#define CPU_IDX_A55C2       4U
+#define CPU_IDX_A55C3       5U
+#define CPU_IDX_A55C4       6U
+#define CPU_IDX_A55C5       7U
+#define CPU_IDX_A55P        8U
+#define CPU_NUM_IDX         9U
+
+#define CPU_SLEEP_MODE_RUN      0U
+#define CPU_SLEEP_MODE_WAIT     1U
+#define CPU_SLEEP_MODE_STOP     2U
+#define CPU_SLEEP_MODE_SUSPEND  3U
+
+#endif /* ZEPHYR_NXP_IMX95_SCMI_CPU_SOC_H_ */
diff --git a/soc/nxp/imx/soc.yml b/soc/nxp/imx/soc.yml
index 64371b41c23..e955bfee6a8 100644
--- a/soc/nxp/imx/soc.yml
+++ b/soc/nxp/imx/soc.yml
@@ -35,6 +35,7 @@ family:
       - name: m4
   - name: imx9
     socs:
+    - name: mimx9131
     - name: mimx9352
       cpuclusters:
       - name: a55
diff --git a/soc/nxp/imxrt/CMakeLists.txt b/soc/nxp/imxrt/CMakeLists.txt
index 5984d081ba9..ac5302a32fc 100644
--- a/soc/nxp/imxrt/CMakeLists.txt
+++ b/soc/nxp/imxrt/CMakeLists.txt
@@ -39,9 +39,6 @@ if(CONFIG_SOC_SERIES_IMXRT10XX OR CONFIG_SOC_SERIES_IMXRT11XX)
 endif()
 
 if(CONFIG_SOC_SERIES_IMXRT118X)
-  if(CONFIG_SOC_MIMXRT1189_CM7)
-    zephyr_sources(mpu_regions.c)
-  endif()
   if(CONFIG_EXTERNAL_MEM_CONFIG_DATA)
     set(boot_hdr_xmcd_data_section ".boot_hdr.xmcd_data")
   endif()
diff --git a/soc/nxp/imxrt/Kconfig b/soc/nxp/imxrt/Kconfig
index 0b8c8f0ab87..37a2916120b 100644
--- a/soc/nxp/imxrt/Kconfig
+++ b/soc/nxp/imxrt/Kconfig
@@ -1,4 +1,4 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_FAMILY_NXP_IMXRT
@@ -10,7 +10,13 @@ if SOC_FAMILY_NXP_IMXRT
 # can override the defaults given here
 rsource "*/Kconfig"
 
+if DT_HAS_NXP_IMX_FLEXSPI_ENABLED
 rsource "../common/Kconfig.flexspi_xip"
+endif
+
+if DT_HAS_NXP_XSPI_ENABLED
+rsource "../common/Kconfig.xspi_xip"
+endif
 
 # Note- When SECOND_CORE_MCUX is set, the dependencies for this Kconfig
 # should be set elsewhere, since the determination of which SOC core
@@ -29,8 +35,13 @@ rsource "../common/Kconfig.rom_loader"
 
 choice BOOT_DEVICE
 	prompt "Boot device"
+	default BOOT_XSPI_NOR if DT_HAS_NXP_XSPI_ENABLED
 	default BOOT_FLEXSPI_NOR
 
+config BOOT_XSPI_NOR
+	bool "XPI serial NOR"
+	depends on DT_HAS_NXP_XSPI_ENABLED
+
 config BOOT_FLEXSPI_NOR
 	bool "FlexSPI serial NOR"
 	depends on HAS_MCUX_FLEXSPI
@@ -49,6 +60,8 @@ config BOOT_SEMC_NAND
 
 endchoice # BOOT_DEVICE
 
+if BOOT_FLEXSPI_NOR
+
 config FLEXSPI_CONFIG_BLOCK_OFFSET
 	hex "FlexSPI config block offset"
 	default 0x0 if BOOT_FLEXSPI_NOR
@@ -59,6 +72,21 @@ config FLEXSPI_CONFIG_BLOCK_OFFSET
 	  sequence (optional), etc. The boot ROM expects FlexSPI configuration
 	  parameter to be presented in serial nor flash.
 
+endif # BOOT_FLEXSPI_NOR
+
+if BOOT_XSPI_NOR
+
+config XSPI_CONFIG_BLOCK_OFFSET
+	hex "XSPI config block offset"
+	default 0x0
+	help
+	  XSPI configuration block consists of parameters regarding specific
+	  flash devices including read command sequence, quad mode enablement
+	  sequence (optional), etc. The boot ROM expects XSPI configuration
+	  parameter to be presented in serial nor flash.
+
+endif # BOOT_XSPI_NOR
+
 config IMAGE_VECTOR_TABLE_OFFSET
 	hex "Image vector table offset"
 	default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
@@ -113,9 +141,10 @@ config NXP_IMX_EXTERNAL_HYPERRAM
 	  This setting should be enabled when the application uses HYPERRAM,
 	  or an MPU region will be defined to disable cached access to the
 	  HYPERRAM memory space.
+
 config SECOND_CORE_MCUX
 	bool "Dual core operation on the RT11xx series"
-	depends on SOC_SERIES_IMXRT11XX
+	depends on SOC_SERIES_IMXRT11XX || SOC_SERIES_IMXRT118X
 	help
 	  Indicates the second core will be enabled, and the part will run
 	  in dual core mode. Enables dual core operation on the RT11xx series,
@@ -142,6 +171,10 @@ config PM_MCUX_DCDC
 config PM_MCUX_PMU
 	bool "MCUX power management unit driver"
 
+config ADJUST_DCDC
+	default y
+	bool "Adjust internal DCDC output"
+
 config DCDC_VALUE
 	hex "DCDC value for VDD_SOC"
 
diff --git a/soc/nxp/imxrt/Kconfig.defconfig b/soc/nxp/imxrt/Kconfig.defconfig
index f82e9e126f0..78469d24fee 100644
--- a/soc/nxp/imxrt/Kconfig.defconfig
+++ b/soc/nxp/imxrt/Kconfig.defconfig
@@ -13,10 +13,6 @@ config ROM_START_OFFSET
 	default 0x400 if BOOTLOADER_MCUBOOT
 	default 0x2000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
 
-config ADC_MCUX_12B1MSPS_SAR
-	default y if HAS_MCUX_12B1MSPS_SAR
-	depends on ADC
-
 config LOG_BACKEND_SWO_FREQ_HZ
 	default 7500000
 	depends on LOG_BACKEND_SWO
@@ -39,10 +35,6 @@ config PM_MCUX_GPC
 	default y if HAS_MCUX_GPC
 	depends on SOC_SERIES_IMXRT11XX && PM
 
-# Don't allow SOC to sleep after tests complete when PM is enabled
-config ZTEST_NO_YIELD
-	default y if (ZTEST && PM)
-
 if SOC_SERIES_IMXRT10XX && PM
 
 config CODE_DATA_RELOCATION
diff --git a/soc/nxp/imxrt/boot_header.ld b/soc/nxp/imxrt/boot_header.ld
index 618c760f017..e52e64506f4 100644
--- a/soc/nxp/imxrt/boot_header.ld
+++ b/soc/nxp/imxrt/boot_header.ld
@@ -9,22 +9,26 @@ __VECTOR_TABLE = CONFIG_ROM_START_OFFSET;
 __Vectors = __VECTOR_TABLE;
 #endif
 
-. = CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET;
+#if defined(CONFIG_BOOT_XSPI_NOR)
+. += CONFIG_XSPI_CONFIG_BLOCK_OFFSET - (. - __rom_start_address);
+#else
+. += CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET - (. - __rom_start_address);
+#endif
 #if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT118X)
 KEEP(*(.boot_hdr.conf))
 #endif
-#if defined(CONFIG_SOC_SERIES_IMXRT6XX) || defined(CONFIG_SOC_SERIES_IMXRT5XX)
+#if defined(CONFIG_SOC_SERIES_IMXRT6XX) || defined(CONFIG_SOC_SERIES_IMXRT5XX) || defined(CONFIG_SOC_SERIES_IMXRT7XX)
 KEEP(*(.flash_conf))
 #endif
 #if defined(CONFIG_SOC_SERIES_IMXRT118X)
 #ifdef CONFIG_EXTERNAL_MEM_CONFIG_DATA
-	. = CONFIG_EXTERNAL_MEM_CONFIG_OFFSET;
+	. += CONFIG_EXTERNAL_MEM_CONFIG_OFFSET - (. - __rom_start_address);
 	KEEP(*(.boot_hdr.xmcd_data))
 #endif
-. = CONFIG_IMAGE_CONTAINER_OFFSET;
+. += CONFIG_IMAGE_CONTAINER_OFFSET - (. - __rom_start_address);
 KEEP(*(.boot_hdr.container))
 #else
-. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;
+. += CONFIG_IMAGE_VECTOR_TABLE_OFFSET - (. - __rom_start_address);
 KEEP(*(.boot_hdr.ivt))
 #endif
 #if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX)
@@ -33,7 +37,7 @@ KEEP(*(.boot_hdr.data))
 	KEEP(*(.boot_hdr.dcd_data))
 #endif /* CONFIG_DEVICE_CONFIGURATION_DATA */
 #ifdef CONFIG_EXTERNAL_MEM_CONFIG_DATA
-	. = CONFIG_EXTERNAL_MEM_CONFIG_OFFSET;
+	. += CONFIG_EXTERNAL_MEM_CONFIG_OFFSET - (. - __rom_start_address);
 	KEEP(*(.boot_hdr.xmcd_data))
 #endif
 #endif /* CONFIG_SOC_SERIES_IMXRT10XX || CONFIG_SOC_SERIES_IMXRT11XX */
diff --git a/soc/nxp/imxrt/imxrt10xx/CMakeLists.txt b/soc/nxp/imxrt/imxrt10xx/CMakeLists.txt
index 0689025c9fc..77421318acc 100644
--- a/soc/nxp/imxrt/imxrt10xx/CMakeLists.txt
+++ b/soc/nxp/imxrt/imxrt10xx/CMakeLists.txt
@@ -11,7 +11,7 @@ if(CONFIG_PM)
   zephyr_code_relocate(FILES power.c LOCATION ITCM_TEXT)
   if(CONFIG_SOC_MIMXRT1064)
     zephyr_sources(lpm_rt1064.c)
-    zephyr_code_relocate(FILES lpm_rt1064 LOCATION ITCM_TEXT)
+    zephyr_code_relocate(FILES lpm_rt1064.c LOCATION ITCM_TEXT)
   endif()
 endif()
 
diff --git a/soc/nxp/imxrt/imxrt10xx/Kconfig b/soc/nxp/imxrt/imxrt10xx/Kconfig
index c86f946aab8..13dc3063acf 100644
--- a/soc/nxp/imxrt/imxrt10xx/Kconfig
+++ b/soc/nxp/imxrt/imxrt10xx/Kconfig
@@ -11,7 +11,6 @@ config SOC_SERIES_IMXRT10XX
 	select CLOCK_CONTROL
 	select HAS_MCUX
 	select HAS_MCUX_CACHE
-	select HAS_MCUX_12B1MSPS_SAR if !SOC_MIMXRT1042
 	select HAS_MCUX_CCM if !SOC_MIMXRT1042
 	select HAS_MCUX_FLEXSPI
 	select HAS_MCUX_IGPIO
@@ -87,7 +86,6 @@ config SOC_MIMXRT1052
 	select HAS_MCUX_FLEXCAN
 	select HAS_MCUX_PWM
 	select HAS_MCUX_SRC
-	select HAS_MCUX_XBARA
 
 config SOC_MIMXRT1062
 	select HAS_MCUX_ELCDIF
@@ -107,7 +105,6 @@ config SOC_MIMXRT1062
 	select HAS_MCUX_I2S
 	select HAS_MCUX_ADC_ETC
 	select HAS_MCUX_SRC
-	select HAS_MCUX_XBARA
 
 config SOC_MIMXRT1064
 	select HAS_MCUX_ELCDIF
diff --git a/soc/nxp/imxrt/imxrt10xx/soc.c b/soc/nxp/imxrt/imxrt10xx/soc.c
index 941ae1d3474..83135d7d834 100644
--- a/soc/nxp/imxrt/imxrt10xx/soc.c
+++ b/soc/nxp/imxrt/imxrt10xx/soc.c
@@ -51,7 +51,7 @@ const clock_sys_pll_config_t sysPllConfig = {
 #endif
 
 #if CONFIG_USB_DC_NXP_EHCI
-/* USB PHY condfiguration */
+/* USB PHY configuration */
 #define BOARD_USB_PHY_D_CAL (0x0CU)
 #define BOARD_USB_PHY_TXCAL45DP (0x06U)
 #define BOARD_USB_PHY_TXCAL45DM (0x06U)
@@ -66,7 +66,7 @@ const clock_enet_pll_config_t ethPllConfig = {
 	defined(CONFIG_SOC_MIMXRT1024)
 	.enableClkOutput500M = true,
 #endif
-#if defined(CONFIG_ETH_NXP_ENET) || defined(CONFIG_ETH_MCUX)
+#if defined(CONFIG_ETH_NXP_ENET)
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet))
 	.enableClkOutput = true,
 #endif
@@ -74,7 +74,7 @@ const clock_enet_pll_config_t ethPllConfig = {
 	.enableClkOutput1 = true,
 #endif
 #endif
-#if defined(CONFIG_PTP_CLOCK_MCUX) || defined(CONFIG_PTP_CLOCK_NXP_ENET)
+#if defined(CONFIG_PTP_CLOCK_NXP_ENET)
 	.enableClkOutput25M = true,
 #else
 	.enableClkOutput25M = false,
@@ -135,7 +135,7 @@ const __imx_boot_ivt_section ivt image_vector_table = {
 /**
  * @brief Initialize the system clock
  */
-static ALWAYS_INLINE void clock_init(void)
+__weak void clock_init(void)
 {
 	/* Boot ROM did initialize the XTAL, here we only sets external XTAL
 	 * OSC freq
@@ -151,14 +151,15 @@ static ALWAYS_INLINE void clock_init(void)
 	/* Set PERIPH_CLK MUX to PERIPH_CLK2 */
 	CLOCK_SetMux(kCLOCK_PeriphMux, 0x1);
 
-	/* Setting the VDD_SOC value.
-	 */
+#if CONFIG_ADJUST_DCDC
+	/* Setting the VDD_SOC value */
 	DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(CONFIG_DCDC_VALUE);
 	/* Waiting for DCDC_STS_DC_OK bit is asserted */
 	while (DCDC_REG0_STS_DC_OK_MASK !=
 			(DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) {
 		;
 	}
+#endif
 
 #ifdef CONFIG_INIT_ARM_PLL
 	CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */
@@ -209,8 +210,9 @@ static ALWAYS_INLINE void clock_init(void)
 #endif
 
 #ifdef CONFIG_SPI_MCUX_LPSPI
-	CLOCK_SetMux(kCLOCK_LpspiMux, 1); /* Set SPI source to USB1 PFD0 720M */
-	CLOCK_SetDiv(kCLOCK_LpspiDiv, 7); /* Set SPI divider to 8 */
+	/* Configure input clock to be able to reach the datasheet specified band rate. */
+	CLOCK_SetMux(kCLOCK_LpspiMux, 1); /* Set SPI source to USB1 PFD0 */
+	CLOCK_SetDiv(kCLOCK_LpspiDiv, 0); /* Set SPI divider to 1 */
 #endif
 
 #ifdef CONFIG_DISPLAY_MCUX_ELCDIF
@@ -227,7 +229,7 @@ static ALWAYS_INLINE void clock_init(void)
 
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet)) && CONFIG_NET_L2_ETHERNET
-#if CONFIG_ETH_MCUX_RMII_EXT_CLK
+#if CONFIG_ETH_NXP_ENET_RMII_EXT_CLK
 	/* Enable clock input for ENET1 */
 	IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, false);
 #else
diff --git a/soc/nxp/imxrt/imxrt118x/CMakeLists.txt b/soc/nxp/imxrt/imxrt118x/CMakeLists.txt
index faabf48236f..75a79185fb6 100644
--- a/soc/nxp/imxrt/imxrt118x/CMakeLists.txt
+++ b/soc/nxp/imxrt/imxrt118x/CMakeLists.txt
@@ -1,5 +1,5 @@
 #
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 #
@@ -11,6 +11,10 @@ if(CONFIG_SOC_MIMXRT1189_CM33)
   zephyr_linker_sources(DTCM_SECTION m33/dtcm.ld)
 endif()
 
+if(CONFIG_SOC_MIMXRT1189_CM7)
+  zephyr_sources(m7/mpu_regions.c)
+endif()
+
 zephyr_include_directories(.)
 
 if(CONFIG_MEMC_MCUX_FLEXSPI)
@@ -20,4 +24,13 @@ if(CONFIG_MEMC_MCUX_FLEXSPI)
   endif()
 endif()
 
+if((CONFIG_NXP_IMXRT_BOOT_HEADER) AND (CONFIG_BOOT_FLEXSPI_NOR))
+  set(RT118x_DEVICE_BOOT_HEADER_DIR
+    "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk-ng/devices/RT/RT1180/MIMXRT1189")
+
+  zephyr_library_sources(${RT118x_DEVICE_BOOT_HEADER_DIR}/xip/fsl_flexspi_nor_boot.c)
+  zephyr_library_include_directories(${RT118x_DEVICE_BOOT_HEADER_DIR}/xip)
+  zephyr_library_include_directories(${RT118x_DEVICE_BOOT_HEADER_DIR})
+endif()
+
 set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")
diff --git a/soc/nxp/imxrt/imxrt118x/Kconfig b/soc/nxp/imxrt/imxrt118x/Kconfig
index 02ba54e0754..d62af3d1b51 100644
--- a/soc/nxp/imxrt/imxrt118x/Kconfig
+++ b/soc/nxp/imxrt/imxrt118x/Kconfig
@@ -2,7 +2,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_IMXRT118X
-	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS if SOC_MIMXRT1189_CM7
 	select CPU_CORTEX_M_HAS_DWT
 	select SOC_RESET_HOOK
 	select INIT_ARCH_HW_AT_BOOT if SOC_MIMXRT1189_CM33
@@ -13,8 +12,8 @@ config SOC_SERIES_IMXRT118X
 	select CPU_HAS_ARM_SAU if SOC_MIMXRT1189_CM33
 	select HAS_MCUX
 	select CPU_HAS_ARM_MPU
-	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS if SOC_MIMXRT1189_CM33
-	select ARM_MPU if SOC_MIMXRT1189_CM33
+	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
+	select ARM_MPU
 	select INIT_ARM_PLL
 	select ARM_TRUSTZONE_M if SOC_MIMXRT1189_CM33
 	select CPU_HAS_ICACHE
@@ -28,6 +27,8 @@ config SOC_SERIES_IMXRT118X
 
 config SOC_MIMXRT1189_CM33
 	select CPU_CORTEX_M33
+	select HAS_MCUX_XCACHE
+	select CACHE_MANAGEMENT
 
 config SOC_MIMXRT1189_CM7
 	select CPU_CORTEX_M7
@@ -66,12 +67,4 @@ config S3MU_MCUX_S3MU
 	default y
 	bool "Use S3MU MCUX Driver"
 
-config IMXRT118X_CM33_XCACHE_PS
-	bool "Use CM33 XCACHE_PS"
-	default y if SOC_MIMXRT1189_CM33
-	help
-	  Use CM33 XCACHE_PS at boot. Please note XCACHE_PC have been
-	  enabled in SystemInit function. If this Kconfig is cleared,
-	  the XCACHE controller won't be enabled during SOC init
-
 endif # SOC_SERIES_IMXRT118X
diff --git a/soc/nxp/imxrt/imxrt118x/Kconfig.defconfig b/soc/nxp/imxrt/imxrt118x/Kconfig.defconfig
index ee930543c9b..439d49d74c4 100644
--- a/soc/nxp/imxrt/imxrt118x/Kconfig.defconfig
+++ b/soc/nxp/imxrt/imxrt118x/Kconfig.defconfig
@@ -1,8 +1,11 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_SERIES_IMXRT118X
 
+config CORTEX_M_SYSTICK
+	default n if MCUX_LPTMR_TIMER
+
 config NUM_IRQS
 	default 239
 
@@ -30,8 +33,13 @@ if SECOND_CORE_MCUX
 
 # RT Boot header is only needed on primary core
 config NXP_IMXRT_BOOT_HEADER
-	depends on !CPU_CORTEX_M7
+	default y
+	depends on !(CPU_CORTEX_M7 || BOOTLOADER_MCUBOOT)
 
 endif # SECOND_CORE_MCUX
 
+choice CACHE_TYPE
+	default EXTERNAL_CACHE if SOC_MIMXRT1189_CM33
+endchoice
+
 endif # SOC_SERIES_IMXRT118X
diff --git a/soc/nxp/imxrt/imxrt118x/m33/mpu_regions.c b/soc/nxp/imxrt/imxrt118x/m33/mpu_regions.c
index 0e017caa56b..8783ad6a77e 100644
--- a/soc/nxp/imxrt/imxrt118x/m33/mpu_regions.c
+++ b/soc/nxp/imxrt/imxrt118x/m33/mpu_regions.c
@@ -11,6 +11,8 @@
 #define REGION_FLEXSPI2_SIZE           0x04000000
 #define REGION_DTCM_BASE_ADDRESS       0x30000000
 #define REGION_DTCM_SIZE               0x00020000
+#define REGION_SRAM2_SHM_BASE_ADDRESS  0x20500000
+#define REGION_SRAM2_SHM_SIZE          0x00008000
 #define REGION_FLEXSPI_BASE_ADDRESS    0x38000000
 #define REGION_FLEXSPI_SIZE            0x08000000
 #define REGION_PERIPHERAL_BASE_ADDRESS 0x50000000
@@ -23,6 +25,9 @@ static const struct arm_mpu_region mpu_regions[] = {
 			 REGION_FLASH_ATTR(REGION_FLEXSPI_BASE_ADDRESS, REGION_FLEXSPI_SIZE)),
 	MPU_REGION_ENTRY("DTCM", REGION_DTCM_BASE_ADDRESS,
 			 REGION_RAM_NOCACHE_ATTR(REGION_DTCM_BASE_ADDRESS, REGION_DTCM_SIZE)),
+	MPU_REGION_ENTRY(
+		"SRAM2_SHM", REGION_SRAM2_SHM_BASE_ADDRESS,
+		REGION_RAM_NOCACHE_ATTR(REGION_SRAM2_SHM_BASE_ADDRESS, REGION_SRAM2_SHM_SIZE)),
 	MPU_REGION_ENTRY(
 		"PERIPHERAL", REGION_PERIPHERAL_BASE_ADDRESS,
 		REGION_DEVICE_ATTR(REGION_PERIPHERAL_BASE_ADDRESS, REGION_PERIPHERAL_SIZE)),
diff --git a/soc/nxp/imxrt/imxrt118x/m7/mpu_regions.c b/soc/nxp/imxrt/imxrt118x/m7/mpu_regions.c
new file mode 100644
index 00000000000..dbc52d8b68f
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt118x/m7/mpu_regions.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
+
+#define REGION_ITCM_BASE_ADDRESS       0x00000000
+#define REGION_ITCM_SIZE               REGION_256K
+#define REGION_FLEXSPI2_BASE_ADDRESS   0x04000000
+#define REGION_FLEXSPI2_SIZE           REGION_64M
+#define REGION_DTCM_BASE_ADDRESS       0x20000000
+#define REGION_DTCM_SIZE               REGION_256K
+#define REGION_FLEXSPI_BASE_ADDRESS    0x28000000
+#define REGION_FLEXSPI_SIZE            REGION_128M
+#define REGION_PERIPHERAL_BASE_ADDRESS 0x40000000
+#define REGION_PERIPHERAL_SIZE         REGION_1G
+
+static const struct arm_mpu_region mpu_regions[] = {
+	MPU_REGION_ENTRY("ITCM", REGION_ITCM_BASE_ADDRESS, REGION_FLASH_ATTR(REGION_ITCM_SIZE)),
+	MPU_REGION_ENTRY("FLEXSPI2", REGION_FLEXSPI2_BASE_ADDRESS,
+			 REGION_RAM_ATTR(REGION_FLEXSPI2_SIZE)),
+	MPU_REGION_ENTRY("FLEXSPI", REGION_FLEXSPI_BASE_ADDRESS,
+			 REGION_FLASH_ATTR(REGION_FLEXSPI_SIZE)),
+	MPU_REGION_ENTRY("DTCM", REGION_DTCM_BASE_ADDRESS, REGION_RAM_ATTR(REGION_DTCM_SIZE)),
+	MPU_REGION_ENTRY("PERIPHERAL", REGION_PERIPHERAL_BASE_ADDRESS,
+			 REGION_PPB_ATTR(REGION_PERIPHERAL_SIZE)),
+};
+
+const struct arm_mpu_config mpu_config = {
+	.num_regions = ARRAY_SIZE(mpu_regions),
+	.mpu_regions = mpu_regions,
+};
diff --git a/soc/nxp/imxrt/imxrt118x/soc.c b/soc/nxp/imxrt/imxrt118x/soc.c
index e1499f03924..5106e647749 100644
--- a/soc/nxp/imxrt/imxrt118x/soc.c
+++ b/soc/nxp/imxrt/imxrt118x/soc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,23 +7,37 @@
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
+#include <zephyr/logging/log.h>
 #include <soc.h>
 #include <zephyr/linker/sections.h>
 #include <zephyr/linker/linker-defs.h>
-#if defined(CONFIG_SOC_MIMXRT1189_CM7)
 #include <zephyr/cache.h>
-#elif defined(CONFIG_IMXRT118X_CM33_XCACHE_PS)
-#include <fsl_cache.h>
-#endif
 #include <fsl_clock.h>
 #include <fsl_gpc.h>
 #include <fsl_pmu.h>
 #include <fsl_dcdc.h>
 #include <fsl_ele_base_api.h>
 #include <fsl_trdc.h>
+#if defined(CONFIG_WDT_MCUX_RTWDOG)
+#include <fsl_soc_src.h>
+#endif
 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
 #include <cmsis_core.h>
 
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#if  defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M33)
+#include <zephyr_image_info.h>
+/* Memcpy macro to copy segments from secondary core image stored in flash
+ * to RAM section that secondary core boots from.
+ * n is the segment number, as defined in zephyr_image_info.h
+ */
+#define MEMCPY_SEGMENT(n, _)							\
+	memcpy((uint32_t *)(((SEGMENT_LMA_ADDRESS_ ## n) - ADJUSTED_LMA) + 0x303C0000),	\
+		(uint32_t *)(SEGMENT_LMA_ADDRESS_ ## n),			\
+		(SEGMENT_SIZE_ ## n))
+#endif
+
 /*
  * Set ELE_STICK_FAILED_STS to 0 when ELE status check is not required,
  * which is useful when debug reset, where the core has already get the
@@ -42,6 +56,18 @@
 #define ELE_TRDC_WAKEUP_ID 0x78
 #define ELE_CORE_CM33_ID   0x1
 #define ELE_CORE_CM7_ID    0x2
+#define EDMA_DID           0x7U
+
+/* When CM33 sets TRDC, CM7 must NOT require TRDC ownership from ELE */
+#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_MIMXRT1189_CM7)
+/* When CONFIG_SECOND_CORE_MCUX then TRDC(AON/WAKEUP) ownership cannot be released
+ * to CM33 and CM7 both in one ELE reset cycle.
+ * Only CM33 will set TRDC.
+ */
+#define CM33_SET_TRDC 0U
+#else
+#define CM33_SET_TRDC 1U
+#endif
 
 #ifdef CONFIG_INIT_ARM_PLL
 static const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
@@ -56,6 +82,14 @@ static const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
 };
 #endif
 
+#if defined(CONFIG_WDT_MCUX_RTWDOG)
+#define RTWDOG_IF_SET_SRC(n, i)                                                                    \
+	if (IS_ENABLED(DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(rtwdog##n), nxp_rtwdog, okay))) {    \
+		SRC_SetGlobalSystemResetMode(SRC_GENERAL_REG, kSRC_Wdog##i##Reset,                 \
+					     kSRC_ResetSystem);                                    \
+	}
+#endif
+
 const clock_sys_pll1_config_t sysPll1Config_BOARD_BootClockRUN = {
 	/* Enable Sys Pll1 divide-by-2 clock or not */
 	.pllDiv2En = 1,
@@ -91,7 +125,7 @@ __attribute__((weak)) void board_flexspi_clock_safe_config(void)
 /**
  * @brief Initialize the system clock
  */
-static ALWAYS_INLINE void clock_init(void)
+__weak void clock_init(void)
 {
 	clock_root_config_t rootCfg = {0};
 
@@ -225,14 +259,58 @@ static ALWAYS_INLINE void clock_init(void)
 	CLOCK_SetRootClock(kCLOCK_Root_M7_Systick, &rootCfg);
 #endif
 
-#if defined(CONFIG_UART_MCUX_LPUART) && \
-	(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1)) \
+#if defined(CONFIG_UART_MCUX_LPUART)
+
+#if	(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1)) \
 	|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart2)))
 	/* Configure LPUART0102 using SYS_PLL3_DIV2_CLK */
 	rootCfg.mux = kCLOCK_LPUART0102_ClockRoot_MuxSysPll3Div2;
 	rootCfg.div = 10;
+	CLOCK_SetRootClock(kCLOCK_Root_Lpuart0102, &rootCfg);
+#endif
+
+#if	(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart3)) \
+	|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart4)))
+	/* Configure LPUART0304 using SYS_PLL3_DIV2_CLK */
+	rootCfg.mux = kCLOCK_LPUART0304_ClockRoot_MuxSysPll3Div2;
+	rootCfg.div = 10;
+	CLOCK_SetRootClock(kCLOCK_Root_Lpuart0304, &rootCfg);
+#endif
+
+#if	(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart5)) \
+	|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart6)))
+	/* Configure LPUART0506 using SYS_PLL3_DIV2_CLK */
+	rootCfg.mux = kCLOCK_LPUART0506_ClockRoot_MuxSysPll3Div2;
+	rootCfg.div = 10;
+	CLOCK_SetRootClock(kCLOCK_Root_Lpuart0506, &rootCfg);
 #endif
 
+#if	(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart7)) \
+	|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart8)))
+	/* Configure LPUART0708 using SYS_PLL3_DIV2_CLK */
+	rootCfg.mux = kCLOCK_LPUART0708_ClockRoot_MuxSysPll3Div2;
+	rootCfg.div = 10;
+	CLOCK_SetRootClock(kCLOCK_Root_Lpuart0708, &rootCfg);
+#endif
+
+#if	(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart9)) \
+	|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart10)))
+	/* Configure LPUART0910 using SYS_PLL3_DIV2_CLK */
+	rootCfg.mux = kCLOCK_LPUART0910_ClockRoot_MuxSysPll3Div2;
+	rootCfg.div = 10;
+	CLOCK_SetRootClock(kCLOCK_Root_Lpuart0910, &rootCfg);
+#endif
+
+#if	(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart11)) \
+	|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart12)))
+	/* Configure LPUART1112 using SYS_PLL3_DIV2_CLK */
+	rootCfg.mux = kCLOCK_LPUART1112_ClockRoot_MuxSysPll3Div2;
+	rootCfg.div = 10;
+	CLOCK_SetRootClock(kCLOCK_Root_Lpuart1112, &rootCfg);
+#endif
+
+#endif /* CONFIG_UART_MCUX_LPUART */
+
 #if defined(CONFIG_I2C_MCUX_LPI2C) && \
 	(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c1)) \
 	|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpi2c2)))
@@ -260,15 +338,34 @@ static ALWAYS_INLINE void clock_init(void)
 	CLOCK_SetRootClock(kCLOCK_Root_Lpi2c0506, &rootCfg);
 #endif
 
-#if defined(CONFIG_SPI_MCUX_LPSPI) && \
-	(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi1)) \
-	|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpspi2)))
+#if defined(CONFIG_SPI_MCUX_LPSPI)
+
+#if	(DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi1), okay) \
+	|| DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi2), okay))
 	/* Configure LPSPI0102 using SYS_PLL3_PFD1_CLK */
 	rootCfg.mux = kCLOCK_LPSPI0102_ClockRoot_MuxSysPll3Pfd1;
 	rootCfg.div = 2;
 	CLOCK_SetRootClock(kCLOCK_Root_Lpspi0102, &rootCfg);
 #endif
 
+#if	(DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi3), okay) \
+	|| DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi4), okay))
+	/* Configure LPSPI0304 using SYS_PLL3_PFD1_CLK */
+	rootCfg.mux = kCLOCK_LPSPI0304_ClockRoot_MuxSysPll3Pfd1;
+	rootCfg.div = 2;
+	CLOCK_SetRootClock(kCLOCK_Root_Lpspi0304, &rootCfg);
+#endif
+
+#if (DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi5), okay) \
+	|| DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi6), okay))
+	/* Configure LPSPI0506 using SYS_PLL3_PFD1_CLK */
+	rootCfg.mux = kCLOCK_LPSPI0506_ClockRoot_MuxSysPll3Pfd1;
+	rootCfg.div = 2;
+	CLOCK_SetRootClock(kCLOCK_Root_Lpspi0506, &rootCfg);
+#endif
+
+#endif /* CONFIG_SPI_MCUX_LPSPI */
+
 #if defined(CONFIG_COUNTER_MCUX_GPT)
 
 #if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(gpt1)))
@@ -287,7 +384,7 @@ static ALWAYS_INLINE void clock_init(void)
 
 #endif /* CONFIG_COUNTER_MCUX_GPT */
 
-#ifdef CONFIG_MCUX_ACMP
+#if defined(CONFIG_COMPARATOR_MCUX_ACMP) || defined(CONFIG_SENSOR_MCUX_ACMP)
 
 #if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(acmp1))  \
 	|| DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(acmp2)) \
@@ -299,7 +396,7 @@ static ALWAYS_INLINE void clock_init(void)
 	CLOCK_SetRootClock(kCLOCK_Root_Acmp, &rootCfg);
 #endif
 
-#endif /* CONFIG_MCUX_ACMP */
+#endif /* CONFIG_COMPARATOR_MCUX_ACMP || CONFIG_SENSOR_MCUX_ACMP */
 
 #if defined(CONFIG_ETH_NXP_IMX_NETC) && (DT_CHILD_NUM_STATUS_OKAY(DT_NODELABEL(netc)) != 0)
 	/* Configure ENET using SYS_PLL1_DIV2_CLK */
@@ -467,9 +564,45 @@ static ALWAYS_INLINE void clock_init(void)
 
 #endif /* CONFIG_DT_HAS_NXP_MCUX_I3C_ENABLED */
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb1)) && CONFIG_UDC_NXP_EHCI
+	CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M,
+		DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency));
+	CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M,
+		DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency));
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb2)) && CONFIG_UDC_NXP_EHCI
+	CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usb480M,
+		DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency));
+	CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M,
+		DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency));
+#endif
+
+#ifdef CONFIG_IMX_USDHC
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay)
+	/* Configure USDHC1 using SysPll2Pfd2 */
+	rootCfg.mux = kCLOCK_USDHC1_ClockRoot_MuxSysPll2Pfd2;
+	rootCfg.div = 2;
+	CLOCK_SetRootClock(kCLOCK_Root_Usdhc1, &rootCfg);
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay)
+	/* Configure USDHC2 using SysPll2Pfd2 */
+	rootCfg.mux = kCLOCK_USDHC2_ClockRoot_MuxSysPll2Pfd2;
+	rootCfg.div = 2;
+	CLOCK_SetRootClock(kCLOCK_Root_Usdhc2, &rootCfg);
+#endif
+
+#endif /* CONFIG_IMX_USDHC */
+
 	/* Keep core clock ungated during WFI */
 	CCM->LPCG[1].LPM0 = 0x33333333;
 	CCM->LPCG[1].LPM1 = 0x33333333;
+
+	/* Let the core clock still running in WAIT mode */
+	BLK_CTRL_S_AONMIX->M7_CFG |= BLK_CTRL_S_AONMIX_M7_CFG_CORECLK_FORCE_ON_MASK;
+
 	/* Keep the system clock running so SYSTICK can wake up
 	 * the system from wfi.
 	 */
@@ -477,13 +610,6 @@ static ALWAYS_INLINE void clock_init(void)
 	GPC_CM_SetNextCpuMode(1, kGPC_RunMode);
 	GPC_CM_EnableCpuSleepHold(0, false);
 	GPC_CM_EnableCpuSleepHold(1, false);
-
-#if !defined(CONFIG_PM)
-	/* Enable the AHB clock while the CM7 is sleeping to allow debug access
-	 * to TCM
-	 */
-	BLK_CTRL_S_AONMIX->M7_CFG |= BLK_CTRL_S_AONMIX_M7_CFG_TCM_SIZE_MASK;
-#endif
 }
 
 /**
@@ -494,33 +620,55 @@ static ALWAYS_INLINE void trdc_enable_all_access(void)
 	status_t sts;
 	uint8_t i, j;
 
-    /* Get ELE FW status */
+	/* Get ELE FW status */
 	do {
 		uint32_t ele_fw_sts;
 
 		sts = ELE_BaseAPI_GetFwStatus(MU_RT_S3MUA, &ele_fw_sts);
 	} while (sts != kStatus_Success);
 
-	do {
 #if defined(CONFIG_SOC_MIMXRT1189_CM33)
-		/* Release TRDC A to CM33 core */
-		sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_AON_ID, ELE_CORE_CM33_ID);
+	/* Release TRDC AON to CM33 core */
+	sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_AON_ID, ELE_CORE_CM33_ID);
 #elif defined(CONFIG_SOC_MIMXRT1189_CM7)
-		/* Release TRDC A to CM7 core */
-		sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_AON_ID, ELE_CORE_CM7_ID);
+	/* Release TRDC AON to CM7 core */
+	sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_AON_ID, ELE_CORE_CM7_ID);
 #endif
-	} while (ELE_IS_FAILED(sts));
+	if (sts != kStatus_Success) {
+		LOG_WRN("warning: TRDC AON permission get failed. If core don't get TRDC "
+			"AON permission, AON domain permission can't be configured.");
+	}
 
-	/* Release TRDC W to CM33 core */
-	do {
 #if defined(CONFIG_SOC_MIMXRT1189_CM33)
-		/* Release TRDC A to CM33 core */
-		sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_WAKEUP_ID, ELE_CORE_CM33_ID);
+	/* Release TRDC Wakeup to CM33 core */
+	sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_WAKEUP_ID, ELE_CORE_CM33_ID);
 #elif defined(CONFIG_SOC_MIMXRT1189_CM7)
-		/* Release TRDC A to CM7 core */
-		sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_WAKEUP_ID, ELE_CORE_CM7_ID);
+	/* Release TRDC Wakeup to CM7 core */
+	sts = ELE_BaseAPI_ReleaseRDC(MU_RT_S3MUA, ELE_TRDC_WAKEUP_ID, ELE_CORE_CM7_ID);
 #endif
-	} while (ELE_IS_FAILED(sts));
+	if (sts != kStatus_Success) {
+		LOG_WRN("warning: TRDC Wakeup permission get failed. If core don't get TRDC "
+			"Wakeup permission, Wakeup domain permission can't be configured.");
+	}
+
+	/* Set the master domain access configuration for eDMA3/eDMA4 */
+	trdc_non_processor_domain_assignment_t edmaAssignment;
+
+	/* By default, EDMA access is done in privilege and security mode,
+	 * However, the NSE bit reset value in TRDC is 0, so that TRDC does
+	 * not allow nonsecurity access to other memory by default.
+	 * So by DAC module, EDMA access mode is changed to security/privilege
+	 * mode by the DAC module
+	 */
+	(void)memset(&edmaAssignment, 0, sizeof(edmaAssignment));
+	edmaAssignment.domainId       = EDMA_DID;
+	edmaAssignment.privilegeAttr  = kTRDC_MasterPrivilege;
+	edmaAssignment.secureAttr     = kTRDC_ForceSecure;
+	edmaAssignment.bypassDomainId = true;
+	edmaAssignment.lock           = false;
+
+	TRDC_SetNonProcessorDomainAssignment(TRDC1, kTRDC1_MasterDMA3, &edmaAssignment);
+	TRDC_SetNonProcessorDomainAssignment(TRDC2, kTRDC2_MasterDMA4, &edmaAssignment);
 
 	/* Enable all access modes for MBC and MRC of TRDCA and TRDCW */
 	trdc_hardware_config_t hwConfig;
@@ -542,12 +690,18 @@ static ALWAYS_INLINE void trdc_enable_all_access(void)
 
 	TRDC_GetHardwareConfig(TRDC1, &hwConfig);
 	for (i = 0U; i < hwConfig.mrcNumber; i++) {
+		/* Set TRDC1(A) secure access for eDMA domain, MRC i, all region for i memory */
+		TRDC_MrcDomainNseClear(TRDC1, i, 1UL << EDMA_DID);
+
 		for (j = 0U; j < 8; j++) {
 			TRDC_MrcSetMemoryAccessConfig(TRDC1, &memAccessConfig, i, j);
 		}
 	}
 
 	for (i = 0U; i < hwConfig.mbcNumber; i++) {
+		/* Set TRDC1(A) secure access for eDMA domain, MBC i, all memory blocks */
+		TRDC_MbcNseClearAll(TRDC1, i, 1UL << EDMA_DID, 0xF);
+
 		for (j = 0U; j < 8; j++) {
 			TRDC_MbcSetMemoryAccessConfig(TRDC1, &memAccessConfig, i, j);
 		}
@@ -555,12 +709,18 @@ static ALWAYS_INLINE void trdc_enable_all_access(void)
 
 	TRDC_GetHardwareConfig(TRDC2, &hwConfig);
 	for (i = 0U; i < hwConfig.mrcNumber; i++) {
+		/* Set TRDC2(W) secure access for eDMA domain, MRC i, all region for i memory */
+		TRDC_MrcDomainNseClear(TRDC2, i, 1UL << EDMA_DID);
+
 		for (j = 0U; j < 8; j++) {
 			TRDC_MrcSetMemoryAccessConfig(TRDC2, &memAccessConfig, i, j);
 		}
 	}
 
 	for (i = 0U; i < hwConfig.mbcNumber; i++) {
+		/* Set TRDC2(W) secure access for eDMA domain, MBC i, all memory blocks */
+		TRDC_MbcNseClearAll(TRDC2, i, 1UL << EDMA_DID, 0xF);
+
 		for (j = 0U; j < 8; j++) {
 			TRDC_MbcSetMemoryAccessConfig(TRDC2, &memAccessConfig, i, j);
 		}
@@ -582,17 +742,42 @@ void soc_early_init_hook(void)
 {
 	/* Initialize system clock */
 	clock_init();
+
+#if (defined(CM33_SET_TRDC) && (CM33_SET_TRDC > 0U))
 	/* Get trdc and enable all access modes for MBC and MRC of TRDCA and TRDCW */
 	trdc_enable_all_access();
+#endif /* (defined(CM33_SET_TRDC) && (CM33_SET_TRDC > 0U) */
+
+#if defined(CONFIG_WDT_MCUX_RTWDOG)
+	/* Unmask the watchdog reset channel */
+	RTWDOG_IF_SET_SRC(0, 1)
+	RTWDOG_IF_SET_SRC(1, 2)
+	RTWDOG_IF_SET_SRC(2, 3)
+	RTWDOG_IF_SET_SRC(3, 4)
+	RTWDOG_IF_SET_SRC(4, 5)
+
+	/* Clear the reset status otherwise TCM memory will reload in next reset */
+	uint32_t mask = SRC_GetResetStatusFlags(SRC_GENERAL_REG);
+
+	SRC_ClearGlobalSystemResetStatus(SRC_GENERAL_REG, mask);
+#endif /* defined(CONFIG_WDT_MCUX_RTWDOG) */
+
+#if (defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M33))
+	/**
+	 * Copy CM7 core from flash to memory. Note that depending on where the
+	 * user decided to store CM7 code, this is likely going to read from the
+	 * flexspi while using XIP. Provided we DO NOT WRITE TO THE FLEXSPI,
+	 * this operation is safe.
+	 *
+	 * Note that this copy MUST occur before enabling the M33 caching to
+	 * ensure the data is written directly to RAM (since the M4 core will use it)
+	 */
+	LISTIFY(SEGMENT_NUM, MEMCPY_SEGMENT, (;));
+#endif /* (defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M33)) */
 
 	/* Enable data cache */
-#if defined(CONFIG_IMXRT118X_CM33_XCACHE_PS)
-	XCACHE_EnableCache(XCACHE_PC);
-	XCACHE_EnableCache(XCACHE_PS);
-#elif defined(CONFIG_SOC_MIMXRT1189_CM7)
-	sys_cache_instr_enable();
 	sys_cache_data_enable();
-#endif
+
 	__ISB();
 	__DSB();
 }
@@ -601,5 +786,41 @@ void soc_early_init_hook(void)
 void soc_reset_hook(void)
 {
 	SystemInit();
+
+#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M33)
+	Prepare_CM7(0);
+#endif
+}
+#endif
+
+#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_CPU_CORTEX_M33)
+
+static int second_core_boot(void)
+{
+	/*
+	 * RT1180 Specific CM7 Kick Off operation
+	 */
+	/* Trigger S401 */
+	while ((MU_RT_S3MUA->TSR & MU_TSR_TE0_MASK) == 0) {
+		; } /* Wait TR empty */
+	MU_RT_S3MUA->TR[0] = 0x17d20106;
+	while ((MU_RT_S3MUA->RSR & MU_RSR_RF0_MASK) == 0) {
+		; } /* Wait RR Full */
+	while ((MU_RT_S3MUA->RSR & MU_RSR_RF1_MASK) == 0) {
+		; } /* Wait RR Full */
+
+	/* Response from ELE must be always read */
+	__attribute__((unused)) volatile uint32_t result1, result2;
+	result1 = MU_RT_S3MUA->RR[0];
+	result2 = MU_RT_S3MUA->RR[1];
+
+	/* Deassert Wait */
+	BLK_CTRL_S_AONMIX->M7_CFG =
+		(BLK_CTRL_S_AONMIX->M7_CFG & (~BLK_CTRL_S_AONMIX_M7_CFG_WAIT_MASK)) |
+		BLK_CTRL_S_AONMIX_M7_CFG_WAIT(0);
+
+	return 0;
 }
+
+SYS_INIT(second_core_boot, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
 #endif
diff --git a/soc/nxp/imxrt/imxrt11xx/Kconfig b/soc/nxp/imxrt/imxrt11xx/Kconfig
index 8b793ffcd02..61a5635c2b8 100644
--- a/soc/nxp/imxrt/imxrt11xx/Kconfig
+++ b/soc/nxp/imxrt/imxrt11xx/Kconfig
@@ -42,7 +42,6 @@ config SOC_SERIES_IMXRT11XX
 	select HAS_MCUX_USB_EHCI
 	select HAS_MCUX_SRC_V2
 	select HAS_MCUX_IOMUXC
-	select HAS_MCUX_XBARA
 	select HAS_SWO
 	select HAS_PM
 
@@ -70,8 +69,4 @@ config BYPASS_LDO_LPSR
 config ADJUST_LDO
 	bool "Adjust LDO setting"
 
-config ADJUST_DCDC
-	default y
-	bool "Adjust internal DCDC output"
-
 endif # SOC_SERIES_IMXRT11XX
diff --git a/soc/nxp/imxrt/imxrt11xx/power.c b/soc/nxp/imxrt/imxrt11xx/power.c
index 04209b807e9..06dee0a901e 100644
--- a/soc/nxp/imxrt/imxrt11xx/power.c
+++ b/soc/nxp/imxrt/imxrt11xx/power.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021, NXP
+ * Copyright (c) 2021, 2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -57,7 +57,6 @@ static void gpc_set_transition_flow(void)
 	gpc_tran_step_config_t step_cfg;
 
 	step_cfg.enableStep = true;
-	step_cfg.cntMode = kGPC_StepCounterDisableMode;
 
 	/* Cortex M7 */
 	GPC_CM_ConfigCpuModeTransitionStep(GPC_CPU_MODE_CTRL,
diff --git a/soc/nxp/imxrt/imxrt11xx/soc.c b/soc/nxp/imxrt/imxrt11xx/soc.c
index 8d6bae63231..e8261016bb3 100644
--- a/soc/nxp/imxrt/imxrt11xx/soc.c
+++ b/soc/nxp/imxrt/imxrt11xx/soc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2021-2024 NXP
+ * Copyright 2021-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,7 +19,7 @@
 
 LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
 
-#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER
+#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_CPU_CORTEX_M7)
 #include <fsl_flexspi_nor_boot.h>
 #endif
 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
@@ -127,7 +127,7 @@ usb_phy_config_struct_t usbPhyConfig = {
 };
 #endif
 
-#ifdef CONFIG_NXP_IMXRT_BOOT_HEADER
+#if defined(CONFIG_NXP_IMXRT_BOOT_HEADER) && defined(CONFIG_CPU_CORTEX_M7)
 const __imx_boot_data_section BOOT_DATA_T boot_data = {
 #ifdef CONFIG_XIP
 	.start = CONFIG_FLASH_BASE_ADDRESS,
@@ -160,7 +160,7 @@ const __imx_boot_ivt_section ivt image_vector_table = {
 /**
  * @brief Initialize the system clock
  */
-static ALWAYS_INLINE void clock_init(void)
+__weak void clock_init(void)
 {
 	clock_root_config_t rootCfg = {0};
 
@@ -408,13 +408,13 @@ static ALWAYS_INLINE void clock_init(void)
 	CLOCK_SetRootClock(kCLOCK_Root_Lpi2c6, &rootCfg);
 #endif
 
-#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET
+#if CONFIG_ETH_NXP_ENET
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(enet))
 	/* 50 MHz ENET clock */
 	rootCfg.mux = kCLOCK_ENET1_ClockRoot_MuxSysPll1Div2;
 	rootCfg.div = 10;
 	CLOCK_SetRootClock(kCLOCK_Root_Enet1, &rootCfg);
-#if CONFIG_ETH_MCUX_RMII_EXT_CLK
+#if CONFIG_ETH_NXP_ENET_RMII_EXT_CLK
 	/* Set ENET_REF_CLK as an input driven by PHY */
 	IOMUXC_GPR->GPR4 &= ~IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(0x01U);
 	IOMUXC_GPR->GPR4 |= IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(0x1U);
@@ -442,7 +442,7 @@ static ALWAYS_INLINE void clock_init(void)
 	 */
 	rootCfg.div = 10;
 	CLOCK_SetRootClock(kCLOCK_Root_Enet2, &rootCfg);
-#if CONFIG_ETH_MCUX_RMII_EXT_CLK
+#if CONFIG_ETH_NXP_ENET_RMII_EXT_CLK
 	/* Set ENET1G_REF_CLK as an input driven by PHY */
 	IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(0x01U);
 	IOMUXC_GPR->GPR5 |= IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(0x1U);
@@ -455,7 +455,7 @@ static ALWAYS_INLINE void clock_init(void)
 #endif
 #endif
 
-#if defined(CONFIG_PTP_CLOCK_MCUX) || defined(CONFIG_PTP_CLOCK_NXP_ENET)
+#if defined(CONFIG_PTP_CLOCK_NXP_ENET)
 	/* 24MHz PTP clock */
 	rootCfg.mux = kCLOCK_ENET_TIMER1_ClockRoot_MuxOscRc48MDiv2;
 	rootCfg.div = 1;
@@ -463,8 +463,8 @@ static ALWAYS_INLINE void clock_init(void)
 #endif
 
 #ifdef CONFIG_SPI_MCUX_LPSPI
-	/* Configure lpspi using Osc48MDiv2 */
-	rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc48MDiv2;
+	/* Configure input clock to be able to reach the datasheet specified band rate. */
+	rootCfg.mux = kCLOCK_LPSPI1_ClockRoot_MuxOscRc400M;
 	rootCfg.div = 1;
 	CLOCK_SetRootClock(kCLOCK_Root_Lpspi1, &rootCfg);
 #endif
@@ -494,7 +494,7 @@ static ALWAYS_INLINE void clock_init(void)
 #endif
 #endif
 
-#ifdef CONFIG_MCUX_ACMP
+#if defined(CONFIG_COMPARATOR_MCUX_ACMP) || defined(CONFIG_SENSOR_MCUX_ACMP)
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(acmp1))
 	/* Configure ACMP1 using Osc48MDiv2*/
 	rootCfg.mux = kCLOCK_ACMP_ClockRoot_MuxOscRc48MDiv2;
@@ -567,6 +567,14 @@ static ALWAYS_INLINE void clock_init(void)
 	CLOCK_SetRootClock(kCLOCK_Root_Flexspi1, &rootCfg);
 #endif
 
+#if !(DT_NODE_HAS_COMPAT(DT_PARENT(DT_CHOSEN(zephyr_flash)), nxp_imx_flexspi)) &&  \
+	defined(CONFIG_MEMC_MCUX_FLEXSPI) && DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(flexspi2))
+	/* Configure FLEXSPI2 using OSC_RC_48M_DIV2 */
+	rootCfg.mux = kCLOCK_FLEXSPI2_ClockRoot_MuxOscRc48MDiv2;
+	rootCfg.div = 1;
+	CLOCK_SetRootClock(kCLOCK_Root_Flexspi2, &rootCfg);
+#endif
+
 	/* Keep core clock ungated during WFI */
 	CCM->GPR_PRIVATE1_SET = 0x1;
 	/* Keep the system clock running so SYSTICK can wake up the system from
diff --git a/soc/nxp/imxrt/imxrt5xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt5xx/Kconfig.defconfig
index 0f91836ca52..63af825bacf 100644
--- a/soc/nxp/imxrt/imxrt5xx/Kconfig.defconfig
+++ b/soc/nxp/imxrt/imxrt5xx/Kconfig.defconfig
@@ -17,9 +17,6 @@ config ROM_START_OFFSET
 config NUM_IRQS
 	default 76
 
-config ZTEST_NO_YIELD
-	default y if (PM && ZTEST)
-
 if MBEDTLS
 #
 # MBEDTLS CTR_DRBG code path needs extra stack space for initialization than
diff --git a/soc/nxp/imxrt/imxrt5xx/cm33/CMakeLists.txt b/soc/nxp/imxrt/imxrt5xx/cm33/CMakeLists.txt
index dc952c53fa2..cffd07d17e6 100644
--- a/soc/nxp/imxrt/imxrt5xx/cm33/CMakeLists.txt
+++ b/soc/nxp/imxrt/imxrt5xx/cm33/CMakeLists.txt
@@ -7,6 +7,7 @@
 zephyr_compile_definitions(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE)
 
 zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
+zephyr_compile_definitions_ifdef(CONFIG_UDC_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
 
 zephyr_include_directories(.)
 
diff --git a/soc/nxp/imxrt/imxrt5xx/cm33/soc.c b/soc/nxp/imxrt/imxrt5xx/cm33/soc.c
index dd95cee362d..b826080323f 100644
--- a/soc/nxp/imxrt/imxrt5xx/cm33/soc.c
+++ b/soc/nxp/imxrt/imxrt5xx/cm33/soc.c
@@ -72,7 +72,7 @@ const clock_frg_clk_config_t g_frg12Config_clock_init = {
 	.num = 12, .sfg_clock_src = kCLOCK_FrgMainClk, .divider = 255U, .mult = 167};
 
 #if CONFIG_USB_DC_NXP_LPCIP3511
-/* USB PHY condfiguration */
+/* USB PHY configuration */
 #define BOARD_USB_PHY_D_CAL     (0x0CU)
 #define BOARD_USB_PHY_TXCAL45DP (0x06U)
 #define BOARD_USB_PHY_TXCAL45DM (0x06U)
@@ -177,7 +177,7 @@ static void usb_device_clock_init(void)
 	while (SYSCTL0->USB0CLKSTAT & SYSCTL0_USB0CLKSTAT_HOST_NEED_CLKST_MASK) {
 		__ASM("nop");
 	}
-	/* According to reference mannual, device mode setting has to be set by access
+	/* According to reference manual, device mode setting has to be set by access
 	 * usb host register
 	 */
 	USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
diff --git a/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig
index b36ea66ad62..097c5c49cf1 100644
--- a/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig
+++ b/soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig
@@ -35,9 +35,6 @@ config ROM_START_OFFSET
 config NUM_IRQS
 	default 60
 
-config ZTEST_NO_YIELD
-	default y if (ZTEST && PM)
-
 if MBEDTLS
 #
 # MBEDTLS CTR_DRBG code path needs extra stack space for initialization than
diff --git a/soc/nxp/imxrt/imxrt6xx/cm33/soc.c b/soc/nxp/imxrt/imxrt6xx/cm33/soc.c
index cf5bc6f57b4..68f5b9faf16 100644
--- a/soc/nxp/imxrt/imxrt6xx/cm33/soc.c
+++ b/soc/nxp/imxrt/imxrt6xx/cm33/soc.c
@@ -67,7 +67,7 @@ const clock_audio_pll_config_t g_audioPllConfig = {.audio_pll_src = kCLOCK_Audio
 #endif
 
 #if CONFIG_USB_DC_NXP_LPCIP3511 || CONFIG_UDC_NXP_IP3511
-/* USB PHY condfiguration */
+/* USB PHY configuration */
 #define BOARD_USB_PHY_D_CAL     (0x0CU)
 #define BOARD_USB_PHY_TXCAL45DP (0x06U)
 #define BOARD_USB_PHY_TXCAL45DM (0x06U)
@@ -168,7 +168,7 @@ static void usb_device_clock_init(void)
 	while (SYSCTL0->USBCLKSTAT & SYSCTL0_USBCLKSTAT_HOST_NEED_CLKST_MASK) {
 		__ASM("nop");
 	}
-	/* According to reference mannual, device mode setting has to be set by
+	/* According to reference manual, device mode setting has to be set by
 	 * access usb host register
 	 */
 	USBHSH->PORTMODE |= USBHSH_PORTMODE_DEV_ENABLE_MASK;
@@ -181,7 +181,7 @@ static void usb_device_clock_init(void)
 /**
  * @brief Initialize the system clock
  */
-static ALWAYS_INLINE void clock_init(void)
+__weak void clock_init(void)
 {
 #ifdef CONFIG_SOC_MIMXRT685S_CM33
 	/* Configure LPOSC clock*/
diff --git a/soc/nxp/imxrt/imxrt7xx/CMakeLists.txt b/soc/nxp/imxrt/imxrt7xx/CMakeLists.txt
new file mode 100644
index 00000000000..aeb9af94d04
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/CMakeLists.txt
@@ -0,0 +1,13 @@
+#
+# Copyright 2024-2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if(CONFIG_SOC_MIMXRT798S_CM33_CPU0 OR CONFIG_SOC_MIMXRT798S_CM33_CPU1)
+  add_subdirectory(cm33)
+elseif(CONFIG_SOC_MIMXRT798S_HIFI4)
+  add_subdirectory(hifi4)
+elseif(CONFIG_SOC_MIMXRT798S_HIFI1)
+  add_subdirectory(hifi1)
+endif()
diff --git a/soc/nxp/imxrt/imxrt7xx/Kconfig b/soc/nxp/imxrt/imxrt7xx/Kconfig
new file mode 100644
index 00000000000..20dc534d855
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/Kconfig
@@ -0,0 +1,80 @@
+# Copyright 2024-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_MIMXRT798S_CM33_CPU0
+	select CPU_CORTEX_M33
+	select CLOCK_CONTROL
+	select CPU_CORTEX_M_HAS_DWT
+	select ARM
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
+	select ARM_TRUSTZONE_M
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select HAS_MCUX
+	select HAS_MCUX_SYSCON
+	select HAS_MCUX_XCACHE
+	select CACHE_MANAGEMENT
+	select CPU_HAS_ICACHE
+	select CPU_HAS_DCACHE
+	select INIT_ARCH_HW_AT_BOOT
+	select SOC_RESET_HOOK
+	select SOC_EARLY_INIT_HOOK
+	select HAS_MCUX_FLEXCOMM
+
+config SOC_MIMXRT798S_CM33_CPU1
+	select CPU_CORTEX_M33
+	select CLOCK_CONTROL
+	select CPU_CORTEX_M_HAS_DWT
+	select ARM
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
+	select ARM_TRUSTZONE_M
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select HAS_MCUX
+	select HAS_MCUX_SYSCON
+	select HAS_MCUX_FLEXCOMM
+
+config SOC_MIMXRT798S_HIFI4
+	select XTENSA
+	select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
+	select XTENSA_RESET_VECTOR
+	select XTENSA_USE_CORE_CRT1
+	select XTENSA_GEN_HANDLERS
+	select XTENSA_SMALL_VECTOR_TABLE_ENTRY
+	select GEN_ISR_TABLES
+	select HAS_MCUX
+
+config SOC_MIMXRT798S_HIFI1
+	select XTENSA
+	select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
+	select XTENSA_RESET_VECTOR
+	select XTENSA_USE_CORE_CRT1
+	select XTENSA_GEN_HANDLERS
+	select XTENSA_SMALL_VECTOR_TABLE_ENTRY
+	select GEN_ISR_TABLES
+	select HAS_MCUX
+
+if SOC_SERIES_IMXRT7XX
+
+if NXP_IMXRT_BOOT_HEADER
+
+config IMAGE_VECTOR_TABLE_OFFSET
+	default 0x4000
+
+endif # NXP_IMXRT_BOOT_HEADER
+
+config GLIKEY_MCUX_GLIKEY
+	default y
+	bool "Use glikey MCUX Driver"
+
+config MCUX_CORE_SUFFIX
+	default "_cm33_core0" if SOC_MIMXRT798S_CM33_CPU0
+	default "_cm33_core1" if SOC_MIMXRT798S_CM33_CPU1
+	default "_hifi4" if SOC_MIMXRT798S_HIFI4
+	default "_hifi1" if SOC_MIMXRT798S_HIFI1
+
+endif # SOC_SERIES_IMXRT7XX
diff --git a/soc/nxp/imxrt/imxrt7xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt7xx/Kconfig.defconfig
new file mode 100644
index 00000000000..f4b910a2578
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/Kconfig.defconfig
@@ -0,0 +1,79 @@
+# Copyright 2024-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_MIMXRT798S_CM33_CPU0
+
+config ROM_START_OFFSET
+	default 0x4000 if NXP_IMXRT_BOOT_HEADER
+
+config NUM_IRQS
+	default 158
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 237500000 if CORTEX_M_SYSTICK
+	default 1000000 if MCUX_OS_TIMER
+
+choice CACHE_TYPE
+	default EXTERNAL_CACHE
+endchoice
+
+endif # SOC_MIMXRT798S_CM33_CPU0
+
+if SOC_MIMXRT798S_CM33_CPU1
+
+config NUM_IRQS
+	default 93
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 100000000 if CORTEX_M_SYSTICK
+	default 1000000 if MCUX_OS_TIMER
+
+endif # SOC_MIMXRT798S_CM33_CPU1
+
+config MFD
+	default y
+	depends on DT_HAS_NXP_LP_FLEXCOMM_ENABLED
+
+if SOC_MIMXRT798S_HIFI4
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config XTENSA_TIMER
+	default y
+
+config XTENSA_CCOUNT_HZ
+	default SYS_CLOCK_HW_CYCLES_PER_SEC
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 1000
+
+config GEN_IRQ_VECTOR_TABLE
+	default n
+
+config NXP_IMXRT_BOOT_HEADER
+	default n
+
+endif # SOC_MIMXRT798S_HIFI4
+
+if SOC_MIMXRT798S_HIFI1
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config XTENSA_TIMER
+	default y
+
+config GEN_IRQ_VECTOR_TABLE
+	default n
+
+config NXP_IMXRT_BOOT_HEADER
+	default n
+
+config XTENSA_CCOUNT_HZ
+	default SYS_CLOCK_HW_CYCLES_PER_SEC
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 1000
+
+endif # SOC_MIMXRT798S_HIFI1
diff --git a/soc/nxp/imxrt/imxrt7xx/Kconfig.soc b/soc/nxp/imxrt/imxrt7xx/Kconfig.soc
new file mode 100644
index 00000000000..384f99cdb6a
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/Kconfig.soc
@@ -0,0 +1,67 @@
+# Copyright 2024-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_IMXRT7XX
+	bool
+	select SOC_FAMILY_NXP_IMXRT
+
+config SOC_MIMXRT798S
+	bool
+	select SOC_SERIES_IMXRT7XX
+
+config SOC_SERIES
+	default "imxrt7xx" if SOC_SERIES_IMXRT7XX
+
+config SOC
+	default "mimxrt798s" if SOC_MIMXRT798S
+
+config SOC_MIMXRT798S_CM33_CPU0
+	bool
+	select SOC_MIMXRT798S
+
+config SOC_MIMXRT798S_CM33_CPU1
+	bool
+	select SOC_MIMXRT798S
+
+config SOC_MIMXRT798S_HIFI4
+	bool
+	select SOC_MIMXRT798S
+	help
+	  NXP i.MXRT7xx HiFi4 DSP Core
+
+config SOC_MIMXRT798S_HIFI1
+	bool
+	select SOC_MIMXRT798S
+	help
+	  NXP i.MXRT7xx HiFi1 DSP Core
+
+config SOC_TOOLCHAIN_NAME
+	string
+	default "nxp_rt700_hifi4" if SOC_MIMXRT798S_HIFI4
+	default "nxp_rt700_hifi1" if SOC_MIMXRT798S_HIFI1
+
+config SOC_PART_NUMBER_MIMXRT798SGAWAR
+	bool
+
+config SOC_PART_NUMBER_MIMXRT798SGFOA
+	bool
+
+config SOC_PART_NUMBER_MIMXRT758SGAWAR
+	bool
+
+config SOC_PART_NUMBER_MIMXRT758SGFOA
+	bool
+
+config SOC_PART_NUMBER_MIMXRT735SGAWAR
+	bool
+
+config SOC_PART_NUMBER_MIMXRT735SGFOA
+	bool
+
+config SOC_PART_NUMBER
+	default "MIMXRT798SGFOA" if SOC_PART_NUMBER_MIMXRT798SGFOA
+	default "MIMXRT798SGAWAR" if SOC_PART_NUMBER_MIMXRT798SGAWAR
+	default "MIMXRT758SGFOA" if SOC_PART_NUMBER_MIMXRT758SGFOA
+	default "MIMXRT758SGAWAR" if SOC_PART_NUMBER_MIMXRT758SGAWAR
+	default "MIMXRT735SGFOA" if SOC_PART_NUMBER_MIMXRT735SGFOA
+	default "MIMXRT735SGAWAR" if SOC_PART_NUMBER_MIMXRT735SGAWAR
diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/CMakeLists.txt b/soc/nxp/imxrt/imxrt7xx/cm33/CMakeLists.txt
new file mode 100644
index 00000000000..5bb16ce1e04
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/cm33/CMakeLists.txt
@@ -0,0 +1,26 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_compile_definitions_ifdef(CONFIG_NXP_LP_FLEXCOMM LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER=1)
+zephyr_compile_definitions_ifdef(CONFIG_UDC_DRIVER USB_DEVICE_CONFIG_BUFFER_PROPERTY_CACHEABLE=1)
+
+zephyr_compile_definitions(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE)
+
+zephyr_include_directories(.)
+
+zephyr_sources(soc.c)
+
+if(CONFIG_FLASH_MCUX_XSPI_XIP)
+  zephyr_sources(flash_clock_setup.c)
+  zephyr_code_relocate(FILES flash_clock_setup.c LOCATION ${CONFIG_FLASH_MCUX_XSPI_XIP_MEM}_TEXT)
+endif()
+
+zephyr_library_include_directories(
+  ${ZEPHYR_BASE}/kernel/include
+  ${ZEPHYR_BASE}/arch/${ARCH}/include
+  )
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/flash_clock_setup.c b/soc/nxp/imxrt/imxrt7xx/cm33/flash_clock_setup.c
new file mode 100644
index 00000000000..65b7021268b
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/cm33/flash_clock_setup.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright 2024-2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <fsl_common.h>
+#include <fsl_clock.h>
+
+#ifdef CONFIG_HAS_MCUX_CACHE
+#include <fsl_cache.h>
+#endif
+
+static void enable_xspi_cache(CACHE64_CTRL_Type *cache)
+{
+	/* First, invalidate the entire cache. */
+	cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK |
+		      CACHE64_CTRL_CCR_GO_MASK;
+	while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) {
+	}
+	/* As a precaution clear the bits to avoid inadvertently re-running this command. */
+	cache->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK);
+	/* Now enable the cache. */
+	cache->CCR |= CACHE64_CTRL_CCR_ENCACHE_MASK;
+}
+
+static void disable_xspi_cache(CACHE64_CTRL_Type *cache)
+{
+	cache->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK |
+		      CACHE64_CTRL_CCR_GO_MASK; /* First, clean XSPI cache. */
+	while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) {
+	}
+	/* As a precaution clear the bits to avoid inadvertently re-running this command. */
+	cache->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK);
+
+	/* Now disable XSPI cache. */
+	cache->CCR &= ~CACHE64_CTRL_CCR_ENCACHE_MASK;
+}
+
+static void flash_deinit(XSPI_Type *base, CACHE64_CTRL_Type *cache)
+{
+	if (base == XSPI0) {
+		/* Enable clock again. */
+		CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_CLR_XSPI0_MASK;
+	} else if (base == XSPI1) {
+		/* Enable clock again. */
+		CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_CLR_XSPI1_MASK;
+	}
+
+	base->MCR &= ~XSPI_MCR_MDIS_MASK;
+	if ((cache->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) != 0x00U) {
+		disable_xspi_cache(cache);
+	}
+	/* Wait until XSPI is not busy */
+	while ((base->SR & XSPI_SR_BUSY_MASK) != 0U) {
+	}
+	/* Disable module. */
+	base->MCR |= XSPI_MCR_MDIS_MASK;
+}
+
+static void flash_init(XSPI_Type *base, CACHE64_CTRL_Type *cache)
+{
+	/* Enable XSPI module */
+	base->MCR |= XSPI_MCR_MDIS_MASK;
+
+	base->MCR |= XSPI_MCR_SWRSTSD_MASK | XSPI_MCR_SWRSTHD_MASK;
+	for (uint32_t i = 0; i < 6; i++) {
+		__NOP();
+	}
+	base->MCR &= ~(XSPI_MCR_SWRSTSD_MASK | XSPI_MCR_SWRSTHD_MASK);
+	base->MCR |= XSPI_MCR_IPS_TG_RST_MASK | XSPI_MCR_MDIS_MASK;
+	base->MCR &= ~XSPI_MCR_ISD3FA_MASK;
+	base->MCR &= ~XSPI_MCR_MDIS_MASK;
+	base->MCR |= XSPI_MCR_MDIS_MASK;
+	base->MCR |= XSPI_MCR_ISD3FA_MASK;
+	base->MCR &= ~XSPI_MCR_MDIS_MASK;
+
+	base->MCR |= XSPI_MCR_MDIS_MASK;
+	base->SMPR = (((base->SMPR) & (~XSPI_SMPR_DLLFSMPFA_MASK)) |
+		      XSPI_SMPR_DLLFSMPFA(FSL_FEATURE_XSPI_DLL_REF_VALUE_DDR_DELAY_TAP_NUM));
+	base->MCR &= ~XSPI_MCR_MDIS_MASK;
+
+	base->DLLCR[0] &=
+		~(XSPI_DLLCR_SLV_DLL_BYPASS_MASK | XSPI_DLLCR_DLL_CDL8_MASK |
+		  XSPI_DLLCR_SLV_DLY_OFFSET_MASK | XSPI_DLLCR_SLV_FINE_OFFSET_MASK |
+		  XSPI_DLLCR_DLLRES_MASK | XSPI_DLLCR_DLL_REFCNTR_MASK | XSPI_DLLCR_FREQEN_MASK);
+	base->DLLCR[0] &=
+		~(XSPI_DLLCR_SLV_EN_MASK | XSPI_DLLCR_SLAVE_AUTO_UPDT_MASK | XSPI_DLLCR_DLLEN_MASK);
+	/* Enable subordinate as auto update mode. */
+	base->DLLCR[0] |= XSPI_DLLCR_SLV_EN_MASK | XSPI_DLLCR_SLAVE_AUTO_UPDT_MASK;
+	/* program DLL to desired delay. */
+	base->DLLCR[0] |= XSPI_DLLCR_DLLRES(FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_RES) |
+		XSPI_DLLCR_DLL_REFCNTR(2U) | XSPI_DLLCR_DLL_CDL8(1U) | XSPI_DLLCR_FREQEN(1U) |
+		XSPI_DLLCR_SLV_FINE_OFFSET(0) | XSPI_DLLCR_SLV_DLY_OFFSET(0);
+	/* Load above settings into delay chain. */
+	base->DLLCR[0] |= XSPI_DLLCR_SLV_UPD_MASK;
+	base->DLLCR[0] |= XSPI_DLLCR_DLLEN_MASK;
+	base->DLLCR[0] &= ~XSPI_DLLCR_SLV_UPD_MASK;
+
+	while ((base->DLLSR & XSPI_DLLSR_SLVA_LOCK_MASK) == 0UL) {
+	}
+
+	if ((cache->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) == 0x00U) {
+		enable_xspi_cache(cache);
+		/* flush pipeline */
+		__DSB();
+		__ISB();
+	}
+}
+
+/* xspi_setup_clock run in RAM when XIP. */
+void xspi_setup_clock(XSPI_Type *base, uint32_t src, uint32_t divider)
+{
+	if (base == XSPI0) {
+		if ((CLKCTL0->XSPI0FCLKSEL != CLKCTL0_XSPI0FCLKSEL_SEL(src)) ||
+		    ((CLKCTL0->XSPI0FCLKDIV & CLKCTL0_XSPI0FCLKDIV_DIV_MASK) != (divider - 1))) {
+			/* Always deinit XSPI and init XSPI for the flash to make
+			 * sure the flash works correctly after the XSPI root clock
+			 * changed as the default XSPI configuration may does not
+			 * work for the new root clock frequency.
+			 */
+			flash_deinit(base, CACHE64_CTRL0);
+
+			/* Disable clock before changing clock source */
+			CLKCTL0->PSCCTL1_CLR = CLKCTL0_PSCCTL1_CLR_XSPI0_MASK;
+			/* Update XSPI clock. */
+			CLKCTL0->XSPI0FCLKSEL =
+				CLKCTL0_XSPI0FCLKSEL_SEL(src) | CLKCTL0_XSPI0FCLKSEL_SEL_EN_MASK;
+			CLKCTL0->XSPI0FCLKDIV = CLKCTL0_XSPI0FCLKDIV_DIV(divider - 1);
+			while ((CLKCTL0->XSPI0FCLKDIV) & CLKCTL0_XSPI0FCLKDIV_REQFLAG_MASK) {
+			}
+			/* Enable XSPI clock again */
+			CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_SET_XSPI0_MASK;
+
+			flash_init(base, CACHE64_CTRL0);
+		}
+	} else if (base == XSPI1) {
+		if ((CLKCTL0->XSPI1FCLKSEL != CLKCTL0_XSPI1FCLKSEL_SEL(src)) ||
+		    ((CLKCTL0->XSPI1FCLKDIV & CLKCTL0_XSPI1FCLKDIV_DIV_MASK) != (divider - 1))) {
+			/* Always deinit XSPI and init XSPI for the flash to make sure the flash
+			 * works correctly after the XSPI root clock changed as the default XSPI
+			 * configuration may does not work for the new root clock frequency.
+			 */
+			flash_deinit(base, CACHE64_CTRL1);
+
+			/* Disable clock before changing clock source */
+			CLKCTL0->PSCCTL1_CLR = CLKCTL0_PSCCTL1_CLR_XSPI1_MASK;
+			/* Update XSPI clock. */
+			CLKCTL0->XSPI1FCLKSEL =
+				CLKCTL0_XSPI1FCLKSEL_SEL(src) | CLKCTL0_XSPI1FCLKSEL_SEL_EN_MASK;
+			CLKCTL0->XSPI1FCLKDIV = CLKCTL0_XSPI1FCLKDIV_DIV(divider - 1);
+			while ((CLKCTL0->XSPI1FCLKDIV) & CLKCTL0_XSPI1FCLKDIV_REQFLAG_MASK) {
+			}
+			/* Enable XSPI clock again */
+			CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_SET_XSPI1_MASK;
+
+			flash_init(base, CACHE64_CTRL1);
+		}
+	}
+}
+
+void xspi_clock_safe_config(void)
+{
+	xspi_setup_clock(XSPI0, 0U, 1U);
+	xspi_setup_clock(XSPI1, 0U, 1U);
+}
diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/pinctrl_soc.h b/soc/nxp/imxrt/imxrt7xx/cm33/pinctrl_soc.h
new file mode 100644
index 00000000000..35f048dd0e6
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/cm33/pinctrl_soc.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT7XX_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_ARM_NXP_IMX_RT7XX_PINCTRL_SOC_H_
+
+#include <zephyr/devicetree.h>
+#include <zephyr/types.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @cond INTERNAL_HIDDEN */
+
+typedef uint32_t pinctrl_soc_pin_t;
+
+#define IOPCTL_PIO_PUPDENA_MASK (0x10U)
+#define IOPCTL_PIO_PUPDSEL_MASK (0x20U)
+
+#define IOPCTL_PIO_ODENA_MASK  (0x400U)
+#define IOPCTL_PIO_ODENA_SHIFT (10U)
+#define IOPCTL_PIO_ODENA(x)                                                                        \
+	(((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_ODENA_SHIFT)) & IOPCTL_PIO_ODENA_MASK)
+
+#define IOPCTL_PIO_IBENA_MASK  (0x40U)
+#define IOPCTL_PIO_IBENA_SHIFT (6U)
+#define IOPCTL_PIO_IBENA(x)                                                                        \
+	(((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_IBENA_SHIFT)) & IOPCTL_PIO_IBENA_MASK)
+
+/* Please note there is no SLEWRATE attribution on IOPCTL2 */
+#define IOPCTL_PIO_SLEWRATE_MASK  (0x80U)
+#define IOPCTL_PIO_SLEWRATE_SHIFT (7U)
+#define IOPCTL_PIO_SLEWRATE(x)                                                                     \
+	(((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_SLEWRATE_SHIFT)) & IOPCTL_PIO_SLEWRATE_MASK)
+
+/* Please note there is no FULLDRIVE attribution on IOPCTL2 */
+#define IOPCTL_PIO_FULLDRIVE_MASK  (0x100U)
+#define IOPCTL_PIO_FULLDRIVE_SHIFT (8U)
+#define IOPCTL_PIO_FULLDRIVE(x)                                                                    \
+	(((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_FULLDRIVE_SHIFT)) & IOPCTL_PIO_FULLDRIVE_MASK)
+
+#define IOPCTL_PIO_IIENA_MASK  (0x800U)
+#define IOPCTL_PIO_IIENA_SHIFT (11U)
+#define IOPCTL_PIO_IIENA(x)                                                                        \
+	(((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_IIENA_SHIFT)) & IOPCTL1_PIO_IIENA_MASK)
+
+/* Please note there is no AMENA attribution on IOPCTL2 */
+#define IOPCTL_PIO_AMENA_MASK  (0x200U)
+#define IOPCTL_PIO_AMENA_SHIFT (9U)
+#define IOPCTL_PIO_AMENA(x)                                                                        \
+	(((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_AMENA_SHIFT)) & IOPCTL_PIO_AMENA_MASK)
+
+#define Z_PINCTRL_IOPCTL_PINCFG(node_id)                                                           \
+	(IF_ENABLED(DT_PROP(node_id, bias_pull_down),				\
+	(IOPCTL_PIO_PUPDENA_MASK |))                                    /* pull down */     \
+		IF_ENABLED(DT_PROP(node_id, bias_pull_up),				\
+	(IOPCTL_PIO_PUPDENA_MASK | IOPCTL_PIO_PUPDSEL_MASK |))    /* pull up */       \
+			IOPCTL_PIO_ODENA(DT_PROP(node_id, drive_open_drain)) | /* open drain */    \
+			IOPCTL_PIO_IBENA(DT_PROP(node_id, input_enable)) |     /* input buffer */  \
+			IOPCTL_PIO_SLEWRATE(DT_ENUM_IDX(node_id, slew_rate)) | /* slew rate */     \
+			IOPCTL_PIO_FULLDRIVE(                                                      \
+				DT_ENUM_IDX(node_id, drive_strength)) |  /* drive strength */      \
+			IOPCTL_PIO_IIENA(DT_PROP(node_id, nxp_invert)) | /* invert input */        \
+			IOPCTL_PIO_AMENA(                                                          \
+				DT_PROP(node_id, nxp_analog_mode))) /* analog multiplexor */
+
+/* MCUX RT parts only have one pin type */
+#define Z_PINCTRL_IOCON_D_PIN_MASK (0xFFF)
+#define Z_PINCTRL_IOCON_A_PIN_MASK (0)
+#define Z_PINCTRL_IOCON_I_PIN_MASK (0)
+
+#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx)                                             \
+	DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_IOPCTL_PINCFG(group),
+
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)                                                   \
+	{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux,           \
+				Z_PINCTRL_STATE_PIN_INIT)}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT7XX_PINCTRL_SOC_H_ */
diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/soc.c b/soc/nxp/imxrt/imxrt7xx/cm33/soc.c
new file mode 100644
index 00000000000..bfe5e5a404b
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/cm33/soc.c
@@ -0,0 +1,109 @@
+/*
+ * Copyright 2024,2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for NXP RT7XX platform
+ *
+ * This module provides routines to initialize and support board-level
+ * hardware for the RT7XX platforms.
+ */
+
+#include <zephyr/init.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/linker/sections.h>
+#include <zephyr/cache.h>
+#include <soc.h>
+#include "fsl_power.h"
+#include "fsl_clock.h"
+
+void soc_early_init_hook(void)
+{
+	/* Enable data cache */
+	sys_cache_data_enable();
+
+	__ISB();
+	__DSB();
+}
+
+#ifdef CONFIG_SOC_RESET_HOOK
+
+void soc_reset_hook(void)
+{
+	SystemInit();
+}
+
+#endif /* CONFIG_SOC_RESET_HOOK */
+
+#ifdef CONFIG_MIPI_DSI
+/* Weak so board can override this function */
+void __weak imxrt_pre_init_display_interface(void)
+{
+	/* Assert MIPI control reset. */
+	RESET_SetPeripheralReset(kMIPI_DSI_CTRL_RST_SHIFT_RSTn);
+
+	/* Disable MIPI DSI power down. */
+	POWER_DisablePD(kPDRUNCFG_APD_MIPIDSI);
+	POWER_DisablePD(kPDRUNCFG_PPD_MIPIDSI);
+	POWER_DisablePD(kPDRUNCFG_PD_VDD2_MIPI);
+
+	/* Apply power down configuration. */
+	POWER_ApplyPD();
+
+	/* Configure MIPY ESC clock. */
+	/* Use PLL PFD1 as clock source, 396m. */
+	CLOCK_AttachClk(kMAIN_PLL_PFD1_to_MIPI_DPHYESC_CLK);
+	/* RxClkEsc min 60MHz, TxClkEsc 12 to 20MHz. */
+	/* RxClkEsc = 396MHz / 6 = 66MHz. */
+	CLOCK_SetClkDiv(kCLOCK_DivDphyEscRxClk, 6);
+	/* TxClkEsc = 396MHz / 6 / 4 = 16.5MHz. */
+	CLOCK_SetClkDiv(kCLOCK_DivDphyEscTxClk, 4);
+
+#ifdef CONFIG_MIPI_DBI
+	/* When using LCDIF, with 279.53MHz DBI source clock and 16bpp format, a 14 wr
+	 * period requires a 279.53MHz / 14 * 16 = 319.46Mhz DPHY clk source. Considering
+	 * the DCS packaging cost, the MIPI DPHY speed shall be ***SLIGHTLY*** larger
+	 * than the DBI interface speed. DPHY uses AUDIO_PLL_PFD2 which is 532.48MHz as
+	 * source, the frequency is 532.48 * 18 / 30 = 319.49MHz, which meets the
+	 * requirement.
+	 */
+	uint32_t mipiDsiDphyBitClkFreq_Hz =
+			DT_PROP(DT_NODELABEL(lcdif), clock_frequency) /
+			DT_PROP_OR(DT_NODELABEL(lcdif), divider, 1) /
+			DT_PROP(DT_NODELABEL(lcdif), wr_period) * 16U;
+#else
+	/* The DPHY bit clock must be fast enough to send out the pixels, it should be
+	 * larger than:
+	 * (Pixel clock * bit per output pixel) / number of MIPI data lane
+	 * DPHY uses AUDIO pll pfd2 as aource, and its max allowed clock frequency is
+	 * 532.48 x 18 / 16 = 599.04MHz. The MIPI panel supports up to 850MHz bit clock.
+	 */
+	uint32_t mipiDsiDphyBitClkFreq_Hz = DT_PROP(DT_NODELABEL(mipi_dsi), phy_clock);
+#endif
+	uint8_t clockDiv = (uint8_t)((uint64_t)CLOCK_GetAudioPllFreq() * 18U /
+					(uint64_t)mipiDsiDphyBitClkFreq_Hz);
+
+	CLOCK_InitAudioPfd(kCLOCK_Pfd2, clockDiv);
+
+	CLOCK_AttachClk(kAUDIO_PLL_PFD2_to_MIPI_DSI_HOST_PHY);
+	CLOCK_SetClkDiv(kCLOCK_DivDphyClk, 1);
+}
+
+void __weak imxrt_post_init_display_interface(void)
+{
+	/* Clear MIPI control reset. */
+	RESET_ClearPeripheralReset(kMIPI_DSI_CTRL_RST_SHIFT_RSTn);
+}
+
+void __weak imxrt_deinit_display_interface(void)
+{
+	/* Assert MIPI DSI reset */
+	RESET_SetPeripheralReset(kMIPI_DSI_CTRL_RST_SHIFT_RSTn);
+	/* Remove clock from DPHY */
+	CLOCK_AttachClk(kNONE_to_MIPI_DSI_HOST_PHY);
+}
+
+#endif
diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/soc.h b/soc/nxp/imxrt/imxrt7xx/cm33/soc.h
new file mode 100644
index 00000000000..0a5cafcfbfa
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/cm33/soc.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Board configuration macros for the MIMXRT7XX platform
+ *
+ * This header file is used to specify and describe board-level aspects for the
+ * 'MIMXRT7XX' platform.
+ */
+
+#ifndef _SOC__H_
+#define _SOC__H_
+
+#ifndef _ASMLANGUAGE
+
+#include <zephyr/sys/util.h>
+#include <fsl_common.h>
+
+/* CPU 0 has an instruction and data cache, provide the defines for XCACHE */
+#ifdef CONFIG_SOC_MIMXRT798S_CM33_CPU0
+#define NXP_XCACHE_INSTR XCACHE1
+#define NXP_XCACHE_DATA XCACHE0
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void xspi_clock_safe_config(void);
+void xspi_setup_clock(XSPI_Type *base, uint32_t src, uint32_t divider);
+
+#ifdef CONFIG_MIPI_DSI
+void imxrt_pre_init_display_interface(void);
+
+void imxrt_post_init_display_interface(void);
+
+void imxrt_deinit_display_interface(void);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _SOC__H_ */
diff --git a/soc/nxp/imxrt/imxrt7xx/hifi1/CMakeLists.txt b/soc/nxp/imxrt/imxrt7xx/hifi1/CMakeLists.txt
new file mode 100644
index 00000000000..1c10b21b9ea
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/hifi1/CMakeLists.txt
@@ -0,0 +1,9 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include)
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")
diff --git a/soc/nxp/imxrt/imxrt7xx/hifi1/include/dsp/cache.h b/soc/nxp/imxrt/imxrt7xx/hifi1/include/dsp/cache.h
new file mode 100644
index 00000000000..d67fca16f87
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/hifi1/include/dsp/cache.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __COMMON_DSP_CACHE_H__
+#define __COMMON_DSP_CACHE_H__
+
+#include <xtensa/hal.h>
+
+#endif
diff --git a/soc/nxp/imxrt/imxrt7xx/hifi1/include/dsp/io.h b/soc/nxp/imxrt/imxrt7xx/hifi1/include/dsp/io.h
new file mode 100644
index 00000000000..7bdd1c5ad27
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/hifi1/include/dsp/io.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INCLUDE_IO__
+#define __INCLUDE_IO__
+
+#include <stdint.h>
+#include <soc/memory.h>
+#include <zephyr/sys/sys_io.h>
+#include <zephyr/arch/common/sys_io.h>
+
+static inline uint32_t io_reg_read(uint32_t reg)
+{
+	return sys_read32(reg);
+}
+
+static inline void io_reg_write(uint32_t reg, uint32_t val)
+{
+	sys_write32(val, reg);
+}
+
+static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, uint32_t value)
+{
+	io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask));
+}
+
+static inline uint16_t io_reg_read16(uint32_t reg)
+{
+	return sys_read16(reg);
+}
+
+static inline void io_reg_write16(uint32_t reg, uint16_t val)
+{
+	sys_write16(val, reg);
+}
+
+#endif
diff --git a/soc/nxp/imxrt/imxrt7xx/hifi1/include/soc.h b/soc/nxp/imxrt/imxrt7xx/hifi1/include/soc.h
new file mode 100644
index 00000000000..f4b7380d84e
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/hifi1/include/soc.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include <errno.h>
+
+#include <zephyr/sys/sys_io.h>
+#include <dsp/cache.h>
+
+#ifndef __INC_IMXRT_SOC_H
+#define __INC_IMXRT_SOC_H
+
+/* Macros related to interrupt handling */
+#define XTENSA_IRQ_NUM_SHIFT 0
+#define XTENSA_IRQ_NUM_MASK  0xff
+
+/*
+ * IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00.
+ *
+ * 1. Peripheral Register bit offset.
+ */
+#define XTENSA_IRQ_NUMBER(_irq) ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
+
+extern void z_soc_irq_enable(uint32_t irq);
+extern void z_soc_irq_disable(uint32_t irq);
+extern int z_soc_irq_is_enabled(unsigned int irq);
+
+#endif /* __INC_IMXRT_SOC_H */
diff --git a/soc/nxp/imxrt/imxrt7xx/hifi1/include/soc/memory.h b/soc/nxp/imxrt/imxrt7xx/hifi1/include/soc/memory.h
new file mode 100644
index 00000000000..0ddd29f3865
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/hifi1/include/soc/memory.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __XTENSA_MEMORY_H__
+#define __XTENSA_MEMORY_H__
+
+#include <zephyr/autoconf.h>
+
+#define IRAM_RESERVE_HEADER_SPACE 0x400
+
+#define IRAM0_BASE 0x00580000
+#define IRAM0_SIZE 0x8000
+
+#define IRAM1_BASE 0x00680000
+#define IRAM1_SIZE 0x80000
+
+#define DRAM_BASE 0x20700000
+#define DRAM_SIZE 0x80000
+
+/* The reset vector address in IRAM and its size. */
+#define XCHAL_RESET_VECTOR0_PADDR_IRAM IRAM0_BASE
+#define MEM_RESET_TEXT_SIZE            (0x2E0)
+#define MEM_RESET_LIT_SIZE             (0x120)
+
+/* Base address of all interrupt vectors in IRAM. */
+#define XCHAL_VECBASE_RESET_PADDR_IRAM (IRAM0_BASE + IRAM_RESERVE_HEADER_SPACE)
+#define MEM_VECBASE_LIT_SIZE           (0x178)
+/* Vector and literal sizes. */
+#define MEM_VECT_LIT_SIZE  (0x4)
+#define MEM_VECT_TEXT_SIZE (0x1C)
+
+/* Addresses of the interrupt vectors. */
+#define XCHAL_INT_VECTOR_ADDR(x)          (XCHAL_VECBASE_RESET_PADDR_IRAM + (x))
+#define XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x17C))
+#define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x19C))
+#define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x1BC))
+#define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x1DC))
+#define XCHAL_KERNEL_VECTOR_PADDR_IRAM    (XCHAL_INT_VECTOR_ADDR(0x1FC))
+#define XCHAL_USER_VECTOR_PADDR_IRAM      (XCHAL_INT_VECTOR_ADDR(0x21C))
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x23C))
+
+/* Location for the intList section which is later used to construct the
+ * Interrupt Descriptor Table (IDT). This is a bogus address as this
+ * section will be stripped off in the final image.
+ */
+#define IDT_BASE (IRAM0_BASE + IRAM0_SIZE)
+
+/* Size of the Interrupt Descriptor Table (IDT). */
+#define IDT_SIZE (0x2000)
+
+#endif
diff --git a/soc/nxp/imxrt/imxrt7xx/hifi1/linker.ld b/soc/nxp/imxrt/imxrt7xx/hifi1/linker.ld
new file mode 100644
index 00000000000..7d8e2b7b03b
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/hifi1/linker.ld
@@ -0,0 +1,498 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+OUTPUT_ARCH(xtensa)
+
+#include <soc/memory.h>
+#include <xtensa/config/core-isa.h>
+
+#include <zephyr/linker/linker-defs.h>
+#include <zephyr/linker/linker-tool.h>
+#include <zephyr/linker/sections.h>
+
+#define RAMABLE_REGION dram :dram_phdr
+#define ROMABLE_REGION dram :dram_phdr
+
+MEMORY
+{
+  vector_reset_text :
+    org = XCHAL_RESET_VECTOR0_PADDR_IRAM,
+    len = MEM_RESET_TEXT_SIZE
+  vector_reset_lit :
+    org = XCHAL_RESET_VECTOR0_PADDR_IRAM + MEM_RESET_TEXT_SIZE,
+    len = MEM_RESET_LIT_SIZE
+  vector_base_text :
+    org = XCHAL_VECBASE_RESET_PADDR_IRAM,
+    len = MEM_VECBASE_LIT_SIZE
+  vector_int2_lit :
+    org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
+    len = MEM_VECT_LIT_SIZE
+  vector_int2_text :
+    org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM,
+    len = MEM_VECT_TEXT_SIZE
+  vector_int3_lit :
+    org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
+    len = MEM_VECT_LIT_SIZE
+  vector_int3_text :
+    org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM,
+    len = MEM_VECT_TEXT_SIZE
+  vector_int4_lit :
+    org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
+    len = MEM_VECT_LIT_SIZE
+  vector_int4_text :
+    org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM,
+    len = MEM_VECT_TEXT_SIZE
+  vector_int5_lit :
+    org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
+    len = MEM_VECT_LIT_SIZE
+  vector_int5_text :
+    org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM,
+    len = MEM_VECT_TEXT_SIZE
+  vector_kernel_lit :
+    org = XCHAL_KERNEL_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
+    len = MEM_VECT_LIT_SIZE
+  vector_kernel_text :
+    org = XCHAL_KERNEL_VECTOR_PADDR_IRAM,
+    len = MEM_VECT_TEXT_SIZE
+  vector_user_lit :
+    org = XCHAL_USER_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
+    len = MEM_VECT_LIT_SIZE
+  vector_user_text :
+    org = XCHAL_USER_VECTOR_PADDR_IRAM,
+    len = MEM_VECT_TEXT_SIZE
+  vector_double_lit :
+    org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
+    len = MEM_VECT_LIT_SIZE
+  vector_double_text :
+    org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM,
+    len = MEM_VECT_TEXT_SIZE
+  iram0_text :
+    org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE,
+    len = (IRAM0_BASE + IRAM0_SIZE) - (XCHAL_DOUBLEEXC_VECTOR_PADDR + MEM_VECT_TEXT_SIZE)
+  iram_text_start :
+    org = IRAM1_BASE,
+    len = IRAM1_SIZE
+  dram :
+    org = DRAM_BASE,
+    len = DRAM_SIZE
+#ifdef CONFIG_GEN_ISR_TABLES
+  IDT_LIST :
+    org = IDT_BASE,
+    len = IDT_SIZE
+#endif
+}
+
+PHDRS
+{
+  vector_reset_text_phdr PT_LOAD;
+  vector_reset_lit_phdr PT_LOAD;
+  vector_base_text_phdr PT_LOAD;
+  vector_base_lit_phdr PT_LOAD;
+  vector_int2_text_phdr PT_LOAD;
+  vector_int2_lit_phdr PT_LOAD;
+  vector_int3_text_phdr PT_LOAD;
+  vector_int3_lit_phdr PT_LOAD;
+  vector_int4_text_phdr PT_LOAD;
+  vector_int4_lit_phdr PT_LOAD;
+  vector_int5_text_phdr PT_LOAD;
+  vector_int5_lit_phdr PT_LOAD;
+  vector_kernel_text_phdr PT_LOAD;
+  vector_kernel_lit_phdr PT_LOAD;
+  vector_user_text_phdr PT_LOAD;
+  vector_user_lit_phdr PT_LOAD;
+  vector_double_text_phdr PT_LOAD;
+  vector_double_lit_phdr PT_LOAD;
+  iram0_text_phdr PT_LOAD;
+  iram_text_start_phdr PT_LOAD;
+  dram_phdr PT_LOAD;
+}
+
+/*  Default entry point:  */
+ENTRY(CONFIG_KERNEL_ENTRY)
+
+_rom_store_table = 0;
+
+PROVIDE(_memmap_reset_vector = XCHAL_RESET_VECTOR0_PADDR_IRAM);
+PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_IRAM);
+
+/* Various memory-map dependent cache attribute settings: */
+_memmap_cacheattr_wb_base = 0x00021022;
+_memmap_cacheattr_wt_base = 0x00021022;
+_memmap_cacheattr_bp_base = 0x00022022;
+_memmap_cacheattr_unused_mask = 0xFFF00F00;
+_memmap_cacheattr_wb_trapnull = 0x22221222;
+_memmap_cacheattr_wba_trapnull = 0x22221222;
+_memmap_cacheattr_wbna_trapnull = 0x22221222;
+_memmap_cacheattr_wt_trapnull = 0x22221222;
+_memmap_cacheattr_bp_trapnull = 0x22222222;
+_memmap_cacheattr_wb_strict = 0xFFF21F22;
+_memmap_cacheattr_wt_strict = 0xFFF21F22;
+_memmap_cacheattr_bp_strict = 0xFFF22F22;
+_memmap_cacheattr_wb_allvalid = 0x22221222;
+_memmap_cacheattr_wt_allvalid = 0x22221222;
+_memmap_cacheattr_bp_allvalid = 0x22222222;
+_memmap_region_map = 0x0000001B;
+PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
+
+SECTIONS
+{
+
+#include <zephyr/linker/rel-sections.ld>
+
+ .ResetVector.text : ALIGN(4)
+  {
+    _ResetVector_text_start = ABSOLUTE(.);
+    KEEP (*(.ResetVector.text))
+    _ResetVector_text_end = ABSOLUTE(.);
+  } >vector_reset_text :vector_reset_text_phdr
+
+  .ResetVector.literal : ALIGN(4)
+  {
+    _ResetVector_literal_start = ABSOLUTE(.);
+    *(.ResetVector.literal)
+    _ResetVector_literal_end = ABSOLUTE(.);
+  } >vector_reset_lit :vector_reset_lit_phdr
+
+  .WindowVectors.text : ALIGN(4)
+  {
+    _WindowVectors_text_start = ABSOLUTE(.);
+    KEEP (*(.WindowVectors.text))
+    _WindowVectors_text_end = ABSOLUTE(.);
+  } >vector_base_text :vector_base_text_phdr
+
+  .Level2InterruptVector.literal : ALIGN(4)
+  {
+    _Level2InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level2InterruptVector.literal)
+    _Level2InterruptVector_literal_end = ABSOLUTE(.);
+  } >vector_int2_lit :vector_int2_lit_phdr
+
+  .Level2InterruptVector.text : ALIGN(4)
+  {
+    _Level2InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level2InterruptVector.text))
+    _Level2InterruptVector_text_end = ABSOLUTE(.);
+  } >vector_int2_text :vector_int2_text_phdr
+
+  .Level3InterruptVector.literal : ALIGN(4)
+  {
+    _Level3InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level3InterruptVector.literal)
+    _Level3InterruptVector_literal_end = ABSOLUTE(.);
+  } >vector_int3_lit :vector_int3_lit_phdr
+
+  .Level3InterruptVector.text : ALIGN(4)
+  {
+    _Level3InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level3InterruptVector.text))
+    _Level3InterruptVector_text_end = ABSOLUTE(.);
+  } >vector_int3_text :vector_int3_text_phdr
+
+  .DebugExceptionVector.literal : ALIGN(4)
+  {
+    _DebugExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DebugExceptionVector.literal)
+    _DebugExceptionVector_literal_end = ABSOLUTE(.);
+  } >vector_int4_lit :vector_int4_lit_phdr
+
+  .DebugExceptionVector.text : ALIGN(4)
+  {
+    _DebugExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DebugExceptionVector.text))
+    _DebugExceptionVector_text_end = ABSOLUTE(.);
+  } >vector_int4_text :vector_int4_text_phdr
+
+  .NMIExceptionVector.literal : ALIGN(4)
+  {
+    _NMIExceptionVector_literal_start = ABSOLUTE(.);
+    *(.NMIExceptionVector.literal)
+    _NMIExceptionVector_literal_end = ABSOLUTE(.);
+  } >vector_int5_lit :vector_int5_lit_phdr
+
+  .NMIExceptionVector.text : ALIGN(4)
+  {
+    _NMIExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.NMIExceptionVector.text))
+    _NMIExceptionVector_text_end = ABSOLUTE(.);
+  } >vector_int5_text :vector_int5_text_phdr
+
+  .KernelExceptionVector.literal : ALIGN(4)
+  {
+    _KernelExceptionVector_literal_start = ABSOLUTE(.);
+    *(.KernelExceptionVector.literal)
+    _KernelExceptionVector_literal_end = ABSOLUTE(.);
+  } >vector_kernel_lit :vector_kernel_lit_phdr
+
+  .KernelExceptionVector.text : ALIGN(4)
+  {
+    _KernelExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.KernelExceptionVector.text))
+    _KernelExceptionVector_text_end = ABSOLUTE(.);
+  } >vector_kernel_text :vector_kernel_text_phdr
+
+  .UserExceptionVector.literal : ALIGN(4)
+  {
+    _UserExceptionVector_literal_start = ABSOLUTE(.);
+    *(.UserExceptionVector.literal)
+    _UserExceptionVector_literal_end = ABSOLUTE(.);
+  } >vector_user_lit :vector_user_lit_phdr
+
+  .UserExceptionVector.text : ALIGN(4)
+  {
+    _UserExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.UserExceptionVector.text))
+    _UserExceptionVector_text_end = ABSOLUTE(.);
+  } >vector_user_text :vector_user_text_phdr
+
+  .DoubleExceptionVector.literal : ALIGN(4)
+  {
+    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DoubleExceptionVector.literal)
+    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
+  } >vector_double_lit :vector_double_lit_phdr
+
+  .DoubleExceptionVector.text : ALIGN(4)
+  {
+    _DoubleExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DoubleExceptionVector.text))
+    _DoubleExceptionVector_text_end = ABSOLUTE(.);
+  } >vector_double_text :vector_double_text_phdr
+
+  .iram0.text : ALIGN(4)
+  {
+    _iram0_text_start = ABSOLUTE(.);
+    *(.iram0.text)
+    *(.iram.text)
+    . = ALIGN (4);
+    _iram0_text_end = ABSOLUTE(.);
+  } >iram0_text :iram0_text_phdr
+
+  .text : ALIGN(4)
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    KEEP (*(.ResetVector.text))
+    *(.ResetVector.literal)
+    *(.entry.text)
+    *(.init.literal)
+    KEEP(*(.init))
+    *(.literal.sort.* SORT(.text.sort.*))
+    KEEP (*(.literal.keepsort.* SORT(.text.keepsort.*) .literal.keep.* .text.keep.* .literal.*personality* .text.*personality*))
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.fini.literal)
+    KEEP(*(.fini))
+    *(.gnu.version)
+    . = ALIGN (4);
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } >iram_text_start :iram_text_start_phdr
+
+  _memmap_mem_iram_max = ABSOLUTE(.);
+
+  .rodata : ALIGN(4)
+  {
+    __rodata_region_start = ABSOLUTE(.);
+    *(.rodata)
+    *(SORT(.rodata.sort.*))
+    KEEP (*(SORT(.rodata.keepsort.*) .rodata.keep.*))
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
+    KEEP (*(.xt_except_table))
+    KEEP (*(.gcc_except_table))
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    PROVIDE (__eh_frame_start = .);
+    KEEP (*(.eh_frame))
+    PROVIDE (__eh_frame_end = .);
+    /*  C++ constructor and destructor tables, properly ordered:  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
+    _bss_table_start = ABSOLUTE(.);
+    LONG(_bss_start)
+    LONG(_bss_end)
+    _bss_table_end = ABSOLUTE(.);
+    . = ALIGN (4);
+    __rodata_region_end = ABSOLUTE(.);
+  } >dram :dram_phdr
+
+  .module_init : ALIGN(4)
+  {
+   _module_init_start = ABSOLUTE(.);
+    *(*.initcall)
+    _module_init_end = ABSOLUTE(.);
+  } >dram :dram_phdr
+
+  .noinit : ALIGN(4)
+  {
+    *(.noinit)
+    *(.noinit.*)
+  } >dram :dram_phdr
+
+  .data : ALIGN(4)
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data)
+    *(SORT(.data.sort.*))
+    KEEP (*(SORT(.data.keepsort.*) .data.keep.*))
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    KEEP(*(.gnu.linkonce.d.*personality*))
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.sdata2)
+    *(.sdata2.*)
+    *(.gnu.linkonce.s2.*)
+    KEEP(*(.jcr))
+    *(__llvm_prf_cnts)
+    *(__llvm_prf_data)
+    *(__llvm_prf_vnds)
+    . = ALIGN (4);
+    _data_end = ABSOLUTE(.);
+  } >dram :dram_phdr
+
+  __llvm_prf_names : ALIGN(4)
+  {
+    __llvm_prf_names_start = ABSOLUTE(.);
+    *(__llvm_prf_names)
+    . = ALIGN (4);
+    __llvm_prf_names_end = ABSOLUTE(.);
+  } >dram :dram_phdr
+
+  .note.gnu.build-id : ALIGN(4)
+  {
+    _note_gnu_build-id_start = ABSOLUTE(.);
+    *(.note.gnu.build-id)
+    . = ALIGN (4);
+    _note_gnu_build-id_end = ABSOLUTE(.);
+  } >dram :dram_phdr
+
+  .bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(SORT(.bss.sort.*))
+    KEEP (*(SORT(.bss.keepsort.*) .bss.keep.*))
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    *(.clib.bss)
+    *(.clib.percpu.bss)
+    *(.rtos.percpu.bss)
+    *(.rtos.bss)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+    _end = ALIGN(0x8);
+    PROVIDE(end = ALIGN(0x8));
+    _stack_sentry = ALIGN(0x8);
+    _memmap_seg_dsp_core_end = ALIGN(0x8);
+  } >dram :dram_phdr
+
+  .heap_mem (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _heap_mem_start = ABSOLUTE(.);
+    *(*.heap_mem)
+    _heap_mem_end = ABSOLUTE(.);
+  } >dram :dram_phdr
+
+  /* stack */
+  _end = ALIGN (8);
+
+  _heap_sentry = DRAM_BASE + DRAM_SIZE - 0x1000;
+  __stack = DRAM_BASE + DRAM_SIZE - 0x1000;
+  .comment  0 :  { *(.comment) }
+  .debug  0 :  { *(.debug) }
+  .line  0 :  { *(.line) }
+  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
+  .debug_sfnames  0 :  { *(.debug_sfnames) }
+  .debug_aranges  0 :  { *(.debug_aranges) }
+  .debug_ranges   0 :  { *(.debug_ranges) }
+  .debug_pubnames  0 :  { *(.debug_pubnames) }
+  .debug_info  0 :  { *(.debug_info) }
+  .debug_abbrev  0 :  { *(.debug_abbrev) }
+  .debug_line  0 :  { *(.debug_line) }
+  .debug_frame  0 :  { *(.debug_frame) }
+  .debug_str  0 :  { *(.debug_str) }
+  .debug_loc  0 :  { *(.debug_loc) }
+  .debug_macinfo  0 :  { *(.debug_macinfo) }
+  .debug_weaknames  0 :  { *(.debug_weaknames) }
+  .debug_funcnames  0 :  { *(.debug_funcnames) }
+  .debug_typenames  0 :  { *(.debug_typenames) }
+  .debug_varnames  0 :  { *(.debug_varnames) }
+  .xt.insn 0 :
+  {
+    KEEP (*(.xt.insn))
+    KEEP (*(.gnu.linkonce.x.*))
+  }
+  .xt.prop 0 :
+  {
+    *(.xt.prop)
+    *(.xt.prop.*)
+    *(.gnu.linkonce.prop.*)
+  }
+  .xt.lit 0 :
+  {
+    *(.xt.lit)
+    *(.xt.lit.*)
+    *(.gnu.linkonce.p.*)
+  }
+  .xtensa.info 0 :
+  {
+    *(.xtensa.info)
+  }
+  .debug.xt.callgraph 0 :
+  {
+    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
+  }
+  .comment 0 :
+  {
+    KEEP(*(.comment))
+  }
+  .note.GNU-stack 0 :
+  {
+    *(.note.GNU-stack)
+  }
+#include <zephyr/linker/common-rom.ld>
+/* Located in generated directory. This file is populated by calling
+ * zephyr_linker_sources(ROM_SECTIONS ...). Useful for grouping iterable RO structs.
+ */
+#include <snippets-rom-sections.ld>
+#include <zephyr/linker/common-ram.ld>
+
+#ifdef CONFIG_GEN_ISR_TABLES
+#include <zephyr/linker/intlist.ld>
+#endif
+
+}
diff --git a/soc/nxp/imxrt/imxrt7xx/hifi4/CMakeLists.txt b/soc/nxp/imxrt/imxrt7xx/hifi4/CMakeLists.txt
new file mode 100644
index 00000000000..1c10b21b9ea
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/hifi4/CMakeLists.txt
@@ -0,0 +1,9 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include)
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")
diff --git a/soc/nxp/imxrt/imxrt7xx/hifi4/include/dsp/cache.h b/soc/nxp/imxrt/imxrt7xx/hifi4/include/dsp/cache.h
new file mode 100644
index 00000000000..d67fca16f87
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/hifi4/include/dsp/cache.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __COMMON_DSP_CACHE_H__
+#define __COMMON_DSP_CACHE_H__
+
+#include <xtensa/hal.h>
+
+#endif
diff --git a/soc/nxp/imxrt/imxrt7xx/hifi4/include/dsp/io.h b/soc/nxp/imxrt/imxrt7xx/hifi4/include/dsp/io.h
new file mode 100644
index 00000000000..7bdd1c5ad27
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/hifi4/include/dsp/io.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INCLUDE_IO__
+#define __INCLUDE_IO__
+
+#include <stdint.h>
+#include <soc/memory.h>
+#include <zephyr/sys/sys_io.h>
+#include <zephyr/arch/common/sys_io.h>
+
+static inline uint32_t io_reg_read(uint32_t reg)
+{
+	return sys_read32(reg);
+}
+
+static inline void io_reg_write(uint32_t reg, uint32_t val)
+{
+	sys_write32(val, reg);
+}
+
+static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, uint32_t value)
+{
+	io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask));
+}
+
+static inline uint16_t io_reg_read16(uint32_t reg)
+{
+	return sys_read16(reg);
+}
+
+static inline void io_reg_write16(uint32_t reg, uint16_t val)
+{
+	sys_write16(val, reg);
+}
+
+#endif
diff --git a/soc/nxp/imxrt/imxrt7xx/hifi4/include/soc.h b/soc/nxp/imxrt/imxrt7xx/hifi4/include/soc.h
new file mode 100644
index 00000000000..f4b7380d84e
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/hifi4/include/soc.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include <errno.h>
+
+#include <zephyr/sys/sys_io.h>
+#include <dsp/cache.h>
+
+#ifndef __INC_IMXRT_SOC_H
+#define __INC_IMXRT_SOC_H
+
+/* Macros related to interrupt handling */
+#define XTENSA_IRQ_NUM_SHIFT 0
+#define XTENSA_IRQ_NUM_MASK  0xff
+
+/*
+ * IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00.
+ *
+ * 1. Peripheral Register bit offset.
+ */
+#define XTENSA_IRQ_NUMBER(_irq) ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
+
+extern void z_soc_irq_enable(uint32_t irq);
+extern void z_soc_irq_disable(uint32_t irq);
+extern int z_soc_irq_is_enabled(unsigned int irq);
+
+#endif /* __INC_IMXRT_SOC_H */
diff --git a/soc/nxp/imxrt/imxrt7xx/hifi4/include/soc/memory.h b/soc/nxp/imxrt/imxrt7xx/hifi4/include/soc/memory.h
new file mode 100644
index 00000000000..b74e695c66d
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/hifi4/include/soc/memory.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __XTENSA_MEMORY_H__
+#define __XTENSA_MEMORY_H__
+
+#include <zephyr/autoconf.h>
+
+#define IRAM_RESERVE_HEADER_SPACE 0x400
+
+#define IRAM_BASE 0x24020000
+#define IRAM_SIZE 0x10000
+
+#define DRAM_BASE 0x24000000
+#define DRAM_SIZE 0x10000
+
+#define SDRAM0_BASE 0x20200000
+#define SDRAM0_SIZE 0xFFFFF
+
+/* The reset vector address in IRAM and its size. */
+#define XCHAL_RESET_VECTOR0_PADDR_IRAM IRAM_BASE
+#define MEM_RESET_TEXT_SIZE            (0x2E0)
+#define MEM_RESET_LIT_SIZE             (0x120)
+
+/* Base address of all interrupt vectors in IRAM. */
+#define XCHAL_VECBASE_RESET_PADDR_IRAM (IRAM_BASE + IRAM_RESERVE_HEADER_SPACE)
+#define MEM_VECBASE_LIT_SIZE           (0x178)
+/* Vector and literal sizes. */
+#define MEM_VECT_LIT_SIZE  (0x4)
+#define MEM_VECT_TEXT_SIZE (0x1C)
+
+/* Addresses of the interrupt vectors. */
+#define XCHAL_INT_VECTOR_ADDR(x)          (XCHAL_VECBASE_RESET_PADDR_IRAM + (x))
+#define XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x17C))
+#define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x19C))
+#define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x1BC))
+#define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x1DC))
+#define XCHAL_KERNEL_VECTOR_PADDR_IRAM    (XCHAL_INT_VECTOR_ADDR(0x1FC))
+#define XCHAL_USER_VECTOR_PADDR_IRAM      (XCHAL_INT_VECTOR_ADDR(0x21C))
+#define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x23C))
+
+/* Location for the intList section which is later used to construct the
+ * Interrupt Descriptor Table (IDT). This is a bogus address as this
+ * section will be stripped off in the final image.
+ */
+#define IDT_BASE (IRAM_BASE + IRAM_SIZE)
+
+/* Size of the Interrupt Descriptor Table (IDT). */
+#define IDT_SIZE (0x2000)
+
+#endif
diff --git a/soc/nxp/imxrt/imxrt7xx/hifi4/linker.ld b/soc/nxp/imxrt/imxrt7xx/hifi4/linker.ld
new file mode 100644
index 00000000000..5ec321fcdcf
--- /dev/null
+++ b/soc/nxp/imxrt/imxrt7xx/hifi4/linker.ld
@@ -0,0 +1,492 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+OUTPUT_ARCH(xtensa)
+
+#include <soc/memory.h>
+#include <xtensa/config/core-isa.h>
+
+#include <zephyr/linker/linker-defs.h>
+#include <zephyr/linker/linker-tool.h>
+#include <zephyr/linker/sections.h>
+
+#define RAMABLE_REGION sdram0 :sdram0_phdr
+#define ROMABLE_REGION sdram0 :sdram0_phdr
+
+MEMORY
+{
+  vector_reset_text :
+    org = XCHAL_RESET_VECTOR0_PADDR_IRAM,
+    len = MEM_RESET_TEXT_SIZE
+  vector_reset_lit :
+    org = XCHAL_RESET_VECTOR0_PADDR_IRAM + MEM_RESET_TEXT_SIZE,
+    len = MEM_RESET_LIT_SIZE
+  vector_base_text :
+    org = XCHAL_VECBASE_RESET_PADDR_IRAM,
+    len = MEM_VECBASE_LIT_SIZE
+  vector_int2_lit :
+    org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
+    len = MEM_VECT_LIT_SIZE
+  vector_int2_text :
+    org = XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM,
+    len = MEM_VECT_TEXT_SIZE
+  vector_int3_lit :
+    org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
+    len = MEM_VECT_LIT_SIZE
+  vector_int3_text :
+    org = XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM,
+    len = MEM_VECT_TEXT_SIZE
+  vector_int4_lit :
+    org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
+    len = MEM_VECT_LIT_SIZE
+  vector_int4_text :
+    org = XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM,
+    len = MEM_VECT_TEXT_SIZE
+  vector_int5_lit :
+    org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
+    len = MEM_VECT_LIT_SIZE
+  vector_int5_text :
+    org = XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM,
+    len = MEM_VECT_TEXT_SIZE
+  vector_kernel_lit :
+    org = XCHAL_KERNEL_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
+    len = MEM_VECT_LIT_SIZE
+  vector_kernel_text :
+    org = XCHAL_KERNEL_VECTOR_PADDR_IRAM,
+    len = MEM_VECT_TEXT_SIZE
+  vector_user_lit :
+    org = XCHAL_USER_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
+    len = MEM_VECT_LIT_SIZE
+  vector_user_text :
+    org = XCHAL_USER_VECTOR_PADDR_IRAM,
+    len = MEM_VECT_TEXT_SIZE
+  vector_double_lit :
+    org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM - MEM_VECT_LIT_SIZE,
+    len = MEM_VECT_LIT_SIZE
+  vector_double_text :
+    org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM,
+    len = MEM_VECT_TEXT_SIZE
+  iram_text_start :
+    org = XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM + MEM_VECT_TEXT_SIZE,
+    len = (IRAM_BASE + IRAM_SIZE) - (XCHAL_DOUBLEEXC_VECTOR_PADDR + MEM_VECT_TEXT_SIZE)
+  sdram0 :
+    org = SDRAM0_BASE,
+    len = SDRAM0_SIZE
+#ifdef CONFIG_GEN_ISR_TABLES
+  IDT_LIST :
+    org = IDT_BASE,
+    len = IDT_SIZE
+#endif
+}
+
+PHDRS
+{
+  vector_reset_text_phdr PT_LOAD;
+  vector_reset_lit_phdr PT_LOAD;
+  vector_base_text_phdr PT_LOAD;
+  vector_base_lit_phdr PT_LOAD;
+  vector_int2_text_phdr PT_LOAD;
+  vector_int2_lit_phdr PT_LOAD;
+  vector_int3_text_phdr PT_LOAD;
+  vector_int3_lit_phdr PT_LOAD;
+  vector_int4_text_phdr PT_LOAD;
+  vector_int4_lit_phdr PT_LOAD;
+  vector_int5_text_phdr PT_LOAD;
+  vector_int5_lit_phdr PT_LOAD;
+  vector_kernel_text_phdr PT_LOAD;
+  vector_kernel_lit_phdr PT_LOAD;
+  vector_user_text_phdr PT_LOAD;
+  vector_user_lit_phdr PT_LOAD;
+  vector_double_text_phdr PT_LOAD;
+  vector_double_lit_phdr PT_LOAD;
+  iram_text_start_phdr PT_LOAD;
+  sdram0_phdr PT_LOAD;
+}
+
+/*  Default entry point:  */
+ENTRY(CONFIG_KERNEL_ENTRY)
+
+_rom_store_table = 0;
+
+PROVIDE(_memmap_reset_vector = XCHAL_RESET_VECTOR0_PADDR_IRAM);
+PROVIDE(_memmap_vecbase_reset = XCHAL_VECBASE_RESET_PADDR_IRAM);
+
+/* Various memory-map dependent cache attribute settings: */
+_memmap_cacheattr_wb_base = 0x00000040;
+_memmap_cacheattr_wt_base = 0x00000010;
+_memmap_cacheattr_bp_base = 0x00000020;
+_memmap_cacheattr_unused_mask = 0xFFFFFF0F;
+_memmap_cacheattr_wb_trapnull = 0x22222244;
+_memmap_cacheattr_wba_trapnull = 0x2222224F;
+_memmap_cacheattr_wbna_trapnull = 0x2222225F;
+_memmap_cacheattr_wt_trapnull = 0x2222221F;
+_memmap_cacheattr_bp_trapnull = 0x2222222F;
+_memmap_cacheattr_wb_strict = 0xFFFFFF4F;
+_memmap_cacheattr_wt_strict = 0xFFFFFF1F;
+_memmap_cacheattr_bp_strict = 0xFFFFFF2F;
+_memmap_cacheattr_wb_allvalid = 0x22222242;
+_memmap_cacheattr_wt_allvalid = 0x22222212;
+_memmap_cacheattr_bp_allvalid = 0x22222222;
+_memmap_region_map = 0x00000002;
+PROVIDE(_memmap_cacheattr_reset = _memmap_cacheattr_wb_trapnull);
+
+SECTIONS
+{
+
+#include <zephyr/linker/rel-sections.ld>
+
+  .ResetVector.text : ALIGN(4)
+  {
+    _ResetVector_text_start = ABSOLUTE(.);
+    KEEP (*(.ResetVector.text))
+    _ResetVector_text_end = ABSOLUTE(.);
+  } >vector_reset_text :vector_reset_text_phdr
+
+  .ResetVector.literal : ALIGN(4)
+  {
+    _ResetVector_literal_start = ABSOLUTE(.);
+    *(.ResetVector.literal)
+    _ResetVector_literal_end = ABSOLUTE(.);
+  } >vector_reset_lit :vector_reset_lit_phdr
+
+  .WindowVectors.text : ALIGN(4)
+  {
+    _WindowVectors_text_start = ABSOLUTE(.);
+    KEEP (*(.WindowVectors.text))
+    _WindowVectors_text_end = ABSOLUTE(.);
+  } >vector_base_text :vector_base_text_phdr
+
+  .Level2InterruptVector.literal : ALIGN(4)
+  {
+    _Level2InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level2InterruptVector.literal)
+    _Level2InterruptVector_literal_end = ABSOLUTE(.);
+  } >vector_int2_lit :vector_int2_lit_phdr
+
+  .Level2InterruptVector.text : ALIGN(4)
+  {
+    _Level2InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level2InterruptVector.text))
+    _Level2InterruptVector_text_end = ABSOLUTE(.);
+  } >vector_int2_text :vector_int2_text_phdr
+
+  .Level3InterruptVector.literal : ALIGN(4)
+  {
+    _Level3InterruptVector_literal_start = ABSOLUTE(.);
+    *(.Level3InterruptVector.literal)
+    _Level3InterruptVector_literal_end = ABSOLUTE(.);
+  } >vector_int3_lit :vector_int3_lit_phdr
+
+  .Level3InterruptVector.text : ALIGN(4)
+  {
+    _Level3InterruptVector_text_start = ABSOLUTE(.);
+    KEEP (*(.Level3InterruptVector.text))
+    _Level3InterruptVector_text_end = ABSOLUTE(.);
+  } >vector_int3_text :vector_int3_text_phdr
+
+  .DebugExceptionVector.literal : ALIGN(4)
+  {
+    _DebugExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DebugExceptionVector.literal)
+    _DebugExceptionVector_literal_end = ABSOLUTE(.);
+  } >vector_int4_lit :vector_int4_lit_phdr
+
+  .DebugExceptionVector.text : ALIGN(4)
+  {
+    _DebugExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DebugExceptionVector.text))
+    _DebugExceptionVector_text_end = ABSOLUTE(.);
+  } >vector_int4_text :vector_int4_text_phdr
+
+  .NMIExceptionVector.literal : ALIGN(4)
+  {
+    _NMIExceptionVector_literal_start = ABSOLUTE(.);
+    *(.NMIExceptionVector.literal)
+    _NMIExceptionVector_literal_end = ABSOLUTE(.);
+  } >vector_int5_lit :vector_int5_lit_phdr
+
+  .NMIExceptionVector.text : ALIGN(4)
+  {
+    _NMIExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.NMIExceptionVector.text))
+    _NMIExceptionVector_text_end = ABSOLUTE(.);
+  } >vector_int5_text :vector_int5_text_phdr
+
+  .KernelExceptionVector.literal : ALIGN(4)
+  {
+    _KernelExceptionVector_literal_start = ABSOLUTE(.);
+    *(.KernelExceptionVector.literal)
+    _KernelExceptionVector_literal_end = ABSOLUTE(.);
+  } >vector_kernel_lit :vector_kernel_lit_phdr
+
+  .KernelExceptionVector.text : ALIGN(4)
+  {
+    _KernelExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.KernelExceptionVector.text))
+    _KernelExceptionVector_text_end = ABSOLUTE(.);
+  } >vector_kernel_text :vector_kernel_text_phdr
+
+  .UserExceptionVector.literal : ALIGN(4)
+  {
+    _UserExceptionVector_literal_start = ABSOLUTE(.);
+    *(.UserExceptionVector.literal)
+    _UserExceptionVector_literal_end = ABSOLUTE(.);
+  } >vector_user_lit :vector_user_lit_phdr
+
+  .UserExceptionVector.text : ALIGN(4)
+  {
+    _UserExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.UserExceptionVector.text))
+    _UserExceptionVector_text_end = ABSOLUTE(.);
+  } >vector_user_text :vector_user_text_phdr
+
+  .DoubleExceptionVector.literal : ALIGN(4)
+  {
+    _DoubleExceptionVector_literal_start = ABSOLUTE(.);
+    *(.DoubleExceptionVector.literal)
+    _DoubleExceptionVector_literal_end = ABSOLUTE(.);
+  } >vector_double_lit :vector_double_lit_phdr
+
+  .DoubleExceptionVector.text : ALIGN(4)
+  {
+    _DoubleExceptionVector_text_start = ABSOLUTE(.);
+    KEEP (*(.DoubleExceptionVector.text))
+    _DoubleExceptionVector_text_end = ABSOLUTE(.);
+  } >vector_double_text :vector_double_text_phdr
+
+  .iram.text : ALIGN(4)
+   {
+    _iram_text_start = ABSOLUTE(.);
+    *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text)
+    _iram_text_end = ABSOLUTE(.);
+   } >iram_text_start :iram_text_start_phdr
+
+  .text : ALIGN(4)
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    KEEP (*(.ResetVector.text))
+    *(.ResetVector.literal)
+    *(.entry.text)
+    *(.init.literal)
+    KEEP(*(.init))
+    *(.literal.sort.* SORT(.text.sort.*))
+    KEEP (*(.literal.keepsort.* SORT(.text.keepsort.*) .literal.keep.* .text.keep.* .literal.*personality* .text.*personality*))
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.fini.literal)
+    KEEP(*(.fini))
+    *(.gnu.version)
+    . = ALIGN (4);
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } >iram_text_start :iram_text_start_phdr
+
+  _memmap_mem_iram0_max = ABSOLUTE(.);
+
+  .rodata : ALIGN(4)
+  {
+    __rodata_region_start = ABSOLUTE(.);
+    *(.rodata)
+    *(SORT(.rodata.sort.*))
+    KEEP (*(SORT(.rodata.keepsort.*) .rodata.keep.*))
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    __XT_EXCEPTION_TABLE__ = ABSOLUTE(.);
+    KEEP (*(.xt_except_table))
+    KEEP (*(.gcc_except_table))
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    PROVIDE (__eh_frame_start = .);
+    KEEP (*(.eh_frame))
+    PROVIDE (__eh_frame_end = .);
+    /*  C++ constructor and destructor tables, properly ordered:  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS__ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    . = ALIGN(4);		/* this table MUST be 4-byte aligned */
+    _bss_table_start = ABSOLUTE(.);
+    LONG(_bss_start)
+    LONG(_bss_end)
+    _bss_table_end = ABSOLUTE(.);
+    . = ALIGN (4);
+    __rodata_region_end = ABSOLUTE(.);
+  } >sdram0 :sdram0_phdr
+
+  .module_init : ALIGN(4)
+  {
+   _module_init_start = ABSOLUTE(.);
+    *(*.initcall)
+    _module_init_end = ABSOLUTE(.);
+  } >sdram0 :sdram0_phdr
+
+  .noinit : ALIGN(4)
+  {
+    *(.noinit)
+    *(.noinit.*)
+  } >sdram0 :sdram0_phdr
+
+  .data : ALIGN(4)
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data)
+    *(SORT(.data.sort.*))
+    KEEP (*(SORT(.data.keepsort.*) .data.keep.*))
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    KEEP(*(.gnu.linkonce.d.*personality*))
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.sdata2)
+    *(.sdata2.*)
+    *(.gnu.linkonce.s2.*)
+    KEEP(*(.jcr))
+    *(__llvm_prf_cnts)
+    *(__llvm_prf_data)
+    *(__llvm_prf_vnds)
+    . = ALIGN (4);
+    _data_end = ABSOLUTE(.);
+  } >sdram0 :sdram0_phdr
+
+  __llvm_prf_names : ALIGN(4)
+  {
+    __llvm_prf_names_start = ABSOLUTE(.);
+    *(__llvm_prf_names)
+    . = ALIGN (4);
+    __llvm_prf_names_end = ABSOLUTE(.);
+  } >sdram0 :sdram0_phdr
+
+  .note.gnu.build-id : ALIGN(4)
+  {
+    _note_gnu_build-id_start = ABSOLUTE(.);
+    *(.note.gnu.build-id)
+    . = ALIGN (4);
+    _note_gnu_build-id_end = ABSOLUTE(.);
+  } >sdram0 :sdram0_phdr
+
+  .bss (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(SORT(.bss.sort.*))
+    KEEP (*(SORT(.bss.keepsort.*) .bss.keep.*))
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    *(.clib.bss)
+    *(.clib.percpu.bss)
+    *(.rtos.percpu.bss)
+    *(.rtos.bss)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+    _end = ALIGN(0x8);
+    PROVIDE(end = ALIGN(0x8));
+    _stack_sentry = ALIGN(0x8);
+    _memmap_seg_dsp_core_end = ALIGN(0x8);
+  } >sdram0 :sdram0_phdr
+
+  .heap_mem (NOLOAD) : ALIGN(8)
+  {
+    . = ALIGN (8);
+    _heap_mem_start = ABSOLUTE(.);
+    *(*.heap_mem)
+    _heap_mem_end = ABSOLUTE(.);
+  } >sdram0 :sdram0_phdr
+
+  /* stack */
+  _end = ALIGN (8);
+
+  _heap_sentry = SDRAM0_BASE + SDRAM0_SIZE - 0x1000;
+  __stack = SDRAM0_BASE + SDRAM0_SIZE - 0x1000;
+  .comment  0 :  { *(.comment) }
+  .debug  0 :  { *(.debug) }
+  .line  0 :  { *(.line) }
+  .debug_srcinfo  0 :  { *(.debug_srcinfo) }
+  .debug_sfnames  0 :  { *(.debug_sfnames) }
+  .debug_aranges  0 :  { *(.debug_aranges) }
+  .debug_ranges   0 :  { *(.debug_ranges) }
+  .debug_pubnames  0 :  { *(.debug_pubnames) }
+  .debug_info  0 :  { *(.debug_info) }
+  .debug_abbrev  0 :  { *(.debug_abbrev) }
+  .debug_line  0 :  { *(.debug_line) }
+  .debug_frame  0 :  { *(.debug_frame) }
+  .debug_str  0 :  { *(.debug_str) }
+  .debug_loc  0 :  { *(.debug_loc) }
+  .debug_macinfo  0 :  { *(.debug_macinfo) }
+  .debug_weaknames  0 :  { *(.debug_weaknames) }
+  .debug_funcnames  0 :  { *(.debug_funcnames) }
+  .debug_typenames  0 :  { *(.debug_typenames) }
+  .debug_varnames  0 :  { *(.debug_varnames) }
+  .xt.insn 0 :
+  {
+    KEEP (*(.xt.insn))
+    KEEP (*(.gnu.linkonce.x.*))
+  }
+  .xt.prop 0 :
+  {
+    *(.xt.prop)
+    *(.xt.prop.*)
+    *(.gnu.linkonce.prop.*)
+  }
+  .xt.lit 0 :
+  {
+    *(.xt.lit)
+    *(.xt.lit.*)
+    *(.gnu.linkonce.p.*)
+  }
+  .xtensa.info 0 :
+  {
+    *(.xtensa.info)
+  }
+  .debug.xt.callgraph 0 :
+  {
+    KEEP (*(.debug.xt.callgraph .debug.xt.callgraph.* .gnu.linkonce.xt.callgraph.*))
+  }
+  .comment 0 :
+  {
+    KEEP(*(.comment))
+  }
+  .note.GNU-stack 0 :
+  {
+    *(.note.GNU-stack)
+  }
+#include <zephyr/linker/common-rom.ld>
+/* Located in generated directory. This file is populated by calling
+ * zephyr_linker_sources(ROM_SECTIONS ...). Useful for grouping iterable RO structs.
+ */
+#include <snippets-rom-sections.ld>
+#include <zephyr/linker/common-ram.ld>
+
+#ifdef CONFIG_GEN_ISR_TABLES
+#include <zephyr/linker/intlist.ld>
+#endif
+
+}
diff --git a/soc/nxp/imxrt/soc.yml b/soc/nxp/imxrt/soc.yml
index 2fd2a0df226..f01629f3f8f 100644
--- a/soc/nxp/imxrt/soc.yml
+++ b/soc/nxp/imxrt/soc.yml
@@ -38,6 +38,14 @@ family:
     - name: mimxrt685s
       cpuclusters:
       - name: cm33
+  - name: imxrt7xx
+    socs:
+    - name: mimxrt798s
+      cpuclusters:
+      - name: cm33_cpu0
+      - name: cm33_cpu1
+      - name: hifi4
+      - name: hifi1
 runners:
   run_once:
     '--erase':
@@ -53,6 +61,9 @@ runners:
       - qualifiers:
         - mimxrt1176/cm7
         - mimxrt1176/cm4
+      - qualifiers:
+        - mimxrt1189/cm33
+        - mimxrt1189/cm7
       - qualifiers:
         - mimxrt595s/cm33
         - mimxrt595s/f1
@@ -71,6 +82,9 @@ runners:
       - qualifiers:
         - mimxrt1176/cm7
         - mimxrt1176/cm4
+      - qualifiers:
+        - mimxrt1189/cm33
+        - mimxrt1189/cm7
       - qualifiers:
         - mimxrt595s/cm33
         - mimxrt595s/f1
diff --git a/soc/nxp/kinetis/k2x/soc.c b/soc/nxp/kinetis/k2x/soc.c
index e89526f5556..069e5a86241 100644
--- a/soc/nxp/kinetis/k2x/soc.c
+++ b/soc/nxp/kinetis/k2x/soc.c
@@ -84,7 +84,7 @@ static const sim_clock_config_t simConfig = {
  * clock.
  *
  */
-static ALWAYS_INLINE void clock_init(void)
+__weak void clock_init(void)
 {
 	CLOCK_SetSimSafeDivs();
 
diff --git a/soc/nxp/kinetis/k6x/soc.c b/soc/nxp/kinetis/k6x/soc.c
index 32832dc8a0a..f46d02163cb 100644
--- a/soc/nxp/kinetis/k6x/soc.c
+++ b/soc/nxp/kinetis/k6x/soc.c
@@ -87,7 +87,7 @@ static const sim_clock_config_t simConfig = {
  * clock.
  *
  */
-static ALWAYS_INLINE void clock_init(void)
+__weak void clock_init(void)
 {
 	CLOCK_SetSimSafeDivs();
 
@@ -105,10 +105,10 @@ static ALWAYS_INLINE void clock_init(void)
 	CLOCK_SetLpuartClock(LPUART0SRC_OSCERCLK);
 #endif
 
-#if CONFIG_ETH_MCUX || CONFIG_ETH_NXP_ENET
+#if CONFIG_ETH_NXP_ENET
 	CLOCK_SetEnetTime0Clock(TIMESRC_OSCERCLK);
 #endif
-#if CONFIG_ETH_MCUX_RMII_EXT_CLK
+#if CONFIG_ETH_NXP_ENET_RMII_EXT_CLK
 	CLOCK_SetRmii0Clock(1);
 #endif
 #if CONFIG_USB_KINETIS || CONFIG_UDC_KINETIS
diff --git a/soc/nxp/kinetis/k8x/soc.c b/soc/nxp/kinetis/k8x/soc.c
index d338ad72a96..df5061cbcb8 100644
--- a/soc/nxp/kinetis/k8x/soc.c
+++ b/soc/nxp/kinetis/k8x/soc.c
@@ -69,7 +69,7 @@ static const sim_clock_config_t sim_config = {
 	.pllFllFrac = (0),
 };
 
-static ALWAYS_INLINE void clk_init(void)
+__weak void clk_init(void)
 {
 	CLOCK_SetSimSafeDivs();
 
diff --git a/soc/nxp/kinetis/ke1xf/soc.c b/soc/nxp/kinetis/ke1xf/soc.c
index 35968f6acf0..899d28984ad 100644
--- a/soc/nxp/kinetis/ke1xf/soc.c
+++ b/soc/nxp/kinetis/ke1xf/soc.c
@@ -145,7 +145,7 @@ static const scg_spll_config_t scg_spll_config = {
 	.mult        = (SCG_CLOCK_MULT(pll) - 16U)
 };
 
-static ALWAYS_INLINE void clk_init(void)
+__weak void clk_init(void)
 {
 	const scg_sys_clk_config_t scg_sys_clk_config_safe = {
 		.divSlow = kSCG_SysClkDivBy4,
diff --git a/soc/nxp/kinetis/ke1xz/soc.c b/soc/nxp/kinetis/ke1xz/soc.c
index 0f8ad0de6ac..d3b8e156dd4 100644
--- a/soc/nxp/kinetis/ke1xz/soc.c
+++ b/soc/nxp/kinetis/ke1xz/soc.c
@@ -81,7 +81,7 @@ static const scg_firc_config_t scg_firc_config = {
 	.trimConfig = NULL
 };
 
-static ALWAYS_INLINE void clk_init(void)
+__weak void clk_init(void)
 {
 	const scg_sys_clk_config_t scg_sys_clk_config_safe = {
 		.divSlow = kSCG_SysClkDivBy4,
diff --git a/soc/nxp/kinetis/kl2x/soc.c b/soc/nxp/kinetis/kl2x/soc.c
index 8ab125d4c7c..359b32bd6cb 100644
--- a/soc/nxp/kinetis/kl2x/soc.c
+++ b/soc/nxp/kinetis/kl2x/soc.c
@@ -24,7 +24,7 @@
  * Variables
  ******************************************************************************/
 
-static ALWAYS_INLINE void clock_init(void)
+__weak void clock_init(void)
 {
    /*
     * Core clock: 48MHz
diff --git a/soc/nxp/kinetis/kv5x/soc.c b/soc/nxp/kinetis/kv5x/soc.c
index cd5d4048c42..f4d7958c2c9 100644
--- a/soc/nxp/kinetis/kv5x/soc.c
+++ b/soc/nxp/kinetis/kv5x/soc.c
@@ -63,7 +63,7 @@ static const sim_clock_config_t sim_config = {
 		   SIM_CLKDIV1_OUTDIV4(CLOCK_DIVIDER(flash_clk)),
 };
 
-static ALWAYS_INLINE void clk_init(void)
+__weak void clk_init(void)
 {
 	CLOCK_SetSimSafeDivs();
 
diff --git a/soc/nxp/kinetis/kwx/soc_kw2xd.c b/soc/nxp/kinetis/kwx/soc_kw2xd.c
index c2fcddfa6ed..a94217fa0cb 100644
--- a/soc/nxp/kinetis/kwx/soc_kw2xd.c
+++ b/soc/nxp/kinetis/kwx/soc_kw2xd.c
@@ -117,7 +117,7 @@ static void set_modem_clock(void)
  * clock.
  *
  */
-static ALWAYS_INLINE void clock_init(void)
+__weak void clock_init(void)
 {
 	CLOCK_SetSimSafeDivs();
 
diff --git a/soc/nxp/kinetis/kwx/soc_kw4xz.c b/soc/nxp/kinetis/kwx/soc_kw4xz.c
index f6baedb07b7..c730dac498e 100644
--- a/soc/nxp/kinetis/kwx/soc_kw4xz.c
+++ b/soc/nxp/kinetis/kwx/soc_kw4xz.c
@@ -52,7 +52,7 @@ static void CLOCK_SYS_FllStableDelay(void)
 	}
 }
 
-static ALWAYS_INLINE void clock_init(void)
+__weak void clock_init(void)
 {
 	CLOCK_SetSimSafeDivs();
 
diff --git a/soc/nxp/lpc/lpc54xxx/soc.c b/soc/nxp/lpc/lpc54xxx/soc.c
index a18e6e300c7..14f6cd31d0b 100644
--- a/soc/nxp/lpc/lpc54xxx/soc.c
+++ b/soc/nxp/lpc/lpc54xxx/soc.c
@@ -46,7 +46,7 @@
  */
 #define CPU_FREQ DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
 
-static ALWAYS_INLINE void clock_init(void)
+__weak void clock_init(void)
 {
 
 #ifdef CONFIG_SOC_LPC54114_M4
diff --git a/soc/nxp/lpc/lpc55xxx/soc.c b/soc/nxp/lpc/lpc55xxx/soc.c
index 7b7332d0b61..2d353583336 100644
--- a/soc/nxp/lpc/lpc55xxx/soc.c
+++ b/soc/nxp/lpc/lpc55xxx/soc.c
@@ -78,7 +78,7 @@ const pll_setup_t pll1Setup = {
  *
  */
 
-static ALWAYS_INLINE void clock_init(void)
+__weak void clock_init(void)
 {
 	ExternalClockFrequency = 0;
 
@@ -245,7 +245,7 @@ static ALWAYS_INLINE void clock_init(void)
 	/* enable usb0 host clock */
 	CLOCK_EnableClock(kCLOCK_Usbhsl0);
 	/*
-	 * According to reference mannual, device mode setting has to be set by access
+	 * According to reference manual, device mode setting has to be set by access
 	 * usb host register
 	 */
 	USBFSH->PORTMODE |= USBFSH_PORTMODE_DEV_ENABLE_MASK;
diff --git a/soc/nxp/mcx/mcxa/Kconfig b/soc/nxp/mcx/mcxa/Kconfig
index 6037d43b55d..194bb57915c 100644
--- a/soc/nxp/mcx/mcxa/Kconfig
+++ b/soc/nxp/mcx/mcxa/Kconfig
@@ -1,4 +1,4 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_MCXA
@@ -10,8 +10,26 @@ config SOC_SERIES_MCXA
 	select CPU_CORTEX_M_HAS_DWT
 	select SOC_RESET_HOOK
 
+config SOC_MCXA153
+	select CPU_CORTEX_M33
+	select HAS_MCUX_CACHE
+
 config SOC_MCXA156
 	select CPU_CORTEX_M33
 	select CPU_HAS_FPU
 	select ARMV8_M_DSP
 	select HAS_MCUX_CACHE
+
+config SOC_MCXA166
+	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
+	select HAS_MCUX_CACHE
+
+config SOC_MCXA276
+	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
+	select HAS_MCUX_CACHE
diff --git a/soc/nxp/mcx/mcxa/Kconfig.defconfig b/soc/nxp/mcx/mcxa/Kconfig.defconfig
index 11195acc0d7..3ee3181cd81 100644
--- a/soc/nxp/mcx/mcxa/Kconfig.defconfig
+++ b/soc/nxp/mcx/mcxa/Kconfig.defconfig
@@ -3,6 +3,9 @@
 
 if SOC_SERIES_MCXA
 
+config CORTEX_M_SYSTICK
+	default n if MCUX_LPTMR_TIMER
+
 config NUM_IRQS
 	default 88
 
diff --git a/soc/nxp/mcx/mcxa/Kconfig.soc b/soc/nxp/mcx/mcxa/Kconfig.soc
index 7f59251affe..2aba6a95a05 100644
--- a/soc/nxp/mcx/mcxa/Kconfig.soc
+++ b/soc/nxp/mcx/mcxa/Kconfig.soc
@@ -1,4 +1,4 @@
-# Copyright 2024 NXP
+# Copyright 2024-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_MCXA
@@ -8,12 +8,39 @@ config SOC_SERIES_MCXA
 config SOC_SERIES
 	default "mcxa" if SOC_SERIES_MCXA
 
+config SOC_MCXA153
+	bool
+	select SOC_SERIES_MCXA
+
 config SOC_MCXA156
 	bool
 	select SOC_SERIES_MCXA
 
+config SOC_MCXA166
+	bool
+	select SOC_SERIES_MCXA
+
+config SOC_MCXA276
+	bool
+	select SOC_SERIES_MCXA
+
 config SOC
+	default "mcxa153" if SOC_MCXA153
 	default "mcxa156" if SOC_MCXA156
+	default "mcxa166" if SOC_MCXA166
+	default "mcxa276" if SOC_MCXA276
+
+config SOC_PART_NUMBER_MCXA153VFM
+	bool
+
+config SOC_PART_NUMBER_MCXA153VFT
+	bool
+
+config SOC_PART_NUMBER_MCXA153VLF
+	bool
+
+config SOC_PART_NUMBER_MCXA153VLH
+	bool
 
 config SOC_PART_NUMBER_MCXA156VPJ
 	bool
@@ -24,7 +51,43 @@ config SOC_PART_NUMBER_MCXA156VLL
 config SOC_PART_NUMBER_MCXA156VMP
 	bool
 
+config SOC_PART_NUMBER_MCXA166VLQ
+	bool
+
+config SOC_PART_NUMBER_MCXA166VLL
+	bool
+
+config SOC_PART_NUMBER_MCXA166VLH
+	bool
+
+config SOC_PART_NUMBER_MCXA166VPN
+	bool
+
+config SOC_PART_NUMBER_MCXA276VLQ
+	bool
+
+config SOC_PART_NUMBER_MCXA276VLL
+	bool
+
+config SOC_PART_NUMBER_MCXA276VLH
+	bool
+
+config SOC_PART_NUMBER_MCXA276VPN
+	bool
+
 config SOC_PART_NUMBER
+	default "MCXA153VFM" if SOC_PART_NUMBER_MCXA153VFM
+	default "MCXA153VFT" if SOC_PART_NUMBER_MCXA153VFT
+	default "MCXA153VLF" if SOC_PART_NUMBER_MCXA153VLF
+	default "MCXA153VLH" if SOC_PART_NUMBER_MCXA153VLH
 	default "MCXA156VPJ" if SOC_PART_NUMBER_MCXA156VPJ
 	default "MCXA156VLL" if SOC_PART_NUMBER_MCXA156VLL
 	default "MCXA156VMP" if SOC_PART_NUMBER_MCXA156VMP
+	default "MCXA166VLQ" if SOC_PART_NUMBER_MCXA166VLQ
+	default "MCXA166VLL" if SOC_PART_NUMBER_MCXA166VLL
+	default "MCXA166VLH" if SOC_PART_NUMBER_MCXA166VLH
+	default "MCXA166VPN" if SOC_PART_NUMBER_MCXA166VPN
+	default "MCXA276VLQ" if SOC_PART_NUMBER_MCXA276VLQ
+	default "MCXA276VLL" if SOC_PART_NUMBER_MCXA276VLL
+	default "MCXA276VLH" if SOC_PART_NUMBER_MCXA276VLH
+	default "MCXA276VPN" if SOC_PART_NUMBER_MCXA276VPN
diff --git a/soc/nxp/mcx/mcxc/Kconfig.defconfig b/soc/nxp/mcx/mcxc/Kconfig.defconfig
index 717158585bc..c1b1f44eb63 100644
--- a/soc/nxp/mcx/mcxc/Kconfig.defconfig
+++ b/soc/nxp/mcx/mcxc/Kconfig.defconfig
@@ -3,6 +3,9 @@
 
 if SOC_SERIES_MCXC
 
+config CORTEX_M_SYSTICK
+	default n if MCUX_LPTMR_TIMER
+
 config NUM_IRQS
 	default 32
 
diff --git a/soc/nxp/mcx/mcxc/Kconfig.soc b/soc/nxp/mcx/mcxc/Kconfig.soc
index 67948a6d958..7a60b591296 100644
--- a/soc/nxp/mcx/mcxc/Kconfig.soc
+++ b/soc/nxp/mcx/mcxc/Kconfig.soc
@@ -52,9 +52,9 @@ config SOC_PART_NUMBER_MCXC444VMP
 	bool
 
 config SOC_PART_NUMBER
-	default "MCXC141VFM" if SOC_PART_NUMBER_MCXC141VLH
+	default "MCXC141VLH" if SOC_PART_NUMBER_MCXC141VLH
 	default "MCXC141VFM" if SOC_PART_NUMBER_MCXC141VFM
-	default "MCXC141VFM" if SOC_PART_NUMBER_MCXC142VFM
+	default "MCXC142VFM" if SOC_PART_NUMBER_MCXC142VFM
 	default "MCXC242VLH" if SOC_PART_NUMBER_MCXC242VLH
 	default "MCXC242VFM" if SOC_PART_NUMBER_MCXC242VFM
 	default "MCXC444VLH" if SOC_PART_NUMBER_MCXC444VLH
diff --git a/soc/nxp/mcx/mcxc/soc.c b/soc/nxp/mcx/mcxc/soc.c
index 4b9c58a8878..0f254bb0068 100644
--- a/soc/nxp/mcx/mcxc/soc.c
+++ b/soc/nxp/mcx/mcxc/soc.c
@@ -83,7 +83,7 @@ const osc_config_t oscConfig_BOARD_BootClockRUN = {
 	}
 };
 
-static void clock_init(void)
+__weak void clock_init(void)
 {
 	/* Set the system clock dividers in SIM to safe value. */
 	CLOCK_SetSimSafeDivs();
@@ -96,10 +96,14 @@ static void clock_init(void)
 	CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
 	/* Set SystemCoreClock variable. */
 	SystemCoreClock = DT_PROP(DT_NODELABEL(cpu0), clock_frequency);
-	/* Set LPUART0 clock source. */
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart0))
+	/* Set LPUART0 clock source. */
 	CLOCK_SetLpuart0Clock(LPUART_CLOCK_SEL(lpuart0));
 #endif
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lpuart1))
+	/* Set LPUART1 clock source. */
+	CLOCK_SetLpuart1Clock(LPUART_CLOCK_SEL(lpuart1));
+#endif
 #if DT_HAS_COMPAT_STATUS_OKAY(nxp_kinetis_tpm)
 	/* All TPM instances share common clock source for counter clock.
 	 * Select the clock source using an arbitrary enabled TPM node.
diff --git a/soc/nxp/mcx/mcxn/Kconfig b/soc/nxp/mcx/mcxn/Kconfig
index c4be2c40554..16b7ef6009b 100644
--- a/soc/nxp/mcx/mcxn/Kconfig
+++ b/soc/nxp/mcx/mcxn/Kconfig
@@ -9,7 +9,6 @@ config SOC_SERIES_MCXN
 	select HAS_MCUX_FLEXCOMM
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_CORTEX_M_HAS_DWT
-	select SOC_RESET_HOOK
 
 config SOC_MCXN947_CPU0
 	select CPU_CORTEX_M33
@@ -17,15 +16,20 @@ config SOC_MCXN947_CPU0
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
 	select ARMV8_M_DSP
+	select SOC_RESET_HOOK
 	select ARM_TRUSTZONE_M
 	select HAS_MCUX_CACHE
 
+config SOC_MCXN947_CPU1
+	select CPU_CORTEX_M33
+
 config SOC_MCXN236
 	select CPU_CORTEX_M33
 	select CPU_HAS_ARM_SAU
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_FPU
 	select ARMV8_M_DSP
+	select SOC_RESET_HOOK
 	select ARM_TRUSTZONE_M
 
 if SOC_SERIES_MCXN
diff --git a/soc/nxp/mcx/mcxn/Kconfig.defconfig b/soc/nxp/mcx/mcxn/Kconfig.defconfig
index ada924c897c..24ba2e4a2ec 100644
--- a/soc/nxp/mcx/mcxn/Kconfig.defconfig
+++ b/soc/nxp/mcx/mcxn/Kconfig.defconfig
@@ -3,6 +3,9 @@
 
 if SOC_SERIES_MCXN
 
+config CORTEX_M_SYSTICK
+	default n if MCUX_LPTMR_TIMER
+
 config MFD
 	default y if DT_HAS_NXP_LP_FLEXCOMM_ENABLED
 
@@ -12,9 +15,6 @@ config NUM_IRQS
 config ROM_START_OFFSET
 	default 0x400 if BOOTLOADER_MCUBOOT
 
-config ZTEST_NO_YIELD
-	default y if (PM && ZTEST)
-
 config MCUX_LPTMR_TIMER
 	default n if (DT_HAS_NXP_OS_TIMER_ENABLED || DT_HAS_ARM_ARMV8M_SYSTICK_ENABLED)
 
@@ -27,4 +27,9 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config FLASH_FILL_BUFFER_SIZE
 	default 128
 
+# The existing SAI diver cannot initialize the PLL on the board,
+# so the PLL settings will not be performed in the driver.
+config I2S_HAS_PLL_SETTING
+	default n
+
 endif # SOC_SERIES_MCXN
diff --git a/soc/nxp/mcx/mcxn/soc.c b/soc/nxp/mcx/mcxn/soc.c
index ddef0d0777b..ce7ae364909 100644
--- a/soc/nxp/mcx/mcxn/soc.c
+++ b/soc/nxp/mcx/mcxn/soc.c
@@ -38,3 +38,24 @@ void soc_reset_hook(void)
  * Throw a build error if user is enabling SPI and UART/I2C on a Flexcomm node.
  */
 DT_FOREACH_STATUS_OKAY(nxp_lpspi, FLEXCOMM_CHECK)
+
+#if defined(CONFIG_SECOND_CORE_MCUX) && defined(CONFIG_SOC_MCXN947_CPU0)
+
+/* This function is also called at deep sleep resume. */
+static int second_core_boot(void)
+{
+	/* Boot source for Core 1 from flash */
+	SYSCON->CPBOOT = ((uint32_t)(char *)DT_REG_ADDR(DT_CHOSEN(zephyr_code_cpu1_partition)) &
+			  SYSCON_CPBOOT_CPBOOT_MASK);
+
+	uint32_t temp = SYSCON->CPUCTRL;
+
+	temp |= 0xc0c40000U;
+	SYSCON->CPUCTRL = temp | SYSCON_CPUCTRL_CPU1RSTEN_MASK | SYSCON_CPUCTRL_CPU1CLKEN_MASK;
+	SYSCON->CPUCTRL = (temp | SYSCON_CPUCTRL_CPU1CLKEN_MASK) & (~SYSCON_CPUCTRL_CPU1RSTEN_MASK);
+
+	return 0;
+}
+
+SYS_INIT(second_core_boot, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+#endif
diff --git a/soc/nxp/mcx/mcxw/CMakeLists.txt b/soc/nxp/mcx/mcxw/CMakeLists.txt
index 1fa189f6215..aad110de351 100644
--- a/soc/nxp/mcx/mcxw/CMakeLists.txt
+++ b/soc/nxp/mcx/mcxw/CMakeLists.txt
@@ -1,8 +1,10 @@
-# Copyright 2023-2024 NXP
+# Copyright 2023-2025 NXP
 #
 # SPDX-License-Identifier: Apache-2.0
 
-zephyr_sources(soc.c mcxw71_platform_init.S)
+zephyr_sources(soc.c)
+zephyr_sources_ifdef(CONFIG_SOC_MCXW716C mcxw71_platform_init.S)
+zephyr_sources_ifdef(CONFIG_SOC_MCXW727C mcxw72_platform_init.S)
 
 zephyr_sources_ifdef(CONFIG_NXP_NBU
   ../../common/nxp_nbu.c
@@ -12,4 +14,6 @@ zephyr_include_directories(.)
 
 set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")
 
-zephyr_linker_sources_ifdef(CONFIG_BT RAM_SECTIONS sections.ld)
+if (CONFIG_BT OR CONFIG_IEEE802154)
+  zephyr_linker_sources(RAM_SECTIONS sections.ld)
+endif()
diff --git a/soc/nxp/mcx/mcxw/Kconfig b/soc/nxp/mcx/mcxw/Kconfig
index 4d127229e6a..2a5c4351ef5 100644
--- a/soc/nxp/mcx/mcxw/Kconfig
+++ b/soc/nxp/mcx/mcxw/Kconfig
@@ -15,5 +15,14 @@ config SOC_SERIES_MCXW
 	select SOC_RESET_HOOK
 	select SOC_EARLY_INIT_HOOK
 	select CLOCK_CONTROL
+	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
 
 	rsource "../../common/Kconfig.nbu"
+
+if SOC_MCXW727C
+
+config MCUX_CORE_SUFFIX
+	default "_cm33_core0" if SOC_MCXW727C_CPU0
+	default "_cm33_core1" if SOC_MCXW727C_CPU1
+
+endif # SOC_MCXW727C
diff --git a/soc/nxp/mcx/mcxw/Kconfig.defconfig b/soc/nxp/mcx/mcxw/Kconfig.defconfig
index 8d715a3aaf7..330d7b80d85 100644
--- a/soc/nxp/mcx/mcxw/Kconfig.defconfig
+++ b/soc/nxp/mcx/mcxw/Kconfig.defconfig
@@ -1,9 +1,13 @@
-# Copyright 2023-2024 NXP
+# Copyright 2023-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_SERIES_MCXW
 
+config CORTEX_M_SYSTICK
+	default n if MCUX_LPTMR_TIMER
+
 config NUM_IRQS
+	default 77 if SOC_MCXW727C
 	default 75
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
@@ -14,6 +18,22 @@ config MCUX_FLASH_K4_API
 
 if BT
 
+config MAIN_STACK_SIZE
+	default 2560
+
+config BT_LONG_WQ_STACK_SIZE
+	default 2560
+
+config SYSTEM_WORKQUEUE_STACK_SIZE
+	default 2048
+
+if SHELL
+
+config SHELL_STACK_SIZE
+	default 4096
+
+endif # SHELL
+
 # Include intercore messaging component
 config NXP_RF_IMU
 	default y
@@ -28,4 +48,14 @@ config HCI_NXP_RX_THREAD
 	default y
 
 endif # BT
+
+if NET_L2_IEEE802154 || NET_L2_OPENTHREAD
+
+# Include intercore messaging component
+config NXP_RF_IMU
+	default y
+
+endif # NET_L2_IEEE802154 || NET_L2_OPENTHREAD
+
+
 endif # SOC_SERIES_MCXW
diff --git a/soc/nxp/mcx/mcxw/Kconfig.soc b/soc/nxp/mcx/mcxw/Kconfig.soc
index f6b03d9b893..9bbc38bcfbd 100644
--- a/soc/nxp/mcx/mcxw/Kconfig.soc
+++ b/soc/nxp/mcx/mcxw/Kconfig.soc
@@ -12,11 +12,28 @@ config SOC_MCXW716C
 	bool
 	select SOC_SERIES_MCXW
 
+config SOC_MCXW727C
+	bool
+	select SOC_SERIES_MCXW
+
+config SOC_MCXW727C_CPU0
+	bool
+	select SOC_MCXW727C
+
+config SOC_MCXW727C_CPU1
+	bool
+	select SOC_MCXW727C
+
 config SOC
 	default "mcxw716c" if SOC_MCXW716C
+	default "mcxw727c" if SOC_MCXW727C
 
 config SOC_PART_NUMBER_MCXW716CMFTA
 	bool
 
+config SOC_PART_NUMBER_MCXW727CMFTA
+	bool
+
 config SOC_PART_NUMBER
 	default "MCXW716CMFTA" if SOC_PART_NUMBER_MCXW716CMFTA
+	default "MCXW727CMFTA" if SOC_PART_NUMBER_MCXW727CMFTA
diff --git a/soc/nxp/mcx/mcxw/mcxw72_platform_init.S b/soc/nxp/mcx/mcxw/mcxw72_platform_init.S
new file mode 100644
index 00000000000..ce02d53580d
--- /dev/null
+++ b/soc/nxp/mcx/mcxw/mcxw72_platform_init.S
@@ -0,0 +1,58 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief MCXW72 Platform-Specific Initialization
+ *
+ * When compared to MCXW71, the Ram Banks with ECC
+ * are located in different addresses.
+ *
+ * MCXW72 SOC reset code that initializes RAM
+ * to prevent ECC causing faults, and calls SystemInit
+ */
+
+#include <zephyr/toolchain.h>
+#include <zephyr/linker/sections.h>
+
+_ASM_FILE_PROLOGUE
+
+GTEXT(soc_reset_hook)
+SECTION_SUBSEC_FUNC(TEXT,_reset_section,soc_reset_hook)
+
+.soc_reset_hook:
+    ldr r0, =0x14000000
+    ldr r1, =.ram_init_ctcm01
+    bics r1, #0x10000000
+    cmp r0, r1
+    bcc .ram_init_done
+.ram_init_ctcm01: /* Initialize ctcm01 */
+    ldr r0, =0x14000000
+    ldr r1, =0x14008000
+    ldr r2, =0
+    ldr r3, =0
+    ldr r4, =0
+    ldr r5, =0
+.loop01:
+    stmia r0!, {r2 - r5}
+    cmp r0, r1
+    bcc.n .loop01
+.ram_init_stcm012: /* Initialize stcm012 */
+    ldr r0, =0x30000000
+    ldr r1, =0x30010000
+.loop012:
+    stmia r0!, {r2 - r5}
+    cmp r0, r1
+    bcc.n .loop012
+.ram_init_stcm8:
+    ldr r0, =0x30038000
+    ldr r1, =0x3003a000
+.loop8: /* Initialize stcm5 */
+    stmia r0!, {r2 - r5}
+    cmp r0, r1
+    bcc.n .loop8
+.ram_init_done:
+    b SystemInit
diff --git a/soc/nxp/mcx/mcxw/soc.c b/soc/nxp/mcx/mcxw/soc.c
index 32fc449f182..94b22710234 100644
--- a/soc/nxp/mcx/mcxw/soc.c
+++ b/soc/nxp/mcx/mcxw/soc.c
@@ -19,7 +19,7 @@
 extern uint32_t SystemCoreClock;
 extern void nxp_nbu_init(void);
 
-static ALWAYS_INLINE void clock_init(void)
+__weak void clock_init(void)
 {
 	/* Unlock Reference Clock Status Registers to allow writes */
 	CLOCK_UnlockFircControlStatusReg();
@@ -39,6 +39,7 @@ static ALWAYS_INLINE void clock_init(void)
 	};
 	/* Enable OSC32K */
 	CCM32K_Set32kOscConfig(CCM32K, kCCM32K_Enable32kHzCrystalOsc, &ccm32k_osc_config);
+
 	/* Disable ROSC Monitor, because switching the source would generate an expected error */
 	CLOCK_SetRoscMonitorMode(kSCG_RoscMonitorDisable);
 
@@ -136,15 +137,19 @@ static ALWAYS_INLINE void clock_init(void)
 		CLOCK_EnableClock(kCLOCK_PortA);
 	}
 
+	if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(gpiob), nxp_kinetis_gpio, okay)) {
+		CLOCK_EnableClock(kCLOCK_PortB);
+	}
+
 	if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(gpioc), nxp_kinetis_gpio, okay)) {
 		CLOCK_EnableClock(kCLOCK_PortC);
 	}
 
-	if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpuart0), nxp_kinetis_lpuart, okay)) {
+	if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpuart0), nxp_lpuart, okay)) {
 		CLOCK_EnableClock(kCLOCK_Lpuart0);
 	}
 
-	if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpuart1), nxp_kinetis_lpuart, okay)) {
+	if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpuart1), nxp_lpuart, okay)) {
 		CLOCK_EnableClock(kCLOCK_Lpuart1);
 	}
 
diff --git a/soc/nxp/mcx/soc.yml b/soc/nxp/mcx/soc.yml
index 265e70b4642..d5591b0b668 100644
--- a/soc/nxp/mcx/soc.yml
+++ b/soc/nxp/mcx/soc.yml
@@ -16,10 +16,17 @@ family:
     - name: mcxc444
   - name: mcxa
     socs:
+    - name: mcxa153
     - name: mcxa156
+    - name: mcxa166
+    - name: mcxa276
   - name: mcxw
     socs:
     - name: mcxw716c
+    - name: mcxw727c
+      cpuclusters:
+      - name: cpu0
+      - name: cpu1
 runners:
   run_once:
     '--erase':
@@ -40,8 +47,14 @@ runners:
         - mcxc242
       - qualifiers:
         - mcxc444
+      - qualifiers:
+        - mcxa153
       - qualifiers:
         - mcxa156
+      - qualifiers:
+        - mcxa166
+      - qualifiers:
+        - mcxa276
       - qualifiers:
         - mcxw716c
     '--reset':
@@ -62,7 +75,13 @@ runners:
         - mcxc242
       - qualifiers:
         - mcxc444
+      - qualifiers:
+        - mcxa153
       - qualifiers:
         - mcxa156
+      - qualifiers:
+        - mcxa166
+      - qualifiers:
+        - mcxa276
       - qualifiers:
         - mcxw716c
diff --git a/soc/nxp/rw/Kconfig b/soc/nxp/rw/Kconfig
index 13b6b4e5dc9..a32483ad0c1 100644
--- a/soc/nxp/rw/Kconfig
+++ b/soc/nxp/rw/Kconfig
@@ -55,4 +55,9 @@ endif # NXP_RW6XX_BOOT_HEADER
 rsource "../common/Kconfig.flexspi_xip"
 rsource "../common/Kconfig.nbu"
 
+config XTAL32K
+	bool "Use the External 32K clock"
+	help
+	  This clock is used by certain peripherals such as RTC.
+
 endif # SOC_SERIES_RW6XX
diff --git a/soc/nxp/rw/Kconfig.defconfig b/soc/nxp/rw/Kconfig.defconfig
index 1ee24dcc7cf..d2da02597fd 100644
--- a/soc/nxp/rw/Kconfig.defconfig
+++ b/soc/nxp/rw/Kconfig.defconfig
@@ -26,7 +26,21 @@ config HCI_NXP_SET_CAL_DATA
 	default y
 
 config MAIN_STACK_SIZE
-	default 1280
+	default 2560
+
+config BT_LONG_WQ_STACK_SIZE
+	default 5120 if (WIFI || IEEE802154)
+	default 2560
+
+config SYSTEM_WORKQUEUE_STACK_SIZE
+	default 2048
+
+if SHELL
+
+config SHELL_STACK_SIZE
+	default 4096
+
+endif # SHELL
 
 endif # BT
 
@@ -39,4 +53,50 @@ config NXP_FW_LOADER
 config NXP_RF_IMU
 	default y if (BT || WIFI || IEEE802154)
 
+if WIFI
+orsource "Kconfig.defconfig.wifi"
+endif # WIFI
+
+if PM
+# For PM mode 3 we change this config to get better accuracy
+# when using the iKHz RTC clock as system clock.
+config SYS_CLOCK_TICKS_PER_SEC
+	default 1000
+	depends on $(dt_nodelabel_enabled,standby)
+
+# Enable PM_DEVICE by default if STANDBY mode is enabled
+# as we use the TURN_OFF and TURN_ON actions to recover
+# from Standby mode (PM Mode 3)
+config PM_DEVICE
+	default y
+	depends on "$(dt_nodelabel_enabled,standby)"
+
+# Enable PM_POLICY_DEVICE_CONSTRAINTS by default when doing PM_DEVICE.
+# This will allow support of device power states.
+config PM_POLICY_DEVICE_CONSTRAINTS
+	default y if PM_DEVICE
+
+# Enable the counter if STANDBY mode is enabled
+# RTC counter is the wakeup source from STANDBY mode
+config COUNTER
+	default y
+	depends on "$(dt_nodelabel_enabled,standby)"
+
+config MCUX_OS_TIMER_PM_POWERED_OFF
+	default y
+
+# PM code that runs from the idle loop has a large
+# footprint. Hence increase the size when PM is enabled.
+config IDLE_STACK_SIZE
+	default 640
+
+endif # PM
+
+if PM_DEVICE
+
+config POWER_DOMAIN
+	default y
+
+endif # PM_DEVICE
+
 endif # SOC_SERIES_RW6XX
diff --git a/soc/nxp/rw/Kconfig.defconfig.wifi b/soc/nxp/rw/Kconfig.defconfig.wifi
new file mode 100644
index 00000000000..7d4d4453137
--- /dev/null
+++ b/soc/nxp/rw/Kconfig.defconfig.wifi
@@ -0,0 +1,17 @@
+# Copyright 2022-2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+if NETWORKING
+if NET_DHCPV4_SERVER
+config NET_DHCPV4_SERVER_ADDR_COUNT
+	default 32
+
+config NET_DHCPV4_SERVER_ICMP_PROBE_TIMEOUT
+	default 100
+endif # NET_DHCPV4_SERVER
+
+if NET_L2_WIFI_MGMT
+config WIFI_MGMT_AP_MAX_NUM_STA
+	default 8 if NXP_WIFI_SOFTAP_SUPPORT
+endif # NET_L2_WIFI_MGMT
+endif # NETWORKING
diff --git a/soc/nxp/rw/boot_header.ld b/soc/nxp/rw/boot_header.ld
index ee0be5b4753..eadc03a4035 100644
--- a/soc/nxp/rw/boot_header.ld
+++ b/soc/nxp/rw/boot_header.ld
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-. = CONFIG_FLASH_CONFIG_OFFSET;
+. += CONFIG_FLASH_CONFIG_OFFSET - (. - __rom_start_address);
 KEEP(*(.flash_conf))
-. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;
+. += CONFIG_IMAGE_VECTOR_TABLE_OFFSET - (. - __rom_start_address);
 KEEP(*(.boot_hdr.ivt))
diff --git a/soc/nxp/rw/pinctrl_defs.h b/soc/nxp/rw/pinctrl_defs.h
index fac97912722..0d98a34783e 100644
--- a/soc/nxp/rw/pinctrl_defs.h
+++ b/soc/nxp/rw/pinctrl_defs.h
@@ -284,49 +284,42 @@
 
 #define IOMUX_GPIO_CLR_28 \
 	(IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
-	IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
 	IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
 	IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
 	IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
 
 #define IOMUX_GPIO_CLR_29 \
 	(IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
-	IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
 	IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
 	IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
 	IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
 
 #define IOMUX_GPIO_CLR_30 \
 	(IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
-	IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
 	IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
 	IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
 	IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
 
 #define IOMUX_GPIO_CLR_31 \
 	(IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
-	IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
 	IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
 	IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
 	IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
 
 #define IOMUX_GPIO_CLR_32 \
 	(IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
-	IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
 	IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
 	IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
 	IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
 
 #define IOMUX_GPIO_CLR_33 \
 	(IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
-	IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
 	IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
 	IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
 	IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
 
 #define IOMUX_GPIO_CLR_34 \
 	(IOMUX_FLEXCOMM_CLR(0x0ULL, 0x0ULL) | /* Flexcomm bits to clear */ \
-	IOMUX_FSEL_CLR(0x2ULL) | /* FSEL bits to clear */ \
 	IOMUX_CTIMER_CLR(0ULL, 0ULL) | /* CTIMER offset to clear */ \
 	IOMUX_SCTIMER_IN_CLR(0ULL, 0ULL) | /* SCTIMER input offset to clear */ \
 	IOMUX_SCTIMER_OUT_CLR(0ULL, 0ULL)) /* SCTIMER output offset to clear */
diff --git a/soc/nxp/rw/power.c b/soc/nxp/rw/power.c
index f4176b6349c..09734d2f505 100644
--- a/soc/nxp/rw/power.c
+++ b/soc/nxp/rw/power.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2023, NXP
+ * Copyright 2023-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,10 +7,16 @@
 #include <zephyr/pm/pm.h>
 #include <zephyr/init.h>
 #include <zephyr/drivers/pinctrl.h>
+#if CONFIG_GPIO && (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin0)) || \
+		    DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin1)))
+#include <zephyr/drivers/gpio/gpio_mcux_lpc.h>
+#endif
 
 #include "fsl_power.h"
 
 #include <zephyr/logging/log.h>
+#include <zephyr/drivers/timer/system_timer.h>
+
 LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
 
 /* Active mode */
@@ -26,10 +32,15 @@ LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
 
 #define NODE_ID DT_INST(0, nxp_pdcfg_power)
 
+extern void clock_init(void);
+
 power_sleep_config_t slp_cfg;
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin0)) || DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin1))
 pinctrl_soc_pin_t pin_cfg;
+#if CONFIG_GPIO
+const struct device *gpio;
+#endif
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin0))
@@ -56,6 +67,81 @@ static void pin1_isr(const struct device *dev)
 }
 #endif
 
+#ifdef CONFIG_MPU
+
+#define MPU_NUM_REGIONS 8
+
+typedef struct mpu_conf {
+	uint32_t CTRL;
+	uint32_t RNR;
+	uint32_t RBAR[MPU_NUM_REGIONS];
+	uint32_t RLAR[MPU_NUM_REGIONS];
+	uint32_t RBAR_A1;
+	uint32_t RLAR_A1;
+	uint32_t RBAR_A2;
+	uint32_t RLAR_A2;
+	uint32_t RBAR_A3;
+	uint32_t RLAR_A3;
+	uint32_t MAIR0;
+	uint32_t MAIR1;
+} mpu_conf;
+mpu_conf saved_mpu_conf;
+
+static void save_mpu_state(void)
+{
+	uint32_t index;
+
+	/*
+	 * MPU is divided in `MPU_NUM_REGIONS` regions.
+	 * Here we save those regions configuration to be restored after PM3 entry
+	 */
+	for (index = 0U; index < MPU_NUM_REGIONS; index++) {
+		MPU->RNR = index;
+		saved_mpu_conf.RBAR[index] = MPU->RBAR;
+		saved_mpu_conf.RLAR[index] = MPU->RLAR;
+	}
+
+	saved_mpu_conf.CTRL = MPU->CTRL;
+	saved_mpu_conf.RNR = MPU->RNR;
+	saved_mpu_conf.RBAR_A1 = MPU->RBAR_A1;
+	saved_mpu_conf.RLAR_A1 = MPU->RLAR_A1;
+	saved_mpu_conf.RBAR_A2 = MPU->RBAR_A2;
+	saved_mpu_conf.RLAR_A2 = MPU->RLAR_A2;
+	saved_mpu_conf.RBAR_A3 = MPU->RBAR_A3;
+	saved_mpu_conf.RLAR_A3 = MPU->RLAR_A3;
+	saved_mpu_conf.MAIR0 = MPU->MAIR0;
+	saved_mpu_conf.MAIR1 = MPU->MAIR1;
+}
+
+static void restore_mpu_state(void)
+{
+	uint32_t index;
+
+	for (index = 0U; index < MPU_NUM_REGIONS; index++) {
+		MPU->RNR = index;
+		MPU->RBAR = saved_mpu_conf.RBAR[index];
+		MPU->RLAR = saved_mpu_conf.RLAR[index];
+	}
+
+	MPU->RNR = saved_mpu_conf.RNR;
+	MPU->RBAR_A1 = saved_mpu_conf.RBAR_A1;
+	MPU->RLAR_A1 = saved_mpu_conf.RLAR_A1;
+	MPU->RBAR_A2 = saved_mpu_conf.RBAR_A2;
+	MPU->RLAR_A2 = saved_mpu_conf.RLAR_A2;
+	MPU->RBAR_A3 = saved_mpu_conf.RBAR_A3;
+	MPU->RLAR_A3 = saved_mpu_conf.RLAR_A3;
+	MPU->MAIR0 = saved_mpu_conf.MAIR0;
+	MPU->MAIR1 = saved_mpu_conf.MAIR1;
+
+	/*
+	 * CTRL register must be restored last in case MPU was enabled,
+	 * because some MPU registers can't be programmed while the MPU is enabled
+	 */
+	MPU->CTRL = saved_mpu_conf.CTRL;
+}
+
+#endif /* CONFIG_MPU */
+
 /* Invoke Low Power/System Off specific Tasks */
 __weak void pm_state_set(enum pm_state state, uint8_t substate_id)
 {
@@ -92,6 +178,28 @@ __weak void pm_state_set(enum pm_state state, uint8_t substate_id)
 		break;
 	case PM_STATE_SUSPEND_TO_IDLE:
 		POWER_EnterPowerMode(POWER_MODE2, &slp_cfg);
+		break;
+	case PM_STATE_STANDBY:
+#ifdef CONFIG_MPU
+		/* Save MPU state before entering PM3 */
+		save_mpu_state();
+#endif /* CONFIG_MPU */
+
+		POWER_EnableWakeup(DT_IRQN(DT_NODELABEL(rtc)));
+		if (POWER_EnterPowerMode(POWER_MODE3, &slp_cfg)) {
+#ifdef CONFIG_MPU
+			/* Restore MPU as is lost after PM3 exit*/
+			restore_mpu_state();
+#endif /* CONFIG_MPU */
+			clock_init();
+
+			sys_clock_idle_exit();
+		}
+
+		/* Clear the RTC wakeup bits */
+		POWER_ClearWakeupStatus(DT_IRQN(DT_NODELABEL(rtc)));
+		POWER_DisableWakeup(DT_IRQN(DT_NODELABEL(rtc)));
+
 		break;
 	default:
 		LOG_DBG("Unsupported power state %u", state);
@@ -105,6 +213,15 @@ __weak void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 	ARG_UNUSED(state);
 	ARG_UNUSED(substate_id);
 
+#if CONFIG_GPIO && (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin0)) || \
+		    DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin1)))
+	if (state == PM_STATE_STANDBY) {
+		/* GPIO_0_24 & GPIO_0_25 are used for wakeup */
+		uint32_t pins = PMU->WAKEUP_STATUS &
+				(PMU_WAKEUP_STATUS_PIN0_MASK | PMU_WAKEUP_STATUS_PIN1_MASK);
+		gpio_mcux_lpc_trigger_cb(gpio, (pins << 24));
+	}
+#endif
 	/* Clear PRIMASK */
 	__enable_irq();
 }
@@ -142,4 +259,16 @@ void nxp_rw6xx_power_init(void)
 	IRQ_CONNECT(DT_IRQN(DT_NODELABEL(pin1)), DT_IRQ(DT_NODELABEL(pin1), priority), pin1_isr,
 		    NULL, 0);
 #endif
+
+	/* Clear the RTC wakeup bits */
+	POWER_ClearWakeupStatus(DT_IRQN(DT_NODELABEL(rtc)));
+	POWER_DisableWakeup(DT_IRQN(DT_NODELABEL(rtc)));
+
+#if CONFIG_GPIO && (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin0)) || \
+		    DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(pin1)))
+	gpio = DEVICE_DT_GET(DT_NODELABEL(hsgpio0));
+	if (!device_is_ready(gpio)) {
+		return;
+	}
+#endif
 }
diff --git a/soc/nxp/rw/soc.c b/soc/nxp/rw/soc.c
index 0ff095a5619..3e928123c49 100644
--- a/soc/nxp/rw/soc.c
+++ b/soc/nxp/rw/soc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2022-2024 NXP
+ * Copyright 2022-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,6 +20,8 @@
 #include "soc.h"
 #include "flexspi_clock_setup.h"
 #include "fsl_ocotp.h"
+
+extern void nxp_nbu_init(void);
 #ifdef CONFIG_NXP_RW6XX_BOOT_HEADER
 extern char z_main_stack[];
 extern char _flash_used[];
@@ -36,7 +38,6 @@ extern void z_arm_debug_monitor(void);
 extern void z_arm_pendsv(void);
 extern void sys_clock_isr(void);
 extern void z_arm_exc_spurious(void);
-extern void nxp_nbu_init(void);
 
 __imx_boot_ivt_section void (*const image_vector_table[])(void) = {
 	(void (*)())(z_main_stack + CONFIG_MAIN_STACK_SIZE), /* 0x00 */
@@ -66,12 +67,6 @@ __imx_boot_ivt_section void (*const image_vector_table[])(void) = {
 };
 #endif /* CONFIG_NXP_RW6XX_BOOT_HEADER */
 
-const clock_avpll_config_t avpll_config = {
-	.ch1Freq = kCLOCK_AvPllChFreq12p288m,
-	.ch2Freq = kCLOCK_AvPllChFreq64m,
-	.enableCali = true
-};
-
 /**
  * @brief Initialize the system clocks and peripheral clocks
  *
@@ -79,7 +74,7 @@ const clock_avpll_config_t avpll_config = {
  * clock needs to be re-initialized on exit from Standby mode. Hence
  * this function is relocated to RAM.
  */
-__ramfunc void clock_init(void)
+__weak __ramfunc void clock_init(void)
 {
 	POWER_DisableGDetVSensors();
 
@@ -94,8 +89,6 @@ __ramfunc void clock_init(void)
 
 	/* Initialize T3 clocks and t3pll_mci_48_60m_irc configured to 48.3MHz */
 	CLOCK_InitT3RefClk(kCLOCK_T3MciIrc48m);
-	/* Enable FFRO */
-	CLOCK_EnableClock(kCLOCK_T3PllMciIrcClk);
 	/* Enable T3 256M clock and SFRO */
 	CLOCK_EnableClock(kCLOCK_T3PllMci256mClk);
 
@@ -113,17 +106,9 @@ __ramfunc void clock_init(void)
 	/* Enable tcpu_mci_clk 260MHz. Keep tcpu_mci_flexspi_clk gated. */
 	CLOCK_EnableClock(kCLOCK_TcpuMciClk);
 
-	/* tddr_mci_flexspi_clk 320MHz */
-	CLOCK_InitTddrRefClk(kCLOCK_TddrFlexspiDiv10);
-	CLOCK_EnableClock(kCLOCK_TddrMciFlexspiClk); /* 320MHz */
-
 	/* Enable AUX0 PLL to 260 MHz */
 	CLOCK_SetClkDiv(kCLOCK_DivAux0PllClk, 1U);
 
-	/* Init AVPLL and enable both channels */
-	CLOCK_InitAvPll(&avpll_config);
-	CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 1U);
-
 	/* Configure MainPll to 260MHz, then let CM33 run on Main PLL. */
 	CLOCK_SetClkDiv(kCLOCK_DivSysCpuAhbClk, 1U);
 	CLOCK_SetClkDiv(kCLOCK_DivMainPllClk, 1U);
@@ -133,6 +118,8 @@ __ramfunc void clock_init(void)
 	CLOCK_SetClkDiv(kCLOCK_DivSystickClk, 1U);
 	CLOCK_AttachClk(kSYSTICK_DIV_to_SYSTICK_CLK);
 
+	SystemCoreClockUpdate();
+
 	/* Set PLL FRG clock to 20MHz. */
 	CLOCK_SetClkDiv(kCLOCK_DivPllFrgClk, 13U);
 
@@ -198,6 +185,10 @@ __ramfunc void clock_init(void)
 #if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm14), nxp_lpc_i2c, okay)) && CONFIG_I2C
 	CLOCK_AttachClk(kSFRO_to_FLEXCOMM14);
 #endif
+#if CONFIG_XTAL32K
+	CLOCK_EnableXtal32K(true);
+	CLOCK_AttachClk(kXTAL32K_to_CLK32K);
+#endif
 
 /* Clock flexcomms when used as SPI */
 #ifdef CONFIG_SPI
@@ -222,13 +213,39 @@ __ramfunc void clock_init(void)
 #endif
 #endif /* CONFIG_SPI */
 
-#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dmic0)) && CONFIG_AUDIO_DMIC_MCUX
+#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(dmic0)) && CONFIG_AUDIO_DMIC_MCUX) || CONFIG_I2S
+	const clock_avpll_config_t avpll_config = {
+		.ch1Freq = kCLOCK_AvPllChFreq12p288m,
+		.ch2Freq = kCLOCK_AvPllChFreq64m,
+		.enableCali = true
+	};
+
+	/* Init AVPLL and enable both channels */
+	CLOCK_InitAvPll(&avpll_config);
+	CLOCK_SetClkDiv(kCLOCK_DivAudioPllClk, 1U);
+
 	/* Clock DMIC from Audio PLL. PLL output is sourced from AVPLL
 	 * channel 1, which is clocked at 12.288 MHz. We can divide this
 	 * by 4 to achieve the desired DMIC bit clk of 3.072 MHz
 	 */
 	CLOCK_AttachClk(kAUDIO_PLL_to_DMIC_CLK);
 	CLOCK_SetClkDiv(kCLOCK_DivDmicClk, 4);
+
+	#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm0), nxp_lpc_i2s, okay))
+		CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM0);
+	#endif
+	#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm1), nxp_lpc_i2s, okay))
+		CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM1);
+	#endif
+	#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm2), nxp_lpc_i2s, okay))
+		CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM2);
+	#endif
+	#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm3), nxp_lpc_i2s, okay))
+		CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM3);
+	#endif
+	#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(flexcomm14), nxp_lpc_i2s, okay))
+		CLOCK_AttachClk(kAUDIO_PLL_to_FLEXCOMM14);
+	#endif
 #endif
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(lcdic)) && CONFIG_MIPI_DBI_NXP_LCDIC
@@ -251,7 +268,8 @@ __ramfunc void clock_init(void)
 #endif
 #endif /* CONFIG_COUNTER_MCUX_CTIMER */
 
-#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb_otg)) && CONFIG_USB_DC_NXP_EHCI
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(usb_otg)) && \
+	(CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)
 	/* Enable system xtal from Analog */
 	SYSCTL2->ANA_GRP_CTRL |= SYSCTL2_ANA_GRP_CTRL_PU_AG_MASK;
 	/* reset USB */
diff --git a/soc/oct/osd32mp15x/Kconfig b/soc/oct/osd32mp15x/Kconfig
new file mode 100644
index 00000000000..3cf3468fdd2
--- /dev/null
+++ b/soc/oct/osd32mp15x/Kconfig
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_OSD32MP15X
+	select SOC_STM32MP15_M4
diff --git a/soc/oct/osd32mp15x/Kconfig.soc b/soc/oct/osd32mp15x/Kconfig.soc
new file mode 100644
index 00000000000..e62fc487b41
--- /dev/null
+++ b/soc/oct/osd32mp15x/Kconfig.soc
@@ -0,0 +1,19 @@
+# Copyright (c) 2024 Antmicro <www.antmicro.com>
+# SPDX-License-Identifier: Apache-2.0
+
+# The OSD32MP15X is technically a SiP (System-in-Package) that consists of
+# the STM32MP15 MCU and additional components like EEPROM. So for
+# OSD32MP1-BRK platform the STM32MP15_M4 SoC is to be indicated as
+# the build target, but since the OSD32MP15x SiP is what a user can actually
+# see on a board, using only STM32MP15_M4 in the Zephyr build
+# infrastructure might be confusing. That's why in the top level of SoC
+# definitions (for user-configurable options in Kconfig, for example)
+# the OSD32MP15X term is used and STM32MP15_M4 underneath.
+
+config SOC_OSD32MP15X
+	bool
+	help
+	  Octavo Systems OSD32MP15X SiP
+
+config SOC
+	default "osd32mp15x" if SOC_OSD32MP15X
diff --git a/soc/oct/osd32mp15x/soc.yml b/soc/oct/osd32mp15x/soc.yml
new file mode 100644
index 00000000000..a254e506568
--- /dev/null
+++ b/soc/oct/osd32mp15x/soc.yml
@@ -0,0 +1,2 @@
+socs:
+  - name: osd32mp15x
diff --git a/soc/openhwgroup/cva6/CMakeLists.txt b/soc/openhwgroup/cva6/CMakeLists.txt
new file mode 100644
index 00000000000..5eab7720420
--- /dev/null
+++ b/soc/openhwgroup/cva6/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(${SOC_SERIES})
+
+zephyr_library_sources_ifdef(CONFIG_CACHE_MANAGEMENT soc_cache_management.c)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
diff --git a/soc/openhwgroup/cva6/Kconfig b/soc/openhwgroup/cva6/Kconfig
new file mode 100644
index 00000000000..a90cbce7cfd
--- /dev/null
+++ b/soc/openhwgroup/cva6/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_OPENHWGROUP_CVA6
+
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_OPENHWGROUP_CVA6
diff --git a/soc/openhwgroup/cva6/Kconfig.defconfig b/soc/openhwgroup/cva6/Kconfig.defconfig
new file mode 100644
index 00000000000..3a063776112
--- /dev/null
+++ b/soc/openhwgroup/cva6/Kconfig.defconfig
@@ -0,0 +1,45 @@
+# Copyright (c) 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_OPENHWGROUP_CVA6
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	int
+	default $(dt_node_int_prop_int,/cpus/cpu@0,timebase-frequency)
+
+config RISCV_SOC_INTERRUPT_INIT
+	default y
+
+# highest implemented first-level interrupt is machine external, 11
+config 2ND_LVL_ISR_TBL_OFFSET
+	default 12
+
+config 2ND_LVL_INTR_00_OFFSET
+	default 11
+
+# 12 first level, 30 second level
+config MAX_IRQ_PER_AGGREGATOR
+	default 30
+
+# one 2nd level aggregator (PLIC) with 30 interrupts
+# offset of 12
+config NUM_IRQS
+	default 42
+
+config MULTI_LEVEL_INTERRUPTS
+	default y
+
+config 2ND_LEVEL_INTERRUPTS
+	default y
+
+# 1 PLIC
+config NUM_2ND_LEVEL_AGGREGATORS
+	default 1
+
+config PLIC
+	default y
+
+config 3RD_LEVEL_INTERRUPTS
+	default n
+
+endif # SOC_FAMILY_OPENHWGROUP_CVA6
diff --git a/soc/openhwgroup/cva6/Kconfig.soc b/soc/openhwgroup/cva6/Kconfig.soc
new file mode 100644
index 00000000000..36b8f2e29a2
--- /dev/null
+++ b/soc/openhwgroup/cva6/Kconfig.soc
@@ -0,0 +1,14 @@
+#Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+#SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_OPENHWGROUP_CVA6
+	bool
+	help
+	  CVA6 RISC-V CPUs, commonly used as soft cores on FPGAs.
+	  There is a 64-bit version with imafdc extensions and sv39 MMU and
+	  several 32-bit configurations, optionally with up to imafdc and sv32 MMU.
+
+config SOC_FAMILY
+	default "openhwgroup_cva6" if SOC_FAMILY_OPENHWGROUP_CVA6
+
+rsource "*/Kconfig.soc"
diff --git a/soc/openhwgroup/cva6/cv32a6/CMakeLists.txt b/soc/openhwgroup/cva6/cv32a6/CMakeLists.txt
new file mode 100644
index 00000000000..da374abd68f
--- /dev/null
+++ b/soc/openhwgroup/cva6/cv32a6/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources()
+
+zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_OPENHWGROUP_CVA6 ".")
diff --git a/soc/openhwgroup/cva6/cv32a6/Kconfig b/soc/openhwgroup/cva6/cv32a6/Kconfig
new file mode 100644
index 00000000000..6582c97826f
--- /dev/null
+++ b/soc/openhwgroup/cva6/cv32a6/Kconfig
@@ -0,0 +1,19 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+# RISCV32 OpenHW Group cva6 configuration options
+
+config SOC_CV32A6
+	select RISCV
+	select RISCV_PRIVILEGED
+	select ATOMIC_OPERATIONS_BUILTIN
+	select RISCV_HAS_PLIC
+	select USE_SWITCH_SUPPORTED
+	select USE_SWITCH
+	select SCHED_IPI_SUPPORTED
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
+	select CPU_HAS_DCACHE
+	select CPU_HAS_ICACHE
diff --git a/soc/openhwgroup/cva6/cv32a6/Kconfig.soc b/soc/openhwgroup/cva6/cv32a6/Kconfig.soc
new file mode 100644
index 00000000000..a1c8eac6e19
--- /dev/null
+++ b/soc/openhwgroup/cva6/cv32a6/Kconfig.soc
@@ -0,0 +1,22 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_CV32A6
+	bool
+	select SOC_FAMILY_OPENHWGROUP_CVA6
+	help
+	  CVA6 32-bit RISC-V CPUs, commonly used as soft cores on FPGAs.
+	  This configuration works with the upstream project (https://github.com/openhwgroup/cva6).
+
+config SOC_CV32A6
+	bool
+	select SOC_SERIES_CV32A6
+	help
+	  Minimal CVA6 core in 32-bit configuration: ima extensions, no MMU or PMP,
+	  SoC with CLINT, PLIC, UART, SPI, and Ethernet (Xilinx or lowRISC).
+
+config SOC_SERIES
+	default "cv32a6" if SOC_SERIES_CV32A6
+
+config SOC
+	default "cv32a6" if SOC_CV32A6
diff --git a/soc/openhwgroup/cva6/cv64a6/CMakeLists.txt b/soc/openhwgroup/cva6/cv64a6/CMakeLists.txt
new file mode 100644
index 00000000000..da374abd68f
--- /dev/null
+++ b/soc/openhwgroup/cva6/cv64a6/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources()
+
+zephyr_include_directories_ifdef(CONFIG_SOC_FAMILY_OPENHWGROUP_CVA6 ".")
diff --git a/soc/openhwgroup/cva6/cv64a6/Kconfig b/soc/openhwgroup/cva6/cv64a6/Kconfig
new file mode 100644
index 00000000000..64d7f54bd04
--- /dev/null
+++ b/soc/openhwgroup/cva6/cv64a6/Kconfig
@@ -0,0 +1,35 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+# RISCV64 OpenHW Group cva6 configuration options
+
+# Shared properties
+config SOC_CV64A6
+	bool
+	select RISCV
+	select RISCV_PRIVILEGED
+	select ATOMIC_OPERATIONS_BUILTIN
+	select RISCV_HAS_PLIC
+	select USE_SWITCH_SUPPORTED
+	select USE_SWITCH
+	select SCHED_IPI_SUPPORTED
+	select 64BIT
+	select RISCV_ISA_RV64I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_C
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
+	select CPU_HAS_DCACHE
+	select CPU_HAS_ICACHE
+
+# Variant with FPU
+config SOC_CV64A6_IMAFDC
+	select SOC_CV64A6
+	select CPU_HAS_FPU
+	select CPU_HAS_FPU_DOUBLE_PRECISION
+	select RISCV_ISA_EXT_F
+	select RISCV_ISA_EXT_D
+
+# Variant without FPU
+config SOC_CV64A6_IMAC
+	select SOC_CV64A6
diff --git a/soc/openhwgroup/cva6/cv64a6/Kconfig.soc b/soc/openhwgroup/cva6/cv64a6/Kconfig.soc
new file mode 100644
index 00000000000..c3be28de834
--- /dev/null
+++ b/soc/openhwgroup/cva6/cv64a6/Kconfig.soc
@@ -0,0 +1,32 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_CV64A6
+	bool
+	select SOC_FAMILY_OPENHWGROUP_CVA6
+	help
+	  CVA6 64-bit RISC-V CPUs, commonly used as soft cores on FPGAs.
+	  This configuration works with the upstream project (https://github.com/openhwgroup/cva6)
+	  as well as the forked project with support for the Xilinx AXI Ethernet Subsystem
+	  (https://github.com/cispa/CVA6-Vivado-Project-with-Xilinx-AXI-Ethernet).
+
+config SOC_CV64A6_IMAFDC
+	bool
+	select SOC_SERIES_CV64A6
+	help
+	  Standard CVA6 core in 64-bit configuration: SV39 MMU and SoC with CLINT, PLIC, UART,
+	  SPI, and Ethernet (Xilinx or lowRISC). Supports imafdc instruction sets.
+
+config SOC_CV64A6_IMAC
+	bool
+	select SOC_SERIES_CV64A6
+	help
+	  Minimal CVA6 core in 64-bit configuration: SV39 MMU and SoC with CLINT, PLIC, UART,
+	  SPI, and Ethernet (Xilinx or lowRISC). Supports imac instruction sets.
+
+config SOC_SERIES
+	default "cv64a6" if SOC_SERIES_CV64A6
+
+config SOC
+	default "cv64a6_imac" if SOC_CV64A6_IMAC
+	default "cv64a6_imafdc" if SOC_CV64A6_IMAFDC
diff --git a/soc/openhwgroup/cva6/cva6.h b/soc/openhwgroup/cva6/cva6.h
new file mode 100644
index 00000000000..f2bd8a3432e
--- /dev/null
+++ b/soc/openhwgroup/cva6/cva6.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright(c) 2024, CISPA Helmholtz Center for Information Security
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * @file
+ * OpenHwGroup CVA6 declarations
+ */
+
+#ifndef ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H
+#define ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * CVA6 provides two custom CSRs for cache management:
+ * CSR 7C1 controls the data cache, CSR 7C0 controls the instruction cache.
+ * The least significant bit of the CSRs can be written to enable or disable the cache.
+ * Writing a value of 1 means enabling the cache, writing 0 disables it.
+ * After reset, both caches are enabled by default.
+ *
+ */
+
+#define SOC_CVA6_CUSTOM_CSR_DCACHE 0x7C1
+#define SOC_CVA6_CUSTOM_CSR_ICACHE 0x7C0
+
+#define SOC_CVA6_CUSTOM_CSR_DCACHE_ENABLE  0x1
+#define SOC_CVA6_CUSTOM_CSR_DCACHE_DISABLE 0x0
+
+#define SOC_CVA6_CUSTOM_CSR_ICACHE_ENABLE  0x1
+#define SOC_CVA6_CUSTOM_CSR_ICACHE_DISABLE 0x0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_SOC_RISCV_OPENHWGROUP_CVA6_H */
diff --git a/soc/openhwgroup/cva6/soc.yml b/soc/openhwgroup/cva6/soc.yml
new file mode 100644
index 00000000000..bd250f81d4b
--- /dev/null
+++ b/soc/openhwgroup/cva6/soc.yml
@@ -0,0 +1,13 @@
+# Copyright 2024 CISPA Helmholtz Center for Information Security gGmbH
+# SPDX-License-Identifier: Apache-2.0
+family:
+- name: openhwgroup_cva6
+  series:
+  - name: cv64a6
+    socs:
+    - name: cv64a6_imafdc
+    - name: cv64a6_imac
+  - name: cv32a6
+    socs:
+    - name: cv32a6
+vendor: OpenHW Group
diff --git a/soc/openhwgroup/cva6/soc_cache_management.c b/soc/openhwgroup/cva6/soc_cache_management.c
new file mode 100644
index 00000000000..0e602779b2d
--- /dev/null
+++ b/soc/openhwgroup/cva6/soc_cache_management.c
@@ -0,0 +1,124 @@
+/*
+ * Non-standard CVA6 cache management operations.
+ *
+ * Copyright(c) 2024, CISPA Helmholtz Center for Information Security
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stddef.h>
+#include <zephyr/arch/cache.h>
+#include <zephyr/arch/riscv/csr.h>
+#include <zephyr/kernel.h>
+
+#include "cva6.h"
+
+void __weak arch_dcache_enable(void)
+{
+	csr_write(SOC_CVA6_CUSTOM_CSR_DCACHE, SOC_CVA6_CUSTOM_CSR_DCACHE_ENABLE);
+}
+
+void __weak arch_dcache_disable(void)
+{
+	csr_write(SOC_CVA6_CUSTOM_CSR_DCACHE, SOC_CVA6_CUSTOM_CSR_DCACHE_DISABLE);
+}
+
+int __weak arch_dcache_flush_all(void)
+{
+	arch_dcache_disable();
+	arch_dcache_enable();
+
+	return 0;
+}
+
+int __weak arch_dcache_invd_all(void)
+{
+	return arch_dcache_flush_all();
+}
+
+int __weak arch_dcache_flush_and_invd_all(void)
+{
+	return arch_dcache_flush_all();
+}
+
+/* FIXME currently not supported by all CVA6 - overwrite at board or SoC level */
+int __weak arch_dcache_flush_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+
+	return arch_dcache_flush_all();
+}
+
+int __weak arch_dcache_invd_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+
+	return arch_dcache_flush_all();
+}
+
+int __weak arch_dcache_flush_and_invd_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+
+	return arch_dcache_flush_all();
+}
+
+void __weak arch_icache_enable(void)
+{
+	csr_write(SOC_CVA6_CUSTOM_CSR_ICACHE, SOC_CVA6_CUSTOM_CSR_ICACHE_ENABLE);
+}
+
+void __weak arch_icache_disable(void)
+{
+	csr_write(SOC_CVA6_CUSTOM_CSR_ICACHE, SOC_CVA6_CUSTOM_CSR_ICACHE_DISABLE);
+}
+
+int __weak arch_icache_flush_all(void)
+{
+	arch_icache_disable();
+	arch_icache_enable();
+
+	return 0;
+}
+
+int __weak arch_icache_invd_all(void)
+{
+	return arch_icache_flush_all();
+}
+
+int __weak arch_icache_flush_and_invd_all(void)
+{
+	return arch_icache_flush_all();
+}
+
+/* FIXME currently not supported by all CVA6 - overwrite at board or SoC level */
+int __weak arch_icache_flush_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+
+	return arch_icache_flush_all();
+}
+
+int __weak arch_icache_invd_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+
+	return arch_icache_flush_all();
+}
+
+int __weak arch_icache_flush_and_invd_range(void *addr, size_t size)
+{
+	ARG_UNUSED(addr);
+	ARG_UNUSED(size);
+
+	return arch_icache_flush_all();
+}
+
+/* FIXME there is no common implementation for RISC-V, so we provide a SoC-level definition */
+/* this prevents a linker error when the function is not defined */
+void __weak arch_cache_init(void)
+{
+}
diff --git a/soc/raspberrypi/rpi_pico/rp2350/Kconfig b/soc/raspberrypi/rpi_pico/rp2350/Kconfig
index 2de28a5dd56..28553021e2c 100644
--- a/soc/raspberrypi/rpi_pico/rp2350/Kconfig
+++ b/soc/raspberrypi/rpi_pico/rp2350/Kconfig
@@ -18,6 +18,15 @@ config SOC_RP2350A_M33
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_ARM_SAU
 
+config SOC_RP2350B_M33
+	select ARM
+	select ARM_TRUSTZONE_M
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select CPU_CORTEX_M_HAS_VTOR
+	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_ARM_SAU
+
 config RP2_REQUIRES_IMAGE_DEFINITION_BLOCK
 	bool
 	default y
diff --git a/soc/raspberrypi/rpi_pico/rp2350/Kconfig.soc b/soc/raspberrypi/rpi_pico/rp2350/Kconfig.soc
index 19012bb5648..069bc56cfbf 100644
--- a/soc/raspberrypi/rpi_pico/rp2350/Kconfig.soc
+++ b/soc/raspberrypi/rpi_pico/rp2350/Kconfig.soc
@@ -20,5 +20,16 @@ config SOC_RP2350A_M33
 	help
 	  Use the RP2350A with a Cortex-M33 core in both 'sockets'.
 
+config SOC_RP2350B
+	bool
+	select SOC_SERIES_RP2350
+
+config SOC_RP2350B_M33
+	bool
+	select SOC_RP2350B
+	help
+	  Use the RP2350B with a Cortex-M33 core in both 'sockets'.
+
 config SOC
 	default "rp2350a" if SOC_RP2350A
+	default "rp2350b" if SOC_RP2350B
diff --git a/soc/raspberrypi/rpi_pico/soc.yml b/soc/raspberrypi/rpi_pico/soc.yml
index 32039c20944..fac2f36cd96 100644
--- a/soc/raspberrypi/rpi_pico/soc.yml
+++ b/soc/raspberrypi/rpi_pico/soc.yml
@@ -9,3 +9,6 @@ family:
     - name: rp2350a
       cpuclusters:
       - name: m33
+    - name: rp2350b
+      cpuclusters:
+      - name: m33
diff --git a/soc/realtek/ec/common/rts5912_imgtool/img_gen.py b/soc/realtek/ec/common/rts5912_imgtool/img_gen.py
index 53fcefb916e..0a7d8de5f15 100644
--- a/soc/realtek/ec/common/rts5912_imgtool/img_gen.py
+++ b/soc/realtek/ec/common/rts5912_imgtool/img_gen.py
@@ -10,6 +10,7 @@
 """
 
 import argparse
+import hashlib
 import os
 import struct
 
@@ -24,6 +25,11 @@
 DUAL_read = "0x3B"
 QUAD_read = "0x6B"
 
+TAG_MAGIC = 0x6907
+TAG_LEN = 0x0028
+TAG_TYPE_SHA = 0x0010
+TAG_SHA_LEN = 0x0020
+
 
 def parse_args():
     """
@@ -88,10 +94,10 @@ def img_gen(load_addr, spi_freq, spi_rdcmd, original_bin, signed_bin):
     To obtain the RTS5912 image header and output a new BIN file
     """
     img_size = os.path.getsize(original_bin)
-    payload = bytearray(0)
-    img_size = os.path.getsize(original_bin)
+    hdr_payload = bytearray(0)
+    tag_payload = bytearray(0)
 
-    fmt = (
+    hdr_fmt = (
         "<"
         +
         # type ImageHdr struct {
@@ -108,8 +114,8 @@ def img_gen(load_addr, spi_freq, spi_rdcmd, original_bin, signed_bin):
         + "H"  # reserved uint16
     )  # }
 
-    header = struct.pack(
-        fmt,
+    hdr = struct.pack(
+        hdr_fmt,
         IMAGE_MAGIC,
         load_addr,
         IMAGE_HDR_SIZE,
@@ -123,15 +129,37 @@ def img_gen(load_addr, spi_freq, spi_rdcmd, original_bin, signed_bin):
         0,
     )
 
-    payload[: len(header)] = header
+    hdr_payload[: len(hdr)] = hdr
+
+    tag_fmt = (
+        "<"
+        +
+        # type ImageTag struct {
+        "H"  # Magic      uint16
+        + "H"  # TagSz    uint16
+        + "H"  # TagHash  uint16
+        + "H"  # HashSz   uint16
+    )  # }
+
+    tag = struct.pack(tag_fmt, TAG_MAGIC, TAG_LEN, TAG_TYPE_SHA, TAG_SHA_LEN)
+
+    tag_payload[: len(tag)] = tag
+
+    sha = hashlib.sha256()
+    sha.update(hdr_payload)
+    with open(original_bin, "rb") as original:
+        sha.update(original.read())
+    digest = sha.digest()
 
     with open(signed_bin, "wb") as signed:
-        signed.write(payload)
+        signed.write(hdr_payload)
         signed.flush()
         signed.close()
 
     with open(signed_bin, "ab") as signed, open(original_bin, "rb") as original:
         signed.write(original.read())
+        signed.write(tag_payload)
+        signed.write(digest)
         signed.flush()
         signed.close()
         original.close()
diff --git a/soc/realtek/ec/rts5912/CMakeLists.txt b/soc/realtek/ec/rts5912/CMakeLists.txt
index 219c68e5a8d..b10306f1768 100644
--- a/soc/realtek/ec/rts5912/CMakeLists.txt
+++ b/soc/realtek/ec/rts5912/CMakeLists.txt
@@ -12,6 +12,8 @@ zephyr_sources_ifdef(CONFIG_PM
   power.c
   )
 
-zephyr_sources_ifdef(CONFIG_DT_HAS_SWJ_CONNECTOR_ENABLED debug_swj.c)
+zephyr_sources_ifdef(CONFIG_RTS5912_DEBUG_SWJ debug_swj.c)
+zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c)
+zephyr_sources_ifdef(CONFIG_SOC_RTS5912_ULPM rts5912_ulpm.c)
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/realtek/ec/rts5912/Kconfig b/soc/realtek/ec/rts5912/Kconfig
index aebac7b3d00..6673b017207 100644
--- a/soc/realtek/ec/rts5912/Kconfig
+++ b/soc/realtek/ec/rts5912/Kconfig
@@ -22,4 +22,19 @@ config RTS5912_ON_ENTER_CPU_IDLE_HOOK
 	  If needed, this hook can be used to prevent the CPU from actually
 	  entering sleep by skipping the WFE/WFI instruction.
 
+config RTS5912_DEBUG_SWJ
+	bool "Serial wire JTAG"
+	default y
+	depends on DT_HAS_SWJ_CONNECTOR_ENABLED
+	help
+	  Enables the serial wire JTAG connection on the RTS5912 EC.
+
+config SOC_RTS5912_ULPM
+	bool "Realtek RTS5912 ULPM (Ultra Low Power Mode)"
+	default y
+	depends on DT_HAS_REALTEK_RTS5912_ULPM_ENABLED
+	select HAS_POWEROFF
+	help
+	  Enable support for RTS5912 ULPM PWR wake-up pins.
+
 endif # SOC_SERIES_RTS5912
diff --git a/soc/realtek/ec/rts5912/Kconfig.defconfig.rts5912 b/soc/realtek/ec/rts5912/Kconfig.defconfig.rts5912
index 5ff22637497..517b5ed6bdf 100644
--- a/soc/realtek/ec/rts5912/Kconfig.defconfig.rts5912
+++ b/soc/realtek/ec/rts5912/Kconfig.defconfig.rts5912
@@ -18,6 +18,7 @@ config SYS_CLOCK_TICKS_PER_SEC
 
 config ARCH_HAS_CUSTOM_BUSY_WAIT
 	default y
+	depends on !COUNTER_REALTEK_RTS5912_SLWTMR
 
 endif # REALTEK_RTS5912_RTMR
 
diff --git a/soc/realtek/ec/rts5912/poweroff.c b/soc/realtek/ec/rts5912/poweroff.c
new file mode 100644
index 00000000000..e95e95574da
--- /dev/null
+++ b/soc/realtek/ec/rts5912/poweroff.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2025 Realtek Semiconductor Corporation, SIBG-SD7
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/sys/poweroff.h>
+#include <zephyr/toolchain.h>
+#include "rts5912_ulpm.h"
+
+void z_sys_poweroff(void)
+{
+	if (IS_ENABLED(CONFIG_SOC_RTS5912_ULPM)) {
+		rts5912_ulpm_enable();
+
+		/* Spin and wait for ULPM */
+		while (1) {
+			;
+		}
+		CODE_UNREACHABLE;
+	}
+}
diff --git a/soc/realtek/ec/rts5912/reg/reg_adc.h b/soc/realtek/ec/rts5912/reg/reg_adc.h
new file mode 100644
index 00000000000..0b54d13c8af
--- /dev/null
+++ b/soc/realtek/ec/rts5912/reg/reg_adc.h
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2025 Realtek, SIBG-SD7
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_ADC_H
+#define ZEPHYR_SOC_REALTEK_RTS5912_REG_ADC_H
+
+struct adc_regs {
+	uint32_t ctrl;
+	uint32_t chctrl;
+	uint32_t sts;
+	uint32_t chdata[12];
+	uint32_t coeffa;
+	uint32_t coeffb;
+};
+
+/* CTRL */
+#define ADC_CTRL_EN         BIT(0)
+#define ADC_CTRL_START      BIT(1)
+#define ADC_CTRL_RST        BIT(2)
+#define ADC_CTRL_MDSEL      BIT(3)
+#define ADC_CTRL_SGLDNINTEN BIT(4)
+#define ADC_CTRL_RPTDNINTEN BIT(5)
+
+/* CHCTRL */
+#define ADC_CHCTRL_CH0EN  BIT(0)
+#define ADC_CHCTRL_CH1EN  BIT(1)
+#define ADC_CHCTRL_CH2EN  BIT(2)
+#define ADC_CHCTRL_CH3EN  BIT(3)
+#define ADC_CHCTRL_CH4EN  BIT(4)
+#define ADC_CHCTRL_CH5EN  BIT(5)
+#define ADC_CHCTRL_CH6EN  BIT(6)
+#define ADC_CHCTRL_CH7EN  BIT(7)
+#define ADC_CHCTRL_CH8EN  BIT(8)
+#define ADC_CHCTRL_CH9EN  BIT(9)
+#define ADC_CHCTRL_CH10EN BIT(10)
+#define ADC_CHCTRL_CH11EN BIT(11)
+#define ADC_CHCTRL_LPFBP  BIT(12)
+#define ADC_CHCTRL_CALBP  BIT(24)
+
+/* STS */
+#define ADC_STS_CH0DN  BIT(0)
+#define ADC_STS_CH1DN  BIT(1)
+#define ADC_STS_CH2DN  BIT(2)
+#define ADC_STS_CH3DN  BIT(3)
+#define ADC_STS_CH4DN  BIT(4)
+#define ADC_STS_CH5DN  BIT(5)
+#define ADC_STS_CH6DN  BIT(6)
+#define ADC_STS_CH7DN  BIT(7)
+#define ADC_STS_CH8DN  BIT(8)
+#define ADC_STS_CH9DN  BIT(9)
+#define ADC_STS_CH10DN BIT(10)
+#define ADC_STS_CH11DN BIT(11)
+#define ADC_STS_SGLDN  BIT(12)
+#define ADC_STS_RPTDN  BIT(13)
+#define ADC_STS_RDY    BIT(16)
+#define ADC_STS_LPFSTB BIT(17)
+
+/* CHDATA */
+#define ADC_CHDATA_RESULT_Pos (0U)
+#define ADC_CHDATA_RESULT_Msk GENMASK(11, 0)
+
+#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_ADC_H */
diff --git a/soc/realtek/ec/rts5912/reg/reg_kbm.h b/soc/realtek/ec/rts5912/reg/reg_kbm.h
new file mode 100644
index 00000000000..1d27d5ecc4f
--- /dev/null
+++ b/soc/realtek/ec/rts5912/reg/reg_kbm.h
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2025 Realtek, SIBG-SD7
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_KBM_H
+#define ZEPHYR_SOC_REALTEK_RTS5912_REG_KBM_H
+
+/**
+ * @brief Keyboard Matrix Controller (KBM)
+ */
+
+struct kbm_regs {
+	uint32_t scan_out;
+	uint32_t scan_in;
+	uint32_t int_en;
+	uint32_t ctrl;
+};
+
+#define KBM_CTRL_KSOTYPE_Msk   BIT(0)
+#define KBM_CTRL_KSI8EN_Msk    BIT(1)
+#define KBM_CTRL_KSI9EN_Msk    BIT(2)
+#define KBM_CTRL_KSO18EN_Msk   BIT(16)
+#define KBM_CTRL_KSO19EN_Msk   BIT(17)
+#define KBM_CTRL_KSIINTSTS_Msk BIT(18)
+
+#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_KBM_H */
diff --git a/soc/realtek/ec/rts5912/reg/reg_rtc.h b/soc/realtek/ec/rts5912/reg/reg_rtc.h
new file mode 100644
index 00000000000..c339fa653a0
--- /dev/null
+++ b/soc/realtek/ec/rts5912/reg/reg_rtc.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2025 Realtek, SIBG-SD7
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_RTC_H
+#define ZEPHYR_SOC_REALTEK_RTS5912_REG_RTC_H
+
+#include <zephyr/kernel.h>
+
+/*
+ * @brief RTC Controller (RTC)
+ */
+
+typedef struct {
+	volatile uint8_t SEC;
+	volatile uint8_t SECALARM;
+	volatile uint8_t MIN;
+	volatile uint8_t MINALARM;
+	volatile uint8_t HR;
+	volatile uint8_t HRALARM;
+	volatile uint8_t DAYWEEK;
+	volatile uint8_t DAYMONTH;
+	volatile uint8_t MONTH;
+	volatile uint8_t YEAR;
+	volatile uint8_t CTRL0;
+	volatile uint8_t CTRL1;
+	volatile uint8_t CTRL2;
+	volatile uint8_t DAYWEEKALARM;
+	volatile uint8_t DAYMONTHALARM;
+	volatile const uint8_t RESERVED;
+	volatile const uint32_t RESERVED1[2];
+	volatile uint32_t DLSFW;
+	volatile uint32_t DLSBW;
+	volatile uint32_t WEEK;
+} RTC_Type;
+
+/* HR */
+#define RTC_HR_VAL_Pos         (0UL)
+#define RTC_HR_VAL_Msk         GENMASK(5, 0)
+#define RTC_HR_AMPM_Pos        (7UL)
+#define RTC_HR_AMPM_Msk        BIT(RTC_HR_AMPM_Pos)
+/* DAYWEEK */
+#define RTC_DAYWEEK_Pos        (0UL)
+#define RTC_DAYWEEK_Msk        GENMASK(3, 0)
+/* DAYMONTH */
+#define RTC_DAYMONTH_Pos       (0UL)
+#define RTC_DAYMONTH_Msk       GENMASK(5, 0)
+/* CTRL0 */
+#define RTC_CTRL0_DIVCTL_Pos   (4UL)
+#define RTC_CTRL0_DIVCTL_Msk   GENMASK(6, 4)
+/* CTRL1 */
+#define RTC_CTRL1_HRMODE_Pos   (1UL)
+#define RTC_CTRL1_HRMODE_Msk   BIT(RTC_CTRL1_HRMODE_Pos)
+#define RTC_CTRL1_DATEMODE_Pos (2UL)
+#define RTC_CTRL1_DATEMODE_Msk BIT(RTC_CTRL1_DATEMODE_Pos)
+#define RTC_CTRL1_SETMODE_Pos  (7UL)
+#define RTC_CTRL1_SETMODE_Msk  BIT(RTC_CTRL1_SETMODE_Pos)
+/* WEEK */
+#define RTC_WEEK_NUM_Pos       (0UL)
+#define RTC_WEEK_NUM_Msk       GENMASK(7, 0)
+
+#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_RTC_H */
diff --git a/soc/realtek/ec/rts5912/reg/reg_slwtmr.h b/soc/realtek/ec/rts5912/reg/reg_slwtmr.h
new file mode 100644
index 00000000000..be37eafc0d5
--- /dev/null
+++ b/soc/realtek/ec/rts5912/reg/reg_slwtmr.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 Realtek, SIBG-SD7
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_SLWTMR_H
+#define ZEPHYR_SOC_REALTEK_RTS5912_REG_SLWTMR_H
+
+/**
+ * @brief SLOW Timer Controller (SLWTMR)
+ */
+
+struct slwtmr_type {
+	uint32_t ldcnt;
+	uint32_t cnt;
+	uint32_t ctrl;
+	uint32_t insts;
+};
+
+/* CTRL */
+#define SLWTMR_CTRL_EN BIT(0)
+
+#define SLWTMR_CTRL_MDSELS_ONESHOT 0
+#define SLWTMR_CTRL_MDSELS_PERIOD  BIT(1)
+
+#define SLWTMR_CTRL_INTEN_EN BIT(2)
+/* INTSTS */
+#define SLWTMR_INTSTS_STS    BIT(0)
+
+#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_SLWTMR_H */
diff --git a/soc/realtek/ec/rts5912/reg/reg_system.h b/soc/realtek/ec/rts5912/reg/reg_system.h
index 673baf4ac35..745d6319674 100644
--- a/soc/realtek/ec/rts5912/reg/reg_system.h
+++ b/soc/realtek/ec/rts5912/reg/reg_system.h
@@ -294,8 +294,8 @@ typedef struct {
 #define SYSTEM_VIVOCTRL_VIN2POL_Msk          BIT(SYSTEM_VIVOCTRL_VIN2POL_Pos)
 #define SYSTEM_VIVOCTRL_VIN3POL_Pos          (15UL)
 #define SYSTEM_VIVOCTRL_VIN3POL_Msk          BIT(SYSTEM_VIVOCTRL_VIN3POL_Pos)
-#define SYSTEM_VIVOCTRL_VIN4POL_Pos          (16UL)
-#define SYSTEM_VIVOCTRL_VIN4POL_Msk          BIT(SYSTEM_VIVOCTRL_VIN4POL_Pos)
+#define SYSTEM_VIVOCTRL_VODEF_Pos            (16UL)
+#define SYSTEM_VIVOCTRL_VODEF_Msk            BIT(SYSTEM_VIVOCTRL_VODEF_Pos)
 #define SYSTEM_VIVOCTRL_VIN5POL_Pos          (17UL)
 #define SYSTEM_VIVOCTRL_VIN5POL_Msk          BIT(SYSTEM_VIVOCTRL_VIN5POL_Pos)
 #define SYSTEM_VIVOCTRL_REGWREN_Pos          (30UL)
@@ -332,4 +332,6 @@ typedef struct {
 #define SYSTEM_PERICLKPWR2_RC32KSRC_Pos      (30UL)
 #define SYSTEM_PERICLKPWR2_RC32KSRC_Msk      GENMASK(31, 30)
 
+#define RTS5912_SCCON_REG_BASE ((SYSTEM_Type *)(DT_REG_ADDR(DT_NODELABEL(sccon))))
+
 #endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_SYSTEM_H */
diff --git a/soc/realtek/ec/rts5912/reg/reg_tacho.h b/soc/realtek/ec/rts5912/reg/reg_tacho.h
new file mode 100644
index 00000000000..4e7b9d0851f
--- /dev/null
+++ b/soc/realtek/ec/rts5912/reg/reg_tacho.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2025 Realtek, SIBG-SD7
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_TACHO_H
+#define ZEPHYR_SOC_REALTEK_RTS5912_REG_TACHO_H
+
+struct tacho_regs {
+	uint32_t ctrl;
+	uint32_t status;
+	uint32_t limit_high;
+	uint32_t limit_low;
+	uint32_t int_en;
+};
+
+/* CTRL */
+#define TACHO_CTRL_EN          BIT(0UL)
+#define TACHO_CTRL_FILTEREN    BIT(1UL)
+#define TACHO_CTRL_SELEDGE_Pos (2UL)
+#define TACHO_CTRL_SELEDGE_Msk GENMASK(3, TACHO_CTRL_SELEDGE_Pos)
+#define TACHO_CTRL_READMODE    BIT(4UL)
+#define TACHO_CTRL_CNT_Pos     (16UL)
+#define TACHO_CTRL_CNT_Msk     GENMASK(31, TACHO_CTRL_CNT_Pos)
+/* STS */
+#define TACHO_STS_LIMIT        BIT(0UL)
+#define TACHO_STS_PIN          BIT(1UL)
+#define TACHO_STS_CHG          BIT(2UL)
+#define TACHO_STS_CNTRDY       BIT(3UL)
+/* LIMITH */
+#define TACHO_LIMITH_VAL_Pos   (0UL)
+#define TACHO_LIMITH_VAL_Msk   GENMASK(15, TACHO_LIMITH_VAL_Pos)
+/* LIMITL */
+#define TACHO_LIMITL_VAL_Pos   (0UL)
+#define TACHO_LIMITL_VAL_Msk   GENMASK(15, TACHO_LIMITL_VAL_Pos)
+/* INTEN */
+#define TACHO_INTEN_LIMITEN    BIT(0UL)
+#define TACHO_INTEN_CNTRDYEN   BIT(1UL)
+#define TACHO_INTEN_CHGEN      BIT(2UL)
+
+#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_TACHO_H */
diff --git a/soc/realtek/ec/rts5912/reg/reg_timer.h b/soc/realtek/ec/rts5912/reg/reg_timer.h
new file mode 100644
index 00000000000..b3cd8f5583b
--- /dev/null
+++ b/soc/realtek/ec/rts5912/reg/reg_timer.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025 Realtek, SIBG-SD7
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_TMRER_H
+#define ZEPHYR_SOC_REALTEK_RTS5912_REG_TMRER_H
+
+/**
+ * @brief 32-bit Timer Controller (TMR)
+ */
+
+struct timer32_type {
+	uint32_t ldcnt;
+	uint32_t cnt;
+	uint32_t ctrl;
+	uint32_t intclr;
+	uint32_t intsts;
+};
+
+/* CTRL */
+#define TIMER32_CTRL_EN BIT(0)
+
+#define TIMER32_CTRL_MDSELS_ONESHOT 0
+#define TIMER32_CTRL_MDSELS_PERIOD  BIT(1)
+
+#define TIMER32_CTRL_INTEN_DIS BIT(2)
+/* INTCLR */
+#define TIMER32_INTCLR_INTCLR  BIT(0)
+/* INTSTS */
+#define TIMER32_INTSTS_STS     (0UL)
+
+#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_TMRER_H */
diff --git a/soc/realtek/ec/rts5912/reg/reg_wdt.h b/soc/realtek/ec/rts5912/reg/reg_wdt.h
new file mode 100644
index 00000000000..2f3fd5db6f1
--- /dev/null
+++ b/soc/realtek/ec/rts5912/reg/reg_wdt.h
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2025 Realtek, SIBG-SD7
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_REALTEK_RTS5912_REG_WDT_H
+#define ZEPHYR_SOC_REALTEK_RTS5912_REG_WDT_H
+
+/**
+ * @brief WDT Controller (WDT)
+ */
+
+typedef struct {
+	volatile uint32_t CTRL;
+	const volatile uint32_t STS;
+	volatile uint32_t CNT;
+	volatile uint32_t DIV;
+	volatile uint32_t INTEN;
+} WDT_Type;
+
+/* CTRL */
+#define WDT_CTRL_EN         BIT(0)
+#define WDT_CTRL_RSTEN      BIT(1)
+#define WDT_CTRL_RELOAD     BIT(2)
+#define WDT_CTRL_CLRRSTFLAG BIT(3)
+/* STS */
+#define WDT_STS_RSTFLAG     BIT(0)
+/* INTEN */
+#define WDT_INTEN_WDTINTEN  BIT(0)
+
+#endif /* ZEPHYR_SOC_REALTEK_RTS5912_REG_WDT_H */
diff --git a/soc/realtek/ec/rts5912/rts5912_ulpm.c b/soc/realtek/ec/rts5912/rts5912_ulpm.c
new file mode 100644
index 00000000000..64ec787b7b3
--- /dev/null
+++ b/soc/realtek/ec/rts5912/rts5912_ulpm.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2025 Realtek Semiconductor Corporation, SIBG-SD7
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/devicetree.h>
+
+#include "rts5912_ulpm.h"
+#include "reg/reg_system.h"
+#include "reg/reg_gpio.h"
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(ulpm, CONFIG_SOC_LOG_LEVEL);
+
+#define DT_DRV_COMPAT realtek_rts5912_ulpm
+
+BUILD_ASSERT(DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) <= 1, "Unsupported number of instances");
+
+#define RTS5912_ULPM_NODE DT_DRV_INST(0)
+
+#define ULPM_RTS5912_MAX_NB_WKUP_PINS DT_INST_PROP(0, wkup_pins_max)
+
+/** @cond INTERNAL_HIDDEN */
+
+/**
+ * @brief flags for wake-up pin polarity configuration
+ * @{
+ */
+enum wkup_pin_mode {
+	RTS5912_ULPM_WKUP_PIN_MODE_VIN = 0,
+	RTS5912_ULPM_WKUP_PIN_MODE_GPIO = 1,
+};
+
+enum wkup_pin_pol {
+	/* detection of wake-up event on the high level : rising edge */
+	RTS5912_ULPM_WKUP_PIN_POL_RISING = 0,
+	/* detection of wake-up event on the low level : falling edge */
+	RTS5912_ULPM_WKUP_PIN_POL_FALLING = 1,
+};
+/** @} */
+
+/**
+ * @brief Structure for storing the devicetree configuration of a wake-up pin.
+ */
+struct wkup_pin_dt_cfg_t {
+	/* starts from 0 */
+	uint32_t wkup_pin_id;
+	/* wake up polarity */
+	enum wkup_pin_pol pin_pol;
+	/* wake up pin mode, VIN / GPIO */
+	enum wkup_pin_mode pin_mode;
+};
+
+/**
+ * @brief Get wake-up pin configuration from a given devicetree node.
+ *
+ * This returns a static initializer for a <tt>struct wkup_pin_dt_cfg_t</tt>
+ * filled with data from a given devicetree node.
+ *
+ * @param node_id Devicetree node identifier.
+ *
+ * @return Static initializer for a wkup_pin_dt_cfg_t structure.
+ */
+#define WKUP_PIN_CFG_DT(node_id)                                                                   \
+	{                                                                                          \
+		.wkup_pin_id = DT_REG_ADDR(node_id),                                               \
+		.pin_pol = (uint8_t)DT_ENUM_IDX(node_id, wkup_pin_pol),                            \
+		.pin_mode = (uint8_t)DT_ENUM_IDX(node_id, wkup_pin_mode),                          \
+	}
+
+/* wkup_pin idx starts from 0 */
+#define WKUP_PIN_CFG_DT_COMMA(wkup_pin_id) WKUP_PIN_CFG_DT(wkup_pin_id),
+
+/** @endcond */
+
+static struct wkup_pin_dt_cfg_t wkup_pins_cfgs[] = {
+	DT_INST_FOREACH_CHILD(0, WKUP_PIN_CFG_DT_COMMA)};
+
+#define WKUP_PIN_SIZE ARRAY_SIZE(wkup_pins_cfgs)
+/**
+ * @brief Enable VOUT function and set the VOUT default value.
+ */
+void ulpm_start(void)
+{
+	SYSTEM_Type *sys_reg = RTS5912_SCCON_REG_BASE;
+	/* enable VOUT */
+	sys_reg->VIVOCTRL &= ~(SYSTEM_VIVOCTRL_VOUTMD_Msk);
+	k_msleep(10);
+	/* Set the VOUT to low */
+	sys_reg->VIVOCTRL &= ~(SYSTEM_VIVOCTRL_VODEF_Msk);
+	k_msleep(10);
+	/* update to ULPM */
+	sys_reg->VIVOCTRL |= SYSTEM_VIVOCTRL_REGWREN_Msk;
+	k_msleep(10);
+}
+/**
+ * @brief Update register value to ULPM IP
+ */
+void update_vivo_register(void)
+{
+	SYSTEM_Type *sys_reg = RTS5912_SCCON_REG_BASE;
+	/* Update Register & reset bit */
+	k_msleep(10);
+	sys_reg->VIVOCTRL |= SYSTEM_VIVOCTRL_REGWREN_Msk;
+	k_msleep(10);
+	sys_reg->VIVOCTRL &= ~(SYSTEM_VIVOCTRL_REGWREN_Msk);
+	k_msleep(10);
+}
+
+/**
+ * @brief Configure & enable a wake-up pin.
+ *
+ * @param wakeup_pin_cfg wake-up pin runtime configuration.
+ *
+ */
+void rts5912_ulpm_enable(void)
+{
+	SYSTEM_Type *sys_reg = RTS5912_SCCON_REG_BASE;
+	int i, id;
+
+	LOG_INF("rts5912 ULPM enabled\n");
+	/* VoutEnable, Keep VOUT output default value as bit 16 */
+	sys_reg->VIVOCTRL |= SYSTEM_VIVOCTRL_VODEF_Msk;
+	k_msleep(10);
+
+	/* set to GPIO mode to clear status and aviod mis-trigger */
+	sys_reg->VIVOCTRL |= (SYSTEM_VIVOCTRL_VIN0MD_Msk | SYSTEM_VIVOCTRL_VIN1MD_Msk |
+			      SYSTEM_VIVOCTRL_VIN2MD_Msk | SYSTEM_VIVOCTRL_VIN3MD_Msk |
+			      SYSTEM_VIVOCTRL_VIN4MD_Msk | SYSTEM_VIVOCTRL_VIN5MD_Msk);
+
+	/* Update Status Bit to ULPM IP */
+	update_vivo_register();
+	/* Configure Mode (VIN/GPIO) and Edge (Falling/Rising) */
+	for (i = 0; i < WKUP_PIN_SIZE; i++) {
+		id = wkup_pins_cfgs[i].wkup_pin_id;
+		/* corner case test */
+		if ((id < 0) || (id >= ULPM_RTS5912_MAX_NB_WKUP_PINS)) {
+			continue;
+		}
+
+		/* Configure Mode */
+		if (wkup_pins_cfgs[i].pin_mode == RTS5912_ULPM_WKUP_PIN_MODE_VIN) {
+			LOG_DBG("setup VIN%d in ", id);
+			/* Configure Polarity */
+			if (wkup_pins_cfgs[i].pin_pol == RTS5912_ULPM_WKUP_PIN_POL_RISING) {
+				/* Falling Edge */
+				sys_reg->VIVOCTRL |= BIT(SYSTEM_VIVOCTRL_VIN0POL_Pos + id);
+				LOG_DBG("Falling Edge\n");
+			} else {
+				/* Rising Edge */
+				sys_reg->VIVOCTRL &= ~BIT(SYSTEM_VIVOCTRL_VIN0POL_Pos + id);
+				LOG_DBG("Rising Edge\n");
+			}
+			/* VIN Mode */
+			sys_reg->VIVOCTRL &= ~BIT(SYSTEM_VIVOCTRL_VIN0MD_Pos + id);
+		}
+	}
+
+	/* Update Status Bit to ULPM IP */
+	update_vivo_register();
+
+	/* Disable LDO 2 power. */
+	sys_reg->LDOCTRL &= ~(SYSTEM_LDOCTRL_LDO2EN_Msk);
+
+	/* ULPM Start */
+	ulpm_start();
+}
diff --git a/soc/realtek/ec/rts5912/rts5912_ulpm.h b/soc/realtek/ec/rts5912/rts5912_ulpm.h
new file mode 100644
index 00000000000..daabffb60ed
--- /dev/null
+++ b/soc/realtek/ec/rts5912/rts5912_ulpm.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025 Realtek Semiconductor Corporation, SIBG-SD7
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_REALTEK_RTS5912_ULPM_H_
+#define ZEPHYR_SOC_REALTEK_RTS5912_ULPM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void rts5912_ulpm_enable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_SOC_REALTEK_RTS5912_ULPM_H_ */
diff --git a/soc/realtek/ec/rts5912/soc.c b/soc/realtek/ec/rts5912/soc.c
index ce1e254e051..e08495e22a2 100644
--- a/soc/realtek/ec/rts5912/soc.c
+++ b/soc/realtek/ec/rts5912/soc.c
@@ -28,6 +28,10 @@ bool z_arm_on_enter_cpu_idle(void)
  */
 void soc_early_init_hook(void)
 {
+	if (!IS_ENABLED(CONFIG_RTS5912_DEBUG_SWJ)) {
+		return;
+	}
+
 	int ret;
 
 	/* Apply device related preinit configuration */
diff --git a/soc/renesas/ra/common_fsp/pinctrl_soc.h b/soc/renesas/ra/common_fsp/pinctrl_soc.h
index dc08dc3db10..ff345032f80 100644
--- a/soc/renesas/ra/common_fsp/pinctrl_soc.h
+++ b/soc/renesas/ra/common_fsp/pinctrl_soc.h
@@ -28,8 +28,6 @@ struct ra_pinctrl_soc_pin {
 
 typedef struct ra_pinctrl_soc_pin pinctrl_soc_pin_t;
 
-int ra_pinctrl_query_config(uint32_t port, uint32_t pin, pinctrl_soc_pin_t *pincfg);
-
 /**
  * @brief Utility macro to initialize each pin.
  *
diff --git a/soc/renesas/ra/ra2a1/Kconfig.defconfig b/soc/renesas/ra/ra2a1/Kconfig.defconfig
index 7176e95746a..e0ae0c6bd23 100644
--- a/soc/renesas/ra/ra2a1/Kconfig.defconfig
+++ b/soc/renesas/ra/ra2a1/Kconfig.defconfig
@@ -6,4 +6,15 @@ if SOC_SERIES_RA2A1
 config NUM_IRQS
 	default 32
 
+DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
 endif # SOC_SERIES_RA2A1
diff --git a/soc/renesas/ra/ra2a1/sections.ld b/soc/renesas/ra/ra2a1/sections.ld
index e3034adb244..9338be067c8 100644
--- a/soc/renesas/ra/ra2a1/sections.ld
+++ b/soc/renesas/ra/ra2a1/sections.ld
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(id_code), okay)
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(id_code))
 
 SECTION_PROLOGUE(.id_code,,)
 {
@@ -13,7 +13,7 @@ SECTION_PROLOGUE(.id_code,,)
 
 #endif
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ofs), okay)
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs))
 
 SECTION_PROLOGUE(.option_setting_ofs,,)
 {
@@ -28,7 +28,7 @@ SECTION_PROLOGUE(.option_setting_ofs,,)
 
 #endif
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_sas), okay)
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas))
 
 SECTION_PROLOGUE(.option_setting_sas,,)
 {
@@ -39,7 +39,7 @@ SECTION_PROLOGUE(.option_setting_sas,,)
 
 #endif
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ns), okay)
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ns))
 
 SECTION_PROLOGUE(.option_setting_ns,,)
 {
@@ -70,7 +70,7 @@ SECTION_PROLOGUE(.option_setting_ns,,)
 
 #endif
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_s), okay)
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s))
 
 SECTION_PROLOGUE(.option_setting_s,,)
 {
diff --git a/soc/renesas/ra/ra2a1/soc.c b/soc/renesas/ra/ra2a1/soc.c
index 76fc4803360..5585eba6a6d 100644
--- a/soc/renesas/ra/ra2a1/soc.c
+++ b/soc/renesas/ra/ra2a1/soc.c
@@ -25,6 +25,11 @@ uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
 
 volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
@@ -35,4 +40,12 @@ void soc_early_init_hook(void)
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
 	bsp_clock_init();
+
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif /* CONFIG_RUNTIME_NMI */
 }
diff --git a/soc/renesas/ra/ra2l1/CMakeLists.txt b/soc/renesas/ra/ra2l1/CMakeLists.txt
new file mode 100644
index 00000000000..240342ab88d
--- /dev/null
+++ b/soc/renesas/ra/ra2l1/CMakeLists.txt
@@ -0,0 +1,15 @@
+# Copyright (c) 2022-2024 MUNIC SA
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+  soc.c
+)
+
+zephyr_linker_sources(ROM_START opt_set_mem.ld)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/ra/ra2l1/Kconfig b/soc/renesas/ra/ra2l1/Kconfig
new file mode 100644
index 00000000000..e3a0ab7ceab
--- /dev/null
+++ b/soc/renesas/ra/ra2l1/Kconfig
@@ -0,0 +1,14 @@
+# Copyright (c) 2024 MUNIC SA
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA2L1
+	select ARM
+	select CPU_CORTEX_M23
+	select CPU_HAS_ARM_MPU
+	select HAS_RENESAS_RA_FSP
+	select CPU_CORTEX_M_HAS_VTOR
+	select CPU_CORTEX_M_HAS_SYSTICK
+	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
+	select HAS_SWO
+	select SOC_EARLY_INIT_HOOK
diff --git a/soc/renesas/ra/ra2l1/Kconfig.defconfig b/soc/renesas/ra/ra2l1/Kconfig.defconfig
new file mode 100644
index 00000000000..ccfd393a9f5
--- /dev/null
+++ b/soc/renesas/ra/ra2l1/Kconfig.defconfig
@@ -0,0 +1,20 @@
+# Copyright (c) 2024 MUNIC SA
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA2L1
+
+config NUM_IRQS
+	default 32
+
+DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
+endif # SOC_SERIES_RA2L1
diff --git a/soc/renesas/ra/ra2l1/Kconfig.soc b/soc/renesas/ra/ra2l1/Kconfig.soc
new file mode 100644
index 00000000000..5a4fdb1cfd7
--- /dev/null
+++ b/soc/renesas/ra/ra2l1/Kconfig.soc
@@ -0,0 +1,21 @@
+# Copyright (c) 2024 MUNIC SA
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA2L1
+	bool
+	select SOC_FAMILY_RENESAS_RA
+
+config SOC_R7FA2L1A9XXFP
+	bool
+	select SOC_SERIES_RA2L1
+
+config SOC_R7FA2L1ABXXFP
+	bool
+	select SOC_SERIES_RA2L1
+
+config SOC_SERIES
+	default "ra2l1" if SOC_SERIES_RA2L1
+
+config SOC
+	default "r7fa2l1a9xxfp" if SOC_R7FA2L1A9XXFP
+	default "r7fa2l1abxxfp" if SOC_R7FA2L1ABXXFP
diff --git a/soc/renesas/ra/ra2l1/opt_set_mem.ld b/soc/renesas/ra/ra2l1/opt_set_mem.ld
new file mode 100644
index 00000000000..07aef9e92d8
--- /dev/null
+++ b/soc/renesas/ra/ra2l1/opt_set_mem.ld
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* ROM Registers start at address 0x00000400 */
+. = 0x400;
+KEEP(*(.rom_registers*))
+/* Reserving 0x100 bytes of space for ROM registers. */
+. = 0x500;
diff --git a/soc/renesas/ra/ra2l1/sections.ld b/soc/renesas/ra/ra2l1/sections.ld
new file mode 100644
index 00000000000..5e7aad11ed7
--- /dev/null
+++ b/soc/renesas/ra/ra2l1/sections.ld
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+	/* If DTC is used, put the DTC vector table at the start of SRAM.
+	   This avoids memory holes due to 1K alignment required by it. */
+	*(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ofs), okay)
+
+SECTION_PROLOGUE(.option_setting_ofs,,)
+{
+	__OPTION_SETTING_OFS_Start = .;
+	KEEP(*(.option_setting_ofs0))
+	. = __OPTION_SETTING_OFS_Start + 0x04;
+	KEEP(*(.option_setting_ofs2))
+	. = __OPTION_SETTING_OFS_Start + 0x10;
+	KEEP(*(.option_setting_dualsel))
+	__OPTION_SETTING_OFS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
+
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_sas), okay)
+
+SECTION_PROLOGUE(.option_setting_sas,,)
+{
+	__OPTION_SETTING_SAS_Start = .;
+	KEEP(*(.option_setting_sas))
+	__OPTION_SETTING_SAS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
+
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ns), okay)
+
+SECTION_PROLOGUE(.option_setting_ns,,)
+{
+	__OPTION_SETTING_NS_Start = .;
+	KEEP(*(.option_setting_ofs1))
+        . = __OPTION_SETTING_NS_Start + 0x04;
+	KEEP(*(.option_setting_ofs3))
+        . = __OPTION_SETTING_NS_Start + 0x10;
+	KEEP(*(.option_setting_banksel))
+        . = __OPTION_SETTING_NS_Start + 0x40;
+	KEEP(*(.option_setting_bps0))
+        . = __OPTION_SETTING_NS_Start + 0x44;
+	KEEP(*(.option_setting_bps1))
+        . = __OPTION_SETTING_NS_Start + 0x48;
+	KEEP(*(.option_setting_bps2))
+        . = __OPTION_SETTING_NS_Start + 0x4C;
+	KEEP(*(.option_setting_bps3))
+        . = __OPTION_SETTING_NS_Start + 0x60;
+	KEEP(*(.option_setting_pbps0))
+        . = __OPTION_SETTING_NS_Start + 0x64;
+	KEEP(*(.option_setting_pbps1))
+        . = __OPTION_SETTING_NS_Start + 0x68;
+	KEEP(*(.option_setting_pbps2))
+        . = __OPTION_SETTING_NS_Start + 0x6C;
+	KEEP(*(.option_setting_pbps3))
+	__OPTION_SETTING_NS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING) = 0xFF
+
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_s), okay)
+
+SECTION_PROLOGUE(.option_setting_s,,)
+{
+	__OPTION_SETTING_S_Start = .;
+	KEEP(*(.option_setting_ofs1_sec))
+	. = __OPTION_SETTING_S_Start + 0x04;
+	KEEP(*(.option_setting_ofs3_sec))
+	. = __OPTION_SETTING_S_Start + 0x10;
+	KEEP(*(.option_setting_banksel_sec))
+	. = __OPTION_SETTING_S_Start + 0x40;
+	KEEP(*(.option_setting_bps_sec0))
+	. = __OPTION_SETTING_S_Start + 0x44;
+	KEEP(*(.option_setting_bps_sec1))
+	. = __OPTION_SETTING_S_Start + 0x48;
+	KEEP(*(.option_setting_bps_sec2))
+	. = __OPTION_SETTING_S_Start + 0x4C;
+	KEEP(*(.option_setting_bps_sec3))
+	. = __OPTION_SETTING_S_Start + 0x60;
+	KEEP(*(.option_setting_pbps_sec0))
+	. = __OPTION_SETTING_S_Start + 0x64;
+	KEEP(*(.option_setting_pbps_sec1))
+	. = __OPTION_SETTING_S_Start + 0x68;
+	KEEP(*(.option_setting_pbps_sec2))
+	. = __OPTION_SETTING_S_Start + 0x6C;
+	KEEP(*(.option_setting_pbps_sec3))
+	. = __OPTION_SETTING_S_Start + 0x80;
+	KEEP(*(.option_setting_ofs1_sel))
+	. = __OPTION_SETTING_S_Start + 0x84;
+	KEEP(*(.option_setting_ofs3_sel))
+	. = __OPTION_SETTING_S_Start + 0x90;
+	KEEP(*(.option_setting_banksel_sel))
+	. = __OPTION_SETTING_S_Start + 0xC0;
+	KEEP(*(.option_setting_bps_sel0))
+	. = __OPTION_SETTING_S_Start + 0xC4;
+	KEEP(*(.option_setting_bps_sel1))
+	. = __OPTION_SETTING_S_Start + 0xC8;
+	KEEP(*(.option_setting_bps_sel2))
+	. = __OPTION_SETTING_S_Start + 0xCC;
+	KEEP(*(.option_setting_bps_sel3))
+	__OPTION_SETTING_S_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
+
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(id_code), okay)
+
+SECTION_PROLOGUE(.id_code,,)
+{
+	KEEP(*(.id_code*))
+} GROUP_LINK_IN(ID_CODE)
+
+#endif
diff --git a/soc/renesas/ra/ra2l1/soc.c b/soc/renesas/ra/ra2l1/soc.c
new file mode 100644
index 00000000000..82a889c994a
--- /dev/null
+++ b/soc/renesas/ra/ra2l1/soc.c
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2023-2024 MUNIC SA
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA2L1 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/arch/arm/nmi.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include "bsp_cfg.h"
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ */
+void soc_early_init_hook(void)
+{
+	SystemCoreClock = BSP_MOCO_HZ;
+	g_protect_pfswe_counter = 0;
+
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif /* CONFIG_RUNTIME_NMI */
+}
diff --git a/soc/renesas/ra/ra2l1/soc.h b/soc/renesas/ra/ra2l1/soc.h
new file mode 100644
index 00000000000..2fa588a6c0c
--- /dev/null
+++ b/soc/renesas/ra/ra2l1/soc.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2021-2024 MUNIC SA
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA2L1 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA2L1_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA2L1_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA2L1_SOC_H_ */
diff --git a/soc/renesas/ra/ra4e1/CMakeLists.txt b/soc/renesas/ra/ra4e1/CMakeLists.txt
new file mode 100644
index 00000000000..e6758812e49
--- /dev/null
+++ b/soc/renesas/ra/ra4e1/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+  soc.c
+)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/ra/ra4e1/Kconfig b/soc/renesas/ra/ra4e1/Kconfig
new file mode 100644
index 00000000000..dd5a14ef2bf
--- /dev/null
+++ b/soc/renesas/ra/ra4e1/Kconfig
@@ -0,0 +1,17 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA4E1
+	select ARM
+	select CPU_HAS_ARM_MPU
+	select CPU_CORTEX_M33
+	select HAS_RENESAS_RA_FSP
+	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
+	select CPU_CORTEX_M_HAS_DWT
+	select ARMV8_M_DSP
+	select CPU_HAS_FPU
+	select FPU
+	select HAS_SWO
+	select XIP
+	select SOC_EARLY_INIT_HOOK
+	select GPIO_RA_HAS_VBTICTLR
diff --git a/soc/renesas/ra/ra4e1/Kconfig.defconfig b/soc/renesas/ra/ra4e1/Kconfig.defconfig
new file mode 100644
index 00000000000..7f12ebb7246
--- /dev/null
+++ b/soc/renesas/ra/ra4e1/Kconfig.defconfig
@@ -0,0 +1,24 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA4E1
+
+config NUM_IRQS
+	default 96
+
+DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
+# Set to the minimal size of data which can be written.
+config FLASH_FILL_BUFFER_SIZE
+	default 128
+
+endif # SOC_SERIES_RA4E1
diff --git a/soc/renesas/ra/ra4e1/Kconfig.soc b/soc/renesas/ra/ra4e1/Kconfig.soc
new file mode 100644
index 00000000000..01f75b23d29
--- /dev/null
+++ b/soc/renesas/ra/ra4e1/Kconfig.soc
@@ -0,0 +1,27 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA4E1
+	bool
+	select SOC_FAMILY_RENESAS_RA
+	help
+	  Renesas RA4E1 series
+
+config SOC_R7FA4E10D2CFM
+	bool
+	select SOC_SERIES_RA4E1
+	help
+	  R7FA4E10D2CFM
+
+config SOC_R7FA4E10D2CNE
+	bool
+	select SOC_SERIES_RA4E1
+	help
+	  R7FA4E10D2CNE
+
+config SOC_SERIES
+	default "ra4e1" if SOC_SERIES_RA4E1
+
+config SOC
+	default "r7fa4e10d2cfm" if SOC_R7FA4E10D2CFM
+	default "r7fa4e10d2cne" if SOC_R7FA4E10D2CNE
diff --git a/soc/renesas/ra/ra4e1/sections.ld b/soc/renesas/ra/ra4e1/sections.ld
new file mode 100644
index 00000000000..24f3f69d86c
--- /dev/null
+++ b/soc/renesas/ra/ra4e1/sections.ld
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+	/* If DTC is used, put the DTC vector table at the start of SRAM.
+		This avoids memory holes due to 1K alignment required by it. */
+	*(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs))
+
+SECTION_PROLOGUE(.option_setting_ofs,,)
+{
+	__OPTION_SETTING_OFS_Start = .;
+	KEEP(*(.option_setting_ofs0))
+	. = __OPTION_SETTING_OFS_Start + 0x04;
+	KEEP(*(.option_setting_ofs2))
+	. = __OPTION_SETTING_OFS_Start + 0x10;
+	KEEP(*(.option_setting_dualsel))
+	__OPTION_SETTING_OFS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
+
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas))
+
+SECTION_PROLOGUE(.option_setting_sas,,)
+{
+	__OPTION_SETTING_SAS_Start = .;
+	KEEP(*(.option_setting_sas))
+	__OPTION_SETTING_SAS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
+
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s))
+
+SECTION_PROLOGUE(.option_setting_s,,)
+{
+	__OPTION_SETTING_S_Start = .;
+	KEEP(*(.option_setting_ofs1_sec))
+	. = __OPTION_SETTING_S_Start + 0x04;
+	KEEP(*(.option_setting_ofs3_sec))
+	. = __OPTION_SETTING_S_Start + 0x10;
+	KEEP(*(.option_setting_banksel_sec))
+	. = __OPTION_SETTING_S_Start + 0x40;
+	KEEP(*(.option_setting_bps_sec0))
+	. = __OPTION_SETTING_S_Start + 0x44;
+	KEEP(*(.option_setting_bps_sec1))
+	. = __OPTION_SETTING_S_Start + 0x48;
+	KEEP(*(.option_setting_bps_sec2))
+	. = __OPTION_SETTING_S_Start + 0x4C;
+	KEEP(*(.option_setting_bps_sec3))
+	. = __OPTION_SETTING_S_Start + 0x60;
+	KEEP(*(.option_setting_pbps_sec0))
+	. = __OPTION_SETTING_S_Start + 0x64;
+	KEEP(*(.option_setting_pbps_sec1))
+	. = __OPTION_SETTING_S_Start + 0x68;
+	KEEP(*(.option_setting_pbps_sec2))
+	. = __OPTION_SETTING_S_Start + 0x6C;
+	KEEP(*(.option_setting_pbps_sec3))
+	. = __OPTION_SETTING_S_Start + 0x80;
+	KEEP(*(.option_setting_ofs1_sel))
+	. = __OPTION_SETTING_S_Start + 0x84;
+	KEEP(*(.option_setting_ofs3_sel))
+	. = __OPTION_SETTING_S_Start + 0x90;
+	KEEP(*(.option_setting_banksel_sel))
+	. = __OPTION_SETTING_S_Start + 0xC0;
+	KEEP(*(.option_setting_bps_sel0))
+	. = __OPTION_SETTING_S_Start + 0xC4;
+	KEEP(*(.option_setting_bps_sel1))
+	. = __OPTION_SETTING_S_Start + 0xC8;
+	KEEP(*(.option_setting_bps_sel2))
+	. = __OPTION_SETTING_S_Start + 0xCC;
+	KEEP(*(.option_setting_bps_sel3))
+	__OPTION_SETTING_S_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
+
+#endif
diff --git a/soc/renesas/ra/ra4e1/soc.c b/soc/renesas/ra/ra4e1/soc.c
new file mode 100644
index 00000000000..c243bb776b3
--- /dev/null
+++ b/soc/renesas/ra/ra4e1/soc.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA4E1 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/arch/arm/nmi.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include "bsp_cfg.h"
+#include <bsp_api.h>
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ */
+void soc_early_init_hook(void)
+{
+	extern volatile uint16_t g_protect_counters[];
+
+	for (uint32_t i = 0; i < 4; i++) {
+		g_protect_counters[i] = 0;
+	}
+
+#if FSP_PRIV_TZ_USE_SECURE_REGS
+	/* Disable protection using PRCR register. */
+	R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
+
+	/* Initialize peripherals to secure mode for flat projects */
+	R_PSCU->PSARB = 0;
+	R_PSCU->PSARC = 0;
+	R_PSCU->PSARD = 0;
+	R_PSCU->PSARE = 0;
+
+	R_CPSCU->ICUSARG = 0;
+	R_CPSCU->ICUSARH = 0;
+	R_CPSCU->ICUSARI = 0;
+
+	/* Enable protection using PRCR register. */
+	R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
+#endif
+
+	SystemCoreClock = BSP_MOCO_HZ;
+	g_protect_pfswe_counter = 0;
+
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif /* CONFIG_RUNTIME_NMI */
+}
diff --git a/soc/renesas/ra/ra4e1/soc.h b/soc/renesas/ra/ra4e1/soc.h
new file mode 100644
index 00000000000..704d430fecf
--- /dev/null
+++ b/soc/renesas/ra/ra4e1/soc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA4E1 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA4E1_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA4E1_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA4E1_SOC_H_ */
diff --git a/soc/renesas/ra/ra4e2/CMakeLists.txt b/soc/renesas/ra/ra4e2/CMakeLists.txt
index 1c7457569ef..2020d20561f 100644
--- a/soc/renesas/ra/ra4e2/CMakeLists.txt
+++ b/soc/renesas/ra/ra4e2/CMakeLists.txt
@@ -7,6 +7,16 @@ zephyr_sources(
   soc.c
 )
 
-zephyr_linker_sources(SECTIONS sections.ld)
+if(CONFIG_CMAKE_LINKER_GENERATOR)
+  zephyr_linker_section(NAME .fsp_dtc_vector_table GROUP RAM)
+  zephyr_linker_section(NAME .option_setting_ofs0 GROUP OPTION_SETTING_OFS ADDRESS 0x0100a100)
+  zephyr_linker_section(NAME .option_setting_sas GROUP OPTION_SETTING_SAS ADDRESS 0x0100a134)
+  zephyr_linker_section(NAME .option_setting_ofs1_sec GROUP OPTION_SETTING_S ADDRESS 0x0100a200)
+  zephyr_linker_section(NAME .option_setting_bps_sec0 GROUP OPTION_SETTING_S ADDRESS 0x0100a240)
+  zephyr_linker_section(NAME .option_setting_pbps_sec0 GROUP OPTION_SETTING_S ADDRESS 0x0100a260)
+  zephyr_linker_section(NAME .id_code GROUP ID_CODE)
+else()
+  zephyr_linker_sources_ifdef(CONFIG_LD_LINKER_TEMPLATE SECTIONS sections.ld)
+endif()
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/ra/ra4e2/Kconfig.defconfig b/soc/renesas/ra/ra4e2/Kconfig.defconfig
index f484852e0de..ff781e3becb 100644
--- a/soc/renesas/ra/ra4e2/Kconfig.defconfig
+++ b/soc/renesas/ra/ra4e2/Kconfig.defconfig
@@ -6,6 +6,17 @@ if SOC_SERIES_RA4E2
 config NUM_IRQS
 	default 96
 
+DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
 # Set to the minimal size of data which can be written.
 config FLASH_FILL_BUFFER_SIZE
 	default 128
diff --git a/soc/renesas/ra/ra4e2/sections.ld b/soc/renesas/ra/ra4e2/sections.ld
index 8999a6524ed..78c380e9fa1 100644
--- a/soc/renesas/ra/ra4e2/sections.ld
+++ b/soc/renesas/ra/ra4e2/sections.ld
@@ -11,6 +11,8 @@ SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
 	*(.fsp_dtc_vector_table)
 } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs))
+
 SECTION_PROLOGUE(.option_setting_ofs,,)
 {
 	__OPTION_SETTING_OFS_Start = .;
@@ -22,6 +24,10 @@ SECTION_PROLOGUE(.option_setting_ofs,,)
 	__OPTION_SETTING_OFS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas))
+
 SECTION_PROLOGUE(.option_setting_sas,,)
 {
 	__OPTION_SETTING_SAS_Start = .;
@@ -29,6 +35,10 @@ SECTION_PROLOGUE(.option_setting_sas,,)
 	__OPTION_SETTING_SAS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s))
+
 SECTION_PROLOGUE(.option_setting_s,,)
 {
 	__OPTION_SETTING_S_Start = .;
@@ -70,7 +80,13 @@ SECTION_PROLOGUE(.option_setting_s,,)
 	__OPTION_SETTING_S_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(id_code))
+
 SECTION_PROLOGUE(.id_code,,)
 {
     KEEP(*(.id_code*))
 } GROUP_LINK_IN(ID_CODE)
+
+#endif
diff --git a/soc/renesas/ra/ra4e2/soc.c b/soc/renesas/ra/ra4e2/soc.c
index 6d11bae8208..dbac92defa9 100644
--- a/soc/renesas/ra/ra4e2/soc.c
+++ b/soc/renesas/ra/ra4e2/soc.c
@@ -26,6 +26,11 @@ uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
 
 volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
@@ -59,4 +64,12 @@ void soc_early_init_hook(void)
 
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
+
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif /* CONFIG_RUNTIME_NMI */
 }
diff --git a/soc/renesas/ra/ra4l1/CMakeLists.txt b/soc/renesas/ra/ra4l1/CMakeLists.txt
new file mode 100644
index 00000000000..e6758812e49
--- /dev/null
+++ b/soc/renesas/ra/ra4l1/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(.)
+
+zephyr_sources(
+  soc.c
+)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/ra/ra4l1/Kconfig b/soc/renesas/ra/ra4l1/Kconfig
new file mode 100644
index 00000000000..314e037d34e
--- /dev/null
+++ b/soc/renesas/ra/ra4l1/Kconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA4L1
+	select ARM
+	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_MPU
+	select CPU_CORTEX_M_HAS_DWT
+	select CPU_HAS_FPU
+	select FPU
+	select ARMV8_M_DSP
+	select HAS_SWO
+	select HAS_RENESAS_RA_FSP
+	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
+	select XIP
+	select SOC_EARLY_INIT_HOOK
diff --git a/soc/renesas/ra/ra4l1/Kconfig.defconfig b/soc/renesas/ra/ra4l1/Kconfig.defconfig
new file mode 100644
index 00000000000..afa4ac00fd3
--- /dev/null
+++ b/soc/renesas/ra/ra4l1/Kconfig.defconfig
@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RA4L1
+
+config NUM_IRQS
+	default 64
+
+DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
+endif # SOC_SERIES_RA4L1
diff --git a/soc/renesas/ra/ra4l1/Kconfig.soc b/soc/renesas/ra/ra4l1/Kconfig.soc
new file mode 100644
index 00000000000..b7a8acf6714
--- /dev/null
+++ b/soc/renesas/ra/ra4l1/Kconfig.soc
@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RA4L1
+	bool
+	select SOC_FAMILY_RENESAS_RA
+	help
+	  Renesas RA4L1 series
+
+config SOC_R7FA4L1BD4CFP
+	bool
+	select SOC_SERIES_RA4L1
+	help
+	  R7FA4L1BD4CFP
+
+config SOC_SERIES
+	default "ra4l1" if SOC_SERIES_RA4L1
+
+config SOC
+	default "r7fa4l1bd4cfp" if SOC_R7FA4L1BD4CFP
diff --git a/soc/renesas/ra/ra4l1/sections.ld b/soc/renesas/ra/ra4l1/sections.ld
new file mode 100644
index 00000000000..d9eb2cd4a9a
--- /dev/null
+++ b/soc/renesas/ra/ra4l1/sections.ld
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
+{
+	/* If DTC is used, put the DTC vector table at the start of SRAM.
+		This avoids memory holes due to 1K alignment required by it. */
+	*(.fsp_dtc_vector_table)
+} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ofs), okay)
+SECTION_PROLOGUE(.option_setting_ofs,,)
+{
+	__OPTION_SETTING_OFS_Start = .;
+	KEEP(*(.option_setting_ofs0))
+	. = __OPTION_SETTING_OFS_Start + 0x04;
+	KEEP(*(.option_setting_ofs2))
+	. = __OPTION_SETTING_OFS_Start + 0x10;
+	KEEP(*(.option_setting_dualsel))
+	__OPTION_SETTING_OFS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_sas), okay)
+SECTION_PROLOGUE(.option_setting_sas,,)
+{
+	__OPTION_SETTING_SAS_Start = .;
+	KEEP(*(.option_setting_sas))
+	__OPTION_SETTING_SAS_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
+#endif
+
+#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_s), okay)
+SECTION_PROLOGUE(.option_setting_s,,)
+{
+	__OPTION_SETTING_S_Start = .;
+	KEEP(*(.option_setting_ofs1_sec))
+	. = __OPTION_SETTING_S_Start + 0x04;
+	KEEP(*(.option_setting_ofs3_sec))
+	. = __OPTION_SETTING_S_Start + 0x10;
+	KEEP(*(.option_setting_banksel_sec))
+	. = __OPTION_SETTING_S_Start + 0x40;
+	KEEP(*(.option_setting_bps_sec0))
+	. = __OPTION_SETTING_S_Start + 0x44;
+	KEEP(*(.option_setting_bps_sec1))
+	. = __OPTION_SETTING_S_Start + 0x48;
+	KEEP(*(.option_setting_bps_sec2))
+	. = __OPTION_SETTING_S_Start + 0x4C;
+	KEEP(*(.option_setting_bps_sec3))
+	. = __OPTION_SETTING_S_Start + 0x60;
+	KEEP(*(.option_setting_pbps_sec0))
+	. = __OPTION_SETTING_S_Start + 0x64;
+	KEEP(*(.option_setting_pbps_sec1))
+	. = __OPTION_SETTING_S_Start + 0x68;
+	KEEP(*(.option_setting_pbps_sec2))
+	. = __OPTION_SETTING_S_Start + 0x6C;
+	KEEP(*(.option_setting_pbps_sec3))
+	. = __OPTION_SETTING_S_Start + 0x80;
+	KEEP(*(.option_setting_ofs1_sel))
+	. = __OPTION_SETTING_S_Start + 0x84;
+	KEEP(*(.option_setting_ofs3_sel))
+	. = __OPTION_SETTING_S_Start + 0x90;
+	KEEP(*(.option_setting_banksel_sel))
+	. = __OPTION_SETTING_S_Start + 0xC0;
+	KEEP(*(.option_setting_bps_sel0))
+	. = __OPTION_SETTING_S_Start + 0xC4;
+	KEEP(*(.option_setting_bps_sel1))
+	. = __OPTION_SETTING_S_Start + 0xC8;
+	KEEP(*(.option_setting_bps_sel2))
+	. = __OPTION_SETTING_S_Start + 0xCC;
+	KEEP(*(.option_setting_bps_sel3))
+	__OPTION_SETTING_S_End = .;
+} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
+#endif
diff --git a/soc/renesas/ra/ra4l1/soc.c b/soc/renesas/ra/ra4l1/soc.c
new file mode 100644
index 00000000000..b756cdd319c
--- /dev/null
+++ b/soc/renesas/ra/ra4l1/soc.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RA4L1 family processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/arch/cpu.h>
+#include <cmsis_core.h>
+#include <zephyr/arch/arm/nmi.h>
+#include <zephyr/irq.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
+
+#include "bsp_cfg.h"
+#include "bsp_api.h"
+
+uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
+
+volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
+
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ */
+void soc_early_init_hook(void)
+{
+	extern volatile uint16_t g_protect_counters[];
+
+	for (uint32_t i = 0; i < 4; i++) {
+		g_protect_counters[i] = 0;
+	}
+
+#if FSP_PRIV_TZ_USE_SECURE_REGS
+	/* Disable protection using PRCR register. */
+	R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_SAR);
+
+	/* Initialize peripherals to secure mode for flat projects */
+	R_PSCU->PSARB = 0;
+	R_PSCU->PSARC = 0;
+	R_PSCU->PSARD = 0;
+	R_PSCU->PSARE = 0;
+
+	R_CPSCU->ICUSARG = 0;
+	R_CPSCU->ICUSARH = 0;
+	R_CPSCU->ICUSARI = 0;
+
+	/* Enable protection using PRCR register. */
+	R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
+#endif
+
+	SystemCoreClock = BSP_MOCO_HZ;
+	g_protect_pfswe_counter = 0;
+
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif /* CONFIG_RUNTIME_NMI */
+}
diff --git a/soc/renesas/ra/ra4l1/soc.h b/soc/renesas/ra/ra4l1/soc.h
new file mode 100644
index 00000000000..cf99273edd3
--- /dev/null
+++ b/soc/renesas/ra/ra4l1/soc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the Renesas RA4L1 family MCU
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RA4L1_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RA4L1_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RA4L1_SOC_H_ */
diff --git a/soc/renesas/ra/ra4m1/Kconfig b/soc/renesas/ra/ra4m1/Kconfig
index 798725677bb..f75e56ae206 100644
--- a/soc/renesas/ra/ra4m1/Kconfig
+++ b/soc/renesas/ra/ra4m1/Kconfig
@@ -13,7 +13,7 @@ config SOC_SERIES_RA4M1
 	select HAS_SWO
 	select XIP
 	select SOC_EARLY_INIT_HOOK
-	select DYNAMIC_INTERRUPTS
+	select GPIO_RA_HAS_VBTICTLR
 
 if SOC_SERIES_RA4M1
 
diff --git a/soc/renesas/ra/ra4m1/Kconfig.defconfig b/soc/renesas/ra/ra4m1/Kconfig.defconfig
index 5913bd7257f..38587b92ebc 100644
--- a/soc/renesas/ra/ra4m1/Kconfig.defconfig
+++ b/soc/renesas/ra/ra4m1/Kconfig.defconfig
@@ -6,4 +6,15 @@ if SOC_SERIES_RA4M1
 config NUM_IRQS
 	default 32
 
+DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
 endif # SOC_SERIES_RA4M1
diff --git a/soc/renesas/ra/ra4m1/Kconfig.soc b/soc/renesas/ra/ra4m1/Kconfig.soc
index cb3cbe60a8f..86c3a5d6399 100644
--- a/soc/renesas/ra/ra4m1/Kconfig.soc
+++ b/soc/renesas/ra/ra4m1/Kconfig.soc
@@ -13,8 +13,22 @@ config SOC_R7FA4M1AB3CFM
 	help
 	  R7FA4M1AB3CFM
 
+config SOC_R7FA4M1AB3CFP
+	bool
+	select SOC_SERIES_RA4M1
+	help
+	  R7FA4M1AB3CFP
+
+config SOC_R7FA4M1AB3CNE
+	bool
+	select SOC_SERIES_RA4M1
+	help
+	  R7FA4M1AB3CNE
+
 config SOC_SERIES
 	default "ra4m1" if SOC_SERIES_RA4M1
 
 config SOC
 	default "r7fa4m1ab3cfm" if SOC_R7FA4M1AB3CFM
+	default "r7fa4m1ab3cfp" if SOC_R7FA4M1AB3CFP
+	default "r7fa4m1ab3cne" if SOC_R7FA4M1AB3CNE
diff --git a/soc/renesas/ra/ra4m1/sections.ld b/soc/renesas/ra/ra4m1/sections.ld
index e3034adb244..9338be067c8 100644
--- a/soc/renesas/ra/ra4m1/sections.ld
+++ b/soc/renesas/ra/ra4m1/sections.ld
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(id_code), okay)
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(id_code))
 
 SECTION_PROLOGUE(.id_code,,)
 {
@@ -13,7 +13,7 @@ SECTION_PROLOGUE(.id_code,,)
 
 #endif
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ofs), okay)
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs))
 
 SECTION_PROLOGUE(.option_setting_ofs,,)
 {
@@ -28,7 +28,7 @@ SECTION_PROLOGUE(.option_setting_ofs,,)
 
 #endif
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_sas), okay)
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas))
 
 SECTION_PROLOGUE(.option_setting_sas,,)
 {
@@ -39,7 +39,7 @@ SECTION_PROLOGUE(.option_setting_sas,,)
 
 #endif
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ns), okay)
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ns))
 
 SECTION_PROLOGUE(.option_setting_ns,,)
 {
@@ -70,7 +70,7 @@ SECTION_PROLOGUE(.option_setting_ns,,)
 
 #endif
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_s), okay)
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s))
 
 SECTION_PROLOGUE(.option_setting_s,,)
 {
diff --git a/soc/renesas/ra/ra4m1/soc.c b/soc/renesas/ra/ra4m1/soc.c
index 06202352c51..dcdbda48726 100644
--- a/soc/renesas/ra/ra4m1/soc.c
+++ b/soc/renesas/ra/ra4m1/soc.c
@@ -26,13 +26,13 @@ LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
 #define HOCO_FREQ DT_PROP(DT_PATH(clocks, clock_hoco), clock_frequency)
 
 #if HOCO_FREQ == MHZ(24)
-#define OFS1_HOCO_FREQ		0
+#define OFS1_HOCO_FREQ 0
 #elif HOCO_FREQ == MHZ(32)
-#define OFS1_HOCO_FREQ		2
+#define OFS1_HOCO_FREQ 2
 #elif HOCO_FREQ == MHZ(48)
-#define OFS1_HOCO_FREQ		4
+#define OFS1_HOCO_FREQ 4
 #elif HOCO_FREQ == MHZ(64)
-#define OFS1_HOCO_FREQ		5
+#define OFS1_HOCO_FREQ 5
 #else
 #error "Unsupported HOCO frequency"
 #endif
@@ -93,38 +93,47 @@ struct opt_set_mem {
 };
 
 #ifdef CONFIG_SOC_OPTION_SETTING_MEMORY
-const struct opt_set_mem ops __attribute__((section(".rom_registers"))) = {
-	.ofs0 = {
-			/*
-			 * Initial settings for watchdog timers. Set all fields to 1,
-			 * disabling watchdog functionality as config options have not
-			 * yet been implemented.
-			 */
-			.RSVD1 = 0x1,       .IWDTSTRT = 0x1, /* Disable independent watchdog timer
-							      */
-			.IWDTTOPS = 0x3,    .IWDTCKS = 0xf,  .IWDTRPES = 0x3,   .IWDTRPSS = 0x3,
-			.IWDTRSTIRQS = 0x1, .RSVD2 = 0x1,    .IWDTSTPCTL = 0x1, .RSVD3 = 0x3,
-			.WDTSTRT = 0x1, /* Stop watchdog timer following reset */
-			.WDTTOPS = 0x3,     .WDTCKS = 0xf,   .WDTRPES = 0x3,    .WDTRPSS = 0x3,
-			.WDTRSTIRQS = 0x1,  .RSVD4 = 0x1,    .WDTSTPCTL = 0x1,  .RSVD5 = 0x1,
-		},
-	.ofs1 = {
-			.RSVD1 = 0x3,
-			.LVDAS = 0x1, /* Disable voltage monitor 0 following reset */
-			.VDSEL1 = 0x3,
-			.RSVD2 = 0x3,
-			.HOCOEN = !DT_NODE_HAS_STATUS(DT_PATH(clocks, clock_hoco), okay),
-			.RSVD3 = 0x7,
-			.HOCOFRQ1 = OFS1_HOCO_FREQ,
-			.RSVD4 = 0x1ffff,
-		},
-	.mpu = {
-		/*
-		 * Initial settings for MPU. Set all areas to maximum values
-		 * essentially disabling MPU functionality as config options
-		 * have not yet been implemented.
-		 */
-		.SECMPUPCSO = 0x00fffffc,
+Z_GENERIC_SECTION(".rom_registers")
+const struct opt_set_mem ops = {
+	/*
+	 * Initial settings for watchdog timers. Set all fields to 1,
+	 * disabling watchdog functionality as config options have not
+	 * yet been implemented.
+	 */
+	.ofs0 = {.RSVD1 = 0x1,
+		 .IWDTSTRT = 0x1, /* Disable independent watchdog timer */
+		 .IWDTTOPS = 0x3,
+		 .IWDTCKS = 0xf,
+		 .IWDTRPES = 0x3,
+		 .IWDTRPSS = 0x3,
+		 .IWDTRSTIRQS = 0x1,
+		 .RSVD2 = 0x1,
+		 .IWDTSTPCTL = 0x1,
+		 .RSVD3 = 0x3,
+		 /* Stop watchdog timer following reset */
+		 .WDTSTRT = !IS_ENABLED(CONFIG_WDT_RENESAS_RA_START_IN_BOOT),
+		 .WDTTOPS = 0x3,
+		 .WDTCKS = 0xf,
+		 .WDTRPES = 0x3,
+		 .WDTRPSS = 0x3,
+		 .WDTRSTIRQS = 0x1,
+		 .RSVD4 = 0x1,
+		 .WDTSTPCTL = 0x1,
+		 .RSVD5 = 0x1},
+	.ofs1 = {.RSVD1 = 0x3,
+		 .LVDAS = 0x1, /* Disable voltage monitor 0 following reset */
+		 .VDSEL1 = 0x3,
+		 .RSVD2 = 0x3,
+		 .HOCOEN = !DT_NODE_HAS_STATUS(DT_PATH(clocks, clock_hoco), okay),
+		 .RSVD3 = 0x7,
+		 .HOCOFRQ1 = OFS1_HOCO_FREQ,
+		 .RSVD4 = 0x1ffff},
+	/*
+	 * Initial settings for MPU. Set all areas to maximum values
+	 * essentially disabling MPU functionality as config options
+	 * have not yet been implemented.
+	 */
+	.mpu = {.SECMPUPCSO = 0x00fffffc,
 		.SECMPUPCEO = 0x00ffffff,
 		.SECMPUPCS1 = 0x00fffffc,
 		.SECMPUPCE1 = 0x00ffffff,
@@ -136,14 +145,18 @@ const struct opt_set_mem ops __attribute__((section(".rom_registers"))) = {
 		.SECMPUE2 = 0x407fffff,
 		.SECMPUS3 = 0x40dffffc,
 		.SECMPUE3 = 0x40dfffff,
-		.SECMPUAC = 0xffffffff,
-	}};
+		.SECMPUAC = 0xffffffff}};
 #endif
 
 uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
 
 volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
@@ -158,5 +171,13 @@ void soc_early_init_hook(void)
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
 
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif /* CONFIG_RUNTIME_NMI */
+
 	irq_unlock(key);
 }
diff --git a/soc/renesas/ra/ra4m2/Kconfig b/soc/renesas/ra/ra4m2/Kconfig
index a4b6d2c7c50..5058fde9616 100644
--- a/soc/renesas/ra/ra4m2/Kconfig
+++ b/soc/renesas/ra/ra4m2/Kconfig
@@ -14,3 +14,4 @@ config SOC_SERIES_RA4M2
 	select HAS_SWO
 	select XIP
 	select SOC_EARLY_INIT_HOOK
+	select GPIO_RA_HAS_VBTICTLR
diff --git a/soc/renesas/ra/ra4m2/Kconfig.defconfig b/soc/renesas/ra/ra4m2/Kconfig.defconfig
index 3c6f986e5ff..87ce2fc6817 100644
--- a/soc/renesas/ra/ra4m2/Kconfig.defconfig
+++ b/soc/renesas/ra/ra4m2/Kconfig.defconfig
@@ -6,6 +6,17 @@ if SOC_SERIES_RA4M2
 config NUM_IRQS
 	default 96
 
+DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
 # Set to the minimal size of data which can be written.
 config FLASH_FILL_BUFFER_SIZE
 	default 128
diff --git a/soc/renesas/ra/ra4m2/sections.ld b/soc/renesas/ra/ra4m2/sections.ld
index 1fe7db907a3..7859d28dea5 100644
--- a/soc/renesas/ra/ra4m2/sections.ld
+++ b/soc/renesas/ra/ra4m2/sections.ld
@@ -11,6 +11,8 @@ SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
 	*(.fsp_dtc_vector_table)
 } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs))
+
 SECTION_PROLOGUE(.option_setting_ofs,,)
 {
 	__OPTION_SETTING_OFS_Start = .;
@@ -22,6 +24,10 @@ SECTION_PROLOGUE(.option_setting_ofs,,)
 	__OPTION_SETTING_OFS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas))
+
 SECTION_PROLOGUE(.option_setting_sas,,)
 {
 	__OPTION_SETTING_SAS_Start = .;
@@ -29,6 +35,10 @@ SECTION_PROLOGUE(.option_setting_sas,,)
 	__OPTION_SETTING_SAS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s))
+
 SECTION_PROLOGUE(.option_setting_s,,)
 {
 	__OPTION_SETTING_S_Start = .;
@@ -69,3 +79,5 @@ SECTION_PROLOGUE(.option_setting_s,,)
 	KEEP(*(.option_setting_bps_sel3))
 	__OPTION_SETTING_S_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
+
+#endif
diff --git a/soc/renesas/ra/ra4m2/soc.c b/soc/renesas/ra/ra4m2/soc.c
index c3c21184aa4..7c95131bebe 100644
--- a/soc/renesas/ra/ra4m2/soc.c
+++ b/soc/renesas/ra/ra4m2/soc.c
@@ -26,6 +26,11 @@ uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
 
 volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
@@ -59,4 +64,12 @@ void soc_early_init_hook(void)
 
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
+
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif /* CONFIG_RUNTIME_NMI */
 }
diff --git a/soc/renesas/ra/ra4m3/Kconfig b/soc/renesas/ra/ra4m3/Kconfig
index 0898c3796bc..dfa37190686 100644
--- a/soc/renesas/ra/ra4m3/Kconfig
+++ b/soc/renesas/ra/ra4m3/Kconfig
@@ -14,3 +14,4 @@ config SOC_SERIES_RA4M3
 	select HAS_SWO
 	select XIP
 	select SOC_EARLY_INIT_HOOK
+	select GPIO_RA_HAS_VBTICTLR
diff --git a/soc/renesas/ra/ra4m3/Kconfig.defconfig b/soc/renesas/ra/ra4m3/Kconfig.defconfig
index 717b6bce432..af4c164af81 100644
--- a/soc/renesas/ra/ra4m3/Kconfig.defconfig
+++ b/soc/renesas/ra/ra4m3/Kconfig.defconfig
@@ -6,6 +6,17 @@ if SOC_SERIES_RA4M3
 config NUM_IRQS
 	default 96
 
+DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
 # Set to the minimal size of data which can be written.
 config FLASH_FILL_BUFFER_SIZE
 	default 128
diff --git a/soc/renesas/ra/ra4m3/sections.ld b/soc/renesas/ra/ra4m3/sections.ld
index 1fe7db907a3..7859d28dea5 100644
--- a/soc/renesas/ra/ra4m3/sections.ld
+++ b/soc/renesas/ra/ra4m3/sections.ld
@@ -11,6 +11,8 @@ SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
 	*(.fsp_dtc_vector_table)
 } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs))
+
 SECTION_PROLOGUE(.option_setting_ofs,,)
 {
 	__OPTION_SETTING_OFS_Start = .;
@@ -22,6 +24,10 @@ SECTION_PROLOGUE(.option_setting_ofs,,)
 	__OPTION_SETTING_OFS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas))
+
 SECTION_PROLOGUE(.option_setting_sas,,)
 {
 	__OPTION_SETTING_SAS_Start = .;
@@ -29,6 +35,10 @@ SECTION_PROLOGUE(.option_setting_sas,,)
 	__OPTION_SETTING_SAS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s))
+
 SECTION_PROLOGUE(.option_setting_s,,)
 {
 	__OPTION_SETTING_S_Start = .;
@@ -69,3 +79,5 @@ SECTION_PROLOGUE(.option_setting_s,,)
 	KEEP(*(.option_setting_bps_sel3))
 	__OPTION_SETTING_S_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
+
+#endif
diff --git a/soc/renesas/ra/ra4m3/soc.c b/soc/renesas/ra/ra4m3/soc.c
index 10658184372..d751f7e6829 100644
--- a/soc/renesas/ra/ra4m3/soc.c
+++ b/soc/renesas/ra/ra4m3/soc.c
@@ -26,6 +26,11 @@ uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
 
 volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
@@ -59,4 +64,12 @@ void soc_early_init_hook(void)
 
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
+
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif /* CONFIG_RUNTIME_NMI */
 }
diff --git a/soc/renesas/ra/ra4w1/Kconfig b/soc/renesas/ra/ra4w1/Kconfig
index c9d1fbb3703..34f44bf6d07 100644
--- a/soc/renesas/ra/ra4w1/Kconfig
+++ b/soc/renesas/ra/ra4w1/Kconfig
@@ -13,3 +13,4 @@ config SOC_SERIES_RA4W1
 	select HAS_SWO
 	select XIP
 	select SOC_EARLY_INIT_HOOK
+	select GPIO_RA_HAS_VBTICTLR
diff --git a/soc/renesas/ra/ra4w1/Kconfig.defconfig b/soc/renesas/ra/ra4w1/Kconfig.defconfig
index 56c1866d0e9..3e3cbb9747c 100644
--- a/soc/renesas/ra/ra4w1/Kconfig.defconfig
+++ b/soc/renesas/ra/ra4w1/Kconfig.defconfig
@@ -6,4 +6,15 @@ if SOC_SERIES_RA4W1
 config NUM_IRQS
 	default 32
 
+DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
 endif # SOC_SERIES_RA4W1
diff --git a/soc/renesas/ra/ra4w1/sections.ld b/soc/renesas/ra/ra4w1/sections.ld
index b850a64f643..f86dac778f7 100644
--- a/soc/renesas/ra/ra4w1/sections.ld
+++ b/soc/renesas/ra/ra4w1/sections.ld
@@ -19,7 +19,11 @@ SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
 	*(.fsp_dtc_vector_table)
 } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(id_code))
+
 SECTION_PROLOGUE(.id_code,,)
 {
     KEEP(*(.id_code*))
 } GROUP_LINK_IN(ID_CODE)
+
+#endif
diff --git a/soc/renesas/ra/ra4w1/soc.c b/soc/renesas/ra/ra4w1/soc.c
index 6d84c068f7d..c62592e320c 100644
--- a/soc/renesas/ra/ra4w1/soc.c
+++ b/soc/renesas/ra/ra4w1/soc.c
@@ -26,6 +26,11 @@ uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
 
 volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
@@ -35,4 +40,12 @@ void soc_early_init_hook(void)
 {
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
+
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif /* CONFIG_RUNTIME_NMI */
 }
diff --git a/soc/renesas/ra/ra6e1/Kconfig b/soc/renesas/ra/ra6e1/Kconfig
index accd57e26a0..097baa62414 100644
--- a/soc/renesas/ra/ra6e1/Kconfig
+++ b/soc/renesas/ra/ra6e1/Kconfig
@@ -14,3 +14,4 @@ config SOC_SERIES_RA6E1
 	select HAS_SWO
 	select XIP
 	select SOC_EARLY_INIT_HOOK
+	select GPIO_RA_HAS_VBTICTLR
diff --git a/soc/renesas/ra/ra6e1/Kconfig.defconfig b/soc/renesas/ra/ra6e1/Kconfig.defconfig
index 5920c21c759..d8478071e7a 100644
--- a/soc/renesas/ra/ra6e1/Kconfig.defconfig
+++ b/soc/renesas/ra/ra6e1/Kconfig.defconfig
@@ -6,6 +6,17 @@ if SOC_SERIES_RA6E1
 config NUM_IRQS
 	default 96
 
+DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
 # Set to the minimal size of data which can be written.
 config FLASH_FILL_BUFFER_SIZE
 	default 128
diff --git a/soc/renesas/ra/ra6e1/sections.ld b/soc/renesas/ra/ra6e1/sections.ld
index 1fe7db907a3..7859d28dea5 100644
--- a/soc/renesas/ra/ra6e1/sections.ld
+++ b/soc/renesas/ra/ra6e1/sections.ld
@@ -11,6 +11,8 @@ SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
 	*(.fsp_dtc_vector_table)
 } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs))
+
 SECTION_PROLOGUE(.option_setting_ofs,,)
 {
 	__OPTION_SETTING_OFS_Start = .;
@@ -22,6 +24,10 @@ SECTION_PROLOGUE(.option_setting_ofs,,)
 	__OPTION_SETTING_OFS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas))
+
 SECTION_PROLOGUE(.option_setting_sas,,)
 {
 	__OPTION_SETTING_SAS_Start = .;
@@ -29,6 +35,10 @@ SECTION_PROLOGUE(.option_setting_sas,,)
 	__OPTION_SETTING_SAS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s))
+
 SECTION_PROLOGUE(.option_setting_s,,)
 {
 	__OPTION_SETTING_S_Start = .;
@@ -69,3 +79,5 @@ SECTION_PROLOGUE(.option_setting_s,,)
 	KEEP(*(.option_setting_bps_sel3))
 	__OPTION_SETTING_S_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
+
+#endif
diff --git a/soc/renesas/ra/ra6e1/soc.c b/soc/renesas/ra/ra6e1/soc.c
index ca37db8e274..7b4331e6926 100644
--- a/soc/renesas/ra/ra6e1/soc.c
+++ b/soc/renesas/ra/ra6e1/soc.c
@@ -25,6 +25,11 @@ uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
 
 volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
@@ -63,5 +68,13 @@ void soc_early_init_hook(void)
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
 
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif /* CONFIG_RUNTIME_NMI */
+
 	irq_unlock(key);
 }
diff --git a/soc/renesas/ra/ra6e2/Kconfig.defconfig b/soc/renesas/ra/ra6e2/Kconfig.defconfig
index d19b73b87a0..9d56855abe1 100644
--- a/soc/renesas/ra/ra6e2/Kconfig.defconfig
+++ b/soc/renesas/ra/ra6e2/Kconfig.defconfig
@@ -6,6 +6,17 @@ if SOC_SERIES_RA6E2
 config NUM_IRQS
 	default 96
 
+DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
 # Set to the minimal size of data which can be written.
 config FLASH_FILL_BUFFER_SIZE
 	default 128
diff --git a/soc/renesas/ra/ra6e2/sections.ld b/soc/renesas/ra/ra6e2/sections.ld
index 8999a6524ed..78c380e9fa1 100644
--- a/soc/renesas/ra/ra6e2/sections.ld
+++ b/soc/renesas/ra/ra6e2/sections.ld
@@ -11,6 +11,8 @@ SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
 	*(.fsp_dtc_vector_table)
 } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs))
+
 SECTION_PROLOGUE(.option_setting_ofs,,)
 {
 	__OPTION_SETTING_OFS_Start = .;
@@ -22,6 +24,10 @@ SECTION_PROLOGUE(.option_setting_ofs,,)
 	__OPTION_SETTING_OFS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas))
+
 SECTION_PROLOGUE(.option_setting_sas,,)
 {
 	__OPTION_SETTING_SAS_Start = .;
@@ -29,6 +35,10 @@ SECTION_PROLOGUE(.option_setting_sas,,)
 	__OPTION_SETTING_SAS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s))
+
 SECTION_PROLOGUE(.option_setting_s,,)
 {
 	__OPTION_SETTING_S_Start = .;
@@ -70,7 +80,13 @@ SECTION_PROLOGUE(.option_setting_s,,)
 	__OPTION_SETTING_S_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(id_code))
+
 SECTION_PROLOGUE(.id_code,,)
 {
     KEEP(*(.id_code*))
 } GROUP_LINK_IN(ID_CODE)
+
+#endif
diff --git a/soc/renesas/ra/ra6e2/soc.c b/soc/renesas/ra/ra6e2/soc.c
index 2b34260479e..0a929d7b300 100644
--- a/soc/renesas/ra/ra6e2/soc.c
+++ b/soc/renesas/ra/ra6e2/soc.c
@@ -25,6 +25,11 @@ uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
 
 volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
@@ -63,5 +68,13 @@ void soc_early_init_hook(void)
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
 
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif /* CONFIG_RUNTIME_NMI */
+
 	irq_unlock(key);
 }
diff --git a/soc/renesas/ra/ra6m1/Kconfig b/soc/renesas/ra/ra6m1/Kconfig
index 649b6702629..ffe57311717 100644
--- a/soc/renesas/ra/ra6m1/Kconfig
+++ b/soc/renesas/ra/ra6m1/Kconfig
@@ -13,3 +13,4 @@ config SOC_SERIES_RA6M1
 	select HAS_SWO
 	select XIP
 	select SOC_EARLY_INIT_HOOK
+	select GPIO_RA_HAS_VBTICTLR
diff --git a/soc/renesas/ra/ra6m1/Kconfig.defconfig b/soc/renesas/ra/ra6m1/Kconfig.defconfig
index 520d9aac59e..f863f67d6f2 100644
--- a/soc/renesas/ra/ra6m1/Kconfig.defconfig
+++ b/soc/renesas/ra/ra6m1/Kconfig.defconfig
@@ -6,6 +6,17 @@ if SOC_SERIES_RA6M1
 config NUM_IRQS
 	default 96
 
+DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
 # Set to the minimal size of data which can be written.
 config FLASH_FILL_BUFFER_SIZE
 	default 128
diff --git a/soc/renesas/ra/ra6m1/sections.ld b/soc/renesas/ra/ra6m1/sections.ld
index 8d31894fc38..fb5ec4d7e24 100644
--- a/soc/renesas/ra/ra6m1/sections.ld
+++ b/soc/renesas/ra/ra6m1/sections.ld
@@ -11,7 +11,11 @@ SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
 	*(.fsp_dtc_vector_table)
 } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(id_code))
+
 SECTION_PROLOGUE(.id_code,,)
 {
     KEEP(*(.id_code*))
 } GROUP_LINK_IN(ID_CODE)
+
+#endif
diff --git a/soc/renesas/ra/ra6m1/soc.c b/soc/renesas/ra/ra6m1/soc.c
index c9809254ae2..1986da3ec8c 100644
--- a/soc/renesas/ra/ra6m1/soc.c
+++ b/soc/renesas/ra/ra6m1/soc.c
@@ -25,6 +25,11 @@ uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
 
 volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
@@ -39,5 +44,13 @@ void soc_early_init_hook(void)
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
 
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif /* CONFIG_RUNTIME_NMI */
+
 	irq_unlock(key);
 }
diff --git a/soc/renesas/ra/ra6m2/Kconfig b/soc/renesas/ra/ra6m2/Kconfig
index 680e649349d..09c6427a52e 100644
--- a/soc/renesas/ra/ra6m2/Kconfig
+++ b/soc/renesas/ra/ra6m2/Kconfig
@@ -13,3 +13,4 @@ config SOC_SERIES_RA6M2
 	select HAS_SWO
 	select XIP
 	select SOC_EARLY_INIT_HOOK
+	select GPIO_RA_HAS_VBTICTLR
diff --git a/soc/renesas/ra/ra6m2/Kconfig.defconfig b/soc/renesas/ra/ra6m2/Kconfig.defconfig
index ca2dc7346d4..7e5cd7a2eec 100644
--- a/soc/renesas/ra/ra6m2/Kconfig.defconfig
+++ b/soc/renesas/ra/ra6m2/Kconfig.defconfig
@@ -6,6 +6,17 @@ if SOC_SERIES_RA6M2
 config NUM_IRQS
 	default 96
 
+DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
 # Set to the minimal size of data which can be written.
 config FLASH_FILL_BUFFER_SIZE
 	default 128
diff --git a/soc/renesas/ra/ra6m2/sections.ld b/soc/renesas/ra/ra6m2/sections.ld
index 8d31894fc38..fb5ec4d7e24 100644
--- a/soc/renesas/ra/ra6m2/sections.ld
+++ b/soc/renesas/ra/ra6m2/sections.ld
@@ -11,7 +11,11 @@ SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
 	*(.fsp_dtc_vector_table)
 } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(id_code))
+
 SECTION_PROLOGUE(.id_code,,)
 {
     KEEP(*(.id_code*))
 } GROUP_LINK_IN(ID_CODE)
+
+#endif
diff --git a/soc/renesas/ra/ra6m2/soc.c b/soc/renesas/ra/ra6m2/soc.c
index f0d399463f5..90d7cd7fad1 100644
--- a/soc/renesas/ra/ra6m2/soc.c
+++ b/soc/renesas/ra/ra6m2/soc.c
@@ -25,6 +25,11 @@ uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
 
 volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
@@ -39,5 +44,13 @@ void soc_early_init_hook(void)
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
 
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif /* CONFIG_RUNTIME_NMI */
+
 	irq_unlock(key);
 }
diff --git a/soc/renesas/ra/ra6m3/Kconfig b/soc/renesas/ra/ra6m3/Kconfig
index bebd78f1bab..3dea36935ae 100644
--- a/soc/renesas/ra/ra6m3/Kconfig
+++ b/soc/renesas/ra/ra6m3/Kconfig
@@ -13,3 +13,4 @@ config SOC_SERIES_RA6M3
 	select HAS_SWO
 	select XIP
 	select SOC_EARLY_INIT_HOOK
+	select GPIO_RA_HAS_VBTICTLR
diff --git a/soc/renesas/ra/ra6m3/Kconfig.defconfig b/soc/renesas/ra/ra6m3/Kconfig.defconfig
index 43f112acb60..ae8951e40c5 100644
--- a/soc/renesas/ra/ra6m3/Kconfig.defconfig
+++ b/soc/renesas/ra/ra6m3/Kconfig.defconfig
@@ -6,6 +6,17 @@ if SOC_SERIES_RA6M3
 config NUM_IRQS
 	default 96
 
+DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
 # Set to the minimal size of data which can be written.
 config FLASH_FILL_BUFFER_SIZE
 	default 128
diff --git a/soc/renesas/ra/ra6m3/sections.ld b/soc/renesas/ra/ra6m3/sections.ld
index 8d31894fc38..fb5ec4d7e24 100644
--- a/soc/renesas/ra/ra6m3/sections.ld
+++ b/soc/renesas/ra/ra6m3/sections.ld
@@ -11,7 +11,11 @@ SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
 	*(.fsp_dtc_vector_table)
 } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(id_code))
+
 SECTION_PROLOGUE(.id_code,,)
 {
     KEEP(*(.id_code*))
 } GROUP_LINK_IN(ID_CODE)
+
+#endif
diff --git a/soc/renesas/ra/ra6m3/soc.c b/soc/renesas/ra/ra6m3/soc.c
index 99f9a60e6eb..9c520b99e3a 100644
--- a/soc/renesas/ra/ra6m3/soc.c
+++ b/soc/renesas/ra/ra6m3/soc.c
@@ -25,6 +25,11 @@ uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
 
 volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
@@ -39,5 +44,13 @@ void soc_early_init_hook(void)
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
 
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif
+
 	irq_unlock(key);
 }
diff --git a/soc/renesas/ra/ra6m4/Kconfig b/soc/renesas/ra/ra6m4/Kconfig
index ee2acc2855f..dec6aba2581 100644
--- a/soc/renesas/ra/ra6m4/Kconfig
+++ b/soc/renesas/ra/ra6m4/Kconfig
@@ -14,3 +14,4 @@ config SOC_SERIES_RA6M4
 	select HAS_SWO
 	select XIP
 	select SOC_EARLY_INIT_HOOK
+	select GPIO_RA_HAS_VBTICTLR
diff --git a/soc/renesas/ra/ra6m4/Kconfig.defconfig b/soc/renesas/ra/ra6m4/Kconfig.defconfig
index 5352885ee93..7e6de81829e 100644
--- a/soc/renesas/ra/ra6m4/Kconfig.defconfig
+++ b/soc/renesas/ra/ra6m4/Kconfig.defconfig
@@ -6,6 +6,17 @@ if SOC_SERIES_RA6M4
 config NUM_IRQS
 	default 96
 
+DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
 # Set to the minimal size of data which can be written.
 config FLASH_FILL_BUFFER_SIZE
 	default 128
diff --git a/soc/renesas/ra/ra6m4/sections.ld b/soc/renesas/ra/ra6m4/sections.ld
index 1fe7db907a3..7859d28dea5 100644
--- a/soc/renesas/ra/ra6m4/sections.ld
+++ b/soc/renesas/ra/ra6m4/sections.ld
@@ -11,6 +11,8 @@ SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
 	*(.fsp_dtc_vector_table)
 } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs))
+
 SECTION_PROLOGUE(.option_setting_ofs,,)
 {
 	__OPTION_SETTING_OFS_Start = .;
@@ -22,6 +24,10 @@ SECTION_PROLOGUE(.option_setting_ofs,,)
 	__OPTION_SETTING_OFS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas))
+
 SECTION_PROLOGUE(.option_setting_sas,,)
 {
 	__OPTION_SETTING_SAS_Start = .;
@@ -29,6 +35,10 @@ SECTION_PROLOGUE(.option_setting_sas,,)
 	__OPTION_SETTING_SAS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s))
+
 SECTION_PROLOGUE(.option_setting_s,,)
 {
 	__OPTION_SETTING_S_Start = .;
@@ -69,3 +79,5 @@ SECTION_PROLOGUE(.option_setting_s,,)
 	KEEP(*(.option_setting_bps_sel3))
 	__OPTION_SETTING_S_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
+
+#endif
diff --git a/soc/renesas/ra/ra6m4/soc.c b/soc/renesas/ra/ra6m4/soc.c
index f561d631b67..c93933f4fb8 100644
--- a/soc/renesas/ra/ra6m4/soc.c
+++ b/soc/renesas/ra/ra6m4/soc.c
@@ -25,6 +25,11 @@ uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
 
 volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
@@ -63,5 +68,13 @@ void soc_early_init_hook(void)
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
 
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif
+
 	irq_unlock(key);
 }
diff --git a/soc/renesas/ra/ra6m5/Kconfig b/soc/renesas/ra/ra6m5/Kconfig
index 4a8f750eab6..792239394c7 100644
--- a/soc/renesas/ra/ra6m5/Kconfig
+++ b/soc/renesas/ra/ra6m5/Kconfig
@@ -14,3 +14,4 @@ config SOC_SERIES_RA6M5
 	select HAS_SWO
 	select XIP
 	select SOC_EARLY_INIT_HOOK
+	select GPIO_RA_HAS_VBTICTLR
diff --git a/soc/renesas/ra/ra6m5/Kconfig.defconfig b/soc/renesas/ra/ra6m5/Kconfig.defconfig
index 3e473cd8932..51c5a3c0de2 100644
--- a/soc/renesas/ra/ra6m5/Kconfig.defconfig
+++ b/soc/renesas/ra/ra6m5/Kconfig.defconfig
@@ -6,6 +6,17 @@ if SOC_SERIES_RA6M5
 config NUM_IRQS
 	default 96
 
+DT_ICLK_PATH := $(dt_nodelabel_path,iclk)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency)
+
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
 # Set to the minimal size of data which can be written.
 config FLASH_FILL_BUFFER_SIZE
 	default 128
diff --git a/soc/renesas/ra/ra6m5/sections.ld b/soc/renesas/ra/ra6m5/sections.ld
index 1fe7db907a3..7859d28dea5 100644
--- a/soc/renesas/ra/ra6m5/sections.ld
+++ b/soc/renesas/ra/ra6m5/sections.ld
@@ -11,6 +11,8 @@ SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
 	*(.fsp_dtc_vector_table)
 } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs))
+
 SECTION_PROLOGUE(.option_setting_ofs,,)
 {
 	__OPTION_SETTING_OFS_Start = .;
@@ -22,6 +24,10 @@ SECTION_PROLOGUE(.option_setting_ofs,,)
 	__OPTION_SETTING_OFS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas))
+
 SECTION_PROLOGUE(.option_setting_sas,,)
 {
 	__OPTION_SETTING_SAS_Start = .;
@@ -29,6 +35,10 @@ SECTION_PROLOGUE(.option_setting_sas,,)
 	__OPTION_SETTING_SAS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s))
+
 SECTION_PROLOGUE(.option_setting_s,,)
 {
 	__OPTION_SETTING_S_Start = .;
@@ -69,3 +79,5 @@ SECTION_PROLOGUE(.option_setting_s,,)
 	KEEP(*(.option_setting_bps_sel3))
 	__OPTION_SETTING_S_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
+
+#endif
diff --git a/soc/renesas/ra/ra6m5/soc.c b/soc/renesas/ra/ra6m5/soc.c
index f156a3c5fb2..87d4b090b5c 100644
--- a/soc/renesas/ra/ra6m5/soc.c
+++ b/soc/renesas/ra/ra6m5/soc.c
@@ -25,6 +25,11 @@ uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
 
 volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
@@ -52,9 +57,16 @@ void soc_early_init_hook(void)
 	R_PSCU->PSARD = 0;
 	R_PSCU->PSARE = 0;
 
-	R_CPSCU->ICUSARG = 0;
-	R_CPSCU->ICUSARH = 0;
-	R_CPSCU->ICUSARI = 0;
+	/* The secure Attribute managed within the ARM CPU NVIC must match the
+	 * security attribution of IELSEn registers (Reference section 13.2.9
+	 * in the RA6M4 manual R01UH0890EJ0050).
+	 */
+	uint32_t volatile *p_icusarg = &R_CPSCU->ICUSARG;
+
+	for (int i = 0; i < BSP_ICU_VECTOR_MAX_ENTRIES / NUM_BITS(uint32_t); i++) {
+		p_icusarg[i] = 0;
+		NVIC->ITNS[i] = 0;
+	}
 
 	/* Enable protection using PRCR register. */
 	R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_SAR);
@@ -63,5 +75,13 @@ void soc_early_init_hook(void)
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
 
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif
+
 	irq_unlock(key);
 }
diff --git a/soc/renesas/ra/ra8d1/CMakeLists.txt b/soc/renesas/ra/ra8d1/CMakeLists.txt
index 1c7457569ef..d648d3689af 100644
--- a/soc/renesas/ra/ra8d1/CMakeLists.txt
+++ b/soc/renesas/ra/ra8d1/CMakeLists.txt
@@ -7,6 +7,10 @@ zephyr_sources(
   soc.c
 )
 
+zephyr_sources_ifdef(CONFIG_PM
+  power.c
+)
+
 zephyr_linker_sources(SECTIONS sections.ld)
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/ra/ra8d1/Kconfig b/soc/renesas/ra/ra8d1/Kconfig
index 968c60343c6..b229ca38168 100644
--- a/soc/renesas/ra/ra8d1/Kconfig
+++ b/soc/renesas/ra/ra8d1/Kconfig
@@ -14,3 +14,5 @@ config SOC_SERIES_RA8D1
 	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
 	select HAS_RENESAS_RA_FSP
 	select SOC_EARLY_INIT_HOOK
+	select GPIO_RA_HAS_VBTICTLR
+	select HAS_PM
diff --git a/soc/renesas/ra/ra8d1/Kconfig.defconfig b/soc/renesas/ra/ra8d1/Kconfig.defconfig
index 5c2a630bfd7..b74c5986b14 100644
--- a/soc/renesas/ra/ra8d1/Kconfig.defconfig
+++ b/soc/renesas/ra/ra8d1/Kconfig.defconfig
@@ -6,8 +6,36 @@ if SOC_SERIES_RA8D1
 config NUM_IRQS
 	default 96
 
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
 # Set to the minimal size of data which can be written.
 config FLASH_FILL_BUFFER_SIZE
 	default 128
 
+config DCACHE
+	default n
+
+config CACHE_MANAGEMENT
+	default n
+
+config CORTEX_M_SYSTICK
+	default n if RENESAS_RA_ULPT_TIMER
+
+DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
+DT_LOCO_PATH := $(dt_nodelabel_path,loco)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) if CORTEX_M_SYSTICK
+	default $(dt_node_int_prop_int,$(DT_LOCO_PATH),clock-frequency) if RENESAS_RA_ULPT_TIMER
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 4096 if RENESAS_RA_ULPT_TIMER
+
+config PM_DEVICE
+	default y if PM
+
 endif # SOC_SERIES_RA8D1
diff --git a/soc/renesas/ra/ra8d1/power.c b/soc/renesas/ra/ra8d1/power.c
new file mode 100644
index 00000000000..fe8b7c291f4
--- /dev/null
+++ b/soc/renesas/ra/ra8d1/power.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/pm/pm.h>
+#include <zephyr/init.h>
+#include <soc.h>
+#include <r_lpm.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
+
+/* Low Power Mode instance control structure */
+static lpm_instance_ctrl_t pm_state_ctrl;
+
+/* Configuration for Runtime Idle Power State */
+const lpm_cfg_t pm_state_runtime_idle_cfg = {
+	.low_power_mode = LPM_MODE_SLEEP,
+	.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
+	.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
+	.io_port_state = LPM_IO_PORT_NO_CHANGE,
+	.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
+	.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
+	.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
+	.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
+	.ram_retention_cfg.tcm_retention = true,
+	.ram_retention_cfg.standby_ram_retention = true,
+	.ldo_standby_cfg.pll1_ldo = false,
+	.ldo_standby_cfg.pll2_ldo = false,
+	.ldo_standby_cfg.hoco_ldo = false,
+	.p_extend = NULL,
+};
+
+/* Configuration for Standby Power State */
+const lpm_cfg_t pm_state_standby_cfg = {
+	.low_power_mode = LPM_MODE_STANDBY,
+	.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
+	.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
+	.io_port_state = LPM_IO_PORT_NO_CHANGE,
+	.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
+	.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
+	.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
+	.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
+	.ram_retention_cfg.tcm_retention = true,
+	.ram_retention_cfg.standby_ram_retention = true,
+	.ldo_standby_cfg.pll1_ldo = false,
+	.ldo_standby_cfg.pll2_ldo = false,
+	.ldo_standby_cfg.hoco_ldo = false,
+	.p_extend = NULL,
+};
+
+void pm_state_set(enum pm_state state, uint8_t substate_id)
+{
+	switch (state) {
+	case PM_STATE_RUNTIME_IDLE:
+		R_LPM_LowPowerReconfigure(&pm_state_ctrl, &pm_state_runtime_idle_cfg);
+		__disable_irq();
+		__set_BASEPRI(0);
+		__ISB();
+
+		R_LPM_LowPowerModeEnter(&pm_state_ctrl);
+		__enable_irq();
+		__ISB();
+		break;
+
+	case PM_STATE_STANDBY:
+		R_LPM_Open(&pm_state_ctrl, &pm_state_standby_cfg);
+		__disable_irq();
+		__set_BASEPRI(0);
+		__ISB();
+
+		R_LPM_LowPowerModeEnter(&pm_state_ctrl);
+		__enable_irq();
+		__ISB();
+		break;
+
+	default:
+		break;
+	}
+}
+
+void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
+{
+	switch (state) {
+	case PM_STATE_RUNTIME_IDLE:
+		__fallthrough;
+	case PM_STATE_STANDBY:
+		R_LPM_Close(&pm_state_ctrl);
+		break;
+
+	default:
+		break;
+	}
+	irq_unlock(0);
+}
diff --git a/soc/renesas/ra/ra8d1/sections.ld b/soc/renesas/ra/ra8d1/sections.ld
index 1fe7db907a3..7859d28dea5 100644
--- a/soc/renesas/ra/ra8d1/sections.ld
+++ b/soc/renesas/ra/ra8d1/sections.ld
@@ -11,6 +11,8 @@ SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
 	*(.fsp_dtc_vector_table)
 } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs))
+
 SECTION_PROLOGUE(.option_setting_ofs,,)
 {
 	__OPTION_SETTING_OFS_Start = .;
@@ -22,6 +24,10 @@ SECTION_PROLOGUE(.option_setting_ofs,,)
 	__OPTION_SETTING_OFS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas))
+
 SECTION_PROLOGUE(.option_setting_sas,,)
 {
 	__OPTION_SETTING_SAS_Start = .;
@@ -29,6 +35,10 @@ SECTION_PROLOGUE(.option_setting_sas,,)
 	__OPTION_SETTING_SAS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s))
+
 SECTION_PROLOGUE(.option_setting_s,,)
 {
 	__OPTION_SETTING_S_Start = .;
@@ -69,3 +79,5 @@ SECTION_PROLOGUE(.option_setting_s,,)
 	KEEP(*(.option_setting_bps_sel3))
 	__OPTION_SETTING_S_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
+
+#endif
diff --git a/soc/renesas/ra/ra8d1/soc.c b/soc/renesas/ra/ra8d1/soc.c
index 4d78ba0e1ca..afde75b266a 100644
--- a/soc/renesas/ra/ra8d1/soc.c
+++ b/soc/renesas/ra/ra8d1/soc.c
@@ -17,14 +17,23 @@
 #include <zephyr/arch/arm/nmi.h>
 #include <zephyr/irq.h>
 #include <zephyr/logging/log.h>
+#include <zephyr/sys/barrier.h>
+#include <zephyr/cache.h>
 LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
 
 #include <bsp_api.h>
 
+#define CCR_CACHE_ENABLE (SCB_CCR_IC_Msk | SCB_CCR_BP_Msk | SCB_CCR_LOB_Msk)
+
 uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
 
 volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
@@ -34,4 +43,35 @@ void soc_early_init_hook(void)
 {
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
+
+#ifdef CONFIG_ICACHE
+	SCB->CCR = (uint32_t)CCR_CACHE_ENABLE;
+	barrier_dsync_fence_full();
+	barrier_isync_fence_full();
+#endif
+#if defined(CONFIG_DCACHE) && defined(CONFIG_CACHE_MANAGEMENT)
+	/* Apply Arm Cortex-M85 errata workarounds for D-Cache
+	 * Attributing all cacheable memory as write-through set FORCEWT bit in MSCR register.
+	 * Set bit 16 in ACTLR to 1.
+	 * See erratum 3175626 and 3190818 in the Cortex-M85 AT640 and Cortex-M85 with FPU AT641
+	 * Software Developer Errata Notice (Date of issue: March 07, 2024, Document version: 13.0,
+	 * Document ID: SDEN-2236668).
+	 */
+	MEMSYSCTL->MSCR |= MEMSYSCTL_MSCR_FORCEWT_Msk;
+	barrier_dsync_fence_full();
+	barrier_isync_fence_full();
+	ICB->ACTLR |= (1U << 16U);
+	barrier_dsync_fence_full();
+	barrier_isync_fence_full();
+
+	sys_cache_data_enable();
+#endif
+
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif /* CONFIG_RUNTIME_NMI */
 }
diff --git a/soc/renesas/ra/ra8m1/CMakeLists.txt b/soc/renesas/ra/ra8m1/CMakeLists.txt
index 1c7457569ef..d648d3689af 100644
--- a/soc/renesas/ra/ra8m1/CMakeLists.txt
+++ b/soc/renesas/ra/ra8m1/CMakeLists.txt
@@ -7,6 +7,10 @@ zephyr_sources(
   soc.c
 )
 
+zephyr_sources_ifdef(CONFIG_PM
+  power.c
+)
+
 zephyr_linker_sources(SECTIONS sections.ld)
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/ra/ra8m1/Kconfig b/soc/renesas/ra/ra8m1/Kconfig
index f1fd9d9967e..e7ee4978139 100644
--- a/soc/renesas/ra/ra8m1/Kconfig
+++ b/soc/renesas/ra/ra8m1/Kconfig
@@ -14,5 +14,7 @@ config SOC_SERIES_RA8M1
 	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
 	select HAS_RENESAS_RA_FSP
 	select SOC_EARLY_INIT_HOOK
+	select GPIO_RA_HAS_VBTICTLR
+	select HAS_PM
 	help
 	  Enable support for Renesas RA8M1 MCU series
diff --git a/soc/renesas/ra/ra8m1/Kconfig.defconfig b/soc/renesas/ra/ra8m1/Kconfig.defconfig
index d963468bb07..faaec2c2068 100644
--- a/soc/renesas/ra/ra8m1/Kconfig.defconfig
+++ b/soc/renesas/ra/ra8m1/Kconfig.defconfig
@@ -1,4 +1,4 @@
-# Copyright (c) 2024 Renesas Electronics Corporation
+# Copyright (c) 2024-2025 Renesas Electronics Corporation
 # SPDX-License-Identifier: Apache-2.0
 
 if SOC_SERIES_RA8M1
@@ -6,8 +6,30 @@ if SOC_SERIES_RA8M1
 config NUM_IRQS
 	default 96
 
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
 # Set to the minimal size of data which can be written.
 config FLASH_FILL_BUFFER_SIZE
 	default 128
 
+config CORTEX_M_SYSTICK
+	default n if RENESAS_RA_ULPT_TIMER
+
+DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
+DT_LOCO_PATH := $(dt_nodelabel_path,loco)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) if CORTEX_M_SYSTICK
+	default $(dt_node_int_prop_int,$(DT_LOCO_PATH),clock-frequency) if RENESAS_RA_ULPT_TIMER
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 4096 if RENESAS_RA_ULPT_TIMER
+
+config PM_DEVICE
+	default y if PM
+
 endif # SOC_SERIES_RA8M1
diff --git a/soc/renesas/ra/ra8m1/power.c b/soc/renesas/ra/ra8m1/power.c
new file mode 100644
index 00000000000..fe8b7c291f4
--- /dev/null
+++ b/soc/renesas/ra/ra8m1/power.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/pm/pm.h>
+#include <zephyr/init.h>
+#include <soc.h>
+#include <r_lpm.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
+
+/* Low Power Mode instance control structure */
+static lpm_instance_ctrl_t pm_state_ctrl;
+
+/* Configuration for Runtime Idle Power State */
+const lpm_cfg_t pm_state_runtime_idle_cfg = {
+	.low_power_mode = LPM_MODE_SLEEP,
+	.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
+	.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
+	.io_port_state = LPM_IO_PORT_NO_CHANGE,
+	.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
+	.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
+	.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
+	.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
+	.ram_retention_cfg.tcm_retention = true,
+	.ram_retention_cfg.standby_ram_retention = true,
+	.ldo_standby_cfg.pll1_ldo = false,
+	.ldo_standby_cfg.pll2_ldo = false,
+	.ldo_standby_cfg.hoco_ldo = false,
+	.p_extend = NULL,
+};
+
+/* Configuration for Standby Power State */
+const lpm_cfg_t pm_state_standby_cfg = {
+	.low_power_mode = LPM_MODE_STANDBY,
+	.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
+	.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
+	.io_port_state = LPM_IO_PORT_NO_CHANGE,
+	.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
+	.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
+	.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
+	.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
+	.ram_retention_cfg.tcm_retention = true,
+	.ram_retention_cfg.standby_ram_retention = true,
+	.ldo_standby_cfg.pll1_ldo = false,
+	.ldo_standby_cfg.pll2_ldo = false,
+	.ldo_standby_cfg.hoco_ldo = false,
+	.p_extend = NULL,
+};
+
+void pm_state_set(enum pm_state state, uint8_t substate_id)
+{
+	switch (state) {
+	case PM_STATE_RUNTIME_IDLE:
+		R_LPM_LowPowerReconfigure(&pm_state_ctrl, &pm_state_runtime_idle_cfg);
+		__disable_irq();
+		__set_BASEPRI(0);
+		__ISB();
+
+		R_LPM_LowPowerModeEnter(&pm_state_ctrl);
+		__enable_irq();
+		__ISB();
+		break;
+
+	case PM_STATE_STANDBY:
+		R_LPM_Open(&pm_state_ctrl, &pm_state_standby_cfg);
+		__disable_irq();
+		__set_BASEPRI(0);
+		__ISB();
+
+		R_LPM_LowPowerModeEnter(&pm_state_ctrl);
+		__enable_irq();
+		__ISB();
+		break;
+
+	default:
+		break;
+	}
+}
+
+void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
+{
+	switch (state) {
+	case PM_STATE_RUNTIME_IDLE:
+		__fallthrough;
+	case PM_STATE_STANDBY:
+		R_LPM_Close(&pm_state_ctrl);
+		break;
+
+	default:
+		break;
+	}
+	irq_unlock(0);
+}
diff --git a/soc/renesas/ra/ra8m1/sections.ld b/soc/renesas/ra/ra8m1/sections.ld
index 1fe7db907a3..7859d28dea5 100644
--- a/soc/renesas/ra/ra8m1/sections.ld
+++ b/soc/renesas/ra/ra8m1/sections.ld
@@ -11,6 +11,8 @@ SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
 	*(.fsp_dtc_vector_table)
 } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs))
+
 SECTION_PROLOGUE(.option_setting_ofs,,)
 {
 	__OPTION_SETTING_OFS_Start = .;
@@ -22,6 +24,10 @@ SECTION_PROLOGUE(.option_setting_ofs,,)
 	__OPTION_SETTING_OFS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas))
+
 SECTION_PROLOGUE(.option_setting_sas,,)
 {
 	__OPTION_SETTING_SAS_Start = .;
@@ -29,6 +35,10 @@ SECTION_PROLOGUE(.option_setting_sas,,)
 	__OPTION_SETTING_SAS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s))
+
 SECTION_PROLOGUE(.option_setting_s,,)
 {
 	__OPTION_SETTING_S_Start = .;
@@ -69,3 +79,5 @@ SECTION_PROLOGUE(.option_setting_s,,)
 	KEEP(*(.option_setting_bps_sel3))
 	__OPTION_SETTING_S_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
+
+#endif
diff --git a/soc/renesas/ra/ra8m1/soc.c b/soc/renesas/ra/ra8m1/soc.c
index a0da08c8616..d898ab3957c 100644
--- a/soc/renesas/ra/ra8m1/soc.c
+++ b/soc/renesas/ra/ra8m1/soc.c
@@ -25,6 +25,11 @@ uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
 
 volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
@@ -34,4 +39,12 @@ void soc_early_init_hook(void)
 {
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
+
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif /* CONFIG_RUNTIME_NMI */
 }
diff --git a/soc/renesas/ra/ra8t1/CMakeLists.txt b/soc/renesas/ra/ra8t1/CMakeLists.txt
index 1c7457569ef..d648d3689af 100644
--- a/soc/renesas/ra/ra8t1/CMakeLists.txt
+++ b/soc/renesas/ra/ra8t1/CMakeLists.txt
@@ -7,6 +7,10 @@ zephyr_sources(
   soc.c
 )
 
+zephyr_sources_ifdef(CONFIG_PM
+  power.c
+)
+
 zephyr_linker_sources(SECTIONS sections.ld)
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/ra/ra8t1/Kconfig b/soc/renesas/ra/ra8t1/Kconfig
index 426e72be95d..17afc4ced60 100644
--- a/soc/renesas/ra/ra8t1/Kconfig
+++ b/soc/renesas/ra/ra8t1/Kconfig
@@ -14,3 +14,5 @@ config SOC_SERIES_RA8T1
 	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
 	select HAS_RENESAS_RA_FSP
 	select SOC_EARLY_INIT_HOOK
+	select GPIO_RA_HAS_VBTICTLR
+	select HAS_PM
diff --git a/soc/renesas/ra/ra8t1/Kconfig.defconfig b/soc/renesas/ra/ra8t1/Kconfig.defconfig
index 3e721bd8fc3..60aaa70c148 100644
--- a/soc/renesas/ra/ra8t1/Kconfig.defconfig
+++ b/soc/renesas/ra/ra8t1/Kconfig.defconfig
@@ -6,8 +6,30 @@ if SOC_SERIES_RA8T1
 config NUM_IRQS
 	default 96
 
+config BUILD_OUTPUT_HEX
+	default y
+
+config CLOCK_CONTROL
+	default y
+
 # Set to the minimal size of data which can be written.
 config FLASH_FILL_BUFFER_SIZE
 	default 128
 
+config CORTEX_M_SYSTICK
+	default n if RENESAS_RA_ULPT_TIMER
+
+DT_ICLK_PATH := $(dt_nodelabel_path,cpuclk)
+DT_LOCO_PATH := $(dt_nodelabel_path,loco)
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,$(DT_ICLK_PATH),clock-frequency) if CORTEX_M_SYSTICK
+	default $(dt_node_int_prop_int,$(DT_LOCO_PATH),clock-frequency) if RENESAS_RA_ULPT_TIMER
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 4096 if RENESAS_RA_ULPT_TIMER
+
+config PM_DEVICE
+	default y if PM
+
 endif # SOC_SERIES_RA8T1
diff --git a/soc/renesas/ra/ra8t1/power.c b/soc/renesas/ra/ra8t1/power.c
new file mode 100644
index 00000000000..fe8b7c291f4
--- /dev/null
+++ b/soc/renesas/ra/ra8t1/power.c
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/pm/pm.h>
+#include <zephyr/init.h>
+#include <soc.h>
+#include <r_lpm.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
+
+/* Low Power Mode instance control structure */
+static lpm_instance_ctrl_t pm_state_ctrl;
+
+/* Configuration for Runtime Idle Power State */
+const lpm_cfg_t pm_state_runtime_idle_cfg = {
+	.low_power_mode = LPM_MODE_SLEEP,
+	.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
+	.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
+	.io_port_state = LPM_IO_PORT_NO_CHANGE,
+	.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
+	.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
+	.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
+	.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
+	.ram_retention_cfg.tcm_retention = true,
+	.ram_retention_cfg.standby_ram_retention = true,
+	.ldo_standby_cfg.pll1_ldo = false,
+	.ldo_standby_cfg.pll2_ldo = false,
+	.ldo_standby_cfg.hoco_ldo = false,
+	.p_extend = NULL,
+};
+
+/* Configuration for Standby Power State */
+const lpm_cfg_t pm_state_standby_cfg = {
+	.low_power_mode = LPM_MODE_STANDBY,
+	.standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_ULP0U,
+	.output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN,
+	.io_port_state = LPM_IO_PORT_NO_CHANGE,
+	.power_supply_state = LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1,
+	.deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0,
+	.deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0,
+	.ram_retention_cfg.ram_retention = (uint16_t)(0x7F),
+	.ram_retention_cfg.tcm_retention = true,
+	.ram_retention_cfg.standby_ram_retention = true,
+	.ldo_standby_cfg.pll1_ldo = false,
+	.ldo_standby_cfg.pll2_ldo = false,
+	.ldo_standby_cfg.hoco_ldo = false,
+	.p_extend = NULL,
+};
+
+void pm_state_set(enum pm_state state, uint8_t substate_id)
+{
+	switch (state) {
+	case PM_STATE_RUNTIME_IDLE:
+		R_LPM_LowPowerReconfigure(&pm_state_ctrl, &pm_state_runtime_idle_cfg);
+		__disable_irq();
+		__set_BASEPRI(0);
+		__ISB();
+
+		R_LPM_LowPowerModeEnter(&pm_state_ctrl);
+		__enable_irq();
+		__ISB();
+		break;
+
+	case PM_STATE_STANDBY:
+		R_LPM_Open(&pm_state_ctrl, &pm_state_standby_cfg);
+		__disable_irq();
+		__set_BASEPRI(0);
+		__ISB();
+
+		R_LPM_LowPowerModeEnter(&pm_state_ctrl);
+		__enable_irq();
+		__ISB();
+		break;
+
+	default:
+		break;
+	}
+}
+
+void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
+{
+	switch (state) {
+	case PM_STATE_RUNTIME_IDLE:
+		__fallthrough;
+	case PM_STATE_STANDBY:
+		R_LPM_Close(&pm_state_ctrl);
+		break;
+
+	default:
+		break;
+	}
+	irq_unlock(0);
+}
diff --git a/soc/renesas/ra/ra8t1/sections.ld b/soc/renesas/ra/ra8t1/sections.ld
index 1fe7db907a3..7859d28dea5 100644
--- a/soc/renesas/ra/ra8t1/sections.ld
+++ b/soc/renesas/ra/ra8t1/sections.ld
@@ -11,6 +11,8 @@ SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
 	*(.fsp_dtc_vector_table)
 } GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_ofs))
+
 SECTION_PROLOGUE(.option_setting_ofs,,)
 {
 	__OPTION_SETTING_OFS_Start = .;
@@ -22,6 +24,10 @@ SECTION_PROLOGUE(.option_setting_ofs,,)
 	__OPTION_SETTING_OFS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_sas))
+
 SECTION_PROLOGUE(.option_setting_sas,,)
 {
 	__OPTION_SETTING_SAS_Start = .;
@@ -29,6 +35,10 @@ SECTION_PROLOGUE(.option_setting_sas,,)
 	__OPTION_SETTING_SAS_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
 
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(option_setting_s))
+
 SECTION_PROLOGUE(.option_setting_s,,)
 {
 	__OPTION_SETTING_S_Start = .;
@@ -69,3 +79,5 @@ SECTION_PROLOGUE(.option_setting_s,,)
 	KEEP(*(.option_setting_bps_sel3))
 	__OPTION_SETTING_S_End = .;
 } GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
+
+#endif
diff --git a/soc/renesas/ra/ra8t1/soc.c b/soc/renesas/ra/ra8t1/soc.c
index 33948ba3097..3c02a1cae0b 100644
--- a/soc/renesas/ra/ra8t1/soc.c
+++ b/soc/renesas/ra/ra8t1/soc.c
@@ -25,6 +25,11 @@ uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
 
 volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
 
+#ifdef CONFIG_RUNTIME_NMI
+extern bsp_grp_irq_cb_t g_bsp_group_irq_sources[];
+extern void NMI_Handler(void);
+#endif /* CONFIG_RUNTIME_NMI */
+
 /**
  * @brief Perform basic hardware initialization at boot.
  *
@@ -34,4 +39,12 @@ void soc_early_init_hook(void)
 {
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
+
+#ifdef CONFIG_RUNTIME_NMI
+	for (uint32_t i = 0; i < 16; i++) {
+		g_bsp_group_irq_sources[i] = 0;
+	}
+
+	z_arm_nmi_set_handler(NMI_Handler);
+#endif /* CONFIG_RUNTIME_NMI */
 }
diff --git a/soc/renesas/ra/soc.yml b/soc/renesas/ra/soc.yml
index 6e7887b098a..4d708f02177 100644
--- a/soc/renesas/ra/soc.yml
+++ b/soc/renesas/ra/soc.yml
@@ -4,12 +4,25 @@ family:
       - name: ra2a1
         socs:
           - name: r7fa2a1ab3cfm
+      - name: ra2l1
+        socs:
+          - name: r7fa2l1a9xxfp
+          - name: r7fa2l1abxxfp
+      - name: ra4e1
+        socs:
+          - name: r7fa4e10d2cfm
+          - name: r7fa4e10d2cne
       - name: ra4e2
         socs:
           - name: r7fa4e2b93cfm
+      - name: ra4l1
+        socs:
+          - name: r7fa4l1bd4cfp
       - name: ra4m1
         socs:
           - name: r7fa4m1ab3cfm
+          - name: r7fa4m1ab3cfp
+          - name: r7fa4m1ab3cne
       - name: ra4m2
         socs:
           - name: r7fa4m2ad3cfp
diff --git a/soc/renesas/rz/common/loader_program.S b/soc/renesas/rz/common/loader_program.S
new file mode 100644
index 00000000000..5556f42eada
--- /dev/null
+++ b/soc/renesas/rz/common/loader_program.S
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/linker/sections.h>
+
+/* Require CONFIG_XIP=n */
+#define ROM_START	(CONFIG_FLASH_BASE_ADDRESS + DT_REG_ADDR(DT_CHOSEN(zephyr_code_partition)))
+#define RAM_START	CONFIG_SRAM_BASE_ADDRESS
+#define APP_SIZE	_flash_used
+
+_ASM_FILE_PROLOGUE
+
+GTEXT(loader_program)
+
+/*
+ * Loader program
+ */
+SECTION_FUNC(loader_text, loader_program)
+	ldr r0, =ROM_START         // Src in ROM
+	ldr r1, =RAM_START         // Des in RAM
+	ldr r2, =APP_SIZE
+
+	cmp r2, #0
+	beq exit
+
+loop:
+	ldrb r3, [r0], #1    // Load byte from src and increment src pointer
+	strb r3, [r1], #1    // Store byte to des and increment des pointer
+	subs r2, r2, #1      // Decrement size and updates the condition flags
+	bne loop             // If size is not 0, repeat loop
+
+done:
+	dsb sy
+	ldr pc, =__start
+
+exit:
+	wfi
diff --git a/soc/renesas/rz/common/pinctrl_rza.h b/soc/renesas/rz/common/pinctrl_rza.h
new file mode 100644
index 00000000000..5471a358699
--- /dev/null
+++ b/soc/renesas/rz/common/pinctrl_rza.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZA_H_
+#define ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZA_H_
+
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/types.h>
+#include "r_ioport.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Porting */
+typedef struct pinctrl_cfg_data_t {
+	uint32_t reserved: 4;
+	uint32_t pupd_reg: 6;
+	uint32_t iolh_reg: 6;
+	uint32_t pmc_reg: 1;
+	uint32_t sr_reg: 1;
+	uint32_t ien_reg: 1;
+	uint32_t filonoff_reg: 1;
+	uint32_t filnum_reg: 2;
+	uint32_t filclksel_reg: 2;
+	uint32_t pfc_reg: 3;
+} pinctrl_cfg_data_t;
+
+typedef struct pinctrl_soc_pin_t {
+	bsp_io_port_pin_t port_pin;
+	pinctrl_cfg_data_t config;
+} pinctrl_soc_pin_t;
+
+/* Iterate over each pinctrl-n phandle child */
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx)                                         \
+	DT_FOREACH_CHILD(DT_PHANDLE_BY_IDX(node_id, state_prop, idx),                              \
+			 Z_PINCTRL_STATE_PIN_CHILD_INIT)
+
+/* Iterate over each pinctrl-n phandle child */
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)                                                   \
+	{DT_FOREACH_PROP_ELEM_SEP(node_id, prop, Z_PINCTRL_STATE_PIN_INIT, ())};
+
+#define Z_PINCTRL_STATE_PIN_CHILD_INIT(node_id)                                                    \
+	COND_CODE_1(DT_NODE_HAS_PROP(node_id, pinmux), \
+		    (DT_FOREACH_PROP_ELEM(node_id, pinmux, Z_PINCTRL_PINMUX_INIT)), \
+		    ())                                           \
+	COND_CODE_1(DT_NODE_HAS_PROP(node_id, pins), \
+		    (DT_FOREACH_PROP_ELEM(node_id, pins, Z_PINCTRL_SPECIAL_PINS_INIT)), \
+		    ())
+
+#define RZA_GET_PORT_PIN(pinmux) (pinmux & ~(0xF << 4))
+#define RZA_GET_FUNC(pinmux)     ((pinmux & 0xF0) >> 4)
+
+#define RZA_GET_PU_PD(node_id)                                                                     \
+	DT_PROP(node_id, bias_pull_up) == 1 ? 1U : (DT_PROP(node_id, bias_pull_down) == 1 ? 2U : 0U)
+
+#define RZA_GET_FILNUM(node_id) ((DT_PROP(node_id, renesas_filter) >> 2) & 0x3)
+
+#define RZA_GET_FILCLKSEL(node_id) (DT_PROP(node_id, renesas_filter) & 0x3)
+
+#define RZA_FILTER_ON_OFF(node_id) COND_CODE_0(DT_PROP(node_id, renesas_filter), (0), (1))
+
+/* Process pinmux cfg */
+#define Z_PINCTRL_PINMUX_INIT(node_id, state_prop, idx)                                            \
+	{                                                                                          \
+		.port_pin = RZA_GET_PORT_PIN(DT_PROP_BY_IDX(node_id, state_prop, idx)),            \
+		.config =                                                                          \
+			{                                                                          \
+				.reserved = 0,                                                     \
+				.pupd_reg = RZA_GET_PU_PD(node_id),                                \
+				.iolh_reg = DT_PROP(node_id, drive_strength),                      \
+				.pmc_reg = 1,                                                      \
+				.sr_reg = DT_ENUM_IDX(node_id, slew_rate),                         \
+				.ien_reg = DT_PROP(node_id, input_enable),                         \
+				.filonoff_reg = RZA_FILTER_ON_OFF(node_id),                        \
+				.filnum_reg = RZA_GET_FILNUM(node_id),                             \
+				.filclksel_reg = RZA_GET_FILCLKSEL(node_id),                       \
+				.pfc_reg = RZA_GET_FUNC(DT_PROP_BY_IDX(node_id, state_prop, idx)), \
+			},                                                                         \
+	},
+
+#define Z_PINCTRL_SPECIAL_PINS_INIT(node_id, state_prop, idx)                                      \
+	{                                                                                          \
+		.port_pin = DT_PROP_BY_IDX(node_id, state_prop, idx),                              \
+		.config =                                                                          \
+			{                                                                          \
+				.reserved = 0,                                                     \
+				.pupd_reg = RZA_GET_PU_PD(node_id),                                \
+				.iolh_reg = DT_PROP(node_id, drive_strength),                      \
+				.pmc_reg = 0,                                                      \
+				.sr_reg = DT_ENUM_IDX(node_id, slew_rate),                         \
+				.ien_reg = DT_PROP(node_id, input_enable),                         \
+				.filonoff_reg = RZA_FILTER_ON_OFF(node_id),                        \
+				.filnum_reg = RZA_GET_FILNUM(node_id),                             \
+				.filclksel_reg = RZA_GET_FILCLKSEL(node_id),                       \
+				.pfc_reg = 0,                                                      \
+			},                                                                         \
+	},
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZA_H_ */
diff --git a/soc/renesas/rz/common/pinctrl_rzg.h b/soc/renesas/rz/common/pinctrl_rzg.h
index e2ef13fbe33..9a580540a71 100644
--- a/soc/renesas/rz/common/pinctrl_rzg.h
+++ b/soc/renesas/rz/common/pinctrl_rzg.h
@@ -61,6 +61,14 @@ typedef struct pinctrl_soc_pin_t {
 
 #define RZG_FILTER_ON_OFF(node_id) COND_CODE_0(DT_PROP(node_id, renesas_filter), (0), (1))
 
+#if defined(CONFIG_SOC_SERIES_RZG3S)
+#define RZG_GET_PFC(node_id, state_prop, idx)                                                      \
+	(RZG_GET_FUNC(DT_PROP_BY_IDX(node_id, state_prop, idx)) - 1)
+#else
+#define RZG_GET_PFC(node_id, state_prop, idx)                                                      \
+	(RZG_GET_FUNC(DT_PROP_BY_IDX(node_id, state_prop, idx)))
+#endif
+
 /* Process pinmux cfg */
 #define Z_PINCTRL_PINMUX_INIT(node_id, state_prop, idx)                                            \
 	{                                                                                          \
@@ -75,9 +83,7 @@ typedef struct pinctrl_soc_pin_t {
 				.filonoff_reg = RZG_FILTER_ON_OFF(node_id),                        \
 				.filnum_reg = RZG_GET_FILNUM(node_id),                             \
 				.filclksel_reg = RZG_GET_FILCLKSEL(node_id),                       \
-				.pfc_reg =                                                         \
-					(RZG_GET_FUNC(DT_PROP_BY_IDX(node_id, state_prop, idx)) -  \
-					 1),                                                       \
+				.pfc_reg = RZG_GET_PFC(node_id, state_prop, idx),                  \
 			},                                                                         \
 	},
 
@@ -101,4 +107,4 @@ typedef struct pinctrl_soc_pin_t {
 #ifdef __cplusplus
 }
 #endif
-#endif /*ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZG_H_*/
+#endif /* ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZG_H_ */
diff --git a/soc/renesas/rz/common/pinctrl_rzn.h b/soc/renesas/rz/common/pinctrl_rzn.h
new file mode 100644
index 00000000000..5779dab1a49
--- /dev/null
+++ b/soc/renesas/rz/common/pinctrl_rzn.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZN_H_
+#define ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZN_H_
+
+#include <zephyr/types.h>
+#include <zephyr/devicetree.h>
+#include "r_ioport.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RZN_GET_PORT_PIN(pinmux) (pinmux & ~(0xF << 4))
+#define RZN_GET_FUNC(pinmux)     ((pinmux & 0xF0) >> 4)
+
+/* Porting */
+typedef struct pinctrl_cfg_data_t {
+	uint32_t p_reg: 1;
+	uint32_t pm_reg: 2;
+	uint32_t pmc_reg: 1;
+	uint32_t pfc_reg: 4;
+	uint32_t drct_reg: 6;
+	uint32_t rsel_reg: 1;
+	uint32_t reserved: 17;
+} pinctrl_cfg_data_t;
+
+typedef struct pinctrl_soc_pin_t {
+	bsp_io_port_pin_t port_pin;
+	pinctrl_cfg_data_t config;
+} pinctrl_soc_pin_t;
+
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx)                                               \
+	{                                                                                          \
+		.port_pin = RZN_GET_PORT_PIN(DT_PROP_BY_IDX(node_id, prop, idx)),                  \
+		.config =                                                                          \
+			{                                                                          \
+				.p_reg = DT_PROP(node_id, output_high),                            \
+				.pm_reg = DT_PROP(node_id, input_enable) == 1                      \
+						  ? 1U                                             \
+						  : (DT_PROP(node_id, output_enable) == 1 ? 2U     \
+											  : 0U),   \
+				.pmc_reg = 1,                                                      \
+				.pfc_reg = RZN_GET_FUNC(DT_PROP_BY_IDX(node_id, prop, idx)),       \
+				.drct_reg =                                                        \
+					(DT_ENUM_IDX(node_id, drive_strength)) |                   \
+					((DT_PROP(node_id, bias_pull_up) == 1                      \
+						  ? 1U                                             \
+						  : (DT_PROP(node_id, bias_pull_down) == 1 ? 2U    \
+											   : 0))   \
+					 << 2) |                                                   \
+					(DT_PROP(node_id, input_schmitt_enable) << 4) |            \
+					(DT_ENUM_IDX(node_id, slew_rate) << 5),                    \
+				.rsel_reg = 1,                                                     \
+				.reserved = 0,                                                     \
+			},                                                                         \
+	},
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)                                                   \
+	{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux,           \
+				Z_PINCTRL_STATE_PIN_INIT)}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZN_H_ */
diff --git a/soc/renesas/rz/common/pinctrl_rzt.h b/soc/renesas/rz/common/pinctrl_rzt.h
new file mode 100644
index 00000000000..e9dc810a572
--- /dev/null
+++ b/soc/renesas/rz/common/pinctrl_rzt.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZT_H_
+#define ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZT_H_
+
+#include <zephyr/types.h>
+#include <zephyr/devicetree.h>
+#include "r_ioport.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define RZT_GET_PORT_PIN(pinmux) (pinmux & ~(0xF << 4))
+#define RZT_GET_FUNC(pinmux)     ((pinmux & 0xF0) >> 4)
+
+/*Porting*/
+typedef struct pinctrl_cfg_data_t {
+	uint32_t p_reg: 1;
+	uint32_t pm_reg: 2;
+	uint32_t pmc_reg: 1;
+	uint32_t pfc_reg: 4;
+	uint32_t drct_reg: 6;
+	uint32_t rsel_reg: 1;
+	uint32_t reserved: 17;
+} pinctrl_cfg_data_t;
+
+typedef struct pinctrl_soc_pin_t {
+	bsp_io_port_pin_t port_pin;
+	pinctrl_cfg_data_t config;
+} pinctrl_soc_pin_t;
+
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx)                                               \
+	{                                                                                          \
+		.port_pin = RZT_GET_PORT_PIN(DT_PROP_BY_IDX(node_id, prop, idx)),                  \
+		.config =                                                                          \
+			{                                                                          \
+				.p_reg = DT_PROP(node_id, output_high),                            \
+				.pm_reg = DT_PROP(node_id, input_enable) == 1                      \
+						  ? 1U                                             \
+						  : (DT_PROP(node_id, output_enable) == 1 ? 2U     \
+											  : 0U),   \
+				.pmc_reg = 1,                                                      \
+				.pfc_reg = RZT_GET_FUNC(DT_PROP_BY_IDX(node_id, prop, idx)),       \
+				.drct_reg =                                                        \
+					(DT_ENUM_IDX(node_id, drive_strength)) |                   \
+					((DT_PROP(node_id, bias_pull_up) == 1                      \
+						  ? 1U                                             \
+						  : (DT_PROP(node_id, bias_pull_down) == 1 ? 2U    \
+											   : 0))   \
+					 << 2) |                                                   \
+					(DT_PROP(node_id, input_schmitt_enable) << 4) |            \
+					(DT_ENUM_IDX(node_id, slew_rate) << 5),                    \
+				.rsel_reg = 1,                                                     \
+				.reserved = 0,                                                     \
+			},                                                                         \
+	},
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)                                                   \
+	{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux,           \
+				Z_PINCTRL_STATE_PIN_INIT)}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZT_H_ */
diff --git a/soc/renesas/rz/common/pinctrl_rzv.h b/soc/renesas/rz/common/pinctrl_rzv.h
new file mode 100644
index 00000000000..a4dd50aef29
--- /dev/null
+++ b/soc/renesas/rz/common/pinctrl_rzv.h
@@ -0,0 +1,102 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZV_H_
+#define ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZV_H_
+
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/types.h>
+#include "r_ioport.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Porting */
+typedef struct pinctrl_cfg_data_t {
+	uint32_t reserved: 4;
+	uint32_t pupd_reg: 6;
+	uint32_t iolh_reg: 6;
+	uint32_t pmc_reg: 1;
+	uint32_t sr_reg: 1;
+	uint32_t ien_reg: 1;
+	uint32_t filonoff_reg: 1;
+	uint32_t filnum_reg: 2;
+	uint32_t filclksel_reg: 2;
+	uint32_t pfc_reg: 3;
+} pinctrl_cfg_data_t;
+
+typedef struct pinctrl_soc_pin_t {
+	bsp_io_port_pin_t port_pin;
+	pinctrl_cfg_data_t config;
+} pinctrl_soc_pin_t;
+
+/* Iterate over each pinctrl-n phandle child */
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx)                                         \
+	DT_FOREACH_CHILD(DT_PHANDLE_BY_IDX(node_id, state_prop, idx),                              \
+			 Z_PINCTRL_STATE_PIN_CHILD_INIT)
+
+/* Iterate over each pinctrl-n phandle child */
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)                                                   \
+	{DT_FOREACH_PROP_ELEM_SEP(node_id, prop, Z_PINCTRL_STATE_PIN_INIT, ())};
+
+#define Z_PINCTRL_STATE_PIN_CHILD_INIT(node_id)                                                    \
+	COND_CODE_1(DT_NODE_HAS_PROP(node_id, pinmux), \
+		    (DT_FOREACH_PROP_ELEM(node_id, pinmux, Z_PINCTRL_PINMUX_INIT)), \
+		    ())                                           \
+	COND_CODE_1(DT_NODE_HAS_PROP(node_id, pins), \
+		    (DT_FOREACH_PROP_ELEM(node_id, pins, Z_PINCTRL_SPECIAL_PINS_INIT)), \
+		    ())
+
+#define RZV_GET_PORT_PIN(pinmux) (pinmux & ~(0xF << 4))
+#define RZV_GET_FUNC(pinmux)     ((pinmux & 0xF0) >> 4)
+
+#define RZV_GET_PU_PD(node_id)                                                                     \
+	DT_PROP(node_id, bias_pull_up) == 1 ? 1U : (DT_PROP(node_id, bias_pull_down) == 1 ? 2U : 0U)
+
+#define RZV_GET_FILNUM(node_id) ((DT_PROP(node_id, renesas_filter) >> 2) & 0x3)
+
+#define RZV_GET_FILCLKSEL(node_id) (DT_PROP(node_id, renesas_filter) & 0x3)
+
+#define RZV_FILTER_ON_OFF(node_id) COND_CODE_0(DT_PROP(node_id, renesas_filter), (0), (1))
+
+/* Process pinmux cfg */
+#define Z_PINCTRL_PINMUX_INIT(node_id, state_prop, idx)                                            \
+	{                                                                                          \
+		.port_pin = RZV_GET_PORT_PIN(DT_PROP_BY_IDX(node_id, state_prop, idx)),            \
+		.config = {.reserved = 0,                                                          \
+			   .pupd_reg = RZV_GET_PU_PD(node_id),                                     \
+			   .iolh_reg = DT_PROP(node_id, drive_strength),                           \
+			   .pmc_reg = 1,                                                           \
+			   .sr_reg = DT_ENUM_IDX(node_id, slew_rate),                              \
+			   .ien_reg = DT_PROP(node_id, input_enable),                              \
+			   .filonoff_reg = RZV_FILTER_ON_OFF(node_id),                             \
+			   .filnum_reg = RZV_GET_FILNUM(node_id),                                  \
+			   .filclksel_reg = RZV_GET_FILCLKSEL(node_id),                            \
+			   .pfc_reg = RZV_GET_FUNC(DT_PROP_BY_IDX(node_id, state_prop, idx))},     \
+	},
+
+#define Z_PINCTRL_SPECIAL_PINS_INIT(node_id, state_prop, idx)                                      \
+	{                                                                                          \
+		.port_pin = DT_PROP_BY_IDX(node_id, state_prop, idx),                              \
+		.config =                                                                          \
+			{                                                                          \
+				.reserved = 0,                                                     \
+				.pupd_reg = RZV_GET_PU_PD(node_id),                                \
+				.iolh_reg = DT_PROP(node_id, drive_strength),                      \
+				.pmc_reg = 0,                                                      \
+				.sr_reg = DT_ENUM_IDX(node_id, slew_rate),                         \
+				.ien_reg = DT_PROP(node_id, input_enable),                         \
+				.filonoff_reg = RZV_FILTER_ON_OFF(node_id),                        \
+				.filnum_reg = RZV_GET_FILNUM(node_id),                             \
+				.filclksel_reg = RZV_GET_FILCLKSEL(node_id),                       \
+				.pfc_reg = 0,                                                      \
+			},                                                                         \
+	},
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ZEPHYR_SOC_RENESAS_RZ_COMMON_PINCTRL_RZV_H_ */
diff --git a/soc/renesas/rz/rza2m/CMakeLists.txt b/soc/renesas/rz/rza2m/CMakeLists.txt
new file mode 100644
index 00000000000..d968c2bd475
--- /dev/null
+++ b/soc/renesas/rz/rza2m/CMakeLists.txt
@@ -0,0 +1,15 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+  soc.c
+  ../common/loader_program.S
+)
+
+zephyr_library_sources_ifdef(CONFIG_ARM_AARCH32_MMU mmu_regions.c)
+
+zephyr_include_directories(.)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/rz/rza2m/Kconfig b/soc/renesas/rz/rza2m/Kconfig
new file mode 100644
index 00000000000..7b81cc9c2da
--- /dev/null
+++ b/soc/renesas/rz/rza2m/Kconfig
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZA2M
+	select ARM
+	select CPU_CORTEX_A9
diff --git a/soc/renesas/rz/rza2m/Kconfig.defconfig b/soc/renesas/rz/rza2m/Kconfig.defconfig
new file mode 100644
index 00000000000..31f95051d85
--- /dev/null
+++ b/soc/renesas/rz/rza2m/Kconfig.defconfig
@@ -0,0 +1,28 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RZA2M
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/soc/cpg/p1clk,clock-frequency)
+
+config NUM_IRQS
+	default 512
+
+config FLASH_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+DT_CHOSEN_IMAGE_ZEPHYR = zephyr,code-partition
+DT_CHOSEN_Z_SRAM = zephyr,sram
+
+config BUILD_OUTPUT_ADJUST_LMA
+	default "($(dt_chosen_partition_addr_hex,$(DT_CHOSEN_IMAGE_ZEPHYR)) - \
+	$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM)))"
+
+config BUILD_OUTPUT_ADJUST_LMA_SECTIONS
+	default "*;!.loader"
+
+endif # SOC_SERIES_RZA2M
diff --git a/soc/renesas/rz/rza2m/Kconfig.soc b/soc/renesas/rz/rza2m/Kconfig.soc
new file mode 100644
index 00000000000..c2897950bb0
--- /dev/null
+++ b/soc/renesas/rz/rza2m/Kconfig.soc
@@ -0,0 +1,24 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZA2M
+	bool
+	select SOC_FAMILY_RENESAS_RZ
+	help
+	  Renesas RZ/A2M series
+
+config SOC_SERIES
+	default "rza2m" if SOC_SERIES_RZA2M
+
+config SOC_R7S921053VCBG
+	bool
+	select SOC_SERIES_RZA2M
+	help
+	  R7S921053VCBG
+
+config SOC_R7S921053VCBG_CA9
+	bool
+	select SOC_R7S921053VCBG
+
+config SOC
+	default "r7s921053vcbg" if SOC_R7S921053VCBG
diff --git a/soc/renesas/rz/rza2m/mmu_regions.c b/soc/renesas/rz/rza2m/mmu_regions.c
new file mode 100644
index 00000000000..483ba009c8f
--- /dev/null
+++ b/soc/renesas/rz/rza2m/mmu_regions.c
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/sys/util.h>
+#include <zephyr/arch/arm/mmu/arm_mmu.h>
+#include <zephyr/devicetree.h>
+
+extern char _vector_start[];
+
+static const struct arm_mmu_region mmu_regions[] = {
+	MMU_REGION_FLAT_ENTRY("vector_tables", POINTER_TO_UINT(_vector_start), 0x1000,
+			      MT_STRONGLY_ORDERED | MPERM_R | MPERM_X),
+
+	MMU_REGION_FLAT_ENTRY("pl310", 0x1F003000, 0x1000,
+			      MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
+
+	MMU_REGION_FLAT_ENTRY("gic", DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
+			      DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
+			      MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
+
+	MMU_REGION_FLAT_ENTRY("gic", DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
+			      DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
+			      MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
+};
+
+const struct arm_mmu_config mmu_config = {
+	.num_regions = ARRAY_SIZE(mmu_regions),
+	.mmu_regions = mmu_regions,
+};
diff --git a/soc/renesas/rz/rza2m/pinctrl_soc.h b/soc/renesas/rz/rza2m/pinctrl_soc.h
new file mode 100644
index 00000000000..e8673745828
--- /dev/null
+++ b/soc/renesas/rz/rza2m/pinctrl_soc.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RZA2M_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RZA2M_PINCTRL_SOC_H_
+
+#include <zephyr/types.h>
+
+typedef struct pinctrl_soc_pin {
+	uint8_t port;
+	uint8_t pin;
+	uint8_t func;
+	uint8_t drive_strength;
+} pinctrl_soc_pin_t;
+
+#define RZA2M_PINS_PER_PORT 8
+
+#define RZA2M_MUX_FUNC_MAX      (BIT(0) | BIT(1) | BIT(2))
+#define RZA2M_FUNC_GPIO_INPUT   BIT(3) /* Pin as input */
+#define RZA2M_FUNC_GPIO_OUTPUT  BIT(4) /* Pin as output */
+#define RZA2M_FUNC_GPIO_INT_EN  BIT(5) /* Enable interrupt for gpio */
+#define RZA2M_FUNC_GPIO_INT_DIS BIT(6) /* Disable interrupt for gpio */
+#define RZA2M_FUNC_GPIO_HIZ     BIT(7) /* Hi-Z mode */
+/*
+ * Use 16 lower bits [15:0] for pin identifier
+ * Use 16 higher bits [31:16] for pin mux function
+ */
+#define RZA2M_MUX_PIN_ID_MASK   GENMASK(15, 0)
+#define RZA2M_MUX_FUNC_MASK     GENMASK(31, 16)
+#define RZA2M_MUX_FUNC_OFFS     16
+#define RZA2M_FUNC(prop)        ((prop & RZA2M_MUX_FUNC_MASK) >> RZA2M_MUX_FUNC_OFFS)
+#define RZA2M_PINCODE(prop)     (prop & RZA2M_MUX_PIN_ID_MASK)
+#define RZA2M_PORT(prop)        ((RZA2M_PINCODE(prop)) / RZA2M_PINS_PER_PORT)
+#define RZA2M_PIN(prop)         ((RZA2M_PINCODE(prop)) % RZA2M_PINS_PER_PORT)
+
+#define Z_PINCTRL_PINMUX_INIT(node_id, state_prop, idx)                                            \
+	{                                                                                          \
+		.port = RZA2M_PORT(DT_PROP_BY_IDX(node_id, state_prop, idx)),                      \
+		.pin = RZA2M_PIN(DT_PROP_BY_IDX(node_id, state_prop, idx)),                        \
+		.func = RZA2M_FUNC(DT_PROP_BY_IDX(node_id, state_prop, idx)),                      \
+		.drive_strength = DT_PROP_OR(node_id, drive_strength, 0),                          \
+	},
+
+#define Z_PINCTRL_STATE_PIN_CHILD_INIT(node_id)                                                    \
+	COND_CODE_1(DT_NODE_HAS_PROP(node_id, pinmux),                                             \
+		    (DT_FOREACH_PROP_ELEM(node_id, pinmux, Z_PINCTRL_PINMUX_INIT)),                \
+		    ())
+
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx)                                         \
+	DT_FOREACH_CHILD(DT_PHANDLE_BY_IDX(node_id, state_prop, idx),                              \
+			 Z_PINCTRL_STATE_PIN_CHILD_INIT)
+
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)                                                   \
+	{DT_FOREACH_PROP_ELEM_SEP(node_id, prop, Z_PINCTRL_STATE_PIN_INIT, ())};
+
+#endif /* ZEPHYR_SOC_RENESAS_RZA2M_PINCTRL_SOC_H_ */
diff --git a/soc/renesas/rz/rza2m/sections.ld b/soc/renesas/rz/rza2m/sections.ld
new file mode 100644
index 00000000000..3abeb09abe3
--- /dev/null
+++ b/soc/renesas/rz/rza2m/sections.ld
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/devicetree.h>
+
+SECTION_PROLOGUE(.loader, CONFIG_FLASH_BASE_ADDRESS,)
+{
+	__loader_program_start = .;
+	KEEP(*(.loader_text.*))
+	__loader_program_end = .;
+} GROUP_LINK_IN(FLASH)
diff --git a/soc/renesas/rz/rza2m/soc.c b/soc/renesas/rz/rza2m/soc.c
new file mode 100644
index 00000000000..a48668181f6
--- /dev/null
+++ b/soc/renesas/rz/rza2m/soc.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/init.h>
+#include <zephyr/arch/cpu.h>
+#include <zephyr/kernel.h>
+
+extern char _vector_start[];
+
+void relocate_vector_table(void)
+{
+#if defined(CONFIG_XIP) && (CONFIG_FLASH_BASE_ADDRESS != 0) ||                                     \
+	!defined(CONFIG_XIP) && (CONFIG_SRAM_BASE_ADDRESS != 0)
+	write_sctlr(read_sctlr() & ~HIVECS);
+#elif defined(CONFIG_SW_VECTOR_RELAY) || defined(CONFIG_SW_VECTOR_RELAY_CLIENT)
+	_vector_table_pointer = _vector_start;
+#endif
+	__set_VBAR(POINTER_TO_UINT(_vector_start));
+}
diff --git a/soc/renesas/rz/rza2m/soc.h b/soc/renesas/rz/rza2m/soc.h
new file mode 100644
index 00000000000..c58c8ec84bf
--- /dev/null
+++ b/soc/renesas/rz/rza2m/soc.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RZA2M_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RZA2M_SOC_H_
+
+/*
+ * The following definitions are required for the inclusion of the CMSIS
+ * Common Peripheral Access Layer for aarch32 Cortex-A CPUs:
+ */
+
+#define __CORTEX_A 9U
+
+#endif /* ZEPHYR_SOC_RENESAS_RZA2M_SOC_H_ */
diff --git a/soc/renesas/rz/rza3ul/CMakeLists.txt b/soc/renesas/rz/rza3ul/CMakeLists.txt
new file mode 100644
index 00000000000..b7bb7ee2f2a
--- /dev/null
+++ b/soc/renesas/rz/rza3ul/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(soc.c)
+zephyr_library_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)
+
+zephyr_include_directories(.)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/rz/rza3ul/Kconfig b/soc/renesas/rz/rza3ul/Kconfig
new file mode 100644
index 00000000000..f5b3226633c
--- /dev/null
+++ b/soc/renesas/rz/rza3ul/Kconfig
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZA3UL
+	select ARM64
+	select CPU_CORTEX_A55
+	select ARM_ARCH_TIMER
+	select HAS_RENESAS_RZ_FSP
+	select SOC_EARLY_INIT_HOOK
diff --git a/soc/renesas/rz/rza3ul/Kconfig.defconfig b/soc/renesas/rz/rza3ul/Kconfig.defconfig
new file mode 100644
index 00000000000..6af7d5b7c9a
--- /dev/null
+++ b/soc/renesas/rz/rza3ul/Kconfig.defconfig
@@ -0,0 +1,31 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RZA3UL
+
+config SYS_CLOCK_EXISTS
+	default y
+
+config NUM_IRQS
+	default 512
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 24000000
+
+config FLASH_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+DT_CHOSEN_IMAGE_ZEPHYR = zephyr,code-partition
+DT_CHOSEN_SRAM_ZEPHYR = zephyr,sram
+
+config BUILD_OUTPUT_ADJUST_LMA
+	default "$(dt_chosen_partition_addr_hex,$(DT_CHOSEN_IMAGE_ZEPHYR)) - \
+	$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_SRAM_ZEPHYR))"
+
+config BUILD_OUTPUT_ADJUST_LMA_SECTIONS
+	default "*;!.header"
+
+endif # SOC_SERIES_RZA3UL
diff --git a/soc/renesas/rz/rza3ul/Kconfig.soc b/soc/renesas/rz/rza3ul/Kconfig.soc
new file mode 100644
index 00000000000..f77dd2aa1d5
--- /dev/null
+++ b/soc/renesas/rz/rza3ul/Kconfig.soc
@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZA3UL
+	bool
+	select SOC_FAMILY_RENESAS_RZ
+	help
+	  Renesas RZ/A3UL series
+
+config SOC_SERIES
+	default "rza3ul" if SOC_SERIES_RZA3UL
+
+config SOC_R9A07G063U02GBG
+	bool
+	select SOC_SERIES_RZA3UL
+	help
+	  R9A07G063U02GBG
+
+config SOC
+	default "r9a07g063u02gbg" if SOC_R9A07G063U02GBG
diff --git a/soc/renesas/rz/rza3ul/mmu_regions.c b/soc/renesas/rz/rza3ul/mmu_regions.c
new file mode 100644
index 00000000000..3f07572e580
--- /dev/null
+++ b/soc/renesas/rz/rza3ul/mmu_regions.c
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm64/arm_mmu.h>
+#include <zephyr/devicetree.h>
+
+static const struct arm_mmu_region mmu_regions[] = {
+	MMU_REGION_FLAT_ENTRY("IO_REG", 0x10000000, 0x10000000,
+			      MT_DEVICE_nGnRnE | MT_RW | MT_DEFAULT_SECURE_STATE),
+};
+
+const struct arm_mmu_config mmu_config = {
+	.num_regions = ARRAY_SIZE(mmu_regions),
+	.mmu_regions = mmu_regions,
+};
diff --git a/soc/renesas/rz/rza3ul/pinctrl_soc.h b/soc/renesas/rz/rza3ul/pinctrl_soc.h
new file mode 100644
index 00000000000..44733d79afd
--- /dev/null
+++ b/soc/renesas/rz/rza3ul/pinctrl_soc.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RZ_RZA3UL_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RZ_RZA3UL_PINCTRL_SOC_H_
+
+#include <pinctrl_rza.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RZ_RZA3UL_PINCTRL_SOC_H_ */
diff --git a/soc/renesas/rz/rza3ul/sections.ld b/soc/renesas/rz/rza3ul/sections.ld
new file mode 100644
index 00000000000..bdc29c67e39
--- /dev/null
+++ b/soc/renesas/rz/rza3ul/sections.ld
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+SECTION_PROLOGUE(.header, CONFIG_FLASH_BASE_ADDRESS,)
+{
+	QUAD(__start)
+	QUAD(0xFFFFFFFFFFFFFFFF-__start)
+	QUAD(CONFIG_SRAM_BASE_ADDRESS)
+	QUAD(0xFFFFFFFFFFFFFFFF-CONFIG_SRAM_BASE_ADDRESS)
+	QUAD(z_mapped_size)
+	QUAD(0xFFFFFFFFFFFFFFFF-z_mapped_size)
+	FILL(0x00)
+	. += 0x1B0;
+	QUAD(0x4120505346205a52)
+	QUAD(0x69746163696c7070)
+	QUAD(0x0000000000006e6f)
+	QUAD(0x0000000000000000)
+} > FLASH
+
+z_mapped_size = z_mapped_end - z_mapped_start;
diff --git a/soc/renesas/rz/rza3ul/soc.c b/soc/renesas/rz/rza3ul/soc.c
new file mode 100644
index 00000000000..dbfb58d4f17
--- /dev/null
+++ b/soc/renesas/rz/rza3ul/soc.c
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RZ/A3UL Group
+ */
+
+#include <zephyr/init.h>
+#include "soc.h"
+
+uint32_t SystemCoreClock;
+
+void soc_early_init_hook(void)
+{
+	/* Configure system clocks. */
+	bsp_clock_init();
+
+	/* InitFialize SystemCoreClock variable. */
+	SystemCoreClockUpdate();
+}
diff --git a/soc/renesas/rz/rza3ul/soc.h b/soc/renesas/rz/rza3ul/soc.h
new file mode 100644
index 00000000000..5df3ba6851e
--- /dev/null
+++ b/soc/renesas/rz/rza3ul/soc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RZA3UL_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RZA3UL_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RZG3S_SOC_H_ */
diff --git a/soc/renesas/rz/rzg2l/CMakeLists.txt b/soc/renesas/rz/rzg2l/CMakeLists.txt
new file mode 100644
index 00000000000..a58ca9b77f5
--- /dev/null
+++ b/soc/renesas/rz/rzg2l/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(soc.c)
+
+zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/rz/rzg2l/Kconfig b/soc/renesas/rz/rzg2l/Kconfig
new file mode 100644
index 00000000000..fa2ec4ab067
--- /dev/null
+++ b/soc/renesas/rz/rzg2l/Kconfig
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZG2L
+	select ARM
+	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_MPU
+	select HAS_RENESAS_RZ_FSP
+	select CPU_CORTEX_M_HAS_DWT
+	select SOC_EARLY_INIT_HOOK
diff --git a/soc/renesas/rz/rzg2l/Kconfig.defconfig b/soc/renesas/rz/rzg2l/Kconfig.defconfig
new file mode 100644
index 00000000000..bfde46db7e1
--- /dev/null
+++ b/soc/renesas/rz/rzg2l/Kconfig.defconfig
@@ -0,0 +1,24 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RZG2L
+
+config NUM_IRQS
+	default 480
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default	$(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config FLASH_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+config SYS_CLOCK_EXISTS
+	default y
+
+config INIT_ARCH_HW_AT_BOOT
+	default y
+
+endif # SOC_SERIES_RZG2L
diff --git a/soc/renesas/rz/rzg2l/Kconfig.soc b/soc/renesas/rz/rzg2l/Kconfig.soc
new file mode 100644
index 00000000000..a5971ea64c0
--- /dev/null
+++ b/soc/renesas/rz/rzg2l/Kconfig.soc
@@ -0,0 +1,35 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZG2L
+	bool
+	select SOC_FAMILY_RENESAS_RZ
+	help
+	  Renesas RZ/G2L series
+
+config SOC_SERIES
+	default "rzg2l" if SOC_SERIES_RZG2L
+
+config SOC_R9A07G044L23GBG
+	bool
+	select SOC_SERIES_RZG2L
+	help
+	  R9A07G044L23GBG
+
+config SOC_R9A07G044C22GBG
+	bool
+	select SOC_SERIES_RZG2L
+	help
+	  R9A07G044C22GBG
+
+config SOC_R9A07G044L23GBG_CM33
+	bool
+	select SOC_R9A07G044L23GBG
+
+config SOC_R9A07G044C22GBG_CM33
+	bool
+	select SOC_R9A07G044C22GBG
+
+config SOC
+	default "r9a07g044l23gbg" if SOC_R9A07G044L23GBG
+	default "r9a07g044c22gbg" if SOC_R9A07G044C22GBG
diff --git a/soc/renesas/rz/rzg2l/pinctrl_soc.h b/soc/renesas/rz/rzg2l/pinctrl_soc.h
new file mode 100644
index 00000000000..cd19f259325
--- /dev/null
+++ b/soc/renesas/rz/rzg2l/pinctrl_soc.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RZ_RZG2L_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RZ_RZG2L_PINCTRL_SOC_H_
+
+#include <pinctrl_rzg.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RZ_RZG2L_PINCTRL_SOC_H_ */
diff --git a/soc/renesas/rz/rzg2l/soc.c b/soc/renesas/rz/rzg2l/soc.c
new file mode 100644
index 00000000000..2418462b14a
--- /dev/null
+++ b/soc/renesas/rz/rzg2l/soc.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RZ/G2L Group
+ */
+
+#include <zephyr/init.h>
+#include <bsp_api.h>
+
+/* System core clock is set to 200 MHz after reset */
+uint32_t SystemCoreClock = 200000000;
+
+void soc_early_init_hook(void)
+{
+	bsp_clock_init();
+}
diff --git a/soc/renesas/rz/rzg2l/soc.h b/soc/renesas/rz/rzg2l/soc.h
new file mode 100644
index 00000000000..20cdc8fd15a
--- /dev/null
+++ b/soc/renesas/rz/rzg2l/soc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RZG2L_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RZG2L_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RZG2L_SOC_H_ */
diff --git a/soc/renesas/rz/rzg3s/CMakeLists.txt b/soc/renesas/rz/rzg3s/CMakeLists.txt
index 2db47f0bb79..7947143a2ab 100644
--- a/soc/renesas/rz/rzg3s/CMakeLists.txt
+++ b/soc/renesas/rz/rzg3s/CMakeLists.txt
@@ -6,3 +6,8 @@ zephyr_sources(soc.c)
 zephyr_include_directories(.)
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
+
+zephyr_linker_sources_ifdef(CONFIG_OPENAMP
+  RODATA
+  resource_table.ld
+)
diff --git a/soc/renesas/rz/rzg3s/resource_table.ld b/soc/renesas/rz/rzg3s/resource_table.ld
new file mode 100644
index 00000000000..d33e1f917c1
--- /dev/null
+++ b/soc/renesas/rz/rzg3s/resource_table.ld
@@ -0,0 +1,6 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+KEEP(*(.resource_table*))
diff --git a/soc/renesas/rz/rzn2l/CMakeLists.txt b/soc/renesas/rz/rzn2l/CMakeLists.txt
new file mode 100644
index 00000000000..7633a8ff2a6
--- /dev/null
+++ b/soc/renesas/rz/rzn2l/CMakeLists.txt
@@ -0,0 +1,14 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+  soc.c
+  loader_param.c
+  ../common/loader_program.S
+)
+
+zephyr_include_directories(.)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_r/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/rz/rzn2l/Kconfig b/soc/renesas/rz/rzn2l/Kconfig
new file mode 100644
index 00000000000..3833827bae2
--- /dev/null
+++ b/soc/renesas/rz/rzn2l/Kconfig
@@ -0,0 +1,13 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZN2L
+	select ARM
+	select CPU_CORTEX_R52
+	select CPU_HAS_ARM_MPU
+	select HAS_RENESAS_RZ_FSP
+	select ARM_ARCH_TIMER
+	select GIC_SINGLE_SECURITY_STATE
+	select SOC_RESET_HOOK
+	select SOC_EARLY_INIT_HOOK
+	select ARM_CUSTOM_INTERRUPT_CONTROLLER
diff --git a/soc/renesas/rz/rzn2l/Kconfig.defconfig b/soc/renesas/rz/rzn2l/Kconfig.defconfig
new file mode 100644
index 00000000000..dd1fbedacd3
--- /dev/null
+++ b/soc/renesas/rz/rzn2l/Kconfig.defconfig
@@ -0,0 +1,30 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RZN2L
+
+config NUM_IRQS
+	default 480
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 25000000
+
+config FPU
+	default y
+
+config FLASH_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+DT_CHOSEN_IMAGE_ZEPHYR = zephyr,code-partition
+
+config BUILD_OUTPUT_ADJUST_LMA
+	default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_ZEPHYR)) + \
+	$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)))"
+
+config BUILD_OUTPUT_ADJUST_LMA_SECTIONS
+	default "*;!.loader"
+
+endif # SOC_SERIES_RZN2L
diff --git a/soc/renesas/rz/rzn2l/Kconfig.soc b/soc/renesas/rz/rzn2l/Kconfig.soc
new file mode 100644
index 00000000000..c95b6f596a1
--- /dev/null
+++ b/soc/renesas/rz/rzn2l/Kconfig.soc
@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZN2L
+	bool
+	select SOC_FAMILY_RENESAS_RZ
+	help
+	  Renesas RZ/N2L series
+
+config SOC_SERIES
+	default "rzn2l" if SOC_SERIES_RZN2L
+
+config SOC_R9A07G084M04GBG
+	bool
+	select SOC_SERIES_RZN2L
+	help
+	  R9A07G084M04GBG
+
+config SOC
+	default "r9a07g084m04gbg" if SOC_R9A07G084M04GBG
diff --git a/soc/renesas/rz/rzn2l/loader_param.c b/soc/renesas/rz/rzn2l/loader_param.c
new file mode 100644
index 00000000000..8c15d563bce
--- /dev/null
+++ b/soc/renesas/rz/rzn2l/loader_param.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <zephyr/linker/section_tags.h>
+
+#define CACHE_FLG            (0x00000000)
+#define CS0BCR_V_WRAPCFG_V   (0x00000000)
+#define CS0WCR_V_COMCFG_V    (0x00000000)
+#define DUMMY0_BMCFG_V       (0x00000000)
+#define BSC_FLG_xSPI_FLG     (0x00000000)
+#define LDR_ADDR_NML         (0x6000004C)
+#define LDR_SIZE_NML         (0x00006000)
+#define DEST_ADDR_NML        (0x00102000)
+#define DUMMY1               (0x00000000)
+#define DUMMY2               (0x00000000)
+#define DUMMY3_CSSCTL_V      (0x0000003F)
+#define DUMMY4_LIOCFGCS0_V   (0x00070000)
+#define DUMMY5               (0x00000000)
+#define DUMMY6               (0x00000000)
+#define DUMMY7               (0x00000000)
+#define DUMMY8               (0x00000000)
+#define DUMMY9               (0x00000000)
+#define DUMMY10_ACCESS_SPEED (0x00000006)
+#define CHECK_SUM            (0xE0A8)
+#define LOADER_PARAM_MAX     (19)
+
+#define __loader_param Z_GENERIC_SECTION(.loader_param)
+
+const uint32_t loader_param[LOADER_PARAM_MAX] __loader_param = {
+	CACHE_FLG,
+	CS0BCR_V_WRAPCFG_V,
+	CS0WCR_V_COMCFG_V,
+	DUMMY0_BMCFG_V,
+	BSC_FLG_xSPI_FLG,
+	LDR_ADDR_NML,
+	LDR_SIZE_NML,
+	DEST_ADDR_NML,
+	DUMMY1,
+	DUMMY2,
+	DUMMY3_CSSCTL_V,
+	DUMMY4_LIOCFGCS0_V,
+	DUMMY5,
+	DUMMY6,
+	DUMMY7,
+	DUMMY8,
+	DUMMY9,
+	DUMMY10_ACCESS_SPEED,
+	CHECK_SUM,
+};
diff --git a/soc/renesas/rz/rzn2l/pinctrl_soc.h b/soc/renesas/rz/rzn2l/pinctrl_soc.h
new file mode 100644
index 00000000000..459bcd6cbd8
--- /dev/null
+++ b/soc/renesas/rz/rzn2l/pinctrl_soc.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RZ_RZN2L_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RZ_RZN2L_PINCTRL_SOC_H_
+
+#include <pinctrl_rzn.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RZ_RZN2L_PINCTRL_SOC_H_ */
diff --git a/soc/renesas/rz/rzn2l/sections.ld b/soc/renesas/rz/rzn2l/sections.ld
new file mode 100644
index 00000000000..f1f3a9665b2
--- /dev/null
+++ b/soc/renesas/rz/rzn2l/sections.ld
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/devicetree.h>
+
+SECTION_PROLOGUE(.loader, CONFIG_FLASH_BASE_ADDRESS,)
+{
+	__loader_param_start = .;
+	KEEP(*(.loader_param))
+	__loader_param_end = .;
+	. = DT_REG_ADDR(DT_NODELABEL(loader_program));
+	__loader_program_start = .;
+	KEEP(*(.loader_text.*))
+	__loader_program_end = .;
+} GROUP_LINK_IN(FLASH)
diff --git a/soc/renesas/rz/rzn2l/soc.c b/soc/renesas/rz/rzn2l/soc.c
new file mode 100644
index 00000000000..b8d2b30c235
--- /dev/null
+++ b/soc/renesas/rz/rzn2l/soc.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RZ/N2L Group
+ */
+
+#include <bsp_api.h>
+#include <zephyr/init.h>
+#include <zephyr/sys/barrier.h>
+#include <zephyr/drivers/interrupt_controller/gic.h>
+#include <zephyr/irq.h>
+
+extern void bsp_global_system_counter_init(void);
+
+void *gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES + BSP_CORTEX_VECTOR_TABLE_ENTRIES];
+IRQn_Type g_current_interrupt_num[32];
+uint8_t g_current_interrupt_pointer;
+
+void soc_reset_hook(void)
+{
+	/* Enable peripheral port access at EL1 and EL0 */
+	__asm__ volatile("mrc p15, 0, r0, c15, c0, 0\n");
+	__asm__ volatile("orr r0, #1\n");
+	__asm__ volatile("mcr p15, 0, r0, c15, c0, 0\n");
+	barrier_dsync_fence_full();
+	barrier_isync_fence_full();
+}
+
+void soc_early_init_hook(void)
+{
+	/* Configure system clocks. */
+	bsp_clock_init();
+
+	/* Initialize SystemCoreClock variable. */
+	SystemCoreClockUpdate();
+
+	/* Initialize global system counter. The counter is enabled and is incrementing. */
+	bsp_global_system_counter_init();
+}
+
+unsigned int z_soc_irq_get_active(void)
+{
+	int intid = arm_gic_get_active();
+
+	g_current_interrupt_num[g_current_interrupt_pointer++] = intid;
+
+	return intid;
+}
+
+void z_soc_irq_eoi(unsigned int intid)
+{
+	g_current_interrupt_pointer--;
+	arm_gic_eoi(intid);
+}
+
+void z_soc_irq_enable(unsigned int irq)
+{
+	arm_gic_irq_enable(irq);
+}
+
+void z_soc_irq_disable(unsigned int irq)
+{
+	arm_gic_irq_disable(irq);
+}
+
+int z_soc_irq_is_enabled(unsigned int irq)
+{
+	return arm_gic_irq_is_enabled(irq);
+}
+
+void z_soc_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
+{
+	arm_gic_irq_set_priority(irq, prio, flags);
+}
+
+void z_soc_irq_init(void)
+{
+	g_current_interrupt_pointer = 0;
+}
+
+/* Porting FSP IRQ configuration by an empty function */
+/* Let Zephyr handle IRQ configuration */
+void bsp_irq_core_cfg(void)
+{
+	/* Do nothing */
+}
diff --git a/soc/renesas/rz/rzn2l/soc.h b/soc/renesas/rz/rzn2l/soc.h
new file mode 100644
index 00000000000..e99f72f790b
--- /dev/null
+++ b/soc/renesas/rz/rzn2l/soc.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RZN2L_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RZN2L_SOC_H_
+
+typedef enum IRQn {
+	SoftwareGeneratedInt0 = 0,
+	SoftwareGeneratedInt1,
+	SoftwareGeneratedInt2,
+	SoftwareGeneratedInt3,
+	SoftwareGeneratedInt4,
+	SoftwareGeneratedInt5,
+	SoftwareGeneratedInt6,
+	SoftwareGeneratedInt7,
+	SoftwareGeneratedInt8,
+	SoftwareGeneratedInt9,
+	SoftwareGeneratedInt10,
+	SoftwareGeneratedInt11,
+	SoftwareGeneratedInt12,
+	SoftwareGeneratedInt13,
+	SoftwareGeneratedInt14,
+	SoftwareGeneratedInt15,
+	DebugCommunicationsChannelInt = 22,
+	PerformanceMonitorCounterOverflowInt = 23,
+	CrossTriggerInterfaceInt = 24,
+	VritualCPUInterfaceMaintenanceInt = 25,
+	HypervisorTimerInt = 26,
+	VirtualTimerInt = 27,
+	NonSecurePhysicalTimerInt = 30,
+	SHARED_PERIPHERAL_INTERRUPTS_MAX_ENTRIES = CONFIG_NUM_IRQS
+} IRQn_Type;
+
+/* Do not let CMSIS to handle GIC and Timer */
+#define __GIC_PRESENT 0
+#define __TIM_PRESENT 0
+#define __FPU_PRESENT 1
+
+/* Porting FSP IRQ configuration by an empty function */
+/* Let Zephyr handle IRQ configuration */
+void bsp_irq_core_cfg(void);
+
+#endif /* ZEPHYR_SOC_RENESAS_RZN2L_SOC_H_ */
diff --git a/soc/renesas/rz/rzt2l/CMakeLists.txt b/soc/renesas/rz/rzt2l/CMakeLists.txt
new file mode 100644
index 00000000000..7633a8ff2a6
--- /dev/null
+++ b/soc/renesas/rz/rzt2l/CMakeLists.txt
@@ -0,0 +1,14 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+  soc.c
+  loader_param.c
+  ../common/loader_program.S
+)
+
+zephyr_include_directories(.)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_r/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/rz/rzt2l/Kconfig b/soc/renesas/rz/rzt2l/Kconfig
new file mode 100644
index 00000000000..90fdc7792d5
--- /dev/null
+++ b/soc/renesas/rz/rzt2l/Kconfig
@@ -0,0 +1,13 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZT2L
+	select ARM
+	select CPU_CORTEX_R52
+	select CPU_HAS_ARM_MPU
+	select GIC_SINGLE_SECURITY_STATE
+	select ARM_ARCH_TIMER
+	select HAS_RENESAS_RZ_FSP
+	select SOC_RESET_HOOK
+	select SOC_EARLY_INIT_HOOK
+	select ARM_CUSTOM_INTERRUPT_CONTROLLER
diff --git a/soc/renesas/rz/rzt2l/Kconfig.defconfig b/soc/renesas/rz/rzt2l/Kconfig.defconfig
new file mode 100644
index 00000000000..3a8c8b13c65
--- /dev/null
+++ b/soc/renesas/rz/rzt2l/Kconfig.defconfig
@@ -0,0 +1,30 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RZT2L
+
+config NUM_IRQS
+	default 480
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 25000000
+
+config FPU
+	default y
+
+config FLASH_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+DT_CHOSEN_IMAGE_ZEPHYR = zephyr,code-partition
+
+config BUILD_OUTPUT_ADJUST_LMA
+	default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_ZEPHYR)) + \
+	$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)))"
+
+config BUILD_OUTPUT_ADJUST_LMA_SECTIONS
+	default "*;!.loader"
+
+endif # SOC_SERIES_RZT2L
diff --git a/soc/renesas/rz/rzt2l/Kconfig.soc b/soc/renesas/rz/rzt2l/Kconfig.soc
new file mode 100644
index 00000000000..6e2625b3200
--- /dev/null
+++ b/soc/renesas/rz/rzt2l/Kconfig.soc
@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZT2L
+	bool
+	select SOC_FAMILY_RENESAS_RZ
+	help
+	  Renesas RZ/T2L series
+
+config SOC_SERIES
+	default "rzt2l" if SOC_SERIES_RZT2L
+
+config SOC_R9A07G074M04GBG
+	bool
+	select SOC_SERIES_RZT2L
+	help
+	  R9A07G074M04GBG
+
+config SOC
+	default "r9a07g074m04gbg" if SOC_R9A07G074M04GBG
diff --git a/soc/renesas/rz/rzt2l/loader_param.c b/soc/renesas/rz/rzt2l/loader_param.c
new file mode 100644
index 00000000000..7e948b3f72c
--- /dev/null
+++ b/soc/renesas/rz/rzt2l/loader_param.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <zephyr/linker/section_tags.h>
+
+#define CACHE_FLG            (0x00000000)
+#define CS0BCR_V_WRAPCFG_V   (0x00000000)
+#define CS0WCR_V_COMCFG_V    (0x00000000)
+#define DUMMY0_BMCFG_V       (0x00000000)
+#define BSC_FLG_xSPI_FLG     (0x00000000)
+#define LDR_ADDR_NML         (0x6800004C)
+#define LDR_SIZE_NML         (0x00006000)
+#define DEST_ADDR_NML        (0x00102000)
+#define DUMMY1               (0x00000000)
+#define DUMMY2               (0x00000000)
+#define DUMMY3_CSSCTL_V      (0x0000003F)
+#define DUMMY4_LIOCFGCS0_V   (0x00070000)
+#define DUMMY5               (0x00000000)
+#define DUMMY6               (0x00000000)
+#define DUMMY7               (0x00000000)
+#define DUMMY8               (0x00000000)
+#define DUMMY9               (0x00000000)
+#define DUMMY10_ACCESS_SPEED (0x00000600)
+#define CHECK_SUM            (0xEEA2)
+#define LOADER_PARAM_MAX     (19)
+
+#define __loader_param Z_GENERIC_SECTION(.loader_param)
+
+const uint32_t loader_param[LOADER_PARAM_MAX] __loader_param = {
+	CACHE_FLG,
+	CS0BCR_V_WRAPCFG_V,
+	CS0WCR_V_COMCFG_V,
+	DUMMY0_BMCFG_V,
+	BSC_FLG_xSPI_FLG,
+	LDR_ADDR_NML,
+	LDR_SIZE_NML,
+	DEST_ADDR_NML,
+	DUMMY1,
+	DUMMY2,
+	DUMMY3_CSSCTL_V,
+	DUMMY4_LIOCFGCS0_V,
+	DUMMY5,
+	DUMMY6,
+	DUMMY7,
+	DUMMY8,
+	DUMMY9,
+	DUMMY10_ACCESS_SPEED,
+	CHECK_SUM,
+};
diff --git a/soc/renesas/rz/rzt2l/pinctrl_soc.h b/soc/renesas/rz/rzt2l/pinctrl_soc.h
new file mode 100644
index 00000000000..adcf52454b0
--- /dev/null
+++ b/soc/renesas/rz/rzt2l/pinctrl_soc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RZ_RZT2L_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RZ_RZT2L_PINCTRL_SOC_H_
+
+#include <pinctrl_rzt.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RZ_RZT2L_PINCTRL_SOC_H_ */
diff --git a/soc/renesas/rz/rzt2l/sections.ld b/soc/renesas/rz/rzt2l/sections.ld
new file mode 100644
index 00000000000..f1f3a9665b2
--- /dev/null
+++ b/soc/renesas/rz/rzt2l/sections.ld
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/devicetree.h>
+
+SECTION_PROLOGUE(.loader, CONFIG_FLASH_BASE_ADDRESS,)
+{
+	__loader_param_start = .;
+	KEEP(*(.loader_param))
+	__loader_param_end = .;
+	. = DT_REG_ADDR(DT_NODELABEL(loader_program));
+	__loader_program_start = .;
+	KEEP(*(.loader_text.*))
+	__loader_program_end = .;
+} GROUP_LINK_IN(FLASH)
diff --git a/soc/renesas/rz/rzt2l/soc.c b/soc/renesas/rz/rzt2l/soc.c
new file mode 100644
index 00000000000..28a554f6aa5
--- /dev/null
+++ b/soc/renesas/rz/rzt2l/soc.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <bsp_api.h>
+#include <zephyr/init.h>
+#include <zephyr/sys/barrier.h>
+#include <zephyr/drivers/interrupt_controller/gic.h>
+#include <zephyr/irq.h>
+
+extern void bsp_global_system_counter_init(void);
+
+void *gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES + BSP_CORTEX_VECTOR_TABLE_ENTRIES];
+IRQn_Type g_current_interrupt_num[32];
+uint8_t g_current_interrupt_pointer;
+
+void soc_reset_hook(void)
+{
+	/* Enable peripheral port access at EL1 and EL0 */
+	__asm__ volatile("mrc p15, 0, r0, c15, c0, 0\n");
+	__asm__ volatile("orr r0, #1\n");
+	__asm__ volatile("mcr p15, 0, r0, c15, c0, 0\n");
+	barrier_dsync_fence_full();
+	barrier_isync_fence_full();
+}
+
+void soc_early_init_hook(void)
+{
+	/* Configure system clocks. */
+	bsp_clock_init();
+
+	/* Initialize SystemCoreClock variable. */
+	SystemCoreClockUpdate();
+
+	/* Initialize global system counter. The counter is enabled and is incrementing. */
+	bsp_global_system_counter_init();
+}
+
+unsigned int z_soc_irq_get_active(void)
+{
+	int intid = arm_gic_get_active();
+
+	g_current_interrupt_num[g_current_interrupt_pointer++] = intid;
+
+	return intid;
+}
+
+void z_soc_irq_eoi(unsigned int intid)
+{
+	g_current_interrupt_pointer--;
+	arm_gic_eoi(intid);
+}
+
+void z_soc_irq_enable(unsigned int irq)
+{
+	arm_gic_irq_enable(irq);
+}
+
+void z_soc_irq_disable(unsigned int irq)
+{
+	arm_gic_irq_disable(irq);
+}
+
+int z_soc_irq_is_enabled(unsigned int irq)
+{
+	return arm_gic_irq_is_enabled(irq);
+}
+
+void z_soc_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
+{
+	arm_gic_irq_set_priority(irq, prio, flags);
+}
+
+void z_soc_irq_init(void)
+{
+	g_current_interrupt_pointer = 0;
+}
+
+/* Porting FSP IRQ configuration by an empty function */
+/* Let Zephyr handle IRQ configuration */
+void bsp_irq_core_cfg(void)
+{
+	/* Do nothing */
+}
diff --git a/soc/renesas/rz/rzt2l/soc.h b/soc/renesas/rz/rzt2l/soc.h
new file mode 100644
index 00000000000..79436f6ad16
--- /dev/null
+++ b/soc/renesas/rz/rzt2l/soc.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RZT2L_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RZT2L_SOC_H_
+
+typedef enum IRQn {
+	SoftwareGeneratedInt0 = 0,
+	SoftwareGeneratedInt1,
+	SoftwareGeneratedInt2,
+	SoftwareGeneratedInt3,
+	SoftwareGeneratedInt4,
+	SoftwareGeneratedInt5,
+	SoftwareGeneratedInt6,
+	SoftwareGeneratedInt7,
+	SoftwareGeneratedInt8,
+	SoftwareGeneratedInt9,
+	SoftwareGeneratedInt10,
+	SoftwareGeneratedInt11,
+	SoftwareGeneratedInt12,
+	SoftwareGeneratedInt13,
+	SoftwareGeneratedInt14,
+	SoftwareGeneratedInt15,
+	DebugCommunicationsChannelInt = 22,
+	PerformanceMonitorCounterOverflowInt = 23,
+	CrossTriggerInterfaceInt = 24,
+	VritualCPUInterfaceMaintenanceInt = 25,
+	HypervisorTimerInt = 26,
+	VirtualTimerInt = 27,
+	NonSecurePhysicalTimerInt = 30,
+	SHARED_PERIPHERAL_INTERRUPTS_MAX_ENTRIES = CONFIG_NUM_IRQS
+} IRQn_Type;
+
+/* Do not let CMSIS to handle GIC and Timer */
+#define __GIC_PRESENT 0
+#define __TIM_PRESENT 0
+#define __FPU_PRESENT 1
+
+/* Porting FSP IRQ configuration by an empty function */
+/* Let Zephyr handle IRQ configuration */
+void bsp_irq_core_cfg(void);
+
+#endif /* ZEPHYR_SOC_RENESAS_RZT2L_SOC_H_ */
diff --git a/soc/renesas/rz/rzt2m/CMakeLists.txt b/soc/renesas/rz/rzt2m/CMakeLists.txt
new file mode 100644
index 00000000000..539837b1be6
--- /dev/null
+++ b/soc/renesas/rz/rzt2m/CMakeLists.txt
@@ -0,0 +1,15 @@
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+  soc.c
+  loader_param.c
+  ../common/loader_program.S
+)
+
+zephyr_include_directories(.)
+
+zephyr_linker_sources(SECTIONS sections.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_r/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/rz/rzt2m/Kconfig b/soc/renesas/rz/rzt2m/Kconfig
new file mode 100644
index 00000000000..5f8948a7c3b
--- /dev/null
+++ b/soc/renesas/rz/rzt2m/Kconfig
@@ -0,0 +1,14 @@
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZT2M
+	select ARM
+	select CPU_CORTEX_R52
+	select CPU_HAS_ARM_MPU
+	select GIC_SINGLE_SECURITY_STATE
+	select ARM_ARCH_TIMER
+	select HAS_RENESAS_RZ_FSP
+	select SOC_RESET_HOOK
+	select SOC_EARLY_INIT_HOOK
+	select ARM_CUSTOM_INTERRUPT_CONTROLLER
diff --git a/soc/renesas/rz/rzt2m/Kconfig.defconfig b/soc/renesas/rz/rzt2m/Kconfig.defconfig
new file mode 100644
index 00000000000..c6fc83fcae0
--- /dev/null
+++ b/soc/renesas/rz/rzt2m/Kconfig.defconfig
@@ -0,0 +1,31 @@
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RZT2M
+
+config NUM_IRQS
+	default 480
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 25000000
+
+config FPU
+	default y
+
+config FLASH_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+DT_CHOSEN_IMAGE_ZEPHYR = zephyr,code-partition
+
+config BUILD_OUTPUT_ADJUST_LMA
+	default "($(dt_chosen_reg_addr_hex,$(DT_CHOSEN_IMAGE_ZEPHYR)) + \
+	$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)))"
+
+config BUILD_OUTPUT_ADJUST_LMA_SECTIONS
+	default "*;!.loader"
+
+endif # SOC_SERIES_RZT2M
diff --git a/soc/renesas/rz/rzt2m/Kconfig.soc b/soc/renesas/rz/rzt2m/Kconfig.soc
new file mode 100644
index 00000000000..c14a76612e8
--- /dev/null
+++ b/soc/renesas/rz/rzt2m/Kconfig.soc
@@ -0,0 +1,25 @@
+# Copyright (c) 2023 Antmicro <www.antmicro.com>
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZT2M
+	bool
+	select SOC_FAMILY_RENESAS_RZ
+	help
+	  Renesas RZ/T2M series
+
+config SOC_SERIES
+	default "rzt2m" if SOC_SERIES_RZT2M
+
+config SOC_R9A07G075M24GBG
+	bool
+	select SOC_SERIES_RZT2M
+	help
+	  R9A07G075M24GBG
+
+config SOC_R9A07G075M24GBG_CR520
+	bool
+	select SOC_R9A07G075M24GBG
+
+config SOC
+	default "r9a07g075m24gbg" if SOC_R9A07G075M24GBG
diff --git a/soc/renesas/rzt2m/linker.ld b/soc/renesas/rz/rzt2m/linker.ld
similarity index 100%
rename from soc/renesas/rzt2m/linker.ld
rename to soc/renesas/rz/rzt2m/linker.ld
diff --git a/soc/renesas/rz/rzt2m/loader_param.c b/soc/renesas/rz/rzt2m/loader_param.c
new file mode 100644
index 00000000000..8c15d563bce
--- /dev/null
+++ b/soc/renesas/rz/rzt2m/loader_param.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+#include <zephyr/linker/section_tags.h>
+
+#define CACHE_FLG            (0x00000000)
+#define CS0BCR_V_WRAPCFG_V   (0x00000000)
+#define CS0WCR_V_COMCFG_V    (0x00000000)
+#define DUMMY0_BMCFG_V       (0x00000000)
+#define BSC_FLG_xSPI_FLG     (0x00000000)
+#define LDR_ADDR_NML         (0x6000004C)
+#define LDR_SIZE_NML         (0x00006000)
+#define DEST_ADDR_NML        (0x00102000)
+#define DUMMY1               (0x00000000)
+#define DUMMY2               (0x00000000)
+#define DUMMY3_CSSCTL_V      (0x0000003F)
+#define DUMMY4_LIOCFGCS0_V   (0x00070000)
+#define DUMMY5               (0x00000000)
+#define DUMMY6               (0x00000000)
+#define DUMMY7               (0x00000000)
+#define DUMMY8               (0x00000000)
+#define DUMMY9               (0x00000000)
+#define DUMMY10_ACCESS_SPEED (0x00000006)
+#define CHECK_SUM            (0xE0A8)
+#define LOADER_PARAM_MAX     (19)
+
+#define __loader_param Z_GENERIC_SECTION(.loader_param)
+
+const uint32_t loader_param[LOADER_PARAM_MAX] __loader_param = {
+	CACHE_FLG,
+	CS0BCR_V_WRAPCFG_V,
+	CS0WCR_V_COMCFG_V,
+	DUMMY0_BMCFG_V,
+	BSC_FLG_xSPI_FLG,
+	LDR_ADDR_NML,
+	LDR_SIZE_NML,
+	DEST_ADDR_NML,
+	DUMMY1,
+	DUMMY2,
+	DUMMY3_CSSCTL_V,
+	DUMMY4_LIOCFGCS0_V,
+	DUMMY5,
+	DUMMY6,
+	DUMMY7,
+	DUMMY8,
+	DUMMY9,
+	DUMMY10_ACCESS_SPEED,
+	CHECK_SUM,
+};
diff --git a/soc/renesas/rz/rzt2m/pinctrl_soc.h b/soc/renesas/rz/rzt2m/pinctrl_soc.h
new file mode 100644
index 00000000000..b4844f72964
--- /dev/null
+++ b/soc/renesas/rz/rzt2m/pinctrl_soc.h
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RZ_RZT2M_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RZ_RZT2M_PINCTRL_SOC_H_
+
+#include <pinctrl_rzt.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RZ_RZT2M_PINCTRL_SOC_H_ */
diff --git a/soc/renesas/rz/rzt2m/sections.ld b/soc/renesas/rz/rzt2m/sections.ld
new file mode 100644
index 00000000000..f1f3a9665b2
--- /dev/null
+++ b/soc/renesas/rz/rzt2m/sections.ld
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/devicetree.h>
+
+SECTION_PROLOGUE(.loader, CONFIG_FLASH_BASE_ADDRESS,)
+{
+	__loader_param_start = .;
+	KEEP(*(.loader_param))
+	__loader_param_end = .;
+	. = DT_REG_ADDR(DT_NODELABEL(loader_program));
+	__loader_program_start = .;
+	KEEP(*(.loader_text.*))
+	__loader_program_end = .;
+} GROUP_LINK_IN(FLASH)
diff --git a/soc/renesas/rz/rzt2m/soc.c b/soc/renesas/rz/rzt2m/soc.c
new file mode 100644
index 00000000000..951f99473e3
--- /dev/null
+++ b/soc/renesas/rz/rzt2m/soc.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <bsp_api.h>
+#include <zephyr/init.h>
+#include <zephyr/sys/barrier.h>
+#include <zephyr/drivers/interrupt_controller/gic.h>
+#include <zephyr/irq.h>
+
+extern void bsp_global_system_counter_init(void);
+
+void *gp_renesas_isr_context[BSP_ICU_VECTOR_MAX_ENTRIES + BSP_CORTEX_VECTOR_TABLE_ENTRIES];
+IRQn_Type g_current_interrupt_num[32];
+uint8_t g_current_interrupt_pointer;
+
+void soc_reset_hook(void)
+{
+	/* Enable peripheral port access at EL1 and EL0 */
+	__asm__ volatile("mrc p15, 0, r0, c15, c0, 0\n");
+	__asm__ volatile("orr r0, #1\n");
+	__asm__ volatile("mcr p15, 0, r0, c15, c0, 0\n");
+	barrier_dsync_fence_full();
+	barrier_isync_fence_full();
+}
+
+void soc_early_init_hook(void)
+{
+	/* Configure system clocks. */
+	bsp_clock_init();
+
+	/* Initialize SystemCoreClock variable. */
+	SystemCoreClockUpdate();
+
+	/* Initialize global system counter. The counter is enabled and is incrementing. */
+	bsp_global_system_counter_init();
+}
+
+unsigned int z_soc_irq_get_active(void)
+{
+	int intid = arm_gic_get_active();
+
+	g_current_interrupt_num[g_current_interrupt_pointer++] = intid;
+
+	return intid;
+}
+
+void z_soc_irq_eoi(unsigned int intid)
+{
+	g_current_interrupt_pointer--;
+	arm_gic_eoi(intid);
+}
+
+void z_soc_irq_enable(unsigned int irq)
+{
+	arm_gic_irq_enable(irq);
+}
+
+void z_soc_irq_disable(unsigned int irq)
+{
+	arm_gic_irq_disable(irq);
+}
+
+int z_soc_irq_is_enabled(unsigned int irq)
+{
+	return arm_gic_irq_is_enabled(irq);
+}
+
+void z_soc_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
+{
+	arm_gic_irq_set_priority(irq, prio, flags);
+}
+
+void z_soc_irq_init(void)
+{
+	g_current_interrupt_pointer = 0;
+}
+
+/* Porting FSP IRQ configuration by an empty function */
+/* Let Zephyr handle IRQ configuration */
+void bsp_irq_core_cfg(void)
+{
+	/* Do nothing */
+}
diff --git a/soc/renesas/rz/rzt2m/soc.h b/soc/renesas/rz/rzt2m/soc.h
new file mode 100644
index 00000000000..e17e05f67a5
--- /dev/null
+++ b/soc/renesas/rz/rzt2m/soc.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2023 Antmicro <www.antmicro.com>
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RZT2M_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RZT2M_SOC_H_
+
+typedef enum IRQn {
+	SoftwareGeneratedInt0 = 0,
+	SoftwareGeneratedInt1,
+	SoftwareGeneratedInt2,
+	SoftwareGeneratedInt3,
+	SoftwareGeneratedInt4,
+	SoftwareGeneratedInt5,
+	SoftwareGeneratedInt6,
+	SoftwareGeneratedInt7,
+	SoftwareGeneratedInt8,
+	SoftwareGeneratedInt9,
+	SoftwareGeneratedInt10,
+	SoftwareGeneratedInt11,
+	SoftwareGeneratedInt12,
+	SoftwareGeneratedInt13,
+	SoftwareGeneratedInt14,
+	SoftwareGeneratedInt15,
+	DebugCommunicationsChannelInt = 22,
+	PerformanceMonitorCounterOverflowInt = 23,
+	CrossTriggerInterfaceInt = 24,
+	VritualCPUInterfaceMaintenanceInt = 25,
+	HypervisorTimerInt = 26,
+	VirtualTimerInt = 27,
+	NonSecurePhysicalTimerInt = 30,
+	SHARED_PERIPHERAL_INTERRUPTS_MAX_ENTRIES = CONFIG_NUM_IRQS
+} IRQn_Type;
+
+/* Do not let CMSIS to handle GIC and Timer */
+#define __GIC_PRESENT 0
+#define __TIM_PRESENT 0
+#define __FPU_PRESENT 1
+
+/* Porting FSP IRQ configuration by an empty function */
+/* Let Zephyr handle IRQ configuration */
+void bsp_irq_core_cfg(void);
+
+#endif /* ZEPHYR_SOC_RENESAS_RZT2M_SOC_H_ */
diff --git a/soc/renesas/rz/rzv2l/CMakeLists.txt b/soc/renesas/rz/rzv2l/CMakeLists.txt
new file mode 100644
index 00000000000..a58ca9b77f5
--- /dev/null
+++ b/soc/renesas/rz/rzv2l/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(soc.c)
+
+zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/rz/rzv2l/Kconfig b/soc/renesas/rz/rzv2l/Kconfig
new file mode 100644
index 00000000000..408fc656c7e
--- /dev/null
+++ b/soc/renesas/rz/rzv2l/Kconfig
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZV2L
+	select ARM
+	select CPU_CORTEX_M33
+	select CPU_HAS_ARM_MPU
+	select HAS_RENESAS_RZ_FSP
+	select CPU_CORTEX_M_HAS_DWT
+	select SOC_EARLY_INIT_HOOK
diff --git a/soc/renesas/rz/rzv2l/Kconfig.defconfig b/soc/renesas/rz/rzv2l/Kconfig.defconfig
new file mode 100644
index 00000000000..335d6e01d91
--- /dev/null
+++ b/soc/renesas/rz/rzv2l/Kconfig.defconfig
@@ -0,0 +1,27 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_RZV2L
+
+config NUM_IRQS
+	default 480
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default	$(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config FLASH_SIZE
+	default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
+
+config FLASH_BASE_ADDRESS
+	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
+
+config SYS_CLOCK_EXISTS
+	default y
+
+config INIT_ARCH_HW_AT_BOOT
+	default y
+
+config BUILD_OUTPUT_S19
+	default y
+
+endif # SOC_SERIES_RZV2L
diff --git a/soc/renesas/rz/rzv2l/Kconfig.soc b/soc/renesas/rz/rzv2l/Kconfig.soc
new file mode 100644
index 00000000000..87411267379
--- /dev/null
+++ b/soc/renesas/rz/rzv2l/Kconfig.soc
@@ -0,0 +1,24 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RZV2L
+	bool
+	select SOC_FAMILY_RENESAS_RZ
+	help
+	  Renesas RZ/V2L series
+
+config SOC_SERIES
+	default "rzv2l" if SOC_SERIES_RZV2L
+
+config SOC_R9A07G054L23GBG
+	bool
+	select SOC_SERIES_RZV2L
+	help
+	  R9A07G054L23GBG
+
+config SOC_R9A07G054L23GBG_CM33
+	bool
+	select SOC_R9A07G054L23GBG
+
+config SOC
+	default "r9a07g054l23gbg" if SOC_R9A07G054L23GBG
diff --git a/soc/renesas/rz/rzv2l/pinctrl_soc.h b/soc/renesas/rz/rzv2l/pinctrl_soc.h
new file mode 100644
index 00000000000..e2c055c173d
--- /dev/null
+++ b/soc/renesas/rz/rzv2l/pinctrl_soc.h
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RZ_RZV2L_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RZ_RZV2L_PINCTRL_SOC_H_
+
+#include <pinctrl_rzv.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RZ_RZV2L_PINCTRL_SOC_H_ */
diff --git a/soc/renesas/rz/rzv2l/soc.c b/soc/renesas/rz/rzv2l/soc.c
new file mode 100644
index 00000000000..ac2139cf7fa
--- /dev/null
+++ b/soc/renesas/rz/rzv2l/soc.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for Renesas RZ/V2L Group
+ */
+
+#include <zephyr/init.h>
+#include <bsp_api.h>
+
+/* System core clock is set to 200 MHz after reset */
+uint32_t SystemCoreClock = 200000000;
+
+void soc_early_init_hook(void)
+{
+	bsp_clock_init();
+}
diff --git a/soc/renesas/rz/rzv2l/soc.h b/soc/renesas/rz/rzv2l/soc.h
new file mode 100644
index 00000000000..dd59487008a
--- /dev/null
+++ b/soc/renesas/rz/rzv2l/soc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_RENESAS_RZV2L_SOC_H_
+#define ZEPHYR_SOC_RENESAS_RZV2L_SOC_H_
+
+#include <bsp_api.h>
+
+#endif /* ZEPHYR_SOC_RENESAS_RZV2L_SOC_H_ */
diff --git a/soc/renesas/rz/soc.yml b/soc/renesas/rz/soc.yml
index 3cc8edd8baf..57681f2cab3 100644
--- a/soc/renesas/rz/soc.yml
+++ b/soc/renesas/rz/soc.yml
@@ -1,8 +1,38 @@
 family:
   - name: renesas_rz
     series:
+      - name: rza2m
+        socs:
+          - name: r7s921053vcbg
+      - name: rza3ul
+        socs:
+          - name: r9a07g063u02gbg
+      - name: rzg2l
+        socs:
+          - name: r9a07g044l23gbg
+            cpuclusters:
+              - name: cm33
+          - name: r9a07g044c22gbg
+            cpuclusters:
+              - name: cm33
       - name: rzg3s
         socs:
           - name: r9a08g045s33gbg
             cpuclusters:
               - name: cm33
+      - name: rzv2l
+        socs:
+          - name: r9a07g054l23gbg
+            cpuclusters:
+              - name: cm33
+      - name: rzn2l
+        socs:
+          - name: r9a07g084m04gbg
+      - name: rzt2l
+        socs:
+          - name: r9a07g074m04gbg
+      - name: rzt2m
+        socs:
+          - name: r9a07g075m24gbg
+            cpuclusters:
+              - name: cr520
diff --git a/soc/renesas/rzt2m/CMakeLists.txt b/soc/renesas/rzt2m/CMakeLists.txt
deleted file mode 100644
index 8cf72713d11..00000000000
--- a/soc/renesas/rzt2m/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# Copyright (c) 2023 Antmicro <www.antmicro.com>
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_sources(soc.c)
-
-zephyr_include_directories(.)
-
-set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_r/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/renesas/rzt2m/Kconfig b/soc/renesas/rzt2m/Kconfig
deleted file mode 100644
index 1b0d438c31f..00000000000
--- a/soc/renesas/rzt2m/Kconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-# Copyright (c) 2023 Antmicro <www.antmicro.com>
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_RENESAS_RZT2M
-	select ARM
-	select CPU_CORTEX_R52
-	select CPU_HAS_ARM_MPU
-	select GIC_SINGLE_SECURITY_STATE
-	select ARM_ARCH_TIMER
-	select SYSCON
-	select SOC_EARLY_INIT_HOOK
diff --git a/soc/renesas/rzt2m/Kconfig.defconfig b/soc/renesas/rzt2m/Kconfig.defconfig
deleted file mode 100644
index 7eedc53ffc6..00000000000
--- a/soc/renesas/rzt2m/Kconfig.defconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-# Copyright (c) 2023 Antmicro <www.antmicro.com>
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_RENESAS_RZT2M
-
-config NUM_IRQS
-	default 994
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default 20000000
-
-config FPU
-	default y
-
-config FLASH_SIZE
-	default 0
-
-config FLASH_BASE_ADDRESS
-	default 0
-
-endif # SOC_RENESAS_RZT2M
diff --git a/soc/renesas/rzt2m/Kconfig.soc b/soc/renesas/rzt2m/Kconfig.soc
deleted file mode 100644
index 9304484d065..00000000000
--- a/soc/renesas/rzt2m/Kconfig.soc
+++ /dev/null
@@ -1,14 +0,0 @@
-# Copyright (c) 2023 Antmicro <www.antmicro.com>
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_RENESAS_RZT2M
-	bool
-
-config SOC_PART_NUMBER_R9A07G075
-	bool
-
-config SOC
-	default "renesas_rzt2m" if SOC_RENESAS_RZT2M
-
-config SOC_PART_NUMBER
-	default "R9A07G075" if SOC_PART_NUMBER_R9A07G075
diff --git a/soc/renesas/rzt2m/pinctrl_soc.h b/soc/renesas/rzt2m/pinctrl_soc.h
deleted file mode 100644
index d740d6c115e..00000000000
--- a/soc/renesas/rzt2m/pinctrl_soc.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Copyright (c) 2023 Antmicro <www.antmicro.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef ZEPHYR_SOC_ARM_RENESAS_RZT2M_PINCTRL_H_
-#define ZEPHYR_SOC_ARM_RENESAS_RZT2M_PINCTRL_H_
-
-#include <zephyr/types.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct pinctrl_soc_pin_t {
-	uint32_t port;
-	uint32_t pin;
-	uint32_t func;
-	uint32_t input_enable: 1;
-	uint32_t output_enable: 1;
-	uint32_t pull_up: 1;
-	uint32_t pull_down: 1;
-	uint32_t high_impedance: 1;
-	uint32_t slew_rate: 2;
-	uint8_t drive_strength;
-	uint32_t schmitt_enable: 1;
-} pinctrl_soc_pin_t;
-
-#define RZT2M_GET_PORT(pinctrl) ((pinctrl >> 16) & 0xff)
-#define RZT2M_GET_PIN(pinctrl) ((pinctrl >> 8) & 0xff)
-#define RZT2M_GET_FUNC(pinctrl) (pinctrl & 0xff)
-
-#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx)			\
-	{							\
-		.port = RZT2M_GET_PORT(DT_PROP_BY_IDX(node_id, prop, idx)),	\
-		.pin = RZT2M_GET_PIN(DT_PROP_BY_IDX(node_id, prop, idx)),	\
-		.func = RZT2M_GET_FUNC(DT_PROP_BY_IDX(node_id, prop, idx)),	\
-		.input_enable = DT_PROP(node_id, input_enable),	\
-		.pull_up = DT_PROP(node_id, bias_pull_up),	\
-		.pull_down = DT_PROP(node_id, bias_pull_down),	\
-		.high_impedance = DT_PROP(node_id, bias_high_impedance),	\
-		.slew_rate = DT_ENUM_IDX(node_id, slew_rate),	\
-		.drive_strength = DT_ENUM_IDX(node_id, drive_strength),	\
-		.schmitt_enable = DT_PROP(node_id, input_schmitt_enable),	\
-	},
-
-#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)                \
-	{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop),	\
-				DT_FOREACH_PROP_ELEM, pinmux,   \
-				Z_PINCTRL_STATE_PIN_INIT)}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ZEPHYR_SOC_ARM_RENESAS_RZT2M_PINCTRL_H_ */
diff --git a/soc/renesas/rzt2m/soc.c b/soc/renesas/rzt2m/soc.c
deleted file mode 100644
index 183381179ba..00000000000
--- a/soc/renesas/rzt2m/soc.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright (c) 2023 Antmicro <www.antmicro.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/init.h>
-#include <stdint.h>
-#include <zephyr/drivers/syscon.h>
-#include "soc.h"
-#include <zephyr/sys/util_macro.h>
-
-static const struct device *const prcrn_dev = DEVICE_DT_GET(DT_NODELABEL(prcrn));
-static const struct device *const prcrs_dev = DEVICE_DT_GET(DT_NODELABEL(prcrs));
-static const struct device *const sckcr_dev = DEVICE_DT_GET(DT_NODELABEL(sckcr));
-static const struct device *const sckcr2_dev = DEVICE_DT_GET(DT_NODELABEL(sckcr2));
-
-void rzt2m_unlock_prcrn(uint32_t mask)
-{
-	uint32_t prcrn;
-
-	syscon_read_reg(prcrn_dev, 0, &prcrn);
-	prcrn |= PRC_KEY_CODE | mask;
-
-	syscon_write_reg(prcrn_dev, 0, prcrn);
-}
-
-void rzt2m_lock_prcrn(uint32_t mask)
-{
-	uint32_t prcrn;
-
-	syscon_read_reg(prcrn_dev, 0, &prcrn);
-	prcrn &= ~mask;
-	prcrn |= PRC_KEY_CODE;
-
-	syscon_write_reg(prcrn_dev, 0, prcrn);
-}
-
-void rzt2m_unlock_prcrs(uint32_t mask)
-{
-	uint32_t prcrs;
-
-	syscon_read_reg(prcrs_dev, 0, &prcrs);
-	prcrs |= PRC_KEY_CODE | mask;
-
-	syscon_write_reg(prcrs_dev, 0, prcrs);
-}
-
-void rzt2m_lock_prcrs(uint32_t mask)
-{
-	uint32_t prcrs;
-
-	syscon_read_reg(prcrs_dev, 0, &prcrs);
-	prcrs &= ~mask;
-	prcrs |= PRC_KEY_CODE;
-
-	syscon_write_reg(prcrs_dev, 0, prcrs);
-}
-
-void rzt2m_set_sckcr2(uint32_t mask)
-{
-	syscon_write_reg(sckcr2_dev, 0, mask);
-}
-
-uint32_t rzt2m_get_sckcr2(void)
-{
-	uint32_t reg;
-
-	syscon_read_reg(sckcr2_dev, 0, &reg);
-	return reg;
-}
-
-void rzt2m_set_sckcr(uint32_t mask)
-{
-	syscon_write_reg(sckcr_dev, 0, mask);
-}
-
-uint32_t rzt2m_get_sckcr(void)
-{
-	uint32_t reg;
-
-	syscon_read_reg(sckcr_dev, 0, &reg);
-	return reg;
-}
-
-void rzt2m_enable_counters(void)
-{
-	const struct device *const dev = DEVICE_DT_GET(DT_NODELABEL(gsc));
-
-	syscon_write_reg(dev, 0, CNTCR_EN);
-}
-
-void soc_early_init_hook(void)
-{
-	/* Unlock the Protect Registers
-	 * so that device drivers can access configuration registers of peripherals.
-	 */
-	/* After the device drivers are done, lock the Protect Registers. */
-	rzt2m_unlock_prcrs(PRCRS_GPIO | PRCRS_CLK);
-	rzt2m_unlock_prcrn(PRCRN_PRC1 | PRCRN_PRC2 | PRCRN_PRC0);
-
-	/* Reset the System Clock Control Registers to default values */
-	rzt2m_set_sckcr(
-		CLMASEL |
-		PHYSEL |
-		FSELCANFD |
-		FSELXSPI0_DEFAULT |
-		FSELXSPI1_DEFAULT |
-		CKIO_DEFAULT
-	);
-
-	rzt2m_set_sckcr2(FSELCPU0_DEFAULT | FSELCPU1_DEFAULT);
-
-	rzt2m_lock_prcrs(PRCRS_GPIO | PRCRS_CLK);
-	rzt2m_lock_prcrn(PRCRN_PRC1 | PRCRN_PRC2 | PRCRN_PRC0);
-
-	rzt2m_enable_counters();
-}
diff --git a/soc/renesas/rzt2m/soc.h b/soc/renesas/rzt2m/soc.h
deleted file mode 100644
index 64ccdc0e0b5..00000000000
--- a/soc/renesas/rzt2m/soc.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (c) 2023 Antmicro <www.antmicro.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#ifndef _SOC__H_
-#define _SOC__H_
-
-/* Do not let CMSIS to handle GIC and Timer */
-#include <stdint.h>
-#define __GIC_PRESENT 0
-#define __TIM_PRESENT 0
-
-/* Global system counter */
-#define CNTCR_EN   BIT(0)
-#define CNTCR_HDBG BIT(1)
-
-/* Safety area protect register */
-#define PRCRS_CLK       BIT(0)
-#define PRCRS_LPC_RESET BIT(1)
-#define PRCRS_GPIO      BIT(2)
-#define PRCRS_SYS_CTRL  BIT(3)
-
-/* Non-safety area protect register */
-#define PRCRN_PRC0 BIT(0)
-#define PRCRN_PRC1 BIT(1)
-#define PRCRN_PRC2 BIT(2)
-
-#define SCI4ASYNCSEL BIT(31)
-#define SCI3ASYNCSEL BIT(30)
-#define SCI2ASYNCSEL BIT(29)
-#define SCI1ASYNCSEL BIT(28)
-#define SCI0ASYNCSEL BIT(27)
-#define SPI2ASYNCSEL BIT(26)
-#define SPI1ASYNCSEL BIT(25)
-#define SPI0ASYNCSEL BIT(24)
-#define CLMASEL      BIT(22)
-#define PHYSEL       BIT(21)
-#define FSELCANFD    BIT(20)
-#define DIVSELXSPI1  BIT(14)
-#define DIVSELXSPI0  BIT(6)
-
-#define CKIO_DEFAULT      BIT(17)
-#define FSELXSPI1_DEFAULT GENMASK(10, 9)
-#define FSELXSPI0_DEFAULT GENMASK(2, 1)
-
-#define SCI5ASYNCSEL     BIT(25)
-#define SPI3ASYNCSEL     BIT(24)
-#define DIVSELSUB        BIT(5)
-#define FSELCPU1_DEFAULT 0b10 << 2
-#define FSELCPU0_DEFAULT 0b10 << 0
-
-/* PRC Key Code - this value is required to allow any write operation
- * to the PRCRS / PRCRN registers.
- * See section 10.2 of the RZ/T2M User's Manual: Hardware.
- */
-#define PRC_KEY_CODE 0xa500
-
-void rzt2m_unlock_prcrn(uint32_t mask);
-void rzt2m_lock_prcrn(uint32_t mask);
-void rzt2m_unlock_prcrs(uint32_t mask);
-void rzt2m_lock_prcrs(uint32_t mask);
-
-void rzt2m_set_sckcr2(uint32_t mask);
-uint32_t rzt2m_get_sckcr2(void);
-void rzt2m_set_sckcr(uint32_t mask);
-uint32_t rzt2m_get_sckcr(void);
-
-#endif /* _SOC__H_ */
diff --git a/soc/renesas/rzt2m/soc.yml b/soc/renesas/rzt2m/soc.yml
deleted file mode 100644
index 35c7cc27f77..00000000000
--- a/soc/renesas/rzt2m/soc.yml
+++ /dev/null
@@ -1,2 +0,0 @@
-socs:
-  - name: renesas_rzt2m
diff --git a/soc/renesas/smartbond/da1469x/Kconfig.defconfig b/soc/renesas/smartbond/da1469x/Kconfig.defconfig
index 23735aae1f4..062a40c0e4c 100644
--- a/soc/renesas/smartbond/da1469x/Kconfig.defconfig
+++ b/soc/renesas/smartbond/da1469x/Kconfig.defconfig
@@ -22,9 +22,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config SYS_CLOCK_TICKS_PER_SEC
 	default $(dt_node_int_prop_int,$(DT_CLOCK_SRC_PATH),clock-frequency) if SMARTBOND_TIMER
 
-config SRAM_VECTOR_TABLE
-	default y
-
 config USE_DT_CODE_PARTITION
 	default y if MCUBOOT
 
diff --git a/soc/renesas/smartbond/da1469x/Kconfig.soc b/soc/renesas/smartbond/da1469x/Kconfig.soc
index b52b2905936..748db2d2c46 100644
--- a/soc/renesas/smartbond/da1469x/Kconfig.soc
+++ b/soc/renesas/smartbond/da1469x/Kconfig.soc
@@ -13,6 +13,12 @@ config SOC_DA14695
 	help
 	  DA14695
 
+config SOC_DA14697
+	bool
+	select SOC_SERIES_DA1469X
+	help
+	  DA14697
+
 config SOC_DA14699
 	bool
 	select SOC_SERIES_DA1469X
@@ -24,4 +30,5 @@ config SOC_SERIES
 
 config SOC
 	default "da14695" if SOC_DA14695
+	default "da14697" if SOC_DA14697
 	default "da14699" if SOC_DA14699
diff --git a/soc/renesas/smartbond/soc.yml b/soc/renesas/smartbond/soc.yml
index ee32857c5b7..34e9a0da302 100644
--- a/soc/renesas/smartbond/soc.yml
+++ b/soc/renesas/smartbond/soc.yml
@@ -4,4 +4,5 @@ family:
       - name: da1469x
         socs:
           - name: da14695
+          - name: da14697
           - name: da14699
diff --git a/soc/rockchip/rk35/CMakeLists.txt b/soc/rockchip/rk35/CMakeLists.txt
new file mode 100644
index 00000000000..b45e8592a61
--- /dev/null
+++ b/soc/rockchip/rk35/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright 2024 Université Gustave Eiffel
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_SOC_RK3568)
+  add_subdirectory(rk3568)
+elseif(CONFIG_SOC_RK3588S)
+  add_subdirectory(rk3588s)
+endif()
diff --git a/soc/rockchip/rk35/Kconfig b/soc/rockchip/rk35/Kconfig
new file mode 100644
index 00000000000..80f0d67eb4d
--- /dev/null
+++ b/soc/rockchip/rk35/Kconfig
@@ -0,0 +1,11 @@
+#
+# Copyright 2021 Huawei France Technologies SASU
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_FAMILY_ROCKCHIP
+
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_ROCKCHIP
diff --git a/soc/rockchip/rk35/Kconfig.defconfig b/soc/rockchip/rk35/Kconfig.defconfig
new file mode 100644
index 00000000000..122e92dc999
--- /dev/null
+++ b/soc/rockchip/rk35/Kconfig.defconfig
@@ -0,0 +1,11 @@
+#
+# Copyright 2021 Huawei France Technologies SASU
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_FAMILY_ROCKCHIP
+
+rsource "*/Kconfig.defconfig"
+
+endif
diff --git a/soc/rockchip/rk35/Kconfig.soc b/soc/rockchip/rk35/Kconfig.soc
new file mode 100644
index 00000000000..5c3276841f8
--- /dev/null
+++ b/soc/rockchip/rk35/Kconfig.soc
@@ -0,0 +1,11 @@
+# Copyright 2024 Université Gustave Eiffel
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_RK35
+	bool
+	select SOC_FAMILY_ROCKCHIP
+
+config SOC_SERIES
+	default "rk35" if SOC_SERIES_RK35
+
+rsource "*/Kconfig.soc"
diff --git a/soc/rockchip/rk3568/CMakeLists.txt b/soc/rockchip/rk35/rk3568/CMakeLists.txt
similarity index 100%
rename from soc/rockchip/rk3568/CMakeLists.txt
rename to soc/rockchip/rk35/rk3568/CMakeLists.txt
diff --git a/soc/rockchip/rk35/rk3568/Kconfig b/soc/rockchip/rk35/rk3568/Kconfig
new file mode 100644
index 00000000000..e29f96c8c77
--- /dev/null
+++ b/soc/rockchip/rk35/rk3568/Kconfig
@@ -0,0 +1,11 @@
+# Copyright 2022 HNU-ESNL
+# Copyright 2022 openEuler SIG-Zephyr
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_RK3568
+	select ARM64
+	select CPU_CORTEX_A55
+	select ARM_ARCH_TIMER
+
+config SOC_PART_NUMBER
+	default "RK3568" if SOC_RK3568
diff --git a/soc/rockchip/rk35/rk3568/Kconfig.defconfig b/soc/rockchip/rk35/rk3568/Kconfig.defconfig
new file mode 100644
index 00000000000..28b62874a3d
--- /dev/null
+++ b/soc/rockchip/rk35/rk3568/Kconfig.defconfig
@@ -0,0 +1,9 @@
+# Copyright 2022 HNU-ESNL
+# Copyright 2022 openEuler SIG-Zephyr
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_RK3568
+
+rsource "Kconfig.defconfig.rk3568"
+
+endif # SOC_SERIES_RK3568
diff --git a/soc/rockchip/rk3568/Kconfig.defconfig.rk3568 b/soc/rockchip/rk35/rk3568/Kconfig.defconfig.rk3568
similarity index 100%
rename from soc/rockchip/rk3568/Kconfig.defconfig.rk3568
rename to soc/rockchip/rk35/rk3568/Kconfig.defconfig.rk3568
diff --git a/soc/rockchip/rk35/rk3568/Kconfig.soc b/soc/rockchip/rk35/rk3568/Kconfig.soc
new file mode 100644
index 00000000000..1acf4d0ffe4
--- /dev/null
+++ b/soc/rockchip/rk35/rk3568/Kconfig.soc
@@ -0,0 +1,10 @@
+# Copyright 2022 HNU-ESNL
+# Copyright 2022 openEuler SIG-Zephyr
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_RK3568
+	bool
+	select SOC_SERIES_RK35
+
+config SOC
+	default "rk3568" if SOC_RK3568
diff --git a/soc/rockchip/rk3568/mmu_regions.c b/soc/rockchip/rk35/rk3568/mmu_regions.c
similarity index 100%
rename from soc/rockchip/rk3568/mmu_regions.c
rename to soc/rockchip/rk35/rk3568/mmu_regions.c
diff --git a/soc/rockchip/rk35/rk3588s/CMakeLists.txt b/soc/rockchip/rk35/rk3588s/CMakeLists.txt
new file mode 100644
index 00000000000..667a960e91b
--- /dev/null
+++ b/soc/rockchip/rk35/rk3588s/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright 2024 Université Gustave Eiffel
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources_ifdef(CONFIG_ARM_MMU mmu_regions.c)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/rockchip/rk35/rk3588s/Kconfig b/soc/rockchip/rk35/rk3588s/Kconfig
new file mode 100644
index 00000000000..edd700a9a9e
--- /dev/null
+++ b/soc/rockchip/rk35/rk3588s/Kconfig
@@ -0,0 +1,10 @@
+# Copyright 2024 Université Gustave Eiffel
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_RK3588S
+	select ARM64
+	select CPU_CORTEX_A55
+	select ARM_ARCH_TIMER if SYS_CLOCK_EXISTS
+
+config SOC_PART_NUMBER
+	default "RK3588S" if SOC_RK3588S
diff --git a/soc/rockchip/rk35/rk3588s/Kconfig.defconfig b/soc/rockchip/rk35/rk3588s/Kconfig.defconfig
new file mode 100644
index 00000000000..f056f362aac
--- /dev/null
+++ b/soc/rockchip/rk35/rk3588s/Kconfig.defconfig
@@ -0,0 +1,8 @@
+# Copyright 2024 Université Gustave Eiffel
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_RK3588S
+
+rsource "Kconfig.defconfig.rk3588s"
+
+endif # SOC_RK3588S
diff --git a/soc/rockchip/rk35/rk3588s/Kconfig.defconfig.rk3588s b/soc/rockchip/rk35/rk3588s/Kconfig.defconfig.rk3588s
new file mode 100644
index 00000000000..fe40d788468
--- /dev/null
+++ b/soc/rockchip/rk35/rk3588s/Kconfig.defconfig.rk3588s
@@ -0,0 +1,19 @@
+# Copyright 2024 Université Gustave Eiffel
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_RK3588S
+
+config NUM_IRQS
+	default 544
+
+config FLASH_SIZE
+	default 0
+
+config FLASH_BASE_ADDRESS
+	default 0
+
+config UART_NS16550_ACCESS_WORD_ONLY
+	default y
+	depends on UART_NS16550
+
+endif
diff --git a/soc/rockchip/rk35/rk3588s/Kconfig.soc b/soc/rockchip/rk35/rk3588s/Kconfig.soc
new file mode 100644
index 00000000000..3dcf0bc6e81
--- /dev/null
+++ b/soc/rockchip/rk35/rk3588s/Kconfig.soc
@@ -0,0 +1,9 @@
+# Copyright 2024 Université Gustave Eiffel
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_RK3588S
+	bool
+	select SOC_SERIES_RK35
+
+config SOC
+	default "rk3588s" if SOC_RK3588S
diff --git a/soc/rockchip/rk35/rk3588s/mmu_regions.c b/soc/rockchip/rk35/rk3588s/mmu_regions.c
new file mode 100644
index 00000000000..f33dce56c63
--- /dev/null
+++ b/soc/rockchip/rk35/rk3588s/mmu_regions.c
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2024 Université Gustave Eiffel
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/devicetree.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/arch/arm64/arm_mmu.h>
+
+static const struct arm_mmu_region mmu_regions[] = {
+
+	MMU_REGION_FLAT_ENTRY("GIC",
+			      DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 0),
+			      DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 0),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
+
+	MMU_REGION_FLAT_ENTRY("GIC",
+			      DT_REG_ADDR_BY_IDX(DT_INST(0, arm_gic), 1),
+			      DT_REG_SIZE_BY_IDX(DT_INST(0, arm_gic), 1),
+			      MT_DEVICE_nGnRnE | MT_P_RW_U_NA | MT_DEFAULT_SECURE_STATE),
+};
+
+const struct arm_mmu_config mmu_config = {
+	.num_regions = ARRAY_SIZE(mmu_regions),
+	.mmu_regions = mmu_regions,
+};
diff --git a/soc/rockchip/rk3568/Kconfig b/soc/rockchip/rk3568/Kconfig
deleted file mode 100644
index b5b046b0430..00000000000
--- a/soc/rockchip/rk3568/Kconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-# Copyright 2022 HNU-ESNL
-# Copyright 2022 openEuler SIG-Zephyr
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_RK3568
-	select ARM64
-	select CPU_CORTEX_A55
-	select ARM_ARCH_TIMER
-
-config SOC_PART_NUMBER
-	default "RK3568" if SOC_SERIES_RK3568
diff --git a/soc/rockchip/rk3568/Kconfig.defconfig b/soc/rockchip/rk3568/Kconfig.defconfig
deleted file mode 100644
index b7f52249abe..00000000000
--- a/soc/rockchip/rk3568/Kconfig.defconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright 2022 HNU-ESNL
-# Copyright 2022 openEuler SIG-Zephyr
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_SERIES_RK3568
-
-rsource "Kconfig.defconfig.rk3568"
-
-endif # SOC_SERIES_RK3568
diff --git a/soc/rockchip/rk3568/Kconfig.soc b/soc/rockchip/rk3568/Kconfig.soc
deleted file mode 100644
index 7d965d764cb..00000000000
--- a/soc/rockchip/rk3568/Kconfig.soc
+++ /dev/null
@@ -1,17 +0,0 @@
-# Copyright 2022 HNU-ESNL
-# Copyright 2022 openEuler SIG-Zephyr
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_RK3568
-	bool
-	select SOC_FAMILY_ROCKCHIP
-
-config SOC_RK3568
-	bool
-	select SOC_SERIES_RK3568
-
-config SOC
-	default "rk3568" if SOC_RK3568
-
-config SOC_SERIES
-	default "rk3568" if SOC_RK3568
diff --git a/soc/rockchip/soc.yml b/soc/rockchip/soc.yml
index 5568a11aa49..777bd05a9d3 100644
--- a/soc/rockchip/soc.yml
+++ b/soc/rockchip/soc.yml
@@ -4,6 +4,7 @@ family:
       - name: rk3399
         socs:
           - name: rk3399
-      - name: rk3568
+      - name: rk35
         socs:
+          - name: rk3588s
           - name: rk3568
diff --git a/soc/silabs/CMakeLists.txt b/soc/silabs/CMakeLists.txt
index d173ecfec66..bce90b74766 100644
--- a/soc/silabs/CMakeLists.txt
+++ b/soc/silabs/CMakeLists.txt
@@ -1,8 +1,11 @@
 # SPDX-License-Identifier: Apache-2.0
 # Copyright (c) 2017 Christian Taedcke
 
-add_subdirectory(common)
+zephyr_include_directories(${SOC_FAMILY})
 zephyr_include_directories(${SOC_FAMILY}/${SOC_SERIES})
 
-add_subdirectory_ifdef(CONFIG_SOC_FAMILY_SILABS_S2 silabs_s2)
-add_subdirectory_ifdef(CONFIG_SOC_SERIES_SIM3U silabs_sim3/sim3u)
+add_subdirectory(common)
+
+add_subdirectory_ifdef(CONFIG_SOC_FAMILY_SILABS_S2      silabs_s2)
+add_subdirectory_ifdef(CONFIG_SOC_FAMILY_SILABS_SIWX91X silabs_siwx91x)
+add_subdirectory_ifdef(CONFIG_SOC_SERIES_SIM3U          silabs_sim3/sim3u)
diff --git a/soc/silabs/Kconfig b/soc/silabs/Kconfig
index dbdda491926..dcf8de541c6 100644
--- a/soc/silabs/Kconfig
+++ b/soc/silabs/Kconfig
@@ -23,6 +23,11 @@ config SOC_GECKO_CORE
 	help
 	  Set if the Core interrupt handling (CORE) HAL module is used.
 
+config SOC_SILABS_ACMP
+	bool
+	help
+	  Set if the Analog comparator (ACMP) HAL module is used.
+
 config SOC_GECKO_ADC
 	bool
 	help
@@ -129,7 +134,7 @@ config SOC_GECKO_TRNG
 config SOC_SILABS_SLEEPTIMER
 	bool
 	select SOC_GECKO_PRS
-	select SOC_GECKO_RTCC if SOC_SERIES_EFR32BG22 || SOC_SERIES_EFR32BG27 || SOC_SERIES_EFR32MG21
+	select SOC_GECKO_RTCC if SOC_FAMILY_SILABS_S2 && $(dt_nodelabel_enabled,rtcc0)
 	help
 	  Set if the Sleeptimer HAL module is used.
 
diff --git a/soc/silabs/Kconfig.defconfig b/soc/silabs/Kconfig.defconfig
index 5c55a394c68..aaf363576f8 100644
--- a/soc/silabs/Kconfig.defconfig
+++ b/soc/silabs/Kconfig.defconfig
@@ -19,4 +19,7 @@ config CORTEX_M_SYSTICK
 config IDLE_STACK_SIZE
 	default 512 if SOC_GECKO_PM_BACKEND_PMGR
 
+configdefault NUM_METAIRQ_PRIORITIES
+	default 1 if BT_SILABS_EFR32
+
 endif
diff --git a/soc/silabs/Kconfig.soc b/soc/silabs/Kconfig.soc
index 7b1174c6864..099b50d751d 100644
--- a/soc/silabs/Kconfig.soc
+++ b/soc/silabs/Kconfig.soc
@@ -5,6 +5,7 @@ config SOC_FAMILY
 	default "silabs_s0" if SOC_FAMILY_SILABS_S0
 	default "silabs_s1" if SOC_FAMILY_SILABS_S1
 	default "silabs_s2" if SOC_FAMILY_SILABS_S2
+	default "silabs_siwx91x" if SOC_FAMILY_SILABS_SIWX91X
 	default "silabs_sim3" if SOC_FAMILY_SILABS_SIM3
 
 rsource "*/Kconfig.soc"
diff --git a/soc/silabs/common/pinctrl_soc.h b/soc/silabs/common/pinctrl_soc.h
index 82592eafcf5..079c056c636 100644
--- a/soc/silabs/common/pinctrl_soc.h
+++ b/soc/silabs/common/pinctrl_soc.h
@@ -73,14 +73,33 @@ typedef struct pinctrl_soc_pin {
 	 .en_bit =                                                                                 \
 		 (FIELD_GET(SILABS_PINCTRL_HAVE_EN_MASK, DT_PROP_BY_IDX(node, prop, idx))          \
 			  ? FIELD_GET(SILABS_PINCTRL_EN_BIT_MASK, DT_PROP_BY_IDX(node, prop, idx)) \
-			  : 0xFF),                                                                 \
-	 .route_offset = FIELD_GET(SILABS_PINCTRL_ROUTE_MASK, DT_PROP_BY_IDX(node, prop, idx)),    \
+			  : SILABS_PINCTRL_UNUSED),                                                \
+	 .route_offset =                                                                           \
+		 (FIELD_GET(SILABS_PINCTRL_HAVE_ROUTE_MASK, DT_PROP_BY_IDX(node, prop, idx))       \
+			  ? FIELD_GET(SILABS_PINCTRL_ROUTE_MASK, DT_PROP_BY_IDX(node, prop, idx))  \
+			  : SILABS_PINCTRL_UNUSED),                                                \
 	 .mode = Z_PINCTRL_SILABS_MODE_INIT(node),                                                 \
 	 .dout = Z_PINCTRL_SILABS_DOUT_INIT(node)},
 
+#define Z_PINCTRL_STATE_ABUS_INIT(node, prop, idx)                                                 \
+	{                                                                                          \
+		.base_offset =                                                                     \
+			FIELD_GET(SILABS_PINCTRL_ABUS_BUS_MASK, DT_PROP_BY_IDX(node, prop, idx)),  \
+		.route_offset = FIELD_GET(SILABS_PINCTRL_ABUS_PERIPH_MASK,                         \
+					  DT_PROP_BY_IDX(node, prop, idx)),                        \
+		.en_bit = SILABS_PINCTRL_ANALOG,                                                   \
+		.mode = FIELD_GET(SILABS_PINCTRL_ABUS_PARITY_MASK,                                 \
+				  DT_PROP_BY_IDX(node, prop, idx)),                                \
+	},
+
+#define Z_PINCTRL_SILABS_DISPATCH(group)                                                           \
+	IF_ENABLED(DT_NODE_HAS_PROP(group, pins),                                                  \
+		   (DT_FOREACH_PROP_ELEM(group, pins, Z_PINCTRL_STATE_PIN_INIT)))                  \
+	IF_ENABLED(DT_NODE_HAS_PROP(group, silabs_analog_bus),                                     \
+		   (DT_FOREACH_PROP_ELEM(group, silabs_analog_bus, Z_PINCTRL_STATE_ABUS_INIT)))
+
 #define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)                                                   \
-	{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pins,             \
-				Z_PINCTRL_STATE_PIN_INIT)}
+	{DT_FOREACH_CHILD(DT_PHANDLE(node_id, prop), Z_PINCTRL_SILABS_DISPATCH)}
 
 #else
 
diff --git a/soc/silabs/common/soc_power_pmgr.c b/soc/silabs/common/soc_power_pmgr.c
index 1980c95a56b..402701c1c23 100644
--- a/soc/silabs/common/soc_power_pmgr.c
+++ b/soc/silabs/common/soc_power_pmgr.c
@@ -8,6 +8,8 @@
 #include <zephyr/logging/log.h>
 #include <zephyr/pm/pm.h>
 #include <sl_power_manager.h>
+#include <sl_hfxo_manager.h>
+#include <sli_hfxo_manager.h>
 
 LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
 
@@ -46,31 +48,25 @@ void pm_state_set(enum pm_state state, uint8_t substate_id)
 		break;
 	}
 
-	/* FIXME: When this function is entered the Kernel has disabled
-	 * interrupts using BASEPRI register. This is incorrect as it prevents
-	 * waking up from any interrupt which priority is not 0. Work around the
-	 * issue and disable interrupts using PRIMASK register as recommended
-	 * by ARM.
-	 */
-
-	/* Set PRIMASK */
-	__disable_irq();
-	/* Set BASEPRI to 0 */
-	irq_unlock(0);
-
 	LOG_DBG("Entry to energy mode %d", energy_mode);
 
-	if (energy_mode != SL_POWER_MANAGER_EM0) {
+	if (energy_mode == SL_POWER_MANAGER_EM4) {
+		sl_power_manager_enter_em4();
+	} else if (energy_mode != SL_POWER_MANAGER_EM0) {
+		/* Calling the tracing and hook functions provided in arch_cpu_idle(). */
+#if defined(CONFIG_TRACING)
+		sys_trace_idle();
+#endif
+#if CONFIG_ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK
+		z_arm_on_enter_cpu_idle_prepare();
+#endif
+
 		sl_power_manager_add_em_requirement(energy_mode);
 		sl_power_manager_sleep();
-		k_cpu_idle();
 		sl_power_manager_remove_em_requirement(energy_mode);
 	}
 
 	LOG_DBG("Exit from energy mode %d", energy_mode);
-
-	/* Clear PRIMASK */
-	__enable_irq();
 }
 
 void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
@@ -79,6 +75,33 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 	ARG_UNUSED(substate_id);
 }
 
+/* This function is called by sl_power_manager_sleep() after it has set the PRIMASK. */
+bool sl_power_manager_is_ok_to_sleep(void)
+{
+	/* FIXME: When this function is entered the Kernel has disabled
+	 * interrupts using BASEPRI register. This is incorrect as it prevents
+	 * waking up from any interrupt which priority is not 0. Work around the
+	 * issue and disable interrupts using PRIMASK register as recommended
+	 * by ARM.
+	 */
+	/* Set BASEPRI to 0. */
+	irq_unlock(0);
+
+	return true;
+}
+
+/* This function is called by sl_power_manager_sleep() right after it was woken up from WFI. */
+void sli_power_manager_on_wakeup(void)
+{
+#if defined(HFXO_MANAGER_SLEEPTIMER_SYSRTC_INTEGRATION_ON)
+	/* Handle the HFXO IRQ as soon as possible to retrieve the startup time. */
+	sl_hfxo_manager_irq_handler();
+#endif
+	/* Forces a clock restore before handling interrupts. */
+	sl_power_manager_add_em_requirement(SL_POWER_MANAGER_EM1);
+	sl_power_manager_remove_em_requirement(SL_POWER_MANAGER_EM1);
+}
+
 /**
  * Some SiLabs blobs, such as RAIL, call directly into sl_power_manager, and
  * for that they had to include sl_power_manager.h during build. Some of those
diff --git a/soc/silabs/silabs_s2/Kconfig.defconfig b/soc/silabs/silabs_s2/Kconfig.defconfig
index d7dec5deb3d..339b1df6778 100644
--- a/soc/silabs/silabs_s2/Kconfig.defconfig
+++ b/soc/silabs/silabs_s2/Kconfig.defconfig
@@ -5,17 +5,32 @@ rsource "*/Kconfig.defconfig"
 
 if SOC_FAMILY_SILABS_S2
 
-config SYS_CLOCK_HW_CYCLES_PER_SEC
+configdefault SYS_CLOCK_HW_CYCLES_PER_SEC
 	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if CORTEX_M_SYSTICK
 	default 32768
 
-config SYS_CLOCK_TICKS_PER_SEC
-	default 1024 if SILABS_SLEEPTIMER_TIMER || GECKO_BURTC_TIMER
+configdefault SYS_CLOCK_TICKS_PER_SEC
+	default 128 if !TICKLESS_KERNEL && (SILABS_SLEEPTIMER_TIMER || GECKO_BURTC_TIMER)
+	default 32768 if SILABS_SLEEPTIMER_TIMER
+	default 1024 if GECKO_BURTC_TIMER
 
-config SILABS_SLEEPTIMER_TIMER
+configdefault SILABS_SLEEPTIMER_TIMER
 	default y
 
-config CORTEX_M_SYSTICK
+configdefault CORTEX_M_SYSTICK
 	default n if SILABS_SLEEPTIMER_TIMER || GECKO_BURTC_TIMER
 
+# silabs_s2 uses simplicity_sdk hal library, which already have by default a zero latency
+# IRQs mechanism with a hardcoded value. In order to be aligned with simplicity_sdk, we
+# need to activate Zero Latency IRQ in Zephyr by default. The level (2) depends on the
+# hardcoded value in simplicity_sdk (CORE_ATOMIC_BASE_PRIORITY_LEVEL). Without this config,
+# if you use an IRQ with a priority of 0 or 1, irq_lock() and irq_unlock() have no effect
+# over this IRQ.
+
+configdefault ZERO_LATENCY_IRQS
+	default y
+
+configdefault ZERO_LATENCY_LEVELS
+	default 2
+
 endif
diff --git a/soc/silabs/silabs_s2/efr32bg22/Kconfig b/soc/silabs/silabs_s2/efr32bg22/Kconfig
index fcecbbbc3e8..5ac51ff898a 100644
--- a/soc/silabs/silabs_s2/efr32bg22/Kconfig
+++ b/soc/silabs/silabs_s2/efr32bg22/Kconfig
@@ -9,7 +9,7 @@ config SOC_SERIES_EFR32BG22
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_ARM_SAU
 	select CPU_HAS_FPU
-	select HAS_SILABS_GECKO
+	select HAS_SILABS_SISDK
 	select HAS_SWO
 	select SOC_GECKO_HAS_RADIO
 	select SOC_GECKO_GPIO
diff --git a/soc/silabs/silabs_s2/efr32bg22/soc.h b/soc/silabs/silabs_s2/efr32bg22/soc.h
deleted file mode 100644
index 7591b111ad2..00000000000
--- a/soc/silabs/silabs_s2/efr32bg22/soc.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2021 Sateesh Kotapati
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief Register access macros for the EFR32BG22 SoC
- *
- */
-
-#ifndef EFR32BG22_SOC_H_
-#define EFR32BG22_SOC_H_
-
-#ifndef _ASMLANGUAGE
-
-#include <em_common.h>
-#include "../common/soc_gpio.h"
-
-#endif /* !_ASMLANGUAGE */
-
-#endif /* EFR32BG22_SOC_H_ */
diff --git a/soc/silabs/silabs_s2/efr32bg27/Kconfig b/soc/silabs/silabs_s2/efr32bg27/Kconfig
index 7431fbecb68..36353d04504 100644
--- a/soc/silabs/silabs_s2/efr32bg27/Kconfig
+++ b/soc/silabs/silabs_s2/efr32bg27/Kconfig
@@ -9,7 +9,7 @@ config SOC_SERIES_EFR32BG27
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_ARM_SAU
 	select CPU_HAS_FPU
-	select HAS_SILABS_GECKO
+	select HAS_SILABS_SISDK
 	select HAS_SWO
 	select SOC_GECKO_HAS_RADIO
 	select SOC_GECKO_CMU
diff --git a/soc/silabs/silabs_s2/efr32bg27/soc.h b/soc/silabs/silabs_s2/efr32bg27/soc.h
deleted file mode 100644
index b1974d02c00..00000000000
--- a/soc/silabs/silabs_s2/efr32bg27/soc.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright (c) 2023 Antmicro <www.antmicro.com>
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief Register access macros for the EFR32BG27 SoC
- */
-
-#ifndef EFR32BG27_SOC_H_
-#define EFR32BG27_SOC_H_
-
-#ifndef _ASMLANGUAGE
-#include <em_common.h>
-#include "../common/soc_gpio.h"
-#endif /* _ASMLANGUAGE */
-
-#endif /* EFR32BG27_SOC_H_ */
diff --git a/soc/silabs/silabs_s2/efr32mg21/Kconfig b/soc/silabs/silabs_s2/efr32mg21/Kconfig
index db3f7e6ae66..0cbeb648461 100644
--- a/soc/silabs/silabs_s2/efr32mg21/Kconfig
+++ b/soc/silabs/silabs_s2/efr32mg21/Kconfig
@@ -11,7 +11,7 @@ config SOC_SERIES_EFR32MG21
 	select CPU_HAS_ARM_MPU
 	select CPU_HAS_ARM_SAU
 	select SOC_GECKO_HAS_RADIO
-	select HAS_SILABS_GECKO
+	select HAS_SILABS_SISDK
 	select HAS_SWO
 	select SOC_GECKO_CMU
 	select SOC_GECKO_EMU
diff --git a/soc/silabs/silabs_s2/efr32mg21/soc.h b/soc/silabs/silabs_s2/efr32mg21/soc.h
deleted file mode 100644
index 90b93a0acd1..00000000000
--- a/soc/silabs/silabs_s2/efr32mg21/soc.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (c) 2020 TriaGnoSys GmbH
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief Board configuration macros for the EFR32MG21 SoC
- *
- */
-
-#ifndef _SILABS_EFR32MG21_SOC_H
-#define _SILABS_EFR32MG21_SOC_H
-
-#include <zephyr/sys/util.h>
-
-#ifndef _ASMLANGUAGE
-
-#include <em_common.h>
-
-#include "soc_pinmap.h"
-#include "../common/soc_gpio.h"
-
-
-#endif  /* !_ASMLANGUAGE */
-
-#endif  /* _SILABS_EFR32MG21_SOC_H */
diff --git a/soc/silabs/silabs_s2/efr32mg24/Kconfig b/soc/silabs/silabs_s2/efr32mg24/Kconfig
index 1412bc95629..8b8df640a8b 100644
--- a/soc/silabs/silabs_s2/efr32mg24/Kconfig
+++ b/soc/silabs/silabs_s2/efr32mg24/Kconfig
@@ -11,7 +11,7 @@ config SOC_SERIES_EFR32MG24
 	select ARMV8_M_DSP
 	select ARM_TRUSTZONE_M
 	select SOC_GECKO_HAS_RADIO
-	select HAS_SILABS_GECKO
+	select HAS_SILABS_SISDK
 	select HAS_SWO
 	select SOC_GECKO_CMU
 	select SOC_GECKO_EMU
diff --git a/soc/silabs/silabs_s2/efr32mg24/soc.h b/soc/silabs/silabs_s2/efr32mg24/soc.h
deleted file mode 100644
index 210526c1109..00000000000
--- a/soc/silabs/silabs_s2/efr32mg24/soc.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright (c) 2020 TriaGnoSys GmbH
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief Board configuration macros for the EFR32MG24 SoC
- *
- */
-
-#ifndef _SILABS_EFR32MG24_SOC_H
-#define _SILABS_EFR32MG24_SOC_H
-
-#include <zephyr/sys/util.h>
-
-#ifndef _ASMLANGUAGE
-
-#include <em_common.h>
-
-#include "soc_pinmap.h"
-#include "../common/soc_gpio.h"
-
-/* Add include for DTS generated information */
-#include <zephyr/devicetree.h>
-
-#endif  /* !_ASMLANGUAGE */
-
-#endif  /* _SILABS_EFR32MG24_SOC_H */
diff --git a/soc/silabs/silabs_s2/efr32zg23/Kconfig b/soc/silabs/silabs_s2/efr32zg23/Kconfig
index 647c52363dc..1e645eb8d23 100644
--- a/soc/silabs/silabs_s2/efr32zg23/Kconfig
+++ b/soc/silabs/silabs_s2/efr32zg23/Kconfig
@@ -11,7 +11,7 @@ config SOC_SERIES_EFR32ZG23
 	select CPU_HAS_ARM_SAU
 	select CPU_HAS_FPU
 	select HAS_PM
-	select HAS_SILABS_GECKO
+	select HAS_SILABS_SISDK
 	select HAS_SWO
 	select SOC_GECKO_CMU
 	select SOC_GECKO_CORE
diff --git a/soc/silabs/silabs_s2/efr32zg23/soc.h b/soc/silabs/silabs_s2/efr32zg23/soc.h
deleted file mode 100644
index 21722ac056d..00000000000
--- a/soc/silabs/silabs_s2/efr32zg23/soc.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright (c) 2024 Yishai Jaffe
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/**
- * @file
- * @brief Register access macros for the EFR32ZG23 SoC
- *
- */
-
-#ifndef EFR32ZG23_SOC_H_
-#define EFR32ZG23_SOC_H_
-
-#ifndef _ASMLANGUAGE
-
-#include <em_common.h>
-#include "../common/soc_gpio.h"
-
-#endif /* !_ASMLANGUAGE */
-
-#endif /* EFR32ZG23_SOC_H_ */
diff --git a/soc/silabs/silabs_s2/soc.h b/soc/silabs/silabs_s2/soc.h
new file mode 100644
index 00000000000..9933938e09f
--- /dev/null
+++ b/soc/silabs/silabs_s2/soc.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Register access macros for Silabs Series 2 SoCs
+ *
+ */
+
+#ifndef SILABS_S2_SOC_H_
+#define SILABS_S2_SOC_H_
+
+#ifndef _ASMLANGUAGE
+#include <em_common.h>
+#endif
+
+#endif
diff --git a/soc/silabs/silabs_s2/xg29/Kconfig b/soc/silabs/silabs_s2/xg29/Kconfig
new file mode 100644
index 00000000000..19f99079c17
--- /dev/null
+++ b/soc/silabs/silabs_s2/xg29/Kconfig
@@ -0,0 +1,43 @@
+# Copyright (c) 2025 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_EFR32BG29
+	select ARM
+	select CPU_CORTEX_M33
+	select CPU_HAS_FPU
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_ARM_SAU
+	select CPU_CORTEX_M_HAS_DWT
+	select ARMV8_M_DSP
+	select ARM_TRUSTZONE_M
+	select SOC_GECKO_HAS_RADIO
+	select HAS_SILABS_SISDK
+	select HAS_SWO
+	select SOC_GECKO_CMU
+	select SOC_GECKO_EMU
+	select SOC_GECKO_GPIO
+	select SOC_GECKO_DEV_INIT
+	select SOC_GECKO_SE
+	select HAS_PM
+
+config SOC_SERIES_EFR32MG29
+	select ARM
+	select CPU_CORTEX_M33
+	select CPU_HAS_FPU
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_ARM_SAU
+	select CPU_CORTEX_M_HAS_DWT
+	select ARMV8_M_DSP
+	select ARM_TRUSTZONE_M
+	select SOC_GECKO_HAS_RADIO
+	select HAS_SILABS_SISDK
+	select HAS_SWO
+	select SOC_GECKO_CMU
+	select SOC_GECKO_EMU
+	select SOC_GECKO_GPIO
+	select SOC_GECKO_DEV_INIT
+	select SOC_GECKO_SE
+	select HAS_PM
+
+config SOC_GECKO_SDID
+	default 240 if SOC_SERIES_EFR32BG29 || SOC_SERIES_EFR32MG29
diff --git a/soc/silabs/silabs_s2/xg29/Kconfig.defconfig b/soc/silabs/silabs_s2/xg29/Kconfig.defconfig
new file mode 100644
index 00000000000..84949e8912c
--- /dev/null
+++ b/soc/silabs/silabs_s2/xg29/Kconfig.defconfig
@@ -0,0 +1,19 @@
+# Copyright (c) 2025 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_EFR32BG29 || SOC_SERIES_EFR32MG29
+
+config NUM_IRQS
+	# must be >= the highest interrupt number used
+	default 70
+
+config PM
+	default n
+	select UART_INTERRUPT_DRIVEN if SERIAL_SUPPORT_INTERRUPT
+
+choice PM_POLICY
+	default PM_POLICY_DEFAULT
+	depends on PM
+endchoice
+
+endif
diff --git a/soc/silabs/silabs_s2/xg29/Kconfig.soc b/soc/silabs/silabs_s2/xg29/Kconfig.soc
new file mode 100644
index 00000000000..f17bd7e5033
--- /dev/null
+++ b/soc/silabs/silabs_s2/xg29/Kconfig.soc
@@ -0,0 +1,58 @@
+# Copyright (c) 2025 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_EFR32BG29
+	bool
+	select SOC_FAMILY_SILABS_S2
+	help
+	  Silicon Labs EFR32BG29 (Blue Gecko) Series MCU
+
+config SOC_SERIES_EFR32MG29
+	bool
+	select SOC_FAMILY_SILABS_S2
+	help
+	  Silicon Labs EFR32MG29 (Mighty Gecko) Series MCU
+
+config SOC_PART_NUMBER_EFR32BG29B140F1024IM40
+	bool
+	select SOC_SERIES_EFR32BG29
+
+config SOC_PART_NUMBER_EFR32BG29B220F1024CJ45
+	bool
+	select SOC_SERIES_EFR32BG29
+
+config SOC_PART_NUMBER_EFR32BG29B221F1024CJ45
+	bool
+	select SOC_SERIES_EFR32BG29
+
+config SOC_PART_NUMBER_EFR32BG29B230F1024CM40
+	bool
+	select SOC_SERIES_EFR32BG29
+
+config SOC_PART_NUMBER_EFR32MG29B140F1024IM40
+	bool
+	select SOC_SERIES_EFR32MG29
+
+config SOC_PART_NUMBER_EFR32MG29B230F1024CM40
+	bool
+	select SOC_SERIES_EFR32MG29
+
+config SOC_SERIES
+	default "efr32bg29" if SOC_SERIES_EFR32BG29
+	default "efr32mg29" if SOC_SERIES_EFR32MG29
+
+config SOC
+	default "efr32bg29b140f1024im40" if SOC_PART_NUMBER_EFR32BG29B140F1024IM40
+	default "efr32bg29b220f1024cj45" if SOC_PART_NUMBER_EFR32BG29B220F1024CJ45
+	default "efr32bg29b221f1024cj45" if SOC_PART_NUMBER_EFR32BG29B221F1024CJ45
+	default "efr32bg29b230f1024cm40" if SOC_PART_NUMBER_EFR32BG29B230F1024CM40
+	default "efr32mg29b140f1024im40" if SOC_PART_NUMBER_EFR32MG29B140F1024IM40
+	default "efr32mg29b230f1024cm40" if SOC_PART_NUMBER_EFR32MG29B230F1024CM40
+
+config SOC_PART_NUMBER
+	default "EFR32BG29B140F1024IM40" if SOC_PART_NUMBER_EFR32BG29B140F1024IM40
+	default "EFR32BG29B220F1024CJ45" if SOC_PART_NUMBER_EFR32BG29B220F1024CJ45
+	default "EFR32BG29B221F1024CJ45" if SOC_PART_NUMBER_EFR32BG29B221F1024CJ45
+	default "EFR32BG29B230F1024CM40" if SOC_PART_NUMBER_EFR32BG29B230F1024CM40
+	default "EFR32MG29B140F1024IM40" if SOC_PART_NUMBER_EFR32MG29B140F1024IM40
+	default "EFR32MG29B230F1024CM40" if SOC_PART_NUMBER_EFR32MG29B230F1024CM40
diff --git a/soc/silabs/silabs_siwx91x/CMakeLists.txt b/soc/silabs/silabs_siwx91x/CMakeLists.txt
new file mode 100644
index 00000000000..7e3a8c84a16
--- /dev/null
+++ b/soc/silabs/silabs_siwx91x/CMakeLists.txt
@@ -0,0 +1,14 @@
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(siwg917)
+
+# Necessary to not overwrite NWP Firmware
+math(EXPR FLASH_LOAD_ADDRESS "(${CONFIG_FLASH_BASE_ADDRESS}) + (${CONFIG_FLASH_LOAD_OFFSET})")
+
+set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+    COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/siwx91x_isp_prepare.py
+    --load-addr ${FLASH_LOAD_ADDRESS}
+    ${KERNEL_BIN_NAME}
+    ${KERNEL_BIN_NAME}.rps
+)
diff --git a/soc/silabs/silabs_siwx91x/Kconfig b/soc/silabs/silabs_siwx91x/Kconfig
new file mode 100644
index 00000000000..eb696d43d19
--- /dev/null
+++ b/soc/silabs/silabs_siwx91x/Kconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2023 Antmicro
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_SILABS_SIWX91X
+	select ARM
+	select CPU_CORTEX_M4
+	select CPU_HAS_FPU
+	select CPU_HAS_ARM_MPU
+	select HAS_SILABS_WISECONNECT
+	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
+
+config SOC_SILABS_SLEEPTIMER
+	bool
+	help
+	  The Sleeptimer HAL module is used for SIWX91X.
diff --git a/soc/silabs/silabs_siwx91x/Kconfig.defconfig b/soc/silabs/silabs_siwx91x/Kconfig.defconfig
new file mode 100644
index 00000000000..7485a175028
--- /dev/null
+++ b/soc/silabs/silabs_siwx91x/Kconfig.defconfig
@@ -0,0 +1,49 @@
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_SILABS_SIWX91X
+
+configdefault SILABS_SLEEPTIMER_TIMER
+	default y if PM
+
+configdefault CORTEX_M_SYSTICK
+	default n if SILABS_SLEEPTIMER_TIMER
+
+configdefault SYS_CLOCK_TICKS_PER_SEC
+	default 128 if !TICKLESS_KERNEL && SILABS_SLEEPTIMER_TIMER
+	default 1024 if SILABS_SLEEPTIMER_TIMER
+
+config WISECONNECT_NETWORK_STACK
+	bool
+	select CMSIS_RTOS_V2
+	select POLL
+	select DYNAMIC_THREAD
+	select THREAD_NAME
+	select THREAD_STACK_INFO
+	select THREAD_MONITOR
+	select INIT_STACKS
+
+if WISECONNECT_NETWORK_STACK
+
+# WiseConnect create threads with realtime priority. Default (10kHz) clock tick
+# prevent proper use of the system with these threads.
+config SYS_CLOCK_TICKS_PER_SEC
+	default 1024
+
+config NUM_PREEMPT_PRIORITIES
+	default 56
+
+config CMSIS_V2_THREAD_DYNAMIC_MAX_COUNT
+	default 2
+
+config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE
+	default 1024
+
+config CMSIS_V2_THREAD_MAX_STACK_SIZE
+	default 2048
+
+endif # WISECONNECT_NETWORK_STACK
+
+rsource "*/Kconfig.defconfig"
+
+endif # SOC_FAMILY_SILABS_SIWX91X
diff --git a/soc/silabs/silabs_siwx91x/Kconfig.soc b/soc/silabs/silabs_siwx91x/Kconfig.soc
new file mode 100644
index 00000000000..f615334d2e4
--- /dev/null
+++ b/soc/silabs/silabs_siwx91x/Kconfig.soc
@@ -0,0 +1,7 @@
+# Copyright (c) 2023 Antmicro
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_SILABS_SIWX91X
+	bool
+
+rsource "*/Kconfig.soc"
diff --git a/soc/silabs/silabs_siwx91x/siwg917/CMakeLists.txt b/soc/silabs/silabs_siwx91x/siwg917/CMakeLists.txt
new file mode 100644
index 00000000000..d49353f7781
--- /dev/null
+++ b/soc/silabs/silabs_siwx91x/siwg917/CMakeLists.txt
@@ -0,0 +1,7 @@
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources_ifdef(CONFIG_SOC_SERIES_SIWG917 soc.c)
+zephyr_sources_ifdef(CONFIG_WISECONNECT_NETWORK_STACK nwp.c)
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")
diff --git a/soc/silabs/silabs_siwx91x/siwg917/Kconfig b/soc/silabs/silabs_siwx91x/siwg917/Kconfig
new file mode 100644
index 00000000000..e9d4e75ff23
--- /dev/null
+++ b/soc/silabs/silabs_siwx91x/siwg917/Kconfig
@@ -0,0 +1,6 @@
+# Copyright (c) 2023 Antmicro
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_SIWG917
+	select SOC_EARLY_INIT_HOOK
diff --git a/soc/silabs/silabs_siwx91x/siwg917/Kconfig.defconfig b/soc/silabs/silabs_siwx91x/siwg917/Kconfig.defconfig
new file mode 100644
index 00000000000..9fa79429bcd
--- /dev/null
+++ b/soc/silabs/silabs_siwx91x/siwg917/Kconfig.defconfig
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_SIWG917
+
+config NUM_IRQS
+	default 99
+
+config BUILD_OUTPUT_HEX
+	default y
+
+endif
diff --git a/soc/silabs/silabs_siwx91x/siwg917/Kconfig.soc b/soc/silabs/silabs_siwx91x/siwg917/Kconfig.soc
new file mode 100644
index 00000000000..c5e89582184
--- /dev/null
+++ b/soc/silabs/silabs_siwx91x/siwg917/Kconfig.soc
@@ -0,0 +1,21 @@
+# Copyright (c) 2024 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_SIWG917
+	bool
+	select SOC_FAMILY_SILABS_SIWX91X
+	help
+	  SiWG917 Series MCU
+
+config SOC_PART_NUMBER_SIWG917M111MGTBA
+	bool
+	select SOC_SERIES_SIWG917
+
+config SOC_SERIES
+	default "siwg917" if SOC_SERIES_SIWG917
+
+config SOC
+	default "siwg917m111mgtba" if SOC_PART_NUMBER_SIWG917M111MGTBA
+
+config SOC_PART_NUMBER
+	default "SIWG917M111MGTBA" if SOC_PART_NUMBER_SIWG917M111MGTBA
diff --git a/soc/silabs/silabs_siwx91x/siwg917/linker.ld b/soc/silabs/silabs_siwx91x/siwg917/linker.ld
new file mode 100644
index 00000000000..b6e2b16cc91
--- /dev/null
+++ b/soc/silabs/silabs_siwx91x/siwg917/linker.ld
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2023 Antmicro
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/arch/arm/cortex_m/scripts/linker.ld>
+
+SECTIONS
+{
+	.common_tcm_code :
+	{
+		*(.common_tcm_code*)
+	} > FLASH
+}
diff --git a/soc/silabs/silabs_siwx91x/siwg917/nwp.c b/soc/silabs/silabs_siwx91x/siwg917/nwp.c
new file mode 100644
index 00000000000..3882fcf07fb
--- /dev/null
+++ b/soc/silabs/silabs_siwx91x/siwg917/nwp.c
@@ -0,0 +1,212 @@
+/**
+ * @file
+ * @brief Network Processor Initialization for SiWx91x.
+ *
+ * This file contains the initialization routine for the (ThreadArch) network processor
+ * on the SiWx91x platform. The component is responsible for setting up the necessary
+ * hardware and software components to enable network communication.
+ *
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/net/wifi.h>
+#include <zephyr/logging/log.h>
+
+#include "nwp.h"
+#include "sl_wifi_callback_framework.h"
+#ifdef CONFIG_BT_SILABS_SIWX91X
+#include "rsi_ble_common_config.h"
+#endif
+
+LOG_MODULE_REGISTER(siwx91x_nwp);
+
+BUILD_ASSERT(DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(196) ||
+	     DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(256) ||
+	     DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(320));
+
+int siwg91x_get_nwp_config(int wifi_oper_mode, sl_wifi_device_configuration_t *get_config)
+{
+	sl_wifi_device_configuration_t default_config = {
+		.band = SL_SI91X_WIFI_BAND_2_4GHZ,
+		.region_code = DEFAULT_REGION,
+		.boot_option = LOAD_NWP_FW,
+		.boot_config = {
+			.feature_bit_map = SL_SI91X_FEAT_SECURITY_OPEN | SL_SI91X_FEAT_WPS_DISABLE,
+			.tcp_ip_feature_bit_map = SL_SI91X_TCP_IP_FEAT_EXTENSION_VALID,
+			.custom_feature_bit_map = SL_SI91X_CUSTOM_FEAT_EXTENSION_VALID,
+			.ext_custom_feature_bit_map = SL_SI91X_EXT_FEAT_XTAL_CLK,
+		}
+	};
+	sl_si91x_boot_configuration_t *boot_config = &default_config.boot_config;
+
+	__ASSERT(get_config, "get_config cannot be NULL");
+
+	if (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(196)) {
+		boot_config->ext_custom_feature_bit_map |= SL_SI91X_EXT_FEAT_480K_M4SS_192K;
+	} else if (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(256)) {
+		boot_config->ext_custom_feature_bit_map |= SL_SI91X_EXT_FEAT_416K_M4SS_256K;
+	} else if (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(320)) {
+		boot_config->ext_custom_feature_bit_map |= SL_SI91X_EXT_FEAT_352K_M4SS_320K;
+	} else {
+		 k_panic();
+	}
+
+	if (wifi_oper_mode == SL_SI91X_CLIENT_MODE) {
+		boot_config->oper_mode = SL_SI91X_CLIENT_MODE;
+
+		if (IS_ENABLED(CONFIG_WIFI_SILABS_SIWX91X_ROAMING_USE_DEAUTH)) {
+			boot_config->custom_feature_bit_map |=
+				SL_SI91X_CUSTOM_FEAT_ROAM_WITH_DEAUTH_OR_NULL_DATA;
+		}
+
+		if (IS_ENABLED(CONFIG_WIFI_SILABS_SIWX91X) &&
+		    IS_ENABLED(CONFIG_BT_SILABS_SIWX91X)) {
+			boot_config->coex_mode = SL_SI91X_WLAN_BLE_MODE;
+		} else if (IS_ENABLED(CONFIG_WIFI_SILABS_SIWX91X)) {
+			boot_config->coex_mode = SL_SI91X_WLAN_ONLY_MODE;
+		} else if (IS_ENABLED(CONFIG_BT_SILABS_SIWX91X)) {
+			boot_config->coex_mode = SL_SI91X_BLE_MODE;
+		} else {
+			/*
+			 * Even if neither WiFi or BLE is used we have to specify a Coex mode
+			 */
+			boot_config->coex_mode = SL_SI91X_BLE_MODE;
+		}
+
+#ifdef CONFIG_WIFI_SILABS_SIWX91X
+		boot_config->ext_tcp_ip_feature_bit_map = SL_SI91X_CONFIG_FEAT_EXTENSION_VALID;
+		boot_config->config_feature_bit_map = SL_SI91X_ENABLE_ENHANCED_MAX_PSP;
+		boot_config->ext_custom_feature_bit_map |=
+			SL_SI91X_EXT_FEAT_IEEE_80211W |
+			SL_SI91X_EXT_FEAT_FRONT_END_SWITCH_PINS_ULP_GPIO_4_5_0;
+#endif
+
+#ifdef CONFIG_BT_SILABS_SIWX91X
+		boot_config->ext_custom_feature_bit_map |= SL_SI91X_EXT_FEAT_BT_CUSTOM_FEAT_ENABLE;
+		boot_config->bt_feature_bit_map |=
+			SL_SI91X_BT_RF_TYPE | SL_SI91X_ENABLE_BLE_PROTOCOL;
+		boot_config->ble_feature_bit_map |=
+			SL_SI91X_BLE_MAX_NBR_PERIPHERALS(RSI_BLE_MAX_NBR_PERIPHERALS) |
+			SL_SI91X_BLE_MAX_NBR_CENTRALS(RSI_BLE_MAX_NBR_CENTRALS) |
+			SL_SI91X_BLE_MAX_NBR_ATT_SERV(RSI_BLE_MAX_NBR_ATT_SERV) |
+			SL_SI91X_BLE_MAX_NBR_ATT_REC(RSI_BLE_MAX_NBR_ATT_REC) |
+			SL_SI91X_BLE_PWR_INX(RSI_BLE_PWR_INX) |
+			SL_SI91X_BLE_PWR_SAVE_OPTIONS(RSI_BLE_PWR_SAVE_OPTIONS) |
+			SL_SI91X_916_BLE_COMPATIBLE_FEAT_ENABLE |
+			SL_SI91X_FEAT_BLE_CUSTOM_FEAT_EXTENSION_VALID;
+		boot_config->ble_ext_feature_bit_map |=
+			SL_SI91X_BLE_NUM_CONN_EVENTS(RSI_BLE_NUM_CONN_EVENTS) |
+			SL_SI91X_BLE_NUM_REC_BYTES(RSI_BLE_NUM_REC_BYTES) |
+			SL_SI91X_BLE_ENABLE_ADV_EXTN |
+			SL_SI91X_BLE_AE_MAX_ADV_SETS(RSI_BLE_AE_MAX_ADV_SETS);
+#endif
+	} else if (wifi_oper_mode == SL_SI91X_ACCESS_POINT_MODE) {
+		boot_config->oper_mode = SL_SI91X_ACCESS_POINT_MODE;
+		boot_config->coex_mode = SL_SI91X_WLAN_ONLY_MODE;
+
+		if (IS_ENABLED(CONFIG_BT_SILABS_SIWX91X)) {
+			LOG_WRN("Bluetooth is not supported in AP mode");
+		}
+	} else {
+		return -EINVAL;
+	}
+
+#ifdef CONFIG_WIFI_SILABS_SIWX91X
+	if (IS_ENABLED(CONFIG_WIFI_SILABS_SIWX91X_NET_STACK_OFFLOAD)) {
+		boot_config->tcp_ip_feature_bit_map |= SL_SI91X_TCP_IP_FEAT_ICMP;
+		boot_config->ext_tcp_ip_feature_bit_map |= SL_SI91X_EXT_TCP_IP_WINDOW_SCALING;
+		boot_config->ext_tcp_ip_feature_bit_map |= SL_SI91X_EXT_TCP_IP_TOTAL_SELECTS(10);
+
+		if (IS_ENABLED(CONFIG_NET_IPV6)) {
+			boot_config->tcp_ip_feature_bit_map |= SL_SI91X_TCP_IP_FEAT_IPV6;
+			if (wifi_oper_mode == SL_SI91X_CLIENT_MODE) {
+				boot_config->tcp_ip_feature_bit_map |=
+					SL_SI91X_TCP_IP_FEAT_DHCPV6_CLIENT;
+			} else if (wifi_oper_mode == SL_SI91X_ACCESS_POINT_MODE) {
+				boot_config->tcp_ip_feature_bit_map |=
+					SL_SI91X_TCP_IP_FEAT_DHCPV6_SERVER;
+			}
+		}
+
+		if (IS_ENABLED(CONFIG_NET_IPV4)) {
+			if (wifi_oper_mode == SL_SI91X_CLIENT_MODE) {
+				boot_config->tcp_ip_feature_bit_map |=
+					SL_SI91X_TCP_IP_FEAT_DHCPV4_CLIENT;
+			} else if (wifi_oper_mode == SL_SI91X_ACCESS_POINT_MODE) {
+				boot_config->tcp_ip_feature_bit_map |=
+					SL_SI91X_TCP_IP_FEAT_DHCPV4_SERVER;
+			}
+		}
+	} else {
+		boot_config->tcp_ip_feature_bit_map |= SL_SI91X_TCP_IP_FEAT_BYPASS;
+	}
+#endif
+	memcpy(get_config, &default_config, sizeof(default_config));
+	return 0;
+}
+
+int siwx91x_nwp_mode_switch(uint8_t oper_mode)
+{
+	sl_wifi_device_configuration_t nwp_config;
+	sl_status_t status;
+
+	switch (oper_mode) {
+	case WIFI_STA_MODE:
+		siwg91x_get_nwp_config(SL_SI91X_CLIENT_MODE, &nwp_config);
+		break;
+	case WIFI_AP_MODE:
+		siwg91x_get_nwp_config(SL_SI91X_ACCESS_POINT_MODE, &nwp_config);
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	/* FIXME: Calling sl_wifi_deinit() impacts Bluetooth if coexistence is enabled */
+	status = sl_wifi_deinit();
+	if (status != SL_STATUS_OK) {
+		return -ETIMEDOUT;
+	}
+
+	status = sl_wifi_init(&nwp_config, NULL, sl_wifi_default_event_handler);
+	if (status != SL_STATUS_OK) {
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
+
+static int siwg917_nwp_init(void)
+{
+	sl_wifi_device_configuration_t network_config;
+	sl_status_t status;
+
+	siwg91x_get_nwp_config(SL_SI91X_CLIENT_MODE, &network_config);
+	/* TODO: If sl_net_*_profile() functions will be needed for WiFi then call
+	 * sl_net_set_profile() here. Currently these are unused.
+	 */
+	status = sl_wifi_init(&network_config, NULL, sl_wifi_default_event_handler);
+	if (status != SL_STATUS_OK) {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+SYS_INIT(siwg917_nwp_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
+
+/* IRQn 74 is used for communication with co-processor */
+Z_ISR_DECLARE(74, 0, IRQ074_Handler, 0);
+
+/* Co-processor will use value stored in IVT to store its stack.
+ *
+ * FIXME: We can't use Z_ISR_DECLARE() to declare this entry
+ * FIXME: Allow to configure size of buffer
+ */
+static uint8_t __aligned(8) siwg917_nwp_stack[10 * 1024];
+static Z_DECL_ALIGN(struct _isr_list) Z_GENERIC_SECTION(.intList)
+	__used __isr_siwg917_coprocessor_stack_irq = {
+		.irq = 30,
+		.flags = ISR_FLAG_DIRECT,
+		.func = &siwg917_nwp_stack[sizeof(siwg917_nwp_stack) - 1],
+	};
diff --git a/soc/silabs/silabs_siwx91x/siwg917/nwp.h b/soc/silabs/silabs_siwx91x/siwg917/nwp.h
new file mode 100644
index 00000000000..74fbec48b85
--- /dev/null
+++ b/soc/silabs/silabs_siwx91x/siwg917/nwp.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef SIWG917_NWP_H
+#define SIWG917_NWP_H
+
+#include "sl_wifi.h"
+
+#define SIWX91X_INTERFACE_MASK (0x03)
+
+/**
+ * @brief Switch the Wi-Fi operating modes.
+ *
+ * This function switches the mode. If the requested mode is already active,
+ * no action is performed. Otherwise, it reinitializes the Wi-Fi subsystem to
+ * apply the new mode.
+ *
+ * @param[in] oper_mode  Desired Wi-Fi operating mode:
+ *
+ * @return 0 on success, or a negative error code on failure:
+ */
+int siwx91x_nwp_mode_switch(uint8_t oper_mode);
+
+#endif
diff --git a/soc/silabs/silabs_siwx91x/siwg917/pinctrl_soc.h b/soc/silabs/silabs_siwx91x/siwg917/pinctrl_soc.h
new file mode 100644
index 00000000000..bf066ff203b
--- /dev/null
+++ b/soc/silabs/silabs_siwx91x/siwg917/pinctrl_soc.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2023 Antmicro
+ * Copyright (c) 2024 Silicon Laboratories, Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_SILABS_SIWG917_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_SILABS_SIWG917_PINCTRL_SOC_H_
+
+#include <zephyr/types.h>
+#include <zephyr/dt-bindings/pinctrl/silabs/siwx91x-pinctrl.h>
+
+typedef struct pinctrl_soc_pin_t {
+	uint8_t port;
+	uint8_t pin;
+	uint8_t ulppin;
+	uint8_t mode;
+	uint8_t ulpmode;
+	uint8_t pad;
+} pinctrl_soc_pin_t;
+
+#define Z_PINCTRL_STATE_PIN_INIT(node, prop, idx) {                                           \
+	.port    = FIELD_GET(SIWX91X_PINCTRL_PORT_MASK,    DT_PROP_BY_IDX(node, prop, idx)),  \
+	.pin     = FIELD_GET(SIWX91X_PINCTRL_PIN_MASK,     DT_PROP_BY_IDX(node, prop, idx)),  \
+	.ulppin  = FIELD_GET(SIWX91X_PINCTRL_ULPPIN_MASK,  DT_PROP_BY_IDX(node, prop, idx)),  \
+	.mode    = FIELD_GET(SIWX91X_PINCTRL_MODE_MASK,    DT_PROP_BY_IDX(node, prop, idx)),  \
+	.ulpmode = FIELD_GET(SIWX91X_PINCTRL_ULPMODE_MASK, DT_PROP_BY_IDX(node, prop, idx)),  \
+	.pad     = FIELD_GET(SIWX91X_PINCTRL_PAD_MASK,     DT_PROP_BY_IDX(node, prop, idx)),  \
+},
+
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) {                                            \
+	DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM,               \
+			       pinmux, Z_PINCTRL_STATE_PIN_INIT)                              \
+}
+
+#endif
diff --git a/soc/silabs/silabs_siwx91x/siwg917/soc.c b/soc/silabs/silabs_siwx91x/siwg917/soc.c
new file mode 100644
index 00000000000..139b7f3492a
--- /dev/null
+++ b/soc/silabs/silabs_siwx91x/siwg917/soc.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2023 Antmicro
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdint.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/sw_isr_table.h>
+
+#include "em_device.h"
+
+void soc_early_init_hook(void)
+{
+	SystemInit();
+}
+
+/* SiWx917's bootloader requires IRQn 32 to hold payload's entry point address. */
+extern void z_arm_reset(void);
+Z_ISR_DECLARE_DIRECT(32, 0, z_arm_reset);
diff --git a/soc/silabs/silabs_siwx91x/siwg917/soc.h b/soc/silabs/silabs_siwx91x/siwg917/soc.h
new file mode 100644
index 00000000000..43b7088894e
--- /dev/null
+++ b/soc/silabs/silabs_siwx91x/siwg917/soc.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef SIWG917_SOC_H
+#define SIWG917_SOC_H
+
+#include "si91x_device.h"
+
+#define SYSRTC_IRQHandler IRQ022_Handler
+
+#endif
diff --git a/soc/silabs/silabs_siwx91x/siwx91x_isp_prepare.py b/soc/silabs/silabs_siwx91x/siwx91x_isp_prepare.py
new file mode 100755
index 00000000000..3a217b0c217
--- /dev/null
+++ b/soc/silabs/silabs_siwx91x/siwx91x_isp_prepare.py
@@ -0,0 +1,193 @@
+#!/usr/bin/env python3
+#
+# Copyright (c) 2023 Antmicro
+# Copyright (c) 2024 Silicon Laboratories Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+import argparse
+import struct
+import sys
+
+import intelhex
+
+
+# For reference:
+#     width=32 poly=0xd95eaae5 init=0 refin=true refout=true xorout=0
+def create_table() -> list[int]:
+    crc_table = [0] * 256
+    for b in range(256):
+        register = b
+        for _ in range(8):
+            lsb = register & 1
+            register >>= 1
+            if lsb:
+                # Reflected polynomial: 0xd95eaae5
+                register ^= 0xA7557A9B
+        crc_table[b] = register
+    return crc_table
+
+
+def calc_crc32(data: bytes) -> int:
+    crc_table = create_table()
+    register = 0
+    for b in data:
+        register = crc_table[(b ^ register) & 0xFF] ^ (register >> 8)
+    return register
+
+
+def calc_checksum(data: bytes | bytearray, size: int, prev_sum: int) -> int:
+    # Truncate
+    data = data[:size]
+    # Zero-pad data to mul of 4 bytes
+    nzeros = ((len(data) + 3) // 4 * 4) - len(data)
+    data += b"\0" * nzeros
+    # Reinterpret data as LE u32
+    ints = list(x[0] for x in struct.iter_unpack("<I", data))
+    # Sum
+    chk = prev_sum + sum(ints)
+    # Convert to u32 and account each overflow as 1"s complement addition
+    chk = (chk & 0xFFFFFFFF) + (chk >> 32)
+    chk = (~chk) & 0xFFFFFFFF
+    return chk
+
+
+def set_bits(x: int, off: int, size: int, field: int) -> int:
+    field = int(field)
+    mask = ((1 << size) - 1) << off
+    x &= ~mask
+    x |= (field << off) & mask
+    return x
+
+
+def get_bootload_entry(
+    ctrl_len: int = 0,
+    ctrl_reserved: int = 0,
+    ctrl_spi_32bitmode: bool = False,
+    ctrl_release_ta_softreset: bool = False,
+    ctrl_start_from_rom_pc: bool = False,
+    ctrl_spi_8bitmode: bool = False,
+    ctrl_last_entry: bool = True,
+    dest_addr: int = 0,
+) -> bytes:
+    # Format bootload_entry struct
+    ctrl = 0
+    ctrl = set_bits(ctrl, 0, 24, ctrl_len)
+    ctrl = set_bits(ctrl, 24, 3, ctrl_reserved)
+    ctrl = set_bits(ctrl, 27, 1, ctrl_spi_32bitmode)
+    ctrl = set_bits(ctrl, 28, 1, ctrl_release_ta_softreset)
+    ctrl = set_bits(ctrl, 29, 1, ctrl_start_from_rom_pc)
+    ctrl = set_bits(ctrl, 30, 1, ctrl_spi_8bitmode)
+    ctrl = set_bits(ctrl, 31, 1, ctrl_last_entry)
+    return struct.pack("<II", ctrl, dest_addr)
+
+
+def get_bootload_ds(offset: int, ivt_offset: int, fixed_pattern: int = 0x5AA5) -> bytes:
+    ret = b""
+    ret += int(fixed_pattern).to_bytes(2, "little")
+    ret += int(offset).to_bytes(2, "little")
+    ret += int(ivt_offset).to_bytes(4, "little")
+    for i in range(7):
+        ret += get_bootload_entry(ctrl_last_entry=i == 0)
+    return ret
+
+
+def get_fwupreq(flash_location: int, image_size: int) -> bytes:
+    # Field values
+    cflags = 1
+    sha_type = 0
+    magic_no = 0x900D900D
+    fw_version = 0
+    # Initially CRC value is set to 0, then the CRC is calculated on the
+    # whole image (including fwupreq header), and injected here
+    crc = 0
+    mic = [0, 0, 0, 0]
+    counter = 0
+    rsvd = [0, 0, 0, 0, magic_no]
+    # Format
+    ret = b""
+    ret += cflags.to_bytes(2, "little")
+    ret += sha_type.to_bytes(2, "little")
+    ret += magic_no.to_bytes(4, "little")
+    ret += image_size.to_bytes(4, "little")
+    ret += fw_version.to_bytes(4, "little")
+    ret += flash_location.to_bytes(4, "little")
+    ret += crc.to_bytes(4, "little")
+    for x in mic:
+        ret += x.to_bytes(4, "little")
+    ret += counter.to_bytes(4, "little")
+    for x in rsvd:
+        ret += x.to_bytes(4, "little")
+    return ret
+
+
+def main():
+    parser = argparse.ArgumentParser(
+        description="Converts raw binary output from Zephyr into an ISP binary for Silabs SiWx91x",
+        allow_abbrev=False,
+    )
+    parser.add_argument(
+        "ifile",
+        metavar="INPUT.BIN",
+        help="Raw binary file to read",
+        type=argparse.FileType("rb"),
+    )
+    parser.add_argument(
+        "ofile",
+        metavar="OUTPUT.BIN",
+        help="ISP binary file to write",
+        type=argparse.FileType("wb"),
+    )
+    parser.add_argument(
+        "--load-addr",
+        metavar="ADDRESS",
+        help="Address at which the raw binary image begins in the memory",
+        type=lambda x: int(x, 0),
+        required=True,
+    )
+    parser.add_argument(
+        "--out-hex",
+        metavar="FILE.HEX",
+        help="Generate Intel HEX output in addition to binary one",
+        type=argparse.FileType("w", encoding="ascii"),
+    )
+    args = parser.parse_args()
+
+    img = bytearray(args.ifile.read())
+
+    # Calculate and inject checksum
+    chk = calc_checksum(img, 236, 1)
+    print(f"ROM checksum: 0x{chk:08x}", file=sys.stderr)
+    img[236:240] = chk.to_bytes(4, "little")
+
+    # Get bootloader header, pad to 4032 and glue it to the image payload
+    bl = bytearray(get_bootload_ds(4032, args.load_addr))
+    padding = bytearray(4032 - len(bl))
+    img = bl + padding + img
+
+    # Get fwupreq header and glue it to the bootloader payload
+    fwupreq = bytearray(get_fwupreq(args.load_addr - 0x8001000, len(img)))
+    img = fwupreq + img
+
+    # Calculate and inject CRC
+    crc = calc_crc32(img)
+    print(f"Image CRC: 0x{crc:08x}", file=sys.stderr)
+    img[20:24] = crc.to_bytes(4, "little")
+
+    args.ofile.write(img)
+
+    # If you want to compare this file with the .hex file generated by Zephyr,
+    # You have to reformat the Zephyr output:
+    #   import intelhex
+    #   hx = intelhex.IntelHex()
+    #   hx.fromfile("zephyr.hex", "hex")
+    #   hx.write_hex_file("zephyr.out.hex", byte_count=32)
+    if args.out_hex:
+        hx = intelhex.IntelHex()
+        # len(bl) + len(padding) + len(fwupreq) == 4096
+        hx.frombytes(img, args.load_addr - 4096)
+        hx.write_hex_file(args.out_hex, byte_count=32)
+
+
+if __name__ == "__main__":
+    main()
diff --git a/soc/silabs/soc.yml b/soc/silabs/soc.yml
index bb933cca30e..b274cbda062 100644
--- a/soc/silabs/soc.yml
+++ b/soc/silabs/soc.yml
@@ -59,6 +59,21 @@ family:
       - name: efr32zg23
         socs:
           - name: efr32zg23b020f512im48
+      - name: efr32bg29
+        socs:
+          - name: efr32bg29b140f1024im40
+          - name: efr32bg29b220f1024cj45
+          - name: efr32bg29b221f1024cj45
+          - name: efr32bg29b230f1024cm40
+      - name: efr32mg29
+        socs:
+          - name: efr32mg29b140f1024im40
+          - name: efr32mg29b230f1024cm40
+  - name: silabs_siwx91x
+    series:
+      - name: siwg917
+        socs:
+          - name: siwg917m111mgtba
   - name: silabs_sim3
     series:
       - name: sim3u
diff --git a/soc/st/stm32/Kconfig b/soc/st/stm32/Kconfig
index 4f3371ab79b..59a245fb17a 100644
--- a/soc/st/stm32/Kconfig
+++ b/soc/st/stm32/Kconfig
@@ -60,7 +60,7 @@ choice POWER_SUPPLY_CHOICE
 	prompt "STM32 power supply configuration"
 	default POWER_SUPPLY_LDO
 	depends on SOC_SERIES_STM32H7X || SOC_SERIES_STM32H7RSX || \
-		SOC_SERIES_STM32U5X || SOC_STM32WBA55XX
+		SOC_SERIES_STM32U5X || SOC_STM32WBA55XX || SOC_STM32WBA65XX
 
 config POWER_SUPPLY_LDO
 	bool "LDO supply"
diff --git a/soc/st/stm32/Kconfig.defconfig b/soc/st/stm32/Kconfig.defconfig
index 0741439de6c..1cf916d1611 100644
--- a/soc/st/stm32/Kconfig.defconfig
+++ b/soc/st/stm32/Kconfig.defconfig
@@ -7,8 +7,13 @@
 
 if SOC_FAMILY_STM32
 
+# Source series Kconfig files first, so SoCs
+# can override the defaults given here
 rsource "*/Kconfig.defconfig"
 
+config CACHE_STM32
+	default y if EXTERNAL_CACHE
+
 config CLOCK_CONTROL
 	default y
 
@@ -61,10 +66,6 @@ config CLOCK_CONTROL_INIT_PRIORITY
 	default 1
 	depends on CLOCK_CONTROL
 
-config PHY_INIT_PRIORITY
-	default 81
-	depends on NET_L2_ETHERNET && ETH_DRIVER
-
 # Get flash configuration for NS image from dts flash partition
 config USE_DT_CODE_PARTITION
 	default y if TRUSTED_EXECUTION_NONSECURE
diff --git a/soc/st/stm32/common/CMakeLists.txt b/soc/st/stm32/common/CMakeLists.txt
index 3ff3d1f5d6f..6d97ebd9ac0 100644
--- a/soc/st/stm32/common/CMakeLists.txt
+++ b/soc/st/stm32/common/CMakeLists.txt
@@ -7,7 +7,14 @@ zephyr_sources(
 	soc_config.c
 )
 
-zephyr_linker_sources_ifdef(CONFIG_STM32_CCM SECTIONS ccm.ld)
+if(DEFINED CONFIG_STM32_CCM)
+  zephyr_linker_group(NAME CCM_REGION VMA CCM LMA ROM_REGION)
+  zephyr_linker_section(NAME .ccm_bss GROUP CCM_REGION SUBALIGN 4 TYPE BSS )
+  zephyr_linker_section(NAME .ccm_noinit GROUP CCM_REGION SUBALIGN 4 TYPE NOLOAD NOINIT)
+  zephyr_linker_section(NAME .ccm_data GROUP CCM_REGION SUBALIGN 4)
+
+  zephyr_linker_sources(SECTIONS ccm.ld)
+endif()
 
 zephyr_sources_ifdef(CONFIG_STM32_BACKUP_SRAM stm32_backup_sram.c)
 zephyr_linker_sources_ifdef(CONFIG_STM32_BACKUP_SRAM SECTIONS stm32_backup_sram.ld)
@@ -19,3 +26,10 @@ endif()
 if (CONFIG_STM32_WKUP_PINS)
   zephyr_sources(stm32_wkup_pins.c)
 endif()
+
+if (CONFIG_PM AND CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP)
+  message(WARNING "\
+SoC Power Management (CONFIG_PM) enabled but the DBGMCU is still enabled \
+(CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP). The SoC will use more power than expected \
+in STOP modes due to internal oscillators that remain active.")
+endif()
diff --git a/soc/st/stm32/common/ccm.ld b/soc/st/stm32/common/ccm.ld
index ee2396b3c79..656b4567b6f 100644
--- a/soc/st/stm32/common/ccm.ld
+++ b/soc/st/stm32/common/ccm.ld
@@ -29,6 +29,6 @@ GROUP_START(CCM)
 
 	__ccm_end = .;
 
-	__ccm_data_rom_start = LOADADDR(_CCM_DATA_SECTION_NAME);
+	__ccm_data_load_start = LOADADDR(_CCM_DATA_SECTION_NAME);
 
 GROUP_END(CCM)
diff --git a/soc/st/stm32/common/soc_config.c b/soc/st/stm32/common/soc_config.c
index 9275ce72bab..07eb74a697c 100644
--- a/soc/st/stm32/common/soc_config.c
+++ b/soc/st/stm32/common/soc_config.c
@@ -76,6 +76,8 @@ static int st_stm32_common_config(void)
 	LL_DBGMCU_EnableDebugInStopMode();
 #elif defined(CONFIG_SOC_SERIES_STM32WB0X)
 	LL_PWR_EnableDEEPSTOP2();
+#elif defined(CONFIG_SOC_SERIES_STM32MP13X)
+	LL_DBGMCU_EnableDebugInLowPowerMode();
 #else /* all other parts */
 	LL_DBGMCU_EnableDBGStopMode();
 #endif
@@ -90,6 +92,8 @@ static int st_stm32_common_config(void)
 	LL_DBGMCU_DisableDebugInStopMode();
 #elif defined(CONFIG_SOC_SERIES_STM32WB0X)
 	LL_PWR_DisableDEEPSTOP2();
+#elif defined(CONFIG_SOC_SERIES_STM32MP13X)
+	LL_DBGMCU_DisableDebugInLowPowerMode();
 #else /* all other parts */
 	LL_DBGMCU_DisableDBGStopMode();
 #endif
diff --git a/soc/st/stm32/common/stm32_wkup_pins.c b/soc/st/stm32/common/stm32_wkup_pins.c
index c25887dfc39..0ca40b9b2a9 100644
--- a/soc/st/stm32/common/stm32_wkup_pins.c
+++ b/soc/st/stm32/common/stm32_wkup_pins.c
@@ -225,11 +225,11 @@ static void wkup_pin_setup(const struct wkup_pin_cfg_t *wakeup_pin_cfg)
 
 #if defined(CONFIG_SOC_SERIES_STM32U5X) || defined(CONFIG_SOC_SERIES_STM32WBAX)
 	/* Select the proper wake-up signal source */
-	if (wakeup_pin_cfg->src_selection & STM32_PWR_WKUP_PIN_SRC_0) {
+	if (wakeup_pin_cfg->src_selection & STM32_PWR_WKUP_EVT_SRC_0) {
 		LL_PWR_SetWakeUpPinSignal0Selection(table_wakeup_pins[wkup_pin_index]);
-	} else if (wakeup_pin_cfg->src_selection & STM32_PWR_WKUP_PIN_SRC_1) {
+	} else if (wakeup_pin_cfg->src_selection & STM32_PWR_WKUP_EVT_SRC_1) {
 		LL_PWR_SetWakeUpPinSignal1Selection(table_wakeup_pins[wkup_pin_index]);
-	} else if (wakeup_pin_cfg->src_selection & STM32_PWR_WKUP_PIN_SRC_2) {
+	} else if (wakeup_pin_cfg->src_selection & STM32_PWR_WKUP_EVT_SRC_2) {
 		LL_PWR_SetWakeUpPinSignal2Selection(table_wakeup_pins[wkup_pin_index]);
 	} else {
 		LL_PWR_SetWakeUpPinSignal3Selection(table_wakeup_pins[wkup_pin_index]);
@@ -275,7 +275,7 @@ int stm32_pwr_wkup_pin_cfg_gpio(const struct gpio_dt_spec *gpio)
 	}
 
 	if (!found_gpio) {
-		LOG_DBG("Couldn't find a wake-up event correspending to GPIO %s pin %d\n",
+		LOG_DBG("Couldn't find a wake-up event corresponding to GPIO %s pin %d\n",
 			gpio->port->name, gpio->pin);
 		LOG_DBG("=> It cannot be used as a wake-up source\n");
 		return -EINVAL;
@@ -286,9 +286,9 @@ int stm32_pwr_wkup_pin_cfg_gpio(const struct gpio_dt_spec *gpio)
 /* Each wake-up pin on STM32U5 is associated with 4 wkup srcs, 3 of them correspond to GPIOs. */
 #if defined(CONFIG_SOC_SERIES_STM32U5X) || defined(CONFIG_SOC_SERIES_STM32WBAX)
 	wakeup_pin_cfg.src_selection = wkup_pin_gpio_cfg->dt_flags &
-					(STM32_PWR_WKUP_PIN_SRC_0 |
-					STM32_PWR_WKUP_PIN_SRC_1 |
-					STM32_PWR_WKUP_PIN_SRC_2);
+					(STM32_PWR_WKUP_EVT_SRC_0 |
+					STM32_PWR_WKUP_EVT_SRC_1 |
+					STM32_PWR_WKUP_EVT_SRC_2);
 #else
 	wakeup_pin_cfg.src_selection = 0;
 #endif /* CONFIG_SOC_SERIES_STM32U5X or CONFIG_SOC_SERIES_STM32WBAX */
diff --git a/soc/st/stm32/soc.yml b/soc/st/stm32/soc.yml
index ba24bcf143e..5b74c7a43ef 100644
--- a/soc/st/stm32/soc.yml
+++ b/soc/st/stm32/soc.yml
@@ -43,6 +43,7 @@ family:
   - name: stm32f4x
     socs:
     - name: stm32f401xc
+    - name: stm32f401xd
     - name: stm32f401xe
     - name: stm32f405xx
     - name: stm32f407xx
@@ -59,8 +60,10 @@ family:
     - name: stm32f427xx
     - name: stm32f429xx
     - name: stm32f437xx
+    - name: stm32f439xx
     - name: stm32f446xx
     - name: stm32f469xx
+    - name: stm32f479xx
   - name: stm32f7x
     socs:
     - name: stm32f722xx
@@ -186,6 +189,12 @@ family:
   - name: stm32mp1x
     socs:
     - name: stm32mp157cxx
+  - name: stm32mp13x
+    socs:
+    - name: stm32mp135fxx
+  - name: stm32n6x
+    socs:
+    - name: stm32n657xx
   - name: stm32u0x
     socs:
     - name: stm32u031xx
@@ -195,6 +204,7 @@ family:
     socs:
     - name: stm32u5a5xx
     - name: stm32u5a9xx
+    - name: stm32u5g9xx
     - name: stm32u545xx
     - name: stm32u575xx
     - name: stm32u585xx
@@ -213,6 +223,7 @@ family:
     socs:
     - name: stm32wba52xx
     - name: stm32wba55xx
+    - name: stm32wba65xx
   - name: stm32wlx
     socs:
     - name: stm32wle4xx
diff --git a/soc/st/stm32/stm32c0x/poweroff.c b/soc/st/stm32/stm32c0x/poweroff.c
index c9c4db49e9d..ec07aaf81bf 100644
--- a/soc/st/stm32/stm32c0x/poweroff.c
+++ b/soc/st/stm32/stm32c0x/poweroff.c
@@ -1,19 +1,30 @@
 /*
  * Copyright (c) 2024 Kickmaker
+ * Copyright (c) 2025 Tomas Jurena
+ *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <zephyr/kernel.h>
 #include <zephyr/sys/poweroff.h>
 #include <zephyr/toolchain.h>
+#include <zephyr/drivers/misc/stm32_wkup_pins/stm32_wkup_pins.h>
 
 #include <stm32_ll_cortex.h>
 #include <stm32_ll_pwr.h>
+#include <stm32_ll_system.h>
 
 void z_sys_poweroff(void)
 {
+#ifdef CONFIG_STM32_WKUP_PINS
+	stm32_pwr_wkup_pin_cfg_pupd();
+
+	LL_PWR_ClearFlag_WU();
+#endif /* CONFIG_STM32_WKUP_PINS */
+
 	LL_PWR_SetPowerMode(LL_PWR_MODE_SHUTDOWN);
 	LL_LPM_EnableDeepSleep();
+	LL_DBGMCU_DisableDBGStandbyMode();
 
 	k_cpu_idle();
 
diff --git a/soc/st/stm32/stm32f4x/CMakeLists.txt b/soc/st/stm32/stm32f4x/CMakeLists.txt
index ea800d26565..b2b70aedeea 100644
--- a/soc/st/stm32/stm32f4x/CMakeLists.txt
+++ b/soc/st/stm32/stm32f4x/CMakeLists.txt
@@ -12,3 +12,4 @@ set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/li
 zephyr_sources_ifdef(CONFIG_PM
   power.c
   )
+zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c)
diff --git a/soc/st/stm32/stm32f4x/Kconfig b/soc/st/stm32/stm32f4x/Kconfig
index 2d8681f3da3..a738978109c 100644
--- a/soc/st/stm32/stm32f4x/Kconfig
+++ b/soc/st/stm32/stm32f4x/Kconfig
@@ -12,4 +12,5 @@ config SOC_SERIES_STM32F4X
 	select CPU_HAS_ARM_MPU
 	select HAS_SWO
 	select HAS_PM
+	select HAS_POWEROFF
 	select SOC_EARLY_INIT_HOOK
diff --git a/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f401xd b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f401xd
new file mode 100644
index 00000000000..cb1bbb16201
--- /dev/null
+++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f401xd
@@ -0,0 +1,11 @@
+# ST STM32F401xD MCU configuration options
+
+# Copyright (c) 2025 Cirrus Logic, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32F401XD
+
+config NUM_IRQS
+	default 85
+
+endif # SOC_STM32F401XD
diff --git a/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f439xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f439xx
new file mode 100644
index 00000000000..0abc2c8fbbe
--- /dev/null
+++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f439xx
@@ -0,0 +1,11 @@
+# ST STM32F439XX MCU configuration options
+
+# Copyright (c) 2025 Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>.
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32F439XX
+
+config NUM_IRQS
+	default 91
+
+endif # SOC_STM32F439XX
diff --git a/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f479xx b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f479xx
new file mode 100644
index 00000000000..baea858199f
--- /dev/null
+++ b/soc/st/stm32/stm32f4x/Kconfig.defconfig.stm32f479xx
@@ -0,0 +1,11 @@
+# ST STM32F479XI MCU configuration options
+
+# Copyright (c) 2025 Christopher Cichiwskyj
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32F479XX
+
+config NUM_IRQS
+	default 93
+
+endif # SOC_STM32F479XX
diff --git a/soc/st/stm32/stm32f4x/Kconfig.soc b/soc/st/stm32/stm32f4x/Kconfig.soc
index 0f830e8a365..31045403450 100644
--- a/soc/st/stm32/stm32f4x/Kconfig.soc
+++ b/soc/st/stm32/stm32f4x/Kconfig.soc
@@ -14,6 +14,10 @@ config SOC_STM32F401XC
 	bool
 	select SOC_SERIES_STM32F4X
 
+config SOC_STM32F401XD
+	bool
+	select SOC_SERIES_STM32F4X
+
 config SOC_STM32F401XE
 	bool
 	select SOC_SERIES_STM32F4X
@@ -82,6 +86,10 @@ config SOC_STM32F437XX
 	bool
 	select SOC_SERIES_STM32F4X
 
+config SOC_STM32F439XX
+	bool
+	select SOC_SERIES_STM32F4X
+
 config SOC_STM32F446XX
 	bool
 	select SOC_SERIES_STM32F4X
@@ -90,8 +98,13 @@ config SOC_STM32F469XX
 	bool
 	select SOC_SERIES_STM32F4X
 
+config SOC_STM32F479XX
+	bool
+	select SOC_SERIES_STM32F4X
+
 config SOC
 	default "stm32f401xc" if SOC_STM32F401XC
+	default "stm32f401xd" if SOC_STM32F401XD
 	default "stm32f401xe" if SOC_STM32F401XE
 	default "stm32f405xx" if SOC_STM32F405XX
 	default "stm32f407xx" if SOC_STM32F407XE
@@ -109,5 +122,7 @@ config SOC
 	default "stm32f427xx" if SOC_STM32F427XX
 	default "stm32f429xx" if SOC_STM32F429XX
 	default "stm32f437xx" if SOC_STM32F437XX
+	default "stm32f439xx" if SOC_STM32F439XX
 	default "stm32f446xx" if SOC_STM32F446XX
 	default "stm32f469xx" if SOC_STM32F469XX
+	default "stm32f479xx" if SOC_STM32F479XX
diff --git a/soc/st/stm32/stm32f4x/poweroff.c b/soc/st/stm32/stm32f4x/poweroff.c
new file mode 100644
index 00000000000..28099224184
--- /dev/null
+++ b/soc/st/stm32/stm32f4x/poweroff.c
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2023 Nordic Semiconductor ASA
+ * Copyright (c) 2024 STMicroelectronics
+ * Copyright (c) 2025 Tomas Jurena
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/sys/poweroff.h>
+#include <zephyr/toolchain.h>
+#include <zephyr/drivers/misc/stm32_wkup_pins/stm32_wkup_pins.h>
+
+#include <stm32_ll_cortex.h>
+#include <stm32_ll_pwr.h>
+
+void z_sys_poweroff(void)
+{
+#ifdef CONFIG_STM32_WKUP_PINS
+	LL_PWR_ClearFlag_WU();
+#endif /* CONFIG_STM32_WKUP_PINS */
+
+	LL_PWR_SetPowerMode(LL_PWR_MODE_STANDBY);
+	LL_LPM_EnableDeepSleep();
+
+	k_cpu_idle();
+
+	CODE_UNREACHABLE;
+}
diff --git a/soc/st/stm32/stm32h5x/Kconfig.defconfig b/soc/st/stm32/stm32h5x/Kconfig.defconfig
index f8167440f33..d3eb43e4286 100644
--- a/soc/st/stm32/stm32h5x/Kconfig.defconfig
+++ b/soc/st/stm32/stm32h5x/Kconfig.defconfig
@@ -7,6 +7,19 @@ if SOC_SERIES_STM32H5X
 
 rsource "Kconfig.defconfig.stm32h5*"
 
+config ICACHE
+	default y
+
+config DCACHE
+	default y if !SOC_STM32H503XX
+
+config CACHE_MANAGEMENT
+	default y
+
+choice CACHE_TYPE
+	default EXTERNAL_CACHE
+endchoice
+
 config ROM_START_OFFSET
 	default 0x400 if BOOTLOADER_MCUBOOT
 
diff --git a/soc/st/stm32/stm32h5x/soc.c b/soc/st/stm32/stm32h5x/soc.c
index c4735c78c79..5ae4618b707 100644
--- a/soc/st/stm32/stm32h5x/soc.c
+++ b/soc/st/stm32/stm32h5x/soc.c
@@ -11,9 +11,9 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
+#include <zephyr/cache.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
-#include <stm32_ll_icache.h>
 #include <zephyr/logging/log.h>
 
 #include <cmsis_core.h>
@@ -29,9 +29,7 @@ extern void stm32_power_init(void);
  */
 void soc_early_init_hook(void)
 {
-	/* Enable instruction cache in 1-way (direct mapped cache) */
-	LL_ICACHE_SetMode(LL_ICACHE_1WAY);
-	LL_ICACHE_Enable();
+	sys_cache_instr_enable();
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 32 MHz from HSI with a HSIDIV = 2 */
diff --git a/soc/st/stm32/stm32h7rsx/soc.c b/soc/st/stm32/stm32h7rsx/soc.c
index 75cf6aa62b8..7d19774cc2c 100644
--- a/soc/st/stm32/stm32h7rsx/soc.c
+++ b/soc/st/stm32/stm32h7rsx/soc.c
@@ -36,16 +36,6 @@ void soc_early_init_hook(void)
 	SystemCoreClock = 64000000;
 
 	/* Power Configuration */
-#if !defined(SMPS) && \
-		(defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS) || \
-		defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO) || \
-		defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_LDO) || \
-		defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT_AND_LDO) || \
-		defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT_AND_LDO) || \
-		defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_EXT) || \
-		defined(CONFIG_POWER_SUPPLY_SMPS_2V5_SUPPLIES_EXT))
-#error Unsupported configuration: Selected SoC do not support SMPS
-#endif
 #if defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
 	LL_PWR_ConfigSupply(LL_PWR_DIRECT_SMPS_SUPPLY);
 #elif defined(CONFIG_POWER_SUPPLY_SMPS_1V8_SUPPLIES_LDO)
diff --git a/soc/st/stm32/stm32h7x/Kconfig.defconfig b/soc/st/stm32/stm32h7x/Kconfig.defconfig
index 790b1659c05..5c9ca2c9772 100644
--- a/soc/st/stm32/stm32h7x/Kconfig.defconfig
+++ b/soc/st/stm32/stm32h7x/Kconfig.defconfig
@@ -14,4 +14,11 @@ config ROM_START_OFFSET
 	default 0x400 if BOOTLOADER_MCUBOOT
 	default 0x0   if !BOOTLOADER_MCUBOOT
 
+if LVGL
+
+config LV_DRAW_DMA2D_HAL_INCLUDE
+	default "stm32h7xx.h"
+
+endif # LVGL
+
 endif # SOC_SERIES_STM32H7X
diff --git a/soc/st/stm32/stm32h7x/mpu_regions.c b/soc/st/stm32/stm32h7x/mpu_regions.c
index 8582db60724..f77018d36ca 100644
--- a/soc/st/stm32/stm32h7x/mpu_regions.c
+++ b/soc/st/stm32/stm32h7x/mpu_regions.c
@@ -22,19 +22,19 @@ static const struct arm_mpu_region mpu_regions[] = {
 					MPU_RASR_XN_Msk | P_RW_U_NA_Msk) }),
 
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(mac))
+
 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sram3))
-	MPU_REGION_ENTRY("SRAM3_ETH_BUF",
-					 DT_REG_ADDR(DT_NODELABEL(sram3)),
-					 REGION_RAM_NOCACHE_ATTR(REGION_16K)),
-	MPU_REGION_ENTRY("SRAM3_ETH_DESC",
-					 DT_REG_ADDR(DT_NODELABEL(sram3)),
-					 REGION_PPB_ATTR(REGION_256B)),
+#define sram_eth_node	DT_NODELABEL(sram3)
 #else
-	MPU_REGION_ENTRY("SRAM2_ETH_BUF",
-					 DT_REG_ADDR(DT_NODELABEL(sram2)),
+#define sram_eth_node	DT_NODELABEL(sram2)
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(sram_eth_node)
+	MPU_REGION_ENTRY("SRAM_ETH_BUF",
+					 DT_REG_ADDR(sram_eth_node),
 					 REGION_RAM_NOCACHE_ATTR(REGION_16K)),
-	MPU_REGION_ENTRY("SRAM2_ETH_DESC",
-					 DT_REG_ADDR(DT_NODELABEL(sram2)),
+	MPU_REGION_ENTRY("SRAM_ETH_DESC",
+					 DT_REG_ADDR(sram_eth_node),
 					 REGION_PPB_ATTR(REGION_256B)),
 #endif
 #endif
diff --git a/soc/st/stm32/stm32h7x/sections.ld b/soc/st/stm32/stm32h7x/sections.ld
index 5f4fd794dd2..4989d8e90ea 100644
--- a/soc/st/stm32/stm32h7x/sections.ld
+++ b/soc/st/stm32/stm32h7x/sections.ld
@@ -4,24 +4,23 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(mac), okay)
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(mac))
 
+#if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(sram3))
+#define sram_eth_node	DT_NODELABEL(sram3)
+#else
+#define sram_eth_node	DT_NODELABEL(sram2)
+#endif
+
+#if DT_NODE_HAS_STATUS_OKAY(sram_eth_node)
 SECTION_DATA_PROLOGUE(eth_stm32,(NOLOAD),)
 {
-#if DT_NODE_HAS_STATUS(DT_NODELABEL(sram3), okay)
-    . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram3)));
+    . = ABSOLUTE(DT_REG_ADDR(sram_eth_node));
     *(.eth_stm32_desc)
-    . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram3))) + 256;
+    . = ABSOLUTE(DT_REG_ADDR(sram_eth_node)) + 256;
     *(.eth_stm32_buf)
-    . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram3))) + 16K;
-} GROUP_DATA_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(sram3)), LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(sram3)))
-
-#else
-    . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram2)));
-    *(.eth_stm32_desc)
-    . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram2))) + 256;
-    *(.eth_stm32_buf)
-    . = ABSOLUTE(DT_REG_ADDR(DT_NODELABEL(sram2))) + 16K;
-} GROUP_DATA_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(sram2)), LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(sram2)))
-#endif
+    . = ABSOLUTE(DT_REG_ADDR(sram_eth_node)) + 16K;
+} GROUP_DATA_LINK_IN(LINKER_DT_NODE_REGION_NAME(sram_eth_node), LINKER_DT_NODE_REGION_NAME(sram_eth_node))
 #endif
+
+#endif /* DT_NODE_HAS_STATUS(DT_NODELABEL(mac), okay) */
diff --git a/soc/st/stm32/stm32h7x/soc_m7.c b/soc/st/stm32/stm32h7x/soc_m7.c
index 79715a5f39e..46c9c954e95 100644
--- a/soc/st/stm32/stm32h7x/soc_m7.c
+++ b/soc/st/stm32/stm32h7x/soc_m7.c
@@ -89,9 +89,6 @@ void soc_early_init_hook(void)
 #else
 	LL_PWR_ConfigSupply(LL_PWR_LDO_SUPPLY);
 #endif
-	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE1);
-	while (LL_PWR_IsActiveFlag_VOS() == 0) {
-	}
 
 	/* Errata ES0392 Rev 8:
 	 * 2.2.9: Reading from AXI SRAM may lead to data read corruption
diff --git a/soc/st/stm32/stm32l5x/Kconfig.defconfig b/soc/st/stm32/stm32l5x/Kconfig.defconfig
index 2c8607c9b79..77ba04cece9 100644
--- a/soc/st/stm32/stm32l5x/Kconfig.defconfig
+++ b/soc/st/stm32/stm32l5x/Kconfig.defconfig
@@ -7,6 +7,16 @@ if SOC_SERIES_STM32L5X
 
 rsource "Kconfig.defconfig.stm32l5*"
 
+config ICACHE
+	default y
+
+config CACHE_MANAGEMENT
+	default y
+
+choice CACHE_TYPE
+	default EXTERNAL_CACHE
+endchoice
+
 config ROM_START_OFFSET
 	default 0x400 if BOOTLOADER_MCUBOOT
 
diff --git a/soc/st/stm32/stm32l5x/soc.c b/soc/st/stm32/stm32l5x/soc.c
index 4c52d30bd01..d8aed0383a6 100644
--- a/soc/st/stm32/stm32l5x/soc.c
+++ b/soc/st/stm32/stm32l5x/soc.c
@@ -11,9 +11,9 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
+#include <zephyr/cache.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
-#include <stm32l5xx_ll_icache.h>
 #include <zephyr/logging/log.h>
 
 #include <cmsis_core.h>
@@ -29,10 +29,7 @@ extern void stm32_power_init(void);
  */
 void soc_early_init_hook(void)
 {
-	/* Enable ICACHE */
-	while (LL_ICACHE_IsActiveFlag_BUSY()) {
-	}
-	LL_ICACHE_Enable();
+	sys_cache_instr_enable();
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 4 MHz from MSI */
diff --git a/soc/st/stm32/stm32mp13x/CMakeLists.txt b/soc/st/stm32/stm32mp13x/CMakeLists.txt
new file mode 100644
index 00000000000..792d64f8df5
--- /dev/null
+++ b/soc/st/stm32/stm32mp13x/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright (c) 2025 STMicroelectronics
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_sources(
+  soc.c
+  )
+
+zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/st/stm32/stm32mp13x/Kconfig b/soc/st/stm32/stm32mp13x/Kconfig
new file mode 100644
index 00000000000..7be5ca01a0c
--- /dev/null
+++ b/soc/st/stm32/stm32mp13x/Kconfig
@@ -0,0 +1,14 @@
+# STMicroelectronics STM32MP13 MPU series
+
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_STM32MP13X
+	select ARM
+	select CPU_CORTEX_A7
+	select HAS_STM32CUBE
+	select CPU_HAS_FPU
+	select SOC_EARLY_INIT_HOOK
+	select ARM_ARCH_TIMER
+	select SYS_CLOCK_EXISTS
+	select XIP
diff --git a/soc/st/stm32/stm32mp13x/Kconfig.defconfig b/soc/st/stm32/stm32mp13x/Kconfig.defconfig
new file mode 100644
index 00000000000..2a3929e30a7
--- /dev/null
+++ b/soc/st/stm32/stm32mp13x/Kconfig.defconfig
@@ -0,0 +1,20 @@
+# STMicroelectronics STM32MP13 MPU series
+
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_STM32MP13X
+
+rsource "Kconfig.defconfig.stm32mp13_a7"
+
+config CACHE_MANAGEMENT
+	default y
+
+DT_STM32_CPU_CLOCK_PATH := $(dt_nodelabel_path,cpusw)
+DT_STM32_CPU_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_CPU_CLOCK_PATH),clock-frequency)
+
+# For STM32MP13, override the default value defined in STM32 Kconfig
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(DT_STM32_CPU_CLOCK_FREQ) if $(dt_nodelabel_enabled,cpusw)
+
+endif # SOC_SERIES_STM32MP13X
diff --git a/soc/st/stm32/stm32mp13x/Kconfig.defconfig.stm32mp13_a7 b/soc/st/stm32/stm32mp13x/Kconfig.defconfig.stm32mp13_a7
new file mode 100644
index 00000000000..f65e137dab6
--- /dev/null
+++ b/soc/st/stm32/stm32mp13x/Kconfig.defconfig.stm32mp13_a7
@@ -0,0 +1,11 @@
+# STMicroelectronics STM32MP13_A7 MPU
+
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32MP135FXX
+
+config NUM_IRQS
+	default 181
+
+endif # SOC_STM32MP135FXX
diff --git a/soc/st/stm32/stm32mp13x/Kconfig.soc b/soc/st/stm32/stm32mp13x/Kconfig.soc
new file mode 100644
index 00000000000..9507ce31a9b
--- /dev/null
+++ b/soc/st/stm32/stm32mp13x/Kconfig.soc
@@ -0,0 +1,18 @@
+# STMicroelectronics STM32MP13 MPU series
+
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_STM32MP13X
+	bool
+	select SOC_FAMILY_STM32
+
+config SOC_SERIES
+	default "stm32mp13x" if SOC_SERIES_STM32MP13X
+
+config SOC_STM32MP135FXX
+	bool
+	select SOC_SERIES_STM32MP13X
+
+config SOC
+	default "stm32mp135fxx" if SOC_STM32MP135FXX
diff --git a/soc/st/stm32/stm32mp13x/soc.c b/soc/st/stm32/stm32mp13x/soc.c
new file mode 100644
index 00000000000..96874d8c483
--- /dev/null
+++ b/soc/st/stm32/stm32mp13x/soc.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for STM32MP13 processor
+ */
+
+#include <zephyr/arch/arm/mmu/arm_mmu.h>
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
+#include <zephyr/linker/linker-defs.h>
+
+#include <stm32_ll_bus.h>
+#include <cmsis_core.h>
+
+#define VECTOR_ADDRESS ((uintptr_t)_vector_start)
+
+void relocate_vector_table(void)
+{
+	write_sctlr(read_sctlr() & ~HIVECS);
+	write_vbar(VECTOR_ADDRESS & VBAR_MASK);
+	barrier_isync_fence_full();
+}
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ */
+
+void soc_early_init_hook(void)
+{
+	/* Update CMSIS SystemCoreClock variable (HCLK) */
+	SystemCoreClock = 1000000000U;
+
+	/* Clear TE bit to take exceptions in Thumb mode to fix the DDR init */
+	write_sctlr(read_sctlr() & ~SCTLR_TE_Msk);
+	barrier_isync_fence_full();
+}
+
+static const struct arm_mmu_region mmu_regions[] = {
+	MMU_REGION_FLAT_ENTRY("APB1", 0x40000000, 0x19400, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("APB2", 0x44000000, 0x14000, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("AHB2", 0x48000000, 0x1040000, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("APB6", 0x4C000000, 0xC400, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("AHB4", 0x50000000, 0xD400, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("APB3", 0x50020000, 0xA400, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("DEBUG APB", 0x50080000, 0x5D000, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("AHB5", 0x54000000, 0x8000, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("AXIMC", 0x57000000, 0x100000, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("AHB6", 0x58000000, 0x10000, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("APB4", 0x5A000000, 0x7400, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("APB5", 0x5C000000, 0xA400, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("GIC", 0xA0021000, 0x7000, MPERM_R | MPERM_W | MT_DEVICE),
+
+	MMU_REGION_FLAT_ENTRY("vectors", 0xC0000000, 0x1000, MPERM_R | MPERM_X | MT_NORMAL),
+
+	MMU_REGION_FLAT_ENTRY("DAPBUS", 0xE0080000, 0x5D000, MPERM_R | MPERM_W | MT_DEVICE),
+};
+
+const struct arm_mmu_config mmu_config = {
+	.num_regions = ARRAY_SIZE(mmu_regions),
+	.mmu_regions = mmu_regions,
+};
diff --git a/soc/st/stm32/stm32mp13x/soc.h b/soc/st/stm32/stm32mp13x/soc.h
new file mode 100644
index 00000000000..49847550700
--- /dev/null
+++ b/soc/st/stm32/stm32mp13x/soc.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _STM32MP13SOC_H_
+#define _STM32MP13SOC_H_
+
+#ifndef _ASMLANGUAGE
+
+#include <stm32mp13xx.h>
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _STM32MP13SOC_H_ */
diff --git a/soc/st/stm32/stm32n6x/CMakeLists.txt b/soc/st/stm32/stm32n6x/CMakeLists.txt
new file mode 100644
index 00000000000..48adb916644
--- /dev/null
+++ b/soc/st/stm32/stm32n6x/CMakeLists.txt
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(${ZEPHYR_BASE}/drivers)
+zephyr_sources(
+  soc.c
+  )
+
+zephyr_include_directories(.)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
+
+if(${CMAKE_HOST_SYSTEM_NAME} STREQUAL Windows)
+  set(SIGNING_TOOL STM32_SigningTool_CLI.exe)
+else()
+  set(SIGNING_TOOL STM32_SigningTool_CLI)
+endif()
+
+find_file(SIGNING_TOOL_FIND ${SIGNING_TOOL})
+if(SIGNING_TOOL_FIND STREQUAL SIGNING_TOOL_FIND-NOTFOUND)
+  message(WARNING "
+  Signing Image tool (${SIGNING_TOOL}) is not available.
+  Signed image will not be generated.
+  You won't be able to run application on the board.
+  Refer to board documentation for more information")
+else()
+  set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
+    COMMAND ${SIGNING_TOOL}
+    -in ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.bin
+    -nk -t fsbl -hv 2.3
+    -o ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.signed.bin
+    -dump ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.signed.bin
+    WORKING_DIRECTORY ${PROJECT_BINARY_DIR}
+  )
+
+  set_property(TARGET runners_yaml_props_target PROPERTY bin_file ${CONFIG_KERNEL_BIN_NAME}.signed.bin)
+endif()
diff --git a/soc/st/stm32/stm32n6x/Kconfig b/soc/st/stm32/stm32n6x/Kconfig
new file mode 100644
index 00000000000..d95a4b04e0f
--- /dev/null
+++ b/soc/st/stm32/stm32n6x/Kconfig
@@ -0,0 +1,23 @@
+# ST Microelectronics STM32N6 MCU series
+
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_STM32N6X
+	select ARM
+	select CPU_CORTEX_M55
+	select ARM_TRUSTZONE_M
+	select CPU_HAS_ARM_SAU
+	select CPU_HAS_ARM_MPU
+	select CPU_HAS_FPU
+	select ARMV8_M_DSP
+	select CPU_CORTEX_M_HAS_DWT
+	select HAS_STM32CUBE
+	select INIT_ARCH_HW_AT_BOOT
+	select SOC_RESET_HOOK
+	select SOC_EARLY_INIT_HOOK
+	select TRUSTED_EXECUTION_SECURE
+	select BUILD_OUTPUT_BIN
+
+config STM32N6_BOOT_SERIAL
+	bool "Serial boot target (USB)"
diff --git a/soc/st/stm32/stm32n6x/Kconfig.defconfig b/soc/st/stm32/stm32n6x/Kconfig.defconfig
new file mode 100644
index 00000000000..2e9856e8b02
--- /dev/null
+++ b/soc/st/stm32/stm32n6x/Kconfig.defconfig
@@ -0,0 +1,17 @@
+# ST Microelectronics STM32N6 MCU series
+
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_STM32N6X
+
+rsource "Kconfig.defconfig.stm32n6*"
+
+DT_STM32_CPU_CLOCK_PATH := $(dt_nodelabel_path,cpusw)
+DT_STM32_CPU_CLOCK_FREQ := $(dt_node_int_prop_int,$(DT_STM32_CPU_CLOCK_PATH),clock-frequency)
+
+# For STM32N6, override the value defined in STM32 Kconfig to use CPU clock frequency
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default "$(DT_STM32_CPU_CLOCK_FREQ)" if "$(dt_nodelabel_enabled,cpusw)"
+
+endif # SOC_SERIES_STM32N6X
diff --git a/soc/st/stm32/stm32n6x/Kconfig.defconfig.stm32n657xx b/soc/st/stm32/stm32n6x/Kconfig.defconfig.stm32n657xx
new file mode 100644
index 00000000000..910e6426690
--- /dev/null
+++ b/soc/st/stm32/stm32n6x/Kconfig.defconfig.stm32n657xx
@@ -0,0 +1,11 @@
+# ST Microelectronics STM32N6 MCU series
+
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32N657XX
+
+config NUM_IRQS
+	default 194
+
+endif # SOC_STM32N657XX
diff --git a/soc/st/stm32/stm32n6x/Kconfig.soc b/soc/st/stm32/stm32n6x/Kconfig.soc
new file mode 100644
index 00000000000..71879c0848a
--- /dev/null
+++ b/soc/st/stm32/stm32n6x/Kconfig.soc
@@ -0,0 +1,18 @@
+# ST Microelectronics STM32N6 MCU series
+
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_STM32N6X
+	bool
+	select SOC_FAMILY_STM32
+
+config SOC_SERIES
+	default "stm32n6x" if SOC_SERIES_STM32N6X
+
+config SOC_STM32N657XX
+	bool
+	select SOC_SERIES_STM32N6X
+
+config SOC
+	default "stm32n657xx" if SOC_STM32N657XX
diff --git a/soc/st/stm32/stm32n6x/soc.c b/soc/st/stm32/stm32n6x/soc.c
new file mode 100644
index 00000000000..d3bae6eeff8
--- /dev/null
+++ b/soc/st/stm32/stm32n6x/soc.c
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief System/hardware module for STM32N6 processor
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/init.h>
+#include <zephyr/cache.h>
+#include <zephyr/logging/log.h>
+
+#include <stm32_ll_bus.h>
+#include <stm32_ll_pwr.h>
+#include <stm32_ll_icache.h>
+
+#include <cmsis_core.h>
+
+#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
+LOG_MODULE_REGISTER(soc);
+
+extern char _vector_start[];
+void *g_pfnVectors = (void *)_vector_start;
+
+#if defined(CONFIG_SOC_RESET_HOOK)
+void soc_reset_hook(void)
+{
+	/* This is provided by STM32Cube HAL */
+	SystemInit();
+}
+#endif
+
+/**
+ * @brief Perform basic hardware initialization at boot.
+ *
+ * This needs to be run from the very beginning.
+ *
+ * @return 0
+ */
+void soc_early_init_hook(void)
+{
+	/* Enable caches */
+	sys_cache_instr_enable();
+	sys_cache_data_enable();
+
+	/* Update CMSIS SystemCoreClock variable (HCLK) */
+	/* At reset, system core clock is set to 64 MHz from HSI */
+	SystemCoreClock = 64000000;
+
+	/* Enable PWR */
+	LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
+
+	/* Set the main internal Regulator output voltage for best performance */
+	LL_PWR_SetRegulVoltageScaling(LL_PWR_REGU_VOLTAGE_SCALE0);
+
+	/* Enable IOs */
+	LL_PWR_EnableVddIO2();
+	LL_PWR_EnableVddIO3();
+	LL_PWR_EnableVddIO4();
+	LL_PWR_EnableVddIO5();
+
+	/* Set Vdd IO2 and IO3 to 1.8V */
+	LL_PWR_SetVddIO2VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_1V8);
+	LL_PWR_SetVddIO3VoltageRange(LL_PWR_VDDIO_VOLTAGE_RANGE_1V8);
+}
diff --git a/soc/st/stm32/stm32n6x/soc.h b/soc/st/stm32/stm32n6x/soc.h
new file mode 100644
index 00000000000..9274a7db70b
--- /dev/null
+++ b/soc/st/stm32/stm32n6x/soc.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file SoC configuration macros for the STM32N6 family processors.
+ *
+ */
+
+
+#ifndef _STM32N6_SOC_H_
+#define _STM32N6_SOC_H_
+
+#ifndef _ASMLANGUAGE
+
+#include <stm32n6xx.h>
+
+#endif /* !_ASMLANGUAGE */
+
+#endif /* _STM32N6_SOC_H_ */
diff --git a/soc/st/stm32/stm32u5x/Kconfig.defconfig b/soc/st/stm32/stm32u5x/Kconfig.defconfig
index 61771d8951e..55a18e69ad0 100644
--- a/soc/st/stm32/stm32u5x/Kconfig.defconfig
+++ b/soc/st/stm32/stm32u5x/Kconfig.defconfig
@@ -10,6 +10,19 @@ rsource "Kconfig.defconfig.stm32u5*"
 config ROM_START_OFFSET
 	default 0x400 if BOOTLOADER_MCUBOOT
 
+config ICACHE
+	default y
+
+config DCACHE
+	default y
+
+config CACHE_MANAGEMENT
+	default y
+
+choice CACHE_TYPE
+	default EXTERNAL_CACHE
+endchoice
+
 if STM32_STOP3_LP_MODE
 
 config COUNTER
diff --git a/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5g9xx b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5g9xx
new file mode 100644
index 00000000000..635fbdd476f
--- /dev/null
+++ b/soc/st/stm32/stm32u5x/Kconfig.defconfig.stm32u5g9xx
@@ -0,0 +1,11 @@
+# STMicroelectronics STM32U5G9XX MCU
+
+# Copyright (c) 2025 Charles Dias
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32U5G9XX
+
+config NUM_IRQS
+	default 141
+
+endif # SOC_STM32U5G9XX
diff --git a/soc/st/stm32/stm32u5x/Kconfig.soc b/soc/st/stm32/stm32u5x/Kconfig.soc
index b3360e9ac10..14f80d74aa7 100644
--- a/soc/st/stm32/stm32u5x/Kconfig.soc
+++ b/soc/st/stm32/stm32u5x/Kconfig.soc
@@ -3,6 +3,7 @@
 # Copyright (c) 2021 Linaro Limited
 # Copyright (c) 2023 PSICONTROL nv
 # Copyright (c) 2023 STMicroelectronics
+# Copyright (c) 2025 Charles Dias
 # SPDX-License-Identifier: Apache-2.0
 
 config SOC_SERIES_STM32U5X
@@ -40,9 +41,14 @@ config SOC_STM32U5A9XX
 	bool
 	select SOC_SERIES_STM32U5X
 
+config SOC_STM32U5G9XX
+	bool
+	select SOC_SERIES_STM32U5X
+
 config SOC
 	default "stm32u5a5xx" if SOC_STM32U5A5XX
 	default "stm32u5a9xx" if SOC_STM32U5A9XX
+	default "stm32u5g9xx" if SOC_STM32U5G9XX
 	default "stm32u545xx" if SOC_STM32U545XX
 	default "stm32u575xx" if SOC_STM32U575XX
 	default "stm32u585xx" if SOC_STM32U585XX
diff --git a/soc/st/stm32/stm32u5x/power.c b/soc/st/stm32/stm32u5x/power.c
index 22f12dc57bb..7ee34394883 100644
--- a/soc/st/stm32/stm32u5x/power.c
+++ b/soc/st/stm32/stm32u5x/power.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <zephyr/kernel.h>
+#include <zephyr/cache.h>
 #include <zephyr/pm/pm.h>
 #include <soc.h>
 #include <zephyr/init.h>
@@ -12,7 +13,6 @@
 #include <stm32u5xx_ll_bus.h>
 #include <stm32u5xx_ll_cortex.h>
 #include <stm32u5xx_ll_pwr.h>
-#include <stm32u5xx_ll_icache.h>
 #include <stm32u5xx_ll_rcc.h>
 #include <stm32u5xx_ll_system.h>
 #include <clock_control/clock_stm32_ll_common.h>
@@ -35,22 +35,6 @@ static void pwr_stop3_isr(const struct device *dev)
 	/* Clear all wake-up flags */
 	LL_PWR_ClearFlag_WU();
 }
-
-static void disable_cache(void)
-{
-	/* Disabling ICACHE */
-	LL_ICACHE_Disable();
-	while (LL_ICACHE_IsEnabled() == 1U) {
-	}
-
-	/* Wait until ICACHE_SR.BUSYF is cleared */
-	while (LL_ICACHE_IsActiveFlag_BUSY() == 1U) {
-	}
-
-	/* Wait until ICACHE_SR.BSYENDF is set */
-	while (LL_ICACHE_IsActiveFlag_BSYEND() == 0U) {
-	}
-}
 #endif
 
 void set_mode_stop(uint8_t substate_id)
@@ -82,7 +66,7 @@ void set_mode_stop(uint8_t substate_id)
 		LL_PWR_ClearFlag_SB();
 		LL_PWR_ClearFlag_WU();
 
-		disable_cache();
+		sys_cache_instr_disable();
 
 		LL_PWR_SetPowerMode(LL_PWR_STOP3_MODE);
 		break;
@@ -135,10 +119,7 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 		} else if (substate_id == 4) {
 			stm32_clock_control_standby_exit();
 
-			LL_ICACHE_SetMode(LL_ICACHE_1WAY);
-			LL_ICACHE_Enable();
-			while (LL_ICACHE_IsEnabled() == 0U) {
-			}
+			sys_cache_instr_enable();
 
 			LL_LPM_DisableSleepOnExit();
 			LL_LPM_EnableSleep();
diff --git a/soc/st/stm32/stm32u5x/soc.c b/soc/st/stm32/stm32u5x/soc.c
index 131279dabae..5263db29c37 100644
--- a/soc/st/stm32/stm32u5x/soc.c
+++ b/soc/st/stm32/stm32u5x/soc.c
@@ -10,10 +10,10 @@
  */
 
 #include <zephyr/device.h>
+#include <zephyr/cache.h>
 #include <zephyr/init.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
-#include <stm32_ll_icache.h>
 #include <zephyr/logging/log.h>
 
 #include <cmsis_core.h>
@@ -29,9 +29,7 @@ extern void stm32_power_init(void);
  */
 void soc_early_init_hook(void)
 {
-	/* Enable instruction cache in 1-way (direct mapped cache) */
-	LL_ICACHE_SetMode(LL_ICACHE_1WAY);
-	LL_ICACHE_Enable();
+	sys_cache_instr_enable();
 
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 4 MHz from MSIS */
diff --git a/soc/st/stm32/stm32wb0x/Kconfig b/soc/st/stm32/stm32wb0x/Kconfig
index 5816f0b83b4..2533ed349e9 100644
--- a/soc/st/stm32/stm32wb0x/Kconfig
+++ b/soc/st/stm32/stm32wb0x/Kconfig
@@ -10,6 +10,7 @@ config SOC_SERIES_STM32WB0X
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select CPU_HAS_ARM_MPU
 	select HAS_STM32CUBE
+	select SOC_EARLY_INIT_HOOK
 	# WB0x has a ROM bootloader executed at reset,
 	# which makes the following option required
 	select INIT_ARCH_HW_AT_BOOT
diff --git a/soc/st/stm32/stm32wb0x/Kconfig.defconfig b/soc/st/stm32/stm32wb0x/Kconfig.defconfig
index a0079e8b2a3..19e70895b92 100644
--- a/soc/st/stm32/stm32wb0x/Kconfig.defconfig
+++ b/soc/st/stm32/stm32wb0x/Kconfig.defconfig
@@ -8,6 +8,8 @@ if SOC_SERIES_STM32WB0X
 config NUM_IRQS
 	default 32
 
+if BT
+
 config BT_AUTO_PHY_UPDATE
 	default n
 
@@ -17,4 +19,9 @@ config BT_AUTO_DATA_LEN_UPDATE
 config BT_HCI_ACL_FLOW_CONTROL
 	default n
 
+config MAIN_STACK_SIZE
+	default 1600
+
+endif # BT
+
 endif # SOC_SERIES_STM32WB0X
diff --git a/soc/st/stm32/stm32wb0x/soc.c b/soc/st/stm32/stm32wb0x/soc.c
index 8cac3ca231e..758652781a7 100644
--- a/soc/st/stm32/stm32wb0x/soc.c
+++ b/soc/st/stm32/stm32wb0x/soc.c
@@ -146,12 +146,9 @@ static void configure_smps(void)
 /**
  * @brief Perform basic hardware initialization at boot.
  *
- * This needs to be run from the very beginning,
- * so the init priority has to be 0 (zero).
- *
- * @return 0
+ * This needs to be run from the very beginning.
  */
-static int stm32wb0_init(void)
+void soc_early_init_hook(void)
 {
 	/* Update CMSIS SystemCoreClock variable (CLK_SYS) */
 	/* On reset, the 64MHz HSI is selected as input to
@@ -181,8 +178,4 @@ static int stm32wb0_init(void)
 
 	/* Configure SMPS step-down converter */
 	configure_smps();
-
-	return 0;
 }
-
-SYS_INIT(stm32wb0_init, PRE_KERNEL_1, 0);
diff --git a/soc/st/stm32/stm32wbax/Kconfig.defconfig b/soc/st/stm32/stm32wbax/Kconfig.defconfig
index 88e41074518..498292d79ce 100644
--- a/soc/st/stm32/stm32wbax/Kconfig.defconfig
+++ b/soc/st/stm32/stm32wbax/Kconfig.defconfig
@@ -7,6 +7,16 @@ if SOC_SERIES_STM32WBAX
 
 rsource "Kconfig.defconfig.stm32wba*"
 
+config ICACHE
+	default y
+
+config CACHE_MANAGEMENT
+	default y
+
+choice CACHE_TYPE
+	default EXTERNAL_CACHE
+endchoice
+
 config STM32_LPTIM_TIMER
 	default y if PM
 
diff --git a/soc/st/stm32/stm32wbax/Kconfig.defconfig.stm32wba65xx b/soc/st/stm32/stm32wbax/Kconfig.defconfig.stm32wba65xx
new file mode 100644
index 00000000000..bd811b035ef
--- /dev/null
+++ b/soc/st/stm32/stm32wbax/Kconfig.defconfig.stm32wba65xx
@@ -0,0 +1,11 @@
+# ST Microelectronics STM32WBA65XX MCU
+
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_STM32WBA65XX
+
+config NUM_IRQS
+	default 82
+
+endif # SOC_STM32WBA65XX
diff --git a/soc/st/stm32/stm32wbax/Kconfig.soc b/soc/st/stm32/stm32wbax/Kconfig.soc
index 104a3923989..cee2f81308f 100644
--- a/soc/st/stm32/stm32wbax/Kconfig.soc
+++ b/soc/st/stm32/stm32wbax/Kconfig.soc
@@ -18,6 +18,11 @@ config SOC_STM32WBA55XX
 	bool
 	select SOC_SERIES_STM32WBAX
 
+config SOC_STM32WBA65XX
+	bool
+	select SOC_SERIES_STM32WBAX
+
 config SOC
 	default "stm32wba52xx" if SOC_STM32WBA52XX
 	default "stm32wba55xx" if SOC_STM32WBA55XX
+	default "stm32wba65xx" if SOC_STM32WBA65XX
diff --git a/soc/st/stm32/stm32wbax/hci_if/host_stack_if.c b/soc/st/stm32/stm32wbax/hci_if/host_stack_if.c
index 6cc224cc60a..2c9f1e57b2c 100644
--- a/soc/st/stm32/stm32wbax/hci_if/host_stack_if.c
+++ b/soc/st/stm32/stm32wbax/hci_if/host_stack_if.c
@@ -7,38 +7,36 @@
 #include <zephyr/kernel.h>
 #include <zephyr/init.h>
 
-#include "app_conf.h"
 #include "blestack.h"
 #include "bpka.h"
 #include "ll_intf.h"
 
-K_MUTEX_DEFINE(ble_ctlr_stack_mutex);
-struct k_work_q ble_ctlr_work_q, ll_work_q;
-struct k_work ble_ctlr_stack_work, bpka_work;
+K_MUTEX_DEFINE(ble_ctrl_stack_mutex);
+struct k_work_q ble_ctrl_work_q, ll_work_q;
+struct k_work ble_ctrl_stack_work, bpka_work;
 
 uint8_t ll_state_busy;
 
-#define BLE_CTLR_TASK_STACK_SIZE (256 * 7)
-#define LL_TASK_STACK_SIZE (256 * 7)
-#define BLE_CTLR_TASK_PRIO	 (14)
-#define LL_TASK_PRIO (14)
+/* TODO: More tests to be done to optimize thread stacks' sizes */
+#define BLE_CTRL_THREAD_STACK_SIZE (256 * 7)
+#define LL_THREAD_STACK_SIZE (256 * 7)
+#define BLE_CTRL_THREAD_PRIO (14)
+/* The LL thread has higher priority than the BLE CTRL thread and the Zephyr BLE stack threads */
+#define LL_THREAD_PRIO (4)
 
-K_THREAD_STACK_DEFINE(ble_ctlr_work_area, BLE_CTLR_TASK_STACK_SIZE);
-K_THREAD_STACK_DEFINE(ll_work_area, LL_TASK_STACK_SIZE);
+K_THREAD_STACK_DEFINE(ble_ctrl_work_area, BLE_CTRL_THREAD_STACK_SIZE);
+K_THREAD_STACK_DEFINE(ll_work_area, LL_THREAD_STACK_SIZE);
 
-void HostStack_Process(void)
-{
-	k_work_submit_to_queue(&ble_ctlr_work_q, &ble_ctlr_stack_work);
-}
+void HostStack_Process(void);
 
-static void ble_ctlr_stack_handler(struct k_work *work)
+static void ble_ctrl_stack_handler(struct k_work *work)
 {
-	uint8_t running = 0x0;
+	uint8_t running = 0x00;
 	change_state_options_t options;
 
-	k_mutex_lock(&ble_ctlr_stack_mutex, K_FOREVER);
+	k_mutex_lock(&ble_ctrl_stack_mutex, K_FOREVER);
 	running = BleStack_Process();
-	k_mutex_unlock(&ble_ctlr_stack_mutex);
+	k_mutex_unlock(&ble_ctrl_stack_mutex);
 
 	if (ll_state_busy == 1) {
 		options.combined_value = 0x0F;
@@ -51,32 +49,37 @@ static void ble_ctlr_stack_handler(struct k_work *work)
 	}
 }
 
-void BPKACB_Process(void)
-{
-	k_work_submit_to_queue(&ble_ctlr_work_q, &bpka_work);
-}
-
 static void bpka_work_handler(struct k_work *work)
 {
 	BPKA_BG_Process();
 }
 
-static int stm32wba_ble_ctlr_init(void)
+static int stm32wba_ble_ctrl_init(void)
 {
-	k_work_queue_init(&ble_ctlr_work_q);
-	k_work_queue_start(&ble_ctlr_work_q, ble_ctlr_work_area,
-				K_THREAD_STACK_SIZEOF(ble_ctlr_work_area),
-				BLE_CTLR_TASK_PRIO, NULL);
+	k_work_queue_init(&ble_ctrl_work_q);
+	k_work_queue_start(&ble_ctrl_work_q, ble_ctrl_work_area,
+			   K_THREAD_STACK_SIZEOF(ble_ctrl_work_area),
+			   BLE_CTRL_THREAD_PRIO, NULL);
 
 	k_work_queue_init(&ll_work_q);
 	k_work_queue_start(&ll_work_q, ll_work_area,
-				K_THREAD_STACK_SIZEOF(ll_work_area),
-				LL_TASK_PRIO, NULL);
+			   K_THREAD_STACK_SIZEOF(ll_work_area),
+			   LL_THREAD_PRIO, NULL);
 
-	k_work_init(&ble_ctlr_stack_work, &ble_ctlr_stack_handler);
+	k_work_init(&ble_ctrl_stack_work, &ble_ctrl_stack_handler);
 	k_work_init(&bpka_work, &bpka_work_handler);
 
 	return 0;
 }
 
-SYS_INIT(stm32wba_ble_ctlr_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+void HostStack_Process(void)
+{
+	k_work_submit_to_queue(&ble_ctrl_work_q, &ble_ctrl_stack_work);
+}
+
+void BPKACB_Process(void)
+{
+	k_work_submit_to_queue(&ble_ctrl_work_q, &bpka_work);
+}
+
+SYS_INIT(stm32wba_ble_ctrl_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
diff --git a/soc/st/stm32/stm32wbax/hci_if/linklayer_plat_adapt.c b/soc/st/stm32/stm32wbax/hci_if/linklayer_plat_adapt.c
index b482c0b86fc..a5d06d591eb 100644
--- a/soc/st/stm32/stm32wbax/hci_if/linklayer_plat_adapt.c
+++ b/soc/st/stm32/stm32wbax/hci_if/linklayer_plat_adapt.c
@@ -29,6 +29,8 @@ volatile int32_t prio_high_isr_counter;
 volatile int32_t prio_low_isr_counter;
 volatile int32_t prio_sys_isr_counter;
 volatile uint32_t local_basepri_value;
+volatile uint8_t irq_counter;
+static uint32_t primask_bit;
 
 /* Radio SW low ISR global variable */
 volatile uint8_t radio_sw_low_isr_is_running_high_prio;
@@ -74,7 +76,7 @@ void radio_high_prio_isr(void)
 
 void radio_low_prio_isr(void)
 {
-	irq_disable((IRQn_Type)RADIO_SW_LOW_INTR_NUM);
+	irq_disable(RADIO_SW_LOW_INTR_NUM);
 
 	low_isr_callback();
 
@@ -85,7 +87,7 @@ void radio_low_prio_isr(void)
 	}
 
 	/* Re-enable SW radio low interrupt */
-	irq_enable((IRQn_Type)RADIO_SW_LOW_INTR_NUM);
+	irq_enable(RADIO_SW_LOW_INTR_NUM);
 
 	ISR_DIRECT_PM();
 }
@@ -96,22 +98,22 @@ void link_layer_register_isr(void)
 	ARM_IRQ_DIRECT_DYNAMIC_CONNECT(RADIO_INTR_NUM, 0, 0, reschedule);
 
 	/* Ensure the IRQ is disabled before enabling it at run time */
-	irq_disable((IRQn_Type)RADIO_INTR_NUM);
+	irq_disable(RADIO_INTR_NUM);
 
-	irq_connect_dynamic((IRQn_Type)RADIO_INTR_NUM, RADIO_INTR_PRIO_HIGH_Z,
+	irq_connect_dynamic(RADIO_INTR_NUM, RADIO_INTR_PRIO_HIGH_Z,
 			    (void (*)(const void *))radio_high_prio_isr, NULL, 0);
 
-	irq_enable((IRQn_Type)RADIO_INTR_NUM);
+	irq_enable(RADIO_INTR_NUM);
 
 	ARM_IRQ_DIRECT_DYNAMIC_CONNECT(RADIO_SW_LOW_INTR_NUM, 0, 0, reschedule);
 
 	/* Ensure the IRQ is disabled before enabling it at run time */
-	irq_disable((IRQn_Type)RADIO_SW_LOW_INTR_NUM);
+	irq_disable(RADIO_SW_LOW_INTR_NUM);
 
-	irq_connect_dynamic((IRQn_Type)RADIO_SW_LOW_INTR_NUM, RADIO_SW_LOW_INTR_PRIO,
+	irq_connect_dynamic(RADIO_SW_LOW_INTR_NUM, RADIO_SW_LOW_INTR_PRIO,
 			    (void (*)(const void *))radio_low_prio_isr, NULL, 0);
 
-	irq_enable((IRQn_Type)RADIO_SW_LOW_INTR_NUM);
+	irq_enable(RADIO_SW_LOW_INTR_NUM);
 }
 
 
@@ -119,24 +121,20 @@ void LINKLAYER_PLAT_TriggerSwLowIT(uint8_t priority)
 {
 	uint8_t low_isr_priority = RADIO_INTR_PRIO_LOW_Z;
 
-	LOG_DBG("Priotity: %d", priority);
+	LOG_DBG("Priority: %d", priority);
 
 	/* Check if a SW low interrupt as already been raised.
 	 * Nested call far radio low isr are not supported
 	 **/
-
-	if (NVIC_GetActive(RADIO_SW_LOW_INTR_NUM) == 0) {
+	if (NVIC_GetActive((IRQn_Type)RADIO_SW_LOW_INTR_NUM) == 0) {
 		/* No nested SW low ISR, default behavior */
-
 		if (priority == 0) {
 			low_isr_priority = RADIO_SW_LOW_INTR_PRIO;
 		}
-
 		NVIC_SetPriority((IRQn_Type)RADIO_SW_LOW_INTR_NUM, low_isr_priority);
 	} else {
 		/* Nested call detected */
 		/* No change for SW radio low interrupt priority for the moment */
-
 		if (priority != 0) {
 			/* At the end of current SW radio low ISR, this pending SW
 			 * low interrupt will run with RADIO_INTR_PRIO_LOW_Z priority
@@ -153,6 +151,26 @@ void LINKLAYER_PLAT_Assert(uint8_t condition)
 	__ASSERT_NO_MSG(condition);
 }
 
+void LINKLAYER_PLAT_EnableIRQ(void)
+{
+	if (irq_counter > 0) {
+		irq_counter--;
+		if (irq_counter == 0) {
+			__set_PRIMASK(primask_bit);
+		}
+	}
+}
+
+void LINKLAYER_PLAT_DisableIRQ(void)
+{
+	if (irq_counter == 0) {
+		/* Save primask bit at first time interrupts disabling */
+		primask_bit = __get_PRIMASK();
+	}
+	__disable_irq();
+	irq_counter++;
+}
+
 void LINKLAYER_PLAT_EnableSpecificIRQ(uint8_t isr_type)
 {
 
@@ -208,11 +226,23 @@ void LINKLAYER_PLAT_DisableSpecificIRQ(uint8_t isr_type)
 	}
 }
 
+void LINKLAYER_PLAT_EnableRadioIT(void)
+{
+	LOG_DBG("Enable RADIO IRQ");
+	irq_enable(RADIO_INTR_NUM);
+}
+
+void LINKLAYER_PLAT_DisableRadioIT(void)
+{
+	LOG_DBG("Disable RADIO IRQ");
+	irq_disable(RADIO_INTR_NUM);
+}
+
 void LINKLAYER_PLAT_StartRadioEvt(void)
 {
 	__HAL_RCC_RADIO_CLK_SLEEP_ENABLE();
 
-	NVIC_SetPriority(RADIO_INTR_NUM, RADIO_INTR_PRIO_HIGH_Z);
+	NVIC_SetPriority((IRQn_Type)RADIO_INTR_NUM, RADIO_INTR_PRIO_HIGH_Z);
 
 	scm_notifyradiostate(SCM_RADIO_ACTIVE);
 }
@@ -221,7 +251,7 @@ void LINKLAYER_PLAT_StopRadioEvt(void)
 {
 	__HAL_RCC_RADIO_CLK_SLEEP_DISABLE();
 
-	NVIC_SetPriority(RADIO_INTR_NUM, RADIO_INTR_PRIO_LOW_Z);
+	NVIC_SetPriority((IRQn_Type)RADIO_INTR_NUM, RADIO_INTR_PRIO_LOW_Z);
 
 	scm_notifyradiostate(SCM_RADIO_NOT_ACTIVE);
 }
@@ -238,10 +268,23 @@ void LINKLAYER_PLAT_RCOStopClbr(void)
 /* Required only for RCO module usage in the context of LSI2 calibration */
 }
 
+/* TODO: To do when porting the temperature measurement function and thread */
 void LINKLAYER_PLAT_RequestTemperature(void) {}
 
 void LINKLAYER_PLAT_SCHLDR_TIMING_UPDATE_NOT(Evnt_timing_t *p_evnt_timing) {}
 
-void LINKLAYER_PLAT_EnableOSContextSwitch(void) {}
+void LINKLAYER_PLAT_EnableOSContextSwitch(void)
+{
+	/* No implementation is needed. However, this function may be used to notify
+	 * upper layers that the link layer has just finished a critical radio job
+	 * (radio channels' calibration).
+	 **/
+}
 
-void LINKLAYER_PLAT_DisableOSContextSwitch(void) {}
+void LINKLAYER_PLAT_DisableOSContextSwitch(void)
+{
+	/* No implementation is needed. However, this function may be used to notify upper layers
+	 * that the link layer is running a critical radio job (radio channels' calibration);
+	 * A sequence of radio ISRs will appear in the next few milli seconds.
+	 **/
+}
diff --git a/soc/st/stm32/stm32wbax/hci_if/ll_sys_if_adapt.c b/soc/st/stm32/stm32wbax/hci_if/ll_sys_if_adapt.c
index df0342ff1f1..f555304ee4e 100644
--- a/soc/st/stm32/stm32wbax/hci_if/ll_sys_if_adapt.c
+++ b/soc/st/stm32/stm32wbax/hci_if/ll_sys_if_adapt.c
@@ -12,28 +12,32 @@ LOG_MODULE_REGISTER(ll_sys_if_adapt);
 
 #include "ll_sys.h"
 
-extern struct k_mutex ble_ctlr_stack_mutex;
+extern struct k_mutex ble_ctrl_stack_mutex;
 extern struct k_work_q ll_work_q;
 struct k_work ll_sys_work;
 
-void ll_sys_schedule_bg_process(void)
+static void ll_sys_bg_process_handler(struct k_work *work)
 {
-	k_work_submit_to_queue(&ll_work_q, &ll_sys_work);
+	k_mutex_lock(&ble_ctrl_stack_mutex, K_FOREVER);
+	ll_sys_bg_process();
+	k_mutex_unlock(&ble_ctrl_stack_mutex);
 }
 
-void ll_sys_schedule_bg_process_isr(void)
+void ll_sys_schedule_bg_process(void)
 {
 	k_work_submit_to_queue(&ll_work_q, &ll_sys_work);
 }
 
-static void ll_sys_bg_process_handler(struct k_work *work)
+void ll_sys_schedule_bg_process_isr(void)
 {
-	k_mutex_lock(&ble_ctlr_stack_mutex, K_FOREVER);
-	ll_sys_bg_process();
-	k_mutex_unlock(&ble_ctlr_stack_mutex);
+	k_work_submit_to_queue(&ll_work_q, &ll_sys_work);
 }
 
 void ll_sys_bg_process_init(void)
 {
 	k_work_init(&ll_sys_work, &ll_sys_bg_process_handler);
 }
+
+/* TODO: Implement temperature measurement thread after
+ * implementing temperature measurement request function
+ **/
diff --git a/soc/st/stm32/stm32wbax/power.c b/soc/st/stm32/stm32wbax/power.c
index 6fc6e424b85..43fcd67b612 100644
--- a/soc/st/stm32/stm32wbax/power.c
+++ b/soc/st/stm32/stm32wbax/power.c
@@ -4,6 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <zephyr/kernel.h>
+#include <zephyr/cache.h>
 #include <zephyr/pm/pm.h>
 #include <soc.h>
 #include <zephyr/init.h>
@@ -13,7 +14,6 @@
 #include <stm32wbaxx_ll_bus.h>
 #include <stm32wbaxx_ll_cortex.h>
 #include <stm32wbaxx_ll_pwr.h>
-#include <stm32wbaxx_ll_icache.h>
 #include <stm32wbaxx_ll_rcc.h>
 #include <stm32wbaxx_ll_system.h>
 #include <clock_control/clock_stm32_ll_common.h>
@@ -28,22 +28,6 @@ LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
 
 void stm32_power_init(void);
 
-static void disable_cache(void)
-{
-	/* Disabling ICACHE */
-	LL_ICACHE_Disable();
-	while (LL_ICACHE_IsEnabled() == 1U) {
-	}
-
-	/* Wait until ICACHE_SR.BUSYF is cleared */
-	while (LL_ICACHE_IsActiveFlag_BUSY() == 1U) {
-	}
-
-	/* Wait until ICACHE_SR.BSYENDF is set */
-	while (LL_ICACHE_IsActiveFlag_BSYEND() == 0U) {
-	}
-}
-
 static void set_mode_stop(uint8_t substate_id)
 {
 
@@ -53,7 +37,7 @@ static void set_mode_stop(uint8_t substate_id)
 	/* Erratum 2.2.15:
 	 * Disabling ICACHE is required before entering stop mode
 	 */
-	disable_cache();
+	sys_cache_instr_disable();
 
 #ifdef CONFIG_BT_STM32WBA
 	scm_setwaitstates(LP);
@@ -108,7 +92,7 @@ static void set_mode_suspend_to_ram(void)
 	LL_PWR_ClearFlag_WU();
 	LL_RCC_ClearResetFlags();
 
-	disable_cache();
+	sys_cache_instr_disable();
 
 	/* Select standby mode */
 	LL_PWR_SetPowerMode(LL_PWR_MODE_STANDBY);
@@ -161,10 +145,7 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 			/* Erratum 2.2.15:
 			 * Enable ICACHE when exiting stop mode
 			 */
-			LL_ICACHE_SetMode(LL_ICACHE_1WAY);
-			LL_ICACHE_Enable();
-			while (LL_ICACHE_IsEnabled() == 0U) {
-			}
+			sys_cache_instr_enable();
 
 			LL_LPM_DisableSleepOnExit();
 			LL_LPM_EnableSleep();
diff --git a/soc/st/stm32/stm32wbax/soc.c b/soc/st/stm32/stm32wbax/soc.c
index 9e49f8be955..fb54c5b5303 100644
--- a/soc/st/stm32/stm32wbax/soc.c
+++ b/soc/st/stm32/stm32wbax/soc.c
@@ -11,10 +11,10 @@
 
 #include <zephyr/device.h>
 #include <zephyr/init.h>
+#include <zephyr/cache.h>
 #include <stm32_ll_bus.h>
 #include <stm32_ll_pwr.h>
 #include <stm32_ll_rcc.h>
-#include <stm32_ll_icache.h>
 #include <zephyr/arch/cpu.h>
 #include <zephyr/irq.h>
 #include <zephyr/logging/log.h>
@@ -31,9 +31,7 @@ LOG_MODULE_REGISTER(soc);
  */
 void stm32wba_init(void)
 {
-	/* Enable instruction cache in 1-way (direct mapped cache) */
-	LL_ICACHE_SetMode(LL_ICACHE_1WAY);
-	LL_ICACHE_Enable();
+	sys_cache_instr_enable();
 #ifdef CONFIG_STM32_FLASH_PREFETCH
 	__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
 #endif
diff --git a/soc/ti/k3/am6x/CMakeLists.txt b/soc/ti/k3/am6x/CMakeLists.txt
index d5e88b78e25..79e4cd12596 100644
--- a/soc/ti/k3/am6x/CMakeLists.txt
+++ b/soc/ti/k3/am6x/CMakeLists.txt
@@ -2,6 +2,7 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_include_directories(.)
+zephyr_sources(common/ctrl_partitions.c)
 
 if(CONFIG_SOC_AM6234_A53)
   zephyr_sources_ifdef(CONFIG_ARM_MMU a53/mmu_regions.c)
diff --git a/soc/ti/k3/am6x/Kconfig b/soc/ti/k3/am6x/Kconfig
index a28996cc305..2612712d551 100644
--- a/soc/ti/k3/am6x/Kconfig
+++ b/soc/ti/k3/am6x/Kconfig
@@ -9,6 +9,7 @@ config SOC_SERIES_AM6X_A53
 config SOC_SERIES_AM6X_M4
 	select ARM
 	select CPU_CORTEX_M4
+	select CPU_HAS_FPU
 	select CPU_CORTEX_M_HAS_SYSTICK
 	select DYNAMIC_INTERRUPTS
 	select CPU_CORTEX_M_HAS_DWT
@@ -23,13 +24,16 @@ config SOC_SERIES_AM6X_R5
 	select ARM
 	select CPU_CORTEX_R5
 	select CPU_HAS_ARM_MPU
+	select VFP_SP_D16
 	select ARM_CUSTOM_INTERRUPT_CONTROLLER
 	select VIM
 	select TI_DM_TIMER
 	select OPENAMP_RSC_TABLE
 	select UART_NS16550_ACCESS_WORD_ONLY if UART_NS16550
+	select SOC_EARLY_INIT_HOOK
 
 config SOC_PART_NUMBER
+	default "AM6232" if SOC_AM6232_M4
 	default "AM6234" if SOC_AM6234_A53
 	default "AM6234" if SOC_AM6234_M4
 	default "AM6442" if SOC_AM6442_M4
diff --git a/soc/ti/k3/am6x/Kconfig.soc b/soc/ti/k3/am6x/Kconfig.soc
index 2f76accd255..8efcc1ed546 100644
--- a/soc/ti/k3/am6x/Kconfig.soc
+++ b/soc/ti/k3/am6x/Kconfig.soc
@@ -31,6 +31,10 @@ config SOC_AM6234_M4
 	bool
 	select SOC_SERIES_AM6X_M4
 
+config SOC_AM6232_M4
+	bool
+	select SOC_SERIES_AM6X_M4
+
 config SOC_AM6442_M4
 	bool
 	select SOC_SERIES_AM6X_M4
@@ -39,10 +43,20 @@ config SOC_J721E_MAIN_R5F0_0
 	bool
 	select SOC_SERIES_AM6X_R5
 
+config SOC_J722S_MAIN_R5F0_0
+	bool
+	select SOC_SERIES_AM6X_R5
+
+config SOC_J722S_MCU_R5F0_0
+	bool
+	select SOC_SERIES_AM6X_R5
+
 config SOC_SERIES
 	default "am6x" if SOC_SERIES_AM6X
 
 config SOC
+	default "am6232" if SOC_AM6232_M4
 	default "am6234" if SOC_AM6234_M4 || SOC_AM6234_A53
 	default "am6442" if SOC_AM6442_M4
 	default "j721e" if SOC_J721E_MAIN_R5F0_0
+	default "j722s" if SOC_J722S_MAIN_R5F0_0 || SOC_J722S_MCU_R5F0_0
diff --git a/soc/ti/k3/am6x/common/ctrl_partitions.c b/soc/ti/k3/am6x/common/ctrl_partitions.c
new file mode 100644
index 00000000000..83df836e5ce
--- /dev/null
+++ b/soc/ti/k3/am6x/common/ctrl_partitions.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2025 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/device_mmio.h>
+#include <zephyr/arch/common/sys_io.h>
+
+#define KICK0_OFFSET     (0x1008)
+#define KICK1_OFFSET     (0x100C)
+#define KICK0_UNLOCK_VAL (0x68EF3490U)
+#define KICK1_UNLOCK_VAL (0xD172BC5AU)
+#define KICK_LOCK_VAL    (0x0U)
+
+#define CTRL_PARTITION_SIZE        (0x4000)
+#define CTRL_PARTITION(base, part) ((base) + (part) * CTRL_PARTITION_SIZE)
+
+#if defined CONFIG_SOC_AM6442_M4
+#define MCU_PADCFG_BASE (0x4080000)
+#elif defined CONFIG_SOC_AM6234_M4 | defined CONFIG_SOC_AM6232_M4
+#define WKUP_PADCFG_BASE (0x4080000)
+#endif
+
+static const uintptr_t ctrl_partitions[] = {
+#if defined CONFIG_SOC_AM6442_M4
+	CTRL_PARTITION(MCU_PADCFG_BASE, 0),
+	CTRL_PARTITION(MCU_PADCFG_BASE, 1),
+#elif defined CONFIG_SOC_AM6234_M4 | defined CONFIG_SOC_AM6232_M4
+	CTRL_PARTITION(WKUP_PADCFG_BASE, 0),
+	CTRL_PARTITION(WKUP_PADCFG_BASE, 1),
+#endif
+};
+
+void k3_unlock_all_ctrl_partitions(void)
+{
+	ARRAY_FOR_EACH(ctrl_partitions, i) {
+		mm_reg_t base_addr = ctrl_partitions[i];
+
+#ifdef DEVICE_MMIO_IS_IN_RAM
+		device_map(&base_addr, base_addr, sizeof(base_addr), K_MEM_CACHE_NONE);
+#endif
+
+		sys_write32(KICK0_UNLOCK_VAL, base_addr + KICK0_OFFSET);
+		sys_write32(KICK1_UNLOCK_VAL, base_addr + KICK1_OFFSET);
+	}
+}
diff --git a/soc/ti/k3/am6x/common/ctrl_partitions.h b/soc/ti/k3/am6x/common/ctrl_partitions.h
new file mode 100644
index 00000000000..a2b1b0d8839
--- /dev/null
+++ b/soc/ti/k3/am6x/common/ctrl_partitions.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Texas Instruments Incorporated
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __K3_CTRL_PARTITIONS_H_
+#define __K3_CTRL_PARTITIONS_H_
+
+void k3_unlock_all_ctrl_partitions(void);
+
+#endif /* __K3_CTRL_PARTITIONS_H */
diff --git a/soc/ti/k3/am6x/m4/linker.ld b/soc/ti/k3/am6x/m4/linker.ld
index 5e478a0541f..dfe71053cfe 100644
--- a/soc/ti/k3/am6x/m4/linker.ld
+++ b/soc/ti/k3/am6x/m4/linker.ld
@@ -13,6 +13,6 @@ SECTIONS
 	SECTION_PROLOGUE(.resource_table,, SUBALIGN(4))
 	{
 		KEEP(*(.resource_table*))
-	} GROUP_LINK_IN(DDR)
+	} GROUP_LINK_IN(RSC_TABLE)
 #endif
 }
diff --git a/soc/ti/k3/am6x/m4/soc.c b/soc/ti/k3/am6x/m4/soc.c
index f3d5e330071..40dc0a7c92a 100644
--- a/soc/ti/k3/am6x/m4/soc.c
+++ b/soc/ti/k3/am6x/m4/soc.c
@@ -4,67 +4,40 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <common/ctrl_partitions.h>
 #include <zephyr/arch/cpu.h>
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <soc.h>
 
-#define ADDR_TRANSLATE_RAT_BASE_ADDR		(0x044200000u)
-#define PINCTRL_BASE_ADDR			(0x4080000u)
-#define KICK0_UNLOCK_VAL			(0x68EF3490U)
-#define KICK1_UNLOCK_VAL			(0xD172BC5AU)
-#define CSL_MCU_PADCONFIG_LOCK0_KICK0_OFFSET	(0x1008)
-#define CSL_MCU_PADCONFIG_LOCK1_KICK0_OFFSET	(0x5008)
+#define ADDR_TRANSLATE_RAT_BASE_ADDR (0x44200000u)
 
 static struct address_trans_region_config am6x_region_config[] = {
 	{
-		.system_addr = 0x0u,
-		.local_addr = 0x80000000u,
-		.size = address_trans_region_size_512M,
+		.system_addr = 0x00000000u,
+		.local_addr =  0x60000000u,
+		.size = address_trans_region_size_256M,
 	},
 	{
-		.local_addr = 0xA0000000u,
 		.system_addr = 0x20000000u,
+		.local_addr =  0xc0000000u,
 		.size = address_trans_region_size_512M,
 	},
 	{
-		.local_addr = 0xC0000000u,
 		.system_addr = 0x40000000u,
-		.size = address_trans_region_size_512M,
-	},
-	{
-		.local_addr = 0x60000000u,
-		.system_addr = 0x60000000u,
-		.size = address_trans_region_size_512M,
+		.local_addr =  0x70000000u,
+		.size = address_trans_region_size_256M,
 	},
-
 /*
  * Add regions here if you want to map more memory.
  */
 };
 
-static void am6x_mmr_unlock(void)
-{
-	uint32_t baseAddr = PINCTRL_BASE_ADDR;
-	uintptr_t kickAddr;
-
-	/* Lock 0 */
-	kickAddr = baseAddr + CSL_MCU_PADCONFIG_LOCK0_KICK0_OFFSET;
-	sys_write32(KICK0_UNLOCK_VAL, kickAddr);   /* KICK 0 */
-	kickAddr = kickAddr + sizeof(uint32_t *);
-	sys_write32(KICK1_UNLOCK_VAL, kickAddr);   /* KICK 1 */
-
-	/* Lock 1 */
-	kickAddr = baseAddr + CSL_MCU_PADCONFIG_LOCK1_KICK0_OFFSET;
-	sys_write32(KICK0_UNLOCK_VAL, kickAddr);   /* KICK 0 */
-	kickAddr = kickAddr + sizeof(uint32_t *);
-	sys_write32(KICK1_UNLOCK_VAL, kickAddr);   /* KICK 1 */
-}
-
 void soc_early_init_hook(void)
 {
 	sys_mm_drv_ti_rat_init(am6x_region_config, ADDR_TRANSLATE_RAT_BASE_ADDR,
-		ARRAY_SIZE(am6x_region_config));
-	am6x_mmr_unlock();
+			       ARRAY_SIZE(am6x_region_config));
+
+	k3_unlock_all_ctrl_partitions();
 }
diff --git a/soc/ti/k3/am6x/r5/soc.c b/soc/ti/k3/am6x/r5/soc.c
index 8190f43353f..3142fdcd96f 100644
--- a/soc/ti/k3/am6x/r5/soc.c
+++ b/soc/ti/k3/am6x/r5/soc.c
@@ -8,6 +8,7 @@
 #include <zephyr/fatal.h>
 
 #include "soc.h"
+#include <common/ctrl_partitions.h>
 
 unsigned int z_soc_irq_get_active(void)
 {
@@ -47,3 +48,8 @@ int z_soc_irq_is_enabled(unsigned int irq)
 	/* Check if interrupt is enabled */
 	return z_vim_irq_is_enabled(irq);
 }
+
+void soc_early_init_hook(void)
+{
+	k3_unlock_all_ctrl_partitions();
+}
diff --git a/soc/ti/k3/soc.yml b/soc/ti/k3/soc.yml
index b8832d4f6b4..dbfc4d30f4b 100644
--- a/soc/ti/k3/soc.yml
+++ b/soc/ti/k3/soc.yml
@@ -3,6 +3,9 @@ family:
   series:
   - name: am6x
     socs:
+    - name: am6232
+      cpuclusters:
+      - name: m4
     - name: am6234
       cpuclusters:
       - name: m4
@@ -13,3 +16,7 @@ family:
     - name: j721e
       cpuclusters:
       - name: main_r5f0_0
+    - name: j722s
+      cpuclusters:
+      - name: main_r5f0_0
+      - name: mcu_r5f0_0
diff --git a/soc/ti/simplelink/Kconfig b/soc/ti/simplelink/Kconfig
index af4cd5f7433..e4e57d9a9dd 100644
--- a/soc/ti/simplelink/Kconfig
+++ b/soc/ti/simplelink/Kconfig
@@ -12,4 +12,10 @@ config HAS_TI_CCFG
 	  Selected when CCFG (Customer Configuration) registers
 	  appear at the end of flash
 
+config TI_SIMPLELINK_DYNAMIC_DPL_OBJECTS
+	bool
+	help
+	  Turn on dynamic memory allocation for DPL objects. Reserves
+	  extra memory for this.
+
 endif # SOC_FAMILY_TI_SIMPLELINK
diff --git a/soc/ti/simplelink/cc23x0/CMakeLists.txt b/soc/ti/simplelink/cc23x0/CMakeLists.txt
new file mode 100644
index 00000000000..b8e02adbd58
--- /dev/null
+++ b/soc/ti/simplelink/cc23x0/CMakeLists.txt
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+# Copyright (c) 2024 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(soc.c)
+zephyr_sources(ccfg.c)
+zephyr_include_directories(.)
+
+zephyr_linker_sources_ifdef(CONFIG_HAS_TI_CCFG SECTIONS ccfg.ld)
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
diff --git a/soc/ti/simplelink/cc23x0/Kconfig b/soc/ti/simplelink/cc23x0/Kconfig
new file mode 100644
index 00000000000..fa1c2c45af3
--- /dev/null
+++ b/soc/ti/simplelink/cc23x0/Kconfig
@@ -0,0 +1,49 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+# Copyright (c) 2024 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_CC23X0
+	select ARM
+	select CPU_CORTEX_M0PLUS
+	select CPU_CORTEX_M_HAS_VTOR
+	select SOC_RESET_HOOK
+	select TICKLESS_KERNEL
+	select DYNAMIC_INTERRUPTS
+	select HAS_CC23X0_SDK
+	select HAS_TI_CCFG
+	select TI_SIMPLELINK_DYNAMIC_DPL_OBJECTS
+	select EVENTS
+	select DYNAMIC_THREAD
+	select DYNAMIC_THREAD_ALLOC
+	select THREAD_STACK_INFO
+	select BUILD_OUTPUT_HEX
+	select BUILD_NO_GAP_FILL
+
+menu "Bootloader Configuration"
+depends on SOC_SERIES_CC23X0
+
+choice CC23X0_BLDR_VTOR_TYPE
+	prompt "Pointer to user bootloader vector table"
+	default CC23X0_BLDR_VTOR_TYPE_UNDEF
+
+config CC23X0_BLDR_VTOR_TYPE_UNDEF
+	bool "ROM serial bootloader"
+
+config CC23X0_BLDR_VTOR_TYPE_FORBID
+	bool "No bootloader invoked"
+
+config CC23X0_BLDR_VTOR_TYPE_USE_FCFG
+	bool "Use factory configuration"
+
+config CC23X0_BLDR_VTOR_TYPE_FLASH
+	bool "Use valid main flash address"
+
+endchoice # CC23X0_BLDR_VTOR_TYPE
+
+config CC23X0_BLDR_ENABLED
+	bool "Bootloader commands"
+	help
+	  If n, bootloader ignores all commands.
+
+endmenu # "Bootloader Configuration"
diff --git a/soc/ti/simplelink/cc23x0/Kconfig.defconfig b/soc/ti/simplelink/cc23x0/Kconfig.defconfig
new file mode 100644
index 00000000000..442c9b09c9e
--- /dev/null
+++ b/soc/ti/simplelink/cc23x0/Kconfig.defconfig
@@ -0,0 +1,19 @@
+# Texas Instruments SimpleLink CC23X0
+
+# Copyright (c) 2024 Texas Instruments Incorporated
+# Copyright (c) 2024 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_CC23X0
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 1000
+
+config NUM_IRQS
+	default 19
+
+endif
diff --git a/soc/ti/simplelink/cc23x0/Kconfig.soc b/soc/ti/simplelink/cc23x0/Kconfig.soc
new file mode 100644
index 00000000000..6817c069f93
--- /dev/null
+++ b/soc/ti/simplelink/cc23x0/Kconfig.soc
@@ -0,0 +1,22 @@
+# Copyright (c) 2024 Texas Instruments Incorporated
+# Copyright (c) 2024 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_CC23X0
+	bool
+	select SOC_FAMILY_TI_SIMPLELINK
+	help
+	  Enable support for TI SimpleLink CC23X0 series SOCs.
+
+config SOC_CC2340R5
+	bool
+	select SOC_SERIES_CC23X0
+	help
+	  CC2340R5
+
+config SOC_SERIES
+	default "cc23x0" if SOC_SERIES_CC23X0
+
+config SOC
+	default "cc2340r5" if SOC_CC2340R5
diff --git a/soc/ti/simplelink/cc23x0/ccfg.c b/soc/ti/simplelink/cc23x0/ccfg.c
new file mode 100644
index 00000000000..08031e40adc
--- /dev/null
+++ b/soc/ti/simplelink/cc23x0/ccfg.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+
+#include <inc/hw_ccfg.h>
+
+#define CC23_CCFG_FLASH            DT_INST(0, ti_cc23x0_ccfg_flash)
+#define CC23_CCFG_FLASH_PROP(prop) DT_PROP(CC23_CCFG_FLASH, prop)
+
+#define CC23_TO_PERM_VAL(en) ((en) ? CCFG_PERMISSION_ALLOW : CCFG_PERMISSION_FORBID)
+
+#if CONFIG_CC23X0_BLDR_VTOR_TYPE_UNDEF
+#define CC23X0_BLDR_VTOR 0xffffffff
+#elif CONFIG_CC23X0_BLDR_VTOR_TYPE_FORBID
+#define CC23X0_BLDR_VTOR 0xfffffffc
+#elif CONFIG_CC23X0_BLDR_VTOR_TYPE_USE_FCFG
+#define CC23X0_BLDR_VTOR 0xfffffff0
+#else
+#define CC23X0_BLDR_VTOR CC23_CCFG_FLASH_PROP(ti_bldr_vtor_flash)
+#endif
+
+#define CC23X0_P_APP_VTOR DT_REG_ADDR(DT_CHOSEN(zephyr_code_partition))
+
+#if CC23_CCFG_FLASH_PROP(ti_chip_erase) == 0
+#warning ti,chip-erase property is NOT PRESENT in your device tree, \
+	 flashing this firmware will LOCK YOUR DEVICE.
+#endif
+
+/* Default CCFG */
+const ccfg_t ccfg __attribute__((section(".ti_ccfg"))) __attribute__((used)) = {
+	.bootCfg.pBldrVtor = (void *)CC23X0_BLDR_VTOR,
+	.bootCfg.bldrParam.serialRomBldrParamStruct.bldrEnabled =
+		IS_ENABLED(CONFIG_CC23X0_BLDR_ENABLED),
+	.bootCfg.bldrParam.serialRomBldrParamStruct.serialIoCfgIndex =
+		CC23_CCFG_FLASH_PROP(ti_serial_io_cfg_index),
+	.bootCfg.bldrParam.serialRomBldrParamStruct.pinTriggerEnabled =
+		CC23_CCFG_FLASH_PROP(ti_pin_trigger),
+	.bootCfg.bldrParam.serialRomBldrParamStruct.pinTriggerDio =
+		CC23_CCFG_FLASH_PROP(ti_pin_trigger_dio),
+	.bootCfg.bldrParam.serialRomBldrParamStruct.pinTriggerLevel =
+		CC23_CCFG_FLASH_PROP(ti_pin_trigger_level_hi),
+	.bootCfg.pAppVtor = (void *)CC23X0_P_APP_VTOR,
+
+	.hwOpts = {0xffffffff, 0xffffffff},
+
+	.permissions.allowDebugPort = CC23_TO_PERM_VAL(CC23_CCFG_FLASH_PROP(ti_debug_port)),
+	.permissions.allowEnergyTrace = CC23_TO_PERM_VAL(CC23_CCFG_FLASH_PROP(ti_energy_trace)),
+	.permissions.allowFlashVerify = CC23_TO_PERM_VAL(CC23_CCFG_FLASH_PROP(ti_flash_verify)),
+	.permissions.allowFlashProgram = CC23_TO_PERM_VAL(CC23_CCFG_FLASH_PROP(ti_flash_program)),
+	.permissions.allowChipErase = CC23_TO_PERM_VAL(CC23_CCFG_FLASH_PROP(ti_chip_erase)),
+	.permissions.allowToolsClientMode = CCFG_PERMISSION_ALLOW,
+	.permissions.allowReturnToFactory =
+		CC23_TO_PERM_VAL(CC23_CCFG_FLASH_PROP(ti_ret_to_factory)),
+	.permissions.allowFakeStby = CCFG_PERMISSION_ALLOW,
+
+	.misc.saciTimeoutOverride = 0,
+	.misc.saciTimeoutExp = XCFG_MISC_SACITOEXP_8SEC,
+
+	.flashProt.writeEraseProt.mainSectors0_31 = CC23_CCFG_FLASH_PROP(ti_wr_er_prot_sect0_31),
+	.flashProt.writeEraseProt.mainSectors32_255 =
+		CC23_CCFG_FLASH_PROP(ti_wr_er_prot_sect32_255),
+	.flashProt.writeEraseProt.ccfgSector = CC23_CCFG_FLASH_PROP(ti_wr_er_prot_ccfg_sect),
+	.flashProt.writeEraseProt.fcfgSector = CC23_CCFG_FLASH_PROP(ti_wr_er_prot_fcfg_sect),
+	.flashProt.writeEraseProt.engrSector = CC23_CCFG_FLASH_PROP(ti_wr_er_prot_engr_sect),
+
+	.flashProt.res = 0xffffffff,
+
+	.flashProt.chipEraseRetain.mainSectors0_31 =
+		CC23_CCFG_FLASH_PROP(ti_chip_er_retain_sect0_31),
+	.flashProt.chipEraseRetain.mainSectors32_255 =
+		CC23_CCFG_FLASH_PROP(ti_chip_er_retain_sect32_255),
+
+	.debugCfg.authorization = CCFG_DBGAUTH_DBGOPEN,
+	.debugCfg.allowBldr = CCFG_DBGBLDR_ALLOW,
+};
diff --git a/soc/ti/simplelink/cc23x0/ccfg.ld b/soc/ti/simplelink/cc23x0/ccfg.ld
new file mode 100644
index 00000000000..a9baf05dcf4
--- /dev/null
+++ b/soc/ti/simplelink/cc23x0/ccfg.ld
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+GROUP_START(FLASH_CCFG)
+
+CRC_CCFG_BOOT_CFG_begin = 0x4e020000;
+CRC_CCFG_BOOT_CFG_end = 0x4e02000B;
+CRC_CCFG_begin = 0x4E020010;
+CRC_CCFG_end = 0x4E02074B;
+CRC_CCFG_DEBUG_begin = 0x4E0207D0;
+CRC_CCFG_DEBUG_end = 0x4E0207FB;
+CRC_CCFG_USER_RECORD_begin = 0x4E020750;
+CRC_CCFG_USER_RECORD_end = 0x4E0207CB;
+SECTION_PROLOGUE(.ti_ccfg,,)
+{
+    KEEP(*(_TI_CCFG_SECTION_NAME))
+} GROUP_LINK_IN(LINKER_DT_NODE_REGION_NAME(DT_NODELABEL(ti_ccfg_partition)))
+
+GROUP_END(FLASH_CCFG)
diff --git a/soc/ti/simplelink/cc23x0/linker.ld b/soc/ti/simplelink/cc23x0/linker.ld
new file mode 100644
index 00000000000..448cc70c043
--- /dev/null
+++ b/soc/ti/simplelink/cc23x0/linker.ld
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/arch/arm/cortex_m/scripts/linker.ld>
diff --git a/soc/ti/simplelink/cc23x0/pinctrl_soc.h b/soc/ti/simplelink/cc23x0/pinctrl_soc.h
new file mode 100644
index 00000000000..4c2c6fefd16
--- /dev/null
+++ b/soc/ti/simplelink/cc23x0/pinctrl_soc.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef TI_SIMPLELINK_CC23X0_SOC_PINCTRL_H_
+#define TI_SIMPLELINK_CC23X0_SOC_PINCTRL_H_
+
+#include <zephyr/types.h>
+
+/* IO enabling/disabling */
+#define IOC_INPUT_ENABLE  BIT(29)
+#define IOC_INPUT_DISABLE 0U
+#define IOC_HYST_ENABLE   BIT(30)
+#define IOC_HYST_DISABLE  0U
+
+/* IO modes */
+#define IOC_IOMODE_NORMAL            0U
+#define IOC_IOMODE_INV               BIT(24)
+#define IOC_IOMODE_OPEN_DRAIN_NORMAL BIT(25)
+#define IOC_IOMODE_OPEN_DRAIN_INV    GENMASK(25, 24)
+#define IOC_IOMODE_OPEN_SRC_NORMAL   BIT(26)
+#define IOC_IOMODE_OPEN_SRC_INV      (BIT(26) | BIT(24))
+
+/* IO pull */
+#define IOC_NO_IOPULL   0U
+#define IOC_IOPULL_UP   BIT(14)
+#define IOC_IOPULL_DOWN BIT(13)
+
+typedef struct pinctrl_soc_pin {
+	uint32_t pin;
+	uint32_t iofunc;
+	uint32_t iomode;
+} pinctrl_soc_pin_t;
+
+/* Convert DT flags to SoC flags */
+#define CC23X0_PIN_FLAGS(node_id)                                                                  \
+	(DT_PROP(node_id, bias_pull_up) * IOC_IOPULL_UP |                                          \
+	 DT_PROP(node_id, bias_pull_down) * IOC_IOPULL_DOWN |                                      \
+	 DT_PROP(node_id, bias_disable) * IOC_NO_IOPULL |                                          \
+	 DT_PROP(node_id, drive_open_drain) * IOC_IOMODE_OPEN_DRAIN_NORMAL |                       \
+	 DT_PROP(node_id, drive_open_source) * IOC_IOMODE_OPEN_SRC_NORMAL |                        \
+	 DT_PROP(node_id, input_enable) * IOC_INPUT_ENABLE |                                       \
+	 DT_PROP(node_id, input_schmitt_enable) * IOC_HYST_ENABLE)
+
+#define CC23X0_DT_PIN(node_id)                                                                     \
+	{.pin = DT_PROP_BY_IDX(node_id, pinmux, 0),                                                \
+	 .iofunc = DT_PROP_BY_IDX(node_id, pinmux, 1),                                             \
+	 .iomode = CC23X0_PIN_FLAGS(node_id)},
+
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx)                                               \
+	CC23X0_DT_PIN(DT_PROP_BY_IDX(node_id, prop, idx))
+
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)                                                   \
+	{DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT)}
+
+#endif /* TI_SIMPLELINK_CC23X0_SOC_PINCTRL_H_ */
diff --git a/soc/ti/simplelink/cc23x0/soc.c b/soc/ti/simplelink/cc23x0/soc.c
new file mode 100644
index 00000000000..cddae58b4e0
--- /dev/null
+++ b/soc/ti/simplelink/cc23x0/soc.c
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <driverlib/setup.h>
+
+void soc_reset_hook(void)
+{
+	/* Perform necessary trim of the device. */
+	SetupTrimDevice();
+}
diff --git a/soc/ti/simplelink/cc23x0/soc.h b/soc/ti/simplelink/cc23x0/soc.h
new file mode 100644
index 00000000000..353b64b6a11
--- /dev/null
+++ b/soc/ti/simplelink/cc23x0/soc.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 Texas Instruments Incorporated
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef TI_SIMPLELINK_CC23X0_SOC_H_
+#define TI_SIMPLELINK_CC23X0_SOC_H_
+
+#include "cmsis/cc23x0r5.h"
+#include "ti_cc23x0_dt.h"
+
+#endif /* TI_SIMPLELINK_CC23X0_SOC_H_ */
diff --git a/soc/ti/simplelink/cc23x0/ti_cc23x0_dt.h b/soc/ti/simplelink/cc23x0/ti_cc23x0_dt.h
new file mode 100644
index 00000000000..d5af5a3947e
--- /dev/null
+++ b/soc/ti/simplelink/cc23x0/ti_cc23x0_dt.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2024 BayLibre, SAS
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief TI CC23X0 MCU family devicetree helper macros
+ */
+
+#ifndef _TI_CC23X0_DT_H_
+#define _TI_CC23X0_DT_H_
+
+/* Common macro to get CPU clock frequency */
+#define TI_CC23X0_DT_CPU_CLK_FREQ_HZ \
+	DT_PROP(DT_PATH(cpus, cpu_0), clock_frequency)
+
+/*
+ * Helper macros for use with TI CC23X0 DMA controller
+ * return 0xff as default value if there is no 'dmas' property
+ */
+#define TI_CC23X0_DT_INST_DMA_CELL(n, name, cell)		\
+	COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas),		\
+		    (DT_INST_DMAS_CELL_BY_NAME(n, name, cell)),	\
+		    (0xff))
+
+#define TI_CC23X0_DT_INST_DMA_TRIGSRC(n, name) \
+	TI_CC23X0_DT_INST_DMA_CELL(n, name, trigsrc)
+
+#define TI_CC23X0_DT_INST_DMA_CHANNEL(n, name) \
+	TI_CC23X0_DT_INST_DMA_CELL(n, name, channel)
+
+#define TI_CC23X0_DT_INST_DMA_CTLR(n, name)			\
+	COND_CODE_1(DT_INST_NODE_HAS_PROP(n, dmas),		\
+		    (DT_INST_DMAS_CTLR_BY_NAME(n, name)),	\
+		    (DT_INVALID_NODE))
+
+#endif /* _TI_CC23X0_DT_H_ */
diff --git a/soc/ti/simplelink/soc.yml b/soc/ti/simplelink/soc.yml
index 2dbf91f315e..bbf1ef19de4 100644
--- a/soc/ti/simplelink/soc.yml
+++ b/soc/ti/simplelink/soc.yml
@@ -13,6 +13,9 @@ family:
     - name: cc1352r7
     - name: cc2652p7
     - name: cc2652r7
+  - name: cc23x0
+    socs:
+    - name: cc2340r5
   - name: cc32xx
     socs:
     - name: cc3220sf
diff --git a/soc/wch/ch32v/CMakeLists.txt b/soc/wch/ch32v/CMakeLists.txt
new file mode 100644
index 00000000000..0f127dd9c75
--- /dev/null
+++ b/soc/wch/ch32v/CMakeLists.txt
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory(${SOC_SERIES})
+
+set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
diff --git a/soc/wch/ch32v/Kconfig b/soc/wch/ch32v/Kconfig
new file mode 100644
index 00000000000..86da17a0321
--- /dev/null
+++ b/soc/wch/ch32v/Kconfig
@@ -0,0 +1,23 @@
+# Copyright (c) 2024 Michael Hope
+# Copyright (c) 2024 Jianxiong Gu
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_CH32V
+	select RISCV
+	select BUILD_OUTPUT_HEX
+	select CH32V00X_SYSTICK
+	select ATOMIC_OPERATIONS_C
+	imply XIP
+
+if SOC_FAMILY_CH32V
+
+config VECTOR_TABLE_SIZE
+	int "Number of Interrupt and Exception Vectors"
+	range 20 256
+	help
+	  This option defines the total number of interrupt and exception
+	  vectors in the vector table.
+
+rsource "*/Kconfig"
+
+endif # SOC_FAMILY_CH32V
diff --git a/soc/wch/ch32v/Kconfig.defconfig b/soc/wch/ch32v/Kconfig.defconfig
new file mode 100644
index 00000000000..7d710b5b910
--- /dev/null
+++ b/soc/wch/ch32v/Kconfig.defconfig
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Michael Hope
+# Copyright (c) 2024 Jianxiong Gu
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_FAMILY_CH32V
+
+rsource "*/Kconfig.defconfig"
+
+endif # SOC_FAMILY_CH32V
diff --git a/soc/wch/ch32v/Kconfig.soc b/soc/wch/ch32v/Kconfig.soc
new file mode 100644
index 00000000000..39cb7270b1c
--- /dev/null
+++ b/soc/wch/ch32v/Kconfig.soc
@@ -0,0 +1,11 @@
+# Copyright (c) 2024 Michael Hope
+# Copyright (c) 2024 Jianxiong Gu
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_FAMILY_CH32V
+	bool
+
+config SOC_FAMILY
+	default "ch32v" if SOC_FAMILY_CH32V
+
+rsource "*/Kconfig.soc"
diff --git a/soc/wch/ch32v/qingke_v2a/CMakeLists.txt b/soc/wch/ch32v/qingke_v2a/CMakeLists.txt
new file mode 100644
index 00000000000..a7e9de643d6
--- /dev/null
+++ b/soc/wch/ch32v/qingke_v2a/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Michael Hope
+# Copyright (c) 2024 Jianxiong Gu
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+  soc_irq.S
+  vector.S
+)
+
+zephyr_include_directories(.)
diff --git a/soc/wch/ch32v/qingke_v2a/Kconfig b/soc/wch/ch32v/qingke_v2a/Kconfig
new file mode 100644
index 00000000000..de004227a47
--- /dev/null
+++ b/soc/wch/ch32v/qingke_v2a/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_QINGKE_V2A
+	select RISCV_ISA_RV32E
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
+	select RISCV_ISA_EXT_C
diff --git a/soc/wch/ch32v/qingke_v2a/Kconfig.defconfig b/soc/wch/ch32v/qingke_v2a/Kconfig.defconfig
new file mode 100644
index 00000000000..02aa7004c3c
--- /dev/null
+++ b/soc/wch/ch32v/qingke_v2a/Kconfig.defconfig
@@ -0,0 +1,23 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_QINGKE_V2A
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config MAIN_STACK_SIZE
+	default 512
+
+config IDLE_STACK_SIZE
+	default 256
+
+config ISR_STACK_SIZE
+	default 256
+
+config CLOCK_CONTROL
+	default y
+
+rsource "Kconfig.defconfig.*"
+
+endif # SOC_SERIES_QINGKE_V2A
diff --git a/soc/wch/ch32v/qingke_v2a/Kconfig.defconfig.ch32v003 b/soc/wch/ch32v/qingke_v2a/Kconfig.defconfig.ch32v003
new file mode 100644
index 00000000000..44d27fd3865
--- /dev/null
+++ b/soc/wch/ch32v/qingke_v2a/Kconfig.defconfig.ch32v003
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_CH32V003
+
+config VECTOR_TABLE_SIZE
+	default 38
+
+config NUM_IRQS
+	default 48
+
+endif # SOC_CH32V003
diff --git a/soc/wch/ch32v/qingke_v2a/Kconfig.soc b/soc/wch/ch32v/qingke_v2a/Kconfig.soc
new file mode 100644
index 00000000000..ccf0d2fdf37
--- /dev/null
+++ b/soc/wch/ch32v/qingke_v2a/Kconfig.soc
@@ -0,0 +1,11 @@
+# Copyright (c) 2024 Jianxiong Gu
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_QINGKE_V2A
+	bool
+	select SOC_FAMILY_CH32V
+
+config SOC_SERIES
+	default "qingke_v2a" if SOC_SERIES_QINGKE_V2A
+
+rsource "Kconfig.soc.*"
diff --git a/soc/wch/ch32v/qingke_v2a/Kconfig.soc.ch32v003 b/soc/wch/ch32v/qingke_v2a/Kconfig.soc.ch32v003
new file mode 100644
index 00000000000..b8ffe5e596b
--- /dev/null
+++ b/soc/wch/ch32v/qingke_v2a/Kconfig.soc.ch32v003
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_CH32V003
+	bool
+	select SOC_SERIES_QINGKE_V2A
+
+config SOC
+	default "ch32v003" if SOC_CH32V003
diff --git a/soc/wch/ch32v00x/pinctrl_soc.h b/soc/wch/ch32v/qingke_v2a/pinctrl_soc.h
similarity index 100%
rename from soc/wch/ch32v00x/pinctrl_soc.h
rename to soc/wch/ch32v/qingke_v2a/pinctrl_soc.h
diff --git a/soc/wch/ch32v00x/soc_irq.S b/soc/wch/ch32v/qingke_v2a/soc_irq.S
similarity index 100%
rename from soc/wch/ch32v00x/soc_irq.S
rename to soc/wch/ch32v/qingke_v2a/soc_irq.S
diff --git a/soc/wch/ch32v/qingke_v2a/vector.S b/soc/wch/ch32v/qingke_v2a/vector.S
new file mode 100644
index 00000000000..d078444d85e
--- /dev/null
+++ b/soc/wch/ch32v/qingke_v2a/vector.S
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2024 Michael Hope
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/toolchain.h>
+
+#ifndef CONFIG_VECTOR_TABLE_SIZE
+#error "VECTOR_TABLE_SIZE must be defined"
+#endif
+
+/* Exports */
+GTEXT(__start)
+
+/* Imports */
+GTEXT(__initialize)
+
+SECTION_FUNC(vectors, ivt)
+	.option norvc
+	j       __start
+	.rept   CONFIG_VECTOR_TABLE_SIZE
+	.word	_isr_wrapper
+	.endr
+
+SECTION_FUNC(vectors, __start)
+	li 	a0, 3
+	csrw	mtvec, a0
+	j	__initialize
diff --git a/soc/wch/ch32v/qingke_v4c/CMakeLists.txt b/soc/wch/ch32v/qingke_v4c/CMakeLists.txt
new file mode 100644
index 00000000000..a7e9de643d6
--- /dev/null
+++ b/soc/wch/ch32v/qingke_v4c/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Michael Hope
+# Copyright (c) 2024 Jianxiong Gu
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+  soc_irq.S
+  vector.S
+)
+
+zephyr_include_directories(.)
diff --git a/soc/wch/ch32v/qingke_v4c/Kconfig b/soc/wch/ch32v/qingke_v4c/Kconfig
new file mode 100644
index 00000000000..732a7d8a9ec
--- /dev/null
+++ b/soc/wch/ch32v/qingke_v4c/Kconfig
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_QINGKE_V4C
+	select RISCV_ISA_RV32I
+	select RISCV_ISA_EXT_M
+	select RISCV_ISA_EXT_A
+	select RISCV_ISA_EXT_C
+	select RISCV_ISA_EXT_ZICSR
+	select RISCV_ISA_EXT_ZIFENCEI
diff --git a/soc/wch/ch32v/qingke_v4c/Kconfig.defconfig b/soc/wch/ch32v/qingke_v4c/Kconfig.defconfig
new file mode 100644
index 00000000000..a782adfdfd2
--- /dev/null
+++ b/soc/wch/ch32v/qingke_v4c/Kconfig.defconfig
@@ -0,0 +1,23 @@
+# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_QINGKE_V4C
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+config MAIN_STACK_SIZE
+	default 512
+
+config IDLE_STACK_SIZE
+	default 256
+
+config ISR_STACK_SIZE
+	default 256
+
+config CLOCK_CONTROL
+	default y
+
+rsource "Kconfig.defconfig.*"
+
+endif # SOC_SERIES_QINGKE_V4C
diff --git a/soc/wch/ch32v/qingke_v4c/Kconfig.defconfig.ch32v208 b/soc/wch/ch32v/qingke_v4c/Kconfig.defconfig.ch32v208
new file mode 100644
index 00000000000..f7b4b3fe1ec
--- /dev/null
+++ b/soc/wch/ch32v/qingke_v4c/Kconfig.defconfig.ch32v208
@@ -0,0 +1,12 @@
+# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_CH32V208
+
+config VECTOR_TABLE_SIZE
+	default 103
+
+config NUM_IRQS
+	default 128
+
+endif # SOC_CH32V208
diff --git a/soc/wch/ch32v/qingke_v4c/Kconfig.soc b/soc/wch/ch32v/qingke_v4c/Kconfig.soc
new file mode 100644
index 00000000000..33ffd7e3f21
--- /dev/null
+++ b/soc/wch/ch32v/qingke_v4c/Kconfig.soc
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_SERIES_QINGKE_V4C
+	bool
+	select SOC_FAMILY_CH32V
+
+config SOC_SERIES
+	default "qingke_v4c" if SOC_SERIES_QINGKE_V4C
+
+rsource "Kconfig.soc.*"
diff --git a/soc/wch/ch32v/qingke_v4c/Kconfig.soc.ch32v208 b/soc/wch/ch32v/qingke_v4c/Kconfig.soc.ch32v208
new file mode 100644
index 00000000000..8baa7d35833
--- /dev/null
+++ b/soc/wch/ch32v/qingke_v4c/Kconfig.soc.ch32v208
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_CH32V208
+	bool
+	select SOC_SERIES_QINGKE_V4C
+
+config SOC
+	default "ch32v208" if SOC_CH32V208
diff --git a/soc/wch/ch32v/qingke_v4c/pinctrl_soc.h b/soc/wch/ch32v/qingke_v4c/pinctrl_soc.h
new file mode 100644
index 00000000000..a448d447b3a
--- /dev/null
+++ b/soc/wch/ch32v/qingke_v4c/pinctrl_soc.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2024 Michael Hope
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __PINCTRL_SOC_H__
+#define __PINCTRL_SOC_H__
+
+/**
+ * @brief Type to hold a pin's pinctrl configuration.
+ */
+struct ch32v208_pinctrl_soc_pin {
+	uint32_t config: 22;
+	bool bias_pull_up: 1;
+	bool bias_pull_down: 1;
+	bool drive_open_drain: 1;
+	bool drive_push_pull: 1;
+	bool output_high: 1;
+	bool output_low: 1;
+	uint8_t slew_rate: 2;
+};
+
+typedef struct ch32v208_pinctrl_soc_pin pinctrl_soc_pin_t;
+
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx)                                               \
+	{                                                                                          \
+		.config = DT_PROP_BY_IDX(node_id, prop, idx),                                      \
+		.bias_pull_up = DT_PROP(node_id, bias_pull_up),                                    \
+		.bias_pull_down = DT_PROP(node_id, bias_pull_down),                                \
+		.drive_open_drain = DT_PROP(node_id, drive_open_drain),                            \
+		.drive_push_pull = DT_PROP(node_id, drive_push_pull),                              \
+		.output_high = DT_PROP(node_id, output_high),                                      \
+		.output_low = DT_PROP(node_id, output_low),                                        \
+		.slew_rate = DT_ENUM_IDX(node_id, slew_rate),                                      \
+	},
+
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop)                                                   \
+	{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux,           \
+				Z_PINCTRL_STATE_PIN_INIT)}
+
+#endif
diff --git a/soc/wch/ch32v/qingke_v4c/soc_irq.S b/soc/wch/ch32v/qingke_v4c/soc_irq.S
new file mode 100644
index 00000000000..fcb0daea51d
--- /dev/null
+++ b/soc/wch/ch32v/qingke_v4c/soc_irq.S
@@ -0,0 +1,19 @@
+/* Copyright (c) 2024 Michael Hope
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <offsets.h>
+#include <zephyr/toolchain.h>
+
+/* Exports */
+GTEXT(__soc_is_irq)
+GTEXT(__soc_handle_irq)
+
+SECTION_FUNC(exception.other, __soc_is_irq)
+	csrr a0, mcause
+	srli a0, a0, 31
+	ret
+
+SECTION_FUNC(exception.other, __soc_handle_irq)
+	ret
diff --git a/soc/wch/ch32v/qingke_v4c/vector.S b/soc/wch/ch32v/qingke_v4c/vector.S
new file mode 100644
index 00000000000..d078444d85e
--- /dev/null
+++ b/soc/wch/ch32v/qingke_v4c/vector.S
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2024 Michael Hope
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/toolchain.h>
+
+#ifndef CONFIG_VECTOR_TABLE_SIZE
+#error "VECTOR_TABLE_SIZE must be defined"
+#endif
+
+/* Exports */
+GTEXT(__start)
+
+/* Imports */
+GTEXT(__initialize)
+
+SECTION_FUNC(vectors, ivt)
+	.option norvc
+	j       __start
+	.rept   CONFIG_VECTOR_TABLE_SIZE
+	.word	_isr_wrapper
+	.endr
+
+SECTION_FUNC(vectors, __start)
+	li 	a0, 3
+	csrw	mtvec, a0
+	j	__initialize
diff --git a/soc/wch/ch32v/soc.yml b/soc/wch/ch32v/soc.yml
new file mode 100644
index 00000000000..a019651b5dc
--- /dev/null
+++ b/soc/wch/ch32v/soc.yml
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Michael Hope
+# SPDX-License-Identifier: Apache-2.0
+
+family:
+- name: ch32v
+  series:
+  - name: qingke-v2
+    socs:
+    - name: ch32v003
+  - name: qingke-v4c
+    socs:
+    - name: ch32v208
diff --git a/soc/wch/ch32v00x/CMakeLists.txt b/soc/wch/ch32v00x/CMakeLists.txt
deleted file mode 100644
index e1688933580..00000000000
--- a/soc/wch/ch32v00x/CMakeLists.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-# Copyright (c) 2024 Michael Hope
-# SPDX-License-Identifier: Apache-2.0
-
-zephyr_sources(
-  soc_irq.S
-  vector.S
-)
-
-set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")
diff --git a/soc/wch/ch32v00x/Kconfig b/soc/wch/ch32v00x/Kconfig
deleted file mode 100644
index c5de3547451..00000000000
--- a/soc/wch/ch32v00x/Kconfig
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (c) 2024 Michael Hope
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_CH32V003
-	select RISCV
-	select BUILD_OUTPUT_HEX
-	select RISCV_ISA_RV32E
-	select RISCV_ISA_EXT_ZICSR
-	select RISCV_ISA_EXT_ZIFENCEI
-	select RISCV_ISA_EXT_C
-	select CH32V00X_SYSTICK
-	select ATOMIC_OPERATIONS_C
-	imply XIP
diff --git a/soc/wch/ch32v00x/Kconfig.defconfig b/soc/wch/ch32v00x/Kconfig.defconfig
deleted file mode 100644
index ecdd57f74f7..00000000000
--- a/soc/wch/ch32v00x/Kconfig.defconfig
+++ /dev/null
@@ -1,24 +0,0 @@
-# Copyright (c) 2024 Michael Hope
-# SPDX-License-Identifier: Apache-2.0
-
-if SOC_CH32V003
-
-config NUM_IRQS
-	default 48
-
-config SYS_CLOCK_HW_CYCLES_PER_SEC
-	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
-
-config MAIN_STACK_SIZE
-	default 512
-
-config IDLE_STACK_SIZE
-	default 256
-
-config ISR_STACK_SIZE
-	default 256
-
-config CLOCK_CONTROL
-	default y
-
-endif # SOC_CH32V003
diff --git a/soc/wch/ch32v00x/Kconfig.soc b/soc/wch/ch32v00x/Kconfig.soc
deleted file mode 100644
index c717a405603..00000000000
--- a/soc/wch/ch32v00x/Kconfig.soc
+++ /dev/null
@@ -1,15 +0,0 @@
-# Copyright (c) 2024 Michael Hope
-# SPDX-License-Identifier: Apache-2.0
-
-config SOC_SERIES_CH32V00X
-	bool
-
-config SOC_CH32V003
-	bool
-	select SOC_SERIES_CH32V00X
-
-config SOC_SERIES
-	default "ch32v00x" if SOC_SERIES_CH32V00X
-
-config SOC
-	default "ch32v003" if SOC_CH32V003
diff --git a/soc/wch/ch32v00x/soc.yml b/soc/wch/ch32v00x/soc.yml
deleted file mode 100644
index 5c39c57a7c7..00000000000
--- a/soc/wch/ch32v00x/soc.yml
+++ /dev/null
@@ -1,7 +0,0 @@
-# Copyright (c) 2024 Michael Hope
-# SPDX-License-Identifier: Apache-2.0
-
-series:
-  - name: ch32v00x
-    socs:
-      - name: ch32v003
diff --git a/soc/wch/ch32v00x/vector.S b/soc/wch/ch32v00x/vector.S
deleted file mode 100644
index 7abbc167c9c..00000000000
--- a/soc/wch/ch32v00x/vector.S
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2024 Michael Hope
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/toolchain.h>
-
-/* Exports */
-GTEXT(__start)
-
-/* Imports */
-GTEXT(__initialize)
-
-SECTION_FUNC(vectors, ivt)
-	.option norvc
-	j       __start
-	.rept 38
-	.word	_isr_wrapper
-	.endr
-
-SECTION_FUNC(vectors, __start)
-	li 	a0, 3
-	csrw	mtvec, a0
-	j	__initialize
diff --git a/soc/xlnx/versalnet/CMakeLists.txt b/soc/xlnx/versalnet/CMakeLists.txt
new file mode 100644
index 00000000000..a6ccdf4f203
--- /dev/null
+++ b/soc/xlnx/versalnet/CMakeLists.txt
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_sources(
+  soc.c
+)
+zephyr_sources_ifdef(
+  CONFIG_ARM_MPU
+  arm_mpu_regions.c
+)
+
+zephyr_include_directories(.)
+
+if(CONFIG_SOC_AMD_VERSALNET_RPU)
+  set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")
+endif()
diff --git a/soc/xlnx/versalnet/Kconfig b/soc/xlnx/versalnet/Kconfig
new file mode 100644
index 00000000000..89e185d6266
--- /dev/null
+++ b/soc/xlnx/versalnet/Kconfig
@@ -0,0 +1,15 @@
+#
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_AMD_VERSALNET_RPU
+	select ARM
+	select ARM_ARCH_TIMER
+	select CPU_CORTEX_R52
+	select SOC_EARLY_INIT_HOOK
+	select CPU_HAS_DCLS
+	select GIC_SINGLE_SECURITY_STATE
+	select CPU_HAS_ARM_MPU
+	select ARM_MPU
diff --git a/soc/xlnx/versalnet/Kconfig.defconfig b/soc/xlnx/versalnet/Kconfig.defconfig
new file mode 100644
index 00000000000..7997b8feb69
--- /dev/null
+++ b/soc/xlnx/versalnet/Kconfig.defconfig
@@ -0,0 +1,25 @@
+#
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_AMD_VERSALNET
+
+if SOC_AMD_VERSALNET_RPU
+
+CONFIG_CACHE_MANAGEMENT=y
+CONFIG_ARM_ARCH_TIMER=y
+CONFIG_CACHE_MANAGEMENT=y
+
+config NUM_IRQS
+	# must be >= the highest interrupt number used
+	# - include the UART interrupts
+	default 256
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
+
+endif # SOC_AMD_VERSALNET_RPU
+
+endif # SOC_AMD_VERSALNET
diff --git a/soc/xlnx/versalnet/Kconfig.soc b/soc/xlnx/versalnet/Kconfig.soc
new file mode 100644
index 00000000000..181a2100d9b
--- /dev/null
+++ b/soc/xlnx/versalnet/Kconfig.soc
@@ -0,0 +1,20 @@
+#
+# Copyright (c) 2025 Advanced Micro Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config SOC_AMD_VERSALNET
+	bool
+
+config SOC_AMD_VERSALNET_RPU
+	bool
+	select SOC_AMD_VERSALNET
+	help
+	  AMD Versal NET SoC
+
+config SOC_FAMILY
+	default "amd_versalnet" if SOC_AMD_VERSALNET
+
+config SOC
+	default "amd_versalnet_rpu" if SOC_AMD_VERSALNET_RPU
diff --git a/soc/xlnx/versalnet/arm_mpu_regions.c b/soc/xlnx/versalnet/arm_mpu_regions.c
new file mode 100644
index 00000000000..865452c6e38
--- /dev/null
+++ b/soc/xlnx/versalnet/arm_mpu_regions.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2025 Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/linker/linker-defs.h>
+#include <zephyr/arch/arm/mpu/arm_mpu.h>
+
+#define DEVICE_REGION_START	0xE2000000U
+#define DEVICE_REGION_END	0xF8000000U
+
+static const struct arm_mpu_region mpu_regions[] = {
+	MPU_REGION_ENTRY("vector",
+			 (uintptr_t)_vector_start,
+			 REGION_RAM_TEXT_ATTR((uintptr_t)_vector_end)),
+
+	MPU_REGION_ENTRY("SRAM_TEXT",
+			 (uintptr_t)__text_region_start,
+			 REGION_RAM_TEXT_ATTR((uintptr_t)__rodata_region_start)),
+
+	MPU_REGION_ENTRY("SRAM_RODATA",
+			 (uintptr_t)__rodata_region_start,
+			 REGION_RAM_RO_ATTR((uintptr_t)__rodata_region_end)),
+
+	MPU_REGION_ENTRY("SRAM_DATA",
+			 (uintptr_t)__rom_region_end,
+			 REGION_RAM_ATTR((uintptr_t)__kernel_ram_end)),
+
+	MPU_REGION_ENTRY("DEVICE",
+			 DEVICE_REGION_START,
+			 REGION_DEVICE_ATTR(DEVICE_REGION_END)),
+};
+
+const struct arm_mpu_config mpu_config = {
+	.num_regions = ARRAY_SIZE(mpu_regions),
+	.mpu_regions = mpu_regions,
+};
diff --git a/soc/xlnx/versalnet/soc.c b/soc/xlnx/versalnet/soc.c
new file mode 100644
index 00000000000..3b269b4eefc
--- /dev/null
+++ b/soc/xlnx/versalnet/soc.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2025 Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/cache.h>
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+
+void soc_early_init_hook(void)
+{
+	if (IS_ENABLED(CONFIG_ICACHE)) {
+		if (!(__get_SCTLR() & SCTLR_I_Msk)) {
+			L1C_InvalidateICacheAll();
+			__set_SCTLR(__get_SCTLR() | SCTLR_I_Msk);
+			barrier_isync_fence_full();
+		}
+	}
+
+	if (IS_ENABLED(CONFIG_DCACHE)) {
+		if (!(__get_SCTLR() & SCTLR_C_Msk)) {
+			L1C_InvalidateDCacheAll();
+			__set_SCTLR(__get_SCTLR() | SCTLR_C_Msk);
+			barrier_dsync_fence_full();
+		}
+	}
+}
diff --git a/soc/xlnx/versalnet/soc.h b/soc/xlnx/versalnet/soc.h
new file mode 100644
index 00000000000..78bafbaaa5f
--- /dev/null
+++ b/soc/xlnx/versalnet/soc.h
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025 Advanced Micro Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef _SOC_XLNX_VERSALNET_SOC_H_
+#define _SOC_XLNX_VERSALNET_SOC_H_
+
+/* Define CMSIS configurations */
+#define __GIC_PRESENT 0
+#define __TIM_PRESENT 0
+
+#endif /* _SOC_XLNX_VERSALNET_SOC_H_ */
diff --git a/soc/xlnx/versalnet/soc.yml b/soc/xlnx/versalnet/soc.yml
new file mode 100644
index 00000000000..8de1e6c40f4
--- /dev/null
+++ b/soc/xlnx/versalnet/soc.yml
@@ -0,0 +1,4 @@
+family:
+- name: amd_versalnet
+  socs:
+  - name: amd_versalnet_rpu
diff --git a/soc/xlnx/zynqmp/Kconfig b/soc/xlnx/zynqmp/Kconfig
index 3c88e5aa90e..73f44865b38 100644
--- a/soc/xlnx/zynqmp/Kconfig
+++ b/soc/xlnx/zynqmp/Kconfig
@@ -6,5 +6,6 @@ config SOC_XILINX_ZYNQMP_RPU
 	select ARM
 	select CPU_CORTEX_R5
 	select SOC_RESET_HOOK
+	select SOC_EARLY_INIT_HOOK
 	select CPU_HAS_ARM_MPU
 	select VFP_DP_D16
diff --git a/soc/xlnx/zynqmp/soc.c b/soc/xlnx/zynqmp/soc.c
index db03b639912..fc8c8e46097 100644
--- a/soc/xlnx/zynqmp/soc.c
+++ b/soc/xlnx/zynqmp/soc.c
@@ -7,6 +7,7 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
+#include <zephyr/cache.h>
 
 #include <cmsis_core.h>
 
@@ -20,3 +21,10 @@ void soc_reset_hook(void)
 	sctlr &= ~SCTLR_V_Msk;
 	__set_SCTLR(sctlr);
 }
+
+void soc_early_init_hook(void)
+{
+	/* Enable caches */
+	sys_cache_instr_enable();
+	sys_cache_data_enable();
+}
diff --git a/submanifests/optional.yaml b/submanifests/optional.yaml
index 0480cce6321..82a9de6a12a 100644
--- a/submanifests/optional.yaml
+++ b/submanifests/optional.yaml
@@ -47,7 +47,7 @@ manifest:
       groups:
         - optional
     - name: tflite-micro
-      revision: 48613f7ba1ffbda46ad771a77a35408f48f922e9
+      revision: 8d404de73acf7687831e16d88e86e4f73cfddf8e
       path: optional/modules/lib/tflite-micro
       repo-path: tflite-micro
       remote: upstream
@@ -60,7 +60,7 @@ manifest:
       groups:
         - optional
     - name: zephyr-lang-rust
-      revision: 7af3db47bf7335ac6a6fe7480df6b41fb46dbe9d
+      revision: d4f9036a88e53080bf2b186afa5289f9c77a0f73
       path: modules/lang/rust
       remote: upstream
       groups:
diff --git a/subsys/CMakeLists.txt b/subsys/CMakeLists.txt
index b4ea9eb4762..a0a2bc828cf 100644
--- a/subsys/CMakeLists.txt
+++ b/subsys/CMakeLists.txt
@@ -22,6 +22,7 @@ add_subdirectory(mem_mgmt)
 add_subdirectory(mgmt)
 add_subdirectory(modbus)
 add_subdirectory(pm)
+add_subdirectory(pmci)
 add_subdirectory(portability)
 add_subdirectory(random)
 add_subdirectory(rtio)
diff --git a/subsys/Kconfig b/subsys/Kconfig
index 561d5263422..a85bda6ece4 100644
--- a/subsys/Kconfig
+++ b/subsys/Kconfig
@@ -32,6 +32,7 @@ source "subsys/modbus/Kconfig"
 source "subsys/modem/Kconfig"
 source "subsys/net/Kconfig"
 source "subsys/pm/Kconfig"
+source "subsys/pmci/Kconfig"
 source "subsys/portability/Kconfig"
 source "subsys/profiling/Kconfig"
 source "subsys/random/Kconfig"
diff --git a/subsys/bluetooth/Kconfig b/subsys/bluetooth/Kconfig
index f61598d4194..45e9bb446f8 100644
--- a/subsys/bluetooth/Kconfig
+++ b/subsys/bluetooth/Kconfig
@@ -224,7 +224,161 @@ config BT_CHANNEL_SOUNDING_REASSEMBLY_BUFFER_CNT
 
 endif # BT_CONN
 
-rsource "Kconfig.iso"
+config BT_ISO
+	bool
+
+config BT_ISO_TX
+	bool
+
+config BT_ISO_RX
+	bool
+
+#TODO : Split between client(central) and server(peripheral)
+config BT_ISO_UNICAST
+	bool
+	depends on BT_CONN
+	select BT_ISO
+	select BT_ISO_TX
+	select BT_ISO_RX
+	help
+	  This option enables support for Bluetooth Unicast
+	  Isochronous channels.
+
+config BT_ISO_PERIPHERAL
+	bool "Bluetooth Isochronous Channel Unicast Peripheral Support"
+	depends on !HAS_BT_CTLR || BT_CTLR_PERIPHERAL_ISO_SUPPORT
+	depends on BT_PERIPHERAL
+	select BT_ISO_UNICAST
+	help
+	  This option enables support for Bluetooth Unicast
+	  Isochronous channels for the peripheral role.
+
+config BT_ISO_CENTRAL
+	bool "Bluetooth Isochronous Channel Unicast Central Support"
+	depends on !HAS_BT_CTLR || BT_CTLR_CENTRAL_ISO_SUPPORT
+	depends on BT_CENTRAL
+	select BT_ISO_UNICAST
+	help
+	  This option enables support for Bluetooth Broadcast
+	  Isochronous channels for the central role.
+
+config BT_ISO_BROADCAST
+	bool
+	select BT_ISO
+	select BT_EXT_ADV
+
+config BT_ISO_BROADCASTER
+	bool "Bluetooth Isochronous Broadcaster Support"
+	depends on !HAS_BT_CTLR || BT_CTLR_ADV_ISO_SUPPORT
+	select BT_ISO_BROADCAST
+	select BT_ISO_TX
+	select BT_BROADCASTER
+	select BT_PER_ADV
+	help
+	  This option enables support for the Bluetooth Isochronous Broadcaster.
+
+config BT_ISO_SYNC_RECEIVER
+	bool "Bluetooth Isochronous Synchronized Receiver Support"
+	depends on !HAS_BT_CTLR || BT_CTLR_SYNC_ISO_SUPPORT
+	depends on BT_OBSERVER
+	select BT_ISO_BROADCAST
+	select BT_ISO_RX
+	select BT_PER_ADV_SYNC
+	help
+	  This option enables support for the Bluetooth Isochronous
+	  Synchronized Receiver.
+
+if BT_ISO
+
+config BT_ISO_MAX_CHAN
+	int "Maximum number of simultaneous ISO channels"
+	depends on BT_ISO
+	default BT_MAX_CONN if BT_CONN
+	default 1
+	range 1 64
+	help
+	  Maximum number of simultaneous Bluetooth isochronous channels
+	  supported.
+
+config BT_ISO_TX_BUF_COUNT
+	int "Number of Isochronous TX buffers"
+	default 1
+	range 1 $(UINT8_MAX)
+	help
+	  Number of buffers available for outgoing Isochronous channel SDUs.
+
+config BT_ISO_TX_FRAG_COUNT
+	int "Number of ISO TX fragment buffers"
+	default 2
+	range 0 $(UINT8_MAX)
+	help
+	  Number of buffers available for fragments of TX buffers. Warning:
+	  setting this to 0 means that the application must ensure that
+	  queued TX buffers never need to be fragmented, i.e. that the
+	  controller's buffer size is large enough. If this is not ensured,
+	  and there are no dedicated fragment buffers, a deadlock may occur.
+	  In most cases the default value of 2 is a safe bet.
+
+config BT_ISO_TX_MTU
+	int "Maximum supported MTU for Isochronous TX buffers"
+	range 1 4095
+	default 247
+	help
+	  Maximum MTU for Isochronous channels TX buffers.
+	  This is the actual data payload. It doesn't include the optional
+	  HCI ISO Data packet fields (e.g. `struct bt_hci_iso_sdu_ts_hdr`).
+	  Set this value to 247 to fit 247 bytes of data within a single
+	  HCI ISO Data packet with Data_Total_Length of 255, utilizing
+	  timestamps.
+
+config BT_ISO_RX_BUF_COUNT
+	int "Number of Isochronous RX buffers"
+	default 1
+	range 1 $(UINT8_MAX)
+	help
+	  Number of buffers available for incoming Isochronous channel SDUs.
+
+config BT_ISO_RX_MTU
+	int "Maximum supported MTU for Isochronous RX buffers"
+	default 251
+	range 23 4095
+	help
+	  Maximum MTU for Isochronous channels RX buffers.
+	  This is the actual data payload. It doesn't include the optional
+	  HCI ISO Data packet fields (e.g. `struct bt_hci_iso_sdu_ts_hdr`)
+
+config BT_ISO_TEST_PARAMS
+	bool "ISO test parameters support"
+	help
+	  Enabling advanced ISO parameters will allow the use of the ISO test
+	  parameters for creating a CIG or a BIG. These test parameters were
+	  intended for testing, but can be used to allow the host to set more
+	  settings that are otherwise usually controlled by the controller.
+
+if BT_ISO_UNICAST
+
+config BT_ISO_MAX_CIG
+	int "Maximum number of Connected Isochronous Groups (CIGs) to support"
+	default 1
+	help
+	  Maximum number of CIGs that are supported by the host. A CIG can be
+	  used for either transmitting or receiving.
+
+endif # BT_ISO_UNICAST
+
+if BT_ISO_BROADCAST
+
+config BT_ISO_MAX_BIG
+	int "Maximum number of Broadcast Isochronous Groups (BIGs) to support"
+	default 1
+	range 1 BT_EXT_ADV_MAX_ADV_SET
+	help
+	  Maximum number of BIGs that are supported by the host. A BIG can be
+	  used for either transmitting or receiving, but not at the same time.
+
+endif # BT_ISO_BROADCAST
+endif # BT_ISO
+
 rsource "common/Kconfig"
 rsource "host/Kconfig"
 rsource "controller/Kconfig"
diff --git a/subsys/bluetooth/Kconfig.iso b/subsys/bluetooth/Kconfig.iso
deleted file mode 100644
index 4c7bb9a03e3..00000000000
--- a/subsys/bluetooth/Kconfig.iso
+++ /dev/null
@@ -1,159 +0,0 @@
-# Bluetooth Isochronous Channel configuration options
-
-# Copyright (c) 2016 Intel Corporation
-# Copyright (c) 2021 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-config BT_ISO
-	bool
-
-config BT_ISO_TX
-	bool
-
-config BT_ISO_RX
-	bool
-
-# TODO: Split between client (central) and server (peripheral)
-config BT_ISO_UNICAST
-	bool
-	depends on BT_CONN
-	select BT_ISO
-	select BT_ISO_TX
-	select BT_ISO_RX
-	help
-	  This option enables support for Bluetooth Unicast
-	  Isochronous channels.
-
-config BT_ISO_PERIPHERAL
-	bool "Bluetooth Isochronous Channel Unicast Peripheral Support"
-	depends on !HAS_BT_CTLR || BT_CTLR_PERIPHERAL_ISO_SUPPORT
-	depends on BT_PERIPHERAL
-	select BT_ISO_UNICAST
-	help
-	  This option enables support for Bluetooth Unicast
-	  Isochronous channels for the peripheral role.
-
-config BT_ISO_CENTRAL
-	bool "Bluetooth Isochronous Channel Unicast Central Support"
-	depends on !HAS_BT_CTLR || BT_CTLR_CENTRAL_ISO_SUPPORT
-	depends on BT_CENTRAL
-	select BT_ISO_UNICAST
-	help
-	  This option enables support for Bluetooth Broadcast
-	  Isochronous channels for the central role.
-
-config BT_ISO_BROADCAST
-	bool
-	select BT_ISO
-	select BT_EXT_ADV
-
-config BT_ISO_BROADCASTER
-	bool "Bluetooth Isochronous Broadcaster Support"
-	depends on !HAS_BT_CTLR || BT_CTLR_ADV_ISO_SUPPORT
-	select BT_ISO_BROADCAST
-	select BT_ISO_TX
-	select BT_BROADCASTER
-	select BT_PER_ADV
-	help
-	  This option enables support for the Bluetooth Isochronous Broadcaster.
-
-config BT_ISO_SYNC_RECEIVER
-	bool "Bluetooth Isochronous Synchronized Receiver Support"
-	depends on !HAS_BT_CTLR || BT_CTLR_SYNC_ISO_SUPPORT
-	depends on BT_OBSERVER
-	select BT_ISO_BROADCAST
-	select BT_ISO_RX
-	select BT_PER_ADV_SYNC
-	help
-	  This option enables support for the Bluetooth Isochronous
-	  Synchronized Receiver.
-
-if BT_ISO
-
-config BT_ISO_MAX_CHAN
-	int "Maximum number of simultaneous ISO channels"
-	depends on BT_ISO
-	default BT_MAX_CONN if BT_CONN
-	default 1
-	range 1 64
-	help
-	  Maximum number of simultaneous Bluetooth isochronous channels
-	  supported.
-
-config BT_ISO_TX_BUF_COUNT
-	int "Number of Isochronous TX buffers"
-	default 1
-	range 1 $(UINT8_MAX)
-	help
-	  Number of buffers available for outgoing Isochronous channel SDUs.
-
-config BT_ISO_TX_FRAG_COUNT
-	int "Number of ISO TX fragment buffers"
-	default 2
-	range 0 $(UINT8_MAX)
-	help
-	  Number of buffers available for fragments of TX buffers. Warning:
-	  setting this to 0 means that the application must ensure that
-	  queued TX buffers never need to be fragmented, i.e. that the
-	  controller's buffer size is large enough. If this is not ensured,
-	  and there are no dedicated fragment buffers, a deadlock may occur.
-	  In most cases the default value of 2 is a safe bet.
-
-config BT_ISO_TX_MTU
-	int "Maximum supported MTU for Isochronous TX buffers"
-	range 1 4095
-	default 247
-	help
-	  Maximum MTU for Isochronous channels TX buffers.
-	  This is the actual data payload. It doesn't include the optional
-	  HCI ISO Data packet fields (e.g. `struct bt_hci_iso_sdu_ts_hdr`).
-	  Set this value to 247 to fit 247 bytes of data within a single
-	  HCI ISO Data packet with Data_Total_Length of 255, utilizing
-	  timestamps.
-
-config BT_ISO_RX_BUF_COUNT
-	int "Number of Isochronous RX buffers"
-	default 1
-	range 1 $(UINT8_MAX)
-	help
-	  Number of buffers available for incoming Isochronous channel SDUs.
-
-config BT_ISO_RX_MTU
-	int "Maximum supported MTU for Isochronous RX buffers"
-	default 251
-	range 23 4095
-	help
-	  Maximum MTU for Isochronous channels RX buffers.
-	  This is the actual data payload. It doesn't include the optional
-	  HCI ISO Data packet fields (e.g. `struct bt_hci_iso_sdu_ts_hdr`)
-
-config BT_ISO_TEST_PARAMS
-	bool "ISO test parameters support"
-	help
-	  Enabling advanced ISO parameters will allow the use of the ISO test
-	  parameters for creating a CIG or a BIG. These test parameters were
-	  intended for testing, but can be used to allow the host to set more
-	  settings that are otherwise usually controlled by the controller.
-
-if BT_ISO_UNICAST
-
-config BT_ISO_MAX_CIG
-	int "Maximum number of Connected Isochronous Groups (CIGs) to support"
-	default 1
-	help
-	  Maximum number of CIGs that are supported by the host. A CIG can be
-	  used for either transmitting or receiving.
-
-endif # BT_ISO_UNICAST
-
-if BT_ISO_BROADCAST
-
-config BT_ISO_MAX_BIG
-	int "Maximum number of Broadcast Isochronous Groups (BIGs) to support"
-	default 1
-	help
-	  Maximum number of BIGs that are supported by the host. A BIG can be
-	  used for either transmitting or receiving, but not at the same time.
-
-endif # BT_ISO_BROADCAST
-endif # BT_ISO
diff --git a/subsys/bluetooth/audio/CMakeLists.txt b/subsys/bluetooth/audio/CMakeLists.txt
index 86f507746be..a7537140a64 100644
--- a/subsys/bluetooth/audio/CMakeLists.txt
+++ b/subsys/bluetooth/audio/CMakeLists.txt
@@ -58,6 +58,7 @@ zephyr_library_sources_ifdef(CONFIG_BT_BAP_BROADCAST_SOURCE bap_broadcast_source
 zephyr_library_sources_ifdef(CONFIG_BT_BAP_BROADCAST_SINK bap_broadcast_sink.c)
 zephyr_library_sources_ifdef(CONFIG_BT_BAP_SCAN_DELEGATOR bap_scan_delegator.c)
 zephyr_library_sources_ifdef(CONFIG_BT_BAP_BROADCAST_ASSISTANT bap_broadcast_assistant.c)
+zephyr_library_sources_ifdef(CONFIG_BT_CCP_CALL_CONTROL_CLIENT ccp_call_control_client.c)
 zephyr_library_sources_ifdef(CONFIG_BT_CCP_CALL_CONTROL_SERVER ccp_call_control_server.c)
 zephyr_library_sources_ifdef(CONFIG_BT_HAS has.c)
 zephyr_library_sources_ifdef(CONFIG_BT_HAS_CLIENT has_client.c)
diff --git a/subsys/bluetooth/audio/Kconfig.aics b/subsys/bluetooth/audio/Kconfig.aics
index bcc6c2fafdb..c2d2283bf9d 100644
--- a/subsys/bluetooth/audio/Kconfig.aics
+++ b/subsys/bluetooth/audio/Kconfig.aics
@@ -10,6 +10,7 @@
 
 config BT_AICS_MAX_INSTANCE_COUNT
 	int "Audio Input Control Service max instance count"
+	depends on BT_SMP
 	default 0
 	range 0 15
 	help
@@ -38,6 +39,7 @@ endif # BT_AICS
 
 config BT_AICS_CLIENT_MAX_INSTANCE_COUNT
 	int "Audio Input Control Service client max instance count"
+	depends on BT_SMP
 	default 0
 	range 0 15
 	help
diff --git a/subsys/bluetooth/audio/Kconfig.ascs b/subsys/bluetooth/audio/Kconfig.ascs
index 21f05dd5200..0c4f05e084d 100644
--- a/subsys/bluetooth/audio/Kconfig.ascs
+++ b/subsys/bluetooth/audio/Kconfig.ascs
@@ -8,6 +8,7 @@
 
 config BT_ASCS
 	bool "Audio Stream Control Service Support"
+	depends on BT_SMP
 	help
 	  This option enables support for Audio Stream Control Service.
 
@@ -39,7 +40,7 @@ config BT_ASCS_MAX_ACTIVE_ASES
 	default BT_ISO_MAX_CHAN
 	range 1 $(UINT16_MAX)
 	help
-	  The number of simultanesouly supported active ASEs, in particular
+	  The number of simultaneously supported active ASEs, in particular
 	  meaning the number of ASEs that are allowed to be in a non-idle state at
 	  a single time.
 
diff --git a/subsys/bluetooth/audio/Kconfig.ccp b/subsys/bluetooth/audio/Kconfig.ccp
index f43557e37a8..c397b831cfc 100644
--- a/subsys/bluetooth/audio/Kconfig.ccp
+++ b/subsys/bluetooth/audio/Kconfig.ccp
@@ -7,6 +7,31 @@
 
 if BT_AUDIO
 
+config BT_CCP_CALL_CONTROL_CLIENT
+	bool "Call Control Profile Client Support"
+	depends on BT_EXT_ADV
+	depends on BT_TBS_CLIENT
+	depends on BT_BONDABLE
+	help
+	  This option enables support for the Call Control Profile Client which uses the Telephone
+	  Bearer Service (TBS) client to control calls on a remote device.
+
+if BT_CCP_CALL_CONTROL_CLIENT
+
+config BT_CCP_CALL_CONTROL_CLIENT_BEARER_COUNT
+	int "Telephone bearer count"
+	default 1
+	range 1 $(UINT8_MAX) if BT_TBS_CLIENT_TBS
+	range 1 1
+	help
+	  The number of supported telephone bearers on the CCP Call Control Client
+
+module = BT_CCP_CALL_CONTROL_CLIENT
+module-str = "Call Control Profile Client"
+source "subsys/logging/Kconfig.template.log_config"
+
+endif # BT_CCP_CALL_CONTROL_CLIENT
+
 config BT_CCP_CALL_CONTROL_SERVER
 	bool "Call Control Profile Call Control Server Support"
 	depends on BT_EXT_ADV
diff --git a/subsys/bluetooth/audio/Kconfig.csip b/subsys/bluetooth/audio/Kconfig.csip
index b0a09606bcf..6601fc38ff6 100644
--- a/subsys/bluetooth/audio/Kconfig.csip
+++ b/subsys/bluetooth/audio/Kconfig.csip
@@ -10,6 +10,8 @@
 
 config BT_CSIP_SET_MEMBER
 	bool "Coordinated Set Identification Profile Set Member support"
+	depends on BT_GATT_DYNAMIC_DB
+	depends on BT_SMP
 	imply BT_EXT_ADV if BT_PRIVACY
 	help
 	  This option enables support for Coordinated Set Identification
@@ -35,7 +37,7 @@ config BT_CSIP_SET_MEMBER_ENC_SIRK_SUPPORT
 	  Enables support encrypting the SIRK.
 
 config BT_CSIP_SET_MEMBER_MAX_INSTANCE_COUNT
-	int "Coordinated Set Identification Profle max service instance count"
+	int "Coordinated Set Identification Profile max service instance count"
 	default 1
 	range 1 $(UINT8_MAX)
 	help
@@ -64,6 +66,7 @@ config BT_CSIP_SET_COORDINATOR
 	bool "Coordinated Set Identification Profile Set Coordinator Support"
 	depends on BT_GATT_CLIENT
 	depends on BT_GATT_AUTO_DISCOVER_CCC
+	depends on BT_SMP
 	help
 	  This option enables support for Coordinated Set Identification
 	  Profile Set Coordinator.
diff --git a/subsys/bluetooth/audio/Kconfig.has b/subsys/bluetooth/audio/Kconfig.has
index adf8cda6bbb..541ee84468b 100644
--- a/subsys/bluetooth/audio/Kconfig.has
+++ b/subsys/bluetooth/audio/Kconfig.has
@@ -60,5 +60,6 @@ config BT_HAS_CLIENT
 	depends on BT_GATT_CLIENT
 	depends on BT_GATT_AUTO_DISCOVER_CCC
 	depends on BT_GATT_AUTO_UPDATE_MTU
+	depends on BT_SMP
 	help
 	  This option enables support for Hearing Access Service Client.
diff --git a/subsys/bluetooth/audio/Kconfig.mcs b/subsys/bluetooth/audio/Kconfig.mcs
index 6c08dd57d20..d1103f796d3 100644
--- a/subsys/bluetooth/audio/Kconfig.mcs
+++ b/subsys/bluetooth/audio/Kconfig.mcs
@@ -13,6 +13,7 @@ config BT_MCS
 	depends on MCTL_LOCAL_PLAYER_REMOTE_CONTROL
 	depends on UTF8
 	depends on BT_GATT_DYNAMIC_DB
+	depends on BT_SMP
 	help
 	  This option enables support for the Media Control Service.
 
@@ -22,6 +23,7 @@ config BT_MCC
 	bool "Media Control Client Support"
 	depends on BT_GATT_CLIENT
 	depends on BT_GATT_AUTO_DISCOVER_CCC
+	depends on BT_SMP
 	help
 	  This option enables support for the Media Control Client.
 
diff --git a/subsys/bluetooth/audio/Kconfig.pacs b/subsys/bluetooth/audio/Kconfig.pacs
index fba32e709fd..a0e851f1ae6 100644
--- a/subsys/bluetooth/audio/Kconfig.pacs
+++ b/subsys/bluetooth/audio/Kconfig.pacs
@@ -9,6 +9,8 @@ menu "Published Audio Capabilities (PAC) options"
 
 config BT_PAC_SNK
 	bool "Sink PAC Characteristic Support"
+	depends on BT_GATT_DYNAMIC_DB
+	depends on BT_SMP
 	help
 	  This option enables support for Sink Published Audio Capabilities.
 
@@ -43,6 +45,7 @@ endif # BT_PACS_SNK
 
 config BT_PAC_SRC
 	bool "Source PAC Characteristic Support"
+	depends on BT_GATT_DYNAMIC_DB
 	help
 	  This option enables support for Source Published Audio Capabilities.
 
diff --git a/subsys/bluetooth/audio/Kconfig.tbs b/subsys/bluetooth/audio/Kconfig.tbs
index 14729499bee..557786a833c 100644
--- a/subsys/bluetooth/audio/Kconfig.tbs
+++ b/subsys/bluetooth/audio/Kconfig.tbs
@@ -13,6 +13,7 @@ if BT_AUDIO
 config BT_TBS
 	bool "Telephone Bearer Service Support"
 	depends on BT_GATT_DYNAMIC_DB
+	depends on BT_SMP
 	depends on UTF8
 	help
 	  This option enables support for Telephone Bearer Service. By default this only
@@ -51,6 +52,14 @@ config BT_TBS_MAX_SCHEME_LIST_LENGTH
 	help
 	  Sets the maximum length of the URI scheme list.
 
+config BT_TBS_LOCK_TIMEOUT
+	int "Milliseconds of timeout when handling concurrent operations"
+	range 0 1000
+	default 10
+	help
+	  The number of milliseconds that the TBS implementation will maximum wait before rejecting
+	  an write request if another is already in progress in another thread.
+
 endif # BT_TBS
 
 
@@ -58,20 +67,24 @@ endif # BT_TBS
 
 config BT_TBS_CLIENT_GTBS
 	bool "Generic Telephone Bearer Service client support"
+	depends on BT_GATT_CLIENT
+	depends on BT_GATT_AUTO_DISCOVER_CCC
+	depends on BT_SMP
 	depends on UTF8
 	help
 	  This option enables support for the GTBS-oriented Call Control client.
 
 config BT_TBS_CLIENT_TBS
 	bool "Telephone Bearer Service client support"
+	depends on BT_GATT_CLIENT
+	depends on BT_GATT_AUTO_DISCOVER_CCC
+	depends on BT_SMP
 	depends on UTF8
 	help
 	  This option enables support for the TBS-oriented Call Control client.
 
 config BT_TBS_CLIENT
 	def_bool BT_TBS_CLIENT_GTBS || BT_TBS_CLIENT_TBS
-	depends on BT_GATT_CLIENT
-	depends on BT_GATT_AUTO_DISCOVER_CCC
 
 if BT_TBS_CLIENT
 
diff --git a/subsys/bluetooth/audio/Kconfig.vcp b/subsys/bluetooth/audio/Kconfig.vcp
index 3699e56c822..7b23a544ee4 100644
--- a/subsys/bluetooth/audio/Kconfig.vcp
+++ b/subsys/bluetooth/audio/Kconfig.vcp
@@ -11,6 +11,7 @@
 config BT_VCP_VOL_REND
 	bool "Volume Control Profile Volume Renderer Support"
 	depends on BT_GATT_DYNAMIC_DB
+	depends on BT_SMP
 	help
 	  This option enables support for Volume Control Profile Volume Renderer
 	  role and the Volume Control Service.
@@ -60,6 +61,7 @@ config BT_VCP_VOL_CTLR
 	bool "Volume Control Profile Volume Controller Support"
 	depends on BT_GATT_CLIENT
 	depends on BT_GATT_AUTO_DISCOVER_CCC
+	depends on BT_SMP
 	help
 	  This option enables support for Volume Control Profile Volume
 	  Controller.
diff --git a/subsys/bluetooth/audio/Kconfig.vocs b/subsys/bluetooth/audio/Kconfig.vocs
index d582b2aaab4..94b0748f4e8 100644
--- a/subsys/bluetooth/audio/Kconfig.vocs
+++ b/subsys/bluetooth/audio/Kconfig.vocs
@@ -9,6 +9,7 @@
 
 config BT_VOCS_MAX_INSTANCE_COUNT
 	int "Volume Offset Control Service max instance count"
+	depends on BT_SMP
 	default 0
 	range 0 15
 	help
@@ -36,6 +37,7 @@ endif # BT_VOCS
 
 config BT_VOCS_CLIENT_MAX_INSTANCE_COUNT
 	int "Volume Offset Control Service client max instance count"
+	depends on BT_SMP
 	default 0
 	range 0 15
 	help
diff --git a/subsys/bluetooth/audio/aics.c b/subsys/bluetooth/audio/aics.c
index 222969aba24..9c87f718adc 100644
--- a/subsys/bluetooth/audio/aics.c
+++ b/subsys/bluetooth/audio/aics.c
@@ -487,7 +487,7 @@ int bt_aics_register(struct bt_aics *aics, struct bt_aics_register_param *param)
 		return -EINVAL;
 	}
 
-	CHECKIF(param->type > BT_AICS_INPUT_TYPE_STREAMING) {
+	CHECKIF(param->type > BT_AICS_INPUT_TYPE_AMBIENT) {
 		LOG_DBG("Invalid AICS input type value: %u", param->type);
 		return -EINVAL;
 	}
diff --git a/subsys/bluetooth/audio/ascs.c b/subsys/bluetooth/audio/ascs.c
index ae94530214c..6f4924dc60d 100644
--- a/subsys/bluetooth/audio/ascs.c
+++ b/subsys/bluetooth/audio/ascs.c
@@ -3,7 +3,7 @@
  */
 /*
  * Copyright (c) 2020 Intel Corporation
- * Copyright (c) 2022-2023 Nordic Semiconductor ASA
+ * Copyright (c) 2022-2025 Nordic Semiconductor ASA
  * Copyright (c) 2024 Demant A/S
  *
  * SPDX-License-Identifier: Apache-2.0
@@ -200,17 +200,6 @@ static void ase_free(struct bt_ascs_ase *ase)
 	(void)k_work_cancel_delayable(&ase->state_transition_work);
 }
 
-static uint16_t get_max_ntf_size(struct bt_conn *conn)
-{
-	const uint16_t mtu = conn == NULL ? 0 : bt_gatt_get_mtu(conn);
-
-	if (mtu > NTF_HEADER_SIZE) {
-		return mtu - NTF_HEADER_SIZE;
-	}
-
-	return 0U;
-}
-
 static int ase_state_notify(struct bt_ascs_ase *ase)
 {
 	struct bt_conn *conn = ase->conn;
@@ -238,7 +227,7 @@ static int ase_state_notify(struct bt_ascs_ase *ase)
 
 	ascs_ep_get_status(&ase->ep, &ase_buf);
 
-	max_ntf_size = get_max_ntf_size(conn);
+	max_ntf_size = bt_audio_get_max_ntf_size(conn);
 
 	ntf_size = MIN(max_ntf_size, ase_buf.len);
 	if (ntf_size < ase_buf.len) {
@@ -329,10 +318,7 @@ static void ase_enter_state_idle(struct bt_ascs_ase *ase)
 
 	ase->ep.receiver_ready = false;
 
-	if (stream->conn != NULL) {
-		bt_conn_unref(stream->conn);
-		stream->conn = NULL;
-	}
+	bt_bap_stream_detach(stream);
 
 	ops = stream->ops;
 	if (ops != NULL && ops->released != NULL) {
@@ -398,6 +384,11 @@ static void ase_enter_state_streaming(struct bt_ascs_ase *ase)
 
 	__ASSERT_NO_MSG(stream != NULL);
 
+	/* Setup the ISO data path when the stream is started. We could do it earlier when the CIS
+	 * is connected, but then we would just receive audio data that we would then just discard
+	 */
+	bt_bap_setup_iso_data_path(stream);
+
 	ops = stream->ops;
 	if (ops != NULL && ops->started != NULL) {
 		ops->started(stream);
@@ -431,6 +422,14 @@ static void ase_exit_state_streaming(struct bt_ascs_ase *ase)
 		reason = BT_HCI_ERR_UNSPECIFIED;
 	}
 
+	if (ase->ep.iso != NULL && ase->ep.iso->chan.state == BT_ISO_STATE_CONNECTED) {
+		/* Remove the ISO data path as we no longer want to process any ISO data for this
+		 * stream, but only if the CIS is still connected. If the CIS disconnected, then the
+		 * data path is automatically removed by the controller
+		 */
+		bt_bap_remove_iso_data_path(stream);
+	}
+
 	ops = stream->ops;
 
 	/*
@@ -1488,32 +1487,12 @@ static void ascs_cp_cfg_changed(const struct bt_gatt_attr *attr, uint16_t value)
 	LOG_DBG("attr %p value 0x%04x", attr, value);
 }
 
-struct codec_cap_lookup_id_data {
-	uint8_t id;
-	uint16_t cid;
-	uint16_t vid;
-	const struct bt_audio_codec_cap *codec_cap;
-};
-
-static bool codec_lookup_id(const struct bt_pacs_cap *cap, void *user_data)
-{
-	struct codec_cap_lookup_id_data *data = user_data;
-
-	if (cap->codec_cap->id == data->id && cap->codec_cap->cid == data->cid &&
-	    cap->codec_cap->vid == data->vid) {
-		data->codec_cap = cap->codec_cap;
-
-		return false;
-	}
-
-	return true;
-}
-
 static int ascs_ep_set_codec(struct bt_bap_ep *ep, uint8_t id, uint16_t cid, uint16_t vid,
 			     uint8_t *cc, uint8_t len, struct bt_bap_ascs_rsp *rsp)
 {
+	const struct bt_audio_codec_cap *codec_cap;
 	struct bt_audio_codec_cfg *codec_cfg;
-	struct codec_cap_lookup_id_data lookup_data = {
+	const struct bt_pac_codec codec_id = {
 		.id = id,
 		.cid = cid,
 		.vid = vid,
@@ -1530,11 +1509,11 @@ static int ascs_ep_set_codec(struct bt_bap_ep *ep, uint8_t id, uint16_t cid, uin
 	LOG_DBG("ep %p dir %s codec id 0x%02x cid 0x%04x vid 0x%04x len %u",
 		ep, bt_audio_dir_str(ep->dir), id, cid, vid, len);
 
-	bt_pacs_cap_foreach(ep->dir, codec_lookup_id, &lookup_data);
-
-	if (lookup_data.codec_cap == NULL) {
-		LOG_DBG("Codec with id %u for dir %s is not supported by our capabilities",
-			id, bt_audio_dir_str(ep->dir));
+	codec_cap = bt_pacs_get_codec_cap(ep->dir, &codec_id);
+	if (codec_cap == NULL) {
+		LOG_DBG("Codec with id 0x%02x cid 0x%04x and vid 0x%04x for dir %s is not "
+			"supported by our capabilities",
+			codec_id.id, codec_id.cid, codec_id.vid, bt_audio_dir_str(ep->dir));
 
 		*rsp = BT_BAP_ASCS_RSP(BT_BAP_ASCS_RSP_CODE_CONF_INVALID,
 				       BT_BAP_ASCS_REASON_CODEC);
@@ -1546,7 +1525,7 @@ static int ascs_ep_set_codec(struct bt_bap_ep *ep, uint8_t id, uint16_t cid, uin
 	codec_cfg->vid = vid;
 	codec_cfg->data_len = len;
 	memcpy(codec_cfg->data, cc, len);
-	codec_cfg->path_id = lookup_data.codec_cap->path_id;
+	codec_cfg->path_id = codec_cap->path_id;
 
 	*rsp = BT_BAP_ASCS_RSP(BT_BAP_ASCS_RSP_CODE_SUCCESS, BT_BAP_ASCS_REASON_NONE);
 
@@ -1728,10 +1707,11 @@ int bt_ascs_config_ase(struct bt_conn *conn, struct bt_bap_stream *stream,
 		       struct bt_audio_codec_cfg *codec_cfg,
 		       const struct bt_bap_qos_cfg_pref *qos_pref)
 {
-	int err;
+	const struct bt_audio_codec_cap *codec_cap;
 	struct bt_ascs_ase *ase = NULL;
+	struct bt_pac_codec codec_id;
 	struct bt_bap_ep *ep;
-	struct codec_cap_lookup_id_data lookup_data;
+	int err;
 
 	CHECKIF(conn == NULL || stream == NULL || codec_cfg == NULL || qos_pref == NULL) {
 		LOG_DBG("NULL value(s) supplied)");
@@ -1763,15 +1743,15 @@ int bt_ascs_config_ase(struct bt_conn *conn, struct bt_bap_stream *stream,
 		return -EINVAL;
 	}
 
-	lookup_data.id = codec_cfg->id;
-	lookup_data.cid = codec_cfg->cid;
-	lookup_data.vid = codec_cfg->vid;
-
-	bt_pacs_cap_foreach(ep->dir, codec_lookup_id, &lookup_data);
+	codec_id.id = codec_cfg->id;
+	codec_id.cid = codec_cfg->cid;
+	codec_id.vid = codec_cfg->vid;
 
-	if (lookup_data.codec_cap == NULL) {
-		LOG_DBG("Codec with id %u for dir %s is not supported by our capabilities",
-			codec_cfg->id, bt_audio_dir_str(ep->dir));
+	codec_cap = bt_pacs_get_codec_cap(ep->dir, &codec_id);
+	if (codec_cap == NULL) {
+		LOG_DBG("Codec with id 0x%02x cid 0x%04x and vid 0x%04x for dir %s is not "
+			"supported by our capabilities",
+			codec_id.id, codec_id.cid, codec_id.vid, bt_audio_dir_str(ep->dir));
 		return -ENOENT;
 	}
 
@@ -1793,7 +1773,7 @@ int bt_ascs_config_ase(struct bt_conn *conn, struct bt_bap_stream *stream,
 
 static uint16_t get_max_ase_rsp_for_conn(struct bt_conn *conn)
 {
-	const uint16_t max_ntf_size = get_max_ntf_size(conn);
+	const uint16_t max_ntf_size = bt_audio_get_max_ntf_size(conn);
 	const size_t rsp_hdr_size = sizeof(struct bt_ascs_cp_rsp);
 
 	if (max_ntf_size > rsp_hdr_size) {
@@ -2029,12 +2009,6 @@ static void ase_qos(struct bt_ascs_ase *ase, uint8_t cig_id, uint8_t cis_id,
 	ep->qos = *qos;
 	stream->qos = &ep->qos;
 
-	/* We setup the data path here, as this is the earliest where
-	 * we have the ISO <-> EP coupling completed (due to setting
-	 * the CIS ID in the QoS procedure).
-	 */
-	bt_bap_iso_configure_data_path(ep, stream->codec_cfg);
-
 	ep->cig_id = cig_id;
 	ep->cis_id = cis_id;
 
@@ -3290,7 +3264,7 @@ int bt_ascs_unregister(void)
 	}
 
 	err = bt_gatt_service_unregister(&ascs_svc);
-	/* If unregistration was succesfull, make sure to reset ascs_attrs so it can be used for
+	/* If unregistration was successful, make sure to reset ascs_attrs so it can be used for
 	 * new registrations
 	 */
 	if (err != 0) {
diff --git a/subsys/bluetooth/audio/ascs_internal.h b/subsys/bluetooth/audio/ascs_internal.h
index 1651e21f42d..97658999cc6 100644
--- a/subsys/bluetooth/audio/ascs_internal.h
+++ b/subsys/bluetooth/audio/ascs_internal.h
@@ -11,6 +11,8 @@
 #ifndef BT_ASCS_INTERNAL_H
 #define BT_ASCS_INTERNAL_H
 
+#include <stdint.h>
+
 #include <zephyr/bluetooth/audio/audio.h>
 #include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/conn.h>
diff --git a/subsys/bluetooth/audio/audio.c b/subsys/bluetooth/audio/audio.c
index 55412c4f7e1..75109d4fd96 100644
--- a/subsys/bluetooth/audio/audio.c
+++ b/subsys/bluetooth/audio/audio.c
@@ -23,6 +23,7 @@
 #include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/sys/check.h>
+#include <zephyr/toolchain.h>
 
 #include "audio_internal.h"
 
@@ -256,4 +257,16 @@ ssize_t bt_audio_ccc_cfg_write(struct bt_conn *conn, const struct bt_gatt_attr *
 
 	return sizeof(value);
 }
+
+uint16_t bt_audio_get_max_ntf_size(struct bt_conn *conn)
+{
+	const uint8_t att_ntf_header_size = 3; /* opcode (1) + handle (2) */
+	const uint16_t mtu = conn == NULL ? 0 : bt_gatt_get_mtu(conn);
+
+	if (mtu > att_ntf_header_size) {
+		return mtu - att_ntf_header_size;
+	}
+
+	return 0U;
+}
 #endif /* CONFIG_BT_CONN */
diff --git a/subsys/bluetooth/audio/audio_internal.h b/subsys/bluetooth/audio/audio_internal.h
index 4336b8ede06..74cc35b4d04 100644
--- a/subsys/bluetooth/audio/audio_internal.h
+++ b/subsys/bluetooth/audio/audio_internal.h
@@ -61,9 +61,10 @@ ssize_t bt_audio_ccc_cfg_write(struct bt_conn *conn, const struct bt_gatt_attr *
 			       uint16_t value);
 
 /** Helper to define LE Audio CCC descriptor. */
-#define BT_AUDIO_CCC(_changed)								\
-	BT_GATT_CCC_MANAGED(((struct _bt_gatt_ccc[])					\
-		{BT_GATT_CCC_INITIALIZER(_changed, bt_audio_ccc_cfg_write, NULL)}),	\
+#define BT_AUDIO_CCC(_changed)                                                                     \
+	BT_GATT_CCC_MANAGED(                                                                       \
+		((struct bt_gatt_ccc_managed_user_data[]){BT_GATT_CCC_MANAGED_USER_DATA_INIT(      \
+			_changed, bt_audio_ccc_cfg_write, NULL)}),                                 \
 		(BT_GATT_PERM_READ | BT_GATT_PERM_WRITE_ENCRYPT))
 
 static inline const char *bt_audio_dir_str(enum bt_audio_dir dir)
@@ -79,3 +80,4 @@ static inline const char *bt_audio_dir_str(enum bt_audio_dir dir)
 }
 
 bool bt_audio_valid_ltv(const uint8_t *data, uint8_t data_len);
+uint16_t bt_audio_get_max_ntf_size(struct bt_conn *conn);
diff --git a/subsys/bluetooth/audio/bap_base.c b/subsys/bluetooth/audio/bap_base.c
index cba23a66c8f..313456f3bde 100644
--- a/subsys/bluetooth/audio/bap_base.c
+++ b/subsys/bluetooth/audio/bap_base.c
@@ -30,7 +30,6 @@ LOG_MODULE_REGISTER(bt_bap_base, CONFIG_BT_BAP_BASE_LOG_LEVEL);
 /* The BASE and the following defines are defined by BAP v1.0.1, section 3.7.2.2 Basic Audio
  * Announcements
  */
-#define BASE_MAX_SIZE            (UINT8_MAX - 1 /* type */ - BT_UUID_SIZE_16)
 #define BASE_CODEC_ID_SIZE       (1 /* id */ + 2 /* cid */ + 2 /* vid */)
 #define BASE_PD_SIZE             3
 #define BASE_SUBGROUP_COUNT_SIZE 1
@@ -39,14 +38,14 @@ LOG_MODULE_REGISTER(bt_bap_base, CONFIG_BT_BAP_BASE_LOG_LEVEL);
 #define BASE_META_LEN_SIZE       1
 #define BASE_BIS_INDEX_SIZE      1
 #define BASE_BIS_CC_LEN_SIZE     1
-#define BASE_SUBGROUP_MAX_SIZE   (BASE_MAX_SIZE - BASE_PD_SIZE - BASE_SUBGROUP_COUNT_SIZE)
+#define BASE_SUBGROUP_MAX_SIZE   (BT_BASE_MAX_SIZE - BASE_PD_SIZE - BASE_SUBGROUP_COUNT_SIZE)
 #define BASE_SUBGROUP_MIN_SIZE                                                                     \
 	(BASE_NUM_BIS_SIZE + BASE_CODEC_ID_SIZE + BASE_CC_LEN_SIZE + BASE_META_LEN_SIZE +          \
 	 BASE_BIS_INDEX_SIZE + BASE_BIS_CC_LEN_SIZE)
 #define BASE_MIN_SIZE                                                                              \
 	(BT_UUID_SIZE_16 + BASE_PD_SIZE + BASE_SUBGROUP_COUNT_SIZE + BASE_SUBGROUP_MIN_SIZE)
 #define BASE_SUBGROUP_MAX_COUNT                                                                    \
-	((BASE_MAX_SIZE - BASE_PD_SIZE - BASE_SUBGROUP_COUNT_SIZE) / BASE_SUBGROUP_MIN_SIZE)
+	((BT_BASE_MAX_SIZE - BASE_PD_SIZE - BASE_SUBGROUP_COUNT_SIZE) / BASE_SUBGROUP_MIN_SIZE)
 
 static uint32_t base_pull_pd(struct net_buf_simple *net_buf)
 {
@@ -233,7 +232,7 @@ int bt_bap_base_get_size(const struct bt_bap_base *base)
 		return -EINVAL;
 	}
 
-	net_buf_simple_init_with_data(&net_buf, (void *)base, BASE_MAX_SIZE);
+	net_buf_simple_init_with_data(&net_buf, (void *)base, BT_BASE_MAX_SIZE);
 	base_pull_pd(&net_buf);
 	size += BASE_PD_SIZE;
 	subgroup_count = net_buf_simple_pull_u8(&net_buf);
@@ -301,7 +300,7 @@ int bt_bap_base_get_subgroup_count(const struct bt_bap_base *base)
 		return -EINVAL;
 	}
 
-	net_buf_simple_init_with_data(&net_buf, (void *)base, BASE_MAX_SIZE);
+	net_buf_simple_init_with_data(&net_buf, (void *)base, BT_BASE_MAX_SIZE);
 	base_pull_pd(&net_buf);
 	subgroup_count = net_buf_simple_pull_u8(&net_buf);
 
@@ -329,7 +328,7 @@ int bt_bap_base_foreach_subgroup(const struct bt_bap_base *base,
 		return -EINVAL;
 	}
 
-	net_buf_simple_init_with_data(&net_buf, (void *)base, BASE_MAX_SIZE);
+	net_buf_simple_init_with_data(&net_buf, (void *)base, BT_BASE_MAX_SIZE);
 	base_pull_pd(&net_buf);
 	subgroup_count = net_buf_simple_pull_u8(&net_buf);
 
diff --git a/subsys/bluetooth/audio/bap_broadcast_assistant.c b/subsys/bluetooth/audio/bap_broadcast_assistant.c
index 5c3973a57f1..34197b99030 100644
--- a/subsys/bluetooth/audio/bap_broadcast_assistant.c
+++ b/subsys/bluetooth/audio/bap_broadcast_assistant.c
@@ -48,9 +48,8 @@ LOG_MODULE_REGISTER(bt_bap_broadcast_assistant, CONFIG_BT_BAP_BROADCAST_ASSISTAN
 
 #include "common/bt_str.h"
 
+#include "audio_internal.h"
 #include "bap_internal.h"
-#include "../host/conn_internal.h"
-#include "../host/hci_core.h"
 
 #define MINIMUM_RECV_STATE_LEN          15
 
@@ -209,12 +208,30 @@ static bool past_available(const struct bt_conn *conn,
 			   uint8_t sid)
 {
 	if (IS_ENABLED(CONFIG_BT_PER_ADV_SYNC_TRANSFER_SENDER)) {
+		struct bt_le_local_features local_features;
+		struct bt_conn_remote_info remote_info;
+		int err;
+
+		err = bt_le_get_local_features(&local_features);
+		if (err != 0) {
+			LOG_DBG("Failed to get local features: %d", err);
+			return false;
+		}
+
+		err = bt_conn_get_remote_info(conn, &remote_info);
+		if (err != 0) {
+			LOG_DBG("Failed to get remote info: %d", err);
+			return false;
+		}
+
 		LOG_DBG("%p remote %s PAST, local %s PAST", (void *)conn,
-			BT_FEAT_LE_PAST_RECV(conn->le.features) ? "supports" : "does not support",
-			BT_FEAT_LE_PAST_SEND(bt_dev.le.features) ? "supports" : "does not support");
+			BT_FEAT_LE_PAST_RECV(remote_info.le.features) ? "supports"
+								      : "does not support",
+			BT_FEAT_LE_PAST_SEND(local_features.features) ? "supports"
+								      : "does not support");
 
-		return BT_FEAT_LE_PAST_RECV(conn->le.features) &&
-		       BT_FEAT_LE_PAST_SEND(bt_dev.le.features) &&
+		return BT_FEAT_LE_PAST_RECV(remote_info.le.features) &&
+		       BT_FEAT_LE_PAST_SEND(local_features.features) &&
 		       bt_le_per_adv_sync_lookup_addr(adv_addr, sid) != NULL;
 	} else {
 		return false;
@@ -378,7 +395,7 @@ static uint8_t broadcast_assistant_bap_ntf_read_func(struct bt_conn *conn, uint8
 		return BT_GATT_ITER_STOP;
 	}
 
-	LOG_DBG("conn %p err 0x%02x len %u", conn, err, length);
+	LOG_DBG("conn %p err 0x%02x len %u", (void *)conn, err, length);
 
 	if (err) {
 		LOG_DBG("Failed to read: %u", err);
@@ -427,7 +444,7 @@ static void long_bap_read(struct bt_conn *conn, uint16_t handle)
 	}
 
 	if (atomic_test_and_set_bit(inst->flags, BAP_BA_FLAG_BUSY)) {
-		LOG_DBG("conn %p", conn);
+		LOG_DBG("conn %p", (void *)conn);
 
 		/* If the client is busy reading reschedule the long read */
 		struct bt_conn_info conn_info;
@@ -514,8 +531,7 @@ static uint8_t notify_handler(struct bt_conn *conn,
 	}
 
 	if (length != 0) {
-		const uint8_t att_ntf_header_size = 3; /* opcode (1) + handle (2) */
-		const uint16_t max_ntf_size = bt_gatt_get_mtu(conn) - att_ntf_header_size;
+		const uint16_t max_ntf_size = bt_audio_get_max_ntf_size(conn);
 
 		/* Cancel any pending long reads containing now obsolete information */
 		(void)k_work_cancel_delayable(&inst->bap_read_work);
diff --git a/subsys/bluetooth/audio/bap_broadcast_sink.c b/subsys/bluetooth/audio/bap_broadcast_sink.c
index 7e55c8c3aa2..36ba199052c 100644
--- a/subsys/bluetooth/audio/bap_broadcast_sink.c
+++ b/subsys/bluetooth/audio/bap_broadcast_sink.c
@@ -1,7 +1,7 @@
 /*  Bluetooth Audio Broadcast Sink */
 
 /*
- * Copyright (c) 2021-2024 Nordic Semiconductor ASA
+ * Copyright (c) 2021-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -43,6 +43,7 @@
 #include "audio_internal.h"
 #include "bap_iso.h"
 #include "bap_endpoint.h"
+#include "pacs_internal.h"
 
 LOG_MODULE_REGISTER(bt_bap_broadcast_sink, CONFIG_BT_BAP_BROADCAST_SINK_LOG_LEVEL);
 
@@ -62,6 +63,11 @@ struct codec_cap_lookup_id_data {
 
 static sys_slist_t sink_cbs = SYS_SLIST_STATIC_INIT(&sink_cbs);
 
+/* The mod_src_param is and shall only be used by the BT RX thread. It is statically defined due to
+ * the size of it, and that it's configurable in size, and can cause stack overflow issues otherwise
+ */
+static struct bt_bap_scan_delegator_mod_src_param mod_src_param;
+
 static void broadcast_sink_cleanup(struct bt_bap_broadcast_sink *sink);
 
 static bool find_recv_state_by_sink_cb(const struct bt_bap_scan_delegator_recv_state *recv_state,
@@ -102,7 +108,6 @@ static bool find_recv_state_by_pa_sync_cb(const struct bt_bap_scan_delegator_rec
 static void update_recv_state_big_synced(const struct bt_bap_broadcast_sink *sink)
 {
 	const struct bt_bap_scan_delegator_recv_state *recv_state;
-	struct bt_bap_scan_delegator_mod_src_param mod_src_param = {0};
 	int err;
 
 	recv_state = bt_bap_scan_delegator_find_state(find_recv_state_by_sink_cb, (void *)sink);
@@ -112,6 +117,8 @@ static void update_recv_state_big_synced(const struct bt_bap_broadcast_sink *sin
 		return;
 	}
 
+	(void)memset(&mod_src_param, 0, sizeof(mod_src_param));
+
 	mod_src_param.num_subgroups = sink->subgroup_count;
 	for (uint8_t i = 0U; i < sink->subgroup_count; i++) {
 		struct bt_bap_bass_subgroup *subgroup_param = &mod_src_param.subgroups[i];
@@ -121,7 +128,8 @@ static void update_recv_state_big_synced(const struct bt_bap_broadcast_sink *sin
 		subgroup_param->bis_sync = sink_subgroup->bis_indexes & sink->indexes_bitfield;
 	}
 
-	if (recv_state->encrypt_state == BT_BAP_BIG_ENC_STATE_BCODE_REQ) {
+	if (recv_state->encrypt_state == BT_BAP_BIG_ENC_STATE_BCODE_REQ ||
+	    recv_state->encrypt_state == BT_BAP_BIG_ENC_STATE_BAD_CODE) {
 		mod_src_param.encrypt_state = BT_BAP_BIG_ENC_STATE_DEC;
 	} else {
 		mod_src_param.encrypt_state = recv_state->encrypt_state;
@@ -144,7 +152,6 @@ static void update_recv_state_big_synced(const struct bt_bap_broadcast_sink *sin
 static void update_recv_state_big_cleared(const struct bt_bap_broadcast_sink *sink,
 					  uint8_t reason)
 {
-	struct bt_bap_scan_delegator_mod_src_param mod_src_param = { 0 };
 	const struct bt_bap_scan_delegator_recv_state *recv_state;
 	int err;
 
@@ -156,6 +163,8 @@ static void update_recv_state_big_cleared(const struct bt_bap_broadcast_sink *si
 		return;
 	}
 
+	(void)memset(&mod_src_param, 0, sizeof(mod_src_param));
+
 	if ((recv_state->encrypt_state == BT_BAP_BIG_ENC_STATE_BCODE_REQ ||
 	     recv_state->encrypt_state == BT_BAP_BIG_ENC_STATE_DEC) &&
 	    reason == BT_HCI_ERR_TERM_DUE_TO_MIC_FAIL) {
@@ -355,6 +364,9 @@ static void broadcast_sink_iso_connected(struct bt_iso_chan *chan)
 
 	broadcast_sink_set_ep_state(ep, BT_BAP_EP_STATE_STREAMING);
 
+	/* Setup the ISO data path */
+	bt_bap_setup_iso_data_path(stream);
+
 	if (ops != NULL && ops->started != NULL) {
 		ops->started(stream);
 	} else {
@@ -484,7 +496,6 @@ static void broadcast_sink_add_src(struct bt_bap_broadcast_sink *sink)
 
 static bool base_subgroup_meta_cb(const struct bt_bap_base_subgroup *subgroup, void *user_data)
 {
-	struct bt_bap_scan_delegator_mod_src_param *mod_src_param = user_data;
 	struct bt_bap_bass_subgroup *subgroup_param;
 	uint8_t *meta;
 	int ret;
@@ -494,19 +505,18 @@ static bool base_subgroup_meta_cb(const struct bt_bap_base_subgroup *subgroup, v
 		return false;
 	}
 
-	subgroup_param = &mod_src_param->subgroups[mod_src_param->num_subgroups++];
+	subgroup_param = &mod_src_param.subgroups[mod_src_param.num_subgroups++];
 	subgroup_param->metadata_len = (uint8_t)ret;
 	memcpy(subgroup_param->metadata, meta, subgroup_param->metadata_len);
 
 	return true;
 }
 
-static int update_recv_state_base_copy_meta(const struct bt_bap_base *base,
-					    struct bt_bap_scan_delegator_mod_src_param *param)
+static int update_recv_state_base_copy_meta(const struct bt_bap_base *base)
 {
 	int err;
 
-	err = bt_bap_base_foreach_subgroup(base, base_subgroup_meta_cb, param);
+	err = bt_bap_base_foreach_subgroup(base, base_subgroup_meta_cb, NULL);
 	if (err != 0) {
 		LOG_DBG("Failed to parse subgroups: %d", err);
 		return err;
@@ -518,7 +528,6 @@ static int update_recv_state_base_copy_meta(const struct bt_bap_base *base,
 static void update_recv_state_base(const struct bt_bap_broadcast_sink *sink,
 				   const struct bt_bap_base *base)
 {
-	struct bt_bap_scan_delegator_mod_src_param mod_src_param = { 0 };
 	const struct bt_bap_scan_delegator_recv_state *recv_state;
 	int err;
 
@@ -529,7 +538,9 @@ static void update_recv_state_base(const struct bt_bap_broadcast_sink *sink,
 		return;
 	}
 
-	err = update_recv_state_base_copy_meta(base, &mod_src_param);
+	(void)memset(&mod_src_param, 0, sizeof(mod_src_param));
+
+	err = update_recv_state_base_copy_meta(base);
 	if (err != 0) {
 		LOG_WRN("Failed to modify Receive State for sink %p: %d", sink, err);
 		return;
@@ -553,127 +564,61 @@ static void update_recv_state_base(const struct bt_bap_broadcast_sink *sink,
 	}
 }
 
-static bool codec_lookup_id(const struct bt_pacs_cap *cap, void *user_data)
+static bool base_subgroup_bis_count_cb(const struct bt_bap_base_subgroup *subgroup, void *user_data)
 {
-	struct codec_cap_lookup_id_data *data = user_data;
-
-	if (cap->codec_cap->id == data->id) {
-		data->codec_cap = cap->codec_cap;
+	uint8_t *bis_cnt = user_data;
+	int ret;
 
+	ret = bt_bap_base_get_subgroup_bis_count(subgroup);
+	if (ret < 0) {
 		return false;
 	}
 
+	*bis_cnt += (uint8_t)ret;
+
 	return true;
 }
 
-struct store_base_info_data {
-	struct bt_bap_broadcast_sink_bis bis[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT];
-	struct bt_bap_broadcast_sink_subgroup subgroups[CONFIG_BT_BAP_BROADCAST_SNK_SUBGROUP_COUNT];
-	struct bt_audio_codec_cfg *subgroup_codec_cfg;
-	uint32_t valid_indexes_bitfield;
-	uint8_t subgroup_count;
-	uint8_t bis_count;
-};
-
-static bool merge_bis_and_subgroup_data_cb(struct bt_data *data, void *user_data)
+static int base_get_bis_count(const struct bt_bap_base *base)
 {
-	struct bt_audio_codec_cfg *codec_cfg = user_data;
+	uint8_t bis_cnt = 0U;
 	int err;
 
-	err = bt_audio_codec_cfg_set_val(codec_cfg, data->type, data->data, data->data_len);
-	if (err < 0) {
-		LOG_DBG("Failed to set type %u with len %u in codec_cfg: %d", data->type,
-			data->data_len, err);
-
-		return false;
+	err = bt_bap_base_foreach_subgroup(base, base_subgroup_bis_count_cb, &bis_cnt);
+	if (err != 0) {
+		LOG_DBG("Failed to parse subgroups: %d", err);
+		return err;
 	}
 
-	return true;
+	return bis_cnt;
 }
 
-static bool base_subgroup_bis_index_cb(const struct bt_bap_base_subgroup_bis *bis, void *user_data)
+static bool base_decode_subgroup_bis_cb(const struct bt_bap_base_subgroup_bis *bis, void *user_data)
 {
-	struct bt_bap_broadcast_sink_subgroup *sink_subgroup;
-	struct store_base_info_data *data = user_data;
-	struct bt_bap_broadcast_sink_bis *sink_bis;
+	uint32_t *base_bis_index_bitfield = user_data;
 
-	if (data->bis_count == ARRAY_SIZE(data->bis)) {
-		/* We've parsed as many subgroups as we support */
-		LOG_DBG("Could only store %u BIS", data->bis_count);
-		return false;
-	}
-
-	sink_bis = &data->bis[data->bis_count];
-	sink_subgroup = &data->subgroups[data->subgroup_count];
-
-	sink_bis->index = bis->index;
-	sink_subgroup->bis_indexes |= BT_ISO_BIS_INDEX_BIT(bis->index);
-
-#if CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE > 0
-
-	memcpy(&sink_bis->codec_cfg, data->subgroup_codec_cfg, sizeof(sink_bis->codec_cfg));
-
-	if (bis->data_len > 0) {
-		/* Merge subgroup codec configuration with the BIS configuration
-		 * As per the BAP spec, if a value exist at level 2 (subgroup) and 3 (BIS), then it
-		 * is the value at level 3 that shall be used
-		 */
-		if (sink_bis->codec_cfg.id == BT_HCI_CODING_FORMAT_LC3) {
-			int err;
-
-			memcpy(&sink_bis->codec_cfg, data->subgroup_codec_cfg,
-			       sizeof(sink_bis->codec_cfg));
-
-			err = bt_audio_data_parse(bis->data, bis->data_len,
-						  merge_bis_and_subgroup_data_cb,
-						  &sink_bis->codec_cfg);
-			if (err != 0) {
-				LOG_DBG("Could not merge BIS and subgroup config in codec_cfg: %d",
-					err);
-
-				return false;
-			}
-		} else {
-			/* If it is not LC3, then we don't know how to merge the subgroup and BIS
-			 * codecs, so we just append them
-			 */
-			if (sink_bis->codec_cfg.data_len + bis->data_len >
-			    sizeof(sink_bis->codec_cfg.data)) {
-				LOG_DBG("Could not store BIS and subgroup config in codec_cfg (%u "
-					"> %u)",
-					sink_bis->codec_cfg.data_len + bis->data_len,
-					sizeof(sink_bis->codec_cfg.data));
-
-				return false;
-			}
-
-			memcpy(&sink_bis->codec_cfg.data[sink_bis->codec_cfg.data_len], bis->data,
-			       bis->data_len);
-			sink_bis->codec_cfg.data_len += bis->data_len;
-		}
-	}
-#endif /* CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE > 0 */
-
-	data->bis_count++;
+	*base_bis_index_bitfield |= BT_ISO_BIS_INDEX_BIT(bis->index);
 
 	return true;
 }
 
-static bool base_subgroup_cb(const struct bt_bap_base_subgroup *subgroup, void *user_data)
+static bool base_decode_subgroup_cb(const struct bt_bap_base_subgroup *subgroup, void *user_data)
 {
-	struct bt_bap_broadcast_sink_subgroup *sink_subgroup;
-	struct codec_cap_lookup_id_data lookup_data = {0};
-	struct store_base_info_data *data = user_data;
+	struct bt_bap_broadcast_sink *sink = (struct bt_bap_broadcast_sink *)user_data;
+	const struct bt_audio_codec_cap *codec_cap;
 	struct bt_audio_codec_cfg codec_cfg;
+	struct bt_pac_codec codec_id;
 	int ret;
 
-	if (data->subgroup_count == ARRAY_SIZE(data->subgroups)) {
+	if (sink->subgroup_count == ARRAY_SIZE(sink->subgroups)) {
 		/* We've parsed as many subgroups as we support */
-		LOG_DBG("Could only store %u subgroups", data->subgroup_count);
+		LOG_DBG("Could only store %u subgroups", sink->subgroup_count);
 		return false;
 	}
 
-	sink_subgroup = &data->subgroups[data->subgroup_count];
+	uint32_t *subgroup_bis_indexes = &sink->subgroups[sink->subgroup_count].bis_indexes;
+
+	*subgroup_bis_indexes = 0;
 
 	ret = bt_bap_base_subgroup_codec_to_codec_cfg(subgroup, &codec_cfg);
 	if (ret < 0) {
@@ -682,151 +627,83 @@ static bool base_subgroup_cb(const struct bt_bap_base_subgroup *subgroup, void *
 	}
 
 	/* Lookup and assign path_id based on capabilities */
-	lookup_data.id = codec_cfg.id;
-
-	bt_pacs_cap_foreach(BT_AUDIO_DIR_SINK, codec_lookup_id, &lookup_data);
-	if (lookup_data.codec_cap == NULL) {
-		LOG_DBG("Codec with id %u is not supported by our capabilities", lookup_data.id);
+	codec_id.id = codec_cfg.id;
+	codec_id.cid = codec_cfg.cid;
+	codec_id.vid = codec_cfg.vid;
+
+	codec_cap = bt_pacs_get_codec_cap(BT_AUDIO_DIR_SINK, &codec_id);
+	if (codec_cap == NULL) {
+		LOG_DBG("Codec with id 0x%02x cid 0x%04x and vid 0x%04x is not supported by our "
+			"capabilities",
+			codec_id.id, codec_id.cid, codec_id.vid);
 	} else {
-		codec_cfg.path_id = lookup_data.codec_cap->path_id;
-		codec_cfg.ctlr_transcode = lookup_data.codec_cap->ctlr_transcode;
+		ret = bt_bap_base_subgroup_foreach_bis(subgroup, base_decode_subgroup_bis_cb,
+						       subgroup_bis_indexes);
 
-		data->subgroup_codec_cfg = &codec_cfg;
-
-		ret = bt_bap_base_subgroup_foreach_bis(subgroup, base_subgroup_bis_index_cb, data);
-		if (ret < 0) {
+		if (ret != 0) {
 			LOG_DBG("Could not parse BISes: %d", ret);
 			return false;
 		}
 
-		/* Add BIS to bitfield of valid BIS indexes we support */
-		data->valid_indexes_bitfield |= sink_subgroup->bis_indexes;
-		data->subgroup_count++;
-	}
-
-	return true;
-}
-
-static int store_base_info(struct bt_bap_broadcast_sink *sink, const struct bt_bap_base *base)
-{
-	/* data is static due to its size, which easily can exceed the stack size */
-	static struct store_base_info_data data;
-	uint32_t pres_delay;
-	int ret;
-
-	ret = bt_bap_base_get_pres_delay(base);
-	if (ret < 0) {
-		LOG_DBG("Could not get presentation delay: %d", ret);
-		return ret;
-	}
-
-	pres_delay = (uint32_t)ret;
-
-	memset(&data, 0, sizeof(data));
-
-	ret = bt_bap_base_foreach_subgroup(base, base_subgroup_cb, &data);
-	if (ret != 0) {
-		LOG_DBG("Failed to parse all subgroups: %d", ret);
-		return ret;
-	}
-
-	/* Ensure that we have not synced while parsing the BASE */
-	if (sink->big == NULL) {
-		sink->qos_cfg.pd = pres_delay;
-		memcpy(sink->bis, data.bis, sizeof(sink->bis));
-		memcpy(sink->subgroups, data.subgroups, sizeof(sink->subgroups));
-		sink->subgroup_count = data.subgroup_count;
-		sink->valid_indexes_bitfield = data.valid_indexes_bitfield;
-	}
-
-	return 0;
-}
-
-static bool base_subgroup_bis_count_cb(const struct bt_bap_base_subgroup *subgroup, void *user_data)
-{
-	uint8_t *bis_cnt = user_data;
-	int ret;
-
-	ret = bt_bap_base_get_subgroup_bis_count(subgroup);
-	if (ret < 0) {
-		return false;
+		sink->valid_indexes_bitfield |= *subgroup_bis_indexes;
 	}
 
-	*bis_cnt += (uint8_t)ret;
+	sink->subgroup_count++;
 
 	return true;
 }
 
-static int base_get_bis_count(const struct bt_bap_base *base)
-{
-	uint8_t bis_cnt = 0U;
-	int err;
-
-	err = bt_bap_base_foreach_subgroup(base, base_subgroup_bis_count_cb, &bis_cnt);
-	if (err != 0) {
-		LOG_DBG("Failed to parse subgroups: %d", err);
-		return err;
-	}
-
-	return bis_cnt;
-}
-
 static bool pa_decode_base(struct bt_data *data, void *user_data)
 {
 	struct bt_bap_broadcast_sink *sink = (struct bt_bap_broadcast_sink *)user_data;
 	const struct bt_bap_base *base = bt_bap_base_get_base_from_ad(data);
 	struct bt_bap_broadcast_sink_cb *listener;
 	int base_size;
-	int ret;
 
 	/* Base is NULL if the data does not contain a valid BASE */
 	if (base == NULL) {
 		return true;
 	}
 
-	if (atomic_test_bit(sink->flags, BT_BAP_BROADCAST_SINK_FLAG_BIGINFO_RECEIVED)) {
-		ret = base_get_bis_count(base);
-
-		if (ret < 0) {
-			LOG_DBG("Invalid BASE: %d", ret);
-			return false;
-		} else if (ret != sink->biginfo_num_bis) {
-			LOG_DBG("BASE contains different amount of BIS (%u) than reported by "
-				"BIGInfo (%u)",
-				ret, sink->biginfo_num_bis);
-			return false;
-		}
-	}
+	/* We provide the BASE without the service data UUID */
+	base_size = bt_bap_base_get_size(base);
+	if (base_size != sink->base_size || memcmp(base, sink->base, base_size) != 0) {
+		/* New BASE, parse */
 
-	/* Store newest BASE info until we are BIG synced */
-	if (sink->big == NULL) {
-		LOG_DBG("Updating BASE for sink %p with %d subgroups\n", sink,
-			bt_bap_base_get_subgroup_count(base));
+		if (atomic_test_bit(sink->flags, BT_BAP_BROADCAST_SINK_FLAG_BIGINFO_RECEIVED)) {
+			int ret;
 
-		ret = store_base_info(sink, base);
-		if (ret < 0) {
-			LOG_DBG("Could not store BASE information: %d", ret);
+			ret = base_get_bis_count(base);
 
-			/* If it returns -ECANCELED it means that we stopped parsing ourselves due
-			 * to lack of memory. In this case we can still provide the BASE to the
-			 * application else abort
-			 */
-			if (ret != -ECANCELED) {
+			if (ret < 0) {
+				LOG_DBG("Invalid BASE: %d", ret);
+				return false;
+			} else if (ret != sink->biginfo_num_bis) {
+				LOG_DBG("BASE contains different amount of BIS (%u) than reported "
+					"by BIGInfo (%u)",
+					ret, sink->biginfo_num_bis);
 				return false;
 			}
 		}
-	}
 
-	if (atomic_test_bit(sink->flags, BT_BAP_BROADCAST_SINK_FLAG_SRC_ID_VALID)) {
-		update_recv_state_base(sink, base);
-	}
+		/* Store newest BASE info until we are BIG synced */
+		if (sink->big == NULL) {
+			sink->qos_cfg.pd = bt_bap_base_get_pres_delay(base);
 
-	/* We provide the BASE without the service data UUID */
-	base_size = bt_bap_base_get_size(base);
-	if (base_size < 0) {
-		LOG_DBG("BASE get size failed (%d)", base_size);
+			sink->subgroup_count = 0;
+			sink->valid_indexes_bitfield = 0;
+			bt_bap_base_foreach_subgroup(base, base_decode_subgroup_cb, sink);
 
-		return false;
+			LOG_DBG("Updating BASE for sink %p with %d subgroups\n", sink,
+				sink->subgroup_count);
+
+			memcpy(sink->base, base, base_size);
+			sink->base_size = base_size;
+		}
+
+		if (atomic_test_bit(sink->flags, BT_BAP_BROADCAST_SINK_FLAG_SRC_ID_VALID)) {
+			update_recv_state_base(sink, base);
+		}
 	}
 
 	SYS_SLIST_FOR_EACH_CONTAINER(&sink_cbs, listener, _node) {
@@ -864,12 +741,12 @@ static void pa_term_cb(struct bt_le_per_adv_sync *sync,
 
 	if (sink != NULL) {
 		sink->pa_sync = NULL;
+		sink->base_size = 0U;
 	}
 }
 
 static void update_recv_state_encryption(const struct bt_bap_broadcast_sink *sink)
 {
-	struct bt_bap_scan_delegator_mod_src_param mod_src_param = { 0 };
 	const struct bt_bap_scan_delegator_recv_state *recv_state;
 	int err;
 
@@ -882,6 +759,8 @@ static void update_recv_state_encryption(const struct bt_bap_broadcast_sink *sin
 		return;
 	}
 
+	(void)memset(&mod_src_param, 0, sizeof(mod_src_param));
+
 	/* Only change the encrypt state, and leave the rest as is */
 	if (atomic_test_bit(sink->flags,
 			    BT_BAP_BROADCAST_SINK_FLAG_BIG_ENCRYPTED)) {
@@ -1105,7 +984,6 @@ static int bt_bap_broadcast_sink_setup_stream(struct bt_bap_broadcast_sink *sink
 	bt_bap_iso_bind_ep(iso, ep);
 
 	bt_bap_qos_cfg_to_iso_qos(iso->chan.qos->rx, &sink->qos_cfg);
-	bt_bap_iso_configure_data_path(ep, codec_cfg);
 
 	bt_bap_iso_unref(iso);
 
@@ -1146,23 +1024,6 @@ static void broadcast_sink_cleanup(struct bt_bap_broadcast_sink *sink)
 	(void)memset(sink, 0, sizeof(*sink)); /* also clears flags */
 }
 
-static struct bt_audio_codec_cfg *codec_cfg_from_base_by_index(struct bt_bap_broadcast_sink *sink,
-							       uint8_t index)
-{
-	for (size_t i = 0U; i < ARRAY_SIZE(sink->bis); i++) {
-		struct bt_bap_broadcast_sink_bis *bis = &sink->bis[i];
-
-		if (bis->index == index) {
-			return &bis->codec_cfg;
-		} else if (bis->index == 0) {
-			/* index 0 is invalid, so we can use that as a terminator in the array */
-			break;
-		}
-	}
-
-	return NULL;
-}
-
 int bt_bap_broadcast_sink_create(struct bt_le_per_adv_sync *pa_sync, uint32_t broadcast_id,
 				 struct bt_bap_broadcast_sink **out_sink)
 {
@@ -1220,15 +1081,166 @@ int bt_bap_broadcast_sink_create(struct bt_le_per_adv_sync *pa_sync, uint32_t br
 	return 0;
 }
 
+static uint8_t bit_count(uint32_t bitfield)
+{
+#ifdef POPCOUNT
+	return POPCOUNT(bitfield);
+#else
+	uint8_t cnt = 0U;
+
+	while (bitfield != 0U) {
+		cnt += bitfield & 1U;
+		bitfield >>= 1U;
+	}
+
+	return cnt;
+#endif
+}
+
+struct sync_base_info_data {
+	struct bt_audio_codec_cfg codec_cfgs[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT];
+	struct bt_audio_codec_cfg *subgroup_codec_cfg;
+	uint32_t sync_indexes_bitfield;
+	uint8_t subgroup_count;
+	uint8_t stream_count;
+};
+
+static bool merge_bis_and_subgroup_data_cb(struct bt_data *data, void *user_data)
+{
+	struct bt_audio_codec_cfg *codec_cfg = user_data;
+	int err;
+
+	err = bt_audio_codec_cfg_set_val(codec_cfg, data->type, data->data, data->data_len);
+	if (err < 0) {
+		LOG_DBG("Failed to set type %u with len %u in codec_cfg: %d", data->type,
+			data->data_len, err);
+
+		return false;
+	}
+
+	return true;
+}
+
+static bool sync_base_subgroup_bis_index_cb(const struct bt_bap_base_subgroup_bis *bis,
+					    void *user_data)
+{
+	struct sync_base_info_data *data = user_data;
+	struct bt_audio_codec_cfg *codec_cfg;
+
+	/* Only process selected BISes */
+	if ((data->sync_indexes_bitfield & BT_ISO_BIS_INDEX_BIT(bis->index)) == 0) {
+		return true;
+	}
+
+#if CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE > 0
+
+	codec_cfg = &data->codec_cfgs[data->stream_count];
+
+	memcpy(codec_cfg, data->subgroup_codec_cfg, sizeof(struct bt_audio_codec_cfg));
+
+	if (bis->data_len > 0) {
+		/* Merge subgroup codec configuration with the BIS configuration
+		 * As per the BAP spec, if a value exist at level 2 (subgroup) and 3 (BIS), then it
+		 * is the value at level 3 that shall be used
+		 */
+		if (codec_cfg->id == BT_HCI_CODING_FORMAT_LC3) {
+			int err;
+
+			memcpy(codec_cfg, data->subgroup_codec_cfg,
+			       sizeof(struct bt_audio_codec_cfg));
+
+			err = bt_audio_data_parse(bis->data, bis->data_len,
+						  merge_bis_and_subgroup_data_cb, codec_cfg);
+			if (err != 0) {
+				LOG_DBG("Could not merge BIS and subgroup config in codec_cfg: %d",
+					err);
+
+				return false;
+			}
+		} else {
+			/* If it is not LC3, then we don't know how to merge the subgroup and BIS
+			 * codecs, so we just append them
+			 */
+			if (codec_cfg->data_len + bis->data_len > sizeof(codec_cfg->data)) {
+				LOG_DBG("Could not store BIS and subgroup config in codec_cfg (%u "
+					"> %u)",
+					codec_cfg->data_len + bis->data_len,
+					sizeof(codec_cfg->data));
+
+				return false;
+			}
+
+			memcpy(&codec_cfg->data[codec_cfg->data_len], bis->data, bis->data_len);
+			codec_cfg->data_len += bis->data_len;
+		}
+	}
+#endif /* CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE > 0 */
+
+	data->stream_count++;
+
+	return true;
+}
+
+static bool sync_base_subgroup_cb(const struct bt_bap_base_subgroup *subgroup, void *user_data)
+{
+	struct sync_base_info_data *data = user_data;
+	const struct bt_audio_codec_cap *codec_cap;
+	struct bt_audio_codec_cfg codec_cfg;
+	struct bt_pac_codec codec_id;
+	int ret;
+
+	if (data->subgroup_count == CONFIG_BT_BAP_BROADCAST_SNK_SUBGROUP_COUNT) {
+		/* We've parsed as many subgroups as we support */
+		LOG_DBG("Could only store %u subgroups", data->subgroup_count);
+		return false;
+	}
+
+	ret = bt_bap_base_subgroup_codec_to_codec_cfg(subgroup, &codec_cfg);
+	if (ret < 0) {
+		LOG_DBG("Could not store codec_cfg: %d", ret);
+		return false;
+	}
+
+	/* Lookup and assign path_id based on capabilities */
+	codec_id.id = codec_cfg.id;
+	codec_id.cid = codec_cfg.cid;
+	codec_id.vid = codec_cfg.vid;
+
+	codec_cap = bt_pacs_get_codec_cap(BT_AUDIO_DIR_SINK, &codec_id);
+	if (codec_cap == NULL) {
+		LOG_DBG("Codec with id 0x%02x cid 0x%04x and vid 0x%04x is not supported by our "
+			"capabilities",
+			codec_id.id, codec_id.cid, codec_id.vid);
+	} else {
+		codec_cfg.path_id = codec_cap->path_id;
+		codec_cfg.ctlr_transcode = codec_cap->ctlr_transcode;
+
+		data->subgroup_codec_cfg = &codec_cfg;
+
+		ret = bt_bap_base_subgroup_foreach_bis(subgroup, sync_base_subgroup_bis_index_cb,
+						       data);
+		if (ret < 0) {
+			LOG_DBG("Could not parse BISes: %d", ret);
+			return false;
+		}
+
+		data->subgroup_count++;
+	}
+
+	return true;
+}
+
 int bt_bap_broadcast_sink_sync(struct bt_bap_broadcast_sink *sink, uint32_t indexes_bitfield,
 			       struct bt_bap_stream *streams[],
 			       const uint8_t broadcast_code[BT_ISO_BROADCAST_CODE_SIZE])
 {
+	static struct sync_base_info_data data;
 	struct bt_iso_big_sync_param param;
-	struct bt_audio_codec_cfg *codec_cfgs[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT] = {NULL};
 	struct bt_iso_chan *bis_channels[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT];
+	uint8_t bis_count;
 	uint8_t stream_count;
 	int err;
+	int ret;
 
 	CHECKIF(sink == NULL) {
 		LOG_DBG("sink is NULL");
@@ -1268,32 +1280,34 @@ int bt_bap_broadcast_sink_sync(struct bt_bap_broadcast_sink *sink, uint32_t inde
 		return -EINVAL;
 	}
 
-	/* Validate that number of bits set is less than number of streams */
+	/* Validate that number of bits set is within supported range */
+	bis_count = bit_count(indexes_bitfield);
+	if (bis_count > CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT) {
+		LOG_DBG("Cannot sync to more than %d streams (%u was requested)",
+			CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT, bis_count);
+		return -EINVAL;
+	}
+
+	/* Validate that the bits set are present in BASE */
 	if ((indexes_bitfield & sink->valid_indexes_bitfield) != indexes_bitfield) {
-		LOG_DBG("Request BIS indexes 0x%08X contains bits not support by the Broadcast "
-			"Sink 0x%08X",
+		LOG_DBG("Request BIS indexes (0x%08X) contains bits not present in BASE (0x%08X)",
 			indexes_bitfield, sink->valid_indexes_bitfield);
 		return -EINVAL;
 	}
 
-	stream_count = 0;
-	for (int i = 1; i < BT_ISO_MAX_GROUP_ISO_COUNT; i++) {
-		if ((indexes_bitfield & BT_ISO_BIS_INDEX_BIT(i)) != 0) {
-			struct bt_audio_codec_cfg *codec_cfg =
-				codec_cfg_from_base_by_index(sink, i);
-
-			__ASSERT(codec_cfg != NULL, "Index %d not found in sink", i);
+	memset(&data, 0, sizeof(data));
 
-			codec_cfgs[stream_count++] = codec_cfg;
+	data.sync_indexes_bitfield = indexes_bitfield;
 
-			if (stream_count > CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT) {
-				LOG_DBG("Cannot sync to more than %d streams (%u was requested)",
-					CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT, stream_count);
-				return -EINVAL;
-			}
-		}
+	ret = bt_bap_base_foreach_subgroup((const struct bt_bap_base *)sink->base,
+					   sync_base_subgroup_cb, &data);
+	if (ret != 0) {
+		LOG_DBG("Failed to parse all subgroups: %d", ret);
+		return ret;
 	}
 
+	stream_count = data.stream_count;
+
 	for (size_t i = 0; i < stream_count; i++) {
 		CHECKIF(streams[i] == NULL) {
 			LOG_DBG("streams[%zu] is NULL", i);
@@ -1307,7 +1321,7 @@ int bt_bap_broadcast_sink_sync(struct bt_bap_broadcast_sink *sink, uint32_t inde
 		struct bt_audio_codec_cfg *codec_cfg;
 
 		stream = streams[i];
-		codec_cfg = codec_cfgs[i];
+		codec_cfg = &data.codec_cfgs[i];
 
 		err = bt_bap_broadcast_sink_setup_stream(sink, stream, codec_cfg);
 		if (err != 0) {
diff --git a/subsys/bluetooth/audio/bap_broadcast_source.c b/subsys/bluetooth/audio/bap_broadcast_source.c
index 132dca5580a..748d9d68db9 100644
--- a/subsys/bluetooth/audio/bap_broadcast_source.c
+++ b/subsys/bluetooth/audio/bap_broadcast_source.c
@@ -1,7 +1,7 @@
 /*  Bluetooth Audio Broadcast Source */
 
 /*
- * Copyright (c) 2021-2024 Nordic Semiconductor ASA
+ * Copyright (c) 2021-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -191,6 +191,9 @@ static void broadcast_source_iso_connected(struct bt_iso_chan *chan)
 	stream->_prev_seq_num = 0U;
 #endif /* CONFIG_BT_BAP_DEBUG_STREAM_SEQ_NUM */
 
+	/* Setup the ISO data path */
+	bt_bap_setup_iso_data_path(stream);
+
 	ops = stream->ops;
 	if (ops != NULL && ops->connected != NULL) {
 		ops->connected(stream);
@@ -317,7 +320,7 @@ static int broadcast_source_setup_stream(uint8_t index, struct bt_bap_stream *st
 	bt_bap_iso_bind_ep(iso, ep);
 
 	bt_bap_qos_cfg_to_iso_qos(iso->chan.qos->tx, qos);
-	bt_bap_iso_configure_data_path(ep, codec_cfg);
+
 #if defined(CONFIG_BT_ISO_TEST_PARAMS)
 	iso->chan.qos->num_subevents = qos->num_subevents;
 #endif /* CONFIG_BT_ISO_TEST_PARAMS */
@@ -967,7 +970,6 @@ int bt_bap_broadcast_source_reconfig(struct bt_bap_broadcast_source *source,
 		 */
 		SYS_SLIST_FOR_EACH_CONTAINER(&subgroup->streams, stream, _node) {
 			bt_bap_stream_attach(NULL, stream, stream->ep, codec_cfg);
-			bt_bap_iso_configure_data_path(stream->ep, codec_cfg);
 		}
 	}
 
diff --git a/subsys/bluetooth/audio/bap_endpoint.h b/subsys/bluetooth/audio/bap_endpoint.h
index 08d385aefac..4f1a5fe7a0b 100644
--- a/subsys/bluetooth/audio/bap_endpoint.h
+++ b/subsys/bluetooth/audio/bap_endpoint.h
@@ -9,6 +9,7 @@
 
 #include <stdbool.h>
 #include <stdint.h>
+#include <stddef.h>
 
 #include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/audio/audio.h>
@@ -180,6 +181,8 @@ struct bt_bap_broadcast_sink {
 	struct bt_bap_qos_cfg qos_cfg;
 	struct bt_le_per_adv_sync *pa_sync;
 	struct bt_iso_big *big;
+	uint8_t base_size;
+	uint8_t base[BT_BASE_MAX_SIZE];
 	struct bt_bap_broadcast_sink_bis bis[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT];
 	struct bt_bap_broadcast_sink_subgroup subgroups[CONFIG_BT_BAP_BROADCAST_SNK_SUBGROUP_COUNT];
 	const struct bt_bap_scan_delegator_recv_state *recv_state;
diff --git a/subsys/bluetooth/audio/bap_iso.c b/subsys/bluetooth/audio/bap_iso.c
index e58e139a771..a661e4c357b 100644
--- a/subsys/bluetooth/audio/bap_iso.c
+++ b/subsys/bluetooth/audio/bap_iso.c
@@ -170,43 +170,68 @@ static struct bt_bap_iso_dir *bap_iso_get_iso_dir(bool unicast_client, struct bt
 	}
 }
 
-void bt_bap_iso_configure_data_path(struct bt_bap_ep *ep, struct bt_audio_codec_cfg *codec_cfg)
+void bt_bap_setup_iso_data_path(struct bt_bap_stream *stream)
 {
+	struct bt_audio_codec_cfg *codec_cfg = stream->codec_cfg;
+	struct bt_bap_ep *ep = stream->ep;
 	struct bt_bap_iso *bap_iso = ep->iso;
-	struct bt_iso_chan_qos *qos = bap_iso->chan.qos;
 	const bool is_unicast_client =
 		IS_ENABLED(CONFIG_BT_BAP_UNICAST_CLIENT) && bt_bap_ep_is_unicast_client(ep);
 	struct bt_bap_iso_dir *iso_dir = bap_iso_get_iso_dir(is_unicast_client, bap_iso, ep->dir);
-	struct bt_iso_chan_path *path = &iso_dir->path;
+	struct bt_iso_chan_path path = {0};
+	uint8_t dir;
+	int err;
 
-	/* Setup the data path objects */
 	if (iso_dir == &bap_iso->rx) {
-		qos->rx->path = path;
+		dir = BT_HCI_DATAPATH_DIR_CTLR_TO_HOST;
 	} else {
-		qos->tx->path = path;
+		dir = BT_HCI_DATAPATH_DIR_HOST_TO_CTLR;
 	}
 
+	path.pid = codec_cfg->path_id;
+
 	/* Configure the data path to either use the controller for transcoding, or set the path to
 	 * be transparent to indicate that the transcoding happens somewhere else
 	 */
-	path->pid = codec_cfg->path_id;
-
 	if (codec_cfg->ctlr_transcode) {
-		path->format = codec_cfg->id;
-		path->cid = codec_cfg->cid;
-		path->vid = codec_cfg->vid;
-		path->delay = 0;
-		path->cc_len = codec_cfg->data_len;
-		path->cc = codec_cfg->data;
+		path.format = codec_cfg->id;
+		path.cid = codec_cfg->cid;
+		path.vid = codec_cfg->vid;
+		path.cc_len = codec_cfg->data_len;
+		path.cc = codec_cfg->data;
+	} else {
+		path.format = BT_HCI_CODING_FORMAT_TRANSPARENT;
+	}
+
+	err = bt_iso_setup_data_path(&bap_iso->chan, dir, &path);
+	if (err != 0) {
+		LOG_ERR("Failed to set ISO data path for ep %p and codec_cfg %p: %d", ep, codec_cfg,
+			err);
+	}
+}
+
+void bt_bap_remove_iso_data_path(struct bt_bap_stream *stream)
+{
+	struct bt_bap_ep *ep = stream->ep;
+	struct bt_bap_iso *bap_iso = ep->iso;
+	const bool is_unicast_client =
+		IS_ENABLED(CONFIG_BT_BAP_UNICAST_CLIENT) && bt_bap_ep_is_unicast_client(ep);
+	struct bt_bap_iso_dir *iso_dir = bap_iso_get_iso_dir(is_unicast_client, bap_iso, ep->dir);
+	uint8_t dir;
+	int err;
+
+	if (iso_dir == &bap_iso->rx) {
+		dir = BT_HCI_DATAPATH_DIR_CTLR_TO_HOST;
 	} else {
-		path->format = BT_HCI_CODING_FORMAT_TRANSPARENT;
-		path->cid = 0;
-		path->vid = 0;
-		path->delay = 0;
-		path->cc_len = 0;
-		path->cc = NULL;
+		dir = BT_HCI_DATAPATH_DIR_HOST_TO_CTLR;
+	}
+
+	err = bt_iso_remove_data_path(&bap_iso->chan, dir);
+	if (err != 0) {
+		LOG_ERR("Failed to remove ISO data path for ep %p: %d", ep, err);
 	}
 }
+
 static bool is_unicast_client_ep(struct bt_bap_ep *ep)
 {
 	return IS_ENABLED(CONFIG_BT_BAP_UNICAST_CLIENT) && bt_bap_ep_is_unicast_client(ep);
diff --git a/subsys/bluetooth/audio/bap_iso.h b/subsys/bluetooth/audio/bap_iso.h
index f1ebd0eed9b..18a65c1ac7a 100644
--- a/subsys/bluetooth/audio/bap_iso.h
+++ b/subsys/bluetooth/audio/bap_iso.h
@@ -2,7 +2,7 @@
  * @brief Internal APIs for BAP ISO handling
  *
  * Copyright (c) 2022 Codecoup
- * Copyright (c) 2023 Nordic Semiconductor ASA
+ * Copyright (c) 2023-2024 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -19,7 +19,6 @@
 struct bt_bap_iso_dir {
 	struct bt_bap_stream *stream;
 	struct bt_bap_ep *ep;
-	struct bt_iso_chan_path path;
 	struct bt_iso_chan_io_qos qos;
 	uint8_t cc[CONFIG_BT_AUDIO_CODEC_CFG_MAX_DATA_SIZE];
 };
@@ -46,7 +45,8 @@ void bt_bap_iso_foreach(bt_bap_iso_func_t func, void *user_data);
 struct bt_bap_iso *bt_bap_iso_find(bt_bap_iso_func_t func, void *user_data);
 void bt_bap_iso_init(struct bt_bap_iso *iso, struct bt_iso_chan_ops *ops);
 void bt_bap_iso_bind_ep(struct bt_bap_iso *iso, struct bt_bap_ep *ep);
-void bt_bap_iso_configure_data_path(struct bt_bap_ep *ep, struct bt_audio_codec_cfg *codec_cfg);
+void bt_bap_setup_iso_data_path(struct bt_bap_stream *stream);
+void bt_bap_remove_iso_data_path(struct bt_bap_stream *stream);
 void bt_bap_iso_unbind_ep(struct bt_bap_iso *iso, struct bt_bap_ep *ep);
 struct bt_bap_ep *bt_bap_iso_get_ep(bool unicast_client, struct bt_bap_iso *iso,
 				    enum bt_audio_dir dir);
diff --git a/subsys/bluetooth/audio/bap_scan_delegator.c b/subsys/bluetooth/audio/bap_scan_delegator.c
index 8fdf83557d7..dc38b3b3baf 100644
--- a/subsys/bluetooth/audio/bap_scan_delegator.c
+++ b/subsys/bluetooth/audio/bap_scan_delegator.c
@@ -51,14 +51,10 @@ LOG_MODULE_REGISTER(bt_bap_scan_delegator, CONFIG_BT_BAP_SCAN_DELEGATOR_LOG_LEVE
 #define PAST_TIMEOUT              K_SECONDS(10)
 
 #define SCAN_DELEGATOR_BUF_SEM_TIMEOUT K_MSEC(CONFIG_BT_BAP_SCAN_DELEGATOR_BUF_TIMEOUT)
-static K_SEM_DEFINE(read_buf_sem, 1, 1);
 NET_BUF_SIMPLE_DEFINE_STATIC(read_buf, BT_ATT_MAX_ATTRIBUTE_LEN);
 
-enum bass_recv_state_internal_flag {
-	/* TODO: Replace this flag with a k_work_delayable */
-	BASS_RECV_STATE_INTERNAL_FLAG_NOTIFY_PEND,
-
-	BASS_RECV_STATE_INTERNAL_FLAG_NUM,
+struct bass_recv_state_flags {
+	bool updated: 1;
 };
 
 /* TODO: Merge bass_recv_state_internal_t and bt_bap_scan_delegator_recv_state */
@@ -73,7 +69,11 @@ struct bass_recv_state_internal {
 	/** Requested BIS sync bitfield for each subgroup */
 	uint32_t requested_bis_sync[CONFIG_BT_BAP_BASS_MAX_SUBGROUPS];
 
-	ATOMIC_DEFINE(flags, BASS_RECV_STATE_INTERNAL_FLAG_NUM);
+	/* Mutex (reentrant Locking) ensure multiple threads to safely access receive state data */
+	struct k_mutex mutex;
+	struct bass_recv_state_flags flags[CONFIG_BT_MAX_CONN];
+
+	struct k_work_delayable notify_work;
 };
 
 struct bt_bap_scan_delegator_inst {
@@ -95,6 +95,35 @@ static ATOMIC_DEFINE(scan_delegator_flags, SCAN_DELEGATOR_FLAG_NUM);
 static struct bt_bap_scan_delegator_inst scan_delegator;
 static struct bt_bap_scan_delegator_cb *scan_delegator_cbs;
 
+static void set_receive_state_changed_cb(struct bt_conn *conn, void *data)
+{
+	struct bass_recv_state_internal *internal_state = data;
+	struct bass_recv_state_flags *flags = &internal_state->flags[bt_conn_index(conn)];
+	struct bt_conn_info conn_info;
+	int err;
+
+	err = bt_conn_get_info(conn, &conn_info);
+	__ASSERT_NO_MSG(err == 0);
+
+	if (conn_info.state != BT_CONN_STATE_CONNECTED ||
+	    !bt_gatt_is_subscribed(conn, internal_state->attr, BT_GATT_CCC_NOTIFY)) {
+		return;
+	}
+
+	flags->updated = true;
+
+	/* We may schedule the same work multiple times, but that is OK as scheduling the same work
+	 * multiple times is a no-op
+	 */
+	err = k_work_schedule(&internal_state->notify_work, K_NO_WAIT);
+	__ASSERT(err >= 0, "Failed to schedule work: %d", err);
+}
+
+static void set_receive_state_changed(struct bass_recv_state_internal *internal_state)
+{
+	bt_conn_foreach(BT_CONN_TYPE_LE, set_receive_state_changed_cb, (void *)internal_state);
+}
+
 /**
  * @brief Returns whether a value's bits is a subset of another value's bits
  *
@@ -151,32 +180,44 @@ static void bt_debug_dump_recv_state(const struct bass_recv_state_internal *recv
 	}
 }
 
-static void bass_notify_receive_state(struct bt_conn *conn,
-				      const struct bass_recv_state_internal *internal_state)
+static void receive_state_notify_cb(struct bt_conn *conn, void *data)
 {
-	const uint8_t att_ntf_header_size = 3; /* opcode (1) + handle (2) */
-	uint16_t max_ntf_size;
-	uint16_t ntf_size;
+	struct bass_recv_state_internal *internal_state = data;
+	struct bass_recv_state_flags *flags = &internal_state->flags[bt_conn_index(conn)];
+	struct bt_conn_info conn_info;
 	int err;
 
-	if (conn != NULL) {
-		max_ntf_size = bt_gatt_get_mtu(conn) - att_ntf_header_size;
-	} else {
-		max_ntf_size = MIN(BT_L2CAP_RX_MTU, BT_L2CAP_TX_MTU) - att_ntf_header_size;
-	}
+	err = bt_conn_get_info(conn, &conn_info);
+	__ASSERT_NO_MSG(err == 0);
 
-	ntf_size = MIN(max_ntf_size, read_buf.len);
-	if (ntf_size < read_buf.len) {
-		LOG_DBG("Sending truncated notification (%u/%u)", ntf_size, read_buf.len);
+	if (conn_info.state != BT_CONN_STATE_CONNECTED ||
+	    !bt_gatt_is_subscribed(conn, internal_state->attr, BT_GATT_CCC_NOTIFY)) {
+		return;
 	}
 
-	LOG_DBG("Sending bytes %d", ntf_size);
-	err = bt_gatt_notify_uuid(NULL, BT_UUID_BASS_RECV_STATE,
-				  internal_state->attr, read_buf.data,
-				  ntf_size);
+	if (flags->updated) {
+		uint16_t max_ntf_size;
+		uint16_t ntf_size;
+
+		max_ntf_size = bt_audio_get_max_ntf_size(conn);
+
+		ntf_size = MIN(max_ntf_size, read_buf.len);
+		if (ntf_size < read_buf.len) {
+			LOG_DBG("Sending truncated notification (%u/%u)", ntf_size, read_buf.len);
+		}
+
+		LOG_DBG("Sending bytes %u for %p", ntf_size, (void *)conn);
+		err = bt_gatt_notify_uuid(conn, BT_UUID_BASS_RECV_STATE, internal_state->attr,
+					  read_buf.data, ntf_size);
+		if (err == 0) {
+			flags->updated = false;
+			return;
+		}
 
-	if (err != 0 && err != -ENOTCONN) {
 		LOG_DBG("Could not notify receive state: %d", err);
+		err = k_work_reschedule(&internal_state->notify_work,
+					K_USEC(BT_CONN_INTERVAL_TO_US(conn_info.le.interval)));
+		__ASSERT(err >= 0, "Failed to reschedule work: %d", err);
 	}
 }
 
@@ -218,33 +259,46 @@ static void net_buf_put_recv_state(const struct bass_recv_state_internal *recv_s
 }
 
 static void receive_state_updated(struct bt_conn *conn,
-				  const struct bass_recv_state_internal *internal_state)
+				  struct bass_recv_state_internal *internal_state)
 {
-	int err;
+	if (IS_ENABLED(CONFIG_BT_BAP_SCAN_DELEGATOR_LOG_LEVEL_DBG)) {
+		int err;
 
-	/* If something is holding the NOTIFY_PEND flag we should not notify now */
-	if (atomic_test_bit(internal_state->flags,
-			    BASS_RECV_STATE_INTERNAL_FLAG_NOTIFY_PEND)) {
-		return;
+		err = k_mutex_lock(&internal_state->mutex, SCAN_DELEGATOR_BUF_SEM_TIMEOUT);
+		if (err == 0) {
+			bt_debug_dump_recv_state(internal_state);
+			err = k_mutex_unlock(&internal_state->mutex);
+			__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
+		} else {
+			LOG_DBG("Failed to lock mutex: %d", err);
+		}
 	}
 
-	err = k_sem_take(&read_buf_sem, SCAN_DELEGATOR_BUF_SEM_TIMEOUT);
-	if (err != 0) {
-		LOG_DBG("Failed to take read_buf_sem: %d", err);
+	if (scan_delegator_cbs != NULL && scan_delegator_cbs->recv_state_updated != NULL) {
+		scan_delegator_cbs->recv_state_updated(conn, &internal_state->state);
+	}
+}
 
+static void notify_work_handler(struct k_work *work)
+{
+	struct bass_recv_state_internal *internal_state = CONTAINER_OF(
+		k_work_delayable_from_work(work), struct bass_recv_state_internal, notify_work);
+	int err;
+
+	err = k_mutex_lock(&internal_state->mutex, SCAN_DELEGATOR_BUF_SEM_TIMEOUT);
+	if (err != 0) {
+		LOG_DBG("Failed to take mutex: %d", err);
+		err = k_work_reschedule(&internal_state->notify_work, K_NO_WAIT);
+		__ASSERT(err >= 0, "Failed to reschedule work: %d", err);
 		return;
 	}
 
-	bt_debug_dump_recv_state(internal_state);
 	net_buf_put_recv_state(internal_state);
-	bass_notify_receive_state(conn, internal_state);
-	if (scan_delegator_cbs != NULL &&
-	    scan_delegator_cbs->recv_state_updated != NULL) {
-		scan_delegator_cbs->recv_state_updated(conn,
-						       &internal_state->state);
-	}
+	bt_conn_foreach(BT_CONN_TYPE_LE, receive_state_notify_cb, internal_state);
 
-	k_sem_give(&read_buf_sem);
+	err = k_mutex_unlock(&internal_state->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
 }
 
 static void bis_sync_request_updated(struct bt_conn *conn,
@@ -264,7 +318,7 @@ static void scan_delegator_security_changed(struct bt_conn *conn,
 					    enum bt_security_err err)
 {
 
-	if (err != 0 || level < BT_SECURITY_L2 || !bt_addr_le_is_bonded(conn->id, &conn->le.dst)) {
+	if (err != 0 || level < BT_SECURITY_L2 || !bt_le_bond_exists(conn->id, &conn->le.dst)) {
 		return;
 	}
 
@@ -277,17 +331,7 @@ static void scan_delegator_security_changed(struct bt_conn *conn,
 			continue;
 		}
 
-		err = k_sem_take(&read_buf_sem, SCAN_DELEGATOR_BUF_SEM_TIMEOUT);
-		if (err != 0) {
-			LOG_DBG("Failed to take read_buf_sem: %d", err);
-
-			return;
-		}
-
-		net_buf_put_recv_state(internal_state);
-		bass_notify_receive_state(conn, internal_state);
-
-		k_sem_give(&read_buf_sem);
+		set_receive_state_changed_cb(conn, (void *)internal_state);
 	}
 }
 
@@ -368,6 +412,8 @@ static void pa_synced(struct bt_le_per_adv_sync *sync,
 		      struct bt_le_per_adv_sync_synced_info *info)
 {
 	struct bass_recv_state_internal *internal_state;
+	bool state_changed = false;
+	int err;
 
 	LOG_DBG("Synced%s", info->conn ? " via PAST" : "");
 
@@ -377,10 +423,25 @@ static void pa_synced(struct bt_le_per_adv_sync *sync,
 		return;
 	}
 
+	err = k_mutex_lock(&internal_state->mutex, SCAN_DELEGATOR_BUF_SEM_TIMEOUT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex: %d", err);
+		return;
+	}
+
 	internal_state->pa_sync = sync;
 
 	if (internal_state->state.pa_sync_state != BT_BAP_PA_STATE_SYNCED) {
 		internal_state->state.pa_sync_state = BT_BAP_PA_STATE_SYNCED;
+		set_receive_state_changed(internal_state);
+		state_changed = true;
+	}
+
+	err = k_mutex_unlock(&internal_state->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
+	if (state_changed) {
+		/* app callback */
 		receive_state_updated(info->conn, internal_state);
 	}
 }
@@ -389,6 +450,8 @@ static void pa_terminated(struct bt_le_per_adv_sync *sync,
 			  const struct bt_le_per_adv_sync_term_info *info)
 {
 	struct bass_recv_state_internal *internal_state = bass_lookup_pa_sync(sync);
+	bool state_changed = false;
+	int err;
 
 	LOG_DBG("Terminated");
 	if (internal_state == NULL) {
@@ -396,10 +459,25 @@ static void pa_terminated(struct bt_le_per_adv_sync *sync,
 		return;
 	}
 
+	err = k_mutex_lock(&internal_state->mutex, SCAN_DELEGATOR_BUF_SEM_TIMEOUT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex: %d", err);
+		return;
+	}
+
 	internal_state->pa_sync = NULL;
 
 	if (internal_state->state.pa_sync_state != BT_BAP_PA_STATE_NOT_SYNCED) {
 		internal_state->state.pa_sync_state = BT_BAP_PA_STATE_NOT_SYNCED;
+		set_receive_state_changed(internal_state);
+		state_changed = true;
+	}
+
+	err = k_mutex_unlock(&internal_state->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
+	if (state_changed) {
+		/* app callback */
 		receive_state_updated(NULL, internal_state);
 	}
 }
@@ -412,14 +490,32 @@ static struct bt_le_per_adv_sync_cb pa_sync_cb =  {
 static bool supports_past(struct bt_conn *conn, uint8_t pa_sync_val)
 {
 	if (IS_ENABLED(CONFIG_BT_PER_ADV_SYNC_TRANSFER_RECEIVER)) {
+		struct bt_le_local_features local_features;
+		struct bt_conn_remote_info remote_info;
+		int err;
+
+		err = bt_le_get_local_features(&local_features);
+		if (err != 0) {
+			LOG_DBG("Failed to get local features: %d", err);
+			return false;
+		}
+
+		err = bt_conn_get_remote_info(conn, &remote_info);
+		if (err != 0) {
+			LOG_DBG("Failed to get remote info: %d", err);
+			return false;
+		}
+
 		LOG_DBG("%p remote %s PAST, local %s PAST (req %u)", (void *)conn,
-			BT_FEAT_LE_PAST_SEND(conn->le.features) ? "supports" : "does not support",
-			BT_FEAT_LE_PAST_RECV(bt_dev.le.features) ? "supports" : "does not support",
+			BT_FEAT_LE_PAST_SEND(remote_info.le.features) ? "supports"
+								      : "does not support",
+			BT_FEAT_LE_PAST_RECV(local_features.features) ? "supports"
+								      : "does not support",
 			pa_sync_val);
 
 		return pa_sync_val == BT_BAP_BASS_PA_REQ_SYNC_PAST &&
-		       BT_FEAT_LE_PAST_SEND(conn->le.features) &&
-		       BT_FEAT_LE_PAST_RECV(bt_dev.le.features);
+		       BT_FEAT_LE_PAST_SEND(remote_info.le.features) &&
+		       BT_FEAT_LE_PAST_RECV(local_features.features);
 	} else {
 		return false;
 	}
@@ -483,7 +579,7 @@ static bool bass_source_is_duplicate(uint32_t broadcast_id, uint8_t adv_sid, uin
 	return false;
 }
 
-static int scan_delegator_add_source(struct bt_conn *conn,
+static int scan_delegator_add_src(struct bt_conn *conn,
 				     struct net_buf_simple *buf)
 {
 	struct bass_recv_state_internal *internal_state = NULL;
@@ -494,6 +590,10 @@ static int scan_delegator_add_source(struct bt_conn *conn,
 	uint32_t aggregated_bis_syncs = 0;
 	uint32_t broadcast_id;
 	bool bis_sync_requested;
+	uint16_t total_len;
+	struct bt_bap_bass_cp_add_src *add_src;
+	int ret = BT_GATT_ERR(BT_ATT_ERR_SUCCESS);
+	int err;
 
 	/* subtract 1 as the opcode has already been pulled */
 	if (buf->len < sizeof(struct bt_bap_bass_cp_add_src) - 1) {
@@ -501,6 +601,34 @@ static int scan_delegator_add_source(struct bt_conn *conn,
 		return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
 	}
 
+	add_src = (void *)(buf->data - 1);
+	total_len = sizeof(struct bt_bap_bass_cp_add_src) - 1;
+	for (int i = 0; i < add_src->num_subgroups; i++) {
+		struct bt_bap_bass_cp_subgroup *subgroup;
+		uint16_t index = total_len;
+
+		total_len += sizeof(struct bt_bap_bass_cp_subgroup);
+		if (total_len > buf->len) {
+			LOG_DBG("Invalid length %u", buf->len);
+
+			return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
+		}
+
+		subgroup = (void *)&buf->data[index];
+		total_len += subgroup->metadata_len;
+		if (total_len > buf->len) {
+			LOG_DBG("Invalid length %u", buf->len);
+
+			return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
+		}
+	}
+
+	if (total_len != buf->len) {
+		LOG_DBG("Invalid length %u", buf->len);
+
+		return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
+	}
+
 	internal_state = get_free_recv_state();
 	if (internal_state == NULL) {
 		LOG_DBG("Could not get free receive state");
@@ -508,13 +636,21 @@ static int scan_delegator_add_source(struct bt_conn *conn,
 		return BT_GATT_ERR(BT_ATT_ERR_INSUFFICIENT_RESOURCES);
 	}
 
+	err = k_mutex_lock(&internal_state->mutex, SCAN_DELEGATOR_BUF_SEM_TIMEOUT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex: %d", err);
+
+		return BT_GATT_ERR(BT_ATT_ERR_INSUFFICIENT_RESOURCES);
+	}
+
 	state = &internal_state->state;
 
 	state->src_id = next_src_id();
 	state->addr.type = net_buf_simple_pull_u8(buf);
 	if (state->addr.type > BT_ADDR_LE_RANDOM) {
 		LOG_DBG("Invalid address type %u", state->addr.type);
-		return BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
+		ret = BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
+		goto unlock_return;
 	}
 
 	addr = net_buf_simple_pull_mem(buf, sizeof(*addr));
@@ -523,7 +659,8 @@ static int scan_delegator_add_source(struct bt_conn *conn,
 	state->adv_sid = net_buf_simple_pull_u8(buf);
 	if (state->adv_sid > BT_GAP_SID_MAX) {
 		LOG_DBG("Invalid adv SID %u", state->adv_sid);
-		return BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
+		ret = BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
+		goto unlock_return;
 	}
 
 	broadcast_id = net_buf_simple_pull_le24(buf);
@@ -532,8 +669,8 @@ static int scan_delegator_add_source(struct bt_conn *conn,
 		LOG_DBG("Adding broadcast_id=0x%06X, adv_sid=0x%02X, and addr.type=0x%02X would "
 			"result in duplication", state->broadcast_id, state->adv_sid,
 			state->addr.type);
-
-		return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
+		ret = BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
+		goto unlock_return;
 	}
 
 	state->broadcast_id = broadcast_id;
@@ -541,7 +678,8 @@ static int scan_delegator_add_source(struct bt_conn *conn,
 	pa_sync = net_buf_simple_pull_u8(buf);
 	if (pa_sync > BT_BAP_BASS_PA_REQ_SYNC) {
 		LOG_DBG("Invalid PA sync value %u", pa_sync);
-		return BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
+		ret = BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
+		goto unlock_return;
 	}
 
 	pa_interval = net_buf_simple_pull_le16(buf);
@@ -550,7 +688,8 @@ static int scan_delegator_add_source(struct bt_conn *conn,
 	if (state->num_subgroups > CONFIG_BT_BAP_BASS_MAX_SUBGROUPS) {
 		LOG_WRN("Too many subgroups %u/%u", state->num_subgroups,
 			CONFIG_BT_BAP_BASS_MAX_SUBGROUPS);
-		return BT_GATT_ERR(BT_ATT_ERR_INSUFFICIENT_RESOURCES);
+		ret = BT_GATT_ERR(BT_ATT_ERR_INSUFFICIENT_RESOURCES);
+		goto unlock_return;
 	}
 
 	bis_sync_requested = false;
@@ -558,17 +697,13 @@ static int scan_delegator_add_source(struct bt_conn *conn,
 		struct bt_bap_bass_subgroup *subgroup = &state->subgroups[i];
 		uint8_t *metadata;
 
-		if (buf->len < (sizeof(subgroup->bis_sync) + sizeof(subgroup->metadata_len))) {
-			LOG_DBG("Invalid length %u", buf->size);
-			return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
-		}
-
 		internal_state->requested_bis_sync[i] = net_buf_simple_pull_le32(buf);
 
 		if (internal_state->requested_bis_sync[i] &&
 		    pa_sync == BT_BAP_BASS_PA_REQ_NO_SYNC) {
 			LOG_DBG("Cannot sync to BIS without PA");
-			return BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
+			ret = BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
+			goto unlock_return;
 		}
 
 		if (internal_state->requested_bis_sync[i] != 0U) {
@@ -581,33 +716,26 @@ static int scan_delegator_add_source(struct bt_conn *conn,
 			LOG_DBG("Duplicate BIS index [%d]%x (aggregated %x)",
 				i, internal_state->requested_bis_sync[i],
 				aggregated_bis_syncs);
-
-			return BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
+			ret = BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
+			goto unlock_return;
 		}
 
 		if (!valid_bis_syncs(internal_state->requested_bis_sync[i])) {
 			LOG_DBG("Invalid BIS sync[%d]: 0x%08X", i,
 				internal_state->requested_bis_sync[i]);
-
-			return BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
+			ret = BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
+			goto unlock_return;
 		}
 
 		aggregated_bis_syncs |= internal_state->requested_bis_sync[i];
 
 		subgroup->metadata_len = net_buf_simple_pull_u8(buf);
 
-		if (buf->len < subgroup->metadata_len) {
-			LOG_DBG("Invalid length %u", buf->size);
-
-			return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
-		}
-
-
 		if (subgroup->metadata_len > CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE) {
 			LOG_WRN("Metadata too long %u/%u", subgroup->metadata_len,
 				CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE);
-
-			return BT_GATT_ERR(BT_ATT_ERR_INSUFFICIENT_RESOURCES);
+			ret = BT_GATT_ERR(BT_ATT_ERR_INSUFFICIENT_RESOURCES);
+			goto unlock_return;
 		}
 
 		metadata = net_buf_simple_pull_mem(buf, subgroup->metadata_len);
@@ -615,55 +743,60 @@ static int scan_delegator_add_source(struct bt_conn *conn,
 			     subgroup->metadata_len);
 	}
 
-	if (buf->len != 0) {
-		LOG_DBG("Invalid length %u", buf->size);
-		return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
-	}
-
 	/* The active flag shall be set before any application callbacks, so that any calls for the
 	 * receive state can be processed
 	 */
 	internal_state->active = true;
 
-	/* Set NOTIFY_PEND flag to ensure that we only send 1 notification in case that the upper
-	 * layer calls another function that changes the state in the pa_sync_request callback
-	 */
-	atomic_set_bit(internal_state->flags, BASS_RECV_STATE_INTERNAL_FLAG_NOTIFY_PEND);
-
 	if (pa_sync != BT_BAP_BASS_PA_REQ_NO_SYNC) {
-		int err;
+		/* Unlock mutex to avoid potential deadlock on app callback */
+		err = k_mutex_unlock(&internal_state->mutex);
+		__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
 
 		err = pa_sync_request(conn, state, pa_sync, pa_interval);
-
 		if (err != 0) {
+			k_mutex_lock(&internal_state->mutex, K_FOREVER);
+
 			(void)memset(state, 0, sizeof(*state));
 			internal_state->active = false;
 
-			LOG_DBG("PA sync %u from %p was rejected with reason %d", pa_sync, conn,
-				err);
+			LOG_DBG("PA sync %u from %p was rejected with reason %d", pa_sync,
+				(void *)conn, err);
+
+			err = k_mutex_unlock(&internal_state->mutex);
+			__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
 
 			return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
 		}
+
+		k_mutex_lock(&internal_state->mutex, K_FOREVER);
 	}
 
 	LOG_DBG("Index %u: New source added: ID 0x%02x",
 		internal_state->index, state->src_id);
 
-	atomic_clear_bit(internal_state->flags,
-			 BASS_RECV_STATE_INTERNAL_FLAG_NOTIFY_PEND);
+	set_receive_state_changed(internal_state);
 
-	receive_state_updated(conn, internal_state);
+unlock_return:
+	err = k_mutex_unlock(&internal_state->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
 
-	if (bis_sync_requested) {
-		bis_sync_request_updated(conn, internal_state);
+	if (ret == BT_GATT_ERR(BT_ATT_ERR_SUCCESS)) {
+		/* app callback */
+		receive_state_updated(conn, internal_state);
+
+		if (bis_sync_requested) {
+			bis_sync_request_updated(conn, internal_state);
+		}
 	}
 
-	return 0;
+	return ret;
 }
 
 static int scan_delegator_mod_src(struct bt_conn *conn,
 				  struct net_buf_simple *buf)
 {
+	uint32_t requested_bis_sync[CONFIG_BT_BAP_BASS_MAX_SUBGROUPS] = {};
 	struct bt_bap_scan_delegator_recv_state backup_state;
 	struct bass_recv_state_internal *internal_state;
 	struct bt_bap_scan_delegator_recv_state *state;
@@ -676,6 +809,10 @@ static int scan_delegator_mod_src(struct bt_conn *conn,
 	uint8_t pa_sync;
 	uint32_t aggregated_bis_syncs = 0;
 	bool bis_sync_change_requested;
+	uint16_t total_len;
+	struct bt_bap_bass_cp_mod_src *mod_src;
+	int ret = BT_GATT_ERR(BT_ATT_ERR_SUCCESS);
+	int err;
 
 	/* subtract 1 as the opcode has already been pulled */
 	if (buf->len < sizeof(struct bt_bap_bass_cp_mod_src) - 1) {
@@ -684,6 +821,34 @@ static int scan_delegator_mod_src(struct bt_conn *conn,
 		return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
 	}
 
+	mod_src = (void *)(buf->data - 1);
+	total_len = sizeof(struct bt_bap_bass_cp_mod_src) - 1;
+	for (int i = 0; i < mod_src->num_subgroups; i++) {
+		struct bt_bap_bass_cp_subgroup *subgroup;
+		uint16_t index = total_len;
+
+		total_len += sizeof(struct bt_bap_bass_cp_subgroup);
+		if (total_len > buf->len) {
+			LOG_DBG("Invalid length %u", buf->len);
+
+			return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
+		}
+
+		subgroup = (void *)&buf->data[index];
+		total_len += subgroup->metadata_len;
+		if (total_len > buf->len) {
+			LOG_DBG("Invalid length %u", buf->len);
+
+			return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
+		}
+	}
+
+	if (total_len != buf->len) {
+		LOG_DBG("Invalid length %u", buf->len);
+
+		return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
+	}
+
 	src_id = net_buf_simple_pull_u8(buf);
 	internal_state = bass_lookup_src_id(src_id);
 
@@ -708,6 +873,12 @@ static int scan_delegator_mod_src(struct bt_conn *conn,
 	if (num_subgroups > CONFIG_BT_BAP_BASS_MAX_SUBGROUPS) {
 		LOG_WRN("Too many subgroups %u/%u", num_subgroups,
 			CONFIG_BT_BAP_BASS_MAX_SUBGROUPS);
+		return BT_GATT_ERR(BT_ATT_ERR_INSUFFICIENT_RESOURCES);
+	}
+
+	err = k_mutex_lock(&internal_state->mutex, SCAN_DELEGATOR_BUF_SEM_TIMEOUT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex: %d", err);
 
 		return BT_GATT_ERR(BT_ATT_ERR_INSUFFICIENT_RESOURCES);
 	}
@@ -715,54 +886,46 @@ static int scan_delegator_mod_src(struct bt_conn *conn,
 	bis_sync_change_requested = false;
 	for (int i = 0; i < num_subgroups; i++) {
 		struct bt_bap_bass_subgroup *subgroup = &subgroups[i];
-		uint32_t old_bis_sync_req;
 		uint8_t *metadata;
 
-		if (buf->len < (sizeof(subgroup->bis_sync) + sizeof(subgroup->metadata_len))) {
-			LOG_DBG("Invalid length %u", buf->len);
-			return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
-		}
-
-		old_bis_sync_req = internal_state->requested_bis_sync[i];
-
-		internal_state->requested_bis_sync[i] = net_buf_simple_pull_le32(buf);
+		requested_bis_sync[i] = net_buf_simple_pull_le32(buf);
 
-		if (internal_state->requested_bis_sync[i] &&
-		    pa_sync == BT_BAP_BASS_PA_REQ_NO_SYNC) {
+		if (requested_bis_sync[i] != 0U && pa_sync == BT_BAP_BASS_PA_REQ_NO_SYNC) {
 			LOG_DBG("Cannot sync to BIS without PA");
-			return BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
+			ret = BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
+			goto unlock_return;
 		}
 
-		if (old_bis_sync_req != internal_state->requested_bis_sync[i]) {
+		/* If the BIS sync request is different than what was previously was requested, or
+		 * different than what we are current synced to, we set bis_sync_change_requested to
+		 * let the application know that the state may need a change
+		 */
+		if (internal_state->requested_bis_sync[i] != requested_bis_sync[i] ||
+		    internal_state->state.subgroups[i].bis_sync != requested_bis_sync[i]) {
 			bis_sync_change_requested = true;
 		}
 
 		/* Verify that the request BIS sync indexes are unique or no preference */
-		if (!bis_syncs_unique_or_no_pref(internal_state->requested_bis_sync[i],
-						 aggregated_bis_syncs)) {
-			LOG_DBG("Duplicate BIS index [%d]%x (aggregated %x)",
-				i, internal_state->requested_bis_sync[i],
-				aggregated_bis_syncs);
-
-			return BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
+		if (!bis_syncs_unique_or_no_pref(requested_bis_sync[i], aggregated_bis_syncs)) {
+			LOG_DBG("Duplicate BIS index [%d]%x (aggregated %x)", i,
+				requested_bis_sync[i], aggregated_bis_syncs);
+			ret = BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
+			goto unlock_return;
 		}
 
-		if (!valid_bis_syncs(internal_state->requested_bis_sync[i])) {
-			return BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
+		if (!valid_bis_syncs(requested_bis_sync[i])) {
+			ret = BT_GATT_ERR(BT_ATT_ERR_VALUE_NOT_ALLOWED);
+			goto unlock_return;
 		}
-		aggregated_bis_syncs |= internal_state->requested_bis_sync[i];
+		aggregated_bis_syncs |= requested_bis_sync[i];
 
 		subgroup->metadata_len = net_buf_simple_pull_u8(buf);
 
-		if (buf->len < subgroup->metadata_len) {
-			LOG_DBG("Invalid length %u", buf->len);
-			return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
-		}
-
 		if (subgroup->metadata_len > CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE) {
 			LOG_WRN("Metadata too long %u/%u", subgroup->metadata_len,
 				CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE);
-			return BT_GATT_ERR(BT_ATT_ERR_INSUFFICIENT_RESOURCES);
+			ret = BT_GATT_ERR(BT_ATT_ERR_INSUFFICIENT_RESOURCES);
+			goto unlock_return;
 		}
 
 		metadata = net_buf_simple_pull_mem(buf, subgroup->metadata_len);
@@ -771,12 +934,6 @@ static int scan_delegator_mod_src(struct bt_conn *conn,
 			     subgroup->metadata_len);
 	}
 
-	if (buf->len != 0) {
-		LOG_DBG("Invalid length %u", buf->size);
-
-		return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
-	}
-
 	/* All input has been validated; update receive state and check for changes */
 	state = &internal_state->state;
 
@@ -813,27 +970,29 @@ static int scan_delegator_mod_src(struct bt_conn *conn,
 		}
 	}
 
-	/* Set NOTIFY_PEND flag to ensure that we only send 1 notification in case that the upper
-	 * layer calls another function that changes the state in the pa_sync_request callback
-	 */
-	atomic_set_bit(internal_state->flags, BASS_RECV_STATE_INTERNAL_FLAG_NOTIFY_PEND);
-
 	/* Only send the sync request to upper layers if it is requested, and
 	 * we are not already synced to the device
 	 */
 	if (pa_sync != BT_BAP_BASS_PA_REQ_NO_SYNC &&
 	    state->pa_sync_state != BT_BAP_PA_STATE_SYNCED) {
 		const uint8_t pa_sync_state = state->pa_sync_state;
-		const int err = pa_sync_request(conn, state, pa_sync,
-						pa_interval);
 
+		/* Unlock mutex to avoid potential deadlock on app callback */
+		err = k_mutex_unlock(&internal_state->mutex);
+		__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
+		err = pa_sync_request(conn, state, pa_sync, pa_interval);
 		if (err != 0) {
+			k_mutex_lock(&internal_state->mutex, K_FOREVER);
+
 			/* Restore backup */
-			(void)memcpy(state, &backup_state,
-				     sizeof(backup_state));
+			(void)memcpy(state, &backup_state, sizeof(backup_state));
 
-			LOG_DBG("PA sync %u from %p was rejected with reason %d", pa_sync, conn,
-				err);
+			LOG_DBG("PA sync %u from %p was rejected with reason %d", pa_sync,
+				(void *)conn, err);
+
+			err = k_mutex_unlock(&internal_state->mutex);
+			__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
 
 			return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
 		} else if (pa_sync_state != state->pa_sync_state) {
@@ -843,28 +1002,45 @@ static int scan_delegator_mod_src(struct bt_conn *conn,
 			 */
 			state_changed = true;
 		}
+		k_mutex_lock(&internal_state->mutex, K_FOREVER);
 	} else if (pa_sync == BT_BAP_BASS_PA_REQ_NO_SYNC &&
 		   (state->pa_sync_state == BT_BAP_PA_STATE_INFO_REQ ||
 		    state->pa_sync_state == BT_BAP_PA_STATE_SYNCED)) {
+		/* Unlock mutex to avoid potential deadlock on app callback */
+		err = k_mutex_unlock(&internal_state->mutex);
+		__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
 		/* Terminate PA sync */
-		const int err = pa_sync_term_request(conn, &internal_state->state);
+		err = pa_sync_term_request(conn, &internal_state->state);
 
 		if (err != 0) {
-			LOG_DBG("PA sync term from %p was rejected with reason %d", conn, err);
+			LOG_DBG("PA sync term from %p was rejected with reason %d", (void *)conn,
+				err);
 
 			return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
 		}
 
 		state_changed = true;
+		k_mutex_lock(&internal_state->mutex, K_FOREVER);
 	}
 
-	atomic_clear_bit(internal_state->flags, BASS_RECV_STATE_INTERNAL_FLAG_NOTIFY_PEND);
+	/* Store requested_bis_sync after everything has been validated */
+	(void)memcpy(internal_state->requested_bis_sync, requested_bis_sync,
+		     sizeof(requested_bis_sync));
 
 	/* Notify if changed */
 	if (state_changed) {
-		LOG_DBG("Index %u: Source modified: ID 0x%02x",
-			internal_state->index, state->src_id);
+		LOG_DBG("Index %u: Source modified: ID 0x%02x", internal_state->index,
+			state->src_id);
+		set_receive_state_changed(internal_state);
+	}
 
+unlock_return:
+	err = k_mutex_unlock(&internal_state->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
+	if (state_changed) {
+		/* app callback */
 		receive_state_updated(conn, internal_state);
 	}
 
@@ -872,7 +1048,7 @@ static int scan_delegator_mod_src(struct bt_conn *conn,
 		bis_sync_request_updated(conn, internal_state);
 	}
 
-	return 0;
+	return ret;
 }
 
 static int scan_delegator_broadcast_code(struct bt_conn *conn,
@@ -918,8 +1094,9 @@ static int scan_delegator_rem_src(struct bt_conn *conn,
 {
 	struct bass_recv_state_internal *internal_state;
 	struct bt_bap_scan_delegator_recv_state *state;
-	bool bis_sync_was_requested;
+	bool bis_sync_was_requested = false;
 	uint8_t src_id;
+	int err;
 
 	/* subtract 1 as the opcode has already been pulled */
 	if (buf->len != sizeof(struct bt_bap_bass_cp_rem_src) - 1) {
@@ -935,25 +1112,37 @@ static int scan_delegator_rem_src(struct bt_conn *conn,
 		return BT_GATT_ERR(BT_BAP_BASS_ERR_INVALID_SRC_ID);
 	}
 
+	err = k_mutex_lock(&internal_state->mutex, SCAN_DELEGATOR_BUF_SEM_TIMEOUT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex: %d", err);
+
+		return BT_GATT_ERR(BT_ATT_ERR_INSUFFICIENT_RESOURCES);
+	}
+
 	state = &internal_state->state;
 
 	/* If conn == NULL then it's a local operation and we do not need to ask the application */
 	if (conn != NULL && (state->pa_sync_state == BT_BAP_PA_STATE_INFO_REQ ||
 			     state->pa_sync_state == BT_BAP_PA_STATE_SYNCED)) {
-		int err;
+		/* Unlock mutex to avoid potential deadlock on app callback */
+		err = k_mutex_unlock(&internal_state->mutex);
+		__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
 
 		/* Terminate PA sync */
 		err = pa_sync_term_request(conn, &internal_state->state);
 		if (err != 0) {
-			LOG_DBG("PA sync term from %p was rejected with reason %d", conn, err);
+			LOG_DBG("PA sync term from %p was rejected with reason %d", (void *)conn,
+				err);
 
 			return BT_GATT_ERR(BT_ATT_ERR_WRITE_REQ_REJECTED);
 		}
+
+		k_mutex_lock(&internal_state->mutex, K_FOREVER);
 	}
 
-	bis_sync_was_requested = false;
 	for (uint8_t i = 0U; i < state->num_subgroups; i++) {
-		if (internal_state->requested_bis_sync[i] != 0U) {
+		if (internal_state->requested_bis_sync[i] != 0U &&
+		    internal_state->state.subgroups[i].bis_sync != 0U) {
 			bis_sync_was_requested = true;
 			break;
 		}
@@ -970,12 +1159,19 @@ static int scan_delegator_rem_src(struct bt_conn *conn,
 	(void)memset(internal_state->requested_bis_sync, 0,
 		     sizeof(internal_state->requested_bis_sync));
 
+	set_receive_state_changed(internal_state);
+
+	err = k_mutex_unlock(&internal_state->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
 	if (bis_sync_was_requested) {
 		bis_sync_request_updated(conn, internal_state);
 	}
+
+	/* app callback */
 	receive_state_updated(conn, internal_state);
 
-	return 0;
+	return BT_GATT_ERR(BT_ATT_ERR_SUCCESS);
 }
 
 static ssize_t write_control_point(struct bt_conn *conn,
@@ -1032,7 +1228,7 @@ static ssize_t write_control_point(struct bt_conn *conn,
 	case BT_BAP_BASS_OP_ADD_SRC:
 		LOG_DBG("Assistant adding source");
 
-		err = scan_delegator_add_source(conn, &buf);
+		err = scan_delegator_add_src(conn, &buf);
 		if (err != 0) {
 			LOG_DBG("Could not add source %d", err);
 			return err;
@@ -1096,20 +1292,23 @@ static ssize_t read_recv_state(struct bt_conn *conn,
 
 		LOG_DBG("Index %u: Source ID 0x%02x", idx, state->src_id);
 
-		err = k_sem_take(&read_buf_sem, SCAN_DELEGATOR_BUF_SEM_TIMEOUT);
+		err = k_mutex_lock(&recv_state->mutex, SCAN_DELEGATOR_BUF_SEM_TIMEOUT);
 		if (err != 0) {
-			LOG_DBG("Failed to take read_buf_sem: %d", err);
+			LOG_DBG("Failed to lock mutex: %d", err);
 
 			return err;
 		}
 
-		bt_debug_dump_recv_state(recv_state);
+		if (IS_ENABLED(CONFIG_BT_BAP_SCAN_DELEGATOR_LOG_LEVEL_DBG)) {
+			bt_debug_dump_recv_state(recv_state);
+		}
 		net_buf_put_recv_state(recv_state);
 
 		ret_val = bt_gatt_attr_read(conn, attr, buf, len, offset,
 					    read_buf.data, read_buf.len);
 
-		k_sem_give(&read_buf_sem);
+		err = k_mutex_unlock(&recv_state->mutex);
+		__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
 
 		return ret_val;
 	}
@@ -1214,6 +1413,15 @@ int bt_bap_scan_delegator_register(struct bt_bap_scan_delegator_cb *cb)
 		}
 	}
 
+	for (size_t i = 0; i < ARRAY_SIZE(scan_delegator.recv_states); i++) {
+		struct bass_recv_state_internal *internal_state = &scan_delegator.recv_states[i];
+
+		err = k_mutex_init(&internal_state->mutex);
+		__ASSERT(err == 0, "Failed to initialize mutex");
+
+		k_work_init_delayable(&internal_state->notify_work, notify_work_handler);
+	}
+
 	scan_delegator_cbs = cb;
 
 	return 0;
@@ -1246,16 +1454,34 @@ int bt_bap_scan_delegator_set_pa_state(uint8_t src_id,
 {
 	struct bass_recv_state_internal *internal_state = bass_lookup_src_id(src_id);
 	struct bt_bap_scan_delegator_recv_state *recv_state;
+	bool state_changed = false;
+	int err;
 
 	if (internal_state == NULL) {
 		LOG_DBG("Could not find recv_state by src_id %u", src_id);
 		return -EINVAL;
 	}
 
+	err = k_mutex_lock(&internal_state->mutex, SCAN_DELEGATOR_BUF_SEM_TIMEOUT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex: %d", err);
+
+		return -EBUSY;
+	}
+
 	recv_state = &internal_state->state;
 
 	if (recv_state->pa_sync_state != pa_state) {
 		recv_state->pa_sync_state = pa_state;
+		set_receive_state_changed(internal_state);
+		state_changed = true;
+	}
+
+	err = k_mutex_unlock(&internal_state->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
+	if (state_changed) {
+		/* app callback */
 		receive_state_updated(NULL, internal_state);
 	}
 
@@ -1268,16 +1494,26 @@ int bt_bap_scan_delegator_set_bis_sync_state(
 {
 	struct bass_recv_state_internal *internal_state = bass_lookup_src_id(src_id);
 	bool notify = false;
+	int ret = 0;
+	int err;
 
 	if (internal_state == NULL) {
 		LOG_DBG("Could not find recv_state by src_id %u", src_id);
 		return -EINVAL;
 	}
 
+	err = k_mutex_lock(&internal_state->mutex, SCAN_DELEGATOR_BUF_SEM_TIMEOUT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex: %d", err);
+
+		return -EBUSY;
+	}
+
 	if (internal_state->state.pa_sync_state != BT_BAP_PA_STATE_SYNCED) {
 		LOG_DBG("PA for src_id %u isn't synced, cannot be BIG synced",
 			src_id);
-		return -EINVAL;
+		ret = -EINVAL;
+		goto unlock_return;
 	}
 
 	/* Verify state for all subgroups before assigning any data */
@@ -1291,8 +1527,8 @@ int bt_bap_scan_delegator_set_bis_sync_state(
 				    internal_state->requested_bis_sync[i])) {
 			LOG_DBG("Subgroup[%u] invalid bis_sync value %x for %x",
 				i, bis_synced[i], internal_state->requested_bis_sync[i]);
-
-			return -EINVAL;
+			ret = -EINVAL;
+			goto unlock_return;
 		}
 	}
 
@@ -1314,16 +1550,24 @@ int bt_bap_scan_delegator_set_bis_sync_state(
 		internal_state->index, src_id);
 
 	if (internal_state->state.encrypt_state == BT_BAP_BIG_ENC_STATE_BAD_CODE) {
-		(void)memcpy(internal_state->state.bad_code,
-			     internal_state->broadcast_code,
+		(void)memset(internal_state->state.bad_code, 0xFF,
 			     sizeof(internal_state->state.bad_code));
 	}
 
 	if (notify) {
+		set_receive_state_changed(internal_state);
+	}
+
+unlock_return:
+	err = k_mutex_unlock(&internal_state->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
+	if (notify) {
+		/* app callback */
 		receive_state_updated(NULL, internal_state);
 	}
 
-	return 0;
+	return ret;
 }
 
 static bool valid_bt_bap_scan_delegator_add_src_param(
@@ -1381,6 +1625,7 @@ int bt_bap_scan_delegator_add_src(const struct bt_bap_scan_delegator_add_src_par
 	struct bass_recv_state_internal *internal_state = NULL;
 	struct bt_bap_scan_delegator_recv_state *state;
 	struct bt_le_per_adv_sync *pa_sync;
+	int err;
 
 	CHECKIF(!valid_bt_bap_scan_delegator_add_src_param(param)) {
 		return -EINVAL;
@@ -1421,6 +1666,13 @@ int bt_bap_scan_delegator_add_src(const struct bt_bap_scan_delegator_add_src_par
 		(void)memset(state->subgroups, 0, sizeof(state->subgroups));
 	}
 
+	err = k_mutex_lock(&internal_state->mutex, SCAN_DELEGATOR_BUF_SEM_TIMEOUT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex: %d", err);
+
+		return -EBUSY;
+	}
+
 	internal_state->active = true;
 	internal_state->pa_sync = pa_sync;
 
@@ -1434,6 +1686,12 @@ int bt_bap_scan_delegator_add_src(const struct bt_bap_scan_delegator_add_src_par
 	LOG_DBG("Index %u: New source added: ID 0x%02x",
 		internal_state->index, state->src_id);
 
+	set_receive_state_changed(internal_state);
+
+	err = k_mutex_unlock(&internal_state->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
+	/* app callback */
 	receive_state_updated(NULL, internal_state);
 
 	return state->src_id;
@@ -1484,6 +1742,8 @@ int bt_bap_scan_delegator_mod_src(const struct bt_bap_scan_delegator_mod_src_par
 	struct bass_recv_state_internal *internal_state = NULL;
 	struct bt_bap_scan_delegator_recv_state *state;
 	bool state_changed = false;
+	int ret = 0;
+	int err;
 
 	CHECKIF(!valid_bt_bap_scan_delegator_mod_src_param(param)) {
 		return -EINVAL;
@@ -1496,6 +1756,13 @@ int bt_bap_scan_delegator_mod_src(const struct bt_bap_scan_delegator_mod_src_par
 		return -ENOENT;
 	}
 
+	err = k_mutex_lock(&internal_state->mutex, SCAN_DELEGATOR_BUF_SEM_TIMEOUT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex: %d", err);
+
+		return -EBUSY;
+	}
+
 	state = &internal_state->state;
 
 	if (state->broadcast_id != param->broadcast_id) {
@@ -1512,8 +1779,7 @@ int bt_bap_scan_delegator_mod_src(const struct bt_bap_scan_delegator_mod_src_par
 		state->encrypt_state = param->encrypt_state;
 
 		if (state->encrypt_state == BT_BAP_BIG_ENC_STATE_BAD_CODE) {
-			(void)memcpy(state->bad_code, internal_state->broadcast_code,
-				     sizeof(internal_state->state.bad_code));
+			(void)memset(state->bad_code, 0xFF, sizeof(internal_state->state.bad_code));
 		}
 
 		state_changed = true;
@@ -1528,8 +1794,8 @@ int bt_bap_scan_delegator_mod_src(const struct bt_bap_scan_delegator_mod_src_par
 		    !bits_subset_of(bis_sync, bis_sync_requested)) {
 			LOG_DBG("Subgroup[%d] invalid bis_sync value %x for %x",
 				i, bis_sync, bis_sync_requested);
-
-			return -EINVAL;
+			ret = -EINVAL;
+			goto unlock_return;
 		}
 	}
 
@@ -1566,11 +1832,20 @@ int bt_bap_scan_delegator_mod_src(const struct bt_bap_scan_delegator_mod_src_par
 	if (state_changed) {
 		LOG_DBG("Index %u: Source modified: ID 0x%02x",
 			internal_state->index, state->src_id);
+		set_receive_state_changed(internal_state);
+	}
 
+unlock_return:
+	err = k_mutex_unlock(&internal_state->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
+
+	if (state_changed) {
+		/* app callback */
 		receive_state_updated(NULL, internal_state);
 	}
 
-	return 0;
+	return ret;
 }
 
 int bt_bap_scan_delegator_rem_src(uint8_t src_id)
diff --git a/subsys/bluetooth/audio/bap_unicast_client.c b/subsys/bluetooth/audio/bap_unicast_client.c
index 280a2ff0222..1f081ee805b 100644
--- a/subsys/bluetooth/audio/bap_unicast_client.c
+++ b/subsys/bluetooth/audio/bap_unicast_client.c
@@ -4,7 +4,7 @@
 
 /*
  * Copyright (c) 2020 Intel Corporation
- * Copyright (c) 2022-2023 Nordic Semiconductor ASA
+ * Copyright (c) 2022-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -1019,13 +1019,6 @@ static void unicast_client_ep_qos_state(struct bt_bap_ep *ep, struct net_buf_sim
 		if (err != 0) {
 			LOG_ERR("Failed to disconnect stream: %d", err);
 		}
-	} else {
-		/* We setup the data path here, as this is the earliest where
-		 * we have the ISO <-> EP coupling completed (due to setting
-		 * the CIS ID in the QoS procedure).
-		 */
-
-		bt_bap_iso_configure_data_path(ep, stream->codec_cfg);
 	}
 
 	/* Notify upper layer */
@@ -1108,6 +1101,11 @@ static void unicast_client_ep_streaming_state(struct bt_bap_ep *ep, struct net_b
 
 	LOG_DBG("dir %s cig 0x%02x cis 0x%02x", bt_audio_dir_str(ep->dir), ep->cig_id, ep->cis_id);
 
+	/* Setup the ISO data path when the stream is started. We could do it earlier when the CIS
+	 * is connected, but then we would just receive audio data that we would then just discard
+	 */
+	bt_bap_setup_iso_data_path(stream);
+
 	/* Notify upper layer
 	 *
 	 * If the state did not change then only the metadata was changed
@@ -1222,6 +1220,13 @@ static void unicast_client_ep_set_status(struct bt_bap_ep *ep, struct net_buf_si
 				ep->reason = BT_HCI_ERR_SUCCESS;
 			}
 
+			if (ep->iso != NULL) {
+				/* Remove the ISO data path as we no longer want to process any ISO
+				 * data for this stream.
+				 */
+				bt_bap_remove_iso_data_path(stream);
+			}
+
 			if (ops != NULL && ops->stopped != NULL) {
 				ops->stopped(stream, reason);
 			} else {
@@ -1747,7 +1752,6 @@ static uint8_t unicast_client_ep_notify(struct bt_conn *conn,
 {
 	struct net_buf_simple buf;
 	struct bt_bap_unicast_client_ep *client_ep;
-	const uint8_t att_ntf_header_size = 3; /* opcode (1) + handle (2) */
 	uint16_t max_ntf_size;
 	struct bt_bap_ep *ep;
 
@@ -1765,7 +1769,7 @@ static uint8_t unicast_client_ep_notify(struct bt_conn *conn,
 		return BT_GATT_ITER_STOP;
 	}
 
-	max_ntf_size = bt_gatt_get_mtu(conn) - att_ntf_header_size;
+	max_ntf_size = bt_audio_get_max_ntf_size(conn);
 
 	if (length == max_ntf_size) {
 		struct unicast_client *client = &uni_cli_insts[bt_conn_index(conn)];
@@ -2166,8 +2170,7 @@ static void gatt_write_cb(struct bt_conn *conn, uint8_t err, struct bt_gatt_writ
 int bt_bap_unicast_client_ep_send(struct bt_conn *conn, struct bt_bap_ep *ep,
 				  struct net_buf_simple *buf)
 {
-	const uint8_t att_write_header_size = 3; /* opcode (1) + handle (2) */
-	const uint16_t max_write_size = bt_gatt_get_mtu(conn) - att_write_header_size;
+	const uint16_t max_write_size = bt_audio_get_max_ntf_size(conn);
 	struct unicast_client *client = &uni_cli_insts[bt_conn_index(conn)];
 	struct bt_bap_unicast_client_ep *client_ep =
 		CONTAINER_OF(ep, struct bt_bap_unicast_client_ep, ep);
diff --git a/subsys/bluetooth/audio/bap_unicast_client_internal.h b/subsys/bluetooth/audio/bap_unicast_client_internal.h
index 6c6c2857b1e..ae71b864d43 100644
--- a/subsys/bluetooth/audio/bap_unicast_client_internal.h
+++ b/subsys/bluetooth/audio/bap_unicast_client_internal.h
@@ -7,6 +7,7 @@
  */
 
 #include <stdint.h>
+#include <stddef.h>
 
 #include <zephyr/bluetooth/audio/audio.h>
 #include <zephyr/bluetooth/audio/bap.h>
diff --git a/subsys/bluetooth/audio/cap_commander.c b/subsys/bluetooth/audio/cap_commander.c
index 1a0bb2f8f9d..83ba8941a0a 100644
--- a/subsys/bluetooth/audio/cap_commander.c
+++ b/subsys/bluetooth/audio/cap_commander.c
@@ -23,6 +23,7 @@
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gap.h>
 #include <zephyr/bluetooth/gatt.h>
+#include <zephyr/bluetooth/iso.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/sys/__assert.h>
 #include <zephyr/sys/check.h>
@@ -333,26 +334,24 @@ int bt_cap_commander_broadcast_reception_start(
 	struct bt_conn *conn;
 	int err;
 
-	if (bt_cap_common_proc_is_active()) {
-		LOG_DBG("A CAP procedure is already in progress");
-
-		return -EBUSY;
-	}
-
 	if (!valid_broadcast_reception_start_param(param)) {
 		return -EINVAL;
 	}
 
-	bt_cap_common_start_proc(BT_CAP_COMMON_PROC_TYPE_BROADCAST_RECEPTION_START, param->count);
+	if (bt_cap_common_test_and_set_proc_active()) {
+		LOG_DBG("A CAP procedure is already in progress");
 
-	broadcast_assistant_cb.add_src = cap_commander_broadcast_assistant_add_src_cb;
-	if (!broadcast_assistant_cb_registered &&
-	    cap_commander_register_broadcast_assistant_cb() != 0) {
-		LOG_DBG("Failed to register broadcast assistant callbacks");
+		return -EBUSY;
+	}
 
-		return -ENOEXEC;
+	broadcast_assistant_cb.add_src = cap_commander_broadcast_assistant_add_src_cb;
+	if (!broadcast_assistant_cb_registered) {
+		err = cap_commander_register_broadcast_assistant_cb();
+		__ASSERT(err == 0, "Failed to register broadcast assistant callbacks: %d", err);
 	}
 
+	bt_cap_common_set_proc(BT_CAP_COMMON_PROC_TYPE_BROADCAST_RECEPTION_START, param->count);
+
 	active_proc = bt_cap_common_get_active_proc();
 
 	for (size_t i = 0U; i < param->count; i++) {
@@ -362,9 +361,12 @@ int bt_cap_commander_broadcast_reception_start(
 		struct bt_conn *member_conn =
 			bt_cap_common_get_member_conn(param->type, &member_param->member);
 
+		/* Perform extra check in case that connection state has changed */
 		if (member_conn == NULL) {
 			LOG_DBG("Invalid param->members[%zu]", i);
 
+			bt_cap_common_clear_active_proc();
+
 			return -EINVAL;
 		}
 
@@ -396,6 +398,8 @@ int bt_cap_commander_broadcast_reception_start(
 	if (err != 0) {
 		LOG_DBG("Failed to start broadcast reception for conn %p: %d", (void *)conn, err);
 
+		bt_cap_common_clear_active_proc();
+
 		return -ENOEXEC;
 	}
 
@@ -517,7 +521,7 @@ static void cap_commander_broadcast_assistant_mod_src_cb(struct bt_conn *conn, i
 
 		bt_cap_common_abort_proc(conn, err);
 	} else {
-		LOG_DBG("Conn %p broadcast source modifified (%zu/%zu streams done)", (void *)conn,
+		LOG_DBG("Conn %p broadcast source modified (%zu/%zu streams done)", (void *)conn,
 			active_proc->proc_done_cnt, active_proc->proc_cnt);
 	}
 
@@ -605,28 +609,26 @@ int bt_cap_commander_broadcast_reception_stop(
 	struct bt_conn *conn;
 	int err;
 
-	if (bt_cap_common_proc_is_active()) {
-		LOG_DBG("A CAP procedure is already in progress");
-
-		return -EBUSY;
-	}
-
 	if (!valid_broadcast_reception_stop_param(param)) {
 		return -EINVAL;
 	}
 
-	bt_cap_common_start_proc(BT_CAP_COMMON_PROC_TYPE_BROADCAST_RECEPTION_STOP, param->count);
+	if (bt_cap_common_test_and_set_proc_active()) {
+		LOG_DBG("A CAP procedure is already in progress");
+
+		return -EBUSY;
+	}
 
 	broadcast_assistant_cb.mod_src = cap_commander_broadcast_assistant_mod_src_cb;
 	broadcast_assistant_cb.rem_src = cap_commander_broadcast_assistant_rem_src_cb;
 	broadcast_assistant_cb.recv_state = cap_commander_broadcast_assistant_recv_state_cb;
-	if (!broadcast_assistant_cb_registered &&
-	    cap_commander_register_broadcast_assistant_cb() != 0) {
-		LOG_DBG("Failed to register broadcast assistant callbacks");
-
-		return -ENOEXEC;
+	if (!broadcast_assistant_cb_registered) {
+		err = cap_commander_register_broadcast_assistant_cb();
+		__ASSERT(err == 0, "Failed to register broadcast assistant callbacks: %d", err);
 	}
 
+	bt_cap_common_set_proc(BT_CAP_COMMON_PROC_TYPE_BROADCAST_RECEPTION_STOP, param->count);
+
 	active_proc = bt_cap_common_get_active_proc();
 
 	for (size_t i = 0U; i < param->count; i++) {
@@ -636,11 +638,15 @@ int bt_cap_commander_broadcast_reception_stop(
 		struct bt_conn *member_conn =
 			bt_cap_common_get_member_conn(param->type, &member_param->member);
 
+		/* Perform extra check in case that connection state has changed */
 		if (member_conn == NULL) {
 			LOG_DBG("Invalid param->member[%zu]", i);
 
+			bt_cap_common_clear_active_proc();
+
 			return -EINVAL;
 		}
+
 		/* Store the necessary parameters as we cannot assume that the supplied
 		 * parameters are kept valid
 		 */
@@ -665,6 +671,8 @@ int bt_cap_commander_broadcast_reception_stop(
 	if (err != 0) {
 		LOG_DBG("Failed to stop broadcast reception for conn %p: %d", (void *)conn, err);
 
+		bt_cap_common_clear_active_proc();
+
 		return -ENOEXEC;
 	}
 
@@ -786,27 +794,25 @@ int bt_cap_commander_distribute_broadcast_code(
 	struct bt_conn *conn;
 	int err;
 
-	if (bt_cap_common_proc_is_active()) {
-		LOG_DBG("A CAP procedure is already in progress");
-
-		return -EBUSY;
-	}
-
 	if (!valid_distribute_broadcast_code_param(param)) {
 		return -EINVAL;
 	}
 
-	bt_cap_common_start_proc(BT_CAP_COMMON_PROC_TYPE_DISTRIBUTE_BROADCAST_CODE, param->count);
+	if (bt_cap_common_test_and_set_proc_active()) {
+		LOG_DBG("A CAP procedure is already in progress");
+
+		return -EBUSY;
+	}
 
 	broadcast_assistant_cb.broadcast_code =
 		cap_commander_broadcast_assistant_set_broadcast_code_cb;
-	if (!broadcast_assistant_cb_registered &&
-	    cap_commander_register_broadcast_assistant_cb() != 0) {
-		LOG_DBG("Failed to register broadcast assistant callbacks");
-
-		return -ENOEXEC;
+	if (!broadcast_assistant_cb_registered) {
+		err = cap_commander_register_broadcast_assistant_cb();
+		__ASSERT(err == 0, "Failed to register broadcast assistant callbacks: %d", err);
 	}
 
+	bt_cap_common_set_proc(BT_CAP_COMMON_PROC_TYPE_DISTRIBUTE_BROADCAST_CODE, param->count);
+
 	active_proc = bt_cap_common_get_active_proc();
 
 	for (size_t i = 0U; i < param->count; i++) {
@@ -816,9 +822,12 @@ int bt_cap_commander_distribute_broadcast_code(
 		struct bt_conn *member_conn =
 			bt_cap_common_get_member_conn(param->type, &member_param->member);
 
+		/* Perform extra check in case that connection state has changed */
 		if (member_conn == NULL) {
 			LOG_DBG("Invalid param->member[%zu]", i);
 
+			bt_cap_common_clear_active_proc();
+
 			return -EINVAL;
 		}
 
@@ -846,6 +855,8 @@ int bt_cap_commander_distribute_broadcast_code(
 		LOG_DBG("Failed to start distribute broadcast code for conn %p: %d", (void *)conn,
 			err);
 
+		bt_cap_common_clear_active_proc();
+
 		return -ENOEXEC;
 	}
 
@@ -1084,33 +1095,36 @@ int bt_cap_commander_change_volume(const struct bt_cap_commander_change_volume_p
 	struct bt_conn *conn;
 	int err;
 
-	if (bt_cap_common_proc_is_active()) {
-		LOG_DBG("A CAP procedure is already in progress");
-
-		return -EBUSY;
-	}
-
 	if (!valid_change_volume_param(param)) {
 		return -EINVAL;
 	}
 
-	bt_cap_common_start_proc(BT_CAP_COMMON_PROC_TYPE_VOLUME_CHANGE, param->count);
+	if (bt_cap_common_test_and_set_proc_active()) {
+		LOG_DBG("A CAP procedure is already in progress");
 
-	vol_ctlr_cb.vol_set = cap_commander_vcp_vol_set_cb;
-	if (!vcp_cb_registered && cap_commander_register_vcp_cb() != 0) {
-		LOG_DBG("Failed to register VCP callbacks");
+		return -EBUSY;
+	}
 
-		return -ENOEXEC;
+	vol_ctlr_cb.vol_set = cap_commander_vcp_vol_set_cb;
+	if (!vcp_cb_registered) {
+		err = cap_commander_register_vcp_cb();
+		__ASSERT(err == 0, "Failed to register VCP callbacks: %d", err);
 	}
 
+	bt_cap_common_set_proc(BT_CAP_COMMON_PROC_TYPE_VOLUME_CHANGE, param->count);
+
 	active_proc = bt_cap_common_get_active_proc();
 
 	for (size_t i = 0U; i < param->count; i++) {
 		struct bt_conn *member_conn =
 			bt_cap_common_get_member_conn(param->type, &param->members[i]);
 
+		/* Perform extra check in case that connection state has changed */
 		if (member_conn == NULL) {
 			LOG_DBG("Invalid param->members[%zu]", i);
+
+			bt_cap_common_clear_active_proc();
+
 			return -EINVAL;
 		}
 
@@ -1128,6 +1142,9 @@ int bt_cap_commander_change_volume(const struct bt_cap_commander_change_volume_p
 				      proc_param->change_volume.volume);
 	if (err != 0) {
 		LOG_DBG("Failed to set volume for conn %p: %d", (void *)conn, err);
+
+		bt_cap_common_clear_active_proc();
+
 		return -ENOEXEC;
 	}
 
@@ -1263,34 +1280,36 @@ int bt_cap_commander_change_volume_mute_state(
 	struct bt_conn *conn;
 	int err;
 
-	if (bt_cap_common_proc_is_active()) {
-		LOG_DBG("A CAP procedure is already in progress");
-
-		return -EBUSY;
-	}
-
 	if (!valid_change_volume_mute_state_param(param)) {
 		return -EINVAL;
 	}
 
-	bt_cap_common_start_proc(BT_CAP_COMMON_PROC_TYPE_VOLUME_MUTE_CHANGE, param->count);
+	if (bt_cap_common_test_and_set_proc_active()) {
+		LOG_DBG("A CAP procedure is already in progress");
+
+		return -EBUSY;
+	}
 
 	vol_ctlr_cb.mute = cap_commander_vcp_vol_mute_cb;
 	vol_ctlr_cb.unmute = cap_commander_vcp_vol_mute_cb;
-	if (!vcp_cb_registered && cap_commander_register_vcp_cb() != 0) {
-		LOG_DBG("Failed to register VCP callbacks");
-
-		return -ENOEXEC;
+	if (!vcp_cb_registered) {
+		err = cap_commander_register_vcp_cb();
+		__ASSERT(err == 0, "Failed to register VCP callbacks: %d", err);
 	}
 
+	bt_cap_common_set_proc(BT_CAP_COMMON_PROC_TYPE_VOLUME_MUTE_CHANGE, param->count);
 	active_proc = bt_cap_common_get_active_proc();
 
 	for (size_t i = 0U; i < param->count; i++) {
 		struct bt_conn *member_conn =
 			bt_cap_common_get_member_conn(param->type, &param->members[i]);
 
-		CHECKIF(member_conn == NULL) {
+		/* Perform extra check in case that connection state has changed */
+		if (member_conn == NULL) {
 			LOG_DBG("Invalid param->members[%zu]", i);
+
+			bt_cap_common_clear_active_proc();
+
 			return -EINVAL;
 		}
 
@@ -1313,6 +1332,9 @@ int bt_cap_commander_change_volume_mute_state(
 
 	if (err != 0) {
 		LOG_DBG("Failed to set volume mute state for conn %p: %d", (void *)conn, err);
+
+		bt_cap_common_clear_active_proc();
+
 		return -ENOEXEC;
 	}
 
@@ -1466,25 +1488,24 @@ int bt_cap_commander_change_volume_offset(
 	struct bt_conn *conn;
 	int err;
 
-	if (bt_cap_common_proc_is_active()) {
-		LOG_DBG("A CAP procedure is already in progress");
-
-		return -EBUSY;
-	}
-
 	if (!valid_change_offset_param(param)) {
 		return -EINVAL;
 	}
 
-	bt_cap_common_start_proc(BT_CAP_COMMON_PROC_TYPE_VOLUME_OFFSET_CHANGE, param->count);
+	if (bt_cap_common_test_and_set_proc_active()) {
+		LOG_DBG("A CAP procedure is already in progress");
 
-	vol_ctlr_cb.vocs_cb.set_offset = cap_commander_vcp_set_offset_cb;
-	if (!vcp_cb_registered && cap_commander_register_vcp_cb() != 0) {
-		LOG_DBG("Failed to register VCP callbacks");
+		return -EBUSY;
+	}
 
-		return -ENOEXEC;
+	vol_ctlr_cb.vocs_cb.set_offset = cap_commander_vcp_set_offset_cb;
+	if (!vcp_cb_registered) {
+		err = cap_commander_register_vcp_cb();
+		__ASSERT(err == 0, "Failed to register VCP callbacks: %d", err);
 	}
 
+	bt_cap_common_set_proc(BT_CAP_COMMON_PROC_TYPE_VOLUME_OFFSET_CHANGE, param->count);
+
 	active_proc = bt_cap_common_get_active_proc();
 
 	for (size_t i = 0U; i < param->count; i++) {
@@ -1494,20 +1515,30 @@ int bt_cap_commander_change_volume_offset(
 			bt_cap_common_get_member_conn(param->type, &member_param->member);
 		struct bt_vcp_included included;
 
+		/* Perform extra check in case that connection state has changed */
 		if (member_conn == NULL) {
 			LOG_DBG("Invalid param->members[%zu]", i);
+
+			bt_cap_common_clear_active_proc();
+
 			return -EINVAL;
 		}
 
 		vol_ctlr = bt_vcp_vol_ctlr_get_by_conn(member_conn);
 		if (vol_ctlr == NULL) {
 			LOG_DBG("Invalid param->members[%zu] vol_ctlr", i);
+
+			bt_cap_common_clear_active_proc();
+
 			return -EINVAL;
 		}
 
 		err = bt_vcp_vol_ctlr_included_get(vol_ctlr, &included);
 		if (err != 0 || included.vocs_cnt == 0) {
 			LOG_DBG("Invalid param->members[%zu] vocs", i);
+
+			bt_cap_common_clear_active_proc();
+
 			return -EINVAL;
 		}
 
@@ -1529,6 +1560,9 @@ int bt_cap_commander_change_volume_offset(
 	err = bt_vocs_state_set(proc_param->change_offset.vocs, proc_param->change_offset.offset);
 	if (err != 0) {
 		LOG_DBG("Failed to set volume for conn %p: %d", (void *)conn, err);
+
+		bt_cap_common_clear_active_proc();
+
 		return -ENOEXEC;
 	}
 
@@ -1686,24 +1720,23 @@ int bt_cap_commander_change_microphone_mute_state(
 	struct bt_conn *conn;
 	int err;
 
-	if (bt_cap_common_proc_is_active()) {
+	if (!valid_change_microphone_mute_state_param(param)) {
+		return -EINVAL;
+	}
+
+	if (bt_cap_common_test_and_set_proc_active()) {
 		LOG_DBG("A CAP procedure is already in progress");
 
 		return -EBUSY;
 	}
 
-	if (!valid_change_microphone_mute_state_param(param)) {
-		return -EINVAL;
-	}
-
-	bt_cap_common_start_proc(BT_CAP_COMMON_PROC_TYPE_MICROPHONE_MUTE_CHANGE, param->count);
+	bt_cap_common_set_proc(BT_CAP_COMMON_PROC_TYPE_MICROPHONE_MUTE_CHANGE, param->count);
 
 	mic_ctlr_cb.mute_written = cap_commander_micp_mic_mute_cb;
 	mic_ctlr_cb.unmute_written = cap_commander_micp_mic_mute_cb;
-	if (!micp_callbacks_registered && cap_commander_register_micp_callbacks() != 0) {
-		LOG_DBG("Failed to register MICP callbacks");
-
-		return -ENOEXEC;
+	if (!micp_callbacks_registered) {
+		err = cap_commander_register_micp_callbacks();
+		__ASSERT(err == 0, "Failed to register MICP callbacks: %d", err);
 	}
 
 	active_proc = bt_cap_common_get_active_proc();
@@ -1712,8 +1745,12 @@ int bt_cap_commander_change_microphone_mute_state(
 		struct bt_conn *member_conn =
 			bt_cap_common_get_member_conn(param->type, &param->members[i]);
 
-		CHECKIF(member_conn == NULL) {
+		/* Perform extra check in case that connection state has changed */
+		if (member_conn == NULL) {
 			LOG_DBG("Invalid param->members[%zu]", i);
+
+			bt_cap_common_clear_active_proc();
+
 			return -EINVAL;
 		}
 
@@ -1736,6 +1773,9 @@ int bt_cap_commander_change_microphone_mute_state(
 
 	if (err != 0) {
 		LOG_DBG("Failed to set microphone mute state for conn %p: %d", (void *)conn, err);
+
+		bt_cap_common_clear_active_proc();
+
 		return -ENOEXEC;
 	}
 
@@ -1879,23 +1919,22 @@ int bt_cap_commander_change_microphone_gain_setting(
 	struct bt_conn *conn;
 	int err;
 
-	if (bt_cap_common_proc_is_active()) {
+	if (!valid_change_microphone_gain_param(param)) {
+		return -EINVAL;
+	}
+
+	if (bt_cap_common_test_and_set_proc_active()) {
 		LOG_DBG("A CAP procedure is already in progress");
 
 		return -EBUSY;
 	}
 
-	if (!valid_change_microphone_gain_param(param)) {
-		return -EINVAL;
-	}
-
-	bt_cap_common_start_proc(BT_CAP_COMMON_PROC_TYPE_MICROPHONE_GAIN_CHANGE, param->count);
+	bt_cap_common_set_proc(BT_CAP_COMMON_PROC_TYPE_MICROPHONE_GAIN_CHANGE, param->count);
 
 	mic_ctlr_cb.aics_cb.set_gain = cap_commander_micp_gain_set_cb;
-	if (!micp_callbacks_registered && cap_commander_register_micp_callbacks() != 0) {
-		LOG_DBG("Failed to register MICP callbacks");
-
-		return -ENOEXEC;
+	if (!micp_callbacks_registered) {
+		err = cap_commander_register_micp_callbacks();
+		__ASSERT(err == 0, "Failed to register MICP callbacks: %d", err);
 	}
 
 	active_proc = bt_cap_common_get_active_proc();
@@ -1906,20 +1945,30 @@ int bt_cap_commander_change_microphone_gain_setting(
 		struct bt_micp_mic_ctlr *mic_ctlr;
 		struct bt_micp_included included;
 
+		/* Perform extra check in case that connection state has changed */
 		if (member_conn == NULL) {
 			LOG_DBG("Invalid param->param[%zu].member", i);
+
+			bt_cap_common_clear_active_proc();
+
 			return -EINVAL;
 		}
 
 		mic_ctlr = bt_micp_mic_ctlr_get_by_conn(member_conn);
 		if (mic_ctlr == NULL) {
 			LOG_DBG("Invalid param->param[%zu].member mic_ctlr", i);
+
+			bt_cap_common_clear_active_proc();
+
 			return -EINVAL;
 		}
 
 		err = bt_micp_mic_ctlr_included_get(mic_ctlr, &included);
 		if (err != 0 || included.aics_cnt == 0) {
 			LOG_DBG("Invalid param->param[%zu].member aics", i);
+
+			bt_cap_common_clear_active_proc();
+
 			return -EINVAL;
 		}
 
@@ -1941,6 +1990,9 @@ int bt_cap_commander_change_microphone_gain_setting(
 	err = bt_aics_gain_set(proc_param->change_gain.aics, proc_param->change_gain.gain);
 	if (err != 0) {
 		LOG_DBG("Failed to set gain for conn %p: %d", (void *)conn, err);
+
+		bt_cap_common_clear_active_proc();
+
 		return -ENOEXEC;
 	}
 
diff --git a/subsys/bluetooth/audio/cap_common.c b/subsys/bluetooth/audio/cap_common.c
index cd52428eb2b..59845acb6eb 100644
--- a/subsys/bluetooth/audio/cap_common.c
+++ b/subsys/bluetooth/audio/cap_common.c
@@ -43,11 +43,10 @@ void bt_cap_common_clear_active_proc(void)
 	(void)memset(&active_proc, 0, sizeof(active_proc));
 }
 
-void bt_cap_common_start_proc(enum bt_cap_common_proc_type proc_type, size_t proc_cnt)
+void bt_cap_common_set_proc(enum bt_cap_common_proc_type proc_type, size_t proc_cnt)
 {
 	LOG_DBG("Setting proc to %d for %zu streams", proc_type, proc_cnt);
 
-	atomic_set_bit(active_proc.proc_state_flags, BT_CAP_COMMON_PROC_STATE_ACTIVE);
 	active_proc.proc_cnt = proc_cnt;
 	active_proc.proc_type = proc_type;
 	active_proc.proc_done_cnt = 0U;
@@ -100,6 +99,12 @@ struct bt_conn *bt_cap_common_get_member_conn(enum bt_cap_set_type type,
 	return member->member;
 }
 
+bool bt_cap_common_test_and_set_proc_active(void)
+{
+	return atomic_test_and_set_bit(active_proc.proc_state_flags,
+				       BT_CAP_COMMON_PROC_STATE_ACTIVE);
+}
+
 bool bt_cap_common_proc_is_active(void)
 {
 	return atomic_test_bit(active_proc.proc_state_flags, BT_CAP_COMMON_PROC_STATE_ACTIVE);
diff --git a/subsys/bluetooth/audio/cap_initiator.c b/subsys/bluetooth/audio/cap_initiator.c
index 45a4b0b03af..92716c84c24 100644
--- a/subsys/bluetooth/audio/cap_initiator.c
+++ b/subsys/bluetooth/audio/cap_initiator.c
@@ -971,7 +971,7 @@ static int cap_initiator_unicast_audio_configure(
 	/* Store the information about the active procedure so that we can
 	 * continue the procedure after each step
 	 */
-	bt_cap_common_start_proc(BT_CAP_COMMON_PROC_TYPE_START, param->count);
+	bt_cap_common_set_proc(BT_CAP_COMMON_PROC_TYPE_START, param->count);
 	bt_cap_common_set_subproc(BT_CAP_COMMON_SUBPROC_TYPE_CODEC_CONFIG);
 
 	proc_param = get_next_proc_param(active_proc);
@@ -1008,17 +1008,18 @@ static int cap_initiator_unicast_audio_configure(
 int bt_cap_initiator_unicast_audio_start(const struct bt_cap_unicast_audio_start_param *param)
 {
 	bool all_streaming = true;
+	int err;
+
+	if (!valid_unicast_audio_start_param(param)) {
+		return -EINVAL;
+	}
 
-	if (bt_cap_common_proc_is_active()) {
+	if (bt_cap_common_test_and_set_proc_active()) {
 		LOG_DBG("A CAP procedure is already in progress");
 
 		return -EBUSY;
 	}
 
-	if (!valid_unicast_audio_start_param(param)) {
-		return -EINVAL;
-	}
-
 	for (size_t i = 0U; i < param->count; i++) {
 		const struct bt_bap_stream *bap_stream =
 			&param->stream_params[i].stream->bap_stream;
@@ -1030,10 +1031,18 @@ int bt_cap_initiator_unicast_audio_start(const struct bt_cap_unicast_audio_start
 
 	if (all_streaming) {
 		LOG_DBG("All streams are already in the streaming state");
+
+		bt_cap_common_clear_active_proc();
+
 		return -EALREADY;
 	}
 
-	return cap_initiator_unicast_audio_configure(param);
+	err = cap_initiator_unicast_audio_configure(param);
+	if (err != 0) {
+		bt_cap_common_clear_active_proc();
+	}
+
+	return err;
 }
 
 void bt_cap_initiator_codec_configured(struct bt_cap_stream *cap_stream)
@@ -1639,16 +1648,16 @@ int bt_cap_initiator_unicast_audio_update(const struct bt_cap_unicast_audio_upda
 	size_t meta_len;
 	int err;
 
-	if (bt_cap_common_proc_is_active()) {
+	if (!valid_unicast_audio_update_param(param)) {
+		return -EINVAL;
+	}
+
+	if (bt_cap_common_test_and_set_proc_active()) {
 		LOG_DBG("A CAP procedure is already in progress");
 
 		return -EBUSY;
 	}
 
-	if (!valid_unicast_audio_update_param(param)) {
-		return -EINVAL;
-	}
-
 	for (size_t i = 0U; i < param->count; i++) {
 		const struct bt_cap_unicast_audio_update_stream_param *stream_param =
 			&param->stream_params[i];
@@ -1663,7 +1672,7 @@ int bt_cap_initiator_unicast_audio_update(const struct bt_cap_unicast_audio_upda
 		       stream_param->meta_len);
 	}
 
-	bt_cap_common_start_proc(BT_CAP_COMMON_PROC_TYPE_UPDATE, param->count);
+	bt_cap_common_set_proc(BT_CAP_COMMON_PROC_TYPE_UPDATE, param->count);
 	bt_cap_common_set_subproc(BT_CAP_COMMON_SUBPROC_TYPE_META_UPDATE);
 
 	proc_param = get_next_proc_param(active_proc);
@@ -1902,16 +1911,16 @@ int bt_cap_initiator_unicast_audio_stop(const struct bt_cap_unicast_audio_stop_p
 	bool can_stop = false;
 	int err;
 
-	if (bt_cap_common_proc_is_active()) {
+	if (!valid_unicast_audio_stop_param(param)) {
+		return -EINVAL;
+	}
+
+	if (bt_cap_common_test_and_set_proc_active()) {
 		LOG_DBG("A CAP procedure is already in progress");
 
 		return -EBUSY;
 	}
 
-	if (!valid_unicast_audio_stop_param(param)) {
-		return -EINVAL;
-	}
-
 	for (size_t i = 0U; i < param->count; i++) {
 		struct bt_cap_stream *cap_stream = param->streams[i];
 		struct bt_bap_stream *bap_stream = &cap_stream->bap_stream;
@@ -1939,10 +1948,13 @@ int bt_cap_initiator_unicast_audio_stop(const struct bt_cap_unicast_audio_stop_p
 		LOG_DBG("Cannot %s any streams", !can_disable ? "disable"
 						 : !can_stop  ? "stop"
 							      : "release");
+
+		bt_cap_common_clear_active_proc();
+
 		return -EALREADY;
 	}
 
-	bt_cap_common_start_proc(BT_CAP_COMMON_PROC_TYPE_STOP, param->count);
+	bt_cap_common_set_proc(BT_CAP_COMMON_PROC_TYPE_STOP, param->count);
 	/** TODO: If this is a CSIP set, then the order of the procedures may
 	 * not match the order in the parameters, and the CSIP ordered access
 	 * procedure should be used.
diff --git a/subsys/bluetooth/audio/cap_internal.h b/subsys/bluetooth/audio/cap_internal.h
index c83c4af0e94..f6bdb40d6e3 100644
--- a/subsys/bluetooth/audio/cap_internal.h
+++ b/subsys/bluetooth/audio/cap_internal.h
@@ -19,6 +19,7 @@
 #include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gatt.h>
+#include <zephyr/bluetooth/iso.h>
 #include <zephyr/sys/atomic.h>
 #include <zephyr/types.h>
 
@@ -113,7 +114,7 @@ struct cap_broadcast_reception_stop {
 
 /* Note that although the broadcast_code will be the same for all
  * we nevertheless store a separate copy for each sink, for
- * consistensy in the struct bt_cap_commander_proc_param
+ * consistency in the struct bt_cap_commander_proc_param
  * There is no memory savings by not having broadcast_code part of the
  * union: struct cap_broadcast_reception_start uses minimum 20 bytes
  * and struct cap_distribute_broadcast_code uses 17 bytes
@@ -203,12 +204,13 @@ struct bt_cap_common_client {
 
 struct bt_cap_common_proc *bt_cap_common_get_active_proc(void);
 void bt_cap_common_clear_active_proc(void);
-void bt_cap_common_start_proc(enum bt_cap_common_proc_type proc_type, size_t proc_cnt);
+void bt_cap_common_set_proc(enum bt_cap_common_proc_type proc_type, size_t proc_cnt);
 void bt_cap_common_set_subproc(enum bt_cap_common_subproc_type subproc_type);
 bool bt_cap_common_proc_is_type(enum bt_cap_common_proc_type proc_type);
 bool bt_cap_common_subproc_is_type(enum bt_cap_common_subproc_type subproc_type);
 struct bt_conn *bt_cap_common_get_member_conn(enum bt_cap_set_type type,
 					      const union bt_cap_set_member *member);
+bool bt_cap_common_test_and_set_proc_active(void);
 bool bt_cap_common_proc_is_active(void);
 bool bt_cap_common_proc_is_aborted(void);
 bool bt_cap_common_proc_all_handled(void);
diff --git a/subsys/bluetooth/audio/ccp_call_control_client.c b/subsys/bluetooth/audio/ccp_call_control_client.c
new file mode 100644
index 00000000000..ade9f280091
--- /dev/null
+++ b/subsys/bluetooth/audio/ccp_call_control_client.c
@@ -0,0 +1,253 @@
+/* Bluetooth CCP - Call Control Profile Call Control Server
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/audio/tbs.h>
+#include <zephyr/bluetooth/audio/ccp.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/check.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+
+LOG_MODULE_REGISTER(bt_ccp_call_control_client, CONFIG_BT_CCP_CALL_CONTROL_CLIENT_LOG_LEVEL);
+
+static sys_slist_t ccp_call_control_client_cbs =
+	SYS_SLIST_STATIC_INIT(&ccp_call_control_client_cbs);
+
+static struct bt_tbs_client_cb tbs_client_cbs;
+
+/* A service instance can either be a GTBS or a TBS insttance */
+struct bt_ccp_call_control_client_bearer {
+	uint8_t tbs_index;
+	bool discovered;
+};
+
+enum ccp_call_control_client_flag {
+	CCP_CALL_CONTROL_CLIENT_FLAG_BUSY,
+
+	CCP_CALL_CONTROL_CLIENT_FLAG_NUM_FLAGS, /* keep as last */
+};
+
+struct bt_ccp_call_control_client {
+	struct bt_ccp_call_control_client_bearer
+		bearers[CONFIG_BT_CCP_CALL_CONTROL_CLIENT_BEARER_COUNT];
+	struct bt_conn *conn;
+
+	ATOMIC_DEFINE(flags, CCP_CALL_CONTROL_CLIENT_FLAG_NUM_FLAGS);
+};
+
+static struct bt_ccp_call_control_client clients[CONFIG_BT_MAX_CONN];
+
+static struct bt_ccp_call_control_client *get_client_by_conn(const struct bt_conn *conn)
+{
+	return &clients[bt_conn_index(conn)];
+}
+
+static void connected_cb(struct bt_conn *conn, uint8_t err)
+{
+	static bool cbs_registered;
+
+	/* We register the callbacks in the connected callback. That way we ensure that they are
+	 * registered before any procedures are completed or we receive any notifications, while
+	 * registering them as late as possible
+	 */
+	if (err == BT_HCI_ERR_SUCCESS && !cbs_registered) {
+		int cb_err;
+
+		cb_err = bt_tbs_client_register_cb(&tbs_client_cbs);
+		__ASSERT(cb_err == 0, "Failed to register TBS callbacks: %d", cb_err);
+
+		cbs_registered = true;
+	}
+}
+
+static void disconnected_cb(struct bt_conn *conn, uint8_t reason)
+{
+	struct bt_ccp_call_control_client *client = get_client_by_conn(conn);
+
+	/* client->conn may be NULL */
+	if (client->conn == conn) {
+		bt_conn_unref(client->conn);
+		client->conn = NULL;
+	}
+}
+
+BT_CONN_CB_DEFINE(conn_callbacks) = {
+	.connected = connected_cb,
+	.disconnected = disconnected_cb,
+};
+
+static void populate_bearers(struct bt_ccp_call_control_client *client,
+			     struct bt_ccp_call_control_client_bearers *bearers)
+{
+	size_t i = 0;
+
+#if defined(CONFIG_BT_TBS_CLIENT_GTBS)
+	if (client->bearers[i].discovered) {
+		bearers->gtbs_bearer = &client->bearers[i++];
+	}
+#endif /* CONFIG_BT_TBS_CLIENT_GTBS */
+
+#if defined(CONFIG_BT_TBS_CLIENT_TBS)
+	for (; i < ARRAY_SIZE(client->bearers); i++) {
+		if (!client->bearers[i].discovered) {
+			break;
+		}
+
+		bearers->tbs_bearers[bearers->tbs_count++] = &client->bearers[i];
+	}
+#endif /* CONFIG_BT_TBS_CLIENT_TBS */
+}
+
+static void tbs_client_discover_cb(struct bt_conn *conn, int err, uint8_t tbs_count,
+				   bool gtbs_found)
+{
+	struct bt_ccp_call_control_client *client = get_client_by_conn(conn);
+	struct bt_ccp_call_control_client_bearers bearers = {0};
+	struct bt_ccp_call_control_client_cb *listener, *next;
+
+	LOG_DBG("conn %p err %d tbs_count %u gtbs_found %d", (void *)conn, err, tbs_count,
+		gtbs_found);
+
+	memset(client->bearers, 0, sizeof((client->bearers)));
+
+	if (IS_ENABLED(CONFIG_BT_TBS_CLIENT_GTBS) && gtbs_found) {
+		client->bearers[0].discovered = true;
+		client->bearers[0].tbs_index = BT_TBS_GTBS_INDEX;
+	}
+
+	if (IS_ENABLED(CONFIG_BT_TBS_CLIENT_TBS)) {
+		for (uint8_t i = 0U; i < tbs_count; i++) {
+			const uint8_t idx = i + (gtbs_found ? 1 : 0);
+
+			if (idx >= ARRAY_SIZE(client->bearers)) {
+				LOG_WRN("Discoverd more TBS instances (%u) than the CCP Call "
+					"Control Client supports %zu",
+					tbs_count, ARRAY_SIZE(client->bearers));
+				break;
+			}
+
+			client->bearers[idx].discovered = true;
+			client->bearers[idx].tbs_index = i;
+		}
+	}
+
+	populate_bearers(client, &bearers);
+
+	atomic_clear_bit(client->flags, CCP_CALL_CONTROL_CLIENT_FLAG_BUSY);
+
+	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&ccp_call_control_client_cbs, listener, next, _node) {
+		if (listener->discover != NULL) {
+			listener->discover(client, err, &bearers);
+		}
+	}
+}
+
+int bt_ccp_call_control_client_discover(struct bt_conn *conn,
+					struct bt_ccp_call_control_client **out_client)
+{
+	struct bt_ccp_call_control_client *client;
+	int err;
+
+	CHECKIF(conn == NULL) {
+		LOG_DBG("conn is NULL");
+
+		return -EINVAL;
+	}
+
+	CHECKIF(out_client == NULL) {
+		LOG_DBG("client is NULL");
+
+		return -EINVAL;
+	}
+
+	client = get_client_by_conn(conn);
+	if (atomic_test_and_set_bit(client->flags, CCP_CALL_CONTROL_CLIENT_FLAG_BUSY)) {
+		return -EBUSY;
+	}
+
+	tbs_client_cbs.discover = tbs_client_discover_cb;
+
+	err = bt_tbs_client_discover(conn);
+	if (err != 0) {
+		LOG_DBG("Failed to discover TBS for %p: %d", (void *)conn, err);
+
+		atomic_clear_bit(client->flags, CCP_CALL_CONTROL_CLIENT_FLAG_BUSY);
+
+		/* Return known errors */
+		if (err == -EBUSY || err == -ENOTCONN) {
+			return err;
+		}
+
+		return -ENOEXEC;
+	}
+
+	client->conn = bt_conn_ref(conn);
+	*out_client = client;
+
+	return 0;
+}
+
+int bt_ccp_call_control_client_register_cb(struct bt_ccp_call_control_client_cb *cb)
+{
+	CHECKIF(cb == NULL) {
+		LOG_DBG("cb is NULL");
+
+		return -EINVAL;
+	}
+
+	if (sys_slist_find(&ccp_call_control_client_cbs, &cb->_node, NULL)) {
+		return -EEXIST;
+	}
+
+	sys_slist_append(&ccp_call_control_client_cbs, &cb->_node);
+
+	return 0;
+}
+
+int bt_ccp_call_control_client_unregister_cb(struct bt_ccp_call_control_client_cb *cb)
+{
+	CHECKIF(cb == NULL) {
+		LOG_DBG("cb is NULL");
+		return -EINVAL;
+	}
+
+	if (!sys_slist_find_and_remove(&ccp_call_control_client_cbs, &cb->_node)) {
+		return -EALREADY;
+	}
+
+	return 0;
+}
+
+int bt_ccp_call_control_client_get_bearers(struct bt_ccp_call_control_client *client,
+					   struct bt_ccp_call_control_client_bearers *bearers)
+{
+	CHECKIF(client == NULL) {
+		LOG_DBG("client is NULL");
+		return -EINVAL;
+	}
+
+	CHECKIF(bearers == NULL) {
+		LOG_DBG("bearers is NULL");
+		return -EINVAL;
+	}
+
+	memset(bearers, 0, sizeof(*bearers));
+	populate_bearers(client, bearers);
+
+	return 0;
+}
diff --git a/subsys/bluetooth/audio/csip_crypto.c b/subsys/bluetooth/audio/csip_crypto.c
index 08346bed0bd..b46ca984f2b 100644
--- a/subsys/bluetooth/audio/csip_crypto.c
+++ b/subsys/bluetooth/audio/csip_crypto.c
@@ -171,14 +171,8 @@ int bt_csip_sef(const uint8_t k[BT_CSIP_CRYPTO_KEY_SIZE], const uint8_t sirk[BT_
 
 	LOG_DBG("SIRK %s", bt_hex(sirk, BT_CSIP_SIRK_SIZE));
 
-	if (IS_ENABLED(CONFIG_LITTLE_ENDIAN)) {
-		/* Swap because aes_cmac is big endian
-		 * and we are little endian
-		 */
-		sys_memcpy_swap(k1_tmp, k, sizeof(k1_tmp));
-	} else {
-		(void)memcpy(k1_tmp, k, sizeof(k1_tmp));
-	}
+	/* Swap because aes_cmac is big endian and k is little endian */
+	sys_memcpy_swap(k1_tmp, k, sizeof(k1_tmp));
 	LOG_DBG("BE: k %s", bt_hex(k1_tmp, sizeof(k1_tmp)));
 
 	err = s1(m, sizeof(m), s1_out);
@@ -195,10 +189,8 @@ int bt_csip_sef(const uint8_t k[BT_CSIP_CRYPTO_KEY_SIZE], const uint8_t sirk[BT_
 
 	LOG_DBG("BE: k1 result %s", bt_hex(k1_out, sizeof(k1_out)));
 
-	if (IS_ENABLED(CONFIG_LITTLE_ENDIAN)) {
-		/* Swap result back to little endian */
-		sys_mem_swap(k1_out, sizeof(k1_out));
-	}
+	/* Get result back to little endian. */
+	sys_mem_swap(k1_out, sizeof(k1_out));
 
 	mem_xor_128(out_sirk, k1_out, sirk);
 	LOG_DBG("out %s", bt_hex(out_sirk, BT_CSIP_SIRK_SIZE));
diff --git a/subsys/bluetooth/audio/csip_crypto.h b/subsys/bluetooth/audio/csip_crypto.h
index b522eb94a98..bc547988ec8 100644
--- a/subsys/bluetooth/audio/csip_crypto.h
+++ b/subsys/bluetooth/audio/csip_crypto.h
@@ -22,9 +22,10 @@
  * used in RSIs - Used by the Coordinated Set Identification service and
  * profile.
  *
- * @param sirk  16 byte LS byte first SIRK
- * @param r     3 byte LS byte first random value
- * @param out   3 byte LS byte first output buffer
+ * @param sirk  16-byte SIRK in little-endian byte order.
+ * @param r     3-byte random value in little-endian byte order.
+ * @param out   3-byte output buffer in little-endian byte order.
+ *
  * @return int 0 on success, any other value indicates a failure.
  */
 int bt_csip_sih(const uint8_t sirk[BT_CSIP_SIRK_SIZE], uint8_t r[BT_CSIP_CRYPTO_PRAND_SIZE],
@@ -37,20 +38,18 @@ int bt_csip_sih(const uint8_t sirk[BT_CSIP_SIRK_SIZE], uint8_t r[BT_CSIP_CRYPTO_
  * with a key K. The value of K depends on the transport on which the pairing
  * between the client and the server was performed.
  *
- * If the pairing was performed on BR/EDR, K is equal to the Link Key shared by
- * the server and the client.
+ * If the pairing was performed on Basic Rate/Enhanced Data Rate (BR/EDR), K is equal to the
+ * Link Key shared by the server and the client.
  *    K = Link Key.
  *
- * If the pairing was performed on LE, the 64 LSBs of K correspond to the 64
- * LSBs of the IRK that the server sent to the client during the Phase 3
- * (Transport Specific Key Distribution) of the pairing procedure (see Volume 3,
- * Part H, Section 2.1 in [2]), and the 64 MSBs of K correspond to the 64 MSBs
- * of the LTK shared by the server and client. That is,
- *    K = LTK_64-127 || IRK_0-63
+ * If the pairing was performed on Bluetooth Low Energy (LE), K is equal to the LTK shared by the
+ * server and client. That is,
+ *    K = LTK
+ *
+ * @param k         16-byte key in little-endian byte order.
+ * @param sirk      16-byte unencrypted SIRK key in little-endian byte order.
+ * @param out_sirk  16-byte encrypted SIRK key in little-endian byte order.
  *
- * @param k         16-byte key.
- * @param sirk      The unencrypted SIRK.
- * @param out_sirk  The encrypted SIRK.
  * @return int 0 on success, any other value indicates a failure.
  */
 int bt_csip_sef(const uint8_t k[BT_CSIP_CRYPTO_KEY_SIZE], const uint8_t sirk[BT_CSIP_SIRK_SIZE],
@@ -63,20 +62,18 @@ int bt_csip_sef(const uint8_t k[BT_CSIP_CRYPTO_KEY_SIZE], const uint8_t sirk[BT_
  * with a key K. The value of K depends on the transport on which the pairing
  * between the client and the server was performed.
  *
- * If the pairing was performed on BR/EDR, K is equal to the Link Key shared by
- * the server and the client.
+ * If the pairing was performed on Basic Rate/Enhanced Data Rate (BR/EDR), K is equal to the
+ * Link Key shared by the server and the client.
  *    K = Link Key.
  *
- * If the pairing was performed on LE, the 64 LSBs of K correspond to the 64
- * LSBs of the IRK that the server sent to the client during the Phase 3
- * (Transport Specific Key Distribution) of the pairing procedure (see Volume 3,
- * Part H, Section 2.1 in [2]), and the 64 MSBs of K correspond to the 64 MSBs
- * of the LTK shared by the server and client. That is,
- *    K = LTK_64-127 || IRK_0-63
+ * If the pairing was performed on Bluetooth Low Energy (LE), K is equal to the LTK shared by the
+ * server and client. That is,
+ *    K = LTK
+ *
+ * @param k         16-byte key in little-endian byte order.
+ * @param sirk      16-byte encrypted SIRK in little-endian byte order.
+ * @param out_sirk  16-byte decrypted SIRK in little-endian byte order.
  *
- * @param k         16-byte key.
- * @param sirk      The encrypted SIRK.
- * @param out_sirk  The decrypted SIRK.
  * @return int 0 on success, any other value indicates a failure.
  */
 int bt_csip_sdf(const uint8_t k[BT_CSIP_CRYPTO_KEY_SIZE], const uint8_t enc_sirk[BT_CSIP_SIRK_SIZE],
diff --git a/subsys/bluetooth/audio/csip_internal.h b/subsys/bluetooth/audio/csip_internal.h
index 0ac61f335c0..8cf6c7f7d07 100644
--- a/subsys/bluetooth/audio/csip_internal.h
+++ b/subsys/bluetooth/audio/csip_internal.h
@@ -21,6 +21,7 @@
 
 struct bt_csip_sirk {
 	uint8_t type;
+	/* SIRK stored in little endian byte order. */
 	uint8_t value[BT_CSIP_SIRK_SIZE];
 } __packed;
 
diff --git a/subsys/bluetooth/audio/csip_set_coordinator.c b/subsys/bluetooth/audio/csip_set_coordinator.c
index e5f29b9526c..d1801f5eaf2 100644
--- a/subsys/bluetooth/audio/csip_set_coordinator.c
+++ b/subsys/bluetooth/audio/csip_set_coordinator.c
@@ -52,7 +52,6 @@
 #include "common/bt_str.h"
 #include "host/conn_internal.h"
 #include "host/keys.h"
-#include "host/hci_core.h"
 
 LOG_MODULE_REGISTER(bt_csip_set_coordinator, CONFIG_BT_CSIP_SET_COORDINATOR_LOG_LEVEL);
 
@@ -266,23 +265,19 @@ static int sirk_decrypt(struct bt_conn *conn,
 			uint8_t *out_sirk)
 {
 	int err;
-	uint8_t *k;
+	const uint8_t *k;
 
 	if (IS_ENABLED(CONFIG_BT_CSIP_SET_COORDINATOR_TEST_SAMPLE_DATA)) {
 		/* test_k is from the sample data from A.2 in the CSIS spec */
-		static uint8_t test_k[] = {0x67, 0x6e, 0x1b, 0x9b,
-					   0xd4, 0x48, 0x69, 0x6f,
-					   0x06, 0x1e, 0xc6, 0x22,
-					   0x3c, 0xe5, 0xce, 0xd9};
-		static bool swapped;
+		static const uint8_t test_k[] = {
+			/* Sample data is in big-endian, we need it in little-endian. */
+			REVERSE_ARGS(0x67, 0x6e, 0x1b, 0x9b,
+				     0xd4, 0x48, 0x69, 0x6f,
+				     0x06, 0x1e, 0xc6, 0x22,
+				     0x3c, 0xe5, 0xce, 0xd9) };
 
 		LOG_DBG("Decrypting with sample data K");
 
-		if (!swapped && IS_ENABLED(CONFIG_LITTLE_ENDIAN)) {
-			/* Swap test_k to little endian */
-			sys_mem_swap(test_k, 16);
-			swapped = true;
-		}
 		k = test_k;
 	} else {
 		k = conn->le.keys->ltk.val;
@@ -1691,7 +1686,7 @@ static bool all_members_bonded(const struct bt_csip_set_coordinator_set_member *
 		int err;
 
 		err = bt_conn_get_info(client->conn, &info);
-		if (err != 0 || !bt_addr_le_is_bonded(info.id, info.le.dst)) {
+		if (err != 0 || !bt_le_bond_exists(info.id, info.le.dst)) {
 			LOG_DBG("Member[%zu] is not bonded", i);
 
 			return false;
diff --git a/subsys/bluetooth/audio/csip_set_member.c b/subsys/bluetooth/audio/csip_set_member.c
index d86d54c2d63..ab7008214a2 100644
--- a/subsys/bluetooth/audio/csip_set_member.c
+++ b/subsys/bluetooth/audio/csip_set_member.c
@@ -38,8 +38,8 @@
 #include <zephyr/sys/check.h>
 
 #include "../host/conn_internal.h"
-#include "../host/hci_core.h"
 #include "../host/keys.h"
+#include "../host/settings.h"
 
 #include "common/bt_str.h"
 #include "audio_internal.h"
@@ -79,11 +79,32 @@ struct bt_csip_set_member_svc_inst {
 	bt_addr_le_t lock_client_addr;
 	struct bt_gatt_service *service_p;
 	struct csip_client clients[CONFIG_BT_MAX_PAIRED];
+	/* Must be last: exclude from memset during unregister */
+	struct k_mutex mutex;
 };
 
 static struct bt_csip_set_member_svc_inst svc_insts[CONFIG_BT_CSIP_SET_MEMBER_MAX_INSTANCE_COUNT];
 
 static void deferred_nfy_work_handler(struct k_work *work);
+static void add_bonded_addr_to_client_list(const struct bt_bond_info *info, void *data);
+
+#if defined(CONFIG_BT_SETTINGS)
+static int csip_settings_commit(void)
+{
+	bt_foreach_bond(BT_ID_DEFAULT, add_bonded_addr_to_client_list, NULL);
+
+	LOG_DBG("Restored CSIP client list from bonded devices");
+
+	return 0;
+}
+
+/* Register CSIP settings handler with commit priority, BT_SETTINGS_CPRIO_2,
+ * to ensure csip_settings_commit() runs after BT keys settings are loaded.
+ * Priority is reduced to ensure existing bonds are loaded first.
+ */
+SETTINGS_STATIC_HANDLER_DEFINE_WITH_CPRIO(bt_csip_set_member, "bt/csip", NULL, NULL,
+					csip_settings_commit, NULL, BT_SETTINGS_CPRIO_2);
+#endif /* CONFIG_BT_SETTINGS */
 
 static K_WORK_DELAYABLE_DEFINE(deferred_nfy_work, deferred_nfy_work_handler);
 
@@ -145,21 +166,16 @@ static int sirk_encrypt(struct bt_conn *conn, const struct bt_csip_sirk *sirk,
 			struct bt_csip_sirk *enc_sirk)
 {
 	int err;
-	uint8_t *k;
+	const uint8_t *k;
 
 	if (IS_ENABLED(CONFIG_BT_CSIP_SET_MEMBER_TEST_SAMPLE_DATA)) {
 		/* test_k is from the sample data from A.2 in the CSIS spec */
-		static uint8_t test_k[] = {0x67, 0x6e, 0x1b, 0x9b,
-					   0xd4, 0x48, 0x69, 0x6f,
-					   0x06, 0x1e, 0xc6, 0x22,
-					   0x3c, 0xe5, 0xce, 0xd9};
-		static bool swapped;
-
-		if (!swapped && IS_ENABLED(CONFIG_LITTLE_ENDIAN)) {
-			/* Swap test_k to little endian */
-			sys_mem_swap(test_k, 16);
-			swapped = true;
-		}
+		static const uint8_t test_k[] = {
+			/* Sample data is in big-endian, we need it in little-endian. */
++                       REVERSE_ARGS(0x67, 0x6e, 0x1b, 0x9b,
+				     0xd4, 0x48, 0x69, 0x6f,
+				     0x06, 0x1e, 0xc6, 0x22,
+				     0x3c, 0xe5, 0xce, 0xd9) };
 		LOG_DBG("Encrypting test SIRK");
 		k = test_k;
 	} else {
@@ -466,28 +482,49 @@ static void set_lock_timer_handler(struct k_work *work)
 static void csip_security_changed(struct bt_conn *conn, bt_security_t level,
 				  enum bt_security_err err)
 {
+	const bt_addr_le_t *peer_addr;
+
 	if (err != 0 || conn->encrypt == 0) {
 		return;
 	}
 
-	if (!bt_addr_le_is_bonded(conn->id, &conn->le.dst)) {
+	peer_addr = bt_conn_get_dst(conn);
+
+	if (!bt_le_bond_exists(conn->id, &conn->le.dst)) {
 		return;
 	}
 
 	for (size_t i = 0U; i < ARRAY_SIZE(svc_insts); i++) {
 		struct bt_csip_set_member_svc_inst *svc_inst = &svc_insts[i];
+		struct csip_client *client;
+		bool found = false;
 
+		/* Check if client is already in the active list */
 		for (size_t j = 0U; j < ARRAY_SIZE(svc_inst->clients); j++) {
-			struct csip_client *client;
-
-			client = &svc_inst->clients[i];
+			client = &svc_inst->clients[j];
 
-			if (atomic_test_bit(client->flags, FLAG_NOTIFY_LOCK) &&
-			    bt_addr_le_eq(bt_conn_get_dst(conn), &client->addr)) {
-				notify_work_reschedule(K_NO_WAIT);
+			if (atomic_test_bit(client->flags, FLAG_ACTIVE) &&
+			    bt_addr_le_eq(peer_addr, &client->addr)) {
+				found = true;
 				break;
 			}
 		}
+
+		/* If not found, add the bonded address to the client list */
+		if (!found) {
+			const struct bt_bond_info bond_info = {
+				.addr = *peer_addr
+			};
+
+			add_bonded_addr_to_client_list(&bond_info, NULL);
+			return;
+		}
+
+		/* Check if client is set with FLAG_NOTIFY_LOCK */
+		if (atomic_test_bit(client->flags, FLAG_NOTIFY_LOCK)) {
+			notify_work_reschedule(K_NO_WAIT);
+			break;
+		}
 	}
 }
 
@@ -526,7 +563,7 @@ static void csip_disconnected(struct bt_conn *conn, uint8_t reason)
 {
 	LOG_DBG("Disconnected: %s (reason %u)", bt_addr_le_str(bt_conn_get_dst(conn)), reason);
 
-	if (!bt_addr_le_is_bonded(conn->id, &conn->le.dst)) {
+	if (!bt_le_bond_exists(conn->id, &conn->le.dst)) {
 		for (size_t i = 0U; i < ARRAY_SIZE(svc_insts); i++) {
 			handle_csip_disconnect(&svc_insts[i], conn);
 		}
@@ -742,12 +779,24 @@ static void notify(struct bt_csip_set_member_svc_inst *svc_inst, struct bt_conn
 		   const struct bt_uuid *uuid, const void *data, uint16_t len)
 {
 	int err;
+	const struct bt_gatt_attr *attr;
+
+	attr = bt_gatt_find_by_uuid(
+		svc_inst->service_p->attrs,
+		svc_inst->service_p->attr_count,
+		uuid);
+
+	if (attr == NULL) {
+		LOG_WRN("Attribute for UUID %p not found", uuid);
+		return;
+	}
 
-	if (svc_inst->service_p == NULL) {
+	if (!bt_gatt_is_subscribed(conn, attr, BT_GATT_CCC_NOTIFY)) {
+		LOG_DBG("Connection %p not subscribed to UUID %p", conn, uuid);
 		return;
 	}
 
-	err = bt_gatt_notify_uuid(conn, uuid, svc_inst->service_p->attrs, data, len);
+	err = bt_gatt_notify(conn, attr, data, len);
 	if (err) {
 		if (err == -ENOTCONN) {
 			LOG_DBG("Notification error: ENOTCONN (%d)", err);
@@ -775,7 +824,35 @@ static void notify_cb(struct bt_conn *conn, void *data)
 
 	for (size_t i = 0U; i < ARRAY_SIZE(svc_insts); i++) {
 		struct bt_csip_set_member_svc_inst *svc_inst = &svc_insts[i];
-		struct csip_client *client = &svc_inst->clients[bt_conn_index(conn)];
+		struct csip_client *client;
+		bool client_found = false;
+
+		err = k_mutex_lock(&svc_inst->mutex, K_NO_WAIT);
+		if (err != 0) {
+			LOG_DBG("Mutex lock failed (%d) for svc_inst[%zu], rescheduling", err, i);
+			notify_work_reschedule(K_USEC(BT_AUDIO_NOTIFY_RETRY_DELAY_US));
+			continue;
+		}
+
+		if (svc_inst->service_p == NULL || svc_inst->service_p->attrs == NULL) {
+			goto unlock_and_return;
+		}
+
+		/* find the client object for the connection */
+		for (size_t j = 0U; j < ARRAY_SIZE(svc_inst->clients); j++) {
+
+			client = &svc_inst->clients[j];
+
+			if (atomic_test_bit(client->flags, FLAG_ACTIVE) &&
+			    bt_addr_le_eq(bt_conn_get_dst(conn), &client->addr)) {
+				client_found = true;
+				break;
+			}
+		}
+
+		if (client_found == false) {
+			goto unlock_and_return;
+		}
 
 		if (atomic_test_and_clear_bit(client->flags, FLAG_NOTIFY_LOCK)) {
 			notify(svc_inst, conn, BT_UUID_CSIS_SET_LOCK, &svc_inst->set_lock,
@@ -793,6 +870,10 @@ static void notify_cb(struct bt_conn *conn, void *data)
 			notify(svc_inst, conn, BT_UUID_CSIS_SET_SIZE, &svc_inst->set_size,
 			       sizeof(svc_inst->set_size));
 		}
+
+unlock_and_return:
+		err = k_mutex_unlock(&svc_inst->mutex);
+		__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
 	}
 }
 
@@ -807,7 +888,7 @@ static void add_bonded_addr_to_client_list(const struct bt_bond_info *info, void
 	for (size_t i = 0U; i < ARRAY_SIZE(svc_insts); i++) {
 		struct bt_csip_set_member_svc_inst *svc_inst = &svc_insts[i];
 
-		for (size_t j = 1U; j < ARRAY_SIZE(svc_inst->clients); i++) {
+		for (size_t j = 0U; j < ARRAY_SIZE(svc_inst->clients); j++) {
 			/* Check if device is registered, it not, add it */
 			if (!atomic_test_bit(svc_inst->clients[j].flags, FLAG_ACTIVE)) {
 				char addr_str[BT_ADDR_LE_STR_LEN];
@@ -847,20 +928,25 @@ int bt_csip_set_member_register(const struct bt_csip_set_member_register_param *
 		return -EINVAL;
 	}
 
-	inst = &svc_insts[instance_cnt];
-	inst->service_p = &csip_set_member_service_list[instance_cnt];
-	instance_cnt++;
-
 	if (!first_register) {
+		for (size_t i = 0U; i < ARRAY_SIZE(svc_insts); i++) {
+			k_mutex_init(&svc_insts[i].mutex);
+		}
 		bt_conn_cb_register(&conn_callbacks);
 		bt_conn_auth_info_cb_register(&auth_callbacks);
+		first_register = true;
+	}
 
-		/* Restore bonding list */
-		bt_foreach_bond(BT_ID_DEFAULT, add_bonded_addr_to_client_list, NULL);
+	inst = &svc_insts[instance_cnt];
 
-		first_register = true;
+	err = k_mutex_lock(&inst->mutex, K_NO_WAIT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex: %d", err);
+		return -EBUSY;
 	}
 
+	inst->service_p = &csip_set_member_service_list[instance_cnt];
+
 	/* The removal of the optional characteristics should be done in reverse order of the order
 	 * in BT_CSIP_SERVICE_DEFINITION, as that improves the performance of remove_csis_char,
 	 * since it's easier to remove the last characteristic
@@ -879,10 +965,15 @@ int bt_csip_set_member_register(const struct bt_csip_set_member_register_param *
 
 	err = bt_gatt_service_register(inst->service_p);
 	if (err != 0) {
+		int mutex_err;
+
 		LOG_DBG("CSIS service register failed: %d", err);
+		mutex_err = k_mutex_unlock(&inst->mutex);
+		__ASSERT(mutex_err == 0, "Failed to unlock mutex: %d", mutex_err);
 		return err;
 	}
 
+	instance_cnt++;
 	k_work_init_delayable(&inst->set_lock_timer,
 			      set_lock_timer_handler);
 	inst->rank = param->rank;
@@ -906,6 +997,10 @@ int bt_csip_set_member_register(const struct bt_csip_set_member_register_param *
 	}
 
 	*svc_inst = inst;
+
+	err = k_mutex_unlock(&inst->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
 	return 0;
 }
 
@@ -918,14 +1013,29 @@ int bt_csip_set_member_unregister(struct bt_csip_set_member_svc_inst *svc_inst)
 		return -EINVAL;
 	}
 
+	err = k_mutex_lock(&svc_inst->mutex, K_NO_WAIT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex");
+		return -EBUSY;
+	}
+
 	err = bt_gatt_service_unregister(svc_inst->service_p);
 	if (err != 0) {
+		int mutex_err;
+
 		LOG_DBG("CSIS service unregister failed: %d", err);
+		mutex_err = k_mutex_unlock(&svc_inst->mutex);
+		__ASSERT(mutex_err == 0, "Failed to unlock mutex: %d", mutex_err);
+
 		return err;
 	}
 
 	(void)k_work_cancel_delayable(&svc_inst->set_lock_timer);
-	memset(svc_inst, 0, sizeof(*svc_inst));
+
+	memset(svc_inst, 0, offsetof(struct bt_csip_set_member_svc_inst, mutex));
+
+	err = k_mutex_unlock(&svc_inst->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
 
 	return 0;
 }
diff --git a/subsys/bluetooth/audio/has.c b/subsys/bluetooth/audio/has.c
index ad72904ec43..2cdc8bbe544 100644
--- a/subsys/bluetooth/audio/has.c
+++ b/subsys/bluetooth/audio/has.c
@@ -34,7 +34,6 @@
 #include <zephyr/sys_clock.h>
 #include <zephyr/toolchain.h>
 
-#include "../bluetooth/host/hci_core.h"
 #include "../bluetooth/host/settings.h"
 
 #include "audio_internal.h"
@@ -270,7 +269,7 @@ static void client_free(struct has_client *client)
 	err = bt_conn_get_info(client->conn, &info);
 	__ASSERT_NO_MSG(err == 0);
 
-	if (client->context != NULL && !bt_addr_le_is_bonded(info.id, info.le.dst)) {
+	if (client->context != NULL && !bt_le_bond_exists(info.id, info.le.dst)) {
 		/* Free stored context of non-bonded client */
 		context_free(client->context);
 		client->context = NULL;
@@ -383,7 +382,7 @@ static void security_changed(struct bt_conn *conn, bt_security_t level, enum bt_
 		return;
 	}
 
-	if (!bt_addr_le_is_bonded(info.id, info.le.dst)) {
+	if (!bt_le_bond_exists(info.id, info.le.dst)) {
 		return;
 	}
 
@@ -750,13 +749,11 @@ static void control_point_ind_complete(struct bt_conn *conn,
 
 static int control_point_send(struct has_client *client, struct net_buf_simple *buf)
 {
-	const uint16_t mtu_size = bt_gatt_get_mtu(client->conn);
-	/* PDU structure is [Opcode (1)] [Handle (2)] [...] */
-	const uint16_t pdu_size = 3 + buf->len;
+	const uint16_t max_ntf_size = bt_audio_get_max_ntf_size(client->conn);
 
-	if (mtu_size < pdu_size) {
-		LOG_WRN("Sending truncated control point PDU %d < %d", mtu_size, pdu_size);
-		buf->len -= (pdu_size - mtu_size);
+	if (max_ntf_size < buf->len) {
+		LOG_WRN("Sending truncated control point PDU %u < %u", max_ntf_size, buf->len);
+		buf->len = max_ntf_size;
 	}
 
 #if defined(CONFIG_BT_HAS_PRESET_CONTROL_POINT_NOTIFIABLE)
@@ -778,6 +775,7 @@ static int control_point_send(struct has_client *client, struct net_buf_simple *
 		client->params.ind.func = control_point_ind_complete;
 		client->params.ind.destroy = NULL;
 		client->params.ind.data = buf->data;
+		/* indications have same size as notifications */
 		client->params.ind.len = buf->len;
 
 		return bt_gatt_indicate(client->conn, &client->params.ind);
diff --git a/subsys/bluetooth/audio/mcs.c b/subsys/bluetooth/audio/mcs.c
index d0eb2f7658b..4120812af4e 100644
--- a/subsys/bluetooth/audio/mcs.c
+++ b/subsys/bluetooth/audio/mcs.c
@@ -985,18 +985,12 @@ static void notify(const struct bt_uuid *uuid, const void *data, uint16_t len)
 
 static void notify_string(struct bt_conn *conn, const struct bt_uuid *uuid, const char *str)
 {
-	const uint8_t att_header_size = 3; /* opcode + handle */
-	uint16_t att_mtu;
-	uint16_t maxlen;
+	const uint16_t max_ntf_size = bt_audio_get_max_ntf_size(conn);
 	int err;
 
-	att_mtu = bt_gatt_get_mtu(conn);
-	__ASSERT(att_mtu > att_header_size, "Could not get valid ATT MTU");
-	maxlen = att_mtu - att_header_size; /* Subtract opcode and handle */
-
 	/* Send notification potentially truncated to the MTU */
 	err = bt_gatt_notify_uuid(conn, uuid, mcs.attrs, (void *)str,
-				  MIN(strlen(str), maxlen));
+				  MIN(strlen(str), max_ntf_size));
 	if (err != 0) {
 		LOG_ERR("Notification error: %d", err);
 	}
diff --git a/subsys/bluetooth/audio/pacs.c b/subsys/bluetooth/audio/pacs.c
index 30e5d64d9a4..05d3a374188 100644
--- a/subsys/bluetooth/audio/pacs.c
+++ b/subsys/bluetooth/audio/pacs.c
@@ -25,7 +25,6 @@
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gatt.h>
 #include <zephyr/bluetooth/uuid.h>
-#include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
@@ -38,8 +37,6 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/sys/util_macro.h>
 
-#include "../host/conn_internal.h"
-#include "../host/hci_core.h"
 #include "common/bt_str.h"
 
 #include "audio_internal.h"
@@ -52,15 +49,19 @@ LOG_MODULE_REGISTER(bt_pacs, CONFIG_BT_PACS_LOG_LEVEL);
 #define READ_BUF_SEM_TIMEOUT    K_MSEC(50)
 
 #if defined(CONFIG_BT_PAC_SRC)
-static uint32_t pacs_src_location;
-static sys_slist_t src_pacs_list = SYS_SLIST_STATIC_INIT(&src_pacs_list);
+static sys_slist_t src_pac_list = SYS_SLIST_STATIC_INIT(&src_pac_list);
 static uint16_t src_supported_contexts;
+#if defined(CONFIG_BT_PAC_SRC_LOC)
+static uint32_t pacs_src_location;
+#endif /* CONFIG_BT_PAC_SRC_LOC */
 #endif /* CONFIG_BT_PAC_SRC */
 
 #if defined(CONFIG_BT_PAC_SNK)
-static uint32_t pacs_snk_location;
-static sys_slist_t snk_pacs_list = SYS_SLIST_STATIC_INIT(&snk_pacs_list);
+static sys_slist_t snk_pac_list = SYS_SLIST_STATIC_INIT(&snk_pac_list);
 static uint16_t snk_supported_contexts;
+#if defined(CONFIG_BT_PAC_SNK_LOC)
+static uint32_t pacs_snk_location;
+#endif /* CONFIG_BT_PAC_SNK_LOC */
 #endif /* CONFIG_BT_PAC_SNK */
 
 static uint16_t src_available_contexts = BT_AUDIO_CONTEXT_TYPE_PROHIBITED;
@@ -77,7 +78,18 @@ enum {
 	FLAG_NUM,
 };
 
-static struct pacs_client {
+enum {
+	PACS_FLAG_REGISTERED,
+	PACS_FLAG_SVC_CHANGING,
+	PACS_FLAG_NOTIFY_RDY,
+	PACS_FLAG_SNK_PAC,
+	PACS_FLAG_SNK_LOC,
+	PACS_FLAG_SRC_PAC,
+	PACS_FLAG_SRC_LOC,
+	PACS_FLAG_NUM,
+};
+
+struct pacs_client {
 	bt_addr_le_t addr;
 
 #if defined(CONFIG_BT_PAC_SNK)
@@ -92,9 +104,14 @@ static struct pacs_client {
 
 	/* Pending notification flags */
 	ATOMIC_DEFINE(flags, FLAG_NUM);
-} clients[CONFIG_BT_MAX_PAIRED];
+};
+
+static struct pacs {
+	ATOMIC_DEFINE(flags, PACS_FLAG_NUM);
+
+	struct pacs_client clients[CONFIG_BT_MAX_PAIRED];
+} pacs;
 
-static atomic_t notify_rdy;
 
 static K_SEM_DEFINE(read_buf_sem, 1, 1);
 NET_BUF_SIMPLE_DEFINE_STATIC(read_buf, BT_ATT_MAX_ATTRIBUTE_LEN);
@@ -117,10 +134,10 @@ static struct pacs_client *client_lookup_conn(const struct bt_conn *conn)
 {
 	__ASSERT_NO_MSG(conn != NULL);
 
-	for (size_t i = 0; i < ARRAY_SIZE(clients); i++) {
-		if (atomic_test_bit(clients[i].flags, FLAG_ACTIVE) &&
-		    bt_addr_le_eq(&clients[i].addr, bt_conn_get_dst(conn))) {
-			return &clients[i];
+	for (size_t i = 0; i < ARRAY_SIZE(pacs.clients); i++) {
+		if (atomic_test_bit(pacs.clients[i].flags, FLAG_ACTIVE) &&
+		    bt_addr_le_eq(&pacs.clients[i].addr, bt_conn_get_dst(conn))) {
+			return &pacs.clients[i];
 		}
 	}
 
@@ -129,9 +146,9 @@ static struct pacs_client *client_lookup_conn(const struct bt_conn *conn)
 
 static void pacs_set_notify_bit(int bit)
 {
-	for (size_t i = 0U; i < ARRAY_SIZE(clients); i++) {
-		if (atomic_test_bit(clients[i].flags, FLAG_ACTIVE)) {
-			atomic_set_bit(clients[i].flags, bit);
+	for (size_t i = 0U; i < ARRAY_SIZE(pacs.clients); i++) {
+		if (atomic_test_bit(pacs.clients[i].flags, FLAG_ACTIVE)) {
+			atomic_set_bit(pacs.clients[i].flags, bit);
 		}
 	}
 }
@@ -226,14 +243,16 @@ static enum bt_audio_context pacs_get_available_contexts_for_conn(struct bt_conn
 	switch (dir) {
 	case BT_AUDIO_DIR_SINK:
 #if defined(CONFIG_BT_PAC_SNK)
-		if (client->snk_available_contexts != NULL) {
+		if (atomic_test_bit(pacs.flags, PACS_FLAG_SNK_PAC) &&
+		    client->snk_available_contexts != NULL) {
 			return POINTER_TO_UINT(client->snk_available_contexts);
 		}
 #endif /* CONFIG_BT_PAC_SNK */
 		break;
 	case BT_AUDIO_DIR_SOURCE:
 #if defined(CONFIG_BT_PAC_SRC)
-		if (client->src_available_contexts != NULL) {
+		if (atomic_test_bit(pacs.flags, PACS_FLAG_SRC_PAC) &&
+		    client->src_available_contexts != NULL) {
 			return POINTER_TO_UINT(client->src_available_contexts);
 		}
 #endif /* CONFIG_BT_PAC_SRC */
@@ -254,7 +273,7 @@ static ssize_t available_contexts_read(struct bt_conn *conn,
 			pacs_get_available_contexts_for_conn(conn, BT_AUDIO_DIR_SOURCE)),
 	};
 
-	LOG_DBG("conn %p attr %p buf %p len %u offset %u", conn, attr, buf, len, offset);
+	LOG_DBG("conn %p attr %p buf %p len %u offset %u", (void *)conn, attr, buf, len, offset);
 
 	return bt_gatt_attr_read(conn, attr, buf, len, offset, &context,
 				 sizeof(context));
@@ -273,11 +292,17 @@ static uint16_t supported_context_get(enum bt_audio_dir dir)
 	switch (dir) {
 #if defined(CONFIG_BT_PAC_SNK)
 	case BT_AUDIO_DIR_SINK:
-		return snk_supported_contexts | BT_AUDIO_CONTEXT_TYPE_UNSPECIFIED;
+		if (atomic_test_bit(pacs.flags, PACS_FLAG_SNK_PAC)) {
+			return snk_supported_contexts | BT_AUDIO_CONTEXT_TYPE_UNSPECIFIED;
+		}
+		break;
 #endif /* CONFIG_BT_PAC_SNK */
 #if defined(CONFIG_BT_PAC_SRC)
 	case BT_AUDIO_DIR_SOURCE:
-		return src_supported_contexts | BT_AUDIO_CONTEXT_TYPE_UNSPECIFIED;
+		if (atomic_test_bit(pacs.flags, PACS_FLAG_SRC_PAC)) {
+			return src_supported_contexts | BT_AUDIO_CONTEXT_TYPE_UNSPECIFIED;
+		}
+		break;
 #endif /* CONFIG_BT_PAC_SRC */
 	default:
 		break;
@@ -295,7 +320,7 @@ static ssize_t supported_context_read(struct bt_conn *conn,
 		.src = sys_cpu_to_le16(supported_context_get(BT_AUDIO_DIR_SOURCE)),
 	};
 
-	LOG_DBG("conn %p attr %p buf %p len %u offset %u", conn, attr, buf, len, offset);
+	LOG_DBG("conn %p attr %p buf %p len %u offset %u", (void *)conn, attr, buf, len, offset);
 
 	return bt_gatt_attr_read(conn, attr, buf, len, offset, &context,
 				 sizeof(context));
@@ -362,7 +387,7 @@ static ssize_t snk_read(struct bt_conn *conn, const struct bt_gatt_attr *attr,
 	ssize_t ret_val;
 	int err;
 
-	LOG_DBG("conn %p attr %p buf %p len %u offset %u", conn, attr, buf, len, offset);
+	LOG_DBG("conn %p attr %p buf %p len %u offset %u", (void *)conn, attr, buf, len, offset);
 
 	err = k_sem_take(&read_buf_sem, READ_BUF_SEM_TIMEOUT);
 	if (err != 0) {
@@ -371,7 +396,7 @@ static ssize_t snk_read(struct bt_conn *conn, const struct bt_gatt_attr *attr,
 		return BT_GATT_ERR(BT_ATT_ERR_INSUFFICIENT_RESOURCES);
 	}
 
-	get_pac_records(&snk_pacs_list, &read_buf);
+	get_pac_records(&snk_pac_list, &read_buf);
 
 	ret_val = bt_gatt_attr_read(conn, attr, buf, len, offset, read_buf.data,
 				    read_buf.len);
@@ -398,7 +423,7 @@ static ssize_t snk_loc_read(struct bt_conn *conn,
 {
 	uint32_t location = sys_cpu_to_le32(pacs_snk_location);
 
-	LOG_DBG("conn %p attr %p buf %p len %u offset %u", conn, attr, buf, len, offset);
+	LOG_DBG("conn %p attr %p buf %p len %u offset %u", (void *)conn, attr, buf, len, offset);
 
 	return bt_gatt_attr_read(conn, attr, buf, len, offset, &location,
 				 sizeof(location));
@@ -415,15 +440,17 @@ static void snk_loc_cfg_changed(const struct bt_gatt_attr *attr, uint16_t value)
 
 static void set_snk_location(enum bt_audio_location audio_location)
 {
-	if (audio_location == pacs_snk_location) {
-		return;
-	}
+	if (atomic_test_bit(pacs.flags, PACS_FLAG_SNK_LOC)) {
+		if (audio_location == pacs_snk_location) {
+			return;
+		}
 
-	pacs_snk_location = audio_location;
+		pacs_snk_location = audio_location;
 
-	if (IS_ENABLED(CONFIG_BT_PAC_SNK_LOC_NOTIFIABLE)) {
-		pacs_set_notify_bit(FLAG_SINK_AUDIO_LOCATIONS_CHANGED);
-		k_work_submit(&deferred_nfy_work);
+		if (IS_ENABLED(CONFIG_BT_PAC_SNK_LOC_NOTIFIABLE)) {
+			pacs_set_notify_bit(FLAG_SINK_AUDIO_LOCATIONS_CHANGED);
+			k_work_submit(&deferred_nfy_work);
+		}
 	}
 }
 #else
@@ -467,7 +494,7 @@ static ssize_t src_read(struct bt_conn *conn, const struct bt_gatt_attr *attr,
 	ssize_t ret_val;
 	int err;
 
-	LOG_DBG("conn %p attr %p buf %p len %u offset %u", conn, attr, buf, len, offset);
+	LOG_DBG("conn %p attr %p buf %p len %u offset %u", (void *)conn, attr, buf, len, offset);
 
 	err = k_sem_take(&read_buf_sem, READ_BUF_SEM_TIMEOUT);
 	if (err != 0) {
@@ -476,7 +503,7 @@ static ssize_t src_read(struct bt_conn *conn, const struct bt_gatt_attr *attr,
 		return BT_GATT_ERR(BT_ATT_ERR_INSUFFICIENT_RESOURCES);
 	}
 
-	get_pac_records(&src_pacs_list, &read_buf);
+	get_pac_records(&src_pac_list, &read_buf);
 
 	ret_val = bt_gatt_attr_read(conn, attr, buf, len, offset, read_buf.data,
 				    read_buf.len);
@@ -503,7 +530,7 @@ static ssize_t src_loc_read(struct bt_conn *conn,
 {
 	uint32_t location = sys_cpu_to_le32(pacs_src_location);
 
-	LOG_DBG("conn %p attr %p buf %p len %u offset %u", conn, attr, buf, len, offset);
+	LOG_DBG("conn %p attr %p buf %p len %u offset %u", (void *)conn, attr, buf, len, offset);
 
 	return bt_gatt_attr_read(conn, attr, buf, len, offset, &location,
 				 sizeof(location));
@@ -520,15 +547,17 @@ static void src_loc_cfg_changed(const struct bt_gatt_attr *attr, uint16_t value)
 
 static void set_src_location(enum bt_audio_location audio_location)
 {
-	if (audio_location == pacs_src_location) {
-		return;
-	}
+	if (atomic_test_bit(pacs.flags, PACS_FLAG_SRC_LOC)) {
+		if (audio_location == pacs_src_location) {
+			return;
+		}
 
-	pacs_src_location = audio_location;
+		pacs_src_location = audio_location;
 
-	if (IS_ENABLED(CONFIG_BT_PAC_SRC_LOC_NOTIFIABLE)) {
-		pacs_set_notify_bit(FLAG_SOURCE_AUDIO_LOCATIONS_CHANGED);
-		k_work_submit(&deferred_nfy_work);
+		if (IS_ENABLED(CONFIG_BT_PAC_SRC_LOC_NOTIFIABLE)) {
+			pacs_set_notify_bit(FLAG_SOURCE_AUDIO_LOCATIONS_CHANGED);
+			k_work_submit(&deferred_nfy_work);
+		}
 	}
 }
 #else
@@ -566,30 +595,35 @@ static ssize_t src_loc_write(struct bt_conn *conn,
 #endif /* CONFIG_BT_PAC_SRC_LOC_WRITEABLE */
 
 
-static sys_slist_t *pacs_get(enum bt_audio_dir dir)
+static sys_slist_t *pacs_get_pac(enum bt_audio_dir dir)
 {
 	switch (dir) {
 #if defined(CONFIG_BT_PAC_SNK)
 	case BT_AUDIO_DIR_SINK:
-		return &snk_pacs_list;
+		if (atomic_test_bit(pacs.flags, PACS_FLAG_SNK_PAC)) {
+			return &snk_pac_list;
+		}
+		return NULL;
 #endif /* CONFIG_BT_PAC_SNK */
 #if defined(CONFIG_BT_PAC_SRC)
 	case BT_AUDIO_DIR_SOURCE:
-		return &src_pacs_list;
+		if (atomic_test_bit(pacs.flags, PACS_FLAG_SRC_PAC)) {
+			return &src_pac_list;
+		}
+		return NULL;
 #endif /* CONFIG_BT_PAC_SRC */
 	default:
 		return NULL;
 	}
 }
 
+#if defined(CONFIG_BT_PAC_SNK)
 #define BT_PACS_SNK_PROP \
 	BT_GATT_CHRC_READ \
 	IF_ENABLED(CONFIG_BT_PAC_SNK_LOC_NOTIFIABLE, (|BT_GATT_CHRC_NOTIFY))
-#define BT_PAC_SNK(_read) \
-	BT_AUDIO_CHRC(BT_UUID_PACS_SNK, \
-		      BT_PACS_SNK_PROP, \
-		      BT_GATT_PERM_READ_ENCRYPT, \
-		      _read, NULL, NULL), \
+#define BT_PAC_SNK                                                                                 \
+	BT_AUDIO_CHRC(BT_UUID_PACS_SNK, BT_PACS_SNK_PROP, BT_GATT_PERM_READ_ENCRYPT, snk_read,     \
+		      NULL, NULL),                                                                 \
 	IF_ENABLED(CONFIG_BT_PAC_SNK_NOTIFIABLE, (BT_AUDIO_CCC(snk_cfg_changed),))
 
 #define BT_PACS_SNK_LOC_PROP \
@@ -597,27 +631,39 @@ static sys_slist_t *pacs_get(enum bt_audio_dir dir)
 	IF_ENABLED(CONFIG_BT_PAC_SNK_LOC_WRITEABLE, (|BT_GATT_CHRC_WRITE)) \
 	IF_ENABLED(CONFIG_BT_PAC_SNK_LOC_NOTIFIABLE, (|BT_GATT_CHRC_NOTIFY))
 
-#define BT_PACS_SNK_LOC_PERM \
-	BT_GATT_PERM_READ_ENCRYPT \
+#define BT_PACS_SNK_LOC_PERM                                                                       \
+	BT_GATT_PERM_READ_ENCRYPT                                                                  \
 	IF_ENABLED(CONFIG_BT_PAC_SNK_LOC_WRITEABLE, (|BT_GATT_PERM_WRITE_ENCRYPT))
 
-#define BT_PACS_SNK_LOC(_read) \
-	BT_AUDIO_CHRC(BT_UUID_PACS_SNK_LOC, \
-		      BT_PACS_SNK_LOC_PROP, \
-		      BT_PACS_SNK_LOC_PERM, \
-		      _read, \
-		      COND_CODE_1(CONFIG_BT_PAC_SNK_LOC_WRITEABLE, (snk_loc_write), (NULL)), \
-		      NULL), \
+/* declaration + value [+ cccd] */
+#define PACS_SNK_PAC_CHAR_ATTR_COUNT COND_CODE_1(IS_ENABLED(CONFIG_BT_PAC_SNK_NOTIFIABLE), (3), (2))
+#else
+#define BT_PAC_SNK
+#define PACS_SNK_PAC_CHAR_ATTR_COUNT 0
+#endif /* CONFIG_BT_PAC_SNK */
+
+#if defined(CONFIG_BT_PAC_SNK_LOC)
+#define BT_PACS_SNK_LOC                                                                            \
+	BT_AUDIO_CHRC(BT_UUID_PACS_SNK_LOC, BT_PACS_SNK_LOC_PROP, BT_PACS_SNK_LOC_PERM,            \
+		      snk_loc_read,                                                                \
+		      COND_CODE_1(CONFIG_BT_PAC_SNK_LOC_WRITEABLE, (snk_loc_write), (NULL)), NULL),\
 	IF_ENABLED(CONFIG_BT_PAC_SNK_LOC_NOTIFIABLE, (BT_AUDIO_CCC(snk_loc_cfg_changed),))
 
+/* declaration + value [+ cccd] */
+#define PACS_SNK_PAC_LOC_CHAR_ATTR_COUNT                                                           \
+	COND_CODE_1(IS_ENABLED(CONFIG_BT_PAC_SNK_LOC_NOTIFIABLE), (3), (2))
+#else
+#define BT_PACS_SNK_LOC
+#define PACS_SNK_PAC_LOC_CHAR_ATTR_COUNT 0
+#endif /* CONFIG_BT_PAC_SNK_LOC*/
+
+#if defined(CONFIG_BT_PAC_SRC)
 #define BT_PACS_SRC_PROP \
 	BT_GATT_CHRC_READ \
 	IF_ENABLED(CONFIG_BT_PAC_SRC_LOC_NOTIFIABLE, (|BT_GATT_CHRC_NOTIFY))
-#define BT_PAC_SRC(_read) \
-	BT_AUDIO_CHRC(BT_UUID_PACS_SRC, \
-		      BT_PACS_SRC_PROP, \
-		      BT_GATT_PERM_READ_ENCRYPT, \
-		      _read, NULL, NULL), \
+#define BT_PAC_SRC                                                                                 \
+	BT_AUDIO_CHRC(BT_UUID_PACS_SRC, BT_PACS_SRC_PROP, BT_GATT_PERM_READ_ENCRYPT, src_read,     \
+		      NULL, NULL),                                                                 \
 	IF_ENABLED(CONFIG_BT_PAC_SRC_NOTIFIABLE, (BT_AUDIO_CCC(src_cfg_changed),))
 
 #define BT_PACS_SRC_LOC_PROP \
@@ -625,55 +671,236 @@ static sys_slist_t *pacs_get(enum bt_audio_dir dir)
 	IF_ENABLED(CONFIG_BT_PAC_SRC_LOC_WRITEABLE, (|BT_GATT_CHRC_WRITE)) \
 	IF_ENABLED(CONFIG_BT_PAC_SRC_LOC_NOTIFIABLE, (|BT_GATT_CHRC_NOTIFY))
 
-#define BT_PACS_SRC_LOC_PERM \
-	BT_GATT_PERM_READ_ENCRYPT \
+#define BT_PACS_SRC_LOC_PERM                                                                       \
+	BT_GATT_PERM_READ_ENCRYPT                                                                  \
 	IF_ENABLED(CONFIG_BT_PAC_SRC_LOC_WRITEABLE, (|BT_GATT_PERM_WRITE_ENCRYPT))
 
-#define BT_PACS_SRC_LOC(_read) \
-	BT_AUDIO_CHRC(BT_UUID_PACS_SRC_LOC, \
-		      BT_PACS_SRC_LOC_PROP, \
-		      BT_PACS_SRC_LOC_PERM, \
-		      _read, \
-		      COND_CODE_1(CONFIG_BT_PAC_SRC_LOC_WRITEABLE, (src_loc_write), (NULL)), \
-		      NULL), \
+/* declaration + value [+ cccd] */
+#define PACS_SRC_PAC_CHAR_ATTR_COUNT COND_CODE_1(IS_ENABLED(CONFIG_BT_PAC_SRC_NOTIFIABLE), (3), (2))
+#else
+#define BT_PAC_SRC
+#define PACS_SRC_PAC_CHAR_ATTR_COUNT 0
+#endif
+
+#if defined(CONFIG_BT_PAC_SRC_LOC)
+#define BT_PACS_SRC_LOC                                                                            \
+	BT_AUDIO_CHRC(BT_UUID_PACS_SRC_LOC, BT_PACS_SRC_LOC_PROP, BT_PACS_SRC_LOC_PERM,            \
+		      src_loc_read,                                                                \
+		      COND_CODE_1(CONFIG_BT_PAC_SRC_LOC_WRITEABLE, (src_loc_write), (NULL)), NULL),\
 	IF_ENABLED(CONFIG_BT_PAC_SRC_LOC_NOTIFIABLE, (BT_AUDIO_CCC(src_loc_cfg_changed),))
 
-#define BT_PAC_AVAILABLE_CONTEXT(_read) \
-	BT_AUDIO_CHRC(BT_UUID_PACS_AVAILABLE_CONTEXT, \
-		      BT_GATT_CHRC_READ|BT_GATT_CHRC_NOTIFY, \
-		      BT_GATT_PERM_READ_ENCRYPT, \
-		      _read, NULL, NULL), \
+/* declaration + value [+ cccd] */
+#define PACS_SRC_PAC_LOC_CHAR_ATTR_COUNT                                                           \
+	COND_CODE_1(IS_ENABLED(CONFIG_BT_PAC_SRC_LOC_NOTIFIABLE), (3), (2))
+#else
+#define BT_PACS_SRC_LOC
+#define PACS_SRC_PAC_LOC_CHAR_ATTR_COUNT 0
+#endif
+
+#define BT_PAC_AVAILABLE_CONTEXT                                                                   \
+	BT_AUDIO_CHRC(BT_UUID_PACS_AVAILABLE_CONTEXT, BT_GATT_CHRC_READ | BT_GATT_CHRC_NOTIFY,     \
+		      BT_GATT_PERM_READ_ENCRYPT, available_contexts_read, NULL, NULL),             \
 	BT_AUDIO_CCC(available_context_cfg_changed),
 
 #define BT_PACS_SUPPORTED_CONTEXT_PROP \
 	BT_GATT_CHRC_READ \
 	IF_ENABLED(CONFIG_BT_PACS_SUPPORTED_CONTEXT_NOTIFIABLE, (|BT_GATT_CHRC_NOTIFY))
 
-#define BT_PAC_SUPPORTED_CONTEXT(_read) \
-	BT_AUDIO_CHRC(BT_UUID_PACS_SUPPORTED_CONTEXT, \
-		      BT_PACS_SUPPORTED_CONTEXT_PROP, \
-		      BT_GATT_PERM_READ_ENCRYPT, \
-		      _read, NULL, NULL), \
-	IF_ENABLED(CONFIG_BT_PACS_SUPPORTED_CONTEXT_NOTIFIABLE, \
+#define BT_PAC_SUPPORTED_CONTEXT                                                                   \
+	BT_AUDIO_CHRC(BT_UUID_PACS_SUPPORTED_CONTEXT, BT_PACS_SUPPORTED_CONTEXT_PROP,              \
+		      BT_GATT_PERM_READ_ENCRYPT, supported_context_read, NULL, NULL),              \
+	IF_ENABLED(CONFIG_BT_PACS_SUPPORTED_CONTEXT_NOTIFIABLE,                                    \
 		   (BT_AUDIO_CCC(supported_context_cfg_changed),))
 
-BT_GATT_SERVICE_DEFINE(pacs_svc,
-	BT_GATT_PRIMARY_SERVICE(BT_UUID_PACS),
-#if defined(CONFIG_BT_PAC_SNK)
-	BT_PAC_SNK(snk_read)
+#define BT_PACS_SERVICE_DEFINITION() {                                                             \
+	BT_GATT_PRIMARY_SERVICE(BT_UUID_PACS),                                                     \
+	BT_PAC_SNK                                                                                 \
+	BT_PACS_SNK_LOC                                                                            \
+	BT_PAC_SRC                                                                                 \
+	BT_PACS_SRC_LOC                                                                            \
+	BT_PAC_AVAILABLE_CONTEXT                                                                   \
+	BT_PAC_SUPPORTED_CONTEXT                                                                   \
+}
+
+static const struct bt_gatt_attr _pacs_attrs[] = BT_PACS_SERVICE_DEFINITION();
+static struct bt_gatt_attr pacs_attrs[] = BT_PACS_SERVICE_DEFINITION();
+static struct bt_gatt_service pacs_svc = (struct bt_gatt_service)BT_GATT_SERVICE(pacs_attrs);
+
+static void configure_pacs_char(const struct bt_pacs_register_param *param)
+{
+	const uint8_t first_attr_offset = 1U;
+	struct bt_gatt_attr *svc_attrs =
+		&pacs_svc.attrs[first_attr_offset]; /* first attribute is the service */
+	uint8_t attrs_to_rem = 0U;
+	uint8_t first_to_rem = 0U;
+
+	/* Remove the Sink PAC and Location */
 #if defined(CONFIG_BT_PAC_SNK_LOC)
-	BT_PACS_SNK_LOC(snk_loc_read)
+	if (!param->snk_loc) {
+		first_to_rem = PACS_SNK_PAC_CHAR_ATTR_COUNT;
+		attrs_to_rem = PACS_SNK_PAC_LOC_CHAR_ATTR_COUNT;
+	}
 #endif /* CONFIG_BT_PAC_SNK_LOC */
+#if defined(CONFIG_BT_PAC_SNK)
+	if (!param->snk_pac) {
+		first_to_rem = 0U;
+		attrs_to_rem = PACS_SNK_PAC_CHAR_ATTR_COUNT + PACS_SNK_PAC_LOC_CHAR_ATTR_COUNT;
+	}
 #endif /* CONFIG_BT_PAC_SNK */
+
+	if (attrs_to_rem > 0U) {
+		for (uint8_t i = first_to_rem + attrs_to_rem;
+		     i < pacs_svc.attr_count - first_attr_offset; i++) {
+			svc_attrs[i - attrs_to_rem] = svc_attrs[i];
+		}
+		pacs_svc.attr_count -= attrs_to_rem;
+	}
+
 #if defined(CONFIG_BT_PAC_SRC)
-	BT_PAC_SRC(src_read)
+	/* Set first_to_rem to the start of Source PAC Char, for cleaner offset calc */
+	const uint8_t src_pac_offset =
+		(PACS_SNK_PAC_CHAR_ATTR_COUNT + PACS_SNK_PAC_LOC_CHAR_ATTR_COUNT) - attrs_to_rem;
+	attrs_to_rem = 0U;
+
+	/* Remove the Source PAC and Location */
 #if defined(CONFIG_BT_PAC_SRC_LOC)
-	BT_PACS_SRC_LOC(src_loc_read)
+	if (!param->src_loc) {
+		first_to_rem = src_pac_offset + PACS_SRC_PAC_CHAR_ATTR_COUNT;
+		attrs_to_rem = PACS_SRC_PAC_LOC_CHAR_ATTR_COUNT;
+	}
 #endif /* CONFIG_BT_PAC_SRC_LOC */
+
+	if (!param->src_pac) {
+		first_to_rem = src_pac_offset;
+		attrs_to_rem = PACS_SRC_PAC_CHAR_ATTR_COUNT + PACS_SRC_PAC_LOC_CHAR_ATTR_COUNT;
+	}
+
+	if (attrs_to_rem > 0U) {
+		for (uint8_t i = first_to_rem + attrs_to_rem;
+		     i < pacs_svc.attr_count - first_attr_offset; i++) {
+			svc_attrs[i - attrs_to_rem] = svc_attrs[i];
+		}
+		pacs_svc.attr_count -= attrs_to_rem;
+	}
+#endif /* CONFIG_BT_PAC_SRC */
+}
+
+static bool valid_pacs_register_param(const struct bt_pacs_register_param *param)
+{
+	bool any_pac_registered = false;
+
+	if (param == NULL) {
+		LOG_DBG("param is NULL");
+		return false;
+	}
+
+#if defined(CONFIG_BT_PAC_SNK)
+	any_pac_registered |= param->snk_pac;
+#endif /* CONFIG_BT_PAC_SNK */
+#if defined(CONFIG_BT_PAC_SNK_LOC)
+	if (param->snk_loc && !param->snk_pac) {
+		LOG_DBG("Cannot register snk_loc without snk_pac");
+		return false;
+	}
+#endif /* CONFIG_BT_PAC_SNK_LOC */
+#if defined(CONFIG_BT_PAC_SRC)
+	any_pac_registered |= param->src_pac;
+#endif /* CONFIG_BT_PAC_SRC */
+#if defined(CONFIG_BT_PAC_SRC_LOC)
+	if (param->src_loc && !param->src_pac) {
+		LOG_DBG("Cannot register src_loc without src_pac");
+		return false;
+	}
+#endif /* CONFIG_BT_PAC_SRC_LOC */
+
+	if (!any_pac_registered) {
+		LOG_DBG("Neither snk_pac or src_pac registered");
+		return false;
+	}
+
+	return true;
+}
+
+int bt_pacs_register(const struct bt_pacs_register_param *param)
+{
+	int err = 0;
+
+	if (!valid_pacs_register_param(param)) {
+		return -EINVAL;
+	}
+
+	if (atomic_test_and_set_bit(pacs.flags, PACS_FLAG_REGISTERED)) {
+		LOG_DBG("PACS already registered");
+
+		return -EALREADY;
+	}
+
+	/* Save registration param so we can guard functions accordingly */
+#if defined(CONFIG_BT_PAC_SNK)
+	atomic_set_bit_to(pacs.flags, PACS_FLAG_SNK_PAC, param->snk_pac);
+#endif /* CONFIG_BT_PAC_SNK */
+#if defined(CONFIG_BT_PAC_SNK_LOC)
+	atomic_set_bit_to(pacs.flags, PACS_FLAG_SNK_LOC, param->snk_loc);
+#endif /* CONFIG_BT_PAC_SNK_LOC */
+#if defined(CONFIG_BT_PAC_SRC)
+	atomic_set_bit_to(pacs.flags, PACS_FLAG_SRC_PAC, param->src_pac);
 #endif /* CONFIG_BT_PAC_SRC */
-	BT_PAC_AVAILABLE_CONTEXT(available_contexts_read)
-	BT_PAC_SUPPORTED_CONTEXT(supported_context_read)
-);
+#if defined(CONFIG_BT_PAC_SRC_LOC)
+	atomic_set_bit_to(pacs.flags, PACS_FLAG_SRC_LOC, param->src_loc);
+#endif /* CONFIG_BT_PAC_SRC_LOC */
+
+	/* Remove characteristics if necessary */
+	configure_pacs_char(param);
+
+	err = bt_gatt_service_register(&pacs_svc);
+	if (err != 0) {
+		LOG_DBG("Failed to register ASCS in gatt DB: %d", err);
+		atomic_clear_bit(pacs.flags, PACS_FLAG_REGISTERED);
+
+		return -ENOEXEC;
+	}
+
+	return 0;
+}
+
+int bt_pacs_unregister(void)
+{
+	int err;
+
+	if (!atomic_test_bit(pacs.flags, PACS_FLAG_REGISTERED)) {
+		LOG_DBG("No pacs instance registered");
+
+		return -EALREADY;
+	}
+
+	if (atomic_test_and_set_bit(pacs.flags, PACS_FLAG_SVC_CHANGING)) {
+		LOG_DBG("Service change already in progress");
+		atomic_clear_bit(pacs.flags, PACS_FLAG_SVC_CHANGING);
+
+		return -EBUSY;
+	}
+
+	err = bt_gatt_service_unregister(&pacs_svc);
+
+	/* If unregistration was successful, make sure to reset pacs_attrs so it can be used for
+	 * new registrations
+	 */
+	if (err != 0) {
+		LOG_DBG("Failed to unregister PACS");
+		atomic_clear_bit(pacs.flags, PACS_FLAG_SVC_CHANGING);
+
+		return err;
+	}
+
+	/* Restore to original definition */
+	memcpy(pacs_svc.attrs, &_pacs_attrs, sizeof(_pacs_attrs));
+	pacs_svc.attr_count = ARRAY_SIZE(pacs_attrs);
+
+	atomic_clear_bit(pacs.flags, PACS_FLAG_REGISTERED);
+	atomic_clear_bit(pacs.flags, PACS_FLAG_SVC_CHANGING);
+
+	return err;
+}
 
 #if defined(CONFIG_BT_PAC_SNK_LOC_NOTIFIABLE) || defined(CONFIG_BT_PAC_SRC_LOC_NOTIFIABLE)
 static int pac_notify_loc(struct bt_conn *conn, enum bt_audio_dir dir)
@@ -713,7 +940,7 @@ static int pac_notify_loc(struct bt_conn *conn, enum bt_audio_dir dir)
 static int pac_notify(struct bt_conn *conn, enum bt_audio_dir dir)
 {
 	int err = 0;
-	sys_slist_t *pacs;
+	sys_slist_t *pac;
 	const struct bt_uuid *uuid;
 
 	switch (dir) {
@@ -738,9 +965,9 @@ static int pac_notify(struct bt_conn *conn, enum bt_audio_dir dir)
 		return err;
 	}
 
-	pacs = pacs_get(dir);
-	__ASSERT(pacs, "Failed to get pacs.\n");
-	get_pac_records(pacs, &read_buf);
+	pac = pacs_get_pac(dir);
+	__ASSERT(pac, "Failed to get pacs.\n");
+	get_pac_records(pac, &read_buf);
 
 	err = pacs_gatt_notify(conn, uuid, pacs_svc.attrs,
 			       read_buf.data, read_buf.len);
@@ -799,7 +1026,7 @@ static int supported_contexts_notify(struct bt_conn *conn)
 void pacs_gatt_notify_complete_cb(struct bt_conn *conn, void *user_data)
 {
 	/* Notification done, clear bit and reschedule work */
-	atomic_clear(&notify_rdy);
+	atomic_clear_bit(pacs.flags, PACS_FLAG_NOTIFY_RDY);
 	k_work_submit(&deferred_nfy_work);
 }
 
@@ -820,11 +1047,16 @@ static int pacs_gatt_notify(struct bt_conn *conn,
 	params.func = pacs_gatt_notify_complete_cb;
 
 	/* Mark notification in progress */
-	atomic_set(&notify_rdy, 1);
+	if (atomic_test_bit(pacs.flags, PACS_FLAG_SVC_CHANGING) ||
+	    !atomic_test_bit(pacs.flags, PACS_FLAG_REGISTERED)) {
+		return 0;
+	}
+
+	atomic_set_bit(pacs.flags, PACS_FLAG_NOTIFY_RDY);
 
 	err = bt_gatt_notify_cb(conn, &params);
 	if (err != 0) {
-		atomic_clear(&notify_rdy);
+		atomic_clear_bit(pacs.flags, PACS_FLAG_NOTIFY_RDY);
 	}
 
 	if (err && err != -ENOTCONN) {
@@ -859,7 +1091,7 @@ static void notify_cb(struct bt_conn *conn, void *data)
 	}
 
 	/* Check if we have unverified notifications in progress */
-	if (atomic_get(&notify_rdy)) {
+	if (atomic_test_bit(pacs.flags, PACS_FLAG_NOTIFY_RDY)) {
 		return;
 	}
 
@@ -936,18 +1168,18 @@ static void pacs_auth_pairing_complete(struct bt_conn *conn, bool bonded)
 	}
 
 	/* Check if already in list, and do nothing if it is */
-	for (size_t i = 0U; i < ARRAY_SIZE(clients); i++) {
-		if (atomic_test_bit(clients[i].flags, FLAG_ACTIVE) &&
-		    bt_addr_le_eq(bt_conn_get_dst(conn), &clients[i].addr)) {
+	for (size_t i = 0U; i < ARRAY_SIZE(pacs.clients); i++) {
+		if (atomic_test_bit(pacs.clients[i].flags, FLAG_ACTIVE) &&
+		    bt_addr_le_eq(bt_conn_get_dst(conn), &pacs.clients[i].addr)) {
 			return;
 		}
 	}
 
 	/* Else add the device */
-	for (size_t i = 0U; i < ARRAY_SIZE(clients); i++) {
-		if (!atomic_test_bit(clients[i].flags, FLAG_ACTIVE)) {
-			atomic_set_bit(clients[i].flags, FLAG_ACTIVE);
-			memcpy(&clients[i].addr, bt_conn_get_dst(conn), sizeof(bt_addr_le_t));
+	for (size_t i = 0U; i < ARRAY_SIZE(pacs.clients); i++) {
+		if (!atomic_test_bit(pacs.clients[i].flags, FLAG_ACTIVE)) {
+			atomic_set_bit(pacs.clients[i].flags, FLAG_ACTIVE);
+			memcpy(&pacs.clients[i].addr, bt_conn_get_dst(conn), sizeof(bt_addr_le_t));
 
 			/* Send out all pending notifications */
 			k_work_submit(&deferred_nfy_work);
@@ -959,35 +1191,44 @@ static void pacs_auth_pairing_complete(struct bt_conn *conn, bool bonded)
 static void pacs_bond_deleted(uint8_t id, const bt_addr_le_t *peer)
 {
 	/* Find the device entry to delete */
-	for (size_t i = 0U; i < ARRAY_SIZE(clients); i++) {
+	for (size_t i = 0U; i < ARRAY_SIZE(pacs.clients); i++) {
 		/* Check if match, and if active, if so, reset */
-		if (atomic_test_bit(clients[i].flags, FLAG_ACTIVE) &&
-		    bt_addr_le_eq(peer, &clients[i].addr)) {
+		if (atomic_test_bit(pacs.clients[i].flags, FLAG_ACTIVE) &&
+		    bt_addr_le_eq(peer, &pacs.clients[i].addr)) {
 			for (size_t j = 0U; j < FLAG_NUM; j++) {
-				atomic_clear_bit(clients[i].flags, j);
+				atomic_clear_bit(pacs.clients[i].flags, j);
 			}
-			(void)memset(&clients[i].addr, 0, sizeof(bt_addr_le_t));
+			(void)memset(&pacs.clients[i].addr, 0, sizeof(bt_addr_le_t));
 			return;
 		}
 	}
 }
 
 static void pacs_security_changed(struct bt_conn *conn, bt_security_t level,
-				  enum bt_security_err err)
+				  enum bt_security_err sec_err)
 {
+	struct bt_conn_info info;
+	int err;
+
 	LOG_DBG("%s changed security level to %d", bt_addr_le_str(bt_conn_get_dst(conn)), level);
 
-	if (err != 0 || conn->encrypt == 0) {
+	if (sec_err != BT_SECURITY_ERR_SUCCESS || level <= BT_SECURITY_L1) {
 		return;
 	}
 
-	if (!bt_addr_le_is_bonded(conn->id, &conn->le.dst)) {
+	err = bt_conn_get_info(conn, &info);
+	if (err < 0) {
+		__ASSERT_NO_MSG(false);
+		return;
+	}
+
+	if (!bt_le_bond_exists(info.id, info.le.dst)) {
 		return;
 	}
 
-	for (size_t i = 0U; i < ARRAY_SIZE(clients); i++) {
+	for (size_t i = 0U; i < ARRAY_SIZE(pacs.clients); i++) {
 		for (size_t j = 0U; j < FLAG_NUM; j++) {
-			if (atomic_test_bit(clients[i].flags, j)) {
+			if (atomic_test_bit(pacs.clients[i].flags, j)) {
 
 				/**
 				 *  It's enough that one flag is set, as the defer work will go
@@ -1010,7 +1251,8 @@ static void pacs_disconnected(struct bt_conn *conn, uint8_t reason)
 	}
 
 #if defined(CONFIG_BT_PAC_SNK)
-	if (client->snk_available_contexts != NULL) {
+	if (atomic_test_bit(pacs.flags, PACS_FLAG_SNK_PAC) &&
+	    client->snk_available_contexts != NULL) {
 		uint16_t old = POINTER_TO_UINT(client->snk_available_contexts);
 		uint16_t new;
 
@@ -1022,7 +1264,8 @@ static void pacs_disconnected(struct bt_conn *conn, uint8_t reason)
 #endif /* CONFIG_BT_PAC_SNK */
 
 #if defined(CONFIG_BT_PAC_SRC)
-	if (client->src_available_contexts != NULL) {
+	if (atomic_test_bit(pacs.flags, PACS_FLAG_SRC_PAC) &&
+	    client->src_available_contexts != NULL) {
 		uint16_t old = POINTER_TO_UINT(client->src_available_contexts);
 		uint16_t new;
 
@@ -1034,7 +1277,7 @@ static void pacs_disconnected(struct bt_conn *conn, uint8_t reason)
 #endif /* CONFIG_BT_PAC_SRC */
 }
 
-static struct bt_conn_cb conn_callbacks = {
+BT_CONN_CB_DEFINE(conn_callbacks) = {
 	.security_changed = pacs_security_changed,
 	.disconnected = pacs_disconnected,
 };
@@ -1053,7 +1296,7 @@ void bt_pacs_cap_foreach(enum bt_audio_dir dir, bt_pacs_cap_foreach_func_t func,
 		return;
 	}
 
-	pac = pacs_get(dir);
+	pac = pacs_get_pac(dir);
 	if (!pac) {
 		return;
 	}
@@ -1063,14 +1306,14 @@ void bt_pacs_cap_foreach(enum bt_audio_dir dir, bt_pacs_cap_foreach_func_t func,
 
 static void add_bonded_addr_to_client_list(const struct bt_bond_info *info, void *data)
 {
-	for (uint8_t i = 0; i < ARRAY_SIZE(clients); i++) {
+	for (uint8_t i = 0; i < ARRAY_SIZE(pacs.clients); i++) {
 		/* Check if device is registered, it not, add it */
-		if (!atomic_test_bit(clients[i].flags, FLAG_ACTIVE)) {
+		if (!atomic_test_bit(pacs.clients[i].flags, FLAG_ACTIVE)) {
 			char addr_str[BT_ADDR_LE_STR_LEN];
 
-			atomic_set_bit(clients[i].flags, FLAG_ACTIVE);
-			memcpy(&clients[i].addr, &info->addr, sizeof(bt_addr_le_t));
-			bt_addr_le_to_str(&clients[i].addr, addr_str, sizeof(addr_str));
+			atomic_set_bit(pacs.clients[i].flags, FLAG_ACTIVE);
+			memcpy(&pacs.clients[i].addr, &info->addr, sizeof(bt_addr_le_t));
+			bt_addr_le_to_str(&pacs.clients[i].addr, addr_str, sizeof(addr_str));
 			LOG_DBG("Added %s to bonded list\n", addr_str);
 			return;
 		}
@@ -1090,7 +1333,7 @@ int bt_pacs_cap_register(enum bt_audio_dir dir, struct bt_pacs_cap *cap)
 
 	codec_cap = cap->codec_cap;
 
-	pac = pacs_get(dir);
+	pac = pacs_get_pac(dir);
 	if (!pac) {
 		return -EINVAL;
 	}
@@ -1104,7 +1347,6 @@ int bt_pacs_cap_register(enum bt_audio_dir dir, struct bt_pacs_cap *cap)
 	sys_slist_append(pac, &cap->_node);
 
 	if (!callbacks_registered) {
-		bt_conn_cb_register(&conn_callbacks);
 		bt_conn_auth_info_cb_register(&auth_callbacks);
 
 		callbacks_registered = true;
@@ -1132,7 +1374,7 @@ int bt_pacs_cap_unregister(enum bt_audio_dir dir, struct bt_pacs_cap *cap)
 		return -EINVAL;
 	}
 
-	pac = pacs_get(dir);
+	pac = pacs_get_pac(dir);
 	if (!pac) {
 		return -EINVAL;
 	}
@@ -1181,13 +1423,22 @@ int bt_pacs_set_location(enum bt_audio_dir dir, enum bt_audio_location location)
 
 int bt_pacs_set_available_contexts(enum bt_audio_dir dir, enum bt_audio_context contexts)
 {
+	if (!atomic_test_bit(pacs.flags, PACS_FLAG_REGISTERED)) {
+		return -EINVAL;
+	}
 	switch (dir) {
 	case BT_AUDIO_DIR_SINK:
-		return set_available_contexts(contexts, &snk_available_contexts,
-					      supported_context_get(dir));
+		if (atomic_test_bit(pacs.flags, PACS_FLAG_SNK_PAC)) {
+			return set_available_contexts(contexts, &snk_available_contexts,
+						      supported_context_get(dir));
+		}
+		return -EINVAL;
 	case BT_AUDIO_DIR_SOURCE:
-		return set_available_contexts(contexts, &src_available_contexts,
-					      supported_context_get(dir));
+		if (atomic_test_bit(pacs.flags, PACS_FLAG_SRC_PAC)) {
+			return set_available_contexts(contexts, &src_available_contexts,
+						      supported_context_get(dir));
+		}
+		return -EINVAL;
 	}
 
 	return -EINVAL;
@@ -1215,23 +1466,29 @@ int bt_pacs_conn_set_available_contexts_for_conn(struct bt_conn *conn, enum bt_a
 	switch (dir) {
 #if defined(CONFIG_BT_PAC_SNK)
 	case BT_AUDIO_DIR_SINK:
-		if (contexts != NULL) {
-			client->snk_available_contexts = UINT_TO_POINTER(*contexts);
-		} else {
-			client->snk_available_contexts = NULL;
+		if (atomic_test_bit(pacs.flags, PACS_FLAG_SNK_PAC)) {
+			if (contexts != NULL) {
+				client->snk_available_contexts = UINT_TO_POINTER(*contexts);
+			} else {
+				client->snk_available_contexts = NULL;
+			}
+			break;
 		}
 
-		break;
+		return -EINVAL;
 #endif /* CONFIG_BT_PAC_SNK */
 #if defined(CONFIG_BT_PAC_SRC)
 	case BT_AUDIO_DIR_SOURCE:
-		if (contexts != NULL) {
-			client->src_available_contexts = UINT_TO_POINTER(*contexts);
-		} else {
-			client->src_available_contexts = NULL;
+		if (atomic_test_bit(pacs.flags, PACS_FLAG_SRC_PAC)) {
+			if (contexts != NULL) {
+				client->src_available_contexts = UINT_TO_POINTER(*contexts);
+			} else {
+				client->src_available_contexts = NULL;
+			}
+			break;
 		}
 
-		break;
+		return -EINVAL;
 #endif /* CONFIG_BT_PAC_SRC */
 	default:
 		return -EINVAL;
@@ -1260,16 +1517,22 @@ int bt_pacs_set_supported_contexts(enum bt_audio_dir dir, enum bt_audio_context
 	switch (dir) {
 	case BT_AUDIO_DIR_SINK:
 #if defined(CONFIG_BT_PAC_SNK)
-		supported_contexts = &snk_supported_contexts;
-		available_contexts = &snk_available_contexts;
-		break;
+		if (atomic_test_bit(pacs.flags, PACS_FLAG_SNK_PAC)) {
+			supported_contexts = &snk_supported_contexts;
+			available_contexts = &snk_available_contexts;
+			break;
+		}
+		return -EINVAL;
 #endif /* CONFIG_BT_PAC_SNK */
 		return -ENOTSUP;
 	case BT_AUDIO_DIR_SOURCE:
 #if defined(CONFIG_BT_PAC_SRC)
-		supported_contexts = &src_supported_contexts;
-		available_contexts = &src_available_contexts;
-		break;
+		if (atomic_test_bit(pacs.flags, PACS_FLAG_SRC_PAC)) {
+			supported_contexts = &src_supported_contexts;
+			available_contexts = &src_available_contexts;
+			break;
+		}
+		return -EINVAL;
 #endif /* CONFIG_BT_PAC_SRC */
 		return -ENOTSUP;
 	default:
@@ -1287,9 +1550,15 @@ enum bt_audio_context bt_pacs_get_available_contexts(enum bt_audio_dir dir)
 {
 	switch (dir) {
 	case BT_AUDIO_DIR_SINK:
-		return snk_available_contexts;
+		if (atomic_test_bit(pacs.flags, PACS_FLAG_SNK_PAC)) {
+			return snk_available_contexts;
+		}
+		break;
 	case BT_AUDIO_DIR_SOURCE:
-		return src_available_contexts;
+		if (atomic_test_bit(pacs.flags, PACS_FLAG_SRC_PAC)) {
+			return src_available_contexts;
+		}
+		break;
 	}
 
 	return BT_AUDIO_CONTEXT_TYPE_PROHIBITED;
@@ -1305,3 +1574,36 @@ enum bt_audio_context bt_pacs_get_available_contexts_for_conn(struct bt_conn *co
 
 	return pacs_get_available_contexts_for_conn(conn, dir);
 }
+
+struct codec_cap_lookup_id_data {
+	const struct bt_pac_codec *codec_id;
+	const struct bt_audio_codec_cap *codec_cap;
+};
+
+static bool codec_lookup_id(const struct bt_pacs_cap *cap, void *user_data)
+{
+	struct codec_cap_lookup_id_data *data = user_data;
+
+	if (cap->codec_cap->id == data->codec_id->id &&
+	    cap->codec_cap->cid == data->codec_id->cid &&
+	    cap->codec_cap->vid == data->codec_id->vid) {
+		data->codec_cap = cap->codec_cap;
+
+		return false;
+	}
+
+	return true;
+}
+
+const struct bt_audio_codec_cap *bt_pacs_get_codec_cap(enum bt_audio_dir dir,
+						       const struct bt_pac_codec *codec_id)
+{
+	struct codec_cap_lookup_id_data lookup_data = {
+		.codec_id = codec_id,
+		.codec_cap = NULL,
+	};
+
+	bt_pacs_cap_foreach(dir, codec_lookup_id, &lookup_data);
+
+	return lookup_data.codec_cap;
+}
diff --git a/subsys/bluetooth/audio/pacs_internal.h b/subsys/bluetooth/audio/pacs_internal.h
index 8fe715e57ba..897f8800504 100644
--- a/subsys/bluetooth/audio/pacs_internal.h
+++ b/subsys/bluetooth/audio/pacs_internal.h
@@ -9,6 +9,7 @@
 
 #include <stdint.h>
 
+#include <zephyr/bluetooth/audio/audio.h>
 #include <zephyr/sys/util_macro.h>
 
 #define BT_AUDIO_LOCATION_MASK BIT_MASK(28)
@@ -38,3 +39,6 @@ struct bt_pacs_context {
 	uint16_t  snk;
 	uint16_t  src;
 } __packed;
+
+const struct bt_audio_codec_cap *bt_pacs_get_codec_cap(enum bt_audio_dir dir,
+						       const struct bt_pac_codec *codec_id);
diff --git a/subsys/bluetooth/audio/shell/CMakeLists.txt b/subsys/bluetooth/audio/shell/CMakeLists.txt
index 5fe6a71b615..bb71e1e65c0 100644
--- a/subsys/bluetooth/audio/shell/CMakeLists.txt
+++ b/subsys/bluetooth/audio/shell/CMakeLists.txt
@@ -7,6 +7,10 @@ zephyr_library_sources_ifdef(
   CONFIG_BT_CCP_CALL_CONTROL_SERVER
   ccp_call_control_server.c
   )
+zephyr_library_sources_ifdef(
+  CONFIG_BT_CCP_CALL_CONTROL_CLIENT
+  ccp_call_control_client.c
+  )
 zephyr_library_sources_ifdef(
   CONFIG_BT_VCP_VOL_REND
   vcp_vol_rend.c
diff --git a/subsys/bluetooth/audio/shell/audio.h b/subsys/bluetooth/audio/shell/audio.h
index 82865453eca..e73e10e0e83 100644
--- a/subsys/bluetooth/audio/shell/audio.h
+++ b/subsys/bluetooth/audio/shell/audio.h
@@ -13,6 +13,7 @@
 #ifndef AUDIO_SHELL_AUDIO_H
 #define AUDIO_SHELL_AUDIO_H
 
+#include <errno.h>
 #include <stdint.h>
 #include <stdbool.h>
 #include <stddef.h>
@@ -32,7 +33,6 @@
 #include <zephyr/sys/util_macro.h>
 #include <zephyr/sys_clock.h>
 
-#include "host/shell/bt.h"
 #include "common/bt_shell_private.h"
 
 #define SHELL_PRINT_INDENT_LEVEL_SIZE 2
@@ -40,17 +40,17 @@
 
 extern struct bt_csip_set_member_svc_inst *svc_inst;
 
-ssize_t audio_ad_data_add(struct bt_data *data, const size_t data_size, const bool discoverable,
-			  const bool connectable);
-ssize_t audio_pa_data_add(struct bt_data *data_array, const size_t data_array_size);
-ssize_t csis_ad_data_add(struct bt_data *data, const size_t data_size, const bool discoverable);
+size_t audio_ad_data_add(struct bt_data *data, const size_t data_size, const bool discoverable,
+			 const bool connectable);
+size_t audio_pa_data_add(struct bt_data *data_array, const size_t data_array_size);
+size_t csis_ad_data_add(struct bt_data *data, const size_t data_size, const bool discoverable);
 size_t cap_acceptor_ad_data_add(struct bt_data data[], size_t data_size, bool discoverable);
 size_t bap_scan_delegator_ad_data_add(struct bt_data data[], size_t data_size);
 size_t gmap_ad_data_add(struct bt_data data[], size_t data_size);
 size_t pbp_ad_data_add(struct bt_data data[], size_t data_size);
-ssize_t cap_initiator_ad_data_add(struct bt_data *data_array, const size_t data_array_size,
-				  const bool discoverable, const bool connectable);
-ssize_t cap_initiator_pa_data_add(struct bt_data *data_array, const size_t data_array_size);
+size_t cap_initiator_ad_data_add(struct bt_data *data_array, const size_t data_array_size,
+				 const bool discoverable, const bool connectable);
+size_t cap_initiator_pa_data_add(struct bt_data *data_array, const size_t data_array_size);
 
 #if defined(CONFIG_BT_AUDIO)
 /* Must guard before including audio.h as audio.h uses Kconfigs guarded by
diff --git a/subsys/bluetooth/audio/shell/bap.c b/subsys/bluetooth/audio/shell/bap.c
index 492c90e9024..71a33585945 100644
--- a/subsys/bluetooth/audio/shell/bap.c
+++ b/subsys/bluetooth/audio/shell/bap.c
@@ -28,6 +28,7 @@
 #include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/crypto.h>
 #include <zephyr/bluetooth/gap.h>
 #include <zephyr/bluetooth/gatt.h>
 #include <zephyr/bluetooth/hci_types.h>
@@ -47,6 +48,7 @@
 #include <zephyr/sys/util_macro.h>
 #include <zephyr/sys_clock.h>
 
+#include "common/bt_shell_private.h"
 #include "host/shell/bt.h"
 #include "audio.h"
 
@@ -3768,7 +3770,20 @@ static int cmd_init(const struct shell *sh, size_t argc, char *argv[])
 		CONFIG_BT_ASCS_MAX_ASE_SNK_COUNT,
 		CONFIG_BT_ASCS_MAX_ASE_SRC_COUNT
 	};
-
+	const struct bt_pacs_register_param pacs_param = {
+#if defined(CONFIG_BT_PAC_SNK)
+		.snk_pac = true,
+#endif /* CONFIG_BT_PAC_SNK */
+#if defined(CONFIG_BT_PAC_SNK_LOC)
+		.snk_loc = true,
+#endif /* CONFIG_BT_PAC_SNK_LOC */
+#if defined(CONFIG_BT_PAC_SRC)
+		.src_pac = true,
+#endif /* CONFIG_BT_PAC_SRC */
+#if defined(CONFIG_BT_PAC_SRC_LOC)
+		.src_loc = true,
+#endif /* CONFIG_BT_PAC_SRC_LOC */
+	};
 
 	if (argc == 3) {
 		snk_cnt = shell_strtoul(argv[1], 0, &err);
@@ -3795,8 +3810,14 @@ static int cmd_init(const struct shell *sh, size_t argc, char *argv[])
 		src_cnt = CONFIG_BT_ASCS_MAX_ASE_SRC_COUNT;
 	}
 
-	bt_bap_unicast_server_register(&unicast_server_param);
-	bt_bap_unicast_server_register_cb(&unicast_server_cb);
+	err = bt_pacs_register(&pacs_param);
+	__ASSERT(err == 0, "Failed to register PACS: %d", err);
+
+	err = bt_bap_unicast_server_register(&unicast_server_param);
+	__ASSERT(err == 0, "Failed to register Unicast Server: %d", err);
+
+	err = bt_bap_unicast_server_register_cb(&unicast_server_cb);
+	__ASSERT(err == 0, "Failed to register Unicast Server Callbacks: %d", err);
 #endif /* CONFIG_BT_BAP_UNICAST_SERVER */
 
 #if defined(CONFIG_BT_PAC_SNK)
@@ -4203,8 +4224,7 @@ static int cmd_bap(const struct shell *sh, size_t argc, char **argv)
 
 SHELL_CMD_ARG_REGISTER(bap, &bap_cmds, "Bluetooth BAP shell commands", cmd_bap, 1, 1);
 
-static ssize_t connectable_ad_data_add(struct bt_data *data_array,
-				       size_t data_array_size)
+static size_t connectable_ad_data_add(struct bt_data *data_array, size_t data_array_size)
 {
 	static const uint8_t ad_ext_uuid16[] = {
 		IF_ENABLED(CONFIG_BT_MICP_MIC_DEV, (BT_UUID_16_ENCODE(BT_UUID_MICS_VAL),))
@@ -4286,8 +4306,7 @@ static ssize_t connectable_ad_data_add(struct bt_data *data_array,
 	return ad_len;
 }
 
-static ssize_t nonconnectable_ad_data_add(struct bt_data *data_array,
-					  const size_t data_array_size)
+static size_t nonconnectable_ad_data_add(struct bt_data *data_array, const size_t data_array_size)
 {
 	static const uint8_t ad_ext_uuid16[] = {
 		IF_ENABLED(CONFIG_BT_PACS, (BT_UUID_16_ENCODE(BT_UUID_PACS_VAL),))
@@ -4318,9 +4337,9 @@ static ssize_t nonconnectable_ad_data_add(struct bt_data *data_array,
 
 		err = bt_rand(&broadcast_id, BT_AUDIO_BROADCAST_ID_SIZE);
 		if (err != 0) {
-			printk("Unable to generate broadcast ID: %d\n", err);
+			bt_shell_error("Unable to generate broadcast ID: %d\n", err);
 
-			return -1;
+			return 0;
 		}
 
 		sys_put_le24(broadcast_id, &ad_bap_broadcast_announcement[2]);
@@ -4346,10 +4365,10 @@ static ssize_t nonconnectable_ad_data_add(struct bt_data *data_array,
 	return ad_len;
 }
 
-ssize_t audio_ad_data_add(struct bt_data *data_array, const size_t data_array_size,
-			  const bool discoverable, const bool connectable)
+size_t audio_ad_data_add(struct bt_data *data_array, const size_t data_array_size,
+			 const bool discoverable, const bool connectable)
 {
-	ssize_t ad_len = 0;
+	size_t ad_len = 0;
 
 	if (!discoverable) {
 		return 0;
@@ -4369,8 +4388,7 @@ ssize_t audio_ad_data_add(struct bt_data *data_array, const size_t data_array_si
 	return ad_len;
 }
 
-ssize_t audio_pa_data_add(struct bt_data *data_array,
-			  const size_t data_array_size)
+size_t audio_pa_data_add(struct bt_data *data_array, const size_t data_array_size)
 {
 	size_t ad_len = 0;
 
@@ -4386,9 +4404,9 @@ ssize_t audio_pa_data_add(struct bt_data *data_array,
 
 		err = bt_bap_broadcast_source_get_base(default_source.bap_source, &base_buf);
 		if (err != 0) {
-			printk("Unable to get BASE: %d\n", err);
+			bt_shell_error("Unable to get BASE: %d\n", err);
 
-			return -1;
+			return 0;
 		}
 
 		data_array[ad_len].type = BT_DATA_SVC_DATA16;
diff --git a/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c b/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c
index 279a5062345..716d2d9bc8d 100644
--- a/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c
+++ b/subsys/bluetooth/audio/shell/bap_broadcast_assistant.c
@@ -32,8 +32,9 @@
 #include <zephyr/sys/util_macro.h>
 #include <zephyr/types.h>
 
+#include "common/bt_shell_private.h"
 #include "host/shell/bt.h"
-#include "../../host/hci_core.h"
+#include "host/hci_core.h"
 #include "audio.h"
 
 static uint8_t received_base[UINT8_MAX];
diff --git a/subsys/bluetooth/audio/shell/bap_usb.c b/subsys/bluetooth/audio/shell/bap_usb.c
index 426ab59e932..5199c62c77f 100644
--- a/subsys/bluetooth/audio/shell/bap_usb.c
+++ b/subsys/bluetooth/audio/shell/bap_usb.c
@@ -33,6 +33,8 @@
 
 #if defined(CONFIG_SOC_NRF5340_CPUAPP)
 #include <nrfx_clock.h>
+#include <drivers/nrfx_errors.h>
+#include <hal/nrf_clock.h>
 #endif /* CONFIG_SOC_NRF5340_CPUAPP */
 
 #include "audio.h"
diff --git a/subsys/bluetooth/audio/shell/cap_commander.c b/subsys/bluetooth/audio/shell/cap_commander.c
index c746cc886db..f623cf0595d 100644
--- a/subsys/bluetooth/audio/shell/cap_commander.c
+++ b/subsys/bluetooth/audio/shell/cap_commander.c
@@ -10,17 +10,24 @@
 #include <stdbool.h>
 #include <stddef.h>
 #include <stdint.h>
+#include <string.h>
 
 #include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/audio/audio.h>
+#include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/audio/csip.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/audio/cap.h>
 #include <zephyr/bluetooth/audio/vocs.h>
+#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/iso.h>
 #include <zephyr/shell/shell.h>
 #include <zephyr/shell/shell_string_conv.h>
 #include <zephyr/sys/util.h>
 #include <zephyr/types.h>
 
+#include "common/bt_shell_private.h"
 #include "host/shell/bt.h"
 #include "audio.h"
 
@@ -813,7 +820,7 @@ static int cmd_cap_commander_distribute_broadcast_code(const struct shell *sh, s
 
 		src_id = shell_strtoul(arg, 0, &err);
 		if (err != 0) {
-			shell_error(sh, "Could not parce src_id: %d", err);
+			shell_error(sh, "Could not parse src_id: %d", err);
 			return -ENOEXEC;
 		}
 		if (src_id > UINT8_MAX) {
diff --git a/subsys/bluetooth/audio/shell/cap_initiator.c b/subsys/bluetooth/audio/shell/cap_initiator.c
index 1a7dcc2e479..bfcba65f70e 100644
--- a/subsys/bluetooth/audio/shell/cap_initiator.c
+++ b/subsys/bluetooth/audio/shell/cap_initiator.c
@@ -18,6 +18,7 @@
 #include <zephyr/bluetooth/audio/audio.h>
 #include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/audio/csip.h>
+#include <zephyr/bluetooth/crypto.h>
 #include <zephyr/bluetooth/gap.h>
 #include <zephyr/bluetooth/iso.h>
 #include <zephyr/bluetooth/uuid.h>
@@ -33,6 +34,7 @@
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/audio/cap.h>
 
+#include "common/bt_shell_private.h"
 #include "host/shell/bt.h"
 #include "audio.h"
 
@@ -1426,7 +1428,7 @@ SHELL_CMD_ARG_REGISTER(cap_initiator, &cap_initiator_cmds,
 		       "Bluetooth CAP initiator shell commands",
 		       cmd_cap_initiator, 1, 1);
 
-static ssize_t nonconnectable_ad_data_add(struct bt_data *data_array, const size_t data_array_size)
+static size_t nonconnectable_ad_data_add(struct bt_data *data_array, const size_t data_array_size)
 {
 #if defined(CONFIG_BT_BAP_BROADCAST_SOURCE)
 	if (default_source.cap_source != NULL && default_source.is_cap) {
@@ -1438,9 +1440,9 @@ static ssize_t nonconnectable_ad_data_add(struct bt_data *data_array, const size
 
 		err = bt_rand(&broadcast_id, BT_AUDIO_BROADCAST_ID_SIZE);
 		if (err) {
-			printk("Unable to generate broadcast ID: %d\n", err);
+			bt_shell_error("Unable to generate broadcast ID: %d\n", err);
 
-			return -1;
+			return 0;
 		}
 
 		sys_put_le24(broadcast_id, &ad_cap_broadcast_announcement[2]);
@@ -1455,8 +1457,8 @@ static ssize_t nonconnectable_ad_data_add(struct bt_data *data_array, const size
 	return 0;
 }
 
-ssize_t cap_initiator_ad_data_add(struct bt_data *data_array, const size_t data_array_size,
-				  const bool discoverable, const bool connectable)
+size_t cap_initiator_ad_data_add(struct bt_data *data_array, const size_t data_array_size,
+				 const bool discoverable, const bool connectable)
 {
 	if (!discoverable) {
 		return 0;
@@ -1469,7 +1471,7 @@ ssize_t cap_initiator_ad_data_add(struct bt_data *data_array, const size_t data_
 	return 0;
 }
 
-ssize_t cap_initiator_pa_data_add(struct bt_data *data_array, const size_t data_array_size)
+size_t cap_initiator_pa_data_add(struct bt_data *data_array, const size_t data_array_size)
 {
 #if defined(CONFIG_BT_BAP_BROADCAST_SOURCE)
 	if (default_source.cap_source != NULL && default_source.is_cap) {
@@ -1483,9 +1485,9 @@ ssize_t cap_initiator_pa_data_add(struct bt_data *data_array, const size_t data_
 
 		err = bt_cap_initiator_broadcast_get_base(default_source.cap_source, &base_buf);
 		if (err != 0) {
-			printk("Unable to get BASE: %d\n", err);
+			bt_shell_error("Unable to get BASE: %d\n", err);
 
-			return -1;
+			return 0;
 		}
 
 		data_array[0].type = BT_DATA_SVC_DATA16;
diff --git a/subsys/bluetooth/audio/shell/ccp_call_control_client.c b/subsys/bluetooth/audio/shell/ccp_call_control_client.c
new file mode 100644
index 00000000000..bcfa418b890
--- /dev/null
+++ b/subsys/bluetooth/audio/shell/ccp_call_control_client.c
@@ -0,0 +1,100 @@
+/** @file
+ *  @brief Bluetooth Call Control Profile Call Control Client shell
+ */
+
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <errno.h>
+#include <stdint.h>
+#include <stdio.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/audio/tbs.h>
+#include <zephyr/bluetooth/audio/ccp.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/shell/shell.h>
+
+#include "common/bt_shell_private.h"
+#include "host/shell/bt.h"
+
+static struct bt_ccp_call_control_client *clients[CONFIG_BT_MAX_CONN];
+
+static void ccp_call_control_client_discover_cb(struct bt_ccp_call_control_client *client, int err,
+						struct bt_ccp_call_control_client_bearers *bearers)
+{
+	struct bt_ccp_call_control_client_bearer *gtbs_bearer = NULL;
+	uint8_t tbs_count = 0U;
+
+	if (err != 0) {
+		bt_shell_error("Failed to discover TBS: %d", err);
+		return;
+	}
+#if defined(CONFIG_BT_TBS_CLIENT_GTBS)
+	gtbs_bearer = bearers->gtbs_bearer;
+#endif /* CONFIG_BT_TBS_CLIENT_GTBS */
+#if defined(CONFIG_BT_TBS_CLIENT_TBS)
+	tbs_count = bearers->tbs_count;
+#endif /* CONFIG_BT_TBS_CLIENT_TBS */
+
+	bt_shell_info("Discovery completed with %s%u TBS bearers",
+		      gtbs_bearer != NULL ? "GTBS and " : "", tbs_count);
+}
+
+static int cmd_ccp_call_control_client_discover(const struct shell *sh, size_t argc, char *argv[])
+{
+	static bool cb_registered;
+
+	int err;
+
+	if (default_conn == NULL) {
+		shell_error(sh, "Not connected");
+		return -ENOEXEC;
+	}
+
+	if (!cb_registered) {
+		static struct bt_ccp_call_control_client_cb ccp_call_control_client_cbs = {
+			.discover = ccp_call_control_client_discover_cb,
+		};
+
+		err = bt_ccp_call_control_client_register_cb(&ccp_call_control_client_cbs);
+		if (err != 0) {
+			shell_error(sh, "Failed to register CCP Call Control Client cbs (err %d)",
+				    err);
+			return -ENOEXEC;
+		}
+	}
+
+	err = bt_ccp_call_control_client_discover(default_conn,
+						  &clients[bt_conn_index(default_conn)]);
+	if (err != 0) {
+		shell_error(sh, "Failed to discover GTBS: %d", err);
+
+		return -ENOEXEC;
+	}
+
+	return 0;
+}
+
+static int cmd_ccp_call_control_client(const struct shell *sh, size_t argc, char **argv)
+{
+	if (argc > 1) {
+		shell_error(sh, "%s unknown parameter: %s", argv[0], argv[1]);
+	} else {
+		shell_error(sh, "%s Missing subcommand", argv[0]);
+	}
+
+	return -ENOEXEC;
+}
+
+SHELL_STATIC_SUBCMD_SET_CREATE(ccp_call_control_client_cmds,
+			       SHELL_CMD_ARG(discover, NULL,
+					     "Discover GTBS and TBS on remote device",
+					     cmd_ccp_call_control_client_discover, 1, 0),
+			       SHELL_SUBCMD_SET_END);
+
+SHELL_CMD_ARG_REGISTER(ccp_call_control_client, &ccp_call_control_client_cmds,
+		       "Bluetooth CCP Call Control Client shell commands",
+		       cmd_ccp_call_control_client, 1, 1);
diff --git a/subsys/bluetooth/audio/shell/csip_set_member.c b/subsys/bluetooth/audio/shell/csip_set_member.c
index 03a19820aba..96e94b872d3 100644
--- a/subsys/bluetooth/audio/shell/csip_set_member.c
+++ b/subsys/bluetooth/audio/shell/csip_set_member.c
@@ -380,8 +380,8 @@ SHELL_CMD_ARG_REGISTER(csip_set_member, &csip_set_member_cmds,
 		       "Bluetooth CSIP set member shell commands",
 		       cmd_csip_set_member, 1, 1);
 
-ssize_t csis_ad_data_add(struct bt_data *data_array, const size_t data_array_size,
-			 const bool discoverable)
+size_t csis_ad_data_add(struct bt_data *data_array, const size_t data_array_size,
+			const bool discoverable)
 {
 	size_t ad_len = 0;
 
@@ -401,7 +401,8 @@ ssize_t csis_ad_data_add(struct bt_data *data_array, const size_t data_array_siz
 		err = bt_csip_set_member_generate_rsi(svc_inst, ad_rsi);
 		if (err != 0) {
 			bt_shell_error("Failed to generate RSI (err %d)", err);
-			return err;
+
+			return 0;
 		}
 
 		__ASSERT(data_array_size > ad_len, "No space for AD_RSI");
diff --git a/subsys/bluetooth/audio/shell/gmap.c b/subsys/bluetooth/audio/shell/gmap.c
index 93f3fe19f2f..cde9087c66b 100644
--- a/subsys/bluetooth/audio/shell/gmap.c
+++ b/subsys/bluetooth/audio/shell/gmap.c
@@ -29,6 +29,7 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/sys/util_macro.h>
 
+#include "common/bt_shell_private.h"
 #include "host/shell/bt.h"
 #include "audio.h"
 
diff --git a/subsys/bluetooth/audio/shell/has.c b/subsys/bluetooth/audio/shell/has.c
index 9f92ab7f2c7..cb4f4b070ea 100644
--- a/subsys/bluetooth/audio/shell/has.c
+++ b/subsys/bluetooth/audio/shell/has.c
@@ -20,7 +20,6 @@
 #include <zephyr/shell/shell.h>
 #include <zephyr/shell/shell_string_conv.h>
 
-#include "host/shell/bt.h"
 #include "common/bt_shell_private.h"
 
 static int preset_select(uint8_t index, bool sync)
diff --git a/subsys/bluetooth/audio/shell/micp_mic_dev.c b/subsys/bluetooth/audio/shell/micp_mic_dev.c
index fb5dd734dfe..c0c0eca487f 100644
--- a/subsys/bluetooth/audio/shell/micp_mic_dev.c
+++ b/subsys/bluetooth/audio/shell/micp_mic_dev.c
@@ -23,7 +23,6 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/types.h>
 
-#include "host/shell/bt.h"
 #include "common/bt_shell_private.h"
 
 static void micp_mic_dev_mute_cb(uint8_t mute)
diff --git a/subsys/bluetooth/audio/shell/mpl.c b/subsys/bluetooth/audio/shell/mpl.c
index 3051164859c..79d7dd3cc5e 100644
--- a/subsys/bluetooth/audio/shell/mpl.c
+++ b/subsys/bluetooth/audio/shell/mpl.c
@@ -21,8 +21,6 @@
 #include <zephyr/shell/shell.h>
 #include <zephyr/shell/shell_string_conv.h>
 
-#include "host/shell/bt.h"
-
 #include "../mpl_internal.h"
 
 LOG_MODULE_REGISTER(bt_mpl_shell, CONFIG_BT_MPL_LOG_LEVEL);
diff --git a/subsys/bluetooth/audio/shell/pbp.c b/subsys/bluetooth/audio/shell/pbp.c
index 697490236b5..d5de5b3282d 100644
--- a/subsys/bluetooth/audio/shell/pbp.c
+++ b/subsys/bluetooth/audio/shell/pbp.c
@@ -23,7 +23,6 @@
 #include <zephyr/sys/__assert.h>
 #include <zephyr/sys/util.h>
 
-#include "host/shell/bt.h"
 #include "common/bt_shell_private.h"
 
 #define PBS_DEMO                'P', 'B', 'P'
diff --git a/subsys/bluetooth/audio/tbs.c b/subsys/bluetooth/audio/tbs.c
index fb94678375f..e4d4881e88b 100644
--- a/subsys/bluetooth/audio/tbs.c
+++ b/subsys/bluetooth/audio/tbs.c
@@ -26,6 +26,7 @@
 #include <zephyr/logging/log.h>
 #include <zephyr/net_buf.h>
 #include <zephyr/sys/__assert.h>
+#include <zephyr/sys/atomic.h>
 #include <zephyr/sys/byteorder.h>
 #include <zephyr/sys/check.h>
 #include <zephyr/sys/util.h>
@@ -34,10 +35,26 @@
 
 #include "audio_internal.h"
 #include "tbs_internal.h"
+#include "common/bt_str.h"
 
 LOG_MODULE_REGISTER(bt_tbs, CONFIG_BT_TBS_LOG_LEVEL);
 
 #define BT_TBS_VALID_STATUS_FLAGS(val) ((val) <= (BIT(0) | BIT(1)))
+#define MUTEX_TIMEOUT                  K_MSEC(CONFIG_BT_TBS_LOCK_TIMEOUT)
+
+struct tbs_flags {
+	bool bearer_provider_name_changed: 1;
+	bool bearer_technology_changed: 1;
+	bool bearer_uri_schemes_supported_list_changed: 1;
+	bool bearer_signal_strength_changed: 1;
+	bool bearer_list_current_calls_changed: 1;
+	bool status_flags_changed: 1;
+	bool incoming_call_target_bearer_uri_changed: 1;
+	bool call_state_changed: 1;
+	bool termination_reason_changed: 1;
+	bool incoming_call_changed: 1;
+	bool call_friendly_name_changed: 1;
+};
 
 /* A service instance can either be a GTBS or a TBS instance */
 struct tbs_inst {
@@ -57,8 +74,6 @@ struct tbs_inst {
 	struct bt_tbs_terminate_reason terminate_reason;
 	struct bt_tbs_call calls[CONFIG_BT_TBS_MAX_CALLS];
 
-	bool notify_current_calls;
-	bool notify_call_states;
 	bool pending_signal_strength_notification;
 	struct k_work_delayable reporting_interval_work;
 
@@ -68,6 +83,22 @@ struct tbs_inst {
 	size_t attr_count;
 
 	bool authorization_required;
+
+	struct k_mutex mutex;
+	/* Flags for each client. Access and modification of these shall be guarded by the mutex */
+	struct tbs_flags flags[CONFIG_BT_MAX_CONN];
+
+	/* Control point notifications are handled separately from other notifications - We will not
+	 * accept any new control point operations while a notification is pending
+	 */
+	struct cp_ntf {
+		struct bt_tbs_call_cp_notify notification;
+
+		uint8_t conn_index; /* The conn index that triggered the request */
+		bool pending: 1;
+	} cp_ntf;
+
+	struct k_work_delayable notify_work;
 };
 
 static struct tbs_inst svc_insts[CONFIG_BT_TBS_BEARER_COUNT];
@@ -303,6 +334,116 @@ static struct tbs_inst *lookup_inst_by_uri_scheme(const uint8_t *uri, uint8_t ur
 	return NULL;
 }
 
+static void disconnected(struct bt_conn *conn, uint8_t reason)
+{
+	/* Clear pending notifications */
+	for (size_t i = 0U; i < ARRAY_SIZE(svc_insts); i++) {
+		const uint8_t conn_index = bt_conn_index(conn);
+		int err;
+
+		err = k_mutex_lock(&svc_insts[i].mutex, MUTEX_TIMEOUT);
+		if (err != 0) {
+			LOG_WRN("Failed to take mutex: %d", err);
+			/* In this case we still need to clear the data, so continue and hope for
+			 * the best
+			 */
+		}
+
+		if (svc_insts[i].cp_ntf.pending && conn_index == svc_insts[i].cp_ntf.conn_index) {
+			memset(&svc_insts[i].cp_ntf, 0, sizeof(svc_insts[i].cp_ntf));
+		}
+
+		memset(&svc_insts[i].flags[conn_index], 0, sizeof(svc_insts[i].flags[conn_index]));
+
+		if (err == 0) { /* if mutex was locked */
+			err = k_mutex_unlock(&svc_insts[i].mutex);
+			__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+		}
+	}
+}
+
+BT_CONN_CB_DEFINE(conn_cb) = {
+	.disconnected = disconnected,
+};
+
+static int notify(struct bt_conn *conn, const struct bt_uuid *uuid,
+		  const struct bt_gatt_attr *attrs, const void *value, size_t value_len)
+{
+	const uint8_t att_header_size = 3; /* opcode + handle */
+	const uint16_t att_mtu = bt_gatt_get_mtu(conn);
+
+	__ASSERT(att_mtu > att_header_size, "Could not get valid ATT MTU");
+	const uint16_t maxlen = att_mtu - att_header_size; /* Subtract opcode and handle */
+
+	if (maxlen < value_len) {
+		LOG_DBG("Truncating notification to %u (was %u)", maxlen, value_len);
+		value_len = maxlen;
+	}
+
+	/* Send notification potentially truncated to the MTU */
+	return bt_gatt_notify_uuid(conn, uuid, attrs, value, value_len);
+}
+
+struct tbs_notify_cb_info {
+	struct tbs_inst *inst;
+	const struct bt_gatt_attr *attr;
+	void (*value_cb)(struct tbs_flags *flags);
+};
+
+static void set_value_changed_cb(struct bt_conn *conn, void *data)
+{
+	struct tbs_notify_cb_info *cb_info = data;
+	struct tbs_inst *inst = cb_info->inst;
+	struct tbs_flags *flags = &inst->flags[bt_conn_index(conn)];
+	const struct bt_gatt_attr *attr = cb_info->attr;
+	struct bt_conn_info info;
+	int err;
+
+	err = bt_conn_get_info(conn, &info);
+	__ASSERT(err == 0, "Failed to get conn info: %d", err);
+
+	if (info.state != BT_CONN_STATE_CONNECTED) {
+		/* Not connected */
+		return;
+	}
+
+	if (!bt_gatt_is_subscribed(conn, attr, BT_GATT_CCC_NOTIFY)) {
+		/* Not subscribed */
+		return;
+	}
+
+	/* Set the specific flag based on the provided callback */
+	cb_info->value_cb(flags);
+
+	/* We may schedule the same work multiple times, but that is OK as scheduling the same work
+	 * multiple times is a no-op
+	 */
+	err = k_work_schedule(&inst->notify_work, K_NO_WAIT);
+	__ASSERT(err >= 0, "Failed to schedule work: %d", err);
+}
+
+static void set_value_changed(struct tbs_inst *inst, void (*value_cb)(struct tbs_flags *flags),
+			      const struct bt_uuid *uuid)
+{
+	struct tbs_notify_cb_info cb_info = {
+		.inst = inst,
+		.value_cb = value_cb,
+		.attr = bt_gatt_find_by_uuid(inst->attrs, 0, uuid),
+	};
+
+	__ASSERT(cb_info.attr != NULL, "Failed to look attribute for %s", bt_uuid_str(uuid));
+	bt_conn_foreach(BT_CONN_TYPE_LE, set_value_changed_cb, &cb_info);
+}
+
+static void set_terminate_reason_changed_cb(struct tbs_flags *flags)
+{
+	if (flags->termination_reason_changed) {
+		LOG_DBG("pending notification replaced");
+	}
+
+	flags->termination_reason_changed = true;
+}
+
 static void tbs_set_terminate_reason(struct tbs_inst *inst, uint8_t call_index, uint8_t reason)
 {
 	inst->terminate_reason.call_index = call_index;
@@ -310,8 +451,7 @@ static void tbs_set_terminate_reason(struct tbs_inst *inst, uint8_t call_index,
 	LOG_DBG("Index %u: call index 0x%02x, reason %s", inst_index(inst), call_index,
 		bt_tbs_term_reason_str(reason));
 
-	bt_gatt_notify_uuid(NULL, BT_UUID_TBS_TERMINATE_REASON, inst->attrs,
-			    (void *)&inst->terminate_reason, sizeof(inst->terminate_reason));
+	set_value_changed(inst, set_terminate_reason_changed_cb, BT_UUID_TBS_TERMINATE_REASON);
 }
 
 /**
@@ -481,34 +621,33 @@ static void net_buf_put_current_calls(const struct tbs_inst *inst, struct net_bu
 	}
 }
 
-static int inst_notify_calls(const struct tbs_inst *inst)
+static void set_call_state_changed_cb(struct tbs_flags *flags)
 {
-	int err;
+	if (flags->call_state_changed) {
+		LOG_DBG("pending notification replaced");
+	}
 
-	if (inst->notify_call_states) {
-		net_buf_put_call_states(inst, &read_buf);
+	flags->call_state_changed = true;
+}
 
-		err = bt_gatt_notify_uuid(NULL, BT_UUID_TBS_CALL_STATE, inst->attrs, read_buf.data,
-					  read_buf.len);
-		if (err != 0) {
-			return err;
-		}
+static void set_list_current_calls_changed_cb(struct tbs_flags *flags)
+{
+	if (flags->bearer_list_current_calls_changed) {
+		LOG_DBG("pending notification replaced");
 	}
 
-	if (inst->notify_current_calls) {
-		net_buf_put_current_calls(inst, &read_buf);
+	flags->bearer_list_current_calls_changed = true;
+}
 
-		err = bt_gatt_notify_uuid(NULL, BT_UUID_TBS_LIST_CURRENT_CALLS, inst->attrs,
-					  read_buf.data, read_buf.len);
-		if (err != 0) {
-			return err;
-		}
-	}
+static int inst_notify_calls(struct tbs_inst *inst)
+{
+	set_value_changed(inst, set_call_state_changed_cb, BT_UUID_TBS_CALL_STATE);
+	set_value_changed(inst, set_list_current_calls_changed_cb, BT_UUID_TBS_LIST_CURRENT_CALLS);
 
 	return 0;
 }
 
-static int notify_calls(const struct tbs_inst *inst)
+static int notify_calls(struct tbs_inst *inst)
 {
 	int err;
 
@@ -533,6 +672,281 @@ static int notify_calls(const struct tbs_inst *inst)
 	return 0;
 }
 
+/**
+ * @brief Attempt to move a call in an instance from dialing to alerting
+ *
+ * This function will look through the state of an instance to see if there are any calls in the
+ * instance that are in the dialing state, and move them to the dialing state if we do not have any
+ * pending call state notification. The reason for this is that we do not have an API for the
+ * application to change from dialing to alterting state at this point, but the qualification tests
+ * require us to do this state change.
+ * Since we only notify the latest value, we need to notify dialing first for both current calls and
+ * call states, and then switch to the alerting state for the call and then notify again.
+ *
+ * @param inst The instance to attempt the state change on
+ * @retval true There was a state change
+ * @retval false There was not a state change
+ */
+static bool try_change_dialing_call_to_alerting(struct tbs_inst *inst)
+{
+	bool state_changed = false;
+
+	/* If we still have pending state change notifications, we cannot change the state
+	 * autonomously
+	 */
+	for (size_t i = 0U; i < ARRAY_SIZE(inst->flags); i++) {
+		const struct tbs_flags *flags = &inst->flags[i];
+
+		if (flags->bearer_list_current_calls_changed || flags->call_state_changed) {
+			return false;
+		}
+	}
+
+	if (!inst_is_gtbs(inst)) {
+		/* If inst is not the GTBS then we also need to ensure that GTBS is done notifying
+		 * before changing state
+		 */
+		for (size_t i = 0U; i < ARRAY_SIZE(gtbs_inst.flags); i++) {
+			const struct tbs_flags *flags = &gtbs_inst.flags[i];
+
+			if (flags->bearer_list_current_calls_changed || flags->call_state_changed) {
+				return false;
+			}
+		}
+	}
+
+	/* Check if we have any calls in the dialing state */
+	for (size_t i = 0U; i < ARRAY_SIZE(inst->calls); i++) {
+		if (inst->calls[i].state == BT_TBS_CALL_STATE_DIALING) {
+			inst->calls[i].state = BT_TBS_CALL_STATE_ALERTING;
+			state_changed = true;
+			break;
+		}
+	}
+
+	if (state_changed) {
+		notify_calls(inst);
+	}
+
+	return state_changed;
+}
+
+static void notify_handler_cb(struct bt_conn *conn, void *data)
+{
+	struct tbs_inst *inst = data;
+	struct tbs_flags *flags = &inst->flags[bt_conn_index(conn)];
+	struct bt_conn_info info;
+	int err;
+
+	err = bt_conn_get_info(conn, &info);
+	__ASSERT(err == 0, "Failed to get conn info: %d", err);
+
+	if (info.state != BT_CONN_STATE_CONNECTED) {
+		/* Not connected */
+		return;
+	}
+
+	if (!inst_is_gtbs(inst)) {
+		notify_handler_cb(conn, &gtbs_inst);
+	}
+
+	err = k_mutex_lock(&inst->mutex, K_NO_WAIT);
+	if (err != 0) {
+		LOG_DBG("Failed to take mutex: %d", err);
+		goto reschedule;
+	}
+
+	if (flags->bearer_provider_name_changed) {
+		LOG_DBG("Notifying Bearer Provider Name: %s", inst->provider_name);
+
+		err = notify(conn, BT_UUID_TBS_PROVIDER_NAME, inst->attrs, inst->provider_name,
+			     strlen(inst->provider_name));
+		if (err == 0) {
+			flags->bearer_provider_name_changed = false;
+		} else {
+			goto fail;
+		}
+	}
+
+	if (flags->bearer_technology_changed) {
+		LOG_DBG("Notifying Bearer Technology: %s (0x%02x)",
+			bt_tbs_technology_str(inst->technology), inst->technology);
+
+		err = notify(conn, BT_UUID_TBS_TECHNOLOGY, inst->attrs, &inst->technology,
+			     sizeof(inst->technology));
+		if (err == 0) {
+			flags->bearer_technology_changed = false;
+		} else {
+			goto fail;
+		}
+	}
+
+	if (flags->bearer_uri_schemes_supported_list_changed) {
+		LOG_DBG("Notifying Bearer URI schemes supported list: %s", inst->uri_scheme_list);
+
+		err = notify(conn, BT_UUID_TBS_URI_LIST, inst->attrs, &inst->uri_scheme_list,
+			     strlen(inst->uri_scheme_list));
+		if (err == 0) {
+			flags->bearer_uri_schemes_supported_list_changed = false;
+		} else {
+			goto fail;
+		}
+	}
+
+	if (flags->bearer_signal_strength_changed) {
+		LOG_DBG("Notifying Bearer Signal Strength: 0x%02x", inst->signal_strength);
+
+		err = notify(conn, BT_UUID_TBS_SIGNAL_STRENGTH, inst->attrs, &inst->signal_strength,
+			     sizeof(inst->signal_strength));
+		if (err == 0) {
+			flags->bearer_signal_strength_changed = false;
+		} else {
+			goto fail;
+		}
+	}
+
+	if (flags->bearer_list_current_calls_changed) {
+		LOG_DBG("Notifying Bearer List Current Calls");
+
+		net_buf_put_current_calls(inst, &read_buf);
+		err = notify(conn, BT_UUID_TBS_LIST_CURRENT_CALLS, inst->attrs, read_buf.data,
+			     read_buf.len);
+		if (err == 0) {
+			flags->bearer_list_current_calls_changed = false;
+		} else {
+			goto fail;
+		}
+
+		if (try_change_dialing_call_to_alerting(inst)) {
+			goto reschedule;
+		}
+	}
+
+	if (flags->status_flags_changed) {
+		LOG_DBG("Notifying Status Flags: 0x%02x", inst->status_flags);
+
+		err = notify(conn, BT_UUID_TBS_STATUS_FLAGS, inst->attrs, &inst->status_flags,
+			     sizeof(inst->status_flags));
+		if (err == 0) {
+			flags->status_flags_changed = false;
+		} else {
+			goto fail;
+		}
+	}
+
+	if (flags->incoming_call_target_bearer_uri_changed) {
+		LOG_DBG("Notifying Incoming Call Target Bearer URI: call index 0x%02x, URI %s",
+			inst->incoming_uri.call_index, inst->incoming_uri.uri);
+
+		err = notify(conn, BT_UUID_TBS_INCOMING_URI, inst->attrs, &inst->incoming_uri,
+			     sizeof(inst->incoming_uri.call_index) +
+				     strlen(inst->incoming_uri.uri));
+		if (err == 0) {
+			flags->incoming_call_target_bearer_uri_changed = false;
+		} else {
+			goto fail;
+		}
+	}
+
+	if (flags->call_state_changed) {
+		LOG_DBG("Notifying Call States");
+
+		net_buf_put_call_states(inst, &read_buf);
+		err = notify(conn, BT_UUID_TBS_CALL_STATE, inst->attrs, read_buf.data,
+			     read_buf.len);
+		if (err == 0) {
+			flags->call_state_changed = false;
+		} else {
+			goto fail;
+		}
+
+		if (try_change_dialing_call_to_alerting(inst)) {
+			goto reschedule;
+		}
+	}
+
+	if (flags->termination_reason_changed) {
+		LOG_DBG("Notifying Bearer Provider Name: call_index 0x%02x reason 0x%02x",
+			inst->terminate_reason.call_index, inst->terminate_reason.reason);
+
+		err = notify(conn, BT_UUID_TBS_TERMINATE_REASON, inst->attrs,
+			     &inst->terminate_reason, sizeof(inst->terminate_reason));
+		if (err == 0) {
+			flags->termination_reason_changed = false;
+		} else {
+			goto fail;
+		}
+	}
+
+	if (flags->incoming_call_changed) {
+		LOG_DBG("Notifying Incoming Call: call index 0x%02x, URI %s",
+			inst->in_call.call_index, inst->in_call.uri);
+
+		err = notify(conn, BT_UUID_TBS_INCOMING_CALL, inst->attrs, &inst->in_call,
+			     sizeof(inst->in_call.call_index) + strlen(inst->in_call.uri));
+		if (err == 0) {
+			flags->incoming_call_changed = false;
+		} else {
+			goto fail;
+		}
+	}
+
+	if (flags->call_friendly_name_changed) {
+		LOG_DBG("Notifying Friendly Name: call index 0x%02x, URI %s",
+			inst->friendly_name.call_index, inst->friendly_name.uri);
+
+		err = notify(conn, BT_UUID_TBS_FRIENDLY_NAME, inst->attrs, &inst->friendly_name,
+			     sizeof(inst->friendly_name.call_index) +
+				     strlen(inst->friendly_name.uri));
+		if (err == 0) {
+			flags->call_friendly_name_changed = false;
+		} else {
+			goto fail;
+		}
+	}
+
+	/* The TBS spec is a bit unclear on this, but the TBS test spec states that the control
+	 * operation notification shall be sent after the current calls and call state
+	 * notifications, this shall be triggered after those.
+	 */
+	if (inst->cp_ntf.pending && bt_conn_index(conn) == inst->cp_ntf.conn_index &&
+	    !flags->bearer_list_current_calls_changed && !flags->call_state_changed) {
+		const struct bt_tbs_call_cp_notify *notification = &inst->cp_ntf.notification;
+
+		LOG_DBG("Notifying CCP: Call index %u, %s opcode and status %s",
+			notification->call_index, bt_tbs_opcode_str(notification->opcode),
+			bt_tbs_status_str(notification->status));
+
+		err = notify(conn, BT_UUID_TBS_CALL_CONTROL_POINT, inst->attrs, notification,
+			     sizeof(*notification));
+		if (err == 0) {
+			inst->cp_ntf.pending = false;
+		} else {
+			goto fail;
+		}
+	}
+
+fail:
+	if (err != 0) {
+		LOG_DBG("Notify failed (%d), retrying next connection interval", err);
+reschedule:
+		err = k_work_reschedule(&inst->notify_work,
+					K_USEC(BT_CONN_INTERVAL_TO_US(info.le.interval)));
+		__ASSERT(err >= 0, "Failed to reschedule work: %d", err);
+	}
+
+	err = k_mutex_unlock(&inst->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+}
+
+static void notify_work_handler(struct k_work *work)
+{
+	struct tbs_inst *inst =
+		CONTAINER_OF(k_work_delayable_from_work(work), struct tbs_inst, notify_work);
+
+	bt_conn_foreach(BT_CONN_TYPE_LE, notify_handler_cb, inst);
+}
+
 static ssize_t read_provider_name(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf,
 				  uint16_t len, uint16_t offset)
 {
@@ -690,7 +1104,6 @@ static void current_calls_cfg_changed(const struct bt_gatt_attr *attr, uint16_t
 
 	if (inst != NULL) {
 		LOG_DBG("Index %u: value 0x%04x", inst_index(inst), value);
-		inst->notify_current_calls = (value == BT_GATT_CCC_NOTIFY);
 	}
 }
 
@@ -795,22 +1208,9 @@ static void call_state_cfg_changed(const struct bt_gatt_attr *attr, uint16_t val
 
 	if (inst != NULL) {
 		LOG_DBG("Index %u: value 0x%04x", inst_index(inst), value);
-		inst->notify_call_states = (value == BT_GATT_CCC_NOTIFY);
 	}
 }
 
-static int notify_ccp(struct bt_conn *conn, const struct bt_gatt_attr *attr, uint8_t call_index,
-		      uint8_t opcode, uint8_t status)
-{
-	const struct bt_tbs_call_cp_notify ccp_not = {
-		.call_index = call_index, .opcode = opcode, .status = status};
-
-	LOG_DBG("Notifying CCP: Call index %u, %s opcode and status %s", call_index,
-		bt_tbs_opcode_str(opcode), bt_tbs_status_str(status));
-
-	return bt_gatt_notify(conn, attr, &ccp_not, sizeof(ccp_not));
-}
-
 static void hold_other_calls(struct tbs_inst *inst, uint8_t call_index_cnt,
 			     const uint8_t *call_indexes)
 {
@@ -958,10 +1358,6 @@ static int originate_call(struct tbs_inst *inst, const struct bt_tbs_call_cp_ori
 
 	hold_other_calls(inst, 1, &call->index);
 
-	notify_calls(inst);
-	call->state = BT_TBS_CALL_STATE_ALERTING;
-	notify_calls(inst);
-
 	LOG_DBG("New call with call index %u", call->index);
 
 	*call_index = call->index;
@@ -1078,9 +1474,7 @@ static void notify_app(struct bt_conn *conn, struct tbs_inst *inst, uint16_t len
 			remote_party_alerted = tbs_cbs->originate_call(conn, call_index, uri);
 		}
 
-		if (remote_party_alerted) {
-			call->state = BT_TBS_CALL_STATE_ALERTING;
-		} else {
+		if (!remote_party_alerted) {
 			const struct bt_tbs_call_cp_term term = {
 				.call_index = call_index, .opcode = BT_TBS_CALL_OPCODE_TERMINATE};
 
@@ -1088,8 +1482,6 @@ static void notify_app(struct bt_conn *conn, struct tbs_inst *inst, uint16_t len
 			terminate_call(inst, &term, BT_TBS_REASON_CALL_FAILED);
 		}
 
-		notify_calls(inst);
-
 		break;
 	}
 	case BT_TBS_CALL_OPCODE_JOIN: {
@@ -1113,6 +1505,30 @@ static void notify_app(struct bt_conn *conn, struct tbs_inst *inst, uint16_t len
 	}
 }
 
+static bool is_valid_cp_len(uint16_t len, const union bt_tbs_call_cp_t *ccp)
+{
+	if (len < sizeof(ccp->opcode)) {
+		return false;
+	}
+
+	switch (ccp->opcode) {
+	case BT_TBS_CALL_OPCODE_ACCEPT:
+		return len == sizeof(ccp->accept);
+	case BT_TBS_CALL_OPCODE_TERMINATE:
+		return len == sizeof(ccp->terminate);
+	case BT_TBS_CALL_OPCODE_HOLD:
+		return len == sizeof(ccp->hold);
+	case BT_TBS_CALL_OPCODE_RETRIEVE:
+		return len == sizeof(ccp->retrieve);
+	case BT_TBS_CALL_OPCODE_ORIGINATE:
+		return len >= sizeof(ccp->originate) + BT_TBS_MIN_URI_LEN;
+	case BT_TBS_CALL_OPCODE_JOIN:
+		return len >= sizeof(ccp->join) + 1; /* at least 1 call index */
+	default:
+		return true; /* defer to future checks */
+	}
+}
+
 static ssize_t write_call_cp(struct bt_conn *conn, const struct bt_gatt_attr *attr, const void *buf,
 			     uint16_t len, uint16_t offset, uint8_t flags)
 {
@@ -1122,6 +1538,8 @@ static ssize_t write_call_cp(struct bt_conn *conn, const struct bt_gatt_attr *at
 	uint8_t status;
 	uint8_t call_index = 0;
 	const bool is_gtbs = inst_is_gtbs(inst);
+	bool calls_changed = false;
+	int err;
 
 	if (!is_authorized(inst, conn)) {
 		return BT_GATT_ERR(BT_ATT_ERR_AUTHORIZATION);
@@ -1131,19 +1549,28 @@ static ssize_t write_call_cp(struct bt_conn *conn, const struct bt_gatt_attr *at
 		return BT_GATT_ERR(BT_ATT_ERR_INVALID_OFFSET);
 	}
 
-	if (len < sizeof(ccp->opcode)) {
+	if (!is_valid_cp_len(len, ccp)) {
 		return BT_GATT_ERR(BT_ATT_ERR_INVALID_ATTRIBUTE_LEN);
 	}
 
 	LOG_DBG("Index %u: Processing the %s opcode", inst_index(inst),
 		bt_tbs_opcode_str(ccp->opcode));
 
+	err = k_mutex_lock(&inst->mutex, MUTEX_TIMEOUT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex");
+		return -EBUSY;
+	}
+
+	if (inst->cp_ntf.pending) {
+		err = k_mutex_unlock(&inst->mutex);
+		__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
+		return BT_GATT_ERR(BT_TBS_RESULT_CODE_OPERATION_NOT_POSSIBLE);
+	}
+
 	switch (ccp->opcode) {
 	case BT_TBS_CALL_OPCODE_ACCEPT:
-		if (len != sizeof(ccp->accept)) {
-			return BT_GATT_ERR(BT_ATT_ERR_INVALID_ATTRIBUTE_LEN);
-		}
-
 		call_index = ccp->accept.call_index;
 
 		if (is_gtbs) {
@@ -1159,10 +1586,6 @@ static ssize_t write_call_cp(struct bt_conn *conn, const struct bt_gatt_attr *at
 		status = accept_call(tbs, &ccp->accept);
 		break;
 	case BT_TBS_CALL_OPCODE_TERMINATE:
-		if (len != sizeof(ccp->terminate)) {
-			return BT_GATT_ERR(BT_ATT_ERR_INVALID_ATTRIBUTE_LEN);
-		}
-
 		call_index = ccp->terminate.call_index;
 
 		if (is_gtbs) {
@@ -1178,10 +1601,6 @@ static ssize_t write_call_cp(struct bt_conn *conn, const struct bt_gatt_attr *at
 		status = terminate_call(tbs, &ccp->terminate, BT_TBS_REASON_CLIENT_TERMINATED);
 		break;
 	case BT_TBS_CALL_OPCODE_HOLD:
-		if (len != sizeof(ccp->hold)) {
-			return BT_GATT_ERR(BT_ATT_ERR_INVALID_ATTRIBUTE_LEN);
-		}
-
 		call_index = ccp->hold.call_index;
 
 		if (is_gtbs) {
@@ -1197,10 +1616,6 @@ static ssize_t write_call_cp(struct bt_conn *conn, const struct bt_gatt_attr *at
 		status = tbs_hold_call(tbs, &ccp->hold);
 		break;
 	case BT_TBS_CALL_OPCODE_RETRIEVE:
-		if (len != sizeof(ccp->retrieve)) {
-			return BT_GATT_ERR(BT_ATT_ERR_INVALID_ATTRIBUTE_LEN);
-		}
-
 		call_index = ccp->retrieve.call_index;
 
 		if (is_gtbs) {
@@ -1218,10 +1633,6 @@ static ssize_t write_call_cp(struct bt_conn *conn, const struct bt_gatt_attr *at
 	case BT_TBS_CALL_OPCODE_ORIGINATE: {
 		const uint16_t uri_len = len - sizeof(ccp->originate);
 
-		if (len < sizeof(ccp->originate) + BT_TBS_MIN_URI_LEN) {
-			return BT_GATT_ERR(BT_ATT_ERR_INVALID_ATTRIBUTE_LEN);
-		}
-
 		if (is_gtbs) {
 			tbs = lookup_inst_by_uri_scheme(ccp->originate.uri, uri_len);
 			if (tbs == NULL) {
@@ -1237,11 +1648,6 @@ static ssize_t write_call_cp(struct bt_conn *conn, const struct bt_gatt_attr *at
 	}
 	case BT_TBS_CALL_OPCODE_JOIN: {
 		const uint16_t call_index_cnt = len - sizeof(ccp->join);
-
-		if (len < sizeof(ccp->join) + 1) { /* at least 1 call index */
-			return BT_GATT_ERR(BT_ATT_ERR_INVALID_ATTRIBUTE_LEN);
-		}
-
 		call_index = ccp->join.call_indexes[0];
 
 		if (is_gtbs) {
@@ -1284,12 +1690,31 @@ static ssize_t write_call_cp(struct bt_conn *conn, const struct bt_gatt_attr *at
 		call_index = 0;
 	}
 
-	if (conn != NULL) {
-		notify_ccp(conn, attr, call_index, ccp->opcode, status);
-	} /* else local operation; don't notify */
-
 	if (tbs != NULL && status == BT_TBS_RESULT_CODE_SUCCESS) {
 		notify_calls(tbs);
+		calls_changed = true;
+	}
+
+	if (conn != NULL && bt_gatt_is_subscribed(conn, attr, BT_GATT_CCC_NOTIFY)) {
+		struct bt_tbs_call_cp_notify *notification = &inst->cp_ntf.notification;
+
+		notification->call_index = call_index;
+		notification->opcode = ccp->opcode;
+		notification->status = status;
+		inst->cp_ntf.pending = true;
+		inst->cp_ntf.conn_index = bt_conn_index(conn);
+
+		/* We may schedule the same work multiple times, but that is OK as scheduling the
+		 * same work multiple times is a no-op
+		 */
+		err = k_work_schedule(&inst->notify_work, K_NO_WAIT);
+		__ASSERT(err >= 0, "Failed to schedule work: %d", err);
+	} /* else local operation; don't notify */
+
+	err = k_mutex_unlock(&inst->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
+	if (calls_changed) {
 		notify_app(conn, tbs, len, ccp, status, call_index);
 	}
 
@@ -1533,6 +1958,10 @@ static int tbs_inst_init_and_register(struct tbs_inst *inst, struct bt_gatt_serv
 	inst->authorization_required = param->authorization_required;
 
 	k_work_init_delayable(&inst->reporting_interval_work, signal_interval_timeout);
+	k_work_init_delayable(&inst->notify_work, notify_work_handler);
+
+	ret = k_mutex_init(&inst->mutex);
+	__ASSERT(ret == 0, "Failed to initialize mutex");
 
 	ret = bt_gatt_service_register(svc);
 	if (ret != 0) {
@@ -1623,7 +2052,7 @@ static bool valid_register_param(const struct bt_tbs_register_param *param)
 
 int bt_tbs_register_bearer(const struct bt_tbs_register_param *param)
 {
-	int ret;
+	int ret = -ENOEXEC;
 
 	CHECKIF(!valid_register_param(param)) {
 		LOG_DBG("Invalid parameters");
@@ -1734,6 +2163,13 @@ int bt_tbs_accept(uint8_t call_index)
 	int status = -EINVAL;
 	const struct bt_tbs_call_cp_acc ccp = {.call_index = call_index,
 					       .opcode = BT_TBS_CALL_OPCODE_ACCEPT};
+	int err;
+
+	err = k_mutex_lock(&inst->mutex, K_NO_WAIT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex");
+		return -EBUSY;
+	}
 
 	if (inst != NULL) {
 		status = accept_call(inst, &ccp);
@@ -1743,6 +2179,9 @@ int bt_tbs_accept(uint8_t call_index)
 		notify_calls(inst);
 	}
 
+	err = k_mutex_unlock(&inst->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
 	return status;
 }
 
@@ -1754,10 +2193,23 @@ int bt_tbs_hold(uint8_t call_index)
 						.opcode = BT_TBS_CALL_OPCODE_HOLD};
 
 	if (inst != NULL) {
+		int err;
+
+		err = k_mutex_lock(&inst->mutex, K_NO_WAIT);
+		if (err != 0) {
+			LOG_DBG("Failed to lock mutex");
+			return -EBUSY;
+		}
+
 		status = tbs_hold_call(inst, &ccp);
-	}
 
-	notify_calls(inst);
+		if (status == BT_TBS_RESULT_CODE_SUCCESS) {
+			notify_calls(inst);
+		}
+
+		err = k_mutex_unlock(&inst->mutex);
+		__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+	}
 
 	return status;
 }
@@ -1770,10 +2222,23 @@ int bt_tbs_retrieve(uint8_t call_index)
 						    .opcode = BT_TBS_CALL_OPCODE_RETRIEVE};
 
 	if (inst != NULL) {
+		int err;
+
+		err = k_mutex_lock(&inst->mutex, K_NO_WAIT);
+		if (err != 0) {
+			LOG_DBG("Failed to lock mutex");
+			return -EBUSY;
+		}
+
 		status = retrieve_call(inst, &ccp);
-	}
 
-	notify_calls(inst);
+		if (status == BT_TBS_RESULT_CODE_SUCCESS) {
+			notify_calls(inst);
+		}
+
+		err = k_mutex_unlock(&inst->mutex);
+		__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+	}
 
 	return status;
 }
@@ -1786,22 +2251,37 @@ int bt_tbs_terminate(uint8_t call_index)
 						.opcode = BT_TBS_CALL_OPCODE_TERMINATE};
 
 	if (inst != NULL) {
+		int err;
+
+		err = k_mutex_lock(&inst->mutex, K_NO_WAIT);
+		if (err != 0) {
+			LOG_DBG("Failed to lock mutex");
+			return -EBUSY;
+		}
+
 		status = terminate_call(inst, &ccp, BT_TBS_REASON_SERVER_ENDED_CALL);
-	}
 
-	notify_calls(inst);
+		if (status == BT_TBS_RESULT_CODE_SUCCESS) {
+			notify_calls(inst);
+		}
+
+		err = k_mutex_unlock(&inst->mutex);
+		__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+	}
 
 	return status;
 }
 
 int bt_tbs_originate(uint8_t bearer_index, char *remote_uri, uint8_t *call_index)
 {
-	struct tbs_inst *tbs = inst_lookup_index(bearer_index);
+	struct tbs_inst *inst = inst_lookup_index(bearer_index);
 	uint8_t buf[CONFIG_BT_TBS_MAX_URI_LENGTH + sizeof(struct bt_tbs_call_cp_originate)];
 	struct bt_tbs_call_cp_originate *ccp = (struct bt_tbs_call_cp_originate *)buf;
 	size_t uri_len;
+	int err;
+	int ret;
 
-	if (tbs == NULL) {
+	if (inst == NULL) {
 		LOG_DBG("Could not find TBS instance from index %u", bearer_index);
 		return -EINVAL;
 	} else if (!bt_tbs_valid_uri((uint8_t *)remote_uri, strlen(remote_uri))) {
@@ -1809,12 +2289,28 @@ int bt_tbs_originate(uint8_t bearer_index, char *remote_uri, uint8_t *call_index
 		return -EINVAL;
 	}
 
+	err = k_mutex_lock(&inst->mutex, K_NO_WAIT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex");
+		return -EBUSY;
+	}
+
 	uri_len = strlen(remote_uri);
 
 	ccp->opcode = BT_TBS_CALL_OPCODE_ORIGINATE;
 	(void)memcpy(ccp->uri, remote_uri, uri_len);
 
-	return originate_call(tbs, ccp, uri_len, call_index);
+	ret = originate_call(inst, ccp, uri_len, call_index);
+
+	/* In the case that we are not connected to any TBS clients, we won't notify and we can
+	 * attempt to change state from dialing to alerting immediately
+	 */
+	(void)try_change_dialing_call_to_alerting(inst);
+
+	err = k_mutex_unlock(&inst->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
+	return ret;
 }
 
 int bt_tbs_join(uint8_t call_index_cnt, uint8_t *call_indexes)
@@ -1831,11 +2327,26 @@ int bt_tbs_join(uint8_t call_index_cnt, uint8_t *call_indexes)
 	}
 
 	if (inst != NULL) {
+		int err;
+
+		err = k_mutex_lock(&inst->mutex, K_NO_WAIT);
+		if (err != 0) {
+			LOG_DBG("Failed to lock mutex");
+			return -EBUSY;
+		}
+
 		ccp->opcode = BT_TBS_CALL_OPCODE_JOIN;
 		(void)memcpy(ccp->call_indexes, call_indexes,
 			     MIN(call_index_cnt, CONFIG_BT_TBS_MAX_CALLS));
 
 		status = join_calls(inst, ccp, call_index_cnt);
+
+		if (status == BT_TBS_RESULT_CODE_SUCCESS) {
+			notify_calls(inst);
+		}
+
+		err = k_mutex_unlock(&inst->mutex);
+		__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
 	}
 
 	return status;
@@ -1845,6 +2356,8 @@ int bt_tbs_remote_answer(uint8_t call_index)
 {
 	struct tbs_inst *inst = lookup_inst_by_call_index(call_index);
 	struct bt_tbs_call *call;
+	int err;
+	int ret;
 
 	if (inst == NULL) {
 		return BT_TBS_RESULT_CODE_INVALID_CALL_INDEX;
@@ -1856,13 +2369,26 @@ int bt_tbs_remote_answer(uint8_t call_index)
 		return BT_TBS_RESULT_CODE_INVALID_CALL_INDEX;
 	}
 
+	err = k_mutex_lock(&inst->mutex, K_NO_WAIT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex");
+		return -EBUSY;
+	}
+
 	if (call->state == BT_TBS_CALL_STATE_ALERTING) {
 		call->state = BT_TBS_CALL_STATE_ACTIVE;
 		notify_calls(inst);
-		return BT_TBS_RESULT_CODE_SUCCESS;
+		ret = BT_TBS_RESULT_CODE_SUCCESS;
 	} else {
-		return BT_TBS_RESULT_CODE_STATE_MISMATCH;
+		LOG_DBG("Call with index %u Invalid state %s", call_index,
+			bt_tbs_state_str(call->state));
+		ret = BT_TBS_RESULT_CODE_STATE_MISMATCH;
 	}
+
+	err = k_mutex_unlock(&inst->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
+	return ret;
 }
 
 int bt_tbs_remote_hold(uint8_t call_index)
@@ -1870,6 +2396,7 @@ int bt_tbs_remote_hold(uint8_t call_index)
 	struct tbs_inst *inst = lookup_inst_by_call_index(call_index);
 	struct bt_tbs_call *call;
 	uint8_t status;
+	int err;
 
 	if (inst == NULL) {
 		return BT_TBS_RESULT_CODE_INVALID_CALL_INDEX;
@@ -1881,6 +2408,12 @@ int bt_tbs_remote_hold(uint8_t call_index)
 		return BT_TBS_RESULT_CODE_INVALID_CALL_INDEX;
 	}
 
+	err = k_mutex_lock(&inst->mutex, K_NO_WAIT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex");
+		return -EBUSY;
+	}
+
 	if (call->state == BT_TBS_CALL_STATE_ACTIVE) {
 		call->state = BT_TBS_CALL_STATE_REMOTELY_HELD;
 		status = BT_TBS_RESULT_CODE_SUCCESS;
@@ -1895,6 +2428,9 @@ int bt_tbs_remote_hold(uint8_t call_index)
 		notify_calls(inst);
 	}
 
+	err = k_mutex_unlock(&inst->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
 	return status;
 }
 
@@ -1903,6 +2439,7 @@ int bt_tbs_remote_retrieve(uint8_t call_index)
 	struct tbs_inst *inst = lookup_inst_by_call_index(call_index);
 	struct bt_tbs_call *call;
 	int status;
+	int err;
 
 	if (inst == NULL) {
 		return BT_TBS_RESULT_CODE_INVALID_CALL_INDEX;
@@ -1914,6 +2451,11 @@ int bt_tbs_remote_retrieve(uint8_t call_index)
 		return BT_TBS_RESULT_CODE_INVALID_CALL_INDEX;
 	}
 
+	err = k_mutex_lock(&inst->mutex, K_NO_WAIT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex");
+		return -EBUSY;
+	}
 	if (call->state == BT_TBS_CALL_STATE_REMOTELY_HELD) {
 		call->state = BT_TBS_CALL_STATE_ACTIVE;
 		status = BT_TBS_RESULT_CODE_SUCCESS;
@@ -1928,6 +2470,9 @@ int bt_tbs_remote_retrieve(uint8_t call_index)
 		notify_calls(inst);
 	}
 
+	err = k_mutex_unlock(&inst->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
 	return status;
 }
 
@@ -1939,50 +2484,76 @@ int bt_tbs_remote_terminate(uint8_t call_index)
 						.opcode = BT_TBS_CALL_OPCODE_TERMINATE};
 
 	if (inst != NULL) {
+		int err;
+
+		err = k_mutex_lock(&inst->mutex, K_NO_WAIT);
+		if (err != 0) {
+			LOG_DBG("Failed to lock mutex");
+			return -EBUSY;
+		}
 		status = terminate_call(inst, &ccp, BT_TBS_REASON_REMOTE_ENDED_CALL);
-	}
 
-	notify_calls(inst);
+		if (status == BT_TBS_RESULT_CODE_SUCCESS) {
+			notify_calls(inst);
+		}
+
+		err = k_mutex_unlock(&inst->mutex);
+		__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+	}
 
 	return status;
 }
 
+static void set_incoming_call_target_bearer_uri_changed_cb(struct tbs_flags *flags)
+{
+	if (flags->incoming_call_target_bearer_uri_changed) {
+		LOG_DBG("pending notification replaced");
+	}
+
+	flags->incoming_call_target_bearer_uri_changed = true;
+}
+
+static void set_incoming_call_changed_cb(struct tbs_flags *flags)
+{
+	if (flags->incoming_call_changed) {
+		LOG_DBG("pending notification replaced");
+	}
+
+	flags->incoming_call_changed = true;
+}
+
+static void set_call_friendly_name_changed_cb(struct tbs_flags *flags)
+{
+	if (flags->call_friendly_name_changed) {
+		LOG_DBG("pending notification replaced");
+	}
+
+	flags->call_friendly_name_changed = true;
+}
+
 static void tbs_inst_remote_incoming(struct tbs_inst *inst, const char *to, const char *from,
 				     const char *friendly_name, const struct bt_tbs_call *call)
 {
-	size_t local_uri_ind_len;
-	size_t remote_uri_ind_len;
-	size_t friend_name_ind_len;
-
 	__ASSERT_NO_MSG(to != NULL);
 	__ASSERT_NO_MSG(from != NULL);
 
-	local_uri_ind_len = strlen(to) + 1;
-	remote_uri_ind_len = strlen(from) + 1;
-
 	inst->in_call.call_index = call->index;
 	(void)utf8_lcpy(inst->in_call.uri, from, sizeof(inst->in_call.uri));
+	set_value_changed(inst, set_incoming_call_target_bearer_uri_changed_cb,
+			  BT_UUID_TBS_INCOMING_URI);
 
 	inst->incoming_uri.call_index = call->index;
 	(void)utf8_lcpy(inst->incoming_uri.uri, to, sizeof(inst->incoming_uri.uri));
-
-	bt_gatt_notify_uuid(NULL, BT_UUID_TBS_INCOMING_URI, inst->attrs, &inst->incoming_uri,
-			    local_uri_ind_len);
-
-	bt_gatt_notify_uuid(NULL, BT_UUID_TBS_INCOMING_CALL, inst->attrs, &inst->in_call,
-			    remote_uri_ind_len);
+	set_value_changed(inst, set_incoming_call_changed_cb, BT_UUID_TBS_INCOMING_CALL);
 
 	if (friendly_name) {
 		inst->friendly_name.call_index = call->index;
 		utf8_lcpy(inst->friendly_name.uri, friendly_name, sizeof(inst->friendly_name.uri));
-		friend_name_ind_len = strlen(from) + 1;
-
-		bt_gatt_notify_uuid(NULL, BT_UUID_TBS_FRIENDLY_NAME, inst->attrs,
-				    &inst->friendly_name, friend_name_ind_len);
 	} else {
 		inst->friendly_name.call_index = BT_TBS_FREE_CALL_INDEX;
-		bt_gatt_notify_uuid(NULL, BT_UUID_TBS_FRIENDLY_NAME, inst->attrs, NULL, 0);
 	}
+
+	set_value_changed(inst, set_call_friendly_name_changed_cb, BT_UUID_TBS_FRIENDLY_NAME);
 }
 
 int bt_tbs_remote_incoming(uint8_t bearer_index, const char *to, const char *from,
@@ -1990,6 +2561,7 @@ int bt_tbs_remote_incoming(uint8_t bearer_index, const char *to, const char *fro
 {
 	struct tbs_inst *inst = inst_lookup_index(bearer_index);
 	struct bt_tbs_call *call = NULL;
+	int err;
 
 	if (inst == NULL) {
 		LOG_DBG("Could not find TBS instance from index %u", bearer_index);
@@ -2007,6 +2579,11 @@ int bt_tbs_remote_incoming(uint8_t bearer_index, const char *to, const char *fro
 		return -ENOMEM;
 	}
 
+	err = k_mutex_lock(&inst->mutex, K_NO_WAIT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex");
+		return -EBUSY;
+	}
 	BT_TBS_CALL_FLAG_SET_INCOMING(call->flags);
 
 	/* Notify TBS*/
@@ -2021,15 +2598,24 @@ int bt_tbs_remote_incoming(uint8_t bearer_index, const char *to, const char *fro
 
 	notify_calls(inst);
 
+	err = k_mutex_unlock(&inst->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
 	LOG_DBG("New call with call index %u", call->index);
 
 	return call->index;
 }
 
+static void set_bearer_provider_name_changed_cb(struct tbs_flags *flags)
+{
+	flags->bearer_provider_name_changed = true;
+}
+
 int bt_tbs_set_bearer_provider_name(uint8_t bearer_index, const char *name)
 {
 	struct tbs_inst *inst = inst_lookup_index(bearer_index);
 	const size_t len = strlen(name);
+	int err;
 
 	if (len >= CONFIG_BT_TBS_MAX_PROVIDER_NAME_LENGTH || len == 0) {
 		return -EINVAL;
@@ -2041,16 +2627,31 @@ int bt_tbs_set_bearer_provider_name(uint8_t bearer_index, const char *name)
 		return 0;
 	}
 
+	err = k_mutex_lock(&inst->mutex, K_NO_WAIT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex");
+		return -EBUSY;
+	}
+
 	(void)utf8_lcpy(inst->provider_name, name, sizeof(inst->provider_name));
 
-	bt_gatt_notify_uuid(NULL, BT_UUID_TBS_PROVIDER_NAME, inst->attrs, inst->provider_name,
-			    strlen(inst->provider_name));
+	set_value_changed(inst, set_bearer_provider_name_changed_cb, BT_UUID_TBS_PROVIDER_NAME);
+
+	err = k_mutex_unlock(&inst->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
 	return 0;
 }
 
+static void set_bearer_technology_changed_cb(struct tbs_flags *flags)
+{
+	flags->bearer_technology_changed = true;
+}
+
 int bt_tbs_set_bearer_technology(uint8_t bearer_index, uint8_t new_technology)
 {
 	struct tbs_inst *inst = inst_lookup_index(bearer_index);
+	int err;
 
 	if (new_technology < BT_TBS_TECHNOLOGY_3G || new_technology > BT_TBS_TECHNOLOGY_WCDMA) {
 		return -EINVAL;
@@ -2062,10 +2663,18 @@ int bt_tbs_set_bearer_technology(uint8_t bearer_index, uint8_t new_technology)
 		return 0;
 	}
 
+	err = k_mutex_lock(&inst->mutex, K_NO_WAIT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex");
+		return -EBUSY;
+	}
+
 	inst->technology = new_technology;
 
-	bt_gatt_notify_uuid(NULL, BT_UUID_TBS_TECHNOLOGY, inst->attrs, &inst->technology,
-			    sizeof(inst->technology));
+	set_value_changed(inst, set_bearer_technology_changed_cb, BT_UUID_TBS_TECHNOLOGY);
+
+	err = k_mutex_unlock(&inst->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
 
 	return 0;
 }
@@ -2099,9 +2708,15 @@ int bt_tbs_set_signal_strength(uint8_t bearer_index, uint8_t new_signal_strength
 	return 0;
 }
 
+static void set_status_flags_changed_cb(struct tbs_flags *flags)
+{
+	flags->status_flags_changed = true;
+}
+
 int bt_tbs_set_status_flags(uint8_t bearer_index, uint16_t status_flags)
 {
 	struct tbs_inst *inst = inst_lookup_index(bearer_index);
+	int err;
 
 	if (!BT_TBS_VALID_STATUS_FLAGS(status_flags)) {
 		return -EINVAL;
@@ -2113,18 +2728,33 @@ int bt_tbs_set_status_flags(uint8_t bearer_index, uint16_t status_flags)
 		return 0;
 	}
 
+	err = k_mutex_lock(&inst->mutex, K_NO_WAIT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex");
+		return -EBUSY;
+	}
+
 	inst->status_flags = status_flags;
 
-	bt_gatt_notify_uuid(NULL, BT_UUID_TBS_STATUS_FLAGS, inst->attrs, &status_flags,
-			    sizeof(status_flags));
+	set_value_changed(inst, set_status_flags_changed_cb, BT_UUID_TBS_STATUS_FLAGS);
+
+	err = k_mutex_unlock(&inst->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
 	return 0;
 }
 
+static void set_bearer_uri_schemes_supported_list_changed_cb(struct tbs_flags *flags)
+{
+	flags->bearer_uri_schemes_supported_list_changed = true;
+}
+
 int bt_tbs_set_uri_scheme_list(uint8_t bearer_index, const char **uri_list, uint8_t uri_count)
 {
 	char uri_scheme_list[CONFIG_BT_TBS_MAX_SCHEME_LIST_LENGTH];
 	size_t len = 0;
 	struct tbs_inst *inst;
+	int err;
 
 	NET_BUF_SIMPLE_DEFINE(uri_scheme_buf, READ_BUF_SIZE);
 
@@ -2159,13 +2789,19 @@ int bt_tbs_set_uri_scheme_list(uint8_t bearer_index, const char **uri_list, uint
 		return 0;
 	}
 
+	err = k_mutex_lock(&inst->mutex, K_NO_WAIT);
+	if (err != 0) {
+		LOG_DBG("Failed to lock mutex");
+		return -EBUSY;
+	}
+
 	/* Store final result */
 	(void)utf8_lcpy(inst->uri_scheme_list, uri_scheme_list, sizeof(inst->uri_scheme_list));
 
 	LOG_DBG("TBS instance %u uri prefix list is now %s", bearer_index, inst->uri_scheme_list);
 
-	bt_gatt_notify_uuid(NULL, BT_UUID_TBS_URI_LIST, inst->attrs, &inst->uri_scheme_list,
-			    strlen(inst->uri_scheme_list));
+	set_value_changed(inst, set_bearer_uri_schemes_supported_list_changed_cb,
+			  BT_UUID_TBS_URI_LIST);
 
 	if (!inst_is_gtbs(inst)) {
 		/* If the instance is different than the GTBS notify on the GTBS instance as well */
@@ -2188,9 +2824,13 @@ int bt_tbs_set_uri_scheme_list(uint8_t bearer_index, const char **uri_list, uint
 
 		LOG_DBG("GTBS: URI scheme %.*s", uri_scheme_buf.len, uri_scheme_buf.data);
 
-		bt_gatt_notify_uuid(NULL, BT_UUID_TBS_URI_LIST, gtbs_inst.attrs,
-				    uri_scheme_buf.data, uri_scheme_buf.len);
+		set_value_changed(&gtbs_inst, set_bearer_uri_schemes_supported_list_changed_cb,
+				  BT_UUID_TBS_URI_LIST);
 	}
+
+	err = k_mutex_unlock(&inst->mutex);
+	__ASSERT(err == 0, "Failed to unlock mutex: %d", err);
+
 	return 0;
 }
 
diff --git a/subsys/bluetooth/audio/tbs_client.c b/subsys/bluetooth/audio/tbs_client.c
index db8e081f83e..f22af7c2e3e 100644
--- a/subsys/bluetooth/audio/tbs_client.c
+++ b/subsys/bluetooth/audio/tbs_client.c
@@ -19,7 +19,6 @@
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gatt.h>
 #include <zephyr/bluetooth/uuid.h>
-#include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
@@ -853,12 +852,16 @@ static void tbs_client_discover_complete(struct bt_conn *conn, int err)
 
 static bool can_add_string_to_net_buf(const struct net_buf_simple *buf, size_t len)
 {
-	return buf->len + len + sizeof('\0') <= buf->size;
+	return buf->len + len + sizeof(char) /* NULL terminator size */ <= buf->size;
 }
 
-/* Common function to read tbs_client strings which may require long reads */
-static uint8_t handle_string_long_read(struct bt_tbs_instance *inst, uint8_t err, const void *data,
-				       uint16_t offset, uint16_t length, bool truncatable)
+/**
+ * Common function to read tbs_client strings which may require long reads
+ *
+ * @return BT_GATT_ITER_CONTINUE, BT_GATT_ITER_STOP or a negative value if there's an error
+ */
+static int handle_string_long_read(struct bt_tbs_instance *inst, uint8_t err, const void *data,
+				   uint16_t offset, uint16_t length, bool truncatable)
 {
 	if (err != 0) {
 		LOG_DBG("err: %u", err);
@@ -877,7 +880,8 @@ static uint8_t handle_string_long_read(struct bt_tbs_instance *inst, uint8_t err
 				 * terminator
 				 */
 				LOG_DBG("Truncating string");
-				length = net_buf_simple_tailroom(&inst->net_buf) - sizeof('\0');
+				length = net_buf_simple_tailroom(&inst->net_buf) -
+					 sizeof(char) /* NULL terminator size */;
 				net_buf_simple_add_mem(&inst->net_buf, data, length);
 
 				/* Ensure that the data is correctly truncated */
@@ -890,7 +894,9 @@ static uint8_t handle_string_long_read(struct bt_tbs_instance *inst, uint8_t err
 
 			return BT_GATT_ITER_CONTINUE;
 		}
-	}
+	} /* else we are done reading and since the buffer is always 0-initialized, it will have the
+	   *  NULL terminator automatically
+	   */
 
 	return BT_GATT_ITER_STOP;
 }
diff --git a/subsys/bluetooth/common/Kconfig b/subsys/bluetooth/common/Kconfig
index a9c17ebceec..6159d2f3d0d 100644
--- a/subsys/bluetooth/common/Kconfig
+++ b/subsys/bluetooth/common/Kconfig
@@ -78,15 +78,23 @@ config BT_BUF_ACL_RX_SIZE
 	  that the Controller will send to the Host.
 
 config BT_BUF_ACL_RX_COUNT_EXTRA
-	int "Number of extra incoming ACL data buffers"
+	# As Host implementation unconditionally references this Kconfig, we
+	# hide it for !BT_CONN and default to 0.
+	int "Number of extra incoming ACL data buffers" if BT_CONN
+	range 1 65535 if BT_CONN
+	default BT_MAX_CONN if BT_CONN
+	range 0 0
 	default 0
-	range 0 65535
 	help
 	  Number of incoming extra ACL data buffers sent from the Controller to
 	  the Host.
 
-	  By default, the number of incoming ACL data buffers is equal to
-	  CONFIG_BT_MAX_CONN + 1.
+	  By default, the total number of incoming ACL data buffers is equal to
+	  CONFIG_BT_MAX_CONN + 1, to support L2CAP recombination.
+
+	  The L2CAP recombination in the Host keeps the first Rx buffer for each
+	  connection and uses one Rx buffer across all connections to receive a
+	  fragment from the Controller.
 
 config BT_BUF_ACL_RX_COUNT
 	int "[DEPRECATED] Number of incoming ACL data buffers"
@@ -183,12 +191,48 @@ config BT_BUF_CMD_TX_SIZE
 	  to the maximum of 255.
 
 config BT_BUF_CMD_TX_COUNT
-	int "Number of HCI command buffers"
-	default 2
-	range 2 64
+	# This option is only visible for a user when Host and Controller are build together, or for
+	# Host-only builds.
+	int "Number of HCI command buffers" if !BT_HCI_RAW || !HAS_BT_CTLR
+	# This option is present when Host and Controller are build together, or
+	# for Host only builds, or when Controller-to-Host ACL data flow control
+	# is disabled.
+	depends on !BT_HCI_RAW || !HAS_BT_CTLR || !BT_HCI_ACL_FLOW_CONTROL
+	# The Mesh stack usage in applications and tests can start both advertising and scanning in
+	# parallel. Also, when BT_MESH_WORKQ_SYS is enabled, the Mesh stack is starting Extended
+	# Advertising in the receive callback run in the system work queue and as the Host also uses
+	# the system work queue for HCI command Tx towards the Controller, one additional HCI
+	# command buffer is needed.
+	range 2 64 if BT_MESH
+	range 1 64
+	default 2 if BT_MESH
+	default 1
 	help
 	  Number of buffers available for outgoing HCI commands from the Host.
 
+	  HCI Controllers may not support Num_HCI_Command_Packets > 1, hence they default to 1 when
+	  not enabling Controller to Host data flow control (BT_HCI_ACL_FLOW_CONTROL), Read Remote
+	  Version Information (BT_REMOTE_VERSION), Auto-Initiate PHY update (BT_AUTO_PHY_UPDATE), or
+	  Auto-Initiate Data Length Update (BT_AUTO_DATA_LEN_UPDATE).
+
+	  Normal HCI commands follow the HCI command flow control using Num_HCI_Command_Packets
+	  return in HCI command complete and status.
+
+	  The Host Number of Completed Packets command does not follow normal flow control of HCI
+	  commands and the Controller side HCI drivers that allocates HCI command buffers with
+	  K_NO_WAIT can end up running out of command buffers.
+
+	  When Controller to Host data flow control is enabled in the Host-only or combined
+	  Host plus Controller build, the internal BT_BUF_CMD_TX_COUNT is adjusted accordingly
+	  taking into considerations the enabled auto-initiated procedures, and to follow the normal
+	  HCI command flow control to be able to send Ncmd normal HCI commands and
+	  BT_BUF_ACL_RX_COUNT of Host Number of Completed Packets command down to the Controller.
+
+	  When Controller to Host data flow control is supported in the Controller-only build,
+	  the internal BT_BUF_CMD_TX_COUNT is adjusted to be equal to (BT_BUF_RX_COUNT + Ncmd).
+
+	  Where Ncmd is supported maximum Num_HCI_Command_Packets in the Controller implementation.
+
 endmenu
 
 # Workaround to have commas on function arguments
@@ -220,7 +264,7 @@ config BT_HCI_VS_FATAL_ERROR
 config BT_HCI_VS_EXT_DETECT
 	bool "Use heuristics to guess HCI vendor extensions support in advance"
 	depends on BT_HCI_VS && !HAS_BT_CTLR
-	default y if BOARD_QEMU_X86 || BOARD_QEMU_CORTEX_M3 || BOARD_NATIVE_POSIX || BOARD_NATIVE_SIM
+	default y if BOARD_QEMU_X86 || BOARD_QEMU_CORTEX_M3 || BOARD_NATIVE_SIM
 	help
 	  Use some heuristics to try to guess in advance whether the controller
 	  supports the HCI vendor extensions in advance, in order to prevent
diff --git a/subsys/bluetooth/common/hci_common_internal.h b/subsys/bluetooth/common/hci_common_internal.h
new file mode 100644
index 00000000000..910ea4b4af3
--- /dev/null
+++ b/subsys/bluetooth/common/hci_common_internal.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#if !defined(CONFIG_BT_HCI_RAW) || !defined(CONFIG_HAS_BT_CTLR) || \
+	!defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
+/* Following build configurations use configurable CONFIG_BT_BUF_CMD_TX_COUNT:
+ * 1. Host + Controller build with and without Controller to Host data flow control, or
+ * 2. Host-only with and without Controller to Host data flow control, or
+ * 3. Controller-only without Controller to Host data flow control support
+ */
+#if !defined(CONFIG_BT_HCI_RAW)
+/* Host + Controller build, and Host-only build */
+
+/* Auto initiated additional HCI command buffers enqueued in the Host */
+#define BT_BUF_CMD_TX_REMOTE_VERSION       COND_CODE_1(CONFIG_BT_REMOTE_VERSION, (1), (0))
+#define BT_BUF_CMD_TX_AUTO_PHY_UPDATE      COND_CODE_1(CONFIG_BT_AUTO_PHY_UPDATE, (1), (0))
+#define BT_BUF_CMD_TX_AUTO_DATA_LEN_UPDATE COND_CODE_1(CONFIG_BT_AUTO_DATA_LEN_UPDATE, (1), (0))
+
+#else /* CONFIG_BT_HCI_RAW */
+#if defined(CONFIG_HAS_BT_CTLR)
+/* Controller-only build need no additional HCI command buffers */
+BUILD_ASSERT((CONFIG_BT_BUF_CMD_TX_COUNT == CONFIG_BT_CTLR_HCI_NUM_CMD_PKT_MAX),
+	     "Mismatch in allocated HCI command buffers compared to Controller supported value.");
+#endif /* CONFIG_HAS_BT_CTLR */
+
+/* Controller-only build do not enqueue auto initiated HCI commands */
+#define BT_BUF_CMD_TX_REMOTE_VERSION       0
+#define BT_BUF_CMD_TX_AUTO_PHY_UPDATE      0
+#define BT_BUF_CMD_TX_AUTO_DATA_LEN_UPDATE 0
+#endif /* !CONFIG_BT_HCI_RAW */
+
+#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
+/* When Controller to Host data flow control is supported in Host plus Controller build, or
+ * Host-only build, then we need additional BT_BUF_ACL_RX_COUNT number of HCI command buffers for
+ * enqueuing Host Number of Completed Packets command.
+ *
+ * Host keeps the first, and subsequent, Rx buffers (that comes from the driver) for each connection
+ * to do re-assembly into, up to the L2CAP SDU length required number of Rx buffers.
+ * BT_BUF_ACL_RX_COUNT_EXTRA holds the application configured number of buffers across active
+ * connections for recombination of HCI data packets to L2CAP SDUs.
+ *
+ * BT_BUF_HCI_EVT_RX_COUNT defines the number of available buffers reserved for "synchronous"
+ * processing of HCI events like Number of Completed Packets, disconnection complete etc.
+ *
+ * BT_BUF_HCI_ACL_RX_COUNT defines the number of available buffers for Controller to Host data
+ * flow control; keeping the application configured BT_BUF_ACL_RX_COUNT_EXTRA number of buffers
+ * available for L2CAP recombination, and a reserved number of buffers for processing HCI events.
+ */
+
+/* FIXME: Calculate the maximum number of HCI events of different types that a connection can
+ *        enqueue while the Host is slow at processing HCI events.
+ *
+ *        1. Disconnection Complete event
+ *        2. LE Connection Update Complete event
+ *        3. LE Long Term Key Request event
+ *        4. LE Remote Connection Parameter Request Event
+ *        5. LE Data Length Change event
+ *        6. LE PHY Update Complete event
+ *        7. ...
+ *
+ * As there is no HCI event flow control defined, implementations will need a transport level flow
+ * control to restrict buffers required on resource constraint devices, i.e. if these events are not
+ * processed "synchronous".
+ */
+#define BT_BUF_HCI_EVT_RX_COUNT          1
+#define BT_BUF_HCI_ACL_RX_COUNT          (BT_BUF_RX_COUNT - BT_BUF_HCI_EVT_RX_COUNT - \
+					  BT_BUF_ACL_RX_COUNT_EXTRA)
+#define BT_BUF_CMD_TX_HOST_NUM_CMPLT_PKT (BT_BUF_HCI_ACL_RX_COUNT)
+
+#else /* !CONFIG_BT_HCI_ACL_FLOW_CONTROL */
+#define BT_BUF_CMD_TX_HOST_NUM_CMPLT_PKT 0
+#endif /* !CONFIG_BT_HCI_ACL_FLOW_CONTROL */
+
+/* Based on Host + Controller, Host-only or Controller-only; Calculate the HCI Command Tx count. */
+#define BT_BUF_CMD_TX_COUNT (CONFIG_BT_BUF_CMD_TX_COUNT + \
+			     BT_BUF_CMD_TX_HOST_NUM_CMPLT_PKT + \
+			     BT_BUF_CMD_TX_REMOTE_VERSION + \
+			     BT_BUF_CMD_TX_AUTO_PHY_UPDATE + \
+			     BT_BUF_CMD_TX_AUTO_DATA_LEN_UPDATE)
+
+#elif defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
+/* When Controller to Host data flow control is supported in the Controller-only build, ensure
+ * that BT_BUF_CMD_TX_COUNT is greater than or equal to (BT_BUF_RX_COUNT + Ncmd),
+ * where Ncmd is supported maximum Num_HCI_Command_Packets in the Controller implementation.
+ */
+BUILD_ASSERT(!IS_ENABLED(CONFIG_BT_BUF_CMD_TX_COUNT),
+	     "Configurable HCI command buffer count disallowed.");
+BUILD_ASSERT(IS_ENABLED(CONFIG_BT_CTLR_HCI_NUM_CMD_PKT_MAX),
+	     "Undefined Controller implementation supported Num_HCI_Command_Packets value.");
+
+/** Can use all of buffer count needed for HCI ACL, HCI ISO or Event RX buffers for ACL RX */
+#define BT_BUF_HCI_ACL_RX_COUNT (BT_BUF_RX_COUNT)
+
+/* Controller-only with Controller to Host data flow control */
+#define BT_BUF_CMD_TX_COUNT     (BT_BUF_RX_COUNT + CONFIG_BT_CTLR_HCI_NUM_CMD_PKT_MAX)
+
+#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */
diff --git a/subsys/bluetooth/controller/Kconfig b/subsys/bluetooth/controller/Kconfig
index f1ef0786d3f..a3b63b0fbf0 100644
--- a/subsys/bluetooth/controller/Kconfig
+++ b/subsys/bluetooth/controller/Kconfig
@@ -161,6 +161,16 @@ config BT_CTLR_HCI
 	  This should almost always be enabled, except in a few special
 	  cases, like for unit testing.
 
+config BT_CTLR_HCI_NUM_CMD_PKT_MAX
+	# Hidden Controller implementation supported Num_HCI_Command_Packets value.
+	# This value will be used to calculate the total number of HCI command buffers to be
+	# allocated, BT_BUF_CMD_TX_COUNT, dependent on HCI Controller to Host data flow control
+	# being enabled.
+	int
+	depends on BT_CTLR_HCI
+	default 1 if BT_LL_SW_SPLIT
+	default 1
+
 if HAS_BT_CTLR
 
 comment "Bluetooth Controller configuration"
@@ -329,13 +339,29 @@ choice BT_CTLR_TX_PWR
 	  The value set here represents the actual default power level fed
 	  to the antenna.
 
+config BT_CTLR_TX_PWR_PLUS_21
+	bool "+21 dBm"
+	depends on SOC_FAMILY_ESPRESSIF_ESP32
+
+config BT_CTLR_TX_PWR_PLUS_18
+	bool "+18 dBm"
+	depends on SOC_FAMILY_ESPRESSIF_ESP32
+
+config BT_CTLR_TX_PWR_PLUS_15
+	bool "+15 dBm"
+	depends on SOC_FAMILY_ESPRESSIF_ESP32
+
+config BT_CTLR_TX_PWR_PLUS_12
+	bool "+12 dBm"
+	depends on SOC_FAMILY_ESPRESSIF_ESP32
+
 config BT_CTLR_TX_PWR_PLUS_10
 	bool "+10 dBm"
 	depends on SOC_SERIES_NRF54HX
 
 config BT_CTLR_TX_PWR_PLUS_9
 	bool "+9 dBm"
-	depends on SOC_SERIES_NRF54HX
+	depends on SOC_SERIES_NRF54HX || SOC_FAMILY_ESPRESSIF_ESP32
 
 config BT_CTLR_TX_PWR_PLUS_8
 	bool "+8 dBm"
@@ -347,7 +373,7 @@ config BT_CTLR_TX_PWR_PLUS_7
 
 config BT_CTLR_TX_PWR_PLUS_6
 	bool "+6 dBm"
-	depends on HAS_HW_NRF_RADIO_TX_PWR_HIGH || SOC_SERIES_NRF54HX || SOC_COMPATIBLE_NRF54LX
+	depends on HAS_HW_NRF_RADIO_TX_PWR_HIGH || SOC_SERIES_NRF54HX || SOC_COMPATIBLE_NRF54LX || SOC_FAMILY_ESPRESSIF_ESP32
 
 config BT_CTLR_TX_PWR_PLUS_5
 	bool "+5 dBm"
@@ -359,7 +385,7 @@ config BT_CTLR_TX_PWR_PLUS_4
 
 config BT_CTLR_TX_PWR_PLUS_3
 	bool "+3 dBm"
-	depends on SOC_COMPATIBLE_NRF52X || SOC_COMPATIBLE_NRF53X || SOC_SERIES_NRF54HX || SOC_COMPATIBLE_NRF54LX
+	depends on SOC_COMPATIBLE_NRF52X || SOC_COMPATIBLE_NRF53X || SOC_SERIES_NRF54HX || SOC_COMPATIBLE_NRF54LX || SOC_FAMILY_ESPRESSIF_ESP32
 
 config BT_CTLR_TX_PWR_PLUS_2
 	bool "+2 dBm"
@@ -382,7 +408,7 @@ config BT_CTLR_TX_PWR_MINUS_2
 
 config BT_CTLR_TX_PWR_MINUS_3
 	bool "-3 dBm"
-	depends on SOC_COMPATIBLE_NRF53X || SOC_COMPATIBLE_NRF54LX
+	depends on SOC_COMPATIBLE_NRF53X || SOC_COMPATIBLE_NRF54LX || SOC_FAMILY_ESPRESSIF_ESP32
 
 config BT_CTLR_TX_PWR_MINUS_4
 	bool "-4 dBm"
@@ -393,7 +419,7 @@ config BT_CTLR_TX_PWR_MINUS_5
 
 config BT_CTLR_TX_PWR_MINUS_6
 	bool "-6 dBm"
-	depends on SOC_COMPATIBLE_NRF53X || SOC_COMPATIBLE_NRF54LX
+	depends on SOC_COMPATIBLE_NRF53X || SOC_COMPATIBLE_NRF54LX || SOC_FAMILY_ESPRESSIF_ESP32
 
 config BT_CTLR_TX_PWR_MINUS_7
 	bool "-7 dBm"
@@ -404,7 +430,7 @@ config BT_CTLR_TX_PWR_MINUS_8
 
 config BT_CTLR_TX_PWR_MINUS_9
 	bool "-9 dBm"
-	depends on SOC_COMPATIBLE_NRF54LX
+	depends on SOC_COMPATIBLE_NRF54LX || SOC_FAMILY_ESPRESSIF_ESP32
 
 config BT_CTLR_TX_PWR_MINUS_10
 	bool "-10 dBm"
@@ -417,12 +443,28 @@ config BT_CTLR_TX_PWR_MINUS_14
 	bool "-14 dBm"
 	depends on SOC_COMPATIBLE_NRF54LX
 
+config BT_CTLR_TX_PWR_MINUS_15
+	bool "-15 dBm"
+	depends on SOC_FAMILY_ESPRESSIF_ESP32
+
 config BT_CTLR_TX_PWR_MINUS_16
 	bool "-16 dBm"
 
+config BT_CTLR_TX_PWR_MINUS_18
+	bool "-18 dBm"
+	depends on SOC_FAMILY_ESPRESSIF_ESP32
+
 config BT_CTLR_TX_PWR_MINUS_20
 	bool "-20 dBm"
 
+config BT_CTLR_TX_PWR_MINUS_21
+	bool "-21 dBm"
+	depends on SOC_FAMILY_ESPRESSIF_ESP32
+
+config BT_CTLR_TX_PWR_MINUS_24
+	bool "-24 dBm"
+	depends on SOC_FAMILY_ESPRESSIF_ESP32
+
 config BT_CTLR_TX_PWR_MINUS_26
 	bool "-26 dBm"
 	depends on SOC_COMPATIBLE_NRF54LX
@@ -447,6 +489,10 @@ endchoice
 
 config BT_CTLR_TX_PWR_DBM
 	int
+	default 21 if BT_CTLR_TX_PWR_PLUS_21
+	default 18 if BT_CTLR_TX_PWR_PLUS_18
+	default 15 if BT_CTLR_TX_PWR_PLUS_15
+	default 12 if BT_CTLR_TX_PWR_PLUS_12
 	default 10 if BT_CTLR_TX_PWR_PLUS_10
 	default 9 if BT_CTLR_TX_PWR_PLUS_9
 	default 8 if BT_CTLR_TX_PWR_PLUS_8
@@ -470,8 +516,12 @@ config BT_CTLR_TX_PWR_DBM
 	default -10 if BT_CTLR_TX_PWR_MINUS_10
 	default -12 if BT_CTLR_TX_PWR_MINUS_12
 	default -14 if BT_CTLR_TX_PWR_MINUS_14
+	default -15 if BT_CTLR_TX_PWR_MINUS_15
 	default -16 if BT_CTLR_TX_PWR_MINUS_16
+	default -18 if BT_CTLR_TX_PWR_MINUS_18
 	default -20 if BT_CTLR_TX_PWR_MINUS_20
+	default -21 if BT_CTLR_TX_PWR_MINUS_21
+	default -24 if BT_CTLR_TX_PWR_MINUS_24
 	default -26 if BT_CTLR_TX_PWR_MINUS_26
 	default -30 if BT_CTLR_TX_PWR_MINUS_30
 	default -40 if BT_CTLR_TX_PWR_MINUS_40
@@ -839,6 +889,7 @@ endif # BT_CTLR_SYNC_PERIODIC
 config BT_CTLR_SYNC_TRANSFER_SENDER
 	bool "Periodic Advertising Sync Transfer sender"
 	depends on BT_CTLR_SYNC_TRANSFER_SENDER_SUPPORT
+	select BT_TICKER_LAZY_GET
 	default BT_PER_ADV_SYNC_TRANSFER_SENDER
 	help
 	  Enable support for the Periodic Advertising Sync Transfer control procedure
@@ -847,9 +898,10 @@ config BT_CTLR_SYNC_TRANSFER_SENDER
 
 config BT_CTLR_ADV_ISO
 	bool "LE Broadcast Isochronous Channel advertising" if !BT_LL_SW_SPLIT
-	depends on BT_BROADCASTER && BT_CTLR_ADV_ISO_SUPPORT
+	depends on BT_ISO_BROADCASTER && BT_CTLR_ADV_ISO_SUPPORT
 	select BT_CTLR_ADV_PERIODIC
 	select BT_CTLR_SET_HOST_FEATURE
+	select BT_CTLR_ADV_ISO_SEQUENTIAL if !BT_CTLR_ADV_ISO_INTERLEAVED
 	default y if BT_ISO_BROADCASTER
 	help
 	  Enable support for Bluetooth 5.2 LE Isochronous Advertising in the
@@ -859,11 +911,20 @@ config BT_CTLR_ADV_ISO
 	bool "LE Broadcast Isochronous Channel advertising (Split Link Layer) [EXPERIMENTAL]" if BT_LL_SW_SPLIT
 	select EXPERIMENTAL if BT_LL_SW_SPLIT
 
+config BT_CTLR_ADV_ISO_SEQUENTIAL
+	bool "LE Broadcast Isochronous Channel advertising sequential packing"
+	depends on BT_CTLR_ADV_ISO
+
+config BT_CTLR_ADV_ISO_INTERLEAVED
+	bool "LE Broadcast Isochronous Channel advertising interleaved packing"
+	depends on BT_CTLR_ADV_ISO
+
 config BT_CTLR_SYNC_ISO
 	bool "LE Broadcast Isochronous Channel advertising sync" if !BT_LL_SW_SPLIT
-	depends on BT_OBSERVER && BT_CTLR_SYNC_ISO_SUPPORT
+	depends on BT_ISO_SYNC_RECEIVER && BT_CTLR_SYNC_ISO_SUPPORT
 	select BT_CTLR_SYNC_PERIODIC
 	select BT_CTLR_SET_HOST_FEATURE
+	select BT_CTLR_SYNC_ISO_SEQUENTIAL if !BT_CTLR_SYNC_ISO_INTERLEAVED
 	default y if BT_ISO_SYNC_RECEIVER
 	help
 	  Enable support for Bluetooth 5.2 LE Isochronous Advertising sync in
@@ -873,6 +934,16 @@ config BT_CTLR_SYNC_ISO
 	bool "LE Broadcast Isochronous Channel advertising sync (Split Link Layer) [EXPERIMENTAL]" if BT_LL_SW_SPLIT
 	select EXPERIMENTAL if BT_LL_SW_SPLIT
 
+config BT_CTLR_SYNC_ISO_SEQUENTIAL
+	bool "LE Broadcast Isochronous Channel advertising sync sequential packing"
+	depends on BT_CTLR_SYNC_ISO
+	default y
+
+config BT_CTLR_SYNC_ISO_INTERLEAVED
+	bool "LE Broadcast Isochronous Channel advertising sync interleaved packing"
+	depends on BT_CTLR_SYNC_ISO
+	default y
+
 config BT_CTLR_BROADCAST_ISO
 	bool
 	default BT_CTLR_ADV_ISO || BT_CTLR_SYNC_ISO
@@ -962,7 +1033,7 @@ config BT_CTLR_SET_HOST_FEATURE
 
 config BT_CTLR_CENTRAL_ISO
 	bool "LE Connected Isochronous Stream Central" if !BT_LL_SW_SPLIT
-	depends on BT_CTLR_CENTRAL_ISO_SUPPORT && BT_CENTRAL
+	depends on BT_CTLR_CENTRAL_ISO_SUPPORT && BT_ISO_CENTRAL
 	default y if BT_ISO_CENTRAL
 	help
 	  Enable support for Bluetooth 5.2 LE Connected Isochronous Stream
@@ -970,12 +1041,14 @@ config BT_CTLR_CENTRAL_ISO
 
 config BT_CTLR_CENTRAL_ISO
 	bool "LE Connected Isochronous Stream Central (Split Link Layer) [EXPERIMENTAL]" if BT_LL_SW_SPLIT
+	depends on BT_CTLR_CENTRAL_ISO_SUPPORT && BT_ISO_CENTRAL
+	default y if BT_ISO_CENTRAL
 	select BT_CTLR_SET_HOST_FEATURE
 	select EXPERIMENTAL if BT_LL_SW_SPLIT
 
 config BT_CTLR_PERIPHERAL_ISO
 	bool "LE Connected Isochronous Stream Peripheral" if !BT_LL_SW_SPLIT
-	depends on BT_CTLR_PERIPHERAL_ISO_SUPPORT && BT_PERIPHERAL
+	depends on BT_CTLR_PERIPHERAL_ISO_SUPPORT && BT_ISO_PERIPHERAL
 	default y if BT_ISO_PERIPHERAL
 	help
 	  Enable support for Bluetooth 5.2 LE Connected Isochronous Stream
@@ -983,6 +1056,8 @@ config BT_CTLR_PERIPHERAL_ISO
 
 config BT_CTLR_PERIPHERAL_ISO
 	bool "LE Connected Isochronous Stream Peripheral (Split Link Layer) [EXPERIMENTAL]" if BT_LL_SW_SPLIT
+	depends on BT_CTLR_PERIPHERAL_ISO_SUPPORT && BT_ISO_PERIPHERAL
+	default y if BT_ISO_PERIPHERAL
 	select BT_CTLR_SET_HOST_FEATURE
 	select EXPERIMENTAL if BT_LL_SW_SPLIT
 
@@ -1023,13 +1098,13 @@ config BT_CTLR_CONN_ISO_PDU_LEN_MAX
 	help
 	  Maximum Connected Isochronous Channel PDU Length.
 
-config BT_CTLR_CONN_ISO_SDU_LEN_MAX
-	int "Maximum Connected Isochronous Channel SDU Length"
-	depends on BT_CTLR_CONN_ISO
+config BT_CTLR_ISO_TX_SDU_LEN_MAX
+	int "Maximum Isochronous Channel Transmit SDU Length"
+	depends on BT_CTLR_ADV_ISO || BT_CTLR_CONN_ISO
 	range 1 4095
-	default 251
+	default 1
 	help
-	  Maximum Connected Isochronous Channel SDU Length.
+	  Maximum Isochronous Channel Transmit SDU Length.
 
 config BT_CTLR_CONN_ISO_STREAMS_MAX_NSE
 	int "LE Connected Isochronous Streams max number of subevents"
diff --git a/subsys/bluetooth/controller/Kconfig.ll_sw_split b/subsys/bluetooth/controller/Kconfig.ll_sw_split
index 886edbfe180..de2716918f4 100644
--- a/subsys/bluetooth/controller/Kconfig.ll_sw_split
+++ b/subsys/bluetooth/controller/Kconfig.ll_sw_split
@@ -11,11 +11,10 @@ config BT_LLL_VENDOR_NORDIC
 	depends on !$(dt_nodelabel_enabled,timer0)
 	depends on !$(dt_nodelabel_enabled,rtc0)
 
-	select BT_CTLR_ENTROPY_SUPPORT if !SOC_COMPATIBLE_NRF54LX || BOARD_NRF54L15BSIM
-	select FAKE_ENTROPY_NATIVE_POSIX if BT_CTLR_ENTROPY && BOARD_NRF54L15BSIM
+	select BT_CTLR_ENTROPY_SUPPORT
 	select ENTROPY_NRF5_RNG if BT_CTLR_ENTROPY && !SOC_COMPATIBLE_NRF54LX
 	select ENTROPY_NRF5_BIAS_CORRECTION if ENTROPY_NRF5_RNG
-	select EXPERIMENTAL if !ENTROPY_HAS_DRIVER || FAKE_ENTROPY_NATIVE_POSIX
+	select EXPERIMENTAL if !ENTROPY_HAS_DRIVER
 
 	select BT_HAS_HCI_VS
 	select BT_CTLR_CRYPTO_SUPPORT
@@ -61,12 +60,13 @@ config BT_LLL_VENDOR_NORDIC
 	select BT_CTLR_TIFS_HW_SUPPORT
 	select BT_CTLR_ULL_LLL_PRIO_SUPPORT
 
-	select BT_TICKER_REMAINDER_SUPPORT
+	select BT_TICKER_REMAINDER_SUPPORT if !SOC_COMPATIBLE_NRF54LX
 	select BT_TICKER_UPDATE if BT_BROADCASTER || BT_CONN || \
 				   (BT_OBSERVER && BT_CTLR_ADV_EXT)
-	select BT_TICKER_START_REMAINDER if BT_CTLR_CENTRAL_ISO
-	select BT_TICKER_REMAINDER_GET if BT_BROADCASTER && BT_CTLR_ADV_EXT
-	select BT_TICKER_LAZY_GET if BT_CTLR_ADV_PERIODIC || BT_CTLR_CENTRAL_ISO || BT_CTLR_SYNC_TRANSFER_SENDER
+	select BT_TICKER_START_REMAINDER if BT_TICKER_REMAINDER_SUPPORT && BT_CTLR_CENTRAL_ISO
+	select BT_TICKER_REMAINDER_GET if BT_TICKER_REMAINDER_SUPPORT && \
+					  (BT_BROADCASTER && BT_CTLR_ADV_EXT)
+	select BT_TICKER_LAZY_GET if BT_CTLR_ADV_PERIODIC || BT_CTLR_CONN_ISO || BT_CTLR_SYNC_TRANSFER_SENDER
 
 	select BT_TICKER_PREFER_START_BEFORE_STOP if BT_TICKER_SLOT_AGNOSTIC
 
@@ -116,10 +116,27 @@ config BT_CTLR_TIFS_HW_SUPPORT
 config BT_CTLR_ULL_LLL_PRIO_SUPPORT
 	bool
 
+config BT_CTLR_RX_POLL
+	# Hidden, Enable Async I/O Framework, i.e. k_poll
+	bool
+	depends on BT_HCI_RAW || BT_HCI_ACL_FLOW_CONTROL
+	select POLL
+	default y
+
 config BT_CTLR_RX_PRIO_STACK_SIZE
-	# Hidden, Controller's Co-Operative high priority Rx thread stack size.
+	# Hidden
 	int
+	depends on !BT_HCI_RAW
 	default 448
+	help
+	  Controller's Co-Operative high priority Rx thread stack size.
+
+	  Rx priority thread is used in Combined Host plus Controller builds to
+	  prioritize Number of Completed Packets event and Disconnect Event
+	  towards the Host while already enqueued ACL and ISO Data are blocked
+	  in the normal Rx thread waiting for free Tx buffer be available.
+
+	  Rx priority thread is redundant in a Controller-only build.
 
 config BT_CTLR_RX_STACK_SIZE
 	# Hidden, Controller's Co-Operative Rx thread stack size.
@@ -890,8 +907,6 @@ config BT_CTLR_LOW_LAT
 config BT_CTLR_LOW_LAT_ULL
 	prompt "Low latency ULL"
 	bool
-	depends on BT_CTLR_LOW_LAT
-	default y
 	help
 	  Low latency ULL implementation that uses tailchaining instead of while
 	  loop to demux rx messages from LLL.
@@ -1088,7 +1103,7 @@ config BT_CTLR_THROUGHPUT
 
 config BT_CTLR_FORCE_MD_COUNT
 	int "Forced MD bit count" if !BT_CTLR_FORCE_MD_AUTO
-	depends on !BT_CTLR_LOW_LAT_ULL
+	depends on !BT_CTLR_LOW_LAT
 	range 0 $(UINT8_MAX)
 	default 1 if BT_CTLR_FORCE_MD_AUTO
 	default 0
@@ -1102,7 +1117,7 @@ config BT_CTLR_FORCE_MD_COUNT
 
 config BT_CTLR_FORCE_MD_AUTO
 	bool "Forced MD bit automatic calculation"
-	depends on !BT_CTLR_LOW_LAT_ULL
+	depends on !BT_CTLR_LOW_LAT
 	select BT_CTLR_THROUGHPUT
 	default y if BT_HCI_RAW
 	help
diff --git a/subsys/bluetooth/controller/hci/hci.c b/subsys/bluetooth/controller/hci/hci.c
index ba6609f7532..7081e58aee8 100644
--- a/subsys/bluetooth/controller/hci/hci.c
+++ b/subsys/bluetooth/controller/hci/hci.c
@@ -21,6 +21,8 @@
 #include <zephyr/bluetooth/hci_vs.h>
 #include <zephyr/bluetooth/buf.h>
 
+#include "common/hci_common_internal.h"
+
 #include "util/util.h"
 #include "util/memq.h"
 #include "util/mem.h"
@@ -182,13 +184,13 @@ static uint8_t sf_curr;
 #endif
 
 #if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
-int32_t    hci_hbuf_total;
-uint32_t    hci_hbuf_sent;
-uint32_t    hci_hbuf_acked;
-uint16_t    hci_hbuf_pend[CONFIG_BT_MAX_CONN];
+int32_t  hci_hbuf_total;
+uint32_t hci_hbuf_sent;
+uint32_t hci_hbuf_acked;
+uint16_t hci_hbuf_pend[CONFIG_BT_MAX_CONN];
 atomic_t hci_state_mask;
 static struct k_poll_signal *hbuf_signal;
-#endif
+#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */
 
 #if defined(CONFIG_BT_CONN)
 static uint32_t conn_count;
@@ -473,7 +475,7 @@ static void reset(struct net_buf *buf, struct net_buf **evt)
 		atomic_set_bit(&hci_state_mask, HCI_STATE_BIT_RESET);
 		k_poll_signal_raise(hbuf_signal, 0x0);
 	}
-#endif
+#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */
 
 	hci_recv_fifo_reset();
 }
@@ -521,6 +523,22 @@ static void set_ctl_to_host_flow(struct net_buf *buf, struct net_buf **evt)
 	hci_hbuf_total = -hci_hbuf_total;
 }
 
+/* Host Number of Completed Packets command does not follow normal flow
+ * control of HCI commands and the Controller side HCI drivers that
+ * allocates HCI command buffers with K_NO_WAIT can end up running out
+ * of command buffers.
+ *
+ * Host will generate up to acl_pkts number of Host Number of Completed
+ * Packets command plus a number of normal HCI commands.
+ *
+ * Normal HCI commands follow the HCI command flow control using
+ * Num_HCI_Command_Packets return in HCI command complete and status.
+ *
+ * Note: Zephyr Controller does not support Num_HCI_Command_Packets > 1.
+ */
+BUILD_ASSERT(BT_BUF_HCI_ACL_RX_COUNT < BT_BUF_CMD_TX_COUNT,
+	     "Too low HCI command buffers compare to ACL Rx buffers.");
+
 static void host_buffer_size(struct net_buf *buf, struct net_buf **evt)
 {
 	struct bt_hci_cp_host_buffer_size *cmd = (void *)buf->data;
@@ -534,15 +552,38 @@ static void host_buffer_size(struct net_buf *buf, struct net_buf **evt)
 		ccst->status = BT_HCI_ERR_CMD_DISALLOWED;
 		return;
 	}
-	/* fragmentation from controller to host not supported, require
+
+	/* Fragmentation from Controller to Host not supported, require
 	 * ACL MTU to be at least the LL MTU
 	 */
 	if (acl_mtu < LL_LENGTH_OCTETS_RX_MAX) {
+		LOG_ERR("FC: Require Host ACL MTU (%u) >= LL Max Data Length (%u)", acl_mtu,
+			LL_LENGTH_OCTETS_RX_MAX);
 		ccst->status = BT_HCI_ERR_INVALID_PARAM;
 		return;
 	}
 
-	LOG_DBG("FC: host buf size: %d", acl_pkts);
+	/* Host Number of Completed Packets command does not follow normal flow
+	 * control of HCI commands and the Controller side HCI drivers that
+	 * allocates HCI command buffers with K_NO_WAIT can end up running out
+	 * of command buffers.
+	 *
+	 * Host will generate up to acl_pkts number of Host Number of Completed
+	 * Packets command plus a number of normal HCI commands.
+	 *
+	 * Normal HCI commands follow the HCI command flow control using
+	 * Num_HCI_Command_Packets return in HCI command complete and status.
+	 *
+	 * Note: Zephyr Controller does not support Num_HCI_Command_Packets > 1.
+	 */
+	if (acl_pkts >= BT_BUF_CMD_TX_COUNT) {
+		LOG_WRN("FC: Host ACL packets (%u), BT_BUF_CMD_TX_COUNT (%u)", acl_pkts,
+			BT_BUF_CMD_TX_COUNT);
+		acl_pkts = BT_BUF_CMD_TX_COUNT - CONFIG_BT_CTLR_HCI_NUM_CMD_PKT_MAX;
+	}
+
+	LOG_DBG("FC: host buf size %u count %u", acl_mtu, acl_pkts);
+
 	hci_hbuf_total = -acl_pkts;
 }
 
@@ -584,7 +625,7 @@ static void host_num_completed_packets(struct net_buf *buf,
 	hci_hbuf_acked += count;
 	k_poll_signal_raise(hbuf_signal, 0x0);
 }
-#endif
+#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */
 
 #if defined(CONFIG_BT_CTLR_LE_PING)
 static void read_auth_payload_timeout(struct net_buf *buf, struct net_buf **evt)
@@ -745,7 +786,7 @@ static int ctrl_bb_cmd_handle(uint16_t  ocf, struct net_buf *cmd,
 	case BT_OCF(BT_HCI_OP_HOST_NUM_COMPLETED_PACKETS):
 		host_num_completed_packets(cmd, evt);
 		break;
-#endif
+#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */
 
 #if defined(CONFIG_BT_CTLR_LE_PING)
 	case BT_OCF(BT_HCI_OP_READ_AUTH_PAYLOAD_TIMEOUT):
@@ -5876,7 +5917,6 @@ int hci_iso_handle(struct net_buf *buf, struct net_buf **evt)
 	struct bt_hci_iso_sdu_hdr *iso_sdu_hdr;
 	struct isoal_sdu_tx sdu_frag_tx;
 	struct bt_hci_iso_hdr *iso_hdr;
-	uint32_t *time_stamp;
 	uint16_t handle;
 	uint8_t pb_flag;
 	uint8_t ts_flag;
@@ -5924,9 +5964,8 @@ int hci_iso_handle(struct net_buf *buf, struct net_buf **evt)
 	sdu_frag_tx.cntr_time_stamp = HAL_TICKER_TICKS_TO_US(ticker_ticks_now_get());
 	if (ts_flag) {
 		/* Use HCI provided time stamp */
-		time_stamp = net_buf_pull_mem(buf, sizeof(*time_stamp));
-		len -= sizeof(*time_stamp);
-		sdu_frag_tx.time_stamp = sys_le32_to_cpu(*time_stamp);
+		sdu_frag_tx.time_stamp = net_buf_pull_le32(buf);
+		len -= sizeof(uint32_t);
 	} else {
 		/* Use controller's capture time */
 		sdu_frag_tx.time_stamp = sdu_frag_tx.cntr_time_stamp;
@@ -5966,6 +6005,7 @@ int hci_iso_handle(struct net_buf *buf, struct net_buf **evt)
 		struct ll_conn_iso_group *cig;
 		struct ll_iso_stream_hdr *hdr;
 		struct ll_iso_datapath *dp_in;
+		uint32_t sdu_interval;
 		uint8_t event_offset;
 
 		cis = ll_iso_stream_connected_get(handle);
@@ -5976,23 +6016,35 @@ int hci_iso_handle(struct net_buf *buf, struct net_buf **evt)
 		cig = cis->group;
 
 		/* We must ensure sufficient time for ISO-AL to fragment SDU and
-		 * deliver PDUs to the TX queue. By checking ull_ref_get, we
-		 * know if we are within the subevents of an ISO event. If so,
-		 * we can assume that we have enough time to deliver in the next
-		 * ISO event. If we're not active within the ISO event, we don't
-		 * know if there is enough time to deliver in the next event,
-		 * and for safety we set the target to current event + 2.
-		 *
-		 * For FT > 1, we have the opportunity to retransmit in later
+		 * deliver PDUs to the TX queue. We don't know if there is enough
+		 * time to deliver in the next event, and for safety we set the
+		 * target to current event + 2.
+		 */
+		event_offset = 2;
+
+		if (cig->lll.role) {
+			/* peripheral */
+			sdu_interval = cig->p_sdu_interval;
+		} else {
+			/* central */
+			sdu_interval = cig->c_sdu_interval;
+		}
+
+		/* By checking ull_ref_get, we know if we are within the subevents
+		 * of an ISO event. If so, we can assume that we have enough time
+		 * to deliver in the next ISO event, provided CIG sync delay is less
+		 * than an SDU interval
+		 */
+		if (ull_ref_get(&cig->ull) && cig->sync_delay < sdu_interval) {
+			event_offset -= 1;
+		}
+
+		/* For FT > 1, we have the opportunity to retransmit in later
 		 * event(s), in which case we have the option to target an
 		 * earlier event (this or next) because being late does not
 		 * instantly flush the payload.
 		 */
-
-		event_offset = ull_ref_get(&cig->ull) ? 1 : 2;
-
 		if (cis->lll.tx.ft > 1) {
-			/* FT > 1, target an earlier event */
 			event_offset -= 1;
 		}
 
@@ -6001,7 +6053,7 @@ int hci_iso_handle(struct net_buf *buf, struct net_buf **evt)
 		uint64_t pkt_seq_num;
 
 		/* Catch up local pkt_seq_num with internal pkt_seq_num */
-		event_count = cis->lll.event_count + event_offset;
+		event_count = cis->lll.event_count_prepare + event_offset;
 		pkt_seq_num = event_count + 1U;
 
 		/* If pb_flag is BT_ISO_START (0b00) or BT_ISO_SINGLE (0b10)
@@ -6044,7 +6096,7 @@ int hci_iso_handle(struct net_buf *buf, struct net_buf **evt)
 						   ISO_INT_UNIT_US));
 
 #else /* !CONFIG_BT_CTLR_ISOAL_PSN_IGNORE */
-		sdu_frag_tx.target_event = cis->lll.event_count + event_offset;
+		sdu_frag_tx.target_event = cis->lll.event_count_prepare + event_offset;
 		sdu_frag_tx.grp_ref_point =
 			isoal_get_wrapped_time_us(cig->cig_ref_point,
 						  (event_offset *
@@ -8739,6 +8791,15 @@ static void encode_control(struct node_rx_pdu *node_rx,
 
 	case NODE_RX_TYPE_TERMINATE:
 		hci_disconn_complete_encode(pdu_data, handle, buf);
+
+#if !defined(CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE)
+		/* Similar to the design of processing the termination when using Rx priority
+		 * thread, we process the termination event to handle Controller to Host data
+		 * flowcontrol in the Controller here.
+		 */
+		hci_disconn_complete_process(handle);
+#endif /* CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE */
+
 		break;
 
 	case NODE_RX_TYPE_CONN_UPDATE:
@@ -9119,7 +9180,7 @@ void hci_acl_encode(struct node_rx_pdu *node_rx, struct net_buf *buf)
 			LL_ASSERT(handle < ARRAY_SIZE(hci_hbuf_pend));
 			hci_hbuf_pend[handle]++;
 		}
-#endif
+#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */
 		break;
 
 	default:
@@ -9325,6 +9386,7 @@ void hci_init(struct k_poll_signal *signal_host_buf)
 {
 #if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
 	hbuf_signal = signal_host_buf;
-#endif
+#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */
+
 	reset(NULL, NULL);
 }
diff --git a/subsys/bluetooth/controller/hci/hci_driver.c b/subsys/bluetooth/controller/hci/hci_driver.c
index 1f856e56f6a..0ba42a67282 100644
--- a/subsys/bluetooth/controller/hci/hci_driver.c
+++ b/subsys/bluetooth/controller/hci/hci_driver.c
@@ -25,7 +25,7 @@
 
 #ifdef CONFIG_CLOCK_CONTROL_NRF
 #include <zephyr/drivers/clock_control/nrf_clock_control.h>
-#endif
+#endif /* CONFIG_CLOCK_CONTROL_NRF */
 
 #include "hal/debug.h"
 
@@ -72,12 +72,9 @@ struct hci_driver_data {
 	bt_hci_recv_t recv;
 };
 
-static struct k_sem sem_prio_recv;
+static struct k_sem sem_recv;
 static struct k_fifo recv_fifo;
 
-struct k_thread prio_recv_thread_data;
-static K_KERNEL_STACK_DEFINE(prio_recv_thread_stack,
-			     CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE);
 struct k_thread recv_thread_data;
 static K_KERNEL_STACK_DEFINE(recv_thread_stack, CONFIG_BT_CTLR_RX_STACK_SIZE);
 
@@ -85,67 +82,9 @@ static K_KERNEL_STACK_DEFINE(recv_thread_stack, CONFIG_BT_CTLR_RX_STACK_SIZE);
 static struct k_poll_signal hbuf_signal;
 static sys_slist_t hbuf_pend;
 static int32_t hbuf_count;
-#endif
-
-#define BT_HCI_EVT_FLAG_RECV_PRIO BIT(0)
-#define BT_HCI_EVT_FLAG_RECV      BIT(1)
-
-/** @brief Get HCI event flags.
- *
- * Helper for the HCI driver to get HCI event flags that describes rules that.
- * must be followed.
- *
- * @param evt HCI event code.
- *
- * @return HCI event flags for the specified event.
- */
-static inline uint8_t bt_hci_evt_get_flags(uint8_t evt)
-{
-	switch (evt) {
-	case BT_HCI_EVT_DISCONN_COMPLETE:
-		return BT_HCI_EVT_FLAG_RECV | BT_HCI_EVT_FLAG_RECV_PRIO;
-		/* fallthrough */
-#if defined(CONFIG_BT_CONN) || defined(CONFIG_BT_ISO)
-	case BT_HCI_EVT_NUM_COMPLETED_PACKETS:
-#if defined(CONFIG_BT_CONN)
-	case BT_HCI_EVT_DATA_BUF_OVERFLOW:
-		__fallthrough;
-#endif /* defined(CONFIG_BT_CONN) */
-#endif /* CONFIG_BT_CONN ||  CONFIG_BT_ISO */
-	case BT_HCI_EVT_CMD_COMPLETE:
-	case BT_HCI_EVT_CMD_STATUS:
-		return BT_HCI_EVT_FLAG_RECV_PRIO;
-	default:
-		return BT_HCI_EVT_FLAG_RECV;
-	}
-}
-
-/* Copied here from `hci_raw.c`, which would be used in
- * conjunction with this driver when serializing HCI over wire.
- * This serves as a converter from the historical (removed from
- * tree) 'recv blocking' API to the normal single-receiver
- * `bt_recv` API.
- */
-static int bt_recv_prio(const struct device *dev, struct net_buf *buf)
-{
-	struct hci_driver_data *data = dev->data;
-
-	if (bt_buf_get_type(buf) == BT_BUF_EVT) {
-		struct bt_hci_evt_hdr *hdr = (void *)buf->data;
-		uint8_t evt_flags = bt_hci_evt_get_flags(hdr->evt);
-
-		if ((evt_flags & BT_HCI_EVT_FLAG_RECV_PRIO) &&
-		    (evt_flags & BT_HCI_EVT_FLAG_RECV)) {
-			/* Avoid queuing the event twice */
-			return 0;
-		}
-	}
-
-	return data->recv(dev, buf);
-}
+#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */
 
 #if defined(CONFIG_BT_CTLR_ISO)
-
 #define SDU_HCI_HDR_SIZE (BT_HCI_ISO_HDR_SIZE + BT_HCI_ISO_SDU_TS_HDR_SIZE)
 
 isoal_status_t sink_sdu_alloc_hci(const struct isoal_sink    *sink_ctx,
@@ -176,7 +115,7 @@ isoal_status_t sink_sdu_emit_hci(const struct isoal_sink             *sink_ctx,
 				 const struct isoal_emitted_sdu      *sdu)
 {
 	const struct device *dev = DEVICE_DT_GET(DT_DRV_INST(0));
-	struct hci_driver_data *data = dev->data;
+	const struct hci_driver_data *data = dev->data;
 	struct bt_hci_iso_sdu_ts_hdr *sdu_hdr;
 	uint16_t packet_status_flag;
 	struct bt_hci_iso_hdr *hdr;
@@ -279,21 +218,68 @@ isoal_status_t sink_sdu_write_hci(void *dbuf,
 
 	return ISOAL_STATUS_OK;
 }
-#endif
+#endif /* CONFIG_BT_CTLR_ISO */
 
-void hci_recv_fifo_reset(void)
+#if defined(CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE)
+struct k_thread prio_recv_thread_data;
+static K_KERNEL_STACK_DEFINE(prio_recv_thread_stack,
+			     CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE);
+
+#define BT_HCI_EVT_FLAG_RECV_PRIO BIT(0)
+#define BT_HCI_EVT_FLAG_RECV      BIT(1)
+
+/** @brief Get HCI event flags.
+ *
+ * Helper for the HCI driver to get HCI event flags that describes rules that.
+ * must be followed.
+ *
+ * @param evt HCI event code.
+ *
+ * @return HCI event flags for the specified event.
+ */
+static inline uint8_t bt_hci_evt_get_flags(uint8_t evt)
 {
-	/* NOTE: As there is no equivalent API to wake up a waiting thread and
-	 * reinitialize the queue so it is empty, we use the cancel wait and
-	 * initialize the queue. As the Tx thread and Rx thread are co-operative
-	 * we should be relatively safe doing the below.
-	 * Added k_sched_lock and k_sched_unlock, as native_posix seems to
-	 * swap to waiting thread on call to k_fifo_cancel_wait!.
-	 */
-	k_sched_lock();
-	k_fifo_cancel_wait(&recv_fifo);
-	k_fifo_init(&recv_fifo);
-	k_sched_unlock();
+	switch (evt) {
+	case BT_HCI_EVT_DISCONN_COMPLETE:
+		return BT_HCI_EVT_FLAG_RECV | BT_HCI_EVT_FLAG_RECV_PRIO;
+		/* fallthrough */
+#if defined(CONFIG_BT_CONN) || defined(CONFIG_BT_ISO)
+	case BT_HCI_EVT_NUM_COMPLETED_PACKETS:
+#if defined(CONFIG_BT_CONN)
+	case BT_HCI_EVT_DATA_BUF_OVERFLOW:
+		__fallthrough;
+#endif /* CONFIG_BT_CONN */
+#endif /* CONFIG_BT_CONN ||  CONFIG_BT_ISO */
+	case BT_HCI_EVT_CMD_COMPLETE:
+	case BT_HCI_EVT_CMD_STATUS:
+		return BT_HCI_EVT_FLAG_RECV_PRIO;
+	default:
+		return BT_HCI_EVT_FLAG_RECV;
+	}
+}
+
+/* Copied here from `hci_raw.c`, which would be used in
+ * conjunction with this driver when serializing HCI over wire.
+ * This serves as a converter from the historical (removed from
+ * tree) 'recv blocking' API to the normal single-receiver
+ * `bt_recv` API.
+ */
+static int bt_recv_prio(const struct device *dev, struct net_buf *buf)
+{
+	const struct hci_driver_data *data = dev->data;
+
+	if (bt_buf_get_type(buf) == BT_BUF_EVT) {
+		struct bt_hci_evt_hdr *hdr = (void *)buf->data;
+		uint8_t evt_flags = bt_hci_evt_get_flags(hdr->evt);
+
+		if ((evt_flags & BT_HCI_EVT_FLAG_RECV_PRIO) &&
+		    (evt_flags & BT_HCI_EVT_FLAG_RECV)) {
+			/* Avoid queuing the event twice */
+			return 0;
+		}
+	}
+
+	return data->recv(dev, buf);
 }
 
 static struct net_buf *process_prio_evt(struct node_rx_pdu *node_rx,
@@ -341,8 +327,6 @@ static void prio_recv_thread(void *p1, void *p2, void *p3)
 		uint8_t num_cmplt;
 		uint16_t handle;
 
-		iso_received = false;
-
 #if defined(CONFIG_BT_CTLR_SYNC_ISO) || defined(CONFIG_BT_CTLR_CONN_ISO)
 		node_rx = ll_iso_rx_get();
 		if (node_rx) {
@@ -358,21 +342,29 @@ static void prio_recv_thread(void *p1, void *p2, void *p3)
 			k_fifo_put(&recv_fifo, node_rx);
 
 			iso_received = true;
+		} else {
+			iso_received = false;
 		}
-#endif /* CONFIG_BT_CTLR_SYNC_ISO || CONFIG_BT_CTLR_CONN_ISO */
+
+#else /* !CONFIG_BT_CTLR_SYNC_ISO && !CONFIG_BT_CTLR_CONN_ISO */
+		iso_received = false;
+#endif /* !CONFIG_BT_CTLR_SYNC_ISO && !CONFIG_BT_CTLR_CONN_ISO */
 
 		/* While there are completed rx nodes */
 		while ((num_cmplt = ll_rx_get((void *)&node_rx, &handle))) {
-#if defined(CONFIG_BT_CONN) || defined(CONFIG_BT_CTLR_ADV_ISO) || \
-	defined(CONFIG_BT_CTLR_CONN_ISO)
+#if defined(CONFIG_BT_CONN) || defined(CONFIG_BT_CTLR_ADV_ISO)
+			int err;
 
 			buf = bt_buf_get_evt(BT_HCI_EVT_NUM_COMPLETED_PACKETS,
 					     false, K_FOREVER);
 			hci_num_cmplt_encode(buf, handle, num_cmplt);
 			LOG_DBG("Num Complete: 0x%04x:%u", handle, num_cmplt);
-			bt_recv_prio(dev, buf);
+
+			err = bt_recv_prio(dev, buf);
+			LL_ASSERT(err == 0);
+
 			k_yield();
-#endif /* CONFIG_BT_CONN || CONFIG_BT_CTLR_ADV_ISO || CONFIG_BT_CTLR_CONN_ISO */
+#endif /* CONFIG_BT_CONN || CONFIG_BT_CTLR_ADV_ISO */
 		}
 
 		if (node_rx) {
@@ -388,13 +380,17 @@ static void prio_recv_thread(void *p1, void *p2, void *p3)
 
 			buf = process_prio_evt(node_rx, &evt_flags);
 			if (buf) {
+				int err;
+
 				LOG_DBG("Priority event");
 				if (!(evt_flags & BT_HCI_EVT_FLAG_RECV)) {
 					node_rx->hdr.next = NULL;
 					ll_rx_mem_release((void **)&node_rx);
 				}
 
-				bt_recv_prio(dev, buf);
+				err = bt_recv_prio(dev, buf);
+				LL_ASSERT(err == 0);
+
 				/* bt_recv_prio would not release normal evt
 				 * buf.
 				 */
@@ -425,12 +421,114 @@ static void prio_recv_thread(void *p1, void *p2, void *p3)
 		 * Blocking-take of the semaphore; we take it once ULL mayfly
 		 * has let it go in ll_rx_sched().
 		 */
-		k_sem_take(&sem_prio_recv, K_FOREVER);
+		k_sem_take(&sem_recv, K_FOREVER);
 		/* Now, ULL mayfly has something to give to us */
 		LOG_DBG("sem taken");
 	}
 }
 
+#else /* !CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE */
+static void node_rx_recv(const struct device *dev)
+{
+#if defined(CONFIG_BT_CONN) || defined(CONFIG_BT_CTLR_ADV_ISO)
+	const struct hci_driver_data *data = dev->data;
+#endif /* CONFIG_BT_CONN || CONFIG_BT_CTLR_ADV_ISO */
+
+	struct node_rx_pdu *node_rx;
+	bool iso_received = false;
+
+	do {
+		uint8_t num_cmplt;
+		uint16_t handle;
+
+#if defined(CONFIG_BT_CTLR_SYNC_ISO) || defined(CONFIG_BT_CTLR_CONN_ISO)
+		node_rx = ll_iso_rx_get();
+		if (node_rx != NULL) {
+			ll_iso_rx_dequeue();
+
+			/* Find out and store the class for this node */
+			node_rx->hdr.user_meta = hci_get_class(node_rx);
+
+			/* Send the rx node up to Host thread,
+			 * recv_thread()
+			 */
+			LOG_DBG("ISO RX node enqueue");
+			k_fifo_put(&recv_fifo, node_rx);
+
+			iso_received = true;
+		} else {
+			iso_received = false;
+		}
+#endif /* CONFIG_BT_CTLR_SYNC_ISO || CONFIG_BT_CTLR_CONN_ISO */
+
+		/* While there are completed rx nodes */
+		num_cmplt = ll_rx_get((void *)&node_rx, &handle);
+		while (num_cmplt != 0U) {
+#if defined(CONFIG_BT_CONN) || defined(CONFIG_BT_CTLR_ADV_ISO)
+			struct net_buf *buf;
+
+			LL_ASSERT(node_rx == NULL);
+
+			buf = bt_buf_get_evt(BT_HCI_EVT_NUM_COMPLETED_PACKETS,
+					     false, K_FOREVER);
+			hci_num_cmplt_encode(buf, handle, num_cmplt);
+
+			LOG_DBG("Num Complete: 0x%04x:%u", handle, num_cmplt);
+
+			data->recv(dev, buf);
+			k_yield();
+
+#else /* !CONFIG_BT_CONN && !CONFIG_BT_CTLR_ADV_ISO */
+			LL_ASSERT(0);
+#endif /* !CONFIG_BT_CONN && !CONFIG_BT_CTLR_ADV_ISO */
+
+			num_cmplt = ll_rx_get((void *)&node_rx, &handle);
+		}
+
+		if (node_rx != NULL) {
+			/* Until now we've only peeked, now we really do
+			 * the handover
+			 */
+			ll_rx_dequeue();
+
+			/* Find out and store the class for this node */
+			node_rx->hdr.user_meta = hci_get_class(node_rx);
+
+			/* Send the rx node up to Host thread, recv_thread()
+			 */
+			LOG_DBG("RX node enqueue");
+			k_fifo_put(&recv_fifo, node_rx);
+		}
+
+		/* There may still be completed nodes, continue pushing all those up to Host before
+		 * waiting/polling for sem_recv.
+		 */
+	} while (iso_received || (node_rx != NULL));
+}
+
+static int bt_recv(const struct device *dev, struct net_buf *buf)
+{
+	const struct hci_driver_data *data = dev->data;
+
+	return data->recv(dev, buf);
+}
+#endif /* !CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE */
+
+void hci_recv_fifo_reset(void)
+{
+	/* NOTE: As there is no equivalent API to wake up a waiting thread and
+	 * reinitialize the queue so it is empty, we use the cancel wait and
+	 * initialize the queue. As the Tx thread and Rx thread are co-operative
+	 * we should be relatively safe doing the below.
+	 * Added k_sched_lock and k_sched_unlock, as native_sim seems to
+	 * swap to waiting thread on call to k_fifo_cancel_wait!.
+	 */
+	k_sched_lock();
+	k_fifo_cancel_wait(&recv_fifo);
+	k_fifo_init(&recv_fifo);
+	k_sched_unlock();
+}
+
 static inline struct net_buf *encode_node(struct node_rx_pdu *node_rx,
 					  int8_t class)
 {
@@ -458,7 +556,8 @@ static inline struct net_buf *encode_node(struct node_rx_pdu *node_rx,
 		buf = bt_buf_get_rx(BT_BUF_ACL_IN, K_FOREVER);
 		hci_acl_encode(node_rx, buf);
 		break;
-#endif
+#endif /* CONFIG_BT_CONN */
+
 #if defined(CONFIG_BT_CTLR_SYNC_ISO) || defined(CONFIG_BT_CTLR_CONN_ISO)
 	case HCI_CLASS_ISO_DATA: {
 		if (false) {
@@ -569,7 +668,7 @@ static inline struct net_buf *process_node(struct node_rx_pdu *node_rx)
 			break;
 		}
 	}
-#endif
+#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */
 
 	/* process regular node from radio */
 	buf = encode_node(node_rx, class);
@@ -665,7 +764,7 @@ static inline struct net_buf *process_hbuf(struct node_rx_pdu *n)
 
 	return buf;
 }
-#endif
+#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */
 
 /**
  * @brief Blockingly pull from Controller thread's recv_fifo
@@ -674,46 +773,86 @@ static inline struct net_buf *process_hbuf(struct node_rx_pdu *n)
 static void recv_thread(void *p1, void *p2, void *p3)
 {
 	const struct device *dev = p1;
-	struct hci_driver_data *data = dev->data;
+	const struct hci_driver_data *data = dev->data;
 
+#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL) || !defined(CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE)
+	enum {
 #if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
+		EVENT_SIGNAL,
+#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */
+
+#if !defined(CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE)
+		EVENT_SEM,
+#endif /* !CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE */
+
+		EVENT_FIFO,
+		EVENT_MAX,
+	};
+
 	/* @todo: check if the events structure really needs to be static */
-	static struct k_poll_event events[2] = {
+	static struct k_poll_event events[EVENT_MAX] = {
+#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
 		K_POLL_EVENT_STATIC_INITIALIZER(K_POLL_TYPE_SIGNAL,
 						K_POLL_MODE_NOTIFY_ONLY,
 						&hbuf_signal, 0),
+#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */
+
+#if !defined(CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE)
+		K_POLL_EVENT_STATIC_INITIALIZER(K_POLL_TYPE_SEM_AVAILABLE,
+						K_POLL_MODE_NOTIFY_ONLY,
+						&sem_recv, 0),
+#endif /* !CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE */
+
 		K_POLL_EVENT_STATIC_INITIALIZER(K_POLL_TYPE_FIFO_DATA_AVAILABLE,
 						K_POLL_MODE_NOTIFY_ONLY,
 						&recv_fifo, 0),
 	};
-#endif
+#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL || !CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE */
 
 	while (1) {
 		struct node_rx_pdu *node_rx = NULL;
 		struct net_buf *buf = NULL;
 
 		LOG_DBG("blocking");
-#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
+
+#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL) || !defined(CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE)
 		int err;
 
-		err = k_poll(events, 2, K_FOREVER);
+		err = k_poll(events, ARRAY_SIZE(events), K_FOREVER);
 		LL_ASSERT(err == 0 || err == -EINTR);
-		if (events[0].state == K_POLL_STATE_SIGNALED) {
-			events[0].signal->signaled = 0U;
-		} else if (events[1].state ==
-			   K_POLL_STATE_FIFO_DATA_AVAILABLE) {
-			node_rx = k_fifo_get(events[1].fifo, K_NO_WAIT);
+
+		if (false) {
+
+#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
+		} else if (events[EVENT_SIGNAL].state == K_POLL_STATE_SIGNALED) {
+			events[EVENT_SIGNAL].signal->signaled = 0U;
+#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */
+
+#if !defined(CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE)
+		} else if (events[EVENT_SEM].state == K_POLL_STATE_SEM_AVAILABLE) {
+			err = k_sem_take(events[EVENT_SEM].sem, K_NO_WAIT);
+			LL_ASSERT(err == 0);
+
+			node_rx_recv(dev);
+#endif /* !CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE */
+
+		} else if (events[EVENT_FIFO].state == K_POLL_STATE_FIFO_DATA_AVAILABLE) {
+			node_rx = k_fifo_get(events[EVENT_FIFO].fifo, K_NO_WAIT);
 		}
 
-		events[0].state = K_POLL_STATE_NOT_READY;
-		events[1].state = K_POLL_STATE_NOT_READY;
+		for (size_t i = 0; i < ARRAY_SIZE(events); i++) {
+			events[i].state = K_POLL_STATE_NOT_READY;
+		}
 
+#if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
 		/* process host buffers first if any */
 		buf = process_hbuf(node_rx);
+#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */
 
-#else
+#else /* !CONFIG_BT_HCI_ACL_FLOW_CONTROL && CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE */
 		node_rx = k_fifo_get(&recv_fifo, K_FOREVER);
-#endif
+#endif /* !CONFIG_BT_HCI_ACL_FLOW_CONTROL && CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE */
+
 		LOG_DBG("unblocked");
 
 		if (node_rx && !buf) {
@@ -748,20 +887,26 @@ static int cmd_handle(const struct device *dev, struct net_buf *buf)
 {
 	struct node_rx_pdu *node_rx = NULL;
 	struct net_buf *evt;
+	int err = 0;
 
 	evt = hci_cmd_handle(buf, (void **) &node_rx);
 	if (evt) {
 		LOG_DBG("Replying with event of %u bytes", evt->len);
-		bt_recv_prio(dev, evt);
 
-		if (node_rx) {
+#if defined(CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE)
+		err = bt_recv_prio(dev, evt);
+#else /* CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE */
+		err = bt_recv(dev, evt);
+#endif /* CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE */
+
+		if ((err == 0) && (node_rx != NULL)) {
 			LOG_DBG("RX node enqueue");
 			node_rx->hdr.user_meta = hci_get_class(node_rx);
 			k_fifo_put(&recv_fifo, node_rx);
 		}
 	}
 
-	return 0;
+	return err;
 }
 
 #if defined(CONFIG_BT_CONN)
@@ -773,7 +918,12 @@ static int acl_handle(const struct device *dev, struct net_buf *buf)
 	err = hci_acl_handle(buf, &evt);
 	if (evt) {
 		LOG_DBG("Replying with event of %u bytes", evt->len);
-		bt_recv_prio(dev, evt);
+
+#if defined(CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE)
+		err = bt_recv_prio(dev, evt);
+#else /* CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE */
+		err = bt_recv(dev, evt);
+#endif /* CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE */
 	}
 
 	return err;
@@ -789,7 +939,12 @@ static int iso_handle(const struct device *dev, struct net_buf *buf)
 	err = hci_iso_handle(buf, &evt);
 	if (evt) {
 		LOG_DBG("Replying with event of %u bytes", evt->len);
-		bt_recv_prio(dev, evt);
+
+#if defined(CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE)
+		err = bt_recv_prio(dev, evt);
+#else /* CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE */
+		err = bt_recv(dev, evt);
+#endif /* CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE */
 	}
 
 	return err;
@@ -845,9 +1000,9 @@ static int hci_driver_open(const struct device *dev, bt_hci_recv_t recv)
 	DEBUG_INIT();
 
 	k_fifo_init(&recv_fifo);
-	k_sem_init(&sem_prio_recv, 0, K_SEM_MAX_LIMIT);
+	k_sem_init(&sem_recv, 0, K_SEM_MAX_LIMIT);
 
-	err = ll_init(&sem_prio_recv);
+	err = ll_init(&sem_recv);
 	if (err) {
 		LOG_ERR("LL initialization failed: %d", err);
 		return err;
@@ -858,15 +1013,17 @@ static int hci_driver_open(const struct device *dev, bt_hci_recv_t recv)
 #if defined(CONFIG_BT_HCI_ACL_FLOW_CONTROL)
 	k_poll_signal_init(&hbuf_signal);
 	hci_init(&hbuf_signal);
-#else
+#else /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */
 	hci_init(NULL);
-#endif
+#endif /* CONFIG_BT_HCI_ACL_FLOW_CONTROL */
 
+#if defined(CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE)
 	k_thread_create(&prio_recv_thread_data, prio_recv_thread_stack,
 			K_KERNEL_STACK_SIZEOF(prio_recv_thread_stack),
 			prio_recv_thread, (void *)dev, NULL, NULL,
 			K_PRIO_COOP(CONFIG_BT_DRIVER_RX_HIGH_PRIO), 0, K_NO_WAIT);
 	k_thread_name_set(&prio_recv_thread_data, "BT RX pri");
+#endif /* CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE */
 
 	k_thread_create(&recv_thread_data, recv_thread_stack,
 			K_KERNEL_STACK_SIZEOF(recv_thread_stack),
@@ -888,8 +1045,10 @@ static int hci_driver_close(const struct device *dev)
 	err = ll_deinit();
 	LL_ASSERT(!err);
 
+#if defined(CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE)
 	/* Abort prio RX thread */
 	k_thread_abort(&prio_recv_thread_data);
+#endif /* CONFIG_BT_CTLR_RX_PRIO_STACK_SIZE */
 
 	/* Abort RX thread */
 	k_thread_abort(&recv_thread_data);
diff --git a/subsys/bluetooth/controller/ll_sw/lll.h b/subsys/bluetooth/controller/ll_sw/lll.h
index 3abddb9e8fa..9b890315cfd 100644
--- a/subsys/bluetooth/controller/ll_sw/lll.h
+++ b/subsys/bluetooth/controller/ll_sw/lll.h
@@ -32,10 +32,6 @@
 /* Intervals after which connection or sync establishment is considered lost */
 #define CONN_ESTAB_COUNTDOWN 6U
 
-#if defined(CONFIG_BT_CTLR_XTAL_ADVANCED)
-#define XON_BITMASK BIT(31) /* XTAL has been retained from previous prepare */
-#endif /* CONFIG_BT_CTLR_XTAL_ADVANCED */
-
 #if defined(CONFIG_BT_BROADCASTER)
 #if defined(CONFIG_BT_CTLR_ADV_SET)
 #define BT_CTLR_ADV_SET CONFIG_BT_CTLR_ADV_SET
@@ -213,19 +209,7 @@ struct ull_hdr {
 				*/
 
 	/* Event parameters */
-	/* TODO: The intention is to use the greater of the
-	 *       ticks_prepare_to_start or ticks_active_to_start as the prepare
-	 *       offset. At the prepare tick generate a software interrupt
-	 *       serviceable by application as the per role configurable advance
-	 *       radio event notification, usable for data acquisitions.
-	 *       ticks_preempt_to_start is the per role dynamic preempt offset,
-	 *       which shall be based on role's preparation CPU usage
-	 *       requirements.
-	 */
 	struct {
-		uint32_t ticks_active_to_start;
-		uint32_t ticks_prepare_to_start;
-		uint32_t ticks_preempt_to_start;
 		uint32_t ticks_slot;
 	};
 
diff --git a/subsys/bluetooth/controller/ll_sw/lll_adv.h b/subsys/bluetooth/controller/ll_sw/lll_adv.h
index 94a3035f42b..5f56f902d19 100644
--- a/subsys/bluetooth/controller/ll_sw/lll_adv.h
+++ b/subsys/bluetooth/controller/ll_sw/lll_adv.h
@@ -18,6 +18,17 @@ struct lll_adv_iso_stream {
 	uint16_t pkt_seq_num;
 };
 
+struct lll_adv_iso_data_chan {
+	uint16_t prn_s;
+	uint16_t remap_idx;
+};
+
+struct lll_adv_iso_data_chan_interleaved {
+	uint16_t prn_s;
+	uint16_t remap_idx;
+	uint16_t id;
+};
+
 struct lll_adv_iso {
 	struct lll_hdr hdr;
 	struct lll_adv *adv;
@@ -26,8 +37,14 @@ struct lll_adv_iso {
 	uint8_t base_crc_init[2];
 	uint16_t latency_prepare;
 	uint16_t latency_event;
-	uint16_t data_chan_prn_s;
-	uint16_t data_chan_remap_idx;
+	union {
+		struct lll_adv_iso_data_chan data_chan;
+
+#if defined(CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED)
+		struct lll_adv_iso_data_chan_interleaved
+			interleaved_data_chan[BT_CTLR_ADV_ISO_STREAM_MAX];
+#endif /* CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED */
+	};
 	uint8_t  next_chan_use;
 
 	uint64_t payload_count:39;
diff --git a/subsys/bluetooth/controller/ll_sw/lll_conn_iso.h b/subsys/bluetooth/controller/ll_sw/lll_conn_iso.h
index 676c574155e..884d1322dbc 100644
--- a/subsys/bluetooth/controller/ll_sw/lll_conn_iso.h
+++ b/subsys/bluetooth/controller/ll_sw/lll_conn_iso.h
@@ -58,6 +58,14 @@ struct lll_conn_iso_stream {
 	uint8_t datapath_ready_rx:1;/* 1 if datapath for RX is ready */
 
 #if !defined(CONFIG_BT_CTLR_JIT_SCHEDULING)
+	/* A CIS LLL is active and prepared in a CIG radio event when ACL instant has passed
+	 * which set the `active` flag and then when CIG event prepare in LLL has picked up the set
+	 * `active` flag.
+	 * FIXME: There is suspected possibility that ACL ULL Prepare that is processing LLCP could
+	 *        execute between CIG ULL Prepare and deferred CIG LLL Prepare say when there is
+	 *        already another state/role that the CIG tries to pre-empt.
+	 */
+	uint8_t prepared:1;
 	/* Lazy at CIS active. Number of previously skipped CIG events that is
 	 * determined when CIS is made active and subtracted from total CIG
 	 * events that where skipped when this CIS gets to use radio for the
diff --git a/subsys/bluetooth/controller/ll_sw/lll_sync_iso.h b/subsys/bluetooth/controller/ll_sw/lll_sync_iso.h
index 6dd6a0907a5..6e295100437 100644
--- a/subsys/bluetooth/controller/ll_sw/lll_sync_iso.h
+++ b/subsys/bluetooth/controller/ll_sw/lll_sync_iso.h
@@ -11,6 +11,17 @@ struct lll_sync_iso_stream {
 	struct ll_iso_datapath *dp;
 };
 
+struct lll_sync_iso_data_chan {
+	uint16_t prn_s;
+	uint16_t remap_idx;
+};
+
+struct lll_sync_iso_data_chan_interleaved {
+	uint16_t prn_s;
+	uint16_t remap_idx;
+	uint16_t id;
+};
+
 struct lll_sync_iso {
 	struct lll_hdr hdr;
 
@@ -21,8 +32,15 @@ struct lll_sync_iso {
 
 	uint16_t latency_prepare;
 	uint16_t latency_event;
-	uint16_t data_chan_prn_s;
-	uint16_t data_chan_remap_idx;
+	union {
+		struct lll_sync_iso_data_chan data_chan;
+
+#if defined(CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED)
+		struct lll_sync_iso_data_chan_interleaved
+			interleaved_data_chan[BT_CTLR_SYNC_ISO_STREAM_MAX];
+#endif /* CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED */
+	};
+	uint8_t  next_chan_use;
 
 	uint64_t payload_count:39;
 	uint64_t framing:1;
@@ -55,11 +73,8 @@ struct lll_sync_iso {
 	uint8_t bis_curr:5;
 
 	uint8_t stream_curr:5;
-
 	uint8_t establish_events:3;
 
-	uint8_t next_chan_use;
-
 	/* Encryption */
 	uint8_t giv[8];
 	struct ccm ccm_rx;
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_df.c b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_df.c
index 500720ba357..1f5c810bc2a 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_df.c
+++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_df.c
@@ -399,7 +399,7 @@ void radio_switch_complete_and_phy_end_b2b_tx(uint8_t phy_curr, uint8_t flags_cu
 					      uint8_t phy_next, uint8_t flags_next)
 {
 #if defined(CONFIG_BT_CTLR_TIFS_HW)
-	NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk | RADIO_SHORTS_END_DISABLE_Msk |
+	NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk |
 			    RADIO_SHORTS_DISABLED_TXEN_Msk;
 #else /* !CONFIG_BT_CTLR_TIFS_HW */
 	NRF_RADIO->SHORTS = RADIO_SHORTS_READY_START_Msk | NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk;
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_dppi.h b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_dppi.h
index 06aea328eaf..4dabe97d910 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_dppi.h
+++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_dppi.h
@@ -89,7 +89,8 @@ static inline void hal_radio_disable_on_hcto_ppi_config(void)
  */
 static inline void hal_radio_end_time_capture_ppi_config(void)
 {
-	nrf_radio_publish_set(NRF_RADIO, HAL_NRF_RADIO_EVENT_END, HAL_RADIO_END_TIME_CAPTURE_PPI);
+	nrf_radio_publish_set(NRF_RADIO, HAL_NRF_RADIO_EVENT_END,
+			      HAL_RADIO_END_TIME_CAPTURE_PPI);
 	nrf_timer_subscribe_set(EVENT_TIMER, HAL_EVENT_TIMER_TRX_END_TASK,
 				HAL_RADIO_END_TIME_CAPTURE_PPI);
 }
@@ -230,15 +231,15 @@ static inline void hal_trigger_crypt_by_bcmatch_ppi_config(void)
 
 /******************************************************************************/
 #if !defined(CONFIG_BT_CTLR_TIFS_HW)
-
 /* DPPI setup used for SW-based auto-switching during TIFS. */
-#if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
-#define HAL_NRF_RADIO_TIFS_DPPI_EVENT_END HAL_NRF_RADIO_EVENT_END
-#define HAL_RADIO_TIFS_DPPI_PUBLISH_END   HAL_RADIO_PUBLISH_END
-#else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
-#define HAL_NRF_RADIO_TIFS_DPPI_EVENT_END HAL_NRF_RADIO_EVENT_PHYEND
-#define HAL_RADIO_TIFS_DPPI_PUBLISH_END   HAL_RADIO_PUBLISH_PHYEND
-#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
+
+#if defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER) && !defined(CONFIG_BT_CTLR_DF)
+#define HAL_NRF_RADIO_TIMER_CLEAR_EVENT_END     HAL_NRF_RADIO_EVENT_END
+#define HAL_RADIO_GROUP_TASK_ENABLE_PUBLISH_END HAL_RADIO_PUBLISH_END
+#else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER || CONFIG_BT_CTLR_DF */
+#define HAL_NRF_RADIO_TIMER_CLEAR_EVENT_END     HAL_NRF_RADIO_EVENT_PHYEND
+#define HAL_RADIO_GROUP_TASK_ENABLE_PUBLISH_END HAL_RADIO_PUBLISH_PHYEND
+#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER || CONFIG_BT_CTLR_DF */
 
 /* Clear SW-switch timer on packet end:
  * wire the RADIO EVENTS_END event to SW_SWITCH_TIMER TASKS_CLEAR task.
@@ -250,7 +251,7 @@ static inline void hal_trigger_crypt_by_bcmatch_ppi_config(void)
  */
 static inline void hal_sw_switch_timer_clear_ppi_config(void)
 {
-	nrf_radio_publish_set(NRF_RADIO, HAL_NRF_RADIO_TIFS_DPPI_EVENT_END,
+	nrf_radio_publish_set(NRF_RADIO, HAL_NRF_RADIO_TIMER_CLEAR_EVENT_END,
 			      HAL_SW_SWITCH_TIMER_CLEAR_PPI);
 	nrf_timer_subscribe_set(SW_SWITCH_TIMER,
 				NRF_TIMER_TASK_CLEAR, HAL_SW_SWITCH_TIMER_CLEAR_PPI);
@@ -321,7 +322,7 @@ static inline void hal_sw_switch_timer_clear_ppi_config(void)
  * a PPI to publish RADIO END event.
  */
 #define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_REGISTER_EVT \
-	(NRF_RADIO->HAL_RADIO_TIFS_DPPI_PUBLISH_END)
+	(NRF_RADIO->HAL_RADIO_GROUP_TASK_ENABLE_PUBLISH_END)
 #define HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI_EVT \
 	(((HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI << \
 		RADIO_PUBLISH_END_CHIDX_Pos) \
@@ -528,8 +529,10 @@ static inline void hal_radio_sw_switch_cleanup(void)
 {
 	hal_radio_sw_switch_disable();
 	nrf_dppi_channels_disable(NRF_DPPIC,
-				  (BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) |
-				   BIT(HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI)));
+#if !defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
+				  BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) |
+#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
+				  BIT(HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI));
 	nrf_dppi_group_disable(NRF_DPPIC, SW_SWITCH_TIMER_TASK_GROUP(0));
 	nrf_dppi_group_disable(NRF_DPPIC, SW_SWITCH_TIMER_TASK_GROUP(1));
 }
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_ppi.h b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_ppi.h
index 05445e1fb48..d9ead6803a9 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_ppi.h
+++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_ppi.h
@@ -170,18 +170,18 @@ static inline void hal_radio_end_time_capture_ppi_config(void)
 	/* No need to configure anything for the pre-programmed channel. */
 }
 
-#else
+#else /* !(EVENT_TIMER_ID == 0) */
 
 static inline void hal_radio_end_time_capture_ppi_config(void)
 {
 	nrf_ppi_channel_endpoint_setup(
 		NRF_PPI,
 		HAL_RADIO_END_TIME_CAPTURE_PPI,
-		(uint32_t)&(NRF_RADIO->HAL_RADIO_TRX_EVENTS_END),
+		(uint32_t)&(NRF_RADIO->HAL_RADIO_EVENTS_END),
 		(uint32_t)&(EVENT_TIMER->TASKS_CAPTURE[HAL_EVENT_TIMER_TRX_END_CC_OFFSET]));
 }
 
-#endif /* (EVENT_TIMER_ID == 0) */
+#endif /* !(EVENT_TIMER_ID == 0) */
 
 /*******************************************************************************
  * Start event timer on RTC tick:
@@ -307,7 +307,7 @@ static inline void hal_sw_switch_timer_clear_ppi_config(void)
 		(uint32_t)&(SW_SWITCH_TIMER->TASKS_CLEAR));
 }
 
-#else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
+#else /* CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
 
 /* Clear event timer (sw-switch timer) on Radio end:
  * wire the RADIO EVENTS_END event to the
@@ -325,7 +325,7 @@ static inline void hal_sw_switch_timer_clear_ppi_config(void)
 		(uint32_t)&(SW_SWITCH_TIMER->TASKS_CLEAR));
 }
 
-#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
+#endif /* CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
 
 /* The 2 adjacent PPI groups used for implementing SW_SWITCH_TIMER-based
  * auto-switch for TIFS. 'index' must be 0 or 1.
@@ -453,11 +453,15 @@ static inline void hal_radio_sw_switch_disable(void)
 {
 	/* Disable the following PPI channels that implement SW Switch:
 	 * - Clearing SW SWITCH TIMER on RADIO END event
+	 *   - Do not clear for single timer use as it uses the same PPI as
+	 *     end time capture
 	 * - Enabling SW SWITCH PPI Group on RADIO END event
 	 */
 	nrf_ppi_channels_disable(
 		NRF_PPI,
+#if !defined(CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER)
 		BIT(HAL_SW_SWITCH_TIMER_CLEAR_PPI) |
+#endif /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
 		BIT(HAL_SW_SWITCH_GROUP_TASK_ENABLE_PPI));
 
 	/* Invalidation of subscription of S2 timer Compare used when
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_resources.h b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_resources.h
index 8bd540bbfa6..a60b27e2482 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_resources.h
+++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_nrf5_resources.h
@@ -18,7 +18,8 @@
  * or reception of a PDU on air. In case of regular PDU it is generated when last bit of CRC is
  * received or transmitted.
  */
-#define HAL_RADIO_TRX_EVENTS_END HAL_RADIO_EVENTS_END
+#define HAL_RADIO_TRX_EVENTS_END    HAL_RADIO_EVENTS_END
+#define HAL_NRF_RADIO_TRX_EVENT_END HAL_NRF_RADIO_EVENT_END
 
 /* Wrapper for RADIO_SHORTS mask connecting EVENTS_END to EVENTS_DISABLE.
  * This is a default shortcut used to automatically disable Radio after end of PDU.
@@ -62,59 +63,62 @@
  */
 #define HAL_RADIO_ISR_LATENCY_MAX_US 80U
 
-#if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
-/* Delay of CCM TASKS_CRYPT start in number of bits for Radio Bit counter */
-#define CCM_TASKS_CRYPT_DELAY_BITS 3
-#endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
+#define SW_SWITCH_TIMER_EVTS_COMP_BASE 4
 
 #if defined(CONFIG_BT_CTLR_PHY_CODED)
-#define SW_SWITCH_TIMER_EVTS_COMP_BASE 4
 #define SW_SWITCH_TIMER_EVTS_COMP_S2_BASE 6
+#endif /* !CONFIG_BT_CTLR_PHY_CODED */
+
+#if defined(CONFIG_BT_CTLR_DF)
+#if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE)
+/* Allocate 2 adjacent channels for PHYEND delay compensation. Use the same channels as for
+ * PHY CODED S2. The CTEINLINE may not be enabled for PHY CODED so PHYEND event is generated
+ * at the same instant as END event. Hence the channels are used interchangeably.
+ * That saves from use of another timer.
+ */
+#define SW_SWITCH_TIMER_EVTS_COMP_PHYEND_DELAY_COMPENSATION_BASE 6
+#endif /* CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE */
 
 /* Wrapper for EVENTS_END event generated by Radio peripheral at the very end of the transmission
  * or reception of a PDU on air. In case of regular PDU it is generated when last bit of CRC is
  * received or transmitted.
+ *
+ * When direction finding is enabled a PDU may include Constant Tone Extension at its end. For PDU
+ * including CTE EVENTS_PHYEND event is generated at very end of a PDU. In case there is no CTE in
+ * a PDU the EVENTS_PHYEND event is generated in the same instant as EVENTS_END event.
  */
-#define HAL_RADIO_TRX_EVENTS_END HAL_RADIO_EVENTS_END
+#define HAL_RADIO_TRX_EVENTS_END    HAL_RADIO_EVENTS_PHYEND
+#define HAL_NRF_RADIO_TRX_EVENT_END HAL_NRF_RADIO_EVENT_PHYEND
 
-/* Wrapper for RADIO_SHORTS mask connecting EVENTS_END to EVENTS_DISABLE.
- * This is a default shortcut used to automatically disable Radio after end of PDU.
+/* Wrapper for RADIO_SHORTS mask connecting EVENTS_PHYEND to EVENTS_DISABLE.
+ * This is a mask for SOC that has Direction Finding Extension in a Radio peripheral.
+ * It enables shortcut for EVENTS_PHYEND event generated at very end to Radio EVENTS_DISABLE event.
+ * In case there is a CTE in a PDU then EVENTS_PHYEND event is generated after the CTE.
+ * If there is no CTE, it is generated in the same instant as EVENTS_END.
  */
-#define NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk HAL_RADIO_SHORTS_TRX_END_DISABLE_Msk
-
-#define HAL_EVENT_TIMER_TRX_CC_OFFSET          0
-#define HAL_EVENT_TIMER_TRX_EVENT              NRF_TIMER_EVENT_COMPARE0
-#define HAL_EVENT_TIMER_READY_TASK             NRF_TIMER_TASK_CAPTURE0
-
-#define HAL_EVENT_TIMER_HCTO_CC_OFFSET         1
-#define HAL_EVENT_TIMER_HCTO_EVENT             NRF_TIMER_EVENT_COMPARE1
-#define HAL_EVENT_TIMER_ADDRESS_TASK           NRF_TIMER_TASK_CAPTURE1
-
-#define HAL_EVENT_TIMER_TRX_END_CC_OFFSET      2
-#define HAL_EVENT_TIMER_TRX_END_TASK           NRF_TIMER_TASK_CAPTURE2
-
-#define HAL_EVENT_TIMER_DEFERRED_TRX_CC_OFFSET 2
-#define HAL_EVENT_TIMER_DEFERRED_TX_EVENT      NRF_TIMER_EVENT_COMPARE2
-
-#define HAL_EVENT_TIMER_SAMPLE_CC_OFFSET       3
-#define HAL_EVENT_TIMER_SAMPLE_TASK            NRF_TIMER_TASK_CAPTURE3
+#define NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk HAL_RADIO_SHORTS_TRX_PHYEND_DISABLE_Msk
 
-#define HAL_EVENT_TIMER_PA_LNA_CC_OFFSET       2
-#define HAL_EVENT_TIMER_PA_LNA_PDN_CC_OFFSET   3
+/* Delay of EVENTS_PHYEND event on receive PDU without CTE included when CTEINLINE is enabled */
+#define RADIO_EVENTS_PHYEND_DELAY_US 16
 
-#else /* !CONFIG_BT_CTLR_PHY_CODED */
-#define SW_SWITCH_TIMER_EVTS_COMP_BASE 4
+#if defined(CONFIG_BT_CTLR_DF_CONN_CTE_RX)
+/* Delay of CCM TASKS_CRYPT start in number of bits for Radio Bit counter */
+#define CCM_TASKS_CRYPT_DELAY_BITS 3
+#endif /* CONFIG_BT_CTLR_DF_CONN_CTE_RX */
 
+#else /* !CONFIG_BT_CTLR_DF */
 /* Wrapper for EVENTS_END event generated by Radio peripheral at the very end of the transmission
  * or reception of a PDU on air. In case of regular PDU it is generated when last bit of CRC is
  * received or transmitted.
  */
-#define HAL_RADIO_TRX_EVENTS_END HAL_RADIO_EVENTS_END
+#define HAL_RADIO_TRX_EVENTS_END    HAL_RADIO_EVENTS_END
+#define HAL_NRF_RADIO_TRX_EVENT_END HAL_NRF_RADIO_EVENT_END
 
 /* Wrapper for RADIO_SHORTS mask connecting EVENTS_END to EVENTS_DISABLE.
  * This is a default shortcut used to automatically disable Radio after end of PDU.
  */
 #define NRF_RADIO_SHORTS_TRX_END_DISABLE_Msk HAL_RADIO_SHORTS_TRX_END_DISABLE_Msk
+#endif /* !CONFIG_BT_CTLR_DF */
 
 #define HAL_EVENT_TIMER_TRX_CC_OFFSET          0
 #define HAL_EVENT_TIMER_TRX_EVENT              NRF_TIMER_EVENT_COMPARE0
@@ -135,7 +139,6 @@
 
 #define HAL_EVENT_TIMER_PA_LNA_CC_OFFSET       2
 #define HAL_EVENT_TIMER_PA_LNA_PDN_CC_OFFSET   3
-#endif /* !CONFIG_BT_CTLR_PHY_CODED */
 
 #else /* !CONFIG_BT_CTLR_SW_SWITCH_SINGLE_TIMER */
 #define EVENT_TIMER_ID 0
@@ -155,7 +158,6 @@
 #endif /* !CONFIG_BT_CTLR_PHY_CODED */
 
 #if defined(CONFIG_BT_CTLR_DF)
-
 #if defined(CONFIG_BT_CTLR_DF_PHYEND_OFFSET_COMPENSATION_ENABLE)
 /* Allocate 2 adjacent channels for PHYEND delay compensation. Use the same channels as for
  * PHY CODED S2. The CTEINLINE may not be enabled for PHY CODED so PHYEND event is generated
@@ -173,7 +175,8 @@
  * including CTE EVENTS_PHYEND event is generated at very end of a PDU. In case there is no CTE in
  * a PDU the EVENTS_PHYEND event is generated in the same instant as EVENTS_END event.
  */
-#define HAL_RADIO_TRX_EVENTS_END HAL_RADIO_EVENTS_PHYEND
+#define HAL_RADIO_TRX_EVENTS_END    HAL_RADIO_EVENTS_PHYEND
+#define HAL_NRF_RADIO_TRX_EVENT_END HAL_NRF_RADIO_EVENT_PHYEND
 
 /* Wrapper for RADIO_SHORTS mask connecting EVENTS_PHYEND to EVENTS_DISABLE.
  * This is a mask for SOC that has Direction Finding Extension in a Radio peripheral.
@@ -196,7 +199,8 @@
  * or reception of a PDU on air. In case of regular PDU it is generated when last bit of CRC is
  * received or transmitted.
  */
-#define HAL_RADIO_TRX_EVENTS_END HAL_RADIO_EVENTS_END
+#define HAL_RADIO_TRX_EVENTS_END    HAL_RADIO_EVENTS_END
+#define HAL_NRF_RADIO_TRX_EVENT_END HAL_NRF_RADIO_EVENT_END
 
 /* Wrapper for RADIO_SHORTS mask connecting EVENTS_END to EVENTS_DISABLE.
  * This is a default shortcut used to automatically disable Radio after end of PDU.
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_sim_nrf54l.h b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_sim_nrf54l.h
index 047e3ea2487..324f2c8edb3 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_sim_nrf54l.h
+++ b/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/radio_sim_nrf54l.h
@@ -30,20 +30,21 @@
 
 /* NRF Radio HW timing constants
  * - provided in US and NS (for higher granularity)
- * - based on empirical measurements and sniffer logs
+ * - based on the timings configured in the HW models, which are based
+ *   on the old 52832 product specification
  */
 
 /* TXEN->TXIDLE + TXIDLE->TX (with fast Radio ramp-up mode)
  * in microseconds for LE 1M PHY.
  */
-#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_1M_FAST_NS 40900 /*40.1 + 0.8*/
+#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_1M_FAST_NS 41000
 #define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_1M_FAST_US \
 	HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_1M_FAST_NS)
 
 /* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode)
  * in microseconds for LE 1M PHY.
  */
-#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_1M_DEFAULT_NS 140900 /*140.1 + 0.8*/
+#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_1M_DEFAULT_NS 141000
 #define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_1M_DEFAULT_US \
 	HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_1M_DEFAULT_NS)
 
@@ -51,7 +52,7 @@
  * and no HW TIFS auto-switch) in microseconds for LE 1M PHY.
  */
  /* 129.5 + 0.8 */
-#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_NS 130300
+#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_NS 130000
 #define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_US \
 	HAL_RADIO_NS2US_ROUND( \
 		HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_1M_DEFAULT_NO_HW_TIFS_NS)
@@ -59,14 +60,14 @@
 /* TXEN->TXIDLE + TXIDLE->TX (with fast Radio ramp-up mode)
  * in microseconds for LE 2M PHY.
  */
-#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_2M_FAST_NS 40000 /* 40.1 - 0.1 */
+#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_2M_FAST_NS 40000
 #define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_2M_FAST_US \
 	HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_2M_FAST_NS)
 
 /* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode)
  * in microseconds for LE 2M PHY.
  */
-#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_2M_DEFAULT_NS 144900 /* 145 - 0.1 */
+#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_2M_DEFAULT_NS 140000
 #define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_2M_DEFAULT_US \
 	HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_2M_DEFAULT_NS)
 
@@ -74,7 +75,7 @@
  * no HW TIFS auto-switch) in microseconds for LE 2M PHY.
  */
 /* 129.5 - 0.1 */
-#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_NS 129400
+#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_NS 129000
 #define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_US \
 	HAL_RADIO_NS2US_ROUND( \
 		HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_2M_DEFAULT_NO_HW_TIFS_NS)
@@ -82,14 +83,14 @@
 /* TXEN->TXIDLE + TXIDLE->TX (with fast Radio ramp-up mode)
  * in microseconds for LE CODED PHY [S2].
  */
-#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S2_FAST_NS 42300 /* 40.1 + 2.2 */
+#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S2_FAST_NS 42000
 #define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S2_FAST_US \
 	HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S2_FAST_NS)
 
 /* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode)
  * in microseconds for LE 2M PHY [S2].
  */
-#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S2_DEFAULT_NS 132200 /* 130 + 2.2 */
+#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S2_DEFAULT_NS 132000
 #define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S2_DEFAULT_US \
 	HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S2_DEFAULT_NS)
 
@@ -97,7 +98,7 @@
  * no HW TIFS auto-switch) in microseconds for LE 2M PHY [S2].
  */
 /* 129.5 + 2.2 */
-#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_NS 131700
+#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_NS 132000
 #define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_US \
 	HAL_RADIO_NS2US_ROUND( \
 		HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S2_DEFAULT_NO_HW_TIFS_NS)
@@ -105,13 +106,13 @@
 /* TXEN->TXIDLE + TXIDLE->TX (with fast Radio ramp-up mode)
  * in microseconds for LE CODED PHY [S8].
  */
-#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S8_FAST_NS 42300 /* 40.1 + 2.2 */
+#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S8_FAST_NS 42000
 #define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S8_FAST_US \
 	HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S8_FAST_NS)
 /* TXEN->TXIDLE + TXIDLE->TX (with default Radio ramp-up mode)
  * in microseconds for LE 2M PHY [S8].
  */
-#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S8_DEFAULT_NS 121800 /*119.6 + 2.2*/
+#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S8_DEFAULT_NS 122000
 #define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S8_DEFAULT_US \
 	HAL_RADIO_NS2US_ROUND(HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S8_DEFAULT_NS)
 
@@ -119,7 +120,7 @@
  * no HW TIFS auto-switch) in microseconds for LE 2M PHY [S8].
  */
  /* 129.5 + 2.2 */
-#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_NS 131700
+#define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_NS 132000
 #define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_US \
 	HAL_RADIO_NS2US_ROUND( \
 		HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_S8_DEFAULT_NO_HW_TIFS_NS)
@@ -127,14 +128,14 @@
 /* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode)
  * in microseconds for LE 1M PHY.
  */
-#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_1M_FAST_NS 40300 /* 40.1 + 0.2 */
+#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_1M_FAST_NS 40000
 #define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_1M_FAST_US \
 	HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_1M_FAST_NS)
 
 /* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode)
  * in microseconds for LE 1M PHY.
  */
-#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_1M_DEFAULT_NS 140300 /*140.1 + 0.2*/
+#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_1M_DEFAULT_NS 140000
 #define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_1M_DEFAULT_US \
 	HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_1M_DEFAULT_NS)
 
@@ -142,7 +143,7 @@
  * no HW TIFS auto-switch) in microseconds for LE 1M PHY.
  */
 /* 129.5 + 0.2 */
-#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_NS 129700
+#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_NS 129000
 #define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_US \
 	HAL_RADIO_NS2US_CEIL( \
 		HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_1M_DEFAULT_NO_HW_TIFS_NS)
@@ -150,22 +151,21 @@
 /* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode)
  * in microseconds for LE 2M PHY.
  */
-#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_2M_FAST_NS 40300 /* 40.1 + 0.2 */
+#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_2M_FAST_NS 40000
 #define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_2M_FAST_US \
 	HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_2M_FAST_NS)
 
 /* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode)
  * in microseconds for LE 2M PHY.
  */
-#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_2M_DEFAULT_NS 144800 /*144.6 + 0.2*/
+#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_2M_DEFAULT_NS 140000
 #define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_2M_DEFAULT_US \
 	HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_2M_DEFAULT_NS)
 
 /* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode and
  * no HW TIFS auto-switch) in microseconds for LE 2M PHY.
  */
-/* 129.5 + 0.2 */
-#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_NS 129700
+#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_NS 129000
 #define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_US \
 	HAL_RADIO_NS2US_CEIL( \
 		HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_2M_DEFAULT_NO_HW_TIFS_NS)
@@ -173,14 +173,14 @@
 /* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode)
  * in microseconds for LE Coded PHY [S2].
  */
-#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S2_FAST_NS 40300 /* 40.1 + 0.2 */
+#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S2_FAST_NS 40000
 #define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S2_FAST_US \
 	HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S2_FAST_NS)
 
 /* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode)
  * in microseconds for LE Coded PHY [S2].
  */
-#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S2_DEFAULT_NS 130200 /* 130 + 0.2 */
+#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S2_DEFAULT_NS 120000
 #define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S2_DEFAULT_US \
 	HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S2_DEFAULT_NS)
 
@@ -188,7 +188,7 @@
  * and no HW TIFS auto-switch) in microseconds for LE Coded PHY [S2].
  */
 /* 129.5 + 0.2 */
-#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_NS 129700
+#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_NS 130000
 #define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_US \
 	HAL_RADIO_NS2US_CEIL( \
 		HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S2_DEFAULT_NO_HW_TIFS_NS)
@@ -196,14 +196,14 @@
 /* RXEN->RXIDLE + RXIDLE->RX (with fast Radio ramp-up mode)
  * in microseconds for LE Coded PHY [S8].
  */
-#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S8_FAST_NS 40300 /* 40.1 + 0.2 */
+#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S8_FAST_NS 40000
 #define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S8_FAST_US \
 	HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S8_FAST_NS)
 
 /* RXEN->RXIDLE + RXIDLE->RX (with default Radio ramp-up mode)
  * in microseconds for LE Coded PHY [S8].
  */
-#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S8_DEFAULT_NS 120200 /* 120.0 + 0.2 */
+#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S8_DEFAULT_NS 120000
 #define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S8_DEFAULT_US \
 	HAL_RADIO_NS2US_CEIL(HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S8_DEFAULT_NS)
 
@@ -211,28 +211,22 @@
  * no HW TIFS auto-switch) in microseconds for LE Coded PHY [S8].
  */
 /* 129.5 + 0.2 */
-#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_NS 129700
+#define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_NS 130000
 #define HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_US \
 	HAL_RADIO_NS2US_CEIL( \
 		HAL_RADIO_NRF54LX_RXEN_RXIDLE_RX_S8_DEFAULT_NO_HW_TIFS_NS)
 
-#define HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_1M_US  1 /* ceil(0.6) */
-#define HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_1M_NS  600 /* 0.6 */
-#define HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_2M_US  1 /* ceil(0.6) */
-#define HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_2M_NS  600 /* 0.6 */
-#define HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_S2_US  1 /* ceil(0.6) */
-#define HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_S2_NS  600 /* 0.6 */
-#define HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_S8_US  1 /* ceil(0.6) */
-#define HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_S8_NS  600 /* 0.6 */
-
-#define HAL_RADIO_NRF54LX_RX_CHAIN_DELAY_1M_US  10 /* ceil(9.4) */
-#define HAL_RADIO_NRF54LX_RX_CHAIN_DELAY_1M_NS  9400 /* 9.4 */
-#define HAL_RADIO_NRF54LX_RX_CHAIN_DELAY_2M_US  5 /* ceil(5.0) */
-#define HAL_RADIO_NRF54LX_RX_CHAIN_DELAY_2M_NS  5000 /* 5.0 */
-#define HAL_RADIO_NRF54LX_RX_CHAIN_DELAY_S2_US  25 /* ceil(19.6) */
-#define HAL_RADIO_NRF54LX_RX_CHAIN_DELAY_S2_NS  24600 /* 19.6 */
-#define HAL_RADIO_NRF54LX_RX_CHAIN_DELAY_S8_US  30 /* ceil(29.6) */
-#define HAL_RADIO_NRF54LX_RX_CHAIN_DELAY_S8_NS  29600 /* 29.6 */
+#define HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_US  1
+#define HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_NS  1000
+
+#define HAL_RADIO_NRF54LX_RX_CHAIN_DELAY_1M_US  9
+#define HAL_RADIO_NRF54LX_RX_CHAIN_DELAY_1M_NS  9000
+#define HAL_RADIO_NRF54LX_RX_CHAIN_DELAY_2M_US  5
+#define HAL_RADIO_NRF54LX_RX_CHAIN_DELAY_2M_NS  5000
+#define HAL_RADIO_NRF54LX_RX_CHAIN_DELAY_S2_US  30
+#define HAL_RADIO_NRF54LX_RX_CHAIN_DELAY_S2_NS  30000
+#define HAL_RADIO_NRF54LX_RX_CHAIN_DELAY_S8_US  30
+#define HAL_RADIO_NRF54LX_RX_CHAIN_DELAY_S8_NS  30000
 
 #if defined(CONFIG_BT_CTLR_RADIO_ENABLE_FAST)
 #define HAL_RADIO_NRF54LX_TXEN_TXIDLE_TX_1M_US \
@@ -713,22 +707,9 @@ static inline uint32_t hal_radio_rx_ready_delay_us_get(uint8_t phy, uint8_t flag
 
 static inline uint32_t hal_radio_tx_chain_delay_us_get(uint8_t phy, uint8_t flags)
 {
-	switch (phy) {
-	default:
-	case BIT(0):
-		return HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_1M_US;
-	case BIT(1):
-		return HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_2M_US;
-
-#if defined(CONFIG_BT_CTLR_PHY_CODED)
-	case BIT(2):
-		if (flags & 0x01) {
-			return HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_S8_US;
-		} else {
-			return HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_S2_US;
-		}
-#endif /* CONFIG_BT_CTLR_PHY_CODED */
-	}
+	ARG_UNUSED(phy);
+	ARG_UNUSED(flags);
+	return HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_US;
 }
 
 static inline uint32_t hal_radio_rx_chain_delay_us_get(uint8_t phy, uint8_t flags)
@@ -793,22 +774,9 @@ static inline uint32_t hal_radio_rx_ready_delay_ns_get(uint8_t phy, uint8_t flag
 
 static inline uint32_t hal_radio_tx_chain_delay_ns_get(uint8_t phy, uint8_t flags)
 {
-	switch (phy) {
-	default:
-	case BIT(0):
-		return HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_1M_NS;
-	case BIT(1):
-		return HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_2M_NS;
-
-#if defined(CONFIG_BT_CTLR_PHY_CODED)
-	case BIT(2):
-		if (flags & 0x01) {
-			return HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_S8_NS;
-		} else {
-			return HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_S2_NS;
-		}
-#endif /* CONFIG_BT_CTLR_PHY_CODED */
-	}
+	ARG_UNUSED(phy);
+	ARG_UNUSED(flags);
+	return HAL_RADIO_NRF54LX_TX_CHAIN_DELAY_NS;
 }
 
 static inline uint32_t hal_radio_rx_chain_delay_ns_get(uint8_t phy, uint8_t flags)
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll.c
index d449c9736b1..f93ea59f38e 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll.c
+++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll.c
@@ -612,16 +612,7 @@ void lll_abort_cb(struct lll_prepare_param *prepare_param, void *param)
 
 uint32_t lll_event_offset_get(struct ull_hdr *ull)
 {
-	if (0) {
-#if defined(CONFIG_BT_CTLR_XTAL_ADVANCED)
-	} else if (ull->ticks_prepare_to_start & XON_BITMASK) {
-		return MAX(ull->ticks_active_to_start,
-			   ull->ticks_preempt_to_start);
-#endif /* CONFIG_BT_CTLR_XTAL_ADVANCED */
-	} else {
-		return MAX(ull->ticks_active_to_start,
-			   ull->ticks_prepare_to_start);
-	}
+	return HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 }
 
 uint32_t lll_preempt_calc(struct ull_hdr *ull, uint8_t ticker_id,
@@ -1108,9 +1099,8 @@ static uint32_t preempt_ticker_start(struct lll_event *first,
 		p = &next->prepare_param;
 		ull = HDR_LLL2ULL(p->param);
 		preempt_anchor = p->ticks_at_expire;
-		preempt_to = MAX(ull->ticks_active_to_start,
-				 ull->ticks_prepare_to_start) -
-			     ull->ticks_preempt_to_start;
+		preempt_to = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US) -
+			     HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
 
 		ticks_at_preempt_new = preempt_anchor + preempt_to;
 		ticks_at_preempt_new &= HAL_TICKER_CNTR_MASK;
@@ -1134,9 +1124,8 @@ static uint32_t preempt_ticker_start(struct lll_event *first,
 		p = &first->prepare_param;
 		ull = HDR_LLL2ULL(p->param);
 		preempt_anchor = p->ticks_at_expire;
-		preempt_to = MAX(ull->ticks_active_to_start,
-				 ull->ticks_prepare_to_start) -
-			     ull->ticks_preempt_to_start;
+		preempt_to = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US) -
+			     HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
 
 		ticks_at_preempt_new = preempt_anchor + preempt_to;
 		ticks_at_preempt_new &= HAL_TICKER_CNTR_MASK;
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_iso.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_iso.c
index 91ca0b1d0c6..0b9ff8d938c 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_iso.c
+++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_adv_iso.c
@@ -56,8 +56,13 @@ static void isr_tx_normal(void *param);
 static void isr_tx_common(void *param,
 			  radio_isr_cb_t isr_tx,
 			  radio_isr_cb_t isr_done);
-static void next_chan_calc(struct lll_adv_iso *lll, uint16_t event_counter,
-			   uint16_t data_chan_id);
+#if defined(CONFIG_BT_CTLR_ADV_ISO_SEQUENTIAL)
+static void next_chan_calc_seq(struct lll_adv_iso *lll, uint16_t event_counter,
+			       uint16_t data_chan_id);
+#endif /* CONFIG_BT_CTLR_ADV_ISO_SEQUENTIAL */
+#if defined(CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED)
+static void next_chan_calc_int(struct lll_adv_iso *lll, uint16_t event_counter);
+#endif /* CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED */
 static void isr_done_create(void *param);
 static void isr_done_term(void *param);
 
@@ -232,8 +237,8 @@ static int prepare_cb_common(struct lll_prepare_param *p)
 	data_chan_use = lll_chan_iso_event(event_counter, data_chan_id,
 					   lll->data_chan_map,
 					   lll->data_chan_count,
-					   &lll->data_chan_prn_s,
-					   &lll->data_chan_remap_idx);
+					   &lll->data_chan.prn_s,
+					   &lll->data_chan.remap_idx);
 
 	/* Start setting up of Radio h/w */
 	radio_reset();
@@ -378,6 +383,8 @@ static int prepare_cb_common(struct lll_prepare_param *p)
 		radio_pkt_tx_set(pdu);
 	}
 
+	const bool is_sequential_packing = (lll->bis_spacing >= (lll->sub_interval * lll->nse));
+
 	/* Setup radio IFS switching */
 	if ((lll->bn_curr == lll->bn) &&
 	    (lll->irc_curr == lll->irc) &&
@@ -389,9 +396,9 @@ static int prepare_cb_common(struct lll_prepare_param *p)
 		uint16_t iss_us;
 
 		/* Calculate next subevent start based on previous PDU length */
-		iss_us = lll->sub_interval -
-			 PDU_BIS_US(pdu->len, ((pdu->len) ? lll->enc : 0U),
-				    lll->phy, lll->phy_flags);
+		iss_us = is_sequential_packing ? lll->sub_interval : lll->bis_spacing;
+		iss_us -= PDU_BIS_US(pdu->len, ((pdu->len) ? lll->enc : 0U),
+				     lll->phy, lll->phy_flags);
 
 		radio_tmr_tifs_set(iss_us);
 		radio_switch_complete_and_b2b_tx(lll->phy, lll->phy_flags,
@@ -444,7 +451,27 @@ static int prepare_cb_common(struct lll_prepare_param *p)
 	LL_ASSERT(!ret);
 
 	/* Calculate ahead the next subevent channel index */
-	next_chan_calc(lll, event_counter, data_chan_id);
+	if (false) {
+
+#if defined(CONFIG_BT_CTLR_ADV_ISO_SEQUENTIAL)
+	} else if (is_sequential_packing) {
+		next_chan_calc_seq(lll, event_counter, data_chan_id);
+#endif /* CONFIG_BT_CTLR_ADV_ISO_SEQUENTIAL */
+
+#if defined(CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED)
+	} else if (!is_sequential_packing) {
+		struct lll_adv_iso_data_chan_interleaved *interleaved_data_chan;
+
+		interleaved_data_chan =
+			&lll->interleaved_data_chan[lll->bis_curr - 1U];
+		interleaved_data_chan->id = data_chan_id;
+
+		next_chan_calc_int(lll, event_counter);
+#endif /* CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED */
+
+	} else {
+		LL_ASSERT(false);
+	}
 
 	return 0;
 }
@@ -470,6 +497,7 @@ static void isr_tx_common(void *param,
 	uint64_t payload_count;
 	uint16_t data_chan_id;
 	uint8_t crc_init[3];
+	uint8_t is_ctrl;
 	uint8_t bis;
 
 #if defined(HAL_RADIO_GPIO_HAVE_PA_PIN)
@@ -481,35 +509,84 @@ static void isr_tx_common(void *param,
 	}
 
 	lll = param;
-	/* FIXME: Sequential or Interleaved BIS subevents decision */
-	/* Sequential Tx complete flow pseudo code */
-	if (lll->bn_curr < lll->bn) {
-		/* transmit the (bn_curr)th Tx PDU of bis_curr */
-		lll->bn_curr++; /* post increment */
 
-		bis = lll->bis_curr;
+	/* Sequential or Interleaved BIS subevents decision */
+	const bool is_sequential_packing = (lll->bis_spacing >= (lll->sub_interval * lll->nse));
 
-	} else if (lll->irc_curr < lll->irc) {
-		/* transmit the (bn_curr)th Tx PDU of bis_curr */
-		lll->bn_curr = 1U;
-		lll->irc_curr++; /* post increment */
+	is_ctrl = 0U;
+	if (false) {
 
-		bis = lll->bis_curr;
+#if defined(CONFIG_BT_CTLR_ADV_ISO_SEQUENTIAL)
+	} else if (is_sequential_packing) {
+		/* Sequential Tx complete flow */
+		if (lll->bn_curr < lll->bn) {
+			/* transmit the (bn_curr)th Tx PDU of bis_curr */
+			lll->bn_curr++; /* post increment */
 
-	} else if (lll->ptc_curr < lll->ptc) {
-		lll->ptc_curr++; /* pre increment */
-		/* transmit the (ptc_curr * bn)th Tx PDU */
+			bis = lll->bis_curr;
 
-		bis = lll->bis_curr;
+		} else if (lll->irc_curr < lll->irc) {
+			/* transmit the (bn_curr)th Tx PDU of bis_curr */
+			lll->bn_curr = 1U;
+			lll->irc_curr++; /* post increment */
 
-	} else if (lll->bis_curr < lll->num_bis) {
-		lll->bis_curr++;
-		lll->ptc_curr = 0U;
-		lll->irc_curr = 1U;
-		/* transmit the (bn_curr)th PDU of bis_curr */
-		lll->bn_curr = 1U;
+			bis = lll->bis_curr;
+
+		} else if (lll->ptc_curr < lll->ptc) {
+			lll->ptc_curr++; /* pre increment */
+			/* transmit the (ptc_curr * bn)th Tx PDU */
+
+			bis = lll->bis_curr;
 
-		bis = lll->bis_curr;
+		} else if (lll->bis_curr < lll->num_bis) {
+			lll->bis_curr++;
+			lll->ptc_curr = 0U;
+			lll->irc_curr = 1U;
+			/* transmit the (bn_curr)th PDU of bis_curr */
+			lll->bn_curr = 1U;
+
+			bis = lll->bis_curr;
+		} else {
+			is_ctrl = 1U;
+		}
+#endif /* CONFIG_BT_CTLR_ADV_ISO_SEQUENTIAL */
+
+#if defined(CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED)
+	} else if (!is_sequential_packing) {
+		/* Interleaved Tx complete flow */
+		if (lll->bis_curr < lll->num_bis) {
+			lll->bis_curr++;
+
+			bis = lll->bis_curr;
+		} else if (lll->bn_curr < lll->bn) {
+			lll->bn_curr++;
+			lll->bis_curr = 1U;
+
+			bis = lll->bis_curr;
+		} else if (lll->irc_curr < lll->irc) {
+			lll->irc_curr++;
+			lll->bn_curr = 1U;
+			lll->bis_curr = 1U;
+
+			bis = lll->bis_curr;
+		} else if (lll->ptc_curr < lll->ptc) {
+			lll->ptc_curr++;
+			lll->bis_curr = 1U;
+
+			bis = lll->bis_curr;
+		} else {
+			is_ctrl = 1U;
+		}
+#endif /* CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED */
+
+	} else {
+		bis = 0U;
+
+		LL_ASSERT(false);
+	}
+
+	if (!is_ctrl) {
+		/* ISO data subevent, nothing to do here */
 
 	} else if (lll->term_ack) {
 		/* Transmit the control PDU and close the BIG event
@@ -558,6 +635,7 @@ static void isr_tx_common(void *param,
 		payload_count = lll->payload_count - lll->bn;
 
 	} else {
+		/* All subevents in the ISO interval is done. */
 		struct lll_adv_iso_stream *stream;
 		uint16_t stream_handle;
 		memq_link_t *link;
@@ -727,8 +805,8 @@ static void isr_tx_common(void *param,
 		data_chan_use = lll_chan_iso_event(event_counter, data_chan_id,
 						   lll->data_chan_map,
 						   lll->data_chan_count,
-						   &lll->data_chan_prn_s,
-						   &lll->data_chan_remap_idx);
+						   &lll->data_chan.prn_s,
+						   &lll->data_chan.remap_idx);
 	}
 
 	lll_chan_set(data_chan_use);
@@ -772,9 +850,9 @@ static void isr_tx_common(void *param,
 		uint16_t iss_us;
 
 		/* Calculate next subevent start based on previous PDU length */
-		iss_us = lll->sub_interval -
-			 PDU_BIS_US(pdu->len, ((pdu->len) ? lll->enc : 0U),
-				    lll->phy, lll->phy_flags);
+		iss_us = is_sequential_packing ? lll->sub_interval : lll->bis_spacing;
+		iss_us -= PDU_BIS_US(pdu->len, ((pdu->len) ? lll->enc : 0U),
+				     lll->phy, lll->phy_flags);
 
 		radio_tmr_tifs_set(iss_us);
 		radio_switch_complete_and_b2b_tx(lll->phy, lll->phy_flags,
@@ -826,26 +904,42 @@ static void isr_tx_common(void *param,
 	/* Calculate ahead the next subevent channel index */
 	const uint16_t event_counter = (lll->payload_count / lll->bn) - 1U;
 
-	next_chan_calc(lll, event_counter, data_chan_id);
+	if (false) {
+
+#if defined(CONFIG_BT_CTLR_ADV_ISO_SEQUENTIAL)
+	} else if (is_sequential_packing) {
+		next_chan_calc_seq(lll, event_counter, data_chan_id);
+#endif /* CONFIG_BT_CTLR_ADV_ISO_SEQUENTIAL */
+
+#if defined(CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED)
+	} else if (!is_sequential_packing) {
+		next_chan_calc_int(lll, event_counter);
+#endif /* CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED */
+
+	} else {
+		LL_ASSERT(false);
+	}
 
 	if (IS_ENABLED(CONFIG_BT_CTLR_PROFILE_ISR)) {
 		lll_prof_send();
 	}
 }
 
-static void next_chan_calc(struct lll_adv_iso *lll, uint16_t event_counter,
-			   uint16_t data_chan_id)
+#if defined(CONFIG_BT_CTLR_ADV_ISO_SEQUENTIAL)
+static void next_chan_calc_seq(struct lll_adv_iso *lll, uint16_t event_counter,
+			       uint16_t data_chan_id)
 {
 	/* Calculate ahead the next subevent channel index */
 	if ((lll->bn_curr < lll->bn) ||
 	    (lll->irc_curr < lll->irc) ||
 	    (lll->ptc_curr < lll->ptc)) {
 		/* Calculate the radio channel to use for next subevent */
-		lll->next_chan_use = lll_chan_iso_subevent(data_chan_id,
-						lll->data_chan_map,
-						lll->data_chan_count,
-						&lll->data_chan_prn_s,
-						&lll->data_chan_remap_idx);
+		lll->next_chan_use =
+			lll_chan_iso_subevent(data_chan_id,
+					      lll->data_chan_map,
+					      lll->data_chan_count,
+					      &lll->data_chan.prn_s,
+					      &lll->data_chan.remap_idx);
 	} else if (lll->bis_curr < lll->num_bis) {
 		uint8_t access_addr[4];
 
@@ -855,14 +949,72 @@ static void next_chan_calc(struct lll_adv_iso *lll, uint16_t event_counter,
 		data_chan_id = lll_chan_id(access_addr);
 
 		/* Calculate the radio channel to use for next BIS */
-		lll->next_chan_use = lll_chan_iso_event(event_counter,
-						data_chan_id,
-						lll->data_chan_map,
-						lll->data_chan_count,
-						&lll->data_chan_prn_s,
-						&lll->data_chan_remap_idx);
+		lll->next_chan_use =
+			lll_chan_iso_event(event_counter,
+					   data_chan_id,
+					   lll->data_chan_map,
+					   lll->data_chan_count,
+					   &lll->data_chan.prn_s,
+					   &lll->data_chan.remap_idx);
+	}
+}
+#endif /* CONFIG_BT_CTLR_ADV_ISO_SEQUENTIAL */
+
+#if defined(CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED)
+static void next_chan_calc_int(struct lll_adv_iso *lll, uint16_t event_counter)
+{
+	struct lll_adv_iso_data_chan_interleaved *interleaved_data_chan;
+
+	if ((lll->bis_curr >= lll->num_bis) &&
+	    (lll->bn_curr >= lll->bn) &&
+	    (lll->irc_curr >= lll->irc) &&
+	    (lll->ptc_curr >= lll->ptc)) {
+		return;
+	}
+
+	if ((lll->bis_curr < lll->num_bis) &&
+	    (lll->bn_curr == 1U) &&
+	    (lll->irc_curr == 1U) &&
+	    (lll->ptc_curr == 0U)) {
+		uint8_t access_addr[4];
+
+		/* Calculate the Access Address for the next BIS subevent */
+		util_bis_aa_le32((lll->bis_curr + 1U), lll->seed_access_addr,
+				 access_addr);
+
+		interleaved_data_chan =
+			&lll->interleaved_data_chan[lll->bis_curr];
+		interleaved_data_chan->id = lll_chan_id(access_addr);
+
+		/* Calculate the radio channel to use for next BIS */
+		lll->next_chan_use =
+			lll_chan_iso_event(event_counter,
+					   interleaved_data_chan->id,
+					   lll->data_chan_map,
+					   lll->data_chan_count,
+					   &interleaved_data_chan->prn_s,
+					   &interleaved_data_chan->remap_idx);
+	} else {
+		uint8_t bis_idx;
+
+		if (lll->bis_curr >= lll->num_bis) {
+			bis_idx = 0U;
+		} else {
+			bis_idx = lll->bis_curr;
+		}
+
+		interleaved_data_chan = &lll->interleaved_data_chan[bis_idx];
+
+		/* Calculate the radio channel to use for next subevent */
+		lll->next_chan_use =
+			lll_chan_iso_subevent(interleaved_data_chan->id,
+					      lll->data_chan_map,
+					      lll->data_chan_count,
+					      &interleaved_data_chan->prn_s,
+					      &interleaved_data_chan->remap_idx);
 	}
 }
+#endif  /* CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED */
 
 static void isr_done_create(void *param)
 {
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_central_iso.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_central_iso.c
index 526403e92d9..889ae0541cf 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_central_iso.c
+++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_central_iso.c
@@ -144,6 +144,12 @@ static int prepare_cb(struct lll_prepare_param *p)
 
 	LL_ASSERT(cis_lll);
 
+	/* Unconditionally set the prepared flag.
+	 * This flag ensures current CIG event does not pick up a new CIS becoming active when the
+	 * ACL overlaps at the instant with this already started CIG events.
+	 */
+	cis_lll->prepared = 1U;
+
 	/* Save first active CIS offset */
 	cis_offset_first = cis_lll->offset;
 
@@ -360,6 +366,13 @@ static int prepare_cb(struct lll_prepare_param *p)
 	do {
 		cis_lll = ull_conn_iso_lll_stream_get_by_group(cig_lll, &cis_handle);
 		if (cis_lll && cis_lll->active) {
+			/* Unconditionally set the prepared flag.
+			 * This flag ensures current CIG event does not pick up a new CIS becoming
+			 * active when the ACL overlaps at the instant with this already started
+			 * CIG events.
+			 */
+			cis_lll->prepared = 1U;
+
 			/* Pick the event_count calculated in the ULL prepare */
 			cis_lll->event_count = cis_lll->event_count_prepare;
 
@@ -404,7 +417,7 @@ static void abort_cb(struct lll_prepare_param *prepare_param, void *param)
 		do {
 			next_cis_lll = ull_conn_iso_lll_stream_get_by_group(cig_lll,
 									    &cis_handle_curr);
-			if (next_cis_lll && next_cis_lll->active) {
+			if (next_cis_lll && next_cis_lll->prepared) {
 				payload_count_flush_or_inc_on_close(next_cis_lll);
 			}
 		} while (next_cis_lll);
@@ -586,7 +599,7 @@ static void isr_tx(void *param)
 		cis_handle = cis_handle_curr;
 		do {
 			next_cis_lll = ull_conn_iso_lll_stream_get_by_group(cig_lll, &cis_handle);
-		} while (next_cis_lll && !next_cis_lll->active);
+		} while (next_cis_lll && !next_cis_lll->prepared);
 
 		if (!next_cis_lll) {
 			return;
@@ -830,7 +843,7 @@ static void isr_rx(void *param)
 		do {
 			next_cis_lll = ull_conn_iso_lll_stream_get_by_group(cig_lll,
 									    &cis_handle_curr);
-		} while (next_cis_lll && !next_cis_lll->active);
+		} while (next_cis_lll && !next_cis_lll->prepared);
 
 		if (!next_cis_lll) {
 			goto isr_rx_done;
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_peripheral_iso.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_peripheral_iso.c
index 00e641fd151..0a451053578 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_peripheral_iso.c
+++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_peripheral_iso.c
@@ -158,6 +158,12 @@ static int prepare_cb(struct lll_prepare_param *p)
 
 	LL_ASSERT(cis_lll);
 
+	/* Unconditionally set the prepared flag.
+	 * This flag ensures current CIG event does not pick up a new CIS becoming active when the
+	 * ACL overlaps at the instant with this already started CIG events.
+	 */
+	cis_lll->prepared = 1U;
+
 	/* Save first active CIS offset */
 	cis_offset_first = cis_lll->offset;
 
@@ -377,6 +383,12 @@ static int prepare_cb(struct lll_prepare_param *p)
 			break;
 		}
 
+		/* Unconditionally set the prepared flag.
+		 * This flag ensures current CIG event does not pick up a new CIS becoming active
+		 * when the ACL overlaps at the instant with this already started CIG events.
+		 */
+		cis_lll->prepared = 1U;
+
 		/* Pick the event_count calculated in the ULL prepare */
 		cis_lll->event_count = cis_lll->event_count_prepare;
 
@@ -421,7 +433,7 @@ static void abort_cb(struct lll_prepare_param *prepare_param, void *param)
 			next_cis_lll =
 				ull_conn_iso_lll_stream_sorted_get_by_group(cig_lll,
 									    &cis_handle_curr);
-			if (next_cis_lll && next_cis_lll->active) {
+			if (next_cis_lll && next_cis_lll->prepared) {
 				payload_count_rx_flush_or_txrx_inc(next_cis_lll);
 			}
 		} while (next_cis_lll);
@@ -782,7 +794,7 @@ static void isr_rx(void *param)
 		do {
 			next_cis_lll =
 				ull_conn_iso_lll_stream_sorted_get_by_group(cig_lll, &cis_handle);
-		} while (next_cis_lll && !next_cis_lll->active);
+		} while (next_cis_lll && !next_cis_lll->prepared);
 
 		if (!next_cis_lll) {
 			/* ISO Event Done */
@@ -994,7 +1006,7 @@ static void next_cis_prepare(void *param)
 	cis_handle = cis_handle_curr;
 	do {
 		next_cis_lll = ull_conn_iso_lll_stream_sorted_get_by_group(cig_lll, &cis_handle);
-	} while (next_cis_lll && !next_cis_lll->active);
+	} while (next_cis_lll && !next_cis_lll->prepared);
 
 	if (!next_cis_lll) {
 		/* ISO Event Done */
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan.c
index 5f51c55f425..8aedcd44a4f 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan.c
+++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_scan.c
@@ -1381,9 +1381,10 @@ static inline int isr_rx_pdu(struct lll_scan *lll, struct pdu_adv *pdu_adv_rx,
 					rl_idx, &dir_report))) ||
 #if defined(CONFIG_BT_CTLR_ADV_EXT)
 		  ((pdu_adv_rx->type == PDU_ADV_TYPE_EXT_IND) &&
-		   lll->phy && lll_scan_ext_tgta_check(lll, true, false,
-						       pdu_adv_rx, rl_idx,
-						       &dir_report)) ||
+		   lll->phy &&
+		   !lll->state &&
+		   lll_scan_ext_tgta_check(lll, true, false, pdu_adv_rx, rl_idx,
+					   &dir_report)) ||
 #endif /* CONFIG_BT_CTLR_ADV_EXT */
 		  ((pdu_adv_rx->type == PDU_ADV_TYPE_SCAN_RSP) &&
 		   (pdu_adv_rx->len >= offsetof(struct pdu_adv_scan_rsp, data)) &&
diff --git a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c
index 0257bc0eafa..dbfec680c8d 100644
--- a/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c
+++ b/subsys/bluetooth/controller/ll_sw/nordic/lll/lll_sync_iso.c
@@ -53,8 +53,14 @@ static void isr_rx(void *param);
 static void isr_rx_done(void *param);
 static void isr_done(void *param);
 static uint16_t payload_index_get(const struct lll_sync_iso *lll);
-static void next_chan_calc(struct lll_sync_iso *lll, uint16_t event_counter,
-			   uint16_t data_chan_id);
+#if defined(CONFIG_BT_CTLR_SYNC_ISO_SEQUENTIAL)
+static void next_chan_calc_seq(struct lll_sync_iso *lll, uint16_t event_counter,
+			       uint16_t data_chan_id);
+#endif /* CONFIG_BT_CTLR_SYNC_ISO_SEQUENTIAL */
+#if defined(CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED)
+static void next_chan_calc_int(struct lll_sync_iso *lll,
+			       uint16_t event_counter);
+#endif /* CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED */
 static void isr_rx_iso_data_valid(const struct lll_sync_iso *const lll,
 				  uint16_t handle, struct node_rx_pdu *node_rx);
 static void isr_rx_iso_data_invalid(const struct lll_sync_iso *const lll,
@@ -263,12 +269,14 @@ static int prepare_cb_common(struct lll_prepare_param *p)
 	data_chan_use = lll_chan_iso_event(event_counter, data_chan_id,
 					   lll->data_chan_map,
 					   lll->data_chan_count,
-					   &lll->data_chan_prn_s,
-					   &lll->data_chan_remap_idx);
+					   &lll->data_chan.prn_s,
+					   &lll->data_chan.remap_idx);
 
 	/* Initialize stream current */
 	lll->stream_curr = 0U;
 
+	const bool is_sequential_packing = (lll->bis_spacing >= (lll->sub_interval * lll->nse));
+
 	/* Skip subevents until first selected BIS */
 	stream_handle = lll->stream_handle[lll->stream_curr];
 	stream = ull_sync_iso_lll_stream_get(stream_handle);
@@ -283,12 +291,36 @@ static int prepare_cb_common(struct lll_prepare_param *p)
 		data_chan_id = lll_chan_id(access_addr);
 
 		/* Calculate the channel id for the next BIS subevent */
-		data_chan_use = lll_chan_iso_event(event_counter,
-					data_chan_id,
-					lll->data_chan_map,
-					lll->data_chan_count,
-					&lll->data_chan_prn_s,
-					&lll->data_chan_remap_idx);
+		if (false) {
+
+#if defined(CONFIG_BT_CTLR_SYNC_ISO_SEQUENTIAL)
+		} else if (is_sequential_packing) {
+			data_chan_use = lll_chan_iso_event(event_counter,
+							   data_chan_id,
+							   lll->data_chan_map,
+							   lll->data_chan_count,
+							   &lll->data_chan.prn_s,
+							   &lll->data_chan.remap_idx);
+#endif /* CONFIG_BT_CTLR_SYNC_ISO_SEQUENTIAL */
+
+#if defined(CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED)
+		} else if (!is_sequential_packing) {
+			struct lll_sync_iso_data_chan_interleaved *interleaved_data_chan;
+
+			interleaved_data_chan =
+				&lll->interleaved_data_chan[lll->bis_curr - 1U];
+
+			data_chan_use = lll_chan_iso_event(event_counter,
+							   data_chan_id,
+							   lll->data_chan_map,
+							   lll->data_chan_count,
+							   &interleaved_data_chan->prn_s,
+							   &interleaved_data_chan->remap_idx);
+#endif /* CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED */
+
+		} else {
+			LL_ASSERT(false);
+		}
 	}
 
 	/* Calculate the CRC init value for the BIS event,
@@ -402,7 +434,27 @@ static int prepare_cb_common(struct lll_prepare_param *p)
 	LL_ASSERT(!ret);
 
 	/* Calculate ahead the next subevent channel index */
-	next_chan_calc(lll, event_counter, data_chan_id);
+	if (false) {
+
+#if defined(CONFIG_BT_CTLR_SYNC_ISO_SEQUENTIAL)
+	} else if (is_sequential_packing) {
+		next_chan_calc_seq(lll, event_counter, data_chan_id);
+#endif /* CONFIG_BT_CTLR_SYNC_ISO_SEQUENTIAL */
+
+#if defined(CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED)
+	} else if (!is_sequential_packing) {
+		struct lll_sync_iso_data_chan_interleaved *interleaved_data_chan;
+
+		interleaved_data_chan =
+			&lll->interleaved_data_chan[lll->bis_curr - 1U];
+		interleaved_data_chan->id = data_chan_id;
+
+		next_chan_calc_int(lll, event_counter);
+#endif /* CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED */
+
+	} else {
+		LL_ASSERT(false);
+	}
 
 	return 0;
 }
@@ -560,15 +612,17 @@ static void isr_rx(void *param)
 		lll_prof_latency_capture();
 	}
 
+	/* initialize LLL context reference */
+	lll = param;
+
+	const bool is_sequential_packing = (lll->bis_spacing >= (lll->sub_interval * lll->nse));
+
 	/* Read radio status and events */
 	trx_done = radio_is_done();
 	if (!trx_done) {
 		/* Clear radio rx status and events */
 		lll_isr_rx_status_reset();
 
-		/* initialize LLL context reference */
-		lll = param;
-
 		/* BIS index */
 		bis_idx = lll->bis_curr - 1U;
 
@@ -582,23 +636,39 @@ static void isr_rx(void *param)
 	rssi_ready = radio_rssi_is_ready();
 	trx_cnt++;
 
-	/* initialize LLL context reference */
-	lll = param;
-
 	/* Save the AA captured for the first anchor point sync */
 	if (!radio_tmr_aa_restore()) {
 		const struct lll_sync_iso_stream *sync_stream;
 		uint32_t se_offset_us;
-		uint8_t se;
 
 		crc_ok_anchor = crc_ok;
 
 		sync_stream = ull_sync_iso_lll_stream_get(lll->stream_handle[0]);
-		se = ((lll->bis_curr - sync_stream->bis_index) *
-		      ((lll->bn * lll->irc) + lll->ptc)) +
-		     ((lll->irc_curr - 1U) * lll->bn) + (lll->bn_curr - 1U) +
-		     lll->ptc_curr + lll->ctrl;
-		se_offset_us = lll->sub_interval * se;
+
+		if (IS_ENABLED(CONFIG_BT_CTLR_SYNC_ISO_SEQUENTIAL) &&
+		    is_sequential_packing) {
+			uint8_t se;
+
+			se = ((lll->bis_curr - sync_stream->bis_index) *
+			      ((lll->bn * lll->irc) + lll->ptc)) +
+			     ((lll->irc_curr - 1U) * lll->bn) +
+			     (lll->bn_curr - 1U) + lll->ptc_curr + lll->ctrl;
+			se_offset_us = lll->sub_interval * se;
+		} else if (IS_ENABLED(CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED) &&
+			   !is_sequential_packing) {
+			uint8_t se;
+
+			se = (lll->bis_curr - sync_stream->bis_index) +
+			     ((((lll->irc_curr - 1U) * lll->bn) +
+			       (lll->bn_curr - 1U) + lll->ptc_curr) *
+			      lll->num_bis) + lll->ctrl;
+			se_offset_us = lll->bis_spacing * se;
+		} else {
+			se_offset_us = 0U;
+
+			LL_ASSERT(false);
+		}
+
 		radio_tmr_aa_save(radio_tmr_aa_get() - se_offset_us);
 		radio_tmr_ready_save(radio_tmr_ready_get() - se_offset_us);
 	}
@@ -718,7 +788,14 @@ static void isr_rx(void *param)
 	skipped = 0U;
 
 isr_rx_find_subevent:
-	/* FIXME: Sequential or Interleaved BIS subevents decision */
+	/* Sequential or Interleaved BIS subevents decision */
+#if defined(CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED)
+	if (!is_sequential_packing) {
+		goto isr_rx_interleaved;
+	}
+#endif /* CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED */
+
+#if defined(CONFIG_BT_CTLR_SYNC_ISO_SEQUENTIAL)
 	/* NOTE: below code is for Sequential Rx only */
 
 	/* Find the next (bn_curr)th subevent to receive PDU */
@@ -840,11 +917,11 @@ static void isr_rx(void *param)
 
 	/* Next BIS */
 	if (lll->bis_curr < lll->num_bis) {
-		struct lll_sync_iso_stream *sync_stream;
-		uint16_t stream_handle;
-
 		/* Next selected stream */
 		if ((lll->stream_curr + 1U) < lll->stream_count) {
+			struct lll_sync_iso_stream *sync_stream;
+			uint16_t stream_handle;
+
 			stream_curr = ++lll->stream_curr;
 			stream_handle = lll->stream_handle[stream_curr];
 			sync_stream = ull_sync_iso_lll_stream_get(stream_handle);
@@ -854,9 +931,9 @@ static void isr_rx(void *param)
 				uint8_t bis_idx_new;
 
 				lll->bis_curr = sync_stream->bis_index;
-				lll->ptc_curr = 0U;
-				lll->irc_curr = 1U;
 				lll->bn_curr = 1U;
+				lll->irc_curr = 1U;
+				lll->ptc_curr = 0U;
 
 				/* new BIS index */
 				bis_idx_new = lll->bis_curr - 1U;
@@ -917,7 +994,159 @@ static void isr_rx(void *param)
 			lll->bis_curr = lll->num_bis;
 		}
 	}
+#endif /* CONFIG_BT_CTLR_SYNC_ISO_SEQUENTIAL */
+
+	goto isr_rx_ctrl;
+
+#if defined(CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED)
+isr_rx_interleaved:
+	/* Next BIS */
+	if (lll->bis_curr < lll->num_bis) {
+		/* Next selected stream */
+		if ((lll->stream_curr + 1U) < lll->stream_count) {
+			struct lll_sync_iso_stream *sync_stream;
+			uint16_t stream_handle;
+
+			stream_curr = ++lll->stream_curr;
+			stream_handle = lll->stream_handle[stream_curr];
+			sync_stream = ull_sync_iso_lll_stream_get(stream_handle);
+			if (sync_stream->bis_index <= lll->num_bis) {
+				uint8_t payload_offset;
+				uint8_t payload_index;
+
+				lll->bis_curr = sync_stream->bis_index;
+
+				/* Check payload buffer overflow */
+				payload_offset = (lll->bn_curr - 1U) +
+						 (lll->ptc_curr * lll->pto);
+				if (payload_offset > lll->payload_count_max) {
+					const uint16_t event_counter =
+						(lll->payload_count / lll->bn) - 1U;
+
+					next_chan_calc_int(lll, event_counter);
+
+					goto isr_rx_interleaved;
+				}
+
+				/* Find the index of the (bn_curr)th Rx PDU buffer */
+				payload_index = lll->payload_tail + payload_offset;
+				if (payload_index >= lll->payload_count_max) {
+					payload_index -= lll->payload_count_max;
+				}
+
+				/* Check if (bn_curr)th Rx PDU has been received */
+				if (lll->payload[stream_curr][payload_index]) {
+					const uint16_t event_counter =
+						(lll->payload_count / lll->bn) - 1U;
+
+					next_chan_calc_int(lll, event_counter);
+
+					goto isr_rx_interleaved;
+				}
+
+				bis = lll->bis_curr;
+
+				goto isr_rx_next_subevent;
+			} else {
+				lll->bis_curr = lll->num_bis;
+			}
+		} else {
+			lll->bis_curr = lll->num_bis;
+		}
+	}
+
+	if (lll->bis_curr >= lll->num_bis) {
+		struct lll_sync_iso_stream *sync_stream;
+		uint16_t stream_handle;
+
+		lll->stream_curr = 0U;
+		stream_curr = 0U;
+		stream_handle = lll->stream_handle[stream_curr];
+		sync_stream = ull_sync_iso_lll_stream_get(stream_handle);
+		if (sync_stream->bis_index <= lll->num_bis) {
+			lll->bis_curr = sync_stream->bis_index;
+			bis_idx = lll->bis_curr - 1U;
+		} else {
+			LL_ASSERT(false);
+		}
+	}
+
+	if (lll->bn_curr < lll->bn) {
+		uint8_t payload_offset;
+		uint8_t payload_index;
 
+		lll->bn_curr++;
+
+		/* Check payload buffer overflow */
+		payload_offset = (lll->bn_curr - 1U);
+		if (payload_offset > lll->payload_count_max) {
+			const uint16_t event_counter =
+				(lll->payload_count / lll->bn) - 1U;
+
+			next_chan_calc_int(lll, event_counter);
+
+			goto isr_rx_interleaved;
+		}
+
+		/* Find the index of the (bn_curr)th Rx PDU buffer */
+		payload_index = lll->payload_tail + payload_offset;
+		if (payload_index >= lll->payload_count_max) {
+			payload_index -= lll->payload_count_max;
+		}
+
+		/* Check if (bn_curr)th Rx PDU has been received */
+		if (lll->payload[stream_curr][payload_index]) {
+			const uint16_t event_counter =
+				(lll->payload_count / lll->bn) - 1U;
+
+			next_chan_calc_int(lll, event_counter);
+
+			goto isr_rx_interleaved;
+		}
+
+		bis = lll->bis_curr;
+
+		goto isr_rx_next_subevent;
+	}
+
+	if (lll->irc_curr < lll->irc) {
+		uint8_t payload_index;
+
+		lll->irc_curr++;
+		lll->bn_curr = 1U;
+
+		/* Find the index of the (irc_curr)th bn = 1 Rx PDU
+		 * buffer.
+		 */
+		payload_index = lll->payload_tail;
+
+		/* Check if (irc_curr)th bn = 1 Rx PDU has been
+		 * received.
+		 */
+		if (lll->payload[stream_curr][payload_index]) {
+			const uint16_t event_counter =
+				(lll->payload_count / lll->bn) - 1U;
+
+			next_chan_calc_int(lll, event_counter);
+
+			goto isr_rx_interleaved;
+		}
+
+		bis = lll->bis_curr;
+
+		goto isr_rx_next_subevent;
+	}
+
+	if (lll->ptc_curr < lll->ptc) {
+		lll->ptc_curr++;
+
+		bis = lll->bis_curr;
+
+		goto isr_rx_next_subevent;
+	}
+#endif /* CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED */
+
+isr_rx_ctrl:
 	/* Control subevent */
 	if (!lll->ctrl && (lll->cssn_next != lll->cssn_curr)) {
 		uint8_t pkt_flags;
@@ -983,8 +1212,8 @@ static void isr_rx(void *param)
 		data_chan_use = lll_chan_iso_event(event_counter, data_chan_id,
 						   lll->data_chan_map,
 						   lll->data_chan_count,
-						   &lll->data_chan_prn_s,
-						   &lll->data_chan_remap_idx);
+						   &lll->data_chan.prn_s,
+						   &lll->data_chan.remap_idx);
 	} else if (!skipped) {
 		data_chan_use = lll->next_chan_use;
 	} else {
@@ -1002,8 +1231,8 @@ static void isr_rx(void *param)
 						data_chan_id,
 						lll->data_chan_map,
 						lll->data_chan_count,
-						&lll->data_chan_prn_s,
-						&lll->data_chan_remap_idx);
+						&lll->data_chan.prn_s,
+						&lll->data_chan.remap_idx);
 
 			skipped -= (bis_idx_new - bis_idx_old) *
 				   ((lll->bn * lll->irc) + lll->ptc);
@@ -1014,8 +1243,8 @@ static void isr_rx(void *param)
 			data_chan_use = lll_chan_iso_subevent(data_chan_id,
 						lll->data_chan_map,
 						lll->data_chan_count,
-						&lll->data_chan_prn_s,
-						&lll->data_chan_remap_idx);
+						&lll->data_chan.prn_s,
+						&lll->data_chan.remap_idx);
 		}
 	}
 
@@ -1082,11 +1311,26 @@ static void isr_rx(void *param)
 	 * subevent.
 	 */
 	stream = ull_sync_iso_lll_stream_get(lll->stream_handle[0]);
-	nse = ((lll->bis_curr - stream->bis_index) *
-	       ((lll->bn * lll->irc) + lll->ptc)) +
-	      ((lll->irc_curr - 1U) * lll->bn) + (lll->bn_curr - 1U) +
-	      lll->ptc_curr + lll->ctrl;
-	hcto = lll->sub_interval * nse;
+	if (IS_ENABLED(CONFIG_BT_CTLR_SYNC_ISO_SEQUENTIAL) &&
+	    is_sequential_packing) {
+		nse = ((lll->bis_curr - stream->bis_index) *
+		       ((lll->bn * lll->irc) + lll->ptc)) +
+		      ((lll->irc_curr - 1U) * lll->bn) + (lll->bn_curr - 1U) +
+		      lll->ptc_curr + lll->ctrl;
+		hcto = lll->sub_interval * nse;
+	} else if (IS_ENABLED(CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED) &&
+		   !is_sequential_packing) {
+		nse = (lll->bis_curr - stream->bis_index) +
+		       ((((lll->irc_curr - 1U) * lll->bn) +
+			 (lll->bn_curr - 1U) + lll->ptc_curr) *
+			lll->num_bis) + lll->ctrl;
+		hcto = lll->bis_spacing * nse;
+	} else {
+		nse = 0U;
+		hcto = 0U;
+
+		LL_ASSERT(false);
+	}
 
 	if (trx_cnt) {
 		/* Setup radio packet timer header complete timeout for
@@ -1173,7 +1417,21 @@ static void isr_rx(void *param)
 	/* Calculate ahead the next subevent channel index */
 	const uint16_t event_counter = (lll->payload_count / lll->bn) - 1U;
 
-	next_chan_calc(lll, event_counter, data_chan_id);
+	if (false) {
+
+#if defined(CONFIG_BT_CTLR_SYNC_ISO_SEQUENTIAL)
+	} else if (is_sequential_packing) {
+		next_chan_calc_seq(lll, event_counter, data_chan_id);
+#endif /* CONFIG_BT_CTLR_SYNC_ISO_SEQUENTIAL */
+
+#if defined(CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED)
+	} else if (!is_sequential_packing) {
+		next_chan_calc_int(lll, event_counter);
+#endif /* CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED */
+
+	} else {
+		LL_ASSERT(false);
+	}
 
 	if (IS_ENABLED(CONFIG_BT_CTLR_PROFILE_ISR)) {
 		lll_prof_send();
@@ -1377,19 +1635,21 @@ static uint16_t payload_index_get(const struct lll_sync_iso *lll)
 	return payload_index;
 }
 
-static void next_chan_calc(struct lll_sync_iso *lll, uint16_t event_counter,
-			   uint16_t data_chan_id)
+#if defined(CONFIG_BT_CTLR_SYNC_ISO_SEQUENTIAL)
+static void next_chan_calc_seq(struct lll_sync_iso *lll, uint16_t event_counter,
+			       uint16_t data_chan_id)
 {
 	/* Calculate ahead the next subevent channel index */
 	if ((lll->bn_curr < lll->bn) ||
 	    (lll->irc_curr < lll->irc) ||
 	    (lll->ptc_curr < lll->ptc)) {
 		/* Calculate the radio channel to use for next subevent */
-		lll->next_chan_use = lll_chan_iso_subevent(data_chan_id,
-						lll->data_chan_map,
-						lll->data_chan_count,
-						&lll->data_chan_prn_s,
-						&lll->data_chan_remap_idx);
+		lll->next_chan_use =
+			lll_chan_iso_subevent(data_chan_id,
+					      lll->data_chan_map,
+					      lll->data_chan_count,
+					      &lll->data_chan.prn_s,
+					      &lll->data_chan.remap_idx);
 	} else if (lll->bis_curr < lll->num_bis) {
 		uint8_t access_addr[4];
 
@@ -1399,14 +1659,95 @@ static void next_chan_calc(struct lll_sync_iso *lll, uint16_t event_counter,
 		data_chan_id = lll_chan_id(access_addr);
 
 		/* Calculate the radio channel to use for next BIS */
-		lll->next_chan_use = lll_chan_iso_event(event_counter,
-						data_chan_id,
-						lll->data_chan_map,
-						lll->data_chan_count,
-						&lll->data_chan_prn_s,
-						&lll->data_chan_remap_idx);
+		lll->next_chan_use =
+			lll_chan_iso_event(event_counter,
+					   data_chan_id,
+					   lll->data_chan_map,
+					   lll->data_chan_count,
+					   &lll->data_chan.prn_s,
+					   &lll->data_chan.remap_idx);
 	}
 }
+#endif /* CONFIG_BT_CTLR_SYNC_ISO_SEQUENTIAL */
+
+#if defined(CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED)
+static void next_chan_calc_int(struct lll_sync_iso *lll, uint16_t event_counter)
+{
+	struct lll_sync_iso_data_chan_interleaved *interleaved_data_chan;
+	uint8_t stream_curr;
+	uint8_t bis_prev;
+
+	if ((lll->bis_curr >= lll->num_bis) &&
+	    (lll->bn_curr >= lll->bn) &&
+	    (lll->irc_curr >= lll->irc) &&
+	    (lll->ptc_curr >= lll->ptc)) {
+		return;
+	}
+
+	/* Next selected stream */
+	stream_curr = lll->stream_curr + 1U;
+	if ((stream_curr < BT_CTLR_SYNC_ISO_STREAM_MAX) &&
+	    (stream_curr < lll->stream_count)) {
+		struct lll_sync_iso_stream *sync_stream;
+		uint16_t stream_handle;
+
+		stream_handle = lll->stream_handle[stream_curr];
+		sync_stream = ull_sync_iso_lll_stream_get(stream_handle);
+		if (sync_stream->bis_index <= lll->num_bis) {
+			bis_prev = sync_stream->bis_index - 1U;
+		} else {
+			bis_prev = lll->num_bis;
+		}
+	} else {
+		bis_prev = lll->num_bis;
+	}
+
+	if ((bis_prev < lll->num_bis) &&
+	    (lll->bn_curr == 1U) &&
+	    (lll->irc_curr == 1U) &&
+	    (lll->ptc_curr == 0U)) {
+		uint8_t access_addr[4];
+
+		/* Calculate the Access Address for the next BIS subevent */
+		util_bis_aa_le32((bis_prev + 1U), lll->seed_access_addr,
+				 access_addr);
+
+		interleaved_data_chan =
+			&lll->interleaved_data_chan[bis_prev];
+		interleaved_data_chan->id = lll_chan_id(access_addr);
+
+		/* Calculate the radio channel to use for next BIS */
+		lll->next_chan_use =
+			lll_chan_iso_event(event_counter,
+					   interleaved_data_chan->id,
+					   lll->data_chan_map,
+					   lll->data_chan_count,
+					   &interleaved_data_chan->prn_s,
+					   &interleaved_data_chan->remap_idx);
+	} else {
+		uint8_t bis_idx;
+
+		if (bis_prev >= lll->num_bis) {
+			struct lll_sync_iso_stream *sync_stream;
+
+			sync_stream = ull_sync_iso_lll_stream_get(lll->stream_handle[0]);
+			bis_idx = sync_stream->bis_index - 1U;
+		} else {
+			bis_idx = bis_prev;
+		}
+
+		interleaved_data_chan = &lll->interleaved_data_chan[bis_idx];
+
+		/* Calculate the radio channel to use for next subevent */
+		lll->next_chan_use =
+			lll_chan_iso_subevent(interleaved_data_chan->id,
+					      lll->data_chan_map,
+					      lll->data_chan_count,
+					      &interleaved_data_chan->prn_s,
+					      &interleaved_data_chan->remap_idx);
+	}
+}
+#endif /* CONFIG_BT_CTLR_SYNC_ISO_INTERLEAVED */
 
 static void isr_rx_iso_data_valid(const struct lll_sync_iso *const lll,
 				  uint16_t handle, struct node_rx_pdu *node_rx)
@@ -1428,12 +1769,21 @@ static void isr_rx_iso_data_valid(const struct lll_sync_iso *const lll,
 			      (DIV_ROUND_UP(lll->ptc_curr, lll->bn) *
 			       lll->pto * lll->iso_interval *
 			       PERIODIC_INT_UNIT_US) -
-			      addr_us_get(lll->phy) -
-			      ((stream->bis_index - 1U) *
-			       lll->sub_interval * ((lll->irc * lll->bn) +
-						    lll->ptc));
+			      addr_us_get(lll->phy);
+
+	const bool is_sequential_packing = (lll->bis_spacing >= (lll->sub_interval * lll->nse));
+
+	if (is_sequential_packing) {
+		iso_meta->timestamp -= (stream->bis_index - 1U) *
+				       lll->sub_interval * lll->nse;
+	} else {
+		iso_meta->timestamp -= (stream->bis_index - 1U) *
+				       lll->bis_spacing;
+	}
+
 	iso_meta->timestamp %=
 		HAL_TICKER_TICKS_TO_US_64BIT(BIT64(HAL_TICKER_CNTR_MSBIT + 1U));
+
 	iso_meta->status = 0U;
 }
 
@@ -1455,14 +1805,24 @@ static void isr_rx_iso_data_invalid(const struct lll_sync_iso *const lll,
 
 	stream = ull_sync_iso_lll_stream_get(lll->stream_handle[0]);
 	iso_meta->timestamp = HAL_TICKER_TICKS_TO_US(radio_tmr_start_get()) +
-			      radio_tmr_aa_restore() - addr_us_get(lll->phy) -
-			      ((stream->bis_index - 1U) *
-			       lll->sub_interval * ((lll->irc * lll->bn) +
-						    lll->ptc));
-	iso_meta->timestamp -= (latency * lll->iso_interval *
-				PERIODIC_INT_UNIT_US);
+			      radio_tmr_aa_restore() - addr_us_get(lll->phy);
+
+	const bool is_sequential_packing = (lll->bis_spacing >= (lll->sub_interval * lll->nse));
+
+	if (is_sequential_packing) {
+		iso_meta->timestamp -= (stream->bis_index - 1U) *
+				       lll->sub_interval * lll->nse;
+	} else {
+		iso_meta->timestamp -= (stream->bis_index - 1U) *
+				       lll->bis_spacing;
+	}
+
+	iso_meta->timestamp -= latency * lll->iso_interval *
+			       PERIODIC_INT_UNIT_US;
+
 	iso_meta->timestamp %=
 		HAL_TICKER_TICKS_TO_US_64BIT(BIT64(HAL_TICKER_CNTR_MSBIT + 1U));
+
 	iso_meta->status = 1U;
 }
 
diff --git a/subsys/bluetooth/controller/ll_sw/openisa/lll/lll.c b/subsys/bluetooth/controller/ll_sw/openisa/lll/lll.c
index c77e39e00f9..e4a83b0bb85 100644
--- a/subsys/bluetooth/controller/ll_sw/openisa/lll/lll.c
+++ b/subsys/bluetooth/controller/ll_sw/openisa/lll/lll.c
@@ -385,16 +385,7 @@ int lll_clk_off(void)
 
 uint32_t lll_event_offset_get(struct ull_hdr *ull)
 {
-	if (0) {
-#if defined(CONFIG_BT_CTLR_XTAL_ADVANCED)
-	} else if (ull->ticks_prepare_to_start & XON_BITMASK) {
-		return MAX(ull->ticks_active_to_start,
-			   ull->ticks_preempt_to_start);
-#endif /* CONFIG_BT_CTLR_XTAL_ADVANCED */
-	} else {
-		return MAX(ull->ticks_active_to_start,
-			   ull->ticks_prepare_to_start);
-	}
+	return HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 }
 
 uint32_t lll_preempt_calc(struct ull_hdr *ull, uint8_t ticker_id,
@@ -674,9 +665,8 @@ static uint32_t preempt_ticker_start(struct lll_event *evt,
 	p = &evt->prepare_param;
 	ull = HDR_LLL2ULL(p->param);
 	preempt_anchor = p->ticks_at_expire;
-	preempt_to = MAX(ull->ticks_active_to_start,
-			 ull->ticks_prepare_to_start) -
-		     ull->ticks_preempt_to_start;
+	preempt_to = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US) -
+		     HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
 
 	/* Setup pre empt timeout */
 	ret = ticker_start(TICKER_INSTANCE_ID_CTLR,
diff --git a/subsys/bluetooth/controller/ll_sw/ull.c b/subsys/bluetooth/controller/ll_sw/ull.c
index 52ab480b663..41df97a29cb 100644
--- a/subsys/bluetooth/controller/ll_sw/ull.c
+++ b/subsys/bluetooth/controller/ll_sw/ull.c
@@ -544,7 +544,7 @@ static void *mark_update;
 #endif /* CONFIG_BT_CONN */
 
 static MFIFO_DEFINE(tx_ack, sizeof(struct lll_tx),
-		    BT_CTLR_TX_BUFFERS + BT_CTLR_ISO_TX_BUFFERS);
+		    BT_CTLR_TX_BUFFERS + BT_CTLR_ISO_TX_PDU_BUFFERS);
 #endif /* CONFIG_BT_CONN || CONFIG_BT_CTLR_ADV_ISO */
 
 static void *mark_disable;
diff --git a/subsys/bluetooth/controller/ll_sw/ull_adv.c b/subsys/bluetooth/controller/ll_sw/ull_adv.c
index 19712c8b8a0..911a433f81d 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_adv.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_adv.c
@@ -1275,16 +1275,9 @@ uint8_t ll_adv_enable(uint8_t enable)
 	/* Initialize ULL context before radio event scheduling is started. */
 	ull_hdr_init(&adv->ull);
 
-	/* TODO: active_to_start feature port */
-	adv->ull.ticks_active_to_start = 0;
-	adv->ull.ticks_prepare_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
-	adv->ull.ticks_preempt_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
 	adv->ull.ticks_slot = HAL_TICKER_US_TO_TICKS_CEIL(time_us);
 
-	ticks_slot_offset = MAX(adv->ull.ticks_active_to_start,
-				adv->ull.ticks_prepare_to_start);
+	ticks_slot_offset = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 
 	if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
 		ticks_slot_overhead = ticks_slot_offset;
@@ -2381,14 +2374,16 @@ static void ticker_cb(uint32_t ticks_at_expire, uint32_t ticks_drift,
 	defined(CONFIG_BT_TICKER_EXT_EXPIRE_INFO)
 		if (adv->lll.aux) {
 			uint32_t ticks_to_expire;
-			uint32_t other_remainder;
+			uint32_t other_remainder = 0U;
 
 			LL_ASSERT(context->other_expire_info);
 
 			/* Adjust ticks to expire based on remainder value */
 			ticks_to_expire = context->other_expire_info->ticks_to_expire;
+#if defined(CONFIG_BT_TICKER_REMAINDER_SUPPORT)
 			other_remainder = context->other_expire_info->remainder;
 			hal_ticker_remove_jitter(&ticks_to_expire, &other_remainder);
+#endif /* CONFIG_BT_TICKER_REMAINDER_SUPPORT */
 
 			/* Store the ticks and remainder offset for aux ptr population in LLL */
 			adv->lll.aux->ticks_pri_pdu_offset = ticks_to_expire;
diff --git a/subsys/bluetooth/controller/ll_sw/ull_adv_aux.c b/subsys/bluetooth/controller/ll_sw/ull_adv_aux.c
index 41ee575f447..f6617f8fbd1 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_adv_aux.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_adv_aux.c
@@ -2521,17 +2521,10 @@ uint32_t ull_adv_aux_evt_init(struct ll_adv_aux_set *aux,
 
 	time_us = aux_time_min_get(aux);
 
-	/* TODO: active_to_start feature port */
-	aux->ull.ticks_active_to_start = 0;
-	aux->ull.ticks_prepare_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
-	aux->ull.ticks_preempt_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
 	aux->ull.ticks_slot = HAL_TICKER_US_TO_TICKS_CEIL(time_us);
 
 	if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
-		ticks_slot_overhead = MAX(aux->ull.ticks_active_to_start,
-					  aux->ull.ticks_prepare_to_start);
+		ticks_slot_overhead = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 	} else {
 		ticks_slot_overhead = 0;
 	}
@@ -3197,7 +3190,7 @@ static void mfy_aux_offset_get(void *param)
 	uint16_t chan_counter;
 	struct pdu_adv *pdu;
 	uint32_t ticks_now;
-	uint32_t remainder;
+	uint32_t remainder = 0U;
 	uint32_t offset_us;
 	uint8_t ticker_id;
 	uint16_t pdu_us;
@@ -3222,12 +3215,20 @@ static void mfy_aux_offset_get(void *param)
 		ticks_previous = ticks_current;
 
 		ret_cb = TICKER_STATUS_BUSY;
+#if defined(CONFIG_BT_TICKER_REMAINDER_SUPPORT)
 		ret = ticker_next_slot_get_ext(TICKER_INSTANCE_ID_CTLR,
 					       TICKER_USER_ID_ULL_LOW,
 					       &id, &ticks_current,
 					       &ticks_to_expire, &remainder,
 					       NULL, NULL, NULL,
 					       ticker_op_cb, (void *)&ret_cb);
+#else /* CONFIG_BT_TICKER_REMAINDER_SUPPORT */
+		ret = ticker_next_slot_get(TICKER_INSTANCE_ID_CTLR,
+					   TICKER_USER_ID_ULL_LOW,
+					   &id, &ticks_current,
+					   &ticks_to_expire,
+					   ticker_op_cb, (void *)&ret_cb);
+#endif /* !CONFIG_BT_TICKER_REMAINDER_SUPPORT */
 		if (ret == TICKER_STATUS_BUSY) {
 			while (ret_cb == TICKER_STATUS_BUSY) {
 				ticker_job_sched(TICKER_INSTANCE_ID_CTLR,
@@ -3320,9 +3321,8 @@ static void mfy_aux_offset_get(void *param)
 	/* Assertion check for delayed aux_offset calculations */
 	ticks_now = ticker_ticks_now_get();
 	ticks_elapsed = ticker_ticks_diff_get(ticks_now, ticks_current);
-	ticks_to_start = MAX(adv->ull.ticks_active_to_start,
-			     adv->ull.ticks_prepare_to_start) -
-			 adv->ull.ticks_preempt_to_start;
+	ticks_to_start = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US) -
+			 HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
 	LL_ASSERT(ticks_elapsed < ticks_to_start);
 }
 
@@ -3369,7 +3369,7 @@ static void ticker_cb(uint32_t ticks_at_expire, uint32_t ticks_drift,
 		sync = HDR_LLL2ULL(adv->lll.sync);
 		if (sync->is_started) {
 			uint32_t ticks_to_expire;
-			uint32_t sync_remainder_us;
+			uint32_t sync_remainder_us = 0U;
 
 			LL_ASSERT(context->other_expire_info);
 
@@ -3377,6 +3377,7 @@ static void ticker_cb(uint32_t ticks_at_expire, uint32_t ticks_drift,
 			 * value.
 			 */
 			ticks_to_expire = context->other_expire_info->ticks_to_expire;
+#if defined(CONFIG_BT_TICKER_REMAINDER_SUPPORT)
 			sync_remainder_us = context->other_expire_info->remainder;
 			hal_ticker_remove_jitter(&ticks_to_expire, &sync_remainder_us);
 
@@ -3384,6 +3385,7 @@ static void ticker_cb(uint32_t ticks_at_expire, uint32_t ticks_drift,
 			 * value.
 			 */
 			hal_ticker_add_jitter(&ticks_to_expire, &remainder);
+#endif /* CONFIG_BT_TICKER_REMAINDER_SUPPORT */
 
 			/* Store the offset in us */
 			lll_sync->us_adv_sync_pdu_offset = HAL_TICKER_TICKS_TO_US(ticks_to_expire) +
diff --git a/subsys/bluetooth/controller/ll_sw/ull_adv_iso.c b/subsys/bluetooth/controller/ll_sw/ull_adv_iso.c
index d041f1e2a30..f8f7cb35d64 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_adv_iso.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_adv_iso.c
@@ -260,9 +260,7 @@ static uint8_t big_create(uint8_t big_handle, uint8_t adv_handle, uint8_t num_bi
 	if (aux && aux->is_started) {
 		ticks_slot_aux = aux->ull.ticks_slot;
 		if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
-			ticks_slot_overhead =
-				MAX(aux->ull.ticks_active_to_start,
-				    aux->ull.ticks_prepare_to_start);
+			ticks_slot_overhead = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 		} else {
 			ticks_slot_overhead = 0U;
 		}
@@ -275,9 +273,7 @@ static uint8_t big_create(uint8_t big_handle, uint8_t adv_handle, uint8_t num_bi
 		ticks_slot_aux = HAL_TICKER_US_TO_TICKS_CEIL(time_us);
 		if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
 			/* Assume primary overheads may be inherited by aux */
-			ticks_slot_overhead =
-				MAX(adv->ull.ticks_active_to_start,
-				    adv->ull.ticks_prepare_to_start);
+			ticks_slot_overhead = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 		} else {
 			ticks_slot_overhead = 0U;
 		}
@@ -299,8 +295,7 @@ static uint8_t big_create(uint8_t big_handle, uint8_t adv_handle, uint8_t num_bi
 	}
 
 	if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
-		ticks_slot_overhead = MAX(sync->ull.ticks_active_to_start,
-					  sync->ull.ticks_prepare_to_start);
+		ticks_slot_overhead = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 	} else {
 		ticks_slot_overhead = 0U;
 	}
@@ -483,15 +478,25 @@ static uint8_t big_create(uint8_t big_handle, uint8_t adv_handle, uint8_t num_bi
 	}
 
 	/* Based on packing requested, sequential or interleaved */
-	if (packing) {
+	if (false) {
+
+#if defined(CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED)
+	} else if (packing) {
 		/* Interleaved Packing */
 		lll_adv_iso->bis_spacing = lll_adv_iso->sub_interval;
 		lll_adv_iso->sub_interval = lll_adv_iso->bis_spacing *
-					lll_adv_iso->nse;
-	} else {
+					    lll_adv_iso->num_bis;
+#endif /* CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED */
+
+#if defined(CONFIG_BT_CTLR_ADV_ISO_SEQUENTIAL)
+	} else if (true) {
 		/* Sequential Packing */
 		lll_adv_iso->bis_spacing = lll_adv_iso->sub_interval *
-					lll_adv_iso->nse;
+					   lll_adv_iso->nse;
+#endif /* CONFIG_BT_CTLR_ADV_ISO_SEQUENTIAL */
+
+	} else {
+		return BT_HCI_ERR_UNSUPP_FEATURE_PARAM_VAL;
 	}
 
 	/* TODO: Group count, GC = NSE / BN; PTO = GC - IRC;
@@ -1250,11 +1255,26 @@ static uint32_t adv_iso_time_get(const struct ll_adv_iso_set *adv_iso, bool max)
 	 */
 
 	if (IS_ENABLED(CONFIG_BT_CTLR_ADV_ISO_RESERVE_MAX) || max) {
+		/* Maximum time reservation for both sequential and interleaved
+		 * packing.
+		 */
 		time_us = (pdu_spacing * lll_iso->nse * lll_iso->num_bis) +
 			  ctrl_spacing;
-	} else {
+
+	} else if (lll_iso->bis_spacing >=
+		   (lll_iso->sub_interval * lll_iso->nse)) {
+		/* Time reservation omitting PTC subevents in sequetial
+		 * packing.
+		 */
 		time_us = pdu_spacing * ((lll_iso->nse * lll_iso->num_bis) -
 					 lll_iso->ptc);
+
+	} else {
+		/* Time reservation omitting PTC subevents in interleaved
+		 * packing.
+		 */
+		time_us = pdu_spacing * ((lll_iso->nse - lll_iso->ptc) *
+					 lll_iso->num_bis);
 	}
 
 	/* Add implementation defined radio event overheads */
@@ -1279,15 +1299,9 @@ static uint32_t adv_iso_start(struct ll_adv_iso_set *adv_iso,
 
 	slot_us = adv_iso_time_get(adv_iso, false);
 
-	adv_iso->ull.ticks_active_to_start = 0U;
-	adv_iso->ull.ticks_prepare_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
-	adv_iso->ull.ticks_preempt_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
 	adv_iso->ull.ticks_slot = HAL_TICKER_US_TO_TICKS_CEIL(slot_us);
 
-	ticks_slot_offset = MAX(adv_iso->ull.ticks_active_to_start,
-				adv_iso->ull.ticks_prepare_to_start);
+	ticks_slot_offset = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 	if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
 		ticks_slot_overhead = ticks_slot_offset;
 	} else {
diff --git a/subsys/bluetooth/controller/ll_sw/ull_adv_sync.c b/subsys/bluetooth/controller/ll_sw/ull_adv_sync.c
index fb111a02f8b..72b1c3b1983 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_adv_sync.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_adv_sync.c
@@ -278,7 +278,7 @@ uint8_t ll_adv_sync_ad_data_set(uint8_t handle, uint8_t op, uint8_t len,
 	/* Check if periodic advertising is associated with advertising set */
 	lll_sync = adv->lll.sync;
 	if (!lll_sync) {
-		return BT_HCI_ERR_UNKNOWN_ADV_IDENTIFIER;
+		return BT_HCI_ERR_CMD_DISALLOWED;
 	}
 
 	sync = HDR_LLL2ULL(lll_sync);
@@ -804,16 +804,9 @@ uint32_t ull_adv_sync_evt_init(struct ll_adv_set *adv,
 
 	time_us = sync_time_get(sync, pdu);
 
-	/* TODO: active_to_start feature port */
-	sync->ull.ticks_active_to_start = 0U;
-	sync->ull.ticks_prepare_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
-	sync->ull.ticks_preempt_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
 	sync->ull.ticks_slot = HAL_TICKER_US_TO_TICKS_CEIL(time_us);
 
-	ticks_slot_offset = MAX(sync->ull.ticks_active_to_start,
-				sync->ull.ticks_prepare_to_start);
+	ticks_slot_offset = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 	if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
 		ticks_slot_overhead = ticks_slot_offset;
 	} else {
@@ -2690,7 +2683,7 @@ static void mfy_sync_offset_get(void *param)
 	uint32_t ticks_to_expire;
 	uint32_t ticks_current;
 	struct pdu_adv *pdu;
-	uint32_t remainder;
+	uint32_t remainder = 0U;
 	uint8_t chm_first;
 	uint8_t ticker_id;
 	uint16_t lazy;
diff --git a/subsys/bluetooth/controller/ll_sw/ull_central.c b/subsys/bluetooth/controller/ll_sw/ull_central.c
index aadeeb8d8f6..000f1640223 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_central.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_central.c
@@ -316,13 +316,6 @@ uint8_t ll_create_connection(uint16_t scan_interval, uint16_t scan_window,
 	conn_lll->tifs_hcto_us = EVENT_IFS_DEFAULT_US;
 	conn_lll->tifs_cis_us = EVENT_IFS_DEFAULT_US;
 
-	/* TODO: active_to_start feature port */
-	conn->ull.ticks_active_to_start = 0U;
-	conn->ull.ticks_prepare_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
-	conn->ull.ticks_preempt_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
-
 #if defined(CONFIG_BT_CTLR_CHECK_SAME_PEER_CONN)
 	/* Remember peer and own identity address */
 	conn->peer_id_addr_type = peer_addr_type;
@@ -802,8 +795,7 @@ void ull_central_setup(struct node_rx_pdu *rx, struct node_rx_ftr *ftr,
 
 	ll_rx_put_sched(link, rx);
 
-	ticks_slot_offset = MAX(conn->ull.ticks_active_to_start,
-				conn->ull.ticks_prepare_to_start);
+	ticks_slot_offset = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 	if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
 		ticks_slot_overhead = ticks_slot_offset;
 	} else {
diff --git a/subsys/bluetooth/controller/ll_sw/ull_central_iso.c b/subsys/bluetooth/controller/ll_sw/ull_central_iso.c
index d49256e3b09..0459dee9b16 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_central_iso.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_central_iso.c
@@ -600,11 +600,6 @@ uint8_t ll_cig_parameters_commit(uint8_t cig_id, uint16_t *handles)
 	slot_us += EVENT_OVERHEAD_START_US + EVENT_OVERHEAD_END_US;
 
 	/* Populate the ULL hdr with event timings overheads */
-	cig->ull.ticks_active_to_start = 0U;
-	cig->ull.ticks_prepare_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
-	cig->ull.ticks_preempt_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
 	cig->ull.ticks_slot = HAL_TICKER_US_TO_TICKS_CEIL(slot_us);
 #endif /* !CONFIG_BT_CTLR_JIT_SCHEDULING */
 
@@ -841,7 +836,6 @@ uint8_t ull_central_iso_setup(uint16_t cis_handle,
 {
 	struct ll_conn_iso_stream *cis;
 	struct ll_conn_iso_group *cig;
-	uint16_t event_counter;
 	struct ll_conn *conn;
 	uint16_t instant;
 
@@ -857,12 +851,14 @@ uint8_t ull_central_iso_setup(uint16_t cis_handle,
 
 	/* ACL connection of the new CIS */
 	conn = ll_conn_get(cis->lll.acl_handle);
-	event_counter = ull_conn_event_counter(conn);
-	instant = MAX(*conn_event_count, event_counter + 1);
 
 #if defined(CONFIG_BT_CTLR_JIT_SCHEDULING)
+	uint16_t event_counter;
 	uint32_t cis_offset;
 
+	event_counter = ull_conn_event_counter(conn);
+	instant = MAX(*conn_event_count, event_counter + 1);
+
 	cis_offset = *cis_offset_min;
 
 	/* Calculate offset for CIS */
@@ -902,6 +898,8 @@ uint8_t ull_central_iso_setup(uint16_t cis_handle,
 
 #else /* !CONFIG_BT_CTLR_JIT_SCHEDULING */
 
+	instant = *conn_event_count;
+
 	if (false) {
 
 #if defined(CONFIG_BT_CTLR_CENTRAL_SPACING)
@@ -923,6 +921,8 @@ uint8_t ull_central_iso_setup(uint16_t cis_handle,
 	} else {
 		cis->offset = *cis_offset_min;
 	}
+
+	cis->lll.prepared = 0U;
 #endif /* !CONFIG_BT_CTLR_JIT_SCHEDULING */
 
 	cis->central.instant = instant;
@@ -975,7 +975,18 @@ int ull_central_iso_cis_offset_get(uint16_t cis_handle,
 
 	conn = ll_conn_get(cis->lll.acl_handle);
 
-	cis->central.instant = ull_conn_event_counter(conn) + 3U;
+	/* NOTE: CIS Create Procedure uses 3 PDU transmissions, hence minimum relative instant not
+	 *       be less than 3. As the CIS_REQ PDU will be transmitted in the next ACL interval,
+	 *       add +1 to the instant. The +1 also helps with the fact that currently we do not
+	 *       have Central implementation to handle event latencies at the instant. Refer to
+	 *       `ull_conn_iso_start()` implementation.
+	 *
+	 *       `ull_conn_llcp()` is called before `ull_ref_inc()` hence we do not need to use
+	 *       `ull_conn_event_counter()`.
+	 */
+	cis->central.instant = conn->lll.event_counter + conn->lll.latency_prepare +
+			       conn->llcp.prep.lazy + 4U;
+
 	*conn_event_count = cis->central.instant;
 
 	/* Provide CIS offset range
@@ -1090,7 +1101,7 @@ static void mfy_cis_offset_get(void *param)
 	uint32_t ticks_current;
 	uint32_t offset_min_us;
 	struct ll_conn *conn;
-	uint32_t remainder;
+	uint32_t remainder = 0U;
 	uint8_t ticker_id;
 	uint16_t lazy;
 	uint8_t retry;
@@ -1177,7 +1188,12 @@ static void mfy_cis_offset_get(void *param)
 	 * and latency counts (typically 3) is low enough to avoid 32-bit
 	 * overflow. Refer to ull_central_iso_cis_offset_get().
 	 */
-	latency_acl = cis->central.instant - ull_conn_event_counter(conn);
+	/* FIXME: Mayfly execution of `mfy_cig_offset_get()` could be before "LLL Prepare" or after
+	 *        conn->lll.event_counter could have been pre-incremented.
+	 *        This race condition needs a fix.
+	 */
+	latency_acl = cis->central.instant - conn->lll.event_counter - conn->lll.latency_prepare -
+		      conn->llcp.prep.lazy;
 	elapsed_acl_us = latency_acl * conn->lll.interval * CONN_INT_UNIT_US;
 
 	/* Calculate elapsed CIG intervals until the instant */
@@ -1201,7 +1217,7 @@ static void mfy_cis_offset_get(void *param)
 	 * CIG interval.
 	 */
 	if (offset_min_us > cig_interval_us) {
-		cis->lll.event_count--;
+		cis->lll.event_count_prepare--;
 	}
 
 	ull_cp_cc_offset_calc_reply(conn, offset_min_us, offset_min_us);
diff --git a/subsys/bluetooth/controller/ll_sw/ull_conn.c b/subsys/bluetooth/controller/ll_sw/ull_conn.c
index 7661bfa6dd2..1be21cfe420 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_conn.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_conn.c
@@ -706,6 +706,12 @@ uint8_t ll_apto_get(uint16_t handle, uint16_t *apto)
 {
 	struct ll_conn *conn;
 
+#if defined(CONFIG_BT_CTLR_ISO)
+	if (IS_CIS_HANDLE(handle) || IS_SYNC_ISO_HANDLE(handle) || IS_ADV_ISO_HANDLE(handle)) {
+		return BT_HCI_ERR_CMD_DISALLOWED;
+	}
+#endif /* CONFIG_BT_CTLR_ISO */
+
 	conn = ll_connected_get(handle);
 	if (!conn) {
 		return BT_HCI_ERR_UNKNOWN_CONN_ID;
@@ -726,6 +732,12 @@ uint8_t ll_apto_set(uint16_t handle, uint16_t apto)
 {
 	struct ll_conn *conn;
 
+#if defined(CONFIG_BT_CTLR_ISO)
+	if (IS_CIS_HANDLE(handle) || IS_SYNC_ISO_HANDLE(handle) || IS_ADV_ISO_HANDLE(handle)) {
+		return BT_HCI_ERR_CMD_DISALLOWED;
+	}
+#endif /* CONFIG_BT_CTLR_ISO */
+
 	conn = ll_connected_get(handle);
 	if (!conn) {
 		return BT_HCI_ERR_UNKNOWN_CONN_ID;
@@ -2227,8 +2239,8 @@ void ull_conn_update_parameters(struct ll_conn *conn, uint8_t is_cu_proc, uint8_
 	uint16_t conn_interval_unit_old;
 	uint16_t conn_interval_unit_new;
 	uint32_t ticks_win_offset = 0U;
-	uint16_t conn_interval_old_us;
-	uint16_t conn_interval_new_us;
+	uint32_t conn_interval_old_us;
+	uint32_t conn_interval_new_us;
 	uint32_t ticks_slot_overhead;
 	uint16_t conn_interval_old;
 	uint16_t conn_interval_new;
@@ -2251,18 +2263,6 @@ void ull_conn_update_parameters(struct ll_conn *conn, uint8_t is_cu_proc, uint8_
 
 	ticks_at_expire = conn->llcp.prep.ticks_at_expire;
 
-#if defined(CONFIG_BT_CTLR_XTAL_ADVANCED)
-	/* restore to normal prepare */
-	if (conn->ull.ticks_prepare_to_start & XON_BITMASK) {
-		uint32_t ticks_prepare_to_start =
-			MAX(conn->ull.ticks_active_to_start, conn->ull.ticks_preempt_to_start);
-
-		conn->ull.ticks_prepare_to_start &= ~XON_BITMASK;
-
-		ticks_at_expire -= (conn->ull.ticks_prepare_to_start - ticks_prepare_to_start);
-	}
-#endif /* CONFIG_BT_CTLR_XTAL_ADVANCED */
-
 #if defined(CONFIG_BT_CTLR_PHY)
 	ready_delay_us = lll_radio_tx_ready_delay_get(lll->phy_tx,
 						      lll->phy_flags);
@@ -2353,10 +2353,7 @@ void ull_conn_update_parameters(struct ll_conn *conn, uint8_t is_cu_proc, uint8_
 
 	/* calculate the offset */
 	if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
-		ticks_slot_overhead =
-			MAX(conn->ull.ticks_active_to_start,
-			    conn->ull.ticks_prepare_to_start);
-
+		ticks_slot_overhead = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 	} else {
 		ticks_slot_overhead = 0U;
 	}
@@ -2744,7 +2741,7 @@ static uint32_t get_ticker_offset(uint8_t ticker_id, uint16_t *lazy)
 	uint32_t ticks_to_expire;
 	uint32_t ticks_current;
 	uint32_t sync_remainder_us;
-	uint32_t remainder;
+	uint32_t remainder = 0U;
 	uint32_t start_us;
 	uint32_t ret;
 	uint8_t id;
diff --git a/subsys/bluetooth/controller/ll_sw/ull_conn_iso.c b/subsys/bluetooth/controller/ll_sw/ull_conn_iso.c
index b25267a34bd..5907e770079 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_conn_iso.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_conn_iso.c
@@ -311,6 +311,7 @@ ull_conn_iso_lll_stream_sorted_get_by_group(struct lll_conn_iso_group *cig_lll,
 					    uint16_t *handle_iter)
 {
 	struct ll_conn_iso_stream *cis_next = NULL;
+	struct ll_conn_iso_stream *cis_curr;
 	struct ll_conn_iso_group *cig;
 	uint32_t cis_offset_curr;
 	uint32_t cis_offset_next;
@@ -322,16 +323,15 @@ ull_conn_iso_lll_stream_sorted_get_by_group(struct lll_conn_iso_group *cig_lll,
 		/* First in the iteration, start with a minimum offset value and
 		 * find the first CIS offset of the active CIS.
 		 */
+		cis_curr = NULL;
 		cis_offset_curr = 0U;
 	} else {
 		/* Subsequent iteration, get reference to current CIS and use
 		 * its CIS offset to find the next active CIS with offset
 		 * greater than the current CIS.
 		 */
-		struct ll_conn_iso_stream *cis_curr;
-
 		cis_curr = ll_conn_iso_stream_get(*handle_iter);
-		cis_offset_curr = cis_curr->offset;
+		cis_offset_curr = cis_curr->lll.offset;
 	}
 
 	cis_offset_next = UINT32_MAX;
@@ -346,7 +346,7 @@ ull_conn_iso_lll_stream_sorted_get_by_group(struct lll_conn_iso_group *cig_lll,
 
 		/* Match CIS contexts associated with the CIG */
 		if (cis->group == cig) {
-			if (cis->offset <= cis_offset_curr) {
+			if (cis_curr && (cis->lll.offset <= cis_offset_curr)) {
 				/* Skip already returned CISes with offsets less
 				 * than the current CIS.
 				 */
@@ -357,9 +357,9 @@ ull_conn_iso_lll_stream_sorted_get_by_group(struct lll_conn_iso_group *cig_lll,
 			 * lower than previous that we remember as the next CIS
 			 * in ascending order.
 			 */
-			if (cis->offset < cis_offset_next) {
+			if (cis->lll.offset < cis_offset_next) {
 				cis_next = cis;
-				cis_offset_next = cis_next->offset;
+				cis_offset_next = cis_next->lll.offset;
 
 				if (handle_iter) {
 					(*handle_iter) = handle;
@@ -977,10 +977,20 @@ void ull_conn_iso_start(struct ll_conn *conn, uint16_t cis_handle,
 
 			cis->lll.event_count_prepare += lost_cig_events;
 
-			lost_payloads = (lost_cig_events - (cis->lll.rx.ft - 1)) * cis->lll.rx.bn;
+			if (lost_cig_events > (cis->lll.rx.ft - 1)) {
+				lost_payloads = (lost_cig_events - (cis->lll.rx.ft - 1)) *
+						cis->lll.rx.bn;
+			} else {
+				lost_payloads = 0U;
+			}
 			cis->lll.rx.payload_count += lost_payloads;
 
-			lost_payloads = (lost_cig_events - (cis->lll.tx.ft - 1)) * cis->lll.tx.bn;
+			if (lost_cig_events > (cis->lll.tx.ft - 1)) {
+				lost_payloads = (lost_cig_events - (cis->lll.tx.ft - 1)) *
+						cis->lll.tx.bn;
+			} else {
+				lost_payloads = 0U;
+			}
 			cis->lll.tx.payload_count += lost_payloads;
 
 			/* Adjust for extra window widening */
@@ -1054,16 +1064,10 @@ void ull_conn_iso_start(struct ll_conn *conn, uint16_t cis_handle,
 		 */
 
 		/* Populate the ULL hdr with event timings overheads */
-		cig->ull.ticks_active_to_start = 0U;
-		cig->ull.ticks_prepare_to_start =
-			HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
-		cig->ull.ticks_preempt_to_start =
-			HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
 		cig->ull.ticks_slot = HAL_TICKER_US_TO_TICKS_CEIL(slot_us);
 	}
 
-	ticks_slot_offset = MAX(cig->ull.ticks_active_to_start,
-				cig->ull.ticks_prepare_to_start);
+	ticks_slot_offset = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 
 	if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
 		ticks_slot_overhead = ticks_slot_offset;
@@ -1075,6 +1079,7 @@ void ull_conn_iso_start(struct ll_conn *conn, uint16_t cis_handle,
 
 	/* Initialize CIS event lazy at CIS create */
 	cis->lll.lazy_active = 0U;
+	cis->lll.prepared = 0U;
 #endif /* !CONFIG_BT_CTLR_JIT_SCHEDULING */
 
 	/* Start CIS peripheral CIG ticker */
@@ -1113,7 +1118,7 @@ static void mfy_cis_lazy_fill(void *param)
 	struct ll_conn_iso_group *cig;
 	uint32_t ticks_to_expire;
 	uint32_t ticks_current;
-	uint32_t remainder;
+	uint32_t remainder = 0U;
 	uint16_t lazy = 0U;
 	uint8_t ticker_id;
 	uint8_t retry;
@@ -1178,6 +1183,7 @@ static void mfy_cis_lazy_fill(void *param)
 	 * CIG before the CIS gets active that be decremented when event_count
 	 * is incremented in ull_conn_iso_ticker_cb().
 	 */
+	cis->lll.prepared = 0U;
 	cis->lll.active = 1U;
 	cis->lll.lazy_active = lazy;
 }
@@ -1221,6 +1227,11 @@ static void cis_disabled_cb(void *param)
 	handle_iter = UINT16_MAX;
 	active_cises = 0;
 
+	if (cig->ull.disabled_cb == cis_disabled_cb) {
+		/* Reset disabled_cb */
+		cig->ull.disabled_cb = NULL;
+	}
+
 	/* Remove all CISes marked for teardown */
 	num_cis = cig->lll.num_cis;
 	for (cis_idx = 0; cis_idx < num_cis; cis_idx++) {
@@ -1287,7 +1298,6 @@ static void cis_disabled_cb(void *param)
 		} else if (cis->teardown) {
 			DECLARE_MAYFLY_ARRAY(mfys, cis_tx_lll_flush,
 				CONFIG_BT_CTLR_CONN_ISO_GROUPS);
-			uint32_t ret;
 
 			if (cis->established) {
 				struct node_rx_pdu *node_terminate;
@@ -1328,11 +1338,12 @@ static void cis_disabled_cb(void *param)
 			 */
 			cis->lll.flush = LLL_CIS_FLUSH_PENDING;
 
-			mfys[cig->lll.handle].param = &cis->lll;
-			ret = mayfly_enqueue(TICKER_USER_ID_ULL_HIGH,
+			/* Ignore enqueue error (already enqueued) as all CISes marked for
+			 * flushing will be handled in cis_tx_lll_flush
+			 */
+			mfys[cig->lll.handle].param = cig;
+			(void)mayfly_enqueue(TICKER_USER_ID_ULL_HIGH,
 					     TICKER_USER_ID_LLL, 1, &mfys[cig->lll.handle]);
-			LL_ASSERT(!ret);
-
 			return;
 		}
 	}
@@ -1359,37 +1370,58 @@ static void cis_tx_lll_flush(void *param)
 {
 	DECLARE_MAYFLY_ARRAY(mfys, cis_disabled_cb, CONFIG_BT_CTLR_CONN_ISO_GROUPS);
 
-	struct lll_conn_iso_stream *lll;
-	struct ll_conn_iso_stream *cis;
 	struct ll_conn_iso_group *cig;
-	struct node_tx_iso *tx;
-	memq_link_t *link;
+	uint16_t handle_iter;
+	uint8_t cis_idx;
+	uint8_t num_cis;
 
-	lll = param;
-	lll->active = 0U;
+	cig = param;
+	handle_iter = UINT16_MAX;
 
-	cis = ll_conn_iso_stream_get(lll->handle);
-	cig = cis->group;
+	/* Flush all CISes in CIG marked for flush */
+	num_cis = cig->lll.num_cis;
+	for (cis_idx = 0; cis_idx < num_cis; cis_idx++) {
+		struct lll_conn_iso_stream *lll;
+		struct ll_conn_iso_stream *cis;
+		struct node_tx_iso *tx;
+		memq_link_t *link;
+
+		cis = ll_conn_iso_stream_get_by_group(cig, &handle_iter);
+		LL_ASSERT(cis);
 
-	/* Flush in LLL - may return TX nodes to ack queue */
-	lll_conn_iso_flush(lll->handle, lll);
+		lll = &cis->lll;
 
-	link = memq_dequeue(lll->memq_tx.tail, &lll->memq_tx.head, (void **)&tx);
-	while (link) {
-		link->next = tx->next;
-		tx->next = link;
-		ull_iso_lll_ack_enqueue(lll->handle, tx);
+		if (lll->flush != LLL_CIS_FLUSH_PENDING) {
+			/* Not flushing this CIS, skip */
+			continue;
+		}
 
-		link = memq_dequeue(lll->memq_tx.tail, &lll->memq_tx.head,
-				    (void **)&tx);
-	}
+		lll->active = 0U;
 
-	LL_ASSERT(!lll->link_tx_free);
-	link = memq_deinit(&lll->memq_tx.head, &lll->memq_tx.tail);
-	LL_ASSERT(link);
-	lll->link_tx_free = link;
+#if !defined(CONFIG_BT_CTLR_JIT_SCHEDULING)
+		lll->prepared = 0U;
+#endif /* !CONFIG_BT_CTLR_JIT_SCHEDULING */
+
+		/* Flush in LLL - may return TX nodes to ack queue */
+		lll_conn_iso_flush(lll->handle, lll);
+
+		link = memq_dequeue(lll->memq_tx.tail, &lll->memq_tx.head, (void **)&tx);
+		while (link) {
+			link->next = tx->next;
+			tx->next = link;
+			ull_iso_lll_ack_enqueue(lll->handle, tx);
 
-	lll->flush = LLL_CIS_FLUSH_COMPLETE;
+			link = memq_dequeue(lll->memq_tx.tail, &lll->memq_tx.head,
+					    (void **)&tx);
+		}
+
+		LL_ASSERT(!lll->link_tx_free);
+		link = memq_deinit(&lll->memq_tx.head, &lll->memq_tx.tail);
+		LL_ASSERT(link);
+		lll->link_tx_free = link;
+
+		lll->flush = LLL_CIS_FLUSH_COMPLETE;
+	}
 
 	/* Resume CIS teardown in ULL_HIGH context */
 	mfys[cig->lll.handle].param = &cig->lll;
diff --git a/subsys/bluetooth/controller/ll_sw/ull_iso.c b/subsys/bluetooth/controller/ll_sw/ull_iso.c
index f10b4c15f11..efbcf411819 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_iso.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_iso.c
@@ -156,12 +156,12 @@ void ll_iso_tx_mem_release(void *node_tx);
 
 static struct {
 	void *free;
-	uint8_t pool[NODE_TX_BUFFER_SIZE * BT_CTLR_ISO_TX_BUFFERS];
+	uint8_t pool[NODE_TX_BUFFER_SIZE * BT_CTLR_ISO_TX_PDU_BUFFERS];
 } mem_iso_tx;
 
 static struct {
 	void *free;
-	uint8_t pool[sizeof(memq_link_t) * BT_CTLR_ISO_TX_BUFFERS];
+	uint8_t pool[sizeof(memq_link_t) * BT_CTLR_ISO_TX_PDU_BUFFERS];
 } mem_link_iso_tx;
 
 #endif /* CONFIG_BT_CTLR_ADV_ISO || CONFIG_BT_CTLR_CONN_ISO */
@@ -1165,7 +1165,7 @@ void ll_iso_transmit_test_send_sdu(uint16_t handle, uint32_t ticks_at_expire)
 		sdu.grp_ref_point = isoal_get_wrapped_time_us(cig->cig_ref_point,
 						(event_offset * cig->iso_interval *
 							ISO_INT_UNIT_US));
-		sdu.target_event = cis->lll.event_count + event_offset;
+		sdu.target_event = cis->lll.event_count_prepare + event_offset;
 		sdu.iso_sdu_length = remaining_tx;
 
 		/* Send all SDU fragments */
@@ -1595,7 +1595,7 @@ static void iso_rx_cig_ref_point_update(struct ll_conn_iso_group *cig,
 	cig_sync_delay = cig->sync_delay;
 	cis_sync_delay = cis->sync_delay;
 	burst_number = cis->lll.rx.bn;
-	event_count = cis->lll.event_count;
+	event_count = cis->lll.event_count_prepare;
 
 	if (role) {
 		/* Peripheral */
@@ -1960,12 +1960,12 @@ static int init_reset(void)
 
 #if defined(CONFIG_BT_CTLR_ADV_ISO) || defined(CONFIG_BT_CTLR_CONN_ISO)
 	/* Initialize tx pool. */
-	mem_init(mem_iso_tx.pool, NODE_TX_BUFFER_SIZE, BT_CTLR_ISO_TX_BUFFERS,
+	mem_init(mem_iso_tx.pool, NODE_TX_BUFFER_SIZE, BT_CTLR_ISO_TX_PDU_BUFFERS,
 		 &mem_iso_tx.free);
 
 	/* Initialize tx link pool. */
-	mem_init(mem_link_iso_tx.pool, sizeof(memq_link_t),
-		 BT_CTLR_ISO_TX_BUFFERS, &mem_link_iso_tx.free);
+	mem_init(mem_link_iso_tx.pool, sizeof(memq_link_t), BT_CTLR_ISO_TX_PDU_BUFFERS,
+		 &mem_link_iso_tx.free);
 #endif /* CONFIG_BT_CTLR_ADV_ISO || CONFIG_BT_CTLR_CONN_ISO */
 
 #if BT_CTLR_ISO_STREAMS
diff --git a/subsys/bluetooth/controller/ll_sw/ull_iso_internal.h b/subsys/bluetooth/controller/ll_sw/ull_iso_internal.h
index bf4e66cbde0..4bd8fe1c620 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_iso_internal.h
+++ b/subsys/bluetooth/controller/ll_sw/ull_iso_internal.h
@@ -4,21 +4,42 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#if defined(CONFIG_BT_CTLR_ADV_ISO) || defined(CONFIG_BT_CTLR_CONN_ISO)
 /* Calculate ISO PDU buffers required considering SDU fragmentation */
-/* FIXME: Calculation considering both Connected and Broadcast ISO PDU
- *        fragmentation.
+#if defined(CONFIG_BT_CTLR_ADV_ISO) || defined(CONFIG_BT_CTLR_CONN_ISO)
+/* Internal ISO Tx SDU maximum length.
+ * A length that is minimum of the resultant combination of the HCI ISO data fragments provided and
+ * the user configured maximum transmit SDU length (CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX).
+ */
+#define BT_CTLR_ISO_TX_SDU_LEN_MAX MIN(((CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE * \
+					 CONFIG_BT_CTLR_ISO_TX_BUFFERS) - \
+					BT_HCI_ISO_SDU_HDR_SIZE), \
+				       CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX)
+
+BUILD_ASSERT(BT_CTLR_ISO_TX_SDU_LEN_MAX == CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX,
+	     "Insufficient ISO Buffer Size and Count for the required ISO SDU Length");
+
+/* Internal ISO Tx buffers to be allocated.
+ * Based on the internal ISO Tx SDU maximum length, calculate the required ISO Tx buffers (PDUs)
+ * required to fragment the SDU into PDU sizes scheduled for transmission.
+ */
+/* Defines the minimum required PDU length to help calculate the number of PDU buffers required
+ * At least one of CONFIG_BT_CTLR_ADV_ISO or CONFIG_BT_CTLR_CONN_ISO will always be enabled,
+ * so if either of them is not defined, it can default to the other
  */
-#if defined(CONFIG_BT_CTLR_CONN_ISO)
-#define BT_CTLR_ISO_TX_BUFFERS (((CONFIG_BT_CTLR_CONN_ISO_SDU_LEN_MAX + \
-				  CONFIG_BT_CTLR_CONN_ISO_PDU_LEN_MAX - 1U) / \
-				 CONFIG_BT_CTLR_CONN_ISO_PDU_LEN_MAX) * \
-				CONFIG_BT_CTLR_ISO_TX_BUFFERS)
-#else /* !CONFIG_BT_CTLR_CONN_ISO */
-#define BT_CTLR_ISO_TX_BUFFERS CONFIG_BT_CTLR_ISO_TX_BUFFERS
-#endif /* !CONFIG_BT_CTLR_CONN_ISO */
+#define BT_CTLR_ISO_TX_MIN_PDU_LEN \
+	MIN(COND_CODE_1(IS_ENABLED(CONFIG_BT_CTLR_ADV_ISO), \
+			(CONFIG_BT_CTLR_ADV_ISO_PDU_LEN_MAX), \
+			(CONFIG_BT_CTLR_CONN_ISO_PDU_LEN_MAX)), \
+	    COND_CODE_1(IS_ENABLED(CONFIG_BT_CTLR_CONN_ISO), \
+			(CONFIG_BT_CTLR_CONN_ISO_PDU_LEN_MAX), \
+			(CONFIG_BT_CTLR_ADV_ISO_PDU_LEN_MAX)))
+#define BT_CTLR_ISO_TX_PDU_BUFFERS \
+	(DIV_ROUND_UP(BT_CTLR_ISO_TX_SDU_LEN_MAX, \
+		      MIN((CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE - BT_HCI_ISO_SDU_TS_HDR_SIZE), \
+			  BT_CTLR_ISO_TX_MIN_PDU_LEN)) * \
+	 CONFIG_BT_CTLR_ISO_TX_BUFFERS)
 #else /* !CONFIG_BT_CTLR_ADV_ISO && !CONFIG_BT_CTLR_CONN_ISO */
-#define BT_CTLR_ISO_TX_BUFFERS 0
+#define BT_CTLR_ISO_TX_PDU_BUFFERS 0
 #endif /* !CONFIG_BT_CTLR_ADV_ISO && !CONFIG_BT_CTLR_CONN_ISO */
 
 int ull_iso_init(void);
diff --git a/subsys/bluetooth/controller/ll_sw/ull_llcp_cc.c b/subsys/bluetooth/controller/ll_sw/ull_llcp_cc.c
index 92e66dd8e35..f0d09e76356 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_llcp_cc.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_llcp_cc.c
@@ -53,6 +53,10 @@
 #include <soc.h>
 #include "hal/debug.h"
 
+#include <zephyr/bluetooth/iso.h>
+
+#define SUB_INTERVAL_MIN 400
+
 static void cc_ntf_established(struct ll_conn *conn, struct proc_ctx *ctx)
 {
 	struct node_rx_conn_iso_estab *pdu;
@@ -321,6 +325,82 @@ static uint8_t rp_cc_check_phy(struct ll_conn *conn, struct proc_ctx *ctx,
 	return BT_HCI_ERR_SUCCESS;
 }
 
+/* Validate that the LL_CIS_REQ parameters are valid according to the rules in
+ * Core Specification v5.4, Vol. 6, Part B, Section 2.4.2.29
+ */
+static uint8_t rp_cc_validate_req(struct ll_conn *conn, struct proc_ctx *ctx,
+				  struct pdu_data *pdu)
+{
+	uint32_t cis_offset_max;
+	uint32_t cis_offset_min;
+	uint32_t c_sdu_interval;
+	uint32_t p_sdu_interval;
+	uint32_t sub_interval;
+	uint16_t iso_interval;
+	uint16_t c_max_pdu;
+	uint16_t p_max_pdu;
+	uint8_t result;
+
+	result = rp_cc_check_phy(conn, ctx, pdu);
+	if (result != BT_HCI_ERR_SUCCESS) {
+		return result;
+	}
+
+	/* Note: SDU intervals are 20 bits; Mask away RFU bits */
+	c_sdu_interval = sys_get_le24(pdu->llctrl.cis_req.c_sdu_interval) & 0x0FFFFF;
+	p_sdu_interval = sys_get_le24(pdu->llctrl.cis_req.p_sdu_interval) & 0x0FFFFF;
+	if (c_sdu_interval < BT_HCI_ISO_SDU_INTERVAL_MIN ||
+	    p_sdu_interval < BT_HCI_ISO_SDU_INTERVAL_MIN) {
+		return BT_HCI_ERR_INVALID_LL_PARAM;
+	}
+
+	c_max_pdu = sys_le16_to_cpu(pdu->llctrl.cis_req.c_max_pdu);
+	p_max_pdu = sys_le16_to_cpu(pdu->llctrl.cis_req.p_max_pdu);
+	if (c_max_pdu > BT_ISO_PDU_MAX || p_max_pdu > BT_ISO_PDU_MAX) {
+		return BT_HCI_ERR_INVALID_LL_PARAM;
+	}
+
+	if (!IN_RANGE(pdu->llctrl.cis_req.nse, BT_ISO_NSE_MIN, BT_ISO_NSE_MAX)) {
+		return BT_HCI_ERR_INVALID_LL_PARAM;
+	}
+
+	iso_interval = sys_le16_to_cpu(pdu->llctrl.cis_req.iso_interval);
+	sub_interval = sys_get_le24(pdu->llctrl.cis_req.sub_interval);
+	if (pdu->llctrl.cis_req.nse == 1) {
+		if (sub_interval > 0) {
+			return BT_HCI_ERR_INVALID_LL_PARAM;
+		}
+	} else if (!IN_RANGE(sub_interval, SUB_INTERVAL_MIN,
+			     iso_interval * CONN_INT_UNIT_US - 1)) {
+		return BT_HCI_ERR_INVALID_LL_PARAM;
+	}
+
+	if ((pdu->llctrl.cis_req.c_bn == 0 && c_max_pdu > 0) ||
+	    (pdu->llctrl.cis_req.p_bn == 0 && p_max_pdu > 0)) {
+		return BT_HCI_ERR_INVALID_LL_PARAM;
+	}
+
+	if (pdu->llctrl.cis_req.c_ft == 0 || pdu->llctrl.cis_req.p_ft == 0) {
+		return BT_HCI_ERR_INVALID_LL_PARAM;
+	}
+
+	if (!IN_RANGE(iso_interval, BT_HCI_ISO_INTERVAL_MIN, BT_HCI_ISO_INTERVAL_MAX)) {
+		return BT_HCI_ERR_INVALID_LL_PARAM;
+	}
+
+	cis_offset_min = sys_get_le24(pdu->llctrl.cis_req.cis_offset_min);
+	if (cis_offset_min < PDU_CIS_OFFSET_MIN_US) {
+		return BT_HCI_ERR_INVALID_LL_PARAM;
+	}
+
+	cis_offset_max = sys_get_le24(pdu->llctrl.cis_req.cis_offset_max);
+	if (!IN_RANGE(cis_offset_max, cis_offset_min, conn->lll.interval * CONN_INT_UNIT_US - 1)) {
+		return BT_HCI_ERR_INVALID_LL_PARAM;
+	}
+
+	return BT_HCI_ERR_SUCCESS;
+}
+
 static void rp_cc_state_wait_rx_cis_req(struct ll_conn *conn, struct proc_ctx *ctx, uint8_t evt,
 					void *param)
 {
@@ -331,8 +411,8 @@ static void rp_cc_state_wait_rx_cis_req(struct ll_conn *conn, struct proc_ctx *c
 		/* Handle CIS request */
 		llcp_pdu_decode_cis_req(ctx, pdu);
 
-		/* Check PHY */
-		ctx->data.cis_create.error = rp_cc_check_phy(conn, ctx, pdu);
+		/* Check validity of request */
+		ctx->data.cis_create.error = rp_cc_validate_req(conn, ctx, pdu);
 
 		if (ctx->data.cis_create.error == BT_HCI_ERR_SUCCESS) {
 			ctx->data.cis_create.error =
diff --git a/subsys/bluetooth/controller/ll_sw/ull_llcp_pdu.c b/subsys/bluetooth/controller/ll_sw/ull_llcp_pdu.c
index 240f2ccfab7..409200f4116 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_llcp_pdu.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_llcp_pdu.c
@@ -901,8 +901,15 @@ void llcp_pdu_decode_cis_rsp(struct proc_ctx *ctx, struct pdu_data *pdu)
 		ctx->data.cis_create.cis_offset_max = cis_offset_max;
 	}
 
+	/* FIXME: We do not pick the instant from the response; if we do, then
+	 *        we need to calculate again a new offset because the ACL and
+	 *        ISO intervals can be dissimilar and hence will be a different
+	 *        CIS offset when sending the CIS_IND PDU at this instant.
+	 *
+
 	ctx->data.cis_create.conn_event_count =
 		sys_le16_to_cpu(pdu->llctrl.cis_rsp.conn_event_count);
+	 */
 }
 
 void llcp_pdu_encode_cis_ind(struct proc_ctx *ctx, struct pdu_data *pdu)
diff --git a/subsys/bluetooth/controller/ll_sw/ull_peripheral.c b/subsys/bluetooth/controller/ll_sw/ull_peripheral.c
index 76ea607df4b..d23d50f2bf9 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_peripheral.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_peripheral.c
@@ -400,16 +400,9 @@ void ull_periph_setup(struct node_rx_pdu *rx, struct node_rx_ftr *ftr,
 		slot_us += EVENT_OVERHEAD_START_US + EVENT_OVERHEAD_END_US;
 	}
 
-	/* TODO: active_to_start feature port */
-	conn->ull.ticks_active_to_start = 0U;
-	conn->ull.ticks_prepare_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
-	conn->ull.ticks_preempt_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
 	conn->ull.ticks_slot = HAL_TICKER_US_TO_TICKS_CEIL(slot_us);
 
-	ticks_slot_offset = MAX(conn->ull.ticks_active_to_start,
-				conn->ull.ticks_prepare_to_start);
+	ticks_slot_offset = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 	if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
 		ticks_slot_overhead = ticks_slot_offset;
 	} else {
diff --git a/subsys/bluetooth/controller/ll_sw/ull_peripheral_iso.c b/subsys/bluetooth/controller/ll_sw/ull_peripheral_iso.c
index 77b3f240f1b..6e6ce570e9f 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_peripheral_iso.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_peripheral_iso.c
@@ -257,6 +257,11 @@ uint8_t ull_peripheral_iso_acquire(struct ll_conn *acl,
 				    req->p_max_sdu[0];
 
 	cis->lll.active = 0U;
+
+#if !defined(CONFIG_BT_CTLR_JIT_SCHEDULING)
+	cis->lll.prepared = 0U;
+#endif /* !CONFIG_BT_CTLR_JIT_SCHEDULING */
+
 	cis->lll.handle = LLL_HANDLE_INVALID;
 	cis->lll.acl_handle = acl->lll.handle;
 	cis->lll.sub_interval = sys_get_le24(req->sub_interval);
diff --git a/subsys/bluetooth/controller/ll_sw/ull_scan.c b/subsys/bluetooth/controller/ll_sw/ull_scan.c
index a1d90d3cc75..493c2330db0 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_scan.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_scan.c
@@ -411,16 +411,8 @@ uint8_t ull_scan_enable(struct ll_scan_set *scan)
 	ticks_interval = HAL_TICKER_US_TO_TICKS((uint64_t)lll->interval *
 						SCAN_INT_UNIT_US);
 
-	/* TODO: active_to_start feature port */
-	scan->ull.ticks_active_to_start = 0U;
-	scan->ull.ticks_prepare_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
-	scan->ull.ticks_preempt_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
-
 	if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
-		ticks_slot_overhead = MAX(scan->ull.ticks_active_to_start,
-					  scan->ull.ticks_prepare_to_start);
+		ticks_slot_overhead = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 	} else {
 		ticks_slot_overhead = 0U;
 	}
@@ -610,6 +602,9 @@ uint8_t ull_scan_enable(struct ll_scan_set *scan)
 	ret_cb = TICKER_STATUS_BUSY;
 
 #if defined(CONFIG_BT_TICKER_EXT)
+#if defined(CONFIG_BT_TICKER_EXT_EXPIRE_INFO)
+	ll_scan_ticker_ext[handle].expire_info_id = TICKER_NULL;
+#endif /* CONFIG_BT_TICKER_EXT_EXPIRE_INFO */
 	ret = ticker_start_ext(
 #else
 	ret = ticker_start(
diff --git a/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c b/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c
index 7419325254a..170168df237 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_scan_aux.c
@@ -872,19 +872,12 @@ void ull_scan_aux_setup(memq_link_t *link, struct node_rx_pdu *rx)
 		aux->rx_head = rx;
 	}
 
-	/* TODO: active_to_start feature port */
-	aux->ull.ticks_active_to_start = 0;
-	aux->ull.ticks_prepare_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
-	aux->ull.ticks_preempt_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
 	aux->ull.ticks_slot = HAL_TICKER_US_TO_TICKS_CEIL(
 		EVENT_OVERHEAD_START_US + ready_delay_us +
 		PDU_AC_MAX_US(PDU_AC_EXT_PAYLOAD_RX_SIZE, lll_aux->phy) +
 		EVENT_OVERHEAD_END_US);
 
-	ticks_slot_offset = MAX(aux->ull.ticks_active_to_start,
-				aux->ull.ticks_prepare_to_start);
+	ticks_slot_offset = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 	if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
 		ticks_slot_overhead = ticks_slot_offset;
 	} else {
@@ -2055,6 +2048,10 @@ void ull_scan_aux_setup(memq_link_t *link, struct node_rx_pdu *rx)
 		uint32_t ticks_now;
 		uint32_t diff;
 
+#if defined(CONFIG_BT_TICKER_SLOT_AGNOSTIC)
+		/* CPU execution overhead to setup the radio for reception */
+		overhead_us = EVENT_OVERHEAD_START_US;
+#else /* !CONFIG_BT_TICKER_SLOT_AGNOSTIC */
 		/* CPU execution overhead to setup the radio for reception plus the
 		 * minimum prepare tick offset. And allow one additional event in
 		 * between as overhead (say, an advertising event in between got closed
@@ -2062,6 +2059,7 @@ void ull_scan_aux_setup(memq_link_t *link, struct node_rx_pdu *rx)
 		 */
 		overhead_us = (EVENT_OVERHEAD_END_US + EVENT_OVERHEAD_START_US +
 			       HAL_TICKER_TICKS_TO_US(HAL_TICKER_CNTR_CMP_OFFSET_MIN)) << 1;
+#endif /* !CONFIG_BT_TICKER_SLOT_AGNOSTIC */
 
 		ticks_now = ticker_ticks_now_get();
 		ticks_at_expire = ftr->ticks_anchor + ticks_aux_offset -
@@ -2760,19 +2758,12 @@ static void chain_start_ticker(struct ll_scan_aux_chain *chain, bool replace)
 
 	ready_delay_us = lll_radio_rx_ready_delay_get(chain->lll.phy, PHY_FLAGS_S8);
 
-	/* TODO: active_to_start feature port */
-	scan_aux_set.ull.ticks_active_to_start = 0;
-	scan_aux_set.ull.ticks_prepare_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
-	scan_aux_set.ull.ticks_preempt_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
 	scan_aux_set.ull.ticks_slot = HAL_TICKER_US_TO_TICKS_CEIL(
 		EVENT_OVERHEAD_START_US + ready_delay_us +
 		PDU_AC_MAX_US(PDU_AC_EXT_PAYLOAD_RX_SIZE, chain->lll.phy) +
 		EVENT_OVERHEAD_END_US);
 
-	ticks_slot_offset = MAX(scan_aux_set.ull.ticks_active_to_start,
-				scan_aux_set.ull.ticks_prepare_to_start);
+	ticks_slot_offset = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 	if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
 		ticks_slot_overhead = ticks_slot_offset;
 	} else {
diff --git a/subsys/bluetooth/controller/ll_sw/ull_sched.c b/subsys/bluetooth/controller/ll_sw/ull_sched.c
index 0725d6784db..116ea101d13 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_sched.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_sched.c
@@ -127,7 +127,7 @@ int ull_sched_after_cen_slot_get(uint8_t user_id, uint32_t ticks_slot_abs,
 {
 	uint32_t ticks_to_expire;
 	uint32_t ticks_slot;
-	uint32_t remainder;
+	uint32_t remainder = 0U;
 	uint8_t ticker_id;
 
 	ticker_id = after_match_slot_get(user_id, ticks_slot_abs,
@@ -180,8 +180,7 @@ void ull_sched_mfy_after_cen_offset_get(void *param)
 
 	conn = HDR_LLL2ULL(lll->conn);
 	if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
-		ticks_slot_overhead = MAX(conn->ull.ticks_active_to_start,
-					  conn->ull.ticks_prepare_to_start);
+		ticks_slot_overhead = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 	} else {
 		ticks_slot_overhead = 0U;
 	}
@@ -204,12 +203,10 @@ void ull_sched_mfy_after_cen_offset_get(void *param)
 
 void ull_sched_mfy_win_offset_use(void *param)
 {
-	struct ll_conn *conn = param;
 	uint32_t ticks_slot_overhead;
 
 	if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
-		ticks_slot_overhead = MAX(conn->ull.ticks_active_to_start,
-					  conn->ull.ticks_prepare_to_start);
+		ticks_slot_overhead = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 	} else {
 		ticks_slot_overhead = 0U;
 	}
@@ -505,28 +502,22 @@ static uint8_t after_match_slot_get(uint8_t user_id, uint32_t ticks_slot_abs,
 			continue;
 		}
 
+#if defined(CONFIG_BT_CONN)
+		/* Consider Peripheral role ticks_slot as available */
+		if (IN_RANGE(ticker_id, TICKER_ID_CONN_BASE, TICKER_ID_CONN_LAST)) {
+			const struct ll_conn *conn;
+
+			conn = ll_conn_get(ticker_id - TICKER_ID_CONN_BASE);
+			if (conn && (conn->lll.role == BT_HCI_ROLE_PERIPHERAL)) {
+				continue;
+			}
+		}
+#endif /* CONFIG_BT_CONN */
+
 		ticks_to_expire_normal = ticks_to_expire;
 
 #if defined(CONFIG_BT_CTLR_LOW_LAT)
-#if defined(CONFIG_BT_CTLR_XTAL_ADVANCED)
-		if (hdr->ticks_prepare_to_start & XON_BITMASK) {
-			const uint32_t ticks_prepare_to_start =
-				MAX(hdr->ticks_active_to_start,
-				    hdr->ticks_preempt_to_start);
-
-			ticks_slot_abs_curr = hdr->ticks_prepare_to_start &
-					      ~XON_BITMASK;
-			ticks_to_expire_normal -= ticks_slot_abs_curr -
-						  ticks_prepare_to_start;
-		} else
-#endif /* CONFIG_BT_CTLR_XTAL_ADVANCED */
-		{
-			const uint32_t ticks_prepare_to_start =
-				MAX(hdr->ticks_active_to_start,
-				    hdr->ticks_prepare_to_start);
-
-			ticks_slot_abs_curr = ticks_prepare_to_start;
-		}
+		ticks_slot_abs_curr = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 #endif
 
 		ticks_slot_abs_curr += ticks_slot;
@@ -701,8 +692,9 @@ static struct ull_hdr *ull_hdr_get_cb(uint8_t ticker_id, uint32_t *ticks_slot)
 		struct ll_conn *conn;
 
 		conn = ll_conn_get(ticker_id - TICKER_ID_CONN_BASE);
-		if (conn && !conn->lll.role) {
-			if (IS_ENABLED(CONFIG_BT_CTLR_CENTRAL_RESERVE_MAX)) {
+		if (conn) {
+			if (IS_ENABLED(CONFIG_BT_CTLR_CENTRAL_RESERVE_MAX) &&
+			    (conn->lll.role == BT_HCI_ROLE_CENTRAL)) {
 				uint32_t ready_delay_us;
 				uint16_t max_tx_time;
 				uint16_t max_rx_time;
@@ -739,7 +731,9 @@ static struct ull_hdr *ull_hdr_get_cb(uint8_t ticker_id, uint32_t *ticks_slot)
 				*ticks_slot = conn->ull.ticks_slot;
 			}
 
-			if (*ticks_slot < HAL_TICKER_US_TO_TICKS(CONFIG_BT_CTLR_CENTRAL_SPACING)) {
+			if ((conn->lll.role == BT_HCI_ROLE_CENTRAL) &&
+			    (*ticks_slot <
+			     HAL_TICKER_US_TO_TICKS(CONFIG_BT_CTLR_CENTRAL_SPACING))) {
 				*ticks_slot =
 					HAL_TICKER_US_TO_TICKS(CONFIG_BT_CTLR_CENTRAL_SPACING);
 			}
diff --git a/subsys/bluetooth/controller/ll_sw/ull_sync.c b/subsys/bluetooth/controller/ll_sw/ull_sync.c
index 9094366716f..403f5075d6e 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_sync.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_sync.c
@@ -394,16 +394,9 @@ void ull_sync_setup_from_sync_transfer(struct ll_conn *conn, uint16_t service_da
 		slot_us += EVENT_OVERHEAD_START_US + EVENT_OVERHEAD_END_US;
 	}
 
-	/* TODO: active_to_start feature port */
-	sync->ull.ticks_active_to_start = 0U;
-	sync->ull.ticks_prepare_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
-	sync->ull.ticks_preempt_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
 	sync->ull.ticks_slot = HAL_TICKER_US_TO_TICKS_CEIL(slot_us);
 
-	ticks_slot_offset = MAX(sync->ull.ticks_active_to_start,
-				sync->ull.ticks_prepare_to_start);
+	ticks_slot_offset = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 	if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
 		ticks_slot_overhead = ticks_slot_offset;
 	} else {
@@ -1138,16 +1131,9 @@ void ull_sync_setup(struct ll_scan_set *scan, uint8_t phy,
 		slot_us += EVENT_OVERHEAD_START_US + EVENT_OVERHEAD_END_US;
 	}
 
-	/* TODO: active_to_start feature port */
-	sync->ull.ticks_active_to_start = 0U;
-	sync->ull.ticks_prepare_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
-	sync->ull.ticks_preempt_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
 	sync->ull.ticks_slot = HAL_TICKER_US_TO_TICKS_CEIL(slot_us);
 
-	ticks_slot_offset = MAX(sync->ull.ticks_active_to_start,
-				sync->ull.ticks_prepare_to_start);
+	ticks_slot_offset = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 	if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
 		ticks_slot_overhead = ticks_slot_offset;
 	} else {
diff --git a/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c b/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c
index f9aa64863cf..816bd18fcc2 100644
--- a/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c
+++ b/subsys/bluetooth/controller/ll_sw/ull_sync_iso.c
@@ -147,7 +147,8 @@ uint8_t ll_big_sync_create(uint8_t big_handle, uint16_t sync_handle,
 	}
 
 	/* Check if free BISes available */
-	if (mem_free_count_get(stream_free) < num_bis) {
+	if ((num_bis > BT_CTLR_SYNC_ISO_STREAM_MAX) ||
+	    (mem_free_count_get(stream_free) < num_bis)) {
 		return BT_HCI_ERR_INSUFFICIENT_RESOURCES;
 	}
 
@@ -580,10 +581,15 @@ void ull_sync_iso_setup(struct ll_sync_iso_set *sync_iso,
 	sync_iso_offset_us += PDU_BIG_INFO_OFFS_GET(bi) *
 			      lll->window_size_event_us;
 	/* Skip to first selected BIS subevent */
-	/* FIXME: add support for interleaved packing */
 	stream = ull_sync_iso_stream_get(lll->stream_handle[0]);
-	sync_iso_offset_us += (stream->bis_index - 1U) * lll->sub_interval *
-			      ((lll->irc * lll->bn) + lll->ptc);
+	if (lll->bis_spacing >= (lll->sub_interval * lll->nse)) {
+		sync_iso_offset_us += (stream->bis_index - 1U) *
+				      lll->sub_interval *
+				      ((lll->irc * lll->bn) + lll->ptc);
+	} else {
+		sync_iso_offset_us += (stream->bis_index - 1U) *
+				      lll->bis_spacing;
+	}
 	sync_iso_offset_us -= PDU_AC_US(pdu->len, sync_iso->sync->lll.phy,
 					ftr->phy_flags);
 	sync_iso_offset_us -= EVENT_TICKER_RES_MARGIN_US;
@@ -651,16 +657,9 @@ void ull_sync_iso_setup(struct ll_sync_iso_set *sync_iso,
 		slot_us += EVENT_OVERHEAD_START_US + EVENT_OVERHEAD_END_US;
 	}
 
-	/* TODO: active_to_start feature port */
-	sync_iso->ull.ticks_active_to_start = 0U;
-	sync_iso->ull.ticks_prepare_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
-	sync_iso->ull.ticks_preempt_to_start =
-		HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_PREEMPT_MIN_US);
 	sync_iso->ull.ticks_slot = HAL_TICKER_US_TO_TICKS_CEIL(slot_us);
 
-	ticks_slot_offset = MAX(sync_iso->ull.ticks_active_to_start,
-				sync_iso->ull.ticks_prepare_to_start);
+	ticks_slot_offset = HAL_TICKER_US_TO_TICKS(EVENT_OVERHEAD_XTAL_US);
 	if (IS_ENABLED(CONFIG_BT_CTLR_LOW_LAT)) {
 		ticks_slot_overhead = ticks_slot_offset;
 	} else {
diff --git a/subsys/bluetooth/controller/ticker/ticker.c b/subsys/bluetooth/controller/ticker/ticker.c
index 7806956c630..4c8ef7fa4b4 100644
--- a/subsys/bluetooth/controller/ticker/ticker.c
+++ b/subsys/bluetooth/controller/ticker/ticker.c
@@ -121,7 +121,9 @@ struct ticker_node {
 
 struct ticker_expire_info_internal {
 	uint32_t ticks_to_expire;
+#if defined(CONFIG_BT_TICKER_REMAINDER_SUPPORT)
 	uint32_t remainder;
+#endif /* CONFIG_BT_TICKER_REMAINDER_SUPPORT */
 	uint16_t lazy;
 	uint8_t ticker_id;
 	uint8_t outdated:1;
@@ -361,8 +363,9 @@ static struct ticker_instance _instance[TICKER_INSTANCE_MAX];
 /*****************************************************************************
  * Static Functions
  ****************************************************************************/
-
+#if defined(CONFIG_BT_TICKER_REMAINDER_SUPPORT)
 static inline uint8_t ticker_add_to_remainder(uint32_t *remainder, uint32_t to_add);
+#endif /* CONFIG_BT_TICKER_REMAINDER_SUPPORT */
 
 /**
  * @brief Update elapsed index
@@ -1101,7 +1104,9 @@ static void ticker_get_expire_info(struct ticker_instance *instance, uint8_t to_
 		}
 
 		expire_info->ticks_to_expire = to_ticks - from_ticks;
+#if defined(CONFIG_BT_TICKER_REMAINDER_SUPPORT)
 		expire_info->remainder = to_remainder;
+#endif /* CONFIG_BT_TICKER_REMAINDER_SUPPORT */
 		expire_info->lazy = to_ticker->lazy_current;
 		expire_info->found = 1;
 	} else {
@@ -1576,6 +1581,7 @@ static void ticks_to_expire_prep(struct ticker_node *ticker,
 	ticker->ticks_to_expire_minus = ticks_to_expire_minus;
 }
 
+#if defined(CONFIG_BT_TICKER_REMAINDER_SUPPORT)
 /**
  * @brief Add to remainder
  *
@@ -1605,7 +1611,6 @@ static inline uint8_t ticker_add_to_remainder(uint32_t *remainder, uint32_t to_a
 	return 0;
 }
 
-#if defined(CONFIG_BT_TICKER_REMAINDER_SUPPORT)
 /**
  * @brief Increment remainder
  *
@@ -2245,7 +2250,9 @@ static inline void ticker_job_worker_bh(struct ticker_instance *instance,
 			count = 1 + ticker->lazy_periodic;
 			while (count--) {
 				ticks_to_expire += ticker->ticks_periodic;
+#if defined(CONFIG_BT_TICKER_REMAINDER_SUPPORT)
 				ticks_to_expire += ticker_remainder_inc(ticker);
+#endif /* CONFIG_BT_TICKER_REMAINDER_SUPPORT */
 			}
 
 			/* Skip intervals that have elapsed w.r.t. current
@@ -2256,7 +2263,9 @@ static inline void ticker_job_worker_bh(struct ticker_instance *instance,
 			/* Schedule to a tick in the future */
 			while (ticks_to_expire < ticks_latency) {
 				ticks_to_expire += ticker->ticks_periodic;
+#if defined(CONFIG_BT_TICKER_REMAINDER_SUPPORT)
 				ticks_to_expire += ticker_remainder_inc(ticker);
+#endif /* CONFIG_BT_TICKER_REMAINDER_SUPPORT */
 				lazy++;
 			}
 
@@ -2792,8 +2801,10 @@ static inline uint8_t ticker_job_insert(struct ticker_instance *instance,
 
 		/* occupied, try next interval */
 		if (ticker->ticks_periodic != 0U) {
-			ticker->ticks_to_expire += ticker->ticks_periodic +
-						   ticker_remainder_inc(ticker);
+			ticker->ticks_to_expire += ticker->ticks_periodic;
+#if defined(CONFIG_BT_TICKER_REMAINDER_SUPPORT)
+			ticker->ticks_to_expire += ticker_remainder_inc(ticker);
+#endif /* CONFIG_BT_TICKER_REMAINDER_SUPPORT */
 			ticker->lazy_current++;
 
 			/* No. of times ticker has skipped its interval */
diff --git a/subsys/bluetooth/controller/ticker/ticker.h b/subsys/bluetooth/controller/ticker/ticker.h
index aa666036ab0..c2dc59318be 100644
--- a/subsys/bluetooth/controller/ticker/ticker.h
+++ b/subsys/bluetooth/controller/ticker/ticker.h
@@ -136,7 +136,9 @@ typedef void (*ticker_timeout_func) (uint32_t ticks_at_expire,
 
 struct ticker_expire_info {
 	uint32_t ticks_to_expire;
+#if defined(CONFIG_BT_TICKER_REMAINDER_SUPPORT)
 	uint32_t remainder;
+#endif /* CONFIG_BT_TICKER_REMAINDER_SUPPORT */
 	uint16_t lazy;
 };
 
diff --git a/subsys/bluetooth/host/Kconfig b/subsys/bluetooth/host/Kconfig
index d49ea5c8fde..e77bd9220a2 100644
--- a/subsys/bluetooth/host/Kconfig
+++ b/subsys/bluetooth/host/Kconfig
@@ -15,12 +15,13 @@ config BT_LONG_WQ_STACK_SIZE
 	# Hidden: Long workqueue stack size. Should be derived from system
 	# requirements.
 	int
+	default 4096 if NO_OPTIMIZATIONS
 	default 1400 if BT_ECC
 	default 1300 if BT_GATT_CACHING
 	default 1024
 
 config BT_LONG_WQ_PRIO
-	int "Long workqueue priority. Should be pre-emptible."
+	int "Long workqueue priority. Should be preemptible."
 	default 10
 	range 0 NUM_PREEMPT_PRIORITIES
 
@@ -978,7 +979,7 @@ config BT_DF_VS_CL_IQ_REPORT_16_BITS_IQ_SAMPLES
 	bool "Use 16 bits signed integer IQ samples in connectionless IQ reports"
 	depends on BT_DF_CONNECTIONLESS_CTE_RX && BT_HCI_VS
 	help
-	  Direction Finging connectionless IQ reports provide a set of IQ samples collected during
+	  Direction Finding connectionless IQ reports provide a set of IQ samples collected during
 	  sampling of CTE. Bluetooth 5.3 Core Specification defines IQ samples to be 8 bits signed
 	  integer, see Vol 4, Part E section 7.7.65.21. This option enables a vendor specific Host
 	  extension to handle connectionless IQ reports with samples that are in 16 bit signed
@@ -988,7 +989,7 @@ config BT_DF_VS_CONN_IQ_REPORT_16_BITS_IQ_SAMPLES
 	bool "Use 16 bits signed integer IQ samples in connection IQ reports"
 	depends on BT_DF_CONNECTION_CTE_RX && BT_HCI_VS
 	help
-	  Direction Finging connection IQ reports provide a set of IQ samples collected during
+	  Direction Finding connection IQ reports provide a set of IQ samples collected during
 	  sampling of CTE. Bluetooth 5.3 Core Specification defines IQ samples to be 8 bits signed
 	  integer, see Vol 4, Part E sections 7.7.65.22. This option enables a vendor specific Host
 	  extension to handle connection IQ report with samples that are in 16 bit signed integer
diff --git a/subsys/bluetooth/host/Kconfig.gatt b/subsys/bluetooth/host/Kconfig.gatt
index 9acfae58c95..221bc413c4b 100644
--- a/subsys/bluetooth/host/Kconfig.gatt
+++ b/subsys/bluetooth/host/Kconfig.gatt
@@ -289,7 +289,7 @@ choice BT_DEVICE_NAME_GATT_WRITABLE_SECURITY
 	prompt "Security requirements"
 	default DEVICE_NAME_GATT_WRITABLE_ENCRYPT
 	help
-	  Select security requirementsf for writing device name by remote GATT
+	  Select security requirements for writing device name by remote GATT
 	  clients.
 
 config DEVICE_NAME_GATT_WRITABLE_NONE
@@ -317,7 +317,7 @@ choice BT_DEVICE_APPEARANCE_GATT_WRITABLE
 	prompt "Security requirements"
 	default DEVICE_APPEARANCE_GATT_WRITABLE_AUTHEN
 	help
-	  Select security requirementsf for writing device name by remote GATT
+	  Select security requirements for writing device name by remote GATT
 	  clients.
 
 config BT_DEVICE_APPEARANCE_GATT_WRITABLE_NONE
diff --git a/subsys/bluetooth/host/addr.c b/subsys/bluetooth/host/addr.c
index 24e0303efbe..bc6d9848081 100644
--- a/subsys/bluetooth/host/addr.c
+++ b/subsys/bluetooth/host/addr.c
@@ -5,14 +5,13 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <errno.h>
 #include <stdbool.h>
 #include <string.h>
-#include <errno.h>
-
-#include <zephyr/sys/util.h>
 
 #include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/crypto.h>
+#include <zephyr/sys/util.h>
 
 #define ADDR_RESOLVED_BITMASK (0x02)
 
diff --git a/subsys/bluetooth/host/adv.c b/subsys/bluetooth/host/adv.c
index d2e0c255e12..0694c2ce54b 100644
--- a/subsys/bluetooth/host/adv.c
+++ b/subsys/bluetooth/host/adv.c
@@ -4,25 +4,38 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#include <sys/types.h>
-
-#include <zephyr/sys/byteorder.h>
+#include <errno.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
 
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/bluetooth.h>
-#include <zephyr/bluetooth/hci.h>
 #include <zephyr/bluetooth/buf.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/byteorder.h>
 #include <zephyr/sys/check.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <sys/types.h>
 
 #include "addr_internal.h"
-#include "hci_core.h"
+#include "common/bt_str.h"
 #include "conn_internal.h"
+#include "hci_core.h"
 #include "id.h"
 #include "scan.h"
 
-#include "common/bt_str.h"
-
 #define LOG_LEVEL CONFIG_BT_HCI_CORE_LOG_LEVEL
-#include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(bt_adv);
 
 enum adv_name_type {
diff --git a/subsys/bluetooth/host/adv.h b/subsys/bluetooth/host/adv.h
index 3a03bfe8f4c..65ad51135ce 100644
--- a/subsys/bluetooth/host/adv.h
+++ b/subsys/bluetooth/host/adv.h
@@ -5,6 +5,10 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stdbool.h>
+
+#include <zephyr/bluetooth/bluetooth.h>
+
 void bt_le_adv_resume(void);
 
 struct bt_le_ext_adv *bt_le_adv_lookup_legacy(void);
diff --git a/subsys/bluetooth/host/aes_ccm.c b/subsys/bluetooth/host/aes_ccm.c
index 2e0022cf4eb..8f3f5dc680f 100644
--- a/subsys/bluetooth/host/aes_ccm.c
+++ b/subsys/bluetooth/host/aes_ccm.c
@@ -5,16 +5,19 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <errno.h>
+#include <stdint.h>
 #include <string.h>
 
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/crypto.h>
 #include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
 #include <zephyr/sys/byteorder.h>
-#include <zephyr/bluetooth/crypto.h>
 
 #include "common/bt_str.h"
 
 #define LOG_LEVEL CONFIG_BT_HCI_CORE_LOG_LEVEL
-#include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(bt_aes_ccm);
 
 static inline void xor16(uint8_t *dst, const uint8_t *a, const uint8_t *b)
diff --git a/subsys/bluetooth/host/att.c b/subsys/bluetooth/host/att.c
index 8ba9957d3a3..335032918fe 100644
--- a/subsys/bluetooth/host/att.c
+++ b/subsys/bluetooth/host/att.c
@@ -5,32 +5,44 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-
-#include <zephyr/kernel.h>
-#include <string.h>
 #include <errno.h>
 #include <stdbool.h>
-#include <zephyr/sys/atomic.h>
-#include <zephyr/sys/byteorder.h>
-#include <zephyr/sys/util.h>
+#include <stdint.h>
+#include <string.h>
 
-#include <zephyr/bluetooth/hci.h>
-#include <zephyr/bluetooth/bluetooth.h>
-#include <zephyr/bluetooth/uuid.h>
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/att.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gatt.h>
+#include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/bluetooth/l2cap.h>
+#include <zephyr/bluetooth/uuid.h>
+#include <zephyr/kernel.h>
+#include <zephyr/kernel/thread.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/toolchain.h>
+#include <sys/types.h>
 
+#include "att_internal.h"
 #include "common/bt_str.h"
-
-#include "hci_core.h"
 #include "conn_internal.h"
+#include "gatt_internal.h"
+#include "hci_core.h"
 #include "l2cap_internal.h"
 #include "smp.h"
-#include "att_internal.h"
-#include "gatt_internal.h"
 
 #define LOG_LEVEL CONFIG_BT_ATT_LOG_LEVEL
-#include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(bt_att);
 
 #define ATT_CHAN(_ch) CONTAINER_OF(_ch, struct bt_att_chan, chan.chan)
@@ -133,7 +145,7 @@ static uint16_t bt_att_mtu(struct bt_att_chan *chan)
 /* Descriptor of application-specific authorization callbacks that are used
  * with the CONFIG_BT_GATT_AUTHORIZATION_CUSTOM Kconfig enabled.
  */
-const static struct bt_gatt_authorization_cb *authorization_cb;
+static const struct bt_gatt_authorization_cb *authorization_cb;
 
 /* ATT connection specific data */
 struct bt_att {
@@ -293,26 +305,26 @@ static void bt_att_disconnected(struct bt_l2cap_chan *chan);
 
 struct net_buf *bt_att_create_rsp_pdu(struct bt_att_chan *chan, uint8_t op);
 
-static void bt_att_sent(struct bt_l2cap_chan *ch);
-
-static void att_sent(void *user_data)
+static void att_disconnect(struct bt_att_chan *chan)
 {
-	struct bt_att_tx_meta_data *data = user_data;
-	struct bt_att_chan *att_chan = data->att_chan;
-	struct bt_conn *conn = att_chan->att->conn;
-	struct bt_l2cap_chan *chan = &att_chan->chan.chan;
+	char addr[BT_ADDR_LE_STR_LEN];
+	int err;
 
-	__ASSERT_NO_MSG(!bt_att_is_enhanced(att_chan));
+	/* In rare circumstances we are "forced" to disconnect the ATT bearer and the ACL.
+	 * Examples of when this is right course of action is when there is an ATT timeout, we
+	 * receive an unexpected response from the server, or the response from the server is
+	 * invalid
+	 */
 
-	LOG_DBG("conn %p chan %p", conn, chan);
+	bt_addr_le_to_str(bt_conn_get_dst(chan->att->conn), addr, sizeof(addr));
+	LOG_DBG("ATT disconnecting device %s", addr);
 
-	/* For EATT, `bt_att_sent` is assigned to the `.sent` L2 callback.
-	 * L2CAP will then call it once the SDU has finished sending.
-	 *
-	 * For UATT, this won't happen, as static LE l2cap channels don't have
-	 * SDUs. Call it manually instead.
-	 */
-	bt_att_sent(chan);
+	bt_att_disconnected(&chan->chan.chan);
+
+	err = bt_conn_disconnect(chan->chan.chan.conn, BT_HCI_ERR_REMOTE_USER_TERM_CONN);
+	if (err) {
+		LOG_ERR("Disconnecting failed (err %d)", err);
+	}
 }
 
 static void chan_sent_cb(struct bt_conn *conn, void *user_data, int err)
@@ -540,7 +552,7 @@ static int process_queue(struct bt_att_chan *chan, struct k_fifo *queue)
 }
 
 /* Send requests without taking tx_sem */
-static int chan_req_send(struct bt_att_chan *chan, struct bt_att_req *req)
+static int bt_att_chan_req_send(struct bt_att_chan *chan, struct bt_att_req *req)
 {
 	struct net_buf *buf;
 	int err;
@@ -597,7 +609,8 @@ static void bt_att_sent(struct bt_l2cap_chan *ch)
 	if (!chan->req && !sys_slist_is_empty(&att->reqs)) {
 		sys_snode_t *node = sys_slist_get(&att->reqs);
 
-		if (chan_req_send(chan, ATT_REQ(node)) >= 0) {
+		err = bt_att_chan_req_send(chan, ATT_REQ(node));
+		if (err == 0) {
 			return;
 		}
 
@@ -677,9 +690,20 @@ static void att_on_sent_cb(struct bt_att_tx_meta_data *meta)
 	}
 
 	if (!bt_att_is_enhanced(meta->att_chan)) {
-		/* For EATT, L2CAP will call it after the SDU is fully sent. */
-		LOG_DBG("UATT bearer, calling att_sent");
-		att_sent(meta);
+		struct bt_att_chan *att_chan = meta->att_chan;
+		struct bt_conn *conn = att_chan->att->conn;
+		struct bt_l2cap_chan *l2cap_chan = &att_chan->chan.chan;
+
+		ARG_UNUSED(conn);
+		LOG_DBG("UATT bearer, calling bt_att_sent: conn %p chan %p", conn, l2cap_chan);
+
+		/* For EATT, `bt_att_sent` is assigned to the `.sent` L2 callback.
+		 * L2CAP will then call it once the SDU has finished sending.
+		 *
+		 * For UATT, this won't happen, as static LE l2cap channels don't have
+		 * SDUs. Call it manually instead.
+		 */
+		bt_att_sent(l2cap_chan);
 	}
 
 	switch (op_type) {
@@ -894,19 +918,6 @@ static uint8_t att_mtu_req(struct bt_att_chan *chan, struct net_buf *buf)
 	return 0;
 }
 
-static int bt_att_chan_req_send(struct bt_att_chan *chan,
-				struct bt_att_req *req)
-{
-	__ASSERT_NO_MSG(chan);
-	__ASSERT_NO_MSG(req);
-	__ASSERT_NO_MSG(req->func);
-	__ASSERT_NO_MSG(!chan->req);
-
-	LOG_DBG("req %p", req);
-
-	return chan_req_send(chan, req);
-}
-
 static void att_req_send_process(struct bt_att *att)
 {
 	struct bt_att_req *req = NULL;
@@ -934,7 +945,7 @@ static void att_req_send_process(struct bt_att *att)
 			continue;
 		}
 
-		if (bt_att_chan_req_send(chan, req) >= 0) {
+		if (bt_att_chan_req_send(chan, req) == 0) {
 			return;
 		}
 
@@ -956,7 +967,8 @@ static uint8_t att_handle_rsp(struct bt_att_chan *chan, void *pdu, uint16_t len,
 
 	if (!chan->req) {
 		LOG_WRN("No pending ATT request");
-		goto process;
+		att_disconnect(chan);
+		return 0; /* Returning a non-0 value would attempt to send an error response */
 	}
 
 	/* Check if request has been cancelled */
@@ -3165,9 +3177,7 @@ static void att_timeout(struct k_work *work)
 {
 	char addr[BT_ADDR_LE_STR_LEN];
 	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
-	struct bt_att_chan *chan = CONTAINER_OF(dwork, struct bt_att_chan,
-						timeout_work);
-	int err;
+	struct bt_att_chan *chan = CONTAINER_OF(dwork, struct bt_att_chan, timeout_work);
 
 	bt_addr_le_to_str(bt_conn_get_dst(chan->att->conn), addr, sizeof(addr));
 	LOG_ERR("ATT Timeout for device %s. Disconnecting...", addr);
@@ -3180,17 +3190,13 @@ static void att_timeout(struct k_work *work)
 	 * requests, commands, indications or notifications shall be sent to the
 	 * target device on this ATT Bearer.
 	 */
-	bt_att_disconnected(&chan->chan.chan);
 
 	/* The timeout state is local and can block new ATT operations, but does not affect the
 	 * remote side. Disconnecting the GATT connection upon ATT timeout simplifies error handling
 	 * for developers. This reduces rare failure conditions to a common one, allowing developers
 	 * to handle unexpected disconnections without needing special cases for ATT timeouts.
 	 */
-	err = bt_conn_disconnect(chan->chan.chan.conn, BT_HCI_ERR_REMOTE_USER_TERM_CONN);
-	if (err) {
-		LOG_ERR("Disconnecting failed (err %d)", err);
-	}
+	att_disconnect(chan);
 }
 
 static struct bt_att_chan *att_get_fixed_chan(struct bt_conn *conn)
@@ -3366,7 +3372,7 @@ static void bt_att_status(struct bt_l2cap_chan *ch, atomic_t *status)
 		return;
 	}
 
-	if (bt_att_chan_req_send(chan, ATT_REQ(node)) >= 0) {
+	if (bt_att_chan_req_send(chan, ATT_REQ(node)) == 0) {
 		return;
 	}
 
diff --git a/subsys/bluetooth/host/att_internal.h b/subsys/bluetooth/host/att_internal.h
index 6eec4c5496e..dc397283de9 100644
--- a/subsys/bluetooth/host/att_internal.h
+++ b/subsys/bluetooth/host/att_internal.h
@@ -1,6 +1,16 @@
 /* att_internal.h - Attribute protocol handling */
 
+#include <stdint.h>
+#include <stddef.h>
+
+#include <zephyr/bluetooth/att.h>
+#include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/l2cap.h>
+#include <zephyr/kernel.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys_clock.h>
 
 /*
  * Copyright (c) 2015-2016 Intel Corporation
diff --git a/subsys/bluetooth/host/buf.c b/subsys/bluetooth/host/buf.c
index 75bd15834ae..a4f75bd5248 100644
--- a/subsys/bluetooth/host/buf.c
+++ b/subsys/bluetooth/host/buf.c
@@ -5,17 +5,28 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/hci.h>
 #include <zephyr/bluetooth/buf.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/l2cap.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/sys_clock.h>
 
 #include "buf_view.h"
-#include "hci_core.h"
+#include "common/hci_common_internal.h"
 #include "conn_internal.h"
+#include "hci_core.h"
 #include "iso_internal.h"
 
-#include <zephyr/bluetooth/hci.h>
-
-#include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(bt_buf, CONFIG_BT_LOG_LEVEL);
 
 /* Events have a length field of 1 byte. This size fits all events.
@@ -72,8 +83,9 @@ static void evt_pool_destroy(struct net_buf *buf)
 	buf_rx_freed_notify(BT_BUF_EVT);
 }
 
-NET_BUF_POOL_DEFINE(acl_in_pool, BT_BUF_ACL_RX_COUNT, BT_BUF_ACL_SIZE(CONFIG_BT_BUF_ACL_RX_SIZE),
-		    sizeof(struct acl_data), acl_in_pool_destroy);
+NET_BUF_POOL_DEFINE(acl_in_pool, (BT_BUF_ACL_RX_COUNT_EXTRA + BT_BUF_HCI_ACL_RX_COUNT),
+		    BT_BUF_ACL_SIZE(CONFIG_BT_BUF_ACL_RX_SIZE), sizeof(struct acl_data),
+		    acl_in_pool_destroy);
 
 NET_BUF_POOL_FIXED_DEFINE(evt_pool, CONFIG_BT_BUF_EVT_RX_COUNT, BT_BUF_EVT_RX_SIZE,
 			  sizeof(struct bt_buf_data), evt_pool_destroy);
diff --git a/subsys/bluetooth/host/buf_view.h b/subsys/bluetooth/host/buf_view.h
index 1b9a78ec7b4..378d0c4be5c 100644
--- a/subsys/bluetooth/host/buf_view.h
+++ b/subsys/bluetooth/host/buf_view.h
@@ -11,6 +11,8 @@
 #ifndef ZEPHYR_SUBSYS_BLUETOOTH_HOST_BUF_VIEW_H_
 #define ZEPHYR_SUBSYS_BLUETOOTH_HOST_BUF_VIEW_H_
 
+#include <stddef.h>
+
 #include <zephyr/net_buf.h>
 
 
diff --git a/subsys/bluetooth/host/classic/CMakeLists.txt b/subsys/bluetooth/host/classic/CMakeLists.txt
index 0f7f01d5c00..ab15843b0a9 100644
--- a/subsys/bluetooth/host/classic/CMakeLists.txt
+++ b/subsys/bluetooth/host/classic/CMakeLists.txt
@@ -14,6 +14,7 @@ zephyr_library_sources_ifdef(CONFIG_BT_RFCOMM           rfcomm.c)
 zephyr_library_sources_ifdef(
   CONFIG_BT_CLASSIC
   br.c
+  conn_br.c
   keys_br.c
   l2cap_br.c
   sdp.c
diff --git a/subsys/bluetooth/host/classic/Kconfig b/subsys/bluetooth/host/classic/Kconfig
index a967cfa65ae..1fbf45f9099 100644
--- a/subsys/bluetooth/host/classic/Kconfig
+++ b/subsys/bluetooth/host/classic/Kconfig
@@ -13,11 +13,20 @@ config BT_CLASSIC
 	select BT_CENTRAL
 	select BT_SMP
 	select BT_L2CAP_DYNAMIC_CHANNEL
+	select CRC
 	select EXPERIMENTAL
 	help
 	  This option enables Bluetooth BR/EDR support
 
 if BT_CLASSIC
+config BT_LIMITED_DISCOVERABLE_DURATION
+	int "Maximum duration that a device is in limited discoverable mode in seconds"
+	default 60
+	range 31 60
+	help
+	  This option sets the maximum duration that a device is in limited discoverable mode in
+	  seconds.
+
 config BT_BR_MIN_ENC_KEY_SIZE
 	int
 	prompt "Minimum encryption key size accepted in octets" if !BT_SMP_SC_ONLY
@@ -35,6 +44,85 @@ config BT_MAX_SCO_CONN
 	  Maximum number of simultaneous Bluetooth synchronous connections
 	  supported. The minimum (and default) number is 1.
 
+config BT_L2CAP_RET
+	bool "Bluetooth L2CAP retransmission mode [EXPERIMENTAL]"
+	select EXPERIMENTAL
+	help
+	  This option enables Bluetooth L2CAP retransmission mode
+
+config BT_L2CAP_FC
+	bool "Bluetooth L2CAP flow control mode [EXPERIMENTAL]"
+	select EXPERIMENTAL
+	help
+	  This option enables Bluetooth L2CAP flow control mode
+
+config BT_L2CAP_ENH_RET
+	bool "Bluetooth L2CAP enhance retransmission [EXPERIMENTAL]"
+	select EXPERIMENTAL
+	help
+	  This option enables Bluetooth L2CAP enhance retransmission
+
+config BT_L2CAP_STREAM
+	bool "Bluetooth L2CAP streaming mode [EXPERIMENTAL]"
+	select EXPERIMENTAL
+	help
+	  This option enables Bluetooth L2CAP streaming mode
+
+config BT_L2CAP_RET_FC
+	def_bool BT_L2CAP_RET || BT_L2CAP_FC || BT_L2CAP_ENH_RET || BT_L2CAP_STREAM
+
+if BT_L2CAP_RET_FC
+config BT_L2CAP_FCS
+	bool "Bluetooth L2CAP FCS Option [EXPERIMENTAL]"
+	select EXPERIMENTAL
+	depends on BT_L2CAP_STREAM || BT_L2CAP_ENH_RET
+	help
+	  This option enables Bluetooth L2CAP FCS Option
+
+config BT_L2CAP_EXT_WIN_SIZE
+	bool "Bluetooth L2CAP Extended window size Option [EXPERIMENTAL]"
+	select EXPERIMENTAL
+	depends on BT_L2CAP_STREAM || BT_L2CAP_ENH_RET
+	help
+	  This option enables Bluetooth L2CAP Extended window size Option
+
+config BT_L2CAP_MPS
+	int "Bluetooth L2CAP MPS for retransmission and Flow control"
+	default 48
+	range 48 BT_L2CAP_TX_MTU
+	help
+	  Bluetooth L2CAP MPS for retransmission and Flow control
+
+config BT_L2CAP_MAX_WINDOW_SIZE
+	int "Maximum Windows Size of Retransmission and Flow Control"
+	default 1
+	range 1 32
+	help
+	  Maximum Windows Size of Retransmission and Flow Control.
+	  The minimum (and default) number is 1.
+
+config BT_L2CAP_BR_RET_TIMEOUT
+	int "Retransmission timeout (milliseconds)"
+	default 2000
+	range 1000 2000
+	help
+	  The Retransmission timeout shall be three times the value of flush timeout,
+	  subject to a minimum of 1000 milliseconds and maximum of 2000 milliseconds.
+
+config BT_L2CAP_BR_MONITOR_TIMEOUT
+	int "Monitor timeout (milliseconds)"
+	default 12000 if BT_L2CAP_ENH_RET
+	default BT_L2CAP_BR_RET_TIMEOUT
+	range BT_L2CAP_BR_RET_TIMEOUT 12000
+	help
+	  If a flush timeout exists on the link for Enhanced Retransmission mode and
+	  both sides of the link are configured to the same flush timeout value then the
+	  monitor timeout shall be set to a value at least as large as the Retransmission
+	  timeout otherwise the value of the Monitor timeout shall be six times the value
+	  of flush timeout, subject to a minimum of the retransmission timeout value and
+	  a maximum of 12000 milliseconds.
+endif # BT_L2CAP_RET_FC
+
 config BT_RFCOMM
 	bool "Bluetooth RFCOMM protocol support [EXPERIMENTAL]"
 	select EXPERIMENTAL
@@ -86,7 +174,144 @@ config BT_HFP_AG
 	help
 	  This option enables Bluetooth AG support
 
+if BT_HFP_HF
+config BT_HFP_HF_CLI
+	bool "CLI presentation capability for HFP HF [EXPERIMENTAL]"
+	default y
+	help
+	  This option enables CLI presentation capability for HFP HF
+
+config BT_HFP_HF_VOLUME
+	bool "Remote audio volume control for HFP HF [EXPERIMENTAL]"
+	default y
+	help
+	  This option enables Remote audio volume control for HFP HF
+
+config BT_HFP_HF_CODEC_NEG
+	bool "Codec Negotiation for HFP HF [EXPERIMENTAL]"
+	help
+	  This option enables Codec Negotiation for HFP HF
+
+config BT_HFP_HF_ECNR
+	bool "EC and/or NR function for HFP HF [EXPERIMENTAL]"
+	help
+	  This option enables EC and/or NR function for HFP HF
+
+if BT_HFP_HF_CODEC_NEG
+config BT_HFP_HF_CODEC_MSBC
+	bool "Support Codec mSBC for HFP HF [EXPERIMENTAL]"
+	help
+	  This option enables Codec mSBC for HFP HF
+
+config BT_HFP_HF_CODEC_LC3_SWB
+	bool "Support Codec LC3 SWB for HFP HF [EXPERIMENTAL]"
+	help
+	  This option enables Codec LC3 SWB for HFP HF
+endif # BT_HFP_HF_CODEC_NEG
+
+config BT_HFP_HF_3WAY_CALL
+	bool "Three-way calling for HFP HF [EXPERIMENTAL]"
+	help
+	  This option enables Three-way calling for HFP HF
+
+config BT_HFP_HF_ECS
+	bool "Enhanced Call Status for HFP HF [EXPERIMENTAL]"
+	default y if BT_HFP_HF_3WAY_CALL
+	help
+	  This option enables Enhanced Call Status for HFP HF
+
+config BT_HFP_HF_ECC
+	bool "Enhanced Call Control for HFP HF [EXPERIMENTAL]"
+	default y if BT_HFP_HF_3WAY_CALL
+	help
+	  This option enables Enhanced Call Control for HFP HF
+
+config BT_HFP_HF_MAX_CALLS
+	int "Maximum supported calls for HFP HF [EXPERIMENTAL]"
+	default 2 if BT_HFP_HF_3WAY_CALL
+	default 1
+	range 1 2
+	help
+	  This option sets maximum supported calls for HFP HF
+
+config BT_HFP_HF_VOICE_RECG
+	bool "Voice recognition activation for HFP HF [EXPERIMENTAL]"
+	help
+	  This option enables Voice recognition activation for HFP HF
+
+config BT_HFP_HF_ENH_VOICE_RECG
+	bool "Enhanced Voice Recognition Status for HFP HF [EXPERIMENTAL]"
+	select BT_HFP_HF_VOICE_RECG
+	help
+	  This option enables Enhanced Voice Recognition Status for HFP HF
+
+config BT_HFP_HF_VOICE_RECG_TEXT
+	bool "Voice Recognition Text for HFP HF [EXPERIMENTAL]"
+	select BT_HFP_HF_ENH_VOICE_RECG
+	help
+	  This option enables Voice Recognition Text for HFP HF
+
+config BT_HFP_HF_HF_INDICATORS
+	bool "HF Indicators for HFP HF [EXPERIMENTAL]"
+	help
+	  This option enables HF Indicators for HFP HF
+
+config BT_HFP_HF_HF_INDICATOR_ENH_SAFETY
+	bool "HF Indicator Enhanced Safety for HFP HF [EXPERIMENTAL]"
+	select BT_HFP_HF_HF_INDICATORS
+	help
+	  This option enables HF Indicator Enhanced Safety for HFP HF
+
+config BT_HFP_HF_HF_INDICATOR_BATTERY
+	bool "HF Indicator Battery level for HFP HF [EXPERIMENTAL]"
+	select BT_HFP_HF_HF_INDICATORS
+	help
+	  This option enables HF Indicator Battery level for HFP HF
+
+endif # BT_HFP_HF
+
 if BT_HFP_AG
+config BT_HFP_AG_EXT_ERR
+	bool "Extended Error Result Codes for HFP AG [EXPERIMENTAL]"
+	default y
+	help
+	  This option enables Extended Error Result Codes for HFP AG
+
+config BT_HFP_AG_CODEC_NEG
+	bool "Codec Negotiation for HFP AG [EXPERIMENTAL]"
+	help
+	  This option enables Codec Negotiation for HFP AG
+
+config BT_HFP_AG_ECNR
+	bool "EC and/or NR function for HFP AG [EXPERIMENTAL]"
+	help
+	  This option enables EC and/or NR function for HFP AG
+
+config BT_HFP_AG_3WAY_CALL
+	bool "Three-way calling for HFP AG [EXPERIMENTAL]"
+	help
+	  This option enables Three-way calling for HFP AG
+
+config BT_HFP_AG_MAX_CALLS
+	int "Maximum supported calls for HFP AG [EXPERIMENTAL]"
+	default 2 if BT_HFP_AG_3WAY_CALL
+	default 1
+	range 1 2
+	help
+	  This option sets maximum supported calls for HFP AG
+
+config BT_HFP_AG_ECS
+	bool "Enhanced call status for HFP AG [EXPERIMENTAL]"
+	default y if BT_HFP_AG_3WAY_CALL
+	help
+	  This option enables Enhanced call status for HFP AG
+
+config BT_HFP_AG_ECC
+	bool "Enhanced call control for HFP AG [EXPERIMENTAL]"
+	default y if BT_HFP_AG_3WAY_CALL
+	help
+	  This option enables Enhanced call control for HFP AG
+
 config BT_HFP_AG_TX_BUF_COUNT
 	int "Maximum number of TX buffers for HFP AG [EXPERIMENTAL]"
 	default BT_RFCOMM_TX_MAX
@@ -147,6 +372,53 @@ config BT_HFP_AG_RING_NOTIFY_INTERVAL
 	help
 	  Ring notification interval if the call is in alert state.
 	  The unit is seconds.
+
+config BT_HFP_AG_VOICE_RECG
+	bool "Voice recognition activation for HFP AG [EXPERIMENTAL]"
+	help
+	  This option enables Voice recognition activation for HFP AG
+
+config BT_HFP_AG_ENH_VOICE_RECG
+	bool "Enhanced Voice Recognition Status for HFP AG [EXPERIMENTAL]"
+	select BT_HFP_AG_VOICE_RECG
+	help
+	  This option enables Enhanced Voice Recognition Status for HFP AG
+
+config BT_HFP_AG_VOICE_RECG_TEXT
+	bool "Voice Recognition Text for HFP AG [EXPERIMENTAL]"
+	select BT_HFP_AG_ENH_VOICE_RECG
+	help
+	  This option enables Voice Recognition Text for HFP AG
+
+config BT_HFP_AG_VOICE_TAG
+	bool "Attach a phone number for a voice tag for HFP AG [EXPERIMENTAL]"
+	select BT_HFP_AG_VOICE_RECG
+	help
+	  This option enables Attach a phone number for a voice tag for HFP AG
+
+config BT_HFP_AG_HF_INDICATORS
+	bool "HF Indicators for HFP AG [EXPERIMENTAL]"
+	help
+	  This option enables HF Indicators for HFP AG
+
+config BT_HFP_AG_HF_INDICATOR_ENH_SAFETY
+	bool "HF Indicator Enhanced Safety for HFP AG [EXPERIMENTAL]"
+	select BT_HFP_AG_HF_INDICATORS
+	help
+	  This option enables HF Indicator Enhanced Safety for HFP AG
+
+config BT_HFP_AG_HF_INDICATOR_BATTERY
+	bool "HF Indicator Battery level for HFP AG [EXPERIMENTAL]"
+	select BT_HFP_AG_HF_INDICATORS
+	help
+	  This option enables HF Indicator Battery level for HFP AG
+
+config BT_HFP_AG_REJECT_CALL
+	bool "Ability to reject a call for HFP AG [EXPERIMENTAL]"
+	default y
+	help
+	  This option enables ability to reject a call for HFP AG
+
 endif # BT_HFP_AG
 
 config BT_AVDTP
diff --git a/subsys/bluetooth/host/classic/a2dp.c b/subsys/bluetooth/host/classic/a2dp.c
index 4fdbbb8b766..504aba7d280 100644
--- a/subsys/bluetooth/host/classic/a2dp.c
+++ b/subsys/bluetooth/host/classic/a2dp.c
@@ -83,6 +83,7 @@ static struct bt_a2dp *a2dp_get_connection(struct bt_conn *conn)
 		/* Clean the memory area before returning */
 		(void)memset(a2dp, 0, sizeof(struct bt_a2dp));
 	}
+
 	return a2dp;
 }
 
@@ -92,6 +93,7 @@ static void a2dp_connected(struct bt_avdtp *session)
 	struct bt_a2dp *a2dp = A2DP_AVDTP(session);
 
 	a2dp->a2dp_state = INTERNAL_STATE_AVDTP_CONNECTED;
+
 	/* notify a2dp app the connection. */
 	if ((a2dp_cb != NULL) && (a2dp_cb->connected != NULL)) {
 		a2dp_cb->connected(a2dp, 0);
@@ -276,12 +278,12 @@ static void bt_a2dp_media_data_callback(struct bt_avdtp_sep *sep, struct net_buf
 	if (ep->stream == NULL || buf->len < sizeof(*media_hdr)) {
 		return;
 	}
-	stream = ep->stream;
 
+	stream = ep->stream;
 	media_hdr = net_buf_pull_mem(buf, sizeof(*media_hdr));
 
-	stream->ops->recv(stream, buf, sys_get_be16((uint8_t *)&media_hdr->sequence_number),
-			  sys_get_be32((uint8_t *)&media_hdr->time_stamp));
+	stream->ops->recv(stream, buf, sys_be16_to_cpu(media_hdr->sequence_number),
+			  sys_be32_to_cpu(media_hdr->time_stamp));
 }
 #endif
 
@@ -301,6 +303,7 @@ static int a2dp_ctrl_ind(struct bt_avdtp *session, struct bt_avdtp_sep *sep, uin
 		*errcode = BT_AVDTP_BAD_ACP_SEID;
 		return -EINVAL;
 	}
+
 	stream = ep->stream;
 
 	if (req_cb != NULL) {
@@ -389,7 +392,7 @@ static int a2dp_abort_ind(struct bt_avdtp *session, struct bt_avdtp_sep *sep, ui
 	return a2dp_ctrl_ind(session, sep, errcode, req_cb, done_cb, true);
 }
 
-static int bt_a2dp_set_config_cb(struct bt_avdtp_req *req)
+static int bt_a2dp_set_config_cb(struct bt_avdtp_req *req, struct net_buf *buf)
 {
 	struct bt_a2dp *a2dp = SET_CONF_PARAM(SET_CONF_REQ(req));
 	struct bt_a2dp_ep *ep;
@@ -400,11 +403,12 @@ static int bt_a2dp_set_config_cb(struct bt_avdtp_req *req)
 	if (ep->stream == NULL) {
 		return -EINVAL;
 	}
+
 	if ((ep->stream == NULL) || (SET_CONF_REQ(req) != &a2dp->set_config_param)) {
 		return -EINVAL;
 	}
-	stream = ep->stream;
 
+	stream = ep->stream;
 	LOG_DBG("SET CONFIGURATION result:%d", req->status);
 
 	if ((a2dp_cb != NULL) && (a2dp_cb->config_rsp != NULL)) {
@@ -418,7 +422,7 @@ static int bt_a2dp_set_config_cb(struct bt_avdtp_req *req)
 	return 0;
 }
 
-static int bt_a2dp_get_capabilities_cb(struct bt_avdtp_req *req)
+static int bt_a2dp_get_capabilities_cb(struct bt_avdtp_req *req, struct net_buf *buf)
 {
 	int err;
 	uint8_t *codec_info_element;
@@ -427,7 +431,7 @@ static int bt_a2dp_get_capabilities_cb(struct bt_avdtp_req *req)
 	uint8_t codec_type;
 	uint8_t user_ret;
 
-	if (GET_CAP_REQ(req) != &a2dp->get_capabilities_param) {
+	if (GET_CAP_REQ(req) != &a2dp->get_capabilities_param || buf == NULL) {
 		return -EINVAL;
 	}
 
@@ -440,7 +444,7 @@ static int bt_a2dp_get_capabilities_cb(struct bt_avdtp_req *req)
 		return 0;
 	}
 
-	err = bt_avdtp_parse_capability_codec(a2dp->get_capabilities_param.buf, &codec_type,
+	err = bt_avdtp_parse_capability_codec(buf, &codec_type,
 					      &codec_info_element, &codec_info_element_len);
 	if (err) {
 		LOG_DBG("codec capability parsing fail");
@@ -456,13 +460,14 @@ static int bt_a2dp_get_capabilities_cb(struct bt_avdtp_req *req)
 		struct bt_a2dp_ep_info *info = &a2dp->discover_cb_param->info;
 
 		info->codec_type = codec_type;
-		info->sep_info = a2dp->discover_cb_param->seps_info[a2dp->get_cap_index];
+		info->sep_info = &a2dp->discover_cb_param->seps_info[a2dp->get_cap_index];
 		memcpy(&info->codec_cap.codec_ie, codec_info_element, codec_info_element_len);
 		info->codec_cap.len = codec_info_element_len;
 		user_ret = a2dp->discover_cb_param->cb(a2dp, info, &ep);
+
 		if (ep != NULL) {
 			ep->codec_type = info->codec_type;
-			ep->sep.sep_info = info->sep_info;
+			ep->sep.sep_info = *info->sep_info;
 			*ep->codec_cap = info->codec_cap;
 			ep->stream = NULL;
 		}
@@ -497,49 +502,57 @@ static int bt_a2dp_get_sep_caps(struct bt_a2dp *a2dp)
 	for (; a2dp->get_cap_index < a2dp->peer_seps_count; a2dp->get_cap_index++) {
 		if (a2dp->discover_cb_param->seps_info[a2dp->get_cap_index].media_type ==
 		    BT_AVDTP_AUDIO) {
+			memset(&a2dp->get_capabilities_param, 0U,
+			       sizeof(a2dp->get_capabilities_param));
 			a2dp->get_capabilities_param.req.func = bt_a2dp_get_capabilities_cb;
-			a2dp->get_capabilities_param.buf = NULL;
 			a2dp->get_capabilities_param.stream_endpoint_id =
 				a2dp->discover_cb_param->seps_info[a2dp->get_cap_index].id;
 			err = bt_avdtp_get_capabilities(&a2dp->session,
 							&a2dp->get_capabilities_param);
+
 			if (err) {
 				LOG_DBG("AVDTP get codec_cap failed");
 				a2dp->discover_cb_param->cb(a2dp, NULL, NULL);
 				a2dp->discover_cb_param = NULL;
 			}
+
 			return 0;
 		}
 	}
 	return -EINVAL;
 }
 
-static int bt_a2dp_discover_cb(struct bt_avdtp_req *req)
+static int bt_a2dp_discover_cb(struct bt_avdtp_req *req, struct net_buf *buf)
 {
 	struct bt_a2dp *a2dp = DISCOVER_PARAM(DISCOVER_REQ(req));
 	struct bt_avdtp_sep_info *sep_info;
 	int err;
 
 	LOG_DBG("DISCOVER result:%d", req->status);
-	if (a2dp->discover_cb_param == NULL) {
+	if (a2dp->discover_cb_param == NULL || buf == NULL) {
 		return -EINVAL;
 	}
+
 	a2dp->peer_seps_count = 0U;
+
 	if (!(req->status)) {
 		if (a2dp->discover_cb_param->sep_count == 0) {
 			if (a2dp->discover_cb_param->cb != NULL) {
 				a2dp->discover_cb_param->cb(a2dp, NULL, NULL);
 				a2dp->discover_cb_param = NULL;
 			}
+
 			return -EINVAL;
 		}
 
 		do {
 			sep_info = &a2dp->discover_cb_param->seps_info[a2dp->peer_seps_count];
-			err = bt_avdtp_parse_sep(DISCOVER_REQ(req)->buf, sep_info);
+			err = bt_avdtp_parse_sep(buf, sep_info);
+
 			if (err) {
 				break;
 			}
+
 			a2dp->peer_seps_count++;
 			LOG_DBG("id:%d, inuse:%d, media_type:%d, tsep:%d, ", sep_info->id,
 				sep_info->inuse, sep_info->media_type, sep_info->tsep);
@@ -580,14 +593,16 @@ int bt_a2dp_discover(struct bt_a2dp *a2dp, struct bt_a2dp_discover_param *param)
 		return -EBUSY;
 	}
 
+	memset(&a2dp->discover_cb_param, 0U, sizeof(a2dp->discover_cb_param));
 	a2dp->discover_cb_param = param;
 	a2dp->discover_param.req.func = bt_a2dp_discover_cb;
-	a2dp->discover_param.buf = NULL;
+
 	err = bt_avdtp_discover(&a2dp->session, &a2dp->discover_param);
 	if (err) {
 		if (a2dp->discover_cb_param->cb != NULL) {
 			a2dp->discover_cb_param->cb(a2dp, NULL, NULL);
 		}
+
 		a2dp->discover_cb_param = NULL;
 	}
 
@@ -606,6 +621,7 @@ static inline void bt_a2dp_stream_config_set_param(struct bt_a2dp *a2dp,
 						   uint8_t int_id, uint8_t codec_type,
 						   struct bt_avdtp_sep *sep)
 {
+	memset(&a2dp->set_config_param, 0U, sizeof(a2dp->set_config_param));
 	a2dp->set_config_param.req.func = cb;
 	a2dp->set_config_param.acp_stream_ep_id = remote_id;
 	a2dp->set_config_param.int_stream_endpoint_id = int_id;
@@ -656,7 +672,9 @@ static int bt_a2dp_ctrl_cb(struct bt_avdtp_req *req, bt_a2dp_rsp_cb rsp_cb, bt_a
 	if ((ep->stream == NULL) || (CTRL_REQ(req) != &a2dp->ctrl_param)) {
 		return -EINVAL;
 	}
+
 	stream = ep->stream;
+
 	if (clear_stream) {
 		ep->stream = NULL;
 	}
@@ -670,10 +688,11 @@ static int bt_a2dp_ctrl_cb(struct bt_avdtp_req *req, bt_a2dp_rsp_cb rsp_cb, bt_a
 	if ((!req->status) && (done_cb != NULL)) {
 		done_cb(stream);
 	}
+
 	return 0;
 }
 
-static int bt_a2dp_open_cb(struct bt_avdtp_req *req)
+static int bt_a2dp_open_cb(struct bt_avdtp_req *req, struct net_buf *buf)
 {
 	struct bt_a2dp_ep *ep = CONTAINER_OF(CTRL_REQ(req)->sep, struct bt_a2dp_ep, sep);
 	bt_a2dp_rsp_cb rsp_cb = a2dp_cb != NULL ? a2dp_cb->establish_rsp : NULL;
@@ -684,7 +703,7 @@ static int bt_a2dp_open_cb(struct bt_avdtp_req *req)
 	return bt_a2dp_ctrl_cb(req, rsp_cb, done_cb, false);
 }
 
-static int bt_a2dp_start_cb(struct bt_avdtp_req *req)
+static int bt_a2dp_start_cb(struct bt_avdtp_req *req, struct net_buf *buf)
 {
 	struct bt_a2dp_ep *ep = CONTAINER_OF(CTRL_REQ(req)->sep, struct bt_a2dp_ep, sep);
 	bt_a2dp_rsp_cb rsp_cb = a2dp_cb != NULL ? a2dp_cb->start_rsp : NULL;
@@ -694,7 +713,7 @@ static int bt_a2dp_start_cb(struct bt_avdtp_req *req)
 	return bt_a2dp_ctrl_cb(req, rsp_cb, done_cb, false);
 }
 
-static int bt_a2dp_suspend_cb(struct bt_avdtp_req *req)
+static int bt_a2dp_suspend_cb(struct bt_avdtp_req *req, struct net_buf *buf)
 {
 	struct bt_a2dp_ep *ep = CONTAINER_OF(CTRL_REQ(req)->sep, struct bt_a2dp_ep, sep);
 	bt_a2dp_rsp_cb rsp_cb = a2dp_cb != NULL ? a2dp_cb->suspend_rsp : NULL;
@@ -704,7 +723,7 @@ static int bt_a2dp_suspend_cb(struct bt_avdtp_req *req)
 	return bt_a2dp_ctrl_cb(req, rsp_cb, done_cb, false);
 }
 
-static int bt_a2dp_close_cb(struct bt_avdtp_req *req)
+static int bt_a2dp_close_cb(struct bt_avdtp_req *req, struct net_buf *buf)
 {
 	struct bt_a2dp_ep *ep = CONTAINER_OF(CTRL_REQ(req)->sep, struct bt_a2dp_ep, sep);
 	bt_a2dp_rsp_cb rsp_cb = a2dp_cb != NULL ? a2dp_cb->release_rsp : NULL;
@@ -714,7 +733,7 @@ static int bt_a2dp_close_cb(struct bt_avdtp_req *req)
 	return bt_a2dp_ctrl_cb(req, rsp_cb, done_cb, true);
 }
 
-static int bt_a2dp_abort_cb(struct bt_avdtp_req *req)
+static int bt_a2dp_abort_cb(struct bt_avdtp_req *req, struct net_buf *buf)
 {
 	struct bt_a2dp_ep *ep = CONTAINER_OF(CTRL_REQ(req)->sep, struct bt_a2dp_ep, sep);
 	bt_a2dp_rsp_cb rsp_cb = a2dp_cb != NULL ? a2dp_cb->abort_rsp : NULL;
@@ -733,6 +752,7 @@ static int bt_a2dp_stream_ctrl_pre(struct bt_a2dp_stream *stream, bt_avdtp_func_
 	}
 
 	a2dp = stream->a2dp;
+	memset(&a2dp->ctrl_param, 0U, sizeof(a2dp->ctrl_param));
 	a2dp->ctrl_param.req.func = cb;
 	a2dp->ctrl_param.acp_stream_ep_id = stream->remote_ep != NULL
 						    ? stream->remote_ep->sep.sep_info.id
@@ -750,6 +770,7 @@ int bt_a2dp_stream_establish(struct bt_a2dp_stream *stream)
 	if (err) {
 		return err;
 	}
+
 	return bt_avdtp_open(&a2dp->session, &a2dp->ctrl_param);
 }
 
@@ -762,6 +783,7 @@ int bt_a2dp_stream_release(struct bt_a2dp_stream *stream)
 	if (err) {
 		return err;
 	}
+
 	return bt_avdtp_close(&a2dp->session, &a2dp->ctrl_param);
 }
 
@@ -774,6 +796,7 @@ int bt_a2dp_stream_start(struct bt_a2dp_stream *stream)
 	if (err) {
 		return err;
 	}
+
 	return bt_avdtp_start(&a2dp->session, &a2dp->ctrl_param);
 }
 
@@ -786,6 +809,7 @@ int bt_a2dp_stream_suspend(struct bt_a2dp_stream *stream)
 	if (err) {
 		return err;
 	}
+
 	return bt_avdtp_suspend(&a2dp->session, &a2dp->ctrl_param);
 }
 
@@ -798,6 +822,7 @@ int bt_a2dp_stream_abort(struct bt_a2dp_stream *stream)
 	if (err) {
 		return err;
 	}
+
 	return bt_avdtp_abort(&a2dp->session, &a2dp->ctrl_param);
 }
 
@@ -838,6 +863,7 @@ int bt_a2dp_stream_send(struct bt_a2dp_stream *stream, struct net_buf *buf, uint
 
 	media_hdr = net_buf_push(buf, sizeof(struct bt_avdtp_media_hdr));
 	memset(media_hdr, 0, sizeof(struct bt_avdtp_media_hdr));
+
 	if (stream->local_ep->codec_type == BT_A2DP_SBC) {
 		media_hdr->playload_type = A2DP_SBC_PAYLOAD_TYPE;
 	}
@@ -859,6 +885,7 @@ int a2dp_stream_l2cap_disconnected(struct bt_avdtp *session, struct bt_avdtp_sep
 
 	__ASSERT(sep, "Invalid sep");
 	ep = CONTAINER_OF(sep, struct bt_a2dp_ep, sep);
+
 	if (ep->stream != NULL) {
 		struct bt_a2dp_stream_ops *ops;
 		struct bt_a2dp_stream *stream = ep->stream;
@@ -869,6 +896,7 @@ int a2dp_stream_l2cap_disconnected(struct bt_avdtp *session, struct bt_avdtp_sep
 		 * all the related callbacks are in the same zephyr task context.
 		 */
 		ep->stream = NULL;
+
 		if ((ops != NULL) && (ops->released != NULL)) {
 			ops->released(stream);
 		}
@@ -945,8 +973,8 @@ struct bt_a2dp *bt_a2dp_connect(struct bt_conn *conn)
 	}
 
 	a2dp->a2dp_state = INTERNAL_STATE_IDLE;
-
 	a2dp->session.ops = &signaling_avdtp_ops;
+
 	err = bt_avdtp_connect(conn, &(a2dp->session));
 	if (err < 0) {
 		LOG_DBG("AVDTP Connect failed");
@@ -978,6 +1006,7 @@ int bt_a2dp_register_ep(struct bt_a2dp_ep *ep, uint8_t media_type, uint8_t sep_t
 #else
 	ep->sep.media_data_cb = NULL;
 #endif
+
 	err = bt_avdtp_register_sep(media_type, sep_type, &(ep->sep));
 	if (err < 0) {
 		return err;
diff --git a/subsys/bluetooth/host/classic/at.c b/subsys/bluetooth/host/classic/at.c
index fadeeab10fb..b56ad286f06 100644
--- a/subsys/bluetooth/host/classic/at.c
+++ b/subsys/bluetooth/host/classic/at.c
@@ -119,24 +119,46 @@ static int get_cmd_value(struct at_client *at, struct net_buf *buf,
 	return 0;
 }
 
-static int get_response_string(struct at_client *at, struct net_buf *buf,
-			       char stop_byte, enum at_state state)
+static bool is_stop_byte(char target, char *stop_string)
+{
+	return (strchr(stop_string, target) != NULL);
+}
+
+static bool is_vgm_or_vgs(struct at_client *at)
+{
+	if (!strcmp(at->buf, "VGM")) {
+		return true;
+	}
+
+	if (!strcmp(at->buf, "VGS")) {
+		return true;
+	}
+	return false;
+}
+
+static int get_response_string(struct at_client *at, struct net_buf *buf, char *stop_string,
+			       enum at_state state)
 {
 	int cmd_len = 0;
 	uint8_t pos = at->pos;
 	const char *str = (char *)buf->data;
 
 	while (cmd_len < buf->len && at->pos != at->buf_max_len) {
-		if (*str != stop_byte) {
+		if (!is_stop_byte(*str, stop_string)) {
 			at->buf[at->pos++] = *str;
 			cmd_len++;
 			str++;
 			pos = at->pos;
 		} else {
+			char stop_byte = at->buf[at->pos];
+
 			cmd_len++;
 			at->buf[at->pos] = '\0';
 			at->pos = 0U;
 			at->state = state;
+			if ((stop_byte == '=') && !is_vgm_or_vgs(at)) {
+				return -EINVAL;
+			}
 			break;
 		}
 	}
@@ -197,7 +219,7 @@ static int at_state_start_lf(struct at_client *at, struct net_buf *buf)
 
 static int at_state_get_cmd_string(struct at_client *at, struct net_buf *buf)
 {
-	return get_response_string(at, buf, ':', AT_STATE_PROCESS_CMD);
+	return get_response_string(at, buf, ":=", AT_STATE_PROCESS_CMD);
 }
 
 static bool is_cmer(struct at_client *at)
@@ -227,7 +249,7 @@ static int at_state_process_cmd(struct at_client *at, struct net_buf *buf)
 
 static int at_state_get_result_string(struct at_client *at, struct net_buf *buf)
 {
-	return get_response_string(at, buf, '\r', AT_STATE_PROCESS_RESULT);
+	return get_response_string(at, buf, "\r", AT_STATE_PROCESS_RESULT);
 }
 
 static bool is_ring(struct at_client *at)
@@ -427,7 +449,7 @@ int at_parse_cmd_input(struct at_client *at, struct net_buf *buf,
 
 int at_has_next_list(struct at_client *at)
 {
-	return at->buf[at->pos] != '\0';
+	return at->buf[at->pos] != '\0' && at->buf[at->pos] != ')';
 }
 
 int at_open_list(struct at_client *at)
@@ -535,3 +557,59 @@ void at_register(struct at_client *at, at_resp_cb_t resp, at_finish_cb_t finish)
 	at->finish = finish;
 	at->state = AT_STATE_START;
 }
+
+char *at_get_string(struct at_client *at)
+{
+	uint8_t pos = at->pos;
+	char *string;
+
+	skip_space(at);
+
+	if (at->buf[at->pos] != '"') {
+		at->pos = pos;
+		return NULL;
+	}
+	at->pos++;
+	string = &at->buf[at->pos];
+
+	while (at->buf[at->pos] != '\0' && at->buf[at->pos] != '"') {
+		at->pos++;
+	}
+
+	if (at->buf[at->pos] != '"') {
+		at->pos = pos;
+		return NULL;
+	}
+
+	at->buf[at->pos] = '\0';
+	at->pos++;
+
+	skip_space(at);
+	next_list(at);
+
+	return string;
+}
+
+char *at_get_raw_string(struct at_client *at, size_t *string_len)
+{
+	char *string;
+
+	skip_space(at);
+
+	string = &at->buf[at->pos];
+
+	while (at->buf[at->pos] != '\0' &&
+		   at->buf[at->pos] != ',' &&
+		   at->buf[at->pos] != ')') {
+		at->pos++;
+	}
+
+	if (string_len) {
+		*string_len = &at->buf[at->pos] - string;
+	}
+
+	skip_space(at);
+	next_list(at);
+
+	return string;
+}
diff --git a/subsys/bluetooth/host/classic/at.h b/subsys/bluetooth/host/classic/at.h
index ae2c7f95d80..fc6ab68ad2f 100644
--- a/subsys/bluetooth/host/classic/at.h
+++ b/subsys/bluetooth/host/classic/at.h
@@ -116,3 +116,5 @@ int at_list_get_string(struct at_client *at, char *name, uint8_t len);
 int at_close_list(struct at_client *at);
 int at_open_list(struct at_client *at);
 int at_has_next_list(struct at_client *at);
+char *at_get_string(struct at_client *at);
+char *at_get_raw_string(struct at_client *at, size_t *string_len);
diff --git a/subsys/bluetooth/host/classic/avctp.c b/subsys/bluetooth/host/classic/avctp.c
index 330b22ad9b8..939361552b5 100644
--- a/subsys/bluetooth/host/classic/avctp.c
+++ b/subsys/bluetooth/host/classic/avctp.c
@@ -82,6 +82,7 @@ static int avctp_l2cap_recv(struct bt_l2cap_chan *chan, struct net_buf *buf)
 	uint8_t tid;
 	bt_avctp_pkt_type_t pkt_type;
 	bt_avctp_cr_t cr;
+	int err;
 
 	if (buf->len < sizeof(*hdr)) {
 		LOG_ERR("invalid AVCTP header received");
@@ -113,11 +114,17 @@ static int avctp_l2cap_recv(struct bt_l2cap_chan *chan, struct net_buf *buf)
 		if (cr == BT_AVCTP_CMD) {
 			rsp = bt_avctp_create_pdu(session, BT_AVCTP_RESPONSE,
 						  BT_AVCTP_PKT_TYPE_SINGLE, BT_AVCTP_IPID_INVALID,
-						  &tid, hdr->pid);
+						  tid, hdr->pid);
 			if (!rsp) {
 				return -ENOMEM;
 			}
-			return bt_avctp_send(session, rsp);
+
+			err = bt_avctp_send(session, rsp);
+			if (err < 0) {
+				net_buf_unref(rsp);
+				LOG_ERR("AVCTP send fail, err = %d", err);
+				return err;
+			}
 		}
 		return 0; /* No need to report to the upper layer */
 	}
@@ -125,15 +132,15 @@ static int avctp_l2cap_recv(struct bt_l2cap_chan *chan, struct net_buf *buf)
 	return session->ops->recv(session, buf);
 }
 
+static const struct bt_l2cap_chan_ops ops = {
+	.connected = avctp_l2cap_connected,
+	.disconnected = avctp_l2cap_disconnected,
+	.encrypt_change = avctp_l2cap_encrypt_changed,
+	.recv = avctp_l2cap_recv,
+};
+
 int bt_avctp_connect(struct bt_conn *conn, struct bt_avctp *session)
 {
-	static const struct bt_l2cap_chan_ops ops = {
-		.connected = avctp_l2cap_connected,
-		.disconnected = avctp_l2cap_disconnected,
-		.encrypt_change = avctp_l2cap_encrypt_changed,
-		.recv = avctp_l2cap_recv,
-	};
-
 	if (!session) {
 		return -EINVAL;
 	}
@@ -158,7 +165,7 @@ int bt_avctp_disconnect(struct bt_avctp *session)
 
 struct net_buf *bt_avctp_create_pdu(struct bt_avctp *session, bt_avctp_cr_t cr,
 				    bt_avctp_pkt_type_t pkt_type, bt_avctp_ipid_t ipid,
-				    uint8_t *tid, uint16_t pid)
+				    uint8_t tid, uint16_t pid)
 {
 	struct net_buf *buf;
 	struct bt_avctp_header *hdr;
@@ -172,16 +179,12 @@ struct net_buf *bt_avctp_create_pdu(struct bt_avctp *session, bt_avctp_cr_t cr,
 	}
 
 	hdr = net_buf_add(buf, sizeof(*hdr));
-	BT_AVCTP_HDR_SET_TRANSACTION_LABLE(hdr, *tid);
+	BT_AVCTP_HDR_SET_TRANSACTION_LABLE(hdr, tid);
 	BT_AVCTP_HDR_SET_PACKET_TYPE(hdr, pkt_type);
 	BT_AVCTP_HDR_SET_CR(hdr, cr);
 	BT_AVCTP_HDR_SET_IPID(hdr, ipid);
 	hdr->pid = pid;
 
-	if (cr == BT_AVCTP_CMD) {
-		*tid = (*tid + 1) & 0x0F; /* Incremented by one */
-	}
-
 	LOG_DBG("cr:0x%lX, tid:0x%02lX", BT_AVCTP_HDR_GET_CR(hdr),
 		BT_AVCTP_HDR_GET_TRANSACTION_LABLE(hdr));
 	return buf;
@@ -189,16 +192,7 @@ struct net_buf *bt_avctp_create_pdu(struct bt_avctp *session, bt_avctp_cr_t cr,
 
 int bt_avctp_send(struct bt_avctp *session, struct net_buf *buf)
 {
-	int err;
-
-	err = bt_l2cap_chan_send(&session->br_chan.chan, buf);
-	if (err < 0) {
-		net_buf_unref(buf);
-		LOG_ERR("L2CAP send fail err = %d", err);
-		return err;
-	}
-
-	return err;
+	return bt_l2cap_chan_send(&session->br_chan.chan, buf);
 }
 
 int bt_avctp_register(const struct bt_avctp_event_cb *cb)
@@ -217,9 +211,29 @@ int bt_avctp_register(const struct bt_avctp_event_cb *cb)
 static int avctp_l2cap_accept(struct bt_conn *conn, struct bt_l2cap_server *server,
 			      struct bt_l2cap_chan **chan)
 {
-	/* TODO */
+	struct bt_avctp *session = NULL;
+	int err;
 
-	return -ENOTSUP;
+	LOG_DBG("conn %p", conn);
+
+	if (!event_cb) {
+		LOG_WRN("AVCTP server is unsupported");
+		return -ENOTSUP;
+	}
+
+	/* Get the AVCTP session from upper layer */
+	err = event_cb->accept(conn, &session);
+	if (err < 0) {
+		LOG_ERR("Get the AVCTP session failed %d", err);
+		return err;
+	}
+
+	session->br_chan.rx.mtu = BT_L2CAP_RX_MTU;
+	session->br_chan.psm = BT_L2CAP_PSM_AVCTP;
+	session->br_chan.chan.ops = &ops;
+	*chan = &session->br_chan.chan;
+
+	return 0;
 }
 
 int bt_avctp_init(void)
diff --git a/subsys/bluetooth/host/classic/avctp_internal.h b/subsys/bluetooth/host/classic/avctp_internal.h
index a0ec073a71a..280622be438 100644
--- a/subsys/bluetooth/host/classic/avctp_internal.h
+++ b/subsys/bluetooth/host/classic/avctp_internal.h
@@ -103,7 +103,7 @@ int bt_avctp_disconnect(struct bt_avctp *session);
 /* Create AVCTP PDU */
 struct net_buf *bt_avctp_create_pdu(struct bt_avctp *session, bt_avctp_cr_t cr,
 				    bt_avctp_pkt_type_t pkt_type, bt_avctp_ipid_t ipid,
-				    uint8_t *tid, uint16_t pid);
+				    uint8_t tid, uint16_t pid);
 
 /* Send AVCTP PDU */
 int bt_avctp_send(struct bt_avctp *session, struct net_buf *buf);
diff --git a/subsys/bluetooth/host/classic/avdtp.c b/subsys/bluetooth/host/classic/avdtp.c
index 237568d5e91..98d071deeef 100644
--- a/subsys/bluetooth/host/classic/avdtp.c
+++ b/subsys/bluetooth/host/classic/avdtp.c
@@ -93,6 +93,7 @@ static void avdtp_sep_unlock(struct bt_avdtp_sep *sep)
 static void bt_avdtp_set_state(struct bt_avdtp_sep *sep, uint8_t state)
 {
 	sep->state = state;
+
 	if (state != AVDTP_IDLE) {
 		sep->sep_info.inuse = 1U;
 	} else {
@@ -132,13 +133,15 @@ void bt_avdtp_media_l2cap_connected(struct bt_l2cap_chan *chan)
 
 	LOG_DBG("chan %p session %p", chan, session);
 	bt_avdtp_set_state_lock(sep, AVDTP_OPEN);
+
 	if (session->req != NULL) {
 		struct bt_avdtp_req *req = session->req;
 
-		req->status = 0;
+		req->status = BT_AVDTP_SUCCESS;
 		bt_avdtp_clear_req(session);
+
 		if (req->func != NULL) {
-			req->func(req);
+			req->func(req, NULL);
 		}
 	}
 }
@@ -156,6 +159,7 @@ void bt_avdtp_media_l2cap_disconnected(struct bt_l2cap_chan *chan)
 	LOG_DBG("chan %p", chan);
 	chan->conn = NULL;
 	avdtp_sep_lock(sep);
+
 	if ((sep->state == AVDTP_CLOSING) && (session->req != NULL) &&
 	    (session->req->sig == BT_AVDTP_CLOSE)) {
 		/* closing the stream */
@@ -163,10 +167,11 @@ void bt_avdtp_media_l2cap_disconnected(struct bt_l2cap_chan *chan)
 
 		bt_avdtp_set_state(sep, AVDTP_IDLE);
 		avdtp_sep_unlock(sep);
-		req->status = 0;
+		req->status = BT_AVDTP_SUCCESS;
 		bt_avdtp_clear_req(session);
+
 		if (req->func != NULL) {
-			req->func(req);
+			req->func(req, NULL);
 		}
 	} else if (sep->state > AVDTP_OPENING) {
 		bt_avdtp_set_state(sep, AVDTP_IDLE);
@@ -245,7 +250,7 @@ static struct net_buf *avdtp_create_reply_pdu(uint8_t msg_type, uint8_t pkt_type
 static void avdtp_set_status(struct bt_avdtp_req *req, struct net_buf *buf, uint8_t msg_type)
 {
 	if (msg_type == BT_AVDTP_ACCEPT) {
-		req->status = 0;
+		req->status = BT_AVDTP_SUCCESS;
 	} else if (msg_type == BT_AVDTP_REJECT) {
 		if (buf->len >= 1U) {
 			req->status = net_buf_pull_u8(buf);
@@ -260,71 +265,68 @@ static void avdtp_set_status(struct bt_avdtp_req *req, struct net_buf *buf, uint
 	}
 }
 
-static void avdtp_discover_handler(struct bt_avdtp *session, struct net_buf *buf, uint8_t msg_type,
-				   uint8_t tid)
+static void avdtp_discover_cmd(struct bt_avdtp *session, struct net_buf *buf, uint8_t tid)
 {
-	if (msg_type == BT_AVDTP_CMD) {
-		int err;
-		struct bt_avdtp_sep *sep;
-		struct net_buf *rsp_buf;
-		uint8_t error_code = 0;
+	int err;
+	struct bt_avdtp_sep *sep;
+	struct net_buf *rsp_buf;
+	uint8_t error_code = 0;
 
-		if (session->ops->discovery_ind == NULL) {
-			err = -ENOTSUP;
-		} else {
-			err = session->ops->discovery_ind(session, &error_code);
-		}
+	if (session->ops->discovery_ind == NULL) {
+		err = -ENOTSUP;
+	} else {
+		err = session->ops->discovery_ind(session, &error_code);
+	}
 
-		rsp_buf =
-			avdtp_create_reply_pdu(err ? BT_AVDTP_REJECT : BT_AVDTP_ACCEPT,
-					       BT_AVDTP_PACKET_TYPE_SINGLE, BT_AVDTP_DISCOVER, tid);
-		if (!rsp_buf) {
-			return;
-		}
+	rsp_buf = avdtp_create_reply_pdu(err ? BT_AVDTP_REJECT : BT_AVDTP_ACCEPT,
+					 BT_AVDTP_PACKET_TYPE_SINGLE, BT_AVDTP_DISCOVER, tid);
+	if (!rsp_buf) {
+		return;
+	}
 
-		if (err) {
-			if (error_code == 0) {
-				error_code = BT_AVDTP_BAD_STATE;
-			}
-			LOG_DBG("discover err code:%d", error_code);
-			net_buf_add_u8(rsp_buf, error_code);
-		} else {
-			struct bt_avdtp_sep_data sep_data;
-
-			SYS_SLIST_FOR_EACH_CONTAINER(&seps, sep, _node) {
-				memset(&sep_data, 0, sizeof(sep_data));
-				sep_data.inuse = sep->sep_info.inuse;
-				sep_data.id = sep->sep_info.id;
-				sep_data.tsep = sep->sep_info.tsep;
-				sep_data.media_type = sep->sep_info.media_type;
-				net_buf_add_mem(rsp_buf, &sep_data, sizeof(sep_data));
-			}
+	if (err) {
+		if (error_code == 0) {
+			error_code = BT_AVDTP_BAD_STATE;
 		}
 
-		err = bt_l2cap_chan_send(&session->br_chan.chan, rsp_buf);
-		if (err < 0) {
-			net_buf_unref(rsp_buf);
-			LOG_ERR("Error:L2CAP send fail - result = %d", err);
-			return;
-		}
+		LOG_DBG("discover err code:%d", error_code);
+		net_buf_add_u8(rsp_buf, error_code);
 	} else {
-		struct bt_avdtp_req *req = session->req;
+		struct bt_avdtp_sep_data sep_data;
 
-		if (req == NULL) {
-			return;
-		}
-		k_work_cancel_delayable(&session->timeout_work);
-		if (msg_type == BT_AVDTP_ACCEPT) {
-			DISCOVER_REQ(req)->buf = buf;
-		} else {
-			DISCOVER_REQ(req)->buf = NULL;
-		}
-		avdtp_set_status(req, buf, msg_type);
-		bt_avdtp_clear_req(session);
-		if (req->func != NULL) {
-			req->func(req);
+		SYS_SLIST_FOR_EACH_CONTAINER(&seps, sep, _node) {
+			memset(&sep_data, 0, sizeof(sep_data));
+			sep_data.inuse = sep->sep_info.inuse;
+			sep_data.id = sep->sep_info.id;
+			sep_data.tsep = sep->sep_info.tsep;
+			sep_data.media_type = sep->sep_info.media_type;
+			net_buf_add_mem(rsp_buf, &sep_data, sizeof(sep_data));
 		}
 	}
+
+	err = bt_l2cap_chan_send(&session->br_chan.chan, rsp_buf);
+	if (err < 0) {
+		net_buf_unref(rsp_buf);
+		LOG_ERR("Error:L2CAP send fail - result = %d", err);
+		return;
+	}
+}
+
+static void avdtp_discover_rsp(struct bt_avdtp *session, struct net_buf *buf, uint8_t msg_type)
+{
+	struct bt_avdtp_req *req = session->req;
+
+	if (req == NULL) {
+		return;
+	}
+
+	k_work_cancel_delayable(&session->timeout_work);
+	avdtp_set_status(req, buf, msg_type);
+	bt_avdtp_clear_req(session);
+
+	if (req->func != NULL) {
+		req->func(req, buf);
+	}
 }
 
 static struct bt_avdtp_sep *avdtp_get_sep(uint8_t stream_endpoint_id)
@@ -340,602 +342,641 @@ static struct bt_avdtp_sep *avdtp_get_sep(uint8_t stream_endpoint_id)
 	return sep;
 }
 
-static struct bt_avdtp_sep *avdtp_get_cmd_sep(struct net_buf *buf)
+static struct bt_avdtp_sep *avdtp_get_cmd_sep(struct net_buf *buf, uint8_t *error_code)
 {
 	struct bt_avdtp_sep *sep;
 
 	if (buf->len < 1U) {
+		*error_code = BT_AVDTP_BAD_LENGTH;
 		LOG_WRN("Invalid ACP SEID");
 		return NULL;
 	}
+
 	sep = avdtp_get_sep(net_buf_pull_u8(buf) >> 2);
 	return sep;
 }
 
-static void avdtp_get_capabilities_handler(struct bt_avdtp *session, struct net_buf *buf,
-					   uint8_t msg_type, uint8_t tid)
+static void avdtp_get_capabilities_cmd(struct bt_avdtp *session, struct net_buf *buf, uint8_t tid)
 {
-	if (msg_type == BT_AVDTP_CMD) {
-		int err = 0;
-		struct net_buf *rsp_buf;
-		struct bt_avdtp_sep *sep;
-		uint8_t error_code = 0;
-
-		sep = avdtp_get_cmd_sep(buf);
-		if ((sep == NULL) || (session->ops->get_capabilities_ind == NULL)) {
-			err = -ENOTSUP;
-		} else {
-			rsp_buf =
-				avdtp_create_reply_pdu(BT_AVDTP_ACCEPT, BT_AVDTP_PACKET_TYPE_SINGLE,
-						       BT_AVDTP_GET_CAPABILITIES, tid);
-			if (!rsp_buf) {
-				return;
-			}
-			err = session->ops->get_capabilities_ind(session, sep, rsp_buf,
-								 &error_code);
-			if (err) {
-				net_buf_unref(rsp_buf);
-			}
-		}
+	int err = 0;
+	struct net_buf *rsp_buf;
+	struct bt_avdtp_sep *sep;
+	uint8_t error_code = 0;
 
-		if (err) {
-			rsp_buf =
-				avdtp_create_reply_pdu(BT_AVDTP_REJECT, BT_AVDTP_PACKET_TYPE_SINGLE,
-						       BT_AVDTP_GET_CAPABILITIES, tid);
-			if (!rsp_buf) {
-				return;
-			}
+	sep = avdtp_get_cmd_sep(buf, &error_code);
 
-			if (error_code == 0) {
-				error_code = BT_AVDTP_BAD_ACP_SEID;
-			}
-			LOG_DBG("get cap err code:%d", error_code);
-			net_buf_add_u8(rsp_buf, error_code);
+	if ((sep == NULL) || (session->ops->get_capabilities_ind == NULL)) {
+		err = -ENOTSUP;
+	} else {
+		rsp_buf = avdtp_create_reply_pdu(BT_AVDTP_ACCEPT, BT_AVDTP_PACKET_TYPE_SINGLE,
+						 BT_AVDTP_GET_CAPABILITIES, tid);
+		if (!rsp_buf) {
+			return;
 		}
 
-		err = bt_l2cap_chan_send(&session->br_chan.chan, rsp_buf);
-		if (err < 0) {
+		err = session->ops->get_capabilities_ind(session, sep, rsp_buf, &error_code);
+		if (err) {
 			net_buf_unref(rsp_buf);
-			LOG_ERR("Error:L2CAP send fail - result = %d", err);
-			return;
 		}
-	} else {
-		struct bt_avdtp_req *req = session->req;
+	}
 
-		if (req == NULL) {
+	if (err) {
+		rsp_buf = avdtp_create_reply_pdu(BT_AVDTP_REJECT, BT_AVDTP_PACKET_TYPE_SINGLE,
+						 BT_AVDTP_GET_CAPABILITIES, tid);
+		if (!rsp_buf) {
 			return;
 		}
-		k_work_cancel_delayable(&session->timeout_work);
-		GET_CAP_REQ(session->req)->buf = NULL;
 
-		if (msg_type == BT_AVDTP_ACCEPT) {
-			GET_CAP_REQ(req)->buf = buf;
-		}
-		avdtp_set_status(req, buf, msg_type);
-		bt_avdtp_clear_req(session);
-		if (req->func != NULL) {
-			req->func(req);
+		if (error_code == 0) {
+			error_code = BT_AVDTP_BAD_ACP_SEID;
 		}
+
+		LOG_DBG("get cap err code:%d", error_code);
+		net_buf_add_u8(rsp_buf, error_code);
+	}
+
+	err = bt_l2cap_chan_send(&session->br_chan.chan, rsp_buf);
+	if (err < 0) {
+		net_buf_unref(rsp_buf);
+		LOG_ERR("Error:L2CAP send fail - result = %d", err);
+		return;
 	}
 }
 
-static void avdtp_process_configuration(struct bt_avdtp *session, struct net_buf *buf,
-					uint8_t msg_type, uint8_t tid, bool reconfig)
+static void avdtp_get_capabilities_rsp(struct bt_avdtp *session, struct net_buf *buf,
+				       uint8_t msg_type)
 {
-	if (msg_type == BT_AVDTP_CMD) {
-		int err = 0;
-		int ret;
-		struct bt_avdtp_sep *sep;
-		struct net_buf *rsp_buf;
-		uint8_t error_code = 0;
+	struct bt_avdtp_req *req = session->req;
 
-		sep = avdtp_get_cmd_sep(buf);
-		avdtp_sep_lock(sep);
-		if (sep == NULL) {
-			err = -ENOTSUP;
-		} else if (!reconfig && session->ops->set_configuration_ind == NULL) {
-			err = -ENOTSUP;
-		} else if (reconfig && session->ops->re_configuration_ind == NULL) {
-			err = -ENOTSUP;
-		} else {
-			uint8_t expected_state;
+	if (req == NULL) {
+		return;
+	}
 
-			if (reconfig) {
-				expected_state = AVDTP_OPEN | AVDTP_OPENING;
-			} else {
-				expected_state = AVDTP_IDLE;
-			}
+	k_work_cancel_delayable(&session->timeout_work);
+	avdtp_set_status(req, buf, msg_type);
+	bt_avdtp_clear_req(session);
 
-			if (!(sep->state & expected_state)) {
-				err = -ENOTSUP;
-				error_code = BT_AVDTP_BAD_STATE;
-			} else {
-				uint8_t int_seid;
+	if (req->func != NULL) {
+		req->func(req, buf);
+	}
+}
 
-				if (buf->len < 1U) {
-					LOG_WRN("Invalid INT SEID");
-					avdtp_sep_unlock(sep);
-					return;
-				}
-				/* INT Stream Endpoint ID */
-				int_seid = net_buf_pull_u8(buf) >> 2;
-				if (!reconfig) {
-					err = session->ops->set_configuration_ind(
-						session, sep, int_seid, buf, &error_code);
-				} else {
-					err = session->ops->re_configuration_ind(
-						session, sep, int_seid, buf, &error_code);
-				}
-			}
-		}
+static void avdtp_process_configuration_cmd(struct bt_avdtp *session, struct net_buf *buf,
+					    uint8_t tid, bool reconfig)
+{
+	int err = 0;
+	struct bt_avdtp_sep *sep;
+	struct net_buf *rsp_buf;
+	uint8_t avdtp_err_code = 0;
 
-		rsp_buf = avdtp_create_reply_pdu(
-			err ? BT_AVDTP_REJECT : BT_AVDTP_ACCEPT, BT_AVDTP_PACKET_TYPE_SINGLE,
-			reconfig ? BT_AVDTP_RECONFIGURE : BT_AVDTP_SET_CONFIGURATION, tid);
-		if (!rsp_buf) {
-			avdtp_sep_unlock(sep);
-			return;
+	sep = avdtp_get_cmd_sep(buf, &avdtp_err_code);
+	avdtp_sep_lock(sep);
+
+	if (sep == NULL) {
+		err = -ENOTSUP;
+	} else if (!reconfig && session->ops->set_configuration_ind == NULL) {
+		err = -ENOTSUP;
+	} else if (reconfig && session->ops->re_configuration_ind == NULL) {
+		err = -ENOTSUP;
+	} else {
+		uint8_t expected_state;
+
+		if (reconfig) {
+			expected_state = AVDTP_OPEN | AVDTP_OPENING;
+		} else {
+			expected_state = AVDTP_IDLE;
 		}
 
-		if (err) {
-			if (error_code == 0) {
-				error_code = BT_AVDTP_BAD_ACP_SEID;
+		if (!(sep->state & expected_state)) {
+			err = -ENOTSUP;
+			avdtp_err_code = BT_AVDTP_BAD_STATE;
+		} else if (buf->len >= 1U) {
+			uint8_t int_seid;
+
+			/* INT Stream Endpoint ID */
+			int_seid = net_buf_pull_u8(buf) >> 2;
+
+			if (!reconfig) {
+				err = session->ops->set_configuration_ind(session, sep, int_seid,
+									  buf, &avdtp_err_code);
+			} else {
+				err = session->ops->re_configuration_ind(session, sep, int_seid,
+									 buf, &avdtp_err_code);
 			}
-			LOG_DBG("set configuration err code:%d", error_code);
-			/* Service Category: Media Codec */
-			net_buf_add_u8(rsp_buf, BT_AVDTP_SERVICE_MEDIA_CODEC);
-			/* Length Of Service Capability */
-			net_buf_add_u8(rsp_buf, 0);
-			/* ERROR CODE */
-			net_buf_add_u8(rsp_buf, error_code);
+		} else {
+			LOG_WRN("Invalid INT SEID");
+			err = -ENOTSUP;
+			avdtp_err_code = BT_AVDTP_BAD_LENGTH;
 		}
+	}
 
-		ret = bt_l2cap_chan_send(&session->br_chan.chan, rsp_buf);
-		if (ret) {
-			net_buf_unref(rsp_buf);
-			LOG_ERR("Error:L2CAP send fail - result = %d", ret);
-		}
-		if (!reconfig && !err && !ret) {
-			bt_avdtp_set_state(sep, AVDTP_CONFIGURED);
-		}
+	rsp_buf = avdtp_create_reply_pdu(
+		err ? BT_AVDTP_REJECT : BT_AVDTP_ACCEPT, BT_AVDTP_PACKET_TYPE_SINGLE,
+		reconfig ? BT_AVDTP_RECONFIGURE : BT_AVDTP_SET_CONFIGURATION, tid);
+	if (!rsp_buf) {
 		avdtp_sep_unlock(sep);
-	} else {
-		struct bt_avdtp_req *req = session->req;
+		return;
+	}
 
-		if (req == NULL) {
-			return;
+	if (err) {
+		if (avdtp_err_code == 0) {
+			avdtp_err_code = BT_AVDTP_BAD_ACP_SEID;
 		}
-		k_work_cancel_delayable(&session->timeout_work);
-		if (msg_type == BT_AVDTP_ACCEPT) {
-			if (!reconfig) {
-				bt_avdtp_set_state_lock(SET_CONF_REQ(req)->sep, AVDTP_CONFIGURED);
-			}
-		} else if (msg_type == BT_AVDTP_REJECT) {
-			if (buf->len < 1U) {
-				LOG_WRN("Invalid RSP frame");
-				return;
-			}
+
+		LOG_DBG("set configuration err code:%d", avdtp_err_code);
+		/* Service Category: Media Codec */
+		net_buf_add_u8(rsp_buf, BT_AVDTP_SERVICE_MEDIA_CODEC);
+		/* Length Of Service Capability */
+		net_buf_add_u8(rsp_buf, 0);
+		/* ERROR CODE */
+		net_buf_add_u8(rsp_buf, avdtp_err_code);
+	}
+
+	err = bt_l2cap_chan_send(&session->br_chan.chan, rsp_buf);
+	if (err) {
+		net_buf_unref(rsp_buf);
+		LOG_ERR("Error:L2CAP send fail - result = %d", err);
+	}
+
+	if (!reconfig && !err && !avdtp_err_code) {
+		bt_avdtp_set_state(sep, AVDTP_CONFIGURED);
+	}
+
+	avdtp_sep_unlock(sep);
+}
+
+static void avdtp_process_configuration_rsp(struct bt_avdtp *session, struct net_buf *buf,
+					    uint8_t msg_type, bool reconfig)
+{
+	struct bt_avdtp_req *req = session->req;
+
+	if (req == NULL) {
+		return;
+	}
+
+	k_work_cancel_delayable(&session->timeout_work);
+
+	if (msg_type == BT_AVDTP_ACCEPT) {
+		if (!reconfig) {
+			bt_avdtp_set_state_lock(SET_CONF_REQ(req)->sep, AVDTP_CONFIGURED);
+		}
+	} else if (msg_type == BT_AVDTP_REJECT) {
+		if (buf->len < 1U) {
+			LOG_WRN("Invalid RSP frame");
+			req->status = BT_AVDTP_BAD_LENGTH;
+		} else {
 			/* Service Category */
 			net_buf_pull_u8(buf);
 		}
+	}
+
+	if (req->status == BT_AVDTP_SUCCESS) {
 		avdtp_set_status(req, buf, msg_type);
-		bt_avdtp_clear_req(session);
-		if (req->func != NULL) {
-			req->func(req);
-		}
 	}
+
+	bt_avdtp_clear_req(session);
+
+	if (req->func != NULL) {
+		req->func(req, NULL);
+	}
+}
+
+static void avdtp_set_configuration_cmd(struct bt_avdtp *session, struct net_buf *buf, uint8_t tid)
+{
+	avdtp_process_configuration_cmd(session, buf, tid, false);
+}
+
+static void avdtp_set_configuration_rsp(struct bt_avdtp *session, struct net_buf *buf,
+					uint8_t msg_type)
+{
+	avdtp_process_configuration_rsp(session, buf, msg_type, false);
+}
+
+static void avdtp_re_configure_cmd(struct bt_avdtp *session, struct net_buf *buf, uint8_t tid)
+{
+	avdtp_process_configuration_cmd(session, buf, tid, true);
 }
 
-static void avdtp_set_configuration_handler(struct bt_avdtp *session, struct net_buf *buf,
-					    uint8_t msg_type, uint8_t tid)
+static void avdtp_re_configure_rsp(struct bt_avdtp *session, struct net_buf *buf, uint8_t msg_type)
 {
-	avdtp_process_configuration(session, buf, msg_type, tid, false);
+	avdtp_process_configuration_rsp(session, buf, msg_type, true);
 }
 
-static void avdtp_get_configuration_handler(struct bt_avdtp *session, struct net_buf *buf,
-					    uint8_t msg_type, uint8_t tid)
+static void avdtp_open_cmd(struct bt_avdtp *session, struct net_buf *buf, uint8_t tid)
 {
-	/* todo: is not supported now, reply reject */
+	int err = 0;
+	struct bt_avdtp_sep *sep;
 	struct net_buf *rsp_buf;
-	int err;
+	uint8_t avdtp_err_code = 0;
+
+	sep = avdtp_get_cmd_sep(buf, &avdtp_err_code);
+	avdtp_sep_lock(sep);
 
-	rsp_buf = avdtp_create_reply_pdu(BT_AVDTP_REJECT, BT_AVDTP_PACKET_TYPE_SINGLE,
-					 BT_AVDTP_GET_CONFIGURATION, tid);
+	if ((sep == NULL) || (session->ops->open_ind == NULL)) {
+		err = -ENOTSUP;
+	} else {
+		if (sep->state != AVDTP_CONFIGURED) {
+			err = -ENOTSUP;
+			avdtp_err_code = BT_AVDTP_BAD_STATE;
+		} else {
+			err = session->ops->open_ind(session, sep, &avdtp_err_code);
+		}
+	}
+
+	rsp_buf = avdtp_create_reply_pdu(err ? BT_AVDTP_REJECT : BT_AVDTP_ACCEPT,
+					 BT_AVDTP_PACKET_TYPE_SINGLE, BT_AVDTP_OPEN, tid);
 	if (!rsp_buf) {
-		LOG_ERR("Error: No Buff available");
+		avdtp_sep_unlock(sep);
 		return;
 	}
 
+	if (err) {
+		if (avdtp_err_code == 0) {
+			avdtp_err_code = BT_AVDTP_BAD_ACP_SEID;
+		}
+
+		LOG_DBG("open_ind err code:%d", avdtp_err_code);
+		net_buf_add_u8(rsp_buf, avdtp_err_code);
+	} else {
+		session->current_sep = sep;
+	}
+
 	err = bt_l2cap_chan_send(&session->br_chan.chan, rsp_buf);
-	if (err < 0) {
+	if (err) {
 		net_buf_unref(rsp_buf);
 		LOG_ERR("Error:L2CAP send fail - result = %d", err);
-		return;
 	}
-}
 
-static void avdtp_re_configure_handler(struct bt_avdtp *session, struct net_buf *buf,
-				       uint8_t msg_type, uint8_t tid)
-{
-	avdtp_process_configuration(session, buf, msg_type, tid, true);
+	if (!err && !avdtp_err_code) {
+		bt_avdtp_set_state(sep, AVDTP_OPENING);
+	}
+
+	avdtp_sep_unlock(sep);
 }
 
-static void avdtp_open_handler(struct bt_avdtp *session, struct net_buf *buf, uint8_t msg_type,
-			       uint8_t tid)
+static void avdtp_open_rsp(struct bt_avdtp *session, struct net_buf *buf, uint8_t msg_type)
 {
-	if (msg_type == BT_AVDTP_CMD) {
-		int err = 0;
-		int ret;
-		struct bt_avdtp_sep *sep;
-		struct net_buf *rsp_buf;
-		uint8_t error_code = 0;
+	struct bt_avdtp_req *req = session->req;
 
-		sep = avdtp_get_cmd_sep(buf);
-		avdtp_sep_lock(sep);
-		if ((sep == NULL) || (session->ops->open_ind == NULL)) {
-			err = -ENOTSUP;
-		} else {
-			if (sep->state != AVDTP_CONFIGURED) {
-				err = -ENOTSUP;
-				error_code = BT_AVDTP_BAD_STATE;
-			} else {
-				err = session->ops->open_ind(session, sep, &error_code);
-			}
-		}
+	if (req == NULL) {
+		return;
+	}
 
-		rsp_buf = avdtp_create_reply_pdu(err ? BT_AVDTP_REJECT : BT_AVDTP_ACCEPT,
-						 BT_AVDTP_PACKET_TYPE_SINGLE, BT_AVDTP_OPEN, tid);
-		if (!rsp_buf) {
-			avdtp_sep_unlock(sep);
+	k_work_cancel_delayable(&session->timeout_work);
+	avdtp_set_status(req, buf, msg_type);
+
+	if (req->status == BT_AVDTP_SUCCESS) {
+		bt_avdtp_set_state_lock(CTRL_REQ(req)->sep, AVDTP_OPENING);
+
+		/* wait the media l2cap is established */
+		if (!avdtp_media_connect(session, CTRL_REQ(req)->sep)) {
 			return;
 		}
+	}
 
-		if (err) {
-			if (error_code == 0) {
-				error_code = BT_AVDTP_BAD_ACP_SEID;
-			}
-			LOG_DBG("open_ind err code:%d", error_code);
-			net_buf_add_u8(rsp_buf, error_code);
-		} else {
-			session->current_sep = sep;
-		}
+	if (req->status != BT_AVDTP_SUCCESS) {
+		bt_avdtp_clear_req(session);
 
-		ret = bt_l2cap_chan_send(&session->br_chan.chan, rsp_buf);
-		if (ret) {
-			net_buf_unref(rsp_buf);
-			LOG_ERR("Error:L2CAP send fail - result = %d", ret);
+		if (req->func != NULL) {
+			req->func(req, NULL);
 		}
+	}
+}
 
-		if (!err && !ret) {
-			bt_avdtp_set_state(sep, AVDTP_OPENING);
-		}
-		avdtp_sep_unlock(sep);
-	} else {
-		struct bt_avdtp_req *req = session->req;
+static void avdtp_handle_reject(struct net_buf *buf, struct bt_avdtp_req *req)
+{
+	if (buf->len > 1U) {
+		uint8_t acp_seid;
 
-		if (req == NULL) {
-			return;
-		}
-		k_work_cancel_delayable(&session->timeout_work);
-		avdtp_set_status(req, buf, msg_type);
-		if (msg_type == BT_AVDTP_ACCEPT) {
-			bt_avdtp_set_state_lock(CTRL_REQ(req)->sep, AVDTP_OPENING);
-			/* wait the media l2cap is established */
-			if (!avdtp_media_connect(session, CTRL_REQ(req)->sep)) {
-				return;
-			}
-		}
-		if (req->status) {
-			bt_avdtp_clear_req(session);
-			if (req->func != NULL) {
-				req->func(req);
-			}
+		acp_seid = net_buf_pull_u8(buf);
+
+		if (acp_seid != CTRL_REQ(req)->acp_stream_ep_id) {
+			req->status = BT_AVDTP_BAD_ACP_SEID;
 		}
+	} else {
+		req->status = BT_AVDTP_BAD_LENGTH;
 	}
 }
 
-static void avdtp_start_handler(struct bt_avdtp *session, struct net_buf *buf, uint8_t msg_type,
-				uint8_t tid)
+static void avdtp_start_cmd(struct bt_avdtp *session, struct net_buf *buf, uint8_t tid)
 {
-	if (msg_type == BT_AVDTP_CMD) {
-		int err = 0;
-		int ret;
-		struct bt_avdtp_sep *sep;
-		struct net_buf *rsp_buf;
-		uint8_t error_code = 0;
+	int err = 0;
+	struct bt_avdtp_sep *sep;
+	struct net_buf *rsp_buf;
+	uint8_t avdtp_err_code = 0;
+
+	sep = avdtp_get_cmd_sep(buf, &avdtp_err_code);
+	avdtp_sep_lock(sep);
 
-		sep = avdtp_get_cmd_sep(buf);
-		avdtp_sep_lock(sep);
-		if ((sep == NULL) || (session->ops->start_ind == NULL)) {
+	if ((sep == NULL) || (session->ops->start_ind == NULL)) {
+		err = -ENOTSUP;
+	} else {
+		if (sep->state != AVDTP_OPEN) {
 			err = -ENOTSUP;
+			avdtp_err_code = BT_AVDTP_BAD_STATE;
 		} else {
-			if (sep->state != AVDTP_OPEN) {
-				err = -ENOTSUP;
-				error_code = BT_AVDTP_BAD_STATE;
-			} else {
-				err = session->ops->start_ind(session, sep, &error_code);
-			}
+			err = session->ops->start_ind(session, sep, &avdtp_err_code);
 		}
+	}
 
-		rsp_buf = avdtp_create_reply_pdu(err ? BT_AVDTP_REJECT : BT_AVDTP_ACCEPT,
-						 BT_AVDTP_PACKET_TYPE_SINGLE, BT_AVDTP_START, tid);
-		if (!rsp_buf) {
-			avdtp_sep_unlock(sep);
-			return;
-		}
+	rsp_buf = avdtp_create_reply_pdu(err ? BT_AVDTP_REJECT : BT_AVDTP_ACCEPT,
+					 BT_AVDTP_PACKET_TYPE_SINGLE, BT_AVDTP_START, tid);
+	if (!rsp_buf) {
+		avdtp_sep_unlock(sep);
+		return;
+	}
 
-		if (err) {
-			if (error_code == 0) {
-				error_code = BT_AVDTP_BAD_ACP_SEID;
-			}
-			LOG_DBG("start err code:%d", error_code);
-			net_buf_add_u8(rsp_buf, error_code);
+	if (err) {
+		if (avdtp_err_code == 0) {
+			avdtp_err_code = BT_AVDTP_BAD_ACP_SEID;
 		}
 
-		ret = bt_l2cap_chan_send(&session->br_chan.chan, rsp_buf);
-		if (ret) {
-			net_buf_unref(rsp_buf);
-			LOG_ERR("Error:L2CAP send fail - result = %d", ret);
-		}
-		if (!err && !ret) {
-			bt_avdtp_set_state(sep, AVDTP_STREAMING);
-		}
-		avdtp_sep_unlock(sep);
-	} else {
-		struct bt_avdtp_req *req = session->req;
+		LOG_DBG("start err code:%d", avdtp_err_code);
+		net_buf_add_u8(rsp_buf, avdtp_err_code);
+	}
 
-		if (req == NULL) {
-			return;
-		}
-		k_work_cancel_delayable(&session->timeout_work);
-		if (msg_type == BT_AVDTP_ACCEPT) {
-			bt_avdtp_set_state_lock(CTRL_REQ(req)->sep, AVDTP_STREAMING);
-		} else if (msg_type == BT_AVDTP_REJECT) {
-			if (buf->len > 1U) {
-				uint8_t acp_seid;
-
-				acp_seid = net_buf_pull_u8(buf);
-				if (acp_seid != CTRL_REQ(req)->acp_stream_ep_id) {
-					return;
-				}
-			}
-		}
+	err = bt_l2cap_chan_send(&session->br_chan.chan, rsp_buf);
+	if (err) {
+		net_buf_unref(rsp_buf);
+		LOG_ERR("Error:L2CAP send fail - result = %d", err);
+	}
+
+	if (!err && !avdtp_err_code) {
+		bt_avdtp_set_state(sep, AVDTP_STREAMING);
+	}
+
+	avdtp_sep_unlock(sep);
+}
+
+static void avdtp_start_rsp(struct bt_avdtp *session, struct net_buf *buf, uint8_t msg_type)
+{
+	struct bt_avdtp_req *req = session->req;
+
+	if (req == NULL) {
+		return;
+	}
+
+	k_work_cancel_delayable(&session->timeout_work);
+
+	if (msg_type == BT_AVDTP_ACCEPT) {
+		bt_avdtp_set_state_lock(CTRL_REQ(req)->sep, AVDTP_STREAMING);
+	} else if (msg_type == BT_AVDTP_REJECT) {
+		avdtp_handle_reject(buf, req);
+	}
+
+	if (req->status == BT_AVDTP_SUCCESS) {
 		avdtp_set_status(req, buf, msg_type);
-		bt_avdtp_clear_req(session);
-		if (req->func != NULL) {
-			req->func(req);
-		}
+	}
+
+	bt_avdtp_clear_req(session);
+
+	if (req->func != NULL) {
+		req->func(req, NULL);
 	}
 }
 
-static void avdtp_close_handler(struct bt_avdtp *session, struct net_buf *buf, uint8_t msg_type,
-				uint8_t tid)
+static void avdtp_close_cmd(struct bt_avdtp *session, struct net_buf *buf, uint8_t tid)
 {
-	if (msg_type == BT_AVDTP_CMD) {
-		int err = 0;
-		int ret;
-		struct bt_avdtp_sep *sep;
-		struct net_buf *rsp_buf;
-		uint8_t error_code = 0;
+	int err = 0;
+	struct bt_avdtp_sep *sep;
+	struct net_buf *rsp_buf;
+	uint8_t avdtp_err_code = 0;
+
+	sep = avdtp_get_cmd_sep(buf, &avdtp_err_code);
+	avdtp_sep_lock(sep);
 
-		sep = avdtp_get_cmd_sep(buf);
-		avdtp_sep_lock(sep);
-		if ((sep == NULL) || (session->ops->close_ind == NULL)) {
+	if ((sep == NULL) || (session->ops->close_ind == NULL)) {
+		err = -ENOTSUP;
+	} else {
+		if (!(sep->state & (AVDTP_OPEN | AVDTP_STREAMING))) {
 			err = -ENOTSUP;
+			avdtp_err_code = BT_AVDTP_BAD_STATE;
 		} else {
-			if (!(sep->state & (AVDTP_OPEN | AVDTP_STREAMING))) {
-				err = -ENOTSUP;
-				error_code = BT_AVDTP_BAD_STATE;
-			} else {
-				err = session->ops->close_ind(session, sep, &error_code);
-			}
+			err = session->ops->close_ind(session, sep, &avdtp_err_code);
 		}
+	}
 
-		rsp_buf = avdtp_create_reply_pdu(err ? BT_AVDTP_REJECT : BT_AVDTP_ACCEPT,
-						 BT_AVDTP_PACKET_TYPE_SINGLE, BT_AVDTP_CLOSE, tid);
-		if (!rsp_buf) {
-			avdtp_sep_unlock(sep);
-			return;
-		}
+	rsp_buf = avdtp_create_reply_pdu(err ? BT_AVDTP_REJECT : BT_AVDTP_ACCEPT,
+					 BT_AVDTP_PACKET_TYPE_SINGLE, BT_AVDTP_CLOSE, tid);
+	if (!rsp_buf) {
+		avdtp_sep_unlock(sep);
+		return;
+	}
 
-		if (err) {
-			if (error_code == 0) {
-				error_code = BT_AVDTP_BAD_ACP_SEID;
-			}
-			LOG_DBG("close err code:%d", error_code);
-			net_buf_add_u8(rsp_buf, error_code);
-		} else {
-			bt_avdtp_set_state(sep, AVDTP_CLOSING);
+	if (err) {
+		if (avdtp_err_code == 0) {
+			avdtp_err_code = BT_AVDTP_BAD_ACP_SEID;
 		}
 
-		ret = bt_l2cap_chan_send(&session->br_chan.chan, rsp_buf);
-		if (ret) {
-			net_buf_unref(rsp_buf);
-			LOG_ERR("Error:L2CAP send fail - result = %d", ret);
-		}
-		if (!err && !ret) {
-			bt_avdtp_set_state(sep, AVDTP_IDLE);
-		}
-		avdtp_sep_unlock(sep);
+		LOG_DBG("close err code:%d", avdtp_err_code);
+		net_buf_add_u8(rsp_buf, avdtp_err_code);
 	} else {
-		struct bt_avdtp_req *req = session->req;
+		bt_avdtp_set_state(sep, AVDTP_CLOSING);
+	}
+
+	err = bt_l2cap_chan_send(&session->br_chan.chan, rsp_buf);
+	if (err) {
+		net_buf_unref(rsp_buf);
+		LOG_ERR("Error:L2CAP send fail - result = %d", err);
+	}
+
+	if (!err && !avdtp_err_code) {
+		bt_avdtp_set_state(sep, AVDTP_IDLE);
+	}
+
+	avdtp_sep_unlock(sep);
+}
 
-		if (req == NULL) {
+static void avdtp_close_rsp(struct bt_avdtp *session, struct net_buf *buf, uint8_t msg_type)
+{
+	struct bt_avdtp_req *req = session->req;
+
+	if (req == NULL) {
+		return;
+	}
+
+	k_work_cancel_delayable(&session->timeout_work);
+	avdtp_set_status(req, buf, msg_type);
+
+	if (req->status == BT_AVDTP_SUCCESS) {
+		bt_avdtp_set_state_lock(CTRL_REQ(req)->sep, AVDTP_CLOSING);
+
+		if (!avdtp_media_disconnect(CTRL_REQ(req)->sep)) {
 			return;
 		}
-		k_work_cancel_delayable(&session->timeout_work);
-		avdtp_set_status(req, buf, msg_type);
-		if (msg_type == BT_AVDTP_ACCEPT) {
-			bt_avdtp_set_state_lock(CTRL_REQ(req)->sep, AVDTP_CLOSING);
-			if (!avdtp_media_disconnect(CTRL_REQ(req)->sep)) {
-				return;
-			}
-		}
-		bt_avdtp_clear_req(session);
-		if (req->func != NULL) {
-			req->func(req);
-		}
+	}
+
+	bt_avdtp_clear_req(session);
+
+	if (req->func != NULL) {
+		req->func(req, NULL);
 	}
 }
 
-static void avdtp_suspend_handler(struct bt_avdtp *session, struct net_buf *buf, uint8_t msg_type,
-				  uint8_t tid)
+static void avdtp_suspend_cmd(struct bt_avdtp *session, struct net_buf *buf, uint8_t tid)
 {
-	if (msg_type == BT_AVDTP_CMD) {
-		int err = 0;
-		int ret;
-		struct bt_avdtp_sep *sep;
-		struct net_buf *rsp_buf;
-		uint8_t error_code = 0;
+	int err = 0;
+	struct bt_avdtp_sep *sep;
+	struct net_buf *rsp_buf;
+	uint8_t avdtp_err_code = 0;
+
+	sep = avdtp_get_cmd_sep(buf, &avdtp_err_code);
+	avdtp_sep_lock(sep);
 
-		sep = avdtp_get_cmd_sep(buf);
-		avdtp_sep_lock(sep);
-		if ((sep == NULL) || (session->ops->suspend_ind == NULL)) {
+	if ((sep == NULL) || (session->ops->suspend_ind == NULL)) {
+		err = -ENOTSUP;
+	} else {
+		if (sep->state != AVDTP_STREAMING) {
 			err = -ENOTSUP;
+			avdtp_err_code = BT_AVDTP_BAD_STATE;
 		} else {
-			if (sep->state != AVDTP_STREAMING) {
-				err = -ENOTSUP;
-				error_code = BT_AVDTP_BAD_STATE;
-			} else {
-				err = session->ops->suspend_ind(session, sep, &error_code);
-			}
+			err = session->ops->suspend_ind(session, sep, &avdtp_err_code);
 		}
+	}
 
-		rsp_buf =
-			avdtp_create_reply_pdu(err ? BT_AVDTP_REJECT : BT_AVDTP_ACCEPT,
-					       BT_AVDTP_PACKET_TYPE_SINGLE, BT_AVDTP_SUSPEND, tid);
-		if (!rsp_buf) {
-			avdtp_sep_unlock(sep);
-			return;
-		}
+	rsp_buf = avdtp_create_reply_pdu(err ? BT_AVDTP_REJECT : BT_AVDTP_ACCEPT,
+					 BT_AVDTP_PACKET_TYPE_SINGLE, BT_AVDTP_SUSPEND, tid);
+	if (!rsp_buf) {
+		avdtp_sep_unlock(sep);
+		return;
+	}
 
-		if (err) {
-			if (error_code == 0) {
-				error_code = BT_AVDTP_BAD_ACP_SEID;
-			}
-			LOG_DBG("suspend err code:%d", error_code);
-			net_buf_add_u8(rsp_buf, error_code);
+	if (err) {
+		if (avdtp_err_code == 0) {
+			avdtp_err_code = BT_AVDTP_BAD_ACP_SEID;
 		}
 
-		ret = bt_l2cap_chan_send(&session->br_chan.chan, rsp_buf);
-		if (ret) {
-			net_buf_unref(rsp_buf);
-			LOG_ERR("Error:L2CAP send fail - result = %d", ret);
-		}
-		if (!err && !ret) {
-			bt_avdtp_set_state(sep, AVDTP_OPEN);
-		}
-		avdtp_sep_unlock(sep);
-	} else {
-		struct bt_avdtp_req *req = session->req;
+		LOG_DBG("suspend err code:%d", avdtp_err_code);
+		net_buf_add_u8(rsp_buf, avdtp_err_code);
+	}
 
-		if (req == NULL) {
-			return;
-		}
-		k_work_cancel_delayable(&session->timeout_work);
-		if (msg_type == BT_AVDTP_ACCEPT) {
-			bt_avdtp_set_state_lock(CTRL_REQ(req)->sep, AVDTP_OPEN);
-		} else if (msg_type == BT_AVDTP_REJECT) {
-			if (buf->len >= 1U) {
-				uint8_t acp_seid;
-
-				acp_seid = net_buf_pull_u8(buf);
-				if (acp_seid != CTRL_REQ(req)->acp_stream_ep_id) {
-					return;
-				}
-			}
-		}
+	err = bt_l2cap_chan_send(&session->br_chan.chan, rsp_buf);
+	if (err) {
+		net_buf_unref(rsp_buf);
+		LOG_ERR("Error:L2CAP send fail - result = %d", err);
+	}
+
+	if (!err && !avdtp_err_code) {
+		bt_avdtp_set_state(sep, AVDTP_OPEN);
+	}
+
+	avdtp_sep_unlock(sep);
+}
+
+static void avdtp_suspend_rsp(struct bt_avdtp *session, struct net_buf *buf, uint8_t msg_type)
+{
+	struct bt_avdtp_req *req = session->req;
+
+	if (req == NULL) {
+		return;
+	}
+
+	k_work_cancel_delayable(&session->timeout_work);
+
+	if (msg_type == BT_AVDTP_ACCEPT) {
+		bt_avdtp_set_state_lock(CTRL_REQ(req)->sep, AVDTP_OPEN);
+	} else if (msg_type == BT_AVDTP_REJECT) {
+		avdtp_handle_reject(buf, req);
+	}
+
+	if (req->status == BT_AVDTP_SUCCESS) {
 		avdtp_set_status(req, buf, msg_type);
-		bt_avdtp_clear_req(session);
-		if (req->func != NULL) {
-			req->func(req);
-		}
+	}
+
+	bt_avdtp_clear_req(session);
+
+	if (req->func != NULL) {
+		req->func(req, NULL);
 	}
 }
 
-static void avdtp_abort_handler(struct bt_avdtp *session, struct net_buf *buf, uint8_t msg_type,
-				uint8_t tid)
+static void avdtp_abort_cmd(struct bt_avdtp *session, struct net_buf *buf, uint8_t tid)
 {
-	if (msg_type == BT_AVDTP_CMD) {
-		int err = 0;
-		int ret;
-		struct bt_avdtp_sep *sep;
-		struct net_buf *rsp_buf;
-		uint8_t error_code = 0;
+	int err = 0;
+	struct bt_avdtp_sep *sep;
+	struct net_buf *rsp_buf;
+	uint8_t avdtp_err_code = 0;
 
-		sep = avdtp_get_cmd_sep(buf);
-		avdtp_sep_lock(sep);
-		if ((sep == NULL) || (session->ops->abort_ind == NULL)) {
-			err = -ENOTSUP;
-		} else {
-			/* all current sep state is OK for abort operation */
-			err = session->ops->abort_ind(session, sep, &error_code);
-		}
+	sep = avdtp_get_cmd_sep(buf, &avdtp_err_code);
+	avdtp_sep_lock(sep);
 
-		rsp_buf = avdtp_create_reply_pdu(err ? BT_AVDTP_REJECT : BT_AVDTP_ACCEPT,
-						 BT_AVDTP_PACKET_TYPE_SINGLE, BT_AVDTP_ABORT, tid);
-		if (!rsp_buf) {
-			avdtp_sep_unlock(sep);
-			return;
-		}
+	if ((sep == NULL) || (session->ops->abort_ind == NULL)) {
+		err = -ENOTSUP;
+	} else {
+		/* all current sep state is OK for abort operation */
+		err = session->ops->abort_ind(session, sep, &avdtp_err_code);
+	}
 
-		if (err) {
-			if (error_code == 0) {
-				error_code = BT_AVDTP_BAD_ACP_SEID;
-			}
-			LOG_DBG("abort err code:%d", error_code);
-			net_buf_add_u8(rsp_buf, error_code);
-		}
+	rsp_buf = avdtp_create_reply_pdu(err ? BT_AVDTP_REJECT : BT_AVDTP_ACCEPT,
+					 BT_AVDTP_PACKET_TYPE_SINGLE, BT_AVDTP_ABORT, tid);
+	if (!rsp_buf) {
+		avdtp_sep_unlock(sep);
+		return;
+	}
 
-		ret = bt_l2cap_chan_send(&session->br_chan.chan, rsp_buf);
-		if (ret) {
-			net_buf_unref(rsp_buf);
-			LOG_ERR("Error:L2CAP send fail - result = %d", ret);
-		}
-		if (!err && !ret) {
-			if ((sep->state & (AVDTP_OPEN | AVDTP_STREAMING)) &&
-			    (sep->chan.state == BT_L2CAP_CONNECTED)) {
-				bt_avdtp_set_state(sep, AVDTP_ABORTING);
-			} else {
-				bt_avdtp_set_state(sep, AVDTP_IDLE);
-			}
+	if (err) {
+		if (avdtp_err_code == 0) {
+			avdtp_err_code = BT_AVDTP_BAD_ACP_SEID;
 		}
-		avdtp_sep_unlock(sep);
-	} else {
-		struct bt_avdtp_req *req = session->req;
 
-		if (req == NULL) {
-			return;
+		LOG_DBG("abort err code:%d", avdtp_err_code);
+		net_buf_add_u8(rsp_buf, avdtp_err_code);
+	}
+
+	err = bt_l2cap_chan_send(&session->br_chan.chan, rsp_buf);
+	if (err) {
+		net_buf_unref(rsp_buf);
+		LOG_ERR("Error:L2CAP send fail - result = %d", err);
+	}
+
+	if (!err && !avdtp_err_code) {
+		if ((sep->state & (AVDTP_OPEN | AVDTP_STREAMING)) &&
+		    (sep->chan.state == BT_L2CAP_CONNECTED)) {
+			bt_avdtp_set_state(sep, AVDTP_ABORTING);
+		} else {
+			bt_avdtp_set_state(sep, AVDTP_IDLE);
 		}
-		k_work_cancel_delayable(&session->timeout_work);
-		if (msg_type == BT_AVDTP_ACCEPT) {
-			uint8_t pre_state = CTRL_REQ(req)->sep->state;
-
-			bt_avdtp_set_state_lock(CTRL_REQ(req)->sep, AVDTP_ABORTING);
-			/* release stream */
-			if (pre_state & (AVDTP_OPEN | AVDTP_STREAMING)) {
-				avdtp_media_disconnect(CTRL_REQ(req)->sep);
-			}
+	}
 
-			/* For abort, make sure the state revert to IDLE state after
-			 * releasing l2cap channel.
-			 */
-			bt_avdtp_set_state_lock(CTRL_REQ(req)->sep, AVDTP_IDLE);
-		} else if (msg_type == BT_AVDTP_REJECT) {
-			if (buf->len >= 1U) {
-				uint8_t acp_seid;
-
-				acp_seid = net_buf_pull_u8(buf);
-				if (acp_seid != CTRL_REQ(req)->acp_stream_ep_id) {
-					return;
-				}
-			}
+	avdtp_sep_unlock(sep);
+}
+
+static void avdtp_abort_rsp(struct bt_avdtp *session, struct net_buf *buf, uint8_t msg_type)
+{
+	struct bt_avdtp_req *req = session->req;
+
+	if (req == NULL) {
+		return;
+	}
+
+	k_work_cancel_delayable(&session->timeout_work);
+
+	if (msg_type == BT_AVDTP_ACCEPT) {
+		uint8_t pre_state = CTRL_REQ(req)->sep->state;
+
+		bt_avdtp_set_state_lock(CTRL_REQ(req)->sep, AVDTP_ABORTING);
+
+		/* release stream */
+		if (pre_state & (AVDTP_OPEN | AVDTP_STREAMING)) {
+			avdtp_media_disconnect(CTRL_REQ(req)->sep);
 		}
+
+		/* For abort, make sure the state revert to IDLE state after
+		 * releasing l2cap channel.
+		 */
+		bt_avdtp_set_state_lock(CTRL_REQ(req)->sep, AVDTP_IDLE);
+	} else if (msg_type == BT_AVDTP_REJECT) {
+		avdtp_handle_reject(buf, req);
+	}
+
+	if (req->status == BT_AVDTP_SUCCESS) {
 		avdtp_set_status(req, buf, msg_type);
-		bt_avdtp_clear_req(session);
-		if (req->func != NULL) {
-			req->func(req);
-		}
+	}
+
+	bt_avdtp_clear_req(session);
+
+	if (req->func != NULL) {
+		req->func(req, NULL);
 	}
 }
 
@@ -959,7 +1000,7 @@ static void avdtp_timeout(struct k_work *work)
 		case BT_AVDTP_START:
 		case BT_AVDTP_SUSPEND:
 			req->status = BT_AVDTP_TIME_OUT;
-			req->func(req);
+			req->func(req, NULL);
 			break;
 		default:
 			break;
@@ -975,10 +1016,12 @@ static int avdtp_send(struct bt_avdtp *session, struct net_buf *buf, struct bt_a
 	struct bt_avdtp_single_sig_hdr *hdr;
 
 	avdtp_lock(session);
+
 	if (session->req != NULL) {
 		avdtp_unlock(session);
 		return -EBUSY;
 	}
+
 	session->req = req;
 	avdtp_unlock(session);
 	hdr = (struct bt_avdtp_single_sig_hdr *)buf->data;
@@ -986,7 +1029,6 @@ static int avdtp_send(struct bt_avdtp *session, struct net_buf *buf, struct bt_a
 	result = bt_l2cap_chan_send(&session->br_chan.chan, buf);
 	if (result < 0) {
 		LOG_ERR("Error:L2CAP send fail - result = %d", result);
-		net_buf_unref(buf);
 		bt_avdtp_clear_req(session);
 		return result;
 	}
@@ -1052,8 +1094,9 @@ void bt_avdtp_l2cap_disconnected(struct bt_l2cap_chan *chan)
 
 		req->status = BT_AVDTP_BAD_STATE;
 		bt_avdtp_clear_req(session);
+
 		if (req->func != NULL) {
-			req->func(req);
+			req->func(req, NULL);
 		}
 	}
 
@@ -1061,27 +1104,45 @@ void bt_avdtp_l2cap_disconnected(struct bt_l2cap_chan *chan)
 	session->ops->disconnected(session);
 }
 
-static const struct {
-	uint8_t sig_id;
-	void (*func)(struct bt_avdtp *session, struct net_buf *buf, uint8_t msg_type, uint8_t tid);
-} handler[] = {
-	{BT_AVDTP_DISCOVER, avdtp_discover_handler},
-	{BT_AVDTP_GET_CAPABILITIES, avdtp_get_capabilities_handler},
-	{BT_AVDTP_SET_CONFIGURATION, avdtp_set_configuration_handler},
-	{BT_AVDTP_GET_CONFIGURATION, avdtp_get_configuration_handler},
-	{BT_AVDTP_RECONFIGURE, avdtp_re_configure_handler},
-	{BT_AVDTP_OPEN, avdtp_open_handler},
-	{BT_AVDTP_START, avdtp_start_handler},
-	{BT_AVDTP_CLOSE, avdtp_close_handler},
-	{BT_AVDTP_SUSPEND, avdtp_suspend_handler},
-	{BT_AVDTP_ABORT, avdtp_abort_handler},
+void (*cmd_handler[])(struct bt_avdtp *session, struct net_buf *buf, uint8_t tid) = {
+	avdtp_discover_cmd,          /* BT_AVDTP_DISCOVER */
+	avdtp_get_capabilities_cmd,  /* BT_AVDTP_GET_CAPABILITIES */
+	avdtp_set_configuration_cmd, /* BT_AVDTP_SET_CONFIGURATION */
+	NULL,                        /* BT_AVDTP_GET_CONFIGURATION */
+	avdtp_re_configure_cmd,      /* BT_AVDTP_RECONFIGURE */
+	avdtp_open_cmd,              /* BT_AVDTP_OPEN */
+	avdtp_start_cmd,             /* BT_AVDTP_START */
+	avdtp_close_cmd,             /* BT_AVDTP_CLOSE */
+	avdtp_suspend_cmd,           /* BT_AVDTP_SUSPEND */
+	avdtp_abort_cmd,             /* BT_AVDTP_ABORT */
+	NULL,                        /* BT_AVDTP_SECURITY_CONTROL */
+	NULL,                        /* BT_AVDTP_GET_ALL_CAPABILITIES */
+	NULL,                        /* BT_AVDTP_DELAYREPORT */
+};
+
+void (*rsp_handler[])(struct bt_avdtp *session, struct net_buf *buf, uint8_t msg_type) = {
+	avdtp_discover_rsp,          /* BT_AVDTP_DISCOVER */
+	avdtp_get_capabilities_rsp,  /* BT_AVDTP_GET_CAPABILITIES */
+	avdtp_set_configuration_rsp, /* BT_AVDTP_SET_CONFIGURATION */
+	NULL,                        /* BT_AVDTP_GET_CONFIGURATION */
+	avdtp_re_configure_rsp,      /* BT_AVDTP_RECONFIGURE */
+	avdtp_open_rsp,              /* BT_AVDTP_OPEN */
+	avdtp_start_rsp,             /* BT_AVDTP_START */
+	avdtp_close_rsp,             /* BT_AVDTP_CLOSE */
+	avdtp_suspend_rsp,           /* BT_AVDTP_SUSPEND */
+	avdtp_abort_rsp,             /* BT_AVDTP_ABORT */
+	NULL,                        /* BT_AVDTP_SECURITY_CONTROL */
+	NULL,                        /* BT_AVDTP_GET_ALL_CAPABILITIES */
+	NULL,                        /* BT_AVDTP_DELAYREPORT */
 };
 
 int bt_avdtp_l2cap_recv(struct bt_l2cap_chan *chan, struct net_buf *buf)
 {
 	struct bt_avdtp_single_sig_hdr *hdr;
 	struct bt_avdtp *session = AVDTP_CHAN(chan);
-	uint8_t i, msgtype, pack_type, sigid, tid;
+	uint8_t msgtype, pack_type, sigid, tid;
+	struct net_buf *rsp_buf;
+	int err;
 
 	if (buf->len < sizeof(*hdr)) {
 		LOG_ERR("Recvd Wrong AVDTP Header");
@@ -1100,30 +1161,27 @@ int bt_avdtp_l2cap_recv(struct bt_l2cap_chan *chan, struct net_buf *buf)
 	/* TODO: only support single packet now */
 	if (pack_type != BT_AVDTP_PACKET_TYPE_SINGLE) {
 		if (pack_type == BT_AVDTP_PACKET_TYPE_START) {
-			struct net_buf *rsp_buf;
-			int err;
-
 			if (buf->len < 1U) {
 				return -EINVAL;
 			}
+
 			sigid = net_buf_pull_u8(buf);
-			rsp_buf = avdtp_create_reply_pdu(BT_AVDTP_REJECT,
-							 BT_AVDTP_PACKET_TYPE_SINGLE, sigid, tid);
-			if (!rsp_buf) {
-				LOG_ERR("Error: No Buff available");
-				return -EINVAL;
-			}
-			err = bt_l2cap_chan_send(&session->br_chan.chan, rsp_buf);
-			if (err < 0) {
-				net_buf_unref(rsp_buf);
-				LOG_ERR("Error:L2CAP send fail - result = %d", err);
-			}
+			goto send_reject;
 		}
-		return 0;
+
+		/* discard the continue packet and end packet */
+		return -EINVAL;
 	}
 
-	/* validate if there is an outstanding resp expected*/
-	if (msgtype != BT_AVDTP_CMD) {
+	if (msgtype == BT_AVDTP_CMD) {
+		if (sigid != 0U && sigid <= BT_AVDTP_DELAYREPORT &&
+		    cmd_handler[sigid - 1U] != NULL) {
+			cmd_handler[sigid - 1U](session, buf, tid);
+			return 0;
+		}
+		/* goto send_reject; */
+	} else {
+		/* validate if the response is expected*/
 		if (session->req == NULL) {
 			LOG_DBG("Unexpected peer response");
 			return -EINVAL;
@@ -1135,16 +1193,32 @@ int bt_avdtp_l2cap_recv(struct bt_l2cap_chan *chan, struct net_buf *buf)
 				session->req->sig, session->req->tid);
 			return -EINVAL;
 		}
-	}
 
-	for (i = 0U; i < ARRAY_SIZE(handler); i++) {
-		if (sigid == handler[i].sig_id) {
-			handler[i].func(session, buf, msgtype, tid);
+		if (sigid != 0U && sigid <= BT_AVDTP_DELAYREPORT &&
+		    cmd_handler[sigid - 1U] != NULL) {
+			rsp_handler[sigid - 1U](session, buf, msgtype);
 			return 0;
 		}
+
+		/* discard unsupported response packet */
+		return -EINVAL;
 	}
 
-	return 0;
+send_reject:
+	rsp_buf = avdtp_create_reply_pdu(BT_AVDTP_GEN_REJECT, BT_AVDTP_PACKET_TYPE_SINGLE, sigid,
+					 tid);
+	if (!rsp_buf) {
+		LOG_ERR("Error: No Buff available");
+		return -EINVAL;
+	}
+
+	err = bt_l2cap_chan_send(&session->br_chan.chan, rsp_buf);
+	if (err < 0) {
+		net_buf_unref(rsp_buf);
+		LOG_ERR("Error:L2CAP send fail - result = %d", err);
+	}
+
+	return err;
 }
 
 static const struct bt_l2cap_chan_ops signal_chan_ops = {
@@ -1166,10 +1240,12 @@ int bt_avdtp_connect(struct bt_conn *conn, struct bt_avdtp *session)
 	 * The whole `session` is cleared by upper layer if it is new l2cap connection.
 	 */
 	k_sem_take(&avdtp_sem_lock, K_FOREVER);
+
 	if (session->br_chan.chan.conn != NULL) {
 		k_sem_give(&avdtp_sem_lock);
 		return -ENOMEM;
 	}
+
 	session->br_chan.chan.conn = conn;
 	k_sem_give(&avdtp_sem_lock);
 	/* Locking semaphore initialized to 1 (unlocked) */
@@ -1211,6 +1287,7 @@ int bt_avdtp_l2cap_accept(struct bt_conn *conn, struct bt_l2cap_server *server,
 	 * The whole `session` is cleared by upper layer if it is new l2cap connection.
 	 */
 	k_sem_take(&avdtp_sem_lock, K_FOREVER);
+
 	if (session->br_chan.chan.conn == NULL) {
 		session->br_chan.chan.conn = conn;
 		k_sem_give(&avdtp_sem_lock);
@@ -1221,6 +1298,7 @@ int bt_avdtp_l2cap_accept(struct bt_conn *conn, struct bt_l2cap_server *server,
 		*chan = &session->br_chan.chan;
 	} else {
 		k_sem_give(&avdtp_sem_lock);
+
 		/* get the current opening endpoint */
 		if (session->current_sep != NULL) {
 			session->current_sep->session = session;
@@ -1306,6 +1384,7 @@ int bt_avdtp_init(void)
 int bt_avdtp_discover(struct bt_avdtp *session, struct bt_avdtp_discover_params *param)
 {
 	struct net_buf *buf;
+	int err;
 
 	LOG_DBG("");
 	if (!param || !session) {
@@ -1319,7 +1398,12 @@ int bt_avdtp_discover(struct bt_avdtp *session, struct bt_avdtp_discover_params
 		return -ENOMEM;
 	}
 
-	return avdtp_send(session, buf, &param->req);
+	err = avdtp_send(session, buf, &param->req);
+	if (err) {
+		net_buf_unref(buf);
+	}
+
+	return err;
 }
 
 int bt_avdtp_parse_sep(struct net_buf *buf, struct bt_avdtp_sep_info *sep_info)
@@ -1345,6 +1429,7 @@ int bt_avdtp_get_capabilities(struct bt_avdtp *session,
 			      struct bt_avdtp_get_capabilities_params *param)
 {
 	struct net_buf *buf;
+	int err;
 
 	LOG_DBG("");
 	if (!param || !session) {
@@ -1362,7 +1447,12 @@ int bt_avdtp_get_capabilities(struct bt_avdtp *session,
 	/* Body of the message */
 	net_buf_add_u8(buf, (param->stream_endpoint_id << 2U));
 
-	return avdtp_send(session, buf, &param->req);
+	err = avdtp_send(session, buf, &param->req);
+	if (err) {
+		net_buf_unref(buf);
+	}
+
+	return err;
 }
 
 int bt_avdtp_parse_capability_codec(struct net_buf *buf, uint8_t *codec_type,
@@ -1395,6 +1485,7 @@ int bt_avdtp_parse_capability_codec(struct net_buf *buf, uint8_t *codec_type,
 				if (buf->len < length) {
 					return -EINVAL;
 				}
+
 				net_buf_pull_mem(buf, length);
 			}
 			break;
@@ -1433,6 +1524,7 @@ static int avdtp_process_configure_command(struct bt_avdtp *session, uint8_t cmd
 					   struct bt_avdtp_set_configuration_params *param)
 {
 	struct net_buf *buf;
+	int err;
 
 	LOG_DBG("");
 	if (!param || !session) {
@@ -1466,7 +1558,12 @@ static int avdtp_process_configure_command(struct bt_avdtp *session, uint8_t cmd
 	/* Codec Info Element */
 	net_buf_add_mem(buf, param->codec_specific_ie, param->codec_specific_ie_len);
 
-	return avdtp_send(session, buf, &param->req);
+	err = avdtp_send(session, buf, &param->req);
+	if (err) {
+		net_buf_unref(buf);
+	}
+
+	return err;
 }
 
 int bt_avdtp_set_configuration(struct bt_avdtp *session,
@@ -1502,6 +1599,7 @@ static int bt_avdtp_ctrl(struct bt_avdtp *session, struct bt_avdtp_ctrl_params *
 			 uint8_t check_state)
 {
 	struct net_buf *buf;
+	int err;
 
 	LOG_DBG("");
 	if (!param || !session || !param->sep) {
@@ -1523,7 +1621,12 @@ static int bt_avdtp_ctrl(struct bt_avdtp *session, struct bt_avdtp_ctrl_params *
 	/* ACP Stream Endpoint ID */
 	net_buf_add_u8(buf, (param->acp_stream_ep_id << 2U));
 
-	return avdtp_send(session, buf, &param->req);
+	err = avdtp_send(session, buf, &param->req);
+	if (err) {
+		net_buf_unref(buf);
+	}
+
+	return err;
 }
 
 int bt_avdtp_open(struct bt_avdtp *session, struct bt_avdtp_ctrl_params *param)
diff --git a/subsys/bluetooth/host/classic/avdtp_internal.h b/subsys/bluetooth/host/classic/avdtp_internal.h
index 86b3c7a2bc7..368dba6c278 100644
--- a/subsys/bluetooth/host/classic/avdtp_internal.h
+++ b/subsys/bluetooth/host/classic/avdtp_internal.h
@@ -111,7 +111,7 @@ struct bt_avdtp_sep_data {
 #endif
 } __packed;
 
-typedef int (*bt_avdtp_func_t)(struct bt_avdtp_req *req);
+typedef int (*bt_avdtp_func_t)(struct bt_avdtp_req *req, struct net_buf *buf);
 
 struct bt_avdtp_req {
 	uint8_t sig;
@@ -148,13 +148,11 @@ struct bt_avdtp_media_hdr {
 
 struct bt_avdtp_discover_params {
 	struct bt_avdtp_req req;
-	struct net_buf *buf;
 };
 
 struct bt_avdtp_get_capabilities_params {
 	struct bt_avdtp_req req;
 	uint8_t stream_endpoint_id;
-	struct net_buf *buf;
 };
 
 struct bt_avdtp_set_configuration_params {
diff --git a/subsys/bluetooth/host/classic/avrcp.c b/subsys/bluetooth/host/classic/avrcp.c
index 049bc84a358..5af99be3149 100644
--- a/subsys/bluetooth/host/classic/avrcp.c
+++ b/subsys/bluetooth/host/classic/avrcp.c
@@ -33,21 +33,14 @@ LOG_MODULE_REGISTER(bt_avrcp);
 
 struct bt_avrcp {
 	struct bt_avctp session;
-	struct bt_avrcp_req req;
-	struct k_work_delayable timeout_work;
-	uint8_t local_tid;
 };
 
 struct avrcp_handler {
 	bt_avrcp_opcode_t opcode;
-	void (*func)(struct bt_avrcp *avrcp, struct net_buf *buf, bt_avctp_cr_t cr);
+	void (*func)(struct bt_avrcp *avrcp, uint8_t tid, struct net_buf *buf, bt_avctp_cr_t cr);
 };
 
-#define AVRCP_TIMEOUT       K_SECONDS(3) /* Shell be greater than TMTP (1000ms) */
 #define AVRCP_AVCTP(_avctp) CONTAINER_OF(_avctp, struct bt_avrcp, session)
-#define AVRCP_KWORK(_work)                                                                         \
-	CONTAINER_OF(CONTAINER_OF(_work, struct k_work_delayable, work), struct bt_avrcp,          \
-		     timeout_work)
 
 static const struct bt_avrcp_cb *avrcp_cb;
 static struct bt_avrcp avrcp_connection[CONFIG_BT_MAX_CONN];
@@ -214,13 +207,6 @@ static struct bt_avrcp *get_new_connection(struct bt_conn *conn)
 	return avrcp;
 }
 
-static void avrcp_timeout(struct k_work *work)
-{
-	struct bt_avrcp *avrcp = AVRCP_KWORK(work);
-
-	LOG_WRN("Timeout: tid 0x%X, opc 0x%02X", avrcp->req.tid, avrcp->req.opcode);
-}
-
 /* The AVCTP L2CAP channel established */
 static void avrcp_connected(struct bt_avctp *session)
 {
@@ -229,8 +215,6 @@ static void avrcp_connected(struct bt_avctp *session)
 	if ((avrcp_cb != NULL) && (avrcp_cb->connected != NULL)) {
 		avrcp_cb->connected(avrcp);
 	}
-
-	k_work_init_delayable(&avrcp->timeout_work, avrcp_timeout);
 }
 
 /* The AVCTP L2CAP channel released */
@@ -243,48 +227,133 @@ static void avrcp_disconnected(struct bt_avctp *session)
 	}
 }
 
-static void avrcp_vendor_dependent_handler(struct bt_avrcp *avrcp, struct net_buf *buf,
+static void process_get_cap_rsp(struct bt_avrcp *avrcp, uint8_t tid, struct net_buf *buf)
+{
+	struct bt_avrcp_avc_pdu *pdu;
+	struct bt_avrcp_get_cap_rsp *rsp;
+	uint16_t len;
+	uint16_t expected_len;
+
+	if (buf->len < sizeof(*pdu)) {
+		LOG_ERR("Invalid vendor payload length: %d", buf->len);
+		return;
+	}
+
+	pdu = net_buf_pull_mem(buf, sizeof(*pdu));
+
+	if (BT_AVRCP_AVC_PDU_GET_PACKET_TYPE(pdu) != BT_AVRVP_PKT_TYPE_SINGLE) {
+		LOG_ERR("Invalid packet type");
+		return;
+	}
+
+	len = sys_be16_to_cpu(pdu->param_len);
+
+	if (len < sizeof(*rsp) || buf->len < len) {
+		LOG_ERR("Invalid capability length: %d, buf length = %d", len, buf->len);
+		return;
+	}
+
+	if ((avrcp_cb == NULL) || (avrcp_cb->get_cap_rsp == NULL)) {
+		return;
+	}
+
+	rsp = (struct bt_avrcp_get_cap_rsp *)buf->data;
+
+	switch (rsp->cap_id) {
+	case BT_AVRCP_CAP_COMPANY_ID:
+		expected_len = rsp->cap_cnt * BT_AVRCP_COMPANY_ID_SIZE;
+		break;
+	case BT_AVRCP_CAP_EVENTS_SUPPORTED:
+		expected_len = rsp->cap_cnt;
+		break;
+	default:
+		LOG_ERR("Unrecognized capability = 0x%x", rsp->cap_id);
+		return;
+	}
+
+	if (buf->len < sizeof(*rsp) + expected_len) {
+		LOG_ERR("Invalid capability payload length: %d", buf->len);
+		return;
+	}
+
+	avrcp_cb->get_cap_rsp(avrcp, tid, rsp);
+}
+
+static void avrcp_vendor_dependent_handler(struct bt_avrcp *avrcp, uint8_t tid, struct net_buf *buf,
 					   bt_avctp_cr_t cr)
 {
-	/* ToDo */
+	struct bt_avrcp_avc_pdu *pdu;
+	struct bt_avrcp_header *avrcp_hdr;
+	uint32_t company_id;
+	uint8_t pdu_id;
+
+	if (buf->len < (sizeof(*avrcp_hdr) + BT_AVRCP_COMPANY_ID_SIZE + sizeof(pdu_id))) {
+		LOG_ERR("Invalid vendor frame length: %d", buf->len);
+		return;
+	}
+
+	avrcp_hdr = net_buf_pull_mem(buf, sizeof(*avrcp_hdr));
+	company_id = net_buf_pull_be24(buf);
+	if (company_id != BT_AVRCP_COMPANY_ID_BLUETOOTH_SIG) {
+		LOG_ERR("Invalid company id: 0x%06x", company_id);
+		return;
+	}
+
+	pdu = (struct bt_avrcp_avc_pdu *)buf->data;
+
+	if (cr == BT_AVCTP_CMD) {
+		LOG_DBG("Unhandled command: 0x%02x", pdu->pdu_id);
+	} else { /* BT_AVCTP_RESPONSE */
+		switch (pdu->pdu_id) {
+		case BT_AVRCP_PDU_ID_GET_CAPS:
+			process_get_cap_rsp(avrcp, tid, buf);
+			break;
+		default:
+			LOG_DBG("Unhandled response: 0x%02x", pdu->pdu_id);
+			break;
+		}
+	}
 }
 
-static void avrcp_unit_info_handler(struct bt_avrcp *avrcp, struct net_buf *buf, bt_avctp_cr_t cr)
+static void avrcp_unit_info_handler(struct bt_avrcp *avrcp, uint8_t tid, struct net_buf *buf,
+				    bt_avctp_cr_t cr)
 {
 	struct bt_avrcp_header *avrcp_hdr;
 	struct bt_avrcp_unit_info_rsp rsp;
 
+	avrcp_hdr = net_buf_pull_mem(buf, sizeof(*avrcp_hdr));
+
 	if (cr == BT_AVCTP_CMD) {
 		/* ToDo */
 	} else { /* BT_AVCTP_RESPONSE */
 		if ((avrcp_cb != NULL) && (avrcp_cb->unit_info_rsp != NULL)) {
-			net_buf_pull(buf, sizeof(*avrcp_hdr));
 			if (buf->len != 5) {
-				LOG_ERR("Invalid unit info length");
+				LOG_ERR("Invalid unit info length: %d", buf->len);
 				return;
 			}
 			net_buf_pull_u8(buf); /* Always 0x07 */
 			rsp.unit_type = FIELD_GET(GENMASK(7, 3), net_buf_pull_u8(buf));
 			rsp.company_id = net_buf_pull_be24(buf);
-			avrcp_cb->unit_info_rsp(avrcp, &rsp);
+			avrcp_cb->unit_info_rsp(avrcp, tid, &rsp);
 		}
 	}
 }
 
-static void avrcp_subunit_info_handler(struct bt_avrcp *avrcp, struct net_buf *buf,
+static void avrcp_subunit_info_handler(struct bt_avrcp *avrcp, uint8_t tid, struct net_buf *buf,
 					   bt_avctp_cr_t cr)
 {
 	struct bt_avrcp_header *avrcp_hdr;
 	struct bt_avrcp_subunit_info_rsp rsp;
 	uint8_t tmp;
 
+	avrcp_hdr = net_buf_pull_mem(buf, sizeof(*avrcp_hdr));
+
 	if (cr == BT_AVCTP_CMD) {
 		/* ToDo */
 	} else { /* BT_AVCTP_RESPONSE */
 		if ((avrcp_cb != NULL) && (avrcp_cb->subunit_info_rsp != NULL)) {
-			net_buf_pull(buf, sizeof(*avrcp_hdr));
 			if (buf->len < 5) {
-				LOG_ERR("Invalid subunit info length");
+				LOG_ERR("Invalid subunit info length: %d", buf->len);
 				return;
 			}
 			net_buf_pull_u8(buf); /* Always 0x07 */
@@ -297,22 +366,42 @@ static void avrcp_subunit_info_handler(struct bt_avrcp *avrcp, struct net_buf *b
 			}
 			rsp.extended_subunit_type = buf->data;
 			rsp.extended_subunit_id = rsp.extended_subunit_type + rsp.max_subunit_id;
-			avrcp_cb->subunit_info_rsp(avrcp, &rsp);
+			avrcp_cb->subunit_info_rsp(avrcp, tid, &rsp);
 		}
 	}
 }
 
-static void avrcp_pass_through_handler(struct bt_avrcp *avrcp, struct net_buf *buf,
+static void avrcp_pass_through_handler(struct bt_avrcp *avrcp, uint8_t tid, struct net_buf *buf,
 					   bt_avctp_cr_t cr)
 {
-	/* ToDo */
+	struct bt_avrcp_header *avrcp_hdr;
+	struct bt_avrcp_passthrough_rsp *rsp;
+	bt_avrcp_rsp_t result;
+
+	avrcp_hdr = net_buf_pull_mem(buf, sizeof(*avrcp_hdr));
+
+	if (cr == BT_AVCTP_CMD) {
+		/* ToDo */
+	} else { /* BT_AVCTP_RESPONSE */
+		if ((avrcp_cb != NULL) && (avrcp_cb->subunit_info_rsp != NULL)) {
+			if (buf->len < sizeof(*rsp)) {
+				LOG_ERR("Invalid passthrough length: %d", buf->len);
+				return;
+			}
+
+			result = BT_AVRCP_HDR_GET_CTYPE_OR_RSP(avrcp_hdr);
+			rsp = (struct bt_avrcp_passthrough_rsp *)buf->data;
+
+			avrcp_cb->passthrough_rsp(avrcp, tid, result, rsp);
+		}
+	}
 }
 
 static const struct avrcp_handler handler[] = {
-	{ BT_AVRCP_OPC_VENDOR_DEPENDENT, avrcp_vendor_dependent_handler },
-	{ BT_AVRCP_OPC_UNIT_INFO, avrcp_unit_info_handler },
-	{ BT_AVRCP_OPC_SUBUNIT_INFO, avrcp_subunit_info_handler },
-	{ BT_AVRCP_OPC_PASS_THROUGH, avrcp_pass_through_handler },
+	{BT_AVRCP_OPC_VENDOR_DEPENDENT, avrcp_vendor_dependent_handler},
+	{BT_AVRCP_OPC_UNIT_INFO, avrcp_unit_info_handler},
+	{BT_AVRCP_OPC_SUBUNIT_INFO, avrcp_subunit_info_handler},
+	{BT_AVRCP_OPC_PASS_THROUGH, avrcp_pass_through_handler},
 };
 
 /* An AVRCP message received */
@@ -323,12 +412,11 @@ static int avrcp_recv(struct bt_avctp *session, struct net_buf *buf)
 	struct bt_avrcp_header *avrcp_hdr;
 	uint8_t tid, i;
 	bt_avctp_cr_t cr;
-	bt_avrcp_ctype_t ctype;
+	bt_avrcp_rsp_t rsp;
 	bt_avrcp_subunit_id_t subunit_id;
 	bt_avrcp_subunit_type_t subunit_type;
 
-	avctp_hdr = (void *)buf->data;
-	net_buf_pull(buf, sizeof(*avctp_hdr));
+	avctp_hdr = net_buf_pull_mem(buf, sizeof(*avctp_hdr));
 	if (buf->len < sizeof(*avrcp_hdr)) {
 		LOG_ERR("invalid AVRCP header received");
 		return -EINVAL;
@@ -337,7 +425,7 @@ static int avrcp_recv(struct bt_avctp *session, struct net_buf *buf)
 	avrcp_hdr = (void *)buf->data;
 	tid = BT_AVCTP_HDR_GET_TRANSACTION_LABLE(avctp_hdr);
 	cr = BT_AVCTP_HDR_GET_CR(avctp_hdr);
-	ctype = BT_AVRCP_HDR_GET_CTYPE(avrcp_hdr);
+	rsp = BT_AVRCP_HDR_GET_CTYPE_OR_RSP(avrcp_hdr);
 	subunit_id = BT_AVRCP_HDR_GET_SUBUNIT_ID(avrcp_hdr);
 	subunit_type = BT_AVRCP_HDR_GET_SUBUNIT_TYPE(avrcp_hdr);
 
@@ -345,27 +433,12 @@ static int avrcp_recv(struct bt_avctp *session, struct net_buf *buf)
 		return -EINVAL; /* Ignore other profile */
 	}
 
-	LOG_DBG("AVRCP msg received, cr:0x%X, tid:0x%X, ctype: 0x%X, opc:0x%02X,", cr, tid, ctype,
+	LOG_DBG("AVRCP msg received, cr:0x%X, tid:0x%X, rsp: 0x%X, opc:0x%02X,", cr, tid, rsp,
 		avrcp_hdr->opcode);
-	if (cr == BT_AVCTP_RESPONSE) {
-		if (avrcp_hdr->opcode == BT_AVRCP_OPC_VENDOR_DEPENDENT &&
-		    ctype == BT_AVRCP_CTYPE_CHANGED) {
-			/* Status changed notifiation, do not reset timer */
-		} else if (avrcp_hdr->opcode == BT_AVRCP_OPC_PASS_THROUGH) {
-			/* No max response time for pass through commands  */
-		} else if (tid != avrcp->req.tid || subunit_type != avrcp->req.subunit ||
-			   avrcp_hdr->opcode != avrcp->req.opcode) {
-			LOG_WRN("unexpected AVRCP response, expected tid:0x%X, subunit:0x%X, "
-				"opc:0x%02X",
-				avrcp->req.tid, avrcp->req.subunit, avrcp->req.opcode);
-		} else {
-			k_work_cancel_delayable(&avrcp->timeout_work);
-		}
-	}
 
 	for (i = 0U; i < ARRAY_SIZE(handler); i++) {
 		if (avrcp_hdr->opcode == handler[i].opcode) {
-			handler[i].func(avrcp, buf, cr);
+			handler[i].func(avrcp, tid, buf, cr);
 			return 0;
 		}
 	}
@@ -460,31 +533,31 @@ int bt_avrcp_disconnect(struct bt_avrcp *avrcp)
 	return err;
 }
 
-static struct net_buf *avrcp_create_pdu(struct bt_avrcp *avrcp, bt_avctp_cr_t cr)
+static struct net_buf *avrcp_create_pdu(struct bt_avrcp *avrcp, uint8_t tid, bt_avctp_cr_t cr)
 {
 	struct net_buf *buf;
 
 	buf = bt_avctp_create_pdu(&(avrcp->session), cr, BT_AVCTP_PKT_TYPE_SINGLE,
-				  BT_AVCTP_IPID_NONE, &avrcp->local_tid,
+				  BT_AVCTP_IPID_NONE, tid,
 				  sys_cpu_to_be16(BT_SDP_AV_REMOTE_SVCLASS));
 
 	return buf;
 }
 
-static struct net_buf *avrcp_create_unit_pdu(struct bt_avrcp *avrcp, bt_avctp_cr_t cr)
+static struct net_buf *avrcp_create_unit_pdu(struct bt_avrcp *avrcp, uint8_t tid, bt_avctp_cr_t cr)
 {
 	struct net_buf *buf;
-	struct bt_avrcp_unit_info_cmd *cmd;
+	struct bt_avrcp_frame *cmd;
 
-	buf = avrcp_create_pdu(avrcp, cr);
+	buf = avrcp_create_pdu(avrcp, tid, cr);
 	if (!buf) {
-		return buf;
+		return NULL;
 	}
 
 	cmd = net_buf_add(buf, sizeof(*cmd));
 	memset(cmd, 0, sizeof(*cmd));
-	BT_AVRCP_HDR_SET_CTYPE(&cmd->hdr, cr == BT_AVCTP_CMD ? BT_AVRCP_CTYPE_STATUS
-							     : BT_AVRCP_CTYPE_IMPLEMENTED_STABLE);
+	BT_AVRCP_HDR_SET_CTYPE_OR_RSP(&cmd->hdr, cr == BT_AVCTP_CMD ? BT_AVRCP_CTYPE_STATUS
+								    : BT_AVRCP_RSP_STABLE);
 	BT_AVRCP_HDR_SET_SUBUNIT_ID(&cmd->hdr, BT_AVRCP_SUBUNIT_ID_IGNORE);
 	BT_AVRCP_HDR_SET_SUBUNIT_TYPE(&cmd->hdr, BT_AVRCP_SUBUNIT_TYPE_UNIT);
 	cmd->hdr.opcode = BT_AVRCP_OPC_UNIT_INFO;
@@ -492,20 +565,21 @@ static struct net_buf *avrcp_create_unit_pdu(struct bt_avrcp *avrcp, bt_avctp_cr
 	return buf;
 }
 
-static struct net_buf *avrcp_create_subunit_pdu(struct bt_avrcp *avrcp, bt_avctp_cr_t cr)
+static struct net_buf *avrcp_create_subunit_pdu(struct bt_avrcp *avrcp, uint8_t tid,
+						bt_avctp_cr_t cr)
 {
 	struct net_buf *buf;
-	struct bt_avrcp_unit_info_cmd *cmd;
+	struct bt_avrcp_frame *cmd;
 
-	buf = avrcp_create_pdu(avrcp, cr);
+	buf = avrcp_create_pdu(avrcp, tid, cr);
 	if (!buf) {
-		return buf;
+		return NULL;
 	}
 
 	cmd = net_buf_add(buf, sizeof(*cmd));
 	memset(cmd, 0, sizeof(*cmd));
-	BT_AVRCP_HDR_SET_CTYPE(&cmd->hdr, cr == BT_AVCTP_CMD ? BT_AVRCP_CTYPE_STATUS
-							     : BT_AVRCP_CTYPE_IMPLEMENTED_STABLE);
+	BT_AVRCP_HDR_SET_CTYPE_OR_RSP(&cmd->hdr, cr == BT_AVCTP_CMD ? BT_AVRCP_CTYPE_STATUS
+								    : BT_AVRCP_RSP_STABLE);
 	BT_AVRCP_HDR_SET_SUBUNIT_ID(&cmd->hdr, BT_AVRCP_SUBUNIT_ID_IGNORE);
 	BT_AVRCP_HDR_SET_SUBUNIT_TYPE(&cmd->hdr, BT_AVRCP_SUBUNIT_TYPE_UNIT);
 	cmd->hdr.opcode = BT_AVRCP_OPC_SUBUNIT_INFO;
@@ -513,6 +587,48 @@ static struct net_buf *avrcp_create_subunit_pdu(struct bt_avrcp *avrcp, bt_avctp
 	return buf;
 }
 
+static struct net_buf *avrcp_create_passthrough_pdu(struct bt_avrcp *avrcp, uint8_t tid,
+						    bt_avctp_cr_t cr, uint8_t ctype_or_rsp)
+{
+	struct net_buf *buf;
+	struct bt_avrcp_frame *cmd;
+
+	buf = avrcp_create_pdu(avrcp, tid, cr);
+	if (!buf) {
+		return NULL;
+	}
+
+	cmd = net_buf_add(buf, sizeof(*cmd));
+	memset(cmd, 0, sizeof(*cmd));
+	BT_AVRCP_HDR_SET_CTYPE_OR_RSP(&cmd->hdr, ctype_or_rsp);
+	BT_AVRCP_HDR_SET_SUBUNIT_ID(&cmd->hdr, BT_AVRCP_SUBUNIT_ID_ZERO);
+	BT_AVRCP_HDR_SET_SUBUNIT_TYPE(&cmd->hdr, BT_AVRCP_SUBUNIT_TYPE_PANEL);
+	cmd->hdr.opcode = BT_AVRCP_OPC_PASS_THROUGH;
+
+	return buf;
+}
+
+static struct net_buf *avrcp_create_vendor_pdu(struct bt_avrcp *avrcp, uint8_t tid,
+					       bt_avctp_cr_t cr, uint8_t ctype_or_rsp)
+{
+	struct net_buf *buf;
+	struct bt_avrcp_frame *cmd;
+
+	buf = avrcp_create_pdu(avrcp, tid, cr);
+	if (!buf) {
+		return NULL;
+	}
+
+	cmd = net_buf_add(buf, sizeof(*cmd));
+	memset(cmd, 0, sizeof(*cmd));
+	BT_AVRCP_HDR_SET_CTYPE_OR_RSP(&cmd->hdr, ctype_or_rsp);
+	BT_AVRCP_HDR_SET_SUBUNIT_ID(&cmd->hdr, BT_AVRCP_SUBUNIT_ID_ZERO);
+	BT_AVRCP_HDR_SET_SUBUNIT_TYPE(&cmd->hdr, BT_AVRCP_SUBUNIT_TYPE_PANEL);
+	cmd->hdr.opcode = BT_AVRCP_OPC_VENDOR_DEPENDENT;
+
+	return buf;
+}
+
 static int avrcp_send(struct bt_avrcp *avrcp, struct net_buf *buf)
 {
 	int err;
@@ -521,33 +637,46 @@ static int avrcp_send(struct bt_avrcp *avrcp, struct net_buf *buf)
 		(struct bt_avrcp_header *)(buf->data + sizeof(*avctp_hdr));
 	uint8_t tid = BT_AVCTP_HDR_GET_TRANSACTION_LABLE(avctp_hdr);
 	bt_avctp_cr_t cr = BT_AVCTP_HDR_GET_CR(avctp_hdr);
-	bt_avrcp_ctype_t ctype = BT_AVRCP_HDR_GET_CTYPE(avrcp_hdr);
-	bt_avrcp_subunit_type_t subunit_type = BT_AVRCP_HDR_GET_SUBUNIT_TYPE(avrcp_hdr);
+	bt_avrcp_ctype_t ctype = BT_AVRCP_HDR_GET_CTYPE_OR_RSP(avrcp_hdr);
 
 	LOG_DBG("AVRCP send cr:0x%X, tid:0x%X, ctype: 0x%X, opc:0x%02X\n", cr, tid, ctype,
 		avrcp_hdr->opcode);
 	err = bt_avctp_send(&(avrcp->session), buf);
 	if (err < 0) {
+		net_buf_unref(buf);
+		LOG_ERR("AVCTP send fail, err = %d", err);
 		return err;
 	}
 
-	if (cr == BT_AVCTP_CMD && avrcp_hdr->opcode != BT_AVRCP_OPC_PASS_THROUGH) {
-		avrcp->req.tid = tid;
-		avrcp->req.subunit = subunit_type;
-		avrcp->req.opcode = avrcp_hdr->opcode;
+	return 0;
+}
 
-		k_work_reschedule(&avrcp->timeout_work, AVRCP_TIMEOUT);
+int bt_avrcp_get_cap(struct bt_avrcp *avrcp, uint8_t tid, uint8_t cap_id)
+{
+	struct net_buf *buf;
+	struct bt_avrcp_avc_pdu *pdu;
+
+	buf = avrcp_create_vendor_pdu(avrcp, tid, BT_AVCTP_CMD, BT_AVRCP_CTYPE_STATUS);
+	if (!buf) {
+		return -ENOMEM;
 	}
 
-	return 0;
+	net_buf_add_be24(buf, BT_AVRCP_COMPANY_ID_BLUETOOTH_SIG);
+	pdu = net_buf_add(buf, sizeof(*pdu));
+	pdu->pdu_id = BT_AVRCP_PDU_ID_GET_CAPS;
+	BT_AVRCP_AVC_PDU_SET_PACKET_TYPE(pdu, BT_AVRVP_PKT_TYPE_SINGLE);
+	pdu->param_len = sys_cpu_to_be16(sizeof(cap_id));
+	net_buf_add_u8(buf, cap_id);
+
+	return avrcp_send(avrcp, buf);
 }
 
-int bt_avrcp_get_unit_info(struct bt_avrcp *avrcp)
+int bt_avrcp_get_unit_info(struct bt_avrcp *avrcp, uint8_t tid)
 {
 	struct net_buf *buf;
 	uint8_t param[5];
 
-	buf = avrcp_create_unit_pdu(avrcp, BT_AVCTP_CMD);
+	buf = avrcp_create_unit_pdu(avrcp, tid, BT_AVCTP_CMD);
 	if (!buf) {
 		return -ENOMEM;
 	}
@@ -558,24 +687,43 @@ int bt_avrcp_get_unit_info(struct bt_avrcp *avrcp)
 	return avrcp_send(avrcp, buf);
 }
 
-int bt_avrcp_get_subunit_info(struct bt_avrcp *avrcp)
+int bt_avrcp_get_subunit_info(struct bt_avrcp *avrcp, uint8_t tid)
 {
 	struct net_buf *buf;
 	uint8_t param[5];
 
-	buf = avrcp_create_subunit_pdu(avrcp, BT_AVCTP_CMD);
+	buf = avrcp_create_subunit_pdu(avrcp, tid, BT_AVCTP_CMD);
 	if (!buf) {
 		return -ENOMEM;
 	}
 
 	memset(param, 0xFF, ARRAY_SIZE(param));
 	param[0] = FIELD_PREP(GENMASK(6, 4), AVRCP_SUBUNIT_PAGE) |
-		   FIELD_PREP(GENMASK(2, 0), AVRCP_SUBUNIT_EXTENSION_COED);
+		   FIELD_PREP(GENMASK(2, 0), AVRCP_SUBUNIT_EXTENSION_CODE);
 	net_buf_add_mem(buf, param, sizeof(param));
 
 	return avrcp_send(avrcp, buf);
 }
 
+int bt_avrcp_passthrough(struct bt_avrcp *avrcp, uint8_t tid, uint8_t opid, uint8_t state,
+			 const uint8_t *payload, uint8_t len)
+{
+	struct net_buf *buf;
+
+	buf = avrcp_create_passthrough_pdu(avrcp, tid, BT_AVCTP_CMD, BT_AVRCP_CTYPE_CONTROL);
+	if (!buf) {
+		return -ENOMEM;
+	}
+
+	net_buf_add_u8(buf, FIELD_PREP(BIT(7), state) | FIELD_PREP(GENMASK(6, 0), opid));
+	net_buf_add_u8(buf, len);
+	if (len) {
+		net_buf_add_mem(buf, payload, len);
+	}
+
+	return avrcp_send(avrcp, buf);
+}
+
 int bt_avrcp_register_cb(const struct bt_avrcp_cb *cb)
 {
 	avrcp_cb = cb;
diff --git a/subsys/bluetooth/host/classic/avrcp_internal.h b/subsys/bluetooth/host/classic/avrcp_internal.h
index cbfcc8e824f..6d4e329da81 100644
--- a/subsys/bluetooth/host/classic/avrcp_internal.h
+++ b/subsys/bluetooth/host/classic/avrcp_internal.h
@@ -18,22 +18,7 @@
 #define AVRCP_CAT_4 BIT(3) /* Menu */
 
 #define AVRCP_SUBUNIT_PAGE           (0) /* Fixed value according to AVRCP */
-#define AVRCP_SUBUNIT_EXTENSION_COED (7) /* Fixed value according to TA Document 2001012 */
-
-typedef enum __packed {
-	BT_AVRCP_CTYPE_CONTROL = 0x0,
-	BT_AVRCP_CTYPE_STATUS = 0x1,
-	BT_AVRCP_CTYPE_SPECIFIC_INQUIRY = 0x2,
-	BT_AVRCP_CTYPE_NOTIFY = 0x3,
-	BT_AVRCP_CTYPE_GENERAL_INQUIRY = 0x4,
-	BT_AVRCP_CTYPE_NOT_IMPLEMENTED = 0x8,
-	BT_AVRCP_CTYPE_ACCEPTED = 0x9,
-	BT_AVRCP_CTYPE_REJECTED = 0xA,
-	BT_AVRCP_CTYPE_IN_TRANSITION = 0xB,
-	BT_AVRCP_CTYPE_IMPLEMENTED_STABLE = 0xC,
-	BT_AVRCP_CTYPE_CHANGED = 0xD,
-	BT_AVRCP_CTYPE_INTERIM = 0xF,
-} bt_avrcp_ctype_t;
+#define AVRCP_SUBUNIT_EXTENSION_CODE (7) /* Fixed value according to TA Document 2001012 */
 
 typedef enum __packed {
 	BT_AVRCP_SUBUNIT_ID_ZERO = 0x0,
@@ -52,6 +37,74 @@ typedef enum __packed {
 	BT_AVRCP_OPC_PASS_THROUGH = 0x7c,
 } bt_avrcp_opcode_t;
 
+typedef enum __packed {
+	BT_AVRVP_PKT_TYPE_SINGLE = 0b00,
+	BT_AVRVP_PKT_TYPE_START = 0b01,
+	BT_AVRVP_PKT_TYPE_CONTINUE = 0b10,
+	BT_AVRVP_PKT_TYPE_END = 0b11,
+} bt_avrcp_pkt_type_t;
+
+typedef enum __packed {
+	/** Capabilities */
+	BT_AVRCP_PDU_ID_GET_CAPS = 0x10,
+
+	/** Player Application Settings */
+	BT_AVRCP_PDU_ID_LIST_PLAYER_APP_SETTING_ATTRS = 0x11,
+	BT_AVRCP_PDU_ID_LIST_PLAYER_APP_SETTING_VALS = 0x12,
+	BT_AVRCP_PDU_ID_GET_CURR_PLAYER_APP_SETTING_VAL = 0x13,
+	BT_AVRCP_PDU_ID_SET_PLAYER_APP_SETTING_VAL = 0x14,
+	BT_AVRCP_PDU_ID_GET_PLAYER_APP_SETTING_ATTR_TEXT = 0x15,
+	BT_AVRCP_PDU_ID_GET_PLAYER_APP_SETTING_VAL_TEXT = 0x16,
+	BT_AVRCP_PDU_ID_INFORM_DISPLAYABLE_CHAR_SET = 0x17,
+	BT_AVRCP_PDU_ID_INFORM_BATT_STATUS_OF_CT = 0x18,
+
+	/** Metadata Attributes for Current Media Item */
+	BT_AVRCP_PDU_ID_GET_ELEMENT_ATTRS = 0x20,
+
+	/** Notifications */
+	BT_AVRCP_PDU_ID_GET_PLAY_STATUS = 0x30,
+	BT_AVRCP_PDU_ID_REGISTER_NOTIFICATION = 0x31,
+	BT_AVRCP_PDU_ID_EVT_PLAYBACK_STATUS_CHANGED = 0x31,
+	BT_AVRCP_PDU_ID_EVT_TRACK_CHANGED = 0x31,
+	BT_AVRCP_PDU_ID_EVT_TRACK_REACHED_END = 0x31,
+	BT_AVRCP_PDU_ID_EVT_TRACK_REACHED_START = 0x31,
+	BT_AVRCP_PDU_ID_EVT_PLAYBACK_POS_CHANGED = 0x31,
+	BT_AVRCP_PDU_ID_EVT_BATT_STATUS_CHANGED = 0x31,
+	BT_AVRCP_PDU_ID_EVT_SYSTEM_STATUS_CHANGED = 0x31,
+	BT_AVRCP_PDU_ID_EVT_PLAYER_APP_SETTING_CHANGED = 0x31,
+	BT_AVRCP_PDU_ID_EVT_VOLUME_CHANGED = 0x31,
+	BT_AVRCP_PDU_ID_EVT_ADDRESSED_PLAYER_CHANGED = 0x31,
+	BT_AVRCP_PDU_ID_EVT_AVAILABLE_PLAYERS_CHANGED = 0x31,
+	BT_AVRCP_PDU_ID_EVT_UIDS_CHANGED = 0x31,
+
+	/** Continuation */
+	BT_AVRCP_PDU_ID_REQ_CONTINUING_RSP = 0x40,
+	BT_AVRCP_PDU_ID_ABORT_CONTINUING_RSP = 0x41,
+
+	/** Absolute Volume */
+	BT_AVRCP_PDU_ID_SET_ABSOLUTE_VOLUME = 0x50,
+
+	/** Media Player Selection */
+	BT_AVRCP_PDU_ID_SET_ADDRESSED_PLAYER = 0x60,
+
+	/** Browsing */
+	BT_AVRCP_PDU_ID_SET_BROWSED_PLAYER = 0x70,
+	BT_AVRCP_PDU_ID_GET_FOLDER_ITEMS = 0x71,
+	BT_AVRCP_PDU_ID_CHANGE_PATH = 0x72,
+	BT_AVRCP_PDU_ID_GET_ITEM_ATTRS = 0x73,
+	BT_AVRCP_PDU_ID_PLAY_ITEM = 0x74,
+	BT_AVRCP_PDU_ID_GET_TOTAL_NUMBER_OF_ITEMS = 0x75,
+
+	/** Search */
+	BT_AVRCP_PDU_ID_SEARCH = 0x80,
+
+	/** Now Playing */
+	BT_AVRCP_PDU_ID_ADD_TO_NOW_PLAYING = 0x90,
+
+	/** Error Response */
+	BT_AVRCP_PDU_ID_GENERAL_REJECT = 0xa0,
+} bt_avrcp_pdu_id_t;
+
 struct bt_avrcp_req {
 	uint8_t tid;
 	uint8_t subunit;
@@ -59,13 +112,20 @@ struct bt_avrcp_req {
 };
 
 struct bt_avrcp_header {
-	uint8_t byte0;  /** [7:4]: RFA, [3:0]: Ctype */
-	uint8_t byte1;  /** [7:3]: Subunit_type, [2:0]: Subunit_ID */
-	uint8_t opcode; /** Unit Info, Subunit Info, Vendor Dependent, or Pass Through */
+	uint8_t byte0;  /**< [7:4]: RFA, [3:0]: Ctype */
+	uint8_t byte1;  /**< [7:3]: Subunit_type, [2:0]: Subunit_ID */
+	uint8_t opcode; /**< Unit Info, Subunit Info, Vendor Dependent, or Pass Through */
+} __packed;
+
+struct bt_avrcp_avc_pdu {
+	uint8_t pdu_id;
+	uint8_t pkt_type; /**< [7:2]: Reserved, [1:0]: Packet Type */
+	uint16_t param_len;
+	uint8_t param[];
 } __packed;
 
 /** The 4-bit command type or the 4-bit response code. */
-#define BT_AVRCP_HDR_GET_CTYPE(hdr)        FIELD_GET(GENMASK(3, 0), ((hdr)->byte0))
+#define BT_AVRCP_HDR_GET_CTYPE_OR_RSP(hdr) FIELD_GET(GENMASK(3, 0), ((hdr)->byte0))
 /** Taken together, the subunit_type and subunit_ID fields define the command recipient’s  address
  *  within the target. These fields enable the target to determine  whether the command is
  *  addressed to the target  unit, or to a specific subunit within the target. The values in these
@@ -80,7 +140,7 @@ struct bt_avrcp_header {
 #define BT_AVRCP_HDR_GET_SUBUNIT_TYPE(hdr) FIELD_GET(GENMASK(7, 3), ((hdr)->byte1))
 
 /** The 4-bit command type or the 4-bit response code. */
-#define BT_AVRCP_HDR_SET_CTYPE(hdr, ctype)                                                         \
+#define BT_AVRCP_HDR_SET_CTYPE_OR_RSP(hdr, ctype)                                                  \
 	(hdr)->byte0 = (((hdr)->byte0) & ~GENMASK(3, 0)) | FIELD_PREP(GENMASK(3, 0), (ctype))
 /** Taken together, the subunit_type and subunit_ID fields define the command recipient’s  address
  *  within the target. These fields enable the target to determine  whether the command is
@@ -97,9 +157,22 @@ struct bt_avrcp_header {
 #define BT_AVRCP_HDR_SET_SUBUNIT_TYPE(hdr, subunit_type)                                           \
 	(hdr)->byte1 = (((hdr)->byte1) & ~GENMASK(7, 3)) | FIELD_PREP(GENMASK(7, 3), (subunit_type))
 
-struct bt_avrcp_unit_info_cmd {
+/** The Packet Type field qualifies each packet as either start (Packet Type=01), continue
+ *  (Packet Type=10), or end packet (Packet Type=11). In the case of a non-fragmented message, this
+ *  field (Packet Type=00) simply indicates that the message is sent in a single AV/C frame.
+ */
+#define BT_AVRCP_AVC_PDU_GET_PACKET_TYPE(pdu) FIELD_GET(GENMASK(1, 0), ((pdu)->pkt_type))
+
+/** The Packet Type field qualifies each packet as either start (Packet Type=01), continue
+ *  (Packet Type=10), or end packet (Packet Type=11). In the case of a non-fragmented message, this
+ *  field (Packet Type=00) simply indicates that the message is sent in a single AV/C frame.
+ */
+#define BT_AVRCP_AVC_PDU_SET_PACKET_TYPE(pdu, packet_type)                                         \
+	(pdu)->pkt_type = FIELD_PREP(GENMASK(1, 0), (packet_type))
+
+struct bt_avrcp_frame {
 	struct bt_avrcp_header hdr;
-	uint8_t data[0];
+	uint8_t data[];
 } __packed;
 
 int bt_avrcp_init(void);
diff --git a/subsys/bluetooth/host/classic/br.c b/subsys/bluetooth/host/classic/br.c
index afdbb0b1d9e..abbd345b44b 100644
--- a/subsys/bluetooth/host/classic/br.c
+++ b/subsys/bluetooth/host/classic/br.c
@@ -22,6 +22,14 @@
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(bt_br);
 
+#define RSSI_INVALID 127
+
+enum __packed resolve_name_state {
+	RESOLVE_REMOTE_NAME_PENDING,
+	RESOLVE_REMOTE_NAME_RESOLVING,
+	RESOLVE_REMOTE_NAME_RESOLVED,
+};
+
 struct bt_br_discovery_result *discovery_results;
 static size_t discovery_results_size;
 static size_t discovery_results_count;
@@ -153,7 +161,7 @@ bool bt_br_update_sec_level(struct bt_conn *conn)
 
 	if (conn->br.link_key) {
 		if (conn->br.link_key->flags & BT_LINK_KEY_AUTHENTICATED) {
-			if (conn->encrypt == 0x02) {
+			if (conn->encrypt == BT_HCI_ENCRYPTION_ON_BR_AES_CCM) {
 				conn->sec_level = BT_SECURITY_L4;
 			} else {
 				conn->sec_level = BT_SECURITY_L3;
@@ -325,11 +333,10 @@ void bt_br_discovery_reset(void)
 	discovery_results_count = 0;
 }
 
-static void report_discovery_results(void)
+static bool check_request_name(void)
 {
-	bool resolving_names = false;
 	int i;
-	struct bt_br_discovery_cb *listener, *next;
+	bool resolving_names = false;
 
 	for (i = 0; i < discovery_results_count; i++) {
 		struct bt_br_discovery_priv *priv;
@@ -340,16 +347,37 @@ static void report_discovery_results(void)
 			continue;
 		}
 
+		if (priv->resolve_state != RESOLVE_REMOTE_NAME_PENDING) {
+			continue;
+		}
+
 		if (request_name(&discovery_results[i].addr, priv->pscan_rep_mode,
 				 priv->clock_offset)) {
+			priv->resolve_state = RESOLVE_REMOTE_NAME_RESOLVED;
 			continue;
 		}
 
-		priv->resolving = true;
+		priv->resolve_state = RESOLVE_REMOTE_NAME_RESOLVING;
 		resolving_names = true;
+		break;
 	}
 
-	if (resolving_names) {
+	return resolving_names;
+}
+
+static void report_discovery_results(void)
+{
+	int i;
+	struct bt_br_discovery_cb *listener, *next;
+
+	for (i = 0; i < discovery_results_count; i++) {
+		struct bt_br_discovery_priv *priv;
+
+		priv = &discovery_results[i]._priv;
+		priv->resolve_state = RESOLVE_REMOTE_NAME_PENDING;
+	}
+
+	if (check_request_name()) {
 		return;
 	}
 
@@ -394,7 +422,7 @@ static struct bt_br_discovery_result *get_result_slot(const bt_addr_t *addr, int
 	}
 
 	/* ignore if invalid RSSI */
-	if (rssi == 0xff) {
+	if (rssi == RSSI_INVALID) {
 		return NULL;
 	}
 
@@ -509,16 +537,15 @@ void bt_hci_remote_name_request_complete(struct net_buf *buf)
 	struct bt_br_discovery_priv *priv;
 	int eir_len = 240;
 	uint8_t *eir;
-	int i;
 	struct bt_br_discovery_cb *listener, *next;
 
-	result = get_result_slot(&evt->bdaddr, 0xff);
+	result = get_result_slot(&evt->bdaddr, RSSI_INVALID);
 	if (!result) {
 		return;
 	}
 
 	priv = &result->_priv;
-	priv->resolving = false;
+	priv->resolve_state = RESOLVE_REMOTE_NAME_RESOLVED;
 
 	if (evt->status) {
 		goto check_names;
@@ -570,15 +597,9 @@ void bt_hci_remote_name_request_complete(struct net_buf *buf)
 	}
 
 check_names:
-	/* if still waiting for names */
-	for (i = 0; i < discovery_results_count; i++) {
-		struct bt_br_discovery_priv *dpriv;
-
-		dpriv = &discovery_results[i]._priv;
-
-		if (dpriv->resolving) {
-			return;
-		}
+	/* if still need to request name */
+	if (check_request_name()) {
+		return;
 	}
 
 	/* all names resolved, report discovery results */
@@ -980,7 +1001,7 @@ int bt_br_discovery_stop(void)
 
 		priv = &discovery_results[i]._priv;
 
-		if (!priv->resolving) {
+		if (priv->resolve_state != RESOLVE_REMOTE_NAME_RESOLVING) {
 			continue;
 		}
 
@@ -1055,8 +1076,128 @@ int bt_br_set_connectable(bool enable)
 	}
 }
 
-int bt_br_set_discoverable(bool enable)
+#define BT_LIAC 0x9e8b00
+#define BT_GIAC 0x9e8b33
+
+static int bt_br_write_current_iac_lap(bool limited)
 {
+	struct bt_hci_cp_write_current_iac_lap *iac_lap;
+	struct net_buf *buf;
+	uint8_t param_len;
+	uint8_t num_current_iac = limited ? 2 : 1;
+
+	LOG_DBG("limited discoverable mode? %s", limited ? "Yes" : "No");
+
+	param_len = sizeof(*iac_lap) + (num_current_iac * sizeof(struct bt_hci_iac_lap));
+
+	buf = bt_hci_cmd_create(BT_HCI_OP_WRITE_CURRENT_IAC_LAP, param_len);
+	if (!buf) {
+		return -ENOBUFS;
+	}
+
+	iac_lap = net_buf_add(buf, param_len);
+	iac_lap->num_current_iac = num_current_iac;
+	sys_put_le24(BT_GIAC, iac_lap->lap[0].iac);
+	if (num_current_iac > 1) {
+		sys_put_le24(BT_LIAC, iac_lap->lap[1].iac);
+	}
+
+	return bt_hci_cmd_send_sync(BT_HCI_OP_WRITE_CURRENT_IAC_LAP, buf, NULL);
+}
+
+#define BT_COD_MAJOR_SVC_CLASS_LIMITED_DISCOVER BIT(13)
+
+static int bt_br_read_cod(uint32_t *cod)
+{
+	struct net_buf *rsp;
+	struct bt_hci_rp_read_class_of_device *rp;
+	int err;
+
+	LOG_DBG("Read COD");
+
+	/* Read Class of device */
+	err = bt_hci_cmd_send_sync(BT_HCI_OP_READ_CLASS_OF_DEVICE, NULL, &rsp);
+	if (err) {
+		LOG_WRN("Fail to read COD");
+		return err;
+	}
+
+	if (!rsp || (rsp->len < sizeof(*rp))) {
+		LOG_WRN("Invalid response");
+		return -EIO;
+	}
+
+	rp = (void *)rsp->data;
+	*cod = sys_get_le24(rp->class_of_device);
+
+	LOG_DBG("Current COD %06x", *cod);
+
+	net_buf_unref(rsp);
+
+	return 0;
+}
+
+static int bt_br_write_cod(uint32_t cod)
+{
+	struct net_buf *buf;
+
+	/* Set Class of device */
+	buf = bt_hci_cmd_create(BT_HCI_OP_WRITE_CLASS_OF_DEVICE,
+				sizeof(struct bt_hci_cp_write_class_of_device));
+	if (!buf) {
+		return -ENOBUFS;
+	}
+
+	net_buf_add_le24(buf, cod);
+
+	return bt_hci_cmd_send_sync(BT_HCI_OP_WRITE_CLASS_OF_DEVICE, buf, NULL);
+}
+
+static int bt_br_update_cod(bool limited)
+{
+	int err;
+	uint32_t cod;
+
+	LOG_DBG("Update COD");
+
+	err = bt_br_read_cod(&cod);
+	if (err) {
+		return err;
+	}
+
+	if (limited) {
+		cod |= BT_COD_MAJOR_SVC_CLASS_LIMITED_DISCOVER;
+	} else {
+		cod &= ~BT_COD_MAJOR_SVC_CLASS_LIMITED_DISCOVER;
+	}
+
+	err = bt_br_write_cod(cod);
+	return err;
+}
+
+static void bt_br_limited_discoverable_timeout_handler(struct k_work *work)
+{
+	int err;
+
+	if (!atomic_test_bit(bt_dev.flags, BT_DEV_LIMITED_DISCOVERABLE_MODE)) {
+		LOG_INF("Limited discoverable mode has been disabled");
+		return;
+	}
+
+	err = bt_br_set_discoverable(false, false);
+	if (err) {
+		LOG_WRN("Disable discoverable failure (err %d)", err);
+	}
+}
+
+/* Work used for limited discoverable mode time span */
+static K_WORK_DELAYABLE_DEFINE(bt_br_limited_discoverable_timeout,
+			       bt_br_limited_discoverable_timeout_handler);
+
+int bt_br_set_discoverable(bool enable, bool limited)
+{
+	int err;
+
 	if (enable) {
 		if (atomic_test_bit(bt_dev.flags, BT_DEV_ISCAN)) {
 			return -EALREADY;
@@ -1066,12 +1207,94 @@ int bt_br_set_discoverable(bool enable)
 			return -EPERM;
 		}
 
-		return write_scan_enable(BT_BREDR_SCAN_INQUIRY | BT_BREDR_SCAN_PAGE);
-	} else {
-		if (!atomic_test_bit(bt_dev.flags, BT_DEV_ISCAN)) {
-			return -EALREADY;
+		err = bt_br_write_current_iac_lap(limited);
+		if (err) {
+			return err;
+		}
+
+		err = bt_br_update_cod(limited);
+		if (err) {
+			return err;
+		}
+
+		err = write_scan_enable(BT_BREDR_SCAN_INQUIRY | BT_BREDR_SCAN_PAGE);
+		if (!err && (limited == true)) {
+			atomic_set_bit(bt_dev.flags, BT_DEV_LIMITED_DISCOVERABLE_MODE);
+			k_work_reschedule(&bt_br_limited_discoverable_timeout,
+					  K_SECONDS(CONFIG_BT_LIMITED_DISCOVERABLE_DURATION));
+		}
+		return err;
+	}
+
+	if (!atomic_test_bit(bt_dev.flags, BT_DEV_ISCAN)) {
+		return -EALREADY;
+	}
+
+	err = write_scan_enable(BT_BREDR_SCAN_PAGE);
+	if (err) {
+		return err;
+	}
+
+	if (atomic_test_bit(bt_dev.flags, BT_DEV_LIMITED_DISCOVERABLE_MODE)) {
+		err = bt_br_write_current_iac_lap(false);
+		if (err) {
+			return err;
+		}
+
+		err = bt_br_update_cod(false);
+		if (err) {
+			return err;
+		}
+
+		atomic_clear_bit(bt_dev.flags, BT_DEV_LIMITED_DISCOVERABLE_MODE);
+		k_work_cancel_delayable(&bt_br_limited_discoverable_timeout);
+	}
+
+	return 0;
+}
+
+bool bt_br_bond_exists(const bt_addr_t *addr)
+{
+	struct bt_keys_link_key *key = bt_keys_find_link_key(addr);
+
+	/* if there are any keys stored then device is bonded */
+	return key != NULL;
+}
+
+static void unpair(const bt_addr_t *addr)
+{
+	struct bt_conn *conn = bt_conn_lookup_addr_br(addr);
+	struct bt_conn_auth_info_cb *listener, *next;
+
+	if (conn) {
+		bt_conn_disconnect(conn, BT_HCI_ERR_REMOTE_USER_TERM_CONN);
+		bt_conn_unref(conn);
+	}
+
+	bt_keys_link_key_clear_addr(addr);
+
+	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&bt_auth_info_cbs, listener,
+					  next, node) {
+		if (listener->br_bond_deleted) {
+			listener->br_bond_deleted(addr);
 		}
+	}
+}
+
+static void bt_br_unpair_remote(const struct bt_br_bond_info *info, void *data)
+{
+	ARG_UNUSED(data);
+
+	unpair(&info->addr);
+}
 
-		return write_scan_enable(BT_BREDR_SCAN_PAGE);
+int bt_br_unpair(const bt_addr_t *addr)
+{
+	if (!addr || bt_addr_eq(addr, BT_ADDR_ANY)) {
+		bt_br_foreach_bond(bt_br_unpair_remote, NULL);
+	} else {
+		unpair(addr);
 	}
+
+	return 0;
 }
diff --git a/subsys/bluetooth/host/classic/conn_br.c b/subsys/bluetooth/host/classic/conn_br.c
new file mode 100644
index 00000000000..f57b33a1509
--- /dev/null
+++ b/subsys/bluetooth/host/classic/conn_br.c
@@ -0,0 +1,145 @@
+/* conn_br.c - Bluetooth Classic connection handling */
+
+/*
+ * Copyright (c) 2015-2016 Intel Corporation
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/bluetooth/iso.h>
+#include <zephyr/kernel.h>
+#include <string.h>
+#include <errno.h>
+#include <stdbool.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/check.h>
+#include <zephyr/sys/iterable_sections.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/debug/stack.h>
+#include <zephyr/sys/__assert.h>
+
+#include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/direction.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/hci_vs.h>
+#include <zephyr/bluetooth/att.h>
+
+#include "common/assert.h"
+#include "common/bt_str.h"
+
+#include "host/conn_internal.h"
+#include "host/l2cap_internal.h"
+#include "host/keys.h"
+#include "host/smp.h"
+#include "ssp.h"
+#include "sco_internal.h"
+
+#define LOG_LEVEL CONFIG_BT_CONN_LOG_LEVEL
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(bt_conn_br);
+
+void bt_sco_cleanup(struct bt_conn *sco_conn)
+{
+	bt_sco_cleanup_acl(sco_conn);
+	bt_conn_unref(sco_conn);
+}
+
+struct bt_conn *bt_conn_create_br(const bt_addr_t *peer,
+				  const struct bt_br_conn_param *param)
+{
+	struct bt_hci_cp_connect *cp;
+	struct bt_conn *conn;
+	struct net_buf *buf;
+
+	conn = bt_conn_lookup_addr_br(peer);
+	if (conn) {
+		switch (conn->state) {
+		case BT_CONN_INITIATING:
+		case BT_CONN_CONNECTED:
+			return conn;
+		default:
+			bt_conn_unref(conn);
+			return NULL;
+		}
+	}
+
+	conn = bt_conn_add_br(peer);
+	if (!conn) {
+		return NULL;
+	}
+
+	buf = bt_hci_cmd_create(BT_HCI_OP_CONNECT, sizeof(*cp));
+	if (!buf) {
+		bt_conn_unref(conn);
+		return NULL;
+	}
+
+	cp = net_buf_add(buf, sizeof(*cp));
+
+	(void)memset(cp, 0, sizeof(*cp));
+
+	memcpy(&cp->bdaddr, peer, sizeof(cp->bdaddr));
+	cp->packet_type = sys_cpu_to_le16(0xcc18); /* DM1 DH1 DM3 DH5 DM5 DH5 */
+	cp->pscan_rep_mode = 0x02; /* R2 */
+	cp->allow_role_switch = param->allow_role_switch ? 0x01 : 0x00;
+	cp->clock_offset = 0x0000; /* TODO used cached clock offset */
+
+	if (bt_hci_cmd_send_sync(BT_HCI_OP_CONNECT, buf, NULL) < 0) {
+		bt_conn_unref(conn);
+		return NULL;
+	}
+
+	bt_conn_set_state(conn, BT_CONN_INITIATING);
+	conn->role = BT_CONN_ROLE_CENTRAL;
+
+	return conn;
+}
+
+int bt_hci_connect_br_cancel(struct bt_conn *conn)
+{
+	struct bt_hci_cp_connect_cancel *cp;
+	struct bt_hci_rp_connect_cancel *rp;
+	struct net_buf *buf, *rsp;
+	int err;
+
+	buf = bt_hci_cmd_create(BT_HCI_OP_CONNECT_CANCEL, sizeof(*cp));
+	if (!buf) {
+		return -ENOBUFS;
+	}
+
+	cp = net_buf_add(buf, sizeof(*cp));
+	memcpy(&cp->bdaddr, &conn->br.dst, sizeof(cp->bdaddr));
+
+	err = bt_hci_cmd_send_sync(BT_HCI_OP_CONNECT_CANCEL, buf, &rsp);
+	if (err) {
+		return err;
+	}
+
+	rp = (void *)rsp->data;
+
+	err = rp->status ? -EIO : 0;
+
+	net_buf_unref(rsp);
+
+	return err;
+}
+
+const bt_addr_t *bt_conn_get_dst_br(const struct bt_conn *conn)
+{
+	if (conn == NULL) {
+		LOG_DBG("Invalid connect");
+		return NULL;
+	}
+
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_BR)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return NULL;
+	}
+
+	return &conn->br.dst;
+}
diff --git a/subsys/bluetooth/host/classic/conn_br_internal.h b/subsys/bluetooth/host/classic/conn_br_internal.h
new file mode 100644
index 00000000000..7ca84974702
--- /dev/null
+++ b/subsys/bluetooth/host/classic/conn_br_internal.h
@@ -0,0 +1,12 @@
+/** @file
+ *  @brief Internal APIs for Bluetooth classic connection handling.
+ */
+
+/*
+ * Copyright (c) 2015 Intel Corporation
+ * Copyright (c) 2021 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+int bt_hci_connect_br_cancel(struct bt_conn *conn);
diff --git a/subsys/bluetooth/host/classic/hfp_ag.c b/subsys/bluetooth/host/classic/hfp_ag.c
index c9f92f1618c..c21195be4db 100644
--- a/subsys/bluetooth/host/classic/hfp_ag.c
+++ b/subsys/bluetooth/host/classic/hfp_ag.c
@@ -17,6 +17,7 @@
 
 #include <zephyr/bluetooth/classic/rfcomm.h>
 #include <zephyr/bluetooth/classic/hfp_ag.h>
+#include <zephyr/bluetooth/classic/sdp.h>
 
 #include "host/hci_core.h"
 #include "host/conn_internal.h"
@@ -24,8 +25,6 @@
 #include "rfcomm_internal.h"
 #include "at.h"
 #include "sco_internal.h"
-
-#include "hfp_internal.h"
 #include "hfp_ag_internal.h"
 
 #define LOG_LEVEL CONFIG_BT_HFP_AG_LOG_LEVEL
@@ -74,21 +73,95 @@ static struct bt_hfp_ag bt_hfp_ag_pool[CONFIG_BT_MAX_CONN];
 
 static struct bt_hfp_ag_cb *bt_ag;
 
+#define AG_SUPT_FEAT(ag, _feature) ((ag->ag_features & (_feature)) != 0)
+#define HF_SUPT_FEAT(ag, _feature) ((ag->hf_features & (_feature)) != 0)
+#define BOTH_SUPT_FEAT(ag, _hf_feature, _ag_feature) \
+	(HF_SUPT_FEAT(ag, _hf_feature) && AG_SUPT_FEAT(ag, _ag_feature))
+
 /* Sent but not acknowledged TX packets with a callback */
 static struct bt_ag_tx ag_tx[CONFIG_BT_HFP_AG_TX_BUF_COUNT * 2];
 static K_FIFO_DEFINE(ag_tx_free);
 static K_FIFO_DEFINE(ag_tx_notify);
 
-struct k_thread ag_thread;
-static K_KERNEL_STACK_MEMBER(ag_thread_stack, CONFIG_BT_HFP_AG_THREAD_STACK_SIZE);
-static k_tid_t ag_thread_id;
+/* HFP Gateway SDP record */
+static struct bt_sdp_attribute hfp_ag_attrs[] = {
+	BT_SDP_NEW_SERVICE,
+	BT_SDP_LIST(
+		BT_SDP_ATTR_SVCLASS_ID_LIST,
+		BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 6),
+		BT_SDP_DATA_ELEM_LIST(
+		{
+			BT_SDP_TYPE_SIZE(BT_SDP_UUID16),
+			BT_SDP_ARRAY_16(BT_SDP_HANDSFREE_AGW_SVCLASS)
+		},
+		{
+			BT_SDP_TYPE_SIZE(BT_SDP_UUID16),
+			BT_SDP_ARRAY_16(BT_SDP_GENERIC_AUDIO_SVCLASS)
+		}
+		)
+	),
+	BT_SDP_LIST(
+		BT_SDP_ATTR_PROTO_DESC_LIST,
+		BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 12),
+		BT_SDP_DATA_ELEM_LIST(
+		{
+			BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 3),
+			BT_SDP_DATA_ELEM_LIST(
+			{
+				BT_SDP_TYPE_SIZE(BT_SDP_UUID16),
+				BT_SDP_ARRAY_16(BT_SDP_PROTO_L2CAP)
+			},
+			)
+		},
+		{
+			BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 5),
+			BT_SDP_DATA_ELEM_LIST(
+			{
+				BT_SDP_TYPE_SIZE(BT_SDP_UUID16),
+				BT_SDP_ARRAY_16(BT_SDP_PROTO_RFCOMM)
+			},
+			{
+				BT_SDP_TYPE_SIZE(BT_SDP_UINT8),
+				BT_SDP_ARRAY_8(BT_RFCOMM_CHAN_HFP_AG)
+			},
+			)
+		},
+		)
+	),
+	BT_SDP_LIST(
+		BT_SDP_ATTR_PROFILE_DESC_LIST,
+		BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 6),
+		BT_SDP_DATA_ELEM_LIST(
+		{
+			BT_SDP_TYPE_SIZE(BT_SDP_UUID16),
+			BT_SDP_ARRAY_16(BT_SDP_HANDSFREE_SVCLASS)
+		},
+		{
+			BT_SDP_TYPE_SIZE(BT_SDP_UINT16),
+			BT_SDP_ARRAY_16(0x0109)
+		},
+		)
+	),
+
+	BT_SDP_LIST(
+		BT_SDP_ATTR_NETWORK,
+		BT_SDP_TYPE_SIZE(BT_SDP_UINT8),
+		BT_SDP_ARRAY_8(IS_ENABLED(CONFIG_BT_HFP_AG_REJECT_CALL))
+	),
+	/* The values of the “SupportedFeatures” bitmap shall be the same as the
+	 * values of the Bits 0 to 4 of the AT-command AT+BRSF (see Section 5.3).
+	 */
+	BT_SDP_SUPPORTED_FEATURES(BT_HFP_AG_SDP_SUPPORTED_FEATURES),
+};
+
+static struct bt_sdp_record hfp_ag_rec = BT_SDP_RECORD(hfp_ag_attrs);
 
 static enum at_cme bt_hfp_ag_get_cme_err(int err)
 {
 	enum at_cme cme_err;
 
 	switch (err) {
-	case -EOPNOTSUPP:
+	case -ENOEXEC:
 		cme_err = CME_ERROR_OPERATION_NOT_SUPPORTED;
 		break;
 	case -EFAULT:
@@ -98,7 +171,6 @@ static enum at_cme bt_hfp_ag_get_cme_err(int err)
 		cme_err = CME_ERROR_MEMORY_FAILURE;
 		break;
 	case -ENOMEM:
-		__fallthrough;
 	case -ENOBUFS:
 		cme_err = CME_ERROR_MEMORY_FULL;
 		break;
@@ -134,12 +206,19 @@ static void hfp_ag_unlock(struct bt_hfp_ag *ag)
 
 static void bt_hfp_ag_set_state(struct bt_hfp_ag *ag, bt_hfp_state_t state)
 {
-	LOG_DBG("update state %p, old %d -> new %d", ag, ag->state, state);
+	bt_hfp_state_t old_state;
 
 	hfp_ag_lock(ag);
+	old_state = ag->state;
 	ag->state = state;
 	hfp_ag_unlock(ag);
 
+	LOG_DBG("update state %p, old %d -> new %d", ag, old_state, state);
+
+	if (old_state == state) {
+		return;
+	}
+
 	switch (state) {
 	case BT_HFP_DISCONNECTED:
 		if (bt_ag && bt_ag->disconnected) {
@@ -152,7 +231,7 @@ static void bt_hfp_ag_set_state(struct bt_hfp_ag *ag, bt_hfp_state_t state)
 		break;
 	case BT_HFP_CONNECTED:
 		if (bt_ag && bt_ag->connected) {
-			bt_ag->connected(ag);
+			bt_ag->connected(ag->acl_conn, ag);
 		}
 		break;
 	case BT_HFP_DISCONNECTING:
@@ -163,50 +242,70 @@ static void bt_hfp_ag_set_state(struct bt_hfp_ag *ag, bt_hfp_state_t state)
 	}
 }
 
-static void bt_hfp_ag_set_call_state(struct bt_hfp_ag *ag, bt_hfp_call_state_t call_state)
+static struct bt_hfp_ag_call *get_call_from_number(struct bt_hfp_ag *ag, const char *number,
+						   uint8_t type)
 {
-	bt_hfp_state_t state;
+	struct bt_hfp_ag_call *call;
 
-	LOG_DBG("update call state %p, old %d -> new %d", ag, ag->call_state, call_state);
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
 
-	hfp_ag_lock(ag);
-	ag->call_state = call_state;
-	state = ag->state;
-	hfp_ag_unlock(ag);
+		if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			continue;
+		}
 
-	switch (call_state) {
-	case BT_HFP_CALL_TERMINATE:
-		atomic_clear(ag->flags);
-		k_work_cancel_delayable(&ag->deferred_work);
-		break;
-	case BT_HFP_CALL_OUTGOING:
-		k_work_reschedule(&ag->deferred_work, K_SECONDS(CONFIG_BT_HFP_AG_OUTGOING_TIMEOUT));
-		break;
-	case BT_HFP_CALL_INCOMING:
-		k_work_reschedule(&ag->deferred_work, K_SECONDS(CONFIG_BT_HFP_AG_INCOMING_TIMEOUT));
-		break;
-	case BT_HFP_CALL_ALERTING:
-		k_work_reschedule(&ag->ringing_work, K_NO_WAIT);
-		k_work_reschedule(&ag->deferred_work, K_SECONDS(CONFIG_BT_HFP_AG_ALERTING_TIMEOUT));
-		break;
-	case BT_HFP_CALL_ACTIVE:
-		k_work_cancel_delayable(&ag->ringing_work);
-		k_work_cancel_delayable(&ag->deferred_work);
-		break;
-	case BT_HFP_CALL_HOLD:
-		break;
-	default:
-		/* Invalid state */
-		break;
+		if (call->type != type) {
+			continue;
+		}
+
+		if (strcmp(call->number, number)) {
+			continue;
+		}
+
+		return call;
 	}
 
-	if (state == BT_HFP_DISCONNECTING) {
-		int err = bt_rfcomm_dlc_disconnect(&ag->rfcomm_dlc);
+	return NULL;
+}
 
-		if (err) {
-			LOG_ERR("Fail to disconnect DLC %p", &ag->rfcomm_dlc);
+static void bt_ag_deferred_work(struct k_work *work);
+static void bt_ag_ringing_work(struct k_work *work);
+
+static struct bt_hfp_ag_call *get_new_call(struct bt_hfp_ag *ag, const char *number, uint8_t type)
+{
+	struct bt_hfp_ag_call *call;
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (!atomic_test_and_set_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			/* Copy number to ag->number including null-character */
+			strcpy(call->number, number);
+			call->type = type;
+			call->ag = ag;
+			k_work_init_delayable(&call->deferred_work, bt_ag_deferred_work);
+			k_work_init_delayable(&call->ringing_work, bt_ag_ringing_work);
+			return call;
+		}
+	}
+
+	return NULL;
+}
+
+static int get_none_released_calls(struct bt_hfp_ag *ag)
+{
+	struct bt_hfp_ag_call *call;
+	int count = 0;
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			count++;
 		}
 	}
+
+	return count;
 }
 
 static struct bt_ag_tx *bt_ag_tx_alloc(void)
@@ -266,67 +365,11 @@ static int hfp_ag_next_step(struct bt_hfp_ag *ag, bt_hfp_ag_tx_cb_t cb, void *us
 	return 0;
 }
 
-static int hfp_ag_send(struct bt_hfp_ag *ag, struct bt_ag_tx *tx)
-{
-	int err = bt_rfcomm_dlc_send(&ag->rfcomm_dlc, tx->buf);
-
-	if (err < 0) {
-		net_buf_unref(tx->buf);
-	}
-
-	return err;
-}
-
-static void bt_ag_tx_work(struct k_work *work)
-{
-	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
-	struct bt_hfp_ag *ag = CONTAINER_OF(dwork, struct bt_hfp_ag, tx_work);
-	sys_snode_t *node;
-	struct bt_ag_tx *tx;
-	bt_hfp_state_t state;
-
-	hfp_ag_lock(ag);
-	state = ag->state;
-	if ((state == BT_HFP_DISCONNECTED) || (state == BT_HFP_DISCONNECTING)) {
-		LOG_ERR("AG %p is not connected", ag);
-		goto unlock;
-	}
-
-	node = sys_slist_peek_head(&ag->tx_pending);
-	if (!node) {
-		LOG_DBG("No pending tx");
-		goto unlock;
-	}
-
-	tx = CONTAINER_OF(node, struct bt_ag_tx, node);
-
-	if (!atomic_test_and_set_bit(ag->flags, BT_HFP_AG_TX_ONGOING)) {
-		LOG_DBG("AG %p sending tx %p", ag, tx);
-		int err = hfp_ag_send(ag, tx);
-
-		if (err < 0) {
-			LOG_ERR("Rfcomm send error :(%d)", err);
-			sys_slist_find_and_remove(&ag->tx_pending, &tx->node);
-			tx->err = err;
-			k_fifo_put(&ag_tx_notify, tx);
-			/* Clear the tx ongoing flag */
-			if (!atomic_test_and_clear_bit(ag->flags, BT_HFP_AG_TX_ONGOING)) {
-				LOG_WRN("tx ongoing flag is not set");
-			}
-			/* Due to the work is failed, restart the tx work */
-			k_work_reschedule(&ag->tx_work, K_NO_WAIT);
-		}
-	}
-
-unlock:
-	hfp_ag_unlock(ag);
-}
-
 static int hfp_ag_send_data(struct bt_hfp_ag *ag, bt_hfp_ag_tx_cb_t cb, void *user_data,
 			    const char *format, ...)
 {
-	struct net_buf *buf;
-	struct bt_ag_tx *tx;
+	struct net_buf *buf = NULL;
+	struct bt_ag_tx *tx = NULL;
 	va_list vargs;
 	int err;
 	bt_hfp_state_t state;
@@ -338,20 +381,22 @@ static int hfp_ag_send_data(struct bt_hfp_ag *ag, bt_hfp_ag_tx_cb_t cb, void *us
 	hfp_ag_unlock(ag);
 	if ((state == BT_HFP_DISCONNECTED) || (state == BT_HFP_DISCONNECTING)) {
 		LOG_ERR("AG %p is not connected", ag);
-		return -ENOTCONN;
+		err = -ENOTCONN;
+		goto failed;
 	}
 
 	buf = bt_rfcomm_create_pdu(&ag_pool);
 	if (!buf) {
 		LOG_ERR("No Buffers!");
-		return -ENOMEM;
+		err = -ENOMEM;
+		goto failed;
 	}
 
 	tx = bt_ag_tx_alloc();
 	if (tx == NULL) {
 		LOG_ERR("No tx buffers!");
-		net_buf_unref(buf);
-		return -ENOMEM;
+		err = -ENOMEM;
+		goto failed;
 	}
 
 	LOG_DBG("buf %p tx %p", buf, tx);
@@ -367,9 +412,7 @@ static int hfp_ag_send_data(struct bt_hfp_ag *ag, bt_hfp_ag_tx_cb_t cb, void *us
 
 	if (err < 0) {
 		LOG_ERR("Unable to format variable arguments");
-		net_buf_unref(buf);
-		bt_ag_tx_free(tx);
-		return err;
+		goto failed;
 	}
 
 	net_buf_add(buf, err);
@@ -384,133 +427,2278 @@ static int hfp_ag_send_data(struct bt_hfp_ag *ag, bt_hfp_ag_tx_cb_t cb, void *us
 	k_work_reschedule(&ag->tx_work, K_NO_WAIT);
 
 	return 0;
-}
 
-static void skip_space(struct net_buf *buf)
-{
-	while ((buf->len > 0) && (buf->data[0] == ' ')) {
-		(void)net_buf_pull(buf, 1);
+failed:
+	if (buf) {
+		net_buf_unref(buf);
+	}
+
+	if (tx) {
+		bt_ag_tx_free(tx);
 	}
+	bt_hfp_ag_disconnect(ag);
+	return err;
 }
 
-static int get_number(struct net_buf *buf, uint32_t *number)
+static int hfp_ag_update_indicator(struct bt_hfp_ag *ag, enum bt_hfp_ag_indicator index,
+				   uint8_t value, bt_hfp_ag_tx_cb_t cb, void *user_data)
 {
-	int err = -EINVAL;
+	int err;
+	uint8_t old_value;
 
-	*number = 0;
+	if (index >= BT_HFP_AG_IND_MAX) {
+		return -EINVAL;
+	}
 
-	skip_space(buf);
-	while (buf->len > 0) {
-		if ((buf->data[0] >= '0') && (buf->data[0] <= '9')) {
-			*number = *number * 10 + buf->data[0] - '0';
-			(void)net_buf_pull(buf, 1);
-			err = 0;
-		} else {
-			break;
+	if ((ag_ind[index].max < value) || (ag_ind[index].min > value)) {
+		return -EINVAL;
+	}
+
+	hfp_ag_lock(ag);
+	old_value = ag->indicator_value[index];
+	if (value == old_value) {
+		LOG_ERR("Duplicate value setting, indicator %d, old %d -> new %d", index, old_value,
+			value);
+		hfp_ag_unlock(ag);
+		if (cb) {
+			cb(ag, user_data);
 		}
+		return -EINVAL;
 	}
-	skip_space(buf);
 
-	return err;
-}
+	ag->indicator_value[index] = value;
+	hfp_ag_unlock(ag);
 
-static bool is_char(struct net_buf *buf, uint8_t c)
-{
-	bool found = false;
+	LOG_DBG("indicator %d, old %d -> new %d", index, old_value, value);
 
-	skip_space(buf);
-	if (buf->len > 0) {
-		if (buf->data[0] == c) {
-			(void)net_buf_pull(buf, 1);
-			found = true;
-		}
+	if (!(ag->indicator & BIT(index))) {
+		LOG_INF("The indicator %d is deactivated", index);
+		/* If the indicator is deactivated, consider it a successful set. */
+		return 0;
 	}
-	skip_space(buf);
 
-	return found;
+	err = hfp_ag_send_data(ag, cb, user_data, "\r\n+CIEV:%d,%d\r\n", (uint8_t)index + 1, value);
+	if (err) {
+		hfp_ag_lock(ag);
+		ag->indicator_value[index] = old_value;
+		hfp_ag_unlock(ag);
+		LOG_ERR("Fail to update indicator %d, current %d", index, old_value);
+	}
+
+	return err;
 }
 
-static int bt_hfp_ag_brsf_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+static int hfp_ag_force_update_indicator(struct bt_hfp_ag *ag, enum bt_hfp_ag_indicator index,
+					 uint8_t value, bt_hfp_ag_tx_cb_t cb, void *user_data)
 {
-	uint32_t hf_features;
 	int err;
+	uint8_t old_value;
 
-	if (!is_char(buf, '=')) {
-		return -ENOTSUP;
-	}
+	hfp_ag_lock(ag);
+	old_value = ag->indicator_value[index];
+	ag->indicator_value[index] = value;
+	hfp_ag_unlock(ag);
 
-	err = get_number(buf, &hf_features);
-	if (err != 0) {
-		return -ENOTSUP;
-	}
+	LOG_DBG("indicator %d, old %d -> new %d", index, old_value, value);
 
-	if (!is_char(buf, '\r')) {
-		return -ENOTSUP;
+	err = hfp_ag_send_data(ag, cb, user_data, "\r\n+CIEV:%d,%d\r\n", (uint8_t)index + 1, value);
+	if (err) {
+		hfp_ag_lock(ag);
+		ag->indicator_value[index] = old_value;
+		hfp_ag_unlock(ag);
+		LOG_ERR("Fail to update indicator %d, current %d", index, old_value);
 	}
 
-	hfp_ag_lock(ag);
-	ag->hf_features = hf_features;
-	hfp_ag_unlock(ag);
-
-	return hfp_ag_send_data(ag, NULL, NULL, "\r\n+BRSF:%d\r\n", ag->ag_features);
+	return err;
 }
 
-static int bt_hfp_ag_bac_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+static void clear_call_setup_ind_cb(struct bt_hfp_ag *ag, void *user_data)
 {
-	uint32_t codec;
-	uint32_t codec_ids = 0U;
-	int err = 0;
-
-	if (!is_char(buf, '=')) {
-		return -ENOTSUP;
-	}
+	uint8_t call_ind;
+	int err;
 
 	hfp_ag_lock(ag);
-	if (!(ag->hf_features & BT_HFP_HF_FEATURE_CODEC_NEG) ||
-	    !(ag->ag_features & BT_HFP_AG_FEATURE_CODEC_NEG)) {
-		hfp_ag_unlock(ag);
-		return -EOPNOTSUPP;
-	}
+	call_ind = ag->indicator_value[BT_HFP_AG_CALL_IND];
 	hfp_ag_unlock(ag);
 
-	while (buf->len > 0) {
-		err = get_number(buf, &codec);
-		if (err != 0) {
-			return -ENOTSUP;
-		}
-
-		if (!is_char(buf, ',')) {
-			if (!is_char(buf, '\r')) {
-				return -ENOTSUP;
-			}
-		}
-
-		if (codec < (sizeof(codec_ids) * 8)) {
-			codec_ids |= BIT(codec);
+	if (call_ind) {
+		err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 0, NULL, NULL);
+		if (err) {
+			LOG_ERR("Fail to clear call_setup ind");
 		}
 	}
+}
+
+static void clear_call_ind_cb(struct bt_hfp_ag *ag, void *user_data)
+{
+	uint8_t call_setup_ind;
+	int err;
 
 	hfp_ag_lock(ag);
-	ag->hf_codec_ids = codec_ids;
+	call_setup_ind = ag->indicator_value[BT_HFP_AG_CALL_SETUP_IND];
 	hfp_ag_unlock(ag);
 
-	if (bt_ag && bt_ag->codec) {
-		bt_ag->codec(ag, ag->hf_codec_ids);
+	if (call_setup_ind) {
+		err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_NONE,
+					      NULL, NULL);
+		if (err) {
+			LOG_ERR("Fail to clear call_setup ind");
+		}
 	}
-
-	return 0;
 }
 
-static int bt_hfp_ag_cind_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+static void clear_call_and_call_setup_ind(struct bt_hfp_ag *ag)
 {
+	uint8_t call_setup_ind;
+	uint8_t call_ind;
 	int err;
-	bool inquiry_status = true;
 
-	if (is_char(buf, '=')) {
-		inquiry_status = false;
-	}
+	hfp_ag_lock(ag);
+	call_setup_ind = ag->indicator_value[BT_HFP_AG_CALL_SETUP_IND];
+	call_ind = ag->indicator_value[BT_HFP_AG_CALL_IND];
+	hfp_ag_unlock(ag);
+
+	if (call_setup_ind) {
+		err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_NONE,
+					      clear_call_setup_ind_cb, NULL);
+		if (err) {
+			LOG_ERR("Fail to clear call_setup ind");
+		}
+	}
+
+	if (call_ind) {
+		err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 0, clear_call_ind_cb, NULL);
+		if (err) {
+			LOG_ERR("Fail to clear call ind");
+		}
+	}
+}
+
+static int get_active_calls(struct bt_hfp_ag *ag)
+{
+	struct bt_hfp_ag_call *call;
+	int count = 0;
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			hfp_ag_lock(ag);
+			if ((call->call_state == BT_HFP_CALL_ACTIVE) &&
+			    (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING_HELD))) {
+				count++;
+			}
+			hfp_ag_unlock(ag);
+		}
+	}
+
+	return count;
+}
+
+#if defined(CONFIG_BT_HFP_AG_3WAY_CALL)
+static int get_active_held_calls(struct bt_hfp_ag *ag)
+{
+	struct bt_hfp_ag_call *call;
+	int count = 0;
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			hfp_ag_lock(ag);
+			if ((call->call_state == BT_HFP_CALL_HOLD) ||
+			    ((call->call_state == BT_HFP_CALL_ACTIVE) &&
+			     (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING_HELD)))) {
+				count++;
+			}
+			hfp_ag_unlock(ag);
+		}
+	}
+
+	return count;
+}
+#endif /* CONFIG_BT_HFP_AG_3WAY_CALL */
+
+static int get_held_calls(struct bt_hfp_ag *ag)
+{
+	struct bt_hfp_ag_call *call;
+	int count = 0;
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			hfp_ag_lock(ag);
+			if ((call->call_state == BT_HFP_CALL_ACTIVE) &&
+			    (atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING_HELD))) {
+				count++;
+			} else if (call->call_state == BT_HFP_CALL_HOLD) {
+				count++;
+			}
+			hfp_ag_unlock(ag);
+		}
+	}
+
+	return count;
+}
+
+static void ag_notify_call_held_ind(struct bt_hfp_ag *ag, void *user_data)
+{
+	int active_call_count;
+	int held_call_count;
+	int err;
+	uint8_t value;
+
+	active_call_count = get_active_calls(ag);
+	held_call_count = get_held_calls(ag);
+	if (active_call_count && held_call_count) {
+		value = BT_HFP_CALL_HELD_ACTIVE_HELD;
+	} else if (held_call_count) {
+		value = BT_HFP_CALL_HELD_HELD;
+	} else {
+		value = BT_HFP_CALL_HELD_NONE;
+	}
+
+	err = hfp_ag_force_update_indicator(ag, BT_HFP_AG_CALL_HELD_IND, value, NULL, NULL);
+	if (err) {
+		LOG_ERR("Fail to notify call_held ind :(%d)", err);
+	}
+}
+
+static void release_call(struct bt_hfp_ag_call *call)
+{
+	atomic_clear_bit(call->flags, BT_HFP_AG_CALL_IN_USING);
+	k_work_cancel_delayable(&call->ringing_work);
+	k_work_cancel_delayable(&call->deferred_work);
+	/*
+	 * Because it is uncertain whether `ringing_work` and `deferred_work` have been cancelled,
+	 * do not clear ringing_work and deferred_work.
+	 * Use `offsetof()` to get the offset of `ringing_work` to avoid access the fields
+	 * `ringing_work` and `deferred_work`.
+	 */
+	(void)memset(call, 0, offsetof(struct bt_hfp_ag_call, ringing_work));
+}
+
+static void free_call(struct bt_hfp_ag_call *call)
+{
+	int call_count;
+	struct bt_hfp_ag *ag;
+	int err;
+
+	ag = call->ag;
+
+	release_call(call);
+
+	call_count = get_none_released_calls(ag);
+
+	if (!call_count) {
+		clear_call_and_call_setup_ind(ag);
+	} else {
+		err = hfp_ag_next_step(ag, ag_notify_call_held_ind, NULL);
+		if (err) {
+			LOG_ERR("Fail to notify call_held ind :(%d)", err);
+		}
+	}
+}
+
+static void bt_hfp_ag_set_call_state(struct bt_hfp_ag_call *call, bt_hfp_call_state_t call_state)
+{
+	bt_hfp_state_t state;
+	struct bt_hfp_ag *ag = call->ag;
+
+	LOG_DBG("update call state %p, old %d -> new %d", call, call->call_state, call_state);
+
+	hfp_ag_lock(ag);
+	call->call_state = call_state;
+	state = ag->state;
+	hfp_ag_unlock(ag);
+
+	switch (call_state) {
+	case BT_HFP_CALL_TERMINATE:
+		atomic_clear_bit(ag->flags, BT_HFP_AG_CREATING_SCO);
+		free_call(call);
+		break;
+	case BT_HFP_CALL_OUTGOING:
+		k_work_reschedule(&call->deferred_work,
+				  K_SECONDS(CONFIG_BT_HFP_AG_OUTGOING_TIMEOUT));
+		break;
+	case BT_HFP_CALL_INCOMING:
+		k_work_reschedule(&call->deferred_work,
+				  K_SECONDS(CONFIG_BT_HFP_AG_INCOMING_TIMEOUT));
+		break;
+	case BT_HFP_CALL_ALERTING:
+		if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING_3WAY)) {
+			k_work_reschedule(&call->ringing_work, K_NO_WAIT);
+		} else {
+			k_work_cancel_delayable(&call->ringing_work);
+		}
+		k_work_reschedule(&call->deferred_work,
+				  K_SECONDS(CONFIG_BT_HFP_AG_ALERTING_TIMEOUT));
+		break;
+	case BT_HFP_CALL_ACTIVE:
+		k_work_cancel_delayable(&call->ringing_work);
+		k_work_cancel_delayable(&call->deferred_work);
+		break;
+	case BT_HFP_CALL_HOLD:
+		break;
+	default:
+		/* Invalid state */
+		break;
+	}
+
+	if (state == BT_HFP_DISCONNECTING) {
+		int err = bt_rfcomm_dlc_disconnect(&ag->rfcomm_dlc);
+
+		if (err) {
+			LOG_ERR("Fail to disconnect DLC %p", &ag->rfcomm_dlc);
+		}
+	}
+}
+
+static void hfp_ag_close_sco(struct bt_hfp_ag *ag)
+{
+	struct bt_conn *sco;
+	int call_count;
+
+	LOG_DBG("");
+
+	hfp_ag_lock(ag);
+	call_count = get_none_released_calls(ag);
+	if (call_count > 0) {
+		LOG_INF("Do not close sco because not all calls are released");
+		hfp_ag_unlock(ag);
+		return;
+	}
+
+	sco = ag->sco_chan.sco;
+	ag->sco_chan.sco = NULL;
+	hfp_ag_unlock(ag);
+	if (sco != NULL) {
+		LOG_DBG("Disconnect sco %p", sco);
+		bt_conn_disconnect(sco, BT_HCI_ERR_LOCALHOST_TERM_CONN);
+	}
+}
+
+static void ag_reject_call(struct bt_hfp_ag_call *call)
+{
+	struct bt_hfp_ag *ag;
+
+	ag = call->ag;
+
+	if (bt_ag && bt_ag->reject) {
+		bt_ag->reject(call);
+	}
+
+	bt_hfp_ag_set_call_state(call, BT_HFP_CALL_TERMINATE);
+
+	if (!atomic_test_bit(ag->flags, BT_HFP_AG_AUDIO_CONN)) {
+		LOG_DBG("It is not audio connection");
+		hfp_ag_close_sco(ag);
+	}
+}
+
+static void ag_terminate_call(struct bt_hfp_ag_call *call)
+{
+	struct bt_hfp_ag *ag;
+
+	ag = call->ag;
+
+	if (bt_ag && bt_ag->terminate) {
+		bt_ag->terminate(call);
+	}
+
+	bt_hfp_ag_set_call_state(call, BT_HFP_CALL_TERMINATE);
+
+	if (!atomic_test_bit(ag->flags, BT_HFP_AG_AUDIO_CONN)) {
+		LOG_DBG("It is not audio connection");
+		hfp_ag_close_sco(ag);
+	}
+}
+
+static int hfp_ag_send(struct bt_hfp_ag *ag, struct bt_ag_tx *tx)
+{
+	int err = bt_rfcomm_dlc_send(&ag->rfcomm_dlc, tx->buf);
+
+	if (err < 0) {
+		net_buf_unref(tx->buf);
+	}
+
+	return err;
+}
+
+static void bt_ag_tx_work(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct bt_hfp_ag *ag = CONTAINER_OF(dwork, struct bt_hfp_ag, tx_work);
+	sys_snode_t *node;
+	struct bt_ag_tx *tx;
+	bt_hfp_state_t state;
+
+	hfp_ag_lock(ag);
+	state = ag->state;
+	if ((state == BT_HFP_DISCONNECTED) || (state == BT_HFP_DISCONNECTING)) {
+		LOG_ERR("AG %p is not connected", ag);
+		goto unlock;
+	}
+
+	node = sys_slist_peek_head(&ag->tx_pending);
+	if (!node) {
+		LOG_DBG("No pending tx");
+		goto unlock;
+	}
+
+	tx = CONTAINER_OF(node, struct bt_ag_tx, node);
+
+	if (!atomic_test_and_set_bit(ag->flags, BT_HFP_AG_TX_ONGOING)) {
+		LOG_DBG("AG %p sending tx %p", ag, tx);
+		int err = hfp_ag_send(ag, tx);
+
+		if (err < 0) {
+			LOG_ERR("Rfcomm send error :(%d)", err);
+			sys_slist_find_and_remove(&ag->tx_pending, &tx->node);
+			tx->err = err;
+			k_fifo_put(&ag_tx_notify, tx);
+			/* Clear the tx ongoing flag */
+			if (!atomic_test_and_clear_bit(ag->flags, BT_HFP_AG_TX_ONGOING)) {
+				LOG_WRN("tx ongoing flag is not set");
+			}
+			/* Due to the work is failed, restart the tx work */
+			k_work_reschedule(&ag->tx_work, K_NO_WAIT);
+		}
+	}
+
+unlock:
+	hfp_ag_unlock(ag);
+}
+
+static void skip_space(struct net_buf *buf)
+{
+	size_t count = 0;
+
+	while ((buf->len > count) && (buf->data[count] == ' ')) {
+		count++;
+	}
+
+	if (count > 0) {
+		(void)net_buf_pull(buf, count);
+	}
+}
+
+static int get_number(struct net_buf *buf, uint32_t *number)
+{
+	int err = -EINVAL;
+
+	*number = 0;
+
+	skip_space(buf);
+	while (buf->len > 0) {
+		if ((buf->data[0] >= '0') && (buf->data[0] <= '9')) {
+			*number = *number * 10 + buf->data[0] - '0';
+			(void)net_buf_pull(buf, 1);
+			err = 0;
+		} else {
+			break;
+		}
+	}
+	skip_space(buf);
+
+	return err;
+}
+
+static int get_char(struct net_buf *buf, char *c)
+{
+	int err = -EINVAL;
+
+	skip_space(buf);
+	if (buf->len > 0) {
+		*c = (char)buf->data[0];
+		(void)net_buf_pull(buf, 1);
+		err = 0;
+	}
+	skip_space(buf);
+
+	return err;
+}
+
+static bool is_char(struct net_buf *buf, uint8_t c)
+{
+	bool found = false;
+
+	skip_space(buf);
+	if (buf->len > 0) {
+		if (buf->data[0] == c) {
+			(void)net_buf_pull(buf, 1);
+			found = true;
+		}
+	}
+	skip_space(buf);
+
+	return found;
+}
+
+static int bt_hfp_ag_brsf_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	uint32_t hf_features;
+	int err;
+
+	if (!is_char(buf, '=')) {
+		return -ENOTSUP;
+	}
+
+	err = get_number(buf, &hf_features);
+	if (err != 0) {
+		return -ENOTSUP;
+	}
+
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	ag->hf_features = hf_features;
+
+	return hfp_ag_send_data(ag, NULL, NULL, "\r\n+BRSF:%d\r\n", ag->ag_features);
+}
+
+static int bt_hfp_ag_bac_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	uint32_t codec;
+	uint32_t codec_ids = 0U;
+	int err = 0;
+
+	if (!is_char(buf, '=')) {
+		return -ENOTSUP;
+	}
+
+	if (!BOTH_SUPT_FEAT(ag, BT_HFP_HF_FEATURE_CODEC_NEG, BT_HFP_AG_FEATURE_CODEC_NEG)) {
+		return -ENOEXEC;
+	}
+
+	while (buf->len > 0) {
+		err = get_number(buf, &codec);
+		if (err != 0) {
+			return -ENOTSUP;
+		}
+
+		if (!is_char(buf, ',')) {
+			if (!is_char(buf, '\r')) {
+				return -ENOTSUP;
+			}
+		}
+
+		if (codec < NUM_BITS(sizeof(codec_ids))) {
+			codec_ids |= BIT(codec);
+		}
+	}
+
+	if (!(codec_ids & BIT(BT_HFP_AG_CODEC_CVSD))) {
+		return -ENOEXEC;
+	}
+
+	hfp_ag_lock(ag);
+	ag->hf_codec_ids = codec_ids;
+	ag->selected_codec_id = 0;
+	hfp_ag_unlock(ag);
+
+	atomic_set_bit(ag->flags, BT_HFP_AG_CODEC_CHANGED);
+
+	if (atomic_test_and_clear_bit(ag->flags, BT_HFP_AG_CODEC_CONN)) {
+		/* Codec connection is ended. It needs to be restarted. */
+		LOG_DBG("Codec connection is ended. It needs to be restarted.");
+		if (bt_ag && bt_ag->codec_negotiate) {
+			bt_ag->codec_negotiate(ag, -EAGAIN);
+		}
+	}
+
+	if (bt_ag && bt_ag->codec) {
+		bt_ag->codec(ag, ag->hf_codec_ids);
+	}
+
+	return 0;
+}
+
+static int bt_hfp_ag_cind_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	int err;
+	bool inquiry_status = true;
+
+	if (is_char(buf, '=')) {
+		inquiry_status = false;
+	}
+
+	if (!is_char(buf, '?')) {
+		return -ENOTSUP;
+	}
+
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	if (!inquiry_status) {
+		err = hfp_ag_send_data(
+			ag, NULL, NULL,
+			"\r\n+CIND:(\"%s\",(%d%s%d)),(\"%s\",(%d%s%d)),(\"%s\",(%d%s%d)),(\"%s\",(%"
+			"d%s%d)),(\"%s\",(%d%s%d)),(\"%s\",(%d%s%d)),(\"%s\",(%d%s%d))\r\n",
+			ag_ind[BT_HFP_AG_SERVICE_IND].name, ag_ind[BT_HFP_AG_SERVICE_IND].min,
+			ag_ind[BT_HFP_AG_SERVICE_IND].connector, ag_ind[BT_HFP_AG_SERVICE_IND].max,
+			ag_ind[BT_HFP_AG_CALL_IND].name, ag_ind[BT_HFP_AG_CALL_IND].min,
+			ag_ind[BT_HFP_AG_CALL_IND].connector, ag_ind[BT_HFP_AG_CALL_IND].max,
+			ag_ind[BT_HFP_AG_CALL_SETUP_IND].name, ag_ind[BT_HFP_AG_CALL_SETUP_IND].min,
+			ag_ind[BT_HFP_AG_CALL_SETUP_IND].connector,
+			ag_ind[BT_HFP_AG_CALL_SETUP_IND].max, ag_ind[BT_HFP_AG_CALL_HELD_IND].name,
+			ag_ind[BT_HFP_AG_CALL_HELD_IND].min,
+			ag_ind[BT_HFP_AG_CALL_HELD_IND].connector,
+			ag_ind[BT_HFP_AG_CALL_HELD_IND].max, ag_ind[BT_HFP_AG_SIGNAL_IND].name,
+			ag_ind[BT_HFP_AG_SIGNAL_IND].min, ag_ind[BT_HFP_AG_SIGNAL_IND].connector,
+			ag_ind[BT_HFP_AG_SIGNAL_IND].max, ag_ind[BT_HFP_AG_ROAM_IND].name,
+			ag_ind[BT_HFP_AG_ROAM_IND].min, ag_ind[BT_HFP_AG_ROAM_IND].connector,
+			ag_ind[BT_HFP_AG_ROAM_IND].max, ag_ind[BT_HFP_AG_BATTERY_IND].name,
+			ag_ind[BT_HFP_AG_BATTERY_IND].min, ag_ind[BT_HFP_AG_BATTERY_IND].connector,
+			ag_ind[BT_HFP_AG_BATTERY_IND].max);
+	} else {
+		err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+CIND:%d,%d,%d,%d,%d,%d,%d\r\n",
+					 ag->indicator_value[BT_HFP_AG_SERVICE_IND],
+					 ag->indicator_value[BT_HFP_AG_CALL_IND],
+					 ag->indicator_value[BT_HFP_AG_CALL_SETUP_IND],
+					 ag->indicator_value[BT_HFP_AG_CALL_HELD_IND],
+					 ag->indicator_value[BT_HFP_AG_SIGNAL_IND],
+					 ag->indicator_value[BT_HFP_AG_ROAM_IND],
+					 ag->indicator_value[BT_HFP_AG_BATTERY_IND]);
+	}
+
+	return err;
+}
+
+static void bt_hfp_ag_set_in_band_ring(struct bt_hfp_ag *ag, void *user_data)
+{
+	bool is_inband_ringtone;
+
+	is_inband_ringtone = AG_SUPT_FEAT(ag, BT_HFP_AG_FEATURE_INBAND_RINGTONE) ? true : false;
+
+	if (is_inband_ringtone && !atomic_test_bit(ag->flags, BT_HFP_AG_INBAND_RING)) {
+		int err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+BSIR:1\r\n");
+
+		atomic_set_bit_to(ag->flags, BT_HFP_AG_INBAND_RING, err == 0);
+	}
+}
+
+static void bt_hfp_ag_slc_connected(struct bt_hfp_ag *ag, void *user_data)
+{
+	bt_hfp_ag_set_state(ag, BT_HFP_CONNECTED);
+	(void)hfp_ag_next_step(ag, bt_hfp_ag_set_in_band_ring, NULL);
+}
+
+static int bt_hfp_ag_cmer_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	uint32_t number;
+	int err;
+	static const uint32_t command_line_prefix[] = {3, 0, 0};
+
+	if (!is_char(buf, '=')) {
+		return -ENOTSUP;
+	}
+
+	for (int i = 0; i < ARRAY_SIZE(command_line_prefix); i++) {
+		err = get_number(buf, &number);
+		if (err != 0) {
+			return -ENOTSUP;
+		}
+
+		if (!is_char(buf, ',')) {
+			return -ENOTSUP;
+		}
+
+		if (command_line_prefix[i] != number) {
+			return -ENOTSUP;
+		}
+	}
+
+	err = get_number(buf, &number);
+	if (err != 0) {
+		return -ENOTSUP;
+	}
+
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	if (number == 1) {
+		atomic_set_bit(ag->flags, BT_HFP_AG_CMER_ENABLE);
+		if (BOTH_SUPT_FEAT(ag, BT_HFP_HF_FEATURE_3WAY_CALL, BT_HFP_AG_FEATURE_3WAY_CALL)) {
+			LOG_DBG("Waiting for AT+CHLD=?");
+			return 0;
+		}
+
+		err = hfp_ag_next_step(ag, bt_hfp_ag_slc_connected, NULL);
+		return err;
+	} else if (number == 0) {
+		atomic_clear_bit(ag->flags, BT_HFP_AG_CMER_ENABLE);
+	} else {
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static void bt_hfp_ag_accept_cb(struct bt_hfp_ag *ag, void *user_data)
+{
+	struct bt_hfp_ag_call *call = (struct bt_hfp_ag_call *)user_data;
+
+	bt_hfp_ag_set_call_state(call, BT_HFP_CALL_ACTIVE);
+
+	if (bt_ag && bt_ag->accept) {
+		bt_ag->accept(call);
+	}
+}
+
+#if defined(CONFIG_BT_HFP_AG_3WAY_CALL)
+static int chld_release_all(struct bt_hfp_ag *ag)
+{
+	struct bt_hfp_ag_call *call;
+	bt_hfp_call_state_t call_state;
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			continue;
+		}
+
+		hfp_ag_lock(ag);
+		call_state = call->call_state;
+		hfp_ag_unlock(ag);
+
+		if ((call_state != BT_HFP_CALL_ACTIVE) ||
+		    ((call_state == BT_HFP_CALL_ACTIVE) &&
+		     atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING_HELD))) {
+			ag_terminate_call(call);
+		}
+	}
+
+	ag_notify_call_held_ind(ag, NULL);
+
+	return 0;
+}
+
+static void bt_hfp_ag_accept_other_cb(struct bt_hfp_ag *ag, void *user_data)
+{
+	struct bt_hfp_ag_call *call = (struct bt_hfp_ag_call *)user_data;
+	bt_hfp_call_state_t call_state;
+	int err;
+
+	if (!call) {
+		return;
+	}
+
+	hfp_ag_lock(ag);
+	call_state = call->call_state;
+	hfp_ag_unlock(ag);
+
+	bt_hfp_ag_set_call_state(call, BT_HFP_CALL_ACTIVE);
+
+	if (call_state == BT_HFP_CALL_HOLD) {
+		err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_HELD_IND,
+					      BT_HFP_CALL_HELD_ACTIVE_HELD, NULL, NULL);
+		if (err) {
+			LOG_ERR("Fail to send err :(%d)", err);
+		}
+	}
+
+	if (call_state == BT_HFP_CALL_HOLD) {
+		if (bt_ag && bt_ag->retrieve) {
+			bt_ag->retrieve(call);
+		}
+	} else {
+		if (bt_ag && bt_ag->accept) {
+			bt_ag->accept(call);
+		}
+	}
+
+	ag_notify_call_held_ind(ag, NULL);
+}
+
+static void bt_hfp_ag_deactivate_accept_other_cb(struct bt_hfp_ag *ag, void *user_data)
+{
+	int err;
+	uint8_t call_setup;
+
+	hfp_ag_lock(ag);
+	call_setup = ag->indicator_value[BT_HFP_AG_CALL_SETUP_IND];
+	hfp_ag_unlock(ag);
+
+	if (call_setup) {
+		err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_NONE,
+					      bt_hfp_ag_accept_other_cb, user_data);
+		if (err) {
+			LOG_ERR("Fail to send err :(%d)", err);
+		}
+	} else {
+		bt_hfp_ag_accept_other_cb(ag, user_data);
+	}
+}
+
+static struct bt_hfp_ag_call *get_none_accept_calls(struct bt_hfp_ag *ag)
+{
+	struct bt_hfp_ag_call *call;
+	bt_hfp_call_state_t call_state;
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			continue;
+		}
+
+		hfp_ag_lock(ag);
+		call_state = call->call_state;
+		hfp_ag_unlock(ag);
+
+		if ((call_state == BT_HFP_CALL_OUTGOING) || (call_state == BT_HFP_CALL_INCOMING) ||
+		    (call_state == BT_HFP_CALL_ALERTING)) {
+			return call;
+		}
+	}
+
+	return NULL;
+}
+
+static struct bt_hfp_ag_call *get_none_active_calls(struct bt_hfp_ag *ag)
+{
+	struct bt_hfp_ag_call *call;
+	bt_hfp_call_state_t call_state;
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			continue;
+		}
+
+		hfp_ag_lock(ag);
+		call_state = call->call_state;
+		hfp_ag_unlock(ag);
+
+		if (call_state != BT_HFP_CALL_ACTIVE) {
+			return call;
+		} else if ((call_state == BT_HFP_CALL_ACTIVE) &&
+			   atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING_HELD)) {
+			return call;
+		}
+	}
+
+	return NULL;
+}
+
+static int chld_deactivate_calls_and_accept_other_call(struct bt_hfp_ag *ag, bool release)
+{
+	struct bt_hfp_ag_call *call;
+	bt_hfp_call_state_t call_state;
+	struct bt_hfp_ag_call *none_active_call;
+
+	none_active_call = get_none_accept_calls(ag);
+
+	if (!none_active_call) {
+		none_active_call = get_none_active_calls(ag);
+	} else {
+		if (!(atomic_test_bit(none_active_call->flags, BT_HFP_AG_CALL_INCOMING_3WAY) ||
+		      atomic_test_bit(none_active_call->flags, BT_HFP_AG_CALL_INCOMING))) {
+			return -ENOTSUP;
+		}
+	}
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			continue;
+		}
+
+		hfp_ag_lock(ag);
+		call_state = call->call_state;
+		hfp_ag_unlock(ag);
+
+		if ((call_state == BT_HFP_CALL_ACTIVE) &&
+		    !atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING_HELD)) {
+			if (release) {
+				ag_terminate_call(call);
+			} else {
+				bt_hfp_ag_set_call_state(call, BT_HFP_CALL_HOLD);
+
+				if (bt_ag && bt_ag->held) {
+					bt_ag->held(call);
+				}
+			}
+		}
+	}
+
+	return hfp_ag_next_step(ag, bt_hfp_ag_deactivate_accept_other_cb, none_active_call);
+}
+
+static int chld_activate_held_call(struct bt_hfp_ag *ag)
+{
+	struct bt_hfp_ag_call *call;
+	bt_hfp_call_state_t call_state;
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			continue;
+		}
+
+		hfp_ag_lock(ag);
+		call_state = call->call_state;
+		hfp_ag_unlock(ag);
+
+		if (call_state == BT_HFP_CALL_HOLD) {
+			bt_hfp_ag_set_call_state(call, BT_HFP_CALL_ACTIVE);
+
+			if (bt_ag && bt_ag->retrieve) {
+				bt_ag->retrieve(call);
+			}
+		}
+	}
+
+	ag_notify_call_held_ind(ag, NULL);
+
+	return 0;
+}
+
+static int chld_drop_conversation(struct bt_hfp_ag *ag)
+{
+	struct bt_hfp_ag_call *call;
+	bt_hfp_call_state_t call_state;
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			continue;
+		}
+
+		hfp_ag_lock(ag);
+		call_state = call->call_state;
+		hfp_ag_unlock(ag);
+
+		if (call_state != BT_HFP_CALL_ACTIVE) {
+			return -ENOTSUP;
+		}
+	}
+
+	if (!bt_ag || !bt_ag->explicit_call_transfer) {
+		return -ENOEXEC;
+	}
+
+	bt_ag->explicit_call_transfer(ag);
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			continue;
+		}
+
+		bt_hfp_ag_set_call_state(call, BT_HFP_CALL_TERMINATE);
+	}
+
+	if (!atomic_test_bit(ag->flags, BT_HFP_AG_AUDIO_CONN)) {
+		LOG_DBG("Close SCO connection");
+		hfp_ag_close_sco(ag);
+	}
+
+	ag_notify_call_held_ind(ag, NULL);
+
+	return 0;
+}
+
+static int chld_release_call(struct bt_hfp_ag *ag, uint8_t call_index)
+{
+	struct bt_hfp_ag_call *call;
+	bt_hfp_call_state_t call_state;
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			continue;
+		}
+
+		if (index != call_index) {
+			continue;
+		}
+
+		hfp_ag_lock(ag);
+		call_state = call->call_state;
+		hfp_ag_unlock(ag);
+
+		if ((call_state == BT_HFP_CALL_HOLD) ||
+		    ((call_state == BT_HFP_CALL_ACTIVE) &&
+		     !atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING_HELD))) {
+			ag_terminate_call(call);
+		} else {
+			ag_reject_call(call);
+		}
+	}
+
+	ag_notify_call_held_ind(ag, NULL);
+
+	return 0;
+}
+
+static int chld_held_other_calls(struct bt_hfp_ag *ag, uint8_t call_index)
+{
+	struct bt_hfp_ag_call *call;
+	bt_hfp_call_state_t call_state;
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			continue;
+		}
+
+		if (index == call_index) {
+			continue;
+		}
+
+		hfp_ag_lock(ag);
+		call_state = call->call_state;
+		hfp_ag_unlock(ag);
+
+		if ((call_state == BT_HFP_CALL_ACTIVE) &&
+		    !atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING_HELD)) {
+			bt_hfp_ag_set_call_state(call, BT_HFP_CALL_HOLD);
+
+			if (bt_ag && bt_ag->held) {
+				bt_ag->held(call);
+			}
+		}
+	}
+
+	call = &ag->calls[call_index];
+	hfp_ag_lock(ag);
+	call_state = call->call_state;
+	hfp_ag_unlock(ag);
+
+	if (call_state == BT_HFP_CALL_HOLD) {
+		bt_hfp_ag_set_call_state(call, BT_HFP_CALL_ACTIVE);
+		if (bt_ag && bt_ag->retrieve) {
+			bt_ag->retrieve(call);
+		}
+	}
+
+	ag_notify_call_held_ind(ag, NULL);
+
+	return 0;
+}
+
+static int chld_other(struct bt_hfp_ag *ag, uint32_t value)
+{
+	uint8_t index;
+	uint8_t command;
+
+	index = value % 10;
+	command = value / 10;
+
+	if (!index) {
+		return -ENOEXEC;
+	}
+
+	index = index - 1;
+
+	if (index >= ARRAY_SIZE(ag->calls)) {
+		return -ENOEXEC;
+	}
+
+	switch (command) {
+	case BT_HFP_CHLD_RELEASE_ACTIVE_ACCEPT_OTHER:
+		return chld_release_call(ag, index);
+	case BT_HFP_CALL_HOLD_ACTIVE_ACCEPT_OTHER:
+		return chld_held_other_calls(ag, index);
+	}
+
+	return -ENOEXEC;
+}
+#endif /* CONFIG_BT_HFP_AG_3WAY_CALL */
+
+static int bt_hfp_ag_chld_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+#if defined(CONFIG_BT_HFP_AG_3WAY_CALL)
+	uint32_t value;
+	int err;
+	char *response;
+
+	if (!BOTH_SUPT_FEAT(ag, BT_HFP_HF_FEATURE_3WAY_CALL, BT_HFP_AG_FEATURE_3WAY_CALL)) {
+		return -ENOEXEC;
+	}
+
+	if (!is_char(buf, '=')) {
+		return -ENOTSUP;
+	}
+
+	if (is_char(buf, '?')) {
+		if (!is_char(buf, '\r')) {
+			return -ENOTSUP;
+		}
+
+#if defined(CONFIG_BT_HFP_AG_ECC)
+		response = "+CHLD:(0,1,1x,2,2x,3,4)";
+#else
+		response = "+CHLD:(0,1,2,3,4)";
+#endif /* CONFIG_BT_HFP_AG_ECC */
+		err = hfp_ag_send_data(ag, bt_hfp_ag_slc_connected, NULL, "\r\n%s\r\n", response);
+		return err;
+	}
+
+	err = get_number(buf, &value);
+	if (err != 0) {
+		return -ENOTSUP;
+	}
+
+	switch (value) {
+	case BT_HFP_CHLD_RELEASE_ALL:
+		return chld_release_all(ag);
+	case BT_HFP_CHLD_RELEASE_ACTIVE_ACCEPT_OTHER:
+		return chld_deactivate_calls_and_accept_other_call(ag, true);
+	case BT_HFP_CALL_HOLD_ACTIVE_ACCEPT_OTHER:
+		return chld_deactivate_calls_and_accept_other_call(ag, false);
+	case BT_HFP_CALL_ACTIVE_HELD:
+		return chld_activate_held_call(ag);
+	case BT_HFP_CALL_QUITE:
+		return chld_drop_conversation(ag);
+	}
+
+	return chld_other(ag, value);
+#else
+	return -ENOEXEC;
+#endif /* CONFIG_BT_HFP_AG_3WAY_CALL */
+}
+
+static int bt_hfp_ag_bind_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	uint32_t indicator;
+	uint32_t hf_indicators = 0U;
+	uint32_t supported_indicators = 0U;
+	int err;
+	char *data;
+	uint32_t len;
+
+	if (!BOTH_SUPT_FEAT(ag, BT_HFP_HF_FEATURE_HF_IND, BT_HFP_AG_FEATURE_HF_IND)) {
+		return -ENOEXEC;
+	}
+
+	if (is_char(buf, '?')) {
+		if (!is_char(buf, '\r')) {
+			return -ENOTSUP;
+		}
+
+		hf_indicators = ag->hf_indicators;
+		supported_indicators = ag->hf_indicators_of_ag & ag->hf_indicators_of_hf;
+		len = MIN(NUM_BITS(sizeof(supported_indicators)), HFP_HF_IND_MAX);
+		for (int i = 1; i < len; i++) {
+			bool enabled;
+
+			if (!(BIT(i) & supported_indicators)) {
+				continue;
+			}
+
+			enabled = BIT(i) & hf_indicators;
+			err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+BIND:%d,%d\r\n", i,
+				enabled ? 1 : 0);
+			if (err) {
+				return err;
+			}
+
+			supported_indicators &= ~BIT(i);
+
+			if (!supported_indicators) {
+				break;
+			}
+		}
+		return 0;
+	}
+
+	if (!is_char(buf, '=')) {
+		return -ENOTSUP;
+	}
+
+	if (is_char(buf, '?')) {
+		if (!is_char(buf, '\r')) {
+			return -ENOTSUP;
+		}
+
+		data = &ag->buffer[0];
+		*data = '(';
+		data++;
+		hf_indicators = ag->hf_indicators_of_ag;
+		len = MIN(NUM_BITS(sizeof(hf_indicators)), HFP_HF_IND_MAX);
+		for (int i = 1; (i < len) && (hf_indicators != 0); i++) {
+			if (BIT(i) & hf_indicators) {
+				int length = snprintk(
+					data, (char *)&ag->buffer[HF_MAX_BUF_LEN - 1] - data - 2,
+					"%d", i);
+				data += length;
+				hf_indicators &= ~BIT(i);
+			}
+			if (hf_indicators != 0) {
+				*data = ',';
+				data++;
+			}
+		}
+		*data = ')';
+		data++;
+		*data = '\0';
+		data++;
+
+		err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+BIND:%s\r\n", &ag->buffer[0]);
+		return err;
+	}
+
+	while (buf->len > 0) {
+		err = get_number(buf, &indicator);
+		if (err != 0) {
+			return -ENOTSUP;
+		}
+
+		if (!is_char(buf, ',')) {
+			if (!is_char(buf, '\r')) {
+				return -ENOTSUP;
+			}
+		}
+
+		if (indicator < NUM_BITS(sizeof(hf_indicators))) {
+			hf_indicators |= BIT(indicator);
+		}
+	}
+
+	ag->hf_indicators_of_hf = hf_indicators;
+
+	return 0;
+}
+
+static int bt_hfp_ag_cmee_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	uint32_t cmee;
+	int err;
+
+	if (!is_char(buf, '=')) {
+		return -ENOTSUP;
+	}
+
+	err = get_number(buf, &cmee);
+	if (err != 0) {
+		return -ENOTSUP;
+	}
+
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	if (cmee > 1) {
+		return -ENOTSUP;
+	}
+
+	if (BT_HFP_AG_FEATURE_EXT_ERR_ENABLE) {
+		atomic_set_bit_to(ag->flags, BT_HFP_AG_CMEE_ENABLE, cmee == 1);
+		return 0;
+	}
+
+	return -ENOTSUP;
+}
+
+static void bt_hfp_ag_reject_cb(struct bt_hfp_ag *ag, void *user_data)
+{
+	struct bt_hfp_ag_call *call = (struct bt_hfp_ag_call *)user_data;
+
+	if (call) {
+		ag_reject_call(call);
+	}
+
+	if (!atomic_test_bit(ag->flags, BT_HFP_AG_AUDIO_CONN)) {
+		LOG_DBG("It is not audio connection");
+		hfp_ag_close_sco(ag);
+	}
+}
+
+static void bt_hfp_ag_call_reject(struct bt_hfp_ag *ag, void *user_data)
+{
+	int err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_NONE,
+					    bt_hfp_ag_reject_cb, user_data);
+	if (err != 0) {
+		LOG_ERR("Fail to send err :(%d)", err);
+	}
+}
+
+static void bt_hfp_ag_terminate_cb(struct bt_hfp_ag *ag, void *user_data)
+{
+	struct bt_hfp_ag_call *call = (struct bt_hfp_ag_call *)user_data;
+
+	if (call) {
+		ag_terminate_call(call);
+	}
+
+	if (!atomic_test_bit(ag->flags, BT_HFP_AG_AUDIO_CONN)) {
+		LOG_DBG("It is not audio connection");
+		hfp_ag_close_sco(ag);
+	}
+}
+
+static void bt_hfp_ag_unit_call_terminate(struct bt_hfp_ag *ag, void *user_data)
+{
+	int err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 0, bt_hfp_ag_terminate_cb,
+					    user_data);
+	if (err != 0) {
+		LOG_ERR("Fail to send err :(%d)", err);
+	}
+}
+
+static void bt_hfp_ag_active_terminate_cb(struct bt_hfp_ag *ag, void *user_data)
+{
+	bt_hfp_ag_unit_call_terminate(ag, user_data);
+}
+
+static void bt_hfp_ag_call_terminate(struct bt_hfp_ag *ag, void *user_data)
+{
+	int err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_NONE,
+					  bt_hfp_ag_active_terminate_cb, user_data);
+	if (err) {
+		LOG_ERR("Fail to send err :(%d)", err);
+	}
+}
+
+struct bt_hfp_ag_call *get_call_with_flag(struct bt_hfp_ag *ag, int bit, bool clear)
+{
+	struct bt_hfp_ag_call *call;
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			continue;
+		}
+
+		if (clear) {
+			if (atomic_test_and_set_bit(call->flags, bit)) {
+				return call;
+			}
+		} else {
+			if (atomic_test_bit(call->flags, bit)) {
+				return call;
+			}
+		}
+	}
+
+	return NULL;
+}
+
+struct bt_hfp_ag_call *get_call_with_flag_and_state(struct bt_hfp_ag *ag, int bit,
+						    bt_hfp_call_state_t state)
+{
+	struct bt_hfp_ag_call *call;
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			continue;
+		}
+
+		if ((call->call_state & state) && atomic_test_bit(call->flags, bit)) {
+			return call;
+		}
+	}
+
+	return NULL;
+}
+
+static int bt_hfp_ag_chup_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	int err;
+	bt_hfp_call_state_t call_state;
+	struct bt_hfp_ag_call *call;
+	int call_count;
+
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	call_count = get_none_released_calls(ag);
+
+	if (call_count == 1) {
+		bt_hfp_ag_tx_cb_t next_step = NULL;
+
+		call = get_call_with_flag(ag, BT_HFP_AG_CALL_IN_USING, false);
+		if (!call) {
+			return 0;
+		}
+
+		hfp_ag_lock(ag);
+		call_state = call->call_state;
+		hfp_ag_unlock(ag);
+
+		if (call_state == BT_HFP_CALL_ALERTING) {
+			if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING)) {
+				next_step = bt_hfp_ag_call_terminate;
+			} else {
+				next_step = bt_hfp_ag_call_reject;
+			}
+		} else if (call_state == BT_HFP_CALL_ACTIVE) {
+			next_step = bt_hfp_ag_unit_call_terminate;
+		}
+		if (next_step) {
+			err = hfp_ag_next_step(ag, next_step, call);
+			return err;
+		}
+
+		return -ENOTSUP;
+	}
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			continue;
+		}
+
+		hfp_ag_lock(ag);
+		call_state = call->call_state;
+		hfp_ag_unlock(ag);
+
+		if (call_state == BT_HFP_CALL_ACTIVE) {
+			err = hfp_ag_next_step(ag, bt_hfp_ag_unit_call_terminate, call);
+		}
+	}
+	return 0;
+}
+
+static uint8_t bt_hfp_get_call_state(struct bt_hfp_ag_call *call)
+{
+	uint8_t status = 0;
+	struct bt_hfp_ag *ag = call->ag;
+
+	hfp_ag_lock(ag);
+	switch (call->call_state) {
+	case BT_HFP_CALL_TERMINATE:
+		if (atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING)) {
+			status = BT_HFP_CLCC_STATUS_INCOMING;
+		} else {
+			status = BT_HFP_CLCC_STATUS_DIALING;
+		}
+		break;
+	case BT_HFP_CALL_OUTGOING:
+		status = BT_HFP_CLCC_STATUS_DIALING;
+		break;
+	case BT_HFP_CALL_INCOMING:
+		status = BT_HFP_CLCC_STATUS_INCOMING;
+		break;
+	case BT_HFP_CALL_ALERTING:
+		if (atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING)) {
+			status = BT_HFP_CLCC_STATUS_WAITING;
+		} else {
+			status = BT_HFP_CLCC_STATUS_ALERTING;
+		}
+		break;
+	case BT_HFP_CALL_ACTIVE:
+		if (atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING_HELD)) {
+			status = BT_HFP_CLCC_STATUS_CALL_HELD_HOLD;
+		} else {
+			status = BT_HFP_CLCC_STATUS_ACTIVE;
+		}
+		break;
+	case BT_HFP_CALL_HOLD:
+		status = BT_HFP_CLCC_STATUS_HELD;
+		break;
+	default:
+		break;
+	}
+	hfp_ag_unlock(ag);
+
+	return status;
+}
+
+static int bt_hfp_ag_clcc_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	int err;
+	struct bt_hfp_ag_call *call;
+	uint8_t dir;
+	uint8_t status;
+	uint8_t mode;
+	uint8_t mpty;
+	int active_calls;
+
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	active_calls = get_active_calls(ag);
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			continue;
+		}
+
+		dir = atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING) ? 1 : 0;
+		status = bt_hfp_get_call_state(call);
+		mode = 0;
+		mpty = (status == BT_HFP_CLCC_STATUS_ACTIVE) && (active_calls > 1) ? 1 : 0;
+		err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+CLCC:%d,%d,%d,%d,%d,\"%s\",%d\r\n",
+				       index + 1, dir, status, mode, mpty, call->number,
+				       call->type);
+		if (err) {
+			LOG_ERR("Fail to send err :(%d)", err);
+		}
+	}
+
+	/* AG shall always send OK response to HF */
+	return 0;
+}
+
+static int bt_hfp_ag_bia_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	uint32_t number;
+	int err;
+	int index = 0;
+	uint32_t indicator;
+
+	if (!is_char(buf, '=')) {
+		return -ENOTSUP;
+	}
+
+	hfp_ag_lock(ag);
+	indicator = ag->indicator;
+	hfp_ag_unlock(ag);
+
+	while (buf->len > 0) {
+		err = get_number(buf, &number);
+		if (err == 0) {
+			/* Valid number */
+			if (number) {
+				indicator |= BIT(index);
+			} else {
+				indicator &= ~BIT(index);
+			}
+		}
+
+		if (is_char(buf, ',')) {
+			index++;
+		} else {
+			if (!is_char(buf, '\r')) {
+				return -ENOTSUP;
+			}
+			if (buf->len != 0) {
+				return -ENOTSUP;
+			}
+		}
+	}
+
+	/* Force call, call setup and held call indicators are enabled. */
+	indicator |= BIT(BT_HFP_AG_CALL_IND) | BIT(BT_HFP_AG_CALL_SETUP_IND) |
+		    BIT(BT_HFP_AG_CALL_HELD_IND);
+
+	hfp_ag_lock(ag);
+	ag->indicator = indicator;
+	hfp_ag_unlock(ag);
+
+	return 0;
+}
+
+static void bt_hfp_ag_call_ringing_cb(struct bt_hfp_ag_call *call, bool in_bond)
+{
+	if (bt_ag && bt_ag->ringing) {
+		bt_ag->ringing(call, in_bond);
+	}
+}
+
+static void hfp_ag_sco_connected(struct bt_sco_chan *chan)
+{
+	struct bt_hfp_ag *ag = CONTAINER_OF(chan, struct bt_hfp_ag, sco_chan);
+	bt_hfp_call_state_t call_state;
+	struct bt_hfp_ag_call *call;
+
+	call = get_call_with_flag(ag, BT_HFP_AG_CALL_OPEN_SCO, true);
+
+	if (call) {
+		hfp_ag_lock(ag);
+		call_state = call->call_state;
+		hfp_ag_unlock(ag);
+		if (call_state == BT_HFP_CALL_INCOMING) {
+			bt_hfp_ag_set_call_state(call, BT_HFP_CALL_ALERTING);
+			bt_hfp_ag_call_ringing_cb(call, true);
+		}
+	}
+
+	if ((bt_ag) && bt_ag->sco_connected) {
+		bt_ag->sco_connected(ag, chan->sco);
+	}
+}
+
+static void hfp_ag_sco_disconnected(struct bt_sco_chan *chan, uint8_t reason)
+{
+	struct bt_hfp_ag *ag = CONTAINER_OF(chan, struct bt_hfp_ag, sco_chan);
+	bt_hfp_call_state_t call_state;
+	struct bt_hfp_ag_call *call;
+
+	call = get_call_with_flag(ag, BT_HFP_AG_CALL_OPEN_SCO, true);
+
+	if ((bt_ag != NULL) && bt_ag->sco_disconnected) {
+		bt_ag->sco_disconnected(chan->sco, reason);
+	}
+
+	if (!call) {
+		return;
+	}
+
+	hfp_ag_lock(ag);
+	call_state = call->call_state;
+	hfp_ag_unlock(ag);
+	if ((call_state == BT_HFP_CALL_INCOMING) || (call_state == BT_HFP_CALL_OUTGOING)) {
+		bt_hfp_ag_call_reject(ag, call);
+	}
+}
+
+static struct bt_conn *bt_hfp_ag_create_sco(struct bt_hfp_ag *ag)
+{
+	struct bt_conn *sco_conn;
+
+	static struct bt_sco_chan_ops ops = {
+		.connected = hfp_ag_sco_connected,
+		.disconnected = hfp_ag_sco_disconnected,
+	};
+
+	LOG_DBG("");
+
+	if (ag->sco_chan.sco == NULL) {
+		ag->sco_chan.ops = &ops;
+
+		/* create SCO connection*/
+		sco_conn = bt_conn_create_sco(&ag->acl_conn->br.dst, &ag->sco_chan);
+		if (sco_conn != NULL) {
+			LOG_DBG("Created sco %p", sco_conn);
+			bt_conn_unref(sco_conn);
+		}
+	} else {
+		sco_conn = ag->sco_chan.sco;
+	}
+
+	return sco_conn;
+}
+
+static int hfp_ag_open_sco(struct bt_hfp_ag *ag, struct bt_hfp_ag_call *call)
+{
+	bool create_sco;
+	bt_hfp_call_state_t call_state;
+
+	if (atomic_test_bit(ag->flags, BT_HFP_AG_CREATING_SCO)) {
+		LOG_WRN("SCO connection is creating!");
+		return 0;
+	}
+
+	hfp_ag_lock(ag);
+	create_sco = (ag->sco_chan.sco == NULL) ? true : false;
+	if (create_sco) {
+		atomic_set_bit(ag->flags, BT_HFP_AG_CREATING_SCO);
+	}
+	hfp_ag_unlock(ag);
+
+	if (create_sco) {
+		struct bt_conn *sco_conn = bt_hfp_ag_create_sco(ag);
+
+		atomic_clear_bit(ag->flags, BT_HFP_AG_CREATING_SCO);
+		atomic_clear_bit(ag->flags, BT_HFP_AG_AUDIO_CONN);
+
+		if (sco_conn == NULL) {
+			LOG_ERR("Fail to create sco connection!");
+			return -ENOTCONN;
+		}
+
+		atomic_set_bit_to(ag->flags, BT_HFP_AG_AUDIO_CONN, call == NULL);
+		if (call) {
+			atomic_set_bit(call->flags, BT_HFP_AG_CALL_OPEN_SCO);
+		}
+
+		LOG_DBG("SCO connection created (%p)", sco_conn);
+	} else {
+		if (call) {
+			hfp_ag_lock(ag);
+			call_state = call->call_state;
+			hfp_ag_unlock(ag);
+
+			if (call_state == BT_HFP_CALL_INCOMING) {
+				bt_hfp_ag_set_call_state(call, BT_HFP_CALL_ALERTING);
+				bt_hfp_ag_call_ringing_cb(call, true);
+			}
+		}
+	}
+
+	return 0;
+}
+
+static int bt_hfp_ag_codec_select(struct bt_hfp_ag *ag)
+{
+	int err;
+
+	LOG_DBG("");
+
+	hfp_ag_lock(ag);
+	if (ag->selected_codec_id == 0) {
+		LOG_WRN("Codec is invalid, set default value");
+		ag->selected_codec_id = BT_HFP_AG_CODEC_CVSD;
+	}
+
+	if (!(ag->hf_codec_ids & BIT(ag->selected_codec_id))) {
+		LOG_ERR("Codec is unsupported (codec id %d)", ag->selected_codec_id);
+		hfp_ag_unlock(ag);
+		return -EINVAL;
+	}
+	hfp_ag_unlock(ag);
+
+	err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+BCS:%d\r\n", ag->selected_codec_id);
+	if (err != 0) {
+		LOG_ERR("Fail to send err :(%d)", err);
+	}
+	return err;
+}
+
+static int bt_hfp_ag_create_audio_connection(struct bt_hfp_ag *ag, struct bt_hfp_ag_call *call)
+{
+	int err;
+	uint32_t hf_codec_ids;
+
+	hfp_ag_lock(ag);
+	hf_codec_ids = ag->hf_codec_ids;
+	hfp_ag_unlock(ag);
+
+	if ((hf_codec_ids != 0) && atomic_test_bit(ag->flags, BT_HFP_AG_CODEC_CHANGED)) {
+		err = bt_hfp_ag_codec_select(ag);
+		atomic_set_bit_to(ag->flags, BT_HFP_AG_CODEC_CONN, err == 0);
+		if (call) {
+			atomic_set_bit_to(call->flags, BT_HFP_AG_CALL_OPEN_SCO, err == 0);
+		}
+	} else {
+		err = hfp_ag_open_sco(ag, call);
+	}
+
+	return err;
+}
+
+static void bt_hfp_ag_audio_connection(struct bt_hfp_ag *ag, void *user_data)
+{
+	int err;
+	struct bt_hfp_ag_call *call = (struct bt_hfp_ag_call *)user_data;
+
+	err = bt_hfp_ag_create_audio_connection(ag, call);
+	if (err) {
+		bt_hfp_ag_unit_call_terminate(ag, user_data);
+	}
+}
+
+static void bt_hfp_ag_call_setup_none_cb(struct bt_hfp_ag *ag, void *user_data)
+{
+	int err;
+	struct bt_hfp_ag_call *call = (struct bt_hfp_ag_call *)user_data;
+
+	if (atomic_test_bit(call->flags, BT_HFP_AG_CALL_OUTGOING_3WAY)) {
+		err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_HELD_IND,
+					      BT_HFP_CALL_HELD_ACTIVE_HELD, bt_hfp_ag_accept_cb,
+					      call);
+		if (err) {
+			bt_hfp_ag_unit_call_terminate(ag, user_data);
+		}
+		return;
+	}
+
+	bt_hfp_ag_audio_connection(ag, user_data);
+}
+
+static void bt_hfp_ag_unit_call_accept(struct bt_hfp_ag *ag, void *user_data)
+{
+	int err;
+
+	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 1, bt_hfp_ag_accept_cb, user_data);
+	if (err) {
+		LOG_ERR("Fail to send err :(%d)", err);
+	}
+
+	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_NONE,
+				      bt_hfp_ag_call_setup_none_cb, user_data);
+	if (err) {
+		LOG_ERR("Fail to send err :(%d)", err);
+	}
+}
+
+static int bt_hfp_ag_ata_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	int err;
+	int call_count;
+	struct bt_hfp_ag_call *call;
+
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	hfp_ag_lock(ag);
+	call_count = get_none_released_calls(ag);
+	if (call_count != 1) {
+		hfp_ag_unlock(ag);
+		return -ENOTSUP;
+	}
+
+	call = get_call_with_flag(ag, BT_HFP_AG_CALL_IN_USING, false);
+	__ASSERT(call, "Invalid call object");
+
+	if (call->call_state != BT_HFP_CALL_ALERTING) {
+		hfp_ag_unlock(ag);
+		return -ENOTSUP;
+	}
+	hfp_ag_unlock(ag);
+
+	if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING)) {
+		return -ENOTSUP;
+	}
+
+	err = hfp_ag_next_step(ag, bt_hfp_ag_unit_call_accept, call);
+
+	return err;
+}
+
+static int bt_hfp_ag_cops_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	int err;
+	uint32_t number;
+
+	if (is_char(buf, '=')) {
+		static const uint32_t command_line_prefix[] = {3, 0};
+
+		for (int i = 0; i < ARRAY_SIZE(command_line_prefix); i++) {
+			err = get_number(buf, &number);
+			if (err != 0) {
+				return -ENOTSUP;
+			}
+
+			if (command_line_prefix[i] != number) {
+				return -ENOTSUP;
+			}
+
+			if (!is_char(buf, ',')) {
+				if (!is_char(buf, '\r')) {
+					return -ENOTSUP;
+				}
+			}
+		}
+
+		atomic_set_bit(ag->flags, BT_HFP_AG_COPS_SET);
+		return 0;
+	}
+
+	if (!atomic_test_bit(ag->flags, BT_HFP_AG_COPS_SET)) {
+		return -ENOTSUP;
+	}
+
+	if (!is_char(buf, '?')) {
+		return -ENOTSUP;
+	}
+
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+COPS:%d,%d,\"%s\"\r\n", ag->mode, 0,
+			       ag->operator);
+	if (err) {
+		LOG_ERR("Fail to send err :(%d)", err);
+	}
+
+	return err;
+}
+
+static int bt_hfp_ag_bcc_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+#if BT_HFP_AG_FEATURE_CODEC_NEG_ENABLE
+	int err;
+
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	hfp_ag_lock(ag);
+	if (ag->selected_codec_id && (!(ag->hf_codec_ids & BIT(ag->selected_codec_id)))) {
+		hfp_ag_unlock(ag);
+		return -ENOTSUP;
+	}
+
+	if (ag->sco_chan.sco) {
+		hfp_ag_unlock(ag);
+		return -ECONNREFUSED;
+	}
+	hfp_ag_unlock(ag);
+
+	if (bt_ag && bt_ag->audio_connect_req) {
+		bt_ag->audio_connect_req(ag);
+		return 0;
+	}
+
+	err = hfp_ag_next_step(ag, bt_hfp_ag_audio_connection, NULL);
+
+	return err;
+#else
+	return -ENOTSUP;
+#endif /* BT_HFP_AG_FEATURE_CODEC_NEG_ENABLE */
+}
+
+static void bt_hfp_ag_unit_codec_conn_setup(struct bt_hfp_ag *ag, void *user_data)
+{
+	int err = hfp_ag_open_sco(ag, user_data);
+
+	if (err) {
+		bt_hfp_ag_call_reject(ag, user_data);
+	}
+}
+
+static int bt_hfp_ag_bcs_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	int err;
+	uint32_t number;
+	bool codec_conn;
+	struct bt_hfp_ag_call *call;
+
+	if (!is_char(buf, '=')) {
+		return -ENOTSUP;
+	}
+
+	err = get_number(buf, &number);
+	if (err != 0) {
+		return -ENOTSUP;
+	}
+
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	if (!atomic_test_bit(ag->flags, BT_HFP_AG_CODEC_CONN)) {
+		return -ESRCH;
+	}
+
+	hfp_ag_lock(ag);
+	if (ag->selected_codec_id != number) {
+		LOG_ERR("Received codec id %d is not aligned with selected %d", number,
+			ag->selected_codec_id);
+		err = -ENOTSUP;
+	} else if (!(ag->hf_codec_ids & BIT(ag->selected_codec_id))) {
+		LOG_ERR("Selected codec id %d is unsupported %d", ag->selected_codec_id,
+			ag->hf_codec_ids);
+		err = -ENOTSUP;
+	}
+	hfp_ag_unlock(ag);
+
+	codec_conn = atomic_test_and_clear_bit(ag->flags, BT_HFP_AG_CODEC_CONN);
+	atomic_clear_bit(ag->flags, BT_HFP_AG_CODEC_CHANGED);
+
+	call = get_call_with_flag(ag, BT_HFP_AG_CALL_OPEN_SCO, false);
+
+	if (err == 0) {
+		if (codec_conn && bt_ag && bt_ag->codec_negotiate) {
+			bt_ag->codec_negotiate(ag, err);
+		}
+		err = hfp_ag_next_step(ag, bt_hfp_ag_unit_codec_conn_setup, call);
+	} else {
+		bt_hfp_call_state_t call_state;
+
+		if (codec_conn && bt_ag && bt_ag->codec_negotiate) {
+			bt_ag->codec_negotiate(ag, err);
+		}
+
+		if (call) {
+			hfp_ag_lock(ag);
+			call_state = call->call_state;
+			hfp_ag_unlock(ag);
+			if (call_state != BT_HFP_CALL_TERMINATE) {
+				(void)hfp_ag_next_step(ag, bt_hfp_ag_unit_call_terminate, call);
+			}
+		}
+	}
+
+	return err;
+}
+
+static void bt_hfp_ag_outgoing_cb(struct bt_hfp_ag *ag, void *user_data)
+{
+	struct bt_hfp_ag_call *call = (struct bt_hfp_ag_call *)user_data;
+
+	bt_hfp_ag_set_call_state(call, BT_HFP_CALL_OUTGOING);
+
+	if (bt_ag && bt_ag->outgoing) {
+		bt_ag->outgoing(ag, call, call->number);
+	}
+
+	if (atomic_test_bit(ag->flags, BT_HFP_AG_INBAND_RING) ||
+	    atomic_test_bit(call->flags, BT_HFP_AG_CALL_OUTGOING_3WAY)) {
+		int err;
+
+		err = bt_hfp_ag_create_audio_connection(ag, call);
+		if (err) {
+			bt_hfp_ag_call_reject(ag, user_data);
+		}
+	}
+}
+
+static void bt_hfp_ag_unit_call_outgoing(struct bt_hfp_ag *ag, void *user_data)
+{
+	struct bt_hfp_ag_call *call = (struct bt_hfp_ag_call *)user_data;
+	int err;
+
+	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_OUTGOING,
+				      bt_hfp_ag_outgoing_cb, call);
+
+	if (err) {
+		LOG_ERR("Fail to send err :(%d)", err);
+	}
+}
+
+#if defined(CONFIG_BT_HFP_AG_3WAY_CALL)
+static void bt_hfp_ag_call_held_cb(struct bt_hfp_ag *ag, void *user_data)
+{
+	struct bt_hfp_ag_call *call = (struct bt_hfp_ag_call *)user_data;
+	bt_hfp_call_state_t call_state;
+
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			continue;
+		}
+
+		hfp_ag_lock(ag);
+		call_state = call->call_state;
+		hfp_ag_unlock(ag);
+
+		if ((call_state == BT_HFP_CALL_ACTIVE) &&
+		    !atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING_HELD)) {
+			bt_hfp_ag_set_call_state(call, BT_HFP_CALL_HOLD);
+			if (bt_ag && bt_ag->held) {
+				bt_ag->held(call);
+			}
+		}
+	}
+
+	bt_hfp_ag_unit_call_outgoing(ag, user_data);
+}
+
+static void bt_hfp_ag_unit_call_outgoing_3way(struct bt_hfp_ag *ag, void *user_data)
+{
+	struct bt_hfp_ag_call *call = (struct bt_hfp_ag_call *)user_data;
+	int err;
+	uint8_t old_value;
+
+	atomic_set_bit(call->flags, BT_HFP_AG_CALL_OUTGOING_3WAY);
+
+	hfp_ag_lock(ag);
+	old_value = ag->indicator_value[BT_HFP_AG_CALL_HELD_IND];
+	hfp_ag_unlock(ag);
+	if (old_value == BT_HFP_CALL_HELD_HELD) {
+		LOG_WRN("No active call");
+		bt_hfp_ag_call_held_cb(ag, user_data);
+		return;
+	}
+
+	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_HELD_IND, BT_HFP_CALL_HELD_HELD,
+				      bt_hfp_ag_call_held_cb, call);
+	if (err) {
+		LOG_ERR("Fail to send err :(%d)", err);
+	}
+}
+#endif /* CONFIG_BT_HFP_AG_3WAY_CALL */
+
+static int bt_hfp_ag_outgoing_call(struct bt_hfp_ag *ag, const char *number, uint8_t type)
+{
+	int err;
+	size_t len;
+	struct bt_hfp_ag_call *call;
+	int call_count;
+
+	len = strlen(number);
+	if (len == 0) {
+		return -ENOTSUP;
+	}
+
+	if (len > CONFIG_BT_HFP_AG_PHONE_NUMBER_MAX_LEN) {
+		return -ENAMETOOLONG;
+	}
+
+	hfp_ag_lock(ag);
+	(void)strcpy(ag->last_number, number);
+	ag->type = type;
+	hfp_ag_unlock(ag);
+
+	call = get_call_from_number(ag, number, type);
+	if (call) {
+		return -EBUSY;
+	}
+
+	call_count = get_none_released_calls(ag);
+
+	if (call_count) {
+#if defined(CONFIG_BT_HFP_AG_3WAY_CALL)
+		if (!BOTH_SUPT_FEAT(ag, BT_HFP_HF_FEATURE_3WAY_CALL,
+				    BT_HFP_AG_FEATURE_3WAY_CALL)) {
+			return -ENOEXEC;
+		}
+
+		if (!get_active_held_calls(ag)) {
+			LOG_WRN("The first call is not accepted");
+			return -EBUSY;
+		}
+#else
+		return -EBUSY;
+#endif /* CONFIG_BT_HFP_AG_3WAY_CALL */
+	}
+
+	call = get_new_call(ag, number, type);
+	if (!call) {
+		LOG_WRN("Cannot allocate a new call object");
+		return -ENOMEM;
+	}
+
+	atomic_clear_bit(call->flags, BT_HFP_AG_CALL_INCOMING);
+	bt_hfp_ag_set_call_state(call, BT_HFP_CALL_OUTGOING);
+
+#if defined(CONFIG_BT_HFP_AG_3WAY_CALL)
+	if (call_count) {
+		err = hfp_ag_next_step(ag, bt_hfp_ag_unit_call_outgoing_3way, call);
+		if (err) {
+			free_call(call);
+		}
+		return err;
+	}
+#endif /* CONFIG_BT_HFP_AG_3WAY_CALL */
+
+	err = hfp_ag_next_step(ag, bt_hfp_ag_unit_call_outgoing, call);
+	if (err) {
+		free_call(call);
+	}
+	return err;
+}
+
+static int bt_hfp_ag_atd_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	int err;
+	char *number = NULL;
+	bool is_memory_dial = false;
+
+	if (buf->data[buf->len - 1] != '\r') {
+		return -ENOTSUP;
+	}
+
+	if (is_char(buf, '>')) {
+		is_memory_dial = true;
+	}
+
+	if ((buf->len - 1) > CONFIG_BT_HFP_AG_PHONE_NUMBER_MAX_LEN) {
+		return -ENAMETOOLONG;
+	}
+
+	buf->data[buf->len - 1] = '\0';
+
+	if (is_memory_dial) {
+		if (bt_ag && bt_ag->memory_dial) {
+			err = bt_ag->memory_dial(ag, &buf->data[0], &number);
+			if ((err != 0) || (number == NULL)) {
+				return -ENOTSUP;
+			}
+		} else {
+			return -ENOTSUP;
+		}
+	} else {
+		number = &buf->data[0];
+		if (bt_ag && bt_ag->number_call) {
+			err = bt_ag->number_call(ag, &buf->data[0]);
+			if (err) {
+				return err;
+			}
+		} else {
+			return -ENOTSUP;
+		}
+	}
+
+	return bt_hfp_ag_outgoing_call(ag, number, 0);
+}
+
+static int bt_hfp_ag_bldn_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	return bt_hfp_ag_outgoing_call(ag, ag->last_number, ag->type);
+}
+
+static int bt_hfp_ag_clip_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	int err;
+	uint32_t clip;
+
+	if (!is_char(buf, '=')) {
+		return -ENOTSUP;
+	}
+
+	err = get_number(buf, &clip);
+	if (err != 0) {
+		return -ENOTSUP;
+	}
+
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	if (clip > 1) {
+		return -ENOTSUP;
+	}
+
+	atomic_set_bit_to(ag->flags, BT_HFP_AG_CLIP_ENABLE, clip == 1);
+
+	return err;
+}
+
+static int bt_hfp_ag_vgm_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	int err;
+	uint32_t vgm;
+
+	if (!is_char(buf, '=')) {
+		return -ENOTSUP;
+	}
+
+	err = get_number(buf, &vgm);
+	if (err != 0) {
+		return -ENOTSUP;
+	}
+
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	if (vgm > BT_HFP_HF_VGM_GAIN_MAX) {
+		LOG_ERR("Invalid vgm (%d>%d)", vgm, BT_HFP_HF_VGM_GAIN_MAX);
+		return -ENOTSUP;
+	}
+
+	if (bt_ag && bt_ag->vgm) {
+		bt_ag->vgm(ag, (uint8_t)vgm);
+	}
+	return err;
+}
+
+static int bt_hfp_ag_vgs_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	int err;
+	uint32_t vgs;
+
+	if (!is_char(buf, '=')) {
+		return -ENOTSUP;
+	}
 
-	if (!is_char(buf, '?')) {
+	err = get_number(buf, &vgs);
+	if (err != 0) {
 		return -ENOTSUP;
 	}
 
@@ -518,97 +2706,401 @@ static int bt_hfp_ag_cind_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
 		return -ENOTSUP;
 	}
 
-	if (!inquiry_status) {
-		err = hfp_ag_send_data(
-			ag, NULL, NULL,
-			"\r\n+CIND:(\"%s\",(%d%s%d)),(\"%s\",(%d%s%d)),(\"%s\",(%d%s%d)),(\"%s\",(%"
-			"d%s%d)),(\"%s\",(%d%s%d)),(\"%s\",(%d%s%d)),(\"%s\",(%d%s%d))\r\n",
-			ag_ind[BT_HFP_AG_SERVICE_IND].name, ag_ind[BT_HFP_AG_SERVICE_IND].min,
-			ag_ind[BT_HFP_AG_SERVICE_IND].connector, ag_ind[BT_HFP_AG_SERVICE_IND].max,
-			ag_ind[BT_HFP_AG_CALL_IND].name, ag_ind[BT_HFP_AG_CALL_IND].min,
-			ag_ind[BT_HFP_AG_CALL_IND].connector, ag_ind[BT_HFP_AG_CALL_IND].max,
-			ag_ind[BT_HFP_AG_CALL_SETUP_IND].name, ag_ind[BT_HFP_AG_CALL_SETUP_IND].min,
-			ag_ind[BT_HFP_AG_CALL_SETUP_IND].connector,
-			ag_ind[BT_HFP_AG_CALL_SETUP_IND].max, ag_ind[BT_HFP_AG_CALL_HELD_IND].name,
-			ag_ind[BT_HFP_AG_CALL_HELD_IND].min,
-			ag_ind[BT_HFP_AG_CALL_HELD_IND].connector,
-			ag_ind[BT_HFP_AG_CALL_HELD_IND].max, ag_ind[BT_HFP_AG_SIGNAL_IND].name,
-			ag_ind[BT_HFP_AG_SIGNAL_IND].min, ag_ind[BT_HFP_AG_SIGNAL_IND].connector,
-			ag_ind[BT_HFP_AG_SIGNAL_IND].max, ag_ind[BT_HFP_AG_ROAM_IND].name,
-			ag_ind[BT_HFP_AG_ROAM_IND].min, ag_ind[BT_HFP_AG_ROAM_IND].connector,
-			ag_ind[BT_HFP_AG_ROAM_IND].max, ag_ind[BT_HFP_AG_BATTERY_IND].name,
-			ag_ind[BT_HFP_AG_BATTERY_IND].min, ag_ind[BT_HFP_AG_BATTERY_IND].connector,
-			ag_ind[BT_HFP_AG_BATTERY_IND].max);
-	} else {
-		err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+CIND:%d,%d,%d,%d,%d,%d,%d\r\n",
-					 ag->indicator_value[BT_HFP_AG_SERVICE_IND],
-					 ag->indicator_value[BT_HFP_AG_CALL_IND],
-					 ag->indicator_value[BT_HFP_AG_CALL_SETUP_IND],
-					 ag->indicator_value[BT_HFP_AG_CALL_HELD_IND],
-					 ag->indicator_value[BT_HFP_AG_SIGNAL_IND],
-					 ag->indicator_value[BT_HFP_AG_ROAM_IND],
-					 ag->indicator_value[BT_HFP_AG_BATTERY_IND]);
+	if (vgs > BT_HFP_HF_VGS_GAIN_MAX) {
+		LOG_ERR("Invalid vgs (%d>%d)", vgs, BT_HFP_HF_VGS_GAIN_MAX);
+		return -ENOTSUP;
 	}
 
+	if (bt_ag && bt_ag->vgs) {
+		bt_ag->vgs(ag, (uint8_t)vgs);
+	}
 	return err;
 }
 
-static void bt_hfp_ag_set_in_band_ring(struct bt_hfp_ag *ag, void *user_data)
+static int bt_hfp_ag_nrec_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
 {
-	bool is_inband_ringtone;
+	int err;
+	uint32_t disable;
 
-	hfp_ag_lock(ag);
-	is_inband_ringtone = (ag->ag_features & BT_HFP_AG_FEATURE_INBAND_RINGTONE) ? true : false;
-	hfp_ag_unlock(ag);
+	if (!is_char(buf, '=')) {
+		return -ENOTSUP;
+	}
 
-	if (is_inband_ringtone) {
-		int err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+BSIR:1\r\n");
+	err = get_number(buf, &disable);
+	if (err != 0) {
+		return -ENOTSUP;
+	}
 
-		atomic_set_bit_to(ag->flags, BT_HFP_AG_INBAND_RING, err == 0);
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	if (!AG_SUPT_FEAT(ag, BT_HFP_AG_FEATURE_ECNR)) {
+		return -ENOTSUP;
+	}
+
+	if (disable) {
+		LOG_ERR("Only support EC NR disable");
+		return -ENOTSUP;
+	}
+
+#if defined(CONFIG_BT_HFP_AG_ECNR)
+	if (bt_ag && bt_ag->ecnr_turn_off) {
+		bt_ag->ecnr_turn_off(ag);
+		return 0;
 	}
+#endif /* CONFIG_BT_HFP_AG_ECNR */
+	return -ENOTSUP;
 }
 
-static int bt_hfp_ag_cmer_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+static void btrh_held_call_updated_cb(struct bt_hfp_ag *ag, void *user_data)
+{
+	struct bt_hfp_ag_call *call = (struct bt_hfp_ag_call *)user_data;
+
+	bt_hfp_ag_set_call_state(call, BT_HFP_CALL_ACTIVE);
+}
+
+static void btrh_held_call_setup_updated_cb(struct bt_hfp_ag *ag, void *user_data)
+{
+	struct bt_hfp_ag_call *call = (struct bt_hfp_ag_call *)user_data;
+
+	if (bt_ag && bt_ag->incoming_held) {
+		bt_ag->incoming_held(call);
+	}
+}
+
+static void btrh_held_cb(struct bt_hfp_ag *ag, void *user_data)
+{
+	int err;
+
+	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 1, btrh_held_call_updated_cb,
+				      user_data);
+	if (err) {
+		LOG_ERR("Fail to send err :(%d)", err);
+		bt_hfp_ag_unit_call_terminate(ag, user_data);
+	}
+
+	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_NONE,
+				      btrh_held_call_setup_updated_cb, user_data);
+	if (err) {
+		LOG_ERR("Fail to send err :(%d)", err);
+		bt_hfp_ag_unit_call_terminate(ag, user_data);
+	}
+}
+
+static void btrh_accept_cb(struct bt_hfp_ag *ag, void *user_data)
+{
+	int err;
+	struct bt_hfp_ag_call *call = (struct bt_hfp_ag_call *)user_data;
+
+	if (bt_ag && bt_ag->accept) {
+		bt_ag->accept(call);
+	}
+
+	err = bt_hfp_ag_create_audio_connection(ag, call);
+	if (err) {
+		bt_hfp_ag_unit_call_terminate(ag, user_data);
+	}
+}
+
+static void btrh_reject_cb(struct bt_hfp_ag *ag, void *user_data)
 {
-	uint32_t number;
 	int err;
-	static const uint32_t command_line_prefix[] = {3, 0, 0};
+
+	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 0, bt_hfp_ag_reject_cb, user_data);
+	if (err) {
+		bt_hfp_ag_unit_call_terminate(ag, user_data);
+	}
+}
+
+static int bt_hfp_ag_btrh_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	int err;
+	uint32_t action;
+	bt_hfp_call_state_t call_state;
+	struct bt_hfp_ag_call *call;
+
+	if (is_char(buf, '?')) {
+		call = get_call_with_flag(ag, BT_HFP_AG_CALL_INCOMING_HELD, false);
+		hfp_ag_lock(ag);
+		call_state = call->call_state;
+		hfp_ag_unlock(ag);
+		if (call && (call_state == BT_HFP_CALL_ACTIVE)) {
+			err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+BTRH:%d\r\n",
+					       BT_HFP_BTRH_ON_HOLD);
+			if (err) {
+				LOG_ERR("Fail to send err :(%d)", err);
+			}
+			return err;
+		}
+		return 0;
+	}
 
 	if (!is_char(buf, '=')) {
 		return -ENOTSUP;
 	}
 
-	for (int i = 0; i < ARRAY_SIZE(command_line_prefix); i++) {
-		err = get_number(buf, &number);
-		if (err != 0) {
-			return -ENOTSUP;
+	err = get_number(buf, &action);
+	if (err != 0) {
+		return -ENOTSUP;
+	}
+
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	if (action == BT_HFP_BTRH_ON_HOLD) {
+		call = get_call_with_flag_and_state(ag, BT_HFP_AG_CALL_INCOMING,
+						    BT_HFP_CALL_ALERTING | BT_HFP_CALL_INCOMING);
+		if (call) {
+			atomic_set_bit(call->flags, BT_HFP_AG_CALL_INCOMING_HELD);
+			err = hfp_ag_send_data(ag, btrh_held_cb, call, "\r\n+BTRH:%d\r\n",
+					       BT_HFP_BTRH_ON_HOLD);
+			if (err) {
+				LOG_ERR("Fail to send err :(%d)", err);
+			}
+			return err;
 		}
+	} else if (action == BT_HFP_BTRH_ACCEPTED) {
+		call = get_call_with_flag_and_state(ag, BT_HFP_AG_CALL_INCOMING_HELD,
+						    BT_HFP_CALL_ACTIVE);
+		if (call) {
+			atomic_clear_bit(call->flags, BT_HFP_AG_CALL_INCOMING_HELD);
+			err = hfp_ag_send_data(ag, btrh_accept_cb, call, "\r\n+BTRH:%d\r\n",
+					       BT_HFP_BTRH_ACCEPTED);
+			if (err) {
+				LOG_ERR("Fail to send err :(%d)", err);
+			}
+			return err;
+		}
+	} else if (action == BT_HFP_BTRH_REJECTED) {
+		call = get_call_with_flag_and_state(ag, BT_HFP_AG_CALL_INCOMING_HELD,
+						    BT_HFP_CALL_ACTIVE);
+		if (call) {
+			atomic_clear_bit(call->flags, BT_HFP_AG_CALL_INCOMING_HELD);
+			err = hfp_ag_send_data(ag, btrh_reject_cb, call, "\r\n+BTRH:%d\r\n",
+					       BT_HFP_BTRH_REJECTED);
+			if (err) {
+				LOG_ERR("Fail to send err :(%d)", err);
+			}
+			return err;
+		}
+	}
 
-		if (!is_char(buf, ',')) {
-			return -ENOTSUP;
+	return -ENOTSUP;
+}
+
+static int bt_hfp_ag_ccwa_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	int err;
+	uint32_t value;
+
+	if (!BOTH_SUPT_FEAT(ag, BT_HFP_HF_FEATURE_3WAY_CALL, BT_HFP_AG_FEATURE_3WAY_CALL)) {
+		return -ENOEXEC;
+	}
+
+	if (!is_char(buf, '=')) {
+		return -ENOTSUP;
+	}
+
+	err = get_number(buf, &value);
+	if (err != 0) {
+		return -ENOTSUP;
+	}
+
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	if (value > 1) {
+		return -ENOTSUP;
+	}
+
+	atomic_set_bit_to(ag->flags, BT_HFP_AG_CCWA_ENABLE, value);
+	return 0;
+}
+
+static void bt_hfp_ag_vr_activate(struct bt_hfp_ag *ag, void *user_data)
+{
+	bool feature;
+
+	feature = BOTH_SUPT_FEAT(ag, BT_HFP_HF_FEATURE_ENH_VOICE_RECG,
+				 BT_HFP_AG_FEATURE_ENH_VOICE_RECG);
+
+#if defined(CONFIG_BT_HFP_AG_VOICE_RECG)
+	if (bt_ag && bt_ag->voice_recognition) {
+		bt_ag->voice_recognition(ag, true);
+	} else {
+		(void)bt_hfp_ag_audio_connect(ag, BT_HFP_AG_CODEC_CVSD);
+	}
+#endif /* CONFIG_BT_HFP_AG_VOICE_RECG */
+
+	atomic_set_bit_to(ag->flags, BT_HFP_AG_VRE_R2A, !feature);
+
+#if defined(CONFIG_BT_HFP_AG_ENH_VOICE_RECG)
+	if (atomic_test_bit(ag->flags, BT_HFP_AG_VRE_R2A)) {
+		if (bt_ag && bt_ag->ready_to_accept_audio) {
+			bt_ag->ready_to_accept_audio(ag);
 		}
+	}
+#endif /* CONFIG_BT_HFP_AG_ENH_VOICE_RECG */
+}
 
-		if (command_line_prefix[i] != number) {
+static void bt_hfp_ag_vr_deactivate(struct bt_hfp_ag *ag, void *user_data)
+{
+#if defined(CONFIG_BT_HFP_AG_ENH_VOICE_RECG)
+	if (bt_ag && bt_ag->voice_recognition) {
+		bt_ag->voice_recognition(ag, false);
+	}
+#endif /* CONFIG_BT_HFP_AG_ENH_VOICE_RECG */
+}
+
+static void bt_hfp_ag_vr_ready2accept(struct bt_hfp_ag *ag, void *user_data)
+{
+	atomic_set_bit(ag->flags, BT_HFP_AG_VRE_R2A);
+
+#if defined(CONFIG_BT_HFP_AG_ENH_VOICE_RECG)
+	if (bt_ag && bt_ag->ready_to_accept_audio) {
+		bt_ag->ready_to_accept_audio(ag);
+	}
+#endif /* CONFIG_BT_HFP_AG_ENH_VOICE_RECG */
+}
+
+static int bt_hfp_ag_bvra_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	int err;
+	uint32_t value;
+
+	if (!BOTH_SUPT_FEAT(ag, BT_HFP_HF_FEATURE_VOICE_RECG, BT_HFP_AG_FEATURE_VOICE_RECG)) {
+		return -ENOEXEC;
+	}
+
+	if (!is_char(buf, '=')) {
+		return -ENOTSUP;
+	}
+
+	err = get_number(buf, &value);
+	if (err != 0) {
+		return -ENOTSUP;
+	}
+
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	switch (value) {
+	case BT_HFP_BVRA_DEACTIVATION:
+		if (!atomic_test_and_clear_bit(ag->flags, BT_HFP_AG_VRE_ACTIVATE)) {
+			LOG_WRN("VR is not activated");
+			return -ENOTSUP;
+		}
+		err = hfp_ag_next_step(ag, bt_hfp_ag_vr_deactivate, NULL);
+		break;
+	case BT_HFP_BVRA_ACTIVATION:
+		if (atomic_test_and_set_bit(ag->flags, BT_HFP_AG_VRE_ACTIVATE)) {
+			LOG_WRN("VR has been activated");
+			return -ENOTSUP;
+		}
+		atomic_clear_bit(ag->flags, BT_HFP_AG_VRE_R2A);
+		err = hfp_ag_next_step(ag, bt_hfp_ag_vr_activate, NULL);
+		break;
+	case BT_HFP_BVRA_READY_TO_ACCEPT:
+		if (!BOTH_SUPT_FEAT(ag, BT_HFP_HF_FEATURE_ENH_VOICE_RECG,
+				    BT_HFP_AG_FEATURE_ENH_VOICE_RECG)) {
+			LOG_WRN("Enhance voice recognition is not supported");
+			return -ENOEXEC;
+		}
+		if (!atomic_test_bit(ag->flags, BT_HFP_AG_VRE_ACTIVATE)) {
+			LOG_WRN("Voice recognition is not activated");
 			return -ENOTSUP;
 		}
+		err = hfp_ag_next_step(ag, bt_hfp_ag_vr_ready2accept, NULL);
+		break;
+	default:
+		return -ENOTSUP;
 	}
 
-	err = get_number(buf, &number);
+	return err;
+}
+
+static int bt_hfp_ag_binp_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	int err;
+	uint32_t value;
+#if defined(CONFIG_BT_HFP_AG_VOICE_TAG)
+	char *number = NULL;
+#endif /* CONFIG_BT_HFP_AG_VOICE_TAG */
+
+	if (!AG_SUPT_FEAT(ag, BT_HFP_AG_FEATURE_VOICE_TAG)) {
+		return -ENOEXEC;
+	}
+
+	if (!is_char(buf, '=')) {
+		return -ENOTSUP;
+	}
+
+	err = get_number(buf, &value);
+	if (err != 0) {
+		return -ENOTSUP;
+	}
+
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	if (value != 1) {
+		return -ENOTSUP;
+	}
+
+#if defined(CONFIG_BT_HFP_AG_VOICE_TAG)
+	if (bt_ag && bt_ag->request_phone_number) {
+		err = bt_ag->request_phone_number(ag, &number);
+		if (err) {
+			LOG_DBG("Cannot request phone number :(%d)", err);
+			return err;
+		}
+
+		err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+BINP:\"%s\"\r\n", number);
+		if (err) {
+			LOG_ERR("Fail to send err :(%d)", err);
+		}
+		return err;
+	}
+#endif /* CONFIG_BT_HFP_AG_VOICE_TAG */
+
+	return -ENOTSUP;
+}
+
+static int bt_hfp_ag_vts_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	int err;
+	char code = 0;
+
+	if (!is_char(buf, '=')) {
+		return -ENOTSUP;
+	}
+
+	err = get_char(buf, &code);
 	if (err != 0) {
 		return -ENOTSUP;
 	}
 
-	if (!is_char(buf, '\r')) {
+	if (!is_char(buf, '\r')) {
+		return -ENOTSUP;
+	}
+
+	if (!IS_VALID_DTMF(code)) {
+		LOG_ERR("Invalid code");
+		return -EINVAL;
+	}
+
+	if (!get_active_calls(ag)) {
+		LOG_ERR("Not valid ongoing call");
 		return -ENOTSUP;
 	}
 
-	if (number == 1) {
-		atomic_set_bit(ag->flags, BT_HFP_AG_CMER_ENABLE);
-		bt_hfp_ag_set_state(ag, BT_HFP_CONNECTED);
-		err = hfp_ag_next_step(ag, bt_hfp_ag_set_in_band_ring, NULL);
-		return err;
-	} else if (number == 0) {
-		atomic_clear_bit(ag->flags, BT_HFP_AG_CMER_ENABLE);
+	if (bt_ag && bt_ag->transmit_dtmf_code) {
+		bt_ag->transmit_dtmf_code(ag, code);
 	} else {
 		return -ENOTSUP;
 	}
@@ -616,129 +3108,53 @@ static int bt_hfp_ag_cmer_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
 	return 0;
 }
 
-static int bt_hfp_ag_chld_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
-{
-	return -EOPNOTSUPP;
-}
-
-static int bt_hfp_ag_bind_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+static int send_subscriber_number(struct bt_hfp_ag *ag, char *number,
+		uint8_t type, uint8_t service)
 {
-	uint32_t indicator;
-	uint32_t hf_indicators = 0U;
 	int err;
-	char *data;
-	uint32_t len;
 
-	hfp_ag_lock(ag);
-	if (!((ag->ag_features & BT_HFP_AG_FEATURE_HF_IND) &&
-	      (ag->hf_features & BT_HFP_HF_FEATURE_HF_IND))) {
-		hfp_ag_unlock(ag);
-		return -EOPNOTSUPP;
+	err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+CNUM:,\"%s\",%d,,%d\r\n",
+		number, type, service);
+	if (err) {
+		LOG_ERR("Fail to send subscriber number :(%d)", err);
 	}
-	hfp_ag_unlock(ag);
-
-	if (is_char(buf, '?')) {
-		if (!is_char(buf, '\r')) {
-			return -ENOTSUP;
-		}
+	return err;
+}
 
-		hfp_ag_lock(ag);
-		hf_indicators = ag->hf_indicators_of_hf & ag->hf_indicators_of_ag;
-		hfp_ag_unlock(ag);
-		len = (sizeof(hf_indicators) * 8) > HFP_HF_IND_MAX ? HFP_HF_IND_MAX
-								   : (sizeof(hf_indicators) * 8);
-		for (int i = 1; i < len; i++) {
-			if (BIT(i) & hf_indicators) {
-				err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+BIND:%d,%d\r\n", i, 1);
-			} else {
-				err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+BIND:%d,%d\r\n", i, 0);
-			}
-			if (err < 0) {
-				return err;
-			}
-			if (hf_indicators == 0) {
-				break;
-			}
-		}
-		return 0;
-	}
+static int bt_hfp_ag_cnum_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+{
+	int err;
 
-	if (!is_char(buf, '=')) {
+	if (!is_char(buf, '\r')) {
 		return -ENOTSUP;
 	}
 
-	if (is_char(buf, '?')) {
-		if (!is_char(buf, '\r')) {
-			return -ENOTSUP;
-		}
-
-		data = &ag->buffer[0];
-		*data = '(';
-		data++;
-		hfp_ag_lock(ag);
-		hf_indicators = ag->hf_indicators_of_ag;
-		hfp_ag_unlock(ag);
-		len = (sizeof(hf_indicators) * 8) > HFP_HF_IND_MAX ? HFP_HF_IND_MAX
-								   : (sizeof(hf_indicators) * 8);
-		for (int i = 1; (i < len) && (hf_indicators != 0); i++) {
-			if (BIT(i) & hf_indicators) {
-				int length = snprintk(
-					data, (char *)&ag->buffer[HF_MAX_BUF_LEN - 1] - data - 3,
-					"%d", i);
-				data += length;
-				hf_indicators &= ~BIT(i);
-			}
-			if (hf_indicators != 0) {
-				*data = ',';
-				data++;
-			}
-		}
-		*data = ')';
-		data++;
-		*data = '\r';
-		data++;
-		*data = '\0';
-		data++;
-
-		err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+BIND:%s\r\n", &ag->buffer[0]);
+	if (bt_ag && bt_ag->subscriber_number) {
+		err = bt_ag->subscriber_number(ag, send_subscriber_number);
 		return err;
 	}
 
-	while (buf->len > 0) {
-		err = get_number(buf, &indicator);
-		if (err != 0) {
-			return -ENOTSUP;
-		}
-
-		if (!is_char(buf, ',')) {
-			if (!is_char(buf, '\r')) {
-				return -ENOTSUP;
-			}
-		}
-
-		if (indicator < (sizeof(hf_indicators) * 8)) {
-			hf_indicators |= BIT(indicator);
-		}
-	}
-
-	hfp_ag_lock(ag);
-	ag->hf_indicators_of_hf = hf_indicators;
-	hfp_ag_unlock(ag);
-
 	return 0;
 }
 
-static int bt_hfp_ag_cmee_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+static int bt_hfp_ag_biev_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
 {
-	uint32_t cmee;
-	int err;
+	uint32_t indicator;
+	uint32_t value;
 
 	if (!is_char(buf, '=')) {
 		return -ENOTSUP;
 	}
 
-	err = get_number(buf, &cmee);
-	if (err != 0) {
+	if (get_number(buf, &indicator)) {
+		return -ENOTSUP;
+	}
+
+	if (!is_char(buf, ',')) {
+		return -ENOTSUP;
+	}
+
+	if (get_number(buf, &value)) {
 		return -ENOTSUP;
 	}
 
@@ -746,1096 +3162,1282 @@ static int bt_hfp_ag_cmee_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
 		return -ENOTSUP;
 	}
 
-	if (cmee > 1) {
+	hfp_ag_lock(ag);
+	if (!(ag->hf_indicators_of_ag & BIT(indicator))) {
+		hfp_ag_unlock(ag);
 		return -ENOTSUP;
 	}
+	hfp_ag_unlock(ag);
 
-	atomic_set_bit_to(ag->flags, BT_HFP_AG_CMEE_ENABLE, cmee == 1);
+#if defined(CONFIG_BT_HFP_AG_HF_INDICATORS)
+	if (bt_ag && bt_ag->hf_indicator_value) {
+		bt_ag->hf_indicator_value(ag, indicator, value);
+	}
+#endif /* CONFIG_BT_HFP_HF_HF_INDICATORS */
 
 	return 0;
 }
 
-static int hfp_ag_update_indicator(struct bt_hfp_ag *ag, enum bt_hfp_ag_indicator index,
-				   uint8_t value, bt_hfp_ag_tx_cb_t cb, void *user_data)
+static struct bt_hfp_ag_at_cmd_handler cmd_handlers[] = {
+	{"AT+BRSF", bt_hfp_ag_brsf_handler}, {"AT+BAC", bt_hfp_ag_bac_handler},
+	{"AT+CIND", bt_hfp_ag_cind_handler}, {"AT+CMER", bt_hfp_ag_cmer_handler},
+	{"AT+CHLD", bt_hfp_ag_chld_handler}, {"AT+BIND", bt_hfp_ag_bind_handler},
+	{"AT+CMEE", bt_hfp_ag_cmee_handler}, {"AT+CHUP", bt_hfp_ag_chup_handler},
+	{"AT+CLCC", bt_hfp_ag_clcc_handler}, {"AT+BIA", bt_hfp_ag_bia_handler},
+	{"ATA", bt_hfp_ag_ata_handler},      {"AT+COPS", bt_hfp_ag_cops_handler},
+	{"AT+BCC", bt_hfp_ag_bcc_handler},   {"AT+BCS", bt_hfp_ag_bcs_handler},
+	{"ATD", bt_hfp_ag_atd_handler},      {"AT+BLDN", bt_hfp_ag_bldn_handler},
+	{"AT+CLIP", bt_hfp_ag_clip_handler}, {"AT+VGM", bt_hfp_ag_vgm_handler},
+	{"AT+VGS", bt_hfp_ag_vgs_handler},   {"AT+NREC", bt_hfp_ag_nrec_handler},
+	{"AT+BTRH", bt_hfp_ag_btrh_handler}, {"AT+CCWA", bt_hfp_ag_ccwa_handler},
+	{"AT+BVRA", bt_hfp_ag_bvra_handler}, {"AT+BINP", bt_hfp_ag_binp_handler},
+	{"AT+VTS", bt_hfp_ag_vts_handler},   {"AT+CNUM", bt_hfp_ag_cnum_handler},
+	{"AT+BIEV", bt_hfp_ag_biev_handler},
+};
+
+static void hfp_ag_connected(struct bt_rfcomm_dlc *dlc)
 {
-	int err;
-	uint8_t old_value;
+	struct bt_hfp_ag *ag = CONTAINER_OF(dlc, struct bt_hfp_ag, rfcomm_dlc);
 
-	hfp_ag_lock(ag);
-	old_value = ag->indicator_value[index];
-	if (value == old_value) {
-		LOG_ERR("Duplicate value setting, indicator %d, old %d -> new %d", index, old_value,
-			value);
-		hfp_ag_unlock(ag);
-		return -EINVAL;
-	}
+	bt_hfp_ag_set_state(ag, BT_HFP_CONFIG);
 
-	ag->indicator_value[index] = value;
-	hfp_ag_unlock(ag);
+	LOG_DBG("AG %p", ag);
+}
 
-	LOG_DBG("indicator %d, old %d -> new %d", index, old_value, value);
+static void hfp_ag_disconnected(struct bt_rfcomm_dlc *dlc)
+{
+	struct bt_hfp_ag *ag = CONTAINER_OF(dlc, struct bt_hfp_ag, rfcomm_dlc);
+	sys_snode_t *node;
+	struct bt_ag_tx *tx;
+	struct bt_hfp_ag_call *call;
 
-	err = hfp_ag_send_data(ag, cb, user_data, "\r\n+CIEV:%d,%d\r\n", (uint8_t)index + 1, value);
-	if (err) {
+	k_work_cancel_delayable(&ag->tx_work);
+
+	hfp_ag_lock(ag);
+	node = sys_slist_get(&ag->tx_pending);
+	hfp_ag_unlock(ag);
+	tx = CONTAINER_OF(node, struct bt_ag_tx, node);
+	while (tx) {
+		if (tx->buf && !atomic_test_and_clear_bit(ag->flags, BT_HFP_AG_TX_ONGOING)) {
+			net_buf_unref(tx->buf);
+		}
+		tx->err = -ESHUTDOWN;
+		k_fifo_put(&ag_tx_notify, tx);
 		hfp_ag_lock(ag);
-		ag->indicator_value[index] = old_value;
+		node = sys_slist_get(&ag->tx_pending);
 		hfp_ag_unlock(ag);
-		LOG_ERR("Fail to update indicator %d, current %d", index, old_value);
+		tx = CONTAINER_OF(node, struct bt_ag_tx, node);
 	}
 
-	return err;
-}
+	bt_hfp_ag_set_state(ag, BT_HFP_DISCONNECTED);
 
-static void hfp_ag_close_sco(struct bt_hfp_ag *ag)
-{
-	struct bt_conn *sco;
+	for (size_t index = 0; index < ARRAY_SIZE(ag->calls); index++) {
+		call = &ag->calls[index];
 
-	LOG_DBG("");
+		if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+			continue;
+		}
 
-	hfp_ag_lock(ag);
-	sco = ag->sco_chan.sco;
-	ag->sco_chan.sco = NULL;
-	hfp_ag_unlock(ag);
-	if (sco != NULL) {
-		LOG_DBG("Disconnect sco %p", sco);
-		bt_conn_disconnect(sco, BT_HCI_ERR_LOCALHOST_TERM_CONN);
+		release_call(call);
 	}
-}
 
-static void bt_hfp_ag_reject_cb(struct bt_hfp_ag *ag, void *user_data)
-{
 	hfp_ag_close_sco(ag);
-	bt_hfp_ag_set_call_state(ag, BT_HFP_CALL_TERMINATE);
 
-	if (bt_ag && bt_ag->reject) {
-		bt_ag->reject(ag);
-	}
+	ag->acl_conn = NULL;
+
+	LOG_DBG("AG %p", ag);
 }
 
-static void bt_hfp_ag_call_reject(struct bt_hfp_ag *ag, void *user_data)
+static void hfp_ag_recv(struct bt_rfcomm_dlc *dlc, struct net_buf *buf)
 {
-	int err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_NONE,
-					    bt_hfp_ag_reject_cb, user_data);
+	struct bt_hfp_ag *ag = CONTAINER_OF(dlc, struct bt_hfp_ag, rfcomm_dlc);
+	uint8_t *data = buf->data;
+	uint16_t len = buf->len;
+	enum at_cme cme_err;
+	int err = -ENOEXEC;
+
+	LOG_HEXDUMP_DBG(data, len, "Received:");
+
+	for (uint32_t index = 0; index < ARRAY_SIZE(cmd_handlers); index++) {
+		if (strlen(cmd_handlers[index].cmd) > len) {
+			continue;
+		}
+		if (strncmp((char *)data, cmd_handlers[index].cmd,
+				 strlen(cmd_handlers[index].cmd)) != 0) {
+			continue;
+		}
+		if (NULL != cmd_handlers[index].handler) {
+			(void)net_buf_pull(buf, strlen(cmd_handlers[index].cmd));
+			err = cmd_handlers[index].handler(ag, buf);
+			LOG_DBG("AT commander is handled (err %d)", err);
+			break;
+		}
+	}
+
+	if ((err != 0) && atomic_test_bit(ag->flags, BT_HFP_AG_CMEE_ENABLE)) {
+		cme_err = bt_hfp_ag_get_cme_err(err);
+		err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+CME ERROR:%d\r\n", (uint32_t)cme_err);
+	} else {
+		err = hfp_ag_send_data(ag, NULL, NULL, "\r\n%s\r\n", (err == 0) ? "OK" : "ERROR");
+	}
+
 	if (err != 0) {
-		LOG_ERR("Fail to send err :(%d)", err);
+		LOG_ERR("HFP AG send response err :(%d)", err);
 	}
 }
 
-static void bt_hfp_ag_terminate_cb(struct bt_hfp_ag *ag, void *user_data)
+static void bt_hfp_ag_thread(void *p1, void *p2, void *p3)
 {
-	hfp_ag_close_sco(ag);
-	bt_hfp_ag_set_call_state(ag, BT_HFP_CALL_TERMINATE);
+	struct bt_ag_tx *tx;
+	bt_hfp_ag_tx_cb_t cb;
+	struct bt_hfp_ag *ag;
+	void *user_data;
+	bt_hfp_state_t state;
+	int err;
 
-	if (bt_ag && bt_ag->terminate) {
-		bt_ag->terminate(ag);
-	}
-}
+	while (true) {
+		tx = (struct bt_ag_tx *)k_fifo_get(&ag_tx_notify, K_FOREVER);
+
+		if (tx == NULL) {
+			continue;
+		}
+
+		cb = tx->cb;
+		ag = tx->ag;
+		user_data = tx->user_data;
+		err = tx->err;
+
+		bt_ag_tx_free(tx);
+
+		if (err < 0) {
+			hfp_ag_lock(ag);
+			state = ag->state;
+			hfp_ag_unlock(ag);
+			if ((state != BT_HFP_DISCONNECTED) && (state != BT_HFP_DISCONNECTING)) {
+				bt_hfp_ag_set_state(ag, BT_HFP_DISCONNECTING);
+				bt_rfcomm_dlc_disconnect(&ag->rfcomm_dlc);
+			}
+		}
 
-static void bt_hfp_ag_unit_call_terminate(struct bt_hfp_ag *ag, void *user_data)
-{
-	int err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 0, bt_hfp_ag_terminate_cb,
-					    user_data);
-	if (err != 0) {
-		LOG_ERR("Fail to send err :(%d)", err);
+		if (cb) {
+			cb(ag, user_data);
+		}
 	}
 }
 
-static int bt_hfp_ag_chup_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+static void hfp_ag_sent(struct bt_rfcomm_dlc *dlc, int err)
 {
-	int err;
-	bt_hfp_call_state_t call_state;
+	struct bt_hfp_ag *ag = CONTAINER_OF(dlc, struct bt_hfp_ag, rfcomm_dlc);
+	sys_snode_t *node;
+	struct bt_ag_tx *tx;
 
-	if (!is_char(buf, '\r')) {
-		return -ENOTSUP;
+	hfp_ag_lock(ag);
+	/* Clear the tx ongoing flag */
+	if (!atomic_test_and_clear_bit(ag->flags, BT_HFP_AG_TX_ONGOING)) {
+		LOG_WRN("tx ongoing flag is not set");
+		hfp_ag_unlock(ag);
+		return;
 	}
 
-	hfp_ag_lock(ag);
-	call_state = ag->call_state;
+	node = sys_slist_get(&ag->tx_pending);
 	hfp_ag_unlock(ag);
-
-	if (call_state == BT_HFP_CALL_ALERTING) {
-		if (!atomic_test_bit(ag->flags, BT_HFP_AG_INCOMING_CALL)) {
-			return -ENOTSUP;
-		}
-		err = hfp_ag_next_step(ag, bt_hfp_ag_call_reject, NULL);
-	} else if ((call_state == BT_HFP_CALL_ACTIVE) || (call_state == BT_HFP_CALL_HOLD)) {
-		err = hfp_ag_next_step(ag, bt_hfp_ag_unit_call_terminate, NULL);
-	} else {
-		return -ENOTSUP;
+	if (!node) {
+		LOG_ERR("No pending tx");
+		return;
 	}
-	return err;
+
+	tx = CONTAINER_OF(node, struct bt_ag_tx, node);
+	LOG_DBG("Completed pending tx %p", tx);
+
+	/* Restart the tx work */
+	k_work_reschedule(&ag->tx_work, K_NO_WAIT);
+
+	tx->err = err;
+	k_fifo_put(&ag_tx_notify, tx);
 }
 
-static uint8_t bt_hfp_get_call_state(struct bt_hfp_ag *ag)
+static const char *bt_ag_get_call_state_string(bt_hfp_call_state_t call_state)
 {
-	uint8_t status = HFP_AG_CLCC_STATUS_INVALID;
+	const char *s;
 
-	hfp_ag_lock(ag);
-	switch (ag->call_state) {
+	switch (call_state) {
 	case BT_HFP_CALL_TERMINATE:
+		s = "terminate";
+		break;
+	case BT_HFP_CALL_ACTIVE:
+		s = "active";
+		break;
+	case BT_HFP_CALL_HOLD:
+		s = "hold";
 		break;
 	case BT_HFP_CALL_OUTGOING:
-		status = HFP_AG_CLCC_STATUS_DIALING;
+		s = "outgoing";
 		break;
 	case BT_HFP_CALL_INCOMING:
-		status = HFP_AG_CLCC_STATUS_INCOMING;
+		s = "incoming";
 		break;
 	case BT_HFP_CALL_ALERTING:
-		if (atomic_test_bit(ag->flags, BT_HFP_AG_INCOMING_CALL)) {
-			status = HFP_AG_CLCC_STATUS_WAITING;
-		} else {
-			status = HFP_AG_CLCC_STATUS_ALERTING;
-		}
-		break;
-	case BT_HFP_CALL_ACTIVE:
-		status = HFP_AG_CLCC_STATUS_ACTIVE;
-		break;
-	case BT_HFP_CALL_HOLD:
-		status = HFP_AG_CLCC_STATUS_HELD;
+		s = "alerting";
 		break;
 	default:
+		s = "unknown";
 		break;
 	}
-	hfp_ag_unlock(ag);
 
-	return status;
+	return s;
 }
 
-static int bt_hfp_ag_clcc_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+static void bt_ag_deferred_work_cb(struct bt_hfp_ag *ag, void *user_data)
 {
 	int err;
-	uint8_t dir;
-	uint8_t status;
-	uint8_t mode;
-	uint8_t mpty;
+	bt_hfp_call_state_t call_state;
+	uint8_t call_setup_ind;
+	uint8_t call_ind;
+	struct bt_hfp_ag_call *call = (struct bt_hfp_ag_call *)user_data;
 
-	if (!is_char(buf, '\r')) {
-		return -ENOTSUP;
-	}
+	LOG_DBG("");
 
 	hfp_ag_lock(ag);
-	if (ag->call_state == BT_HFP_CALL_TERMINATE) {
-		/* AG shall always send OK response to HF */
-		hfp_ag_unlock(ag);
-		return 0;
-	}
+	call_state = call->call_state;
+	call_setup_ind = ag->indicator_value[BT_HFP_AG_CALL_SETUP_IND];
+	call_ind = ag->indicator_value[BT_HFP_AG_CALL_IND];
 	hfp_ag_unlock(ag);
 
-	dir = atomic_test_bit(ag->flags, BT_HFP_AG_INCOMING_CALL) ? 1 : 0;
-	status = bt_hfp_get_call_state(ag);
-	mode = 0;
-	mpty = 0;
-	err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+CLCC:%d,%d,%d,%d,%d\r\n", 1, dir, status, mode,
-			       mpty);
-	if (err != 0) {
-		LOG_ERR("Fail to send err :(%d)", err);
+	switch (call_state) {
+	case BT_HFP_CALL_TERMINATE:
+		break;
+	case BT_HFP_CALL_ACTIVE:
+		break;
+	case BT_HFP_CALL_HOLD:
+		break;
+	case BT_HFP_CALL_OUTGOING:
+	case BT_HFP_CALL_INCOMING:
+	case BT_HFP_CALL_ALERTING:
+	default:
+		LOG_WRN("Call timeout, status %s", bt_ag_get_call_state_string(call_state));
+
+		if (atomic_test_bit(call->flags, BT_HFP_AG_CALL_OUTGOING_3WAY) ||
+		    atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING_3WAY)) {
+			if (!call_setup_ind) {
+				return;
+			}
+
+			err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND,
+						      BT_HFP_CALL_SETUP_NONE,
+						      bt_hfp_ag_reject_cb, call);
+			if (err) {
+				LOG_ERR("Fail to send indicator");
+				bt_hfp_ag_terminate_cb(ag, call);
+			}
+			return;
+		}
+
+		if (call_setup_ind && call_ind) {
+			err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND,
+						      BT_HFP_CALL_SETUP_NONE, NULL, NULL);
+			if (err) {
+				LOG_ERR("Fail to send indicator");
+				bt_hfp_ag_terminate_cb(ag, call);
+			} else {
+				err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 0,
+							      bt_hfp_ag_terminate_cb, call);
+				if (err) {
+					LOG_ERR("Fail to send indicator");
+					bt_hfp_ag_terminate_cb(ag, call);
+				}
+			}
+		} else if (call_setup_ind) {
+			err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND,
+						      BT_HFP_CALL_SETUP_NONE, bt_hfp_ag_reject_cb,
+						      call);
+			if (err) {
+				LOG_ERR("Fail to send indicator");
+				bt_hfp_ag_terminate_cb(ag, call);
+			}
+		} else if (call_ind) {
+			err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 0,
+						      bt_hfp_ag_terminate_cb, call);
+			if (err) {
+				LOG_ERR("Fail to send indicator");
+				bt_hfp_ag_terminate_cb(ag, call);
+			}
+		}
+		break;
 	}
+}
 
-	/* AG shall always send OK response to HF */
-	return 0;
+static void bt_ag_deferred_work(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct bt_hfp_ag_call *call = CONTAINER_OF(dwork, struct bt_hfp_ag_call, deferred_work);
+	struct bt_hfp_ag *ag = call->ag;
+
+	LOG_DBG("");
+
+	if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+		return;
+	}
+
+	(void)hfp_ag_next_step(ag, bt_ag_deferred_work_cb, call);
 }
 
-static int bt_hfp_ag_bia_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+static void bt_ag_ringing_work_cb(struct bt_hfp_ag *ag, void *user_data)
 {
-	uint32_t number;
 	int err;
-	int index = 0;
-	uint32_t indicator;
+	bt_hfp_call_state_t call_state;
+	struct bt_hfp_ag_call *call = (struct bt_hfp_ag_call *)user_data;
 
-	if (!is_char(buf, '=')) {
-		return -ENOTSUP;
-	}
+	LOG_DBG("");
 
 	hfp_ag_lock(ag);
-	indicator = ag->indicator;
+	call_state = call->call_state;
 	hfp_ag_unlock(ag);
+	if (call_state == BT_HFP_CALL_ALERTING) {
 
-	while (buf->len > 0) {
-		err = get_number(buf, &number);
-		if (err == 0) {
-			/* Valid number */
-			if (number) {
-				indicator |= BIT(index);
-			} else {
-				indicator &= ~BIT(index);
-			}
+		if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING)) {
+			return;
 		}
 
-		if (is_char(buf, ',')) {
-			index++;
+		k_work_reschedule(&call->ringing_work,
+				  K_SECONDS(CONFIG_BT_HFP_AG_RING_NOTIFY_INTERVAL));
+
+		err = hfp_ag_send_data(ag, NULL, NULL, "\r\nRING\r\n");
+		if (err) {
+			LOG_ERR("Fail to send RING %d", err);
 		} else {
-			if (!is_char(buf, '\r')) {
-				return -ENOTSUP;
-			}
-			if (buf->len != 0) {
-				return -ENOTSUP;
+			if (atomic_test_bit(ag->flags, BT_HFP_AG_CLIP_ENABLE)) {
+				err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+CLIP:\"%s\",%d\r\n",
+						       call->number, 0);
+				if (err) {
+					LOG_ERR("Fail to send CLIP %d", err);
+				}
 			}
 		}
 	}
+}
 
-	/* Force call, call setup and held call indicators are enabled. */
-	indicator = BIT(BT_HFP_AG_CALL_IND) | BIT(BT_HFP_AG_CALL_SETUP_IND) |
-		    BIT(BT_HFP_AG_CALL_HELD_IND);
+static void bt_ag_ringing_work(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct bt_hfp_ag_call *call = CONTAINER_OF(dwork, struct bt_hfp_ag_call, ringing_work);
 
-	hfp_ag_lock(ag);
-	ag->indicator = indicator;
-	hfp_ag_unlock(ag);
+	LOG_DBG("");
 
-	return 0;
+	if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_IN_USING)) {
+		return;
+	}
+
+	(void)hfp_ag_next_step(call->ag, bt_ag_ringing_work_cb, call);
 }
 
-static void bt_hfp_ag_accept_cb(struct bt_hfp_ag *ag, void *user_data)
+static K_KERNEL_STACK_MEMBER(ag_thread_stack, CONFIG_BT_HFP_AG_THREAD_STACK_SIZE);
+
+static struct bt_hfp_ag *hfp_ag_create(struct bt_conn *conn)
 {
-	bt_hfp_ag_set_call_state(ag, BT_HFP_CALL_ACTIVE);
+	static struct bt_rfcomm_dlc_ops ops = {
+		.connected = hfp_ag_connected,
+		.disconnected = hfp_ag_disconnected,
+		.recv = hfp_ag_recv,
+		.sent = hfp_ag_sent,
+	};
+	static k_tid_t ag_thread_id;
+	static struct k_thread ag_thread;
+	size_t index;
+	struct bt_hfp_ag *ag;
 
-	if (bt_ag && bt_ag->accept) {
-		bt_ag->accept(ag);
+	LOG_DBG("conn %p", conn);
+
+	if (ag_thread_id == NULL) {
+
+		k_fifo_init(&ag_tx_free);
+		k_fifo_init(&ag_tx_notify);
+
+		for (index = 0; index < ARRAY_SIZE(ag_tx); index++) {
+			k_fifo_put(&ag_tx_free, &ag_tx[index]);
+		}
+
+		ag_thread_id = k_thread_create(
+			&ag_thread, ag_thread_stack, K_KERNEL_STACK_SIZEOF(ag_thread_stack),
+			bt_hfp_ag_thread, NULL, NULL, NULL,
+			K_PRIO_COOP(CONFIG_BT_HFP_AG_THREAD_PRIO), 0, K_NO_WAIT);
+		__ASSERT(ag_thread_id, "Cannot create thread for AG");
+		k_thread_name_set(ag_thread_id, "HFP AG");
+	}
+
+	index = (size_t)bt_conn_index(conn);
+	ag = &bt_hfp_ag_pool[index];
+	if (ag->acl_conn) {
+		LOG_ERR("AG connection (%p) is established", conn);
+		return NULL;
 	}
+
+	(void)memset(ag, 0, sizeof(struct bt_hfp_ag));
+
+	sys_slist_init(&ag->tx_pending);
+
+	k_sem_init(&ag->lock, 1, 1);
+
+	ag->rfcomm_dlc.ops = &ops;
+	ag->rfcomm_dlc.mtu = BT_HFP_MAX_MTU;
+
+	/* Set the supported features*/
+	ag->ag_features = BT_HFP_AG_SUPPORTED_FEATURES;
+
+	/* Support HF indicators */
+	if (IS_ENABLED(CONFIG_BT_HFP_AG_HF_INDICATOR_ENH_SAFETY)) {
+		ag->hf_indicators_of_ag |= BIT(HFP_HF_ENHANCED_SAFETY_IND);
+	}
+
+	if (IS_ENABLED(CONFIG_BT_HFP_AG_HF_INDICATOR_BATTERY)) {
+		ag->hf_indicators_of_ag |= BIT(HFP_HF_BATTERY_LEVEL_IND);
+	}
+
+	ag->hf_indicators = ag->hf_indicators_of_ag;
+
+	/* If supported codec ids cannot be notified, disable codec negotiation. */
+	if (!(bt_ag && bt_ag->codec)) {
+		ag->ag_features &= ~BT_HFP_AG_FEATURE_CODEC_NEG;
+	}
+
+	ag->hf_features = 0;
+	ag->hf_codec_ids = 0;
+
+	ag->acl_conn = conn;
+
+	/* Set AG indicator value */
+	ag->indicator_value[BT_HFP_AG_SERVICE_IND] = 0;
+	ag->indicator_value[BT_HFP_AG_CALL_IND] = 0;
+	ag->indicator_value[BT_HFP_AG_CALL_SETUP_IND] = 0;
+	ag->indicator_value[BT_HFP_AG_CALL_HELD_IND] = 0;
+	ag->indicator_value[BT_HFP_AG_SIGNAL_IND] = 0;
+	ag->indicator_value[BT_HFP_AG_ROAM_IND] = 0;
+	ag->indicator_value[BT_HFP_AG_BATTERY_IND] = 0;
+
+	/* Set AG indicator status */
+	ag->indicator = BIT(BT_HFP_AG_SERVICE_IND) | BIT(BT_HFP_AG_CALL_IND) |
+				BIT(BT_HFP_AG_CALL_SETUP_IND) | BIT(BT_HFP_AG_CALL_HELD_IND) |
+				BIT(BT_HFP_AG_SIGNAL_IND) | BIT(BT_HFP_AG_ROAM_IND) |
+				BIT(BT_HFP_AG_BATTERY_IND);
+
+	/* Set AG operator */
+	memcpy(ag->operator, "UNKNOWN", sizeof("UNKNOWN"));
+
+	/* Set Codec ID*/
+	ag->selected_codec_id = BT_HFP_AG_CODEC_CVSD;
+
+	/* Init delay work */
+	k_work_init_delayable(&ag->tx_work, bt_ag_tx_work);
+
+	return ag;
 }
 
-static void bt_hfp_ag_call_ringing_cb(struct bt_hfp_ag *ag, bool in_bond)
+int bt_hfp_ag_connect(struct bt_conn *conn, struct bt_hfp_ag **ag, uint8_t channel)
 {
-	if (bt_ag && bt_ag->ringing) {
-		bt_ag->ringing(ag, in_bond);
+	struct bt_hfp_ag *new_ag;
+	int err;
+
+	LOG_DBG("");
+
+	if (!conn || !ag || !channel) {
+		return -EINVAL;
+	}
+
+	if (!bt_ag) {
+		return -EFAULT;
+	}
+
+	new_ag = hfp_ag_create(conn);
+	if (!new_ag) {
+		return -ECONNREFUSED;
+	}
+
+	err = bt_rfcomm_dlc_connect(conn, &new_ag->rfcomm_dlc, channel);
+	if (err != 0) {
+		(void)memset(new_ag, 0, sizeof(*new_ag));
+		*ag = NULL;
+	} else {
+		*ag = new_ag;
+		bt_hfp_ag_set_state(*ag, BT_HFP_CONNECTING);
 	}
+
+	return err;
 }
 
-static void hfp_ag_sco_connected(struct bt_sco_chan *chan)
+int bt_hfp_ag_disconnect(struct bt_hfp_ag *ag)
 {
-	struct bt_hfp_ag *ag = CONTAINER_OF(chan, struct bt_hfp_ag, sco_chan);
-	bt_hfp_call_state_t call_state;
+	LOG_DBG("");
 
-	hfp_ag_lock(ag);
-	call_state = ag->call_state;
-	hfp_ag_unlock(ag);
-	if (call_state == BT_HFP_CALL_INCOMING) {
-		bt_hfp_ag_set_call_state(ag, BT_HFP_CALL_ALERTING);
-		bt_hfp_ag_call_ringing_cb(ag, true);
+	if (ag == NULL) {
+		return -EINVAL;
 	}
 
-	if ((bt_ag) && bt_ag->sco_connected) {
-		bt_ag->sco_connected(ag, chan->sco);
-	}
+	bt_hfp_ag_set_state(ag, BT_HFP_DISCONNECTING);
+
+	return bt_rfcomm_dlc_disconnect(&ag->rfcomm_dlc);
 }
 
-static void hfp_ag_sco_disconnected(struct bt_sco_chan *chan, uint8_t reason)
+static int hfp_ag_accept(struct bt_conn *conn, struct bt_rfcomm_server *server,
+			 struct bt_rfcomm_dlc **dlc)
 {
-	struct bt_hfp_ag *ag = CONTAINER_OF(chan, struct bt_hfp_ag, sco_chan);
-	bt_hfp_call_state_t call_state;
+	struct bt_hfp_ag *ag;
 
-	if ((bt_ag) && bt_ag->sco_disconnected) {
-		bt_ag->sco_disconnected(ag);
-	}
+	ag = hfp_ag_create(conn);
 
-	hfp_ag_lock(ag);
-	call_state = ag->call_state;
-	hfp_ag_unlock(ag);
-	if ((call_state == BT_HFP_CALL_INCOMING) || (call_state == BT_HFP_CALL_OUTGOING)) {
-		bt_hfp_ag_call_reject(ag, NULL);
+	if (!ag) {
+		return -ECONNREFUSED;
 	}
+
+	*dlc = &ag->rfcomm_dlc;
+
+	return 0;
 }
 
-static struct bt_conn *bt_hfp_ag_create_sco(struct bt_hfp_ag *ag)
+static int bt_hfp_ag_sco_accept(const struct bt_sco_accept_info *info,
+		struct bt_sco_chan **chan)
 {
-	struct bt_conn *sco_conn;
-
 	static struct bt_sco_chan_ops ops = {
 		.connected = hfp_ag_sco_connected,
 		.disconnected = hfp_ag_sco_disconnected,
 	};
+	size_t index;
+	struct bt_hfp_ag *ag;
 
-	LOG_DBG("");
+	LOG_DBG("conn %p", info->acl);
 
-	if (ag->sco_chan.sco == NULL) {
-		ag->sco_chan.ops = &ops;
+	index = (size_t)bt_conn_index(info->acl);
+	ag = &bt_hfp_ag_pool[index];
+	if (ag->acl_conn != info->acl) {
+		LOG_ERR("ACL %p of AG is unaligned with SCO's %p", ag->acl_conn, info->acl);
+		return -EINVAL;
+	}
 
-		/* create SCO connection*/
-		sco_conn = bt_conn_create_sco(&ag->acl_conn->br.dst, &ag->sco_chan);
-		if (sco_conn != NULL) {
-			LOG_DBG("Created sco %p", sco_conn);
-			bt_conn_unref(sco_conn);
-		}
-	} else {
-		sco_conn = ag->sco_chan.sco;
+	if (ag->sco_chan.sco) {
+		return -ECONNREFUSED;
 	}
 
-	return sco_conn;
+	ag->sco_chan.ops = &ops;
+
+	*chan = &ag->sco_chan;
+
+	return 0;
 }
 
-static int hfp_ag_open_sco(struct bt_hfp_ag *ag)
+static void hfp_ag_init(void)
 {
-	bool create_sco;
+	static struct bt_rfcomm_server chan = {
+		.channel = BT_RFCOMM_CHAN_HFP_AG,
+		.accept = hfp_ag_accept,
+	};
 
-	if (atomic_test_bit(ag->flags, BT_HFP_AG_CREATING_SCO)) {
-		LOG_WRN("SCO connection is creating!");
-		return 0;
-	}
+	bt_rfcomm_server_register(&chan);
 
-	hfp_ag_lock(ag);
-	create_sco = (ag->sco_chan.sco == NULL) ? true : false;
-	if (create_sco) {
-		atomic_set_bit(ag->flags, BT_HFP_AG_CREATING_SCO);
-	}
-	hfp_ag_unlock(ag);
+	static struct bt_sco_server sco_server = {
+		.sec_level = BT_SECURITY_L0,
+		.accept = bt_hfp_ag_sco_accept,
+	};
 
-	if (create_sco) {
-		struct bt_conn *sco_conn = bt_hfp_ag_create_sco(ag);
+	bt_sco_server_register(&sco_server);
 
-		atomic_clear_bit(ag->flags, BT_HFP_AG_CREATING_SCO);
+	bt_sdp_register_service(&hfp_ag_rec);
+}
 
-		if (sco_conn == NULL) {
-			LOG_ERR("Fail to create sco connection!");
-			return -ENOTCONN;
-		}
+int bt_hfp_ag_register(struct bt_hfp_ag_cb *cb)
+{
+	if (!cb) {
+		return -EINVAL;
+	}
 
-		LOG_DBG("SCO connection created (%p)", sco_conn);
+	if (bt_ag) {
+		return -EALREADY;
 	}
 
+	bt_ag = cb;
+
+	hfp_ag_init();
+
 	return 0;
 }
 
-static int bt_hfp_ag_codec_select(struct bt_hfp_ag *ag)
+static void bt_hfp_ag_incoming_cb(struct bt_hfp_ag *ag, void *user_data)
 {
-	int err;
+	struct bt_hfp_ag_call *call = (struct bt_hfp_ag_call *)user_data;
 
-	LOG_DBG("");
+	__ASSERT(call, "Invalid call object");
 
-	hfp_ag_lock(ag);
-	if (ag->selected_codec_id == 0) {
-		LOG_ERR("Codec is invalid");
-		hfp_ag_unlock(ag);
-		return -EINVAL;
-	}
+	bt_hfp_ag_set_call_state(call, BT_HFP_CALL_INCOMING);
 
-	if (!(ag->hf_codec_ids & BIT(ag->selected_codec_id))) {
-		LOG_ERR("Codec is unsupported (codec id %d)", ag->selected_codec_id);
-		hfp_ag_unlock(ag);
-		return -EINVAL;
+	if (bt_ag && bt_ag->incoming) {
+		bt_ag->incoming(ag, call, call->number);
 	}
-	hfp_ag_unlock(ag);
 
-	err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+BCS:%d\r\n", ag->selected_codec_id);
-	if (err != 0) {
-		LOG_ERR("Fail to send err :(%d)", err);
+	if (atomic_test_bit(ag->flags, BT_HFP_AG_INBAND_RING)) {
+		int err;
+
+		err = bt_hfp_ag_create_audio_connection(ag, call);
+		if (err) {
+			bt_hfp_ag_call_reject(ag, user_data);
+		}
+	} else {
+		bt_hfp_ag_set_call_state(call, BT_HFP_CALL_ALERTING);
+		bt_hfp_ag_call_ringing_cb(call, false);
 	}
-	return err;
 }
 
-static int bt_hfp_ag_create_audio_connection(struct bt_hfp_ag *ag)
+#if defined(CONFIG_BT_HFP_AG_3WAY_CALL)
+static void bt_hfp_ag_2nd_incoming_cb(struct bt_hfp_ag *ag, void *user_data)
 {
-	int err;
-	uint32_t hf_codec_ids;
+	struct bt_hfp_ag_call *call;
 
-	hfp_ag_lock(ag);
-	hf_codec_ids = ag->hf_codec_ids;
-	hfp_ag_unlock(ag);
+	call = (struct bt_hfp_ag_call *)user_data;
 
-	if ((hf_codec_ids != 0) && atomic_test_bit(ag->flags, BT_HFP_AG_CODEC_CHANGED)) {
-		atomic_set_bit(ag->flags, BT_HFP_AG_CODEC_CONN);
-		err = bt_hfp_ag_codec_select(ag);
-	} else {
-		err = hfp_ag_open_sco(ag);
+	__ASSERT(call, "Invalid call object");
+
+	if (bt_ag && bt_ag->incoming) {
+		bt_ag->incoming(ag, call, call->number);
 	}
 
-	return err;
+	bt_hfp_ag_set_call_state(call, BT_HFP_CALL_ALERTING);
 }
 
-static void bt_hfp_ag_audio_connection(struct bt_hfp_ag *ag, void *user_data)
+static void bt_hfp_ag_ccwa_cb(struct bt_hfp_ag *ag, void *user_data)
 {
 	int err;
 
-	err = bt_hfp_ag_create_audio_connection(ag);
+	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_INCOMING,
+				      bt_hfp_ag_2nd_incoming_cb, user_data);
 	if (err) {
-		bt_hfp_ag_unit_call_terminate(ag, user_data);
+		LOG_ERR("Fail to send call setup");
 	}
 }
+#endif /* CONFIG_BT_HFP_AG_3WAY_CALL */
 
-static void bt_hfp_ag_unit_call_accept(struct bt_hfp_ag *ag, void *user_data)
+int bt_hfp_ag_remote_incoming(struct bt_hfp_ag *ag, const char *number)
 {
-	int err;
-
-	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 1, bt_hfp_ag_accept_cb, user_data);
-	if (err != 0) {
-		LOG_ERR("Fail to send err :(%d)", err);
-	}
-
-	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_NONE,
-					bt_hfp_ag_audio_connection, user_data);
-	if (err != 0) {
-		LOG_ERR("Fail to send err :(%d)", err);
-	}
-}
+	int err = 0;
+	size_t len;
+	struct bt_hfp_ag_call *call;
+	int call_count;
 
-static int bt_hfp_ag_ata_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
-{
-	int err;
+	LOG_DBG("");
 
-	if (!is_char(buf, '\r')) {
-		return -ENOTSUP;
+	if (ag == NULL) {
+		return -EINVAL;
 	}
 
 	hfp_ag_lock(ag);
-	if (ag->call_state != BT_HFP_CALL_ALERTING) {
+	if (ag->state != BT_HFP_CONNECTED) {
 		hfp_ag_unlock(ag);
-		return -ENOTSUP;
+		return -ENOTCONN;
 	}
 	hfp_ag_unlock(ag);
 
-	if (!atomic_test_bit(ag->flags, BT_HFP_AG_INCOMING_CALL)) {
-		return -ENOTSUP;
+	len = strlen(number);
+	if ((len == 0) || (len > CONFIG_BT_HFP_AG_PHONE_NUMBER_MAX_LEN)) {
+		return -EINVAL;
 	}
 
-	err = hfp_ag_next_step(ag, bt_hfp_ag_unit_call_accept, NULL);
-
-	return err;
-}
-
-static int bt_hfp_ag_cops_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
-{
-	int err;
-	uint32_t number;
-
-	if (is_char(buf, '=')) {
-		static const uint32_t command_line_prefix[] = {3, 0};
-
-		for (int i = 0; i < ARRAY_SIZE(command_line_prefix); i++) {
-			err = get_number(buf, &number);
-			if (err != 0) {
-				return -ENOTSUP;
-			}
+	call = get_call_from_number(ag, number, 0);
+	if (call) {
+		return -EBUSY;
+	}
 
-			if (command_line_prefix[i] != number) {
-				return -ENOTSUP;
-			}
+	call_count = get_none_released_calls(ag);
+	if (call_count) {
+#if defined(CONFIG_BT_HFP_AG_3WAY_CALL)
+		if (!BOTH_SUPT_FEAT(ag, BT_HFP_HF_FEATURE_3WAY_CALL,
+				    BT_HFP_AG_FEATURE_3WAY_CALL)) {
+			LOG_WRN("3 Way call feature is not supported on both sides");
+			return -ENOEXEC;
+		}
 
-			if (!is_char(buf, ',')) {
-				if (!is_char(buf, '\r')) {
-					return -ENOTSUP;
-				}
-			}
+		if (!atomic_test_bit(ag->flags, BT_HFP_AG_CCWA_ENABLE)) {
+			LOG_WRN("Call waiting notification is not enabled");
+			return -ENOTSUP;
 		}
 
-		atomic_set_bit(ag->flags, BT_HFP_AG_COPS_SET);
-		return 0;
+		if (!get_active_held_calls(ag)) {
+			LOG_WRN("The first call is not accepted");
+			return -EBUSY;
+		}
+#else
+		return -EBUSY;
+#endif /* CONFIG_BT_HFP_AG_3WAY_CALL */
 	}
 
-	if (!atomic_test_bit(ag->flags, BT_HFP_AG_COPS_SET)) {
-		return -ENOTSUP;
+	call = get_new_call(ag, number, 0);
+	if (!call) {
+		LOG_WRN("Cannot allocate a new call object");
+		return -ENOMEM;
 	}
 
-	if (!is_char(buf, '?')) {
-		return -ENOTSUP;
-	}
+	atomic_set_bit(call->flags, BT_HFP_AG_CALL_INCOMING);
+	bt_hfp_ag_set_call_state(call, BT_HFP_CALL_INCOMING);
 
-	if (!is_char(buf, '\r')) {
-		return -ENOTSUP;
+#if defined(CONFIG_BT_HFP_AG_3WAY_CALL)
+	if (call_count) {
+		atomic_set_bit(call->flags, BT_HFP_AG_CALL_INCOMING_3WAY);
+		err = hfp_ag_send_data(ag, bt_hfp_ag_ccwa_cb, call, "\r\n+CCWA:\"%s\",%d\r\n",
+				       call->number, call->type);
+		if (err) {
+			LOG_WRN("Fail to send call waiting notification");
+			free_call(call);
+		}
+
+		return err;
 	}
+#endif /* CONFIG_BT_HFP_AG_3WAY_CALL */
 
-	err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+COPS:%d,%d,\"%s\"\r\n", 0, 0, ag->operator);
-	if (err != 0) {
-		LOG_ERR("Fail to send err :(%d)", err);
+	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_INCOMING,
+				      bt_hfp_ag_incoming_cb, call);
+	if (err) {
+		free_call(call);
 	}
 
 	return err;
 }
 
-static int bt_hfp_ag_bcc_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+int bt_hfp_ag_hold_incoming(struct bt_hfp_ag_call *call)
 {
-	int err;
+	int err = 0;
+	struct bt_hfp_ag *ag;
+	bt_hfp_call_state_t call_state;
 
-	if (!is_char(buf, '\r')) {
-		return -ENOTSUP;
-	}
+	LOG_DBG("");
 
-	hfp_ag_lock(ag);
-	if ((ag->selected_codec_id == 0) ||
-		(!(ag->hf_codec_ids & BIT(ag->selected_codec_id))) ||
-		(ag->call_state == BT_HFP_CALL_TERMINATE) ||
-		(ag->sco_chan.sco != NULL)) {
-		hfp_ag_unlock(ag);
-		return -ENOTSUP;
+	if (call == NULL) {
+		return -EINVAL;
 	}
-	hfp_ag_unlock(ag);
-
-	err = hfp_ag_next_step(ag, bt_hfp_ag_audio_connection, NULL);
-
-	return 0;
-}
 
-static void bt_hfp_ag_unit_codec_conn_setup(struct bt_hfp_ag *ag, void *user_data)
-{
-	int err = hfp_ag_open_sco(ag);
+	ag = call->ag;
 
-	if (err) {
-		bt_hfp_ag_call_reject(ag, user_data);
+	if (ag == NULL) {
+		return -EINVAL;
 	}
-}
-
-static int bt_hfp_ag_bcs_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
-{
-	int err;
-	uint32_t number;
 
-	if (!is_char(buf, '=')) {
-		return -ENOTSUP;
+	hfp_ag_lock(ag);
+	if (ag->state != BT_HFP_CONNECTED) {
+		hfp_ag_unlock(ag);
+		return -ENOTCONN;
 	}
 
-	err = get_number(buf, &number);
-	if (err != 0) {
-		return -ENOTSUP;
-	}
+	call_state = call->call_state;
+	hfp_ag_unlock(ag);
 
-	if (!is_char(buf, '\r')) {
-		return -ENOTSUP;
+	if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING)) {
+		return -EINVAL;
 	}
 
-	if (!atomic_test_bit(ag->flags, BT_HFP_AG_CODEC_CONN)) {
-		return -ESRCH;
+	if ((call_state == BT_HFP_CALL_ALERTING) || (call_state == BT_HFP_CALL_INCOMING)) {
+		atomic_set_bit(call->flags, BT_HFP_AG_CALL_INCOMING_HELD);
+		err = hfp_ag_send_data(ag, btrh_held_cb, call, "\r\n+BTRH:%d\r\n",
+				       BT_HFP_BTRH_ON_HOLD);
+		if (err) {
+			LOG_ERR("Fail to send err :(%d)", err);
+		}
+		return err;
 	}
 
-	hfp_ag_lock(ag);
-	if (ag->selected_codec_id != number) {
-		LOG_ERR("Received codec id %d is not aligned with selected %d",
-				number, ag->selected_codec_id);
-		err = -ENOTSUP;
-	} else if (!(ag->hf_codec_ids & BIT(ag->selected_codec_id))) {
-		LOG_ERR("Selected codec id %d is unsupported %d",
-				ag->selected_codec_id, ag->hf_codec_ids);
-		err = -ENOTSUP;
-	}
-	hfp_ag_unlock(ag);
+	return -EINVAL;
+}
 
-	atomic_clear_bit(ag->flags, BT_HFP_AG_CODEC_CONN);
-	atomic_clear_bit(ag->flags, BT_HFP_AG_CODEC_CHANGED);
+int bt_hfp_ag_reject(struct bt_hfp_ag_call *call)
+{
+	int err = 0;
+	struct bt_hfp_ag *ag;
+	bt_hfp_call_state_t call_state;
 
-	if (err == 0) {
-		err = hfp_ag_next_step(ag, bt_hfp_ag_unit_codec_conn_setup, NULL);
-	} else {
-		bt_hfp_call_state_t call_state;
+	LOG_DBG("");
 
-		hfp_ag_lock(ag);
-		call_state = ag->call_state;
-		hfp_ag_unlock(ag);
-		if (call_state != BT_HFP_CALL_TERMINATE) {
-			(void)hfp_ag_next_step(ag, bt_hfp_ag_unit_call_terminate, NULL);
-		}
+	if (call == NULL) {
+		return -EINVAL;
 	}
 
-	return err;
-}
+	ag = call->ag;
 
-static void bt_hfp_ag_unit_call_outgoing(struct bt_hfp_ag *ag, void *user_data)
-{
-	int err = bt_hfp_ag_outgoing(ag, ag->number);
+	if (ag == NULL) {
+		return -EINVAL;
+	}
 
-	if (err != 0) {
-		LOG_ERR("Fail to send err :(%d)", err);
+	hfp_ag_lock(ag);
+	if (ag->state != BT_HFP_CONNECTED) {
+		hfp_ag_unlock(ag);
+		return -ENOTCONN;
 	}
-}
 
-static int bt_hfp_ag_atd_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
-{
-	int err;
-	char *number = NULL;
-	bool is_memory_dial = false;
-	size_t len;
+	call_state = call->call_state;
+	hfp_ag_unlock(ag);
 
-	if (buf->data[buf->len - 1] != '\r') {
-		return -ENOTSUP;
+	if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING)) {
+		return -EINVAL;
 	}
 
-	if (is_char(buf, '>')) {
-		is_memory_dial = true;
+	if (!AG_SUPT_FEAT(ag, BT_HFP_AG_FEATURE_REJECT_CALL)) {
+		LOG_ERR("AG has not ability to reject call");
+		return -ENOTSUP;
 	}
 
-	if ((buf->len - 1) > CONFIG_BT_HFP_AG_PHONE_NUMBER_MAX_LEN) {
-		return -ENAMETOOLONG;
-	}
+	if (atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING_3WAY)) {
+		if ((call_state == BT_HFP_CALL_ALERTING) || (call_state == BT_HFP_CALL_INCOMING)) {
+			uint8_t call_setup;
 
-	buf->data[buf->len - 1] = '\0';
+			hfp_ag_lock(ag);
+			call_setup = ag->indicator_value[BT_HFP_AG_CALL_SETUP_IND];
+			hfp_ag_unlock(ag);
 
-	if (is_memory_dial) {
-		if (bt_ag && bt_ag->memory_dial) {
-			err = bt_ag->memory_dial(ag, &buf->data[0], &number);
-			if ((err != 0) || (number == NULL)) {
-				return -ENOTSUP;
+			if (call_setup) {
+				err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND,
+							      BT_HFP_CALL_SETUP_NONE, NULL, NULL);
+				if (err) {
+					return err;
+				}
 			}
-		} else {
-			return -ENOTSUP;
+
+			ag_reject_call(call);
+
+			return 0;
 		}
-	} else {
-		number = &buf->data[0];
 	}
 
-	len = strlen(number);
-	if (len == 0) {
-		return -ENOTSUP;
-	}
+	if ((call_state == BT_HFP_CALL_ALERTING) || (call_state == BT_HFP_CALL_INCOMING)) {
+		err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_NONE,
+					      bt_hfp_ag_reject_cb, call);
 
-	if (len > CONFIG_BT_HFP_AG_PHONE_NUMBER_MAX_LEN) {
-		return -ENAMETOOLONG;
+		return err;
 	}
 
-	hfp_ag_lock(ag);
-	if (ag->call_state != BT_HFP_CALL_TERMINATE) {
-		hfp_ag_unlock(ag);
-		return -EBUSY;
+	if ((call_state == BT_HFP_CALL_ACTIVE) &&
+	    atomic_test_and_clear_bit(call->flags, BT_HFP_AG_CALL_INCOMING_HELD)) {
+		err = hfp_ag_send_data(ag, btrh_reject_cb, call, "\r\n+BTRH:%d\r\n",
+				       BT_HFP_BTRH_REJECTED);
+		if (err) {
+			LOG_ERR("Fail to send err :(%d)", err);
+		}
+		return err;
 	}
 
-	/* Copy number to ag->number including null-character */
-	memcpy(ag->number, number, len + 1);
-	hfp_ag_unlock(ag);
-
-	err = hfp_ag_next_step(ag, bt_hfp_ag_unit_call_outgoing, NULL);
-
-	return err;
+	return -EINVAL;
 }
 
-static int bt_hfp_ag_bldn_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
+int bt_hfp_ag_accept(struct bt_hfp_ag_call *call)
 {
-	int err;
+	int err = 0;
+	struct bt_hfp_ag *ag;
+	bt_hfp_call_state_t call_state;
 
-	if (!is_char(buf, '\r')) {
-		return -ENOTSUP;
+	LOG_DBG("");
+
+	if (call == NULL) {
+		return -EINVAL;
 	}
 
-	hfp_ag_lock(ag);
-	if (strlen(ag->number) == 0) {
-		hfp_ag_unlock(ag);
-		return -ENOSR;
+	ag = call->ag;
+
+	if (ag == NULL) {
+		return -EINVAL;
 	}
 
-	if (ag->call_state != BT_HFP_CALL_TERMINATE) {
+	hfp_ag_lock(ag);
+	if (ag->state != BT_HFP_CONNECTED) {
 		hfp_ag_unlock(ag);
-		return -EBUSY;
+		return -ENOTCONN;
 	}
+
+	call_state = call->call_state;
 	hfp_ag_unlock(ag);
 
-	err = hfp_ag_next_step(ag, bt_hfp_ag_unit_call_outgoing, NULL);
+	if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING)) {
+		return -EINVAL;
+	}
 
-	return err;
-}
+#if defined(CONFIG_BT_HFP_AG_3WAY_CALL)
+	if (atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING_3WAY)) {
+		if ((call_state == BT_HFP_CALL_ALERTING) || (call_state == BT_HFP_CALL_INCOMING)) {
+			return chld_deactivate_calls_and_accept_other_call(ag, false);
+		}
+	}
+#endif /* CONFIG_BT_HFP_AG_3WAY_CALL */
 
-static int bt_hfp_ag_clip_handler(struct bt_hfp_ag *ag, struct net_buf *buf)
-{
-	int err;
-	uint32_t clip;
+	if (call_state == BT_HFP_CALL_ALERTING) {
+		err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 1, bt_hfp_ag_accept_cb, call);
+		if (err) {
+			LOG_ERR("Fail to send err :(%d)", err);
+		}
 
-	err = get_number(buf, &clip);
-	if (err != 0) {
-		return -ENOTSUP;
-	}
+		err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_NONE,
+					      bt_hfp_ag_call_setup_none_cb, call);
+		if (err) {
+			LOG_ERR("Fail to send err :(%d)", err);
+		}
 
-	if (!is_char(buf, '\r')) {
-		return -ENOTSUP;
+		return err;
 	}
 
-	if (clip > 1) {
-		return -ENOTSUP;
+	if (atomic_test_and_clear_bit(call->flags, BT_HFP_AG_CALL_INCOMING_HELD) &&
+	    (call_state == BT_HFP_CALL_ACTIVE)) {
+		err = hfp_ag_send_data(ag, btrh_accept_cb, call, "\r\n+BTRH:%d\r\n",
+				       BT_HFP_BTRH_ACCEPTED);
+		if (err) {
+			LOG_ERR("Fail to send err :(%d)", err);
+		}
+		return err;
 	}
 
-	atomic_set_bit_to(ag->flags, BT_HFP_AG_CLIP_ENABLE, clip == 1);
-
-	return err;
+	return -EINVAL;
 }
 
-static struct bt_hfp_ag_at_cmd_handler cmd_handlers[] = {
-	{"AT+BRSF", bt_hfp_ag_brsf_handler}, {"AT+BAC", bt_hfp_ag_bac_handler},
-	{"AT+CIND", bt_hfp_ag_cind_handler}, {"AT+CMER", bt_hfp_ag_cmer_handler},
-	{"AT+CHLD", bt_hfp_ag_chld_handler}, {"AT+BIND", bt_hfp_ag_bind_handler},
-	{"AT+CMEE", bt_hfp_ag_cmee_handler}, {"AT+CHUP", bt_hfp_ag_chup_handler},
-	{"AT+CLCC", bt_hfp_ag_clcc_handler}, {"AT+BIA", bt_hfp_ag_bia_handler},
-	{"ATA", bt_hfp_ag_ata_handler},      {"AT+COPS", bt_hfp_ag_cops_handler},
-	{"AT+BCC", bt_hfp_ag_bcc_handler},   {"AT+BCS", bt_hfp_ag_bcs_handler},
-	{"ATD", bt_hfp_ag_atd_handler},      {"AT+BLDN", bt_hfp_ag_bldn_handler},
-	{"AT+CLIP", bt_hfp_ag_clip_handler},
-};
-
-static void hfp_ag_connected(struct bt_rfcomm_dlc *dlc)
+int bt_hfp_ag_terminate(struct bt_hfp_ag_call *call)
 {
-	struct bt_hfp_ag *ag = CONTAINER_OF(dlc, struct bt_hfp_ag, rfcomm_dlc);
+	int err = 0;
+	struct bt_hfp_ag *ag;
+	bt_hfp_call_state_t call_state;
 
-	bt_hfp_ag_set_state(ag, BT_HFP_CONFIG);
+	LOG_DBG("");
 
-	LOG_DBG("AG %p", ag);
-}
+	if (call == NULL) {
+		return -EINVAL;
+	}
 
-static void hfp_ag_disconnected(struct bt_rfcomm_dlc *dlc)
-{
-	struct bt_hfp_ag *ag = CONTAINER_OF(dlc, struct bt_hfp_ag, rfcomm_dlc);
-	bt_hfp_call_state_t call_state;
-	sys_snode_t *node;
-	struct bt_ag_tx *tx;
+	ag = call->ag;
 
-	k_work_cancel_delayable(&ag->tx_work);
+	if (ag == NULL) {
+		return -EINVAL;
+	}
 
 	hfp_ag_lock(ag);
-	node = sys_slist_get(&ag->tx_pending);
-	hfp_ag_unlock(ag);
-	tx = CONTAINER_OF(node, struct bt_ag_tx, node);
-	while (tx) {
-		if (tx->buf && !atomic_test_and_clear_bit(ag->flags, BT_HFP_AG_TX_ONGOING)) {
-			net_buf_unref(tx->buf);
-		}
-		tx->err = -ESHUTDOWN;
-		k_fifo_put(&ag_tx_notify, tx);
-		hfp_ag_lock(ag);
-		node = sys_slist_get(&ag->tx_pending);
+	if (ag->state != BT_HFP_CONNECTED) {
 		hfp_ag_unlock(ag);
-		tx = CONTAINER_OF(node, struct bt_ag_tx, node);
+		return -ENOTCONN;
 	}
 
-	bt_hfp_ag_set_state(ag, BT_HFP_DISCONNECTED);
-
-	hfp_ag_lock(ag);
-	call_state = ag->call_state;
+	call_state = call->call_state;
 	hfp_ag_unlock(ag);
-	if ((call_state == BT_HFP_CALL_ALERTING) || (call_state == BT_HFP_CALL_ACTIVE) ||
-	    (call_state == BT_HFP_CALL_HOLD)) {
-		bt_hfp_ag_terminate_cb(ag, NULL);
+
+	if (atomic_test_and_clear_bit(call->flags, BT_HFP_AG_CALL_INCOMING_HELD) &&
+	    atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING) &&
+	    (call_state == BT_HFP_CALL_ACTIVE)) {
+		err = hfp_ag_send_data(ag, btrh_reject_cb, call, "\r\n+BTRH:%d\r\n",
+				       BT_HFP_BTRH_REJECTED);
+		if (err) {
+			LOG_ERR("Fail to send err :(%d)", err);
+		}
+		return err;
 	}
 
-	LOG_DBG("AG %p", ag);
+	if ((call_state != BT_HFP_CALL_ACTIVE) && (call_state != BT_HFP_CALL_HOLD)) {
+		return -EINVAL;
+	}
+
+	ag_terminate_call(call);
+
+	return 0;
 }
 
-static void hfp_ag_recv(struct bt_rfcomm_dlc *dlc, struct net_buf *buf)
+int bt_hfp_ag_retrieve(struct bt_hfp_ag_call *call)
 {
-	struct bt_hfp_ag *ag = CONTAINER_OF(dlc, struct bt_hfp_ag, rfcomm_dlc);
-	uint8_t *data = buf->data;
-	uint16_t len = buf->len;
-	enum at_cme cme_err;
-	int err = -EOPNOTSUPP;
+	struct bt_hfp_ag *ag;
+	bt_hfp_call_state_t call_state;
 
-	LOG_HEXDUMP_DBG(data, len, "Received:");
+	LOG_DBG("");
 
-	for (uint32_t index = 0; index < ARRAY_SIZE(cmd_handlers); index++) {
-		if (strlen(cmd_handlers[index].cmd) > len) {
-			continue;
-		}
-		if (strncmp((char *)data, cmd_handlers[index].cmd,
-				 strlen(cmd_handlers[index].cmd)) != 0) {
-			continue;
-		}
-		if (NULL != cmd_handlers[index].handler) {
-			(void)net_buf_pull(buf, strlen(cmd_handlers[index].cmd));
-			err = cmd_handlers[index].handler(ag, buf);
-			LOG_DBG("AT commander is handled (err %d)", err);
-			break;
-		}
+	if (call == NULL) {
+		return -EINVAL;
 	}
 
-	if ((err != 0) && atomic_test_bit(ag->flags, BT_HFP_AG_CMEE_ENABLE)) {
-		cme_err = bt_hfp_ag_get_cme_err(err);
-		err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+CME ERROR:%d\r\n", (uint32_t)cme_err);
-	} else {
-		err = hfp_ag_send_data(ag, NULL, NULL, "\r\n%s\r\n", (err == 0) ? "OK" : "ERROR");
+	ag = call->ag;
+
+	if (ag == NULL) {
+		return -EINVAL;
 	}
 
-	if (err != 0) {
-		LOG_ERR("HFP AG send response err :(%d)", err);
+	hfp_ag_lock(ag);
+	if (ag->state != BT_HFP_CONNECTED) {
+		hfp_ag_unlock(ag);
+		return -ENOTCONN;
 	}
-}
 
-static void bt_hfp_ag_thread(void *p1, void *p2, void *p3)
-{
-	struct bt_ag_tx *tx;
-	bt_hfp_ag_tx_cb_t cb;
-	struct bt_hfp_ag *ag;
-	void *user_data;
-	bt_hfp_state_t state;
-	int err;
+	call_state = call->call_state;
+	hfp_ag_unlock(ag);
 
-	while (true) {
-		tx = (struct bt_ag_tx *)k_fifo_get(&ag_tx_notify, K_FOREVER);
+	if (call_state != BT_HFP_CALL_HOLD) {
+		return -EINVAL;
+	}
 
-		if (tx == NULL) {
-			continue;
-		}
+	bt_hfp_ag_set_call_state(call, BT_HFP_CALL_ACTIVE);
 
-		cb = tx->cb;
-		ag = tx->ag;
-		user_data = tx->user_data;
-		err = tx->err;
+	if (bt_ag && bt_ag->retrieve) {
+		bt_ag->retrieve(call);
+	}
 
-		bt_ag_tx_free(tx);
+	ag_notify_call_held_ind(ag, NULL);
 
-		if (err < 0) {
-			hfp_ag_lock(ag);
-			state = ag->state;
-			hfp_ag_unlock(ag);
-			if ((state != BT_HFP_DISCONNECTED) && (state != BT_HFP_DISCONNECTING)) {
-				bt_hfp_ag_set_state(ag, BT_HFP_DISCONNECTING);
-				bt_rfcomm_dlc_disconnect(&ag->rfcomm_dlc);
-			}
-		}
+	return 0;
+}
+
+int bt_hfp_ag_hold(struct bt_hfp_ag_call *call)
+{
+	struct bt_hfp_ag *ag;
+	bt_hfp_call_state_t call_state;
+
+	LOG_DBG("");
 
-		if (cb) {
-			cb(ag, user_data);
-		}
+	if (call == NULL) {
+		return -EINVAL;
 	}
-}
 
-static void hfp_ag_sent(struct bt_rfcomm_dlc *dlc, int err)
-{
-	struct bt_hfp_ag *ag = CONTAINER_OF(dlc, struct bt_hfp_ag, rfcomm_dlc);
-	sys_snode_t *node;
-	struct bt_ag_tx *tx;
+	ag = call->ag;
+
+	if (ag == NULL) {
+		return -EINVAL;
+	}
 
 	hfp_ag_lock(ag);
-	/* Clear the tx ongoing flag */
-	if (!atomic_test_and_clear_bit(ag->flags, BT_HFP_AG_TX_ONGOING)) {
-		LOG_WRN("tx ongoing flag is not set");
+	if (ag->state != BT_HFP_CONNECTED) {
 		hfp_ag_unlock(ag);
-		return;
+		return -ENOTCONN;
 	}
 
-	node = sys_slist_get(&ag->tx_pending);
+	call_state = call->call_state;
 	hfp_ag_unlock(ag);
-	if (!node) {
-		LOG_ERR("No pending tx");
-		return;
+
+	if (call_state != BT_HFP_CALL_ACTIVE) {
+		return -EINVAL;
 	}
 
-	tx = CONTAINER_OF(node, struct bt_ag_tx, node);
-	LOG_ERR("Completed pending tx %p", tx);
+	if ((call_state == BT_HFP_CALL_ACTIVE) &&
+	    (atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING_HELD))) {
+		return -EINVAL;
+	}
 
-	/* Restart the tx work */
-	k_work_reschedule(&ag->tx_work, K_NO_WAIT);
+	bt_hfp_ag_set_call_state(call, BT_HFP_CALL_HOLD);
 
-	tx->err = err;
-	k_fifo_put(&ag_tx_notify, tx);
+	if (bt_ag && bt_ag->held) {
+		bt_ag->held(call);
+	}
+
+	ag_notify_call_held_ind(ag, NULL);
+
+	return 0;
 }
 
-static void bt_ag_deferred_work_cb(struct bt_hfp_ag *ag, void *user_data)
+int bt_hfp_ag_outgoing(struct bt_hfp_ag *ag, const char *number)
 {
-	int err;
-	bt_hfp_call_state_t call_state;
-
 	LOG_DBG("");
 
+	if (ag == NULL) {
+		return -EINVAL;
+	}
+
 	hfp_ag_lock(ag);
-	call_state = ag->call_state;
+	if (ag->state != BT_HFP_CONNECTED) {
+		hfp_ag_unlock(ag);
+		return -ENOTCONN;
+	}
 	hfp_ag_unlock(ag);
 
-	switch (call_state) {
-	case BT_HFP_CALL_TERMINATE:
-		break;
-	case BT_HFP_CALL_ACTIVE:
-		break;
-	case BT_HFP_CALL_HOLD:
-		break;
-	case BT_HFP_CALL_OUTGOING:
-		__fallthrough;
-	case BT_HFP_CALL_INCOMING:
-		__fallthrough;
-	case BT_HFP_CALL_ALERTING:
-		__fallthrough;
-	default:
-		if (ag->indicator_value[BT_HFP_AG_CALL_SETUP_IND] &&
-		    ag->indicator_value[BT_HFP_AG_CALL_IND]) {
-			err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND,
-							BT_HFP_CALL_SETUP_NONE, NULL, NULL);
-			if (err) {
-				LOG_ERR("Fail to send indicator");
-				bt_hfp_ag_terminate_cb(ag, NULL);
-			} else {
-				err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 0,
-								bt_hfp_ag_terminate_cb, NULL);
-				if (err) {
-					LOG_ERR("Fail to send indicator");
-					bt_hfp_ag_terminate_cb(ag, NULL);
-				}
-			}
-		} else if (ag->indicator_value[BT_HFP_AG_CALL_SETUP_IND]) {
-			err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND,
-							BT_HFP_CALL_SETUP_NONE, bt_hfp_ag_reject_cb,
-							NULL);
-			if (err) {
-				LOG_ERR("Fail to send indicator");
-				bt_hfp_ag_terminate_cb(ag, NULL);
-			}
-		} else if (ag->indicator_value[BT_HFP_AG_CALL_IND]) {
-			err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 0,
-							bt_hfp_ag_terminate_cb, NULL);
-			if (err) {
-				LOG_ERR("Fail to send indicator");
-				bt_hfp_ag_terminate_cb(ag, NULL);
-			}
-		}
-		break;
-	}
+	return bt_hfp_ag_outgoing_call(ag, number, 0);
 }
 
-static void bt_ag_deferred_work(struct k_work *work)
+static void bt_hfp_ag_ringing_cb(struct bt_hfp_ag *ag, void *user_data)
 {
-	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
-	struct bt_hfp_ag *ag = CONTAINER_OF(dwork, struct bt_hfp_ag, deferred_work);
+	struct bt_hfp_ag_call *call = (struct bt_hfp_ag_call *)user_data;
 
-	(void)hfp_ag_next_step(ag, bt_ag_deferred_work_cb, NULL);
+	bt_hfp_ag_set_call_state(call, BT_HFP_CALL_ALERTING);
+
+	if (atomic_test_bit(ag->flags, BT_HFP_AG_INBAND_RING)) {
+		bt_hfp_ag_call_ringing_cb(call, true);
+	} else {
+		bt_hfp_ag_call_ringing_cb(call, false);
+	}
 }
 
-static void bt_ag_ringing_work_cb(struct bt_hfp_ag *ag, void *user_data)
+int bt_hfp_ag_remote_ringing(struct bt_hfp_ag_call *call)
 {
-	int err;
-	bt_hfp_call_state_t call_state;
+	int err = 0;
+	struct bt_hfp_ag *ag;
 
 	LOG_DBG("");
 
-	hfp_ag_lock(ag);
-	call_state = ag->call_state;
-	hfp_ag_unlock(ag);
-	if (call_state == BT_HFP_CALL_ALERTING) {
+	if (call == NULL) {
+		return -EINVAL;
+	}
 
-		if (!atomic_test_bit(ag->flags, BT_HFP_AG_INCOMING_CALL)) {
-			return;
-		}
+	ag = call->ag;
 
-		k_work_reschedule(&ag->ringing_work,
-				  K_SECONDS(CONFIG_BT_HFP_AG_RING_NOTIFY_INTERVAL));
+	if (ag == NULL) {
+		return -EINVAL;
+	}
 
-		err = hfp_ag_send_data(ag, NULL, NULL, "\r\nRING\r\n");
-		if (err) {
-			LOG_ERR("Fail to send RING %d", err);
-		} else {
-			if (atomic_test_bit(ag->flags, BT_HFP_AG_CLIP_ENABLE)) {
-				err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+CLIP:\"%s\",%d\r\n",
-							 ag->number, 0);
-				if (err) {
-					LOG_ERR("Fail to send CLIP %d", err);
-				}
-			}
+	hfp_ag_lock(ag);
+	if (ag->state != BT_HFP_CONNECTED) {
+		hfp_ag_unlock(ag);
+		return -ENOTCONN;
+	}
+
+	if (call->call_state != BT_HFP_CALL_OUTGOING) {
+		hfp_ag_unlock(ag);
+		return -EBUSY;
+	}
+
+	if (atomic_test_bit(ag->flags, BT_HFP_AG_INBAND_RING)) {
+		if (ag->sco_chan.sco == NULL) {
+			hfp_ag_unlock(ag);
+			return -ENOTCONN;
 		}
 	}
-}
+	hfp_ag_unlock(ag);
 
-static void bt_ag_ringing_work(struct k_work *work)
-{
-	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
-	struct bt_hfp_ag *ag = CONTAINER_OF(dwork, struct bt_hfp_ag, ringing_work);
+	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND,
+				      BT_HFP_CALL_SETUP_REMOTE_ALERTING, bt_hfp_ag_ringing_cb,
+				      call);
 
-	(void)hfp_ag_next_step(ag, bt_ag_ringing_work_cb, NULL);
+	return err;
 }
 
-int bt_hfp_ag_connect(struct bt_conn *conn, struct bt_hfp_ag **ag, uint8_t channel)
+int bt_hfp_ag_remote_reject(struct bt_hfp_ag_call *call)
 {
-	int i;
 	int err;
-
-	static struct bt_rfcomm_dlc_ops ops = {
-		.connected = hfp_ag_connected,
-		.disconnected = hfp_ag_disconnected,
-		.recv = hfp_ag_recv,
-		.sent = hfp_ag_sent,
-	};
+	struct bt_hfp_ag *ag;
 
 	LOG_DBG("");
 
-	if (ag == NULL) {
+	if (call == NULL) {
 		return -EINVAL;
 	}
 
-	*ag = NULL;
+	ag = call->ag;
 
-	if (ag_thread_id == NULL) {
+	if (ag == NULL) {
+		return -EINVAL;
+	}
 
-		k_fifo_init(&ag_tx_free);
-		k_fifo_init(&ag_tx_notify);
+	hfp_ag_lock(ag);
+	if (ag->state != BT_HFP_CONNECTED) {
+		hfp_ag_unlock(ag);
+		return -ENOTCONN;
+	}
 
-		for (i = 0; i < ARRAY_SIZE(ag_tx); i++) {
-			k_fifo_put(&ag_tx_free, &ag_tx[i]);
-		}
+	if ((call->call_state != BT_HFP_CALL_ALERTING) &&
+	    (call->call_state != BT_HFP_CALL_OUTGOING)) {
+		hfp_ag_unlock(ag);
+		return -EINVAL;
+	}
+	hfp_ag_unlock(ag);
 
-		ag_thread_id = k_thread_create(
-			&ag_thread, ag_thread_stack, K_KERNEL_STACK_SIZEOF(ag_thread_stack),
-			bt_hfp_ag_thread, NULL, NULL, NULL,
-			K_PRIO_COOP(CONFIG_BT_HFP_AG_THREAD_PRIO), 0, K_NO_WAIT);
-		if (ag_thread_id == NULL) {
-			return -ENOMEM;
-		}
-		k_thread_name_set(ag_thread_id, "HFP AG");
+	if (atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING)) {
+		return -EINVAL;
 	}
 
-	for (i = 0; i < ARRAY_SIZE(bt_hfp_ag_pool); i++) {
-		struct bt_hfp_ag *_ag = &bt_hfp_ag_pool[i];
+	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_NONE,
+				      bt_hfp_ag_reject_cb, call);
 
-		if (_ag->rfcomm_dlc.session) {
-			continue;
-		}
+	return err;
+}
+
+int bt_hfp_ag_remote_accept(struct bt_hfp_ag_call *call)
+{
+	int err;
+	struct bt_hfp_ag *ag;
 
-		(void)memset(_ag, 0, sizeof(struct bt_hfp_ag));
+	LOG_DBG("");
 
-		sys_slist_init(&_ag->tx_pending);
+	if (call == NULL) {
+		return -EINVAL;
+	}
 
-		k_sem_init(&_ag->lock, 1, 1);
+	ag = call->ag;
 
-		_ag->rfcomm_dlc.ops = &ops;
-		_ag->rfcomm_dlc.mtu = BT_HFP_MAX_MTU;
+	if (ag == NULL) {
+		return -EINVAL;
+	}
 
-		/* Set the supported features*/
-		_ag->ag_features = BT_HFP_AG_SUPPORTED_FEATURES;
+	hfp_ag_lock(ag);
+	if (ag->state != BT_HFP_CONNECTED) {
+		hfp_ag_unlock(ag);
+		return -ENOTCONN;
+	}
 
-		/* If supported codec ids cannot be notified, disable codec negotiation. */
-		if (!(bt_ag && bt_ag->codec)) {
-			_ag->ag_features &= ~BT_HFP_AG_FEATURE_CODEC_NEG;
-		}
+	if (call->call_state != BT_HFP_CALL_ALERTING) {
+		hfp_ag_unlock(ag);
+		return -EINVAL;
+	}
+	hfp_ag_unlock(ag);
 
-		_ag->hf_features = 0;
-		_ag->hf_codec_ids = 0;
+	if (atomic_test_bit(call->flags, BT_HFP_AG_CALL_INCOMING)) {
+		return -EINVAL;
+	}
 
-		_ag->acl_conn = conn;
+	if (!atomic_test_bit(call->flags, BT_HFP_AG_CALL_OUTGOING_3WAY)) {
+		err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 1, bt_hfp_ag_accept_cb, call);
+		if (err) {
+			LOG_ERR("Fail to send err :(%d)", err);
+		}
+	}
 
-		/* Set AG indicator value */
-		_ag->indicator_value[BT_HFP_AG_SERVICE_IND] = 0;
-		_ag->indicator_value[BT_HFP_AG_CALL_IND] = 0;
-		_ag->indicator_value[BT_HFP_AG_CALL_SETUP_IND] = 0;
-		_ag->indicator_value[BT_HFP_AG_CALL_HELD_IND] = 0;
-		_ag->indicator_value[BT_HFP_AG_SIGNAL_IND] = 0;
-		_ag->indicator_value[BT_HFP_AG_ROAM_IND] = 0;
-		_ag->indicator_value[BT_HFP_AG_BATTERY_IND] = 0;
+	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_NONE,
+				      bt_hfp_ag_call_setup_none_cb, call);
+	if (err) {
+		LOG_ERR("Fail to send err :(%d)", err);
+	}
 
-		/* Set AG indicator status */
-		_ag->indicator = BIT(BT_HFP_AG_SERVICE_IND) | BIT(BT_HFP_AG_CALL_IND) |
-				 BIT(BT_HFP_AG_CALL_SETUP_IND) | BIT(BT_HFP_AG_CALL_HELD_IND) |
-				 BIT(BT_HFP_AG_SIGNAL_IND) | BIT(BT_HFP_AG_ROAM_IND) |
-				 BIT(BT_HFP_AG_BATTERY_IND);
+	return err;
+}
 
-		/* Set AG operator */
-		memcpy(_ag->operator, "UNKNOWN", sizeof("UNKNOWN"));
+int bt_hfp_ag_remote_terminate(struct bt_hfp_ag_call *call)
+{
+	struct bt_hfp_ag *ag;
 
-		/* Set Codec ID*/
-		_ag->selected_codec_id = BT_HFP_AG_CODEC_CVSD;
+	LOG_DBG("");
 
-		/* Init delay work */
-		k_work_init_delayable(&_ag->deferred_work, bt_ag_deferred_work);
+	if (call == NULL) {
+		return -EINVAL;
+	}
 
-		k_work_init_delayable(&_ag->ringing_work, bt_ag_ringing_work);
+	ag = call->ag;
 
-		k_work_init_delayable(&_ag->tx_work, bt_ag_tx_work);
+	if (ag == NULL) {
+		return -EINVAL;
+	}
 
-		atomic_set_bit(_ag->flags, BT_HFP_AG_CODEC_CHANGED);
+	hfp_ag_lock(ag);
+	if (ag->state != BT_HFP_CONNECTED) {
+		hfp_ag_unlock(ag);
+		return -ENOTCONN;
+	}
 
-		*ag = _ag;
+	if ((call->call_state != BT_HFP_CALL_ACTIVE) && (call->call_state != BT_HFP_CALL_HOLD)) {
+		hfp_ag_unlock(ag);
+		return -EINVAL;
 	}
+	hfp_ag_unlock(ag);
 
-	if (*ag == NULL) {
-		return -ENOMEM;
+	ag_terminate_call(call);
+
+	return 0;
+}
+
+int bt_hfp_ag_explicit_call_transfer(struct bt_hfp_ag *ag)
+{
+#if defined(CONFIG_BT_HFP_AG_3WAY_CALL)
+	if (ag == NULL) {
+		return -EINVAL;
 	}
 
-	err = bt_rfcomm_dlc_connect(conn, &(*ag)->rfcomm_dlc, channel);
-	if (err != 0) {
-		(void)memset(*ag, 0, sizeof(struct bt_hfp_ag));
-		*ag = NULL;
-	} else {
-		bt_hfp_ag_set_state(*ag, BT_HFP_CONNECTING);
+	hfp_ag_lock(ag);
+	if (ag->state != BT_HFP_CONNECTED) {
+		hfp_ag_unlock(ag);
+		return -ENOTCONN;
 	}
+	hfp_ag_unlock(ag);
 
-	return err;
+	return chld_drop_conversation(ag);
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_AG_3WAY_CALL */
 }
 
-int bt_hfp_ag_disconnect(struct bt_hfp_ag *ag)
+int bt_hfp_ag_set_indicator(struct bt_hfp_ag *ag, enum bt_hfp_ag_indicator index, uint8_t value)
 {
 	int err;
-	bt_hfp_call_state_t call_state;
 
 	LOG_DBG("");
 
@@ -1844,70 +4446,62 @@ int bt_hfp_ag_disconnect(struct bt_hfp_ag *ag)
 	}
 
 	hfp_ag_lock(ag);
-	call_state = ag->call_state;
+	if (ag->state != BT_HFP_CONNECTED) {
+		hfp_ag_unlock(ag);
+		return -ENOTCONN;
+	}
 	hfp_ag_unlock(ag);
 
-	bt_hfp_ag_set_state(ag, BT_HFP_DISCONNECTING);
-
-	if ((call_state == BT_HFP_CALL_ACTIVE) || (call_state == BT_HFP_CALL_HOLD)) {
-		err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 0, bt_hfp_ag_terminate_cb,
-					      NULL);
-		if (err != 0) {
-			LOG_ERR("HFP AG send response err :(%d)", err);
-		}
-		return err;
-	} else if (call_state != BT_HFP_CALL_TERMINATE) {
-		err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_NONE,
-					      bt_hfp_ag_reject_cb, NULL);
-		if (err != 0) {
-			LOG_ERR("HFP AG send response err :(%d)", err);
+	switch (index) {
+	case BT_HFP_AG_SERVICE_IND:
+	case BT_HFP_AG_SIGNAL_IND:
+	case BT_HFP_AG_ROAM_IND:
+	case BT_HFP_AG_BATTERY_IND:
+		if ((ag_ind[(uint8_t)index].min > value) || (ag_ind[(uint8_t)index].max < value)) {
+			return -EINVAL;
 		}
-		return err;
+		break;
+	case BT_HFP_AG_CALL_IND:
+	case BT_HFP_AG_CALL_SETUP_IND:
+	case BT_HFP_AG_CALL_HELD_IND:
+	default:
+		return -EINVAL;
 	}
 
-	return bt_rfcomm_dlc_disconnect(&ag->rfcomm_dlc);
+	err = hfp_ag_update_indicator(ag, index, value, NULL, NULL);
+
+	return err;
 }
 
-int bt_hfp_ag_register(struct bt_hfp_ag_cb *cb)
+int bt_hfp_ag_set_operator(struct bt_hfp_ag *ag, uint8_t mode, char *name)
 {
-	if (!cb) {
+	int len;
+
+	LOG_DBG("");
+
+	if (ag == NULL) {
 		return -EINVAL;
 	}
 
-	if (bt_ag) {
-		return -EALREADY;
+	hfp_ag_lock(ag);
+	if (ag->state != BT_HFP_CONNECTED) {
+		hfp_ag_unlock(ag);
+		return -ENOTCONN;
 	}
 
-	bt_ag = cb;
+	len = strlen(name);
+	len = MIN(sizeof(ag->operator) - 1, len);
+	memcpy(ag->operator, name, len);
+	ag->operator[len] = '\0';
+	ag->mode = mode;
+	hfp_ag_unlock(ag);
 
 	return 0;
 }
 
-static void bt_hfp_ag_incoming_cb(struct bt_hfp_ag *ag, void *user_data)
-{
-	bt_hfp_ag_set_call_state(ag, BT_HFP_CALL_INCOMING);
-
-	if (bt_ag && bt_ag->incoming) {
-		bt_ag->incoming(ag, ag->number);
-	}
-
-	if (atomic_test_bit(ag->flags, BT_HFP_AG_INBAND_RING)) {
-		int err;
-
-		err = bt_hfp_ag_create_audio_connection(ag);
-		if (err) {
-			bt_hfp_ag_call_reject(ag, NULL);
-		}
-	} else {
-		bt_hfp_ag_set_call_state(ag, BT_HFP_CALL_ALERTING);
-		bt_hfp_ag_call_ringing_cb(ag, false);
-	}
-}
-
-int bt_hfp_ag_remote_incoming(struct bt_hfp_ag *ag, const char *number)
+int bt_hfp_ag_audio_connect(struct bt_hfp_ag *ag, uint8_t id)
 {
-	int err = 0;
-	size_t len;
+	int err;
 
 	LOG_DBG("");
 
@@ -1921,34 +4515,42 @@ int bt_hfp_ag_remote_incoming(struct bt_hfp_ag *ag, const char *number)
 		return -ENOTCONN;
 	}
 
-	if (ag->call_state != BT_HFP_CALL_TERMINATE) {
+	if (ag->hf_codec_ids) {
+		if (!(ag->hf_codec_ids & BIT(id))) {
+			hfp_ag_unlock(ag);
+			return -EINVAL;
+		}
+	} else {
+		if (id != BT_HFP_AG_CODEC_CVSD) {
+			hfp_ag_unlock(ag);
+			return -ENOTSUP;
+		}
+	}
+
+	if (ag->sco_chan.sco) {
+		LOG_ERR("Audio conenction has been connected");
 		hfp_ag_unlock(ag);
-		return -EBUSY;
+		return -ECONNREFUSED;
 	}
 	hfp_ag_unlock(ag);
 
-	len = strlen(number);
-	if ((len == 0) || (len > CONFIG_BT_HFP_AG_PHONE_NUMBER_MAX_LEN)) {
-		return -EINVAL;
+	if (atomic_test_bit(ag->flags, BT_HFP_AG_CODEC_CONN)) {
+		return -EBUSY;
 	}
 
 	hfp_ag_lock(ag);
-	/* Copy number to ag->number including null-character */
-	memcpy(ag->number, number, len + 1);
+	if (ag->selected_codec_id != id) {
+		atomic_set_bit(ag->flags, BT_HFP_AG_CODEC_CHANGED);
+	}
+	ag->selected_codec_id = id;
 	hfp_ag_unlock(ag);
 
-	atomic_set_bit(ag->flags, BT_HFP_AG_INCOMING_CALL);
-
-	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_INCOMING,
-					bt_hfp_ag_incoming_cb, NULL);
-	if (err != 0) {
-		atomic_clear_bit(ag->flags, BT_HFP_AG_INCOMING_CALL);
-	}
+	err = bt_hfp_ag_create_audio_connection(ag, NULL);
 
 	return err;
 }
 
-int bt_hfp_ag_reject(struct bt_hfp_ag *ag)
+int bt_hfp_ag_vgm(struct bt_hfp_ag *ag, uint8_t vgm)
 {
 	int err;
 
@@ -1958,29 +4560,32 @@ int bt_hfp_ag_reject(struct bt_hfp_ag *ag)
 		return -EINVAL;
 	}
 
+	if (vgm > BT_HFP_HF_VGM_GAIN_MAX) {
+		LOG_ERR("Invalid VGM (%d>%d)", vgm, BT_HFP_HF_VGM_GAIN_MAX);
+		return -EINVAL;
+	}
+
 	hfp_ag_lock(ag);
 	if (ag->state != BT_HFP_CONNECTED) {
 		hfp_ag_unlock(ag);
 		return -ENOTCONN;
 	}
-
-	if ((ag->call_state != BT_HFP_CALL_ALERTING) && (ag->call_state != BT_HFP_CALL_INCOMING)) {
-		hfp_ag_unlock(ag);
-		return -EINVAL;
-	}
 	hfp_ag_unlock(ag);
 
-	if (!atomic_test_bit(ag->flags, BT_HFP_AG_INCOMING_CALL)) {
-		return -EINVAL;
+	if (!HF_SUPT_FEAT(ag, BT_HFP_HF_FEATURE_VOLUME)) {
+		LOG_ERR("Remote Audio Volume Control is unsupported");
+		return -ENOTSUP;
 	}
 
-	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_NONE,
-					bt_hfp_ag_reject_cb, NULL);
+	err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+VGM=%d\r\n", vgm);
+	if (err) {
+		LOG_ERR("Fail to notify vgm err :(%d)", err);
+	}
 
 	return err;
 }
 
-int bt_hfp_ag_accept(struct bt_hfp_ag *ag)
+int bt_hfp_ag_vgs(struct bt_hfp_ag *ag, uint8_t vgs)
 {
 	int err;
 
@@ -1990,37 +4595,32 @@ int bt_hfp_ag_accept(struct bt_hfp_ag *ag)
 		return -EINVAL;
 	}
 
+	if (vgs > BT_HFP_HF_VGS_GAIN_MAX) {
+		LOG_ERR("Invalid VGM (%d>%d)", vgs, BT_HFP_HF_VGS_GAIN_MAX);
+		return -EINVAL;
+	}
+
 	hfp_ag_lock(ag);
 	if (ag->state != BT_HFP_CONNECTED) {
 		hfp_ag_unlock(ag);
 		return -ENOTCONN;
 	}
-
-	if (ag->call_state != BT_HFP_CALL_ALERTING) {
-		hfp_ag_unlock(ag);
-		return -EINVAL;
-	}
 	hfp_ag_unlock(ag);
 
-	if (!atomic_test_bit(ag->flags, BT_HFP_AG_INCOMING_CALL)) {
-		return -EINVAL;
-	}
-
-	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 1, bt_hfp_ag_accept_cb, NULL);
-	if (err != 0) {
-		LOG_ERR("Fail to send err :(%d)", err);
+	if (!HF_SUPT_FEAT(ag, BT_HFP_HF_FEATURE_VOLUME)) {
+		LOG_ERR("Remote Audio Volume Control is unsupported");
+		return -ENOTSUP;
 	}
 
-	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_NONE,
-					bt_hfp_ag_audio_connection, NULL);
-	if (err != 0) {
-		LOG_ERR("Fail to send err :(%d)", err);
+	err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+VGS=%d\r\n", vgs);
+	if (err) {
+		LOG_ERR("Fail to notify vgs err :(%d)", err);
 	}
 
 	return err;
 }
 
-int bt_hfp_ag_terminate(struct bt_hfp_ag *ag)
+int bt_hfp_ag_inband_ringtone(struct bt_hfp_ag *ag, bool inband)
 {
 	int err;
 
@@ -2035,40 +4635,24 @@ int bt_hfp_ag_terminate(struct bt_hfp_ag *ag)
 		hfp_ag_unlock(ag);
 		return -ENOTCONN;
 	}
-
-	if ((ag->call_state != BT_HFP_CALL_ACTIVE) && (ag->call_state != BT_HFP_CALL_HOLD)) {
-		hfp_ag_unlock(ag);
-		return -EINVAL;
-	}
 	hfp_ag_unlock(ag);
 
-	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 0, bt_hfp_ag_terminate_cb, NULL);
-
-	return err;
-}
-
-static void bt_hfp_ag_outgoing_cb(struct bt_hfp_ag *ag, void *user_data)
-{
-	bt_hfp_ag_set_call_state(ag, BT_HFP_CALL_OUTGOING);
-
-	if (bt_ag && bt_ag->outgoing) {
-		bt_ag->outgoing(ag, ag->number);
+	err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+BSIR=%d\r\n", inband ? 1 : 0);
+	if (err) {
+		LOG_ERR("Fail to set inband ringtone err :(%d)", err);
+		return err;
 	}
 
-	if (atomic_test_bit(ag->flags, BT_HFP_AG_INBAND_RING)) {
-		int err;
-
-		err = bt_hfp_ag_create_audio_connection(ag);
-		if (err) {
-			bt_hfp_ag_call_reject(ag, NULL);
-		}
-	}
+	atomic_set_bit_to(ag->flags, BT_HFP_AG_INBAND_RING, inband);
+	return 0;
 }
 
-int bt_hfp_ag_outgoing(struct bt_hfp_ag *ag, const char *number)
+int bt_hfp_ag_voice_recognition(struct bt_hfp_ag *ag, bool activate)
 {
-	int err = 0;
-	size_t len;
+#if defined(CONFIG_BT_HFP_AG_VOICE_RECG)
+	int err;
+	bool feature;
+	char *bvra;
 
 	LOG_DBG("");
 
@@ -2081,45 +4665,43 @@ int bt_hfp_ag_outgoing(struct bt_hfp_ag *ag, const char *number)
 		hfp_ag_unlock(ag);
 		return -ENOTCONN;
 	}
-
-	if (ag->call_state != BT_HFP_CALL_TERMINATE) {
-		hfp_ag_unlock(ag);
-		return -EBUSY;
-	}
 	hfp_ag_unlock(ag);
 
-	len = strlen(number);
-	if ((len == 0) || (len > CONFIG_BT_HFP_AG_PHONE_NUMBER_MAX_LEN)) {
-		return -EINVAL;
+	if (activate && atomic_test_bit(ag->flags, BT_HFP_AG_VRE_ACTIVATE)) {
+		LOG_WRN("VR has been activated");
+		return -ENOTSUP;
+	} else if (!activate && !atomic_test_bit(ag->flags, BT_HFP_AG_VRE_ACTIVATE)) {
+		LOG_WRN("VR is not activated");
+		return -ENOTSUP;
 	}
 
-	hfp_ag_lock(ag);
-	/* Copy number to ag->number including null-character */
-	memcpy(ag->number, number, len + 1);
-	hfp_ag_unlock(ag);
-
-	atomic_clear_bit(ag->flags, BT_HFP_AG_INCOMING_CALL);
-
-	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_OUTGOING,
-					bt_hfp_ag_outgoing_cb, NULL);
-
-	return err;
-}
-
-static void bt_hfp_ag_ringing_cb(struct bt_hfp_ag *ag, void *user_data)
-{
-	bt_hfp_ag_set_call_state(ag, BT_HFP_CALL_ALERTING);
-
-	if (atomic_test_bit(ag->flags, BT_HFP_AG_INBAND_RING)) {
-		bt_hfp_ag_call_ringing_cb(ag, true);
+	feature = BOTH_SUPT_FEAT(ag, BT_HFP_HF_FEATURE_ENH_VOICE_RECG,
+				 BT_HFP_AG_FEATURE_ENH_VOICE_RECG);
+	if (!feature) {
+		bvra = "";
 	} else {
-		bt_hfp_ag_call_ringing_cb(ag, false);
+		bvra = ",0";
+	}
+
+	err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+BVRA:%d%s\r\n", activate, bvra);
+	if (err) {
+		LOG_ERR("Fail to notify VR activation :(%d)", err);
+		return err;
 	}
+
+	atomic_set_bit_to(ag->flags, BT_HFP_AG_VRE_ACTIVATE, activate);
+	atomic_clear_bit(ag->flags, BT_HFP_AG_VRE_R2A);
+	return 0;
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_AG_VOICE_RECG */
 }
 
-int bt_hfp_ag_remote_ringing(struct bt_hfp_ag *ag)
+int bt_hfp_ag_vre_state(struct bt_hfp_ag *ag, uint8_t state)
 {
-	int err = 0;
+#if defined(CONFIG_BT_HFP_AG_ENH_VOICE_RECG)
+	int err;
+	bool feature;
 
 	LOG_DBG("");
 
@@ -2132,30 +4714,43 @@ int bt_hfp_ag_remote_ringing(struct bt_hfp_ag *ag)
 		hfp_ag_unlock(ag);
 		return -ENOTCONN;
 	}
+	hfp_ag_unlock(ag);
 
-	if (ag->call_state != BT_HFP_CALL_OUTGOING) {
-		hfp_ag_unlock(ag);
-		return -EBUSY;
+	if (!atomic_test_bit(ag->flags, BT_HFP_AG_VRE_ACTIVATE)) {
+		LOG_WRN("Voice Recognition is not activated");
+		return -EINVAL;
 	}
 
-	if (atomic_test_bit(ag->flags, BT_HFP_AG_INBAND_RING)) {
-		if (ag->sco_chan.sco == NULL) {
-			hfp_ag_unlock(ag);
-			return -ENOTCONN;
-		}
+	feature = BOTH_SUPT_FEAT(ag, BT_HFP_HF_FEATURE_ENH_VOICE_RECG,
+				 BT_HFP_AG_FEATURE_ENH_VOICE_RECG);
+	if (!feature) {
+		return -ENOTSUP;
 	}
-	hfp_ag_unlock(ag);
 
-	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND,
-					BT_HFP_CALL_SETUP_REMOTE_ALERTING, bt_hfp_ag_ringing_cb,
-					NULL);
+	if ((state & BT_HFP_BVRA_STATE_SEND_AUDIO) &&
+		!atomic_test_bit(ag->flags, BT_HFP_AG_VRE_R2A)) {
+		LOG_ERR("HFP HF is not ready to accept audio input");
+		return -EINVAL;
+	}
 
-	return err;
+	err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+BVRA:1,%d\r\n", state);
+	if (err) {
+		LOG_ERR("Fail to send state of VRE :(%d)", err);
+		return err;
+	}
+
+	return 0;
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_AG_ENH_VOICE_RECG */
 }
 
-int bt_hfp_ag_remote_reject(struct bt_hfp_ag *ag)
+int bt_hfp_ag_vre_textual_representation(struct bt_hfp_ag *ag, uint8_t state, const char *id,
+					 uint8_t type, uint8_t operation, const char *text)
 {
+#if defined(CONFIG_BT_HFP_AG_VOICE_RECG_TEXT)
 	int err;
+	bool feature;
 
 	LOG_DBG("");
 
@@ -2168,24 +4763,45 @@ int bt_hfp_ag_remote_reject(struct bt_hfp_ag *ag)
 		hfp_ag_unlock(ag);
 		return -ENOTCONN;
 	}
+	hfp_ag_unlock(ag);
 
-	if ((ag->call_state != BT_HFP_CALL_ALERTING) && (ag->call_state != BT_HFP_CALL_OUTGOING)) {
-		hfp_ag_unlock(ag);
+	if (!atomic_test_bit(ag->flags, BT_HFP_AG_VRE_ACTIVATE)) {
+		LOG_WRN("Voice Recognition is not activated");
 		return -EINVAL;
 	}
-	hfp_ag_unlock(ag);
 
-	if (atomic_test_bit(ag->flags, BT_HFP_AG_INCOMING_CALL)) {
+	feature = BOTH_SUPT_FEAT(ag, BT_HFP_HF_FEATURE_ENH_VOICE_RECG,
+				 BT_HFP_AG_FEATURE_ENH_VOICE_RECG);
+	if (!feature) {
+		return -ENOTSUP;
+	}
+
+	feature = BOTH_SUPT_FEAT(ag, BT_HFP_HF_FEATURE_VOICE_RECG_TEXT,
+				 BT_HFP_AG_FEATURE_VOICE_RECG_TEXT);
+	if (!feature) {
+		return -ENOTSUP;
+	}
+
+	if ((state & BT_HFP_BVRA_STATE_SEND_AUDIO) &&
+		!atomic_test_bit(ag->flags, BT_HFP_AG_VRE_R2A)) {
+		LOG_ERR("HFP HF is not ready to accept audio input");
 		return -EINVAL;
 	}
 
-	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_NONE,
-					bt_hfp_ag_reject_cb, NULL);
+	err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+BVRA:1,%d,%s,%d,%d,\"%s\"\r\n",
+		state, id, type, operation, text);
+	if (err) {
+		LOG_ERR("Fail to send state of VRE :(%d)", err);
+		return err;
+	}
 
-	return err;
+	return 0;
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_AG_VOICE_RECG_TEXT */
 }
 
-int bt_hfp_ag_remote_accept(struct bt_hfp_ag *ag)
+int bt_hfp_ag_signal_strength(struct bt_hfp_ag *ag, uint8_t strength)
 {
 	int err;
 
@@ -2200,32 +4816,18 @@ int bt_hfp_ag_remote_accept(struct bt_hfp_ag *ag)
 		hfp_ag_unlock(ag);
 		return -ENOTCONN;
 	}
-
-	if (ag->call_state != BT_HFP_CALL_ALERTING) {
-		hfp_ag_unlock(ag);
-		return -EINVAL;
-	}
 	hfp_ag_unlock(ag);
 
-	if (atomic_test_bit(ag->flags, BT_HFP_AG_INCOMING_CALL)) {
-		return -EINVAL;
-	}
-
-	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 1, bt_hfp_ag_accept_cb, NULL);
-	if (err != 0) {
-		LOG_ERR("Fail to send err :(%d)", err);
-	}
-
-	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_SETUP_IND, BT_HFP_CALL_SETUP_NONE,
-					bt_hfp_ag_audio_connection, NULL);
-	if (err != 0) {
-		LOG_ERR("Fail to send err :(%d)", err);
+	err = hfp_ag_update_indicator(ag, BT_HFP_AG_SIGNAL_IND, strength,
+						NULL, NULL);
+	if (err) {
+		LOG_ERR("Fail to set signal strength err :(%d)", err);
 	}
 
 	return err;
 }
 
-int bt_hfp_ag_remote_terminate(struct bt_hfp_ag *ag)
+int bt_hfp_ag_roaming_status(struct bt_hfp_ag *ag, uint8_t status)
 {
 	int err;
 
@@ -2240,19 +4842,18 @@ int bt_hfp_ag_remote_terminate(struct bt_hfp_ag *ag)
 		hfp_ag_unlock(ag);
 		return -ENOTCONN;
 	}
-
-	if ((ag->call_state != BT_HFP_CALL_ACTIVE) && (ag->call_state != BT_HFP_CALL_HOLD)) {
-		hfp_ag_unlock(ag);
-		return -EINVAL;
-	}
 	hfp_ag_unlock(ag);
 
-	err = hfp_ag_update_indicator(ag, BT_HFP_AG_CALL_IND, 0, bt_hfp_ag_terminate_cb, NULL);
+	err = hfp_ag_update_indicator(ag, BT_HFP_AG_ROAM_IND, status,
+						NULL, NULL);
+	if (err) {
+		LOG_ERR("Fail to set roaming status err :(%d)", err);
+	}
 
 	return err;
 }
 
-int bt_hfp_ag_set_indicator(struct bt_hfp_ag *ag, enum bt_hfp_ag_indicator index, uint8_t value)
+int bt_hfp_ag_battery_level(struct bt_hfp_ag *ag, uint8_t level)
 {
 	int err;
 
@@ -2269,36 +4870,18 @@ int bt_hfp_ag_set_indicator(struct bt_hfp_ag *ag, enum bt_hfp_ag_indicator index
 	}
 	hfp_ag_unlock(ag);
 
-	switch (index) {
-	case BT_HFP_AG_SERVICE_IND:
-		__fallthrough;
-	case BT_HFP_AG_SIGNAL_IND:
-		__fallthrough;
-	case BT_HFP_AG_ROAM_IND:
-		__fallthrough;
-	case BT_HFP_AG_BATTERY_IND:
-		if ((ag_ind[(uint8_t)index].min > value) || (ag_ind[(uint8_t)index].max < value)) {
-			return -EINVAL;
-		}
-		break;
-	case BT_HFP_AG_CALL_IND:
-		__fallthrough;
-	case BT_HFP_AG_CALL_SETUP_IND:
-		__fallthrough;
-	case BT_HFP_AG_CALL_HELD_IND:
-		__fallthrough;
-	default:
-		return -EINVAL;
+	err = hfp_ag_update_indicator(ag, BT_HFP_AG_BATTERY_IND, level,
+						NULL, NULL);
+	if (err) {
+		LOG_ERR("Fail to set battery level err :(%d)", err);
 	}
 
-	err = hfp_ag_update_indicator(ag, index, value, NULL, NULL);
-
 	return err;
 }
 
-int bt_hfp_ag_set_operator(struct bt_hfp_ag *ag, char *name)
+int bt_hfp_ag_service_availability(struct bt_hfp_ag *ag, bool available)
 {
-	int len;
+	int err;
 
 	LOG_DBG("");
 
@@ -2311,19 +4894,22 @@ int bt_hfp_ag_set_operator(struct bt_hfp_ag *ag, char *name)
 		hfp_ag_unlock(ag);
 		return -ENOTCONN;
 	}
-
-	len = strlen(name);
-	len = MIN(sizeof(ag->operator) - 1, len);
-	memcpy(ag->operator, name, len);
-	ag->operator[len] = '\0';
 	hfp_ag_unlock(ag);
 
-	return 0;
+	err = hfp_ag_update_indicator(ag, BT_HFP_AG_SERVICE_IND,
+		available ? 1 : 0, NULL, NULL);
+	if (err) {
+		LOG_ERR("Fail to set service availability err :(%d)", err);
+	}
+
+	return err;
 }
 
-int bt_hfp_ag_select_codec(struct bt_hfp_ag *ag, uint8_t id)
+int bt_hfp_ag_hf_indicator(struct bt_hfp_ag *ag, enum hfp_ag_hf_indicators indicator, bool enable)
 {
+#if defined(CONFIG_BT_HFP_AG_HF_INDICATORS)
 	int err;
+	uint32_t supported_indicators;
 
 	LOG_DBG("");
 
@@ -2337,23 +4923,30 @@ int bt_hfp_ag_select_codec(struct bt_hfp_ag *ag, uint8_t id)
 		return -ENOTCONN;
 	}
 
-	if (!(ag->hf_codec_ids && BIT(id))) {
-		hfp_ag_unlock(ag);
-		return -ENOTSUP;
-	}
+	supported_indicators = ag->hf_indicators_of_ag & ag->hf_indicators_of_hf;
 	hfp_ag_unlock(ag);
 
-	if (atomic_test_bit(ag->flags, BT_HFP_AG_CODEC_CONN)) {
-		return -EBUSY;
+	if (!(supported_indicators & BIT(indicator))) {
+		LOG_ERR("Unsupported indicator %d", indicator);
+		return -ENOTSUP;
 	}
 
 	hfp_ag_lock(ag);
-	ag->selected_codec_id = id;
+	if (enable) {
+		ag->hf_indicators |= BIT(indicator);
+	} else {
+		ag->hf_indicators &= ~BIT(indicator);
+	}
 	hfp_ag_unlock(ag);
 
-	atomic_set_bit(ag->flags, BT_HFP_AG_CODEC_CHANGED);
-
-	err = bt_hfp_ag_create_audio_connection(ag);
+	err = hfp_ag_send_data(ag, NULL, NULL, "\r\n+BIND:%d,%d\r\n",
+		indicator, enable ? 1  : 0);
+	if (err) {
+		LOG_ERR("Fail to update registration status of indicator:(%d)", err);
+	}
 
 	return err;
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_HF_INDICATORS */
 }
diff --git a/subsys/bluetooth/host/classic/hfp_ag_internal.h b/subsys/bluetooth/host/classic/hfp_ag_internal.h
index 94191140da0..fb17595422b 100644
--- a/subsys/bluetooth/host/classic/hfp_ag_internal.h
+++ b/subsys/bluetooth/host/classic/hfp_ag_internal.h
@@ -9,31 +9,149 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "hfp_internal.h"
+
+#if defined(CONFIG_BT_HFP_AG_EXT_ERR)
+#define BT_HFP_AG_FEATURE_EXT_ERR_ENABLE BT_HFP_AG_FEATURE_EXT_ERR
+#else
+#define BT_HFP_AG_FEATURE_EXT_ERR_ENABLE 0
+#endif /* CONFIG_BT_HFP_AG_EXT_ERR */
+
+#if defined(CONFIG_BT_HFP_AG_CODEC_NEG)
+#define BT_HFP_AG_FEATURE_CODEC_NEG_ENABLE BT_HFP_AG_FEATURE_CODEC_NEG
+#else
+#define BT_HFP_AG_FEATURE_CODEC_NEG_ENABLE 0
+#endif /* CONFIG_BT_HFP_AG_CODEC_NEG */
+
+#if defined(CONFIG_BT_HFP_AG_ECNR)
+#define BT_HFP_AG_FEATURE_ECNR_ENABLE BT_HFP_AG_FEATURE_ECNR
+#define BT_HFP_AG_SDP_FEATURE_ECNR_ENABLE BT_HFP_AG_SDP_FEATURE_ECNR
+#else
+#define BT_HFP_AG_FEATURE_ECNR_ENABLE 0
+#define BT_HFP_AG_SDP_FEATURE_ECNR_ENABLE 0
+#endif /* CONFIG_BT_HFP_AG_CODEC_NEG */
+
+#if defined(CONFIG_BT_HFP_AG_ECS)
+#define BT_HFP_AG_FEATURE_ECS_ENABLE BT_HFP_AG_FEATURE_ECS
+#else
+#define BT_HFP_AG_FEATURE_ECS_ENABLE 0
+#endif /* CONFIG_BT_HFP_AG_ECS*/
+
+#if defined(CONFIG_BT_HFP_AG_3WAY_CALL)
+#define BT_HFP_AG_FEATURE_3WAY_CALL_ENABLE BT_HFP_AG_FEATURE_3WAY_CALL
+#define BT_HFP_AG_SDP_FEATURE_3WAY_CALL_ENABLE BT_HFP_AG_SDP_FEATURE_3WAY_CALL
+#else
+#define BT_HFP_AG_FEATURE_3WAY_CALL_ENABLE 0
+#define BT_HFP_AG_SDP_FEATURE_3WAY_CALL_ENABLE 0
+#endif /* CONFIG_BT_HFP_AG_3WAY_CALL */
+
+#if defined(CONFIG_BT_HFP_AG_ECC)
+#define BT_HFP_AG_FEATURE_ECC_ENABLE BT_HFP_AG_FEATURE_ECC
+#else
+#define BT_HFP_AG_FEATURE_ECC_ENABLE 0
+#endif /* CONFIG_BT_HFP_AG_ECC */
+
+#if defined(CONFIG_BT_HFP_AG_VOICE_RECG)
+#define BT_HFP_AG_FEATURE_VOICE_RECG_ENABLE BT_HFP_AG_FEATURE_VOICE_RECG
+#define BT_HFP_AG_SDP_FEATURE_VOICE_RECG_ENABLE BT_HFP_AG_SDP_FEATURE_VOICE_RECG
+#else
+#define BT_HFP_AG_FEATURE_VOICE_RECG_ENABLE 0
+#define BT_HFP_AG_SDP_FEATURE_VOICE_RECG_ENABLE 0
+#endif /* CONFIG_BT_HFP_AG_VOICE_RECG */
+
+#if defined(CONFIG_BT_HFP_AG_ENH_VOICE_RECG)
+#define BT_HFP_AG_FEATURE_ENH_VOICE_RECG_ENABLE BT_HFP_AG_FEATURE_ENH_VOICE_RECG
+#define BT_HFP_AG_SDP_FEATURE_ENH_VOICE_RECG_ENABLE BT_HFP_AG_SDP_FEATURE_ENH_VOICE_RECG
+#else
+#define BT_HFP_AG_FEATURE_ENH_VOICE_RECG_ENABLE 0
+#define BT_HFP_AG_SDP_FEATURE_ENH_VOICE_RECG_ENABLE 0
+#endif /* CONFIG_BT_HFP_AG_ENH_VOICE_RECG */
+
+#if defined(CONFIG_BT_HFP_AG_VOICE_RECG_TEXT)
+#define BT_HFP_AG_FEATURE_VOICE_RECG_TEXT_ENABLE BT_HFP_AG_FEATURE_VOICE_RECG_TEXT
+#define BT_HFP_AG_SDP_FEATURE_VOICE_RECG_TEXT_ENABLE BT_HFP_AG_SDP_FEATURE_VOICE_RECG_TEXT
+#else
+#define BT_HFP_AG_FEATURE_VOICE_RECG_TEXT_ENABLE 0
+#define BT_HFP_AG_SDP_FEATURE_VOICE_RECG_TEXT_ENABLE 0
+#endif /* CONFIG_BT_HFP_AG_VOICE_RECG_TEXT */
+
+#if defined(CONFIG_BT_HFP_AG_VOICE_TAG)
+#define BT_HFP_AG_FEATURE_VOICE_TAG_ENABLE BT_HFP_AG_FEATURE_VOICE_TAG
+#define BT_HFP_AG_SDP_FEATURE_VOICE_TAG_ENABLE BT_HFP_AG_SDP_FEATURE_VOICE_TAG
+#else
+#define BT_HFP_AG_FEATURE_VOICE_TAG_ENABLE 0
+#define BT_HFP_AG_SDP_FEATURE_VOICE_TAG_ENABLE 0
+#endif /* CONFIG_BT_HFP_AG_VOICE_TAG */
+
+#if defined(CONFIG_BT_HFP_AG_HF_INDICATORS)
+#define BT_HFP_AG_FEATURE_HF_IND_ENABLE BT_HFP_AG_FEATURE_HF_IND
+#else
+#define BT_HFP_AG_FEATURE_HF_IND_ENABLE 0
+#endif /* CONFIG_BT_HFP_HF_HF_INDICATORS */
+
+#if defined(CONFIG_BT_HFP_AG_REJECT_CALL)
+#define BT_HFP_AG_FEATURE_REJECT_CALL_ENABLE BT_HFP_AG_FEATURE_REJECT_CALL
+#else
+#define BT_HFP_AG_FEATURE_REJECT_CALL_ENABLE 0
+#endif /* CONFIG_BT_HFP_AG_REJECT_CALL */
+
 /* HFP AG Supported features */
-#define BT_HFP_AG_SUPPORTED_FEATURES (BT_HFP_AG_FEATURE_INBAND_RINGTONE | BT_HFP_AG_FEATURE_EXT_ERR)
+#define BT_HFP_AG_SUPPORTED_FEATURES (\
+	BT_HFP_AG_FEATURE_3WAY_CALL_ENABLE | \
+	BT_HFP_AG_FEATURE_INBAND_RINGTONE | \
+	BT_HFP_AG_FEATURE_EXT_ERR_ENABLE | \
+	BT_HFP_AG_FEATURE_CODEC_NEG_ENABLE | \
+	BT_HFP_AG_FEATURE_ECNR_ENABLE | \
+	BT_HFP_AG_FEATURE_ECS_ENABLE | \
+	BT_HFP_AG_FEATURE_ECC_ENABLE | \
+	BT_HFP_AG_FEATURE_VOICE_RECG_ENABLE | \
+	BT_HFP_AG_FEATURE_ENH_VOICE_RECG_ENABLE | \
+	BT_HFP_AG_FEATURE_VOICE_RECG_TEXT_ENABLE | \
+	BT_HFP_AG_FEATURE_VOICE_TAG_ENABLE | \
+	BT_HFP_AG_FEATURE_HF_IND_ENABLE | \
+	BT_HFP_AG_FEATURE_REJECT_CALL_ENABLE)
+
+/* HFP AG Supported features in SDP */
+#define BT_HFP_AG_SDP_SUPPORTED_FEATURES (\
+	BT_HFP_AG_SDP_FEATURE_3WAY_CALL_ENABLE | \
+	BT_HFP_AG_SDP_FEATURE_INBAND_RINGTONE | \
+	BT_HFP_AG_SDP_FEATURE_ECNR_ENABLE | \
+	BT_HFP_AG_SDP_FEATURE_VOICE_RECG_ENABLE | \
+	BT_HFP_AG_SDP_FEATURE_ENH_VOICE_RECG_ENABLE | \
+	BT_HFP_AG_SDP_FEATURE_VOICE_RECG_TEXT_ENABLE | \
+	BT_HFP_AG_SDP_FEATURE_VOICE_TAG_ENABLE)
 
 /* bt_hfp_ag flags: the flags defined here represent HFP AG parameters */
 enum {
 	BT_HFP_AG_CMEE_ENABLE,   /* Extended Audio Gateway Error Result Code */
 	BT_HFP_AG_CMER_ENABLE,   /* Indicator Events Reporting */
 	BT_HFP_AG_CLIP_ENABLE,   /* Calling Line Identification notification */
+	BT_HFP_AG_CCWA_ENABLE,   /* Call Waiting notification */
 	BT_HFP_AG_INBAND_RING,   /* In-band ring */
 	BT_HFP_AG_COPS_SET,      /* Query Operator selection */
-	BT_HFP_AG_INCOMING_CALL, /* Incoming call */
+	BT_HFP_AG_AUDIO_CONN,    /* Audio connection */
 	BT_HFP_AG_CODEC_CONN,    /* Codec connection is ongoing */
 	BT_HFP_AG_CODEC_CHANGED, /* Codec Id Changed */
 	BT_HFP_AG_TX_ONGOING,    /* TX is ongoing */
 	BT_HFP_AG_CREATING_SCO,  /* SCO is creating */
+	BT_HFP_AG_VRE_ACTIVATE,  /* VRE is activated */
+	BT_HFP_AG_VRE_R2A,       /* HF is ready to accept audio */
 
 	/* Total number of flags - must be at the end of the enum */
 	BT_HFP_AG_NUM_FLAGS,
 };
 
-/* HFP HF Indicators */
+/* bt_hfp_ag_call flags: the flags defined here represent HFP AG parameters */
 enum {
-	HFP_HF_ENHANCED_SAFETY_IND = 1, /* Enhanced Safety */
-	HFP_HF_BATTERY_LEVEL_IND = 2,   /* Remaining level of Battery */
-	HFP_HF_IND_MAX
+	BT_HFP_AG_CALL_IN_USING,      /* Object is in using */
+	BT_HFP_AG_CALL_INCOMING,      /* Incoming call */
+	BT_HFP_AG_CALL_INCOMING_HELD, /* Incoming call held */
+	BT_HFP_AG_CALL_OPEN_SCO,      /* Open SCO */
+	BT_HFP_AG_CALL_OUTGOING_3WAY, /* Outgoing 3 way call */
+	BT_HFP_AG_CALL_INCOMING_3WAY, /* Incoming 3 way call */
+
+	/* Total number of flags - must be at the end of the enum */
+	BT_HFP_AG_CALL_NUM_FLAGS,
 };
 
 typedef enum __packed {
@@ -51,21 +169,38 @@ typedef enum __packed {
 
 typedef enum __packed {
 	/** Call terminate */
-	BT_HFP_CALL_TERMINATE,
+	BT_HFP_CALL_TERMINATE = 1,
 	/** Call outgoing */
-	BT_HFP_CALL_OUTGOING,
+	BT_HFP_CALL_OUTGOING = 2,
 	/** Call incoming */
-	BT_HFP_CALL_INCOMING,
+	BT_HFP_CALL_INCOMING = 4,
 	/** Call alerting */
-	BT_HFP_CALL_ALERTING,
+	BT_HFP_CALL_ALERTING = 8,
 	/** Call active */
-	BT_HFP_CALL_ACTIVE,
+	BT_HFP_CALL_ACTIVE = 16,
 	/** Call hold */
-	BT_HFP_CALL_HOLD,
+	BT_HFP_CALL_HOLD = 32,
 } bt_hfp_call_state_t;
 
 #define AT_COPS_OPERATOR_MAX_LEN 16
 
+struct bt_hfp_ag_call {
+	struct bt_hfp_ag *ag;
+
+	char number[CONFIG_BT_HFP_AG_PHONE_NUMBER_MAX_LEN + 1];
+	uint8_t type;
+
+	ATOMIC_DEFINE(flags, BT_HFP_AG_CALL_NUM_FLAGS);
+
+	/* HFP Call state */
+	bt_hfp_call_state_t call_state;
+
+	/* Calling Line Identification notification */
+	struct k_work_delayable ringing_work;
+
+	struct k_work_delayable deferred_work;
+};
+
 struct bt_hfp_ag {
 	struct bt_rfcomm_dlc rfcomm_dlc;
 	char buffer[HF_MAX_BUF_LEN];
@@ -84,14 +219,6 @@ struct bt_hfp_ag {
 	/* HFP Connection state */
 	bt_hfp_state_t state;
 
-	/* HFP Call state */
-	bt_hfp_call_state_t call_state;
-
-	/* Delayed work deferred tasks:
-	 * - call status cleanup.
-	 */
-	struct k_work_delayable deferred_work;
-
 	/* AG Indicators */
 	uint8_t indicator_value[BT_HFP_AG_IND_MAX];
 	uint32_t indicator;
@@ -99,42 +226,27 @@ struct bt_hfp_ag {
 	/* HF Indicators */
 	uint32_t hf_indicators_of_ag;
 	uint32_t hf_indicators_of_hf;
-	uint8_t hf_indicator_value[HFP_HF_IND_MAX];
+	uint32_t hf_indicators;
 
 	/* operator */
+	uint8_t mode;
 	char operator[AT_COPS_OPERATOR_MAX_LEN + 1];
 
+	/* calls */
+	struct bt_hfp_ag_call calls[CONFIG_BT_HFP_AG_MAX_CALLS];
+
+	/* last dialing number and type */
+	char last_number[CONFIG_BT_HFP_AG_PHONE_NUMBER_MAX_LEN + 1];
+	uint8_t type;
+
 	/* SCO Connection Object */
 	struct bt_sco_chan sco_chan;
 	/* HFP TX pending */
 	sys_slist_t tx_pending;
 
-	/* Dial number or incoming number */
-	char number[CONFIG_BT_HFP_AG_PHONE_NUMBER_MAX_LEN + 1];
-
-	/* Calling Line Identification notification */
-	struct k_work_delayable ringing_work;
-
 	/* Critical locker */
 	struct k_sem lock;
 
 	/* TX work */
 	struct k_work_delayable tx_work;
 };
-
-/* Active */
-#define HFP_AG_CLCC_STATUS_ACTIVE         0
-/* Held */
-#define HFP_AG_CLCC_STATUS_HELD           1
-/* Dialing (outgoing calls only) */
-#define HFP_AG_CLCC_STATUS_DIALING        2
-/* Alerting (outgoing calls only) */
-#define HFP_AG_CLCC_STATUS_ALERTING       3
-/* Incoming (incoming calls only) */
-#define HFP_AG_CLCC_STATUS_INCOMING       4
-/* Waiting (incoming calls only) */
-#define HFP_AG_CLCC_STATUS_WAITING        5
-/* Call held by Response and Hold */
-#define HFP_AG_CLCC_STATUS_CALL_HELD_HOLD 6
-/* Invalid status */
-#define HFP_AG_CLCC_STATUS_INVALID        0xFFU
diff --git a/subsys/bluetooth/host/classic/hfp_hf.c b/subsys/bluetooth/host/classic/hfp_hf.c
index 4bde73e9399..ceeabf0ead9 100644
--- a/subsys/bluetooth/host/classic/hfp_hf.c
+++ b/subsys/bluetooth/host/classic/hfp_hf.c
@@ -26,7 +26,7 @@
 #include "rfcomm_internal.h"
 #include "at.h"
 #include "sco_internal.h"
-#include "hfp_internal.h"
+#include "hfp_hf_internal.h"
 
 #define LOG_LEVEL CONFIG_BT_HFP_HF_LOG_LEVEL
 #include <zephyr/logging/log.h>
@@ -42,6 +42,29 @@ NET_BUF_POOL_FIXED_DEFINE(hf_pool, CONFIG_BT_MAX_CONN + 1,
 
 static struct bt_hfp_hf bt_hfp_hf_pool[CONFIG_BT_MAX_CONN];
 
+#define HF_ENHANCED_CALL_STATUS_TIMEOUT 50 /* ms */
+
+struct at_callback_set {
+	void *resp;
+	void *finish;
+} __packed;
+
+static inline void make_at_callback_set(void *storage, void *resp, void *finish)
+{
+	((struct at_callback_set *)storage)->resp = resp;
+	((struct at_callback_set *)storage)->finish = finish;
+}
+
+static inline void *at_callback_set_resp(void *storage)
+{
+	return ((struct at_callback_set *)storage)->resp;
+}
+
+static inline void *at_callback_set_finish(void *storage)
+{
+	return ((struct at_callback_set *)storage)->finish;
+}
+
 /* The order should follow the enum hfp_hf_ag_indicators */
 static const struct {
 	char *name;
@@ -119,7 +142,7 @@ static struct bt_sdp_attribute hfp_attrs[] = {
 	/* The values of the “SupportedFeatures” bitmap shall be the same as the
 	 * values of the Bits 0 to 4 of the AT-command AT+BRSF (see Section 5.3).
 	 */
-	BT_SDP_SUPPORTED_FEATURES(BT_HFP_HF_SUPPORTED_FEATURES & 0x1f),
+	BT_SDP_SUPPORTED_FEATURES(BT_HFP_HF_SDP_SUPPORTED_FEATURES),
 };
 
 static struct bt_sdp_record hfp_rec = BT_SDP_RECORD(hfp_attrs);
@@ -136,6 +159,89 @@ void hf_slc_error(struct at_client *hf_at)
 	}
 }
 
+static void hfp_hf_send_failed(struct bt_hfp_hf *hf)
+{
+	int err;
+
+	LOG_ERR("SLC error: disconnecting");
+
+	err = bt_rfcomm_dlc_disconnect(&hf->rfcomm_dlc);
+	if (err) {
+		LOG_ERR("Fail to disconnect: %d", err);
+	}
+}
+
+static void hfp_hf_send_data(struct bt_hfp_hf *hf);
+
+static int hfp_hf_common_finish(struct at_client *at, enum at_result result,
+			  enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(at, struct bt_hfp_hf, at);
+	int err = 0;
+
+	if (result != AT_RESULT_OK) {
+		LOG_WRN("Fail to send AT command (result %d, cme err %d) on %p",
+		    result, cme_err, hf);
+	}
+
+	if (hf->backup_finish) {
+		err = hf->backup_finish(at, result, cme_err);
+		hf->backup_finish = NULL;
+	}
+
+	if (atomic_test_and_clear_bit(hf->flags, BT_HFP_HF_FLAG_TX_ONGOING)) {
+		LOG_DBG("TX is done on %p", hf);
+	} else {
+		LOG_WRN("Tx is not ongoing on %p", hf);
+	}
+
+	hfp_hf_send_data(hf);
+	return err;
+}
+
+static void hfp_hf_send_data(struct bt_hfp_hf *hf)
+{
+	struct net_buf *buf;
+	at_resp_cb_t resp;
+	at_finish_cb_t finish;
+	int err;
+
+	if (atomic_test_bit(hf->flags, BT_HFP_HF_FLAG_RX_ONGOING)) {
+		return;
+	}
+
+	if (atomic_test_and_set_bit(hf->flags, BT_HFP_HF_FLAG_TX_ONGOING)) {
+		return;
+	}
+
+	buf = k_fifo_get(&hf->tx_pending, K_NO_WAIT);
+	if (!buf) {
+		atomic_clear_bit(hf->flags, BT_HFP_HF_FLAG_TX_ONGOING);
+		return;
+	}
+
+	resp = (at_resp_cb_t)at_callback_set_resp(buf->user_data);
+	finish = (at_finish_cb_t)at_callback_set_finish(buf->user_data);
+
+	/*
+	 * Backup the `finish` callback.
+	 * Provide a default finish callback to drive the next sending.
+	 */
+	hf->backup_finish = finish;
+	finish = hfp_hf_common_finish;
+
+	make_at_callback_set(buf->user_data, NULL, NULL);
+	at_register(&hf->at, resp, finish);
+
+	err = bt_rfcomm_dlc_send(&hf->rfcomm_dlc, buf);
+	if (err < 0) {
+		LOG_ERR("Rfcomm send error :(%d)", err);
+		atomic_clear_bit(hf->flags, BT_HFP_HF_FLAG_TX_ONGOING);
+		net_buf_unref(buf);
+		hfp_hf_send_failed(hf);
+	}
+}
+
 int hfp_hf_send_cmd(struct bt_hfp_hf *hf, at_resp_cb_t resp,
 		    at_finish_cb_t finish, const char *format, ...)
 {
@@ -143,15 +249,14 @@ int hfp_hf_send_cmd(struct bt_hfp_hf *hf, at_resp_cb_t resp,
 	va_list vargs;
 	int ret;
 
-	/* register the callbacks */
-	at_register(&hf->at, resp, finish);
-
 	buf = bt_rfcomm_create_pdu(&hf_pool);
 	if (!buf) {
 		LOG_ERR("No Buffers!");
 		return -ENOMEM;
 	}
 
+	make_at_callback_set(buf->user_data, resp, finish);
+
 	va_start(vargs, format);
 	ret = vsnprintk(buf->data, (net_buf_tailroom(buf) - 1), format, vargs);
 	if (ret < 0) {
@@ -165,11 +270,8 @@ int hfp_hf_send_cmd(struct bt_hfp_hf *hf, at_resp_cb_t resp,
 
 	LOG_DBG("HF %p, DLC %p sending buf %p", hf, &hf->rfcomm_dlc, buf);
 
-	ret = bt_rfcomm_dlc_send(&hf->rfcomm_dlc, buf);
-	if (ret < 0) {
-		LOG_ERR("Rfcomm send error :(%d)", ret);
-		return ret;
-	}
+	k_fifo_put(&hf->tx_pending, buf);
+	hfp_hf_send_data(hf);
 
 	return 0;
 }
@@ -295,390 +397,3513 @@ int cind_resp(struct at_client *hf_at, struct net_buf *buf)
 	return 0;
 }
 
-void ag_indicator_handle_values(struct at_client *hf_at, uint32_t index,
-				uint32_t value)
+static void free_call(struct bt_hfp_hf_call *call)
 {
-	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
-	struct bt_conn *conn = hf->acl;
-
-	LOG_DBG("Index :%u, Value :%u", index, value);
+	memset(call, 0, sizeof(*call));
+}
 
-	if (index >= ARRAY_SIZE(ag_ind)) {
-		LOG_ERR("Max only %zu indicators are supported", ARRAY_SIZE(ag_ind));
-		return;
-	}
+#if defined(CONFIG_BT_HFP_HF_ECS)
+static struct bt_hfp_hf_call *get_call_with_index(struct bt_hfp_hf *hf, uint8_t index)
+{
+	struct bt_hfp_hf_call *call;
 
-	if (value > ag_ind[hf->ind_table[index]].max ||
-	    value < ag_ind[hf->ind_table[index]].min) {
-		LOG_ERR("Indicators out of range - value: %u", value);
-		return;
-	}
+	for (size_t i = 0; i < ARRAY_SIZE(hf->calls); i++) {
+		call = &hf->calls[i];
 
-	switch (hf->ind_table[index]) {
-	case HF_SERVICE_IND:
-		if (bt_hf->service) {
-			bt_hf->service(conn, value);
-		}
-		break;
-	case HF_CALL_IND:
-		if (bt_hf->call) {
-			bt_hf->call(conn, value);
-		}
-		break;
-	case HF_CALL_SETUP_IND:
-		if (bt_hf->call_setup) {
-			bt_hf->call_setup(conn, value);
-		}
-		break;
-	case HF_CALL_HELD_IND:
-		if (bt_hf->call_held) {
-			bt_hf->call_held(conn, value);
-		}
-		break;
-	case HF_SINGNAL_IND:
-		if (bt_hf->signal) {
-			bt_hf->signal(conn, value);
-		}
-		break;
-	case HF_ROAM_IND:
-		if (bt_hf->roam) {
-			bt_hf->roam(conn, value);
+		if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_IN_USING)) {
+			continue;
 		}
-		break;
-	case HF_BATTERY_IND:
-		if (bt_hf->battery) {
-			bt_hf->battery(conn, value);
+
+		if (call->index == index) {
+			return call;
 		}
-		break;
-	default:
-		LOG_ERR("Unknown AG indicator");
-		break;
 	}
+
+	return NULL;
 }
 
-int cind_status_handle(struct at_client *hf_at)
+static struct bt_hfp_hf_call *get_call_without_index(struct bt_hfp_hf *hf)
 {
-	uint32_t index = 0U;
+	struct bt_hfp_hf_call *call;
 
-	while (at_has_next_list(hf_at)) {
-		uint32_t value;
-		int ret;
+	for (size_t index = 0; index < ARRAY_SIZE(hf->calls); index++) {
+		call = &hf->calls[index];
 
-		ret = at_get_number(hf_at, &value);
-		if (ret < 0) {
-			LOG_ERR("could not get the value");
-			return ret;
+		if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_IN_USING)) {
+			continue;
 		}
 
-		ag_indicator_handle_values(hf_at, index, value);
-
-		index++;
+		if (!call->index) {
+			return call;
+		}
 	}
 
-	return 0;
+	return NULL;
 }
+#endif /* CONFIG_BT_HFP_HF_ECS */
 
-int cind_status_resp(struct at_client *hf_at, struct net_buf *buf)
+static void hf_reject_call(struct bt_hfp_hf_call *call)
 {
-	int err;
-
-	err = at_parse_cmd_input(hf_at, buf, "CIND", cind_status_handle,
-				 AT_CMD_TYPE_NORMAL);
-	if (err < 0) {
-		LOG_ERR("Error parsing CMD input");
-		hf_slc_error(hf_at);
+	if (bt_hf->reject) {
+		bt_hf->reject(call);
 	}
+	free_call(call);
+}
 
-	return 0;
+static void hf_terminate_call(struct bt_hfp_hf_call *call)
+{
+	if (bt_hf->terminate) {
+		bt_hf->terminate(call);
+	}
+	free_call(call);
 }
 
-int ciev_handle(struct at_client *hf_at)
+static void clear_call_without_clcc(struct bt_hfp_hf *hf)
 {
-	uint32_t index, value;
-	int ret;
+	struct bt_hfp_hf_call *call;
 
-	ret = at_get_number(hf_at, &index);
-	if (ret < 0) {
-		LOG_ERR("could not get the Index");
-		return ret;
-	}
-	/* The first element of the list shall have 1 */
-	if (!index) {
-		LOG_ERR("Invalid index value '0'");
-		return 0;
-	}
+	for (size_t index = 0; index < ARRAY_SIZE(hf->calls); index++) {
+		call = &hf->calls[index];
 
-	ret = at_get_number(hf_at, &value);
-	if (ret < 0) {
-		LOG_ERR("could not get the value");
-		return ret;
-	}
+		if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_IN_USING)) {
+			continue;
+		}
 
-	ag_indicator_handle_values(hf_at, (index - 1), value);
+		if (atomic_test_and_clear_bit(call->flags, BT_HFP_HF_CALL_CLCC)) {
+			continue;
+		}
 
-	return 0;
+		switch (atomic_get(call->state)) {
+		case BT_HFP_HF_CALL_STATE_TERMINATE:
+			break;
+		case BT_HFP_HF_CALL_STATE_OUTGOING:
+		case BT_HFP_HF_CALL_STATE_INCOMING:
+		case BT_HFP_HF_CALL_STATE_ALERTING:
+		case BT_HFP_HF_CALL_STATE_WAITING:
+			hf_reject_call(call);
+			break;
+		case BT_HFP_HF_CALL_STATE_ACTIVE:
+		case BT_HFP_HF_CALL_STATE_HELD:
+			hf_terminate_call(call);
+			break;
+		default:
+			free_call(call);
+			break;
+		}
+	}
 }
 
-int ring_handle(struct at_client *hf_at)
+static int clcc_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
 {
 	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
-	struct bt_conn *conn = hf->acl;
 
-	if (bt_hf->ring_indication) {
-		bt_hf->ring_indication(conn);
+	LOG_DBG("AT+CLCC (result %d) on %p", result, hf);
+
+	if (result == AT_RESULT_OK) {
+		clear_call_without_clcc(hf);
 	}
 
+	atomic_clear_bit(hf->flags, BT_HFP_HF_FLAG_CLCC_PENDING);
+
 	return 0;
 }
 
-static const struct unsolicited {
-	const char *cmd;
-	enum at_cmd_type type;
-	int (*func)(struct at_client *hf_at);
-} handlers[] = {
-	{ "CIEV", AT_CMD_TYPE_UNSOLICITED, ciev_handle },
-	{ "RING", AT_CMD_TYPE_OTHER, ring_handle }
-};
-
-static const struct unsolicited *hfp_hf_unsol_lookup(struct at_client *hf_at)
+static void clear_call_clcc_state(struct bt_hfp_hf *hf)
 {
-	int i;
+	struct bt_hfp_hf_call *call;
 
-	for (i = 0; i < ARRAY_SIZE(handlers); i++) {
-		if (!strncmp(hf_at->buf, handlers[i].cmd,
-			     strlen(handlers[i].cmd))) {
-			return &handlers[i];
+	for (size_t index = 0; index < ARRAY_SIZE(hf->calls); index++) {
+		call = &hf->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_IN_USING)) {
+			continue;
 		}
-	}
 
-	return NULL;
+		atomic_clear_bit(call->flags, BT_HFP_HF_CALL_CLCC);
+	}
 }
 
-int unsolicited_cb(struct at_client *hf_at, struct net_buf *buf)
+static void hf_query_current_calls(struct bt_hfp_hf *hf)
 {
-	const struct unsolicited *handler;
+	int err;
 
-	handler = hfp_hf_unsol_lookup(hf_at);
-	if (!handler) {
-		LOG_ERR("Unhandled unsolicited response");
-		return -ENOMSG;
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return;
 	}
 
-	if (!at_parse_cmd_input(hf_at, buf, handler->cmd, handler->func,
-				handler->type)) {
-		return 0;
+	if (!atomic_test_bit(hf->flags, BT_HFP_HF_FLAG_CONNECTED)) {
+		return;
 	}
 
-	return -ENOMSG;
+	if (!(hf->ag_features & BT_HFP_AG_FEATURE_ECS)) {
+		return;
+	}
+
+	if (!(hf->hf_features & BT_HFP_HF_FEATURE_ECS)) {
+		return;
+	}
+
+	if (atomic_test_bit(hf->flags, BT_HFP_HF_FLAG_CLCC_PENDING)) {
+		k_work_reschedule(&hf->deferred_work, K_MSEC(HF_ENHANCED_CALL_STATUS_TIMEOUT));
+		return;
+	}
+
+	clear_call_clcc_state(hf);
+
+	err = hfp_hf_send_cmd(hf, NULL, clcc_finish, "AT+CLCC");
+	if (err < 0) {
+		LOG_ERR("Fail to query current calls on %p", hf);
+	}
 }
 
-int cmd_complete(struct at_client *hf_at, enum at_result result,
-	       enum at_cme cme_err)
+static void hf_call_state_update(struct bt_hfp_hf_call *call, int state)
 {
-	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
-	struct bt_conn *conn = hf->acl;
-	struct bt_hfp_hf_cmd_complete cmd = { 0 };
+	int old_state;
 
-	LOG_DBG("");
+	old_state = atomic_get(call->state);
+	atomic_set(call->state, state);
+
+	LOG_DBG("Call %p state update %d->%d", call, old_state, state);
 
-	switch (result) {
-	case AT_RESULT_OK:
-		cmd.type = HFP_HF_CMD_OK;
+	switch (state) {
+	case BT_HFP_HF_CALL_STATE_TERMINATE:
+		free_call(call);
 		break;
-	case AT_RESULT_ERROR:
-		cmd.type = HFP_HF_CMD_ERROR;
+	case BT_HFP_HF_CALL_STATE_OUTGOING:
 		break;
-	case AT_RESULT_CME_ERROR:
-		cmd.type = HFP_HF_CMD_CME_ERROR;
-		cmd.cme = cme_err;
+	case BT_HFP_HF_CALL_STATE_INCOMING:
 		break;
-	default:
-		LOG_ERR("Unknown error code");
-		cmd.type = HFP_HF_CMD_UNKNOWN_ERROR;
+	case BT_HFP_HF_CALL_STATE_ALERTING:
+		k_work_reschedule(&call->hf->deferred_work,
+				  K_MSEC(HF_ENHANCED_CALL_STATUS_TIMEOUT));
+		break;
+	case BT_HFP_HF_CALL_STATE_WAITING:
+		k_work_reschedule(&call->hf->deferred_work,
+				  K_MSEC(HF_ENHANCED_CALL_STATUS_TIMEOUT));
+		break;
+	case BT_HFP_HF_CALL_STATE_ACTIVE:
+		break;
+	case BT_HFP_HF_CALL_STATE_HELD:
 		break;
 	}
-
-	if (bt_hf->cmd_complete_cb) {
-		bt_hf->cmd_complete_cb(conn, &cmd);
-	}
-
-	return 0;
 }
 
-int cmee_finish(struct at_client *hf_at, enum at_result result,
-		enum at_cme cme_err)
+#if defined(CONFIG_BT_HFP_HF_ECS)
+static void call_state_update(struct bt_hfp_hf_call *call, uint32_t status)
 {
-	if (result != AT_RESULT_OK) {
-		LOG_ERR("SLC Connection ERROR in response");
-		return -EINVAL;
+	switch (status) {
+	case BT_HFP_CLCC_STATUS_ACTIVE:
+		if ((atomic_get(call->state) != BT_HFP_HF_CALL_STATE_ACTIVE) ||
+		    ((atomic_get(call->state) == BT_HFP_HF_CALL_STATE_ACTIVE) &&
+		    atomic_test_and_clear_bit(call->flags, BT_HFP_HF_CALL_INCOMING_HELD))) {
+			atomic_val_t state;
+
+			state = atomic_get(call->state);
+			hf_call_state_update(call, BT_HFP_HF_CALL_STATE_ACTIVE);
+			if (state == BT_HFP_HF_CALL_STATE_HELD) {
+				if (bt_hf->retrieve) {
+					bt_hf->retrieve(call);
+				}
+			} else {
+				if (bt_hf->accept) {
+					bt_hf->accept(call);
+				}
+			}
+		}
+		break;
+	case BT_HFP_CLCC_STATUS_HELD:
+		if ((atomic_get(call->state) == BT_HFP_HF_CALL_STATE_ACTIVE) &&
+		    !atomic_test_and_clear_bit(call->flags, BT_HFP_HF_CALL_INCOMING_HELD)) {
+			hf_call_state_update(call, BT_HFP_HF_CALL_STATE_HELD);
+			if (bt_hf->held) {
+				bt_hf->held(call);
+			}
+		}
+		break;
+	case BT_HFP_CLCC_STATUS_DIALING:
+		break;
+	case BT_HFP_CLCC_STATUS_ALERTING:
+		break;
+	case BT_HFP_CLCC_STATUS_INCOMING:
+		break;
+	case BT_HFP_CLCC_STATUS_WAITING:
+		break;
+	case BT_HFP_CLCC_STATUS_CALL_HELD_HOLD:
+		if ((atomic_get(call->state) == BT_HFP_HF_CALL_STATE_INCOMING) ||
+		    (atomic_get(call->state) == BT_HFP_HF_CALL_STATE_WAITING)) {
+			atomic_set_bit(call->flags, BT_HFP_HF_CALL_INCOMING_HELD);
+			hf_call_state_update(call, BT_HFP_HF_CALL_STATE_ACTIVE);
+			if (bt_hf->incoming_held) {
+				bt_hf->incoming_held(call);
+			}
+		}
+		break;
 	}
-
-	return 0;
 }
 
-static void slc_completed(struct at_client *hf_at)
+static int clcc_handle(struct at_client *hf_at)
 {
 	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
-	struct bt_conn *conn = hf->acl;
-
-	if (bt_hf->connected) {
-		bt_hf->connected(conn);
+	int err;
+	struct bt_hfp_hf_call *call;
+	uint32_t index;
+	uint32_t dir;
+	uint32_t status;
+	uint32_t mode;
+	uint32_t mpty;
+	char *number = NULL;
+	uint32_t type = 0;
+	bool incoming = false;
+
+	err = at_get_number(hf_at, &index);
+	if (err < 0) {
+		LOG_ERR("Error getting index");
+		return err;
 	}
 
-	if (hfp_hf_send_cmd(hf, NULL, cmee_finish, "AT+CMEE=1") < 0) {
-		LOG_ERR("Error Sending AT+CMEE");
+	call = get_call_with_index(hf, (uint8_t)index);
+	if (!call) {
+		LOG_INF("Valid call with index %d not found", index);
+		call = get_call_without_index(hf);
+		if (!call) {
+			LOG_INF("Not available call");
+			return 0;
+		}
+		call->index = (uint8_t)index;
 	}
-}
 
-int cmer_finish(struct at_client *hf_at, enum at_result result,
-		enum at_cme cme_err)
-{
-	if (result != AT_RESULT_OK) {
-		LOG_ERR("SLC Connection ERROR in response");
-		hf_slc_error(hf_at);
-		return -EINVAL;
-	}
+	atomic_set_bit(call->flags, BT_HFP_HF_CALL_CLCC);
 
-	slc_completed(hf_at);
+	err = at_get_number(hf_at, &dir);
+	if (err < 0) {
+		LOG_ERR("Error getting dir");
+		return err;
+	}
+
+	if (atomic_test_bit(call->flags, BT_HFP_HF_CALL_INCOMING) ||
+		atomic_test_bit(call->flags, BT_HFP_HF_CALL_INCOMING_3WAY)) {
+		incoming = true;
+	}
+
+	if (incoming != !!dir) {
+		LOG_ERR("Call dir of HF is not aligned with AG");
+		return 0;
+	}
+
+	err = at_get_number(hf_at, &status);
+	if (err < 0) {
+		LOG_ERR("Error getting status");
+		return err;
+	}
+
+	err = at_get_number(hf_at, &mode);
+	if (err < 0) {
+		LOG_ERR("Error getting mode");
+		return err;
+	}
+
+	err = at_get_number(hf_at, &mpty);
+	if (err < 0) {
+		LOG_ERR("Error getting mpty");
+		return err;
+	}
+
+	number = at_get_string(hf_at);
+
+	if (number) {
+		(void)at_get_number(hf_at, &type);
+	}
+
+	call_state_update(call, status);
+
+	LOG_DBG("CLCC idx %d dir %d status %d mode %d mpty %d number %s type %d",
+		index, dir, status, mode, mpty, number, type);
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_ECS */
+
+#if defined(CONFIG_BT_HFP_HF_VOICE_RECG)
+static int bvra_handle(struct at_client *hf_at)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	int err;
+	uint32_t activate;
+	uint32_t state;
+	char *id;
+	char text_id[BT_HFP_BVRA_TEXT_ID_MAX_LEN + 1];
+	size_t id_len;
+	uint32_t type;
+	uint32_t operation;
+	char *text;
+
+	err = at_get_number(hf_at, &activate);
+	if (err < 0) {
+		LOG_ERR("Error getting activate");
+		return err;
+	}
+
+	if (activate) {
+		if (!atomic_test_and_set_bit(hf->flags, BT_HFP_HF_FLAG_VRE_ACTIVATE)) {
+			if (bt_hf->voice_recognition) {
+				bt_hf->voice_recognition(hf, true);
+			}
+		}
+	} else {
+		if (atomic_test_and_clear_bit(hf->flags, BT_HFP_HF_FLAG_VRE_ACTIVATE)) {
+			if (bt_hf->voice_recognition) {
+				bt_hf->voice_recognition(hf, false);
+			}
+		}
+	}
+
+#if defined(CONFIG_BT_HFP_HF_ENH_VOICE_RECG)
+	err = at_get_number(hf_at, &state);
+	if (err < 0) {
+		LOG_INF("Error getting VRE state");
+		return 0;
+	}
+
+	if (bt_hf->vre_state) {
+		bt_hf->vre_state(hf, (uint8_t)state);
+	}
+#endif /* CONFIG_BT_HFP_HF_ENH_VOICE_RECG */
+
+#if defined(CONFIG_BT_HFP_HF_VOICE_RECG_TEXT)
+	id = at_get_raw_string(hf_at, &id_len);
+	if (!id) {
+		LOG_INF("Error getting text ID");
+		return 0;
+	}
+
+	if (id_len > BT_HFP_BVRA_TEXT_ID_MAX_LEN) {
+		LOG_ERR("Invalid text ID length %d", id_len);
+		return -ENOTSUP;
+	}
+
+	strncpy(text_id, id, MIN(id_len, BT_HFP_BVRA_TEXT_ID_MAX_LEN));
+	text_id[MIN(id_len, BT_HFP_BVRA_TEXT_ID_MAX_LEN)] = '\0';
+
+	err = at_get_number(hf_at, &type);
+	if (err < 0) {
+		LOG_INF("Error getting text type");
+		return 0;
+	}
+
+	err = at_get_number(hf_at, &operation);
+	if (err < 0) {
+		LOG_INF("Error getting text operation");
+		return 0;
+	}
+
+	text = at_get_string(hf_at);
+	if (!text) {
+		LOG_INF("Error getting text string");
+		return 0;
+	}
+
+	if (bt_hf->textual_representation) {
+		bt_hf->textual_representation(hf, text_id, (uint8_t)type,
+			(uint8_t)operation, text);
+	}
+#endif /* CONFIG_BT_HFP_HF_VOICE_RECG_TEXT */
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_VOICE_RECG */
+
+static struct bt_hfp_hf_call *get_dialing_call(struct bt_hfp_hf *hf)
+{
+	struct bt_hfp_hf_call *call;
+
+	for (size_t index = 0; index < ARRAY_SIZE(hf->calls); index++) {
+		call = &hf->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_IN_USING)) {
+			continue;
+		}
+
+		switch (atomic_get(call->state)) {
+		case BT_HFP_HF_CALL_STATE_OUTGOING:
+		case BT_HFP_HF_CALL_STATE_INCOMING:
+		case BT_HFP_HF_CALL_STATE_ALERTING:
+		case BT_HFP_HF_CALL_STATE_WAITING:
+			return call;
+		}
+	}
+
+	return NULL;
+}
+
+static struct bt_hfp_hf_call *get_call_with_state(struct bt_hfp_hf *hf, int state)
+{
+	struct bt_hfp_hf_call *call;
+
+	for (size_t index = 0; index < ARRAY_SIZE(hf->calls); index++) {
+		call = &hf->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_IN_USING)) {
+			continue;
+		}
+
+		if (atomic_get(call->state) == state) {
+			return call;
+		}
+	}
+
+	return NULL;
+}
+
+static struct bt_hfp_hf_call *get_call_with_flag(struct bt_hfp_hf *hf, int flag)
+{
+	struct bt_hfp_hf_call *call;
+
+	for (size_t index = 0; index < ARRAY_SIZE(hf->calls); index++) {
+		call = &hf->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_IN_USING)) {
+			continue;
+		}
+
+		if (atomic_test_bit(call->flags, flag)) {
+			return call;
+		}
+	}
+
+	return NULL;
+}
+
+static struct bt_hfp_hf_call *get_call_with_state_and_flag(struct bt_hfp_hf *hf,
+		int state, int flag)
+{
+	struct bt_hfp_hf_call *call;
+
+	for (size_t index = 0; index < ARRAY_SIZE(hf->calls); index++) {
+		call = &hf->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_IN_USING)) {
+			continue;
+		}
+
+		if ((atomic_get(call->state) == state) &&
+			atomic_test_bit(call->flags, flag)) {
+			return call;
+		}
+	}
+
+	return NULL;
+}
+
+static struct bt_hfp_hf_call *get_using_call(struct bt_hfp_hf *hf)
+{
+	struct bt_hfp_hf_call *call;
+
+	for (size_t index = 0; index < ARRAY_SIZE(hf->calls); index++) {
+		call = &hf->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_IN_USING)) {
+			continue;
+		}
+
+		return call;
+	}
+
+	return NULL;
+}
+
+static void bt_hf_deferred_work(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct bt_hfp_hf *hf = CONTAINER_OF(dwork, struct bt_hfp_hf, deferred_work);
+
+	hf_query_current_calls(hf);
+}
+
+static struct bt_hfp_hf_call *get_new_call(struct bt_hfp_hf *hf)
+{
+	struct bt_hfp_hf_call *call;
+
+	for (size_t index = 0; index < ARRAY_SIZE(hf->calls); index++) {
+		call = &hf->calls[index];
+
+		if (atomic_test_and_set_bit(call->flags, BT_HFP_HF_CALL_IN_USING)) {
+			continue;
+		}
+
+		call->hf = hf;
+
+		return call;
+	}
+
+	return NULL;
+}
+
+static int get_using_call_count(struct bt_hfp_hf *hf)
+{
+	struct bt_hfp_hf_call *call;
+	int count = 0;
+
+	for (size_t index = 0; index < ARRAY_SIZE(hf->calls); index++) {
+		call = &hf->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_IN_USING)) {
+			continue;
+		}
+
+		count++;
+	}
+
+	return count;
+}
+
+static void set_all_calls_held_state(struct bt_hfp_hf *hf, bool held)
+{
+	struct bt_hfp_hf_call *call;
+
+	for (size_t index = 0; index < ARRAY_SIZE(hf->calls); index++) {
+		call = &hf->calls[index];
+
+		if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_IN_USING)) {
+			continue;
+		}
+
+		if (held && (atomic_get(call->state) == BT_HFP_HF_CALL_STATE_ACTIVE)) {
+			hf_call_state_update(call, BT_HFP_HF_CALL_STATE_HELD);
+			if (bt_hf->held) {
+				bt_hf->held(call);
+			}
+		}
+
+		if (!held && (atomic_get(call->state) == BT_HFP_HF_CALL_STATE_HELD)) {
+			hf_call_state_update(call, BT_HFP_HF_CALL_STATE_ACTIVE);
+			if (bt_hf->retrieve) {
+				bt_hf->retrieve(call);
+			}
+		}
+	}
+}
+
+static void ag_indicator_handle_call(struct bt_hfp_hf *hf, uint32_t value)
+{
+	struct bt_hfp_hf_call *call;
+
+	LOG_DBG("call %d", value);
+
+	if (value) {
+		call = get_dialing_call(hf);
+		if (!call) {
+			return;
+		}
+
+		hf_call_state_update(call, BT_HFP_HF_CALL_STATE_ACTIVE);
+
+		if (atomic_test_bit(call->flags, BT_HFP_HF_CALL_INCOMING_HELD)) {
+			if (bt_hf->incoming_held) {
+				bt_hf->incoming_held(call);
+			}
+		} else {
+			if (bt_hf->accept) {
+				bt_hf->accept(call);
+			}
+		}
+	} else {
+		do {
+			call = get_using_call(hf);
+			if (!call) {
+				return;
+			}
+
+			switch (atomic_get(call->state)) {
+			case BT_HFP_HF_CALL_STATE_OUTGOING:
+			case BT_HFP_HF_CALL_STATE_INCOMING:
+			case BT_HFP_HF_CALL_STATE_ALERTING:
+			case BT_HFP_HF_CALL_STATE_WAITING:
+				hf_reject_call(call);
+				break;
+			case BT_HFP_HF_CALL_STATE_ACTIVE:
+				if (atomic_test_and_clear_bit(call->flags,
+							      BT_HFP_HF_CALL_INCOMING_HELD)) {
+					hf_reject_call(call);
+					break;
+				}
+				__fallthrough;
+			case BT_HFP_HF_CALL_STATE_HELD:
+				hf_terminate_call(call);
+				break;
+			default:
+				free_call(call);
+				break;
+			}
+		} while (call);
+	}
+}
+
+static void ag_indicator_handle_call_setup(struct bt_hfp_hf *hf, uint32_t value)
+{
+	struct bt_hfp_hf_call *call;
+	int call_count;
+
+	call_count = get_using_call_count(hf);
+
+	LOG_DBG("call setup %d", value);
+
+	switch (value) {
+	case BT_HFP_CALL_SETUP_NONE:
+		if (call_count == 1) {
+			call = get_using_call(hf);
+			if (!call) {
+				break;
+			}
+
+			if ((atomic_get(call->state) == BT_HFP_HF_CALL_STATE_ACTIVE) ||
+				(atomic_get(call->state) == BT_HFP_HF_CALL_STATE_HELD)) {
+				break;
+			}
+
+			hf_reject_call(call);
+		} else {
+			call = get_dialing_call(hf);
+			if (!call) {
+				break;
+			}
+
+			if (atomic_get(call->state) == BT_HFP_HF_CALL_STATE_OUTGOING) {
+				LOG_INF("The outgoing is not alerted");
+				hf_reject_call(call);
+			} else {
+				LOG_INF("Waiting for +CIEV: (callheld = 1)");
+				k_work_reschedule(&hf->deferred_work,
+						  K_MSEC(HF_ENHANCED_CALL_STATUS_TIMEOUT));
+			}
+		}
+		break;
+	case BT_HFP_CALL_SETUP_INCOMING:
+		call = get_call_with_state(hf, BT_HFP_HF_CALL_STATE_INCOMING);
+		if (!call) {
+			call = get_new_call(hf);
+			if (!call) {
+				break;
+			}
+			hf_call_state_update(call, BT_HFP_HF_CALL_STATE_INCOMING);
+		}
+
+		if (call_count == 0) {
+			atomic_set_bit(call->flags, BT_HFP_HF_CALL_INCOMING);
+		} else {
+			atomic_set_bit(call->flags, BT_HFP_HF_CALL_INCOMING_3WAY);
+		}
+		if (bt_hf->incoming) {
+			bt_hf->incoming(hf, call);
+		}
+		hf_call_state_update(call, BT_HFP_HF_CALL_STATE_WAITING);
+		break;
+	case BT_HFP_CALL_SETUP_OUTGOING:
+		call = get_call_with_state(hf, BT_HFP_HF_CALL_STATE_OUTGOING);
+		if (!call) {
+			call = get_new_call(hf);
+			if (!call) {
+				break;
+			}
+			hf_call_state_update(call, BT_HFP_HF_CALL_STATE_OUTGOING);
+		}
+
+		if (call_count) {
+			atomic_set_bit(call->flags, BT_HFP_HF_CALL_OUTGOING_3WAY);
+		}
+		if (bt_hf->outgoing) {
+			bt_hf->outgoing(hf, call);
+		}
+		break;
+	case BT_HFP_CALL_SETUP_REMOTE_ALERTING:
+		call = get_call_with_state(hf, BT_HFP_HF_CALL_STATE_OUTGOING);
+		if (!call) {
+			break;
+		}
+
+		hf_call_state_update(call, BT_HFP_HF_CALL_STATE_ALERTING);
+		if (bt_hf->remote_ringing) {
+			bt_hf->remote_ringing(call);
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+static void ag_indicator_handle_call_held(struct bt_hfp_hf *hf, uint32_t value)
+{
+	struct bt_hfp_hf_call *call;
+
+	k_work_reschedule(&hf->deferred_work, K_MSEC(HF_ENHANCED_CALL_STATUS_TIMEOUT));
+
+	LOG_DBG("call setup %d", value);
+
+	switch (value) {
+	case BT_HFP_CALL_HELD_NONE:
+		set_all_calls_held_state(hf, false);
+		break;
+	case BT_HFP_CALL_HELD_ACTIVE_HELD:
+		call = get_call_with_state(hf, BT_HFP_HF_CALL_STATE_ALERTING);
+		if (!call) {
+			call = get_call_with_state(hf, BT_HFP_HF_CALL_STATE_WAITING);
+			if (!call) {
+				break;
+			}
+		}
+
+		hf_call_state_update(call, BT_HFP_HF_CALL_STATE_ACTIVE);
+		if (bt_hf->accept) {
+			bt_hf->accept(call);
+		}
+		break;
+	case BT_HFP_CALL_HELD_HELD:
+		set_all_calls_held_state(hf, true);
+		break;
+	default:
+		break;
+	}
+}
+
+void ag_indicator_handle_values(struct at_client *hf_at, uint32_t index,
+				uint32_t value)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("Index :%u, Value :%u", index, value);
+
+	if (index >= ARRAY_SIZE(ag_ind)) {
+		LOG_ERR("Max only %zu indicators are supported", ARRAY_SIZE(ag_ind));
+		return;
+	}
+
+	if (value > ag_ind[hf->ind_table[index]].max ||
+	    value < ag_ind[hf->ind_table[index]].min) {
+		LOG_ERR("Indicators out of range - value: %u", value);
+		return;
+	}
+
+	switch (hf->ind_table[index]) {
+	case HF_SERVICE_IND:
+		if (bt_hf->service) {
+			bt_hf->service(hf, value);
+		}
+		break;
+	case HF_CALL_IND:
+		ag_indicator_handle_call(hf, value);
+		break;
+	case HF_CALL_SETUP_IND:
+		ag_indicator_handle_call_setup(hf, value);
+		break;
+	case HF_CALL_HELD_IND:
+		ag_indicator_handle_call_held(hf, value);
+		break;
+	case HF_SIGNAL_IND:
+		if (bt_hf->signal) {
+			bt_hf->signal(hf, value);
+		}
+		break;
+	case HF_ROAM_IND:
+		if (bt_hf->roam) {
+			bt_hf->roam(hf, value);
+		}
+		break;
+	case HF_BATTERY_IND:
+		if (bt_hf->battery) {
+			bt_hf->battery(hf, value);
+		}
+		break;
+	default:
+		LOG_ERR("Unknown AG indicator");
+		break;
+	}
+}
+
+int cind_status_handle(struct at_client *hf_at)
+{
+	uint32_t index = 0U;
+
+	while (at_has_next_list(hf_at)) {
+		uint32_t value;
+		int ret;
+
+		ret = at_get_number(hf_at, &value);
+		if (ret < 0) {
+			LOG_ERR("could not get the value");
+			return ret;
+		}
+
+		ag_indicator_handle_values(hf_at, index, value);
+
+		index++;
+	}
+
+	return 0;
+}
+
+int cind_status_resp(struct at_client *hf_at, struct net_buf *buf)
+{
+	int err;
+
+	err = at_parse_cmd_input(hf_at, buf, "CIND", cind_status_handle,
+				 AT_CMD_TYPE_NORMAL);
+	if (err < 0) {
+		LOG_ERR("Error parsing CMD input");
+		hf_slc_error(hf_at);
+	}
+
+	return 0;
+}
+
+int ciev_handle(struct at_client *hf_at)
+{
+	uint32_t index, value;
+	int ret;
+
+	ret = at_get_number(hf_at, &index);
+	if (ret < 0) {
+		LOG_ERR("could not get the Index");
+		return ret;
+	}
+	/* The first element of the list shall have 1 */
+	if (!index) {
+		LOG_ERR("Invalid index value '0'");
+		return 0;
+	}
+
+	ret = at_get_number(hf_at, &value);
+	if (ret < 0) {
+		LOG_ERR("could not get the value");
+		return ret;
+	}
+
+	ag_indicator_handle_values(hf_at, (index - 1), value);
+
+	return 0;
+}
+
+int ring_handle(struct at_client *hf_at)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	struct bt_hfp_hf_call *call;
+
+	call = get_call_with_state(hf, BT_HFP_HF_CALL_STATE_WAITING);
+	if (!call) {
+		return 0;
+	}
+
+	if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_INCOMING)) {
+		LOG_WRN("Invalid call dir (outgoing)");
+	}
+
+	if (bt_hf->ring_indication) {
+		bt_hf->ring_indication(call);
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_BT_HFP_HF_CLI)
+int clip_handle(struct at_client *hf_at)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	char *number;
+	uint32_t type;
+	int err;
+	struct bt_hfp_hf_call *call;
+
+	number = at_get_string(hf_at);
+
+	err = at_get_number(hf_at, &type);
+	if (err) {
+		LOG_WRN("could not get the type");
+	} else {
+		type = 0;
+	}
+
+
+	call = get_call_with_state(hf, BT_HFP_HF_CALL_STATE_WAITING);
+	if (!call) {
+		return 0;
+	}
+
+	if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_INCOMING)) {
+		LOG_WRN("Invalid call dir (outgoing)");
+	}
+
+	if (bt_hf->clip) {
+		bt_hf->clip(call, number, (uint8_t)type);
+	}
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_CLI */
+
+#if defined(CONFIG_BT_HFP_HF_VOLUME)
+int vgm_handle(struct at_client *hf_at)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	uint32_t gain;
+	int err;
+
+	err = at_get_number(hf_at, &gain);
+	if (err) {
+		LOG_ERR("could not get the microphone gain");
+		return err;
+	}
+
+	if (gain > BT_HFP_HF_VGM_GAIN_MAX) {
+		LOG_ERR("Invalid microphone gain (%d > %d)", gain, BT_HFP_HF_VGM_GAIN_MAX);
+		return -EINVAL;
+	}
+
+	if (bt_hf->vgm) {
+		bt_hf->vgm(hf, (uint8_t)gain);
+	}
+
+	return 0;
+}
+
+int vgs_handle(struct at_client *hf_at)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	uint32_t gain;
+	int err;
+
+	err = at_get_number(hf_at, &gain);
+	if (err) {
+		LOG_ERR("could not get the speaker gain");
+		return err;
+	}
+
+	if (gain > BT_HFP_HF_VGS_GAIN_MAX) {
+		LOG_ERR("Invalid speaker gain (%d > %d)", gain, BT_HFP_HF_VGS_GAIN_MAX);
+		return -EINVAL;
+	}
+
+	if (bt_hf->vgs) {
+		bt_hf->vgs(hf, (uint8_t)gain);
+	}
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_VOLUME */
+
+int bsir_handle(struct at_client *hf_at)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	uint32_t inband;
+	int err;
+
+	err = at_get_number(hf_at, &inband);
+	if (err) {
+		LOG_ERR("could not get bsir value");
+		return err;
+	}
+
+	if (inband > 1) {
+		LOG_ERR("Invalid %d bsir value", inband);
+		return -EINVAL;
+	}
+
+	if (bt_hf->inband_ring) {
+		bt_hf->inband_ring(hf, (bool)inband);
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_BT_HFP_HF_CODEC_NEG)
+int bcs_handle(struct at_client *hf_at)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	uint32_t codec_id;
+	int err;
+
+	err = at_get_number(hf_at, &codec_id);
+	if (err) {
+		LOG_ERR("could not get bcs value");
+		return err;
+	}
+
+	if (!(hf->hf_codec_ids & BIT(codec_id))) {
+		LOG_ERR("Invalid codec id %d", codec_id);
+		err = bt_hfp_hf_set_codecs(hf, hf->hf_codec_ids);
+		return err;
+	}
+
+	atomic_set_bit(hf->flags, BT_HFP_HF_FLAG_CODEC_CONN);
+
+	if (bt_hf->codec_negotiate) {
+		bt_hf->codec_negotiate(hf, codec_id);
+		return 0;
+	}
+
+	err = bt_hfp_hf_select_codec(hf, codec_id);
+	return err;
+}
+#endif /* CONFIG_BT_HFP_HF_CODEC_NEG */
+
+static int btrh_handle(struct at_client *hf_at)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	uint32_t on_hold;
+	int err;
+	struct bt_hfp_hf_call *call;
+
+	err = at_get_number(hf_at, &on_hold);
+	if (err < 0) {
+		LOG_ERR("Error getting value");
+		return err;
+	}
+
+	if (on_hold == BT_HFP_BTRH_ON_HOLD) {
+		call = get_call_with_state(hf, BT_HFP_HF_CALL_STATE_WAITING);
+		if (!call) {
+			return 0;
+		}
+
+		if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_INCOMING)) {
+			LOG_WRN("Invalid call dir (outgoing)");
+		}
+		atomic_set_bit(call->flags, BT_HFP_HF_CALL_INCOMING_HELD);
+	} else {
+		call = get_call_with_state_and_flag(hf,
+			BT_HFP_HF_CALL_STATE_ACTIVE, BT_HFP_HF_CALL_INCOMING_HELD);
+		if (!call) {
+			return 0;
+		}
+
+		if (on_hold == BT_HFP_BTRH_ACCEPTED) {
+			atomic_clear_bit(call->flags, BT_HFP_HF_CALL_INCOMING_HELD);
+			if (bt_hf && bt_hf->accept) {
+				bt_hf->accept(call);
+			}
+		} else if (on_hold == BT_HFP_BTRH_REJECTED) {
+			hf_reject_call(call);
+		} else {
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+static int ccwa_handle(struct at_client *hf_at)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	char *number;
+	uint32_t type;
+	int err;
+	struct bt_hfp_hf_call *call;
+
+	number = at_get_string(hf_at);
+
+	err = at_get_number(hf_at, &type);
+	if (err) {
+		LOG_WRN("could not get the type");
+	} else {
+		type = 0;
+	}
+
+	call = get_new_call(hf);
+	if (!call) {
+		LOG_ERR("Not available call object");
+		return 0;
+	}
+
+	hf_call_state_update(call, BT_HFP_HF_CALL_STATE_INCOMING);
+	if (bt_hf->call_waiting) {
+		bt_hf->call_waiting(call, number, (uint8_t)type);
+	}
+
+	return 0;
+}
+
+static struct _chld_feature {
+	const char *name;
+	int value;
+} chld_feature_map[] = {
+	{ "1x", BT_HFP_CALL_RELEASE_SPECIFIED_ACTIVE },
+	{ "2x", BT_HFP_CALL_PRIVATE_CNLTN_MODE },
+	{ "0",  BT_HFP_CHLD_RELEASE_ALL },
+	{ "1",  BT_HFP_CHLD_RELEASE_ACTIVE_ACCEPT_OTHER },
+	{ "2",  BT_HFP_CALL_HOLD_ACTIVE_ACCEPT_OTHER },
+	{ "3",  BT_HFP_CALL_ACTIVE_HELD },
+	{ "4",  BT_HFP_CALL_QUITE },
+};
+
+static int get_chld_feature(const char *name)
+{
+	struct _chld_feature *chld;
+
+	for (size_t index = 0; index < ARRAY_SIZE(chld_feature_map); index++) {
+		chld = &chld_feature_map[index];
+		if (!strncmp(name, chld->name, strlen(chld->name))) {
+			return chld->value;
+		}
+	}
+
+	return -EINVAL;
+}
+
+int chld_handle(struct at_client *hf_at)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	char *value;
+	uint32_t chld_features = 0;
+	int err;
+
+	/* Parsing Example: CHLD: (0,1,2,3,4) */
+	if (at_open_list(hf_at) < 0) {
+		LOG_ERR("Could not get open list");
+		goto error;
+	}
+
+	while (at_has_next_list(hf_at)) {
+		value = at_get_raw_string(hf_at, NULL);
+		if (!value) {
+			LOG_ERR("Could not get value");
+			goto error;
+		}
+
+		err = get_chld_feature(value);
+		if (err < 0) {
+			LOG_ERR("Cannot parse the value %s", value);
+			goto error;
+		}
+
+		if (NUM_BITS(sizeof(chld_features)) > err) {
+			chld_features |= BIT(err);
+		}
+	}
+
+	if (at_close_list(hf_at) < 0) {
+		LOG_ERR("Could not get close list");
+		goto error;
+	}
+
+	if (!((chld_features & BIT(BT_HFP_CHLD_RELEASE_ACTIVE_ACCEPT_OTHER)) &&
+	    (chld_features & BIT(BT_HFP_CALL_HOLD_ACTIVE_ACCEPT_OTHER)))) {
+		LOG_ERR("AT+CHLD values 1 and 2 should be supported by AG");
+		goto error;
+	}
+
+	hf->chld_features = chld_features;
+
+	return 0;
+
+error:
+	LOG_ERR("Error on AT+CHLD=? response");
+	hf_slc_error(hf_at);
+	return -EINVAL;
+}
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+
+static int cnum_handle(struct at_client *hf_at)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	int err;
+	char *alpha;
+	char *number;
+	uint32_t type;
+	char *speed;
+	uint32_t service = 4;
+
+	alpha = at_get_raw_string(hf_at, NULL);
+	number = at_get_string(hf_at);
+	if (!number) {
+		LOG_INF("Cannot get number");
+		return -EINVAL;
+	}
+
+	err = at_get_number(hf_at, &type);
+	if (err) {
+		LOG_INF("Cannot get type");
+		return -EINVAL;
+	}
+
+	speed = at_get_raw_string(hf_at, NULL);
+
+	err = at_get_number(hf_at, &service);
+	if (err) {
+		LOG_INF("Cannot get service");
+	}
+
+	if (bt_hf->subscriber_number) {
+		bt_hf->subscriber_number(hf, number, (uint8_t)type, (uint8_t)service);
+	}
+
+	LOG_DBG("CNUM number %s type %d service %d", number, type, service);
+
+	return 0;
+}
+
+#if defined(CONFIG_BT_HFP_HF_HF_INDICATORS)
+static int bind_handle(struct at_client *hf_at)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	int err;
+	uint32_t index;
+	uint32_t value;
+	uint32_t ind = 0;
+	uint32_t ind_enable = hf->ind_enable;
+
+	err = at_open_list(hf_at);
+	if (!err) {
+		/* It is a list. */
+		while (at_has_next_list(hf_at)) {
+			err = at_get_number(hf_at, &index);
+			if (err) {
+				LOG_INF("Cannot get indicator");
+				goto failed;
+			}
+
+			ind |= BIT(index);
+		}
+
+		if (at_close_list(hf_at) < 0) {
+			LOG_ERR("Could not get close list");
+			goto failed;
+		}
+
+		hf->ag_ind = ind;
+		return 0;
+	}
+
+	err = at_get_number(hf_at, &index);
+	if (err) {
+		LOG_INF("Cannot get indicator");
+		goto failed;
+	}
+
+	err = at_get_number(hf_at, &value);
+	if (err) {
+		LOG_INF("Cannot get status");
+		goto failed;
+	}
+
+	if (!value) {
+		ind_enable &= ~BIT(index);
+	} else {
+		ind_enable |= BIT(index);
+	}
+
+	hf->ind_enable = ind_enable;
+	return 0;
+
+failed:
+	LOG_ERR("Error on AT+BIND response");
+	hf_slc_error(hf_at);
+	return -EINVAL;
+}
+#endif /* CONFIG_BT_HFP_HF_HF_INDICATORS */
+
+static const struct unsolicited {
+	const char *cmd;
+	enum at_cmd_type type;
+	int (*func)(struct at_client *hf_at);
+} handlers[] = {
+	{ "CIEV", AT_CMD_TYPE_UNSOLICITED, ciev_handle },
+	{ "RING", AT_CMD_TYPE_OTHER, ring_handle },
+#if defined(CONFIG_BT_HFP_HF_CLI)
+	{ "CLIP", AT_CMD_TYPE_UNSOLICITED, clip_handle },
+#endif /* CONFIG_BT_HFP_HF_CLI */
+#if defined(CONFIG_BT_HFP_HF_VOLUME)
+	{ "VGM", AT_CMD_TYPE_UNSOLICITED, vgm_handle },
+	{ "VGS", AT_CMD_TYPE_UNSOLICITED, vgs_handle },
+#endif /* CONFIG_BT_HFP_HF_VOLUME */
+	{ "BSIR", AT_CMD_TYPE_UNSOLICITED, bsir_handle },
+#if defined(CONFIG_BT_HFP_HF_CODEC_NEG)
+	{ "BCS", AT_CMD_TYPE_UNSOLICITED, bcs_handle },
+#endif /* CONFIG_BT_HFP_HF_CODEC_NEG */
+	{ "BTRH", AT_CMD_TYPE_UNSOLICITED, btrh_handle },
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+	{ "CCWA", AT_CMD_TYPE_UNSOLICITED, ccwa_handle },
+	{ "CHLD", AT_CMD_TYPE_UNSOLICITED, chld_handle },
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+#if defined(CONFIG_BT_HFP_HF_ECS)
+	{ "CLCC", AT_CMD_TYPE_UNSOLICITED, clcc_handle },
+#endif /* CONFIG_BT_HFP_HF_ECS */
+#if defined(CONFIG_BT_HFP_HF_VOICE_RECG)
+	{ "BVRA", AT_CMD_TYPE_UNSOLICITED, bvra_handle },
+#endif /* CONFIG_BT_HFP_HF_VOICE_RECG */
+	{ "CNUM", AT_CMD_TYPE_UNSOLICITED, cnum_handle },
+#if defined(CONFIG_BT_HFP_HF_HF_INDICATORS)
+	{ "BIND", AT_CMD_TYPE_UNSOLICITED, bind_handle },
+#endif /* CONFIG_BT_HFP_HF_HF_INDICATORS */
+};
+
+static const struct unsolicited *hfp_hf_unsol_lookup(struct at_client *hf_at)
+{
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(handlers); i++) {
+		if (!strncmp(hf_at->buf, handlers[i].cmd,
+			     strlen(handlers[i].cmd))) {
+			return &handlers[i];
+		}
+	}
+
+	return NULL;
+}
+
+int unsolicited_cb(struct at_client *hf_at, struct net_buf *buf)
+{
+	const struct unsolicited *handler;
+
+	handler = hfp_hf_unsol_lookup(hf_at);
+	if (!handler) {
+		LOG_ERR("Unhandled unsolicited response");
+		return -ENOMSG;
+	}
+
+	if (!at_parse_cmd_input(hf_at, buf, handler->cmd, handler->func,
+				handler->type)) {
+		return 0;
+	}
+
+	return -ENOMSG;
+}
+
+static int send_at_cmee(struct bt_hfp_hf *hf, at_finish_cb_t cb)
+{
+	if (hf->ag_features & BT_HFP_AG_FEATURE_EXT_ERR) {
+		return hfp_hf_send_cmd(hf, NULL, cb, "AT+CMEE=1");
+	} else {
+		return -ENOTSUP;
+	}
+}
+
+static int at_cmee_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("CMEE set (result %d) on %p", result, hf);
+
+	return 0;
+}
+
+static int send_at_cops(struct bt_hfp_hf *hf, at_finish_cb_t cb)
+{
+	return hfp_hf_send_cmd(hf, NULL, cb, "AT+COPS=3,0");
+}
+
+static int at_cops_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("COPS set (result %d) on %p", result, hf);
+
+	return 0;
+}
+
+#if defined(CONFIG_BT_HFP_HF_CLI)
+static int send_at_clip(struct bt_hfp_hf *hf, at_finish_cb_t cb)
+{
+	return hfp_hf_send_cmd(hf, NULL, cb, "AT+CLIP=1");
+}
+
+static int at_clip_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("CLIP set (result %d) on %p", result, hf);
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_CLI */
+
+#if defined(CONFIG_BT_HFP_HF_VOLUME)
+static int send_at_vgm(struct bt_hfp_hf *hf, at_finish_cb_t cb)
+{
+	return hfp_hf_send_cmd(hf, NULL, cb, "AT+VGM=%d", hf->vgm);
+}
+
+static int at_vgm_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("VGM set (result %d) on %p", result, hf);
+
+	return 0;
+}
+
+static int send_at_vgs(struct bt_hfp_hf *hf, at_finish_cb_t cb)
+{
+	return hfp_hf_send_cmd(hf, NULL, cb, "AT+VGS=%d", hf->vgs);
+}
+
+static int at_vgs_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("VGS set (result %d) on %p", result, hf);
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_VOLUME */
+
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+static int send_at_ccwa(struct bt_hfp_hf *hf, at_finish_cb_t cb)
+{
+	if (!(hf->ag_features & BT_HFP_AG_FEATURE_3WAY_CALL)) {
+		return -ENOTSUP;
+	}
+
+	if (!(hf->hf_features & BT_HFP_HF_FEATURE_3WAY_CALL)) {
+		return -ENOTSUP;
+	}
+
+	return hfp_hf_send_cmd(hf, NULL, cb, "AT+CCWA=1");
+}
+
+static int at_ccwa_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("CCWA set (result %d) on %p", result, hf);
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+
+typedef int (*at_send_t)(struct bt_hfp_hf *hf, at_finish_cb_t cb);
+
+static struct at_cmd_init
+{
+	at_send_t send;
+	at_finish_cb_t finish;
+	bool disconnect; /* Disconnect if command failed. */
+} cmd_init_list[] = {
+#if defined(CONFIG_BT_HFP_HF_VOLUME)
+	{send_at_vgm, at_vgm_finish, false},
+	{send_at_vgs, at_vgs_finish, false},
+#endif /* CONFIG_BT_HFP_HF_VOLUME */
+	{send_at_cmee, at_cmee_finish, false},
+	{send_at_cops, at_cops_finish, false},
+#if defined(CONFIG_BT_HFP_HF_CLI)
+	{send_at_clip, at_clip_finish, false},
+#endif /* CONFIG_BT_HFP_HF_CLI */
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+	{send_at_ccwa, at_ccwa_finish, false},
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+};
+
+static int at_cmd_init_start(struct bt_hfp_hf *hf);
+
+static int at_cmd_init_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	at_finish_cb_t finish;
+
+	if (result != AT_RESULT_OK) {
+		LOG_WRN("It is ERROR response of AT command %d.", hf->cmd_init_seq);
+	}
+
+	if (ARRAY_SIZE(cmd_init_list) > hf->cmd_init_seq) {
+		finish = cmd_init_list[hf->cmd_init_seq].finish;
+		if (finish) {
+			(void)finish(hf_at, result, cme_err);
+		}
+	} else {
+		LOG_ERR("Invalid indicator (%d>=%d)", hf->cmd_init_seq,
+		    ARRAY_SIZE(cmd_init_list));
+	}
+
+	/* Goto next AT command */
+	hf->cmd_init_seq++;
+	(void)at_cmd_init_start(hf);
+	return 0;
+}
+
+static int at_cmd_init_start(struct bt_hfp_hf *hf)
+{
+	at_send_t send;
+	int err = -EINVAL;
+
+	while (ARRAY_SIZE(cmd_init_list) > hf->cmd_init_seq) {
+		LOG_DBG("Fetch AT command (%d)", hf->cmd_init_seq);
+		send = cmd_init_list[hf->cmd_init_seq].send;
+		if (send) {
+			LOG_DBG("Send AT command");
+			err = send(hf, at_cmd_init_finish);
+		} else {
+			LOG_WRN("Invalid send func of AT command");
+		}
+
+		if (!err) {
+			break;
+		}
+
+		LOG_WRN("AT command sending failed");
+		if (cmd_init_list[hf->cmd_init_seq].disconnect) {
+			hfp_hf_send_failed(hf);
+			break;
+		}
+		/* Goto next AT command */
+		LOG_WRN("Send next AT command");
+		hf->cmd_init_seq++;
+	}
+	return err;
+}
+
+static void slc_completed(struct at_client *hf_at)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	struct bt_conn *conn = hf->acl;
+
+	if (bt_hf->connected) {
+		bt_hf->connected(conn, hf);
+	}
+
+	atomic_set_bit(hf->flags, BT_HFP_HF_FLAG_CONNECTED);
+
+	/* Start with first AT command */
+	hf->cmd_init_seq = 0;
+	if (at_cmd_init_start(hf)) {
+		LOG_ERR("Fail to start AT command initialization");
+	}
+}
+
+#if defined(CONFIG_BT_HFP_HF_HF_INDICATORS)
+static int send_at_bind_status(struct bt_hfp_hf *hf, at_finish_cb_t cb)
+{
+	return hfp_hf_send_cmd(hf, NULL, cb, "AT+BIND?");
+}
+
+static int send_at_bind_hf_supported(struct bt_hfp_hf *hf, at_finish_cb_t cb)
+{
+	char buffer[4];
+	char *bind;
+
+	hf->hf_ind = 0;
+
+	bind = &buffer[0];
+	if (IS_ENABLED(CONFIG_BT_HFP_HF_HF_INDICATOR_ENH_SAFETY)) {
+		*bind = '0' + HFP_HF_ENHANCED_SAFETY_IND;
+		bind++;
+		*bind = ',';
+		bind++;
+		hf->hf_ind |= BIT(HFP_HF_ENHANCED_SAFETY_IND);
+	}
+
+	if (IS_ENABLED(CONFIG_BT_HFP_HF_HF_INDICATOR_BATTERY)) {
+		*bind = '0' + HFP_HF_BATTERY_LEVEL_IND;
+		bind++;
+		*bind = ',';
+		bind++;
+		hf->hf_ind |= BIT(HFP_HF_BATTERY_LEVEL_IND);
+	}
+
+	if (bind <= &buffer[0]) {
+		return -EINVAL;
+	}
+
+	bind--;
+	*bind = '\0';
+	return hfp_hf_send_cmd(hf, NULL, cb, "AT+BIND=%s", buffer);
+}
+
+static int send_at_bind_supported(struct bt_hfp_hf *hf, at_finish_cb_t cb)
+{
+	return hfp_hf_send_cmd(hf, NULL, cb, "AT+BIND=?");
+}
+#endif /* CONFIG_BT_HFP_HF_HF_INDICATORS */
+
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+static int send_at_chld_supported(struct bt_hfp_hf *hf, at_finish_cb_t cb)
+{
+	return hfp_hf_send_cmd(hf, NULL, cb, "AT+CHLD=?");
+}
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+
+static int send_at_cmer(struct bt_hfp_hf *hf, at_finish_cb_t cb)
+{
+	at_register_unsolicited(&hf->at, unsolicited_cb);
+	return hfp_hf_send_cmd(hf, NULL, cb, "AT+CMER=3,0,0,1");
+}
+
+static int send_at_cind_status(struct bt_hfp_hf *hf, at_finish_cb_t cb)
+{
+	return hfp_hf_send_cmd(hf, cind_status_resp, cb, "AT+CIND?");
+}
+
+static int send_at_cind_supported(struct bt_hfp_hf *hf, at_finish_cb_t cb)
+{
+	return hfp_hf_send_cmd(hf, cind_resp, cb, "AT+CIND=?");
+}
+
+#if defined(CONFIG_BT_HFP_HF_CODEC_NEG)
+static void get_codec_ids(struct bt_hfp_hf *hf, char *buffer, size_t buffer_len)
+{
+	size_t len = 0;
+	uint8_t ids = hf->hf_codec_ids;
+	int index = 0;
+
+	while (ids && (len < (buffer_len-2))) {
+		if (ids & 0x01) {
+			buffer[len++] = index + '0';
+			buffer[len++] = ',';
+		}
+		index++;
+		ids = ids >> 1;
+	}
+
+	if (len > 0) {
+		len--;
+	}
+
+	buffer[len] = '\0';
+}
+
+static int send_at_bac(struct bt_hfp_hf *hf, at_finish_cb_t cb)
+{
+	char ids[sizeof(hf->hf_codec_ids)*2*8 + 1];
+
+	get_codec_ids(hf, &ids[0], ARRAY_SIZE(ids));
+	return hfp_hf_send_cmd(hf, NULL, cb, "AT+BAC=%s", ids);
+}
+#endif /* CONFIG_BT_HFP_HF_CODEC_NEG */
+
+static int send_at_brsf(struct bt_hfp_hf *hf, at_finish_cb_t cb)
+{
+	return hfp_hf_send_cmd(hf, brsf_resp, cb, "AT+BRSF=%u", hf->hf_features);
+}
+
+static struct slc_init
+{
+	at_send_t send;
+	bool disconnect; /* Disconnect if command failed. */
+	uint32_t ag_feature_mask; /* AG feature mask */
+} slc_init_list[] = {
+	{send_at_brsf, true, 0},
+#if defined(CONFIG_BT_HFP_HF_CODEC_NEG)
+	{send_at_bac, true, BT_HFP_AG_FEATURE_CODEC_NEG},
+#endif /* CONFIG_BT_HFP_HF_CODEC_NEG */
+	{send_at_cind_supported, true, 0},
+	{send_at_cind_status, true, 0},
+	{send_at_cmer, true, 0},
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+	{send_at_chld_supported, true, BT_HFP_AG_FEATURE_3WAY_CALL},
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+#if defined(CONFIG_BT_HFP_HF_HF_INDICATORS)
+	{send_at_bind_hf_supported, true, BT_HFP_AG_FEATURE_HF_IND},
+	{send_at_bind_supported, true, BT_HFP_AG_FEATURE_HF_IND},
+	{send_at_bind_status, true, BT_HFP_AG_FEATURE_HF_IND},
+#endif /* CONFIG_BT_HFP_HF_HF_INDICATORS */
+};
+
+static int slc_init_start(struct bt_hfp_hf *hf);
+
+static int slc_init_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	if (result != AT_RESULT_OK) {
+		LOG_WRN("It is ERROR response of AT command %d.", hf->cmd_init_seq);
+		if (slc_init_list[hf->cmd_init_seq].disconnect) {
+			hf_slc_error(&hf->at);
+			return 0;
+		}
+	}
+
+	if (ARRAY_SIZE(slc_init_list) <= hf->cmd_init_seq) {
+		LOG_ERR("Invalid indicator (%d>=%d)", hf->cmd_init_seq,
+		    ARRAY_SIZE(slc_init_list));
+	}
+
+	/* Goto next AT command */
+	hf->cmd_init_seq++;
+	(void)slc_init_start(hf);
+	return 0;
+}
+
+static int slc_init_start(struct bt_hfp_hf *hf)
+{
+	at_send_t send;
+	uint32_t feture_mask;
+	int err = -EINVAL;
+
+	while (ARRAY_SIZE(slc_init_list) > hf->cmd_init_seq) {
+		LOG_DBG("Fetch AT command (%d)", hf->cmd_init_seq);
+		feture_mask = slc_init_list[hf->cmd_init_seq].ag_feature_mask;
+		if (feture_mask && (!(feture_mask & hf->ag_features))) {
+			/* The feature is not supported by AG. Skip the step. */
+			LOG_INF("Skip SLC init step %d", hf->cmd_init_seq);
+			hf->cmd_init_seq++;
+			continue;
+		}
+
+		send = slc_init_list[hf->cmd_init_seq].send;
+		if (send) {
+			LOG_DBG("Send AT command");
+			err = send(hf, slc_init_finish);
+		} else {
+			LOG_WRN("Invalid send func of AT command");
+		}
+
+		if (!err) {
+			break;
+		}
+
+		LOG_WRN("AT command sending failed");
+		if (slc_init_list[hf->cmd_init_seq].disconnect) {
+			hfp_hf_send_failed(hf);
+			break;
+		}
+		/* Goto next AT command */
+		LOG_WRN("Send next AT command");
+		hf->cmd_init_seq++;
+	}
+
+	if (ARRAY_SIZE(slc_init_list) <= hf->cmd_init_seq) {
+		slc_completed(&hf->at);
+	}
+
+	return err;
+}
+
+int hf_slc_establish(struct bt_hfp_hf *hf)
+{
+	int err;
+
+	LOG_DBG("");
+
+	hf->cmd_init_seq = 0;
+	err = slc_init_start(hf);
+	if (err < 0) {
+		hf_slc_error(&hf->at);
+		return err;
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_BT_HFP_HF_CLI)
+static int cli_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("CLIP set (result %d) on %p", result, hf);
+
+	/* AT+CLI is done. */
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_CLI */
+
+int bt_hfp_hf_cli(struct bt_hfp_hf *hf, bool enable)
+{
+#if defined(CONFIG_BT_HFP_HF_CLI)
+	int err;
+
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!atomic_test_bit(hf->flags, BT_HFP_HF_FLAG_CONNECTED)) {
+		LOG_ERR("SLC is not established on %p", hf);
+		return -EINVAL;
+	}
+
+	err = hfp_hf_send_cmd(hf, NULL, cli_finish, "AT+CLIP=%d", enable ? 1 : 0);
+	if (err < 0) {
+		LOG_ERR("HFP HF CLI set failed on %p", hf);
+	}
+
+	return err;
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_CLI */
+}
+
+#if defined(CONFIG_BT_HFP_HF_VOLUME)
+static int vgm_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("VGM set (result %d) on %p", result, hf);
+
+	/* AT+VGM is done. */
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_VOLUME */
+
+int bt_hfp_hf_vgm(struct bt_hfp_hf *hf, uint8_t gain)
+{
+#if defined(CONFIG_BT_HFP_HF_VOLUME)
+	int err;
+
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (gain > BT_HFP_HF_VGM_GAIN_MAX) {
+		LOG_ERR("Invalid gain %d>%d", gain, BT_HFP_HF_VGM_GAIN_MAX);
+		return -EINVAL;
+	}
+
+	hf->vgm = gain;
+
+	if (!atomic_test_bit(hf->flags, BT_HFP_HF_FLAG_CONNECTED)) {
+		return 0;
+	}
+
+	err = hfp_hf_send_cmd(hf, NULL, vgm_finish, "AT+VGM=%d", gain);
+	if (err < 0) {
+		LOG_ERR("HFP HF VGM set failed on %p", hf);
+	}
+
+	return err;
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_VOLUME */
+}
+
+#if defined(CONFIG_BT_HFP_HF_VOLUME)
+static int vgs_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("VGS set (result %d) on %p", result, hf);
+
+	/* AT+VGS is done. */
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_VOLUME */
+
+int bt_hfp_hf_vgs(struct bt_hfp_hf *hf, uint8_t gain)
+{
+#if defined(CONFIG_BT_HFP_HF_VOLUME)
+	int err;
+
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (gain > BT_HFP_HF_VGM_GAIN_MAX) {
+		LOG_ERR("Invalid gain %d>%d", gain, BT_HFP_HF_VGM_GAIN_MAX);
+		return -EINVAL;
+	}
+
+	hf->vgs = gain;
+
+	if (!atomic_test_bit(hf->flags, BT_HFP_HF_FLAG_CONNECTED)) {
+		return 0;
+	}
+
+	err = hfp_hf_send_cmd(hf, NULL, vgs_finish, "AT+VGS=%d", gain);
+	if (err < 0) {
+		LOG_ERR("HFP HF VGS set failed on %p", hf);
+	}
+
+	return err;
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_VOLUME */
+}
+
+static int cops_handle(struct at_client *hf_at)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	uint32_t mode;
+	uint32_t format;
+	char *operator;
+	int err;
+
+	err = at_get_number(hf_at, &mode);
+	if (err < 0) {
+		LOG_ERR("Error getting value");
+		return err;
+	}
+
+	err = at_get_number(hf_at, &format);
+	if (err < 0) {
+		LOG_ERR("Error getting value");
+		return err;
+	}
+
+	operator = at_get_string(hf_at);
+
+	if (bt_hf && bt_hf->operator) {
+		bt_hf->operator(hf, (uint8_t)mode, (uint8_t)format, operator);
+	}
+
+	return 0;
+}
+
+static int cops_resp(struct at_client *hf_at, struct net_buf *buf)
+{
+	int err;
+
+	LOG_DBG("");
+
+	err = at_parse_cmd_input(hf_at, buf, "COPS", cops_handle,
+				 AT_CMD_TYPE_NORMAL);
+	if (err < 0) {
+		LOG_ERR("Cannot parse response of AT+COPS?");
+		return err;
+	}
+
+	return 0;
+}
+
+static int cops_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("AT+COPS? (result %d) on %p", result, hf);
+
+	return 0;
+}
+
+int bt_hfp_hf_get_operator(struct bt_hfp_hf *hf)
+{
+	int err;
+
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!atomic_test_bit(hf->flags, BT_HFP_HF_FLAG_CONNECTED)) {
+		return 0;
+	}
+
+	err = hfp_hf_send_cmd(hf, cops_resp, cops_finish, "AT+COPS?");
+	if (err < 0) {
+		LOG_ERR("Fail to read the currently selected operator on %p", hf);
+	}
+
+	return err;
+}
+
+static int binp_handle(struct at_client *hf_at)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	char *number;
+
+	number = at_get_string(hf_at);
+
+	atomic_set_bit(hf->flags, BT_HFP_HF_FLAG_BINP);
+
+	if (bt_hf && bt_hf->request_phone_number) {
+		bt_hf->request_phone_number(hf, number);
+	}
+
+	return 0;
+}
+
+static int binp_resp(struct at_client *hf_at, struct net_buf *buf)
+{
+	int err;
+
+	LOG_DBG("");
+
+	err = at_parse_cmd_input(hf_at, buf, "BINP", binp_handle,
+				 AT_CMD_TYPE_NORMAL);
+	if (err < 0) {
+		LOG_ERR("Cannot parse response of AT+BINP=1");
+		return err;
+	}
+
+	return 0;
+}
+
+static int binp_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("AT+BINP=1 (result %d) on %p", result, hf);
+
+	if (!atomic_test_and_clear_bit(hf->flags, BT_HFP_HF_FLAG_BINP)) {
+		if (bt_hf && bt_hf->request_phone_number) {
+			bt_hf->request_phone_number(hf, NULL);
+		}
+	}
+
+	return 0;
+}
+
+int bt_hfp_hf_request_phone_number(struct bt_hfp_hf *hf)
+{
+	int err;
+
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!atomic_test_bit(hf->flags, BT_HFP_HF_FLAG_CONNECTED)) {
+		return 0;
+	}
+
+	atomic_clear_bit(hf->flags, BT_HFP_HF_FLAG_BINP);
+
+	err = hfp_hf_send_cmd(hf, binp_resp, binp_finish, "AT+BINP=1");
+	if (err < 0) {
+		LOG_ERR("Fail to request phone number to the AG on %p", hf);
+	}
+
+	return err;
+}
+
+static int vts_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("AT+VTS (result %d) on %p", result, hf);
+
+	return 0;
+}
+
+int bt_hfp_hf_transmit_dtmf_code(struct bt_hfp_hf_call *call, char code)
+{
+	struct bt_hfp_hf *hf;
+	int err;
+
+	LOG_DBG("");
+
+	if (!call) {
+		LOG_ERR("Invalid call");
+		return -ENOTCONN;
+	}
+
+	hf = call->hf;
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!atomic_test_bit(hf->flags, BT_HFP_HF_FLAG_CONNECTED)) {
+		LOG_ERR("SLC is not established on %p", hf);
+		return -ENOTCONN;
+	}
+
+	if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_IN_USING) ||
+		(!(!atomic_test_bit(call->flags, BT_HFP_HF_CALL_INCOMING_HELD) &&
+		(atomic_get(call->state) == BT_HFP_HF_CALL_STATE_ACTIVE)))) {
+		LOG_ERR("Invalid call status");
+		return -EINVAL;
+	}
+
+	if (!IS_VALID_DTMF(code)) {
+		LOG_ERR("Invalid code");
+		return -EINVAL;
+	}
+
+	err = hfp_hf_send_cmd(hf, NULL, vts_finish, "AT+VTS=%c", code);
+	if (err < 0) {
+		LOG_ERR("Fail to tramsit DTMF Codes on %p", hf);
+	}
+
+	return err;
+}
+
+static int cnum_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("AT+CNUM (result %d) on %p", result, hf);
+
+	return 0;
+}
+
+int bt_hfp_hf_query_subscriber(struct bt_hfp_hf *hf)
+{
+	int err;
+
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!atomic_test_bit(hf->flags, BT_HFP_HF_FLAG_CONNECTED)) {
+		LOG_ERR("SLC is not established on %p", hf);
+		return -ENOTCONN;
+	}
+
+	err = hfp_hf_send_cmd(hf, NULL, cnum_finish, "AT+CNUM");
+	if (err < 0) {
+		LOG_ERR("Fail to query subscriber number information on %p", hf);
+	}
+
+	return err;
+}
+
+static int bia_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("AT+BIA (result %d) on %p", result, hf);
+
+	return 0;
+}
+
+int bt_hfp_hf_indicator_status(struct bt_hfp_hf *hf, uint8_t status)
+{
+	int err;
+	size_t index;
+	char buffer[HF_MAX_AG_INDICATORS * 2 + 1];
+	char *bia_status;
+
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!atomic_test_bit(hf->flags, BT_HFP_HF_FLAG_CONNECTED)) {
+		LOG_ERR("SLC is not established on %p", hf);
+		return -ENOTCONN;
+	}
+
+	bia_status = &buffer[0];
+	for (index = 0; index < ARRAY_SIZE(hf->ind_table); index++) {
+		if ((hf->ind_table[index] != -1) && (index < NUM_BITS(sizeof(status)))) {
+			if (status & BIT(hf->ind_table[index])) {
+				*bia_status = '1';
+			} else {
+				*bia_status = '0';
+			}
+			bia_status++;
+			*bia_status = ',';
+			bia_status++;
+		} else {
+			break;
+		}
+	}
+
+	if (bia_status <= &buffer[0]) {
+		LOG_ERR("Not found valid AG indicator on %p", hf);
+		return -EINVAL;
+	}
+
+	bia_status--;
+	*bia_status = '\0';
+
+	err = hfp_hf_send_cmd(hf, NULL, bia_finish, "AT+BIA=%s", buffer);
+	if (err < 0) {
+		LOG_ERR("Fail to activated/deactivated AG indicators on %p", hf);
+	}
+
+	return err;
+}
+
+#if defined(CONFIG_BT_HFP_HF_HF_INDICATOR_ENH_SAFETY)
+static int biev_enh_safety_finish(struct at_client *hf_at,
+		   enum at_result result, enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("AT+BIEV (result %d) on %p", result, hf);
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_HF_INDICATOR_ENH_SAFETY */
+
+int bt_hfp_hf_enhanced_safety(struct bt_hfp_hf *hf, bool enable)
+{
+#if defined(CONFIG_BT_HFP_HF_HF_INDICATOR_ENH_SAFETY)
+	int err;
+
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!atomic_test_bit(hf->flags, BT_HFP_HF_FLAG_CONNECTED)) {
+		LOG_ERR("SLC is not established on %p", hf);
+		return -ENOTCONN;
+	}
+
+	if (!((hf->hf_ind & BIT(HFP_HF_ENHANCED_SAFETY_IND)) &&
+		(hf->ag_ind & BIT(HFP_HF_ENHANCED_SAFETY_IND)))) {
+		LOG_ERR("The indicator is unsupported");
+		return -ENOTSUP;
+	}
+
+	if (!(hf->ind_enable & BIT(HFP_HF_ENHANCED_SAFETY_IND))) {
+		LOG_ERR("The indicator is disabled");
+		return -EINVAL;
+	}
+
+	err = hfp_hf_send_cmd(hf, NULL, biev_enh_safety_finish, "AT+BIEV=%d,%d",
+		HFP_HF_ENHANCED_SAFETY_IND, enable ? 1 : 0);
+	if (err < 0) {
+		LOG_ERR("Fail to transfer enhanced safety value on %p", hf);
+	}
+
+	return err;
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_HF_INDICATOR_ENH_SAFETY */
+}
+
+#if defined(CONFIG_BT_HFP_HF_HF_INDICATOR_BATTERY)
+static int biev_battery_finish(struct at_client *hf_at,
+		   enum at_result result, enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("AT+BIEV (result %d) on %p", result, hf);
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_HF_INDICATOR_BATTERY */
+
+int bt_hfp_hf_battery(struct bt_hfp_hf *hf, uint8_t level)
+{
+#if defined(CONFIG_BT_HFP_HF_HF_INDICATOR_BATTERY)
+	int err;
+
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!atomic_test_bit(hf->flags, BT_HFP_HF_FLAG_CONNECTED)) {
+		LOG_ERR("SLC is not established on %p", hf);
+		return -ENOTCONN;
+	}
+
+	if (!((hf->hf_ind & BIT(HFP_HF_BATTERY_LEVEL_IND)) &&
+		(hf->ag_ind & BIT(HFP_HF_BATTERY_LEVEL_IND)))) {
+		LOG_ERR("The indicator is unsupported");
+		return -ENOTSUP;
+	}
+
+	if (!(hf->ind_enable & BIT(HFP_HF_BATTERY_LEVEL_IND))) {
+		LOG_ERR("The indicator is disabled");
+		return -EINVAL;
+	}
+
+	if (!IS_VALID_BATTERY_LEVEL(level)) {
+		LOG_ERR("Invalid battery level %d", level);
+		return -EINVAL;
+	}
+
+	err = hfp_hf_send_cmd(hf, NULL, biev_battery_finish, "AT+BIEV=%d,%d",
+		HFP_HF_BATTERY_LEVEL_IND, level);
+	if (err < 0) {
+		LOG_ERR("Fail to transfer remaining battery level on %p", hf);
+	}
+
+	return err;
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_HF_INDICATOR_BATTERY */
+}
+
+static int ata_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("ATA (result %d) on %p", result, hf);
+
+	return 0;
+}
+
+static int btrh_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("AT+BTRH (result %d) on %p", result, hf);
+
+	return 0;
+}
+
+int bt_hfp_hf_accept(struct bt_hfp_hf_call *call)
+{
+	int err;
+	struct bt_hfp_hf *hf;
+	int count;
+
+	LOG_DBG("");
+
+	if (!call) {
+		LOG_ERR("Invalid call");
+		return -EINVAL;
+	}
+
+	hf = call->hf;
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_IN_USING)) {
+		LOG_ERR("No valid call");
+		return -EINVAL;
+	}
+
+	count = get_using_call_count(call->hf);
+	if (count > 1) {
+		LOG_ERR("Unsupported 3Way call");
+		return -EINVAL;
+	}
+
+	if (atomic_get(call->state) == BT_HFP_HF_CALL_STATE_WAITING) {
+		err = hfp_hf_send_cmd(hf, NULL, ata_finish, "ATA");
+		if (err < 0) {
+			LOG_ERR("Fail to accept the incoming call on %p", hf);
+		}
+		return err;
+	}
+
+	if (atomic_test_bit(call->flags, BT_HFP_HF_CALL_INCOMING_HELD) &&
+		(atomic_get(call->state) == BT_HFP_HF_CALL_STATE_ACTIVE)) {
+		err = hfp_hf_send_cmd(hf, NULL, btrh_finish, "AT+BTRH=%d",
+			BT_HFP_BTRH_ACCEPTED);
+		if (err < 0) {
+			LOG_ERR("Fail to accept the held incoming call on %p", hf);
+		}
+		return err;
+	}
+
+	return -EINVAL;
+}
+
+static int chup_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("AT+CHUP (result %d) on %p", result, hf);
+
+	return 0;
+}
+
+int bt_hfp_hf_reject(struct bt_hfp_hf_call *call)
+{
+	int err;
+	struct bt_hfp_hf *hf;
+	int count;
+
+	LOG_DBG("");
+
+	if (!call) {
+		LOG_ERR("Invalid call");
+		return -EINVAL;
+	}
+
+	hf = call->hf;
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_IN_USING)) {
+		LOG_ERR("No valid call");
+		return -EINVAL;
+	}
+
+	count = get_using_call_count(call->hf);
+	if (count > 1) {
+		LOG_ERR("Unsupported 3Way call");
+		return -EINVAL;
+	}
+
+	if (!(hf->ag_features & BT_HFP_AG_FEATURE_REJECT_CALL)) {
+		LOG_ERR("AG has not ability to reject call");
+		return -ENOTSUP;
+	}
+
+	if (atomic_get(call->state) == BT_HFP_HF_CALL_STATE_WAITING) {
+		err = hfp_hf_send_cmd(hf, NULL, chup_finish, "AT+CHUP");
+		if (err < 0) {
+			LOG_ERR("Fail to reject the incoming call on %p", hf);
+		}
+		return err;
+	}
+
+	if (atomic_test_bit(call->flags, BT_HFP_HF_CALL_INCOMING_HELD) &&
+		(atomic_get(call->state) == BT_HFP_HF_CALL_STATE_ACTIVE)) {
+		err = hfp_hf_send_cmd(hf, NULL, btrh_finish, "AT+BTRH=%d",
+			BT_HFP_BTRH_REJECTED);
+		if (err < 0) {
+			LOG_ERR("Fail to reject the held incoming call on %p", hf);
+		}
+		return err;
+	}
+
+	return -EINVAL;
+}
+
+int bt_hfp_hf_terminate(struct bt_hfp_hf_call *call)
+{
+	int err;
+	struct bt_hfp_hf *hf;
+	int count;
+
+	LOG_DBG("");
+
+	if (!call) {
+		LOG_ERR("Invalid call");
+		return -EINVAL;
+	}
+
+	hf = call->hf;
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_IN_USING)) {
+		LOG_ERR("No valid call");
+		return -EINVAL;
+	}
+
+	count = get_using_call_count(call->hf);
+	if (count > 1) {
+		LOG_ERR("Unsupported 3Way call");
+		return -EINVAL;
+	}
+
+	if (atomic_get(call->state) == BT_HFP_HF_CALL_STATE_HELD) {
+		LOG_ERR("Held call cannot be terminated");
+		return -EINVAL;
+	}
+
+	err = hfp_hf_send_cmd(hf, NULL, chup_finish, "AT+CHUP");
+	if (err < 0) {
+		LOG_ERR("Fail to terminate the none held call on %p", hf);
+	}
+
+	return err;
+}
+
+int bt_hfp_hf_hold_incoming(struct bt_hfp_hf_call *call)
+{
+	int err;
+	struct bt_hfp_hf *hf;
+	int count;
+
+	LOG_DBG("");
+
+	if (!call) {
+		LOG_ERR("Invalid call");
+		return -EINVAL;
+	}
+
+	hf = call->hf;
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!atomic_test_bit(call->flags, BT_HFP_HF_CALL_IN_USING)) {
+		LOG_ERR("No valid call");
+		return -EINVAL;
+	}
+
+	count = get_using_call_count(call->hf);
+	if (count > 1) {
+		LOG_ERR("Unsupported 3Way call");
+		return -EINVAL;
+	}
+
+	if (!(atomic_get(call->state) == BT_HFP_HF_CALL_STATE_WAITING)) {
+		LOG_ERR("No incoming call setup in progress");
+		return -EINVAL;
+	}
+
+	err = hfp_hf_send_cmd(hf, NULL, btrh_finish, "AT+BTRH=%d",
+		BT_HFP_BTRH_ON_HOLD);
+	if (err < 0) {
+		LOG_ERR("Fail to hold the incoming call on %p", hf);
+	}
+
+	return err;
+}
+
+static int query_btrh_handle(struct at_client *hf_at)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	int err;
+	struct bt_hfp_hf_call *call;
+	uint32_t value;
+
+	err = at_get_number(hf_at, &value);
+	if (err < 0) {
+		LOG_ERR("Cannot get value");
+		return err;
+	}
+
+	if (value) {
+		LOG_ERR("Only support value 0");
+		return 0;
+	}
+
+	call = get_call_with_flag(hf, BT_HFP_HF_CALL_INCOMING_HELD);
+	if (!call) {
+		LOG_ERR("Held incoming call is not found");
+		return -EINVAL;
+	}
+
+	if (bt_hf->incoming_held) {
+		bt_hf->incoming_held(call);
+	}
+
+	return 0;
+}
+
+static int query_btrh_resp(struct at_client *hf_at, struct net_buf *buf)
+{
+	int err;
+
+	err = at_parse_cmd_input(hf_at, buf, "BTRH", query_btrh_handle,
+				 AT_CMD_TYPE_NORMAL);
+	if (err < 0) {
+		LOG_ERR("Error parsing CMD input");
+		hf_slc_error(hf_at);
+	}
+
+	return 0;
+}
+
+static int query_btrh_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("AT+BTRH? (result %d) on %p", result, hf);
+
+	return 0;
+}
+
+int bt_hfp_hf_query_respond_hold_status(struct bt_hfp_hf *hf)
+{
+	int err;
+
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	err = hfp_hf_send_cmd(hf, query_btrh_resp, query_btrh_finish, "AT+BTRH?");
+	if (err < 0) {
+		LOG_ERR("Fail to query respond and hold status of AG on %p", hf);
+	}
+
+	return err;
+}
+
+static int bt_hfp_ag_get_cme_err(enum at_cme cme_err)
+{
+	int err;
+
+	switch (cme_err) {
+	case CME_ERROR_OPERATION_NOT_SUPPORTED:
+		err = -EOPNOTSUPP;
+		break;
+	case CME_ERROR_AG_FAILURE:
+		err = -EFAULT;
+		break;
+	case CME_ERROR_MEMORY_FAILURE:
+		err = -ENOSR;
+		break;
+	case CME_ERROR_MEMORY_FULL:
+		err = -ENOMEM;
+		break;
+	case CME_ERROR_DIAL_STRING_TO_LONG:
+		err = -ENAMETOOLONG;
+		break;
+	case CME_ERROR_INVALID_INDEX:
+		err = -EINVAL;
+		break;
+	case CME_ERROR_OPERATION_NOT_ALLOWED:
+		err = -ENOTSUP;
+		break;
+	case CME_ERROR_NO_CONNECTION_TO_PHONE:
+		err = -ENOTCONN;
+		break;
+	default:
+		err = -ENOTSUP;
+		break;
+	}
+
+	return err;
+}
+
+static int atd_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	int err;
+	struct bt_hfp_hf_call *call;
+
+	LOG_DBG("ATD (result %d) on %p", result, hf);
+
+	if (result == AT_RESULT_CME_ERROR) {
+		err = bt_hfp_ag_get_cme_err(cme_err);
+	} else if (result == AT_RESULT_ERROR) {
+		err = -ENOTSUP;
+	} else {
+		err = 0;
+	}
+
+	call = get_call_with_state(hf, BT_HFP_HF_CALL_STATE_OUTGOING);
+	if (!call) {
+		return -EINVAL;
+	}
+
+	if (err) {
+		free_call(call);
+	}
+
+	if (bt_hf && bt_hf->dialing) {
+		bt_hf->dialing(hf, err);
+	}
+	return 0;
+}
+
+int bt_hfp_hf_number_call(struct bt_hfp_hf *hf, const char *number)
+{
+	struct bt_hfp_hf_call *call;
+	int err;
+
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	call = get_dialing_call(hf);
+	if (call) {
+		LOG_ERR("There is a call in alerting or waiting");
+		return -EBUSY;
+	}
+
+	call = get_new_call(hf);
+	if (!call) {
+		LOG_ERR("Not available call object");
+		return -ENOMEM;
+	}
+
+	hf_call_state_update(call, BT_HFP_HF_CALL_STATE_OUTGOING);
+
+	err = hfp_hf_send_cmd(hf, NULL, atd_finish, "ATD%s", number);
+	if (err < 0) {
+		LOG_ERR("Fail to start phone number call on %p", hf);
+	}
+
+	return err;
+}
+
+int bt_hfp_hf_memory_dial(struct bt_hfp_hf *hf, const char *location)
+{
+	struct bt_hfp_hf_call *call;
+	int err;
+
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	call = get_dialing_call(hf);
+	if (call) {
+		LOG_ERR("There is a call in alerting or waiting");
+		return -EBUSY;
+	}
+
+	call = get_new_call(hf);
+	if (!call) {
+		LOG_ERR("Not available call object");
+		return -ENOMEM;
+	}
+
+	hf_call_state_update(call, BT_HFP_HF_CALL_STATE_OUTGOING);
+
+	err = hfp_hf_send_cmd(hf, NULL, atd_finish, "ATD>%s", location);
+	if (err < 0) {
+		LOG_ERR("Fail to last number re-Dial on %p", hf);
+	}
+
+	return err;
+}
+
+static int bldn_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	int err;
+	struct bt_hfp_hf_call *call;
+
+	LOG_DBG("AT+BLDN (result %d) on %p", result, hf);
+
+	if (result == AT_RESULT_CME_ERROR) {
+		err = bt_hfp_ag_get_cme_err(cme_err);
+	} else if (result == AT_RESULT_ERROR) {
+		err = -ENOTSUP;
+	} else {
+		err = 0;
+	}
+
+	call = get_call_with_state(hf, BT_HFP_HF_CALL_STATE_OUTGOING);
+	if (!call) {
+		return -EINVAL;
+	}
+
+	if (err) {
+		free_call(call);
+	}
+
+	if (bt_hf && bt_hf->dialing) {
+		bt_hf->dialing(hf, err);
+	}
+	return 0;
+}
+
+int bt_hfp_hf_redial(struct bt_hfp_hf *hf)
+{
+	struct bt_hfp_hf_call *call;
+	int err;
+
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	call = get_dialing_call(hf);
+	if (call) {
+		LOG_ERR("There is a call in alerting or waiting");
+		return -EBUSY;
+	}
+
+	call = get_new_call(hf);
+	if (!call) {
+		LOG_ERR("Not available call object");
+		return -ENOMEM;
+	}
+
+	hf_call_state_update(call, BT_HFP_HF_CALL_STATE_OUTGOING);
+
+	err = hfp_hf_send_cmd(hf, NULL, bldn_finish, "AT+BLDN");
+	if (err < 0) {
+		LOG_ERR("Fail to start memory dialing on %p", hf);
+	}
+
+	return err;
+}
+
+#if defined(CONFIG_BT_HFP_HF_CODEC_NEG)
+static int bcc_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("BCC (result %d) on %p", result, hf);
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_CODEC_NEG */
+
+int bt_hfp_hf_audio_connect(struct bt_hfp_hf *hf)
+{
+#if defined(CONFIG_BT_HFP_HF_CODEC_NEG)
+	int err;
+
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (hf->chan.sco) {
+		LOG_ERR("Audio conenction has been connected");
+		return -ECONNREFUSED;
+	}
+
+	err = hfp_hf_send_cmd(hf, NULL, bcc_finish, "AT+BCC");
+	if (err < 0) {
+		LOG_ERR("Fail to setup audio connection on %p", hf);
+	}
+
+	return err;
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_CODEC_NEG */
+}
+
+#if defined(CONFIG_BT_HFP_HF_CODEC_NEG)
+static int bcs_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("BCS (result %d) on %p", result, hf);
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_CODEC_NEG */
+
+int bt_hfp_hf_select_codec(struct bt_hfp_hf *hf, uint8_t codec_id)
+{
+#if defined(CONFIG_BT_HFP_HF_CODEC_NEG)
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!(hf->hf_codec_ids & BIT(codec_id))) {
+		LOG_ERR("Codec ID is unsupported");
+		return -ENOTSUP;
+	}
+
+	if (!atomic_test_and_clear_bit(hf->flags, BT_HFP_HF_FLAG_CODEC_CONN)) {
+		LOG_ERR("Invalid context");
+		return -ESRCH;
+	}
+
+	return hfp_hf_send_cmd(hf, NULL, bcs_finish, "AT+BCS=%d", codec_id);
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_CODEC_NEG */
+}
+
+#if defined(CONFIG_BT_HFP_HF_CODEC_NEG)
+static int bac_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("BAC (result %d) on %p", result, hf);
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_CODEC_NEG */
+
+int bt_hfp_hf_set_codecs(struct bt_hfp_hf *hf, uint8_t codec_ids)
+{
+#if defined(CONFIG_BT_HFP_HF_CODEC_NEG)
+	char ids[sizeof(hf->hf_codec_ids)*2*8 + 1];
+
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (codec_ids & BT_HFP_HF_CODEC_CVSD) {
+		LOG_ERR("CVSD should be supported");
+		return -EINVAL;
+	}
+
+	atomic_clear_bit(hf->flags, BT_HFP_HF_FLAG_CODEC_CONN);
+	hf->hf_codec_ids = codec_ids;
+
+	get_codec_ids(hf, &ids[0], ARRAY_SIZE(ids));
+	return hfp_hf_send_cmd(hf, NULL, bac_finish, "AT+BAC=%s", ids);
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_CODEC_NEG */
+}
+
+#if defined(CONFIG_BT_HFP_HF_ECNR)
+static int nrec_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+	int err;
+
+	LOG_DBG("AT+NREC=0 (result %d) on %p", result, hf);
+
+	if (result == AT_RESULT_CME_ERROR) {
+		err = bt_hfp_ag_get_cme_err(cme_err);
+	} else if (result == AT_RESULT_ERROR) {
+		err = -ENOTSUP;
+	} else {
+		err = 0;
+	}
+
+	if (bt_hf && bt_hf->ecnr_turn_off) {
+		bt_hf->ecnr_turn_off(hf, err);
+	}
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_ECNR */
+
+int bt_hfp_hf_turn_off_ecnr(struct bt_hfp_hf *hf)
+{
+#if defined(CONFIG_BT_HFP_HF_ECNR)
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!(hf->ag_features & BT_HFP_AG_FEATURE_ECNR)) {
+		LOG_ERR("EC and/or NR functions is unsupported by AG");
+		return -ENOTSUP;
+	}
+
+	if (hf->chan.sco) {
+		LOG_ERR("Audio conenction has been connected");
+		return -EBUSY;
+	}
+
+	return hfp_hf_send_cmd(hf, NULL, nrec_finish, "AT+NREC=0");
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_ECNR */
+}
+
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+static int ccwa_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("AT+CCWA (result %d) on %p", result, hf);
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+
+int bt_hfp_hf_call_waiting_notify(struct bt_hfp_hf *hf, bool enable)
+{
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!(hf->ag_features & BT_HFP_AG_FEATURE_3WAY_CALL)) {
+		LOG_ERR("Three-way calling is unsupported by AG");
+		return -ENOTSUP;
+	}
+
+	return hfp_hf_send_cmd(hf, NULL, ccwa_finish, "AT+CCWA=%d", enable ? 1 : 0);
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+}
+
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+static int chld_release_all_held_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("AT+CHLD=0 (result %d) on %p", result, hf);
+
+	k_work_reschedule(&hf->deferred_work, K_MSEC(HF_ENHANCED_CALL_STATUS_TIMEOUT));
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+
+int bt_hfp_hf_release_all_held(struct bt_hfp_hf *hf)
+{
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!(hf->ag_features & BT_HFP_AG_FEATURE_3WAY_CALL)) {
+		LOG_ERR("Three-way calling is unsupported by AG");
+		return -ENOTSUP;
+	}
+
+	if (!(hf->chld_features & BIT(BT_HFP_CHLD_RELEASE_ALL))) {
+		LOG_ERR("Releasing all held calls is unsupported by AG");
+		return -ENOTSUP;
+	}
+
+	return hfp_hf_send_cmd(hf, NULL, chld_release_all_held_finish, "AT+CHLD=0");
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+}
+
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+static int chld_set_udub_finish(struct at_client *hf_at, enum at_result result,
+		   enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("AT+CHLD=0 (result %d) on %p", result, hf);
+
+	k_work_reschedule(&hf->deferred_work, K_MSEC(HF_ENHANCED_CALL_STATUS_TIMEOUT));
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+
+int bt_hfp_hf_set_udub(struct bt_hfp_hf *hf)
+{
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
 
-	return 0;
+	if (!(hf->ag_features & BT_HFP_AG_FEATURE_3WAY_CALL)) {
+		LOG_ERR("Three-way calling is unsupported by AG");
+		return -ENOTSUP;
+	}
+
+	if (!(hf->chld_features & BIT(BT_HFP_CHLD_RELEASE_ALL))) {
+		LOG_ERR("UDUB is unsupported by AG");
+		return -ENOTSUP;
+	}
+
+	return hfp_hf_send_cmd(hf, NULL, chld_set_udub_finish, "AT+CHLD=0");
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
 }
 
-int cind_status_finish(struct at_client *hf_at, enum at_result result,
-		       enum at_cme cme_err)
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+static int chld_release_active_accept_other_finish(struct at_client *hf_at,
+		   enum at_result result, enum at_cme cme_err)
 {
 	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
-	int err;
 
-	if (result != AT_RESULT_OK) {
-		LOG_ERR("SLC Connection ERROR in response");
-		hf_slc_error(hf_at);
-		return -EINVAL;
+	LOG_DBG("AT+CHLD=1 (result %d) on %p", result, hf);
+
+	k_work_reschedule(&hf->deferred_work, K_MSEC(HF_ENHANCED_CALL_STATUS_TIMEOUT));
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+
+int bt_hfp_hf_release_active_accept_other(struct bt_hfp_hf *hf)
+{
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
 	}
 
-	at_register_unsolicited(hf_at, unsolicited_cb);
-	err = hfp_hf_send_cmd(hf, NULL, cmer_finish, "AT+CMER=3,0,0,1");
-	if (err < 0) {
-		hf_slc_error(hf_at);
-		return err;
+	if (!(hf->ag_features & BT_HFP_AG_FEATURE_3WAY_CALL)) {
+		LOG_ERR("Three-way calling is unsupported by AG");
+		return -ENOTSUP;
 	}
 
+	return hfp_hf_send_cmd(hf, NULL, chld_release_active_accept_other_finish,
+	    "AT+CHLD=1");
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+}
+
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+static int chld_hold_active_accept_other_finish(struct at_client *hf_at,
+		   enum at_result result, enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("AT+CHLD=2 (result %d) on %p", result, hf);
+
+	k_work_reschedule(&hf->deferred_work, K_MSEC(HF_ENHANCED_CALL_STATUS_TIMEOUT));
+
 	return 0;
 }
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+
+int bt_hfp_hf_hold_active_accept_other(struct bt_hfp_hf *hf)
+{
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!(hf->ag_features & BT_HFP_AG_FEATURE_3WAY_CALL)) {
+		LOG_ERR("Three-way calling is unsupported by AG");
+		return -ENOTSUP;
+	}
+
+	return hfp_hf_send_cmd(hf, NULL, chld_hold_active_accept_other_finish,
+	    "AT+CHLD=2");
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+}
 
-int cind_finish(struct at_client *hf_at, enum at_result result,
-		enum at_cme cme_err)
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+static int chld_join_conversation_finish(struct at_client *hf_at,
+		   enum at_result result, enum at_cme cme_err)
 {
 	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
-	int err;
 
-	if (result != AT_RESULT_OK) {
-		LOG_ERR("SLC Connection ERROR in response");
-		hf_slc_error(hf_at);
-		return -EINVAL;
+	LOG_DBG("AT+CHLD=3 (result %d) on %p", result, hf);
+
+	k_work_reschedule(&hf->deferred_work, K_MSEC(HF_ENHANCED_CALL_STATUS_TIMEOUT));
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+
+int bt_hfp_hf_join_conversation(struct bt_hfp_hf *hf)
+{
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
 	}
 
-	err = hfp_hf_send_cmd(hf, cind_status_resp, cind_status_finish,
-			      "AT+CIND?");
-	if (err < 0) {
-		hf_slc_error(hf_at);
-		return err;
+	if (!(hf->ag_features & BT_HFP_AG_FEATURE_3WAY_CALL)) {
+		LOG_ERR("Three-way calling is unsupported by AG");
+		return -ENOTSUP;
+	}
+
+	if (!(hf->chld_features & BIT(BT_HFP_CALL_ACTIVE_HELD))) {
+		LOG_ERR("Adding a held call to the conversation is unsupported by AG");
+		return -ENOTSUP;
 	}
 
+	return hfp_hf_send_cmd(hf, NULL, chld_join_conversation_finish,
+	    "AT+CHLD=3");
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+}
+
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+static int chld_explicit_call_transfer_finish(struct at_client *hf_at,
+		   enum at_result result, enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("AT+CHLD=4 (result %d) on %p", result, hf);
+
+	k_work_reschedule(&hf->deferred_work, K_MSEC(HF_ENHANCED_CALL_STATUS_TIMEOUT));
+
 	return 0;
 }
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+
+int bt_hfp_hf_explicit_call_transfer(struct bt_hfp_hf *hf)
+{
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+	LOG_DBG("");
+
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!(hf->ag_features & BT_HFP_AG_FEATURE_3WAY_CALL)) {
+		LOG_ERR("Three-way calling is unsupported by AG");
+		return -ENOTSUP;
+	}
+
+	if (!(hf->chld_features & BIT(BT_HFP_CALL_QUITE))) {
+		LOG_ERR("Expliciting Call Transfer is unsupported by AG");
+		return -ENOTSUP;
+	}
+
+	return hfp_hf_send_cmd(hf, NULL, chld_explicit_call_transfer_finish,
+	    "AT+CHLD=4");
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+}
 
-int brsf_finish(struct at_client *hf_at, enum at_result result,
-		enum at_cme cme_err)
+#if defined(CONFIG_BT_HFP_HF_ECC)
+static int chld_release_specified_call_finish(struct at_client *hf_at,
+		   enum at_result result, enum at_cme cme_err)
 {
 	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
-	int err;
 
-	if (result != AT_RESULT_OK) {
-		LOG_ERR("SLC Connection ERROR in response");
-		hf_slc_error(hf_at);
-		return -EINVAL;
+	LOG_DBG("AT+CHLD=1<idx> (result %d) on %p", result, hf);
+
+	k_work_reschedule(&hf->deferred_work, K_MSEC(HF_ENHANCED_CALL_STATUS_TIMEOUT));
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_ECC */
+
+int bt_hfp_hf_release_specified_call(struct bt_hfp_hf_call *call)
+{
+#if defined(CONFIG_BT_HFP_HF_ECC)
+	struct bt_hfp_hf *hf;
+
+	LOG_DBG("");
+
+	if (!call) {
+		LOG_ERR("Invalid call");
+		return -ENOTCONN;
 	}
 
-	err = hfp_hf_send_cmd(hf, cind_resp, cind_finish, "AT+CIND=?");
-	if (err < 0) {
-		hf_slc_error(hf_at);
-		return err;
+	hf = call->hf;
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!(hf->ag_features & BT_HFP_AG_FEATURE_3WAY_CALL)) {
+		LOG_ERR("Three-way calling is unsupported by AG");
+		return -ENOTSUP;
+	}
+
+	if (!(hf->ag_features & BT_HFP_AG_FEATURE_ECC)) {
+		LOG_ERR("Enhanced Call Control is unsupported by AG");
+		return -ENOTSUP;
+	}
+
+	if (!(hf->hf_features & BT_HFP_HF_FEATURE_ECC)) {
+		LOG_ERR("Enhanced Call Control is unsupported by HF");
+		return -ENOTSUP;
+	}
+
+	if (!(hf->chld_features & BIT(BT_HFP_CALL_RELEASE_SPECIFIED_ACTIVE))) {
+		LOG_ERR("Releasing a specific active call is unsupported by AG");
+		return -ENOTSUP;
+	}
+
+	if (!call->index) {
+		LOG_ERR("Invalid call index");
+		return -EINVAL;
 	}
 
+	return hfp_hf_send_cmd(hf, NULL, chld_release_specified_call_finish,
+	    "AT+CHLD=1%d", call->index);
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_ECC */
+}
+
+#if defined(CONFIG_BT_HFP_HF_ECC)
+static int chld_private_consultation_mode_finish(struct at_client *hf_at,
+		   enum at_result result, enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("AT+CHLD=2<idx> (result %d) on %p", result, hf);
+
+	k_work_reschedule(&hf->deferred_work, K_MSEC(HF_ENHANCED_CALL_STATUS_TIMEOUT));
+
 	return 0;
 }
+#endif /* CONFIG_BT_HFP_HF_ECC */
 
-int hf_slc_establish(struct bt_hfp_hf *hf)
+int bt_hfp_hf_private_consultation_mode(struct bt_hfp_hf_call *call)
 {
-	int err;
+#if defined(CONFIG_BT_HFP_HF_ECC)
+	struct bt_hfp_hf *hf;
 
 	LOG_DBG("");
 
-	err = hfp_hf_send_cmd(hf, brsf_resp, brsf_finish, "AT+BRSF=%u",
-			      hf->hf_features);
-	if (err < 0) {
-		hf_slc_error(&hf->at);
-		return err;
+	if (!call) {
+		LOG_ERR("Invalid call");
+		return -ENOTCONN;
+	}
+
+	hf = call->hf;
+	if (!hf) {
+		LOG_ERR("No HF connection found");
+		return -ENOTCONN;
+	}
+
+	if (!(hf->ag_features & BT_HFP_AG_FEATURE_3WAY_CALL)) {
+		LOG_ERR("Three-way calling is unsupported by AG");
+		return -ENOTSUP;
+	}
+
+	if (!(hf->ag_features & BT_HFP_AG_FEATURE_ECC)) {
+		LOG_ERR("Enhanced Call Control is unsupported by AG");
+		return -ENOTSUP;
+	}
+
+	if (!(hf->hf_features & BT_HFP_HF_FEATURE_ECC)) {
+		LOG_ERR("Enhanced Call Control is unsupported by HF");
+		return -ENOTSUP;
+	}
+
+	if (!(hf->chld_features & BIT(BT_HFP_CALL_PRIVATE_CNLTN_MODE))) {
+		LOG_ERR("Private Consultation Mode is unsupported by AG");
+		return -ENOTSUP;
+	}
+
+	if (!call->index) {
+		LOG_ERR("Invalid call index");
+		return -EINVAL;
+	}
+
+	return hfp_hf_send_cmd(hf, NULL, chld_private_consultation_mode_finish,
+			       "AT+CHLD=2%d", call->index);
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_ECC */
+}
+
+#if defined(CONFIG_BT_HFP_HF_VOICE_RECG)
+static int bvra_1_finish(struct at_client *hf_at,
+		   enum at_result result, enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("AT+BVRA=1 (result %d) on %p", result, hf);
+
+	if (result == AT_RESULT_OK) {
+		if (!atomic_test_and_set_bit(hf->flags, BT_HFP_HF_FLAG_VRE_ACTIVATE)) {
+			if (bt_hf->voice_recognition) {
+				bt_hf->voice_recognition(hf, true);
+			}
+		}
 	}
 
 	return 0;
 }
 
-static struct bt_hfp_hf *bt_hfp_hf_lookup_bt_conn(struct bt_conn *conn)
+static int bvra_0_finish(struct at_client *hf_at,
+		   enum at_result result, enum at_cme cme_err)
 {
-	int i;
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
 
-	for (i = 0; i < ARRAY_SIZE(bt_hfp_hf_pool); i++) {
-		struct bt_hfp_hf *hf = &bt_hfp_hf_pool[i];
+	LOG_DBG("AT+BVRA=0 (result %d) on %p", result, hf);
 
-		if (hf->acl == conn) {
-			return hf;
+	if (atomic_test_and_clear_bit(hf->flags, BT_HFP_HF_FLAG_VRE_ACTIVATE)) {
+		if (bt_hf->voice_recognition) {
+			bt_hf->voice_recognition(hf, false);
 		}
 	}
 
-	return NULL;
+	return 0;
 }
+#endif /* CONFIG_BT_HFP_HF_VOICE_RECG */
 
-int bt_hfp_hf_send_cmd(struct bt_conn *conn, enum bt_hfp_hf_at_cmd cmd)
+int bt_hfp_hf_voice_recognition(struct bt_hfp_hf *hf, bool activate)
 {
-	struct bt_hfp_hf *hf;
-	int err;
+#if defined(CONFIG_BT_HFP_HF_VOICE_RECG)
+	at_finish_cb_t finish;
 
 	LOG_DBG("");
 
-	if (!conn) {
-		LOG_ERR("Invalid connection");
+	if (!hf) {
+		LOG_ERR("No HF connection found");
 		return -ENOTCONN;
 	}
 
-	hf = bt_hfp_hf_lookup_bt_conn(conn);
+	if (!(hf->ag_features & BT_HFP_AG_FEATURE_VOICE_RECG)) {
+		LOG_ERR("Voice recognition is unsupported by AG");
+		return -ENOTSUP;
+	}
+
+	if (activate) {
+		finish = bvra_1_finish;
+	} else {
+		finish = bvra_0_finish;
+	}
+
+	return hfp_hf_send_cmd(hf, NULL, finish, "AT+BVRA=%d",
+		activate ? 1 : 0);
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_VOICE_RECG */
+}
+
+#if defined(CONFIG_BT_HFP_HF_ENH_VOICE_RECG)
+static int bvra_2_finish(struct at_client *hf_at,
+		   enum at_result result, enum at_cme cme_err)
+{
+	struct bt_hfp_hf *hf = CONTAINER_OF(hf_at, struct bt_hfp_hf, at);
+
+	LOG_DBG("AT+BVRA=2 (result %d) on %p", result, hf);
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_ENH_VOICE_RECG */
+
+int bt_hfp_hf_ready_to_accept_audio(struct bt_hfp_hf *hf)
+{
+#if defined(CONFIG_BT_HFP_HF_ENH_VOICE_RECG)
+	LOG_DBG("");
+
 	if (!hf) {
 		LOG_ERR("No HF connection found");
 		return -ENOTCONN;
 	}
 
-	switch (cmd) {
-	case BT_HFP_HF_ATA:
-		err = hfp_hf_send_cmd(hf, NULL, cmd_complete, "ATA");
-		if (err < 0) {
-			LOG_ERR("Failed ATA");
-			return err;
-		}
-		break;
-	case BT_HFP_HF_AT_CHUP:
-		err = hfp_hf_send_cmd(hf, NULL, cmd_complete, "AT+CHUP");
-		if (err < 0) {
-			LOG_ERR("Failed AT+CHUP");
-			return err;
-		}
-		break;
-	default:
-		LOG_ERR("Invalid AT Command");
+	if (!(hf->ag_features & BT_HFP_AG_FEATURE_VOICE_RECG)) {
+		LOG_ERR("Voice recognition is unsupported by AG");
+		return -ENOTSUP;
+	}
+
+	if (!atomic_test_bit(hf->flags, BT_HFP_HF_FLAG_VRE_ACTIVATE)) {
+		LOG_ERR("Voice recognition is not activated");
 		return -EINVAL;
 	}
 
-	return 0;
+	if (!hf->chan.sco) {
+		LOG_ERR("SCO channel is not ready");
+		return -ENOTCONN;
+	}
+
+	return hfp_hf_send_cmd(hf, NULL, bvra_2_finish, "AT+BVRA=2");
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_HFP_HF_ENH_VOICE_RECG */
 }
 
 static void hfp_hf_connected(struct bt_rfcomm_dlc *dlc)
@@ -694,21 +3919,27 @@ static void hfp_hf_connected(struct bt_rfcomm_dlc *dlc)
 static void hfp_hf_disconnected(struct bt_rfcomm_dlc *dlc)
 {
 	struct bt_hfp_hf *hf = CONTAINER_OF(dlc, struct bt_hfp_hf, rfcomm_dlc);
-	struct bt_conn *conn = hf->acl;
 
 	LOG_DBG("hf disconnected!");
 	if (bt_hf->disconnected) {
-		bt_hf->disconnected(conn);
+		bt_hf->disconnected(hf);
 	}
+
+	k_work_cancel(&hf->work);
+	k_work_cancel_delayable(&hf->deferred_work);
+	hf->acl = NULL;
 }
 
 static void hfp_hf_recv(struct bt_rfcomm_dlc *dlc, struct net_buf *buf)
 {
 	struct bt_hfp_hf *hf = CONTAINER_OF(dlc, struct bt_hfp_hf, rfcomm_dlc);
 
+	atomic_set_bit(hf->flags, BT_HFP_HF_FLAG_RX_ONGOING);
 	if (at_parse_input(&hf->at, buf) < 0) {
 		LOG_ERR("Parsing failed");
 	}
+	atomic_clear_bit(hf->flags, BT_HFP_HF_FLAG_RX_ONGOING);
+	k_work_submit(&hf->work);
 }
 
 static void hfp_hf_sent(struct bt_rfcomm_dlc *dlc, int err)
@@ -716,54 +3947,83 @@ static void hfp_hf_sent(struct bt_rfcomm_dlc *dlc, int err)
 	LOG_DBG("DLC %p sent cb (err %d)", dlc, err);
 }
 
-static int bt_hfp_hf_accept(struct bt_conn *conn, struct bt_rfcomm_dlc **dlc)
+static void bt_hf_work(struct k_work *work)
 {
-	int i;
+	struct bt_hfp_hf *hf = CONTAINER_OF(work, struct bt_hfp_hf, work);
+
+	hfp_hf_send_data(hf);
+}
+
+static struct bt_hfp_hf *hfp_hf_create(struct bt_conn *conn)
+{
+	size_t index;
 	static struct bt_rfcomm_dlc_ops ops = {
 		.connected = hfp_hf_connected,
 		.disconnected = hfp_hf_disconnected,
 		.recv = hfp_hf_recv,
 		.sent = hfp_hf_sent,
 	};
+	struct bt_hfp_hf *hf;
 
 	LOG_DBG("conn %p", conn);
 
-	for (i = 0; i < ARRAY_SIZE(bt_hfp_hf_pool); i++) {
-		struct bt_hfp_hf *hf = &bt_hfp_hf_pool[i];
-		int j;
+	index = (size_t)bt_conn_index(conn);
+	hf = &bt_hfp_hf_pool[index];
+	if (hf->acl) {
+		LOG_ERR("HF connection (%p) is established", conn);
+		return NULL;
+	}
 
-		if (hf->rfcomm_dlc.session) {
-			continue;
-		}
+	memset(hf, 0, sizeof(*hf));
 
-		hf->acl = conn;
-		hf->at.buf = hf->hf_buffer;
-		hf->at.buf_max_len = HF_MAX_BUF_LEN;
+	hf->acl = conn;
+	hf->at.buf = hf->hf_buffer;
+	hf->at.buf_max_len = HF_MAX_BUF_LEN;
 
-		hf->rfcomm_dlc.ops = &ops;
-		hf->rfcomm_dlc.mtu = BT_HFP_MAX_MTU;
+	hf->rfcomm_dlc.ops = &ops;
+	hf->rfcomm_dlc.mtu = BT_HFP_MAX_MTU;
 
-		*dlc = &hf->rfcomm_dlc;
+	/* Set the supported features*/
+	hf->hf_features = BT_HFP_HF_SUPPORTED_FEATURES;
 
-		/* Set the supported features*/
-		hf->hf_features = BT_HFP_HF_SUPPORTED_FEATURES;
+	/* Set supported codec ids */
+	hf->hf_codec_ids = BT_HFP_HF_SUPPORTED_CODEC_IDS;
 
-		for (j = 0; j < HF_MAX_AG_INDICATORS; j++) {
-			hf->ind_table[j] = -1;
-		}
+	k_fifo_init(&hf->tx_pending);
 
-		return 0;
+	k_work_init(&hf->work, bt_hf_work);
+
+	k_work_init_delayable(&hf->deferred_work, bt_hf_deferred_work);
+
+	for (index = 0; index < ARRAY_SIZE(hf->ind_table); index++) {
+		hf->ind_table[index] = -1;
+	}
+
+	return hf;
+}
+
+static int hfp_hf_accept(struct bt_conn *conn, struct bt_rfcomm_server *server,
+			 struct bt_rfcomm_dlc **dlc)
+{
+	struct bt_hfp_hf *hf;
+
+	hf = hfp_hf_create(conn);
+
+	if (!hf) {
+		return -ECONNREFUSED;
 	}
 
-	LOG_ERR("Unable to establish HF connection (%p)", conn);
+	*dlc = &hf->rfcomm_dlc;
 
-	return -ENOMEM;
+	return 0;
 }
 
 static void hfp_hf_sco_connected(struct bt_sco_chan *chan)
 {
+	struct bt_hfp_hf *hf = CONTAINER_OF(chan, struct bt_hfp_hf, chan);
+
 	if ((bt_hf != NULL) && (bt_hf->sco_connected)) {
-		bt_hf->sco_connected(chan->sco->sco.acl, chan->sco);
+		bt_hf->sco_connected(hf, chan->sco);
 	}
 }
 
@@ -777,42 +4037,34 @@ static void hfp_hf_sco_disconnected(struct bt_sco_chan *chan, uint8_t reason)
 static int bt_hfp_hf_sco_accept(const struct bt_sco_accept_info *info,
 		      struct bt_sco_chan **chan)
 {
-	int i;
 	static struct bt_sco_chan_ops ops = {
 		.connected = hfp_hf_sco_connected,
 		.disconnected = hfp_hf_sco_disconnected,
 	};
+	size_t index;
+	struct bt_hfp_hf *hf;
 
 	LOG_DBG("conn %p", info->acl);
 
-	for (i = 0; i < ARRAY_SIZE(bt_hfp_hf_pool); i++) {
-		struct bt_hfp_hf *hf = &bt_hfp_hf_pool[i];
-
-		if (NULL == hf->rfcomm_dlc.session) {
-			continue;
-		}
-
-		if (info->acl != hf->rfcomm_dlc.session->br_chan.chan.conn) {
-			continue;
-		}
-
-		hf->chan.ops = &ops;
-
-		*chan = &hf->chan;
-
-		return 0;
+	index = (size_t)bt_conn_index(info->acl);
+	hf = &bt_hfp_hf_pool[index];
+	if (hf->acl != info->acl) {
+		LOG_ERR("ACL %p of HF is unaligned with SCO's %p", hf->acl, info->acl);
+		return -EINVAL;
 	}
 
-	LOG_ERR("Unable to establish HF connection (%p)", info->acl);
+	hf->chan.ops = &ops;
+
+	*chan = &hf->chan;
 
-	return -ENOMEM;
+	return 0;
 }
 
 static void hfp_hf_init(void)
 {
 	static struct bt_rfcomm_server chan = {
 		.channel = BT_RFCOMM_CHAN_HFP_HF,
-		.accept = bt_hfp_hf_accept,
+		.accept = hfp_hf_accept,
 	};
 
 	bt_rfcomm_server_register(&chan);
@@ -843,3 +4095,43 @@ int bt_hfp_hf_register(struct bt_hfp_hf_cb *cb)
 
 	return 0;
 }
+
+int bt_hfp_hf_connect(struct bt_conn *conn, struct bt_hfp_hf **hf, uint8_t channel)
+{
+	struct bt_hfp_hf *new_hf;
+	int err;
+
+	if (!conn || !hf || !channel) {
+		return -EINVAL;
+	}
+
+	if (!bt_hf) {
+		return -EFAULT;
+	}
+
+	new_hf = hfp_hf_create(conn);
+	if (!new_hf) {
+		return -ECONNREFUSED;
+	}
+
+	err = bt_rfcomm_dlc_connect(conn, &new_hf->rfcomm_dlc, channel);
+	if (err != 0) {
+		(void)memset(new_hf, 0, sizeof(*new_hf));
+		*hf = NULL;
+	} else {
+		*hf = new_hf;
+	}
+
+	return err;
+}
+
+int bt_hfp_hf_disconnect(struct bt_hfp_hf *hf)
+{
+	LOG_DBG("");
+
+	if (!hf) {
+		return -EINVAL;
+	}
+
+	return bt_rfcomm_dlc_disconnect(&hf->rfcomm_dlc);
+}
diff --git a/subsys/bluetooth/host/classic/hfp_hf_internal.h b/subsys/bluetooth/host/classic/hfp_hf_internal.h
new file mode 100644
index 00000000000..caecc60dac9
--- /dev/null
+++ b/subsys/bluetooth/host/classic/hfp_hf_internal.h
@@ -0,0 +1,223 @@
+/** @file
+ *  @brief Internal APIs for Bluetooth Handsfree profile handling.
+ */
+
+/*
+ * Copyright (c) 2015-2016 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "hfp_internal.h"
+
+#if defined(CONFIG_BT_HFP_HF_CLI)
+#define BT_HFP_HF_FEATURE_CLI_ENABLE BT_HFP_HF_FEATURE_CLI
+#define BT_HFP_HF_SDP_FEATURE_CLI_ENABLE BT_HFP_HF_SDP_FEATURE_CLI
+#else
+#define BT_HFP_HF_FEATURE_CLI_ENABLE 0
+#define BT_HFP_HF_SDP_FEATURE_CLI_ENABLE 0
+#endif /* CONFIG_BT_HFP_HF_CLI */
+
+#if defined(CONFIG_BT_HFP_HF_VOLUME)
+#define BT_HFP_HF_FEATURE_VOLUME_ENABLE BT_HFP_HF_FEATURE_VOLUME
+#define BT_HFP_HF_SDP_FEATURE_VOLUME_ENABLE BT_HFP_HF_SDP_FEATURE_VOLUME
+#else
+#define BT_HFP_HF_FEATURE_VOLUME_ENABLE 0
+#define BT_HFP_HF_SDP_FEATURE_VOLUME_ENABLE 0
+#endif /* CONFIG_BT_HFP_HF_VOLUME */
+
+#if defined(CONFIG_BT_HFP_HF_CODEC_NEG)
+#define BT_HFP_HF_CODEC_NEG_ENABLE BT_HFP_HF_FEATURE_CODEC_NEG
+#else
+#define BT_HFP_HF_CODEC_NEG_ENABLE 0
+#endif /* CONFIG_BT_HFP_HF_CODEC_NEG */
+
+#if defined(CONFIG_BT_HFP_HF_ECNR)
+#define BT_HFP_HF_FEATURE_ECNR_ENABLE BT_HFP_HF_FEATURE_ECNR
+#define BT_HFP_HF_SDP_FEATURE_ECNR_ENABLE BT_HFP_HF_SDP_FEATURE_ECNR
+#else
+#define BT_HFP_HF_FEATURE_ECNR_ENABLE 0
+#define BT_HFP_HF_SDP_FEATURE_ECNR_ENABLE 0
+#endif /* CONFIG_BT_HFP_HF_CODEC_NEG */
+
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+#define BT_HFP_HF_FEATURE_3WAY_CALL_ENABLE BT_HFP_HF_FEATURE_3WAY_CALL
+#define BT_HFP_HF_SDP_FEATURE_3WAY_CALL_ENABLE BT_HFP_HF_SDP_FEATURE_3WAY_CALL
+#else
+#define BT_HFP_HF_FEATURE_3WAY_CALL_ENABLE 0
+#define BT_HFP_HF_SDP_FEATURE_3WAY_CALL_ENABLE 0
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+
+#if defined(CONFIG_BT_HFP_HF_ECS)
+#define BT_HFP_HF_FEATURE_ECS_ENABLE BT_HFP_HF_FEATURE_ECS
+#else
+#define BT_HFP_HF_FEATURE_ECS_ENABLE 0
+#endif /* CONFIG_BT_HFP_HF_ECS */
+
+#if defined(CONFIG_BT_HFP_HF_ECC)
+#define BT_HFP_HF_FEATURE_ECC_ENABLE BT_HFP_HF_FEATURE_ECC
+#else
+#define BT_HFP_HF_FEATURE_ECC_ENABLE 0
+#endif /* CONFIG_BT_HFP_HF_ECC */
+
+#if defined(CONFIG_BT_HFP_HF_VOICE_RECG)
+#define BT_HFP_HF_FEATURE_VOICE_RECG_ENABLE BT_HFP_HF_FEATURE_VOICE_RECG
+#define BT_HFP_HF_SDP_FEATURE_VOICE_RECG_ENABLE BT_HFP_HF_SDP_FEATURE_VOICE_RECG
+#else
+#define BT_HFP_HF_FEATURE_VOICE_RECG_ENABLE 0
+#define BT_HFP_HF_SDP_FEATURE_VOICE_RECG_ENABLE 0
+#endif /* CONFIG_BT_HFP_HF_VOICE_RECG */
+
+#if defined(CONFIG_BT_HFP_HF_ENH_VOICE_RECG)
+#define BT_HFP_HF_FEATURE_ENH_VOICE_RECG_ENABLE BT_HFP_HF_FEATURE_ENH_VOICE_RECG
+#define BT_HFP_HF_SDP_FEATURE_ENH_VOICE_RECG_ENABLE BT_HFP_HF_SDP_FEATURE_ENH_VOICE_RECG
+#else
+#define BT_HFP_HF_FEATURE_ENH_VOICE_RECG_ENABLE 0
+#define BT_HFP_HF_SDP_FEATURE_ENH_VOICE_RECG_ENABLE 0
+#endif /* CONFIG_BT_HFP_HF_ENH_VOICE_RECG */
+
+#if defined(CONFIG_BT_HFP_HF_VOICE_RECG_TEXT)
+#define BT_HFP_HF_FEATURE_VOICE_RECG_TEXT_ENABLE BT_HFP_HF_FEATURE_VOICE_RECG_TEXT
+#define BT_HFP_HF_SDP_FEATURE_VOICE_RECG_TEXT_ENABLE BT_HFP_HF_SDP_FEATURE_VOICE_RECG_TEXT
+#else
+#define BT_HFP_HF_FEATURE_VOICE_RECG_TEXT_ENABLE 0
+#define BT_HFP_HF_SDP_FEATURE_VOICE_RECG_TEXT_ENABLE 0
+#endif /* CONFIG_BT_HFP_HF_VOICE_RECG_TEXT */
+
+#if defined(CONFIG_BT_HFP_HF_HF_INDICATORS)
+#define BT_HFP_HF_FEATURE_HF_IND_ENABLE BT_HFP_HF_FEATURE_HF_IND
+#else
+#define BT_HFP_HF_FEATURE_HF_IND_ENABLE 0
+#endif /* CONFIG_BT_HFP_HF_HF_INDICATORS */
+
+/* HFP HF Supported features */
+#define BT_HFP_HF_SUPPORTED_FEATURES (\
+	BT_HFP_HF_FEATURE_CLI_ENABLE | \
+	BT_HFP_HF_SDP_FEATURE_VOLUME_ENABLE |\
+	BT_HFP_HF_CODEC_NEG_ENABLE | \
+	BT_HFP_HF_FEATURE_ECNR_ENABLE | \
+	BT_HFP_HF_FEATURE_3WAY_CALL_ENABLE | \
+	BT_HFP_HF_FEATURE_ECS_ENABLE | \
+	BT_HFP_HF_FEATURE_ECC_ENABLE | \
+	BT_HFP_HF_FEATURE_VOICE_RECG_ENABLE | \
+	BT_HFP_HF_FEATURE_ENH_VOICE_RECG_ENABLE | \
+	BT_HFP_HF_FEATURE_VOICE_RECG_TEXT_ENABLE | \
+	BT_HFP_HF_FEATURE_HF_IND_ENABLE)
+
+/* HFP HF Supported features in SDP */
+#define BT_HFP_HF_SDP_SUPPORTED_FEATURES (\
+	BT_HFP_HF_SDP_FEATURE_CLI_ENABLE | \
+	BT_HFP_HF_SDP_FEATURE_VOLUME_ENABLE | \
+	BT_HFP_HF_SDP_FEATURE_ECNR_ENABLE | \
+	BT_HFP_HF_SDP_FEATURE_3WAY_CALL_ENABLE | \
+	BT_HFP_HF_SDP_FEATURE_VOICE_RECG_ENABLE | \
+	BT_HFP_HF_SDP_FEATURE_ENH_VOICE_RECG_ENABLE | \
+	BT_HFP_HF_SDP_FEATURE_VOICE_RECG_TEXT_ENABLE)
+
+#define BT_HFP_HF_CODEC_CVSD_MASK BIT(BT_HFP_HF_CODEC_CVSD)
+
+#if defined(CONFIG_BT_HFP_HF_CODEC_MSBC)
+#define BT_HFP_HF_CODEC_MSBC_ENABLE BIT(BT_HFP_HF_CODEC_MSBC)
+#else
+#define BT_HFP_HF_CODEC_MSBC_ENABLE 0
+#endif /* CONFIG_BT_HFP_HF_CODEC_MSBC */
+
+#if defined(CONFIG_BT_HFP_HF_CODEC_LC3_SWB)
+#define BT_HFP_HF_CODEC_LC3_SWB_ENABLE BIT(BT_HFP_HF_CODEC_LC3_SWB)
+#else
+#define BT_HFP_HF_CODEC_LC3_SWB_ENABLE 0
+#endif /* CONFIG_BT_HFP_HF_CODEC_LC3_SWB */
+
+/* HFP HF Supported Codec IDs*/
+#define BT_HFP_HF_SUPPORTED_CODEC_IDS \
+	BT_HFP_HF_CODEC_CVSD_MASK | \
+	BT_HFP_HF_CODEC_MSBC_ENABLE | \
+	BT_HFP_HF_CODEC_LC3_SWB_ENABLE
+
+/* bt_hfp_hf flags: the flags defined here represent hfp hf parameters */
+enum {
+	BT_HFP_HF_FLAG_CONNECTED,     /* HFP HF SLC Established */
+	BT_HFP_HF_FLAG_TX_ONGOING,    /* HFP HF TX is ongoing */
+	BT_HFP_HF_FLAG_RX_ONGOING,    /* HFP HF RX is ongoing */
+	BT_HFP_HF_FLAG_CODEC_CONN,    /* HFP HF codec connection setup */
+	BT_HFP_HF_FLAG_CLCC_PENDING,  /* HFP HF CLCC is pending */
+	BT_HFP_HF_FLAG_VRE_ACTIVATE,  /* VRE is activated */
+	BT_HFP_HF_FLAG_BINP,          /* +BINP result code is received */
+	/* Total number of flags - must be at the end of the enum */
+	BT_HFP_HF_NUM_FLAGS,
+};
+
+/* bt_hfp_hf_call flags: the flags defined here represent hfp hf call parameters */
+enum {
+	BT_HFP_HF_CALL_IN_USING,      /* Object is in using */
+	BT_HFP_HF_CALL_CLCC,          /* CLCC report received */
+	BT_HFP_HF_CALL_INCOMING,      /* Incoming call */
+	BT_HFP_HF_CALL_INCOMING_HELD, /* Incoming call held */
+	BT_HFP_HF_CALL_OUTGOING_3WAY, /* Outgoing 3 way call */
+	BT_HFP_HF_CALL_INCOMING_3WAY, /* Incoming 3 way call */
+
+	/* Total number of flags - must be at the end of the enum */
+	BT_HFP_HF_CALL_NUM_FLAGS,
+};
+
+/* bt_hfp_hf_call state: the flags defined here represent hfp hf call state parameters */
+enum {
+	/* Call state flags */
+	BT_HFP_HF_CALL_STATE_TERMINATE, /* Call terminate */
+	BT_HFP_HF_CALL_STATE_OUTGOING,  /* Call outgoing */
+	BT_HFP_HF_CALL_STATE_INCOMING,  /* Call incoming */
+	BT_HFP_HF_CALL_STATE_ALERTING,  /* Call alerting */
+	BT_HFP_HF_CALL_STATE_WAITING,   /* Call waiting */
+	BT_HFP_HF_CALL_STATE_ACTIVE,    /* Call active */
+	BT_HFP_HF_CALL_STATE_HELD,      /* Call held */
+
+	/* Total number of flags - must be at the end of the enum */
+	BT_HFP_HF_CALL_STATE_NUM_FLAGS,
+};
+
+struct bt_hfp_hf_call {
+	struct bt_hfp_hf *hf;
+	uint8_t index;
+
+	ATOMIC_DEFINE(flags, BT_HFP_HF_CALL_NUM_FLAGS);
+	ATOMIC_DEFINE(state, BT_HFP_HF_CALL_STATE_NUM_FLAGS);
+};
+
+struct bt_hfp_hf {
+	struct bt_rfcomm_dlc rfcomm_dlc;
+	/* ACL connection handle */
+	struct bt_conn *acl;
+	/* AT command sending queue */
+	at_finish_cb_t backup_finish;
+	struct k_fifo tx_pending;
+	/* SCO Channel */
+	struct bt_sco_chan chan;
+	char hf_buffer[HF_MAX_BUF_LEN];
+	struct at_client at;
+	uint32_t hf_features;
+	uint32_t ag_features;
+	uint8_t hf_codec_ids;
+	uint8_t vgm;
+	uint8_t vgs;
+	int8_t ind_table[HF_MAX_AG_INDICATORS];
+
+	uint32_t hf_ind;
+	uint32_t ag_ind;
+	uint32_t ind_enable;
+
+	/* AT command initialization indicator */
+	uint8_t cmd_init_seq;
+
+	/* The features supported by AT+CHLD */
+	uint32_t chld_features;
+
+	/* Worker for pending TX */
+	struct k_work work;
+
+	struct k_work_delayable deferred_work;
+
+	/* calls */
+	struct bt_hfp_hf_call calls[CONFIG_BT_HFP_HF_MAX_CALLS];
+
+	ATOMIC_DEFINE(flags, BT_HFP_HF_NUM_FLAGS);
+};
diff --git a/subsys/bluetooth/host/classic/hfp_internal.h b/subsys/bluetooth/host/classic/hfp_internal.h
index 11680718704..03a85e1a123 100644
--- a/subsys/bluetooth/host/classic/hfp_internal.h
+++ b/subsys/bluetooth/host/classic/hfp_internal.h
@@ -41,37 +41,130 @@
 #define BT_HFP_HF_FEATURE_ENH_VOICE_RECG  0x00000400 /* Enhanced Voice Recognition Status */
 #define BT_HFP_HF_FEATURE_VOICE_RECG_TEXT 0x00000800 /* Voice Recognition Text */
 
-/* HFP HF Supported features */
-#define BT_HFP_HF_SUPPORTED_FEATURES (BT_HFP_HF_FEATURE_CLI | BT_HFP_HF_FEATURE_VOLUME)
+/* HFP HF Features in SDP */
+#define BT_HFP_HF_SDP_FEATURE_ECNR            BIT(0) /* EC and/or NR function */
+#define BT_HFP_HF_SDP_FEATURE_3WAY_CALL       BIT(1) /* Three-way calling */
+#define BT_HFP_HF_SDP_FEATURE_CLI             BIT(2) /* CLI presentation */
+#define BT_HFP_HF_SDP_FEATURE_VOICE_RECG      BIT(3) /* Voice recognition */
+#define BT_HFP_HF_SDP_FEATURE_VOLUME          BIT(4) /* Remote volume control */
+#define BT_HFP_HF_SDP_FEATURE_WBS             BIT(5) /* Wide Band Speech */
+#define BT_HFP_HF_SDP_FEATURE_ENH_VOICE_RECG  BIT(6) /* Enhanced Voice Recognition Status */
+#define BT_HFP_HF_SDP_FEATURE_VOICE_RECG_TEXT BIT(7) /* Voice Recognition Text */
+#define BT_HFP_HF_SDP_FEATURE_SUPER_WBS       BIT(7) /* Super Wide Band Speech */
 
+/* HFP AG Features in SDP */
+#define BT_HFP_AG_SDP_FEATURE_3WAY_CALL       BIT(0) /* Three-way calling */
+#define BT_HFP_AG_SDP_FEATURE_ECNR            BIT(1) /* EC and/or NR function */
+#define BT_HFP_AG_SDP_FEATURE_VOICE_RECG      BIT(2) /* Voice recognition */
+#define BT_HFP_AG_SDP_FEATURE_INBAND_RINGTONE BIT(3) /* In-band ring tone capability */
+#define BT_HFP_AG_SDP_FEATURE_VOICE_TAG       BIT(4) /* Attach no. to voice tag */
+#define BT_HFP_AG_SDP_FEATURE_WBS             BIT(5) /* Wide Band Speech */
+#define BT_HFP_AG_SDP_FEATURE_ENH_VOICE_RECG  BIT(6) /* Enhanced Voice Recognition Status */
+#define BT_HFP_AG_SDP_FEATURE_VOICE_RECG_TEXT BIT(7) /* Voice Recognition Text */
+#define BT_HFP_AG_SDP_FEATURE_SUPER_WBS       BIT(8) /* Super Wide Band Speech */
 #define HF_MAX_BUF_LEN       BT_HF_CLIENT_MAX_PDU
 #define HF_MAX_AG_INDICATORS 20
 
-struct bt_hfp_hf {
-	struct bt_rfcomm_dlc rfcomm_dlc;
-	/* ACL connection handle */
-	struct bt_conn *acl;
-	/* SCO Channel */
-	struct bt_sco_chan chan;
-	char hf_buffer[HF_MAX_BUF_LEN];
-	struct at_client at;
-	uint32_t hf_features;
-	uint32_t ag_features;
-	int8_t ind_table[HF_MAX_AG_INDICATORS];
-};
+#define BT_HFP_HF_VGM_GAIN_MAX 15
+#define BT_HFP_HF_VGM_GAIN_MIN 0
 
-enum hfp_hf_ag_indicators {
-	HF_SERVICE_IND,
-	HF_CALL_IND,
-	HF_CALL_SETUP_IND,
-	HF_CALL_HELD_IND,
-	HF_SINGNAL_IND,
-	HF_ROAM_IND,
-	HF_BATTERY_IND
-};
+#define BT_HFP_HF_VGS_GAIN_MAX 15
+#define BT_HFP_HF_VGS_GAIN_MIN 0
 
 /* HFP call setup status */
 #define BT_HFP_CALL_SETUP_NONE            0
 #define BT_HFP_CALL_SETUP_INCOMING        1
 #define BT_HFP_CALL_SETUP_OUTGOING        2
 #define BT_HFP_CALL_SETUP_REMOTE_ALERTING 3
+
+/* HFP incoming call status */
+#define BT_HFP_BTRH_ON_HOLD  0
+#define BT_HFP_BTRH_ACCEPTED 1
+#define BT_HFP_BTRH_REJECTED 2
+
+/* HFP Call held status */
+/* No calls held */
+#define BT_HFP_CALL_HELD_NONE        0
+/* Call is placed on hold or active/held calls swapped
+ * The AG has both an active AND a held call
+ */
+#define BT_HFP_CALL_HELD_ACTIVE_HELD 1
+/* Call on hold, no active call */
+#define BT_HFP_CALL_HELD_HELD        2
+
+/* HFP AT+CHLD command value */
+/* Releases all held calls or sets User Determined User Busy
+ * (UDUB) for a waiting call
+ */
+#define BT_HFP_CHLD_RELEASE_ALL                 0
+/* Releases all active calls (if any exist) and accepts the
+ * other (held or waiting) call.
+ */
+#define BT_HFP_CHLD_RELEASE_ACTIVE_ACCEPT_OTHER 1
+/* Places all active calls (if any exist) on hold and accepts
+ * the other (held or waiting) call
+ */
+#define BT_HFP_CALL_HOLD_ACTIVE_ACCEPT_OTHER    2
+/* Adds a held call to the conversation */
+#define BT_HFP_CALL_ACTIVE_HELD                 3
+/* Connects the two calls and disconnects the subscriber from
+ * both calls (Explicit Call Transfer).
+ * Support for this value and its associated functionality is
+ * optional for the HF.
+ */
+#define BT_HFP_CALL_QUITE	                    4
+/* Release a specific active call */
+#define BT_HFP_CALL_RELEASE_SPECIFIED_ACTIVE    10
+/* Private Consultation Mode
+ * place all parties of a multiparty call on hold with the
+ * exception of the specified call.
+ */
+#define BT_HFP_CALL_PRIVATE_CNLTN_MODE          20
+
+/* Active */
+#define BT_HFP_CLCC_STATUS_ACTIVE         0
+/* Held */
+#define BT_HFP_CLCC_STATUS_HELD           1
+/* Dialing (outgoing calls only) */
+#define BT_HFP_CLCC_STATUS_DIALING        2
+/* Alerting (outgoing calls only) */
+#define BT_HFP_CLCC_STATUS_ALERTING       3
+/* Incoming (incoming calls only) */
+#define BT_HFP_CLCC_STATUS_INCOMING       4
+/* Waiting (incoming calls only) */
+#define BT_HFP_CLCC_STATUS_WAITING        5
+/* Call held by Response and Hold */
+#define BT_HFP_CLCC_STATUS_CALL_HELD_HOLD 6
+
+/* BVRA Value */
+/* BVRA Deactivation */
+#define BT_HFP_BVRA_DEACTIVATION    0
+/* BVRA Activation */
+#define BT_HFP_BVRA_ACTIVATION      1
+/* Ready to accept audio */
+#define BT_HFP_BVRA_READY_TO_ACCEPT 2
+
+/* a maximum of 4 characters in length, but
+ * less than 4 characters in length is valid.
+ */
+#define BT_HFP_BVRA_TEXT_ID_MAX_LEN 4
+
+/* BVRA VRE state */
+/* BVRA VRE state: the AG is ready to accept audio input */
+#define BT_HFP_BVRA_STATE_ACCEPT_INPUT BIT(0)
+/* BVRA VRE state: the AG is sending audio to the HF */
+#define BT_HFP_BVRA_STATE_SEND_AUDIO BIT(1)
+/* BVRA VRE state: the AG is processing the audio input */
+#define BT_HFP_BVRA_STATE_PROCESS_AUDIO BIT(2)
+
+#define IS_VALID_DTMF(c) ((((c) >= '0') && ((c) <= '9')) || \
+	(((c) >= 'A') && ((c) <= 'D')) || ((c) == '#') || ((c) == '*'))
+
+/* HFP HF Indicators */
+enum {
+	HFP_HF_ENHANCED_SAFETY_IND = 1, /* Enhanced Safety */
+	HFP_HF_BATTERY_LEVEL_IND = 2,   /* Remaining level of Battery */
+	HFP_HF_IND_MAX
+};
+
+#define IS_VALID_BATTERY_LEVEL(level) (((level) >= 0) && ((level) <= 100))
diff --git a/subsys/bluetooth/host/classic/keys_br.c b/subsys/bluetooth/host/classic/keys_br.c
index 3c9536fe112..2c9c6e32c98 100644
--- a/subsys/bluetooth/host/classic/keys_br.c
+++ b/subsys/bluetooth/host/classic/keys_br.c
@@ -146,7 +146,7 @@ void bt_keys_link_key_store(struct bt_keys_link_key *link_key)
 	}
 }
 
-void bt_foreach_bond_br(void (*func)(const struct bt_bond_info *info, void *user_data),
+void bt_br_foreach_bond(void (*func)(const struct bt_br_bond_info *info, void *user_data),
 			void *user_data)
 {
 	__ASSERT_NO_MSG(func != NULL);
@@ -155,10 +155,9 @@ void bt_foreach_bond_br(void (*func)(const struct bt_bond_info *info, void *user
 		const struct bt_keys_link_key *key = &key_pool[i];
 
 		if (!bt_addr_eq(&key->addr, BT_ADDR_ANY)) {
-			struct bt_bond_info info;
+			struct bt_br_bond_info info;
 
-			info.addr.type = BT_ADDR_LE_PUBLIC;
-			bt_addr_copy(&info.addr.a, &key->addr);
+			bt_addr_copy(&info.addr, &key->addr);
 			func(&info, user_data);
 		}
 	}
diff --git a/subsys/bluetooth/host/classic/l2cap_br.c b/subsys/bluetooth/host/classic/l2cap_br.c
index 405a971cfef..36f49bba3a8 100644
--- a/subsys/bluetooth/host/classic/l2cap_br.c
+++ b/subsys/bluetooth/host/classic/l2cap_br.c
@@ -13,6 +13,7 @@
 #include <zephyr/sys/byteorder.h>
 #include <zephyr/sys/iterable_sections.h>
 #include <zephyr/sys/util.h>
+#include <zephyr/sys/crc.h>
 
 #include <zephyr/bluetooth/hci.h>
 #include <zephyr/bluetooth/bluetooth.h>
@@ -21,6 +22,7 @@
 #include "host/buf_view.h"
 #include "host/hci_core.h"
 #include "host/conn_internal.h"
+#include "host/keys.h"
 #include "l2cap_br_internal.h"
 #include "avdtp_internal.h"
 #include "a2dp_internal.h"
@@ -35,8 +37,16 @@ LOG_MODULE_REGISTER(bt_l2cap_br, CONFIG_BT_L2CAP_LOG_LEVEL);
 #define BR_CHAN_RTX(_w) CONTAINER_OF(k_work_delayable_from_work(_w), \
 				     struct bt_l2cap_br_chan, rtx_work)
 
+#define BR_CHAN_RET(_w) CONTAINER_OF(k_work_delayable_from_work(_w), \
+				     struct bt_l2cap_br_chan, ret_work)
+
+#define BR_CHAN_MONITOR(_w) CONTAINER_OF(k_work_delayable_from_work(_w), \
+					 struct bt_l2cap_br_chan, monitor_work)
+
 #define L2CAP_BR_PSM_START	0x0001
 #define L2CAP_BR_PSM_END	0xffff
+#define L2CAP_BR_PSM_DYN_START	0x1000
+#define L2CAP_BR_PSM_DYN_END	L2CAP_BR_PSM_END
 
 #define L2CAP_BR_CID_DYN_START	0x0040
 #define L2CAP_BR_CID_DYN_END	0xffff
@@ -48,30 +58,133 @@ LOG_MODULE_REGISTER(bt_l2cap_br, CONFIG_BT_L2CAP_LOG_LEVEL);
 
 #define L2CAP_BR_PSM_SDP	0x0001
 
-#define L2CAP_BR_INFO_TIMEOUT		K_SECONDS(4)
-#define L2CAP_BR_CFG_TIMEOUT		K_SECONDS(4)
-#define L2CAP_BR_DISCONN_TIMEOUT	K_SECONDS(1)
-#define L2CAP_BR_CONN_TIMEOUT		K_SECONDS(40)
+#define L2CAP_BR_S_FRAME_FLAG_MASK 0xffffff00U
+#define L2CAP_BR_S_FRAME_UD_FLAG   0xffffff00
+#define L2CAP_BR_IS_S_FRAME(flag)                                                \
+	((POINTER_TO_UINT(flag) & L2CAP_BR_S_FRAME_FLAG_MASK) == L2CAP_BR_S_FRAME_UD_FLAG)
+
+#define L2CAP_BR_GET_S_BIT(flag) (POINTER_TO_UINT(flag) & ~L2CAP_BR_S_FRAME_FLAG_MASK)
+
+#define L2CAP_BR_S_FRAME_UD_FLAG_SET(s) UINT_TO_POINTER(L2CAP_BR_S_FRAME_UD_FLAG | (s))
+#define L2CAP_BR_S_RR_FRAME             L2CAP_BR_S_FRAME_UD_FLAG_SET(BT_L2CAP_CONTROL_S_RR)
+#define L2CAP_BR_S_REJ_FRAME            L2CAP_BR_S_FRAME_UD_FLAG_SET(BT_L2CAP_CONTROL_S_REJ)
+#define L2CAP_BR_S_RNR_FRAME            L2CAP_BR_S_FRAME_UD_FLAG_SET(BT_L2CAP_CONTROL_S_RNR)
+#define L2CAP_BR_S_SREJ_FRAME           L2CAP_BR_S_FRAME_UD_FLAG_SET(BT_L2CAP_CONTROL_S_SREJ)
+
+#define L2CAP_BR_INFO_TIMEOUT    K_SECONDS(4)
+#define L2CAP_BR_CFG_TIMEOUT     K_SECONDS(4)
+#define L2CAP_BR_DISCONN_TIMEOUT K_SECONDS(1)
+#define L2CAP_BR_CONN_TIMEOUT    K_SECONDS(40)
+
+#define L2CAP_FEAT_FC_MASK           BIT(0)
+#define L2CAP_FEAT_RET_MASK          BIT(1)
+#define L2CAP_FEAT_QOS_MASK          BIT(2)
+#define L2CAP_FEAT_ENH_RET_MASK      BIT(3)
+#define L2CAP_FEAT_STREAM_MASK       BIT(4)
+#define L2CAP_FEAT_FCS_MASK          BIT(5)
+#define L2CAP_FEAT_EXT_FS_MASK       BIT(6)
+#define L2CAP_FEAT_FIXED_CHAN_MASK   BIT(7)
+#define L2CAP_FEAT_EXT_WIN_SIZE_MASK BIT(8)
+#define L2CAP_FEAT_CLS_MASK          BIT(9)
+#define L2CAP_FEAT_ECBFC_MASK        BIT(10)
+
+#if defined(CONFIG_BT_L2CAP_RET)
+#define L2CAP_FEAT_RET_ENABLE_MASK L2CAP_FEAT_RET_MASK
+#else
+#define L2CAP_FEAT_RET_ENABLE_MASK 0
+#endif /* CONFIG_BT_L2CAP_RET */
+
+#if defined(CONFIG_BT_L2CAP_FC)
+#define L2CAP_FEAT_FC_ENABLE_MASK L2CAP_FEAT_FC_MASK
+#else
+#define L2CAP_FEAT_FC_ENABLE_MASK 0
+#endif /* CONFIG_BT_L2CAP_FC */
+
+#if defined(CONFIG_BT_L2CAP_ENH_RET)
+#define L2CAP_FEAT_ENH_RET_ENABLE_MASK L2CAP_FEAT_ENH_RET_MASK
+#else
+#define L2CAP_FEAT_ENH_RET_ENABLE_MASK 0
+#endif /* CONFIG_BT_L2CAP_ENH_RET */
+
+#if defined(CONFIG_BT_L2CAP_STREAM)
+#define L2CAP_FEAT_STREAM_ENABLE_MASK L2CAP_FEAT_STREAM_MASK
+#else
+#define L2CAP_FEAT_STREAM_ENABLE_MASK 0
+#endif /* CONFIG_BT_L2CAP_STREAM */
+
+#if defined(CONFIG_BT_L2CAP_FCS)
+#define L2CAP_FEAT_FCS_ENABLE_MASK L2CAP_FEAT_FCS_MASK
+#else
+#define L2CAP_FEAT_FCS_ENABLE_MASK 0
+#endif /* CONFIG_BT_L2CAP_FCS */
+
+#if defined(CONFIG_BT_L2CAP_EXT_WIN_SIZE)
+#define L2CAP_FEAT_EXT_WIN_SIZE_ENABLE_MASK L2CAP_FEAT_EXT_WIN_SIZE_MASK
+#else
+#define L2CAP_FEAT_EXT_WIN_SIZE_ENABLE_MASK 0
+#endif /* CONFIG_BT_L2CAP_EXT_WIN_SIZE */
 
 /*
  * L2CAP extended feature mask:
  * BR/EDR fixed channel support enabled
  */
-#define L2CAP_FEAT_FIXED_CHAN_MASK	0x00000080
+#define L2CAP_EXTENDED_FEAT_MASK                                                               \
+	(L2CAP_FEAT_FIXED_CHAN_MASK | L2CAP_FEAT_RET_ENABLE_MASK |                             \
+	 L2CAP_FEAT_FC_ENABLE_MASK | L2CAP_FEAT_ENH_RET_ENABLE_MASK |                          \
+	 L2CAP_FEAT_STREAM_ENABLE_MASK | L2CAP_FEAT_FCS_ENABLE_MASK |                          \
+	 L2CAP_FEAT_EXT_WIN_SIZE_ENABLE_MASK)
 
 enum {
 	/* Connection oriented channels flags */
-	L2CAP_FLAG_CONN_LCONF_DONE,	/* local config accepted by remote */
-	L2CAP_FLAG_CONN_RCONF_DONE,	/* remote config accepted by local */
-	L2CAP_FLAG_CONN_ACCEPTOR,	/* getting incoming connection req */
-	L2CAP_FLAG_CONN_PENDING,	/* remote sent pending result in rsp */
+	L2CAP_FLAG_CONN_LCONF_DONE, /* local config accepted by remote */
+	L2CAP_FLAG_CONN_RCONF_DONE, /* remote config accepted by local */
+	L2CAP_FLAG_CONN_ACCEPTOR,   /* getting incoming connection req */
+	L2CAP_FLAG_CONN_PENDING,    /* remote sent pending result in rsp */
 
 	/* Signaling channel flags */
-	L2CAP_FLAG_SIG_INFO_PENDING,	/* retrieving remote l2cap info */
-	L2CAP_FLAG_SIG_INFO_DONE,	/* remote l2cap info is done */
+	L2CAP_FLAG_SIG_INFO_PENDING, /* retrieving remote l2cap info */
+	L2CAP_FLAG_SIG_INFO_DONE,    /* remote l2cap info is done */
 
 	/* fixed channels flags */
-	L2CAP_FLAG_FIXED_CONNECTED,		/* fixed connected */
+	L2CAP_FLAG_FIXED_CONNECTED, /* fixed connected */
+
+	/* Retransmition and flow control flags*/
+	L2CAP_FLAG_RET_TIMER,   /* Retransmission timer is working */
+	L2CAP_FLAG_PDU_RETRANS, /* PDU retransmission */
+
+	/* Receiving S-frame/I-frame flags */
+	L2CAP_FLAG_RECV_FRAME_P,         /* Poll (P) flag of received frame */
+	L2CAP_FLAG_RECV_FRAME_R,         /* Retransmission Disable (R) of received frame */
+	L2CAP_FLAG_RECV_FRAME_R_CHANGED, /* Flag the R flag changed.
+					  * After send received frame with R bit set,
+					  * clear the flag.
+					  */
+
+	/* Sending S-frame/I-frame flags */
+	L2CAP_FLAG_SEND_FRAME_REJ,         /* Report an REJ in received frame */
+	L2CAP_FLAG_SEND_FRAME_REJ_CHANGED, /* Flag the REJ flag changed.
+					    * After send received frame with REJ flag,
+					    * clear the flag.
+					    */
+	L2CAP_FLAG_SEND_FRAME_P,           /* Poll (P) flag */
+	L2CAP_FLAG_SEND_FRAME_P_CHANGED,   /* Poll (P) flag changed */
+	L2CAP_FLAG_SEND_S_FRAME,           /* Need to send S-frame */
+
+	/* Remote State */
+	L2CAP_FLAG_REMOTE_BUSY, /* Remote Busy Flag */
+
+	/* Local State */
+	L2CAP_FLAG_LOCAL_BUSY,         /* Local Busy Flag */
+	L2CAP_FLAG_LOCAL_BUSY_CHANGED, /* Local Busy Flag changed */
+	L2CAP_FLAG_REJ_ACTIONED,       /* REJ Actioned */
+	L2CAP_FLAG_SREJ_ACTIONED,      /* SREJ Actioned */
+	L2CAP_FLAG_RET_I_FRAME,        /* Could Retransmit I-frames */
+	L2CAP_FLAG_NEW_I_FRAME,        /* Could Send Pending I-frames */
+	L2CAP_FLAG_RET_REQ_I_FRAME,    /* Could Retransmit Requested I-frames */
+	L2CAP_FLAG_REQ_SEQ_UPDATED,    /* req_seq has been updated */
+
+	/* Auth failed, disconnect ACL */
+	L2CAP_FLAG_DISCONNECT_ACL,	/* Disconnect ACL */
 };
 
 static sys_slist_t br_servers;
@@ -81,11 +194,27 @@ static sys_slist_t br_servers;
 NET_BUF_POOL_FIXED_DEFINE(br_sig_pool, CONFIG_BT_MAX_CONN,
 			  BT_L2CAP_BUF_SIZE(L2CAP_BR_MIN_MTU), 8, NULL);
 
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+static void br_tx_buf_destroy(struct net_buf *buf)
+{
+	net_buf_destroy(buf);
+
+	LOG_DBG("");
+
+	/* Kick the TX processor to send the rest of the frags. */
+	bt_tx_irq_raise();
+}
+
+/* Pool for outgoing BR/EDR signaling packets, min MTU is 48 */
+NET_BUF_POOL_FIXED_DEFINE(br_tx_pool, CONFIG_BT_L2CAP_TX_BUF_COUNT,
+			  BT_L2CAP_BUF_SIZE(CONFIG_BT_L2CAP_MPS), CONFIG_BT_CONN_TX_USER_DATA_SIZE,
+			  br_tx_buf_destroy);
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+
 /* BR/EDR L2CAP signalling channel specific context */
 struct bt_l2cap_br {
 	/* The channel this context is associated with */
 	struct bt_l2cap_br_chan	chan;
-	uint8_t			info_ident;
 	/*
 	 * 2.1 CHANNEL IDENTIFIERS in
 	 * BLUETOOTH CORE SPECIFICATION Version 5.4 | Vol 3, Part A.
@@ -197,6 +326,11 @@ static void l2cap_br_chan_destroy(struct bt_l2cap_chan *chan)
 		k_work_cancel_delayable(&br_chan->rtx_work);
 	}
 
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	k_work_cancel_delayable(&br_chan->ret_work);
+	k_work_cancel_delayable(&br_chan->monitor_work);
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+
 	atomic_clear(BR_CHAN(chan)->flags);
 }
 
@@ -227,30 +361,6 @@ static void l2cap_br_rtx_timeout(struct k_work *work)
 	}
 }
 
-static bool l2cap_br_chan_add(struct bt_conn *conn, struct bt_l2cap_chan *chan,
-			      bt_l2cap_chan_destroy_t destroy)
-{
-	struct bt_l2cap_br_chan *ch = l2cap_br_chan_alloc_cid(conn, chan);
-
-	if (!ch) {
-		LOG_DBG("Unable to allocate L2CAP CID");
-		return false;
-	}
-
-	k_fifo_init(&ch->_pdu_tx_queue);
-
-	/* All dynamic channels have the destroy handler which makes sure that
-	 * the RTX work structure is properly released with a cancel sync.
-	 * The fixed signal channel is only removed when disconnected and the
-	 * disconnected handler is always called from the workqueue itself so
-	 * canceling from there should always succeed.
-	 */
-	k_work_init_delayable(&ch->rtx_work, l2cap_br_rtx_timeout);
-	bt_l2cap_chan_add(conn, chan, destroy);
-
-	return true;
-}
-
 static uint8_t l2cap_br_get_ident(void)
 {
 	static uint8_t ident;
@@ -264,6 +374,12 @@ static uint8_t l2cap_br_get_ident(void)
 	return ident;
 }
 
+/* L2CAP channel wants to send a PDU */
+static bool chan_has_data(struct bt_l2cap_br_chan *br_chan)
+{
+	return !sys_slist_is_empty(&br_chan->_pdu_tx_queue);
+}
+
 static void raise_data_ready(struct bt_l2cap_br_chan *br_chan)
 {
 	if (!atomic_set(&br_chan->_pdu_ready_lock, 1)) {
@@ -299,1706 +415,5384 @@ static void cancel_data_ready(struct bt_l2cap_br_chan *br_chan)
 	atomic_set(&br_chan->_pdu_ready_lock, 0);
 }
 
-int bt_l2cap_br_send_cb(struct bt_conn *conn, uint16_t cid, struct net_buf *buf,
-			bt_conn_tx_cb_t cb, void *user_data)
-{
-	struct bt_l2cap_hdr *hdr;
-	struct bt_l2cap_chan *ch = bt_l2cap_br_lookup_tx_cid(conn, cid);
-	struct bt_l2cap_br_chan *br_chan = CONTAINER_OF(ch, struct bt_l2cap_br_chan, chan);
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+enum l2cap_br_timer_type {
+	BT_L2CAP_BR_TIMER_RET,
+	BT_L2CAP_BR_TIMER_MONITOR,
+};
 
-	LOG_DBG("chan %p buf %p len %zu", br_chan, buf, buf->len);
+static void l2cap_br_start_timer(struct bt_l2cap_br_chan *br_chan, enum l2cap_br_timer_type type,
+				 bool restart)
+{
+	if (type == BT_L2CAP_BR_TIMER_RET) {
+		if (!atomic_test_and_set_bit(br_chan->flags, L2CAP_FLAG_RET_TIMER)) {
+			k_work_cancel_delayable(&br_chan->monitor_work);
+			k_work_schedule(&br_chan->ret_work, K_MSEC(br_chan->tx.ret_timeout));
+			LOG_DBG("Start ret timer");
+		} else {
+			if (!restart) {
+				return;
+			}
 
-	hdr = net_buf_push(buf, sizeof(*hdr));
-	hdr->len = sys_cpu_to_le16(buf->len - sizeof(*hdr));
-	hdr->cid = sys_cpu_to_le16(cid);
+			k_work_reschedule(&br_chan->ret_work, K_MSEC(br_chan->tx.ret_timeout));
+			LOG_DBG("Restart ret timer");
+		}
+	} else {
+		if (atomic_test_and_clear_bit(br_chan->flags, L2CAP_FLAG_RET_TIMER)) {
+			k_work_cancel_delayable(&br_chan->ret_work);
+			k_work_schedule(&br_chan->monitor_work,
+					K_MSEC(br_chan->tx.monitor_timeout));
+			LOG_DBG("Start monitor timer");
+		} else {
+			if (!restart) {
+				return;
+			}
 
-	if (buf->user_data_size < sizeof(struct closure)) {
-		LOG_WRN("not enough room in user_data %d < %d pool %u",
-			buf->user_data_size,
-			CONFIG_BT_CONN_TX_USER_DATA_SIZE,
-			buf->pool_id);
-		return -EINVAL;
+			k_work_reschedule(&br_chan->monitor_work,
+					  K_MSEC(br_chan->tx.monitor_timeout));
+			LOG_DBG("Restart monitor timer");
+		}
 	}
+}
 
-	LOG_DBG("push PDU: cb %p userdata %p", cb, user_data);
+static uint16_t bt_l2cap_br_get_outstanding_count(struct bt_l2cap_br_chan *br_chan)
+{
+	struct bt_l2cap_br_window *tx_win, *next;
+	uint16_t count = 0;
 
-	make_closure(buf->user_data, cb, user_data);
-	k_fifo_put(&br_chan->_pdu_tx_queue, buf);
-	raise_data_ready(br_chan);
+	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&br_chan->_pdu_outstanding, tx_win, next, node) {
+		count++;
+	}
 
-	return 0;
+	return count;
 }
 
-/* Send the buffer and release it in case of failure.
- * Any other cleanup in failure to send should be handled by the disconnected
- * handler.
- */
-static inline void l2cap_send(struct bt_conn *conn, uint16_t cid,
-			      struct net_buf *buf)
+static struct bt_l2cap_br_window *l2cap_br_find_window(struct bt_l2cap_br_chan *br_chan)
 {
-	if (bt_l2cap_br_send_cb(conn, cid, buf, NULL, NULL)) {
-		net_buf_unref(buf);
+	struct bt_l2cap_br_window *win;
+	uint16_t count;
+
+	count = bt_l2cap_br_get_outstanding_count(br_chan);
+	if (count >= br_chan->tx.max_window) {
+		return NULL;
+	}
+
+	win = k_fifo_get(&br_chan->_free_tx_win, K_NO_WAIT);
+	if (win) {
+		memset(win, 0, sizeof(*win));
 	}
+
+	return win;
 }
 
-static void l2cap_br_chan_send_req(struct bt_l2cap_br_chan *chan,
-				   struct net_buf *buf, k_timeout_t timeout)
+static void l2cap_br_free_window(struct bt_l2cap_br_chan *br_chan,
+				 struct bt_l2cap_br_window *tx_win)
 {
-
-	if (bt_l2cap_br_send_cb(chan->chan.conn, BT_L2CAP_CID_BR_SIG, buf,
-			     NULL, NULL)) {
-		net_buf_unref(buf);
-		return;
+	if (tx_win) {
+		memset(tx_win, 0, sizeof(*tx_win));
+		k_fifo_put(&br_chan->_free_tx_win, tx_win);
 	}
-
-	/* BLUETOOTH SPECIFICATION Version 4.2 [Vol 3, Part A] page 126:
-	 *
-	 * The value of this timer is implementation-dependent but the minimum
-	 * initial value is 1 second and the maximum initial value is 60
-	 * seconds. One RTX timer shall exist for each outstanding signaling
-	 * request, including each Echo Request. The timer disappears on the
-	 * final expiration, when the response is received, or the physical
-	 * link is lost.
-	 */
-	k_work_reschedule(&chan->rtx_work, timeout);
 }
 
-/* L2CAP channel wants to send a PDU */
-static bool chan_has_data(struct bt_l2cap_br_chan *br_chan)
+static uint16_t bt_l2cap_br_update_seq(struct bt_l2cap_br_chan *br_chan, uint16_t seq)
 {
-	return !k_fifo_is_empty(&br_chan->_pdu_tx_queue);
+	if ((br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_ERET) ||
+	    (br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_STREAM)) {
+		if (br_chan->tx.extended_control) {
+			seq = seq % BT_L2CAP_EXT_CONTROL_SEQ_MAX;
+		} else {
+			seq = seq % BT_L2CAP_CONTROL_SEQ_MAX;
+		}
+	} else if ((br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_RET) ||
+		   (br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_FC)) {
+		seq = seq % BT_L2CAP_CONTROL_SEQ_MAX;
+	}
+
+	return seq;
 }
 
-struct net_buf *l2cap_br_data_pull(struct bt_conn *conn,
-				   size_t amount,
-				   size_t *length)
+static struct bt_l2cap_br_window *l2cap_br_find_srej(struct bt_l2cap_br_chan *br_chan)
 {
-	const sys_snode_t *pdu_ready = sys_slist_peek_head(&conn->l2cap_data_ready);
+	struct bt_l2cap_br_window *tx_win, *next;
 
-	if (!pdu_ready) {
-		LOG_DBG("nothing to send on this conn");
-		return NULL;
+	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&br_chan->_pdu_outstanding, tx_win, next, node) {
+		if (tx_win->srej) {
+			return tx_win;
+		}
 	}
 
-	struct bt_l2cap_br_chan *br_chan = CONTAINER_OF(pdu_ready,
-							struct bt_l2cap_br_chan,
-							_pdu_ready);
+	return NULL;
+}
 
-	/* Leave the PDU buffer in the queue until we have sent all its
-	 * fragments.
-	 */
-	struct net_buf *pdu = k_fifo_peek_head(&br_chan->_pdu_tx_queue);
+static bool bt_l2cap_br_check_req_seq_valid(struct bt_l2cap_br_chan *br_chan, uint16_t req_seq)
+{
+	uint16_t outstanding_frames;
+	uint16_t ack_frames;
+	uint16_t outstanding_count;
+
+	outstanding_frames = (uint16_t)(br_chan->next_tx_seq - br_chan->expected_ack_seq);
+	ack_frames = (uint16_t)(req_seq - br_chan->expected_ack_seq);
+
+	if ((br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_ERET) ||
+	    (br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_STREAM)) {
+		if (br_chan->tx.extended_control) {
+			outstanding_frames = outstanding_frames % BT_L2CAP_EXT_CONTROL_SEQ_MAX;
+			ack_frames = ack_frames % BT_L2CAP_EXT_CONTROL_SEQ_MAX;
+		} else {
+			outstanding_frames = outstanding_frames % BT_L2CAP_CONTROL_SEQ_MAX;
+			ack_frames = ack_frames % BT_L2CAP_CONTROL_SEQ_MAX;
+		}
+	} else if ((br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_RET) ||
+		   (br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_FC)) {
+		outstanding_frames = outstanding_frames % BT_L2CAP_CONTROL_SEQ_MAX;
+		ack_frames = ack_frames % BT_L2CAP_CONTROL_SEQ_MAX;
+	}
 
-	__ASSERT(pdu, "signaled ready but no PDUs in the TX queue");
+	outstanding_count = bt_l2cap_br_get_outstanding_count(br_chan);
+	__ASSERT(outstanding_count == outstanding_frames,
+		 "Mismatch between window and seq %zu - %zu", outstanding_count,
+		 outstanding_frames);
 
-	if (bt_buf_has_view(pdu)) {
-		LOG_ERR("already have view on %p", pdu);
-		return NULL;
+	if (ack_frames <= outstanding_frames) {
+		return true;
 	}
 
-	/* We can't interleave ACL fragments from different channels for the
-	 * same ACL conn -> we have to wait until a full L2 PDU is transferred
-	 * before switching channels.
-	 */
-	bool last_frag = amount >= pdu->len;
+	return false;
+}
 
-	if (last_frag) {
-		LOG_DBG("last frag, removing %p", pdu);
-		__maybe_unused struct net_buf *b = k_fifo_get(&br_chan->_pdu_tx_queue, K_NO_WAIT);
+static void l2cap_br_sdu_is_done(struct bt_l2cap_br_chan *br_chan, struct net_buf *sdu, int err)
+{
+	bt_conn_tx_cb_t cb;
 
-		__ASSERT_NO_MSG(b == pdu);
+	__ASSERT(sdu, "Invalid sdu buffer on chan %p", br_chan);
 
-		LOG_DBG("chan %p done", br_chan);
-		lower_data_ready(br_chan);
+	/* The SDU is done */
+	LOG_DBG("SDU is done, removing %p", sdu);
 
-		/* Append channel to list if it still has data */
-		if (chan_has_data(br_chan)) {
-			LOG_DBG("chan %p ready", br_chan);
-			raise_data_ready(br_chan);
-		}
+	if (!sys_slist_find_and_remove(&br_chan->_pdu_tx_queue, &sdu->node)) {
+		LOG_WRN("SDU %p is not found", sdu);
 	}
 
-	*length = pdu->len;
+	cb = closure_cb(sdu->user_data);
+	if (cb) {
+		cb(br_chan->chan.conn, closure_data(sdu->user_data), err);
+	}
 
-	return pdu;
+	/* Remove the pdu */
+	net_buf_unref(sdu);
+
+	LOG_DBG("chan %p done", br_chan);
+
+	/* Append channel to list if it still has data */
+	if (chan_has_data(br_chan)) {
+		LOG_DBG("chan %p ready", br_chan);
+		raise_data_ready(br_chan);
+	}
 }
 
-static void l2cap_br_get_info(struct bt_l2cap_br *l2cap, uint16_t info_type)
+static int bt_l2cap_br_update_req_seq_direct(struct bt_l2cap_br_chan *br_chan, uint16_t req_seq,
+					     bool rej)
 {
-	struct bt_l2cap_info_req *info;
-	struct net_buf *buf;
-	struct bt_l2cap_sig_hdr *hdr;
-
-	LOG_DBG("info type %u", info_type);
+	struct bt_l2cap_br_window *tx_win;
+	struct net_buf *sdu;
+
+	tx_win = (void *)sys_slist_peek_head(&br_chan->_pdu_outstanding);
+	while (tx_win && (tx_win->tx_seq != req_seq)) {
+		sdu = tx_win->sdu;
+		if ((tx_win->sar == BT_L2CAP_CONTROL_SAR_UNSEG) ||
+		    (tx_win->sar == BT_L2CAP_CONTROL_SAR_END)) {
+			l2cap_br_sdu_is_done(br_chan, sdu, 0);
+		}
+		tx_win = (void *)sys_slist_get(&br_chan->_pdu_outstanding);
+		l2cap_br_free_window(br_chan, tx_win);
+		tx_win = (void *)sys_slist_peek_head(&br_chan->_pdu_outstanding);
+	}
+	br_chan->expected_ack_seq = req_seq;
+
+	if (rej) {
+		tx_win = (void *)sys_slist_peek_head(&br_chan->_pdu_outstanding);
+		if (tx_win) {
+			sdu = tx_win->sdu;
+			__ASSERT(sdu, "Invalid sdu buffer on chan %p", br_chan);
+			net_buf_simple_restore(&sdu->b, &tx_win->sdu_state);
+			if ((tx_win->sar == BT_L2CAP_CONTROL_SAR_UNSEG) ||
+			    (tx_win->sar == BT_L2CAP_CONTROL_SAR_START)) {
+				br_chan->_sdu_total_len = 0;
+			} else {
+				br_chan->_sdu_total_len = tx_win->sdu_total_len;
+			}
+			br_chan->next_tx_seq = tx_win->tx_seq;
+		}
 
-	if (atomic_test_bit(l2cap->chan.flags, L2CAP_FLAG_SIG_INFO_PENDING)) {
-		return;
+		while (tx_win) {
+			tx_win = (void *)sys_slist_get(&br_chan->_pdu_outstanding);
+			l2cap_br_free_window(br_chan, tx_win);
+			tx_win = (void *)sys_slist_peek_head(&br_chan->_pdu_outstanding);
+			if (tx_win) {
+				sdu = tx_win->sdu;
+				__ASSERT(sdu, "Invalid sdu buffer on chan %p", br_chan);
+				if ((tx_win->sar == BT_L2CAP_CONTROL_SAR_UNSEG) ||
+					(tx_win->sar == BT_L2CAP_CONTROL_SAR_START)) {
+					net_buf_simple_restore(&sdu->b, &tx_win->sdu_state);
+				}
+			}
+		}
 	}
 
-	switch (info_type) {
-	case BT_L2CAP_INFO_FEAT_MASK:
-	case BT_L2CAP_INFO_FIXED_CHAN:
-		break;
-	default:
-		LOG_WRN("Unsupported info type %u", info_type);
-		return;
+	if (!atomic_test_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_R)) {
+		if (bt_l2cap_br_get_outstanding_count(br_chan)) {
+			l2cap_br_start_timer(br_chan, BT_L2CAP_BR_TIMER_RET, true);
+		} else {
+			l2cap_br_start_timer(br_chan, BT_L2CAP_BR_TIMER_MONITOR, false);
+		}
 	}
 
-	buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
+	if (chan_has_data(br_chan)) {
+		LOG_DBG("chan %p ready", br_chan);
+		raise_data_ready(br_chan);
+	}
 
-	atomic_set_bit(l2cap->chan.flags, L2CAP_FLAG_SIG_INFO_PENDING);
-	l2cap->info_ident = l2cap_br_get_ident();
+	return 0;
+}
 
-	hdr = net_buf_add(buf, sizeof(*hdr));
-	hdr->code = BT_L2CAP_INFO_REQ;
-	hdr->ident = l2cap->info_ident;
-	hdr->len = sys_cpu_to_le16(sizeof(*info));
+static int bt_l2cap_br_update_req_seq(struct bt_l2cap_br_chan *br_chan, uint16_t req_seq, bool rej)
+{
+	int err = 0;
 
-	info = net_buf_add(buf, sizeof(*info));
-	info->type = sys_cpu_to_le16(info_type);
+	if (bt_l2cap_br_check_req_seq_valid(br_chan, req_seq)) {
+		err = bt_l2cap_br_update_req_seq_direct(br_chan, req_seq, rej);
+	} else {
+		LOG_ERR("Invalid req seq %d received on %p", req_seq, br_chan);
+		/* The L2CAP entity shall close the channel as a consequence
+		 * of an ReqSeq Sequence error.
+		 */
+		bt_l2cap_br_chan_disconnect(&br_chan->chan);
+		err = -ESHUTDOWN;
+	}
 
-	l2cap_br_chan_send_req(&l2cap->chan, buf, L2CAP_BR_INFO_TIMEOUT);
+	return err;
 }
 
-static void connect_fixed_channel(struct bt_l2cap_br_chan *chan)
+static int l2cap_br_send_s_frame(struct bt_l2cap_br_chan *br_chan, uint8_t s, k_timeout_t timeout)
 {
-	if (atomic_test_and_set_bit(chan->flags, L2CAP_FLAG_FIXED_CONNECTED)) {
-		return;
+	struct net_buf *buf;
+	int err;
+
+	if (atomic_test_and_set_bit(br_chan->flags, L2CAP_FLAG_SEND_S_FRAME)) {
+		LOG_WRN("S-frame is in pending on %p", br_chan);
 	}
 
-	if (chan->chan.ops && chan->chan.ops->connected) {
-		chan->chan.ops->connected(&chan->chan);
+	if (chan_has_data(br_chan)) {
+		/* There is PDU in pending. No Empty SDU needed to trigger S-frame sending. */
+		raise_data_ready(br_chan);
+		return 0;
 	}
-}
 
-static void connect_optional_fixed_channels(struct bt_l2cap_br *l2cap)
-{
-	/* can be change to loop if more BR/EDR fixed channels are added */
-	if (l2cap->info_fixed_chan & BIT(BT_L2CAP_CID_BR_SMP)) {
-		struct bt_l2cap_chan *chan;
+	buf = bt_l2cap_create_pdu_timeout(&br_tx_pool, 0, timeout);
+	if (!buf) {
+		return -ENOBUFS;
+	}
 
-		chan = bt_l2cap_br_lookup_rx_cid(l2cap->chan.chan.conn,
-						 BT_L2CAP_CID_BR_SMP);
-		if (chan) {
-			connect_fixed_channel(BR_CHAN(chan));
-		}
+	err = bt_l2cap_br_send_cb(br_chan->chan.conn, br_chan->tx.cid, buf, NULL,
+				  L2CAP_BR_S_FRAME_UD_FLAG_SET(s));
+	if (err) {
+		LOG_ERR("Fail to send S-frame %d on %p", err, br_chan);
+		net_buf_unref(buf);
 	}
+
+	return err;
 }
 
-static int l2cap_br_info_rsp(struct bt_l2cap_br *l2cap, uint8_t ident,
-			     struct net_buf *buf)
+static void l2cap_br_ret_timeout(struct k_work *work)
 {
-	struct bt_l2cap_info_rsp *rsp;
-	uint16_t type, result;
-	int err = 0;
+	struct bt_l2cap_br_chan *br_chan = BR_CHAN_RET(work);
+	uint16_t expected_ack_seq;
 
-	if (atomic_test_bit(l2cap->chan.flags, L2CAP_FLAG_SIG_INFO_DONE)) {
-		return 0;
+	if (!br_chan->chan.conn || br_chan->chan.conn->state != BT_CONN_CONNECTED) {
+		/* ACL connection is broken. */
+		return;
 	}
 
-	if (atomic_test_and_clear_bit(l2cap->chan.flags,
-				      L2CAP_FLAG_SIG_INFO_PENDING)) {
-		/*
-		 * Release RTX timer since got the response & there's pending
-		 * command request.
-		 */
-		k_work_cancel_delayable(&l2cap->chan.rtx_work);
+	if (br_chan->state != BT_L2CAP_CONNECTED) {
+		/* The channel is not connected */
+		return;
 	}
 
-	if (buf->len < sizeof(*rsp)) {
-		LOG_ERR("Too small info rsp packet size");
-		err = -EINVAL;
-		goto done;
+	/* Restart the timer */
+	if (atomic_test_bit(br_chan->flags, L2CAP_FLAG_RET_TIMER)) {
+		k_work_schedule(&br_chan->ret_work, K_MSEC(br_chan->tx.ret_timeout));
 	}
 
-	if (ident != l2cap->info_ident) {
-		LOG_WRN("Idents mismatch");
-		err = -EINVAL;
-		goto done;
-	}
+	LOG_DBG("chan %p retransmission timeout", br_chan);
 
-	rsp = net_buf_pull_mem(buf, sizeof(*rsp));
-	result = sys_le16_to_cpu(rsp->result);
-	if (result != BT_L2CAP_INFO_SUCCESS) {
-		LOG_WRN("Result unsuccessful");
-		err = -EINVAL;
-		goto done;
+	if (sys_slist_peek_head(&br_chan->_pdu_outstanding) == NULL) {
+		return;
 	}
 
-	type = sys_le16_to_cpu(rsp->type);
-
-	switch (type) {
-	case BT_L2CAP_INFO_FEAT_MASK:
-		if (buf->len < sizeof(uint32_t)) {
-			LOG_ERR("Invalid remote info feat mask");
-			err = -EINVAL;
-			break;
+	switch (br_chan->tx.mode) {
+	case BT_L2CAP_BR_LINK_MODE_RET:
+		LOG_WRN("Retrans on chan %p", br_chan);
+		atomic_set_bit(br_chan->flags, L2CAP_FLAG_PDU_RETRANS);
+		/* Append channel to list if it still has data */
+		if (chan_has_data(br_chan)) {
+			LOG_DBG("chan %p ready", br_chan);
+			raise_data_ready(br_chan);
 		}
-		l2cap->info_feat_mask = net_buf_pull_le32(buf);
-		LOG_DBG("remote info mask 0x%08x", l2cap->info_feat_mask);
+		break;
+	case BT_L2CAP_BR_LINK_MODE_FC:
+		expected_ack_seq = bt_l2cap_br_update_seq(br_chan, br_chan->expected_ack_seq + 1);
 
-		if (!(l2cap->info_feat_mask & L2CAP_FEAT_FIXED_CHAN_MASK)) {
-			break;
-		}
+		LOG_WRN("unacknowledged I-frame with sequence number %d",
+			br_chan->expected_ack_seq);
+		bt_l2cap_br_update_req_seq(br_chan, expected_ack_seq, false);
+		break;
+	case BT_L2CAP_BR_LINK_MODE_ERET:
+		if (!atomic_test_and_set_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_P)) {
+			int err;
 
-		l2cap_br_get_info(l2cap, BT_L2CAP_INFO_FIXED_CHAN);
-		return 0;
-	case BT_L2CAP_INFO_FIXED_CHAN:
-		if (buf->len < sizeof(uint8_t)) {
-			LOG_ERR("Invalid remote info fixed chan");
-			err = -EINVAL;
-			break;
-		}
-		/*
-		 * 2.1 CHANNEL IDENTIFIERS in
-		 * BLUETOOTH CORE SPECIFICATION Version 5.4 | Vol 3, Part A.
-		 * The info length of `Fixed channels supported` is 8 octets.
-		 * Then the range of fixed L2CAP CID is 0x0001 ~ 0x0007 both for LE and BR.
-		 * So use one octet buffer to keep the `Fixed channels supported`
-		 * of peer device.
-		 */
-		l2cap->info_fixed_chan = net_buf_pull_u8(buf);
-		LOG_DBG("remote fixed channel mask 0x%02x", l2cap->info_fixed_chan);
+			/* State: XMIT
+			 * Retrans Timer expires Or Local Busy Clears
+			 * Action: send RR(P=1) or RNR(P=1)
+			 */
+			br_chan->retry_count = 1;
 
-		connect_optional_fixed_channels(l2cap);
+			LOG_WRN("Send RR(P=1) on chan %p", br_chan);
 
+			l2cap_br_start_timer(br_chan, BT_L2CAP_BR_TIMER_MONITOR, true);
+
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_P_CHANGED);
+			err = l2cap_br_send_s_frame(br_chan, BT_L2CAP_CONTROL_S_RR, K_NO_WAIT);
+			if (err) {
+				bt_l2cap_chan_disconnect(&br_chan->chan);
+			}
+		}
 		break;
 	default:
-		LOG_WRN("type 0x%04x unsupported", type);
-		err = -EINVAL;
+		/* Nothing to do */
 		break;
 	}
-done:
-	atomic_set_bit(l2cap->chan.flags, L2CAP_FLAG_SIG_INFO_DONE);
-	l2cap->info_ident = 0U;
-	return err;
 }
 
-static uint8_t get_fixed_channels_mask(void)
+static void l2cap_br_monitor_timeout(struct k_work *work)
 {
-	uint8_t mask = 0U;
+	struct bt_l2cap_br_chan *br_chan = BR_CHAN_MONITOR(work);
 
-	/* this needs to be enhanced if AMP Test Manager support is added */
-	STRUCT_SECTION_FOREACH(bt_l2cap_br_fixed_chan, fchan) {
-		mask |= BIT(fchan->cid);
+	if (!br_chan->chan.conn || br_chan->chan.conn->state != BT_CONN_CONNECTED) {
+		/* ACL connection is broken. */
+		return;
 	}
 
-	return mask;
-}
-
-static int l2cap_br_info_req(struct bt_l2cap_br *l2cap, uint8_t ident,
-			     struct net_buf *buf)
-{
-	struct bt_conn *conn = l2cap->chan.chan.conn;
-	struct bt_l2cap_info_req *req = (void *)buf->data;
-	struct bt_l2cap_info_rsp *rsp;
-	struct net_buf *rsp_buf;
-	struct bt_l2cap_sig_hdr *hdr_info;
-	uint16_t type;
-
-	if (buf->len < sizeof(*req)) {
-		LOG_ERR("Too small info req packet size");
-		return -EINVAL;
+	if (br_chan->state != BT_L2CAP_CONNECTED) {
+		/* The channel is not connected */
+		return;
 	}
 
-	rsp_buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
+	/* Restart the timer */
+	if (!atomic_test_bit(br_chan->flags, L2CAP_FLAG_RET_TIMER)) {
+		k_work_schedule(&br_chan->monitor_work, K_MSEC(br_chan->tx.monitor_timeout));
+	}
 
-	type = sys_le16_to_cpu(req->type);
-	LOG_DBG("type 0x%04x", type);
+	LOG_DBG("chan %p monitor timeout", br_chan);
 
-	hdr_info = net_buf_add(rsp_buf, sizeof(*hdr_info));
-	hdr_info->code = BT_L2CAP_INFO_RSP;
-	hdr_info->ident = ident;
+	if (br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_ERET) {
+		if (!atomic_test_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_P_CHANGED) &&
+		    atomic_test_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_P)) {
+			/* State: WAIT_F
+			 * Monitor Timer expires
+			 * Action: send RR(P=1) or RNR(P=1)
+			 */
+			int err;
 
-	rsp = net_buf_add(rsp_buf, sizeof(*rsp));
+			br_chan->retry_count++;
+			if (br_chan->tx.max_transmit &&
+			    (br_chan->retry_count > br_chan->tx.max_transmit)) {
+				bt_l2cap_chan_disconnect(&br_chan->chan);
+				return;
+			}
 
-	switch (type) {
-	case BT_L2CAP_INFO_FEAT_MASK:
-		rsp->type = sys_cpu_to_le16(BT_L2CAP_INFO_FEAT_MASK);
-		rsp->result = sys_cpu_to_le16(BT_L2CAP_INFO_SUCCESS);
-		net_buf_add_le32(rsp_buf, L2CAP_FEAT_FIXED_CHAN_MASK);
-		hdr_info->len = sys_cpu_to_le16(sizeof(*rsp) + sizeof(uint32_t));
-		break;
-	case BT_L2CAP_INFO_FIXED_CHAN:
-		rsp->type = sys_cpu_to_le16(BT_L2CAP_INFO_FIXED_CHAN);
-		rsp->result = sys_cpu_to_le16(BT_L2CAP_INFO_SUCCESS);
-		/* fixed channel mask protocol data is 8 octets wide */
-		(void)memset(net_buf_add(rsp_buf, 8), 0, 8);
-		rsp->data[0] = get_fixed_channels_mask();
+			LOG_WRN("Resend RR(P=1) on chan %p", br_chan);
 
-		hdr_info->len = sys_cpu_to_le16(sizeof(*rsp) + 8);
-		break;
-	default:
-		rsp->type = req->type;
-		rsp->result = sys_cpu_to_le16(BT_L2CAP_INFO_NOTSUPP);
-		hdr_info->len = sys_cpu_to_le16(sizeof(*rsp));
-		break;
-	}
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_P_CHANGED);
+			l2cap_br_start_timer(br_chan, BT_L2CAP_BR_TIMER_MONITOR, true);
 
-	l2cap_send(conn, BT_L2CAP_CID_BR_SIG, rsp_buf);
+			err = l2cap_br_send_s_frame(br_chan, BT_L2CAP_CONTROL_S_RR, K_NO_WAIT);
+			if (err) {
+				bt_l2cap_chan_disconnect(&br_chan->chan);
+			}
+		}
+	} else if ((br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_FC) ||
+		   (br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_RET)) {
+		/* Send S-frame with R=0.
+		 * Send S-Frame if there is not any pending I-frame
+		 */
+		int err;
 
-	return 0;
+		err = l2cap_br_send_s_frame(br_chan, BT_L2CAP_CONTROL_S_RR, K_NO_WAIT);
+		if (!err) {
+			atomic_clear_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_R);
+		} else {
+			bt_l2cap_chan_disconnect(&br_chan->chan);
+		}
+	}
 }
+#endif /* CONFIG_BT_L2CAP_RET_FC */
 
-void bt_l2cap_br_connected(struct bt_conn *conn)
+static bool l2cap_br_chan_add(struct bt_conn *conn, struct bt_l2cap_chan *chan,
+			      bt_l2cap_chan_destroy_t destroy)
 {
-	struct bt_l2cap_chan *chan;
+	struct bt_l2cap_br_chan *ch = l2cap_br_chan_alloc_cid(conn, chan);
 
-	STRUCT_SECTION_FOREACH(bt_l2cap_br_fixed_chan, fchan) {
-		struct bt_l2cap_br_chan *br_chan;
+	if (!ch) {
+		LOG_WRN("Unable to allocate L2CAP CID");
+		return false;
+	}
 
-		if (!fchan->accept) {
-			continue;
-		}
+	sys_slist_init(&ch->_pdu_tx_queue);
 
-		if (fchan->accept(conn, &chan) < 0) {
-			continue;
-		}
+	/* All dynamic channels have the destroy handler which makes sure that
+	 * the RTX work structure is properly released with a cancel sync.
+	 * The fixed signal channel is only removed when disconnected and the
+	 * disconnected handler is always called from the workqueue itself so
+	 * canceling from there should always succeed.
+	 */
+	k_work_init_delayable(&ch->rtx_work, l2cap_br_rtx_timeout);
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	k_work_init_delayable(&ch->ret_work, l2cap_br_ret_timeout);
+	k_work_init_delayable(&ch->monitor_work, l2cap_br_monitor_timeout);
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+	bt_l2cap_chan_add(conn, chan, destroy);
 
-		br_chan = BR_CHAN(chan);
+	return true;
+}
 
-		br_chan->rx.cid = fchan->cid;
-		br_chan->tx.cid = fchan->cid;
+int bt_l2cap_br_send_cb(struct bt_conn *conn, uint16_t cid, struct net_buf *buf,
+			bt_conn_tx_cb_t cb, void *user_data)
+{
+	struct bt_l2cap_chan *ch = bt_l2cap_br_lookup_tx_cid(conn, cid);
+	struct bt_l2cap_br_chan *br_chan;
+	struct bt_l2cap_hdr *hdr;
 
-		if (!l2cap_br_chan_add(conn, chan, NULL)) {
-			return;
-		}
+	if (ch == NULL) {
+		LOG_WRN("CID %d is not found on conn %p", cid, conn);
+		return -ESHUTDOWN;
+	}
 
-		/*
-		 * other fixed channels will be connected after Information
-		 * Response is received
-		 */
-		if (fchan->cid == BT_L2CAP_CID_BR_SIG) {
-			struct bt_l2cap_br *sig_ch;
+	br_chan = CONTAINER_OF(ch, struct bt_l2cap_br_chan, chan);
 
-			connect_fixed_channel(br_chan);
+	LOG_DBG("chan %p buf %p len %u", br_chan, buf, buf->len);
 
-			sig_ch = CONTAINER_OF(br_chan, struct bt_l2cap_br, chan);
-			l2cap_br_get_info(sig_ch, BT_L2CAP_INFO_FEAT_MASK);
-		}
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	if (br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_BASIC) {
+		hdr = net_buf_push(buf, sizeof(*hdr));
+		hdr->len = sys_cpu_to_le16(buf->len - sizeof(*hdr));
+		hdr->cid = sys_cpu_to_le16(cid);
 	}
-}
-
-void bt_l2cap_br_disconnected(struct bt_conn *conn)
-{
-	struct bt_l2cap_chan *chan, *next;
+#else
+	hdr = net_buf_push(buf, sizeof(*hdr));
+	hdr->len = sys_cpu_to_le16(buf->len - sizeof(*hdr));
+	hdr->cid = sys_cpu_to_le16(cid);
+#endif /* CONFIG_BT_L2CAP_RET_FC */
 
-	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&conn->channels, chan, next, node) {
-		bt_l2cap_br_chan_del(chan);
+	if (buf->user_data_size < sizeof(struct closure)) {
+		LOG_WRN("not enough room in user_data %d < %d pool %u",
+			buf->user_data_size,
+			CONFIG_BT_CONN_TX_USER_DATA_SIZE,
+			buf->pool_id);
+		return -EINVAL;
 	}
-}
 
-static struct bt_l2cap_server *l2cap_br_server_lookup_psm(uint16_t psm)
-{
-	struct bt_l2cap_server *server;
+	LOG_DBG("push PDU: cb %p userdata %p", cb, user_data);
 
-	SYS_SLIST_FOR_EACH_CONTAINER(&br_servers, server, node) {
-		if (server->psm == psm) {
-			return server;
-		}
-	}
+	make_closure(buf->user_data, cb, user_data);
+	sys_slist_append(&br_chan->_pdu_tx_queue, &buf->node);
+	raise_data_ready(br_chan);
 
-	return NULL;
+	return 0;
 }
 
-static void l2cap_br_conf_add_mtu(struct net_buf *buf, const uint16_t mtu)
+/* Send the buffer and release it in case of failure.
+ * Any other cleanup in failure to send should be handled by the disconnected
+ * handler.
+ */
+static inline void l2cap_send(struct bt_conn *conn, uint16_t cid,
+			      struct net_buf *buf)
 {
-	net_buf_add_u8(buf, BT_L2CAP_CONF_OPT_MTU);
-	net_buf_add_u8(buf, sizeof(mtu));
-	net_buf_add_le16(buf, mtu);
+	if (bt_l2cap_br_send_cb(conn, cid, buf, NULL, NULL)) {
+		net_buf_unref(buf);
+	}
 }
 
-static void l2cap_br_conf_add_opt(struct net_buf *buf, const struct bt_l2cap_conf_opt *opt)
+static void l2cap_br_chan_send_req(struct bt_l2cap_br_chan *chan,
+				   struct net_buf *buf, k_timeout_t timeout)
 {
-	net_buf_add_u8(buf, opt->type & BT_L2CAP_CONF_MASK);
-	net_buf_add_u8(buf, opt->len);
-	net_buf_add_mem(buf, opt->data, opt->len);
+
+	if (bt_l2cap_br_send_cb(chan->chan.conn, BT_L2CAP_CID_BR_SIG, buf,
+			     NULL, NULL)) {
+		net_buf_unref(buf);
+		return;
+	}
+
+	/* BLUETOOTH SPECIFICATION Version 4.2 [Vol 3, Part A] page 126:
+	 *
+	 * The value of this timer is implementation-dependent but the minimum
+	 * initial value is 1 second and the maximum initial value is 60
+	 * seconds. One RTX timer shall exist for each outstanding signaling
+	 * request, including each Echo Request. The timer disappears on the
+	 * final expiration, when the response is received, or the physical
+	 * link is lost.
+	 */
+	k_work_reschedule(&chan->rtx_work, timeout);
 }
 
-static void l2cap_br_conf(struct bt_l2cap_chan *chan)
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+static uint16_t get_pdu_len(struct bt_l2cap_br_chan *br_chan, struct net_buf *buf, bool start_seg)
 {
-	struct bt_l2cap_sig_hdr *hdr;
-	struct bt_l2cap_conf_req *conf;
-	struct net_buf *buf;
+	uint16_t pdu_len = buf->len;
+	uint16_t actual_mps;
 
-	buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
+	if (br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_BASIC) {
+		return pdu_len;
+	}
 
-	hdr = net_buf_add(buf, sizeof(*hdr));
-	hdr->code = BT_L2CAP_CONF_REQ;
-	hdr->ident = l2cap_br_get_ident();
-	conf = net_buf_add(buf, sizeof(*conf));
-	(void)memset(conf, 0, sizeof(*conf));
+	/* MPS is Max PDU Size.
+	 * PDU of I-frame includes the Control, L2CAP SDU Length (when present),
+	 * Information Payload, and frame check sequence (FCS) (when present) fields.
+	 */
+	actual_mps = br_chan->tx.mps - BT_L2CAP_RT_FC_SDU_HDR_SIZE(br_chan) -
+		     BT_L2CAP_RT_FC_SDU_TAIL_SIZE(br_chan);
 
-	conf->dcid = sys_cpu_to_le16(BR_CHAN(chan)->tx.cid);
-	/*
-	 * Add MTU option if app set non default BR/EDR L2CAP MTU,
-	 * otherwise sent empty configuration data meaning default MTU
-	 * to be used.
+	/* To get the max available space,
+	 * assume SDU field is no present.
 	 */
-	if (BR_CHAN(chan)->rx.mtu != L2CAP_BR_DEFAULT_MTU) {
-		l2cap_br_conf_add_mtu(buf, BR_CHAN(chan)->rx.mtu);
+	actual_mps += BT_L2CAP_RT_FC_SDU_LEN_SIZE;
+
+	if (pdu_len <= actual_mps) {
+		return pdu_len;
 	}
 
-	hdr->len = sys_cpu_to_le16(buf->len - sizeof(*hdr));
+	if (start_seg) {
+		/* The max mps length cannot meet the requirement.
+		 * Deduct the SDU length field for Max length could be used for seg.
+		 */
+		return actual_mps - BT_L2CAP_RT_FC_SDU_LEN_SIZE;
+	}
 
-	/*
-	 * TODO:
-	 * might be needed to start tracking number of configuration iterations
-	 * on both directions
-	 */
-	l2cap_br_chan_send_req(BR_CHAN(chan), buf, L2CAP_BR_CFG_TIMEOUT);
+	return actual_mps;
 }
 
-enum l2cap_br_conn_security_result {
-	L2CAP_CONN_SECURITY_PASSED,
-	L2CAP_CONN_SECURITY_REJECT,
-	L2CAP_CONN_SECURITY_PENDING
-};
+static int bt_l2cap_br_pack_s_frame_header(struct bt_l2cap_br_chan *br_chan, struct net_buf *buf,
+					   uint8_t s)
+{
+	struct bt_l2cap_hdr *hdr;
+	uint16_t std_control;
+	uint16_t enh_control;
+	uint32_t ext_control;
+	uint8_t f_bit = 0;
+	uint8_t r_bit = 0;
+	uint8_t p_bit = 0;
+	uint16_t pdu_len;
 
-/*
- * Security helper against channel connection.
- * Returns L2CAP_CONN_SECURITY_PASSED if:
- * - existing security on link is applicable for requested PSM in connection,
- * - legacy (non SSP) devices connecting with low security requirements,
- * Returns L2CAP_CONN_SECURITY_PENDING if:
- * - channel connection process is on hold since there were valid security
- *   conditions triggering authentication indirectly in subcall.
- * Returns L2CAP_CONN_SECURITY_REJECT if:
- * - bt_conn_set_security API returns < 0.
- */
+	pdu_len = BT_L2CAP_RT_FC_SDU_HDR_SIZE(br_chan) + BT_L2CAP_RT_FC_SDU_TAIL_SIZE(br_chan) -
+		  BT_L2CAP_RT_FC_SDU_LEN_SIZE;
 
-static enum l2cap_br_conn_security_result
-l2cap_br_conn_security(struct bt_l2cap_chan *chan, const uint16_t psm)
-{
-	int check;
-	struct bt_l2cap_br_chan *br_chan = BR_CHAN(chan);
+	hdr = net_buf_push(buf, sizeof(*hdr));
 
-	/* For SDP PSM there's no need to change existing security on link */
-	if (br_chan->required_sec_level == BT_SECURITY_L0) {
-		return L2CAP_CONN_SECURITY_PASSED;
-	}
+	hdr->len = sys_cpu_to_le16(pdu_len);
+	hdr->cid = sys_cpu_to_le16(br_chan->tx.cid);
 
-	/*
-	 * No link key needed for legacy devices (pre 2.1) and when low security
-	 * level is required.
-	 */
-	if (br_chan->required_sec_level == BT_SECURITY_L1 &&
-	    !BT_FEAT_HOST_SSP(chan->conn->br.features)) {
-		return L2CAP_CONN_SECURITY_PASSED;
+	if (s == BT_L2CAP_CONTROL_S_RR) {
+		if (atomic_test_and_clear_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_REJ_CHANGED) &&
+		    atomic_test_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_REJ)) {
+			s = BT_L2CAP_CONTROL_S_REJ;
+		}
 	}
 
-	switch (br_chan->required_sec_level) {
-	case BT_SECURITY_L4:
-	case BT_SECURITY_L3:
-	case BT_SECURITY_L2:
-		break;
-	default:
-		/*
-		 * For non SDP PSM connections GAP's Security Mode 4 requires at
-		 * least unauthenticated link key and enabled encryption if
-		 * remote supports SSP before any L2CAP CoC traffic. So preset
-		 * local to MEDIUM security to trigger it if needed.
-		 */
-		if (BT_FEAT_HOST_SSP(chan->conn->br.features)) {
-			br_chan->required_sec_level = BT_SECURITY_L2;
+	if (s == BT_L2CAP_CONTROL_S_RR) {
+		if (atomic_test_and_clear_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_P)) {
+			f_bit = 1;
+		} else if (atomic_test_and_clear_bit(br_chan->flags,
+						     L2CAP_FLAG_SEND_FRAME_P_CHANGED) &&
+			   atomic_test_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_P)) {
+			p_bit = 1;
+		} else if (atomic_test_and_clear_bit(br_chan->flags,
+						     L2CAP_FLAG_LOCAL_BUSY_CHANGED) &&
+			   atomic_test_bit(br_chan->flags, L2CAP_FLAG_LOCAL_BUSY)) {
+			s = BT_L2CAP_CONTROL_S_RNR;
+		}
+
+		if (atomic_test_bit(br_chan->flags, L2CAP_FLAG_LOCAL_BUSY)) {
+			s = BT_L2CAP_CONTROL_S_RNR;
 		}
-		break;
 	}
 
-	check = bt_conn_set_security(chan->conn, br_chan->required_sec_level);
+	if (atomic_test_bit(br_chan->flags, L2CAP_FLAG_LOCAL_BUSY) &&
+	    (s != BT_L2CAP_CONTROL_S_RNR)) {
+		LOG_WRN("Local is busy and cannot send S-frame on %p", br_chan);
+		return -EINVAL;
+	}
 
-	/*
-	 * Check case when on existing connection security level already covers
-	 * channel (service) security requirements against link security and
-	 * bt_conn_set_security API returns 0 what implies also there was no
-	 * need to trigger authentication.
-	 */
-	if (check == 0 &&
-	    chan->conn->sec_level >= br_chan->required_sec_level) {
-		return L2CAP_CONN_SECURITY_PASSED;
+	if (atomic_test_and_clear_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_R_CHANGED) &&
+	    atomic_test_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_R)) {
+		r_bit = 1;
 	}
 
-	/*
-	 * If 'check' still holds 0, it means local host just sent HCI
-	 * authentication command to start procedure to increase link security
-	 * since service/profile requires that.
-	 */
-	if (check == 0) {
-		/*
-		 * General Bonding refers to the process of performing bonding
-		 * during connection setup or channel establishment procedures
-		 * as a precursor to accessing a service.
-		 * For current case, it is dedicated bonding.
-		 */
-		atomic_set_bit(chan->conn->flags, BT_CONN_BR_GENERAL_BONDING);
-		return L2CAP_CONN_SECURITY_PENDING;
+	if (br_chan->tx.mode != BT_L2CAP_BR_LINK_MODE_STREAM) {
+		br_chan->req_seq = br_chan->expected_tx_seq;
+	} else {
+		br_chan->req_seq = 0;
 	}
 
-	/*
-	 * For any other values in 'check' it means there was internal
-	 * validation condition forbidding to start authentication at this
-	 * moment.
-	 */
-	return L2CAP_CONN_SECURITY_REJECT;
+	if ((br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_ERET) ||
+	    (br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_STREAM)) {
+		if (br_chan->tx.extended_control) {
+			/* Space occupied for extended control field. */
+			ext_control = sys_cpu_to_le32(BT_L2CAP_S_FRAME_EXT_CONTROL_SET(
+				f_bit, br_chan->req_seq, s, p_bit));
+			net_buf_add_le32(buf, ext_control);
+		} else {
+			/* Space occupied for enhanced control field. */
+			enh_control = sys_cpu_to_le16(BT_L2CAP_S_FRAME_ENH_CONTROL_SET(
+				s, p_bit, f_bit, br_chan->req_seq));
+			net_buf_add_le16(buf, enh_control);
+		}
+	} else {
+		/* Space occupied for standard control field. */
+		std_control = sys_cpu_to_le16(
+			BT_L2CAP_S_FRAME_STD_CONTROL_SET(s, r_bit, br_chan->req_seq));
+		net_buf_add_le16(buf, std_control);
+	}
+
+	return 0;
 }
 
-static void l2cap_br_send_conn_rsp(struct bt_conn *conn, uint16_t scid,
-				  uint16_t dcid, uint8_t ident, uint16_t result)
+static void bt_l2cap_br_pack_i_frame_header(struct bt_l2cap_br_chan *br_chan, struct net_buf *buf,
+					    uint8_t pdu_len, uint8_t sar, uint8_t tx_seq)
 {
-	struct net_buf *buf;
-	struct bt_l2cap_conn_rsp *rsp;
-	struct bt_l2cap_sig_hdr *hdr;
-
-	buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
+	struct bt_l2cap_hdr *hdr;
+	uint16_t std_control;
+	uint16_t enh_control;
+	uint32_t ext_control;
+	uint8_t f_bit = 0;
+	uint8_t r_bit = 0;
 
-	hdr = net_buf_add(buf, sizeof(*hdr));
-	hdr->code = BT_L2CAP_CONN_RSP;
-	hdr->ident = ident;
-	hdr->len = sys_cpu_to_le16(sizeof(*rsp));
+	/* HDR space has been reserved */
+	hdr = net_buf_push(buf, sizeof(*hdr));
 
-	rsp = net_buf_add(buf, sizeof(*rsp));
-	rsp->dcid = sys_cpu_to_le16(dcid);
-	rsp->scid = sys_cpu_to_le16(scid);
-	rsp->result = sys_cpu_to_le16(result);
+	hdr->len = sys_cpu_to_le16(pdu_len);
+	hdr->cid = sys_cpu_to_le16(br_chan->tx.cid);
 
-	if (result == BT_L2CAP_BR_PENDING) {
-		rsp->status = sys_cpu_to_le16(BT_L2CAP_CS_AUTHEN_PEND);
-	} else {
-		rsp->status = sys_cpu_to_le16(BT_L2CAP_CS_NO_INFO);
+	if (atomic_test_and_clear_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_P)) {
+		f_bit = 1;
 	}
 
-	l2cap_send(conn, BT_L2CAP_CID_BR_SIG, buf);
-}
-
-static int l2cap_br_conn_req_reply(struct bt_l2cap_chan *chan, uint16_t result)
-{
-	/* Send response to connection request only when in acceptor role */
-	if (!atomic_test_bit(BR_CHAN(chan)->flags, L2CAP_FLAG_CONN_ACCEPTOR)) {
-		return -ESRCH;
+	if (atomic_test_and_clear_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_R_CHANGED) &&
+	    atomic_test_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_R)) {
+		r_bit = 1;
 	}
 
-	l2cap_br_send_conn_rsp(chan->conn, BR_CHAN(chan)->tx.cid,
-			       BR_CHAN(chan)->rx.cid, BR_CHAN(chan)->ident, result);
-	BR_CHAN(chan)->ident = 0U;
+	if (br_chan->tx.mode != BT_L2CAP_BR_LINK_MODE_STREAM) {
+		br_chan->req_seq = br_chan->expected_tx_seq;
+	} else {
+		br_chan->req_seq = 0;
+	}
 
-	return 0;
+	if ((br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_ERET) ||
+	    (br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_STREAM)) {
+		if (br_chan->tx.extended_control) {
+			/* Space occupied for extended control field. */
+			ext_control = BT_L2CAP_I_FRAME_EXT_CONTROL_SET(f_bit, tx_seq, sar,
+								       br_chan->req_seq);
+			net_buf_add_le32(buf, ext_control);
+		} else {
+			/* Space occupied for enhanced control field. */
+			enh_control = BT_L2CAP_I_FRAME_ENH_CONTROL_SET(tx_seq, f_bit,
+								       br_chan->req_seq, sar);
+			net_buf_add_le16(buf, enh_control);
+		}
+	} else {
+		/* Space occupied for standard control field. */
+		std_control =
+			BT_L2CAP_I_FRAME_STD_CONTROL_SET(tx_seq, r_bit, br_chan->req_seq, sar);
+		net_buf_add_le16(buf, std_control);
+	}
 }
 
-#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
-#if defined(CONFIG_BT_L2CAP_LOG_LEVEL_DBG)
-void bt_l2cap_br_chan_set_state_debug(struct bt_l2cap_chan *chan,
-				   bt_l2cap_chan_state_t state,
-				   const char *func, int line)
+static struct net_buf *l2cap_br_get_next_sdu(struct bt_l2cap_br_chan *br_chan)
 {
-	struct bt_l2cap_br_chan *br_chan;
+	struct net_buf *sdu, *next;
 
-	br_chan = BR_CHAN(chan);
-
-	LOG_DBG("chan %p psm 0x%04x %s -> %s", chan, br_chan->psm,
-		bt_l2cap_chan_state_str(br_chan->state), bt_l2cap_chan_state_str(state));
+	if (br_chan->_pdu_buf) {
+		return br_chan->_pdu_buf;
+	}
 
-	/* check transitions validness */
-	switch (state) {
-	case BT_L2CAP_DISCONNECTED:
-		/* regardless of old state always allows this state */
-		break;
-	case BT_L2CAP_CONNECTING:
-		if (br_chan->state != BT_L2CAP_DISCONNECTED) {
-			LOG_WRN("%s()%d: invalid transition", func, line);
-		}
-		break;
-	case BT_L2CAP_CONFIG:
-		if (br_chan->state != BT_L2CAP_CONNECTING) {
-			LOG_WRN("%s()%d: invalid transition", func, line);
-		}
-		break;
-	case BT_L2CAP_CONNECTED:
-		if (br_chan->state != BT_L2CAP_CONFIG &&
-		    br_chan->state != BT_L2CAP_CONNECTING) {
-			LOG_WRN("%s()%d: invalid transition", func, line);
+	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&br_chan->_pdu_tx_queue, sdu, next, node) {
+		if (sdu->len) {
+			return sdu;
 		}
-		break;
-	case BT_L2CAP_DISCONNECTING:
-		if (br_chan->state != BT_L2CAP_CONFIG &&
-		    br_chan->state != BT_L2CAP_CONNECTED) {
-			LOG_WRN("%s()%d: invalid transition", func, line);
+
+		if (L2CAP_BR_IS_S_FRAME(closure_data(sdu->user_data))) {
+			return sdu;
 		}
-		break;
-	default:
-		LOG_ERR("%s()%d: unknown (%u) state was set", func, line, state);
-		return;
 	}
 
-	br_chan->state = state;
-}
-#else
-void bt_l2cap_br_chan_set_state(struct bt_l2cap_chan *chan,
-			     bt_l2cap_chan_state_t state)
-{
-	BR_CHAN(chan)->state = state;
+	return NULL;
 }
-#endif /* CONFIG_BT_L2CAP_LOG_LEVEL_DBG */
-#endif /* CONFIG_BT_L2CAP_DYNAMIC_CHANNEL */
 
-void bt_l2cap_br_chan_del(struct bt_l2cap_chan *chan)
+static bool l2cap_br_send_i_frame(struct bt_l2cap_br_chan *br_chan, struct net_buf *sdu)
 {
-	const struct bt_l2cap_chan_ops *ops = chan->ops;
-	struct bt_l2cap_br_chan *br_chan = CONTAINER_OF(chan, struct bt_l2cap_br_chan, chan);
-
-	LOG_DBG("conn %p chan %p", chan->conn, chan);
+	if (atomic_test_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_R)) {
+		return false;
+	}
 
-	if (!chan->conn) {
-		goto destroy;
+	if (atomic_test_bit(br_chan->flags, L2CAP_FLAG_RET_REQ_I_FRAME)) {
+		if (l2cap_br_find_srej(br_chan)) {
+			return true;
+		}
 	}
 
-	cancel_data_ready(br_chan);
+	if (atomic_test_bit(br_chan->flags, L2CAP_FLAG_RET_I_FRAME) &&
+	    (atomic_test_bit(br_chan->flags, L2CAP_FLAG_PDU_RETRANS) ||
+	     atomic_test_bit(br_chan->flags, L2CAP_FLAG_REQ_SEQ_UPDATED))) {
+		return true;
+	}
 
-	/* Remove buffers on the PDU TX queue. */
-	while (chan_has_data(br_chan)) {
-		struct net_buf *buf = k_fifo_get(&br_chan->_pdu_tx_queue, K_NO_WAIT);
+	if (atomic_test_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_P)) {
+		return false;
+	}
 
-		net_buf_unref(buf);
+	if (atomic_test_bit(br_chan->flags, L2CAP_FLAG_REMOTE_BUSY)) {
+		return false;
 	}
 
-	if (ops->disconnected) {
-		ops->disconnected(chan);
+	if (!atomic_test_bit(br_chan->flags, L2CAP_FLAG_NEW_I_FRAME)) {
+		return false;
 	}
 
-	chan->conn = NULL;
+	if (!sdu) {
+		return false;
+	}
 
-destroy:
-#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
-	/* Reset internal members of common channel */
-	bt_l2cap_br_chan_set_state(chan, BT_L2CAP_DISCONNECTED);
-	BR_CHAN(chan)->psm = 0U;
-#endif
-	if (chan->destroy) {
-		chan->destroy(chan);
+	if (bt_l2cap_br_get_outstanding_count(br_chan) >= br_chan->tx.max_window) {
+		return false;
 	}
 
-	if (ops->released) {
-		ops->released(chan);
+	if (k_fifo_peek_head(&br_chan->_free_tx_win)) {
+		return true;
 	}
+
+	return false;
 }
 
-static void l2cap_br_conn_req(struct bt_l2cap_br *l2cap, uint8_t ident,
-			      struct net_buf *buf)
+static struct net_buf *l2cap_br_ret_fc_data_pull(struct bt_conn *conn, size_t amount,
+						 size_t *length)
 {
-	struct bt_conn *conn = l2cap->chan.chan.conn;
-	struct bt_l2cap_chan *chan;
-	struct bt_l2cap_server *server;
-	struct bt_l2cap_conn_req *req = (void *)buf->data;
-	uint16_t psm, scid, result;
-	struct bt_l2cap_br_chan *br_chan;
+	const sys_snode_t *pdu_ready = sys_slist_peek_head(&conn->l2cap_data_ready);
 
-	if (buf->len < sizeof(*req)) {
-		LOG_ERR("Too small L2CAP conn req packet size");
-		return;
+	if (!pdu_ready) {
+		LOG_DBG("nothing to send on this conn");
+		return NULL;
 	}
 
-	psm = sys_le16_to_cpu(req->psm);
-	scid = sys_le16_to_cpu(req->scid);
-
-	LOG_DBG("psm 0x%02x scid 0x%04x", psm, scid);
+	struct bt_l2cap_br_chan *br_chan =
+		CONTAINER_OF(pdu_ready, struct bt_l2cap_br_chan, _pdu_ready);
 
-	/* Check if there is a server registered */
-	server = l2cap_br_server_lookup_psm(psm);
-	if (!server) {
-		result = BT_L2CAP_BR_ERR_PSM_NOT_SUPP;
-		goto no_chan;
+	if (br_chan->_pdu_buf && bt_buf_has_view(br_chan->_pdu_buf)) {
+		LOG_ERR("already have view on %p", br_chan->_pdu_buf);
+		return NULL;
 	}
 
-	/*
-	 * Report security violation for non SDP channel without encryption when
-	 * remote supports SSP.
+	/* Leave the PDU buffer in the queue until we have sent all its
+	 * fragments.
 	 */
-	if (server->sec_level != BT_SECURITY_L0 &&
-	    BT_FEAT_HOST_SSP(conn->br.features) && !conn->encrypt) {
-		result = BT_L2CAP_BR_ERR_SEC_BLOCK;
-		goto no_chan;
-	}
+	struct net_buf *pdu = l2cap_br_get_next_sdu(br_chan);
+	struct net_buf *send_buf = NULL;
+
+	if (br_chan->_pdu_remaining == 0) {
+		struct bt_l2cap_br_window *tx_win;
+		bool first = true;
+		uint8_t s_bit = BT_L2CAP_CONTROL_S_RR;
+		bool alloc = false;
+
+		if (pdu && !pdu->len && L2CAP_BR_IS_S_FRAME(closure_data(pdu->user_data))) {
+			/* It is a S-frame */
+			s_bit = L2CAP_BR_GET_S_BIT(closure_data(pdu->user_data));
+			alloc = true;
+		}
 
-	if (!L2CAP_BR_CID_IS_DYN(scid)) {
-		result = BT_L2CAP_BR_ERR_INVALID_SCID;
-		goto no_chan;
-	}
+		if ((atomic_test_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_R) &&
+		     atomic_test_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_R_CHANGED)) ||
+		    (atomic_test_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_REJ) &&
+		     atomic_test_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_REJ_CHANGED)) ||
+		    (atomic_test_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_P) &&
+		     atomic_test_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_P_CHANGED)) ||
+		    (atomic_test_bit(br_chan->flags, L2CAP_FLAG_LOCAL_BUSY) &&
+		     atomic_test_bit(br_chan->flags, L2CAP_FLAG_LOCAL_BUSY_CHANGED)) ||
+		    atomic_test_bit(br_chan->flags, L2CAP_FLAG_SEND_S_FRAME)) {
+			alloc = true;
+		}
 
-	chan = bt_l2cap_br_lookup_tx_cid(conn, scid);
-	if (chan) {
-		/*
-		 * we have a chan here but this is due to SCID being already in
-		 * use so it is not channel we are suppose to pass to
-		 * l2cap_br_conn_req_reply as wrong DCID would be used
-		 */
-		result = BT_L2CAP_BR_ERR_SCID_IN_USE;
-		goto no_chan;
-	}
+		if (atomic_test_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_P) &&
+		    !l2cap_br_send_i_frame(br_chan, pdu)) {
+			alloc = true;
+		}
 
-	/*
-	 * Request server to accept the new connection and allocate the
-	 * channel. If no free channels available for PSM server reply with
-	 * proper result and quit since chan pointer is uninitialized then.
-	 */
-	if (server->accept(conn, server, &chan) < 0) {
-		result = BT_L2CAP_BR_ERR_NO_RESOURCES;
-		goto no_chan;
-	}
+		if (alloc) {
+			int err;
+
+			/* Send S-Frame with R bit set. */
+			send_buf = bt_l2cap_create_pdu_timeout(&br_tx_pool, 0, K_NO_WAIT);
+			if (send_buf == NULL) {
+				/* No buffer can be used for transmission.
+				 * Waiting for buffer available.
+				 */
+				LOG_WRN("no buf for sending S-frame on %p", br_chan);
+				return NULL;
+			}
 
-	br_chan = BR_CHAN(chan);
-	br_chan->required_sec_level = server->sec_level;
+			err = bt_l2cap_br_pack_s_frame_header(br_chan, send_buf, s_bit);
+			if (err < 0) {
+				net_buf_unref(send_buf);
+				LOG_WRN("Cannot sending S-frame on %p", br_chan);
+				return NULL;
+			}
 
-	l2cap_br_chan_add(conn, chan, l2cap_br_chan_destroy);
-	BR_CHAN(chan)->tx.cid = scid;
-	br_chan->ident = ident;
-	bt_l2cap_br_chan_set_state(chan, BT_L2CAP_CONNECTING);
-	atomic_set_bit(BR_CHAN(chan)->flags, L2CAP_FLAG_CONN_ACCEPTOR);
+			atomic_clear_bit(br_chan->flags, L2CAP_FLAG_SEND_S_FRAME);
 
-	/* Disable fragmentation of l2cap rx pdu */
-	BR_CHAN(chan)->rx.mtu = MIN(BR_CHAN(chan)->rx.mtu, BT_L2CAP_RX_MTU);
+			if (BT_L2CAP_RT_FC_SDU_TAIL_SIZE(br_chan)) {
+				uint16_t fcs =
+					crc16_reflect(0xa001, 0, send_buf->data, send_buf->len);
 
-	switch (l2cap_br_conn_security(chan, psm)) {
-	case L2CAP_CONN_SECURITY_PENDING:
-		result = BT_L2CAP_BR_PENDING;
-		/* TODO: auth timeout */
-		break;
-	case L2CAP_CONN_SECURITY_PASSED:
-		result = BT_L2CAP_BR_SUCCESS;
-		break;
-	case L2CAP_CONN_SECURITY_REJECT:
-	default:
-		result = BT_L2CAP_BR_ERR_SEC_BLOCK;
-		break;
-	}
-	/* Reply on connection request as acceptor */
-	l2cap_br_conn_req_reply(chan, result);
+				net_buf_add_le16(send_buf, fcs);
+			}
+			br_chan->_pdu_remaining = send_buf->len;
+			br_chan->_pdu_buf = send_buf;
 
-	if (result != BT_L2CAP_BR_SUCCESS) {
-		/* Disconnect link when security rules were violated */
-		if (result == BT_L2CAP_BR_ERR_SEC_BLOCK) {
-			bt_conn_disconnect(conn, BT_HCI_ERR_AUTH_FAIL);
-		} else if (result == BT_L2CAP_BR_PENDING) {
-			/* Recover the ident when conn is pending */
-			br_chan->ident = ident;
+			make_closure(send_buf->user_data, NULL, NULL);
+
+			if (pdu && !pdu->len && L2CAP_BR_IS_S_FRAME(closure_data(pdu->user_data))) {
+				l2cap_br_sdu_is_done(br_chan, pdu, 0);
+			}
+
+			goto done;
 		}
 
-		return;
-	}
+		if (atomic_test_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_R)) {
+			/* No I-frames shall be transmitted if the last
+			 * RetransmissionDisableBit (R) received is set to one.
+			 */
+			LOG_DBG("Stop to send I-frame on %p", br_chan);
+			lower_data_ready(br_chan);
+			return NULL;
+		}
 
-	bt_l2cap_br_chan_set_state(chan, BT_L2CAP_CONFIG);
-	l2cap_br_conf(chan);
-	return;
+		if (atomic_test_bit(br_chan->flags, L2CAP_FLAG_REMOTE_BUSY)) {
+			/* RemoteBusy = TRUE, Pending sending data
+			 */
+			LOG_DBG("Remote is busy, cannot send I-frame on %p", br_chan);
+			lower_data_ready(br_chan);
+			return NULL;
+		}
 
-no_chan:
-	l2cap_br_send_conn_rsp(conn, scid, 0, ident, result);
-}
+		/* Found SREJ frame */
+		if (atomic_test_bit(br_chan->flags, L2CAP_FLAG_RET_REQ_I_FRAME)) {
+			tx_win = l2cap_br_find_srej(br_chan);
+			if (tx_win) {
+				first = false;
+				goto send_i_frame;
+			}
+		}
 
-static void l2cap_br_conf_rsp(struct bt_l2cap_br *l2cap, uint8_t ident,
-			      uint16_t len, struct net_buf *buf)
-{
-	struct bt_conn *conn = l2cap->chan.chan.conn;
-	struct bt_l2cap_chan *chan;
-	struct bt_l2cap_conf_rsp *rsp = (void *)buf->data;
-	uint16_t flags, scid, result, opt_len;
-	struct bt_l2cap_br_chan *br_chan;
+		/* Retransmission i-Frame. Or, if seq_req has been updated, send next I-frame*/
+		if (atomic_test_bit(br_chan->flags, L2CAP_FLAG_RET_I_FRAME) &&
+		    (atomic_test_and_clear_bit(br_chan->flags, L2CAP_FLAG_PDU_RETRANS) ||
+		     atomic_test_and_clear_bit(br_chan->flags, L2CAP_FLAG_REQ_SEQ_UPDATED))) {
+			tx_win = (void *)sys_slist_peek_head(&br_chan->_pdu_outstanding);
+			if (tx_win) {
+				first = false;
+				goto send_i_frame;
+			}
+		}
 
-	if (buf->len < sizeof(*rsp)) {
-		LOG_ERR("Too small L2CAP conf rsp packet size");
-		return;
-	}
+		if (atomic_test_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_P)) {
+			/* Cannot send any new I-frames if waiting for F bit.
+			 * New I-frames cannot be sent while in the WAIT_F
+			 * state to prevent the situation where retransmission of
+			 * I-frames could result in the channel being disconnected.
+			 */
+			LOG_DBG("Waiting for F flag, cannot send I-frame on %p", br_chan);
+			lower_data_ready(br_chan);
+			return NULL;
+		}
 
-	flags = sys_le16_to_cpu(rsp->flags);
-	scid = sys_le16_to_cpu(rsp->scid);
-	result = sys_le16_to_cpu(rsp->result);
-	opt_len = len - sizeof(*rsp);
+		/* Cannot send out new I-frame */
+		if (!atomic_test_bit(br_chan->flags, L2CAP_FLAG_NEW_I_FRAME)) {
+			/* Sending is blocked
+			 */
+			LOG_DBG("Sending is blocked, cannot send I-frame on %p", br_chan);
+			lower_data_ready(br_chan);
+			return NULL;
+		}
 
-	LOG_DBG("scid 0x%04x flags 0x%02x result 0x%02x len %u", scid, flags, result, opt_len);
+		/* Check whether all PDUs have been sent. But not of all are confirmed. */
+		if (!pdu) {
+			/* No pending I-frame needs to be sent
+			 */
+			LOG_DBG("No pending I-frame needs to be sent on %p", br_chan);
+			lower_data_ready(br_chan);
+			return NULL;
+		}
 
-	chan = bt_l2cap_br_lookup_rx_cid(conn, scid);
-	if (!chan) {
-		LOG_ERR("channel mismatch!");
-		return;
-	}
+		tx_win = l2cap_br_find_window(br_chan);
+		if (!tx_win) {
+			/* No more window for sending I-frame PDU.
+			 * Remove the channel from the ready-list, it will be added
+			 * back later when the S-frame PDU has been received.
+			 */
+			LOG_DBG("no more window for sending I-frame on %p", br_chan);
+			lower_data_ready(br_chan);
+			return NULL;
+		}
 
-	br_chan = BR_CHAN(chan);
+send_i_frame:
+		send_buf = bt_l2cap_create_pdu_timeout(&br_tx_pool, 0, K_NO_WAIT);
+		if (send_buf == NULL) {
+			/* No buffer can be used for transmission.
+			 * Waiting for buffer available.
+			 */
+			LOG_WRN("no buf for sending I-frame on %p", br_chan);
+			/* Maybe we can disconnect channel here if retransmission I-frame. */
 
-	/* Release RTX work since got the response */
-	k_work_cancel_delayable(&br_chan->rtx_work);
+			/* Free allocated tx_win. */
+			l2cap_br_free_window(br_chan, tx_win);
+			return NULL;
+		}
 
-	/*
-	 * TODO: handle other results than success and parse response data if
-	 * available
-	 */
-	switch (result) {
-	case BT_L2CAP_CONF_SUCCESS:
-		atomic_set_bit(br_chan->flags, L2CAP_FLAG_CONN_LCONF_DONE);
+		make_closure(send_buf->user_data, NULL, NULL);
 
-		if (br_chan->state == BT_L2CAP_CONFIG &&
-		    atomic_test_bit(br_chan->flags,
-				    L2CAP_FLAG_CONN_RCONF_DONE)) {
-			LOG_DBG("scid 0x%04x rx MTU %u dcid 0x%04x tx MTU %u", br_chan->rx.cid,
-				br_chan->rx.mtu, br_chan->tx.cid, br_chan->tx.mtu);
+		uint16_t pdu_len;
+		uint16_t actual_pdu_len;
+		uint8_t sar;
+		uint16_t fcs;
 
-			bt_l2cap_br_chan_set_state(chan, BT_L2CAP_CONNECTED);
-			if (chan->ops && chan->ops->connected) {
-				chan->ops->connected(chan);
-			}
-		}
-		break;
-	default:
-		/* currently disconnect channel on non success result */
-		bt_l2cap_chan_disconnect(chan);
-		break;
-	}
-}
+		if (first) {
+			bool last_seg;
+			bool start_seg;
 
-int bt_l2cap_br_server_register(struct bt_l2cap_server *server)
-{
-	if (server->psm < L2CAP_BR_PSM_START || !server->accept) {
-		return -EINVAL;
-	}
+			start_seg = br_chan->_sdu_total_len ? false : true;
 
-	/* PSM must be odd and lsb of upper byte must be 0 */
-	if ((server->psm & 0x0101) != 0x0001) {
-		return -EINVAL;
-	}
+			if (start_seg) {
+				br_chan->_sdu_total_len = pdu->len;
+			} else {
+				if (br_chan->_sdu_total_len <= pdu->len) {
+					start_seg = true;
+				}
+			}
 
-	if (server->sec_level > BT_SECURITY_L4) {
-		return -EINVAL;
-	} else if (server->sec_level == BT_SECURITY_L0 &&
-		   server->psm != L2CAP_BR_PSM_SDP) {
-		server->sec_level = BT_SECURITY_L1;
-	}
+			net_buf_simple_save(&pdu->b, &tx_win->sdu_state);
 
-	/* Check if given PSM is already in use */
-	if (l2cap_br_server_lookup_psm(server->psm)) {
-		LOG_DBG("PSM already registered");
-		return -EADDRINUSE;
-	}
+			pdu_len = get_pdu_len(br_chan, pdu, start_seg);
 
-	LOG_DBG("PSM 0x%04x", server->psm);
+			actual_pdu_len = pdu_len + BT_L2CAP_RT_FC_SDU_HDR_SIZE(br_chan) +
+					 BT_L2CAP_RT_FC_SDU_TAIL_SIZE(br_chan);
 
-	sys_slist_append(&br_servers, &server->node);
+			last_seg = pdu_len == pdu->len;
 
-	return 0;
-}
+			sar = start_seg ? (last_seg ? BT_L2CAP_CONTROL_SAR_UNSEG
+						    : BT_L2CAP_CONTROL_SAR_START)
+					: (last_seg ? BT_L2CAP_CONTROL_SAR_END
+						    : BT_L2CAP_CONTROL_SAR_CONTI);
+			if (sar == BT_L2CAP_CONTROL_SAR_START) {
+				net_buf_push_le16(pdu, pdu->len);
+				pdu_len += BT_L2CAP_RT_FC_SDU_LEN_SIZE;
+			} else {
+				/* Remove the SDU length from Header */
+				actual_pdu_len -= BT_L2CAP_RT_FC_SDU_LEN_SIZE;
+			}
 
-static void l2cap_br_send_reject(struct bt_conn *conn, uint8_t ident,
-				 uint16_t reason, void *data, uint8_t data_len)
-{
-	struct bt_l2cap_cmd_reject *rej;
-	struct bt_l2cap_sig_hdr *hdr;
-	struct net_buf *buf;
+			if (net_buf_tailroom(send_buf) < actual_pdu_len) {
+				LOG_ERR("Tailroom of the buffer cannot be filled %zu / %zu",
+					net_buf_tailroom(send_buf), actual_pdu_len);
+				__ASSERT(false, "Tailroom of the buffer cannot be filled %zu / %zu",
+					 net_buf_tailroom(send_buf), actual_pdu_len);
+				net_buf_unref(send_buf);
+				l2cap_br_free_window(br_chan, tx_win);
+				return NULL;
+			}
 
-	buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
+			if (br_chan->tx.mode != BT_L2CAP_BR_LINK_MODE_STREAM) {
+				br_chan->req_seq = br_chan->expected_tx_seq;
+			} else {
+				br_chan->req_seq = 0;
+			}
 
-	hdr = net_buf_add(buf, sizeof(*hdr));
-	hdr->code = BT_L2CAP_CMD_REJECT;
-	hdr->ident = ident;
-	hdr->len = sys_cpu_to_le16(sizeof(*rej) + data_len);
+			br_chan->tx_seq = br_chan->next_tx_seq;
+			tx_win->tx_seq = br_chan->tx_seq;
+			tx_win->data = pdu->data;
+			tx_win->len = pdu_len;
+			tx_win->srej = false;
+			tx_win->sar = sar;
+			tx_win->transmit_counter = 1;
+			tx_win->sdu_total_len = br_chan->_sdu_total_len;
+			tx_win->sdu = pdu;
+
+			LOG_DBG("Sending I-frame %u: buf %p chan %p len %zu", tx_win->tx_seq, pdu,
+				br_chan, pdu_len);
+		} else {
+			bool disconnect = false;
+
+			pdu_len = tx_win->len;
+			actual_pdu_len = pdu_len + BT_L2CAP_RT_FC_SDU_HDR_SIZE(br_chan) +
+					 BT_L2CAP_RT_FC_SDU_TAIL_SIZE(br_chan);
+			sar = tx_win->sar;
+			/* Remove the SDU length from Header.
+			 * Do not care SDU length, it has been handled in the first time.
+			 */
+			actual_pdu_len -= BT_L2CAP_RT_FC_SDU_LEN_SIZE;
+
+			tx_win->transmit_counter++;
+			tx_win->srej = false;
+
+			if (br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_ERET) {
+				if (br_chan->tx.max_transmit &&
+				    (tx_win->transmit_counter > br_chan->tx.max_transmit)) {
+					disconnect = true;
+				}
+			} else {
+				if (tx_win->transmit_counter > br_chan->tx.max_transmit) {
+					disconnect = true;
+				}
+			}
 
-	rej = net_buf_add(buf, sizeof(*rej));
-	rej->reason = sys_cpu_to_le16(reason);
+			if (disconnect) {
+				/* If the TransmitCounter is equal to MaxTransmit this channel to
+				 * the peer entity shall be assumed lost. The channel shall move
+				 * to the CLOSED state and appropriate action shall be taken to
+				 * report this to the upper layers.
+				 */
+				bt_l2cap_br_chan_disconnect(&br_chan->chan);
+				net_buf_unref(send_buf);
+				return NULL;
+			}
 
-	/*
-	 * optional data if available must be already in little-endian format
-	 * made by caller.and be compliant with Core 4.2 [Vol 3, Part A, 4.1,
-	 * table 4.4]
-	 */
-	if (data) {
-		net_buf_add_mem(buf, data, data_len);
-	}
+			LOG_WRN("Retransmission I-frame %u: buf %p chan %p len %zu", tx_win->tx_seq,
+				pdu, br_chan, pdu_len);
+		}
 
-	l2cap_send(conn, BT_L2CAP_CID_BR_SIG, buf);
-}
+		bt_l2cap_br_pack_i_frame_header(br_chan, send_buf, actual_pdu_len, sar,
+						tx_win->tx_seq);
 
-static uint16_t l2cap_br_conf_opt_mtu(struct bt_l2cap_chan *chan,
-				   struct net_buf *buf, size_t len)
-{
-	uint16_t mtu, result = BT_L2CAP_CONF_SUCCESS;
-	struct bt_l2cap_conf_opt_mtu *opt_mtu;
+		net_buf_add_mem(send_buf, tx_win->data, pdu_len);
 
-	/* Core 4.2 [Vol 3, Part A, 5.1] MTU payload length */
-	if (len != sizeof(*opt_mtu)) {
-		LOG_ERR("tx MTU length %zu invalid", len);
-		result = BT_L2CAP_CONF_REJECT;
-		goto done;
-	}
+		if (BT_L2CAP_RT_FC_SDU_TAIL_SIZE(br_chan)) {
+			fcs = crc16_reflect(0xa001, 0, send_buf->data, send_buf->len);
+			net_buf_add_le16(send_buf, fcs);
+		}
 
-	opt_mtu = (struct bt_l2cap_conf_opt_mtu *)buf->data;
+		br_chan->_pdu_remaining = send_buf->len;
+		br_chan->_pdu_buf = send_buf;
 
-	mtu = sys_le16_to_cpu(opt_mtu->mtu);
-	if (mtu < L2CAP_BR_MIN_MTU) {
-		result = BT_L2CAP_CONF_UNACCEPT;
-		BR_CHAN(chan)->tx.mtu = L2CAP_BR_MIN_MTU;
-		opt_mtu->mtu = sys_cpu_to_le16(L2CAP_BR_MIN_MTU);
-		LOG_DBG("tx MTU %u invalid", mtu);
-		goto done;
-	}
+		if (first) {
+			br_chan->next_tx_seq =
+				bt_l2cap_br_update_seq(br_chan, br_chan->next_tx_seq + 1);
 
-	BR_CHAN(chan)->tx.mtu = mtu;
-	LOG_DBG("tx MTU %u", mtu);
-done:
-	return result;
-}
+			net_buf_pull(pdu, pdu_len);
 
-static uint16_t l2cap_br_conf_opt_flush_timeout(struct bt_l2cap_chan *chan,
-						struct net_buf *buf, size_t len)
-{
-	uint16_t result = BT_L2CAP_CONF_SUCCESS;
-	struct bt_l2cap_conf_opt_flush_timeout *opt_to;
+			if (br_chan->rx.mode != BT_L2CAP_BR_LINK_MODE_STREAM) {
+				sys_slist_append(&br_chan->_pdu_outstanding, &tx_win->node);
+			} else {
+				l2cap_br_free_window(br_chan, tx_win);
 
-	if (len != sizeof(*opt_to)) {
-		LOG_ERR("qos frame length %zu invalid", len);
-		result = BT_L2CAP_CONF_REJECT;
-		goto done;
+				if (pdu->len == 0) {
+					l2cap_br_sdu_is_done(br_chan, pdu, 0);
+				}
+			}
+		}
 	}
 
-	opt_to = (struct bt_l2cap_conf_opt_flush_timeout *)buf->data;
-
-	LOG_DBG("Flush timeout %u", opt_to->timeout);
+	if (br_chan->_pdu_buf != NULL) {
+		if (bt_l2cap_br_get_outstanding_count(br_chan) == 1) {
+			/* It is the first one */
+			l2cap_br_start_timer(br_chan, BT_L2CAP_BR_TIMER_RET, true);
+		} else {
+			l2cap_br_start_timer(br_chan, BT_L2CAP_BR_TIMER_RET, false);
+		}
+	}
 
-	opt_to->timeout = sys_cpu_to_le16(0xFFFF);
-	result = BT_L2CAP_CONF_UNACCEPT;
 done:
-	return result;
-}
+	/* This is used by `conn.c` to figure out if the PDU is done sending. */
+	*length = br_chan->_pdu_remaining;
 
-static uint16_t l2cap_br_conf_opt_qos(struct bt_l2cap_chan *chan,
-				      struct net_buf *buf, size_t len)
-{
-	uint16_t result = BT_L2CAP_CONF_SUCCESS;
-	struct bt_l2cap_conf_opt_qos *opt_qos;
+	struct net_buf *buf;
 
-	if (len != sizeof(*opt_qos)) {
-		LOG_ERR("qos frame length %zu invalid", len);
-		result = BT_L2CAP_CONF_REJECT;
-		goto done;
-	}
+	buf = br_chan->_pdu_buf;
 
-	opt_qos = (struct bt_l2cap_conf_opt_qos *)buf->data;
+	if (br_chan->_pdu_remaining > amount) {
+		br_chan->_pdu_remaining -= amount;
+	} else {
+		br_chan->_pdu_buf = NULL;
+		br_chan->_pdu_remaining = 0;
+		if (pdu && !pdu->len) {
+			br_chan->_sdu_total_len = 0;
+		}
 
-	LOG_DBG("QOS Type %u", opt_qos->service_type);
+		LOG_DBG("done sending PDU");
 
-	if (opt_qos->service_type == BT_L2CAP_QOS_TYPE_GUARANTEED) {
-		/* Set to default value */
-		result = BT_L2CAP_CONF_UNACCEPT;
-		opt_qos->flags = 0x00;
-		/* do not care */
-		opt_qos->token_rate = sys_cpu_to_le32(0x00000000);
-		/* no token bucket is needed */
-		opt_qos->token_bucket_size = sys_cpu_to_le32(0x00000000);
-		/* do not care */
-		opt_qos->peak_bandwidth = sys_cpu_to_le32(0x00000000);
-		/* do not care */
-		opt_qos->latency = sys_cpu_to_le32(0xFFFFFFFF);
-		/* do not care */
-		opt_qos->delay_variation = sys_cpu_to_le32(0xFFFFFFFF);
+		/* Lowering the "request to send" and raising it again allows
+		 * fair scheduling of channels on an ACL link: the channel is
+		 * marked as "ready to send" by adding a reference to it on a
+		 * FIFO on `conn`. Adding it again will send it to the back of
+		 * the queue.
+		 *
+		 * TODO: add a user-controlled QoS function.
+		 */
+		LOG_DBG("chan %p done", br_chan);
+		lower_data_ready(br_chan);
+
+		/* Append channel to list if it still has data */
+		if (chan_has_data(br_chan)) {
+			LOG_DBG("chan %p ready", br_chan);
+			raise_data_ready(br_chan);
+		}
 	}
 
-done:
-	return result;
+	return buf;
 }
+#endif /* CONFIG_BT_L2CAP_RET_FC */
 
-static uint16_t l2cap_br_conf_opt_ret_fc(struct bt_l2cap_chan *chan,
-					 struct net_buf *buf, size_t len)
+struct net_buf *l2cap_br_data_pull(struct bt_conn *conn, size_t amount, size_t *length)
 {
-	uint16_t result = BT_L2CAP_CONF_SUCCESS;
-	struct bt_l2cap_conf_opt_ret_fc *opt_ret_fc;
+	const sys_snode_t *pdu_ready = sys_slist_peek_head(&conn->l2cap_data_ready);
 
-	if (len != sizeof(*opt_ret_fc)) {
-		LOG_ERR("ret_fc frame length %zu invalid", len);
-		result = BT_L2CAP_CONF_REJECT;
-		goto done;
+	if (!pdu_ready) {
+		LOG_DBG("nothing to send on this conn");
+		return NULL;
 	}
 
-	opt_ret_fc = (struct bt_l2cap_conf_opt_ret_fc *)buf->data;
+	struct bt_l2cap_br_chan *br_chan;
 
-	LOG_DBG("ret_fc mode %u", opt_ret_fc->mode);
+	br_chan = CONTAINER_OF(pdu_ready, struct bt_l2cap_br_chan, _pdu_ready);
 
-	if (opt_ret_fc->mode != BT_L2CAP_RET_FC_MODE_BASIC) {
-		/* Set to default value */
-		result = BT_L2CAP_CONF_UNACCEPT;
-		opt_ret_fc->mode = BT_L2CAP_RET_FC_MODE_BASIC;
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	if (br_chan->tx.mode != BT_L2CAP_BR_LINK_MODE_BASIC) {
+		return l2cap_br_ret_fc_data_pull(conn, amount, length);
 	}
+#endif /* CONFIG_BT_L2CAP_RET_FC */
 
-done:
-	return result;
-}
+	/* Leave the PDU buffer in the queue until we have sent all its
+	 * fragments.
+	 */
+	const sys_snode_t *tx_pdu = sys_slist_peek_head(&br_chan->_pdu_tx_queue);
 
-static uint16_t l2cap_br_conf_opt_fcs(struct bt_l2cap_chan *chan,
-				      struct net_buf *buf, size_t len)
-{
-	uint16_t result = BT_L2CAP_CONF_SUCCESS;
-	struct bt_l2cap_conf_opt_fcs *opt_fcs;
+	__ASSERT(tx_pdu, "signaled ready but no PDUs in the TX queue");
 
-	if (len != sizeof(*opt_fcs)) {
-		LOG_ERR("fcs frame length %zu invalid", len);
-		result = BT_L2CAP_CONF_REJECT;
-		goto done;
+	struct net_buf *pdu = CONTAINER_OF(tx_pdu, struct net_buf, node);
+
+	if (bt_buf_has_view(pdu)) {
+		LOG_ERR("already have view on %p", pdu);
+		return NULL;
 	}
 
-	opt_fcs = (struct bt_l2cap_conf_opt_fcs *)buf->data;
+	/* We can't interleave ACL fragments from different channels for the
+	 * same ACL conn -> we have to wait until a full L2 PDU is transferred
+	 * before switching channels.
+	 */
+	bool last_frag = amount >= pdu->len;
 
-	LOG_DBG("FCS type %u", opt_fcs->type);
+	if (last_frag) {
+		LOG_DBG("last frag, removing %p", pdu);
+		__maybe_unused bool found;
 
-	if (opt_fcs->type != BT_L2CAP_FCS_TYPE_NO) {
-		/* Set to default value */
-		result = BT_L2CAP_CONF_UNACCEPT;
-		opt_fcs->type = BT_L2CAP_FCS_TYPE_NO;
+		found = sys_slist_find_and_remove(&br_chan->_pdu_tx_queue, &pdu->node);
+
+		__ASSERT_NO_MSG(found);
+
+		LOG_DBG("chan %p done", br_chan);
+		lower_data_ready(br_chan);
+
+		/* Append channel to list if it still has data */
+		if (chan_has_data(br_chan)) {
+			LOG_DBG("chan %p ready", br_chan);
+			raise_data_ready(br_chan);
+		}
 	}
 
-done:
-	return result;
+	*length = pdu->len;
+
+	return pdu;
 }
 
-static void l2cap_br_conf_req(struct bt_l2cap_br *l2cap, uint8_t ident,
-			      uint16_t len, struct net_buf *buf)
+static void l2cap_br_get_info(struct bt_l2cap_br *l2cap, uint16_t info_type)
 {
-	struct bt_conn *conn = l2cap->chan.chan.conn;
-	struct bt_l2cap_chan *chan;
-	struct bt_l2cap_conf_req *req;
+	struct bt_l2cap_info_req *info;
+	struct net_buf *buf;
 	struct bt_l2cap_sig_hdr *hdr;
-	struct bt_l2cap_conf_rsp *rsp;
-	struct bt_l2cap_conf_opt *opt = NULL;
-	uint16_t flags, dcid, opt_len, hint, result = BT_L2CAP_CONF_SUCCESS;
 
-	if (buf->len < sizeof(*req)) {
-		LOG_ERR("Too small L2CAP conf req packet size");
+	LOG_DBG("info type %u", info_type);
+
+	if (atomic_test_bit(l2cap->chan.flags, L2CAP_FLAG_SIG_INFO_PENDING)) {
 		return;
 	}
 
-	req = net_buf_pull_mem(buf, sizeof(*req));
-	flags = sys_le16_to_cpu(req->flags);
-	dcid = sys_le16_to_cpu(req->dcid);
-	opt_len = len - sizeof(*req);
+	switch (info_type) {
+	case BT_L2CAP_INFO_FEAT_MASK:
+	case BT_L2CAP_INFO_FIXED_CHAN:
+		break;
+	default:
+		LOG_WRN("Unsupported info type %u", info_type);
+		return;
+	}
 
-	LOG_DBG("dcid 0x%04x flags 0x%02x len %u", dcid, flags, opt_len);
+	buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
 
-	chan = bt_l2cap_br_lookup_rx_cid(conn, dcid);
-	if (!chan) {
-		LOG_ERR("rx channel mismatch!");
-		struct bt_l2cap_cmd_reject_cid_data data = {
-			.scid = req->dcid,
-			.dcid = 0,
-		};
+	atomic_set_bit(l2cap->chan.flags, L2CAP_FLAG_SIG_INFO_PENDING);
+	l2cap->chan.ident = l2cap_br_get_ident();
+
+	hdr = net_buf_add(buf, sizeof(*hdr));
+	hdr->code = BT_L2CAP_INFO_REQ;
+	hdr->ident = l2cap->chan.ident;
+	hdr->len = sys_cpu_to_le16(sizeof(*info));
+
+	info = net_buf_add(buf, sizeof(*info));
+	info->type = sys_cpu_to_le16(info_type);
+
+	l2cap_br_chan_send_req(&l2cap->chan, buf, L2CAP_BR_INFO_TIMEOUT);
+}
 
-		l2cap_br_send_reject(conn, ident, BT_L2CAP_REJ_INVALID_CID,
-				     &data, sizeof(data));
+static void connect_fixed_channel(struct bt_l2cap_br_chan *chan)
+{
+	if (atomic_test_and_set_bit(chan->flags, L2CAP_FLAG_FIXED_CONNECTED)) {
 		return;
 	}
 
-	if (!opt_len) {
-		LOG_DBG("tx default MTU %u", L2CAP_BR_DEFAULT_MTU);
-		BR_CHAN(chan)->tx.mtu = L2CAP_BR_DEFAULT_MTU;
-		goto send_rsp;
+	if (chan->chan.ops && chan->chan.ops->connected) {
+		chan->chan.ops->connected(&chan->chan);
 	}
+}
 
-	while (buf->len >= sizeof(*opt)) {
-		opt = net_buf_pull_mem(buf, sizeof(*opt));
+static void connect_optional_fixed_channels(struct bt_l2cap_br *l2cap)
+{
+	/* can be change to loop if more BR/EDR fixed channels are added */
+	if (l2cap->info_fixed_chan & BIT(BT_L2CAP_CID_BR_SMP)) {
+		struct bt_l2cap_chan *chan;
 
-		/* make sure opt object can get safe dereference in iteration */
-		if (buf->len < opt->len) {
-			LOG_ERR("Received too short option data");
-			result = BT_L2CAP_CONF_REJECT;
-			break;
+		chan = bt_l2cap_br_lookup_rx_cid(l2cap->chan.chan.conn,
+						 BT_L2CAP_CID_BR_SMP);
+		if (chan) {
+			connect_fixed_channel(BR_CHAN(chan));
 		}
+	}
+}
 
-		hint = opt->type & BT_L2CAP_CONF_HINT;
+static int l2cap_br_info_rsp(struct bt_l2cap_br *l2cap, uint8_t ident,
+			     struct net_buf *buf)
+{
+	struct bt_l2cap_info_rsp *rsp;
+	uint16_t type, result;
+	int err = 0;
 
-		switch (opt->type & BT_L2CAP_CONF_MASK) {
-		case BT_L2CAP_CONF_OPT_MTU:
-			/* getting MTU modifies buf internals */
-			result = l2cap_br_conf_opt_mtu(chan, buf, opt->len);
-			/*
-			 * MTU is done. For now bailout the loop but later on
-			 * there can be a need to continue checking next options
-			 * that are after MTU value and then goto is not proper
-			 * way out here.
-			 */
-			goto send_rsp;
-		case BT_L2CAP_CONF_OPT_FLUSH_TIMEOUT:
-			result = l2cap_br_conf_opt_flush_timeout(chan, buf, opt->len);
-			if (result != BT_L2CAP_CONF_SUCCESS) {
-				goto send_rsp;
-			}
-			break;
-		case BT_L2CAP_CONF_OPT_QOS:
-			result = l2cap_br_conf_opt_qos(chan, buf, opt->len);
-			if (result != BT_L2CAP_CONF_SUCCESS) {
-				goto send_rsp;
-			}
-			break;
-		case BT_L2CAP_CONF_OPT_RET_FC:
-			result = l2cap_br_conf_opt_ret_fc(chan, buf, opt->len);
-			if (result != BT_L2CAP_CONF_SUCCESS) {
-				goto send_rsp;
-			}
+	if (atomic_test_bit(l2cap->chan.flags, L2CAP_FLAG_SIG_INFO_DONE)) {
+		return 0;
+	}
+
+	if (atomic_test_and_clear_bit(l2cap->chan.flags,
+				      L2CAP_FLAG_SIG_INFO_PENDING)) {
+		/*
+		 * Release RTX timer since got the response & there's pending
+		 * command request.
+		 */
+		k_work_cancel_delayable(&l2cap->chan.rtx_work);
+	}
+
+	if (buf->len < sizeof(*rsp)) {
+		LOG_ERR("Too small info rsp packet size");
+		err = -EINVAL;
+		goto done;
+	}
+
+	if (ident != l2cap->chan.ident) {
+		LOG_WRN("Idents mismatch");
+		err = -EINVAL;
+		goto done;
+	}
+
+	rsp = net_buf_pull_mem(buf, sizeof(*rsp));
+	result = sys_le16_to_cpu(rsp->result);
+	if (result != BT_L2CAP_INFO_SUCCESS) {
+		LOG_WRN("Result unsuccessful");
+		err = -EINVAL;
+		goto done;
+	}
+
+	type = sys_le16_to_cpu(rsp->type);
+
+	switch (type) {
+	case BT_L2CAP_INFO_FEAT_MASK:
+		if (buf->len < sizeof(uint32_t)) {
+			LOG_ERR("Invalid remote info feat mask");
+			err = -EINVAL;
 			break;
-		case BT_L2CAP_CONF_OPT_FCS:
-			result = l2cap_br_conf_opt_fcs(chan, buf, opt->len);
-			if (result != BT_L2CAP_CONF_SUCCESS) {
-				goto send_rsp;
-			}
+		}
+		l2cap->info_feat_mask = net_buf_pull_le32(buf);
+		LOG_DBG("remote info mask 0x%08x", l2cap->info_feat_mask);
+
+		if (!(l2cap->info_feat_mask & L2CAP_FEAT_FIXED_CHAN_MASK)) {
 			break;
-		case BT_L2CAP_CONF_OPT_EXT_FLOW_SPEC:
-			__fallthrough;
-		case BT_L2CAP_CONF_OPT_EXT_WIN_SIZE:
-			result = BT_L2CAP_CONF_REJECT;
-			goto send_rsp;
-		default:
-			if (!hint) {
-				LOG_DBG("option %u not handled", opt->type);
-				result = BT_L2CAP_CONF_UNKNOWN_OPT;
-				goto send_rsp;
-			}
+		}
+
+		l2cap_br_get_info(l2cap, BT_L2CAP_INFO_FIXED_CHAN);
+		return 0;
+	case BT_L2CAP_INFO_FIXED_CHAN:
+		if (buf->len < sizeof(uint8_t)) {
+			LOG_ERR("Invalid remote info fixed chan");
+			err = -EINVAL;
 			break;
 		}
+		/*
+		 * 2.1 CHANNEL IDENTIFIERS in
+		 * BLUETOOTH CORE SPECIFICATION Version 5.4 | Vol 3, Part A.
+		 * The info length of `Fixed channels supported` is 8 octets.
+		 * Then the range of fixed L2CAP CID is 0x0001 ~ 0x0007 both for LE and BR.
+		 * So use one octet buffer to keep the `Fixed channels supported`
+		 * of peer device.
+		 */
+		l2cap->info_fixed_chan = net_buf_pull_u8(buf);
+		LOG_DBG("remote fixed channel mask 0x%02x", l2cap->info_fixed_chan);
 
-		/* Update buffer to point at next option */
-		net_buf_pull(buf, opt->len);
+		connect_optional_fixed_channels(l2cap);
+
+		break;
+	default:
+		LOG_WRN("type 0x%04x unsupported", type);
+		err = -EINVAL;
+		break;
 	}
+done:
+	atomic_set_bit(l2cap->chan.flags, L2CAP_FLAG_SIG_INFO_DONE);
+	l2cap->chan.ident = 0U;
+	return err;
+}
 
-send_rsp:
-	buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
+static uint8_t get_fixed_channels_mask(void)
+{
+	uint8_t mask = 0U;
 
-	hdr = net_buf_add(buf, sizeof(*hdr));
-	hdr->code = BT_L2CAP_CONF_RSP;
-	hdr->ident = ident;
-	rsp = net_buf_add(buf, sizeof(*rsp));
-	(void)memset(rsp, 0, sizeof(*rsp));
+	/* this needs to be enhanced if AMP Test Manager support is added */
+	STRUCT_SECTION_FOREACH(bt_l2cap_br_fixed_chan, fchan) {
+		mask |= BIT(fchan->cid);
+	}
 
-	rsp->result = sys_cpu_to_le16(result);
-	rsp->scid = sys_cpu_to_le16(BR_CHAN(chan)->tx.cid);
+	return mask;
+}
 
-	/*
-	 * Core 5.4, Vol 3, Part A, section 4.5.
-	 * When used in the L2CAP_CONFIGURATION_RSP packet,
-	 * the continuation flag shall be set to one if the
-	 * flag is set to one in the Request, except for
-	 * those error conditions more appropriate for an
-	 * L2CAP_COMMAND_REJECT_RSP packet.
-	 */
-	rsp->flags = sys_cpu_to_le16(flags & BT_L2CAP_CONF_FLAGS_MASK);
+static int l2cap_br_info_req(struct bt_l2cap_br *l2cap, uint8_t ident,
+			     struct net_buf *buf)
+{
+	struct bt_conn *conn = l2cap->chan.chan.conn;
+	struct bt_l2cap_info_req *req = (void *)buf->data;
+	struct bt_l2cap_info_rsp *rsp;
+	struct net_buf *rsp_buf;
+	struct bt_l2cap_sig_hdr *hdr_info;
+	uint16_t type;
 
-	/*
-	 * TODO: If options other than MTU became meaningful then processing
+	if (buf->len < sizeof(*req)) {
+		LOG_ERR("Too small info req packet size");
+		return -EINVAL;
+	}
+
+	rsp_buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
+
+	type = sys_le16_to_cpu(req->type);
+	LOG_DBG("type 0x%04x", type);
+
+	hdr_info = net_buf_add(rsp_buf, sizeof(*hdr_info));
+	hdr_info->code = BT_L2CAP_INFO_RSP;
+	hdr_info->ident = ident;
+
+	rsp = net_buf_add(rsp_buf, sizeof(*rsp));
+
+	switch (type) {
+	case BT_L2CAP_INFO_FEAT_MASK:
+		rsp->type = sys_cpu_to_le16(BT_L2CAP_INFO_FEAT_MASK);
+		rsp->result = sys_cpu_to_le16(BT_L2CAP_INFO_SUCCESS);
+		net_buf_add_le32(rsp_buf, L2CAP_EXTENDED_FEAT_MASK);
+		hdr_info->len = sys_cpu_to_le16(sizeof(*rsp) + sizeof(uint32_t));
+		break;
+	case BT_L2CAP_INFO_FIXED_CHAN:
+		rsp->type = sys_cpu_to_le16(BT_L2CAP_INFO_FIXED_CHAN);
+		rsp->result = sys_cpu_to_le16(BT_L2CAP_INFO_SUCCESS);
+		/* fixed channel mask protocol data is 8 octets wide */
+		(void)memset(net_buf_add(rsp_buf, 8), 0, 8);
+		rsp->data[0] = get_fixed_channels_mask();
+
+		hdr_info->len = sys_cpu_to_le16(sizeof(*rsp) + 8);
+		break;
+	default:
+		rsp->type = req->type;
+		rsp->result = sys_cpu_to_le16(BT_L2CAP_INFO_NOTSUPP);
+		hdr_info->len = sys_cpu_to_le16(sizeof(*rsp));
+		break;
+	}
+
+	l2cap_send(conn, BT_L2CAP_CID_BR_SIG, rsp_buf);
+
+	return 0;
+}
+
+void bt_l2cap_br_connected(struct bt_conn *conn)
+{
+	struct bt_l2cap_chan *chan;
+
+	STRUCT_SECTION_FOREACH(bt_l2cap_br_fixed_chan, fchan) {
+		struct bt_l2cap_br_chan *br_chan;
+
+		if (!fchan->accept) {
+			continue;
+		}
+
+		if (fchan->accept(conn, &chan) < 0) {
+			continue;
+		}
+
+		br_chan = BR_CHAN(chan);
+
+		br_chan->rx.cid = fchan->cid;
+		br_chan->tx.cid = fchan->cid;
+
+		if (!l2cap_br_chan_add(conn, chan, NULL)) {
+			return;
+		}
+
+		/*
+		 * other fixed channels will be connected after Information
+		 * Response is received
+		 */
+		if (fchan->cid == BT_L2CAP_CID_BR_SIG) {
+			struct bt_l2cap_br *sig_ch;
+
+			connect_fixed_channel(br_chan);
+
+			sig_ch = CONTAINER_OF(br_chan, struct bt_l2cap_br, chan);
+			l2cap_br_get_info(sig_ch, BT_L2CAP_INFO_FEAT_MASK);
+		}
+	}
+}
+
+void bt_l2cap_br_disconnected(struct bt_conn *conn)
+{
+	struct bt_l2cap_chan *chan, *next;
+
+	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&conn->channels, chan, next, node) {
+		bt_l2cap_br_chan_del(chan);
+	}
+}
+
+static struct bt_l2cap_server *l2cap_br_server_lookup_psm(uint16_t psm)
+{
+	struct bt_l2cap_server *server;
+
+	SYS_SLIST_FOR_EACH_CONTAINER(&br_servers, server, node) {
+		if (server->psm == psm) {
+			return server;
+		}
+	}
+
+	return NULL;
+}
+
+static void l2cap_br_conf_add_mtu(struct net_buf *buf, const uint16_t mtu)
+{
+	if (net_buf_tailroom(buf) < (sizeof(struct bt_l2cap_conf_opt) + sizeof(mtu))) {
+		LOG_WRN("No tail room for opt mtu");
+		return;
+	}
+	net_buf_add_u8(buf, BT_L2CAP_CONF_OPT_MTU);
+	net_buf_add_u8(buf, sizeof(mtu));
+	net_buf_add_le16(buf, mtu);
+}
+
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+static void l2cap_br_conf_add_ret_fc(struct net_buf *buf,
+				     const struct bt_l2cap_conf_opt_ret_fc *ret_fc)
+{
+	if (net_buf_tailroom(buf) < (sizeof(struct bt_l2cap_conf_opt) + sizeof(*ret_fc))) {
+		LOG_WRN("No tail room for opt flash_timeout");
+		return;
+	}
+	net_buf_add_u8(buf, BT_L2CAP_CONF_OPT_RET_FC);
+	net_buf_add_u8(buf, sizeof(*ret_fc));
+	net_buf_add_mem(buf, ret_fc, sizeof(*ret_fc));
+}
+
+static void l2cap_br_conf_add_fcs(struct net_buf *buf, const struct bt_l2cap_conf_opt_fcs *fcs)
+{
+	if (net_buf_tailroom(buf) < (sizeof(struct bt_l2cap_conf_opt) + sizeof(*fcs))) {
+		LOG_WRN("No tail room for opt flash_timeout");
+		return;
+	}
+	net_buf_add_u8(buf, BT_L2CAP_CONF_OPT_FCS);
+	net_buf_add_u8(buf, sizeof(*fcs));
+	net_buf_add_mem(buf, fcs, sizeof(*fcs));
+}
+
+static void
+l2cap_br_conf_add_ext_win_size(struct net_buf *buf,
+			       const struct bt_l2cap_conf_opt_ext_win_size *ext_win_size)
+{
+	if (net_buf_tailroom(buf) < (sizeof(struct bt_l2cap_conf_opt) + sizeof(*ext_win_size))) {
+		LOG_WRN("No tail room for opt flash_timeout");
+		return;
+	}
+	net_buf_add_u8(buf, BT_L2CAP_CONF_OPT_EXT_WIN_SIZE);
+	net_buf_add_u8(buf, sizeof(*ext_win_size));
+	net_buf_add_mem(buf, ext_win_size, sizeof(*ext_win_size));
+}
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+
+static void l2cap_br_conf_add_opt(struct net_buf *buf, const struct bt_l2cap_conf_opt *opt)
+{
+	if (net_buf_tailroom(buf) < (sizeof(*opt) + opt->len)) {
+		LOG_WRN("No tail room for opt flash_timeout");
+		return;
+	}
+
+	net_buf_add_u8(buf, opt->type & BT_L2CAP_CONF_MASK);
+	net_buf_add_u8(buf, opt->len);
+	net_buf_add_mem(buf, opt->data, opt->len);
+}
+
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+static int l2cap_br_check_chan_config(struct bt_conn *conn, struct bt_l2cap_br_chan *br_chan)
+{
+	struct bt_l2cap_chan *chan_sig;
+	struct bt_l2cap_br *br_chan_sig;
+
+	if (!conn) {
+		return -ENOTCONN;
+	}
+
+	chan_sig = bt_l2cap_br_lookup_rx_cid(conn, BT_L2CAP_CID_BR_SIG);
+	if (!chan_sig) {
+		LOG_WRN("Ignoring data for unknown channel ID 0x%04x", BT_L2CAP_CID_BR_SIG);
+		return -EINVAL;
+	}
+
+	br_chan_sig = CONTAINER_OF(chan_sig, struct bt_l2cap_br, chan.chan);
+
+	/* Disable segment/reassemble of l2cap rx pdu */
+	br_chan->rx.mtu = MIN(br_chan->rx.mtu, BT_L2CAP_RX_MTU);
+	br_chan->rx.mps = br_chan->rx.mtu;
+
+	br_chan->tx.mps = CONFIG_BT_L2CAP_MPS;
+	br_chan->tx.mtu = L2CAP_BR_DEFAULT_MTU;
+	/* Set FCS to default value */
+	br_chan->tx.fcs = BT_L2CAP_BR_FCS_16BIT;
+
+	/* Set default value */
+	br_chan->rx.max_window = CONFIG_BT_L2CAP_MAX_WINDOW_SIZE;
+	br_chan->rx.ret_timeout = CONFIG_BT_L2CAP_BR_RET_TIMEOUT;
+	br_chan->rx.monitor_timeout = CONFIG_BT_L2CAP_BR_MONITOR_TIMEOUT;
+
+	br_chan->tx.extended_control = false;
+	br_chan->tx.optional = false;
+	br_chan->tx.max_transmit = 1;
+	br_chan->tx.max_window = CONFIG_BT_L2CAP_MAX_WINDOW_SIZE;
+	br_chan->tx.ret_timeout = CONFIG_BT_L2CAP_BR_RET_TIMEOUT;
+	br_chan->tx.monitor_timeout = CONFIG_BT_L2CAP_BR_MONITOR_TIMEOUT;
+
+	/* Set all variables and sequence numbers to zero */
+	br_chan->tx_seq = 0;
+	br_chan->next_tx_seq = 0;
+	br_chan->expected_ack_seq = 0;
+	br_chan->req_seq = 0;
+	br_chan->expected_tx_seq = 0;
+	br_chan->buffer_seq = 0;
+
+	memset(&br_chan->tx_win[0], 0, sizeof(br_chan->tx_win));
+
+	sys_slist_init(&br_chan->_pdu_outstanding);
+	k_fifo_init(&br_chan->_free_tx_win);
+
+	for (int i = 0; i < ARRAY_SIZE(br_chan->tx_win); i++) {
+		k_fifo_put(&br_chan->_free_tx_win, &br_chan->tx_win[i]);
+	}
+
+	switch (br_chan->rx.mode) {
+	case BT_L2CAP_BR_LINK_MODE_BASIC:
+		break;
+	case BT_L2CAP_BR_LINK_MODE_RET:
+		__fallthrough;
+	case BT_L2CAP_BR_LINK_MODE_FC:
+		if ((br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_FC) &&
+		    (((br_chan_sig->info_feat_mask & L2CAP_FEAT_FC_MASK) == 0) ||
+		     ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_FC_MASK) == 0))) {
+			if (!br_chan->rx.optional) {
+				LOG_ERR("Invalid mode %u", br_chan->rx.mode);
+				return -ENOTSUP;
+			}
+
+			LOG_WRN("Unsupp mode %u, set basic mode", br_chan->rx.mode);
+			br_chan->rx.mode = BT_L2CAP_BR_LINK_MODE_BASIC;
+			break;
+		}
+
+		if ((br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_RET) &&
+		    (((br_chan_sig->info_feat_mask & L2CAP_FEAT_RET_MASK) == 0) ||
+		     ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_RET_MASK) == 0))) {
+			if (!br_chan->rx.optional) {
+				LOG_ERR("Invalid mode %u", br_chan->rx.mode);
+				return -ENOTSUP;
+			}
+
+			LOG_WRN("Unsupp mode %u, set basic mode", br_chan->rx.mode);
+			br_chan->rx.mode = BT_L2CAP_BR_LINK_MODE_BASIC;
+			break;
+		}
+
+		if (((br_chan_sig->info_feat_mask & L2CAP_FEAT_ENH_RET_MASK) != 0) &&
+		    ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_ENH_RET_MASK) != 0)) {
+			/* If enhance transmission mode is supported by both side,
+			 * the enhance transmission mode should be used instead of
+			 * transmission or flow control mode.
+			 */
+			br_chan->rx.mode = BT_L2CAP_BR_LINK_MODE_ERET;
+			br_chan->tx.mode = BT_L2CAP_BR_LINK_MODE_ERET;
+		}
+		break;
+	case BT_L2CAP_BR_LINK_MODE_ERET:
+		if (((br_chan_sig->info_feat_mask & L2CAP_FEAT_ENH_RET_MASK) == 0) ||
+		    ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_ENH_RET_MASK) == 0)) {
+			if (!br_chan->rx.optional) {
+				LOG_ERR("Invalid mode %u", br_chan->rx.mode);
+				return -ENOTSUP;
+			}
+
+			LOG_WRN("Unsupp mode %u, set basic mode", br_chan->rx.mode);
+			br_chan->rx.mode = BT_L2CAP_BR_LINK_MODE_BASIC;
+			break;
+		}
+		break;
+	case BT_L2CAP_BR_LINK_MODE_STREAM:
+		if (((br_chan_sig->info_feat_mask & L2CAP_FEAT_STREAM_MASK) == 0) ||
+		    ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_STREAM_MASK) == 0)) {
+			if (!br_chan->rx.optional) {
+				LOG_ERR("Invalid mode %u", br_chan->rx.mode);
+				return -ENOTSUP;
+			}
+
+			LOG_WRN("Unsupp mode %u, set basic mode", br_chan->rx.mode);
+			br_chan->rx.mode = BT_L2CAP_BR_LINK_MODE_BASIC;
+			break;
+		}
+		break;
+	default:
+		br_chan->rx.mode = BT_L2CAP_BR_LINK_MODE_BASIC;
+		br_chan->tx.mode = BT_L2CAP_BR_LINK_MODE_BASIC;
+		break;
+	}
+
+	atomic_set_bit(br_chan->flags, L2CAP_FLAG_NEW_I_FRAME);
+	atomic_set_bit(br_chan->flags, L2CAP_FLAG_RET_I_FRAME);
+
+	switch (br_chan->rx.mode) {
+	case BT_L2CAP_BR_LINK_MODE_BASIC:
+		br_chan->tx.fcs = 0;
+		br_chan->rx.fcs = 0;
+		break;
+	case BT_L2CAP_BR_LINK_MODE_RET:
+		__fallthrough;
+	case BT_L2CAP_BR_LINK_MODE_FC:
+		if (br_chan->rx.max_window < 1) {
+			br_chan->rx.max_window = 1;
+		} else if (br_chan->rx.max_window > 32) {
+			br_chan->rx.max_window = 32;
+		}
+
+		if (br_chan->rx.max_transmit < 1) {
+			br_chan->rx.max_transmit = 1;
+		}
+
+		br_chan->tx.fcs = BT_L2CAP_BR_FCS_16BIT;
+		br_chan->rx.fcs = BT_L2CAP_BR_FCS_16BIT;
+		break;
+	case BT_L2CAP_BR_LINK_MODE_ERET:
+		if (((br_chan_sig->info_feat_mask & L2CAP_FEAT_EXT_WIN_SIZE_MASK) == 0) ||
+		    ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_EXT_WIN_SIZE_MASK) == 0)) {
+			LOG_WRN("Unsupported extended window size");
+			br_chan->rx.extended_control = false;
+			br_chan->tx.extended_control = false;
+		}
+
+		if (br_chan->rx.max_window < 1) {
+			br_chan->rx.max_window = 1;
+		} else if (br_chan->rx.max_window > 63) {
+			if (br_chan->rx.extended_control) {
+				br_chan->rx.max_window = MIN(br_chan->rx.max_window, 0x3fff);
+			} else {
+				br_chan->rx.max_window = 63;
+			}
+		}
+
+		if (br_chan->rx.max_transmit < 1) {
+			br_chan->rx.max_transmit = 1;
+		}
+
+		if (((br_chan_sig->info_feat_mask & L2CAP_FEAT_FCS_MASK) == 0) ||
+		    ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_FCS_MASK) == 0)) {
+			LOG_WRN("Unsupported FCS option, force to enable FCS");
+			br_chan->tx.fcs = BT_L2CAP_BR_FCS_16BIT;
+			br_chan->rx.fcs = BT_L2CAP_BR_FCS_16BIT;
+		}
+		break;
+	case BT_L2CAP_BR_LINK_MODE_STREAM:
+		if (((br_chan_sig->info_feat_mask & L2CAP_FEAT_EXT_WIN_SIZE_MASK) == 0) ||
+		    ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_EXT_WIN_SIZE_MASK) == 0)) {
+			LOG_WRN("Unsupported extended window size");
+			br_chan->rx.extended_control = false;
+			br_chan->tx.extended_control = false;
+		}
+
+		br_chan->rx.max_transmit = 1;
+		if (((br_chan_sig->info_feat_mask & L2CAP_FEAT_FCS_MASK) == 0) ||
+		    ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_FCS_MASK) == 0)) {
+			LOG_WRN("Unsupported FCS option, force to enable FCS");
+			br_chan->tx.fcs = BT_L2CAP_BR_FCS_16BIT;
+			br_chan->rx.fcs = BT_L2CAP_BR_FCS_16BIT;
+		}
+		break;
+	default:
+		/* Should not have gotten here */
+		break;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+
+static void l2cap_br_conf(struct bt_l2cap_chan *chan, bool init)
+{
+	struct bt_l2cap_sig_hdr *hdr;
+	struct bt_l2cap_conf_req *conf;
+	struct net_buf *buf;
+
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	if (init) {
+		int err;
+
+		err = l2cap_br_check_chan_config(chan->conn, BR_CHAN(chan));
+		if (err) {
+			bt_l2cap_chan_disconnect(chan);
+			return;
+		}
+	}
+#else
+	(void)init;
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+
+	buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
+
+	hdr = net_buf_add(buf, sizeof(*hdr));
+	hdr->code = BT_L2CAP_CONF_REQ;
+	hdr->ident = l2cap_br_get_ident();
+	conf = net_buf_add(buf, sizeof(*conf));
+	(void)memset(conf, 0, sizeof(*conf));
+
+	conf->dcid = sys_cpu_to_le16(BR_CHAN(chan)->tx.cid);
+	/* Set the ident for the signaling request */
+	BR_CHAN(chan)->ident = hdr->ident;
+	/*
+	 * Add MTU option if app set non default BR/EDR L2CAP MTU,
+	 * otherwise sent empty configuration data meaning default MTU
+	 * to be used.
+	 */
+	if (BR_CHAN(chan)->rx.mtu != L2CAP_BR_DEFAULT_MTU) {
+		l2cap_br_conf_add_mtu(buf, BR_CHAN(chan)->rx.mtu);
+	}
+
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	if (BR_CHAN(chan)->rx.mode != BT_L2CAP_BR_LINK_MODE_BASIC) {
+		struct bt_l2cap_conf_opt_ret_fc ret_fc;
+		struct bt_l2cap_conf_opt_fcs fcs;
+
+		ret_fc.mode = BR_CHAN(chan)->rx.mode;
+		ret_fc.tx_windows_size = BR_CHAN(chan)->rx.max_window;
+		ret_fc.max_transmit = BR_CHAN(chan)->rx.max_transmit;
+		ret_fc.retransmission_timeout = sys_cpu_to_le16(BR_CHAN(chan)->rx.ret_timeout);
+		ret_fc.monitor_timeout = sys_cpu_to_le16(BR_CHAN(chan)->rx.monitor_timeout);
+		ret_fc.mps = sys_cpu_to_le16(BR_CHAN(chan)->rx.mps);
+		l2cap_br_conf_add_ret_fc(buf, &ret_fc);
+
+		fcs.type = BR_CHAN(chan)->rx.fcs;
+		if (fcs.type == BT_L2CAP_FCS_TYPE_NO) {
+			l2cap_br_conf_add_fcs(buf, &fcs);
+		}
+
+		if (BR_CHAN(chan)->rx.extended_control &&
+		    ((BR_CHAN(chan)->rx.mode == BT_L2CAP_BR_LINK_MODE_ERET) ||
+		     (BR_CHAN(chan)->rx.mode == BT_L2CAP_BR_LINK_MODE_STREAM))) {
+			struct bt_l2cap_conf_opt_ext_win_size ext_win_size;
+
+			if (BR_CHAN(chan)->rx.mode == BT_L2CAP_BR_LINK_MODE_STREAM) {
+				ext_win_size.max_windows_size = 0;
+			} else {
+				ext_win_size.max_windows_size =
+					sys_cpu_to_le16(BR_CHAN(chan)->rx.max_window);
+			}
+			l2cap_br_conf_add_ext_win_size(buf, &ext_win_size);
+		}
+	}
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+
+	hdr->len = sys_cpu_to_le16(buf->len - sizeof(*hdr));
+
+	/*
+	 * TODO:
+	 * might be needed to start tracking number of configuration iterations
+	 * on both directions
+	 */
+	l2cap_br_chan_send_req(BR_CHAN(chan), buf, L2CAP_BR_CFG_TIMEOUT);
+}
+
+enum l2cap_br_conn_security_result {
+	L2CAP_CONN_SECURITY_PASSED,
+	L2CAP_CONN_SECURITY_REJECT,
+	L2CAP_CONN_SECURITY_PENDING
+};
+
+/*
+ * Security helper against channel connection.
+ * Returns L2CAP_CONN_SECURITY_PASSED if:
+ * - existing security on link is applicable for requested PSM in connection,
+ * - legacy (non SSP) devices connecting with low security requirements,
+ * Returns L2CAP_CONN_SECURITY_PENDING if:
+ * - channel connection process is on hold since there were valid security
+ *   conditions triggering authentication indirectly in subcall.
+ * Returns L2CAP_CONN_SECURITY_REJECT if:
+ * - bt_conn_set_security API returns < 0,
+ * - Or, the ACL connection has been encrypted, the security level of link key cannot be upgraded,
+ *   and the security level is less than the required security level.
+ */
+
+static enum l2cap_br_conn_security_result
+l2cap_br_conn_security(struct bt_l2cap_chan *chan, const uint16_t psm)
+{
+	int check;
+	struct bt_l2cap_br_chan *br_chan = BR_CHAN(chan);
+
+	/* For SDP PSM there's no need to change existing security on link */
+	if (br_chan->required_sec_level == BT_SECURITY_L0) {
+		return L2CAP_CONN_SECURITY_PASSED;
+	}
+
+	/*
+	 * No link key needed for legacy devices (pre 2.1) and when low security
+	 * level is required.
+	 */
+	if (br_chan->required_sec_level == BT_SECURITY_L1 &&
+	    !BT_FEAT_HOST_SSP(chan->conn->br.features)) {
+		return L2CAP_CONN_SECURITY_PASSED;
+	}
+
+	switch (br_chan->required_sec_level) {
+	case BT_SECURITY_L4:
+	case BT_SECURITY_L3:
+	case BT_SECURITY_L2:
+		break;
+	default:
+		/*
+		 * For non SDP PSM connections GAP's Security Mode 4 requires at
+		 * least unauthenticated link key and enabled encryption if
+		 * remote supports SSP before any L2CAP CoC traffic. So preset
+		 * local to MEDIUM security to trigger it if needed.
+		 */
+		if (BT_FEAT_HOST_SSP(chan->conn->br.features)) {
+			br_chan->required_sec_level = BT_SECURITY_L2;
+		}
+		break;
+	}
+
+	if (chan->conn->sec_level < br_chan->required_sec_level &&
+	    chan->conn->encrypt && chan->conn->br.link_key &&
+	    (chan->conn->br.link_key->flags & BT_LINK_KEY_AUTHENTICATED)) {
+		/*
+		 * If the ACL link has been encrypted and it has a authenticated link key, it means
+		 * the pairing procedure has been done. And the security level of the link key can
+		 * not be upgraded. In this case, if `conn->sec_level` is less than the required
+		 * security level of the L2CAP channel, reject the L2CAP conn request.
+		 */
+		return L2CAP_CONN_SECURITY_REJECT;
+	}
+
+	check = bt_conn_set_security(chan->conn, br_chan->required_sec_level);
+
+	/*
+	 * Check case when on existing connection security level already covers
+	 * channel (service) security requirements against link security and
+	 * bt_conn_set_security API returns 0 what implies also there was no
+	 * need to trigger authentication.
+	 */
+	if (check == 0 &&
+	    chan->conn->sec_level >= br_chan->required_sec_level) {
+		return L2CAP_CONN_SECURITY_PASSED;
+	}
+
+	/*
+	 * If 'check' still holds 0, it means local host just sent HCI
+	 * authentication command to start procedure to increase link security
+	 * since service/profile requires that.
+	 */
+	if (check == 0) {
+		/*
+		 * General Bonding refers to the process of performing bonding
+		 * during connection setup or channel establishment procedures
+		 * as a precursor to accessing a service.
+		 * For current case, it is dedicated bonding.
+		 */
+		atomic_set_bit(chan->conn->flags, BT_CONN_BR_GENERAL_BONDING);
+		return L2CAP_CONN_SECURITY_PENDING;
+	}
+
+	/*
+	 * For any other values in 'check' it means there was internal
+	 * validation condition forbidding to start authentication at this
+	 * moment.
+	 */
+	return L2CAP_CONN_SECURITY_REJECT;
+}
+
+static void l2cap_br_conn_rsp_sent_cb(struct bt_conn *conn, void *user_data, int err)
+{
+	uint16_t scid = POINTER_TO_UINT(user_data);
+	struct bt_l2cap_chan *chan;
+
+	chan = bt_l2cap_br_lookup_tx_cid(conn, scid);
+	if (!chan) {
+		return;
+	}
+
+	/* Check whether the ACL connection needs to be disconnected. */
+	if (atomic_test_and_clear_bit(BR_CHAN(chan)->flags, L2CAP_FLAG_DISCONNECT_ACL)) {
+		bt_conn_disconnect(conn, BT_HCI_ERR_AUTH_FAIL);
+	}
+}
+
+static void l2cap_br_send_conn_rsp(struct bt_conn *conn, uint16_t scid,
+				  uint16_t dcid, uint8_t ident, uint16_t result)
+{
+	struct net_buf *buf;
+	struct bt_l2cap_conn_rsp *rsp;
+	struct bt_l2cap_sig_hdr *hdr;
+
+	buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
+
+	hdr = net_buf_add(buf, sizeof(*hdr));
+	hdr->code = BT_L2CAP_CONN_RSP;
+	hdr->ident = ident;
+	hdr->len = sys_cpu_to_le16(sizeof(*rsp));
+
+	rsp = net_buf_add(buf, sizeof(*rsp));
+	rsp->dcid = sys_cpu_to_le16(dcid);
+	rsp->scid = sys_cpu_to_le16(scid);
+	rsp->result = sys_cpu_to_le16(result);
+
+	if (result == BT_L2CAP_BR_PENDING) {
+		rsp->status = sys_cpu_to_le16(BT_L2CAP_CS_AUTHEN_PEND);
+	} else {
+		rsp->status = sys_cpu_to_le16(BT_L2CAP_CS_NO_INFO);
+	}
+
+	if (bt_l2cap_br_send_cb(conn, BT_L2CAP_CID_BR_SIG, buf, l2cap_br_conn_rsp_sent_cb,
+				UINT_TO_POINTER(scid))) {
+		net_buf_unref(buf);
+	}
+}
+
+static int l2cap_br_conn_req_reply(struct bt_l2cap_chan *chan, uint16_t result)
+{
+	/* Send response to connection request only when in acceptor role */
+	if (!atomic_test_bit(BR_CHAN(chan)->flags, L2CAP_FLAG_CONN_ACCEPTOR)) {
+		return -ESRCH;
+	}
+
+	l2cap_br_send_conn_rsp(chan->conn, BR_CHAN(chan)->tx.cid,
+			       BR_CHAN(chan)->rx.cid, BR_CHAN(chan)->ident, result);
+	BR_CHAN(chan)->ident = 0U;
+
+	return 0;
+}
+
+#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL) && defined(CONFIG_BT_L2CAP_LOG_LEVEL_DBG)
+void bt_l2cap_br_chan_set_state_debug(struct bt_l2cap_chan *chan,
+				   bt_l2cap_chan_state_t state,
+				   const char *func, int line)
+{
+	struct bt_l2cap_br_chan *br_chan;
+
+	br_chan = BR_CHAN(chan);
+
+	LOG_DBG("chan %p psm 0x%04x %s -> %s", chan, br_chan->psm,
+		bt_l2cap_chan_state_str(br_chan->state), bt_l2cap_chan_state_str(state));
+
+	/* check transitions validness */
+	switch (state) {
+	case BT_L2CAP_DISCONNECTED:
+		/* regardless of old state always allows this state */
+		break;
+	case BT_L2CAP_CONNECTING:
+		if (br_chan->state != BT_L2CAP_DISCONNECTED) {
+			LOG_WRN("%s()%d: invalid transition", func, line);
+		}
+		break;
+	case BT_L2CAP_CONFIG:
+		if (br_chan->state != BT_L2CAP_CONNECTING) {
+			LOG_WRN("%s()%d: invalid transition", func, line);
+		}
+		break;
+	case BT_L2CAP_CONNECTED:
+		if (br_chan->state != BT_L2CAP_CONFIG &&
+		    br_chan->state != BT_L2CAP_CONNECTING) {
+			LOG_WRN("%s()%d: invalid transition", func, line);
+		}
+		break;
+	case BT_L2CAP_DISCONNECTING:
+		if (br_chan->state != BT_L2CAP_CONFIG &&
+		    br_chan->state != BT_L2CAP_CONNECTED) {
+			LOG_WRN("%s()%d: invalid transition", func, line);
+		}
+		break;
+	default:
+		LOG_ERR("%s()%d: unknown (%u) state was set", func, line, state);
+		return;
+	}
+
+	br_chan->state = state;
+}
+#else
+void bt_l2cap_br_chan_set_state(struct bt_l2cap_chan *chan,
+			     bt_l2cap_chan_state_t state)
+{
+	BR_CHAN(chan)->state = state;
+}
+#endif /* CONFIG_BT_L2CAP_LOG_LEVEL_DBG && CONFIG_BT_L2CAP_DYNAMIC_CHANNEL*/
+
+void bt_l2cap_br_chan_del(struct bt_l2cap_chan *chan)
+{
+	const struct bt_l2cap_chan_ops *ops = chan->ops;
+	struct bt_l2cap_br_chan *br_chan = CONTAINER_OF(chan, struct bt_l2cap_br_chan, chan);
+
+	LOG_DBG("conn %p chan %p", chan->conn, chan);
+
+	if (!chan->conn) {
+		goto destroy;
+	}
+
+	cancel_data_ready(br_chan);
+
+	/* Remove buffers on the PDU TX queue. */
+	while (chan_has_data(br_chan)) {
+		const sys_snode_t *tx_buf = sys_slist_get(&br_chan->_pdu_tx_queue);
+
+		struct net_buf *buf = CONTAINER_OF(tx_buf, struct net_buf, node);
+
+		net_buf_unref(buf);
+	}
+
+	if (ops->disconnected) {
+		ops->disconnected(chan);
+	}
+
+	chan->conn = NULL;
+
+destroy:
+#if defined(CONFIG_BT_L2CAP_DYNAMIC_CHANNEL)
+	/* Reset internal members of common channel */
+	bt_l2cap_br_chan_set_state(chan, BT_L2CAP_DISCONNECTED);
+	BR_CHAN(chan)->psm = 0U;
+#endif
+	if (chan->destroy) {
+		chan->destroy(chan);
+	}
+
+	if (ops->released) {
+		ops->released(chan);
+	}
+}
+
+static void l2cap_br_conn_req(struct bt_l2cap_br *l2cap, uint8_t ident,
+			      struct net_buf *buf)
+{
+	struct bt_conn *conn = l2cap->chan.chan.conn;
+	struct bt_l2cap_chan *chan;
+	struct bt_l2cap_server *server;
+	struct bt_l2cap_conn_req *req = (void *)buf->data;
+	uint16_t psm, scid, result;
+	struct bt_l2cap_br_chan *br_chan;
+
+	if (buf->len < sizeof(*req)) {
+		LOG_ERR("Too small L2CAP conn req packet size");
+		return;
+	}
+
+	psm = sys_le16_to_cpu(req->psm);
+	scid = sys_le16_to_cpu(req->scid);
+
+	LOG_DBG("psm 0x%02x scid 0x%04x", psm, scid);
+
+	/* Check if there is a server registered */
+	server = l2cap_br_server_lookup_psm(psm);
+	if (!server) {
+		result = BT_L2CAP_BR_ERR_PSM_NOT_SUPP;
+		goto no_chan;
+	}
+
+	/*
+	 * Report security violation for non SDP channel without encryption when
+	 * remote supports SSP.
+	 */
+	if (server->sec_level != BT_SECURITY_L0 &&
+	    BT_FEAT_HOST_SSP(conn->br.features) && !conn->encrypt) {
+		result = BT_L2CAP_BR_ERR_SEC_BLOCK;
+		goto no_chan;
+	}
+
+	if (!L2CAP_BR_CID_IS_DYN(scid)) {
+		result = BT_L2CAP_BR_ERR_INVALID_SCID;
+		goto no_chan;
+	}
+
+	chan = bt_l2cap_br_lookup_tx_cid(conn, scid);
+	if (chan) {
+		/*
+		 * we have a chan here but this is due to SCID being already in
+		 * use so it is not channel we are suppose to pass to
+		 * l2cap_br_conn_req_reply as wrong DCID would be used
+		 */
+		result = BT_L2CAP_BR_ERR_SCID_IN_USE;
+		goto no_chan;
+	}
+
+	/*
+	 * Request server to accept the new connection and allocate the
+	 * channel. If no free channels available for PSM server reply with
+	 * proper result and quit since chan pointer is uninitialized then.
+	 */
+	if (server->accept(conn, server, &chan) < 0) {
+		result = BT_L2CAP_BR_ERR_NO_RESOURCES;
+		goto no_chan;
+	}
+
+	br_chan = BR_CHAN(chan);
+	br_chan->required_sec_level = server->sec_level;
+
+	l2cap_br_chan_add(conn, chan, l2cap_br_chan_destroy);
+	BR_CHAN(chan)->tx.cid = scid;
+	br_chan->ident = ident;
+	bt_l2cap_br_chan_set_state(chan, BT_L2CAP_CONNECTING);
+	atomic_set_bit(BR_CHAN(chan)->flags, L2CAP_FLAG_CONN_ACCEPTOR);
+
+#if !CONFIG_BT_L2CAP_RET_FC
+	/* Disable fragmentation of l2cap rx pdu */
+	BR_CHAN(chan)->rx.mtu = MIN(BR_CHAN(chan)->rx.mtu, BT_L2CAP_RX_MTU);
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+
+	switch (l2cap_br_conn_security(chan, psm)) {
+	case L2CAP_CONN_SECURITY_PENDING:
+		result = BT_L2CAP_BR_PENDING;
+		/* TODO: auth timeout */
+		break;
+	case L2CAP_CONN_SECURITY_PASSED:
+		result = BT_L2CAP_BR_SUCCESS;
+		break;
+	case L2CAP_CONN_SECURITY_REJECT:
+	default:
+		result = BT_L2CAP_BR_ERR_SEC_BLOCK;
+		/* Set disconnect ACL flag. */
+		atomic_set_bit(BR_CHAN(chan)->flags, L2CAP_FLAG_DISCONNECT_ACL);
+		break;
+	}
+	/* Reply on connection request as acceptor */
+	l2cap_br_conn_req_reply(chan, result);
+
+	if (result != BT_L2CAP_BR_SUCCESS) {
+		/* Disconnect link when security rules were violated */
+		if (result == BT_L2CAP_BR_ERR_SEC_BLOCK) {
+			/*
+			 * Disconnect the ACL after the packet of response has been sent.
+			 * The `L2CAP_FLAG_DISCONNECT_ACL` is used to flag whether ACL disconnect
+			 * request needs to be sent when the L2CAP conn rsp sent out callback is
+			 * triggered.
+			 */
+		} else if (result == BT_L2CAP_BR_PENDING) {
+			/* Recover the ident when conn is pending */
+			br_chan->ident = ident;
+		}
+
+		return;
+	}
+
+	bt_l2cap_br_chan_set_state(chan, BT_L2CAP_CONFIG);
+	l2cap_br_conf(chan, true);
+	return;
+
+no_chan:
+	l2cap_br_send_conn_rsp(conn, scid, 0, ident, result);
+}
+
+#define L2CAP_QOS_TOKEN_RATE_DEFAULT        0x00000000
+#define L2CAP_QOS_TOKEN_BUCKET_SIZE_DEFAULT 0x00000000
+#define L2CAP_QOS_PEAK_BANDWIDTH_DEFAULT    0x00000000
+#define L2CAP_QOS_LATENCY_DEFAULT           0xffffffff
+#define L2CAP_QOS_DELAY_DEFAULT             0xffffffff
+
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+static uint16_t l2cap_br_conf_rsp_opt_mtu(struct bt_l2cap_chan *chan, struct net_buf *buf,
+					  size_t len)
+{
+	uint16_t mtu, result = BT_L2CAP_CONF_SUCCESS;
+	struct bt_l2cap_conf_opt_mtu *opt_mtu;
+
+	/* Core 4.2 [Vol 3, Part A, 5.1] MTU payload length */
+	if (len != sizeof(*opt_mtu)) {
+		LOG_ERR("tx MTU length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	opt_mtu = (struct bt_l2cap_conf_opt_mtu *)buf->data;
+
+	mtu = sys_le16_to_cpu(opt_mtu->mtu);
+	if (mtu < L2CAP_BR_MIN_MTU) {
+		result = BT_L2CAP_CONF_UNACCEPT;
+		opt_mtu->mtu = sys_cpu_to_le16(BR_CHAN(chan)->rx.mtu);
+		LOG_DBG("tx MTU %u invalid", mtu);
+		goto done;
+	}
+
+	if (mtu < BR_CHAN(chan)->rx.mtu) {
+		BR_CHAN(chan)->rx.mtu = mtu;
+	}
+
+	LOG_DBG("rx MTU %u", BR_CHAN(chan)->rx.mtu);
+done:
+	return result;
+}
+
+static uint16_t l2cap_br_conf_rsp_opt_flush_timeout(struct bt_l2cap_chan *chan, struct net_buf *buf,
+						    size_t len)
+{
+	uint16_t result = BT_L2CAP_CONF_SUCCESS;
+	struct bt_l2cap_conf_opt_flush_timeout *opt_to;
+
+	if (len != sizeof(*opt_to)) {
+		LOG_ERR("qos frame length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	opt_to = (struct bt_l2cap_conf_opt_flush_timeout *)buf->data;
+
+	LOG_DBG("Flash timeout %u", opt_to->timeout);
+
+	opt_to->timeout = sys_cpu_to_le32(0xffff);
+	result = BT_L2CAP_CONF_UNACCEPT;
+done:
+	return result;
+}
+
+static uint16_t l2cap_br_conf_rsp_opt_qos(struct bt_l2cap_chan *chan, struct net_buf *buf,
+					  size_t len)
+{
+	uint16_t result = BT_L2CAP_CONF_SUCCESS;
+	struct bt_l2cap_conf_opt_qos *opt_qos;
+	struct bt_l2cap_chan *chan_sig;
+	struct bt_l2cap_br *br_chan_sig;
+
+	chan_sig = bt_l2cap_br_lookup_rx_cid(chan->conn, BT_L2CAP_CID_BR_SIG);
+	if (!chan_sig) {
+		LOG_WRN("Ignoring data for unknown channel ID 0x%04x", BT_L2CAP_CID_BR_SIG);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	br_chan_sig = CONTAINER_OF(chan_sig, struct bt_l2cap_br, chan.chan);
+	if (((br_chan_sig->info_feat_mask & L2CAP_FEAT_QOS_MASK) == 0) ||
+	    ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_QOS_MASK) == 0)) {
+		LOG_WRN("Unsupported extended flow spec");
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	if (len != sizeof(*opt_qos)) {
+		LOG_ERR("qos frame length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	opt_qos = (struct bt_l2cap_conf_opt_qos *)buf->data;
+
+	LOG_DBG("QOS Type %u", opt_qos->service_type);
+
+	if (opt_qos->service_type == BT_L2CAP_QOS_TYPE_GUARANTEED) {
+		result = BT_L2CAP_CONF_UNACCEPT;
+		/* Set to default value */
+		opt_qos->flags = 0x00;
+		/* do not care */
+		opt_qos->token_rate = sys_cpu_to_le32(L2CAP_QOS_TOKEN_RATE_DEFAULT);
+		/* no token bucket is needed */
+		opt_qos->token_bucket_size = sys_cpu_to_le32(L2CAP_QOS_TOKEN_BUCKET_SIZE_DEFAULT);
+		/* do not care */
+		opt_qos->peak_bandwidth = sys_cpu_to_le32(L2CAP_QOS_PEAK_BANDWIDTH_DEFAULT);
+		/* do not care */
+		opt_qos->latency = sys_cpu_to_le32(L2CAP_QOS_LATENCY_DEFAULT);
+		/* do not care */
+		opt_qos->delay_variation = sys_cpu_to_le32(L2CAP_QOS_DELAY_DEFAULT);
+	}
+
+done:
+	return result;
+}
+
+static uint16_t l2cap_br_conf_rsp_opt_ret_fc(struct bt_l2cap_chan *chan, struct net_buf *buf,
+					     size_t len)
+{
+	uint16_t result = BT_L2CAP_CONF_UNACCEPT;
+	struct bt_l2cap_conf_opt_ret_fc *opt_ret_fc;
+	struct bt_l2cap_br_chan *br_chan;
+	struct bt_l2cap_chan *chan_sig;
+	struct bt_l2cap_br *br_chan_sig;
+	bool accept = true;
+
+	if (len != sizeof(*opt_ret_fc)) {
+		LOG_ERR("ret_fc frame length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	chan_sig = bt_l2cap_br_lookup_rx_cid(chan->conn, BT_L2CAP_CID_BR_SIG);
+	if (!chan_sig) {
+		LOG_WRN("Ignoring data for unknown channel ID 0x%04x", BT_L2CAP_CID_BR_SIG);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	br_chan_sig = CONTAINER_OF(chan_sig, struct bt_l2cap_br, chan.chan);
+
+	opt_ret_fc = (struct bt_l2cap_conf_opt_ret_fc *)buf->data;
+
+	LOG_DBG("ret_fc mode %u", opt_ret_fc->mode);
+
+	br_chan = BR_CHAN(chan);
+
+	if (opt_ret_fc->mode != br_chan->rx.mode) {
+		if (br_chan->rx.optional) {
+			br_chan->rx.mode = opt_ret_fc->mode;
+		} else {
+			opt_ret_fc->mode = br_chan->rx.mode;
+			accept = false;
+		}
+	}
+
+	if (opt_ret_fc->mode != BT_L2CAP_BR_LINK_MODE_BASIC) {
+		if (sys_le16_to_cpu(opt_ret_fc->mps) < br_chan->rx.mps) {
+			br_chan->rx.mps = sys_le16_to_cpu(opt_ret_fc->mps);
+		} else {
+			opt_ret_fc->mps = sys_cpu_to_le16(br_chan->rx.mps);
+		}
+
+		if ((opt_ret_fc->mode == BT_L2CAP_BR_LINK_MODE_RET) ||
+		    (opt_ret_fc->mode == BT_L2CAP_BR_LINK_MODE_FC)) {
+			if ((opt_ret_fc->tx_windows_size < 1) ||
+			    (opt_ret_fc->tx_windows_size > 32)) {
+				opt_ret_fc->tx_windows_size = CONFIG_BT_L2CAP_MAX_WINDOW_SIZE;
+				accept = false;
+			}
+
+			if (opt_ret_fc->max_transmit < 1) {
+				opt_ret_fc->max_transmit = 1;
+				accept = false;
+			}
+		}
+
+		if (opt_ret_fc->mode == BT_L2CAP_BR_LINK_MODE_ERET) {
+			if ((opt_ret_fc->tx_windows_size < 1) ||
+			    (opt_ret_fc->tx_windows_size > 63)) {
+				opt_ret_fc->tx_windows_size = CONFIG_BT_L2CAP_MAX_WINDOW_SIZE;
+				accept = false;
+			}
+		}
+
+		opt_ret_fc->retransmission_timeout =
+			sys_cpu_to_le16(CONFIG_BT_L2CAP_BR_RET_TIMEOUT);
+		opt_ret_fc->monitor_timeout = sys_cpu_to_le16(CONFIG_BT_L2CAP_BR_MONITOR_TIMEOUT);
+
+		if (opt_ret_fc->tx_windows_size > CONFIG_BT_L2CAP_MAX_WINDOW_SIZE) {
+			opt_ret_fc->tx_windows_size =
+				sys_cpu_to_le16(CONFIG_BT_L2CAP_MAX_WINDOW_SIZE);
+		}
+
+		if (!accept) {
+			goto done;
+		}
+
+		br_chan->rx.ret_timeout = CONFIG_BT_L2CAP_BR_RET_TIMEOUT;
+		br_chan->rx.monitor_timeout = CONFIG_BT_L2CAP_BR_MONITOR_TIMEOUT;
+		br_chan->rx.max_transmit = opt_ret_fc->max_transmit;
+		br_chan->rx.max_window = sys_le16_to_cpu(opt_ret_fc->tx_windows_size);
+		br_chan->rx.mps = sys_le16_to_cpu(opt_ret_fc->mps);
+	}
+
+	if (!accept) {
+		goto done;
+	}
+
+	result = BT_L2CAP_CONF_SUCCESS;
+
+done:
+	return result;
+}
+
+static uint16_t l2cap_br_conf_rsp_opt_fcs(struct bt_l2cap_chan *chan, struct net_buf *buf,
+					  size_t len)
+{
+	uint16_t result = BT_L2CAP_CONF_SUCCESS;
+	struct bt_l2cap_conf_opt_fcs *opt_fcs;
+	struct bt_l2cap_br_chan *br_chan;
+
+	if (len != sizeof(*opt_fcs)) {
+		LOG_ERR("fcs frame length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	opt_fcs = (struct bt_l2cap_conf_opt_fcs *)buf->data;
+
+	LOG_DBG("FCS type %u", opt_fcs->type);
+
+	if ((opt_fcs->type != BT_L2CAP_FCS_TYPE_NO) && (opt_fcs->type != BT_L2CAP_FCS_TYPE_16BIT)) {
+		LOG_ERR("fcs type %u invalid", opt_fcs->type);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	br_chan = BR_CHAN(chan);
+
+	switch (br_chan->rx.mode) {
+	case BT_L2CAP_BR_LINK_MODE_BASIC:
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	case BT_L2CAP_BR_LINK_MODE_RET:
+		__fallthrough;
+	case BT_L2CAP_BR_LINK_MODE_FC:
+		LOG_ERR("fcs opt is mandatory in mode %u", br_chan->rx.mode);
+		if (opt_fcs->type != BT_L2CAP_BR_FCS_16BIT) {
+			result = BT_L2CAP_CONF_UNACCEPT;
+			opt_fcs->type = BT_L2CAP_BR_FCS_16BIT;
+			br_chan->rx.fcs = opt_fcs->type;
+			goto done;
+		}
+		break;
+	case BT_L2CAP_BR_LINK_MODE_ERET:
+		__fallthrough;
+	case BT_L2CAP_BR_LINK_MODE_STREAM:
+		br_chan->rx.fcs = opt_fcs->type;
+		break;
+	default:
+		/* Should not have been here */
+		LOG_ERR("Unknown mode %u", br_chan->rx.mode);
+		break;
+	}
+
+done:
+	return result;
+}
+
+#define L2CAP_EXT_FLOW_SPEC_SDU_DEFAULT 0xffff
+#define L2CAP_EXT_FLOW_SPEC_DEFAULT     0xffffffff
+
+static uint16_t l2cap_br_conf_rsp_opt_ext_flow_spec(struct bt_l2cap_chan *chan, struct net_buf *buf,
+						    size_t len)
+{
+	uint16_t result = BT_L2CAP_CONF_SUCCESS;
+	struct bt_l2cap_conf_opt_ext_flow_spec *ext_flow_spec;
+	struct bt_l2cap_br_chan *br_chan;
+
+	if (len != sizeof(*ext_flow_spec)) {
+		LOG_ERR("fcs frame length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	ext_flow_spec = (struct bt_l2cap_conf_opt_ext_flow_spec *)buf->data;
+
+	LOG_DBG("Ext Flow Spec %u %u %u %u %u %u", ext_flow_spec->identifier,
+		ext_flow_spec->service_type, ext_flow_spec->sdu,
+		ext_flow_spec->sdu_inter_arrival_time, ext_flow_spec->access_latency,
+		ext_flow_spec->flush_timeout);
+
+	br_chan = BR_CHAN(chan);
+
+	/* Set to default value */
+	result = BT_L2CAP_CONF_UNACCEPT;
+	ext_flow_spec->identifier = 0x01;
+	ext_flow_spec->service_type = 0x01;
+	ext_flow_spec->sdu = sys_cpu_to_le16(L2CAP_EXT_FLOW_SPEC_SDU_DEFAULT);
+	ext_flow_spec->sdu_inter_arrival_time = sys_cpu_to_le32(L2CAP_EXT_FLOW_SPEC_DEFAULT);
+	ext_flow_spec->access_latency = sys_cpu_to_le32(L2CAP_EXT_FLOW_SPEC_DEFAULT);
+	ext_flow_spec->flush_timeout = sys_cpu_to_le32(L2CAP_EXT_FLOW_SPEC_DEFAULT);
+
+done:
+	return result;
+}
+
+static uint16_t l2cap_br_conf_rsp_opt_ext_win_size(struct bt_l2cap_chan *chan, struct net_buf *buf,
+						   size_t len)
+{
+	uint16_t result = BT_L2CAP_CONF_SUCCESS;
+	struct bt_l2cap_conf_opt_ext_win_size *opt_ext_win_size;
+	struct bt_l2cap_br_chan *br_chan;
+	uint16_t win_size;
+
+	if (len != sizeof(*opt_ext_win_size)) {
+		LOG_ERR("fcs frame length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	opt_ext_win_size = (struct bt_l2cap_conf_opt_ext_win_size *)buf->data;
+	win_size = sys_le16_to_cpu(opt_ext_win_size->max_windows_size);
+
+	LOG_DBG("EXT Win Size value %u", win_size);
+
+	br_chan = BR_CHAN(chan);
+
+	switch (br_chan->rx.mode) {
+	case BT_L2CAP_BR_LINK_MODE_BASIC:
+		__fallthrough;
+	case BT_L2CAP_BR_LINK_MODE_RET:
+		__fallthrough;
+	case BT_L2CAP_BR_LINK_MODE_FC:
+		/* ignore */
+		LOG_WRN("Ignored by mode %u", br_chan->rx.mode);
+		break;
+	case BT_L2CAP_BR_LINK_MODE_ERET:
+		if ((win_size < 1) || (win_size > CONFIG_BT_L2CAP_MAX_WINDOW_SIZE)) {
+			/* Set to default value */
+			opt_ext_win_size->max_windows_size =
+				sys_cpu_to_le16(CONFIG_BT_L2CAP_MAX_WINDOW_SIZE);
+			result = BT_L2CAP_CONF_UNACCEPT;
+			goto done;
+		}
+
+		br_chan->tx.extended_control = true;
+		br_chan->tx.max_window = win_size;
+		break;
+	case BT_L2CAP_BR_LINK_MODE_STREAM:
+		if (win_size) {
+			result = BT_L2CAP_CONF_UNACCEPT;
+			opt_ext_win_size->max_windows_size = 0;
+			goto done;
+		}
+		br_chan->tx.extended_control = true;
+		break;
+	default:
+		/* Should not have been here */
+		LOG_ERR("Unknown mode %u", br_chan->rx.mode);
+		break;
+	}
+
+done:
+	return result;
+}
+
+static int l2cap_br_conf_rsp_opt_check(struct bt_l2cap_chan *chan, uint16_t opt_len,
+				       struct net_buf *buf)
+{
+	struct bt_l2cap_conf_opt *opt = NULL;
+	uint16_t result = BT_L2CAP_CONF_SUCCESS;
+	uint8_t hint;
+
+	if (opt_len > buf->len) {
+		return -EINVAL;
+	}
+
+	while (opt_len >= sizeof(*opt)) {
+		opt = net_buf_pull_mem(buf, sizeof(*opt));
+
+		opt_len -= sizeof(*opt);
+
+		if (opt_len < opt->len) {
+			LOG_ERR("Received too short option data");
+			return -EINVAL;
+		}
+
+		opt_len -= opt->len;
+
+		hint = opt->type & BT_L2CAP_CONF_HINT;
+		if (hint) {
+			return -EINVAL;
+		}
+
+		switch (opt->type & BT_L2CAP_CONF_MASK) {
+		case BT_L2CAP_CONF_OPT_MTU:
+			/* getting MTU modifies buf internals */
+			result = l2cap_br_conf_rsp_opt_mtu(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto invalid_opt;
+			}
+			break;
+		case BT_L2CAP_CONF_OPT_FLUSH_TIMEOUT:
+			result = l2cap_br_conf_rsp_opt_flush_timeout(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto invalid_opt;
+			}
+			break;
+		case BT_L2CAP_CONF_OPT_QOS:
+			result = l2cap_br_conf_rsp_opt_qos(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto invalid_opt;
+			}
+			break;
+		case BT_L2CAP_CONF_OPT_RET_FC:
+			result = l2cap_br_conf_rsp_opt_ret_fc(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto invalid_opt;
+			}
+			break;
+		case BT_L2CAP_CONF_OPT_FCS:
+			result = l2cap_br_conf_rsp_opt_fcs(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto invalid_opt;
+			}
+			break;
+		case BT_L2CAP_CONF_OPT_EXT_FLOW_SPEC:
+			result = l2cap_br_conf_rsp_opt_ext_flow_spec(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto invalid_opt;
+			}
+			break;
+		case BT_L2CAP_CONF_OPT_EXT_WIN_SIZE:
+			result = l2cap_br_conf_rsp_opt_ext_win_size(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto invalid_opt;
+			}
+			break;
+		default:
+			result = BT_L2CAP_CONF_UNKNOWN_OPT;
+			goto invalid_opt;
+		}
+		net_buf_pull(buf, opt->len);
+	}
+
+	if (BR_CHAN(chan)->rx.fcs == BT_L2CAP_BR_FCS_16BIT) {
+		/* If local enable FCS, peer also needs to enable it. */
+		BR_CHAN(chan)->tx.fcs = BT_L2CAP_BR_FCS_16BIT;
+	}
+
+	if (BR_CHAN(chan)->rx.extended_control) {
+		/* If peer enables extended control field,
+		 * local also needs to enable it.
+		 */
+		BR_CHAN(chan)->tx.extended_control = true;
+	}
+
+	return 0;
+
+invalid_opt:
+	return -EINVAL;
+}
+
+static uint16_t l2cap_br_conf_rsp_unaccept_opt_mtu(struct bt_l2cap_chan *chan, struct net_buf *buf,
+						   size_t len)
+{
+	uint16_t mtu, result = BT_L2CAP_CONF_SUCCESS;
+	struct bt_l2cap_conf_opt_mtu *opt_mtu;
+
+	/* Core 4.2 [Vol 3, Part A, 5.1] MTU payload length */
+	if (len != sizeof(*opt_mtu)) {
+		LOG_ERR("tx MTU length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	opt_mtu = (struct bt_l2cap_conf_opt_mtu *)buf->data;
+
+	mtu = sys_le16_to_cpu(opt_mtu->mtu);
+	if (mtu < L2CAP_BR_MIN_MTU) {
+		LOG_DBG("tx MTU %u invalid", mtu);
+		goto done;
+	}
+
+	if (mtu < BR_CHAN(chan)->rx.mtu) {
+		BR_CHAN(chan)->rx.mtu = mtu;
+	}
+
+done:
+	LOG_DBG("rx MTU %u", BR_CHAN(chan)->rx.mtu);
+	return result;
+}
+
+static uint16_t l2cap_br_conf_rsp_unaccept_opt_flush_timeout(struct bt_l2cap_chan *chan,
+							     struct net_buf *buf, size_t len)
+{
+	uint16_t result = BT_L2CAP_CONF_SUCCESS;
+	struct bt_l2cap_conf_opt_flush_timeout *opt_to;
+
+	if (len != sizeof(*opt_to)) {
+		LOG_ERR("qos frame length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	opt_to = (struct bt_l2cap_conf_opt_flush_timeout *)buf->data;
+
+	LOG_DBG("Flash timeout %u", opt_to->timeout);
+
+done:
+	return result;
+}
+
+static uint16_t l2cap_br_conf_rsp_unaccept_opt_qos(struct bt_l2cap_chan *chan, struct net_buf *buf,
+						   size_t len)
+{
+	uint16_t result = BT_L2CAP_CONF_SUCCESS;
+	struct bt_l2cap_conf_opt_qos *opt_qos;
+	struct bt_l2cap_chan *chan_sig;
+	struct bt_l2cap_br *br_chan_sig;
+
+	chan_sig = bt_l2cap_br_lookup_rx_cid(chan->conn, BT_L2CAP_CID_BR_SIG);
+	if (!chan_sig) {
+		LOG_WRN("Ignoring data for unknown channel ID 0x%04x", BT_L2CAP_CID_BR_SIG);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	br_chan_sig = CONTAINER_OF(chan_sig, struct bt_l2cap_br, chan.chan);
+	if (((br_chan_sig->info_feat_mask & L2CAP_FEAT_QOS_MASK) == 0) ||
+	    ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_QOS_MASK) == 0)) {
+		LOG_WRN("Unsupported extended flow spec");
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	if (len != sizeof(*opt_qos)) {
+		LOG_ERR("qos frame length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	opt_qos = (struct bt_l2cap_conf_opt_qos *)buf->data;
+
+	LOG_DBG("QOS Type %u", opt_qos->service_type);
+
+done:
+	return result;
+}
+
+static uint16_t l2cap_br_conf_rsp_unaccept_opt_ret_fc(struct bt_l2cap_chan *chan,
+						      struct net_buf *buf, size_t len)
+{
+	uint16_t result = BT_L2CAP_CONF_UNACCEPT;
+	struct bt_l2cap_conf_opt_ret_fc *opt_ret_fc;
+	struct bt_l2cap_br_chan *br_chan;
+
+	if (len != sizeof(*opt_ret_fc)) {
+		LOG_ERR("ret_fc frame length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	opt_ret_fc = (struct bt_l2cap_conf_opt_ret_fc *)buf->data;
+
+	LOG_DBG("ret_fc mode %u", opt_ret_fc->mode);
+
+	br_chan = BR_CHAN(chan);
+
+	if (opt_ret_fc->mode != br_chan->rx.mode) {
+		if (br_chan->rx.optional) {
+			br_chan->rx.mode = opt_ret_fc->mode;
+		} else {
+			goto done;
+		}
+	}
+
+	if (opt_ret_fc->mode != BT_L2CAP_BR_LINK_MODE_BASIC) {
+		if (sys_le16_to_cpu(opt_ret_fc->mps) > br_chan->rx.mtu) {
+			opt_ret_fc->mps = sys_cpu_to_le16(br_chan->rx.mtu);
+		}
+
+		if ((opt_ret_fc->mode == BT_L2CAP_BR_LINK_MODE_RET) ||
+		    (opt_ret_fc->mode == BT_L2CAP_BR_LINK_MODE_FC)) {
+			if ((opt_ret_fc->tx_windows_size < 1) ||
+			    (opt_ret_fc->tx_windows_size > 32)) {
+				opt_ret_fc->tx_windows_size = CONFIG_BT_L2CAP_MAX_WINDOW_SIZE;
+			}
+
+			if (opt_ret_fc->max_transmit < 1) {
+				opt_ret_fc->max_transmit = 1;
+			}
+		}
+
+		if (opt_ret_fc->mode == BT_L2CAP_BR_LINK_MODE_ERET) {
+			if ((opt_ret_fc->tx_windows_size < 1) ||
+			    (opt_ret_fc->tx_windows_size > 63)) {
+				opt_ret_fc->tx_windows_size = CONFIG_BT_L2CAP_MAX_WINDOW_SIZE;
+			}
+		}
+
+		opt_ret_fc->retransmission_timeout =
+			sys_cpu_to_le16(CONFIG_BT_L2CAP_BR_RET_TIMEOUT);
+		opt_ret_fc->monitor_timeout = sys_cpu_to_le16(CONFIG_BT_L2CAP_BR_MONITOR_TIMEOUT);
+
+		if (opt_ret_fc->tx_windows_size > CONFIG_BT_L2CAP_MAX_WINDOW_SIZE) {
+			opt_ret_fc->tx_windows_size = CONFIG_BT_L2CAP_MAX_WINDOW_SIZE;
+		}
+
+		br_chan->rx.ret_timeout = CONFIG_BT_L2CAP_BR_RET_TIMEOUT;
+		br_chan->rx.monitor_timeout = CONFIG_BT_L2CAP_BR_MONITOR_TIMEOUT;
+		br_chan->rx.max_transmit = opt_ret_fc->max_transmit;
+		br_chan->rx.max_window = opt_ret_fc->tx_windows_size;
+		br_chan->rx.mps = sys_le16_to_cpu(opt_ret_fc->mps);
+	}
+
+	if (br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_BASIC) {
+		br_chan->tx.mode = BT_L2CAP_BR_LINK_MODE_BASIC;
+	}
+
+	result = BT_L2CAP_CONF_SUCCESS;
+
+done:
+	return result;
+}
+
+static uint16_t l2cap_br_conf_rsp_unaccept_opt_fcs(struct bt_l2cap_chan *chan, struct net_buf *buf,
+						   size_t len)
+{
+	uint16_t result = BT_L2CAP_CONF_SUCCESS;
+	struct bt_l2cap_conf_opt_fcs *opt_fcs;
+	struct bt_l2cap_br_chan *br_chan;
+
+	if (len != sizeof(*opt_fcs)) {
+		LOG_ERR("fcs frame length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	opt_fcs = (struct bt_l2cap_conf_opt_fcs *)buf->data;
+
+	LOG_DBG("FCS type %u", opt_fcs->type);
+
+	if ((opt_fcs->type != BT_L2CAP_FCS_TYPE_NO) && (opt_fcs->type != BT_L2CAP_FCS_TYPE_16BIT)) {
+		LOG_ERR("fcs type %u invalid", opt_fcs->type);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	br_chan = BR_CHAN(chan);
+
+	switch (br_chan->rx.mode) {
+	case BT_L2CAP_BR_LINK_MODE_BASIC:
+		goto done;
+	case BT_L2CAP_BR_LINK_MODE_RET:
+		__fallthrough;
+	case BT_L2CAP_BR_LINK_MODE_FC:
+		LOG_ERR("fcs opt is mandatory in mode %u", br_chan->rx.mode);
+		br_chan->rx.fcs = BT_L2CAP_BR_FCS_16BIT;
+		break;
+	case BT_L2CAP_BR_LINK_MODE_ERET:
+		__fallthrough;
+	case BT_L2CAP_BR_LINK_MODE_STREAM:
+		br_chan->rx.fcs = opt_fcs->type;
+		break;
+	default:
+		/* Should not have been here */
+		LOG_ERR("Unknown mode %u", br_chan->rx.mode);
+		break;
+	}
+
+done:
+	return result;
+}
+
+static uint16_t l2cap_br_conf_rsp_unaccept_opt_ext_flow_spec(struct bt_l2cap_chan *chan,
+							     struct net_buf *buf, size_t len)
+{
+	uint16_t result = BT_L2CAP_CONF_SUCCESS;
+	struct bt_l2cap_conf_opt_ext_flow_spec *ext_flow_spec;
+
+	if (len != sizeof(*ext_flow_spec)) {
+		LOG_ERR("fcs frame length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	ext_flow_spec = (struct bt_l2cap_conf_opt_ext_flow_spec *)buf->data;
+
+	LOG_DBG("Ext Flow Spec %u %u %u %u %u %u", ext_flow_spec->identifier,
+		ext_flow_spec->service_type, ext_flow_spec->sdu,
+		ext_flow_spec->sdu_inter_arrival_time, ext_flow_spec->access_latency,
+		ext_flow_spec->flush_timeout);
+done:
+	return result;
+}
+
+static uint16_t l2cap_br_conf_rsp_unaccept_opt_ext_win_size(struct bt_l2cap_chan *chan,
+							    struct net_buf *buf, size_t len)
+{
+	uint16_t result = BT_L2CAP_CONF_SUCCESS;
+	struct bt_l2cap_conf_opt_ext_win_size *opt_ext_win_size;
+	struct bt_l2cap_br_chan *br_chan;
+	uint16_t win_size;
+
+	if (len != sizeof(*opt_ext_win_size)) {
+		LOG_ERR("fcs frame length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	opt_ext_win_size = (struct bt_l2cap_conf_opt_ext_win_size *)buf->data;
+	win_size = sys_le16_to_cpu(opt_ext_win_size->max_windows_size);
+
+	LOG_DBG("EXT Win Size value %u", win_size);
+
+	br_chan = BR_CHAN(chan);
+
+	switch (br_chan->rx.mode) {
+	case BT_L2CAP_BR_LINK_MODE_BASIC:
+		__fallthrough;
+	case BT_L2CAP_BR_LINK_MODE_RET:
+		__fallthrough;
+	case BT_L2CAP_BR_LINK_MODE_FC:
+		/* ignore */
+		LOG_WRN("Ignored by mode %u", br_chan->rx.mode);
+		break;
+	case BT_L2CAP_BR_LINK_MODE_ERET:
+		__fallthrough;
+	case BT_L2CAP_BR_LINK_MODE_STREAM:
+		if ((win_size < 1) || (win_size > CONFIG_BT_L2CAP_MAX_WINDOW_SIZE)) {
+			/* Set to default value */
+			br_chan->rx.max_window = CONFIG_BT_L2CAP_MAX_WINDOW_SIZE;
+		} else {
+			br_chan->rx.max_window = win_size;
+		}
+		break;
+	default:
+		/* Should not have been here */
+		LOG_ERR("Unknown mode %u", br_chan->rx.mode);
+		break;
+	}
+
+done:
+	return result;
+}
+
+static int l2cap_br_conf_rsp_unaccept_opt(struct bt_l2cap_chan *chan, uint16_t opt_len,
+					  struct net_buf *buf)
+{
+	struct bt_l2cap_conf_opt *opt = NULL;
+	uint16_t result = BT_L2CAP_CONF_SUCCESS;
+	uint8_t hint;
+
+	if (opt_len > buf->len) {
+		return -EINVAL;
+	}
+
+	while (opt_len >= sizeof(*opt)) {
+		opt = net_buf_pull_mem(buf, sizeof(*opt));
+
+		opt_len -= sizeof(*opt);
+
+		if (opt_len < opt->len) {
+			LOG_ERR("Received too short option data");
+			return -EINVAL;
+		}
+
+		opt_len -= opt->len;
+
+		hint = opt->type & BT_L2CAP_CONF_HINT;
+		if (hint) {
+			return -EINVAL;
+		}
+
+		switch (opt->type & BT_L2CAP_CONF_MASK) {
+		case BT_L2CAP_CONF_OPT_MTU:
+			/* getting MTU modifies buf internals */
+			result = l2cap_br_conf_rsp_unaccept_opt_mtu(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto invalid_opt;
+			}
+			break;
+		case BT_L2CAP_CONF_OPT_FLUSH_TIMEOUT:
+			result = l2cap_br_conf_rsp_unaccept_opt_flush_timeout(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto invalid_opt;
+			}
+			break;
+		case BT_L2CAP_CONF_OPT_QOS:
+			result = l2cap_br_conf_rsp_unaccept_opt_qos(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto invalid_opt;
+			}
+			break;
+		case BT_L2CAP_CONF_OPT_RET_FC:
+			result = l2cap_br_conf_rsp_unaccept_opt_ret_fc(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto invalid_opt;
+			}
+			break;
+		case BT_L2CAP_CONF_OPT_FCS:
+			result = l2cap_br_conf_rsp_unaccept_opt_fcs(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto invalid_opt;
+			}
+			break;
+		case BT_L2CAP_CONF_OPT_EXT_FLOW_SPEC:
+			result = l2cap_br_conf_rsp_unaccept_opt_ext_flow_spec(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto invalid_opt;
+			}
+			break;
+		case BT_L2CAP_CONF_OPT_EXT_WIN_SIZE:
+			result = l2cap_br_conf_rsp_unaccept_opt_ext_win_size(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto invalid_opt;
+			}
+			break;
+		default:
+			result = BT_L2CAP_CONF_UNKNOWN_OPT;
+			goto invalid_opt;
+		}
+		net_buf_pull(buf, opt->len);
+	}
+
+	if (BR_CHAN(chan)->rx.fcs == BT_L2CAP_BR_FCS_16BIT) {
+		/* If local enable FCS, peer also needs to enable it. */
+		BR_CHAN(chan)->tx.fcs = BT_L2CAP_BR_FCS_16BIT;
+	}
+
+	return 0;
+
+invalid_opt:
+	return -EINVAL;
+}
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+
+static void l2cap_br_conf_rsp(struct bt_l2cap_br *l2cap, uint8_t ident, uint16_t len,
+			      struct net_buf *buf)
+{
+	struct bt_conn *conn = l2cap->chan.chan.conn;
+	struct bt_l2cap_chan *chan;
+	struct bt_l2cap_conf_rsp *rsp = (void *)buf->data;
+	uint16_t flags, scid, result, opt_len;
+	struct bt_l2cap_br_chan *br_chan;
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	int err;
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+
+	if (buf->len < sizeof(*rsp)) {
+		LOG_ERR("Too small L2CAP conf rsp packet size");
+		return;
+	}
+
+	net_buf_pull(buf, sizeof(*rsp));
+
+	flags = sys_le16_to_cpu(rsp->flags);
+	scid = sys_le16_to_cpu(rsp->scid);
+	result = sys_le16_to_cpu(rsp->result);
+	opt_len = len - sizeof(*rsp);
+
+	LOG_DBG("scid 0x%04x flags 0x%02x result 0x%02x len %u", scid, flags, result, opt_len);
+
+	chan = bt_l2cap_br_lookup_rx_cid(conn, scid);
+	if (!chan) {
+		LOG_ERR("channel mismatch!");
+		return;
+	}
+
+	br_chan = BR_CHAN(chan);
+	if (br_chan->ident != ident) {
+		LOG_WRN("ident mismatch (%u != %u)!", br_chan->ident, ident);
+		return;
+	}
+	br_chan->ident = 0;
+
+	/* Release RTX work since got the response */
+	k_work_cancel_delayable(&br_chan->rtx_work);
+
+	/*
+	 * TODO: handle other results than success and parse response data if
+	 * available
+	 */
+	switch (result) {
+	case BT_L2CAP_CONF_SUCCESS:
+		atomic_set_bit(br_chan->flags, L2CAP_FLAG_CONN_LCONF_DONE);
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+		err = l2cap_br_conf_rsp_opt_check(chan, opt_len, buf);
+		if (err) {
+			/* currently disconnect channel if opt is invalid */
+			bt_l2cap_chan_disconnect(chan);
+			break;
+		}
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+		if (br_chan->state == BT_L2CAP_CONFIG &&
+		    atomic_test_bit(br_chan->flags, L2CAP_FLAG_CONN_RCONF_DONE)) {
+			LOG_DBG("scid 0x%04x rx MTU %u dcid 0x%04x tx MTU %u", br_chan->rx.cid,
+				br_chan->rx.mtu, br_chan->tx.cid, br_chan->tx.mtu);
+
+			bt_l2cap_br_chan_set_state(chan, BT_L2CAP_CONNECTED);
+			if (chan->ops && chan->ops->connected) {
+				chan->ops->connected(chan);
+			}
+		}
+		break;
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	case BT_L2CAP_CONF_UNACCEPT:
+		err = l2cap_br_conf_rsp_unaccept_opt(chan, opt_len, buf);
+		if (!err) {
+			l2cap_br_conf(chan, false);
+			break;
+		}
+		__fallthrough;
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+	default:
+		/* currently disconnect channel on non success result */
+		bt_l2cap_chan_disconnect(chan);
+		break;
+	}
+}
+
+static int bt_l2cap_br_allocate_psm(uint16_t *psm)
+{
+	/* DYN_END is UINT16_MAX, so to be able to do a psm <= DYN_END comparison
+	 * we need to use uint32_t as the type.
+	 */
+	static uint32_t allocated_psm = L2CAP_BR_PSM_DYN_START;
+
+	if (allocated_psm < L2CAP_BR_PSM_DYN_END) {
+		allocated_psm = allocated_psm + 1;
+	} else {
+		goto failed;
+	}
+
+	for (; allocated_psm <= L2CAP_BR_PSM_DYN_END; allocated_psm++) {
+		/* Bluetooth Core Specification Version 6.0 | Vol 3, Part A, section 4.2
+		 *
+		 * The PSM field is at least two octets in length. All PSM values shall have
+		 * the least significant bit of the most significant octet equal to 0 and the
+		 * least significant bit of all other octets equal to 1.
+		 */
+		if ((allocated_psm & 0x0101) != 0x0001) {
+			continue;
+		}
+
+		if (l2cap_br_server_lookup_psm((uint16_t)allocated_psm)) {
+			LOG_DBG("PSM 0x%04x has been used", allocated_psm);
+			continue;
+		}
+
+		LOG_DBG("Allocated PSM 0x%04x for new server", allocated_psm);
+		*psm = (uint16_t)allocated_psm;
+		return 0;
+	}
+
+failed:
+	LOG_WRN("No free dynamic PSMs available");
+	return -EADDRNOTAVAIL;
+}
+
+bt_security_t bt_l2cap_br_get_max_sec_level(void)
+{
+	struct bt_l2cap_server *server;
+	bt_security_t sec_level = BT_SECURITY_L0;
+
+	SYS_SLIST_FOR_EACH_CONTAINER(&br_servers, server, node) {
+		if (sec_level < server->sec_level) {
+			sec_level = server->sec_level;
+		}
+	}
+
+	return sec_level;
+}
+
+int bt_l2cap_br_server_register(struct bt_l2cap_server *server)
+{
+	int err;
+
+	if (!server->accept) {
+		return -EINVAL;
+	}
+
+	if (server->sec_level > BT_SECURITY_L4) {
+		return -EINVAL;
+	} else if (server->sec_level == BT_SECURITY_L0 && server->psm != L2CAP_BR_PSM_SDP) {
+		server->sec_level = BT_SECURITY_L1;
+	}
+
+	if (!server->psm) {
+		err = bt_l2cap_br_allocate_psm(&server->psm);
+		if (err) {
+			return err;
+		}
+	} else {
+		/* PSM must be odd and lsb of upper byte must be 0 */
+		if ((server->psm & 0x0101) != 0x0001) {
+			LOG_WRN("PSM must be odd and lsb of upper byte must be 0");
+			return -EINVAL;
+		}
+
+		/* Check if given PSM is already in use */
+		if (l2cap_br_server_lookup_psm(server->psm)) {
+			LOG_WRN("PSM already registered");
+			return -EADDRINUSE;
+		}
+	}
+
+	LOG_DBG("PSM 0x%04x", server->psm);
+
+	sys_slist_append(&br_servers, &server->node);
+
+	return 0;
+}
+
+static void l2cap_br_send_reject(struct bt_conn *conn, uint8_t ident, uint16_t reason, void *data,
+				 uint8_t data_len)
+{
+	struct bt_l2cap_cmd_reject *rej;
+	struct bt_l2cap_sig_hdr *hdr;
+	struct net_buf *buf;
+
+	buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
+
+	hdr = net_buf_add(buf, sizeof(*hdr));
+	hdr->code = BT_L2CAP_CMD_REJECT;
+	hdr->ident = ident;
+	hdr->len = sys_cpu_to_le16(sizeof(*rej) + data_len);
+
+	rej = net_buf_add(buf, sizeof(*rej));
+	rej->reason = sys_cpu_to_le16(reason);
+
+	/*
+	 * optional data if available must be already in little-endian format
+	 * made by caller.and be compliant with Core 4.2 [Vol 3, Part A, 4.1,
+	 * table 4.4]
+	 */
+	if (data) {
+		net_buf_add_mem(buf, data, data_len);
+	}
+
+	l2cap_send(conn, BT_L2CAP_CID_BR_SIG, buf);
+}
+
+static uint16_t l2cap_br_conf_opt_mtu(struct bt_l2cap_chan *chan, struct net_buf *buf, size_t len)
+{
+	uint16_t mtu, result = BT_L2CAP_CONF_SUCCESS;
+	struct bt_l2cap_conf_opt_mtu *opt_mtu;
+
+	/* Core 4.2 [Vol 3, Part A, 5.1] MTU payload length */
+	if (len != sizeof(*opt_mtu)) {
+		LOG_ERR("tx MTU length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	opt_mtu = (struct bt_l2cap_conf_opt_mtu *)buf->data;
+
+	mtu = sys_le16_to_cpu(opt_mtu->mtu);
+	if (mtu < L2CAP_BR_MIN_MTU) {
+		result = BT_L2CAP_CONF_UNACCEPT;
+		BR_CHAN(chan)->tx.mtu = L2CAP_BR_MIN_MTU;
+		opt_mtu->mtu = sys_cpu_to_le16(L2CAP_BR_MIN_MTU);
+		LOG_DBG("tx MTU %u invalid", mtu);
+		goto done;
+	}
+
+	BR_CHAN(chan)->tx.mtu = mtu;
+	LOG_DBG("tx MTU %u", mtu);
+done:
+	return result;
+}
+
+static uint16_t l2cap_br_conf_opt_flush_timeout(struct bt_l2cap_chan *chan, struct net_buf *buf,
+						size_t len)
+{
+	uint16_t result = BT_L2CAP_CONF_SUCCESS;
+	struct bt_l2cap_conf_opt_flush_timeout *opt_to;
+
+	if (len != sizeof(*opt_to)) {
+		LOG_ERR("qos frame length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	opt_to = (struct bt_l2cap_conf_opt_flush_timeout *)buf->data;
+
+	LOG_DBG("Flush timeout %u", opt_to->timeout);
+
+	opt_to->timeout = sys_cpu_to_le16(0xffff);
+	result = BT_L2CAP_CONF_UNACCEPT;
+done:
+	return result;
+}
+
+static uint16_t l2cap_br_conf_opt_qos(struct bt_l2cap_chan *chan, struct net_buf *buf, size_t len)
+{
+	uint16_t result = BT_L2CAP_CONF_SUCCESS;
+	struct bt_l2cap_conf_opt_qos *opt_qos;
+	struct bt_l2cap_chan *chan_sig;
+	struct bt_l2cap_br *br_chan_sig;
+
+	chan_sig = bt_l2cap_br_lookup_rx_cid(chan->conn, BT_L2CAP_CID_BR_SIG);
+	if (!chan_sig) {
+		LOG_WRN("Ignoring data for unknown channel ID 0x%04x", BT_L2CAP_CID_BR_SIG);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	br_chan_sig = CONTAINER_OF(chan_sig, struct bt_l2cap_br, chan.chan);
+	if (((br_chan_sig->info_feat_mask & L2CAP_FEAT_QOS_MASK) == 0) ||
+	    ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_QOS_MASK) == 0)) {
+		LOG_WRN("Unsupported extended flow spec");
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	if (len != sizeof(*opt_qos)) {
+		LOG_ERR("qos frame length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	opt_qos = (struct bt_l2cap_conf_opt_qos *)buf->data;
+
+	LOG_DBG("QOS Type %u", opt_qos->service_type);
+
+	if (opt_qos->service_type == BT_L2CAP_QOS_TYPE_GUARANTEED) {
+		result = BT_L2CAP_CONF_UNACCEPT;
+		/* Set to default value */
+		opt_qos->flags = 0x00;
+		/* do not care */
+		opt_qos->token_rate = sys_cpu_to_le32(L2CAP_QOS_TOKEN_RATE_DEFAULT);
+		/* no token bucket is needed */
+		opt_qos->token_bucket_size = sys_cpu_to_le32(L2CAP_QOS_TOKEN_BUCKET_SIZE_DEFAULT);
+		/* do not care */
+		opt_qos->peak_bandwidth = sys_cpu_to_le32(L2CAP_QOS_PEAK_BANDWIDTH_DEFAULT);
+		/* do not care */
+		opt_qos->latency = sys_cpu_to_le32(L2CAP_QOS_LATENCY_DEFAULT);
+		/* do not care */
+		opt_qos->delay_variation = sys_cpu_to_le32(L2CAP_QOS_DELAY_DEFAULT);
+	}
+
+done:
+	return result;
+}
+
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+static uint16_t l2cap_br_conf_opt_ret_fc(struct bt_l2cap_chan *chan, struct net_buf *buf,
+					 size_t len)
+{
+	uint16_t result = BT_L2CAP_CONF_UNACCEPT;
+	struct bt_l2cap_conf_opt_ret_fc *opt_ret_fc;
+	struct bt_l2cap_br_chan *br_chan;
+	struct bt_l2cap_chan *chan_sig;
+	struct bt_l2cap_br *br_chan_sig;
+	uint16_t retransmission_timeout;
+	uint16_t monitor_timeout;
+	bool accept = true;
+	uint8_t mode;
+
+	if (len != sizeof(*opt_ret_fc)) {
+		LOG_ERR("ret_fc frame length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	chan_sig = bt_l2cap_br_lookup_rx_cid(chan->conn, BT_L2CAP_CID_BR_SIG);
+	if (!chan_sig) {
+		LOG_WRN("Ignoring data for unknown channel ID 0x%04x", BT_L2CAP_CID_BR_SIG);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	br_chan_sig = CONTAINER_OF(chan_sig, struct bt_l2cap_br, chan.chan);
+
+	opt_ret_fc = (struct bt_l2cap_conf_opt_ret_fc *)buf->data;
+
+	LOG_DBG("ret_fc mode %u", opt_ret_fc->mode);
+
+	br_chan = BR_CHAN(chan);
+
+	mode = opt_ret_fc->mode;
+
+	switch (opt_ret_fc->mode) {
+	case BT_L2CAP_BR_LINK_MODE_BASIC:
+		break;
+	case BT_L2CAP_BR_LINK_MODE_RET:
+		__fallthrough;
+	case BT_L2CAP_BR_LINK_MODE_FC:
+		if (((br_chan_sig->info_feat_mask & L2CAP_FEAT_ENH_RET_MASK) != 0) &&
+		    ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_ENH_RET_MASK) != 0)) {
+			/* If enhance transmission mode is supported by both side,
+			 * the enhance transmission mode should be used instead of
+			 * transmission or flow control mode.
+			 */
+			mode = BT_L2CAP_BR_LINK_MODE_ERET;
+		} else {
+			if ((opt_ret_fc->mode == BT_L2CAP_BR_LINK_MODE_FC) &&
+			    (((br_chan_sig->info_feat_mask & L2CAP_FEAT_FC_MASK) == 0) ||
+			     ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_FC_MASK) == 0))) {
+				mode = BT_L2CAP_BR_LINK_MODE_BASIC;
+			}
+
+			if ((opt_ret_fc->mode == BT_L2CAP_BR_LINK_MODE_RET) &&
+			    (((br_chan_sig->info_feat_mask & L2CAP_FEAT_RET_MASK) == 0) ||
+			     ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_RET_MASK) == 0))) {
+				mode = BT_L2CAP_BR_LINK_MODE_BASIC;
+			}
+		}
+		break;
+	case BT_L2CAP_BR_LINK_MODE_ERET:
+		if (((br_chan_sig->info_feat_mask & L2CAP_FEAT_ENH_RET_MASK) == 0) ||
+		    ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_ENH_RET_MASK) == 0)) {
+			/* If enhance transmission mode is unsupported by any side,
+			 * the transmission mode should be used instead of
+			 * enhance transmission mode.
+			 */
+			if (((br_chan_sig->info_feat_mask & L2CAP_FEAT_RET_MASK) != 0) &&
+			    ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_RET_MASK) != 0)) {
+				mode = BT_L2CAP_BR_LINK_MODE_RET;
+			} else if (((br_chan_sig->info_feat_mask & L2CAP_FEAT_FC_MASK) != 0) &&
+				   ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_FC_MASK) != 0)) {
+				mode = BT_L2CAP_BR_LINK_MODE_FC;
+			} else {
+				mode = BT_L2CAP_BR_LINK_MODE_BASIC;
+			}
+		}
+		break;
+	case BT_L2CAP_BR_LINK_MODE_STREAM:
+		if (((br_chan_sig->info_feat_mask & L2CAP_FEAT_STREAM_MASK) == 0) ||
+		    ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_STREAM_MASK) == 0)) {
+			/* Unsupported mode */
+			mode = BT_L2CAP_BR_LINK_MODE_BASIC;
+		}
+		break;
+	default:
+		mode = BT_L2CAP_BR_LINK_MODE_BASIC;
+		break;
+	}
+
+	if (!br_chan->rx.optional) {
+		switch (mode) {
+		case BT_L2CAP_BR_LINK_MODE_BASIC:
+			__fallthrough;
+		case BT_L2CAP_BR_LINK_MODE_ERET:
+			__fallthrough;
+		case BT_L2CAP_BR_LINK_MODE_STREAM:
+			/* The tx mode should be same as rx mode */
+			if (mode != br_chan->rx.mode) {
+				mode = br_chan->rx.mode;
+			}
+			break;
+		case BT_L2CAP_BR_LINK_MODE_RET:
+			__fallthrough;
+		case BT_L2CAP_BR_LINK_MODE_FC:
+			/* The tx mode should be aligned with rx mode */
+			if ((br_chan->rx.mode != BT_L2CAP_BR_LINK_MODE_RET) &&
+			    (br_chan->rx.mode != BT_L2CAP_BR_LINK_MODE_FC)) {
+				mode = br_chan->rx.mode;
+			}
+			break;
+		default:
+			break;
+		}
+	} else {
+		if (br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_BASIC) {
+			mode = br_chan->rx.mode;
+		} else {
+			br_chan->rx.mode = mode;
+		}
+	}
+
+	if (opt_ret_fc->mode != mode) {
+		accept = false;
+		opt_ret_fc->mode = mode;
+	}
+
+	br_chan->tx.mode = mode;
+
+	if (opt_ret_fc->mode != BT_L2CAP_BR_LINK_MODE_BASIC) {
+		uint16_t mps = CONFIG_BT_L2CAP_MPS;
+
+		if (sys_le16_to_cpu(opt_ret_fc->mps) > br_chan->tx.mtu) {
+			opt_ret_fc->mps = sys_cpu_to_le16(br_chan->tx.mtu);
+			accept = false;
+		}
+
+		if (sys_le16_to_cpu(opt_ret_fc->mps) > mps) {
+			opt_ret_fc->mps = sys_cpu_to_le16(mps);
+		}
+
+		if ((opt_ret_fc->mode == BT_L2CAP_BR_LINK_MODE_RET) ||
+		    (opt_ret_fc->mode == BT_L2CAP_BR_LINK_MODE_FC)) {
+			if ((opt_ret_fc->tx_windows_size < 1) ||
+			    (opt_ret_fc->tx_windows_size > 32)) {
+				opt_ret_fc->tx_windows_size = CONFIG_BT_L2CAP_MAX_WINDOW_SIZE;
+				accept = false;
+			}
+
+			if (opt_ret_fc->max_transmit < 1) {
+				opt_ret_fc->max_transmit = 1;
+				accept = false;
+			}
+		}
+
+		if (opt_ret_fc->mode == BT_L2CAP_BR_LINK_MODE_ERET) {
+			if ((opt_ret_fc->tx_windows_size < 1) ||
+			    (opt_ret_fc->tx_windows_size > 63)) {
+				opt_ret_fc->tx_windows_size = CONFIG_BT_L2CAP_MAX_WINDOW_SIZE;
+				accept = false;
+			}
+		}
+
+		retransmission_timeout = sys_le16_to_cpu(opt_ret_fc->retransmission_timeout);
+
+		monitor_timeout = sys_le16_to_cpu(opt_ret_fc->monitor_timeout);
+		if (monitor_timeout < retransmission_timeout) {
+			monitor_timeout = retransmission_timeout;
+			accept = false;
+		}
+
+		if (opt_ret_fc->tx_windows_size > CONFIG_BT_L2CAP_MAX_WINDOW_SIZE) {
+			opt_ret_fc->tx_windows_size = CONFIG_BT_L2CAP_MAX_WINDOW_SIZE;
+		}
+
+		opt_ret_fc->retransmission_timeout = sys_cpu_to_le16(retransmission_timeout);
+		opt_ret_fc->monitor_timeout = sys_cpu_to_le16(monitor_timeout);
+
+		if (!accept) {
+			goto done;
+		}
+
+		br_chan->tx.ret_timeout = retransmission_timeout;
+		br_chan->tx.monitor_timeout = monitor_timeout;
+		br_chan->tx.max_transmit = opt_ret_fc->max_transmit;
+		br_chan->tx.max_window = opt_ret_fc->tx_windows_size;
+		br_chan->tx.mps = sys_le16_to_cpu(opt_ret_fc->mps);
+	}
+
+	if (!accept) {
+		goto done;
+	}
+
+	result = BT_L2CAP_CONF_SUCCESS;
+
+done:
+	return result;
+}
+
+static uint16_t l2cap_br_conf_opt_fcs(struct bt_l2cap_chan *chan, struct net_buf *buf, size_t len)
+{
+	uint16_t result = BT_L2CAP_CONF_SUCCESS;
+	struct bt_l2cap_conf_opt_fcs *opt_fcs;
+	struct bt_l2cap_br_chan *br_chan;
+	struct bt_l2cap_chan *chan_sig;
+	struct bt_l2cap_br *br_chan_sig;
+
+	chan_sig = bt_l2cap_br_lookup_rx_cid(chan->conn, BT_L2CAP_CID_BR_SIG);
+	if (!chan_sig) {
+		LOG_WRN("Ignoring data for unknown channel ID 0x%04x", BT_L2CAP_CID_BR_SIG);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	br_chan_sig = CONTAINER_OF(chan_sig, struct bt_l2cap_br, chan.chan);
+	if (((br_chan_sig->info_feat_mask & L2CAP_FEAT_FCS_MASK) == 0) ||
+	    ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_FCS_MASK) == 0)) {
+		LOG_WRN("Unsupported extended flow spec");
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	if (len != sizeof(*opt_fcs)) {
+		LOG_ERR("fcs frame length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	opt_fcs = (struct bt_l2cap_conf_opt_fcs *)buf->data;
+
+	LOG_DBG("FCS type %u", opt_fcs->type);
+
+	if ((opt_fcs->type != BT_L2CAP_FCS_TYPE_NO) && (opt_fcs->type != BT_L2CAP_FCS_TYPE_16BIT)) {
+		LOG_ERR("fcs type %u invalid", opt_fcs->type);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	br_chan = BR_CHAN(chan);
+
+	switch (br_chan->tx.mode) {
+	case BT_L2CAP_BR_LINK_MODE_BASIC:
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	case BT_L2CAP_BR_LINK_MODE_RET:
+		__fallthrough;
+	case BT_L2CAP_BR_LINK_MODE_FC:
+		LOG_ERR("fcs opt is mandatory in mode %u", br_chan->tx.mode);
+		if (opt_fcs->type != BT_L2CAP_BR_FCS_16BIT) {
+			result = BT_L2CAP_CONF_UNACCEPT;
+			opt_fcs->type = BT_L2CAP_BR_FCS_16BIT;
+			br_chan->tx.fcs = opt_fcs->type;
+			goto done;
+		}
+		br_chan->tx.fcs = BT_L2CAP_BR_FCS_16BIT;
+		break;
+	case BT_L2CAP_BR_LINK_MODE_ERET:
+		__fallthrough;
+	case BT_L2CAP_BR_LINK_MODE_STREAM:
+		br_chan->tx.fcs = opt_fcs->type;
+		break;
+	default:
+		/* Should not have been here */
+		LOG_ERR("Unknown mode %u", br_chan->tx.mode);
+		break;
+	}
+
+done:
+	return result;
+}
+
+static uint16_t l2cap_br_conf_opt_ext_flow_spec(struct bt_l2cap_chan *chan, struct net_buf *buf,
+						size_t len)
+{
+	uint16_t result = BT_L2CAP_CONF_SUCCESS;
+	struct bt_l2cap_conf_opt_ext_flow_spec *ext_flow_spec;
+	struct bt_l2cap_br_chan *br_chan;
+	struct bt_l2cap_chan *chan_sig;
+	struct bt_l2cap_br *br_chan_sig;
+
+	chan_sig = bt_l2cap_br_lookup_rx_cid(chan->conn, BT_L2CAP_CID_BR_SIG);
+	if (!chan_sig) {
+		LOG_WRN("Ignoring data for unknown channel ID 0x%04x", BT_L2CAP_CID_BR_SIG);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	br_chan_sig = CONTAINER_OF(chan_sig, struct bt_l2cap_br, chan.chan);
+	if (((br_chan_sig->info_feat_mask & L2CAP_FEAT_EXT_FS_MASK) == 0) ||
+	    ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_EXT_FS_MASK) == 0)) {
+		LOG_WRN("Unsupported extended flow spec");
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	if (len != sizeof(*ext_flow_spec)) {
+		LOG_ERR("fcs frame length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	ext_flow_spec = (struct bt_l2cap_conf_opt_ext_flow_spec *)buf->data;
+
+	LOG_DBG("Ext Flow Spec %u %u %u %u %u %u", ext_flow_spec->identifier,
+		ext_flow_spec->service_type, ext_flow_spec->sdu,
+		ext_flow_spec->sdu_inter_arrival_time, ext_flow_spec->access_latency,
+		ext_flow_spec->flush_timeout);
+
+	br_chan = BR_CHAN(chan);
+
+	/* Set to default value */
+	result = BT_L2CAP_CONF_REJECT;
+	ext_flow_spec->identifier = 0x01;
+	ext_flow_spec->service_type = 0x01;
+	ext_flow_spec->sdu = sys_cpu_to_le16(L2CAP_EXT_FLOW_SPEC_SDU_DEFAULT);
+	ext_flow_spec->sdu_inter_arrival_time = sys_cpu_to_le32(L2CAP_EXT_FLOW_SPEC_DEFAULT);
+	ext_flow_spec->access_latency = sys_cpu_to_le32(L2CAP_EXT_FLOW_SPEC_DEFAULT);
+	ext_flow_spec->flush_timeout = sys_cpu_to_le32(L2CAP_EXT_FLOW_SPEC_DEFAULT);
+
+done:
+	return result;
+}
+
+static uint16_t l2cap_br_conf_opt_ext_win_size(struct bt_l2cap_chan *chan, struct net_buf *buf,
+					       size_t len)
+{
+	uint16_t result = BT_L2CAP_CONF_SUCCESS;
+	struct bt_l2cap_conf_opt_ext_win_size *opt_ext_win_size;
+	struct bt_l2cap_br_chan *br_chan;
+	uint16_t win_size;
+	struct bt_l2cap_chan *chan_sig;
+	struct bt_l2cap_br *br_chan_sig;
+
+	chan_sig = bt_l2cap_br_lookup_rx_cid(chan->conn, BT_L2CAP_CID_BR_SIG);
+	if (!chan_sig) {
+		LOG_WRN("Ignoring data for unknown channel ID 0x%04x", BT_L2CAP_CID_BR_SIG);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	br_chan_sig = CONTAINER_OF(chan_sig, struct bt_l2cap_br, chan.chan);
+	if (((br_chan_sig->info_feat_mask & L2CAP_FEAT_EXT_WIN_SIZE_MASK) == 0) ||
+	    ((L2CAP_EXTENDED_FEAT_MASK & L2CAP_FEAT_EXT_WIN_SIZE_MASK) == 0)) {
+		LOG_WRN("Unsupported extended window size");
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	if (len != sizeof(*opt_ext_win_size)) {
+		LOG_ERR("fcs frame length %zu invalid", len);
+		result = BT_L2CAP_CONF_REJECT;
+		goto done;
+	}
+
+	opt_ext_win_size = (struct bt_l2cap_conf_opt_ext_win_size *)buf->data;
+	win_size = sys_le16_to_cpu(opt_ext_win_size->max_windows_size);
+
+	LOG_DBG("EXT Win Size value %u", win_size);
+
+	br_chan = BR_CHAN(chan);
+
+	switch (br_chan->tx.mode) {
+	case BT_L2CAP_BR_LINK_MODE_BASIC:
+		__fallthrough;
+	case BT_L2CAP_BR_LINK_MODE_RET:
+		__fallthrough;
+	case BT_L2CAP_BR_LINK_MODE_FC:
+		/* ignore */
+		LOG_WRN("Ignored by mode %u", br_chan->tx.mode);
+		break;
+	case BT_L2CAP_BR_LINK_MODE_ERET:
+		if ((win_size < 1) || (win_size > 0x3fff)) {
+			/* Set to default value */
+			opt_ext_win_size->max_windows_size =
+				sys_cpu_to_le16(CONFIG_BT_L2CAP_MAX_WINDOW_SIZE);
+			result = BT_L2CAP_CONF_UNACCEPT;
+			goto done;
+		}
+		if (win_size > CONFIG_BT_L2CAP_MAX_WINDOW_SIZE) {
+			opt_ext_win_size->max_windows_size =
+				sys_cpu_to_le16(CONFIG_BT_L2CAP_MAX_WINDOW_SIZE);
+		}
+		br_chan->tx.extended_control = true;
+		br_chan->tx.max_window = win_size;
+		break;
+	case BT_L2CAP_BR_LINK_MODE_STREAM:
+		if (win_size) {
+			result = BT_L2CAP_CONF_UNACCEPT;
+			opt_ext_win_size->max_windows_size = 0;
+			goto done;
+		}
+		br_chan->tx.extended_control = true;
+		break;
+	default:
+		/* Should not have been here */
+		LOG_ERR("Unknown mode %u", br_chan->tx.mode);
+		break;
+	}
+
+done:
+	return result;
+}
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+
+static void l2cap_br_conf_req(struct bt_l2cap_br *l2cap, uint8_t ident, uint16_t len,
+			      struct net_buf *buf)
+{
+	struct bt_conn *conn = l2cap->chan.chan.conn;
+	struct bt_l2cap_chan *chan;
+	struct bt_l2cap_conf_req *req;
+	struct bt_l2cap_sig_hdr *hdr;
+	struct bt_l2cap_conf_rsp *rsp;
+	struct bt_l2cap_conf_opt *opt = NULL;
+	uint16_t flags, dcid, opt_len, hint, result = BT_L2CAP_CONF_SUCCESS;
+	struct net_buf *rsp_buf;
+
+	if (buf->len < sizeof(*req)) {
+		LOG_ERR("Too small L2CAP conf req packet size");
+		return;
+	}
+
+	req = net_buf_pull_mem(buf, sizeof(*req));
+	flags = sys_le16_to_cpu(req->flags);
+	dcid = sys_le16_to_cpu(req->dcid);
+	opt_len = len - sizeof(*req);
+
+	LOG_DBG("dcid 0x%04x flags 0x%02x len %u", dcid, flags, opt_len);
+
+	chan = bt_l2cap_br_lookup_rx_cid(conn, dcid);
+	if (!chan) {
+		LOG_ERR("rx channel mismatch!");
+		struct bt_l2cap_cmd_reject_cid_data data = {
+			.scid = req->dcid,
+			.dcid = 0,
+		};
+
+		l2cap_br_send_reject(conn, ident, BT_L2CAP_REJ_INVALID_CID, &data, sizeof(data));
+		return;
+	}
+
+	rsp_buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
+
+	hdr = net_buf_add(rsp_buf, sizeof(*hdr));
+	hdr->code = BT_L2CAP_CONF_RSP;
+	hdr->ident = ident;
+	rsp = net_buf_add(rsp_buf, sizeof(*rsp));
+	(void)memset(rsp, 0, sizeof(*rsp));
+
+	rsp->scid = sys_cpu_to_le16(BR_CHAN(chan)->tx.cid);
+
+	/*
+	 * Core 5.4, Vol 3, Part A, section 4.5.
+	 * When used in the L2CAP_CONFIGURATION_RSP packet,
+	 * the continuation flag shall be set to one if the
+	 * flag is set to one in the Request, except for
+	 * those error conditions more appropriate for an
+	 * L2CAP_COMMAND_REJECT_RSP packet.
+	 */
+	rsp->flags = sys_cpu_to_le16(flags & BT_L2CAP_CONF_FLAGS_MASK);
+
+	if (!opt_len) {
+		LOG_DBG("tx default MTU %u", L2CAP_BR_DEFAULT_MTU);
+		BR_CHAN(chan)->tx.mtu = L2CAP_BR_DEFAULT_MTU;
+		goto send_rsp;
+	}
+
+	while (opt_len >= sizeof(*opt)) {
+		opt = net_buf_pull_mem(buf, sizeof(*opt));
+
+		opt_len -= sizeof(*opt);
+
+		/* make sure opt object can get safe dereference in iteration */
+		if (opt_len < opt->len) {
+			LOG_ERR("Received too short option data");
+			result = BT_L2CAP_CONF_REJECT;
+			break;
+		}
+
+		opt_len -= opt->len;
+
+		hint = opt->type & BT_L2CAP_CONF_HINT;
+
+		switch (opt->type & BT_L2CAP_CONF_MASK) {
+		case BT_L2CAP_CONF_OPT_MTU:
+			/* getting MTU modifies buf internals */
+			result = l2cap_br_conf_opt_mtu(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto send_rsp;
+			}
+			break;
+		case BT_L2CAP_CONF_OPT_FLUSH_TIMEOUT:
+			result = l2cap_br_conf_opt_flush_timeout(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto send_rsp;
+			}
+			break;
+		case BT_L2CAP_CONF_OPT_QOS:
+			result = l2cap_br_conf_opt_qos(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto send_rsp;
+			}
+			break;
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+		case BT_L2CAP_CONF_OPT_RET_FC:
+			result = l2cap_br_conf_opt_ret_fc(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto send_rsp;
+			} else {
+				l2cap_br_conf_add_opt(rsp_buf, opt);
+			}
+			break;
+		case BT_L2CAP_CONF_OPT_FCS:
+			result = l2cap_br_conf_opt_fcs(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto send_rsp;
+			}
+			break;
+		case BT_L2CAP_CONF_OPT_EXT_FLOW_SPEC:
+			result = l2cap_br_conf_opt_ext_flow_spec(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto send_rsp;
+			}
+			break;
+		case BT_L2CAP_CONF_OPT_EXT_WIN_SIZE:
+			result = l2cap_br_conf_opt_ext_win_size(chan, buf, opt->len);
+			if (result != BT_L2CAP_CONF_SUCCESS) {
+				goto send_rsp;
+			} else {
+				l2cap_br_conf_add_opt(rsp_buf, opt);
+			}
+			break;
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+		default:
+			if (!hint) {
+				LOG_DBG("option %u not handled", opt->type);
+				result = BT_L2CAP_CONF_UNKNOWN_OPT;
+				goto send_rsp;
+			}
+			break;
+		}
+
+		/* Update buffer to point at next option */
+		net_buf_pull(buf, opt->len);
+	}
+
+send_rsp:
+	rsp->result = sys_cpu_to_le16(result);
+
+	/*
+	 * TODO: If options other than MTU became meaningful then processing
 	 * the options chain need to be modified and taken into account when
 	 * sending back to peer.
 	 */
-	if ((result == BT_L2CAP_CONF_UNKNOWN_OPT) || (result == BT_L2CAP_CONF_UNACCEPT)) {
-		if (opt) {
-			l2cap_br_conf_add_opt(buf, opt);
+	if ((result == BT_L2CAP_CONF_UNKNOWN_OPT) || (result == BT_L2CAP_CONF_UNACCEPT)) {
+		if (opt) {
+			l2cap_br_conf_add_opt(rsp_buf, opt);
+		}
+	}
+
+	hdr->len = sys_cpu_to_le16(rsp_buf->len - sizeof(*hdr));
+
+	l2cap_send(conn, BT_L2CAP_CID_BR_SIG, rsp_buf);
+
+	if (result != BT_L2CAP_CONF_SUCCESS) {
+		return;
+	}
+
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	if (BR_CHAN(chan)->tx.fcs == BT_L2CAP_BR_FCS_16BIT) {
+		/* If peer enables FCS, local also needs to enable it. */
+		BR_CHAN(chan)->rx.fcs = BT_L2CAP_BR_FCS_16BIT;
+	}
+
+	if (BR_CHAN(chan)->tx.extended_control) {
+		/* If peer enables extended control field,
+		 * local also needs to enable it.
+		 */
+		BR_CHAN(chan)->rx.extended_control = true;
+	}
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+
+	atomic_set_bit(BR_CHAN(chan)->flags, L2CAP_FLAG_CONN_RCONF_DONE);
+
+	if (atomic_test_bit(BR_CHAN(chan)->flags, L2CAP_FLAG_CONN_LCONF_DONE) &&
+	    BR_CHAN(chan)->state == BT_L2CAP_CONFIG) {
+		LOG_DBG("scid 0x%04x rx MTU %u dcid 0x%04x tx MTU %u", BR_CHAN(chan)->rx.cid,
+			BR_CHAN(chan)->rx.mtu, BR_CHAN(chan)->tx.cid, BR_CHAN(chan)->tx.mtu);
+
+		bt_l2cap_br_chan_set_state(chan, BT_L2CAP_CONNECTED);
+		if (chan->ops && chan->ops->connected) {
+			chan->ops->connected(chan);
+		}
+	}
+}
+
+static struct bt_l2cap_br_chan *l2cap_br_remove_tx_cid(struct bt_conn *conn, uint16_t cid)
+{
+	struct bt_l2cap_chan *chan;
+	sys_snode_t *prev = NULL;
+
+	/* Protect fixed channels against accidental removal */
+	if (!L2CAP_BR_CID_IS_DYN(cid)) {
+		return NULL;
+	}
+
+	SYS_SLIST_FOR_EACH_CONTAINER(&conn->channels, chan, node) {
+		if (BR_CHAN(chan)->tx.cid == cid) {
+			sys_slist_remove(&conn->channels, prev, &chan->node);
+			return BR_CHAN(chan);
+		}
+
+		prev = &chan->node;
+	}
+
+	return NULL;
+}
+
+static void l2cap_br_disconn_req(struct bt_l2cap_br *l2cap, uint8_t ident, struct net_buf *buf)
+{
+	struct bt_conn *conn = l2cap->chan.chan.conn;
+	struct bt_l2cap_br_chan *chan;
+	struct bt_l2cap_disconn_req *req = (void *)buf->data;
+	struct bt_l2cap_disconn_rsp *rsp;
+	struct bt_l2cap_sig_hdr *hdr;
+	uint16_t scid, dcid;
+
+	if (buf->len < sizeof(*req)) {
+		LOG_ERR("Too small disconn req packet size");
+		return;
+	}
+
+	dcid = sys_le16_to_cpu(req->dcid);
+	scid = sys_le16_to_cpu(req->scid);
+
+	LOG_DBG("scid 0x%04x dcid 0x%04x", dcid, scid);
+
+	chan = l2cap_br_remove_tx_cid(conn, scid);
+	if (!chan) {
+		struct bt_l2cap_cmd_reject_cid_data data;
+
+		data.scid = req->scid;
+		data.dcid = req->dcid;
+		l2cap_br_send_reject(conn, ident, BT_L2CAP_REJ_INVALID_CID, &data, sizeof(data));
+		return;
+	}
+
+	buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
+
+	hdr = net_buf_add(buf, sizeof(*hdr));
+	hdr->code = BT_L2CAP_DISCONN_RSP;
+	hdr->ident = ident;
+	hdr->len = sys_cpu_to_le16(sizeof(*rsp));
+
+	rsp = net_buf_add(buf, sizeof(*rsp));
+	rsp->dcid = sys_cpu_to_le16(chan->rx.cid);
+	rsp->scid = sys_cpu_to_le16(chan->tx.cid);
+
+	bt_l2cap_br_chan_del(&chan->chan);
+
+	l2cap_send(conn, BT_L2CAP_CID_BR_SIG, buf);
+}
+
+static void l2cap_br_connected(struct bt_l2cap_chan *chan)
+{
+	LOG_DBG("ch %p cid 0x%04x", BR_CHAN(chan), BR_CHAN(chan)->rx.cid);
+}
+
+static void l2cap_br_disconnected(struct bt_l2cap_chan *chan)
+{
+	struct bt_l2cap_br_chan *br_chan = BR_CHAN(chan);
+
+	LOG_DBG("ch %p cid 0x%04x", br_chan, br_chan->rx.cid);
+
+	if (atomic_test_and_clear_bit(br_chan->flags, L2CAP_FLAG_SIG_INFO_PENDING)) {
+		/* Cancel RTX work on signal channel.
+		 * Disconnected callback is always called from system workqueue
+		 * so this should always succeed.
+		 */
+		(void)k_work_cancel_delayable(&br_chan->rtx_work);
+	}
+}
+
+int bt_l2cap_br_chan_disconnect(struct bt_l2cap_chan *chan)
+{
+	struct bt_conn *conn = chan->conn;
+	struct net_buf *buf;
+	struct bt_l2cap_disconn_req *req;
+	struct bt_l2cap_sig_hdr *hdr;
+	struct bt_l2cap_br_chan *br_chan;
+
+	if (!conn) {
+		return -ENOTCONN;
+	}
+
+	br_chan = BR_CHAN(chan);
+
+	if (br_chan->state == BT_L2CAP_DISCONNECTING) {
+		return -EALREADY;
+	}
+
+	LOG_DBG("chan %p scid 0x%04x dcid 0x%04x", chan, br_chan->rx.cid, br_chan->tx.cid);
+
+	buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
+
+	hdr = net_buf_add(buf, sizeof(*hdr));
+	hdr->code = BT_L2CAP_DISCONN_REQ;
+	hdr->ident = l2cap_br_get_ident();
+	hdr->len = sys_cpu_to_le16(sizeof(*req));
+
+	req = net_buf_add(buf, sizeof(*req));
+	req->dcid = sys_cpu_to_le16(br_chan->tx.cid);
+	req->scid = sys_cpu_to_le16(br_chan->rx.cid);
+
+	/* Set the ident for the signaling request */
+	br_chan->ident = hdr->ident;
+
+	l2cap_br_chan_send_req(br_chan, buf, L2CAP_BR_DISCONN_TIMEOUT);
+	bt_l2cap_br_chan_set_state(chan, BT_L2CAP_DISCONNECTING);
+
+	return 0;
+}
+
+static void l2cap_br_disconn_rsp(struct bt_l2cap_br *l2cap, uint8_t ident, struct net_buf *buf)
+{
+	struct bt_conn *conn = l2cap->chan.chan.conn;
+	struct bt_l2cap_br_chan *chan;
+	struct bt_l2cap_disconn_rsp *rsp = (void *)buf->data;
+	uint16_t dcid, scid;
+
+	if (buf->len < sizeof(*rsp)) {
+		LOG_ERR("Too small disconn rsp packet size");
+		return;
+	}
+
+	dcid = sys_le16_to_cpu(rsp->dcid);
+	scid = sys_le16_to_cpu(rsp->scid);
+
+	LOG_DBG("dcid 0x%04x scid 0x%04x", dcid, scid);
+
+	chan = l2cap_br_remove_tx_cid(conn, dcid);
+	if (!chan) {
+		LOG_WRN("No dcid 0x%04x channel found", dcid);
+		return;
+	}
+
+	if (chan->ident != ident) {
+		LOG_WRN("ident mismatch (%u != %u)!", chan->ident, ident);
+		return;
+	}
+	chan->ident = 0;
+
+	bt_l2cap_br_chan_del(&chan->chan);
+}
+
+int bt_l2cap_br_chan_connect(struct bt_conn *conn, struct bt_l2cap_chan *chan, uint16_t psm)
+{
+	struct net_buf *buf;
+	struct bt_l2cap_sig_hdr *hdr;
+	struct bt_l2cap_conn_req *req;
+	struct bt_l2cap_br_chan *br_chan = BR_CHAN(chan);
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	int err;
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+
+	if (!psm) {
+		return -EINVAL;
+	}
+
+	if (br_chan->psm) {
+		return -EEXIST;
+	}
+
+	/* PSM must be odd and lsb of upper byte must be 0 */
+	if ((psm & 0x0101) != 0x0001) {
+		return -EINVAL;
+	}
+
+	if (br_chan->required_sec_level > BT_SECURITY_L4) {
+		return -EINVAL;
+	} else if (br_chan->required_sec_level == BT_SECURITY_L0 && psm != L2CAP_BR_PSM_SDP) {
+		br_chan->required_sec_level = BT_SECURITY_L1;
+	}
+
+	switch (br_chan->state) {
+	case BT_L2CAP_CONNECTED:
+		/* Already connected */
+		return -EISCONN;
+	case BT_L2CAP_DISCONNECTED:
+		/* Can connect */
+		break;
+	case BT_L2CAP_CONFIG:
+	case BT_L2CAP_DISCONNECTING:
+	default:
+		/* Bad context */
+		return -EBUSY;
+	}
+
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	err = l2cap_br_check_chan_config(conn, br_chan);
+	if (err) {
+		return err;
+	}
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+
+	if (!l2cap_br_chan_add(conn, chan, l2cap_br_chan_destroy)) {
+		return -ENOMEM;
+	}
+
+	br_chan->psm = psm;
+	bt_l2cap_br_chan_set_state(chan, BT_L2CAP_CONNECTING);
+	atomic_set_bit(BR_CHAN(chan)->flags, L2CAP_FLAG_CONN_PENDING);
+
+	switch (l2cap_br_conn_security(chan, psm)) {
+	case L2CAP_CONN_SECURITY_PENDING:
+		/*
+		 * Authentication was triggered, wait with sending request on
+		 * connection security changed callback context.
+		 */
+		return 0;
+	case L2CAP_CONN_SECURITY_PASSED:
+		break;
+	case L2CAP_CONN_SECURITY_REJECT:
+	default:
+		l2cap_br_chan_cleanup(chan);
+		return -EIO;
+	}
+
+	buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
+
+	hdr = net_buf_add(buf, sizeof(*hdr));
+	hdr->code = BT_L2CAP_CONN_REQ;
+	hdr->ident = l2cap_br_get_ident();
+	hdr->len = sys_cpu_to_le16(sizeof(*req));
+
+	req = net_buf_add(buf, sizeof(*req));
+	req->psm = sys_cpu_to_le16(psm);
+	req->scid = sys_cpu_to_le16(BR_CHAN(chan)->rx.cid);
+
+	/* Set the ident for the signaling request */
+	BR_CHAN(chan)->ident = hdr->ident;
+
+	l2cap_br_chan_send_req(BR_CHAN(chan), buf, L2CAP_BR_CONN_TIMEOUT);
+
+	return 0;
+}
+
+static void l2cap_br_conn_rsp(struct bt_l2cap_br *l2cap, uint8_t ident, struct net_buf *buf)
+{
+	struct bt_conn *conn = l2cap->chan.chan.conn;
+	struct bt_l2cap_chan *chan;
+	struct bt_l2cap_conn_rsp *rsp = (void *)buf->data;
+	uint16_t dcid, scid, result, status;
+	struct bt_l2cap_br_chan *br_chan;
+
+	if (buf->len < sizeof(*rsp)) {
+		LOG_ERR("Too small L2CAP conn rsp packet size");
+		return;
+	}
+
+	dcid = sys_le16_to_cpu(rsp->dcid);
+	scid = sys_le16_to_cpu(rsp->scid);
+	result = sys_le16_to_cpu(rsp->result);
+	status = sys_le16_to_cpu(rsp->status);
+
+	LOG_DBG("dcid 0x%04x scid 0x%04x result %u status %u", dcid, scid, result, status);
+
+	chan = bt_l2cap_br_lookup_rx_cid(conn, scid);
+	if (!chan) {
+		LOG_ERR("No scid 0x%04x channel found", scid);
+		return;
+	}
+
+	br_chan = BR_CHAN(chan);
+	if (br_chan->ident != ident) {
+		LOG_WRN("ident mismatch (%u != %u)!", br_chan->ident, ident);
+		return;
+	}
+	br_chan->ident = 0;
+
+	/* Release RTX work since got the response */
+	k_work_cancel_delayable(&br_chan->rtx_work);
+
+	if (br_chan->state != BT_L2CAP_CONNECTING) {
+		LOG_DBG("Invalid channel %p state %s", chan,
+			bt_l2cap_chan_state_str(br_chan->state));
+		return;
+	}
+
+	switch (result) {
+	case BT_L2CAP_BR_SUCCESS:
+		br_chan->ident = 0U;
+		BR_CHAN(chan)->tx.cid = dcid;
+		l2cap_br_conf(chan, true);
+		bt_l2cap_br_chan_set_state(chan, BT_L2CAP_CONFIG);
+		atomic_clear_bit(BR_CHAN(chan)->flags, L2CAP_FLAG_CONN_PENDING);
+		break;
+	case BT_L2CAP_BR_PENDING:
+		br_chan->ident = ident;
+		k_work_reschedule(&br_chan->rtx_work, L2CAP_BR_CONN_TIMEOUT);
+		break;
+	default:
+		l2cap_br_chan_cleanup(chan);
+		break;
+	}
+}
+
+int bt_l2cap_br_chan_send_cb(struct bt_l2cap_chan *chan, struct net_buf *buf, bt_conn_tx_cb_t cb,
+			     void *user_data)
+{
+	struct bt_l2cap_br_chan *br_chan;
+
+	if (!buf || !chan) {
+		return -EINVAL;
+	}
+
+	br_chan = BR_CHAN(chan);
+
+	LOG_DBG("chan %p buf %p len %zu", chan, buf, net_buf_frags_len(buf));
+
+	if (!chan->conn || chan->conn->state != BT_CONN_CONNECTED) {
+		return -ENOTCONN;
+	}
+
+	if (atomic_test_bit(chan->status, BT_L2CAP_STATUS_SHUTDOWN)) {
+		return -ESHUTDOWN;
+	}
+
+	if (buf->len > br_chan->tx.mtu) {
+		LOG_ERR("attempt to send %u bytes on %u MTU chan", buf->len, br_chan->tx.mtu);
+		return -EMSGSIZE;
+	}
+
+	return bt_l2cap_br_send_cb(br_chan->chan.conn, br_chan->tx.cid, buf, cb, user_data);
+}
+
+int bt_l2cap_br_chan_send(struct bt_l2cap_chan *chan, struct net_buf *buf)
+{
+	return bt_l2cap_br_chan_send_cb(chan, buf, NULL, NULL);
+}
+
+static struct bt_l2cap_br_chan *bt_l2cap_br_lookup_ident(struct bt_conn *conn, uint8_t ident)
+{
+	struct bt_l2cap_chan *chan;
+
+	SYS_SLIST_FOR_EACH_CONTAINER(&conn->channels, chan, node) {
+		if (BR_CHAN(chan)->ident == ident) {
+			return BR_CHAN(chan);
+		}
+	}
+
+	return NULL;
+}
+
+static void l2cap_br_reject_rsp(struct bt_l2cap_br *l2cap, uint8_t ident, struct net_buf *buf)
+{
+	struct bt_conn *conn = l2cap->chan.chan.conn;
+	struct bt_l2cap_br_chan *chan;
+
+	do {
+		chan = bt_l2cap_br_lookup_ident(conn, ident);
+		if (chan != NULL) {
+			int err = -EINVAL;
+
+			/* Only send disconnect req when the L2CAP channel has been connected. */
+			if ((chan->state == BT_L2CAP_CONFIG) ||
+			    (chan->state == BT_L2CAP_CONNECTED)) {
+				err = bt_l2cap_br_chan_disconnect(&chan->chan);
+			}
+
+			if (err) {
+				/* Fail to send disconnect request. Remove channel directly. */
+				bt_l2cap_chan_remove(conn, &chan->chan);
+				bt_l2cap_br_chan_del(&chan->chan);
+			}
+		}
+	} while (chan != NULL);
+}
+
+static void l2cap_br_sig_handle(struct bt_l2cap_br *l2cap, struct bt_l2cap_sig_hdr *hdr,
+				struct net_buf *buf)
+{
+	uint16_t len;
+	struct net_buf_simple_state state;
+
+	len = sys_le16_to_cpu(hdr->len);
+
+	net_buf_simple_save(&buf->b, &state);
+
+	switch (hdr->code) {
+	case BT_L2CAP_INFO_RSP:
+		l2cap_br_info_rsp(l2cap, hdr->ident, buf);
+		break;
+	case BT_L2CAP_INFO_REQ:
+		l2cap_br_info_req(l2cap, hdr->ident, buf);
+		break;
+	case BT_L2CAP_DISCONN_REQ:
+		l2cap_br_disconn_req(l2cap, hdr->ident, buf);
+		break;
+	case BT_L2CAP_CONN_REQ:
+		l2cap_br_conn_req(l2cap, hdr->ident, buf);
+		break;
+	case BT_L2CAP_CONF_RSP:
+		l2cap_br_conf_rsp(l2cap, hdr->ident, len, buf);
+		break;
+	case BT_L2CAP_CONF_REQ:
+		l2cap_br_conf_req(l2cap, hdr->ident, len, buf);
+		break;
+	case BT_L2CAP_DISCONN_RSP:
+		l2cap_br_disconn_rsp(l2cap, hdr->ident, buf);
+		break;
+	case BT_L2CAP_CONN_RSP:
+		l2cap_br_conn_rsp(l2cap, hdr->ident, buf);
+		break;
+	case BT_L2CAP_CMD_REJECT:
+		l2cap_br_reject_rsp(l2cap, hdr->ident, buf);
+		break;
+	default:
+		LOG_WRN("Unknown/Unsupported L2CAP PDU code 0x%02x", hdr->code);
+		l2cap_br_send_reject(l2cap->chan.chan.conn, hdr->ident, BT_L2CAP_REJ_NOT_UNDERSTOOD,
+				     NULL, 0);
+		break;
+	}
+
+	net_buf_simple_restore(&buf->b, &state);
+	(void)net_buf_pull_mem(buf, len);
+}
+
+static int l2cap_br_recv(struct bt_l2cap_chan *chan, struct net_buf *buf)
+{
+	struct bt_l2cap_br *l2cap = CONTAINER_OF(chan, struct bt_l2cap_br, chan.chan);
+	struct bt_l2cap_sig_hdr *hdr;
+	uint16_t len;
+
+	while (buf->len > 0) {
+		if (buf->len < sizeof(*hdr)) {
+			LOG_ERR("Too small L2CAP signaling PDU");
+			return 0;
+		}
+
+		hdr = net_buf_pull_mem(buf, sizeof(*hdr));
+		len = sys_le16_to_cpu(hdr->len);
+
+		LOG_DBG("Signaling code 0x%02x ident %u len %u", hdr->code, hdr->ident, len);
+
+		if (buf->len < len) {
+			LOG_ERR("L2CAP length is short (%u < %u)", buf->len, len);
+			return 0;
+		}
+
+		if (!hdr->ident) {
+			LOG_ERR("Invalid ident value in L2CAP PDU");
+			(void)net_buf_pull_mem(buf, len);
+			continue;
+		}
+
+		l2cap_br_sig_handle(l2cap, hdr, buf);
+	}
+
+	return 0;
+}
+
+static void l2cap_br_conn_pend(struct bt_l2cap_chan *chan, uint8_t status)
+{
+	struct net_buf *buf;
+	struct bt_l2cap_sig_hdr *hdr;
+	struct bt_l2cap_conn_req *req;
+
+	if (BR_CHAN(chan)->state != BT_L2CAP_CONNECTING) {
+		return;
+	}
+
+	LOG_DBG("chan %p status 0x%02x encr 0x%02x", chan, status, chan->conn->encrypt);
+
+	if (status) {
+		/*
+		 * Security procedure status is non-zero so respond with
+		 * security violation only as channel acceptor.
+		 */
+		l2cap_br_conn_req_reply(chan, BT_L2CAP_BR_ERR_SEC_BLOCK);
+
+		/* Release channel allocated to outgoing connection request */
+		if (atomic_test_bit(BR_CHAN(chan)->flags, L2CAP_FLAG_CONN_PENDING)) {
+			l2cap_br_chan_cleanup(chan);
+		}
+
+		return;
+	}
+
+	if (!chan->conn->encrypt) {
+		return;
+	}
+
+	/*
+	 * For incoming connection state send confirming outstanding
+	 * response and initiate configuration request.
+	 */
+	if (l2cap_br_conn_req_reply(chan, BT_L2CAP_BR_SUCCESS) == 0) {
+		bt_l2cap_br_chan_set_state(chan, BT_L2CAP_CONFIG);
+		/*
+		 * Initialize config request since remote needs to know
+		 * local MTU segmentation.
+		 */
+		l2cap_br_conf(chan, true);
+	} else if (atomic_test_and_clear_bit(BR_CHAN(chan)->flags, L2CAP_FLAG_CONN_PENDING)) {
+		buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
+
+		hdr = net_buf_add(buf, sizeof(*hdr));
+		hdr->code = BT_L2CAP_CONN_REQ;
+		hdr->ident = l2cap_br_get_ident();
+		hdr->len = sys_cpu_to_le16(sizeof(*req));
+
+		req = net_buf_add(buf, sizeof(*req));
+		req->psm = sys_cpu_to_le16(BR_CHAN(chan)->psm);
+		req->scid = sys_cpu_to_le16(BR_CHAN(chan)->rx.cid);
+
+		/* Set the ident for the signaling request */
+		BR_CHAN(chan)->ident = hdr->ident;
+
+		l2cap_br_chan_send_req(BR_CHAN(chan), buf, L2CAP_BR_CONN_TIMEOUT);
+	}
+}
+
+void l2cap_br_encrypt_change(struct bt_conn *conn, uint8_t hci_status)
+{
+	struct bt_l2cap_chan *chan;
+
+	SYS_SLIST_FOR_EACH_CONTAINER(&conn->channels, chan, node) {
+		l2cap_br_conn_pend(chan, hci_status);
+
+		if (chan->ops && chan->ops->encrypt_change) {
+			chan->ops->encrypt_change(chan, hci_status);
+		}
+	}
+}
+
+static void check_fixed_channel(struct bt_l2cap_chan *chan)
+{
+	struct bt_l2cap_br_chan *br_chan = BR_CHAN(chan);
+
+	if (br_chan->rx.cid < L2CAP_BR_CID_DYN_START) {
+		connect_fixed_channel(br_chan);
+	}
+}
+
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+static bool bt_l2cap_br_check_tx_seq_out_of_sequence(struct bt_l2cap_br_chan *br_chan,
+						     uint16_t tx_seq)
+{
+	uint16_t outstanding_frames;
+	uint16_t tx_frames;
+
+	outstanding_frames =
+		(br_chan->buffer_seq + br_chan->rx.max_window) - br_chan->expected_tx_seq;
+	tx_frames = (uint16_t)(tx_seq - br_chan->expected_tx_seq);
+
+	if ((br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_ERET) ||
+	    (br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_STREAM)) {
+		if (br_chan->tx.extended_control) {
+			outstanding_frames = outstanding_frames % BT_L2CAP_EXT_CONTROL_SEQ_MAX;
+			tx_frames = tx_frames % BT_L2CAP_EXT_CONTROL_SEQ_MAX;
+		} else {
+			outstanding_frames = outstanding_frames % BT_L2CAP_CONTROL_SEQ_MAX;
+			tx_frames = tx_frames % BT_L2CAP_CONTROL_SEQ_MAX;
+		}
+	} else if ((br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_RET) ||
+		   (br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_FC)) {
+		outstanding_frames = outstanding_frames % BT_L2CAP_CONTROL_SEQ_MAX;
+		tx_frames = tx_frames % BT_L2CAP_CONTROL_SEQ_MAX;
+	}
+
+	if (tx_frames && (tx_frames < outstanding_frames)) {
+		return true;
+	}
+
+	return false;
+}
+
+static bool bt_l2cap_br_check_tx_seq_duplicated(struct bt_l2cap_br_chan *br_chan, uint16_t tx_seq)
+{
+	uint16_t outstanding_frames;
+	uint16_t tx_frames;
+
+	outstanding_frames = (uint16_t)(br_chan->expected_tx_seq - br_chan->buffer_seq - 1);
+	tx_frames = (uint16_t)(tx_seq - br_chan->buffer_seq);
+
+	if ((br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_ERET) ||
+	    (br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_STREAM)) {
+		if (br_chan->tx.extended_control) {
+			outstanding_frames = outstanding_frames % BT_L2CAP_EXT_CONTROL_SEQ_MAX;
+			tx_frames = tx_frames % BT_L2CAP_EXT_CONTROL_SEQ_MAX;
+		} else {
+			outstanding_frames = outstanding_frames % BT_L2CAP_CONTROL_SEQ_MAX;
+			tx_frames = tx_frames % BT_L2CAP_CONTROL_SEQ_MAX;
 		}
+	} else if ((br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_RET) ||
+		   (br_chan->tx.mode == BT_L2CAP_BR_LINK_MODE_FC)) {
+		outstanding_frames = outstanding_frames % BT_L2CAP_CONTROL_SEQ_MAX;
+		tx_frames = tx_frames % BT_L2CAP_CONTROL_SEQ_MAX;
 	}
 
-	hdr->len = sys_cpu_to_le16(buf->len - sizeof(*hdr));
-
-	l2cap_send(conn, BT_L2CAP_CID_BR_SIG, buf);
-
-	if (result != BT_L2CAP_CONF_SUCCESS) {
-		return;
+	if (tx_frames <= outstanding_frames) {
+		return true;
 	}
 
-	atomic_set_bit(BR_CHAN(chan)->flags, L2CAP_FLAG_CONN_RCONF_DONE);
+	return false;
+}
 
-	if (atomic_test_bit(BR_CHAN(chan)->flags, L2CAP_FLAG_CONN_LCONF_DONE) &&
-	    BR_CHAN(chan)->state == BT_L2CAP_CONFIG) {
-		LOG_DBG("scid 0x%04x rx MTU %u dcid 0x%04x tx MTU %u", BR_CHAN(chan)->rx.cid,
-			BR_CHAN(chan)->rx.mtu, BR_CHAN(chan)->tx.cid, BR_CHAN(chan)->tx.mtu);
+static void bt_l2cap_br_update_srej(struct bt_l2cap_br_chan *br_chan, uint16_t req_seq)
+{
+	if (bt_l2cap_br_check_req_seq_valid(br_chan, req_seq)) {
+		struct bt_l2cap_br_window *tx_win, *next;
 
-		bt_l2cap_br_chan_set_state(chan, BT_L2CAP_CONNECTED);
-		if (chan->ops && chan->ops->connected) {
-			chan->ops->connected(chan);
+		SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&br_chan->_pdu_outstanding, tx_win, next, node) {
+			if (tx_win->tx_seq == req_seq) {
+				tx_win->srej = true;
+				break;
+			}
 		}
+	} else {
+		LOG_WRN("Invalid req seq %d received on %p", req_seq, br_chan);
+		/* The L2CAP entity shall close the channel as a consequence
+		 * of an ReqSeq Sequence error.
+		 */
+		bt_l2cap_br_chan_disconnect(&br_chan->chan);
+	}
+	/* Append channel to list if it still has data */
+	if (chan_has_data(br_chan)) {
+		LOG_DBG("chan %p ready", br_chan);
+		raise_data_ready(br_chan);
 	}
 }
 
-static struct bt_l2cap_br_chan *l2cap_br_remove_tx_cid(struct bt_conn *conn,
-						       uint16_t cid)
+static void bt_l2cap_br_update_r(struct bt_l2cap_br_chan *br_chan, uint8_t r)
 {
-	struct bt_l2cap_chan *chan;
-	sys_snode_t *prev = NULL;
+	int err;
 
-	/* Protect fixed channels against accidental removal */
-	if (!L2CAP_BR_CID_IS_DYN(cid)) {
-		return NULL;
+	if (br_chan->rx.mode != BT_L2CAP_BR_LINK_MODE_RET) {
+		LOG_DBG("Only Support retransmission mode");
+		return;
 	}
 
-	SYS_SLIST_FOR_EACH_CONTAINER(&conn->channels, chan, node) {
-		if (BR_CHAN(chan)->tx.cid == cid) {
-			sys_slist_remove(&conn->channels, prev, &chan->node);
-			return BR_CHAN(chan);
+	if (!r) {
+		if (!atomic_test_and_clear_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_R)) {
+			/* R bit without any change */
+			return;
 		}
 
-		prev = &chan->node;
+		/* R bit is changed from 1 -> 0 */
+		atomic_set_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_R_CHANGED);
+		if (bt_l2cap_br_get_outstanding_count(br_chan)) {
+			/* If any unacknowledged I-frames have been sent then RetransmissionTimer
+			 * shall be restarted.
+			 */
+			l2cap_br_start_timer(br_chan, BT_L2CAP_BR_TIMER_RET, true);
+		} else {
+			/* If the RetransmissionTimer is not running and the MonitorTimer is
+			 * not running, then start the MonitorTimer.
+			 */
+			l2cap_br_start_timer(br_chan, BT_L2CAP_BR_TIMER_MONITOR, false);
+		}
+	} else {
+		if (atomic_test_and_set_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_R)) {
+			/* R bit without any change */
+			return;
+		}
+
+		/* R bit is changed from 0 -> 1 */
+		atomic_set_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_R_CHANGED);
+		l2cap_br_start_timer(br_chan, BT_L2CAP_BR_TIMER_MONITOR, false);
 	}
 
-	return NULL;
+	err = l2cap_br_send_s_frame(br_chan, BT_L2CAP_CONTROL_S_RR, K_NO_WAIT);
+	if (err) {
+		LOG_ERR("Fail to send frame %d on %p", err, br_chan);
+		bt_l2cap_chan_disconnect(&br_chan->chan);
+	}
 }
 
-static void l2cap_br_disconn_req(struct bt_l2cap_br *l2cap, uint8_t ident,
-				 struct net_buf *buf)
+static int bt_l2cap_br_update_f(struct bt_l2cap_br_chan *br_chan, uint8_t f)
 {
-	struct bt_conn *conn = l2cap->chan.chan.conn;
-	struct bt_l2cap_br_chan *chan;
-	struct bt_l2cap_disconn_req *req = (void *)buf->data;
-	struct bt_l2cap_disconn_rsp *rsp;
-	struct bt_l2cap_sig_hdr *hdr;
-	uint16_t scid, dcid;
-
-	if (buf->len < sizeof(*req)) {
-		LOG_ERR("Too small disconn req packet size");
-		return;
+	if (br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_STREAM) {
+		/* Ignore f bit if the mode is streaming. */
+		return 0;
 	}
 
-	dcid = sys_le16_to_cpu(req->dcid);
-	scid = sys_le16_to_cpu(req->scid);
+	if (f) {
+		if (!atomic_test_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_P_CHANGED)) {
+			if (!atomic_test_and_clear_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_P)) {
+				LOG_WRN("Unexpected F flag set on %p", br_chan);
+				return -EINVAL;
+			}
 
-	LOG_DBG("scid 0x%04x dcid 0x%04x", dcid, scid);
+			if (bt_l2cap_br_get_outstanding_count(br_chan)) {
+				/* If any unacknowledged I-frames have been sent then
+				 * RetransmissionTimer shall be restarted.
+				 */
+				l2cap_br_start_timer(br_chan, BT_L2CAP_BR_TIMER_RET, true);
+			} else {
+				/* If the RetransmissionTimer is not running and the MonitorTimer
+				 * is not running, then start the MonitorTimer.
+				 */
+				l2cap_br_start_timer(br_chan, BT_L2CAP_BR_TIMER_MONITOR, false);
+			}
+		}
+		/* Append channel to list if it still has data */
+		if (chan_has_data(br_chan)) {
+			LOG_DBG("chan %p ready", br_chan);
+			raise_data_ready(br_chan);
+		}
+	}
 
-	chan = l2cap_br_remove_tx_cid(conn, scid);
-	if (!chan) {
-		struct bt_l2cap_cmd_reject_cid_data data;
+	return 0;
+}
 
-		data.scid = req->scid;
-		data.dcid = req->dcid;
-		l2cap_br_send_reject(conn, ident, BT_L2CAP_REJ_INVALID_CID,
-				     &data, sizeof(data));
+static void bt_l2cap_br_ret_fc_s_recv(struct bt_l2cap_br_chan *br_chan, struct net_buf *buf)
+{
+	uint16_t control;
+	uint32_t ext_control;
+	uint16_t req_seq;
+	uint8_t r = 0;
+	uint8_t s;
+	uint8_t f = 0;
+	uint8_t p = 0;
+	bool remote_busy = false;
+	int err;
+
+	if (br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_STREAM) {
+		/* Ignore S-frame if the mode is streaming. */
 		return;
 	}
 
-	buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
+	if ((br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_ERET) ||
+	    (br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_STREAM)) {
+		if (br_chan->rx.extended_control) {
+			ext_control = net_buf_pull_le32(buf);
+			req_seq = BT_L2CAP_S_FRAME_EXT_CONTROL_GET_REQ_SEQ(ext_control);
+			f = BT_L2CAP_S_FRAME_EXT_CONTROL_GET_F(ext_control);
+			s = BT_L2CAP_S_FRAME_EXT_CONTROL_GET_S(ext_control);
+			p = BT_L2CAP_S_FRAME_EXT_CONTROL_GET_P(ext_control);
+		} else {
+			control = net_buf_pull_le16(buf);
+			req_seq = BT_L2CAP_S_FRAME_ENH_CONTROL_GET_REQ_SEQ(control);
+			f = BT_L2CAP_S_FRAME_ENH_CONTROL_GET_F(control);
+			s = BT_L2CAP_S_FRAME_ENH_CONTROL_GET_S(control);
+			p = BT_L2CAP_S_FRAME_ENH_CONTROL_GET_P(control);
+		}
 
-	hdr = net_buf_add(buf, sizeof(*hdr));
-	hdr->code = BT_L2CAP_DISCONN_RSP;
-	hdr->ident = ident;
-	hdr->len = sys_cpu_to_le16(sizeof(*rsp));
+		err = bt_l2cap_br_update_f(br_chan, f);
+		if (err) {
+			/* Discard the S-frame with invalid f bit */
+			return;
+		}
+	} else {
+		control = net_buf_pull_le16(buf);
+		req_seq = BT_L2CAP_S_FRAME_STD_CONTROL_GET_REQ_SEQ(control);
+		s = BT_L2CAP_S_FRAME_STD_CONTROL_GET_S(control);
+		r = BT_L2CAP_S_FRAME_STD_CONTROL_GET_R(control);
 
-	rsp = net_buf_add(buf, sizeof(*rsp));
-	rsp->dcid = sys_cpu_to_le16(chan->rx.cid);
-	rsp->scid = sys_cpu_to_le16(chan->tx.cid);
+		bt_l2cap_br_update_r(br_chan, r);
+	}
 
-	bt_l2cap_br_chan_del(&chan->chan);
+	switch (s) {
+	case BT_L2CAP_CONTROL_S_RR:
+		if (p) {
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_P);
+		} else {
+			if (!atomic_test_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_REJ)) {
+				atomic_set_bit(br_chan->flags, L2CAP_FLAG_NEW_I_FRAME);
+			} else if (f) {
+				atomic_set_bit(br_chan->flags, L2CAP_FLAG_NEW_I_FRAME);
+			}
+		}
 
-	l2cap_send(conn, BT_L2CAP_CID_BR_SIG, buf);
-}
+		bt_l2cap_br_update_req_seq(br_chan, req_seq, false);
+		remote_busy = atomic_test_bit(br_chan->flags, L2CAP_FLAG_REMOTE_BUSY);
+		atomic_clear_bit(br_chan->flags, L2CAP_FLAG_REMOTE_BUSY);
 
-static void l2cap_br_connected(struct bt_l2cap_chan *chan)
-{
-	LOG_DBG("ch %p cid 0x%04x", BR_CHAN(chan), BR_CHAN(chan)->rx.cid);
-}
+		if (f && !atomic_test_and_clear_bit(br_chan->flags, L2CAP_FLAG_REJ_ACTIONED)) {
+			/* Retransmit I-frames */
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_RET_I_FRAME);
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_REQ_SEQ_UPDATED);
+		}
 
-static void l2cap_br_disconnected(struct bt_l2cap_chan *chan)
-{
-	struct bt_l2cap_br_chan *br_chan = BR_CHAN(chan);
+		if (p) {
+			/* Send IorRRorRNR(F=1) */
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_NEW_I_FRAME);
+			err = l2cap_br_send_s_frame(br_chan, BT_L2CAP_CONTROL_S_RR, K_NO_WAIT);
+			if (err) {
+				bt_l2cap_br_chan_disconnect(&br_chan->chan);
+			}
 
-	LOG_DBG("ch %p cid 0x%04x", br_chan, br_chan->rx.cid);
+			if (remote_busy && bt_l2cap_br_get_outstanding_count(br_chan)) {
+				/* Start-RetransTimer */
+				l2cap_br_start_timer(br_chan, BT_L2CAP_BR_TIMER_RET, true);
+			}
+		}
+		break;
+	case BT_L2CAP_CONTROL_S_REJ:
+		if (br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_FC) {
+			/* Unsupported */
+			LOG_DBG("Ignore REJ frame");
+			break;
+		}
 
-	if (atomic_test_and_clear_bit(br_chan->flags,
-				      L2CAP_FLAG_SIG_INFO_PENDING)) {
-		/* Cancel RTX work on signal channel.
-		 * Disconnected callback is always called from system workqueue
-		 * so this should always succeed.
+		atomic_clear_bit(br_chan->flags, L2CAP_FLAG_REMOTE_BUSY);
+		atomic_set_bit(br_chan->flags, L2CAP_FLAG_NEW_I_FRAME);
+
+		if (!f && atomic_test_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_P)) {
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_REJ_ACTIONED);
+		}
+
+		if (!f && atomic_test_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_REJ)) {
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_RET_I_FRAME);
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_REQ_SEQ_UPDATED);
+		}
+
+		if (f && !atomic_test_and_clear_bit(br_chan->flags, L2CAP_FLAG_REJ_ACTIONED)) {
+			/* Retransmit I-frames */
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_RET_I_FRAME);
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_REQ_SEQ_UPDATED);
+		}
+
+		bt_l2cap_br_update_req_seq(br_chan, req_seq, true);
+		/* Do not change br_chan->next_tx_seq to req_seq. Because the
+		 * TxSeq are saved in tx_win.
 		 */
-		(void)k_work_cancel_delayable(&br_chan->rtx_work);
-	}
-}
+		break;
+	case BT_L2CAP_CONTROL_S_RNR:
+		if (br_chan->rx.mode != BT_L2CAP_BR_LINK_MODE_ERET) {
+			break;
+		}
 
-int bt_l2cap_br_chan_disconnect(struct bt_l2cap_chan *chan)
-{
-	struct bt_conn *conn = chan->conn;
-	struct net_buf *buf;
-	struct bt_l2cap_disconn_req *req;
-	struct bt_l2cap_sig_hdr *hdr;
-	struct bt_l2cap_br_chan *br_chan;
+		LOG_WRN("RNR p=%d f=%d on chan %p", p, f, br_chan);
+		if (p) {
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_P);
+		}
 
-	if (!conn) {
-		return -ENOTCONN;
-	}
+		atomic_set_bit(br_chan->flags, L2CAP_FLAG_REMOTE_BUSY);
+		bt_l2cap_br_update_req_seq(br_chan, req_seq, false);
 
-	br_chan = BR_CHAN(chan);
+		if (!p) {
+			l2cap_br_start_timer(br_chan, BT_L2CAP_BR_TIMER_MONITOR, true);
+		}
 
-	if (br_chan->state == BT_L2CAP_DISCONNECTING) {
-		return -EALREADY;
-	}
+		if (!atomic_test_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_REJ)) {
+			l2cap_br_start_timer(br_chan, BT_L2CAP_BR_TIMER_MONITOR, true);
+			atomic_clear_bit(br_chan->flags, L2CAP_FLAG_RET_I_FRAME);
+		}
 
-	LOG_DBG("chan %p scid 0x%04x dcid 0x%04x", chan, br_chan->rx.cid, br_chan->tx.cid);
+		if (p || atomic_test_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_REJ)) {
+			/* Send RRorRNR (F=1) or Send RR (F=0) */
+			err = l2cap_br_send_s_frame(br_chan, BT_L2CAP_CONTROL_S_RR, K_NO_WAIT);
+			if (err) {
+				bt_l2cap_br_chan_disconnect(&br_chan->chan);
+			}
+		}
+		break;
+	case BT_L2CAP_CONTROL_S_SREJ:
+		if (br_chan->rx.mode != BT_L2CAP_BR_LINK_MODE_ERET) {
+			break;
+		}
 
-	buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
+		bt_l2cap_br_update_srej(br_chan, req_seq);
 
-	hdr = net_buf_add(buf, sizeof(*hdr));
-	hdr->code = BT_L2CAP_DISCONN_REQ;
-	hdr->ident = l2cap_br_get_ident();
-	hdr->len = sys_cpu_to_le16(sizeof(*req));
+		if (p) {
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_RECV_FRAME_P);
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_NEW_I_FRAME);
+		}
 
-	req = net_buf_add(buf, sizeof(*req));
-	req->dcid = sys_cpu_to_le16(br_chan->tx.cid);
-	req->scid = sys_cpu_to_le16(br_chan->rx.cid);
+		atomic_clear_bit(br_chan->flags, L2CAP_FLAG_REMOTE_BUSY);
 
-	l2cap_br_chan_send_req(br_chan, buf, L2CAP_BR_DISCONN_TIMEOUT);
-	bt_l2cap_br_chan_set_state(chan, BT_L2CAP_DISCONNECTING);
+		if (f) {
+			if (atomic_test_and_clear_bit(br_chan->flags, L2CAP_FLAG_SREJ_ACTIONED) &&
+			    (br_chan->srej_save_req_seq == req_seq)) {
+				/* Clear flag L2CAP_FLAG_SREJ_ACTIONED */
+			} else {
+				/* Retransmit-Requested-I-frame */
+				atomic_set_bit(br_chan->flags, L2CAP_FLAG_RET_REQ_I_FRAME);
+			}
+		} else {
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_RET_REQ_I_FRAME);
+			if (atomic_test_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_P)) {
+				atomic_set_bit(br_chan->flags, L2CAP_FLAG_SREJ_ACTIONED);
+				br_chan->srej_save_req_seq = req_seq;
+			}
+		}
 
-	return 0;
+		if (p) {
+			bt_l2cap_br_update_req_seq(br_chan, req_seq, false);
+		}
+		break;
+	}
 }
 
-static void l2cap_br_disconn_rsp(struct bt_l2cap_br *l2cap, uint8_t ident,
-				 struct net_buf *buf)
+#if defined(CONFIG_BT_L2CAP_SEG_RECV)
+static void bt_l2cap_br_recv_seg_direct(struct bt_l2cap_br_chan *br_chan, struct net_buf *seg,
+					uint8_t sar)
 {
-	struct bt_conn *conn = l2cap->chan.chan.conn;
-	struct bt_l2cap_br_chan *chan;
-	struct bt_l2cap_disconn_rsp *rsp = (void *)buf->data;
-	uint16_t dcid, scid;
+	uint16_t seg_offset = 0;
+	uint16_t sdu_remaining = 0;
+
+	switch (sar) {
+	case BT_L2CAP_CONTROL_SAR_UNSEG:
+		__fallthrough;
+	case BT_L2CAP_CONTROL_SAR_START:
+		if (sar == BT_L2CAP_CONTROL_SAR_START) {
+			br_chan->_sdu_len = net_buf_pull_le16(seg);
+		} else {
+			br_chan->_sdu_len = seg->len;
+		}
+		br_chan->_sdu_len_done = 0;
 
-	if (buf->len < sizeof(*rsp)) {
-		LOG_ERR("Too small disconn rsp packet size");
+		if (br_chan->_sdu_len > br_chan->rx.mtu) {
+			LOG_WRN("SDU exceeds MTU");
+			bt_l2cap_chan_disconnect(&br_chan->chan);
+			return;
+		}
+		break;
+	case BT_L2CAP_CONTROL_SAR_END:
+		__fallthrough;
+	case BT_L2CAP_CONTROL_SAR_CONTI:
+		seg_offset = br_chan->_sdu_len_done;
+		sdu_remaining = br_chan->_sdu_len - br_chan->_sdu_len_done;
+
+		br_chan->_sdu_len_done += seg->len;
+
+		if (sar == BT_L2CAP_CONTROL_SAR_END) {
+			if (br_chan->_sdu_len_done < br_chan->_sdu_len) {
+				br_chan->_sdu_len = 0;
+				br_chan->_sdu_len_done = 0;
+				LOG_WRN("Short data packet %u < %u", br_chan->_sdu_len_done,
+					br_chan->_sdu_len);
+				bt_l2cap_chan_disconnect(&br_chan->chan);
+				return;
+			}
+		}
+		break;
+	}
+
+	if (sdu_remaining < seg->len) {
+		br_chan->_sdu_len = 0;
+		br_chan->_sdu_len_done = 0;
+		LOG_WRN("L2CAP RX PDU total exceeds SDU");
+		bt_l2cap_chan_disconnect(&br_chan->chan);
 		return;
 	}
 
-	dcid = sys_le16_to_cpu(rsp->dcid);
-	scid = sys_le16_to_cpu(rsp->scid);
+	/* Tail call. */
+	br_chan->chan.ops->seg_recv(&br_chan->chan, br_chan->_sdu_len, seg_offset, &seg->b);
+}
+#endif /* CONFIG_BT_L2CAP_SEG_RECV */
 
-	LOG_DBG("dcid 0x%04x scid 0x%04x", dcid, scid);
+static struct net_buf *l2cap_br_alloc_frag(k_timeout_t timeout, void *user_data)
+{
+	struct bt_l2cap_br_chan *chan = user_data;
+	struct net_buf *frag = NULL;
 
-	chan = l2cap_br_remove_tx_cid(conn, dcid);
-	if (!chan) {
-		LOG_WRN("No dcid 0x%04x channel found", dcid);
-		return;
+	frag = chan->chan.ops->alloc_buf(&chan->chan);
+	if (!frag) {
+		return NULL;
 	}
 
-	bt_l2cap_br_chan_del(&chan->chan);
+	LOG_DBG("frag %p tailroom %zu", frag, net_buf_tailroom(frag));
+
+	return frag;
 }
 
-int bt_l2cap_br_chan_connect(struct bt_conn *conn, struct bt_l2cap_chan *chan,
-			     uint16_t psm)
+static int bt_l2cap_br_recv_seg(struct bt_l2cap_br_chan *br_chan, struct net_buf *seg, uint8_t sar)
 {
+	uint16_t len;
 	struct net_buf *buf;
-	struct bt_l2cap_sig_hdr *hdr;
-	struct bt_l2cap_conn_req *req;
-	struct bt_l2cap_br_chan *br_chan = BR_CHAN(chan);
 
-	if (!psm) {
-		return -EINVAL;
-	}
+	LOG_DBG("seg on chan %p with len %zu", br_chan, seg->len);
 
-	if (br_chan->psm) {
-		return -EEXIST;
-	}
+	if ((sar == BT_L2CAP_CONTROL_SAR_UNSEG) || (sar == BT_L2CAP_CONTROL_SAR_START)) {
+		if (br_chan->_sdu) {
+			LOG_ERR("Last SDU is not done");
+			net_buf_unref(br_chan->_sdu);
+			br_chan->_sdu = NULL;
+			bt_l2cap_chan_disconnect(&br_chan->chan);
+			return -ESHUTDOWN;
+		}
 
-	/* PSM must be odd and lsb of upper byte must be 0 */
-	if ((psm & 0x0101) != 0x0001) {
-		return -EINVAL;
+		br_chan->_sdu = br_chan->chan.ops->alloc_buf(&br_chan->chan);
+		if (!br_chan->_sdu) {
+			LOG_WRN("Unable to allocate buffer for SDU");
+			return -ENOBUFS;
+		}
+
+		if (sar == BT_L2CAP_CONTROL_SAR_UNSEG) {
+			br_chan->_sdu_len = seg->len;
+		} else {
+			br_chan->_sdu_len = net_buf_pull_le16(seg);
+		}
 	}
 
-	if (br_chan->required_sec_level > BT_SECURITY_L4) {
-		return -EINVAL;
-	} else if (br_chan->required_sec_level == BT_SECURITY_L0 &&
-		   psm != L2CAP_BR_PSM_SDP) {
-		br_chan->required_sec_level = BT_SECURITY_L1;
+	if (!br_chan->_sdu) {
+		LOG_ERR("Insufficient memory for SDU");
+		if ((br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_FC) ||
+		    (br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_STREAM)) {
+			return -ENOBUFS;
+		}
+		bt_l2cap_chan_disconnect(&br_chan->chan);
+		return -ESHUTDOWN;
 	}
 
-	switch (br_chan->state) {
-	case BT_L2CAP_CONNECTED:
-		/* Already connected */
-		return -EISCONN;
-	case BT_L2CAP_DISCONNECTED:
-		/* Can connect */
-		break;
-	case BT_L2CAP_CONFIG:
-	case BT_L2CAP_DISCONNECTING:
-	default:
-		/* Bad context */
-		return -EBUSY;
+	if ((br_chan->_sdu->len + seg->len) > br_chan->_sdu_len) {
+		LOG_ERR("SDU length mismatch");
+		net_buf_unref(br_chan->_sdu);
+		br_chan->_sdu = NULL;
+		bt_l2cap_chan_disconnect(&br_chan->chan);
+		return -ESHUTDOWN;
 	}
 
-	if (!l2cap_br_chan_add(conn, chan, l2cap_br_chan_destroy)) {
-		return -ENOMEM;
+	/* Append received segment to SDU */
+	len = net_buf_append_bytes(br_chan->_sdu, seg->len, seg->data, K_NO_WAIT,
+				   l2cap_br_alloc_frag, br_chan);
+	if (len != seg->len) {
+		LOG_ERR("Unable to store SDU");
+		net_buf_unref(br_chan->_sdu);
+		br_chan->_sdu = NULL;
+		bt_l2cap_chan_disconnect(&br_chan->chan);
+		return -ESHUTDOWN;
 	}
 
-	br_chan->psm = psm;
-	bt_l2cap_br_chan_set_state(chan, BT_L2CAP_CONNECTING);
-	atomic_set_bit(BR_CHAN(chan)->flags, L2CAP_FLAG_CONN_PENDING);
+	LOG_DBG("chan %p len %zu / %zu", br_chan, br_chan->_sdu->len, br_chan->_sdu_len);
 
-	switch (l2cap_br_conn_security(chan, psm)) {
-	case L2CAP_CONN_SECURITY_PENDING:
-		/*
-		 * Authentication was triggered, wait with sending request on
-		 * connection security changed callback context.
-		 */
-		 return 0;
-	case L2CAP_CONN_SECURITY_PASSED:
-		break;
-	case L2CAP_CONN_SECURITY_REJECT:
-	default:
-		l2cap_br_chan_cleanup(chan);
-		return -EIO;
-	}
+	if ((sar == BT_L2CAP_CONTROL_SAR_UNSEG) || (sar == BT_L2CAP_CONTROL_SAR_END)) {
+		if (br_chan->_sdu->len < br_chan->_sdu_len) {
+			LOG_ERR("SDU length mismatch");
+			net_buf_unref(br_chan->_sdu);
+			br_chan->_sdu = NULL;
+			bt_l2cap_chan_disconnect(&br_chan->chan);
+			return -ESHUTDOWN;
+		}
 
-	buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
+		buf = br_chan->_sdu;
+		br_chan->_sdu = NULL;
+		br_chan->_sdu_len = 0;
 
-	hdr = net_buf_add(buf, sizeof(*hdr));
-	hdr->code = BT_L2CAP_CONN_REQ;
-	hdr->ident = l2cap_br_get_ident();
-	hdr->len = sys_cpu_to_le16(sizeof(*req));
+		/* Receiving complete SDU, notify channel and reset SDU buf */
+		int err;
 
-	req = net_buf_add(buf, sizeof(*req));
-	req->psm = sys_cpu_to_le16(psm);
-	req->scid = sys_cpu_to_le16(BR_CHAN(chan)->rx.cid);
+		err = br_chan->chan.ops->recv(&br_chan->chan, buf);
+		if (err < 0) {
+			if (err != -EINPROGRESS) {
+				LOG_ERR("err %d", err);
+				bt_l2cap_chan_disconnect(&br_chan->chan);
+				net_buf_unref(buf);
+				return -ESHUTDOWN;
+			}
+			/* If the buf in progress, it will be freed by upper layer. */
+			return err;
+		}
 
-	l2cap_br_chan_send_req(BR_CHAN(chan), buf, L2CAP_BR_CONN_TIMEOUT);
+		net_buf_unref(buf);
+	}
 
 	return 0;
 }
 
-static void l2cap_br_conn_rsp(struct bt_l2cap_br *l2cap, uint8_t ident,
-			      struct net_buf *buf)
+static void bt_l2cap_br_update_expected_tx_seq(struct bt_l2cap_br_chan *br_chan, uint16_t seq)
 {
-	struct bt_conn *conn = l2cap->chan.chan.conn;
-	struct bt_l2cap_chan *chan;
-	struct bt_l2cap_conn_rsp *rsp = (void *)buf->data;
-	uint16_t dcid, scid, result, status;
-	struct bt_l2cap_br_chan *br_chan;
+	enum l2cap_br_timer_type type;
 
-	if (buf->len < sizeof(*rsp)) {
-		LOG_ERR("Too small L2CAP conn rsp packet size");
+	if (br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_STREAM) {
+		/* Ignore expected_tx_seq if the mode is streaming. */
 		return;
 	}
 
-	dcid = sys_le16_to_cpu(rsp->dcid);
-	scid = sys_le16_to_cpu(rsp->scid);
-	result = sys_le16_to_cpu(rsp->result);
-	status = sys_le16_to_cpu(rsp->status);
-
-	LOG_DBG("dcid 0x%04x scid 0x%04x result %u status %u", dcid, scid, result, status);
+	if ((br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_ERET) ||
+	    (br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_STREAM)) {
+		if (br_chan->rx.extended_control) {
+			seq = seq % BT_L2CAP_EXT_CONTROL_SEQ_MAX;
+		} else {
+			seq = seq % BT_L2CAP_CONTROL_SEQ_MAX;
+		}
+	} else if ((br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_RET) ||
+		   (br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_FC)) {
+		seq = seq % BT_L2CAP_CONTROL_SEQ_MAX;
+	}
 
-	chan = bt_l2cap_br_lookup_rx_cid(conn, scid);
-	if (!chan) {
-		LOG_ERR("No scid 0x%04x channel found", scid);
-		return;
+	/* Restart monitor timer if it is active */
+	if (atomic_test_bit(br_chan->flags, L2CAP_FLAG_RET_TIMER)) {
+		type = BT_L2CAP_BR_TIMER_RET;
+	} else {
+		type = BT_L2CAP_BR_TIMER_MONITOR;
 	}
+	l2cap_br_start_timer(br_chan, type, true);
 
-	br_chan = BR_CHAN(chan);
+	/* Currently, buffer seq is unsupported. */
+	br_chan->buffer_seq = br_chan->expected_tx_seq;
 
-	/* Release RTX work since got the response */
-	k_work_cancel_delayable(&br_chan->rtx_work);
+	br_chan->expected_tx_seq = seq;
 
-	if (br_chan->state != BT_L2CAP_CONNECTING) {
-		LOG_DBG("Invalid channel %p state %s", chan,
-			bt_l2cap_chan_state_str(br_chan->state));
-		return;
-	}
+	if (chan_has_data(br_chan)) {
+		LOG_DBG("chan %p ready", br_chan);
+		raise_data_ready(br_chan);
+	} else {
+		/* Send S-Frame if there is not any pending I-frame */
+		int err;
 
-	switch (result) {
-	case BT_L2CAP_BR_SUCCESS:
-		br_chan->ident = 0U;
-		BR_CHAN(chan)->tx.cid = dcid;
-		l2cap_br_conf(chan);
-		bt_l2cap_br_chan_set_state(chan, BT_L2CAP_CONFIG);
-		atomic_clear_bit(BR_CHAN(chan)->flags, L2CAP_FLAG_CONN_PENDING);
-		break;
-	case BT_L2CAP_BR_PENDING:
-		k_work_reschedule(&br_chan->rtx_work, L2CAP_BR_CONN_TIMEOUT);
-		break;
-	default:
-		l2cap_br_chan_cleanup(chan);
-		break;
+		err = l2cap_br_send_s_frame(br_chan, BT_L2CAP_CONTROL_S_RR, K_NO_WAIT);
+		if (err) {
+			LOG_ERR("Fail to send frame %d on %p", err, br_chan);
+			bt_l2cap_chan_disconnect(&br_chan->chan);
+		}
 	}
 }
 
-int bt_l2cap_br_chan_send_cb(struct bt_l2cap_chan *chan, struct net_buf *buf, bt_conn_tx_cb_t cb,
-			     void *user_data)
+static void bt_l2cap_br_rej_exception(struct bt_l2cap_br_chan *br_chan)
 {
-	struct bt_l2cap_br_chan *br_chan;
+	int err;
 
-	if (!buf || !chan) {
-		return -EINVAL;
+	if (atomic_test_and_set_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_REJ)) {
+		return;
 	}
 
-	br_chan = BR_CHAN(chan);
+	LOG_DBG("Set REJ Exception received flag");
+	atomic_set_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_REJ_CHANGED);
+	err = l2cap_br_send_s_frame(br_chan, BT_L2CAP_CONTROL_S_RR, K_NO_WAIT);
+	if (err) {
+		LOG_ERR("Fail to send frame %d on %p", err, br_chan);
+		bt_l2cap_chan_disconnect(&br_chan->chan);
+	}
+}
 
-	LOG_DBG("chan %p buf %p len %zu", chan, buf, net_buf_frags_len(buf));
+static void bt_l2cap_br_ret_fc_i_recv(struct bt_l2cap_br_chan *br_chan, struct net_buf *buf)
+{
+	uint16_t control;
+	uint32_t ext_control;
+	uint16_t req_seq;
+	uint16_t tx_seq;
+	uint8_t r = 0;
+	uint8_t sar = 0;
+	uint8_t f = 0;
+	bool discard = false;
+	bool expected_tx_seq = false;
+	int err;
+
+	if ((br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_ERET) ||
+	    (br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_STREAM)) {
+		if (br_chan->rx.extended_control) {
+			ext_control = net_buf_pull_le32(buf);
+			req_seq = BT_L2CAP_I_FRAME_EXT_CONTROL_GET_REQ_SEQ(ext_control);
+			f = BT_L2CAP_I_FRAME_EXT_CONTROL_GET_F(ext_control);
+			sar = BT_L2CAP_I_FRAME_EXT_CONTROL_GET_SAR(ext_control);
+			tx_seq = BT_L2CAP_I_FRAME_EXT_CONTROL_GET_TX_SEQ(ext_control);
+		} else {
+			control = net_buf_pull_le16(buf);
+			req_seq = BT_L2CAP_I_FRAME_ENH_CONTROL_GET_REQ_SEQ(control);
+			f = BT_L2CAP_I_FRAME_ENH_CONTROL_GET_F(control);
+			sar = BT_L2CAP_I_FRAME_ENH_CONTROL_GET_SAR(control);
+			tx_seq = BT_L2CAP_I_FRAME_ENH_CONTROL_GET_TX_SEQ(control);
+		}
 
-	if (!chan->conn || chan->conn->state != BT_CONN_CONNECTED) {
-		return -ENOTCONN;
+		err = bt_l2cap_br_update_f(br_chan, f);
+		if (err) {
+			/* Invalid F bit. Ignore the I-frame. */
+			return;
+		}
+	} else {
+		control = net_buf_pull_le16(buf);
+		req_seq = BT_L2CAP_I_FRAME_STD_CONTROL_GET_REQ_SEQ(control);
+		sar = BT_L2CAP_I_FRAME_STD_CONTROL_GET_SAR(control);
+		r = BT_L2CAP_I_FRAME_STD_CONTROL_GET_R(control);
+		tx_seq = BT_L2CAP_I_FRAME_STD_CONTROL_GET_TX_SEQ(control);
+		bt_l2cap_br_update_r(br_chan, r);
 	}
 
-	if (atomic_test_bit(chan->status, BT_L2CAP_STATUS_SHUTDOWN)) {
-		return -ESHUTDOWN;
+	if (br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_STREAM) {
+		bt_l2cap_br_update_expected_tx_seq(br_chan, tx_seq + 1);
+		/* Missing report */
+		goto valid_frame;
 	}
 
-	if (buf->len > br_chan->tx.mtu) {
-		return -EMSGSIZE;
+	/* The first valid I-frame received after an REJ was sent, with a TxSeq of the
+	 * received I-frame equal to ReqSeq of the REJ, shall clear the REJ Exception
+	 * condition.
+	 */
+	if (br_chan->req_seq == tx_seq) {
+		LOG_DBG("Seq %zu equals to req_seq, clears the REJ exception", tx_seq);
+		atomic_clear_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_REJ);
 	}
 
-	return bt_l2cap_br_send_cb(br_chan->chan.conn, br_chan->tx.cid, buf, cb, user_data);
-}
-
-int bt_l2cap_br_chan_send(struct bt_l2cap_chan *chan, struct net_buf *buf)
-{
-	return bt_l2cap_br_chan_send_cb(chan, buf, NULL, NULL);
-}
+	if (br_chan->expected_tx_seq == tx_seq) {
+		/* Valid TX seq received */
+		LOG_DBG("Valid information received seq %zu", tx_seq);
+		expected_tx_seq = true;
+	} else {
+		if (bt_l2cap_br_check_tx_seq_duplicated(br_chan, tx_seq)) {
+			/*
+			 * The Information field shall be discarded since it has already been
+			 * received.
+			 */
+			discard = true;
+			LOG_DBG("Duplicated Information received %zu", tx_seq);
+		} else if (bt_l2cap_br_check_tx_seq_out_of_sequence(br_chan, tx_seq)) {
+			/* The missing I-frame(s) are considered lost and ExpectedTXSeq is
+			 * set equal to TxSeq+1.
+			 */
+			LOG_DBG("Missing I-frame detected %zu", tx_seq);
+			if (br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_FC) {
+				expected_tx_seq = true;
+				/* TODO: Missing report */
+			} else {
+				/* A REJ exception is triggered, and an REJ frame with
+				 * ReqSeq equal to ExpectedTxSeq shall be sent to initiate
+				 * recovery. The received I-frame shall be discarded.
+				 */
+				discard = true;
+				LOG_DBG("Set REJ Exception");
+				bt_l2cap_br_rej_exception(br_chan);
+			}
+		} else {
+			/* An invalid TxSeq value is a value that does not meet either of
+			 * the above conditions and TxSeq is not equal to ExpectedTxSeq.
+			 * An I-frame with an invalid TxSeq is likely to have errors in
+			 * the control field and shall be silently discarded.
+			 */
+			return;
+		}
+	}
 
-static void l2cap_br_sig_handle(struct bt_l2cap_br *l2cap, struct bt_l2cap_sig_hdr *hdr,
-				      struct net_buf *buf)
-{
-	uint16_t len;
-	struct net_buf_simple_state state;
+	err = bt_l2cap_br_update_req_seq(br_chan, req_seq, false);
+	if (err) {
+		return;
+	}
 
-	len = sys_le16_to_cpu(hdr->len);
+	if (discard) {
+		return;
+	}
 
-	net_buf_simple_save(&buf->b, &state);
+	if (br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_ERET) {
+		if (f && !atomic_test_and_clear_bit(br_chan->flags, L2CAP_FLAG_REJ_ACTIONED)) {
+			/* Retransmit I-frames and Send-Pending-I-frames */
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_NEW_I_FRAME);
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_RET_I_FRAME);
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_REQ_SEQ_UPDATED);
+		}
+	}
 
-	switch (hdr->code) {
-	case BT_L2CAP_INFO_RSP:
-		l2cap_br_info_rsp(l2cap, hdr->ident, buf);
-		break;
-	case BT_L2CAP_INFO_REQ:
-		l2cap_br_info_req(l2cap, hdr->ident, buf);
-		break;
-	case BT_L2CAP_DISCONN_REQ:
-		l2cap_br_disconn_req(l2cap, hdr->ident, buf);
-		break;
-	case BT_L2CAP_CONN_REQ:
-		l2cap_br_conn_req(l2cap, hdr->ident, buf);
-		break;
-	case BT_L2CAP_CONF_RSP:
-		l2cap_br_conf_rsp(l2cap, hdr->ident, len, buf);
-		break;
-	case BT_L2CAP_CONF_REQ:
-		l2cap_br_conf_req(l2cap, hdr->ident, len, buf);
-		break;
-	case BT_L2CAP_DISCONN_RSP:
-		l2cap_br_disconn_rsp(l2cap, hdr->ident, buf);
-		break;
-	case BT_L2CAP_CONN_RSP:
-		l2cap_br_conn_rsp(l2cap, hdr->ident, buf);
+valid_frame:
+	switch (sar) {
+	case BT_L2CAP_CONTROL_SAR_UNSEG:
+		__fallthrough;
+	case BT_L2CAP_CONTROL_SAR_START:
+		if (buf->len < 2) {
+			LOG_WRN("Invalid SDU length");
+			bt_l2cap_chan_disconnect(&br_chan->chan);
+			return;
+		}
 		break;
-	default:
-		LOG_WRN("Unknown/Unsupported L2CAP PDU code 0x%02x", hdr->code);
-		l2cap_br_send_reject(l2cap->chan.chan.conn, hdr->ident,
-					BT_L2CAP_REJ_NOT_UNDERSTOOD, NULL, 0);
+	case BT_L2CAP_CONTROL_SAR_END:
+		__fallthrough;
+	case BT_L2CAP_CONTROL_SAR_CONTI:
 		break;
 	}
 
-	net_buf_simple_restore(&buf->b, &state);
-	(void)net_buf_pull_mem(buf, len);
-}
-
-static int l2cap_br_recv(struct bt_l2cap_chan *chan, struct net_buf *buf)
-{
-	struct bt_l2cap_br *l2cap = CONTAINER_OF(chan, struct bt_l2cap_br, chan.chan);
-	struct bt_l2cap_sig_hdr *hdr;
-	uint16_t len;
-
-	while (buf->len > 0) {
-		if (buf->len < sizeof(*hdr)) {
-			LOG_ERR("Too small L2CAP signaling PDU");
-			return 0;
+	/* Redirect to experimental API. */
+	IF_ENABLED(CONFIG_BT_L2CAP_SEG_RECV, ({
+		if (br_chan->chan.ops->seg_recv) {
+			bt_l2cap_br_recv_seg_direct(br_chan, buf, sar);
+			goto done;
 		}
+	}))
 
-		hdr = net_buf_pull_mem(buf, sizeof(*hdr));
-		len = sys_le16_to_cpu(hdr->len);
-
-		LOG_DBG("Signaling code 0x%02x ident %u len %u", hdr->code, hdr->ident, len);
+	if (br_chan->chan.ops->alloc_buf) {
+		err = bt_l2cap_br_recv_seg(br_chan, buf, sar);
+		if (err != -ENOBUFS) {
+			goto done;
+		}
 
-		if (buf->len < len) {
-			LOG_ERR("L2CAP length is short (%u < %u)", buf->len, len);
-			return 0;
+		if ((br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_RET) ||
+		    (br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_ERET)) {
+			expected_tx_seq = false;
 		}
 
-		if (!hdr->ident) {
-			LOG_ERR("Invalid ident value in L2CAP PDU");
-			(void)net_buf_pull_mem(buf, len);
-			continue;
+		if ((br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_ERET) &&
+		    (!atomic_test_and_set_bit(br_chan->flags, L2CAP_FLAG_LOCAL_BUSY))) {
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_LOCAL_BUSY_CHANGED);
+			err = l2cap_br_send_s_frame(br_chan, BT_L2CAP_CONTROL_S_RR, K_NO_WAIT);
+			if (err) {
+				LOG_ERR("Fail to send frame %d on %p", err, br_chan);
+				bt_l2cap_chan_disconnect(&br_chan->chan);
+			}
 		}
+		goto done;
+	}
 
-		l2cap_br_sig_handle(l2cap, hdr, buf);
+	err = br_chan->chan.ops->recv(&br_chan->chan, buf);
+	if (err < 0) {
+		if (err != -EINPROGRESS) {
+			LOG_ERR("err %d", err);
+			bt_l2cap_chan_disconnect(&br_chan->chan);
+		}
+		goto done;
 	}
 
-	return 0;
+done:
+	if (expected_tx_seq) {
+		bt_l2cap_br_update_expected_tx_seq(br_chan, tx_seq + 1);
+	}
 }
 
-static void l2cap_br_conn_pend(struct bt_l2cap_chan *chan, uint8_t status)
+static bool bt_l2cap_br_check_valid_fcs(struct bt_l2cap_br_chan *br_chan, struct net_buf *buf)
 {
-	struct net_buf *buf;
-	struct bt_l2cap_sig_hdr *hdr;
-	struct bt_l2cap_conn_req *req;
+	if (br_chan->rx.mode != BT_L2CAP_BR_LINK_MODE_BASIC) {
+		if (br_chan->rx.fcs == BT_L2CAP_BR_FCS_16BIT) {
+			uint16_t lfcs;
+			uint16_t cfcs;
 
-	if (BR_CHAN(chan)->state != BT_L2CAP_CONNECTING) {
-		return;
+			lfcs = net_buf_remove_le16(buf);
+			cfcs = crc16_reflect(0xa001, 0, &buf->data[0], buf->len);
+
+			if (lfcs != cfcs) {
+				return false;
+			}
+		}
 	}
+	return true;
+}
 
-	LOG_DBG("chan %p status 0x%02x encr 0x%02x", chan, status, chan->conn->encrypt);
+static uint16_t bt_l2cap_br_get_required_len(struct bt_l2cap_br_chan *br_chan)
+{
+	uint16_t len = 0;
 
-	if (status) {
-		/*
-		 * Security procedure status is non-zero so respond with
-		 * security violation only as channel acceptor.
-		 */
-		l2cap_br_conn_req_reply(chan, BT_L2CAP_BR_ERR_SEC_BLOCK);
+	if (br_chan->rx.mode != BT_L2CAP_BR_LINK_MODE_BASIC) {
+		if (br_chan->rx.fcs == BT_L2CAP_BR_FCS_16BIT) {
+			len += BT_L2CAP_FCS_SIZE;
+		}
+	}
 
-		/* Release channel allocated to outgoing connection request */
-		if (atomic_test_bit(BR_CHAN(chan)->flags,
-				    L2CAP_FLAG_CONN_PENDING)) {
-			l2cap_br_chan_cleanup(chan);
+	if (br_chan->rx.mode != BT_L2CAP_BR_LINK_MODE_BASIC) {
+		if (br_chan->rx.extended_control) {
+			len += BT_L2CAP_EXT_CONTROL_SIZE;
+		} else {
+			len += BT_L2CAP_STD_CONTROL_SIZE;
 		}
+	}
 
+	return len;
+}
+
+static void bt_l2cap_br_ret_fc_recv(struct bt_l2cap_br_chan *br_chan, struct net_buf *buf)
+{
+	struct bt_l2cap_hdr *hdr;
+	uint16_t control;
+	uint32_t ext_control;
+	uint8_t type;
+	struct net_buf_simple_state state;
+
+	hdr = (struct bt_l2cap_hdr *)buf->data;
+
+	if (bt_l2cap_br_get_required_len(br_chan) > hdr->len) {
+		LOG_WRN("Invalid Pdu len %u > %u", bt_l2cap_br_get_required_len(br_chan), hdr->len);
+		bt_l2cap_chan_disconnect(&br_chan->chan);
 		return;
 	}
 
-	if (!chan->conn->encrypt) {
+	if (buf->len != (hdr->len + sizeof(*hdr))) {
+		LOG_WRN("Invalid frame %zd != %zd with short packet on%p", buf->len,
+			(hdr->len + sizeof(*hdr)), br_chan);
+		/* Discard the frame */
 		return;
 	}
 
-	/*
-	 * For incoming connection state send confirming outstanding
-	 * response and initiate configuration request.
-	 */
-	if (l2cap_br_conn_req_reply(chan, BT_L2CAP_BR_SUCCESS) == 0) {
-		bt_l2cap_br_chan_set_state(chan, BT_L2CAP_CONFIG);
-		/*
-		 * Initialize config request since remote needs to know
-		 * local MTU segmentation.
-		 */
-		l2cap_br_conf(chan);
-	} else if (atomic_test_and_clear_bit(BR_CHAN(chan)->flags,
-					     L2CAP_FLAG_CONN_PENDING)) {
-		buf = bt_l2cap_create_pdu(&br_sig_pool, 0);
-
-		hdr = net_buf_add(buf, sizeof(*hdr));
-		hdr->code = BT_L2CAP_CONN_REQ;
-		hdr->ident = l2cap_br_get_ident();
-		hdr->len = sys_cpu_to_le16(sizeof(*req));
-
-		req = net_buf_add(buf, sizeof(*req));
-		req->psm = sys_cpu_to_le16(BR_CHAN(chan)->psm);
-		req->scid = sys_cpu_to_le16(BR_CHAN(chan)->rx.cid);
-
-		l2cap_br_chan_send_req(BR_CHAN(chan), buf,
-				       L2CAP_BR_CONN_TIMEOUT);
+	if (!bt_l2cap_br_check_valid_fcs(br_chan, buf)) {
+		LOG_WRN("Invalid frame with incorrect FCS on %p", br_chan);
+		/* Discard the frame */
+		return;
 	}
-}
 
-void l2cap_br_encrypt_change(struct bt_conn *conn, uint8_t hci_status)
-{
-	struct bt_l2cap_chan *chan;
+	/* Pull L2CAP Header from received frame */
+	net_buf_pull_mem(buf, sizeof(*hdr));
 
-	SYS_SLIST_FOR_EACH_CONTAINER(&conn->channels, chan, node) {
-		l2cap_br_conn_pend(chan, hci_status);
+	if (buf->len > br_chan->rx.mps) {
+		LOG_WRN("PDU size > MPS (%u > %u)", buf->len, br_chan->rx.mps);
+		bt_l2cap_chan_disconnect(&br_chan->chan);
+		return;
+	}
 
-		if (chan->ops && chan->ops->encrypt_change) {
-			chan->ops->encrypt_change(chan, hci_status);
+	net_buf_simple_save(&buf->b, &state);
+	if ((br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_ERET) ||
+	    (br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_STREAM)) {
+		if (br_chan->rx.extended_control) {
+			ext_control = net_buf_pull_le32(buf);
+			type = (uint8_t)BT_L2CAP_S_FRAME_EXT_CONTROL_GET_TYPE(ext_control);
+		} else {
+			control = net_buf_pull_le16(buf);
+			type = (uint8_t)BT_L2CAP_S_FRAME_ENH_CONTROL_GET_TYPE(control);
 		}
+	} else {
+		control = net_buf_pull_le16(buf);
+		type = (uint8_t)BT_L2CAP_S_FRAME_STD_CONTROL_GET_TYPE(control);
 	}
-}
-
-static void check_fixed_channel(struct bt_l2cap_chan *chan)
-{
-	struct bt_l2cap_br_chan *br_chan = BR_CHAN(chan);
+	net_buf_simple_restore(&buf->b, &state);
 
-	if (br_chan->rx.cid < L2CAP_BR_CID_DYN_START) {
-		connect_fixed_channel(br_chan);
+	if (type == BT_L2CAP_CONTROL_TYPE_S) {
+		bt_l2cap_br_ret_fc_s_recv(br_chan, buf);
+	} else {
+		bt_l2cap_br_ret_fc_i_recv(br_chan, buf);
 	}
 }
+#endif /* CONFIG_BT_L2CAP_RET_FC */
 
 void bt_l2cap_br_recv(struct bt_conn *conn, struct net_buf *buf)
 {
@@ -2028,10 +5822,60 @@ void bt_l2cap_br_recv(struct bt_conn *conn, struct net_buf *buf)
 	 */
 	check_fixed_channel(chan);
 
-	chan->ops->recv(chan, buf);
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	if (BR_CHAN(chan)->rx.mode != BT_L2CAP_BR_LINK_MODE_BASIC) {
+		/* Add back HDR for FCS check */
+		net_buf_push(buf, sizeof(*hdr));
+		bt_l2cap_br_ret_fc_recv(BR_CHAN(chan), buf);
+	} else {
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+		chan->ops->recv(chan, buf);
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	}
+#endif /* CONFIG_BT_L2CAP_RET_FC */
 	net_buf_unref(buf);
 }
 
+int bt_l2cap_br_chan_recv_complete(struct bt_l2cap_chan *chan)
+{
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	struct bt_l2cap_br_chan *br_chan;
+	int err = 0;
+
+	br_chan = BR_CHAN(chan);
+
+	LOG_DBG("Receiving completed on %p", br_chan);
+
+	if ((br_chan->rx.mode == BT_L2CAP_BR_LINK_MODE_ERET) &&
+	    atomic_test_and_clear_bit(br_chan->flags, L2CAP_FLAG_LOCAL_BUSY)) {
+
+		if (!atomic_test_bit(br_chan->flags, L2CAP_FLAG_LOCAL_BUSY_CHANGED) &&
+		    !atomic_test_and_set_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_P)) {
+			/* State: XMIT
+			 * Local Busy Clears
+			 * Action: send RR(P=1)
+			 */
+			br_chan->retry_count = 1;
+
+			l2cap_br_start_timer(br_chan, BT_L2CAP_BR_TIMER_MONITOR, true);
+
+			atomic_set_bit(br_chan->flags, L2CAP_FLAG_SEND_FRAME_P_CHANGED);
+			err = l2cap_br_send_s_frame(br_chan, BT_L2CAP_CONTROL_S_RR, K_NO_WAIT);
+			if (err) {
+				LOG_ERR("Fail to send frame %d on %p", err, br_chan);
+				bt_l2cap_chan_disconnect(&br_chan->chan);
+			}
+		} else {
+			atomic_clear_bit(br_chan->flags, L2CAP_FLAG_LOCAL_BUSY_CHANGED);
+		}
+	}
+
+	return err;
+#else
+	return -ENOTSUP;
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+}
+
 static int l2cap_br_accept(struct bt_conn *conn, struct bt_l2cap_chan **chan)
 {
 	int i;
diff --git a/subsys/bluetooth/host/classic/l2cap_br_interface.h b/subsys/bluetooth/host/classic/l2cap_br_interface.h
index fd64ed80102..afabe5d1874 100644
--- a/subsys/bluetooth/host/classic/l2cap_br_interface.h
+++ b/subsys/bluetooth/host/classic/l2cap_br_interface.h
@@ -70,3 +70,6 @@ struct bt_l2cap_chan *bt_l2cap_br_lookup_tx_cid(struct bt_conn *conn,
 
 /* Get remote supported fixed channels */
 uint8_t bt_l2cap_br_get_remote_fixed_chan(struct bt_conn *conn);
+
+/* L2CAP data receiving complete. */
+int bt_l2cap_br_chan_recv_complete(struct bt_l2cap_chan *chan);
diff --git a/subsys/bluetooth/host/classic/l2cap_br_internal.h b/subsys/bluetooth/host/classic/l2cap_br_internal.h
index 92a760173ed..90821a3cb22 100644
--- a/subsys/bluetooth/host/classic/l2cap_br_internal.h
+++ b/subsys/bluetooth/host/classic/l2cap_br_internal.h
@@ -134,11 +134,6 @@ struct bt_l2cap_conf_opt_qos {
 	uint32_t delay_variation;
 } __packed;
 
-#define BT_L2CAP_RET_FC_MODE_BASIC   0x00
-#define BT_L2CAP_RET_FC_MODE_RET     0x01
-#define BT_L2CAP_RET_FC_MODE_FC      0x02
-#define BT_L2CAP_RET_FC_MODE_ENH_RET 0x03
-#define BT_L2CAP_RET_FC_MODE_STREAM  0x04
 struct bt_l2cap_conf_opt_ret_fc {
 	uint8_t mode;
 	uint8_t tx_windows_size;
@@ -154,6 +149,19 @@ struct bt_l2cap_conf_opt_fcs {
 	uint8_t type;
 } __packed;
 
+struct bt_l2cap_conf_opt_ext_flow_spec {
+	uint8_t identifier;
+	uint8_t service_type;
+	uint16_t sdu;
+	uint32_t sdu_inter_arrival_time;
+	uint32_t access_latency;
+	uint32_t flush_timeout;
+} __packed;
+
+struct bt_l2cap_conf_opt_ext_win_size {
+	uint16_t max_windows_size;
+} __packed;
+
 #define BT_L2CAP_DISCONN_REQ            0x06
 struct bt_l2cap_disconn_req {
 	uint16_t dcid;
@@ -185,6 +193,188 @@ struct bt_l2cap_info_rsp {
 	uint8_t  data[0];
 } __packed;
 
+/* I Frame Standard Control Field Format definition */
+#define BT_L2CAP_I_FRAME_STD_CONTROL_GET_TYPE(control)    ((control) & 0x01)
+#define BT_L2CAP_I_FRAME_STD_CONTROL_GET_TX_SEQ(control)  (((control) >> 0x01) & 0x3f)
+#define BT_L2CAP_I_FRAME_STD_CONTROL_GET_R(control)       (((control) >> 0x07) & 0x01)
+#define BT_L2CAP_I_FRAME_STD_CONTROL_GET_REQ_SEQ(control) (((control) >> 0x08) & 0x3f)
+#define BT_L2CAP_I_FRAME_STD_CONTROL_GET_SAR(control)     (((control) >> 0x0e) & 0x03)
+
+#define BT_L2CAP_I_FRAME_STD_CONTROL_SET(tx_seq, r, req_seq, sar)                                  \
+	((((tx_seq) & 0x3f) << 0x01) | (((r) & 0x01) << 0x07) | (((req_seq) & 0x3f) << 0x08) |     \
+	 (((sar) & 0x03) << 0x0e))
+
+/* I Frame Enhanced Control Field Format definition */
+#define BT_L2CAP_I_FRAME_ENH_CONTROL_GET_TYPE(control)    ((control) & 0x01)
+#define BT_L2CAP_I_FRAME_ENH_CONTROL_GET_TX_SEQ(control)  (((control) >> 0x01) & 0x3f)
+#define BT_L2CAP_I_FRAME_ENH_CONTROL_GET_F(control)       (((control) >> 0x07) & 0x01)
+#define BT_L2CAP_I_FRAME_ENH_CONTROL_GET_REQ_SEQ(control) (((control) >> 0x08) & 0x3f)
+#define BT_L2CAP_I_FRAME_ENH_CONTROL_GET_SAR(control)     (((control) >> 0x0e) & 0x03)
+
+#define BT_L2CAP_I_FRAME_ENH_CONTROL_SET(tx_seq, f, req_seq, sar)                                  \
+	((((tx_seq) & 0x3f) << 0x01) | (((f) & 0x01) << 0x07) | (((req_seq) & 0x3f) << 0x08) |     \
+	 (((sar) & 0x03) << 0x0e))
+
+/* I Frame Extended Control Field Format definition */
+#define BT_L2CAP_I_FRAME_EXT_CONTROL_GET_TYPE(control)    ((control) & 0x01)
+#define BT_L2CAP_I_FRAME_EXT_CONTROL_GET_F(control)       (((control) >> 0x01) & 0x01)
+#define BT_L2CAP_I_FRAME_EXT_CONTROL_GET_REQ_SEQ(control) (((control) >> 0x02) & 0x3fff)
+#define BT_L2CAP_I_FRAME_EXT_CONTROL_GET_SAR(control)     (((control) >> 0x10) & 0x03)
+#define BT_L2CAP_I_FRAME_EXT_CONTROL_GET_TX_SEQ(control)  (((control) >> 0x12) & 0x3fff)
+
+#define BT_L2CAP_I_FRAME_EXT_CONTROL_SET(f, tx_seq, sar, req_seq)                                  \
+	((((f) & 0x01) << 0x01) | (((req_seq) & 0x3fff) << 0x02) | (((sar) & 0x03) << 0x10) |      \
+	 (((tx_seq) & 0x3fff) << 0x12))
+
+/* S Frame Standard Control Field Format definition */
+#define BT_L2CAP_S_FRAME_STD_CONTROL_GET_TYPE(control)    ((control) & 0x01)
+#define BT_L2CAP_S_FRAME_STD_CONTROL_GET_S(control)       (((control) >> 0x02) & 0x03)
+#define BT_L2CAP_S_FRAME_STD_CONTROL_GET_R(control)       (((control) >> 0x07) & 0x01)
+#define BT_L2CAP_S_FRAME_STD_CONTROL_GET_REQ_SEQ(control) (((control) >> 0x08) & 0x3f)
+
+#define BT_L2CAP_S_FRAME_STD_CONTROL_SET(s, r, req_seq)                                            \
+	(((1) & 0x01) | (((s) & 0x03) << 0x02) | (((r) & 0x01) << 0x07) |                          \
+	 (((req_seq) & 0x3f) << 0x08))
+
+/* S Frame Enhanced Control Field Format definition */
+#define BT_L2CAP_S_FRAME_ENH_CONTROL_GET_TYPE(control)    ((control) & 0x01)
+#define BT_L2CAP_S_FRAME_ENH_CONTROL_GET_S(control)       (((control) >> 0x02) & 0x03)
+#define BT_L2CAP_S_FRAME_ENH_CONTROL_GET_P(control)       (((control) >> 0x04) & 0x01)
+#define BT_L2CAP_S_FRAME_ENH_CONTROL_GET_F(control)       (((control) >> 0x07) & 0x01)
+#define BT_L2CAP_S_FRAME_ENH_CONTROL_GET_REQ_SEQ(control) (((control) >> 0x08) & 0x3f)
+
+#define BT_L2CAP_S_FRAME_ENH_CONTROL_SET(s, p, f, req_seq)                                         \
+	(((1) & 0x01) | (((s) & 0x03) << 0x02) | (((p) & 0x01) << 0x04) | (((f) & 0x01) << 0x07) | \
+	 (((req_seq) & 0x3f) << 0x08))
+
+/* S Frame Extended Control Field Format definition */
+#define BT_L2CAP_S_FRAME_EXT_CONTROL_GET_TYPE(control)    ((control) & 0x01)
+#define BT_L2CAP_S_FRAME_EXT_CONTROL_GET_F(control)       (((control) >> 0x01) & 0x01)
+#define BT_L2CAP_S_FRAME_EXT_CONTROL_GET_REQ_SEQ(control) (((control) >> 0x02) & 0x3fff)
+#define BT_L2CAP_S_FRAME_EXT_CONTROL_GET_S(control)       (((control) >> 0x10) & 0x03)
+#define BT_L2CAP_S_FRAME_EXT_CONTROL_GET_P(control)       (((control) >> 0x12) & 0x01)
+
+#define BT_L2CAP_S_FRAME_EXT_CONTROL_SET(f, req_seq, s, p)                                         \
+	(((1) & 0x01) | (((f) & 0x01) << 0x01) | (((req_seq) & 0x3fff) << 0x02) |                  \
+	 (((s) & 0x03) << 0x10) | (((p) & 0x01) << 0x12))
+
+#define BT_L2CAP_CONTROL_TYPE_I 0x00
+#define BT_L2CAP_CONTROL_TYPE_S 0x01
+
+#define BT_L2CAP_CONTROL_SEQ_MAX     0x40
+#define BT_L2CAP_EXT_CONTROL_SEQ_MAX 0x4000
+
+#define BT_L2CAP_CONTROL_SAR_UNSEG 0x00
+#define BT_L2CAP_CONTROL_SAR_START 0x01
+#define BT_L2CAP_CONTROL_SAR_END   0x02
+#define BT_L2CAP_CONTROL_SAR_CONTI 0x03
+
+#define BT_L2CAP_CONTROL_S_RR   0x00
+#define BT_L2CAP_CONTROL_S_REJ  0x01
+#define BT_L2CAP_CONTROL_S_RNR  0x02
+#define BT_L2CAP_CONTROL_S_SREJ 0x03
+
+#define BT_L2CAP_RT_FC_SDU_LEN_SIZE 2
+
+#define BT_L2CAP_STD_CONTROL_SIZE 2
+#define BT_L2CAP_ENH_CONTROL_SIZE 2
+#define BT_L2CAP_EXT_CONTROL_SIZE 4
+
+#define BT_L2CAP_FCS_SIZE 2
+
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+/**
+ *
+ *  @brief Helper to calculate L2CAP SDU header size.
+ *         Useful for creating buffer pools.
+ *
+ *  @param mtu Required BT_L2CAP_*_SDU.
+ *
+ *  @return Header size of the L2CAP channel.
+ */
+static inline size_t bt_l2cap_br_get_ret_fc_hdr_size(struct bt_l2cap_br_chan *chan)
+{
+	if (chan->tx.mode != BT_L2CAP_BR_LINK_MODE_BASIC) {
+		if (chan->tx.extended_control) {
+			return BT_L2CAP_EXT_CONTROL_SIZE + BT_L2CAP_RT_FC_SDU_LEN_SIZE;
+		} else {
+			return BT_L2CAP_STD_CONTROL_SIZE + BT_L2CAP_RT_FC_SDU_LEN_SIZE;
+		}
+	}
+
+	return 0;
+}
+
+static inline size_t bt_l2cap_br_get_ret_fc_tail_size(struct bt_l2cap_br_chan *chan)
+{
+	if (chan->tx.mode != BT_L2CAP_BR_LINK_MODE_BASIC) {
+		if (chan->tx.fcs == BT_L2CAP_BR_FCS_16BIT) {
+			return BT_L2CAP_FCS_SIZE;
+		}
+	}
+
+	return 0;
+}
+
+/**
+ *
+ *  @brief Helper to calculate L2CAP SDU header size.
+ *         Useful for creating buffer pools.
+ *
+ *  @param chan the BR channel object point to `struct bt_l2cap_br_chan`.
+ *
+ *  @return Header size of the L2CAP channel.
+ */
+#define BT_L2CAP_RT_FC_SDU_HDR_SIZE(chan) bt_l2cap_br_get_ret_fc_hdr_size(chan)
+
+/**
+ *
+ *  @brief Helper to calculate L2CAP SDU tail size.
+ *         Useful for creating buffer pools.
+ *
+ *  @param chan the BR channel object point to `struct bt_l2cap_br_chan`.
+ *
+ *  @return Header size of the L2CAP channel.
+ */
+#define BT_L2CAP_RT_FC_SDU_TAIL_SIZE(chan) bt_l2cap_br_get_ret_fc_tail_size(chan)
+
+/**
+ *
+ *  @brief Helper to calculate needed buffer size for L2CAP SDUs.
+ *         Useful for creating buffer pools.
+ *
+ *  @param chan the BR channel object point to `struct bt_l2cap_br_chan`.
+ *  @param mtu Required BT_L2CAP_*_SDU.
+ *
+ *  @return Needed buffer size to match the requested L2CAP SDU MTU.
+ */
+#define BT_L2CAP_RT_FC_SDU_BUF_SIZE(chan, mtu)                                                     \
+	(BT_L2CAP_BUF_SIZE(BT_L2CAP_RT_FC_SDU_HDR_SIZE((chan)) + (mtu) +                           \
+			   BT_L2CAP_RT_FC_SDU_TAIL_SIZE((chan))))
+
+/**
+ *
+ *  @brief Helper to calculate needed buffer size for L2CAP SDUs.
+ *         Useful for creating buffer pools.
+ *
+ *  @param mtu Required BT_L2CAP_*_SDU.
+ *
+ *  @return Needed buffer size to match the requested L2CAP SDU MTU.
+ */
+#define BT_L2CAP_RT_FC_MAX_SDU_BUF_SIZE(mtu)                                                       \
+	BT_L2CAP_BUF_SIZE((mtu) + BT_L2CAP_EXT_CONTROL_SIZE + BT_L2CAP_RT_FC_SDU_LEN_SIZE +        \
+			  BT_L2CAP_FCS_SIZE)
+
+/**
+ *  @brief Headroom needed for outgoing L2CAP PDUs if channel in one of
+ *  following mode, including retransmission, flow control, enhance
+ *  retransmission, and streaming.
+ *
+ *  @param chan the BR channel object point to `struct bt_l2cap_br_chan`.
+ */
+#define BT_L2CAP_RET_FC_SDU_CHAN_SEND_RESERVE(chan) (BT_L2CAP_RT_FC_SDU_HDR_SIZE(chan))
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+
 #define BR_CHAN(_ch) CONTAINER_OF(_ch, struct bt_l2cap_br_chan, chan)
 
 /* Add channel to the connection */
@@ -217,3 +407,5 @@ struct net_buf *bt_l2cap_create_pdu_timeout(struct net_buf_pool *pool,
 
 #define bt_l2cap_create_pdu(_pool, _reserve) \
 	bt_l2cap_create_pdu_timeout(_pool, _reserve, K_FOREVER)
+
+bt_security_t bt_l2cap_br_get_max_sec_level(void);
diff --git a/subsys/bluetooth/host/classic/rfcomm.c b/subsys/bluetooth/host/classic/rfcomm.c
index 45e2a50b7e1..a360d3f6493 100644
--- a/subsys/bluetooth/host/classic/rfcomm.c
+++ b/subsys/bluetooth/host/classic/rfcomm.c
@@ -199,15 +199,32 @@ rfcomm_sessions_lookup_bt_conn(struct bt_conn *conn)
 
 int bt_rfcomm_server_register(struct bt_rfcomm_server *server)
 {
-	if (server->channel < RFCOMM_CHANNEL_START ||
-	    server->channel > RFCOMM_CHANNEL_END || !server->accept) {
+	if (server->channel > RFCOMM_CHANNEL_END || !server->accept) {
 		return -EINVAL;
 	}
 
-	/* Check if given channel is already in use */
-	if (rfcomm_server_lookup_channel(server->channel)) {
-		LOG_DBG("Channel already registered");
-		return -EADDRINUSE;
+	if (!server->channel) {
+		uint8_t chan = (uint8_t)BT_RFCOMM_CHAN_DYNAMIC_START;
+
+		for (; chan <= RFCOMM_CHANNEL_END; chan++) {
+			/* Check if given channel is already in use */
+			if (!rfcomm_server_lookup_channel(chan)) {
+				server->channel = chan;
+				LOG_DBG("Allocated channel 0x%02x for new server", chan);
+				break;
+			}
+		}
+
+		if (!server->channel) {
+			LOG_WRN("No free dynamic rfcomm channels available");
+			return -EADDRNOTAVAIL;
+		}
+	} else {
+		/* Check if given channel is already in use */
+		if (rfcomm_server_lookup_channel(server->channel)) {
+			LOG_WRN("Channel already registered");
+			return -EADDRINUSE;
+		}
 	}
 
 	LOG_DBG("Channel 0x%02x", server->channel);
@@ -478,7 +495,7 @@ static struct bt_rfcomm_dlc *rfcomm_dlc_accept(struct bt_rfcomm_session *session
 		return NULL;
 	}
 
-	if (server->accept(session->br_chan.chan.conn, &dlc) < 0) {
+	if (server->accept(session->br_chan.chan.conn, server, &dlc) < 0) {
 		LOG_DBG("Incoming connection rejected");
 		return NULL;
 	}
@@ -1528,7 +1545,7 @@ static int rfcomm_recv(struct bt_l2cap_chan *chan, struct net_buf *buf)
 	}
 
 	if (buf->len < (hdr_len + msg_len + sizeof(fcs))) {
-		LOG_ERR("Too small RFCOMM information (%d < %d)", buf->len,
+		LOG_ERR("Too small RFCOMM information (%u < %zu)", buf->len,
 			hdr_len + msg_len + sizeof(fcs));
 		return 0;
 	}
diff --git a/subsys/bluetooth/host/classic/rfcomm_internal.h b/subsys/bluetooth/host/classic/rfcomm_internal.h
index 07ff13bd0e9..afc7b366d15 100644
--- a/subsys/bluetooth/host/classic/rfcomm_internal.h
+++ b/subsys/bluetooth/host/classic/rfcomm_internal.h
@@ -133,15 +133,6 @@ struct bt_rfcomm_rpn {
 #define BT_RFCOMM_CHECK_MTU(mtu) (!!((mtu) >= BT_RFCOMM_SIG_MIN_MTU && \
 				     (mtu) <= BT_RFCOMM_SIG_MAX_MTU))
 
-/* Helper to calculate needed outgoing buffer size.
- * Length in rfcomm header can be two bytes depending on user data length.
- * One byte in the tail should be reserved for FCS.
- */
-#define BT_RFCOMM_BUF_SIZE(mtu) (BT_BUF_RESERVE + \
-				 BT_HCI_ACL_HDR_SIZE + BT_L2CAP_HDR_SIZE + \
-				 sizeof(struct bt_rfcomm_hdr) + 1 + (mtu) + \
-				 BT_RFCOMM_FCS_SIZE)
-
 #define BT_RFCOMM_GET_DLCI(addr)                  (((addr) & 0xfc) >> 2)
 #define BT_RFCOMM_GET_FRAME_TYPE(ctrl)            ((ctrl) & 0xef)
 #define BT_RFCOMM_GET_MSG_TYPE(type)              (((type) & 0xfc) >> 2)
@@ -192,7 +183,6 @@ struct bt_rfcomm_rpn {
 
 /* Length can be 2 bytes depending on data size */
 #define BT_RFCOMM_HDR_SIZE  (sizeof(struct bt_rfcomm_hdr) + 1)
-#define BT_RFCOMM_FCS_SIZE  1
 
 #define BT_RFCOMM_FCS_LEN_UIH      2
 #define BT_RFCOMM_FCS_LEN_NON_UIH  3
diff --git a/subsys/bluetooth/host/classic/sco.c b/subsys/bluetooth/host/classic/sco.c
index 51433c9090b..9157caaf941 100644
--- a/subsys/bluetooth/host/classic/sco.c
+++ b/subsys/bluetooth/host/classic/sco.c
@@ -120,11 +120,11 @@ void bt_sco_disconnected(struct bt_conn *sco)
 
 	bt_sco_cleanup_acl(sco);
 
-	chan->sco = NULL;
-
 	if (chan->ops && chan->ops->disconnected) {
 		chan->ops->disconnected(chan, sco->err);
 	}
+
+	chan->sco = NULL;
 }
 
 static uint8_t sco_server_check_security(struct bt_conn *conn)
diff --git a/subsys/bluetooth/host/classic/sdp.c b/subsys/bluetooth/host/classic/sdp.c
index 124ca2e3a4a..5c10f8b521a 100644
--- a/subsys/bluetooth/host/classic/sdp.c
+++ b/subsys/bluetooth/host/classic/sdp.c
@@ -92,6 +92,10 @@ struct bt_sdp_client {
 	struct bt_sdp_pdu_cstate             cstate;
 	/* buffer for collecting record data */
 	struct net_buf                      *rec_buf;
+	/* The total length of response */
+	uint32_t                             total_len;
+	/* Received data length */
+	uint32_t                             recv_len;
 };
 
 static struct bt_sdp_client bt_sdp_client_pool[CONFIG_BT_MAX_CONN];
@@ -515,6 +519,8 @@ static uint16_t find_services(struct net_buf *buf,
 			return BT_SDP_INVALID_SYNTAX;
 		}
 
+		uuid_list_size -= data_elem.total_size;
+
 		if (data_elem.data_size == 2U) {
 			u.uuid.type = BT_UUID_TYPE_16;
 			u.u16.val = net_buf_pull_be16(buf);
@@ -530,10 +536,9 @@ static uint16_t find_services(struct net_buf *buf,
 			LOG_WRN("Invalid UUID len %u in service search pattern",
 				data_elem.data_size);
 			net_buf_pull(buf, data_elem.data_size);
+			continue;
 		}
 
-		uuid_list_size -= data_elem.total_size;
-
 		/* Go over the list of services, and look for a service which
 		 * doesn't have this UUID
 		 */
@@ -1003,7 +1008,7 @@ static uint16_t get_att_search_list(struct net_buf *buf, uint32_t *filter,
 
 	while (size) {
 		if (*num_filters >= max_filters) {
-			LOG_WRN("Exceeded maximum array length %u of %p", max_filters, filter);
+			LOG_WRN("Exceeded maximum array length %zu of %p", max_filters, filter);
 			return 0;
 		}
 
@@ -1654,55 +1659,7 @@ static int sdp_client_ssa_search(struct bt_sdp_client *session,
 			   session->tid);
 }
 
-static void sdp_client_params_iterator(struct bt_sdp_client *session);
-
-static int sdp_client_discover(struct bt_sdp_client *session)
-{
-	const struct bt_sdp_discover_params *param;
-	int err;
-
-	/*
-	 * Select proper user params, if session->param is invalid it means
-	 * getting new UUID from top of to be resolved params list. Otherwise
-	 * the context is in a middle of partial SDP PDU responses and cached
-	 * value from context can be used.
-	 */
-	if (!session->param) {
-		param = GET_PARAM(sys_slist_peek_head(&session->reqs));
-	} else {
-		param = session->param;
-	}
-
-	if (!param) {
-		struct bt_l2cap_chan *chan = &session->chan.chan;
-
-		LOG_WRN("No more request, disconnect channel");
-		/* No UUID items, disconnect channel */
-		return bt_l2cap_chan_disconnect(chan);
-	}
-
-	switch (param->type) {
-	case BT_SDP_DISCOVER_SERVICE_SEARCH:
-		err = sdp_client_ss_search(session, param);
-		break;
-	case BT_SDP_DISCOVER_SERVICE_ATTR:
-		err = sdp_client_sa_search(session, param);
-		break;
-	case BT_SDP_DISCOVER_SERVICE_SEARCH_ATTR:
-		err = sdp_client_ssa_search(session, param);
-		break;
-	default:
-		err = -EINVAL;
-		break;
-	}
-
-	if (err) {
-		/* Get next UUID and start resolving it */
-		sdp_client_params_iterator(session);
-	}
-
-	return 0;
-}
+static int sdp_client_discover(struct bt_sdp_client *session);
 
 static void sdp_client_params_iterator(struct bt_sdp_client *session)
 {
@@ -1722,6 +1679,10 @@ static void sdp_client_params_iterator(struct bt_sdp_client *session)
 		session->param = NULL;
 		/* Reset continuation state in current context */
 		(void)memset(&session->cstate, 0, sizeof(session->cstate));
+		/* Clear total length */
+		session->total_len = 0;
+		/* Clear received length */
+		session->recv_len = 0;
 
 		/* Check if there's valid next UUID */
 		if (!sys_slist_is_empty(&session->reqs)) {
@@ -1857,7 +1818,7 @@ static void sdp_client_notify_result(struct bt_sdp_client *session,
 	uint16_t rec_len;
 	uint8_t user_ret;
 
-	if (state == UUID_NOT_RESOLVED) {
+	if ((state == UUID_NOT_RESOLVED) || (session->rec_buf->len == 0U)) {
 		result.resp_buf = NULL;
 		result.next_record_hint = false;
 		session->param->func(conn, &result, session->param);
@@ -1901,6 +1862,56 @@ static void sdp_client_notify_result(struct bt_sdp_client *session,
 	}
 }
 
+static int sdp_client_discover(struct bt_sdp_client *session)
+{
+	const struct bt_sdp_discover_params *param;
+	int err;
+
+	/*
+	 * Select proper user params, if session->param is invalid it means
+	 * getting new UUID from top of to be resolved params list. Otherwise
+	 * the context is in a middle of partial SDP PDU responses and cached
+	 * value from context can be used.
+	 */
+	if (!session->param) {
+		param = GET_PARAM(sys_slist_peek_head(&session->reqs));
+	} else {
+		param = session->param;
+	}
+
+	if (!param) {
+		struct bt_l2cap_chan *chan = &session->chan.chan;
+
+		LOG_WRN("No more request, disconnect channel");
+		/* No UUID items, disconnect channel */
+		return bt_l2cap_chan_disconnect(chan);
+	}
+
+	switch (param->type) {
+	case BT_SDP_DISCOVER_SERVICE_SEARCH:
+		err = sdp_client_ss_search(session, param);
+		break;
+	case BT_SDP_DISCOVER_SERVICE_ATTR:
+		err = sdp_client_sa_search(session, param);
+		break;
+	case BT_SDP_DISCOVER_SERVICE_SEARCH_ATTR:
+		err = sdp_client_ssa_search(session, param);
+		break;
+	default:
+		err = -EINVAL;
+		break;
+	}
+
+	if (err) {
+		/* Notify the result */
+		sdp_client_notify_result(session, UUID_NOT_RESOLVED);
+		/* Get next UUID and start resolving it */
+		sdp_client_params_iterator(session);
+	}
+
+	return 0;
+}
+
 static int sdp_client_receive_ss(struct bt_sdp_client *session, struct net_buf *buf)
 {
 	struct bt_sdp_pdu_cstate *cstate;
@@ -1912,7 +1923,7 @@ static int sdp_client_receive_ss(struct bt_sdp_client *session, struct net_buf *
 	/* Check the buffer len for the total_count field */
 	if (buf->len < sizeof(total_count)) {
 		LOG_ERR("Invalid frame payload length");
-		return 0;
+		return -EINVAL;
 	}
 
 	/* Get total service record count. */
@@ -1921,7 +1932,7 @@ static int sdp_client_receive_ss(struct bt_sdp_client *session, struct net_buf *
 	/* Check the buffer len for the current_count field */
 	if (buf->len < sizeof(current_count)) {
 		LOG_ERR("Invalid frame payload length");
-		return 0;
+		return -EINVAL;
 	}
 
 	/* Get current service record count. */
@@ -1929,19 +1940,19 @@ static int sdp_client_receive_ss(struct bt_sdp_client *session, struct net_buf *
 	/* Check valid of current service record count */
 	if (current_count > total_count) {
 		LOG_ERR("Invalid current service record count");
-		return 0;
+		return -EINVAL;
 	}
 
 	received_count = session->rec_buf->len / SDP_RECORD_HANDLE_SIZE;
 	if ((received_count + current_count) > total_count) {
 		LOG_ERR("Excess data received");
-		return 0;
+		return -EINVAL;
 	}
 
 	record_len = current_count * SDP_RECORD_HANDLE_SIZE;
 	if (record_len >= buf->len) {
 		LOG_ERR("Invalid packet");
-		return 0;
+		return -EINVAL;
 	}
 
 	/* Get PDU continuation state */
@@ -1949,12 +1960,12 @@ static int sdp_client_receive_ss(struct bt_sdp_client *session, struct net_buf *
 
 	if (cstate->length > BT_SDP_MAX_PDU_CSTATE_LEN) {
 		LOG_ERR("Invalid SDP PDU Continuation State length %u", cstate->length);
-		return 0;
+		return -EINVAL;
 	}
 
 	if ((record_len + SDP_CONT_STATE_LEN_SIZE + cstate->length) > buf->len) {
 		LOG_ERR("Invalid payload length");
-		return 0;
+		return -EINVAL;
 	}
 
 	/*
@@ -1963,16 +1974,13 @@ static int sdp_client_receive_ss(struct bt_sdp_client *session, struct net_buf *
 	 * valid and this is the first response frame as well.
 	 */
 	if (!current_count && cstate->length == 0U && session->cstate.length == 0U) {
-		LOG_DBG("Service record handle 0x%x not found", session->param->handle);
-		/* Call user UUID handler */
-		sdp_client_notify_result(session, UUID_NOT_RESOLVED);
-		net_buf_pull(buf, sizeof(cstate->length));
-		goto iterate;
+		LOG_WRN("Service record handle 0x%x not found", session->param->handle);
+		return -EINVAL;
 	}
 
 	if (record_len > net_buf_tailroom(session->rec_buf)) {
 		LOG_WRN("Not enough room for getting records data");
-		goto iterate;
+		return -EINVAL;
 	}
 
 	net_buf_add_mem(session->rec_buf, buf->data, record_len);
@@ -1985,15 +1993,20 @@ static int sdp_client_receive_ss(struct bt_sdp_client *session, struct net_buf *
 
 		net_buf_pull(buf, cstate->length + sizeof(cstate->length));
 
-		/* Request for next portion of attributes data */
-		return sdp_client_discover(session);
+		/*
+		 * Request for next portion of attributes data.
+		 * All failure case are handled internally in the function.
+		 * Ignore the return value.
+		 */
+		(void)sdp_client_discover(session);
+
+		return 0;
 	}
 
 	net_buf_pull(buf, sizeof(cstate->length));
 
 	LOG_DBG("UUID 0x%s resolved", bt_uuid_str(session->param->uuid));
 	sdp_client_notify_result(session, UUID_RESOLVED);
-iterate:
 	/* Get next UUID and start resolving it */
 	sdp_client_params_iterator(session);
 
@@ -2009,7 +2022,7 @@ static int sdp_client_receive_ssa_sa(struct bt_sdp_client *session, struct net_b
 	/* Check the buffer len for the frame_len field */
 	if (buf->len < sizeof(frame_len)) {
 		LOG_ERR("Invalid frame payload length");
-		return 0;
+		return -EINVAL;
 	}
 
 	/* Get number of attributes in this frame. */
@@ -2017,12 +2030,12 @@ static int sdp_client_receive_ssa_sa(struct bt_sdp_client *session, struct net_b
 	/* Check valid buf len for attribute list and cont state */
 	if (buf->len < frame_len + SDP_CONT_STATE_LEN_SIZE) {
 		LOG_ERR("Invalid frame payload length");
-		return 0;
+		return -EINVAL;
 	}
 	/* Check valid range of attributes length */
 	if (frame_len < 2) {
 		LOG_ERR("Invalid attributes data length");
-		return 0;
+		return -EINVAL;
 	}
 
 	/* Get PDU continuation state */
@@ -2030,12 +2043,12 @@ static int sdp_client_receive_ssa_sa(struct bt_sdp_client *session, struct net_b
 
 	if (cstate->length > BT_SDP_MAX_PDU_CSTATE_LEN) {
 		LOG_ERR("Invalid SDP PDU Continuation State length %u", cstate->length);
-		return 0;
+		return -EINVAL;
 	}
 
 	if ((frame_len + SDP_CONT_STATE_LEN_SIZE + cstate->length) > buf->len) {
 		LOG_ERR("Invalid frame payload length");
-		return 0;
+		return -EINVAL;
 	}
 
 	/*
@@ -2044,19 +2057,32 @@ static int sdp_client_receive_ssa_sa(struct bt_sdp_client *session, struct net_b
 	 * valid and this is the first response frame as well.
 	 */
 	if (frame_len == 2U && cstate->length == 0U && session->cstate.length == 0U) {
-		LOG_DBG("Record for UUID 0x%s not found", bt_uuid_str(session->param->uuid));
-		/* Call user UUID handler */
-		sdp_client_notify_result(session, UUID_NOT_RESOLVED);
-		net_buf_pull(buf, frame_len + sizeof(cstate->length));
-		goto iterate;
+		LOG_WRN("Record for UUID 0x%s not found", bt_uuid_str(session->param->uuid));
+		return -EINVAL;
 	}
 
 	/* Get total value of all attributes to be collected */
 	frame_len -= sdp_client_get_total(session, buf, &total);
+	/*
+	 * If total is not 0, there are two valid cases,
+	 * Case 1, the continuation state length is 0, the frame_len should equal total,
+	 * Case 2, the continuation state length is not 0, it means there are more data will be
+	 * received. So the frame_len is less than total.
+	 */
+	if (total && (frame_len > total)) {
+		LOG_ERR("Invalid attribute lists");
+		return -EINVAL;
+	}
+
+	if (session->cstate.length == 0U) {
+		session->total_len = total;
+	}
+
+	session->recv_len += frame_len;
 
-	if (total > net_buf_tailroom(session->rec_buf)) {
+	if (frame_len > net_buf_tailroom(session->rec_buf)) {
 		LOG_WRN("Not enough room for getting records data");
-		goto iterate;
+		return -EINVAL;
 	}
 
 	net_buf_add_mem(session->rec_buf, buf->data, frame_len);
@@ -2069,15 +2095,26 @@ static int sdp_client_receive_ssa_sa(struct bt_sdp_client *session, struct net_b
 
 		net_buf_pull(buf, cstate->length + sizeof(cstate->length));
 
-		/* Request for next portion of attributes data */
-		return sdp_client_discover(session);
+		/*
+		 * Request for next portion of attributes data.
+		 * All failure case are handled internally in the function.
+		 * Ignore the return value.
+		 */
+		(void)sdp_client_discover(session);
+
+		return 0;
+	}
+
+	if (session->total_len && (session->recv_len != session->total_len)) {
+		LOG_WRN("The received len %d is mismatched with total len %d", session->recv_len,
+			session->total_len);
+		return -EINVAL;
 	}
 
 	net_buf_pull(buf, sizeof(cstate->length));
 
 	LOG_DBG("UUID 0x%s resolved", bt_uuid_str(session->param->uuid));
 	sdp_client_notify_result(session, UUID_RESOLVED);
-iterate:
 	/* Get next UUID and start resolving it */
 	sdp_client_params_iterator(session);
 
@@ -2089,6 +2126,7 @@ static int sdp_client_receive(struct bt_l2cap_chan *chan, struct net_buf *buf)
 	struct bt_sdp_client *session = SDP_CLIENT_CHAN(chan);
 	struct bt_sdp_hdr *hdr;
 	uint16_t len, tid;
+	int err = -EINVAL;
 
 	LOG_DBG("session %p buf %p", session, buf);
 
@@ -2113,23 +2151,32 @@ static int sdp_client_receive(struct bt_l2cap_chan *chan, struct net_buf *buf)
 		return 0;
 	}
 
+	if (session->param == NULL) {
+		LOG_WRN("No request in progress");
+		return 0;
+	}
+
 	switch (hdr->op_code) {
 	case BT_SDP_SVC_SEARCH_RSP:
-		return sdp_client_receive_ss(session, buf);
+		err = sdp_client_receive_ss(session, buf);
+		break;
 	case BT_SDP_SVC_ATTR_RSP:
-		__fallthrough;
 	case BT_SDP_SVC_SEARCH_ATTR_RSP:
-		return sdp_client_receive_ssa_sa(session, buf);
+		err = sdp_client_receive_ssa_sa(session, buf);
+		break;
 	case BT_SDP_ERROR_RSP:
 		LOG_INF("Invalid SDP request");
-		sdp_client_notify_result(session, UUID_NOT_RESOLVED);
-		sdp_client_params_iterator(session);
-		return 0;
+		break;
 	default:
 		LOG_DBG("PDU 0x%0x response not handled", hdr->op_code);
 		break;
 	}
 
+	if (err < 0) {
+		sdp_client_notify_result(session, UUID_NOT_RESOLVED);
+		sdp_client_params_iterator(session);
+	}
+
 	return 0;
 }
 
diff --git a/subsys/bluetooth/host/classic/shell/CMakeLists.txt b/subsys/bluetooth/host/classic/shell/CMakeLists.txt
index dbf42a44cb1..2732cb2eb6d 100644
--- a/subsys/bluetooth/host/classic/shell/CMakeLists.txt
+++ b/subsys/bluetooth/host/classic/shell/CMakeLists.txt
@@ -5,3 +5,8 @@ zephyr_library_sources(bredr.c)
 zephyr_library_sources_ifdef(CONFIG_BT_RFCOMM rfcomm.c)
 zephyr_library_sources_ifdef(CONFIG_BT_A2DP a2dp.c)
 zephyr_library_sources_ifdef(CONFIG_BT_AVRCP avrcp.c)
+if(CONFIG_BT_HFP_HF OR CONFIG_BT_HFP_AG)
+  zephyr_library_sources(
+    hfp.c
+    )
+endif()
diff --git a/subsys/bluetooth/host/classic/shell/a2dp.c b/subsys/bluetooth/host/classic/shell/a2dp.c
index 2e8ffc5a08c..19e38e35094 100644
--- a/subsys/bluetooth/host/classic/shell/a2dp.c
+++ b/subsys/bluetooth/host/classic/shell/a2dp.c
@@ -25,6 +25,7 @@
 #include <zephyr/shell/shell.h>
 
 #include "host/shell/bt.h"
+#include "common/bt_shell_private.h"
 
 struct bt_a2dp *default_a2dp;
 static uint8_t a2dp_sink_sdp_registered;
@@ -207,82 +208,82 @@ static void shell_a2dp_print_capabilities(struct bt_a2dp_ep_info *ep_info)
 	codec_type = ep_info->codec_type;
 	codec_ie = ep_info->codec_cap.codec_ie;
 	codec_ie_len = ep_info->codec_cap.len;
-	shell_print(ctx_shell, "endpoint id: %d, %s, %s:", ep_info->sep_info.id,
-			(ep_info->sep_info.tsep == BT_AVDTP_SINK) ? "(sink)" : "(source)",
-			(ep_info->sep_info.inuse) ? "(in use)" : "(idle)");
+	bt_shell_print("endpoint id: %d, %s, %s:", ep_info->sep_info->id,
+		       (ep_info->sep_info->tsep == BT_AVDTP_SINK) ? "(sink)" : "(source)",
+		       (ep_info->sep_info->inuse) ? "(in use)" : "(idle)");
 	if (BT_A2DP_SBC == codec_type) {
-		shell_print(ctx_shell, "  codec type: SBC");
+		bt_shell_print("  codec type: SBC");
 
 		if (BT_A2DP_SBC_IE_LENGTH != codec_ie_len) {
-			shell_error(ctx_shell, "  wrong sbc codec ie");
+			bt_shell_error("  wrong sbc codec ie");
 			return;
 		}
 
-		shell_print(ctx_shell, "  sample frequency:");
+		bt_shell_print("  sample frequency:");
 		if (0U != (codec_ie[0U] & A2DP_SBC_SAMP_FREQ_16000)) {
-			shell_print(ctx_shell, "	16000 ");
+			bt_shell_print("	16000 ");
 		}
 		if (0U != (codec_ie[0U] & A2DP_SBC_SAMP_FREQ_32000)) {
-			shell_print(ctx_shell, "	32000 ");
+			bt_shell_print("	32000 ");
 		}
 		if (0U != (codec_ie[0U] & A2DP_SBC_SAMP_FREQ_44100)) {
-			shell_print(ctx_shell, "	44100 ");
+			bt_shell_print("	44100 ");
 		}
 		if (0U != (codec_ie[0U] & A2DP_SBC_SAMP_FREQ_48000)) {
-			shell_print(ctx_shell, "	48000");
+			bt_shell_print("	48000");
 		}
 
-		shell_print(ctx_shell, "  channel mode:");
+		bt_shell_print("  channel mode:");
 		if (0U != (codec_ie[0U] & A2DP_SBC_CH_MODE_MONO)) {
-			shell_print(ctx_shell, "	Mono ");
+			bt_shell_print("	Mono ");
 		}
 		if (0U != (codec_ie[0U] & A2DP_SBC_CH_MODE_DUAL)) {
-			shell_print(ctx_shell, "	Dual ");
+			bt_shell_print("	Dual ");
 		}
 		if (0U != (codec_ie[0U] & A2DP_SBC_CH_MODE_STREO)) {
-			shell_print(ctx_shell, "	Stereo ");
+			bt_shell_print("	Stereo ");
 		}
 		if (0U != (codec_ie[0U] & A2DP_SBC_CH_MODE_JOINT)) {
-			shell_print(ctx_shell, "	Joint-Stereo");
+			bt_shell_print("	Joint-Stereo");
 		}
 
-		 /* Decode Support for Block Length */
-		shell_print(ctx_shell, "  Block Length:");
+		/* Decode Support for Block Length */
+		bt_shell_print("  Block Length:");
 		if (0U != (codec_ie[1U] & A2DP_SBC_BLK_LEN_4)) {
-			shell_print(ctx_shell, "	4 ");
+			bt_shell_print("	4 ");
 		}
 		if (0U != (codec_ie[1U] & A2DP_SBC_BLK_LEN_8)) {
-			shell_print(ctx_shell, "	8 ");
+			bt_shell_print("	8 ");
 		}
 		if (0U != (codec_ie[1U] & A2DP_SBC_BLK_LEN_12)) {
-			shell_print(ctx_shell, "	12 ");
+			bt_shell_print("	12 ");
 		}
 		if (0U != (codec_ie[1U] & A2DP_SBC_BLK_LEN_16)) {
-			shell_print(ctx_shell, "	16");
+			bt_shell_print("	16");
 		}
 
 		/* Decode Support for Subbands */
-		shell_print(ctx_shell, "  Subbands:");
+		bt_shell_print("  Subbands:");
 		if (0U != (codec_ie[1U] & A2DP_SBC_SUBBAND_4)) {
-			shell_print(ctx_shell, "	4 ");
+			bt_shell_print("	4 ");
 		}
 		if (0U != (codec_ie[1U] & A2DP_SBC_SUBBAND_8)) {
-			shell_print(ctx_shell, "	8");
+			bt_shell_print("	8");
 		}
 
 		/* Decode Support for Allocation Method */
-		shell_print(ctx_shell, "  Allocation Method:");
+		bt_shell_print("  Allocation Method:");
 		if (0U != (codec_ie[1U] & A2DP_SBC_ALLOC_MTHD_SNR)) {
-			shell_print(ctx_shell, "	SNR ");
+			bt_shell_print("	SNR ");
 		}
 		if (0U != (codec_ie[1U] & A2DP_SBC_ALLOC_MTHD_LOUDNESS)) {
-			shell_print(ctx_shell, "	Loudness");
+			bt_shell_print("	Loudness");
 		}
 
-		shell_print(ctx_shell, "  Bitpool Range: %d - %d",
-					codec_ie[2U], codec_ie[3U]);
+		bt_shell_print("  Bitpool Range: %d - %d",
+			       codec_ie[2U], codec_ie[3U]);
 	} else {
-		shell_print(ctx_shell, "  not SBC codecs");
+		bt_shell_print("  not SBC codecs");
 	}
 }
 
@@ -290,16 +291,16 @@ void app_connected(struct bt_a2dp *a2dp, int err)
 {
 	if (!err) {
 		default_a2dp = a2dp;
-		shell_print(ctx_shell, "a2dp connected");
+		bt_shell_print("a2dp connected");
 	} else {
-		shell_print(ctx_shell, "a2dp connecting fail");
+		bt_shell_print("a2dp connecting fail");
 	}
 }
 
 void app_disconnected(struct bt_a2dp *a2dp)
 {
 	found_peer_sbc_endpoint = NULL;
-	shell_print(ctx_shell, "a2dp disconnected");
+	bt_shell_print("a2dp disconnected");
 }
 
 int app_config_req(struct bt_a2dp *a2dp, struct bt_a2dp_ep *ep,
@@ -312,10 +313,10 @@ int app_config_req(struct bt_a2dp *a2dp, struct bt_a2dp_ep *ep,
 	*stream = &sbc_stream;
 	*rsp_err_code = 0;
 
-	shell_print(ctx_shell, "receive requesting config and accept");
+	bt_shell_print("receive requesting config and accept");
 	sample_rate = bt_a2dp_sbc_get_sampling_frequency(
 		(struct bt_a2dp_codec_sbc_params *)&codec_cfg->codec_config->codec_ie[0]);
-	shell_print(ctx_shell, "sample rate %dHz", sample_rate);
+	bt_shell_print("sample rate %dHz", sample_rate);
 
 	return 0;
 }
@@ -326,10 +327,10 @@ int app_reconfig_req(struct bt_a2dp_stream *stream,
 	uint32_t sample_rate;
 
 	*rsp_err_code = 0;
-	shell_print(ctx_shell, "receive requesting reconfig and accept");
+	bt_shell_print("receive requesting reconfig and accept");
 	sample_rate = bt_a2dp_sbc_get_sampling_frequency(
 		(struct bt_a2dp_codec_sbc_params *)&codec_cfg->codec_config->codec_ie[0]);
-	shell_print(ctx_shell, "sample rate %dHz", sample_rate);
+	bt_shell_print("sample rate %dHz", sample_rate);
 
 	return 0;
 }
@@ -337,104 +338,104 @@ int app_reconfig_req(struct bt_a2dp_stream *stream,
 void app_config_rsp(struct bt_a2dp_stream *stream, uint8_t rsp_err_code)
 {
 	if (rsp_err_code == 0) {
-		shell_print(ctx_shell, "success to configure");
+		bt_shell_print("success to configure");
 	} else {
-		shell_print(ctx_shell, "fail to configure");
+		bt_shell_print("fail to configure");
 	}
 }
 
 int app_establish_req(struct bt_a2dp_stream *stream, uint8_t *rsp_err_code)
 {
 	*rsp_err_code = 0;
-	shell_print(ctx_shell, "receive requesting establishment and accept");
+	bt_shell_print("receive requesting establishment and accept");
 	return 0;
 }
 
 void app_establish_rsp(struct bt_a2dp_stream *stream, uint8_t rsp_err_code)
 {
 	if (rsp_err_code == 0) {
-		shell_print(ctx_shell, "success to establish");
+		bt_shell_print("success to establish");
 	} else {
-		shell_print(ctx_shell, "fail to establish");
+		bt_shell_print("fail to establish");
 	}
 }
 
 int app_release_req(struct bt_a2dp_stream *stream, uint8_t *rsp_err_code)
 {
 	*rsp_err_code = 0;
-	shell_print(ctx_shell, "receive requesting release and accept");
+	bt_shell_print("receive requesting release and accept");
 	return 0;
 }
 
 void app_release_rsp(struct bt_a2dp_stream *stream, uint8_t rsp_err_code)
 {
 	if (rsp_err_code == 0) {
-		shell_print(ctx_shell, "success to release");
+		bt_shell_print("success to release");
 	} else {
-		shell_print(ctx_shell, "fail to release");
+		bt_shell_print("fail to release");
 	}
 }
 
 int app_start_req(struct bt_a2dp_stream *stream, uint8_t *rsp_err_code)
 {
 	*rsp_err_code = 0;
-	shell_print(ctx_shell, "receive requesting start and accept");
+	bt_shell_print("receive requesting start and accept");
 	return 0;
 }
 
 void app_start_rsp(struct bt_a2dp_stream *stream, uint8_t rsp_err_code)
 {
 	if (rsp_err_code == 0) {
-		shell_print(ctx_shell, "success to start");
+		bt_shell_print("success to start");
 	} else {
-		shell_print(ctx_shell, "fail to start");
+		bt_shell_print("fail to start");
 	}
 }
 
 int app_suspend_req(struct bt_a2dp_stream *stream, uint8_t *rsp_err_code)
 {
 	*rsp_err_code = 0;
-	shell_print(ctx_shell, "receive requesting suspend and accept");
+	bt_shell_print("receive requesting suspend and accept");
 	return 0;
 }
 
 void app_suspend_rsp(struct bt_a2dp_stream *stream, uint8_t rsp_err_code)
 {
 	if (rsp_err_code == 0) {
-		shell_print(ctx_shell, "success to suspend");
+		bt_shell_print("success to suspend");
 	} else {
-		shell_print(ctx_shell, "fail to suspend");
+		bt_shell_print("fail to suspend");
 	}
 }
 
 void stream_configured(struct bt_a2dp_stream *stream)
 {
-	shell_print(ctx_shell, "stream configured");
+	bt_shell_print("stream configured");
 }
 
 void stream_established(struct bt_a2dp_stream *stream)
 {
-	shell_print(ctx_shell, "stream established");
+	bt_shell_print("stream established");
 }
 
 void stream_released(struct bt_a2dp_stream *stream)
 {
-	shell_print(ctx_shell, "stream released");
+	bt_shell_print("stream released");
 }
 
 void stream_started(struct bt_a2dp_stream *stream)
 {
-	shell_print(ctx_shell, "stream started");
+	bt_shell_print("stream started");
 }
 
 void stream_suspended(struct bt_a2dp_stream *stream)
 {
-	shell_print(ctx_shell, "stream suspended");
+	bt_shell_print("stream suspended");
 }
 
 void stream_aborted(struct bt_a2dp_stream *stream)
 {
-	shell_print(ctx_shell, "stream aborted");
+	bt_shell_print("stream aborted");
 }
 
 void sink_sbc_streamer_data(struct bt_a2dp_stream *stream, struct net_buf *buf,
@@ -446,9 +447,9 @@ void sink_sbc_streamer_data(struct bt_a2dp_stream *stream, struct net_buf *buf,
 		return;
 	}
 	sbc_hdr = net_buf_pull_u8(buf);
-	shell_print(ctx_shell, "received, num of frames: %d, data length:%d",
-		(uint8_t)BT_A2DP_SBC_MEDIA_HDR_NUM_FRAMES_GET(sbc_hdr), buf->len);
-	shell_print(ctx_shell, "data: %d, %d, %d, %d, %d, %d ......", buf->data[0],
+	bt_shell_print("received, num of frames: %d, data length:%d",
+		       (uint8_t)BT_A2DP_SBC_MEDIA_HDR_NUM_FRAMES_GET(sbc_hdr), buf->len);
+	bt_shell_print("data: %d, %d, %d, %d, %d, %d ......", buf->data[0],
 		buf->data[1], buf->data[2], buf->data[3], buf->data[4], buf->data[5]);
 }
 
@@ -584,7 +585,7 @@ static int cmd_disconnect(const struct shell *sh, int32_t argc, char *argv[])
 void app_configured(int err)
 {
 	if (err) {
-		shell_print(ctx_shell, "configure fail");
+		bt_shell_print("configure fail");
 	}
 }
 
@@ -655,7 +656,7 @@ static uint8_t bt_a2dp_discover_peer_endpoint_cb(struct bt_a2dp *a2dp,
 		struct bt_a2dp_ep_info *info, struct bt_a2dp_ep **ep)
 {
 	if (info != NULL) {
-		shell_print(ctx_shell, "find one endpoint");
+		bt_shell_print("find one endpoint");
 		shell_a2dp_print_capabilities(info);
 		if ((info->codec_type == BT_A2DP_SBC) &&
 		    (ep != NULL)) {
diff --git a/subsys/bluetooth/host/classic/shell/avrcp.c b/subsys/bluetooth/host/classic/shell/avrcp.c
index 182168b17a3..4e926646f71 100644
--- a/subsys/bluetooth/host/classic/shell/avrcp.c
+++ b/subsys/bluetooth/host/classic/shell/avrcp.c
@@ -27,45 +27,97 @@
 #include <zephyr/shell/shell.h>
 
 #include "host/shell/bt.h"
+#include "common/bt_shell_private.h"
 
 struct bt_avrcp *default_avrcp;
 static bool avrcp_registered;
+static uint8_t local_tid;
+
+static uint8_t get_next_tid(void)
+{
+	uint8_t ret = local_tid;
+
+	local_tid++;
+	local_tid &= 0x0F;
+
+	return ret;
+}
 
 static void avrcp_connected(struct bt_avrcp *avrcp)
 {
+	bt_shell_print("AVRCP connected");
 	default_avrcp = avrcp;
-	shell_print(ctx_shell, "AVRCP connected");
+	local_tid = 0;
 }
 
 static void avrcp_disconnected(struct bt_avrcp *avrcp)
 {
-	shell_print(ctx_shell, "AVRCP disconnected");
+	bt_shell_print("AVRCP disconnected");
+	local_tid = 0;
+}
+
+static void avrcp_get_cap_rsp(struct bt_avrcp *avrcp, uint8_t tid,
+			      const struct bt_avrcp_get_cap_rsp *rsp)
+{
+	uint8_t i;
+
+	switch (rsp->cap_id) {
+	case BT_AVRCP_CAP_COMPANY_ID:
+		for (i = 0; i < rsp->cap_cnt; i++) {
+			bt_shell_print("Remote CompanyID = 0x%06x",
+				       sys_get_be24(&rsp->cap[BT_AVRCP_COMPANY_ID_SIZE * i]));
+		}
+		break;
+	case BT_AVRCP_CAP_EVENTS_SUPPORTED:
+		for (i = 0; i < rsp->cap_cnt; i++) {
+			bt_shell_print("Remote supported EventID = 0x%02x", rsp->cap[i]);
+		}
+		break;
+	}
 }
 
-static void avrcp_unit_info_rsp(struct bt_avrcp *avrcp, struct bt_avrcp_unit_info_rsp *rsp)
+static void avrcp_unit_info_rsp(struct bt_avrcp *avrcp, uint8_t tid,
+				struct bt_avrcp_unit_info_rsp *rsp)
 {
-	shell_print(ctx_shell, "AVRCP unit info received, unit type = 0x%02x, company_id = 0x%06x",
-		    rsp->unit_type, rsp->company_id);
+	bt_shell_print("AVRCP unit info received, unit type = 0x%02x, company_id = 0x%06x",
+		       rsp->unit_type, rsp->company_id);
 }
 
-static void avrcp_subunit_info_rsp(struct bt_avrcp *avrcp, struct bt_avrcp_subunit_info_rsp *rsp)
+static void avrcp_subunit_info_rsp(struct bt_avrcp *avrcp, uint8_t tid,
+				   struct bt_avrcp_subunit_info_rsp *rsp)
 {
 	int i;
 
-	shell_print(ctx_shell,
-		    "AVRCP subunit info received, subunit type = 0x%02x, extended subunit = %d",
-		    rsp->subunit_type, rsp->max_subunit_id);
+	bt_shell_print("AVRCP subunit info received, subunit type = 0x%02x, extended subunit = %d",
+		       rsp->subunit_type, rsp->max_subunit_id);
 	for (i = 0; i < rsp->max_subunit_id; i++) {
-		shell_print(ctx_shell, "extended subunit id = %d, subunit type = 0x%02x",
-			    rsp->extended_subunit_id[i], rsp->extended_subunit_type[i]);
+		bt_shell_print("extended subunit id = %d, subunit type = 0x%02x",
+			       rsp->extended_subunit_id[i], rsp->extended_subunit_type[i]);
+	}
+}
+
+static void avrcp_passthrough_rsp(struct bt_avrcp *avrcp, uint8_t tid, bt_avrcp_rsp_t result,
+				  const struct bt_avrcp_passthrough_rsp *rsp)
+{
+	if (result == BT_AVRCP_RSP_ACCEPTED) {
+		bt_shell_print(
+			"AVRCP passthough command accepted, operation id = 0x%02x, state = %d",
+			BT_AVRCP_PASSTHROUGH_GET_OPID(rsp), BT_AVRCP_PASSTHROUGH_GET_STATE(rsp));
+	} else {
+		bt_shell_print("AVRCP passthough command rejected, operation id = 0x%02x, state = "
+			       "%d, response = %d",
+			       BT_AVRCP_PASSTHROUGH_GET_OPID(rsp),
+			       BT_AVRCP_PASSTHROUGH_GET_STATE(rsp), result);
 	}
 }
 
 static struct bt_avrcp_cb avrcp_cb = {
 	.connected = avrcp_connected,
 	.disconnected = avrcp_disconnected,
+	.get_cap_rsp = avrcp_get_cap_rsp,
 	.unit_info_rsp = avrcp_unit_info_rsp,
 	.subunit_info_rsp = avrcp_subunit_info_rsp,
+	.passthrough_rsp = avrcp_passthrough_rsp,
 };
 
 static int register_cb(const struct shell *sh)
@@ -147,7 +199,7 @@ static int cmd_get_unit_info(const struct shell *sh, int32_t argc, char *argv[])
 	}
 
 	if (default_avrcp != NULL) {
-		bt_avrcp_get_unit_info(default_avrcp);
+		bt_avrcp_get_unit_info(default_avrcp, get_next_tid());
 	} else {
 		shell_error(sh, "AVRCP is not connected");
 	}
@@ -164,7 +216,7 @@ static int cmd_get_subunit_info(const struct shell *sh, int32_t argc, char *argv
 	}
 
 	if (default_avrcp != NULL) {
-		bt_avrcp_get_subunit_info(default_avrcp);
+		bt_avrcp_get_subunit_info(default_avrcp, get_next_tid());
 	} else {
 		shell_error(sh, "AVRCP is not connected");
 	}
@@ -172,15 +224,74 @@ static int cmd_get_subunit_info(const struct shell *sh, int32_t argc, char *argv
 	return 0;
 }
 
-SHELL_STATIC_SUBCMD_SET_CREATE(avrcp_cmds,
-			       SHELL_CMD_ARG(register_cb, NULL, "register avrcp callbacks",
-					     cmd_register_cb, 1, 0),
-			       SHELL_CMD_ARG(connect, NULL, "<address>", cmd_connect, 2, 0),
-			       SHELL_CMD_ARG(disconnect, NULL, "<address>", cmd_disconnect, 2, 0),
-			       SHELL_CMD_ARG(get_unit, NULL, "<address>", cmd_get_unit_info, 2, 0),
-			       SHELL_CMD_ARG(get_subunit, NULL, "<address>", cmd_get_subunit_info,
-					     2, 0),
-			       SHELL_SUBCMD_SET_END);
+static int cmd_passthrough(const struct shell *sh, bt_avrcp_opid_t opid, const uint8_t *payload,
+			   uint8_t len)
+{
+	if (!avrcp_registered) {
+		if (register_cb(sh) != 0) {
+			return -ENOEXEC;
+		}
+	}
+
+	if (default_avrcp != NULL) {
+		bt_avrcp_passthrough(default_avrcp, get_next_tid(), opid, BT_AVRCP_BUTTON_PRESSED,
+				     payload, len);
+		bt_avrcp_passthrough(default_avrcp, get_next_tid(), opid, BT_AVRCP_BUTTON_RELEASED,
+				     payload, len);
+	} else {
+		shell_error(sh, "AVRCP is not connected");
+	}
+
+	return 0;
+}
+
+static int cmd_play(const struct shell *sh, int32_t argc, char *argv[])
+{
+	return cmd_passthrough(sh, BT_AVRCP_OPID_PLAY, NULL, 0);
+}
+
+static int cmd_pause(const struct shell *sh, int32_t argc, char *argv[])
+{
+	return cmd_passthrough(sh, BT_AVRCP_OPID_PAUSE, NULL, 0);
+}
+
+static int cmd_get_cap(const struct shell *sh, int32_t argc, char *argv[])
+{
+	const char *cap_id;
+
+	if (!avrcp_registered) {
+		if (register_cb(sh) != 0) {
+			return -ENOEXEC;
+		}
+	}
+
+	if (default_avrcp == NULL) {
+		shell_error(sh, "AVRCP is not connected");
+		return 0;
+	}
+
+	cap_id = argv[1];
+	if (!strcmp(cap_id, "company")) {
+		bt_avrcp_get_cap(default_avrcp, get_next_tid(), BT_AVRCP_CAP_COMPANY_ID);
+	} else if (!strcmp(cap_id, "events")) {
+		bt_avrcp_get_cap(default_avrcp, get_next_tid(), BT_AVRCP_CAP_EVENTS_SUPPORTED);
+	}
+
+	return 0;
+}
+
+SHELL_STATIC_SUBCMD_SET_CREATE(
+	avrcp_cmds,
+	SHELL_CMD_ARG(register_cb, NULL, "register avrcp callbacks", cmd_register_cb, 1, 0),
+	SHELL_CMD_ARG(connect, NULL, "connect AVRCP", cmd_connect, 1, 0),
+	SHELL_CMD_ARG(disconnect, NULL, "disconnect AVRCP", cmd_disconnect, 1, 0),
+	SHELL_CMD_ARG(get_unit, NULL, "get unit info", cmd_get_unit_info, 1, 0),
+	SHELL_CMD_ARG(get_subunit, NULL, "get subunit info", cmd_get_subunit_info, 1, 0),
+	SHELL_CMD_ARG(get_cap, NULL, "get capabilities <cap_id: company or events>", cmd_get_cap, 2,
+		      0),
+	SHELL_CMD_ARG(play, NULL, "request a play at the remote player", cmd_play, 1, 0),
+	SHELL_CMD_ARG(pause, NULL, "request a pause at the remote player", cmd_pause, 1, 0),
+	SHELL_SUBCMD_SET_END);
 
 static int cmd_avrcp(const struct shell *sh, size_t argc, char **argv)
 {
diff --git a/subsys/bluetooth/host/classic/shell/bredr.c b/subsys/bluetooth/host/classic/shell/bredr.c
index b59dee96fb7..ac7d2ff5f4d 100644
--- a/subsys/bluetooth/host/classic/shell/bredr.c
+++ b/subsys/bluetooth/host/classic/shell/bredr.c
@@ -30,22 +30,23 @@
 #include <zephyr/shell/shell.h>
 
 #include "host/shell/bt.h"
+#include "common/bt_shell_private.h"
 
 #if defined(CONFIG_BT_CONN)
 /* Connection context for BR/EDR legacy pairing in sec mode 3 */
 static struct bt_conn *pairing_conn;
 #endif /* CONFIG_BT_CONN */
 
-#define DATA_BREDR_MTU		48
+#define DATA_BREDR_MTU 48
 
-NET_BUF_POOL_FIXED_DEFINE(data_pool, 1, DATA_BREDR_MTU, 8, NULL);
+NET_BUF_POOL_FIXED_DEFINE(data_tx_pool, 1, BT_L2CAP_SDU_BUF_SIZE(DATA_BREDR_MTU),
+			  CONFIG_BT_CONN_TX_USER_DATA_SIZE, NULL);
+NET_BUF_POOL_FIXED_DEFINE(data_rx_pool, 1, DATA_BREDR_MTU, 8, NULL);
 
-#define SDP_CLIENT_USER_BUF_LEN		512
-NET_BUF_POOL_FIXED_DEFINE(sdp_client_pool, CONFIG_BT_MAX_CONN,
-			  SDP_CLIENT_USER_BUF_LEN, 8, NULL);
+#define SDP_CLIENT_USER_BUF_LEN 512
+NET_BUF_POOL_FIXED_DEFINE(sdp_client_pool, CONFIG_BT_MAX_CONN, SDP_CLIENT_USER_BUF_LEN, 8, NULL);
 
-static int cmd_auth_pincode(const struct shell *sh,
-			    size_t argc, char *argv[])
+static int cmd_auth_pincode(const struct shell *sh, size_t argc, char *argv[])
 {
 	struct bt_conn *conn;
 	uint8_t max = 16U;
@@ -64,8 +65,7 @@ static int cmd_auth_pincode(const struct shell *sh,
 	}
 
 	if (strlen(argv[1]) > max) {
-		shell_print(sh, "PIN code value invalid - enter max %u "
-			    "digits", max);
+		shell_print(sh, "PIN code value invalid - enter max %u digits", max);
 		return -ENOEXEC;
 	}
 
@@ -102,8 +102,8 @@ static int cmd_connect(const struct shell *sh, size_t argc, char *argv[])
 	return 0;
 }
 
-static void br_device_found(const bt_addr_t *addr, int8_t rssi,
-				  const uint8_t cod[3], const uint8_t eir[240])
+static void br_device_found(const bt_addr_t *addr, int8_t rssi, const uint8_t cod[3],
+			    const uint8_t eir[240])
 {
 	char br_addr[BT_ADDR_STR_LEN];
 	char name[239];
@@ -146,21 +146,19 @@ static void br_device_found(const bt_addr_t *addr, int8_t rssi,
 
 	bt_addr_to_str(addr, br_addr, sizeof(br_addr));
 
-	shell_print(ctx_shell, "[DEVICE]: %s, RSSI %i %s", br_addr, rssi, name);
+	bt_shell_print("[DEVICE]: %s, RSSI %i %s", br_addr, rssi, name);
 }
 
 static struct bt_br_discovery_result br_discovery_results[5];
 
-static void br_discovery_complete(const struct bt_br_discovery_result *results,
-				  size_t count)
+static void br_discovery_complete(const struct bt_br_discovery_result *results, size_t count)
 {
 	size_t i;
 
-	shell_print(ctx_shell, "BR/EDR discovery complete");
+	bt_shell_print("BR/EDR discovery complete");
 
 	for (i = 0; i < count; i++) {
-		br_device_found(&results[i].addr, results[i].rssi,
-				results[i].cod, results[i].eir);
+		br_device_found(&results[i].addr, results[i].rssi, results[i].cod, results[i].eir);
 	}
 }
 
@@ -216,104 +214,441 @@ static int cmd_discovery(const struct shell *sh, size_t argc, char *argv[])
 	return 0;
 }
 
+struct bt_l2cap_br_server {
+	struct bt_l2cap_server server;
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	uint8_t options;
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+};
+
+struct l2cap_br_chan {
+	struct bt_l2cap_br_chan chan;
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	struct k_fifo l2cap_recv_fifo;
+	bool hold_credit;
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+};
+
 static int l2cap_recv(struct bt_l2cap_chan *chan, struct net_buf *buf)
 {
-	shell_print(ctx_shell, "Incoming data channel %p len %u", chan,
-		    buf->len);
+	struct l2cap_br_chan *br_chan = CONTAINER_OF(chan, struct l2cap_br_chan, chan.chan);
+
+	bt_shell_print("Incoming data channel %p len %u", chan, buf->len);
+
+	if (buf->len) {
+		bt_shell_hexdump(buf->data, buf->len);
+	}
+
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	if (br_chan->hold_credit) {
+		k_fifo_put(&br_chan->l2cap_recv_fifo, buf);
+		return -EINPROGRESS;
+	}
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+	(void)br_chan;
 
 	return 0;
 }
 
 static void l2cap_connected(struct bt_l2cap_chan *chan)
 {
-	shell_print(ctx_shell, "Channel %p connected", chan);
+	struct l2cap_br_chan *br_chan = CONTAINER_OF(chan, struct l2cap_br_chan, chan.chan);
+
+	bt_shell_print("Channel %p connected", chan);
+
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	switch (br_chan->chan.rx.mode) {
+	case BT_L2CAP_BR_LINK_MODE_BASIC:
+		bt_shell_print("It is basic mode");
+		if (br_chan->hold_credit) {
+			br_chan->hold_credit = false;
+			bt_shell_warn("hold_credit is unsupported in basic mode");
+		}
+		break;
+	case BT_L2CAP_BR_LINK_MODE_RET:
+		bt_shell_print("It is retransmission mode");
+		break;
+	case BT_L2CAP_BR_LINK_MODE_FC:
+		bt_shell_print("It is flow control mode");
+		break;
+	case BT_L2CAP_BR_LINK_MODE_ERET:
+		bt_shell_print("It is enhance retransmission mode");
+		break;
+	case BT_L2CAP_BR_LINK_MODE_STREAM:
+		bt_shell_print("It is streaming mode");
+		break;
+	default:
+		bt_shell_error("It is unknown mode");
+		break;
+	}
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+	(void)br_chan;
 }
 
 static void l2cap_disconnected(struct bt_l2cap_chan *chan)
 {
-	shell_print(ctx_shell, "Channel %p disconnected", chan);
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	struct net_buf *buf;
+	struct l2cap_br_chan *br_chan = CONTAINER_OF(chan, struct l2cap_br_chan, chan.chan);
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+
+	bt_shell_print("Channel %p disconnected", chan);
+
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	do {
+		buf = k_fifo_get(&br_chan->l2cap_recv_fifo, K_NO_WAIT);
+		if (buf != NULL) {
+			net_buf_unref(buf);
+		}
+	} while (buf != NULL);
+#endif /* CONFIG_BT_L2CAP_RET_FC */
 }
 
 static struct net_buf *l2cap_alloc_buf(struct bt_l2cap_chan *chan)
 {
-	shell_print(ctx_shell, "Channel %p requires buffer", chan);
+	bt_shell_print("Channel %p requires buffer", chan);
 
-	return net_buf_alloc(&data_pool, K_FOREVER);
+	return net_buf_alloc(&data_rx_pool, K_NO_WAIT);
 }
 
 static const struct bt_l2cap_chan_ops l2cap_ops = {
-	.alloc_buf	= l2cap_alloc_buf,
-	.recv		= l2cap_recv,
-	.connected	= l2cap_connected,
-	.disconnected	= l2cap_disconnected,
+	.alloc_buf = l2cap_alloc_buf,
+	.recv = l2cap_recv,
+	.connected = l2cap_connected,
+	.disconnected = l2cap_disconnected,
 };
 
-static struct bt_l2cap_br_chan l2cap_chan = {
-	.chan.ops	= &l2cap_ops,
-	 /* Set for now min. MTU */
-	.rx.mtu		= 48,
+#define BT_L2CAP_BR_SERVER_OPT_RET           BIT(0)
+#define BT_L2CAP_BR_SERVER_OPT_FC            BIT(1)
+#define BT_L2CAP_BR_SERVER_OPT_ERET          BIT(2)
+#define BT_L2CAP_BR_SERVER_OPT_STREAM        BIT(3)
+#define BT_L2CAP_BR_SERVER_OPT_MODE_OPTIONAL BIT(4)
+#define BT_L2CAP_BR_SERVER_OPT_EXT_WIN_SIZE  BIT(5)
+#define BT_L2CAP_BR_SERVER_OPT_HOLD_CREDIT   BIT(6)
+
+static struct l2cap_br_chan l2cap_chan = {
+	.chan = {
+		.chan.ops = &l2cap_ops,
+		/* Set for now min. MTU */
+		.rx.mtu = DATA_BREDR_MTU,
+	},
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	.l2cap_recv_fifo = Z_FIFO_INITIALIZER(l2cap_chan.l2cap_recv_fifo),
+#endif /* CONFIG_BT_L2CAP_RET_FC */
 };
 
 static int l2cap_accept(struct bt_conn *conn, struct bt_l2cap_server *server,
 			struct bt_l2cap_chan **chan)
 {
-	shell_print(ctx_shell, "Incoming BR/EDR conn %p", conn);
+	struct bt_l2cap_br_server *br_server;
+
+	br_server = CONTAINER_OF(server, struct bt_l2cap_br_server, server);
 
-	if (l2cap_chan.chan.conn) {
-		shell_error(ctx_shell, "No channels available");
+	bt_shell_print("Incoming BR/EDR conn %p", conn);
+
+	if (l2cap_chan.chan.chan.conn) {
+		bt_shell_error("No channels available");
 		return -ENOMEM;
 	}
 
-	*chan = &l2cap_chan.chan;
+	*chan = &l2cap_chan.chan.chan;
 
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	if (br_server->options & BT_L2CAP_BR_SERVER_OPT_HOLD_CREDIT) {
+		l2cap_chan.hold_credit = true;
+	} else {
+		l2cap_chan.hold_credit = false;
+	}
+
+	if (br_server->options & BT_L2CAP_BR_SERVER_OPT_EXT_WIN_SIZE) {
+		l2cap_chan.chan.rx.extended_control = true;
+	} else {
+		l2cap_chan.chan.rx.extended_control = false;
+	}
+
+	if (br_server->options & BT_L2CAP_BR_SERVER_OPT_MODE_OPTIONAL) {
+		l2cap_chan.chan.rx.optional = true;
+	} else {
+		l2cap_chan.chan.rx.optional = false;
+	}
+
+	l2cap_chan.chan.rx.fcs = BT_L2CAP_BR_FCS_16BIT;
+
+	if (br_server->options & BT_L2CAP_BR_SERVER_OPT_STREAM) {
+		l2cap_chan.chan.rx.mode = BT_L2CAP_BR_LINK_MODE_STREAM;
+		l2cap_chan.chan.rx.max_window = CONFIG_BT_L2CAP_MAX_WINDOW_SIZE;
+		l2cap_chan.chan.rx.max_transmit = 0;
+	} else if (br_server->options & BT_L2CAP_BR_SERVER_OPT_ERET) {
+		l2cap_chan.chan.rx.mode = BT_L2CAP_BR_LINK_MODE_ERET;
+		l2cap_chan.chan.rx.max_window = CONFIG_BT_L2CAP_MAX_WINDOW_SIZE;
+		l2cap_chan.chan.rx.max_transmit = 3;
+	} else if (br_server->options & BT_L2CAP_BR_SERVER_OPT_FC) {
+		l2cap_chan.chan.rx.mode = BT_L2CAP_BR_LINK_MODE_FC;
+		l2cap_chan.chan.rx.max_window = CONFIG_BT_L2CAP_MAX_WINDOW_SIZE;
+		l2cap_chan.chan.rx.max_transmit = 3;
+	} else if (br_server->options & BT_L2CAP_BR_SERVER_OPT_RET) {
+		l2cap_chan.chan.rx.mode = BT_L2CAP_BR_LINK_MODE_RET;
+		l2cap_chan.chan.rx.max_window = CONFIG_BT_L2CAP_MAX_WINDOW_SIZE;
+		l2cap_chan.chan.rx.max_transmit = 3;
+	}
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+	(void)br_server;
 	return 0;
 }
 
-static struct bt_l2cap_server br_server = {
-	.accept = l2cap_accept,
+static struct bt_l2cap_br_server l2cap_server = {
+	.server = {
+		.accept = l2cap_accept,
+	},
 };
 
-static int cmd_l2cap_register(const struct shell *sh,
-			      size_t argc, char *argv[])
+static int cmd_l2cap_register(const struct shell *sh, size_t argc, char *argv[])
 {
-	if (br_server.psm) {
+	if (l2cap_server.server.psm) {
 		shell_print(sh, "Already registered");
 		return -ENOEXEC;
 	}
 
-	br_server.psm = strtoul(argv[1], NULL, 16);
+	l2cap_server.server.psm = strtoul(argv[1], NULL, 16);
+
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	l2cap_server.options = 0;
+
+	if (!strcmp(argv[2], "none")) {
+		/* Support mode: None */
+	} else if (!strcmp(argv[2], "ret")) {
+		l2cap_server.options |= BT_L2CAP_BR_SERVER_OPT_RET;
+	} else if (!strcmp(argv[2], "fc")) {
+		l2cap_server.options |= BT_L2CAP_BR_SERVER_OPT_FC;
+	} else if (!strcmp(argv[2], "eret")) {
+		l2cap_server.options |= BT_L2CAP_BR_SERVER_OPT_ERET;
+	} else if (!strcmp(argv[2], "stream")) {
+		l2cap_server.options |= BT_L2CAP_BR_SERVER_OPT_STREAM;
+	} else {
+		l2cap_server.server.psm = 0;
+		shell_help(sh);
+		return SHELL_CMD_HELP_PRINTED;
+	}
+
+	for (size_t index = 3; index < argc; index++) {
+		if (!strcmp(argv[index], "hold_credit")) {
+			l2cap_server.options |= BT_L2CAP_BR_SERVER_OPT_HOLD_CREDIT;
+		} else if (!strcmp(argv[index], "mode_optional")) {
+			l2cap_server.options |= BT_L2CAP_BR_SERVER_OPT_MODE_OPTIONAL;
+		} else if (!strcmp(argv[index], "extended_control")) {
+			l2cap_server.options |= BT_L2CAP_BR_SERVER_OPT_EXT_WIN_SIZE;
+		} else {
+			l2cap_server.server.psm = 0;
+			shell_help(sh);
+			return SHELL_CMD_HELP_PRINTED;
+		}
+	}
 
-	if (bt_l2cap_br_server_register(&br_server) < 0) {
+	if ((l2cap_server.options & BT_L2CAP_BR_SERVER_OPT_EXT_WIN_SIZE) &&
+	    (!(l2cap_server.options &
+	       (BT_L2CAP_BR_SERVER_OPT_ERET | BT_L2CAP_BR_SERVER_OPT_STREAM)))) {
+		shell_error(sh, "[extended_control] only supports mode eret and stream");
+		l2cap_server.server.psm = 0U;
+		return -ENOEXEC;
+	}
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+
+	if (bt_l2cap_br_server_register(&l2cap_server.server) < 0) {
 		shell_error(sh, "Unable to register psm");
-		br_server.psm = 0U;
+		l2cap_server.server.psm = 0U;
 		return -ENOEXEC;
 	}
 
-	shell_print(sh, "L2CAP psm %u registered", br_server.psm);
+	shell_print(sh, "L2CAP psm %u registered", l2cap_server.server.psm);
 
 	return 0;
 }
 
-static int cmd_discoverable(const struct shell *sh,
-			    size_t argc, char *argv[])
+static int cmd_l2cap_connect(const struct shell *sh, size_t argc, char *argv[])
 {
+	uint16_t psm;
+	struct bt_conn_info info;
 	int err;
-	const char *action;
 
-	action = argv[1];
+	if (!default_conn) {
+		shell_error(sh, "Not connected");
+		return -ENOEXEC;
+	}
 
-	if (!strcmp(action, "on")) {
-		err = bt_br_set_discoverable(true);
-	} else if (!strcmp(action, "off")) {
-		err = bt_br_set_discoverable(false);
+	if (l2cap_chan.chan.chan.conn) {
+		bt_shell_error("No channels available");
+		return -ENOMEM;
+	}
+
+	err = bt_conn_get_info(default_conn, &info);
+	if ((err < 0) || (info.type != BT_CONN_TYPE_BR)) {
+		shell_error(sh, "Invalid conn type");
+		return -ENOEXEC;
+	}
+
+	psm = strtoul(argv[1], NULL, 16);
+
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	if (!strcmp(argv[2], "none")) {
+		l2cap_chan.chan.rx.mode = BT_L2CAP_BR_LINK_MODE_BASIC;
+	} else if (!strcmp(argv[2], "ret")) {
+		l2cap_chan.chan.rx.mode = BT_L2CAP_BR_LINK_MODE_RET;
+		l2cap_chan.chan.rx.max_transmit = 3;
+	} else if (!strcmp(argv[2], "fc")) {
+		l2cap_chan.chan.rx.mode = BT_L2CAP_BR_LINK_MODE_FC;
+		l2cap_chan.chan.rx.max_transmit = 3;
+	} else if (!strcmp(argv[2], "eret")) {
+		l2cap_chan.chan.rx.mode = BT_L2CAP_BR_LINK_MODE_ERET;
+		l2cap_chan.chan.rx.max_transmit = 3;
+	} else if (!strcmp(argv[2], "stream")) {
+		l2cap_chan.chan.rx.mode = BT_L2CAP_BR_LINK_MODE_STREAM;
+		l2cap_chan.chan.rx.max_transmit = 0;
+	} else {
+		shell_help(sh);
+		return SHELL_CMD_HELP_PRINTED;
+	}
+
+	l2cap_chan.hold_credit = false;
+	l2cap_chan.chan.rx.optional = false;
+	l2cap_chan.chan.rx.extended_control = false;
+
+	for (size_t index = 3; index < argc; index++) {
+		if (!strcmp(argv[index], "hold_credit")) {
+			l2cap_chan.hold_credit = true;
+		} else if (!strcmp(argv[index], "mode_optional")) {
+			l2cap_chan.chan.rx.optional = true;
+		} else if (!strcmp(argv[index], "extended_control")) {
+			l2cap_chan.chan.rx.extended_control = true;
+		} else {
+			shell_help(sh);
+			return SHELL_CMD_HELP_PRINTED;
+		}
+	}
+
+	if ((l2cap_chan.chan.rx.extended_control) &&
+	    ((l2cap_chan.chan.rx.mode != BT_L2CAP_BR_LINK_MODE_ERET) &&
+	     (l2cap_chan.chan.rx.mode != BT_L2CAP_BR_LINK_MODE_STREAM))) {
+		shell_error(sh, "[extended_control] only supports mode eret and stream");
+		return -ENOEXEC;
+	}
+
+	if (l2cap_chan.hold_credit && (l2cap_chan.chan.rx.mode == BT_L2CAP_BR_LINK_MODE_BASIC)) {
+		shell_error(sh, "[hold_credit] cannot support basic mode");
+		return -ENOEXEC;
+	}
+
+	l2cap_chan.chan.rx.max_window = CONFIG_BT_L2CAP_MAX_WINDOW_SIZE;
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+
+	err = bt_l2cap_chan_connect(default_conn, &l2cap_chan.chan.chan, psm);
+	if (err < 0) {
+		shell_error(sh, "Unable to connect to psm %u (err %d)", psm, err);
+	} else {
+		shell_print(sh, "L2CAP connection pending");
+	}
+
+	return err;
+}
+
+static int cmd_l2cap_disconnect(const struct shell *sh, size_t argc, char *argv[])
+{
+	int err;
+
+	err = bt_l2cap_chan_disconnect(&l2cap_chan.chan.chan);
+	if (err) {
+		shell_error(sh, "Unable to disconnect: %u", -err);
+	}
+
+	return err;
+}
+
+static int cmd_l2cap_send(const struct shell *sh, size_t argc, char *argv[])
+{
+	static uint8_t buf_data[DATA_BREDR_MTU];
+	int err, len = DATA_BREDR_MTU, count = 1;
+	struct net_buf *buf;
+
+	if (argc > 1) {
+		count = strtoul(argv[1], NULL, 10);
+	}
+
+	if (argc > 2) {
+		len = strtoul(argv[2], NULL, 10);
+		if (len > DATA_BREDR_MTU) {
+			shell_error(sh, "Length exceeds TX MTU for the channel");
+			return -ENOEXEC;
+		}
+	}
+
+	len = MIN(l2cap_chan.chan.tx.mtu, len);
+
+	while (count--) {
+		shell_print(sh, "Rem %d", count);
+		buf = net_buf_alloc(&data_tx_pool, K_SECONDS(2));
+		if (!buf) {
+			if (l2cap_chan.chan.state != BT_L2CAP_CONNECTED) {
+				shell_error(sh, "Channel disconnected, stopping TX");
+
+				return -EAGAIN;
+			}
+			shell_error(sh, "Allocation timeout, stopping TX");
+
+			return -EAGAIN;
+		}
+		net_buf_reserve(buf, BT_L2CAP_CHAN_SEND_RESERVE);
+		memset(buf_data, count, sizeof(buf_data));
+
+		net_buf_add_mem(buf, buf_data, len);
+		err = bt_l2cap_chan_send(&l2cap_chan.chan.chan, buf);
+		if (err < 0) {
+			shell_error(sh, "Unable to send: %d", -err);
+			net_buf_unref(buf);
+			return -ENOEXEC;
+		}
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+static int cmd_l2cap_credits(const struct shell *sh, size_t argc, char *argv[])
+{
+	int err;
+	struct net_buf *buf;
+
+	buf = k_fifo_get(&l2cap_chan.l2cap_recv_fifo, K_NO_WAIT);
+	if (buf != NULL) {
+		err = bt_l2cap_chan_recv_complete(&l2cap_chan.chan.chan, buf);
+		if (err < 0) {
+			shell_error(sh, "Unable to set recv_complete: %d", -err);
+		}
 	} else {
+		shell_warn(sh, "No pending recv buffer");
+	}
+
+	return 0;
+}
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+
+static int cmd_discoverable(const struct shell *sh, size_t argc, char *argv[])
+{
+	int err = 0;
+	bool enable;
+	bool limited = false;
+
+	enable = shell_strtobool(argv[1], 10, &err);
+	if (err) {
 		shell_help(sh);
 		return SHELL_CMD_HELP_PRINTED;
 	}
 
+	if (argc > 2 && !strcmp(argv[2], "limited")) {
+		limited = true;
+	}
+
+	err = bt_br_set_discoverable(enable, limited);
 	if (err) {
-		shell_print(sh, "BR/EDR set/reset discoverable failed "
-			    "(err %d)", err);
+		shell_print(sh, "BR/EDR set/reset discoverable failed (err %d)", err);
 		return -ENOEXEC;
 	}
 
@@ -322,8 +657,7 @@ static int cmd_discoverable(const struct shell *sh,
 	return 0;
 }
 
-static int cmd_connectable(const struct shell *sh,
-			   size_t argc, char *argv[])
+static int cmd_connectable(const struct shell *sh, size_t argc, char *argv[])
 {
 	int err;
 	const char *action;
@@ -340,8 +674,7 @@ static int cmd_connectable(const struct shell *sh,
 	}
 
 	if (err) {
-		shell_print(sh, "BR/EDR set/rest connectable failed "
-			    "(err %d)", err);
+		shell_print(sh, "BR/EDR set/rest connectable failed (err %d)", err);
 		return -ENOEXEC;
 	}
 
@@ -369,8 +702,7 @@ static int cmd_oob(const struct shell *sh, size_t argc, char *argv[])
 	return 0;
 }
 
-static uint8_t sdp_hfp_ag_user(struct bt_conn *conn,
-			       struct bt_sdp_client_result *result,
+static uint8_t sdp_hfp_ag_user(struct bt_conn *conn, struct bt_sdp_client_result *result,
 			       const struct bt_sdp_discover_params *params)
 {
 	char addr[BT_ADDR_STR_LEN];
@@ -381,33 +713,80 @@ static uint8_t sdp_hfp_ag_user(struct bt_conn *conn,
 	conn_addr_str(conn, addr, sizeof(addr));
 
 	if (result && result->resp_buf) {
-		shell_print(ctx_shell, "SDP HFPAG data@%p (len %u) hint %u from"
-			    " remote %s", result->resp_buf,
-			    result->resp_buf->len, result->next_record_hint,
-			    addr);
+		bt_shell_print("SDP HFPAG data@%p (len %u) hint %u from remote %s",
+			       result->resp_buf, result->resp_buf->len, result->next_record_hint,
+			       addr);
 
 		/*
 		 * Focus to get BT_SDP_ATTR_PROTO_DESC_LIST attribute item to
 		 * get HFPAG Server Channel Number operating on RFCOMM protocol.
 		 */
-		err = bt_sdp_get_proto_param(result->resp_buf,
-					     BT_SDP_PROTO_RFCOMM, &param);
+		err = bt_sdp_get_proto_param(result->resp_buf, BT_SDP_PROTO_RFCOMM, &param);
+		if (err < 0) {
+			bt_shell_error("Error getting Server CN, err %d", err);
+			goto done;
+		}
+		bt_shell_print("HFPAG Server CN param 0x%04x", param);
+
+		err = bt_sdp_get_profile_version(result->resp_buf, BT_SDP_HANDSFREE_SVCLASS,
+						 &version);
+		if (err < 0) {
+			bt_shell_error("Error getting profile version, err %d", err);
+			goto done;
+		}
+		bt_shell_print("HFP version param 0x%04x", version);
+
+		/*
+		 * Focus to get BT_SDP_ATTR_SUPPORTED_FEATURES attribute item to
+		 * get profile Supported Features mask.
+		 */
+		err = bt_sdp_get_features(result->resp_buf, &features);
+		if (err < 0) {
+			bt_shell_error("Error getting HFPAG Features, err %d", err);
+			goto done;
+		}
+		bt_shell_print("HFPAG Supported Features param 0x%04x", features);
+	} else {
+		bt_shell_print("No SDP HFPAG data from remote %s", addr);
+	}
+done:
+	return BT_SDP_DISCOVER_UUID_CONTINUE;
+}
+
+static uint8_t sdp_hfp_hf_user(struct bt_conn *conn,
+			       struct bt_sdp_client_result *result,
+			       const struct bt_sdp_discover_params *params)
+{
+	char addr[BT_ADDR_STR_LEN];
+	uint16_t param, version;
+	uint16_t features;
+	int err;
+
+	conn_addr_str(conn, addr, sizeof(addr));
+
+	if (result && result->resp_buf) {
+		bt_shell_print("SDP HFPHF data@%p (len %u) hint %u from remote %s",
+			       result->resp_buf, result->resp_buf->len, result->next_record_hint,
+			       addr);
+
+		/*
+		 * Focus to get BT_SDP_ATTR_PROTO_DESC_LIST attribute item to
+		 * get HFPHF Server Channel Number operating on RFCOMM protocol.
+		 */
+		err = bt_sdp_get_proto_param(result->resp_buf, BT_SDP_PROTO_RFCOMM, &param);
 		if (err < 0) {
-			shell_error(ctx_shell, "Error getting Server CN, "
-				    "err %d", err);
+			bt_shell_error("Error getting Server CN, err %d", err);
 			goto done;
 		}
-		shell_print(ctx_shell, "HFPAG Server CN param 0x%04x", param);
+		bt_shell_print("HFPHF Server CN param 0x%04x", param);
 
-		err = bt_sdp_get_profile_version(result->resp_buf,
-						 BT_SDP_HANDSFREE_SVCLASS,
+		err = bt_sdp_get_profile_version(result->resp_buf, BT_SDP_HANDSFREE_SVCLASS,
 						 &version);
 		if (err < 0) {
-			shell_error(ctx_shell, "Error getting profile version, "
-				    "err %d", err);
+			bt_shell_error("Error getting profile version, err %d", err);
 			goto done;
 		}
-		shell_print(ctx_shell, "HFP version param 0x%04x", version);
+		bt_shell_print("HFP version param 0x%04x", version);
 
 		/*
 		 * Focus to get BT_SDP_ATTR_SUPPORTED_FEATURES attribute item to
@@ -415,22 +794,18 @@ static uint8_t sdp_hfp_ag_user(struct bt_conn *conn,
 		 */
 		err = bt_sdp_get_features(result->resp_buf, &features);
 		if (err < 0) {
-			shell_error(ctx_shell, "Error getting HFPAG Features, "
-				    "err %d", err);
+			bt_shell_error("Error getting HFPHF Features, err %d", err);
 			goto done;
 		}
-		shell_print(ctx_shell, "HFPAG Supported Features param 0x%04x",
-		      features);
+		bt_shell_print("HFPHF Supported Features param 0x%04x", features);
 	} else {
-		shell_print(ctx_shell, "No SDP HFPAG data from remote %s",
-			    addr);
+		bt_shell_print("No SDP HFPHF data from remote %s", addr);
 	}
 done:
 	return BT_SDP_DISCOVER_UUID_CONTINUE;
 }
 
-static uint8_t sdp_a2src_user(struct bt_conn *conn,
-			      struct bt_sdp_client_result *result,
+static uint8_t sdp_a2src_user(struct bt_conn *conn, struct bt_sdp_client_result *result,
 			      const struct bt_sdp_discover_params *params)
 {
 	char addr[BT_ADDR_STR_LEN];
@@ -441,39 +816,33 @@ static uint8_t sdp_a2src_user(struct bt_conn *conn,
 	conn_addr_str(conn, addr, sizeof(addr));
 
 	if (result && result->resp_buf) {
-		shell_print(ctx_shell, "SDP A2SRC data@%p (len %u) hint %u from"
-			    " remote %s", result->resp_buf,
-			    result->resp_buf->len, result->next_record_hint,
-			    addr);
+		bt_shell_print("SDP A2SRC data@%p (len %u) hint %u from remote %s",
+			       result->resp_buf, result->resp_buf->len, result->next_record_hint,
+			       addr);
 
 		/*
 		 * Focus to get BT_SDP_ATTR_PROTO_DESC_LIST attribute item to
 		 * get A2SRC Server PSM Number.
 		 */
-		err = bt_sdp_get_proto_param(result->resp_buf,
-					     BT_SDP_PROTO_L2CAP, &param);
+		err = bt_sdp_get_proto_param(result->resp_buf, BT_SDP_PROTO_L2CAP, &param);
 		if (err < 0) {
-			shell_error(ctx_shell, "A2SRC PSM Number not found, "
-				    "err %d", err);
+			bt_shell_error("A2SRC PSM Number not found, err %d", err);
 			goto done;
 		}
 
-		shell_print(ctx_shell, "A2SRC Server PSM Number param 0x%04x",
-			    param);
+		bt_shell_print("A2SRC Server PSM Number param 0x%04x", param);
 
 		/*
 		 * Focus to get BT_SDP_ATTR_PROFILE_DESC_LIST attribute item to
 		 * get profile version number.
 		 */
-		err = bt_sdp_get_profile_version(result->resp_buf,
-						 BT_SDP_ADVANCED_AUDIO_SVCLASS,
+		err = bt_sdp_get_profile_version(result->resp_buf, BT_SDP_ADVANCED_AUDIO_SVCLASS,
 						 &version);
 		if (err < 0) {
-			shell_error(ctx_shell, "A2SRC version not found, "
-				    "err %d", err);
+			bt_shell_error("A2SRC version not found, err %d", err);
 			goto done;
 		}
-		shell_print(ctx_shell, "A2SRC version param 0x%04x", version);
+		bt_shell_print("A2SRC version param 0x%04x", version);
 
 		/*
 		 * Focus to get BT_SDP_ATTR_SUPPORTED_FEATURES attribute item to
@@ -481,15 +850,12 @@ static uint8_t sdp_a2src_user(struct bt_conn *conn,
 		 */
 		err = bt_sdp_get_features(result->resp_buf, &features);
 		if (err < 0) {
-			shell_error(ctx_shell, "A2SRC Features not found, "
-				    "err %d", err);
+			bt_shell_error("A2SRC Features not found, err %d", err);
 			goto done;
 		}
-		shell_print(ctx_shell, "A2SRC Supported Features param 0x%04x",
-		      features);
+		bt_shell_print("A2SRC Supported Features param 0x%04x", features);
 	} else {
-		shell_print(ctx_shell, "No SDP A2SRC data from remote %s",
-			    addr);
+		bt_shell_print("No SDP A2SRC data from remote %s", addr);
 	}
 done:
 	return BT_SDP_DISCOVER_UUID_CONTINUE;
@@ -502,6 +868,13 @@ static struct bt_sdp_discover_params discov_hfpag = {
 	.pool = &sdp_client_pool,
 };
 
+static struct bt_sdp_discover_params discov_hfphf = {
+	.type = BT_SDP_DISCOVER_SERVICE_SEARCH_ATTR,
+	.uuid = BT_UUID_DECLARE_16(BT_SDP_HANDSFREE_SVCLASS),
+	.func = sdp_hfp_hf_user,
+	.pool = &sdp_client_pool,
+};
+
 static struct bt_sdp_discover_params discov_a2src = {
 	.type = BT_SDP_DISCOVER_SERVICE_SEARCH_ATTR,
 	.uuid = BT_UUID_DECLARE_16(BT_SDP_AUDIO_SOURCE_SVCLASS),
@@ -511,8 +884,7 @@ static struct bt_sdp_discover_params discov_a2src = {
 
 static struct bt_sdp_discover_params discov;
 
-static int cmd_sdp_find_record(const struct shell *sh,
-			       size_t argc, char *argv[])
+static int cmd_sdp_find_record(const struct shell *sh, size_t argc, char *argv[])
 {
 	int err;
 	const char *action;
@@ -526,6 +898,8 @@ static int cmd_sdp_find_record(const struct shell *sh,
 
 	if (!strcmp(action, "HFPAG")) {
 		discov = discov_hfpag;
+	} else if (!strcmp(action, "HFPHF")) {
+		discov = discov_hfphf;
 	} else if (!strcmp(action, "A2SRC")) {
 		discov = discov_a2src;
 	} else {
@@ -546,24 +920,60 @@ static int cmd_sdp_find_record(const struct shell *sh,
 	return 0;
 }
 
-#define HELP_NONE "[none]"
-#define HELP_ADDR_LE "<address: XX:XX:XX:XX:XX:XX> <type: (public|random)>"
+static void bond_info(const struct bt_br_bond_info *info, void *user_data)
+{
+	char addr[BT_ADDR_STR_LEN];
+	int *bond_count = user_data;
 
-SHELL_STATIC_SUBCMD_SET_CREATE(br_cmds,
-	SHELL_CMD_ARG(auth-pincode, NULL, "<pincode>", cmd_auth_pincode, 2, 0),
-	SHELL_CMD_ARG(connect, NULL, "<address>", cmd_connect, 2, 0),
-	SHELL_CMD_ARG(discovery, NULL,
-		      "<value: on, off> [length: 1-48] [mode: limited]",
-		      cmd_discovery, 2, 2),
-	SHELL_CMD_ARG(iscan, NULL, "<value: on, off>", cmd_discoverable, 2, 0),
-	SHELL_CMD_ARG(l2cap-register, NULL, "<psm>", cmd_l2cap_register, 2, 0),
-	SHELL_CMD_ARG(oob, NULL, NULL, cmd_oob, 1, 0),
-	SHELL_CMD_ARG(pscan, NULL, "<value: on, off>", cmd_connectable, 2, 0),
-	SHELL_CMD_ARG(sdp-find, NULL, "<HFPAG>", cmd_sdp_find_record, 2, 0),
-	SHELL_SUBCMD_SET_END
-);
+	bt_addr_to_str(&info->addr, addr, sizeof(addr));
+	bt_shell_print("Remote Identity: %s", addr);
+	(*bond_count)++;
+}
+
+static int cmd_bonds(const struct shell *sh, size_t argc, char *argv[])
+{
+	int bond_count = 0;
+
+	shell_print(sh, "Bonded devices:");
+	bt_br_foreach_bond(bond_info, &bond_count);
+	shell_print(sh, "Total %d", bond_count);
+
+	return 0;
+}
 
-static int cmd_br(const struct shell *sh, size_t argc, char **argv)
+static int cmd_clear(const struct shell *sh, size_t argc, char *argv[])
+{
+	bt_addr_t addr;
+	int err;
+
+	if (strcmp(argv[1], "all") == 0) {
+		err = bt_br_unpair(NULL);
+		if (err) {
+			shell_error(sh, "Failed to clear pairings (err %d)", err);
+			return err;
+		}
+
+		shell_print(sh, "Pairings successfully cleared");
+		return 0;
+	}
+
+	err = bt_addr_from_str(argv[1], &addr);
+	if (err) {
+		shell_print(sh, "Invalid address");
+		return err;
+	}
+
+	err = bt_br_unpair(&addr);
+	if (err) {
+		shell_error(sh, "Failed to clear pairing (err %d)", err);
+	} else {
+		shell_print(sh, "Pairing successfully cleared");
+	}
+
+	return err;
+}
+
+static int cmd_default_handler(const struct shell *sh, size_t argc, char **argv)
 {
 	if (argc == 1) {
 		shell_help(sh);
@@ -572,8 +982,50 @@ static int cmd_br(const struct shell *sh, size_t argc, char **argv)
 
 	shell_error(sh, "%s unknown parameter: %s", argv[0], argv[1]);
 
-	return -ENOEXEC;
+	return -EINVAL;
 }
 
-SHELL_CMD_ARG_REGISTER(br, &br_cmds, "Bluetooth BR/EDR shell commands", cmd_br,
-		       1, 1);
+#define HELP_NONE "[none]"
+#define HELP_ADDR "<address: XX:XX:XX:XX:XX:XX>"
+#define HELP_REG                                                      \
+	"<psm> <mode: none, ret, fc, eret, stream> [hold_credit] "    \
+	"[mode_optional] [extended_control]"
+
+#define HELP_CONN                                                     \
+	"<psm> <mode: none, ret, fc, eret, stream> [hold_credit] "    \
+	"[mode_optional] [extended_control]"
+
+SHELL_STATIC_SUBCMD_SET_CREATE(l2cap_cmds,
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	SHELL_CMD_ARG(register, NULL, HELP_REG, cmd_l2cap_register, 3, 3),
+	SHELL_CMD_ARG(connect, NULL, HELP_CONN, cmd_l2cap_connect, 3, 3),
+#else
+	SHELL_CMD_ARG(register, NULL, "<psm>", cmd_l2cap_register, 2, 0),
+	SHELL_CMD_ARG(connect, NULL, "<psm>", cmd_l2cap_connect, 2, 0),
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+	SHELL_CMD_ARG(disconnect, NULL, HELP_NONE, cmd_l2cap_disconnect, 1, 0),
+	SHELL_CMD_ARG(send, NULL, "[number of packets] [length of packet(s)]",
+		      cmd_l2cap_send, 1, 2),
+#if defined(CONFIG_BT_L2CAP_RET_FC)
+	SHELL_CMD_ARG(credits, NULL, HELP_NONE, cmd_l2cap_credits, 1, 0),
+#endif /* CONFIG_BT_L2CAP_RET_FC */
+	SHELL_SUBCMD_SET_END
+);
+
+SHELL_STATIC_SUBCMD_SET_CREATE(br_cmds,
+	SHELL_CMD_ARG(auth-pincode, NULL, "<pincode>", cmd_auth_pincode, 2, 0),
+	SHELL_CMD_ARG(connect, NULL, "<address>", cmd_connect, 2, 0),
+	SHELL_CMD_ARG(bonds, NULL, HELP_NONE, cmd_bonds, 1, 0),
+	SHELL_CMD_ARG(clear, NULL, "[all] ["HELP_ADDR"]", cmd_clear, 2, 0),
+	SHELL_CMD_ARG(discovery, NULL, "<value: on, off> [length: 1-48] [mode: limited]",
+		      cmd_discovery, 2, 2),
+	SHELL_CMD_ARG(iscan, NULL, "<value: on, off> [mode: limited]",
+		      cmd_discoverable, 2, 1),
+	SHELL_CMD(l2cap, &l2cap_cmds, HELP_NONE, cmd_default_handler),
+	SHELL_CMD_ARG(oob, NULL, NULL, cmd_oob, 1, 0),
+	SHELL_CMD_ARG(pscan, NULL, "<value: on, off>", cmd_connectable, 2, 0),
+	SHELL_CMD_ARG(sdp-find, NULL, "<HFPAG, HFPHF>", cmd_sdp_find_record, 2, 0),
+	SHELL_SUBCMD_SET_END
+);
+
+SHELL_CMD_ARG_REGISTER(br, &br_cmds, "Bluetooth BR/EDR shell commands", cmd_default_handler, 1, 1);
diff --git a/subsys/bluetooth/host/classic/shell/hfp.c b/subsys/bluetooth/host/classic/shell/hfp.c
new file mode 100644
index 00000000000..58cd44451ee
--- /dev/null
+++ b/subsys/bluetooth/host/classic/shell/hfp.c
@@ -0,0 +1,1948 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <zephyr/types.h>
+#include <stddef.h>
+#include <stdlib.h>
+#include <string.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/kernel.h>
+
+#include <zephyr/settings/settings.h>
+
+#include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/l2cap.h>
+#include <zephyr/bluetooth/classic/hfp_hf.h>
+#include <zephyr/bluetooth/classic/hfp_ag.h>
+
+#include <zephyr/shell/shell.h>
+
+#include "host/shell/bt.h"
+#include "common/bt_shell_private.h"
+
+#define HELP_NONE "[none]"
+
+extern struct bt_conn *default_conn;
+
+#if defined(CONFIG_BT_HFP_HF)
+
+struct bt_conn *hf_conn;
+struct bt_hfp_hf *hfp_hf;
+struct bt_conn *hf_sco_conn;
+static struct bt_hfp_hf_call *hfp_hf_call[CONFIG_BT_HFP_HF_MAX_CALLS];
+
+static void hf_add_a_call(struct bt_hfp_hf_call *call)
+{
+	ARRAY_FOR_EACH(hfp_hf_call, i) {
+		if (!hfp_hf_call[i]) {
+			hfp_hf_call[i] = call;
+			return;
+		}
+	}
+}
+
+static void hf_remove_a_call(struct bt_hfp_hf_call *call)
+{
+	ARRAY_FOR_EACH(hfp_hf_call, i) {
+		if (call == hfp_hf_call[i]) {
+			hfp_hf_call[i] = NULL;
+			return;
+		}
+	}
+}
+
+static void hf_remove_calls(void)
+{
+	ARRAY_FOR_EACH(hfp_hf_call, i) {
+		if (hfp_hf_call[i] != NULL) {
+			hfp_hf_call[i] = NULL;
+		}
+	}
+}
+
+static void hf_connected(struct bt_conn *conn, struct bt_hfp_hf *hf)
+{
+	hf_conn = conn;
+	hfp_hf = hf;
+	bt_shell_print("HF connected");
+}
+
+static void hf_disconnected(struct bt_hfp_hf *hf)
+{
+	hf_conn = NULL;
+	hfp_hf = NULL;
+	hf_remove_calls();
+	bt_shell_print("HF disconnected");
+}
+
+static void hf_sco_connected(struct bt_hfp_hf *hf, struct bt_conn *sco_conn)
+{
+	bt_shell_print("HF SCO connected %p", sco_conn);
+
+	if (hf_sco_conn != NULL) {
+		bt_shell_warn("HF SCO conn %p exists", hf_sco_conn);
+		return;
+	}
+
+	hf_sco_conn = bt_conn_ref(sco_conn);
+}
+
+static void hf_sco_disconnected(struct bt_conn *sco_conn, uint8_t reason)
+{
+	bt_shell_print("HF SCO disconnected %p (reason %u)", sco_conn, reason);
+
+	if (hf_sco_conn == sco_conn) {
+		bt_conn_unref(hf_sco_conn);
+		hf_sco_conn = NULL;
+	} else {
+		bt_shell_warn("Unknown SCO disconnected (%p != %p)", hf_sco_conn, sco_conn);
+	}
+}
+
+void hf_service(struct bt_hfp_hf *hf, uint32_t value)
+{
+	bt_shell_print("HF service %d", value);
+}
+
+void hf_outgoing(struct bt_hfp_hf *hf, struct bt_hfp_hf_call *call)
+{
+	hf_add_a_call(call);
+	bt_shell_print("HF call %p outgoing", call);
+}
+
+void hf_remote_ringing(struct bt_hfp_hf_call *call)
+{
+	bt_shell_print("HF remote call %p start ringing", call);
+}
+
+void hf_incoming(struct bt_hfp_hf *hf, struct bt_hfp_hf_call *call)
+{
+	hf_add_a_call(call);
+	bt_shell_print("HF call %p incoming", call);
+}
+
+void hf_incoming_held(struct bt_hfp_hf_call *call)
+{
+	bt_shell_print("HF call %p is held", call);
+}
+
+void hf_accept(struct bt_hfp_hf_call *call)
+{
+	bt_shell_print("HF call %p accepted", call);
+}
+
+void hf_reject(struct bt_hfp_hf_call *call)
+{
+	hf_remove_a_call(call);
+	bt_shell_print("HF call %p rejected", call);
+}
+
+void hf_terminate(struct bt_hfp_hf_call *call)
+{
+	hf_remove_a_call(call);
+	bt_shell_print("HF call %p terminated", call);
+}
+
+void hf_held(struct bt_hfp_hf_call *call)
+{
+	bt_shell_print("hf call %p held", call);
+}
+
+void hf_retrieve(struct bt_hfp_hf_call *call)
+{
+	bt_shell_print("hf call %p retrieve", call);
+}
+
+void hf_signal(struct bt_hfp_hf *hf, uint32_t value)
+{
+	bt_shell_print("HF signal %d", value);
+}
+
+void hf_roam(struct bt_hfp_hf *hf, uint32_t value)
+{
+	bt_shell_print("HF roam %d", value);
+}
+
+void hf_battery(struct bt_hfp_hf *hf, uint32_t value)
+{
+	bt_shell_print("HF battery %d", value);
+}
+
+void hf_ring_indication(struct bt_hfp_hf_call *call)
+{
+	bt_shell_print("HF call %p ring", call);
+}
+
+void hf_dialing(struct bt_hfp_hf *hf, int err)
+{
+	bt_shell_print("HF start dialing call: err %d", err);
+}
+
+#if defined(CONFIG_BT_HFP_HF_CLI)
+void hf_clip(struct bt_hfp_hf_call *call, char *number, uint8_t type)
+{
+	bt_shell_print("HF call %p CLIP %s %d", call, number, type);
+}
+#endif /* CONFIG_BT_HFP_HF_CLI */
+
+#if defined(CONFIG_BT_HFP_HF_VOLUME)
+static void hf_vgm(struct bt_hfp_hf *hf, uint8_t gain)
+{
+	bt_shell_print("HF VGM %d", gain);
+}
+
+static void hf_vgs(struct bt_hfp_hf *hf, uint8_t gain)
+{
+	bt_shell_print("HF VGS %d", gain);
+}
+#endif /* CONFIG_BT_HFP_HF_VOLUME */
+
+static void hf_inband_ring(struct bt_hfp_hf *hf, bool inband)
+{
+	bt_shell_print("HF ring: %s", inband ? "in-band" : "no in-hand");
+}
+
+static void hf_operator(struct bt_hfp_hf *hf, uint8_t mode, uint8_t format, char *operator)
+{
+	bt_shell_print("HF mode %d, format %d, operator %s", mode, format, operator);
+}
+
+#if defined(CONFIG_BT_HFP_HF_CODEC_NEG)
+static void hf_codec_negotiate(struct bt_hfp_hf *hf, uint8_t id)
+{
+	bt_shell_print("codec negotiation: %d", id);
+}
+#endif /* CONFIG_BT_HFP_HF_CODEC_NEG */
+
+#if defined(CONFIG_BT_HFP_HF_ECNR)
+static void hf_ecnr_turn_off(struct bt_hfp_hf *hf, int err)
+{
+	bt_shell_print("Turn off ECNR: %d", err);
+}
+#endif /* CONFIG_BT_HFP_HF_ECNR */
+
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+static void hf_call_waiting(struct bt_hfp_hf_call *call, char *number, uint8_t type)
+{
+	bt_shell_print("3way call %p waiting. number %s type %d", call, number, type);
+}
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+
+#if defined(CONFIG_BT_HFP_HF_VOICE_RECG)
+void hf_voice_recognition(struct bt_hfp_hf *hf, bool activate)
+{
+	bt_shell_print("Voice recognition %s", activate ? "activate" : "deactivate");
+}
+
+#if defined(CONFIG_BT_HFP_HF_ENH_VOICE_RECG)
+void hf_vre_state(struct bt_hfp_hf *hf, uint8_t state)
+{
+	bt_shell_print("Voice recognition engine state %d", state);
+}
+#endif /* CONFIG_BT_HFP_HF_ENH_VOICE_RECG */
+
+#if defined(CONFIG_BT_HFP_HF_VOICE_RECG_TEXT)
+void hf_textual_representation(struct bt_hfp_hf *hf, char *id, uint8_t type, uint8_t operation,
+			       char *text)
+{
+	bt_shell_print("Text id %s, type %d, operation %d, string %s", id, type, operation, text);
+}
+#endif /* CONFIG_BT_HFP_HF_VOICE_RECG_TEXT */
+#endif /* CONFIG_BT_HFP_HF_VOICE_RECG */
+
+void hf_request_phone_number(struct bt_hfp_hf *hf, const char *number)
+{
+	if (number) {
+		bt_shell_print("Requested phone number %s", number);
+	} else {
+		bt_shell_print("Failed to request phone number");
+	}
+}
+
+void hf_subscriber_number(struct bt_hfp_hf *hf, const char *number, uint8_t type, uint8_t service)
+{
+	bt_shell_print("Subscriber number %s, type %d, service %d", number, type, service);
+}
+
+static struct bt_hfp_hf_cb hf_cb = {
+	.connected = hf_connected,
+	.disconnected = hf_disconnected,
+	.sco_connected = hf_sco_connected,
+	.sco_disconnected = hf_sco_disconnected,
+	.service = hf_service,
+	.outgoing = hf_outgoing,
+	.remote_ringing = hf_remote_ringing,
+	.incoming = hf_incoming,
+	.incoming_held = hf_incoming_held,
+	.accept = hf_accept,
+	.reject = hf_reject,
+	.terminate = hf_terminate,
+	.held = hf_held,
+	.retrieve = hf_retrieve,
+	.signal = hf_signal,
+	.roam = hf_roam,
+	.battery = hf_battery,
+	.ring_indication = hf_ring_indication,
+	.dialing = hf_dialing,
+#if defined(CONFIG_BT_HFP_HF_CLI)
+	.clip = hf_clip,
+#endif /* CONFIG_BT_HFP_HF_CLI */
+#if defined(CONFIG_BT_HFP_HF_VOLUME)
+	.vgm = hf_vgm,
+	.vgs = hf_vgs,
+#endif /* CONFIG_BT_HFP_HF_VOLUME */
+	.inband_ring = hf_inband_ring,
+	.operator = hf_operator,
+#if defined(CONFIG_BT_HFP_HF_CODEC_NEG)
+	.codec_negotiate = hf_codec_negotiate,
+#endif /* CONFIG_BT_HFP_HF_CODEC_NEG */
+#if defined(CONFIG_BT_HFP_HF_ECNR)
+	.ecnr_turn_off = hf_ecnr_turn_off,
+#endif /* CONFIG_BT_HFP_HF_ECNR */
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+	.call_waiting = hf_call_waiting,
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+#if defined(CONFIG_BT_HFP_HF_VOICE_RECG)
+	.voice_recognition = hf_voice_recognition,
+#if defined(CONFIG_BT_HFP_HF_ENH_VOICE_RECG)
+	.vre_state = hf_vre_state,
+#endif /* CONFIG_BT_HFP_HF_ENH_VOICE_RECG */
+#if defined(CONFIG_BT_HFP_HF_VOICE_RECG_TEXT)
+	.textual_representation = hf_textual_representation,
+#endif /* CONFIG_BT_HFP_HF_VOICE_RECG_TEXT */
+#endif /* CONFIG_BT_HFP_HF_VOICE_RECG */
+	.request_phone_number = hf_request_phone_number,
+	.subscriber_number = hf_subscriber_number,
+};
+
+static int cmd_reg_enable(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_hf_register(&hf_cb);
+	if (err) {
+		shell_error(sh, "Callback register failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_connect(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	struct bt_hfp_hf *hf;
+	uint8_t channel;
+
+	channel = atoi(argv[1]);
+
+	err = bt_hfp_hf_connect(default_conn, &hf, channel);
+	if (err) {
+		shell_error(sh, "Connect failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_disconnect(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_hf_disconnect(hfp_hf);
+	if (err) {
+		shell_error(sh, "Disconnect failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_sco_disconnect(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_conn_disconnect(hf_sco_conn, BT_HCI_ERR_REMOTE_USER_TERM_CONN);
+	if (err) {
+		shell_error(sh, "Disconnect failed: %d", err);
+	}
+
+	return err;
+}
+
+#if defined(CONFIG_BT_HFP_HF_CLI)
+static int cmd_cli_enable(const struct shell *sh, size_t argc, char **argv)
+{
+	const char *action = argv[1];
+	bool enable;
+	int err;
+
+	if (strcmp(action, "enable") == 0) {
+		enable = true;
+	} else if (strcmp(action, "disable") == 0) {
+		enable = false;
+	} else {
+		shell_error(sh, "Invalid option.");
+		return -ENOEXEC;
+	}
+
+	err = bt_hfp_hf_cli(hfp_hf, enable);
+	if (err) {
+		shell_error(sh, "Fail to send AT+CLIP=%d (err %d)", enable, err);
+		return -ENOEXEC;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_BT_HFP_HF_CLI */
+
+#if defined(CONFIG_BT_HFP_HF_VOLUME)
+static int cmd_vgm_enable(const struct shell *sh, size_t argc, char **argv)
+{
+	uint32_t gain;
+	int err;
+
+	gain = atoi(argv[1]);
+
+	err = bt_hfp_hf_vgm(hfp_hf, gain);
+	if (err) {
+		shell_error(sh, "Fail to send AT+VGM=%d (err %d)", gain, err);
+	}
+
+	return err;
+}
+
+static int cmd_vgs_enable(const struct shell *sh, size_t argc, char **argv)
+{
+	uint32_t gain;
+	int err;
+
+	gain = atoi(argv[1]);
+
+	err = bt_hfp_hf_vgs(hfp_hf, gain);
+	if (err) {
+		shell_error(sh, "Fail to send AT+VGS=%d (err %d)", gain, err);
+	}
+
+	return err;
+}
+#endif /* CONFIG_BT_HFP_HF_VOLUME */
+
+static int cmd_operator(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_hf_get_operator(hfp_hf);
+	if (err) {
+		shell_error(sh, "Failed to read network operator: %d", err);
+	}
+
+	return err;
+}
+
+#if defined(CONFIG_BT_HFP_HF_CODEC_NEG)
+static int cmd_audio_connect(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_hf_audio_connect(hfp_hf);
+	if (err) {
+		shell_error(sh, "Failed to start audio connection procedure: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_select_codec(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	uint8_t codec_id;
+
+	codec_id = atoi(argv[1]);
+
+	err = bt_hfp_hf_select_codec(hfp_hf, codec_id);
+	if (err) {
+		shell_error(sh, "Failed to select codec id: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_set_codecs(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	uint8_t codec_ids;
+
+	codec_ids = atoi(argv[1]);
+
+	err = bt_hfp_hf_set_codecs(hfp_hf, codec_ids);
+	if (err) {
+		shell_error(sh, "Failed to set codecs: %d", err);
+	}
+
+	return err;
+}
+#endif /* CONFIG_BT_HFP_HF_CODEC_NEG */
+
+static int cmd_accept(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int index;
+
+	index = atoi(argv[1]);
+	if ((index >= ((int)ARRAY_SIZE(hfp_hf_call))) || !hfp_hf_call[index]) {
+		shell_error(sh, "Invalid call index: %d", index);
+		return -EINVAL;
+	}
+
+	err = bt_hfp_hf_accept(hfp_hf_call[index]);
+	if (err) {
+		shell_error(sh, "Failed to accept call: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_reject(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int index;
+
+	index = atoi(argv[1]);
+	if ((index >= ((int)ARRAY_SIZE(hfp_hf_call))) || !hfp_hf_call[index]) {
+		shell_error(sh, "Invalid call index: %d", index);
+		return -EINVAL;
+	}
+
+	err = bt_hfp_hf_reject(hfp_hf_call[index]);
+	if (err) {
+		shell_error(sh, "Failed to reject call: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_terminate(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int index;
+
+	index = atoi(argv[1]);
+	if ((index >= ((int)ARRAY_SIZE(hfp_hf_call))) || !hfp_hf_call[index]) {
+		shell_error(sh, "Invalid call index: %d", index);
+		return -EINVAL;
+	}
+
+	err = bt_hfp_hf_terminate(hfp_hf_call[index]);
+	if (err) {
+		shell_error(sh, "Failed to terminate call: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_hold_incoming(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int index;
+
+	index = atoi(argv[1]);
+	if ((index >= ((int)ARRAY_SIZE(hfp_hf_call))) || !hfp_hf_call[index]) {
+		shell_error(sh, "Invalid call index: %d", index);
+		return -EINVAL;
+	}
+
+	err = bt_hfp_hf_hold_incoming(hfp_hf_call[index]);
+	if (err) {
+		shell_error(sh, "Failed to put incoming call on hold: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_query_respond_hold_status(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_hf_query_respond_hold_status(hfp_hf);
+	if (err) {
+		shell_error(sh, "Failed to query respond and hold status: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_number_call(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_hf_number_call(hfp_hf, argv[1]);
+	if (err) {
+		shell_error(sh, "Failed to start phone number call: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_memory_dial(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_hf_memory_dial(hfp_hf, argv[1]);
+	if (err) {
+		shell_error(sh, "Failed to memory dial call: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_redial(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_hf_redial(hfp_hf);
+	if (err) {
+		shell_error(sh, "Failed to redial call: %d", err);
+	}
+
+	return err;
+}
+
+#if defined(CONFIG_BT_HFP_HF_ECNR)
+static int cmd_turn_off_ecnr(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_hf_turn_off_ecnr(hfp_hf);
+	if (err) {
+		shell_error(sh, "Failed to turn off ecnr: %d", err);
+	}
+
+	return err;
+}
+#endif /* CONFIG_BT_HFP_HF_ECNR */
+
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+static int cmd_call_waiting_notify(const struct shell *sh, size_t argc, char **argv)
+{
+	const char *action = argv[1];
+	bool enable;
+	int err;
+
+	action = argv[1];
+
+	if (strcmp(action, "enable") == 0) {
+		enable = true;
+	} else if (strcmp(action, "disable") == 0) {
+		enable = false;
+	} else {
+		shell_error(sh, "Invalid option.");
+		return -ENOEXEC;
+	}
+
+	err = bt_hfp_hf_call_waiting_notify(hfp_hf, enable);
+	if (err) {
+		shell_error(sh, "Failed to set call waiting notify: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_release_all_held(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_hf_release_all_held(hfp_hf);
+	if (err) {
+		shell_error(sh, "Failed to release all held: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_set_udub(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_hf_set_udub(hfp_hf);
+	if (err) {
+		shell_error(sh, "Failed to reject waiting call: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_release_active_accept_other(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_hf_release_active_accept_other(hfp_hf);
+	if (err) {
+		shell_error(sh, "Failed to release active calls and accept other call: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_hold_active_accept_other(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_hf_hold_active_accept_other(hfp_hf);
+	if (err) {
+		shell_error(sh, "Failed to hold all active calls and accept other call: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_join_conversation(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_hf_join_conversation(hfp_hf);
+	if (err) {
+		shell_error(sh, "Failed to join the conversation: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_explicit_call_transfer(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_hf_explicit_call_transfer(hfp_hf);
+	if (err) {
+		shell_error(sh, "Failed to explicit call transfer: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_release_specified_call(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int index;
+
+	index = atoi(argv[1]);
+	if ((index >= ((int)ARRAY_SIZE(hfp_hf_call))) || !hfp_hf_call[index]) {
+		shell_error(sh, "Invalid call index: %d", index);
+		return -EINVAL;
+	}
+
+	err = bt_hfp_hf_release_specified_call(hfp_hf_call[index]);
+	if (err) {
+		shell_error(sh, "Failed to release specified call: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_private_consultation_mode(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int index;
+
+	index = atoi(argv[1]);
+	if ((index >= ((int)ARRAY_SIZE(hfp_hf_call))) || !hfp_hf_call[index]) {
+		shell_error(sh, "Invalid call index: %d", index);
+		return -EINVAL;
+	}
+
+	err = bt_hfp_hf_private_consultation_mode(hfp_hf_call[index]);
+	if (err) {
+		shell_error(sh, "Failed to set private consultation mode: %d", err);
+	}
+
+	return err;
+}
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+
+#if defined(CONFIG_BT_HFP_HF_VOICE_RECG)
+static int cmd_voice_recognition(const struct shell *sh, size_t argc, char **argv)
+{
+	const char *action;
+	bool activate;
+	int err;
+
+	action = argv[1];
+
+	if (strcmp(action, "activate") == 0) {
+		activate = true;
+	} else if (strcmp(action, "deactivate") == 0) {
+		activate = false;
+	} else {
+		shell_error(sh, "Invalid option.");
+		return -ENOEXEC;
+	}
+
+	err = bt_hfp_hf_voice_recognition(hfp_hf, activate);
+	if (err) {
+		shell_error(sh, "Failed to set voice recognition: %d", err);
+	}
+
+	return err;
+}
+
+#if defined(CONFIG_BT_HFP_HF_ENH_VOICE_RECG)
+static int cmd_ready_to_accept_audio(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_hf_ready_to_accept_audio(hfp_hf);
+	if (err) {
+		shell_error(sh, "Failed to send ready to accept audio notify: %d", err);
+	}
+
+	return err;
+}
+#endif /* CONFIG_BT_HFP_HF_ENH_VOICE_RECG */
+#endif /* CONFIG_BT_HFP_HF_VOICE_RECG */
+
+static int cmd_request_phone_number(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_hf_request_phone_number(hfp_hf);
+	if (err) {
+		shell_error(sh, "Failed to request phone number: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_transmit_dtmf_code(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int index;
+
+	index = atoi(argv[1]);
+	if ((index >= ((int)ARRAY_SIZE(hfp_hf_call))) || !hfp_hf_call[index]) {
+		shell_error(sh, "Invalid call index: %d", index);
+		return -EINVAL;
+	}
+
+	err = bt_hfp_hf_transmit_dtmf_code(hfp_hf_call[index], argv[2][0]);
+	if (err) {
+		shell_error(sh, "Failed to transmit DTMF Code: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_query_subscriber(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_hf_query_subscriber(hfp_hf);
+	if (err) {
+		shell_error(sh, "Failed to query subscriber: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_indicator_status(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	uint8_t status[4];
+	size_t len;
+
+	len = hex2bin(argv[1], strlen(argv[1]), status, sizeof(status));
+	if (len == 0) {
+		shell_error(sh, "Failed to parse status %s", argv[1]);
+		return -EINVAL;
+	}
+
+	err = bt_hfp_hf_indicator_status(hfp_hf, (uint32_t)status[0]);
+	if (err) {
+		shell_error(sh, "Failed to set AG indicator activated/deactivated status: %d", err);
+	}
+
+	return err;
+}
+
+#if defined(CONFIG_BT_HFP_HF_HF_INDICATOR_ENH_SAFETY)
+static int cmd_enhanced_safety(const struct shell *sh, size_t argc, char **argv)
+{
+	const char *action;
+	bool enable;
+	int err;
+
+	action = argv[1];
+
+	if (strcmp(action, "enable") == 0) {
+		enable = true;
+	} else if (strcmp(action, "disable") == 0) {
+		enable = false;
+	} else {
+		shell_error(sh, "Invalid option.");
+		return -ENOEXEC;
+	}
+
+	err = bt_hfp_hf_enhanced_safety(hfp_hf, enable);
+	if (err) {
+		shell_error(sh, "Failed to transfer enhanced safety status: %d", err);
+	}
+
+	return err;
+}
+#endif /* CONFIG_BT_HFP_HF_HF_INDICATOR_ENH_SAFETY */
+
+#if defined(CONFIG_BT_HFP_HF_HF_INDICATOR_BATTERY)
+static int cmd_battery(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int level;
+
+	level = atoi(argv[1]);
+
+	err = bt_hfp_hf_battery(hfp_hf, level);
+	if (err) {
+		shell_error(sh, "Failed to transfer battery level: %d", err);
+	}
+
+	return err;
+}
+#endif /* CONFIG_BT_HFP_HF_HF_INDICATOR_BATTERY */
+
+SHELL_STATIC_SUBCMD_SET_CREATE(hf_cmds,
+	SHELL_CMD_ARG(reg, NULL, HELP_NONE, cmd_reg_enable, 1, 0),
+	SHELL_CMD_ARG(connect, NULL, "<channel>", cmd_connect, 2, 0),
+	SHELL_CMD_ARG(disconnect, NULL, HELP_NONE, cmd_disconnect, 1, 0),
+	SHELL_CMD_ARG(sco_disconnect, NULL, HELP_NONE, cmd_sco_disconnect, 1, 0),
+#if defined(CONFIG_BT_HFP_HF_CLI)
+	SHELL_CMD_ARG(cli, NULL, "<enable/disable>", cmd_cli_enable, 2, 0),
+#endif /* CONFIG_BT_HFP_HF_CLI */
+#if defined(CONFIG_BT_HFP_HF_VOLUME)
+	SHELL_CMD_ARG(vgm, NULL, "<gain>", cmd_vgm_enable, 2, 0),
+	SHELL_CMD_ARG(vgs, NULL, "<gain>", cmd_vgs_enable, 2, 0),
+#endif /* CONFIG_BT_HFP_HF_VOLUME */
+	SHELL_CMD_ARG(operator, NULL, HELP_NONE, cmd_operator, 1, 0),
+#if defined(CONFIG_BT_HFP_HF_CODEC_NEG)
+	SHELL_CMD_ARG(audio_connect, NULL, HELP_NONE, cmd_audio_connect, 1, 0),
+	SHELL_CMD_ARG(select_codec, NULL, "Codec ID", cmd_select_codec, 2, 0),
+	SHELL_CMD_ARG(set_codecs, NULL, "Codec ID Map", cmd_set_codecs, 2, 0),
+#endif /* CONFIG_BT_HFP_HF_CODEC_NEG */
+	SHELL_CMD_ARG(accept, NULL, "<call index>", cmd_accept, 2, 0),
+	SHELL_CMD_ARG(reject, NULL, "<call index>", cmd_reject, 2, 0),
+	SHELL_CMD_ARG(terminate, NULL, "<call index>", cmd_terminate, 2, 0),
+	SHELL_CMD_ARG(hold_incoming, NULL, "<call index>", cmd_hold_incoming, 2, 0),
+	SHELL_CMD_ARG(query_respond_hold_status, NULL, HELP_NONE, cmd_query_respond_hold_status, 1,
+		      0),
+	SHELL_CMD_ARG(number_call, NULL, "<phone number>", cmd_number_call, 2, 0),
+	SHELL_CMD_ARG(memory_dial, NULL, "<memory location>", cmd_memory_dial, 2, 0),
+	SHELL_CMD_ARG(redial, NULL, HELP_NONE, cmd_redial, 1, 0),
+#if defined(CONFIG_BT_HFP_HF_ECNR)
+	SHELL_CMD_ARG(turn_off_ecnr, NULL, HELP_NONE, cmd_turn_off_ecnr, 1, 0),
+#endif /* CONFIG_BT_HFP_HF_ECNR */
+#if defined(CONFIG_BT_HFP_HF_3WAY_CALL)
+	SHELL_CMD_ARG(call_waiting_notify, NULL, "<enable/disable>", cmd_call_waiting_notify, 2, 0),
+	SHELL_CMD_ARG(release_all_held, NULL, HELP_NONE, cmd_release_all_held, 1, 0),
+	SHELL_CMD_ARG(set_udub, NULL, HELP_NONE, cmd_set_udub, 1, 0),
+	SHELL_CMD_ARG(release_active_accept_other, NULL, HELP_NONE, cmd_release_active_accept_other,
+		      1, 0),
+	SHELL_CMD_ARG(hold_active_accept_other, NULL, HELP_NONE, cmd_hold_active_accept_other, 1,
+		      0),
+	SHELL_CMD_ARG(join_conversation, NULL, HELP_NONE, cmd_join_conversation, 1, 0),
+	SHELL_CMD_ARG(explicit_call_transfer, NULL, HELP_NONE, cmd_explicit_call_transfer, 1, 0),
+	SHELL_CMD_ARG(release_specified_call, NULL, "<call index>", cmd_release_specified_call, 2,
+		      0),
+	SHELL_CMD_ARG(private_consultation_mode, NULL, "<call index>",
+		      cmd_private_consultation_mode, 2, 0),
+#endif /* CONFIG_BT_HFP_HF_3WAY_CALL */
+#if defined(CONFIG_BT_HFP_HF_VOICE_RECG)
+	SHELL_CMD_ARG(voice_recognition, NULL, "<activate/deactivate>", cmd_voice_recognition, 2,
+		      0),
+#if defined(CONFIG_BT_HFP_HF_ENH_VOICE_RECG)
+	SHELL_CMD_ARG(ready_to_accept_audio, NULL, HELP_NONE, cmd_ready_to_accept_audio, 1, 0),
+#endif /* CONFIG_BT_HFP_HF_ENH_VOICE_RECG */
+#endif /* CONFIG_BT_HFP_HF_VOICE_RECG */
+	SHELL_CMD_ARG(request_phone_number, NULL, HELP_NONE, cmd_request_phone_number, 1, 0),
+	SHELL_CMD_ARG(transmit_dtmf_code, NULL, "<call index> <code(set 0-9, #,*,A-D)>",
+		      cmd_transmit_dtmf_code, 3, 0),
+	SHELL_CMD_ARG(query_subscriber, NULL, HELP_NONE, cmd_query_subscriber, 1, 0),
+	SHELL_CMD_ARG(indicator_status, NULL, "<Activate/deactivate AG indicators bitmap>",
+		      cmd_indicator_status, 2, 0),
+#if defined(CONFIG_BT_HFP_HF_HF_INDICATOR_ENH_SAFETY)
+	SHELL_CMD_ARG(enhanced_safety, NULL, "<enable/disable>", cmd_enhanced_safety, 2, 0),
+#endif /* CONFIG_BT_HFP_HF_HF_INDICATOR_ENH_SAFETY */
+#if defined(CONFIG_BT_HFP_HF_HF_INDICATOR_BATTERY)
+	SHELL_CMD_ARG(battery, NULL, "<level>", cmd_battery, 2, 0),
+#endif /* CONFIG_BT_HFP_HF_HF_INDICATOR_BATTERY */
+	SHELL_SUBCMD_SET_END
+);
+#endif /* CONFIG_BT_HFP_HF */
+
+#if defined(CONFIG_BT_HFP_AG)
+
+struct bt_hfp_ag *hfp_ag;
+struct bt_conn *hfp_ag_sco_conn;
+static struct bt_hfp_ag_call *hfp_ag_call[CONFIG_BT_HFP_AG_MAX_CALLS];
+
+static void ag_add_a_call(struct bt_hfp_ag_call *call)
+{
+	ARRAY_FOR_EACH(hfp_ag_call, i) {
+		if (!hfp_ag_call[i]) {
+			hfp_ag_call[i] = call;
+			return;
+		}
+	}
+}
+
+static void ag_remove_a_call(struct bt_hfp_ag_call *call)
+{
+	ARRAY_FOR_EACH(hfp_ag_call, i) {
+		if (call == hfp_ag_call[i]) {
+			hfp_ag_call[i] = NULL;
+			return;
+		}
+	}
+}
+
+static void ag_remove_calls(void)
+{
+	ARRAY_FOR_EACH(hfp_ag_call, i) {
+		if (hfp_ag_call[i] != NULL) {
+			hfp_ag_call[i] = NULL;
+		}
+	}
+}
+
+static void ag_connected(struct bt_conn *conn, struct bt_hfp_ag *ag)
+{
+	if (conn != default_conn) {
+		bt_shell_warn("The conn %p is not aligned with ACL conn %p", conn, default_conn);
+	}
+	hfp_ag = ag;
+	bt_shell_print("AG connected");
+}
+
+static void ag_disconnected(struct bt_hfp_ag *ag)
+{
+	ag_remove_calls();
+	bt_shell_print("AG disconnected");
+}
+
+static void ag_sco_connected(struct bt_hfp_ag *ag, struct bt_conn *sco_conn)
+{
+	bt_shell_print("AG SCO connected %p", sco_conn);
+
+	if (hfp_ag_sco_conn != NULL) {
+		bt_shell_warn("AG SCO conn %p exists", hfp_ag_sco_conn);
+		return;
+	}
+
+	hfp_ag_sco_conn = bt_conn_ref(sco_conn);
+}
+
+static void ag_sco_disconnected(struct bt_conn *sco_conn, uint8_t reason)
+{
+	bt_shell_print("AG SCO disconnected %p (reason %u)", sco_conn, reason);
+
+	if (hfp_ag_sco_conn == sco_conn) {
+		bt_conn_unref(hfp_ag_sco_conn);
+		hfp_ag_sco_conn = NULL;
+	} else {
+		bt_shell_warn("Unknown SCO disconnected (%p != %p)", hfp_ag_sco_conn, sco_conn);
+	}
+}
+
+static int ag_memory_dial(struct bt_hfp_ag *ag, const char *location, char **number)
+{
+	static char *phone = "123456789";
+
+	if (strcmp(location, "0")) {
+		return -ENOTSUP;
+	}
+
+	bt_shell_print("AG memory dial");
+
+	*number = phone;
+
+	return 0;
+}
+
+static int ag_number_call(struct bt_hfp_ag *ag, const char *number)
+{
+	static char *phone = "123456789";
+
+	bt_shell_print("AG number call");
+
+	if (strcmp(number, phone)) {
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static void ag_outgoing(struct bt_hfp_ag *ag, struct bt_hfp_ag_call *call, const char *number)
+{
+	bt_shell_print("AG outgoing call %p, number %s", call, number);
+	ag_add_a_call(call);
+}
+
+static void ag_incoming(struct bt_hfp_ag *ag, struct bt_hfp_ag_call *call, const char *number)
+{
+	bt_shell_print("AG incoming call %p, number %s", call, number);
+	ag_add_a_call(call);
+}
+
+static void ag_incoming_held(struct bt_hfp_ag_call *call)
+{
+	bt_shell_print("AG incoming call %p is held", call);
+}
+
+static void ag_ringing(struct bt_hfp_ag_call *call, bool in_band)
+{
+	bt_shell_print("AG call %p start ringing mode %d", call, in_band);
+}
+
+static void ag_accept(struct bt_hfp_ag_call *call)
+{
+	bt_shell_print("AG call %p accept", call);
+}
+
+static void ag_held(struct bt_hfp_ag_call *call)
+{
+	bt_shell_print("AG call %p held", call);
+}
+
+static void ag_retrieve(struct bt_hfp_ag_call *call)
+{
+	bt_shell_print("AG call %p retrieved", call);
+}
+
+static void ag_reject(struct bt_hfp_ag_call *call)
+{
+	bt_shell_print("AG call %p reject", call);
+	ag_remove_a_call(call);
+}
+
+static void ag_terminate(struct bt_hfp_ag_call *call)
+{
+	bt_shell_print("AG call %p terminate", call);
+	ag_remove_a_call(call);
+}
+
+static void ag_codec(struct bt_hfp_ag *ag, uint32_t ids)
+{
+	bt_shell_print("AG received codec id bit map %x", ids);
+}
+
+void ag_vgm(struct bt_hfp_ag *ag, uint8_t gain)
+{
+	bt_shell_print("AG received vgm %d", gain);
+}
+
+void ag_vgs(struct bt_hfp_ag *ag, uint8_t gain)
+{
+	bt_shell_print("AG received vgs %d", gain);
+}
+
+void ag_codec_negotiate(struct bt_hfp_ag *ag, int err)
+{
+	bt_shell_print("AG codec negotiation result %d", err);
+}
+
+void ag_audio_connect_req(struct bt_hfp_ag *ag)
+{
+	bt_shell_print("Receive audio connect request. "
+		       "Input `hfp ag audio_connect` to start audio connect");
+}
+
+void ag_ecnr_turn_off(struct bt_hfp_ag *ag)
+{
+	bt_shell_print("encr is disabled");
+}
+
+#if defined(CONFIG_BT_HFP_AG_3WAY_CALL)
+void ag_explicit_call_transfer(struct bt_hfp_ag *ag)
+{
+	bt_shell_print("explicit call transfer");
+}
+#endif /* CONFIG_BT_HFP_AG_3WAY_CALL */
+
+#if defined(CONFIG_BT_HFP_AG_VOICE_RECG)
+void ag_voice_recognition(struct bt_hfp_ag *ag, bool activate)
+{
+	bt_shell_print("AG Voice recognition %s", activate ? "activate" : "deactivate");
+}
+
+#if defined(CONFIG_BT_HFP_AG_ENH_VOICE_RECG)
+void ag_ready_to_accept_audio(struct bt_hfp_ag *ag)
+{
+	bt_shell_print("hf is ready to accept audio");
+}
+#endif /* CONFIG_BT_HFP_AG_ENH_VOICE_RECG */
+#endif /* CONFIG_BT_HFP_AG_VOICE_RECG */
+
+#if defined(CONFIG_BT_HFP_AG_VOICE_TAG)
+int ag_request_phone_number(struct bt_hfp_ag *ag, char **number)
+{
+	static bool valid_number;
+
+	if (valid_number && number) {
+		valid_number = false;
+		*number = "123456789";
+		return 0;
+	}
+
+	valid_number = true;
+	return -EINVAL;
+}
+#endif /* CONFIG_BT_HFP_AG_VOICE_TAG */
+
+void ag_transmit_dtmf_code(struct bt_hfp_ag *ag, char code)
+{
+	bt_shell_print("DTMF code is %c", code);
+}
+
+struct {
+	char *number;
+	uint8_t type;
+	uint8_t service;
+} ag_subscriber_number_info[] = {
+	{
+		.number = "12345678",
+		.type = 128,
+		.service = 4,
+	},
+	{
+		.number = "87654321",
+		.type = 128,
+		.service = 4,
+	},
+};
+
+static bool subscriber;
+
+int ag_subscriber_number(struct bt_hfp_ag *ag, bt_hfp_ag_query_subscriber_func_t func)
+{
+	int err;
+
+	if (subscriber && func) {
+		for (size_t index = 0; index < ARRAY_SIZE(ag_subscriber_number_info); index++) {
+			err = func(ag, ag_subscriber_number_info[index].number,
+				   ag_subscriber_number_info[index].type,
+				   ag_subscriber_number_info[index].service);
+			if (err < 0) {
+				break;
+			}
+		}
+	}
+	return 0;
+}
+
+void ag_hf_indicator_value(struct bt_hfp_ag *ag, enum hfp_ag_hf_indicators indicator,
+			   uint32_t value)
+{
+	bt_shell_print("indicator %d value %d", indicator, value);
+}
+
+static struct bt_hfp_ag_cb ag_cb = {
+	.connected = ag_connected,
+	.disconnected = ag_disconnected,
+	.sco_connected = ag_sco_connected,
+	.sco_disconnected = ag_sco_disconnected,
+	.memory_dial = ag_memory_dial,
+	.number_call = ag_number_call,
+	.outgoing = ag_outgoing,
+	.incoming = ag_incoming,
+	.incoming_held = ag_incoming_held,
+	.ringing = ag_ringing,
+	.accept = ag_accept,
+	.held = ag_held,
+	.retrieve = ag_retrieve,
+	.reject = ag_reject,
+	.terminate = ag_terminate,
+	.codec = ag_codec,
+	.codec_negotiate = ag_codec_negotiate,
+	.audio_connect_req = ag_audio_connect_req,
+	.vgm = ag_vgm,
+	.vgs = ag_vgs,
+#if defined(CONFIG_BT_HFP_AG_ECNR)
+	.ecnr_turn_off = ag_ecnr_turn_off,
+#endif /* CONFIG_BT_HFP_AG_ECNR */
+#if defined(CONFIG_BT_HFP_AG_3WAY_CALL)
+	.explicit_call_transfer = ag_explicit_call_transfer,
+#endif /* CONFIG_BT_HFP_AG_3WAY_CALL */
+#if defined(CONFIG_BT_HFP_AG_VOICE_RECG)
+	.voice_recognition = ag_voice_recognition,
+#if defined(CONFIG_BT_HFP_AG_ENH_VOICE_RECG)
+	.ready_to_accept_audio = ag_ready_to_accept_audio,
+#endif /* CONFIG_BT_HFP_AG_ENH_VOICE_RECG */
+#endif /* CONFIG_BT_HFP_AG_VOICE_RECG */
+#if defined(CONFIG_BT_HFP_AG_VOICE_TAG)
+	.request_phone_number = ag_request_phone_number,
+#endif /* CONFIG_BT_HFP_AG_VOICE_TAG */
+	.transmit_dtmf_code = ag_transmit_dtmf_code,
+	.subscriber_number = ag_subscriber_number,
+	.hf_indicator_value = ag_hf_indicator_value,
+};
+
+static int cmd_ag_reg_enable(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_ag_register(&ag_cb);
+	if (err) {
+		shell_error(sh, "Callback register failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_connect(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	struct bt_hfp_ag *ag;
+	uint8_t channel;
+
+	channel = atoi(argv[1]);
+
+	err = bt_hfp_ag_connect(default_conn, &ag, channel);
+	if (err) {
+		shell_error(sh, "Connect failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_disconnect(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_ag_disconnect(hfp_ag);
+	if (err) {
+		shell_error(sh, "Disconnect failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_sco_disconnect(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_conn_disconnect(hfp_ag_sco_conn, BT_HCI_ERR_REMOTE_USER_TERM_CONN);
+	if (err) {
+		shell_error(sh, "Disconnect failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_remote_incoming(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_ag_remote_incoming(hfp_ag, argv[1]);
+	if (err) {
+		shell_error(sh, "Set remote incoming failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_hold_incoming(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int index;
+
+	index = atoi(argv[1]);
+	if ((index >= ((int)ARRAY_SIZE(hfp_ag_call))) || !hfp_ag_call[index]) {
+		shell_error(sh, "Invalid call index: %d", index);
+		return -EINVAL;
+	}
+
+	err = bt_hfp_ag_hold_incoming(hfp_ag_call[index]);
+	if (err) {
+		shell_error(sh, "Set remote incoming failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_remote_reject(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int index;
+
+	index = atoi(argv[1]);
+	if ((index >= ((int)ARRAY_SIZE(hfp_ag_call))) || !hfp_ag_call[index]) {
+		shell_error(sh, "Invalid call index: %d", index);
+		return -EINVAL;
+	}
+
+	err = bt_hfp_ag_remote_reject(hfp_ag_call[index]);
+	if (err) {
+		shell_error(sh, "Set remote reject failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_remote_accept(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int index;
+
+	index = atoi(argv[1]);
+	if ((index >= ((int)ARRAY_SIZE(hfp_ag_call))) || !hfp_ag_call[index]) {
+		shell_error(sh, "Invalid call index: %d", index);
+		return -EINVAL;
+	}
+
+	err = bt_hfp_ag_remote_accept(hfp_ag_call[index]);
+	if (err) {
+		shell_error(sh, "Set remote accept failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_remote_terminate(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int index;
+
+	index = atoi(argv[1]);
+	if ((index >= ((int)ARRAY_SIZE(hfp_ag_call))) || !hfp_ag_call[index]) {
+		shell_error(sh, "Invalid call index: %d", index);
+		return -EINVAL;
+	}
+
+	err = bt_hfp_ag_remote_terminate(hfp_ag_call[index]);
+	if (err) {
+		shell_error(sh, "Set remote terminate failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_remote_ringing(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int index;
+
+	index = atoi(argv[1]);
+	if ((index >= ((int)ARRAY_SIZE(hfp_ag_call))) || !hfp_ag_call[index]) {
+		shell_error(sh, "Invalid call index: %d", index);
+		return -EINVAL;
+	}
+
+	err = bt_hfp_ag_remote_ringing(hfp_ag_call[index]);
+	if (err) {
+		shell_error(sh, "Set remote ringing failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_outgoing(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_ag_outgoing(hfp_ag, argv[1]);
+	if (err) {
+		shell_error(sh, "Set outgoing failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_reject(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int index;
+
+	index = atoi(argv[1]);
+	if ((index >= ((int)ARRAY_SIZE(hfp_ag_call))) || !hfp_ag_call[index]) {
+		shell_error(sh, "Invalid call index: %d", index);
+		return -EINVAL;
+	}
+
+	err = bt_hfp_ag_reject(hfp_ag_call[index]);
+	if (err) {
+		shell_error(sh, "Set reject failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_accept(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int index;
+
+	index = atoi(argv[1]);
+	if ((index >= ((int)ARRAY_SIZE(hfp_ag_call))) || !hfp_ag_call[index]) {
+		shell_error(sh, "Invalid call index: %d", index);
+		return -EINVAL;
+	}
+
+	err = bt_hfp_ag_accept(hfp_ag_call[index]);
+	if (err) {
+		shell_error(sh, "Set accept failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_hold(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int index;
+
+	index = atoi(argv[1]);
+	if ((index >= ((int)ARRAY_SIZE(hfp_ag_call))) || !hfp_ag_call[index]) {
+		shell_error(sh, "Invalid call index: %d", index);
+		return -EINVAL;
+	}
+
+	err = bt_hfp_ag_hold(hfp_ag_call[index]);
+	if (err) {
+		shell_error(sh, "Set hold failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_retrieve(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int index;
+
+	index = atoi(argv[1]);
+	if ((index >= ((int)ARRAY_SIZE(hfp_ag_call))) || !hfp_ag_call[index]) {
+		shell_error(sh, "Invalid call index: %d", index);
+		return -EINVAL;
+	}
+
+	err = bt_hfp_ag_retrieve(hfp_ag_call[index]);
+	if (err) {
+		shell_error(sh, "Set retrieve failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_terminate(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int index;
+
+	index = atoi(argv[1]);
+	if ((index >= ((int)ARRAY_SIZE(hfp_ag_call))) || !hfp_ag_call[index]) {
+		shell_error(sh, "Invalid call index: %d", index);
+		return -EINVAL;
+	}
+
+	err = bt_hfp_ag_terminate(hfp_ag_call[index]);
+	if (err) {
+		shell_error(sh, "Set terminate failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_vgm(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	uint8_t vgm;
+
+	vgm = atoi(argv[1]);
+
+	err = bt_hfp_ag_vgm(hfp_ag, vgm);
+	if (err) {
+		shell_error(sh, "Set microphone gain failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_vgs(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	uint8_t vgs;
+
+	vgs = atoi(argv[1]);
+
+	err = bt_hfp_ag_vgs(hfp_ag, vgs);
+	if (err) {
+		shell_error(sh, "Set speaker gain failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_operator(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	uint8_t mode;
+
+	mode = atoi(argv[1]);
+
+	err = bt_hfp_ag_set_operator(hfp_ag, mode, argv[2]);
+	if (err) {
+		shell_error(sh, "Set network operator failed: %d", err);
+	}
+
+	return err;
+}
+
+#if defined(CONFIG_BT_HFP_AG_CODEC_NEG)
+static int cmd_ag_audio_connect(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	uint8_t id;
+
+	id = atoi(argv[1]);
+
+	err = bt_hfp_ag_audio_connect(hfp_ag, id);
+	if (err) {
+		shell_error(sh, "Start audio connection procedure failed: %d", err);
+	}
+
+	return err;
+}
+#endif /* CONFIG_BT_HFP_AG_CODEC_NEG */
+
+static int cmd_ag_inband_ringtone(const struct shell *sh, size_t argc, char **argv)
+{
+	const char *action;
+	bool enable;
+	int err;
+
+	action = argv[1];
+
+	if (strcmp(action, "enable") == 0) {
+		enable = true;
+	} else if (strcmp(action, "disable") == 0) {
+		enable = false;
+	} else {
+		shell_error(sh, "Invalid option.");
+		return -ENOEXEC;
+	}
+
+	err = bt_hfp_ag_inband_ringtone(hfp_ag, (bool)enable);
+	if (err) {
+		shell_error(sh, "Set inband ringtone failed: %d", err);
+	}
+
+	return err;
+}
+
+#if defined(CONFIG_BT_HFP_AG_3WAY_CALL)
+static int cmd_ag_explicit_call_transfer(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+
+	err = bt_hfp_ag_explicit_call_transfer(hfp_ag);
+	if (err) {
+		shell_error(sh, "Explicit call transfer failed: %d", err);
+	}
+
+	return err;
+}
+#endif /* CONFIG_BT_HFP_AG_3WAY_CALL */
+
+#if defined(CONFIG_BT_HFP_AG_VOICE_RECG)
+static int cmd_ag_voice_recognition(const struct shell *sh, size_t argc, char **argv)
+{
+	const char *action;
+	bool enable;
+	int err;
+
+	action = argv[1];
+
+	if (strcmp(action, "activate") == 0) {
+		enable = true;
+	} else if (strcmp(action, "deactivate") == 0) {
+		enable = false;
+	} else {
+		shell_error(sh, "Invalid option.");
+		return -ENOEXEC;
+	}
+
+	err = bt_hfp_ag_voice_recognition(hfp_ag, enable);
+	if (err) {
+		shell_error(sh, "Set voice recognition failed: %d", err);
+	}
+
+	return err;
+}
+
+#if defined(CONFIG_BT_HFP_AG_ENH_VOICE_RECG)
+static int cmd_ag_vre_state(const struct shell *sh, size_t argc, char **argv)
+{
+	const char *action;
+	uint8_t state = 0;
+	int err;
+
+	action = argv[1];
+
+	for (size_t index = 0; index < strlen(action); index++) {
+		switch (action[index]) {
+		case 'R':
+			state |= BIT(0);
+			break;
+		case 'S':
+			state |= BIT(1);
+			break;
+		case 'P':
+			state |= BIT(2);
+			break;
+		}
+	}
+
+	err = bt_hfp_ag_vre_state(hfp_ag, state);
+	if (err) {
+		shell_error(sh, "Set voice recognition engine state failed: %d", err);
+	}
+
+	return err;
+}
+#endif /* CONFIG_BT_HFP_AG_ENH_VOICE_RECG */
+#if defined(CONFIG_BT_HFP_AG_VOICE_RECG_TEXT)
+static int cmd_ag_vre_text(const struct shell *sh, size_t argc, char **argv)
+{
+	const char *action;
+	uint8_t state = 0;
+	const char *id;
+	uint8_t type;
+	uint8_t operation;
+	const char *text;
+	int err;
+
+	action = argv[1];
+	id = argv[2];
+	type = (uint8_t)atoi(argv[3]);
+	operation = (uint8_t)atoi(argv[4]);
+	text = argv[5];
+
+	for (size_t index = 0; index < strlen(action); index++) {
+		switch (action[index]) {
+		case 'R':
+			state |= BIT(0);
+			break;
+		case 'S':
+			state |= BIT(1);
+			break;
+		case 'P':
+			state |= BIT(2);
+			break;
+		}
+	}
+
+	err = bt_hfp_ag_vre_textual_representation(hfp_ag, state, id, type, operation, text);
+	if (err) {
+		shell_error(sh, "Set voice recognition engine textual representation failed: %d",
+			    err);
+	}
+
+	return err;
+}
+#endif /* CONFIG_BT_HFP_AG_VOICE_RECG_TEXT */
+#endif /* CONFIG_BT_HFP_AG_VOICE_RECG */
+
+static int cmd_ag_subscriber(const struct shell *sh, size_t argc, char **argv)
+{
+	const char *action;
+
+	action = argv[1];
+
+	if (strcmp(action, "empty") == 0) {
+		subscriber = false;
+	} else if (strcmp(action, "notempty") == 0) {
+		subscriber = true;
+	} else {
+		shell_error(sh, "Invalid option.");
+		return -ENOEXEC;
+	}
+
+	return 0;
+}
+
+static int cmd_ag_signal_strength(const struct shell *sh, size_t argc, char **argv)
+{
+	uint8_t strength;
+	int err;
+
+	strength = (uint8_t)atoi(argv[1]);
+
+	err = bt_hfp_ag_signal_strength(hfp_ag, strength);
+	if (err) {
+		shell_error(sh, "Set signal strength failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_roaming_status(const struct shell *sh, size_t argc, char **argv)
+{
+	uint8_t status;
+	int err;
+
+	status = (uint8_t)atoi(argv[1]);
+
+	err = bt_hfp_ag_roaming_status(hfp_ag, status);
+	if (err) {
+		shell_error(sh, "Set roaming status failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_battery_level(const struct shell *sh, size_t argc, char **argv)
+{
+	uint8_t level;
+	int err;
+
+	level = (uint8_t)atoi(argv[1]);
+
+	err = bt_hfp_ag_battery_level(hfp_ag, level);
+	if (err) {
+		shell_error(sh, "Set battery level failed: %d", err);
+	}
+
+	return err;
+}
+
+static int cmd_ag_service_availability(const struct shell *sh, size_t argc, char **argv)
+{
+	bool available;
+	const char *action;
+	int err;
+
+	action = argv[1];
+
+	if (strcmp(action, "yes") == 0) {
+		available = true;
+	} else if (strcmp(action, "no") == 0) {
+		available = false;
+	} else {
+		shell_error(sh, "Invalid option.");
+		return -ENOEXEC;
+	}
+
+	err = bt_hfp_ag_service_availability(hfp_ag, available);
+	if (err) {
+		shell_error(sh, "Set service availability failed: %d", err);
+	}
+
+	return err;
+}
+
+#if defined(CONFIG_BT_HFP_AG_HF_INDICATORS)
+static int cmd_ag_hf_indicator(const struct shell *sh, size_t argc, char **argv)
+{
+	bool enable;
+	const char *action;
+	int err;
+	size_t indicator;
+
+	indicator = atoi(argv[1]);
+	action = argv[2];
+
+	if (strcmp(action, "enable") == 0) {
+		enable = true;
+	} else if (strcmp(action, "disable") == 0) {
+		enable = false;
+	} else {
+		shell_error(sh, "Invalid option.");
+		return -ENOEXEC;
+	}
+
+	err = bt_hfp_ag_hf_indicator(hfp_ag, indicator, enable);
+	if (err) {
+		shell_error(sh, "Activate/deactivate HF indicator failed: %d", err);
+	}
+
+	return err;
+}
+#endif /* CONFIG_BT_HFP_HF_HF_INDICATORS */
+
+#define HELP_AG_TEXTUAL_REPRESENTATION          \
+	"<[R-ready][S-send][P-processing]> "        \
+	"<id> <type> <operation> <text string>"
+
+SHELL_STATIC_SUBCMD_SET_CREATE(ag_cmds,
+	SHELL_CMD_ARG(reg, NULL, HELP_NONE, cmd_ag_reg_enable, 1, 0),
+	SHELL_CMD_ARG(connect, NULL, "<channel>", cmd_ag_connect, 2, 0),
+	SHELL_CMD_ARG(disconnect, NULL, HELP_NONE, cmd_ag_disconnect, 1, 0),
+	SHELL_CMD_ARG(sco_disconnect, NULL, HELP_NONE, cmd_ag_sco_disconnect, 1, 0),
+	SHELL_CMD_ARG(remote_incoming, NULL, "<number>", cmd_ag_remote_incoming, 2, 0),
+	SHELL_CMD_ARG(hold_incoming, NULL, "<number>", cmd_ag_hold_incoming, 2, 0),
+	SHELL_CMD_ARG(remote_reject, NULL, "<call index>", cmd_ag_remote_reject, 2, 0),
+	SHELL_CMD_ARG(remote_accept, NULL, "<call index>", cmd_ag_remote_accept, 2, 0),
+	SHELL_CMD_ARG(remote_terminate, NULL, "<call index>", cmd_ag_remote_terminate, 2, 0),
+	SHELL_CMD_ARG(remote_ringing, NULL, "<call index>", cmd_ag_remote_ringing, 2, 0),
+	SHELL_CMD_ARG(outgoing, NULL, "<number>", cmd_ag_outgoing, 2, 0),
+	SHELL_CMD_ARG(reject, NULL, "<call index>", cmd_ag_reject, 2, 0),
+	SHELL_CMD_ARG(accept, NULL, "<call index>", cmd_ag_accept, 2, 0),
+	SHELL_CMD_ARG(hold, NULL, "<call index>", cmd_ag_hold, 2, 0),
+	SHELL_CMD_ARG(retrieve, NULL, "<call index>", cmd_ag_retrieve, 2, 0),
+	SHELL_CMD_ARG(terminate, NULL, "<call index>", cmd_ag_terminate, 2, 0),
+	SHELL_CMD_ARG(vgm, NULL, "<gain>", cmd_ag_vgm, 2, 0),
+	SHELL_CMD_ARG(vgs, NULL, "<gain>", cmd_ag_vgs, 2, 0),
+	SHELL_CMD_ARG(operator, NULL, "<mode> <operator>", cmd_ag_operator, 3, 0),
+#if defined(CONFIG_BT_HFP_AG_CODEC_NEG)
+	SHELL_CMD_ARG(audio_connect, NULL, "<codec id>", cmd_ag_audio_connect, 2, 0),
+#endif /* CONFIG_BT_HFP_AG_CODEC_NEG */
+	SHELL_CMD_ARG(inband_ringtone, NULL, "<enable/disable>", cmd_ag_inband_ringtone, 2, 0),
+#if defined(CONFIG_BT_HFP_AG_3WAY_CALL)
+	SHELL_CMD_ARG(explicit_call_transfer, NULL, HELP_NONE, cmd_ag_explicit_call_transfer, 1, 0),
+#endif /* CONFIG_BT_HFP_AG_3WAY_CALL */
+#if defined(CONFIG_BT_HFP_AG_VOICE_RECG)
+	SHELL_CMD_ARG(voice_recognition, NULL, "<activate/deactivate>", cmd_ag_voice_recognition, 2,
+		      0),
+#if defined(CONFIG_BT_HFP_AG_ENH_VOICE_RECG)
+	SHELL_CMD_ARG(vre_state, NULL, "<[R-ready][S-send][P-processing]>", cmd_ag_vre_state, 2, 0),
+#endif /* CONFIG_BT_HFP_AG_ENH_VOICE_RECG */
+#if defined(CONFIG_BT_HFP_AG_VOICE_RECG_TEXT)
+	SHELL_CMD_ARG(vre_text, NULL, HELP_AG_TEXTUAL_REPRESENTATION, cmd_ag_vre_text, 6, 0),
+#endif /* CONFIG_BT_HFP_AG_VOICE_RECG_TEXT */
+#endif /* CONFIG_BT_HFP_AG_VOICE_RECG */
+	SHELL_CMD_ARG(subscriber, NULL, "<empty/notempty>", cmd_ag_subscriber, 2, 0),
+	SHELL_CMD_ARG(signal_strength, NULL, "<signal strength>", cmd_ag_signal_strength, 2, 0),
+	SHELL_CMD_ARG(roaming_status, NULL, "<roaming status>", cmd_ag_roaming_status, 2, 0),
+	SHELL_CMD_ARG(battery_level, NULL, "<battery level>", cmd_ag_battery_level, 2, 0),
+	SHELL_CMD_ARG(service_availability, NULL, "<yes/no>", cmd_ag_service_availability, 2, 0),
+#if defined(CONFIG_BT_HFP_AG_HF_INDICATORS)
+	SHELL_CMD_ARG(hf_indicator, NULL, "<indicator> <enable/disable>", cmd_ag_hf_indicator, 3,
+		      0),
+#endif /* CONFIG_BT_HFP_HF_HF_INDICATORS */
+	SHELL_SUBCMD_SET_END
+);
+#endif /* CONFIG_BT_HFP_AG */
+
+static int cmd_default(const struct shell *sh, size_t argc, char **argv)
+{
+	if (argc == 1) {
+		shell_help(sh);
+		/* sh returns 1 when help is printed */
+		return SHELL_CMD_HELP_PRINTED;
+	}
+
+	shell_error(sh, "%s unknown parameter: %s", argv[0], argv[1]);
+
+	return -ENOEXEC;
+}
+
+SHELL_STATIC_SUBCMD_SET_CREATE(hfp_cmds,
+#if defined(CONFIG_BT_HFP_HF)
+	SHELL_CMD(hf, &hf_cmds, "HFP HF shell commands", cmd_default),
+#endif /* CONFIG_BT_HFP_HF */
+#if defined(CONFIG_BT_HFP_AG)
+	SHELL_CMD(ag, &ag_cmds, "HFP AG shell commands", cmd_default),
+#endif /* CONFIG_BT_HFP_AG */
+	SHELL_SUBCMD_SET_END
+);
+
+SHELL_CMD_ARG_REGISTER(hfp, &hfp_cmds, "Bluetooth HFP shell commands", cmd_default, 1, 1);
diff --git a/subsys/bluetooth/host/classic/shell/rfcomm.c b/subsys/bluetooth/host/classic/shell/rfcomm.c
index a3990b59d86..feba34ecf7d 100644
--- a/subsys/bluetooth/host/classic/shell/rfcomm.c
+++ b/subsys/bluetooth/host/classic/shell/rfcomm.c
@@ -30,6 +30,7 @@
 #include <zephyr/shell/shell.h>
 
 #include "host/shell/bt.h"
+#include "common/bt_shell_private.h"
 
 #define DATA_MTU 48
 
@@ -101,17 +102,17 @@ static struct bt_sdp_record spp_rec = BT_SDP_RECORD(spp_attrs);
 
 static void rfcomm_recv(struct bt_rfcomm_dlc *dlci, struct net_buf *buf)
 {
-	shell_print(ctx_shell, "Incoming data dlc %p len %u", dlci, buf->len);
+	bt_shell_print("Incoming data dlc %p len %u", dlci, buf->len);
 }
 
 static void rfcomm_connected(struct bt_rfcomm_dlc *dlci)
 {
-	shell_print(ctx_shell, "Dlc %p connected", dlci);
+	bt_shell_print("Dlc %p connected", dlci);
 }
 
 static void rfcomm_disconnected(struct bt_rfcomm_dlc *dlci)
 {
-	shell_print(ctx_shell, "Dlc %p disconnected", dlci);
+	bt_shell_print("Dlc %p disconnected", dlci);
 }
 
 static struct bt_rfcomm_dlc_ops rfcomm_ops = {
@@ -125,12 +126,13 @@ static struct bt_rfcomm_dlc rfcomm_dlc = {
 	.mtu = 30,
 };
 
-static int rfcomm_accept(struct bt_conn *conn, struct bt_rfcomm_dlc **dlc)
+static int rfcomm_accept(struct bt_conn *conn, struct bt_rfcomm_server *server,
+			 struct bt_rfcomm_dlc **dlc)
 {
-	shell_print(ctx_shell, "Incoming RFCOMM conn %p", conn);
+	bt_shell_print("Incoming RFCOMM conn %p", conn);
 
 	if (rfcomm_dlc.session) {
-		shell_error(ctx_shell, "No channels available");
+		bt_shell_error("No channels available");
 		return -ENOMEM;
 	}
 
diff --git a/subsys/bluetooth/host/classic/ssp.c b/subsys/bluetooth/host/classic/ssp.c
index 9ccf22d3632..9f43b8a69d2 100644
--- a/subsys/bluetooth/host/classic/ssp.c
+++ b/subsys/bluetooth/host/classic/ssp.c
@@ -1,12 +1,14 @@
 /*
- * Copyright (c) 2017 Nordic Semiconductor ASA
+ * Copyright (c) 2017-2025 Nordic Semiconductor ASA
  * Copyright (c) 2015 Intel Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <errno.h>
 #include <stdint.h>
 
+#include <zephyr/bluetooth/conn.h>
 #include <zephyr/sys/byteorder.h>
 
 #include <zephyr/bluetooth/buf.h>
@@ -19,6 +21,7 @@
 
 #include "host/hci_core.h"
 #include "host/conn_internal.h"
+#include "l2cap_br_internal.h"
 
 #define LOG_LEVEL CONFIG_BT_HCI_CORE_LOG_LEVEL
 #include <zephyr/logging/log.h>
@@ -87,7 +90,8 @@ int bt_conn_auth_pincode_entry(struct bt_conn *conn, const char *pin)
 		return -EINVAL;
 	}
 
-	if (conn->type != BT_CONN_TYPE_BR) {
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_BR)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
 		return -EINVAL;
 	}
 
@@ -158,15 +162,16 @@ static uint8_t ssp_pair_method(const struct bt_conn *conn)
 
 static uint8_t ssp_get_auth(const struct bt_conn *conn)
 {
-	/* Validate no bond auth request, and if valid use it. */
-	if ((conn->br.remote_auth == BT_HCI_NO_BONDING) ||
-	    ((conn->br.remote_auth == BT_HCI_NO_BONDING_MITM) &&
-	     (ssp_pair_method(conn) > JUST_WORKS))) {
-		return conn->br.remote_auth;
-	}
+	bt_security_t max_sec_level;
+
+	/* Check if the MITM is required by service */
+	max_sec_level = bt_l2cap_br_get_max_sec_level();
 
-	/* Local & remote have enough IO capabilities to get MITM protection. */
-	if (ssp_pair_method(conn) > JUST_WORKS) {
+	/*
+	 * The local device shall only set the MITM protection required flag
+	 * if the local device itself requires MITM protection.
+	 */
+	if ((max_sec_level > BT_SECURITY_L2) && (ssp_pair_method(conn) > JUST_WORKS)) {
 		return conn->br.remote_auth | BT_MITM;
 	}
 
@@ -673,21 +678,13 @@ void bt_hci_io_capa_req(struct net_buf *buf)
 
 		err = bt_auth->pairing_accept(conn, NULL);
 		if (err != BT_SECURITY_ERR_SUCCESS) {
-			io_capa_neg_reply(&evt->bdaddr,
-					  BT_HCI_ERR_PAIRING_NOT_ALLOWED);
+			io_capa_neg_reply(&evt->bdaddr, BT_HCI_ERR_PAIRING_NOT_ALLOWED);
+			bt_conn_unref(conn);
 			return;
 		}
 	}
 #endif
 
-	resp_buf = bt_hci_cmd_create(BT_HCI_OP_IO_CAPABILITY_REPLY,
-				     sizeof(*cp));
-	if (!resp_buf) {
-		LOG_ERR("Out of command buffers");
-		bt_conn_unref(conn);
-		return;
-	}
-
 	/*
 	 * Set authentication requirements when acting as pairing initiator to
 	 * 'dedicated bond' with MITM protection set if local IO capa
@@ -715,6 +712,25 @@ void bt_hci_io_capa_req(struct net_buf *buf)
 		}
 	} else {
 		auth = ssp_get_auth(conn);
+
+		/*
+		 * Core v6.0, Vol 3, Part C, Section 4.3.1 Non-bondable mode
+		 * When a Bluetooth device is in non-bondable mode it shall not accept a
+		 * pairing request that results in bonding. Devices in non-bondable mode
+		 * may accept connections that do not request or require bonding.
+		 *
+		 * If the peer supports bonding mode, but the local is in non-bondable
+		 * mode, it will send a negative response with error code
+		 * `BT_HCI_ERR_PAIRING_NOT_ALLOWED`.
+		 */
+		if (!atomic_test_bit(conn->flags, BT_CONN_BR_BONDABLE) &&
+		    (conn->br.remote_auth > BT_HCI_NO_BONDING_MITM)) {
+			LOG_WRN("Invalid remote bonding requirements");
+			io_capa_neg_reply(&evt->bdaddr,
+					  BT_HCI_ERR_PAIRING_NOT_ALLOWED);
+			bt_conn_unref(conn);
+			return;
+		}
 	}
 
 	if (!atomic_test_bit(conn->flags, BT_CONN_BR_BONDABLE)) {
@@ -722,6 +738,13 @@ void bt_hci_io_capa_req(struct net_buf *buf)
 		auth = BT_HCI_SET_NO_BONDING(auth);
 	}
 
+	resp_buf = bt_hci_cmd_create(BT_HCI_OP_IO_CAPABILITY_REPLY, sizeof(*cp));
+	if (!resp_buf) {
+		LOG_ERR("Out of command buffers");
+		bt_conn_unref(conn);
+		return;
+	}
+
 	cp = net_buf_add(resp_buf, sizeof(*cp));
 	bt_addr_copy(&cp->bdaddr, &evt->bdaddr);
 	cp->capability = get_io_capa();
diff --git a/subsys/bluetooth/host/conn.c b/subsys/bluetooth/host/conn.c
index f10f1aceed8..4f8725663ee 100644
--- a/subsys/bluetooth/host/conn.c
+++ b/subsys/bluetooth/host/conn.c
@@ -2,14 +2,33 @@
 
 /*
  * Copyright (c) 2015-2016 Intel Corporation
+ * Copyright (c) 2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-
-#include <zephyr/kernel.h>
-#include <string.h>
 #include <errno.h>
 #include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/att.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/buf.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/direction.h>
+#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/bluetooth/hci_vs.h>
+#include <zephyr/bluetooth/iso.h>
+#include <zephyr/bluetooth/l2cap.h>
+#include <zephyr/irq.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
 #include <zephyr/sys/atomic.h>
 #include <zephyr/sys/byteorder.h>
 #include <zephyr/sys/check.h>
@@ -19,35 +38,29 @@
 #include <zephyr/sys/slist.h>
 #include <zephyr/debug/stack.h>
 #include <zephyr/sys/__assert.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/toolchain.h>
 
-#include <zephyr/bluetooth/hci.h>
-#include <zephyr/bluetooth/bluetooth.h>
-#include <zephyr/bluetooth/direction.h>
-#include <zephyr/bluetooth/conn.h>
-#include <zephyr/bluetooth/hci_vs.h>
-#include <zephyr/bluetooth/att.h>
-
+#include "addr_internal.h"
+#include "adv.h"
+#include "att_internal.h"
+#include "buf_view.h"
+#include "classic/conn_br_internal.h"
+#include "classic/sco_internal.h"
+#include "classic/ssp.h"
 #include "common/assert.h"
 #include "common/bt_str.h"
-
-#include "buf_view.h"
-#include "addr_internal.h"
+#include "conn_internal.h"
+#include "direction_internal.h"
 #include "hci_core.h"
 #include "id.h"
-#include "adv.h"
-#include "scan.h"
-#include "conn_internal.h"
-#include "l2cap_internal.h"
+#include "iso_internal.h"
 #include "keys.h"
+#include "l2cap_internal.h"
+#include "scan.h"
 #include "smp.h"
-#include "classic/ssp.h"
-#include "att_internal.h"
-#include "iso_internal.h"
-#include "direction_internal.h"
-#include "classic/sco_internal.h"
 
 #define LOG_LEVEL CONFIG_BT_CONN_LOG_LEVEL
-#include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(bt_conn);
 
 K_FIFO_DEFINE(free_tx);
@@ -110,8 +123,6 @@ static sys_slist_t conn_cbs = SYS_SLIST_STATIC_INIT(&conn_cbs);
 static struct bt_conn_tx conn_tx[CONFIG_BT_CONN_TX_MAX];
 
 #if defined(CONFIG_BT_CLASSIC)
-static int bt_hci_connect_br_cancel(struct bt_conn *conn);
-
 static struct bt_conn sco_conns[CONFIG_BT_MAX_SCO_CONN];
 #endif /* CONFIG_BT_CLASSIC */
 #endif /* CONFIG_BT_CONN */
@@ -1892,6 +1903,9 @@ int bt_conn_disconnect(struct bt_conn *conn, uint8_t reason)
 #if defined(CONFIG_BT_CLASSIC)
 		else if (conn->type == BT_CONN_TYPE_BR) {
 			return bt_hci_connect_br_cancel(conn);
+		} else if (conn->type == BT_CONN_TYPE_SCO) {
+			/* There is no HCI cmd to cancel SCO connecting from spec */
+			return -EPROTONOSUPPORT;
 		}
 #endif /* CONFIG_BT_CLASSIC */
 		else {
@@ -2306,68 +2320,11 @@ static struct bt_conn *acl_conn_new(void)
 }
 
 #if defined(CONFIG_BT_CLASSIC)
-void bt_sco_cleanup(struct bt_conn *sco_conn)
-{
-	bt_sco_cleanup_acl(sco_conn);
-	bt_conn_unref(sco_conn);
-}
-
 static struct bt_conn *sco_conn_new(void)
 {
 	return bt_conn_new(sco_conns, ARRAY_SIZE(sco_conns));
 }
 
-struct bt_conn *bt_conn_create_br(const bt_addr_t *peer,
-				  const struct bt_br_conn_param *param)
-{
-	struct bt_hci_cp_connect *cp;
-	struct bt_conn *conn;
-	struct net_buf *buf;
-
-	conn = bt_conn_lookup_addr_br(peer);
-	if (conn) {
-		switch (conn->state) {
-		case BT_CONN_INITIATING:
-		case BT_CONN_CONNECTED:
-			return conn;
-		default:
-			bt_conn_unref(conn);
-			return NULL;
-		}
-	}
-
-	conn = bt_conn_add_br(peer);
-	if (!conn) {
-		return NULL;
-	}
-
-	buf = bt_hci_cmd_create(BT_HCI_OP_CONNECT, sizeof(*cp));
-	if (!buf) {
-		bt_conn_unref(conn);
-		return NULL;
-	}
-
-	cp = net_buf_add(buf, sizeof(*cp));
-
-	(void)memset(cp, 0, sizeof(*cp));
-
-	memcpy(&cp->bdaddr, peer, sizeof(cp->bdaddr));
-	cp->packet_type = sys_cpu_to_le16(0xcc18); /* DM1 DH1 DM3 DH5 DM5 DH5 */
-	cp->pscan_rep_mode = 0x02; /* R2 */
-	cp->allow_role_switch = param->allow_role_switch ? 0x01 : 0x00;
-	cp->clock_offset = 0x0000; /* TODO used cached clock offset */
-
-	if (bt_hci_cmd_send_sync(BT_HCI_OP_CONNECT, buf, NULL) < 0) {
-		bt_conn_unref(conn);
-		return NULL;
-	}
-
-	bt_conn_set_state(conn, BT_CONN_INITIATING);
-	conn->role = BT_CONN_ROLE_CENTRAL;
-
-	return conn;
-}
-
 struct bt_conn *bt_conn_lookup_addr_sco(const bt_addr_t *peer)
 {
 	int i;
@@ -2399,6 +2356,11 @@ struct bt_conn *bt_conn_lookup_addr_br(const bt_addr_t *peer)
 {
 	int i;
 
+	if (peer == NULL) {
+		LOG_DBG("Invalid peer address");
+		return NULL;
+	}
+
 	for (i = 0; i < ARRAY_SIZE(acl_conns); i++) {
 		struct bt_conn *conn = bt_conn_ref(&acl_conns[i]);
 
@@ -2470,36 +2432,6 @@ struct bt_conn *bt_conn_add_br(const bt_addr_t *peer)
 
 	return conn;
 }
-
-static int bt_hci_connect_br_cancel(struct bt_conn *conn)
-{
-	struct bt_hci_cp_connect_cancel *cp;
-	struct bt_hci_rp_connect_cancel *rp;
-	struct net_buf *buf, *rsp;
-	int err;
-
-	buf = bt_hci_cmd_create(BT_HCI_OP_CONNECT_CANCEL, sizeof(*cp));
-	if (!buf) {
-		return -ENOBUFS;
-	}
-
-	cp = net_buf_add(buf, sizeof(*cp));
-	memcpy(&cp->bdaddr, &conn->br.dst, sizeof(cp->bdaddr));
-
-	err = bt_hci_cmd_send_sync(BT_HCI_OP_CONNECT_CANCEL, buf, &rsp);
-	if (err) {
-		return err;
-	}
-
-	rp = (void *)rsp->data;
-
-	err = rp->status ? -EIO : 0;
-
-	net_buf_unref(rsp);
-
-	return err;
-}
-
 #endif /* CONFIG_BT_CLASSIC */
 
 #if defined(CONFIG_BT_SMP)
@@ -2580,6 +2512,11 @@ int bt_conn_le_start_encryption(struct bt_conn *conn, uint8_t rand[8],
 #if defined(CONFIG_BT_SMP) || defined(CONFIG_BT_CLASSIC)
 uint8_t bt_conn_enc_key_size(const struct bt_conn *conn)
 {
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE | BT_CONN_TYPE_BR)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return 0;
+	}
+
 	if (!conn->encrypt) {
 		return 0;
 	}
@@ -2695,6 +2632,11 @@ int bt_conn_set_security(struct bt_conn *conn, bt_security_t sec)
 	bool force_pair;
 	int err;
 
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE | BT_CONN_TYPE_BR)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
 	if (conn->state != BT_CONN_CONNECTED) {
 		return -ENOTCONN;
 	}
@@ -2730,6 +2672,11 @@ int bt_conn_set_security(struct bt_conn *conn, bt_security_t sec)
 
 bt_security_t bt_conn_get_security(const struct bt_conn *conn)
 {
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE | BT_CONN_TYPE_BR)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return BT_SECURITY_L0;
+	}
+
 	return conn->sec_level;
 }
 #else
@@ -2890,6 +2837,11 @@ struct bt_conn *bt_conn_lookup_state_le(uint8_t id, const bt_addr_le_t *peer,
 
 const bt_addr_le_t *bt_conn_get_dst(const struct bt_conn *conn)
 {
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return NULL;
+	}
+
 	return &conn->le.dst;
 }
 
@@ -2967,7 +2919,9 @@ int bt_conn_get_info(const struct bt_conn *conn, struct bt_conn_info *info)
 #if defined(CONFIG_BT_ISO)
 	case BT_CONN_TYPE_ISO:
 		if (IS_ENABLED(CONFIG_BT_ISO_UNICAST) &&
-		    conn->iso.info.type == BT_ISO_CHAN_TYPE_CONNECTED && conn->iso.acl != NULL) {
+		    (conn->iso.info.type == BT_ISO_CHAN_TYPE_CENTRAL ||
+		     conn->iso.info.type == BT_ISO_CHAN_TYPE_PERIPHERAL) &&
+		    conn->iso.acl != NULL) {
 			info->le.dst = &conn->iso.acl->le.dst;
 			info->le.src = &bt_dev.id_addr[conn->iso.acl->id];
 		} else {
@@ -2983,9 +2937,22 @@ int bt_conn_get_info(const struct bt_conn *conn, struct bt_conn_info *info)
 	return -EINVAL;
 }
 
-int bt_conn_get_remote_info(struct bt_conn *conn,
-			    struct bt_conn_remote_info *remote_info)
+bool bt_conn_is_type(const struct bt_conn *conn, enum bt_conn_type type)
+{
+	if (conn == NULL) {
+		return false;
+	}
+
+	return (conn->type & type) != 0;
+}
+
+int bt_conn_get_remote_info(const struct bt_conn *conn, struct bt_conn_remote_info *remote_info)
 {
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE | BT_CONN_TYPE_BR)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
 	if (!atomic_test_bit(conn->flags, BT_CONN_LE_FEATURES_EXCHANGED) ||
 	    (IS_ENABLED(CONFIG_BT_REMOTE_VERSION) &&
 	     !atomic_test_bit(conn->flags, BT_CONN_AUTO_VERSION_INFO))) {
@@ -3079,6 +3046,11 @@ int bt_conn_le_enhanced_get_tx_power_level(struct bt_conn *conn,
 	struct bt_hci_cp_le_read_tx_power_level *cp;
 	struct net_buf *buf;
 
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
 	if (!tx_power->phy) {
 		return -EINVAL;
 	}
@@ -3112,6 +3084,11 @@ int bt_conn_le_get_remote_tx_power_level(struct bt_conn *conn,
 	struct bt_hci_cp_le_read_tx_power_level *cp;
 	struct net_buf *buf;
 
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
 	if (!phy) {
 		return -EINVAL;
 	}
@@ -3135,6 +3112,11 @@ int bt_conn_le_set_tx_power_report_enable(struct bt_conn *conn,
 	struct bt_hci_cp_le_set_tx_power_report_enable *cp;
 	struct net_buf *buf;
 
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
 	buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_TX_POWER_REPORT_ENABLE, sizeof(*cp));
 	if (!buf) {
 		return -ENOBUFS;
@@ -3156,6 +3138,11 @@ int bt_conn_le_get_tx_power_level(struct bt_conn *conn,
 {
 	int err;
 
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
 	if (tx_power_level->phy != 0) {
 		if (IS_ENABLED(CONFIG_BT_TRANSMIT_POWER_CONTROL)) {
 			return bt_conn_le_enhanced_get_tx_power_level(conn, tx_power_level);
@@ -3201,6 +3188,11 @@ int bt_conn_le_set_path_loss_mon_param(struct bt_conn *conn,
 	struct bt_hci_cp_le_set_path_loss_reporting_parameters *cp;
 	struct net_buf *buf;
 
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
 	buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_PATH_LOSS_REPORTING_PARAMETERS, sizeof(*cp));
 	if (!buf) {
 		return -ENOBUFS;
@@ -3222,6 +3214,11 @@ int bt_conn_le_set_path_loss_mon_enable(struct bt_conn *conn, bool reporting_ena
 	struct bt_hci_cp_le_set_path_loss_reporting_enable *cp;
 	struct net_buf *buf;
 
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
 	buf = bt_hci_cmd_create(BT_HCI_OP_LE_SET_PATH_LOSS_REPORTING_ENABLE, sizeof(*cp));
 	if (!buf) {
 		return -ENOBUFS;
@@ -3318,6 +3315,11 @@ int bt_conn_le_subrate_request(struct bt_conn *conn,
 	struct bt_hci_cp_le_subrate_request *cp;
 	struct net_buf *buf;
 
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
 	if (!le_subrate_common_params_valid(params)) {
 		return -EINVAL;
 	}
@@ -3467,6 +3469,11 @@ void notify_cs_subevent_result(struct bt_conn *conn, struct bt_conn_le_cs_subeve
 int bt_conn_le_param_update(struct bt_conn *conn,
 			    const struct bt_le_conn_param *param)
 {
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
 	LOG_DBG("conn %p features 0x%02x params (%d-%d %d %d)", conn, conn->le.features[0],
 		param->interval_min, param->interval_max, param->latency, param->timeout);
 
@@ -3496,6 +3503,11 @@ int bt_conn_le_param_update(struct bt_conn *conn,
 int bt_conn_le_data_len_update(struct bt_conn *conn,
 			       const struct bt_conn_le_data_len_param *param)
 {
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
 	if (conn->le.data_len.tx_max_len == param->tx_max_len &&
 	    conn->le.data_len.tx_max_time == param->tx_max_time) {
 		return -EALREADY;
@@ -3511,6 +3523,11 @@ int bt_conn_le_phy_update(struct bt_conn *conn,
 {
 	uint8_t phy_opts, all_phys;
 
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
 	if ((param->options & BT_CONN_LE_PHY_OPT_CODED_S2) &&
 	    (param->options & BT_CONN_LE_PHY_OPT_CODED_S8)) {
 		phy_opts = BT_HCI_LE_PHY_CODED_ANY;
@@ -3985,7 +4002,8 @@ int bt_conn_auth_cb_register(const struct bt_conn_auth_cb *cb)
 #if defined(CONFIG_BT_SMP)
 int bt_conn_auth_cb_overlay(struct bt_conn *conn, const struct bt_conn_auth_cb *cb)
 {
-	CHECKIF(conn == NULL) {
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE | BT_CONN_TYPE_BR)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
 		return -EINVAL;
 	}
 
@@ -4036,6 +4054,11 @@ int bt_conn_auth_info_cb_unregister(struct bt_conn_auth_info_cb *cb)
 
 int bt_conn_auth_passkey_entry(struct bt_conn *conn, unsigned int passkey)
 {
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE | BT_CONN_TYPE_BR)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
 	if (IS_ENABLED(CONFIG_BT_SMP) && conn->type == BT_CONN_TYPE_LE) {
 		return bt_smp_auth_passkey_entry(conn, passkey);
 	}
@@ -4055,7 +4078,12 @@ int bt_conn_auth_passkey_entry(struct bt_conn *conn, unsigned int passkey)
 int bt_conn_auth_keypress_notify(struct bt_conn *conn,
 				 enum bt_conn_auth_keypress type)
 {
-	if (IS_ENABLED(CONFIG_BT_SMP) && conn->type == BT_CONN_TYPE_LE) {
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
+	if (IS_ENABLED(CONFIG_BT_SMP)) {
 		return bt_smp_auth_keypress_notify(conn, type);
 	}
 
@@ -4066,6 +4094,11 @@ int bt_conn_auth_keypress_notify(struct bt_conn *conn,
 
 int bt_conn_auth_passkey_confirm(struct bt_conn *conn)
 {
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE | BT_CONN_TYPE_BR)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
 	if (IS_ENABLED(CONFIG_BT_SMP) && conn->type == BT_CONN_TYPE_LE) {
 		return bt_smp_auth_passkey_confirm(conn);
 	}
@@ -4083,6 +4116,11 @@ int bt_conn_auth_passkey_confirm(struct bt_conn *conn)
 
 int bt_conn_auth_cancel(struct bt_conn *conn)
 {
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE | BT_CONN_TYPE_BR)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
 	if (IS_ENABLED(CONFIG_BT_SMP) && conn->type == BT_CONN_TYPE_LE) {
 		return bt_smp_auth_cancel(conn);
 	}
@@ -4100,6 +4138,11 @@ int bt_conn_auth_cancel(struct bt_conn *conn)
 
 int bt_conn_auth_pairing_confirm(struct bt_conn *conn)
 {
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE | BT_CONN_TYPE_BR)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
 	if (IS_ENABLED(CONFIG_BT_SMP) && conn->type == BT_CONN_TYPE_LE) {
 		return bt_smp_auth_pairing_confirm(conn);
 	}
diff --git a/subsys/bluetooth/host/conn_internal.h b/subsys/bluetooth/host/conn_internal.h
index 12ab95a8ac4..eddd2eb2c72 100644
--- a/subsys/bluetooth/host/conn_internal.h
+++ b/subsys/bluetooth/host/conn_internal.h
@@ -9,7 +9,20 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stddef.h>
+#include <stdint.h>
+
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/buf.h>
+#include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/iso.h>
+#include <zephyr/kernel.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/toolchain.h>
 
 typedef enum __packed {
 	BT_CONN_DISCONNECTED,         /* Disconnected, conn is completely down */
@@ -423,9 +436,6 @@ void bt_sco_cleanup(struct bt_conn *sco_conn);
 /* Look up an existing sco connection by BT address */
 struct bt_conn *bt_conn_lookup_addr_sco(const bt_addr_t *peer);
 
-/* Look up an existing connection by BT address */
-struct bt_conn *bt_conn_lookup_addr_br(const bt_addr_t *peer);
-
 void bt_conn_disconnect_all(uint8_t id);
 
 /* Allocate new connection object */
diff --git a/subsys/bluetooth/host/crypto_psa.c b/subsys/bluetooth/host/crypto_psa.c
index f71584c649c..2586da08f17 100644
--- a/subsys/bluetooth/host/crypto_psa.c
+++ b/subsys/bluetooth/host/crypto_psa.c
@@ -5,26 +5,28 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <string.h>
 #include <errno.h>
+#include <stdint.h>
+#include <string.h>
 
-#include <zephyr/kernel.h>
-#include <zephyr/sys/byteorder.h>
-#include <zephyr/sys/check.h>
-
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/bluetooth.h>
-#include <zephyr/bluetooth/hci.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/crypto.h>
-
-#include "psa/crypto.h"
+#include <zephyr/bluetooth/hci.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/check.h>
+#include <psa/crypto.h>
+#include <psa/crypto_struct.h>
+#include <psa/crypto_types.h>
+#include <psa/crypto_values.h>
 
 #include "common/bt_str.h"
-
 #include "hci_core.h"
 
 #define LOG_LEVEL CONFIG_BT_HCI_CORE_LOG_LEVEL
-#include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(bt_host_crypto);
 
 int bt_crypto_init(void)
diff --git a/subsys/bluetooth/host/cs.c b/subsys/bluetooth/host/cs.c
index e9caaba5b96..7b84bbafe62 100644
--- a/subsys/bluetooth/host/cs.c
+++ b/subsys/bluetooth/host/cs.c
@@ -5,16 +5,28 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-
-#include <zephyr/sys/byteorder.h>
+#include <errno.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/cs.h>
 #include <zephyr/bluetooth/hci.h>
 #include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
 
 #include "conn_internal.h"
 
 #define LOG_LEVEL CONFIG_BT_HCI_CORE_LOG_LEVEL
-#include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(bt_cs);
 
 #if defined(CONFIG_BT_CHANNEL_SOUNDING)
diff --git a/subsys/bluetooth/host/data.c b/subsys/bluetooth/host/data.c
index 4afd9aad0a7..20c49fc6c41 100644
--- a/subsys/bluetooth/host/data.c
+++ b/subsys/bluetooth/host/data.c
@@ -4,13 +4,18 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
 
-#include <zephyr/sys/check.h>
-
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/check.h>
 
 #define LOG_LEVEL CONFIG_BT_HCI_CORE_LOG_LEVEL
-#include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(bt_data);
 
 void bt_data_parse(struct net_buf_simple *ad,
diff --git a/subsys/bluetooth/host/direction.c b/subsys/bluetooth/host/direction.c
index a2dee2561ce..a59cbdada37 100644
--- a/subsys/bluetooth/host/direction.c
+++ b/subsys/bluetooth/host/direction.c
@@ -3,25 +3,30 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <errno.h>
+#include <stdbool.h>
 #include <stdint.h>
-#include <assert.h>
-#include <zephyr/sys/check.h>
-#include <zephyr/sys/byteorder.h>
+#include <string.h>
 
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
-#include <zephyr/bluetooth/l2cap.h>
+#include <zephyr/bluetooth/direction.h>
 #include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/hci_vs.h>
-#include <zephyr/bluetooth/direction.h>
+#include <zephyr/bluetooth/l2cap.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/check.h>
 
 #include "hci_core.h"
-#include "scan.h"
 #include "conn_internal.h"
 #include "direction_internal.h"
 
-#include <zephyr/logging/log.h>
-
 LOG_MODULE_REGISTER(bt_df, CONFIG_BT_DF_LOG_LEVEL);
 
 /* @brief Antenna information for LE Direction Finding */
@@ -182,9 +187,9 @@ static int hci_df_read_ant_info(uint8_t *switch_sample_rates,
 
 	rp = (void *)rsp->data;
 
-	LOG_DBG("DF: sw. sampl rates: %x ant num: %u , max sw. pattern len: %u,"
-	       "max CTE len %d", rp->switch_sample_rates, rp->num_ant,
-	       rp->max_switch_pattern_len, rp->max_cte_len);
+	LOG_DBG("DF: sw. sample rates: %x ant num: %u , max sw. pattern len: %u,"
+		"max CTE len %d",
+		rp->switch_sample_rates, rp->num_ant, rp->max_switch_pattern_len, rp->max_cte_len);
 
 	*switch_sample_rates = rp->switch_sample_rates;
 	*num_ant = rp->num_ant;
diff --git a/subsys/bluetooth/host/direction_internal.h b/subsys/bluetooth/host/direction_internal.h
index 30284f402d4..2a6303ff4c3 100644
--- a/subsys/bluetooth/host/direction_internal.h
+++ b/subsys/bluetooth/host/direction_internal.h
@@ -4,6 +4,10 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/direction.h>
+#include <zephyr/net_buf.h>
+
 /* Performs initialization of Direction Finding in Host */
 int le_df_init(void);
 
diff --git a/subsys/bluetooth/host/ecc.c b/subsys/bluetooth/host/ecc.c
index d06af6a52e0..87b9fb1cb5d 100644
--- a/subsys/bluetooth/host/ecc.c
+++ b/subsys/bluetooth/host/ecc.c
@@ -5,20 +5,32 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <errno.h>
+#include <stdbool.h>
 #include <stdint.h>
+#include <string.h>
 
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/atomic.h>
 #include <zephyr/sys/byteorder.h>
 #include <zephyr/sys/check.h>
 #include <zephyr/bluetooth/hci.h>
-
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/sys/util_macro.h>
 #include <psa/crypto.h>
+#include <psa/crypto_struct.h>
+#include <psa/crypto_types.h>
+#include <psa/crypto_values.h>
 
 #include "long_wq.h"
 #include "ecc.h"
 #include "hci_core.h"
 
 #define LOG_LEVEL CONFIG_BT_HCI_CORE_LOG_LEVEL
-#include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(bt_ecc);
 
 static uint8_t pub_key[BT_PUB_KEY_LEN];
diff --git a/subsys/bluetooth/host/ecc.h b/subsys/bluetooth/host/ecc.h
index a5866097847..8feb3823a6a 100644
--- a/subsys/bluetooth/host/ecc.h
+++ b/subsys/bluetooth/host/ecc.h
@@ -6,6 +6,11 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <zephyr/sys/slist.h>
+
 /** Key size used in Bluetooth's ECC domain. */
 #define BT_ECC_KEY_SIZE            32
 /** Length of a Bluetooth ECC public key coordinate. */
@@ -46,7 +51,7 @@ bool bt_pub_key_is_debug(uint8_t *cmp_pub_key);
 
 /*  @brief Check if public key is valid.
  *
- *  Verify that the public key is valid, e.g. that its coordinates lie on the eliptic curve.
+ *  Verify that the public key is valid, e.g. that its coordinates lie on the elliptic curve.
  *
  *  @param key The public key to validate.
  *
diff --git a/subsys/bluetooth/host/gatt.c b/subsys/bluetooth/host/gatt.c
index fa8fb1c7bd6..3092801554a 100644
--- a/subsys/bluetooth/host/gatt.c
+++ b/subsys/bluetooth/host/gatt.c
@@ -7,46 +7,57 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include "sys/types.h"
+#include <errno.h>
+#include <inttypes.h>
+#include <stdbool.h>
 #include <stdint.h>
+#include <stdlib.h>
+#include <string.h>
 
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/att.h>
+#include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/bluetooth/uuid.h>
+#include <zephyr/bluetooth/gatt.h>
 #include <zephyr/kernel.h>
-#include <string.h>
-#include <errno.h>
-#include <stdbool.h>
-#include <stdlib.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/settings/settings.h>
+#include <zephyr/sys/__assert.h>
 #include <zephyr/sys/atomic.h>
 #include <zephyr/sys/byteorder.h>
 #include <zephyr/sys/iterable_sections.h>
+#include <zephyr/sys/slist.h>
 #include <zephyr/sys/util.h>
 #include <zephyr/sys/check.h>
-
-#include <zephyr/settings/settings.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/toolchain.h>
 
 #if defined(CONFIG_BT_GATT_CACHING)
-#include "psa/crypto.h"
+#include <psa/crypto.h>
+#include <psa/crypto_struct.h>
+#include <psa/crypto_types.h>
+#include <psa/crypto_values.h>
 #endif /* CONFIG_BT_GATT_CACHING */
 
-#include <zephyr/bluetooth/hci.h>
-#include <zephyr/bluetooth/bluetooth.h>
-#include <zephyr/bluetooth/conn.h>
-#include <zephyr/bluetooth/uuid.h>
-#include <zephyr/bluetooth/gatt.h>
-
+#include "att_internal.h"
+#include "conn_internal.h"
 #include "common/bt_str.h"
-
+#include "gatt_internal.h"
 #include "hci_core.h"
-#include "conn_internal.h"
 #include "keys.h"
+#include "long_wq.h"
 #include "l2cap_internal.h"
-#include "att_internal.h"
-#include "smp.h"
 #include "settings.h"
-#include "gatt_internal.h"
-#include "long_wq.h"
+#include "smp.h"
 
 #define LOG_LEVEL CONFIG_BT_GATT_LOG_LEVEL
-#include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(bt_gatt);
 
 #define SC_TIMEOUT	K_MSEC(10)
@@ -384,7 +395,7 @@ static int bt_gatt_clear_sc(uint8_t id, const bt_addr_le_t *addr)
 
 static void sc_clear(struct bt_conn *conn)
 {
-	if (bt_addr_le_is_bonded(conn->id, &conn->le.dst)) {
+	if (bt_le_bond_exists(conn->id, &conn->le.dst)) {
 		int err;
 
 		err = bt_gatt_clear_sc(conn->id, &conn->le.dst);
@@ -466,8 +477,7 @@ static void sc_save(uint8_t id, bt_addr_le_t *peer, uint16_t start, uint16_t end
 	modified = update_range(&cfg->data.start, &cfg->data.end, start, end);
 
 done:
-	if (IS_ENABLED(CONFIG_BT_SETTINGS) &&
-	    modified && bt_addr_le_is_bonded(cfg->id, &cfg->peer)) {
+	if (IS_ENABLED(CONFIG_BT_SETTINGS) && modified && bt_le_bond_exists(cfg->id, &cfg->peer)) {
 		sc_store(cfg);
 	}
 }
@@ -487,9 +497,8 @@ static ssize_t sc_ccc_cfg_write(struct bt_conn *conn,
 	return sizeof(value);
 }
 
-static struct _bt_gatt_ccc sc_ccc = BT_GATT_CCC_INITIALIZER(NULL,
-							    sc_ccc_cfg_write,
-							    NULL);
+static struct bt_gatt_ccc_managed_user_data sc_ccc =
+	BT_GATT_CCC_MANAGED_USER_DATA_INIT(NULL, sc_ccc_cfg_write, NULL);
 
 /* Do not shuffle the values in this enum, they are used as bit offsets when
  * saving the CF flags to NVS (i.e. NVS persists between FW upgrades).
@@ -1030,7 +1039,7 @@ static void remove_cf_cfg(struct bt_conn *conn)
 	 * trusted relationship the characteristic value shall be set to the
 	 * default value at each connection.
 	 */
-	if (!bt_addr_le_is_bonded(conn->id, &conn->le.dst)) {
+	if (!bt_le_bond_exists(conn->id, &conn->le.dst)) {
 		clear_cf_cfg(cfg);
 	} else {
 		/* Update address in case it has changed */
@@ -1119,7 +1128,7 @@ struct addr_match {
 static uint8_t convert_to_id_on_match(const struct bt_gatt_attr *attr,
 				      uint16_t handle, void *user_data)
 {
-	struct _bt_gatt_ccc *ccc;
+	struct bt_gatt_ccc_managed_user_data *ccc;
 	struct addr_match *match = user_data;
 
 	if (!is_host_managed_ccc(attr)) {
@@ -1148,7 +1157,7 @@ static void bt_gatt_identity_resolved(struct bt_conn *conn, const bt_addr_le_t *
 		.private_addr = private_addr,
 		.id_addr      = id_addr
 	};
-	bool is_bonded = bt_addr_le_is_bonded(conn->id, &conn->le.dst);
+	bool is_bonded = bt_le_bond_exists(conn->id, &conn->le.dst);
 
 	bt_gatt_foreach_attr(0x0001, 0xffff, convert_to_id_on_match, &user_data);
 
@@ -1448,7 +1457,7 @@ static struct ds_peer *gatt_delayed_store_alloc(uint8_t id,
 static void gatt_delayed_store_enqueue(uint8_t id, const bt_addr_le_t *peer_addr,
 				       enum delayed_store_flags flag)
 {
-	bool bonded = bt_addr_le_is_bonded(id, peer_addr);
+	bool bonded = bt_le_bond_exists(id, peer_addr);
 	struct ds_peer *el = gatt_delayed_store_find(id, peer_addr);
 
 	if (bonded) {
@@ -1483,7 +1492,7 @@ static void gatt_store_ccc_cf(uint8_t id, const bt_addr_le_t *peer_addr)
 {
 	struct ds_peer *el = gatt_delayed_store_find(id, peer_addr);
 
-	if (bt_addr_le_is_bonded(id, peer_addr)) {
+	if (bt_le_bond_exists(id, peer_addr)) {
 		if (!IS_ENABLED(CONFIG_BT_SETTINGS_CCC_STORE_ON_WRITE) ||
 		    (IS_ENABLED(CONFIG_BT_SETTINGS_CCC_STORE_ON_WRITE) && el &&
 		     atomic_test_and_clear_bit(el->flags, DELAYED_STORE_CCC))) {
@@ -1645,7 +1654,7 @@ static void db_changed(void)
 #endif
 }
 
-static void gatt_unregister_ccc(struct _bt_gatt_ccc *ccc)
+static void gatt_unregister_ccc(struct bt_gatt_ccc_managed_user_data *ccc)
 {
 	ccc->value = 0;
 
@@ -1671,7 +1680,7 @@ static void gatt_unregister_ccc(struct _bt_gatt_ccc *ccc)
 			}
 
 			if (IS_ENABLED(CONFIG_BT_SETTINGS) && store &&
-			    bt_addr_le_is_bonded(cfg->id, &cfg->peer)) {
+			    bt_le_bond_exists(cfg->id, &cfg->peer)) {
 				bt_gatt_store_ccc(cfg->id, &cfg->peer);
 			}
 
@@ -2128,7 +2137,7 @@ struct bt_gatt_attr *bt_gatt_attr_next(const struct bt_gatt_attr *attr)
 }
 
 static struct bt_gatt_ccc_cfg *find_ccc_cfg(const struct bt_conn *conn,
-					    struct _bt_gatt_ccc *ccc)
+					    struct bt_gatt_ccc_managed_user_data *ccc)
 {
 	for (size_t i = 0; i < ARRAY_SIZE(ccc->cfg); i++) {
 		struct bt_gatt_ccc_cfg *cfg = &ccc->cfg[i];
@@ -2150,7 +2159,7 @@ ssize_t bt_gatt_attr_read_ccc(struct bt_conn *conn,
 			      const struct bt_gatt_attr *attr, void *buf,
 			      uint16_t len, uint16_t offset)
 {
-	struct _bt_gatt_ccc *ccc = attr->user_data;
+	struct bt_gatt_ccc_managed_user_data *ccc = attr->user_data;
 	const struct bt_gatt_ccc_cfg *cfg;
 	uint16_t value;
 
@@ -2167,7 +2176,7 @@ ssize_t bt_gatt_attr_read_ccc(struct bt_conn *conn,
 }
 
 static void gatt_ccc_changed(const struct bt_gatt_attr *attr,
-			     struct _bt_gatt_ccc *ccc)
+			     struct bt_gatt_ccc_managed_user_data *ccc)
 {
 	int i;
 	uint16_t value = 0x0000;
@@ -2201,7 +2210,7 @@ ssize_t bt_gatt_attr_write_ccc(struct bt_conn *conn,
 			       const struct bt_gatt_attr *attr, const void *buf,
 			       uint16_t len, uint16_t offset, uint8_t flags)
 {
-	struct _bt_gatt_ccc *ccc = attr->user_data;
+	struct bt_gatt_ccc_managed_user_data *ccc = attr->user_data;
 	struct bt_gatt_ccc_cfg *cfg;
 	bool value_changed;
 	uint16_t value;
@@ -2733,7 +2742,7 @@ static uint8_t notify_cb(const struct bt_gatt_attr *attr, uint16_t handle,
 			 void *user_data)
 {
 	struct notify_data *data = user_data;
-	struct _bt_gatt_ccc *ccc;
+	struct bt_gatt_ccc_managed_user_data *ccc;
 	size_t i;
 
 	if (!is_host_managed_ccc(attr)) {
@@ -3322,7 +3331,7 @@ static uint8_t update_ccc(const struct bt_gatt_attr *attr, uint16_t handle,
 {
 	struct conn_data *data = user_data;
 	struct bt_conn *conn = data->conn;
-	struct _bt_gatt_ccc *ccc;
+	struct bt_gatt_ccc_managed_user_data *ccc;
 	size_t i;
 	uint8_t err;
 
@@ -3384,7 +3393,7 @@ static uint8_t disconnected_cb(const struct bt_gatt_attr *attr, uint16_t handle,
 			       void *user_data)
 {
 	struct bt_conn *conn = user_data;
-	struct _bt_gatt_ccc *ccc;
+	struct bt_gatt_ccc_managed_user_data *ccc;
 	bool value_used;
 	size_t i;
 
@@ -3424,7 +3433,7 @@ static uint8_t disconnected_cb(const struct bt_gatt_attr *attr, uint16_t handle,
 			}
 		} else {
 			/* Clear value if not paired */
-			if (!bt_addr_le_is_bonded(conn->id, &conn->le.dst)) {
+			if (!bt_le_bond_exists(conn->id, &conn->le.dst)) {
 				if (ccc == &sc_ccc) {
 					sc_clear(conn);
 				}
@@ -3472,7 +3481,7 @@ bool bt_gatt_is_subscribed(struct bt_conn *conn,
 			LOG_ERR("Read method not set");
 			return false;
 		}
-		/* The charactestic properties is the first byte of the attribute value */
+		/* The characterstic properties is the first byte of the attribute value */
 		len = attr->read(NULL, attr, &properties, sizeof(properties), 0);
 		if (len < 0) {
 			LOG_ERR("Failed to read attribute %p (err %zd)", attr, len);
@@ -3740,9 +3749,8 @@ static void remove_subscriptions(struct bt_conn *conn)
 	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&sub->list, params, tmp, node) {
 		atomic_clear_bit(params->flags, BT_GATT_SUBSCRIBE_FLAG_SENT);
 
-		if (!bt_addr_le_is_bonded(conn->id, &conn->le.dst) ||
-		    (atomic_test_bit(params->flags,
-				     BT_GATT_SUBSCRIBE_FLAG_VOLATILE))) {
+		if (!bt_le_bond_exists(conn->id, &conn->le.dst) ||
+		    (atomic_test_bit(params->flags, BT_GATT_SUBSCRIBE_FLAG_VOLATILE))) {
 			/* Remove subscription */
 			params->value = 0U;
 			gatt_sub_remove(conn, sub, prev, params);
@@ -5261,10 +5269,18 @@ static int gatt_prepare_write(struct bt_conn *conn,
 			      struct bt_gatt_write_params *params)
 {
 	uint16_t len, req_len;
+	uint16_t mtu = bt_att_get_mtu(conn);
 
 	req_len = sizeof(struct bt_att_prepare_write_req);
 
-	len = bt_att_get_mtu(conn) - req_len - 1;
+	/** MTU size is bigger than the ATT_PREPARE_WRITE_REQ header (5 bytes),
+	 * unless there's no connection.
+	 */
+	if (mtu == 0) {
+		return -ENOTCONN;
+	}
+
+	len = mtu - req_len - 1;
 	len = MIN(params->length, len);
 	len += req_len;
 
@@ -5667,7 +5683,7 @@ static void add_subscriptions(struct bt_conn *conn)
 	struct gatt_sub *sub;
 	struct bt_gatt_subscribe_params *params;
 
-	if (!bt_addr_le_is_bonded(conn->id, &conn->le.dst)) {
+	if (!bt_le_bond_exists(conn->id, &conn->le.dst)) {
 		return;
 	}
 
@@ -5718,7 +5734,7 @@ static struct bt_gatt_exchange_params gatt_exchange_params = {
 #define CCC_STORE_MAX 0
 #endif /* defined(CONFIG_BT_SETTINGS_CCC_STORE_MAX) */
 
-static struct bt_gatt_ccc_cfg *ccc_find_cfg(struct _bt_gatt_ccc *ccc,
+static struct bt_gatt_ccc_cfg *ccc_find_cfg(struct bt_gatt_ccc_managed_user_data *ccc,
 					    const bt_addr_le_t *addr,
 					    uint8_t id)
 {
@@ -5743,7 +5759,7 @@ struct ccc_load {
 	size_t count;
 };
 
-static void ccc_clear(struct _bt_gatt_ccc *ccc,
+static void ccc_clear(struct bt_gatt_ccc_managed_user_data *ccc,
 		      const bt_addr_le_t *addr,
 		      uint8_t id)
 {
@@ -5762,7 +5778,7 @@ static uint8_t ccc_load(const struct bt_gatt_attr *attr, uint16_t handle,
 			void *user_data)
 {
 	struct ccc_load *load = user_data;
-	struct _bt_gatt_ccc *ccc;
+	struct bt_gatt_ccc_managed_user_data *ccc;
 	struct bt_gatt_ccc_cfg *cfg;
 
 	if (!is_host_managed_ccc(attr)) {
@@ -5882,6 +5898,7 @@ static int ccc_set(const char *name, size_t len_rd, settings_read_cb read_cb,
 	return 0;
 }
 
+#ifdef CONFIG_BT_SETTINGS
 static int ccc_set_cb(const char *name, size_t len_rd, settings_read_cb read_cb,
 		      void *cb_arg)
 {
@@ -5894,6 +5911,7 @@ static int ccc_set_cb(const char *name, size_t len_rd, settings_read_cb read_cb,
 }
 
 BT_SETTINGS_DEFINE(ccc, "ccc", ccc_set_cb, NULL);
+#endif /* CONFIG_BT_SETTINGS */
 
 static int ccc_set_direct(const char *key, size_t len, settings_read_cb read_cb,
 			  void *cb_arg, void *param)
@@ -5925,7 +5943,7 @@ void bt_gatt_connected(struct bt_conn *conn)
 
 	/* Load CCC settings from backend if bonded */
 	if (IS_ENABLED(CONFIG_BT_SETTINGS_CCC_LAZY_LOADING) &&
-	    bt_addr_le_is_bonded(conn->id, &conn->le.dst)) {
+	    bt_le_bond_exists(conn->id, &conn->le.dst)) {
 		char key[BT_SETTINGS_KEY_MAX];
 
 		if (conn->id) {
@@ -6099,7 +6117,7 @@ static uint8_t ccc_save(const struct bt_gatt_attr *attr, uint16_t handle,
 			void *user_data)
 {
 	struct ccc_save *save = user_data;
-	struct _bt_gatt_ccc *ccc;
+	struct bt_gatt_ccc_managed_user_data *ccc;
 	struct bt_gatt_ccc_cfg *cfg;
 
 	if (!is_host_managed_ccc(attr)) {
@@ -6382,7 +6400,7 @@ static uint8_t remove_peer_from_attr(const struct bt_gatt_attr *attr,
 				     uint16_t handle, void *user_data)
 {
 	const struct addr_with_id *addr_with_id = user_data;
-	struct _bt_gatt_ccc *ccc;
+	struct bt_gatt_ccc_managed_user_data *ccc;
 	struct bt_gatt_ccc_cfg *cfg;
 
 	if (!is_host_managed_ccc(attr)) {
@@ -6513,7 +6531,7 @@ void bt_gatt_disconnected(struct bt_conn *conn)
 
 	/* Make sure to clear the CCC entry when using lazy loading */
 	if (IS_ENABLED(CONFIG_BT_SETTINGS_CCC_LAZY_LOADING) &&
-	    bt_addr_le_is_bonded(conn->id, &conn->le.dst)) {
+	    bt_le_bond_exists(conn->id, &conn->le.dst)) {
 		struct addr_with_id addr_with_id = {
 			.addr = &conn->le.dst,
 			.id = conn->id,
diff --git a/subsys/bluetooth/host/gatt_internal.h b/subsys/bluetooth/host/gatt_internal.h
index 718ce95a5d7..6e3daa56ff7 100644
--- a/subsys/bluetooth/host/gatt_internal.h
+++ b/subsys/bluetooth/host/gatt_internal.h
@@ -8,6 +8,12 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/conn.h>
+
 #define BT_GATT_CENTRAL_ADDR_RES_NOT_SUPP	0
 #define BT_GATT_CENTRAL_ADDR_RES_SUPP		1
 
diff --git a/subsys/bluetooth/host/hci_common.c b/subsys/bluetooth/host/hci_common.c
index 1f382075d05..bac2a21da66 100644
--- a/subsys/bluetooth/host/hci_common.c
+++ b/subsys/bluetooth/host/hci_common.c
@@ -4,9 +4,16 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stdbool.h>
 #include <stdint.h>
-#include <zephyr/sys/byteorder.h>
+
+#include <zephyr/bluetooth/buf.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/drivers/bluetooth.h>
+#include <zephyr/kernel.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/byteorder.h>
+
 #include "common/assert.h"
 
 struct net_buf *bt_hci_evt_create(uint8_t evt, uint8_t len)
@@ -33,7 +40,17 @@ struct net_buf *bt_hci_cmd_complete_create(uint16_t op, uint8_t plen)
 	buf = bt_hci_evt_create(BT_HCI_EVT_CMD_COMPLETE, sizeof(*cc) + plen);
 
 	cc = net_buf_add(buf, sizeof(*cc));
+
+	/* The Num_HCI_Command_Packets parameter allows the Controller to
+	 * indicate the number of HCI command packets the Host can send to the
+	 * Controller. If the Controller requires the Host to stop sending
+	 * commands, Num_HCI_Command_Packets will be set to zero.
+	 *
+	 * NOTE: Zephyr Controller (and may be other Controllers) do not support
+	 *       higher Number of HCI Command packets than 1.
+	 */
 	cc->ncmd = 1U;
+
 	cc->opcode = sys_cpu_to_le16(op);
 
 	return buf;
@@ -48,7 +65,17 @@ struct net_buf *bt_hci_cmd_status_create(uint16_t op, uint8_t status)
 
 	cs = net_buf_add(buf, sizeof(*cs));
 	cs->status = status;
+
+	/* The Num_HCI_Command_Packets parameter allows the Controller to
+	 * indicate the number of HCI command packets the Host can send to the
+	 * Controller. If the Controller requires the Host to stop sending
+	 * commands, Num_HCI_Command_Packets will be set to zero.
+	 *
+	 * NOTE: Zephyr Controller (and may be other Controllers) do not support
+	 *       higher Number of HCI Command packets than 1.
+	 */
 	cs->ncmd = 1U;
+
 	cs->opcode = sys_cpu_to_le16(op);
 
 	return buf;
diff --git a/subsys/bluetooth/host/hci_core.c b/subsys/bluetooth/host/hci_core.c
index aa22f31b570..45be1425f46 100644
--- a/subsys/bluetooth/host/hci_core.c
+++ b/subsys/bluetooth/host/hci_core.c
@@ -7,55 +7,64 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
 
 #include <zephyr/autoconf.h>
-
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/buf.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/direction.h>
+#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/l2cap.h>
+#include <zephyr/bluetooth/hci.h>
 #include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/bluetooth/hci_vs.h>
+#include <zephyr/bluetooth/testing.h>
+#include <zephyr/debug/stack.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/bluetooth.h>
 #include <zephyr/kernel.h>
-#include <string.h>
-#include <stdio.h>
-#include <errno.h>
+#include <zephyr/kernel/thread.h>
+#include <zephyr/kernel/thread_stack.h>
+#include <zephyr/logging/log.h>
 #include <zephyr/net_buf.h>
+#include <zephyr/settings/settings.h>
 #include <zephyr/sys/atomic.h>
 #include <zephyr/sys/check.h>
 #include <zephyr/sys/util_macro.h>
 #include <zephyr/sys/util.h>
 #include <zephyr/sys/slist.h>
 #include <zephyr/sys/byteorder.h>
-#include <zephyr/debug/stack.h>
 #include <zephyr/sys/__assert.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/toolchain.h>
 #include <soc.h>
 
-#include <zephyr/settings/settings.h>
-
-#include <zephyr/bluetooth/bluetooth.h>
-#include <zephyr/bluetooth/conn.h>
-#include <zephyr/bluetooth/l2cap.h>
-#include <zephyr/bluetooth/hci.h>
-#include <zephyr/bluetooth/hci_vs.h>
-#include <zephyr/bluetooth/testing.h>
-#include <zephyr/drivers/bluetooth.h>
-
+#include "addr_internal.h"
+#include "adv.h"
+#include "common/hci_common_internal.h"
 #include "common/bt_str.h"
-#include "common/assert.h"
-
 #include "common/rpa.h"
-#include "keys.h"
-#include "monitor.h"
-#include "hci_core.h"
+#include "common/assert.h"
+#include "conn_internal.h"
+#include "crypto.h"
 #include "ecc.h"
+#include "gatt_internal.h"
+#include "hci_core.h"
 #include "id.h"
-#include "adv.h"
-#include "scan.h"
-
-#include "addr_internal.h"
-#include "conn_internal.h"
 #include "iso_internal.h"
+#include "keys.h"
 #include "l2cap_internal.h"
-#include "gatt_internal.h"
-#include "smp.h"
-#include "crypto.h"
+#include "monitor.h"
+#include "scan.h"
 #include "settings.h"
+#include "smp.h"
 
 #if defined(CONFIG_BT_CLASSIC)
 #include "classic/br.h"
@@ -66,7 +75,6 @@
 #endif /* CONFIG_BT_DF */
 
 #define LOG_LEVEL CONFIG_BT_HCI_CORE_LOG_LEVEL
-#include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(bt_hci_core);
 
 #if DT_HAS_CHOSEN(zephyr_bt_hci)
@@ -129,7 +137,7 @@ struct cmd_data {
 	struct k_sem *sync;
 };
 
-static struct cmd_data cmd_data[CONFIG_BT_BUF_CMD_TX_COUNT];
+static struct cmd_data cmd_data[BT_BUF_CMD_TX_COUNT];
 
 #define cmd(buf) (&cmd_data[net_buf_id(buf)])
 #define acl(buf) ((struct acl_data *)net_buf_user_data(buf))
@@ -159,7 +167,7 @@ void bt_hci_cmd_state_set_init(struct net_buf *buf,
  * command complete or command status.
  */
 #define CMD_BUF_SIZE MAX(BT_BUF_EVT_RX_SIZE, BT_BUF_CMD_TX_SIZE)
-NET_BUF_POOL_FIXED_DEFINE(hci_cmd_pool, CONFIG_BT_BUF_CMD_TX_COUNT,
+NET_BUF_POOL_FIXED_DEFINE(hci_cmd_pool, BT_BUF_CMD_TX_COUNT,
 			  CMD_BUF_SIZE, sizeof(struct bt_buf_data), NULL);
 
 struct event_handler {
@@ -566,7 +574,7 @@ static void hci_num_completed_packets(struct net_buf *buf)
 	int i;
 
 	if (sizeof(*evt) + sizeof(evt->h[0]) * evt->num_handles > buf->len) {
-		LOG_ERR("evt num_handles (=%u) too large (%u > %u)",
+		LOG_ERR("evt num_handles (=%u) too large (%zu > %u)",
 			evt->num_handles,
 			sizeof(*evt) + sizeof(evt->h[0]) * evt->num_handles,
 			buf->len);
@@ -1012,7 +1020,7 @@ static void hci_disconn_complete(struct net_buf *buf)
 		 * If only for one connection session bond was set, clear keys
 		 * database row for this connection.
 		 */
-		if (conn->type == BT_CONN_TYPE_BR &&
+		if (conn->type == BT_CONN_TYPE_BR && conn->br.link_key != NULL &&
 		    atomic_test_and_clear_bit(conn->flags, BT_CONN_BR_NOBOND)) {
 			bt_keys_link_key_clear(conn->br.link_key);
 		}
@@ -2004,7 +2012,7 @@ static int set_flow_control(void)
 	hbs = net_buf_add(buf, sizeof(*hbs));
 	(void)memset(hbs, 0, sizeof(*hbs));
 	hbs->acl_mtu = sys_cpu_to_le16(CONFIG_BT_BUF_ACL_RX_SIZE);
-	hbs->acl_pkts = sys_cpu_to_le16(BT_BUF_ACL_RX_COUNT);
+	hbs->acl_pkts = sys_cpu_to_le16(BT_BUF_HCI_ACL_RX_COUNT);
 
 	err = bt_hci_cmd_send_sync(BT_HCI_OP_HOST_BUFFER_SIZE, buf, NULL);
 	if (err) {
@@ -2040,13 +2048,6 @@ static void unpair(uint8_t id, const bt_addr_le_t *addr)
 		bt_conn_unref(conn);
 	}
 
-	if (IS_ENABLED(CONFIG_BT_CLASSIC)) {
-		/* LE Public may indicate BR/EDR as well */
-		if (addr->type == BT_ADDR_LE_PUBLIC) {
-			bt_keys_link_key_clear_addr(&addr->a);
-		}
-	}
-
 	if (IS_ENABLED(CONFIG_BT_SMP)) {
 		if (!keys) {
 			keys = bt_keys_find_addr(id, addr);
@@ -2271,6 +2272,17 @@ static void hci_encrypt_key_refresh_complete(struct net_buf *buf)
 			bt_conn_unref(conn);
 			return;
 		}
+
+		if (IS_ENABLED(CONFIG_BT_SMP)) {
+			/*
+			 * Start SMP over BR/EDR if we are pairing and are
+			 * central on the link
+			 */
+			if (atomic_test_bit(conn->flags, BT_CONN_BR_PAIRED) &&
+			    conn->role == BT_CONN_ROLE_CENTRAL) {
+				bt_smp_br_send_pairing_req(conn);
+			}
+		}
 	}
 #endif /* CONFIG_BT_CLASSIC */
 
@@ -4540,7 +4552,7 @@ int bt_le_get_local_features(struct bt_le_local_features *remote_info)
 	return 0;
 }
 
-bool bt_addr_le_is_bonded(uint8_t id, const bt_addr_le_t *addr)
+bool bt_le_bond_exists(uint8_t id, const bt_addr_le_t *addr)
 {
 	if (IS_ENABLED(CONFIG_BT_SMP)) {
 		struct bt_keys *keys = bt_keys_find_addr(id, addr);
diff --git a/subsys/bluetooth/host/hci_core.h b/subsys/bluetooth/host/hci_core.h
index 6502be80c3f..226353f96e6 100644
--- a/subsys/bluetooth/host/hci_core.h
+++ b/subsys/bluetooth/host/hci_core.h
@@ -6,10 +6,20 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stdbool.h>
 #include <stdint.h>
 
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/devicetree.h>
+#include <zephyr/kernel.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/sys/util_macro.h>
 
 /* LL connection parameters */
 #define LE_CONN_LATENCY		0x0000
@@ -76,6 +86,7 @@ enum {
 	BT_DEV_ISCAN,
 	BT_DEV_PSCAN,
 	BT_DEV_INQUIRY,
+	BT_DEV_LIMITED_DISCOVERABLE_MODE,
 #endif /* CONFIG_BT_CLASSIC */
 
 	/* Total number of flags - must be at the end of the enum */
@@ -84,7 +95,8 @@ enum {
 
 /* Flags which should not be cleared upon HCI_Reset */
 #define BT_DEV_PERSISTENT_FLAGS (BIT(BT_DEV_ENABLE) | \
-				 BIT(BT_DEV_PRESET_ID))
+				 BIT(BT_DEV_PRESET_ID) | \
+				 BIT(BT_DEV_DISABLE))
 
 #if defined(CONFIG_BT_EXT_ADV_LEGACY_SUPPORT)
 /* Check the feature bit for extended or legacy advertising commands */
@@ -479,7 +491,6 @@ int bt_le_create_conn_cancel(void);
 int bt_le_create_conn_synced(const struct bt_conn *conn, const struct bt_le_ext_adv *adv,
 			     uint8_t subevent);
 
-bool bt_addr_le_is_bonded(uint8_t id, const bt_addr_le_t *addr);
 const bt_addr_le_t *bt_lookup_id_addr(uint8_t id, const bt_addr_le_t *addr);
 
 int bt_send(struct net_buf *buf);
diff --git a/subsys/bluetooth/host/hci_raw.c b/subsys/bluetooth/host/hci_raw.c
index 3e913151156..fde25bbc62f 100644
--- a/subsys/bluetooth/host/hci_raw.c
+++ b/subsys/bluetooth/host/hci_raw.c
@@ -7,23 +7,33 @@
  */
 
 #include <errno.h>
-#include <zephyr/sys/atomic.h>
-#include <zephyr/sys/byteorder.h>
-#include <zephyr/devicetree.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
 
-#include <zephyr/drivers/bluetooth.h>
 #include <zephyr/bluetooth/buf.h>
+#include <zephyr/bluetooth/hci.h>
 #include <zephyr/bluetooth/hci_raw.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/l2cap.h>
 #include <zephyr/bluetooth/iso.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/bluetooth.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/toolchain.h>
 
-#include <zephyr/bluetooth/hci.h>
-
-#include "monitor.h"
+#include "common/hci_common_internal.h"
 #include "hci_raw_internal.h"
+#include "monitor.h"
 
 #define LOG_LEVEL CONFIG_BT_HCI_CORE_LOG_LEVEL
-#include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(bt_hci_raw);
 
 static struct k_fifo *raw_rx;
@@ -48,7 +58,7 @@ static void hci_rx_buf_destroy(struct net_buf *buf)
 
 NET_BUF_POOL_FIXED_DEFINE(hci_rx_pool, BT_BUF_RX_COUNT, BT_BUF_RX_SIZE, sizeof(struct bt_buf_data),
 			  hci_rx_buf_destroy);
-NET_BUF_POOL_FIXED_DEFINE(hci_cmd_pool, CONFIG_BT_BUF_CMD_TX_COUNT,
+NET_BUF_POOL_FIXED_DEFINE(hci_cmd_pool, BT_BUF_CMD_TX_COUNT,
 			  BT_BUF_CMD_SIZE(CONFIG_BT_BUF_CMD_TX_SIZE),
 			  sizeof(struct bt_buf_data), NULL);
 NET_BUF_POOL_FIXED_DEFINE(hci_acl_pool, CONFIG_BT_BUF_ACL_TX_COUNT,
diff --git a/subsys/bluetooth/host/id.c b/subsys/bluetooth/host/id.c
index 67f691dfa79..926175f8b33 100644
--- a/subsys/bluetooth/host/id.c
+++ b/subsys/bluetooth/host/id.c
@@ -1,40 +1,47 @@
 /*
- * Copyright (c) 2017-2024 Nordic Semiconductor ASA
+ * Copyright (c) 2017-2025 Nordic Semiconductor ASA
  * Copyright (c) 2015-2016 Intel Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <errno.h>
 #include <stdbool.h>
+#include <stddef.h>
 #include <stdint.h>
+#include <string.h>
 
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/buf.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/crypto.h>
+#include <zephyr/bluetooth/hci.h>
 #include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/bluetooth/hci_vs.h>
+#include <zephyr/kernel.h>
+#include <zephyr/net_buf.h>
 #include <zephyr/settings/settings.h>
+#include <zephyr/sys/atomic.h>
 #include <zephyr/sys/byteorder.h>
 #include <zephyr/sys/check.h>
-
-#include <zephyr/bluetooth/addr.h>
-#include <zephyr/bluetooth/bluetooth.h>
-#include <zephyr/bluetooth/hci_vs.h>
-#include <zephyr/bluetooth/buf.h>
+#include <zephyr/sys/time_units.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
 #include <zephyr/sys/__assert.h>
+#include <zephyr/toolchain.h>
 
-#include "hci_core.h"
-#include "id.h"
-#include "scan.h"
 #include "adv.h"
-#include "smp.h"
+#include "common/bt_str.h"
+#include "common/rpa.h"
 #include "conn_internal.h"
+#include "hci_core.h"
+#include "id.h"
 #include "keys.h"
-#include "common/rpa.h"
-
+#include "scan.h"
 #include "settings.h"
-
-#include <zephyr/bluetooth/hci.h>
-#include <zephyr/sys/util_macro.h>
-#include <zephyr/toolchain.h>
-
-#include "common/bt_str.h"
+#include "smp.h"
 
 #define LOG_LEVEL CONFIG_BT_HCI_CORE_LOG_LEVEL
 #include <zephyr/logging/log.h>
@@ -265,7 +272,7 @@ static void adv_rpa_clear_data(struct bt_le_ext_adv *adv, void *data)
 		atomic_clear_bit(adv->flags, BT_ADV_RPA_VALID);
 		bt_addr_copy(&bt_dev.rpa[adv->id], BT_ADDR_NONE);
 	} else {
-		LOG_WRN("Adv sets rpa expired cb with id %d returns false\n", adv->id);
+		LOG_WRN("Adv sets rpa expired cb with id %d returns false", adv->id);
 	}
 }
 #endif
@@ -284,6 +291,9 @@ static void le_rpa_invalidate(void)
 			return;
 		}
 		bool rpa_expired_data[bt_dev.id_count];
+		for (uint8_t i = 0; i < bt_dev.id_count; i++) {
+			rpa_expired_data[i] = true;
+		}
 
 		bt_le_ext_adv_foreach(adv_rpa_invalidate, &rpa_expired_data);
 #if defined(CONFIG_BT_RPA_SHARING)
@@ -916,7 +926,7 @@ static void pending_id_update(struct bt_keys *keys, void *data)
 	}
 }
 
-static void bt_id_pending_keys_update_set(struct bt_keys *keys, uint8_t flag)
+void bt_id_pending_keys_update_set(struct bt_keys *keys, uint8_t flag)
 {
 	atomic_set_bit(bt_dev.flags, BT_DEV_ID_PENDING);
 	keys->state |= flag;
@@ -2133,7 +2143,12 @@ int bt_le_ext_adv_oob_get_local(struct bt_le_ext_adv *adv,
 #if !defined(CONFIG_BT_SMP_SC_PAIR_ONLY)
 int bt_le_oob_set_legacy_tk(struct bt_conn *conn, const uint8_t *tk)
 {
-	CHECKIF(conn == NULL || tk == NULL) {
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
+	CHECKIF(tk == NULL) {
 		return -EINVAL;
 	}
 
@@ -2146,7 +2161,8 @@ int bt_le_oob_set_sc_data(struct bt_conn *conn,
 			  const struct bt_le_oob_sc_data *oobd_local,
 			  const struct bt_le_oob_sc_data *oobd_remote)
 {
-	CHECKIF(conn == NULL) {
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
 		return -EINVAL;
 	}
 
@@ -2161,7 +2177,9 @@ int bt_le_oob_get_sc_data(struct bt_conn *conn,
 			  const struct bt_le_oob_sc_data **oobd_local,
 			  const struct bt_le_oob_sc_data **oobd_remote)
 {
-	CHECKIF(conn == NULL) {
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		LOG_ERR("Invalid connection: %p", conn);
+		LOG_ERR("Invalid connection type: %u for %p", conn->handle, conn);
 		return -EINVAL;
 	}
 
diff --git a/subsys/bluetooth/host/id.h b/subsys/bluetooth/host/id.h
index 55a25d93400..8824d3bb496 100644
--- a/subsys/bluetooth/host/id.h
+++ b/subsys/bluetooth/host/id.h
@@ -4,12 +4,25 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/time_units.h>
+#include <zephyr/sys_clock.h>
+
+#include "keys.h"
 
 #define RPA_TIMEOUT_MS(_rpa_timeout) (_rpa_timeout * MSEC_PER_SEC)
 
 static inline bool bt_id_rpa_is_new(void)
 {
 #if defined(CONFIG_BT_PRIVACY)
+	/* TODO: To get bt_dev we should include "hci_core.h" but that gives redefinitions
+	 * Should we have an API to get the rpa_update value?
+	 */
 	uint32_t remaining_ms = k_ticks_to_ms_floor32(
 		k_work_delayable_remaining_get(&bt_dev.rpa_update));
 	/* RPA is considered new if there is less than half a second since the
@@ -44,4 +57,6 @@ int bt_id_set_private_addr(uint8_t id);
 
 void bt_id_pending_keys_update(void);
 
+void bt_id_pending_keys_update_set(struct bt_keys *keys, uint8_t flag);
+
 void bt_id_adv_limited_stopped(struct bt_le_ext_adv *adv);
diff --git a/subsys/bluetooth/host/iso.c b/subsys/bluetooth/host/iso.c
index 4b05178d906..0500eb5cc72 100644
--- a/subsys/bluetooth/host/iso.c
+++ b/subsys/bluetooth/host/iso.c
@@ -2,7 +2,7 @@
 
 /*
  * Copyright (c) 2020 Intel Corporation
- * Copyright (c) 2021-2024 Nordic Semiconductor ASA
+ * Copyright (c) 2021-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -77,7 +77,6 @@ struct bt_conn iso_conns[CONFIG_BT_ISO_MAX_CHAN];
 struct bt_iso_cig cigs[CONFIG_BT_ISO_MAX_CIG];
 
 static struct bt_iso_cig *get_cig(const struct bt_iso_chan *iso_chan);
-static void bt_iso_remove_data_path(struct bt_conn *iso);
 static int hci_le_create_cis(const struct bt_iso_connect_param *param, size_t count);
 
 #endif /* CONFIG_BT_ISO_CENTRAL */
@@ -197,15 +196,6 @@ static int hci_le_setup_iso_data_path(const struct bt_conn *iso, uint8_t dir,
 	uint8_t *cc;
 	int err;
 
-	__ASSERT(dir == BT_HCI_DATAPATH_DIR_HOST_TO_CTLR || dir == BT_HCI_DATAPATH_DIR_CTLR_TO_HOST,
-		 "invalid ISO data path dir: %u", dir);
-
-	if ((path->cc == NULL && path->cc_len != 0)) {
-		LOG_DBG("Invalid ISO data path CC: %p %u", path->cc, path->cc_len);
-
-		return -EINVAL;
-	}
-
 	buf = bt_hci_cmd_create(BT_HCI_OP_LE_SETUP_ISO_PATH, sizeof(*cp) + path->cc_len);
 	if (!buf) {
 		return -ENOBUFS;
@@ -249,103 +239,197 @@ static void bt_iso_chan_add(struct bt_conn *iso, struct bt_iso_chan *chan)
 	LOG_DBG("iso %p chan %p", iso, chan);
 }
 
-static int bt_iso_setup_data_path(struct bt_iso_chan *chan)
+static int validate_iso_setup_data_path_parms(const struct bt_iso_chan *chan, uint8_t dir,
+					      const struct bt_iso_chan_path *path)
 {
-	int err;
-	struct bt_iso_chan_path default_hci_path = {.pid = BT_ISO_DATA_PATH_HCI,
-						    .format = BT_HCI_CODING_FORMAT_TRANSPARENT,
-						    .cc_len = 0x00};
-	struct bt_iso_chan_path *out_path = NULL;
-	struct bt_iso_chan_path *in_path = NULL;
-	struct bt_iso_chan_io_qos *tx_qos;
-	struct bt_iso_chan_io_qos *rx_qos;
 	struct bt_conn *iso;
-	uint8_t dir;
+
+	CHECKIF(chan == NULL) {
+		LOG_DBG("chan is NULL");
+
+		return -EINVAL;
+	}
+
+	CHECKIF(path == NULL) {
+		LOG_DBG("path is NULL");
+
+		return -EINVAL;
+	}
+
+	CHECKIF(dir != BT_HCI_DATAPATH_DIR_HOST_TO_CTLR &&
+		dir != BT_HCI_DATAPATH_DIR_CTLR_TO_HOST) {
+		LOG_DBG("Invalid dir: %u", dir);
+
+		return -EINVAL;
+	}
 
 	iso = chan->iso;
+	if (iso == NULL) {
+		LOG_DBG("chan %p not associated with a CIS/BIS handle", chan);
 
-	tx_qos = chan->qos->tx;
-	rx_qos = chan->qos->rx;
+		return -ENODEV;
+	}
 
-	/* The following code sets the in and out paths for ISO data.
-	 * If the application provides a path for a direction (tx/rx) we use
-	 * that, otherwise we simply fall back to HCI.
-	 *
-	 * If the direction is not set (by whether tx_qos or rx_qos is NULL),
-	 * then we fallback to the HCI path object, but we disable the direction
-	 * in the controller.
-	 */
+	if (!iso->iso.info.can_recv && dir == BT_HCI_DATAPATH_DIR_CTLR_TO_HOST) {
+		LOG_DBG("Invalid dir %u for chan %p that cannot receive data", dir, chan);
 
-	if (tx_qos != NULL && iso->iso.info.can_send) {
-		if (tx_qos->path != NULL) { /* Use application path */
-			in_path = tx_qos->path;
-		} else { /* else fallback to HCI path */
-			in_path = &default_hci_path;
-		}
+		return -EINVAL;
 	}
 
-	if (rx_qos != NULL && iso->iso.info.can_recv) {
-		if (rx_qos->path != NULL) { /* Use application path */
-			out_path = rx_qos->path;
-		} else { /* else fallback to HCI path */
-			out_path = &default_hci_path;
-		}
+	if (!iso->iso.info.can_send && dir == BT_HCI_DATAPATH_DIR_HOST_TO_CTLR) {
+		LOG_DBG("Invalid dir %u for chan %p that cannot send data", dir, chan);
+
+		return -EINVAL;
 	}
 
-	__ASSERT(in_path || out_path, "At least one path shall be shell: in %p out %p", in_path,
-		 out_path);
+	CHECKIF(path->pid != BT_ISO_DATA_PATH_HCI &&
+		!IN_RANGE(path->pid, BT_ISO_DATA_PATH_VS_ID_MIN, BT_ISO_DATA_PATH_VS_ID_MAX)) {
+		LOG_DBG("Invalid pid %u", path->pid);
 
-	if (IS_ENABLED(CONFIG_BT_ISO_BROADCASTER) &&
-	    iso->iso.info.type == BT_ISO_CHAN_TYPE_BROADCASTER && in_path) {
-		dir = BT_HCI_DATAPATH_DIR_HOST_TO_CTLR;
-		err = hci_le_setup_iso_data_path(iso, dir, in_path);
-		if (err != 0) {
-			LOG_DBG("Failed to set broadcaster data path: %d", err);
-		}
+		return -EINVAL;
+	}
+
+	CHECKIF(path->format > BT_HCI_CODING_FORMAT_G729A &&
+		path->format != BT_HCI_CODING_FORMAT_VS) {
+		LOG_DBG("Invalid format %u", path->format);
+
+		return -EINVAL;
+	}
+
+	CHECKIF(path->delay > BT_ISO_CONTROLLER_DELAY_MAX) {
+		LOG_DBG("Invalid delay: %u", path->delay);
+
+		return -EINVAL;
+	}
+
+	CHECKIF(path->cc_len > 0U && path->cc == NULL) {
+		LOG_DBG("No CC provided for CC length %u", path->cc_len);
 
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int bt_iso_setup_data_path(const struct bt_iso_chan *chan, uint8_t dir,
+			   const struct bt_iso_chan_path *path)
+{
+	int err;
+
+	err = validate_iso_setup_data_path_parms(chan, dir, path);
+	if (err != 0) {
 		return err;
-	} else if (IS_ENABLED(CONFIG_BT_ISO_SYNC_RECEIVER) &&
-		   iso->iso.info.type == BT_ISO_CHAN_TYPE_SYNC_RECEIVER && out_path) {
-		dir = BT_HCI_DATAPATH_DIR_CTLR_TO_HOST;
-		err = hci_le_setup_iso_data_path(iso, dir, out_path);
-		if (err != 0) {
-			LOG_DBG("Failed to set sync receiver data path: %d", err);
+	}
+
+	err = hci_le_setup_iso_data_path(chan->iso, dir, path);
+	if (err != 0) {
+		LOG_DBG("Failed to set data path: %d", err);
+
+		/* Return known possible errors */
+		if (err == -ENOBUFS || err == -EIO || err == -EACCES) {
+			return err;
 		}
 
+		LOG_DBG("Unknown error from hci_le_setup_iso_data_path: %d", err);
+
+		return -ENOEXEC;
+	}
+
+	return 0;
+}
+
+static int hci_le_remove_iso_data_path(struct bt_conn *iso, uint8_t dir)
+{
+	struct bt_hci_cp_le_remove_iso_path *cp;
+	struct bt_hci_rp_le_remove_iso_path *rp;
+	struct net_buf *buf, *rsp;
+	int err;
+
+	buf = bt_hci_cmd_create(BT_HCI_OP_LE_REMOVE_ISO_PATH, sizeof(*cp));
+	if (!buf) {
+		return -ENOBUFS;
+	}
+
+	cp = net_buf_add(buf, sizeof(*cp));
+	cp->handle = sys_cpu_to_le16(iso->handle);
+	/* The path_dir is a bitfield and it's technically possible to do BIT(0) | BIT(1) but for
+	 * simplicity our API only supports removing a single ISO data path at a time.
+	 * We can convert from BT_HCI_DATAPATH_DIR_HOST_TO_CTLR and BT_HCI_DATAPATH_DIR_CTLR_TO_HOST
+	 * to the proper values just by using `BIT`
+	 */
+	cp->path_dir = BIT(dir);
+
+	err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_REMOVE_ISO_PATH, buf, &rsp);
+	if (err) {
 		return err;
-	} else if (IS_ENABLED(CONFIG_BT_ISO_UNICAST) &&
-		   iso->iso.info.type == BT_ISO_CHAN_TYPE_CONNECTED) {
-		if (in_path != NULL) {
-			/* Enable TX */
-			dir = BT_HCI_DATAPATH_DIR_HOST_TO_CTLR;
-			err = hci_le_setup_iso_data_path(iso, dir, in_path);
-			if (err) {
-				LOG_DBG("Failed to setup host-to-ctrl path: %d", err);
-				return err;
-			}
-		}
+	}
 
-		if (out_path != NULL) {
-			/* Enable RX */
-			dir = BT_HCI_DATAPATH_DIR_CTLR_TO_HOST;
-			err = hci_le_setup_iso_data_path(iso, dir, out_path);
-			if (err) {
-				LOG_DBG("Failed to setup ctlr-to-host path: %d", err);
-				return err;
-			}
-		}
+	rp = (void *)rsp->data;
+	if (rp->status || (sys_le16_to_cpu(rp->handle) != iso->handle)) {
+		err = -EIO;
+	}
+
+	net_buf_unref(rsp);
+
+	return err;
+}
+
+static int validate_iso_remove_data_path(const struct bt_iso_chan *chan, uint8_t dir)
+{
+	struct bt_conn *iso;
+
+	CHECKIF(chan == NULL) {
+		LOG_DBG("chan is NULL");
 
-		return 0;
-	} else {
-		__ASSERT(false, "Invalid iso.info.type: %u", iso->iso.info.type);
 		return -EINVAL;
 	}
+
+	CHECKIF(dir != BT_HCI_DATAPATH_DIR_HOST_TO_CTLR &&
+		dir != BT_HCI_DATAPATH_DIR_CTLR_TO_HOST) {
+		LOG_DBG("Invalid dir: %u", dir);
+
+		return -EINVAL;
+	}
+
+	iso = chan->iso;
+	if (iso == NULL) {
+		LOG_DBG("chan %p not associated with a CIS/BIS handle", chan);
+
+		return -ENODEV;
+	}
+
+	return 0;
+}
+
+int bt_iso_remove_data_path(const struct bt_iso_chan *chan, uint8_t dir)
+{
+	int err;
+
+	err = validate_iso_remove_data_path(chan, dir);
+	if (err != 0) {
+		return err;
+	}
+
+	err = hci_le_remove_iso_data_path(chan->iso, dir);
+	if (err != 0) {
+		LOG_DBG("Failed to remove data path: %d", err);
+
+		/* Return known possible errors */
+		if (err == -ENOBUFS || err == -EIO || err == -EACCES) {
+			return err;
+		}
+
+		LOG_DBG("Unknown error from hci_le_remove_iso_data_path: %d", err);
+
+		return -ENOEXEC;
+	}
+
+	return 0;
 }
 
 void bt_iso_connected(struct bt_conn *iso)
 {
 	struct bt_iso_chan *chan;
-	int err;
 
 	if (iso == NULL || iso->type != BT_CONN_TYPE_ISO) {
 		LOG_DBG("Invalid parameters: iso %p iso->type %u", iso, iso ? iso->type : 0);
@@ -360,32 +444,6 @@ void bt_iso_connected(struct bt_conn *iso)
 		return;
 	}
 
-	err = bt_iso_setup_data_path(chan);
-	if (err != 0) {
-		if (false) {
-
-#if defined(CONFIG_BT_ISO_BROADCAST)
-		} else if (iso->iso.info.type == BT_ISO_CHAN_TYPE_BROADCASTER ||
-			   iso->iso.info.type == BT_ISO_CHAN_TYPE_SYNC_RECEIVER) {
-			struct bt_iso_big *big;
-
-			big = lookup_big_by_handle(iso->iso.big_handle);
-
-			err = bt_iso_big_terminate(big);
-			if (err != 0) {
-				LOG_ERR("Could not terminate BIG: %d", err);
-			}
-#endif /* CONFIG_BT_ISO_BROADCAST */
-
-		} else if (IS_ENABLED(CONFIG_BT_ISO_UNICAST) &&
-			   iso->iso.info.type == BT_ISO_CHAN_TYPE_CONNECTED) {
-			bt_conn_disconnect(iso, BT_HCI_ERR_REMOTE_USER_TERM_CONN);
-		} else {
-			__ASSERT(false, "Invalid iso.info.type: %u", iso->iso.info.type);
-		}
-		return;
-	}
-
 	bt_iso_chan_set_state(chan, BT_ISO_STATE_CONNECTED);
 
 	if (chan->ops->connected) {
@@ -395,6 +453,7 @@ void bt_iso_connected(struct bt_conn *iso)
 
 static void bt_iso_chan_disconnected(struct bt_iso_chan *chan, uint8_t reason)
 {
+	const uint8_t conn_type = chan->iso->iso.info.type;
 	LOG_DBG("%p, reason 0x%02x", chan, reason);
 
 	__ASSERT(chan->iso != NULL, "NULL conn for iso chan %p", chan);
@@ -402,23 +461,26 @@ static void bt_iso_chan_disconnected(struct bt_iso_chan *chan, uint8_t reason)
 	bt_iso_chan_set_state(chan, BT_ISO_STATE_DISCONNECTED);
 	bt_conn_set_state(chan->iso, BT_CONN_DISCONNECT_COMPLETE);
 
+	/* Calling disconnected before final cleanup allows users to use bt_iso_chan_get_info in
+	 * the callback and to be more similar to the ACL disconnected callback. This also means
+	 * that the channel cannot be reused or memset in the callback
+	 */
+	if (chan->ops->disconnected) {
+		chan->ops->disconnected(chan, reason);
+	}
+
 	/* The peripheral does not have the concept of a CIG, so once a CIS
 	 * disconnects it is completely freed by unref'ing it
 	 */
 	if (IS_ENABLED(CONFIG_BT_ISO_UNICAST) &&
-	    chan->iso->iso.info.type == BT_ISO_CHAN_TYPE_CONNECTED) {
+	    (conn_type == BT_ISO_CHAN_TYPE_CENTRAL || conn_type == BT_ISO_CHAN_TYPE_PERIPHERAL)) {
 		bt_iso_cleanup_acl(chan->iso);
 
-		if (chan->iso->role == BT_HCI_ROLE_PERIPHERAL) {
+		if (conn_type == BT_ISO_CHAN_TYPE_PERIPHERAL) {
 			bt_conn_unref(chan->iso);
 			chan->iso = NULL;
 #if defined(CONFIG_BT_ISO_CENTRAL)
 		} else {
-			/* ISO data paths are automatically removed when the
-			 * peripheral disconnects, so we only need to
-			 * move it for the central
-			 */
-			bt_iso_remove_data_path(chan->iso);
 			bool is_chan_connected;
 			struct bt_iso_cig *cig;
 			struct bt_iso_chan *cis_chan;
@@ -442,10 +504,6 @@ static void bt_iso_chan_disconnected(struct bt_iso_chan *chan, uint8_t reason)
 #endif /* CONFIG_BT_ISO_CENTRAL */
 		}
 	}
-
-	if (chan->ops->disconnected) {
-		chan->ops->disconnected(chan, reason);
-	}
 }
 
 void bt_iso_disconnected(struct bt_conn *iso)
@@ -910,7 +968,7 @@ int bt_iso_chan_send_ts(struct bt_iso_chan *chan, struct net_buf *buf, uint16_t
 	BT_ISO_DATA_DBG("chan %p len %zu", chan, net_buf_frags_len(buf));
 
 	hdr = net_buf_push(buf, sizeof(*hdr));
-	hdr->ts = ts;
+	hdr->ts = sys_cpu_to_le32(ts);
 	hdr->sdu.sn = sys_cpu_to_le16(seq_num);
 	hdr->sdu.slen = sys_cpu_to_le16(
 		bt_iso_pkt_len_pack(net_buf_frags_len(buf) - sizeof(*hdr), BT_ISO_DATA_VALID));
@@ -1131,7 +1189,7 @@ static void store_cis_info(const struct bt_hci_evt_le_cis_established *evt, stru
 			tx->sdu = sys_le16_to_cpu(evt->p_max_pdu);
 		}
 
-		iso_conn->info.type = BT_ISO_CHAN_TYPE_CONNECTED;
+		iso_conn->info.type = BT_ISO_CHAN_TYPE_PERIPHERAL;
 	} else {
 		/* values are already set for central - Verify */
 		if (tx != NULL && tx->phy != c_phy) {
@@ -1548,7 +1606,7 @@ void hci_le_cis_req(struct net_buf *buf)
 		return;
 	}
 
-	iso->iso.info.type = BT_ISO_CHAN_TYPE_CONNECTED;
+	iso->iso.info.type = BT_ISO_CHAN_TYPE_PERIPHERAL;
 	iso->iso.cig_id = evt->cig_id;
 	iso->iso.cis_id = evt->cis_id;
 
@@ -1591,80 +1649,6 @@ static struct bt_conn *bt_conn_add_iso(struct bt_conn *acl)
 #endif /* CONFIG_BT_ISO_PERIPHERAL */
 
 #if defined(CONFIG_BT_ISO_CENTRAL)
-static int hci_le_remove_iso_data_path(struct bt_conn *iso, uint8_t dir)
-{
-	struct bt_hci_cp_le_remove_iso_path *cp;
-	struct bt_hci_rp_le_remove_iso_path *rp;
-	struct net_buf *buf, *rsp;
-	int err;
-
-	buf = bt_hci_cmd_create(BT_HCI_OP_LE_REMOVE_ISO_PATH, sizeof(*cp));
-	if (!buf) {
-		return -ENOBUFS;
-	}
-
-	cp = net_buf_add(buf, sizeof(*cp));
-	cp->handle = sys_cpu_to_le16(iso->handle);
-	cp->path_dir = dir;
-
-	err = bt_hci_cmd_send_sync(BT_HCI_OP_LE_REMOVE_ISO_PATH, buf, &rsp);
-	if (err) {
-		return err;
-	}
-
-	rp = (void *)rsp->data;
-	if (rp->status || (sys_le16_to_cpu(rp->handle) != iso->handle)) {
-		err = -EIO;
-	}
-
-	net_buf_unref(rsp);
-
-	return err;
-}
-
-static void bt_iso_remove_data_path(struct bt_conn *iso)
-{
-	enum bt_iso_chan_type type = iso->iso.info.type;
-
-	LOG_DBG("%p", iso);
-
-	/* TODO: Removing the ISO data path is never used for broadcast:
-	 * Remove the following broadcast implementation?
-	 */
-	if ((IS_ENABLED(CONFIG_BT_ISO_BROADCASTER) && type == BT_ISO_CHAN_TYPE_BROADCASTER) ||
-	    (IS_ENABLED(CONFIG_BT_ISO_SYNC_RECEIVER) && type == BT_ISO_CHAN_TYPE_SYNC_RECEIVER)) {
-		struct bt_iso_chan *chan;
-		struct bt_iso_chan_io_qos *tx_qos;
-		uint8_t dir;
-
-		chan = iso_chan(iso);
-		if (chan == NULL) {
-			return;
-		}
-
-		tx_qos = chan->qos->tx;
-
-		/* Only remove one data path for BIS as per the spec */
-		if (tx_qos) {
-			dir = BIT(BT_HCI_DATAPATH_DIR_HOST_TO_CTLR);
-		} else {
-			dir = BIT(BT_HCI_DATAPATH_DIR_CTLR_TO_HOST);
-		}
-
-		(void)hci_le_remove_iso_data_path(iso, dir);
-	} else if (IS_ENABLED(CONFIG_BT_ISO_UNICAST) && type == BT_ISO_CHAN_TYPE_CONNECTED) {
-		/* Remove both directions for CIS*/
-
-		/* TODO: Check which has been setup first to avoid removing
-		 * data paths that are not setup
-		 */
-		(void)hci_le_remove_iso_data_path(iso, BIT(BT_HCI_DATAPATH_DIR_HOST_TO_CTLR));
-		(void)hci_le_remove_iso_data_path(iso, BIT(BT_HCI_DATAPATH_DIR_CTLR_TO_HOST));
-	} else {
-		__ASSERT(false, "Invalid iso.type: %u", type);
-	}
-}
-
 static bool valid_chan_qos(const struct bt_iso_chan_qos *qos, bool advanced)
 {
 #if defined(CONFIG_BT_ISO_TEST_PARAMS)
@@ -1984,7 +1968,7 @@ static int cig_init_cis(struct bt_iso_cig *cig, const struct bt_iso_cig_param *p
 			iso_conn = &cis->iso->iso;
 
 			iso_conn->cig_id = cig->id;
-			iso_conn->info.type = BT_ISO_CHAN_TYPE_CONNECTED;
+			iso_conn->info.type = BT_ISO_CHAN_TYPE_CENTRAL;
 			iso_conn->cis_id = cig->num_cis++;
 
 			bt_iso_chan_add(cis->iso, cis);
@@ -2134,7 +2118,7 @@ static bool valid_cig_param(const struct bt_iso_cig_param *param, bool advanced,
 int bt_iso_cig_create(const struct bt_iso_cig_param *param, struct bt_iso_cig **out_cig)
 {
 	int err;
-	struct net_buf *rsp;
+	struct net_buf *rsp = NULL;
 	struct bt_iso_cig *cig;
 	struct bt_hci_rp_le_set_cig_params *cig_rsp;
 	struct bt_iso_chan *cis;
@@ -2255,7 +2239,7 @@ int bt_iso_cig_reconfigure(struct bt_iso_cig *cig, const struct bt_iso_cig_param
 	struct bt_hci_rp_le_set_cig_params *cig_rsp;
 	uint8_t existing_num_cis;
 	bool advanced = false;
-	struct net_buf *rsp;
+	struct net_buf *rsp = NULL;
 	int err;
 
 	CHECKIF(cig == NULL) {
@@ -2553,7 +2537,8 @@ static bool iso_chans_connecting(void)
 		const struct bt_conn *iso = &iso_conns[i];
 		const struct bt_iso_chan *iso_chan;
 
-		if (iso == NULL || iso->iso.info.type != BT_ISO_CHAN_TYPE_CONNECTED) {
+		if (iso == NULL || !(iso->iso.info.type == BT_ISO_CHAN_TYPE_CENTRAL ||
+				     iso->iso.info.type == BT_ISO_CHAN_TYPE_PERIPHERAL)) {
 			continue;
 		}
 
diff --git a/subsys/bluetooth/host/keys.c b/subsys/bluetooth/host/keys.c
index 6740d43b1cd..6341fc1e58e 100644
--- a/subsys/bluetooth/host/keys.c
+++ b/subsys/bluetooth/host/keys.c
@@ -5,33 +5,38 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-
-#include <zephyr/kernel.h>
-#include <string.h>
+#include <errno.h>
+#include <stdbool.h>
 #include <stdlib.h>
-#include <zephyr/sys/atomic.h>
-#include <zephyr/sys/util.h>
-#include <zephyr/sys/byteorder.h>
-
-#include <zephyr/settings/settings.h>
+#include <stdint.h>
+#include <string.h>
 
+#include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/buf.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/hci.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/settings/settings.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util_macro.h>
 
 #include "common/bt_str.h"
-
 #include "common/rpa.h"
 #include "conn_internal.h"
 #include "gatt_internal.h"
 #include "hci_core.h"
-#include "smp.h"
-#include "settings.h"
+#include "id.h"
 #include "keys.h"
+#include "settings.h"
+#include "smp.h"
+#include "sys/types.h"
 
 #define LOG_LEVEL CONFIG_BT_KEYS_LOG_LEVEL
-#include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(bt_keys);
 
 static struct bt_keys key_pool[CONFIG_BT_MAX_PAIRED];
@@ -174,10 +179,6 @@ void bt_foreach_bond(uint8_t id, void (*func)(const struct bt_bond_info *info,
 			func(&info, user_data);
 		}
 	}
-
-	if (IS_ENABLED(CONFIG_BT_CLASSIC)) {
-		bt_foreach_bond_br(func, user_data);
-	}
 }
 
 void bt_keys_foreach_type(enum bt_keys_type type, void (*func)(struct bt_keys *keys, void *data),
@@ -435,11 +436,19 @@ static int keys_set(const char *name, size_t len_rd, settings_read_cb read_cb,
 	return 0;
 }
 
+static void add_id_cb(struct k_work *work)
+{
+	bt_id_pending_keys_update();
+}
+
+static K_WORK_DEFINE(add_id_work, add_id_cb);
+
 static void id_add(struct bt_keys *keys, void *user_data)
 {
 	__ASSERT_NO_MSG(keys != NULL);
 
-	bt_id_add(keys);
+	bt_id_pending_keys_update_set(keys, BT_KEYS_ID_PENDING_ADD);
+	k_work_submit(&add_id_work);
 }
 
 static int keys_commit(void)
diff --git a/subsys/bluetooth/host/keys.h b/subsys/bluetooth/host/keys.h
index c1da17fb488..b53635ce2c5 100644
--- a/subsys/bluetooth/host/keys.h
+++ b/subsys/bluetooth/host/keys.h
@@ -9,83 +9,89 @@
 #ifndef ZEPHYR_SUBSYS_BLUETOOTH_HOST_KEYS_H_
 #define ZEPHYR_SUBSYS_BLUETOOTH_HOST_KEYS_H_
 
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/toolchain.h>
 
 /** @cond INTERNAL_HIDDEN */
 
 enum bt_keys_type {
-	BT_KEYS_PERIPH_LTK     = BIT(0),
-	BT_KEYS_IRK            = BIT(1),
-	BT_KEYS_LTK            = BIT(2),
-	BT_KEYS_LOCAL_CSRK     = BIT(3),
-	BT_KEYS_REMOTE_CSRK    = BIT(4),
-	BT_KEYS_LTK_P256       = BIT(5),
-
-	BT_KEYS_ALL            = (BT_KEYS_PERIPH_LTK | BT_KEYS_IRK |
-				  BT_KEYS_LTK | BT_KEYS_LOCAL_CSRK |
-				  BT_KEYS_REMOTE_CSRK | BT_KEYS_LTK_P256),
+	BT_KEYS_PERIPH_LTK = BIT(0),
+	BT_KEYS_IRK = BIT(1),
+	BT_KEYS_LTK = BIT(2),
+	BT_KEYS_LOCAL_CSRK = BIT(3),
+	BT_KEYS_REMOTE_CSRK = BIT(4),
+	BT_KEYS_LTK_P256 = BIT(5),
+
+	BT_KEYS_ALL = (BT_KEYS_PERIPH_LTK | BT_KEYS_IRK | BT_KEYS_LTK | BT_KEYS_LOCAL_CSRK |
+		       BT_KEYS_REMOTE_CSRK | BT_KEYS_LTK_P256),
 };
 
 enum {
-	BT_KEYS_ID_PENDING_ADD  = BIT(0),
-	BT_KEYS_ID_PENDING_DEL  = BIT(1),
-	BT_KEYS_ID_ADDED        = BIT(2),
+	BT_KEYS_ID_PENDING_ADD = BIT(0),
+	BT_KEYS_ID_PENDING_DEL = BIT(1),
+	BT_KEYS_ID_ADDED = BIT(2),
 };
 
 enum {
-	BT_KEYS_AUTHENTICATED   = BIT(0),
-	BT_KEYS_DEBUG           = BIT(1),
+	BT_KEYS_AUTHENTICATED = BIT(0),
+	BT_KEYS_DEBUG = BIT(1),
 	/* Bit 2 and 3 might accidentally exist in old stored keys */
-	BT_KEYS_SC              = BIT(4),
-	BT_KEYS_OOB             = BIT(5),
+	BT_KEYS_SC = BIT(4),
+	BT_KEYS_OOB = BIT(5),
 };
 
 struct bt_ltk {
-	uint8_t                    rand[8];
-	uint8_t                    ediv[2];
-	uint8_t                    val[16];
+	uint8_t rand[8];
+	uint8_t ediv[2];
+	uint8_t val[16];
 };
 
 struct bt_irk {
-	uint8_t                    val[16];
+	uint8_t val[16];
 	/* Cache for `bt_keys_find_irk`. Not reliable as "current RPA"! */
-	bt_addr_t               rpa;
+	bt_addr_t rpa;
 };
 
 static inline bool bt_irk_eq(struct bt_irk const *a, struct bt_irk const *b)
 {
-	return (memcmp(a->val, b->val, sizeof(a->val)) == 0);
+	return util_memeq(a->val, b->val, sizeof(a->val));
 }
 
 struct bt_csrk {
-	uint8_t                    val[16];
-	uint32_t                   cnt;
+	uint8_t val[16];
+	uint32_t cnt;
 };
 
 struct bt_keys {
-	uint8_t                    id;
-	bt_addr_le_t            addr;
-	uint8_t                    state;
-	uint8_t                    storage_start[0] __aligned(sizeof(void *));
-	uint8_t                    enc_size;
-	uint8_t                    flags;
-	uint16_t                   keys;
-	struct bt_ltk           ltk;
-	struct bt_irk           irk;
+	uint8_t id;
+	bt_addr_le_t addr;
+	uint8_t state;
+	uint8_t storage_start[0] __aligned(sizeof(void *));
+	uint8_t enc_size;
+	uint8_t flags;
+	uint16_t keys;
+	struct bt_ltk ltk;
+	struct bt_irk irk;
 #if defined(CONFIG_BT_SIGNING)
-	struct bt_csrk          local_csrk;
-	struct bt_csrk          remote_csrk;
+	struct bt_csrk local_csrk;
+	struct bt_csrk remote_csrk;
 #endif /* BT_SIGNING */
 #if !defined(CONFIG_BT_SMP_SC_PAIR_ONLY)
-	struct bt_ltk           periph_ltk;
+	struct bt_ltk periph_ltk;
 #endif /* CONFIG_BT_SMP_SC_PAIR_ONLY */
 #if (defined(CONFIG_BT_KEYS_OVERWRITE_OLDEST))
-	uint32_t                   aging_counter;
+	uint32_t aging_counter;
 #endif /* CONFIG_BT_KEYS_OVERWRITE_OLDEST */
 };
 
-#define BT_KEYS_STORAGE_LEN     (sizeof(struct bt_keys) - \
-				 offsetof(struct bt_keys, storage_start))
+#define BT_KEYS_STORAGE_LEN (sizeof(struct bt_keys) - offsetof(struct bt_keys, storage_start))
 
 /** Clears all keys.
  *
@@ -204,30 +210,28 @@ static inline int bt_keys_store(struct bt_keys *keys)
 #endif
 
 enum {
-	BT_LINK_KEY_AUTHENTICATED  = BIT(0),
-	BT_LINK_KEY_DEBUG          = BIT(1),
-	BT_LINK_KEY_SC             = BIT(2),
+	BT_LINK_KEY_AUTHENTICATED = BIT(0),
+	BT_LINK_KEY_DEBUG = BIT(1),
+	BT_LINK_KEY_SC = BIT(2),
 };
 
 struct bt_keys_link_key {
-	bt_addr_t               addr;
-	uint8_t                 storage_start[0]  __aligned(sizeof(void *));
-	uint8_t                 flags;
-	uint8_t                 val[16];
+	bt_addr_t addr;
+	uint8_t storage_start[0] __aligned(sizeof(void *));
+	uint8_t flags;
+	uint8_t val[16];
 #if (defined(CONFIG_BT_KEYS_OVERWRITE_OLDEST))
-	uint32_t                aging_counter;
+	uint32_t aging_counter;
 #endif /* CONFIG_BT_KEYS_OVERWRITE_OLDEST */
 };
-#define BT_KEYS_LINK_KEY_STORAGE_LEN     (sizeof(struct bt_keys_link_key) - \
-	offsetof(struct bt_keys_link_key, storage_start))
+#define BT_KEYS_LINK_KEY_STORAGE_LEN                                                               \
+	(sizeof(struct bt_keys_link_key) - offsetof(struct bt_keys_link_key, storage_start))
 
 struct bt_keys_link_key *bt_keys_get_link_key(const bt_addr_t *addr);
 struct bt_keys_link_key *bt_keys_find_link_key(const bt_addr_t *addr);
 void bt_keys_link_key_clear(struct bt_keys_link_key *link_key);
 void bt_keys_link_key_clear_addr(const bt_addr_t *addr);
 void bt_keys_link_key_store(struct bt_keys_link_key *link_key);
-void bt_foreach_bond_br(void (*func)(const struct bt_bond_info *info, void *user_data),
-			void *user_data);
 
 /* This function is used to signal that the key has been used for paring */
 /* It updates the aging counter and saves it to flash if configuration option */
diff --git a/subsys/bluetooth/host/l2cap.c b/subsys/bluetooth/host/l2cap.c
index 9a6de949733..0f7017269ef 100644
--- a/subsys/bluetooth/host/l2cap.c
+++ b/subsys/bluetooth/host/l2cap.c
@@ -6,33 +6,39 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <errno.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
 
+#include <zephyr/bluetooth/buf.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/kernel.h>
-#include <string.h>
-#include <errno.h>
+
+#include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/l2cap.h>
+#include <zephyr/logging/log.h>
 #include <zephyr/sys/__assert.h>
 #include <zephyr/sys/atomic.h>
 #include <zephyr/sys/check.h>
 #include <zephyr/sys/iterable_sections.h>
 #include <zephyr/sys/byteorder.h>
 #include <zephyr/sys/math_extras.h>
+#include <zephyr/sys/slist.h>
 #include <zephyr/sys/util.h>
 #include <zephyr/net_buf.h>
-
-#include <zephyr/bluetooth/hci.h>
-#include <zephyr/bluetooth/bluetooth.h>
-#include <zephyr/bluetooth/conn.h>
-#include <zephyr/bluetooth/l2cap.h>
-
-#define LOG_DBG_ENABLED IS_ENABLED(CONFIG_BT_L2CAP_LOG_LEVEL_DBG)
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/toolchain.h>
 
 #include "buf_view.h"
 #include "hci_core.h"
 #include "conn_internal.h"
 #include "l2cap_internal.h"
-#include "keys.h"
 
-#include <zephyr/logging/log.h>
+#define LOG_DBG_ENABLED IS_ENABLED(CONFIG_BT_L2CAP_LOG_LEVEL_DBG)
 LOG_MODULE_REGISTER(bt_l2cap, CONFIG_BT_L2CAP_LOG_LEVEL);
 
 #define LE_CHAN_RTX(_w) CONTAINER_OF(k_work_delayable_from_work(_w), \
@@ -2421,6 +2427,10 @@ int bt_l2cap_chan_recv_complete(struct bt_l2cap_chan *chan, struct net_buf *buf)
 		return -ENOTCONN;
 	}
 
+	if (IS_ENABLED(CONFIG_BT_CLASSIC) && conn->type == BT_CONN_TYPE_BR) {
+		return bt_l2cap_br_chan_recv_complete(chan);
+	}
+
 	if (conn->type != BT_CONN_TYPE_LE) {
 		return -ENOTSUP;
 	}
@@ -2454,7 +2464,7 @@ static void l2cap_chan_le_recv_sdu(struct bt_l2cap_le_chan *chan,
 {
 	int err;
 
-	LOG_DBG("chan %p len %zu", chan, buf->len);
+	LOG_DBG("chan %p len %u", chan, buf->len);
 
 	__ASSERT_NO_MSG(bt_l2cap_chan_get_state(&chan->chan) == BT_L2CAP_CONNECTED);
 	__ASSERT_NO_MSG(atomic_get(&chan->rx.credits) == 0);
@@ -2496,7 +2506,7 @@ static void l2cap_chan_le_recv_seg(struct bt_l2cap_le_chan *chan,
 	/* Store received segments in user_data */
 	memcpy(net_buf_user_data(chan->_sdu), &seg, sizeof(seg));
 
-	LOG_DBG("chan %p seg %d len %zu", chan, seg, buf->len);
+	LOG_DBG("chan %p seg %d len %u", chan, seg, buf->len);
 
 	/* Append received segment to SDU */
 	len = net_buf_append_bytes(chan->_sdu, buf->len, buf->data, K_NO_WAIT,
@@ -3292,7 +3302,7 @@ int bt_l2cap_chan_send(struct bt_l2cap_chan *chan, struct net_buf *buf)
 		return -EINVAL;
 	}
 
-	LOG_DBG("chan %p buf %p len %zu", chan, buf, buf->len);
+	LOG_DBG("chan %p buf %p len %u", chan, buf, buf->len);
 
 	if (buf->ref != 1) {
 		LOG_WRN("Expecting 1 ref, got %d", buf->ref);
diff --git a/subsys/bluetooth/host/l2cap_internal.h b/subsys/bluetooth/host/l2cap_internal.h
index 60f614b7caa..07bd428334a 100644
--- a/subsys/bluetooth/host/l2cap_internal.h
+++ b/subsys/bluetooth/host/l2cap_internal.h
@@ -7,10 +7,19 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
 
+#include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/l2cap.h>
+#include <zephyr/kernel.h>
+#include <zephyr/net_buf.h>
 #include <zephyr/sys/iterable_sections.h>
+#include <zephyr/sys_clock.h>
+
 #include "host/classic/l2cap_br_interface.h"
+/* TODO: we should include conn_internal.h for bt_conn_tx_cb_t but that causes redefinitions */
 
 enum l2cap_conn_list_action {
 	BT_L2CAP_CHAN_LOOKUP,
diff --git a/subsys/bluetooth/host/long_wq.c b/subsys/bluetooth/host/long_wq.c
index b7b6e3dc03b..06f89ce71fc 100644
--- a/subsys/bluetooth/host/long_wq.c
+++ b/subsys/bluetooth/host/long_wq.c
@@ -5,8 +5,12 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+
+#include <zephyr/autoconf.h>
 #include <zephyr/kernel.h>
 #include <zephyr/init.h>
+#include <zephyr/kernel/thread_stack.h>
+#include <zephyr/sys_clock.h>
 
 K_THREAD_STACK_DEFINE(bt_lw_stack_area, CONFIG_BT_LONG_WQ_STACK_SIZE);
 static struct k_work_q bt_long_wq;
diff --git a/subsys/bluetooth/host/long_wq.h b/subsys/bluetooth/host/long_wq.h
index 714aa0af355..905048735bf 100644
--- a/subsys/bluetooth/host/long_wq.h
+++ b/subsys/bluetooth/host/long_wq.h
@@ -6,6 +6,9 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <zephyr/kernel.h>
+#include <zephyr/sys_clock.h>
+
 int bt_long_wq_schedule(struct k_work_delayable *dwork, k_timeout_t timeout);
 int bt_long_wq_reschedule(struct k_work_delayable *dwork, k_timeout_t timeout);
 int bt_long_wq_submit(struct k_work *dwork);
diff --git a/subsys/bluetooth/host/monitor.c b/subsys/bluetooth/host/monitor.c
index 10f18c3435d..77f116caab5 100644
--- a/subsys/bluetooth/host/monitor.c
+++ b/subsys/bluetooth/host/monitor.c
@@ -8,24 +8,32 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/types.h>
 #include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
 
-#include <zephyr/kernel.h>
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/buf.h>
 #include <zephyr/device.h>
-#include <zephyr/init.h>
 #include <zephyr/drivers/uart_pipe.h>
-#include <zephyr/sys/byteorder.h>
-#include <zephyr/sys/printk-hooks.h>
-#include <zephyr/sys/libc-hooks.h>
-#include <zephyr/drivers/uart.h>
-
+#include <zephyr/init.h>
+#include <zephyr/kernel.h>
 #include <zephyr/logging/log_backend.h>
+#include <zephyr/logging/log_core.h>
+#include <zephyr/logging/log_msg.h>
 #include <zephyr/logging/log_output.h>
 #include <zephyr/logging/log_ctrl.h>
 #include <zephyr/logging/log.h>
-
-#include <zephyr/bluetooth/buf.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/atomic_types.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/printk-hooks.h>
+#include <zephyr/sys/libc-hooks.h>
+#include <zephyr/drivers/uart.h>
+#include <zephyr/sys/time_units.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
 
 #include "monitor.h"
 
diff --git a/subsys/bluetooth/host/monitor.h b/subsys/bluetooth/host/monitor.h
index e5a6422bfd8..873f51348aa 100644
--- a/subsys/bluetooth/host/monitor.h
+++ b/subsys/bluetooth/host/monitor.h
@@ -7,8 +7,10 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stdint.h>
 
-#if defined(CONFIG_BT_MONITOR)
+#include <zephyr/bluetooth/buf.h>
+#include <zephyr/net_buf.h>
 
 #define BT_MONITOR_NEW_INDEX    0
 #define BT_MONITOR_DEL_INDEX    1
@@ -95,6 +97,8 @@ static inline uint8_t bt_monitor_opcode(struct net_buf *buf)
 	}
 }
 
+/* TODO: Remove guard and replace with IS_ENABLED(CONFIG_BT_MONITOR) */
+#if defined(CONFIG_BT_MONITOR)
 void bt_monitor_send(uint16_t opcode, const void *data, size_t len);
 
 void bt_monitor_new_index(uint8_t type, uint8_t bus, const bt_addr_t *addr,
diff --git a/subsys/bluetooth/host/scan.c b/subsys/bluetooth/host/scan.c
index c3551c2ef07..7094ebd664d 100644
--- a/subsys/bluetooth/host/scan.c
+++ b/subsys/bluetooth/host/scan.c
@@ -4,31 +4,42 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#include <sys/types.h>
+#include <errno.h>
 #include <stdbool.h>
+#include <stddef.h>
 #include <stdint.h>
 #include <string.h>
 
-#include <zephyr/sys/atomic.h>
-#include <zephyr/kernel.h>
-#include <zephyr/sys/byteorder.h>
-#include <zephyr/sys/check.h>
-
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/iso.h>
 #include <zephyr/bluetooth/buf.h>
 #include <zephyr/bluetooth/direction.h>
 #include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/hci.h>
 #include <zephyr/bluetooth/hci_vs.h>
+#include <zephyr/kernel.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/check.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/toolchain.h>
+
+#include <sys/types.h>
 
 #include "addr_internal.h"
-#include "hci_core.h"
+#include "common/bt_str.h"
 #include "conn_internal.h"
 #include "direction_internal.h"
+#include "hci_core.h"
 #include "id.h"
-
-#include "common/bt_str.h"
 #include "scan.h"
 
 #define LOG_LEVEL CONFIG_BT_HCI_CORE_LOG_LEVEL
@@ -908,7 +919,7 @@ void bt_hci_le_adv_ext_report(struct net_buf *buf)
 		}
 
 		if (evt->length + ext_scan_buf.len > ext_scan_buf.size) {
-			/* The report does not fit in the reassemby buffer
+			/* The report does not fit in the reassembly buffer
 			 * Discard this and future reports from the advertiser.
 			 */
 			reassembling_advertiser.state = FRAG_ADV_DISCARDING;
@@ -1419,7 +1430,7 @@ void bt_hci_le_per_adv_sync_lost(struct net_buf *buf)
 	per_adv_sync = bt_hci_per_adv_sync_lookup_handle(sys_le16_to_cpu(evt->handle));
 
 	if (!per_adv_sync) {
-		LOG_ERR("Unknown handle 0x%04Xfor periodic adv sync lost",
+		LOG_ERR("Unknown handle 0x%04X for periodic adv sync lost",
 			sys_le16_to_cpu(evt->handle));
 		return;
 	}
diff --git a/subsys/bluetooth/host/scan.h b/subsys/bluetooth/host/scan.h
index 85e1e4f828b..6f9c094bc43 100644
--- a/subsys/bluetooth/host/scan.h
+++ b/subsys/bluetooth/host/scan.h
@@ -8,10 +8,12 @@
 #ifndef SUBSYS_BLUETOOTH_HOST_SCAN_H_
 #define SUBSYS_BLUETOOTH_HOST_SCAN_H_
 
+#include <stdbool.h>
 #include <stdint.h>
 
-#include <zephyr/sys/atomic.h>
 #include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/sys/atomic.h>
 
 /**
  * Reasons why a scanner can be running.
diff --git a/subsys/bluetooth/host/settings.c b/subsys/bluetooth/host/settings.c
index 1718bc653d4..84b4f1eb4b6 100644
--- a/subsys/bluetooth/host/settings.c
+++ b/subsys/bluetooth/host/settings.c
@@ -5,19 +5,28 @@
  */
 
 #include <errno.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
 
-#include <zephyr/kernel.h>
-#include <zephyr/settings/settings.h>
-#include <common/bt_settings_commit.h>
-
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/hci.h>
+#include <zephyr/settings/settings.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/printk.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/toolchain.h>
 
+#include "common/bt_settings_commit.h"
 #include "common/bt_str.h"
-
 #include "hci_core.h"
 #include "settings.h"
+#include "sys/types.h"
 
 #define LOG_LEVEL CONFIG_BT_SETTINGS_LOG_LEVEL
 #include <zephyr/logging/log.h>
diff --git a/subsys/bluetooth/host/settings.h b/subsys/bluetooth/host/settings.h
index cf5618b378d..526d850f70a 100644
--- a/subsys/bluetooth/host/settings.h
+++ b/subsys/bluetooth/host/settings.h
@@ -8,9 +8,8 @@
 #include <stdint.h>
 
 #include <zephyr/bluetooth/addr.h>
-
 #include <zephyr/settings/settings.h>
-#include <common/bt_settings_commit.h>
+#include "common/bt_settings_commit.h"
 
 /* Max settings key length (with all components) */
 #define BT_SETTINGS_KEY_MAX 36
diff --git a/subsys/bluetooth/host/shell/bt.c b/subsys/bluetooth/host/shell/bt.c
index c35e7c226e0..a2ee453b2ea 100644
--- a/subsys/bluetooth/host/shell/bt.c
+++ b/subsys/bluetooth/host/shell/bt.c
@@ -12,43 +12,52 @@
  */
 
 #include <errno.h>
-#include <zephyr/autoconf.h>
-#include <zephyr/bluetooth/audio/bap.h>
-#include <zephyr/bluetooth/gap.h>
-#include <zephyr/types.h>
-#include <ctype.h>
 #include <stddef.h>
+#include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
 #include <strings.h>
-#include <zephyr/sys/printk.h>
-#include <zephyr/sys/byteorder.h>
-#include <zephyr/sys/util.h>
-#include <zephyr/sys/util_macro.h>
-#include <zephyr/kernel.h>
-
-#include <zephyr/settings/settings.h>
+#include <sys/types.h>
 
-#include <zephyr/bluetooth/hci.h>
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/bluetooth.h>
-#include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/classic/rfcomm.h>
 #include <zephyr/bluetooth/classic/sdp.h>
-#include <zephyr/bluetooth/iso.h>
+#include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/ead.h>
-
+#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/bluetooth/iso.h>
+#include <zephyr/bluetooth/uuid.h>
+#include <zephyr/kernel.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/settings/settings.h>
 #include <zephyr/shell/shell.h>
-#include "common/bt_shell_private.h"
+#include <zephyr/shell/shell_string_conv.h>
+#include <zephyr/shell/shell_types.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/printk.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/toolchain.h>
+#include <zephyr/types.h>
 
 #include "audio/shell/audio.h"
+#include "common/bt_shell_private.h"
+#if defined(CONFIG_BT_LL_SW_SPLIT)
 #include "controller/ll_sw/shell/ll.h"
+#endif /* CONFIG_BT_LL_SW_SPLIT */
 #include "host/shell/bt.h"
 #include "mesh/shell/hci.h"
 
 static bool no_settings_load;
 
 uint8_t selected_id = BT_ID_DEFAULT;
-const struct shell *ctx_shell;
 
 #if defined(CONFIG_BT_CONN)
 struct bt_conn *default_conn;
@@ -362,7 +371,8 @@ static void print_data_set(uint8_t set_value_len,
 
 static bool data_verbose_cb(struct bt_data *data, void *user_data)
 {
-	bt_shell_fprintf_info("%*sType 0x%02x: ", strlen(scan_response_label), "", data->type);
+	bt_shell_fprintf_info("%*sType 0x%02x: ",
+			      (int)strlen(scan_response_label), "", data->type);
 
 	switch (data->type) {
 	case BT_DATA_UUID16_SOME:
@@ -573,10 +583,10 @@ static void scan_recv(const struct bt_le_scan_recv_info *info, struct net_buf_si
 
 	if (scan_verbose_output) {
 		bt_shell_info("%*s[SCAN DATA START - %s]",
-			      strlen(scan_response_label), "",
+			      (int)strlen(scan_response_label), "",
 			      scan_response_type_txt(info->adv_type));
 		bt_data_parse(&buf_copy, data_verbose_cb, NULL);
-		bt_shell_info("%*s[SCAN DATA END]", strlen(scan_response_label), "");
+		bt_shell_info("%*s[SCAN DATA END]", (int)strlen(scan_response_label), "");
 	}
 
 #if defined(CONFIG_BT_CENTRAL)
@@ -1334,8 +1344,6 @@ static int cmd_init(const struct shell *sh, size_t argc, char *argv[])
 	int err;
 	bool sync = false;
 
-	ctx_shell = sh;
-
 	for (size_t argn = 1; argn < argc; argn++) {
 		const char *arg = argv[argn];
 
@@ -1523,7 +1531,7 @@ static int cmd_id_reset(const struct shell *sh, size_t argc, char *argv[])
 	int err;
 
 	if (argc < 2) {
-		shell_error(sh, "Identity identifier not specified");
+		shell_error(sh, "Identity handle not specified");
 		return -ENOEXEC;
 	}
 
@@ -1557,7 +1565,7 @@ static int cmd_id_delete(const struct shell *sh, size_t argc, char *argv[])
 	int err;
 
 	if (argc < 2) {
-		shell_error(sh, "Identity identifier not specified");
+		shell_error(sh, "Identity handle not specified");
 		return -ENOEXEC;
 	}
 
@@ -1959,7 +1967,7 @@ static ssize_t ad_init(struct bt_data *data_array, const size_t data_array_size,
 		csis_ad_len = csis_ad_data_add(&data_array[ad_len],
 					       data_array_size - ad_len, discoverable);
 		if (csis_ad_len < 0) {
-			bt_shell_error("Failed to add CSIS data (err %d)", csis_ad_len);
+			bt_shell_error("Failed to add CSIS data (err %zd)", csis_ad_len);
 			return ad_len;
 		}
 
@@ -1968,15 +1976,9 @@ static ssize_t ad_init(struct bt_data *data_array, const size_t data_array_size,
 
 	if (IS_ENABLED(CONFIG_BT_AUDIO) && IS_ENABLED(CONFIG_BT_EXT_ADV) && adv_ext) {
 		const bool connectable = atomic_test_bit(adv_options, SHELL_ADV_OPT_CONNECTABLE);
-		ssize_t audio_ad_len;
-
-		audio_ad_len = audio_ad_data_add(&data_array[ad_len], data_array_size - ad_len,
-						 discoverable, connectable);
-		if (audio_ad_len < 0) {
-			return audio_ad_len;
-		}
 
-		ad_len += audio_ad_len;
+		ad_len += audio_ad_data_add(&data_array[ad_len], data_array_size - ad_len,
+					    discoverable, connectable);
 	}
 
 	return ad_len;
@@ -3803,13 +3805,8 @@ static int cmd_clear(const struct shell *sh, size_t argc, char *argv[])
 	}
 
 	if (argc < 3) {
-#if defined(CONFIG_BT_CLASSIC)
-		addr.type = BT_ADDR_LE_PUBLIC;
-		err = bt_addr_from_str(argv[1], &addr.a);
-#else
 		shell_print(sh, "Both address and address type needed");
 		return -ENOEXEC;
-#endif
 	} else {
 		err = bt_addr_le_from_str(argv[1], argv[2], &addr);
 	}
@@ -4146,8 +4143,23 @@ static void auth_pairing_oob_data_request(struct bt_conn *conn,
 static void auth_pairing_complete(struct bt_conn *conn, bool bonded)
 {
 	char addr[BT_ADDR_LE_STR_LEN];
+	struct bt_conn_info info;
 
-	bt_addr_le_to_str(bt_conn_get_dst(conn), addr, sizeof(addr));
+	if (bt_conn_get_info(conn, &info) < 0) {
+		return;
+	}
+
+	switch (info.type) {
+	case BT_CONN_TYPE_LE:
+		bt_addr_le_to_str(info.le.dst, addr, sizeof(addr));
+		break;
+	case BT_CONN_TYPE_BR:
+		bt_addr_to_str(info.br.dst, addr, sizeof(addr));
+		break;
+	default:
+		bt_shell_print("Unrecognized conn type: %d", info.type);
+		return;
+	}
 
 	bt_shell_print("%s with %s", bonded ? "Bonded" : "Paired", addr);
 }
@@ -4155,8 +4167,23 @@ static void auth_pairing_complete(struct bt_conn *conn, bool bonded)
 static void auth_pairing_failed(struct bt_conn *conn, enum bt_security_err err)
 {
 	char addr[BT_ADDR_LE_STR_LEN];
+	struct bt_conn_info info;
 
-	bt_addr_le_to_str(bt_conn_get_dst(conn), addr, sizeof(addr));
+	if (bt_conn_get_info(conn, &info) < 0) {
+		return;
+	}
+
+	switch (info.type) {
+	case BT_CONN_TYPE_LE:
+		bt_addr_le_to_str(info.le.dst, addr, sizeof(addr));
+		break;
+	case BT_CONN_TYPE_BR:
+		bt_addr_to_str(info.br.dst, addr, sizeof(addr));
+		break;
+	default:
+		bt_shell_print("Unrecognized conn type: %d", info.type);
+		return;
+	}
 
 	bt_shell_print("Pairing failed with %s reason: %s (%d)", addr, security_err_str(err), err);
 }
@@ -4216,6 +4243,16 @@ void bond_deleted(uint8_t id, const bt_addr_le_t *peer)
 	bt_shell_print("Bond deleted for %s, id %u", addr, id);
 }
 
+#if defined(CONFIG_BT_CLASSIC)
+static void br_bond_deleted(const bt_addr_t *peer)
+{
+	char addr[BT_ADDR_STR_LEN];
+
+	bt_addr_to_str(peer, addr, sizeof(addr));
+	bt_shell_print("Classic bond deleted for %s", addr);
+}
+#endif /* CONFIG_BT_CLASSIC */
+
 static struct bt_conn_auth_cb auth_cb_display = {
 	.passkey_display = auth_passkey_display,
 #if defined(CONFIG_BT_PASSKEY_KEYPRESS)
@@ -4316,6 +4353,9 @@ static struct bt_conn_auth_info_cb auth_info_cb = {
 	.pairing_failed = auth_pairing_failed,
 	.pairing_complete = auth_pairing_complete,
 	.bond_deleted = bond_deleted,
+#if defined(CONFIG_BT_CLASSIC)
+	.br_bond_deleted = br_bond_deleted,
+#endif /* CONFIG_BT_CLASSIC */
 };
 
 static int cmd_auth(const struct shell *sh, size_t argc, char *argv[])
diff --git a/subsys/bluetooth/host/shell/bt.h b/subsys/bluetooth/host/shell/bt.h
index 9ba015f7e17..ca612d2e95e 100644
--- a/subsys/bluetooth/host/shell/bt.h
+++ b/subsys/bluetooth/host/shell/bt.h
@@ -12,11 +12,14 @@
 
 #ifndef __BT_H
 #define __BT_H
+#include <stddef.h>
+#include <stdint.h>
 
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/net_buf.h>
 #include <sys/types.h>
 
-extern const struct shell *ctx_shell;
 extern struct bt_conn *default_conn;
 
 bool passes_scan_filter(const struct bt_le_scan_recv_info *info, const struct net_buf_simple *buf);
diff --git a/subsys/bluetooth/host/shell/cs.c b/subsys/bluetooth/host/shell/cs.c
index adacd94bca9..964eff9c65c 100644
--- a/subsys/bluetooth/host/shell/cs.c
+++ b/subsys/bluetooth/host/shell/cs.c
@@ -9,23 +9,26 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <errno.h>
 #include <stdlib.h>
 #include <stdbool.h>
 #include <stdint.h>
-#include <zephyr/kernel.h>
-#include <zephyr/shell/shell.h>
-#include <zephyr/sys/byteorder.h>
-#include <zephyr/sys/util.h>
+#include <string.h>
 
 #include <zephyr/bluetooth/hci.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/iso.h>
 #include <zephyr/bluetooth/cs.h>
-#include <errno.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/shell/shell_string_conv.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util.h>
 
-#include "host/shell/bt.h"
 #include "common/bt_shell_private.h"
+#include "host/shell/bt.h"
 
 static int check_cs_sync_antenna_selection_input(uint16_t input)
 {
@@ -137,6 +140,7 @@ static int cmd_read_remote_fae_table(const struct shell *sh, size_t argc, char *
 	return 0;
 }
 
+#if defined(CONFIG_BT_CHANNEL_SOUNDING_TEST)
 static bool process_step_data(struct bt_le_cs_subevent_step *step, void *user_data)
 {
 	bt_shell_print("Subevent results contained step data: ");
@@ -254,6 +258,7 @@ static int cmd_cs_test_simple(const struct shell *sh, size_t argc, char *argv[])
 
 	return 0;
 }
+#endif /* CONFIG_BT_CHANNEL_SOUNDING_TEST */
 
 static int cmd_remove_config(const struct shell *sh, size_t argc, char *argv[])
 {
@@ -430,6 +435,7 @@ static int cmd_create_config(const struct shell *sh, size_t argc, char *argv[])
 	return 0;
 }
 
+#if defined(CONFIG_BT_CHANNEL_SOUNDING_TEST)
 static int cmd_cs_stop_test(const struct shell *sh, size_t argc, char *argv[])
 {
 	int err = 0;
@@ -442,6 +448,7 @@ static int cmd_cs_stop_test(const struct shell *sh, size_t argc, char *argv[])
 
 	return 0;
 }
+#endif /* CONFIG_BT_CHANNEL_SOUNDING_TEST */
 
 static int cmd_read_local_supported_capabilities(const struct shell *sh, size_t argc, char *argv[])
 {
@@ -702,9 +709,11 @@ SHELL_STATIC_SUBCMD_SET_CREATE(
 		" <CS_SYNC antenna selection: 0x01 - 0x04, 0xFE, 0xFF> <Max TX power: -127 - 20>",
 		cmd_set_default_settings, 5, 0),
 	SHELL_CMD_ARG(read_remote_fae_table, NULL, "<None>", cmd_read_remote_fae_table, 1, 0),
+#if defined(CONFIG_BT_CHANNEL_SOUNDING_TEST)
 	SHELL_CMD_ARG(start_simple_cs_test, NULL, "<Role selection (initiator, reflector): 0, 1>",
 		      cmd_cs_test_simple, 2, 0),
 	SHELL_CMD_ARG(stop_cs_test, NULL, "<None>", cmd_cs_stop_test, 1, 0),
+#endif /* CONFIG_BT_CHANNEL_SOUNDING_TEST */
 	SHELL_CMD_ARG(
 		create_config, NULL,
 		"<id> <context: local-only, local-remote> <role: initiator, reflector> "
diff --git a/subsys/bluetooth/host/shell/gatt.c b/subsys/bluetooth/host/shell/gatt.c
index 35543a0e285..30919f0966b 100644
--- a/subsys/bluetooth/host/shell/gatt.c
+++ b/subsys/bluetooth/host/shell/gatt.c
@@ -10,24 +10,28 @@
  */
 
 #include <errno.h>
-#include <zephyr/types.h>
 #include <stddef.h>
 #include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
-#include <zephyr/shell/shell_string_conv.h>
-#include <zephyr/sys/byteorder.h>
-#include <zephyr/sys/util.h>
-#include <zephyr/kernel.h>
 
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/att.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gatt.h>
-
+#include <zephyr/bluetooth/uuid.h>
+#include <zephyr/kernel.h>
 #include <zephyr/shell/shell.h>
+#include <zephyr/shell/shell_string_conv.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/time_units.h>
+#include <zephyr/sys/util.h>
+#include <sys/types.h>
 
-#include "host/shell/bt.h"
 #include "common/bt_shell_private.h"
+#include "host/shell/bt.h"
 
 #if defined(CONFIG_BT_GATT_CLIENT) || defined(CONFIG_BT_GATT_DYNAMIC_DB)
 extern uint8_t selected_id;
@@ -740,7 +744,7 @@ static int cmd_show_db(const struct shell *sh, size_t argc, char *argv[])
 	total_len = stats.svc_count * sizeof(struct bt_gatt_service);
 	total_len += stats.chrc_count * sizeof(struct bt_gatt_chrc);
 	total_len += stats.attr_count * sizeof(struct bt_gatt_attr);
-	total_len += stats.ccc_count * sizeof(struct _bt_gatt_ccc);
+	total_len += stats.ccc_count * sizeof(struct bt_gatt_ccc_managed_user_data);
 
 	shell_print(sh, "=================================================");
 	shell_print(sh, "Total: %u services %u attributes (%zu bytes)",
@@ -1013,7 +1017,7 @@ static void notify_cb(struct bt_conn *conn, void *user_data)
 {
 	const struct shell *sh = user_data;
 
-	shell_print(sh, "Nofication sent to conn %p", conn);
+	shell_print(sh, "Notification sent to conn %p", conn);
 }
 static int cmd_notify_mult(const struct shell *sh, size_t argc, char *argv[])
 {
diff --git a/subsys/bluetooth/host/shell/iso.c b/subsys/bluetooth/host/shell/iso.c
index 3b6340c5e9c..cc2adda15cd 100644
--- a/subsys/bluetooth/host/shell/iso.c
+++ b/subsys/bluetooth/host/shell/iso.c
@@ -5,22 +5,30 @@
 
 /*
  * Copyright (c) 2020 Intel Corporation
- * Copyright (c) 2021 Nordic Semiconductor ASA
+ * Copyright (c) 2021-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-
+#include <errno.h>
+#include <stddef.h>
+#include <stdint.h>
 #include <stdlib.h>
-#include <ctype.h>
-#include <zephyr/kernel.h>
-#include <zephyr/shell/shell.h>
-#include <zephyr/sys/byteorder.h>
-#include <zephyr/sys/util.h>
+#include <string.h>
 
+#include <zephyr/bluetooth/gap.h>
 #include <zephyr/bluetooth/hci.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/iso.h>
+#include <zephyr/kernel.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/shell/shell.h>
+#include <zephyr/shell/shell_string_conv.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/time_units.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
 
 #include "host/shell/bt.h"
 #include "common/bt_shell_private.h"
@@ -84,6 +92,10 @@ static void iso_recv(struct bt_iso_chan *chan, const struct bt_iso_recv_info *in
 
 static void iso_connected(struct bt_iso_chan *chan)
 {
+	const struct bt_iso_chan_path hci_path = {
+		.pid = BT_ISO_DATA_PATH_HCI,
+		.format = BT_HCI_CODING_FORMAT_TRANSPARENT,
+	};
 	struct bt_iso_info iso_info;
 	int err;
 
@@ -91,12 +103,13 @@ static void iso_connected(struct bt_iso_chan *chan)
 
 	err = bt_iso_chan_get_info(chan, &iso_info);
 	if (err != 0) {
-		printk("Failed to get ISO info: %d", err);
+		bt_shell_error("Failed to get ISO info: %d", err);
 		return;
 	}
 
 #if defined(CONFIG_BT_ISO_TX)
-	if (iso_info.type == BT_ISO_CHAN_TYPE_CONNECTED) {
+	if (iso_info.type == BT_ISO_CHAN_TYPE_CENTRAL ||
+	    iso_info.type == BT_ISO_CHAN_TYPE_PERIPHERAL) {
 		cis_sn_last = 0U;
 		cis_sn_last_updated_ticks = k_uptime_ticks();
 	} else {
@@ -104,12 +117,47 @@ static void iso_connected(struct bt_iso_chan *chan)
 		bis_sn_last_updated_ticks = k_uptime_ticks();
 	}
 #endif /* CONFIG_BT_ISO_TX */
+
+	if (iso_info.can_recv) {
+		err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_CTLR_TO_HOST, &hci_path);
+		if (err != 0) {
+			bt_shell_error("Failed to setup ISO RX data path: %d", err);
+		}
+	}
+
+	if (iso_info.can_send) {
+		err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR, &hci_path);
+		if (err != 0) {
+			bt_shell_error("Failed to setup ISO TX data path: %d", err);
+		}
+	}
 }
 
 static void iso_disconnected(struct bt_iso_chan *chan, uint8_t reason)
 {
-	bt_shell_print("ISO Channel %p disconnected with reason 0x%02x",
-		       chan, reason);
+	struct bt_iso_info iso_info;
+	int err;
+
+	bt_shell_print("ISO Channel %p disconnected with reason 0x%02x", chan, reason);
+
+	err = bt_iso_chan_get_info(chan, &iso_info);
+	if (err != 0) {
+		bt_shell_error("Failed to get ISO info: %d", err);
+	} else if (iso_info.type == BT_ISO_CHAN_TYPE_CENTRAL) {
+		if (iso_info.can_recv) {
+			err = bt_iso_remove_data_path(chan, BT_HCI_DATAPATH_DIR_CTLR_TO_HOST);
+			if (err != 0) {
+				bt_shell_error("Failed to remove ISO RX data path: %d", err);
+			}
+		}
+
+		if (iso_info.can_send) {
+			err = bt_iso_remove_data_path(chan, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR);
+			if (err != 0) {
+				bt_shell_error("Failed to remove ISO TX data path: %d", err);
+			}
+		}
+	}
 }
 
 static struct bt_iso_chan_ops iso_ops = {
@@ -557,6 +605,12 @@ static int cmd_send(const struct shell *sh, size_t argc, char *argv[])
 
 			return -ENOEXEC;
 		}
+
+		if (count < 1) {
+			shell_error(sh, "Cannot send 0 times");
+
+			return -ENOEXEC;
+		}
 	}
 
 	if (!iso_chan.iso) {
@@ -673,6 +727,12 @@ static int cmd_broadcast(const struct shell *sh, size_t argc, char *argv[])
 
 			return -ENOEXEC;
 		}
+
+		if (count < 1) {
+			shell_error(sh, "Cannot send 0 times");
+
+			return -ENOEXEC;
+		}
 	}
 
 	if (!bis_iso_chan.iso) {
diff --git a/subsys/bluetooth/host/shell/l2cap.c b/subsys/bluetooth/host/shell/l2cap.c
index 07fc465163c..e01a1c940e7 100644
--- a/subsys/bluetooth/host/shell/l2cap.c
+++ b/subsys/bluetooth/host/shell/l2cap.c
@@ -11,26 +11,30 @@
  */
 
 #include <errno.h>
-#include <zephyr/types.h>
 #include <stddef.h>
+#include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
-#include <zephyr/sys/byteorder.h>
-#include <zephyr/kernel.h>
-
-#include <zephyr/settings/settings.h>
 
 #include <zephyr/bluetooth/hci.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/l2cap.h>
 #include <zephyr/bluetooth/classic/rfcomm.h>
 #include <zephyr/bluetooth/classic/sdp.h>
-
+#include <zephyr/net_buf.h>
+#include <zephyr/settings/settings.h>
 #include <zephyr/shell/shell.h>
+#include <zephyr/shell/shell_string_conv.h>
+#include <zephyr/sys/atomic_types.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/time_units.h>
+#include <zephyr/sys/util.h>
 
-#include "host/shell/bt.h"
 #include "common/bt_shell_private.h"
+#include "host/shell/bt.h"
 
 #define CREDITS			10
 #define DATA_MTU		(23 * CREDITS)
diff --git a/subsys/bluetooth/host/smp.c b/subsys/bluetooth/host/smp.c
index d439024d5c5..667c8919181 100644
--- a/subsys/bluetooth/host/smp.c
+++ b/subsys/bluetooth/host/smp.c
@@ -4,20 +4,26 @@
  */
 
 /*
- * Copyright (c) 2017 Nordic Semiconductor ASA
+ * Copyright (c) 2017-2025 Nordic Semiconductor ASA
  * Copyright (c) 2015-2016 Intel Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <errno.h>
+#include <stdbool.h>
 #include <stddef.h>
+#include <stdint.h>
 #include <string.h>
 
+#include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/buf.h>
 #include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/crypto.h>
 #include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/bluetooth/l2cap.h>
 #include <zephyr/debug/stack.h>
 #include <zephyr/kernel.h>
 #include <zephyr/net_buf.h>
@@ -25,17 +31,18 @@
 #include <zephyr/sys/atomic.h>
 #include <zephyr/sys/byteorder.h>
 #include <zephyr/sys/check.h>
+#include <zephyr/sys/slist.h>
 #include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/toolchain.h>
 
-
+#include "conn_internal.h"
 #include "common/bt_str.h"
-
 #include "crypto/bt_crypto.h"
-
-#include "hci_core.h"
 #include "ecc.h"
+#include "hci_core.h"
 #include "keys.h"
-#include "conn_internal.h"
 #include "l2cap_internal.h"
 #include "smp.h"
 
@@ -262,6 +269,9 @@ struct bt_smp_br {
 	/* Remote key distribution */
 	uint8_t			remote_dist;
 
+	/* Local keys have been distributed */
+	uint8_t			local_distributed;
+
 	/* Encryption Key Size used for connection */
 	uint8_t 			enc_key_size;
 
@@ -749,6 +759,47 @@ static void smp_sign_info_sent(struct bt_conn *conn, void *user_data, int err)
 #endif /* CONFIG_BT_SIGNING */
 
 #if defined(CONFIG_BT_CLASSIC)
+static bool ltk_derive_link_key_allowed(struct bt_smp *smp)
+{
+	struct bt_conn *conn;
+	struct bt_keys_link_key *link_key;
+	struct bt_keys *keys;
+
+	if (!smp->chan.chan.conn) {
+		return false;
+	}
+
+	conn = smp->chan.chan.conn;
+	keys = conn->le.keys;
+	if (keys == NULL) {
+		return false;
+	}
+
+	/* Check whether it is has been bonded */
+	link_key = bt_keys_find_link_key(&conn->le.dst.a);
+	if (link_key == NULL) {
+		return true;
+	}
+
+	if (link_key->flags & BT_LINK_KEY_DEBUG) {
+		LOG_DBG("Debug LK can be overwrote");
+		return true;
+	}
+
+	if ((link_key->flags & BT_LINK_KEY_AUTHENTICATED) &&
+	    ((keys->flags & BT_KEYS_AUTHENTICATED) == 0)) {
+		LOG_DBG("Stronger LK (MITM) cannot be overwrote by weaker LTK");
+		return false;
+	}
+
+	if ((link_key->flags & BT_LINK_KEY_SC) && ((keys->flags & BT_KEYS_SC) == 0)) {
+		LOG_DBG("Stronger LK (SC) cannot be overwrote by weaker LTK");
+		return false;
+	}
+
+	return true;
+}
+
 static void sc_derive_link_key(struct bt_smp *smp)
 {
 	/* constants as specified in Core Spec Vol.3 Part H 2.4.2.4 */
@@ -761,6 +812,17 @@ static void sc_derive_link_key(struct bt_smp *smp)
 
 	/* TODO handle errors? */
 
+	if (!ltk_derive_link_key_allowed(smp)) {
+		LOG_DBG("LK cannot be derived by LTK");
+		return;
+	}
+
+	/* Remove the bonding information */
+	link_key = bt_keys_find_link_key(&conn->le.dst.a);
+	if (link_key != NULL) {
+		bt_keys_link_key_clear(link_key);
+	}
+
 	/*
 	 * At this point remote device identity is known so we can use
 	 * destination address here
@@ -795,22 +857,38 @@ static void sc_derive_link_key(struct bt_smp *smp)
 		bt_keys_link_key_clear(link_key);
 	}
 
-	link_key->flags |= BT_LINK_KEY_SC;
+	if (conn->le.keys->flags & BT_KEYS_SC) {
+		link_key->flags |= BT_LINK_KEY_SC;
+	} else {
+		link_key->flags &= ~BT_LINK_KEY_SC;
+	}
 
 	if (conn->le.keys->flags & BT_KEYS_AUTHENTICATED) {
 		link_key->flags |= BT_LINK_KEY_AUTHENTICATED;
 	} else {
 		link_key->flags &= ~BT_LINK_KEY_AUTHENTICATED;
 	}
+
+	if (atomic_test_bit(smp->flags, SMP_FLAG_BOND)) {
+		/* Store the link key */
+		bt_keys_link_key_store(link_key);
+	}
 }
 
 static void smp_br_reset(struct bt_smp_br *smp)
 {
+	bool br_smp_connected;
+
+	br_smp_connected = atomic_test_bit(smp->flags, SMP_FLAG_BR_CONNECTED);
+
 	/* Clear flags first in case canceling of timeout fails. The SMP context
 	 * shall be marked as timed out in that case.
 	 */
 	atomic_set(smp->flags, 0);
 
+	/* Set back the status of the flag SMP_FLAG_BR_CONNECTED. */
+	atomic_set_bit_to(smp->flags, SMP_FLAG_BR_CONNECTED, br_smp_connected);
+
 	/* If canceling fails the timeout handler will set the timeout flag and
 	 * mark the it as timed out. No new pairing procedures shall be started
 	 * on this connection if that happens.
@@ -822,6 +900,29 @@ static void smp_br_reset(struct bt_smp_br *smp)
 	atomic_set_bit(smp->allowed_cmds, BT_SMP_CMD_PAIRING_REQ);
 }
 
+static void smp_br_id_add_replace(struct bt_keys *keys)
+{
+	struct bt_keys *conflict;
+
+	/* Check whether key has been added to resolving list. */
+	if (keys->state & BT_KEYS_ID_ADDED) {
+		bt_id_del(keys);
+	}
+
+	conflict = bt_id_find_conflict(keys);
+	if (conflict != NULL) {
+		int err;
+
+		LOG_DBG("Un-pairing old conflicting bond and finalizing new.");
+
+		err = bt_unpair(conflict->id, &conflict->addr);
+		__ASSERT_NO_MSG(!err);
+	}
+
+	__ASSERT_NO_MSG(!bt_id_find_conflict(keys));
+	bt_id_add(keys);
+}
+
 static void smp_pairing_br_complete(struct bt_smp_br *smp, uint8_t status)
 {
 	struct bt_conn *conn = smp->chan.chan.conn;
@@ -852,9 +953,13 @@ static void smp_pairing_br_complete(struct bt_smp_br *smp, uint8_t status)
 			}
 		}
 	} else {
-		bool bond_flag = atomic_test_bit(smp->flags, SMP_FLAG_BOND);
+		bool bond_flag = !atomic_test_bit(conn->flags, BT_CONN_BR_NOBOND);
 		struct bt_conn_auth_info_cb *listener, *next;
 
+		if (keys) {
+			smp_br_id_add_replace(keys);
+		}
+
 		if (bond_flag && keys) {
 			bt_keys_store(keys);
 		}
@@ -934,11 +1039,18 @@ static void bt_smp_br_disconnected(struct bt_l2cap_chan *chan)
 
 static void smp_br_init(struct bt_smp_br *smp)
 {
+	bool br_smp_connected;
+
+	br_smp_connected = atomic_test_bit(smp->flags, SMP_FLAG_BR_CONNECTED);
+
 	/* Initialize SMP context excluding L2CAP channel context and anything
 	 * else declared after.
 	 */
 	(void)memset(smp, 0, offsetof(struct bt_smp_br, chan));
 
+	/* Set back the status of the flag SMP_FLAG_BR_CONNECTED. */
+	atomic_set_bit_to(smp->flags, SMP_FLAG_BR_CONNECTED, br_smp_connected);
+
 	atomic_set_bit(smp->allowed_cmds, BT_SMP_CMD_PAIRING_FAIL);
 }
 
@@ -958,7 +1070,8 @@ static void smp_br_derive_ltk(struct bt_smp_br *smp)
 		return;
 	}
 
-	if (IS_ENABLED(CONFIG_BT_SMP_FORCE_BREDR) && conn->encrypt != 0x02) {
+	if (IS_ENABLED(CONFIG_BT_SMP_FORCE_BREDR) &&
+	    conn->encrypt != BT_HCI_ENCRYPTION_ON_BR_AES_CCM) {
 		LOG_WRN("Using P192 Link Key for P256 LTK derivation");
 	}
 
@@ -969,6 +1082,12 @@ static void smp_br_derive_ltk(struct bt_smp_br *smp)
 	bt_addr_copy(&addr.a, &conn->br.dst);
 	addr.type = BT_ADDR_LE_PUBLIC;
 
+	keys = bt_keys_find_addr(conn->id, &addr);
+	if (keys != NULL) {
+		LOG_DBG("Clear the current keys for %s", bt_addr_le_str(&addr));
+		bt_keys_clear(keys);
+	}
+
 	keys = bt_keys_get_type(BT_KEYS_LTK_P256, conn->id, &addr);
 	if (!keys) {
 		LOG_ERR("Unable to get keys for %s", bt_addr_le_str(&addr));
@@ -1011,6 +1130,12 @@ static void smp_br_derive_ltk(struct bt_smp_br *smp)
 		keys->flags &= ~BT_KEYS_AUTHENTICATED;
 	}
 
+	if (conn->encrypt == BT_HCI_ENCRYPTION_ON_BR_AES_CCM) {
+		keys->flags |= BT_KEYS_SC;
+	} else {
+		keys->flags &= ~BT_KEYS_SC;
+	}
+
 	LOG_DBG("LTK derived from LinkKey");
 }
 
@@ -1066,12 +1191,13 @@ static void smp_br_distribute_keys(struct bt_smp_br *smp)
 	}
 
 #if defined(CONFIG_BT_PRIVACY)
-	if (smp->local_dist & BT_SMP_DIST_ID_KEY) {
+	if ((smp->local_dist & BT_SMP_DIST_ID_KEY) &&
+	    ((smp->local_distributed & BT_SMP_DIST_ID_KEY) == 0)) {
 		struct bt_smp_ident_info *id_info;
 		struct bt_smp_ident_addr_info *id_addr_info;
 		struct net_buf *buf;
 
-		smp->local_dist &= ~BT_SMP_DIST_ID_KEY;
+		smp->local_distributed |= BT_SMP_DIST_ID_KEY;
 
 		buf = smp_br_create_pdu(smp, BT_SMP_CMD_IDENT_INFO,
 					sizeof(*id_info));
@@ -1100,11 +1226,12 @@ static void smp_br_distribute_keys(struct bt_smp_br *smp)
 #endif /* CONFIG_BT_PRIVACY */
 
 #if defined(CONFIG_BT_SIGNING)
-	if (smp->local_dist & BT_SMP_DIST_SIGN) {
+	if ((smp->local_dist & BT_SMP_DIST_SIGN) &&
+	    ((smp->local_distributed & BT_SMP_DIST_SIGN) == 0)) {
 		struct bt_smp_signing_info *info;
 		struct net_buf *buf;
 
-		smp->local_dist &= ~BT_SMP_DIST_SIGN;
+		smp->local_distributed |= BT_SMP_DIST_SIGN;
 
 		buf = smp_br_create_pdu(smp, BT_SMP_CMD_SIGNING_INFO,
 					sizeof(*info));
@@ -1133,12 +1260,42 @@ static void smp_br_distribute_keys(struct bt_smp_br *smp)
 
 static bool smp_br_pairing_allowed(struct bt_smp_br *smp)
 {
-	if (smp->chan.chan.conn->encrypt == 0x02) {
+	bt_addr_le_t addr;
+	struct bt_conn *conn;
+	struct bt_keys_link_key *key;
+	bool le_bonded;
+
+	if (!smp->chan.chan.conn) {
+		return false;
+	}
+
+	conn = smp->chan.chan.conn;
+
+	addr.type = BT_ADDR_LE_PUBLIC;
+	bt_addr_copy(&addr.a, &conn->br.dst);
+	le_bonded = bt_le_bond_exists(BT_ID_DEFAULT, &addr);
+
+	key = bt_keys_find_link_key(&conn->br.dst);
+	if (!key) {
+		return false;
+	}
+
+	/**
+	 * Core v6.0, Vol 3, Part C, 14.1 Cross-transport key derivation
+	 *
+	 * If an LE LTK already exists and the BR/EDR link key is weaker in either strength
+	 * or MITM protection, then neither device shall generate an LE LTK using cross-transport
+	 * key derivation from a BR/EDR link key.
+	 */
+	if (le_bonded && !(key->flags & BT_LINK_KEY_AUTHENTICATED)) {
+		return false;
+	}
+
+	if (conn->encrypt == BT_HCI_ENCRYPTION_ON_BR_AES_CCM) {
 		return true;
 	}
 
-	if (IS_ENABLED(CONFIG_BT_SMP_FORCE_BREDR) &&
-	    smp->chan.chan.conn->encrypt == 0x01) {
+	if (IS_ENABLED(CONFIG_BT_SMP_FORCE_BREDR) && conn->encrypt == BT_HCI_ENCRYPTION_ON_BR_E0) {
 		LOG_WRN("Allowing BR/EDR SMP with P-192 key");
 		return true;
 	}
@@ -1201,7 +1358,7 @@ static uint8_t smp_br_pairing_req(struct bt_smp_br *smp, struct net_buf *buf)
 	rsp->oob_flag = 0x00;
 	rsp->max_key_size = max_key_size;
 	rsp->init_key_dist = (req->init_key_dist & BR_RECV_KEYS_SC);
-	rsp->resp_key_dist = (req->resp_key_dist & BR_RECV_KEYS_SC);
+	rsp->resp_key_dist = (req->resp_key_dist & BR_SEND_KEYS_SC);
 
 	smp->local_dist = rsp->resp_key_dist;
 	smp->remote_dist = rsp->init_key_dist;
@@ -4240,7 +4397,7 @@ static uint8_t smp_public_key_periph(struct bt_smp *smp)
 
 	if (!atomic_test_bit(smp->flags, SMP_FLAG_SC_DEBUG_KEY) &&
 	    memcmp(smp->pkey, sc_public_key, BT_PUB_KEY_COORD_LEN) == 0) {
-		/* Deny public key with identitcal X coordinate unless it is the
+		/* Deny public key with identical X coordinate unless it is the
 		 * debug public key.
 		 */
 		LOG_WRN("Remote public key rejected");
@@ -4326,7 +4483,7 @@ static uint8_t smp_public_key(struct bt_smp *smp, struct net_buf *buf)
 	    smp->chan.chan.conn->role == BT_HCI_ROLE_CENTRAL) {
 		if (!atomic_test_bit(smp->flags, SMP_FLAG_SC_DEBUG_KEY) &&
 		    memcmp(smp->pkey, sc_public_key, BT_PUB_KEY_COORD_LEN) == 0) {
-			/* Deny public key with identitcal X coordinate unless
+			/* Deny public key with identical X coordinate unless
 			 * it is the debug public key.
 			 */
 			LOG_WRN("Remote public key rejected");
@@ -5468,6 +5625,11 @@ int bt_conn_set_bondable(struct bt_conn *conn, bool enable)
 {
 	struct bt_smp *smp;
 
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE | BT_CONN_TYPE_BR)) {
+		LOG_DBG("Invalid connection type: %u for %p", conn->type, conn);
+		return -EINVAL;
+	}
+
 	if (IS_ENABLED(CONFIG_BT_CLASSIC) && (conn->type == BT_CONN_TYPE_BR)) {
 		if (enable && atomic_test_and_set_bit(conn->flags, BT_CONN_BR_BONDABLE)) {
 			return -EALREADY;
diff --git a/subsys/bluetooth/host/smp.h b/subsys/bluetooth/host/smp.h
index 51969aaadfb..9bc7e29ff85 100644
--- a/subsys/bluetooth/host/smp.h
+++ b/subsys/bluetooth/host/smp.h
@@ -9,6 +9,16 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/toolchain.h>
+
 struct bt_smp_hdr {
 	uint8_t  code;
 } __packed;
diff --git a/subsys/bluetooth/host/smp_null.c b/subsys/bluetooth/host/smp_null.c
index 77774e99934..0ff20b4a16d 100644
--- a/subsys/bluetooth/host/smp_null.c
+++ b/subsys/bluetooth/host/smp_null.c
@@ -9,22 +9,26 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/kernel.h>
 #include <errno.h>
-#include <zephyr/sys/atomic.h>
-#include <zephyr/sys/util.h>
+#include <stddef.h>
 
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/buf.h>
+#include <zephyr/bluetooth/l2cap.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/toolchain.h>
 
-#include "hci_core.h"
 #include "conn_internal.h"
+#include "hci_core.h"
 #include "l2cap_internal.h"
 #include "smp.h"
 
 #define LOG_LEVEL CONFIG_BT_HCI_CORE_LOG_LEVEL
-#include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(bt_smp);
 
 static struct bt_l2cap_le_chan bt_smp_pool[CONFIG_BT_MAX_CONN];
diff --git a/subsys/bluetooth/host/uuid.c b/subsys/bluetooth/host/uuid.c
index 9995487db59..2d48f2a2a9f 100644
--- a/subsys/bluetooth/host/uuid.c
+++ b/subsys/bluetooth/host/uuid.c
@@ -6,12 +6,14 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <string.h>
 #include <errno.h>
-#include <zephyr/sys/byteorder.h>
-#include <zephyr/sys/printk.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
 
 #include <zephyr/bluetooth/uuid.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/printk.h>
 
 #define UUID_16_BASE_OFFSET 12
 
diff --git a/subsys/bluetooth/mesh/lpn.c b/subsys/bluetooth/mesh/lpn.c
index 862ab784890..8eef0573375 100644
--- a/subsys/bluetooth/mesh/lpn.c
+++ b/subsys/bluetooth/mesh/lpn.c
@@ -254,7 +254,7 @@ static void clear_friendship(bool force, bool disable)
 	/* The timer handler returns without any actions if this fails. */
 	(void)k_work_cancel_delayable(&lpn->timer);
 
-	if (IS_ENABLED(CONFIG_BT_MESH_LPN_ESTABLISHMENT) || disable) {
+	if (IS_ENABLED(CONFIG_BT_MESH_LPN_ESTABLISHMENT)) {
 		bt_mesh_scan_disable();
 	}
 
diff --git a/subsys/bluetooth/mesh/pb_gatt_srv.c b/subsys/bluetooth/mesh/pb_gatt_srv.c
index 67ba1c63408..1b48c910932 100644
--- a/subsys/bluetooth/mesh/pb_gatt_srv.c
+++ b/subsys/bluetooth/mesh/pb_gatt_srv.c
@@ -149,8 +149,8 @@ static ssize_t prov_ccc_write(struct bt_conn *conn,
 }
 
 /* Mesh Provisioning Service Declaration */
-static struct _bt_gatt_ccc prov_ccc =
-	BT_GATT_CCC_INITIALIZER(prov_ccc_changed, prov_ccc_write, NULL);
+static struct bt_gatt_ccc_managed_user_data prov_ccc =
+	BT_GATT_CCC_MANAGED_USER_DATA_INIT(prov_ccc_changed, prov_ccc_write, NULL);
 
 static struct bt_gatt_attr prov_attrs[] = {
 	BT_GATT_PRIMARY_SERVICE(BT_UUID_MESH_PROV),
diff --git a/subsys/bluetooth/mesh/proxy_srv.c b/subsys/bluetooth/mesh/proxy_srv.c
index 7894ef8d608..5f40fe0e7d3 100644
--- a/subsys/bluetooth/mesh/proxy_srv.c
+++ b/subsys/bluetooth/mesh/proxy_srv.c
@@ -937,8 +937,8 @@ static ssize_t proxy_ccc_write(struct bt_conn *conn,
 }
 
 /* Mesh Proxy Service Declaration */
-static struct _bt_gatt_ccc proxy_ccc =
-	BT_GATT_CCC_INITIALIZER(proxy_ccc_changed, proxy_ccc_write, NULL);
+static struct bt_gatt_ccc_managed_user_data proxy_ccc =
+	BT_GATT_CCC_MANAGED_USER_DATA_INIT(proxy_ccc_changed, proxy_ccc_write, NULL);
 
 static struct bt_gatt_attr proxy_attrs[] = {
 	BT_GATT_PRIMARY_SERVICE(BT_UUID_MESH_PROXY),
diff --git a/subsys/bluetooth/mesh/shell/Kconfig b/subsys/bluetooth/mesh/shell/Kconfig
index cda22193243..ecd4e731ddb 100644
--- a/subsys/bluetooth/mesh/shell/Kconfig
+++ b/subsys/bluetooth/mesh/shell/Kconfig
@@ -6,6 +6,7 @@
 menuconfig BT_MESH_SHELL
 	bool "Bluetooth Mesh shell"
 	select SHELL
+	select BT_PRIVATE_SHELL
 	help
 	  Activate shell module that provides Bluetooth Mesh commands to
 	  the console.
diff --git a/subsys/bluetooth/mesh/shell/blob.c b/subsys/bluetooth/mesh/shell/blob.c
index a6888da4270..afce5aa50fd 100644
--- a/subsys/bluetooth/mesh/shell/blob.c
+++ b/subsys/bluetooth/mesh/shell/blob.c
@@ -11,10 +11,9 @@
 #include <zephyr/bluetooth/mesh.h>
 #include <zephyr/bluetooth/mesh/shell.h>
 
+#include "common/bt_shell_private.h"
 #include "utils.h"
 
-extern const struct shell *bt_mesh_shell_ctx_shell;
-
 /***************************************************************************************************
  * Implementation of models' instances
  **************************************************************************************************/
@@ -85,8 +84,7 @@ static void blob_cli_lost_target(struct bt_mesh_blob_cli *cli,
 				 struct bt_mesh_blob_target *target,
 				 enum bt_mesh_blob_status reason)
 {
-	shell_print(bt_mesh_shell_ctx_shell, "Mesh Blob: Lost target 0x%04x (reason: %u)",
-		    target->addr, reason);
+	bt_shell_print("Mesh Blob: Lost target 0x%04x (reason: %u)", target->addr, reason);
 }
 
 static void blob_cli_caps(struct bt_mesh_blob_cli *cli,
@@ -100,30 +98,29 @@ static void blob_cli_caps(struct bt_mesh_blob_cli *cli,
 	};
 
 	if (!caps) {
-		shell_print(bt_mesh_shell_ctx_shell,
-			    "None of the targets can be used for BLOB transfer");
+		bt_shell_print("None of the targets can be used for BLOB transfer");
 		return;
 	}
 
-	shell_print(bt_mesh_shell_ctx_shell, "Mesh BLOB: capabilities:");
-	shell_print(bt_mesh_shell_ctx_shell, "\tMax BLOB size: %u bytes", caps->max_size);
-	shell_print(bt_mesh_shell_ctx_shell, "\tBlock size: %u-%u (%u-%u bytes)",
-		    caps->min_block_size_log, caps->max_block_size_log,
-		    1 << caps->min_block_size_log,
-		    1 << caps->max_block_size_log);
-	shell_print(bt_mesh_shell_ctx_shell, "\tMax chunks: %u", caps->max_chunks);
-	shell_print(bt_mesh_shell_ctx_shell, "\tChunk size: %u", caps->max_chunk_size);
-	shell_print(bt_mesh_shell_ctx_shell, "\tMTU size: %u", caps->mtu_size);
-	shell_print(bt_mesh_shell_ctx_shell, "\tModes: %s", modes[caps->modes]);
+	bt_shell_print("Mesh BLOB: capabilities:");
+	bt_shell_print("\tMax BLOB size: %u bytes", caps->max_size);
+	bt_shell_print("\tBlock size: %u-%u (%u-%u bytes)",
+		       caps->min_block_size_log, caps->max_block_size_log,
+		       1 << caps->min_block_size_log,
+		       1 << caps->max_block_size_log);
+	bt_shell_print("\tMax chunks: %u", caps->max_chunks);
+	bt_shell_print("\tChunk size: %u", caps->max_chunk_size);
+	bt_shell_print("\tMTU size: %u", caps->mtu_size);
+	bt_shell_print("\tModes: %s", modes[caps->modes]);
 }
 
 static void blob_cli_end(struct bt_mesh_blob_cli *cli,
 			 const struct bt_mesh_blob_xfer *xfer, bool success)
 {
 	if (success) {
-		shell_print(bt_mesh_shell_ctx_shell, "Mesh BLOB transfer complete.");
+		bt_shell_print("Mesh BLOB transfer complete.");
 	} else {
-		shell_print(bt_mesh_shell_ctx_shell, "Mesh BLOB transfer failed.");
+		bt_shell_print("Mesh BLOB transfer failed.");
 	}
 }
 
@@ -142,7 +139,7 @@ static uint8_t get_progress(const struct bt_mesh_blob_xfer_info *info)
 		blocks_not_rxed += info->missing_blocks[i % 8] & (1 << (i % 8));
 	}
 
-	return  (total_blocks - blocks_not_rxed) / total_blocks;
+	return (total_blocks - blocks_not_rxed) / total_blocks;
 }
 
 static void xfer_progress(struct bt_mesh_blob_cli *cli,
@@ -151,16 +148,15 @@ static void xfer_progress(struct bt_mesh_blob_cli *cli,
 {
 	uint8_t progress = get_progress(info);
 
-	shell_print(bt_mesh_shell_ctx_shell,
-		    "BLOB transfer progress received from target 0x%04x:\n"
-		    "\tphase: %d\n"
-		    "\tprogress: %u%%",
-		    target->addr, info->phase, progress);
+	bt_shell_print("BLOB transfer progress received from target 0x%04x:\n"
+		       "\tphase: %d\n"
+		       "\tprogress: %u%%",
+		       target->addr, info->phase, progress);
 }
 
 static void xfer_progress_complete(struct bt_mesh_blob_cli *cli)
 {
-	shell_print(bt_mesh_shell_ctx_shell, "Determine BLOB transfer progress procedure complete");
+	bt_shell_print("Determine BLOB transfer progress procedure complete");
 }
 
 static const struct bt_mesh_blob_cli_cb blob_cli_handlers = {
@@ -185,7 +181,7 @@ static int blob_srv_start(struct bt_mesh_blob_srv *srv,
 			  struct bt_mesh_msg_ctx *ctx,
 			  struct bt_mesh_blob_xfer *xfer)
 {
-	shell_print(bt_mesh_shell_ctx_shell, "BLOB start");
+	bt_shell_print("BLOB start");
 	blob_time = k_uptime_get();
 	return 0;
 }
@@ -196,11 +192,11 @@ static void blob_srv_end(struct bt_mesh_blob_srv *srv, uint64_t id,
 	if (success) {
 		int64_t duration = k_uptime_delta(&blob_time);
 
-		shell_print(bt_mesh_shell_ctx_shell, "BLOB completed in %u.%03u s",
-			(uint32_t)(duration / MSEC_PER_SEC),
-			(uint32_t)(duration % MSEC_PER_SEC));
+		bt_shell_print("BLOB completed in %u.%03u s",
+			       (uint32_t)(duration / MSEC_PER_SEC),
+			       (uint32_t)(duration % MSEC_PER_SEC));
 	} else {
-		shell_print(bt_mesh_shell_ctx_shell, "BLOB cancelled");
+		bt_shell_print("BLOB cancelled");
 	}
 }
 
diff --git a/subsys/bluetooth/mesh/shell/cfg.c b/subsys/bluetooth/mesh/shell/cfg.c
index 016a67ff2be..c6292d679e0 100644
--- a/subsys/bluetooth/mesh/shell/cfg.c
+++ b/subsys/bluetooth/mesh/shell/cfg.c
@@ -1561,7 +1561,7 @@ static int mod_pub_set(const struct shell *sh, uint16_t addr, bool is_va, uint16
 		return -EINVAL;
 	}
 
-	pub.period = (steps << 2) + res_step;
+	pub.period = steps + (res_step << 6);
 	count = shell_strtoul(argv[6], 0, &err);
 	if (count > 7) {
 		shell_print(sh, "Invalid retransmit count");
diff --git a/subsys/bluetooth/mesh/shell/dfu.c b/subsys/bluetooth/mesh/shell/dfu.c
index 6b7df4a8bd4..4ff050f3e59 100644
--- a/subsys/bluetooth/mesh/shell/dfu.c
+++ b/subsys/bluetooth/mesh/shell/dfu.c
@@ -16,6 +16,7 @@
 #include <zephyr/dfu/mcuboot.h>
 #include <zephyr/storage/flash_map.h>
 
+#include "common/bt_shell_private.h"
 #include "utils.h"
 #include "blob.h"
 #include "../dfu_slot.h"
@@ -24,30 +25,28 @@
  * Implementation of models' instances
  **************************************************************************************************/
 
-extern const struct shell *bt_mesh_shell_ctx_shell;
-
 #if defined(CONFIG_BT_MESH_SHELL_DFU_CLI)
 
 static void dfu_cli_ended(struct bt_mesh_dfu_cli *cli,
 			  enum bt_mesh_dfu_status reason)
 {
-	shell_print(bt_mesh_shell_ctx_shell, "DFU ended: %u", reason);
+	bt_shell_print("DFU ended: %u", reason);
 }
 
 static void dfu_cli_applied(struct bt_mesh_dfu_cli *cli)
 {
-	shell_print(bt_mesh_shell_ctx_shell, "DFU applied.");
+	bt_shell_print("DFU applied.");
 }
 
 static void dfu_cli_lost_target(struct bt_mesh_dfu_cli *cli,
 				struct bt_mesh_dfu_target *target)
 {
-	shell_print(bt_mesh_shell_ctx_shell, "DFU target lost: 0x%04x", target->blob.addr);
+	bt_shell_print("DFU target lost: 0x%04x", target->blob.addr);
 }
 
 static void dfu_cli_confirmed(struct bt_mesh_dfu_cli *cli)
 {
-	shell_print(bt_mesh_shell_ctx_shell, "DFU confirmed");
+	bt_shell_print("DFU confirmed");
 }
 
 const struct bt_mesh_dfu_cli_cb dfu_cli_cb = {
@@ -86,7 +85,7 @@ static int dfu_start(struct bt_mesh_dfu_srv *srv,
 		     struct net_buf_simple *metadata,
 		     const struct bt_mesh_blob_io **io)
 {
-	shell_print(bt_mesh_shell_ctx_shell, "DFU setup");
+	bt_shell_print("DFU setup");
 
 	*io = bt_mesh_shell_blob_io;
 
@@ -96,7 +95,7 @@ static int dfu_start(struct bt_mesh_dfu_srv *srv,
 static void dfu_end(struct bt_mesh_dfu_srv *srv, const struct bt_mesh_dfu_img *img, bool success)
 {
 	if (!success) {
-		shell_print(bt_mesh_shell_ctx_shell, "DFU failed");
+		bt_shell_print("DFU failed");
 		return;
 	}
 
@@ -115,7 +114,7 @@ static int dfu_apply(struct bt_mesh_dfu_srv *srv,
 		return -EINVAL;
 	}
 
-	shell_print(bt_mesh_shell_ctx_shell, "Applying DFU transfer...");
+	bt_shell_print("Applying DFU transfer...");
 
 	return 0;
 }
@@ -620,10 +619,10 @@ static enum bt_mesh_dfu_iter dfu_img_cb(struct bt_mesh_dfu_cli *cli,
 	len = bin2hex(img->fwid, img->fwid_len, fwid, sizeof(fwid));
 	fwid[len] = '\0';
 
-	shell_print(bt_mesh_shell_ctx_shell, "Image %u:", idx);
-	shell_print(bt_mesh_shell_ctx_shell, "\tFWID: %s", fwid);
+	bt_shell_print("Image %u:", idx);
+	bt_shell_print("\tFWID: %s", fwid);
 	if (img->uri) {
-		shell_print(bt_mesh_shell_ctx_shell, "\tURI:  %s", img->uri);
+		bt_shell_print("\tURI:  %s", img->uri);
 	}
 
 	return BT_MESH_DFU_ITER_CONTINUE;
diff --git a/subsys/bluetooth/mesh/shell/large_comp_data.c b/subsys/bluetooth/mesh/shell/large_comp_data.c
index 750f7b318fd..d95f60927b3 100644
--- a/subsys/bluetooth/mesh/shell/large_comp_data.c
+++ b/subsys/bluetooth/mesh/shell/large_comp_data.c
@@ -9,22 +9,19 @@
 #include <zephyr/bluetooth/mesh.h>
 #include <zephyr/bluetooth/mesh/shell.h>
 
+#include "common/bt_shell_private.h"
 #include "utils.h"
 
-extern const struct shell *bt_mesh_shell_ctx_shell;
-
 static void status_print(int err, char *msg, uint16_t addr, struct bt_mesh_large_comp_data_rsp *rsp)
 {
 	if (err) {
-		shell_error(bt_mesh_shell_ctx_shell,
-			    "Failed to send %s Get message (err %d)", msg, err);
+		bt_shell_error("Failed to send %s Get message (err %d)", msg, err);
 		return;
 	}
 
-	shell_print(bt_mesh_shell_ctx_shell,
-		    "%s [0x%04x]: page: %u offset: %u total size: %u", msg, addr, rsp->page,
-		    rsp->offset, rsp->total_size);
-	shell_hexdump(bt_mesh_shell_ctx_shell, rsp->data->data, rsp->data->len);
+	bt_shell_print("%s [0x%04x]: page: %u offset: %u total size: %u", msg, addr, rsp->page,
+		       rsp->offset, rsp->total_size);
+	bt_shell_hexdump(rsp->data->data, rsp->data->len);
 }
 
 static int cmd_large_comp_data_get(const struct shell *sh, size_t argc, char *argv[])
diff --git a/subsys/bluetooth/mesh/shell/rpr.c b/subsys/bluetooth/mesh/shell/rpr.c
index 870fc7c5d37..bd6285ff0fa 100644
--- a/subsys/bluetooth/mesh/shell/rpr.c
+++ b/subsys/bluetooth/mesh/shell/rpr.c
@@ -17,8 +17,6 @@ static const struct bt_mesh_model *mod;
  * Implementation of the model's instance
  **************************************************************************************************/
 
-extern const struct shell *bt_mesh_shell_ctx_shell;
-
 static void rpr_scan_report(struct bt_mesh_rpr_cli *cli,
 			    const struct bt_mesh_rpr_node *srv,
 			    struct bt_mesh_rpr_unprov *unprov,
@@ -28,11 +26,10 @@ static void rpr_scan_report(struct bt_mesh_rpr_cli *cli,
 
 	bin2hex(unprov->uuid, 16, uuid_hex_str, sizeof(uuid_hex_str));
 
-	shell_print(bt_mesh_shell_ctx_shell,
-		    "Server 0x%04x:\n"
-		    "\tuuid:   %s\n"
-		    "\tOOB:    0x%04x",
-		    srv->addr, uuid_hex_str, unprov->oob);
+	bt_shell_print("Server 0x%04x:\n"
+		       "\tuuid:   %s\n"
+		       "\tOOB:    0x%04x",
+		       srv->addr, uuid_hex_str, unprov->oob);
 
 	while (adv_data && adv_data->len > 2) {
 		uint8_t len, type;
@@ -61,15 +58,14 @@ static void rpr_scan_report(struct bt_mesh_rpr_cli *cli,
 		data[len] = '\0';
 
 		if (type == BT_DATA_URI) {
-			shell_print(bt_mesh_shell_ctx_shell, "\tURI:    \"\\x%02x%s\"",
-				    data[0], &data[1]);
+			bt_shell_print("\tURI:    \"\\x%02x%s\"", data[0], &data[1]);
 		} else if (type == BT_DATA_NAME_COMPLETE) {
-			shell_print(bt_mesh_shell_ctx_shell, "\tName:   \"%s\"", data);
+			bt_shell_print("\tName:   \"%s\"", data);
 		} else {
 			char string[64 + 1];
 
 			bin2hex(data, len, string, sizeof(string));
-			shell_print(bt_mesh_shell_ctx_shell, "\t0x%02x:  %s", type, string);
+			bt_shell_print("\t0x%02x:  %s", type, string);
 		}
 	}
 }
diff --git a/subsys/bluetooth/mesh/shell/shell.c b/subsys/bluetooth/mesh/shell/shell.c
index 511f50a78f9..5475cc5d49b 100644
--- a/subsys/bluetooth/mesh/shell/shell.c
+++ b/subsys/bluetooth/mesh/shell/shell.c
@@ -25,6 +25,7 @@
 #include "mesh/foundation.h"
 #include "mesh/settings.h"
 #include "mesh/access.h"
+#include "common/bt_shell_private.h"
 #include "utils.h"
 #include "dfu.h"
 #include "blob.h"
@@ -33,19 +34,10 @@
 #define COMPANY_ID_LF 0x05F1
 #define COMPANY_ID_NORDIC_SEMI 0x05F9
 
-const struct shell *bt_mesh_shell_ctx_shell;
-
 struct bt_mesh_shell_target bt_mesh_shell_target_ctx = {
 	.dst = BT_MESH_ADDR_UNASSIGNED,
 };
 
-#define shell_print_ctx(_ft, ...)                                                            \
-		do {                                                                         \
-			if (bt_mesh_shell_ctx_shell != NULL) {                               \
-				shell_print(bt_mesh_shell_ctx_shell, _ft, ##__VA_ARGS__);    \
-			}                                                                    \
-		} while (0)
-
 /* Default net, app & dev key values, unless otherwise specified */
 const uint8_t bt_mesh_shell_default_key[16] = {
 	0x01, 0x23, 0x45, 0x67, 0x89, 0xab, 0xcd, 0xef,
@@ -71,7 +63,7 @@ static void get_faults(uint8_t *faults, uint8_t faults_size, uint8_t *dst, uint8
 static int fault_get_cur(const struct bt_mesh_model *model, uint8_t *test_id,
 			 uint16_t *company_id, uint8_t *faults, uint8_t *fault_count)
 {
-	shell_print_ctx("Sending current faults");
+	bt_shell_print("Sending current faults");
 
 	*test_id = 0x00;
 	*company_id = BT_COMP_ID_LF;
@@ -85,12 +77,11 @@ static int fault_get_reg(const struct bt_mesh_model *model, uint16_t cid,
 			 uint8_t *test_id, uint8_t *faults, uint8_t *fault_count)
 {
 	if (cid != CONFIG_BT_COMPANY_ID) {
-		shell_print_ctx("Faults requested for unknown Company ID"
-				" 0x%04x", cid);
+		bt_shell_print("Faults requested for unknown Company ID 0x%04x", cid);
 		return -EINVAL;
 	}
 
-	shell_print_ctx("Sending registered faults");
+	bt_shell_print("Sending registered faults");
 
 	*test_id = 0x00;
 
@@ -126,12 +117,12 @@ static int fault_test(const struct bt_mesh_model *model, uint8_t test_id,
 
 static void attention_on(const struct bt_mesh_model *model)
 {
-	shell_print_ctx("Attention On");
+	bt_shell_print("Attention On");
 }
 
 static void attention_off(const struct bt_mesh_model *model)
 {
-	shell_print_ctx("Attention Off");
+	bt_shell_print("Attention Off");
 }
 
 static const struct bt_mesh_health_srv_cb health_srv_cb = {
@@ -168,16 +159,16 @@ static void show_faults(uint8_t test_id, uint16_t cid, uint8_t *faults, size_t f
 	size_t i;
 
 	if (!fault_count) {
-		shell_print_ctx("Health Test ID 0x%02x Company ID "
-				"0x%04x: no faults", test_id, cid);
+		bt_shell_print("Health Test ID 0x%02x Company ID 0x%04x: no faults",
+			       test_id, cid);
 		return;
 	}
 
-	shell_print_ctx("Health Test ID 0x%02x Company ID 0x%04x Fault "
-			"Count %zu:", test_id, cid, fault_count);
+	bt_shell_print("Health Test ID 0x%02x Company ID 0x%04x Fault Count %zu:",
+		       test_id, cid, fault_count);
 
 	for (i = 0; i < fault_count; i++) {
-		shell_print_ctx("\t0x%02x", faults[i]);
+		bt_shell_print("\t0x%02x", faults[i]);
 	}
 }
 
@@ -185,7 +176,7 @@ static void health_current_status(struct bt_mesh_health_cli *cli, uint16_t addr,
 				  uint8_t test_id, uint16_t cid, uint8_t *faults,
 				  size_t fault_count)
 {
-	shell_print_ctx("Health Current Status from 0x%04x", addr);
+	bt_shell_print("Health Current Status from 0x%04x", addr);
 	show_faults(test_id, cid, faults, fault_count);
 }
 
@@ -193,20 +184,20 @@ static void health_fault_status(struct bt_mesh_health_cli *cli, uint16_t addr,
 				uint8_t test_id, uint16_t cid, uint8_t *faults,
 				size_t fault_count)
 {
-	shell_print_ctx("Health Fault Status from 0x%04x", addr);
+	bt_shell_print("Health Fault Status from 0x%04x", addr);
 	show_faults(test_id, cid, faults, fault_count);
 }
 
 static void health_attention_status(struct bt_mesh_health_cli *cli,
 				    uint16_t addr, uint8_t attention)
 {
-	shell_print_ctx("Health Attention Status from 0x%04x: %u", addr, attention);
+	bt_shell_print("Health Attention Status from 0x%04x: %u", addr, attention);
 }
 
 static void health_period_status(struct bt_mesh_health_cli *cli, uint16_t addr,
 				 uint8_t period)
 {
-	shell_print_ctx("Health Fast Period Divisor Status from 0x%04x: %u", addr, period);
+	bt_shell_print("Health Fast Period Divisor Status from 0x%04x: %u", addr, period);
 }
 
 struct bt_mesh_health_cli bt_mesh_shell_health_cli = {
@@ -219,8 +210,6 @@ struct bt_mesh_health_cli bt_mesh_shell_health_cli = {
 
 static int cmd_init(const struct shell *sh, size_t argc, char *argv[])
 {
-
-	bt_mesh_shell_ctx_shell = sh;
 	shell_print(sh, "Mesh shell initialized");
 
 #if defined(CONFIG_BT_MESH_SHELL_DFU_CLI) || defined(CONFIG_BT_MESH_SHELL_DFU_SRV)
@@ -242,7 +231,7 @@ static int cmd_reset(const struct shell *sh, size_t argc, char *argv[])
 {
 #if defined(CONFIG_BT_MESH_CDB)
 	bt_mesh_cdb_clear();
-# endif
+#endif
 	bt_mesh_reset();
 	shell_print(sh, "Local node reset complete");
 
@@ -311,15 +300,14 @@ static int cmd_poll(const struct shell *sh, size_t argc, char *argv[])
 static void lpn_established(uint16_t net_idx, uint16_t friend_addr,
 					uint8_t queue_size, uint8_t recv_win)
 {
-	shell_print_ctx("Friendship (as LPN) established to "
-			"Friend 0x%04x Queue Size %d Receive Window %d",
-			friend_addr, queue_size, recv_win);
+	bt_shell_print("Friendship (as LPN) established to "
+		       "Friend 0x%04x Queue Size %d Receive Window %d",
+		       friend_addr, queue_size, recv_win);
 }
 
 static void lpn_terminated(uint16_t net_idx, uint16_t friend_addr)
 {
-	shell_print_ctx("Friendship (as LPN) lost with Friend "
-			"0x%04x", friend_addr);
+	bt_shell_print("Friendship (as LPN) lost with Friend 0x%04x", friend_addr);
 }
 
 BT_MESH_LPN_CB_DEFINE(lpn_cb) = {
@@ -461,17 +449,15 @@ static uint8_t dev_uuid[16] = { 0xdd, 0xdd };
 static void prov_complete(uint16_t net_idx, uint16_t addr)
 {
 
-	shell_print_ctx("Local node provisioned, net_idx 0x%04x address "
-			"0x%04x", net_idx, addr);
+	bt_shell_print("Local node provisioned, net_idx 0x%04x address 0x%04x", net_idx, addr);
 
-	bt_mesh_shell_target_ctx.net_idx = net_idx,
+	bt_mesh_shell_target_ctx.net_idx = net_idx;
 	bt_mesh_shell_target_ctx.dst = addr;
 }
 
 static void reprovisioned(uint16_t addr)
 {
-	shell_print(bt_mesh_shell_ctx_shell, "Local node re-provisioned, new address 0x%04x",
-		    addr);
+	bt_shell_print("Local node re-provisioned, new address 0x%04x", addr);
 
 	if (bt_mesh_shell_target_ctx.dst == bt_mesh_primary_addr()) {
 		bt_mesh_shell_target_ctx.dst = addr;
@@ -481,10 +467,10 @@ static void reprovisioned(uint16_t addr)
 static void prov_node_added(uint16_t net_idx, uint8_t uuid[16], uint16_t addr,
 			    uint8_t num_elem)
 {
-	shell_print_ctx("Node provisioned, net_idx 0x%04x address "
-			"0x%04x elements %d", net_idx, addr, num_elem);
+	bt_shell_print("Node provisioned, net_idx 0x%04x address 0x%04x elements %d",
+		       net_idx, addr, num_elem);
 
-	bt_mesh_shell_target_ctx.net_idx = net_idx,
+	bt_mesh_shell_target_ctx.net_idx = net_idx;
 	bt_mesh_shell_target_ctx.dst = addr;
 }
 
@@ -506,22 +492,22 @@ static const char *const input_meth_string[] = {
 
 static void capabilities(const struct bt_mesh_dev_capabilities *cap)
 {
-	shell_print_ctx("Provisionee capabilities:");
-	shell_print_ctx("\tStatic OOB is %ssupported", cap->oob_type & 1 ? "" : "not ");
+	bt_shell_print("Provisionee capabilities:");
+	bt_shell_print("\tStatic OOB is %ssupported", cap->oob_type & 1 ? "" : "not ");
 
-	shell_print_ctx("\tAvailable output actions (%d bytes max):%s", cap->output_size,
-			cap->output_actions ? "" : "\n\t\tNone");
+	bt_shell_print("\tAvailable output actions (%d bytes max):%s", cap->output_size,
+		       cap->output_actions ? "" : "\n\t\tNone");
 	for (int i = 0; i < ARRAY_SIZE(output_meth_string); i++) {
 		if (cap->output_actions & BIT(i)) {
-			shell_print_ctx("\t\t%s", output_meth_string[i]);
+			bt_shell_print("\t\t%s", output_meth_string[i]);
 		}
 	}
 
-	shell_print_ctx("\tAvailable input actions (%d bytes max):%s", cap->input_size,
-			cap->input_actions ? "" : "\n\t\tNone");
+	bt_shell_print("\tAvailable input actions (%d bytes max):%s", cap->input_size,
+		       cap->input_actions ? "" : "\n\t\tNone");
 	for (int i = 0; i < ARRAY_SIZE(input_meth_string); i++) {
 		if (cap->input_actions & BIT(i)) {
-			shell_print_ctx("\t\t%s", input_meth_string[i]);
+			bt_shell_print("\t\t%s", input_meth_string[i]);
 		}
 	}
 }
@@ -529,36 +515,32 @@ static void capabilities(const struct bt_mesh_dev_capabilities *cap)
 
 static void prov_input_complete(void)
 {
-	shell_print_ctx("Input complete");
+	bt_shell_print("Input complete");
 }
 
 static void prov_reset(void)
 {
-	shell_print_ctx("The local node has been reset and needs "
-			"reprovisioning");
+	bt_shell_print("The local node has been reset and needs reprovisioning");
 }
 
 static int output_number(bt_mesh_output_action_t action, uint32_t number)
 {
 	switch (action) {
 	case BT_MESH_BLINK:
-		shell_print_ctx("OOB blink Number: %u", number);
+		bt_shell_print("OOB blink Number: %u", number);
 		break;
 	case BT_MESH_BEEP:
-		shell_print_ctx("OOB beep Number: %u", number);
+		bt_shell_print("OOB beep Number: %u", number);
 		break;
 	case BT_MESH_VIBRATE:
-		shell_print_ctx("OOB vibrate Number: %u", number);
+		bt_shell_print("OOB vibrate Number: %u", number);
 		break;
 	case BT_MESH_DISPLAY_NUMBER:
-		shell_print_ctx("OOB display Number: %u", number);
+		bt_shell_print("OOB display Number: %u", number);
 		break;
 	default:
-		if (bt_mesh_shell_ctx_shell != NULL) {
-			shell_error(bt_mesh_shell_ctx_shell,
-				    "Unknown Output action %u (number %u) requested!",
-				    action, number);
-		}
+		bt_shell_error("Unknown Output action %u (number %u) requested!",
+			       action, number);
 		return -EINVAL;
 	}
 
@@ -567,7 +549,7 @@ static int output_number(bt_mesh_output_action_t action, uint32_t number)
 
 static int output_string(const char *str)
 {
-	shell_print_ctx("OOB String: %s", str);
+	bt_shell_print("OOB String: %s", str);
 	return 0;
 }
 
@@ -576,22 +558,19 @@ static int input(bt_mesh_input_action_t act, uint8_t size)
 
 	switch (act) {
 	case BT_MESH_ENTER_NUMBER:
-		shell_print_ctx("Enter a number (max %u digits) with: Input-num <num>", size);
+		bt_shell_print("Enter a number (max %u digits) with: Input-num <num>", size);
 		break;
 	case BT_MESH_ENTER_STRING:
-		shell_print_ctx("Enter a string (max %u chars) with: Input-str <str>", size);
+		bt_shell_print("Enter a string (max %u chars) with: Input-str <str>", size);
 		break;
 	case BT_MESH_TWIST:
-		shell_print_ctx("\"Twist\" a number (max %u digits) with: Input-num <num>", size);
+		bt_shell_print("\"Twist\" a number (max %u digits) with: Input-num <num>", size);
 		break;
 	case BT_MESH_PUSH:
-		shell_print_ctx("\"Push\" a number (max %u digits) with: Input-num <num>", size);
+		bt_shell_print("\"Push\" a number (max %u digits) with: Input-num <num>", size);
 		break;
 	default:
-		if (bt_mesh_shell_ctx_shell != NULL) {
-			shell_error(bt_mesh_shell_ctx_shell,
-				    "Unknown Input action %u (size %u) requested!", act, size);
-		}
+		bt_shell_error("Unknown Input action %u (size %u) requested!", act, size);
 		return -EINVAL;
 	}
 
@@ -600,12 +579,12 @@ static int input(bt_mesh_input_action_t act, uint8_t size)
 
 static void link_open(bt_mesh_prov_bearer_t bearer)
 {
-	shell_print_ctx("Provisioning link opened on %s", bearer2str(bearer));
+	bt_shell_print("Provisioning link opened on %s", bearer2str(bearer));
 }
 
 static void link_close(bt_mesh_prov_bearer_t bearer)
 {
-	shell_print_ctx("Provisioning link closed on %s", bearer2str(bearer));
+	bt_shell_print("Provisioning link closed on %s", bearer2str(bearer));
 }
 
 static uint8_t static_val[32];
@@ -670,7 +649,7 @@ static int cmd_uuid(const struct shell *sh, size_t argc, char *argv[])
 
 		bin2hex(dev_uuid, 16, uuid_hex_str, sizeof(uuid_hex_str));
 
-		shell_print_ctx("Device UUID: %s", uuid_hex_str);
+		bt_shell_print("Device UUID: %s", uuid_hex_str);
 		return 0;
 	}
 
@@ -695,9 +674,9 @@ static void print_unprovisioned_beacon(uint8_t uuid[16],
 
 	bin2hex(uuid, 16, uuid_hex_str, sizeof(uuid_hex_str));
 
-	shell_print_ctx("PB-ADV UUID %s, OOB Info 0x%04x, URI Hash 0x%x",
-			uuid_hex_str, oob_info,
-			(uri_hash == NULL ? 0 : *uri_hash));
+	bt_shell_print("PB-ADV UUID %s, OOB Info 0x%04x, URI Hash 0x%x",
+		       uuid_hex_str, oob_info,
+		       (uri_hash == NULL ? 0 : *uri_hash));
 }
 
 #if defined(CONFIG_BT_MESH_PB_GATT_CLIENT)
@@ -708,7 +687,7 @@ static void pb_gatt_unprovisioned(uint8_t uuid[16],
 
 	bin2hex(uuid, 16, uuid_hex_str, sizeof(uuid_hex_str));
 
-	shell_print_ctx("PB-GATT UUID %s, OOB Info 0x%04x", uuid_hex_str, oob_info);
+	bt_shell_print("PB-GATT UUID %s, OOB Info 0x%04x", uuid_hex_str, oob_info);
 }
 #endif
 
diff --git a/subsys/bluetooth/mesh/va.h b/subsys/bluetooth/mesh/va.h
index 7620a157b2e..32b9d956191 100644
--- a/subsys/bluetooth/mesh/va.h
+++ b/subsys/bluetooth/mesh/va.h
@@ -4,6 +4,9 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stdint.h>
+#include <stdbool.h>
+
 /** Virtual address entry. */
 struct bt_mesh_va {
 	uint16_t ref:15,
diff --git a/subsys/bluetooth/services/cts.c b/subsys/bluetooth/services/cts.c
index d5744bc5a24..dcc0ce090bb 100644
--- a/subsys/bluetooth/services/cts.c
+++ b/subsys/bluetooth/services/cts.c
@@ -170,8 +170,8 @@ BT_GATT_SERVICE_DEFINE(cts_svc, BT_GATT_PRIMARY_SERVICE(BT_UUID_CTS),
 
 int bt_cts_init(const struct bt_cts_cb *cb)
 {
-	__ASSERT(cb == NULL, "Current Time service need valid `struct bt_cts_cb` callback");
-	__ASSERT(cb->fill_current_cts_time == NULL,
+	__ASSERT(cb != NULL, "Current Time service need valid `struct bt_cts_cb` callback");
+	__ASSERT(cb->fill_current_cts_time != NULL,
 		 "`fill_current_cts_time` callback api is required for functioning of CTS");
 	if (!cb || !cb->fill_current_cts_time) {
 		return -EINVAL;
diff --git a/subsys/bluetooth/services/dis.c b/subsys/bluetooth/services/dis.c
index c9f429560c3..f3fdccf100e 100644
--- a/subsys/bluetooth/services/dis.c
+++ b/subsys/bluetooth/services/dis.c
@@ -179,7 +179,7 @@ static ssize_t read_system_id(struct bt_conn *conn, const struct bt_gatt_attr *a
 #endif
 
 #if CONFIG_BT_DIS_UDI
-#define DIS_STR_SIZE(x)           ((x[0]) != '\0' ? strlen(x) + sizeof('\0') : 0)
+#define DIS_STR_SIZE(x)           ((x[0]) != '\0' ? strlen(x) + 1 : 0)
 #define BT_DIS_UDI_FLAG_LABEL     (!!BT_DIS_UDI_LABEL_STR_REF[0])
 #define BT_DIS_UDI_FLAG_DI        (!!BT_DIS_UDI_DI_STR_REF[0])
 #define BT_DIS_UDI_FLAG_ISSUER    (!!BT_DIS_UDI_ISSUER_STR_REF[0])
@@ -196,7 +196,7 @@ static void read_udi_subval(const char *str, uint16_t val_len, char *buf, uint16
 			    uint16_t *index, uint16_t len, uint16_t offset)
 {
 	/* String should not be with included null-terminator if empty */
-	if (val_len == sizeof('\0')) {
+	if (val_len == sizeof("")) {
 		return;
 	}
 
diff --git a/subsys/bluetooth/services/ias/shell/ias.c b/subsys/bluetooth/services/ias/shell/ias.c
index be2d709db38..8da9818e474 100644
--- a/subsys/bluetooth/services/ias/shell/ias.c
+++ b/subsys/bluetooth/services/ias/shell/ias.c
@@ -18,22 +18,21 @@
 #include <zephyr/bluetooth/services/ias.h>
 
 #include "host/shell/bt.h"
-
-extern const struct shell *ctx_shell;
+#include "common/bt_shell_private.h"
 
 static void alert_stop(void)
 {
-	shell_print(ctx_shell, "Alert stopped\n");
+	bt_shell_print("Alert stopped\n");
 }
 
 static void alert_start(void)
 {
-	shell_print(ctx_shell, "Mild alert started\n");
+	bt_shell_print("Mild alert started\n");
 }
 
 static void alert_high_start(void)
 {
-	shell_print(ctx_shell, "High alert started\n");
+	bt_shell_print("High alert started\n");
 }
 
 BT_IAS_CB_DEFINE(ias_callbacks) = {
diff --git a/subsys/bluetooth/services/ias/shell/ias_client.c b/subsys/bluetooth/services/ias/shell/ias_client.c
index 0fa9f024601..1b5c51e07d2 100644
--- a/subsys/bluetooth/services/ias/shell/ias_client.c
+++ b/subsys/bluetooth/services/ias/shell/ias_client.c
@@ -16,15 +16,14 @@
 #include <zephyr/bluetooth/services/ias.h>
 
 #include "host/shell/bt.h"
-
-extern const struct shell *ctx_shell;
+#include "common/bt_shell_private.h"
 
 static void ias_discover_cb(struct bt_conn *conn, int err)
 {
 	if (err != 0) {
-		shell_error(ctx_shell, "Failed to discover IAS err: %d\n", err);
+		bt_shell_error("Failed to discover IAS err: %d\n", err);
 	} else {
-		shell_print(ctx_shell, "IAS discover success\n");
+		bt_shell_print("IAS discover success\n");
 	}
 }
 
@@ -36,10 +35,6 @@ static int cmd_ias_client_init(const struct shell *sh, size_t argc, char **argv)
 {
 	int err;
 
-	if (!ctx_shell) {
-		ctx_shell = sh;
-	}
-
 	err = bt_ias_client_cb_register(&ias_client_callbacks);
 	if (err != 0) {
 		shell_print(sh, "IAS client init failed");
diff --git a/subsys/bluetooth/services/ots/ots_internal.h b/subsys/bluetooth/services/ots/ots_internal.h
index af1cafb0251..77ca60d9db5 100644
--- a/subsys/bluetooth/services/ots/ots_internal.h
+++ b/subsys/bluetooth/services/ots/ots_internal.h
@@ -120,7 +120,7 @@ struct bt_gatt_ots_object {
 struct bt_gatt_ots_indicate {
 	struct bt_gatt_indicate_params params;
 	struct bt_gatt_attr attr;
-	struct _bt_gatt_ccc ccc;
+	struct bt_gatt_ccc_managed_user_data ccc;
 	bool is_enabled;
 	struct k_work work;
 	uint8_t res[OACP_OLCP_RES_MAX_SIZE];
diff --git a/subsys/bluetooth/services/ots/ots_oacp.c b/subsys/bluetooth/services/ots/ots_oacp.c
index 3d6b3cf560a..bf88b27882f 100644
--- a/subsys/bluetooth/services/ots/ots_oacp.c
+++ b/subsys/bluetooth/services/ots/ots_oacp.c
@@ -728,7 +728,7 @@ void bt_gatt_ots_oacp_cfg_changed(const struct bt_gatt_attr *attr,
 				      uint16_t value)
 {
 	struct bt_gatt_ots_indicate *oacp_ind =
-	    CONTAINER_OF((struct _bt_gatt_ccc *) attr->user_data,
+	    CONTAINER_OF((struct bt_gatt_ccc_managed_user_data *) attr->user_data,
 			 struct bt_gatt_ots_indicate, ccc);
 
 	LOG_DBG("Object Action Control Point CCCD value: 0x%04X", value);
diff --git a/subsys/bluetooth/services/ots/ots_olcp.c b/subsys/bluetooth/services/ots/ots_olcp.c
index 7a7efb56435..4673b567e02 100644
--- a/subsys/bluetooth/services/ots/ots_olcp.c
+++ b/subsys/bluetooth/services/ots/ots_olcp.c
@@ -311,7 +311,7 @@ void bt_gatt_ots_olcp_cfg_changed(const struct bt_gatt_attr *attr,
 				      uint16_t value)
 {
 	struct bt_gatt_ots_indicate *olcp_ind =
-	    CONTAINER_OF((struct _bt_gatt_ccc *) attr->user_data,
+	    CONTAINER_OF((struct bt_gatt_ccc_managed_user_data *) attr->user_data,
 			 struct bt_gatt_ots_indicate, ccc);
 
 	LOG_DBG("Object List Control Point CCCD value: 0x%04X", value);
diff --git a/subsys/dap/CMakeLists.txt b/subsys/dap/CMakeLists.txt
index c021d240711..6ece4319c35 100644
--- a/subsys/dap/CMakeLists.txt
+++ b/subsys/dap/CMakeLists.txt
@@ -5,3 +5,5 @@ zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR})
 
 zephyr_library()
 zephyr_library_sources(cmsis_dap.c)
+
+zephyr_library_sources_ifdef(CONFIG_DAP_BACKEND_USB dap_backend_usb.c)
diff --git a/subsys/dap/Kconfig b/subsys/dap/Kconfig
index cfa50bf80ea..a9417c55c7a 100644
--- a/subsys/dap/Kconfig
+++ b/subsys/dap/Kconfig
@@ -17,13 +17,6 @@ config CMSIS_DAP_PACKET_COUNT
 	help
 	  Maximum packet buffers for request and response data.
 
-config CMSIS_DAP_PACKET_SIZE
-	int "Maximum packet size for request and response data."
-	default 64
-	range 64 512
-	help
-	  Maximum packet size for request and response data.
-
 config CMSIS_DAP_PROBE_VENDOR
 	string "Probe vendor"
 	default "Zephyr"
@@ -48,6 +41,12 @@ config CMSIS_DAP_DEVICE_NAME
 	string "Target device name"
 	default ""
 
+config DAP_BACKEND_USB
+	bool "USB backend"
+	depends on USB_DEVICE_STACK_NEXT
+	help
+	  DAP USB backend using bulk endpoints.
+
 module = DAP
 module-str = dap
 source "subsys/logging/Kconfig.template.log_config"
diff --git a/subsys/dap/cmsis_dap.c b/subsys/dap/cmsis_dap.c
index 4148346e15f..cd68f634a56 100644
--- a/subsys/dap/cmsis_dap.c
+++ b/subsys/dap/cmsis_dap.c
@@ -47,23 +47,25 @@ struct dap_context {
 
 static struct dap_context dap_ctx[1];
 
+#define CMSIS_DAP_PACKET_MIN_SIZE 64
+
 BUILD_ASSERT(sizeof(CONFIG_CMSIS_DAP_PROBE_VENDOR) <=
-	     MIN(CONFIG_CMSIS_DAP_PACKET_SIZE - 2, UINT8_MAX - 2),
+	     MIN(CMSIS_DAP_PACKET_MIN_SIZE - 2, UINT8_MAX - 2),
 	     "PROBE_VENDOR string is too long.");
 BUILD_ASSERT(sizeof(CONFIG_CMSIS_DAP_PROBE_NAME) <=
-	     MIN(CONFIG_CMSIS_DAP_PACKET_SIZE - 2, UINT8_MAX - 2),
+	     MIN(CMSIS_DAP_PACKET_MIN_SIZE - 2, UINT8_MAX - 2),
 	     "PROBE_NAME string is too long.");
 BUILD_ASSERT(sizeof(CONFIG_CMSIS_DAP_BOARD_VENDOR) <=
-	     MIN(CONFIG_CMSIS_DAP_PACKET_SIZE - 2, UINT8_MAX - 2),
+	     MIN(CMSIS_DAP_PACKET_MIN_SIZE - 2, UINT8_MAX - 2),
 	     "BOARD_VENDOR string is too long.");
 BUILD_ASSERT(sizeof(CONFIG_CMSIS_DAP_BOARD_NAME) <=
-	     MIN(CONFIG_CMSIS_DAP_PACKET_SIZE - 2, UINT8_MAX - 2),
+	     MIN(CMSIS_DAP_PACKET_MIN_SIZE - 2, UINT8_MAX - 2),
 	     "BOARD_NAME string is too long.");
 BUILD_ASSERT(sizeof(CONFIG_CMSIS_DAP_DEVICE_VENDOR) <=
-	     MIN(CONFIG_CMSIS_DAP_PACKET_SIZE - 2, UINT8_MAX - 2),
+	     MIN(CMSIS_DAP_PACKET_MIN_SIZE - 2, UINT8_MAX - 2),
 	     "DEVICE_VENDOR string is too long.");
 BUILD_ASSERT(sizeof(CONFIG_CMSIS_DAP_DEVICE_NAME) <=
-	     MIN(CONFIG_CMSIS_DAP_PACKET_SIZE - 2, UINT8_MAX - 2),
+	     MIN(CMSIS_DAP_PACKET_MIN_SIZE - 2, UINT8_MAX - 2),
 	     "DEVICE_NAME string is too long.");
 
 /* Get DAP Information */
@@ -1037,6 +1039,12 @@ uint32_t dap_execute_cmd(const uint8_t *request,
 	return dap_process_cmd(&dap_ctx[0], request, response);
 }
 
+void dap_update_pkt_size(const uint16_t pkt_size)
+{
+	dap_ctx[0].pkt_size = pkt_size;
+	LOG_INF("New packet size %u", dap_ctx[0].pkt_size);
+}
+
 int dap_setup(const struct device *const dev)
 {
 	dap_ctx[0].swdp_dev = (void *)dev;
@@ -1047,7 +1055,7 @@ int dap_setup(const struct device *const dev)
 	}
 
 	/* Default settings */
-	dap_ctx[0].pkt_size = CONFIG_CMSIS_DAP_PACKET_SIZE;
+	dap_ctx[0].pkt_size = CMSIS_DAP_PACKET_MIN_SIZE;
 	dap_ctx[0].debug_port = 0U;
 	dap_ctx[0].transfer.idle_cycles = 0U;
 	dap_ctx[0].transfer.retry_count = 100U;
diff --git a/subsys/dap/cmsis_dap.h b/subsys/dap/cmsis_dap.h
index d8869e2160a..94743582875 100644
--- a/subsys/dap/cmsis_dap.h
+++ b/subsys/dap/cmsis_dap.h
@@ -132,5 +132,6 @@
 /* Keep it internal until an other interface has been implemented. */
 int dap_setup(const struct device *const dev);
 uint32_t dap_execute_cmd(const uint8_t *request, uint8_t *response);
+void dap_update_pkt_size(const uint16_t pkt_size);
 
 #endif	/* ZEPHYR_INCLUDE_CMSIS_DAP_H_ */
diff --git a/subsys/dap/dap_backend_usb.c b/subsys/dap/dap_backend_usb.c
new file mode 100644
index 00000000000..5986e3a1e2c
--- /dev/null
+++ b/subsys/dap/dap_backend_usb.c
@@ -0,0 +1,305 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/usb/usbd.h>
+#include <zephyr/drivers/usb/udc.h>
+#include <zephyr/sys/byteorder.h>
+
+#include "cmsis_dap.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(dap_usb, CONFIG_DAP_LOG_LEVEL);
+
+/*
+ * This file implements CMSIS DAP USB backend function using bulk endpoints.
+ */
+
+static uint8_t response_buf[512];
+
+NET_BUF_POOL_FIXED_DEFINE(dap_func_pool,
+			  1, 0, sizeof(struct udc_buf_info), NULL);
+
+UDC_STATIC_BUF_DEFINE(dap_func_buf, 512);
+
+struct dap_func_desc {
+	struct usb_if_descriptor if0;
+	struct usb_ep_descriptor if0_out_ep;
+	struct usb_ep_descriptor if0_in_ep;
+	struct usb_ep_descriptor if0_hs_out_ep;
+	struct usb_ep_descriptor if0_hs_in_ep;
+	struct usb_desc_header nil_desc;
+};
+
+#define SAMPLE_FUNCTION_ENABLED		0
+
+struct dap_func_data {
+	struct dap_func_desc *const desc;
+	const struct usb_desc_header **const fs_desc;
+	const struct usb_desc_header **const hs_desc;
+	struct usbd_desc_node *const iface_str_desc_nd;
+	atomic_t state;
+};
+
+static uint8_t dap_func_get_bulk_out(struct usbd_class_data *const c_data)
+{
+	struct dap_func_data *data = usbd_class_get_private(c_data);
+	struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data);
+	struct dap_func_desc *desc = data->desc;
+
+	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+		return desc->if0_hs_out_ep.bEndpointAddress;
+	}
+
+	return desc->if0_out_ep.bEndpointAddress;
+}
+
+static uint8_t dap_func_get_bulk_in(struct usbd_class_data *const c_data)
+{
+	struct dap_func_data *data = usbd_class_get_private(c_data);
+	struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data);
+	struct dap_func_desc *desc = data->desc;
+
+	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+		return desc->if0_hs_in_ep.bEndpointAddress;
+	}
+
+	return desc->if0_in_ep.bEndpointAddress;
+}
+
+static int dap_func_request_handler(struct usbd_class_data *c_data,
+				  struct net_buf *buf, int err)
+{
+	struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data);
+	struct dap_func_data *data = usbd_class_get_private(c_data);
+	struct udc_buf_info *bi = NULL;
+
+	bi = (struct udc_buf_info *)net_buf_user_data(buf);
+	LOG_DBG("Transfer finished %p -> ep 0x%02x, len %u, err %d",
+		(void *)c_data, bi->ep, buf->len, err);
+
+	if (atomic_test_bit(&data->state, SAMPLE_FUNCTION_ENABLED) && err == 0) {
+		uint8_t ep = bi->ep;
+		size_t len;
+
+		memset(bi, 0, sizeof(struct udc_buf_info));
+		if (ep == dap_func_get_bulk_in(c_data)) {
+			bi->ep = dap_func_get_bulk_out(c_data);
+			net_buf_reset(buf);
+		} else {
+			bi->ep = dap_func_get_bulk_in(c_data);
+
+			len = dap_execute_cmd(buf->data, response_buf);
+			net_buf_reset(buf);
+			LOG_DBG("response length %u, starting with [0x%02X, 0x%02X]",
+				len, response_buf[0], response_buf[1]);
+			net_buf_add_mem(buf, response_buf, MIN(len, net_buf_tailroom(buf)));
+		}
+
+		if (usbd_ep_enqueue(c_data, buf)) {
+			LOG_ERR("Failed to enqueue buffer");
+			usbd_ep_buf_free(uds_ctx, buf);
+		}
+	} else {
+		LOG_ERR("Function is disabled or transfer failed");
+		usbd_ep_buf_free(uds_ctx, buf);
+	}
+
+	return 0;
+}
+
+static void *dap_func_get_desc(struct usbd_class_data *const c_data,
+			     const enum usbd_speed speed)
+{
+	struct dap_func_data *data = usbd_class_get_private(c_data);
+
+	if (speed == USBD_SPEED_HS) {
+		return data->hs_desc;
+	}
+
+	return data->fs_desc;
+}
+
+struct net_buf *dap_func_buf_alloc(struct usbd_class_data *const c_data,
+				const uint8_t ep)
+{
+	struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data);
+	struct net_buf *buf = NULL;
+	struct udc_buf_info *bi;
+	size_t size;
+
+	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+		size = 512U;
+	} else {
+		size = 64U;
+	}
+
+	buf = net_buf_alloc_with_data(&dap_func_pool, dap_func_buf, size, K_NO_WAIT);
+	net_buf_reset(buf);
+	if (!buf) {
+		return NULL;
+	}
+
+	bi = udc_get_buf_info(buf);
+	memset(bi, 0, sizeof(struct udc_buf_info));
+	bi->ep = ep;
+
+	return buf;
+}
+
+static void dap_func_enable(struct usbd_class_data *const c_data)
+{
+	struct dap_func_data *data = usbd_class_get_private(c_data);
+	struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data);
+	struct net_buf *buf;
+
+	LOG_INF("Configuration enabled");
+
+	if (!atomic_test_and_set_bit(&data->state, SAMPLE_FUNCTION_ENABLED)) {
+		if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+			dap_update_pkt_size(512);
+		} else {
+			dap_update_pkt_size(64);
+		}
+
+		buf = dap_func_buf_alloc(c_data, dap_func_get_bulk_out(c_data));
+		if (buf == NULL) {
+			LOG_ERR("Failed to allocate buffer");
+			return;
+		}
+
+		if (usbd_ep_enqueue(c_data, buf)) {
+			LOG_ERR("Failed to enqueue buffer");
+			usbd_ep_buf_free(uds_ctx, buf);
+		}
+	}
+}
+
+static void dap_func_disable(struct usbd_class_data *const c_data)
+{
+	struct dap_func_data *data = usbd_class_get_private(c_data);
+
+	atomic_clear_bit(&data->state, SAMPLE_FUNCTION_ENABLED);
+	LOG_INF("Configuration disabled");
+}
+
+static int dap_func_init(struct usbd_class_data *c_data)
+{
+	struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data);
+	struct dap_func_data *data = usbd_class_get_private(c_data);
+	struct dap_func_desc *desc = data->desc;
+
+	LOG_DBG("Init class instance %p", (void *)c_data);
+
+	if (usbd_add_descriptor(uds_ctx, data->iface_str_desc_nd)) {
+		LOG_ERR("Failed to add interface string descriptor");
+	} else {
+		desc->if0.iInterface = usbd_str_desc_get_idx(data->iface_str_desc_nd);
+	}
+
+	return 0;
+}
+
+struct usbd_class_api dap_func_api = {
+	.request = dap_func_request_handler,
+	.get_desc = dap_func_get_desc,
+	.enable = dap_func_enable,
+	.disable = dap_func_disable,
+	.init = dap_func_init,
+};
+
+#define DAP_FUNC_DESCRIPTOR_DEFINE(n, _)					\
+static struct dap_func_desc dap_func_desc_##n = {				\
+	/* Interface descriptor 0 */						\
+	.if0 = {								\
+		.bLength = sizeof(struct usb_if_descriptor),			\
+		.bDescriptorType = USB_DESC_INTERFACE,				\
+		.bInterfaceNumber = 0,						\
+		.bAlternateSetting = 0,						\
+		.bNumEndpoints = 2,						\
+		.bInterfaceClass = USB_BCC_VENDOR,				\
+		.bInterfaceSubClass = 0,					\
+		.bInterfaceProtocol = 0,					\
+		.iInterface = 0,						\
+	},									\
+										\
+	/* Endpoint OUT */							\
+	.if0_out_ep = {								\
+		.bLength = sizeof(struct usb_ep_descriptor),			\
+		.bDescriptorType = USB_DESC_ENDPOINT,				\
+		.bEndpointAddress = 0x01,					\
+		.bmAttributes = USB_EP_TYPE_BULK,				\
+		.wMaxPacketSize = sys_cpu_to_le16(64U),				\
+		.bInterval = 0x00,						\
+	},									\
+										\
+	/* Endpoint IN */							\
+	.if0_in_ep = {								\
+		.bLength = sizeof(struct usb_ep_descriptor),			\
+		.bDescriptorType = USB_DESC_ENDPOINT,				\
+		.bEndpointAddress = 0x81,					\
+		.bmAttributes = USB_EP_TYPE_BULK,				\
+		.wMaxPacketSize = sys_cpu_to_le16(64U),				\
+		.bInterval = 0x00,						\
+	},									\
+										\
+	/* High-speed Endpoint OUT */						\
+	.if0_hs_out_ep = {							\
+		.bLength = sizeof(struct usb_ep_descriptor),			\
+		.bDescriptorType = USB_DESC_ENDPOINT,				\
+		.bEndpointAddress = 0x01,					\
+		.bmAttributes = USB_EP_TYPE_BULK,				\
+		.wMaxPacketSize = sys_cpu_to_le16(512),				\
+		.bInterval = 0x00,						\
+	},									\
+										\
+	/* High-speed Endpoint IN */						\
+	.if0_hs_in_ep = {							\
+		.bLength = sizeof(struct usb_ep_descriptor),			\
+		.bDescriptorType = USB_DESC_ENDPOINT,				\
+		.bEndpointAddress = 0x81,					\
+		.bmAttributes = USB_EP_TYPE_BULK,				\
+		.wMaxPacketSize = sys_cpu_to_le16(512),				\
+		.bInterval = 0x00,						\
+	},									\
+										\
+	/* Termination descriptor */						\
+	.nil_desc = {								\
+		.bLength = 0,							\
+		.bDescriptorType = 0,						\
+	},									\
+};										\
+										\
+const static struct usb_desc_header *dap_func_fs_desc_##n[] = {			\
+	(struct usb_desc_header *) &dap_func_desc_##n.if0,			\
+	(struct usb_desc_header *) &dap_func_desc_##n.if0_out_ep,		\
+	(struct usb_desc_header *) &dap_func_desc_##n.if0_in_ep,		\
+	(struct usb_desc_header *) &dap_func_desc_##n.nil_desc,			\
+};										\
+										\
+const static struct usb_desc_header *dap_func_hs_desc_##n[] = {			\
+	(struct usb_desc_header *) &dap_func_desc_##n.if0,			\
+	(struct usb_desc_header *) &dap_func_desc_##n.if0_hs_out_ep,		\
+	(struct usb_desc_header *) &dap_func_desc_##n.if0_hs_in_ep,		\
+	(struct usb_desc_header *) &dap_func_desc_##n.nil_desc,			\
+};
+
+
+#define DAP_FUNC_FUNCTION_DATA_DEFINE(n, _)					\
+	USBD_DESC_STRING_DEFINE(iface_str_desc_nd_##n,				\
+				"CMSIS-DAP v2",					\
+				USBD_DUT_STRING_INTERFACE);			\
+										\
+	static struct dap_func_data dap_func_data_##n = {			\
+		.desc = &dap_func_desc_##n,					\
+		.fs_desc = dap_func_fs_desc_##n,				\
+		.hs_desc = dap_func_hs_desc_##n,				\
+		.iface_str_desc_nd = &iface_str_desc_nd_##n,			\
+	};									\
+										\
+	USBD_DEFINE_CLASS(dap_func_##n, &dap_func_api, &dap_func_data_##n, NULL);
+
+LISTIFY(1, DAP_FUNC_DESCRIPTOR_DEFINE, ())
+LISTIFY(1, DAP_FUNC_FUNCTION_DATA_DEFINE, ())
diff --git a/subsys/debug/CMakeLists.txt b/subsys/debug/CMakeLists.txt
index 183305f8430..2e99f5a648e 100644
--- a/subsys/debug/CMakeLists.txt
+++ b/subsys/debug/CMakeLists.txt
@@ -10,9 +10,9 @@ zephyr_sources_ifdef(
   asan_hacks.c
   )
 
-zephyr_sources_ifdef(
+add_subdirectory_ifdef(
   CONFIG_THREAD_ANALYZER
-  thread_analyzer.c
+  thread_analyzer
   )
 
 add_subdirectory_ifdef(
@@ -39,3 +39,8 @@ zephyr_sources_ifdef(
   CONFIG_CS_TRACE_DEFMT
   coresight/cs_trace_defmt.c
 )
+
+zephyr_sources_ifdef(
+  CONFIG_CPU_LOAD
+  cpu_load.c
+  )
diff --git a/subsys/debug/Kconfig b/subsys/debug/Kconfig
index eaa88056414..6ee215c16f5 100644
--- a/subsys/debug/Kconfig
+++ b/subsys/debug/Kconfig
@@ -6,105 +6,7 @@
 
 menu "System Monitoring Options"
 
-menuconfig THREAD_ANALYZER
-	bool "Thread analyzer"
-	depends on !ARCH_POSIX
-	select INIT_STACKS
-	select THREAD_MONITOR
-	select THREAD_STACK_INFO
-	select THREAD_RUNTIME_STATS
-	help
-	  Enable thread analyzer functionality and all the required modules.
-	  This module may be used to debug thread configuration issues, e.g.
-	  stack size configuration to find stack overflow or to find stacks
-	  which may be optimized.
-
-if THREAD_ANALYZER
-module = THREAD_ANALYZER
-module-str = thread analyzer
-source "subsys/logging/Kconfig.template.log_config"
-
-choice
-	prompt "Thread analysis print mode"
-	default THREAD_ANALYZER_USE_PRINTK
-
-config THREAD_ANALYZER_USE_LOG
-	bool "Use logger output"
-	select LOG
-	help
-	  Use logger output to print thread information.
-
-config THREAD_ANALYZER_USE_PRINTK
-	bool "Use printk function"
-	help
-	  Use kernel printk function to print thread information.
-
-endchoice
-
-config THREAD_ANALYZER_ISR_STACK_USAGE
-	bool "Analyze interrupt stacks usage"
-	default y
-
-config THREAD_ANALYZER_PRIV_STACK_USAGE
-	bool "Analyze privileged stacks usage"
-	depends on USERSPACE
-	depends on ARCH_HAS_THREAD_PRIV_STACK_SPACE_GET
-	help
-	  Print privileged stack usage for user threads.
-
-config THREAD_ANALYZER_RUN_UNLOCKED
-	bool "Run analysis with interrupts unlocked"
-	default y
-	help
-	  The thread analysis takes quite a long time.
-	  Every thread it finds is analyzed word by word to find any that
-	  does not match the magic number.
-	  Normally while thread are analyzed the k_thread_foreach function
-	  is used.
-	  While this is a safe run from the thread list perspective it may lock
-	  the interrupts for a long time - long enough to disconnect when
-	  Bluetooth communication is used.
-	  Setting this flag will force thread analyzer to use
-	  the k_thread_foreach_unlocked function.
-	  This will allow the interrupts to be processed while the thread is
-	  analyzed.
-	  For the limitation of such configuration see the k_thread_foreach
-	  documentation.
-
-config THREAD_ANALYZER_AUTO
-	bool "Run periodic thread analysis in a thread"
-	help
-	  Run the thread analyzer automatically, without the need to add
-	  any code to the application.
-	  Thread analysis would be called periodically.
-
-if THREAD_ANALYZER_AUTO
-
-config THREAD_ANALYZER_AUTO_SEPARATE_CORES
-	bool "Run thread analyzer separately on each core"
-	default y if KERNEL_COHERENCE
-	depends on SCHED_CPU_MASK
-	help
-	  Run the thread analyzer auto thread on each core and report
-	  cores separately. This feature is needed for platforms running
-	  on cache-incoherent architectures.
-
-config THREAD_ANALYZER_AUTO_INTERVAL
-	int "Thread analysis interval"
-	default 60
-	range 5 3600
-	help
-	  The time in seconds to call thread analyzer periodic printing function.
-
-config THREAD_ANALYZER_AUTO_STACK_SIZE
-	int "Stack size for the periodic thread analysis thread"
-	default 2048 if THREAD_ANALYZER_USE_LOG && LOG_MODE_IMMEDIATE && NO_OPTIMIZATIONS
-	default 1024
-
-endif # THREAD_ANALYZER_AUTO
-
-endif # THREAD_ANALYZER
-
+source "subsys/debug/thread_analyzer/Kconfig"
 
 endmenu
 
@@ -431,3 +333,31 @@ config CS_TRACE_DEFMT
 	help
 	  Module is decoding data which is formatted using Coresight
 	  Trace Formatter, e.g. when data is put into ETR (Embedded Trace Router).
+
+config CPU_LOAD
+	select TRACING
+	depends on CPU_CORTEX_M || RISCV
+	depends on !SMP
+	bool "CPU load measurement"
+
+# Workaround for not being able to have commas in macro arguments
+DT_CHOSEN_Z_CPU_LOAD_COUNTER := zephyr,cpu-load-counter
+
+config CPU_LOAD_USE_COUNTER
+	bool "Use counter"
+	depends on $(dt_chosen_enabled,$(DT_CHOSEN_Z_CPU_LOAD_COUNTER))
+	default y
+	select COUNTER
+	help
+	  Use counter for tracking CPU idle time.
+
+config CPU_LOAD_LOG_PERIODICALLY
+	int "Report period (in milliseconds)"
+	depends on LOG
+	default 0
+	help
+	  Specifies how often CPU load shall be logged. 0 means that there is no logging.
+
+module = CPU_LOAD
+module-str = cpu_load
+source "subsys/logging/Kconfig.template.log_config"
diff --git a/subsys/debug/coredump/CMakeLists.txt b/subsys/debug/coredump/CMakeLists.txt
index b1219f91dff..8e5b0769da8 100644
--- a/subsys/debug/coredump/CMakeLists.txt
+++ b/subsys/debug/coredump/CMakeLists.txt
@@ -28,6 +28,16 @@ zephyr_library_sources_ifdef(
   coredump_backend_intel_adsp_mem_window.c
   )
 
+zephyr_library_sources_ifdef(
+  CONFIG_DEBUG_COREDUMP_SHELL
+  coredump_shell.c
+  )
+
+zephyr_library_sources_ifdef(
+  CONFIG_DEBUG_COREDUMP_BACKEND_IN_MEMORY
+  coredump_backend_in_memory.c
+  )
+
   # @Intent: Set XTENSA_TOOLCHAIN_VARIANT macro required for Xtensa coredump
 if(CONFIG_XTENSA)
   if(${ZEPHYR_TOOLCHAIN_VARIANT} STREQUAL "zephyr")
diff --git a/subsys/debug/coredump/Kconfig b/subsys/debug/coredump/Kconfig
index ad46d7d80b8..fdab0361820 100644
--- a/subsys/debug/coredump/Kconfig
+++ b/subsys/debug/coredump/Kconfig
@@ -28,6 +28,17 @@ config DEBUG_COREDUMP_BACKEND_FLASH_PARTITION
 	  Core dump is saved to a flash partition with DTS alias
 	  "coredump-partition".
 
+config DEBUG_COREDUMP_BACKEND_IN_MEMORY
+	bool "Use memory to store the coredump"
+	help
+	  Core dump (or part of it) is saved in a dedicated area in
+	  memory. Such memory is protected at boot time so it could be
+	  read after a warm reboot. This is obviously NOT a valid solution
+	  when a full hardware reboot cycle occurs (on/off etc..) where
+	  the RAM will most likely loose its data.
+	  See DEBUG_COREDUMP_BACKEND_IN_MEMORY_SIZE on how much space to
+	  reserve.
+
 config DEBUG_COREDUMP_BACKEND_INTEL_ADSP_MEM_WINDOW
 	bool "Use memory window for coredump on Intel ADSP"
 	depends on DT_HAS_INTEL_ADSP_MEM_WINDOW_ENABLED
@@ -118,4 +129,19 @@ config DEBUG_COREDUMP_DUMP_THREAD_PRIV_STACK
 	  Say n to conserve space on coredump backend or if you will never
 	  need to look into the privilege stacks.
 
+config DEBUG_COREDUMP_BACKEND_IN_MEMORY_SIZE
+	int "In-memory coredump size"
+	default 128
+	depends on DEBUG_COREDUMP_BACKEND_IN_MEMORY
+	help
+	  Sets the dedicated memory area where a coredump can be stored
+	  and accessed after a warm reboot. It has to be able to hold at
+	  least the info dumped by arch_coredump_info_dump().
+	  Extra memory region will silently be ignored if there isn't
+	  enough space.
+
+module = DEBUG_COREDUMP
+module-str = coredump
+source "subsys/logging/Kconfig.template.log_config"
+
 endif # DEBUG_COREDUMP
diff --git a/subsys/debug/coredump/coredump_backend_flash_partition.c b/subsys/debug/coredump/coredump_backend_flash_partition.c
index ad929d3d742..46b93d3ca2b 100644
--- a/subsys/debug/coredump/coredump_backend_flash_partition.c
+++ b/subsys/debug/coredump/coredump_backend_flash_partition.c
@@ -16,7 +16,7 @@
 #include "coredump_internal.h"
 
 #include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(coredump, CONFIG_KERNEL_LOG_LEVEL);
+LOG_MODULE_REGISTER(coredump, CONFIG_DEBUG_COREDUMP_LOG_LEVEL);
 
 /**
  * @file
@@ -630,306 +630,4 @@ struct coredump_backend_api coredump_backend_flash_partition = {
 	.cmd = coredump_flash_backend_cmd,
 };
 
-#ifdef CONFIG_DEBUG_COREDUMP_SHELL
-#include <zephyr/shell/shell.h>
-
-/* Length of buffer of printable size */
-#define PRINT_BUF_SZ		64
-
-/* Length of buffer of printable size plus null character */
-#define PRINT_BUF_SZ_RAW	(PRINT_BUF_SZ + 1)
-
-/* Print buffer */
-static char print_buf[PRINT_BUF_SZ_RAW];
-static off_t print_buf_ptr;
-
-/**
- * @brief Shell command to get backend error.
- *
- * @param sh shell instance
- * @param argc (not used)
- * @param argv (not used)
- * @return 0
- */
-static int cmd_coredump_error_get(const struct shell *sh,
-				  size_t argc, char **argv)
-{
-	ARG_UNUSED(argc);
-	ARG_UNUSED(argv);
-
-	if (backend_ctx.error == 0) {
-		shell_print(sh, "No error.");
-	} else {
-		shell_print(sh, "Error: %d", backend_ctx.error);
-	}
-
-	return 0;
-}
-
-/**
- * @brief Shell command to clear backend error.
- *
- * @param sh shell instance
- * @param argc (not used)
- * @param argv (not used)
- * @return 0
- */
-static int cmd_coredump_error_clear(const struct shell *sh,
-				    size_t argc, char **argv)
-{
-	backend_ctx.error = 0;
-
-	shell_print(sh, "Error cleared.");
-
-	return 0;
-}
-
-/**
- * @brief Shell command to see if there is a stored coredump in flash.
- *
- * @param sh shell instance
- * @param argc (not used)
- * @param argv (not used)
- * @return 0
- */
-static int cmd_coredump_has_stored_dump(const struct shell *sh,
-					size_t argc, char **argv)
-{
-	int ret;
-
-	ARG_UNUSED(argc);
-	ARG_UNUSED(argv);
-
-	ret = coredump_flash_backend_query(COREDUMP_QUERY_HAS_STORED_DUMP,
-					   NULL);
-
-	if (ret == 1) {
-		shell_print(sh, "Stored coredump found.");
-	} else if (ret == 0) {
-		shell_print(sh, "Stored coredump NOT found.");
-	} else {
-		shell_print(sh, "Failed to perform query: %d", ret);
-	}
-
-	return 0;
-}
-
-/**
- * @brief Shell command to verify if the stored coredump is valid.
- *
- * @param sh shell instance
- * @param argc (not used)
- * @param argv (not used)
- * @return 0
- */
-static int cmd_coredump_verify_stored_dump(const struct shell *sh,
-					   size_t argc, char **argv)
-{
-	int ret;
-
-	ARG_UNUSED(argc);
-	ARG_UNUSED(argv);
-
-	ret = coredump_flash_backend_cmd(COREDUMP_CMD_VERIFY_STORED_DUMP,
-					 NULL);
-
-	if (ret == 1) {
-		shell_print(sh, "Stored coredump verified.");
-	} else if (ret == 0) {
-		shell_print(sh, "Stored coredump verification failed "
-				   "or there is no stored coredump.");
-	} else {
-		shell_print(sh, "Failed to perform verify command: %d",
-			    ret);
-	}
-
-	return 0;
-}
-
-/**
- * @brief Flush the print buffer to shell.
- *
- * This prints what is in the print buffer to the shell.
- *
- * @param sh shell instance.
- */
-static void flush_print_buf(const struct shell *sh)
-{
-	shell_print(sh, "%s%s", COREDUMP_PREFIX_STR, print_buf);
-	print_buf_ptr = 0;
-	(void)memset(print_buf, 0, sizeof(print_buf));
-}
-
-/**
- * @brief Callback to print stored coredump to shell
- *
- * This converts the binary data in @p buf to hexadecimal digits
- * which can be printed to the shell.
- *
- * @param arg shell instance
- * @param buf binary data buffer
- * @param len number of bytes in buffer to be printed
- * @return 0 if no issues; -EINVAL if error converting data
- */
-static int cb_print_stored_dump(void *arg, uint8_t *buf, size_t len)
-{
-	int ret = 0;
-	size_t i = 0;
-	size_t remaining = len;
-	const struct shell *sh = (const struct shell *)arg;
-
-	if (len == 0) {
-		/* Flush print buffer */
-		flush_print_buf(sh);
-
-		goto out;
-	}
-
-	/* Do checksum for process_stored_dump() */
-	cb_calc_buf_checksum(arg, buf, len);
-
-	while (remaining > 0) {
-		if (hex2char(buf[i] >> 4, &print_buf[print_buf_ptr]) < 0) {
-			ret = -EINVAL;
-			break;
-		}
-		print_buf_ptr++;
-
-		if (hex2char(buf[i] & 0xf, &print_buf[print_buf_ptr]) < 0) {
-			ret = -EINVAL;
-			break;
-		}
-		print_buf_ptr++;
-
-		remaining--;
-		i++;
-
-		if (print_buf_ptr == PRINT_BUF_SZ) {
-			flush_print_buf(sh);
-		}
-	}
-
-out:
-	return ret;
-}
-
-/**
- * @brief Shell command to print stored coredump data to shell
- *
- * @param sh shell instance
- * @param argc (not used)
- * @param argv (not used)
- * @return 0
- */
-static int cmd_coredump_print_stored_dump(const struct shell *sh,
-					  size_t argc, char **argv)
-{
-	int ret;
-
-	ARG_UNUSED(argc);
-	ARG_UNUSED(argv);
-
-	/* Verify first to see if stored dump is valid */
-	ret = coredump_flash_backend_cmd(COREDUMP_CMD_VERIFY_STORED_DUMP,
-					 NULL);
-
-	if (ret == 0) {
-		shell_print(sh, "Stored coredump verification failed "
-				   "or there is no stored coredump.");
-		goto out;
-	} else if (ret != 1) {
-		shell_print(sh, "Failed to perform verify command: %d",
-			    ret);
-		goto out;
-	}
-
-	/* If valid, start printing to shell */
-	print_buf_ptr = 0;
-	(void)memset(print_buf, 0, sizeof(print_buf));
-
-	shell_print(sh, "%s%s", COREDUMP_PREFIX_STR, COREDUMP_BEGIN_STR);
-
-	ret = process_stored_dump(cb_print_stored_dump, (void *)sh);
-	if (print_buf_ptr != 0) {
-		shell_print(sh, "%s%s", COREDUMP_PREFIX_STR, print_buf);
-	}
-
-	if (backend_ctx.error != 0) {
-		shell_print(sh, "%s%s", COREDUMP_PREFIX_STR,
-			    COREDUMP_ERROR_STR);
-	}
-
-	shell_print(sh, "%s%s", COREDUMP_PREFIX_STR, COREDUMP_END_STR);
-
-	if (ret == 1) {
-		shell_print(sh, "Stored coredump printed.");
-	} else if (ret == 0) {
-		shell_print(sh, "Stored coredump verification failed "
-				   "or there is no stored coredump.");
-	} else {
-		shell_print(sh, "Failed to print: %d", ret);
-	}
-
-out:
-	return 0;
-}
-
-/**
- * @brief Shell command to erase stored coredump.
- *
- * @param sh shell instance
- * @param argc (not used)
- * @param argv (not used)
- * @return 0
- */
-static int cmd_coredump_erase_stored_dump(const struct shell *sh,
-					  size_t argc, char **argv)
-{
-	int ret;
-
-	ARG_UNUSED(argc);
-	ARG_UNUSED(argv);
-
-	ret = coredump_flash_backend_cmd(COREDUMP_CMD_ERASE_STORED_DUMP,
-					 NULL);
-
-	if (ret == 0) {
-		shell_print(sh, "Stored coredump erased.");
-	} else {
-		shell_print(sh, "Failed to perform erase command: %d", ret);
-	}
-
-	return 0;
-}
-
-SHELL_STATIC_SUBCMD_SET_CREATE(sub_coredump_error,
-	SHELL_CMD(clear, NULL, "Clear Coredump error",
-		  cmd_coredump_error_clear),
-	SHELL_CMD(get, NULL, "Get Coredump error", cmd_coredump_error_get),
-	SHELL_SUBCMD_SET_END /* Array terminated. */
-);
-
-SHELL_STATIC_SUBCMD_SET_CREATE(sub_coredump,
-	SHELL_CMD(error, &sub_coredump_error,
-		  "Get/clear backend error.", NULL),
-	SHELL_CMD(erase, NULL,
-		  "Erase stored coredump",
-		  cmd_coredump_erase_stored_dump),
-	SHELL_CMD(find, NULL,
-		  "Query if there is a stored coredump",
-		  cmd_coredump_has_stored_dump),
-	SHELL_CMD(print, NULL,
-		  "Print stored coredump to shell",
-		  cmd_coredump_print_stored_dump),
-	SHELL_CMD(verify, NULL,
-		  "Verify stored coredump",
-		  cmd_coredump_verify_stored_dump),
-	SHELL_SUBCMD_SET_END /* Array terminated. */
-);
-
-SHELL_CMD_REGISTER(coredump, &sub_coredump,
-		   "Coredump commands (flash partition backend)", NULL);
-
-#endif /* CONFIG_DEBUG_COREDUMP_SHELL */
-
 #endif /* FIXED_PARTITION_EXISTS(coredump_partition) */
diff --git a/subsys/debug/coredump/coredump_backend_in_memory.c b/subsys/debug/coredump/coredump_backend_in_memory.c
new file mode 100644
index 00000000000..84a8d0d2a1f
--- /dev/null
+++ b/subsys/debug/coredump/coredump_backend_in_memory.c
@@ -0,0 +1,194 @@
+/*
+ * Copyright (c) 2025 Bang & Olufsen.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <string.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/logging/log_ctrl.h>
+#include <zephyr/debug/coredump.h>
+
+#include "coredump_internal.h"
+
+LOG_MODULE_REGISTER(coredump, CONFIG_DEBUG_COREDUMP_LOG_LEVEL);
+
+#define IN_MEMORY_CANARY_SIZE 4
+#define IN_MEMORY_COREDUMP_SIZE_RECORD sizeof(size_t)
+
+/**
+ * In-memory coredump space is arranged that way:
+ * CANARY+ Recorded coredump size + Coredump + Left space (if any) + CANARY
+ */
+#define IN_MEMORY_SPACE CONFIG_DEBUG_COREDUMP_BACKEND_IN_MEMORY_SIZE + \
+	(IN_MEMORY_CANARY_SIZE * 2) + IN_MEMORY_COREDUMP_SIZE_RECORD
+#define IN_MEMORY_START IN_MEMORY_CANARY_SIZE + IN_MEMORY_COREDUMP_SIZE_RECORD
+#define IN_MEMORY_END IN_MEMORY_SPACE - IN_MEMORY_CANARY_SIZE
+
+static const uint8_t in_memory_canary[IN_MEMORY_CANARY_SIZE] = {
+	0xDE, 0xB0, 0xDE, 0xB0
+};
+
+static uint8_t __noinit_named(_in_memory_coredump)
+	__aligned(4) in_memory_coredump[IN_MEMORY_SPACE];
+
+static size_t *coredump_size =
+	(size_t *)&in_memory_coredump[IN_MEMORY_CANARY_SIZE];
+static uint8_t *cur_ptr;
+
+
+static inline void in_memory_invalidate(void)
+{
+	memset(in_memory_coredump, 0, IN_MEMORY_CANARY_SIZE);
+	memset(&in_memory_coredump[IN_MEMORY_END], 0, IN_MEMORY_CANARY_SIZE);
+	*coredump_size = 0;
+	cur_ptr = NULL;
+}
+static inline void in_memory_erase(void)
+{
+	LOG_DBG("Erasing in-memory coredump\n");
+
+	in_memory_invalidate();
+}
+
+static int in_memory_is_valid(void)
+{
+	if (!memcmp(in_memory_coredump,
+		    in_memory_canary, IN_MEMORY_CANARY_SIZE) &&
+	    !memcmp(&in_memory_coredump[IN_MEMORY_END],
+		    in_memory_canary, IN_MEMORY_CANARY_SIZE)) {
+		return 1;
+	}
+
+	return 0;
+}
+
+static int in_memory_copy_to(struct coredump_cmd_copy_arg *copy_arg)
+{
+	LOG_DBG("Copy to: %p offset: %lu length: %lu",
+		(void *)copy_arg->buffer, copy_arg->offset,
+		(unsigned long)copy_arg->length);
+
+	if (copy_arg->buffer == NULL ||
+	    copy_arg->offset >= IN_MEMORY_END ||
+	    (copy_arg->length + copy_arg->offset) >= IN_MEMORY_END) {
+		return -EINVAL;
+	}
+
+	if (in_memory_is_valid() == 0) {
+		return -EIO;
+	}
+
+	memcpy(copy_arg->buffer,
+	       &in_memory_coredump[IN_MEMORY_START + copy_arg->offset],
+	       copy_arg->length);
+
+	return 0;
+}
+
+static void coredump_in_memory_backend_start(void)
+{
+	in_memory_erase();
+
+	LOG_ERR(COREDUMP_PREFIX_STR "LOCATION %p", (void *)in_memory_coredump);
+
+	memcpy(in_memory_coredump, in_memory_canary, IN_MEMORY_CANARY_SIZE);
+	cur_ptr = &in_memory_coredump[IN_MEMORY_START];
+
+	*coredump_size = 0;
+
+	while (LOG_PROCESS()) {
+		;
+	}
+
+	LOG_PANIC();
+	LOG_ERR(COREDUMP_PREFIX_STR COREDUMP_BEGIN_STR);
+}
+
+static void coredump_in_memory_backend_end(void)
+{
+	memcpy(&in_memory_coredump[IN_MEMORY_END],
+	       in_memory_canary, IN_MEMORY_CANARY_SIZE);
+
+	*coredump_size = cur_ptr - &in_memory_coredump[IN_MEMORY_START];
+
+	LOG_ERR(COREDUMP_PREFIX_STR COREDUMP_END_STR);
+}
+
+static void coredump_in_memory_backend_buffer_output(uint8_t *buf,
+						     size_t buflen)
+{
+	int space;
+
+	LOG_DBG("Output buffer size %lu", (unsigned long)buflen);
+
+	if (cur_ptr == &in_memory_coredump[IN_MEMORY_END]) {
+		/* Once full, we silently ignore the request */
+		return;
+	}
+
+	space = &in_memory_coredump[IN_MEMORY_END] - cur_ptr;
+	if (buflen < space) {
+		space = buflen;
+	}
+
+	memcpy(cur_ptr, buf, space);
+	cur_ptr += space;
+}
+
+static int coredump_in_memory_backend_query(enum coredump_query_id query_id,
+					    void *arg)
+{
+	switch (query_id) {
+	case COREDUMP_QUERY_GET_ERROR:
+		break;
+	case COREDUMP_QUERY_HAS_STORED_DUMP:
+		return in_memory_is_valid();
+	case COREDUMP_QUERY_GET_STORED_DUMP_SIZE:
+		if (in_memory_is_valid() == 1) {
+			return *coredump_size;
+		}
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int coredump_in_memory_backend_cmd(enum coredump_cmd_id cmd_id,
+					  void *arg)
+{
+	switch (cmd_id) {
+	case COREDUMP_CMD_CLEAR_ERROR:
+		break;
+	case COREDUMP_CMD_VERIFY_STORED_DUMP:
+		return in_memory_is_valid();
+	case COREDUMP_CMD_ERASE_STORED_DUMP:
+		in_memory_erase();
+		break;
+	case COREDUMP_CMD_COPY_STORED_DUMP:
+		if (arg == NULL) {
+			return -EINVAL;
+		}
+		return in_memory_copy_to((struct coredump_cmd_copy_arg *)arg);
+	case COREDUMP_CMD_INVALIDATE_STORED_DUMP:
+		in_memory_invalidate();
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+struct coredump_backend_api coredump_backend_in_memory = {
+	.start = coredump_in_memory_backend_start,
+	.end = coredump_in_memory_backend_end,
+	.buffer_output = coredump_in_memory_backend_buffer_output,
+	.query = coredump_in_memory_backend_query,
+	.cmd = coredump_in_memory_backend_cmd,
+};
diff --git a/subsys/debug/coredump/coredump_backend_intel_adsp_mem_window.c b/subsys/debug/coredump/coredump_backend_intel_adsp_mem_window.c
index 06f1e5a8f6a..201a2e8a2a4 100644
--- a/subsys/debug/coredump/coredump_backend_intel_adsp_mem_window.c
+++ b/subsys/debug/coredump/coredump_backend_intel_adsp_mem_window.c
@@ -14,7 +14,8 @@
 #include <zephyr/logging/log_ctrl.h>
 #include <adsp_memory.h>
 #include <adsp_debug_window.h>
-LOG_MODULE_REGISTER(coredump_error, CONFIG_KERNEL_LOG_LEVEL);
+
+LOG_MODULE_REGISTER(coredump, CONFIG_DEBUG_COREDUMP_LOG_LEVEL);
 
 static int error;
 static uint32_t mem_wptr;
diff --git a/subsys/debug/coredump/coredump_backend_logging.c b/subsys/debug/coredump/coredump_backend_logging.c
index f646d5fe7fa..c64dcfc68be 100644
--- a/subsys/debug/coredump/coredump_backend_logging.c
+++ b/subsys/debug/coredump/coredump_backend_logging.c
@@ -12,7 +12,8 @@
 
 #include <zephyr/logging/log.h>
 #include <zephyr/logging/log_ctrl.h>
-LOG_MODULE_REGISTER(coredump, CONFIG_KERNEL_LOG_LEVEL);
+
+LOG_MODULE_REGISTER(coredump, CONFIG_DEBUG_COREDUMP_LOG_LEVEL);
 
 /* Length of buffer of printable size */
 #define LOG_BUF_SZ		64
@@ -125,50 +126,3 @@ struct coredump_backend_api coredump_backend_logging = {
 	.query = coredump_logging_backend_query,
 	.cmd = coredump_logging_backend_cmd,
 };
-
-
-#ifdef CONFIG_DEBUG_COREDUMP_SHELL
-#include <zephyr/shell/shell.h>
-
-static int cmd_coredump_error_get(const struct shell *sh,
-				  size_t argc, char **argv)
-{
-	ARG_UNUSED(argc);
-	ARG_UNUSED(argv);
-
-	if (error == 0) {
-		shell_print(sh, "No error.");
-	} else {
-		shell_print(sh, "Error: %d", error);
-	}
-
-	return 0;
-}
-
-static int cmd_coredump_error_clear(const struct shell *sh,
-				    size_t argc, char **argv)
-{
-	error = 0;
-
-	shell_print(sh, "Error cleared.");
-
-	return 0;
-}
-
-SHELL_STATIC_SUBCMD_SET_CREATE(sub_coredump_error,
-	SHELL_CMD(get, NULL, "Get Coredump error", cmd_coredump_error_get),
-	SHELL_CMD(clear, NULL, "Clear Coredump error",
-		  cmd_coredump_error_clear),
-	SHELL_SUBCMD_SET_END /* Array terminated. */
-);
-
-SHELL_STATIC_SUBCMD_SET_CREATE(sub_coredump,
-	SHELL_CMD(error, &sub_coredump_error,
-		  "Get/clear backend error.", NULL),
-	SHELL_SUBCMD_SET_END /* Array terminated. */
-);
-
-SHELL_CMD_REGISTER(coredump, &sub_coredump,
-		   "Coredump commands (logging backend)", NULL);
-
-#endif /* CONFIG_DEBUG_COREDUMP_SHELL */
diff --git a/subsys/debug/coredump/coredump_core.c b/subsys/debug/coredump/coredump_core.c
index 8b17c6d26b0..12fa0fa8dfd 100644
--- a/subsys/debug/coredump/coredump_core.c
+++ b/subsys/debug/coredump/coredump_core.c
@@ -24,6 +24,10 @@ static struct coredump_backend_api
 extern struct coredump_backend_api coredump_backend_intel_adsp_mem_window;
 static struct coredump_backend_api
 	*backend_api = &coredump_backend_intel_adsp_mem_window;
+#elif defined(CONFIG_DEBUG_COREDUMP_BACKEND_IN_MEMORY)
+extern struct coredump_backend_api coredump_backend_in_memory;
+static struct coredump_backend_api
+	*backend_api = &coredump_backend_in_memory;
 #elif defined(CONFIG_DEBUG_COREDUMP_BACKEND_OTHER)
 extern struct coredump_backend_api coredump_backend_other;
 static struct coredump_backend_api
diff --git a/subsys/debug/coredump/coredump_shell.c b/subsys/debug/coredump/coredump_shell.c
new file mode 100644
index 00000000000..731162aa27c
--- /dev/null
+++ b/subsys/debug/coredump/coredump_shell.c
@@ -0,0 +1,626 @@
+/*
+ * Copyright (c) 2020 Intel Corporation.
+ * Copyright (c) 2025 Bang & Olufsen A/S, Denmark
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <zephyr/kernel.h>
+#include <zephyr/shell/shell.h>
+
+#include <zephyr/debug/coredump.h>
+
+#if defined(CONFIG_DEBUG_COREDUMP_BACKEND_LOGGING)
+#define COREDUMP_BACKEND_STR "logging"
+#elif defined(CONFIG_DEBUG_COREDUMP_BACKEND_FLASH_PARTITION)
+#define COREDUMP_BACKEND_STR "flash partition"
+#elif defined(CONFIG_DEBUG_COREDUMP_BACKEND_INTEL_ADSP_MEM_WINDOW)
+#define COREDUMP_BACKEND_STR "ADSP memory window"
+#elif defined(CONFIG_DEBUG_COREDUMP_BACKEND_IN_MEMORY)
+#define COREDUMP_BACKEND_STR "In memory - volatile -"
+#elif defined(CONFIG_DEBUG_COREDUMP_BACKEND_OTHER)
+#define COREDUMP_BACKEND_STR "other"
+#else
+#error "Need to select a coredump backend"
+#endif
+
+/* Length of buffer of printable size */
+#define PRINT_BUF_SZ		64
+/* Length of copy buffer */
+#define COPY_BUF_SZ		128
+
+/* Length of buffer of printable size plus null character */
+#define PRINT_BUF_SZ_RAW	(PRINT_BUF_SZ + 1)
+
+/* Print buffer */
+static char print_buf[PRINT_BUF_SZ_RAW];
+static off_t print_buf_ptr;
+
+/**
+ * Since enum coredump_tgt_code is sequential and starting from 0,
+ * let's just have an array
+ */
+static const char * const coredump_target_code2str[] = {
+	"Unknown",
+	"x86",
+	"x86_64",
+	"ARM Cortex-m",
+	"Risc V",
+	"Xtensa",
+	"ARM64"
+};
+
+/**
+ * @brief Shell command to get backend error.
+ *
+ * @param sh shell instance
+ * @param argc (not used)
+ * @param argv (not used)
+ * @return 0
+ */
+static int cmd_coredump_error_get(const struct shell *sh,
+				  size_t argc, char **argv)
+{
+	int ret;
+
+	ARG_UNUSED(argc);
+	ARG_UNUSED(argv);
+
+	ret = coredump_query(COREDUMP_QUERY_GET_ERROR, NULL);
+	if (ret == 0) {
+		shell_print(sh, "No error.");
+	} else if (ret == -ENOTSUP) {
+		shell_print(sh, "Unsupported query from the backend");
+	} else {
+		shell_print(sh, "Error: %d", ret);
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Shell command to clear backend error.
+ *
+ * @param sh shell instance
+ * @param argc (not used)
+ * @param argv (not used)
+ * @return 0
+ */
+static int cmd_coredump_error_clear(const struct shell *sh,
+				    size_t argc, char **argv)
+{
+	int ret;
+
+	ARG_UNUSED(argc);
+	ARG_UNUSED(argv);
+
+	ret = coredump_cmd(COREDUMP_CMD_CLEAR_ERROR, NULL);
+	if (ret == 0) {
+		shell_print(sh, "Error cleared.");
+	} else if (ret == -ENOTSUP) {
+		shell_print(sh, "Unsupported command from the backend");
+	} else {
+		shell_print(sh, "Failed to clear the error: %d", ret);
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Shell command to see if there is a stored coredump in flash.
+ *
+ * @param sh shell instance
+ * @param argc (not used)
+ * @param argv (not used)
+ * @return 0
+ */
+static int cmd_coredump_has_stored_dump(const struct shell *sh,
+					size_t argc, char **argv)
+{
+	int ret;
+
+	ARG_UNUSED(argc);
+	ARG_UNUSED(argv);
+
+	ret = coredump_query(COREDUMP_QUERY_HAS_STORED_DUMP, NULL);
+	if (ret == 1) {
+		shell_print(sh, "Stored coredump found.");
+	} else if (ret == 0) {
+		shell_print(sh, "Stored coredump NOT found.");
+	} else if (ret == -ENOTSUP) {
+		shell_print(sh, "Unsupported query from the backend");
+	} else {
+		shell_print(sh, "Failed to perform query: %d", ret);
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Shell command to verify if the stored coredump is valid.
+ *
+ * @param sh shell instance
+ * @param argc (not used)
+ * @param argv (not used)
+ * @return 0
+ */
+static int cmd_coredump_verify_stored_dump(const struct shell *sh,
+					   size_t argc, char **argv)
+{
+	int ret;
+
+	ARG_UNUSED(argc);
+	ARG_UNUSED(argv);
+
+	ret = coredump_cmd(COREDUMP_CMD_VERIFY_STORED_DUMP, NULL);
+	if (ret == 1) {
+		shell_print(sh, "Stored coredump verified.");
+	} else if (ret == 0) {
+		shell_print(sh, "Stored coredump verification failed "
+			    "or there is no stored coredump.");
+	} else if (ret == -ENOTSUP) {
+		shell_print(sh, "Unsupported command from the backend");
+	} else {
+		shell_print(sh, "Failed to perform verify command: %d", ret);
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Flush the print buffer to shell.
+ *
+ * This prints what is in the print buffer to the shell.
+ *
+ * @param sh shell instance.
+ */
+static void flush_print_buf(const struct shell *sh)
+{
+	shell_print(sh, "%s%s", COREDUMP_PREFIX_STR, print_buf);
+	print_buf_ptr = 0;
+	(void)memset(print_buf, 0, sizeof(print_buf));
+}
+
+/**
+ * @brief Helper to print Zephyr coredump header to shell
+ *
+ * @param sh shell instance
+ * @param buf pointer to header
+ * @return size of data processed, -EINVAL if error converting data
+ */
+static int print_coredump_hdr(const struct shell *sh, uint8_t *buf)
+{
+	struct coredump_hdr_t *hdr = (struct coredump_hdr_t *)buf;
+
+	if (memcmp(hdr->id, "ZE", sizeof(char)*2) != 0) {
+		shell_print(sh, "Not a Zephyr coredump header");
+		return -EINVAL;
+	}
+
+	shell_print(sh, "**** Zephyr Coredump ****");
+	shell_print(sh, "\tVersion %u", hdr->hdr_version);
+	shell_print(sh, "\tTarget: %s",
+		    coredump_target_code2str[sys_le16_to_cpu(
+				    hdr->tgt_code)]);
+	shell_print(sh, "\tPointer size: %u",
+		    (uint16_t)BIT(hdr->ptr_size_bits));
+	shell_print(sh, "\tFlag: %u", hdr->flag);
+	shell_print(sh, "\tReason: %u", sys_le16_to_cpu(hdr->reason));
+
+	return sizeof(struct coredump_hdr_t);
+}
+
+/**
+ * @brief Helper to print stored coredump data to shell
+ *
+ * This converts the binary data in @p buf to hexadecimal digits
+ * which can be printed to the shell.
+ *
+ * @param sh shell instance
+ * @param buf binary data buffer
+ * @param len number of bytes in buffer to be printed
+ * @return 0 if no issues; -EINVAL if error converting data
+ */
+static int print_stored_dump(const struct shell *sh, uint8_t *buf, size_t len)
+{
+	int ret = 0;
+	size_t i = 0;
+	size_t remaining = len;
+
+	if (len == 0) {
+		/* Flush print buffer */
+		flush_print_buf(sh);
+		goto out;
+	}
+
+	while (remaining > 0) {
+		if (hex2char(buf[i] >> 4, &print_buf[print_buf_ptr]) < 0) {
+			ret = -EINVAL;
+			break;
+		}
+		print_buf_ptr++;
+
+		if (hex2char(buf[i] & 0xf, &print_buf[print_buf_ptr]) < 0) {
+			ret = -EINVAL;
+			break;
+		}
+		print_buf_ptr++;
+
+		remaining--;
+		i++;
+
+		if (print_buf_ptr == PRINT_BUF_SZ) {
+			flush_print_buf(sh);
+		}
+	}
+
+out:
+	return ret;
+}
+
+/**
+ * @brief Print raw data to shell in hexadecimal (prefixed)
+ *
+ * @param sh Shell instance
+ * @param copy A pointer on the coredump copy current context
+ * @param size Size of the data to recover/print
+ * @param error A boolean indicating so query coredump error at the end
+ * @return 0 on success, -EINVAL otherwise
+ */
+static int print_raw_data(const struct shell *sh,
+			  struct coredump_cmd_copy_arg *copy,
+			  int size, bool error)
+{
+	int ret;
+
+	copy->length = COPY_BUF_SZ;
+
+	print_buf_ptr = 0;
+	(void)memset(print_buf, 0, sizeof(print_buf));
+
+	shell_print(sh, "%s%s", COREDUMP_PREFIX_STR, COREDUMP_BEGIN_STR);
+
+	while (size > 0) {
+		if (size < COPY_BUF_SZ) {
+			copy->length = size;
+		}
+
+		ret = coredump_cmd(COREDUMP_CMD_COPY_STORED_DUMP, copy);
+		if (ret != 0) {
+			return -EINVAL;
+		}
+
+		ret = print_stored_dump(sh, copy->buffer, copy->length);
+		if (ret != 0) {
+			return -EINVAL;
+		}
+
+		if (print_buf_ptr != 0) {
+			shell_print(sh, "%s%s", COREDUMP_PREFIX_STR, print_buf);
+		}
+
+		copy->offset += copy->length;
+		size -= copy->length;
+	}
+
+	if (error && coredump_query(COREDUMP_QUERY_GET_ERROR, NULL) != 0) {
+		shell_print(sh, "%s%s", COREDUMP_PREFIX_STR,
+			    COREDUMP_ERROR_STR);
+	}
+
+	shell_print(sh, "%s%s\n", COREDUMP_PREFIX_STR, COREDUMP_END_STR);
+
+	return 0;
+}
+
+/**
+ * @brief Helper parsing and pretty-printing the coredump
+ *
+ * @param sh shell instance
+ * @param coredump_header Pointer to a boolean indicating zephyr coredump
+ *        got parsed/printed aleardy header
+ * @param copy A pointer on the coredump copy context
+ * @param left_size How much of the coredump has not been parsed/printed yet
+ * @return 0 if all has been processed, a positive value indicating the amount
+ *        that the function call has processed, a negative errno otherwise
+ */
+static int parse_and_print_coredump(const struct shell *sh,
+				    bool *coredump_header,
+				    struct coredump_cmd_copy_arg *copy,
+				    size_t left_size)
+{
+	int processed_size = 0;
+	int data_size = 0;
+	int ret;
+
+	if (!*coredump_header) {
+		copy->length = sizeof(struct coredump_hdr_t);
+	} else {
+		/* thread header is of same size, but memory header */
+		copy->length = sizeof(struct coredump_arch_hdr_t);
+	}
+
+	if (copy->length > left_size) {
+		return -ENOMEM;
+	}
+
+	ret = coredump_cmd(COREDUMP_CMD_COPY_STORED_DUMP, copy);
+	if (ret != 0) {
+		return ret;
+	}
+
+	if (!*coredump_header) {
+		ret = print_coredump_hdr(sh, copy->buffer);
+		shell_print(sh, "\tSize of the coredump: %lu\n",
+			    (unsigned long)left_size);
+
+		*coredump_header = true;
+
+		goto hdr_done;
+	}
+
+	/* hdr id */
+	switch (copy->buffer[0]) {
+	case COREDUMP_ARCH_HDR_ID: {
+		struct coredump_arch_hdr_t *hdr =
+			(struct coredump_arch_hdr_t *)copy->buffer;
+
+		shell_print(sh, "-> Arch coredump header found");
+		shell_print(sh, "\tVersion %u", hdr->hdr_version);
+		shell_print(sh, "\tSize %u", hdr->num_bytes);
+
+		data_size = hdr->num_bytes;
+		break;
+	}
+	case THREADS_META_HDR_ID: {
+		struct coredump_threads_meta_hdr_t *hdr =
+			(struct coredump_threads_meta_hdr_t *)copy->buffer;
+
+		shell_print(sh, "-> Thread coredump header found");
+		shell_print(sh, "\tVersion %u", hdr->hdr_version);
+		shell_print(sh, "\tSize %u", hdr->num_bytes);
+
+		data_size = hdr->num_bytes;
+		break;
+	}
+	case COREDUMP_MEM_HDR_ID: {
+		struct coredump_mem_hdr_t *hdr;
+
+		copy->length = sizeof(struct coredump_mem_hdr_t);
+		if (copy->length > left_size) {
+			return -ENOMEM;
+		}
+
+		ret = coredump_cmd(COREDUMP_CMD_COPY_STORED_DUMP, copy);
+		if (ret != 0) {
+			return -ENOMEM;
+		}
+
+		hdr = (struct coredump_mem_hdr_t *)copy->buffer;
+
+		if (sizeof(uintptr_t) == 8) {
+			hdr->start = sys_le64_to_cpu(hdr->start);
+			hdr->end = sys_le64_to_cpu(hdr->end);
+		} else {
+			hdr->start = sys_le32_to_cpu(hdr->start);
+			hdr->end = sys_le32_to_cpu(hdr->end);
+		}
+
+		data_size = hdr->end - hdr->start;
+
+		shell_print(sh, "-> Memory coredump header found");
+		shell_print(sh, "\tVersion %u", hdr->hdr_version);
+		shell_print(sh, "\tSize %u", data_size);
+		shell_print(sh, "\tStarts at %p ends at %p",
+			    (void *)hdr->start, (void *)hdr->end);
+		break;
+	}
+	default:
+		return -EINVAL;
+	}
+
+	if (data_size > left_size) {
+		return -ENOMEM;
+	}
+
+hdr_done:
+	copy->offset += copy->length;
+	processed_size += copy->length + data_size;
+
+	if (data_size == 0) {
+		goto out;
+	}
+
+	shell_print(sh, "Data:");
+
+	ret = print_raw_data(sh, copy, data_size, false);
+	if (ret !=  0) {
+		return ret;
+	}
+out:
+	return processed_size;
+}
+
+
+/**
+ * @brief Print out the coredump in a human-readable way
+ *
+ * @param sh Shell instance
+ * @param size Size of the coredump
+ * @return 0
+ */
+static int pretty_print_coredump(const struct shell *sh, int size)
+{
+	uint8_t rbuf[COPY_BUF_SZ];
+	struct coredump_cmd_copy_arg copy = {
+		.offset = 0,
+		.buffer = rbuf,
+	};
+	bool cdump_hdr = false;
+	int ret;
+
+	while (size > 0) {
+		ret = parse_and_print_coredump(sh, &cdump_hdr, &copy, size);
+		if (ret < 0) {
+			goto error;
+		}
+
+		if (ret == 0) {
+			break;
+		}
+
+		size -= ret;
+	}
+
+	shell_print(sh, "Stored coredump printed");
+
+	goto out;
+error:
+	if (ret == -ENOTSUP) {
+		shell_print(sh, "Unsupported command from the backend");
+	} else {
+		shell_print(sh, "Error while retrieving/parsing coredump: %d", ret);
+	}
+out:
+	return 0;
+}
+
+/**
+ * @brief Print out the coredump fully in hexadecimal
+ *
+ * @param sh Shell instance
+ * @param size Size of the coredump
+ * @return 0
+ */
+static int hex_print_coredump(const struct shell *sh, int size)
+{
+	uint8_t rbuf[COPY_BUF_SZ];
+	struct coredump_cmd_copy_arg copy = {
+		.offset = 0,
+		.buffer = rbuf,
+	};
+	int ret;
+
+	ret = print_raw_data(sh, &copy, size, true);
+	if (ret == 0) {
+		shell_print(sh, "Stored coredump printed.");
+	} else {
+		shell_print(sh, "Failed to print: %d", ret);
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Shell command to print stored coredump data to shell
+ *
+ * @param sh Shell instance
+ * @param argc Number of elements in argv
+ * @param argv Parsed arguments
+ * @return 0
+ */
+static int cmd_coredump_print_stored_dump(const struct shell *sh,
+					  size_t argc, char **argv)
+{
+	int size;
+	int ret;
+
+	if (argc > 2) {
+		shell_print(sh, "Too many options");
+		return 0;
+	}
+
+	if (argv[1] != NULL) {
+		if (strncmp(argv[1], "pretty", 6) != 0) {
+			shell_print(sh, "Unknown option: %s", argv[1]);
+			return 0;
+		}
+	}
+
+	/* Verify first to see if stored dump is valid */
+	ret = coredump_cmd(COREDUMP_CMD_VERIFY_STORED_DUMP, NULL);
+	if (ret == 0) {
+		shell_print(sh, "Stored coredump verification failed "
+			    "or there is no stored coredump.");
+		return 0;
+	} else if (ret == -ENOTSUP) {
+		shell_print(sh, "Unsupported command from the backend");
+		return 0;
+	} else if (ret != 1) {
+		shell_print(sh, "Failed to perform verify command: %d", ret);
+		return 0;
+	}
+
+	size = coredump_query(COREDUMP_QUERY_GET_STORED_DUMP_SIZE, NULL);
+	if (size <= 0) {
+		shell_print(sh, "Invalid coredump size: %d", size);
+		return 0;
+	}
+
+	if (argv[1] != NULL) {
+		pretty_print_coredump(sh, size);
+	} else {
+		hex_print_coredump(sh, size);
+	}
+
+	return 0;
+}
+
+/**
+ * @brief Shell command to erase stored coredump.
+ *
+ * @param sh shell instance
+ * @param argc (not used)
+ * @param argv (not used)
+ * @return 0
+ */
+static int cmd_coredump_erase_stored_dump(const struct shell *sh,
+					  size_t argc, char **argv)
+{
+	int ret;
+
+	ARG_UNUSED(argc);
+	ARG_UNUSED(argv);
+
+	ret = coredump_cmd(COREDUMP_CMD_ERASE_STORED_DUMP, NULL);
+	if (ret == 0) {
+		shell_print(sh, "Stored coredump erased.");
+	} else if (ret == -ENOTSUP) {
+		shell_print(sh, "Unsupported command from the backend");
+	} else {
+		shell_print(sh, "Failed to perform erase command: %d", ret);
+	}
+
+	return 0;
+}
+
+SHELL_STATIC_SUBCMD_SET_CREATE(sub_coredump_error,
+	SHELL_CMD(clear, NULL, "Clear Coredump error",
+		  cmd_coredump_error_clear),
+	SHELL_CMD(get, NULL, "Get Coredump error", cmd_coredump_error_get),
+	SHELL_SUBCMD_SET_END /* Array terminated. */
+);
+
+SHELL_STATIC_SUBCMD_SET_CREATE(sub_coredump,
+	SHELL_CMD(error, &sub_coredump_error,
+		  "Get/clear backend error.", NULL),
+	SHELL_CMD(erase, NULL,
+		  "Erase stored coredump",
+		  cmd_coredump_erase_stored_dump),
+	SHELL_CMD(find, NULL,
+		  "Query if there is a stored coredump",
+		  cmd_coredump_has_stored_dump),
+	SHELL_CMD(print, NULL,
+		  "Print stored coredump to shell "
+		  "(use option 'pretty' to get human readable output)",
+		  cmd_coredump_print_stored_dump),
+	SHELL_CMD(verify, NULL,
+		  "Verify stored coredump",
+		  cmd_coredump_verify_stored_dump),
+	SHELL_SUBCMD_SET_END /* Array terminated. */
+);
+
+SHELL_CMD_REGISTER(coredump, &sub_coredump,
+		   "Coredump commands (" COREDUMP_BACKEND_STR " backend)",
+		   NULL);
diff --git a/subsys/debug/cpu_load.c b/subsys/debug/cpu_load.c
new file mode 100644
index 00000000000..0754d673b77
--- /dev/null
+++ b/subsys/debug/cpu_load.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2024, Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/debug/cpu_load.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/counter.h>
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(cpu_load, CONFIG_CPU_LOAD_LOG_LEVEL);
+
+BUILD_ASSERT(!IS_ENABLED(CONFIG_CPU_LOAD_USE_COUNTER) || DT_HAS_CHOSEN(zephyr_cpu_load_counter));
+
+#ifndef CONFIG_CPU_LOAD_LOG_PERIODICALLY
+#define CONFIG_CPU_LOAD_LOG_PERIODICALLY 0
+#endif
+
+static const struct device *counter = COND_CODE_1(CONFIG_CPU_LOAD_USE_COUNTER,
+				(DEVICE_DT_GET(DT_CHOSEN(zephyr_cpu_load_counter))), (NULL));
+static uint32_t enter_ts;
+static uint32_t cyc_start;
+static uint32_t ticks_idle;
+
+static struct k_work_delayable cpu_load_log;
+
+void cpu_load_log_control(bool enable)
+{
+	if (CONFIG_CPU_LOAD_LOG_PERIODICALLY == 0) {
+		return;
+	}
+
+	if (enable) {
+		(void)cpu_load_get(true);
+		k_work_schedule(&cpu_load_log, K_MSEC(CONFIG_CPU_LOAD_LOG_PERIODICALLY));
+	} else {
+		k_work_cancel_delayable(&cpu_load_log);
+	}
+}
+
+#if CONFIG_CPU_LOAD_USE_COUNTER || CONFIG_CPU_LOAD_LOG_PERIODICALLY
+static void cpu_load_log_fn(struct k_work *work)
+{
+	int load = cpu_load_get(true);
+	uint32_t percent = load / 10;
+	uint32_t fraction = load % 10;
+
+	LOG_INF("Load:%d.%03d%%", percent, fraction);
+	cpu_load_log_control(true);
+}
+
+static int cpu_load_init(void)
+{
+	if (IS_ENABLED(CONFIG_CPU_LOAD_USE_COUNTER)) {
+		int err = counter_start(counter);
+
+		(void)err;
+		__ASSERT_NO_MSG(err == 0);
+	}
+
+	if (CONFIG_CPU_LOAD_LOG_PERIODICALLY > 0) {
+		k_work_init_delayable(&cpu_load_log, cpu_load_log_fn);
+		return k_work_schedule(&cpu_load_log, K_MSEC(CONFIG_CPU_LOAD_LOG_PERIODICALLY));
+	}
+
+	return 0;
+}
+
+SYS_INIT(cpu_load_init, POST_KERNEL, 0);
+#endif
+
+void cpu_load_on_enter_idle(void)
+{
+	if (IS_ENABLED(CONFIG_CPU_LOAD_USE_COUNTER)) {
+		counter_get_value(counter, &enter_ts);
+		return;
+	}
+
+	enter_ts = k_cycle_get_32();
+}
+
+void cpu_load_on_exit_idle(void)
+{
+	uint32_t now;
+
+	if (IS_ENABLED(CONFIG_CPU_LOAD_USE_COUNTER)) {
+		counter_get_value(counter, &now);
+	} else {
+		now = k_cycle_get_32();
+	}
+
+	ticks_idle += now - enter_ts;
+}
+
+int cpu_load_get(bool reset)
+{
+	uint32_t idle_us;
+	uint32_t total = k_cycle_get_32() - cyc_start;
+	uint32_t total_us = (uint32_t)k_cyc_to_us_floor32(total);
+	uint32_t res;
+	uint32_t active_us;
+
+	if (IS_ENABLED(CONFIG_CPU_LOAD_USE_COUNTER)) {
+		idle_us = counter_ticks_to_us(counter, ticks_idle);
+	} else {
+		idle_us = k_cyc_to_us_floor32(ticks_idle);
+	}
+
+	idle_us = MIN(idle_us, total_us);
+	active_us = total_us - idle_us;
+
+	res = ((1000 * active_us) / total_us);
+
+	if (reset) {
+		cyc_start = k_cycle_get_32();
+		ticks_idle = 0;
+	}
+
+	return res;
+}
diff --git a/subsys/debug/gdbstub/gdbstub.c b/subsys/debug/gdbstub/gdbstub.c
index bb07d0575e5..82e06521a6e 100644
--- a/subsys/debug/gdbstub/gdbstub.c
+++ b/subsys/debug/gdbstub/gdbstub.c
@@ -55,12 +55,6 @@ __weak const size_t gdb_mem_num_regions;
  * @return Pointer to the memory region description if found.
  *         NULL if not found.
  */
-#if defined(__GNUC__)
-#pragma GCC diagnostic push
-/* Required due to gdb_mem_region_array having a default size of zero. */
-#pragma GCC diagnostic ignored "-Warray-bounds"
-#endif
-
 static inline const
 struct gdb_mem_region *find_memory_region(const uintptr_t addr, const size_t len)
 {
@@ -82,10 +76,6 @@ struct gdb_mem_region *find_memory_region(const uintptr_t addr, const size_t len
 	return ret;
 }
 
-#if defined(__GNUC__)
-#pragma GCC diagnostic pop
-#endif
-
 bool gdb_mem_can_read(const uintptr_t addr, const size_t len, uint8_t *align)
 {
 	bool ret = false;
diff --git a/subsys/debug/thread_analyzer/CMakeLists.txt b/subsys/debug/thread_analyzer/CMakeLists.txt
new file mode 100644
index 00000000000..982f6b8a969
--- /dev/null
+++ b/subsys/debug/thread_analyzer/CMakeLists.txt
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources(
+  thread_analyzer.c
+  )
diff --git a/subsys/debug/thread_analyzer/Kconfig b/subsys/debug/thread_analyzer/Kconfig
new file mode 100644
index 00000000000..d0828a3b642
--- /dev/null
+++ b/subsys/debug/thread_analyzer/Kconfig
@@ -0,0 +1,116 @@
+# Thread analyzer configuration options
+
+# Copyright (c) 2015 Wind River Systems, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig THREAD_ANALYZER
+	bool "Thread analyzer"
+	depends on !ARCH_POSIX
+	select INIT_STACKS
+	select THREAD_MONITOR
+	select THREAD_STACK_INFO
+	select THREAD_RUNTIME_STATS
+	help
+	  Enable thread analyzer functionality and all the required modules.
+	  This module may be used to debug thread configuration issues, e.g.
+	  stack size configuration to find stack overflow or to find stacks
+	  which may be optimized.
+
+if THREAD_ANALYZER
+module = THREAD_ANALYZER
+module-str = thread analyzer
+source "subsys/logging/Kconfig.template.log_config"
+
+choice
+	prompt "Thread analysis print mode"
+	default THREAD_ANALYZER_USE_PRINTK
+
+config THREAD_ANALYZER_USE_LOG
+	bool "Use logger output"
+	select LOG
+	help
+	  Use logger output to print thread information.
+
+config THREAD_ANALYZER_USE_PRINTK
+	bool "Use printk function"
+	help
+	  Use kernel printk function to print thread information.
+
+endchoice
+
+config THREAD_ANALYZER_ISR_STACK_USAGE
+	bool "Analyze interrupt stacks usage"
+	default y
+
+config THREAD_ANALYZER_PRIV_STACK_USAGE
+	bool "Analyze privileged stacks usage"
+	depends on USERSPACE
+	depends on ARCH_HAS_THREAD_PRIV_STACK_SPACE_GET
+	help
+	  Print privileged stack usage for user threads.
+
+config THREAD_ANALYZER_RUN_UNLOCKED
+	bool "Run analysis with interrupts unlocked"
+	default y
+	help
+	  The thread analysis takes quite a long time.
+	  Every thread it finds is analyzed word by word to find any that
+	  does not match the magic number.
+	  Normally while thread are analyzed the k_thread_foreach function
+	  is used.
+	  While this is a safe run from the thread list perspective it may lock
+	  the interrupts for a long time - long enough to disconnect when
+	  Bluetooth communication is used.
+	  Setting this flag will force thread analyzer to use
+	  the k_thread_foreach_unlocked function.
+	  This will allow the interrupts to be processed while the thread is
+	  analyzed.
+	  For the limitation of such configuration see the k_thread_foreach
+	  documentation.
+
+config THREAD_ANALYZER_AUTO
+	bool "Run periodic thread analysis in a thread"
+	help
+	  Run the thread analyzer automatically, without the need to add
+	  any code to the application.
+	  Thread analysis would be called periodically.
+
+if THREAD_ANALYZER_AUTO
+
+config THREAD_ANALYZER_AUTO_SEPARATE_CORES
+	bool "Run thread analyzer separately on each core"
+	default y if KERNEL_COHERENCE
+	depends on SCHED_CPU_MASK
+	help
+	  Run the thread analyzer auto thread on each core and report
+	  cores separately. This feature is needed for platforms running
+	  on cache-incoherent architectures.
+
+config THREAD_ANALYZER_AUTO_INTERVAL
+	int "Thread analysis interval"
+	default 60
+	range 5 3600
+	help
+	  The time in seconds to call thread analyzer periodic printing function.
+
+config THREAD_ANALYZER_AUTO_STACK_SIZE
+	int "Stack size for the periodic thread analysis thread"
+	default 2048 if THREAD_ANALYZER_USE_LOG && LOG_MODE_IMMEDIATE && NO_OPTIMIZATIONS
+	default 1024
+
+config THREAD_ANALYZER_AUTO_THREAD_PRIORITY_OVERRIDE
+	bool "Override default thread analysis thread priority"
+	help
+	  Option to change the default value of thread analysis thread priority.
+
+if THREAD_ANALYZER_AUTO_THREAD_PRIORITY_OVERRIDE
+config THREAD_ANALYZER_AUTO_THREAD_PRIORITY
+	int "Thread analysis thread priority"
+	default 0
+	help
+	  Set thread priority of the thread analysis
+endif # THREAD_ANALYZER_AUTO_THREAD_PRIORITY_OVERRIDE
+
+endif # THREAD_ANALYZER_AUTO
+
+endif # THREAD_ANALYZER
diff --git a/subsys/debug/thread_analyzer.c b/subsys/debug/thread_analyzer/thread_analyzer.c
similarity index 95%
rename from subsys/debug/thread_analyzer.c
rename to subsys/debug/thread_analyzer/thread_analyzer.c
index 28399776394..a35d9a386c4 100644
--- a/subsys/debug/thread_analyzer.c
+++ b/subsys/debug/thread_analyzer/thread_analyzer.c
@@ -9,15 +9,23 @@
  */
 
 #include <zephyr/kernel.h>
+/* For z_stack_space_get() */
 #include <kernel_internal.h>
 #include <zephyr/debug/thread_analyzer.h>
 #include <zephyr/debug/stack.h>
 #include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
 #include <stdio.h>
+#include <zephyr/init.h>
 
 LOG_MODULE_REGISTER(thread_analyzer, CONFIG_THREAD_ANALYZER_LOG_LEVEL);
 
+#if CONFIG_THREAD_ANALYZER_AUTO_THREAD_PRIORITY_OVERRIDE
+#define AUTO_THREAD_PRIO CONFIG_THREAD_ANALYZER_AUTO_THREAD_PRIORITY
+#else
+#define AUTO_THREAD_PRIO K_LOWEST_APPLICATION_THREAD_PRIO
+#endif
+
 #if defined(CONFIG_THREAD_ANALYZER_USE_PRINTK)
 #define THREAD_ANALYZER_PRINT(...) printk(__VA_ARGS__)
 #define THREAD_ANALYZER_FMT(str)   str "\n"
@@ -106,8 +114,6 @@ static void thread_analyze_cb(const struct k_thread *cthread, void *user_data)
 	int err;
 	int ret;
 
-
-
 	name = k_thread_name_get((k_tid_t)thread);
 	if (!name || name[0] == '\0') {
 		name = hexname;
@@ -264,8 +270,8 @@ static int thread_analyzer_init(void)
 		tid = k_thread_create(&analyzer_thread[i], analyzer_thread_stacks[i],
 				      CONFIG_THREAD_ANALYZER_AUTO_STACK_SIZE,
 				      thread_analyzer_auto,
-				      (void *) (uint32_t) i, NULL, NULL,
-				      K_LOWEST_APPLICATION_THREAD_PRIO, 0, K_FOREVER);
+				      (void *) (uintptr_t) i, NULL, NULL,
+				      AUTO_THREAD_PRIO, 0, K_FOREVER);
 		if (!tid) {
 			LOG_ERR("k_thread_create() failed for core %u", i);
 			continue;
@@ -297,7 +303,7 @@ K_THREAD_DEFINE(thread_analyzer,
 		CONFIG_THREAD_ANALYZER_AUTO_STACK_SIZE,
 		thread_analyzer_auto,
 		NULL, NULL, NULL,
-		K_LOWEST_APPLICATION_THREAD_PRIO,
+		AUTO_THREAD_PRIO,
 		0, 0);
 
 #endif /* CONFIG_THREAD_ANALYZER_AUTO_SEPARATE_CORES */
diff --git a/subsys/demand_paging/backing_store/Kconfig b/subsys/demand_paging/backing_store/Kconfig
index 96b8ead7796..73507d0b034 100644
--- a/subsys/demand_paging/backing_store/Kconfig
+++ b/subsys/demand_paging/backing_store/Kconfig
@@ -3,7 +3,7 @@
 
 choice BACKING_STORE_CHOICE
 	prompt "Backing store algorithms"
-	default BACKING_STORE_CUSTOM
+	default BACKING_STORE_RAM
 
 config BACKING_STORE_CUSTOM
 	bool "Custom backing store implementation"
diff --git a/subsys/demand_paging/backing_store/backing_store_ondemand_semihost.c b/subsys/demand_paging/backing_store/backing_store_ondemand_semihost.c
index 9f062a3002a..26095e4b628 100644
--- a/subsys/demand_paging/backing_store/backing_store_ondemand_semihost.c
+++ b/subsys/demand_paging/backing_store/backing_store_ondemand_semihost.c
@@ -34,7 +34,7 @@ void k_mem_paging_backing_store_location_free(uintptr_t location)
 
 void k_mem_paging_backing_store_page_out(uintptr_t location)
 {
-	__ASSERT(true, "not ever supposed to be called");
+	__ASSERT(false, "not ever supposed to be called");
 	k_panic();
 }
 
diff --git a/subsys/dfu/boot/mcuboot.c b/subsys/dfu/boot/mcuboot.c
index b9753eef141..2984efe0906 100644
--- a/subsys/dfu/boot/mcuboot.c
+++ b/subsys/dfu/boot/mcuboot.c
@@ -42,6 +42,13 @@ LOG_MODULE_REGISTER(mcuboot_dfu, LOG_LEVEL_DBG);
 #define BOOT_HEADER_MAGIC_V1 0x96f3b83d
 #define BOOT_HEADER_SIZE_V1 32
 
+enum IMAGE_INDEXES {
+	IMAGE_INDEX_INVALID = -1,
+	IMAGE_INDEX_0,
+	IMAGE_INDEX_1,
+	IMAGE_INDEX_2
+};
+
 #if USE_PARTITION_MANAGER
 #include <pm_config.h>
 
@@ -86,7 +93,6 @@ LOG_MODULE_REGISTER(mcuboot_dfu, LOG_LEVEL_DBG);
 
 #if defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD)
 /* For RAM LOAD mode, the active image must be fetched from the bootloader */
-static uint8_t boot_fetch_active_slot(void);
 #define ACTIVE_SLOT_FLASH_AREA_ID boot_fetch_active_slot()
 #define INVALID_SLOT_ID 255
 #else
@@ -120,7 +126,7 @@ struct mcuboot_v1_raw_header {
  */
 
 #if defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD)
-static uint8_t boot_fetch_active_slot(void)
+uint8_t boot_fetch_active_slot(void)
 {
 	int rc;
 	uint8_t slot;
@@ -137,13 +143,76 @@ static uint8_t boot_fetch_active_slot(void)
 
 	return slot;
 }
+#else  /* CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD */
+uint8_t boot_fetch_active_slot(void)
+{
+	return ACTIVE_SLOT_FLASH_AREA_ID;
+}
+#endif /* CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD */
+
+#if defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_USING_OFFSET)
+size_t boot_get_image_start_offset(uint8_t area_id)
+{
+	size_t off = 0;
+	int image = IMAGE_INDEX_INVALID;
+
+	if (area_id == FIXED_PARTITION_ID(slot1_partition)) {
+		image = IMAGE_INDEX_0;
+#if FIXED_PARTITION_EXISTS(slot3_partition)
+	} else if (area_id == FIXED_PARTITION_ID(slot3_partition)) {
+		image = IMAGE_INDEX_1;
+#endif
+#if FIXED_PARTITION_EXISTS(slot5_partition)
+	} else if (area_id == FIXED_PARTITION_ID(slot5_partition)) {
+		image = IMAGE_INDEX_2;
 #endif
+	}
+
+	if (image != IMAGE_INDEX_INVALID) {
+		/* Need to check status from primary slot to get correct offset for secondary
+		 * slot image header
+		 */
+		const struct flash_area *fa;
+		uint32_t num_sectors = SWAP_USING_OFFSET_SECTOR_UPDATE_BEGIN;
+		struct flash_sector sector_data;
+		int rc;
+
+		rc = flash_area_open(area_id, &fa);
+		if (rc) {
+			LOG_ERR("Flash open area %u failed: %d", area_id, rc);
+			goto done;
+		}
+
+		if (mcuboot_swap_type_multi(image) != BOOT_SWAP_TYPE_REVERT) {
+			/* For swap using offset mode, the image starts in the second sector of
+			 * the upgrade slot, so apply the offset when this is needed, do this by
+			 * getting information on first sector only, this is expected to return an
+			 * error as there are more slots, so allow the not enough memory error
+			 */
+			rc = flash_area_get_sectors(area_id, &num_sectors, &sector_data);
+			if ((rc != 0 && rc != -ENOMEM) ||
+			    num_sectors != SWAP_USING_OFFSET_SECTOR_UPDATE_BEGIN) {
+				LOG_ERR("Failed to get sector details: %d", rc);
+			} else {
+				off = sector_data.fs_size;
+			}
+		}
+
+		flash_area_close(fa);
+	}
+
+done:
+	LOG_DBG("Start offset for area %u: 0x%x", area_id, off);
+	return off;
+}
+#endif /* CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_USING_OFFSET */
 
 static int boot_read_v1_header(uint8_t area_id,
 			       struct mcuboot_v1_raw_header *v1_raw)
 {
 	const struct flash_area *fa;
 	int rc;
+	size_t off = boot_get_image_start_offset(area_id);
 
 	rc = flash_area_open(area_id, &fa);
 	if (rc) {
@@ -151,27 +220,19 @@ static int boot_read_v1_header(uint8_t area_id,
 	}
 
 	/*
-	 * Read and sanity-check the raw header.
+	 * Read and validty-check the raw header.
 	 */
-	rc = flash_area_read(fa, 0, v1_raw, sizeof(*v1_raw));
+	rc = flash_area_read(fa, off, v1_raw, sizeof(*v1_raw));
 	flash_area_close(fa);
 	if (rc) {
 		return rc;
 	}
 
 	v1_raw->header_magic = sys_le32_to_cpu(v1_raw->header_magic);
-	v1_raw->image_load_address =
-		sys_le32_to_cpu(v1_raw->image_load_address);
 	v1_raw->header_size = sys_le16_to_cpu(v1_raw->header_size);
-	v1_raw->image_size = sys_le32_to_cpu(v1_raw->image_size);
-	v1_raw->image_flags = sys_le32_to_cpu(v1_raw->image_flags);
-	v1_raw->version.revision =
-		sys_le16_to_cpu(v1_raw->version.revision);
-	v1_raw->version.build_num =
-		sys_le32_to_cpu(v1_raw->version.build_num);
 
 	/*
-	 * Sanity checks.
+	 * Validity checks.
 	 *
 	 * Larger values in header_size than BOOT_HEADER_SIZE_V1 are
 	 * possible, e.g. if Zephyr was linked with
@@ -182,6 +243,16 @@ static int boot_read_v1_header(uint8_t area_id,
 		return -EIO;
 	}
 
+	v1_raw->image_load_address =
+		sys_le32_to_cpu(v1_raw->image_load_address);
+	v1_raw->header_size = sys_le16_to_cpu(v1_raw->header_size);
+	v1_raw->image_size = sys_le32_to_cpu(v1_raw->image_size);
+	v1_raw->image_flags = sys_le32_to_cpu(v1_raw->image_flags);
+	v1_raw->version.revision =
+		sys_le16_to_cpu(v1_raw->version.revision);
+	v1_raw->version.build_num =
+		sys_le32_to_cpu(v1_raw->version.build_num);
+
 	return 0;
 }
 
diff --git a/subsys/dfu/img_util/flash_img.c b/subsys/dfu/img_util/flash_img.c
index 69fa559f0e3..8f287404da3 100644
--- a/subsys/dfu/img_util/flash_img.c
+++ b/subsys/dfu/img_util/flash_img.c
@@ -1,21 +1,26 @@
 /*
- * Copyright (c) 2017, 2020 Nordic Semiconductor ASA
+ * Copyright (c) 2017-2025 Nordic Semiconductor ASA
  * Copyright (c) 2017 Linaro Limited
  * Copyright (c) 2020 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <zephyr/types.h>
+#include <assert.h>
 #include <stddef.h>
 #include <stdio.h>
 #include <string.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/dfu/mcuboot.h>
 #include <zephyr/dfu/flash_img.h>
+#include <zephyr/dfu/mcuboot.h>
 #include <zephyr/storage/flash_map.h>
 #include <zephyr/storage/stream_flash.h>
 
+LOG_MODULE_REGISTER(flash_img, CONFIG_IMG_MANAGER_LOG_LEVEL);
+
 #ifdef CONFIG_IMG_ERASE_PROGRESSIVELY
 #include <bootutil/bootutil_public.h>
-#include <zephyr/dfu/mcuboot.h>
 #endif
 
 #include <zephyr/devicetree.h>
@@ -29,8 +34,13 @@
 #endif
 #endif
 
+#ifdef CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD
+/* For RAM LOAD mode, the active image must be fetched from the bootloader */
+#define UPLOAD_FLASH_AREA_ID flash_img_get_upload_slot()
+#else
 /* FIXED_PARTITION_ID() values used below are auto-generated by DT */
 #define UPLOAD_FLASH_AREA_ID FIXED_PARTITION_ID(UPLOAD_FLASH_AREA_LABEL)
+#endif /* CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD */
 #define UPLOAD_FLASH_AREA_CONTROLLER \
 	DT_GPARENT(DT_NODELABEL(UPLOAD_FLASH_AREA_LABEL))
 
@@ -43,6 +53,9 @@ BUILD_ASSERT((CONFIG_IMG_BLOCK_BUF_SIZE % FLASH_WRITE_BLOCK_SIZE == 0),
 	     "FLASH_WRITE_BLOCK_SIZE");
 #endif
 
+#define FLASH_CHECK_ERASED_BUFFER_SIZE 16
+#define ERASED_VAL_32(x) (((x) << 24) | ((x) << 16) | ((x) << 8) | (x))
+
 static int scramble_mcuboot_trailer(struct flash_img_context *ctx)
 {
 	int rc = 0;
@@ -127,10 +140,64 @@ size_t flash_img_bytes_written(struct flash_img_context *ctx)
 	return stream_flash_bytes_written(&ctx->stream);
 }
 
+#if defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_USING_OFFSET)
+/**
+ * Determines if the specified area of flash is completely unwritten.
+ *
+ * @param	fa	pointer to flash area to scan
+ *
+ * @return	0	when not empty, 1 when empty, negative errno code on error.
+ */
+static int flash_check_erased(const struct flash_area *fa)
+{
+	uint32_t data[FLASH_CHECK_ERASED_BUFFER_SIZE];
+	off_t addr;
+	off_t end;
+	int bytes_to_read;
+	int rc;
+	int i;
+	uint8_t erased_val;
+	uint32_t erased_val_32;
+
+	assert(fa->fa_size % sizeof(erased_val_32) == 0);
+
+	erased_val = flash_area_erased_val(fa);
+	erased_val_32 = ERASED_VAL_32(erased_val);
+
+	end = fa->fa_size;
+	for (addr = 0; addr < end; addr += sizeof(data)) {
+		if (end - addr < sizeof(data)) {
+			bytes_to_read = end - addr;
+		} else {
+			bytes_to_read = sizeof(data);
+		}
+
+		rc = flash_area_read(fa, addr, data, bytes_to_read);
+
+		if (rc < 0) {
+			LOG_ERR("Failed to read data from flash area: %d", rc);
+			return rc;
+		}
+
+		for (i = 0; i < bytes_to_read / sizeof(erased_val_32); i++) {
+			if (data[i] != erased_val_32) {
+				return 0;
+			}
+		}
+	}
+
+	return 1;
+}
+#endif
+
 int flash_img_init_id(struct flash_img_context *ctx, uint8_t area_id)
 {
 	int rc;
 	const struct device *flash_dev;
+#if defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_USING_OFFSET)
+	uint32_t sector_count = SWAP_USING_OFFSET_SECTOR_UPDATE_BEGIN;
+	struct flash_sector sector_data;
+#endif
 
 	rc = flash_area_open(area_id,
 			       (const struct flash_area **)&(ctx->flash_area));
@@ -140,10 +207,65 @@ int flash_img_init_id(struct flash_img_context *ctx, uint8_t area_id)
 
 	flash_dev = flash_area_get_device(ctx->flash_area);
 
+#if defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_USING_OFFSET)
+	/* Query size of first sector in flash for upgrade slot, so it can be erased, and begin
+	 * upload started at the second sector
+	 */
+	rc = flash_area_sectors((const struct flash_area *)ctx->flash_area, &sector_count,
+				&sector_data);
+
+	if (rc && rc != -ENOMEM) {
+		flash_area_close(ctx->flash_area);
+		ctx->flash_area = NULL;
+		return rc;
+	} else if (sector_count != SWAP_USING_OFFSET_SECTOR_UPDATE_BEGIN) {
+		flash_area_close(ctx->flash_area);
+		ctx->flash_area = NULL;
+		return -ENOENT;
+	}
+
+	if (!flash_check_erased((const struct flash_area *)ctx->flash_area)) {
+		/* Flash is not empty, therefore flatten/erase the area to prevent issues when
+		 * the firmware update process begins
+		 */
+		rc = flash_area_flatten((const struct flash_area *)ctx->flash_area, 0,
+					sector_data.fs_size);
+
+		if (rc) {
+			flash_area_close(ctx->flash_area);
+			ctx->flash_area = NULL;
+			return rc;
+		}
+	}
+
+	return stream_flash_init(&ctx->stream, flash_dev, ctx->buf, CONFIG_IMG_BLOCK_BUF_SIZE,
+				 (ctx->flash_area->fa_off + sector_data.fs_size),
+				 (ctx->flash_area->fa_size - sector_data.fs_size), NULL);
+#else
 	return stream_flash_init(&ctx->stream, flash_dev, ctx->buf,
 			CONFIG_IMG_BLOCK_BUF_SIZE, ctx->flash_area->fa_off,
 			ctx->flash_area->fa_size, NULL);
+#endif
+}
+
+#ifdef CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD
+uint8_t flash_img_get_upload_slot(void)
+{
+	uint8_t slot;
+
+	slot = boot_fetch_active_slot();
+
+	if (slot == FIXED_PARTITION_ID(slot0_partition)) {
+		return FIXED_PARTITION_ID(slot1_partition);
+	}
+	return FIXED_PARTITION_ID(slot0_partition);
+}
+#else  /* CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD */
+uint8_t flash_img_get_upload_slot(void)
+{
+	return UPLOAD_FLASH_AREA_ID;
 }
+#endif /* CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD */
 
 int flash_img_init(struct flash_img_context *ctx)
 {
@@ -170,7 +292,7 @@ int flash_img_check(struct flash_img_context *ctx,
 
 	fac.match = fic->match;
 	fac.clen = fic->clen;
-	fac.off = 0;
+	fac.off = boot_get_image_start_offset(area_id);
 	fac.rbuf = ctx->buf;
 	fac.rblen = sizeof(ctx->buf);
 
diff --git a/subsys/fb/Kconfig b/subsys/fb/Kconfig
index 00be2ab08c0..6e4cf8b668a 100644
--- a/subsys/fb/Kconfig
+++ b/subsys/fb/Kconfig
@@ -23,14 +23,6 @@ config CHARACTER_FRAMEBUFFER_SHELL
 	  Activate shell module that provides Framebuffer commands to the
 	  console.
 
-config CHARACTER_FRAMEBUFFER_SHELL_DRIVER_NAME
-	string
-	default "SSD16XX" if SSD16XX
-	default "SSD1306" if SSD1306
-	depends on CHARACTER_FRAMEBUFFER_SHELL
-	help
-	  Character Framebuffer Display Driver Name
-
 module = CFB
 module-str = cfb
 source "subsys/logging/Kconfig.template.log_config"
diff --git a/subsys/fb/cfb.c b/subsys/fb/cfb.c
index d1e0cd6cf95..24cb8d3cc8d 100644
--- a/subsys/fb/cfb.c
+++ b/subsys/fb/cfb.c
@@ -67,7 +67,7 @@ struct char_framebuffer {
 
 static struct char_framebuffer char_fb;
 
-static inline uint8_t *get_glyph_ptr(const struct cfb_font *fptr, char c)
+static inline uint8_t *get_glyph_ptr(const struct cfb_font *fptr, uint8_t c)
 {
 	return (uint8_t *)fptr->data +
 	       (c - fptr->first_char) *
@@ -75,10 +75,14 @@ static inline uint8_t *get_glyph_ptr(const struct cfb_font *fptr, char c)
 }
 
 static inline uint8_t get_glyph_byte(uint8_t *glyph_ptr, const struct cfb_font *fptr,
-				     uint8_t x, uint8_t y)
+				     uint8_t x, uint8_t y, bool vtiled)
 {
 	if (fptr->caps & CFB_FONT_MONO_VPACKED) {
-		return glyph_ptr[x * (fptr->height / 8U) + y];
+		if (vtiled) {
+			return glyph_ptr[x * (fptr->height / 8U) + y];
+		} else {
+			return glyph_ptr[(x * fptr->height + y) / 8];
+		}
 	} else if (fptr->caps & CFB_FONT_MONO_HPACKED) {
 		return glyph_ptr[y * (fptr->width) + x];
 	}
@@ -92,7 +96,7 @@ static inline uint8_t get_glyph_byte(uint8_t *glyph_ptr, const struct cfb_font *
  * a byte is interpreted as 8 pixels ordered vertically among each other.
  */
 static uint8_t draw_char_vtmono(const struct char_framebuffer *fb,
-				char c, uint16_t x, uint16_t y,
+				uint8_t c, uint16_t x, uint16_t y,
 				bool draw_bg)
 {
 	const struct cfb_font *fptr = &(fb->fonts[fb->font_idx]);
@@ -140,10 +144,11 @@ static uint8_t draw_char_vtmono(const struct char_framebuffer *fb,
 				 * So, we process assume that nothing is drawn above.
 				 */
 				byte = 0;
-				next_byte = get_glyph_byte(glyph_ptr, fptr, g_x, g_y / 8);
+				next_byte = get_glyph_byte(glyph_ptr, fptr, g_x, g_y / 8, true);
 			} else {
-				byte = get_glyph_byte(glyph_ptr, fptr, g_x, g_y / 8);
-				next_byte = get_glyph_byte(glyph_ptr, fptr, g_x, (g_y + 8) / 8);
+				byte = get_glyph_byte(glyph_ptr, fptr, g_x, g_y / 8, true);
+				next_byte =
+					get_glyph_byte(glyph_ptr, fptr, g_x, (g_y + 8) / 8, true);
 			}
 
 			if (font_is_msbfirst) {
@@ -209,6 +214,62 @@ static uint8_t draw_char_vtmono(const struct char_framebuffer *fb,
 	return fptr->width;
 }
 
+/*
+ * Draw the monochrome character in the monochrome tiled framebuffer,
+ * a byte is interpreted as 8 pixels ordered horizontally among each other.
+ */
+static uint8_t draw_char_htmono(const struct char_framebuffer *fb,
+				uint8_t c, uint16_t x, uint16_t y,
+				bool draw_bg)
+{
+	const struct cfb_font *fptr = &(fb->fonts[fb->font_idx]);
+	const bool font_is_msbfirst = (fptr->caps & CFB_FONT_MSB_FIRST) != 0;
+	const bool display_is_msbfirst = (fb->screen_info & SCREEN_INFO_MONO_MSB_FIRST) != 0;
+	uint8_t *glyph_ptr;
+
+	if (c < fptr->first_char || c > fptr->last_char) {
+		c = ' ';
+	}
+
+	glyph_ptr = get_glyph_ptr(fptr, c);
+	if (!glyph_ptr) {
+		return 0;
+	}
+
+	for (size_t g_y = 0; g_y < fptr->height; g_y++) {
+		const int16_t fb_y = y + g_y;
+
+		for (size_t g_x = 0; g_x < fptr->width; g_x++) {
+			const int16_t fb_x = x + g_x;
+			const size_t fb_pixel_index = fb_y * fb->x_res + fb_x;
+			const size_t fb_byte_index = fb_pixel_index / 8;
+			uint8_t byte;
+			uint8_t pixel_value;
+
+			if (fb_x < 0 || fb->x_res <= fb_x || fb_y < 0 || fb->y_res <= fb_y) {
+				g_y++;
+				continue;
+			}
+
+			byte = get_glyph_byte(glyph_ptr, fptr, g_x, g_y, false);
+			if (font_is_msbfirst) {
+				byte = byte_reverse(byte);
+			}
+			pixel_value = byte & BIT(g_y % 8);
+
+			if (pixel_value) {
+				if (display_is_msbfirst) {
+					fb->buf[fb_byte_index] |= BIT(7 - (fb_x % 8));
+				} else {
+					fb->buf[fb_byte_index] |= BIT(fb_x % 8);
+				}
+			}
+		}
+	}
+
+	return fptr->width;
+}
+
 static inline void draw_point(struct char_framebuffer *fb, int16_t x, int16_t y)
 {
 	const bool need_reverse = ((fb->screen_info & SCREEN_INFO_MONO_MSB_FIRST) != 0);
@@ -277,21 +338,20 @@ static int draw_text(const struct device *dev, const char *const str, int16_t x,
 		return -EINVAL;
 	}
 
-	if ((fb->screen_info & SCREEN_INFO_MONO_VTILED)) {
-		const size_t len = strlen(str);
+	const size_t len = strlen(str);
 
-		for (size_t i = 0; i < len; i++) {
-			if ((x + fptr->width > fb->x_res) && wrap) {
-				x = 0U;
-				y += fptr->height;
-			}
+	for (size_t i = 0; i < len; i++) {
+		if ((x + fptr->width > fb->x_res) && wrap) {
+			x = 0U;
+			y += fptr->height;
+		}
+		if (fb->screen_info & SCREEN_INFO_MONO_VTILED) {
 			x += fb->kerning + draw_char_vtmono(fb, str[i], x, y, wrap);
+		} else {
+			x += fb->kerning + draw_char_htmono(fb, str[i], x, y, wrap);
 		}
-		return 0;
 	}
-
-	LOG_ERR("Unsupported framebuffer configuration");
-	return -EINVAL;
+	return 0;
 }
 
 int cfb_draw_point(const struct device *dev, const struct cfb_position *pos)
@@ -477,7 +537,7 @@ int cfb_framebuffer_finalize(const struct device *dev)
 		.pitch = fb->x_res,
 	};
 
-	if (!(fb->pixel_format & PIXEL_FORMAT_MONO10) != !(fb->inverted)) {
+	if ((fb->pixel_format == PIXEL_FORMAT_MONO10) == fb->inverted) {
 		cfb_invert(fb);
 		err = api->write(dev, 0, 0, &desc, fb->buf);
 		cfb_invert(fb);
@@ -493,7 +553,7 @@ int cfb_get_display_parameter(const struct device *dev,
 	const struct char_framebuffer *fb = &char_fb;
 
 	switch (param) {
-	case CFB_DISPLAY_HEIGH:
+	case CFB_DISPLAY_HEIGHT:
 		return fb->y_res;
 	case CFB_DISPLAY_WIDTH:
 		return fb->x_res;
diff --git a/subsys/fb/cfb_shell.c b/subsys/fb/cfb_shell.c
index 571c4dc3c58..7d63c10b893 100644
--- a/subsys/fb/cfb_shell.c
+++ b/subsys/fb/cfb_shell.c
@@ -18,7 +18,7 @@
 #define HELP_NONE "[none]"
 #define HELP_INIT "call \"cfb init\" first"
 #define HELP_PRINT "<col: pos> <row: pos> \"<text>\""
-#define HELP_DRAW_POINT "<x> <y0>"
+#define HELP_DRAW_POINT "<x> <y>"
 #define HELP_DRAW_LINE "<x0> <y0> <x1> <y1>"
 #define HELP_DRAW_RECT "<x0> <y0> <x1> <y1>"
 #define HELP_INVERT "[<x> <y> <width> <height>]"
@@ -282,7 +282,7 @@ static int cmd_set_font(const struct shell *sh, size_t argc, char *argv[])
 		return err;
 	}
 
-	shell_print(sh, "Font idx=%d height=%d widht=%d set", idx, height,
+	shell_print(sh, "Font idx=%d height=%d width=%d set", idx, height,
 		    width);
 
 	return err;
@@ -396,8 +396,8 @@ static int cmd_get_param_height(const struct shell *sh, size_t argc,
 	ARG_UNUSED(argc);
 	ARG_UNUSED(argv);
 
-	shell_print(sh, "param: %s=%d", param_name[CFB_DISPLAY_HEIGH],
-		    cfb_get_display_parameter(dev, CFB_DISPLAY_HEIGH));
+	shell_print(sh, "param: %s=%d", param_name[CFB_DISPLAY_HEIGHT],
+		    cfb_get_display_parameter(dev, CFB_DISPLAY_HEIGHT));
 
 	return 0;
 }
diff --git a/subsys/fs/CMakeLists.txt b/subsys/fs/CMakeLists.txt
index 15f97649a13..48df605ae01 100644
--- a/subsys/fs/CMakeLists.txt
+++ b/subsys/fs/CMakeLists.txt
@@ -36,9 +36,12 @@ if(CONFIG_FUSE_FS_ACCESS)
   zephyr_include_directories(${FUSE_INCLUDE_DIRS})
   if (CONFIG_NATIVE_LIBRARY)
     target_link_options(native_simulator INTERFACE "-l${FUSE_LIBRARIES}")
+    target_sources(native_simulator INTERFACE fuse_fs_access_bottom.c)
+    target_compile_options(native_simulator INTERFACE "-D_FILE_OFFSET_BITS=64")
   else()
     zephyr_link_libraries(${FUSE_LIBRARIES})
+    zephyr_library_sources(fuse_fs_access_bottom.c)
+    zephyr_library_compile_definitions(_FILE_OFFSET_BITS=64)
   endif()
-  zephyr_library_compile_definitions(_FILE_OFFSET_BITS=64)
   zephyr_library_sources(fuse_fs_access.c)
 endif()
diff --git a/subsys/fs/Kconfig b/subsys/fs/Kconfig
index ed3ead2f841..4dde4b27100 100644
--- a/subsys/fs/Kconfig
+++ b/subsys/fs/Kconfig
@@ -22,18 +22,6 @@ config FILE_SYSTEM
 
 if FILE_SYSTEM
 
-module = FS
-module-str = fs
-source "subsys/logging/Kconfig.template.log_config"
-
-config APP_LINK_WITH_FS
-	bool "Link 'app' with FS"
-	default y
-	help
-	  Add FS header files to the 'app' include path. It may be
-	  disabled if the include paths for FS are causing aliasing
-	  issues for 'app'.
-
 config FILE_SYSTEM_MAX_TYPES
 	int "Maximum number of distinct file system types allowed"
 	default 2
@@ -107,14 +95,32 @@ config FILE_SYSTEM_MKFS
 config FUSE_FS_ACCESS
 	bool "FUSE based access to file system partitions"
 	depends on ARCH_POSIX
+	select NATIVE_USE_NSI_ERRNO
 	help
 	  Expose file system partitions to the host system through FUSE.
 
+endif # FILE_SYSTEM
+
+if FILE_SYSTEM_LIB_LINK
+
+config APP_LINK_WITH_FS
+	bool "Link 'app' with FS"
+	default y
+	help
+	  Add FS header files to the 'app' include path. It may be
+	  disabled if the include paths for FS are causing aliasing
+	  issues for 'app'.
+
+# Logging defined here as modules/fs/littlefs/lfs.c expects CONFIG_FS_LOG_LEVEL
+module = FS
+module-str = fs
+source "subsys/logging/Kconfig.template.log_config"
+
 rsource "Kconfig.fatfs"
 rsource "Kconfig.littlefs"
 rsource "ext2/Kconfig"
 
-endif # FILE_SYSTEM
+endif # FILE_SYSTEM_LIB_LINK
 
 rsource "fcb/Kconfig"
 rsource "nvs/Kconfig"
diff --git a/subsys/fs/Kconfig.fatfs b/subsys/fs/Kconfig.fatfs
index 59bf3f7aa2d..ee0ec6ab4f2 100644
--- a/subsys/fs/Kconfig.fatfs
+++ b/subsys/fs/Kconfig.fatfs
@@ -5,7 +5,7 @@
 
 config FAT_FILESYSTEM_ELM
 	bool "ELM FAT file system support"
-	depends on FILE_SYSTEM
+	depends on FILE_SYSTEM_LIB_LINK
 	select DISK_ACCESS
 	help
 	  Use the ELM FAT File system implementation.
@@ -277,6 +277,36 @@ config FS_FATFS_MULTI_PARTITION
 	  physical drive number and only an FAT volume found on the physical drive
 	  will be mounted.
 
+config FS_FATFS_CUSTOM_MOUNT_POINT_COUNT
+	int "Count of custom mount points"
+	default 0
+	range 0 10
+	help
+	  This option has to be used in combination with FS_FATFS_CUSTOM_MOUNT_POINTS.
+	  It specifies how many custom mount points are defined in the custom mount
+	  point string.
+
+config FS_FATFS_CUSTOM_MOUNT_POINTS
+	string "Support for custom mountpoints when using fatfs"
+	help
+	   This option allows to specify custom mount points where fatfs filesystems
+	   can be mounted. The option has to be defined as a comma separated list
+	   with no whitespaces and no trailing commas.
+	   Example: "RAM,SD,SD2,NAND".
+	   It is also necessary to define the count of mount points specified in the
+	   list with the option FS_FATFS_CUSTOM_MOUNT_POINT_COUNT.
+	   If this option is active no mount points not defined within the list can
+	   be used for mounting fatfs filesystems anymore.
+	depends on FS_FATFS_CUSTOM_MOUNT_POINT_COUNT > 0
+
+DT_COMPAT_ZEPHYR_FSTAB_FATFS := zephyr,fstab,fatfs
+config FS_FATFS_FSTAB_AUTOMOUNT
+	bool "Support for fstab auto-mounting"
+	depends on $(dt_compat_enabled,$(DT_COMPAT_ZEPHYR_FSTAB_FATFS))
+	help
+	  This option enables fatfs support for the devicetree fstab auto-mounting
+	  functionality.
+
 endmenu
 
 endif # FAT_FILESYSTEM_ELM
diff --git a/subsys/fs/Kconfig.littlefs b/subsys/fs/Kconfig.littlefs
index bef620ed715..b7e1c4bf8d4 100644
--- a/subsys/fs/Kconfig.littlefs
+++ b/subsys/fs/Kconfig.littlefs
@@ -5,7 +5,7 @@
 
 config FILE_SYSTEM_LITTLEFS
 	bool "LittleFS support"
-	depends on FILE_SYSTEM
+	depends on FILE_SYSTEM_LIB_LINK
 	depends on ZEPHYR_LITTLEFS_MODULE
 	help
 	  Enables LittleFS file system support.
@@ -56,8 +56,7 @@ config FS_LITTLEFS_LOOKAHEAD_SIZE
 	help
 	  A larger lookahead buffer increases the number of blocks found
 	  during an allocation pass. The lookahead buffer is stored as a
-	  compact bitmap, so each byte of RAM can track 8 blocks. Must
-	  be a multiple of 8.
+	  compact bitmap, so each byte of RAM can track 8 blocks.
 
 config FS_LITTLEFS_BLOCK_CYCLES
 	int "Number of erase cycles before moving data to another block"
diff --git a/subsys/fs/ext2/CMakeLists.txt b/subsys/fs/ext2/CMakeLists.txt
index e66c8895a4c..8bb69eb2e13 100644
--- a/subsys/fs/ext2/CMakeLists.txt
+++ b/subsys/fs/ext2/CMakeLists.txt
@@ -6,12 +6,12 @@ target_include_directories(EXT2 INTERFACE ${CMAKE_CURRENT_SOURCE_DIR})
 
 zephyr_library()
 zephyr_library_sources(
-  ext2_ops.c
   ext2_impl.c
   ext2_disk_access.c
   ext2_bitmap.c
   ext2_diskops.c
 )
+zephyr_library_sources_ifdef(CONFIG_FILE_SYSTEM ext2_ops.c)
 zephyr_library_sources_ifdef(CONFIG_FILE_SYSTEM_MKFS ext2_format.c)
 
 zephyr_library_link_libraries(EXT2)
diff --git a/subsys/fs/ext2/Kconfig b/subsys/fs/ext2/Kconfig
index 9633a595b61..83ebd62f9a7 100644
--- a/subsys/fs/ext2/Kconfig
+++ b/subsys/fs/ext2/Kconfig
@@ -5,7 +5,7 @@
 
 config FILE_SYSTEM_EXT2
 	bool "Ext2 file system support"
-	depends on FILE_SYSTEM
+	depends on FILE_SYSTEM_LIB_LINK
 	help
 	  Enable Ext2 file system support.
 
@@ -18,7 +18,7 @@ if FILE_SYSTEM_EXT2
 menu "Ext2 file system Settings"
 	visible if FILE_SYSTEM_EXT2
 
-config MAX_FILES
+config EXT2_MAX_FILES
 	int "Maximum number of opened inodes"
 	default 10
 
diff --git a/subsys/fs/ext2/ext2_disk_access.c b/subsys/fs/ext2/ext2_disk_access.c
index 96ded31f8e3..c068473dc2f 100644
--- a/subsys/fs/ext2/ext2_disk_access.c
+++ b/subsys/fs/ext2/ext2_disk_access.c
@@ -23,7 +23,7 @@ static int64_t disk_access_device_size(struct ext2_data *fs)
 {
 	struct disk_data *disk = fs->backend;
 
-	return disk->sector_count * disk->sector_size;
+	return (uint64_t)disk->sector_count * (uint64_t)disk->sector_size;
 }
 
 static int64_t disk_access_write_size(struct ext2_data *fs)
diff --git a/subsys/fs/ext2/ext2_impl.c b/subsys/fs/ext2/ext2_impl.c
index 201e8cd92cb..a0b49415ec9 100644
--- a/subsys/fs/ext2/ext2_impl.c
+++ b/subsys/fs/ext2/ext2_impl.c
@@ -630,7 +630,7 @@ ssize_t ext2_inode_read(struct ext2_inode *inode, void *buf, uint32_t offset, si
 		memcpy((uint8_t *)buf + read, inode_current_block_mem(inode) + block_off, to_read);
 
 		read += to_read;
-		nbytes_to_read -= read;
+		nbytes_to_read -= to_read;
 		offset += to_read;
 	}
 
@@ -954,7 +954,7 @@ static int ext2_add_direntry(struct ext2_inode *dir, struct ext2_direntry *entry
 	}
 
 	uint32_t offset = 0;
-	uint16_t reclen;
+	uint16_t reclen = 0;
 
 	struct ext2_disk_direntry *de = 0;
 
diff --git a/subsys/fs/ext2/ext2_ops.c b/subsys/fs/ext2/ext2_ops.c
index 10acb8c891e..509a1c1b73d 100644
--- a/subsys/fs/ext2/ext2_ops.c
+++ b/subsys/fs/ext2/ext2_ops.c
@@ -18,7 +18,8 @@
 
 LOG_MODULE_DECLARE(ext2);
 
-K_MEM_SLAB_DEFINE(file_struct_slab, sizeof(struct ext2_file), CONFIG_MAX_FILES, sizeof(void *));
+K_MEM_SLAB_DEFINE(file_struct_slab, sizeof(struct ext2_file), CONFIG_EXT2_MAX_FILES,
+		  sizeof(void *));
 
 /* File operations */
 
@@ -28,7 +29,7 @@ static int ext2_open(struct fs_file_t *filp, const char *fs_path, fs_mode_t flag
 	struct ext2_file *file;
 	struct ext2_data *fs = filp->mp->fs_data;
 
-	if (fs->open_files >= CONFIG_MAX_FILES) {
+	if (fs->open_files >= CONFIG_EXT2_MAX_FILES) {
 		LOG_DBG("Too many open files");
 		return -EMFILE;
 	}
diff --git a/subsys/fs/ext2/ext2_struct.h b/subsys/fs/ext2/ext2_struct.h
index f2805752140..64c8c5a255f 100644
--- a/subsys/fs/ext2/ext2_struct.h
+++ b/subsys/fs/ext2/ext2_struct.h
@@ -224,7 +224,7 @@ struct ext2_backend_ops {
 	int (*sync)(struct ext2_data *fs);
 };
 
-#define MAX_INODES (CONFIG_MAX_FILES + 2)
+#define MAX_INODES (CONFIG_EXT2_MAX_FILES + 2)
 
 struct ext2_data {
 	struct ext2_superblock sblock; /* superblock */
diff --git a/subsys/fs/fat_fs.c b/subsys/fs/fat_fs.c
index 20367a811a3..016c23ac9cb 100644
--- a/subsys/fs/fat_fs.c
+++ b/subsys/fs/fat_fs.c
@@ -557,10 +557,82 @@ static const struct fs_file_system_t fatfs_fs = {
 #endif
 };
 
+#define DT_DRV_COMPAT zephyr_fstab_fatfs
+
+#define DEFINE_FS(inst)                                                                            \
+	BUILD_ASSERT(DT_INST_PROP(inst, disk_access), "FATFS needs disk-access");                  \
+	BUILD_ASSERT(!DT_INST_PROP(inst, read_only),                                               \
+		     "READ_ONLY not supported for individual instances see FS_FATFS_READ_ONLY");   \
+	BUILD_ASSERT(!DT_INST_PROP(inst, no_format),                                               \
+		     "NO_FORMAT not supported for individual instanzes FS_FATFS_MKFS");            \
+	static FATFS fs_data_##inst;                                                               \
+	struct fs_mount_t FS_FSTAB_ENTRY(DT_DRV_INST(inst)) = {                                    \
+		.type = FS_FATFS,                                                                  \
+		.mnt_point = DT_INST_PROP(inst, mount_point),                                      \
+		.fs_data = &fs_data_##inst,                                                        \
+		.storage_dev = NULL,                                                               \
+		.flags = FSTAB_ENTRY_DT_MOUNT_FLAGS(DT_DRV_INST(inst)),                            \
+	};
+
+DT_INST_FOREACH_STATUS_OKAY(DEFINE_FS);
+
+#ifdef CONFIG_FS_FATFS_FSTAB_AUTOMOUNT
+#define REFERENCE_MOUNT(inst) (&FS_FSTAB_ENTRY(DT_DRV_INST(inst))),
+
+static void automount_if_enabled(struct fs_mount_t *mountp)
+{
+	int ret = 0;
+
+	if ((mountp->flags & FS_MOUNT_FLAG_AUTOMOUNT) != 0) {
+		ret = fs_mount(mountp);
+		if (ret < 0) {
+			LOG_ERR("Error mounting filesystem: at %s: %d", mountp->mnt_point, ret);
+		} else {
+			LOG_DBG("FATFS Filesystem \"%s\" initialized", mountp->mnt_point);
+		}
+	}
+}
+#endif /* CONFIG_FS_FATFS_FSTAB_AUTOMOUNT */
+
+#if CONFIG_FS_FATFS_CUSTOM_MOUNT_POINT_COUNT
+const char *VolumeStr[CONFIG_FS_FATFS_CUSTOM_MOUNT_POINT_COUNT];
+#endif /* CONFIG_FS_FATFS_CUSTOM_MOUNT_POINT_COUNT */
+
 static int fatfs_init(void)
 {
+#if CONFIG_FS_FATFS_CUSTOM_MOUNT_POINT_COUNT
+	static char mount_points[] = CONFIG_FS_FATFS_CUSTOM_MOUNT_POINTS;
+	int mount_point_count = 0;
+
+	VolumeStr[0] = mount_points;
+	for (int i = 0; i < ARRAY_SIZE(mount_points) - 1; i++) {
+		if (mount_points[i] == ',') {
+			mount_points[i] = 0;
+			mount_point_count++;
+			if (mount_point_count >= ARRAY_SIZE(VolumeStr)) {
+				LOG_ERR("Mount point count not sufficient for defined mount "
+					"points.");
+				return -1;
+			}
+			VolumeStr[mount_point_count] = &mount_points[i + 1];
+		}
+	}
+#endif /* CONFIG_FS_FATFS_CUSTOM_MOUNT_POINT_COUNT */
+	int rc = fs_register(FS_FATFS, &fatfs_fs);
+
+#ifdef CONFIG_FS_FATFS_FSTAB_AUTOMOUNT
+	if (rc == 0) {
+		struct fs_mount_t *partitions[] = {DT_INST_FOREACH_STATUS_OKAY(REFERENCE_MOUNT)};
+
+		for (size_t i = 0; i < ARRAY_SIZE(partitions); i++) {
+			struct fs_mount_t *mpi = partitions[i];
+
+			automount_if_enabled(mpi);
+		}
+	}
+#endif /* CONFIG_FS_FATFS_FSTAB_AUTOMOUNT */
 
-	return fs_register(FS_FATFS, &fatfs_fs);
+	return rc;
 }
 
 SYS_INIT(fatfs_init, POST_KERNEL, CONFIG_FILE_SYSTEM_INIT_PRIORITY);
diff --git a/subsys/fs/fs.c b/subsys/fs/fs.c
index 37781535f32..5df0c13236b 100644
--- a/subsys/fs/fs.c
+++ b/subsys/fs/fs.c
@@ -16,10 +16,8 @@
 #include <zephyr/fs/fs_sys.h>
 #include <zephyr/sys/check.h>
 
-
-#define LOG_LEVEL CONFIG_FS_LOG_LEVEL
 #include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(fs);
+LOG_MODULE_REGISTER(fs, CONFIG_FS_LOG_LEVEL);
 
 /* list of mounted file systems */
 static sys_dlist_t fs_mnt_list = SYS_DLIST_STATIC_INIT(&fs_mnt_list);
@@ -686,7 +684,7 @@ int fs_mount(struct fs_mount_t *mp)
 
 	len = strlen(mp->mnt_point);
 
-	if ((len <= 1) || (mp->mnt_point[0] != '/')) {
+	if ((len == 0) || (mp->mnt_point[0] != '/')) {
 		LOG_ERR("invalid mount point!!");
 		return -EINVAL;
 	}
diff --git a/subsys/fs/fuse_fs_access.c b/subsys/fs/fuse_fs_access.c
index 9ecc2eddb4b..e4c26511c64 100644
--- a/subsys/fs/fuse_fs_access.c
+++ b/subsys/fs/fuse_fs_access.c
@@ -1,46 +1,24 @@
 /*
  * Copyright (c) 2019 Jan Van Winkel <jan.van_winkel@dxplore.eu>
+ * Copyright (c) 2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#define FUSE_USE_VERSION 26
-
-#undef _XOPEN_SOURCE
-#define _XOPEN_SOURCE 700
-
-#include <fuse.h>
-#include <libgen.h>
-#include <linux/limits.h>
-#include <unistd.h>
-#include <pthread.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <sys/mount.h>
-#include <sys/stat.h>
-#include <sys/time.h>
-#include <sys/types.h>
-
 #include <zephyr/kernel.h>
 #include <zephyr/fs/fs.h>
+#include <nsi_errno.h>
 
 #include "cmdline.h"
 #include "soc.h"
 
-#define S_IRWX_DIR (0775)
-#define S_IRW_FILE (0664)
+#include "fuse_fs_access_bottom.h"
 
 #define NUMBER_OF_OPEN_FILES 128
-#define INVALID_FILE_HANDLE (NUMBER_OF_OPEN_FILES + 1)
-
-#define DIR_END '\0'
 
 static struct fs_file_t files[NUMBER_OF_OPEN_FILES];
 static uint8_t file_handles[NUMBER_OF_OPEN_FILES];
 
-static pthread_t fuse_thread;
-
 static const char default_fuse_mountpoint[] = "flash";
 
 static const char *fuse_mountpoint;
@@ -66,427 +44,221 @@ static void release_file_handle(size_t handle)
 	}
 }
 
-static bool is_mount_point(const char *path)
-{
-	char dir_path[PATH_MAX];
-	size_t len;
-
-	len = strlen(path);
-	if (len >=  sizeof(dir_path)) {
-		return false;
-	}
-
-	memcpy(dir_path, path, len);
-	dir_path[len] = '\0';
-	return strcmp(dirname(dir_path), "/") == 0;
-}
-
-static int fuse_fs_access_getattr(const char *path, struct stat *stat)
+static int ffa_stat_top(const char *path, struct ffa_dirent *entry_bottom)
 {
 	struct fs_dirent entry;
 	int err;
 
-	stat->st_dev = 0;
-	stat->st_ino = 0;
-	stat->st_nlink = 0;
-	stat->st_uid = getuid();
-	stat->st_gid = getgid();
-	stat->st_rdev = 0;
-	stat->st_blksize = 0;
-	stat->st_blocks = 0;
-	stat->st_atime = 0;
-	stat->st_mtime = 0;
-	stat->st_ctime = 0;
-
-	if ((strcmp(path, "/") == 0) || is_mount_point(path)) {
-		if (strstr(path, "/.") != NULL) {
-			return -ENOENT;
-		}
-		stat->st_mode = S_IFDIR | S_IRWX_DIR;
-		stat->st_size = 0;
-		return 0;
-	}
-
 	err = fs_stat(path, &entry);
+
 	if (err != 0) {
-		return err;
+		return nsi_errno_to_mid(-err);
 	}
 
+	entry_bottom->size = entry.size;
+
 	if (entry.type == FS_DIR_ENTRY_DIR) {
-		stat->st_mode = S_IFDIR | S_IRWX_DIR;
-		stat->st_size = 0;
+		entry_bottom->is_directory = true;
 	} else {
-		stat->st_mode = S_IFREG | S_IRW_FILE;
-		stat->st_size = entry.size;
+		entry_bottom->is_directory = false;
 	}
 
 	return 0;
 }
 
-static int fuse_fs_access_readmount(void *buf, fuse_fill_dir_t filler)
+static int ffa_readmount_top(int *mnt_nbr, const char **mnt_name)
 {
-	int mnt_nbr = 0;
-	const char *mnt_name;
-	struct stat stat;
-	int err;
+	int err = fs_readmount(mnt_nbr, mnt_name);
 
-	stat.st_dev = 0;
-	stat.st_ino = 0;
-	stat.st_nlink = 0;
-	stat.st_uid = getuid();
-	stat.st_gid = getgid();
-	stat.st_rdev = 0;
-	stat.st_atime = 0;
-	stat.st_mtime = 0;
-	stat.st_ctime = 0;
-	stat.st_mode = S_IFDIR | S_IRWX_DIR;
-	stat.st_size = 0;
-	stat.st_blksize = 0;
-	stat.st_blocks = 0;
-
-	filler(buf, ".", &stat, 0);
-	filler(buf, "..", NULL, 0);
-
-	do {
-		err = fs_readmount(&mnt_nbr, &mnt_name);
-		if (err < 0) {
-			break;
-		}
+	return nsi_errno_to_mid(-err);
+}
 
-		filler(buf, &mnt_name[1], &stat, 0);
+/* Status shared between readdir_* calls */
+static struct {
+	struct fs_dir_t dir;
+	struct fs_dirent entry;
+} readdir_status;
 
-	} while (true);
+static int ffa_readdir_start(const char *path)
+{
+	int err;
 
-	if (err == -ENOENT) {
-		err = 0;
-	}
+	fs_dir_t_init(&readdir_status.dir);
+	err = fs_opendir(&readdir_status.dir, path);
 
-	return err;
+	return nsi_errno_to_mid(-err);
 }
 
-static int fuse_fs_access_readdir(const char *path, void *buf,
-			      fuse_fill_dir_t filler, off_t off,
-			      struct fuse_file_info *fi)
+static int ffa_readdir_read_next(struct ffa_dirent *entry_bottom)
 {
-	struct fs_dir_t dir;
-	struct fs_dirent entry;
 	int err;
-	struct stat stat;
 
-	ARG_UNUSED(off);
-	ARG_UNUSED(fi);
+	err = fs_readdir(&readdir_status.dir, &readdir_status.entry);
 
-	if (strcmp(path, "/") == 0) {
-		return fuse_fs_access_readmount(buf, filler);
+	if (err) {
+		return nsi_errno_to_mid(-err);
 	}
+	entry_bottom->name = readdir_status.entry.name;
+	entry_bottom->size = readdir_status.entry.size;
 
-	fs_dir_t_init(&dir);
-
-	if (is_mount_point(path)) {
-		/* File system API expects trailing slash for a mount point
-		 * directory but FUSE strips the trailing slashes from
-		 * directory names so add it back.
-		 */
-		char mount_path[PATH_MAX] = {0};
-		size_t len = strlen(path);
-
-		if (len >= (PATH_MAX - 2)) {
-			return -ENOMEM;
-		}
-
-		memcpy(mount_path, path, len);
-		mount_path[len] = '/';
-		err = fs_opendir(&dir, mount_path);
+	if (readdir_status.entry.type == FS_DIR_ENTRY_DIR) {
+		entry_bottom->is_directory = true;
 	} else {
-		err = fs_opendir(&dir, path);
+		entry_bottom->is_directory = false;
 	}
 
-	if (err) {
-		return -ENOEXEC;
-	}
-
-	stat.st_dev = 0;
-	stat.st_ino = 0;
-	stat.st_nlink = 0;
-	stat.st_uid = getuid();
-	stat.st_gid = getgid();
-	stat.st_rdev = 0;
-	stat.st_atime = 0;
-	stat.st_mtime = 0;
-	stat.st_ctime = 0;
-	stat.st_mode = S_IFDIR | S_IRWX_DIR;
-	stat.st_size = 0;
-	stat.st_blksize = 0;
-	stat.st_blocks = 0;
-
-	filler(buf, ".", &stat, 0);
-	filler(buf, "..", &stat, 0);
-
-	do {
-		err = fs_readdir(&dir, &entry);
-		if (err) {
-			break;
-		}
-
-		if (entry.name[0] == DIR_END) {
-			break;
-		}
-
-		if (entry.type == FS_DIR_ENTRY_DIR) {
-			stat.st_mode = S_IFDIR | S_IRWX_DIR;
-			stat.st_size = 0;
-		} else {
-			stat.st_mode = S_IFREG | S_IRW_FILE;
-			stat.st_size = entry.size;
-		}
-
-		if (filler(buf, entry.name, &stat, 0)) {
-			break;
-		}
-
-	} while (1);
-
-	fs_closedir(&dir);
-
-	return err;
+	return 0;
+}
 
+static void ffa_readdir_end(void)
+{
+	(void)fs_closedir(&readdir_status.dir);
 }
 
-static int fuse_fs_access_create(const char *path, mode_t mode,
-			     struct fuse_file_info *fi)
+static int ffa_create_top(const char *path, uint64_t *fh)
 {
 	int err;
 	ssize_t handle;
 
-	ARG_UNUSED(mode);
-
-	if (is_mount_point(path)) {
-		return -ENOENT;
-	}
-
 	handle = get_new_file_handle();
 	if (handle < 0) {
-		return handle;
+		return nsi_errno_to_mid(-handle);
 	}
 
-	fi->fh = handle;
+	*fh = handle;
 
 	err = fs_open(&files[handle], path, FS_O_CREATE | FS_O_WRITE);
 	if (err != 0) {
 		release_file_handle(handle);
-		fi->fh = INVALID_FILE_HANDLE;
-		return err;
+		*fh = INVALID_FILE_HANDLE;
+		return nsi_errno_to_mid(-err);
 	}
 
 	return 0;
 }
 
-static int fuse_fs_access_open(const char *path, struct fuse_file_info *fi)
-{
-	return fuse_fs_access_create(path, 0, fi);
-}
-
-static int fuse_fs_access_release(const char *path, struct fuse_file_info *fi)
+static int ffa_release_top(uint64_t fh)
 {
-	ARG_UNUSED(path);
-
-	if (fi->fh == INVALID_FILE_HANDLE) {
-		return -EINVAL;
-	}
-
-	fs_close(&files[fi->fh]);
+	fs_close(&files[fh]);
 
-	release_file_handle(fi->fh);
+	release_file_handle(fh);
 
 	return 0;
 }
 
-static int fuse_fs_access_read(const char *path, char *buf, size_t size,
-		off_t off, struct fuse_file_info *fi)
+static int ffa_read_top(uint64_t fh, char *buf, size_t size, off_t off)
 {
 	int err;
 
-	ARG_UNUSED(path);
+	err = fs_seek(&files[fh], off, FS_SEEK_SET);
 
-	if (fi->fh == INVALID_FILE_HANDLE) {
-		return -EINVAL;
+	if (err == 0) {
+		err = fs_read(&files[fh], buf, size);
 	}
 
-	err = fs_seek(&files[fi->fh], off, FS_SEEK_SET);
-	if (err != 0) {
-		return err;
-	}
-
-	err = fs_read(&files[fi->fh], buf, size);
-
-	return err;
+	return nsi_errno_to_mid(-err);
 }
 
-static int fuse_fs_access_write(const char *path, const char *buf, size_t size,
-		off_t off, struct fuse_file_info *fi)
+static int ffa_write_top(uint64_t fh, const char *buf, size_t size, off_t off)
 {
 	int err;
 
-	ARG_UNUSED(path);
+	err = fs_seek(&files[fh], off, FS_SEEK_SET);
 
-	if (fi->fh == INVALID_FILE_HANDLE) {
-		return -EINVAL;
+	if (err == 0) {
+		err = fs_write(&files[fh], buf, size);
 	}
 
-	err = fs_seek(&files[fi->fh], off, FS_SEEK_SET);
-	if (err != 0) {
-		return err;
-	}
-
-	err = fs_write(&files[fi->fh], buf, size);
-
-	return err;
+	return nsi_errno_to_mid(-err);
 }
 
-static int fuse_fs_access_ftruncate(const char *path, off_t size,
-				struct fuse_file_info *fi)
+static int ffa_ftruncate_top(uint64_t fh, off_t size)
 {
-	int err;
-
-	ARG_UNUSED(path);
-
-	if (fi->fh == INVALID_FILE_HANDLE) {
-		return -EINVAL;
-	}
+	int err = fs_truncate(&files[fh], size);
 
-	err = fs_truncate(&files[fi->fh], size);
-
-	return err;
+	return nsi_errno_to_mid(-err);
 }
 
-static int fuse_fs_access_truncate(const char *path, off_t size)
+static int ffa_truncate_top(const char *path, off_t size)
 {
 	int err;
 	static struct fs_file_t file;
 
 	err = fs_open(&file, path, FS_O_CREATE | FS_O_WRITE);
 	if (err != 0) {
-		return err;
+		return nsi_errno_to_mid(-err);
 	}
 
 	err = fs_truncate(&file, size);
 	if (err != 0) {
 		fs_close(&file);
-		return err;
+	} else {
+		err = fs_close(&file);
 	}
 
-	err = fs_close(&file);
-
-	return err;
-}
-
-static int fuse_fs_access_mkdir(const char *path, mode_t mode)
-{
-	ARG_UNUSED(mode);
-
-	return fs_mkdir(path);
+	return nsi_errno_to_mid(-err);
 }
 
-static int fuse_fs_access_rmdir(const char *path)
+static int ffa_mkdir_top(const char *path)
 {
-	return fs_unlink(path);
-}
+	int err = fs_mkdir(path);
 
-static int fuse_fs_access_unlink(const char *path)
-{
-	return fs_unlink(path);
-}
-
-static int fuse_fs_access_statfs(const char *path, struct statvfs *buf)
-{
-	ARG_UNUSED(path);
-	ARG_UNUSED(buf);
-	return 0;
+	return nsi_errno_to_mid(-err);
 }
 
-static int fuse_fs_access_utimens(const char *path, const struct timespec tv[2])
+static int ffa_unlink_top(const char *path)
 {
-	/* dummy */
-	ARG_UNUSED(path);
-	ARG_UNUSED(tv);
+	int err = fs_unlink(path);
 
-	return 0;
+	return nsi_errno_to_mid(-err);
 }
 
-
-static struct fuse_operations fuse_fs_access_oper = {
-	.getattr = fuse_fs_access_getattr,
-	.readlink = NULL,
-	.getdir = NULL,
-	.mknod = NULL,
-	.mkdir = fuse_fs_access_mkdir,
-	.unlink = fuse_fs_access_unlink,
-	.rmdir = fuse_fs_access_rmdir,
-	.symlink = NULL,
-	.rename = NULL,
-	.link = NULL,
-	.chmod = NULL,
-	.chown = NULL,
-	.truncate = fuse_fs_access_truncate,
-	.utime = NULL,
-	.open = fuse_fs_access_open,
-	.read = fuse_fs_access_read,
-	.write = fuse_fs_access_write,
-	.statfs = fuse_fs_access_statfs,
-	.flush = NULL,
-	.release = fuse_fs_access_release,
-	.fsync = NULL,
-	.setxattr = NULL,
-	.getxattr = NULL,
-	.listxattr = NULL,
-	.removexattr = NULL,
-	.opendir  = NULL,
-	.readdir = fuse_fs_access_readdir,
-	.releasedir = NULL,
-	.fsyncdir = NULL,
-	.init = NULL,
-	.destroy = NULL,
-	.access = NULL,
-	.create = fuse_fs_access_create,
-	.ftruncate = fuse_fs_access_ftruncate,
-	.fgetattr = NULL,
-	.lock = NULL,
-	.utimens = fuse_fs_access_utimens,
-	.bmap = NULL,
-	.flag_nullpath_ok = 0,
-	.flag_nopath = 0,
-	.flag_utime_omit_ok = 0,
-	.flag_reserved = 0,
-	.ioctl = NULL,
-	.poll = NULL,
-	.write_buf = NULL,
-	.read_buf = NULL,
-	.flock = NULL,
-	.fallocate = NULL,
+struct ffa_op_callbacks op_callbacks = {
+	.readdir_start = ffa_readdir_start,
+	.readdir_read_next = ffa_readdir_read_next,
+	.readdir_end = ffa_readdir_end,
+	.stat = ffa_stat_top,
+	.readmount = ffa_readmount_top,
+	.mkdir = ffa_mkdir_top,
+	.create = ffa_create_top,
+	.release = ffa_release_top,
+	.read = ffa_read_top,
+	.write = ffa_write_top,
+	.ftruncate = ffa_ftruncate_top,
+	.truncate = ffa_truncate_top,
+	.unlink = ffa_unlink_top,
+	.rmdir = ffa_unlink_top,
 };
 
-static void *fuse_fs_access_main(void *arg)
+static void fuse_top_dispath_thread(void *arg1, void *arg2, void *arg3)
 {
-	ARG_UNUSED(arg);
-
-	char *argv[] = {
-		"",
-		"-f",
-		"-s",
-		(char *) fuse_mountpoint
-	};
-	int argc = ARRAY_SIZE(argv);
+	ARG_UNUSED(arg1);
+	ARG_UNUSED(arg2);
+	ARG_UNUSED(arg3);
 
-	posix_print_trace("Mounting flash at %s/\n", fuse_mountpoint);
-	fuse_main(argc, argv, &fuse_fs_access_oper, NULL);
+#define COOLDOWN_TIME 10
+	int cooldown_count = 0;
 
-	pthread_exit(0);
+	while (true) {
+		if (ffa_is_op_pended()) {
+			ffa_run_pending_op();
+			cooldown_count = COOLDOWN_TIME;
+		} else {
+			if (cooldown_count > 0) {
+				k_sleep(K_MSEC(1));
+				cooldown_count--;
+			} else {
+				k_sleep(K_MSEC(20));
+			}
+		}
+	}
 }
 
+K_THREAD_DEFINE(fuse_op_handler, CONFIG_ARCH_POSIX_RECOMMENDED_STACK_SIZE,
+		fuse_top_dispath_thread, NULL, NULL, NULL, 100, 0, 0);
+
 static void fuse_fs_access_init(void)
 {
-	int err;
-	struct stat st;
 	size_t i = 0;
 
 	while (i < ARRAY_SIZE(files)) {
@@ -498,44 +270,16 @@ static void fuse_fs_access_init(void)
 		fuse_mountpoint = default_fuse_mountpoint;
 	}
 
-	if (stat(fuse_mountpoint, &st) < 0) {
-		if (mkdir(fuse_mountpoint, 0700) < 0) {
-			posix_print_error_and_exit("Failed to create"
-				" directory for flash mount point (%s): %s\n",
-				fuse_mountpoint, strerror(errno));
-		}
-	} else if (!S_ISDIR(st.st_mode)) {
-		posix_print_error_and_exit("%s is not a directory\n",
-					   fuse_mountpoint);
-
-	}
-
-	err = pthread_create(&fuse_thread, NULL, fuse_fs_access_main, NULL);
-	if (err < 0) {
-		posix_print_error_and_exit(
-					"Failed to create thread for "
-					"fuse_fs_access_main\n");
-	}
+	ffsa_init_bottom(fuse_mountpoint, &op_callbacks);
 }
 
-static void fuse_fs_access_exit(void)
+static void fuse_fs_access_cleanup(void)
 {
-	char *full_cmd;
-	const char cmd[] = "fusermount -uz ";
-
 	if (fuse_mountpoint == NULL) {
 		return;
 	}
 
-	full_cmd = malloc(strlen(cmd) + strlen(fuse_mountpoint) + 1);
-
-	sprintf(full_cmd, "%s%s", cmd, fuse_mountpoint);
-	if (system(full_cmd) < -1) {
-		printf("Failed to unmount fuse mount point\n");
-	}
-	free(full_cmd);
-
-	pthread_join(fuse_thread, NULL);
+	ffsa_cleanup_bottom(fuse_mountpoint);
 }
 
 static void fuse_fs_access_options(void)
@@ -558,4 +302,4 @@ static void fuse_fs_access_options(void)
 
 NATIVE_TASK(fuse_fs_access_options, PRE_BOOT_1, 1);
 NATIVE_TASK(fuse_fs_access_init, PRE_BOOT_2, 1);
-NATIVE_TASK(fuse_fs_access_exit, ON_EXIT, 1);
+NATIVE_TASK(fuse_fs_access_cleanup, ON_EXIT, 1);
diff --git a/subsys/fs/fuse_fs_access_bottom.c b/subsys/fs/fuse_fs_access_bottom.c
new file mode 100644
index 00000000000..e3d3cd8b96e
--- /dev/null
+++ b/subsys/fs/fuse_fs_access_bottom.c
@@ -0,0 +1,642 @@
+/*
+ * Copyright (c) 2019 Jan Van Winkel <jan.van_winkel@dxplore.eu>
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define FUSE_USE_VERSION 26
+
+#undef _XOPEN_SOURCE
+#define _XOPEN_SOURCE 700
+
+#include <stdbool.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include <limits.h>
+#include <pthread.h>
+#include <semaphore.h>
+#include <fuse.h>
+#include <libgen.h>
+#include <linux/limits.h>
+#include <unistd.h>
+#include <sys/mount.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include <sys/types.h>
+#include <nsi_tracing.h>
+#include <nsi_utils.h>
+#include <nsi_errno.h>
+#include "fuse_fs_access_bottom.h"
+
+
+#define S_IRWX_DIR (0775)
+#define S_IRW_FILE (0664)
+
+#define DIR_END '\0'
+
+static pthread_t fuse_thread;
+static struct ffa_op_callbacks *op_callbacks;
+
+/* Pending operation the bottom/fuse thread is queuing into the Zephyr thread */
+struct {
+	int op;        /* One of OP_**/
+	void *args;    /* Pointer to arguments structure, one of op_args_* or a simple argument */
+	int ret;       /* Return from the operation */
+	bool pending;  /* Is there a pending operation */
+	sem_t op_done; /* semaphore to signal the job is done */
+} op_queue;
+
+#define OP_STAT              offsetof(struct ffa_op_callbacks, stat)
+#define OP_READMOUNT         offsetof(struct ffa_op_callbacks, readmount)
+#define OP_READDIR_START     offsetof(struct ffa_op_callbacks, readdir_start)
+#define OP_READDIR_READ_NEXT offsetof(struct ffa_op_callbacks, readdir_read_next)
+#define OP_READDIR_END       offsetof(struct ffa_op_callbacks, readdir_end)
+#define OP_MKDIR             offsetof(struct ffa_op_callbacks, mkdir)
+#define OP_CREATE            offsetof(struct ffa_op_callbacks, create)
+#define OP_RELEASE           offsetof(struct ffa_op_callbacks, release)
+#define OP_READ              offsetof(struct ffa_op_callbacks, read)
+#define OP_WRITE             offsetof(struct ffa_op_callbacks, write)
+#define OP_FTRUNCATE         offsetof(struct ffa_op_callbacks, ftruncate)
+#define OP_TRUNCATE          offsetof(struct ffa_op_callbacks, truncate)
+#define OP_UNLINK            offsetof(struct ffa_op_callbacks, unlink)
+#define OP_RMDIR             offsetof(struct ffa_op_callbacks, rmdir)
+
+struct op_args_truncate {
+	const char *path;
+	off_t size;
+};
+struct op_args_ftruncate {
+	uint64_t fh;
+	off_t size;
+};
+struct op_args_readwrite {
+	uint64_t fh;
+	char *buf;
+	off_t size;
+	off_t off;
+};
+struct op_args_create {
+	const char *path;
+	uint64_t *fh_p;
+};
+struct op_args_readmount {
+	int *mnt_nbr_p;
+	const char **mnt_name_p;
+};
+struct op_args_stat {
+	const char *path;
+	struct ffa_dirent *entry_p;
+};
+
+static inline int queue_op(int op, void *args)
+{
+	op_queue.op = op;
+	op_queue.args = args;
+	op_queue.pending = true;
+
+	sem_wait(&op_queue.op_done);
+
+	return op_queue.ret;
+}
+
+bool ffa_is_op_pended(void)
+{
+	return op_queue.pending;
+}
+
+void ffa_run_pending_op(void)
+{
+	switch ((intptr_t)op_queue.op) {
+	case OP_RMDIR:
+		op_queue.ret = op_callbacks->rmdir((const char *)op_queue.args);
+		break;
+	case OP_UNLINK:
+		op_queue.ret = op_callbacks->unlink((const char *)op_queue.args);
+		break;
+	case OP_TRUNCATE: {
+		struct op_args_truncate *args = op_queue.args;
+
+		op_queue.ret = op_callbacks->truncate(args->path, args->size);
+		break;
+	}
+	case OP_FTRUNCATE: {
+		struct op_args_ftruncate *args = op_queue.args;
+
+		op_queue.ret = op_callbacks->ftruncate(args->fh, args->size);
+		break;
+	}
+	case OP_WRITE: {
+		struct op_args_readwrite *args = op_queue.args;
+
+		op_queue.ret = op_callbacks->write(args->fh, args->buf, args->size, args->off);
+		break;
+	}
+	case OP_READ: {
+		struct op_args_readwrite *args = op_queue.args;
+
+		op_queue.ret = op_callbacks->read(args->fh, args->buf, args->size, args->off);
+		break;
+	}
+	case OP_RELEASE:
+		op_queue.ret = op_callbacks->release(*(uint64_t *)op_queue.args);
+		break;
+	case OP_CREATE: {
+		struct op_args_create *args = op_queue.args;
+
+		op_queue.ret = op_callbacks->create(args->path, args->fh_p);
+		break;
+	}
+	case OP_MKDIR:
+		op_queue.ret = op_callbacks->mkdir((const char *)op_queue.args);
+		break;
+	case OP_READDIR_END:
+		op_callbacks->readdir_end();
+		break;
+	case OP_READDIR_READ_NEXT:
+		op_queue.ret = op_callbacks->readdir_read_next((struct ffa_dirent *)op_queue.args);
+		break;
+	case OP_READDIR_START:
+		op_queue.ret = op_callbacks->readdir_start((const char *)op_queue.args);
+		break;
+	case OP_READMOUNT: {
+		struct op_args_readmount *args = op_queue.args;
+
+		op_queue.ret = op_callbacks->readmount(args->mnt_nbr_p, args->mnt_name_p);
+		break;
+	}
+	case OP_STAT: {
+		struct op_args_stat *args = op_queue.args;
+
+		op_queue.ret = op_callbacks->stat(args->path, args->entry_p);
+		break;
+	}
+	default:
+		nsi_print_error_and_exit("Programming error, unknown queued operation\n");
+		break;
+	}
+	op_queue.pending = false;
+	sem_post(&op_queue.op_done);
+}
+
+static bool is_mount_point(const char *path)
+{
+	char dir_path[PATH_MAX];
+	size_t len;
+
+	len = strlen(path);
+	if (len >= sizeof(dir_path)) {
+		return false;
+	}
+
+	memcpy(dir_path, path, len);
+	dir_path[len] = '\0';
+	return strcmp(dirname(dir_path), "/") == 0;
+}
+
+static int fuse_fs_access_getattr(const char *path, struct stat *st)
+{
+	struct ffa_dirent entry;
+	int err;
+
+	st->st_dev = 0;
+	st->st_ino = 0;
+	st->st_nlink = 0;
+	st->st_uid = getuid();
+	st->st_gid = getgid();
+	st->st_rdev = 0;
+	st->st_blksize = 0;
+	st->st_blocks = 0;
+	st->st_atime = 0;
+	st->st_mtime = 0;
+	st->st_ctime = 0;
+
+	if ((strcmp(path, "/") == 0) || is_mount_point(path)) {
+		if (strstr(path, "/.") != NULL) {
+			return -ENOENT;
+		}
+		st->st_mode = S_IFDIR | S_IRWX_DIR;
+		st->st_size = 0;
+		return 0;
+	}
+
+	struct op_args_stat args;
+
+	args.path = path;
+	args.entry_p = &entry;
+
+	err = queue_op(OP_STAT, (void *)&args);
+
+	if (err != 0) {
+		return -nsi_errno_from_mid(err);
+	}
+
+	if (entry.is_directory) {
+		st->st_mode = S_IFDIR | S_IRWX_DIR;
+		st->st_size = 0;
+	} else {
+		st->st_mode = S_IFREG | S_IRW_FILE;
+		st->st_size = entry.size;
+	}
+
+	return 0;
+}
+
+static int fuse_fs_access_readmount(void *buf, fuse_fill_dir_t filler)
+{
+	int mnt_nbr = 0;
+	const char *mnt_name;
+	struct stat st;
+	int err;
+
+	st.st_dev = 0;
+	st.st_ino = 0;
+	st.st_nlink = 0;
+	st.st_uid = getuid();
+	st.st_gid = getgid();
+	st.st_rdev = 0;
+	st.st_atime = 0;
+	st.st_mtime = 0;
+	st.st_ctime = 0;
+	st.st_mode = S_IFDIR | S_IRWX_DIR;
+	st.st_size = 0;
+	st.st_blksize = 0;
+	st.st_blocks = 0;
+
+	filler(buf, ".", &st, 0);
+	filler(buf, "..", NULL, 0);
+
+	do {
+		struct op_args_readmount args;
+
+		args.mnt_nbr_p = &mnt_nbr;
+		args.mnt_name_p = &mnt_name;
+
+		err = queue_op(OP_READMOUNT, (void *)&args);
+		err = -nsi_errno_from_mid(err);
+
+		if (err < 0) {
+			break;
+		}
+
+		filler(buf, &mnt_name[1], &st, 0);
+
+	} while (true);
+
+	if (err == -ENOENT) {
+		err = 0;
+	}
+
+	return err;
+}
+
+static int fuse_fs_access_readdir(const char *path, void *buf, fuse_fill_dir_t filler, off_t off,
+				  struct fuse_file_info *fi)
+{
+	NSI_ARG_UNUSED(off);
+	NSI_ARG_UNUSED(fi);
+
+	struct ffa_dirent entry;
+	int err;
+	struct stat st;
+
+	if (strcmp(path, "/") == 0) {
+		err = fuse_fs_access_readmount(buf, filler);
+		return -nsi_errno_from_mid(err);
+	}
+
+	if (is_mount_point(path)) {
+		/* File system API expects trailing slash for a mount point
+		 * directory but FUSE strips the trailing slashes from
+		 * directory names so add it back.
+		 */
+		char mount_path[PATH_MAX] = {0};
+		size_t len = strlen(path);
+
+		if (len >= (PATH_MAX - 2)) {
+			return -ENOMEM;
+		}
+
+		memcpy(mount_path, path, len);
+		mount_path[len] = '/';
+		err = queue_op(OP_READDIR_START, (void *)mount_path);
+	} else {
+		err = queue_op(OP_READDIR_START, (void *)path);
+	}
+
+	if (err) {
+		return -ENOEXEC;
+	}
+
+	st.st_dev = 0;
+	st.st_ino = 0;
+	st.st_nlink = 0;
+	st.st_uid = getuid();
+	st.st_gid = getgid();
+	st.st_rdev = 0;
+	st.st_atime = 0;
+	st.st_mtime = 0;
+	st.st_ctime = 0;
+	st.st_mode = S_IFDIR | S_IRWX_DIR;
+	st.st_size = 0;
+	st.st_blksize = 0;
+	st.st_blocks = 0;
+
+	filler(buf, ".", &st, 0);
+	filler(buf, "..", &st, 0);
+
+	do {
+		err = queue_op(OP_READDIR_READ_NEXT, (void *)&entry);
+		if (err) {
+			break;
+		}
+
+		if (entry.name[0] == DIR_END) {
+			break;
+		}
+
+		if (entry.is_directory) {
+			st.st_mode = S_IFDIR | S_IRWX_DIR;
+			st.st_size = 0;
+		} else {
+			st.st_mode = S_IFREG | S_IRW_FILE;
+			st.st_size = entry.size;
+		}
+
+		if (filler(buf, entry.name, &st, 0)) {
+			break;
+		}
+	} while (1);
+
+	queue_op(OP_READDIR_END, NULL);
+
+	return -nsi_errno_from_mid(err);
+}
+
+static int fuse_fs_access_mkdir(const char *path, mode_t mode)
+{
+	NSI_ARG_UNUSED(mode);
+
+	int err = queue_op(OP_MKDIR, (void *)path);
+
+	return -nsi_errno_from_mid(err);
+}
+
+static int fuse_fs_access_create(const char *path, mode_t mode, struct fuse_file_info *fi)
+{
+	int err;
+	struct op_args_create args;
+
+	NSI_ARG_UNUSED(mode);
+
+	if (is_mount_point(path)) {
+		return -ENOENT;
+	}
+
+	args.path = path;
+	args.fh_p = &fi->fh;
+
+	err = queue_op(OP_CREATE, (void *)&args);
+
+	return -nsi_errno_from_mid(err);
+}
+
+static int fuse_fs_access_open(const char *path, struct fuse_file_info *fi)
+{
+	int err = fuse_fs_access_create(path, 0, fi);
+
+	return -nsi_errno_from_mid(err);
+}
+
+static int fuse_fs_access_release(const char *path, struct fuse_file_info *fi)
+{
+	NSI_ARG_UNUSED(path);
+
+	if (fi->fh == INVALID_FILE_HANDLE) {
+		return -EINVAL;
+	}
+
+	(void)queue_op(OP_RELEASE, (void *)&fi->fh);
+
+	return 0;
+}
+
+static int fuse_fs_access_read(const char *path, char *buf, size_t size, off_t off,
+			       struct fuse_file_info *fi)
+{
+	int err;
+	struct op_args_readwrite args;
+
+	NSI_ARG_UNUSED(path);
+
+	if (fi->fh == INVALID_FILE_HANDLE) {
+		return -EINVAL;
+	}
+
+	args.fh = fi->fh;
+	args.buf = buf;
+	args.size = size;
+	args.off = off;
+
+	err = queue_op(OP_READ, (void *)&args);
+
+	return -nsi_errno_from_mid(err);
+}
+
+static int fuse_fs_access_write(const char *path, const char *buf, size_t size, off_t off,
+				struct fuse_file_info *fi)
+{
+	int err;
+	struct op_args_readwrite args;
+
+	NSI_ARG_UNUSED(path);
+
+	if (fi->fh == INVALID_FILE_HANDLE) {
+		return -EINVAL;
+	}
+
+	args.fh = fi->fh;
+	args.buf = (char *)buf;
+	args.size = size;
+	args.off = off;
+
+	err = queue_op(OP_WRITE, (void *)&args);
+
+	return -nsi_errno_from_mid(err);
+}
+
+static int fuse_fs_access_ftruncate(const char *path, off_t size, struct fuse_file_info *fi)
+{
+	struct op_args_ftruncate args;
+	int err;
+
+	NSI_ARG_UNUSED(path);
+
+	if (fi->fh == INVALID_FILE_HANDLE) {
+		return -EINVAL;
+	}
+
+	args.fh = fi->fh;
+	args.size = size;
+
+	err = queue_op(OP_FTRUNCATE, (void *)&args);
+
+	return -nsi_errno_from_mid(err);
+}
+
+static int fuse_fs_access_truncate(const char *path, off_t size)
+{
+	struct op_args_truncate args;
+	int err;
+
+	args.path = path;
+	args.size = size;
+
+	err = queue_op(OP_TRUNCATE, (void *)&args);
+
+	return -nsi_errno_from_mid(err);
+}
+
+static int fuse_fs_access_rmdir(const char *path)
+{
+	int err = queue_op(OP_RMDIR, (void *)path);
+
+	return -nsi_errno_from_mid(err);
+}
+
+static int fuse_fs_access_unlink(const char *path)
+{
+	int err = queue_op(OP_UNLINK, (void *)path);
+
+	return -nsi_errno_from_mid(err);
+}
+
+static int fuse_fs_access_statfs(const char *path, struct statvfs *buf)
+{
+	NSI_ARG_UNUSED(path);
+	NSI_ARG_UNUSED(buf);
+	return 0;
+}
+
+static int fuse_fs_access_utimens(const char *path, const struct timespec tv[2])
+{
+	/* dummy */
+	NSI_ARG_UNUSED(path);
+	NSI_ARG_UNUSED(tv);
+	return 0;
+}
+
+static struct fuse_operations fuse_fs_access_oper = {
+	.getattr = fuse_fs_access_getattr,
+	.readlink = NULL,
+	.getdir = NULL,
+	.mknod = NULL,
+	.mkdir = fuse_fs_access_mkdir,
+	.unlink = fuse_fs_access_unlink,
+	.rmdir = fuse_fs_access_rmdir,
+	.symlink = NULL,
+	.rename = NULL,
+	.link = NULL,
+	.chmod = NULL,
+	.chown = NULL,
+	.truncate = fuse_fs_access_truncate,
+	.utime = NULL,
+	.open = fuse_fs_access_open,
+	.read = fuse_fs_access_read,
+	.write = fuse_fs_access_write,
+	.statfs = fuse_fs_access_statfs,
+	.flush = NULL,
+	.release = fuse_fs_access_release,
+	.fsync = NULL,
+	.setxattr = NULL,
+	.getxattr = NULL,
+	.listxattr = NULL,
+	.removexattr = NULL,
+	.opendir = NULL,
+	.readdir = fuse_fs_access_readdir,
+	.releasedir = NULL,
+	.fsyncdir = NULL,
+	.init = NULL,
+	.destroy = NULL,
+	.access = NULL,
+	.create = fuse_fs_access_create,
+	.ftruncate = fuse_fs_access_ftruncate,
+	.fgetattr = NULL,
+	.lock = NULL,
+	.utimens = fuse_fs_access_utimens,
+	.bmap = NULL,
+	.flag_nullpath_ok = 0,
+	.flag_nopath = 0,
+	.flag_utime_omit_ok = 0,
+	.flag_reserved = 0,
+	.ioctl = NULL,
+	.poll = NULL,
+	.write_buf = NULL,
+	.read_buf = NULL,
+	.flock = NULL,
+	.fallocate = NULL,
+};
+
+static void *ffsa_main(void *fuse_mountpoint)
+{
+	char *argv[] = {
+		"",
+		"-f",
+		"-s",
+		(char *)fuse_mountpoint
+	};
+	int argc = NSI_ARRAY_SIZE(argv);
+
+	nsi_print_trace("FUSE mounting flash in host %s/\n", (char *)fuse_mountpoint);
+
+	fuse_main(argc, argv, &fuse_fs_access_oper, NULL);
+
+	pthread_exit(0);
+	return NULL;
+}
+
+void ffsa_init_bottom(const char *fuse_mountpoint, struct ffa_op_callbacks *op_cbs)
+{
+	struct stat st;
+	int err;
+
+	op_callbacks = op_cbs;
+
+	if (stat(fuse_mountpoint, &st) < 0) {
+		if (mkdir(fuse_mountpoint, 0700) < 0) {
+			nsi_print_error_and_exit("Failed to create directory for flash mount point "
+						 "(%s): %s\n",
+						 fuse_mountpoint, strerror(errno));
+		}
+	} else if (!S_ISDIR(st.st_mode)) {
+		nsi_print_error_and_exit("%s is not a directory\n", fuse_mountpoint);
+	}
+
+	err = pthread_create(&fuse_thread, NULL, ffsa_main, (void *)fuse_mountpoint);
+	if (err < 0) {
+		nsi_print_error_and_exit("Failed to create thread for fuse_fs_access_main\n");
+	}
+
+	err = sem_init(&op_queue.op_done, 0, 0);
+	if (err) {
+		nsi_print_error_and_exit("Failed to initialize semaphore\n");
+	}
+}
+
+void ffsa_cleanup_bottom(const char *fuse_mountpoint)
+{
+	char *full_cmd;
+	static const char cmd[] = "fusermount -uz ";
+
+	full_cmd = malloc(strlen(cmd) + strlen(fuse_mountpoint) + 1);
+
+	sprintf(full_cmd, "%s%s", cmd, fuse_mountpoint);
+	if (system(full_cmd) < -1) {
+		nsi_print_trace("Failed to unmount fuse mount point\n");
+	}
+	free(full_cmd);
+
+	pthread_join(fuse_thread, NULL);
+}
diff --git a/subsys/fs/fuse_fs_access_bottom.h b/subsys/fs/fuse_fs_access_bottom.h
new file mode 100644
index 00000000000..93d198c09ea
--- /dev/null
+++ b/subsys/fs/fuse_fs_access_bottom.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef SUBSYS_FS_FUSE_FS_ACCESS_BOTTOM_H
+#define SUBSYS_FS_FUSE_FS_ACCESS_BOTTOM_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define INVALID_FILE_HANDLE (INT32_MAX)
+
+struct ffa_dirent {
+	bool is_directory;
+	char *name;
+	size_t size;
+};
+
+struct ffa_op_callbacks {
+	int (*stat)(const char *path, struct ffa_dirent *entry);
+	int (*readmount)(int *mnt_nbr, const char **mnt_name);
+	int (*readdir_start)(const char *path);
+	int (*readdir_read_next)(struct ffa_dirent *entry);
+	void (*readdir_end)(void);
+	int (*mkdir)(const char *path);
+	int (*create)(const char *path, uint64_t *fh);
+	int (*release)(uint64_t fh);
+	int (*read)(uint64_t fh, char *buf, size_t size, off_t off);
+	int (*write)(uint64_t fh, const char *buf, size_t size, off_t off);
+	int (*ftruncate)(uint64_t fh, off_t size);
+	int (*truncate)(const char *path, off_t size);
+	int (*unlink)(const char *path);
+	int (*rmdir)(const char *path);
+};
+
+void ffsa_init_bottom(const char *fuse_mountpoint, struct ffa_op_callbacks *op_cbs);
+void ffsa_cleanup_bottom(const char *fuse_mountpoint);
+
+bool ffa_is_op_pended(void);
+void ffa_run_pending_op(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SUBSYS_FS_FUSE_FS_ACCESS_BOTTOM_H */
diff --git a/subsys/fs/littlefs_fs.c b/subsys/fs/littlefs_fs.c
index 0ab47e2b983..554a9b289ac 100644
--- a/subsys/fs/littlefs_fs.c
+++ b/subsys/fs/littlefs_fs.c
@@ -657,7 +657,7 @@ static int littlefs_flash_init(struct fs_littlefs *fs, void *dev_id)
 	/* Open flash area */
 	ret = flash_area_open(area_id, fap);
 	if ((ret < 0) || (*fap == NULL)) {
-		LOG_ERR("can't open flash area %d", area_id);
+		LOG_ERR("can't open flash area %d, err %d", area_id, ret);
 		return -ENODEV;
 	}
 
@@ -844,9 +844,6 @@ static int littlefs_init_cfg(struct fs_littlefs *fs, int flags)
 	lcp->context = fs->backend;
 	/* Set the validated/defaulted values. */
 	if (littlefs_on_blkdev(flags)) {
-		lfs_size_t new_cache_size = block_size;
-		lfs_size_t new_lookahead_size = block_size * 4;
-
 		lcp->read = lfs_api_read_blk;
 		lcp->prog = lfs_api_prog_blk;
 		lcp->erase = lfs_api_erase_blk;
@@ -854,19 +851,13 @@ static int littlefs_init_cfg(struct fs_littlefs *fs, int flags)
 		lcp->read_size = block_size;
 		lcp->prog_size = block_size;
 
-		if (cache_size < new_cache_size) {
+		if (cache_size < block_size) {
 			LOG_ERR("Configured cache size is too small: %d < %d", cache_size,
-				new_cache_size);
-			return -ENOMEM;
+				block_size);
 		}
-		lcp->cache_size = new_cache_size;
+		lcp->cache_size = ROUND_DOWN(cache_size, block_size);
 
-		if (lookahead_size < new_lookahead_size) {
-			LOG_ERR("Configured lookahead size is too small: %d < %d",
-				lookahead_size, new_lookahead_size);
-			return -ENOMEM;
-		}
-		lcp->lookahead_size = new_lookahead_size;
+		lcp->lookahead_size = lookahead_size;
 
 		lcp->sync = lfs_api_sync_blk;
 
diff --git a/subsys/fs/nvs/Kconfig b/subsys/fs/nvs/Kconfig
index db9334506fd..21798932f52 100644
--- a/subsys/fs/nvs/Kconfig
+++ b/subsys/fs/nvs/Kconfig
@@ -6,8 +6,8 @@
 config NVS
 	bool "Non-volatile Storage"
 	depends on FLASH
+	depends on FLASH_PAGE_LAYOUT
 	select CRC
-	select FLASH_PAGE_LAYOUT
 	help
 	  Enable support of Non-volatile Storage.
 
diff --git a/subsys/fs/shell.c b/subsys/fs/shell.c
index 76a2aeb909e..5ef7b16d4fc 100644
--- a/subsys/fs/shell.c
+++ b/subsys/fs/shell.c
@@ -17,14 +17,14 @@
 #include <inttypes.h>
 #include <limits.h>
 
-#define STORAGE_PARTITION	storage_partition
-#define STORAGE_PARTITION_ID	FIXED_PARTITION_ID(STORAGE_PARTITION)
+#define STORAGE_PARTITION    storage_partition
+#define STORAGE_PARTITION_ID FIXED_PARTITION_ID(STORAGE_PARTITION)
 
 #ifdef CONFIG_FILE_SYSTEM_SHELL_MOUNT_COMMAND
 /* FAT */
 #ifdef CONFIG_FAT_FILESYSTEM_ELM
 #include <ff.h>
-#define FATFS_MNTP      "/RAM:"
+#define FATFS_MNTP "/RAM:"
 /* FatFs work area */
 FATFS fat_fs;
 /* mounting info */
@@ -77,11 +77,11 @@ static struct fs_mount_t littlefs_mnt = {
 
 #define BUF_CNT 64
 
-#define MAX_PATH_LEN 128
+#define MAX_PATH_LEN     128
 #define MAX_FILENAME_LEN 128
-#define MAX_INPUT_LEN 20
+#define MAX_INPUT_LEN    20
 
-#define SHELL_FS    "fs"
+#define SHELL_FS "fs"
 
 /* Maintenance guarantees this begins with '/' and is NUL-terminated. */
 static char cwd[MAX_PATH_LEN] = "/";
@@ -143,14 +143,14 @@ static int cmd_cd(const struct shell *sh, size_t argc, char **argv)
 	create_abs_path(argv[1], path, sizeof(path));
 
 	err = fs_stat(path, &entry);
-	if (err) {
+	if (err != 0) {
 		shell_error(sh, "%s doesn't exist", path);
-		return -ENOEXEC;
+		return -ENOENT;
 	}
 
 	if (entry.type != FS_DIR_ENTRY_DIR) {
 		shell_error(sh, "%s is not a directory", path);
-		return -ENOEXEC;
+		return -ENOTDIR;
 	}
 
 	strncpy(cwd, path, sizeof(cwd));
@@ -175,16 +175,16 @@ static int cmd_ls(const struct shell *sh, size_t argc, char **argv)
 	fs_dir_t_init(&dir);
 
 	err = fs_opendir(&dir, path);
-	if (err) {
+	if (err != 0) {
 		shell_error(sh, "Unable to open %s (err %d)", path, err);
-		return -ENOEXEC;
+		return -EIO;
 	}
 
 	while (1) {
 		struct fs_dirent entry;
 
 		err = fs_readdir(&dir, &entry);
-		if (err) {
+		if (err != 0) {
 			shell_error(sh, "Unable to read directory");
 			break;
 		}
@@ -194,8 +194,7 @@ static int cmd_ls(const struct shell *sh, size_t argc, char **argv)
 			break;
 		}
 
-		shell_print(sh, "%s%s", entry.name,
-			      (entry.type == FS_DIR_ENTRY_DIR) ? "/" : "");
+		shell_print(sh, "%s%s", entry.name, (entry.type == FS_DIR_ENTRY_DIR) ? "/" : "");
 	}
 
 	fs_closedir(&dir);
@@ -227,15 +226,15 @@ static int cmd_trunc(const struct shell *sh, size_t argc, char **argv)
 
 	fs_file_t_init(&file);
 	err = fs_open(&file, path, FS_O_WRITE);
-	if (err) {
+	if (err != 0) {
 		shell_error(sh, "Failed to open %s (%d)", path, err);
-		return -ENOEXEC;;
+		return -EIO;
 	}
 
 	err = fs_truncate(&file, length);
-	if (err) {
+	if (err != 0) {
 		shell_error(sh, "Failed to truncate %s (%d)", path, err);
-		err = -ENOEXEC;
+		err = -EIO;
 	}
 
 	fs_close(&file);
@@ -251,9 +250,9 @@ static int cmd_mkdir(const struct shell *sh, size_t argc, char **argv)
 	create_abs_path(argv[1], path, sizeof(path));
 
 	err = fs_mkdir(path);
-	if (err) {
+	if (err != 0) {
 		shell_error(sh, "Error creating dir[%d]", err);
-		err = -ENOEXEC;
+		err = -EIO;
 	}
 
 	return err;
@@ -267,14 +266,88 @@ static int cmd_rm(const struct shell *sh, size_t argc, char **argv)
 	create_abs_path(argv[1], path, sizeof(path));
 
 	err = fs_unlink(path);
-	if (err) {
+	if (err != 0) {
 		shell_error(sh, "Failed to remove %s (%d)", path, err);
-		err = -ENOEXEC;
+		err = -EIO;
 	}
 
 	return err;
 }
 
+static int cmd_cp(const struct shell *sh, size_t argc, char **argv)
+{
+	int err;
+	int close_err;
+	char path_src[MAX_PATH_LEN];
+	char path_dst[MAX_PATH_LEN];
+	struct fs_file_t file_src;
+	struct fs_file_t file_dst;
+	uint8_t buf[BUF_CNT];
+	ssize_t buf_len;
+	ssize_t num_written;
+
+	create_abs_path(argv[1], path_src, sizeof(path_src));
+	create_abs_path(argv[2], path_dst, sizeof(path_dst));
+
+	fs_file_t_init(&file_src);
+	fs_file_t_init(&file_dst);
+
+	err = fs_open(&file_src, path_src, FS_O_READ);
+	if (err != 0) {
+		shell_error(sh, "Failed to open %s (%d)", path_src, err);
+		err = -EIO;
+		goto exit;
+	}
+
+	err = fs_open(&file_dst, path_dst, FS_O_CREATE | FS_O_TRUNC | FS_O_WRITE);
+	if (err != 0) {
+		shell_error(sh, "Failed to open %s (%d)", path_dst, err);
+		err = -EIO;
+		goto close_src;
+	}
+
+	while (true) {
+		buf_len = fs_read(&file_src, buf, BUF_CNT);
+		if (buf_len < 0) {
+			shell_error(sh, "Failed to read %s (%d)", path_src, (int)buf_len);
+			err = -EIO;
+			goto close;
+		}
+		if (buf_len == 0) {
+			break;
+		}
+
+		num_written = fs_write(&file_dst, buf, buf_len);
+		if (num_written < 0) {
+			shell_error(sh, "Failed to write %s (%d)", path_dst, (int)num_written);
+			err = -EIO;
+			goto close;
+		}
+		if (num_written != buf_len) {
+			shell_error(sh, "Failed to write %s", path_dst);
+			err = -EIO;
+			goto close;
+		}
+	}
+
+close:
+	close_err = fs_close(&file_dst);
+	if (close_err != 0) {
+		shell_error(sh, "Failed to close %s", path_dst);
+		err = -EIO;
+	}
+
+close_src:
+	close_err = fs_close(&file_src);
+	if (close_err != 0) {
+		shell_error(sh, "Failed to close %s", path_src);
+		err = -EIO;
+	}
+
+exit:
+	return err;
+}
+
 static int cmd_read(const struct shell *sh, size_t argc, char **argv)
 {
 	char path[MAX_PATH_LEN];
@@ -302,38 +375,36 @@ static int cmd_read(const struct shell *sh, size_t argc, char **argv)
 	}
 
 	err = fs_stat(path, &dirent);
-	if (err) {
-		shell_error(sh, "Failed to obtain file %s (err: %d)",
-			    path, err);
-		return -ENOEXEC;
+	if (err != 0) {
+		shell_error(sh, "Failed to obtain file %s (err: %d)", path, err);
+		return -EIO;
 	}
 
 	if (dirent.type != FS_DIR_ENTRY_FILE) {
 		shell_error(sh, "Not a file %s", path);
-		return -ENOEXEC;
+		return -EIO;
 	}
 
 	shell_print(sh, "File size: %zd", dirent.size);
 
 	fs_file_t_init(&file);
 	err = fs_open(&file, path, FS_O_READ);
-	if (err) {
+	if (err != 0) {
 		shell_error(sh, "Failed to open %s (%d)", path, err);
-		return -ENOEXEC;
+		return -EIO;
 	}
 
 	if (offset > 0) {
 		err = fs_seek(&file, offset, FS_SEEK_SET);
-		if (err) {
-			shell_error(sh, "Failed to seek %s (%d)",
-				    path, err);
+		if (err != 0) {
+			shell_error(sh, "Failed to seek %s (%d)", path, err);
 			fs_close(&file);
-			return -ENOEXEC;
+			return -EIO;
 		}
 	}
 
+	ssize_t read = 0;
 	while (count > 0) {
-		ssize_t read;
 		uint8_t buf[16];
 		int i;
 
@@ -351,11 +422,11 @@ static int cmd_read(const struct shell *sh, size_t argc, char **argv)
 			shell_fprintf(sh, SHELL_NORMAL, "   ");
 		}
 		i = sizeof(buf) - i;
-		shell_fprintf(sh, SHELL_NORMAL, "%*c", i*3, ' ');
+		shell_fprintf(sh, SHELL_NORMAL, "%*c", i * 3, ' ');
 
 		for (i = 0; i < read; i++) {
-			shell_fprintf(sh, SHELL_NORMAL, "%c", buf[i] < 32 ||
-				      buf[i] > 127 ? '.' : buf[i]);
+			shell_fprintf(sh, SHELL_NORMAL, "%c",
+				      buf[i] < 32 || buf[i] > 127 ? '.' : buf[i]);
 		}
 
 		shell_print(sh, "");
@@ -364,6 +435,10 @@ static int cmd_read(const struct shell *sh, size_t argc, char **argv)
 		count -= read;
 	}
 
+	if (read < 0) {
+		shell_error(sh, "Failed to read from file %s (err: %zd)", path, read);
+	}
+
 	fs_close(&file);
 
 	return 0;
@@ -385,8 +460,7 @@ static int cmd_cat(const struct shell *sh, size_t argc, char **argv)
 
 		err = fs_stat(path, &dirent);
 		if (err < 0) {
-			shell_error(sh, "Failed to obtain file %s (err: %d)",
-					path, err);
+			shell_error(sh, "Failed to obtain file %s (err: %d)", path, err);
 			continue;
 		}
 
@@ -413,8 +487,7 @@ static int cmd_cat(const struct shell *sh, size_t argc, char **argv)
 		}
 
 		if (read < 0) {
-			shell_error(sh, "Failed to read from file %s (err: %zd)",
-				path, read);
+			shell_error(sh, "Failed to read from file %s (err: %zd)", path, read);
 		}
 
 		fs_close(&file);
@@ -434,11 +507,10 @@ static int cmd_statvfs(const struct shell *sh, size_t argc, char **argv)
 	err = fs_statvfs(path, &stat);
 	if (err < 0) {
 		shell_error(sh, "Failed to statvfs %s (%d)", path, err);
-		return -ENOEXEC;
+		return -EIO;
 	}
 
-	shell_fprintf(sh, SHELL_NORMAL,
-		      "bsize %lu, frsize %lu, blocks %lu, bfree %lu\n",
+	shell_fprintf(sh, SHELL_NORMAL, "bsize %lu, frsize %lu, blocks %lu, bfree %lu\n",
 		      stat.f_bsize, stat.f_frsize, stat.f_blocks, stat.f_bfree);
 
 	return 0;
@@ -459,7 +531,7 @@ static int cmd_write(const struct shell *sh, size_t argc, char **argv)
 	if (!strcmp(argv[2], "-o")) {
 		if (argc < 4) {
 			shell_error(sh, "Missing argument");
-			return -ENOEXEC;
+			return -EINVAL;
 		}
 
 		offset = strtol(argv[3], NULL, 0);
@@ -471,9 +543,9 @@ static int cmd_write(const struct shell *sh, size_t argc, char **argv)
 
 	fs_file_t_init(&file);
 	err = fs_open(&file, path, FS_O_CREATE | FS_O_WRITE);
-	if (err) {
+	if (err != 0) {
 		shell_error(sh, "Failed to open %s (%d)", path, err);
-		return -ENOEXEC;
+		return -EIO;
 	}
 
 	if (offset < 0) {
@@ -481,10 +553,10 @@ static int cmd_write(const struct shell *sh, size_t argc, char **argv)
 	} else {
 		err = fs_seek(&file, offset, FS_SEEK_SET);
 	}
-	if (err) {
+	if (err != 0) {
 		shell_error(sh, "Failed to seek %s (%d)", path, err);
 		fs_close(&file);
-		return -ENOEXEC;
+		return -EIO;
 	}
 
 	buf_len = 0U;
@@ -494,10 +566,9 @@ static int cmd_write(const struct shell *sh, size_t argc, char **argv)
 		if ((buf_len == BUF_CNT) || (arg_offset == argc)) {
 			err = fs_write(&file, buf, buf_len);
 			if (err < 0) {
-				shell_error(sh, "Failed to write %s (%d)",
-					      path, err);
+				shell_error(sh, "Failed to write %s (%d)", path, err);
 				fs_close(&file);
-				return -ENOEXEC;
+				return -EIO;
 			}
 
 			buf_len = 0U;
@@ -510,7 +581,7 @@ static int cmd_write(const struct shell *sh, size_t argc, char **argv)
 }
 
 #ifdef CONFIG_FILE_SYSTEM_SHELL_TEST_COMMANDS
-const static uint8_t speed_types[][4] = { "B", "KiB", "MiB", "GiB" };
+const static uint8_t speed_types[][4] = {"B", "KiB", "MiB", "GiB"};
 const static uint32_t speed_divisor = 1024;
 
 static void file_size_output(const struct shell *sh, double size)
@@ -522,8 +593,7 @@ static void file_size_output(const struct shell *sh, double size)
 		++speed_index;
 	}
 
-	shell_print(sh, "File size: %.1f%s",
-		    size, speed_types[speed_index]);
+	shell_print(sh, "File size: %.1f%s", size, speed_types[speed_index]);
 }
 
 static void speed_output(const struct shell *sh, uint64_t total_time, double loops, double size)
@@ -541,8 +611,8 @@ static void speed_output(const struct shell *sh, uint64_t total_time, double loo
 		++speed_index;
 	}
 
-	shell_print(sh, "Total: %llums, Per loop: ~%.0fms, Speed: ~%.1f%sps",
-		    total_time, time_per_loop, throughput, speed_types[speed_index]);
+	shell_print(sh, "Total: %llums, Per loop: ~%.0fms, Speed: ~%.1f%sps", total_time,
+		    time_per_loop, throughput, speed_types[speed_index]);
 }
 
 static int cmd_read_test(const struct shell *sh, size_t argc, char **argv)
@@ -594,9 +664,9 @@ static int cmd_read_test(const struct shell *sh, size_t argc, char **argv)
 
 		fs_file_t_init(&file);
 		err = fs_open(&file, path, FS_O_READ);
-		if (err) {
+		if (err != 0) {
 			shell_error(sh, "Failed to open %s (%d)", path, err);
-			return -ENOEXEC;
+			return -EIO;
 		}
 
 		/* Read data in chunk by chunk until the full size has been read */
@@ -604,27 +674,26 @@ static int cmd_read_test(const struct shell *sh, size_t argc, char **argv)
 		while (1) {
 			err = fs_read(&file, random_data, sizeof(random_data));
 			if (err < 0) {
-				shell_error(sh, "Failed to write %s (%d)",
-					      path, err);
+				shell_error(sh, "Failed to read %s (%d)", path, err);
 				fs_close(&file);
-				return -ENOEXEC;
+				return -EIO;
 			}
 
 			i += err;
 
-			if (err < sizeof(random_data)) {
+			if (err == 0) {
 				/* Read finished */
 				break;
 			}
 		}
 
-		/* Ensure file contents is fully written then close file */
+		/* Ensure file contents is fully read then close file */
 		fs_close(&file);
 
 		if (i != size) {
-			shell_error(sh, "File read error, expected %d bytes but only read %d",
-				    size, i);
-			return -EINVAL;
+			shell_error(sh, "File read error, expected %d bytes but only read %d", size,
+				    i);
+			return -EIO;
 		}
 
 		++loops;
@@ -683,9 +752,9 @@ static int cmd_erase_write_test(const struct shell *sh, size_t argc, char **argv
 
 		fs_file_t_init(&file);
 		err = fs_open(&file, path, FS_O_CREATE | FS_O_WRITE);
-		if (err) {
+		if (err != 0) {
 			shell_error(sh, "Failed to open %s (%d)", path, err);
-			return -ENOEXEC;
+			return -EIO;
 		}
 
 		/* Truncate the file size to 0 (if supported, erase if not) */
@@ -695,20 +764,20 @@ static int cmd_erase_write_test(const struct shell *sh, size_t argc, char **argv
 			fs_close(&file);
 
 			err = fs_unlink(path);
-			if (err) {
+			if (err != 0) {
 				shell_error(sh, "Failed to delete %s (%d)", path, err);
-				return -ENOEXEC;
+				return -EIO;
 			}
 
 			err = fs_open(&file, path, FS_O_CREATE | FS_O_WRITE);
-			if (err) {
+			if (err != 0) {
 				shell_error(sh, "Failed to open %s (%d)", path, err);
-				return -ENOEXEC;
+				return -EIO;
 			}
-		} else if (err) {
+		} else if (err != 0) {
 			shell_error(sh, "Failed to truncate %s (%d)", path, err);
 			fs_close(&file);
-			return -ENOEXEC;
+			return -EIO;
 		}
 
 		/* Write data out chunk by chunk until the full size has been written */
@@ -722,10 +791,9 @@ static int cmd_erase_write_test(const struct shell *sh, size_t argc, char **argv
 
 			err = fs_write(&file, random_data, write_size);
 			if (err < 0) {
-				shell_error(sh, "Failed to write %s (%d)",
-					      path, err);
+				shell_error(sh, "Failed to write %s (%d)", path, err);
 				fs_close(&file);
-				return -ENOEXEC;
+				return -EIO;
 			}
 
 			i += write_size;
@@ -754,7 +822,7 @@ static char *mntpt_prepare(char *mntpt)
 	char *cpy_mntpt;
 
 	cpy_mntpt = k_malloc(strlen(mntpt) + 1);
-	if (cpy_mntpt) {
+	if (cpy_mntpt != NULL) {
 		strcpy(cpy_mntpt, mntpt);
 	}
 	return cpy_mntpt;
@@ -767,24 +835,21 @@ static int cmd_mount_fat(const struct shell *sh, size_t argc, char **argv)
 	int res;
 
 	mntpt = mntpt_prepare(argv[1]);
-	if (!mntpt) {
-		shell_error(sh,
-			    "Failed to allocate  buffer for mount point");
-		return -ENOEXEC;
+	if (mntpt == NULL) {
+		shell_error(sh, "Failed to allocate buffer for mount point");
+		return -EIO;
 	}
 
 	fatfs_mnt.mnt_point = (const char *)mntpt;
 	res = fs_mount(&fatfs_mnt);
 	if (res != 0) {
-		shell_error(sh,
-			"Error mounting FAT fs. Error Code [%d]", res);
+		shell_error(sh, "Error mounting FAT fs. Error Code [%d]", res);
 		k_free((void *)fatfs_mnt.mnt_point);
 		fatfs_mnt.mnt_point = NULL;
-		return -ENOEXEC;
+		return -EIO;
 	}
 
-	shell_print(sh, "Successfully mounted fat fs:%s",
-			fatfs_mnt.mnt_point);
+	shell_print(sh, "Successfully mounted fat fs:%s", fatfs_mnt.mnt_point);
 
 	return 0;
 }
@@ -799,9 +864,9 @@ static int cmd_mount_littlefs(const struct shell *sh, size_t argc, char **argv)
 
 	char *mntpt = mntpt_prepare(argv[1]);
 
-	if (!mntpt) {
+	if (mntpt == NULL) {
 		shell_error(sh, "Failed to allocate mount point");
-		return -ENOEXEC; /* ?!? */
+		return -EIO;
 	}
 
 	littlefs_mnt.mnt_point = mntpt;
@@ -812,7 +877,7 @@ static int cmd_mount_littlefs(const struct shell *sh, size_t argc, char **argv)
 		shell_error(sh, "Error mounting as littlefs: %d", rc);
 		k_free((void *)littlefs_mnt.mnt_point);
 		littlefs_mnt.mnt_point = NULL;
-		return -ENOEXEC;
+		return -EIO;
 	}
 
 	return rc;
@@ -850,14 +915,13 @@ SHELL_STATIC_SUBCMD_SET_CREATE(sub_fs,
 		"Concatenate files and print on the standard output",
 		cmd_cat, 2, 255),
 	SHELL_CMD_ARG(rm, NULL, "Remove file", cmd_rm, 2, 0),
+	SHELL_CMD_ARG(cp, NULL, "Copy file", cmd_cp, 3, 0),
 	SHELL_CMD_ARG(statvfs, NULL, "Show file system state", cmd_statvfs, 2, 0),
 	SHELL_CMD_ARG(trunc, NULL, "Truncate file", cmd_trunc, 2, 255),
 	SHELL_CMD_ARG(write, NULL, "Write file", cmd_write, 3, 255),
 #ifdef CONFIG_FILE_SYSTEM_SHELL_TEST_COMMANDS
-	SHELL_CMD_ARG(read_test, NULL, "Read file test",
-		      cmd_read_test, 2, 2),
-	SHELL_CMD_ARG(erase_write_test, NULL, "Erase/write file test",
-		      cmd_erase_write_test, 3, 3),
+	SHELL_CMD_ARG(read_test, NULL, "Read file test", cmd_read_test, 2, 2),
+	SHELL_CMD_ARG(erase_write_test, NULL, "Erase/write file test", cmd_erase_write_test, 3, 3),
 #endif
 	SHELL_SUBCMD_SET_END
 );
diff --git a/subsys/fs/zms/Kconfig b/subsys/fs/zms/Kconfig
index c2b1d6f0fef..65dcdd875ff 100644
--- a/subsys/fs/zms/Kconfig
+++ b/subsys/fs/zms/Kconfig
@@ -1,3 +1,4 @@
+# Copyright (c) 2018 Laczen
 # Copyright (c) 2024 BayLibre SAS
 
 # SPDX-License-Identifier: Apache-2.0
diff --git a/subsys/fs/zms/zms.c b/subsys/fs/zms/zms.c
index 4336d90805b..efbf6e2cc84 100644
--- a/subsys/fs/zms/zms.c
+++ b/subsys/fs/zms/zms.c
@@ -1,4 +1,5 @@
-/* Copyright (c) 2024 BayLibre SAS
+/* Copyright (c) 2018 Laczen
+ * Copyright (c) 2024 BayLibre SAS
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -751,6 +752,40 @@ static int zms_add_gc_done_ate(struct zms_fs *fs)
 	return zms_flash_ate_wrt(fs, &gc_done_ate);
 }
 
+/* This function verifies that the cycle_cnt of the close ATE will not be equal
+ * to the cycle_cnt of the empty ATE after incrementing it.
+ * This is possible only in these extreme conditions:
+ * 1- A Garbage collection operation is interrupted due to a power cut
+ * 2- When rebooting, the sector is erased (cycle_cnt incremented)
+ * 3- Garbage collection restarts again and got interrupted again by a power cut
+ * 4- Steps [2..3] occurred 255 times in a row
+ * At this point the sector that we should erase becomes closed.
+ */
+static inline int zms_verify_and_increment_cycle_cnt(struct zms_fs *fs, uint64_t addr,
+						     uint8_t *cycle_cnt)
+{
+	int rc;
+	uint64_t close_addr;
+	struct zms_ate close_ate;
+
+	close_addr = zms_close_ate_addr(fs, addr);
+	/* Read the second ate in the sector to get the close ATE */
+	rc = zms_flash_ate_rd(fs, close_addr, &close_ate);
+	if (rc < 0) {
+		return rc;
+	}
+
+	*cycle_cnt = (*cycle_cnt + 1) % BIT(8);
+	/* Verify that the close cycle_cnt is not equal to the incremented value.
+	 * If they are equal increment it again.
+	 */
+	if (close_ate.cycle_cnt == *cycle_cnt) {
+		*cycle_cnt = (*cycle_cnt + 1) % BIT(8);
+	}
+
+	return 0;
+}
+
 static int zms_add_empty_ate(struct zms_fs *fs, uint64_t addr)
 {
 	struct zms_ate empty_ate;
@@ -776,8 +811,12 @@ static int zms_add_empty_ate(struct zms_fs *fs, uint64_t addr)
 		return rc;
 	}
 
-	/* increase cycle counter */
-	empty_ate.cycle_cnt = (cycle_cnt + 1) % BIT(8);
+	/* Increase cycle counter */
+	rc = zms_verify_and_increment_cycle_cnt(fs, addr, &cycle_cnt);
+	if (rc < 0) {
+		return rc;
+	}
+	empty_ate.cycle_cnt = cycle_cnt;
 	zms_ate_crc8_update(&empty_ate);
 
 	/* Adding empty ate to this sector changes fs->ate_wra value
@@ -1287,6 +1326,7 @@ static int zms_init(struct zms_fs *fs)
 			}
 
 			if (zms_gc_done_ate_valid(fs, &gc_done_ate)) {
+				gc_done_marker = true;
 				break;
 			}
 			addr += fs->ate_size;
@@ -1393,6 +1433,7 @@ int zms_mount(struct zms_fs *fs)
 	if (fs->sector_size < ZMS_MIN_ATE_NUM * fs->ate_size) {
 		LOG_ERR("Invalid sector size, should be at least %zu",
 			ZMS_MIN_ATE_NUM * fs->ate_size);
+		return -EINVAL;
 	}
 
 	/* check the number of sectors, it should be at least 2 */
diff --git a/subsys/fs/zms/zms_priv.h b/subsys/fs/zms/zms_priv.h
index e2cbf5f08bb..84f77296f4f 100644
--- a/subsys/fs/zms/zms_priv.h
+++ b/subsys/fs/zms/zms_priv.h
@@ -1,4 +1,5 @@
-/* Copyright (c) 2024 BayLibre SAS
+/* Copyright (c) 2018 Laczen
+ * Copyright (c) 2024 BayLibre SAS
  *
  * SPDX-License-Identifier: Apache-2.0
  *
diff --git a/subsys/ipc/ipc_service/backends/ipc_icbmsg.c b/subsys/ipc/ipc_service/backends/ipc_icbmsg.c
index f74aafc8ce2..312642aafeb 100644
--- a/subsys/ipc/ipc_service/backends/ipc_icbmsg.c
+++ b/subsys/ipc/ipc_service/backends/ipc_icbmsg.c
@@ -1088,7 +1088,6 @@ static int register_ept(const struct device *instance, void **token,
 	struct ept_data *ept = NULL;
 	bool matching_state;
 	int ept_index;
-	int r = 0;
 
 	/* Try to find endpoint to rebound */
 	for (ept_index = 0; ept_index < NUM_EPT; ept_index++) {
@@ -1135,7 +1134,7 @@ static int register_ept(const struct device *instance, void **token,
 	ept_bound_process(dev_data);
 #endif
 
-	return r;
+	return 0;
 }
 
 /**
@@ -1238,8 +1237,13 @@ static int hold_rx_buffer(const struct device *instance, void *token, void *data
 static int release_rx_buffer(const struct device *instance, void *token, void *data)
 {
 	struct backend_data *dev_data = instance->data;
+	int r;
 
-	return send_release(dev_data, (uint8_t *)data, MSG_RELEASE_DATA, 0);
+	r = send_release(dev_data, (uint8_t *)data, MSG_RELEASE_DATA, 0);
+	if (r < 0) {
+		return r;
+	}
+	return 0;
 }
 
 /**
@@ -1409,11 +1413,11 @@ const static struct ipc_service_backend backend_ops = {
 	PBUF_DEFINE(tx_icbmsg_pb_##i,							\
 			GET_MEM_ADDR_INST(i, tx),					\
 			GET_ICMSG_SIZE_INST(i, tx, rx),					\
-			GET_CACHE_ALIGNMENT(i));					\
+			GET_CACHE_ALIGNMENT(i), 0, 0);					\
 	PBUF_DEFINE(rx_icbmsg_pb_##i,							\
 			GET_MEM_ADDR_INST(i, rx),					\
 			GET_ICMSG_SIZE_INST(i, rx, tx),					\
-			GET_CACHE_ALIGNMENT(i));					\
+			GET_CACHE_ALIGNMENT(i), 0, 0);					\
 	static struct backend_data backend_data_##i = {					\
 		.control_data = {							\
 			.tx_pb = &tx_icbmsg_pb_##i,					\
@@ -1425,6 +1429,7 @@ const static struct ipc_service_backend backend_ops = {
 		.control_config = {							\
 			.mbox_tx = MBOX_DT_SPEC_INST_GET(i, tx),			\
 			.mbox_rx = MBOX_DT_SPEC_INST_GET(i, rx),			\
+			.unbound_mode = ICMSG_UNBOUND_MODE_DISABLE,			\
 		},									\
 		.tx = {									\
 			.blocks_ptr = (uint8_t *)GET_BLOCKS_ADDR_INST(i, tx, rx),	\
diff --git a/subsys/ipc/ipc_service/backends/ipc_icmsg.c b/subsys/ipc/ipc_service/backends/ipc_icmsg.c
index 40cc06b8a6f..77b118633ea 100644
--- a/subsys/ipc/ipc_service/backends/ipc_icmsg.c
+++ b/subsys/ipc/ipc_service/backends/ipc_icmsg.c
@@ -54,33 +54,52 @@ static int backend_init(const struct device *instance)
 	return 0;
 }
 
-#define DEFINE_BACKEND_DEVICE(i)					\
-	static const struct icmsg_config_t backend_config_##i = {	\
-		.mbox_tx = MBOX_DT_SPEC_INST_GET(i, tx),		\
-		.mbox_rx = MBOX_DT_SPEC_INST_GET(i, rx),		\
-	};								\
-									\
-	PBUF_DEFINE(tx_pb_##i,						\
-			DT_REG_ADDR(DT_INST_PHANDLE(i, tx_region)),	\
-			DT_REG_SIZE(DT_INST_PHANDLE(i, tx_region)),	\
-			DT_INST_PROP_OR(i, dcache_alignment, 0));	\
-	PBUF_DEFINE(rx_pb_##i,						\
-			DT_REG_ADDR(DT_INST_PHANDLE(i, rx_region)),	\
-			DT_REG_SIZE(DT_INST_PHANDLE(i, rx_region)),	\
-			DT_INST_PROP_OR(i, dcache_alignment, 0));	\
-									\
-	static struct icmsg_data_t backend_data_##i = {			\
-		.tx_pb = &tx_pb_##i,					\
-		.rx_pb = &rx_pb_##i,					\
-	};								\
-									\
-	DEVICE_DT_INST_DEFINE(i,					\
-			 &backend_init,					\
-			 NULL,						\
-			 &backend_data_##i,				\
-			 &backend_config_##i,				\
-			 POST_KERNEL,					\
-			 CONFIG_IPC_SERVICE_REG_BACKEND_PRIORITY,	\
+#define UNBOUND_MODE(i) CONCAT(ICMSG_UNBOUND_MODE_, DT_INST_STRING_UPPER_TOKEN(i, unbound))
+
+#define DEFINE_BACKEND_DEVICE(i)						\
+	static const struct icmsg_config_t backend_config_##i = {		\
+		.mbox_tx = MBOX_DT_SPEC_INST_GET(i, tx),			\
+		.mbox_rx = MBOX_DT_SPEC_INST_GET(i, rx),			\
+		.unbound_mode = UNBOUND_MODE(i),				\
+	};									\
+										\
+	PBUF_DEFINE(tx_pb_##i,							\
+			DT_REG_ADDR(DT_INST_PHANDLE(i, tx_region)),		\
+			DT_REG_SIZE(DT_INST_PHANDLE(i, tx_region)),		\
+			DT_INST_PROP_OR(i, dcache_alignment, 0),		\
+			UNBOUND_MODE(i) != ICMSG_UNBOUND_MODE_DISABLE,		\
+			UNBOUND_MODE(i) == ICMSG_UNBOUND_MODE_DETECT);		\
+	PBUF_DEFINE(rx_pb_##i,							\
+			DT_REG_ADDR(DT_INST_PHANDLE(i, rx_region)),		\
+			DT_REG_SIZE(DT_INST_PHANDLE(i, rx_region)),		\
+			DT_INST_PROP_OR(i, dcache_alignment, 0),		\
+			UNBOUND_MODE(i) != ICMSG_UNBOUND_MODE_DISABLE,		\
+			UNBOUND_MODE(i) == ICMSG_UNBOUND_MODE_DETECT);		\
+										\
+	BUILD_ASSERT(UNBOUND_MODE(i) != ICMSG_UNBOUND_MODE_DISABLE ||		\
+		IS_ENABLED(CONFIG_IPC_SERVICE_ICMSG_UNBOUND_DISABLED_ALLOWED),	\
+		"Unbound mode \"disabled\" is was forbidden in Kconfig.");	\
+										\
+	BUILD_ASSERT(UNBOUND_MODE(i) != ICMSG_UNBOUND_MODE_ENABLE ||		\
+		IS_ENABLED(CONFIG_IPC_SERVICE_ICMSG_UNBOUND_ENABLED_ALLOWED),	\
+		"Unbound mode \"enabled\" is was forbidden in Kconfig.");	\
+										\
+	BUILD_ASSERT(UNBOUND_MODE(i) != ICMSG_UNBOUND_MODE_DETECT ||		\
+		IS_ENABLED(CONFIG_IPC_SERVICE_ICMSG_UNBOUND_DETECT_ALLOWED),	\
+		"Unbound mode \"detect\" is was forbidden in Kconfig.");	\
+										\
+	static struct icmsg_data_t backend_data_##i = {				\
+		.tx_pb = &tx_pb_##i,						\
+		.rx_pb = &rx_pb_##i,						\
+	};									\
+										\
+	DEVICE_DT_INST_DEFINE(i,						\
+			 &backend_init,						\
+			 NULL,							\
+			 &backend_data_##i,					\
+			 &backend_config_##i,					\
+			 POST_KERNEL,						\
+			 CONFIG_IPC_SERVICE_REG_BACKEND_PRIORITY,		\
 			 &backend_ops);
 
 DT_INST_FOREACH_STATUS_OKAY(DEFINE_BACKEND_DEVICE)
diff --git a/subsys/ipc/ipc_service/backends/ipc_icmsg_me_follower.c b/subsys/ipc/ipc_service/backends/ipc_icmsg_me_follower.c
index cc374b31f57..bf682cd51e1 100644
--- a/subsys/ipc/ipc_service/backends/ipc_icmsg_me_follower.c
+++ b/subsys/ipc/ipc_service/backends/ipc_icmsg_me_follower.c
@@ -280,16 +280,17 @@ static int backend_init(const struct device *instance)
 	static const struct icmsg_config_t backend_config_##i = {		\
 		.mbox_tx = MBOX_DT_SPEC_INST_GET(i, tx),			\
 		.mbox_rx = MBOX_DT_SPEC_INST_GET(i, rx),			\
+		.unbound_mode = ICMSG_UNBOUND_MODE_DISABLE,			\
 	};									\
 										\
 	PBUF_DEFINE(tx_pb_##i,							\
 			DT_REG_ADDR(DT_INST_PHANDLE(i, tx_region)),		\
 			DT_REG_SIZE(DT_INST_PHANDLE(i, tx_region)),		\
-			DT_INST_PROP_OR(i, dcache_alignment, 0));		\
+			DT_INST_PROP_OR(i, dcache_alignment, 0), 0, 0);		\
 	PBUF_DEFINE(rx_pb_##i,							\
 			DT_REG_ADDR(DT_INST_PHANDLE(i, rx_region)),		\
 			DT_REG_SIZE(DT_INST_PHANDLE(i, rx_region)),		\
-			DT_INST_PROP_OR(i, dcache_alignment, 0));		\
+			DT_INST_PROP_OR(i, dcache_alignment, 0), 0, 0);		\
 										\
 	static struct backend_data_t backend_data_##i = {			\
 		.icmsg_me_data = {						\
diff --git a/subsys/ipc/ipc_service/backends/ipc_icmsg_me_initiator.c b/subsys/ipc/ipc_service/backends/ipc_icmsg_me_initiator.c
index 28170f909ec..f2064a9dc0f 100644
--- a/subsys/ipc/ipc_service/backends/ipc_icmsg_me_initiator.c
+++ b/subsys/ipc/ipc_service/backends/ipc_icmsg_me_initiator.c
@@ -186,16 +186,17 @@ static int backend_init(const struct device *instance)
 	static const struct icmsg_config_t backend_config_##i = {		\
 		.mbox_tx = MBOX_DT_SPEC_INST_GET(i, tx),			\
 		.mbox_rx = MBOX_DT_SPEC_INST_GET(i, rx),			\
+		.unbound_mode = ICMSG_UNBOUND_MODE_DISABLE,			\
 	};									\
 										\
 	PBUF_DEFINE(tx_pb_##i,							\
 			DT_REG_ADDR(DT_INST_PHANDLE(i, tx_region)),		\
 			DT_REG_SIZE(DT_INST_PHANDLE(i, tx_region)),		\
-			DT_INST_PROP_OR(i, dcache_alignment, 0));		\
+			DT_INST_PROP_OR(i, dcache_alignment, 0), 0, 0);		\
 	PBUF_DEFINE(rx_pb_##i,							\
 			DT_REG_ADDR(DT_INST_PHANDLE(i, rx_region)),		\
 			DT_REG_SIZE(DT_INST_PHANDLE(i, rx_region)),		\
-			DT_INST_PROP_OR(i, dcache_alignment, 0));		\
+			DT_INST_PROP_OR(i, dcache_alignment, 0), 0, 0);		\
 										\
 	static struct backend_data_t backend_data_##i = {			\
 		.icmsg_me_data = {						\
diff --git a/subsys/ipc/ipc_service/lib/Kconfig.icmsg b/subsys/ipc/ipc_service/lib/Kconfig.icmsg
index bc15d9a5999..6bbc79d4fa2 100644
--- a/subsys/ipc/ipc_service/lib/Kconfig.icmsg
+++ b/subsys/ipc/ipc_service/lib/Kconfig.icmsg
@@ -21,14 +21,6 @@ config IPC_SERVICE_ICMSG_SHMEM_ACCESS_TO_MS
 	  Maximum time to wait, in milliseconds, for access to send data with
 	  backends basing on icmsg library. This time should be relatively low.
 
-config IPC_SERVICE_ICMSG_BOND_NOTIFY_REPEAT_TO_MS
-	int "Bond notification timeout in miliseconds"
-	range 1 100
-	default 1
-	help
-	  Time to wait for remote bonding notification before the
-	  notification is repeated.
-
 config IPC_SERVICE_BACKEND_ICMSG_WQ_ENABLE
 	bool "Use dedicated workqueue"
 	depends on MULTITHREADING
@@ -68,6 +60,33 @@ config IPC_SERVICE_BACKEND_ICMSG_WQ_PRIORITY
 
 endif
 
+config IPC_SERVICE_ICMSG_UNBOUND_ENABLED_ALLOWED
+	bool "Instance is allowed to set unbound to enabled"
+	default y
+	help
+	  Controls whether the "enabled" value of the "unbound"
+	  property is allowed to be set in any of the ICMsg instances. You
+	  can set this option to "n", if you want to reduce code size and
+	  no instance of ICMsg is using unbound functionality.
+
+config IPC_SERVICE_ICMSG_UNBOUND_DISABLED_ALLOWED
+	bool "Instance is allowed to set unbound to disabled"
+	default y
+	help
+	  Controls whether the "disabled" value of the "unbound"
+	  property is allowed to be set in any of the ICMsg instances. You
+	  can set this option to "n", if you want to reduce code size and
+	  all instances of ICMsg are using unbound functionality.
+
+config IPC_SERVICE_ICMSG_UNBOUND_DETECT_ALLOWED
+	bool "Instance is allowed to set unbound to detect"
+	default y
+	help
+	  Controls whether the "detect" value of the "unbound"
+	  property is allowed to be set in any of the ICMsg instances. You
+	  can set this option to "n", if you want to reduce code size and
+	  all instances of ICMsg are using unbound detection functionality.
+
 # The Icmsg library in its simplicity requires the system workqueue to execute
 # at a cooperative priority.
 config SYSTEM_WORKQUEUE_PRIORITY
diff --git a/subsys/ipc/ipc_service/lib/icmsg.c b/subsys/ipc/ipc_service/lib/icmsg.c
index f574e71ec14..500ca20cde6 100644
--- a/subsys/ipc/ipc_service/lib/icmsg.c
+++ b/subsys/ipc/ipc_service/lib/icmsg.c
@@ -12,7 +12,39 @@
 #include <zephyr/ipc/pbuf.h>
 #include <zephyr/init.h>
 
-#define BOND_NOTIFY_REPEAT_TO	K_MSEC(CONFIG_IPC_SERVICE_ICMSG_BOND_NOTIFY_REPEAT_TO_MS)
+
+#define UNBOUND_DISABLED IS_ENABLED(CONFIG_IPC_SERVICE_ICMSG_UNBOUND_DISABLED_ALLOWED)
+#define UNBOUND_ENABLED IS_ENABLED(CONFIG_IPC_SERVICE_ICMSG_UNBOUND_ENABLED_ALLOWED)
+#define UNBOUND_DETECT IS_ENABLED(CONFIG_IPC_SERVICE_ICMSG_UNBOUND_DETECT_ALLOWED)
+
+/** Get local session id request from RX handshake word.
+ */
+#define LOCAL_SID_REQ_FROM_RX(rx_handshake) ((rx_handshake) & 0xFFFF)
+
+/** Get remote session id request from TX handshake word.
+ */
+#define REMOTE_SID_REQ_FROM_TX(tx_handshake) ((tx_handshake) & 0xFFFF)
+
+/** Get local session id acknowledge from TX handshake word.
+ */
+#define LOCAL_SID_ACK_FROM_TX(tx_handshake) ((tx_handshake) >> 16)
+
+/** Create RX handshake word from local session id request
+ * and remote session id acknowledge.
+ */
+#define MAKE_RX_HANDSHAKE(local_sid_req, remote_sid_ack) \
+	((local_sid_req) | ((remote_sid_ack) << 16))
+
+/** Create TX handshake word from remote session id request
+ * and local session id acknowledge.
+ */
+#define MAKE_TX_HANDSHAKE(remote_sid_req, local_sid_ack) \
+	((remote_sid_req) | ((local_sid_ack) << 16))
+
+/** Special session id indicating that peers are disconnected.
+ */
+#define SID_DISCONNECTED 0
+
 #define SHMEM_ACCESS_TO		K_MSEC(CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_TO_MS)
 
 static const uint8_t magic[] = {0x45, 0x6d, 0x31, 0x6c, 0x31, 0x4b,
@@ -23,13 +55,10 @@ static const uint8_t magic[] = {0x45, 0x6d, 0x31, 0x6c, 0x31, 0x4b,
 static K_THREAD_STACK_DEFINE(icmsg_stack, CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_STACK_SIZE);
 static struct k_work_q icmsg_workq;
 static struct k_work_q *const workq = &icmsg_workq;
-#else
+#else /* defined(CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_ENABLE) */
 static struct k_work_q *const workq = &k_sys_work_q;
-#endif
-static void mbox_callback_process(struct k_work *item);
-#else
-static void mbox_callback_process(struct icmsg_data_t *dev_data);
-#endif
+#endif /* defined(CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_ENABLE) */
+#endif /* def CONFIG_MULTITHREADING */
 
 static int mbox_deinit(const struct icmsg_config_t *conf,
 		       struct icmsg_data_t *dev_data)
@@ -48,76 +77,33 @@ static int mbox_deinit(const struct icmsg_config_t *conf,
 
 #ifdef CONFIG_MULTITHREADING
 	(void)k_work_cancel(&dev_data->mbox_work);
-	(void)k_work_cancel_delayable(&dev_data->notify_work);
 #endif
 
 	return 0;
 }
 
-static bool is_endpoint_ready(struct icmsg_data_t *dev_data)
+static bool is_endpoint_ready(atomic_t state)
 {
-	return atomic_get(&dev_data->state) == ICMSG_STATE_READY;
+	return state >= MIN(ICMSG_STATE_CONNECTED_SID_DISABLED, ICMSG_STATE_CONNECTED_SID_ENABLED);
 }
 
-#ifdef CONFIG_MULTITHREADING
-static void notify_process(struct k_work *item)
+static inline int reserve_tx_buffer_if_unused(struct icmsg_data_t *dev_data)
 {
-	struct k_work_delayable *dwork = k_work_delayable_from_work(item);
-	struct icmsg_data_t *dev_data =
-		CONTAINER_OF(dwork, struct icmsg_data_t, notify_work);
-
-	(void)mbox_send_dt(&dev_data->cfg->mbox_tx, NULL);
-
-	atomic_t state = atomic_get(&dev_data->state);
-
-	if (state != ICMSG_STATE_READY) {
-		int ret;
-
-		ret = k_work_reschedule_for_queue(workq, dwork, BOND_NOTIFY_REPEAT_TO);
-		__ASSERT_NO_MSG(ret >= 0);
-		(void)ret;
-	}
-}
-#else
-static void notify_process(struct icmsg_data_t *dev_data)
-{
-	(void)mbox_send_dt(&dev_data->cfg->mbox_tx, NULL);
-#if defined(CONFIG_SYS_CLOCK_EXISTS)
-	int64_t start = k_uptime_get();
-#endif
-
-	while (false == is_endpoint_ready(dev_data)) {
-		mbox_callback_process(dev_data);
-
-#if defined(CONFIG_SYS_CLOCK_EXISTS)
-		if ((k_uptime_get() - start) > CONFIG_IPC_SERVICE_ICMSG_BOND_NOTIFY_REPEAT_TO_MS) {
-#endif
-			(void)mbox_send_dt(&dev_data->cfg->mbox_tx, NULL);
-#if defined(CONFIG_SYS_CLOCK_EXISTS)
-			start = k_uptime_get();
-		};
-#endif
-	}
-}
-#endif
-
 #ifdef CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_SYNC
-static int reserve_tx_buffer_if_unused(struct icmsg_data_t *dev_data)
-{
-	int ret = k_mutex_lock(&dev_data->tx_lock, SHMEM_ACCESS_TO);
-
-	if (ret < 0) {
-		return ret;
-	}
-
+	return k_mutex_lock(&dev_data->tx_lock, SHMEM_ACCESS_TO);
+#else
 	return 0;
+#endif
 }
 
-static int release_tx_buffer(struct icmsg_data_t *dev_data)
+static inline int release_tx_buffer(struct icmsg_data_t *dev_data)
 {
+#ifdef CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_SYNC
 	return k_mutex_unlock(&dev_data->tx_lock);
-}
+#else
+	return 0;
 #endif
+}
 
 static uint32_t data_available(struct icmsg_data_t *dev_data)
 {
@@ -135,103 +121,242 @@ static void submit_mbox_work(struct icmsg_data_t *dev_data)
 	}
 }
 
-static void submit_work_if_buffer_free(struct icmsg_data_t *dev_data)
-{
-	submit_mbox_work(dev_data);
-}
+#endif
 
-static void submit_work_if_buffer_free_and_data_available(
-		struct icmsg_data_t *dev_data)
+static int initialize_tx_with_sid_disabled(struct icmsg_data_t *dev_data)
 {
-	if (!data_available(dev_data)) {
-		return;
+	int ret;
+
+	ret = pbuf_tx_init(dev_data->tx_pb);
+
+	if (ret < 0) {
+		__ASSERT(false, "Incorrect Tx configuration");
+		return ret;
 	}
 
-	submit_mbox_work(dev_data);
-}
-#else
-static void submit_if_buffer_free(struct icmsg_data_t *dev_data)
-{
-	mbox_callback_process(dev_data);
-}
+	ret = pbuf_write(dev_data->tx_pb, magic, sizeof(magic));
 
-static void submit_if_buffer_free_and_data_available(
-		struct icmsg_data_t *dev_data)
-{
+	if (ret < 0) {
+		__ASSERT_NO_MSG(false);
+		return ret;
+	}
 
-	if (!data_available(dev_data)) {
-		return;
+	if (ret < (int)sizeof(magic)) {
+		__ASSERT_NO_MSG(ret == sizeof(magic));
+		return -EINVAL;
 	}
 
-	mbox_callback_process(dev_data);
+	return 0;
 }
-#endif
 
-#ifdef CONFIG_MULTITHREADING
-static void mbox_callback_process(struct k_work *item)
-#else
-static void mbox_callback_process(struct icmsg_data_t *dev_data)
-#endif
+static bool callback_process(struct icmsg_data_t *dev_data)
 {
-#ifdef CONFIG_MULTITHREADING
-	struct icmsg_data_t *dev_data = CONTAINER_OF(item, struct icmsg_data_t, mbox_work);
-#endif
+	int ret;
 	uint8_t rx_buffer[CONFIG_PBUF_RX_READ_BUF_SIZE] __aligned(4);
-
+	uint32_t len = 0;
+	uint32_t len_available;
+	bool rerun = false;
+	bool notify_remote = false;
 	atomic_t state = atomic_get(&dev_data->state);
 
-	uint32_t len = data_available(dev_data);
-
-	if (len == 0) {
-		/* Unlikely, no data in buffer. */
-		return;
+	switch (state) {
+
+#if UNBOUND_DETECT
+	case ICMSG_STATE_INITIALIZING_SID_DETECT: {
+		/* Initialization with detection of remote session awareness */
+		volatile char *magic_buf;
+		uint16_t magic_len;
+
+		ret = pbuf_get_initial_buf(dev_data->rx_pb, &magic_buf, &magic_len);
+
+		if (ret == 0 && magic_len == sizeof(magic) &&
+		    memcmp((void *)magic_buf, magic, sizeof(magic)) == 0) {
+			/* Remote initialized in session-unaware mode, so we do old way of
+			 * initialization.
+			 */
+			ret = initialize_tx_with_sid_disabled(dev_data);
+			if (ret < 0) {
+				if (dev_data->cb->error) {
+					dev_data->cb->error("Incorrect Tx configuration",
+							    dev_data->ctx);
+				}
+				__ASSERT(false, "Incorrect Tx configuration");
+				atomic_set(&dev_data->state, ICMSG_STATE_OFF);
+				return false;
+			}
+			/* We got magic data, so we can handle it later. */
+			notify_remote = true;
+			rerun = true;
+			atomic_set(&dev_data->state, ICMSG_STATE_INITIALIZING_SID_DISABLED);
+			break;
+		}
+		/* If remote did not initialize the RX in session-unaware mode, we can try
+		 * with session-aware initialization.
+		 */
+		__fallthrough;
 	}
+#endif /* UNBOUND_DETECT */
+
+#if UNBOUND_ENABLED || UNBOUND_DETECT
+	case ICMSG_STATE_INITIALIZING_SID_ENABLED: {
+		uint32_t tx_handshake = pbuf_handshake_read(dev_data->tx_pb);
+		uint32_t remote_sid_req = REMOTE_SID_REQ_FROM_TX(tx_handshake);
+		uint32_t local_sid_ack = LOCAL_SID_ACK_FROM_TX(tx_handshake);
+
+		if (remote_sid_req != dev_data->remote_sid && remote_sid_req != SID_DISCONNECTED) {
+			/* We can now initialize TX, since we know that remote, during receiving,
+			 * will first read FIFO indexes and later, it will check if session has
+			 * changed before using indexes to receive the message. Additionally,
+			 * we know that remote after session request change will no try to receive
+			 * more data.
+			 */
+			ret = pbuf_tx_init(dev_data->tx_pb);
+			if (ret < 0) {
+				if (dev_data->cb->error) {
+					dev_data->cb->error("Incorrect Tx configuration",
+						dev_data->ctx);
+				}
+				__ASSERT(false, "Incorrect Tx configuration");
+				atomic_set(&dev_data->state, ICMSG_STATE_DISCONNECTED);
+				return false;
+			}
+			/* Acknowledge the remote session. */
+			dev_data->remote_sid = remote_sid_req;
+			pbuf_handshake_write(dev_data->rx_pb,
+				MAKE_RX_HANDSHAKE(dev_data->local_sid, dev_data->remote_sid));
+			notify_remote = true;
+		}
 
-	__ASSERT_NO_MSG(len <= sizeof(rx_buffer));
+		if (local_sid_ack == dev_data->local_sid &&
+		    dev_data->remote_sid != SID_DISCONNECTED) {
+			/* We send acknowledge to remote, receive acknowledge from remote,
+			 * so we are ready.
+			 */
+			atomic_set(&dev_data->state, ICMSG_STATE_CONNECTED_SID_ENABLED);
+
+			if (dev_data->cb->bound) {
+				dev_data->cb->bound(dev_data->ctx);
+			}
+			/* Re-run this handler, because remote may already send something. */
+			rerun = true;
+			notify_remote = true;
+		}
 
-	if (sizeof(rx_buffer) < len) {
-		return;
+		break;
 	}
+#endif /* UNBOUND_ENABLED || UNBOUND_DETECT */
 
-	len = pbuf_read(dev_data->rx_pb, rx_buffer, sizeof(rx_buffer));
+#if UNBOUND_ENABLED || UNBOUND_DETECT
+	case ICMSG_STATE_CONNECTED_SID_ENABLED:
+#endif
+#if UNBOUND_DISABLED || UNBOUND_DETECT
+	case ICMSG_STATE_CONNECTED_SID_DISABLED:
+#endif
+#if UNBOUND_DISABLED
+	case ICMSG_STATE_INITIALIZING_SID_DISABLED:
+#endif
+
+		len_available = data_available(dev_data);
 
-	if (state == ICMSG_STATE_READY) {
-		if (dev_data->cb->received) {
-			dev_data->cb->received(rx_buffer, len, dev_data->ctx);
+		if (len_available > 0 && sizeof(rx_buffer) >= len_available) {
+			len = pbuf_read(dev_data->rx_pb, rx_buffer, sizeof(rx_buffer));
+		}
+
+		if (state == ICMSG_STATE_CONNECTED_SID_ENABLED &&
+		    (UNBOUND_ENABLED || UNBOUND_DETECT)) {
+			/* The incoming message is valid only if remote session is as expected,
+			 * so we need to check remote session now.
+			 */
+			uint32_t remote_sid_req = REMOTE_SID_REQ_FROM_TX(
+				pbuf_handshake_read(dev_data->tx_pb));
+
+			if (remote_sid_req != dev_data->remote_sid) {
+				atomic_set(&dev_data->state, ICMSG_STATE_DISCONNECTED);
+				if (dev_data->cb->unbound) {
+					dev_data->cb->unbound(dev_data->ctx);
+				}
+				return false;
+			}
+		}
+
+		if (len_available == 0) {
+			/* Unlikely, no data in buffer. */
+			return false;
 		}
-	} else {
-		__ASSERT_NO_MSG(state == ICMSG_STATE_BUSY);
 
-		/* Allow magic number longer than sizeof(magic) for future protocol version. */
-		bool endpoint_invalid = (len < sizeof(magic) ||
-					memcmp(magic, rx_buffer, sizeof(magic)));
+		__ASSERT_NO_MSG(len_available <= sizeof(rx_buffer));
 
-		if (endpoint_invalid) {
-			__ASSERT_NO_MSG(false);
-			return;
+		if (sizeof(rx_buffer) < len_available) {
+			return false;
 		}
 
-		if (dev_data->cb->bound) {
-			dev_data->cb->bound(dev_data->ctx);
+		if (state != ICMSG_STATE_INITIALIZING_SID_DISABLED || !UNBOUND_DISABLED) {
+			if (dev_data->cb->received) {
+				dev_data->cb->received(rx_buffer, len, dev_data->ctx);
+			}
+		} else {
+			/* Allow magic number longer than sizeof(magic) for future protocol
+			 * version.
+			 */
+			bool endpoint_invalid = (len < sizeof(magic) ||
+						memcmp(magic, rx_buffer, sizeof(magic)));
+
+			if (endpoint_invalid) {
+				__ASSERT_NO_MSG(false);
+				return false;
+			}
+
+			if (dev_data->cb->bound) {
+				dev_data->cb->bound(dev_data->ctx);
+			}
+
+			atomic_set(&dev_data->state, ICMSG_STATE_CONNECTED_SID_DISABLED);
+			notify_remote = true;
 		}
 
-		atomic_set(&dev_data->state, ICMSG_STATE_READY);
+		rerun = (data_available(dev_data) > 0);
+		break;
+
+	case ICMSG_STATE_OFF:
+	case ICMSG_STATE_DISCONNECTED:
+	default:
+		/* Nothing to do in this state. */
+		return false;
 	}
+
+	if (notify_remote) {
+		(void)mbox_send_dt(&dev_data->cfg->mbox_tx, NULL);
+	}
+
+	return rerun;
+}
+
 #ifdef CONFIG_MULTITHREADING
-	submit_work_if_buffer_free_and_data_available(dev_data);
-#else
-	submit_if_buffer_free_and_data_available(dev_data);
-#endif
+static void workq_callback_process(struct k_work *item)
+{
+	bool rerun;
+	struct icmsg_data_t *dev_data = CONTAINER_OF(item, struct icmsg_data_t, mbox_work);
+
+	rerun = callback_process(dev_data);
+	if (rerun) {
+		submit_mbox_work(dev_data);
+	}
 }
+#endif /* def CONFIG_MULTITHREADING */
 
 static void mbox_callback(const struct device *instance, uint32_t channel,
 			  void *user_data, struct mbox_msg *msg_data)
 {
+	bool rerun;
 	struct icmsg_data_t *dev_data = user_data;
+
 #ifdef CONFIG_MULTITHREADING
-	submit_work_if_buffer_free(dev_data);
+	ARG_UNUSED(rerun);
+	submit_mbox_work(dev_data);
 #else
-	submit_if_buffer_free(dev_data);
+	do {
+		rerun = callback_process(dev_data);
+	} while (rerun);
 #endif
 }
 
@@ -241,8 +366,7 @@ static int mbox_init(const struct icmsg_config_t *conf,
 	int err;
 
 #ifdef CONFIG_MULTITHREADING
-	k_work_init(&dev_data->mbox_work, mbox_callback_process);
-	k_work_init_delayable(&dev_data->notify_work, notify_process);
+	k_work_init(&dev_data->mbox_work, workq_callback_process);
 #endif
 
 	err = mbox_register_callback_dt(&conf->mbox_rx, mbox_callback, dev_data);
@@ -257,9 +381,27 @@ int icmsg_open(const struct icmsg_config_t *conf,
 	       struct icmsg_data_t *dev_data,
 	       const struct ipc_service_cb *cb, void *ctx)
 {
-	if (!atomic_cas(&dev_data->state, ICMSG_STATE_OFF, ICMSG_STATE_BUSY)) {
-		/* Already opened. */
-		return -EALREADY;
+	int ret;
+	enum icmsg_state old_state;
+
+	__ASSERT(conf->unbound_mode != ICMSG_UNBOUND_MODE_DISABLE || UNBOUND_DISABLED,
+		 "Unbound mode \"disabled\" is was forbidden in Kconfig.");
+	__ASSERT(conf->unbound_mode != ICMSG_UNBOUND_MODE_ENABLE || UNBOUND_ENABLED,
+		 "Unbound mode \"enabled\" is was forbidden in Kconfig.");
+	__ASSERT(conf->unbound_mode != ICMSG_UNBOUND_MODE_DETECT || UNBOUND_DETECT,
+		 "Unbound mode \"detect\" is was forbidden in Kconfig.");
+
+	if (conf->unbound_mode == ICMSG_UNBOUND_MODE_DISABLE ||
+	    !(UNBOUND_ENABLED || UNBOUND_DETECT)) {
+		if (!atomic_cas(&dev_data->state, ICMSG_STATE_OFF,
+				ICMSG_STATE_INITIALIZING_SID_DISABLED)) {
+			/* Already opened. */
+			return -EALREADY;
+		}
+		old_state = ICMSG_STATE_OFF;
+	} else {
+		/* Unbound mode has the same values as ICMSG_STATE_INITIALIZING_* */
+		old_state = atomic_set(&dev_data->state, conf->unbound_mode);
 	}
 
 	dev_data->cb = cb;
@@ -270,60 +412,82 @@ int icmsg_open(const struct icmsg_config_t *conf,
 	k_mutex_init(&dev_data->tx_lock);
 #endif
 
-	int ret = pbuf_tx_init(dev_data->tx_pb);
-
-	if (ret < 0) {
-		__ASSERT(false, "Incorrect Tx configuration");
-		return ret;
-	}
-
 	ret = pbuf_rx_init(dev_data->rx_pb);
 
 	if (ret < 0) {
 		__ASSERT(false, "Incorrect Rx configuration");
-		return ret;
+		goto cleanup_and_exit;
 	}
 
-	ret = pbuf_write(dev_data->tx_pb, magic, sizeof(magic));
-
-	if (ret < 0) {
-		__ASSERT_NO_MSG(false);
-		return ret;
+	if (conf->unbound_mode != ICMSG_UNBOUND_MODE_DISABLE &&
+	    (UNBOUND_ENABLED || UNBOUND_DETECT)) {
+		/* Increment local session id without conflicts with forbidden values. */
+		uint32_t local_sid_ack =
+			LOCAL_SID_ACK_FROM_TX(pbuf_handshake_read(dev_data->tx_pb));
+		dev_data->local_sid =
+			LOCAL_SID_REQ_FROM_RX(pbuf_handshake_read(dev_data->tx_pb));
+		dev_data->remote_sid = SID_DISCONNECTED;
+		do {
+			dev_data->local_sid = (dev_data->local_sid + 1) & 0xFFFF;
+		} while (dev_data->local_sid == local_sid_ack ||
+			 dev_data->local_sid == SID_DISCONNECTED);
+		/* Write local session id request without remote acknowledge */
+		pbuf_handshake_write(dev_data->rx_pb,
+			MAKE_RX_HANDSHAKE(dev_data->local_sid, SID_DISCONNECTED));
+	} else if (UNBOUND_DISABLED) {
+		ret = initialize_tx_with_sid_disabled(dev_data);
 	}
 
-	if (ret < (int)sizeof(magic)) {
-		__ASSERT_NO_MSG(ret == sizeof(magic));
-		return ret;
+	if (old_state == ICMSG_STATE_OFF && (UNBOUND_ENABLED || UNBOUND_DETECT)) {
+		/* Initialize mbox only if we are doing first-time open (not re-open
+		 * after unbound)
+		 */
+		ret = mbox_init(conf, dev_data);
+		if (ret) {
+			goto cleanup_and_exit;
+		}
 	}
 
-	ret = mbox_init(conf, dev_data);
-	if (ret) {
-		return ret;
-	}
-#ifdef CONFIG_MULTITHREADING
-	ret = k_work_schedule_for_queue(workq, &dev_data->notify_work, K_NO_WAIT);
+	/* We need to send a notification to remote, it may not be delivered
+	 * since it may be uninitialized yet, but when it finishes the initialization
+	 * we get a notification from it. We need to send this notification in callback
+	 * again to make sure that it arrived.
+	 */
+	ret = mbox_send_dt(&conf->mbox_tx, NULL);
+
 	if (ret < 0) {
-		return ret;
+		__ASSERT(false, "Cannot send mbox notification");
+		goto cleanup_and_exit;
 	}
-#else
-	notify_process(dev_data);
-#endif
-	return 0;
+
+	return ret;
+
+cleanup_and_exit:
+	atomic_set(&dev_data->state, ICMSG_STATE_OFF);
+	return ret;
 }
 
 int icmsg_close(const struct icmsg_config_t *conf,
 		struct icmsg_data_t *dev_data)
 {
-	int ret;
+	int ret = 0;
+	enum icmsg_state old_state;
 
-	ret = mbox_deinit(conf, dev_data);
-	if (ret) {
-		return ret;
+	if (conf->unbound_mode != ICMSG_UNBOUND_MODE_DISABLE &&
+	    (UNBOUND_ENABLED || UNBOUND_DETECT)) {
+		pbuf_handshake_write(dev_data->rx_pb,
+			MAKE_RX_HANDSHAKE(SID_DISCONNECTED, SID_DISCONNECTED));
 	}
 
-	atomic_set(&dev_data->state, ICMSG_STATE_OFF);
+	(void)mbox_send_dt(&conf->mbox_tx, NULL);
 
-	return 0;
+	old_state = atomic_set(&dev_data->state, ICMSG_STATE_OFF);
+
+	if (old_state != ICMSG_STATE_OFF) {
+		ret = mbox_deinit(conf, dev_data);
+	}
+
+	return ret;
 }
 
 int icmsg_send(const struct icmsg_config_t *conf,
@@ -332,13 +496,15 @@ int icmsg_send(const struct icmsg_config_t *conf,
 {
 	int ret;
 	int write_ret;
-#ifdef CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_SYNC
 	int release_ret;
-#endif
 	int sent_bytes;
+	uint32_t state = atomic_get(&dev_data->state);
 
-	if (!is_endpoint_ready(dev_data)) {
-		return -EBUSY;
+	if (!is_endpoint_ready(state)) {
+		/* If instance was disconnected on the remote side, some threads may still
+		 * don't know it yet and still may try to send messages.
+		 */
+		return (state == ICMSG_STATE_DISCONNECTED) ? len : -EBUSY;
 	}
 
 	/* Empty message is not allowed */
@@ -346,19 +512,15 @@ int icmsg_send(const struct icmsg_config_t *conf,
 		return -ENODATA;
 	}
 
-#ifdef CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_SYNC
 	ret = reserve_tx_buffer_if_unused(dev_data);
 	if (ret < 0) {
 		return -ENOBUFS;
 	}
-#endif
 
 	write_ret = pbuf_write(dev_data->tx_pb, msg, len);
 
-#ifdef CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_SYNC
 	release_ret = release_tx_buffer(dev_data);
 	__ASSERT_NO_MSG(!release_ret);
-#endif
 
 	if (write_ret < 0) {
 		return write_ret;
diff --git a/subsys/ipc/ipc_service/lib/pbuf.c b/subsys/ipc/ipc_service/lib/pbuf.c
index c744946f4ca..d45c86bcd51 100644
--- a/subsys/ipc/ipc_service/lib/pbuf.c
+++ b/subsys/ipc/ipc_service/lib/pbuf.c
@@ -15,7 +15,7 @@
 #include <soc.h>
 #endif
 
-/* Helper funciton for getting numer of bytes being written to the bufer. */
+/* Helper function for getting number of bytes being written to the buffer. */
 static uint32_t idx_occupied(uint32_t len, uint32_t wr_idx, uint32_t rd_idx)
 {
 	/* It is implicitly assumed wr_idx and rd_idx cannot differ by more then len. */
@@ -38,6 +38,7 @@ static int validate_cfg(const struct pbuf_cfg *cfg)
 	/* Validate pointer alignment. */
 	if (!IS_PTR_ALIGNED_BYTES(cfg->rd_idx_loc, MAX(cfg->dcache_alignment, _PBUF_IDX_SIZE)) ||
 	    !IS_PTR_ALIGNED_BYTES(cfg->wr_idx_loc, MAX(cfg->dcache_alignment, _PBUF_IDX_SIZE)) ||
+	    !IS_PTR_ALIGNED_BYTES(cfg->handshake_loc, _PBUF_IDX_SIZE) ||
 	    !IS_PTR_ALIGNED_BYTES(cfg->data_loc, _PBUF_IDX_SIZE)) {
 		return -EINVAL;
 	}
@@ -49,6 +50,8 @@ static int validate_cfg(const struct pbuf_cfg *cfg)
 
 	/* Validate pointer values. */
 	if (!(cfg->rd_idx_loc < cfg->wr_idx_loc) ||
+	    (cfg->handshake_loc && !(cfg->rd_idx_loc < cfg->handshake_loc)) ||
+	    !(cfg->handshake_loc < cfg->wr_idx_loc) ||
 	    !((uint8_t *)cfg->wr_idx_loc < cfg->data_loc) ||
 	    !(((uint8_t *)cfg->rd_idx_loc + MAX(_PBUF_IDX_SIZE, cfg->dcache_alignment)) ==
 	    (uint8_t *)cfg->wr_idx_loc)) {
@@ -176,6 +179,44 @@ int pbuf_write(struct pbuf *pb, const char *data, uint16_t len)
 	return len;
 }
 
+int pbuf_get_initial_buf(struct pbuf *pb, volatile char **buf, uint16_t *len)
+{
+	uint32_t wr_idx;
+	uint16_t plen;
+
+	if (pb == NULL || pb->data.rd_idx != 0) {
+		/* Incorrect call. */
+		return -EINVAL;
+	}
+
+	sys_cache_data_invd_range((void *)(pb->cfg->wr_idx_loc), sizeof(*(pb->cfg->wr_idx_loc)));
+	__sync_synchronize();
+
+	wr_idx = *(pb->cfg->wr_idx_loc);
+	if (wr_idx >= pb->cfg->len || wr_idx > 0xFFFF || wr_idx == 0) {
+		/* Wrong index - probably pbuf was not initialized or message was not send yet. */
+		return -EINVAL;
+	}
+
+	sys_cache_data_invd_range((void *)(pb->cfg->data_loc), PBUF_PACKET_LEN_SZ);
+	__sync_synchronize();
+
+	plen = sys_get_be16(&pb->cfg->data_loc[0]);
+
+	if (plen + 4 > wr_idx) {
+		/* Wrong length - probably pbuf was not initialized or message was not send yet. */
+		return -EINVAL;
+	}
+
+	*buf = &pb->cfg->data_loc[PBUF_PACKET_LEN_SZ];
+	*len = plen;
+
+	sys_cache_data_invd_range((void *)*buf, plen);
+	__sync_synchronize();
+
+	return 0;
+}
+
 int pbuf_read(struct pbuf *pb, char *buf, uint16_t len)
 {
 	if (pb == NULL) {
@@ -253,3 +294,23 @@ int pbuf_read(struct pbuf *pb, char *buf, uint16_t len)
 
 	return len;
 }
+
+uint32_t pbuf_handshake_read(struct pbuf *pb)
+{
+	volatile uint32_t *ptr = pb->cfg->handshake_loc;
+
+	__ASSERT_NO_MSG(ptr);
+	sys_cache_data_invd_range((void *)ptr, sizeof(*ptr));
+	__sync_synchronize();
+	return *ptr;
+}
+
+void pbuf_handshake_write(struct pbuf *pb, uint32_t value)
+{
+	volatile uint32_t *ptr = pb->cfg->handshake_loc;
+
+	__ASSERT_NO_MSG(ptr);
+	*ptr = value;
+	__sync_synchronize();
+	sys_cache_data_flush_range((void *)ptr, sizeof(*ptr));
+}
diff --git a/subsys/jwt/Kconfig b/subsys/jwt/Kconfig
index 367ba43d225..052908a7775 100644
--- a/subsys/jwt/Kconfig
+++ b/subsys/jwt/Kconfig
@@ -20,6 +20,10 @@ config JWT_SIGN_RSA_LEGACY
 	bool "Use RSA signature (RS-256). Use Mbed TLS as crypto library."
 	depends on CSPRNG_AVAILABLE
 	select MBEDTLS
+	select MBEDTLS_MD
+	select MBEDTLS_RSA_C
+	select MBEDTLS_PKCS1_V15
+	select MBEDTLS_PKCS1_V21
 	select MBEDTLS_KEY_EXCHANGE_RSA_ENABLED
 
 config JWT_SIGN_RSA_PSA
diff --git a/subsys/llext/Kconfig b/subsys/llext/Kconfig
index 0e3ce5dd57d..2b0baa0c5e7 100644
--- a/subsys/llext/Kconfig
+++ b/subsys/llext/Kconfig
@@ -86,6 +86,14 @@ config LLEXT_EXPORT_DEVICES
 	  When enabled, all Zephyr devices defined in the device tree are
 	  made available to llexts via the standard DT_ / DEVICE_* macros.
 
+config LLEXT_EXPORT_DEV_IDS_BY_HASH
+	bool "Use hash of device path in device name"
+	depends on LLEXT_EXPORT_DEVICES
+	help
+	  When enabled, exported device names are generated from a hash of the
+	  node path instead of an ordinal number. Identifiers generated this
+	  way are stable across rebuilds.
+
 config LLEXT_EXPORT_BUILTINS_BY_SLID
 	bool "Export built-in symbols to llexts via SLIDs"
 	help
@@ -101,29 +109,74 @@ config LLEXT_EXPORT_BUILTINS_BY_SLID
 	  up symbols from the built-in table by name. It also
 	  requires the LLEXTs to be post-processed after build.
 
+config LLEXT_IMPORT_ALL_GLOBALS
+	bool "Import all global symbols from extensions"
+	help
+	  When loading an extension, by default only symbols that are mentioned
+	  in the '.exported_sym' section (possibly via EXPORT_SYMBOL) are made
+	  available to the Zephyr core.
+
+	  This option instead allows all global symbols from extensions to be
+	  used by the main application. This is useful to load basic extensions
+	  that have been compiled without the full Zephyr EDK.
+
 module = LLEXT
 module-str = llext
 source "subsys/logging/Kconfig.template.log_config"
 
 endif
 
-menu "Linkable loadable Extension Development Kit (EDK)"
+menuconfig LLEXT_EDK
+	bool "Linkable loadable Extension Development Kit (EDK)"
+	default y if LLEXT
+	help
+	  Enable the generation of an Extension Development Kit (EDK) for the
+	  Linkable Loadable Extension subsystem. The EDK is an archive that
+	  contains the necessary files and build settings to build extensions
+	  for Zephyr without the need to have the full Zephyr source tree.
+
+if LLEXT_EDK
 
 config LLEXT_EDK_NAME
 	string "Name for llext EDK (Extension Development Kit)"
 	default "llext-edk"
 	help
-	  Name will be used when generating the EDK file, as <name>.tar.xz.
+	  <name> will be used when generating the EDK file; the appropriate
+	  extension will be appended depending on the chosen output format.
 	  It will also be used, normalized, as the prefix for the variable
 	  stating EDK location, used on generated Makefile.cflags. For
 	  instance, the default name, "llext-edk", becomes LLEXT_EDK_INSTALL_DIR.
 
+choice LLEXT_EDK_FORMAT
+prompt "EDK compression and output format"
+default LLEXT_EDK_FORMAT_TAR_XZ
+
+config LLEXT_EDK_FORMAT_TAR_XZ
+	bool ".tar.xz"
+	help
+	  Use GNU tar with XZ compression for the EDK file. Highest compression
+	  ratio, slower choice.
+
+config LLEXT_EDK_FORMAT_TAR_ZSTD
+	bool ".tar.Z"
+	help
+	  Use GNU tar with Zstd compression for the EDK file. Way faster than
+	  XZ, but still with a high compression ratio.
+
+config LLEXT_EDK_FORMAT_ZIP
+	bool ".zip"
+	help
+	  Use Zip format and compression for the EDK file. This is the most
+	  portable option, but it may not compress as well as XZ or Zstd.
+
+endchoice
+
 config LLEXT_EDK_USERSPACE_ONLY
-	bool "Only generate the Userpace codepath on syscall stubs for the EDK"
+	bool "Only generate the Userspace codepath on syscall stubs for the EDK"
 	help
 	  Syscall stubs can contain code that verifies if running code is at user
 	  or kernel space and route the call accordingly. If the EDK is expected
 	  to be used by userspace only extensions, this option will make EDK stubs
 	  not contain the routing code, and only generate the userspace one.
 
-endmenu
+endif
diff --git a/subsys/llext/llext.c b/subsys/llext/llext.c
index c1871a0c6f0..83148025b77 100644
--- a/subsys/llext/llext.c
+++ b/subsys/llext/llext.c
@@ -23,32 +23,36 @@ static sys_slist_t _llext_list = SYS_SLIST_STATIC_INIT(&_llext_list);
 
 static struct k_mutex llext_lock = Z_MUTEX_INITIALIZER(llext_lock);
 
-int llext_get_section_header(struct llext_loader *ldr, struct llext *ext, const char *search_name,
-			     elf_shdr_t *shdr)
+int llext_section_shndx(const struct llext_loader *ldr, const struct llext *ext,
+			const char *sect_name)
 {
-	const elf_shdr_t *tmp;
 	unsigned int i;
 
-	for (i = 0, tmp = ext->sect_hdrs;
-	     i < ext->sect_cnt;
-	     i++, tmp++) {
-		const char *name = llext_peek(ldr,
-					      ldr->sects[LLEXT_MEM_SHSTRTAB].sh_offset +
-					      tmp->sh_name);
+	for (i = 1; i < ext->sect_cnt; i++) {
+		const char *name = llext_section_name(ldr, ext, ext->sect_hdrs + i);
 
-		if (!name) {
-			return -ENOTSUP;
-		}
-
-		if (!strcmp(name, search_name)) {
-			*shdr = *tmp;
-			return 0;
+		if (!strcmp(name, sect_name)) {
+			return i;
 		}
 	}
 
 	return -ENOENT;
 }
 
+int llext_get_section_header(struct llext_loader *ldr, struct llext *ext, const char *search_name,
+			     elf_shdr_t *shdr)
+{
+	int ret;
+
+	ret = llext_section_shndx(ldr, ext, search_name);
+	if (ret < 0) {
+		return ret;
+	}
+
+	*shdr = ext->sect_hdrs[ret];
+	return 0;
+}
+
 ssize_t llext_find_section(struct llext_loader *ldr, const char *search_name)
 {
 	elf_shdr_t *shdr;
@@ -91,7 +95,7 @@ struct llext *llext_by_name(const char *name)
 	     node = sys_slist_peek_next(node)) {
 		struct llext *ext = CONTAINER_OF(node, struct llext, _llext_list);
 
-		if (strncmp(ext->name, name, sizeof(ext->name)) == 0) {
+		if (strncmp(ext->name, name, LLEXT_MAX_NAME_LEN) == 0) {
 			k_mutex_unlock(&llext_lock);
 			return ext;
 		}
@@ -189,8 +193,9 @@ int llext_load(struct llext_loader *ldr, const char *name, struct llext **ext,
 		goto out;
 	}
 
-	strncpy((*ext)->name, name, sizeof((*ext)->name));
-	(*ext)->name[sizeof((*ext)->name) - 1] = '\0';
+	/* The (*ext)->name array is LLEXT_MAX_NAME_LEN + 1 bytes long */
+	strncpy((*ext)->name, name, LLEXT_MAX_NAME_LEN);
+	(*ext)->name[LLEXT_MAX_NAME_LEN] = '\0';
 	(*ext)->use_count++;
 
 	sys_slist_append(&_llext_list, &(*ext)->_llext_list);
@@ -203,60 +208,17 @@ int llext_load(struct llext_loader *ldr, const char *name, struct llext **ext,
 
 #include <zephyr/logging/log_ctrl.h>
 
-static void llext_log_flush(void)
-{
-#ifdef CONFIG_LOG_MODE_DEFERRED
-	extern struct k_thread logging_thread;
-	int cur_prio = k_thread_priority_get(k_current_get());
-	int log_prio = k_thread_priority_get(&logging_thread);
-	int target_prio;
-	bool adjust_cur, adjust_log;
-
-	/*
-	 * Our goal is to raise the logger thread priority above current, but if
-	 * current has the highest possble priority, both need to be adjusted,
-	 * particularly if the logger thread has the lowest possible priority
-	 */
-	if (log_prio < cur_prio) {
-		adjust_cur = false;
-		adjust_log = false;
-		target_prio = 0;
-	} else if (cur_prio == K_HIGHEST_THREAD_PRIO) {
-		adjust_cur = true;
-		adjust_log = true;
-		target_prio = cur_prio;
-		k_thread_priority_set(k_current_get(), cur_prio + 1);
-	} else {
-		adjust_cur = false;
-		adjust_log = true;
-		target_prio = cur_prio - 1;
-	}
-
-	/* adjust logging thread priority if needed */
-	if (adjust_log) {
-		k_thread_priority_set(&logging_thread, target_prio);
-	}
-
-	log_thread_trigger();
-	k_yield();
-
-	if (adjust_log) {
-		k_thread_priority_set(&logging_thread, log_prio);
-	}
-	if (adjust_cur) {
-		k_thread_priority_set(&logging_thread, cur_prio);
-	}
-#endif
-}
-
 int llext_unload(struct llext **ext)
 {
 	__ASSERT(*ext, "Expected non-null extension");
 	struct llext *tmp = *ext;
 
-	k_mutex_lock(&llext_lock, K_FOREVER);
+	/* Flush pending log messages, as the deferred formatting may be referencing
+	 * strings/args in the extension we are about to unload
+	 */
+	log_flush();
 
-	llext_log_flush();
+	k_mutex_lock(&llext_lock, K_FOREVER);
 
 	__ASSERT(tmp->use_count, "A valid LLEXT cannot have a zero use-count!");
 
diff --git a/subsys/llext/llext_link.c b/subsys/llext/llext_link.c
index 2cd038dfb11..5d37172c08e 100644
--- a/subsys/llext/llext_link.c
+++ b/subsys/llext/llext_link.c
@@ -26,8 +26,8 @@ LOG_MODULE_DECLARE(llext, CONFIG_LLEXT_LOG_LEVEL);
 #define SYM_NAME_OR_SLID(name, slid) name
 #endif
 
-__weak int arch_elf_relocate(elf_rela_t *rel, uintptr_t loc,
-			     uintptr_t sym_base_addr, const char *sym_name, uintptr_t load_bias)
+__weak int arch_elf_relocate(struct llext_loader *ldr, struct llext *ext, elf_rela_t *rel,
+			     const elf_shdr_t *shdr)
 {
 	return -ENOTSUP;
 }
@@ -48,7 +48,7 @@ __weak void arch_elf_relocate_global(struct llext_loader *ldr, struct llext *ext
  * Find the memory region containing the supplied offset and return the
  * corresponding file offset
  */
-static size_t llext_file_offset(struct llext_loader *ldr, size_t offset)
+ssize_t llext_file_offset(struct llext_loader *ldr, uintptr_t offset)
 {
 	unsigned int i;
 
@@ -59,7 +59,7 @@ static size_t llext_file_offset(struct llext_loader *ldr, size_t offset)
 		}
 	}
 
-	return offset;
+	return -ENOEXEC;
 }
 
 /*
@@ -142,6 +142,92 @@ static const void *llext_find_extension_sym(const char *sym_name, struct llext *
 	return se.addr;
 }
 
+/*
+ * Read the symbol entry corresponding to a relocation from the binary.
+ */
+int llext_read_symbol(struct llext_loader *ldr, struct llext *ext, const elf_rela_t *rel,
+		      elf_sym_t *sym)
+{
+	int ret;
+
+	ret = llext_seek(ldr, ldr->sects[LLEXT_MEM_SYMTAB].sh_offset
+		+ ELF_R_SYM(rel->r_info) * sizeof(elf_sym_t));
+	if (ret != 0) {
+		return ret;
+	}
+
+	ret = llext_read(ldr, sym, sizeof(elf_sym_t));
+
+	return ret;
+}
+
+/*
+ * Determine address of a symbol.
+ */
+int llext_lookup_symbol(struct llext_loader *ldr, struct llext *ext, uintptr_t *link_addr,
+			const elf_rela_t *rel, const elf_sym_t *sym, const char *name,
+			const elf_shdr_t *shdr)
+{
+	if (ELF_R_SYM(rel->r_info) == 0) {
+		/*
+		 * no symbol
+		 * example:  R_ARM_V4BX relocation, R_ARM_RELATIVE
+		 */
+		*link_addr = 0;
+	} else if (sym->st_shndx == SHN_UNDEF) {
+		/* If symbol is undefined, then we need to look it up */
+		*link_addr = (uintptr_t)llext_find_sym(NULL, SYM_NAME_OR_SLID(name, sym->st_value));
+
+		if (*link_addr == 0) {
+			/* Try loaded tables */
+			struct llext *dep;
+
+			*link_addr = (uintptr_t)llext_find_extension_sym(name, &dep);
+			if (*link_addr) {
+				llext_dependency_add(ext, dep);
+			}
+		}
+
+		if (*link_addr == 0) {
+			LOG_ERR("Undefined symbol with no entry in "
+				"symbol table %s, offset %zd, link section %d",
+				name, (size_t)rel->r_offset, shdr->sh_link);
+			return -ENODATA;
+		}
+
+		LOG_INF("found symbol %s at %#lx", name, *link_addr);
+	} else if (sym->st_shndx == SHN_ABS) {
+		/* Absolute symbol */
+		*link_addr = sym->st_value;
+	} else if ((sym->st_shndx < ldr->hdr.e_shnum) &&
+		   !IN_RANGE(sym->st_shndx, SHN_LORESERVE, SHN_HIRESERVE)) {
+		/* This check rejects all relocations whose target symbol has a section index higher
+		 * than the maximum possible in this ELF file, or belongs in the reserved range:
+		 * they will be caught by the `else` below and cause an error to be returned. This
+		 * aborts the LLEXT's loading and prevents execution of improperly relocated code,
+		 * which is dangerous.
+		 *
+		 * Note that the unsupported SHN_COMMON section is rejected as part of this check.
+		 * Also note that SHN_ABS would be rejected as well, but we want to handle it
+		 * properly: for this reason, this check must come AFTER handling the case where the
+		 * symbol's section index is SHN_ABS!
+		 *
+		 *
+		 * For regular symbols, the link address is obtained by adding st_value to the start
+		 * address of the section in which the target symbol resides.
+		 */
+		*link_addr =
+			(uintptr_t)llext_loaded_sect_ptr(ldr, ext, sym->st_shndx) + sym->st_value;
+	} else {
+		LOG_ERR("cannot apply relocation: "
+			"target symbol has unexpected section index %d (%#x)",
+			sym->st_shndx, sym->st_shndx);
+		return -ENOEXEC;
+	}
+
+	return 0;
+}
+
 static void llext_link_plt(struct llext_loader *ldr, struct llext *ext, elf_shdr_t *shdr,
 			   const struct llext_load_param *ldr_parm, elf_shdr_t *tgt)
 {
@@ -153,7 +239,7 @@ static void llext_link_plt(struct llext_loader *ldr, struct llext *ext, elf_shdr
 	uint8_t *text = ext->mem[LLEXT_MEM_TEXT];
 
 	LOG_DBG("Found %p in PLT %u size %zu cnt %u text %p",
-		(void *)llext_string(ldr, ext, LLEXT_MEM_SHSTRTAB, shdr->sh_name),
+		(void *)llext_section_name(ldr, ext, shdr),
 		shdr->sh_type, (size_t)shdr->sh_entsize, sh_cnt, (void *)text);
 
 	const elf_shdr_t *sym_shdr = ldr->sects + LLEXT_MEM_SYMTAB;
@@ -188,7 +274,7 @@ static void llext_link_plt(struct llext_loader *ldr, struct llext *ext, elf_shdr
 			ret = llext_read(ldr, &sym, sizeof(sym));
 		}
 
-		if (ret < 0) {
+		if (ret != 0) {
 			LOG_ERR("PLT: failed to read symbol table #%u RELA #%u, trying to continue",
 				j, i);
 			continue;
@@ -203,7 +289,7 @@ static void llext_link_plt(struct llext_loader *ldr, struct llext *ext, elf_shdr
 			continue;
 		}
 
-		const char *name = llext_string(ldr, ext, LLEXT_MEM_STRTAB, sym.st_name);
+		const char *name = llext_symbol_name(ldr, ext, &sym);
 
 		/*
 		 * Both r_offset and sh_addr are addresses for which the extension
@@ -213,9 +299,14 @@ static void llext_link_plt(struct llext_loader *ldr, struct llext *ext, elf_shdr
 		 * beginning of the .text section in the ELF file can be
 		 * applied to the memory location of mem[LLEXT_MEM_TEXT].
 		 *
-		 * This is valid only when CONFIG_LLEXT_STORAGE_WRITABLE=y
-		 * and peek() is usable on the source ELF file.
+		 * This is valid only for LLEXT_STORAGE_WRITABLE loaders
+		 * since the buffer will be directly modified.
 		 */
+		if (ldr->storage != LLEXT_STORAGE_WRITABLE) {
+			LOG_ERR("PLT: cannot link read-only ELF file");
+			continue;
+		}
+
 		uint8_t *rel_addr = (uint8_t *)ext->mem[LLEXT_MEM_TEXT] -
 			ldr->sects[LLEXT_MEM_TEXT].sh_offset;
 
@@ -224,7 +315,15 @@ static void llext_link_plt(struct llext_loader *ldr, struct llext *ext, elf_shdr
 			rel_addr += rela.r_offset + tgt->sh_offset;
 		} else {
 			/* Shared / dynamically linked ELF */
-			rel_addr += llext_file_offset(ldr, rela.r_offset);
+			ssize_t offset = llext_file_offset(ldr, rela.r_offset);
+
+			if (offset < 0) {
+				LOG_ERR("Offset %#zx not found in ELF, trying to continue",
+					(size_t)rela.r_offset);
+				continue;
+			}
+
+			rel_addr += offset;
 		}
 
 		uint32_t stb = ELF_ST_BIND(sym.st_info);
@@ -273,7 +372,6 @@ int llext_link(struct llext_loader *ldr, struct llext *ext, const struct llext_l
 {
 	uintptr_t sect_base = 0;
 	elf_rela_t rel;
-	elf_sym_t sym;
 	elf_word rel_cnt = 0;
 	const char *name;
 	int i, ret;
@@ -318,7 +416,7 @@ int llext_link(struct llext_loader *ldr, struct llext *ext, const struct llext_l
 
 		rel_cnt = shdr->sh_size / shdr->sh_entsize;
 
-		name = llext_string(ldr, ext, LLEXT_MEM_SHSTRTAB, shdr->sh_name);
+		name = llext_section_name(ldr, ext, shdr);
 
 		/*
 		 * FIXME: The Xtensa port is currently using a different way of
@@ -345,6 +443,11 @@ int llext_link(struct llext_loader *ldr, struct llext *ext, const struct llext_l
 			continue;
 		}
 
+		if (!(ext->sect_hdrs[shdr->sh_info].sh_flags & SHF_ALLOC)) {
+			/* ignore relocations acting on volatile (debug) sections */
+			continue;
+		}
+
 		LOG_DBG("relocation section %s (%d) acting on section %d has %zd relocations",
 			name, i, shdr->sh_info, (size_t)rel_cnt);
 
@@ -355,7 +458,7 @@ int llext_link(struct llext_loader *ldr, struct llext *ext, const struct llext_l
 			return -ENOEXEC;
 		}
 
-		sect_base = (uintptr_t)llext_loaded_sect_ptr(ldr, ext, shdr->sh_info);
+		sect_base = (uintptr_t) llext_loaded_sect_ptr(ldr, ext, shdr->sh_info);
 
 		for (int j = 0; j < rel_cnt; j++) {
 			/* get each relocation entry */
@@ -369,99 +472,46 @@ int llext_link(struct llext_loader *ldr, struct llext *ext, const struct llext_l
 				return ret;
 			}
 
-			/* get corresponding symbol */
-			ret = llext_seek(ldr, ldr->sects[LLEXT_MEM_SYMTAB].sh_offset
-				    + ELF_R_SYM(rel.r_info) * sizeof(elf_sym_t));
-			if (ret != 0) {
-				return ret;
-			}
-
-			ret = llext_read(ldr, &sym, sizeof(elf_sym_t));
-			if (ret != 0) {
-				return ret;
-			}
-
-			name = llext_string(ldr, ext, LLEXT_MEM_STRTAB, sym.st_name);
+#ifdef CONFIG_LLEXT_LOG_LEVEL
+			if (CONFIG_LLEXT_LOG_LEVEL >= LOG_LEVEL_INF) {
+				uintptr_t link_addr;
+				uintptr_t op_loc =
+					llext_get_reloc_instruction_location(ldr, ext,
+									     shdr->sh_info,
+									     &rel);
+				elf_sym_t sym;
 
-			LOG_DBG("relocation %d:%d info 0x%zx (type %zd, sym %zd) offset %zd "
-				"sym_name %s sym_type %d sym_bind %d sym_ndx %d",
-				i, j, (size_t)rel.r_info, (size_t)ELF_R_TYPE(rel.r_info),
-				(size_t)ELF_R_SYM(rel.r_info), (size_t)rel.r_offset,
-				name, ELF_ST_TYPE(sym.st_info),
-				ELF_ST_BIND(sym.st_info), sym.st_shndx);
+				ret = llext_read_symbol(ldr, ext, &rel, &sym);
 
-			uintptr_t link_addr, op_loc;
-
-			op_loc = sect_base + rel.r_offset;
+				if (ret != 0) {
+					return ret;
+				}
 
-			if (ELF_R_SYM(rel.r_info) == 0) {
-				/* no symbol ex: R_ARM_V4BX relocation, R_ARM_RELATIVE  */
-				link_addr = 0;
-			} else if (sym.st_shndx == SHN_UNDEF) {
-				/* If symbol is undefined, then we need to look it up */
-				link_addr = (uintptr_t)llext_find_sym(NULL,
-					SYM_NAME_OR_SLID(name, sym.st_value));
+				name = llext_symbol_name(ldr, ext, &sym);
 
-				if (link_addr == 0) {
-					/* Try loaded tables */
-					struct llext *dep;
+				ret = llext_lookup_symbol(ldr, ext, &link_addr, &rel, &sym, name,
+							  shdr);
 
-					link_addr = (uintptr_t)llext_find_extension_sym(name, &dep);
-					if (link_addr) {
-						llext_dependency_add(ext, dep);
-					}
+				if (ret != 0) {
+					LOG_ERR("Could not find symbol %s!", name);
+					return ret;
 				}
 
-				if (link_addr == 0) {
-					LOG_ERR("Undefined symbol with no entry in "
-						"symbol table %s, offset %zd, link section %d",
-						name, (size_t)rel.r_offset, shdr->sh_link);
-					return -ENODATA;
-				}
+				LOG_DBG("relocation %d:%d info %#zx (type %zd, sym %zd) offset %zd"
+					" sym_name %s sym_type %d sym_bind %d sym_ndx %d",
+					i, j, (size_t)rel.r_info, (size_t)ELF_R_TYPE(rel.r_info),
+					(size_t)ELF_R_SYM(rel.r_info), (size_t)rel.r_offset,
+					name, ELF_ST_TYPE(sym.st_info),
+					ELF_ST_BIND(sym.st_info), sym.st_shndx);
 
-				LOG_INF("found symbol %s at 0x%lx", name, link_addr);
-			} else if (sym.st_shndx == SHN_ABS) {
-				/* Absolute symbol */
-				link_addr = sym.st_value;
-			} else if ((sym.st_shndx < ldr->hdr.e_shnum) &&
-				!IN_RANGE(sym.st_shndx, SHN_LORESERVE, SHN_HIRESERVE)) {
-				/* This check rejects all relocations whose target symbol
-				 * has a section index higher than the maximum possible
-				 * in this ELF file, or belongs in the reserved range:
-				 * they will be caught by the `else` below and cause an
-				 * error to be returned. This aborts the LLEXT's loading
-				 * and prevents execution of improperly relocated code,
-				 * which is dangerous.
-				 *
-				 * Note that the unsupported SHN_COMMON section is rejected
-				 * as part of this check. Also note that SHN_ABS would be
-				 * rejected as well, but we want to handle it properly:
-				 * for this reason, this check must come AFTER handling
-				 * the case where the symbol's section index is SHN_ABS!
-				 *
-				 *
-				 * For regular symbols, the link address is obtained by
-				 * adding st_value to the start address of the section
-				 * in which the target symbol resides.
-				 */
-				link_addr = (uintptr_t)llext_loaded_sect_ptr(ldr, ext,
-									     sym.st_shndx)
-					    + sym.st_value;
-			} else {
-				LOG_ERR("rela section %d, entry %d: cannot apply relocation: "
-					"target symbol has unexpected section index %d (0x%X)",
-					i, j, sym.st_shndx, sym.st_shndx);
-				return -ENOEXEC;
+				LOG_INF("writing relocation type %d at %#lx with symbol %s (%#lx)",
+					(int)ELF_R_TYPE(rel.r_info), op_loc, name, link_addr);
 			}
+#endif /* CONFIG_LLEXT_LOG_LEVEL */
 
-			LOG_INF("writing relocation symbol %s type %zd sym %zd at addr 0x%lx "
-				"addr 0x%lx",
-				name, (size_t)ELF_R_TYPE(rel.r_info), (size_t)ELF_R_SYM(rel.r_info),
-				op_loc, link_addr);
 
 			/* relocation */
-			ret = arch_elf_relocate(&rel, op_loc, link_addr, name,
-					     (uintptr_t)ext->mem[LLEXT_MEM_TEXT]);
+			ret = arch_elf_relocate(ldr, ext, &rel, shdr);
 			if (ret != 0) {
 				return ret;
 			}
diff --git a/subsys/llext/llext_load.c b/subsys/llext/llext_load.c
index 06f4b9a2f97..c4c0b26c35e 100644
--- a/subsys/llext/llext_load.c
+++ b/subsys/llext/llext_load.c
@@ -112,6 +112,7 @@ static int llext_load_elf_data(struct llext_loader *ldr, struct llext *ext)
 		LOG_ERR("Failed to allocate section map, size %zu", sect_map_sz);
 		return -ENOMEM;
 	}
+	ext->alloc_size += sect_map_sz;
 	for (int i = 0; i < ext->sect_cnt; i++) {
 		ldr->sect_map[i].mem_idx = LLEXT_MEM_COUNT;
 		ldr->sect_map[i].offset = 0;
@@ -152,6 +153,8 @@ static int llext_load_elf_data(struct llext_loader *ldr, struct llext *ext)
 static int llext_find_tables(struct llext_loader *ldr, struct llext *ext)
 {
 	int table_cnt, i;
+	int shstrtab_ndx = ldr->hdr.e_shstrndx;
+	int strtab_ndx = -1;
 
 	memset(ldr->sects, 0, sizeof(ldr->sects));
 
@@ -159,40 +162,41 @@ static int llext_find_tables(struct llext_loader *ldr, struct llext *ext)
 	for (i = 0, table_cnt = 0; i < ext->sect_cnt && table_cnt < 3; ++i) {
 		elf_shdr_t *shdr = ext->sect_hdrs + i;
 
-		LOG_DBG("section %d at 0x%zx: name %d, type %d, flags 0x%zx, "
-			"addr 0x%zx, size %zd, link %d, info %d",
+		LOG_DBG("section %d at %#zx: name %d, type %d, flags %#zx, "
+			"addr %#zx, align %#zx, size %zd, link %d, info %d",
 			i,
 			(size_t)shdr->sh_offset,
 			shdr->sh_name,
 			shdr->sh_type,
 			(size_t)shdr->sh_flags,
 			(size_t)shdr->sh_addr,
+			(size_t)shdr->sh_addralign,
 			(size_t)shdr->sh_size,
 			shdr->sh_link,
 			shdr->sh_info);
 
-		switch (shdr->sh_type) {
-		case SHT_SYMTAB:
-		case SHT_DYNSYM:
+		if (shdr->sh_type == SHT_SYMTAB && ldr->hdr.e_type == ET_REL) {
 			LOG_DBG("symtab at %d", i);
 			ldr->sects[LLEXT_MEM_SYMTAB] = *shdr;
 			ldr->sect_map[i].mem_idx = LLEXT_MEM_SYMTAB;
+			strtab_ndx = shdr->sh_link;
 			table_cnt++;
-			break;
-		case SHT_STRTAB:
-			if (ldr->hdr.e_shstrndx == i) {
-				LOG_DBG("shstrtab at %d", i);
-				ldr->sects[LLEXT_MEM_SHSTRTAB] = *shdr;
-				ldr->sect_map[i].mem_idx = LLEXT_MEM_SHSTRTAB;
-			} else {
-				LOG_DBG("strtab at %d", i);
-				ldr->sects[LLEXT_MEM_STRTAB] = *shdr;
-				ldr->sect_map[i].mem_idx = LLEXT_MEM_STRTAB;
-			}
+		} else if (shdr->sh_type == SHT_DYNSYM && ldr->hdr.e_type == ET_DYN) {
+			LOG_DBG("dynsym at %d", i);
+			ldr->sects[LLEXT_MEM_SYMTAB] = *shdr;
+			ldr->sect_map[i].mem_idx = LLEXT_MEM_SYMTAB;
+			strtab_ndx = shdr->sh_link;
+			table_cnt++;
+		} else if (shdr->sh_type == SHT_STRTAB && i == shstrtab_ndx) {
+			LOG_DBG("shstrtab at %d", i);
+			ldr->sects[LLEXT_MEM_SHSTRTAB] = *shdr;
+			ldr->sect_map[i].mem_idx = LLEXT_MEM_SHSTRTAB;
+			table_cnt++;
+		} else if (shdr->sh_type == SHT_STRTAB && i == strtab_ndx) {
+			LOG_DBG("strtab at %d", i);
+			ldr->sects[LLEXT_MEM_STRTAB] = *shdr;
+			ldr->sect_map[i].mem_idx = LLEXT_MEM_STRTAB;
 			table_cnt++;
-			break;
-		default:
-			break;
 		}
 	}
 
@@ -206,9 +210,22 @@ static int llext_find_tables(struct llext_loader *ldr, struct llext *ext)
 	return 0;
 }
 
+/* First (bottom) and last (top) entries of a region, inclusive, for a specific field. */
+#define REGION_BOT(reg, field) (size_t)(reg->field + reg->sh_info)
+#define REGION_TOP(reg, field) (size_t)(reg->field + reg->sh_size - 1)
+
+/* Check if two regions x and y have any overlap on a given field. Any shared value counts. */
+#define REGIONS_OVERLAP_ON(x, y, f) \
+	((REGION_BOT(x, f) <= REGION_BOT(y, f) && REGION_TOP(x, f) >= REGION_BOT(y, f)) || \
+	 (REGION_BOT(y, f) <= REGION_BOT(x, f) && REGION_TOP(y, f) >= REGION_BOT(x, f)))
+
 /*
- * Maps the ELF sections into regions according to their usage flags,
- * calculating ldr->sects and ldr->sect_map.
+ * Loops through all defined ELF sections and collapses those with similar
+ * usage flags into LLEXT "regions", taking alignment constraints into account.
+ * Checks the generated regions for overlaps and calculates the offset of each
+ * section within its region.
+ *
+ * This information is stored in the ldr->sects and ldr->sect_map arrays.
  */
 static int llext_map_sections(struct llext_loader *ldr, struct llext *ext,
 			      const struct llext_load_param *ldr_parm)
@@ -219,7 +236,7 @@ static int llext_map_sections(struct llext_loader *ldr, struct llext *ext,
 	for (i = 0; i < ext->sect_cnt; ++i) {
 		elf_shdr_t *shdr = ext->sect_hdrs + i;
 
-		name = llext_string(ldr, ext, LLEXT_MEM_SHSTRTAB, shdr->sh_name);
+		name = llext_section_name(ldr, ext, shdr);
 
 		if (ldr->sect_map[i].mem_idx != LLEXT_MEM_COUNT) {
 			LOG_DBG("section %d name %s already mapped to region %d",
@@ -288,9 +305,11 @@ static int llext_map_sections(struct llext_loader *ldr, struct llext *ext,
 		elf_shdr_t *region = ldr->sects + mem_idx;
 
 		/*
-		 * ELF objects can have sections for memory regions, detached from
-		 * other sections of the same type. E.g. executable sections that will be
-		 * placed in slower memory. Don't merge such sections into main regions
+		 * Some applications may require specific ELF sections to not
+		 * be included in their default memory regions; e.g. the ELF
+		 * file may contain executable sections that are designed to be
+		 * placed in slower memory. Don't merge such sections into main
+		 * regions.
 		 */
 		if (ldr_parm->section_detached && ldr_parm->section_detached(shdr)) {
 			continue;
@@ -301,65 +320,109 @@ static int llext_map_sections(struct llext_loader *ldr, struct llext *ext,
 			 * region descriptor.
 			 */
 			memcpy(region, shdr, sizeof(*region));
-		} else {
-			/* Make sure this section is compatible with the region */
-			if ((shdr->sh_flags & SHF_BASIC_TYPE_MASK) !=
-			    (region->sh_flags & SHF_BASIC_TYPE_MASK)) {
-				LOG_ERR("Unsupported section flags %#x / %#x for %s (region %d)",
-					(uint32_t)shdr->sh_flags, (uint32_t)region->sh_flags,
+			continue;
+		}
+
+		/* Make sure this section is compatible with the existing region */
+		if ((shdr->sh_flags & SHF_BASIC_TYPE_MASK) !=
+		    (region->sh_flags & SHF_BASIC_TYPE_MASK)) {
+			LOG_ERR("Unsupported section flags %#x / %#x for %s (region %d)",
+				(uint32_t)shdr->sh_flags, (uint32_t)region->sh_flags,
+				name, mem_idx);
+			return -ENOEXEC;
+		}
+
+		/* Check if this region type is extendable */
+		switch (mem_idx) {
+		case LLEXT_MEM_BSS:
+			/* SHT_NOBITS sections cannot be merged properly:
+			 * as they use no space in the file, the logic
+			 * below does not work; they must be treated as
+			 * independent entities.
+			 */
+			LOG_ERR("Multiple SHT_NOBITS sections are not supported");
+			return -ENOTSUP;
+		case LLEXT_MEM_PREINIT:
+		case LLEXT_MEM_INIT:
+		case LLEXT_MEM_FINI:
+			/* These regions are not extendable and must be
+			 * referenced at most once in the ELF file.
+			 */
+			LOG_ERR("Region %d redefined", mem_idx);
+			return -ENOEXEC;
+		default:
+			break;
+		}
+
+		if (ldr->hdr.e_type == ET_DYN) {
+			/* In shared objects, sh_addr is the VMA.
+			 * Before merging this section in the region,
+			 * make sure the delta in VMAs matches that of
+			 * file offsets.
+			 */
+			if (shdr->sh_addr - region->sh_addr !=
+			    shdr->sh_offset - region->sh_offset) {
+				LOG_ERR("Incompatible section addresses for %s (region %d)",
 					name, mem_idx);
 				return -ENOEXEC;
 			}
+		}
 
-			/* Check if this region type is extendable */
-			switch (mem_idx) {
-			case LLEXT_MEM_BSS:
-				/* SHT_NOBITS sections cannot be merged properly:
-				 * as they use no space in the file, the logic
-				 * below does not work; they must be treated as
-				 * independent entities.
-				 */
-				LOG_ERR("Multiple SHT_NOBITS sections are not supported");
-				return -ENOTSUP;
-			case LLEXT_MEM_PREINIT:
-			case LLEXT_MEM_INIT:
-			case LLEXT_MEM_FINI:
-				/* These regions are not extendable and must be
-				 * referenced at most once in the ELF file.
-				 */
-				LOG_ERR("Region %d redefined", mem_idx);
-				return -ENOEXEC;
-			default:
-				break;
-			}
+		/*
+		 * Extend the current region to include the new section
+		 * (overlaps are detected later)
+		 */
+		size_t address = MIN(region->sh_addr, shdr->sh_addr);
+		size_t bot_ofs = MIN(region->sh_offset, shdr->sh_offset);
+		size_t top_ofs = MAX(region->sh_offset + region->sh_size,
+				     shdr->sh_offset + shdr->sh_size);
+		size_t addralign = MAX(region->sh_addralign, shdr->sh_addralign);
 
-			if (ldr->hdr.e_type == ET_DYN) {
-				/* In shared objects, sh_addr is the VMA.
-				 * Before merging this section in the region,
-				 * make sure the delta in VMAs matches that of
-				 * file offsets.
-				 */
-				if (shdr->sh_addr - region->sh_addr !=
-				    shdr->sh_offset - region->sh_offset) {
-					LOG_ERR("Incompatible section addresses "
-						"for %s (region %d)", name, mem_idx);
-					return -ENOEXEC;
-				}
+		region->sh_addr = address;
+		region->sh_offset = bot_ofs;
+		region->sh_size = top_ofs - bot_ofs;
+		region->sh_addralign = addralign;
+	}
+
+	/*
+	 * Make sure each of the mapped sections satisfies its alignment
+	 * requirement when placed in the region.
+	 *
+	 * The ELF standard already guarantees that each section's offset in
+	 * the file satisfies its own alignment, and since only powers of 2 can
+	 * be specified, a solution satisfying the largest alignment will also
+	 * work for any smaller one. Aligning the ELF region to the largest
+	 * requirement among the contained sections will then guarantee that
+	 * all are properly aligned.
+	 *
+	 * However, adjusting the region's start address will make the region
+	 * appear larger than it actually is, and might even make it overlap
+	 * with others. To allow for further precise adjustments, the length of
+	 * the calculated pre-padding area is stored in the 'sh_info' field of
+	 * the region descriptor, which is not used on any SHF_ALLOC section.
+	 */
+	for (i = 0; i < LLEXT_MEM_COUNT; i++) {
+		elf_shdr_t *region = ldr->sects + i;
+
+		if (region->sh_type == SHT_NULL || region->sh_size == 0) {
+			/* Skip empty regions */
+			continue;
+		}
+
+		size_t prepad = region->sh_offset & (region->sh_addralign - 1);
+
+		if (ldr->hdr.e_type == ET_DYN) {
+			/* Only shared files populate sh_addr fields */
+			if (prepad > region->sh_addr) {
+				LOG_ERR("Bad section alignment in region %d", i);
+				return -ENOEXEC;
 			}
 
-			/*
-			 * Extend the current region to include the new section
-			 * (overlaps are detected later)
-			 */
-			size_t address = MIN(region->sh_addr, shdr->sh_addr);
-			size_t bot_ofs = MIN(region->sh_offset, shdr->sh_offset);
-			size_t top_ofs = MAX(region->sh_offset + region->sh_size,
-					     shdr->sh_offset + shdr->sh_size);
-
-			region->sh_addr = address;
-			region->sh_offset = bot_ofs;
-			region->sh_size = top_ofs - bot_ofs;
+			region->sh_addr -= prepad;
 		}
+		region->sh_offset -= prepad;
+		region->sh_size += prepad;
+		region->sh_info = prepad;
 	}
 
 	/*
@@ -395,18 +458,16 @@ static int llext_map_sections(struct llext_loader *ldr, struct llext *ext,
 				continue;
 			}
 
-			if (ldr->hdr.e_type == ET_DYN) {
+			if ((ldr->hdr.e_type == ET_DYN) &&
+			    (x->sh_flags & SHF_ALLOC) && (y->sh_flags & SHF_ALLOC)) {
 				/*
-				 * Test all merged VMA ranges for overlaps
+				 * Test regions that have VMA ranges for overlaps
 				 */
-				if ((x->sh_addr <= y->sh_addr &&
-				     x->sh_addr + x->sh_size > y->sh_addr) ||
-				    (y->sh_addr <= x->sh_addr &&
-				     y->sh_addr + y->sh_size > x->sh_addr)) {
-					LOG_ERR("Region %d VMA range (0x%zx +%zd) "
-						"overlaps with %d (0x%zx +%zd)",
-						i, (size_t)x->sh_addr, (size_t)x->sh_size,
-						j, (size_t)y->sh_addr, (size_t)y->sh_size);
+				if (REGIONS_OVERLAP_ON(x, y, sh_addr)) {
+					LOG_ERR("Region %d VMA range (%#zx-%#zx) "
+						"overlaps with %d (%#zx-%#zx)",
+						i, REGION_BOT(x, sh_addr), REGION_TOP(x, sh_addr),
+						j, REGION_BOT(y, sh_addr), REGION_TOP(y, sh_addr));
 					return -ENOEXEC;
 				}
 			}
@@ -420,14 +481,11 @@ static int llext_map_sections(struct llext_loader *ldr, struct llext *ext,
 				continue;
 			}
 
-			if ((x->sh_offset <= y->sh_offset &&
-			     x->sh_offset + x->sh_size > y->sh_offset) ||
-			    (y->sh_offset <= x->sh_offset &&
-			     y->sh_offset + y->sh_size > x->sh_offset)) {
-				LOG_ERR("Region %d ELF file range (0x%zx +%zd) "
-					"overlaps with %d (0x%zx +%zd)",
-					i, (size_t)x->sh_offset, (size_t)x->sh_size,
-					j, (size_t)y->sh_offset, (size_t)y->sh_size);
+			if (REGIONS_OVERLAP_ON(x, y, sh_offset)) {
+				LOG_ERR("Region %d ELF file range (%#zx-%#zx) "
+					"overlaps with %d (%#zx-%#zx)",
+					i, REGION_BOT(x, sh_offset), REGION_TOP(x, sh_offset),
+					j, REGION_BOT(y, sh_offset), REGION_TOP(y, sh_offset));
 				return -ENOEXEC;
 			}
 		}
@@ -436,11 +494,20 @@ static int llext_map_sections(struct llext_loader *ldr, struct llext *ext,
 	/*
 	 * Calculate each ELF section's offset inside its memory region. This
 	 * is done as a separate pass so the final regions are already defined.
+	 * Also mark the regions that include relocation targets.
 	 */
 	for (i = 0; i < ext->sect_cnt; ++i) {
 		elf_shdr_t *shdr = ext->sect_hdrs + i;
 		enum llext_mem mem_idx = ldr->sect_map[i].mem_idx;
 
+		if (shdr->sh_type == SHT_REL || shdr->sh_type == SHT_RELA) {
+			enum llext_mem target_region = ldr->sect_map[shdr->sh_info].mem_idx;
+
+			if (target_region != LLEXT_MEM_COUNT) {
+				ldr->sects[target_region].sh_flags |= SHF_LLEXT_HAS_RELOCS;
+			}
+		}
+
 		if (mem_idx != LLEXT_MEM_COUNT) {
 			ldr->sect_map[i].offset = shdr->sh_offset - ldr->sects[mem_idx].sh_offset;
 		}
@@ -484,7 +551,7 @@ static int llext_count_export_syms(struct llext_loader *ldr, struct llext *ext)
 		uint32_t stb = ELF_ST_BIND(sym.st_info);
 		uint32_t sect = sym.st_shndx;
 
-		name = llext_string(ldr, ext, LLEXT_MEM_STRTAB, sym.st_name);
+		name = llext_symbol_name(ldr, ext, &sym);
 
 		if ((stt == STT_FUNC || stt == STT_OBJECT) && stb == STB_GLOBAL) {
 			LOG_DBG("function symbol %d, name %s, type tag %d, bind %d, sect %d",
@@ -514,31 +581,56 @@ static int llext_allocate_symtab(struct llext_loader *ldr, struct llext *ext)
 	return 0;
 }
 
-static int llext_export_symbols(struct llext_loader *ldr, struct llext *ext)
+static int llext_export_symbols(struct llext_loader *ldr, struct llext *ext,
+				const struct llext_load_param *ldr_parm)
 {
-	elf_shdr_t *shdr = ldr->sects + LLEXT_MEM_EXPORT;
+	struct llext_symtable *exp_tab = &ext->exp_tab;
 	struct llext_symbol *sym;
 	unsigned int i;
 
-	if (shdr->sh_size < sizeof(struct llext_symbol)) {
-		/* Not found, no symbols exported */
-		return 0;
+	if (IS_ENABLED(CONFIG_LLEXT_IMPORT_ALL_GLOBALS)) {
+		/* Use already discovered global symbols */
+		exp_tab->sym_cnt = ext->sym_tab.sym_cnt;
+		sym = ext->sym_tab.syms;
+	} else {
+		/* Only use symbols in the .exported_sym section */
+		exp_tab->sym_cnt = ldr->sects[LLEXT_MEM_EXPORT].sh_size
+				   / sizeof(struct llext_symbol);
+		sym = ext->mem[LLEXT_MEM_EXPORT];
 	}
 
-	struct llext_symtable *exp_tab = &ext->exp_tab;
+	if (!exp_tab->sym_cnt) {
+		/* No symbols exported */
+		return 0;
+	}
 
-	exp_tab->sym_cnt = shdr->sh_size / sizeof(struct llext_symbol);
 	exp_tab->syms = llext_alloc(exp_tab->sym_cnt * sizeof(struct llext_symbol));
 	if (!exp_tab->syms) {
 		return -ENOMEM;
 	}
 
-	for (i = 0, sym = ext->mem[LLEXT_MEM_EXPORT];
-	     i < exp_tab->sym_cnt;
-	     i++, sym++) {
-		exp_tab->syms[i].name = sym->name;
+	for (i = 0; i < exp_tab->sym_cnt; i++, sym++) {
+		/*
+		 * Offsets in objects, built for pre-defined addresses have to
+		 * be translated to memory locations for symbol name access
+		 * during dependency resolution.
+		 */
+		const char *name = NULL;
+
+		if (ldr_parm->pre_located) {
+			ssize_t name_offset = llext_file_offset(ldr, (uintptr_t)sym->name);
+
+			if (name_offset > 0) {
+				name = llext_peek(ldr, name_offset);
+			}
+		}
+		if (!name) {
+			name = sym->name;
+		}
+
+		exp_tab->syms[i].name = name;
 		exp_tab->syms[i].addr = sym->addr;
-		LOG_DBG("sym %p name %s in %p", sym->addr, sym->name, exp_tab->syms + i);
+		LOG_DBG("sym %p name %s", sym->addr, sym->name);
 	}
 
 	return 0;
@@ -579,7 +671,7 @@ static int llext_copy_symbols(struct llext_loader *ldr, struct llext *ext,
 
 		if ((stt == STT_FUNC || stt == STT_OBJECT) &&
 		    stb == STB_GLOBAL && shndx != SHN_UNDEF) {
-			const char *name = llext_string(ldr, ext, LLEXT_MEM_STRTAB, sym.st_name);
+			const char *name = llext_symbol_name(ldr, ext, &sym);
 
 			__ASSERT(j <= sym_tab->sym_cnt, "Miscalculated symbol number %u\n", j);
 
@@ -671,7 +763,7 @@ int do_llext_load(struct llext_loader *ldr, struct llext *ext,
 	}
 
 	LOG_DBG("Allocate and copy strings...");
-	ret = llext_copy_strings(ldr, ext);
+	ret = llext_copy_strings(ldr, ext, ldr_parm);
 	if (ret != 0) {
 		LOG_ERR("Failed to copy ELF string sections, ret %d", ret);
 		goto out;
@@ -721,22 +813,25 @@ int do_llext_load(struct llext_loader *ldr, struct llext *ext,
 		}
 	}
 
-	ret = llext_export_symbols(ldr, ext);
+	ret = llext_export_symbols(ldr, ext, ldr_parm);
 	if (ret != 0) {
 		LOG_ERR("Failed to export, ret %d", ret);
 		goto out;
 	}
 
-	llext_adjust_mmu_permissions(ext);
+	if (!ldr_parm->pre_located) {
+		llext_adjust_mmu_permissions(ext);
+	}
 
 out:
 	/*
-	 * Free resources only used during loading. Note that this exploits
-	 * the fact that freeing a NULL pointer has no effect.
+	 * Free resources only used during loading, unless explicitly requested.
+	 * Note that this exploits the fact that freeing a NULL pointer has no effect.
 	 */
 
-	llext_free(ldr->sect_map);
-	ldr->sect_map = NULL;
+	if (ret != 0 || !ldr_parm->keep_section_info) {
+		llext_free_inspection_data(ldr, ext);
+	}
 
 	/* Until proper inter-llext linking is implemented, the symbol table is
 	 * not useful outside of the loading process; keep it only if debugging
@@ -760,11 +855,22 @@ int do_llext_load(struct llext_loader *ldr, struct llext *ext,
 		ext->exp_tab.sym_cnt = 0;
 		ext->exp_tab.syms = NULL;
 	} else {
-		LOG_DBG("loaded module, .text at %p, .rodata at %p", ext->mem[LLEXT_MEM_TEXT],
-			ext->mem[LLEXT_MEM_RODATA]);
+		LOG_DBG("Loaded llext: %zu bytes in heap, .text at %p, .rodata at %p",
+			ext->alloc_size, ext->mem[LLEXT_MEM_TEXT], ext->mem[LLEXT_MEM_RODATA]);
 	}
 
 	llext_finalize(ldr);
 
 	return ret;
 }
+
+int llext_free_inspection_data(struct llext_loader *ldr, struct llext *ext)
+{
+	if (ldr->sect_map) {
+		ext->alloc_size -= ext->sect_cnt * sizeof(ldr->sect_map[0]);
+		llext_free(ldr->sect_map);
+		ldr->sect_map = NULL;
+	}
+
+	return 0;
+}
diff --git a/subsys/llext/llext_mem.c b/subsys/llext/llext_mem.c
index 7ce804147e7..34599bcddac 100644
--- a/subsys/llext/llext_mem.c
+++ b/subsys/llext/llext_mem.c
@@ -55,33 +55,77 @@ static void llext_init_mem_part(struct llext *ext, enum llext_mem mem_idx,
 	}
 #endif
 
-	LOG_DBG("region %d: start 0x%zx, size %zd", mem_idx, (size_t)start, len);
+	LOG_DBG("region %d: start %#zx, size %zd", mem_idx, (size_t)start, len);
 }
 
-static int llext_copy_section(struct llext_loader *ldr, struct llext *ext,
+static int llext_copy_region(struct llext_loader *ldr, struct llext *ext,
 			      enum llext_mem mem_idx, const struct llext_load_param *ldr_parm)
 {
 	int ret;
+	elf_shdr_t *region = ldr->sects + mem_idx;
+	uintptr_t region_alloc = region->sh_size;
+	uintptr_t region_align = region->sh_addralign;
 
-	if (!ldr->sects[mem_idx].sh_size) {
+	if (!region_alloc) {
 		return 0;
 	}
-	ext->mem_size[mem_idx] = ldr->sects[mem_idx].sh_size;
+	ext->mem_size[mem_idx] = region_alloc;
 
-	if (IS_ENABLED(CONFIG_LLEXT_STORAGE_WRITABLE)) {
-		if (ldr->sects[mem_idx].sh_type != SHT_NOBITS) {
-			/* Directly use data from the ELF buffer if peek() is supported */
-			ext->mem[mem_idx] = llext_peek(ldr, ldr->sects[mem_idx].sh_offset);
+	/*
+	 * Calculate the minimum region size and alignment that can satisfy
+	 * MMU/MPU requirements. This only applies to regions that contain
+	 * program-accessible data (not to string tables, for example).
+	 */
+	if (region->sh_flags & SHF_ALLOC) {
+		if (IS_ENABLED(CONFIG_ARM_MPU)) {
+			/* On ARM with an MPU, regions must be sized and
+			 * aligned to the same power of two (larger than 32).
+			 */
+			uintptr_t block_sz = MAX(MAX(region_alloc, region_align), LLEXT_PAGE_SIZE);
+
+			block_sz = 1 << LOG2CEIL(block_sz); /* align to next power of two */
+			region_alloc = block_sz;
+			region_align = block_sz;
+		} else if (IS_ENABLED(CONFIG_MMU)) {
+			/* MMU targets map memory in page-sized chunks. Round
+			 * the region to multiples of those.
+			 */
+			region_alloc = ROUND_UP(region_alloc, LLEXT_PAGE_SIZE);
+			region_align = MAX(region_align, LLEXT_PAGE_SIZE);
+		}
+	}
+
+	if (ldr->storage == LLEXT_STORAGE_WRITABLE ||           /* writable storage         */
+	    (ldr->storage == LLEXT_STORAGE_PERSISTENT &&        /* || persistent storage    */
+	     !(region->sh_flags & SHF_WRITE) &&                 /*    && read-only region   */
+	     !(region->sh_flags & SHF_LLEXT_HAS_RELOCS))) {     /*    && no relocs to apply */
+		/*
+		 * Try to reuse data areas from the ELF buffer, if possible.
+		 * If any of the following tests fail, a normal allocation
+		 * will be attempted.
+		 */
+		if (region->sh_type != SHT_NOBITS) {
+			/* Region has data in the file, check if peek() is supported */
+			ext->mem[mem_idx] = llext_peek(ldr, region->sh_offset);
 			if (ext->mem[mem_idx]) {
-				llext_init_mem_part(ext, mem_idx, (uintptr_t)ext->mem[mem_idx],
-						    ldr->sects[mem_idx].sh_size);
-				ext->mem_on_heap[mem_idx] = false;
-				return 0;
+				if (IS_ALIGNED(ext->mem[mem_idx], region_align) ||
+				    ldr_parm->pre_located) {
+					/* Map this region directly to the ELF buffer */
+					llext_init_mem_part(ext, mem_idx,
+							    (uintptr_t)ext->mem[mem_idx],
+							    region_alloc);
+					ext->mem_on_heap[mem_idx] = false;
+					return 0;
+				}
+
+				LOG_WRN("Cannot peek region %d: %p not aligned to %#zx",
+					mem_idx, ext->mem[mem_idx], (size_t)region_align);
 			}
-		} else if (ldr_parm && ldr_parm->pre_located) {
+		} else if (ldr_parm->pre_located) {
 			/*
-			 * ldr_parm cannot be NULL here with the current flow, but
-			 * we add a check to make it future-proof
+			 * In pre-located files all regions, including BSS,
+			 * are placed by the user with a linker script. No
+			 * additional memory allocation is needed here.
 			 */
 			ext->mem[mem_idx] = NULL;
 			ext->mem_on_heap[mem_idx] = false;
@@ -89,45 +133,51 @@ static int llext_copy_section(struct llext_loader *ldr, struct llext *ext,
 		}
 	}
 
-	if (ldr_parm && ldr_parm->pre_located) {
+	if (ldr_parm->pre_located) {
+		/*
+		 * The ELF file is supposed to be pre-located, but some
+		 * regions are not accessible or not in the correct place.
+		 */
 		return -EFAULT;
 	}
 
-	/* On ARM with an MPU a pow(2, N)*32 sized and aligned region is needed,
-	 * otherwise its typically an mmu page (sized and aligned memory region)
-	 * we are after that we can assign memory permission bits on.
-	 */
-#ifndef CONFIG_ARM_MPU
-	const uintptr_t sect_alloc = ROUND_UP(ldr->sects[mem_idx].sh_size, LLEXT_PAGE_SIZE);
-	const uintptr_t sect_align = LLEXT_PAGE_SIZE;
-#else
-	uintptr_t sect_alloc = LLEXT_PAGE_SIZE;
-
-	while (sect_alloc < ldr->sects[mem_idx].sh_size) {
-		sect_alloc *= 2;
-	}
-	uintptr_t sect_align = sect_alloc;
-#endif
-
-	ext->mem[mem_idx] = llext_aligned_alloc(sect_align, sect_alloc);
+	/* Allocate a suitably aligned area for the region. */
+	ext->mem[mem_idx] = llext_aligned_alloc(region_align, region_alloc);
 	if (!ext->mem[mem_idx]) {
+		LOG_ERR("Failed allocating %zd bytes %zd-aligned for region %d",
+			(size_t)region_alloc, (size_t)region_align, mem_idx);
 		return -ENOMEM;
 	}
 
-	ext->alloc_size += sect_alloc;
+	ext->alloc_size += region_alloc;
 
 	llext_init_mem_part(ext, mem_idx, (uintptr_t)ext->mem[mem_idx],
-		sect_alloc);
+		region_alloc);
 
-	if (ldr->sects[mem_idx].sh_type == SHT_NOBITS) {
-		memset(ext->mem[mem_idx], 0, ldr->sects[mem_idx].sh_size);
+	if (region->sh_type == SHT_NOBITS) {
+		memset(ext->mem[mem_idx], 0, region->sh_size);
 	} else {
-		ret = llext_seek(ldr, ldr->sects[mem_idx].sh_offset);
+		uintptr_t base = (uintptr_t)ext->mem[mem_idx];
+		size_t offset = region->sh_offset;
+		size_t length = region->sh_size;
+
+		if (region->sh_flags & SHF_ALLOC) {
+			/* zero out any prepad bytes, not part of the data area */
+			size_t prepad = region->sh_info;
+
+			memset((void *)base, 0, prepad);
+			base += prepad;
+			offset += prepad;
+			length -= prepad;
+		}
+
+		/* actual data area without prepad bytes */
+		ret = llext_seek(ldr, offset);
 		if (ret != 0) {
 			goto err;
 		}
 
-		ret = llext_read(ldr, ext->mem[mem_idx], ldr->sects[mem_idx].sh_size);
+		ret = llext_read(ldr, (void *)base, length);
 		if (ret != 0) {
 			goto err;
 		}
@@ -143,12 +193,13 @@ static int llext_copy_section(struct llext_loader *ldr, struct llext *ext,
 	return ret;
 }
 
-int llext_copy_strings(struct llext_loader *ldr, struct llext *ext)
+int llext_copy_strings(struct llext_loader *ldr, struct llext *ext,
+		       const struct llext_load_param *ldr_parm)
 {
-	int ret = llext_copy_section(ldr, ext, LLEXT_MEM_SHSTRTAB, NULL);
+	int ret = llext_copy_region(ldr, ext, LLEXT_MEM_SHSTRTAB, ldr_parm);
 
 	if (!ret) {
-		ret = llext_copy_section(ldr, ext, LLEXT_MEM_STRTAB, NULL);
+		ret = llext_copy_region(ldr, ext, LLEXT_MEM_STRTAB, ldr_parm);
 	}
 
 	return ret;
@@ -163,13 +214,28 @@ int llext_copy_regions(struct llext_loader *ldr, struct llext *ext,
 			continue;
 		}
 
-		int ret = llext_copy_section(ldr, ext, mem_idx, ldr_parm);
+		int ret = llext_copy_region(ldr, ext, mem_idx, ldr_parm);
 
 		if (ret < 0) {
 			return ret;
 		}
 	}
 
+	if (IS_ENABLED(CONFIG_LLEXT_LOG_LEVEL_DBG)) {
+		LOG_DBG("gdb add-symbol-file flags:");
+		for (int i = 0; i < ext->sect_cnt; ++i) {
+			elf_shdr_t *shdr = ext->sect_hdrs + i;
+			enum llext_mem mem_idx = ldr->sect_map[i].mem_idx;
+			const char *name = llext_section_name(ldr, ext, shdr);
+
+			/* only show sections mapped to program memory */
+			if (mem_idx < LLEXT_MEM_EXPORT) {
+				LOG_DBG("-s %s %#zx", name,
+					(size_t)ext->mem[mem_idx] + ldr->sect_map[i].offset);
+			}
+		}
+	}
+
 	return 0;
 }
 
@@ -204,6 +270,8 @@ void llext_adjust_mmu_permissions(struct llext *ext)
 		sys_cache_data_flush_range(addr, size);
 		k_mem_update_flags(addr, size, flags);
 	}
+
+	ext->mmu_permissions_set = true;
 #endif
 }
 
@@ -211,8 +279,9 @@ void llext_free_regions(struct llext *ext)
 {
 	for (int i = 0; i < LLEXT_MEM_COUNT; i++) {
 #ifdef CONFIG_MMU
-		if (ext->mem_size[i] != 0) {
-			/* restore default RAM permissions */
+		if (ext->mmu_permissions_set && ext->mem_size[i] != 0 &&
+		    (i == LLEXT_MEM_TEXT || i == LLEXT_MEM_RODATA)) {
+			/* restore default RAM permissions of changed regions */
 			k_mem_update_flags(ext->mem[i],
 					   ROUND_UP(ext->mem_size[i], LLEXT_PAGE_SIZE),
 					   K_MEM_PERM_RW);
diff --git a/subsys/llext/llext_priv.h b/subsys/llext/llext_priv.h
index e3b9fd282a6..3a5bbc96abd 100644
--- a/subsys/llext/llext_priv.h
+++ b/subsys/llext/llext_priv.h
@@ -9,17 +9,14 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/llext/llext.h>
-
-struct llext_elf_sect_map {
-	enum llext_mem mem_idx;
-	size_t offset;
-};
+#include <zephyr/llext/llext_internal.h>
 
 /*
  * Memory management (llext_mem.c)
  */
 
-int llext_copy_strings(struct llext_loader *ldr, struct llext *ext);
+int llext_copy_strings(struct llext_loader *ldr, struct llext *ext,
+		       const struct llext_load_param *ldr_parm);
 int llext_copy_regions(struct llext_loader *ldr, struct llext *ext,
 		       const struct llext_load_param *ldr_parm);
 void llext_free_regions(struct llext *ext);
@@ -53,18 +50,13 @@ static inline void llext_free(void *ptr)
 int do_llext_load(struct llext_loader *ldr, struct llext *ext,
 		  const struct llext_load_param *ldr_parm);
 
-static inline const char *llext_string(struct llext_loader *ldr, struct llext *ext,
-				       enum llext_mem mem_idx, unsigned int idx)
-{
-	return (char *)ext->mem[mem_idx] + idx;
-}
-
 /*
  * Relocation (llext_link.c)
  */
 
 int llext_link(struct llext_loader *ldr, struct llext *ext,
 	       const struct llext_load_param *ldr_parm);
+ssize_t llext_file_offset(struct llext_loader *ldr, uintptr_t offset);
 void llext_dependency_remove_all(struct llext *ext);
 
 #endif /* ZEPHYR_SUBSYS_LLEXT_PRIV_H_ */
diff --git a/subsys/llext/shell.c b/subsys/llext/shell.c
index b912f9a5049..00fcda1fde4 100644
--- a/subsys/llext/shell.c
+++ b/subsys/llext/shell.c
@@ -52,9 +52,9 @@ static int cmd_llext_list_symbols(const struct shell *sh, size_t argc, char *arg
 
 	shell_print(sh, "Extension: %s symbols", m->name);
 	shell_print(sh, "| Symbol           | Address    |");
-	for (elf_word i = 0; i < m->sym_tab.sym_cnt; i++) {
-		shell_print(sh, "| %16s | %p |", m->sym_tab.syms[i].name,
-			    m->sym_tab.syms[i].addr);
+	for (elf_word i = 0; i < m->exp_tab.sym_cnt; i++) {
+		shell_print(sh, "| %16s | %p |", m->exp_tab.syms[i].name,
+			    m->exp_tab.syms[i].addr);
 	}
 
 	return 0;
@@ -124,22 +124,24 @@ static int cmd_llext_list(const struct shell *sh, size_t argc, char *argv[])
 	return llext_iterate(llext_shell_list_cb, &sl);
 }
 
-static uint8_t llext_buf[CONFIG_LLEXT_SHELL_MAX_SIZE];
+static uint8_t llext_buf[CONFIG_LLEXT_SHELL_MAX_SIZE] __aligned(Z_KERNEL_STACK_OBJ_ALIGN);
 
 static int cmd_llext_load_hex(const struct shell *sh, size_t argc, char *argv[])
 {
-	char name[16];
-	size_t hex_len = strnlen(argv[2], CONFIG_LLEXT_SHELL_MAX_SIZE*2+1);
-	size_t bin_len = hex_len/2;
+	char *name = argv[1];
+	size_t hex_len = strlen(argv[2]);
 
-	if (bin_len > CONFIG_LLEXT_SHELL_MAX_SIZE) {
+	if (strlen(name) > LLEXT_MAX_NAME_LEN) {
+		shell_print(sh, "Extension name too long, max %d chars\n", LLEXT_MAX_NAME_LEN);
+		return -EINVAL;
+	}
+
+	if (hex_len > CONFIG_LLEXT_SHELL_MAX_SIZE*2) {
 		shell_print(sh, "Extension %d bytes too large to load, max %d bytes\n", hex_len/2,
 			    CONFIG_LLEXT_SHELL_MAX_SIZE);
 		return -ENOMEM;
 	}
 
-	strncpy(name, argv[1], sizeof(name));
-
 	size_t llext_buf_len = hex2bin(argv[2], hex_len, llext_buf, CONFIG_LLEXT_SHELL_MAX_SIZE);
 	struct llext_buf_loader buf_loader = LLEXT_BUF_LOADER(llext_buf, llext_buf_len);
 	struct llext_loader *ldr = &buf_loader.loader;
diff --git a/subsys/logging/Kconfig.misc b/subsys/logging/Kconfig.misc
index a9c90526e14..0dd3afb40ad 100644
--- a/subsys/logging/Kconfig.misc
+++ b/subsys/logging/Kconfig.misc
@@ -19,6 +19,7 @@ config LOG_TEST_CLEAR_MESSAGE_SPACE
 config LOG_USE_VLA
 	bool "Using variable length arrays"
 	default y if !MISRA_SANE
+	depends on TOOLCHAIN_SUPPORTS_VLA_IN_STATEMENTS
 	help
 	  Using VLA slightly decreases stack usage in some cases it may not be
 	  supported. Note that VLA are used for arrays which size is resolved at
diff --git a/subsys/logging/Kconfig.mode b/subsys/logging/Kconfig.mode
index b573aa59906..4e1fd2495b1 100644
--- a/subsys/logging/Kconfig.mode
+++ b/subsys/logging/Kconfig.mode
@@ -74,3 +74,15 @@ config LOG_DEFAULT_MINIMAL
 config LOG_MULTIDOMAIN
 	bool "Multi-domain logger"
 	select LOG_TIMESTAMP_64BIT
+
+if LOG_MODE_DEFERRED
+
+config LOG_FLUSH_SLEEP_US
+	int "Sleep time when flushing the log queue, microseconds"
+	range 100 100000
+	default 10000
+	help
+	  In deferred logging mode this is the time, used in
+	  log_flush() on each sleep iteration in microseconds.
+
+endif # LOG_MODE_DEFERRED
diff --git a/subsys/logging/backends/Kconfig.rtt b/subsys/logging/backends/Kconfig.rtt
index e275f9b18f2..d1fc0617141 100644
--- a/subsys/logging/backends/Kconfig.rtt
+++ b/subsys/logging/backends/Kconfig.rtt
@@ -4,7 +4,7 @@
 config LOG_BACKEND_RTT
 	bool "Segger J-Link RTT backend"
 	depends on USE_SEGGER_RTT
-	default y if !SHELL_BACKEND_RTT
+	default y if !SHELL_LOG_BACKEND
 	select SEGGER_RTT_CUSTOM_LOCKING
 	select LOG_BACKEND_SUPPORTS_FORMAT_TIMESTAMP
 	help
diff --git a/subsys/logging/backends/Kconfig.xtensa_sim b/subsys/logging/backends/Kconfig.xtensa_sim
index 6b81914cf2d..e3c35b83da6 100644
--- a/subsys/logging/backends/Kconfig.xtensa_sim
+++ b/subsys/logging/backends/Kconfig.xtensa_sim
@@ -3,7 +3,7 @@
 
 config LOG_BACKEND_XTENSA_SIM
 	bool "Xtensa simulator backend"
-	depends on SOC_XTENSA_SAMPLE_CONTROLLER || SOC_XTENSA_DC233C || SOC_FAMILY_INTEL_ADSP
+	depends on SIMULATOR_XTENSA
 	default y if SOC_XTENSA_SAMPLE_CONTROLLER || SOC_XTENSA_DC233C
 	select LOG_BACKEND_SUPPORTS_FORMAT_TIMESTAMP
 	help
diff --git a/subsys/logging/backends/log_backend_fs.c b/subsys/logging/backends/log_backend_fs.c
index 1f977403d65..b15c2c0fa03 100644
--- a/subsys/logging/backends/log_backend_fs.c
+++ b/subsys/logging/backends/log_backend_fs.c
@@ -31,9 +31,7 @@ static int file_ctr, newest, oldest;
 static int allocate_new_file(struct fs_file_t *file);
 static int del_oldest_log(void);
 static int get_log_file_id(struct fs_dirent *ent);
-#ifndef CONFIG_LOG_BACKEND_FS_TESTSUITE
 static uint32_t log_format_current = CONFIG_LOG_BACKEND_FS_OUTPUT_DEFAULT;
-#endif
 
 static int check_log_volume_available(void)
 {
@@ -107,42 +105,34 @@ static int create_log_dir(const char *path)
 
 }
 
+static int get_log_path(char *buf, size_t buf_len, int num)
+{
+	if (num > MAX_FILE_NUMERAL) {
+		return -EINVAL;
+	}
+	return snprintf(buf, buf_len, "%s/%s%04d", CONFIG_LOG_BACKEND_FS_DIR,
+			CONFIG_LOG_BACKEND_FS_FILE_PREFIX, num);
+}
+
 static int check_log_file_exist(int num)
 {
-	struct fs_dir_t dir;
 	struct fs_dirent ent;
+	char fname[MAX_PATH_LEN];
 	int rc;
 
-	fs_dir_t_init(&dir);
+	rc = get_log_path(fname, sizeof(fname), num);
 
-	rc = fs_opendir(&dir, CONFIG_LOG_BACKEND_FS_DIR);
-	if (rc) {
-		return -EIO;
+	if (rc < 0) {
+		return rc;
 	}
 
-	while (true) {
-		rc = fs_readdir(&dir, &ent);
-		if (rc < 0) {
-			rc = -EIO;
-			goto close_dir;
-		}
-		if (ent.name[0] == 0) {
-			break;
-		}
-
-		rc = get_log_file_id(&ent);
+	rc = fs_stat(fname, &ent);
 
-		if (rc == num) {
-			rc = 1;
-			goto close_dir;
-		}
+	if (rc == 0) {
+		return 1;
+	} else if (rc == -ENOENT) {
+		return 0;
 	}
-
-	rc = 0;
-
-close_dir:
-	(void) fs_closedir(&dir);
-
 	return rc;
 }
 
@@ -210,12 +200,6 @@ int write_log_to_file(uint8_t *data, size_t length, void *ctx)
 			}
 			length = 0;
 		}
-
-		rc = fs_sync(f);
-		if (rc < 0) {
-			/* Something is wrong */
-			goto on_error;
-		}
 	}
 
 	return length;
@@ -341,8 +325,7 @@ static int allocate_new_file(struct fs_file_t *file)
 		curr_file_num = newest;
 
 		/* Is there space left in the newest file? */
-		snprintf(fname, sizeof(fname), "%s/%s%04d", CONFIG_LOG_BACKEND_FS_DIR,
-			 CONFIG_LOG_BACKEND_FS_FILE_PREFIX, curr_file_num);
+		get_log_path(fname, sizeof(fname), curr_file_num);
 		rc = fs_open(file, fname, FS_O_CREATE | FS_O_WRITE | FS_O_APPEND);
 		if (rc < 0) {
 			goto out;
@@ -403,9 +386,7 @@ static int allocate_new_file(struct fs_file_t *file)
 		}
 	}
 
-	snprintf(fname, sizeof(fname), "%s/%s%04d",
-		CONFIG_LOG_BACKEND_FS_DIR,
-		CONFIG_LOG_BACKEND_FS_FILE_PREFIX, curr_file_num);
+	get_log_path(fname, sizeof(fname), curr_file_num);
 
 	rc = fs_open(file, fname, FS_O_CREATE | FS_O_WRITE);
 	if (rc < 0) {
@@ -424,9 +405,7 @@ static int del_oldest_log(void)
 	static char dellname[MAX_PATH_LEN];
 
 	while (true) {
-		snprintf(dellname, sizeof(dellname), "%s/%s%04d",
-			 CONFIG_LOG_BACKEND_FS_DIR,
-			 CONFIG_LOG_BACKEND_FS_FILE_PREFIX, oldest);
+		get_log_path(dellname, sizeof(dellname), oldest);
 		rc = fs_unlink(dellname);
 
 		if ((rc == 0) || (rc == -ENOENT)) {
@@ -450,8 +429,6 @@ static int del_oldest_log(void)
 BUILD_ASSERT(!IS_ENABLED(CONFIG_LOG_MODE_IMMEDIATE),
 	     "Immediate logging is not supported by LOG FS backend.");
 
-#ifndef CONFIG_LOG_BACKEND_FS_TESTSUITE
-
 static uint8_t __aligned(4) buf[MAX_FLASH_WRITE_SIZE];
 LOG_OUTPUT_DEFINE(log_output, write_log_to_file, buf, MAX_FLASH_WRITE_SIZE);
 
@@ -481,7 +458,7 @@ static void dropped(const struct log_backend *const backend, uint32_t cnt)
 static void process(const struct log_backend *const backend,
 		union log_msg_generic *msg)
 {
-	uint32_t flags = log_backend_std_get_flags();
+	uint32_t flags = log_backend_std_get_flags() & ~LOG_OUTPUT_FLAG_COLORS;
 
 	log_format_func_t log_output_func = log_format_func_t_get(log_format_current);
 
@@ -494,14 +471,28 @@ static int format_set(const struct log_backend *const backend, uint32_t log_type
 	return 0;
 }
 
+static void notify(const struct log_backend *const backend, enum log_backend_evt event,
+		   union log_backend_evt_arg *arg)
+{
+	if (event == LOG_BACKEND_EVT_PROCESS_THREAD_DONE) {
+		if (backend_state == BACKEND_FS_OK) {
+			int rc = fs_sync(&fs_file);
+
+			if (rc != 0) {
+				backend_state = BACKEND_FS_CORRUPTED;
+			}
+		}
+	}
+}
+
 static const struct log_backend_api log_backend_fs_api = {
 	.process = process,
 	.panic = panic,
 	.init = log_backend_fs_init,
 	.dropped = dropped,
 	.format_set = format_set,
+	.notify = notify,
 };
 
 LOG_BACKEND_DEFINE(log_backend_fs, log_backend_fs_api,
 		   IS_ENABLED(CONFIG_LOG_BACKEND_FS_AUTOSTART));
-#endif
diff --git a/subsys/logging/backends/log_backend_rtt.c b/subsys/logging/backends/log_backend_rtt.c
index 43ebbbfcbab..d78e530621c 100644
--- a/subsys/logging/backends/log_backend_rtt.c
+++ b/subsys/logging/backends/log_backend_rtt.c
@@ -32,6 +32,10 @@
 #define CONFIG_LOG_BACKEND_RTT_RETRY_CNT 10
 #endif
 
+#if defined(CONFIG_LOG_BACKEND_RTT_OUTPUT_DICTIONARY)
+static const uint8_t LOG_HEX_SEP[10] = "##ZLOGV1##";
+#endif
+
 #define DROP_MAX 99
 
 #define DROP_MSG "messages dropped:    \r\n"
@@ -247,12 +251,34 @@ static int data_out_overwrite_mode(uint8_t *data, size_t length, void *ctx)
 	return length;
 }
 
-LOG_OUTPUT_DEFINE(log_output_rtt,
-		  IS_ENABLED(CONFIG_LOG_BACKEND_RTT_MODE_BLOCK) ?
-		  data_out_block_mode :
-		  IS_ENABLED(CONFIG_LOG_BACKEND_RTT_MODE_OVERWRITE) ?
-		  data_out_overwrite_mode : data_out_drop_mode,
-		  char_buf, sizeof(char_buf));
+static const log_output_func_t logging_func =
+	IS_ENABLED(CONFIG_LOG_BACKEND_RTT_MODE_BLOCK)       ? data_out_block_mode
+	: IS_ENABLED(CONFIG_LOG_BACKEND_RTT_MODE_OVERWRITE) ? data_out_overwrite_mode
+							    : data_out_drop_mode;
+
+static int data_out(uint8_t *data, size_t length, void *ctx)
+{
+#if defined(CONFIG_LOG_BACKEND_RTT_OUTPUT_DICTIONARY)
+	for (size_t i = 0; i < length; i++) {
+		char c[2];
+		uint8_t x[2];
+
+		/* upper 8-bit */
+		x[0] = data[i] >> 4;
+		(void)hex2char(x[0], &c[0]);
+
+		/* lower 8-bit */
+		x[1] = data[i] & 0x0FU;
+		(void)hex2char(x[1], &c[1]);
+		logging_func(c, sizeof(c), ctx);
+	}
+	return length;
+#endif
+
+	return logging_func(data, length, ctx);
+}
+
+LOG_OUTPUT_DEFINE(log_output_rtt, data_out, char_buf, sizeof(char_buf));
 
 static void log_backend_rtt_cfg(void)
 {
@@ -267,6 +293,10 @@ static void log_backend_rtt_init(struct log_backend const *const backend)
 		log_backend_rtt_cfg();
 	}
 
+#if defined(CONFIG_LOG_BACKEND_RTT_OUTPUT_DICTIONARY)
+	logging_func((uint8_t *)LOG_HEX_SEP, sizeof(LOG_HEX_SEP), NULL);
+#endif
+
 	host_present = true;
 	line_pos = line_buf;
 }
diff --git a/subsys/logging/backends/log_backend_ws.c b/subsys/logging/backends/log_backend_ws.c
index 370bd7a41eb..ec6e9ebb00f 100644
--- a/subsys/logging/backends/log_backend_ws.c
+++ b/subsys/logging/backends/log_backend_ws.c
@@ -15,11 +15,6 @@ LOG_MODULE_REGISTER(log_backend_ws, CONFIG_LOG_DEFAULT_LEVEL);
 #include <zephyr/net/net_if.h>
 #include <zephyr/net/socket.h>
 
-/* Set this to 1 if you want to see what is being sent to server */
-#define DEBUG_PRINTING 0
-
-#define DBG(fmt, ...) IF_ENABLED(DEBUG_PRINTING, (printk(fmt, ##__VA_ARGS__)))
-
 static bool ws_init_done;
 static bool panic_mode;
 static uint32_t log_format_current = CONFIG_LOG_BACKEND_WS_OUTPUT_DEFAULT;
@@ -66,17 +61,19 @@ static int ws_console_out(struct log_backend_ws_ctx *ctx, int c)
 	unsigned int cnt = 0;
 	int ret = 0;
 
-	if (pos >= (sizeof(output_buf) - 1)) {
-		printnow = true;
+	__ASSERT_NO_MSG(pos < sizeof(output_buf));
+
+	if ((c != '\n') && (c != '\r')) {
+		output_buf[pos++] = c;
 	} else {
-		if ((c != '\n') && (c != '\r')) {
-			output_buf[pos++] = c;
-		} else {
-			printnow = true;
-		}
+		printnow = true;
 	}
 
-	if (printnow) {
+	if (pos >= sizeof(output_buf)) {
+		printnow = true;
+	}
+
+	if (pos > 0 && printnow) {
 		while (ctx->sock >= 0 && cnt < max_cnt) {
 			ret = ws_send_all(ctx->sock, output_buf, pos);
 			if (ret < 0) {
@@ -103,13 +100,14 @@ static int ws_console_out(struct log_backend_ws_ctx *ctx, int c)
 		}
 	}
 
-	return cnt;
+	return ret;
 }
 
 static int line_out(uint8_t *data, size_t length, void *output_ctx)
 {
 	struct log_backend_ws_ctx *ctx = (struct log_backend_ws_ctx *)output_ctx;
 	int ret = -ENOMEM;
+	int sent = 0;
 
 	if (ctx == NULL || ctx->sock == -1) {
 		return length;
@@ -118,14 +116,21 @@ static int line_out(uint8_t *data, size_t length, void *output_ctx)
 	for (int i = 0; i < length; i++) {
 		ret = ws_console_out(ctx, data[i]);
 		if (ret < 0) {
-			goto fail;
+			break;
 		}
+
+		sent++;
 	}
 
-	length = ret;
+	/* In case we've managed to buffer/send anything, return the actual
+	 * number of bytes processed. Otherwise, assume the data was dropped
+	 * to avoid busy looping endlessly (which could happen in case of fatal
+	 * socket failures or persistent EAGAIN).
+	 */
+	if (sent > 0) {
+		length = sent;
+	}
 
-	DBG(data);
-fail:
 	return length;
 }
 
@@ -188,7 +193,7 @@ int log_backend_ws_unregister(int fd)
 	struct log_backend_ws_ctx *ctx = log_output_ws.control_block->ctx;
 
 	if (ctx->sock != fd) {
-		DBG("Websocket sock mismatch (%d vs %d)", ctx->sock, fd);
+		LOG_DBG("Websocket sock mismatch (%d vs %d)", ctx->sock, fd);
 	}
 
 	ctx->sock = -1;
diff --git a/subsys/logging/log_cmds.c b/subsys/logging/log_cmds.c
index fd7997a84bd..cc23a843eaf 100644
--- a/subsys/logging/log_cmds.c
+++ b/subsys/logging/log_cmds.c
@@ -341,7 +341,19 @@ static int log_go(const struct shell *sh,
 		  char **argv)
 {
 	if (backend || !IS_ENABLED(CONFIG_LOG_FRONTEND)) {
-		log_backend_activate(backend, backend->cb->ctx);
+		if (!backend->cb->initialized) {
+			log_backend_init(backend);
+			while (log_backend_is_ready(backend) != 0) {
+				if (IS_ENABLED(CONFIG_MULTITHREADING)) {
+					k_msleep(10);
+				}
+			}
+			if (log_backend_is_ready(backend) == 0) {
+				log_backend_enable(backend, backend->cb->ctx, CONFIG_LOG_MAX_LEVEL);
+			}
+		} else {
+			log_backend_activate(backend, backend->cb->ctx);
+		}
 		return 0;
 	}
 
diff --git a/subsys/logging/log_core.c b/subsys/logging/log_core.c
index c5a0469afba..25345f75fb0 100644
--- a/subsys/logging/log_core.c
+++ b/subsys/logging/log_core.c
@@ -27,6 +27,11 @@
 #include <zephyr/posix/time.h>
 #endif
 
+#if CONFIG_USERSPACE && CONFIG_LOG_ALWAYS_RUNTIME
+#include <zephyr/app_memory/app_memdomain.h>
+K_APPMEM_PARTITION_DEFINE(k_log_partition);
+#endif
+
 LOG_MODULE_REGISTER(log);
 
 #ifndef CONFIG_LOG_PROCESS_THREAD_SLEEP_MS
@@ -288,6 +293,14 @@ void log_core_init(void)
 	if (IS_ENABLED(CONFIG_LOG_RUNTIME_FILTERING)) {
 		z_log_runtime_filters_init();
 	}
+
+	STRUCT_SECTION_FOREACH(log_backend, backend) {
+		uint32_t id;
+		/* As first slot in filtering mask is reserved, backend ID has offset.*/
+		id = LOG_FILTER_FIRST_BACKEND_SLOT_IDX;
+		id += backend - log_backend_get(0);
+		log_backend_id_set(backend, id);
+	}
 }
 
 static uint32_t activate_foreach_backend(uint32_t mask)
@@ -330,8 +343,8 @@ static uint32_t z_log_init(bool blocking, bool can_sleep)
 
 	int backend_index = 0;
 
-	/* Activate autostart backends */
 	STRUCT_SECTION_FOREACH(log_backend, backend) {
+		/* Activate autostart backends */
 		if (backend->autostart) {
 			log_backend_init(backend);
 
@@ -557,9 +570,9 @@ bool z_impl_log_process(void)
 	msg = z_log_msg_claim(&backoff);
 
 	if (msg) {
-		atomic_dec(&buffered_cnt);
 		msg_process(msg);
 		z_log_msg_free(msg);
+		atomic_dec(&buffered_cnt);
 	} else if (CONFIG_LOG_PROCESSING_LATENCY_US > 0 && !K_TIMEOUT_EQ(backoff, K_NO_WAIT)) {
 		/* If backoff is requested, it means that there are pending
 		 * messages but they are too new and processing shall back off
@@ -992,4 +1005,19 @@ static int enable_logger(void)
 	return 0;
 }
 
+#ifdef CONFIG_LOG_MODE_DEFERRED
+void log_flush(void)
+{
+	if (IS_ENABLED(CONFIG_LOG_PROCESS_THREAD)) {
+		while (atomic_get(&buffered_cnt)) {
+			log_thread_trigger();
+			k_sleep(K_USEC(CONFIG_LOG_FLUSH_SLEEP_US));
+		}
+	} else {
+		while (LOG_PROCESS()) {
+		}
+	}
+}
+#endif
+
 SYS_INIT(enable_logger, POST_KERNEL, CONFIG_LOG_CORE_INIT_PRIORITY);
diff --git a/subsys/logging/log_mgmt.c b/subsys/logging/log_mgmt.c
index 85d5e578f47..a004a4ab27c 100644
--- a/subsys/logging/log_mgmt.c
+++ b/subsys/logging/log_mgmt.c
@@ -560,12 +560,6 @@ void log_backend_enable(struct log_backend const *const backend,
 			void *ctx,
 			uint32_t level)
 {
-	/* As first slot in filtering mask is reserved, backend ID has offset.*/
-	uint32_t id = LOG_FILTER_FIRST_BACKEND_SLOT_IDX;
-
-	id += backend - log_backend_get(0);
-
-	log_backend_id_set(backend, id);
 	backend->cb->level = level;
 	backend_filter_set(backend, level);
 	log_backend_activate(backend, ctx);
diff --git a/subsys/logging/log_msg.c b/subsys/logging/log_msg.c
index f9b760f1e58..c1bd614ce0c 100644
--- a/subsys/logging/log_msg.c
+++ b/subsys/logging/log_msg.c
@@ -372,7 +372,10 @@ void z_log_msg_runtime_vcreate(uint8_t domain_id, const void *source,
 	struct log_msg_desc desc =
 		Z_LOG_MSG_DESC_INITIALIZER(domain_id, level, plen, dlen);
 
-	if (IS_ENABLED(CONFIG_LOG_MODE_DEFERRED) && BACKENDS_IN_USE()) {
+	if (IS_ENABLED(CONFIG_USERSPACE) && k_is_user_context()) {
+		pkg = alloca(plen);
+		msg = NULL;
+	} else if (IS_ENABLED(CONFIG_LOG_MODE_DEFERRED) && BACKENDS_IN_USE()) {
 		msg = z_log_msg_alloc(msg_wlen);
 		if (IS_ENABLED(CONFIG_LOG_FRONTEND) && msg == NULL) {
 			pkg = alloca(plen);
@@ -389,12 +392,17 @@ void z_log_msg_runtime_vcreate(uint8_t domain_id, const void *source,
 		__ASSERT_NO_MSG(plen >= 0);
 	}
 
-	if (IS_ENABLED(CONFIG_LOG_FRONTEND) && frontend_runtime_filtering(source, desc.level)) {
-		log_frontend_msg(source, desc, pkg, data);
-	}
+	if (IS_ENABLED(CONFIG_USERSPACE) && k_is_user_context()) {
+		z_log_msg_static_create(source, desc, pkg, data);
+	} else {
+		if (IS_ENABLED(CONFIG_LOG_FRONTEND) &&
+		    frontend_runtime_filtering(source, desc.level)) {
+			log_frontend_msg(source, desc, pkg, data);
+		}
 
-	if (BACKENDS_IN_USE()) {
-		z_log_msg_finalize(msg, source, desc, data);
+		if (BACKENDS_IN_USE()) {
+			z_log_msg_finalize(msg, source, desc, data);
+		}
 	}
 }
 EXPORT_SYMBOL(z_log_msg_runtime_vcreate);
diff --git a/subsys/lorawan/lorawan.c b/subsys/lorawan/lorawan.c
index 0f3c777fece..5a55281d086 100644
--- a/subsys/lorawan/lorawan.c
+++ b/subsys/lorawan/lorawan.c
@@ -93,6 +93,7 @@ static enum lorawan_channels_mask_size region_channels_mask_size =
 
 static lorawan_battery_level_cb_t battery_level_cb;
 static lorawan_dr_changed_cb_t dr_changed_cb;
+static lorawan_link_check_ans_cb_t link_check_cb;
 
 /* implementation required by the soft-se (software secure element) */
 void BoardGetUniqueId(uint8_t *id)
@@ -213,8 +214,10 @@ static void mlme_confirm_handler(MlmeConfirm_t *mlme_confirm)
 		LOG_INF("Joined network! DevAddr: %08x", mib_req.Param.DevAddr);
 		break;
 	case MLME_LINK_CHECK:
-		/* Not implemented */
-		LOG_INF("Link check not implemented yet!");
+		if (link_check_cb != NULL) {
+			link_check_cb(mlme_confirm->DemodMargin, mlme_confirm->NbGateways);
+		}
+		LOG_INF("Link check done");
 		break;
 	case MLME_DEVICE_TIME:
 		LOG_INF("DevTimeReq done");
@@ -399,6 +402,27 @@ int lorawan_set_region(enum lorawan_region region)
 	return 0;
 }
 
+int lorawan_request_link_check(bool force_request)
+{
+	int ret = 0;
+	LoRaMacStatus_t status;
+	MlmeReq_t mlme_req;
+
+	mlme_req.Type = MLME_LINK_CHECK;
+	status = LoRaMacMlmeRequest(&mlme_req);
+	if (status != LORAMAC_STATUS_OK) {
+		LOG_ERR("LinkCheckReq failed: %s", lorawan_status2str(status));
+		ret = lorawan_status2errno(status);
+		return ret;
+	}
+
+	if (force_request) {
+		ret = lorawan_send(0U, "", 0U, LORAWAN_MSG_UNCONFIRMED);
+	}
+
+	return ret;
+}
+
 int lorawan_request_device_time(bool force_request)
 {
 	int ret = 0;
@@ -732,6 +756,11 @@ void lorawan_register_dr_changed_callback(lorawan_dr_changed_cb_t cb)
 	dr_changed_cb = cb;
 }
 
+void lorawan_register_link_check_ans_callback(lorawan_link_check_ans_cb_t cb)
+{
+	link_check_cb = cb;
+}
+
 int lorawan_start(void)
 {
 	LoRaMacStatus_t status;
diff --git a/subsys/lorawan/services/clock_sync.c b/subsys/lorawan/services/clock_sync.c
index bac4b466cda..7334641e0af 100644
--- a/subsys/lorawan/services/clock_sync.c
+++ b/subsys/lorawan/services/clock_sync.c
@@ -16,6 +16,7 @@
 #include <zephyr/lorawan/lorawan.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/random/random.h>
+#include <zephyr/sys/__assert.h>
 
 LOG_MODULE_REGISTER(lorawan_clock_sync, CONFIG_LORAWAN_SERVICES_LOG_LEVEL);
 
@@ -69,13 +70,11 @@ static struct clock_sync_context ctx;
  *
  * @returns number of bytes written or -ENOSPC in case of error
  */
-static int clock_sync_serialize_device_time(uint8_t *buf, size_t size)
+static uint8_t clock_sync_serialize_device_time(uint8_t *buf, size_t size)
 {
 	uint32_t device_time = k_uptime_seconds() + ctx.time_offset;
 
-	if (size < sizeof(uint32_t)) {
-		return -ENOSPC;
-	}
+	__ASSERT_NO_MSG(size >= sizeof(uint32_t));
 
 	buf[0] = (device_time >> 0) & 0xFF;
 	buf[1] = (device_time >> 8) & 0xFF;
diff --git a/subsys/lorawan/services/frag_transport.c b/subsys/lorawan/services/frag_transport.c
index 5bb180bb161..2ee4c86e40f 100644
--- a/subsys/lorawan/services/frag_transport.c
+++ b/subsys/lorawan/services/frag_transport.c
@@ -101,6 +101,9 @@ static struct frag_transport_context ctx;
 /* Callback for notification of finished firmware transfer */
 static void (*finished_cb)(void);
 
+/* Callback to handle descriptor field */
+static transport_descriptor_cb descriptor_cb;
+
 static void frag_transport_package_callback(uint8_t port, uint8_t flags, int16_t rssi, int8_t snr,
 					    uint8_t len, const uint8_t *rx_buf)
 {
@@ -207,7 +210,14 @@ static void frag_transport_package_callback(uint8_t port, uint8_t flags, int16_t
 			}
 #endif
 
-			/* Descriptor not used: Ignore Wrong Descriptor error */
+			if (descriptor_cb != NULL) {
+				int rc = descriptor_cb(ctx.descriptor);
+
+				if (rc < 0) {
+					/* Wrong Descriptor */
+					status |= BIT(3);
+				}
+			}
 
 			if ((status & 0x1F) == 0) {
 #ifdef CONFIG_LORAWAN_FRAG_TRANSPORT_DECODER_SEMTECH
@@ -314,6 +324,11 @@ static void frag_transport_package_callback(uint8_t port, uint8_t flags, int16_t
 	}
 }
 
+void lorawan_frag_transport_register_descriptor_callback(transport_descriptor_cb cb)
+{
+	descriptor_cb = cb;
+}
+
 static struct lorawan_downlink_cb downlink_cb = {
 	.port = (uint8_t)LORAWAN_PORT_FRAG_TRANSPORT,
 	.cb = frag_transport_package_callback,
diff --git a/subsys/mgmt/ec_host_cmd/backends/Kconfig b/subsys/mgmt/ec_host_cmd/backends/Kconfig
index 8b03d0de844..e97b1d2fd18 100644
--- a/subsys/mgmt/ec_host_cmd/backends/Kconfig
+++ b/subsys/mgmt/ec_host_cmd/backends/Kconfig
@@ -120,3 +120,15 @@ config EC_HOST_CMD_BACKEND_SPI_STM32
 endchoice
 
 endif # EC_HOST_CMD_BACKEND_SPI
+
+if EC_HOST_CMD_BACKEND_UART
+
+config EC_HOST_CMD_BACKEND_UART_TIMEOUT
+	int "Timeout waiting for a rest of a message in ms"
+	default 150
+	help
+	  Host can send a message in chunks. Use this config to say how much time in ms
+	  UART backend should wait for the rest of a message after receiving first
+	  chunk.
+
+endif # EC_HOST_CMD_BACKEND_UART
diff --git a/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_uart.c b/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_uart.c
index 2e77d3f0ccd..fb7e4eec86e 100644
--- a/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_uart.c
+++ b/subsys/mgmt/ec_host_cmd/backends/ec_host_cmd_backend_uart.c
@@ -67,6 +67,16 @@ enum uart_host_command_state {
 	UART_HOST_CMD_RX_OVERRUN,
 };
 
+static const char * const state_name[] = {
+	[UART_HOST_CMD_STATE_DISABLED] = "DISABLED",
+	[UART_HOST_CMD_READY_TO_RX] = "READY_TO_RX",
+	[UART_HOST_CMD_RECEIVING] = "RECEIVING",
+	[UART_HOST_CMD_PROCESSING] = "PROCESSING",
+	[UART_HOST_CMD_SENDING] = "SENDING",
+	[UART_HOST_CMD_RX_BAD] = "RX_BAD",
+	[UART_HOST_CMD_RX_OVERRUN] = "RX_OVERRUN",
+};
+
 struct ec_host_cmd_uart_ctx {
 	const struct device *uart_dev;
 	struct ec_host_cmd_rx_ctx *rx_ctx;
@@ -100,9 +110,6 @@ static int request_expected_size(const struct ec_host_cmd_request_header *r)
 		.ctx = &_name##_hc_uart,                                                           \
 	}
 
-/* Timeout after receiving first byte */
-#define UART_REQ_RX_TIMEOUT K_MSEC(150)
-
 /*
  * Max data size for a version 3 request/response packet. This is big enough
  * to handle a request/response header, flash write offset/size and 512 bytes
@@ -116,32 +123,11 @@ static void rx_timeout(struct k_work *work)
 	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
 	struct ec_host_cmd_uart_ctx *hc_uart =
 		CONTAINER_OF(dwork, struct ec_host_cmd_uart_ctx, timeout_work);
-	int res;
 
-	switch (hc_uart->state) {
-	case UART_HOST_CMD_RECEIVING:
-		/* If state is receiving then timeout was hit due to underrun */
-		LOG_ERR("Request underrun detected");
-		break;
-	case UART_HOST_CMD_RX_OVERRUN:
-		/* If state is rx_overrun then timeout was hit because
-		 * process request was cancelled and extra rx bytes were
-		 * dropped
-		 */
-		LOG_ERR("Request overrun detected");
-		break;
-	case UART_HOST_CMD_RX_BAD:
-		/* If state is rx_bad then packet header was bad and process
-		 * request was cancelled to drop all incoming bytes.
-		 */
-		LOG_ERR("Bad packet header detected");
-		break;
-	default:
-		LOG_ERR("Request timeout mishandled, state: %d", hc_uart->state);
-	}
+	LOG_ERR("Request error in state: %s", state_name[hc_uart->state]);
 
-	res = uart_rx_disable(hc_uart->uart_dev);
-	res = uart_rx_enable(hc_uart->uart_dev, hc_uart->rx_ctx->buf, hc_uart->rx_buf_size, 0);
+	uart_rx_disable(hc_uart->uart_dev);
+	uart_rx_enable(hc_uart->uart_dev, hc_uart->rx_ctx->buf, hc_uart->rx_buf_size, 0);
 
 	hc_uart->state = UART_HOST_CMD_READY_TO_RX;
 }
@@ -156,10 +142,11 @@ static void uart_callback(const struct device *dev, struct uart_event *evt, void
 		if (hc_uart->state == UART_HOST_CMD_READY_TO_RX) {
 			hc_uart->rx_ctx->len = 0;
 			hc_uart->state = UART_HOST_CMD_RECEIVING;
-			k_work_reschedule(&hc_uart->timeout_work, UART_REQ_RX_TIMEOUT);
+			k_work_reschedule(&hc_uart->timeout_work,
+					  K_MSEC(CONFIG_EC_HOST_CMD_BACKEND_UART_TIMEOUT));
 		} else if (hc_uart->state == UART_HOST_CMD_PROCESSING ||
 			   hc_uart->state == UART_HOST_CMD_SENDING) {
-			LOG_ERR("UART HOST CMD ERROR: Received data while processing or sending");
+			LOG_ERR("Received data while in state: %s", state_name[hc_uart->state]);
 			return;
 		} else if (hc_uart->state == UART_HOST_CMD_RX_BAD ||
 			   hc_uart->state == UART_HOST_CMD_RX_OVERRUN) {
@@ -217,13 +204,13 @@ static void uart_callback(const struct device *dev, struct uart_event *evt, void
 		break;
 	case UART_TX_DONE:
 		if (hc_uart->state != UART_HOST_CMD_SENDING) {
-			LOG_ERR("UART HOST CMD ERROR: unexpected end of sending");
+			LOG_ERR("Unexpected end of sending");
 		}
 		/* Receiving is already enabled in the send function. */
 		hc_uart->state = UART_HOST_CMD_READY_TO_RX;
 		break;
 	case UART_RX_STOPPED:
-		LOG_ERR("UART HOST CMD ERROR: Receiving data stopped");
+		LOG_ERR("Receiving data stopped");
 		break;
 	default:
 		break;
@@ -273,7 +260,7 @@ static int ec_host_cmd_uart_send(const struct ec_host_cmd_backend *backend)
 	int ret;
 
 	if (hc_uart->state != UART_HOST_CMD_PROCESSING) {
-		LOG_ERR("UART HOST CMD ERROR: unexpected state while sending");
+		LOG_ERR("Unexpected state while sending");
 	}
 
 	/* The state is changed to UART_HOST_CMD_READY_TO_RX in the UART_TX_DONE event */
@@ -293,7 +280,7 @@ static int ec_host_cmd_uart_send(const struct ec_host_cmd_backend *backend)
 	/* If sending fails, reset the state */
 	if (ret) {
 		hc_uart->state = UART_HOST_CMD_READY_TO_RX;
-		LOG_ERR("UART HOST CMD ERROR: sending failed");
+		LOG_ERR("Sending failed");
 	}
 
 	return ret;
diff --git a/subsys/mgmt/hawkbit/Kconfig b/subsys/mgmt/hawkbit/Kconfig
index 8004fac4c1c..902a42eaf12 100644
--- a/subsys/mgmt/hawkbit/Kconfig
+++ b/subsys/mgmt/hawkbit/Kconfig
@@ -19,7 +19,6 @@ menuconfig HAWKBIT
 	select MPU_ALLOW_FLASH_WRITE
 	select IMG_ENABLE_IMAGE_CHECK
 	select IMG_ERASE_PROGRESSIVELY
-	imply HWINFO if !HAWKBIT_CUSTOM_DEVICE_ID
 	help
 	  hawkBit is a domain independent back-end framework for polling out
 	  software updates to constrained edge devices as well as more powerful
@@ -77,18 +76,28 @@ choice HAWKBIT_DDI_SECURITY
 
 config HAWKBIT_DDI_NO_SECURITY
 	bool "No authentication security"
+	select DEPRECATED
 	help
-	  No authentication security for the hawkBit DDI API.
+	  No authentication security for the hawkBit DDI API. Support for this
+	  had been removed from the hawkBit server in version 0.8.0. Use gateway
+	  security token authentication instead, if you want something similar.
 
 config HAWKBIT_DDI_TARGET_SECURITY
 	bool "Use target security token authentication"
 	help
 	  Use target security token authentication for the hawkBit DDI API.
+	  Here the security token is unique for each device and is generated
+	  during the device registration process. The device has to be registered
+	  in the hawkBit server before using this authentication mode.
 
 config HAWKBIT_DDI_GATEWAY_SECURITY
 	bool "Use gateway security token authentication"
 	help
 	  Use gateway security token authentication for the hawkBit DDI API.
+	  Here the security token is shared between all devices in the same
+	  tenant. The device can register itself in the hawkBit server on
+	  first connection to the server. The device does not need to be registered
+	  in the hawkBit server before using this authentication mode.
 
 endchoice
 
@@ -113,12 +122,21 @@ config HAWKBIT_STATUS_BUFFER_SIZE
 	  json strings, that are sent to the hawkBit server. It might
 	  be increased if the custom attributes are used extensively.
 
+choice HAWKBIT_DEVICE_ID_SOURCE
+	prompt "Source of the Hawkbit device ID"
+
+config HAWKBIT_HWINFO_DEVICE_ID
+	bool "Device ID through HWINFO module"
+	depends on HWINFO
+
 config HAWKBIT_CUSTOM_DEVICE_ID
 	bool "Custom device id through callback function"
 	help
 	  Be able to customize the device id during runtime to a custom value,
 	  by configuring the callback function. See `hawkbit_set_device_identity_cb`
 
+endchoice
+
 config HAWKBIT_DEVICE_ID_MAX_LENGTH
 	int "Maximum length of the device id"
 	depends on HAWKBIT_CUSTOM_DEVICE_ID
@@ -188,6 +206,26 @@ config HAWKBIT_EVENT_CALLBACKS
 	help
 	  Be able to set event callbacks for hawkBit.
 
+config HAWKBIT_SAVE_PROGRESS
+	bool "Save the hawkBit update download progress"
+	depends on STREAM_FLASH_PROGRESS
+	help
+	  Regularly save progress of hawkBit update download operation.
+	  When enabled, the download progress is periodically saved to
+	  non-volatile storage. If a download is interrupted, it can be resumed from
+	  the last saved point rather than starting over, saving bandwidth and time.
+	  This is especially useful for large updates over unreliable networks or in
+	  resource-constrained environments.
+
+config HAWKBIT_SAVE_PROGRESS_INTERVAL
+	int "Save the hawkBit update download progress interval"
+	default 5
+	range 0 100
+	depends on HAWKBIT_SAVE_PROGRESS
+	help
+	  Set the interval (in percent) that the hawkBit update download progress will be saved.
+	  0 means that the progress will be saved every time a new chunk is downloaded.
+
 module = HAWKBIT
 module-str = Log Level for hawkbit
 module-help = Enables logging for hawkBit code.
diff --git a/subsys/mgmt/hawkbit/hawkbit.c b/subsys/mgmt/hawkbit/hawkbit.c
index 2e833a2b078..28666b033d1 100644
--- a/subsys/mgmt/hawkbit/hawkbit.c
+++ b/subsys/mgmt/hawkbit/hawkbit.c
@@ -44,6 +44,7 @@ LOG_MODULE_REGISTER(hawkbit, CONFIG_HAWKBIT_LOG_LEVEL);
 #define SHA256_HASH_SIZE 32
 #define RESPONSE_BUFFER_SIZE 1100
 #define DDI_SECURITY_TOKEN_SIZE 32
+#define RANGE_HEADER_SIZE 50
 #define HAWKBIT_RECV_TIMEOUT (300 * MSEC_PER_SEC)
 #define HAWKBIT_SET_SERVER_TIMEOUT K_MSEC(300)
 
@@ -115,8 +116,6 @@ static struct hawkbit_config {
 #endif /* CONFIG_HAWKBIT_USE_DYNAMIC_CERT_TAG */
 
 struct hawkbit_download {
-	int download_status;
-	int download_progress;
 	size_t downloaded_size;
 	size_t http_content_size;
 	uint8_t file_hash[SHA256_HASH_SIZE];
@@ -343,6 +342,13 @@ static int hawkbit_settings_set(const char *name, size_t len, settings_read_cb r
 		return 0;
 	}
 #endif /* CONFIG_HAWKBIT_SET_SETTINGS_RUNTIME */
+	/* This is to omit the error message, as that is fetched in stream_flash_progress_load()
+	 * and we don't need to get it here.
+	 */
+	if (IS_ENABLED(CONFIG_HAWKBIT_SAVE_PROGRESS) &&
+	    settings_name_steq(name, "flash_progress", NULL)) {
+		return 0;
+	}
 
 	return -ENOENT;
 }
@@ -853,7 +859,7 @@ int hawkbit_init(void)
 		}
 
 		LOG_DBG("Marked current image as OK");
-		ret = boot_erase_img_bank(FIXED_PARTITION_ID(SLOT1_LABEL));
+		ret = boot_erase_img_bank(flash_img_get_upload_slot());
 		if (ret < 0) {
 			LOG_ERR("Failed to erase second slot: %d", ret);
 			return ret;
@@ -864,123 +870,155 @@ int hawkbit_init(void)
 	return ret;
 }
 
-static void response_cb(struct http_response *rsp, enum http_final_call final_data, void *userdata)
+static void response_json_cb(struct http_response *rsp, enum http_final_call final_data,
+			     struct hawkbit_context *hb_context)
 {
-	struct hawkbit_context *hb_context = userdata;
 	size_t body_len;
-	int ret, downloaded;
+	int ret;
 	uint8_t *body_data = NULL, *rsp_tmp = NULL;
 
-	if (rsp->http_status_code != 200) {
-		LOG_ERR("HTTP request denied: %d", rsp->http_status_code);
-		if (rsp->http_status_code == 401 || rsp->http_status_code == 403) {
-			hb_context->code_status = HAWKBIT_PERMISSION_ERROR;
-		} else {
-			hb_context->code_status = HAWKBIT_METADATA_ERROR;
-		}
-		return;
+	if (hb_context->dl.http_content_size == 0) {
+		hb_context->dl.http_content_size = rsp->content_length;
 	}
 
-	switch (hb_context->type) {
-	case HAWKBIT_PROBE:
-	case HAWKBIT_PROBE_DEPLOYMENT_BASE:
-		if (hb_context->dl.http_content_size == 0) {
-			hb_context->dl.http_content_size = rsp->content_length;
-		}
+	if (rsp->body_found) {
+		body_data = rsp->body_frag_start;
+		body_len = rsp->body_frag_len;
 
-		if (rsp->body_found) {
-			body_data = rsp->body_frag_start;
-			body_len = rsp->body_frag_len;
-
-			if ((hb_context->dl.downloaded_size + body_len) >
-			    hb_context->response_data_size) {
-				hb_context->response_data_size =
-					hb_context->dl.downloaded_size + body_len;
-				rsp_tmp = k_realloc(hb_context->response_data,
-						    hb_context->response_data_size);
-				if (rsp_tmp == NULL) {
-					LOG_ERR("Failed to realloc memory");
-					hb_context->code_status = HAWKBIT_ALLOC_ERROR;
-					break;
-				}
-
-				hb_context->response_data = rsp_tmp;
+		if ((hb_context->dl.downloaded_size + body_len) >
+			hb_context->response_data_size) {
+			hb_context->response_data_size =
+				hb_context->dl.downloaded_size + body_len;
+			rsp_tmp = k_realloc(hb_context->response_data,
+						hb_context->response_data_size);
+			if (rsp_tmp == NULL) {
+				LOG_ERR("Failed to realloc memory");
+				hb_context->code_status = HAWKBIT_ALLOC_ERROR;
+				return;
 			}
-			strncpy(hb_context->response_data + hb_context->dl.downloaded_size,
-				body_data, body_len);
-			hb_context->dl.downloaded_size += body_len;
+
+			hb_context->response_data = rsp_tmp;
+		}
+		strncpy(hb_context->response_data + hb_context->dl.downloaded_size,
+			body_data, body_len);
+		hb_context->dl.downloaded_size += body_len;
+	}
+
+	if (final_data == HTTP_DATA_FINAL) {
+		if (hb_context->dl.http_content_size != hb_context->dl.downloaded_size) {
+			LOG_ERR("HTTP response len mismatch, expected %d, got %d",
+				hb_context->dl.http_content_size,
+				hb_context->dl.downloaded_size);
+			hb_context->code_status = HAWKBIT_METADATA_ERROR;
+			return;
 		}
 
-		if (final_data == HTTP_DATA_FINAL) {
-			if (hb_context->dl.http_content_size != hb_context->dl.downloaded_size) {
-				LOG_ERR("HTTP response len mismatch, expected %d, got %d",
-					hb_context->dl.http_content_size,
-					hb_context->dl.downloaded_size);
+		hb_context->response_data[hb_context->dl.downloaded_size] = '\0';
+		memset(&hb_context->results, 0, sizeof(hb_context->results));
+		if (hb_context->type == HAWKBIT_PROBE) {
+			ret = json_obj_parse(
+				hb_context->response_data, hb_context->dl.downloaded_size,
+				json_ctl_res_descr, ARRAY_SIZE(json_ctl_res_descr),
+				&hb_context->results.base);
+			if (ret < 0) {
+				LOG_ERR("JSON parse error (%s): %d", "HAWKBIT_PROBE", ret);
 				hb_context->code_status = HAWKBIT_METADATA_ERROR;
-				break;
 			}
-
-			hb_context->response_data[hb_context->dl.downloaded_size] = '\0';
-			memset(&hb_context->results, 0, sizeof(hb_context->results));
-			if (hb_context->type == HAWKBIT_PROBE) {
-				ret = json_obj_parse(
-					hb_context->response_data, hb_context->dl.downloaded_size,
-					json_ctl_res_descr, ARRAY_SIZE(json_ctl_res_descr),
-					&hb_context->results.base);
-				if (ret < 0) {
-					LOG_ERR("JSON parse error (%s): %d", "HAWKBIT_PROBE", ret);
-					hb_context->code_status = HAWKBIT_METADATA_ERROR;
-				}
-			} else {
-				ret = json_obj_parse(
-					hb_context->response_data, hb_context->dl.downloaded_size,
-					json_dep_res_descr, ARRAY_SIZE(json_dep_res_descr),
-					&hb_context->results.dep);
-				if (ret < 0) {
-					LOG_ERR("JSON parse error (%s): %d", "deploymentBase", ret);
-					hb_context->code_status = HAWKBIT_METADATA_ERROR;
-				}
+		} else {
+			ret = json_obj_parse(
+				hb_context->response_data, hb_context->dl.downloaded_size,
+				json_dep_res_descr, ARRAY_SIZE(json_dep_res_descr),
+				&hb_context->results.dep);
+			if (ret < 0) {
+				LOG_ERR("JSON parse error (%s): %d", "deploymentBase", ret);
+				hb_context->code_status = HAWKBIT_METADATA_ERROR;
 			}
 		}
+	}
+}
 
-		break;
-
-	case HAWKBIT_DOWNLOAD:
-		if (hb_context->dl.http_content_size == 0) {
-			hb_context->dl.http_content_size = rsp->content_length;
+static void response_download_cb(struct http_response *rsp, enum http_final_call final_data,
+				 struct hawkbit_context *hb_context)
+{
+	size_t body_len;
+	int ret, downloaded;
+	uint8_t *body_data = NULL;
+	static uint8_t download_progress;
+
+	if (hb_context->dl.http_content_size == 0) {
+		hb_context->dl.http_content_size = rsp->content_length;
+		download_progress = 0;
+		if (IS_ENABLED(CONFIG_HAWKBIT_SAVE_PROGRESS) && rsp->http_status_code != 206) {
+			hb_context->flash_ctx.stream.bytes_written = 0;
 		}
+	}
 
-		if (rsp->body_found) {
-			body_data = rsp->body_frag_start;
-			body_len = rsp->body_frag_len;
+	if (!rsp->body_found) {
+		return;
+	}
 
-			ret = flash_img_buffered_write(&hb_context->flash_ctx, body_data, body_len,
-						       final_data == HTTP_DATA_FINAL);
-			if (ret < 0) {
-				LOG_ERR("Failed to write flash: %d", ret);
-				hb_context->code_status = HAWKBIT_DOWNLOAD_ERROR;
-				break;
-			}
-		}
+	body_data = rsp->body_frag_start;
+	body_len = rsp->body_frag_len;
 
-		hb_context->dl.downloaded_size = flash_img_bytes_written(&hb_context->flash_ctx);
+	ret = flash_img_buffered_write(&hb_context->flash_ctx, body_data, body_len,
+				       final_data == HTTP_DATA_FINAL);
+	if (ret < 0) {
+		LOG_ERR("Failed to write flash: %d", ret);
+		hb_context->code_status = HAWKBIT_DOWNLOAD_ERROR;
+		return;
+	}
+
+#if defined CONFIG_HAWKBIT_SAVE_PROGRESS && IS_EQ(CONFIG_HAWKBIT_SAVE_PROGRESS_INTERVAL, 0)
+	stream_flash_progress_save(&hb_context->flash_ctx.stream, "hawkbit/flash_progress");
+#endif
 
-		downloaded =
-			hb_context->dl.downloaded_size * 100 / hb_context->dl.http_content_size;
+	hb_context->dl.downloaded_size = flash_img_bytes_written(&hb_context->flash_ctx);
 
-		if (downloaded > hb_context->dl.download_progress) {
-			hb_context->dl.download_progress = downloaded;
-			LOG_DBG("Downloaded: %d%% ", hb_context->dl.download_progress);
+	downloaded = hb_context->dl.downloaded_size * 100 / hb_context->dl.file_size;
+
+	if (downloaded != download_progress) {
+#if defined CONFIG_HAWKBIT_SAVE_PROGRESS && !IS_EQ(CONFIG_HAWKBIT_SAVE_PROGRESS_INTERVAL, 0)
+		if ((downloaded / CONFIG_HAWKBIT_SAVE_PROGRESS_INTERVAL) >
+		    (download_progress / CONFIG_HAWKBIT_SAVE_PROGRESS_INTERVAL)) {
+			stream_flash_progress_save(&hb_context->flash_ctx.stream,
+						   "hawkbit/flash_progress");
 		}
+#endif
+		download_progress = downloaded;
+		LOG_DBG("Downloaded: %u%% (%u / %u)", download_progress,
+			hb_context->dl.downloaded_size, hb_context->dl.file_size);
+	}
 
-		if (final_data == HTTP_DATA_FINAL) {
-			hb_context->final_data_received = true;
+	if (final_data == HTTP_DATA_FINAL) {
+		hb_context->final_data_received = true;
+	}
+}
+
+static void response_cb(struct http_response *rsp, enum http_final_call final_data, void *userdata)
+{
+	struct hawkbit_context *hb_context = userdata;
+
+	if (!IN_RANGE(rsp->http_status_code, 200, 299)) {
+		LOG_ERR("HTTP request denied: %d", rsp->http_status_code);
+		if (rsp->http_status_code == 401 || rsp->http_status_code == 403) {
+			hb_context->code_status = HAWKBIT_PERMISSION_ERROR;
+		} else {
+			hb_context->code_status = HAWKBIT_METADATA_ERROR;
 		}
+		return;
+	}
 
+	switch (hb_context->type) {
+	case HAWKBIT_PROBE:
+	case HAWKBIT_PROBE_DEPLOYMENT_BASE:
+		response_json_cb(rsp, final_data, hb_context);
 		break;
 
-	default:
+	case HAWKBIT_DOWNLOAD:
+		response_download_cb(rsp, final_data, hb_context);
+		break;
 
+	default:
 		break;
 	}
 }
@@ -1055,6 +1093,13 @@ static bool send_request(struct hawkbit_context *hb_context, enum hawkbit_http_r
 		 * Resource for software module (Deployment Base)
 		 * GET: /{tenant}/controller/v1/{controllerId}/deploymentBase/{actionId}
 		 */
+
+		http_req.method = HTTP_GET;
+		hb_context->dl.http_content_size = 0;
+		hb_context->dl.downloaded_size = 0;
+
+		break;
+
 	case HAWKBIT_DOWNLOAD:
 		/*
 		 * Resource for software module (Deployment Base)
@@ -1063,7 +1108,23 @@ static bool send_request(struct hawkbit_context *hb_context, enum hawkbit_http_r
 		 */
 		http_req.method = HTTP_GET;
 		hb_context->dl.http_content_size = 0;
+
+#ifdef CONFIG_HAWKBIT_SAVE_PROGRESS
+		hb_context->dl.downloaded_size = flash_img_bytes_written(&hb_context->flash_ctx);
+		if (IN_RANGE(hb_context->dl.downloaded_size, 1, hb_context->dl.file_size)) {
+			char header_range[RANGE_HEADER_SIZE] = {0};
+
+			snprintf(header_range, sizeof(header_range), "Range: bytes=%u-" HTTP_CRLF,
+				 hb_context->dl.downloaded_size);
+			const char *const headers_range[] = {header_range, NULL};
+
+			http_req.optional_headers = (const char **)headers_range;
+			LOG_DBG("optional header: %s", header_range);
+			LOG_INF("Resuming download from %d bytes", hb_context->dl.downloaded_size);
+		}
+#else
 		hb_context->dl.downloaded_size = 0;
+#endif
 
 		break;
 
@@ -1459,6 +1520,10 @@ static void s_download(void *o)
 	 */
 	flash_area_ptr = s->hb_context.flash_ctx.flash_area;
 
+#ifdef CONFIG_HAWKBIT_SAVE_PROGRESS
+	stream_flash_progress_load(&s->hb_context.flash_ctx.stream, "hawkbit/flash_progress");
+#endif
+
 	if (!send_request(&s->hb_context, HAWKBIT_DOWNLOAD, url_buffer, NULL)) {
 		LOG_ERR("Send request failed (%s)", "HAWKBIT_DOWNLOAD");
 		smf_set_state(SMF_CTX(s), &hawkbit_states[S_HAWKBIT_TERMINATE]);
@@ -1473,6 +1538,10 @@ static void s_download(void *o)
 		return;
 	}
 
+#ifdef CONFIG_HAWKBIT_SAVE_PROGRESS
+	stream_flash_progress_clear(&s->hb_context.flash_ctx.stream, "hawkbit/flash_progress");
+#endif
+
 	/* Verify the hash of the stored firmware */
 	fic.match = s->hb_context.dl.file_hash;
 	fic.clen = s->hb_context.dl.downloaded_size;
diff --git a/subsys/mgmt/hawkbit/hawkbit_device.c b/subsys/mgmt/hawkbit/hawkbit_device.c
index 2d39c845a3e..c574316667a 100644
--- a/subsys/mgmt/hawkbit/hawkbit_device.c
+++ b/subsys/mgmt/hawkbit/hawkbit_device.c
@@ -19,7 +19,7 @@ bool hawkbit_get_device_identity(char *id, int id_max_len)
 
 static bool hawkbit_get_device_identity_default(char *id, int id_max_len)
 {
-#ifdef CONFIG_HWINFO
+#ifdef CONFIG_HAWKBIT_HWINFO_DEVICE_ID
 	uint8_t hwinfo_id[DEVICE_ID_BIN_MAX_SIZE];
 	ssize_t length;
 
@@ -32,12 +32,12 @@ static bool hawkbit_get_device_identity_default(char *id, int id_max_len)
 	length = bin2hex(hwinfo_id, (size_t)length, id, id_max_len);
 
 	return length > 0;
-#else /* CONFIG_HWINFO */
+#else /* CONFIG_HAWKBIT_HWINFO_DEVICE_ID */
 	ARG_UNUSED(id);
 	ARG_UNUSED(id_max_len);
 
 	return false;
-#endif /* CONFIG_HWINFO */
+#endif /* CONFIG_HAWKBIT_HWINFO_DEVICE_ID */
 }
 
 #ifdef CONFIG_HAWKBIT_CUSTOM_DEVICE_ID
diff --git a/subsys/mgmt/mcumgr/grp/fs_mgmt/src/fs_mgmt.c b/subsys/mgmt/mcumgr/grp/fs_mgmt/src/fs_mgmt.c
index 1052ec2ef4c..7d491e93e6e 100644
--- a/subsys/mgmt/mcumgr/grp/fs_mgmt/src/fs_mgmt.c
+++ b/subsys/mgmt/mcumgr/grp/fs_mgmt/src/fs_mgmt.c
@@ -190,9 +190,39 @@ static bool fs_mgmt_file_rsp(zcbor_state_t *zse, int rc, uint64_t off)
 static void fs_mgmt_upload_download_finish_check(void)
 {
 	if (fs_mgmt_ctxt.len > 0 && fs_mgmt_ctxt.off >= fs_mgmt_ctxt.len) {
+#if defined(CONFIG_MCUMGR_GRP_FS_FILE_ACCESS_HOOK)
+		char path[CONFIG_MCUMGR_GRP_FS_PATH_LEN + 1];
+		struct fs_mgmt_file_access file_access_data = {
+			.filename = path,
+		};
+		int32_t err_rc;
+		uint16_t err_group;
+
+		strcpy(path, fs_mgmt_ctxt.path);
+
+		switch (fs_mgmt_ctxt.state) {
+		case STATE_DOWNLOAD:
+			file_access_data.access = FS_MGMT_FILE_ACCESS_READ;
+			break;
+
+		case STATE_UPLOAD:
+			file_access_data.access = FS_MGMT_FILE_ACCESS_WRITE;
+			break;
+
+		default:
+			break;
+		}
+#endif
+
 		/* File upload/download has finished, clean up */
 		k_work_cancel_delayable(&fs_mgmt_ctxt.file_close_work);
 		fs_mgmt_cleanup();
+
+#if defined(CONFIG_MCUMGR_GRP_FS_FILE_ACCESS_HOOK)
+		/* Warn application that file download/upload is done. */
+		(void)mgmt_callback_notify(MGMT_EVT_OP_FS_MGMT_FILE_ACCESS_DONE, &file_access_data,
+					   sizeof(file_access_data), &err_rc, &err_group);
+#endif
 	} else {
 		k_work_reschedule(&fs_mgmt_ctxt.file_close_work, FILE_CLOSE_IDLE_TIME);
 	}
diff --git a/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt.c b/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt.c
index 399d87be1d8..8fb938e7e9a 100644
--- a/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt.c
+++ b/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt.c
@@ -13,6 +13,7 @@
 #include <zephyr/toolchain.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/storage/flash_map.h>
+#include <zephyr/dfu/mcuboot.h>
 
 #include <zcbor_common.h>
 #include <zcbor_decode.h>
@@ -286,7 +287,10 @@ int img_mgmt_read_info(int image_slot, struct image_version *ver, uint8_t *hash,
 		return IMG_MGMT_ERR_FLASH_CONFIG_QUERY_FAIL;
 	}
 
-	rc = img_mgmt_read(image_slot, 0, &hdr, sizeof(hdr));
+	rc = img_mgmt_read(image_slot,
+			   boot_get_image_start_offset(img_mgmt_flash_area_id(image_slot)),
+			   &hdr, sizeof(hdr));
+
 	if (rc != 0) {
 		return rc;
 	}
@@ -314,7 +318,8 @@ int img_mgmt_read_info(int image_slot, struct image_version *ver, uint8_t *hash,
 	 * TLV. All images are required to have a hash TLV.  If the hash is missing, the image
 	 * is considered invalid.
 	 */
-	data_off = hdr.ih_hdr_size + hdr.ih_img_size;
+	data_off = hdr.ih_hdr_size + hdr.ih_img_size +
+		   boot_get_image_start_offset(img_mgmt_flash_area_id(image_slot));
 
 	rc = img_mgmt_find_tlvs(image_slot, &data_off, &data_end, IMAGE_TLV_PROT_INFO_MAGIC);
 	if (!rc) {
diff --git a/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt_state.c b/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt_state.c
index 9e3e867e17d..db2bec057f6 100644
--- a/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt_state.c
+++ b/subsys/mgmt/mcumgr/grp/img_mgmt/src/img_mgmt_state.c
@@ -285,8 +285,8 @@ int img_mgmt_get_next_boot_slot(int image, enum img_mgmt_next_boot_type *type)
 			return_slot = other_slot;
 		}
 	}
-out:
 
+out:
 #else
 	if (rcs == 0 && rca == 0 && img_mgmt_vercmp(&aver, &over) < 0) {
 		return_slot = other_slot;
@@ -388,11 +388,6 @@ img_mgmt_state_confirm(void)
 {
 	int rc;
 
-#if defined(CONFIG_MCUMGR_GRP_IMG_STATUS_HOOKS)
-	int32_t err_rc;
-	uint16_t err_group;
-#endif
-
 	/* Confirm disallowed if a test is pending. */
 	if (img_mgmt_state_any_pending()) {
 		rc = IMG_MGMT_ERR_IMAGE_ALREADY_PENDING;
@@ -402,8 +397,16 @@ img_mgmt_state_confirm(void)
 	rc = img_mgmt_write_confirmed();
 
 #if defined(CONFIG_MCUMGR_GRP_IMG_STATUS_HOOKS)
-	(void)mgmt_callback_notify(MGMT_EVT_OP_IMG_MGMT_DFU_CONFIRMED, NULL, 0, &err_rc,
-				   &err_group);
+	if (!rc) {
+		int32_t err_rc;
+		uint16_t err_group;
+		struct img_mgmt_image_confirmed confirmed_data = {
+			.image = 0
+		};
+
+		(void)mgmt_callback_notify(MGMT_EVT_OP_IMG_MGMT_DFU_CONFIRMED, &confirmed_data,
+					   sizeof(confirmed_data), &err_rc, &err_group);
+	}
 #endif
 
 err:
@@ -574,12 +577,15 @@ static int img_mgmt_set_next_boot_slot_common(int slot, int active_slot, bool co
 
 #if defined(CONFIG_MCUMGR_GRP_IMG_STATUS_HOOKS)
 	if (rc == 0 && slot == active_slot && confirm) {
+		/* Confirm event is only sent for active slot */
 		int32_t err_rc;
 		uint16_t err_group;
+		struct img_mgmt_image_confirmed confirmed_data = {
+			.image = img_mgmt_slot_to_image(slot)
+		};
 
-		/* Confirm event is only sent for active slot */
-		(void)mgmt_callback_notify(MGMT_EVT_OP_IMG_MGMT_DFU_CONFIRMED, NULL, 0, &err_rc,
-					   &err_group);
+		(void)mgmt_callback_notify(MGMT_EVT_OP_IMG_MGMT_DFU_CONFIRMED, &confirmed_data,
+					   sizeof(confirmed_data), &err_rc, &err_group);
 	}
 #endif
 
diff --git a/subsys/mgmt/mcumgr/grp/img_mgmt/src/zephyr_img_mgmt.c b/subsys/mgmt/mcumgr/grp/img_mgmt/src/zephyr_img_mgmt.c
index 8d58a3b8634..3c9223a54e1 100644
--- a/subsys/mgmt/mcumgr/grp/img_mgmt/src/zephyr_img_mgmt.c
+++ b/subsys/mgmt/mcumgr/grp/img_mgmt/src/zephyr_img_mgmt.c
@@ -441,6 +441,10 @@ int img_mgmt_erase_image_data(unsigned int off, unsigned int num_bytes)
 {
 	const struct flash_area *fa;
 	int rc;
+	const struct device *dev;
+	struct flash_pages_info page;
+	off_t page_offset;
+	size_t erase_size;
 
 	if (off != 0) {
 		rc = IMG_MGMT_ERR_INVALID_OFFSET;
@@ -454,16 +458,15 @@ int img_mgmt_erase_image_data(unsigned int off, unsigned int num_bytes)
 		goto end;
 	}
 
-	/* align requested erase size to the erase-block-size */
-	const struct device *dev = flash_area_get_device(fa);
+	/* Align requested erase size to the erase-block-size */
+	dev = flash_area_get_device(fa);
 
 	if (dev == NULL) {
 		rc = IMG_MGMT_ERR_FLASH_AREA_DEVICE_NULL;
 		goto end_fa;
 	}
-	struct flash_pages_info page;
-	off_t page_offset = fa->fa_off + num_bytes - 1;
 
+	page_offset = fa->fa_off + num_bytes - 1;
 	rc = flash_get_page_info_by_offs(dev, page_offset, &page);
 	if (rc != 0) {
 		LOG_ERR("bad offset (0x%lx)", (long)page_offset);
@@ -471,9 +474,9 @@ int img_mgmt_erase_image_data(unsigned int off, unsigned int num_bytes)
 		goto end_fa;
 	}
 
-	size_t erase_size = page.start_offset + page.size - fa->fa_off;
-
-	rc = flash_area_flatten(fa, 0, erase_size);
+	erase_size = page.start_offset + page.size - fa->fa_off;
+	rc = flash_area_flatten(fa, boot_get_image_start_offset(g_img_mgmt_state.area_id),
+				erase_size);
 
 	if (rc != 0) {
 		LOG_ERR("image slot erase of 0x%zx bytes failed (err %d)", erase_size,
@@ -560,6 +563,7 @@ int img_mgmt_upload_inspect(const struct img_mgmt_upload_req *req,
 	if (req->off == SIZE_MAX) {
 		/* Request did not include an `off` field. */
 		IMG_MGMT_UPLOAD_ACTION_SET_RC_RSN(action, img_mgmt_err_str_hdr_malformed);
+		LOG_DBG("Request did not include an `off` field");
 		return IMG_MGMT_ERR_INVALID_OFFSET;
 	}
 
@@ -568,6 +572,8 @@ int img_mgmt_upload_inspect(const struct img_mgmt_upload_req *req,
 		const struct flash_area *fa;
 #if defined(CONFIG_MCUMGR_GRP_IMG_TOO_LARGE_SYSBUILD) &&			\
 	(defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_WITHOUT_SCRATCH) ||	\
+	 defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_USING_OFFSET) ||		\
+	 defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_USING_MOVE) ||		\
 	 defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_SCRATCH) ||		\
 	 defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY) ||		\
 	 defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD) ||			\
@@ -583,12 +589,15 @@ int img_mgmt_upload_inspect(const struct img_mgmt_upload_req *req,
 		if (req->img_data.len < sizeof(struct image_header)) {
 			/*  Image header is the first thing in the image */
 			IMG_MGMT_UPLOAD_ACTION_SET_RC_RSN(action, img_mgmt_err_str_hdr_malformed);
+			LOG_DBG("Image data too short: %u < %u", req->img_data.len,
+				sizeof(struct image_header));
 			return IMG_MGMT_ERR_INVALID_IMAGE_HEADER;
 		}
 
 		if (req->size == SIZE_MAX) {
 			/* Request did not include a `len` field. */
 			IMG_MGMT_UPLOAD_ACTION_SET_RC_RSN(action, img_mgmt_err_str_hdr_malformed);
+			LOG_DBG("Request did not include a `len` field");
 			return IMG_MGMT_ERR_INVALID_LENGTH;
 		}
 
@@ -597,10 +606,12 @@ int img_mgmt_upload_inspect(const struct img_mgmt_upload_req *req,
 		hdr = (struct image_header *)req->img_data.value;
 		if (hdr->ih_magic != IMAGE_MAGIC) {
 			IMG_MGMT_UPLOAD_ACTION_SET_RC_RSN(action, img_mgmt_err_str_magic_mismatch);
+			LOG_DBG("Magic mismatch: %08X != %08X", hdr->ih_magic, IMAGE_MAGIC);
 			return IMG_MGMT_ERR_INVALID_IMAGE_HEADER_MAGIC;
 		}
 
 		if (req->data_sha.len > IMG_MGMT_DATA_SHA_LEN) {
+			LOG_DBG("Invalid hash length: %u", req->data_sha.len);
 			return IMG_MGMT_ERR_INVALID_HASH;
 		}
 
@@ -620,8 +631,9 @@ int img_mgmt_upload_inspect(const struct img_mgmt_upload_req *req,
 
 		action->area_id = img_mgmt_get_unused_slot_area_id(req->image);
 		if (action->area_id < 0) {
-			/* No slot where to upload! */
+			/* No slot available to upload to */
 			IMG_MGMT_UPLOAD_ACTION_SET_RC_RSN(action, img_mgmt_err_str_no_slot);
+			LOG_DBG("No slot available to upload to");
 			return IMG_MGMT_ERR_NO_FREE_SLOT;
 		}
 
@@ -638,12 +650,15 @@ int img_mgmt_upload_inspect(const struct img_mgmt_upload_req *req,
 			IMG_MGMT_UPLOAD_ACTION_SET_RC_RSN(action,
 				img_mgmt_err_str_image_too_large);
 			flash_area_close(fa);
-			LOG_ERR("Upload too large for slot: %u > %u", req->size, fa->fa_size);
+			LOG_DBG("Upload too large for slot: %u > %u", req->size,
+				fa->fa_size);
 			return IMG_MGMT_ERR_INVALID_IMAGE_TOO_LARGE;
 		}
 
 #if defined(CONFIG_MCUMGR_GRP_IMG_TOO_LARGE_SYSBUILD) &&			\
 	(defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_WITHOUT_SCRATCH) ||	\
+	 defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_USING_OFFSET) ||		\
+	 defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_USING_MOVE) ||		\
 	 defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_SCRATCH) ||		\
 	 defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY) ||		\
 	 defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD) ||			\
@@ -688,7 +703,7 @@ int img_mgmt_upload_inspect(const struct img_mgmt_upload_req *req,
 			IMG_MGMT_UPLOAD_ACTION_SET_RC_RSN(action,
 				img_mgmt_err_str_image_too_large);
 			flash_area_close(fa);
-			LOG_ERR("Upload too large for slot (with end offset): %u > %u", req->size,
+			LOG_DBG("Upload too large for slot (with end offset): %u > %u", req->size,
 				(fa->fa_size - CONFIG_MCUBOOT_UPDATE_FOOTER_SIZE));
 			return IMG_MGMT_ERR_INVALID_IMAGE_TOO_LARGE;
 		}
@@ -703,7 +718,7 @@ int img_mgmt_upload_inspect(const struct img_mgmt_upload_req *req,
 			IMG_MGMT_UPLOAD_ACTION_SET_RC_RSN(action,
 				img_mgmt_err_str_image_too_large);
 			flash_area_close(fa);
-			LOG_ERR("Upload too large for slot (with max image size): %u > %u",
+			LOG_DBG("Upload too large for slot (with max image size): %u > %u",
 				req->size, max_image_size);
 			return IMG_MGMT_ERR_INVALID_IMAGE_TOO_LARGE;
 		}
@@ -715,6 +730,8 @@ int img_mgmt_upload_inspect(const struct img_mgmt_upload_req *req,
 				IMG_MGMT_UPLOAD_ACTION_SET_RC_RSN(action,
 					img_mgmt_err_str_image_bad_flash_addr);
 				flash_area_close(fa);
+				LOG_DBG("Invalid flash address: %08X, expected: %08X",
+					hdr->ih_load_addr, (int)fa->fa_off);
 				return IMG_MGMT_ERR_INVALID_FLASH_ADDRESS;
 			}
 		}
@@ -728,12 +745,18 @@ int img_mgmt_upload_inspect(const struct img_mgmt_upload_req *req,
 			 */
 			rc = img_mgmt_my_version(&cur_ver);
 			if (rc != 0) {
+				LOG_DBG("Version get failed: %d", rc);
 				return IMG_MGMT_ERR_VERSION_GET_FAILED;
 			}
 
 			if (img_mgmt_vercmp(&cur_ver, &hdr->ih_ver) >= 0) {
 				IMG_MGMT_UPLOAD_ACTION_SET_RC_RSN(action,
 					img_mgmt_err_str_downgrade);
+				LOG_DBG("Downgrade: %d.%d.%d.%d, expected: %d.%d.%d.%d",
+					cur_ver.iv_major, cur_ver.iv_minor, cur_ver.iv_revision,
+					cur_ver.iv_build_num, hdr->ih_ver.iv_major,
+					hdr->ih_ver.iv_minor, hdr->ih_ver.iv_revision,
+					hdr->ih_ver.iv_build_num);
 				return IMG_MGMT_ERR_CURRENT_VERSION_IS_NEWER;
 			}
 		}
@@ -741,6 +764,7 @@ int img_mgmt_upload_inspect(const struct img_mgmt_upload_req *req,
 #ifndef CONFIG_IMG_ERASE_PROGRESSIVELY
 		rc = img_mgmt_flash_check_empty(action->area_id);
 		if (rc < 0) {
+			LOG_DBG("Flash check empty failed: %d", rc);
 			return rc;
 		}
 
@@ -756,6 +780,8 @@ int img_mgmt_upload_inspect(const struct img_mgmt_upload_req *req,
 			 * Invalid offset. Drop the data, and respond with the offset we're
 			 * expecting data for.
 			 */
+			LOG_DBG("Invalid offset: %08x, expected: %08x", req->off,
+				g_img_mgmt_state.off);
 			return IMG_MGMT_ERR_OK;
 		}
 
@@ -764,6 +790,8 @@ int img_mgmt_upload_inspect(const struct img_mgmt_upload_req *req,
 			 * of the image that the client originally sent
 			 */
 			IMG_MGMT_UPLOAD_ACTION_SET_RC_RSN(action, img_mgmt_err_str_data_overrun);
+			LOG_DBG("Data overrun: %u + %u > %llu", req->off, req->img_data.len,
+				action->size);
 			return IMG_MGMT_ERR_INVALID_IMAGE_DATA_OVERRUN;
 		}
 	}
@@ -782,6 +810,7 @@ int img_mgmt_erased_val(int slot, uint8_t *erased_val)
 	int area_id = img_mgmt_flash_area_id(slot);
 
 	if (area_id < 0) {
+		LOG_DBG("Invalid slot: %d", area_id);
 		return IMG_MGMT_ERR_INVALID_SLOT;
 	}
 
diff --git a/subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h b/subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h
index 71dfda7c193..21f9f272a63 100644
--- a/subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h
+++ b/subsys/mgmt/mcumgr/grp/os_mgmt/include/os_mgmt_processor.h
@@ -103,6 +103,8 @@ extern "C" {
 #else
 #define PROCESSOR_NAME "cortex-r52"
 #endif
+#elif defined(CONFIG_CPU_CORTEX_A7)
+#define PROCESSOR_NAME "cortex-a7"
 #elif defined(CONFIG_CPU_CORTEX_A9)
 #define PROCESSOR_NAME "cortex-a9"
 #endif
diff --git a/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c b/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c
index 8629c0030f9..3fc4d42cfe1 100644
--- a/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c
+++ b/subsys/mgmt/mcumgr/grp/os_mgmt/src/os_mgmt.c
@@ -430,7 +430,10 @@ os_mgmt_mcumgr_params(struct smp_streamer *ctxt)
 #define BOOTLOADER_MODE MCUBOOT_MODE_SWAP_USING_SCRATCH
 #elif defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_OVERWRITE_ONLY)
 #define BOOTLOADER_MODE MCUBOOT_MODE_UPGRADE_ONLY
-#elif defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_WITHOUT_SCRATCH)
+#elif defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_USING_OFFSET)
+#define BOOTLOADER_MODE MCUBOOT_MODE_SWAP_USING_OFFSET
+#elif defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_USING_MOVE) || \
+defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_WITHOUT_SCRATCH)
 #define BOOTLOADER_MODE MCUBOOT_MODE_SWAP_USING_MOVE
 #elif defined(CONFIG_MCUBOOT_BOOTLOADER_MODE_DIRECT_XIP)
 #define BOOTLOADER_MODE MCUBOOT_MODE_DIRECT_XIP
diff --git a/subsys/mgmt/mcumgr/smp/src/smp.c b/subsys/mgmt/mcumgr/smp/src/smp.c
index 693a26f4d1f..0da3815907d 100644
--- a/subsys/mgmt/mcumgr/smp/src/smp.c
+++ b/subsys/mgmt/mcumgr/smp/src/smp.c
@@ -310,9 +310,15 @@ static int smp_handle_single_req(struct smp_streamer *streamer, const struct smp
 	}
 #endif
 
-	smp_make_rsp_hdr(req_hdr, &rsp_hdr,
-			 zsp->payload_mut - nbw->nb->data - MGMT_HDR_SIZE);
-	nbw->nb->len = zsp->payload_mut - nbw->nb->data;
+#if defined(CONFIG_MCUMGR_MGMT_CUSTOM_PAYLOAD)
+	if (!mgmt_find_group(req_hdr->nh_group)->custom_payload) {
+#endif
+		nbw->nb->len = zsp->payload_mut - nbw->nb->data;
+#if defined(CONFIG_MCUMGR_MGMT_CUSTOM_PAYLOAD)
+	}
+#endif
+
+	smp_make_rsp_hdr(req_hdr, &rsp_hdr, (nbw->nb->len - MGMT_HDR_SIZE));
 	smp_write_hdr(streamer, &rsp_hdr);
 
 	return 0;
diff --git a/subsys/mgmt/mcumgr/transport/src/smp_lorawan.c b/subsys/mgmt/mcumgr/transport/src/smp_lorawan.c
index e6d330d01bb..b073626add4 100644
--- a/subsys/mgmt/mcumgr/transport/src/smp_lorawan.c
+++ b/subsys/mgmt/mcumgr/transport/src/smp_lorawan.c
@@ -249,10 +249,6 @@ static void smp_lorawan_start(void)
 		LOG_ERR("Failed to init LoRaWAN MCUmgr SMP transport: %d", rc);
 	}
 
-#ifdef CONFIG_MCUMGR_TRANSPORT_LORAWAN_REASSEMBLY
-	smp_reassembly_init(&smp_lorawan_transport);
-#endif
-
 #ifdef CONFIG_MCUMGR_TRANSPORT_LORAWAN_POLL_FOR_DATA
 	k_thread_create(&smp_lorawan_thread, smp_lorawan_stack,
 			K_KERNEL_STACK_SIZEOF(smp_lorawan_stack),
diff --git a/subsys/mgmt/mcumgr/transport/src/smp_udp.c b/subsys/mgmt/mcumgr/transport/src/smp_udp.c
index 60ed9816ed2..8067b36d6e6 100644
--- a/subsys/mgmt/mcumgr/transport/src/smp_udp.c
+++ b/subsys/mgmt/mcumgr/transport/src/smp_udp.c
@@ -163,38 +163,29 @@ static int create_socket(enum proto_type proto, int *sock)
 {
 	int tmp_sock;
 	int err;
-	struct sockaddr *addr;
+	struct sockaddr_storage addr_storage;
+	struct sockaddr *addr = (struct sockaddr *)&addr_storage;
 	socklen_t addr_len = 0;
 
-#ifdef CONFIG_MCUMGR_TRANSPORT_UDP_IPV4
-	struct sockaddr_in addr4;
-#endif
-
-#ifdef CONFIG_MCUMGR_TRANSPORT_UDP_IPV6
-	struct sockaddr_in6 addr6;
-#endif
-
-#ifdef CONFIG_MCUMGR_TRANSPORT_UDP_IPV4
-	if (proto == PROTOCOL_IPV4) {
-		addr_len = sizeof(struct sockaddr_in);
-		memset(&addr4, 0, sizeof(addr4));
-		addr4.sin_family = AF_INET;
-		addr4.sin_port = htons(CONFIG_MCUMGR_TRANSPORT_UDP_PORT);
-		addr4.sin_addr.s_addr = htonl(INADDR_ANY);
-		addr = (struct sockaddr *)&addr4;
+	if (IS_ENABLED(CONFIG_MCUMGR_TRANSPORT_UDP_IPV4) &&
+	    proto == PROTOCOL_IPV4) {
+		struct sockaddr_in *addr4 = (struct sockaddr_in *)addr;
+
+		addr_len = sizeof(*addr4);
+		memset(addr4, 0, sizeof(*addr4));
+		addr4->sin_family = AF_INET;
+		addr4->sin_port = htons(CONFIG_MCUMGR_TRANSPORT_UDP_PORT);
+		addr4->sin_addr.s_addr = htonl(INADDR_ANY);
+	} else if (IS_ENABLED(CONFIG_MCUMGR_TRANSPORT_UDP_IPV6) &&
+		   proto == PROTOCOL_IPV6) {
+		struct sockaddr_in6 *addr6 = (struct sockaddr_in6 *)addr;
+
+		addr_len = sizeof(*addr6);
+		memset(addr6, 0, sizeof(*addr6));
+		addr6->sin6_family = AF_INET6;
+		addr6->sin6_port = htons(CONFIG_MCUMGR_TRANSPORT_UDP_PORT);
+		addr6->sin6_addr = in6addr_any;
 	}
-#endif
-
-#ifdef CONFIG_MCUMGR_TRANSPORT_UDP_IPV6
-	if (proto == PROTOCOL_IPV6) {
-		addr_len = sizeof(struct sockaddr_in6);
-		memset(&addr6, 0, sizeof(addr6));
-		addr6.sin6_family = AF_INET6;
-		addr6.sin6_port = htons(CONFIG_MCUMGR_TRANSPORT_UDP_PORT);
-		addr6.sin6_addr = in6addr_any;
-		addr = (struct sockaddr *)&addr6;
-	}
-#endif
 
 	tmp_sock = zsock_socket(addr->sa_family, SOCK_DGRAM, IPPROTO_UDP);
 	err = errno;
diff --git a/subsys/modbus/modbus_serial.c b/subsys/modbus/modbus_serial.c
index 05ab70563ee..d9087693c6f 100644
--- a/subsys/modbus/modbus_serial.c
+++ b/subsys/modbus/modbus_serial.c
@@ -560,6 +560,7 @@ int modbus_serial_init(struct modbus_context *ctx,
 	struct modbus_serial_config *cfg = ctx->cfg;
 	const uint32_t if_delay_max = 3500000;
 	const uint32_t numof_bits = 11;
+	int err;
 
 	switch (param.mode) {
 	case MODBUS_MODE_RTU:
@@ -595,7 +596,11 @@ int modbus_serial_init(struct modbus_context *ctx,
 	cfg->uart_buf_ctr = 0;
 	cfg->uart_buf_ptr = &cfg->uart_buf[0];
 
-	uart_irq_callback_user_data_set(cfg->dev, uart_cb_handler, ctx);
+	err = uart_irq_callback_user_data_set(cfg->dev, uart_cb_handler, ctx);
+	if (err != 0) {
+		return err;
+	};
+
 	k_timer_init(&cfg->rtu_timer, rtu_tmr_handler, NULL);
 	k_timer_user_data_set(&cfg->rtu_timer, ctx);
 
diff --git a/subsys/modbus/modbus_server.c b/subsys/modbus/modbus_server.c
index 30001144ab3..9b4035f9bae 100644
--- a/subsys/modbus/modbus_server.c
+++ b/subsys/modbus/modbus_server.c
@@ -309,7 +309,7 @@ static bool mbs_fc03_hreg_read(struct modbus_context *ctx)
 	const uint16_t regs_limit = 125;
 	const uint8_t request_len = 4;
 	uint8_t *presp;
-	uint16_t err;
+	uint16_t err = 0;
 	uint16_t reg_addr;
 	uint16_t reg_qty;
 	uint16_t num_bytes;
@@ -421,7 +421,7 @@ static bool mbs_fc04_inreg_read(struct modbus_context *ctx)
 	const uint16_t regs_limit = 125;
 	const uint8_t request_len = 4;
 	uint8_t *presp;
-	int err;
+	int err = 0;
 	uint16_t reg_addr;
 	uint16_t reg_qty;
 	uint16_t num_bytes;
diff --git a/subsys/net/ip/6lo.c b/subsys/net/ip/6lo.c
index 5d951fb3f8f..6a0dfa66758 100644
--- a/subsys/net/ip/6lo.c
+++ b/subsys/net/ip/6lo.c
@@ -365,8 +365,6 @@ static uint8_t *compress_nh(struct net_ipv6_hdr *ipv6, uint8_t *inline_ptr,
 static uint8_t *compress_sa(struct net_ipv6_hdr *ipv6, struct net_pkt *pkt,
 			 uint8_t *inline_ptr, uint16_t *iphc)
 {
-	NET_ASSERT(net_pkt_lladdr_src(pkt)->addr);
-
 	/* Address is fully elided */
 	if (net_ipv6_addr_based_on_ll((struct in6_addr *)ipv6->src,
 				      net_pkt_lladdr_src(pkt))) {
@@ -411,8 +409,6 @@ static uint8_t *compress_sa_ctx(struct net_ipv6_hdr *ipv6, uint8_t *inline_ptr,
 			     struct net_pkt *pkt, uint16_t *iphc,
 			     struct net_6lo_context *src)
 {
-	NET_ASSERT(net_pkt_lladdr_src(pkt)->addr);
-
 	NET_DBG("SAC_1 src address context based");
 	*iphc |= NET_6LO_IPHC_SAC_1;
 
@@ -510,8 +506,6 @@ static uint8_t *compress_da_mcast(struct net_ipv6_hdr *ipv6, uint8_t *inline_ptr
 static uint8_t *compress_da(struct net_ipv6_hdr *ipv6, struct net_pkt *pkt,
 			 uint8_t *inline_ptr, uint16_t *iphc)
 {
-	NET_ASSERT(net_pkt_lladdr_dst(pkt)->addr);
-
 	/* Address is fully elided */
 	if (net_ipv6_addr_based_on_ll((struct in6_addr *)ipv6->dst,
 				      net_pkt_lladdr_dst(pkt))) {
diff --git a/subsys/net/ip/Kconfig b/subsys/net/ip/Kconfig
index e3b499ecf9c..e822e881881 100644
--- a/subsys/net/ip/Kconfig
+++ b/subsys/net/ip/Kconfig
@@ -268,6 +268,11 @@ config NET_SHELL_PKT_ALLOC_SUPPORTED
 	default y
 	depends on NET_SHELL_SHOW_DISABLED_COMMANDS || NET_DEBUG_NET_PKT_ALLOC
 
+config NET_SHELL_PKT_FILTER_SUPPORTED
+	bool "Network packet filter related configuration"
+	default y
+	depends on NET_SHELL_SHOW_DISABLED_COMMANDS || NET_PKT_FILTER
+
 config NET_SHELL_PMTU_SUPPORTED
 	bool "PMTU config"
 	default y
@@ -401,12 +406,32 @@ config NET_TC_RX_COUNT
 	  enable at least 1 RX thread.
 
 config NET_TC_SKIP_FOR_HIGH_PRIO
+	bool "Push high priority packets directly to network driver [DEPRECATED]"
+	select DEPRECATED
+	help
+	  Deprecated, use NET_TC_TX_SKIP_FOR_HIGH_PRIO instead.
+
+config NET_TC_TX_SKIP_FOR_HIGH_PRIO
 	bool "Push high priority packets directly to network driver"
+	default NET_TC_SKIP_FOR_HIGH_PRIO
 	help
 	  If this is set, then high priority (>= NET_PRIORITY_CA) net_pkt will
 	  be pushed directly to network driver and will skip the traffic class
 	  queues. This is currently not enabled by default.
 
+config NET_TC_RX_SKIP_FOR_HIGH_PRIO
+	bool "Push high priority packets directly to the application"
+	help
+	  If this is set, then high priority (>= NET_PRIORITY_CA) net_pkt will
+	  be pushed directly to the application and will skip the traffic class
+	  queues. If you select this option, then it means that high priority
+	  network traffic is pushed from the driver to the application thread
+	  without any intermediate RX queue. If the network device driver is
+	  running in IRQ context, it will handle the packet all the way to the
+	  application. This might cause other incoming packets to be lost if
+	  the RX processing takes long time.
+	  This is currently not enabled by default.
+
 choice NET_TC_THREAD_TYPE
 	prompt "How the network RX/TX threads should work"
 	help
@@ -642,6 +667,12 @@ config NET_MAX_CONN
 	  The value depends on your network needs. The value
 	  should include both UDP and TCP connections.
 
+config NET_CONN_PACKET_CLONE_TIMEOUT
+	int "Timeout value in milliseconds for cloning a packet"
+	default 100
+	help
+	  Maximum wait time when cloning a packet for a network connection.
+
 config NET_MAX_CONTEXTS
 	int "Number of network contexts to allocate"
 	default 6
@@ -930,6 +961,9 @@ config NET_DEFAULT_IF_PPP
 	bool "PPP interface"
 	depends on NET_L2_PPP
 
+config NET_DEFAULT_IF_OFFLOADED_NETDEV
+	bool "Offloaded network device"
+
 config NET_DEFAULT_IF_WIFI
 	bool "WiFi interface"
 	depends on NET_L2_ETHERNET
diff --git a/subsys/net/ip/Kconfig.ipv4 b/subsys/net/ip/Kconfig.ipv4
index 023a184e0fd..842a02edd7b 100644
--- a/subsys/net/ip/Kconfig.ipv4
+++ b/subsys/net/ip/Kconfig.ipv4
@@ -13,7 +13,7 @@ if NET_IPV4
 
 config NET_IF_MAX_IPV4_COUNT
 	int "Max number of IPv4 network interfaces in the system"
-	default NET_VLAN_COUNT if NET_VLAN
+	default NET_VLAN_COUNT if NET_VLAN && NET_VLAN_COUNT > 0
 	default 2 if NET_LOOPBACK
 	default 1
 	help
@@ -42,6 +42,14 @@ config NET_IPV4_DEFAULT_NETMASK
 
 if NET_NATIVE_IPV4
 
+config NET_IPV4_MTU
+	int "Initial IPv4 MTU value"
+	default 576
+	range 576 1500
+	help
+	  The value should normally be 576 which is the minimum IPv4 packet
+	  size that implementations need to support without fragmentation.
+
 config NET_INITIAL_TTL
 	int "Initial IPv4 time to live value for unicast packets"
 	default 64
@@ -65,6 +73,13 @@ config NET_INITIAL_MCAST_TTL
 	  don't leave the local network unless the application explicitly
 	  requests it.
 
+config NET_INITIAL_IPV4_MCAST_LOOP
+	bool "Control whether the socket sees multicast packets sent by itself"
+	default y
+	help
+	Assign initial value to IPV4_MULTICAST_LOOP in socket options,
+	if not set by the user using setsockopt().
+
 config NET_IF_MCAST_IPV4_SOURCE_COUNT
 	int "Max number of IPv4 sources per mcast address to be included or excluded"
 	default 1
diff --git a/subsys/net/ip/Kconfig.ipv6 b/subsys/net/ip/Kconfig.ipv6
index 653fef97fdf..017061b974a 100644
--- a/subsys/net/ip/Kconfig.ipv6
+++ b/subsys/net/ip/Kconfig.ipv6
@@ -1,6 +1,7 @@
 # IPv6 Options
 
 # Copyright (c) 2016 Intel Corporation.
+# Copyright (c) 2025 Aerlync Labs Inc.
 # SPDX-License-Identifier: Apache-2.0
 
 menuconfig NET_IPV6
@@ -14,7 +15,7 @@ if NET_IPV6
 
 config NET_IF_MAX_IPV6_COUNT
 	int "Max number of IPv6 network interfaces in the system"
-	default NET_VLAN_COUNT if NET_VLAN
+	default NET_VLAN_COUNT if NET_VLAN && NET_VLAN_COUNT > 0
 	default 2 if NET_LOOPBACK
 	default 1
 	help
@@ -81,6 +82,13 @@ config NET_INITIAL_MCAST_HOP_LIMIT
 	  don't leave the local network unless the application explicitly
 	  requests it.
 
+config NET_INITIAL_IPV6_MCAST_LOOP
+	bool "Control whether the socket sees multicast packets sent by itself"
+	default y
+	help
+	  Assign initial value to IPV6_MULTICAST_LOOP in socket options,
+	  if not set by the user using setsockopt().
+
 config NET_IPV6_MAX_NEIGHBORS
 	int "How many IPv6 neighbors are supported"
 	default 8
diff --git a/subsys/net/ip/Kconfig.stats b/subsys/net/ip/Kconfig.stats
index 48d4246c49e..e7ed8dfaa28 100644
--- a/subsys/net/ip/Kconfig.stats
+++ b/subsys/net/ip/Kconfig.stats
@@ -114,6 +114,13 @@ config NET_STATISTICS_DNS
 	help
 	  Keep track of DNS related statistics
 
+config NET_STATISTICS_PKT_FILTER
+	bool "Network packet filter statistics"
+	depends on NET_PKT_FILTER
+	default y
+	help
+	  Keep track of network packet filter related statistics
+
 config NET_STATISTICS_PPP
 	bool "Point-to-point (PPP) statistics"
 	depends on NET_L2_PPP
@@ -162,4 +169,11 @@ config NET_STATISTICS_VIA_PROMETHEUS
 	  Enable this option to expose the network statistics
 	  to Prometheus monitoring system.
 
+config NET_STATISTICS_VPN
+	bool "VPN statistics"
+	depends on NET_VPN
+	default y
+	help
+	  Keep track of VPN related statistics
+
 endif # NET_STATISTICS
diff --git a/subsys/net/ip/canbus_socket.c b/subsys/net/ip/canbus_socket.c
index e9f99eddaf8..5a2debc2e09 100644
--- a/subsys/net/ip/canbus_socket.c
+++ b/subsys/net/ip/canbus_socket.c
@@ -23,7 +23,7 @@ enum net_verdict net_canbus_socket_input(struct net_pkt *pkt)
 	__ASSERT_NO_MSG(net_pkt_family(pkt) == AF_CAN);
 
 	if (net_if_l2(net_pkt_iface(pkt)) == &NET_L2_GET_NAME(CANBUS_RAW)) {
-		return net_conn_input(pkt, NULL, CAN_RAW, NULL);
+		return net_conn_can_input(pkt, CAN_RAW);
 	}
 
 	return NET_CONTINUE;
diff --git a/subsys/net/ip/connection.c b/subsys/net/ip/connection.c
index d105da2e943..caab187e3f6 100644
--- a/subsys/net/ip/connection.c
+++ b/subsys/net/ip/connection.c
@@ -33,9 +33,6 @@ LOG_MODULE_REGISTER(net_conn, CONFIG_NET_CONN_LOG_LEVEL);
 #include "connection.h"
 #include "net_stats.h"
 
-/** How long to wait for when cloning multicast packet */
-#define CLONE_TIMEOUT K_MSEC(100)
-
 /** Is this connection used or not */
 #define NET_CONN_IN_USE			BIT(0)
 
@@ -325,7 +322,7 @@ static int net_conn_change_remote(struct net_conn *conn,
 	return 0;
 }
 
-int net_conn_register(uint16_t proto, uint8_t family,
+int net_conn_register(uint16_t proto, enum net_sock_type type, uint8_t family,
 		      const struct sockaddr *remote_addr,
 		      const struct sockaddr *local_addr,
 		      uint16_t remote_port,
@@ -408,6 +405,7 @@ int net_conn_register(uint16_t proto, uint8_t family,
 
 	conn->flags = flags;
 	conn->proto = proto;
+	conn->type = type;
 	conn->family = family;
 	conn->context = context;
 
@@ -578,61 +576,282 @@ static bool conn_are_endpoints_valid(struct net_pkt *pkt, uint8_t family,
 	return !are_invalid_endpoints;
 }
 
-static enum net_verdict conn_raw_socket(struct net_pkt *pkt,
-					struct net_conn *conn, uint8_t proto)
+/* Is the candidate connection matching the packet's interface? */
+static bool is_iface_matching(struct net_conn *conn, struct net_pkt *pkt)
 {
-	enum net_sock_type type = net_context_get_type(conn->context);
+	if (conn->context == NULL) {
+		return true;
+	}
 
-	if (proto == ETH_P_ALL) {
-		if ((type == SOCK_DGRAM && !net_pkt_is_l2_processed(pkt)) ||
-		    (type == SOCK_RAW && net_pkt_is_l2_processed(pkt))) {
-			return NET_CONTINUE;
-		}
+	if (!net_context_is_bound_to_iface(conn->context)) {
+		return true;
 	}
 
-	/*
-	 * After l2 processed only deliver protocol matched pkt,
-	 * unless the connection protocol is all packets
-	 */
-	if (type == SOCK_DGRAM && net_pkt_is_l2_processed(pkt) &&
-	    conn->proto != ETH_P_ALL &&
-	    conn->proto != net_pkt_ll_proto_type(pkt)) {
-		return NET_CONTINUE;
+	return (net_pkt_iface(pkt) == net_context_get_iface(conn->context));
+}
+
+#if defined(CONFIG_NET_SOCKETS_PACKET) || defined(CONFIG_NET_SOCKETS_INET_RAW)
+static void conn_raw_socket_deliver(struct net_pkt *pkt, struct net_conn *conn,
+				    bool is_ip)
+{
+	struct net_pkt *raw_pkt;
+	struct net_pkt_cursor cur;
+
+	net_pkt_cursor_backup(pkt, &cur);
+	net_pkt_cursor_init(pkt);
+
+	NET_DBG("[%p] raw%s match found cb %p ud %p", conn, is_ip ? " IP" : "",
+		conn->cb, conn->user_data);
+
+	raw_pkt = net_pkt_clone(pkt, K_MSEC(CONFIG_NET_CONN_PACKET_CLONE_TIMEOUT));
+	if (raw_pkt == NULL) {
+		NET_WARN("pkt cloning failed, pkt %p not delivered", pkt);
+		goto out;
 	}
 
-	if (!(conn->flags & NET_CONN_LOCAL_ADDR_SET)) {
-		return NET_CONTINUE;
+	if (conn->cb(conn, raw_pkt, NULL, NULL, conn->user_data) == NET_DROP) {
+		net_pkt_unref(raw_pkt);
 	}
 
-	struct net_if *pkt_iface = net_pkt_iface(pkt);
+out:
+	net_pkt_cursor_restore(pkt, &cur);
+}
+#endif /* defined(CONFIG_NET_SOCKETS_PACKET) || defined(CONFIG_NET_SOCKETS_INET_RAW) */
+
+#if defined(CONFIG_NET_SOCKETS_PACKET)
+enum net_verdict net_conn_packet_input(struct net_pkt *pkt, uint16_t proto)
+{
+	bool raw_sock_found = false;
+	bool raw_pkt_continue = false;
 	struct sockaddr_ll *local;
-	struct net_pkt *raw_pkt;
+	struct net_conn *conn;
+
+	/* Only accept input with AF_PACKET family. */
+	if (net_pkt_family(pkt) != AF_PACKET) {
+		return NET_CONTINUE;
+	}
+
+	NET_DBG("Check proto 0x%04x listener for pkt %p family %d",
+		proto, pkt, net_pkt_family(pkt));
+
+	k_mutex_lock(&conn_lock, K_FOREVER);
 
-	local = (struct sockaddr_ll *)&conn->local_addr;
+	SYS_SLIST_FOR_EACH_CONTAINER(&conn_used, conn, node) {
+		if (!is_iface_matching(conn, pkt)) {
+			continue; /* wrong interface */
+		}
 
-	if (local->sll_ifindex != net_if_get_by_iface(pkt_iface)) {
+		/* If there are other listening connections than
+		 * AF_PACKET, the packet shall be also passed back to
+		 * net_conn_input() in upper layer processing in order to
+		 * re-check if there is any listening socket interested
+		 * in this packet.
+		 */
+		if (conn->family != AF_PACKET) {
+			raw_pkt_continue = true;
+			continue; /* wrong family */
+		}
+
+		if (conn->type == SOCK_DGRAM && !net_pkt_is_l2_processed(pkt)) {
+			/* If DGRAM packet sockets are present, we shall continue
+			 * with this packet regardless the result.
+			 */
+			raw_pkt_continue = true;
+			continue; /* L2 not processed yet */
+		}
+
+		if (conn->type == SOCK_RAW && net_pkt_is_l2_processed(pkt)) {
+			continue; /* L2 already processed */
+		}
+
+		if (conn->proto == 0) {
+			continue; /* Local proto 0 doesn't forward any packets */
+		}
+
+		if (conn->proto != proto) {
+			/* Allow proto mismatch if socket was created with ETH_P_ALL, or it's raw
+			 * packet socket input (proto ETH_P_ALL).
+			 */
+			if (conn->proto != ETH_P_ALL && proto != ETH_P_ALL) {
+				continue; /* wrong protocol */
+			}
+		}
+
+		/* Apply protocol-specific matching criteria... */
+
+		if (!(conn->flags & NET_CONN_LOCAL_ADDR_SET)) {
+			continue;
+		}
+
+		local = (struct sockaddr_ll *)&conn->local_addr;
+		if (local->sll_ifindex != net_if_get_by_iface(net_pkt_iface(pkt))) {
+			continue;
+		}
+
+		conn_raw_socket_deliver(pkt, conn, false);
+
+		raw_sock_found = true;
+	}
+
+	k_mutex_unlock(&conn_lock);
+
+	if (!raw_pkt_continue && raw_sock_found) {
+		/* As one or more raw socket packets have already been delivered
+		 * in the loop above, report NET_OK.
+		 */
+		net_pkt_unref(pkt);
+		return NET_OK;
+	}
+
+	/* When there is open connection different than AF_PACKET this
+	 * packet shall be also handled in the upper net stack layers.
+	 */
+	return NET_CONTINUE;
+}
+#else
+enum net_verdict net_conn_packet_input(struct net_pkt *pkt, uint16_t proto)
+{
+	ARG_UNUSED(pkt);
+	ARG_UNUSED(proto);
+
+	return NET_CONTINUE;
+}
+#endif /* defined(CONFIG_NET_SOCKETS_PACKET) */
+
+#if defined(CONFIG_NET_SOCKETS_INET_RAW)
+enum net_verdict net_conn_raw_ip_input(struct net_pkt *pkt,
+				       union net_ip_header *ip_hdr,
+				       uint8_t proto)
+{
+	uint8_t pkt_family = net_pkt_family(pkt);
+	struct net_conn *conn;
+
+	if (pkt_family != AF_INET && pkt_family != AF_INET6) {
 		return NET_CONTINUE;
 	}
 
-	NET_DBG("[%p] raw match found cb %p ud %p", conn, conn->cb,
-		conn->user_data);
+	NET_DBG("Check %s listener for pkt %p family %d",
+		net_proto2str(net_pkt_family(pkt), proto), pkt,
+		net_pkt_family(pkt));
+
+	k_mutex_lock(&conn_lock, K_FOREVER);
+
+	SYS_SLIST_FOR_EACH_CONTAINER(&conn_used, conn, node) {
+		if (!is_iface_matching(conn, pkt)) {
+			continue; /* wrong interface */
+		}
+
+		if (conn->family != pkt_family) {
+			continue; /* wrong family */
+		}
+
+		if (conn->type != SOCK_RAW) {
+			continue; /* wrong type */
+		}
+
+		if (conn->proto != proto && conn->proto != IPPROTO_IP) {
+			continue; /* wrong protocol */
+		}
+
+		/* Apply protocol-specific matching criteria... */
 
-	raw_pkt = net_pkt_clone(pkt, CLONE_TIMEOUT);
-	if (!raw_pkt) {
-		net_stats_update_per_proto_drop(pkt_iface, proto);
-		NET_WARN("pkt cloning failed, pkt %p dropped", pkt);
+		if ((conn->flags & NET_CONN_LOCAL_ADDR_SET) &&
+		    !conn_addr_cmp(pkt, ip_hdr, &conn->local_addr, false)) {
+			continue; /* wrong local address */
+		}
+
+		conn_raw_socket_deliver(pkt, conn, true);
+	}
+
+	k_mutex_unlock(&conn_lock);
+
+	/* Raw IP packets are passed further in the stack regardless. */
+	return NET_CONTINUE;
+}
+#else
+enum net_verdict net_conn_raw_ip_input(struct net_pkt *pkt,
+				       union net_ip_header *ip_hdr,
+				       uint8_t proto)
+{
+	ARG_UNUSED(pkt);
+	ARG_UNUSED(ip_hdr);
+	ARG_UNUSED(proto);
+
+	return NET_CONTINUE;
+}
+#endif /* defined(CONFIG_NET_SOCKETS_INET_RAW) */
+
+#if defined(CONFIG_NET_SOCKETS_CAN)
+enum net_verdict net_conn_can_input(struct net_pkt *pkt, uint8_t proto)
+{
+	struct net_conn *best_match = NULL;
+	struct net_conn *conn;
+	net_conn_cb_t cb = NULL;
+	void *user_data = NULL;
+
+	/* Only accept input with AF_CAN family and CAN_RAW protocol. */
+	if (net_pkt_family(pkt) != AF_CAN || proto != CAN_RAW) {
 		return NET_DROP;
 	}
 
-	if (conn->cb(conn, raw_pkt, NULL, NULL, conn->user_data) == NET_DROP) {
-		net_stats_update_per_proto_drop(pkt_iface, proto);
-		net_pkt_unref(raw_pkt);
-	} else {
-		net_stats_update_per_proto_recv(pkt_iface, proto);
+	NET_DBG("Check %s listener for pkt %p family %d",
+		net_proto2str(net_pkt_family(pkt), proto), pkt,
+		net_pkt_family(pkt));
+
+	k_mutex_lock(&conn_lock, K_FOREVER);
+
+	SYS_SLIST_FOR_EACH_CONTAINER(&conn_used, conn, node) {
+		if (!is_iface_matching(conn, pkt)) {
+			continue; /* wrong interface */
+		}
+
+		if (conn->family != AF_CAN) {
+			continue; /* wrong family */
+		}
+
+		if (conn->proto != CAN_RAW) {
+			continue; /* wrong protocol */
+		}
+
+		best_match = conn;
+	}
+
+	if (best_match != NULL) {
+		cb = best_match->cb;
+		user_data = best_match->user_data;
+	}
+
+	k_mutex_unlock(&conn_lock);
+
+	if (cb != NULL) {
+		NET_DBG("[%p] match found cb %p ud %p rank 0x%02x", best_match, cb,
+			user_data, NET_CONN_RANK(best_match->flags));
+
+		if (cb(best_match, pkt, NULL, NULL, user_data) == NET_DROP) {
+			goto drop;
+		}
+
+		net_stats_update_per_proto_recv(net_pkt_iface(pkt), proto);
+
+		return NET_OK;
 	}
 
-	return NET_OK;
+	NET_DBG("No match found.");
+
+drop:
+	net_stats_update_per_proto_drop(net_pkt_iface(pkt), proto);
+
+	return NET_DROP;
 }
+#else
+enum net_verdict net_conn_can_input(struct net_pkt *pkt, uint8_t proto)
+{
+	ARG_UNUSED(pkt);
+	ARG_UNUSED(proto);
+
+	return NET_DROP;
+}
+#endif /* defined(CONFIG_NET_SOCKETS_CAN) */
 
 enum net_verdict net_conn_input(struct net_pkt *pkt,
 				union net_ip_header *ip_hdr,
@@ -645,10 +864,11 @@ enum net_verdict net_conn_input(struct net_pkt *pkt,
 
 	if (!net_pkt_filter_local_in_recv_ok(pkt)) {
 		/* drop the packet */
+		net_stats_update_filter_rx_local_drop(net_pkt_iface(pkt));
 		return NET_DROP;
 	}
 
-	if (IS_ENABLED(CONFIG_NET_IP) && (pkt_family == AF_INET || pkt_family == AF_INET6)) {
+	if (pkt_family == AF_INET || pkt_family == AF_INET6) {
 		if (IS_ENABLED(CONFIG_NET_UDP) && proto == IPPROTO_UDP) {
 			src_port = proto_hdr->udp->src_port;
 			dst_port = proto_hdr->udp->dst_port;
@@ -659,18 +879,11 @@ enum net_verdict net_conn_input(struct net_pkt *pkt,
 			src_port = proto_hdr->tcp->src_port;
 			dst_port = proto_hdr->tcp->dst_port;
 		}
-		if (!conn_are_endpoints_valid(pkt, pkt_family, ip_hdr, src_port, dst_port)) {
+		if (!conn_are_endpoints_valid(pkt, pkt_family, ip_hdr,
+					      src_port, dst_port)) {
 			NET_DBG("Dropping invalid src/dst end-points packet");
 			return NET_DROP;
 		}
-	} else if (IS_ENABLED(CONFIG_NET_SOCKETS_PACKET) && pkt_family == AF_PACKET) {
-		if (proto != ETH_P_ALL && proto != IPPROTO_RAW) {
-			return NET_DROP;
-		}
-	} else if (IS_ENABLED(CONFIG_NET_SOCKETS_CAN) && pkt_family == AF_CAN) {
-		if (proto != CAN_RAW) {
-			return NET_DROP;
-		}
 	} else {
 		NET_DBG("No suitable protocol handler configured");
 		return NET_DROP;
@@ -680,62 +893,42 @@ enum net_verdict net_conn_input(struct net_pkt *pkt,
 		" family %d", net_proto2str(net_pkt_family(pkt), proto), pkt,
 		ntohs(src_port), ntohs(dst_port), net_pkt_family(pkt));
 
-
 	struct net_conn *best_match = NULL;
 	int16_t best_rank = -1;
 	bool is_mcast_pkt = false;
 	bool mcast_pkt_delivered = false;
 	bool is_bcast_pkt = false;
-	bool raw_pkt_delivered = false;
-	bool raw_pkt_continue = false;
 	struct net_conn *conn;
 	net_conn_cb_t cb = NULL;
 	void *user_data = NULL;
 
-	if (IS_ENABLED(CONFIG_NET_IP)) {
-		/* If we receive a packet with multicast destination address, we might
-		 * need to deliver the packet to multiple recipients.
-		 */
-		if (IS_ENABLED(CONFIG_NET_IPV4) && pkt_family == AF_INET) {
-			if (net_ipv4_is_addr_mcast((struct in_addr *)ip_hdr->ipv4->dst)) {
-				is_mcast_pkt = true;
-			} else if (net_if_ipv4_is_addr_bcast(pkt_iface,
-							     (struct in_addr *)ip_hdr->ipv4->dst)) {
-				is_bcast_pkt = true;
-			}
-		} else if (IS_ENABLED(CONFIG_NET_IPV6) && pkt_family == AF_INET6) {
-			is_mcast_pkt = net_ipv6_is_addr_mcast((struct in6_addr *)ip_hdr->ipv6->dst);
+	/* If we receive a packet with multicast destination address, we might
+	 * need to deliver the packet to multiple recipients.
+	 */
+	if (IS_ENABLED(CONFIG_NET_IPV4) && pkt_family == AF_INET) {
+		if (net_ipv4_is_addr_mcast((struct in_addr *)ip_hdr->ipv4->dst)) {
+			is_mcast_pkt = true;
+		} else if (net_if_ipv4_is_addr_bcast(pkt_iface,
+						     (struct in_addr *)ip_hdr->ipv4->dst)) {
+			is_bcast_pkt = true;
 		}
+	} else if (IS_ENABLED(CONFIG_NET_IPV6) && pkt_family == AF_INET6) {
+		is_mcast_pkt = net_ipv6_is_addr_mcast((struct in6_addr *)ip_hdr->ipv6->dst);
 	}
 
 	k_mutex_lock(&conn_lock, K_FOREVER);
 
 	SYS_SLIST_FOR_EACH_CONTAINER(&conn_used, conn, node) {
 		/* Is the candidate connection matching the packet's interface? */
-		if (conn->context != NULL &&
-		    net_context_is_bound_to_iface(conn->context) &&
-		    net_pkt_iface(pkt) != net_context_get_iface(conn->context)) {
+		if (!is_iface_matching(conn, pkt)) {
 			continue; /* wrong interface */
 		}
 
 		/* Is the candidate connection matching the packet's protocol family? */
-		if (conn->family != AF_UNSPEC &&
-		    conn->family != pkt_family) {
-			if (IS_ENABLED(CONFIG_NET_SOCKETS_PACKET)) {
-				/* If there are other listening connections than
-				 * AF_PACKET, the packet shall be also passed back to
-				 * net_conn_input() in upper layer processing in order to
-				 * re-check if there is any listening socket interested
-				 * in this packet.
-				 */
-				if (conn->family != AF_PACKET) {
-					raw_pkt_continue = true;
-				}
-			}
-
+		if (conn->family != AF_UNSPEC && conn->family != pkt_family) {
 			if (IS_ENABLED(CONFIG_NET_IPV4_MAPPING_TO_IPV6)) {
 				if (!(conn->family == AF_INET6 && pkt_family == AF_INET &&
-				      !conn->v6only)) {
+				      !conn->v6only && conn->type != SOCK_RAW)) {
 					continue;
 				}
 			} else {
@@ -747,54 +940,15 @@ enum net_verdict net_conn_input(struct net_pkt *pkt,
 
 		/* Is the candidate connection matching the packet's protocol within the family? */
 		if (conn->proto != proto) {
-			/* For packet socket data, the proto is set to ETH_P_ALL
-			 * or IPPROTO_RAW but the listener might have a specific
-			 * protocol set. This is ok and let the packet pass this
-			 * check in this case.
-			 */
-			if (IS_ENABLED(CONFIG_NET_SOCKETS_PACKET) && pkt_family == AF_PACKET) {
-				if (proto != ETH_P_ALL && proto != IPPROTO_RAW) {
-					continue; /* wrong protocol */
-				}
-			} else {
-				continue; /* wrong protocol */
-			}
+			continue; /* wrong protocol */
 		}
 
 		/* Apply protocol-specific matching criteria... */
 		uint8_t conn_family = conn->family;
 
-		if (IS_ENABLED(CONFIG_NET_SOCKETS_PACKET) && conn_family == AF_PACKET) {
-			/* This code shall be only executed when one enters
-			 * the net_conn_input() from net_packet_socket() which
-			 * targets AF_PACKET sockets.
-			 *
-			 * All AF_PACKET connections will receive the packet if
-			 * their socket type and - in case of IPPROTO - protocol
-			 * also matches.
-			 */
-			if (proto == ETH_P_ALL) {
-				/* We shall continue with ETH_P_ALL to IPPROTO_RAW: */
-				raw_pkt_continue = true;
-			}
-
-			/* With IPPROTO_RAW deliver only if protocol match: */
-			if ((proto == ETH_P_ALL && conn->proto != IPPROTO_RAW) ||
-			    conn->proto == proto) {
-				enum net_verdict ret = conn_raw_socket(pkt, conn, proto);
-
-				if (ret == NET_DROP) {
-					k_mutex_unlock(&conn_lock);
-					goto drop;
-				} else if (ret == NET_OK) {
-					raw_pkt_delivered = true;
-				}
-
-				continue; /* packet was consumed */
-			}
-		} else if ((IS_ENABLED(CONFIG_NET_UDP) || IS_ENABLED(CONFIG_NET_TCP)) &&
-			   (conn_family == AF_INET || conn_family == AF_INET6 ||
-			    conn_family == AF_UNSPEC)) {
+		if ((IS_ENABLED(CONFIG_NET_UDP) || IS_ENABLED(CONFIG_NET_TCP)) &&
+		    (conn_family == AF_INET || conn_family == AF_INET6 ||
+		     conn_family == AF_UNSPEC)) {
 			/* Is the candidate connection matching the packet's TCP/UDP
 			 * address and port?
 			 */
@@ -857,7 +1011,8 @@ enum net_verdict net_conn_input(struct net_pkt *pkt,
 				NET_DBG("[%p] mcast match found cb %p ud %p", conn, conn->cb,
 					conn->user_data);
 
-				mcast_pkt = net_pkt_clone(pkt, CLONE_TIMEOUT);
+				mcast_pkt = net_pkt_clone(
+					pkt, K_MSEC(CONFIG_NET_CONN_PACKET_CLONE_TIMEOUT));
 				if (!mcast_pkt) {
 					k_mutex_unlock(&conn_lock);
 					goto drop;
@@ -873,37 +1028,17 @@ enum net_verdict net_conn_input(struct net_pkt *pkt,
 
 				mcast_pkt_delivered = true;
 			}
-		} else if (IS_ENABLED(CONFIG_NET_SOCKETS_CAN) && conn_family == AF_CAN) {
-			best_match = conn;
 		}
 	} /* loop end */
 
-	if (best_match) {
+	if (best_match != NULL) {
 		cb = best_match->cb;
 		user_data = best_match->user_data;
 	}
 
 	k_mutex_unlock(&conn_lock);
 
-	if (IS_ENABLED(CONFIG_NET_SOCKETS_PACKET) && pkt_family == AF_PACKET) {
-		if (raw_pkt_continue) {
-			/* When there is open connection different than
-			 * AF_PACKET this packet shall be also handled in
-			 * the upper net stack layers.
-			 */
-			return NET_CONTINUE;
-		}
-		if (raw_pkt_delivered) {
-			/* As one or more raw socket packets
-			 * have already been delivered in the loop above,
-			 * we shall not call the callback again here.
-			 */
-			net_pkt_unref(pkt);
-			return NET_OK;
-		}
-	}
-
-	if (IS_ENABLED(CONFIG_NET_IP) && is_mcast_pkt && mcast_pkt_delivered) {
+	if (is_mcast_pkt && mcast_pkt_delivered) {
 		/* As one or more multicast packets
 		 * have already been delivered in the loop above,
 		 * we shall not call the callback again here.
@@ -912,7 +1047,7 @@ enum net_verdict net_conn_input(struct net_pkt *pkt,
 		return NET_OK;
 	}
 
-	if (cb) {
+	if (cb != NULL) {
 		NET_DBG("[%p] match found cb %p ud %p rank 0x%02x", best_match, cb,
 			user_data, NET_CONN_RANK(best_match->flags));
 
@@ -928,7 +1063,7 @@ enum net_verdict net_conn_input(struct net_pkt *pkt,
 
 	NET_DBG("No match found.");
 
-	if (IS_ENABLED(CONFIG_NET_IP) && (pkt_family == AF_INET || pkt_family == AF_INET6) &&
+	if ((pkt_family == AF_INET || pkt_family == AF_INET6) &&
 	    !(is_mcast_pkt || is_bcast_pkt)) {
 		if (IS_ENABLED(CONFIG_NET_TCP) && proto == IPPROTO_TCP &&
 		    IS_ENABLED(CONFIG_NET_TCP_REJECT_CONN_WITH_RST)) {
diff --git a/subsys/net/ip/connection.h b/subsys/net/ip/connection.h
index 32280f51cae..ab0afc8101f 100644
--- a/subsys/net/ip/connection.h
+++ b/subsys/net/ip/connection.h
@@ -74,6 +74,9 @@ struct net_conn {
 	/** Connection protocol */
 	uint16_t proto;
 
+	/** Connection type */
+	enum net_sock_type type;
+
 	/** Protocol family */
 	uint8_t family;
 
@@ -90,6 +93,7 @@ struct net_conn {
  *
  * @param proto Protocol for the connection (depends on the protocol
  *              family, e.g. UDP/TCP in the case of AF_INET/AF_INET6)
+ * @param type Connection type (SOCK_STREAM/DGRAM/RAW)
  * @param family Protocol family (AF_*)
  * @param remote_addr Remote address of the connection end point.
  * @param local_addr Local address of the connection end point.
@@ -103,7 +107,7 @@ struct net_conn {
  * @return Return 0 if the registration succeed, <0 otherwise.
  */
 #if defined(CONFIG_NET_NATIVE)
-int net_conn_register(uint16_t proto, uint8_t family,
+int net_conn_register(uint16_t proto, enum net_sock_type type, uint8_t family,
 		      const struct sockaddr *remote_addr,
 		      const struct sockaddr *local_addr,
 		      uint16_t remote_port,
@@ -113,7 +117,8 @@ int net_conn_register(uint16_t proto, uint8_t family,
 		      void *user_data,
 		      struct net_conn_handle **handle);
 #else
-static inline int net_conn_register(uint16_t proto, uint8_t family,
+static inline int net_conn_register(uint16_t proto, enum net_sock_type type,
+				    uint8_t family,
 				    const struct sockaddr *remote_addr,
 				    const struct sockaddr *local_addr,
 				    uint16_t remote_port,
@@ -175,10 +180,50 @@ int net_conn_update(struct net_conn_handle *handle,
 		    uint16_t remote_port);
 
 /**
- * @brief Called by net_core.c when a network packet is received.
+ * @brief Called by net_core.c when a network packet is received
+ *        (before L3 processing).
+ *
+ * @param pkt Network packet holding received data
+ * @param proto LL protocol for the connection
+ *
+ * @return NET_OK if the packet was consumed, NET_CONTINUE if the packet should
+ * be processed further in the stack.
+ */
+enum net_verdict net_conn_packet_input(struct net_pkt *pkt, uint16_t proto);
+
+/**
+ * @brief Called by net_core.c when an IP packet is received
+ *        (before L4 processing).
+ *
+ * @param pkt Network packet holding received data
+ * @param ip_hdr A pointer to the IP header within the packet
+ * @param proto L4 protocol for the connection
+ *
+ * @return NET_CONTINUE if the packet should be further processed in the stack.
+ */
+enum net_verdict net_conn_raw_ip_input(struct net_pkt *pkt,
+				       union net_ip_header *ip_hdr,
+				       uint8_t proto);
+
+/**
+ * @brief Called by net_core.c when a CAN packet is received.
+ *
+ * @param pkt Network packet holding received data
+ * @param proto Protocol for the connection
+ *
+ * @return NET_OK if the packet was consumed, NET_DROP if the packet parsing
+ * failed and the packet should be discarded.
+ */
+enum net_verdict net_conn_can_input(struct net_pkt *pkt, uint8_t proto);
+
+/**
+ * @brief Called by net_core.c when a network packet is received (after L4
+ *        processing).
  *
  * @param pkt Network packet holding received data
+ * @param ip_hdr A pointer to the IP header within the packet
  * @param proto Protocol for the connection
+ * @param proto_hdr A pointer to the L4 protocol header within the packet
  *
  * @return NET_OK if the packet was consumed, NET_DROP if
  * the packet parsing failed and the caller should handle
diff --git a/subsys/net/ip/icmp.c b/subsys/net/ip/icmp.c
index e8553726271..12d2f022912 100644
--- a/subsys/net/ip/icmp.c
+++ b/subsys/net/ip/icmp.c
@@ -207,7 +207,7 @@ static int send_icmpv4_echo_request(struct net_icmp_ctx *ctx,
 	ctx->user_data = user_data;
 	ctx->iface = iface;
 
-	if (net_send_data(pkt) >= 0) {
+	if (net_try_send_data(pkt, K_NO_WAIT) >= 0) {
 		net_stats_update_icmp_sent(iface);
 		return 0;
 	}
@@ -330,7 +330,7 @@ static int send_icmpv6_echo_request(struct net_icmp_ctx *ctx,
 	ctx->user_data = user_data;
 	ctx->iface = iface;
 
-	if (net_send_data(pkt) >= 0) {
+	if (net_try_send_data(pkt, K_NO_WAIT) >= 0) {
 		net_stats_update_icmp_sent(iface);
 		return 0;
 	}
diff --git a/subsys/net/ip/icmpv4.c b/subsys/net/ip/icmpv4.c
index cc25e572dd4..ed0784a5c8d 100644
--- a/subsys/net/ip/icmpv4.c
+++ b/subsys/net/ip/icmpv4.c
@@ -493,7 +493,7 @@ static int icmpv4_handle_echo_request(struct net_icmp_ctx *ctx,
 		net_sprint_ipv4_addr(src),
 		net_sprint_ipv4_addr(&ip_hdr->src));
 
-	if (net_send_data(reply) < 0) {
+	if (net_try_send_data(reply, K_NO_WAIT) < 0) {
 		goto drop;
 	}
 
@@ -580,15 +580,16 @@ int net_icmpv4_send_error(struct net_pkt *orig, uint8_t type, uint8_t code)
 	net_pkt_cursor_init(pkt);
 	net_ipv4_finalize(pkt, IPPROTO_ICMP);
 
-	net_pkt_lladdr_dst(pkt)->addr = net_pkt_lladdr_src(orig)->addr;
-	net_pkt_lladdr_dst(pkt)->len = net_pkt_lladdr_src(orig)->len;
+	net_linkaddr_set(net_pkt_lladdr_dst(pkt),
+			 net_pkt_lladdr_src(orig)->addr,
+			 net_pkt_lladdr_src(orig)->len);
 
 	NET_DBG("Sending ICMPv4 Error Message type %d code %d from %s to %s",
 		type, code,
 		net_sprint_ipv4_addr(&ip_hdr->dst),
 		net_sprint_ipv4_addr(&ip_hdr->src));
 
-	if (net_send_data(pkt) >= 0) {
+	if (net_try_send_data(pkt, K_NO_WAIT) >= 0) {
 		net_stats_update_icmp_sent(net_pkt_iface(orig));
 		return 0;
 	}
diff --git a/subsys/net/ip/icmpv6.c b/subsys/net/ip/icmpv6.c
index 048521e1c12..4efdbdcf550 100644
--- a/subsys/net/ip/icmpv6.c
+++ b/subsys/net/ip/icmpv6.c
@@ -145,8 +145,8 @@ static int icmpv6_handle_echo_request(struct net_icmp_ctx *ctx,
 	 * that it is set properly using a value from neighbor cache.
 	 * Same for source as it points to original pkt ll src address.
 	 */
-	net_pkt_lladdr_dst(reply)->addr = NULL;
-	net_pkt_lladdr_src(reply)->addr = NULL;
+	(void)net_linkaddr_clear(net_pkt_lladdr_dst(reply));
+	(void)net_linkaddr_clear(net_pkt_lladdr_src(reply));
 
 	net_pkt_set_ip_dscp(reply, net_pkt_ip_dscp(pkt));
 	net_pkt_set_ip_ecn(reply, net_pkt_ip_ecn(pkt));
@@ -169,7 +169,7 @@ static int icmpv6_handle_echo_request(struct net_icmp_ctx *ctx,
 		net_sprint_ipv6_addr(src),
 		net_sprint_ipv6_addr(&ip_hdr->src));
 
-	if (net_send_data(reply) < 0) {
+	if (net_try_send_data(reply, K_NO_WAIT) < 0) {
 		goto drop;
 	}
 
@@ -264,7 +264,8 @@ int net_icmpv6_send_error(struct net_pkt *orig, uint8_t type, uint8_t code,
 		goto drop;
 	}
 
-	net_pkt_lladdr_dst(pkt)->addr = pkt->buffer->data;
+	memcpy(net_pkt_lladdr_dst(pkt)->addr, pkt->buffer->data,
+	       net_pkt_lladdr_dst(orig)->len);
 
 	ret = net_pkt_write(pkt, net_pkt_lladdr_dst(orig)->addr,
 			    net_pkt_lladdr_dst(orig)->len);
@@ -275,7 +276,8 @@ int net_icmpv6_send_error(struct net_pkt *orig, uint8_t type, uint8_t code,
 
 	net_buf_pull_mem(pkt->buffer, net_pkt_lladdr_dst(orig)->len);
 
-	net_pkt_lladdr_src(pkt)->addr = pkt->buffer->data;
+	memcpy(net_pkt_lladdr_src(pkt)->addr, pkt->buffer->data,
+	       net_pkt_lladdr_src(orig)->len);
 
 	net_buf_pull_mem(pkt->buffer, net_pkt_lladdr_src(orig)->len);
 
@@ -319,7 +321,7 @@ int net_icmpv6_send_error(struct net_pkt *orig, uint8_t type, uint8_t code,
 		net_sprint_ipv6_addr(src),
 		net_sprint_ipv6_addr(&ip_hdr->src));
 
-	if (net_send_data(pkt) >= 0) {
+	if (net_try_send_data(pkt, K_NO_WAIT) >= 0) {
 		net_stats_update_icmp_sent(net_pkt_iface(pkt));
 		return 0;
 	}
diff --git a/subsys/net/ip/ipv4.c b/subsys/net/ip/ipv4.c
index 7178ba1d1db..d59d0e7b297 100644
--- a/subsys/net/ip/ipv4.c
+++ b/subsys/net/ip/ipv4.c
@@ -17,6 +17,7 @@ LOG_MODULE_REGISTER(net_ipv4, CONFIG_NET_IPV4_LOG_LEVEL);
 #include <zephyr/net/net_stats.h>
 #include <zephyr/net/net_context.h>
 #include <zephyr/net/virtual.h>
+#include <zephyr/net/ethernet.h>
 #include "net_private.h"
 #include "connection.h"
 #include "net_stats.h"
@@ -133,6 +134,7 @@ int net_ipv4_finalize(struct net_pkt *pkt, uint8_t next_header_proto)
 	}
 
 	net_pkt_set_data(pkt, &ipv4_access);
+	net_pkt_set_ll_proto_type(pkt, NET_ETH_PTYPE_IP);
 
 	if (IS_ENABLED(CONFIG_NET_UDP) &&
 	    next_header_proto == IPPROTO_UDP) {
@@ -341,6 +343,7 @@ enum net_verdict net_ipv4_input(struct net_pkt *pkt, bool is_loopback)
 
 	if (!net_pkt_filter_ip_recv_ok(pkt)) {
 		/* drop the packet */
+		net_stats_update_filter_rx_ipv4_drop(net_pkt_iface(pkt));
 		return NET_DROP;
 	}
 
@@ -381,6 +384,14 @@ enum net_verdict net_ipv4_input(struct net_pkt *pkt, bool is_loopback)
 		net_sprint_ipv4_addr(&hdr->src),
 		net_sprint_ipv4_addr(&hdr->dst));
 
+	ip.ipv4 = hdr;
+
+	if (IS_ENABLED(CONFIG_NET_SOCKETS_INET_RAW)) {
+		if (net_conn_raw_ip_input(pkt, &ip, hdr->proto) == NET_DROP) {
+			goto drop;
+		}
+	}
+
 	switch (hdr->proto) {
 	case IPPROTO_ICMP:
 		verdict = net_icmpv4_input(pkt, hdr);
@@ -438,8 +449,6 @@ enum net_verdict net_ipv4_input(struct net_pkt *pkt, bool is_loopback)
 		goto drop;
 	}
 
-	ip.ipv4 = hdr;
-
 	verdict = net_conn_input(pkt, &ip, hdr->proto, &proto_hdr);
 	if (verdict != NET_DROP) {
 		return verdict;
diff --git a/subsys/net/ip/ipv4.h b/subsys/net/ip/ipv4.h
index e70fae3ff1f..120bb0b20b2 100644
--- a/subsys/net/ip/ipv4.h
+++ b/subsys/net/ip/ipv4.h
@@ -25,6 +25,26 @@
 #define NET_IPV4_DSCP_OFFSET 2
 #define NET_IPV4_ECN_MASK 0x03
 
+/* IPv4 DiffServ code points (DSCP) for Assured Forwarding (AF) group.
+ * See https://tools.ietf.org/html/rfc2597
+ *     https://en.wikipedia.org/wiki/Differentiated_services
+ */
+/* Drop probability low */
+#define NET_IPV4_DSCP_AF11 10 /* 001010 */ /* Class 1 */
+#define NET_IPV4_DSCP_AF21 18 /* 010010 */ /* Class 2 */
+#define NET_IPV4_DSCP_AF31 26 /* 011010 */ /* Class 3 */
+#define NET_IPV4_DSCP_AF41 34 /* 100010 */ /* Class 4 */
+/* Drop probability medium */
+#define NET_IPV4_DSCP_AF12 12 /* 001100 */ /* Class 1 */
+#define NET_IPV4_DSCP_AF22 20 /* 010100 */ /* Class 2 */
+#define NET_IPV4_DSCP_AF32 28 /* 011100 */ /* Class 3 */
+#define NET_IPV4_DSCP_AF42 36 /* 100100 */ /* Class 4 */
+/* Drop probability high */
+#define NET_IPV4_DSCP_AF13 14 /* 001110 */ /* Class 1 */
+#define NET_IPV4_DSCP_AF23 22 /* 010110 */ /* Class 2 */
+#define NET_IPV4_DSCP_AF33 30 /* 011110 */ /* Class 3 */
+#define NET_IPV4_DSCP_AF43 38 /* 100110 */ /* Class 4 */
+
 /* IPv4 Options */
 #define NET_IPV4_OPTS_EO   0   /* End of Options */
 #define NET_IPV4_OPTS_NOP  1   /* No operation */
diff --git a/subsys/net/ip/ipv4_acd.c b/subsys/net/ip/ipv4_acd.c
index 3cb1d2c6f95..5fa07a97d6a 100644
--- a/subsys/net/ip/ipv4_acd.c
+++ b/subsys/net/ip/ipv4_acd.c
@@ -74,7 +74,8 @@ static struct net_pkt *ipv4_acd_prepare_arp(struct net_if *iface,
 					    struct in_addr *sender_ip,
 					    struct in_addr *target_ip)
 {
-	struct net_pkt *pkt;
+	struct net_pkt *pkt, *arp;
+	int ret;
 
 	/* We provide AF_UNSPEC to the allocator: this packet does not
 	 * need space for any IPv4 header.
@@ -88,7 +89,13 @@ static struct net_pkt *ipv4_acd_prepare_arp(struct net_if *iface,
 	net_pkt_set_family(pkt, AF_INET);
 	net_pkt_set_ipv4_acd(pkt, true);
 
-	return net_arp_prepare(pkt, target_ip, sender_ip);
+	ret = net_arp_prepare(pkt, target_ip, sender_ip, &arp);
+	if (ret == NET_ARP_PKT_REPLACED) {
+		pkt = arp;
+	} else if (ret < 0)  {
+		pkt = NULL;
+	}
+	return pkt;
 }
 
 static void ipv4_acd_send_probe(struct net_if_addr *ifaddr)
diff --git a/subsys/net/ip/ipv4_fragment.c b/subsys/net/ip/ipv4_fragment.c
index 69fe9522159..720430753a9 100644
--- a/subsys/net/ip/ipv4_fragment.c
+++ b/subsys/net/ip/ipv4_fragment.c
@@ -441,6 +441,8 @@ static int send_ipv4_fragment(struct net_pkt *pkt, uint16_t rand_id, uint16_t fi
 	net_pkt_cursor_backup(pkt, &cur_pkt);
 	net_pkt_cursor_backup(frag_pkt, &cur);
 
+	net_pkt_set_ll_proto_type(frag_pkt, net_pkt_ll_proto_type(pkt));
+
 	/* Copy the original IPv4 headers back to the fragment packet */
 	if (net_pkt_copy(frag_pkt, pkt, net_pkt_ip_hdr_len(pkt))) {
 		goto fail;
diff --git a/subsys/net/ip/ipv6.c b/subsys/net/ip/ipv6.c
index 4bc3fde0636..79ea9551140 100644
--- a/subsys/net/ip/ipv6.c
+++ b/subsys/net/ip/ipv6.c
@@ -30,6 +30,7 @@ LOG_MODULE_REGISTER(net_ipv6, CONFIG_NET_IPV6_LOG_LEVEL);
 #include <zephyr/net/net_context.h>
 #include <zephyr/net/net_mgmt.h>
 #include <zephyr/net/virtual.h>
+#include <zephyr/net/ethernet.h>
 #include "net_private.h"
 #include "connection.h"
 #include "icmpv6.h"
@@ -142,6 +143,8 @@ int net_ipv6_finalize(struct net_pkt *pkt, uint8_t next_header_proto)
 		return -ENOBUFS;
 	}
 
+	net_pkt_set_ll_proto_type(pkt, NET_ETH_PTYPE_IPV6);
+
 	if (IS_ENABLED(CONFIG_NET_UDP) &&
 	    next_header_proto == IPPROTO_UDP) {
 		return net_udp_finalize(pkt, false);
@@ -581,6 +584,7 @@ enum net_verdict net_ipv6_input(struct net_pkt *pkt, bool is_loopback)
 	if (!net_pkt_filter_ip_recv_ok(pkt)) {
 		/* drop the packet */
 		NET_DBG("DROP: pkt filter");
+		net_stats_update_filter_rx_ipv6_drop(net_pkt_iface(pkt));
 		return NET_DROP;
 	}
 
@@ -759,6 +763,14 @@ enum net_verdict net_ipv6_input(struct net_pkt *pkt, bool is_loopback)
 
 	net_pkt_set_ipv6_ext_len(pkt, ext_len);
 
+	ip.ipv6 = hdr;
+
+	if (IS_ENABLED(CONFIG_NET_SOCKETS_INET_RAW)) {
+		if (net_conn_raw_ip_input(pkt, &ip, current_hdr) == NET_DROP) {
+			goto drop;
+		}
+	}
+
 	switch (current_hdr) {
 	case IPPROTO_ICMPV6:
 		verdict = net_icmpv6_input(pkt, hdr);
@@ -813,8 +825,6 @@ enum net_verdict net_ipv6_input(struct net_pkt *pkt, bool is_loopback)
 		return verdict;
 	}
 
-	ip.ipv6 = hdr;
-
 	verdict = net_conn_input(pkt, &ip, current_hdr, &proto_hdr);
 
 	NET_DBG("%s verdict %s", "Connection", net_verdict2str(verdict));
diff --git a/subsys/net/ip/ipv6.h b/subsys/net/ip/ipv6.h
index 68115f818c2..2420de6db90 100644
--- a/subsys/net/ip/ipv6.h
+++ b/subsys/net/ip/ipv6.h
@@ -641,7 +641,7 @@ static inline int net_ipv6_pe_init(struct net_if *iface)
 #endif /* CONFIG_NET_IPV6_PE */
 
 typedef void (*net_ipv6_pe_filter_cb_t)(struct in6_addr *prefix,
-					bool is_blacklist,
+					bool is_denylist,
 					void *user_data);
 
 /**
diff --git a/subsys/net/ip/ipv6_fragment.c b/subsys/net/ip/ipv6_fragment.c
index f50e5f9e4e2..a32aae979b1 100644
--- a/subsys/net/ip/ipv6_fragment.c
+++ b/subsys/net/ip/ipv6_fragment.c
@@ -609,6 +609,8 @@ static int send_ipv6_fragment(struct net_pkt *pkt,
 
 	net_pkt_cursor_init(pkt);
 
+	net_pkt_set_ll_proto_type(frag_pkt, net_pkt_ll_proto_type(pkt));
+
 	/* We copy original headers back to the fragment packet
 	 * Note that we insert the right next header to point to fragment header
 	 */
diff --git a/subsys/net/ip/ipv6_nbr.c b/subsys/net/ip/ipv6_nbr.c
index e09fa0cba2d..b64a73ed537 100644
--- a/subsys/net/ip/ipv6_nbr.c
+++ b/subsys/net/ip/ipv6_nbr.c
@@ -25,6 +25,7 @@ LOG_MODULE_REGISTER(net_ipv6_nd, CONFIG_NET_IPV6_ND_LOG_LEVEL);
 #include <zephyr/net/net_mgmt.h>
 #include <zephyr/net/dns_resolve.h>
 #include <zephyr/net/icmp.h>
+#include <zephyr/net/ethernet.h>
 #include "net_private.h"
 #include "connection.h"
 #include "icmpv6.h"
@@ -134,21 +135,6 @@ static inline struct net_nbr *get_nbr(int idx)
 	return &net_neighbor_pool[idx].nbr;
 }
 
-static inline struct net_nbr *get_nbr_from_data(struct net_ipv6_nbr_data *data)
-{
-	int i;
-
-	for (i = 0; i < CONFIG_NET_IPV6_MAX_NEIGHBORS; i++) {
-		struct net_nbr *nbr = get_nbr(i);
-
-		if (nbr->data == (uint8_t *)data) {
-			return nbr;
-		}
-	}
-
-	return NULL;
-}
-
 static void ipv6_nbr_set_state(struct net_nbr *nbr,
 			       enum net_ipv6_nbr_state new_state)
 {
@@ -457,7 +443,7 @@ static struct net_nbr *nbr_new(struct net_if *iface,
 }
 
 static void dbg_update_neighbor_lladdr(const struct net_linkaddr *new_lladdr,
-				       const struct net_linkaddr_storage *old_lladdr,
+				       const struct net_linkaddr *old_lladdr,
 				       const struct in6_addr *addr)
 {
 	char out[sizeof("xx:xx:xx:xx:xx:xx:xx:xx")];
@@ -472,14 +458,15 @@ static void dbg_update_neighbor_lladdr(const struct net_linkaddr *new_lladdr,
 }
 
 static void dbg_update_neighbor_lladdr_raw(uint8_t *new_lladdr,
-				       struct net_linkaddr_storage *old_lladdr,
-				       struct in6_addr *addr)
+					   struct net_linkaddr *old_lladdr,
+					   struct in6_addr *addr)
 {
 	struct net_linkaddr lladdr = {
 		.len = old_lladdr->len,
-		.addr = new_lladdr,
 	};
 
+	memcpy(lladdr.addr, new_lladdr, lladdr.len);
+
 	dbg_update_neighbor_lladdr(&lladdr, old_lladdr, addr);
 }
 
@@ -617,14 +604,14 @@ struct net_nbr *net_ipv6_nbr_add(struct net_if *iface,
 	if (lladdr && net_nbr_link(nbr, iface, lladdr) == -EALREADY &&
 	    net_ipv6_nbr_data(nbr)->state != NET_IPV6_NBR_STATE_STATIC) {
 		/* Update the lladdr if the node was already known */
-		struct net_linkaddr_storage *cached_lladdr;
+		struct net_linkaddr *cached_lladdr;
 
 		cached_lladdr = net_nbr_get_lladdr(nbr->idx);
 
 		if (memcmp(cached_lladdr->addr, lladdr->addr, lladdr->len)) {
 			dbg_update_neighbor_lladdr(lladdr, cached_lladdr, addr);
 
-			net_linkaddr_set(cached_lladdr, lladdr->addr,
+			net_linkaddr_set(cached_lladdr, (uint8_t *)lladdr->addr,
 					 lladdr->len);
 
 			ipv6_nbr_set_state(nbr, NET_IPV6_NBR_STATE_STALE);
@@ -860,7 +847,7 @@ enum net_verdict net_ipv6_prepare_for_send(struct net_pkt *pkt)
 	 * contain public IPv6 address information so in that case we should
 	 * not enter this branch.
 	 */
-	if ((net_pkt_lladdr_dst(pkt)->addr &&
+	if ((net_pkt_lladdr_dst(pkt)->len > 0 &&
 	     ((IS_ENABLED(CONFIG_NET_ROUTING) &&
 	      (net_ipv6_is_ll_addr((struct in6_addr *)ip_hdr->dst) ||
 	       net_if_ipv6_addr_onlink(NULL, (struct in6_addr *)ip_hdr->dst) ||
@@ -954,12 +941,12 @@ enum net_verdict net_ipv6_prepare_for_send(struct net_pkt *pkt)
 		"-");
 
 	if (nbr && nbr->idx != NET_NBR_LLADDR_UNKNOWN) {
-		struct net_linkaddr_storage *lladdr;
+		struct net_linkaddr *lladdr;
 
 		lladdr = net_nbr_get_lladdr(nbr->idx);
 
-		net_pkt_lladdr_dst(pkt)->addr = lladdr->addr;
-		net_pkt_lladdr_dst(pkt)->len = lladdr->len;
+		(void)net_linkaddr_set(net_pkt_lladdr_dst(pkt), lladdr->addr,
+				       lladdr->len);
 
 		NET_DBG("Neighbor %p addr %s", nbr,
 			net_sprint_ll_addr(lladdr->addr, lladdr->len));
@@ -1084,20 +1071,21 @@ static inline bool set_llao(struct net_pkt *pkt,
 
 static bool read_llao(struct net_pkt *pkt,
 		      uint8_t len,
-		      struct net_linkaddr_storage *llstorage)
+		      struct net_linkaddr *lladdr)
 {
 	uint8_t padding;
 
-	llstorage->len = NET_LINK_ADDR_MAX_LENGTH;
-	if (net_pkt_lladdr_src(pkt)->len < llstorage->len) {
-		llstorage->len = net_pkt_lladdr_src(pkt)->len;
+	lladdr->len = NET_LINK_ADDR_MAX_LENGTH;
+
+	if (net_pkt_lladdr_src(pkt)->len < lladdr->len) {
+		lladdr->len = net_pkt_lladdr_src(pkt)->len;
 	}
 
-	if (net_pkt_read(pkt, llstorage->addr, llstorage->len)) {
+	if (net_pkt_read(pkt, lladdr->addr, lladdr->len)) {
 		return false;
 	}
 
-	padding = len * 8U - 2 - llstorage->len;
+	padding = len * 8U - 2 - lladdr->len;
 	if (padding) {
 		if (net_pkt_skip(pkt, padding)) {
 			return false;
@@ -1224,7 +1212,6 @@ static int handle_ns_input(struct net_icmp_ctx *ctx,
 	const struct in6_addr *na_src;
 	const struct in6_addr *na_dst;
 	struct in6_addr *tgt;
-	struct net_linkaddr_storage src_lladdr_s;
 	struct net_linkaddr src_lladdr;
 
 	src_lladdr.len = 0;
@@ -1274,14 +1261,11 @@ static int handle_ns_input(struct net_icmp_ctx *ctx,
 				goto drop;
 			}
 
-			if (!read_llao(pkt, nd_opt_hdr->len, &src_lladdr_s)) {
+			if (!read_llao(pkt, nd_opt_hdr->len, &src_lladdr)) {
 				NET_ERR("DROP: failed to read LLAO");
 				goto drop;
 			}
 
-			src_lladdr.len = src_lladdr_s.len;
-			src_lladdr.addr = src_lladdr_s.addr;
-
 			break;
 		default:
 			NET_DBG("Unknown ND option 0x%x", nd_opt_hdr->type);
@@ -1445,7 +1429,7 @@ static int handle_ns_input(struct net_icmp_ctx *ctx,
 	}
 
 send_na:
-	if (src_lladdr.len) {
+	if (src_lladdr.len > 0) {
 		if (!net_ipv6_nbr_add(net_pkt_iface(pkt),
 				      (struct in6_addr *)ip_hdr->src,
 				      &src_lladdr, false,
@@ -1591,7 +1575,7 @@ static void ipv6_nd_reachable_timeout(struct k_work *work)
 					data->ns_count);
 
 				ret = net_ipv6_send_ns(nbr->iface, NULL, NULL,
-						       NULL, &data->addr,
+						       &data->addr, &data->addr,
 						       false);
 				if (ret < 0) {
 					NET_DBG("Cannot send NS (%d)", ret);
@@ -1653,9 +1637,9 @@ static inline bool handle_na_neighbor(struct net_pkt *pkt,
 				      struct net_icmpv6_na_hdr *na_hdr,
 				      uint16_t tllao_offset)
 {
-	struct net_linkaddr_storage lladdr = { 0 };
+	struct net_linkaddr lladdr = { 0 };
 	bool lladdr_changed = false;
-	struct net_linkaddr_storage *cached_lladdr;
+	struct net_linkaddr *cached_lladdr;
 	struct net_pkt *pending;
 	struct net_nbr *nbr;
 
@@ -1694,8 +1678,7 @@ static inline bool handle_na_neighbor(struct net_pkt *pkt,
 			goto err;
 		}
 
-		nbr_lladdr.len = lladdr.len;
-		nbr_lladdr.addr = lladdr.addr;
+		(void)net_linkaddr_set(&nbr_lladdr, lladdr.addr, lladdr.len);
 
 		if (net_nbr_link(nbr, net_pkt_iface(pkt), &nbr_lladdr)) {
 			nbr_free(nbr);
@@ -1769,7 +1752,7 @@ static inline bool handle_na_neighbor(struct net_pkt *pkt,
 
 	if (na_hdr->flags & NET_ICMPV6_NA_FLAG_OVERRIDE ||
 	    (!(na_hdr->flags & NET_ICMPV6_NA_FLAG_OVERRIDE) &&
-	     tllao_offset && !lladdr_changed)) {
+	     !lladdr_changed)) {
 
 		if (lladdr_changed) {
 			dbg_update_neighbor_lladdr_raw(
@@ -2175,15 +2158,11 @@ int net_ipv6_start_rs(struct net_if *iface)
 static inline struct net_nbr *handle_ra_neighbor(struct net_pkt *pkt, uint8_t len)
 {
 	struct net_linkaddr lladdr;
-	struct net_linkaddr_storage llstorage;
 
-	if (!read_llao(pkt, len, &llstorage)) {
+	if (!read_llao(pkt, len, &lladdr)) {
 		return NULL;
 	}
 
-	lladdr.len = llstorage.len;
-	lladdr.addr = llstorage.addr;
-
 	return net_ipv6_nbr_add(net_pkt_iface(pkt),
 				(struct in6_addr *)NET_IPV6_HDR(pkt)->src,
 				&lladdr, true,
@@ -2612,12 +2591,6 @@ static int handle_ra_input(struct net_icmp_ctx *ctx,
 	nd_opt_hdr = (struct net_icmpv6_nd_opt_hdr *)
 				net_pkt_get_data(pkt, &nd_access);
 
-	/* Add neighbor cache entry using link local address, regardless of link layer address
-	 * presence in Router Advertisement.
-	 */
-	nbr = net_ipv6_nbr_add(net_pkt_iface(pkt), (struct in6_addr *)NET_IPV6_HDR(pkt)->src, NULL,
-				true, NET_IPV6_NBR_STATE_INCOMPLETE);
-
 	while (nd_opt_hdr) {
 		net_pkt_acknowledge_data(pkt, &nd_access);
 
@@ -2718,6 +2691,15 @@ static int handle_ra_input(struct net_icmp_ctx *ctx,
 					net_pkt_get_data(pkt, &nd_access);
 	}
 
+	if (nbr == NULL) {
+		/* Add neighbor cache entry using link local address, regardless
+		 * of link layer address presence in Router Advertisement.
+		 */
+		nbr = net_ipv6_nbr_add(net_pkt_iface(pkt),
+				       (struct in6_addr *)NET_IPV6_HDR(pkt)->src,
+				       NULL, true, NET_IPV6_NBR_STATE_INCOMPLETE);
+	}
+
 	router = net_if_ipv6_router_lookup(net_pkt_iface(pkt),
 					   (struct in6_addr *)ip_hdr->src);
 	if (router) {
diff --git a/subsys/net/ip/nbr.c b/subsys/net/ip/nbr.c
index 8cf42862d0d..f9d9f68f882 100644
--- a/subsys/net/ip/nbr.c
+++ b/subsys/net/ip/nbr.c
@@ -122,7 +122,8 @@ int net_nbr_link(struct net_nbr *nbr, struct net_if *iface,
 	net_neighbor_lladdr[avail].ref++;
 	nbr->idx = avail;
 
-	net_linkaddr_set(&net_neighbor_lladdr[avail].lladdr, lladdr->addr,
+	net_linkaddr_set(&net_neighbor_lladdr[avail].lladdr,
+			 (uint8_t *)lladdr->addr,
 			 lladdr->len);
 	net_neighbor_lladdr[avail].lladdr.len = lladdr->len;
 	net_neighbor_lladdr[avail].lladdr.type = lladdr->type;
@@ -176,7 +177,7 @@ struct net_nbr *net_nbr_lookup(struct net_nbr_table *table,
 	return NULL;
 }
 
-struct net_linkaddr_storage *net_nbr_get_lladdr(uint8_t idx)
+struct net_linkaddr *net_nbr_get_lladdr(uint8_t idx)
 {
 	NET_ASSERT(idx < CONFIG_NET_IPV6_MAX_NEIGHBORS,
 		   "idx %d >= max %d", idx,
@@ -191,10 +192,10 @@ void net_nbr_clear_table(struct net_nbr_table *table)
 
 	for (i = 0; i < table->nbr_count; i++) {
 		struct net_nbr *nbr = get_nbr(table->nbr, i);
-		struct net_linkaddr lladdr = {
-			.addr = net_neighbor_lladdr[i].lladdr.addr,
-			.len = net_neighbor_lladdr[i].lladdr.len
-		};
+		struct net_linkaddr lladdr;
+
+		(void)net_linkaddr_set(&lladdr, net_neighbor_lladdr[i].lladdr.addr,
+				       net_neighbor_lladdr[i].lladdr.len);
 
 		net_nbr_unlink(nbr, &lladdr);
 	}
diff --git a/subsys/net/ip/nbr.h b/subsys/net/ip/nbr.h
index bab4249acba..92e672b3ac6 100644
--- a/subsys/net/ip/nbr.h
+++ b/subsys/net/ip/nbr.h
@@ -28,7 +28,7 @@ extern "C" {
  */
 struct net_nbr_lladdr {
 	/** Link layer address */
-	struct net_linkaddr_storage lladdr;
+	struct net_linkaddr lladdr;
 
 	/** Reference count. */
 	uint8_t ref;
@@ -177,9 +177,9 @@ int net_nbr_unlink(struct net_nbr *nbr, struct net_linkaddr *lladdr);
  * @return Pointer to link layer address storage, NULL if not found
  */
 #if defined(CONFIG_NET_NATIVE)
-struct net_linkaddr_storage *net_nbr_get_lladdr(uint8_t idx);
+struct net_linkaddr *net_nbr_get_lladdr(uint8_t idx);
 #else
-static inline struct net_linkaddr_storage *net_nbr_get_lladdr(uint8_t idx)
+static inline struct net_linkaddr *net_nbr_get_lladdr(uint8_t idx)
 {
 	ARG_UNUSED(idx);
 
diff --git a/subsys/net/ip/net_context.c b/subsys/net/ip/net_context.c
index 886d6325a3b..0890a22764c 100644
--- a/subsys/net/ip/net_context.c
+++ b/subsys/net/ip/net_context.c
@@ -7,6 +7,7 @@
 /*
  * Copyright (c) 2016 Intel Corporation
  * Copyright (c) 2021 Nordic Semiconductor
+ * Copyright (c) 2025 Aerlync Labs Inc.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -465,6 +466,10 @@ static int net_context_check(sa_family_t family, enum net_sock_type type,
 			}
 			break;
 		case SOCK_RAW:
+			if (!IS_ENABLED(CONFIG_NET_SOCKETS_INET_RAW)) {
+				NET_DBG("RAW IP sockets disabled.");
+				return -EPROTONOSUPPORT;
+			}
 			break;
 		default:
 			NET_DBG("Unknown context type.");
@@ -565,6 +570,10 @@ int net_context_get(sa_family_t family, enum net_sock_type type, uint16_t proto,
 #if defined(CONFIG_NET_IPV4_MAPPING_TO_IPV6)
 		/* By default IPv4 and IPv6 are in different port spaces */
 		contexts[i].options.ipv6_v6only = true;
+#endif
+#if defined(CONFIG_NET_IPV4)
+		contexts[i].options.ipv4_mcast_loop =
+			IS_ENABLED(CONFIG_NET_INITIAL_IPV4_MCAST_LOOP);
 #endif
 		if (IS_ENABLED(CONFIG_NET_IP)) {
 			(void)memset(&contexts[i].remote, 0, sizeof(struct sockaddr));
@@ -583,6 +592,10 @@ int net_context_get(sa_family_t family, enum net_sock_type type, uint16_t proto,
 
 				contexts[i].ipv6_hop_limit = INITIAL_HOP_LIMIT;
 				contexts[i].ipv6_mcast_hop_limit = INITIAL_MCAST_HOP_LIMIT;
+#if defined(CONFIG_NET_IPV6)
+				contexts[i].options.ipv6_mcast_loop =
+					IS_ENABLED(CONFIG_NET_INITIAL_IPV6_MCAST_LOOP);
+#endif
 			}
 			if (IS_ENABLED(CONFIG_NET_IPV4) && family == AF_INET) {
 				struct sockaddr_in *addr = (struct sockaddr_in *)&contexts[i].local;
@@ -724,9 +737,9 @@ static int bind_default(struct net_context *context)
 		addr6.sin6_family = AF_INET6;
 		memcpy(&addr6.sin6_addr, net_ipv6_unspecified_address(),
 		       sizeof(addr6.sin6_addr));
-		addr6.sin6_port =
-			find_available_port(context,
-					    (struct sockaddr *)&addr6);
+		addr6.sin6_port = net_context_get_type(context) == SOCK_RAW ?
+			0 : find_available_port(context,
+						(struct sockaddr *)&addr6);
 
 		return net_context_bind(context, (struct sockaddr *)&addr6,
 					sizeof(addr6));
@@ -741,9 +754,9 @@ static int bind_default(struct net_context *context)
 
 		addr4.sin_family = AF_INET;
 		addr4.sin_addr.s_addr = INADDR_ANY;
-		addr4.sin_port =
-			find_available_port(context,
-					    (struct sockaddr *)&addr4);
+		addr4.sin_port = net_context_get_type(context) == SOCK_RAW ?
+			0 : find_available_port(context,
+						(struct sockaddr *)&addr4);
 
 		return net_context_bind(context, (struct sockaddr *)&addr4,
 					sizeof(addr4));
@@ -751,14 +764,19 @@ static int bind_default(struct net_context *context)
 
 	if (IS_ENABLED(CONFIG_NET_SOCKETS_PACKET) && family == AF_PACKET) {
 		struct sockaddr_ll ll_addr;
+		struct net_if *iface = net_context_get_iface(context);
 
 		if (net_sll_ptr(&context->local)->sll_addr) {
 			return 0;
 		}
 
+		if (iface == NULL) {
+			iface = net_if_get_default();
+		}
+
 		ll_addr.sll_family = AF_PACKET;
 		ll_addr.sll_protocol = htons(ETH_P_ALL);
-		ll_addr.sll_ifindex = net_if_get_by_iface(net_if_get_default());
+		ll_addr.sll_ifindex = net_if_get_by_iface(iface);
 
 		return net_context_bind(context, (struct sockaddr *)&ll_addr,
 					sizeof(ll_addr));
@@ -1244,7 +1262,7 @@ int net_context_create_ipv4_new(struct net_context *context,
 						  (struct in_addr *)dst);
 		/* If src address is still unspecified, do not create pkt */
 		if (net_ipv4_is_addr_unspecified(src)) {
-			NET_DBG("DROP: src addr is unspecified");
+			NET_WARN("DROP: src addr is unspecified");
 			return -EINVAL;
 		}
 	}
@@ -1778,6 +1796,19 @@ static int get_context_mcast_ttl(struct net_context *context,
 #endif
 }
 
+static int get_context_ipv4_mcast_loop(struct net_context *context,
+				  void *value, size_t *len)
+{
+#if defined(CONFIG_NET_IPV4)
+	return get_bool_option(context->options.ipv4_mcast_loop, value, len);
+#else
+	ARG_UNUSED(context);
+	ARG_UNUSED(value);
+	ARG_UNUSED(len);
+	return -ENOTSUP;
+#endif
+}
+
 static int get_context_mcast_hop_limit(struct net_context *context,
 				       void *value, size_t *len)
 {
@@ -2033,6 +2064,20 @@ static int get_context_local_port_range(struct net_context *context,
 #endif
 }
 
+static int get_context_ipv6_mcast_loop(struct net_context *context,
+				       void *value, size_t *len)
+{
+#if defined(CONFIG_NET_IPV6)
+	return get_bool_option(context->options.ipv6_mcast_loop, value, len);
+#else
+	ARG_UNUSED(context);
+	ARG_UNUSED(value);
+	ARG_UNUSED(len);
+
+	return -ENOTSUP;
+#endif
+}
+
 /* If buf is not NULL, then use it. Otherwise read the data to be written
  * to net_pkt from msghdr.
  */
@@ -2128,6 +2173,57 @@ static int context_setup_udp_packet(struct net_context *context,
 	return 0;
 }
 
+static int context_setup_raw_ip_packet(sa_family_t family,
+				       struct net_pkt *pkt,
+				       const void *buf,
+				       size_t len,
+				       const struct msghdr *msg)
+{
+	int ret;
+
+	ret = context_write_data(pkt, buf, len, msg);
+	if (ret < 0) {
+		return ret;
+	}
+
+	if (family == AF_INET) {
+		NET_PKT_DATA_ACCESS_CONTIGUOUS_DEFINE(ipv4_access,
+						      struct net_ipv4_hdr);
+		struct net_ipv4_hdr *ipv4_hdr;
+		uint8_t hdr_len;
+
+		net_pkt_cursor_init(pkt);
+		net_pkt_set_overwrite(pkt, true);
+
+		ipv4_hdr = (struct net_ipv4_hdr *)net_pkt_get_data(pkt, &ipv4_access);
+		if (ipv4_hdr == NULL) {
+			return -ENOBUFS;
+		}
+
+		net_pkt_set_ip_hdr_len(pkt, sizeof(struct net_ipv4_hdr));
+
+		hdr_len = (ipv4_hdr->vhl & 0x0F) * 4;
+		if (hdr_len > sizeof(struct net_ipv4_hdr)) {
+			net_pkt_set_ipv4_opts_len(
+				pkt, hdr_len - sizeof(struct net_ipv4_hdr));
+		}
+
+		if (net_if_need_calc_tx_checksum(net_pkt_iface(pkt),
+						 NET_IF_CHECKSUM_IPV4_HEADER)) {
+			ipv4_hdr->chksum = 0;
+			ipv4_hdr->chksum = net_calc_chksum_ipv4(pkt);
+			net_pkt_set_data(pkt, &ipv4_access);
+		}
+
+		net_pkt_set_ll_proto_type(pkt, ETH_P_IP);
+	} else {
+		net_pkt_set_ip_hdr_len(pkt, sizeof(struct net_ipv6_hdr));
+		net_pkt_set_ll_proto_type(pkt, ETH_P_IPV6);
+	}
+
+	return 0;
+}
+
 static void context_finalize_packet(struct net_context *context,
 				    sa_family_t family,
 				    struct net_pkt *pkt)
@@ -2396,6 +2492,8 @@ static int context_sendto(struct net_context *context,
 					ll_addr->sll_ifindex);
 				return -EDESTADDRREQ;
 			}
+
+			net_context_set_iface(context, iface);
 		}
 
 		if (net_context_get_type(context) == SOCK_DGRAM) {
@@ -2486,7 +2584,8 @@ static int context_sendto(struct net_context *context,
 	tmp_len = net_pkt_available_payload_buffer(
 				pkt, net_context_get_proto(context));
 	if (tmp_len < len) {
-		if (net_context_get_type(context) == SOCK_DGRAM) {
+		if (net_context_get_type(context) == SOCK_DGRAM ||
+		    net_context_get_type(context) == SOCK_RAW) {
 			NET_ERR("Available payload buffer (%zu) is not enough for requested DGRAM (%zu)",
 				tmp_len, len);
 			ret = -ENOMEM;
@@ -2534,6 +2633,16 @@ static int context_sendto(struct net_context *context,
 			ret = net_offload_send(net_context_get_iface(context),
 					       pkt, cb, timeout, user_data);
 		}
+	} else if (((IS_ENABLED(CONFIG_NET_IPV4) && family == AF_INET) ||
+		    (IS_ENABLED(CONFIG_NET_IPV6) && family == AF_INET6)) &&
+		   IS_ENABLED(CONFIG_NET_SOCKETS_INET_RAW) &&
+		   net_context_get_type(context) == SOCK_RAW) {
+		ret = context_setup_raw_ip_packet(family, pkt, buf, len, msghdr);
+		if (ret < 0) {
+			goto fail;
+		}
+
+		ret = net_try_send_data(pkt, timeout);
 	} else if (IS_ENABLED(CONFIG_NET_UDP) &&
 	    net_context_get_proto(context) == IPPROTO_UDP) {
 		ret = context_setup_udp_packet(context, family, pkt, buf, len, msghdr,
@@ -2544,7 +2653,7 @@ static int context_sendto(struct net_context *context,
 
 		context_finalize_packet(context, family, pkt);
 
-		ret = net_send_data(pkt);
+		ret = net_try_send_data(pkt, timeout);
 	} else if (IS_ENABLED(CONFIG_NET_TCP) &&
 		   net_context_get_proto(context) == IPPROTO_TCP) {
 
@@ -2564,27 +2673,25 @@ static int context_sendto(struct net_context *context,
 
 		net_pkt_cursor_init(pkt);
 
-		if (net_context_get_proto(context) == IPPROTO_RAW) {
-			char type = (NET_IPV6_HDR(pkt)->vtc & 0xf0);
+		struct sockaddr_ll_ptr *ll_src_addr;
+		struct sockaddr_ll *ll_dst_addr;
 
-			/* Set the family to pkt if detected */
-			switch (type) {
-			case 0x60:
-				net_pkt_set_family(pkt, AF_INET6);
-				break;
-			case 0x40:
-				net_pkt_set_family(pkt, AF_INET);
-				break;
-			default:
-				/* Not IP traffic, let it go forward as it is */
-				break;
-			}
+		/* The destination address is set in remote for this
+		 * socket type.
+		 */
+		ll_dst_addr = (struct sockaddr_ll *)&context->remote;
+		ll_src_addr = (struct sockaddr_ll_ptr *)&context->local;
 
-			/* Pass to L2: */
-			ret = net_send_data(pkt);
-		} else {
-			net_if_queue_tx(net_pkt_iface(pkt), pkt);
-		}
+		(void)net_linkaddr_set(net_pkt_lladdr_dst(pkt),
+				       ll_dst_addr->sll_addr,
+				       sizeof(struct net_eth_addr));
+		(void)net_linkaddr_set(net_pkt_lladdr_src(pkt),
+				       ll_src_addr->sll_addr,
+				       sizeof(struct net_eth_addr));
+
+		net_pkt_set_ll_proto_type(pkt, ntohs(ll_dst_addr->sll_protocol));
+
+		net_if_try_queue_tx(net_pkt_iface(pkt), pkt, timeout);
 	} else if (IS_ENABLED(CONFIG_NET_SOCKETS_CAN) && family == AF_CAN &&
 		   net_context_get_proto(context) == CAN_RAW) {
 		ret = context_write_data(pkt, buf, len, msghdr);
@@ -2594,7 +2701,7 @@ static int context_sendto(struct net_context *context,
 
 		net_pkt_cursor_init(pkt);
 
-		ret = net_send_data(pkt);
+		ret = net_try_send_data(pkt, timeout);
 	} else {
 		NET_DBG("Unknown protocol while sending packet: %d",
 		net_context_get_proto(context));
@@ -2614,6 +2721,75 @@ static int context_sendto(struct net_context *context,
 	return ret;
 }
 
+static void raw_inet_set_remote(struct net_context *context, const void *buf,
+				size_t len)
+{
+	struct net_if *iface;
+
+	if (net_context_get_family(context) == AF_INET) {
+		struct sockaddr_in *remote =
+			(struct sockaddr_in *)&context->remote;
+		const struct net_ipv4_hdr *iphdr = buf;
+
+		if (len < sizeof(struct net_ipv4_hdr)) {
+			return;
+		}
+
+		if (!net_ipv4_is_addr_unspecified(
+				&net_sin(&context->remote)->sin_addr)) {
+			goto out;
+		}
+
+		remote->sin_family = AF_INET;
+		remote->sin_port = 0;
+		memcpy(&remote->sin_addr, iphdr->dst, sizeof(remote->sin_addr));
+
+		if (net_context_is_bound_to_iface(context)) {
+			goto out;
+		}
+
+		iface = net_if_ipv4_select_src_iface(&remote->sin_addr);
+		if (iface == NULL) {
+			goto out;
+		}
+
+		net_context_set_iface(context, iface);
+	} else if (net_context_get_family(context) == AF_INET6) {
+		struct sockaddr_in6 *remote =
+			(struct sockaddr_in6 *)&context->remote;
+		const struct net_ipv6_hdr *iphdr = buf;
+
+		if (len < sizeof(struct net_ipv6_hdr)) {
+			return;
+		}
+
+		if (!net_ipv6_is_addr_unspecified(
+				&net_sin6(&context->remote)->sin6_addr)) {
+			goto out;
+		}
+
+		remote->sin6_family = AF_INET6;
+		remote->sin6_port = 0;
+		memcpy(&remote->sin6_addr, iphdr->dst, sizeof(remote->sin6_addr));
+
+		if (net_context_is_bound_to_iface(context)) {
+			goto out;
+		}
+
+		iface = net_if_ipv6_select_src_iface(&remote->sin6_addr);
+		if (iface == NULL) {
+			goto out;
+		}
+
+		net_context_set_iface(context, iface);
+	} else {
+		return;
+	}
+
+out:
+	context->flags |= NET_CONTEXT_REMOTE_ADDR_SET;
+}
+
 int net_context_send(struct net_context *context,
 		     const void *buf,
 		     size_t len,
@@ -2621,23 +2797,28 @@ int net_context_send(struct net_context *context,
 		     k_timeout_t timeout,
 		     void *user_data)
 {
+	bool dst_check = true;
 	socklen_t addrlen;
 	int ret = 0;
 
 	k_mutex_lock(&context->lock, K_FOREVER);
 
-	if (!(context->flags & NET_CONTEXT_REMOTE_ADDR_SET) ||
-	    !net_sin(&context->remote)->sin_port) {
-		ret = -EDESTADDRREQ;
-		goto unlock;
-	}
-
 	if (IS_ENABLED(CONFIG_NET_IPV6) &&
 	    net_context_get_family(context) == AF_INET6) {
 		addrlen = sizeof(struct sockaddr_in6);
+		if (IS_ENABLED(CONFIG_NET_SOCKETS_INET_RAW) &&
+		    net_context_get_type(context) == SOCK_RAW) {
+			raw_inet_set_remote(context, buf, len);
+			dst_check = false;
+		}
 	} else if (IS_ENABLED(CONFIG_NET_IPV4) &&
 		   net_context_get_family(context) == AF_INET) {
 		addrlen = sizeof(struct sockaddr_in);
+		if (IS_ENABLED(CONFIG_NET_SOCKETS_INET_RAW) &&
+		    net_context_get_type(context) == SOCK_RAW) {
+			raw_inet_set_remote(context, buf, len);
+			dst_check = false;
+		}
 	} else if (IS_ENABLED(CONFIG_NET_SOCKETS_PACKET) &&
 		   net_context_get_family(context) == AF_PACKET) {
 		ret = -EOPNOTSUPP;
@@ -2649,6 +2830,14 @@ int net_context_send(struct net_context *context,
 		addrlen = 0;
 	}
 
+	if (dst_check) {
+		if (!(context->flags & NET_CONTEXT_REMOTE_ADDR_SET) ||
+		    net_sin(&context->remote)->sin_port == 0) {
+			ret = -EDESTADDRREQ;
+			goto unlock;
+		}
+	}
+
 	ret = context_sendto(context, buf, len, &context->remote,
 			     addrlen, cb, timeout, user_data, false);
 unlock:
@@ -2744,11 +2933,11 @@ enum net_verdict net_context_packet_received(struct net_conn *conn,
 	return verdict;
 }
 
-#if defined(CONFIG_NET_NATIVE_UDP)
-static int recv_udp(struct net_context *context,
-		    net_context_recv_cb_t cb,
-		    k_timeout_t timeout,
-		    void *user_data)
+#if defined(CONFIG_NET_NATIVE_IP)
+static int recv_dgram(struct net_context *context,
+		      net_context_recv_cb_t cb,
+		      k_timeout_t timeout,
+		      void *user_data)
 {
 	struct sockaddr local_addr = {
 		.sa_family = net_context_get_family(context),
@@ -2811,6 +3000,7 @@ static int recv_udp(struct net_context *context,
 	context->recv_cb = cb;
 
 	ret = net_conn_register(net_context_get_proto(context),
+				net_context_get_type(context),
 				net_context_get_family(context),
 				context->flags & NET_CONTEXT_REMOTE_ADDR_SET ?
 							&context->remote : NULL,
@@ -2825,7 +3015,7 @@ static int recv_udp(struct net_context *context,
 	return ret;
 }
 #else
-#define recv_udp(...) 0
+#define recv_dgram(...) 0
 #endif /* CONFIG_NET_NATIVE_UDP */
 
 static enum net_verdict net_context_raw_packet_received(
@@ -2896,6 +3086,7 @@ static int recv_raw(struct net_context *context,
 	context->recv_cb = cb;
 
 	ret = net_conn_register(net_context_get_proto(context),
+				net_context_get_type(context),
 				net_context_get_family(context),
 				NULL, local_addr, 0, 0,
 				context,
@@ -2911,7 +3102,9 @@ int net_context_recv(struct net_context *context,
 		     k_timeout_t timeout,
 		     void *user_data)
 {
+	int family;
 	int ret;
+
 	NET_ASSERT(context);
 
 	if (!net_context_is_used(context)) {
@@ -2928,15 +3121,22 @@ int net_context_recv(struct net_context *context,
 		goto unlock;
 	}
 
-	if (IS_ENABLED(CONFIG_NET_UDP) &&
-	    net_context_get_proto(context) == IPPROTO_UDP) {
-		ret = recv_udp(context, cb, timeout, user_data);
+	family = net_context_get_family(context);
+
+	if (((IS_ENABLED(CONFIG_NET_IPV4) && family == AF_INET) ||
+	     (IS_ENABLED(CONFIG_NET_IPV6) && family == AF_INET6)) &&
+	    IS_ENABLED(CONFIG_NET_SOCKETS_INET_RAW) &&
+	    net_context_get_type(context) == SOCK_RAW) {
+		ret = recv_dgram(context, cb, timeout, user_data);
+	} else if (IS_ENABLED(CONFIG_NET_UDP) &&
+		   net_context_get_proto(context) == IPPROTO_UDP) {
+		ret = recv_dgram(context, cb, timeout, user_data);
 	} else if (IS_ENABLED(CONFIG_NET_TCP) &&
 		   net_context_get_proto(context) == IPPROTO_TCP) {
 		ret = net_tcp_recv(context, cb, user_data);
 	} else {
 		if (IS_ENABLED(CONFIG_NET_SOCKETS_PACKET) &&
-		    net_context_get_family(context) == AF_PACKET) {
+		    family == AF_PACKET) {
 			struct sockaddr_ll addr;
 
 			addr.sll_family = AF_PACKET;
@@ -2954,7 +3154,7 @@ int net_context_recv(struct net_context *context,
 			ret = recv_raw(context, cb, timeout,
 				       (struct sockaddr *)&addr, user_data);
 		} else if (IS_ENABLED(CONFIG_NET_SOCKETS_CAN) &&
-			   net_context_get_family(context) == AF_CAN) {
+			   family == AF_CAN) {
 			struct sockaddr_can local_addr = {
 				.can_family = AF_CAN,
 			};
@@ -3248,6 +3448,20 @@ static int set_context_mcast_ttl(struct net_context *context,
 #endif
 }
 
+static int set_context_ipv4_mcast_loop(struct net_context *context,
+				       const void *value, size_t len)
+{
+#if defined(CONFIG_NET_IPV4)
+	return set_bool_option(&context->options.ipv4_mcast_loop, value, len);
+#else
+	ARG_UNUSED(context);
+	ARG_UNUSED(value);
+	ARG_UNUSED(len);
+
+	return -ENOTSUP;
+#endif
+}
+
 static int set_context_mcast_hop_limit(struct net_context *context,
 				       const void *value, size_t len)
 {
@@ -3303,6 +3517,20 @@ static int set_context_unicast_hop_limit(struct net_context *context,
 #endif
 }
 
+static int set_context_ipv6_mcast_loop(struct net_context *context,
+				       const void *value, size_t len)
+{
+#if defined(CONFIG_NET_IPV6)
+	return set_bool_option(&context->options.ipv6_mcast_loop, value, len);
+#else
+	ARG_UNUSED(context);
+	ARG_UNUSED(value);
+	ARG_UNUSED(len);
+
+	return -ENOTSUP;
+#endif
+}
+
 static int set_context_reuseaddr(struct net_context *context,
 				 const void *value, size_t len)
 {
@@ -3626,6 +3854,12 @@ int net_context_set_option(struct net_context *context,
 	case NET_OPT_LOCAL_PORT_RANGE:
 		ret = set_context_local_port_range(context, value, len);
 		break;
+	case NET_OPT_IPV6_MCAST_LOOP:
+		ret = set_context_ipv6_mcast_loop(context, value, len);
+		break;
+	case NET_OPT_IPV4_MCAST_LOOP:
+		ret = set_context_ipv4_mcast_loop(context, value, len);
+		break;
 	}
 
 	k_mutex_unlock(&context->lock);
@@ -3711,6 +3945,12 @@ int net_context_get_option(struct net_context *context,
 	case NET_OPT_LOCAL_PORT_RANGE:
 		ret = get_context_local_port_range(context, value, len);
 		break;
+	case NET_OPT_IPV6_MCAST_LOOP:
+		ret = get_context_ipv6_mcast_loop(context, value, len);
+		break;
+	case NET_OPT_IPV4_MCAST_LOOP:
+		ret = get_context_ipv4_mcast_loop(context, value, len);
+		break;
 	}
 
 	k_mutex_unlock(&context->lock);
diff --git a/subsys/net/ip/net_core.c b/subsys/net/ip/net_core.c
index facc4c8ecc7..d27defd2c12 100644
--- a/subsys/net/ip/net_core.c
+++ b/subsys/net/ip/net_core.c
@@ -7,6 +7,7 @@
 
 /*
  * Copyright (c) 2016 Intel Corporation
+ * Copyright (c) 2025 Aerlync Labs Inc.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -116,7 +117,7 @@ static inline enum net_verdict process_data(struct net_pkt *pkt,
 		/* Consecutive call will forward packets to SOCK_DGRAM packet sockets
 		 * (after L2 removed header).
 		 */
-		ret = net_packet_socket_input(pkt, ETH_P_ALL);
+		ret = net_packet_socket_input(pkt, net_pkt_ll_proto_type(pkt));
 		if (ret != NET_CONTINUE) {
 			return ret;
 		}
@@ -126,13 +127,6 @@ static inline enum net_verdict process_data(struct net_pkt *pkt,
 
 	if (IS_ENABLED(CONFIG_NET_IP) && (family == AF_INET || family == AF_INET6 ||
 					  family == AF_UNSPEC || family == AF_PACKET)) {
-		/* L2 processed, now we can pass IPPROTO_RAW to packet socket:
-		 */
-		ret = net_packet_socket_input(pkt, IPPROTO_RAW);
-		if (ret != NET_CONTINUE) {
-			return ret;
-		}
-
 		/* IP version and header length. */
 		uint8_t vtc_vhl = NET_IPV6_HDR(pkt)->vtc & 0xf0;
 
@@ -215,7 +209,8 @@ static inline int check_ip(struct net_pkt *pkt)
 	family = net_pkt_family(pkt);
 	ret = 0;
 
-	if (IS_ENABLED(CONFIG_NET_IPV6) && family == AF_INET6) {
+	if (IS_ENABLED(CONFIG_NET_IPV6) && family == AF_INET6 &&
+	    net_pkt_ll_proto_type(pkt) == NET_ETH_PTYPE_IPV6) {
 		/* Drop IPv6 packet if hop limit is 0 */
 		if (NET_IPV6_HDR(pkt)->hop_limit == 0) {
 			NET_DBG("DROP: IPv6 hop limit");
@@ -288,7 +283,8 @@ static inline int check_ip(struct net_pkt *pkt)
 			goto drop;
 		}
 
-	} else if (IS_ENABLED(CONFIG_NET_IPV4) && family == AF_INET) {
+	} else if (IS_ENABLED(CONFIG_NET_IPV4) && family == AF_INET &&
+		   net_pkt_ll_proto_type(pkt) == NET_ETH_PTYPE_IP) {
 		/* Drop IPv4 packet if ttl is 0 */
 		if (NET_IPV4_HDR(pkt)->ttl == 0) {
 			NET_DBG("DROP: IPv4 ttl");
@@ -363,8 +359,35 @@ static inline int check_ip(struct net_pkt *pkt)
 	return ret;
 }
 
-/* Called when data needs to be sent to network */
-int net_send_data(struct net_pkt *pkt)
+#if defined(CONFIG_NET_IPV4) || defined(CONFIG_NET_IPV6)
+static inline bool process_multicast(struct net_pkt *pkt)
+{
+	struct net_context *ctx = net_pkt_context(pkt);
+	sa_family_t family = net_pkt_family(pkt);
+
+	if (ctx == NULL) {
+		return false;
+	}
+
+#if defined(CONFIG_NET_IPV4)
+	if (family == AF_INET) {
+		const struct in_addr *dst = (const struct in_addr *)&NET_IPV4_HDR(pkt)->dst;
+
+		return net_ipv4_is_addr_mcast(dst) && net_context_get_ipv4_mcast_loop(ctx);
+	}
+#endif
+#if defined(CONFIG_NET_IPV6)
+	if (family == AF_INET6) {
+		const struct in6_addr *dst = (const struct in6_addr *)&NET_IPV6_HDR(pkt)->dst;
+
+		return net_ipv6_is_addr_mcast(dst) && net_context_get_ipv6_mcast_loop(ctx);
+	}
+#endif
+	return false;
+}
+#endif
+
+int net_try_send_data(struct net_pkt *pkt, k_timeout_t timeout)
 {
 	int status;
 	int ret;
@@ -392,6 +415,7 @@ int net_send_data(struct net_pkt *pkt)
 		 * we just silently drop the packet by returning 0.
 		 */
 		if (status == -ENOMSG) {
+			net_pkt_unref(pkt);
 			ret = 0;
 			goto err;
 		}
@@ -407,7 +431,36 @@ int net_send_data(struct net_pkt *pkt)
 		goto err;
 	}
 
-	if (net_if_send_data(net_pkt_iface(pkt), pkt) == NET_DROP) {
+#if defined(CONFIG_NET_IPV4) || defined(CONFIG_NET_IPV6)
+	if (process_multicast(pkt)) {
+		struct net_pkt *clone = net_pkt_clone(pkt, K_NO_WAIT);
+
+		if (clone != NULL) {
+			net_pkt_set_iface(clone, net_pkt_iface(pkt));
+			if (net_recv_data(net_pkt_iface(clone), clone) < 0) {
+				if (IS_ENABLED(CONFIG_NET_STATISTICS)) {
+					switch (net_pkt_family(pkt)) {
+#if defined(CONFIG_NET_IPV4)
+					case AF_INET:
+						net_stats_update_ipv4_sent(net_pkt_iface(pkt));
+						break;
+#endif
+#if defined(CONFIG_NET_IPV6)
+					case AF_INET6:
+						net_stats_update_ipv6_sent(net_pkt_iface(pkt));
+						break;
+#endif
+					}
+				}
+				net_pkt_unref(clone);
+			}
+		} else {
+			NET_DBG("Failed to clone multicast packet");
+		}
+	}
+#endif
+
+	if (net_if_try_send_data(net_pkt_iface(pkt), pkt, timeout) == NET_DROP) {
 		ret = -EIO;
 		goto err;
 	}
@@ -467,30 +520,46 @@ void net_process_rx_packet(struct net_pkt *pkt)
 
 static void net_queue_rx(struct net_if *iface, struct net_pkt *pkt)
 {
+	size_t len = net_pkt_get_len(pkt);
 	uint8_t prio = net_pkt_priority(pkt);
 	uint8_t tc = net_rx_priority2tc(prio);
 
-#if defined(CONFIG_NET_STATISTICS)
-	net_stats_update_tc_recv_pkt(iface, tc);
-	net_stats_update_tc_recv_bytes(iface, tc, net_pkt_get_len(pkt));
-	net_stats_update_tc_recv_priority(iface, tc, prio);
-#endif
-
 #if NET_TC_RX_COUNT > 1
 	NET_DBG("TC %d with prio %d pkt %p", tc, prio, pkt);
 #endif
 
-	if (NET_TC_RX_COUNT == 0) {
+	if ((IS_ENABLED(CONFIG_NET_TC_RX_SKIP_FOR_HIGH_PRIO) &&
+	     prio >= NET_PRIORITY_CA) || NET_TC_RX_COUNT == 0) {
 		net_process_rx_packet(pkt);
 	} else {
-		net_tc_submit_to_rx_queue(tc, pkt);
+		if (net_tc_submit_to_rx_queue(tc, pkt) != NET_OK) {
+			goto drop;
+		}
 	}
+
+	net_stats_update_tc_recv_pkt(iface, tc);
+	net_stats_update_tc_recv_bytes(iface, tc, len);
+	net_stats_update_tc_recv_priority(iface, tc, prio);
+	return;
+
+drop:
+	net_pkt_unref(pkt);
+	net_stats_update_tc_recv_dropped(iface, tc);
+	return;
 }
 
 /* Called by driver when a packet has been received */
 int net_recv_data(struct net_if *iface, struct net_pkt *pkt)
 {
 	int ret;
+#if defined(CONFIG_NET_DSA) && !defined(CONFIG_NET_DSA_DEPRECATED)
+	struct ethernet_context *eth_ctx = net_if_l2_data(iface);
+
+	/* DSA driver handles first to untag and to redirect to user interface. */
+	if (eth_ctx != NULL && (eth_ctx->dsa_port == DSA_CONDUIT_PORT)) {
+		iface = dsa_recv(iface, pkt);
+	}
+#endif
 
 	SYS_PORT_TRACING_FUNC_ENTER(net, recv_data, iface, pkt);
 
@@ -522,7 +591,10 @@ int net_recv_data(struct net_if *iface, struct net_pkt *pkt)
 	net_pkt_set_iface(pkt, iface);
 
 	if (!net_pkt_filter_recv_ok(pkt)) {
-		/* silently drop the packet */
+		/* Silently drop the packet, but update the statistics in order
+		 * to be able to monitor filter activity.
+		 */
+		net_stats_update_filter_rx_drop(net_pkt_iface(pkt));
 		net_pkt_unref(pkt);
 	} else {
 		net_queue_rx(iface, pkt);
@@ -562,9 +634,10 @@ static inline void l3_init(void)
 #else /* CONFIG_NET_NATIVE */
 #define l3_init(...)
 #define net_post_init(...)
-int net_send_data(struct net_pkt *pkt)
+int net_try_send_data(struct net_pkt *pkt, k_timeout_t timeout)
 {
 	ARG_UNUSED(pkt);
+	ARG_UNUSED(timeout);
 
 	return -ENOTSUP;
 }
diff --git a/subsys/net/ip/net_if.c b/subsys/net/ip/net_if.c
index c86a1d1b9d3..3a56b606e01 100644
--- a/subsys/net/ip/net_if.c
+++ b/subsys/net/ip/net_if.c
@@ -215,10 +215,7 @@ static void update_txtime_stats_detail(struct net_pkt *pkt,
 
 static bool net_if_tx(struct net_if *iface, struct net_pkt *pkt)
 {
-	struct net_linkaddr ll_dst = {
-		.addr = NULL
-	};
-	struct net_linkaddr_storage ll_dst_storage;
+	struct net_linkaddr ll_dst = { 0 };
 	struct net_context *context;
 	uint32_t create_time;
 	int status;
@@ -239,12 +236,10 @@ static bool net_if_tx(struct net_if *iface, struct net_pkt *pkt)
 	 * case packet is freed before callback is called.
 	 */
 	if (!sys_slist_is_empty(&link_callbacks)) {
-		if (net_linkaddr_set(&ll_dst_storage,
+		if (net_linkaddr_set(&ll_dst,
 				     net_pkt_lladdr_dst(pkt)->addr,
-				     net_pkt_lladdr_dst(pkt)->len) == 0) {
-			ll_dst.addr = ll_dst_storage.addr;
-			ll_dst.len = ll_dst_storage.len;
-			ll_dst.type = net_pkt_lladdr_dst(pkt)->type;
+				     net_pkt_lladdr_dst(pkt)->len) < 0) {
+			return false;
 		}
 	}
 
@@ -266,6 +261,10 @@ static bool net_if_tx(struct net_if *iface, struct net_pkt *pkt)
 		net_if_tx_lock(iface);
 		status = net_if_l2(iface)->send(iface, pkt);
 		net_if_tx_unlock(iface);
+		if (status < 0) {
+			NET_WARN("iface %d pkt %p send failure status %d",
+				 net_if_get_by_iface(iface), pkt, status);
+		}
 
 		if (IS_ENABLED(CONFIG_NET_PKT_TXTIME_STATS) ||
 		    IS_ENABLED(CONFIG_TRACING_NET_CORE)) {
@@ -303,7 +302,7 @@ static bool net_if_tx(struct net_if *iface, struct net_pkt *pkt)
 
 	} else {
 		/* Drop packet if interface is not up */
-		NET_WARN("iface %p is down", iface);
+		NET_WARN("iface %d is down", net_if_get_by_iface(iface));
 		status = -ENETDOWN;
 	}
 
@@ -320,7 +319,7 @@ static bool net_if_tx(struct net_if *iface, struct net_pkt *pkt)
 		net_context_send_cb(context, status);
 	}
 
-	if (ll_dst.addr) {
+	if (ll_dst.len > 0) {
 		net_if_call_link_cb(iface, &ll_dst, status);
 	}
 
@@ -342,47 +341,52 @@ void net_process_tx_packet(struct net_pkt *pkt)
 #endif
 }
 
-void net_if_queue_tx(struct net_if *iface, struct net_pkt *pkt)
+void net_if_try_queue_tx(struct net_if *iface, struct net_pkt *pkt, k_timeout_t timeout)
 {
 	if (!net_pkt_filter_send_ok(pkt)) {
-		/* silently drop the packet */
+		/* Silently drop the packet, but update the statistics in order
+		 * to be able to monitor filter activity.
+		 */
+		net_stats_update_filter_tx_drop(net_pkt_iface(pkt));
 		net_pkt_unref(pkt);
 		return;
 	}
 
+	size_t len = net_pkt_get_len(pkt);
 	uint8_t prio = net_pkt_priority(pkt);
 	uint8_t tc = net_tx_priority2tc(prio);
 
-	net_stats_update_tc_sent_pkt(iface, tc);
-	net_stats_update_tc_sent_bytes(iface, tc, net_pkt_get_len(pkt));
-	net_stats_update_tc_sent_priority(iface, tc, prio);
+#if NET_TC_TX_COUNT > 1
+	NET_DBG("TC %d with prio %d pkt %p", tc, prio, pkt);
+#endif
 
 	/* For highest priority packet, skip the TX queue and push directly to
 	 * the driver. Also if there are no TX queue/thread, push the packet
 	 * directly to the driver.
 	 */
-	if ((IS_ENABLED(CONFIG_NET_TC_SKIP_FOR_HIGH_PRIO) &&
+	if ((IS_ENABLED(CONFIG_NET_TC_TX_SKIP_FOR_HIGH_PRIO) &&
 	     prio >= NET_PRIORITY_CA) || NET_TC_TX_COUNT == 0) {
 		net_pkt_set_tx_stats_tick(pkt, k_cycle_get_32());
 
 		net_if_tx(net_pkt_iface(pkt), pkt);
-		return;
-	}
-
-#if NET_TC_TX_COUNT > 1
-	NET_DBG("TC %d with prio %d pkt %p", tc, prio, pkt);
-#endif
-
-#if defined(CONFIG_NET_POWER_MANAGEMENT)
-	iface->tx_pending++;
-#endif
-
-	if (!net_tc_submit_to_tx_queue(tc, pkt)) {
+	} else {
+		if (net_tc_try_submit_to_tx_queue(tc, pkt, timeout) != NET_OK) {
+			goto drop;
+		}
 #if defined(CONFIG_NET_POWER_MANAGEMENT)
-		iface->tx_pending--
+		iface->tx_pending++;
 #endif
-			;
 	}
+
+	net_stats_update_tc_sent_pkt(iface, tc);
+	net_stats_update_tc_sent_bytes(iface, tc, len);
+	net_stats_update_tc_sent_priority(iface, tc, prio);
+	return;
+
+drop:
+	net_pkt_unref(pkt);
+	net_stats_update_tc_sent_dropped(iface, tc);
+	return;
 }
 #endif /* CONFIG_NET_NATIVE */
 
@@ -434,7 +438,7 @@ static inline void init_iface(struct net_if *iface)
 
 	net_virtual_init(iface);
 
-	NET_DBG("On iface %p", iface);
+	NET_DBG("On iface %d", net_if_get_by_iface(iface));
 
 #ifdef CONFIG_USERSPACE
 	k_object_init(iface);
@@ -449,7 +453,8 @@ static inline void init_iface(struct net_if *iface)
 }
 
 #if defined(CONFIG_NET_NATIVE)
-enum net_verdict net_if_send_data(struct net_if *iface, struct net_pkt *pkt)
+enum net_verdict net_if_try_send_data(struct net_if *iface, struct net_pkt *pkt,
+				      k_timeout_t timeout)
 {
 	const struct net_l2 *l2;
 	struct net_context *context = net_pkt_context(pkt);
@@ -460,7 +465,7 @@ enum net_verdict net_if_send_data(struct net_if *iface, struct net_pkt *pkt)
 	if (!net_if_flag_is_set(iface, NET_IF_LOWER_UP) ||
 	    net_if_flag_is_set(iface, NET_IF_SUSPENDED)) {
 		/* Drop packet if interface is not up */
-		NET_WARN("iface %p is down", iface);
+		NET_WARN("iface %d is down", net_if_get_by_iface(iface));
 		verdict = NET_DROP;
 		status = -ENETDOWN;
 		goto done;
@@ -473,14 +478,15 @@ enum net_verdict net_if_send_data(struct net_if *iface, struct net_pkt *pkt)
 		l2 = net_if_l2(iface);
 		if (l2 == NULL) {
 			/* Offloaded ifaces may choose not to use an L2 at all. */
-			NET_WARN("no l2 for iface %p, discard pkt", iface);
+			NET_WARN("no l2 for iface %d, discard pkt", net_if_get_by_iface(iface));
 			verdict = NET_DROP;
 			goto done;
 		} else if (l2->send == NULL) {
 			/* Or, their chosen L2 (for example, OFFLOADED_NETDEV_L2)
 			 * might simply not implement send.
 			 */
-			NET_WARN("l2 for iface %p cannot send, discard pkt", iface);
+			NET_WARN("l2 for iface %d cannot send, discard pkt",
+				 net_if_get_by_iface(iface));
 			verdict = NET_DROP;
 			goto done;
 		}
@@ -492,9 +498,10 @@ enum net_verdict net_if_send_data(struct net_if *iface, struct net_pkt *pkt)
 	 * https://github.com/zephyrproject-rtos/zephyr/issues/3111
 	 */
 	if (!net_if_flag_is_set(iface, NET_IF_POINTOPOINT) &&
-	    !net_pkt_lladdr_src(pkt)->addr) {
-		net_pkt_lladdr_src(pkt)->addr = net_pkt_lladdr_if(pkt)->addr;
-		net_pkt_lladdr_src(pkt)->len = net_pkt_lladdr_if(pkt)->len;
+	    net_pkt_lladdr_src(pkt)->len == 0) {
+		(void)net_linkaddr_set(net_pkt_lladdr_src(pkt),
+				       net_pkt_lladdr_if(pkt)->addr,
+				       net_pkt_lladdr_if(pkt)->len);
 	}
 
 #if defined(CONFIG_NET_LOOPBACK)
@@ -506,10 +513,10 @@ enum net_verdict net_if_send_data(struct net_if *iface, struct net_pkt *pkt)
 	}
 #endif
 
-	/* Bypass the IP stack with SOCK_RAW/IPPROTO_RAW sockets */
-	if (IS_ENABLED(CONFIG_NET_SOCKETS_PACKET) &&
-	    context && net_context_get_type(context) == SOCK_RAW &&
-	    net_context_get_proto(context) == IPPROTO_RAW) {
+	/* Bypass the IP stack with AF_INET(6)/SOCK_RAW */
+	if (context && net_context_get_type(context) == SOCK_RAW &&
+	    (net_context_get_family(context) == AF_INET ||
+	     net_context_get_family(context) == AF_INET6)) {
 		goto done;
 	}
 
@@ -543,12 +550,12 @@ enum net_verdict net_if_send_data(struct net_if *iface, struct net_pkt *pkt)
 			net_context_send_cb(context, status);
 		}
 
-		if (dst->addr) {
+		if (dst->len > 0) {
 			net_if_call_link_cb(iface, dst, status);
 		}
 	} else if (verdict == NET_OK) {
 		/* Packet is ready to be sent by L2, let's queue */
-		net_if_queue_tx(iface, pkt);
+		net_if_try_queue_tx(iface, pkt, timeout);
 	}
 
 	return verdict;
@@ -632,6 +639,9 @@ struct net_if *net_if_get_default(void)
 #if defined(CONFIG_NET_DEFAULT_IF_PPP)
 	iface = net_if_get_first_by_type(&NET_L2_GET_NAME(PPP));
 #endif
+#if defined(CONFIG_NET_DEFAULT_IF_OFFLOADED_NETDEV)
+	iface = net_if_get_first_by_type(&NET_L2_GET_NAME(OFFLOADED_NETDEV));
+#endif
 #if defined(CONFIG_NET_DEFAULT_IF_UP)
 	iface = net_if_get_first_up();
 #endif
@@ -1293,21 +1303,25 @@ void net_if_ipv6_start_dad(struct net_if *iface,
 
 		ifaddr->dad_count = 1U;
 
-		if (!net_ipv6_start_dad(iface, ifaddr)) {
-			ifaddr->dad_start = k_uptime_get_32();
-			ifaddr->ifindex = net_if_get_by_iface(iface);
+		if (net_ipv6_start_dad(iface, ifaddr) != 0) {
+			NET_ERR("Interface %p failed to send DAD query for %s",
+				iface,
+				net_sprint_ipv6_addr(&ifaddr->address.in6_addr));
+		}
 
-			k_mutex_lock(&lock, K_FOREVER);
-			sys_slist_find_and_remove(&active_dad_timers,
-						  &ifaddr->dad_node);
-			sys_slist_append(&active_dad_timers, &ifaddr->dad_node);
-			k_mutex_unlock(&lock);
+		ifaddr->dad_start = k_uptime_get_32();
+		ifaddr->ifindex = net_if_get_by_iface(iface);
 
-			/* FUTURE: use schedule, not reschedule. */
-			if (!k_work_delayable_remaining_get(&dad_timer)) {
-				k_work_reschedule(&dad_timer,
-						  K_MSEC(DAD_TIMEOUT));
-			}
+		k_mutex_lock(&lock, K_FOREVER);
+		sys_slist_find_and_remove(&active_dad_timers,
+					  &ifaddr->dad_node);
+		sys_slist_append(&active_dad_timers, &ifaddr->dad_node);
+		k_mutex_unlock(&lock);
+
+		/* FUTURE: use schedule, not reschedule. */
+		if (!k_work_delayable_remaining_get(&dad_timer)) {
+			k_work_reschedule(&dad_timer,
+					  K_MSEC(DAD_TIMEOUT));
 		}
 	} else {
 		NET_DBG("Interface %p is down, starting DAD for %s later.",
@@ -1318,14 +1332,15 @@ void net_if_ipv6_start_dad(struct net_if *iface,
 
 void net_if_start_dad(struct net_if *iface)
 {
-	struct net_if_addr *ifaddr;
+	struct net_if_addr *ifaddr, *next;
 	struct net_if_ipv6 *ipv6;
+	sys_slist_t dad_needed;
 	struct in6_addr addr = { };
 	int ret;
 
 	net_if_lock(iface);
 
-	NET_DBG("Starting DAD for iface %p", iface);
+	NET_DBG("Starting DAD for iface %d", net_if_get_by_iface(iface));
 
 	ret = net_if_config_ipv6_get(iface, &ipv6);
 	if (ret < 0) {
@@ -1369,6 +1384,8 @@ void net_if_start_dad(struct net_if *iface)
 	/* Start DAD for all the addresses that were added earlier when
 	 * the interface was down.
 	 */
+	sys_slist_init(&dad_needed);
+
 	ARRAY_FOR_EACH(ipv6->unicast, i) {
 		if (!ipv6->unicast[i].is_used ||
 		    ipv6->unicast[i].address.family != AF_INET6 ||
@@ -1378,9 +1395,21 @@ void net_if_start_dad(struct net_if *iface)
 			continue;
 		}
 
-		net_if_ipv6_start_dad(iface, &ipv6->unicast[i]);
+		sys_slist_prepend(&dad_needed, &ipv6->unicast[i].dad_need_node);
+	}
+
+	net_if_unlock(iface);
+
+	/* Start DAD for all the addresses without holding the iface lock
+	 * to avoid any possible mutex deadlock issues.
+	 */
+	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&dad_needed,
+					  ifaddr, next, dad_need_node) {
+		net_if_ipv6_start_dad(iface, ifaddr);
 	}
 
+	return;
+
 out:
 	net_if_unlock(iface);
 }
@@ -1428,7 +1457,10 @@ void net_if_ipv6_dad_failed(struct net_if *iface, const struct in6_addr *addr)
 	net_if_ipv6_addr_rm(iface, addr);
 
 	if (IS_ENABLED(CONFIG_NET_IPV6_PE) && iface->pe_enabled) {
+		net_if_unlock(iface);
+
 		net_ipv6_pe_start(iface, addr, timeout, preferred_lifetime);
+		return;
 	}
 
 out:
@@ -1442,12 +1474,7 @@ static inline void iface_ipv6_dad_init(void)
 }
 
 #else
-static inline void net_if_ipv6_start_dad(struct net_if *iface,
-					 struct net_if_addr *ifaddr)
-{
-	ifaddr->addr_state = NET_ADDR_PREFERRED;
-}
-
+#define net_if_ipv6_start_dad(...)
 #define iface_ipv6_dad_init(...)
 #endif /* CONFIG_NET_IPV6_DAD */
 
@@ -1506,8 +1533,8 @@ static void rs_timeout(struct k_work *work)
 		}
 
 		if (iface) {
-			NET_DBG("RS no respond iface %p count %d",
-				iface, ipv6->rs_count);
+			NET_DBG("RS no respond iface %d count %d",
+				net_if_get_by_iface(iface), ipv6->rs_count);
 			if (ipv6->rs_count < RS_COUNT) {
 				net_if_start_rs(iface);
 			}
@@ -1532,13 +1559,19 @@ void net_if_start_rs(struct net_if *iface)
 		goto out;
 	}
 
-	NET_DBG("Starting ND/RS for iface %p", iface);
+	net_if_unlock(iface);
+
+	NET_DBG("Starting ND/RS for iface %d", net_if_get_by_iface(iface));
 
 	if (!net_ipv6_start_rs(iface)) {
 		ipv6->rs_start = k_uptime_get_32();
 
 		k_mutex_lock(&lock, K_FOREVER);
+
+		/* Make sure that the RS timer is not in the list twice */
+		(void)sys_slist_find_and_remove(&active_rs_timers, &ipv6->rs_node);
 		sys_slist_append(&active_rs_timers, &ipv6->rs_node);
+
 		k_mutex_unlock(&lock);
 
 		/* FUTURE: use schedule, not reschedule. */
@@ -1547,6 +1580,7 @@ void net_if_start_rs(struct net_if *iface)
 		}
 	}
 
+	return;
 out:
 	net_if_unlock(iface);
 }
@@ -1562,7 +1596,7 @@ void net_if_stop_rs(struct net_if *iface)
 		goto out;
 	}
 
-	NET_DBG("Stopping ND/RS for iface %p", iface);
+	NET_DBG("Stopping ND/RS for iface %d", net_if_get_by_iface(iface));
 
 	k_mutex_lock(&lock, K_FOREVER);
 	sys_slist_find_and_remove(&active_rs_timers, &ipv6->rs_node);
@@ -1611,7 +1645,9 @@ void net_if_nbr_reachability_hint(struct net_if *iface, const struct in6_addr *i
  */
 static void rejoin_ipv6_mcast_groups(struct net_if *iface)
 {
+	struct net_if_mcast_addr *ifaddr, *next;
 	struct net_if_ipv6 *ipv6;
+	sys_slist_t rejoin_needed;
 
 	net_if_lock(iface);
 
@@ -1633,27 +1669,41 @@ static void rejoin_ipv6_mcast_groups(struct net_if *iface)
 		join_mcast_nodes(iface, &ipv6->unicast[i].address.in6_addr);
 	}
 
+	sys_slist_init(&rejoin_needed);
+
 	/* Rejoin any mcast address present on the interface, but marked as not joined. */
 	ARRAY_FOR_EACH(ipv6->mcast, i) {
-		int ret;
-
 		if (!ipv6->mcast[i].is_used ||
 		    net_if_ipv6_maddr_is_joined(&ipv6->mcast[i])) {
 			continue;
 		}
 
-		ret = net_ipv6_mld_join(iface, &ipv6->mcast[i].address.in6_addr);
+		sys_slist_prepend(&rejoin_needed, &ipv6->mcast[i].rejoin_node);
+	}
+
+	net_if_unlock(iface);
+
+	/* Start DAD for all the addresses without holding the iface lock
+	 * to avoid any possible mutex deadlock issues.
+	 */
+	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&rejoin_needed,
+					  ifaddr, next, rejoin_node) {
+		int ret;
+
+		ret = net_ipv6_mld_join(iface, &ifaddr->address.in6_addr);
 		if (ret < 0) {
 			NET_ERR("Cannot join mcast address %s for %d (%d)",
-				net_sprint_ipv6_addr(&ipv6->mcast[i].address.in6_addr),
+				net_sprint_ipv6_addr(&ifaddr->address.in6_addr),
 				net_if_get_by_iface(iface), ret);
 		} else {
 			NET_DBG("Rejoined mcast address %s for %d",
-				net_sprint_ipv6_addr(&ipv6->mcast[i].address.in6_addr),
+				net_sprint_ipv6_addr(&ifaddr->address.in6_addr),
 				net_if_get_by_iface(iface));
 		}
 	}
 
+	return;
+
 out:
 	net_if_unlock(iface);
 }
@@ -1770,11 +1820,7 @@ static void address_start_timer(struct net_if_addr *ifaddr, uint32_t vlifetime)
 }
 #else /* CONFIG_NET_NATIVE_IPV6 */
 #define address_start_timer(...)
-static inline void net_if_ipv6_start_dad(struct net_if *iface,
-					 struct net_if_addr *ifaddr)
-{
-	ifaddr->addr_state = NET_ADDR_PREFERRED;
-}
+#define net_if_ipv6_start_dad(...)
 #define join_mcast_nodes(...)
 #endif /* CONFIG_NET_NATIVE_IPV6 */
 
@@ -1924,6 +1970,7 @@ static inline void net_if_addr_init(struct net_if_addr *ifaddr,
 				    uint32_t vlifetime)
 {
 	ifaddr->is_used = true;
+	ifaddr->is_added = true;
 	ifaddr->is_temporary = false;
 	ifaddr->address.family = AF_INET6;
 	ifaddr->addr_type = addr_type;
@@ -1953,6 +2000,7 @@ struct net_if_addr *net_if_ipv6_addr_add(struct net_if *iface,
 {
 	struct net_if_addr *ifaddr = NULL;
 	struct net_if_ipv6 *ipv6;
+	bool do_dad = false;
 
 	net_if_lock(iface);
 
@@ -1962,6 +2010,17 @@ struct net_if_addr *net_if_ipv6_addr_add(struct net_if *iface,
 
 	ifaddr = ipv6_addr_find(iface, addr);
 	if (ifaddr) {
+		/* Address already exists, just return it but update ref count
+		 * if it was not updated. This could happen if the address was
+		 * added and then removed but for example an active connection
+		 * was still using it. In this case we must update the ref count
+		 * so that the address is not removed if the connection is closed.
+		 */
+		if (!ifaddr->is_added) {
+			atomic_inc(&ifaddr->atomic_ref);
+			ifaddr->is_added = true;
+		}
+
 		goto out;
 	}
 
@@ -1978,23 +2037,12 @@ struct net_if_addr *net_if_ipv6_addr_add(struct net_if *iface,
 			net_sprint_ipv6_addr(addr),
 			net_addr_type2str(addr_type));
 
-		if (!(l2_flags_get(iface) & NET_L2_POINT_TO_POINT) &&
+		if (IS_ENABLED(CONFIG_NET_IPV6_DAD) &&
+		    !(l2_flags_get(iface) & NET_L2_POINT_TO_POINT) &&
 		    !net_ipv6_is_addr_loopback(addr) &&
 		    !net_if_flag_is_set(iface, NET_IF_IPV6_NO_ND)) {
-			/* RFC 4862 5.4.2
-			 * Before sending a Neighbor Solicitation, an interface
-			 * MUST join the all-nodes multicast address and the
-			 * solicited-node multicast address of the tentative
-			 * address.
-			 */
-			/* The allnodes multicast group is only joined once as
-			 * net_ipv6_mld_join() checks if we have already
-			 * joined.
-			 */
-			join_mcast_nodes(iface,
-					 &ipv6->unicast[i].address.in6_addr);
-
-			net_if_ipv6_start_dad(iface, &ipv6->unicast[i]);
+			/* The groups are joined without locks held */
+			do_dad = true;
 		} else {
 			/* If DAD is not done for point-to-point links, then
 			 * the address is usable immediately.
@@ -2008,9 +2056,29 @@ struct net_if_addr *net_if_ipv6_addr_add(struct net_if *iface,
 			sizeof(struct in6_addr));
 
 		ifaddr = &ipv6->unicast[i];
-		goto out;
+		break;
+	}
+
+	net_if_unlock(iface);
+
+	if (ifaddr != NULL && do_dad) {
+		/* RFC 4862 5.4.2
+		 * Before sending a Neighbor Solicitation, an interface
+		 * MUST join the all-nodes multicast address and the
+		 * solicited-node multicast address of the tentative
+		 * address.
+		 */
+		/* The allnodes multicast group is only joined once as
+		 * net_ipv6_mld_join() checks if we have already
+		 * joined.
+		 */
+		join_mcast_nodes(iface, &ifaddr->address.in6_addr);
+
+		net_if_ipv6_start_dad(iface, ifaddr);
 	}
 
+	return ifaddr;
+
 out:
 	net_if_unlock(iface);
 
@@ -2019,6 +2087,7 @@ struct net_if_addr *net_if_ipv6_addr_add(struct net_if *iface,
 
 bool net_if_ipv6_addr_rm(struct net_if *iface, const struct in6_addr *addr)
 {
+	struct net_if_addr *ifaddr;
 	struct net_if_ipv6 *ipv6;
 	bool result = true;
 	int ret;
@@ -2035,11 +2104,12 @@ bool net_if_ipv6_addr_rm(struct net_if *iface, const struct in6_addr *addr)
 		goto out;
 	}
 
-	ret = net_if_addr_unref(iface, AF_INET6, addr);
+	ret = net_if_addr_unref(iface, AF_INET6, addr, &ifaddr);
 	if (ret > 0) {
 		NET_DBG("Address %s still in use (ref %d)",
 			net_sprint_ipv6_addr(addr), ret);
 		result = false;
+		ifaddr->is_added = false;
 		goto out;
 	} else if (ret < 0) {
 		NET_DBG("Address %s not found (%d)",
@@ -3072,6 +3142,29 @@ static struct in6_addr *net_if_ipv6_get_best_match(struct net_if *iface,
 			continue;
 		}
 
+		/* This is a dirty hack until we have proper IPv6 routing.
+		 * Without this the IPv6 packets might go to VPN interface for
+		 * subnets that are not on the same subnet as the VPN interface
+		 * which typically is not desired.
+		 * TODO: Implement IPv6 routing support and remove this hack.
+		 */
+		if (IS_ENABLED(CONFIG_NET_VPN)) {
+			/* For the VPN interface, we need to check if
+			 * address matches exactly the address of the interface.
+			 */
+			if (net_if_l2(iface) == &NET_L2_GET_NAME(VIRTUAL) &&
+			    net_virtual_get_iface_capabilities(iface) == VIRTUAL_INTERFACE_VPN) {
+				/* FIXME: Do not hard code the prefix length */
+				if (!net_ipv6_is_prefix(
+					    (const uint8_t *)&ipv6->unicast[i].address.in6_addr,
+					    (const uint8_t *)dst,
+					    64)) {
+					/* Skip this address as it is no match */
+					continue;
+				}
+			}
+		}
+
 		len = get_diff_ipv6(dst, &ipv6->unicast[i].address.in6_addr);
 		if (len >= prefix_len) {
 			len = prefix_len;
@@ -3217,7 +3310,8 @@ const struct in6_addr *net_if_ipv6_select_src_addr(struct net_if *dst_iface,
 						IPV6_PREFER_SRC_PUBTMP_DEFAULT);
 }
 
-struct net_if *net_if_ipv6_select_src_iface(const struct in6_addr *dst)
+struct net_if *net_if_ipv6_select_src_iface_addr(const struct in6_addr *dst,
+						 const struct in6_addr **src_addr)
 {
 	struct net_if *iface = NULL;
 	const struct in6_addr *src;
@@ -3227,6 +3321,10 @@ struct net_if *net_if_ipv6_select_src_iface(const struct in6_addr *dst)
 		net_if_ipv6_addr_lookup(src, &iface);
 	}
 
+	if (src_addr != NULL) {
+		*src_addr = src;
+	}
+
 	if (iface == NULL) {
 		iface = net_if_get_default();
 	}
@@ -3234,6 +3332,11 @@ struct net_if *net_if_ipv6_select_src_iface(const struct in6_addr *dst)
 	return iface;
 }
 
+struct net_if *net_if_ipv6_select_src_iface(const struct in6_addr *dst)
+{
+	return net_if_ipv6_select_src_iface_addr(dst, NULL);
+}
+
 #if defined(CONFIG_NET_NATIVE_IPV6)
 
 uint32_t net_if_ipv6_calc_reachable_time(struct net_if_ipv6 *ipv6)
@@ -3289,6 +3392,8 @@ static void iface_ipv6_stop(struct net_if *iface)
 	IF_ENABLED(CONFIG_NET_IPV6_IID_STABLE, (ipv6->network_counter++));
 	IF_ENABLED(CONFIG_NET_IPV6_IID_STABLE, (ipv6->iid = NULL));
 
+	net_if_stop_rs(iface);
+
 	/* Remove all autoconf addresses */
 	ARRAY_FOR_EACH(ipv6->unicast, i) {
 		if (ipv6->unicast[i].is_used &&
@@ -3542,7 +3647,8 @@ bool net_if_ipv4_is_addr_bcast(struct net_if *iface,
 	return ret;
 }
 
-struct net_if *net_if_ipv4_select_src_iface(const struct in_addr *dst)
+struct net_if *net_if_ipv4_select_src_iface_addr(const struct in_addr *dst,
+						 const struct in_addr **src_addr)
 {
 	struct net_if *selected = NULL;
 	const struct in_addr *src;
@@ -3556,9 +3662,18 @@ struct net_if *net_if_ipv4_select_src_iface(const struct in_addr *dst)
 		selected = net_if_get_default();
 	}
 
+	if (src_addr != NULL) {
+		*src_addr = src;
+	}
+
 	return selected;
 }
 
+struct net_if *net_if_ipv4_select_src_iface(const struct in_addr *dst)
+{
+	return net_if_ipv4_select_src_iface_addr(dst, NULL);
+}
+
 static uint8_t get_diff_ipv4(const struct in_addr *src,
 			  const struct in_addr *dst)
 {
@@ -3601,6 +3716,29 @@ static struct in_addr *net_if_ipv4_get_best_match(struct net_if *iface,
 			continue;
 		}
 
+		/* This is a dirty hack until we have proper IPv4 routing.
+		 * Without this the IPv4 packets might go to VPN interface for
+		 * subnets that are not on the same subnet as the VPN interface
+		 * which typically is not desired.
+		 * TODO: Implement IPv4 routing support and remove this hack.
+		 */
+		if (IS_ENABLED(CONFIG_NET_VPN)) {
+			/* For the VPN interface, we need to check if
+			 * address matches exactly the address of the interface.
+			 */
+			if (net_if_l2(iface) == &NET_L2_GET_NAME(VIRTUAL) &&
+			    net_virtual_get_iface_capabilities(iface) == VIRTUAL_INTERFACE_VPN) {
+				subnet.s_addr = ipv4->unicast[i].ipv4.address.in_addr.s_addr &
+					ipv4->unicast[i].netmask.s_addr;
+
+				if (subnet.s_addr !=
+				    (dst->s_addr & ipv4->unicast[i].netmask.s_addr)) {
+					/* Skip this address as it is no match */
+					continue;
+				}
+			}
+		}
+
 		subnet.s_addr = ipv4->unicast[i].ipv4.address.in_addr.s_addr &
 				ipv4->unicast[i].netmask.s_addr;
 		len = get_diff_ipv4(dst, &subnet);
@@ -4226,9 +4364,9 @@ void net_if_ipv4_start_acd(struct net_if *iface, struct net_if_addr *ifaddr)
 			net_sprint_ipv4_addr(&ifaddr->address.in_addr));
 
 		if (net_ipv4_acd_start(iface, ifaddr) != 0) {
-			NET_DBG("Failed to start ACD for %s on iface %p.",
+			NET_DBG("Failed to start ACD for %s on iface %d.",
 				net_sprint_ipv4_addr(&ifaddr->address.in_addr),
-				iface);
+				net_if_get_by_iface(iface));
 
 			/* Just act as if no conflict was detected. */
 			net_if_ipv4_acd_succeeded(iface, ifaddr);
@@ -4241,12 +4379,14 @@ void net_if_ipv4_start_acd(struct net_if *iface, struct net_if_addr *ifaddr)
 
 void net_if_start_acd(struct net_if *iface)
 {
+	struct net_if_addr *ifaddr, *next;
 	struct net_if_ipv4 *ipv4;
+	sys_slist_t acd_needed;
 	int ret;
 
 	net_if_lock(iface);
 
-	NET_DBG("Starting ACD for iface %p", iface);
+	NET_DBG("Starting ACD for iface %d", net_if_get_by_iface(iface));
 
 	ret = net_if_config_ipv4_get(iface, &ipv4);
 	if (ret < 0) {
@@ -4263,6 +4403,11 @@ void net_if_start_acd(struct net_if *iface)
 
 	ipv4->conflict_cnt = 0;
 
+	/* Start ACD for all the addresses that were added earlier when
+	 * the interface was down.
+	 */
+	sys_slist_init(&acd_needed);
+
 	/* Start ACD for all the addresses that were added earlier when
 	 * the interface was down.
 	 */
@@ -4274,20 +4419,26 @@ void net_if_start_acd(struct net_if *iface)
 			continue;
 		}
 
-		net_if_ipv4_start_acd(iface, &ipv4->unicast[i].ipv4);
+		sys_slist_prepend(&acd_needed, &ipv4->unicast[i].ipv4.acd_need_node);
+	}
+
+	net_if_unlock(iface);
+
+	/* Start ACD for all the addresses without holding the iface lock
+	 * to avoid any possible mutex deadlock issues.
+	 */
+	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&acd_needed,
+					  ifaddr, next, acd_need_node) {
+		net_if_ipv4_start_acd(iface, ifaddr);
 	}
 
+	return;
+
 out:
 	net_if_unlock(iface);
 }
 #else
-void net_if_ipv4_start_acd(struct net_if *iface, struct net_if_addr *ifaddr)
-{
-	ARG_UNUSED(iface);
-
-	ifaddr->addr_state = NET_ADDR_PREFERRED;
-}
-
+#define net_if_ipv4_start_acd(...)
 #define net_if_start_acd(...)
 #endif /* CONFIG_NET_IPV4_ACD */
 
@@ -4311,6 +4462,17 @@ struct net_if_addr *net_if_ipv4_addr_add(struct net_if *iface,
 	ifaddr = ipv4_addr_find(iface, addr);
 	if (ifaddr) {
 		/* TODO: should set addr_type/vlifetime */
+		/* Address already exists, just return it but update ref count
+		 * if it was not updated. This could happen if the address was
+		 * added and then removed but for example an active connection
+		 * was still using it. In this case we must update the ref count
+		 * so that the address is not removed if the connection is closed.
+		 */
+		if (!ifaddr->is_added) {
+			atomic_inc(&ifaddr->atomic_ref);
+			ifaddr->is_added = true;
+		}
+
 		goto out;
 	}
 
@@ -4333,6 +4495,7 @@ struct net_if_addr *net_if_ipv4_addr_add(struct net_if *iface,
 
 	if (ifaddr) {
 		ifaddr->is_used = true;
+		ifaddr->is_added = true;
 		ifaddr->address.family = AF_INET;
 		ifaddr->address.in_addr.s4_addr32[0] =
 						addr->s4_addr32[0];
@@ -4356,9 +4519,11 @@ struct net_if_addr *net_if_ipv4_addr_add(struct net_if *iface,
 			net_sprint_ipv4_addr(addr),
 			net_addr_type2str(addr_type));
 
-		if (!(l2_flags_get(iface) & NET_L2_POINT_TO_POINT) &&
+		if (IS_ENABLED(CONFIG_NET_IPV4_ACD) &&
+		    !(l2_flags_get(iface) & NET_L2_POINT_TO_POINT) &&
 		    !net_ipv4_is_addr_loopback(addr)) {
-			net_if_ipv4_start_acd(iface, ifaddr);
+			/* ACD is started after the lock is released. */
+			;
 		} else {
 			ifaddr->addr_state = NET_ADDR_PREFERRED;
 		}
@@ -4368,7 +4533,12 @@ struct net_if_addr *net_if_ipv4_addr_add(struct net_if *iface,
 		net_mgmt_event_notify_with_info(NET_EVENT_IPV4_ADDR_ADD, iface,
 						&ifaddr->address.in_addr,
 						sizeof(struct in_addr));
-		goto out;
+
+		net_if_unlock(iface);
+
+		net_if_ipv4_start_acd(iface, ifaddr);
+
+		return ifaddr;
 	}
 
 out:
@@ -4379,6 +4549,7 @@ struct net_if_addr *net_if_ipv4_addr_add(struct net_if *iface,
 
 bool net_if_ipv4_addr_rm(struct net_if *iface, const struct in_addr *addr)
 {
+	struct net_if_addr *ifaddr;
 	struct net_if_ipv4 *ipv4;
 	bool result = true;
 	int ret;
@@ -4395,11 +4566,12 @@ bool net_if_ipv4_addr_rm(struct net_if *iface, const struct in_addr *addr)
 		goto out;
 	}
 
-	ret = net_if_addr_unref(iface, AF_INET, addr);
+	ret = net_if_addr_unref(iface, AF_INET, addr, &ifaddr);
 	if (ret > 0) {
 		NET_DBG("Address %s still in use (ref %d)",
 			net_sprint_ipv4_addr(addr), ret);
 		result = false;
+		ifaddr->is_added = false;
 		goto out;
 	} else if (ret < 0) {
 		NET_DBG("Address %s not found (%d)",
@@ -4846,7 +5018,9 @@ static void iface_ipv4_start(struct net_if *iface)
  */
 static void rejoin_ipv4_mcast_groups(struct net_if *iface)
 {
+	struct net_if_mcast_addr *ifaddr, *next;
 	struct net_if_ipv4 *ipv4;
+	sys_slist_t rejoin_needed;
 
 	net_if_lock(iface);
 
@@ -4858,27 +5032,37 @@ static void rejoin_ipv4_mcast_groups(struct net_if *iface)
 		goto out;
 	}
 
+	sys_slist_init(&rejoin_needed);
+
 	/* Rejoin any mcast address present on the interface, but marked as not joined. */
 	ARRAY_FOR_EACH(ipv4->mcast, i) {
-		int ret;
-
 		if (!ipv4->mcast[i].is_used ||
 		    net_if_ipv4_maddr_is_joined(&ipv4->mcast[i])) {
 			continue;
 		}
 
-		ret = net_ipv4_igmp_join(iface, &ipv4->mcast[i].address.in_addr, NULL);
+		sys_slist_prepend(&rejoin_needed, &ipv4->mcast[i].rejoin_node);
+	}
+
+	net_if_unlock(iface);
+
+	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&rejoin_needed, ifaddr, next, rejoin_node) {
+		int ret;
+
+		ret = net_ipv4_igmp_join(iface, &ifaddr->address.in_addr, NULL);
 		if (ret < 0) {
 			NET_ERR("Cannot join mcast address %s for %d (%d)",
-				net_sprint_ipv4_addr(&ipv4->mcast[i].address.in_addr),
+				net_sprint_ipv4_addr(&ifaddr->address.in_addr),
 				net_if_get_by_iface(iface), ret);
 		} else {
 			NET_DBG("Rejoined mcast address %s for %d",
-				net_sprint_ipv4_addr(&ipv4->mcast[i].address.in_addr),
+				net_sprint_ipv4_addr(&ifaddr->address.in_addr),
 				net_if_get_by_iface(iface));
 		}
 	}
 
+	return;
+
 out:
 	net_if_unlock(iface);
 }
@@ -5094,8 +5278,13 @@ static void remove_ipv6_ifaddr(struct net_if *iface,
 #if defined(CONFIG_NET_IPV6_DAD)
 	if (!net_if_flag_is_set(iface, NET_IF_IPV6_NO_ND)) {
 		k_mutex_lock(&lock, K_FOREVER);
-		sys_slist_find_and_remove(&active_dad_timers,
-					  &ifaddr->dad_node);
+		if (sys_slist_find_and_remove(&active_dad_timers,
+					      &ifaddr->dad_node)) {
+			/* Addreess with active DAD timer would still have
+			 * stale entry in the neighbor cache.
+			 */
+			net_ipv6_nbr_rm(iface, &ifaddr->address.in6_addr);
+		}
 		k_mutex_unlock(&lock);
 	}
 #endif
@@ -5210,11 +5399,13 @@ struct net_if_addr *net_if_addr_ref(struct net_if *iface,
 int net_if_addr_unref_debug(struct net_if *iface,
 			    sa_family_t family,
 			    const void *addr,
+			    struct net_if_addr **ret_ifaddr,
 			    const char *caller, int line)
 #else
 int net_if_addr_unref(struct net_if *iface,
 		      sa_family_t family,
-		      const void *addr)
+		      const void *addr,
+		      struct net_if_addr **ret_ifaddr)
 #endif /* NET_LOG_LEVEL >= LOG_LEVEL_DBG */
 {
 	struct net_if_addr *ifaddr;
@@ -5268,6 +5459,10 @@ int net_if_addr_unref(struct net_if *iface,
 #endif
 
 	if (ref > 1) {
+		if (ret_ifaddr) {
+			*ret_ifaddr = ifaddr;
+		}
+
 		return ref - 1;
 	}
 
@@ -5482,9 +5677,8 @@ static void notify_iface_down(struct net_if *iface)
 	}
 }
 
-static inline const char *net_if_oper_state2str(enum net_if_oper_state state)
+const char *net_if_oper_state2str(enum net_if_oper_state state)
 {
-#if CONFIG_NET_IF_LOG_LEVEL >= LOG_LEVEL_DBG
 	switch (state) {
 	case NET_IF_OPER_UNKNOWN:
 		return "UNKNOWN";
@@ -5505,11 +5699,6 @@ static inline const char *net_if_oper_state2str(enum net_if_oper_state state)
 	}
 
 	return "<invalid>";
-#else
-	ARG_UNUSED(state);
-
-	return "";
-#endif /* CONFIG_NET_IF_LOG_LEVEL >= LOG_LEVEL_DBG */
 }
 
 static void update_operational_state(struct net_if *iface)
@@ -5653,7 +5842,7 @@ int net_if_down(struct net_if *iface)
 {
 	int status = 0;
 
-	NET_DBG("iface %p", iface);
+	NET_DBG("iface %d", net_if_get_by_iface(iface));
 
 	net_if_lock(iface);
 
diff --git a/subsys/net/ip/net_pkt.c b/subsys/net/ip/net_pkt.c
index 675ca9d2b34..21a28e2d66e 100644
--- a/subsys/net/ip/net_pkt.c
+++ b/subsys/net/ip/net_pkt.c
@@ -1336,6 +1336,16 @@ int net_pkt_alloc_buffer_with_reserve(struct net_pkt *pkt,
 	return 0;
 }
 
+static bool is_pkt_tx(struct net_pkt *pkt)
+{
+#if defined(CONFIG_NET_CONTEXT_NET_PKT_POOL)
+	if ((pkt->context != NULL) && (get_tx_slab(pkt->context) != NULL)) {
+		return pkt->slab == get_tx_slab(pkt->context);
+	}
+#endif
+	return pkt->slab == &tx_pkts;
+}
+
 #if NET_LOG_LEVEL >= LOG_LEVEL_DBG
 int net_pkt_alloc_buffer_debug(struct net_pkt *pkt,
 			       size_t size,
@@ -1363,7 +1373,7 @@ int net_pkt_alloc_buffer(struct net_pkt *pkt,
 
 	iface = net_pkt_iface(pkt);
 
-	if (iface != NULL && net_if_l2(iface)->alloc != NULL) {
+	if (iface != NULL && is_pkt_tx(pkt) && net_if_l2(iface)->alloc != NULL) {
 		ret = net_if_l2(iface)->alloc(iface, pkt, size, proto, timeout);
 		if (ret != -ENOTSUP) {
 			return ret;
@@ -1997,49 +2007,6 @@ int net_pkt_copy(struct net_pkt *pkt_dst,
 	return 0;
 }
 
-static int32_t net_pkt_find_offset(struct net_pkt *pkt, uint8_t *ptr)
-{
-	struct net_buf *buf;
-	uint32_t ret = -EINVAL;
-	uint16_t offset;
-
-	if (!ptr || !pkt || !pkt->buffer) {
-		return ret;
-	}
-
-	offset = 0U;
-	buf = pkt->buffer;
-
-	while (buf) {
-		if (buf->data <= ptr && ptr < (buf->data + buf->len)) {
-			ret = offset + (ptr - buf->data);
-			break;
-		}
-		offset += buf->len;
-		buf = buf->frags;
-	}
-
-	return ret;
-}
-
-static void clone_pkt_lladdr(struct net_pkt *pkt, struct net_pkt *clone_pkt,
-			     struct net_linkaddr *lladdr)
-{
-	int32_t ll_addr_offset;
-
-	if (!lladdr->addr) {
-		return;
-	}
-
-	ll_addr_offset = net_pkt_find_offset(pkt, lladdr->addr);
-
-	if (ll_addr_offset >= 0) {
-		net_pkt_cursor_init(clone_pkt);
-		net_pkt_skip(clone_pkt, ll_addr_offset);
-		lladdr->addr = net_pkt_cursor_get_pos(clone_pkt);
-	}
-}
-
 #if defined(NET_PKT_HAS_CONTROL_BLOCK)
 static inline void clone_pkt_cb(struct net_pkt *pkt, struct net_pkt *clone_pkt)
 {
@@ -2067,32 +2034,30 @@ static void clone_pkt_attributes(struct net_pkt *pkt, struct net_pkt *clone_pkt)
 	net_pkt_set_captured(clone_pkt, net_pkt_is_captured(pkt));
 	net_pkt_set_eof(clone_pkt, net_pkt_eof(pkt));
 	net_pkt_set_ptp(clone_pkt, net_pkt_is_ptp(pkt));
+	net_pkt_set_ppp(clone_pkt, net_pkt_is_ppp(pkt));
+	net_pkt_set_lldp(clone_pkt, net_pkt_is_lldp(pkt));
+	net_pkt_set_ipv4_acd(clone_pkt, net_pkt_ipv4_acd(pkt));
 	net_pkt_set_tx_timestamping(clone_pkt, net_pkt_is_tx_timestamping(pkt));
 	net_pkt_set_rx_timestamping(clone_pkt, net_pkt_is_rx_timestamping(pkt));
 	net_pkt_set_forwarding(clone_pkt, net_pkt_forwarding(pkt));
 	net_pkt_set_chksum_done(clone_pkt, net_pkt_is_chksum_done(pkt));
 	net_pkt_set_ip_reassembled(pkt, net_pkt_is_ip_reassembled(pkt));
-
+	net_pkt_set_cooked_mode(clone_pkt, net_pkt_is_cooked_mode(pkt));
+	net_pkt_set_ipv4_pmtu(clone_pkt, net_pkt_ipv4_pmtu(pkt));
 	net_pkt_set_l2_bridged(clone_pkt, net_pkt_is_l2_bridged(pkt));
 	net_pkt_set_l2_processed(clone_pkt, net_pkt_is_l2_processed(pkt));
 	net_pkt_set_ll_proto_type(clone_pkt, net_pkt_ll_proto_type(pkt));
 
+#if defined(CONFIG_NET_OFFLOAD) || defined(CONFIG_NET_L2_IPIP)
+	net_pkt_set_remote_address(clone_pkt, net_pkt_remote_address(pkt),
+				   sizeof(struct sockaddr_storage));
+#endif
+
 	if (pkt->buffer && clone_pkt->buffer) {
 		memcpy(net_pkt_lladdr_src(clone_pkt), net_pkt_lladdr_src(pkt),
 		       sizeof(struct net_linkaddr));
 		memcpy(net_pkt_lladdr_dst(clone_pkt), net_pkt_lladdr_dst(pkt),
 		       sizeof(struct net_linkaddr));
-		/* The link header pointers are usable as-is if we
-		 * shallow-copied the buffer even if they point
-		 * into the fragment memory of the buffer,
-		 * otherwise we have to set the ll address pointer
-		 * relative to the new buffer to avoid dangling
-		 * pointers into the source packet.
-		 */
-		if (pkt->buffer != clone_pkt->buffer) {
-			clone_pkt_lladdr(pkt, clone_pkt, net_pkt_lladdr_src(clone_pkt));
-			clone_pkt_lladdr(pkt, clone_pkt, net_pkt_lladdr_dst(clone_pkt));
-		}
 	}
 
 	if (IS_ENABLED(CONFIG_NET_IPV4) && net_pkt_family(pkt) == AF_INET) {
diff --git a/subsys/net/ip/net_private.h b/subsys/net/ip/net_private.h
index cc1774a48b7..4ed66f386a8 100644
--- a/subsys/net/ip/net_private.h
+++ b/subsys/net/ip/net_private.h
@@ -59,6 +59,7 @@ extern void net_if_init(void);
 extern void net_if_post_init(void);
 extern void net_if_stats_reset(struct net_if *iface);
 extern void net_if_stats_reset_all(void);
+extern const char *net_if_oper_state2str(enum net_if_oper_state state);
 extern void net_process_rx_packet(struct net_pkt *pkt);
 extern void net_process_tx_packet(struct net_pkt *pkt);
 
@@ -153,6 +154,24 @@ extern void mdns_init_responder(void);
 static inline void mdns_init_responder(void) { }
 #endif /* CONFIG_MDNS_RESPONDER */
 
+#if defined(CONFIG_DNS_RESOLVER)
+#include <zephyr/net/dns_resolve.h>
+extern int dns_resolve_name_internal(struct dns_resolve_context *ctx,
+				     const char *query,
+				     enum dns_query_type type,
+				     uint16_t *dns_id,
+				     dns_resolve_cb_t cb,
+				     void *user_data,
+				     int32_t timeout,
+				     bool use_cache);
+#include <zephyr/net/socket_service.h>
+extern int dns_resolve_init_with_svc(struct dns_resolve_context *ctx,
+				     const char *servers[],
+				     const struct sockaddr *servers_sa[],
+				     const struct net_socket_service_desc *svc,
+				     uint16_t port, int interfaces[]);
+#endif /* CONFIG_DNS_RESOLVER */
+
 #if defined(CONFIG_NET_TEST)
 extern void loopback_enable_address_swap(bool swap_addresses);
 #endif /* CONFIG_NET_TEST */
@@ -184,8 +203,9 @@ static inline enum net_verdict net_ipv6_input(struct net_pkt *pkt,
 static inline void net_tc_tx_init(void) { }
 static inline void net_tc_rx_init(void) { }
 #endif
-extern bool net_tc_submit_to_tx_queue(uint8_t tc, struct net_pkt *pkt);
-extern void net_tc_submit_to_rx_queue(uint8_t tc, struct net_pkt *pkt);
+enum net_verdict net_tc_try_submit_to_tx_queue(uint8_t tc, struct net_pkt *pkt,
+					       k_timeout_t timeout);
+extern enum net_verdict net_tc_submit_to_rx_queue(uint8_t tc, struct net_pkt *pkt);
 extern enum net_verdict net_promisc_mode_input(struct net_pkt *pkt);
 
 char *net_sprint_addr(sa_family_t af, const void *addr);
@@ -239,18 +259,8 @@ void net_if_ipv6_start_dad(struct net_if *iface,
  * @brief Initialize Precision Time Protocol Layer.
  */
 void net_gptp_init(void);
-
-/**
- * @brief Process a ptp message.
- *
- * @param buf Buffer with a valid PTP Ethernet type.
- *
- * @return Return the policy for network buffer.
- */
-enum net_verdict net_gptp_recv(struct net_if *iface, struct net_pkt *pkt);
 #else
 #define net_gptp_init()
-#define net_gptp_recv(iface, pkt) NET_DROP
 #endif /* CONFIG_NET_GPTP */
 
 #if defined(CONFIG_NET_IPV4_FRAGMENT)
@@ -291,7 +301,9 @@ enum net_verdict net_context_packet_received(struct net_conn *conn,
 					     void *user_data);
 
 #if defined(CONFIG_NET_IPV4)
-extern uint16_t net_calc_chksum_ipv4(struct net_pkt *pkt);
+uint16_t net_calc_chksum_ipv4(struct net_pkt *pkt);
+#else
+#define net_calc_chksum_ipv4(...) 0U
 #endif /* CONFIG_NET_IPV4 */
 
 #if defined(CONFIG_NET_IPV4_IGMP)
diff --git a/subsys/net/ip/net_stats.h b/subsys/net/ip/net_stats.h
index 60777d06f1e..17b3f0d8c7f 100644
--- a/subsys/net/ip/net_stats.h
+++ b/subsys/net/ip/net_stats.h
@@ -59,12 +59,56 @@ static inline void net_stats_update_bytes_sent(struct net_if *iface,
 {
 	UPDATE_STAT(iface, stats.bytes.sent += bytes);
 }
+
+#if defined(CONFIG_NET_STATISTICS_PKT_FILTER)
+static inline void net_stats_update_filter_rx_drop(struct net_if *iface)
+{
+	UPDATE_STAT(iface, stats.pkt_filter.rx.drop++);
+}
+
+static inline void net_stats_update_filter_tx_drop(struct net_if *iface)
+{
+	UPDATE_STAT(iface, stats.pkt_filter.tx.drop++);
+}
+
+static inline void net_stats_update_filter_rx_ipv4_drop(struct net_if *iface)
+{
+#if defined(CONFIG_NET_PKT_FILTER_IPV4_HOOK)
+	UPDATE_STAT(iface, stats.pkt_filter.rx.ipv4_drop++);
+#endif
+}
+
+static inline void net_stats_update_filter_rx_ipv6_drop(struct net_if *iface)
+{
+#if defined(CONFIG_NET_PKT_FILTER_IPV6_HOOK)
+	UPDATE_STAT(iface, stats.pkt_filter.rx.ipv6_drop++);
+#endif
+}
+
+static inline void net_stats_update_filter_rx_local_drop(struct net_if *iface)
+{
+#if defined(CONFIG_NET_PKT_FILTER_LOCAL_IN_HOOK)
+	UPDATE_STAT(iface, stats.pkt_filter.rx.local_drop++);
+#endif
+}
+#else /* CONFIG_NET_STATISTICS_PKT_FILTER */
+#define net_stats_update_filter_rx_drop(iface)
+#define net_stats_update_filter_tx_drop(iface)
+#define net_stats_update_filter_rx_ipv4_drop(iface)
+#define net_stats_update_filter_rx_ipv6_drop(iface)
+#define net_stats_update_filter_rx_local_drop(iface)
+#endif /* CONFIG_NET_STATISTICS_PKT_FILTER */
 #else
 #define net_stats_update_processing_error(iface)
 #define net_stats_update_ip_errors_protoerr(iface)
 #define net_stats_update_ip_errors_vhlerr(iface)
 #define net_stats_update_bytes_recv(iface, bytes)
 #define net_stats_update_bytes_sent(iface, bytes)
+#define net_stats_update_filter_rx_drop(iface)
+#define net_stats_update_filter_tx_drop(iface)
+#define net_stats_update_filter_rx_ipv4_drop(iface)
+#define net_stats_update_filter_rx_ipv6_drop(iface)
+#define net_stats_update_filter_rx_local_drop(iface)
 #endif /* CONFIG_NET_STATISTICS */
 
 #if defined(CONFIG_NET_STATISTICS_IPV6) && defined(CONFIG_NET_NATIVE_IPV6)
@@ -485,6 +529,11 @@ static inline void net_stats_update_tc_sent_pkt(struct net_if *iface, uint8_t tc
 	UPDATE_STAT(iface, stats.tc.sent[tc].pkts++);
 }
 
+static inline void net_stats_update_tc_sent_dropped(struct net_if *iface, uint8_t tc)
+{
+	UPDATE_STAT(iface, stats.tc.sent[tc].dropped++);
+}
+
 static inline void net_stats_update_tc_sent_bytes(struct net_if *iface,
 						  uint8_t tc, size_t bytes)
 {
@@ -586,6 +635,11 @@ static inline void net_stats_update_tc_recv_pkt(struct net_if *iface, uint8_t tc
 	UPDATE_STAT(iface, stats.tc.recv[tc].pkts++);
 }
 
+static inline void net_stats_update_tc_recv_dropped(struct net_if *iface, uint8_t tc)
+{
+	UPDATE_STAT(iface, stats.tc.recv[tc].dropped++);
+}
+
 static inline void net_stats_update_tc_recv_bytes(struct net_if *iface,
 						  uint8_t tc, size_t bytes)
 {
@@ -598,12 +652,61 @@ static inline void net_stats_update_tc_recv_priority(struct net_if *iface,
 	UPDATE_STAT(iface, stats.tc.recv[tc].priority = priority);
 }
 #else
-#define net_stats_update_tc_sent_pkt(iface, tc)
-#define net_stats_update_tc_sent_bytes(iface, tc, bytes)
-#define net_stats_update_tc_sent_priority(iface, tc, priority)
-#define net_stats_update_tc_recv_pkt(iface, tc)
-#define net_stats_update_tc_recv_bytes(iface, tc, bytes)
-#define net_stats_update_tc_recv_priority(iface, tc, priority)
+static inline void net_stats_update_tc_sent_pkt(struct net_if *iface, uint8_t tc)
+{
+	ARG_UNUSED(iface);
+	ARG_UNUSED(tc);
+}
+
+static inline void net_stats_update_tc_sent_dropped(struct net_if *iface, uint8_t tc)
+{
+	ARG_UNUSED(iface);
+	ARG_UNUSED(tc);
+}
+
+static inline void net_stats_update_tc_sent_bytes(struct net_if *iface,
+						  uint8_t tc, size_t bytes)
+{
+	ARG_UNUSED(iface);
+	ARG_UNUSED(tc);
+	ARG_UNUSED(bytes);
+}
+
+static inline void net_stats_update_tc_sent_priority(struct net_if *iface,
+						     uint8_t tc, uint8_t priority)
+{
+	ARG_UNUSED(iface);
+	ARG_UNUSED(tc);
+	ARG_UNUSED(priority);
+}
+
+static inline void net_stats_update_tc_recv_pkt(struct net_if *iface, uint8_t tc)
+{
+	ARG_UNUSED(iface);
+	ARG_UNUSED(tc);
+}
+
+static inline void net_stats_update_tc_recv_dropped(struct net_if *iface, uint8_t tc)
+{
+	ARG_UNUSED(iface);
+	ARG_UNUSED(tc);
+}
+
+static inline void net_stats_update_tc_recv_bytes(struct net_if *iface,
+						  uint8_t tc, size_t bytes)
+{
+	ARG_UNUSED(iface);
+	ARG_UNUSED(tc);
+	ARG_UNUSED(bytes);
+}
+
+static inline void net_stats_update_tc_recv_priority(struct net_if *iface,
+						     uint8_t tc, uint8_t priority)
+{
+	ARG_UNUSED(iface);
+	ARG_UNUSED(tc);
+	ARG_UNUSED(priority);
+}
 
 #if defined(CONFIG_NET_PKT_TXTIME_STATS) && \
 	defined(CONFIG_NET_STATISTICS) && defined(CONFIG_NET_NATIVE)
diff --git a/subsys/net/ip/net_tc.c b/subsys/net/ip/net_tc.c
index 7be023ca0e9..15a928ffcd3 100644
--- a/subsys/net/ip/net_tc.c
+++ b/subsys/net/ip/net_tc.c
@@ -18,6 +18,31 @@ LOG_MODULE_REGISTER(net_tc, CONFIG_NET_TC_LOG_LEVEL);
 #include "net_stats.h"
 #include "net_tc_mapping.h"
 
+#define TC_RX_PSEUDO_QUEUE (COND_CODE_1(CONFIG_NET_TC_RX_SKIP_FOR_HIGH_PRIO, (1), (0)))
+#define NET_TC_RX_EFFECTIVE_COUNT (NET_TC_RX_COUNT + TC_RX_PSEUDO_QUEUE)
+
+#if NET_TC_RX_EFFECTIVE_COUNT > 1
+#define NET_TC_RX_SLOTS (CONFIG_NET_PKT_RX_COUNT / NET_TC_RX_EFFECTIVE_COUNT)
+BUILD_ASSERT(NET_TC_RX_SLOTS > 0,
+		"Misconfiguration: There are more traffic classes then packets, "
+		"either increase CONFIG_NET_PKT_RX_COUNT or decrease "
+		"CONFIG_NET_TC_RX_COUNT or disable CONFIG_NET_TC_RX_SKIP_FOR_HIGH_PRIO");
+#endif
+
+#define TC_TX_PSEUDO_QUEUE (COND_CODE_1(CONFIG_NET_TC_TX_SKIP_FOR_HIGH_PRIO, (1), (0)))
+#define NET_TC_TX_EFFECTIVE_COUNT (NET_TC_TX_COUNT + TC_TX_PSEUDO_QUEUE)
+
+#if NET_TC_TX_EFFECTIVE_COUNT > 1
+#define NET_TC_TX_SLOTS (CONFIG_NET_PKT_TX_COUNT / NET_TC_TX_EFFECTIVE_COUNT)
+BUILD_ASSERT(NET_TC_TX_SLOTS > 0,
+		"Misconfiguration: There are more traffic classes then packets, "
+		"either increase CONFIG_NET_PKT_TX_COUNT or decrease "
+		"CONFIG_NET_TC_TX_COUNT or disable CONFIG_NET_TC_TX_SKIP_FOR_HIGH_PRIO");
+#endif
+
+#if NET_TC_RX_EFFECTIVE_COUNT > 1
+#define NET_TC_RETRY_CNT 1
+#endif
 /* Template for thread name. The "xx" is either "TX" denoting transmit thread,
  * or "RX" denoting receive thread. The "q[y]" denotes the traffic class queue
  * where y indicates the traffic class id. The value of y can be from 0 to 7.
@@ -40,35 +65,55 @@ static struct net_traffic_class tx_classes[NET_TC_TX_COUNT];
 static struct net_traffic_class rx_classes[NET_TC_RX_COUNT];
 #endif
 
-#if NET_TC_RX_COUNT > 0 || NET_TC_TX_COUNT > 0
-static void submit_to_queue(struct k_fifo *queue, struct net_pkt *pkt)
-{
-	k_fifo_put(queue, pkt);
-}
-#endif
-
-bool net_tc_submit_to_tx_queue(uint8_t tc, struct net_pkt *pkt)
+enum net_verdict net_tc_try_submit_to_tx_queue(uint8_t tc, struct net_pkt *pkt,
+					       k_timeout_t timeout)
 {
 #if NET_TC_TX_COUNT > 0
 	net_pkt_set_tx_stats_tick(pkt, k_cycle_get_32());
 
-	submit_to_queue(&tx_classes[tc].fifo, pkt);
+#if NET_TC_TX_EFFECTIVE_COUNT > 1
+	if (k_sem_take(&tx_classes[tc].fifo_slot, timeout) != 0) {
+		return NET_DROP;
+	}
+#endif
+
+	k_fifo_put(&tx_classes[tc].fifo, pkt);
+	return NET_OK;
 #else
 	ARG_UNUSED(tc);
 	ARG_UNUSED(pkt);
+	return NET_DROP;
 #endif
-	return true;
 }
 
-void net_tc_submit_to_rx_queue(uint8_t tc, struct net_pkt *pkt)
+enum net_verdict net_tc_submit_to_rx_queue(uint8_t tc, struct net_pkt *pkt)
 {
 #if NET_TC_RX_COUNT > 0
+#if NET_TC_RX_EFFECTIVE_COUNT > 1
+	uint8_t retry_cnt = NET_TC_RETRY_CNT;
+#endif
 	net_pkt_set_rx_stats_tick(pkt, k_cycle_get_32());
 
-	submit_to_queue(&rx_classes[tc].fifo, pkt);
+#if NET_TC_RX_EFFECTIVE_COUNT > 1
+	while (k_sem_take(&rx_classes[tc].fifo_slot, K_NO_WAIT) != 0) {
+		if (k_is_in_isr() || retry_cnt == 0) {
+			return NET_DROP;
+		}
+
+		retry_cnt--;
+		/* Let thread with same priority run,
+		 * try to reduce dropping packets
+		 */
+		k_yield();
+	}
+#endif
+
+	k_fifo_put(&rx_classes[tc].fifo, pkt);
+	return NET_OK;
 #else
 	ARG_UNUSED(tc);
 	ARG_UNUSED(pkt);
+	return NET_DROP;
 #endif
 }
 
@@ -242,10 +287,14 @@ static void net_tc_rx_stats_priority_setup(struct net_if *iface,
 #if NET_TC_RX_COUNT > 0
 static void tc_rx_handler(void *p1, void *p2, void *p3)
 {
-	ARG_UNUSED(p2);
 	ARG_UNUSED(p3);
 
 	struct k_fifo *fifo = p1;
+#if NET_TC_RX_EFFECTIVE_COUNT > 1
+	struct k_sem *fifo_slot = p2;
+#else
+	ARG_UNUSED(p2);
+#endif
 	struct net_pkt *pkt;
 
 	while (1) {
@@ -254,6 +303,10 @@ static void tc_rx_handler(void *p1, void *p2, void *p3)
 			continue;
 		}
 
+#if NET_TC_RX_EFFECTIVE_COUNT > 1
+		k_sem_give(fifo_slot);
+#endif
+
 		net_process_rx_packet(pkt);
 	}
 }
@@ -262,10 +315,14 @@ static void tc_rx_handler(void *p1, void *p2, void *p3)
 #if NET_TC_TX_COUNT > 0
 static void tc_tx_handler(void *p1, void *p2, void *p3)
 {
-	ARG_UNUSED(p2);
 	ARG_UNUSED(p3);
 
 	struct k_fifo *fifo = p1;
+#if NET_TC_TX_EFFECTIVE_COUNT > 1
+	struct k_sem *fifo_slot = p2;
+#else
+	ARG_UNUSED(p2);
+#endif
 	struct net_pkt *pkt;
 
 	while (1) {
@@ -274,6 +331,10 @@ static void tc_tx_handler(void *p1, void *p2, void *p3)
 			continue;
 		}
 
+#if NET_TC_TX_EFFECTIVE_COUNT > 1
+		k_sem_give(fifo_slot);
+#endif
+
 		net_process_tx_packet(pkt);
 	}
 }
@@ -318,10 +379,20 @@ void net_tc_tx_init(void)
 
 		k_fifo_init(&tx_classes[i].fifo);
 
+#if NET_TC_TX_EFFECTIVE_COUNT > 1
+		k_sem_init(&tx_classes[i].fifo_slot, NET_TC_TX_SLOTS, NET_TC_TX_SLOTS);
+#endif
+
 		tid = k_thread_create(&tx_classes[i].handler, tx_stack[i],
 				      K_KERNEL_STACK_SIZEOF(tx_stack[i]),
 				      tc_tx_handler,
-				      &tx_classes[i].fifo, NULL, NULL,
+				      &tx_classes[i].fifo,
+#if NET_TC_TX_EFFECTIVE_COUNT > 1
+				      &tx_classes[i].fifo_slot,
+#else
+				      NULL,
+#endif
+				      NULL,
 				      priority, 0, K_FOREVER);
 		if (!tid) {
 			NET_ERR("Cannot create TC handler thread %d", i);
@@ -376,10 +447,20 @@ void net_tc_rx_init(void)
 
 		k_fifo_init(&rx_classes[i].fifo);
 
+#if NET_TC_RX_EFFECTIVE_COUNT > 1
+		k_sem_init(&rx_classes[i].fifo_slot, NET_TC_RX_SLOTS, NET_TC_RX_SLOTS);
+#endif
+
 		tid = k_thread_create(&rx_classes[i].handler, rx_stack[i],
 				      K_KERNEL_STACK_SIZEOF(rx_stack[i]),
 				      tc_rx_handler,
-				      &rx_classes[i].fifo, NULL, NULL,
+				      &rx_classes[i].fifo,
+#if NET_TC_RX_EFFECTIVE_COUNT > 1
+				      &rx_classes[i].fifo_slot,
+#else
+				      NULL,
+#endif
+				      NULL,
 				      priority, 0, K_FOREVER);
 		if (!tid) {
 			NET_ERR("Cannot create TC handler thread %d", i);
diff --git a/subsys/net/ip/packet_socket.c b/subsys/net/ip/packet_socket.c
index e0d0c8318f1..829e990dafe 100644
--- a/subsys/net/ip/packet_socket.c
+++ b/subsys/net/ip/packet_socket.c
@@ -15,17 +15,19 @@ LOG_MODULE_REGISTER(net_sockets_raw, CONFIG_NET_SOCKETS_LOG_LEVEL);
 #include <zephyr/net/net_pkt.h>
 #include <zephyr/net/net_context.h>
 #include <zephyr/net/ethernet.h>
+#if defined(CONFIG_NET_DSA_DEPRECATED)
 #include <zephyr/net/dsa.h>
+#endif
 
 #include "connection.h"
 #include "packet_socket.h"
 
-enum net_verdict net_packet_socket_input(struct net_pkt *pkt, uint8_t proto)
+enum net_verdict net_packet_socket_input(struct net_pkt *pkt, uint16_t proto)
 {
 	sa_family_t orig_family;
 	enum net_verdict net_verdict;
 
-#if defined(CONFIG_NET_DSA)
+#if defined(CONFIG_NET_DSA_DEPRECATED)
 	/*
 	 * For DSA the master port is not supporting raw packets. Only the
 	 * lan1..3 are working with them.
@@ -39,13 +41,9 @@ enum net_verdict net_packet_socket_input(struct net_pkt *pkt, uint8_t proto)
 
 	net_pkt_set_family(pkt, AF_PACKET);
 
-	net_verdict = net_conn_input(pkt, NULL, proto, NULL);
+	net_verdict = net_conn_packet_input(pkt, proto);
 
 	net_pkt_set_family(pkt, orig_family);
 
-	if (net_verdict == NET_DROP) {
-		return NET_CONTINUE;
-	} else {
-		return net_verdict;
-	}
+	return net_verdict;
 }
diff --git a/subsys/net/ip/packet_socket.h b/subsys/net/ip/packet_socket.h
index 1d853e157ff..b44717635b4 100644
--- a/subsys/net/ip/packet_socket.h
+++ b/subsys/net/ip/packet_socket.h
@@ -26,10 +26,10 @@
  * disabled, the function will always return NET_DROP.
  */
 #if defined(CONFIG_NET_SOCKETS_PACKET)
-enum net_verdict net_packet_socket_input(struct net_pkt *pkt, uint8_t proto);
+enum net_verdict net_packet_socket_input(struct net_pkt *pkt, uint16_t proto);
 #else
 static inline enum net_verdict net_packet_socket_input(struct net_pkt *pkt,
-	uint8_t proto)
+						       uint16_t proto)
 {
 	return NET_CONTINUE;
 }
diff --git a/subsys/net/ip/route.c b/subsys/net/ip/route.c
index f26f84948a8..4f646b3d37b 100644
--- a/subsys/net/ip/route.c
+++ b/subsys/net/ip/route.c
@@ -328,7 +328,7 @@ struct net_route_entry *net_route_add(struct net_if *iface,
 				      uint32_t lifetime,
 				      uint8_t preference)
 {
-	struct net_linkaddr_storage *nexthop_lladdr;
+	struct net_linkaddr *nexthop_lladdr;
 	struct net_nbr *nbr, *nbr_nexthop, *tmp;
 	struct net_route_nexthop *nexthop_route;
 	struct net_route_entry *route = NULL;
@@ -403,7 +403,7 @@ struct net_route_entry *net_route_add(struct net_if *iface,
 
 		if (CONFIG_NET_ROUTE_LOG_LEVEL >= LOG_LEVEL_DBG) {
 			struct in6_addr *in6_addr_tmp;
-			struct net_linkaddr_storage *llstorage;
+			struct net_linkaddr *llstorage;
 
 			in6_addr_tmp = net_route_get_nexthop(route);
 			nbr = net_ipv6_nbr_lookup(iface, in6_addr_tmp);
@@ -1031,7 +1031,7 @@ static bool is_ll_addr_supported(struct net_if *iface)
 
 int net_route_packet(struct net_pkt *pkt, struct in6_addr *nexthop)
 {
-	struct net_linkaddr_storage *lladdr = NULL;
+	struct net_linkaddr *lladdr = NULL;
 	struct net_nbr *nbr;
 	int err;
 
@@ -1055,7 +1055,7 @@ int net_route_packet(struct net_pkt *pkt, struct in6_addr *nexthop)
 			goto error;
 		}
 
-		if (!net_pkt_lladdr_src(pkt)->addr) {
+		if (net_pkt_lladdr_src(pkt)->len == 0) {
 			NET_DBG("Link layer source address not set");
 			err = -EINVAL;
 			goto error;
@@ -1079,15 +1079,12 @@ int net_route_packet(struct net_pkt *pkt, struct in6_addr *nexthop)
 	 * destination address to be the nexthop recipient.
 	 */
 	if (is_ll_addr_supported(net_pkt_iface(pkt))) {
-		net_pkt_lladdr_src(pkt)->addr = net_pkt_lladdr_if(pkt)->addr;
-		net_pkt_lladdr_src(pkt)->type = net_pkt_lladdr_if(pkt)->type;
-		net_pkt_lladdr_src(pkt)->len = net_pkt_lladdr_if(pkt)->len;
+		(void)net_linkaddr_copy(net_pkt_lladdr_src(pkt),
+					net_pkt_lladdr_if(pkt));
 	}
 
 	if (lladdr) {
-		net_pkt_lladdr_dst(pkt)->addr = lladdr->addr;
-		net_pkt_lladdr_dst(pkt)->type = lladdr->type;
-		net_pkt_lladdr_dst(pkt)->len = lladdr->len;
+		(void)net_linkaddr_copy(net_pkt_lladdr_dst(pkt), lladdr);
 	}
 
 	net_pkt_set_iface(pkt, nbr->iface);
@@ -1113,7 +1110,9 @@ int net_route_packet_if(struct net_pkt *pkt, struct net_if *iface)
 
 	/* Set source LL address if only if relevant */
 	if (is_ll_addr_supported(iface)) {
-		net_pkt_lladdr_src(pkt)->addr = net_pkt_lladdr_if(pkt)->addr;
+		memcpy(net_pkt_lladdr_src(pkt)->addr,
+		       net_pkt_lladdr_if(pkt)->addr,
+		       net_pkt_lladdr_if(pkt)->len);
 		net_pkt_lladdr_src(pkt)->type = net_pkt_lladdr_if(pkt)->type;
 		net_pkt_lladdr_src(pkt)->len = net_pkt_lladdr_if(pkt)->len;
 	}
diff --git a/subsys/net/ip/tcp.c b/subsys/net/ip/tcp.c
index 14da3f0cc34..89c0fa6fde0 100644
--- a/subsys/net/ip/tcp.c
+++ b/subsys/net/ip/tcp.c
@@ -784,7 +784,8 @@ static void tcp_conn_release(struct k_work *work)
 		net_if_addr_unref(conn->iface, conn->src.sa.sa_family,
 				  conn->src.sa.sa_family == AF_INET ?
 				  (const void *)&conn->src.sin.sin_addr :
-				  (const void *)&conn->src.sin6.sin6_addr);
+				  (const void *)&conn->src.sin6.sin6_addr,
+				  NULL);
 	}
 
 	conn->context->tcp = NULL;
@@ -2482,7 +2483,7 @@ static struct tcp *tcp_conn_new(struct net_pkt *pkt)
 		net_sprint_addr(context->remote.sa_family,
 				(const void *)&net_sin(&context->remote)->sin_addr));
 
-	ret = net_conn_register(IPPROTO_TCP, af,
+	ret = net_conn_register(IPPROTO_TCP, SOCK_STREAM, af,
 				&context->remote, &local_addr,
 				ntohs(conn->dst.sin.sin_port),/* local port */
 				ntohs(conn->src.sin.sin_port),/* remote port */
@@ -2853,6 +2854,7 @@ static enum net_verdict tcp_in(struct tcp *conn, struct net_pkt *pkt)
 		net_stats_update_tcp_seg_rst(net_pkt_iface(pkt));
 		do_close = true;
 		close_status = -ECONNRESET;
+		conn->rst_received = true;
 
 		/* If we receive RST and ACK for the sent SYN, it means
 		 * that there is no socket listening the port we are trying
@@ -3920,6 +3922,7 @@ int net_tcp_connect(struct net_context *context,
 	net_context_set_state(context, NET_CONTEXT_CONNECTING);
 
 	ret = net_conn_register(net_context_get_proto(context),
+				net_context_get_type(context),
 				net_context_get_family(context),
 				remote_addr, local_addr,
 				ntohs(remote_port), ntohs(local_port),
@@ -3951,7 +3954,11 @@ int net_tcp_connect(struct net_context *context,
 
 	if (!IS_ENABLED(CONFIG_NET_TEST_PROTOCOL)) {
 		if (conn->state == TCP_UNUSED || conn->state == TCP_CLOSED) {
-			ret = -ENOTCONN;
+			if (conn->rst_received) {
+				ret = -ECONNREFUSED;
+			} else {
+				ret = -ENOTCONN;
+			}
 			goto out_unref;
 		} else if ((K_TIMEOUT_EQ(timeout, K_NO_WAIT)) &&
 			   conn->state != TCP_ESTABLISHED) {
@@ -3964,7 +3971,11 @@ int net_tcp_connect(struct net_context *context,
 				tcp_conn_close(conn, -ETIMEDOUT);
 			}
 
-			ret = -ETIMEDOUT;
+			if (conn->rst_received) {
+				ret = -ECONNREFUSED;
+			} else {
+				ret = -ETIMEDOUT;
+			}
 			goto out_unref;
 		}
 		conn->in_connect = false;
@@ -4053,6 +4064,7 @@ int net_tcp_accept(struct net_context *context, net_tcp_accept_cb_t cb,
 	net_conn_unregister(context->conn_handler);
 
 	return net_conn_register(net_context_get_proto(context),
+				 net_context_get_type(context),
 				 local_addr.sa_family,
 				 context->flags & NET_CONTEXT_REMOTE_ADDR_SET ?
 				 &context->remote : NULL,
@@ -4353,13 +4365,15 @@ enum net_verdict tp_input(struct net_conn *net_conn,
 	return verdict;
 }
 
-static void test_cb_register(sa_family_t family, uint8_t proto, uint16_t remote_port,
+static void test_cb_register(sa_family_t family, enum net_sock_type type,
+			     uint8_t proto, uint16_t remote_port,
 			     uint16_t local_port, net_conn_cb_t cb)
 {
 	struct net_conn_handle *conn_handle = NULL;
 	const struct sockaddr addr = { .sa_family = family, };
 
 	int ret = net_conn_register(proto,
+				    type,
 				    family,
 				    &addr,	/* remote address */
 				    &addr,	/* local address */
@@ -4622,10 +4636,10 @@ void net_tcp_init(void)
 	int rto;
 #if defined(CONFIG_NET_TEST_PROTOCOL)
 	/* Register inputs for TTCN-3 based TCP sanity check */
-	test_cb_register(AF_INET,  IPPROTO_TCP, 4242, 4242, tcp_input);
-	test_cb_register(AF_INET6, IPPROTO_TCP, 4242, 4242, tcp_input);
-	test_cb_register(AF_INET,  IPPROTO_UDP, 4242, 4242, tp_input);
-	test_cb_register(AF_INET6, IPPROTO_UDP, 4242, 4242, tp_input);
+	test_cb_register(AF_INET,  SOCK_STREAM, IPPROTO_TCP, 4242, 4242, tcp_input);
+	test_cb_register(AF_INET6, SOCK_STREAM, IPPROTO_TCP, 4242, 4242, tcp_input);
+	test_cb_register(AF_INET,  SOCK_DGRAM, IPPROTO_UDP, 4242, 4242, tp_input);
+	test_cb_register(AF_INET6, SOCK_DGRAM, IPPROTO_UDP, 4242, 4242, tp_input);
 
 	tcp_recv_cb = tp_tcp_recv_cb;
 #endif
diff --git a/subsys/net/ip/tcp_private.h b/subsys/net/ip/tcp_private.h
index e9e41df99f7..a0ab02332e3 100644
--- a/subsys/net/ip/tcp_private.h
+++ b/subsys/net/ip/tcp_private.h
@@ -338,6 +338,7 @@ struct tcp { /* TCP connection */
 #endif /* CONFIG_NET_TCP_KEEPALIVE */
 	bool tcp_nodelay : 1;
 	bool addr_ref_done : 1;
+	bool rst_received : 1;
 };
 
 #define _flags(_fl, _op, _mask, _cond)					\
diff --git a/subsys/net/ip/udp.c b/subsys/net/ip/udp.c
index 3ff428cd8a4..e2214bbe470 100644
--- a/subsys/net/ip/udp.c
+++ b/subsys/net/ip/udp.c
@@ -137,9 +137,9 @@ int net_udp_register(uint8_t family,
 		     void *user_data,
 		     struct net_conn_handle **handle)
 {
-	return net_conn_register(IPPROTO_UDP, family, remote_addr, local_addr,
-				 remote_port, local_port, context, cb,
-				 user_data, handle);
+	return net_conn_register(IPPROTO_UDP, SOCK_DGRAM, family, remote_addr,
+				 local_addr, remote_port, local_port, context,
+				 cb, user_data, handle);
 }
 
 int net_udp_unregister(struct net_conn_handle *handle)
diff --git a/subsys/net/ip/utils.c b/subsys/net/ip/utils.c
index 5025e326b80..3e4d76e2968 100644
--- a/subsys/net/ip/utils.c
+++ b/subsys/net/ip/utils.c
@@ -335,24 +335,63 @@ int z_impl_net_addr_pton(sa_family_t family, const char *src,
 {
 	if (family == AF_INET) {
 		struct in_addr *addr = (struct in_addr *)dst;
-		size_t i, len;
-
-		len = strlen(src);
-		for (i = 0; i < len; i++) {
-			if (!(src[i] >= '0' && src[i] <= '9') &&
-			    src[i] != '.') {
-				return -EINVAL;
-			}
-		}
+		uint8_t index = 0, digits = 0;
+		uint16_t value = 0, count = 0;
 
 		(void)memset(addr, 0, sizeof(struct in_addr));
 
-		for (i = 0; i < sizeof(struct in_addr); i++) {
-			char *endptr;
+		/* A valid IPv4 address that can be used with inet_pton
+		 * must be in the standard dotted-decimal notation:
+		 *
+		 *    - Four octets, each ranging from 0 to 255
+		 *    - Separated by dots (.)
+		 *    - No leading zeros in each octet
+		 */
 
-			addr->s4_addr[i] = strtol(src, &endptr, 10);
+		while (index < sizeof(struct in_addr)) {
+			if (*src == '\0' || *src == '.') {
+				if (*src == '.') {
+					count++;
+				}
+
+				if ((digits > 1 && value < 10) ||
+				    (digits > 2 && value < 100)) {
+					/* Preceding zeroes */
+					return -EINVAL;
+				}
+
+				if (digits == 0 || value > UINT8_MAX) {
+					return -EINVAL;
+				}
 
-			src = ++endptr;
+				addr->s4_addr[index] = value;
+
+				if (*src == '\0') {
+					break;
+				}
+
+				index++;
+				digits = 0;
+				value = 0;
+			} else if ('0' <= *src && *src <= '9') {
+				if (++digits > 3) {
+					/* Number too large */
+					return -EINVAL;
+				}
+
+				value *= 10;
+				value += *src - '0';
+			} else {
+				/* Invalid character */
+				return -EINVAL;
+			}
+
+			src++;
+		}
+
+		if (count != 3) {
+			/* Three dots needed */
+			return -EINVAL;
 		}
 
 	} else if (family == AF_INET6) {
@@ -597,6 +636,7 @@ uint16_t calc_chksum(uint16_t sum_in, const uint8_t *data, size_t len)
 	}
 }
 
+#if defined(CONFIG_NET_NATIVE_IP)
 static inline uint16_t pkt_calc_chksum(struct net_pkt *pkt, uint16_t sum)
 {
 	struct net_pkt_cursor *cur = &pkt->cursor;
@@ -634,7 +674,6 @@ static inline uint16_t pkt_calc_chksum(struct net_pkt *pkt, uint16_t sum)
 	return sum;
 }
 
-#if defined(CONFIG_NET_NATIVE_IP)
 uint16_t net_calc_chksum(struct net_pkt *pkt, uint8_t proto)
 {
 	size_t len = 0U;
@@ -932,6 +971,162 @@ bool net_ipaddr_parse(const char *str, size_t str_len, struct sockaddr *addr)
 	return false;
 }
 
+const char *net_ipaddr_parse_mask(const char *str, size_t str_len,
+				  struct sockaddr *addr, uint8_t *mask_len)
+{
+	const char *next = NULL, *mask_ptr = NULL;
+	int parsed_mask_len = -1;
+	bool ret = false;
+
+	if (str == NULL || str_len == 0 || addr == NULL || mask_len == NULL) {
+		return NULL;
+	}
+
+	if (*str == '\0') {
+		return NULL;
+	}
+
+	for (int i = 0; i < str_len; i++) {
+		if (str[i] == ',' || str[i] == ' ') {
+			next = str + i + 1;
+			str_len = next - str - 1;
+			break;
+		}
+
+		if (str[i] == '/') {
+			mask_ptr = str + i;
+		}
+	}
+
+	if (mask_ptr != NULL) {
+		char *endptr;
+
+		parsed_mask_len = strtoul(mask_ptr + 1, &endptr, 10);
+		if (*endptr != '\0') {
+			if (next == NULL) {
+				return NULL;
+			}
+		}
+
+		str_len = mask_ptr - str;
+		*mask_len = (uint8_t)parsed_mask_len;
+	}
+
+#if defined(CONFIG_NET_IPV4) && defined(CONFIG_NET_IPV6)
+	ret = parse_ipv4(str, str_len, addr, false);
+	if (!ret) {
+		ret = parse_ipv6(str, str_len, addr, false);
+	}
+#elif defined(CONFIG_NET_IPV4) && !defined(CONFIG_NET_IPV6)
+	ret = parse_ipv4(str, str_len, addr, false);
+
+#elif defined(CONFIG_NET_IPV6) && !defined(CONFIG_NET_IPV4)
+	ret = parse_ipv6(str, str_len, addr, false);
+#endif
+
+	if (!ret) {
+		return NULL;
+	}
+
+	if (parsed_mask_len < 0) {
+		if (addr->sa_family == AF_INET) {
+			*mask_len = 32;
+		} else if (addr->sa_family == AF_INET6) {
+			*mask_len = 128;
+		}
+	}
+
+	if (next != NULL) {
+		return next;
+	}
+
+	return "";
+}
+
+int net_mask_len_to_netmask(sa_family_t family, uint8_t mask_len, struct sockaddr *mask)
+{
+	if (family == AF_INET) {
+		struct in_addr *addr4 = &net_sin(mask)->sin_addr;
+		struct sockaddr_in *mask4 = (struct sockaddr_in *)mask;
+
+		if (mask_len > 32) {
+			return -ERANGE;
+		}
+
+		memset(mask4, 0, sizeof(struct sockaddr_in));
+
+		mask4->sin_family = AF_INET;
+		mask4->sin_port = 0;
+		addr4->s_addr = htonl(UINT32_MAX << (32 - mask_len));
+
+	} else if (family == AF_INET6) {
+		struct in6_addr *addr6 = &net_sin6(mask)->sin6_addr;
+		struct sockaddr_in6 *mask6 = (struct sockaddr_in6 *)mask;
+		uint32_t mask_val[4] = { 0 };
+
+		if (mask_len > 128) {
+			return -ERANGE;
+		}
+
+		memset(mask6, 0, sizeof(struct sockaddr_in6));
+
+		mask6->sin6_family = AF_INET6;
+		mask6->sin6_port = 0;
+
+		for (int i = 0; i < 4; i++) {
+			int bits = mask_len - i * 32;
+
+			if (bits >= 32) {
+				mask_val[i] = UINT32_MAX;
+			} else if (bits > 0) {
+				mask_val[i] = htonl(UINT32_MAX << (32 - bits));
+			}
+		}
+
+		memcpy(addr6->s6_addr32, mask_val, sizeof(mask_val));
+	} else {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int net_netmask_to_mask_len(sa_family_t family, struct sockaddr *mask, uint8_t *mask_len)
+{
+	int zerobits = 0;
+	int maxlen;
+	uint8_t n;
+
+	if (mask_len == NULL || mask == NULL) {
+		return -EINVAL;
+	}
+
+	if (family != AF_INET && family != AF_INET6) {
+		return -EINVAL;
+	}
+
+	maxlen = family == AF_INET ? sizeof(struct in_addr) :
+				     sizeof(struct in6_addr);
+
+	for (int i = maxlen - 1; i >= 0; i--) {
+		n = net_sin6(mask)->sin6_addr.s6_addr[i];
+
+		for (int j = 0; j < 8; j++) {
+			if ((n & 0x1) == 0) {
+				zerobits++;
+			} else {
+				break;
+			}
+
+			n = n >> 1;
+		}
+	}
+
+	*mask_len = maxlen * 8 - zerobits;
+
+	return 0;
+}
+
 int net_port_set_default(struct sockaddr *addr, uint16_t default_port)
 {
 	if (IS_ENABLED(CONFIG_NET_IPV4) && addr->sa_family == AF_INET &&
diff --git a/subsys/net/l2/canbus/canbus_raw.c b/subsys/net/l2/canbus/canbus_raw.c
index 2bd7d605b25..8bdf1aa3650 100644
--- a/subsys/net/l2/canbus/canbus_raw.c
+++ b/subsys/net/l2/canbus/canbus_raw.c
@@ -16,10 +16,10 @@ LOG_MODULE_REGISTER(net_l2_canbus, LOG_LEVEL_NONE);
 static inline enum net_verdict canbus_recv(struct net_if *iface,
 					   struct net_pkt *pkt)
 {
-	net_pkt_lladdr_src(pkt)->addr = NULL;
+	memset(net_pkt_lladdr_src(pkt)->addr, 0, sizeof(net_pkt_lladdr_src(pkt)->addr));
 	net_pkt_lladdr_src(pkt)->len = 0U;
 	net_pkt_lladdr_src(pkt)->type = NET_LINK_CANBUS_RAW;
-	net_pkt_lladdr_dst(pkt)->addr = NULL;
+	memset(net_pkt_lladdr_dst(pkt)->addr, 0, sizeof(net_pkt_lladdr_dst(pkt)->addr));
 	net_pkt_lladdr_dst(pkt)->len = 0U;
 	net_pkt_lladdr_dst(pkt)->type = NET_LINK_CANBUS_RAW;
 
diff --git a/subsys/net/l2/dummy/CMakeLists.txt b/subsys/net/l2/dummy/CMakeLists.txt
index 48f5841f9a8..f9e0b184c9f 100644
--- a/subsys/net/l2/dummy/CMakeLists.txt
+++ b/subsys/net/l2/dummy/CMakeLists.txt
@@ -5,6 +5,8 @@ zephyr_library_compile_definitions_ifdef(
   CONFIG_NEWLIB_LIBC __LINUX_ERRNO_EXTENSIONS__
   )
 
+zephyr_library_include_directories(. ${ZEPHYR_BASE}/subsys/net/ip)
+
 zephyr_library_sources_ifdef(CONFIG_NET_L2_DUMMY    dummy.c)
 
 if(CONFIG_NET_PSEUDO_IFACE)
diff --git a/subsys/net/l2/dummy/dummy.c b/subsys/net/l2/dummy/dummy.c
index 37ac492a1a1..0b73ba6967a 100644
--- a/subsys/net/l2/dummy/dummy.c
+++ b/subsys/net/l2/dummy/dummy.c
@@ -14,6 +14,8 @@ LOG_MODULE_REGISTER(net_l2_dummy, LOG_LEVEL_NONE);
 
 #include <zephyr/net/dummy.h>
 
+#include "net_stats.h"
+
 static inline enum net_verdict dummy_recv(struct net_if *iface,
 					  struct net_pkt *pkt)
 {
@@ -41,7 +43,14 @@ static inline int dummy_send(struct net_if *iface, struct net_pkt *pkt)
 
 	ret = net_l2_send(api->send, net_if_get_device(iface), iface, pkt);
 	if (!ret) {
-		ret = net_pkt_get_len(pkt);
+		size_t pkt_len = net_pkt_get_len(pkt);
+
+		if (IS_ENABLED(CONFIG_NET_STATISTICS)) {
+			NET_DBG("Sending pkt %p len %zu", pkt, pkt_len);
+			net_stats_update_bytes_sent(iface, pkt_len);
+		}
+
+		ret = (int)pkt_len;
 		net_pkt_unref(pkt);
 	}
 
diff --git a/subsys/net/l2/ethernet/Kconfig b/subsys/net/l2/ethernet/Kconfig
index 3e5d1c5bb15..00b4ebba3d6 100644
--- a/subsys/net/l2/ethernet/Kconfig
+++ b/subsys/net/l2/ethernet/Kconfig
@@ -49,10 +49,14 @@ config NET_VLAN
 config NET_VLAN_COUNT
 	int "Max VLAN tags supported in the system"
 	default 1
-	range 1 $(UINT8_MAX)
+	range 0 $(UINT8_MAX)
 	depends on NET_VLAN
 	help
-	  How many VLAN tags can be configured.
+	  How many VLAN tags can be configured. If set to 0, then only
+	  priority tagged VLAN frames with tag value 0 can be handled.
+	  This is useful if you do not want to receive any other VLAN
+	  tagged frames than tag 0. This will save some memory as the
+	  VLAN virtual interface is not created in this case.
 
 config NET_VLAN_TXRX_DEBUG
 	bool "Debug received and sent packets in VLAN"
diff --git a/subsys/net/l2/ethernet/arp.c b/subsys/net/l2/ethernet/arp.c
index 9ff51875795..af816185fe1 100644
--- a/subsys/net/l2/ethernet/arp.c
+++ b/subsys/net/l2/ethernet/arp.c
@@ -19,6 +19,7 @@ LOG_MODULE_REGISTER(net_arp, CONFIG_NET_ARP_LOG_LEVEL);
 #include <zephyr/net/net_mgmt.h>
 
 #include "arp.h"
+#include "ipv4.h"
 #include "net_private.h"
 
 #define NET_BUF_TIMEOUT K_MSEC(100)
@@ -77,6 +78,9 @@ static struct arp_entry *arp_entry_find(sys_slist_t *list,
 
 		if (entry->iface == iface &&
 		    net_ipv4_addr_cmp(&entry->ip, dst)) {
+			NET_DBG("found dst %s",
+				net_sprint_ipv4_addr(dst));
+
 			return entry;
 		}
 
@@ -280,6 +284,9 @@ static inline struct net_pkt *arp_prepare(struct net_if *iface,
 		}
 	}
 
+	net_pkt_set_ll_proto_type(pkt, NET_ETH_PTYPE_ARP);
+	net_pkt_set_family(pkt, AF_INET);
+
 	net_buf_add(pkt->buffer, sizeof(struct net_arp_hdr));
 
 	hdr = NET_ARP_HDR(pkt);
@@ -299,19 +306,20 @@ static inline struct net_pkt *arp_prepare(struct net_if *iface,
 
 		net_ipaddr_copy(&entry->ip, next_addr);
 
-		net_pkt_lladdr_src(pkt)->addr =
-			(uint8_t *)net_if_get_link_addr(entry->iface)->addr;
+		(void)net_linkaddr_set(net_pkt_lladdr_src(pkt),
+				       net_if_get_link_addr(entry->iface)->addr,
+				       sizeof(struct net_eth_addr));
 
 		arp_entry_register_pending(entry);
 	} else {
-		net_pkt_lladdr_src(pkt)->addr =
-			(uint8_t *)net_if_get_link_addr(iface)->addr;
+		(void)net_linkaddr_set(net_pkt_lladdr_src(pkt),
+				       net_if_get_link_addr(iface)->addr,
+				       sizeof(struct net_eth_addr));
 	}
 
-	net_pkt_lladdr_src(pkt)->len = sizeof(struct net_eth_addr);
-
-	net_pkt_lladdr_dst(pkt)->addr = (uint8_t *)net_eth_broadcast_addr();
-	net_pkt_lladdr_dst(pkt)->len = sizeof(struct net_eth_addr);
+	(void)net_linkaddr_set(net_pkt_lladdr_dst(pkt),
+			       (const uint8_t *)net_eth_broadcast_addr(),
+			       sizeof(struct net_eth_addr));
 
 	hdr->hwtype = htons(NET_ARP_HTYPE_ETH);
 	hdr->protocol = htons(NET_ETH_PTYPE_IP);
@@ -344,21 +352,23 @@ static inline struct net_pkt *arp_prepare(struct net_if *iface,
 	return pkt;
 }
 
-struct net_pkt *net_arp_prepare(struct net_pkt *pkt,
-				struct in_addr *request_ip,
-				struct in_addr *current_ip)
+int net_arp_prepare(struct net_pkt *pkt,
+		    struct in_addr *request_ip,
+		    struct in_addr *current_ip,
+		    struct net_pkt **arp_pkt)
 {
 	bool is_ipv4_ll_used = false;
 	struct arp_entry *entry;
 	struct in_addr *addr;
 
 	if (!pkt || !pkt->buffer) {
-		return NULL;
+		return -EINVAL;
 	}
 
 	if (net_pkt_ipv4_acd(pkt)) {
-		return arp_prepare(net_pkt_iface(pkt), request_ip, NULL,
-				   pkt, current_ip);
+		*arp_pkt = arp_prepare(net_pkt_iface(pkt), request_ip, NULL,
+				       pkt, current_ip);
+		return *arp_pkt ? NET_ARP_PKT_REPLACED : -ENOMEM;
 	}
 
 	if (IS_ENABLED(CONFIG_NET_IPV4_AUTO)) {
@@ -383,7 +393,7 @@ struct net_pkt *net_arp_prepare(struct net_pkt *pkt,
 					net_if_get_by_iface(net_pkt_iface(pkt)),
 					net_sprint_ipv4_addr(request_ip));
 
-				return NULL;
+				return -EINVAL;
 			}
 		} else {
 			addr = request_ip;
@@ -413,15 +423,19 @@ struct net_pkt *net_arp_prepare(struct net_pkt *pkt,
 			/* There is a pending ARP request already, check if this packet is already
 			 * in the pending list and if so, resend the request, otherwise just
 			 * append the packet to the request fifo list.
+			 * Ensure the packet reference is incremented to account for the queue
+			 * holding the reference.
 			 */
-			if (k_queue_unique_append(&entry->pending_queue._queue,
-						  net_pkt_ref(pkt))) {
+			pkt = net_pkt_ref(pkt);
+			if (k_queue_unique_append(&entry->pending_queue._queue, pkt)) {
 				NET_DBG("Pending ARP request for %s, queuing pkt %p",
 					net_sprint_ipv4_addr(addr), pkt);
 				k_mutex_unlock(&arp_mutex);
-				return NULL;
+				return NET_ARP_PKT_QUEUED;
 			}
 
+			/* Queueing the packet failed, undo the net_pkt_ref */
+			net_pkt_unref(pkt);
 			entry = NULL;
 		}
 
@@ -444,24 +458,25 @@ struct net_pkt *net_arp_prepare(struct net_pkt *pkt,
 		}
 
 		k_mutex_unlock(&arp_mutex);
-		return req;
+		*arp_pkt = req;
+		return req ? NET_ARP_PKT_REPLACED : -ENOMEM;
 	}
 
 	k_mutex_unlock(&arp_mutex);
 
-	net_pkt_lladdr_src(pkt)->addr =
-		(uint8_t *)net_if_get_link_addr(entry->iface)->addr;
-	net_pkt_lladdr_src(pkt)->len = sizeof(struct net_eth_addr);
+	(void)net_linkaddr_set(net_pkt_lladdr_src(pkt),
+			       net_if_get_link_addr(entry->iface)->addr,
+			       sizeof(struct net_eth_addr));
 
-	net_pkt_lladdr_dst(pkt)->addr = (uint8_t *)&entry->eth;
-	net_pkt_lladdr_dst(pkt)->len = sizeof(struct net_eth_addr);
+	(void)net_linkaddr_set(net_pkt_lladdr_dst(pkt),
+			       (const uint8_t *)&entry->eth, sizeof(struct net_eth_addr));
 
 	NET_DBG("ARP using ll %s for IP %s",
 		net_sprint_ll_addr(net_pkt_lladdr_dst(pkt)->addr,
 				   sizeof(struct net_eth_addr)),
-		net_sprint_ipv4_addr(&NET_IPV4_HDR(pkt)->dst));
+		net_sprint_ipv4_addr(NET_IPV4_HDR(pkt)->dst));
 
-	return pkt;
+	return NET_ARP_COMPLETE;
 }
 
 static void arp_gratuitous(struct net_if *iface,
@@ -498,6 +513,7 @@ static void arp_gratuitous_send(struct net_if *iface,
 
 	net_buf_add(pkt->buffer, sizeof(struct net_arp_hdr));
 	net_pkt_set_vlan_tag(pkt, net_eth_get_vlan_tag(iface));
+	net_pkt_set_ll_proto_type(pkt, NET_ETH_PTYPE_ARP);
 
 	hdr = NET_ARP_HDR(pkt);
 
@@ -515,15 +531,20 @@ static void arp_gratuitous_send(struct net_if *iface,
 	net_ipv4_addr_copy_raw(hdr->dst_ipaddr, (uint8_t *)ipaddr);
 	net_ipv4_addr_copy_raw(hdr->src_ipaddr, (uint8_t *)ipaddr);
 
-	net_pkt_lladdr_src(pkt)->addr = net_if_get_link_addr(iface)->addr;
-	net_pkt_lladdr_src(pkt)->len = sizeof(struct net_eth_addr);
+	(void)net_linkaddr_set(net_pkt_lladdr_src(pkt),
+			       net_if_get_link_addr(iface)->addr,
+			       sizeof(struct net_eth_addr));
 
-	net_pkt_lladdr_dst(pkt)->addr = (uint8_t *)net_eth_broadcast_addr();
-	net_pkt_lladdr_dst(pkt)->len = sizeof(struct net_eth_addr);
+	(void)net_linkaddr_set(net_pkt_lladdr_dst(pkt),
+			       (uint8_t *)net_eth_broadcast_addr(),
+			       sizeof(struct net_eth_addr));
 
 	NET_DBG("Sending gratuitous ARP pkt %p", pkt);
 
-	if (net_if_send_data(iface, pkt) == NET_DROP) {
+	/* send without timeout, so we do not risk being blocked by tx when
+	 * being flooded
+	 */
+	if (net_if_try_send_data(iface, pkt, K_NO_WAIT) == NET_DROP) {
 		net_pkt_unref(pkt);
 	}
 }
@@ -682,14 +703,14 @@ void net_arp_update(struct net_if *iface,
 		pkt = k_fifo_get(&entry->pending_queue, K_FOREVER);
 
 		/* Set the dst in the pending packet */
-		net_pkt_lladdr_dst(pkt)->len = sizeof(struct net_eth_addr);
-		net_pkt_lladdr_dst(pkt)->addr =
-			(uint8_t *) &NET_ETH_HDR(pkt)->dst.addr;
+		(void)net_linkaddr_set(net_pkt_lladdr_dst(pkt),
+				       (const uint8_t *)&NET_ETH_HDR(pkt)->dst.addr,
+				       sizeof(struct net_eth_addr));
 
-		NET_DBG("iface %d (%p) dst %s pending %p frag %p",
+		NET_DBG("iface %d (%p) dst %s pending %p frag %p ptype 0x%04x",
 			net_if_get_by_iface(iface), iface,
 			net_sprint_ipv4_addr(&entry->ip),
-			pkt, pkt->frags);
+			pkt, pkt->frags, net_pkt_ll_proto_type(pkt));
 
 		/* We directly send the packet without first queueing it.
 		 * The pkt has already been queued for sending, once by
@@ -710,7 +731,6 @@ void net_arp_update(struct net_if *iface,
 
 static inline struct net_pkt *arp_prepare_reply(struct net_if *iface,
 						struct net_pkt *req,
-						struct net_eth_hdr *eth_query,
 						struct net_eth_addr *dst_addr)
 {
 	struct net_arp_hdr *hdr, *query;
@@ -745,11 +765,16 @@ static inline struct net_pkt *arp_prepare_reply(struct net_if *iface,
 	net_ipv4_addr_copy_raw(hdr->dst_ipaddr, query->src_ipaddr);
 	net_ipv4_addr_copy_raw(hdr->src_ipaddr, query->dst_ipaddr);
 
-	net_pkt_lladdr_src(pkt)->addr = net_if_get_link_addr(iface)->addr;
-	net_pkt_lladdr_src(pkt)->len = sizeof(struct net_eth_addr);
+	(void)net_linkaddr_set(net_pkt_lladdr_src(pkt),
+			       net_if_get_link_addr(iface)->addr,
+			       sizeof(struct net_eth_addr));
+
+	(void)net_linkaddr_set(net_pkt_lladdr_dst(pkt),
+			       (uint8_t *)&hdr->dst_hwaddr.addr,
+			       sizeof(struct net_eth_addr));
 
-	net_pkt_lladdr_dst(pkt)->addr = (uint8_t *)&hdr->dst_hwaddr.addr;
-	net_pkt_lladdr_dst(pkt)->len = sizeof(struct net_eth_addr);
+	net_pkt_set_ll_proto_type(pkt, NET_ETH_PTYPE_ARP);
+	net_pkt_set_family(pkt, AF_INET);
 
 	return pkt;
 }
@@ -769,18 +794,17 @@ static bool arp_hdr_check(struct net_arp_hdr *arp_hdr)
 }
 
 enum net_verdict net_arp_input(struct net_pkt *pkt,
-			       struct net_eth_hdr *eth_hdr)
+			       struct net_eth_addr *src,
+			       struct net_eth_addr *dst)
 {
 	struct net_eth_addr *dst_hw_addr;
 	struct net_arp_hdr *arp_hdr;
 	struct net_pkt *reply;
 	struct in_addr *addr;
 
-	if (net_pkt_get_len(pkt) < (sizeof(struct net_arp_hdr) -
-				    (net_pkt_ip_data(pkt) - (uint8_t *)eth_hdr))) {
-		NET_DBG("Invalid ARP header (len %zu, min %zu bytes) %p",
-			net_pkt_get_len(pkt), sizeof(struct net_arp_hdr) -
-			(net_pkt_ip_data(pkt) - (uint8_t *)eth_hdr), pkt);
+	if (net_pkt_get_len(pkt) < sizeof(struct net_arp_hdr)) {
+		NET_DBG("DROP: Too short ARP msg (%zu bytes, min %zu bytes)",
+			net_pkt_get_len(pkt), sizeof(struct net_arp_hdr));
 		return NET_DROP;
 	}
 
@@ -801,7 +825,7 @@ enum net_verdict net_arp_input(struct net_pkt *pkt,
 		}
 
 		if (IS_ENABLED(CONFIG_NET_ARP_GRATUITOUS)) {
-			if (net_eth_is_addr_broadcast(&eth_hdr->dst) &&
+			if (net_eth_is_addr_broadcast(dst) &&
 			    (net_eth_is_addr_broadcast(&arp_hdr->dst_hwaddr) ||
 			     net_eth_is_addr_all_zeroes(&arp_hdr->dst_hwaddr)) &&
 			    net_ipv4_addr_cmp_raw(arp_hdr->dst_ipaddr,
@@ -820,7 +844,7 @@ enum net_verdict net_arp_input(struct net_pkt *pkt,
 		/* Discard ARP request if Ethernet address is broadcast
 		 * and Source IP address is Multicast address.
 		 */
-		if (memcmp(&eth_hdr->dst, net_eth_broadcast_addr(),
+		if (memcmp(dst, net_eth_broadcast_addr(),
 			   sizeof(struct net_eth_addr)) == 0 &&
 		    net_ipv4_is_addr_mcast((struct in_addr *)arp_hdr->src_ipaddr)) {
 			NET_DBG("DROP: eth addr is bcast, src addr is mcast");
@@ -859,14 +883,13 @@ enum net_verdict net_arp_input(struct net_pkt *pkt,
 
 			dst_hw_addr = &arp_hdr->src_hwaddr;
 		} else {
-			dst_hw_addr = &eth_hdr->src;
+			dst_hw_addr = src;
 		}
 
 		/* Send reply */
-		reply = arp_prepare_reply(net_pkt_iface(pkt), pkt, eth_hdr,
-					  dst_hw_addr);
+		reply = arp_prepare_reply(net_pkt_iface(pkt), pkt, dst_hw_addr);
 		if (reply) {
-			net_if_queue_tx(net_pkt_iface(reply), reply);
+			net_if_try_queue_tx(net_pkt_iface(reply), reply, K_NO_WAIT);
 		} else {
 			NET_DBG("Cannot send ARP reply");
 		}
@@ -1006,3 +1029,28 @@ void net_arp_init(void)
 			  K_SECONDS(CONFIG_NET_ARP_GRATUITOUS_INTERVAL));
 #endif /* defined(CONFIG_NET_ARP_GRATUITOUS_TRANSMISSION) */
 }
+
+static enum net_verdict arp_recv(struct net_if *iface,
+				 uint16_t ptype,
+				 struct net_pkt *pkt)
+{
+	ARG_UNUSED(iface);
+	ARG_UNUSED(ptype);
+
+	net_pkt_set_family(pkt, AF_INET);
+
+	NET_DBG("ARP packet from %s received",
+		net_sprint_ll_addr(net_pkt_lladdr_src(pkt)->addr,
+				   sizeof(struct net_eth_addr)));
+
+	if (IS_ENABLED(CONFIG_NET_IPV4_ACD) &&
+	    net_ipv4_acd_input(iface, pkt) == NET_DROP) {
+		return NET_DROP;
+	}
+
+	return net_arp_input(pkt,
+			     (struct net_eth_addr *)net_pkt_lladdr_src(pkt)->addr,
+			     (struct net_eth_addr *)net_pkt_lladdr_dst(pkt)->addr);
+}
+
+ETH_NET_L3_REGISTER(ARP, NET_ETH_PTYPE_ARP, arp_recv);
diff --git a/subsys/net/l2/ethernet/arp.h b/subsys/net/l2/ethernet/arp.h
index 46589cbc1f7..03ef9bbe4f8 100644
--- a/subsys/net/l2/ethernet/arp.h
+++ b/subsys/net/l2/ethernet/arp.h
@@ -7,8 +7,6 @@
 #ifndef __ARP_H
 #define __ARP_H
 
-#if defined(CONFIG_NET_ARP) && defined(CONFIG_NET_NATIVE)
-
 #include <zephyr/sys/slist.h>
 #include <zephyr/net/ethernet.h>
 
@@ -23,6 +21,15 @@ extern "C" {
  * @{
  */
 
+/** @brief Address resolution complete, destination link address injected */
+#define NET_ARP_COMPLETE     0
+/** @brief Destination link address unknown, ARP request to be sent instead */
+#define NET_ARP_PKT_REPLACED 1
+/** @brief Destination link address unknown, ARP request pending, packet queued */
+#define NET_ARP_PKT_QUEUED   2
+
+#if defined(CONFIG_NET_ARP) && defined(CONFIG_NET_NATIVE)
+
 #define NET_ARP_HDR(pkt) ((struct net_arp_hdr *)net_pkt_data(pkt))
 
 struct net_arp_hdr {
@@ -43,11 +50,26 @@ struct net_arp_hdr {
 #define NET_ARP_REQUEST 1
 #define NET_ARP_REPLY   2
 
-struct net_pkt *net_arp_prepare(struct net_pkt *pkt,
-				struct in_addr *request_ip,
-				struct in_addr *current_ip);
+/**
+ * @brief Prepare an ARP request, if required
+ *
+ * @param pkt Packet that wants to be sent
+ * @param request_ip Destination address of the packet
+ * @param current_ip Sending IP (Can be NULL)
+ * @param arp_pkt ARP packet that should be sent in place of @a pkt, if not NULL
+ *
+ * @retval NET_ARP_COMPLETE ARP information populated in @a pkt
+ * @retval NET_ARP_PKT_REPLACED ARP request to be sent existing in @a arp_pkt
+ * @retval NET_ARP_PKT_QUEUED @a pkt was queued for transmission on ARP resolution
+ * @retval <0 on failure
+ */
+int net_arp_prepare(struct net_pkt *pkt,
+			struct in_addr *request_ip,
+			struct in_addr *current_ip,
+			struct net_pkt **arp_pkt);
 enum net_verdict net_arp_input(struct net_pkt *pkt,
-			       struct net_eth_hdr *eth_hdr);
+			       struct net_eth_addr *src,
+			       struct net_eth_addr *dst);
 
 int net_arp_clear_pending(struct net_if *iface,
 				struct in_addr *dst);
@@ -71,16 +93,9 @@ void net_arp_update(struct net_if *iface, struct in_addr *src,
 		    struct net_eth_addr *hwaddr, bool gratuitous,
 		    bool force);
 
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
 
 #else /* CONFIG_NET_ARP */
-#define net_arp_prepare(_kt, _u1, _u2) _kt
+#define net_arp_prepare(_kt, _u1, _u2, _arp) NET_ARP_COMPLETE
 #define net_arp_input(...) NET_OK
 #define net_arp_clear_cache(...)
 #define net_arp_foreach(...) 0
@@ -90,4 +105,12 @@ void net_arp_update(struct net_if *iface, struct in_addr *src,
 
 #endif /* CONFIG_NET_ARP */
 
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
 #endif /* __ARP_H */
diff --git a/subsys/net/l2/ethernet/bridge.c b/subsys/net/l2/ethernet/bridge.c
index 4b883643c3a..11384a857d9 100644
--- a/subsys/net/l2/ethernet/bridge.c
+++ b/subsys/net/l2/ethernet/bridge.c
@@ -140,7 +140,7 @@ int eth_bridge_iface_add(struct net_if *br, struct net_if *iface)
 		 * we do not need host promiscuous working when testing
 		 * bridging using native-sim.
 		 */
-		if (!IS_ENABLED(CONFIG_ETH_NATIVE_POSIX)) {
+		if (!IS_ENABLED(CONFIG_ETH_NATIVE_TAP)) {
 			NET_DBG("iface %d promiscuous mode failed: %d",
 				net_if_get_by_iface(iface), ret);
 			eth_bridge_iface_remove(br, iface);
diff --git a/subsys/net/l2/ethernet/dsa/CMakeLists.txt b/subsys/net/l2/ethernet/dsa/CMakeLists.txt
index ddcaed306ee..7c5d26ebb2e 100644
--- a/subsys/net/l2/ethernet/dsa/CMakeLists.txt
+++ b/subsys/net/l2/ethernet/dsa/CMakeLists.txt
@@ -1,4 +1,11 @@
 # SPDX-License-Identifier: Apache-2.0
 
 zephyr_library()
+if(CONFIG_NET_DSA_DEPRECATED)
 zephyr_library_sources(dsa.c)
+else()
+zephyr_library_sources(dsa_core.c)
+zephyr_library_sources(dsa_port.c)
+zephyr_library_sources(dsa_user.c)
+zephyr_library_sources(dsa_tag.c)
+endif()
diff --git a/subsys/net/l2/ethernet/dsa/dsa.c b/subsys/net/l2/ethernet/dsa/dsa.c
index e293af4237a..aa167dc1f2d 100644
--- a/subsys/net/l2/ethernet/dsa/dsa.c
+++ b/subsys/net/l2/ethernet/dsa/dsa.c
@@ -38,7 +38,7 @@ bool dsa_is_port_master(struct net_if *iface)
 	if (net_if_l2(iface) == &NET_L2_GET_NAME(ETHERNET)) {
 		/* Check its capabilities */
 		if (net_eth_get_hw_capabilities(iface) &
-		    ETHERNET_DSA_MASTER_PORT) {
+		    ETHERNET_DSA_CONDUIT_PORT) {
 			return true;
 		}
 	}
@@ -62,8 +62,8 @@ static int dsa_check_iface(struct net_if *iface)
 		return -ENOENT;
 	}
 
-	if (!((net_eth_get_hw_capabilities(iface) & ETHERNET_DSA_MASTER_PORT) ||
-	    (net_eth_get_hw_capabilities(iface) & ETHERNET_DSA_SLAVE_PORT))) {
+	if (!((net_eth_get_hw_capabilities(iface) & ETHERNET_DSA_CONDUIT_PORT) ||
+	    (net_eth_get_hw_capabilities(iface) & ETHERNET_DSA_USER_PORT))) {
 		return -ESRCH;
 	}
 
diff --git a/subsys/net/l2/ethernet/dsa/dsa_core.c b/subsys/net/l2/ethernet/dsa/dsa_core.c
new file mode 100644
index 00000000000..f21b5b8350c
--- /dev/null
+++ b/subsys/net/l2/ethernet/dsa/dsa_core.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(net_dsa_core, CONFIG_NET_DSA_LOG_LEVEL);
+
+#include <zephyr/net/ethernet.h>
+#include <zephyr/net/dsa_core.h>
+
+#include "dsa_tag.h"
+
+struct net_if *dsa_recv(struct net_if *iface, struct net_pkt *pkt)
+{
+	if (iface == NULL || pkt == NULL) {
+		return iface;
+	}
+
+	/* Tag protocol handles to untag and re-direct interface */
+	return dsa_tag_recv(iface, pkt);
+}
+
+int dsa_xmit(const struct device *dev, struct net_pkt *pkt)
+{
+	struct dsa_switch_context *dsa_switch_ctx = dev->data;
+	struct net_if *iface = net_if_lookup_by_dev(dev);
+	struct net_if *iface_conduit = dsa_switch_ctx->iface_conduit;
+	const struct device *dev_conduit = net_if_get_device(iface_conduit);
+	const struct ethernet_api *eth_api_conduit = dev_conduit->api;
+	/* Tag protocol handles pkt first */
+	struct net_pkt *dsa_pkt = dsa_tag_xmit(iface, pkt);
+
+	/* Transmit from conduit port */
+	return eth_api_conduit->send(dev_conduit, dsa_pkt);
+}
+
+int dsa_eth_init(struct net_if *iface)
+{
+	struct ethernet_context *eth_ctx = net_if_l2_data(iface);
+
+	if (eth_ctx->dsa_port == DSA_CONDUIT_PORT) {
+		net_if_flag_clear(iface, NET_IF_IPV4);
+		net_if_flag_clear(iface, NET_IF_IPV6);
+	}
+
+	return 0;
+}
diff --git a/subsys/net/l2/ethernet/dsa/dsa_port.c b/subsys/net/l2/ethernet/dsa/dsa_port.c
new file mode 100644
index 00000000000..33f9b156e05
--- /dev/null
+++ b/subsys/net/l2/ethernet/dsa/dsa_port.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(net_dsa_port, CONFIG_NET_DSA_LOG_LEVEL);
+
+#include <zephyr/net/ethernet.h>
+#include <zephyr/net/phy.h>
+#include <zephyr/net/dsa_core.h>
+
+#if defined(CONFIG_NET_INTERFACE_NAME_LEN)
+#define INTERFACE_NAME_LEN CONFIG_NET_INTERFACE_NAME_LEN
+#else
+#define INTERFACE_NAME_LEN 10
+#endif
+
+int dsa_port_initialize(const struct device *dev)
+{
+	const struct dsa_port_config *cfg = dev->config;
+	struct dsa_switch_context *dsa_switch_ctx = dev->data;
+	struct net_if *iface = net_if_lookup_by_dev(dev);
+	struct ethernet_context *eth_ctx = net_if_l2_data(iface);
+	struct ethernet_context *eth_ctx_conduit = NULL;
+	int err = 0;
+
+	dsa_switch_ctx->init_ports++;
+
+	/* Find conduit port */
+	if (dsa_switch_ctx->iface_conduit == NULL && cfg->ethernet_connection != NULL) {
+		dsa_switch_ctx->iface_conduit = net_if_lookup_by_dev(cfg->ethernet_connection);
+		if (dsa_switch_ctx->iface_conduit == NULL) {
+			LOG_ERR("DSA: Conduit iface NOT found!");
+		}
+
+		eth_ctx->dsa_port = DSA_CPU_PORT;
+
+		/*
+		 * Provide pointer to DSA switch context to conduit's eth interface
+		 * struct ethernet_context
+		 */
+		eth_ctx_conduit = net_if_l2_data(dsa_switch_ctx->iface_conduit);
+		eth_ctx_conduit->dsa_switch_ctx = dsa_switch_ctx;
+		eth_ctx_conduit->dsa_port = DSA_CONDUIT_PORT;
+	}
+
+	if (cfg->ethernet_connection == NULL) {
+		eth_ctx->dsa_port = DSA_USER_PORT;
+		eth_ctx->dsa_switch_ctx = dsa_switch_ctx;
+		dsa_switch_ctx->iface_user[cfg->port_idx] = iface;
+	}
+
+	if (dsa_switch_ctx->dapi->port_init != NULL) {
+		err = dsa_switch_ctx->dapi->port_init(dev);
+		if (err != 0) {
+			goto out;
+		}
+	}
+
+out:
+	/* All ports are initialized. May need switch setup. */
+	if (dsa_switch_ctx->init_ports == dsa_switch_ctx->num_ports) {
+		if (dsa_switch_ctx->dapi->switch_setup != NULL) {
+			err = dsa_switch_ctx->dapi->switch_setup(dsa_switch_ctx);
+		}
+	}
+
+	return err;
+}
+
+static void dsa_port_iface_init(struct net_if *iface)
+{
+	const struct device *dev = net_if_get_device(iface);
+	struct dsa_port_config *cfg = (struct dsa_port_config *)dev->config;
+	struct dsa_switch_context *dsa_switch_ctx = dev->data;
+	char name[INTERFACE_NAME_LEN];
+
+	/* Set interface name */
+	snprintf(name, sizeof(name), "swp%d", cfg->port_idx);
+	net_if_set_name(iface, name);
+
+	/* Use random mac address if could */
+	if (cfg->use_random_mac_addr && dsa_switch_ctx->dapi->port_generate_random_mac != NULL) {
+		dsa_switch_ctx->dapi->port_generate_random_mac(cfg->mac_addr);
+	}
+
+	net_if_set_link_addr(iface, cfg->mac_addr, sizeof(cfg->mac_addr), NET_LINK_ETHERNET);
+
+	if (cfg->ethernet_connection != NULL) {
+		net_if_carrier_off(iface);
+		return;
+	}
+
+	/*
+	 * Initialize ethernet context 'work' for this iface to
+	 * be able to monitor the carrier status.
+	 */
+	ethernet_init(iface);
+
+	/* Do not start the interface until link is up */
+	net_if_carrier_off(iface);
+
+	if (!device_is_ready(cfg->phy_dev)) {
+		LOG_ERR("PHY device (%p) is not ready, cannot init iface", cfg->phy_dev);
+		return;
+	}
+
+	if (dsa_switch_ctx->dapi->port_phylink_change == NULL) {
+		LOG_ERR("require port_phylink_change callback");
+		return;
+	}
+
+	phy_link_callback_set(cfg->phy_dev, dsa_switch_ctx->dapi->port_phylink_change, (void *)dev);
+}
+
+static const struct device *dsa_port_get_phy(const struct device *dev)
+{
+	const struct dsa_port_config *cfg = dev->config;
+
+	return cfg->phy_dev;
+}
+
+const struct ethernet_api dsa_eth_api = {
+	.iface_api.init = dsa_port_iface_init,
+	.get_phy = dsa_port_get_phy,
+	.send = dsa_xmit,
+};
diff --git a/subsys/net/l2/ethernet/dsa/dsa_tag.c b/subsys/net/l2/ethernet/dsa/dsa_tag.c
new file mode 100644
index 00000000000..b63d901d2bb
--- /dev/null
+++ b/subsys/net/l2/ethernet/dsa/dsa_tag.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/net/ethernet.h>
+#include <zephyr/net/dsa_core.h>
+
+struct net_if *dsa_tag_recv(struct net_if *iface, struct net_pkt *pkt)
+{
+	const struct ethernet_context *eth_ctx = net_if_l2_data(iface);
+	const struct dsa_switch_context *dsa_switch_ctx = eth_ctx->dsa_switch_ctx;
+
+	/* For no tag type, use NULL recv to let host ethernet driver handle. */
+	if (dsa_switch_ctx->dapi->recv == NULL) {
+		return iface;
+	}
+
+	return dsa_switch_ctx->dapi->recv(iface, pkt);
+}
+
+struct net_pkt *dsa_tag_xmit(struct net_if *iface, struct net_pkt *pkt)
+{
+	const struct device *dev = net_if_get_device(iface);
+	const struct dsa_switch_context *dsa_switch_ctx = dev->data;
+
+	/* For no tag type, use NULL xmit to let host ethernet driver handle. */
+	if (dsa_switch_ctx->dapi->xmit == NULL) {
+		/* Here utilize iface field to store origin user port iface.
+		 * Host ethernet driver needs to handle then.
+		 */
+		pkt->iface = iface;
+		return pkt;
+	}
+
+	return dsa_switch_ctx->dapi->xmit(iface, pkt);
+}
diff --git a/subsys/net/l2/ethernet/dsa/dsa_tag.h b/subsys/net/l2/ethernet/dsa/dsa_tag.h
new file mode 100644
index 00000000000..3728fa991e6
--- /dev/null
+++ b/subsys/net/l2/ethernet/dsa/dsa_tag.h
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_SUBSYS_DSA_TAG_PRIV_H_
+#define ZEPHYR_SUBSYS_DSA_TAG_PRIV_H_
+
+struct net_if *dsa_tag_recv(struct net_if *iface, struct net_pkt *pkt);
+struct net_pkt *dsa_tag_xmit(struct net_if *iface, struct net_pkt *pkt);
+
+#endif
diff --git a/subsys/net/l2/ethernet/dsa/dsa_user.c b/subsys/net/l2/ethernet/dsa/dsa_user.c
new file mode 100644
index 00000000000..3eee505d126
--- /dev/null
+++ b/subsys/net/l2/ethernet/dsa/dsa_user.c
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(net_dsa_user, CONFIG_NET_DSA_LOG_LEVEL);
+
+#include <zephyr/net/ethernet.h>
+#include <zephyr/net/dsa_core.h>
+
+struct net_if *dsa_user_get_iface(struct net_if *iface, int port_idx)
+{
+	struct ethernet_context *eth_ctx = net_if_l2_data(iface);
+	struct dsa_switch_context *dsa_switch_ctx;
+
+	if (eth_ctx == NULL || eth_ctx->dsa_switch_ctx == NULL) {
+		LOG_ERR("Iface %p context not available!", iface);
+		return NULL;
+	}
+
+	dsa_switch_ctx = eth_ctx->dsa_switch_ctx;
+
+	if (port_idx < 0 || port_idx >= dsa_switch_ctx->num_ports) {
+		return NULL;
+	}
+
+	return dsa_switch_ctx->iface_user[port_idx];
+}
diff --git a/subsys/net/l2/ethernet/ethernet.c b/subsys/net/l2/ethernet/ethernet.c
index 890940f87fc..2e95b0ed216 100644
--- a/subsys/net/l2/ethernet/ethernet.c
+++ b/subsys/net/l2/ethernet/ethernet.c
@@ -122,6 +122,14 @@ static inline void ethernet_update_length(struct net_if *iface,
 					  struct net_pkt *pkt)
 {
 	uint16_t len;
+#ifdef CONFIG_NET_VLAN
+	const uint16_t min_len =
+		NET_ETH_MINIMAL_FRAME_SIZE - (net_pkt_vlan_tag(pkt) != NET_VLAN_TAG_UNSPEC
+						      ? sizeof(struct net_eth_vlan_hdr)
+						      : sizeof(struct net_eth_hdr));
+#else
+	const uint16_t min_len = NET_ETH_MINIMAL_FRAME_SIZE - sizeof(struct net_eth_hdr);
+#endif
 
 	/* Let's check IP payload's length. If it's smaller than 46 bytes,
 	 * i.e. smaller than minimal Ethernet frame size minus ethernet
@@ -131,11 +139,13 @@ static inline void ethernet_update_length(struct net_if *iface,
 
 	if (net_pkt_family(pkt) == AF_INET) {
 		len = ntohs(NET_IPV4_HDR(pkt)->len);
-	} else {
+	} else if (net_pkt_family(pkt) == AF_INET6) {
 		len = ntohs(NET_IPV6_HDR(pkt)->len) + NET_IPV6H_LEN;
+	} else {
+		return;
 	}
 
-	if (len < NET_ETH_MINIMAL_FRAME_SIZE - sizeof(struct net_eth_hdr)) {
+	if (len < min_len) {
 		struct net_buf *frag;
 
 		for (frag = pkt->frags; frag; frag = frag->frags) {
@@ -149,19 +159,21 @@ static inline void ethernet_update_length(struct net_if *iface,
 	}
 }
 
-static void ethernet_update_rx_stats(struct net_if *iface,
-				     struct net_eth_hdr *hdr, size_t length)
+
+static void ethernet_update_rx_stats(struct net_if *iface, size_t length,
+				     bool dst_broadcast, bool dst_eth_multicast)
 {
-#if defined(CONFIG_NET_STATISTICS_ETHERNET)
+	if (!IS_ENABLED(CONFIG_NET_STATISTICS_ETHERNET)) {
+		return;
+	}
+
 	eth_stats_update_bytes_rx(iface, length);
 	eth_stats_update_pkts_rx(iface);
-
-	if (net_eth_is_addr_broadcast(&hdr->dst)) {
+	if (dst_broadcast) {
 		eth_stats_update_broadcast_rx(iface);
-	} else if (net_eth_is_addr_multicast(&hdr->dst)) {
+	} else if (dst_eth_multicast) {
 		eth_stats_update_multicast_rx(iface);
 	}
-#endif /* CONFIG_NET_STATISTICS_ETHERNET */
 }
 
 static inline bool eth_is_vlan_tag_stripped(struct net_if *iface)
@@ -169,6 +181,7 @@ static inline bool eth_is_vlan_tag_stripped(struct net_if *iface)
 	return (net_eth_get_hw_capabilities(iface) & ETHERNET_HW_VLAN_TAG_STRIP);
 }
 
+#if defined(CONFIG_NET_IPV4) || defined(CONFIG_NET_IPV6)
 /* Drop packet if it has broadcast destination MAC address but the IP
  * address is not multicast or broadcast address. See RFC 1122 ch 3.3.6
  */
@@ -189,6 +202,7 @@ enum net_verdict ethernet_check_ipv4_bcast_addr(struct net_pkt *pkt,
 
 	return NET_OK;
 }
+#endif
 
 #if defined(CONFIG_NET_NATIVE_IP) && !defined(CONFIG_NET_RAW_MODE)
 static void ethernet_mcast_monitor_cb(struct net_if *iface, const struct net_addr *addr,
@@ -240,12 +254,15 @@ static enum net_verdict ethernet_recv(struct net_if *iface,
 				      struct net_pkt *pkt)
 {
 	struct ethernet_context *ctx = net_if_l2_data(iface);
-	struct net_eth_hdr *hdr = NET_ETH_HDR(pkt);
 	uint8_t hdr_len = sizeof(struct net_eth_hdr);
-	uint16_t type;
-	struct net_linkaddr *lladdr;
-	sa_family_t family = AF_UNSPEC;
+	size_t body_len;
+	struct net_eth_hdr *hdr = NET_ETH_HDR(pkt);
+	enum net_verdict verdict = NET_CONTINUE;
 	bool is_vlan_pkt = false;
+	bool handled = false;
+	struct net_linkaddr *lladdr;
+	uint16_t type;
+	bool dst_broadcast, dst_eth_multicast, dst_iface_addr;
 
 	/* This expects that the Ethernet header is in the first net_buf
 	 * fragment. This is a safe expectation here as it would not make
@@ -284,87 +301,58 @@ static enum net_verdict ethernet_recv(struct net_if *iface,
 		    !eth_is_vlan_tag_stripped(iface)) {
 			struct net_eth_vlan_hdr *hdr_vlan =
 				(struct net_eth_vlan_hdr *)NET_ETH_HDR(pkt);
-			enum net_verdict verdict;
+			struct net_if *vlan_iface;
 
 			net_pkt_set_vlan_tci(pkt, ntohs(hdr_vlan->vlan.tci));
 			type = ntohs(hdr_vlan->type);
 			hdr_len = sizeof(struct net_eth_vlan_hdr);
 			is_vlan_pkt = true;
 
-			net_pkt_set_iface(pkt,
-					  net_eth_get_vlan_iface(iface,
-						       net_pkt_vlan_tag(pkt)));
-
 			/* If we receive a packet with a VLAN tag, for that we don't
 			 * have a VLAN interface, drop the packet.
 			 */
+			vlan_iface = net_eth_get_vlan_iface(iface,
+							    net_pkt_vlan_tag(pkt));
+			if (vlan_iface == NULL) {
+				NET_DBG("Dropping frame, no VLAN interface for tag %d",
+					net_pkt_vlan_tag(pkt));
+				goto drop;
+			}
+
+			net_pkt_set_iface(pkt, vlan_iface);
+
 			if (net_if_l2(net_pkt_iface(pkt)) == NULL) {
 				goto drop;
 			}
 
-			/* We could call VLAN interface directly but then the
-			 * interface statistics would not get updated so route
-			 * the call via Virtual L2 layer.
-			 */
-			if (net_if_l2(net_pkt_iface(pkt))->recv != NULL) {
-				verdict = net_if_l2(net_pkt_iface(pkt))->recv(iface, pkt);
-				if (verdict == NET_DROP) {
-					goto drop;
+			if (net_pkt_vlan_tag(pkt) != NET_VLAN_TAG_PRIORITY) {
+				/* We could call VLAN interface directly but then the
+				 * interface statistics would not get updated so route
+				 * the call via Virtual L2 layer.
+				 */
+				if (net_if_l2(net_pkt_iface(pkt))->recv != NULL) {
+					verdict = net_if_l2(net_pkt_iface(pkt))->recv(iface, pkt);
+					if (verdict == NET_DROP) {
+						goto drop;
+					}
 				}
 			}
 		}
 	}
 
-	switch (type) {
-	case NET_ETH_PTYPE_IP:
-	case NET_ETH_PTYPE_ARP:
-		net_pkt_set_family(pkt, AF_INET);
-		family = AF_INET;
-		break;
-	case NET_ETH_PTYPE_IPV6:
-		net_pkt_set_family(pkt, AF_INET6);
-		family = AF_INET6;
-		break;
-	case NET_ETH_PTYPE_EAPOL:
-		family = AF_UNSPEC;
-		break;
-#if defined(CONFIG_NET_L2_PTP)
-	case NET_ETH_PTYPE_PTP:
-		family = AF_UNSPEC;
-		break;
-#endif
-	case NET_ETH_PTYPE_LLDP:
-#if defined(CONFIG_NET_LLDP)
-		net_buf_pull(pkt->frags, hdr_len);
-		return net_lldp_recv(iface, pkt);
-#else
-		NET_DBG("LLDP Rx agent not enabled");
-		goto drop;
-#endif
-	default:
-		if (IS_ENABLED(CONFIG_NET_ETHERNET_FORWARD_UNRECOGNISED_ETHERTYPE)) {
-			family = AF_UNSPEC;
-			break;
-		}
-
-		NET_DBG("Unknown hdr type 0x%04x iface %d (%p)", type,
-			net_if_get_by_iface(iface), iface);
-		eth_stats_update_unknown_protocol(iface);
-		return NET_DROP;
-	}
-
 	/* Set the pointers to ll src and dst addresses */
-	lladdr = net_pkt_lladdr_src(pkt);
-	lladdr->addr = hdr->src.addr;
-	lladdr->len = sizeof(struct net_eth_addr);
-	lladdr->type = NET_LINK_ETHERNET;
+	(void)net_linkaddr_create(net_pkt_lladdr_src(pkt), hdr->src.addr,
+				  sizeof(struct net_eth_addr), NET_LINK_ETHERNET);
+
+	(void)net_linkaddr_create(net_pkt_lladdr_dst(pkt), hdr->dst.addr,
+				  sizeof(struct net_eth_addr), NET_LINK_ETHERNET);
 
 	lladdr = net_pkt_lladdr_dst(pkt);
-	lladdr->addr = hdr->dst.addr;
-	lladdr->len = sizeof(struct net_eth_addr);
-	lladdr->type = NET_LINK_ETHERNET;
 
 	net_pkt_set_ll_proto_type(pkt, type);
+	dst_broadcast = net_eth_is_addr_broadcast((struct net_eth_addr *)lladdr->addr);
+	dst_eth_multicast = net_eth_is_addr_group((struct net_eth_addr *)lladdr->addr);
+	dst_iface_addr = net_linkaddr_cmp(net_if_get_link_addr(iface), lladdr);
 
 	if (is_vlan_pkt) {
 		print_vlan_ll_addrs(pkt, type, net_pkt_vlan_tci(pkt),
@@ -378,12 +366,7 @@ static enum net_verdict ethernet_recv(struct net_if *iface,
 			       net_pkt_lladdr_dst(pkt));
 	}
 
-	if (!net_eth_is_addr_broadcast((struct net_eth_addr *)lladdr->addr) &&
-	    !net_eth_is_addr_multicast((struct net_eth_addr *)lladdr->addr) &&
-	    !net_eth_is_addr_lldp_multicast(
-		    (struct net_eth_addr *)lladdr->addr) &&
-	    !net_eth_is_addr_ptp_multicast((struct net_eth_addr *)lladdr->addr) &&
-	    !net_linkaddr_cmp(net_if_get_link_addr(iface), lladdr)) {
+	if (!(dst_broadcast || dst_eth_multicast || dst_iface_addr)) {
 		/* The ethernet frame is not for me as the link addresses
 		 * are different.
 		 */
@@ -393,44 +376,93 @@ static enum net_verdict ethernet_recv(struct net_if *iface,
 		goto drop;
 	}
 
+	/* Get rid of the Ethernet header. */
 	net_buf_pull(pkt->frags, hdr_len);
 
-	if (IS_ENABLED(CONFIG_NET_IPV4) && type == NET_ETH_PTYPE_IP &&
-	    ethernet_check_ipv4_bcast_addr(pkt, hdr) == NET_DROP) {
-		goto drop;
-	}
+	body_len = net_pkt_get_len(pkt);
 
-	ethernet_update_rx_stats(iface, hdr, net_pkt_get_len(pkt) + hdr_len);
+	STRUCT_SECTION_FOREACH(net_l3_register, l3) {
+		if (l3->ptype != type || l3->l2 != &NET_L2_GET_NAME(ETHERNET) ||
+		    l3->handler == NULL) {
+			continue;
+		}
 
-	if (IS_ENABLED(CONFIG_NET_ARP) &&
-	    family == AF_INET && type == NET_ETH_PTYPE_ARP) {
-		NET_DBG("ARP packet from %s received",
-			net_sprint_ll_addr((uint8_t *)hdr->src.addr,
-					   sizeof(struct net_eth_addr)));
+		NET_DBG("Calling L3 %s handler for type 0x%04x iface %d (%p)",
+			l3->name, type, net_if_get_by_iface(iface), iface);
 
-		if (IS_ENABLED(CONFIG_NET_IPV4_ACD) &&
-		    net_ipv4_acd_input(iface, pkt) == NET_DROP) {
-			return NET_DROP;
+		verdict = l3->handler(iface, type, pkt);
+		if (verdict == NET_OK) {
+			/* the packet was consumed by the l3-handler */
+			goto out;
+		} else if (verdict == NET_DROP) {
+			NET_DBG("Dropping frame, packet rejected by %s", l3->name);
+			goto drop;
 		}
 
-		return net_arp_input(pkt, hdr);
+		/* The packet will be processed further by IP-stack
+		 * when NET_CONTINUE is returned
+		 */
+		handled = true;
+		break;
 	}
 
-	if (IS_ENABLED(CONFIG_NET_GPTP) && type == NET_ETH_PTYPE_PTP) {
-		return net_gptp_recv(iface, pkt);
+	if (!handled) {
+		if (IS_ENABLED(CONFIG_NET_ETHERNET_FORWARD_UNRECOGNISED_ETHERTYPE)) {
+			net_pkt_set_family(pkt, AF_UNSPEC);
+		} else {
+			NET_DBG("Unknown hdr type 0x%04x iface %d (%p)", type,
+				net_if_get_by_iface(iface), iface);
+			eth_stats_update_unknown_protocol(iface);
+			return NET_DROP;
+		}
 	}
 
 	if (type != NET_ETH_PTYPE_EAPOL) {
 		ethernet_update_length(iface, pkt);
 	}
 
-	return NET_CONTINUE;
+out:
+	ethernet_update_rx_stats(iface, body_len + hdr_len, dst_broadcast, dst_eth_multicast);
+	return verdict;
 drop:
 	eth_stats_update_errors_rx(iface);
 	return NET_DROP;
 }
 
+#if defined(CONFIG_NET_IPV4) || defined(CONFIG_NET_IPV6)
+static enum net_verdict ethernet_ip_recv(struct net_if *iface,
+					 uint16_t ptype,
+					 struct net_pkt *pkt)
+{
+	ARG_UNUSED(iface);
+
+	if (ptype == NET_ETH_PTYPE_IP) {
+		struct net_eth_hdr *hdr = NET_ETH_HDR(pkt);
+
+		if (ethernet_check_ipv4_bcast_addr(pkt, hdr) == NET_DROP) {
+			return NET_DROP;
+		}
+
+		net_pkt_set_family(pkt, AF_INET);
+	} else if (ptype == NET_ETH_PTYPE_IPV6) {
+		net_pkt_set_family(pkt, AF_INET6);
+	} else {
+		return NET_DROP;
+	}
+
+	return NET_CONTINUE;
+}
+#endif /* CONFIG_NET_IPV4 || CONFIG_NET_IPV6 */
+
 #ifdef CONFIG_NET_IPV4
+ETH_NET_L3_REGISTER(IPv4, NET_ETH_PTYPE_IP, ethernet_ip_recv);
+#endif
+
+#if defined(CONFIG_NET_IPV6)
+ETH_NET_L3_REGISTER(IPv6, NET_ETH_PTYPE_IPV6, ethernet_ip_recv);
+#endif /* CONFIG_NET_IPV6 */
+
+#if defined(CONFIG_NET_IPV4)
 static inline bool ethernet_ipv4_dst_is_broadcast_or_mcast(struct net_pkt *pkt)
 {
 	if (net_ipv4_is_addr_bcast(net_pkt_iface(pkt),
@@ -457,8 +489,9 @@ static bool ethernet_fill_in_dst_on_ipv4_mcast(struct net_pkt *pkt,
 	return false;
 }
 
-static struct net_pkt *ethernet_ll_prepare_on_ipv4(struct net_if *iface,
-						   struct net_pkt *pkt)
+static int ethernet_ll_prepare_on_ipv4(struct net_if *iface,
+				       struct net_pkt *pkt,
+				       struct net_pkt **out)
 {
 	struct ethernet_context *ctx = net_if_l2_data(iface);
 
@@ -471,34 +504,19 @@ static struct net_pkt *ethernet_ll_prepare_on_ipv4(struct net_if *iface,
 	}
 
 	if (ethernet_ipv4_dst_is_broadcast_or_mcast(pkt)) {
-		return pkt;
+		return NET_ARP_COMPLETE;
 	}
 
 	if (IS_ENABLED(CONFIG_NET_ARP)) {
-		struct net_pkt *arp_pkt;
-
-		arp_pkt = net_arp_prepare(pkt, (struct in_addr *)NET_IPV4_HDR(pkt)->dst, NULL);
-		if (!arp_pkt) {
-			return NULL;
-		}
-
-		if (pkt != arp_pkt) {
-			NET_DBG("Sending arp pkt %p (orig %p) to iface %d (%p)",
-				arp_pkt, pkt, net_if_get_by_iface(iface), iface);
-			net_pkt_unref(pkt);
-			return arp_pkt;
-		}
-
-		NET_DBG("Found ARP entry, sending pkt %p to iface %d (%p)",
-			pkt, net_if_get_by_iface(iface), iface);
+		return net_arp_prepare(pkt, (struct in_addr *)NET_IPV4_HDR(pkt)->dst, NULL, out);
 	}
 
-	return pkt;
+	return NET_ARP_COMPLETE;
 }
 #else
 #define ethernet_ipv4_dst_is_broadcast_or_mcast(...) false
 #define ethernet_fill_in_dst_on_ipv4_mcast(...) false
-#define ethernet_ll_prepare_on_ipv4(...) NULL
+#define ethernet_ll_prepare_on_ipv4(...) NET_ARP_COMPLETE
 #endif /* CONFIG_NET_IPV4 */
 
 #ifdef CONFIG_NET_IPV6
@@ -646,11 +664,14 @@ static struct net_buf *ethernet_fill_header(struct ethernet_context *ctx,
 	return hdr_frag;
 }
 
-#if defined(CONFIG_NET_STATISTICS_ETHERNET)
 static void ethernet_update_tx_stats(struct net_if *iface, struct net_pkt *pkt)
 {
 	struct net_eth_hdr *hdr = NET_ETH_HDR(pkt);
 
+	if (!IS_ENABLED(CONFIG_NET_STATISTICS_ETHERNET)) {
+		return;
+	}
+
 	eth_stats_update_bytes_tx(iface, net_pkt_get_len(pkt));
 	eth_stats_update_pkts_tx(iface);
 
@@ -660,17 +681,14 @@ static void ethernet_update_tx_stats(struct net_if *iface, struct net_pkt *pkt)
 		eth_stats_update_broadcast_tx(iface);
 	}
 }
-#else
-#define ethernet_update_tx_stats(...)
-#endif /* CONFIG_NET_STATISTICS_ETHERNET */
 
 static int ethernet_send(struct net_if *iface, struct net_pkt *pkt)
 {
 	const struct ethernet_api *api = net_if_get_device(iface)->api;
 	struct ethernet_context *ctx = net_if_l2_data(iface);
-	uint16_t ptype = 0;
-	int ret;
+	uint16_t ptype = htons(net_pkt_ll_proto_type(pkt));
 	struct net_pkt *orig_pkt = pkt;
+	int ret;
 
 	if (!api) {
 		ret = -ENOENT;
@@ -690,65 +708,51 @@ static int ethernet_send(struct net_if *iface, struct net_pkt *pkt)
 		goto send;
 	}
 
-	if (IS_ENABLED(CONFIG_NET_IPV4) &&
-	    net_pkt_family(pkt) == AF_INET) {
-		struct net_pkt *tmp;
+	if (IS_ENABLED(CONFIG_NET_IPV4) && net_pkt_family(pkt) == AF_INET &&
+	    net_pkt_ll_proto_type(pkt) == NET_ETH_PTYPE_IP) {
+		if (!net_pkt_ipv4_acd(pkt)) {
+			struct net_pkt *arp;
 
-		if (net_pkt_ipv4_acd(pkt)) {
-			ptype = htons(NET_ETH_PTYPE_ARP);
-		} else {
-			tmp = ethernet_ll_prepare_on_ipv4(iface, pkt);
-			if (!tmp) {
-				ret = -ENOMEM;
-				goto error;
-			} else if (IS_ENABLED(CONFIG_NET_ARP) && tmp != pkt) {
+			ret = ethernet_ll_prepare_on_ipv4(iface, pkt, &arp);
+			if (ret == NET_ARP_COMPLETE) {
+				/* ARP resolution complete, packet ready to send */
+				NET_DBG("Found ARP entry, sending pkt %p to iface %d (%p)",
+					pkt, net_if_get_by_iface(iface), iface);
+			} else if (ret == NET_ARP_PKT_REPLACED) {
 				/* Original pkt got queued and is replaced
 				 * by an ARP request packet.
 				 */
-				pkt = tmp;
-				ptype = htons(NET_ETH_PTYPE_ARP);
-				net_pkt_set_family(pkt, AF_INET);
+				NET_DBG("Sending arp pkt %p (orig %p) to iface %d (%p)",
+					arp, pkt, net_if_get_by_iface(iface), iface);
+				net_pkt_unref(pkt);
+				pkt = arp;
+				ptype = htons(net_pkt_ll_proto_type(pkt));
+			} else if (ret == NET_ARP_PKT_QUEUED) {
+				/* Original pkt got queued, pending resolution
+				 * of an ongoing ARP request.
+				 */
+				NET_DBG("Pending ARP request, pkt %p queued", pkt);
+				net_pkt_unref(pkt);
+				ret = 0;
+				goto error;
 			} else {
-				ptype = htons(NET_ETH_PTYPE_IP);
+				__ASSERT_NO_MSG(ret < 0);
+				goto error;
 			}
 		}
-	} else if (IS_ENABLED(CONFIG_NET_IPV6) &&
-		   net_pkt_family(pkt) == AF_INET6) {
-		ptype = htons(NET_ETH_PTYPE_IPV6);
 	} else if (IS_ENABLED(CONFIG_NET_SOCKETS_PACKET) &&
 		   net_pkt_family(pkt) == AF_PACKET) {
 		struct net_context *context = net_pkt_context(pkt);
 
-		if (context && net_context_get_type(context) == SOCK_DGRAM) {
-			struct sockaddr_ll *dst_addr;
-			struct sockaddr_ll_ptr *src_addr;
-
-			/* The destination address is set in remote for this
-			 * socket type.
-			 */
-			dst_addr = (struct sockaddr_ll *)&context->remote;
-			src_addr = (struct sockaddr_ll_ptr *)&context->local;
-
-			net_pkt_lladdr_dst(pkt)->addr = dst_addr->sll_addr;
-			net_pkt_lladdr_dst(pkt)->len =
-						sizeof(struct net_eth_addr);
-			net_pkt_lladdr_src(pkt)->addr = src_addr->sll_addr;
-			net_pkt_lladdr_src(pkt)->len =
-						sizeof(struct net_eth_addr);
-			ptype = dst_addr->sll_protocol;
-		} else {
+		if (!(context && net_context_get_type(context) == SOCK_DGRAM)) {
+			/* Raw packet, just send it */
 			goto send;
 		}
-	} else if (IS_ENABLED(CONFIG_NET_L2_PTP) && net_pkt_is_ptp(pkt)) {
-		ptype = htons(NET_ETH_PTYPE_PTP);
-	} else if (IS_ENABLED(CONFIG_NET_LLDP) && net_pkt_is_lldp(pkt)) {
-		ptype = htons(NET_ETH_PTYPE_LLDP);
-	} else if (IS_ENABLED(CONFIG_NET_ARP)) {
-		/* Unknown type: Unqueued pkt is an ARP reply.
-		 */
-		ptype = htons(NET_ETH_PTYPE_ARP);
-		net_pkt_set_family(pkt, AF_INET);
-	} else {
+	}
+
+	if (ptype == 0) {
+		/* Caller of this function has not set the ptype */
+		NET_ERR("No protocol set for pkt %p", pkt);
 		ret = -ENOTSUP;
 		goto error;
 	}
@@ -757,9 +761,10 @@ static int ethernet_send(struct net_if *iface, struct net_pkt *pkt)
 	 * temporarily it's a broadcast one. When filling the header,
 	 * it might detect this should be multicast and act accordingly.
 	 */
-	if (!net_pkt_lladdr_dst(pkt)->addr) {
-		net_pkt_lladdr_dst(pkt)->addr = (uint8_t *)broadcast_eth_addr.addr;
-		net_pkt_lladdr_dst(pkt)->len = sizeof(struct net_eth_addr);
+	if (net_pkt_lladdr_dst(pkt)->len == 0) {
+		(void)net_linkaddr_set(net_pkt_lladdr_dst(pkt),
+				       broadcast_eth_addr.addr,
+				       sizeof(struct net_eth_addr));
 	}
 
 	/* Then set the ethernet header. Note that the iface parameter tells
@@ -1085,6 +1090,11 @@ void ethernet_init(struct net_if *iface)
 	NET_DBG("Initializing Ethernet L2 %p for iface %d (%p)", ctx,
 		net_if_get_by_iface(iface), iface);
 
+#if defined(CONFIG_NET_DSA) && !defined(CONFIG_NET_DSA_DEPRECATED)
+	/* DSA port may need to handle flags */
+	dsa_eth_init(iface);
+#endif
+
 	ctx->ethernet_l2_flags = NET_L2_MULTICAST;
 	ctx->iface = iface;
 	k_work_init(&ctx->carrier_work, carrier_on_off);
diff --git a/subsys/net/l2/ethernet/ethernet_mgmt.c b/subsys/net/l2/ethernet/ethernet_mgmt.c
index 93183c3b10d..3979ef88a32 100644
--- a/subsys/net/l2/ethernet/ethernet_mgmt.c
+++ b/subsys/net/l2/ethernet/ethernet_mgmt.c
@@ -90,7 +90,7 @@ static int ethernet_set_config(uint32_t mgmt_request,
 		config.full_duplex = params->full_duplex;
 		type = ETHERNET_CONFIG_TYPE_DUPLEX;
 	} else if (mgmt_request == NET_REQUEST_ETHERNET_SET_MAC_ADDRESS) {
-		if (net_if_is_up(iface)) {
+		if (net_if_is_admin_up(iface)) {
 			return -EACCES;
 		}
 
diff --git a/subsys/net/l2/ethernet/gptp/gptp.c b/subsys/net/l2/ethernet/gptp/gptp.c
index 81fda33f113..e22b10c515d 100644
--- a/subsys/net/l2/ethernet/gptp/gptp.c
+++ b/subsys/net/l2/ethernet/gptp/gptp.c
@@ -320,10 +320,20 @@ static void gptp_handle_msg(struct net_pkt *pkt)
 	}
 }
 
-enum net_verdict net_gptp_recv(struct net_if *iface, struct net_pkt *pkt)
+static enum net_verdict net_gptp_recv(struct net_if *iface, uint16_t ptype,
+				      struct net_pkt *pkt)
 {
 	struct gptp_hdr *hdr = GPTP_HDR(pkt);
 
+	ARG_UNUSED(ptype);
+
+	if (!(net_eth_is_addr_ptp_multicast(
+		      (struct net_eth_addr *)net_pkt_lladdr_dst(pkt)->addr) ||
+	      net_eth_is_addr_lldp_multicast(
+		      (struct net_eth_addr *)net_pkt_lladdr_dst(pkt)->addr))) {
+		return NET_DROP;
+	}
+
 	if ((hdr->ptp_version != GPTP_VERSION) ||
 			(hdr->transport_specific != GPTP_TRANSPORT_802_1_AS)) {
 		/* The stack only supports PTP V2 and transportSpecific set
@@ -346,6 +356,8 @@ enum net_verdict net_gptp_recv(struct net_if *iface, struct net_pkt *pkt)
 	return NET_DROP;
 }
 
+ETH_NET_L3_REGISTER(gPTP, NET_ETH_PTYPE_PTP, net_gptp_recv);
+
 static void gptp_init_clock_ds(void)
 {
 	struct gptp_global_ds *global_ds;
@@ -574,7 +586,7 @@ static void gptp_thread(void *p1, void *p2, void *p3)
 
 static void gptp_add_port(struct net_if *iface, void *user_data)
 {
-	int *num_ports = user_data;
+	uint8_t *num_ports = user_data;
 	const struct device *clk;
 
 	if (*num_ports >= CONFIG_NET_GPTP_NUM_PORTS) {
diff --git a/subsys/net/l2/ethernet/gptp/gptp_messages.c b/subsys/net/l2/ethernet/gptp/gptp_messages.c
index 7fe558d8a2c..079940b3ff1 100644
--- a/subsys/net/l2/ethernet/gptp/gptp_messages.c
+++ b/subsys/net/l2/ethernet/gptp/gptp_messages.c
@@ -170,12 +170,14 @@ static struct net_pkt *setup_gptp_frame(struct net_if *iface,
 
 	net_buf_add(pkt->buffer, sizeof(struct gptp_hdr) + extra_header);
 	net_pkt_set_ptp(pkt, true);
+	net_pkt_set_ll_proto_type(pkt, NET_ETH_PTYPE_PTP);
 
-	net_pkt_lladdr_src(pkt)->addr = net_if_get_link_addr(iface)->addr;
-	net_pkt_lladdr_src(pkt)->len = net_if_get_link_addr(iface)->len;
+	(void)net_linkaddr_copy(net_pkt_lladdr_src(pkt),
+				net_if_get_link_addr(iface));
 
-	net_pkt_lladdr_dst(pkt)->addr = (uint8_t *)&gptp_multicast_eth_addr;
-	net_pkt_lladdr_dst(pkt)->len = sizeof(struct net_eth_addr);
+	(void)net_linkaddr_set(net_pkt_lladdr_dst(pkt),
+			       (uint8_t *)&gptp_multicast_eth_addr,
+			       sizeof(struct net_eth_addr));
 
 	return pkt;
 }
diff --git a/subsys/net/l2/ethernet/lldp/lldp.c b/subsys/net/l2/ethernet/lldp/lldp.c
index 8d9f995bc7f..2895691d6f0 100644
--- a/subsys/net/l2/ethernet/lldp/lldp.c
+++ b/subsys/net/l2/ethernet/lldp/lldp.c
@@ -114,6 +114,7 @@ static int lldp_send(struct ethernet_lldp *lldp)
 	}
 
 	net_pkt_set_lldp(pkt, true);
+	net_pkt_set_ll_proto_type(pkt, NET_ETH_PTYPE_LLDP);
 
 	ret = net_pkt_write(pkt, (uint8_t *)lldp->lldpdu,
 			    sizeof(struct net_lldpdu));
@@ -141,12 +142,17 @@ static int lldp_send(struct ethernet_lldp *lldp)
 		}
 	}
 
-	net_pkt_lladdr_src(pkt)->addr = net_if_get_link_addr(lldp->iface)->addr;
-	net_pkt_lladdr_src(pkt)->len = sizeof(struct net_eth_addr);
-	net_pkt_lladdr_dst(pkt)->addr = (uint8_t *)lldp_multicast_eth_addr.addr;
-	net_pkt_lladdr_dst(pkt)->len = sizeof(struct net_eth_addr);
+	(void)net_linkaddr_copy(net_pkt_lladdr_src(pkt),
+				net_if_get_link_addr(lldp->iface));
 
-	if (net_if_send_data(lldp->iface, pkt) == NET_DROP) {
+	(void)net_linkaddr_set(net_pkt_lladdr_dst(pkt),
+			       (uint8_t *)lldp_multicast_eth_addr.addr,
+			       sizeof(struct net_eth_addr));
+
+	/* send without timeout, so we do not risk being blocked by tx when
+	 * being flooded
+	 */
+	if (net_if_try_send_data(lldp->iface, pkt, K_NO_WAIT) == NET_DROP) {
 		net_pkt_unref(pkt);
 		ret = -EIO;
 	}
@@ -264,12 +270,19 @@ static int lldp_start(struct net_if *iface, uint32_t mgmt_event)
 	return 0;
 }
 
-enum net_verdict net_lldp_recv(struct net_if *iface, struct net_pkt *pkt)
+static enum net_verdict net_lldp_recv(struct net_if *iface, uint16_t ptype, struct net_pkt *pkt)
 {
 	struct ethernet_context *ctx;
 	net_lldp_recv_cb_t recv_cb;
 	int ret;
 
+	ARG_UNUSED(ptype);
+
+	if (!net_eth_is_addr_lldp_multicast(
+		    (struct net_eth_addr *)net_pkt_lladdr_dst(pkt)->addr)) {
+		return NET_DROP;
+	}
+
 	ret = lldp_check_iface(iface);
 	if (ret < 0) {
 		return NET_DROP;
@@ -290,6 +303,8 @@ enum net_verdict net_lldp_recv(struct net_if *iface, struct net_pkt *pkt)
 	return NET_DROP;
 }
 
+ETH_NET_L3_REGISTER(LLDP, NET_ETH_PTYPE_LLDP, net_lldp_recv);
+
 int net_lldp_register_callback(struct net_if *iface, net_lldp_recv_cb_t recv_cb)
 {
 	struct ethernet_context *ctx;
diff --git a/subsys/net/l2/ethernet/vlan.c b/subsys/net/l2/ethernet/vlan.c
index a746225ae6b..23c73b40deb 100644
--- a/subsys/net/l2/ethernet/vlan.c
+++ b/subsys/net/l2/ethernet/vlan.c
@@ -26,6 +26,12 @@ LOG_MODULE_REGISTER(net_ethernet_vlan, CONFIG_NET_L2_ETHERNET_LOG_LEVEL);
 #define DEBUG_RX 0
 #endif
 
+/* If the VLAN interface count is 0, then only priority tagged (tag 0)
+ * Ethernet frames can be received. In this case we do not need to
+ * allocate any memory for VLAN interfaces.
+ */
+#if CONFIG_NET_VLAN_COUNT > 0
+
 #define MAX_VLAN_NAME_LEN MIN(sizeof("VLAN-<#####>"), \
 			      CONFIG_NET_INTERFACE_NAME_LEN)
 #define MAX_VIRT_NAME_LEN MIN(sizeof("<not attached>"), \
@@ -214,6 +220,10 @@ struct net_if *net_eth_get_vlan_iface(struct net_if *iface, uint16_t tag)
 
 	ctx = get_vlan(iface, tag);
 	if (ctx == NULL) {
+		if (tag == NET_VLAN_TAG_PRIORITY) {
+			return iface;
+		}
+
 		return NULL;
 	}
 
@@ -438,7 +448,7 @@ int net_eth_vlan_enable(struct net_if *iface, uint16_t tag)
 			continue;
 		}
 
-		NET_DBG("[%d] Adding vlan tag %d to iface %d (%p) attached to %d (%p)",
+		NET_DBG("[%zd] Adding vlan tag %d to iface %d (%p) attached to %d (%p)",
 			i, vlan->tag, net_if_get_by_iface(vlan->iface), vlan->iface,
 			net_if_get_by_iface(iface), iface);
 
@@ -668,3 +678,27 @@ static void vlan_iface_init(struct net_if *iface)
 
 	ctx->init_done = true;
 }
+
+#else /* CONFIG_NET_VLAN_COUNT > 0 */
+
+/* Dummy functions if VLAN is not really used. This is only needed
+ * if priority tagged frames (tag 0) are supported.
+ */
+bool net_eth_is_vlan_enabled(struct ethernet_context *ctx,
+			     struct net_if *iface)
+{
+	ARG_UNUSED(ctx);
+	ARG_UNUSED(iface);
+
+	return true;
+}
+
+struct net_if *net_eth_get_vlan_iface(struct net_if *iface, uint16_t tag)
+{
+	if (tag == NET_VLAN_TAG_PRIORITY) {
+		return iface;
+	}
+
+	return NULL;
+}
+#endif /* CONFIG_NET_VLAN_COUNT > 0 */
diff --git a/subsys/net/l2/ieee802154/ieee802154.c b/subsys/net/l2/ieee802154/ieee802154.c
index 9f34c4701be..4302f1f09fa 100644
--- a/subsys/net/l2/ieee802154/ieee802154.c
+++ b/subsys/net/l2/ieee802154/ieee802154.c
@@ -251,24 +251,27 @@ static inline void swap_and_set_pkt_ll_addr(struct net_linkaddr *addr, bool has_
 					    enum ieee802154_addressing_mode mode,
 					    struct ieee802154_address_field *ll)
 {
-	addr->type = NET_LINK_IEEE802154;
-
 	switch (mode) {
 	case IEEE802154_ADDR_MODE_EXTENDED:
-		addr->len = IEEE802154_EXT_ADDR_LENGTH;
-		addr->addr = has_pan_id ? ll->plain.addr.ext_addr : ll->comp.addr.ext_addr;
+		(void)net_linkaddr_create(
+			addr,
+			has_pan_id ? ll->plain.addr.ext_addr : ll->comp.addr.ext_addr,
+			IEEE802154_EXT_ADDR_LENGTH,
+			NET_LINK_IEEE802154);
 		break;
 
 	case IEEE802154_ADDR_MODE_SHORT:
-		addr->len = IEEE802154_SHORT_ADDR_LENGTH;
-		addr->addr = (uint8_t *)(has_pan_id ? &ll->plain.addr.short_addr
-						    : &ll->comp.addr.short_addr);
+		(void)net_linkaddr_create(
+			addr,
+			(const uint8_t *)(has_pan_id ?
+					  &ll->plain.addr.short_addr : &ll->comp.addr.short_addr),
+			IEEE802154_SHORT_ADDR_LENGTH,
+			NET_LINK_IEEE802154);
 		break;
 
 	case IEEE802154_ADDR_MODE_NONE:
 	default:
-		addr->len = 0U;
-		addr->addr = NULL;
+		(void)net_linkaddr_clear(addr);
 	}
 
 	/* The net stack expects big endian link layer addresses for POSIX compliance
@@ -504,10 +507,13 @@ static int ieee802154_send(struct net_if *iface, struct net_pkt *pkt)
 			struct sockaddr_ll_ptr *src_addr =
 				(struct sockaddr_ll_ptr *)&context->local;
 
-			net_pkt_lladdr_dst(pkt)->addr = dst_addr->sll_addr;
-			net_pkt_lladdr_dst(pkt)->len = dst_addr->sll_halen;
-			net_pkt_lladdr_src(pkt)->addr = src_addr->sll_addr;
-			net_pkt_lladdr_src(pkt)->len = src_addr->sll_halen;
+			(void)net_linkaddr_set(net_pkt_lladdr_dst(pkt),
+					       dst_addr->sll_addr,
+					       dst_addr->sll_halen);
+
+			(void)net_linkaddr_set(net_pkt_lladdr_src(pkt),
+					       src_addr->sll_addr,
+					       src_addr->sll_halen);
 		} else {
 			return -EINVAL;
 		}
diff --git a/subsys/net/l2/ieee802154/ieee802154_frame.c b/subsys/net/l2/ieee802154/ieee802154_frame.c
index b2ef53a9957..73be90d048a 100644
--- a/subsys/net/l2/ieee802154/ieee802154_frame.c
+++ b/subsys/net/l2/ieee802154/ieee802154_frame.c
@@ -449,7 +449,7 @@ void ieee802154_compute_header_and_authtag_len(struct net_if *iface, struct net_
 					       uint8_t *authtag_len)
 {
 	uint8_t hdr_len = sizeof(struct ieee802154_fcf_seq), tag_len = 0;
-	bool broadcast = !dst->addr;
+	bool broadcast = (dst->len == 0);
 
 	/* PAN ID */
 	hdr_len += IEEE802154_PAN_ID_LENGTH;
@@ -458,7 +458,7 @@ void ieee802154_compute_header_and_authtag_len(struct net_if *iface, struct net_
 	hdr_len += broadcast ? IEEE802154_SHORT_ADDR_LENGTH : dst->len;
 
 	/* Source Address - see data_addr_to_fs_settings() */
-	hdr_len += src->addr ? src->len : dst->len;
+	hdr_len += (src->len > 0) ? src->len : dst->len;
 
 #ifdef CONFIG_NET_L2_IEEE802154_SECURITY
 	struct ieee802154_security_ctx *sec_ctx;
@@ -539,7 +539,7 @@ static inline struct ieee802154_fcf_seq *generate_fcf_grounds(uint8_t **p_buf, b
 static inline enum ieee802154_addressing_mode get_dst_addr_mode(struct net_linkaddr *dst,
 								bool *broadcast)
 {
-	if (!dst->addr) {
+	if (dst->len == 0) {
 		NET_DBG("Broadcast destination");
 		*broadcast = true;
 		return IEEE802154_ADDR_MODE_SHORT;
@@ -688,7 +688,7 @@ bool ieee802154_create_data_frame(struct ieee802154_context *ctx, struct net_lin
 
 	params.dst.pan_id = ctx->pan_id;
 	params.pan_id = ctx->pan_id;
-	if (src->addr && src->len == IEEE802154_SHORT_ADDR_LENGTH) {
+	if (src->len == IEEE802154_SHORT_ADDR_LENGTH) {
 		params.short_addr = ntohs(*(uint16_t *)(src->addr));
 		if (ctx->short_addr != params.short_addr) {
 			goto out;
diff --git a/subsys/net/l2/openthread/Kconfig b/subsys/net/l2/openthread/Kconfig
index bf022741f56..022f01b7896 100644
--- a/subsys/net/l2/openthread/Kconfig
+++ b/subsys/net/l2/openthread/Kconfig
@@ -2,106 +2,23 @@
 
 # Copyright (c) 2018 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
-config OPENTHREAD_SECURITY_INTERNAL
-	bool
-	help
-	  OpenThread setting to signal that OpenThread security settings, such
-	  as the OPENTHREAD_MBEDTLS setting will be controlled through other
-	  Kconfig dependencies and should not be user configurable.
 
 menuconfig NET_L2_OPENTHREAD
 	bool "OpenThread L2"
 	depends on NETWORKING
-	select NET_L2_PHY_IEEE802154
 	select OPENTHREAD
 
-	imply FLASH
-	imply FLASH_MAP
-	imply MPU_ALLOW_FLASH_WRITE
-
-	select SETTINGS if FLASH
-	select OPENTHREAD_SETTINGS_RAM if !FLASH
-	select CPP
-	select REBOOT
-	select ENTROPY_GENERATOR
-
+	select NET_L2_PHY_IEEE802154
 	imply NET_UDP
 	imply NET_IPV6
 	imply NET_CONFIG_NEED_IPV6
-
-if NET_L2_OPENTHREAD
-
-choice OPENTHREAD_IMPLEMENTATION
-	prompt "OpenThread origin selection"
 	help
-	  Select OpenThread to use for build. Custom OpenThread implementations
-	  can be added to the application Kconfig.
-
-config OPENTHREAD_SOURCES
-	bool "OpenThread from sources"
-	help
-	  Build Zephyr's OpenThread port from sources.
-
-endchoice
+	  Use Zephyr's implementation of the OpenThread L2.
 
-config OPENTHREAD_MANUAL_START
-	bool "Start OpenThread stack manually"
-	help
-	  If enabled, OpenThread stack will have to be configured and
-	  started manually, with respective API calls or CLI/NCP commands.
-	  Otherwise, OpenThread will configure the network parameters and try to
-	  join the Thread network automatically during initialization (using
-	  credentials stored in persistent storage, obtained during
-	  commissioning or pre-commissioned with other Kconfig options,
-	  depending on configuration used).
+if NET_L2_OPENTHREAD
 
 menu "Logging"
 
-menuconfig OPENTHREAD_DEBUG
-	bool "OpenThread stack logging support"
-	depends on NET_L2_OPENTHREAD
-	help
-	  This option enables logging support for OpenThread.
-
-choice
-	prompt "OpenThread stack log level"
-	depends on OPENTHREAD_DEBUG
-	help
-	  This option selects log level for OpenThread stack.
-
-config OPENTHREAD_LOG_LEVEL_CRIT
-	bool "Critical"
-config OPENTHREAD_LOG_LEVEL_WARN
-	bool "Warning"
-config OPENTHREAD_LOG_LEVEL_NOTE
-	bool "Notice"
-config OPENTHREAD_LOG_LEVEL_INFO
-	bool "Informational"
-config OPENTHREAD_LOG_LEVEL_DEBG
-	bool "Debug"
-endchoice
-
-config OPENTHREAD_LOG_LEVEL
-	int
-	default 1 if OPENTHREAD_LOG_LEVEL_CRIT
-	default 2 if OPENTHREAD_LOG_LEVEL_WARN
-	default 3 if OPENTHREAD_LOG_LEVEL_NOTE
-	default 4 if OPENTHREAD_LOG_LEVEL_INFO
-	default 5 if OPENTHREAD_LOG_LEVEL_DEBG
-	default 0
-	help
-	  Log level for OpenThread stack.
-
-config OPENTHREAD_PLATFORM_LOG_LEVEL
-	int
-	default 1 if OPENTHREAD_LOG_LEVEL_CRIT
-	default 2 if OPENTHREAD_LOG_LEVEL_WARN
-	default 3 if OPENTHREAD_LOG_LEVEL_NOTE || OPENTHREAD_LOG_LEVEL_INFO
-	default 4 if OPENTHREAD_LOG_LEVEL_DEBG
-	default 0
-	help
-	  Log level for OpenThread Zephyr platform.
-
 menuconfig OPENTHREAD_L2_DEBUG
 	bool "OpenThread L2 log support"
 	help
@@ -129,225 +46,4 @@ source "subsys/net/Kconfig.template.log_config.net"
 
 endmenu # "Logging"
 
-menu "Zephyr optimizations"
-
-config OPENTHREAD_THREAD_PREEMPTIVE
-	bool "Set Openthread thread to be preemptive"
-
-config OPENTHREAD_THREAD_PRIORITY
-	int "OpenThread thread priority"
-	default 0 if OPENTHREAD_THREAD_PREEMPTIVE
-	default 8
-
-config OPENTHREAD_THREAD_STACK_SIZE
-	int "OpenThread thread stack size"
-	default 6144 if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER
-	default 6240 if (OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER) && MPU_STACK_GUARD && FPU_SHARING && CPU_CORTEX_M
-	default 3168 if MPU_STACK_GUARD && FPU_SHARING && CPU_CORTEX_M
-	default 3072
-
-
-config OPENTHREAD_PKT_LIST_SIZE
-	int "List size for IPv6 packet buffering"
-	default 10
-
-config OPENTHREAD_RADIO_WORKQUEUE_STACK_SIZE
-	int "OpenThread radio transmit workqueue stack size"
-	default 608 if MPU_STACK_GUARD && FPU_SHARING && CPU_CORTEX_M
-	default 512
-
-endmenu # "Zephyr optimizations"
-
-config OPENTHREAD_SHELL
-	bool "OpenThread shell"
-	depends on SHELL
-
-config MBEDTLS_PROMPTLESS
-	bool
-	default y if !CUSTOM_OPENTHREAD_SECURITY
-
-choice OPENTHREAD_SECURITY
-	prompt "OpenThread security"
-	default OPENTHREAD_MBEDTLS_CHOICE
-	depends on !OPENTHREAD_SECURITY_INTERNAL
-
-config CUSTOM_OPENTHREAD_SECURITY
-	bool "Custom"
-	help
-	  Security settings will be controlled directly by the user.
-	  Enabling this setting will give access to full control of mbed TLS
-	  configuration.
-
-config OPENTHREAD_MBEDTLS_CHOICE
-	bool "mbed TLS built-in"
-	select OPENTHREAD_MBEDTLS
-	help
-	  Use the OpenThread mbed TLS configuration pre-defined security scheme.
-
-endchoice
-
-config OPENTHREAD_MBEDTLS
-	bool
-	select MBEDTLS
-	select MBEDTLS_ENABLE_HEAP
-	select MBEDTLS_CIPHER_AES_ENABLED
-	select MBEDTLS_CIPHER_CCM_ENABLED
-	select MBEDTLS_SHA256
-	select MBEDTLS_ENTROPY_C
-	select MBEDTLS_CMAC
-	select MBEDTLS_CIPHER
-	select MBEDTLS_MD
-	select MBEDTLS_TLS_VERSION_1_2 if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER
-	select MBEDTLS_DTLS if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER
-	select MBEDTLS_KEY_EXCHANGE_ECJPAKE_ENABLED if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER
-	select MBEDTLS_ECJPAKE_C if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER
-	select MBEDTLS_ECP_DP_SECP256R1_ENABLED if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER || \
-	    OPENTHREAD_SRP_CLIENT || OPENTHREAD_SRP_SERVER
-	select MBEDTLS_ECP_NIST_OPTIM if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER
-	select MBEDTLS_CTR_DRBG_ENABLED if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER
-	select MBEDTLS_HMAC_DRBG_ENABLED if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER || \
-	    OPENTHREAD_SRP_CLIENT || OPENTHREAD_SRP_SERVER
-	select MBEDTLS_KEY_EXCHANGE_ECDHE_ECDSA_ENABLED if OPENTHREAD_ECDSA
-	select MBEDTLS_ECDH_C if OPENTHREAD_ECDSA
-	select MBEDTLS_ECDSA_C if OPENTHREAD_ECDSA
-	select MBEDTLS_ECDSA_DETERMINISTIC if OPENTHREAD_ECDSA
-	select MBEDTLS_PK_WRITE_C if OPENTHREAD_ECDSA
-	select MBEDTLS_ECP_C if OPENTHREAD_COMMISSIONER || OPENTHREAD_JOINER || OPENTHREAD_ECDSA
-
-
-config OPENTHREAD_MBEDTLS_LIB_NAME
-	string "mbedtls lib name"
-	default "mbedTLS"
-	help
-	  This option allows to specify one or more mbedtls library files to be
-	  linked with OpenThread. Separate multiple values with space " ".
-
-config OPENTHREAD_COPROCESSOR
-	bool "OpenThread Co-Processor"
-	select OPENTHREAD_MANUAL_START
-	select RING_BUFFER
-	select UART_INTERRUPT_DRIVEN
-	help
-	  Enable Co-Processor in OpenThread stack.
-
-if OPENTHREAD_COPROCESSOR
-
-choice
-	prompt "OpenThread Co-Processor type"
-	help
-	  This option selects Thread network co-processor type
-
-config OPENTHREAD_COPROCESSOR_NCP
-	bool "NCP - Network Co-Processor"
-config OPENTHREAD_COPROCESSOR_RCP
-	bool "RCP - Radio Co-Processor"
-endchoice
-
-config OPENTHREAD_COPROCESSOR_UART_RING_BUFFER_SIZE
-	int "Set Co-Processor UART ring buffer size"
-	default 4096
-	help
-	  TX buffer size for the OpenThread Co-Processor UART.
-
-config OPENTHREAD_COPROCESSOR_VENDOR_HOOK_SOURCE
-	string "Path to vendor hook source file"
-	help
-	  Provides path to compile vendor hook file.
-
-endif # OPENTHREAD_COPROCESSOR
-
-config OPENTHREAD_PLATFORM_INFO
-	string "Platform information for OpenThread"
-	default "ZEPHYR"
-	help
-	  Platform information for OpenThread
-
-config OPENTHREAD_CUSTOM_PARAMETERS
-	string "Custom Parameters to pass to OpenThread build system"
-	default ""
-	help
-	  This option is intended for advanced users only.
-	  Pass additional parameters that do not have corresponding Kconfig
-	  options to the OpenThread build system. Separate multiple values with
-	  space " ", for example:
-	  "OPENTHREAD_CONFIG_JOINER_ENABLE=1 OPENTHREAD_CONFIG_JOINER_MAX_CANDIDATES=3"
-
-config OPENTHREAD_NUM_MESSAGE_BUFFERS
-	int "The number of message buffers in the buffer pool"
-	default 128
-	help
-	  "The number of message buffers in the buffer pool."
-
-config OPENTHREAD_MESSAGE_BUFFER_SIZE
-	int "The size of a message buffer in bytes"
-	default 128
-	help
-	  "The size of a message buffer in bytes"
-
-config OPENTHREAD_PLATFORM_MESSAGE_MANAGEMENT
-	bool "Use platform message management"
-	help
-	  The message pool is managed by platform defined logic.
-
-config OPENTHREAD_MAX_STATECHANGE_HANDLERS
-	int "The maximum number of state-changed callback handlers"
-	default 2
-	help
-	  The maximum number of state-changed callback handlers
-	  set using otSetStateChangedCallback.
-
-config OPENTHREAD_TMF_ADDRESS_CACHE_ENTRIES
-	int "The number of EID-to-RLOC cache entries"
-	default 20
-	help
-	  The number of EID-to-RLOC cache entries.
-
-config OPENTHREAD_TMF_ADDRESS_CACHE_MAX_SNOOP_ENTRIES
-	int "The maximum number of EID-to-RLOC cache entries"
-	default 2
-	help
-	  The maximum number of EID-to-RLOC cache entries that can be used for
-	  "snoop optimization" where an entry is created by inspecting a received
-	  message.
-
-config OPENTHREAD_LOG_PREPEND_LEVEL_ENABLE
-	bool "Prepending the log level to all OpenThread log messages"
-	help
-	  When enabled the OpenThread logs will be prepended with the appropriate
-	  log level prefix i.e. [CRIT], [WARN], [NOTE], [INFO], [DEBG].
-
-config OPENTHREAD_MAC_SOFTWARE_ACK_TIMEOUT_ENABLE
-	bool "Software ACK timeout logic"
-	default y
-	help
-	  Set y if the radio supports AckTime event
-
-config OPENTHREAD_MAC_SOFTWARE_RETRANSMIT_ENABLE
-	bool "Software retransmission logic"
-	default y
-	help
-	  Set y if the radio supports tx retry logic with collision avoidance (CSMA)
-
-config OPENTHREAD_MAC_SOFTWARE_CSMA_BACKOFF_ENABLE
-	bool "Software CSMA backoff logic"
-	default y
-	help
-	  Set y to enable software CSMA backoff. The option can be disabled if
-	  the radio has hardware support for this feature (IEEE802154_HW_CSMA).
-
-config OPENTHREAD_CRYPTO_PSA
-	bool "ARM PSA crypto API"
-	depends on MBEDTLS_PSA_CRYPTO_CLIENT
-	select OPENTHREAD_PLATFORM_KEY_REF if !OPENTHREAD_COPROCESSOR_RCP
-	imply OPENTHREAD_PLATFORM_KEYS_EXPORTABLE_ENABLE
-	help
-	  Enable crypto backend library implementation based on ARM PSA crypto
-	  API instead of the default, using mbedTLS.
-
-config OPENTHREAD_PLATFORM_KEYS_EXPORTABLE_ENABLE
-	bool "Make MAC keys exportable"
-	depends on OPENTHREAD_PLATFORM_KEY_REF
-	help
-	  Enable the creation of exportable MAC keys in the OpenThread Key Manager.
-
 endif # NET_L2_OPENTHREAD
diff --git a/subsys/net/l2/openthread/openthread.c b/subsys/net/l2/openthread/openthread.c
index f3553e13874..c82dfdea2d2 100644
--- a/subsys/net/l2/openthread/openthread.c
+++ b/subsys/net/l2/openthread/openthread.c
@@ -187,12 +187,20 @@ static void ot_state_changed_handler(uint32_t flags, void *context)
 {
 	struct openthread_state_changed_cb *entry, *next;
 	struct openthread_context *ot_context = context;
+	bool is_up = otIp6IsEnabled(ot_context->instance);
 
-	NET_INFO("State changed! Flags: 0x%08" PRIx32 " Current role: %s",
+	NET_INFO("State changed! Flags: 0x%08" PRIx32 " Current role: %s Ip6: %s",
 		flags,
-		otThreadDeviceRoleToString(otThreadGetDeviceRole(ot_context->instance))
-		);
+		otThreadDeviceRoleToString(otThreadGetDeviceRole(ot_context->instance)),
+		(is_up ? "up" : "down"));
 
+#if defined(CONFIG_OPENTHREAD_INTERFACE_EARLY_UP)
+	if (is_up) {
+		net_if_dormant_off(ot_context->iface);
+	} else {
+		net_if_dormant_on(ot_context->iface);
+	}
+#else
 	if (flags & OT_CHANGED_THREAD_ROLE) {
 		switch (otThreadGetDeviceRole(ot_context->instance)) {
 		case OT_DEVICE_ROLE_CHILD:
@@ -208,6 +216,7 @@ static void ot_state_changed_handler(uint32_t flags, void *context)
 			break;
 		}
 	}
+#endif
 
 	if (flags & OT_CHANGED_IP6_ADDRESS_REMOVED) {
 		NET_DBG("Ipv6 address removed");
diff --git a/subsys/net/l2/ppp/ipv6cp.c b/subsys/net/l2/ppp/ipv6cp.c
index e18e54b393d..b1e81775f94 100644
--- a/subsys/net/l2/ppp/ipv6cp.c
+++ b/subsys/net/l2/ppp/ipv6cp.c
@@ -261,11 +261,9 @@ static void ipv6cp_up(struct ppp_fsm *fsm)
 	/* Add peer to neighbor table */
 	setup_iid_address(ctx->ipv6cp.peer_options.iid, &peer_addr);
 
-	peer_lladdr.addr = ctx->ipv6cp.peer_options.iid;
-	peer_lladdr.len = sizeof(ctx->ipv6cp.peer_options.iid);
-
-	/* TODO: What should be the type? */
-	peer_lladdr.type = NET_LINK_DUMMY;
+	(void)net_linkaddr_create(&peer_lladdr, ctx->ipv6cp.peer_options.iid,
+				  sizeof(ctx->ipv6cp.peer_options.iid),
+				  NET_LINK_DUMMY);
 
 	nbr = net_ipv6_nbr_add(ctx->iface, &peer_addr, &peer_lladdr,
 			       false, NET_IPV6_NBR_STATE_STATIC);
@@ -317,11 +315,9 @@ static void ipv6cp_down(struct ppp_fsm *fsm)
 	/* Remove peer from neighbor table */
 	setup_iid_address(ctx->ipv6cp.peer_options.iid, &peer_addr);
 
-	peer_lladdr.addr = ctx->ipv6cp.peer_options.iid;
-	peer_lladdr.len = sizeof(ctx->ipv6cp.peer_options.iid);
-
-	/* TODO: What should be the type? */
-	peer_lladdr.type = NET_LINK_DUMMY;
+	(void)net_linkaddr_create(&peer_lladdr, ctx->ipv6cp.peer_options.iid,
+				  sizeof(ctx->ipv6cp.peer_options.iid),
+				  NET_LINK_DUMMY);
 
 	ret = net_ipv6_nbr_rm(ctx->iface, &peer_addr);
 	if (!ret) {
diff --git a/subsys/net/l2/ppp/ppp_l2.c b/subsys/net/l2/ppp/ppp_l2.c
index bfe28738f79..b9edd2629ce 100644
--- a/subsys/net/l2/ppp/ppp_l2.c
+++ b/subsys/net/l2/ppp/ppp_l2.c
@@ -8,6 +8,7 @@
 LOG_MODULE_REGISTER(net_l2_ppp, CONFIG_NET_L2_PPP_LOG_LEVEL);
 
 #include <stdlib.h>
+#include <zephyr/net/ethernet.h>
 #include <zephyr/net/net_core.h>
 #include <zephyr/net/net_l2.h>
 #include <zephyr/net/net_if.h>
@@ -180,6 +181,24 @@ static int ppp_send(struct net_if *iface, struct net_pkt *pkt)
 		return -ENETDOWN;
 	}
 
+	/* PPP drivers only support IP packet types, therefore in order to be
+	 * able to use AF_PACKET family sockets with PPP, we need to translate
+	 * L2 proto type to packet family.
+	 */
+	if (IS_ENABLED(CONFIG_NET_SOCKETS_PACKET) &&
+	    net_pkt_family(pkt) == AF_PACKET) {
+		switch (net_pkt_ll_proto_type(pkt)) {
+		case ETH_P_IP:
+			net_pkt_set_family(pkt, AF_INET);
+			break;
+		case ETH_P_IPV6:
+			net_pkt_set_family(pkt, AF_INET6);
+			break;
+		default:
+			return -EPROTONOSUPPORT;
+		}
+	}
+
 	ret = net_l2_send(api->send, net_if_get_device(iface), iface, pkt);
 	if (!ret) {
 		ret = net_pkt_get_len(pkt);
diff --git a/subsys/net/l2/virtual/virtual.c b/subsys/net/l2/virtual/virtual.c
index ef58a99a5fa..83c5ec88761 100644
--- a/subsys/net/l2/virtual/virtual.c
+++ b/subsys/net/l2/virtual/virtual.c
@@ -25,6 +25,7 @@ static enum net_verdict virtual_recv(struct net_if *iface,
 {
 	struct virtual_interface_context *ctx, *tmp;
 	const struct virtual_interface_api *api;
+	struct net_if *filtered_iface = NULL;
 	enum net_verdict verdict;
 	sys_slist_t *interfaces;
 
@@ -46,6 +47,28 @@ static enum net_verdict virtual_recv(struct net_if *iface,
 			continue;
 		}
 
+		if (IS_ENABLED(CONFIG_NET_PKT_FILTER)) {
+			struct net_if *tmp_iface;
+
+			tmp_iface = net_pkt_iface(pkt);
+			net_pkt_set_iface(pkt, ctx->virtual_iface);
+
+			if (!net_pkt_filter_recv_ok(pkt)) {
+				/* We cannot update the statistics here because
+				 * the interface might not be the correct one for
+				 * the packet. We would know that only after the
+				 * call to api->recv() which is too late. So mark
+				 * the interface as filtered and continue and
+				 * update the filter statistics out of the loop.
+				 */
+				net_pkt_set_iface(pkt, tmp_iface);
+				filtered_iface = tmp_iface;
+				continue;
+			}
+
+			net_pkt_set_iface(pkt, tmp_iface);
+		}
+
 		verdict = api->recv(ctx->virtual_iface, pkt);
 		if (verdict == NET_CONTINUE) {
 			continue;
@@ -69,8 +92,53 @@ static enum net_verdict virtual_recv(struct net_if *iface,
 		return verdict;
 	}
 
+	if (IS_ENABLED(CONFIG_NET_PKT_FILTER) && filtered_iface != NULL) {
+		/* We need to update the statistics for the filtered iface here.
+		 */
+		net_stats_update_filter_rx_drop(filtered_iface);
+		goto silent_drop;
+	}
+
+	/* If there are no virtual interfaces attached, then pass the packet
+	 * to the actual virtual network interface.
+	 */
+	api = net_if_get_device(iface)->api;
+	if (!api || api->recv == NULL) {
+		goto drop;
+	}
+
+	if (!net_if_is_up(iface)) {
+		NET_DBG("Interface %d is down.", net_if_get_by_iface(iface));
+		goto silent_drop;
+	}
+
+	if (!net_pkt_filter_recv_ok(pkt)) {
+		net_stats_update_filter_rx_drop(iface);
+		goto silent_drop;
+	}
+
+	verdict = api->recv(iface, pkt);
+
+	if (IS_ENABLED(CONFIG_NET_STATISTICS)) {
+		size_t pkt_len;
+
+		pkt_len = net_pkt_get_len(pkt);
+
+		NET_DBG("Received pkt %p len %zu", pkt, pkt_len);
+
+		net_stats_update_bytes_recv(iface, pkt_len);
+	}
+
+	if (verdict == NET_DROP) {
+		net_stats_update_processing_error(iface);
+	}
+
+	return verdict;
+
+drop:
 	NET_DBG("No handler, dropping pkt %p len %zu", pkt, net_pkt_get_len(pkt));
 
+silent_drop:
 	return NET_DROP;
 }
 
@@ -186,7 +254,8 @@ static void random_linkaddr(uint8_t *linkaddr, size_t len)
 {
 	sys_rand_get(linkaddr, len);
 
-	linkaddr[0] |= 0x02; /* force LAA bit */
+	linkaddr[0] |= 0x02;  /* force LAA bit */
+	linkaddr[0] &= ~0x01; /* clear multicast bit */
 }
 
 int net_virtual_interface_attach(struct net_if *virtual_iface,
@@ -362,8 +431,8 @@ void net_virtual_set_name(struct net_if *iface, const char *name)
 
 	ctx = net_if_l2_data(iface);
 
-	strncpy(ctx->name, name, CONFIG_NET_L2_VIRTUAL_MAX_NAME_LEN);
-	ctx->name[CONFIG_NET_L2_VIRTUAL_MAX_NAME_LEN - 1] = '\0';
+	strncpy(ctx->name, name, ARRAY_SIZE(ctx->name) - 1);
+	ctx->name[ARRAY_SIZE(ctx->name) - 1] = '\0';
 }
 
 enum net_l2_flags net_virtual_set_flags(struct net_if *iface,
diff --git a/subsys/net/l2/virtual/virtual_mgmt.c b/subsys/net/l2/virtual/virtual_mgmt.c
index b0a8d62a04d..1210fc59083 100644
--- a/subsys/net/l2/virtual/virtual_mgmt.c
+++ b/subsys/net/l2/virtual/virtual_mgmt.c
@@ -61,6 +61,15 @@ static int virtual_interface_set_config(uint32_t mgmt_request,
 		memcpy(&config.link_types, &params->link_types,
 		       sizeof(config.link_types));
 		type = VIRTUAL_INTERFACE_CONFIG_TYPE_LINK_TYPE;
+
+	} else if (mgmt_request == NET_REQUEST_VIRTUAL_INTERFACE_SET_PRIVATE_KEY) {
+		if (net_if_is_up(iface)) {
+			return -EACCES;
+		}
+
+		config.private_key.len = params->private_key.len;
+		config.private_key.data = params->private_key.data;
+		type = VIRTUAL_INTERFACE_CONFIG_TYPE_PRIVATE_KEY;
 	} else {
 		return -EINVAL;
 	}
@@ -77,6 +86,9 @@ NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_SET_MTU,
 NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_SET_LINK_TYPE,
 				  virtual_interface_set_config);
 
+NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_SET_PRIVATE_KEY,
+				  virtual_interface_set_config);
+
 static int virtual_interface_get_config(uint32_t mgmt_request,
 					struct net_if *iface,
 					void *data, size_t len)
@@ -133,6 +145,19 @@ static int virtual_interface_get_config(uint32_t mgmt_request,
 
 		memcpy(&params->link_types, &config.link_types,
 		       sizeof(params->link_types));
+
+	} else if (mgmt_request == NET_REQUEST_VIRTUAL_INTERFACE_GET_PUBLIC_KEY) {
+		type = VIRTUAL_INTERFACE_CONFIG_TYPE_PUBLIC_KEY;
+
+		ret = api->get_config(iface, type, &config);
+		if (ret) {
+			return ret;
+		}
+
+		params->public_key.len = config.public_key.len;
+		memcpy(&params->public_key.data, &config.public_key.data,
+		       MIN(sizeof(params->public_key.data),
+			   params->public_key.len));
 	} else {
 		return -EINVAL;
 	}
@@ -148,3 +173,6 @@ NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_GET_MTU,
 
 NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_GET_LINK_TYPE,
 				  virtual_interface_get_config);
+
+NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_VIRTUAL_INTERFACE_GET_PUBLIC_KEY,
+				  virtual_interface_get_config);
diff --git a/subsys/net/l2/wifi/CMakeLists.txt b/subsys/net/l2/wifi/CMakeLists.txt
index 6cf0183e141..e1e9606bfd2 100644
--- a/subsys/net/l2/wifi/CMakeLists.txt
+++ b/subsys/net/l2/wifi/CMakeLists.txt
@@ -27,6 +27,9 @@ if(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE AND CONFIG_NET_L2_WIFI_SHELL)
   # Wi-Fi Enterprise test certificates handling
   set(gen_inc_dir ${ZEPHYR_BINARY_DIR}/misc/generated)
   set(gen_dir ${gen_inc_dir}/wifi_enterprise_test_certs)
+  if(NOT DEFINED WIFI_TEST_CERTS_DIR)
+    set(WIFI_TEST_CERTS_DIR ${ZEPHYR_BASE}/samples/net/wifi/test_certs/rsa3k)
+  endif()
   # Create output directory for test certs
   file(MAKE_DIRECTORY ${gen_dir})
 
@@ -34,14 +37,14 @@ if(CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE AND CONFIG_NET_L2_WIFI_SHELL)
   zephyr_include_directories(${gen_inc_dir})
 
   foreach(cert_file IN ITEMS
-      ${ZEPHYR_BASE}/samples/net/wifi/test_certs/client.pem
-      ${ZEPHYR_BASE}/samples/net/wifi/test_certs/client-key.pem
-      ${ZEPHYR_BASE}/samples/net/wifi/test_certs/ca.pem
-      ${ZEPHYR_BASE}/samples/net/wifi/test_certs/client2.pem
-      ${ZEPHYR_BASE}/samples/net/wifi/test_certs/client-key2.pem
-      ${ZEPHYR_BASE}/samples/net/wifi/test_certs/ca2.pem
-      ${ZEPHYR_BASE}/samples/net/wifi/test_certs/server.pem
-      ${ZEPHYR_BASE}/samples/net/wifi/test_certs/server-key.pem
+      ${WIFI_TEST_CERTS_DIR}/client.pem
+      ${WIFI_TEST_CERTS_DIR}/client-key.pem
+      ${WIFI_TEST_CERTS_DIR}/ca.pem
+      ${WIFI_TEST_CERTS_DIR}/client2.pem
+      ${WIFI_TEST_CERTS_DIR}/client-key2.pem
+      ${WIFI_TEST_CERTS_DIR}/ca2.pem
+      ${WIFI_TEST_CERTS_DIR}/server.pem
+      ${WIFI_TEST_CERTS_DIR}/server-key.pem
       )
     if(EXISTS ${cert_file})
       get_filename_component(cert_name ${cert_file} NAME)
diff --git a/subsys/net/l2/wifi/wifi_mgmt.c b/subsys/net/l2/wifi/wifi_mgmt.c
index 251068d1614..95ff6b45f0c 100644
--- a/subsys/net/l2/wifi/wifi_mgmt.c
+++ b/subsys/net/l2/wifi/wifi_mgmt.c
@@ -91,12 +91,28 @@ const char *wifi_security_txt(enum wifi_security_type security)
 		return "FT-EAP";
 	case WIFI_SECURITY_TYPE_FT_EAP_SHA384:
 		return "FT-EAP-SHA384";
+	case WIFI_SECURITY_TYPE_SAE_EXT_KEY:
+		return "WPA3-SAE-EXT-KEY";
 	case WIFI_SECURITY_TYPE_UNKNOWN:
 	default:
 		return "UNKNOWN";
 	}
 }
 
+const char *wifi_wpa3_enterprise_txt(enum wifi_wpa3_enterprise_type wpa3_ent)
+{
+	switch (wpa3_ent) {
+	case WIFI_WPA3_ENTERPRISE_SUITEB:
+		return "WPA3-SuiteB";
+	case WIFI_WPA3_ENTERPRISE_SUITEB_192:
+		return "WPA3-SuiteB-192";
+	case WIFI_WPA3_ENTERPRISE_ONLY:
+		return "WPA3-Enterprise-Only";
+	default:
+		return "";
+	}
+}
+
 const char *wifi_mfp_txt(enum wifi_mfp_options mfp)
 {
 	switch (mfp) {
@@ -317,11 +333,34 @@ const char *wifi_ps_exit_strategy_txt(enum wifi_ps_exit_strategy ps_exit_strateg
 	}
 }
 
+const char *wifi_conn_status_txt(enum wifi_conn_status status)
+{
+	switch (status) {
+	case WIFI_STATUS_CONN_SUCCESS:
+		return "Connection successful";
+	case WIFI_STATUS_CONN_FAIL:
+		return "Connection failed";
+	case WIFI_STATUS_CONN_WRONG_PASSWORD:
+		return "Wrong password";
+	case WIFI_STATUS_CONN_TIMEOUT:
+		return "Connection timeout";
+	case WIFI_STATUS_CONN_AP_NOT_FOUND:
+		return "AP not found";
+	default:
+		return "UNKNOWN";
+	}
+}
+
 static const struct wifi_mgmt_ops *const get_wifi_api(struct net_if *iface)
 {
 	const struct device *dev = net_if_get_device(iface);
-	struct net_wifi_mgmt_offload *off_api =
-			(struct net_wifi_mgmt_offload *) dev->api;
+	struct net_wifi_mgmt_offload *off_api;
+
+	if (dev == NULL) {
+		return NULL;
+	}
+
+	off_api = (struct net_wifi_mgmt_offload *) dev->api;
 #ifdef CONFIG_WIFI_NM
 	struct wifi_nm_instance *nm = wifi_nm_get_instance_iface(iface);
 
@@ -345,6 +384,10 @@ static int wifi_connect(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	LOG_HEXDUMP_DBG(params->ssid, params->ssid_length, "ssid");
 	LOG_HEXDUMP_DBG(params->psk, params->psk_length, "psk");
 	if (params->sae_password) {
@@ -352,26 +395,52 @@ static int wifi_connect(uint32_t mgmt_request, struct net_if *iface,
 	}
 	NET_DBG("ch %u sec %u", params->channel, params->security);
 
-	if ((params->security > WIFI_SECURITY_TYPE_MAX) ||
-	    (params->ssid_length > WIFI_SSID_MAX_LEN) ||
-	    (params->ssid_length == 0U) ||
-	    ((params->security == WIFI_SECURITY_TYPE_PSK ||
-		  params->security == WIFI_SECURITY_TYPE_WPA_PSK ||
-		  params->security == WIFI_SECURITY_TYPE_PSK_SHA256 ||
-		  params->security == WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL) &&
-	     ((params->psk_length < 8) || (params->psk_length > 64) ||
-	      (params->psk_length == 0U) || !params->psk)) ||
-	    ((params->security == WIFI_SECURITY_TYPE_SAE_HNP ||
-		  params->security == WIFI_SECURITY_TYPE_SAE_H2E ||
-		  params->security == WIFI_SECURITY_TYPE_SAE_AUTO) &&
-	      ((params->psk_length == 0U) || !params->psk) &&
-		  ((params->sae_password_length == 0U) || !params->sae_password)) ||
-	    ((params->channel != WIFI_CHANNEL_ANY) &&
-	     (params->channel > WIFI_CHANNEL_MAX)) ||
-	    !params->ssid) {
+	if (params->channel > WIFI_CHANNEL_MAX && params->channel != WIFI_CHANNEL_ANY) {
 		return -EINVAL;
 	}
 
+	if (!params->ssid) {
+		return -EINVAL;
+	}
+
+	if (params->ssid_length <= 0 || params->ssid_length > WIFI_SSID_MAX_LEN) {
+		return -EINVAL;
+	}
+
+	if (params->psk_length && (params->psk_length < 8 || params->psk_length > 64)) {
+		return -EINVAL;
+	}
+
+	if (params->sae_password_length &&
+	    (params->sae_password_length < 8 || params->sae_password_length > 64)) {
+		return -EINVAL;
+	}
+
+	if (params->security > WIFI_SECURITY_TYPE_MAX) {
+		return -EINVAL;
+	}
+
+	switch (params->security) {
+	case WIFI_SECURITY_TYPE_PSK:
+	case WIFI_SECURITY_TYPE_WPA_PSK:
+	case WIFI_SECURITY_TYPE_PSK_SHA256:
+	case WIFI_SECURITY_TYPE_WPA_AUTO_PERSONAL:
+		if (!params->psk_length || !params->psk) {
+			return -EINVAL;
+		}
+		break;
+	case WIFI_SECURITY_TYPE_SAE_HNP:
+	case WIFI_SECURITY_TYPE_SAE_H2E:
+	case WIFI_SECURITY_TYPE_SAE_AUTO:
+		if ((!params->psk_length || !params->psk) &&
+		    (!params->sae_password_length || !params->sae_password)) {
+			return -EINVAL;
+		}
+		break;
+	default:
+		break;
+	}
+
 #ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_ROAMING
 	memset(&roaming_params, 0x0, sizeof(roaming_params));
 	roaming_params.is_11r_used = params->ft_used;
@@ -417,6 +486,10 @@ static int wifi_scan(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 #ifdef CONFIG_WIFI_MGMT_FORCED_PASSIVE_SCAN
 	struct wifi_scan_params default_params = {0};
 
@@ -441,6 +514,10 @@ static int wifi_disconnect(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	return wifi_mgmt_api->disconnect(dev);
 }
 
@@ -478,6 +555,11 @@ static int wifi_start_roaming(uint32_t mgmt_request, struct net_if *iface,
 	if (wifi_mgmt_api == NULL) {
 		return -ENOTSUP;
 	}
+
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	if (roaming_params.is_11r_used) {
 		if (wifi_mgmt_api->start_11r_roaming == NULL) {
 			return -ENOTSUP;
@@ -514,6 +596,10 @@ static int wifi_neighbor_rep_complete(uint32_t mgmt_request, struct net_if *ifac
 	const struct wifi_mgmt_ops *const wifi_mgmt_api = get_wifi_api(iface);
 	struct wifi_scan_params params = {0};
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	for (int i = 0; i < roaming_params.neighbor_rep.neighbor_cnt; i++) {
 		params.band_chan[i].channel = roaming_params.neighbor_rep.neighbor_ap[i].channel;
 		if (params.band_chan[i].channel > 14) {
@@ -610,6 +696,10 @@ static int wifi_ap_enable(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	return wifi_mgmt_api->ap_enable(dev, params);
 }
 
@@ -625,6 +715,10 @@ static int wifi_ap_disable(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	return wifi_mgmt_api->ap_disable(dev);
 }
 
@@ -645,6 +739,10 @@ static int wifi_ap_sta_disconnect(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	if (!data || len != sizeof(uint8_t) * WIFI_MAC_ADDR_LEN) {
 		return -EINVAL;
 	}
@@ -670,6 +768,10 @@ static int wifi_ap_config_params(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	if (!data || len != sizeof(*params)) {
 		return -EINVAL;
 	}
@@ -699,6 +801,10 @@ static int wifi_ap_set_rts_threshold(uint32_t mgmt_request, struct net_if *iface
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	if (data == NULL || len != sizeof(*rts_threshold)) {
 		return -EINVAL;
 	}
@@ -781,6 +887,10 @@ static int wifi_11k_cfg(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 #ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_ROAMING
 	if (params->oper == WIFI_MGMT_SET) {
 		roaming_params.is_11k_enabled = params->enable_11k;
@@ -803,6 +913,10 @@ static int wifi_11k_neighbor_request(uint32_t mgmt_request, struct net_if *iface
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	return wifi_mgmt_api->send_11k_neighbor_request(dev, params);
 }
 
@@ -821,6 +935,10 @@ static int wifi_set_power_save(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	switch (ps_params->type) {
 	case WIFI_PS_PARAM_LISTEN_INTERVAL:
 	case WIFI_PS_PARAM_MODE:
@@ -870,6 +988,10 @@ static int wifi_get_power_save_config(uint32_t mgmt_request, struct net_if *ifac
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	if (!data || len != sizeof(*ps_config)) {
 		return -EINVAL;
 	}
@@ -893,6 +1015,10 @@ static int wifi_set_twt(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	if (twt_params->operation == WIFI_TWT_TEARDOWN) {
 		return wifi_mgmt_api->set_twt(dev, twt_params);
 	}
@@ -956,6 +1082,10 @@ static int wifi_set_btwt(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	if (net_mgmt(NET_REQUEST_WIFI_IFACE_STATUS, iface, &info,
 			sizeof(struct wifi_iface_status))) {
 		twt_params->fail_reason =
@@ -989,6 +1119,10 @@ static int wifi_reg_domain(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	if (!data || len != sizeof(*reg_domain)) {
 		return -EINVAL;
 	}
@@ -1021,6 +1155,10 @@ static int wifi_mode(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	return wifi_mgmt_api->mode(dev, mode_info);
 }
 
@@ -1041,6 +1179,10 @@ static int wifi_packet_filter(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	return wifi_mgmt_api->filter(dev, filter_info);
 }
 
@@ -1061,6 +1203,10 @@ static int wifi_channel(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	return wifi_mgmt_api->channel(dev, channel_info);
 }
 
@@ -1082,7 +1228,6 @@ static int wifi_get_version(uint32_t mgmt_request, struct net_if *iface,
 
 NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_WIFI_VERSION, wifi_get_version);
 
-#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM
 static int wifi_btm_query(uint32_t mgmt_request, struct net_if *iface, void *data, size_t len)
 {
 	const struct device *dev = net_if_get_device(iface);
@@ -1093,6 +1238,10 @@ static int wifi_btm_query(uint32_t mgmt_request, struct net_if *iface, void *dat
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	if (query_reason >= WIFI_BTM_QUERY_REASON_UNSPECIFIED &&
 	    query_reason <= WIFI_BTM_QUERY_REASON_LEAVING_ESS) {
 		return wifi_mgmt_api->btm_query(dev, query_reason);
@@ -1102,7 +1251,6 @@ static int wifi_btm_query(uint32_t mgmt_request, struct net_if *iface, void *dat
 }
 
 NET_MGMT_REGISTER_REQUEST_HANDLER(NET_REQUEST_WIFI_BTM_QUERY, wifi_btm_query);
-#endif
 
 static int wifi_get_connection_params(uint32_t mgmt_request, struct net_if *iface,
 			void *data, size_t len)
@@ -1115,6 +1263,10 @@ static int wifi_get_connection_params(uint32_t mgmt_request, struct net_if *ifac
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	return wifi_mgmt_api->get_conn_params(dev, conn_params);
 }
 
@@ -1130,6 +1282,10 @@ static int wifi_wps_config(uint32_t mgmt_request, struct net_if *iface, void *da
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	return wifi_mgmt_api->wps_config(dev, params);
 }
 
@@ -1146,6 +1302,10 @@ static int wifi_set_rts_threshold(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	if (!data || len != sizeof(*rts_threshold)) {
 		return -EINVAL;
 	}
@@ -1167,6 +1327,10 @@ static int wifi_dpp(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	return wifi_mgmt_api->dpp_dispatch(dev, params);
 }
 
@@ -1184,6 +1348,10 @@ static int wifi_pmksa_flush(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	return wifi_mgmt_api->pmksa_flush(dev);
 }
 
@@ -1200,6 +1368,10 @@ static int wifi_get_rts_threshold(uint32_t mgmt_request, struct net_if *iface,
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	if (!data || len != sizeof(*rts_threshold)) {
 		return -EINVAL;
 	}
@@ -1221,6 +1393,10 @@ static int wifi_set_enterprise_creds(uint32_t mgmt_request, struct net_if *iface
 		return -ENOTSUP;
 	}
 
+	if (!net_if_is_admin_up(iface)) {
+		return -ENETDOWN;
+	}
+
 	return wifi_mgmt_api->enterprise_creds(dev, params);
 }
 
diff --git a/subsys/net/l2/wifi/wifi_shell.c b/subsys/net/l2/wifi/wifi_shell.c
index 83f4e2abcde..7713988594e 100644
--- a/subsys/net/l2/wifi/wifi_shell.c
+++ b/subsys/net/l2/wifi/wifi_shell.c
@@ -94,21 +94,24 @@ static const char server_key_test[] = {
 
 #define WIFI_SHELL_MODULE "wifi"
 
-#define WIFI_SHELL_MGMT_EVENTS_COMMON (NET_EVENT_WIFI_SCAN_DONE   |\
+#define WIFI_SHELL_MGMT_EVENTS (            \
 				NET_EVENT_WIFI_CONNECT_RESULT     |\
 				NET_EVENT_WIFI_DISCONNECT_RESULT  |\
 				NET_EVENT_WIFI_TWT                |\
-				NET_EVENT_WIFI_RAW_SCAN_RESULT    |\
 				NET_EVENT_WIFI_AP_ENABLE_RESULT   |\
 				NET_EVENT_WIFI_AP_DISABLE_RESULT  |\
 				NET_EVENT_WIFI_AP_STA_CONNECTED   |\
 				NET_EVENT_WIFI_AP_STA_DISCONNECTED)
 
 #ifdef CONFIG_WIFI_MGMT_RAW_SCAN_RESULTS_ONLY
-#define WIFI_SHELL_MGMT_EVENTS (WIFI_SHELL_MGMT_EVENTS_COMMON)
+#define WIFI_SHELL_SCAN_EVENTS (                   \
+				NET_EVENT_WIFI_SCAN_DONE          |\
+				NET_EVENT_WIFI_RAW_SCAN_RESULT)
 #else
-#define WIFI_SHELL_MGMT_EVENTS (WIFI_SHELL_MGMT_EVENTS_COMMON |\
-				NET_EVENT_WIFI_SCAN_RESULT)
+#define WIFI_SHELL_SCAN_EVENTS (                   \
+				NET_EVENT_WIFI_SCAN_RESULT        |\
+				NET_EVENT_WIFI_SCAN_DONE          |\
+				NET_EVENT_WIFI_RAW_SCAN_RESULT)
 #endif /* CONFIG_WIFI_MGMT_RAW_SCAN_RESULTS_ONLY */
 
 #define MAX_BANDS_STR_LEN 64
@@ -134,6 +137,7 @@ static struct {
 } context;
 
 static struct net_mgmt_event_callback wifi_shell_mgmt_cb;
+static struct net_mgmt_event_callback wifi_shell_scan_cb;
 static struct wifi_reg_chan_info chan_info[MAX_REG_CHAN_NUM];
 
 static K_MUTEX_DEFINE(wifi_ap_sta_list_lock);
@@ -405,18 +409,21 @@ static void handle_wifi_scan_result(struct net_mgmt_event_callback *cb)
 	context.scan_result++;
 
 	if (context.scan_result == 1U) {
-		PR("\n%-4s | %-32s %-5s | %-13s | %-4s | %-15s | %-17s | %-8s\n",
+		PR("\n%-4s | %-32s %-5s | %-13s | %-4s | %-20s | %-17s | %-8s\n",
 		   "Num", "SSID", "(len)", "Chan (Band)", "RSSI", "Security", "BSSID", "MFP");
 	}
 
 	strncpy(ssid_print, entry->ssid, sizeof(ssid_print) - 1);
 	ssid_print[sizeof(ssid_print) - 1] = '\0';
 
-	PR("%-4d | %-32s %-5u | %-4u (%-6s) | %-4d | %-15s | %-17s | %-8s\n",
+	PR("%-4d | %-32s %-5u | %-4u (%-6s) | %-4d | %-20s | %-17s | %-8s\n",
 	   context.scan_result, ssid_print, entry->ssid_length, entry->channel,
 	   wifi_band_txt(entry->band),
 	   entry->rssi,
-	   wifi_security_txt(entry->security),
+	   ((entry->wpa3_ent_type) ?
+		wifi_wpa3_enterprise_txt(entry->wpa3_ent_type)
+		 : (entry->security == WIFI_SECURITY_TYPE_EAP ? "WPA2 Enterprise"
+		 : wifi_security_txt(entry->security))),
 	   ((entry->mac_length) ?
 		   net_sprint_ll_addr_buf(entry->mac, WIFI_MAC_ADDR_LEN,
 					  mac_string_buf,
@@ -510,6 +517,8 @@ static void handle_wifi_scan_done(struct net_mgmt_event_callback *cb)
 		PR("Scan request done\n");
 	}
 
+	net_mgmt_del_event_callback(&wifi_shell_scan_cb);
+
 	context.scan_result = 0U;
 }
 
@@ -518,9 +527,20 @@ static void handle_wifi_connect_result(struct net_mgmt_event_callback *cb)
 	const struct wifi_status *status =
 		(const struct wifi_status *) cb->info;
 	const struct shell *sh = context.sh;
+	int st = status->status;
+
+	if (st) {
+		if (st < 0) {
+			/* Errno values are negative, try to map to
+			 * wifi status values.
+			 */
+			if (st == -ETIMEDOUT) {
+				st = WIFI_STATUS_CONN_TIMEOUT;
+			}
+		}
 
-	if (status->status) {
-		PR_WARNING("Connection request failed (%d)\n", status->status);
+		PR_WARNING("Connection request failed (%s/%d)\n",
+			   wifi_conn_status_txt(st), st);
 	} else {
 		PR("Connected\n");
 	}
@@ -729,12 +749,6 @@ static void wifi_mgmt_event_handler(struct net_mgmt_event_callback *cb,
 				    uint32_t mgmt_event, struct net_if *iface)
 {
 	switch (mgmt_event) {
-	case NET_EVENT_WIFI_SCAN_RESULT:
-		handle_wifi_scan_result(cb);
-		break;
-	case NET_EVENT_WIFI_SCAN_DONE:
-		handle_wifi_scan_done(cb);
-		break;
 	case NET_EVENT_WIFI_CONNECT_RESULT:
 		handle_wifi_connect_result(cb);
 		break;
@@ -744,11 +758,6 @@ static void wifi_mgmt_event_handler(struct net_mgmt_event_callback *cb,
 	case NET_EVENT_WIFI_TWT:
 		handle_wifi_twt_event(cb);
 		break;
-#ifdef CONFIG_WIFI_MGMT_RAW_SCAN_RESULTS
-	case NET_EVENT_WIFI_RAW_SCAN_RESULT:
-		handle_wifi_raw_scan_result(cb);
-		break;
-#endif /* CONFIG_WIFI_MGMT_RAW_SCAN_RESULTS */
 	case NET_EVENT_WIFI_AP_ENABLE_RESULT:
 		handle_wifi_ap_enable_result(cb);
 		break;
@@ -774,6 +783,26 @@ static void wifi_mgmt_event_handler(struct net_mgmt_event_callback *cb,
 	}
 }
 
+static void wifi_mgmt_scan_event_handler(struct net_mgmt_event_callback *cb,
+				    uint32_t mgmt_event, struct net_if *iface)
+{
+	switch (mgmt_event) {
+	case NET_EVENT_WIFI_SCAN_RESULT:
+		handle_wifi_scan_result(cb);
+		break;
+	case NET_EVENT_WIFI_SCAN_DONE:
+		handle_wifi_scan_done(cb);
+		break;
+#ifdef CONFIG_WIFI_MGMT_RAW_SCAN_RESULTS
+	case NET_EVENT_WIFI_RAW_SCAN_RESULT:
+		handle_wifi_raw_scan_result(cb);
+		break;
+#endif /* CONFIG_WIFI_MGMT_RAW_SCAN_RESULTS */
+	default:
+		break;
+	}
+}
+
 static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv[],
 				 struct wifi_connect_req_params *params,
 				 enum wifi_iface_mode iface_mode)
@@ -794,8 +823,9 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv
 		{"bandwidth", required_argument, 0, 'B'},
 		{"key1-pwd", required_argument, 0, 'K'},
 		{"key2-pwd", required_argument, 0, 'K'},
-		{"suiteb-type", required_argument, 0, 'S'},
+		{"wpa3-enterprise", required_argument, 0, 'S'},
 		{"TLS-cipher", required_argument, 0, 'T'},
+		{"verify-peer-cert", required_argument, 0, 'A'},
 		{"eap-version", required_argument, 0, 'V'},
 		{"eap-id1", required_argument, 0, 'I'},
 		{"eap-id2", required_argument, 0, 'I'},
@@ -841,8 +871,9 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv
 	params->eap_ver = 1;
 	params->ignore_broadcast_ssid = 0;
 	params->bandwidth = WIFI_FREQ_BANDWIDTH_20MHZ;
+	params->verify_peer_cert = false;
 
-	while ((opt = getopt_long(argc, argv, "s:p:k:e:w:b:c:m:t:a:B:K:S:T:V:I:P:i:Rh",
+	while ((opt = getopt_long(argc, argv, "s:p:k:e:w:b:c:m:t:a:B:K:S:T:A:V:I:P:i:Rh",
 				  long_options, &opt_index)) != -1) {
 		state = getopt_state_get();
 		switch (opt) {
@@ -867,12 +898,10 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv
 			break;
 		case 'c':
 			channel = strtol(state->optarg, &endptr, 10);
-#ifdef CONFIG_WIFI_NM_HOSTAPD_AP
 			if (iface_mode == WIFI_MODE_AP && channel == 0) {
 				params->channel = channel;
 				break;
 			}
-#endif
 			for (band = 0; band < ARRAY_SIZE(all_bands); band++) {
 				offset += snprintf(bands_str + offset,
 						   sizeof(bands_str) - offset,
@@ -904,7 +933,7 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv
 			break;
 		case 'b':
 			if (iface_mode == WIFI_MODE_INFRA ||
-				iface_mode == WIFI_MODE_AP) {
+			    iface_mode == WIFI_MODE_AP) {
 				switch (atoi(state->optarg)) {
 				case 2:
 					params->band = WIFI_FREQ_BAND_2_4_GHZ;
@@ -915,6 +944,13 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv
 				case 6:
 					params->band = WIFI_FREQ_BAND_6_GHZ;
 					break;
+				case 0:
+					/* Allow default value when connecting */
+					if (iface_mode == WIFI_MODE_INFRA) {
+						params->band = WIFI_FREQ_BAND_UNKNOWN;
+						break;
+					}
+					__fallthrough;
 				default:
 					PR_ERROR("Invalid band: %d\n", atoi(state->optarg));
 					return -EINVAL;
@@ -999,11 +1035,16 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv
 			key_passwd_cnt++;
 			break;
 		case 'S':
-			params->suiteb_type = atoi(state->optarg);
+			params->wpa3_ent_mode = atoi(state->optarg);
 			break;
 		case 'T':
 			params->TLS_cipher = atoi(state->optarg);
 			break;
+		case 'A':
+			if (iface_mode == WIFI_MODE_INFRA) {
+				params->verify_peer_cert = !!atoi(state->optarg);
+			}
+			break;
 		case 'V':
 			params->eap_ver = atoi(state->optarg);
 			if (params->eap_ver != 0U && params->eap_ver != 1U) {
@@ -1075,6 +1116,16 @@ static int __wifi_args_to_params(const struct shell *sh, size_t argc, char *argv
 		return -EINVAL;
 	}
 
+	if (params->security == WIFI_SECURITY_TYPE_SAE_HNP
+		|| params->security == WIFI_SECURITY_TYPE_SAE_H2E
+		|| params->security == WIFI_SECURITY_TYPE_SAE_AUTO
+		|| params->wpa3_ent_mode != WIFI_WPA3_ENTERPRISE_NA) {
+		if (params->mfp != WIFI_MFP_REQUIRED) {
+			PR_ERROR("MFP is required for WPA3 mode\n");
+			return -EINVAL;
+		}
+	}
+
 	if (iface_mode == WIFI_MODE_AP && params->channel == WIFI_CHANNEL_ANY) {
 		PR_ERROR("Channel not provided\n");
 		return -EINVAL;
@@ -1319,6 +1370,8 @@ static int cmd_wifi_scan(const struct shell *sh, size_t argc, char *argv[])
 	}
 
 	if (do_scan) {
+		net_mgmt_add_event_callback(&wifi_shell_scan_cb);
+
 		if (net_mgmt(NET_REQUEST_WIFI_SCAN, iface, &params, sizeof(params))) {
 			PR_WARNING("Scan request failed\n");
 			return -ENOEXEC;
@@ -1363,7 +1416,8 @@ static int cmd_wifi_status(const struct shell *sh, size_t argc, char *argv[])
 					  sizeof(mac_string_buf)));
 		PR("Band: %s\n", wifi_band_txt(status.band));
 		PR("Channel: %d\n", status.channel);
-		PR("Security: %s\n", wifi_security_txt(status.security));
+		PR("Security: %s %s\n", wifi_wpa3_enterprise_txt(status.wpa3_ent_type),
+								wifi_security_txt(status.security));
 		PR("MFP: %s\n", wifi_mfp_txt(status.mfp));
 		if (status.iface_mode == WIFI_MODE_INFRA) {
 			PR("RSSI: %d\n", status.rssi);
@@ -1429,7 +1483,8 @@ static int cmd_wifi_ap_status(const struct shell *sh, size_t argc, char *argv[])
 						 sizeof(mac_string_buf)));
 	PR("Band: %s\n", wifi_band_txt(status.band));
 	PR("Channel: %d\n", status.channel);
-	PR("Security: %s\n", wifi_security_txt(status.security));
+	PR("Security: %s %s\n", wifi_wpa3_enterprise_txt(status.wpa3_ent_type),
+							wifi_security_txt(status.security));
 	PR("MFP: %s\n", wifi_mfp_txt(status.mfp));
 	if (status.iface_mode == WIFI_MODE_INFRA) {
 		PR("RSSI: %d\n", status.rssi);
@@ -1560,7 +1615,7 @@ static int cmd_wifi_11k_neighbor_request(const struct shell *sh, size_t argc, ch
 
 	context.sh = sh;
 
-	if ((argc != 1 && argc != 3) || (argc == 3 && !strncasecmp("ssid", argv[1], 4))) {
+	if ((argc != 1 && argc != 3) || (argc == 3 && strncasecmp("ssid", argv[1], 4))) {
 		PR_WARNING("Invalid input arguments\n");
 		PR_WARNING("Usage: %s\n", argv[0]);
 		PR_WARNING("or	 %s ssid <ssid>\n", argv[0]);
@@ -2487,7 +2542,6 @@ static int cmd_wifi_listen_interval(const struct shell *sh, size_t argc, char *a
 	return 0;
 }
 
-#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM
 static int cmd_wifi_btm_query(const struct shell *sh, size_t argc, char *argv[])
 {
 	struct net_if *iface = net_if_get_wifi_sta();
@@ -2512,7 +2566,6 @@ static int cmd_wifi_btm_query(const struct shell *sh, size_t argc, char *argv[])
 
 	return 0;
 }
-#endif
 
 static int cmd_wifi_wps_pbc(const struct shell *sh, size_t argc, char *argv[])
 {
@@ -3630,7 +3683,7 @@ SHELL_STATIC_SUBCMD_SET_CREATE(
 		      "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE-HNP, 4:SAE-H2E, 5:SAE-AUTO, 6:WAPI,"
 		      "7:EAP-TLS, 8:WEP, 9: WPA-PSK, 10: WPA-Auto-Personal, 11: DPP\n"
 		      "12: EAP-PEAP-MSCHAPv2, 13: EAP-PEAP-GTC, 14: EAP-TTLS-MSCHAPv2,\n"
-		      "15: EAP-PEAP-TLS\n"
+		      "15: EAP-PEAP-TLS, 20: SAE-EXT-KEY\n"
 		      "-w --ieee-80211w=<MFP> (optional: needs security type to be specified)\n"
 		      "0:Disable, 1:Optional, 2:Required\n"
 		      "-b --band=<band> (2 -2.6GHz, 5 - 5Ghz, 6 - 6GHz)\n"
@@ -3644,7 +3697,9 @@ SHELL_STATIC_SUBCMD_SET_CREATE(
 		      "[-B, --bandwidth=<bandwidth>]: 1:20MHz, 2:40MHz, 3:80MHz\n"
 		      "[-K, --key1-pwd for eap phase1 or --key2-pwd for eap phase2]:\n"
 		      "Private key passwd for enterprise mode. Default no password for private key.\n"
-		      "[-S, --suiteb-type]: 1:suiteb, 2:suiteb-192. Default 0: not suiteb mode.\n"
+		      "[-S, --wpa3-enterprise]: WPA3 enterprise mode:\n"
+		      "Default 0: Not WPA3 enterprise mode.\n"
+		      "1:Suite-b mode, 2:Suite-b-192-bit mode, 3:WPA3-enterprise-only mode.\n"
 		      "[-V, --eap-version]: 0 or 1. Default 1: eap version 1.\n"
 		      "[-I, --eap-id1...--eap-id8]: Client Identity. Default no eap identity.\n"
 		      "[-P, --eap-pwd1...--eap-pwd8]: Client Password.\n"
@@ -3839,12 +3894,10 @@ SHELL_SUBCMD_ADD((wifi), 11k_neighbor_request, NULL,
 		 cmd_wifi_11k_neighbor_request,
 		 1, 2);
 
-#ifdef CONFIG_WIFI_NM_WPA_SUPPLICANT_WNM
 SHELL_SUBCMD_ADD((wifi), 11v_btm_query, NULL,
 		 "<query_reason: The reason code for a BSS transition management query>.\n",
 		 cmd_wifi_btm_query,
 		 2, 0);
-#endif
 
 SHELL_SUBCMD_ADD((wifi), channel, NULL,
 		 "wifi channel setting\n"
@@ -3873,7 +3926,7 @@ SHELL_SUBCMD_ADD((wifi), connect, NULL,
 		  "0:None, 1:WPA2-PSK, 2:WPA2-PSK-256, 3:SAE-HNP, 4:SAE-H2E, 5:SAE-AUTO, 6:WAPI,"
 		  "7:EAP-TLS, 8:WEP, 9: WPA-PSK, 10: WPA-Auto-Personal, 11: DPP\n"
 		  "12: EAP-PEAP-MSCHAPv2, 13: EAP-PEAP-GTC, 14: EAP-TTLS-MSCHAPv2,\n"
-		  "15: EAP-PEAP-TLS\n"
+		  "15: EAP-PEAP-TLS, 20: SAE-EXT-KEY\n"
 		  "[-w, --ieee-80211w]: MFP (optional: needs security type to be specified)\n"
 		  ": 0:Disable, 1:Optional, 2:Required.\n"
 		  "[-m, --bssid]: MAC address of the AP (BSSID).\n"
@@ -3881,8 +3934,12 @@ SHELL_SUBCMD_ADD((wifi), connect, NULL,
 		  "[-a, --anon-id]: Anonymous identity for enterprise mode.\n"
 		  "[-K, --key1-pwd for eap phase1 or --key2-pwd for eap phase2]:\n"
 		  "Private key passwd for enterprise mode. Default no password for private key.\n"
-		  "[-S, --suiteb-type]: 1:suiteb, 2:suiteb-192. Default 0: not suiteb mode.\n"
+		  "[-S, --wpa3-enterprise]: WPA3 enterprise mode:\n"
+		  "Default 0: Not WPA3 enterprise mode.\n"
+		  "1:Suite-b mode, 2:Suite-b-192-bit mode, 3:WPA3-enterprise-only mode.\n"
 		  "[-T, --TLS-cipher]: 0:TLS-NONE, 1:TLS-ECC-P384, 2:TLS-RSA-3K.\n"
+		  "[-A, --verify-peer-cert]: apply for EAP-PEAP-MSCHAPv2 and EAP-TTLS-MSCHAPv2\n"
+		  "Default 0. 0:not use CA to verify peer, 1:use CA to verify peer.\n"
 		  "[-V, --eap-version]: 0 or 1. Default 1: eap version 1.\n"
 		  "[-I, --eap-id1]: Client Identity. Default no eap identity.\n"
 		  "[-P, --eap-pwd1]: Client Password.\n"
@@ -3890,7 +3947,7 @@ SHELL_SUBCMD_ADD((wifi), connect, NULL,
 		  "[-R, --ieee-80211r]: Use IEEE80211R fast BSS transition connect."
 		  "[-h, --help]: Print out the help for the connect command.\n",
 		  cmd_wifi_connect,
-		 2, 19);
+		 2, 40);
 
 SHELL_SUBCMD_ADD((wifi), disconnect, NULL,
 		 "Disconnect from the Wi-Fi AP.\n",
@@ -4058,6 +4115,11 @@ static int wifi_shell_init(void)
 
 	net_mgmt_add_event_callback(&wifi_shell_mgmt_cb);
 
+
+	net_mgmt_init_event_callback(&wifi_shell_scan_cb,
+				     wifi_mgmt_scan_event_handler,
+				     WIFI_SHELL_SCAN_EVENTS);
+
 	return 0;
 }
 
diff --git a/subsys/net/lib/Kconfig b/subsys/net/lib/Kconfig
index ab7aa98373d..e530877125a 100644
--- a/subsys/net/lib/Kconfig
+++ b/subsys/net/lib/Kconfig
@@ -53,4 +53,12 @@ source "subsys/net/lib/prometheus/Kconfig"
 
 source "subsys/net/lib/wifi_credentials/Kconfig"
 
+# Hidden option for VPN usage. Can be selected by the application
+# to setup VPN enablers in the network stack.
+config NET_VPN
+	bool
+	help
+	  Setup VPN enablers in the network stack. Meant to
+	  be enabled by the VPN implementation.
+
 endmenu
diff --git a/subsys/net/lib/capture/cooked.c b/subsys/net/lib/capture/cooked.c
index a076abc0ff2..b4f44034138 100644
--- a/subsys/net/lib/capture/cooked.c
+++ b/subsys/net/lib/capture/cooked.c
@@ -446,10 +446,10 @@ void net_capture_data(struct net_capture_cooked *ctx,
 	 */
 	net_pkt_set_ll_proto_type(pkt, ptype);
 
-	net_pkt_lladdr_src(pkt)->addr = NULL;
+	memset(net_pkt_lladdr_src(pkt)->addr, 0, sizeof(net_pkt_lladdr_src(pkt)->addr));
 	net_pkt_lladdr_src(pkt)->len = 0U;
 	net_pkt_lladdr_src(pkt)->type = NET_LINK_DUMMY;
-	net_pkt_lladdr_dst(pkt)->addr = NULL;
+	memset(net_pkt_lladdr_dst(pkt)->addr, 0, sizeof(net_pkt_lladdr_dst(pkt)->addr));
 	net_pkt_lladdr_dst(pkt)->len = 0U;
 	net_pkt_lladdr_dst(pkt)->type = NET_LINK_DUMMY;
 
diff --git a/subsys/net/lib/coap/Kconfig b/subsys/net/lib/coap/Kconfig
index 443514a6861..3dce7fd1fa4 100644
--- a/subsys/net/lib/coap/Kconfig
+++ b/subsys/net/lib/coap/Kconfig
@@ -166,7 +166,8 @@ config COAP_SERVER
 	bool "CoAP server support [EXPERIMENTAL]"
 	select EXPERIMENTAL
 	select NET_SOCKETS
-	select NET_SOCKETPAIR
+	select ZVFS
+	select ZVFS_EVENTFD
 	help
 	  This option enables the API for CoAP-services to register resources.
 
@@ -247,6 +248,14 @@ config COAP_SERVER_PENDING_ALLOCATOR_STATIC_BLOCKS
 	help
 	  The number of data blocks to reserve for pending messages to retransmit.
 
+config COAP_SERVER_TRUNCATE_MSGS
+	bool "Handle truncated messages"
+	default y
+	help
+	  Include ZSOCK_MSG_TRUNC in flags passed to zsock_recvfrom() to
+	  receive network stack notifications about block truncation.
+	  Otherwise it happens silently.
+
 config COAP_SERVER_SHELL
 	bool "CoAP service shell commands"
 	depends on SHELL
diff --git a/subsys/net/lib/coap/coap.c b/subsys/net/lib/coap/coap.c
index 70f2610adf0..041cc49515a 100644
--- a/subsys/net/lib/coap/coap.c
+++ b/subsys/net/lib/coap/coap.c
@@ -498,6 +498,7 @@ static int decode_delta(uint8_t *data, uint16_t offset, uint16_t *pos, uint16_t
 			uint16_t opt, uint16_t *opt_ext, uint16_t *hdr_len)
 {
 	int ret = 0;
+	*hdr_len = 0;
 
 	if (opt == COAP_OPTION_EXT_13) {
 		uint8_t val;
@@ -1172,7 +1173,7 @@ bool coap_packet_is_request(const struct coap_packet *cpkt)
 {
 	uint8_t code = coap_header_get_code(cpkt);
 
-	return !(code & ~COAP_REQUEST_MASK);
+	return (code != COAP_CODE_EMPTY) && !(code & ~COAP_REQUEST_MASK);
 }
 
 int coap_handle_request_len(struct coap_packet *cpkt,
@@ -1183,7 +1184,7 @@ int coap_handle_request_len(struct coap_packet *cpkt,
 			    struct sockaddr *addr, socklen_t addr_len)
 {
 	if (!coap_packet_is_request(cpkt)) {
-		return 0;
+		return -ENOTSUP;
 	}
 
 	/* FIXME: deal with hierarchical resources */
@@ -1394,7 +1395,7 @@ int insert_option(struct coap_packet *cpkt, uint16_t code, const uint8_t *value,
 	uint16_t opt_len = 0;
 	uint16_t last_opt = 0;
 	uint16_t last_offset = cpkt->hdr_len;
-	struct coap_option option;
+	struct coap_option option = {0};
 	int r;
 
 	while (offset < cpkt->hdr_len + cpkt->opt_len) {
@@ -1548,7 +1549,7 @@ int coap_next_block_for_option(const struct coap_packet *cpkt,
 			       enum coap_option_num option)
 {
 	int block;
-	uint16_t block_len;
+	uint16_t block_len = 0;
 
 	if (option != COAP_OPTION_BLOCK1 && option != COAP_OPTION_BLOCK2) {
 		return -EINVAL;
@@ -1808,39 +1809,71 @@ struct coap_reply *coap_response_received(
 {
 	struct coap_reply *r;
 	uint8_t token[COAP_TOKEN_MAX_LEN];
+	bool piggybacked = false;
+	uint8_t type;
 	uint16_t id;
 	uint8_t tkl;
 	size_t i;
 
-	if (!is_empty_message(response) && coap_packet_is_request(response)) {
-		/* Request can't be response */
+	type = coap_header_get_type(response);
+	id = coap_header_get_id(response);
+	tkl = coap_header_get_token(response, token);
+
+	if ((type == COAP_TYPE_ACK && is_empty_message(response)) ||
+	    coap_packet_is_request(response)) {
+		/* Request or empty ACK can't be response */
 		return NULL;
 	}
 
-	id = coap_header_get_id(response);
-	tkl = coap_header_get_token(response, token);
+	if (type == COAP_TYPE_ACK) {
+		piggybacked = true;
+	}
 
 	for (i = 0, r = replies; i < len; i++, r++) {
 		int age;
 
-		if ((r->id == 0U) && (r->tkl == 0U)) {
+		/* Skip unused entry. */
+		if (r->reply == NULL) {
 			continue;
 		}
 
-		/* Piggybacked must match id when token is empty */
-		if ((r->id != id) && (tkl == 0U)) {
-			continue;
+		/* Reset should only be handled if Message ID matches. */
+		if (type == COAP_TYPE_RESET) {
+			if (r->id != id) {
+				continue;
+			}
+
+			goto handle_reply;
+		}
+
+		/* In a piggybacked response, the Message ID of the Confirmable
+		 * request and the Acknowledgment MUST match, and the tokens of
+		 * the response and original request MUST match.  In a separate
+		 * response, just the tokens of the response and original request
+		 * MUST match.
+		 */
+		if (piggybacked) {
+			if (r->id != id) {
+				continue;
+			}
 		}
 
-		if (tkl > 0 && memcmp(r->token, token, tkl)) {
+		if (r->tkl != tkl) {
 			continue;
 		}
 
+		if (r->tkl > 0) {
+			if (memcmp(r->token, token, r->tkl) != 0) {
+				continue;
+			}
+		}
+
 		age = coap_get_option_int(response, COAP_OPTION_OBSERVE);
 		/* handle observed requests only if received in order */
 		if (age == -ENOENT || coap_age_is_newer(r->age, age)) {
 			r->age = age;
 			if (coap_header_get_code(response) != COAP_RESPONSE_CODE_CONTINUE) {
+handle_reply:
 				r->reply(response, r, from);
 			}
 		}
diff --git a/subsys/net/lib/coap/coap_client.c b/subsys/net/lib/coap/coap_client.c
index b892432c4e8..67fd8af91c1 100644
--- a/subsys/net/lib/coap/coap_client.c
+++ b/subsys/net/lib/coap/coap_client.c
@@ -995,7 +995,15 @@ static int handle_response(struct coap_client *client, const struct coap_packet
 		report_callback_error(internal_req, ret);
 	}
 	if (!internal_req->is_observe) {
-		release_internal_request(internal_req);
+		if (response_type == COAP_TYPE_ACK) {
+			/* This is piggybacked ACK,
+			 * no need to wait for lifetime to expire, all data is already transferred
+			 * and acknowledged
+			 */
+			reset_internal_request(internal_req);
+		} else {
+			release_internal_request(internal_req);
+		}
 	}
 	return ret;
 }
@@ -1013,14 +1021,12 @@ static void cancel_requests_with(struct coap_client *client, int error)
 			 * request was cancelled anyway.
 			 */
 			report_callback_error(&client->requests[i], error);
-			release_internal_request(&client->requests[i]);
 		}
-		/* If our socket has failed, clear all requests, even completed ones,
-		 * so that our handle_poll() does not poll() anymore for this socket.
+
+		/* Clear all requests, even completed ones, so that our
+		 * handle_poll() does not poll() anymore for this socket.
 		 */
-		if (error == -EIO) {
-			reset_internal_request(&client->requests[i]);
-		}
+		reset_internal_request(&client->requests[i]);
 	}
 	k_mutex_unlock(&client->lock);
 
@@ -1112,7 +1118,31 @@ int coap_client_init(struct coap_client *client, const char *info)
 	return 0;
 }
 
+struct coap_client_option coap_client_option_initial_block2(void)
+{
+	struct coap_client_option block2 = {
+		.code = COAP_OPTION_BLOCK2,
+		.len = 1,
+		.value[0] = coap_bytes_to_block_size(CONFIG_COAP_CLIENT_BLOCK_SIZE),
+	};
+
+	return block2;
+}
+
+bool coap_client_has_ongoing_exchange(struct coap_client *client)
+{
+	if (client == NULL) {
+		LOG_ERR("Invalid (NULL) Client");
+		return false;
+	}
+
+	return has_ongoing_exchange(client);
+}
+
+#define COAP_CLIENT_THREAD_PRIORITY CLAMP(CONFIG_COAP_CLIENT_THREAD_PRIORITY, \
+					  K_HIGHEST_APPLICATION_THREAD_PRIO, \
+					  K_LOWEST_APPLICATION_THREAD_PRIO)
 
 K_THREAD_DEFINE(coap_client_recv_thread, CONFIG_COAP_CLIENT_STACK_SIZE,
 		coap_client_recv, NULL, NULL, NULL,
-		CONFIG_COAP_CLIENT_THREAD_PRIORITY, 0, 0);
+		COAP_CLIENT_THREAD_PRIORITY, 0, 0);
diff --git a/subsys/net/lib/coap/coap_link_format.c b/subsys/net/lib/coap/coap_link_format.c
index a3ea175b2df..5e2221b76ab 100644
--- a/subsys/net/lib/coap/coap_link_format.c
+++ b/subsys/net/lib/coap/coap_link_format.c
@@ -36,22 +36,6 @@ static inline bool append_u8(struct coap_packet *cpkt, uint8_t data)
 	return true;
 }
 
-static inline bool append_be16(struct coap_packet *cpkt, uint16_t data)
-{
-	if (!cpkt) {
-		return false;
-	}
-
-	if (cpkt->max_len - cpkt->offset < 2) {
-		return false;
-	}
-
-	cpkt->data[cpkt->offset++] = data >> 8;
-	cpkt->data[cpkt->offset++] = (uint8_t) data;
-
-	return true;
-}
-
 static inline bool append(struct coap_packet *cpkt, const uint8_t *data, uint16_t len)
 {
 	if (!cpkt || !data) {
diff --git a/subsys/net/lib/coap/coap_server.c b/subsys/net/lib/coap/coap_server.c
index 8b7fc0168c3..45fdb7c9825 100644
--- a/subsys/net/lib/coap/coap_server.c
+++ b/subsys/net/lib/coap/coap_server.c
@@ -16,7 +16,8 @@ LOG_MODULE_DECLARE(net_coap, CONFIG_COAP_LOG_LEVEL);
 #include <zephyr/net/coap_link_format.h>
 #include <zephyr/net/coap_mgmt.h>
 #include <zephyr/net/coap_service.h>
-#include <zephyr/posix/fcntl.h>
+#include <zephyr/sys/fdtable.h>
+#include <zephyr/zvfs/eventfd.h>
 
 #if defined(CONFIG_NET_TC_THREAD_COOPERATIVE)
 /* Lowest priority cooperative thread */
@@ -38,7 +39,7 @@ LOG_MODULE_DECLARE(net_coap, CONFIG_COAP_LOG_LEVEL);
 BUILD_ASSERT(CONFIG_ZVFS_POLL_MAX > 0, "CONFIG_ZVFS_POLL_MAX can't be 0");
 
 static K_MUTEX_DEFINE(lock);
-static int control_socks[2];
+static int control_sock;
 
 #if defined(CONFIG_COAP_SERVER_PENDING_ALLOCATOR_STATIC)
 K_MEM_SLAB_DEFINE_STATIC(pending_data, CONFIG_COAP_SERVER_MESSAGE_SIZE,
@@ -135,10 +136,13 @@ static int coap_server_process(int sock_fd)
 	uint8_t type;
 	ssize_t received;
 	int ret;
+	int flags = ZSOCK_MSG_DONTWAIT;
 
-	received = zsock_recvfrom(sock_fd, buf, sizeof(buf), ZSOCK_MSG_DONTWAIT, &client_addr,
-				  &client_addr_len);
-	__ASSERT_NO_MSG(received <= sizeof(buf));
+	if (IS_ENABLED(CONFIG_COAP_SERVER_TRUNCATE_MSGS)) {
+		flags |= ZSOCK_MSG_TRUNC;
+	}
+
+	received = zsock_recvfrom(sock_fd, buf, sizeof(buf), flags, &client_addr, &client_addr_len);
 
 	if (received < 0) {
 		if (errno == EWOULDBLOCK) {
@@ -149,7 +153,7 @@ static int coap_server_process(int sock_fd)
 		return -errno;
 	}
 
-	ret = coap_packet_parse(&request, buf, received, options, opt_num);
+	ret = coap_packet_parse(&request, buf, MIN(received, sizeof(buf)), options, opt_num);
 	if (ret < 0) {
 		LOG_ERR("Failed To parse coap message (%d)", ret);
 		return ret;
@@ -170,6 +174,42 @@ static int coap_server_process(int sock_fd)
 
 	type = coap_header_get_type(&request);
 
+	if (received > sizeof(buf)) {
+		/* The message was truncated and can't be processed further */
+		struct coap_packet response;
+		uint8_t token[COAP_TOKEN_MAX_LEN];
+		uint8_t tkl = coap_header_get_token(&request, token);
+		uint16_t id = coap_header_get_id(&request);
+
+		if (type == COAP_TYPE_CON) {
+			type = COAP_TYPE_ACK;
+		} else {
+			type = COAP_TYPE_NON_CON;
+		}
+
+		ret = coap_packet_init(&response, buf, sizeof(buf), COAP_VERSION_1, type, tkl,
+				       token, COAP_RESPONSE_CODE_REQUEST_TOO_LARGE, id);
+		if (ret < 0) {
+			LOG_ERR("Failed to init response (%d)", ret);
+			goto unlock;
+		}
+
+		ret = coap_append_option_int(&response, COAP_OPTION_SIZE1,
+					     CONFIG_COAP_SERVER_MESSAGE_SIZE);
+		if (ret < 0) {
+			LOG_ERR("Failed to add SIZE1 option (%d)", ret);
+			goto unlock;
+		}
+
+		ret = coap_service_send(service, &response, &client_addr, client_addr_len, NULL);
+		if (ret < 0) {
+			LOG_ERR("Failed to reply \"Request Entity Too Large\" (%d)", ret);
+			goto unlock;
+		}
+
+		goto unlock;
+	}
+
 	pending = coap_pending_received(&request, service->data->pending, MAX_PENDINGS);
 	if (pending) {
 		uint8_t token[COAP_TOKEN_MAX_LEN];
@@ -331,7 +371,7 @@ static int coap_server_poll_timeout(void)
 
 static void coap_server_update_services(void)
 {
-	if (zsock_send(control_socks[1], &(char){0}, 1, 0) < 0) {
+	if (zvfs_eventfd_write(control_sock, 1)) {
 		LOG_ERR("Failed to notify server thread (%d)", errno);
 	}
 }
@@ -429,7 +469,7 @@ int coap_service_start(const struct coap_service *service)
 		goto end;
 	}
 
-	ret = zsock_fcntl(service->data->sock_fd, F_SETFL, O_NONBLOCK);
+	ret = zsock_fcntl(service->data->sock_fd, ZVFS_F_SETFL, ZVFS_O_NONBLOCK);
 	if (ret < 0) {
 		ret = -errno;
 		goto close;
@@ -724,25 +764,12 @@ static void coap_server_thread(void *p1, void *p2, void *p3)
 	ARG_UNUSED(p2);
 	ARG_UNUSED(p3);
 
-	/* Create a socket pair to wake zsock_poll */
-	ret = zsock_socketpair(AF_UNIX, SOCK_STREAM, 0, control_socks);
-	if (ret < 0) {
-		LOG_ERR("Failed to create socket pair (%d)", ret);
+	control_sock = zvfs_eventfd(0, ZVFS_EFD_NONBLOCK);
+	if (control_sock < 0) {
+		LOG_ERR("Failed to create event fd (%d)", -errno);
 		return;
 	}
 
-	for (int i = 0; i < 2; ++i) {
-		ret = zsock_fcntl(control_socks[i], F_SETFL, O_NONBLOCK);
-
-		if (ret < 0) {
-			zsock_close(control_socks[0]);
-			zsock_close(control_socks[1]);
-
-			LOG_ERR("Failed to set socket pair [%d] non-blocking (%d)", i, ret);
-			return;
-		}
-	}
-
 	COAP_SERVICE_FOREACH(svc) {
 		if (svc->flags & COAP_SERVICE_AUTOSTART) {
 			ret = coap_service_start(svc);
@@ -771,9 +798,9 @@ static void coap_server_thread(void *p1, void *p2, void *p3)
 			sock_nfds++;
 		}
 
-		/* Add socket pair FD to allow wake up */
+		/* Add event FD to allow wake up */
 		if (sock_nfds < MAX_POLL_FD) {
-			sock_fds[sock_nfds].fd = control_socks[0];
+			sock_fds[sock_nfds].fd = control_sock;
 			sock_fds[sock_nfds].events = ZSOCK_POLLIN;
 			sock_fds[sock_nfds].revents = 0;
 			sock_nfds++;
@@ -789,11 +816,11 @@ static void coap_server_thread(void *p1, void *p2, void *p3)
 
 		for (int i = 0; i < sock_nfds; ++i) {
 			/* Check the wake up event */
-			if (sock_fds[i].fd == control_socks[0] &&
+			if (sock_fds[i].fd == control_sock &&
 			    sock_fds[i].revents & ZSOCK_POLLIN) {
-				char tmp;
+				zvfs_eventfd_t tmp;
 
-				zsock_recv(sock_fds[i].fd, &tmp, 1, 0);
+				zvfs_eventfd_read(sock_fds[i].fd, &tmp);
 				continue;
 			}
 
diff --git a/subsys/net/lib/config/Kconfig b/subsys/net/lib/config/Kconfig
index e2238a3db47..08e43b6e1b1 100644
--- a/subsys/net/lib/config/Kconfig
+++ b/subsys/net/lib/config/Kconfig
@@ -244,9 +244,18 @@ config NET_CONFIG_SNTP_INIT_RESYNC
 	  Perform an SNTP request over networking periodically to get and
 	  absolute wall clock time, and resync system time from it.
 
+if NET_CONFIG_SNTP_INIT_RESYNC
+
 config NET_CONFIG_SNTP_INIT_RESYNC_INTERVAL
 	int "SNTP resync interval (sec)"
-	depends on NET_CONFIG_SNTP_INIT_RESYNC
 	default 3600
 
+config NET_CONFIG_SNTP_INIT_RESYNC_ON_FAILURE_INTERVAL
+	int "SNTP resync interval (sec) on failure"
+	default NET_CONFIG_SNTP_INIT_RESYNC_INTERVAL
+	help
+	  If the SNTP request fails, then this is the interval to wait
+	  before trying again.
+
+endif # NET_CONFIG_SNTP_INIT_RESYNC
 endif # NET_CONFIG_CLOCK_SNTP_INIT
diff --git a/subsys/net/lib/config/init_clock_sntp.c b/subsys/net/lib/config/init_clock_sntp.c
index 7f90df1d9e3..e027170c688 100644
--- a/subsys/net/lib/config/init_clock_sntp.c
+++ b/subsys/net/lib/config/init_clock_sntp.c
@@ -18,6 +18,11 @@ static void sntp_resync_handler(struct k_work *work);
 static K_WORK_DELAYABLE_DEFINE(sntp_resync_work_handle, sntp_resync_handler);
 #endif
 
+BUILD_ASSERT(
+	IS_ENABLED(CONFIG_NET_CONFIG_SNTP_INIT_SERVER_USE_DHCPV4_OPTION) ||
+	(sizeof(CONFIG_NET_CONFIG_SNTP_INIT_SERVER) != 1),
+	"SNTP server has to be configured, unless DHCPv4 is used to set it");
+
 static int sntp_init_helper(struct sntp_time *tm)
 {
 #ifdef CONFIG_NET_CONFIG_SNTP_INIT_SERVER_USE_DHCPV4_OPTION
@@ -31,6 +36,10 @@ static int sntp_init_helper(struct sntp_time *tm)
 		return sntp_simple_addr((struct sockaddr *)&sntp_addr, sizeof(sntp_addr),
 					CONFIG_NET_CONFIG_SNTP_INIT_TIMEOUT, tm);
 	}
+	if (sizeof(CONFIG_NET_CONFIG_SNTP_INIT_SERVER) == 1) {
+		/* Empty address, skip using SNTP via Kconfig defaults */
+		return -EINVAL;
+	}
 	LOG_INF("SNTP address not set by DHCPv4, using Kconfig defaults");
 #endif /* NET_CONFIG_SNTP_INIT_SERVER_USE_DHCPV4_OPTION */
 	return sntp_simple(CONFIG_NET_CONFIG_SNTP_INIT_SERVER,
@@ -54,8 +63,10 @@ int net_init_clock_via_sntp(void)
 
 end:
 #ifdef CONFIG_NET_CONFIG_SNTP_INIT_RESYNC
-	k_work_reschedule(&sntp_resync_work_handle,
-			  K_SECONDS(CONFIG_NET_CONFIG_SNTP_INIT_RESYNC_INTERVAL));
+	k_work_reschedule(
+		&sntp_resync_work_handle,
+		(res < 0) ? K_SECONDS(CONFIG_NET_CONFIG_SNTP_INIT_RESYNC_ON_FAILURE_INTERVAL)
+			  : K_SECONDS(CONFIG_NET_CONFIG_SNTP_INIT_RESYNC_INTERVAL));
 #endif
 	return res;
 }
diff --git a/subsys/net/lib/dhcpv4/Kconfig b/subsys/net/lib/dhcpv4/Kconfig
index 2c4adcd0649..52dcfc099b5 100644
--- a/subsys/net/lib/dhcpv4/Kconfig
+++ b/subsys/net/lib/dhcpv4/Kconfig
@@ -22,7 +22,6 @@ source "subsys/net/Kconfig.template.log_config.net"
 
 config NET_DHCPV4_INITIAL_DELAY_MAX
 	int "Maximum time out for initial discover request"
-	depends on NET_DHCPV4
 	default 10
 	range 2 10
 	help
@@ -31,7 +30,6 @@ config NET_DHCPV4_INITIAL_DELAY_MAX
 
 config NET_DHCPV4_OPTION_CALLBACKS
 	bool "Option callbacks"
-	depends on NET_DHCPV4
 	help
 	  If set, custom callbacks for arbitrary DHCP options
 	  can be added. These can be used to support otherwise
@@ -39,7 +37,7 @@ config NET_DHCPV4_OPTION_CALLBACKS
 
 config NET_DHCPV4_MAX_REQUESTED_OPTIONS
 	int "Maximum number of requested options"
-	depends on NET_DHCPV4 && NET_DHCPV4_OPTION_CALLBACKS
+	depends on NET_DHCPV4_OPTION_CALLBACKS
 	default 10
 	range 3 $(UINT8_MAX)
 	help
@@ -49,7 +47,6 @@ config NET_DHCPV4_MAX_REQUESTED_OPTIONS
 
 config NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC
 	bool "Encapsulated vendor specific option callbacks"
-	depends on NET_DHCPV4
 	select NET_DHCPV4_OPTION_CALLBACKS
 	help
 	  If set, custom callbacks for encapsulated vendor-specific
@@ -57,7 +54,6 @@ config NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC
 
 config NET_DHCPV4_ACCEPT_UNICAST
 	bool "Accept unicast DHCPv4 traffic"
-	depends on NET_DHCPV4
 	default y
 	help
 	  If set, the network stack will accept unicast DHCPv4 responses from
@@ -65,7 +61,6 @@ config NET_DHCPV4_ACCEPT_UNICAST
 
 config NET_DHCPV4_VENDOR_CLASS_IDENTIFIER
 	bool "Send vendor class identifier in DHCPv4 request"
-	depends on NET_DHCPV4
 	help
 	  If set, the network stack will include the specified string in the
 	  DHCPv4 vendor class identifier option in the DHCPv4 request.
@@ -94,6 +89,13 @@ config NET_DHCPV4_OPTION_DNS_ADDRESS
 	  If this option is set, then the DNS server can be set from the
 	  DHCPv4 option.
 
+config NET_DHCPV4_OPTION_PRINT_IGNORED
+	bool "Print information about ignored options"
+	help
+	  If this option is set, then we print information about options that we
+	  received and ignored. If this is not set, then we print these as unknown
+	  options.
+
 endif # NET_DHCPV4
 
 config NET_DHCPV4_SERVER
@@ -181,4 +183,13 @@ config NET_DHCPV4_SERVER_OPTION_DNS_ADDRESS
 	  acknowledgment messages sent to the clients, allowing them to use the
 	  specified DNS server for name resolution.
 
+config NET_DHCPV4_SERVER_OPTION_ROUTER
+	bool "Set the router option in the DHCP server response"
+	default y
+	help
+	  If enabled, set the DHCP router option pointing to the interface own
+	  gateway address in responses from the DHCP server. This can be
+	  disabled so that the client does not try to forward traffic to our
+	  device.
+
 endif # NET_DHCPV4_SERVER
diff --git a/subsys/net/lib/dhcpv4/dhcpv4.c b/subsys/net/lib/dhcpv4/dhcpv4.c
index 6541365f3a5..2ffb1e96e4d 100644
--- a/subsys/net/lib/dhcpv4/dhcpv4.c
+++ b/subsys/net/lib/dhcpv4/dhcpv4.c
@@ -21,6 +21,7 @@ LOG_MODULE_REGISTER(net_dhcpv4, CONFIG_NET_DHCPV4_LOG_LEVEL);
 #include <zephyr/net/net_pkt.h>
 #include <zephyr/net/net_if.h>
 #include <zephyr/net/net_mgmt.h>
+#include <zephyr/net/hostname.h>
 #include "net_private.h"
 
 #include <zephyr/net/udp.h>
@@ -1053,6 +1054,64 @@ static bool dhcpv4_parse_options(struct net_pkt *pkt,
 
 			break;
 		}
+
+#if defined(CONFIG_NET_DHCPV4_OPTION_PRINT_IGNORED)
+		case DHCPV4_OPTIONS_BROADCAST: {
+			struct in_addr bcast;
+
+			/* Broadcast address option may present 1 address */
+			if (length != 4) {
+				NET_ERR("options_broadcast, bad length");
+				return false;
+			}
+
+			if (net_pkt_read(pkt, bcast.s4_addr, 4)) {
+				NET_ERR("options_broadcast, short packet");
+				return false;
+			}
+
+			NET_DBG("options_broadcast: %s (ignored)",
+				net_sprint_ipv4_addr(&bcast));
+			break;
+		}
+		case DHCPV4_OPTIONS_HOST_NAME: {
+			char hostname[NET_HOSTNAME_SIZE] = { 0 };
+
+			if (length < 1) {
+				NET_ERR("options_host_name, bad length");
+				return false;
+			}
+
+			if (net_pkt_read(pkt, hostname, MIN(length,
+							    sizeof(hostname) - 1))) {
+				NET_ERR("options_host_name, short packet");
+				return false;
+			}
+
+			NET_DBG("options_host_name: %s (ignored%s)", hostname,
+				(length > sizeof(hostname) - 1) ? " and truncated" : "");
+			break;
+		}
+		case DHCPV4_OPTIONS_DOMAIN_NAME: {
+			char domain_name[NET_HOSTNAME_SIZE] = { 0 };
+
+			if (length < 1) {
+				NET_ERR("options_domain_name, bad length");
+				return false;
+			}
+
+			if (net_pkt_read(pkt, domain_name, MIN(length,
+							       sizeof(domain_name) - 1))) {
+				NET_ERR("options_domain_name, short packet");
+				return false;
+			}
+
+			NET_DBG("options_domain_name: %s (ignored%s)", domain_name,
+				(length > sizeof(domain_name) - 1) ? " and truncated" : "");
+			break;
+		}
+#endif /* CONFIG_NET_DHCPV4_OPTION_PRINT_IGNORED */
+
 #if defined(CONFIG_NET_DHCPV4_OPTION_DNS_ADDRESS)
 #define MAX_DNS_SERVERS CONFIG_DNS_RESOLVER_MAX_SERVERS
 		case DHCPV4_OPTIONS_DNS_SERVER: {
@@ -1555,6 +1614,11 @@ static void dhcpv4_iface_event_handler(struct net_mgmt_event_callback *cb,
 {
 	sys_snode_t *node = NULL;
 
+	if (mgmt_event != NET_EVENT_IF_UP &&
+	    mgmt_event != NET_EVENT_IF_DOWN) {
+		return;
+	}
+
 	k_mutex_lock(&lock, K_FOREVER);
 
 	SYS_SLIST_FOR_EACH_NODE(&dhcpv4_ifaces, node) {
@@ -1602,6 +1666,16 @@ static void dhcpv4_acd_event_handler(struct net_mgmt_event_callback *cb,
 	sys_snode_t *node = NULL;
 	struct in_addr *addr;
 
+	if (mgmt_event != NET_EVENT_IPV4_ACD_FAILED &&
+	    mgmt_event != NET_EVENT_IPV4_ACD_CONFLICT) {
+		return;
+	}
+
+	if (cb->info_length != sizeof(struct in_addr)) {
+		return;
+	}
+
+	addr = (struct in_addr *)cb->info;
 
 	k_mutex_lock(&lock, K_FOREVER);
 
@@ -1615,17 +1689,6 @@ static void dhcpv4_acd_event_handler(struct net_mgmt_event_callback *cb,
 		goto out;
 	}
 
-	if (mgmt_event != NET_EVENT_IPV4_ACD_FAILED &&
-	    mgmt_event != NET_EVENT_IPV4_ACD_CONFLICT) {
-		goto out;
-	}
-
-	if (cb->info_length != sizeof(struct in_addr)) {
-		goto out;
-	}
-
-	addr = (struct in_addr *)cb->info;
-
 	if (!net_ipv4_addr_cmp(&iface->config.dhcpv4.requested_ip, addr)) {
 		goto out;
 	}
@@ -1885,8 +1948,7 @@ int net_dhcpv4_init(void)
 	 * all dhcpv4 related incoming packets.
 	 */
 	ret = net_udp_register(AF_INET, NULL, &local_addr,
-			       DHCPV4_SERVER_PORT,
-			       DHCPV4_CLIENT_PORT,
+			       0, DHCPV4_CLIENT_PORT,
 			       NULL, net_dhcpv4_input, NULL, NULL);
 	if (ret < 0) {
 		NET_DBG("UDP callback registration failed");
diff --git a/subsys/net/lib/dhcpv4/dhcpv4_internal.h b/subsys/net/lib/dhcpv4/dhcpv4_internal.h
index 350e16946be..e4c7305a599 100644
--- a/subsys/net/lib/dhcpv4/dhcpv4_internal.h
+++ b/subsys/net/lib/dhcpv4/dhcpv4_internal.h
@@ -56,6 +56,8 @@ struct dhcp_msg {
 #define DHCPV4_OPTIONS_DNS_SERVER	6
 #define DHCPV4_OPTIONS_LOG_SERVER	7
 #define DHCPV4_OPTIONS_HOST_NAME	12
+#define DHCPV4_OPTIONS_DOMAIN_NAME	15
+#define DHCPV4_OPTIONS_BROADCAST	28
 #define DHCPV4_OPTIONS_NTP_SERVER	42
 #define DHCPV4_OPTIONS_VENDOR_SPECIFIC	43
 #define DHCPV4_OPTIONS_REQ_IPADDR	50
diff --git a/subsys/net/lib/dhcpv4/dhcpv4_server.c b/subsys/net/lib/dhcpv4/dhcpv4_server.c
index d56bf83f33b..43ef774c9c8 100644
--- a/subsys/net/lib/dhcpv4/dhcpv4_server.c
+++ b/subsys/net/lib/dhcpv4/dhcpv4_server.c
@@ -516,6 +516,10 @@ static uint8_t *dhcpv4_encode_requested_params(
 			break;
 
 		case DHCPV4_OPTIONS_ROUTER:
+			if (!IS_ENABLED(CONFIG_NET_DHCPV4_SERVER_OPTION_ROUTER)) {
+				break;
+			}
+
 			buf = dhcpv4_encode_router_option(
 				buf, buflen, &ctx->iface->config.ip.ipv4->gw);
 			if (buf == NULL) {
@@ -524,6 +528,10 @@ static uint8_t *dhcpv4_encode_requested_params(
 			break;
 
 		case DHCPV4_OPTIONS_DNS_SERVER:
+			if (strlen(CONFIG_NET_DHCPV4_SERVER_OPTION_DNS_ADDRESS) == 0) {
+				break;
+			}
+
 			buf = dhcpv4_encode_dns_server_option(buf, buflen);
 			if (buf == NULL) {
 				goto out;
diff --git a/subsys/net/lib/dhcpv6/Kconfig b/subsys/net/lib/dhcpv6/Kconfig
index 24443c9b36c..dad049dac77 100644
--- a/subsys/net/lib/dhcpv6/Kconfig
+++ b/subsys/net/lib/dhcpv6/Kconfig
@@ -22,6 +22,15 @@ config NET_DHCPV6_DUID_MAX_LEN
 	help
 	  This will set the available number of bytes for the DUID.
 
+config NET_DHCPV6_OPTION_DNS_ADDRESS
+	bool "Use DNS Recursive Name Server option to configure DNS resolver"
+	default y
+	depends on DNS_RESOLVER
+	help
+	  If enabled, the DHCPv6 client will request DNS Recursive Name Server
+	  option from the server, and if available, use obtained information
+	  to configure DNS resolver.
+
 if NET_DHCPV6
 module = NET_DHCPV6
 module-dep = NET_LOG
diff --git a/subsys/net/lib/dhcpv6/dhcpv6.c b/subsys/net/lib/dhcpv6/dhcpv6.c
index 196b318be37..29dd652d428 100644
--- a/subsys/net/lib/dhcpv6/dhcpv6.c
+++ b/subsys/net/lib/dhcpv6/dhcpv6.c
@@ -12,6 +12,7 @@
 LOG_MODULE_REGISTER(net_dhcpv6, CONFIG_NET_DHCPV6_LOG_LEVEL);
 
 #include <zephyr/net/dhcpv6.h>
+#include <zephyr/net/dns_resolve.h>
 #include <zephyr/net/net_ip.h>
 #include <zephyr/random/random.h>
 #include <zephyr/sys/math_extras.h>
@@ -26,6 +27,12 @@ LOG_MODULE_REGISTER(net_dhcpv6, CONFIG_NET_DHCPV6_LOG_LEVEL);
 /* Maximum number of options client can request. */
 #define DHCPV6_MAX_OPTION_REQUEST 2
 
+#if defined(CONFIG_NET_DHCPV6_OPTION_DNS_ADDRESS)
+#define MAX_DNS_SERVERS CONFIG_DNS_RESOLVER_MAX_SERVERS
+#else
+#define MAX_DNS_SERVERS 1
+#endif
+
 struct dhcpv6_options_include {
 	bool clientid : 1;
 	bool serverid : 1;
@@ -625,7 +632,12 @@ static int dhcpv6_send_solicit(struct net_if *iface)
 		.elapsed_time = true,
 		.ia_na = iface->config.dhcpv6.params.request_addr,
 		.ia_pd = iface->config.dhcpv6.params.request_prefix,
-		.oro = { DHCPV6_OPTION_CODE_SOL_MAX_RT },
+		.oro = {
+			DHCPV6_OPTION_CODE_SOL_MAX_RT,
+#if defined(CONFIG_NET_DHCPV6_OPTION_DNS_ADDRESS)
+			DHCPV6_OPTION_CODE_OPTION_DNS_SERVERS,
+#endif
+		},
 	};
 
 	pkt = dhcpv6_create_message(iface, DHCPV6_MSG_TYPE_SOLICIT, &options);
@@ -651,7 +663,12 @@ static int dhcpv6_send_request(struct net_if *iface)
 		.elapsed_time = true,
 		.ia_na = iface->config.dhcpv6.params.request_addr,
 		.ia_pd = iface->config.dhcpv6.params.request_prefix,
-		.oro = { DHCPV6_OPTION_CODE_SOL_MAX_RT },
+		.oro = {
+			DHCPV6_OPTION_CODE_SOL_MAX_RT,
+#if defined(CONFIG_NET_DHCPV6_OPTION_DNS_ADDRESS)
+			DHCPV6_OPTION_CODE_OPTION_DNS_SERVERS,
+#endif
+		},
 	};
 
 	pkt = dhcpv6_create_message(iface, DHCPV6_MSG_TYPE_REQUEST, &options);
@@ -1178,6 +1195,42 @@ static int dhcpv6_parse_option_ia_pd(struct net_pkt *pkt, uint16_t length,
 	return 0;
 }
 
+static int dhcpv6_parse_option_dns_servers(struct net_pkt *pkt, uint16_t length,
+					   struct sockaddr_in6 *servers,
+					   uint16_t *server_count)
+
+{
+	const uint8_t addr_size = sizeof(struct in6_addr);
+	uint16_t addr_count;
+	int ret;
+
+	if (length % addr_size != 0) {
+		NET_ERR("Invalid DNS Recursive Name Server option size");
+		return -EMSGSIZE;
+	}
+
+	/* Parse only as many server addresses as the buffer allows. */
+	addr_count = length / addr_size;
+	addr_count = MIN(addr_count, *server_count);
+
+	for (int i = 0; i < addr_count; i++) {
+		ret = net_pkt_read(pkt, &servers[i].sin6_addr, addr_size);
+		if (ret < 0) {
+			return ret;
+		}
+
+		length -= addr_size;
+	}
+
+	*server_count = addr_count;
+
+	if (length > 0) {
+		net_pkt_skip(pkt, length);
+	}
+
+	return 0;
+}
+
 static int dhcpv6_find_option(struct net_pkt *pkt, enum dhcpv6_option_code opt_code,
 			      uint16_t *opt_len)
 {
@@ -1327,6 +1380,50 @@ static int dhcpv6_find_status_code(struct net_pkt *pkt, uint16_t *status)
 	return ret;
 }
 
+static int dhcpv6_handle_dns_server_option(struct net_pkt *pkt)
+{
+	const struct sockaddr *dns_servers[MAX_DNS_SERVERS + 1] = { 0 };
+	struct sockaddr_in6 dns_saddr[MAX_DNS_SERVERS] = { 0 };
+	uint16_t server_count = MAX_DNS_SERVERS;
+	struct dns_resolve_context *ctx;
+	struct net_pkt_cursor backup;
+	uint16_t length;
+	int ret, status;
+
+	net_pkt_cursor_backup(pkt, &backup);
+
+	ret = dhcpv6_find_option(pkt, DHCPV6_OPTION_CODE_OPTION_DNS_SERVERS,
+				 &length);
+	if (ret < 0) {
+		/* If the option is not present, don't report an error. */
+		ret = 0;
+		goto out;
+	}
+
+	ret = dhcpv6_parse_option_dns_servers(pkt, length, dns_saddr,
+					      &server_count);
+	if (ret < 0 || server_count == 0) {
+		goto out;
+	}
+
+	for (uint8_t i = 0; i < server_count; i++) {
+		dns_saddr[i].sin6_family = AF_INET6;
+		dns_servers[i] = (struct sockaddr *)&dns_saddr[i];
+	}
+
+	ctx = dns_resolve_get_default();
+	status = dns_resolve_reconfigure(ctx, NULL, dns_servers);
+	if (status < 0) {
+		NET_DBG("Failed to reconfigure DNS resolver from DHCPv6 "
+			"option: %d", status);
+	}
+
+out:
+	net_pkt_cursor_restore(pkt, &backup);
+
+	return ret;
+}
+
 /* DHCPv6 state changes */
 
 static void dhcpv6_enter_init(struct net_if *iface)
@@ -1766,6 +1863,14 @@ static int dhcpv6_handle_reply(struct net_if *iface, struct net_pkt *pkt,
 		}
 	}
 
+	if (IS_ENABLED(CONFIG_NET_DHCPV6_OPTION_DNS_ADDRESS)) {
+		ret = dhcpv6_handle_dns_server_option(pkt);
+		if (ret < 0) {
+			NET_ERR("DNS server option handling failed");
+			return ret;
+		}
+	}
+
 out:
 	if (rediscover) {
 		dhcpv6_enter_state(iface, NET_DHCPV6_SOLICITING);
@@ -2222,7 +2327,7 @@ int net_dhcpv6_init(void)
 	unspec_addr.sa_family = AF_INET6;
 
 	ret = net_udp_register(AF_INET6, NULL, &unspec_addr,
-			       DHCPV6_SERVER_PORT, DHCPV6_CLIENT_PORT,
+			       0, DHCPV6_CLIENT_PORT,
 			       NULL, dhcpv6_input, NULL, NULL);
 	if (ret < 0) {
 		NET_DBG("UDP callback registration failed");
diff --git a/subsys/net/lib/dhcpv6/dhcpv6_internal.h b/subsys/net/lib/dhcpv6/dhcpv6_internal.h
index 5ec129e601f..dd511516fbe 100644
--- a/subsys/net/lib/dhcpv6/dhcpv6_internal.h
+++ b/subsys/net/lib/dhcpv6/dhcpv6_internal.h
@@ -158,6 +158,7 @@ enum dhcpv6_option_code {
 	DHCPV6_OPTION_CODE_INTERFACE_ID = 18,
 	DHCPV6_OPTION_CODE_RECONF_MSG = 19,
 	DHCPV6_OPTION_CODE_RECONF_ACCEPT = 20,
+	DHCPV6_OPTION_CODE_OPTION_DNS_SERVERS = 23,
 	DHCPV6_OPTION_CODE_IA_PD = 25,
 	DHCPV6_OPTION_CODE_IAPREFIX = 26,
 	DHCPV6_OPTION_CODE_INFORMATION_REFRESH_TIME = 32,
diff --git a/subsys/net/lib/dns/Kconfig b/subsys/net/lib/dns/Kconfig
index 8067e85653d..c3f3ba6bc99 100644
--- a/subsys/net/lib/dns/Kconfig
+++ b/subsys/net/lib/dns/Kconfig
@@ -188,6 +188,36 @@ config MDNS_RESPONDER_INIT_PRIO
 	  Note that if NET_CONFIG_AUTO_INIT is enabled, then this value
 	  should be bigger than its value.
 
+config MDNS_RESPONDER_PROBE
+	bool "mDNS probing support [EXPERIMENTAL]"
+	select NET_CONNECTION_MANAGER
+	select MDNS_RESOLVER
+	select DNS_RESOLVER
+	select EXPERIMENTAL
+	help
+	  Note that for probing to work, the mDNS and DNS resolver need to
+	  be enabled. The probing is made optional to allow smaller memory
+	  usage.
+
+config MDNS_WORKQ_STACK_SIZE
+	int "mDNS work queue thread stack size"
+	default 1200 if X86
+	default 1024
+	depends on MDNS_RESPONDER_PROBE
+	help
+	  Set the mDNS work queue thread stack size in bytes.
+
+config MDNS_WORKER_PRIO
+	int "Priority of the mDNS work queue"
+	default 2
+	depends on MDNS_RESPONDER_PROBE
+	help
+	  Set the priority of the mDNS worker queue, that handles all
+	  mDNS probing. Value 0 = highest priortity.
+	  When CONFIG_NET_TC_THREAD_COOPERATIVE = y, lowest priority is
+	  CONFIG_NUM_COOP_PRIORITIES-1 else lowest priority is
+	  CONFIG_NUM_PREEMPT_PRIORITIES-1.
+
 config MDNS_RESPONDER_DNS_SD
 	bool "DNS Service Discovery via mDNS"
 	default y
diff --git a/subsys/net/lib/dns/dispatcher.c b/subsys/net/lib/dns/dispatcher.c
index c0803f093bd..a296adcb698 100644
--- a/subsys/net/lib/dns/dispatcher.c
+++ b/subsys/net/lib/dns/dispatcher.c
@@ -63,11 +63,11 @@ static int dns_dispatch(struct dns_socket_dispatcher *dispatcher,
 	if (is_query) {
 		if (dispatcher->type == DNS_SOCKET_RESPONDER) {
 			/* Call the responder callback */
-			ret = dispatcher->cb(dispatcher->ctx, sock,
+			ret = dispatcher->cb(dispatcher, sock,
 					     addr, addrlen,
 					     dns_data, data_len);
 		} else if (dispatcher->pair) {
-			ret = dispatcher->pair->cb(dispatcher->pair->ctx, sock,
+			ret = dispatcher->pair->cb(dispatcher, sock,
 						   addr, addrlen,
 						   dns_data, data_len);
 		} else {
@@ -81,11 +81,11 @@ static int dns_dispatch(struct dns_socket_dispatcher *dispatcher,
 		 */
 		if (dispatcher->type == DNS_SOCKET_RESOLVER) {
 			/* Call the resolver callback */
-			ret = dispatcher->cb(dispatcher->ctx, sock,
+			ret = dispatcher->cb(dispatcher, sock,
 					     addr, addrlen,
 					     dns_data, data_len);
 		} else if (dispatcher->pair) {
-			ret = dispatcher->pair->cb(dispatcher->pair->ctx, sock,
+			ret = dispatcher->pair->cb(dispatcher, sock,
 						   addr, addrlen,
 						   dns_data, data_len);
 		} else {
@@ -190,7 +190,7 @@ void dns_dispatcher_svc_handler(struct net_socket_service_event *pev)
 
 	ret = recv_data(pev);
 	if (ret < 0 && ret != DNS_EAI_ALLDONE && ret != -ENOENT) {
-		NET_ERR("DNS recv error (%d)", ret);
+		NET_DBG("DNS recv error (%d)", ret);
 	}
 }
 
diff --git a/subsys/net/lib/dns/dns_cache.c b/subsys/net/lib/dns/dns_cache.c
index 9364189f22e..29a1bc1b9cf 100644
--- a/subsys/net/lib/dns/dns_cache.c
+++ b/subsys/net/lib/dns/dns_cache.c
@@ -5,6 +5,7 @@
  */
 
 #include <zephyr/net/dns_resolve.h>
+#include <zephyr/net/net_ip.h>
 #include "dns_cache.h"
 
 LOG_MODULE_REGISTER(net_dns_cache, CONFIG_DNS_RESOLVER_LOG_LEVEL);
@@ -97,15 +98,23 @@ int dns_cache_remove(struct dns_cache *cache, char const *query)
 	return 0;
 }
 
-int dns_cache_find(struct dns_cache const *cache, const char *query, struct dns_addrinfo *addrinfo,
-		   size_t addrinfo_array_len)
+int dns_cache_find(struct dns_cache const *cache, const char *query, enum dns_query_type type,
+		   struct dns_addrinfo *addrinfo, size_t addrinfo_array_len)
 {
 	size_t found = 0;
+	sa_family_t family;
 
 	NET_DBG("Find \"%s\"", query);
 	if (cache == NULL || query == NULL || addrinfo == NULL || addrinfo_array_len <= 0) {
 		return -EINVAL;
 	}
+	if (type == DNS_QUERY_TYPE_A) {
+		family = AF_INET;
+	} else if (type == DNS_QUERY_TYPE_AAAA) {
+		family = AF_INET6;
+	} else {
+		return -EINVAL;
+	}
 	if (strlen(query) >= CONFIG_DNS_RESOLVER_MAX_QUERY_LEN) {
 		NET_WARN("Query string to big to be processed %u >= "
 			 "CONFIG_DNS_RESOLVER_MAX_QUERY_LEN",
@@ -124,6 +133,9 @@ int dns_cache_find(struct dns_cache const *cache, const char *query, struct dns_
 		if (strcmp(cache->entries[i].query, query) != 0) {
 			continue;
 		}
+		if (cache->entries[i].data.ai_family != family) {
+			continue;
+		}
 		if (found >= addrinfo_array_len) {
 			NET_WARN("Found \"%s\" but not enough space in provided buffer.", query);
 			found++;
diff --git a/subsys/net/lib/dns/dns_cache.h b/subsys/net/lib/dns/dns_cache.h
index b389c491713..1780824b087 100644
--- a/subsys/net/lib/dns/dns_cache.h
+++ b/subsys/net/lib/dns/dns_cache.h
@@ -86,6 +86,7 @@ int dns_cache_remove(struct dns_cache *cache, char const *query);
  *
  * @param cache Cache where the entry should be searched.
  * @param query Query which should be searched for.
+ * @param type Query type which will control the types of addresses that will be found.
  * @param addrinfo dns_addrinfo array which will be written if the query was found.
  * @param addrinfo_array_len Array size of the dns_addrinfo array
  * @retval on success the amount of dns_addrinfo written into the addrinfo array will be returned.
@@ -94,7 +95,7 @@ int dns_cache_remove(struct dns_cache *cache, char const *query);
  * -ENOSR means there was not enough space in the addrinfo array to accommodate all cache hits the
  * array will however be filled with valid data.
  */
-int dns_cache_find(struct dns_cache const *cache, const char *query, struct dns_addrinfo *addrinfo,
-		   size_t addrinfo_array_len);
+int dns_cache_find(struct dns_cache const *cache, const char *query, enum dns_query_type type,
+		   struct dns_addrinfo *addrinfo, size_t addrinfo_array_len);
 
 #endif /* ZEPHYR_INCLUDE_NET_DNS_CACHE_H_ */
diff --git a/subsys/net/lib/dns/dns_pack.c b/subsys/net/lib/dns/dns_pack.c
index 3607514abf3..a1efc20f81a 100644
--- a/subsys/net/lib/dns/dns_pack.c
+++ b/subsys/net/lib/dns/dns_pack.c
@@ -5,6 +5,8 @@
  */
 
 #include <string.h>
+#include <zephyr/sys/bitarray.h>
+#include <zephyr/net/dns_resolve.h>
 #include <zephyr/net_buf.h>
 
 #include "dns_pack.h"
@@ -352,8 +354,14 @@ int dns_unpack_response_query(struct dns_msg_t *dns_msg)
 		return -EINVAL;
 	}
 
-	dns_msg->answer_offset = dns_msg->query_offset + qname_size +
-				 DNS_QTYPE_LEN + DNS_QCLASS_LEN;
+	offset = dns_msg->query_offset + qname_size +
+		 DNS_QTYPE_LEN + DNS_QCLASS_LEN;
+
+	if (offset >= dns_msg->msg_size) {
+		return -ENOMEM;
+	}
+
+	dns_msg->answer_offset = offset;
 
 	return 0;
 }
@@ -361,10 +369,11 @@ int dns_unpack_response_query(struct dns_msg_t *dns_msg)
 int dns_copy_qname(uint8_t *buf, uint16_t *len, uint16_t size,
 		   struct dns_msg_t *dns_msg, uint16_t pos)
 {
+	SYS_BITARRAY_DEFINE(visited, DNS_RESOLVER_MAX_BUF_SIZE);
 	uint16_t msg_size = dns_msg->msg_size;
 	uint8_t *msg = dns_msg->msg;
 	uint16_t lb_size;
-	int rc = -EINVAL;
+	int rc = -EINVAL, ret, prev;
 
 	*len = 0U;
 
@@ -377,7 +386,7 @@ int dns_copy_qname(uint8_t *buf, uint16_t *len, uint16_t size,
 		lb_size = msg[pos];
 
 		/* pointer */
-		if (lb_size > DNS_LABEL_MAX_SIZE) {
+		if ((lb_size & NS_CMPRSFLGS) == NS_CMPRSFLGS) {
 			uint8_t mask = DNS_LABEL_MAX_SIZE;
 
 			if (pos + 1 >= msg_size) {
@@ -388,7 +397,21 @@ int dns_copy_qname(uint8_t *buf, uint16_t *len, uint16_t size,
 			/* See: RFC 1035, 4.1.4. Message compression */
 			pos = ((msg[pos] & mask) << 8) + msg[pos + 1];
 
+			ret = sys_bitarray_test_and_set_bit(&visited, pos, &prev);
+			if (ret < 0) {
+				rc = -EINVAL;
+				break;
+			}
+
+			if (prev) {
+				rc = -ELOOP;
+				break;
+			}
+
 			continue;
+		} else if (lb_size & NS_CMPRSFLGS) {
+			rc = -EINVAL;
+			break;
 		}
 
 		/* validate that the label (i.e. size + elements),
@@ -478,7 +501,7 @@ static int dns_unpack_name(const uint8_t *msg, int maxlen, const uint8_t *src,
 	}
 
 	while ((val = *curr_src++)) {
-		if (val & NS_CMPRSFLGS) {
+		if ((val & NS_CMPRSFLGS) == NS_CMPRSFLGS) {
 			/* Follow pointer */
 			int pos;
 
@@ -586,6 +609,7 @@ int dns_unpack_query(struct dns_msg_t *dns_msg, struct net_buf *buf,
 		&& query_type != DNS_RR_TYPE_PTR
 		&& query_type != DNS_RR_TYPE_SRV
 		&& query_type != DNS_RR_TYPE_TXT
+		&& query_type != DNS_RR_TYPE_HTTPS
 		&& query_type != DNS_RR_TYPE_ANY) {
 		return -EINVAL;
 	}
diff --git a/subsys/net/lib/dns/dns_pack.h b/subsys/net/lib/dns/dns_pack.h
index 58041ed6e03..07ad7bc6723 100644
--- a/subsys/net/lib/dns/dns_pack.h
+++ b/subsys/net/lib/dns/dns_pack.h
@@ -93,6 +93,7 @@ enum dns_rr_type {
 	DNS_RR_TYPE_TXT = 16,		/* TXT   */
 	DNS_RR_TYPE_AAAA = 28,		/* IPv6  */
 	DNS_RR_TYPE_SRV = 33,		/* SRV   */
+	DNS_RR_TYPE_HTTPS = 65,		/* HTTPS */
 	DNS_RR_TYPE_ANY = 0xff,		/* ANY (all records)   */
 };
 
diff --git a/subsys/net/lib/dns/mdns_responder.c b/subsys/net/lib/dns/mdns_responder.c
index bb96d7813ff..29f1c657ae1 100644
--- a/subsys/net/lib/dns/mdns_responder.c
+++ b/subsys/net/lib/dns/mdns_responder.c
@@ -8,6 +8,7 @@
  * Copyright (c) 2017 Intel Corporation
  * Copyright (c) 2020 Friedt Professional Engineering Services, Inc
  * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 SynchronicIT BV
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,6 +23,7 @@ LOG_MODULE_REGISTER(net_mdns_responder, CONFIG_MDNS_RESPONDER_LOG_LEVEL);
 #include <errno.h>
 #include <stdlib.h>
 
+#include <zephyr/random/random.h>
 #include <zephyr/net/mld.h>
 #include <zephyr/net/net_core.h>
 #include <zephyr/net/net_ip.h>
@@ -42,12 +44,8 @@ LOG_MODULE_REGISTER(net_mdns_responder, CONFIG_MDNS_RESPONDER_LOG_LEVEL);
  * address-family-specific variants being of differing sizes. Let's not
  * mess with code (which looks correct), just silence the compiler.
  */
-#ifdef __GNUC__
-#pragma GCC diagnostic ignored "-Wpragmas"
-#pragma GCC diagnostic ignored "-Wunknown-warning-option"
-#pragma GCC diagnostic ignored "-Warray-bounds"
-#pragma GCC diagnostic ignored "-Wstringop-overread"
-#endif
+TOOLCHAIN_DISABLE_GCC_WARNING(TOOLCHAIN_WARNING_ARRAY_BOUNDS);
+TOOLCHAIN_DISABLE_GCC_WARNING(TOOLCHAIN_WARNING_STRINGOP_OVERREAD);
 
 extern void dns_dispatcher_svc_handler(struct net_socket_service_event *pev);
 
@@ -69,7 +67,39 @@ NET_SOCKET_SERVICE_SYNC_DEFINE_STATIC(v6_svc, dns_dispatcher_svc_handler,
 				      MDNS_MAX_IPV6_IFACE_COUNT);
 #endif
 
-static struct net_mgmt_event_callback mgmt_cb;
+static struct net_mgmt_event_callback mgmt_iface_cb;
+
+#if defined(CONFIG_MDNS_RESPONDER_PROBE)
+static void cancel_probes(struct mdns_responder_context *ctx);
+static struct net_mgmt_event_callback mgmt_conn_cb;
+#if defined(CONFIG_NET_IPV4)
+static struct net_mgmt_event_callback mgmt4_addr_cb;
+#endif
+#if defined(CONFIG_NET_IPV6)
+static struct net_mgmt_event_callback mgmt6_addr_cb;
+#endif
+static struct k_work_q mdns_work_q;
+static K_KERNEL_STACK_DEFINE(mdns_work_q_stack, CONFIG_MDNS_WORKQ_STACK_SIZE);
+struct k_work_delayable init_listener_timer;
+static int failed_probes;
+static int probe_count;
+static int announce_count;
+static bool do_announce;
+static bool init_listener_done;
+
+/* Collect added/deleted IP addresses to announce them */
+struct mdns_monitor_iface_addr {
+	struct net_if *iface;
+	struct net_addr addr;
+	bool in_use : 1;
+	bool needs_announce : 1;
+};
+
+static struct mdns_monitor_iface_addr mon_if[
+	MAX(MAX_IPV4_IFACE_COUNT, MAX_IPV4_IFACE_COUNT) *
+	(NET_IF_MAX_IPV4_ADDR + NET_IF_MAX_IPV6_ADDR)];
+#endif
+
 static const struct dns_sd_rec *external_records;
 static size_t external_records_count;
 
@@ -77,6 +107,7 @@ static size_t external_records_count;
 
 #ifndef CONFIG_NET_TEST
 static int setup_dst_addr(int sock, sa_family_t family,
+			  struct sockaddr *src, socklen_t src_len,
 			  struct sockaddr *dst, socklen_t *dst_len);
 #endif /* CONFIG_NET_TEST */
 
@@ -106,6 +137,25 @@ static void create_ipv4_addr(struct sockaddr_in *addr)
 	addr->sin_addr.s_addr = htonl(0xE00000FB);
 }
 
+#if defined(CONFIG_MDNS_RESPONDER_PROBE)
+static void mark_needs_announce(struct net_if *iface, bool needs_announce)
+{
+	ARRAY_FOR_EACH(mon_if, i) {
+		if (!mon_if[i].in_use) {
+			continue;
+		}
+
+		if (iface != NULL) {
+			if (mon_if[i].iface != iface) {
+				continue;
+			}
+		}
+
+		mon_if[i].needs_announce = needs_announce;
+	}
+}
+#endif /* CONFIG_MDNS_RESPONDER_PROBE */
+
 static void mdns_iface_event_handler(struct net_mgmt_event_callback *cb,
 				     uint32_t mgmt_event, struct net_if *iface)
 
@@ -116,13 +166,24 @@ static void mdns_iface_event_handler(struct net_mgmt_event_callback *cb,
 			int ret = net_ipv4_igmp_join(iface,
 					&net_sin(&v4_ctx[i].dispatcher.local_addr)->sin_addr,
 					NULL);
-			if (ret < 0) {
-				NET_DBG("Cannot add IPv4 multicast address to iface %d",
-					net_if_get_by_iface(iface));
+			if (ret < 0 && ret != -EALREADY) {
+				NET_DBG("Cannot add IPv4 multicast address %s to iface %d (%d)",
+					net_sprint_ipv4_addr(&net_sin(
+						&v4_ctx[i].dispatcher.local_addr)->sin_addr),
+					net_if_get_by_iface(iface), ret);
 			}
 		}
 #endif /* defined(CONFIG_NET_IPV4) */
 	}
+
+#if defined(CONFIG_MDNS_RESPONDER_PROBE)
+	if (mgmt_event == NET_EVENT_IF_UP && init_listener_done) {
+		do_announce = true;
+		announce_count = 0;
+
+		mark_needs_announce(iface, true);
+	}
+#endif /* CONFIG_MDNS_RESPONDER_PROBE */
 }
 
 static int set_ttl_hop_limit(int sock, int level, int option, int new_limit)
@@ -131,25 +192,36 @@ static int set_ttl_hop_limit(int sock, int level, int option, int new_limit)
 }
 
 int setup_dst_addr(int sock, sa_family_t family,
+		   struct sockaddr *src, socklen_t src_len,
 		   struct sockaddr *dst, socklen_t *dst_len)
 {
 	int ret;
 
 	if (IS_ENABLED(CONFIG_NET_IPV4) && family == AF_INET) {
-		create_ipv4_addr(net_sin(dst));
-		*dst_len = sizeof(struct sockaddr_in);
+		if ((src != NULL) && (net_sin(src)->sin_port != htons(MDNS_LISTEN_PORT))) {
+			memcpy(dst, src, src_len);
+			*dst_len = src_len;
+		} else {
+			create_ipv4_addr(net_sin(dst));
+			*dst_len = sizeof(struct sockaddr_in);
 
-		ret = set_ttl_hop_limit(sock, IPPROTO_IP, IP_MULTICAST_TTL, 255);
-		if (ret < 0) {
-			NET_DBG("Cannot set %s multicast %s (%d)", "IPv4", "TTL", ret);
+			ret = set_ttl_hop_limit(sock, IPPROTO_IP, IP_MULTICAST_TTL, 255);
+			if (ret < 0) {
+				NET_DBG("Cannot set %s multicast %s (%d)", "IPv4", "TTL", ret);
+			}
 		}
 	} else if (IS_ENABLED(CONFIG_NET_IPV6) && family == AF_INET6) {
-		create_ipv6_addr(net_sin6(dst));
-		*dst_len = sizeof(struct sockaddr_in6);
+		if ((src != NULL) && (net_sin6(src)->sin6_port != htons(MDNS_LISTEN_PORT))) {
+			memcpy(dst, src, src_len);
+			*dst_len = src_len;
+		} else {
+			create_ipv6_addr(net_sin6(dst));
+			*dst_len = sizeof(struct sockaddr_in6);
 
-		ret = set_ttl_hop_limit(sock, IPPROTO_IPV6, IPV6_MULTICAST_HOPS, 255);
-		if (ret < 0) {
-			NET_DBG("Cannot set %s multicast %s (%d)", "IPv6", "hoplimit", ret);
+			ret = set_ttl_hop_limit(sock, IPPROTO_IPV6, IPV6_MULTICAST_HOPS, 255);
+			if (ret < 0) {
+				NET_DBG("Cannot set %s multicast %s (%d)", "IPv6", "hoplimit", ret);
+			}
 		}
 	} else {
 		return -EPFNOSUPPORT;
@@ -165,7 +237,6 @@ static int get_socket(sa_family_t family)
 	ret = zsock_socket(family, SOCK_DGRAM, IPPROTO_UDP);
 	if (ret < 0) {
 		ret = -errno;
-		NET_DBG("Cannot get socket (%d)", ret);
 	}
 
 	return ret;
@@ -283,7 +354,7 @@ static int send_response(int sock,
 	COND_CODE_1(IS_ENABLED(CONFIG_NET_IPV6),
 		    (struct sockaddr_in6), (struct sockaddr_in)) dst;
 
-	ret = setup_dst_addr(sock, family, (struct sockaddr *)&dst, &dst_len);
+	ret = setup_dst_addr(sock, family, src_addr, addrlen, (struct sockaddr *)&dst, &dst_len);
 	if (ret < 0) {
 		NET_DBG("unable to set up the response address");
 		return ret;
@@ -337,6 +408,7 @@ static int send_response(int sock,
 	ret = zsock_sendto(sock, query->data, query->len, 0,
 			   (struct sockaddr *)&dst, dst_len);
 	if (ret < 0) {
+		ret = -errno;
 		NET_DBG("Cannot send %s reply (%d)", "mDNS", ret);
 	} else {
 		net_stats_update_dns_sent(iface);
@@ -392,7 +464,7 @@ static void send_sd_response(int sock,
 	label[2] = proto_buf;
 	label[3] = domain_buf;
 
-	ret = setup_dst_addr(sock, family, (struct sockaddr *)&dst, &dst_len);
+	ret = setup_dst_addr(sock, family, src_addr, addrlen, (struct sockaddr *)&dst, &dst_len);
 	if (ret < 0) {
 		NET_DBG("unable to set up the response address");
 		return;
@@ -544,12 +616,15 @@ static int dns_read(int sock,
 
 	queries = ret;
 
-	NET_DBG("Received %d %s from %s", queries,
+	NET_DBG("Received %d %s from %s:%u", queries,
 		queries > 1 ? "queries" : "query",
 		net_sprint_addr(family,
 				family == AF_INET ?
 				(const void *)&net_sin(src_addr)->sin_addr :
-				(const void *)&net_sin6(src_addr)->sin6_addr));
+				(const void *)&net_sin6(src_addr)->sin6_addr),
+				ntohs(family == AF_INET ?
+				net_sin(src_addr)->sin_port :
+				net_sin6(src_addr)->sin6_port));
 
 	do {
 		enum dns_rr_type qtype;
@@ -581,8 +656,9 @@ static int dns_read(int sock,
 		if (!strncasecmp(hostname, result->data + 1, hostname_len) &&
 		    (result->len - 1) >= hostname_len &&
 		    &(result->data + 1)[hostname_len] == lquery) {
-			NET_DBG("%s query to our hostname %s.local", "mDNS",
-				hostname);
+			NET_DBG("%s %s %s to our hostname %s%s", "mDNS",
+				family == AF_INET ? "IPv4" : "IPv6", "query",
+				hostname, ".local");
 			send_response(sock, family, src_addr, addrlen,
 				      result, qtype);
 		} else if (IS_ENABLED(CONFIG_MDNS_RESPONDER_DNS_SD)
@@ -603,6 +679,448 @@ static int dns_read(int sock,
 	return ret;
 }
 
+/* The probing sends mDNS query so in order that to work the mDNS resolver
+ * needs to be enabled.
+ */
+#if defined(CONFIG_MDNS_RESPONDER_PROBE)
+
+static int add_address(struct net_if *iface, sa_family_t family,
+		       const void *address, size_t addrlen)
+{
+	size_t expected_len;
+	int first_free;
+
+	if (family != AF_INET && family != AF_INET6) {
+		return -EINVAL;
+	}
+
+	if (family == AF_INET) {
+		expected_len = sizeof(struct in_addr);
+	} else {
+		expected_len = sizeof(struct in6_addr);
+	}
+
+	if (addrlen != expected_len) {
+		return -EINVAL;
+	}
+
+	first_free = -1;
+
+	ARRAY_FOR_EACH(mon_if, j) {
+		if (!mon_if[j].in_use) {
+			if (first_free < 0) {
+				first_free = j;
+			}
+		}
+
+		if (mon_if[j].iface != iface) {
+			continue;
+		}
+
+		if (mon_if[j].addr.family != family) {
+			continue;
+		}
+
+		if (memcmp(&mon_if[j].addr.in_addr, address, expected_len) == 0) {
+			return -EALREADY;
+		}
+	}
+
+	if (first_free >= 0) {
+		mon_if[first_free].in_use = true;
+		mon_if[first_free].iface = iface;
+		mon_if[first_free].addr.family = family;
+
+		memcpy(&mon_if[first_free].addr.in_addr, address, expected_len);
+
+		NET_DBG("%s added %s address %s to iface %d in slot %d",
+			"mDNS", family == AF_INET ? "IPv4" : "IPv6",
+			family == AF_INET ? net_sprint_ipv4_addr(address) :
+					    net_sprint_ipv6_addr(address),
+			net_if_get_by_iface(iface), first_free);
+		return 0;
+	}
+
+	return -ENOENT;
+}
+
+static int del_address(struct net_if *iface, sa_family_t family,
+		       const void *address, size_t addrlen)
+{
+	size_t expected_len;
+
+	if (family != AF_INET && family != AF_INET6) {
+		return -EINVAL;
+	}
+
+	if (family == AF_INET) {
+		expected_len = sizeof(struct in_addr);
+	} else {
+		expected_len = sizeof(struct in6_addr);
+	}
+
+	ARRAY_FOR_EACH(mon_if, j) {
+		if (!mon_if[j].in_use) {
+			continue;
+		}
+
+		if (mon_if[j].iface != iface) {
+			continue;
+		}
+
+		if (mon_if[j].addr.family != family) {
+			continue;
+		}
+
+		if (memcmp(&mon_if[j].addr.in_addr, address, expected_len) == 0) {
+			mon_if[j].in_use = false;
+			return 0;
+		}
+	}
+
+	return -ENOENT;
+}
+
+static void probe_cb(enum dns_resolve_status status,
+		     struct dns_addrinfo *info,
+		     void *user_data)
+{
+	struct mdns_probe_user_data *ud = user_data;
+
+	NET_DBG("status %d", status);
+
+	if (status == DNS_EAI_ALLDONE) {
+		/* We got a reply, so we can stop probing as there was reply
+		 * to our query.
+		 */
+		cancel_probes(ud->ctx);
+		failed_probes++;
+
+		NET_WARN("mDNS probe received data, will not use \"%s\" name.",
+			 ud->query);
+
+		dns_resolve_close(&ud->ctx->probe_ctx);
+
+	} else if (status == DNS_EAI_CANCELED) {
+		if (--probe_count <= 0) {
+			int ret;
+
+			dns_resolve_close(&ud->ctx->probe_ctx);
+
+			/* Schedule a handler that will initialize the listener
+			 * and start announcing the services.
+			 */
+			ret = k_work_reschedule_for_queue(&mdns_work_q,
+							  &init_listener_timer,
+							  K_NO_WAIT);
+			if (ret < 0) {
+				NET_DBG("Cannot schedule %s init work (%d)", "mDNS", ret);
+			}
+		}
+	}
+}
+
+#define PROBE_TIMEOUT 1750 /* in ms, see RFC 6762 ch 8.1 */
+#define PORT_COUNT 5
+
+/* Sending unsolicited mDNS query when interface is up. RFC 6762 ch 8.1 */
+static int send_probe(struct mdns_responder_context *ctx)
+{
+	const char *hostname = net_hostname_get();
+	struct sockaddr *servers[2] = { 0 };
+	struct sockaddr_in6 server = { 0 };
+	int interfaces[ARRAY_SIZE(servers)] = { 0 };
+	uint16_t local_port;
+	int ret;
+
+	NET_DBG("%s %s %s to our hostname %s%s iface %d", "mDNS",
+		ctx->dispatcher.local_addr.sa_family == AF_INET ? "IPv4" : "IPv6",
+		"probe", hostname, ".local", net_if_get_by_iface(ctx->iface));
+
+	ret = 0;
+	do {
+		local_port = sys_rand16_get() | 0x8000;
+		ret++;
+	} while (net_context_port_in_use(IPPROTO_UDP, local_port,
+					 &ctx->dispatcher.local_addr) && ret < PORT_COUNT);
+	if (ret >= PORT_COUNT) {
+		NET_ERR("No available port, %s probe fails!", "mDNS");
+		ret = -EIO;
+		goto out;
+	}
+
+	if (ctx->dispatcher.local_addr.sa_family == AF_INET) {
+		create_ipv4_addr((struct sockaddr_in *)&server);
+	} else {
+		create_ipv6_addr(&server);
+	}
+
+	servers[0] = (struct sockaddr *)&server;
+	interfaces[0] = net_if_get_by_iface(ctx->iface);
+
+	ret = dns_resolve_init_with_svc(&ctx->probe_ctx, NULL,
+					(const struct sockaddr **)servers,
+					ctx->dispatcher.svc, local_port,
+					interfaces);
+	if (ret < 0) {
+		NET_DBG("Cannot initialize DNS resolver (%d)", ret);
+		goto out;
+	}
+
+	snprintk(ctx->probe_data.query, sizeof(ctx->probe_data.query),
+		 "%s%s", hostname, ".local");
+
+	ctx->probe_data.dns_id = 0U;
+	ctx->probe_data.ctx = ctx;
+
+	NET_DBG("Sending mDNS probe for %s to iface %d",
+		ctx->probe_data.query, interfaces[0]);
+
+	/* Then the actual probe sending. RFC 6762 ch 8.1 says to use
+	 * the ANY resource type. Use the internal resolve function that does
+	 * not use cache.
+	 */
+	ret = dns_resolve_name_internal(&ctx->probe_ctx, ctx->probe_data.query,
+					DNS_RR_TYPE_ANY,
+					&ctx->probe_data.dns_id, probe_cb,
+					&ctx->probe_data, PROBE_TIMEOUT,
+					false);
+	if (ret < 0) {
+		NET_DBG("Cannot send mDNS probe (%d)", ret);
+		goto fail;
+	}
+
+	probe_count++;
+
+	return 0;
+
+fail:
+	dns_resolve_close(&ctx->probe_ctx);
+out:
+	return ret;
+}
+
+static void cancel_probes(struct mdns_responder_context *ctx)
+{
+#if defined(CONFIG_NET_IPV4)
+	ARRAY_FOR_EACH(v4_ctx, i) {
+		if (&v4_ctx[i] == ctx) {
+			continue;
+		}
+
+		NET_DBG("Cancel probe for %s mDNS ctx %p", "IPv4", ctx);
+
+		(void)k_work_cancel_delayable(&v4_ctx[i].probe_timer);
+	}
+#endif /* defined(CONFIG_NET_IPV4) */
+
+#if defined(CONFIG_NET_IPV6)
+	ARRAY_FOR_EACH(v6_ctx, i) {
+		if (&v6_ctx[i] == ctx) {
+			continue;
+		}
+
+		NET_DBG("Cancel probe for %s mDNS ctx %p", "IPv6", ctx);
+
+		(void)k_work_cancel_delayable(&v6_ctx[i].probe_timer);
+	}
+#endif /* defined(CONFIG_NET_IPV6) */
+}
+
+static void probing(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct mdns_responder_context *ctx =
+		CONTAINER_OF(dwork, struct mdns_responder_context, probe_timer);
+	int ret;
+
+	if (failed_probes > 0) {
+		/* No point doing any new probe because one already failed */
+		NET_DBG("Probe already failed, not sending any more probes.");
+
+		(void)k_work_cancel_delayable(&init_listener_timer);
+		return;
+	}
+
+	ret = send_probe(ctx);
+	if (ret < 0) {
+		if (errno == EEXIST) {
+			/* Cancel the other possible probes */
+			cancel_probes(ctx);
+		}
+
+		NET_DBG("Cannot send %s mDNS probe (%d, errno %d)",
+			ctx->dispatcher.local_addr.sa_family == AF_INET ? "IPv4" :
+			(ctx->dispatcher.local_addr.sa_family == AF_INET6 ? "IPv6" :
+			 ""),
+			ret, errno);
+	}
+}
+
+static void mdns_addr_event_handler(struct net_mgmt_event_callback *cb,
+				    uint32_t mgmt_event, struct net_if *iface)
+{
+	uint32_t probe_delay = sys_rand32_get() % 250;
+	bool probe_started = false;
+	int ret;
+
+#if defined(CONFIG_NET_IPV4)
+	if (mgmt_event == NET_EVENT_IPV4_ADDR_ADD) {
+		ARRAY_FOR_EACH(v4_ctx, i) {
+			if (v4_ctx[i].iface != iface) {
+				continue;
+			}
+
+			ret = add_address(iface, AF_INET, cb->info, cb->info_length);
+			if (ret < 0 && ret != -EALREADY) {
+				NET_DBG("Cannot %s %s address (%d)", "add", "IPv4", ret);
+				return;
+			}
+
+			ret = k_work_reschedule_for_queue(&mdns_work_q,
+							  &v4_ctx[i].probe_timer,
+							  K_MSEC(probe_delay));
+			if (ret < 0) {
+				NET_DBG("Cannot schedule %s probe work (%d)", "IPv4", ret);
+			} else {
+				probe_started = true;
+
+				NET_DBG("%s %s probing scheduled for iface %d ctx %p",
+					"IPv4", "add", net_if_get_by_iface(iface),
+					&v4_ctx[i]);
+			}
+
+			break;
+		}
+
+		return;
+	}
+
+	if (mgmt_event == NET_EVENT_IPV4_ADDR_DEL) {
+		ARRAY_FOR_EACH(v4_ctx, i) {
+			if (v4_ctx[i].iface != iface) {
+				continue;
+			}
+
+			ret = del_address(iface, AF_INET, cb->info, cb->info_length);
+			if (ret < 0) {
+				if (ret == -ENOENT) {
+					continue;
+				}
+
+				NET_DBG("Cannot %s %s address (%d)", "del", "IPv4", ret);
+				return;
+			}
+
+			if (!net_if_is_up(iface)) {
+				continue;
+			}
+
+			ret = k_work_reschedule_for_queue(&mdns_work_q,
+							  &v4_ctx[i].probe_timer,
+							  K_MSEC(probe_delay));
+			if (ret < 0) {
+				NET_DBG("Cannot schedule %s probe work (%d)", "IPv4", ret);
+			} else {
+				probe_started = true;
+
+				NET_DBG("%s %s probing scheduled for iface %d ctx %p",
+					"IPv4", "del", net_if_get_by_iface(iface),
+					&v4_ctx[i]);
+			}
+
+			break;
+		}
+
+		return;
+	}
+#endif /* defined(CONFIG_NET_IPV4) */
+
+#if defined(CONFIG_NET_IPV6)
+	if (mgmt_event == NET_EVENT_IPV6_ADDR_ADD) {
+		ARRAY_FOR_EACH(v6_ctx, i) {
+			if (v6_ctx[i].iface != iface) {
+				continue;
+			}
+
+			ret = add_address(iface, AF_INET6, cb->info, cb->info_length);
+			if (ret < 0 && ret != -EALREADY) {
+				NET_DBG("Cannot %s %s address (%d)", "add", "IPv6", ret);
+				return;
+			}
+
+			ret = k_work_reschedule_for_queue(&mdns_work_q,
+							  &v6_ctx[i].probe_timer,
+							  K_MSEC(probe_delay));
+			if (ret < 0) {
+				NET_DBG("Cannot schedule %s probe work (%d)", "IPv6", ret);
+			} else {
+				probe_started = true;
+
+				NET_DBG("%s %s probing scheduled for iface %d ctx %p",
+					"IPv6", "add", net_if_get_by_iface(iface),
+					&v6_ctx[i]);
+			}
+
+			break;
+		}
+
+		return;
+	}
+
+	if (mgmt_event == NET_EVENT_IPV6_ADDR_DEL) {
+		ARRAY_FOR_EACH(v6_ctx, i) {
+			if (v6_ctx[i].iface != iface) {
+				continue;
+			}
+
+			ret = del_address(iface, AF_INET6, cb->info, cb->info_length);
+			if (ret < 0) {
+				if (ret == -ENOENT) {
+					continue;
+				}
+
+				NET_DBG("Cannot %s %s address (%d)", "del", "IPv6", ret);
+				return;
+			}
+
+			if (!net_if_is_up(iface)) {
+				continue;
+			}
+
+			ret = k_work_reschedule_for_queue(&mdns_work_q,
+							  &v4_ctx[i].probe_timer,
+							  K_MSEC(probe_delay));
+			if (ret < 0) {
+				NET_DBG("Cannot schedule %s probe work (%d)", "IPv6", ret);
+			} else {
+				probe_started = true;
+
+				NET_DBG("%s %s probing scheduled for iface %d ctx %p",
+					"IPv6", "del", net_if_get_by_iface(iface),
+					&v6_ctx[i]);
+			}
+
+			break;
+		}
+
+		return;
+	}
+#endif /* defined(CONFIG_NET_IPV6) */
+}
+
+static void mdns_conn_event_handler(struct net_mgmt_event_callback *cb,
+				    uint32_t mgmt_event, struct net_if *iface)
+{
+	if (mgmt_event == NET_EVENT_L4_DISCONNECTED) {
+		/* Clear the failed probes counter so that we can start
+		 * probing again.
+		 */
+		failed_probes = 0;
+	}
+}
+#endif /* CONFIG_MDNS_RESPONDER_PROBE */
+
 #if defined(CONFIG_NET_IPV6)
 static void iface_ipv6_cb(struct net_if *iface, void *user_data)
 {
@@ -666,14 +1184,12 @@ static void setup_ipv4_addr(struct sockaddr_in *local_addr)
 #define INTERFACE_NAME_LEN 0
 #endif
 
-static int dispatcher_cb(void *my_ctx, int sock,
+static int dispatcher_cb(struct dns_socket_dispatcher *ctx, int sock,
 			 struct sockaddr *addr, size_t addrlen,
 			 struct net_buf *dns_data, size_t len)
 {
 	int ret;
 
-	ARG_UNUSED(my_ctx);
-
 	ret = dns_read(sock, dns_data, len, addr, addrlen);
 	if (ret < 0 && ret != -EINVAL && ret != -ENOENT) {
 		NET_DBG("%s read failed (%d)", "mDNS", ret);
@@ -719,6 +1235,73 @@ static int register_dispatcher(struct mdns_responder_context *ctx,
 	return dns_dispatcher_register(&ctx->dispatcher);
 }
 
+#if defined(CONFIG_MDNS_RESPONDER_PROBE)
+/* Initialize things so that we can do probing before staring the listener */
+static int pre_init_listener(void)
+{
+	int ok = 0;
+	struct net_if *iface;
+	int iface_count;
+
+	NET_IFACE_COUNT(&iface_count);
+	NET_DBG("Pre-init %s for %d interface%s", "mDNS", iface_count,
+		iface_count > 1 ? "s" : "");
+
+#if defined(CONFIG_NET_IPV6)
+	if ((iface_count > MAX_IPV6_IFACE_COUNT && MAX_IPV6_IFACE_COUNT > 0)) {
+		NET_WARN("You have %d %s interfaces configured but there "
+			 "are %d network interfaces in the system.",
+			 MAX_IPV6_IFACE_COUNT, "IPv6", iface_count);
+	}
+
+	ARRAY_FOR_EACH(v6_ctx, i) {
+		iface = net_if_get_by_index(i + 1);
+		if (iface == NULL) {
+			continue;
+		}
+
+		v6_ctx[i].iface = iface;
+		v6_ctx[i].dispatcher.local_addr.sa_family = AF_INET6;
+		v6_ctx[i].dispatcher.svc = &v6_svc;
+
+		k_work_init_delayable(&v6_ctx[i].probe_timer, probing);
+
+		ok++;
+	}
+#endif /* CONFIG_NET_IPV6 */
+
+#if defined(CONFIG_NET_IPV4)
+	if ((iface_count > MAX_IPV4_IFACE_COUNT && MAX_IPV4_IFACE_COUNT > 0)) {
+		NET_WARN("You have %d %s interfaces configured but there "
+			 "are %d network interfaces in the system.",
+			 MAX_IPV4_IFACE_COUNT, "IPv4", iface_count);
+	}
+
+	ARRAY_FOR_EACH(v4_ctx, i) {
+		iface = net_if_get_by_index(i + 1);
+		if (iface == NULL) {
+			continue;
+		}
+
+		v4_ctx[i].iface = iface;
+		v4_ctx[i].dispatcher.local_addr.sa_family = AF_INET;
+		v4_ctx[i].dispatcher.svc = &v4_svc;
+
+		k_work_init_delayable(&v4_ctx[i].probe_timer, probing);
+
+		ok++;
+	}
+#endif /* CONFIG_NET_IPV4 */
+
+	if (ok == 0) {
+		NET_WARN("Cannot pre-init %s responder", "mDNS");
+		return -ENOENT;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_MDNS_RESPONDER_PROBE */
+
 static int init_listener(void)
 {
 	int ret, ok = 0, ifindex;
@@ -760,9 +1343,9 @@ static int init_listener(void)
 
 		v6 = get_socket(AF_INET6);
 		if (v6 < 0) {
-			NET_ERR("Cannot get %s socket (%d %s interfaces). Max sockets is %d",
+			NET_ERR("Cannot get %s socket (%d %s interfaces). Max sockets is %d (%d)",
 				"IPv6", MAX_IPV6_IFACE_COUNT,
-				"IPv6", CONFIG_NET_MAX_CONTEXTS);
+				"IPv6", CONFIG_NET_MAX_CONTEXTS, v6);
 			continue;
 		}
 
@@ -780,13 +1363,17 @@ static int init_listener(void)
 				ifindex, ret);
 		} else {
 			memset(&if_req, 0, sizeof(if_req));
-			strncpy(if_req.ifr_name, name, sizeof(if_req.ifr_name) - 1);
+			memcpy(if_req.ifr_name, name,
+			       MIN(sizeof(name) - 1, sizeof(if_req.ifr_name) - 1));
 
 			ret = zsock_setsockopt(v6, SOL_SOCKET, SO_BINDTODEVICE,
 					       &if_req, sizeof(if_req));
 			if (ret < 0) {
 				NET_DBG("Cannot bind sock %d to interface %d (%d)",
 					v6, ifindex, ret);
+			} else {
+				NET_DBG("Bound %s sock %d to interface %d",
+					"IPv6", v6, ifindex);
 			}
 		}
 
@@ -817,7 +1404,7 @@ static int init_listener(void)
 
 		ret = register_dispatcher(&v6_ctx[i], &v6_svc, (struct sockaddr *)&local_addr6,
 					  ifindex, ipv6_fds, ARRAY_SIZE(ipv6_fds));
-		if (ret < 0) {
+		if (ret < 0 && ret != -EALREADY) {
 			NET_DBG("Cannot register %s %s socket service (%d)",
 				"IPv6", "mDNS", ret);
 			zsock_close(v6);
@@ -853,9 +1440,9 @@ static int init_listener(void)
 
 		v4 = get_socket(AF_INET);
 		if (v4 < 0) {
-			NET_ERR("Cannot get %s socket (%d %s interfaces). Max sockets is %d",
+			NET_ERR("Cannot get %s socket (%d %s interfaces). Max sockets is %d (%d)",
 				"IPv4", MAX_IPV4_IFACE_COUNT,
-				"IPv4", CONFIG_NET_MAX_CONTEXTS);
+				"IPv4", CONFIG_NET_MAX_CONTEXTS, v4);
 			continue;
 		}
 
@@ -873,13 +1460,17 @@ static int init_listener(void)
 				ifindex, ret);
 		} else {
 			memset(&if_req, 0, sizeof(if_req));
-			strncpy(if_req.ifr_name, name, sizeof(if_req.ifr_name) - 1);
+			memcpy(if_req.ifr_name, name,
+			       MIN(sizeof(name) - 1, sizeof(if_req.ifr_name) - 1));
 
 			ret = zsock_setsockopt(v4, SOL_SOCKET, SO_BINDTODEVICE,
 					       &if_req, sizeof(if_req));
 			if (ret < 0) {
 				NET_DBG("Cannot bind sock %d to interface %d (%d)",
 					v4, ifindex, ret);
+			} else {
+				NET_DBG("Bound %s sock %d to interface %d",
+					"IPv4", v4, ifindex);
 			}
 		}
 
@@ -910,7 +1501,7 @@ static int init_listener(void)
 
 		ret = register_dispatcher(&v4_ctx[i], &v4_svc, (struct sockaddr *)&local_addr4,
 					  ifindex, ipv4_fds, ARRAY_SIZE(ipv4_fds));
-		if (ret < 0) {
+		if (ret < 0 && ret != -EALREADY) {
 			NET_DBG("Cannot register %s %s socket service (%d)",
 				"IPv4", "mDNS", ret);
 			zsock_close(v4);
@@ -920,24 +1511,369 @@ static int init_listener(void)
 	}
 #endif /* CONFIG_NET_IPV4 */
 
-	if (!ok) {
+	if (ok == 0) {
 		NET_WARN("Cannot start %s responder", "mDNS");
+		return -ENOENT;
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_MDNS_RESPONDER_PROBE)
+
+#define ANNOUNCE_TIMEOUT 1 /* in seconds, RFC 6762 ch 8.3 */
+
+/* ATM we do only .local announcing, SD announcing is TODO */
+
+static int send_unsolicited_response(struct net_if *iface,
+				     int sock,
+				     sa_family_t family,
+				     struct sockaddr *src_addr,
+				     size_t addrlen,
+				     struct net_buf *answer)
+{
+	socklen_t dst_len;
+	int ret;
+
+	COND_CODE_1(IS_ENABLED(CONFIG_NET_IPV6),
+		    (struct sockaddr_in6), (struct sockaddr_in)) dst;
+
+	ret = setup_dst_addr(sock, family, NULL, 0, (struct sockaddr *)&dst, &dst_len);
+	if (ret < 0) {
+		NET_DBG("unable to set up the response address");
+		return ret;
+	}
+
+	ret = zsock_sendto(sock, answer->data, answer->len, 0,
+			   (struct sockaddr *)&dst, dst_len);
+	if (ret < 0) {
+		ret = -errno;
+	} else {
+		net_stats_update_dns_sent(iface);
+	}
+
+	return ret;
+}
+
+static struct net_buf *create_unsolicited_mdns_answer(struct net_if *iface,
+						      const char *name,
+						      uint32_t ttl,
+						      struct mdns_monitor_iface_addr *addr_list,
+						      size_t addr_list_len)
+{
+	struct net_buf *answer;
+	uint16_t answer_count;
+	int len;
+
+	answer = net_buf_alloc(&mdns_msg_pool, BUF_ALLOC_TIMEOUT);
+	if (answer == NULL) {
+		return NULL;
+	}
+
+	setup_dns_hdr(answer->data, 1);
+	net_buf_add(answer, DNS_MSG_HEADER_SIZE);
+
+	answer_count = 0U;
+
+	for (size_t i = 0; i < addr_list_len; i++) {
+		uint16_t type;
+		size_t left;
+
+		if (!addr_list[i].in_use) {
+			continue;
+		}
+
+		if (iface != addr_list[i].iface) {
+			continue;
+		}
+
+		if (addr_list[i].addr.family == AF_INET) {
+			type = DNS_RR_TYPE_A;
+		} else if (addr_list[i].addr.family == AF_INET6) {
+			type = DNS_RR_TYPE_AAAA;
+		} else {
+			NET_DBG("Unknown family %d", addr_list[i].addr.family);
+
+			net_buf_unref(answer);
+			return NULL;
+		}
+
+		if (answer_count == 0) {
+			len = strlen(name);
+		}
+
+		left = net_buf_tailroom(answer);
+		if ((answer_count == 0 &&
+		     left < (1 + len + 1 + 5 + 1 + 2 + 2 + 4 + 4 +
+			     (type == DNS_RR_TYPE_A ? sizeof(struct in_addr) :
+			      sizeof(struct in6_addr)))) ||
+		    (answer_count > 0 &&
+		     left < (1 + 1 + 2 + 2 + 4 + 4 +
+			     (type == DNS_RR_TYPE_A ? sizeof(struct in_addr) :
+			      sizeof(struct in6_addr))))) {
+			NET_DBG("No more space (%u left)", left);
+			net_buf_unref(answer);
+			return NULL;
+		}
+
+		if (answer_count == 0) {
+			net_buf_add_u8(answer, len);
+			net_buf_add_mem(answer, name, len);
+			net_buf_add_u8(answer, sizeof(".local") - 2);
+			net_buf_add_mem(answer, &".local"[1], sizeof(".local") - 2);
+			net_buf_add_u8(answer, 0U);
+		} else {
+			/* Add pointer to the name (compression) */
+			net_buf_add_u8(answer, 0xc0);
+			net_buf_add_u8(answer, 0x0c);
+		}
+
+		net_buf_add_be16(answer, type);
+		net_buf_add_be16(answer, DNS_CLASS_IN);
+		net_buf_add_be32(answer, ttl);
+
+		if (type == DNS_RR_TYPE_A) {
+			net_buf_add_be16(answer, sizeof(struct in_addr));
+			net_buf_add_mem(answer, &addr_list[i].addr.in_addr,
+					sizeof(struct in_addr));
+		} else if (type == DNS_RR_TYPE_AAAA) {
+			net_buf_add_be16(answer, sizeof(struct in6_addr));
+			net_buf_add_mem(answer, &addr_list[i].addr.in6_addr,
+				sizeof(struct in6_addr));
+		}
+
+		answer_count++;
+	}
+
+	/* Adjust the answer count in the header */
+	if (answer_count > 1) {
+		UNALIGNED_PUT(htons(answer_count), (uint16_t *)&answer->data[6]);
+	}
+
+	return answer;
+}
+
+static bool check_if_needs_announce(struct net_if *iface)
+{
+	ARRAY_FOR_EACH(mon_if, i) {
+		if (!mon_if[i].in_use) {
+			continue;
+		}
+
+		if (mon_if[i].iface != iface) {
+			continue;
+		}
+
+		if (mon_if[i].needs_announce) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
+static int send_announce(const char *name)
+{
+	struct net_buf *answer;
+	int ret;
+
+#if defined(CONFIG_NET_IPV4)
+	struct sockaddr_in dst_addr4;
+
+	create_ipv4_addr(&dst_addr4);
+
+	ARRAY_FOR_EACH(v4_ctx, i) {
+		if (v4_ctx[i].sock < 0 || v4_ctx[i].iface == NULL ||
+		    !net_if_is_up(v4_ctx[i].iface)) {
+			continue;
+		}
+
+		if (!check_if_needs_announce(v4_ctx[i].iface)) {
+			continue;
+		}
+
+		answer = create_unsolicited_mdns_answer(v4_ctx[i].iface,
+							name,
+							MDNS_TTL,
+							mon_if,
+							ARRAY_SIZE(mon_if));
+		if (answer == NULL) {
+			continue;
+		}
+
+		ret = send_unsolicited_response(v4_ctx[i].iface,
+						v4_ctx[i].sock,
+						AF_INET,
+						(struct sockaddr *)&dst_addr4,
+						sizeof(dst_addr4),
+						answer);
+
+		net_buf_unref(answer);
+
+		if (ret < 0) {
+			NET_DBG("Cannot send %s announce (%d)", "mDNS", ret);
+			continue;
+		}
+
+		NET_DBG("Announcing %s responder for %s%s (iface %d)",
+			"mDNS", name, ".local", net_if_get_by_iface(v4_ctx[i].iface));
+	}
+#endif /* defined(CONFIG_NET_IPV4) */
+
+#if defined(CONFIG_NET_IPV6)
+	struct sockaddr_in6 dst_addr6;
+
+	create_ipv6_addr(&dst_addr6);
+
+	ARRAY_FOR_EACH(v6_ctx, i) {
+		if (v6_ctx[i].sock < 0 || v6_ctx[i].iface == NULL ||
+		    !net_if_is_up(v6_ctx[i].iface)) {
+			continue;
+		}
+
+		if (!check_if_needs_announce(v6_ctx[i].iface)) {
+			continue;
+		}
+
+		answer = create_unsolicited_mdns_answer(v6_ctx[i].iface,
+							name,
+							MDNS_TTL,
+							mon_if,
+							ARRAY_SIZE(mon_if));
+		if (answer == NULL) {
+			continue;
+		}
+
+		ret = send_unsolicited_response(v6_ctx[i].iface,
+						v6_ctx[i].sock,
+						AF_INET6,
+						(struct sockaddr *)&dst_addr6,
+						sizeof(dst_addr6),
+						answer);
+
+		net_buf_unref(answer);
+
+		if (ret < 0) {
+			NET_DBG("Cannot send %s announce (%d)", "mDNS", ret);
+			continue;
+		}
+
+		NET_DBG("Announcing %s responder for %s%s (iface %d)",
+			"mDNS", name, ".local", net_if_get_by_iface(v6_ctx[i].iface));
+	}
+#endif /* defined(CONFIG_NET_IPV6) */
+
+	return 0;
+}
+
+static void announce_start(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	char name[DNS_MAX_NAME_SIZE + 1];
+	int ret;
+
+	snprintk(name, sizeof(name), "%s", net_hostname_get());
+
+	ret = send_announce(name);
+	if (ret < 0) {
+		NET_DBG("Cannot send %s announce (%d)", "mDNS", ret);
+		return;
 	}
 
-	return !ok;
+	do_announce = true;
+	announce_count++;
+
+	ret = k_work_reschedule_for_queue(&mdns_work_q, dwork, K_SECONDS(ANNOUNCE_TIMEOUT));
+	if (ret < 0) {
+		NET_DBG("Cannot schedule %s work (%d)", "announce", ret);
+	}
 }
 
+static void do_init_listener(struct k_work *work)
+{
+	int ret;
+
+	if (failed_probes) {
+		NET_DBG("Probing failed, will not init responder.");
+		return;
+	}
+
+	if (do_announce) {
+		if (announce_count < 1) {
+			announce_start(work);
+		} else {
+			mark_needs_announce(NULL, false);
+		}
+	} else {
+		NET_DBG("Probing done, starting %s responder", "mDNS");
+
+		ret = init_listener();
+		if (ret < 0) {
+			NET_ERR("Cannot start %s responder", "mDNS");
+		} else {
+			init_listener_done = true;
+		};
+
+		mark_needs_announce(NULL, true);
+		announce_count = 0;
+		announce_start(work);
+	}
+}
+#endif /* CONFIG_MDNS_RESPONDER_PROBE */
+
 static int mdns_responder_init(void)
 {
+	uint32_t flags = NET_EVENT_IF_UP;
 	external_records = NULL;
 	external_records_count = 0;
 
-	net_mgmt_init_event_callback(&mgmt_cb, mdns_iface_event_handler,
-				     NET_EVENT_IF_UP);
+	net_mgmt_init_event_callback(&mgmt_iface_cb, mdns_iface_event_handler, flags);
+	net_mgmt_add_event_callback(&mgmt_iface_cb);
+
+#if defined(CONFIG_MDNS_RESPONDER_PROBE)
+	int ret;
 
-	net_mgmt_add_event_callback(&mgmt_cb);
+	net_mgmt_init_event_callback(&mgmt_conn_cb, mdns_conn_event_handler,
+				     NET_EVENT_L4_DISCONNECTED);
+	net_mgmt_add_event_callback(&mgmt_conn_cb);
 
+#if defined(CONFIG_NET_IPV4)
+	net_mgmt_init_event_callback(&mgmt4_addr_cb, mdns_addr_event_handler,
+				     NET_EVENT_IPV4_ADDR_ADD |
+				     NET_EVENT_IPV4_ADDR_DEL);
+	net_mgmt_add_event_callback(&mgmt4_addr_cb);
+#endif
+
+#if defined(CONFIG_NET_IPV6)
+	net_mgmt_init_event_callback(&mgmt6_addr_cb, mdns_addr_event_handler,
+				     NET_EVENT_IPV6_ADDR_ADD |
+				     NET_EVENT_IPV6_ADDR_DEL);
+	net_mgmt_add_event_callback(&mgmt6_addr_cb);
+#endif
+
+#if defined(CONFIG_NET_TC_THREAD_COOPERATIVE)
+#define THREAD_PRIORITY K_PRIO_COOP(CONFIG_MDNS_WORKER_PRIO)
+#else
+#define THREAD_PRIORITY K_PRIO_PREEMPT(CONFIG_MDNS_WORKER_PRIO)
+#endif
+
+	ret = pre_init_listener();
+	if (ret < 0) {
+		NET_ERR("Cannot start %s workq", "mDNS");
+	} else {
+		k_work_queue_start(&mdns_work_q, mdns_work_q_stack,
+				   K_KERNEL_STACK_SIZEOF(mdns_work_q_stack),
+				   THREAD_PRIORITY, NULL);
+
+		k_thread_name_set(&mdns_work_q.thread, "mdns_work");
+	}
+
+	k_work_init_delayable(&init_listener_timer, do_init_listener);
+
+	return ret;
+#else
 	return init_listener();
+#endif
 }
 
 int mdns_responder_set_ext_records(const struct dns_sd_rec *records, size_t count)
diff --git a/subsys/net/lib/dns/resolve.c b/subsys/net/lib/dns/resolve.c
index e6b77661763..813b7cd8f6c 100644
--- a/subsys/net/lib/dns/resolve.c
+++ b/subsys/net/lib/dns/resolve.c
@@ -25,6 +25,8 @@ LOG_MODULE_REGISTER(net_dns_resolve, CONFIG_DNS_RESOLVER_LOG_LEVEL);
 #include <zephyr/net/net_ip.h>
 #include <zephyr/net/net_pkt.h>
 #include <zephyr/net/net_mgmt.h>
+#include <zephyr/net/igmp.h>
+#include <zephyr/net/mld.h>
 #include <zephyr/net/dns_resolve.h>
 #include <zephyr/net/socket_service.h>
 #include "../../ip/net_private.h"
@@ -148,6 +150,34 @@ static bool server_is_llmnr(sa_family_t family, struct sockaddr *addr)
 	return false;
 }
 
+static void join_ipv4_mcast_group(struct net_if *iface, void *user_data)
+{
+	struct sockaddr *addr = user_data;
+	int ret;
+
+	ret = net_ipv4_igmp_join(iface, &net_sin(addr)->sin_addr, NULL);
+	if (ret < 0 && ret != -EALREADY) {
+		NET_DBG("Cannot join %s mDNS group (%d)", "IPv4", ret);
+	} else {
+		NET_DBG("Joined %s mDNS group %s", "IPv4",
+			net_sprint_ipv4_addr(&net_sin(addr)->sin_addr));
+	}
+}
+
+static void join_ipv6_mcast_group(struct net_if *iface, void *user_data)
+{
+	struct sockaddr *addr = user_data;
+	int ret;
+
+	ret = net_ipv6_mld_join(iface, &net_sin6(addr)->sin6_addr);
+	if (ret < 0 && ret != -EALREADY) {
+		NET_DBG("Cannot join %s mDNS group (%d)", "IPv6", ret);
+	} else {
+		NET_DBG("Joined %s mDNS group %s", "IPv6",
+			net_sprint_ipv6_addr(&net_sin6(addr)->sin6_addr));
+	}
+}
+
 static void dns_postprocess_server(struct dns_resolve_context *ctx, int idx)
 {
 	struct sockaddr *addr = &ctx->servers[idx].dns_server;
@@ -180,6 +210,26 @@ static void dns_postprocess_server(struct dns_resolve_context *ctx, int idx)
 				net_sin(addr)->sin_port = htons(53);
 			}
 		}
+
+		/* Join the mDNS multicast group if responder is not enabled,
+		 * because it will join the group itself.
+		 */
+		if (!IS_ENABLED(CONFIG_MDNS_RESPONDER) && ctx->servers[idx].is_mdns) {
+			struct in_addr mcast_addr = { { { 224, 0, 0, 251 } } };
+
+			if (net_sin(addr)->sin_addr.s_addr == mcast_addr.s_addr) {
+				struct net_if *iface;
+
+				iface = net_if_get_by_index(ctx->servers[idx].if_index);
+				if (iface == NULL) {
+					/* Join all interfaces */
+					net_if_foreach(join_ipv4_mcast_group, addr);
+				} else {
+					/* Join specific interface */
+					join_ipv4_mcast_group(iface, addr);
+				}
+			}
+		}
 	} else {
 		ctx->servers[idx].is_mdns = server_is_mdns(AF_INET6, addr);
 		if (!ctx->servers[idx].is_mdns) {
@@ -198,14 +248,33 @@ static void dns_postprocess_server(struct dns_resolve_context *ctx, int idx)
 				net_sin6(addr)->sin6_port = htons(53);
 			}
 		}
+
+		if (!IS_ENABLED(CONFIG_MDNS_RESPONDER) && ctx->servers[idx].is_mdns) {
+			struct in6_addr mcast_addr = { { { 0xff, 0x02, 0, 0, 0, 0, 0, 0,
+						0, 0, 0, 0, 0, 0, 0, 0xfb } } };
+
+			if (memcmp(&net_sin6(addr)->sin6_addr, &mcast_addr,
+				   sizeof(struct in6_addr)) == 0) {
+				struct net_if *iface;
+
+				iface = net_if_get_by_index(ctx->servers[idx].if_index);
+				if (iface == NULL) {
+					/* Join all interfaces */
+					net_if_foreach(join_ipv6_mcast_group, addr);
+				} else {
+					/* Join specific interface */
+					join_ipv6_mcast_group(iface, addr);
+				}
+			}
+		}
 	}
 }
 
-static int dispatcher_cb(void *my_ctx, int sock,
+static int dispatcher_cb(struct dns_socket_dispatcher *my_ctx, int sock,
 			 struct sockaddr *addr, size_t addrlen,
 			 struct net_buf *dns_data, size_t len)
 {
-	struct dns_resolve_context *ctx = my_ctx;
+	struct dns_resolve_context *ctx = my_ctx->resolve_ctx;
 	struct net_buf *dns_cname = NULL;
 	uint16_t query_hash = 0U;
 	uint16_t dns_id = 0U;
@@ -348,18 +417,20 @@ static int bind_to_iface(int sock, const struct sockaddr *addr, int if_index)
 /* Must be invoked with context lock held */
 static int dns_resolve_init_locked(struct dns_resolve_context *ctx,
 				   const char *servers[],
-				   const struct sockaddr *servers_sa[])
+				   const struct sockaddr *servers_sa[],
+				   const struct net_socket_service_desc *svc,
+				   uint16_t port, int interfaces[])
 {
 #if defined(CONFIG_NET_IPV6)
 	struct sockaddr_in6 local_addr6 = {
 		.sin6_family = AF_INET6,
-		.sin6_port = 0,
+		.sin6_port = htons(port),
 	};
 #endif
 #if defined(CONFIG_NET_IPV4)
 	struct sockaddr_in local_addr4 = {
 		.sin_family = AF_INET,
-		.sin_port = 0,
+		.sin_port = htons(port),
 	};
 #endif
 	struct sockaddr *local_addr = NULL;
@@ -387,6 +458,12 @@ static int dns_resolve_init_locked(struct dns_resolve_context *ctx,
 		ctx->fds[j].fd = -1;
 	}
 
+	/* If user has provided a list of servers in string format, then
+	 * figure out the network interface from that list. If user used
+	 * list of sockaddr servers, then use the interfaces parameter.
+	 * The interfaces parameter should point to an array that is the
+	 * the same length as the servers_sa parameter array.
+	 */
 	if (servers) {
 		for (i = 0; idx < SERVER_COUNT && servers[i]; i++) {
 			const char *iface_str;
@@ -447,6 +524,11 @@ static int dns_resolve_init_locked(struct dns_resolve_context *ctx,
 		for (i = 0; idx < SERVER_COUNT && servers_sa[i]; i++) {
 			memcpy(&ctx->servers[idx].dns_server, servers_sa[i],
 			       sizeof(ctx->servers[idx].dns_server));
+
+			if (interfaces != NULL) {
+				ctx->servers[idx].if_index = interfaces[idx];
+			}
+
 			dns_postprocess_server(ctx, idx);
 			idx++;
 		}
@@ -461,7 +543,7 @@ static int dns_resolve_init_locked(struct dns_resolve_context *ctx,
 			addr_len = sizeof(struct sockaddr_in6);
 
 			if (IS_ENABLED(CONFIG_MDNS_RESOLVER) &&
-			    ctx->servers[i].is_mdns) {
+			    ctx->servers[i].is_mdns && port == 0) {
 				local_addr6.sin6_port = htons(5353);
 			}
 #else
@@ -475,7 +557,7 @@ static int dns_resolve_init_locked(struct dns_resolve_context *ctx,
 			addr_len = sizeof(struct sockaddr_in);
 
 			if (IS_ENABLED(CONFIG_MDNS_RESOLVER) &&
-			    ctx->servers[i].is_mdns) {
+			    ctx->servers[i].is_mdns && port == 0) {
 				local_addr4.sin_port = htons(5353);
 			}
 #else
@@ -558,8 +640,8 @@ static int dns_resolve_init_locked(struct dns_resolve_context *ctx,
 			continue;
 		}
 
-		ret = register_dispatcher(ctx, &resolve_svc, &ctx->servers[i], local_addr,
-						  addr6, addr4);
+		ret = register_dispatcher(ctx, svc, &ctx->servers[i], local_addr,
+					  addr6, addr4);
 		if (ret < 0) {
 			if (ret == -EALREADY) {
 				goto skip_event;
@@ -582,11 +664,11 @@ static int dns_resolve_init_locked(struct dns_resolve_context *ctx,
 skip_event:
 
 #if defined(CONFIG_NET_IPV6)
-		local_addr6.sin6_port = 0;
+		local_addr6.sin6_port = htons(port);
 #endif
 
 #if defined(CONFIG_NET_IPV4)
-		local_addr4.sin_port = 0;
+		local_addr4.sin_port = htons(port);
 #endif
 
 		count++;
@@ -608,8 +690,10 @@ static int dns_resolve_init_locked(struct dns_resolve_context *ctx,
 	return ret;
 }
 
-int dns_resolve_init(struct dns_resolve_context *ctx, const char *servers[],
-		     const struct sockaddr *servers_sa[])
+int dns_resolve_init_with_svc(struct dns_resolve_context *ctx, const char *servers[],
+			      const struct sockaddr *servers_sa[],
+			      const struct net_socket_service_desc *svc,
+			      uint16_t port, int interfaces[])
 {
 	if (!ctx) {
 		return -ENOENT;
@@ -623,7 +707,15 @@ int dns_resolve_init(struct dns_resolve_context *ctx, const char *servers[],
 	/* As this function is called only once during system init, there is no
 	 * reason to acquire lock.
 	 */
-	return dns_resolve_init_locked(ctx, servers, servers_sa);
+	return dns_resolve_init_locked(ctx, servers, servers_sa, svc, port,
+				       interfaces);
+}
+
+int dns_resolve_init(struct dns_resolve_context *ctx, const char *servers[],
+		     const struct sockaddr *servers_sa[])
+{
+	return dns_resolve_init_with_svc(ctx, servers, servers_sa,
+					 &resolve_svc, 0, NULL);
 }
 
 /* Check whether a slot is available for use, or optionally whether it can be
@@ -782,7 +874,8 @@ int dns_validate_msg(struct dns_resolve_context *ctx,
 
 	ret = dns_unpack_response_header(dns_msg, *dns_id);
 	if (ret < 0) {
-		ret = DNS_EAI_FAIL;
+		errno = -ret;
+		ret = DNS_EAI_SYSTEM;
 		goto quit;
 	}
 
@@ -797,7 +890,8 @@ int dns_validate_msg(struct dns_resolve_context *ctx,
 	ret = dns_unpack_response_query(dns_msg);
 	if (ret < 0) {
 		if (ret == -ENOMEM) {
-			ret = DNS_EAI_FAIL;
+			errno = -ret;
+			ret = DNS_EAI_SYSTEM;
 			goto quit;
 		}
 
@@ -806,7 +900,9 @@ int dns_validate_msg(struct dns_resolve_context *ctx,
 			ret = DNS_EAI_FAIL;
 			goto quit;
 		}
+	}
 
+	if (dns_header_qdcount(dns_msg->msg) < 1 && *dns_id == 0) {
 		/* mDNS responses to do not have the query part so the
 		 * answer starts immediately after the header.
 		 */
@@ -828,33 +924,64 @@ int dns_validate_msg(struct dns_resolve_context *ctx,
 		ret = dns_unpack_answer(dns_msg, answer_ptr, &ttl,
 					&answer_type);
 		if (ret < 0) {
-			ret = DNS_EAI_FAIL;
+			errno = -ret;
+			ret = DNS_EAI_SYSTEM;
 			goto quit;
 		}
 
 		switch (dns_msg->response_type) {
-		case DNS_RESPONSE_IP:
+		case DNS_RESPONSE_IP: {
+			int query_name_len;
+
 			if (*query_idx >= 0) {
 				goto query_known;
 			}
 
 			query_name = dns_msg->msg + dns_msg->query_offset;
 
+			query_name_len = strlen(query_name);
+
 			/* Convert the query name to small case so that our
 			 * hash checker can find it.
 			 */
-			for (size_t i = 0, n = strlen(query_name); i < n; i++) {
+			for (size_t i = 0, n = query_name_len; i < n; i++) {
 				query_name[i] = tolower(query_name[i]);
 			}
 
 			/* Add \0 and query type (A or AAAA) to the hash */
 			*query_hash = crc16_ansi(query_name,
-						 strlen(query_name) + 1 + 2);
+						 query_name_len + 1 + 2);
 
 			*query_idx = get_slot_by_id(ctx, *dns_id, *query_hash);
 			if (*query_idx < 0) {
-				ret = DNS_EAI_SYSTEM;
-				goto quit;
+				/* Re-check if this was a mDNS probe query */
+				if (IS_ENABLED(CONFIG_MDNS_RESPONDER_PROBE) && *dns_id == 0) {
+					uint16_t orig_qtype;
+
+					orig_qtype = sys_get_be16(&query_name[query_name_len + 1]);
+
+					/* Replace the query type with ANY as that was used
+					 * when creating the hash.
+					 */
+					sys_put_be16(DNS_RR_TYPE_ANY,
+						     &query_name[query_name_len + 1]);
+
+					*query_hash = crc16_ansi(query_name,
+								 query_name_len + 1 + 2);
+
+					sys_put_be16(orig_qtype, &query_name[query_name_len + 1]);
+
+					*query_idx = get_slot_by_id(ctx, *dns_id, *query_hash);
+					if (*query_idx < 0) {
+						errno = ENOENT;
+						ret = DNS_EAI_SYSTEM;
+						goto quit;
+					}
+				} else {
+					errno = ENOENT;
+					ret = DNS_EAI_SYSTEM;
+					goto quit;
+				}
 			}
 
 query_known:
@@ -865,6 +992,7 @@ int dns_validate_msg(struct dns_resolve_context *ctx,
 					goto quit;
 				}
 
+rr_qtype_a:
 				address_size = DNS_IPV4_LEN;
 				addr = (uint8_t *)&net_sin(&info.ai_addr)->
 								sin_addr;
@@ -879,6 +1007,7 @@ int dns_validate_msg(struct dns_resolve_context *ctx,
 					goto quit;
 				}
 
+rr_qtype_aaaa:
 				/* We cannot resolve IPv6 address if IPv6 is
 				 * disabled. The reason being that
 				 * "struct sockaddr" does not have enough space
@@ -895,6 +1024,20 @@ int dns_validate_msg(struct dns_resolve_context *ctx,
 				ret = DNS_EAI_FAMILY;
 				goto quit;
 #endif
+			} else if (ctx->queries[*query_idx].query_type ==
+				   (enum dns_query_type)DNS_RR_TYPE_ANY) {
+				/* If we did ANY query, we need to check what
+				 * type of answer we got. Currently only A or AAAA
+				 * are supported.
+				 */
+				if (answer_type == DNS_RR_TYPE_A) {
+					goto rr_qtype_a;
+				} else if (answer_type == DNS_RR_TYPE_AAAA) {
+					goto rr_qtype_aaaa;
+				} else {
+					ret = DNS_EAI_ADDRFAMILY;
+					goto quit;
+				}
 			} else {
 				ret = DNS_EAI_FAMILY;
 				goto quit;
@@ -902,14 +1045,16 @@ int dns_validate_msg(struct dns_resolve_context *ctx,
 
 			if (dns_msg->response_length < address_size) {
 				/* it seems this is a malformed message */
-				ret = DNS_EAI_FAIL;
+				errno = EMSGSIZE;
+				ret = DNS_EAI_SYSTEM;
 				goto quit;
 			}
 
 			if ((dns_msg->response_position + address_size) >
 			    dns_msg->msg_size) {
 				/* Too short message */
-				ret = DNS_EAI_FAIL;
+				errno = EMSGSIZE;
+				ret = DNS_EAI_SYSTEM;
 				goto quit;
 			}
 
@@ -924,7 +1069,7 @@ int dns_validate_msg(struct dns_resolve_context *ctx,
 #endif /* CONFIG_DNS_RESOLVER_CACHE */
 			items++;
 			break;
-
+		}
 		case DNS_RESPONSE_CNAME_NO_IP:
 			/* Instead of using the QNAME at DNS_QUERY_POS,
 			 * we will use this CNAME
@@ -955,6 +1100,7 @@ int dns_validate_msg(struct dns_resolve_context *ctx,
 
 		*query_idx = get_slot_by_id(ctx, *dns_id, *query_hash);
 		if (*query_idx < 0) {
+			errno = ENOENT;
 			ret = DNS_EAI_SYSTEM;
 			goto quit;
 		}
@@ -977,6 +1123,7 @@ int dns_validate_msg(struct dns_resolve_context *ctx,
 						     net_buf_max_len(dns_cname),
 						     dns_msg, pos);
 				if (ret < 0) {
+					errno = -ret;
 					ret = DNS_EAI_SYSTEM;
 					goto quit;
 				}
@@ -1333,13 +1480,14 @@ static void query_timeout(struct k_work *work)
 	k_mutex_unlock(&pending_query->ctx->lock);
 }
 
-int dns_resolve_name(struct dns_resolve_context *ctx,
-		     const char *query,
-		     enum dns_query_type type,
-		     uint16_t *dns_id,
-		     dns_resolve_cb_t cb,
-		     void *user_data,
-		     int32_t timeout)
+int dns_resolve_name_internal(struct dns_resolve_context *ctx,
+			      const char *query,
+			      enum dns_query_type type,
+			      uint16_t *dns_id,
+			      dns_resolve_cb_t cb,
+			      void *user_data,
+			      int32_t timeout,
+			      bool use_cache)
 {
 	k_timeout_t tout;
 	struct net_buf *dns_data = NULL;
@@ -1414,18 +1562,24 @@ int dns_resolve_name(struct dns_resolve_context *ctx,
 
 try_resolve:
 #ifdef CONFIG_DNS_RESOLVER_CACHE
-	ret = dns_cache_find(&dns_cache, query, cached_info, ARRAY_SIZE(cached_info));
-	if (ret > 0) {
-		/* The query was cached, no
-		 * need to continue further.
-		 */
-		for (size_t cache_index = 0; cache_index < ret; cache_index++) {
-			cb(DNS_EAI_INPROGRESS, &cached_info[cache_index], user_data);
-		}
-		cb(DNS_EAI_ALLDONE, NULL, user_data);
+	if (use_cache) {
+		ret = dns_cache_find(&dns_cache, query, type, cached_info,
+				     ARRAY_SIZE(cached_info));
+		if (ret > 0) {
+			/* The query was cached, no
+			 * need to continue further.
+			 */
+			for (size_t cache_index = 0; cache_index < ret; cache_index++) {
+				cb(DNS_EAI_INPROGRESS, &cached_info[cache_index], user_data);
+			}
 
-		return 0;
+			cb(DNS_EAI_ALLDONE, NULL, user_data);
+
+			return 0;
+		}
 	}
+#else
+	ARG_UNUSED(use_cache);
 #endif /* CONFIG_DNS_RESOLVER_CACHE */
 
 	k_mutex_lock(&ctx->lock, K_FOREVER);
@@ -1573,6 +1727,18 @@ int dns_resolve_name(struct dns_resolve_context *ctx,
 	return ret;
 }
 
+int dns_resolve_name(struct dns_resolve_context *ctx,
+		     const char *query,
+		     enum dns_query_type type,
+		     uint16_t *dns_id,
+		     dns_resolve_cb_t cb,
+		     void *user_data,
+		     int32_t timeout)
+{
+	return dns_resolve_name_internal(ctx, query, type, dns_id, cb,
+					 user_data, timeout, true);
+}
+
 /* Must be invoked with context lock held */
 static int dns_resolve_close_locked(struct dns_resolve_context *ctx)
 {
@@ -1743,7 +1909,7 @@ int dns_resolve_reconfigure(struct dns_resolve_context *ctx,
 		}
 	}
 
-	err = dns_resolve_init_locked(ctx, servers, servers_sa);
+	err = dns_resolve_init_locked(ctx, servers, servers_sa, &resolve_svc, 0, NULL);
 
 unlock:
 	k_mutex_unlock(&ctx->lock);
diff --git a/subsys/net/lib/http/CMakeLists.txt b/subsys/net/lib/http/CMakeLists.txt
index f049b42d103..0d8382ea8b1 100644
--- a/subsys/net/lib/http/CMakeLists.txt
+++ b/subsys/net/lib/http/CMakeLists.txt
@@ -16,6 +16,7 @@ zephyr_library_sources_ifdef(CONFIG_HTTP_SERVER http_server_core.c
 						http_server_http2.c
 						http_hpack.c
 						http_huffman.c)
+zephyr_library_sources_ifdef(CONFIG_HTTP_SERVER_COMPRESSION http_compression.c)
 if(CONFIG_HTTP_SERVER AND CONFIG_WEBSOCKET)
   zephyr_library_sources(http_server_ws.c)
   zephyr_library_link_libraries_ifdef(CONFIG_MBEDTLS mbedTLS)
diff --git a/subsys/net/lib/http/Kconfig b/subsys/net/lib/http/Kconfig
index 2cce0f5c45b..a83bb722fe6 100644
--- a/subsys/net/lib/http/Kconfig
+++ b/subsys/net/lib/http/Kconfig
@@ -29,7 +29,7 @@ config HTTP_CLIENT
 	help
 	  HTTP client API
 
-config HTTP_SERVER
+menuconfig HTTP_SERVER
 	bool "HTTP Server [EXPERIMENTAL]"
 	select HTTP_PARSER
 	select HTTP_PARSER_URL
@@ -163,7 +163,8 @@ config HTTP_SERVER_WEBSOCKET
 
 config HTTP_SERVER_RESOURCE_WILDCARD
 	bool "Allow wildcard matching of resources"
-	select FNMATCH
+	# The POSIX_C_LIB_EXT will get fnmatch() support
+	select POSIX_C_LIB_EXT
 	help
 	  Allow user to specify wildcards when setting up resource strings.
 	  This means that instead of specifying multiple resources with exact
@@ -188,12 +189,34 @@ config HTTP_SERVER_TLS_USE_ALPN
 	  protocol for TLS connections. Web browsers use this mechanism to determine
 	  whether HTTP2 is supported.
 
+config HTTP_SERVER_REPORT_FAILURE_REASON
+	bool "Report failure reason in HTTP 500 Internal Server Error reply"
+	help
+	  If enabled, the server will include the failure reason within
+	  HTTP 500 Internal Server Error response. Otherwise, no information
+	  is provided within the message.
+
 config WEBSOCKET_CONSOLE
 	bool
 	default y if HTTP_SERVER_WEBSOCKET && SHELL_BACKEND_WEBSOCKET
 	help
 	  Hidden option that is enabled only when all the necessary options
 	  needed by websocket console are set.
+
+config HTTP_SERVER_COMPRESSION
+	bool "Compression support in HTTP fileserver"
+	help
+	  If enabled, the fileserver will parse the accept-encoding header
+	  from the client and extract the supported compression methods.
+	  Afterwards it will try to serve the first compressed file available
+	  by using the file ending as compression indicator in this order:
+	    1. brotli   -> .br
+	    2. gzip     -> .gz
+	    3. zstd     -> .zst
+	    4. compress -> .lzw
+	    5. deflate  -> .zz
+	    6. File without compression
+
 endif
 
 # Hidden option to avoid having multiple individual options that are ORed together
diff --git a/subsys/net/lib/http/headers/server_internal.h b/subsys/net/lib/http/headers/server_internal.h
index 5048a8543fb..1cbd04b0d38 100644
--- a/subsys/net/lib/http/headers/server_internal.h
+++ b/subsys/net/lib/http/headers/server_internal.h
@@ -36,19 +36,28 @@ int enter_http1_request(struct http_client_ctx *client);
 int enter_http2_request(struct http_client_ctx *client);
 int enter_http_done_state(struct http_client_ctx *client);
 
+/* HTTP Compression handling */
+#define HTTP_COMPRESSION_MAX_STRING_LEN 8
+void http_compression_parse_accept_encoding(const char *accept_encoding, size_t len,
+					    uint8_t *supported_compression);
+const char *http_compression_text(enum http_compression compression);
+int http_compression_from_text(enum http_compression *compression, const char *text);
+bool compression_value_is_valid(enum http_compression compression);
+
 /* Others */
-struct http_resource_detail *get_resource_detail(const char *path, int *len, bool is_ws);
+struct http_resource_detail *get_resource_detail(const struct http_service_desc *service,
+						 const char *path, int *len, bool is_ws);
 int http_server_sendall(struct http_client_ctx *client, const void *buf, size_t len);
 void http_server_get_content_type_from_extension(char *url, char *content_type,
 						 size_t content_type_size);
-int http_server_find_file(char *fname, size_t fname_size, size_t *file_size, bool *gzipped);
+int http_server_find_file(char *fname, size_t fname_size, size_t *file_size,
+			  uint8_t supported_compression, enum http_compression *chosen_compression);
 void http_client_timer_restart(struct http_client_ctx *client);
 bool http_response_is_final(struct http_response_ctx *rsp, enum http_data_status status);
 bool http_response_is_provided(struct http_response_ctx *rsp);
 
 /* TODO Could be static, but currently used in tests. */
-int parse_http_frame_header(struct http_client_ctx *client, const uint8_t *buffer,
-			    size_t buflen);
+int parse_http_frame_header(struct http_client_ctx *client, const uint8_t *buffer, size_t buflen);
 const char *get_frame_type_name(enum http2_frame_type type);
 
 void populate_request_ctx(struct http_request_ctx *req_ctx, uint8_t *data, size_t len,
diff --git a/subsys/net/lib/http/http_client.c b/subsys/net/lib/http/http_client.c
index 51cab197a7a..c95e970ea1e 100644
--- a/subsys/net/lib/http/http_client.c
+++ b/subsys/net/lib/http/http_client.c
@@ -23,6 +23,7 @@ LOG_MODULE_REGISTER(net_http_client, CONFIG_NET_HTTP_LOG_LEVEL);
 #include <zephyr/net/net_ip.h>
 #include <zephyr/net/socket.h>
 #include <zephyr/net/http/client.h>
+#include <zephyr/net/http/status.h>
 
 #include "net_private.h"
 
@@ -217,12 +218,17 @@ static int on_header_field(struct http_parser *parser, const char *at,
 	struct http_request *req = CONTAINER_OF(parser,
 						struct http_request,
 						internal.parser);
-	const char *content_len = "Content-Length";
-	uint16_t len;
+	static const char content_len[] = "Content-Length";
+	static const char content_range[] = "Content-Range";
+
+	uint16_t content_len_len = sizeof(content_len) - 1;
+	uint16_t content_range_len = sizeof(content_range) - 1;
 
-	len = strlen(content_len);
-	if (length >= len && strncasecmp(at, content_len, len) == 0) {
+	if (length >= content_len_len && strncasecmp(at, content_len, content_len_len) == 0) {
 		req->internal.response.cl_present = true;
+	} else if (length >= content_range_len &&
+		   strncasecmp(at, content_range, content_range_len) == 0) {
+		req->internal.response.cr_present = true;
 	}
 
 	print_header_field(length, at);
@@ -264,6 +270,13 @@ static int on_header_value(struct http_parser *parser, const char *at,
 		req->internal.response.cl_present = false;
 	}
 
+	if (req->internal.response.cr_present) {
+		req->internal.response.content_range.start = parser->content_range.start;
+		req->internal.response.content_range.end = parser->content_range.end;
+		req->internal.response.content_range.total = parser->content_range.total;
+		req->internal.response.cr_present = false;
+	}
+
 	if (req->internal.response.http_cb &&
 	    req->internal.response.http_cb->on_header_value) {
 		req->internal.response.http_cb->on_header_value(parser, at,
@@ -315,6 +328,11 @@ static int on_headers_complete(struct http_parser *parser)
 		req->internal.response.http_cb->on_headers_complete(parser);
 	}
 
+	if (parser->status_code == HTTP_101_SWITCHING_PROTOCOLS) {
+		NET_DBG("Switching protocols, skipping body");
+		return 1;
+	}
+
 	if (parser->status_code >= 500 && parser->status_code < 600) {
 		NET_DBG("Status %d, skipping body", parser->status_code);
 		return 1;
@@ -484,8 +502,16 @@ static int http_wait_data(int sock, struct http_request *req, const k_timepoint_
 			ret = -errno;
 			goto error;
 		}
-		if (fds[0].revents & (ZSOCK_POLLERR | ZSOCK_POLLNVAL)) {
-			ret = -errno;
+
+		if (fds[0].revents & ZSOCK_POLLERR) {
+			int sock_err;
+			socklen_t optlen = sizeof(sock_err);
+
+			(void)zsock_getsockopt(sock, SOL_SOCKET, SO_ERROR, &sock_err, &optlen);
+			ret = -sock_err;
+			goto error;
+		} else if (fds[0].revents & ZSOCK_POLLNVAL) {
+			ret = -EBADF;
 			goto error;
 		} else if (fds[0].revents & ZSOCK_POLLHUP) {
 			/* Connection closed */
diff --git a/subsys/net/lib/http/http_compression.c b/subsys/net/lib/http/http_compression.c
new file mode 100644
index 00000000000..d41d4ad7233
--- /dev/null
+++ b/subsys/net/lib/http/http_compression.c
@@ -0,0 +1,133 @@
+/** @file
+ * @brief HTTP compression handling functions
+ *
+ * Helper functions to handle compression formats
+ */
+
+/*
+ * Copyright (c) 2025 Endress+Hauser
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdbool.h>
+#include <string.h>
+#include <strings.h>
+
+#include <zephyr/net/http/server.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/util.h>
+
+#include "headers/server_internal.h"
+
+static int http_compression_match(enum http_compression *compression, const char *text,
+				  enum http_compression expected);
+
+void http_compression_parse_accept_encoding(const char *accept_encoding, size_t len,
+					    uint8_t *supported_compression)
+{
+	enum http_compression detected_compression;
+	char strbuf[HTTP_COMPRESSION_MAX_STRING_LEN + 1] = {0};
+	const char *start = accept_encoding;
+	const char *end = NULL;
+	bool priority_string = false;
+
+	*supported_compression = HTTP_NONE;
+	for (size_t i = 0; i < len; i++) {
+		if (accept_encoding[i] == 0) {
+			break;
+		} else if (accept_encoding[i] == ' ') {
+			start = &accept_encoding[i + 1];
+			continue;
+		} else if (accept_encoding[i] == ';') {
+			end = &accept_encoding[i];
+			priority_string = true;
+		} else if (accept_encoding[i] == ',') {
+			if (!priority_string) {
+				end = &accept_encoding[i];
+			}
+			priority_string = false;
+		} else if (i + 1 == len) {
+			end = &accept_encoding[i + 1];
+		}
+
+		if (end == NULL) {
+			continue;
+		}
+
+		if (end - start > HTTP_COMPRESSION_MAX_STRING_LEN) {
+			end = NULL;
+			start = end + 1;
+			continue;
+		}
+
+		memcpy(strbuf, start, end - start);
+		strbuf[end - start] = 0;
+
+		if (http_compression_from_text(&detected_compression, strbuf) == 0) {
+			WRITE_BIT(*supported_compression, detected_compression, true);
+		}
+
+		end = NULL;
+		start = end + 1;
+	}
+}
+
+const char *http_compression_text(enum http_compression compression)
+{
+	switch (compression) {
+	case HTTP_NONE:
+		return "";
+	case HTTP_GZIP:
+		return "gzip";
+	case HTTP_COMPRESS:
+		return "compress";
+	case HTTP_DEFLATE:
+		return "deflate";
+	case HTTP_BR:
+		return "br";
+	case HTTP_ZSTD:
+		return "zstd";
+	}
+	return "";
+}
+
+int http_compression_from_text(enum http_compression *compression, const char *text)
+{
+	__ASSERT_NO_MSG(compression);
+	__ASSERT_NO_MSG(text);
+
+	for (enum http_compression i = 0; compression_value_is_valid(i); ++i) {
+		if (http_compression_match(compression, text, i) == 0) {
+			return 0;
+		}
+	}
+	return 1;
+}
+
+bool compression_value_is_valid(enum http_compression compression)
+{
+	switch (compression) {
+	case HTTP_NONE:
+	case HTTP_GZIP:
+	case HTTP_COMPRESS:
+	case HTTP_DEFLATE:
+	case HTTP_BR:
+	case HTTP_ZSTD:
+		return true;
+	}
+	return false;
+}
+
+static int http_compression_match(enum http_compression *compression, const char *text,
+				  enum http_compression expected)
+{
+	__ASSERT_NO_MSG(compression);
+	__ASSERT_NO_MSG(text);
+
+	if (strcasecmp(http_compression_text(expected), text) == 0) {
+		*compression = expected;
+		return 0;
+	} else {
+		return 1;
+	}
+}
diff --git a/subsys/net/lib/http/http_hpack.c b/subsys/net/lib/http/http_hpack.c
index 5fdc7e4004d..4df4de0f749 100644
--- a/subsys/net/lib/http/http_hpack.c
+++ b/subsys/net/lib/http/http_hpack.c
@@ -18,11 +18,6 @@ static inline bool http_hpack_key_is_static(uint32_t key)
 	return key > HTTP_SERVER_HPACK_INVALID && key <= HTTP_SERVER_HPACK_WWW_AUTHENTICATE;
 }
 
-static inline bool http_hpack_key_is_dynamic(uint32_t key)
-{
-	return key > HTTP_SERVER_HPACK_WWW_AUTHENTICATE;
-}
-
 struct hpack_table_entry {
 	const char *name;
 	const char *value;
diff --git a/subsys/net/lib/http/http_parser.c b/subsys/net/lib/http/http_parser.c
index ff8867b853d..e8c179bce18 100644
--- a/subsys/net/lib/http/http_parser.c
+++ b/subsys/net/lib/http/http_parser.c
@@ -100,7 +100,9 @@ int count_header_size(struct http_parser *parser, int bytes)
 
 #define PROXY_CONNECTION "proxy-connection"
 #define CONNECTION "connection"
+#define CONTENT "content-"
 #define CONTENT_LENGTH "content-length"
+#define CONTENT_RANGE "content-range"
 #define TRANSFER_ENCODING "transfer-encoding"
 #define UPGRADE "upgrade"
 #define CHUNKED "chunked"
@@ -183,11 +185,17 @@ enum header_states {
 	h_CON,
 	h_matching_connection,
 	h_matching_proxy_connection,
+	h_matching_content,
+	h_CONTENT_,
 	h_matching_content_length,
+	h_matching_content_range,
 	h_matching_transfer_encoding,
 	h_matching_upgrade,
 	h_connection,
 	h_content_length,
+	h_content_range_start,
+	h_content_range_end,
+	h_content_range_total,
 	h_transfer_encoding,
 	h_upgrade,
 	h_matching_transfer_encoding_chunked,
@@ -356,6 +364,8 @@ static struct {
 	{"HPE_INVALID_CONTENT_LENGTH", "invalid character in content-length "
 				       "header"},
 	{"HPE_UNEXPECTED_CONTENT_LENGTH", "unexpected content-length header"},
+	{"HPE_INVALID_CONTENT_RANGE", "invalid character in content-range header"},
+	{"HPE_UNEXPECTED_CONTENT_RANGE", "unexpected content-range header"},
 	{"HPE_INVALID_CHUNK_SIZE", "invalid character in chunk size header"},
 	{"HPE_INVALID_CONSTANT", "invalid constant string"},
 	{"HPE_INVALID_INTERNAL_STATE", "encountered unexpected internal state"},
@@ -392,7 +402,7 @@ int parser_header_state(struct http_parser *parser, char ch, char c)
 			parser->header_state = h_matching_connection;
 			break;
 		case 't':
-			parser->header_state = h_matching_content_length;
+			parser->header_state = h_matching_content;
 			break;
 		default:
 			parser->header_state = h_general;
@@ -424,7 +434,29 @@ int parser_header_state(struct http_parser *parser, char ch, char c)
 		}
 		break;
 
-	/* content-length */
+	/*content-length or content-range*/
+
+	case h_matching_content:
+		parser->index++;
+		cond1 = parser->index > sizeof(CONTENT) - 1;
+		if (cond1 || c != CONTENT[parser->index]) {
+			parser->header_state = h_general;
+		} else if (parser->index == sizeof(CONTENT) - 2) {
+			parser->header_state = h_CONTENT_;
+		}
+		break;
+
+	case h_CONTENT_:
+		parser->index++;
+		if (c == 'l') {
+			parser->header_state = h_matching_content_length;
+		} else if (c == 'r') {
+			parser->header_state = h_matching_content_range;
+		} else {
+			parser->header_state = h_general;
+		}
+		break;
+
 
 	case h_matching_content_length:
 		parser->index++;
@@ -436,6 +468,16 @@ int parser_header_state(struct http_parser *parser, char ch, char c)
 		}
 		break;
 
+	case h_matching_content_range:
+		parser->index++;
+		cond1 = parser->index > sizeof(CONTENT_RANGE) - 1;
+		if (cond1 || c != CONTENT_RANGE[parser->index]) {
+			parser->header_state = h_general;
+		} else if (parser->index == sizeof(CONTENT_RANGE) - 2) {
+			parser->header_state = h_content_range_start;
+		}
+		break;
+
 	/* transfer-encoding */
 
 	case h_matching_transfer_encoding:
@@ -462,6 +504,9 @@ int parser_header_state(struct http_parser *parser, char ch, char c)
 
 	case h_connection:
 	case h_content_length:
+	case h_content_range_start:
+	case h_content_range_end:
+	case h_content_range_total:
 	case h_transfer_encoding:
 	case h_upgrade:
 		if (ch != ' ') {
@@ -546,6 +591,117 @@ int header_states(struct http_parser *parser, const char *data, size_t len,
 		break;
 	}
 
+	case h_content_range_start: {
+		uint64_t t;
+		uint64_t value;
+
+		if (IS_ALPHA(ch)) {
+			break;
+		}
+
+		if (ch == ' ') {
+			break;
+		}
+
+		if (ch == '-' || ch == '*') {
+			h_state = h_content_range_end;
+			break;
+		}
+
+		if (UNLIKELY(!IS_NUM(ch))) {
+			SET_ERRNO(HPE_INVALID_CONTENT_RANGE);
+			parser->header_state = h_state;
+			return -1;
+		}
+
+		t = parser->content_range.start;
+		t *= 10U;
+		t += ch - '0';
+
+		/* Overflow? Test against a conservative limit for simplicity */
+		value = (ULLONG_MAX - 10) / 10;
+
+		if (UNLIKELY(value < parser->content_range.start)) {
+			SET_ERRNO(HPE_INVALID_CONTENT_RANGE);
+			parser->header_state = h_state;
+			return -1;
+		}
+
+		parser->content_range.start = t;
+		break;
+	}
+
+	case h_content_range_end: {
+		uint64_t t;
+		uint64_t value;
+
+		if (ch == ' ') {
+			break;
+		}
+
+		if (ch == '/') {
+			h_state = h_content_range_total;
+			break;
+		}
+
+		if (UNLIKELY(!IS_NUM(ch))) {
+			SET_ERRNO(HPE_INVALID_CONTENT_RANGE);
+			parser->header_state = h_state;
+			return -1;
+		}
+
+		t = parser->content_range.end;
+		t *= 10U;
+		t += ch - '0';
+
+		/* Overflow? Test against a conservative limit for simplicity */
+		value = (ULLONG_MAX - 10) / 10;
+
+		if (UNLIKELY(value < parser->content_range.end)) {
+			SET_ERRNO(HPE_INVALID_CONTENT_RANGE);
+			parser->header_state = h_state;
+			return -1;
+		}
+
+		parser->content_range.end = t;
+		break;
+	}
+
+	case h_content_range_total: {
+		uint64_t t;
+		uint64_t value;
+
+		if (ch == ' ') {
+			break;
+		}
+
+		if (ch == '*') {
+			break;
+		}
+
+		if (UNLIKELY(!IS_NUM(ch))) {
+			SET_ERRNO(HPE_INVALID_CONTENT_RANGE);
+			parser->header_state = h_state;
+			return -1;
+		}
+
+		t = parser->content_range.total;
+		t *= 10U;
+		t += ch - '0';
+
+		/* Overflow? Test against a conservative limit for simplicity */
+		value = (ULLONG_MAX - 10) / 10;
+
+		if (UNLIKELY(value < parser->content_range.total)) {
+			SET_ERRNO(HPE_INVALID_CONTENT_RANGE);
+			parser->header_state = h_state;
+			return -1;
+		}
+
+		parser->content_range.total = t;
+		break;
+	}
+
 	/* Transfer-Encoding: chunked */
 	case h_matching_transfer_encoding_chunked:
 		parser->index++;
@@ -811,6 +967,10 @@ int parser_execute(struct http_parser *parser,
 			}
 			parser->flags = 0U;
 			parser->content_length = ULLONG_MAX;
+			parser->content_range.start = 0U;
+			parser->content_range.end = 0U;
+			parser->content_range.total = 0U;
+			parser->content_range_present = false;
 
 			if (ch == 'H') {
 				UPDATE_STATE(s_res_or_resp_H);
@@ -1104,6 +1264,10 @@ int parser_execute(struct http_parser *parser,
 			}
 			parser->flags = 0U;
 			parser->content_length = ULLONG_MAX;
+			parser->content_range.start = 0U;
+			parser->content_range.end = 0U;
+			parser->content_range.total = 0U;
+			parser->content_range_present = false;
 
 			if (UNLIKELY(!IS_ALPHA(ch))) {
 				SET_ERRNO(HPE_INVALID_METHOD);
@@ -1639,6 +1803,16 @@ int parser_execute(struct http_parser *parser,
 				parser->content_length = ch - '0';
 				break;
 
+			case h_content_range_start:
+				if (parser->content_range_present) {
+					SET_ERRNO(HPE_UNEXPECTED_CONTENT_RANGE);
+					goto error;
+				}
+
+				parser->content_range_present = true;
+				parser->content_range.start = 0;
+				break;
+
 			case h_connection:
 				/* looking for 'Connection: keep-alive' */
 				if (c == 'k') {
diff --git a/subsys/net/lib/http/http_server_core.c b/subsys/net/lib/http/http_server_core.c
index 61fae3b5862..98f651c20b3 100644
--- a/subsys/net/lib/http/http_server_core.c
+++ b/subsys/net/lib/http/http_server_core.c
@@ -22,6 +22,7 @@
 #include <zephyr/net/tls_credentials.h>
 #include <zephyr/posix/sys/eventfd.h>
 #include <zephyr/posix/fnmatch.h>
+#include <zephyr/sys/util_macro.h>
 
 LOG_MODULE_REGISTER(net_http_server, CONFIG_NET_HTTP_SERVER_LOG_LEVEL);
 
@@ -43,7 +44,6 @@ LOG_MODULE_REGISTER(net_http_server, CONFIG_NET_HTTP_SERVER_LOG_LEVEL);
 #define HTTP_SERVER_SOCK_COUNT (1 + HTTP_SERVER_MAX_SERVICES + HTTP_SERVER_MAX_CLIENTS)
 
 struct http_server_ctx {
-	int num_clients;
 	int listen_fds; /* max value of 1 + MAX_SERVICES */
 
 	/* First pollfd is eventfd that can be used to stop the server,
@@ -227,7 +227,8 @@ int http_server_init(struct http_server_ctx *ctx)
 			*svc->port = ntohs(addr.addr4->sin_port);
 		}
 
-		if (zsock_listen(fd, HTTP_SERVER_MAX_CLIENTS) < 0) {
+		svc->data->num_clients = 0;
+		if (zsock_listen(fd, svc->backlog) < 0) {
 			LOG_ERR("listen: %d", errno);
 			failed++;
 			zsock_close(fd);
@@ -237,6 +238,7 @@ int http_server_init(struct http_server_ctx *ctx)
 		LOG_DBG("Initialized HTTP Service %s:%u",
 			svc->host ? svc->host : "<any>", *svc->port);
 
+		*svc->fd = fd;
 		ctx->fds[count].fd = fd;
 		ctx->fds[count].events = ZSOCK_POLLIN;
 		count++;
@@ -250,7 +252,6 @@ int http_server_init(struct http_server_ctx *ctx)
 	}
 
 	ctx->listen_fds = count;
-	ctx->num_clients = 0;
 
 	return 0;
 }
@@ -299,6 +300,10 @@ static void close_all_sockets(struct http_server_ctx *ctx)
 
 		ctx->fds[i].fd = -1;
 	}
+
+	HTTP_SERVICE_FOREACH(svc) {
+		*svc->fd = -1;
+	}
 }
 
 static void client_release_resources(struct http_client_ctx *client)
@@ -350,8 +355,14 @@ void http_server_release_client(struct http_client_ctx *client)
 	k_work_cancel_delayable_sync(&client->inactivity_timer, &sync);
 	client_release_resources(client);
 
-	server_ctx.num_clients--;
+	client->service->data->num_clients--;
 
+	for (i = 0; i < server_ctx.listen_fds; i++) {
+		if (server_ctx.fds[i].fd == *client->service->fd) {
+			server_ctx.fds[i].events = ZSOCK_POLLIN;
+			break;
+		}
+	}
 	for (i = server_ctx.listen_fds; i < ARRAY_SIZE(server_ctx.fds); i++) {
 		if (server_ctx.fds[i].fd == client->fd) {
 			server_ctx.fds[i].fd = INVALID_SOCK;
@@ -393,9 +404,22 @@ void http_client_timer_restart(struct http_client_ctx *client)
 	k_work_reschedule(&client->inactivity_timer, INACTIVITY_TIMEOUT);
 }
 
-static void init_client_ctx(struct http_client_ctx *client, int new_socket)
+static const struct http_service_desc *lookup_service(int server_fd)
+{
+	HTTP_SERVICE_FOREACH(svc) {
+		if (*svc->fd == server_fd) {
+			return svc;
+		}
+	}
+
+	return NULL;
+}
+
+static void init_client_ctx(struct http_client_ctx *client, const struct http_service_desc *svc,
+			    int new_socket)
 {
 	client->fd = new_socket;
+	client->service = svc;
 	client->data_len = 0;
 	client->server_state = HTTP_SERVER_PREFACE_STATE;
 	client->has_upgrade_header = false;
@@ -523,6 +547,7 @@ static int handle_http_request(struct http_client_ctx *client)
 static int http_server_run(struct http_server_ctx *ctx)
 {
 	struct http_client_ctx *client;
+	const struct http_service_desc *service;
 	eventfd_t value;
 	bool found_slot;
 	int new_socket;
@@ -593,6 +618,14 @@ static int http_server_run(struct http_server_ctx *ctx)
 
 			/* First check if we have something to accept */
 			if (i < ctx->listen_fds) {
+				service = lookup_service(ctx->fds[i].fd);
+				__ASSERT(NULL != service, "fd not associated with a service");
+
+				if (service->data->num_clients >= service->concurrent) {
+					ctx->fds[i].events = 0;
+					continue;
+				}
+
 				new_socket = accept_new_client(ctx->fds[i].fd);
 				if (new_socket < 0) {
 					ret = -errno;
@@ -611,11 +644,11 @@ static int http_server_run(struct http_server_ctx *ctx)
 					ctx->fds[j].events = ZSOCK_POLLIN;
 					ctx->fds[j].revents = 0;
 
-					ctx->num_clients++;
+					service->data->num_clients++;
 
 					LOG_DBG("Init client #%d", j - ctx->listen_fds);
 
-					init_client_ctx(&ctx->clients[j - ctx->listen_fds],
+					init_client_ctx(&ctx->clients[j - ctx->listen_fds], service,
 							new_socket);
 					found_slot = true;
 					break;
@@ -678,22 +711,36 @@ static int http_server_run(struct http_server_ctx *ctx)
 	return ret;
 }
 
-/* Compare two strings where the terminator is either "\0" or "?" */
-static int compare_strings(const char *s1, const char *s2)
+/* Compare a path and a resource string. The path string comes from the HTTP request and may be
+ * terminated by either '?' or '\0'. The resource string is registered along with the resource and
+ * may only be terminated by `\0`.
+ */
+static int compare_strings(const char *path, const char *resource)
 {
-	while ((*s1 && *s2) && (*s1 == *s2) && (*s1 != '?')) {
-		s1++;
-		s2++;
+	while ((*path && *resource) && (*path == *resource) && (*path != '?')) {
+		path++;
+		resource++;
 	}
 
-	/* Check if both strings have reached their terminators or '?' */
-	if ((*s1 == '\0' || *s1 == '?') && (*s2 == '\0' || *s2 == '?')) {
+	/* Check if both strings have reached their terminators */
+	if ((*path == '\0' || *path == '?') && (*resource == '\0')) {
 		return 0; /* Strings are equal */
 	}
 
 	return 1; /* Strings are not equal */
 }
 
+static int path_len_without_query(const char *path)
+{
+	int len = 0;
+
+	while ((path[len] != '\0') && (path[len] != '?')) {
+		len++;
+	}
+
+	return len;
+}
+
 static bool skip_this(struct http_resource_desc *resource, bool is_websocket)
 {
 	struct http_resource_detail *detail;
@@ -713,61 +760,101 @@ static bool skip_this(struct http_resource_desc *resource, bool is_websocket)
 	return false;
 }
 
-struct http_resource_detail *get_resource_detail(const char *path,
-						 int *path_len,
-						 bool is_websocket)
+struct http_resource_detail *get_resource_detail(const struct http_service_desc *service,
+						 const char *path, int *path_len, bool is_websocket)
 {
-	HTTP_SERVICE_FOREACH(service) {
-		HTTP_SERVICE_FOREACH_RESOURCE(service, resource) {
-			if (skip_this(resource, is_websocket)) {
-				continue;
-			}
+	HTTP_SERVICE_FOREACH_RESOURCE(service, resource) {
+		if (skip_this(resource, is_websocket)) {
+			continue;
+		}
 
-			if (IS_ENABLED(CONFIG_HTTP_SERVER_RESOURCE_WILDCARD)) {
-				int ret;
+		if (IS_ENABLED(CONFIG_HTTP_SERVER_RESOURCE_WILDCARD)) {
+			int ret;
 
-				ret = fnmatch(resource->resource, path,
-					      (FNM_PATHNAME | FNM_LEADING_DIR));
-				if (ret == 0) {
-					*path_len = strlen(resource->resource);
-					return resource->detail;
-				}
+			ret = fnmatch(resource->resource, path, (FNM_PATHNAME | FNM_LEADING_DIR));
+			if (ret == 0) {
+				*path_len = path_len_without_query(path);
+				return resource->detail;
 			}
+		}
 
-			if (compare_strings(path, resource->resource) == 0) {
-				NET_DBG("Got match for %s", resource->resource);
+		if (compare_strings(path, resource->resource) == 0) {
+			NET_DBG("Got match for %s", resource->resource);
 
-				*path_len = strlen(resource->resource);
-				return resource->detail;
-			}
+			*path_len = strlen(resource->resource);
+			return resource->detail;
 		}
 	}
 
+	if (service->res_fallback != NULL) {
+		*path_len = path_len_without_query(path);
+		return service->res_fallback;
+	}
+
 	NET_DBG("No match for %s", path);
 
 	return NULL;
 }
 
-int http_server_find_file(char *fname, size_t fname_size, size_t *file_size, bool *gzipped)
+int http_server_find_file(char *fname, size_t fname_size, size_t *file_size,
+			  uint8_t supported_compression, enum http_compression *chosen_compression)
 {
 	struct fs_dirent dirent;
 	size_t len;
 	int ret;
 
-	ret = fs_stat(fname, &dirent);
-	if (ret < 0) {
-		len = strlen(fname);
-		snprintk(fname + len, fname_size - len, ".gz");
-		ret = fs_stat(fname, &dirent);
-		*gzipped = (ret == 0);
+	len = strlen(fname);
+	if (IS_ENABLED(CONFIG_HTTP_SERVER_COMPRESSION)) {
+		*chosen_compression = HTTP_NONE;
+		if (IS_BIT_SET(supported_compression, HTTP_BR)) {
+			snprintk(fname + len, fname_size - len, ".br");
+			ret = fs_stat(fname, &dirent);
+			if (ret == 0) {
+				*chosen_compression = HTTP_BR;
+				goto return_filename;
+			}
+		}
+		if (IS_BIT_SET(supported_compression, HTTP_GZIP)) {
+			snprintk(fname + len, fname_size - len, ".gz");
+			ret = fs_stat(fname, &dirent);
+			if (ret == 0) {
+				*chosen_compression = HTTP_GZIP;
+				goto return_filename;
+			}
+		}
+		if (IS_BIT_SET(supported_compression, HTTP_ZSTD)) {
+			snprintk(fname + len, fname_size - len, ".zst");
+			ret = fs_stat(fname, &dirent);
+			if (ret == 0) {
+				*chosen_compression = HTTP_ZSTD;
+				goto return_filename;
+			}
+		}
+		if (IS_BIT_SET(supported_compression, HTTP_COMPRESS)) {
+			snprintk(fname + len, fname_size - len, ".lzw");
+			ret = fs_stat(fname, &dirent);
+			if (ret == 0) {
+				*chosen_compression = HTTP_COMPRESS;
+				goto return_filename;
+			}
+		}
+		if (IS_BIT_SET(supported_compression, HTTP_DEFLATE)) {
+			snprintk(fname + len, fname_size - len, ".zz");
+			ret = fs_stat(fname, &dirent);
+			if (ret == 0) {
+				*chosen_compression = HTTP_DEFLATE;
+				goto return_filename;
+			}
+		}
 	}
-
-	if (ret == 0) {
-		*file_size = dirent.size;
-		return ret;
+	ret = fs_stat(fname, &dirent);
+	if (ret != 0) {
+		return -ENOENT;
 	}
 
-	return -ENOENT;
+return_filename:
+	*file_size = dirent.size;
+	return ret;
 }
 
 void http_server_get_content_type_from_extension(char *url, char *content_type,
diff --git a/subsys/net/lib/http/http_server_http1.c b/subsys/net/lib/http/http_server_http1.c
index e5ea4d478d2..399ea8b8efd 100644
--- a/subsys/net/lib/http/http_server_http1.c
+++ b/subsys/net/lib/http/http_server_http1.c
@@ -19,6 +19,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/net/http/service.h>
+#include <zephyr/net/http/server.h>
 
 LOG_MODULE_DECLARE(net_http_server, CONFIG_NET_HTTP_SERVER_LOG_LEVEL);
 
@@ -37,6 +38,85 @@ static const char conflict_response[] = "HTTP/1.1 409 Conflict\r\n\r\n";
 static const char final_chunk[] = "0\r\n\r\n";
 static const char *crlf = &final_chunk[3];
 
+static int send_http1_error_common(struct http_client_ctx *client,
+				   const char *response, size_t len)
+{
+	int ret;
+
+	ret = http_server_sendall(client, response, len);
+	if (ret < 0) {
+		LOG_DBG("Cannot write to socket (%d)", ret);
+		return ret;
+	}
+
+	client->http1_headers_sent = true;
+
+	return 0;
+}
+
+static int send_http1_404(struct http_client_ctx *client)
+{
+	return send_http1_error_common(client, not_found_response,
+				       sizeof(not_found_response) - 1);
+}
+
+static int send_http1_405(struct http_client_ctx *client)
+{
+	return send_http1_error_common(client, not_allowed_response,
+				       sizeof(not_allowed_response) - 1);
+}
+
+static int send_http1_409(struct http_client_ctx *client)
+{
+	return send_http1_error_common(client, conflict_response,
+				       sizeof(conflict_response) - 1);
+}
+
+static void send_http1_500(struct http_client_ctx *client, int error_code)
+{
+#define HTTP_500_RESPONSE_TEMPLATE			\
+	"HTTP/1.1 500 Internal Server Error\r\n"	\
+	"Content-Type: text/plain\r\n"			\
+	"Content-Length: %d\r\n\r\n"			\
+	"Internal Server Error%s%s\r\n"
+#define MAX_ERROR_DESC_LEN 32
+
+	/* Placeholder for the error description. */
+	char error_str[] = "xxx";
+	char http_response[sizeof(HTTP_500_RESPONSE_TEMPLATE) +
+			   sizeof("xx") + /* Content-Length */
+			   MAX_ERROR_DESC_LEN + 1]; /* For the error description */
+	const char *error_desc;
+	const char *desc_separator;
+	int desc_len;
+
+	if (IS_ENABLED(CONFIG_HTTP_SERVER_REPORT_FAILURE_REASON)) {
+		/* Try to fetch error description, fallback to error number if
+		 * not available
+		 */
+		error_desc = strerror(error_code);
+		if (strlen(error_desc) == 0) {
+			/* Cast error value to uint8_t to avoid truncation warnings. */
+			(void)snprintk(error_str, sizeof(error_str), "%u",
+				       (uint8_t)error_code);
+			error_desc = error_str;
+		}
+		desc_separator = ": ";
+		desc_len = MIN(MAX_ERROR_DESC_LEN, strlen(error_desc));
+		desc_len += 2; /* For ": " */
+	} else {
+		error_desc = "";
+		desc_separator = "";
+		desc_len = 0;
+	}
+
+	(void)snprintk(http_response, sizeof(http_response),
+		       HTTP_500_RESPONSE_TEMPLATE,
+		       (int)sizeof("Internal Server Error\r\n") - 1 + desc_len,
+		       desc_separator, error_desc);
+	(void)http_server_sendall(client, http_response, strlen(http_response));
+}
+
 static int handle_http1_static_resource(
 	struct http_resource_detail_static *static_detail,
 	struct http_client_ctx *client)
@@ -56,37 +136,40 @@ static int handle_http1_static_resource(
 	int len;
 	int ret;
 
-	if (static_detail->common.bitmask_of_supported_http_methods & BIT(HTTP_GET)) {
-		data = static_detail->static_data;
-		len = static_detail->static_data_len;
-
-		if (static_detail->common.content_encoding != NULL &&
-		    static_detail->common.content_encoding[0] != '\0') {
-			snprintk(http_response, sizeof(http_response),
-				 RESPONSE_TEMPLATE "Content-Encoding: %s\r\n\r\n",
-				 "Content-Type: ",
-				 static_detail->common.content_type == NULL ?
-				 "text/html" : static_detail->common.content_type,
-				 len, static_detail->common.content_encoding);
-		} else {
-			snprintk(http_response, sizeof(http_response),
-				 RESPONSE_TEMPLATE "\r\n",
-				 "Content-Type: ",
-				 static_detail->common.content_type == NULL ?
-				 "text/html" : static_detail->common.content_type,
-				 len);
-		}
+	if (client->method != HTTP_GET) {
+		return send_http1_405(client);
+	}
 
-		ret = http_server_sendall(client, http_response,
-					  strlen(http_response));
-		if (ret < 0) {
-			return ret;
-		}
+	data = static_detail->static_data;
+	len = static_detail->static_data_len;
+
+	if (static_detail->common.content_encoding != NULL &&
+	    static_detail->common.content_encoding[0] != '\0') {
+		snprintk(http_response, sizeof(http_response),
+			 RESPONSE_TEMPLATE "Content-Encoding: %s\r\n\r\n",
+			 "Content-Type: ",
+			 static_detail->common.content_type == NULL ?
+			 "text/html" : static_detail->common.content_type,
+			 len, static_detail->common.content_encoding);
+	} else {
+		snprintk(http_response, sizeof(http_response),
+			 RESPONSE_TEMPLATE "\r\n",
+			 "Content-Type: ",
+			 static_detail->common.content_type == NULL ?
+			 "text/html" : static_detail->common.content_type,
+			 len);
+	}
 
-		ret = http_server_sendall(client, data, len);
-		if (ret < 0) {
-			return ret;
-		}
+	ret = http_server_sendall(client, http_response, strlen(http_response));
+	if (ret < 0) {
+		return ret;
+	}
+
+	client->http1_headers_sent = true;
+
+	ret = http_server_sendall(client, data, len);
+	if (ret < 0) {
+		return ret;
 	}
 
 	return 0;
@@ -388,10 +471,24 @@ int handle_http1_static_fs_resource(struct http_resource_detail_static_fs *stati
 {
 #define RESPONSE_TEMPLATE_STATIC_FS                                                                \
 	"HTTP/1.1 200 OK\r\n"                                                                      \
-	"Content-Type: %s%s\r\n\r\n"
-#define CONTENT_ENCODING_GZIP "\r\nContent-Encoding: gzip"
-
-	bool gzipped = false;
+	"Content-Length: %zd\r\n"                                                                  \
+	"Content-Type: %s%s%s\r\n\r\n"
+#define CONTENT_ENCODING_HEADER "\r\nContent-Encoding: "
+/* Add couple of bytes to response template size to have space
+ * for the content type and encoding
+ */
+#define STATIC_FS_RESPONSE_BASE_SIZE                                                               \
+	sizeof(RESPONSE_TEMPLATE_STATIC_FS) + HTTP_SERVER_MAX_CONTENT_TYPE_LEN +                   \
+		sizeof("Content-Length: 01234567890123456789\r\n")
+#define CONTENT_ENCODING_HEADER_SIZE                                                               \
+	sizeof(CONTENT_ENCODING_HEADER) + HTTP_COMPRESSION_MAX_STRING_LEN + sizeof("\r\n")
+#define STATIC_FS_RESPONSE_SIZE                                                                    \
+	COND_CODE_1(                                                                               \
+		IS_ENABLED(CONFIG_HTTP_SERVER_COMPRESSION),                                        \
+		(STATIC_FS_RESPONSE_BASE_SIZE + CONTENT_ENCODING_HEADER_SIZE),                     \
+		(STATIC_FS_RESPONSE_BASE_SIZE))
+
+	enum http_compression chosen_compression = 0;
 	int len;
 	int remaining;
 	int ret;
@@ -399,19 +496,10 @@ int handle_http1_static_fs_resource(struct http_resource_detail_static_fs *stati
 	struct fs_file_t file;
 	char fname[HTTP_SERVER_MAX_URL_LENGTH];
 	char content_type[HTTP_SERVER_MAX_CONTENT_TYPE_LEN] = "text/html";
-	/* Add couple of bytes to response template size to have space
-	 * for the content type and encoding
-	 */
-	char http_response[sizeof(RESPONSE_TEMPLATE_STATIC_FS) + HTTP_SERVER_MAX_CONTENT_TYPE_LEN +
-			   sizeof(CONTENT_ENCODING_GZIP)];
+	char http_response[STATIC_FS_RESPONSE_SIZE];
 
-	if (!(static_fs_detail->common.bitmask_of_supported_http_methods & BIT(HTTP_GET))) {
-		ret = http_server_sendall(client, not_allowed_response,
-					  sizeof(not_allowed_response) - 1);
-		if (ret < 0) {
-			LOG_DBG("Cannot write to socket (%d)", ret);
-		}
-		return ret;
+	if (client->method != HTTP_GET) {
+		return send_http1_405(client);
 	}
 
 	/* get filename and content-type from url */
@@ -427,15 +515,15 @@ int handle_http1_static_fs_resource(struct http_resource_detail_static_fs *stati
 	}
 
 	/* open file, if it exists */
-	ret = http_server_find_file(fname, sizeof(fname), &file_size, &gzipped);
+#ifdef CONFIG_HTTP_SERVER_COMPRESSION
+	ret = http_server_find_file(fname, sizeof(fname), &file_size, client->supported_compression,
+			    &chosen_compression);
+#else
+	ret = http_server_find_file(fname, sizeof(fname), &file_size, 0, NULL);
+#endif /* CONFIG_HTTP_SERVER_COMPRESSION */
 	if (ret < 0) {
 		LOG_ERR("fs_stat %s: %d", fname, ret);
-		ret = http_server_sendall(client, not_found_response,
-					  sizeof(not_found_response) - 1);
-		if (ret < 0) {
-			LOG_DBG("Cannot write to socket (%d)", ret);
-		}
-		return ret;
+		return send_http1_404(client);
 	}
 	fs_file_t_init(&file);
 	ret = fs_open(&file, fname, FS_O_READ);
@@ -449,13 +537,22 @@ int handle_http1_static_fs_resource(struct http_resource_detail_static_fs *stati
 	LOG_DBG("found %s, file size: %zu", fname, file_size);
 
 	/* send HTTP header */
-	len = snprintk(http_response, sizeof(http_response), RESPONSE_TEMPLATE_STATIC_FS,
-		       content_type, gzipped ? CONTENT_ENCODING_GZIP : "");
+	if (IS_ENABLED(CONFIG_HTTP_SERVER_COMPRESSION) &&
+	    http_compression_text(chosen_compression)[0] != 0) {
+		len = snprintk(http_response, sizeof(http_response), RESPONSE_TEMPLATE_STATIC_FS,
+			       file_size, content_type, CONTENT_ENCODING_HEADER,
+			       http_compression_text(chosen_compression));
+	} else {
+		len = snprintk(http_response, sizeof(http_response), RESPONSE_TEMPLATE_STATIC_FS,
+			       file_size, content_type, "", "");
+	}
 	ret = http_server_sendall(client, http_response, len);
 	if (ret < 0) {
 		goto close;
 	}
 
+	client->http1_headers_sent = true;
+
 	/* read and send file */
 	remaining = file_size;
 	while (remaining > 0) {
@@ -495,14 +592,12 @@ static int handle_http1_dynamic_resource(
 	user_method = dynamic_detail->common.bitmask_of_supported_http_methods;
 
 	if (!(BIT(client->method) & user_method)) {
-		return -ENOPROTOOPT;
+		return send_http1_405(client);
 	}
 
 	if (dynamic_detail->holder != NULL && dynamic_detail->holder != client) {
-		ret = http_server_sendall(client, conflict_response,
-					  sizeof(conflict_response) - 1);
+		ret = send_http1_409(client);
 		if (ret < 0) {
-			LOG_DBG("Cannot write to socket (%d)", ret);
 			return ret;
 		}
 
@@ -520,6 +615,7 @@ static int handle_http1_dynamic_resource(
 				return ret;
 			}
 
+			client->http1_headers_sent = true;
 			dynamic_detail->holder = NULL;
 
 			return 0;
@@ -582,7 +678,7 @@ static void check_user_request_headers(struct http_header_capture_ctx *ctx, cons
 				break;
 			}
 
-			strcpy(dest, header->name);
+			memcpy(dest, header->name, header_len + 1);
 
 			ctx->headers[ctx->count].name = dest;
 			ctx->cursor += (header_len + 1);
@@ -623,6 +719,11 @@ static int on_header_field(struct http_parser *parser, const char *at,
 			} else if (strcasecmp(ctx->header_buffer, "Sec-WebSocket-Key") == 0) {
 				ctx->websocket_sec_key_next = true;
 			}
+#ifdef CONFIG_HTTP_SERVER_COMPRESSION
+			else if (strcasecmp(ctx->header_buffer, "Accept-Encoding") == 0) {
+				ctx->accept_encoding_next = true;
+			}
+#endif /* CONFIG_HTTP_SERVER_COMPRESSION */
 
 			ctx->header_buffer[0] = '\0';
 		}
@@ -655,7 +756,7 @@ static void populate_user_request_header(struct http_header_capture_ctx *ctx, co
 	}
 
 	dest = &ctx->buffer[ctx->cursor];
-	strcpy(dest, buf);
+	memcpy(dest, buf, value_len + 1);
 	ctx->cursor += (value_len + 1);
 
 	ctx->headers[ctx->count].value = dest;
@@ -708,6 +809,13 @@ static int on_header_value(struct http_parser *parser,
 #endif
 				ctx->websocket_sec_key_next = false;
 			}
+#ifdef CONFIG_HTTP_SERVER_COMPRESSION
+			if (ctx->accept_encoding_next) {
+				http_compression_parse_accept_encoding(ctx->header_buffer, offset,
+								       &ctx->supported_compression);
+				ctx->accept_encoding_next = false;
+			}
+#endif /* CONFIG_HTTP_SERVER_COMPRESSION */
 
 			ctx->header_buffer[0] = '\0';
 		}
@@ -814,12 +922,14 @@ int handle_http1_request(struct http_client_ctx *client)
 
 	if (parsed > client->data_len) {
 		LOG_ERR("HTTP/1 parser error, too much data consumed");
-		return -EBADMSG;
+		ret = -EBADMSG;
+		goto error;
 	}
 
 	if (client->parser.http_errno != HPE_OK) {
 		LOG_ERR("HTTP/1 parsing error, %d", client->parser.http_errno);
-		return -EBADMSG;
+		ret = -EBADMSG;
+		goto error;
 	}
 
 	if (client->parser_state < HTTP1_RECEIVED_HEADER_STATE) {
@@ -838,7 +948,8 @@ int handle_http1_request(struct http_client_ctx *client)
 		size_t frag_headers_len;
 
 		if (parsed < client->http1_frag_data_len) {
-			return -EBADMSG;
+			ret = -EBADMSG;
+			goto error;
 		}
 
 		frag_headers_len = parsed - client->http1_frag_data_len;
@@ -859,21 +970,33 @@ int handle_http1_request(struct http_client_ctx *client)
 
 		if (client->websocket_upgrade) {
 			if (IS_ENABLED(CONFIG_HTTP_SERVER_WEBSOCKET)) {
-				detail = get_resource_detail(client->url_buffer,
+				detail = get_resource_detail(client->service, client->url_buffer,
 							     &path_len, true);
 				if (detail == NULL) {
 					goto not_found;
 				}
 
+				detail->path_len = path_len;
 				client->current_detail = detail;
-				return handle_http1_to_websocket_upgrade(client);
+
+				ret = handle_http1_to_websocket_upgrade(client);
+				if (ret < 0) {
+					goto error;
+				}
+
+				return 0;
 			}
 
 			goto upgrade_not_found;
 		}
 
 		if (client->http2_upgrade) {
-			return handle_http1_to_http2_upgrade(client);
+			ret = handle_http1_to_http2_upgrade(client);
+			if (ret < 0) {
+				goto error;
+			}
+
+			return 0;
 		}
 
 upgrade_not_found:
@@ -881,25 +1004,27 @@ int handle_http1_request(struct http_client_ctx *client)
 					  sizeof(upgrade_required) - 1);
 		if (ret < 0) {
 			LOG_DBG("Cannot write to socket (%d)", ret);
-			return ret;
+			goto error;
 		}
 
+		client->http1_headers_sent = true;
+
 		ret = http_server_sendall(client, needed_upgrade,
 					  strlen(needed_upgrade));
 		if (ret < 0) {
 			LOG_DBG("Cannot write to socket (%d)", ret);
-			return ret;
+			goto error;
 		}
 
 		ret = http_server_sendall(client, upgrade_msg,
 					  sizeof(upgrade_msg) - 1);
 		if (ret < 0) {
 			LOG_DBG("Cannot write to socket (%d)", ret);
-			return ret;
+			goto error;
 		}
 	}
 
-	detail = get_resource_detail(client->url_buffer, &path_len, false);
+	detail = get_resource_detail(client->service, client->url_buffer, &path_len, false);
 	if (detail != NULL) {
 		detail->path_len = path_len;
 
@@ -908,14 +1033,14 @@ int handle_http1_request(struct http_client_ctx *client)
 				(struct http_resource_detail_static *)detail,
 				client);
 			if (ret < 0) {
-				return ret;
+				goto error;
 			}
 #if defined(CONFIG_FILE_SYSTEM)
 		} else if (detail->type == HTTP_RESOURCE_TYPE_STATIC_FS) {
 			ret = handle_http1_static_fs_resource(
 				(struct http_resource_detail_static_fs *)detail, client);
 			if (ret < 0) {
-				return ret;
+				goto error;
 			}
 #endif
 		} else if (detail->type == HTTP_RESOURCE_TYPE_DYNAMIC) {
@@ -923,17 +1048,17 @@ int handle_http1_request(struct http_client_ctx *client)
 				(struct http_resource_detail_dynamic *)detail,
 				client);
 			if (ret < 0) {
-				return ret;
+				goto error;
 			}
 		}
 	} else {
 not_found: ; /* Add extra semicolon to make clang to compile when using label */
-		ret = http_server_sendall(client, not_found_response,
-					  sizeof(not_found_response) - 1);
+		ret = send_http1_404(client);
 		if (ret < 0) {
-			LOG_DBG("Cannot write to socket (%d)", ret);
-			return ret;
+			goto error;
 		}
+
+		client->http1_headers_sent = true;
 	}
 
 	client->cursor += parsed;
@@ -950,4 +1075,16 @@ not_found: ; /* Add extra semicolon to make clang to compile when using label */
 	}
 
 	return 0;
+
+error:
+	/* Best effort try to send HTTP 500 Internal Server Error response in
+	 * case of errors. This can only be done however if we haven't sent
+	 * response header elsewhere (i. e. can't send another reply if the
+	 * error ocurred amid resource processing).
+	 */
+	if (ret != -EAGAIN && !client->http1_headers_sent) {
+		send_http1_500(client, -ret);
+	}
+
+	return ret;
 }
diff --git a/subsys/net/lib/http/http_server_http2.c b/subsys/net/lib/http/http_server_http2.c
index 5a21691d4ab..fad55b6265e 100644
--- a/subsys/net/lib/http/http_server_http2.c
+++ b/subsys/net/lib/http/http_server_http2.c
@@ -17,6 +17,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/net/http/service.h>
+#include <zephyr/net/http/server.h>
 
 LOG_MODULE_DECLARE(net_http_server, CONFIG_NET_HTTP_SERVER_LOG_LEVEL);
 
@@ -208,6 +209,8 @@ static int send_headers_frame(struct http_client_ctx *client, enum http_status s
 		return ret;
 	}
 
+	client->current_stream->headers_sent = true;
+
 	return 0;
 }
 
@@ -337,6 +340,22 @@ static int send_http2_404(struct http_client_ctx *client,
 	return ret;
 }
 
+static int send_http2_405(struct http_client_ctx *client,
+			  struct http2_frame *frame)
+{
+	int ret;
+
+	ret = send_headers_frame(client, HTTP_405_METHOD_NOT_ALLOWED,
+				 frame->stream_identifier, NULL,
+				 HTTP2_FLAG_END_STREAM, NULL, 0);
+	if (ret < 0) {
+		LOG_DBG("Cannot write to socket (%d)", ret);
+		return ret;
+	}
+
+	return ret;
+}
+
 static int send_http2_409(struct http_client_ctx *client,
 			  struct http2_frame *frame)
 {
@@ -351,6 +370,46 @@ static int send_http2_409(struct http_client_ctx *client,
 	return ret;
 }
 
+static void send_http2_500(struct http_client_ctx *client,
+			   struct http2_frame *frame, int error_code)
+{
+#define HTTP_500_RESPONSE_TEMPLATE "Internal Server Error%s%s"
+#define MAX_ERROR_DESC_LEN 32
+
+	char error_str[] = "xxx";
+	char http_response[sizeof(HTTP_500_RESPONSE_TEMPLATE) +
+			   MAX_ERROR_DESC_LEN + 1]; /* For the error description */
+	const char *error_desc;
+	const char *desc_separator;
+
+	if (IS_ENABLED(CONFIG_HTTP_SERVER_REPORT_FAILURE_REASON)) {
+		/* Try to fetch error description, fallback to error number if
+		 * not available
+		 */
+		error_desc = strerror(error_code);
+		if (strlen(error_desc) == 0) {
+			/* Cast error value to uint8_t to avoid truncation warnings. */
+			(void)snprintk(error_str, sizeof(error_str), "%u",
+				       (uint8_t)error_code);
+			error_desc = error_str;
+		}
+		desc_separator = ": ";
+	} else {
+		error_desc = "";
+		desc_separator = "";
+	}
+
+	if (send_headers_frame(client, HTTP_500_INTERNAL_SERVER_ERROR,
+			       frame->stream_identifier, NULL, 0, NULL, 0) < 0) {
+		return;
+	}
+
+	(void)snprintk(http_response, sizeof(http_response),
+		       HTTP_500_RESPONSE_TEMPLATE, desc_separator, error_desc);
+	(void)send_data_frame(client, http_response, strlen(http_response),
+			      frame->stream_identifier, HTTP2_FLAG_END_STREAM);
+}
+
 static int handle_http2_static_resource(
 	struct http_resource_detail_static *static_detail,
 	struct http2_frame *frame, struct http_client_ctx *client)
@@ -359,8 +418,8 @@ static int handle_http2_static_resource(
 	size_t content_len;
 	int ret;
 
-	if (!(static_detail->common.bitmask_of_supported_http_methods & BIT(HTTP_GET))) {
-		return -ENOTSUP;
+	if (client->method != HTTP_GET) {
+		return send_http2_405(client, frame);
 	}
 
 	if (client->current_stream == NULL) {
@@ -377,8 +436,6 @@ static int handle_http2_static_resource(
 		goto out;
 	}
 
-	client->current_stream->headers_sent = true;
-
 	ret = send_data_frame(client, content_200, content_len,
 			      frame->stream_identifier,
 			      HTTP2_FLAG_END_STREAM);
@@ -393,6 +450,7 @@ static int handle_http2_static_resource(
 	return ret;
 }
 
+#if defined(CONFIG_FILE_SYSTEM)
 static int handle_http2_static_fs_resource(struct http_resource_detail_static_fs *static_fs_detail,
 					   struct http2_frame *frame,
 					   struct http_client_ctx *client)
@@ -408,13 +466,13 @@ static int handle_http2_static_fs_resource(struct http_resource_detail_static_fs
 		.path_len = static_fs_detail->common.path_len,
 		.type = static_fs_detail->common.type,
 	};
-	bool gzipped;
+	enum http_compression chosen_compression = 0;
 	int len;
 	int remaining;
 	char tmp[64];
 
-	if (!(static_fs_detail->common.bitmask_of_supported_http_methods & BIT(HTTP_GET))) {
-		return -ENOTSUP;
+	if (client->method != HTTP_GET) {
+		return send_http2_405(client, frame);
 	}
 
 	if (client->current_stream == NULL) {
@@ -434,7 +492,12 @@ static int handle_http2_static_fs_resource(struct http_resource_detail_static_fs
 	}
 
 	/* open file, if it exists */
-	ret = http_server_find_file(fname, sizeof(fname), &client->data_len, &gzipped);
+#ifdef CONFIG_HTTP_SERVER_COMPRESSION
+	ret = http_server_find_file(fname, sizeof(fname), &client->data_len,
+					client->supported_compression, &chosen_compression);
+#else
+	ret = http_server_find_file(fname, sizeof(fname), &client->data_len, 0, NULL);
+#endif /* CONFIG_HTTP_SERVER_COMPRESSION */
 	if (ret < 0) {
 		LOG_ERR("fs_stat %s: %d", fname, ret);
 
@@ -455,8 +518,8 @@ static int handle_http2_static_fs_resource(struct http_resource_detail_static_fs
 	}
 
 	/* send headers */
-	if (gzipped) {
-		res_detail.content_encoding = "gzip";
+	if (IS_ENABLED(CONFIG_HTTP_SERVER_COMPRESSION)) {
+		res_detail.content_encoding = http_compression_text(chosen_compression);
 	}
 	ret = send_headers_frame(client, HTTP_200_OK, frame->stream_identifier, &res_detail, 0,
 				 NULL, 0);
@@ -465,8 +528,6 @@ static int handle_http2_static_fs_resource(struct http_resource_detail_static_fs
 		goto out;
 	}
 
-	client->current_stream->headers_sent = true;
-
 	/* read and send file */
 	remaining = client->data_len;
 	while (remaining > 0) {
@@ -493,6 +554,7 @@ static int handle_http2_static_fs_resource(struct http_resource_detail_static_fs
 
 	return ret;
 }
+#endif /* CONFIG_FILE_SYSTEM */
 
 static int http2_dynamic_response(struct http_client_ctx *client, struct http2_frame *frame,
 				  struct http_response_ctx *rsp, enum http_data_status data_status,
@@ -535,8 +597,6 @@ static int http2_dynamic_response(struct http_client_ctx *client, struct http2_f
 		if (ret < 0) {
 			return ret;
 		}
-
-		client->current_stream->headers_sent = true;
 	}
 
 	/* Send body data if provided */
@@ -719,7 +779,7 @@ static int handle_http2_dynamic_resource(
 	user_method = dynamic_detail->common.bitmask_of_supported_http_methods;
 
 	if (!(BIT(client->method) & user_method)) {
-		return -ENOPROTOOPT;
+		return send_http2_405(client, frame);
 	}
 
 	if (dynamic_detail->holder != NULL && dynamic_detail->holder != client) {
@@ -1015,9 +1075,11 @@ int handle_http1_to_http2_upgrade(struct http_client_ctx *client)
 		ret = http_server_sendall(client, switching_protocols,
 					  sizeof(switching_protocols) - 1);
 		if (ret < 0) {
-			goto error;
+			return ret;
 		}
 
+		client->http1_headers_sent = true;
+
 		/* The first HTTP/2 frame sent by the server MUST be a server connection
 		 * preface.
 		 */
@@ -1029,7 +1091,7 @@ int handle_http1_to_http2_upgrade(struct http_client_ctx *client)
 		client->preface_sent = true;
 	}
 
-	detail = get_resource_detail(client->url_buffer, &path_len, false);
+	detail = get_resource_detail(client->service, client->url_buffer, &path_len, false);
 	if (detail != NULL) {
 		detail->path_len = path_len;
 
@@ -1040,12 +1102,14 @@ int handle_http1_to_http2_upgrade(struct http_client_ctx *client)
 			if (ret < 0) {
 				goto error;
 			}
+#if defined(CONFIG_FILE_SYSTEM)
 		} else if (detail->type == HTTP_RESOURCE_TYPE_STATIC_FS) {
 			ret = handle_http2_static_fs_resource(
 				(struct http_resource_detail_static_fs *)detail, frame, client);
 			if (ret < 0) {
 				goto error;
 			}
+#endif
 		} else if (detail->type == HTTP_RESOURCE_TYPE_DYNAMIC) {
 			ret = handle_http2_dynamic_resource(
 				(struct http_resource_detail_dynamic *)detail,
@@ -1087,6 +1151,11 @@ int handle_http1_to_http2_upgrade(struct http_client_ctx *client)
 	return 0;
 
 error:
+	if (ret != -EAGAIN && client->current_stream &&
+	    !client->current_stream->headers_sent) {
+		send_http2_500(client, frame, -ret);
+	}
+
 	return ret;
 }
 
@@ -1155,13 +1224,14 @@ int handle_http_frame_data(struct http_client_ctx *client)
 		/* There is no handler */
 		LOG_DBG("No dynamic handler found.");
 		(void)send_http2_404(client, frame);
-		return -ENOENT;
+		ret = -ENOENT;
+		goto error;
 	}
 
 	if (is_header_flag_set(frame->flags, HTTP2_FLAG_PADDED)) {
 		ret = parse_http_frame_padded_field(client);
 		if (ret < 0) {
-			return ret;
+			goto error;
 		}
 	}
 
@@ -1173,7 +1243,7 @@ int handle_http_frame_data(struct http_client_ctx *client)
 	}
 
 	if (ret < 0) {
-		return ret;
+		goto error;
 	}
 
 	if (frame->length == 0) {
@@ -1183,17 +1253,18 @@ int handle_http_frame_data(struct http_client_ctx *client)
 		if (stream == NULL) {
 			LOG_DBG("No stream context found for ID %d",
 				frame->stream_identifier);
-			return -EBADMSG;
+			ret = -EBADMSG;
+			goto error;
 		}
 
 		ret = send_window_update_frame(client, stream);
 		if (ret < 0) {
-			return ret;
+			goto error;
 		}
 
 		ret = send_window_update_frame(client, NULL);
 		if (ret < 0) {
-			return ret;
+			goto error;
 		}
 
 		if (is_header_flag_set(frame->flags, HTTP2_FLAG_END_STREAM)) {
@@ -1210,6 +1281,14 @@ int handle_http_frame_data(struct http_client_ctx *client)
 	}
 
 	return 0;
+
+error:
+	if (ret != -EAGAIN && client->current_stream &&
+	    !client->current_stream->headers_sent) {
+		send_http2_500(client, frame, -ret);
+	}
+
+	return ret;
 }
 
 static void check_user_request_headers_http2(struct http_header_capture_ctx *ctx,
@@ -1318,7 +1397,15 @@ static int process_header(struct http_client_ctx *client,
 		}
 
 		client->content_len = (size_t)len;
-	} else {
+	}
+#ifdef CONFIG_HTTP_SERVER_COMPRESSION
+	else if (header->name_len == (sizeof("accept-encoding") - 1) &&
+		 memcmp(header->name, "accept-encoding", header->name_len) == 0) {
+		http_compression_parse_accept_encoding(header->value, header->value_len,
+						       &client->supported_compression);
+	}
+#endif /* CONFIG_HTTP_SERVER_COMPRESSION */
+	else {
 		/* Just ignore for now. */
 		LOG_DBG("Ignoring field %.*s", (int)header->name_len, header->name);
 	}
@@ -1459,14 +1546,14 @@ int handle_http_frame_headers(struct http_client_ctx *client)
 	if (is_header_flag_set(frame->flags, HTTP2_FLAG_PADDED)) {
 		ret = parse_http_frame_padded_field(client);
 		if (ret < 0) {
-			return ret;
+			goto error;
 		}
 	}
 
 	if (is_header_flag_set(frame->flags, HTTP2_FLAG_PRIORITY)) {
 		ret = parse_http_frame_priority_field(client);
 		if (ret < 0) {
-			return ret;
+			goto error;
 		}
 	}
 
@@ -1482,12 +1569,17 @@ int handle_http_frame_headers(struct http_client_ctx *client)
 				ret = -EBADMSG;
 			}
 
-			return ret;
+			if (ret < 0) {
+				goto error;
+			}
+
+			return 0;
 		}
 
 		if (ret > frame->length) {
 			LOG_ERR("Protocol error, frame length exceeded");
-			return -EBADMSG;
+			ret = -EBADMSG;
+			goto error;
 		}
 
 		frame->length -= ret;
@@ -1499,7 +1591,7 @@ int handle_http_frame_headers(struct http_client_ctx *client)
 
 		ret = process_header(client, header);
 		if (ret < 0) {
-			return ret;
+			goto error;
 		}
 	}
 
@@ -1509,7 +1601,7 @@ int handle_http_frame_headers(struct http_client_ctx *client)
 		return 0;
 	}
 
-	detail = get_resource_detail(client->url_buffer, &path_len, false);
+	detail = get_resource_detail(client->service, client->url_buffer, &path_len, false);
 	if (detail != NULL) {
 		detail->path_len = path_len;
 
@@ -1518,34 +1610,36 @@ int handle_http_frame_headers(struct http_client_ctx *client)
 				(struct http_resource_detail_static *)detail,
 				frame, client);
 			if (ret < 0) {
-				return ret;
+				goto error;
 			}
+#if defined(CONFIG_FILE_SYSTEM)
 		} else if (detail->type == HTTP_RESOURCE_TYPE_STATIC_FS) {
 			ret = handle_http2_static_fs_resource(
 				(struct http_resource_detail_static_fs *)detail, frame, client);
 			if (ret < 0) {
-				return ret;
+				goto error;
 			}
+#endif
 		} else if (detail->type == HTTP_RESOURCE_TYPE_DYNAMIC) {
 			ret = handle_http2_dynamic_resource(
 				(struct http_resource_detail_dynamic *)detail,
 				frame, client);
 			if (ret < 0) {
-				return ret;
+				goto error;
 			}
 		}
 
 	} else {
 		ret = send_http2_404(client, frame);
 		if (ret < 0) {
-			return ret;
+			goto error;
 		}
 	}
 
 	if (is_header_flag_set(frame->flags, HTTP2_FLAG_END_STREAM)) {
 		ret = handle_http_frame_headers_end_stream(client);
 		if (ret < 0) {
-			return ret;
+			goto error;
 		}
 	}
 
@@ -1556,6 +1650,14 @@ int handle_http_frame_headers(struct http_client_ctx *client)
 	}
 
 	return 0;
+
+error:
+	if (ret != -EAGAIN && client->current_stream &&
+	    !client->current_stream->headers_sent) {
+		send_http2_500(client, frame, -ret);
+	}
+
+	return ret;
 }
 
 int handle_http_frame_priority(struct http_client_ctx *client)
diff --git a/subsys/net/lib/http/http_server_ws.c b/subsys/net/lib/http/http_server_ws.c
index 4cf1a7d1a6c..0eee1e02003 100644
--- a/subsys/net/lib/http/http_server_ws.c
+++ b/subsys/net/lib/http/http_server_ws.c
@@ -70,6 +70,8 @@ int handle_http1_to_websocket_upgrade(struct http_client_ctx *client)
 		goto error;
 	}
 
+	client->http1_headers_sent = true;
+
 	ret = http_server_sendall(client, tmp, strlen(tmp));
 	if (ret < 0) {
 		NET_DBG("Cannot write to socket (%d)", ret);
@@ -93,7 +95,10 @@ int handle_http1_to_websocket_upgrade(struct http_client_ctx *client)
 	 */
 	if (client->parser_state == HTTP1_MESSAGE_COMPLETE_STATE) {
 		struct http_resource_detail_websocket *ws_detail;
+		struct http_request_ctx request_ctx;
 		int ws_sock;
+		char *params;
+		size_t params_len;
 
 		ws_detail = (struct http_resource_detail_websocket *)client->current_detail;
 
@@ -105,9 +110,14 @@ int handle_http1_to_websocket_upgrade(struct http_client_ctx *client)
 			goto error;
 		}
 
+		memset(&request_ctx, 0, sizeof(request_ctx));
+		params = &client->url_buffer[client->current_detail->path_len];
+		params_len = strlen(params);
+		populate_request_ctx(&request_ctx, params, params_len, &client->header_capture_ctx);
+
+		ret = ws_detail->cb(ws_sock, &request_ctx, ws_detail->user_data);
 		http_server_release_client(client);
 
-		ret = ws_detail->cb(ws_sock, ws_detail->user_data);
 		if (ret < 0) {
 			NET_DBG("WS connection failed (%d)", ret);
 			websocket_unregister(ws_sock);
diff --git a/subsys/net/lib/lwm2m/Kconfig b/subsys/net/lib/lwm2m/Kconfig
index 8b32ec854f0..206b6d4c380 100644
--- a/subsys/net/lib/lwm2m/Kconfig
+++ b/subsys/net/lib/lwm2m/Kconfig
@@ -161,12 +161,12 @@ endchoice
 
 choice
 	prompt "LwM2M Engine operation mode"
-	default LWM2M_TICKLESS if NET_SOCKETPAIR
-	default LWM2M_INTERVAL if !NET_SOCKETPAIR
+	default LWM2M_TICKLESS if ZVFS_EVENTFD_MAX > 1
+	default LWM2M_INTERVAL
 
 config LWM2M_TICKLESS
 	bool "Tickless operation mode"
-	depends on NET_SOCKETPAIR
+	depends on ZVFS_EVENTFD
 
 config LWM2M_INTERVAL
 	bool "Interval based polling mode"
@@ -273,25 +273,25 @@ config LWM2M_ENGINE_MAX_MESSAGES
 
 config LWM2M_COAP_BLOCK_SIZE
 	int "LWM2M CoAP block-wise transfer size"
-	default 256
+	default 512
 	range 64 1024
 	help
 	  CoAP block size used by LwM2M when performing block-wise
 	  transfers. Possible values: 64, 128, 256, 512 and 1024.
-
-config LWM2M_ENGINE_MESSAGE_HEADER_SIZE
-	int "Room for CoAP header data"
-	default 48
-	range 24 128
-	help
-	  Extra room allocated to handle CoAP header data
+	  When adjusting the value, ensure that LWM2M_COAP_MAX_MSG_SIZE is large enough
+	  to fit all CoAP headers and full block size.
 
 config LWM2M_COAP_MAX_MSG_SIZE
 	int "LWM2M CoAP maximum message size"
-	default LWM2M_COAP_BLOCK_SIZE
-	help
-	  CoAP message size used by LWM2M. Minimum is the block size used
-	  in blockwise transfers.
+	default 1232 if !LWM2M_DTLS_SUPPORT
+	default 1195 if LWM2M_DTLS_SUPPORT && !LWM2M_DTLS_CID
+	default 1187 if LWM2M_DTLS_SUPPORT && LWM2M_DTLS_CID
+	help
+	  CoAP message size used by LWM2M. Default is the maximum
+	  packet size for IPv6 network (MTU(1280)-IPv6(40)-UDP(8)-DTLS(29..53)).
+	  If the network has a smaller MTU, this value should be adjusted accordingly.
+	  If CoAP block-wise transfer is enabled, this value should be larger than
+	  the block size and estimated CoAP header sizes.
 
 config LWM2M_ENGINE_VALIDATION_BUFFER_SIZE
 	int "Size of the validation buffer for the incoming data"
diff --git a/subsys/net/lib/lwm2m/lwm2m_message_handling.c b/subsys/net/lib/lwm2m/lwm2m_message_handling.c
index b04221b188a..1725661fe17 100644
--- a/subsys/net/lib/lwm2m/lwm2m_message_handling.c
+++ b/subsys/net/lib/lwm2m/lwm2m_message_handling.c
@@ -383,6 +383,7 @@ STATIC int build_msg_block_for_send(struct lwm2m_message *msg, uint16_t block_nu
 	ret = buf_append(CPKT_BUF_WRITE(&msg->cpkt),
 			 complete_payload + (block_num * block_size_bytes), payload_size);
 	if (ret < 0) {
+		LOG_ERR("CoAP message size overflow");
 		return ret;
 	}
 
@@ -392,19 +393,16 @@ STATIC int build_msg_block_for_send(struct lwm2m_message *msg, uint16_t block_nu
 STATIC int prepare_msg_for_send(struct lwm2m_message *msg)
 {
 	int ret;
-	uint16_t len;
-	const uint8_t *payload;
-
 	/* save the big buffer for later use (splitting blocks) */
 	msg->body_encode_buffer = msg->cpkt;
 
 	/* set the default (small) buffer for sending blocks */
 	msg->cpkt.data = msg->msg_data;
 	msg->cpkt.offset = 0;
-	msg->cpkt.max_len = MAX_PACKET_SIZE;
+	msg->cpkt.max_len = sizeof(msg->msg_data);
 
-	payload = coap_packet_get_payload(&msg->body_encode_buffer, &len);
-	if (len <= CONFIG_LWM2M_COAP_MAX_MSG_SIZE) {
+	/* Can we fit a whole message into one frame */
+	if (msg->body_encode_buffer.offset <= msg->cpkt.max_len) {
 
 		/* copy the packet */
 		ret = buf_append(CPKT_BUF_WRITE(&msg->cpkt), msg->body_encode_buffer.data,
@@ -422,6 +420,9 @@ STATIC int prepare_msg_for_send(struct lwm2m_message *msg)
 
 		NET_ASSERT(msg->out.block_ctx == NULL, "Expecting to have no context to release");
 	} else {
+		uint16_t len;
+		const uint8_t *payload = coap_packet_get_payload(&msg->body_encode_buffer, &len);
+
 		/* Before splitting the content, append Etag option to protect the integrity of
 		 * the payload.
 		 */
@@ -461,6 +462,9 @@ void lwm2m_engine_context_close(struct lwm2m_ctx *client_ctx)
 
 	for (i = 0, msg = messages; i < ARRAY_SIZE(messages); i++, msg++) {
 		if (msg->ctx == client_ctx) {
+			if (msg->send_status_cb) {
+				msg->send_status_cb(LWM2M_SEND_STATUS_FAILURE);
+			}
 			lwm2m_reset_message(msg, true);
 		}
 	}
@@ -998,6 +1002,7 @@ static int lwm2m_write_handler_opaque(struct lwm2m_engine_obj_inst *obj_inst,
 	struct lwm2m_opaque_context opaque_ctx = {0};
 	void *write_buf;
 	size_t write_buf_len;
+	int written = 0;
 
 	if (msg->in.block_ctx != NULL) {
 		last_block = msg->in.block_ctx->last_block;
@@ -1025,7 +1030,7 @@ static int lwm2m_write_handler_opaque(struct lwm2m_engine_obj_inst *obj_inst,
 		len = engine_get_opaque(&msg->in, write_buf, MIN(data_len, write_buf_len),
 					&opaque_ctx, &last_pkt_block);
 		if (len <= 0) {
-			return len;
+			break;
 		}
 
 #if CONFIG_LWM2M_ENGINE_VALIDATION_BUFFER_SIZE > 0
@@ -1033,7 +1038,7 @@ static int lwm2m_write_handler_opaque(struct lwm2m_engine_obj_inst *obj_inst,
 			ret = res->validate_cb(obj_inst->obj_inst_id, res->res_id,
 					       res_inst->res_inst_id, write_buf, len,
 					       last_pkt_block && last_block, opaque_ctx.len,
-					       msg->in.block_ctx->ctx.current);
+					       opaque_ctx.offset);
 			if (ret < 0) {
 				/* -EEXIST will generate Bad Request LWM2M response. */
 				return -EEXIST;
@@ -1047,7 +1052,7 @@ static int lwm2m_write_handler_opaque(struct lwm2m_engine_obj_inst *obj_inst,
 			ret = res->post_write_cb(
 				obj_inst->obj_inst_id, res->res_id, res_inst->res_inst_id, data_ptr,
 				len, last_pkt_block && last_block, opaque_ctx.len,
-				(msg->in.block_ctx ? msg->in.block_ctx->ctx.current : 0));
+				opaque_ctx.offset);
 			if (ret < 0) {
 				return ret;
 			}
@@ -1055,13 +1060,15 @@ static int lwm2m_write_handler_opaque(struct lwm2m_engine_obj_inst *obj_inst,
 		if (msg->in.block_ctx && !last_pkt_block) {
 			msg->in.block_ctx->ctx.current += len;
 		}
+		opaque_ctx.offset += len;
+		written += len;
 	}
 
 	if (msg->in.block_ctx != NULL) {
 		msg->in.block_ctx->opaque = opaque_ctx;
 	}
 
-	return opaque_ctx.len;
+	return (len < 0 ? len : written);
 }
 /* This function is exposed for the content format writers */
 int lwm2m_write_handler(struct lwm2m_engine_obj_inst *obj_inst, struct lwm2m_engine_res *res,
@@ -1102,7 +1109,7 @@ int lwm2m_write_handler(struct lwm2m_engine_obj_inst *obj_inst, struct lwm2m_eng
 	if (msg->in.block_ctx != NULL) {
 		/* Get block_ctx for total_size (might be zero) */
 		total_size = msg->in.block_ctx->ctx.total_size;
-		offset = msg->in.block_ctx->ctx.current;
+		offset = msg->in.block_ctx->opaque.offset;
 
 		LOG_DBG("BLOCK1: total:%zu current:%zu"
 			" last:%u",
@@ -1160,14 +1167,14 @@ int lwm2m_write_handler(struct lwm2m_engine_obj_inst *obj_inst, struct lwm2m_eng
 				break;
 			}
 
-			if (write_buf_len == sizeof(time_t)) {
+			if (data_len == sizeof(time_t)) {
 				*(time_t *)write_buf = temp_time;
 				len = sizeof(time_t);
-			} else if (write_buf_len == sizeof(uint32_t)) {
+			} else if (data_len == sizeof(uint32_t)) {
 				*(uint32_t *)write_buf = (uint32_t)temp_time;
 				len = sizeof(uint32_t);
 			} else {
-				LOG_ERR("Time resource buf len not supported %zu", write_buf_len);
+				LOG_ERR("Time resource buf len not supported %zu", data_len);
 				ret = -EINVAL;
 			}
 
@@ -1293,6 +1300,10 @@ int lwm2m_write_handler(struct lwm2m_engine_obj_inst *obj_inst, struct lwm2m_eng
 		}
 	}
 
+	if (!res->post_write_cb) {
+		len += offset;
+	}
+
 	res_inst->data_len = len;
 
 	if (LWM2M_HAS_PERM(obj_field, LWM2M_PERM_R)) {
@@ -1396,9 +1407,7 @@ static int lwm2m_read_cached_data(struct lwm2m_message *msg,
 		read_info = &msg->cache_info->read_info[msg->cache_info->entry_size];
 		/* Store original timeseries ring buffer get states for failure handling */
 		read_info->cache_data = cached_data;
-		read_info->original_get_base = cached_data->rb.get_base;
-		read_info->original_get_head = cached_data->rb.get_head;
-		read_info->original_get_tail = cached_data->rb.get_tail;
+		read_info->original_rb_get = cached_data->rb.get;
 		msg->cache_info->entry_size++;
 		if (msg->cache_info->entry_limit) {
 			length = MIN(length, msg->cache_info->entry_limit);
@@ -2775,14 +2784,25 @@ void lwm2m_udp_receive(struct lwm2m_ctx *client_ctx, uint8_t *buf, uint16_t buf_
 			goto client_unlock;
 		}
 
+		bool is_empty = coap_header_get_code(&response) == COAP_CODE_EMPTY;
+		bool was_request = coap_packet_is_request(&msg->cpkt);
+
 		/* If the original message was a request and an empty
 		 * ACK was received, expect separate response later.
 		 */
-		if ((msg->code >= COAP_METHOD_GET) && (msg->code <= COAP_METHOD_DELETE) &&
-		    (coap_header_get_code(&response) == COAP_CODE_EMPTY)) {
+		if (was_request && is_empty) {
 			LOG_DBG("Empty ACK, expect separate response.");
 			goto client_unlock;
 		}
+
+		/* If the original message was a response (like a Notify) and
+		 * empty Ack is received, handle that as a response.
+		 */
+		if (!was_request && is_empty) {
+			msg->reply->reply(&response, msg->reply, from_addr);
+			lwm2m_reset_message(msg, true);
+			goto client_unlock;
+		}
 	}
 
 	reply = coap_response_received(&response, from_addr, client_ctx->replies,
@@ -2912,7 +2932,12 @@ void lwm2m_udp_receive(struct lwm2m_ctx *client_ctx, uint8_t *buf, uint16_t buf_
 		}
 
 		client_ctx->processed_req = NULL;
-		lwm2m_send_message_async(msg);
+		r = lwm2m_send_message_async(msg);
+		if (r < 0) {
+			LOG_ERR("Failed to send response (err: %d)", r);
+			lwm2m_reset_message(msg, true);
+			return;
+		}
 	} else {
 		LOG_DBG("No handler for response");
 	}
@@ -3056,12 +3081,8 @@ static bool lwm2m_timeseries_data_rebuild(struct lwm2m_message *msg, int error_c
 
 	/* Put Ring buffer back to original */
 	for (int i = 0; i < cache_temp->entry_size; i++) {
-		cache_temp->read_info[i].cache_data->rb.get_head =
-			cache_temp->read_info[i].original_get_head;
-		cache_temp->read_info[i].cache_data->rb.get_tail =
-			cache_temp->read_info[i].original_get_tail;
-		cache_temp->read_info[i].cache_data->rb.get_base =
-			cache_temp->read_info[i].original_get_base;
+		cache_temp->read_info[i].cache_data->rb.get =
+			cache_temp->read_info[i].original_rb_get;
 	}
 
 	if (cache_temp->entry_limit) {
@@ -3478,7 +3499,6 @@ static void do_send_timeout_cb(struct lwm2m_message *msg)
 	LOG_WRN("Send Timeout");
 	lwm2m_rd_client_timeout(msg->ctx);
 }
-#endif
 
 #if defined(CONFIG_LWM2M_RESOURCE_DATA_CACHE_SUPPORT)
 static bool init_next_pending_timeseries_data(struct lwm2m_cache_read_info *cache_temp,
@@ -3512,7 +3532,8 @@ static bool init_next_pending_timeseries_data(struct lwm2m_cache_read_info *cach
 	cache_temp->entry_limit = 0;
 	return true;
 }
-#endif
+#endif /* CONFIG_LWM2M_RESOURCE_DATA_CACHE_SUPPORT */
+#endif /* CONFIG_LWM2M_VERSION_1_1 */
 
 int lwm2m_send_cb(struct lwm2m_ctx *ctx, const struct lwm2m_obj_path path_list[],
 			 uint8_t path_list_size, lwm2m_send_cb_t reply_cb)
diff --git a/subsys/net/lib/lwm2m/lwm2m_obj_gateway.c b/subsys/net/lib/lwm2m/lwm2m_obj_gateway.c
index fb82fe6c3f5..40db670d2ba 100644
--- a/subsys/net/lib/lwm2m/lwm2m_obj_gateway.c
+++ b/subsys/net/lib/lwm2m/lwm2m_obj_gateway.c
@@ -159,6 +159,10 @@ int lwm2m_gw_handle_req(struct lwm2m_message *msg)
 		return ret;
 	}
 
+	if (ret == 0) {
+		return -ENOENT;
+	}
+
 	for (int index = 0; index < MAX_INSTANCE_COUNT; index++) {
 		/* Skip uninitialized objects */
 		if (!inst[index].obj) {
diff --git a/subsys/net/lib/lwm2m/lwm2m_object.h b/subsys/net/lib/lwm2m/lwm2m_object.h
index 26322f50b1b..79a63f43ce8 100644
--- a/subsys/net/lib/lwm2m/lwm2m_object.h
+++ b/subsys/net/lib/lwm2m/lwm2m_object.h
@@ -131,15 +131,12 @@
 
 BUILD_ASSERT(CONFIG_LWM2M_COAP_BLOCK_SIZE <= CONFIG_LWM2M_COAP_MAX_MSG_SIZE,
 	     "CoAP block size can't exceed maximum message size");
-
-#define MAX_PACKET_SIZE		(CONFIG_LWM2M_COAP_MAX_MSG_SIZE + \
-				 CONFIG_LWM2M_ENGINE_MESSAGE_HEADER_SIZE)
-
-#if defined(CONFIG_LWM2M_COAP_BLOCK_TRANSFER)
-BUILD_ASSERT(CONFIG_LWM2M_COAP_ENCODE_BUFFER_SIZE >
-		     (CONFIG_LWM2M_COAP_BLOCK_SIZE + CONFIG_LWM2M_ENGINE_MESSAGE_HEADER_SIZE),
-	     "The buffer for serializing message needs to be bigger than a message with one block");
-#endif
+BUILD_ASSERT(CONFIG_LWM2M_COAP_BLOCK_SIZE == 64 ||
+	     CONFIG_LWM2M_COAP_BLOCK_SIZE == 128 ||
+	     CONFIG_LWM2M_COAP_BLOCK_SIZE == 256 ||
+	     CONFIG_LWM2M_COAP_BLOCK_SIZE == 512 ||
+	     CONFIG_LWM2M_COAP_BLOCK_SIZE == 1024,
+	     "CoAP block must be 64, 128, 256, 512 or 1024");
 
 /* buffer util macros */
 #define CPKT_BUF_WRITE(cpkt)	(cpkt)->data, &(cpkt)->offset, (cpkt)->max_len
@@ -434,7 +431,7 @@ static inline void init_res_instance(struct lwm2m_engine_res_inst *ri,
 
 struct lwm2m_opaque_context {
 	size_t len;
-	size_t remaining;
+	size_t offset;
 };
 
 struct lwm2m_block_context {
@@ -494,7 +491,7 @@ struct lwm2m_message {
 	struct coap_packet cpkt;
 
 	/** Buffer data related outgoing message */
-	uint8_t msg_data[MAX_PACKET_SIZE];
+	uint8_t msg_data[CONFIG_LWM2M_COAP_MAX_MSG_SIZE];
 
 #if defined(CONFIG_LWM2M_COAP_BLOCK_TRANSFER)
 	/** Buffer data containing complete message */
diff --git a/subsys/net/lib/lwm2m/lwm2m_pull_context.c b/subsys/net/lib/lwm2m/lwm2m_pull_context.c
index 8081c3793ed..a8efd933a54 100644
--- a/subsys/net/lib/lwm2m/lwm2m_pull_context.c
+++ b/subsys/net/lib/lwm2m/lwm2m_pull_context.c
@@ -311,7 +311,7 @@ static int do_firmware_transfer_reply_cb(const struct coap_packet *response,
 		}
 
 		if (context.write_cb) {
-			size_t offset = context.block_ctx.current;
+			size_t offset = received_block_ctx.current;
 
 			/* flush incoming data to write_cb */
 			while (payload_len > 0) {
diff --git a/subsys/net/lib/lwm2m/lwm2m_rd_client.c b/subsys/net/lib/lwm2m/lwm2m_rd_client.c
index 1db25c598fe..8054340281f 100644
--- a/subsys/net/lib/lwm2m/lwm2m_rd_client.c
+++ b/subsys/net/lib/lwm2m/lwm2m_rd_client.c
@@ -785,7 +785,11 @@ static int sm_send_bootstrap_registration(void)
 	LOG_DBG("Register ID with bootstrap server as '%s'",
 		query_buffer);
 
-	lwm2m_send_message_async(msg);
+	ret = lwm2m_send_message_async(msg);
+	if (ret < 0) {
+		LOG_ERR("Failed to send bootstrap message (err: %d)", ret);
+		goto cleanup;
+	}
 
 	return 0;
 
@@ -834,10 +838,14 @@ static void sm_do_bootstrap_reg(void)
 void engine_bootstrap_finish(void)
 {
 	LOG_INF("Bootstrap data transfer done!");
-	/* Delay the state transition, so engine have some time to send ACK
-	 * before we close the socket
+	/* Transition only if the client is bootstrapping, otherwise retransmissions of bootstrap
+	 * finish may restart an already registered client.
+	 * Delay the state transition, so engine have some time to send ACK before we close the
+	 * socket.
 	 */
-	set_sm_state_delayed(ENGINE_BOOTSTRAP_TRANS_DONE, DELAY_BEFORE_CLOSING);
+	if (get_sm_state() == ENGINE_BOOTSTRAP_REG_DONE) {
+		set_sm_state_delayed(ENGINE_BOOTSTRAP_TRANS_DONE, DELAY_BEFORE_CLOSING);
+	}
 }
 
 static int sm_bootstrap_trans_done(void)
@@ -987,7 +995,10 @@ static int sm_send_registration(bool send_obj_support_data,
 		}
 	}
 
-	lwm2m_send_message_async(msg);
+	ret = lwm2m_send_message_async(msg);
+	if (ret < 0) {
+		goto cleanup;
+	}
 
 	/* log the registration attempt */
 	LOG_DBG("registration sent [%s]",
@@ -1259,7 +1270,11 @@ static int sm_do_deregister(void)
 
 	LOG_INF("Deregister from '%s'", client.server_ep);
 
-	lwm2m_send_message_async(msg);
+	ret = lwm2m_send_message_async(msg);
+	if (ret < 0) {
+		LOG_ERR("Failed to send deregistration message (err:%d).", ret);
+		goto cleanup;
+	}
 
 	set_sm_state(ENGINE_DEREGISTER_SENT);
 	return 0;
diff --git a/subsys/net/lib/lwm2m/lwm2m_registry.c b/subsys/net/lib/lwm2m/lwm2m_registry.c
index be7b49212ee..5f94e4bbd97 100644
--- a/subsys/net/lib/lwm2m/lwm2m_registry.c
+++ b/subsys/net/lib/lwm2m/lwm2m_registry.c
@@ -1089,7 +1089,7 @@ int lwm2m_get_resource(const struct lwm2m_obj_path *path, struct lwm2m_engine_re
 size_t lwm2m_engine_get_opaque_more(struct lwm2m_input_context *in, uint8_t *buf, size_t buflen,
 				    struct lwm2m_opaque_context *opaque, bool *last_block)
 {
-	uint32_t in_len = opaque->remaining;
+	uint32_t in_len = opaque->len - opaque->offset;
 	uint16_t remaining = in->in_cpkt->max_len - in->offset;
 
 	if (in_len > buflen) {
@@ -1100,9 +1100,8 @@ size_t lwm2m_engine_get_opaque_more(struct lwm2m_input_context *in, uint8_t *buf
 		in_len = remaining;
 	}
 
-	opaque->remaining -= in_len;
 	remaining -= in_len;
-	if (opaque->remaining == 0U || remaining == 0) {
+	if (opaque->offset + in_len >= opaque->len) {
 		*last_block = true;
 	}
 
@@ -1724,13 +1723,11 @@ size_t lwm2m_cache_size(const struct lwm2m_time_series_resource *cache_entry)
 #if defined(CONFIG_LWM2M_RESOURCE_DATA_CACHE_SUPPORT)
 	uint32_t bytes_available;
 
-	/* ring_buf_is_empty() takes non-const pointer but still does not modify */
-	if (ring_buf_is_empty((struct ring_buf *) &cache_entry->rb)) {
+	if (ring_buf_is_empty(&cache_entry->rb)) {
 		return 0;
 	}
 
-	/* ring_buf_size_get() takes non-const pointer but still does not modify */
-	bytes_available = ring_buf_size_get((struct ring_buf *) &cache_entry->rb);
+	bytes_available = ring_buf_size_get(&cache_entry->rb);
 
 	return (bytes_available / sizeof(struct lwm2m_time_series_elem));
 #else
diff --git a/subsys/net/lib/lwm2m/lwm2m_registry.h b/subsys/net/lib/lwm2m/lwm2m_registry.h
index 3489c0c3fc8..6c876551bf5 100644
--- a/subsys/net/lib/lwm2m/lwm2m_registry.h
+++ b/subsys/net/lib/lwm2m/lwm2m_registry.h
@@ -219,9 +219,7 @@ struct lwm2m_time_series_resource {
 
 struct lwm2m_cache_read_entry {
 	struct lwm2m_time_series_resource *cache_data;
-	int32_t original_get_head;
-	int32_t original_get_tail;
-	int32_t original_get_base;
+	struct ring_buf_index original_rb_get;
 };
 
 struct lwm2m_cache_read_info {
diff --git a/subsys/net/lib/lwm2m/lwm2m_rw_cbor.c b/subsys/net/lib/lwm2m/lwm2m_rw_cbor.c
index ef009162ca0..4627d68ed21 100644
--- a/subsys/net/lib/lwm2m/lwm2m_rw_cbor.c
+++ b/subsys/net/lib/lwm2m/lwm2m_rw_cbor.c
@@ -237,6 +237,8 @@ static int get_s64(struct lwm2m_input_context *in, int64_t *value)
 {
 	ZCBOR_STATE_D(states, 0, ICTX_BUF_R_PTR(in), ICTX_BUF_R_LEFT_SZ(in),  1, 0);
 
+	states->constant_state->enforce_canonical = false;
+
 	if (!zcbor_int64_decode(states, value)) {
 		LOG_WRN("unable to decode a 64-bit integer value");
 		return -EBADMSG;
@@ -253,6 +255,8 @@ static int get_s32(struct lwm2m_input_context *in, int32_t *value)
 {
 	ZCBOR_STATE_D(states, 0, ICTX_BUF_R_PTR(in), ICTX_BUF_R_LEFT_SZ(in),  1, 0);
 
+	states->constant_state->enforce_canonical = false;
+
 	if (!zcbor_int32_decode(states, value)) {
 		LOG_WRN("unable to decode a 32-bit integer value, err: %d",
 				states->constant_state->error);
@@ -270,6 +274,8 @@ static int get_float(struct lwm2m_input_context *in, double *value)
 {
 	ZCBOR_STATE_D(states, 0, ICTX_BUF_R_PTR(in), ICTX_BUF_R_LEFT_SZ(in),  1, 0);
 
+	states->constant_state->enforce_canonical = false;
+
 	if (!zcbor_float_decode(states, value)) {
 		LOG_ERR("unable to decode a floating-point value");
 		return -EBADMSG;
@@ -289,6 +295,8 @@ static int get_string(struct lwm2m_input_context *in, uint8_t *value, size_t buf
 
 	ZCBOR_STATE_D(states, 0, ICTX_BUF_R_PTR(in), ICTX_BUF_R_LEFT_SZ(in),  1, 0);
 
+	states->constant_state->enforce_canonical = false;
+
 	if (!zcbor_tstr_decode(states, &hndl)) {
 		LOG_WRN("unable to decode a string");
 		return -EBADMSG;
@@ -318,6 +326,8 @@ static int get_time_string(struct lwm2m_input_context *in, int64_t *value)
 
 	ZCBOR_STATE_D(states, 0, ICTX_BUF_R_PTR(in), ICTX_BUF_R_LEFT_SZ(in),  1, 0);
 
+	states->constant_state->enforce_canonical = false;
+
 	if (!zcbor_tstr_decode(states, &hndl)) {
 		return -EBADMSG;
 	}
@@ -336,6 +346,8 @@ static int get_time_numerical(struct lwm2m_input_context *in, int64_t *value)
 {
 	ZCBOR_STATE_D(states, 0, ICTX_BUF_R_PTR(in), ICTX_BUF_R_LEFT_SZ(in),  1, 0);
 
+	states->constant_state->enforce_canonical = false;
+
 	if (!zcbor_int64_decode(states, value)) {
 		LOG_WRN("unable to decode seconds since Epoch");
 		return -EBADMSG;
@@ -355,6 +367,8 @@ static int get_time(struct lwm2m_input_context *in, time_t *value)
 
 	ZCBOR_STATE_D(states, 0, ICTX_BUF_R_PTR(in), ICTX_BUF_R_LEFT_SZ(in),  1, 0);
 
+	states->constant_state->enforce_canonical = false;
+
 	success = zcbor_tag_decode(states, &tag);
 
 	if (success) {
@@ -405,6 +419,8 @@ static int get_bool(struct lwm2m_input_context *in, bool *value)
 {
 	ZCBOR_STATE_D(states, 0, ICTX_BUF_R_PTR(in), ICTX_BUF_R_LEFT_SZ(in),  1, 0);
 
+	states->constant_state->enforce_canonical = false;
+
 	if (!zcbor_bool_decode(states, value)) {
 		LOG_WRN("unable to decode a boolean value");
 		return -EBADMSG;
@@ -425,8 +441,10 @@ static int get_opaque(struct lwm2m_input_context *in, uint8_t *value, size_t buf
 
 	ZCBOR_STATE_D(states, 1, ICTX_BUF_R_PTR(in), ICTX_BUF_R_LEFT_SZ(in),  1, 0);
 
+	states->constant_state->enforce_canonical = false;
+
 	/* Get the CBOR header only on first read. */
-	if (opaque->remaining == 0) {
+	if (opaque->offset == 0) {
 		ret = zcbor_bstr_start_decode_fragment(states, &hndl);
 
 		if (!ret) {
@@ -435,7 +453,6 @@ static int get_opaque(struct lwm2m_input_context *in, uint8_t *value, size_t buf
 		}
 
 		opaque->len = hndl.total_len;
-		opaque->remaining = hndl.total_len;
 
 		int len = ICTX_CBOR_R_SZ(states[0].payload, in);
 
diff --git a/subsys/net/lib/lwm2m/lwm2m_rw_oma_tlv.c b/subsys/net/lib/lwm2m/lwm2m_rw_oma_tlv.c
index 661c26b4d47..c93671612b3 100644
--- a/subsys/net/lib/lwm2m/lwm2m_rw_oma_tlv.c
+++ b/subsys/net/lib/lwm2m/lwm2m_rw_oma_tlv.c
@@ -745,14 +745,13 @@ static int get_opaque(struct lwm2m_input_context *in, uint8_t *value,
 	int size;
 
 	/* Get the TLV header only on first read. */
-	if (opaque->remaining == 0) {
+	if (opaque->offset == 0) {
 		size = oma_tlv_get(&tlv, in, false);
 		if (size < 0) {
 			return size;
 		}
 
 		opaque->len = tlv.length;
-		opaque->remaining = tlv.length;
 	}
 
 	return lwm2m_engine_get_opaque_more(in, value, buflen,
diff --git a/subsys/net/lib/lwm2m/lwm2m_rw_opaque.c b/subsys/net/lib/lwm2m/lwm2m_rw_opaque.c
index 90cb4619d9a..505d7113e4b 100644
--- a/subsys/net/lib/lwm2m/lwm2m_rw_opaque.c
+++ b/subsys/net/lib/lwm2m/lwm2m_rw_opaque.c
@@ -57,7 +57,7 @@ static int get_opaque(struct lwm2m_input_context *in, uint8_t *value,
 {
 	uint16_t in_len;
 
-	if (opaque->remaining == 0) {
+	if (opaque->offset == 0) {
 		coap_packet_get_payload(in->in_cpkt, &in_len);
 
 		if (in_len == 0) {
@@ -79,14 +79,10 @@ static int get_opaque(struct lwm2m_input_context *in, uint8_t *value,
 				 * payload size. This will reset on next packet
 				 * received.
 				 */
-				opaque->remaining = in_len;
-			} else {
-				opaque->remaining = opaque->len;
+				opaque->len = in_len;
 			}
-
 		} else {
 			opaque->len = in_len;
-			opaque->remaining = in_len;
 		}
 	}
 
diff --git a/subsys/net/lib/lwm2m/lwm2m_rw_senml_cbor.c b/subsys/net/lib/lwm2m/lwm2m_rw_senml_cbor.c
index 2429c60864f..65f6cbcc6ef 100644
--- a/subsys/net/lib/lwm2m/lwm2m_rw_senml_cbor.c
+++ b/subsys/net/lib/lwm2m/lwm2m_rw_senml_cbor.c
@@ -541,7 +541,7 @@ static int get_opaque(struct lwm2m_input_context *in,
 	uint8_t *dest = NULL;
 
 	/* Get the CBOR header only on first read. */
-	if (opaque->remaining == 0) {
+	if (opaque->offset == 0) {
 
 		fd = engine_get_in_user_data(in);
 		if (!fd || !fd->current) {
diff --git a/subsys/net/lib/lwm2m/lwm2m_rw_senml_json.c b/subsys/net/lib/lwm2m/lwm2m_rw_senml_json.c
index 6d2bb2b96b6..6700304f68b 100644
--- a/subsys/net/lib/lwm2m/lwm2m_rw_senml_json.c
+++ b/subsys/net/lib/lwm2m/lwm2m_rw_senml_json.c
@@ -1233,7 +1233,7 @@ static int get_opaque(struct lwm2m_input_context *in, uint8_t *value, size_t buf
 	/* Decode from url safe to normal */
 	base64_url_safe_decode(data_ptr, val_opaque->length);
 
-	if (opaque->remaining == 0) {
+	if (opaque->offset == 0) {
 		size_t original_size = val_opaque->length;
 		size_t base64_length;
 
@@ -1260,10 +1260,9 @@ static int get_opaque(struct lwm2m_input_context *in, uint8_t *value, size_t buf
 			val_opaque->length += buffer_base64_length;
 		}
 		opaque->len = val_opaque->length;
-		opaque->remaining = val_opaque->length;
 	}
 
-	in_len = opaque->remaining;
+	in_len = opaque->len - opaque->offset;
 
 	if (in_len > buflen) {
 		in_len = buflen;
@@ -1273,8 +1272,7 @@ static int get_opaque(struct lwm2m_input_context *in, uint8_t *value, size_t buf
 		in_len = val_opaque->length;
 	}
 
-	opaque->remaining -= in_len;
-	if (opaque->remaining == 0U) {
+	if (opaque->offset + in_len >= opaque->len) {
 		*last_block = true;
 	}
 	/* Copy data to buffer */
diff --git a/subsys/net/lib/lwm2m/lwm2m_senml_cbor_decode.c b/subsys/net/lib/lwm2m/lwm2m_senml_cbor_decode.c
index 335c8dfbb1f..10be0e8eb0c 100644
--- a/subsys/net/lib/lwm2m/lwm2m_senml_cbor_decode.c
+++ b/subsys/net/lib/lwm2m/lwm2m_senml_cbor_decode.c
@@ -212,6 +212,8 @@ static bool decode_lwm2m_senml(zcbor_state_t *state, struct lwm2m_senml *result)
 {
 	zcbor_log("%s\r\n", __func__);
 
+	state->constant_state->enforce_canonical = false;
+
 	bool res =
 		(((zcbor_list_start_decode(state) &&
 		   ((zcbor_multi_decode(
diff --git a/subsys/net/lib/mqtt_sn/mqtt_sn.c b/subsys/net/lib/mqtt_sn/mqtt_sn.c
index 3d6789b3d23..1c0d2b89055 100644
--- a/subsys/net/lib/mqtt_sn/mqtt_sn.c
+++ b/subsys/net/lib/mqtt_sn/mqtt_sn.c
@@ -21,6 +21,10 @@ LOG_MODULE_REGISTER(net_mqtt_sn, CONFIG_MQTT_SN_LOG_LEVEL);
 NET_BUF_POOL_FIXED_DEFINE(mqtt_sn_messages, MQTT_SN_NET_BUFS, CONFIG_MQTT_SN_LIB_MAX_PAYLOAD_SIZE,
 			  0, NULL);
 
+/**
+ * A struct to track attempts for actions that require acknowledgment,
+ * i.e. topic registering, subscribing, or unsubscribing.
+ */
 struct mqtt_sn_confirmable {
 	int64_t last_attempt;
 	uint16_t msg_id;
@@ -38,11 +42,14 @@ struct mqtt_sn_publish {
 };
 
 enum mqtt_sn_topic_state {
-	MQTT_SN_TOPIC_STATE_REGISTERING,
-	MQTT_SN_TOPIC_STATE_REGISTERED,
-	MQTT_SN_TOPIC_STATE_SUBSCRIBING,
-	MQTT_SN_TOPIC_STATE_SUBSCRIBED,
-	MQTT_SN_TOPIC_STATE_UNSUBSCRIBING,
+	MQTT_SN_TOPIC_STATE_REGISTER,      /*!< Topic requested to be registered */
+	MQTT_SN_TOPIC_STATE_REGISTERING,   /*!< Topic in progress of registering */
+	MQTT_SN_TOPIC_STATE_REGISTERED,    /*!< Topic registered */
+	MQTT_SN_TOPIC_STATE_SUBSCRIBE,     /*!< Topic requested to subscribe */
+	MQTT_SN_TOPIC_STATE_SUBSCRIBING,   /*!< Topic in progress of subscribing */
+	MQTT_SN_TOPIC_STATE_SUBSCRIBED,    /*!< Topic subscribed */
+	MQTT_SN_TOPIC_STATE_UNSUBSCRIBE,   /*!< Topic requested to unsubscribe */
+	MQTT_SN_TOPIC_STATE_UNSUBSCRIBING, /*!< Topic in progress of unsubscribing */
 };
 
 struct mqtt_sn_topic {
@@ -197,8 +204,8 @@ static struct mqtt_sn_publish *mqtt_sn_publish_create(struct mqtt_sn_data *data)
 	return pub;
 }
 
-static struct mqtt_sn_publish *mqtt_sn_publish_find_msg_id(struct mqtt_sn_client *client,
-							   uint16_t msg_id)
+static struct mqtt_sn_publish *mqtt_sn_publish_find_by_msg_id(struct mqtt_sn_client *client,
+							      uint16_t msg_id)
 {
 	struct mqtt_sn_publish *pub;
 
@@ -211,8 +218,8 @@ static struct mqtt_sn_publish *mqtt_sn_publish_find_msg_id(struct mqtt_sn_client
 	return NULL;
 }
 
-static struct mqtt_sn_publish *mqtt_sn_publish_find_topic(struct mqtt_sn_client *client,
-							  struct mqtt_sn_topic *topic)
+static struct mqtt_sn_publish *mqtt_sn_publish_find_by_topic(struct mqtt_sn_client *client,
+							     struct mqtt_sn_topic *topic)
 {
 	struct mqtt_sn_publish *pub;
 
@@ -254,8 +261,8 @@ static struct mqtt_sn_topic *mqtt_sn_topic_create(struct mqtt_sn_data *name)
 	return topic;
 }
 
-static struct mqtt_sn_topic *mqtt_sn_topic_find_name(struct mqtt_sn_client *client,
-						     struct mqtt_sn_data *topic_name)
+static struct mqtt_sn_topic *mqtt_sn_topic_find_by_name(struct mqtt_sn_client *client,
+							struct mqtt_sn_data *topic_name)
 {
 	struct mqtt_sn_topic *topic;
 
@@ -269,8 +276,8 @@ static struct mqtt_sn_topic *mqtt_sn_topic_find_name(struct mqtt_sn_client *clie
 	return NULL;
 }
 
-static struct mqtt_sn_topic *mqtt_sn_topic_find_msg_id(struct mqtt_sn_client *client,
-						       uint16_t msg_id)
+static struct mqtt_sn_topic *mqtt_sn_topic_find_by_msg_id(struct mqtt_sn_client *client,
+							  uint16_t msg_id)
 {
 	struct mqtt_sn_topic *topic;
 
@@ -288,7 +295,7 @@ static void mqtt_sn_topic_destroy(struct mqtt_sn_client *client, struct mqtt_sn_
 	struct mqtt_sn_publish *pub;
 
 	/* Destroy all pubs referencing this topic */
-	while ((pub = mqtt_sn_publish_find_topic(client, topic)) != NULL) {
+	while ((pub = mqtt_sn_publish_find_by_topic(client, topic)) != NULL) {
 		LOG_WRN("Destroying publish msg_id %d", pub->con.msg_id);
 		mqtt_sn_publish_destroy(client, pub);
 	}
@@ -305,7 +312,7 @@ static void mqtt_sn_topic_destroy_all(struct mqtt_sn_client *client)
 	while ((next = sys_slist_get(&client->topic)) != NULL) {
 		topic = SYS_SLIST_CONTAINER(next, topic, next);
 		/* Destroy all pubs referencing this topic */
-		while ((pub = mqtt_sn_publish_find_topic(client, topic)) != NULL) {
+		while ((pub = mqtt_sn_publish_find_by_topic(client, topic)) != NULL) {
 			LOG_WRN("Destroying publish msg_id %d", pub->con.msg_id);
 			mqtt_sn_publish_destroy(client, pub);
 		}
@@ -361,7 +368,7 @@ static struct mqtt_sn_gateway *mqtt_sn_gw_create(uint8_t gw_id, short duration,
 	return gw;
 }
 
-static struct mqtt_sn_gateway *mqtt_sn_gw_find_id(struct mqtt_sn_client *client, uint16_t gw_id)
+static struct mqtt_sn_gateway *mqtt_sn_gw_find_by_id(struct mqtt_sn_client *client, uint16_t gw_id)
 {
 	struct mqtt_sn_gateway *gw;
 
@@ -403,6 +410,13 @@ static void mqtt_sn_sleep_internal(struct mqtt_sn_client *client)
 	}
 }
 
+/**
+ * @brief Internal function to send a SUBSCRIBE message for a topic.
+ *
+ * @param client
+ * @param topic
+ * @param dup DUP flag - see MQTT-SN spec
+ */
 static void mqtt_sn_do_subscribe(struct mqtt_sn_client *client, struct mqtt_sn_topic *topic,
 				 bool dup)
 {
@@ -438,6 +452,12 @@ static void mqtt_sn_do_subscribe(struct mqtt_sn_client *client, struct mqtt_sn_t
 	encode_and_send(client, &p, 0);
 }
 
+/**
+ * @brief Internal function to send an UNSUBSCRIBE message for a topic.
+ *
+ * @param client
+ * @param topic
+ */
 static void mqtt_sn_do_unsubscribe(struct mqtt_sn_client *client, struct mqtt_sn_topic *topic)
 {
 	struct mqtt_sn_param p = {.type = MQTT_SN_MSG_TYPE_UNSUBSCRIBE};
@@ -470,6 +490,12 @@ static void mqtt_sn_do_unsubscribe(struct mqtt_sn_client *client, struct mqtt_sn
 	encode_and_send(client, &p, 0);
 }
 
+/**
+ * @brief Internal function to a register a topic with the MQTT-SN gateway.
+ *
+ * @param client
+ * @param topic
+ */
 static void mqtt_sn_do_register(struct mqtt_sn_client *client, struct mqtt_sn_topic *topic)
 {
 	struct mqtt_sn_param p = {.type = MQTT_SN_MSG_TYPE_REGISTER};
@@ -498,6 +524,15 @@ static void mqtt_sn_do_register(struct mqtt_sn_client *client, struct mqtt_sn_to
 	encode_and_send(client, &p, 0);
 }
 
+/**
+ * @brief Internal function to send a PUBLISH message.
+ *
+ * Note that this function does not do sanity checks regarding the pub's topic.
+ *
+ * @param client
+ * @param pub
+ * @param dup DUP flag - see MQTT-SN spec.
+ */
 static void mqtt_sn_do_publish(struct mqtt_sn_client *client, struct mqtt_sn_publish *pub, bool dup)
 {
 	struct mqtt_sn_param p = {.type = MQTT_SN_MSG_TYPE_PUBLISH};
@@ -525,6 +560,11 @@ static void mqtt_sn_do_publish(struct mqtt_sn_client *client, struct mqtt_sn_pub
 	encode_and_send(client, &p, 0);
 }
 
+/**
+ * @brief Internal function to send a SEARCHGW message.
+ *
+ * @param client
+ */
 static void mqtt_sn_do_searchgw(struct mqtt_sn_client *client)
 {
 	struct mqtt_sn_param p = {.type = MQTT_SN_MSG_TYPE_SEARCHGW};
@@ -534,6 +574,11 @@ static void mqtt_sn_do_searchgw(struct mqtt_sn_client *client)
 	encode_and_send(client, &p, CONFIG_MQTT_SN_LIB_BROADCAST_RADIUS);
 }
 
+/**
+ * @brief Internal function to send a GWINFO message.
+ *
+ * @param client
+ */
 static void mqtt_sn_do_gwinfo(struct mqtt_sn_client *client)
 {
 	struct mqtt_sn_param response = {.type = MQTT_SN_MSG_TYPE_GWINFO};
@@ -555,6 +600,11 @@ static void mqtt_sn_do_gwinfo(struct mqtt_sn_client *client)
 	encode_and_send(client, &response, client->radius_gwinfo);
 }
 
+/**
+ * @brief Internal function to send a PINGREQ message.
+ *
+ * @param client
+ */
 static void mqtt_sn_do_ping(struct mqtt_sn_client *client)
 {
 	struct mqtt_sn_param p = {.type = MQTT_SN_MSG_TYPE_PINGREQ};
@@ -579,12 +629,21 @@ static void mqtt_sn_do_ping(struct mqtt_sn_client *client)
 	}
 }
 
+/**
+ * @brief Process all publish tasks in the queue.
+ *
+ * @param client
+ * @param next_cycle will be set to the time when the next action is required
+ *
+ * @retval 0 on success
+ * @retval -ETIMEDOUT when a publish task ran out of retries
+ */
 static int process_pubs(struct mqtt_sn_client *client, int64_t *next_cycle)
 {
 	struct mqtt_sn_publish *pub, *pubs;
 	const int64_t now = k_uptime_get();
 	int64_t next_attempt;
-	bool dup;
+	bool dup; /* dup flag if message is resent */
 
 	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&client->publish, pub, pubs, next) {
 		LOG_HEXDUMP_DBG(pub->topic->name, pub->topic->namelen,
@@ -599,13 +658,9 @@ static int process_pubs(struct mqtt_sn_client *client, int64_t *next_cycle)
 			dup = true;
 		}
 
+		/* Check if action is due */
 		if (next_attempt <= now) {
 			switch (pub->topic->state) {
-			case MQTT_SN_TOPIC_STATE_REGISTERING:
-			case MQTT_SN_TOPIC_STATE_SUBSCRIBING:
-			case MQTT_SN_TOPIC_STATE_UNSUBSCRIBING:
-				LOG_INF("Can't publish; topic is not ready");
-				break;
 			case MQTT_SN_TOPIC_STATE_REGISTERED:
 			case MQTT_SN_TOPIC_STATE_SUBSCRIBED:
 				if (!pub->con.retries--) {
@@ -624,9 +679,13 @@ static int process_pubs(struct mqtt_sn_client *client, int64_t *next_cycle)
 					next_attempt = now + T_RETRY_MSEC;
 				}
 				break;
+			default:
+				LOG_INF("Can't publish; topic is not ready");
+				break;
 			}
 		}
 
+		/* Remember time when next action is due */
 		if (next_attempt > now && (*next_cycle == 0 || next_attempt < *next_cycle)) {
 			*next_cycle = next_attempt;
 		}
@@ -637,13 +696,42 @@ static int process_pubs(struct mqtt_sn_client *client, int64_t *next_cycle)
 	return 0;
 }
 
+/**
+ * @brief Process all topic tasks in the queue.
+ *
+ * @param client
+ * @param next_cycle will be set to the time when the next action is required
+ *
+ * @retval 0 on success
+ * @retval -ETIMEDOUT when a publish task ran out of retries
+ */
 static int process_topics(struct mqtt_sn_client *client, int64_t *next_cycle)
 {
 	struct mqtt_sn_topic *topic;
 	const int64_t now = k_uptime_get();
 	int64_t next_attempt;
-	bool dup;
 
+	bool subscribing = false;
+	bool registering = false;
+
+	bool dup; /* dup flag if message is resent */
+
+	/* First pass to check for REGISTERING, SUBSCRIBING, UNSUBSCRIBING */
+	SYS_SLIST_FOR_EACH_CONTAINER(&client->topic, topic, next) {
+		switch (topic->state) {
+		case MQTT_SN_TOPIC_STATE_UNSUBSCRIBING:
+		case MQTT_SN_TOPIC_STATE_SUBSCRIBING:
+			subscribing = true;
+			break;
+		case MQTT_SN_TOPIC_STATE_REGISTERING:
+			registering = true;
+			break;
+		default:
+			break;
+		}
+	}
+
+	/* Second pass */
 	SYS_SLIST_FOR_EACH_CONTAINER(&client->topic, topic, next) {
 		LOG_HEXDUMP_DBG(topic->name, topic->namelen, "Processing topic");
 
@@ -655,9 +743,22 @@ static int process_topics(struct mqtt_sn_client *client, int64_t *next_cycle)
 			dup = true;
 		}
 
+		/* Check if action is due */
 		if (next_attempt <= now) {
 			switch (topic->state) {
+			case MQTT_SN_TOPIC_STATE_SUBSCRIBE:
+				if (subscribing) {
+					/*
+					 * Only one topic can be subscribing or unsubscribing
+					 * at the same time
+					 */
+					break;
+				}
+				topic->state = MQTT_SN_TOPIC_STATE_SUBSCRIBING;
+				LOG_INF("Topic subscription now in progress");
+				__fallthrough;
 			case MQTT_SN_TOPIC_STATE_SUBSCRIBING:
+				subscribing = true;
 				if (!topic->con.retries--) {
 					LOG_WRN("Topic ran out of retries, disconnecting");
 					mqtt_sn_disconnect_internal(client);
@@ -668,7 +769,16 @@ static int process_topics(struct mqtt_sn_client *client, int64_t *next_cycle)
 				topic->con.last_attempt = now;
 				next_attempt = now + T_RETRY_MSEC;
 				break;
+			case MQTT_SN_TOPIC_STATE_REGISTER:
+				if (registering) {
+					/* Only one topic can be registering at the same time */
+					break;
+				}
+				topic->state = MQTT_SN_TOPIC_STATE_REGISTERING;
+				LOG_INF("Topic registration now in progress");
+				__fallthrough;
 			case MQTT_SN_TOPIC_STATE_REGISTERING:
+				registering = true;
 				if (!topic->con.retries--) {
 					LOG_WRN("Topic ran out of retries, disconnecting");
 					mqtt_sn_disconnect_internal(client);
@@ -679,7 +789,19 @@ static int process_topics(struct mqtt_sn_client *client, int64_t *next_cycle)
 				topic->con.last_attempt = now;
 				next_attempt = now + T_RETRY_MSEC;
 				break;
+			case MQTT_SN_TOPIC_STATE_UNSUBSCRIBE:
+				if (subscribing) {
+					/*
+					 * Only one topic can be subscribing or unsubscribing
+					 * at the same time
+					 */
+					break;
+				}
+				topic->state = MQTT_SN_TOPIC_STATE_UNSUBSCRIBING;
+				LOG_INF("Topic unsubscription now in progress");
+				__fallthrough;
 			case MQTT_SN_TOPIC_STATE_UNSUBSCRIBING:
+				subscribing = true;
 				if (!topic->con.retries--) {
 					LOG_WRN("Topic ran out of retries, disconnecting");
 					mqtt_sn_disconnect_internal(client);
@@ -695,6 +817,7 @@ static int process_topics(struct mqtt_sn_client *client, int64_t *next_cycle)
 			}
 		}
 
+		/* Remember time when next action is due */
 		if (next_attempt > now && (*next_cycle == 0 || next_attempt < *next_cycle)) {
 			*next_cycle = next_attempt;
 		}
@@ -705,6 +828,14 @@ static int process_topics(struct mqtt_sn_client *client, int64_t *next_cycle)
 	return 0;
 }
 
+/**
+ * @brief Housekeeping task for the client ping
+ *
+ * @param client
+ * @param next_cycle will be set to the time when the next action is required
+ * @retval 0 on success
+ * @retval -ETIMEDOUT if client ran out of ping retries
+ */
 static int process_ping(struct mqtt_sn_client *client, int64_t *next_cycle)
 {
 	const int64_t now = k_uptime_get();
@@ -743,6 +874,13 @@ static int process_ping(struct mqtt_sn_client *client, int64_t *next_cycle)
 	return 0;
 }
 
+/**
+ * @brief Housekeeping task for the gateway search
+ *
+ * @param client
+ * @param next_cycle will be set to the time when the next action is required
+ * @retval 0 on success
+ */
 static int process_search(struct mqtt_sn_client *client, int64_t *next_cycle)
 {
 	const int64_t now = k_uptime_get();
@@ -774,6 +912,13 @@ static int process_search(struct mqtt_sn_client *client, int64_t *next_cycle)
 	return 0;
 }
 
+/**
+ * @brief Housekeeping task for gateway advertisements
+ *
+ * @param client
+ * @param next_cycle will be set to the time when the next action is required
+ * @return int
+ */
 static int process_advertise(struct mqtt_sn_client *client, int64_t *next_cycle)
 {
 	const int64_t now = k_uptime_get();
@@ -798,6 +943,11 @@ static int process_advertise(struct mqtt_sn_client *client, int64_t *next_cycle)
 	return 0;
 }
 
+/**
+ * @brief Housekeeping task that is called by workqueue item
+ *
+ * @param wrk The work item
+ */
 static void process_work(struct k_work *wrk)
 {
 	struct mqtt_sn_client *client;
@@ -897,7 +1047,7 @@ int mqtt_sn_add_gw(struct mqtt_sn_client *client, uint8_t gw_id, struct mqtt_sn_
 {
 	struct mqtt_sn_gateway *gw;
 
-	gw = mqtt_sn_gw_find_id(client, gw_id);
+	gw = mqtt_sn_gw_find_by_id(client, gw_id);
 
 	if (gw != NULL) {
 		mqtt_sn_gw_destroy(client, gw);
@@ -1004,7 +1154,7 @@ int mqtt_sn_subscribe(struct mqtt_sn_client *client, enum mqtt_sn_qos qos,
 		return -ENOTCONN;
 	}
 
-	topic = mqtt_sn_topic_find_name(client, topic_name);
+	topic = mqtt_sn_topic_find_by_name(client, topic_name);
 	if (!topic) {
 		topic = mqtt_sn_topic_create(topic_name);
 		if (!topic) {
@@ -1012,7 +1162,7 @@ int mqtt_sn_subscribe(struct mqtt_sn_client *client, enum mqtt_sn_qos qos,
 		}
 
 		topic->qos = qos;
-		topic->state = MQTT_SN_TOPIC_STATE_SUBSCRIBING;
+		topic->state = MQTT_SN_TOPIC_STATE_SUBSCRIBE;
 		sys_slist_append(&client->topic, &topic->next);
 	}
 
@@ -1039,13 +1189,18 @@ int mqtt_sn_unsubscribe(struct mqtt_sn_client *client, enum mqtt_sn_qos qos,
 		return -ENOTCONN;
 	}
 
-	topic = mqtt_sn_topic_find_name(client, topic_name);
+	topic = mqtt_sn_topic_find_by_name(client, topic_name);
 	if (!topic) {
 		LOG_HEXDUMP_ERR(topic_name->data, topic_name->size, "Topic not found");
 		return -ENOENT;
 	}
 
-	topic->state = MQTT_SN_TOPIC_STATE_UNSUBSCRIBING;
+	if (topic->state != MQTT_SN_TOPIC_STATE_SUBSCRIBED) {
+		LOG_ERR("Cannot unsubscribe: not subscribed");
+		return -EAGAIN;
+	}
+
+	topic->state = MQTT_SN_TOPIC_STATE_UNSUBSCRIBE;
 	mqtt_sn_con_init(&topic->con);
 
 	err = k_work_reschedule(&client->process_work, K_NO_WAIT);
@@ -1077,7 +1232,7 @@ int mqtt_sn_publish(struct mqtt_sn_client *client, enum mqtt_sn_qos qos,
 		return -ENOTCONN;
 	}
 
-	topic = mqtt_sn_topic_find_name(client, topic_name);
+	topic = mqtt_sn_topic_find_by_name(client, topic_name);
 	if (!topic) {
 		topic = mqtt_sn_topic_create(topic_name);
 		if (!topic) {
@@ -1085,7 +1240,7 @@ int mqtt_sn_publish(struct mqtt_sn_client *client, enum mqtt_sn_qos qos,
 		}
 
 		topic->qos = qos;
-		topic->state = MQTT_SN_TOPIC_STATE_REGISTERING;
+		topic->state = MQTT_SN_TOPIC_STATE_REGISTER;
 		sys_slist_append(&client->topic, &topic->next);
 	}
 
@@ -1115,7 +1270,7 @@ static void handle_advertise(struct mqtt_sn_client *client, struct mqtt_sn_param
 	struct mqtt_sn_evt evt = {.type = MQTT_SN_EVT_ADVERTISE};
 	struct mqtt_sn_gateway *gw;
 
-	gw = mqtt_sn_gw_find_id(client, p->gw_id);
+	gw = mqtt_sn_gw_find_by_id(client, p->gw_id);
 
 	if (gw == NULL) {
 		LOG_DBG("Creating GW 0x%02x with duration %d", p->gw_id, p->duration);
@@ -1262,7 +1417,7 @@ static void handle_register(struct mqtt_sn_client *client, struct mqtt_sn_param_
 
 static void handle_regack(struct mqtt_sn_client *client, struct mqtt_sn_param_regack *p)
 {
-	struct mqtt_sn_topic *topic = mqtt_sn_topic_find_msg_id(client, p->msg_id);
+	struct mqtt_sn_topic *topic = mqtt_sn_topic_find_by_msg_id(client, p->msg_id);
 
 	if (!topic) {
 		LOG_ERR("Can't REGACK, no topic found");
@@ -1307,7 +1462,7 @@ static void handle_publish(struct mqtt_sn_client *client, struct mqtt_sn_param_p
 
 static void handle_puback(struct mqtt_sn_client *client, struct mqtt_sn_param_puback *p)
 {
-	struct mqtt_sn_publish *pub = mqtt_sn_publish_find_msg_id(client, p->msg_id);
+	struct mqtt_sn_publish *pub = mqtt_sn_publish_find_by_msg_id(client, p->msg_id);
 
 	if (!pub) {
 		LOG_ERR("No matching PUBLISH found for msg id %u", p->msg_id);
@@ -1320,7 +1475,7 @@ static void handle_puback(struct mqtt_sn_client *client, struct mqtt_sn_param_pu
 static void handle_pubrec(struct mqtt_sn_client *client, struct mqtt_sn_param_pubrec *p)
 {
 	struct mqtt_sn_param response = {.type = MQTT_SN_MSG_TYPE_PUBREL};
-	struct mqtt_sn_publish *pub = mqtt_sn_publish_find_msg_id(client, p->msg_id);
+	struct mqtt_sn_publish *pub = mqtt_sn_publish_find_by_msg_id(client, p->msg_id);
 
 	if (!pub) {
 		LOG_ERR("No matching PUBLISH found for msg id %u", p->msg_id);
@@ -1346,7 +1501,7 @@ static void handle_pubrel(struct mqtt_sn_client *client, struct mqtt_sn_param_pu
 
 static void handle_pubcomp(struct mqtt_sn_client *client, struct mqtt_sn_param_pubcomp *p)
 {
-	struct mqtt_sn_publish *pub = mqtt_sn_publish_find_msg_id(client, p->msg_id);
+	struct mqtt_sn_publish *pub = mqtt_sn_publish_find_by_msg_id(client, p->msg_id);
 
 	if (!pub) {
 		LOG_ERR("No matching PUBLISH found for msg id %u", p->msg_id);
@@ -1358,7 +1513,7 @@ static void handle_pubcomp(struct mqtt_sn_client *client, struct mqtt_sn_param_p
 
 static void handle_suback(struct mqtt_sn_client *client, struct mqtt_sn_param_suback *p)
 {
-	struct mqtt_sn_topic *topic = mqtt_sn_topic_find_msg_id(client, p->msg_id);
+	struct mqtt_sn_topic *topic = mqtt_sn_topic_find_by_msg_id(client, p->msg_id);
 
 	if (!topic) {
 		LOG_ERR("No matching SUBSCRIBE found for msg id %u", p->msg_id);
@@ -1376,7 +1531,7 @@ static void handle_suback(struct mqtt_sn_client *client, struct mqtt_sn_param_su
 
 static void handle_unsuback(struct mqtt_sn_client *client, struct mqtt_sn_param_unsuback *p)
 {
-	struct mqtt_sn_topic *topic = mqtt_sn_topic_find_msg_id(client, p->msg_id);
+	struct mqtt_sn_topic *topic = mqtt_sn_topic_find_by_msg_id(client, p->msg_id);
 
 	if (!topic || topic->state != MQTT_SN_TOPIC_STATE_UNSUBSCRIBING) {
 		LOG_ERR("No matching UNSUBSCRIBE found for msg id %u", p->msg_id);
diff --git a/subsys/net/lib/ptp/clock.c b/subsys/net/lib/ptp/clock.c
index f599ca90605..e808275dbe4 100644
--- a/subsys/net/lib/ptp/clock.c
+++ b/subsys/net/lib/ptp/clock.c
@@ -509,7 +509,7 @@ int ptp_clock_management_msg_process(struct ptp_port *port, struct ptp_msg *msg)
 void ptp_clock_synchronize(uint64_t ingress, uint64_t egress)
 {
 	int64_t offset;
-	uint64_t delay = ptp_clk.current_ds.mean_delay >> 16;
+	int64_t delay = ptp_clk.current_ds.mean_delay >> 16;
 
 	ptp_clk.timestamp.t1 = egress;
 	ptp_clk.timestamp.t2 = ingress;
@@ -518,7 +518,7 @@ void ptp_clock_synchronize(uint64_t ingress, uint64_t egress)
 		return;
 	}
 
-	offset = ptp_clk.timestamp.t2 - ptp_clk.timestamp.t1 - delay;
+	offset = (int64_t)(ptp_clk.timestamp.t2 - ptp_clk.timestamp.t1) - delay;
 
 	/* If diff is too big, ptp_clk needs to be set first. */
 	if ((offset > (int64_t)NSEC_PER_SEC) || (offset < -(int64_t)NSEC_PER_SEC)) {
@@ -559,8 +559,9 @@ void ptp_clock_delay(uint64_t egress, uint64_t ingress)
 	ptp_clk.timestamp.t3 = egress;
 	ptp_clk.timestamp.t4 = ingress;
 
-	delay = ((ptp_clk.timestamp.t2 - ptp_clk.timestamp.t3) +
-		 (ptp_clk.timestamp.t4 - ptp_clk.timestamp.t1)) / 2;
+	delay = ((int64_t)(ptp_clk.timestamp.t2 - ptp_clk.timestamp.t3) +
+		 (int64_t)(ptp_clk.timestamp.t4 - ptp_clk.timestamp.t1)) /
+		2LL;
 
 	LOG_DBG("Delay %lldns", delay);
 	ptp_clk.current_ds.mean_delay = clock_ns_to_timeinterval(delay);
diff --git a/subsys/net/lib/ptp/ptp.c b/subsys/net/lib/ptp/ptp.c
index 8f702492951..2097121072d 100644
--- a/subsys/net/lib/ptp/ptp.c
+++ b/subsys/net/lib/ptp/ptp.c
@@ -114,3 +114,16 @@ static int ptp_init(void)
 }
 
 SYS_INIT(ptp_init, APPLICATION, CONFIG_PTP_INIT_PRIO);
+
+static enum net_verdict ptp_recv(struct net_if *iface, uint16_t ptype,
+				 struct net_pkt *pkt)
+{
+	ARG_UNUSED(iface);
+	ARG_UNUSED(ptype);
+
+	net_pkt_set_family(pkt, AF_UNSPEC);
+
+	return NET_CONTINUE;
+}
+
+ETH_NET_L3_REGISTER(PTP, NET_ETH_PTYPE_PTP, ptp_recv);
diff --git a/subsys/net/lib/shell/CMakeLists.txt b/subsys/net/lib/shell/CMakeLists.txt
index 02e9dde5e28..db06c84d8bb 100644
--- a/subsys/net/lib/shell/CMakeLists.txt
+++ b/subsys/net/lib/shell/CMakeLists.txt
@@ -24,6 +24,7 @@ zephyr_library_sources(mem.c)
 zephyr_library_sources_ifdef(CONFIG_NET_SHELL_IPV6_SUPPORTED nbr.c)
 zephyr_library_sources_ifdef(CONFIG_NET_SHELL_IP_SUPPORTED ping.c)
 zephyr_library_sources(pkt.c)
+zephyr_library_sources_ifdef(CONFIG_NET_SHELL_PKT_FILTER_SUPPORTED filter.c)
 zephyr_library_sources_ifdef(CONFIG_NET_SHELL_PMTU_SUPPORTED pmtu.c)
 zephyr_library_sources_ifdef(CONFIG_NET_SHELL_PPP_SUPPORTED ppp.c)
 zephyr_library_sources_ifdef(CONFIG_NET_SHELL_POWER_MANAGEMENT_SUPPORTED resume.c)
diff --git a/subsys/net/lib/shell/conn.c b/subsys/net/lib/shell/conn.c
index 24b528537bd..ca32074a4ef 100644
--- a/subsys/net/lib/shell/conn.c
+++ b/subsys/net/lib/shell/conn.c
@@ -51,7 +51,6 @@ static void context_cb(struct net_context *context, void *user_data)
 }
 #endif /* CONFIG_NET_OFFLOAD || CONFIG_NET_NATIVE */
 
-#if CONFIG_NET_CONN_LOG_LEVEL >= LOG_LEVEL_DBG
 static void conn_handler_cb(struct net_conn *conn, void *user_data)
 {
 #if defined(CONFIG_NET_IPV6) && !defined(CONFIG_NET_IPV4)
@@ -95,14 +94,13 @@ static void conn_handler_cb(struct net_conn *conn, void *user_data)
 			 conn->local_addr.sa_family);
 	}
 
-	PR("[%2d] %p %p\t%s\t%16s\t%16s\n",
+	PR("[%2d] %p %p  %s\t%16s\t%16s\n",
 	   (*count) + 1, conn, conn->cb,
 	   net_proto2str(conn->local_addr.sa_family, conn->proto),
 	   addr_local, addr_remote);
 
 	(*count)++;
 }
-#endif /* CONFIG_NET_CONN_LOG_LEVEL >= LOG_LEVEL_DBG */
 
 #if CONFIG_NET_TCP_LOG_LEVEL >= LOG_LEVEL_DBG
 struct tcp_detail_info {
@@ -227,8 +225,7 @@ static int cmd_net_conn(const struct shell *sh, size_t argc, char *argv[])
 		PR("No connections\n");
 	}
 
-#if CONFIG_NET_CONN_LOG_LEVEL >= LOG_LEVEL_DBG
-	PR("\n     Handler    Callback  \tProto\tLocal           \tRemote\n");
+	PR("\n     Handler    Callback  Proto            Local                  Remote\n");
 
 	count = 0;
 
@@ -237,7 +234,6 @@ static int cmd_net_conn(const struct shell *sh, size_t argc, char *argv[])
 	if (count == 0) {
 		PR("No connection handlers found.\n");
 	}
-#endif
 
 #if defined(CONFIG_NET_TCP)
 	PR("\nTCP        Context   Src port Dst port   "
diff --git a/subsys/net/lib/shell/events.c b/subsys/net/lib/shell/events.c
index 699db20ef53..c61922f073d 100644
--- a/subsys/net/lib/shell/events.c
+++ b/subsys/net/lib/shell/events.c
@@ -13,6 +13,7 @@ LOG_MODULE_DECLARE(net_shell);
 #include <zephyr/net/net_mgmt.h>
 #include <zephyr/net/net_event.h>
 #include <zephyr/net/coap_mgmt.h>
+#include <zephyr/net/ethernet_mgmt.h>
 
 #include "net_shell_private.h"
 
@@ -24,6 +25,11 @@ LOG_MODULE_DECLARE(net_shell);
 #define MONITOR_L3_IPV6_MASK (_NET_EVENT_IPV6_BASE | NET_MGMT_COMMAND_MASK)
 #define MONITOR_L4_MASK (_NET_EVENT_L4_BASE | NET_MGMT_COMMAND_MASK)
 
+#if defined(CONFIG_NET_L2_ETHERNET_MGMT)
+#define MONITOR_L2_ETHERNET_MASK (_NET_ETHERNET_BASE)
+static struct net_mgmt_event_callback l2_ethernet_cb;
+#endif
+
 static bool net_event_monitoring;
 static bool net_event_shutting_down;
 static struct net_mgmt_event_callback l2_cb;
@@ -33,6 +39,8 @@ static struct net_mgmt_event_callback l4_cb;
 static struct k_thread event_mon;
 static K_THREAD_STACK_DEFINE(event_mon_stack, CONFIG_NET_MGMT_EVENT_MONITOR_STACK_SIZE);
 
+static const char unknown_event_str[] = "<unknown event>";
+
 struct event_msg {
 	struct net_if *iface;
 	size_t len;
@@ -65,27 +73,81 @@ static void event_handler(struct net_mgmt_event_callback *cb,
 	}
 }
 
-static const char *get_l2_desc(uint32_t event)
+static char *get_l2_desc(struct event_msg *msg,
+			 const char **desc, const char **desc2,
+			 char *extra_info, size_t extra_info_len)
 {
-	static const char *desc = "<unknown event>";
+	static const char *desc_unknown = unknown_event_str;
+	char *info = NULL;
+
+#if defined(CONFIG_NET_L2_ETHERNET_MGMT)
+#define MAX_VLAN_TAG_INFO_STR_LEN sizeof("tag xxxx disabled")
+	static char vlan_buf[MAX_VLAN_TAG_INFO_STR_LEN + 1];
+#endif
+
+	*desc = desc_unknown;
 
-	switch (event) {
+	switch (msg->event) {
 	case NET_EVENT_IF_DOWN:
-		desc = "down";
+		*desc = "interface";
+		*desc2 = "down";
 		break;
 	case NET_EVENT_IF_UP:
-		desc = "up";
+		*desc = "interface";
+		*desc2 = "up";
+		break;
+	case NET_EVENT_IF_ADMIN_UP:
+		*desc = "interface";
+		*desc2 = "admin up";
+		break;
+	case NET_EVENT_IF_ADMIN_DOWN:
+		*desc = "interface";
+		*desc2 = "admin down";
+		break;
+	case NET_EVENT_ETHERNET_CARRIER_ON:
+#if defined(CONFIG_NET_L2_ETHERNET_MGMT)
+		*desc = "Ethernet";
+		*desc2 = "carrier on";
+#endif
 		break;
+	case NET_EVENT_ETHERNET_CARRIER_OFF:
+#if defined(CONFIG_NET_L2_ETHERNET_MGMT)
+		*desc = "Ethernet";
+		*desc2 = "carrier off";
+#endif
+		break;
+	case NET_EVENT_ETHERNET_VLAN_TAG_ENABLED: {
+#if defined(CONFIG_NET_L2_ETHERNET_MGMT)
+		uint16_t tag = *((uint16_t *)msg->data);
+
+		*desc = "VLAN";
+		snprintk(vlan_buf, MAX_VLAN_TAG_INFO_STR_LEN,
+			 "tag %u enabled", (uint16_t)tag);
+		*desc2 = vlan_buf;
+#endif
+		break;
+	}
+	case NET_EVENT_ETHERNET_VLAN_TAG_DISABLED: {
+#if defined(CONFIG_NET_L2_ETHERNET_MGMT)
+		uint16_t tag = *((uint16_t *)msg->data);
+
+		*desc = "VLAN";
+		snprintk(vlan_buf, MAX_VLAN_TAG_INFO_STR_LEN,
+			 "tag %u enabled", (uint16_t)tag);
+		*desc2 = vlan_buf;
+#endif
+		break;
+	}
 	}
 
-	return desc;
+	return info;
 }
 
 static char *get_l3_desc(struct event_msg *msg,
 			 const char **desc, const char **desc2,
 			 char *extra_info, size_t extra_info_len)
 {
-	static const char *desc_unknown = "<unknown event>";
+	static const char *desc_unknown = unknown_event_str;
 	char *info = NULL;
 
 #if defined(CONFIG_NET_PMTU)
@@ -230,6 +292,18 @@ static char *get_l3_desc(struct event_msg *msg,
 		info = net_addr_ntop(AF_INET, msg->data, extra_info,
 				     extra_info_len);
 		break;
+	case NET_EVENT_IPV4_MADDR_ADD:
+		*desc = "IPv4 mcast address";
+		*desc2 = "add";
+		info = net_addr_ntop(AF_INET, msg->data, extra_info,
+				     extra_info_len);
+		break;
+	case NET_EVENT_IPV4_MADDR_DEL:
+		*desc = "IPv4 mcast address";
+		*desc2 = "del";
+		info = net_addr_ntop(AF_INET, msg->data, extra_info,
+				     extra_info_len);
+		break;
 	case NET_EVENT_IPV4_ROUTER_ADD:
 		*desc = "IPv4 router";
 		*desc2 = "add";
@@ -260,6 +334,18 @@ static char *get_l3_desc(struct event_msg *msg,
 		*desc = "DHCPv4";
 		*desc2 = "stop";
 		break;
+	case NET_EVENT_IPV4_MCAST_JOIN:
+		*desc = "IPv4 mcast";
+		*desc2 = "join";
+		info = net_addr_ntop(AF_INET, msg->data, extra_info,
+				     extra_info_len);
+		break;
+	case NET_EVENT_IPV4_MCAST_LEAVE:
+		*desc = "IPv4 mcast";
+		*desc2 = "leave";
+		info = net_addr_ntop(AF_INET, msg->data, extra_info,
+				     extra_info_len);
+		break;
 	case NET_EVENT_IPV4_ACD_SUCCEED:
 		*desc = "IPv4 ACD";
 		*desc2 = "ok";
@@ -305,59 +391,115 @@ static char *get_l3_desc(struct event_msg *msg,
 	return info;
 }
 
-static const char *get_l4_desc(uint32_t event)
+static char *sockaddr_ntop(const struct sockaddr *addr, char *dst, size_t size)
 {
-	static const char *desc = "<unknown event>";
+	if (addr->sa_family == AF_INET) {
+		return net_addr_ntop(AF_INET, &net_sin(addr)->sin_addr, dst, size);
+	} else if (addr->sa_family == AF_INET6) {
+		return net_addr_ntop(AF_INET6, &net_sin6(addr)->sin6_addr, dst, size);
+	}
 
-	switch (event) {
+	return NULL;
+}
+
+static char *get_l4_desc(struct event_msg *msg,
+			 const char **desc, const char **desc2,
+			 char *extra_info, size_t extra_info_len)
+{
+	static const char *desc_unknown = unknown_event_str;
+	char *info = NULL;
+
+	*desc = desc_unknown;
+
+	switch (msg->event) {
 	case NET_EVENT_L4_CONNECTED:
-		desc = "connected";
+		*desc = "connected";
 		break;
 	case NET_EVENT_L4_DISCONNECTED:
-		desc = "disconnected";
+		*desc = "disconnected";
 		break;
 	case NET_EVENT_L4_IPV4_CONNECTED:
-		desc = "IPv4 connectivity available";
+		*desc = "IPv4 connectivity";
+		*desc2 = "available";
 		break;
 	case NET_EVENT_L4_IPV4_DISCONNECTED:
-		desc = "IPv4 connectivity lost";
+		*desc = "IPv4 connectivity";
+		*desc2 = "lost";
 		break;
 	case NET_EVENT_L4_IPV6_CONNECTED:
-		desc = "IPv6 connectivity available";
+		*desc = "IPv6 connectivity";
+		*desc2 = "available";
 		break;
 	case NET_EVENT_L4_IPV6_DISCONNECTED:
-		desc = "IPv6 connectivity lost";
+		*desc = "IPv6 connectivity";
+		*desc2 = "lost";
 		break;
-	case NET_EVENT_DNS_SERVER_ADD:
-		desc = "DNS server add";
+	case NET_EVENT_DNS_SERVER_ADD: {
+		struct sockaddr *addr = (struct sockaddr *)msg->data;
+
+		*desc = "DNS server";
+		*desc2 = "add";
+
+		info = sockaddr_ntop(addr, extra_info, extra_info_len);
+
 		break;
-	case NET_EVENT_DNS_SERVER_DEL:
-		desc = "DNS server del";
+	}
+	case NET_EVENT_DNS_SERVER_DEL: {
+		struct sockaddr *addr = (struct sockaddr *)msg->data;
+
+		*desc = "DNS server";
+		*desc2 = "del";
+
+		info = sockaddr_ntop(addr, extra_info, extra_info_len);
+
 		break;
+	}
 	case NET_EVENT_HOSTNAME_CHANGED:
-		desc = "Hostname changed";
+		*desc = "Hostname changed";
 		break;
 	case NET_EVENT_COAP_SERVICE_STARTED:
-		desc = "CoAP service started";
+		*desc = "CoAP service";
+		*desc2 = "started";
 		break;
 	case NET_EVENT_COAP_SERVICE_STOPPED:
-		desc = "CoAP service stopped";
+		*desc = "CoAP service";
+		*desc2 = "stopped";
 		break;
 	case NET_EVENT_COAP_OBSERVER_ADDED:
-		desc = "CoAP observer added";
+		*desc = "CoAP observer";
+		*desc2 = "added";
 		break;
 	case NET_EVENT_COAP_OBSERVER_REMOVED:
-		desc = "CoAP observer removed";
+		*desc = "CoAP observer";
+		*desc2 = "removed";
 		break;
 	case NET_EVENT_CAPTURE_STARTED:
-		desc = "Capture started";
+		*desc = "Capture";
+		*desc2 = "started";
 		break;
 	case NET_EVENT_CAPTURE_STOPPED:
-		desc = "Capture stopped";
+		*desc = "Capture";
+		*desc2 = "stopped";
+		break;
+	case NET_EVENT_VPN_PEER_ADD:
+		*desc = "VPN peer";
+		*desc2 = "add";
+		break;
+	case NET_EVENT_VPN_PEER_DEL:
+		*desc = "VPN peer";
+		*desc2 = "del";
+		break;
+	case NET_EVENT_VPN_CONNECTED:
+		*desc = "VPN";
+		*desc2 = "connected";
+		break;
+	case NET_EVENT_VPN_DISCONNECTED:
+		*desc = "VPN";
+		*desc2 = "disconnected";
 		break;
 	}
 
-	return desc;
+	return info;
 }
 
 /* We use a separate thread in order not to do any shell printing from
@@ -365,7 +507,7 @@ static const char *get_l4_desc(uint32_t event)
  */
 static void event_mon_handler(const struct shell *sh, void *p2, void *p3)
 {
-	char extra_info[NET_IPV6_ADDR_LEN];
+	char extra_info[NET_IPV6_ADDR_LEN + sizeof("id 0123456789 ")];
 	struct event_msg msg;
 
 	ARG_UNUSED(p2);
@@ -386,6 +528,12 @@ static void event_mon_handler(const struct shell *sh, void *p2, void *p3)
 				     MONITOR_L4_MASK);
 	net_mgmt_add_event_callback(&l4_cb);
 
+#if defined(CONFIG_NET_L2_ETHERNET_MGMT)
+	net_mgmt_init_event_callback(&l2_ethernet_cb, event_handler,
+				     MONITOR_L2_ETHERNET_MASK);
+	net_mgmt_add_event_callback(&l2_ethernet_cb);
+#endif
+
 	while (net_event_shutting_down == false) {
 		const char *layer_str = "<unknown layer>";
 		const char *desc = "", *desc2 = "";
@@ -402,20 +550,29 @@ static void event_mon_handler(const struct shell *sh, void *p2, void *p3)
 		layer = NET_MGMT_GET_LAYER(msg.event);
 		if (layer == NET_MGMT_LAYER_L2) {
 			layer_str = "L2";
-			desc = get_l2_desc(msg.event);
+			info = get_l2_desc(&msg, &desc, &desc2,
+					   extra_info, sizeof(extra_info));
 		} else if (layer == NET_MGMT_LAYER_L3) {
 			layer_str = "L3";
 			info = get_l3_desc(&msg, &desc, &desc2,
-					   extra_info, NET_IPV6_ADDR_LEN);
+					   extra_info, sizeof(extra_info));
 		} else if (layer == NET_MGMT_LAYER_L4) {
 			layer_str = "L4";
-			desc = get_l4_desc(msg.event);
+			info = get_l4_desc(&msg, &desc, &desc2,
+					   extra_info, sizeof(extra_info));
 		}
 
-		PR_INFO("EVENT: %s [%d] %s%s%s%s%s\n", layer_str,
-			net_if_get_by_iface(msg.iface), desc,
-			desc2 ? " " : "", desc2 ? desc2 : "",
-			info ? " " : "", info ? info : "");
+		if (desc == unknown_event_str) {
+			PR_INFO("EVENT: %s [%d] %s%s%s%s%s (0x%08x)\n", layer_str,
+				net_if_get_by_iface(msg.iface), desc,
+				desc2 ? " " : "", desc2 ? desc2 : "",
+				info ? " " : "", info ? info : "", msg.event);
+		} else {
+			PR_INFO("EVENT: %s [%d] %s%s%s%s%s\n", layer_str,
+				net_if_get_by_iface(msg.iface), desc,
+				desc2 ? " " : "", desc2 ? desc2 : "",
+				info ? " " : "", info ? info : "");
+		}
 	}
 
 	net_mgmt_del_event_callback(&l2_cb);
@@ -423,6 +580,10 @@ static void event_mon_handler(const struct shell *sh, void *p2, void *p3)
 	net_mgmt_del_event_callback(&l3_ipv6_cb);
 	net_mgmt_del_event_callback(&l4_cb);
 
+#if defined(CONFIG_NET_L2_ETHERNET_MGMT)
+	net_mgmt_del_event_callback(&l2_ethernet_cb);
+#endif
+
 	k_msgq_purge(&event_mon_msgq);
 
 	net_event_monitoring = false;
diff --git a/subsys/net/lib/shell/filter.c b/subsys/net/lib/shell/filter.c
new file mode 100644
index 00000000000..59de20f588a
--- /dev/null
+++ b/subsys/net/lib/shell/filter.c
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_DECLARE(net_shell);
+
+#include <zephyr/net/net_pkt_filter.h>
+
+#include "net_shell_private.h"
+
+
+#if defined(CONFIG_NET_PKT_FILTER)
+static const char *rule_type2str(enum npf_rule_type type)
+{
+	switch (type) {
+	case NPF_RULE_TYPE_SEND:
+		return "send";
+	case NPF_RULE_TYPE_RECV:
+		return "recv";
+	case NPF_RULE_TYPE_LOCAL_IN_RECV:
+		return "local recv";
+	case NPF_RULE_TYPE_IPV4_RECV:
+		return "IPv4 recv";
+	case NPF_RULE_TYPE_IPV6_RECV:
+		return "IPv6 recv";
+	case NPF_RULE_TYPE_UNKNOWN:
+		__fallthrough;
+	default:
+		break;
+	}
+
+	return "<UNKNOWN>";
+}
+
+static const char *verdict2str(enum net_verdict verdict)
+{
+	switch (verdict) {
+	case NET_OK:
+		return "OK";
+	case NET_DROP:
+		return "DROP";
+	case NET_CONTINUE:
+		return "CONTINUE";
+	default:
+		break;
+	}
+
+	return "<UNK>";
+}
+
+static void rule_cb(struct npf_rule *rule, enum npf_rule_type type, void *user_data)
+{
+	struct net_shell_user_data *data = user_data;
+	const struct shell *sh = data->sh;
+	int *count = data->user_data;
+
+	PR("[%2d]  %-10s  %-7s  %-5d",
+	   (*count) + 1, rule_type2str(type), verdict2str(rule->result), rule->nb_tests);
+
+	for (int i = 0; i < rule->nb_tests; i++) {
+		/* Allocate room for storing two full IPv4/6 addresses */
+#define MAX_BUF_LEN ((IS_ENABLED(CONFIG_NET_IPV6) ?		\
+		      INET6_ADDRSTRLEN : INET_ADDRSTRLEN) * 2)
+		char buf[MAX_BUF_LEN] = { 0 };
+		struct npf_test *test;
+		const char *str;
+
+		test = rule->tests[i];
+
+		str = npf_test_get_str(test, buf, sizeof(buf) - 1);
+		PR("%s%s%s", str, buf[0] != '\0' ? buf : "",
+		   i == rule->nb_tests - 1 ? "" : ",");
+	}
+
+	PR("\n");
+	(*count)++;
+}
+#endif /* CONFIG_NET_PKT_FILTER */
+
+static int cmd_net_filter(const struct shell *sh, size_t argc, char *argv[])
+{
+	ARG_UNUSED(argc);
+	ARG_UNUSED(argv);
+
+#if defined(CONFIG_NET_PKT_FILTER)
+	struct net_shell_user_data user_data;
+	int count = 0;
+
+	PR("Rule  %-10s  Verdict  Tests \n", "Type");
+
+	user_data.sh = sh;
+	user_data.user_data = &count;
+
+	npf_rules_foreach(rule_cb, &user_data);
+
+	if (count == 0) {
+		PR("No network packet filter rules\n");
+	}
+#else
+	PR_INFO("Set %s to enable %s support.\n",
+		"CONFIG_NET_PKT_FILTER",
+		"packet filter information");
+
+#endif /* CONFIG_NET_PKT_FILTER */
+
+	return 0;
+}
+
+
+SHELL_SUBCMD_ADD((net), filter, NULL, "Print information about network packet filters.",
+		 cmd_net_filter, 1, 0);
diff --git a/subsys/net/lib/shell/http.c b/subsys/net/lib/shell/http.c
index ed4bebff533..6a8c57f210d 100644
--- a/subsys/net/lib/shell/http.c
+++ b/subsys/net/lib/shell/http.c
@@ -12,8 +12,7 @@ LOG_MODULE_DECLARE(net_shell);
 #include <zephyr/net/http/server.h>
 #include <zephyr/net/http/method.h>
 #include <zephyr/net/http/parser.h>
-
-#define IS_BIT_SET(val, bit) (((val >> bit) & (0x1)) != 0)
+#include <zephyr/sys/util.h>
 
 static int cmd_net_http(const struct shell *sh, size_t argc, char *argv[])
 {
diff --git a/subsys/net/lib/shell/iface.c b/subsys/net/lib/shell/iface.c
index 7f6519d525e..8d54ae1ae5d 100644
--- a/subsys/net/lib/shell/iface.c
+++ b/subsys/net/lib/shell/iface.c
@@ -10,6 +10,8 @@
 #include <strings.h>
 LOG_MODULE_DECLARE(net_shell);
 
+#include <zephyr/sys/base64.h>
+
 #if defined(CONFIG_NET_L2_ETHERNET)
 #include <zephyr/net/ethernet.h>
 #endif
@@ -18,6 +20,7 @@ LOG_MODULE_DECLARE(net_shell);
 #endif
 #if defined(CONFIG_NET_L2_VIRTUAL)
 #include <zephyr/net/virtual.h>
+#include <zephyr/net/virtual_mgmt.h>
 #endif
 #if defined(CONFIG_ETH_PHY_DRIVER)
 #include <zephyr/net/phy.h>
@@ -54,8 +57,8 @@ static struct ethernet_capabilities eth_hw_caps[] = {
 	EC(ETHERNET_PROMISC_MODE,         "Promiscuous mode"),
 	EC(ETHERNET_PRIORITY_QUEUES,      "Priority queues"),
 	EC(ETHERNET_HW_FILTERING,         "MAC address filtering"),
-	EC(ETHERNET_DSA_SLAVE_PORT,       "DSA slave port"),
-	EC(ETHERNET_DSA_MASTER_PORT,      "DSA master port"),
+	EC(ETHERNET_DSA_USER_PORT,        "DSA user port"),
+	EC(ETHERNET_DSA_CONDUIT_PORT,     "DSA conduit port"),
 	EC(ETHERNET_TXTIME,               "TXTIME supported"),
 	EC(ETHERNET_TXINJECTION_MODE,     "TX-Injection supported"),
 	EC(ETHERNET_LINK_2500BASE_T,      "2.5 Gbits"),
@@ -156,6 +159,9 @@ static void iface_cb(struct net_if *iface, void *user_data)
 {
 	struct net_shell_user_data *data = user_data;
 	const struct shell *sh = data->sh;
+	int ret;
+
+	ARG_UNUSED(ret); /* could be unused depending on config */
 
 #if defined(CONFIG_NET_NATIVE_IPV6)
 	struct net_if_ipv6_prefix *prefix;
@@ -173,7 +179,6 @@ static void iface_cb(struct net_if *iface, void *user_data)
 #endif
 #if defined(CONFIG_NET_L2_ETHERNET_MGMT)
 	struct ethernet_req_params params;
-	int ret;
 #endif
 	const char *extra;
 #if defined(CONFIG_NET_IP) || defined(CONFIG_NET_L2_ETHERNET_MGMT)
@@ -257,11 +262,42 @@ static void iface_cb(struct net_if *iface, void *user_data)
 			   orig_iface);
 		}
 	}
+
+	if (IS_ENABLED(CONFIG_NET_VPN) &&
+	    net_if_l2(iface) == &NET_L2_GET_NAME(VIRTUAL)) {
+		if (net_virtual_get_iface_capabilities(iface) & VIRTUAL_INTERFACE_VPN) {
+			struct virtual_interface_req_params vparams = { 0 };
+			char public_key[NET_VIRTUAL_MAX_PUBLIC_KEY_LEN * 2];
+			size_t olen;
+
+			ret = net_mgmt(NET_REQUEST_VIRTUAL_INTERFACE_GET_PUBLIC_KEY,
+				       iface, &vparams, sizeof(vparams));
+			if (ret < 0) {
+				PR_WARNING("Cannot get VPN public key (%d)\n", ret);
+			} else {
+				bool all_zeros = true;
+
+				for (int i = 0;
+				     all_zeros && i < NET_VIRTUAL_MAX_PUBLIC_KEY_LEN; i++) {
+					all_zeros = (vparams.public_key.data[i] == 0);
+				}
+
+				if (all_zeros) {
+					PR("Public key: <not set>\n");
+				} else {
+					(void)base64_encode(public_key, sizeof(public_key),
+							    &olen, vparams.public_key.data,
+							    vparams.public_key.len);
+
+					PR("Public key: %s\n", public_key);
+				}
+			}
+		}
+	}
 #endif /* CONFIG_NET_L2_VIRTUAL */
 
 	net_if_lock(iface);
-	if (net_if_get_link_addr(iface) &&
-	    net_if_get_link_addr(iface)->addr) {
+	if (net_if_get_link_addr(iface)->len > 0) {
 		PR("Link addr : %s\n",
 		   net_sprint_ll_addr(net_if_get_link_addr(iface)->addr,
 				      net_if_get_link_addr(iface)->len));
@@ -274,6 +310,25 @@ static void iface_cb(struct net_if *iface, void *user_data)
 	   net_if_get_device(iface) ? net_if_get_device(iface)->name : "<?>",
 	   net_if_get_device(iface));
 
+	PR("Status    : oper=%s, admin=%s, carrier=%s\n",
+	   net_if_oper_state2str(net_if_oper_state(iface)),
+	   net_if_is_admin_up(iface) ? "UP" : "DOWN",
+	   net_if_is_carrier_ok(iface) ? "ON" : "OFF");
+
+#if defined(CONFIG_NET_IF_LOG_LEVEL_DBG)
+	/* Print low level details only if debug is enabled */
+	if (IS_ENABLED(CONFIG_NET_IPV4) && net_if_flag_is_set(iface, NET_IF_IPV4)) {
+		PR("IPv4 TTL             : %d\n", net_if_ipv4_get_ttl(iface));
+		PR("IPv4 mcast TTL       : %d\n", net_if_ipv4_get_mcast_ttl(iface));
+	}
+
+	if (IS_ENABLED(CONFIG_NET_IPV6) && net_if_flag_is_set(iface, NET_IF_IPV6)) {
+		PR("IPv6 hop limit       : %d\n", net_if_ipv6_get_hop_limit(iface));
+		PR("IPv6 mcast hop limit : %d\n",
+		   net_if_ipv6_get_mcast_hop_limit(iface));
+	}
+#endif /* CONFIG_NET_IF_LOG_LEVEL_DBG */
+
 #if defined(CONFIG_NET_L2_ETHERNET_MGMT)
 	if (net_if_l2(iface) == &NET_L2_GET_NAME(ETHERNET)) {
 		count = 0;
@@ -448,20 +503,22 @@ static void iface_cb(struct net_if *iface, void *user_data)
 
 #if defined(CONFIG_NET_DHCPV6)
 	if (net_if_flag_is_set(iface, NET_IF_IPV6)) {
-		PR("DHCPv6 renewal time (T1) : %llu ms\n",
-		   iface->config.dhcpv6.t1);
-		PR("DHCPv6 rebind time (T2)  : %llu ms\n",
-		   iface->config.dhcpv6.t2);
-		PR("DHCPv6 expire time       : %llu ms\n",
-		   iface->config.dhcpv6.expire);
-		if (iface->config.dhcpv6.params.request_addr) {
-			PR("DHCPv6 address           : %s\n",
-			   net_sprint_ipv6_addr(&iface->config.dhcpv6.addr));
-		}
+		if (iface->config.dhcpv6.state != NET_DHCPV6_DISABLED) {
+			PR("DHCPv6 renewal time (T1) : %llu ms\n",
+			   iface->config.dhcpv6.t1);
+			PR("DHCPv6 rebind time (T2)  : %llu ms\n",
+			   iface->config.dhcpv6.t2);
+			PR("DHCPv6 expire time       : %llu ms\n",
+			   iface->config.dhcpv6.expire);
+			if (iface->config.dhcpv6.params.request_addr) {
+				PR("DHCPv6 address           : %s\n",
+				   net_sprint_ipv6_addr(&iface->config.dhcpv6.addr));
+			}
 
-		if (iface->config.dhcpv6.params.request_prefix) {
-			PR("DHCPv6 prefix            : %s\n",
-			   net_sprint_ipv6_addr(&iface->config.dhcpv6.prefix));
+			if (iface->config.dhcpv6.params.request_prefix) {
+				PR("DHCPv6 prefix            : %s\n",
+				   net_sprint_ipv6_addr(&iface->config.dhcpv6.prefix));
+			}
 		}
 
 		PR("DHCPv6 state             : %s\n",
@@ -546,18 +603,23 @@ static void iface_cb(struct net_if *iface, void *user_data)
 
 #if defined(CONFIG_NET_DHCPV4)
 	if (net_if_flag_is_set(iface, NET_IF_IPV4)) {
-		PR("DHCPv4 lease time : %u\n",
-		   iface->config.dhcpv4.lease_time);
-		PR("DHCPv4 renew time : %u\n",
-		   iface->config.dhcpv4.renewal_time);
-		PR("DHCPv4 server     : %s\n",
-		   net_sprint_ipv4_addr(&iface->config.dhcpv4.server_id));
-		PR("DHCPv4 requested  : %s\n",
-		   net_sprint_ipv4_addr(&iface->config.dhcpv4.requested_ip));
+		if (iface->config.dhcpv4.state != NET_DHCPV4_DISABLED) {
+			PR("DHCPv4 lease time : %u\n",
+			   iface->config.dhcpv4.lease_time);
+			PR("DHCPv4 renew time : %u\n",
+			   iface->config.dhcpv4.renewal_time);
+			PR("DHCPv4 server     : %s\n",
+			   net_sprint_ipv4_addr(&iface->config.dhcpv4.server_id));
+			PR("DHCPv4 requested  : %s\n",
+			   net_sprint_ipv4_addr(&iface->config.dhcpv4.requested_ip));
+			PR("DHCPv4 state      : %s\n",
+			   net_dhcpv4_state_name(iface->config.dhcpv4.state));
+			PR("DHCPv4 attempts   : %d\n",
+			   iface->config.dhcpv4.attempts);
+		}
+
 		PR("DHCPv4 state      : %s\n",
 		   net_dhcpv4_state_name(iface->config.dhcpv4.state));
-		PR("DHCPv4 attempts   : %d\n",
-		   iface->config.dhcpv4.attempts);
 	}
 #endif /* CONFIG_NET_DHCPV4 */
 }
@@ -706,8 +768,10 @@ static int cmd_net_iface(const struct shell *sh, size_t argc, char *argv[])
 	}
 
 #if defined(CONFIG_NET_HOSTNAME_ENABLE)
-	PR("Hostname: %s\n\n", net_hostname_get());
+	PR("Hostname: %s\n", net_hostname_get());
 #endif
+	PR("Default interface: %d\n\n",
+	   net_if_get_by_iface(net_if_get_default()));
 
 	user_data.sh = sh;
 	user_data.user_data = iface;
@@ -717,6 +781,42 @@ static int cmd_net_iface(const struct shell *sh, size_t argc, char *argv[])
 	return 0;
 }
 
+static int cmd_net_default_iface(const struct shell *sh, size_t argc, char *argv[])
+{
+	struct net_if *iface = NULL;
+	int idx;
+
+	if (argc < 2) {
+		iface = net_if_get_default();
+		if (!iface) {
+			PR_WARNING("No default interface\n");
+			return -ENOEXEC;
+		}
+
+		idx = net_if_get_by_iface(iface);
+		PR("Default interface: %d\n", idx);
+	} else {
+		int new_idx;
+
+		idx = get_iface_idx(sh, argv[1]);
+		if (idx < 0) {
+			return -ENOEXEC;
+		}
+
+		net_if_set_default(net_if_get_by_index(idx));
+
+		new_idx = net_if_get_by_iface(net_if_get_default());
+		if (new_idx != idx) {
+			PR_WARNING("Failed to set default interface to %d\n", idx);
+			return -ENOEXEC;
+		}
+
+		PR("Default interface: %d\n", new_idx);
+	}
+
+	return 0;
+}
+
 #if defined(CONFIG_NET_SHELL_DYN_CMD_COMPLETION)
 
 #include "iface_dynamic.h"
@@ -738,6 +838,9 @@ SHELL_STATIC_SUBCMD_SET_CREATE(net_cmd_iface,
 	SHELL_CMD(set_mac, IFACE_DYN_CMD,
 		  "'net iface set_mac <index> <MAC>' sets MAC address for the network interface.",
 		  cmd_net_set_mac),
+	SHELL_CMD(default, IFACE_DYN_CMD,
+		  "'net iface default [<index>]' displays or sets the default network interface.",
+		  cmd_net_default_iface),
 	SHELL_SUBCMD_SET_END
 );
 
diff --git a/subsys/net/lib/shell/mem.c b/subsys/net/lib/shell/mem.c
index 400f1be8baa..1ba3a37fa76 100644
--- a/subsys/net/lib/shell/mem.c
+++ b/subsys/net/lib/shell/mem.c
@@ -114,19 +114,25 @@ static int cmd_net_mem(const struct shell *sh, size_t argc, char *argv[])
 	PR("Network buffer pools:\n");
 
 #if defined(CONFIG_NET_BUF_POOL_USAGE)
-	PR("Address\t\tTotal\tAvail\tName\n");
+	PR("Address\t\tTotal\tAvail\tMaxUsed\tName\n");
+#if defined(CONFIG_MEM_SLAB_TRACE_MAX_UTILIZATION)
+	PR("%p\t%d\t%u\t%u\tRX\n", rx, rx->info.num_blocks,
+	   k_mem_slab_num_free_get(rx), rx->info.max_used);
 
-	PR("%p\t%d\t%u\tRX\n",
+	PR("%p\t%d\t%u\t%u\tTX\n", tx, tx->info.num_blocks,
+	   k_mem_slab_num_free_get(tx), tx->info.max_used);
+#else
+	PR("%p\t%d\t%u\t-\tRX\n",
 	       rx, rx->info.num_blocks, k_mem_slab_num_free_get(rx));
 
-	PR("%p\t%d\t%u\tTX\n",
+	PR("%p\t%d\t%u\t-\tTX\n",
 	       tx, tx->info.num_blocks, k_mem_slab_num_free_get(tx));
+#endif
+	PR("%p\t%d\t%ld\t%d\tRX DATA (%s)\n", rx_data, rx_data->buf_count,
+	   atomic_get(&rx_data->avail_count), rx_data->max_used, rx_data->name);
 
-	PR("%p\t%d\t%ld\tRX DATA (%s)\n", rx_data, rx_data->buf_count,
-	   atomic_get(&rx_data->avail_count), rx_data->name);
-
-	PR("%p\t%d\t%ld\tTX DATA (%s)\n", tx_data, tx_data->buf_count,
-	   atomic_get(&tx_data->avail_count), tx_data->name);
+	PR("%p\t%d\t%ld\t%d\tTX DATA (%s)\n", tx_data, tx_data->buf_count,
+	   atomic_get(&tx_data->avail_count), tx_data->max_used, tx_data->name);
 #else
 	PR("Address\t\tTotal\tName\n");
 
diff --git a/subsys/net/lib/shell/net_shell_private.h b/subsys/net/lib/shell/net_shell_private.h
index ef9931e1397..130fe88f5bc 100644
--- a/subsys/net/lib/shell/net_shell_private.h
+++ b/subsys/net/lib/shell/net_shell_private.h
@@ -64,8 +64,12 @@ struct net_shell_user_data {
 #if !defined(NET_VLAN_MAX_COUNT)
 #define MAX_IFACE_COUNT NET_IF_MAX_CONFIGS
 #else
+#if NET_VLAN_MAX_COUNT > 0
 #define MAX_IFACE_COUNT NET_VLAN_MAX_COUNT
-#endif
+#else
+#define MAX_IFACE_COUNT NET_IF_MAX_CONFIGS
+#endif /* NET_VLAN_MAX_COUNT > 0 */
+#endif /* !NET_VLAN_MAX_COUNT */
 
 #if defined(CONFIG_NET_IPV6) && !defined(CONFIG_NET_IPV4)
 #define ADDR_LEN NET_IPV6_ADDR_LEN
diff --git a/subsys/net/lib/shell/route.c b/subsys/net/lib/shell/route.c
index 9e84860b1e2..f690beafd98 100644
--- a/subsys/net/lib/shell/route.c
+++ b/subsys/net/lib/shell/route.c
@@ -32,7 +32,7 @@ static void route_cb(struct net_route_entry *entry, void *user_data)
 	count = 0;
 
 	SYS_SLIST_FOR_EACH_CONTAINER(&entry->nexthop, nexthop_route, node) {
-		struct net_linkaddr_storage *lladdr;
+		struct net_linkaddr *lladdr;
 		char remaining_str[sizeof("01234567890 sec")];
 		uint32_t remaining;
 
diff --git a/subsys/net/lib/shell/stats.c b/subsys/net/lib/shell/stats.c
index 3556ec0269a..64256bc7473 100644
--- a/subsys/net/lib/shell/stats.c
+++ b/subsys/net/lib/shell/stats.c
@@ -368,22 +368,24 @@ static void print_tc_rx_stats(const struct shell *sh, struct net_if *iface)
 	PR("RX traffic class statistics:\n");
 
 #if defined(CONFIG_NET_PKT_RXTIME_STATS)
-	PR("TC  Priority\tRecv pkts\tbytes\ttime\n");
+	PR("TC  Priority\tRecv pkts\tDrop pkts\tbytes\ttime\n");
 
 	for (i = 0; i < NET_TC_RX_COUNT; i++) {
 		net_stats_t count = GET_STAT(iface,
 					     tc.recv[i].rx_time.count);
 		if (count == 0) {
-			PR("[%d] %s (%d)\t%d\t\t%d\t-\n", i,
+			PR("[%d] %s (%d)\t%d\t%d\t\t%d\t-\n", i,
 			   priority2str(GET_STAT(iface, tc.recv[i].priority)),
 			   GET_STAT(iface, tc.recv[i].priority),
 			   GET_STAT(iface, tc.recv[i].pkts),
+			   GET_STAT(iface, tc.recv[i].dropped),
 			   GET_STAT(iface, tc.recv[i].bytes));
 		} else {
-			PR("[%d] %s (%d)\t%d\t\t%d\t%u us%s\n", i,
+			PR("[%d] %s (%d)\t%d\t%d\t\t%d\t%u us%s\n", i,
 			   priority2str(GET_STAT(iface, tc.recv[i].priority)),
 			   GET_STAT(iface, tc.recv[i].priority),
 			   GET_STAT(iface, tc.recv[i].pkts),
+			   GET_STAT(iface, tc.recv[i].dropped),
 			   GET_STAT(iface, tc.recv[i].bytes),
 			   (uint32_t)(GET_STAT(iface,
 					    tc.recv[i].rx_time.sum) /
@@ -392,13 +394,14 @@ static void print_tc_rx_stats(const struct shell *sh, struct net_if *iface)
 		}
 	}
 #else
-	PR("TC  Priority\tRecv pkts\tbytes\n");
+	PR("TC  Priority\tRecv pkts\tDrop pkts\tbytes\n");
 
 	for (i = 0; i < NET_TC_RX_COUNT; i++) {
-		PR("[%d] %s (%d)\t%d\t\t%d\n", i,
+		PR("[%d] %s (%d)\t%d\t%d\t\t%d\n", i,
 		   priority2str(GET_STAT(iface, tc.recv[i].priority)),
 		   GET_STAT(iface, tc.recv[i].priority),
 		   GET_STAT(iface, tc.recv[i].pkts),
+		   GET_STAT(iface, tc.recv[i].dropped),
 		   GET_STAT(iface, tc.recv[i].bytes));
 	}
 #endif /* CONFIG_NET_PKT_RXTIME_STATS */
@@ -556,6 +559,21 @@ static void net_shell_print_statistics(struct net_if *iface, void *user_data)
 	   GET_STAT(iface, dns.sent),
 	   GET_STAT(iface, dns.drop));
 #endif /* CONFIG_NET_STATISTICS_DNS */
+#if defined(CONFIG_NET_STATISTICS_PKT_FILTER)
+	PR("Filter drop rx %d"
+	   IF_ENABLED(CONFIG_NET_PKT_FILTER_IPV4_HOOK, ("\tIPv4\t%d"))
+	   IF_ENABLED(CONFIG_NET_PKT_FILTER_IPV6_HOOK, ("\tIPv6\t%d"))
+	   IF_ENABLED(CONFIG_NET_PKT_FILTER_LOCAL_IN_HOOK, ("\tlocal\t%d"))
+	   "\ttx\t%d\n",
+	   GET_STAT(iface, pkt_filter.rx.drop),
+	   IF_ENABLED(CONFIG_NET_PKT_FILTER_IPV4_HOOK,
+		      (GET_STAT(iface, pkt_filter.rx.ipv4_drop),))
+	   IF_ENABLED(CONFIG_NET_PKT_FILTER_IPV6_HOOK,
+		      (GET_STAT(iface, pkt_filter.rx.ipv6_drop),))
+	   IF_ENABLED(CONFIG_NET_PKT_FILTER_LOCAL_IN_HOOK,
+		      (GET_STAT(iface, pkt_filter.rx.local_drop),))
+	   GET_STAT(iface, pkt_filter.tx.drop));
+#endif /* CONFIG_NET_STATISTICS_DNS */
 
 	PR("Bytes received %u\n", GET_STAT(iface, bytes.received));
 	PR("Bytes sent     %u\n", GET_STAT(iface, bytes.sent));
diff --git a/subsys/net/lib/sntp/sntp.c b/subsys/net/lib/sntp/sntp.c
index f7ac8cd5669..c6be0b80ae3 100644
--- a/subsys/net/lib/sntp/sntp.c
+++ b/subsys/net/lib/sntp/sntp.c
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2017 Linaro Limited
  * Copyright (c) 2019 Intel Corporation
+ * Copyright (c) 2024 Embeint Inc
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -181,16 +182,11 @@ int sntp_init(struct sntp_ctx *ctx, struct sockaddr *addr, socklen_t addr_len)
 	return 0;
 }
 
-int sntp_query(struct sntp_ctx *ctx, uint32_t timeout, struct sntp_time *ts)
+static int sntp_query_send(struct sntp_ctx *ctx)
 {
 	struct sntp_pkt tx_pkt = { 0 };
-	int ret = 0;
 	int64_t ts_us = 0;
 
-	if (!ctx || !ts) {
-		return -EFAULT;
-	}
-
 	/* prepare request pkt */
 	tx_pkt.li = 0;
 	tx_pkt.vn = SNTP_VERSION_NUMBER;
@@ -201,7 +197,18 @@ int sntp_query(struct sntp_ctx *ctx, uint32_t timeout, struct sntp_time *ts)
 	tx_pkt.tx_tm_s = htonl(ctx->expected_orig_ts.seconds);
 	tx_pkt.tx_tm_f = htonl(ctx->expected_orig_ts.fraction);
 
-	ret = zsock_send(ctx->sock.fd, (uint8_t *)&tx_pkt, sizeof(tx_pkt), 0);
+	return zsock_send(ctx->sock.fd, (uint8_t *)&tx_pkt, sizeof(tx_pkt), 0);
+}
+
+int sntp_query(struct sntp_ctx *ctx, uint32_t timeout, struct sntp_time *ts)
+{
+	int ret = 0;
+
+	if (!ctx || !ts) {
+		return -EFAULT;
+	}
+
+	ret = sntp_query_send(ctx);
 	if (ret < 0) {
 		NET_ERR("Failed to send over UDP socket %d", ret);
 		return ret;
@@ -248,3 +255,76 @@ void sntp_close(struct sntp_ctx *ctx)
 		(void)zsock_close(ctx->sock.fd);
 	}
 }
+
+#ifdef CONFIG_NET_SOCKETS_SERVICE
+
+int sntp_init_async(struct sntp_ctx *ctx, struct sockaddr *addr, socklen_t addr_len,
+		    const struct net_socket_service_desc *service)
+{
+	int ret;
+
+	/* Validate service pointer */
+	if (service == NULL) {
+		return -EFAULT;
+	}
+	/* Standard init */
+	ret = sntp_init(ctx, addr, addr_len);
+	if (ret < 0) {
+		return ret;
+	}
+	/* Attach socket to socket service */
+	ret = net_socket_service_register(service, ctx->sock.fds, ctx->sock.nfds, ctx);
+	if (ret < 0) {
+		NET_ERR("Failed to register socket %d", ret);
+		/* Cleanup init on register failure*/
+		sntp_close(ctx);
+	}
+	return ret;
+}
+
+int sntp_send_async(struct sntp_ctx *ctx)
+{
+	int ret = 0;
+
+	if (!ctx) {
+		return -EFAULT;
+	}
+
+	ret = sntp_query_send(ctx);
+	if (ret < 0) {
+		NET_ERR("Failed to send over UDP socket %d", ret);
+		return ret;
+	}
+	return 0;
+}
+
+int sntp_read_async(struct net_socket_service_event *event, struct sntp_time *ts)
+{
+	struct sntp_ctx *ctx = event->user_data;
+	struct sntp_pkt buf = {0};
+	int rcvd;
+
+	rcvd = zsock_recv(ctx->sock.fd, (uint8_t *)&buf, sizeof(buf), 0);
+	if (rcvd < 0) {
+		return -errno;
+	}
+
+	if (rcvd != sizeof(struct sntp_pkt)) {
+		return -EMSGSIZE;
+	}
+
+	return parse_response((uint8_t *)&buf, sizeof(buf), &ctx->expected_orig_ts, ts);
+}
+
+void sntp_close_async(const struct net_socket_service_desc *service)
+{
+	struct sntp_ctx *ctx = service->pev->user_data;
+	/* Detach socket from socket service */
+	net_socket_service_unregister(service);
+	/* CLose the socket */
+	if (ctx) {
+		(void)zsock_close(ctx->sock.fd);
+	}
+}
+
+#endif /* CONFIG_NET_SOCKETS_SERVICE */
diff --git a/subsys/net/lib/sockets/Kconfig b/subsys/net/lib/sockets/Kconfig
index 0669846a963..0f4a27e655a 100644
--- a/subsys/net/lib/sockets/Kconfig
+++ b/subsys/net/lib/sockets/Kconfig
@@ -116,6 +116,10 @@ config NET_SOCKETS_SOCKOPT_TLS
 	imply TLS_CREDENTIALS
 	select MBEDTLS if NET_NATIVE
 	imply MBEDTLS_TLS_VERSION_1_2 if !NET_L2_OPENTHREAD
+	imply MBEDTLS_MD if !NET_L2_OPENTHREAD
+	imply MBEDTLS_RSA_C if !NET_L2_OPENTHREAD
+	imply MBEDTLS_PKCS1_V15 if !NET_L2_OPENTHREAD
+	imply MBEDTLS_PKCS1_V21 if !NET_L2_OPENTHREAD
 	imply MBEDTLS_KEY_EXCHANGE_RSA_ENABLED if !NET_L2_OPENTHREAD
 	imply MBEDTLS_CIPHER_AES_ENABLED if !NET_L2_OPENTHREAD
 	imply PSA_WANT_KEY_TYPE_AES if !NET_L2_OPENTHREAD && PSA_CRYPTO_CLIENT
@@ -306,6 +310,13 @@ config NET_SOCKETS_PACKET_DGRAM
 	  on the information in the sockaddr_ll destination address before
 	  they are queued.
 
+config NET_SOCKETS_INET_RAW
+	bool "AF_INET/AF_INET6 and SOCK_RAW sockets support"
+	depends on NET_NATIVE_IP
+	help
+	  Support SOCK_RAW socket type for AF_INET/AF_INET6 sockets. This allows
+	  to receive raw IP datagrams before further processing takes place.
+
 config NET_SOCKETS_CAN
 	bool "Socket CAN support [EXPERIMENTAL]"
 	select NET_L2_CANBUS_RAW
@@ -324,7 +335,6 @@ config NET_SOCKETS_CAN_RECEIVERS
 
 config NET_SOCKETPAIR
 	bool "Support for socketpair"
-	select PIPES
 	help
 	  Communicate over a pair of connected, unnamed UNIX domain sockets.
 
@@ -338,7 +348,7 @@ config NET_SOCKETPAIR_BUFFER_SIZE
 	help
 	  Buffer size for socketpair(2)
 
-choice
+choice NET_SOCKETPAIR_ALLOCATION_STRATEGY
 	prompt "Memory management for socketpair"
 	default NET_SOCKETPAIR_HEAP if KERNEL_MEM_POOL
 
@@ -354,7 +364,8 @@ if NET_SOCKETPAIR_STATIC
 
 config NET_SOCKETPAIR_MAX
 	int "How many socketpairs to pre-allocate"
-	default 6 if WIFI_NM_WPA_SUPPLICANT
+	default 6 if WIFI_NM_HOSTAPD_AP
+	default 4 if WIFI_NM_WPA_SUPPLICANT
 	default 1
 
 endif # NET_SOCKETPAIR_STATIC
@@ -363,8 +374,8 @@ if NET_SOCKETPAIR_HEAP
 
 config HEAP_MEM_POOL_ADD_SIZE_SOCKETPAIR
 	int
-	default 13696 if WIFI_NM_HOSTAPD_AP
-	default 9120 if WIFI_NM_WPA_SUPPLICANT
+	default 9136 if WIFI_NM_HOSTAPD_AP
+	default 6852 if WIFI_NM_WPA_SUPPLICANT
 	default 256
 
 endif # NET_SOCKETPAIR_HEAP
diff --git a/subsys/net/lib/sockets/socketpair.c b/subsys/net/lib/sockets/socketpair.c
index 8f2e1961e8a..b89a292e1fd 100644
--- a/subsys/net/lib/sockets/socketpair.c
+++ b/subsys/net/lib/sockets/socketpair.c
@@ -47,7 +47,7 @@ __net_socket struct spair {
 	int remote; /**< the remote endpoint file descriptor */
 	uint32_t flags; /**< status and option bits */
 	struct k_sem sem; /**< semaphore for exclusive structure access */
-	struct k_pipe recv_q; /**< receive queue of local endpoint */
+	struct ring_buf recv_q;
 	/** indicates local @a recv_q isn't empty */
 	struct k_poll_signal readable;
 	/** indicates local @a recv_q isn't full */
@@ -106,7 +106,7 @@ static inline size_t spair_write_avail(struct spair *spair)
 		return 0;
 	}
 
-	return k_pipe_write_avail(&remote->recv_q);
+	return ring_buf_space_get(&remote->recv_q);
 }
 
 /**
@@ -117,7 +117,7 @@ static inline size_t spair_write_avail(struct spair *spair)
  */
 static inline size_t spair_read_avail(struct spair *spair)
 {
-	return k_pipe_read_avail(&spair->recv_q);
+	return ring_buf_size_get(&spair->recv_q);
 }
 
 /** Swap two 32-bit integers */
@@ -250,7 +250,7 @@ static struct spair *spair_new(void)
 	spair->flags = SPAIR_FLAGS_DEFAULT;
 
 	k_sem_init(&spair->sem, 1, 1);
-	k_pipe_init(&spair->recv_q, spair->buf, sizeof(spair->buf));
+	ring_buf_init(&spair->recv_q, sizeof(spair->buf), spair->buf);
 	k_poll_signal_init(&spair->readable);
 	k_poll_signal_init(&spair->writeable);
 
@@ -550,10 +550,7 @@ static ssize_t spair_write(void *obj, const void *buffer, size_t count)
 		}
 	}
 
-	res = k_pipe_put(&remote->recv_q, (void *)buffer, count,
-			 &bytes_written, 1, K_NO_WAIT);
-	__ASSERT(res == 0, "k_pipe_put() failed: %d", res);
-
+	bytes_written = ring_buf_put(&remote->recv_q, (void *)buffer, count);
 	if (spair_write_avail(spair) == 0) {
 		k_poll_signal_reset(&remote->writeable);
 	}
@@ -724,10 +721,7 @@ static ssize_t spair_read(void *obj, void *buffer, size_t count)
 		}
 	}
 
-	res = k_pipe_get(&spair->recv_q, (void *)buffer, count, &bytes_read,
-			 1, K_NO_WAIT);
-	__ASSERT(res == 0, "k_pipe_get() failed: %d", res);
-
+	bytes_read = ring_buf_get(&spair->recv_q, (void *)buffer, count);
 	if (spair_read_avail(spair) == 0 && !sock_is_eof(spair)) {
 		k_poll_signal_reset(&spair->readable);
 	}
diff --git a/subsys/net/lib/sockets/sockets_inet.c b/subsys/net/lib/sockets/sockets_inet.c
index 83326b0b384..34d8eabbb31 100644
--- a/subsys/net/lib/sockets/sockets_inet.c
+++ b/subsys/net/lib/sockets/sockets_inet.c
@@ -2,6 +2,7 @@
  * Copyright (c) 2017 Linaro Limited
  * Copyright (c) 2021 Nordic Semiconductor
  * Copyright (c) 2023 Arm Limited (or its affiliates). All rights reserved.
+ * Copyright (c) 2025 Aerlync Labs Inc.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -35,6 +36,10 @@ LOG_MODULE_DECLARE(net_sock, CONFIG_NET_SOCKETS_LOG_LEVEL);
 #include "../../ip/tcp_internal.h"
 #include "../../ip/net_private.h"
 
+#if defined(CONFIG_NET_SOCKETS_INET_RAW)
+BUILD_ASSERT(IPPROTO_IP == 0, "Wildcard IPPROTO_IP must equal 0.");
+#endif
+
 const struct socket_op_vtable sock_fd_op_vtable;
 
 static void zsock_received_cb(struct net_context *ctx,
@@ -63,6 +68,11 @@ static void zsock_flush_queue(struct net_context *ctx)
 	while ((p = k_fifo_get(&ctx->recv_q, K_NO_WAIT)) != NULL) {
 		if (is_listen) {
 			NET_DBG("discarding ctx %p", p);
+
+			/* Note that we must release all the packets we
+			 * might have received to the accepted socket.
+			 */
+			zsock_flush_queue(p);
 			net_context_put(p);
 		} else {
 			NET_DBG("discarding pkt %p", p);
@@ -308,11 +318,12 @@ int zsock_bind_ctx(struct net_context *ctx, const struct sockaddr *addr,
 		return -1;
 	}
 
-	/* For DGRAM socket, we expect to receive packets after call to
+	/* For DGRAM or RAW socket, we expect to receive packets after call to
 	 * bind(), but for STREAM socket, next expected operation is
 	 * listen(), which doesn't work if recv callback is set.
 	 */
-	if (net_context_get_type(ctx) == SOCK_DGRAM) {
+	if (net_context_get_type(ctx) == SOCK_DGRAM ||
+	    net_context_get_type(ctx) == SOCK_RAW) {
 		ret = net_context_recv(ctx, zsock_received_cb, K_NO_WAIT,
 				       ctx->user_data);
 		if (ret < 0) {
@@ -339,6 +350,11 @@ int zsock_connect_ctx(struct net_context *ctx, const struct sockaddr *addr,
 	net_context_connect_cb_t cb = NULL;
 	int ret;
 
+	if (net_context_get_type(ctx) == SOCK_RAW) {
+		errno = EOPNOTSUPP;
+		return -1;
+	}
+
 #if defined(CONFIG_SOCKS)
 	if (net_context_is_proxy_enabled(ctx)) {
 		ret = net_socks5_connect(ctx, addr, addrlen);
@@ -414,6 +430,11 @@ int zsock_listen_ctx(struct net_context *ctx, int backlog)
 {
 	int ret;
 
+	if (net_context_get_type(ctx) == SOCK_RAW) {
+		errno = EOPNOTSUPP;
+		return -1;
+	}
+
 	ret = net_context_listen(ctx, backlog);
 	if (ret < 0) {
 		errno = -ret;
@@ -436,6 +457,11 @@ int zsock_accept_ctx(struct net_context *parent, struct sockaddr *addr,
 	struct net_pkt *last_pkt;
 	int fd, ret;
 
+	if (net_context_get_type(parent) == SOCK_RAW) {
+		errno = EOPNOTSUPP;
+		return -1;
+	}
+
 	if (!sock_is_nonblock(parent)) {
 		k_timeout_t timeout = K_FOREVER;
 
@@ -689,14 +715,16 @@ ssize_t zsock_sendmsg_ctx(struct net_context *ctx, const struct msghdr *msg,
 	return status;
 }
 
-static int sock_get_pkt_src_addr(struct net_pkt *pkt,
-				 enum net_ip_protocol proto,
+static int sock_get_pkt_src_addr(struct net_context *ctx,
+				 struct net_pkt *pkt,
 				 struct sockaddr *addr,
 				 socklen_t addrlen)
 {
 	int ret = 0;
 	struct net_pkt_cursor backup;
 	uint16_t *port;
+	enum net_ip_protocol proto = net_context_get_proto(ctx);
+	enum net_sock_type type = net_context_get_type(ctx);
 
 	if (!addr || !pkt) {
 		return -EINVAL;
@@ -782,6 +810,8 @@ static int sock_get_pkt_src_addr(struct net_pkt *pkt,
 		}
 
 		*port = tcp_hdr->src_port;
+	} else if (IS_ENABLED(CONFIG_NET_SOCKETS_INET_RAW) && type == SOCK_RAW) {
+		*port = 0;
 	} else {
 		ret = -ENOTSUP;
 	}
@@ -1047,13 +1077,13 @@ static int update_msg_controllen(struct msghdr *msg)
 	return 0;
 }
 
-static inline ssize_t zsock_recv_dgram(struct net_context *ctx,
-				       struct msghdr *msg,
-				       void *buf,
-				       size_t max_len,
-				       int flags,
-				       struct sockaddr *src_addr,
-				       socklen_t *addrlen)
+static ssize_t zsock_recv_dgram(struct net_context *ctx,
+				struct msghdr *msg,
+				void *buf,
+				size_t max_len,
+				int flags,
+				struct sockaddr *src_addr,
+				socklen_t *addrlen)
 {
 	k_timeout_t timeout = K_FOREVER;
 	size_t recv_len = 0;
@@ -1112,8 +1142,7 @@ static inline ssize_t zsock_recv_dgram(struct net_context *ctx,
 		} else {
 			int ret;
 
-			ret = sock_get_pkt_src_addr(pkt, net_context_get_proto(ctx),
-						   src_addr, *addrlen);
+			ret = sock_get_pkt_src_addr(ctx, pkt, src_addr, *addrlen);
 			if (ret < 0) {
 				errno = -ret;
 				NET_DBG("sock_get_pkt_src_addr %d", ret);
@@ -1164,7 +1193,6 @@ static inline ssize_t zsock_recv_dgram(struct net_context *ctx,
 
 			if (len <= tmp_read_len) {
 				tmp_read_len -= len;
-				msg->msg_iov[iovec].iov_len = len;
 				iovec++;
 			} else {
 				errno = EINVAL;
@@ -1172,8 +1200,6 @@ static inline ssize_t zsock_recv_dgram(struct net_context *ctx,
 			}
 		}
 
-		msg->msg_iovlen = iovec;
-
 		if (recv_len != read_len) {
 			msg->msg_flags |= ZSOCK_MSG_TRUNC;
 		}
@@ -1325,7 +1351,7 @@ static ssize_t zsock_recv_stream_timed(struct net_context *ctx, struct msghdr *m
 {
 	int res;
 	k_timepoint_t end;
-	size_t recv_len = 0, iovec = 0, available_len, max_iovlen = 0;
+	size_t recv_len = 0, iovec = 0, available_len;
 	const bool waitall = (flags & ZSOCK_MSG_WAITALL) == ZSOCK_MSG_WAITALL;
 
 	if (msg != NULL && buf == NULL) {
@@ -1335,8 +1361,6 @@ static ssize_t zsock_recv_stream_timed(struct net_context *ctx, struct msghdr *m
 
 		buf = msg->msg_iov[iovec].iov_base;
 		available_len = msg->msg_iov[iovec].iov_len;
-		msg->msg_iov[iovec].iov_len = 0;
-		max_iovlen = msg->msg_iovlen;
 	}
 
 	for (end = sys_timepoint_calc(timeout); max_len > 0; timeout = sys_timepoint_timeout(end)) {
@@ -1365,7 +1389,6 @@ static ssize_t zsock_recv_stream_timed(struct net_context *ctx, struct msghdr *m
 				return -EAGAIN;
 			}
 
-			msg->msg_iov[iovec].iov_len += res;
 			buf = (uint8_t *)(msg->msg_iov[iovec].iov_base) + res;
 			max_len -= res;
 
@@ -1373,14 +1396,12 @@ static ssize_t zsock_recv_stream_timed(struct net_context *ctx, struct msghdr *m
 				/* All data to this iovec was written */
 				iovec++;
 
-				if (iovec == max_iovlen) {
+				if (iovec == msg->msg_iovlen) {
 					break;
 				}
 
-				msg->msg_iovlen = iovec;
 				buf = msg->msg_iov[iovec].iov_base;
 				available_len = msg->msg_iov[iovec].iov_len;
-				msg->msg_iov[iovec].iov_len = 0;
 
 				/* If there is more data, read it now and do not wait */
 				if (buf != NULL && available_len > 0) {
@@ -1462,7 +1483,7 @@ ssize_t zsock_recvfrom_ctx(struct net_context *ctx, void *buf, size_t max_len,
 		return 0;
 	}
 
-	if (sock_type == SOCK_DGRAM) {
+	if (sock_type == SOCK_DGRAM || sock_type == SOCK_RAW) {
 		return zsock_recv_dgram(ctx, NULL, buf, max_len, flags, src_addr, addrlen);
 	} else if (sock_type == SOCK_STREAM) {
 		return zsock_recv_stream(ctx, NULL, buf, max_len, flags);
@@ -1495,7 +1516,7 @@ ssize_t zsock_recvmsg_ctx(struct net_context *ctx, struct msghdr *msg,
 		max_len += msg->msg_iov[i].iov_len;
 	}
 
-	if (sock_type == SOCK_DGRAM) {
+	if (sock_type == SOCK_DGRAM || sock_type == SOCK_RAW) {
 		return zsock_recv_dgram(ctx, msg, NULL, max_len, flags,
 					msg->msg_name, &msg->msg_namelen);
 	} else if (sock_type == SOCK_STREAM) {
@@ -1567,7 +1588,9 @@ static int zsock_poll_update_ctx(struct net_context *ctx,
 	ARG_UNUSED(ctx);
 
 	if (pfd->events & ZSOCK_POLLIN) {
-		if ((*pev)->state != K_POLL_STATE_NOT_READY || sock_is_eof(ctx)) {
+		if (((*pev)->state != K_POLL_STATE_NOT_READY &&
+		     (*pev)->state != K_POLL_STATE_CANCELLED) ||
+		    sock_is_eof(ctx)) {
 			pfd->revents |= ZSOCK_POLLIN;
 		}
 		(*pev)++;
@@ -1974,6 +1997,18 @@ int zsock_getsockopt_ctx(struct net_context *ctx, int level, int optname,
 			}
 
 			break;
+#if defined(CONFIG_NET_IPV4)
+		case IP_MULTICAST_LOOP:
+			ret = net_context_get_option(ctx,
+						     NET_OPT_IPV4_MCAST_LOOP,
+						     optval, optlen);
+			if (ret < 0) {
+				errno  = -ret;
+				return -1;
+			}
+
+			return 0;
+#endif
 		}
 
 		break;
@@ -2081,6 +2116,18 @@ int zsock_getsockopt_ctx(struct net_context *ctx, int level, int optname,
 			}
 
 			return 0;
+
+		case IPV6_MULTICAST_LOOP:
+			ret = net_context_get_option(ctx,
+						     NET_OPT_IPV6_MCAST_LOOP,
+						     optval, optlen);
+			if (ret < 0) {
+				errno = -ret;
+				return -1;
+			}
+
+			return 0;
+
 		}
 
 		break;
@@ -2592,6 +2639,18 @@ int zsock_setsockopt_ctx(struct net_context *ctx, int level, int optname,
 			}
 
 			break;
+#if defined(CONFIG_NET_IPV4)
+		case IP_MULTICAST_LOOP:
+			ret = net_context_set_option(ctx,
+						     NET_OPT_IPV4_MCAST_LOOP,
+						     optval, optlen);
+			if (ret < 0) {
+				errno  = -ret;
+				return -1;
+			}
+
+			return 0;
+#endif
 		}
 
 		break;
@@ -2723,6 +2782,17 @@ int zsock_setsockopt_ctx(struct net_context *ctx, int level, int optname,
 			}
 
 			break;
+
+		case IPV6_MULTICAST_LOOP:
+			ret = net_context_set_option(ctx,
+						     NET_OPT_IPV6_MCAST_LOOP,
+						     optval, optlen);
+			if (ret < 0) {
+				errno = -ret;
+				return -1;
+			}
+
+			return 0;
 		}
 
 		break;
@@ -2737,6 +2807,11 @@ int zsock_getpeername_ctx(struct net_context *ctx, struct sockaddr *addr,
 {
 	socklen_t newlen = 0;
 
+	if (net_context_get_type(ctx) == SOCK_RAW) {
+		errno = EOPNOTSUPP;
+		return -1;
+	}
+
 	if (addr == NULL || addrlen == NULL) {
 		errno = EINVAL;
 		return -1;
diff --git a/subsys/net/lib/sockets/sockets_packet.c b/subsys/net/lib/sockets/sockets_packet.c
index ec2d7e18539..508520c430d 100644
--- a/subsys/net/lib/sockets/sockets_packet.c
+++ b/subsys/net/lib/sockets/sockets_packet.c
@@ -51,11 +51,7 @@ static int zpacket_socket(int family, int type, int proto)
 		return -1;
 	}
 
-	if (proto == 0) {
-		if (type == SOCK_RAW) {
-			proto = IPPROTO_RAW;
-		}
-	} else {
+	if (proto != 0) {
 		/* For example in Linux, the protocol parameter can be given
 		 * as htons(ETH_P_ALL) to receive all the network packets.
 		 * So convert the proto field back to host byte order so that
@@ -148,7 +144,7 @@ static void zpacket_set_eth_pkttype(struct net_if *iface,
 				    struct sockaddr_ll *addr,
 				    struct net_linkaddr *lladdr)
 {
-	if (lladdr == NULL || lladdr->addr == NULL) {
+	if (lladdr == NULL || lladdr->len == 0) {
 		return;
 	}
 
@@ -187,7 +183,7 @@ static void zpacket_set_source_addr(struct net_context *ctx,
 		memcpy(addr.sll_addr, pkt->lladdr_src.addr,
 		       MIN(sizeof(addr.sll_addr), pkt->lladdr_src.len));
 
-		addr.sll_protocol = net_pkt_ll_proto_type(pkt);
+		addr.sll_protocol = htons(net_pkt_ll_proto_type(pkt));
 
 		if (net_if_get_link_addr(iface)->type == NET_LINK_ETHERNET) {
 			addr.sll_hatype = ARPHRD_ETHER;
@@ -216,12 +212,12 @@ static void zpacket_set_source_addr(struct net_context *ctx,
 		memcpy(addr.sll_addr, hdr->src.addr,
 		       sizeof(struct net_eth_addr));
 
-		addr.sll_protocol = ntohs(hdr->type);
+		addr.sll_protocol = hdr->type;
 		addr.sll_hatype = ARPHRD_ETHER;
 
-		dst_addr.addr = hdr->dst.addr;
-		dst_addr.len = sizeof(struct net_eth_addr);
-		dst_addr.type = NET_LINK_ETHERNET;
+		(void)net_linkaddr_create(&dst_addr, hdr->dst.addr,
+					  sizeof(struct net_eth_addr),
+					  NET_LINK_ETHERNET);
 
 		zpacket_set_eth_pkttype(iface, &addr, &dst_addr);
 		net_pkt_cursor_restore(pkt, &cur);
@@ -238,6 +234,7 @@ ssize_t zpacket_sendto_ctx(struct net_context *ctx, const void *buf, size_t len,
 			   int flags, const struct sockaddr *dest_addr,
 			   socklen_t addrlen)
 {
+	const struct sockaddr_ll *ll_addr = (const struct sockaddr_ll *)dest_addr;
 	k_timeout_t timeout = K_FOREVER;
 	int status;
 
@@ -252,6 +249,21 @@ ssize_t zpacket_sendto_ctx(struct net_context *ctx, const void *buf, size_t len,
 		net_context_get_option(ctx, NET_OPT_SNDTIMEO, &timeout, NULL);
 	}
 
+	/* If no interface was set on the context yet, use the one provided in
+	 * the destination address for default binding, unless 0 (any interface)
+	 * was set, in that case let the stack choose the default.
+	 */
+	if (net_context_get_iface(ctx) == NULL && ll_addr->sll_ifindex != 0) {
+		struct net_if *iface = net_if_get_by_index(ll_addr->sll_ifindex);
+
+		if (iface == NULL) {
+			errno = EDESTADDRREQ;
+			return -1;
+		}
+
+		net_context_set_iface(ctx, iface);
+	}
+
 	/* Register the callback before sending in order to receive the response
 	 * from the peer.
 	 */
@@ -490,13 +502,13 @@ static bool packet_is_supported(int family, int type, int proto)
 	switch (type) {
 	case SOCK_RAW:
 		proto = ntohs(proto);
-		return proto == ETH_P_ALL
+		return proto == 0
+		  || proto == ETH_P_ALL
 		  || proto == ETH_P_ECAT
-		  || proto == ETH_P_IEEE802154
-		  || proto == IPPROTO_RAW;
+		  || proto == ETH_P_IEEE802154;
 
 	case SOCK_DGRAM:
-		return proto > 0;
+		return true;
 
 	default:
 		return false;
diff --git a/subsys/net/lib/sockets/sockets_service.c b/subsys/net/lib/sockets/sockets_service.c
index 827c78bc10b..aac226f64f7 100644
--- a/subsys/net/lib/sockets/sockets_service.c
+++ b/subsys/net/lib/sockets/sockets_service.c
@@ -71,9 +71,9 @@ int z_impl_net_socket_service_register(const struct net_socket_service_desc *svc
 		goto out;
 	}
 
-	if (fds == NULL) {
-		cleanup_svc_events(svc);
-	} else {
+	cleanup_svc_events(svc);
+
+	if (fds != NULL) {
 		if (len > svc->pev_len) {
 			NET_DBG("Too many file descriptors, "
 				"max is %d for service %p",
@@ -121,22 +121,15 @@ static struct net_socket_service_desc *find_svc_and_event(
  */
 void net_socket_service_callback(struct net_socket_service_event *pev)
 {
-	struct net_socket_service_desc *svc = pev->svc;
 	struct net_socket_service_event ev = *pev;
 
 	ev.callback(&ev);
-
-	/* Copy back the socket fd to the global array because we marked
-	 * it as -1 when triggering the work.
-	 */
-	for (int i = 0; i < svc->pev_len; i++) {
-		ctx.events[get_idx(svc) + i] = svc->pev[i].event;
-	}
 }
 
 static int call_work(struct zsock_pollfd *pev, struct net_socket_service_event *event)
 {
 	int ret = 0;
+	int fd = pev->fd;
 
 	/* Mark the global fd non pollable so that we do not
 	 * call the callback second time.
@@ -146,8 +139,10 @@ static int call_work(struct zsock_pollfd *pev, struct net_socket_service_event *
 	/* Synchronous call */
 	net_socket_service_callback(event);
 
-	return ret;
+	/* Restore the fd so that new data can be re-triggered */
+	pev->fd = fd;
 
+	return ret;
 }
 
 static int trigger_work(struct zsock_pollfd *pev)
@@ -245,12 +240,7 @@ static void socket_service_thread(void)
 			break;
 		}
 
-		if (ret > 0 && ctx.events[0].revents) {
-			zvfs_eventfd_read(ctx.events[0].fd, &value);
-			NET_DBG("Received restart event.");
-			goto restart;
-		}
-
+		/* Process work here */
 		for (i = 1; i < (count + 1); i++) {
 			if (ctx.events[i].fd < 0) {
 				continue;
@@ -260,9 +250,18 @@ static void socket_service_thread(void)
 				ret = trigger_work(&ctx.events[i]);
 				if (ret < 0) {
 					NET_DBG("Triggering work failed (%d)", ret);
+					goto restart;
 				}
 			}
 		}
+
+		/* Relocate after trigger work so the work gets done before restarting */
+		if (ret > 0 && ctx.events[0].revents) {
+			zvfs_eventfd_read(ctx.events[0].fd, &value);
+			ctx.events[0].revents = 0;
+			NET_DBG("Received restart event.");
+			goto restart;
+		}
 	}
 
 out:
diff --git a/subsys/net/lib/tls_credentials/tls_credentials_shell.c b/subsys/net/lib/tls_credentials/tls_credentials_shell.c
index 78b279840a4..8ab9d4a7052 100644
--- a/subsys/net/lib/tls_credentials/tls_credentials_shell.c
+++ b/subsys/net/lib/tls_credentials/tls_credentials_shell.c
@@ -561,7 +561,7 @@ static int tls_cred_cmd_del(const struct shell *sh, size_t argc, char *argv[])
 		goto cleanup;
 	}
 
-	ref_slot = find_ref_slot(cred->buf);
+	ref_slot = cred->buf != NULL ? find_ref_slot(cred->buf) : -1;
 	if (ref_slot >= 0) {
 		/* This was a credential we copied to heap. Clear and free it. */
 		memset(&cred_refs[ref_slot], 0, cred->len);
diff --git a/subsys/net/lib/websocket/websocket.c b/subsys/net/lib/websocket/websocket.c
index 12eddd04f4b..5e35c981f49 100644
--- a/subsys/net/lib/websocket/websocket.c
+++ b/subsys/net/lib/websocket/websocket.c
@@ -421,7 +421,7 @@ static int websocket_interal_disconnect(struct websocket_context *ctx)
 	NET_DBG("[%p] Disconnecting", ctx);
 
 	ret = websocket_send_msg(ctx->sock, NULL, 0, WEBSOCKET_OPCODE_CLOSE,
-				 true, true, SYS_FOREVER_MS);
+				 ctx->is_client, true, SYS_FOREVER_MS);
 	if (ret < 0) {
 		NET_DBG("[%p] Failed to send close message (err %d).", ctx, ret);
 	}
diff --git a/subsys/net/lib/wifi_credentials/wifi_credentials.c b/subsys/net/lib/wifi_credentials/wifi_credentials.c
index 6239ebeb3ff..d7db5593e31 100644
--- a/subsys/net/lib/wifi_credentials/wifi_credentials.c
+++ b/subsys/net/lib/wifi_credentials/wifi_credentials.c
@@ -132,12 +132,7 @@ int wifi_credentials_get_by_ssid_personal_struct(const char *ssid, size_t ssid_l
 		goto exit;
 	}
 
-	if (buf->header.type != WIFI_SECURITY_TYPE_NONE &&
-	    buf->header.type != WIFI_SECURITY_TYPE_PSK &&
-	    buf->header.type != WIFI_SECURITY_TYPE_PSK_SHA256 &&
-	    buf->header.type != WIFI_SECURITY_TYPE_SAE &&
-	    buf->header.type != WIFI_SECURITY_TYPE_EAP_TLS &&
-	    buf->header.type != WIFI_SECURITY_TYPE_WPA_PSK) {
+	if (buf->header.type < 0 || buf->header.type > WIFI_SECURITY_TYPE_MAX) {
 		LOG_ERR("Requested WiFi credentials entry is corrupted");
 		ret = -EPROTO;
 		goto exit;
diff --git a/subsys/net/lib/zperf/CMakeLists.txt b/subsys/net/lib/zperf/CMakeLists.txt
index 77ae40b5e26..f265c0389e1 100644
--- a/subsys/net/lib/zperf/CMakeLists.txt
+++ b/subsys/net/lib/zperf/CMakeLists.txt
@@ -2,14 +2,15 @@
 
 zephyr_library_named(zperf)
 
-zephyr_library_sources(
-  zperf_common.c
-  zperf_session.c
-  zperf_udp_receiver.c
-  zperf_udp_uploader.c
-  zperf_tcp_receiver.c
-  zperf_tcp_uploader.c
-)
+zephyr_library_sources(zperf_common.c)
+zephyr_library_sources_ifdef(CONFIG_NET_UDP zperf_udp_uploader.c)
+zephyr_library_sources_ifdef(CONFIG_NET_TCP zperf_tcp_uploader.c)
+
+if(CONFIG_NET_ZPERF_SERVER)
+  zephyr_library_sources(zperf_session.c)
+  zephyr_library_sources_ifdef(CONFIG_NET_UDP zperf_udp_receiver.c)
+  zephyr_library_sources_ifdef(CONFIG_NET_TCP zperf_tcp_receiver.c)
+endif()
 
 zephyr_library_sources_ifdef(CONFIG_NET_SHELL
   zperf_shell.c
diff --git a/subsys/net/lib/zperf/Kconfig b/subsys/net/lib/zperf/Kconfig
index 44ef4815c3c..510509f6316 100644
--- a/subsys/net/lib/zperf/Kconfig
+++ b/subsys/net/lib/zperf/Kconfig
@@ -3,16 +3,36 @@
 # SPDX-License-Identifier: Apache-2.0
 
 menuconfig NET_ZPERF
-	bool "zperf shell utility"
+	bool "zperf library"
 	select NET_CONTEXT_RCVTIMEO if NET_NATIVE_UDP
-	select NET_SOCKETS_SERVICE
 	select NET_SOCKETS
 	help
-	  This option enables zperf shell utility, which allows to generate
-	  network traffic and evaluate network bandwidth.
+	  This option enables zperf library, which allows to generate
+	  network traffic and evaluate network bandwidth in conjunction
+	  with other devices running zperf or a desktop running the
+	  iperf2 utility.
 
 if NET_ZPERF
 
+config NET_ZPERF_LEGACY_HEADER_COMPAT
+	bool "Legacy iperf UDP header format"
+	help
+	  iperf 2.0.10 (2017) updated the UDP header format in a
+	  backwards incompatible manner that cannot be automatically
+	  detected. This option reverts the header format for use with
+	  iperf version 2.0.9 and earlier.
+
+config ZPERF_SESSION_PER_THREAD
+	bool "Run each session in a separate thread"
+	select EVENTS
+	help
+	  Each session is started in its own thread. This means
+	  that the system will use more memory because multiple
+	  stack frames are needed, so this is not enabled by default.
+	  User is also able to set each thread priority separately and
+	  the ZPERF_WORK_Q_THREAD_PRIORITY is a default value if thread
+	  priority is not set when starting the session.
+
 config ZPERF_WORK_Q_THREAD_PRIORITY
 	int "zperf work queue thread priority"
 	default NUM_PREEMPT_PRIORITIES
@@ -37,8 +57,15 @@ config NET_ZPERF_MAX_PACKET_SIZE
 	help
 	  Upper size limit for packets sent by zperf.
 
+config NET_ZPERF_SERVER
+	bool "zperf server support"
+	select NET_SOCKETS_SERVICE
+	help
+	  Support running a zperf server for testing downloads from the application
+
 config NET_ZPERF_MAX_SESSIONS
 	int "Maximum number of zperf sessions"
+	depends on NET_ZPERF_SERVER
 	default 4
 	help
 	  Upper size limit for connections handled by zperf.
diff --git a/subsys/net/lib/zperf/zperf_common.c b/subsys/net/lib/zperf/zperf_common.c
index 474ecde024d..f42c5b08996 100644
--- a/subsys/net/lib/zperf/zperf_common.c
+++ b/subsys/net/lib/zperf/zperf_common.c
@@ -41,13 +41,71 @@ struct sockaddr_in *zperf_get_sin(void)
 	return &in4_addr_my;
 }
 
-#define ZPERF_WORK_Q_THREAD_PRIORITY                                                               \
-	CLAMP(CONFIG_ZPERF_WORK_Q_THREAD_PRIORITY, K_HIGHEST_APPLICATION_THREAD_PRIO,              \
+#define ZPERF_WORK_Q_THREAD_PRIORITY					\
+	CLAMP(CONFIG_ZPERF_WORK_Q_THREAD_PRIORITY,			\
+	      K_HIGHEST_APPLICATION_THREAD_PRIO,			\
 	      K_LOWEST_APPLICATION_THREAD_PRIO)
-K_THREAD_STACK_DEFINE(zperf_work_q_stack, CONFIG_ZPERF_WORK_Q_STACK_SIZE);
 
+#if defined(CONFIG_ZPERF_SESSION_PER_THREAD)
+static K_EVENT_DEFINE(start_event);
+
+#define CREATE_WORK_Q(i, _)					       \
+	static struct k_work_q zperf_work_q_##i;		       \
+	static K_KERNEL_STACK_DEFINE(zperf_work_q_stack_##i,	       \
+				     CONFIG_ZPERF_WORK_Q_STACK_SIZE)
+
+/* Both UDP and TCP can have separate sessions so multiply by 2 */
+#if defined(CONFIG_NET_UDP) && defined(CONFIG_NET_TCP)
+#define MAX_SESSION_COUNT UTIL_X2(CONFIG_NET_ZPERF_MAX_SESSIONS)
+#define SESSION_INDEX CONFIG_NET_ZPERF_MAX_SESSIONS
+#else
+#define MAX_SESSION_COUNT CONFIG_NET_ZPERF_MAX_SESSIONS
+#define SESSION_INDEX 0
+#endif
+
+LISTIFY(MAX_SESSION_COUNT, CREATE_WORK_Q, (;), _);
+
+#define SET_WORK_Q(i, _)			 \
+	[i] = {					 \
+		.queue = &zperf_work_q_##i,	 \
+		.stack = zperf_work_q_stack_##i, \
+		.stack_size = K_THREAD_STACK_SIZEOF(zperf_work_q_stack_##i), \
+	}
+
+static struct zperf_work zperf_work_q[] = {
+	LISTIFY(MAX_SESSION_COUNT, SET_WORK_Q, (,), _)
+};
+
+struct zperf_work *get_queue(enum session_proto proto, int session_id)
+{
+	if (session_id < 0 || session_id >= CONFIG_NET_ZPERF_MAX_SESSIONS) {
+		return NULL;
+	}
+
+	if (proto < 0 || proto >= SESSION_PROTO_END) {
+		return NULL;
+	}
+
+	NET_DBG("%s using queue %d for session %d\n",
+		proto == SESSION_UDP ? "UDP" : "TCP",
+		proto * SESSION_INDEX + session_id,
+		session_id);
+
+
+	return &zperf_work_q[proto * SESSION_INDEX + session_id];
+}
+
+void start_jobs(void)
+{
+	k_event_set(&start_event, START_EVENT);
+}
+#else /* CONFIG_ZPERF_SESSION_PER_THREAD */
+
+K_THREAD_STACK_DEFINE(zperf_work_q_stack, CONFIG_ZPERF_WORK_Q_STACK_SIZE);
 static struct k_work_q zperf_work_q;
 
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
+
 int zperf_get_ipv6_addr(char *host, char *prefix_str, struct in6_addr *addr)
 {
 	struct net_if_ipv6_prefix *prefix;
@@ -220,24 +278,66 @@ uint32_t zperf_packet_duration(uint32_t packet_size, uint32_t rate_in_kbps)
 			  (rate_in_kbps * 1024U));
 }
 
-void zperf_async_work_submit(struct k_work *work)
+void zperf_async_work_submit(enum session_proto proto, int session_id, struct k_work *work)
 {
+#if defined(CONFIG_ZPERF_SESSION_PER_THREAD)
+	k_work_submit_to_queue(zperf_work_q[proto * SESSION_INDEX + session_id].queue, work);
+#else
+	ARG_UNUSED(proto);
+	ARG_UNUSED(session_id);
+
 	k_work_submit_to_queue(&zperf_work_q, work);
+#endif
 }
 
 static int zperf_init(void)
 {
+#if defined(CONFIG_ZPERF_SESSION_PER_THREAD)
+
+	ARRAY_FOR_EACH(zperf_work_q, i) {
+		struct k_work_queue_config cfg = {
+			.no_yield = false,
+		};
+
+		zperf_work_q[i].start_event = &start_event;
+
+#define MAX_NAME_LEN sizeof("zperf_work_q[xxx]")
+		char name[MAX_NAME_LEN];
+
+		snprintk(name, sizeof(name), "zperf_work_q[%d]", i);
+		cfg.name = name;
+
+		k_work_queue_init(zperf_work_q[i].queue);
+
+		k_work_queue_start(zperf_work_q[i].queue,
+				   zperf_work_q[i].stack,
+				   zperf_work_q[i].stack_size,
+				   ZPERF_WORK_Q_THREAD_PRIORITY,
+				   &cfg);
+	}
+
+#else /* CONFIG_ZPERF_SESSION_PER_THREAD */
 
 	k_work_queue_init(&zperf_work_q);
 	k_work_queue_start(&zperf_work_q, zperf_work_q_stack,
-			   K_THREAD_STACK_SIZEOF(zperf_work_q_stack), ZPERF_WORK_Q_THREAD_PRIORITY,
+			   K_THREAD_STACK_SIZEOF(zperf_work_q_stack),
+			   ZPERF_WORK_Q_THREAD_PRIORITY,
 			   NULL);
 	k_thread_name_set(&zperf_work_q.thread, "zperf_work_q");
 
-	zperf_udp_uploader_init();
-	zperf_tcp_uploader_init();
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
 
-	zperf_session_init();
+	if (IS_ENABLED(CONFIG_NET_UDP)) {
+		zperf_udp_uploader_init();
+	}
+	if (IS_ENABLED(CONFIG_NET_TCP)) {
+		zperf_tcp_uploader_init();
+	}
+
+	if (IS_ENABLED(CONFIG_NET_ZPERF_SERVER) ||
+	    IS_ENABLED(CONFIG_ZPERF_SESSION_PER_THREAD)) {
+		zperf_session_init();
+	}
 
 	if (IS_ENABLED(CONFIG_NET_SHELL)) {
 		zperf_shell_init();
diff --git a/subsys/net/lib/zperf/zperf_internal.h b/subsys/net/lib/zperf/zperf_internal.h
index a798edd8537..1f4abb2000d 100644
--- a/subsys/net/lib/zperf/zperf_internal.h
+++ b/subsys/net/lib/zperf/zperf_internal.h
@@ -53,14 +53,28 @@
 
 #define ZPERF_VERSION "1.1"
 
+enum session_proto {
+	SESSION_UDP = 0,
+	SESSION_TCP = 1,
+	SESSION_PROTO_END
+};
+
 struct zperf_udp_datagram {
-	int32_t id;
+	uint32_t id;
 	uint32_t tv_sec;
 	uint32_t tv_usec;
+#ifndef CONFIG_NET_ZPERF_LEGACY_HEADER_COMPAT
+	uint32_t id2;
+#endif
 } __packed;
 
 BUILD_ASSERT(sizeof(struct zperf_udp_datagram) <= PACKET_SIZE_MAX, "Invalid PACKET_SIZE_MAX");
 
+#define ZPERF_FLAGS_VERSION1      0x80000000
+#define ZPERF_FLAGS_EXTEND        0x40000000
+#define ZPERF_FLAGS_UDPTESTS      0x20000000
+#define ZPERF_FLAGS_SEQNO64B      0x08000000
+
 struct zperf_client_hdr_v1 {
 	int32_t flags;
 	int32_t num_of_threads;
@@ -103,12 +117,23 @@ struct sockaddr_in *zperf_get_sin(void);
 
 extern void connect_ap(char *ssid);
 
+struct zperf_work {
+	struct k_work_q *queue;
+	struct z_thread_stack_element *stack;
+	struct k_event *start_event;
+	size_t stack_size;
+};
+
+#define START_EVENT 0x0001
+extern void start_jobs(void);
+extern struct zperf_work *get_queue(enum session_proto proto, int session_id);
+
 int zperf_prepare_upload_sock(const struct sockaddr *peer_addr, uint8_t tos,
 			      int priority, int tcp_nodelay, int proto);
 
 uint32_t zperf_packet_duration(uint32_t packet_size, uint32_t rate_in_kbps);
 
-void zperf_async_work_submit(struct k_work *work);
+void zperf_async_work_submit(enum session_proto proto, int session_id, struct k_work *work);
 void zperf_udp_uploader_init(void);
 void zperf_tcp_uploader_init(void);
 
diff --git a/subsys/net/lib/zperf/zperf_session.c b/subsys/net/lib/zperf/zperf_session.c
index 6fff4abf9cc..d824057931d 100644
--- a/subsys/net/lib/zperf/zperf_session.c
+++ b/subsys/net/lib/zperf/zperf_session.c
@@ -19,6 +19,70 @@ LOG_MODULE_DECLARE(net_zperf, CONFIG_NET_ZPERF_LOG_LEVEL);
 
 static struct session sessions[SESSION_PROTO_END][SESSION_MAX];
 
+struct session *get_free_session(const struct sockaddr *addr,
+				 enum session_proto proto)
+{
+	struct session *ptr;
+	uint64_t oldest = 0ULL;
+	int oldest_completed_index = -1, oldest_free_index = -1;
+	int i = 0;
+
+	const struct sockaddr_in *addr4 = (const struct sockaddr_in *)addr;
+	const struct sockaddr_in6 *addr6 = (const struct sockaddr_in6 *)addr;
+
+	/* Check whether we already have an active session */
+	while (i < SESSION_MAX) {
+		ptr = &sessions[proto][i];
+
+		if (ptr->state == STATE_NULL ||
+		    ptr->state == STATE_COMPLETED) {
+
+			if (oldest == 0ULL || ptr->last_time < oldest) {
+				oldest = ptr->last_time;
+
+				if (ptr->state == STATE_COMPLETED) {
+					if (oldest_completed_index < 0) {
+						oldest_completed_index = i;
+					}
+				} else {
+					/* Free session */
+					if (oldest_free_index < 0) {
+						oldest_free_index = i;
+					}
+				}
+			}
+		}
+
+		i++;
+	}
+
+	ptr = NULL;
+
+	if (oldest_free_index >= 0) {
+		ptr = &sessions[proto][oldest_free_index];
+	} else if (oldest_completed_index >= 0) {
+		ptr = &sessions[proto][oldest_completed_index];
+	}
+
+	if (ptr != NULL) {
+		if (IS_ENABLED(CONFIG_NET_IPV4) &&
+		    addr->sa_family == AF_INET) {
+			ptr->port = addr4->sin_port;
+			ptr->ip.family = AF_INET;
+			net_ipaddr_copy(&ptr->ip.in_addr, &addr4->sin_addr);
+		} else if (IS_ENABLED(CONFIG_NET_IPV6) &&
+			   addr->sa_family == AF_INET6) {
+			ptr->port = addr6->sin6_port;
+			ptr->ip.family = AF_INET6;
+			net_ipaddr_copy(&ptr->ip.in6_addr, &addr6->sin6_addr);
+		}
+
+		ptr->state = STATE_STARTING;
+	}
+
+	return ptr;
+}
+
 /* Get session from a given packet */
 struct session *get_session(const struct sockaddr *addr,
 			    enum session_proto proto)
@@ -102,6 +166,14 @@ void zperf_reset_session_stats(struct session *session)
 	session->last_transit_time = 0;
 }
 
+void zperf_session_foreach(enum session_proto proto, session_cb_t cb,
+			   void *user_data)
+{
+	ARRAY_FOR_EACH(sessions[proto], i) {
+		cb(&sessions[proto][i], proto, user_data);
+	}
+}
+
 void zperf_session_reset(enum session_proto proto)
 {
 	int i, j;
@@ -114,6 +186,7 @@ void zperf_session_reset(enum session_proto proto)
 
 	for (j = 0; j < SESSION_MAX; j++) {
 		sessions[i][j].state = STATE_NULL;
+		sessions[i][j].id = j;
 		zperf_reset_session_stats(&(sessions[i][j]));
 	}
 }
diff --git a/subsys/net/lib/zperf/zperf_session.h b/subsys/net/lib/zperf/zperf_session.h
index f01bc66b71a..c6f9e417739 100644
--- a/subsys/net/lib/zperf/zperf_session.h
+++ b/subsys/net/lib/zperf/zperf_session.h
@@ -21,23 +21,21 @@
 /* Type definition */
 enum state {
 	STATE_NULL, /* Session has not yet started */
+	STATE_STARTING, /* Session is starting */
 	STATE_ONGOING, /* 1st packet has been received, last packet not yet */
 	STATE_LAST_PACKET_RECEIVED, /* Last packet has been received */
 	STATE_COMPLETED /* Session completed, stats pkt can be sent if needed */
 };
 
-enum session_proto {
-	SESSION_UDP = 0,
-	SESSION_TCP = 1,
-	SESSION_PROTO_END
-};
-
 struct session {
+	int id;
+
 	/* Tuple for UDP */
 	uint16_t port;
 	struct net_addr ip;
 
 	enum state state;
+	enum session_proto proto;
 
 	/* Stat data */
 	uint32_t counter;
@@ -52,13 +50,28 @@ struct session {
 
 	/* Stats packet*/
 	struct zperf_server_hdr stat;
+
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+	struct zperf_results result;
+	struct zperf_async_upload_context async_upload_ctx;
+	struct zperf_work *zperf;
+	bool in_progress; /* is this session finished or not */
+	bool wait_for_start; /* wait until the user starts the sessions */
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
 };
 
+typedef void (*session_cb_t)(struct session *ses, enum session_proto proto,
+			     void *user_data);
+
 struct session *get_session(const struct sockaddr *addr,
 			    enum session_proto proto);
+struct session *get_free_session(const struct sockaddr *addr,
+				 enum session_proto proto);
 void zperf_session_init(void);
 void zperf_reset_session_stats(struct session *session);
 /* Reset all sessions for a given protocol. */
 void zperf_session_reset(enum session_proto proto);
+void zperf_session_foreach(enum session_proto proto, session_cb_t cb,
+			   void *user_data);
 
 #endif /* __ZPERF_SESSION_H */
diff --git a/subsys/net/lib/zperf/zperf_shell.c b/subsys/net/lib/zperf/zperf_shell.c
index f3f2257f7cc..d92a7aaa9d1 100644
--- a/subsys/net/lib/zperf/zperf_shell.c
+++ b/subsys/net/lib/zperf/zperf_shell.c
@@ -19,6 +19,7 @@ LOG_MODULE_DECLARE(net_zperf, CONFIG_NET_ZPERF_LOG_LEVEL);
 #include <zephyr/net/net_core.h>
 #include <zephyr/net/socket.h>
 #include <zephyr/net/zperf.h>
+#include <zephyr/sys/util_macro.h>
 
 #include "zperf_internal.h"
 #include "zperf_session.h"
@@ -200,6 +201,8 @@ static int parse_ipv4_addr(const struct shell *sh, char *host, char *port,
 	return 0;
 }
 
+#ifdef CONFIG_NET_ZPERF_SERVER
+
 static int zperf_bind_host(const struct shell *sh,
 			   size_t argc, char *argv[],
 			   struct zperf_download_params *param)
@@ -233,6 +236,8 @@ static int zperf_bind_host(const struct shell *sh,
 	return 0;
 }
 
+#endif
+
 static int cmd_setip(const struct shell *sh, size_t argc, char *argv[])
 {
 	int start = 0;
@@ -311,6 +316,8 @@ static int cmd_setip(const struct shell *sh, size_t argc, char *argv[])
 	return 0;
 }
 
+#ifdef CONFIG_NET_ZPERF_SERVER
+
 static void udp_session_cb(enum zperf_status status,
 			   struct zperf_results *result,
 			   void *user_data)
@@ -475,8 +482,11 @@ static int cmd_udp_download(const struct shell *sh, size_t argc,
 	}
 }
 
+#endif
+
 static void shell_udp_upload_print_stats(const struct shell *sh,
-					 struct zperf_results *results)
+					 struct zperf_results *results,
+					 bool is_async)
 {
 	if (IS_ENABLED(CONFIG_NET_UDP)) {
 		uint64_t rate_in_kbps, client_rate_in_kbps;
@@ -536,11 +546,35 @@ static void shell_udp_upload_print_stats(const struct shell *sh,
 		shell_fprintf(sh, SHELL_NORMAL, "\t(");
 		print_number(sh, client_rate_in_kbps, KBPS, KBPS_UNIT);
 		shell_fprintf(sh, SHELL_NORMAL, ")\n");
+
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+		if (is_async) {
+			struct session *ses = CONTAINER_OF(results,
+							   struct session,
+							   result);
+
+#ifdef CONFIG_NET_CONTEXT_PRIORITY
+			shell_fprintf(sh, SHELL_NORMAL,
+				      "Packet priority:\t%d\n",
+				      ses->async_upload_ctx.param.options.priority);
+#endif /* CONFIG_NET_CONTEXT_PRIORITY */
+
+			shell_fprintf(sh, SHELL_NORMAL,
+				      "Thread priority:\t%d\n",
+				      ses->async_upload_ctx.param.options.thread_priority);
+			shell_fprintf(sh, SHELL_NORMAL,
+				      "Protocol:\t\t%s\n",
+				      ses->proto == SESSION_UDP ? "UDP" : "TCP");
+			shell_fprintf(sh, SHELL_NORMAL,
+				      "Session id:\t\t%d\n", ses->id);
+		}
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
 	}
 }
 
 static void shell_tcp_upload_print_stats(const struct shell *sh,
-					 struct zperf_results *results)
+					 struct zperf_results *results,
+					 bool is_async)
 {
 	if (IS_ENABLED(CONFIG_NET_TCP)) {
 		uint64_t client_rate_in_kbps;
@@ -557,18 +591,41 @@ static void shell_tcp_upload_print_stats(const struct shell *sh,
 			client_rate_in_kbps = 0U;
 		}
 
-		shell_fprintf(sh, SHELL_NORMAL, "Duration:\t");
+		shell_fprintf(sh, SHELL_NORMAL, "Duration:\t\t");
 		print_number_64(sh, results->client_time_in_us,
 			     TIME_US, TIME_US_UNIT);
 		shell_fprintf(sh, SHELL_NORMAL, "\n");
-		shell_fprintf(sh, SHELL_NORMAL, "Num packets:\t%u\n",
+		shell_fprintf(sh, SHELL_NORMAL, "Num packets:\t\t%u\n",
 			      results->nb_packets_sent);
 		shell_fprintf(sh, SHELL_NORMAL,
-			      "Num errors:\t%u (retry or fail)\n",
+			      "Num errors:\t\t%u (retry or fail)\n",
 			      results->nb_packets_errors);
-		shell_fprintf(sh, SHELL_NORMAL, "Rate:\t\t");
+		shell_fprintf(sh, SHELL_NORMAL, "Rate:\t\t\t");
 		print_number(sh, client_rate_in_kbps, KBPS, KBPS_UNIT);
 		shell_fprintf(sh, SHELL_NORMAL, "\n");
+
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+		if (is_async) {
+			struct session *ses = CONTAINER_OF(results,
+							   struct session,
+							   result);
+
+#ifdef CONFIG_NET_CONTEXT_PRIORITY
+			shell_fprintf(sh, SHELL_NORMAL,
+				      "Packet priority:\t%d\n",
+				      ses->async_upload_ctx.param.options.priority);
+#endif /* CONFIG_NET_CONTEXT_PRIORITY */
+
+			shell_fprintf(sh, SHELL_NORMAL,
+				      "Thread priority:\t%d\n",
+				      ses->async_upload_ctx.param.options.thread_priority);
+			shell_fprintf(sh, SHELL_NORMAL,
+				      "Protocol:\t\t%s\n",
+				      ses->proto == SESSION_UDP ? "UDP" : "TCP");
+			shell_fprintf(sh, SHELL_NORMAL,
+				      "Session id:\t\t%d\n", ses->id);
+		}
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
 	}
 }
 
@@ -609,17 +666,32 @@ static void udp_upload_cb(enum zperf_status status,
 {
 	const struct shell *sh = user_data;
 
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+	struct session *ses = CONTAINER_OF(result, struct session, result);
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
+
 	switch (status) {
 	case ZPERF_SESSION_STARTED:
 		break;
 
 	case ZPERF_SESSION_FINISHED: {
-		shell_udp_upload_print_stats(sh, result);
+		shell_udp_upload_print_stats(sh, result, true);
+
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+		ses->in_progress = false;
+		ses->state = STATE_COMPLETED;
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
+
 		break;
 	}
 
 	case ZPERF_SESSION_ERROR:
 		shell_fprintf(sh, SHELL_ERROR, "UDP upload failed\n");
+
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+		ses->in_progress = false;
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
+
 		break;
 
 	default:
@@ -633,6 +705,10 @@ static void tcp_upload_cb(enum zperf_status status,
 {
 	const struct shell *sh = user_data;
 
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+	struct session *ses = CONTAINER_OF(result, struct session, result);
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
+
 	switch (status) {
 	case ZPERF_SESSION_STARTED:
 		break;
@@ -642,12 +718,23 @@ static void tcp_upload_cb(enum zperf_status status,
 		break;
 
 	case ZPERF_SESSION_FINISHED: {
-		shell_tcp_upload_print_stats(sh, result);
+		shell_tcp_upload_print_stats(sh, result, true);
+
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+		ses->in_progress = false;
+		ses->state = STATE_COMPLETED;
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
+
 		break;
 	}
 
 	case ZPERF_SESSION_ERROR:
 		shell_fprintf(sh, SHELL_ERROR, "TCP upload failed\n");
+
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+		ses->in_progress = false;
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
+
 		break;
 	}
 }
@@ -719,7 +806,14 @@ static int execute_upload(const struct shell *sh,
 		      param->packet_size);
 	shell_fprintf(sh, SHELL_NORMAL, "Rate:\t\t%u kbps\n",
 		      param->rate_kbps);
-	shell_fprintf(sh, SHELL_NORMAL, "Starting...\n");
+
+	if (IS_ENABLED(CONFIG_ZPERF_SESSION_PER_THREAD) &&
+	    COND_CODE_1(CONFIG_ZPERF_SESSION_PER_THREAD,
+			(param->options.wait_for_start), (0))) {
+		shell_fprintf(sh, SHELL_NORMAL, "Waiting \"zperf jobs start\" command.\n");
+	} else {
+		shell_fprintf(sh, SHELL_NORMAL, "Starting...\n");
+	}
 
 	if (IS_ENABLED(CONFIG_NET_IPV6) && param->peer_addr.sa_family == AF_INET6) {
 		struct sockaddr_in6 *ipv6 =
@@ -763,7 +857,7 @@ static int execute_upload(const struct shell *sh,
 				return ret;
 			}
 
-			shell_udp_upload_print_stats(sh, &results);
+			shell_udp_upload_print_stats(sh, &results, false);
 		}
 	} else {
 		if (is_udp && !IS_ENABLED(CONFIG_NET_UDP)) {
@@ -789,7 +883,7 @@ static int execute_upload(const struct shell *sh,
 				return ret;
 			}
 
-			shell_tcp_upload_print_stats(sh, &results);
+			shell_tcp_upload_print_stats(sh, &results, false);
 		}
 	} else {
 		if (!is_udp && !IS_ENABLED(CONFIG_NET_TCP)) {
@@ -830,6 +924,25 @@ static int parse_arg(size_t *i, size_t argc, char *argv[])
 	return res;
 }
 
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+static bool check_priority(const struct shell *sh, int priority)
+{
+	if (!((priority >= -CONFIG_NUM_COOP_PRIORITIES && priority <= -1) ||
+	      (priority >= 0 && priority <= (CONFIG_NUM_PREEMPT_PRIORITIES - 1)))) {
+		shell_fprintf(sh, SHELL_WARNING,
+			      "Invalid priority: %d\n"
+			      "Valid values are [%d, %d] for co-operative "
+			      "and [%d, %d] for pre-emptive threads\n",
+			      priority,
+			      -CONFIG_NUM_COOP_PRIORITIES, -1,
+			      0, CONFIG_NUM_PREEMPT_PRIORITIES - 1);
+		return false;
+	}
+
+	return true;
+}
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
+
 static int shell_cmd_upload(const struct shell *sh, size_t argc,
 			     char *argv[], enum net_ip_protocol proto)
 {
@@ -883,6 +996,24 @@ static int shell_cmd_upload(const struct shell *sh, size_t argc,
 			opt_cnt += 1;
 			break;
 
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+		case 't':
+			param.options.thread_priority = parse_arg(&i, argc, argv);
+			if (!check_priority(sh, param.options.thread_priority)) {
+				shell_fprintf(sh, SHELL_WARNING,
+					      "Parse error: %s\n", argv[i]);
+				return -ENOEXEC;
+			}
+			opt_cnt += 2;
+			async = true;
+			break;
+
+		case 'w':
+			param.options.wait_for_start = true;
+			opt_cnt += 1;
+			break;
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
+
 #ifdef CONFIG_NET_CONTEXT_PRIORITY
 		case 'p':
 			param.options.priority = parse_arg(&i, argc, argv);
@@ -1117,6 +1248,24 @@ static int shell_cmd_upload2(const struct shell *sh, size_t argc,
 			opt_cnt += 1;
 			break;
 
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+		case 't':
+			param.options.thread_priority = parse_arg(&i, argc, argv);
+			if (!check_priority(sh, param.options.thread_priority)) {
+				shell_fprintf(sh, SHELL_WARNING,
+					      "Parse error: %s\n", argv[i]);
+				return -ENOEXEC;
+			}
+			opt_cnt += 2;
+			async = true;
+			break;
+
+		case 'w':
+			param.options.wait_for_start = true;
+			opt_cnt += 1;
+			break;
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
+
 #ifdef CONFIG_NET_CONTEXT_PRIORITY
 		case 'p':
 			param.options.priority = parse_arg(&i, argc, argv);
@@ -1286,11 +1435,13 @@ static int cmd_udp(const struct shell *sh, size_t argc, char *argv[])
 static int cmd_connectap(const struct shell *sh, size_t argc, char *argv[])
 {
 	shell_fprintf(sh, SHELL_INFO,
-		      "Zephyr has not been built with Wi-Fi support.\n");
+		      "Zephyr has not been built with %s support.\n", "Wi-Fi");
 
 	return 0;
 }
 
+#ifdef CONFIG_NET_ZPERF_SERVER
+
 static void tcp_session_cb(enum zperf_status status,
 			   struct zperf_results *result,
 			   void *user_data)
@@ -1395,6 +1546,8 @@ static int cmd_tcp_download(const struct shell *sh, size_t argc,
 	}
 }
 
+#endif
+
 static int cmd_version(const struct shell *sh, size_t argc, char *argv[])
 {
 	shell_fprintf(sh, SHELL_NORMAL, "Version: %s\nConfig: %s\n",
@@ -1403,6 +1556,267 @@ static int cmd_version(const struct shell *sh, size_t argc, char *argv[])
 	return 0;
 }
 
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+struct zperf_shell_user_data {
+	const struct shell *sh;
+	void *user_data;
+	int in_progress_count;
+	int finalized_count;
+	bool active;
+};
+
+static void session_cb(struct session *ses,
+		       enum session_proto proto,
+		       void *user_data)
+{
+	struct zperf_shell_user_data *data = user_data;
+	const struct shell *sh = data->sh;
+	bool active = data->active;
+
+	if (ses->state == STATE_NULL) {
+		return;
+	}
+
+	if (active) {
+		if (ses->in_progress) {
+			uint32_t remaining;
+
+			if (ses->state != STATE_STARTING && ses->state != STATE_ONGOING) {
+				return;
+			}
+
+			if (ses->proto != proto) {
+				return;
+			}
+
+			if (data->in_progress_count == 0) {
+				shell_fprintf(sh, SHELL_NORMAL,
+					      "           Thread    Remaining\n"
+					      "Id  Proto  Priority  time (sec)\n");
+			}
+
+			remaining = (uint32_t)
+				(((uint64_t)ses->async_upload_ctx.param.duration_ms -
+				  (k_uptime_get() -
+				   k_ticks_to_ms_ceil64(ses->start_time))) / MSEC_PER_SEC);
+
+			shell_fprintf(sh, SHELL_NORMAL,
+				      "[%d] %s    %d\t\t%d\n",
+				      ses->id, ses->proto == SESSION_UDP ? "UDP" : "TCP",
+				      ses->async_upload_ctx.param.options.thread_priority,
+				      remaining);
+
+			data->in_progress_count++;
+		}
+
+		return;
+	}
+
+	if (!ses->in_progress) {
+		if (ses->state != STATE_COMPLETED) {
+			return;
+		}
+
+		if (ses->proto != proto) {
+			return;
+		}
+
+		if (data->finalized_count == 0) {
+			shell_fprintf(sh, SHELL_NORMAL,
+				"            Thread\n"
+				"Id  Proto  Priority  \tDuration\tRate\n");
+		}
+
+		shell_fprintf(sh, SHELL_NORMAL,
+			      "[%d] %s    %d\t\t",
+			      ses->id, ses->proto == SESSION_UDP ? "UDP" : "TCP",
+			      ses->async_upload_ctx.param.options.thread_priority);
+		print_number_64(sh,
+				(uint64_t)ses->async_upload_ctx.param.duration_ms * USEC_PER_MSEC,
+				TIME_US, TIME_US_UNIT);
+		shell_fprintf(sh, SHELL_NORMAL, "\t\t%u kbps\n",
+			      ses->async_upload_ctx.param.rate_kbps);
+
+		data->finalized_count++;
+	}
+}
+
+static void session_all_cb(struct session *ses,
+			   enum session_proto proto,
+			   void *user_data)
+{
+	struct zperf_shell_user_data *data = user_data;
+	const struct shell *sh = data->sh;
+
+	if (ses->state == STATE_NULL) {
+		return;
+	}
+
+	if (!ses->in_progress) {
+		if (ses->state != STATE_COMPLETED) {
+			return;
+		}
+
+		if (ses->proto != proto) {
+			return;
+		}
+
+		if (proto == SESSION_UDP) {
+			shell_udp_upload_print_stats(sh, &ses->result, true);
+		} else {
+			shell_tcp_upload_print_stats(sh, &ses->result, true);
+		}
+
+		data->finalized_count++;
+	}
+}
+
+static void session_clear_cb(struct session *ses,
+			     enum session_proto proto,
+			     void *user_data)
+{
+	struct zperf_shell_user_data *data = user_data;
+
+	if (ses->state == STATE_NULL) {
+		return;
+	}
+
+	if (!ses->in_progress) {
+		if (ses->state == STATE_COMPLETED) {
+			ses->state = STATE_NULL;
+			data->finalized_count++;
+		}
+	} else {
+		if (ses->state == STATE_STARTING || ses->state == STATE_ONGOING) {
+			data->in_progress_count++;
+		}
+	}
+}
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
+
+static int cmd_jobs(const struct shell *sh, size_t argc, char *argv[])
+{
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+	struct zperf_shell_user_data user_data;
+
+	user_data.sh = sh;
+	user_data.in_progress_count = 0;
+	user_data.finalized_count = 0;
+	user_data.active = true;
+
+	zperf_session_foreach(SESSION_UDP, session_cb, &user_data);
+	zperf_session_foreach(SESSION_TCP, session_cb, &user_data);
+
+	if (user_data.in_progress_count == 0) {
+		shell_fprintf(sh, SHELL_NORMAL,
+			      "No active upload sessions\n");
+	}
+
+	shell_fprintf(sh, SHELL_NORMAL, "\n");
+
+	user_data.active = false;
+
+	zperf_session_foreach(SESSION_UDP, session_cb, &user_data);
+	zperf_session_foreach(SESSION_TCP, session_cb, &user_data);
+
+	if (user_data.finalized_count == 0 && user_data.in_progress_count > 0) {
+		shell_fprintf(sh, SHELL_NORMAL,
+			      "Active sessions have not yet finished\n");
+	} else if (user_data.finalized_count == 0) {
+		shell_fprintf(sh, SHELL_NORMAL,
+			      "No finished sessions found\n");
+	} else {
+		shell_fprintf(sh, SHELL_NORMAL,
+			      "Total %d sessions done\n",
+			      user_data.finalized_count);
+	}
+#else
+	shell_fprintf(sh, SHELL_INFO,
+		      "Zephyr has not been built with %s support.\n",
+		      "CONFIG_ZPERF_SESSION_PER_THREAD");
+#endif
+	return 0;
+}
+
+static int cmd_jobs_all(const struct shell *sh, size_t argc, char *argv[])
+{
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+	struct zperf_shell_user_data user_data;
+
+	user_data.sh = sh;
+	user_data.in_progress_count = 0;
+	user_data.finalized_count = 0;
+	user_data.active = false;
+
+	zperf_session_foreach(SESSION_UDP, session_all_cb, &user_data);
+	zperf_session_foreach(SESSION_TCP, session_all_cb, &user_data);
+
+	if (user_data.finalized_count == 0 && user_data.in_progress_count > 0) {
+		shell_fprintf(sh, SHELL_NORMAL,
+			      "Active sessions have not yet finished\n");
+	} else if (user_data.finalized_count == 0) {
+		shell_fprintf(sh, SHELL_NORMAL,
+			      "No finished sessions found\n");
+	} else {
+		shell_fprintf(sh, SHELL_NORMAL,
+			      "Total %d sessions done\n",
+			      user_data.finalized_count);
+	}
+#else
+	shell_fprintf(sh, SHELL_INFO,
+		      "Zephyr has not been built with %s support.\n",
+		      "CONFIG_ZPERF_SESSION_PER_THREAD");
+#endif
+	return 0;
+}
+
+static int cmd_jobs_clear(const struct shell *sh, size_t argc, char *argv[])
+{
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+	struct zperf_shell_user_data user_data;
+
+	user_data.sh = sh;
+	user_data.in_progress_count = 0;
+	user_data.finalized_count = 0;
+	user_data.active = false;
+
+	zperf_session_foreach(SESSION_UDP, session_clear_cb, &user_data);
+	zperf_session_foreach(SESSION_TCP, session_clear_cb, &user_data);
+
+	if (user_data.finalized_count == 0 && user_data.in_progress_count > 0) {
+		shell_fprintf(sh, SHELL_NORMAL,
+			      "Active sessions have not yet finished, not clearing\n");
+	} else if (user_data.finalized_count == 0) {
+		shell_fprintf(sh, SHELL_NORMAL, "All sessions already cleared\n");
+	} else {
+		shell_fprintf(sh, SHELL_NORMAL,
+			      "Cleared data from %d sessions\n",
+			      user_data.finalized_count);
+	}
+#else
+	shell_fprintf(sh, SHELL_INFO,
+		      "Zephyr has not been built with %s support.\n",
+		      "CONFIG_ZPERF_SESSION_PER_THREAD");
+#endif
+	return 0;
+}
+
+static int cmd_jobs_start(const struct shell *sh, size_t argc, char *argv[])
+{
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+	ARG_UNUSED(argc);
+	ARG_UNUSED(argv);
+	ARG_UNUSED(sh);
+
+	start_jobs();
+#else
+	shell_fprintf(sh, SHELL_INFO,
+		      "Zephyr has not been built with %s support.\n",
+		      "CONFIG_ZPERF_SESSION_PER_THREAD");
+#endif
+	return 0;
+}
+
 void zperf_shell_init(void)
 {
 	int ret;
@@ -1454,11 +1868,15 @@ void zperf_shell_init(void)
 	}
 }
 
+#ifdef CONFIG_NET_ZPERF_SERVER
+
 SHELL_STATIC_SUBCMD_SET_CREATE(zperf_cmd_tcp_download,
 	SHELL_CMD(stop, NULL, "Stop TCP server\n", cmd_tcp_download_stop),
 	SHELL_SUBCMD_SET_END
 );
 
+#endif
+
 SHELL_STATIC_SUBCMD_SET_CREATE(zperf_cmd_tcp,
 	SHELL_CMD(upload, NULL,
 		  "[<options>] <dest ip> <dest port> <duration> <packet size>[K]\n"
@@ -1475,6 +1893,10 @@ SHELL_STATIC_SUBCMD_SET_CREATE(zperf_cmd_tcp,
 		  "-a: Asynchronous call (shell will not block for the upload)\n"
 		  "-i sec: Periodic reporting interval in seconds (async only)\n"
 		  "-n: Disable Nagle's algorithm\n"
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+		  "-t: Specify custom thread priority\n"
+		  "-w: Wait for start signal before starting the tests\n"
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
 #ifdef CONFIG_NET_CONTEXT_PRIORITY
 		  "-p: Specify custom packet priority\n"
 #endif /* CONFIG_NET_CONTEXT_PRIORITY */
@@ -1495,6 +1917,10 @@ SHELL_STATIC_SUBCMD_SET_CREATE(zperf_cmd_tcp,
 		  "-a: Asynchronous call (shell will not block for the upload)\n"
 		  "-i sec: Periodic reporting interval in seconds (async only)\n"
 		  "-n: Disable Nagle's algorithm\n"
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+		  "-t: Specify custom thread priority\n"
+		  "-w: Wait for start signal before starting the tests\n"
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
 #ifdef CONFIG_NET_CONTEXT_PRIORITY
 		  "-p: Specify custom packet priority\n"
 #endif /* CONFIG_NET_CONTEXT_PRIORITY */
@@ -1510,18 +1936,22 @@ SHELL_STATIC_SUBCMD_SET_CREATE(zperf_cmd_tcp,
 #endif
 		  ,
 		  cmd_tcp_upload2),
+#ifdef CONFIG_NET_ZPERF_SERVER
 	SHELL_CMD(download, &zperf_cmd_tcp_download,
 		  "[<port>]:  Server port to listen on/connect to\n"
 		  "[<host>]:  Bind to <host>, an interface address\n"
 		  "Example: tcp download 5001 192.168.0.1\n",
 		  cmd_tcp_download),
+#endif
 	SHELL_SUBCMD_SET_END
 );
 
+#ifdef CONFIG_NET_ZPERF_SERVER
 SHELL_STATIC_SUBCMD_SET_CREATE(zperf_cmd_udp_download,
 	SHELL_CMD(stop, NULL, "Stop UDP server\n", cmd_udp_download_stop),
 	SHELL_SUBCMD_SET_END
 );
+#endif
 
 SHELL_STATIC_SUBCMD_SET_CREATE(zperf_cmd_udp,
 	SHELL_CMD(upload, NULL,
@@ -1540,6 +1970,10 @@ SHELL_STATIC_SUBCMD_SET_CREATE(zperf_cmd_udp,
 		  "Available options:\n"
 		  "-S tos: Specify IPv4/6 type of service\n"
 		  "-a: Asynchronous call (shell will not block for the upload)\n"
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+		  "-t: Specify custom thread priority\n"
+		  "-w: Wait for start signal before starting the tests\n"
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
 #ifdef CONFIG_NET_CONTEXT_PRIORITY
 		  "-p: Specify custom packet priority\n"
 #endif /* CONFIG_NET_CONTEXT_PRIORITY */
@@ -1561,6 +1995,10 @@ SHELL_STATIC_SUBCMD_SET_CREATE(zperf_cmd_udp,
 		  "Available options:\n"
 		  "-S tos: Specify IPv4/6 type of service\n"
 		  "-a: Asynchronous call (shell will not block for the upload)\n"
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+		  "-t: Specify custom thread priority\n"
+		  "-w: Wait for start signal before starting the tests\n"
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
 #ifdef CONFIG_NET_CONTEXT_PRIORITY
 		  "-p: Specify custom packet priority\n"
 #endif /* CONFIG_NET_CONTEXT_PRIORITY */
@@ -1577,6 +2015,7 @@ SHELL_STATIC_SUBCMD_SET_CREATE(zperf_cmd_udp,
 #endif
 		  ,
 		  cmd_udp_upload2),
+#ifdef CONFIG_NET_ZPERF_SERVER
 	SHELL_CMD(download, &zperf_cmd_udp_download,
 		  "[<options>] command options (optional): [-I eth0]\n"
 		  "[<port>]:  Server port to listen on/connect to\n"
@@ -1585,13 +2024,23 @@ SHELL_STATIC_SUBCMD_SET_CREATE(zperf_cmd_udp,
 		  "-I <interface name>: Specify host interface name\n"
 		  "Example: udp download 5001 192.168.0.1\n",
 		  cmd_udp_download),
+#endif
 	SHELL_SUBCMD_SET_END
 );
 
+SHELL_STATIC_SUBCMD_SET_CREATE(zperf_cmd_jobs,
+	SHELL_CMD(all, NULL, "Show all statistics", cmd_jobs_all),
+	SHELL_CMD(clear, NULL, "Clear all statistics", cmd_jobs_clear),
+	SHELL_CMD(start, NULL, "Start waiting jobs", cmd_jobs_start),
+);
+
 SHELL_STATIC_SUBCMD_SET_CREATE(zperf_commands,
 	SHELL_CMD(connectap, NULL,
 		  "Connect to AP",
 		  cmd_connectap),
+	SHELL_CMD(jobs, &zperf_cmd_jobs,
+		  "Show currently active tests",
+		  cmd_jobs),
 	SHELL_CMD(setip, NULL,
 		  "Set IP address\n"
 		  "<my ip> <prefix len>\n"
diff --git a/subsys/net/lib/zperf/zperf_tcp_uploader.c b/subsys/net/lib/zperf/zperf_tcp_uploader.c
index 6f463851c90..b8cf12ad0b7 100644
--- a/subsys/net/lib/zperf/zperf_tcp_uploader.c
+++ b/subsys/net/lib/zperf/zperf_tcp_uploader.c
@@ -15,10 +15,13 @@ LOG_MODULE_DECLARE(net_zperf, CONFIG_NET_ZPERF_LOG_LEVEL);
 #include <zephyr/net/zperf.h>
 
 #include "zperf_internal.h"
+#include "zperf_session.h"
 
 static char sample_packet[PACKET_SIZE_MAX];
 
+#if !defined(CONFIG_ZPERF_SESSION_PER_THREAD)
 static struct zperf_async_upload_context tcp_async_upload_ctx;
+#endif /* !CONFIG_ZPERF_SESSION_PER_THREAD */
 
 static ssize_t sendall(int sock, const void *buf, size_t len)
 {
@@ -105,6 +108,7 @@ static int tcp_upload(int sock,
 				k_ticks_to_us_ceil64(end_time - start_time);
 	results->packet_size = packet_size;
 	results->nb_packets_errors = nb_errors;
+	results->total_len = (uint64_t)nb_packets * packet_size;
 
 	if (alloc_errors > 0) {
 		NET_WARN("There was %u network buffer allocation "
@@ -148,9 +152,36 @@ int zperf_tcp_upload(const struct zperf_upload_params *param,
 
 static void tcp_upload_async_work(struct k_work *work)
 {
-	struct zperf_async_upload_context *upload_ctx =
-		CONTAINER_OF(work, struct zperf_async_upload_context, work);
-	struct zperf_results result = { 0 };
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+	struct session *ses;
+	struct zperf_async_upload_context *upload_ctx;
+	struct zperf_results *result;
+
+	ses = CONTAINER_OF(work, struct session, async_upload_ctx.work);
+	upload_ctx = &ses->async_upload_ctx;
+
+	if (ses->wait_for_start) {
+		NET_INFO("[%d] %s waiting for start", ses->id, "TCP");
+
+		/* Wait for the start event to be set */
+		k_event_wait(ses->zperf->start_event, START_EVENT, true, K_FOREVER);
+
+		NET_INFO("[%d] %s starting", ses->id, "TCP");
+	}
+
+	NET_DBG("[%d] thread %p priority %d name %s", ses->id, k_current_get(),
+		k_thread_priority_get(k_current_get()),
+		k_thread_name_get(k_current_get()));
+
+	result = &ses->result;
+
+	ses->in_progress = true;
+#else
+	struct zperf_async_upload_context *upload_ctx = &tcp_async_upload_ctx;
+	struct zperf_results result_storage = { 0 };
+	struct zperf_results *result = &result_storage;
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
+
 	int ret;
 	struct zperf_upload_params param = upload_ctx->param;
 	int sock;
@@ -197,15 +228,15 @@ static void tcp_upload_async_work(struct k_work *work)
 			upload_ctx->callback(ZPERF_SESSION_PERIODIC_RESULT, &periodic_result,
 					     upload_ctx->user_data);
 
-			result.nb_packets_sent += periodic_result.nb_packets_sent;
-			result.client_time_in_us += periodic_result.client_time_in_us;
-			result.nb_packets_errors += periodic_result.nb_packets_errors;
+			result->nb_packets_sent += periodic_result.nb_packets_sent;
+			result->client_time_in_us += periodic_result.client_time_in_us;
+			result->nb_packets_errors += periodic_result.nb_packets_errors;
 		}
 
-		result.packet_size = periodic_result.packet_size;
+		result->packet_size = periodic_result.packet_size;
 
 	} else {
-		ret = tcp_upload(sock, param.duration_ms, param.packet_size, &result);
+		ret = tcp_upload(sock, param.duration_ms, param.packet_size, result);
 		if (ret < 0) {
 			upload_ctx->callback(ZPERF_SESSION_ERROR, NULL,
 					     upload_ctx->user_data);
@@ -213,7 +244,7 @@ static void tcp_upload_async_work(struct k_work *work)
 		}
 	}
 
-	upload_ctx->callback(ZPERF_SESSION_FINISHED, &result,
+	upload_ctx->callback(ZPERF_SESSION_FINISHED, result,
 			     upload_ctx->user_data);
 cleanup:
 	zsock_close(sock);
@@ -226,6 +257,54 @@ int zperf_tcp_upload_async(const struct zperf_upload_params *param,
 		return -EINVAL;
 	}
 
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+	struct k_work_q *queue;
+	struct zperf_work *zperf;
+	struct session *ses;
+	k_tid_t tid;
+
+	ses = get_free_session(&param->peer_addr, SESSION_TCP);
+	if (ses == NULL) {
+		NET_ERR("Cannot get a session!");
+		return -ENOENT;
+	}
+
+	if (k_work_is_pending(&ses->async_upload_ctx.work)) {
+		NET_ERR("[%d] upload already in progress", ses->id);
+		return -EBUSY;
+	}
+
+	memcpy(&ses->async_upload_ctx.param, param, sizeof(*param));
+
+	ses->proto = SESSION_TCP;
+	ses->async_upload_ctx.callback = callback;
+	ses->async_upload_ctx.user_data = user_data;
+
+	zperf = get_queue(SESSION_TCP, ses->id);
+
+	queue = zperf->queue;
+	if (queue == NULL) {
+		NET_ERR("Cannot get a work queue!");
+		return -ENOENT;
+	}
+
+	tid = k_work_queue_thread_get(queue);
+	k_thread_priority_set(tid, ses->async_upload_ctx.param.options.thread_priority);
+
+	k_work_init(&ses->async_upload_ctx.work, tcp_upload_async_work);
+
+	ses->start_time = k_uptime_ticks();
+	ses->zperf = zperf;
+	ses->wait_for_start = param->options.wait_for_start;
+
+	zperf_async_work_submit(SESSION_TCP, ses->id, &ses->async_upload_ctx.work);
+
+	NET_DBG("[%d] thread %p priority %d name %s", ses->id, k_current_get(),
+		k_thread_priority_get(k_current_get()),
+		k_thread_name_get(k_current_get()));
+
+#else /* CONFIG_ZPERF_SESSION_PER_THREAD */
+
 	if (k_work_is_pending(&tcp_async_upload_ctx.work)) {
 		return -EBUSY;
 	}
@@ -234,12 +313,16 @@ int zperf_tcp_upload_async(const struct zperf_upload_params *param,
 	tcp_async_upload_ctx.callback = callback;
 	tcp_async_upload_ctx.user_data = user_data;
 
-	zperf_async_work_submit(&tcp_async_upload_ctx.work);
+	zperf_async_work_submit(SESSION_TCP, -1, &tcp_async_upload_ctx.work);
+
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
 
 	return 0;
 }
 
 void zperf_tcp_uploader_init(void)
 {
+#if !defined(CONFIG_ZPERF_SESSION_PER_THREAD)
 	k_work_init(&tcp_async_upload_ctx.work, tcp_upload_async_work);
+#endif /* !CONFIG_ZPERF_SESSION_PER_THREAD */
 }
diff --git a/subsys/net/lib/zperf/zperf_udp_receiver.c b/subsys/net/lib/zperf/zperf_udp_receiver.c
index c29fb022f25..62ce71da724 100644
--- a/subsys/net/lib/zperf/zperf_udp_receiver.c
+++ b/subsys/net/lib/zperf/zperf_udp_receiver.c
@@ -315,7 +315,7 @@ static void udp_receiver_cleanup(void)
 static int udp_recv_data(struct net_socket_service_event *pev)
 {
 	static uint8_t buf[UDP_RECEIVER_BUF_SIZE];
-	int ret = 0;
+	int ret = 1;
 	int family, sock_error;
 	struct sockaddr addr;
 	socklen_t optlen = sizeof(int);
@@ -341,19 +341,25 @@ static int udp_recv_data(struct net_socket_service_event *pev)
 		return 0;
 	}
 
-	ret = zsock_recvfrom(pev->event.fd, buf, sizeof(buf), 0,
-			     &addr, &addrlen);
-	if (ret < 0) {
-		ret = -errno;
-		(void)zsock_getsockopt(pev->event.fd, SOL_SOCKET,
-				       SO_DOMAIN, &family, &optlen);
-		NET_ERR("recv failed on IPv%d socket (%d)",
-			family == AF_INET ? 4 : 6, -ret);
-		goto error;
-	}
+	while (ret > 0) {
+		ret = zsock_recvfrom(pev->event.fd, buf, sizeof(buf), ZSOCK_MSG_DONTWAIT,
+				     &addr, &addrlen);
+		if ((ret < 0) && (errno == EAGAIN)) {
+			ret = 0;
+			break;
+		}
 
-	udp_received(pev->event.fd, &addr, buf, ret);
+		if (ret < 0) {
+			ret = -errno;
+			(void)zsock_getsockopt(pev->event.fd, SOL_SOCKET,
+					       SO_DOMAIN, &family, &optlen);
+			NET_ERR("recv failed on IPv%d socket (%d)",
+				family == AF_INET ? 4 : 6, -ret);
+			goto error;
+		}
 
+		udp_received(pev->event.fd, &addr, buf, ret);
+	}
 	return ret;
 
 error:
diff --git a/subsys/net/lib/zperf/zperf_udp_uploader.c b/subsys/net/lib/zperf/zperf_udp_uploader.c
index daf2cf21d01..daeee4a43f2 100644
--- a/subsys/net/lib/zperf/zperf_udp_uploader.c
+++ b/subsys/net/lib/zperf/zperf_udp_uploader.c
@@ -13,18 +13,22 @@ LOG_MODULE_DECLARE(net_zperf, CONFIG_NET_ZPERF_LOG_LEVEL);
 #include <zephyr/net/zperf.h>
 
 #include "zperf_internal.h"
+#include "zperf_session.h"
 
 static uint8_t sample_packet[sizeof(struct zperf_udp_datagram) +
 			     sizeof(struct zperf_client_hdr_v1) +
 			     PACKET_SIZE_MAX];
 
+#if !defined(CONFIG_ZPERF_SESSION_PER_THREAD)
 static struct zperf_async_upload_context udp_async_upload_ctx;
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
 
 static inline void zperf_upload_decode_stat(const uint8_t *data,
 					    size_t datalen,
 					    struct zperf_results *results)
 {
 	struct zperf_server_hdr *stat;
+	uint32_t flags;
 
 	if (datalen < sizeof(struct zperf_udp_datagram) +
 		      sizeof(struct zperf_server_hdr)) {
@@ -33,6 +37,10 @@ static inline void zperf_upload_decode_stat(const uint8_t *data,
 
 	stat = (struct zperf_server_hdr *)
 			(data + sizeof(struct zperf_udp_datagram));
+	flags = ntohl(UNALIGNED_GET(&stat->flags));
+	if (!(flags & ZPERF_FLAGS_VERSION1)) {
+		NET_WARN("Unexpected response flags");
+	}
 
 	results->nb_packets_rcvd = ntohl(UNALIGNED_GET(&stat->datagrams));
 	results->nb_packets_lost = ntohl(UNALIGNED_GET(&stat->error_cnt));
@@ -330,20 +338,47 @@ int zperf_udp_upload(const struct zperf_upload_params *param,
 
 static void udp_upload_async_work(struct k_work *work)
 {
-	struct zperf_async_upload_context *upload_ctx =
-		&udp_async_upload_ctx;
-	struct zperf_results result;
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+	struct session *ses;
+	struct zperf_async_upload_context *upload_ctx;
+	struct zperf_results *result;
+
+	ses = CONTAINER_OF(work, struct session, async_upload_ctx.work);
+	upload_ctx = &ses->async_upload_ctx;
+
+	if (ses->wait_for_start) {
+		NET_INFO("[%d] %s waiting for start", ses->id, "UDP");
+
+		/* Wait for the start event to be set */
+		k_event_wait(ses->zperf->start_event, START_EVENT, true, K_FOREVER);
+
+		NET_INFO("[%d] %s starting", ses->id, "UDP");
+	}
+
+	NET_DBG("[%d] thread %p priority %d name %s", ses->id, k_current_get(),
+		k_thread_priority_get(k_current_get()),
+		k_thread_name_get(k_current_get()));
+
+	result = &ses->result;
+
+	ses->in_progress = true;
+#else
+	struct zperf_async_upload_context *upload_ctx = &udp_async_upload_ctx;
+	struct zperf_results result_storage = { 0 };
+	struct zperf_results *result = &result_storage;
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
+
 	int ret;
 
 	upload_ctx->callback(ZPERF_SESSION_STARTED, NULL,
 			     upload_ctx->user_data);
 
-	ret = zperf_udp_upload(&upload_ctx->param, &result);
+	ret = zperf_udp_upload(&upload_ctx->param, result);
 	if (ret < 0) {
 		upload_ctx->callback(ZPERF_SESSION_ERROR, NULL,
 				     upload_ctx->user_data);
 	} else {
-		upload_ctx->callback(ZPERF_SESSION_FINISHED, &result,
+		upload_ctx->callback(ZPERF_SESSION_FINISHED, result,
 				     upload_ctx->user_data);
 	}
 }
@@ -355,6 +390,54 @@ int zperf_udp_upload_async(const struct zperf_upload_params *param,
 		return -EINVAL;
 	}
 
+#ifdef CONFIG_ZPERF_SESSION_PER_THREAD
+	struct k_work_q *queue;
+	struct zperf_work *zperf;
+	struct session *ses;
+	k_tid_t tid;
+
+	ses = get_free_session(&param->peer_addr, SESSION_UDP);
+	if (ses == NULL) {
+		NET_ERR("Cannot get a session!");
+		return -ENOENT;
+	}
+
+	if (k_work_is_pending(&ses->async_upload_ctx.work)) {
+		NET_ERR("[%d] upload already in progress", ses->id);
+		return -EBUSY;
+	}
+
+	memcpy(&ses->async_upload_ctx.param, param, sizeof(*param));
+
+	ses->proto = SESSION_UDP;
+	ses->async_upload_ctx.callback = callback;
+	ses->async_upload_ctx.user_data = user_data;
+
+	zperf = get_queue(SESSION_UDP, ses->id);
+
+	queue = zperf->queue;
+	if (queue == NULL) {
+		NET_ERR("Cannot get a work queue!");
+		return -ENOENT;
+	}
+
+	tid = k_work_queue_thread_get(queue);
+	k_thread_priority_set(tid, ses->async_upload_ctx.param.options.thread_priority);
+
+	k_work_init(&ses->async_upload_ctx.work, udp_upload_async_work);
+
+	ses->start_time = k_uptime_ticks();
+	ses->zperf = zperf;
+	ses->wait_for_start = param->options.wait_for_start;
+
+	zperf_async_work_submit(SESSION_UDP, ses->id, &ses->async_upload_ctx.work);
+
+	NET_DBG("[%d] thread %p priority %d name %s", ses->id, k_current_get(),
+		k_thread_priority_get(k_current_get()),
+		k_thread_name_get(k_current_get()));
+
+#else /* CONFIG_ZPERF_SESSION_PER_THREAD */
+
 	if (k_work_is_pending(&udp_async_upload_ctx.work)) {
 		return -EBUSY;
 	}
@@ -363,12 +446,16 @@ int zperf_udp_upload_async(const struct zperf_upload_params *param,
 	udp_async_upload_ctx.callback = callback;
 	udp_async_upload_ctx.user_data = user_data;
 
-	zperf_async_work_submit(&udp_async_upload_ctx.work);
+	zperf_async_work_submit(SESSION_UDP, -1, &udp_async_upload_ctx.work);
+
+#endif /* CONFIG_ZPERF_SESSION_PER_THREAD */
 
 	return 0;
 }
 
 void zperf_udp_uploader_init(void)
 {
+#if !defined(CONFIG_ZPERF_SESSION_PER_THREAD)
 	k_work_init(&udp_async_upload_ctx.work, udp_upload_async_work);
+#endif /* !CONFIG_ZPERF_SESSION_PER_THREAD */
 }
diff --git a/subsys/net/pkt_filter/CMakeLists.txt b/subsys/net/pkt_filter/CMakeLists.txt
index 6147f1ab125..d8fd06af74a 100644
--- a/subsys/net/pkt_filter/CMakeLists.txt
+++ b/subsys/net/pkt_filter/CMakeLists.txt
@@ -5,5 +5,6 @@ if(CONFIG_NET_PKT_FILTER)
 zephyr_library()
 zephyr_library_sources(base.c)
 zephyr_library_sources_ifdef(CONFIG_NET_L2_ETHERNET ethernet.c)
+zephyr_library_include_directories(${ZEPHYR_BASE}/subsys/net/ip)
 
 endif()
diff --git a/subsys/net/pkt_filter/base.c b/subsys/net/pkt_filter/base.c
index bb2eb9f085b..289a55e9d60 100644
--- a/subsys/net/pkt_filter/base.c
+++ b/subsys/net/pkt_filter/base.c
@@ -49,6 +49,7 @@ struct npf_rule_list npf_ipv6_recv_rules = {
 /*
  * Helper function
  */
+#if defined(CONFIG_NET_PKT_FILTER_IPV4_HOOK) || defined(CONFIG_NET_PKT_FILTER_IPV6_HOOK)
 static struct npf_rule_list *get_ip_rules(uint8_t pf)
 {
 	switch (pf) {
@@ -68,7 +69,7 @@ static struct npf_rule_list *get_ip_rules(uint8_t pf)
 
 	return NULL;
 }
-
+#endif /* CONFIG_NET_PKT_FILTER_IPV4_HOOK || CONFIG_NET_PKT_FILTER_IPV6_HOOK */
 /*
  * Rule application
  */
@@ -86,7 +87,9 @@ static bool apply_tests(struct npf_rule *rule, struct net_pkt *pkt)
 	for (i = 0; i < rule->nb_tests; i++) {
 		test = rule->tests[i];
 		result = test->fn(test, pkt);
-		NET_DBG("test %p result %d", test, result);
+		NET_DBG("test %s (%p) result %d",
+			COND_CODE_1(NPF_TEST_ENABLE_NAME, (test->name), ("")),
+			test, result);
 		if (result == false) {
 			return false;
 		}
@@ -239,6 +242,10 @@ bool npf_iface_match(struct npf_test *test, struct net_pkt *pkt)
 	struct npf_test_iface *test_iface =
 			CONTAINER_OF(test, struct npf_test_iface, test);
 
+	NET_DBG("iface %d pkt %d",
+		net_if_get_by_iface(test_iface->iface),
+		net_if_get_by_iface(net_pkt_iface(pkt)));
+
 	return test_iface->iface == net_pkt_iface(pkt);
 }
 
@@ -252,6 +259,10 @@ bool npf_orig_iface_match(struct npf_test *test, struct net_pkt *pkt)
 	struct npf_test_iface *test_iface =
 			CONTAINER_OF(test, struct npf_test_iface, test);
 
+	NET_DBG("orig iface %d pkt %d",
+		net_if_get_by_iface(test_iface->iface),
+		net_if_get_by_iface(net_pkt_orig_iface(pkt)));
+
 	return test_iface->iface == net_pkt_orig_iface(pkt);
 }
 
@@ -266,6 +277,9 @@ bool npf_size_inbounds(struct npf_test *test, struct net_pkt *pkt)
 			CONTAINER_OF(test, struct npf_test_size_bounds, test);
 	size_t pkt_size = net_pkt_get_len(pkt);
 
+	NET_DBG("pkt_size %zu min %zu max %zu",
+		pkt_size, bounds->min, bounds->max);
+
 	return pkt_size >= bounds->min && pkt_size <= bounds->max;
 }
 
@@ -297,3 +311,156 @@ bool npf_ip_src_addr_unmatch(struct npf_test *test, struct net_pkt *pkt)
 {
 	return !npf_ip_src_addr_match(test, pkt);
 }
+
+static void rules_cb(struct npf_rule_list *rules, enum npf_rule_type type,
+		     npf_rule_cb_t cb, void *user_data)
+{
+	struct npf_rule *rule;
+
+	SYS_SLIST_FOR_EACH_CONTAINER(&rules->rule_head, rule, node) {
+		cb(rule, type, user_data);
+	}
+}
+
+void npf_rules_foreach(npf_rule_cb_t cb, void *user_data)
+{
+	rules_cb(&npf_send_rules, NPF_RULE_TYPE_SEND, cb, user_data);
+	rules_cb(&npf_recv_rules, NPF_RULE_TYPE_RECV, cb, user_data);
+
+#ifdef CONFIG_NET_PKT_FILTER_LOCAL_IN_HOOK
+	rules_cb(&npf_local_in_recv_rules, NPF_RULE_TYPE_LOCAL_IN_RECV, cb, user_data);
+#endif /* CONFIG_NET_PKT_FILTER_LOCAL_IN_HOOK */
+
+#ifdef CONFIG_NET_PKT_FILTER_IPV4_HOOK
+	rules_cb(&npf_ipv4_recv_rules, NPF_RULE_TYPE_IPV4_RECV, cb, user_data);
+#endif /* CONFIG_NET_PKT_FILTER_IPV4_HOOK */
+
+#ifdef CONFIG_NET_PKT_FILTER_IPV6_HOOK
+	rules_cb(&npf_ipv6_recv_rules, NPF_RULE_TYPE_IPV6_RECV, cb, user_data);
+#endif /* CONFIG_NET_PKT_FILTER_IPV6_HOOK */
+}
+
+#include "net_private.h" /* for net_sprint_addr() */
+
+const char *npf_test_get_str(struct npf_test *test, char *buf, size_t len)
+{
+#if defined(CONFIG_NET_SHELL_PKT_FILTER_SUPPORTED)
+	if (test->type == NPF_TEST_TYPE_IFACE_MATCH ||
+	    test->type == NPF_TEST_TYPE_IFACE_UNMATCH ||
+	    test->type == NPF_TEST_TYPE_ORIG_IFACE_MATCH ||
+	    test->type == NPF_TEST_TYPE_ORIG_IFACE_UNMATCH) {
+		struct npf_test_iface *test_iface =
+			CONTAINER_OF(test, struct npf_test_iface, test);
+
+		snprintk(buf, len, "[%d]", net_if_get_by_iface(test_iface->iface));
+
+	} else if (test->type == NPF_TEST_TYPE_SIZE_BOUNDS ||
+		   test->type == NPF_TEST_TYPE_SIZE_MIN ||
+		   test->type == NPF_TEST_TYPE_SIZE_MAX) {
+		struct npf_test_size_bounds *bounds =
+			CONTAINER_OF(test, struct npf_test_size_bounds, test);
+
+		if (test->type == NPF_TEST_TYPE_SIZE_MIN ||
+		    test->type == NPF_TEST_TYPE_SIZE_MAX) {
+			snprintk(buf, len, "[%zu]",
+				 test->type == NPF_TEST_TYPE_SIZE_MIN ?
+				 bounds->min :  bounds->max);
+		} else {
+			snprintk(buf, len, "[%zu-%zu]", bounds->min, bounds->max);
+		}
+
+	} else if (test->type == NPF_TEST_TYPE_IP_SRC_ADDR_ALLOWLIST ||
+		   test->type == NPF_TEST_TYPE_IP_SRC_ADDR_BLOCKLIST) {
+		struct npf_test_ip *test_ip =
+			CONTAINER_OF(test, struct npf_test_ip, test);
+		int pos = 1;
+
+		if (len < 2) {
+			goto out;
+		}
+
+		if (test_ip->ipaddr_num == 0) {
+			snprintk(buf, len, "[]");
+			goto out;
+		}
+
+		buf[0] = '[';
+
+		for (uint32_t i = 0; i < test_ip->ipaddr_num; i++) {
+			if (IS_ENABLED(CONFIG_NET_IPV4) &&
+			    test_ip->addr_family == AF_INET) {
+				struct in_addr *addr =
+					&((struct in_addr *)test_ip->ipaddr)[i];
+
+				pos += snprintk(buf + pos, len - pos,
+						"%s%s", pos > 1 ? "," : "",
+						net_sprint_ipv4_addr(addr));
+
+			} else if (IS_ENABLED(CONFIG_NET_IPV6) &&
+				   test_ip->addr_family == AF_INET6) {
+				struct in6_addr *addr =
+					&((struct in6_addr *)test_ip->ipaddr)[i];
+
+				pos += snprintk(buf + pos, len - pos,
+						"%s%s", pos > 1 ? "," : "",
+						net_sprint_ipv6_addr(addr));
+			}
+		}
+
+		if (pos >= len) {
+			goto out;
+		}
+
+		buf[pos] = ']';
+
+	} else if (test->type == NPF_TEST_TYPE_ETH_SRC_ADDR_MATCH ||
+		   test->type == NPF_TEST_TYPE_ETH_SRC_ADDR_UNMATCH ||
+		   test->type == NPF_TEST_TYPE_ETH_DST_ADDR_MATCH ||
+		   test->type == NPF_TEST_TYPE_ETH_DST_ADDR_UNMATCH ||
+		   test->type == NPF_TEST_TYPE_ETH_SRC_ADDR_MASK_MATCH ||
+		   test->type == NPF_TEST_TYPE_ETH_DST_ADDR_MASK_MATCH) {
+		struct npf_test_eth_addr *test_eth =
+			CONTAINER_OF(test, struct npf_test_eth_addr, test);
+		int pos = 1;
+
+		if (len < 2) {
+			goto out;
+		}
+
+		if (test_eth->nb_addresses == 0) {
+			snprintk(buf, len, "[]");
+			goto out;
+		}
+
+		buf[0] = '[';
+
+		for (uint32_t i = 0; i < test_eth->nb_addresses; i++) {
+			pos += snprintk(buf + pos, len - pos,
+					"%s%s", pos > 1 ? "," : "",
+					net_sprint_ll_addr(
+						(const uint8_t *)(&test_eth->addresses[i]),
+						NET_ETH_ADDR_LEN));
+		}
+
+		if (pos >= len) {
+			goto out;
+		}
+
+		buf[pos] = ']';
+
+	} else if (test->type == NPF_TEST_TYPE_ETH_TYPE_MATCH ||
+		   test->type == NPF_TEST_TYPE_ETH_TYPE_UNMATCH ||
+		   test->type == NPF_TEST_TYPE_ETH_VLAN_TYPE_MATCH ||
+		   test->type == NPF_TEST_TYPE_ETH_VLAN_TYPE_UNMATCH) {
+		struct npf_test_eth_type *test_eth =
+			CONTAINER_OF(test, struct npf_test_eth_type, test);
+
+		snprintk(buf, len, "[0x%04x]", ntohs(test_eth->type));
+	}
+
+out:
+	return test->name;
+#else
+	return "<UNKNOWN>";
+#endif
+}
diff --git a/subsys/net/pkt_filter/ethernet.c b/subsys/net/pkt_filter/ethernet.c
index 9dddd899885..22ddd939dcf 100644
--- a/subsys/net/pkt_filter/ethernet.c
+++ b/subsys/net/pkt_filter/ethernet.c
@@ -72,6 +72,10 @@ bool npf_eth_type_match(struct npf_test *test, struct net_pkt *pkt)
 	struct net_eth_hdr *eth_hdr = NET_ETH_HDR(pkt);
 
 	/* note: type_match->type is assumed to be in network order already */
+	NET_DBG("proto type 0x%04x pkt 0x%04x",
+		ntohs(test_eth_type->type),
+		ntohs(eth_hdr->type));
+
 	return eth_hdr->type == test_eth_type->type;
 }
 
@@ -79,3 +83,23 @@ bool npf_eth_type_unmatch(struct npf_test *test, struct net_pkt *pkt)
 {
 	return !npf_eth_type_match(test, pkt);
 }
+
+bool npf_eth_vlan_type_match(struct npf_test *test, struct net_pkt *pkt)
+{
+	struct npf_test_eth_type *test_eth_type =
+			CONTAINER_OF(test, struct npf_test_eth_type, test);
+	struct net_eth_vlan_hdr *eth_hdr =
+		(struct net_eth_vlan_hdr *)NET_ETH_HDR(pkt);
+
+	/* note: type_match->type is assumed to be in network order already */
+	NET_DBG("proto type 0x%04x pkt 0x%04x",
+		ntohs(test_eth_type->type),
+		ntohs(eth_hdr->type));
+
+	return eth_hdr->type == test_eth_type->type;
+}
+
+bool npf_eth_vlan_type_unmatch(struct npf_test *test, struct net_pkt *pkt)
+{
+	return !npf_eth_vlan_type_match(test, pkt);
+}
diff --git a/subsys/pm/Kconfig b/subsys/pm/Kconfig
index 8acee7c6848..19078d02b81 100644
--- a/subsys/pm/Kconfig
+++ b/subsys/pm/Kconfig
@@ -53,6 +53,26 @@ config PM_NEED_ALL_DEVICES_IDLE
 	  When this option is enabled, check that no devices are busy before
 	  entering into system low power mode.
 
+choice PM_PREWAKEUP_CONV_MODE
+	prompt "Pre-wakeup microseconds to ticks conversion method"
+	default PM_PREWAKEUP_CONV_MODE_NEAR
+	help
+	  Exit latency for each power state is given in microseconds. It is converted
+	  to ticks and system clock is set to wake up the core earlier before scheduled
+	  wake up. This option specifies rounding that is used when converting exit
+	  latency from microseconds to system ticks.
+
+config PM_PREWAKEUP_CONV_MODE_NEAR
+	bool "Nearest"
+
+config PM_PREWAKEUP_CONV_MODE_CEIL
+	bool "Round up"
+
+config PM_PREWAKEUP_CONV_MODE_FLOOR
+	bool "Round down"
+
+endchoice
+
 endif # PM
 
 config PM_DEVICE
@@ -101,14 +121,6 @@ config PM_DEVICE_RUNTIME
 	  enabled, devices can be suspended or resumed based on the device
 	  usage even while the CPU or system is running.
 
-config PM_DEVICE_RUNTIME_EXCLUSIVE
-	depends on PM_DEVICE_RUNTIME
-	bool "[DEPRECATED] Use only on Runtime Power Management on system suspend / resume"
-	select DEPRECATED
-	help
-	  On system suspend / resume do not trigger the Device PM hooks but
-	  only rely on Runtime PM to manage the devices power states.
-
 config PM_DEVICE_SHELL
 	bool "Device Power Management shell"
 	depends on SHELL
@@ -118,7 +130,7 @@ config PM_DEVICE_SHELL
 
 config PM_DEVICE_SYSTEM_MANAGED
 	bool "System-Managed Device Power Management"
-	default y if !PM_DEVICE_RUNTIME_EXCLUSIVE && !PM_DEVICE_RUNTIME
+	default y if !PM_DEVICE_RUNTIME
 	help
 	  This option enables the system-managed device power
 	  management.  The power management subsystem will suspend
diff --git a/subsys/pm/device.c b/subsys/pm/device.c
index 518e20a8630..a1a7e92ee92 100644
--- a/subsys/pm/device.c
+++ b/subsys/pm/device.c
@@ -361,10 +361,13 @@ int pm_device_driver_init(const struct device *dev,
 	struct pm_device_base *pm = dev->pm_base;
 	int rc;
 
+	/* Device is currently in the OFF state */
+	if (pm) {
+		pm->state = PM_DEVICE_STATE_OFF;
+	}
+
 	/* Work only needs to be performed if the device is powered */
 	if (!pm_device_is_powered(dev)) {
-		/* Start in off mode */
-		pm_device_init_off(dev);
 		return 0;
 	}
 
@@ -380,16 +383,21 @@ int pm_device_driver_init(const struct device *dev,
 		return action_cb(dev, PM_DEVICE_ACTION_RESUME);
 	}
 
+	/* Device is currently in the SUSPENDED state */
+	pm->state = PM_DEVICE_STATE_SUSPENDED;
+
 	/* If device will have PM device runtime enabled */
 	if (IS_ENABLED(CONFIG_PM_DEVICE_RUNTIME) &&
 	    atomic_test_bit(&pm->flags, PM_DEVICE_FLAG_RUNTIME_AUTO)) {
-		/* Init into suspend mode.
-		 * This saves a SUSPENDED->ACTIVE->SUSPENDED cycle.
-		 */
-		pm_device_init_suspended(dev);
 		return 0;
 	}
 
 	/* Startup into active mode */
-	return action_cb(dev, PM_DEVICE_ACTION_RESUME);
+	rc = action_cb(dev, PM_DEVICE_ACTION_RESUME);
+
+	/* Device is now in the ACTIVE state */
+	pm->state = PM_DEVICE_STATE_ACTIVE;
+
+	/* Return the PM_DEVICE_ACTION_RESUME result */
+	return rc;
 }
diff --git a/subsys/pm/pm.c b/subsys/pm/pm.c
index ba90fe7b42f..b4f7c2d765f 100644
--- a/subsys/pm/pm.c
+++ b/subsys/pm/pm.c
@@ -26,19 +26,15 @@ LOG_MODULE_REGISTER(pm, CONFIG_PM_LOG_LEVEL);
 static ATOMIC_DEFINE(z_post_ops_required, CONFIG_MP_MAX_NUM_CPUS);
 static sys_slist_t pm_notifiers = SYS_SLIST_STATIC_INIT(&pm_notifiers);
 
-/*
- * Properly initialize cpu power states. Do not make assumptions that
- * ACTIVE_STATE is 0
- */
-#define CPU_PM_STATE_INIT(_, __)		\
-	{ .state = PM_STATE_ACTIVE }
-static struct pm_state_info z_cpus_pm_state[] = {
-	LISTIFY(CONFIG_MP_MAX_NUM_CPUS, CPU_PM_STATE_INIT, (,))
-};
+/* Convert exit-latency-us to ticks using specified method. */
+#define EXIT_LATENCY_US_TO_TICKS(us)						    \
+	IS_ENABLED(CONFIG_PM_PREWAKEUP_CONV_MODE_NEAR) ? k_us_to_ticks_near32(us) : \
+	IS_ENABLED(CONFIG_PM_PREWAKEUP_CONV_MODE_CEIL) ? k_us_to_ticks_ceil32(us) : \
+		k_us_to_ticks_floor32(us)
 
-static struct pm_state_info z_cpus_pm_forced_state[] = {
-	LISTIFY(CONFIG_MP_MAX_NUM_CPUS, CPU_PM_STATE_INIT, (,))
-};
+/* State pointers which are set to NULL indicate ACTIVE state. */
+static const struct pm_state_info *z_cpus_pm_state[CONFIG_MP_MAX_NUM_CPUS];
+static const struct pm_state_info *z_cpus_pm_forced_state[CONFIG_MP_MAX_NUM_CPUS];
 
 static struct k_spinlock pm_forced_state_lock;
 static struct k_spinlock pm_notifier_lock;
@@ -62,7 +58,7 @@ static inline void pm_state_notify(bool entering_state)
 		}
 
 		if (callback) {
-			callback(z_cpus_pm_state[_current_cpu->id].state);
+			callback(z_cpus_pm_state[CPU_ID]->state);
 		}
 	}
 	k_spin_unlock(&pm_notifier_lock, pm_notifier_key);
@@ -93,7 +89,7 @@ static inline int32_t ticks_expiring_sooner(int32_t ticks1, int32_t ticks2)
 
 void pm_system_resume(void)
 {
-	uint8_t id = _current_cpu->id;
+	uint8_t id = CPU_ID;
 
 	/*
 	 * This notification is called from the ISR of the event
@@ -110,19 +106,19 @@ void pm_system_resume(void)
 	if (atomic_test_and_clear_bit(z_post_ops_required, id)) {
 #ifdef CONFIG_PM_DEVICE_SYSTEM_MANAGED
 		if (atomic_add(&_cpus_active, 1) == 0) {
-			if ((z_cpus_pm_state[id].state != PM_STATE_RUNTIME_IDLE) &&
-					!z_cpus_pm_state[id].pm_device_disabled) {
+			if ((z_cpus_pm_state[id]->state != PM_STATE_RUNTIME_IDLE) &&
+					!z_cpus_pm_state[id]->pm_device_disabled) {
 				pm_resume_devices();
 			}
 		}
 #endif
-		pm_state_exit_post_ops(z_cpus_pm_state[id].state, z_cpus_pm_state[id].substate_id);
+		pm_state_exit_post_ops(z_cpus_pm_state[id]->state,
+				       z_cpus_pm_state[id]->substate_id);
 		pm_state_notify(false);
 #ifdef CONFIG_SYS_CLOCK_EXISTS
 		sys_clock_idle_exit();
 #endif /* CONFIG_SYS_CLOCK_EXISTS */
-		z_cpus_pm_state[id] = (struct pm_state_info){PM_STATE_ACTIVE, 0, false,
-			0, 0};
+		z_cpus_pm_state[id] = NULL;
 	}
 }
 
@@ -133,8 +129,10 @@ bool pm_state_force(uint8_t cpu, const struct pm_state_info *info)
 	__ASSERT(info->state < PM_STATE_COUNT,
 		 "Invalid power state %d!", info->state);
 
+	info = pm_state_get(cpu, info->state, info->substate_id);
+
 	key = k_spin_lock(&pm_forced_state_lock);
-	z_cpus_pm_forced_state[cpu] = *info;
+	z_cpus_pm_forced_state[cpu] = info;
 	k_spin_unlock(&pm_forced_state_lock, key);
 
 	return true;
@@ -142,12 +140,18 @@ bool pm_state_force(uint8_t cpu, const struct pm_state_info *info)
 
 bool pm_system_suspend(int32_t kernel_ticks)
 {
-	uint8_t id = _current_cpu->id;
+	uint8_t id = CPU_ID;
 	k_spinlock_key_t key;
 	int32_t ticks, events_ticks;
+	uint32_t exit_latency_ticks;
 
 	SYS_PORT_TRACING_FUNC_ENTER(pm, system_suspend, kernel_ticks);
 
+	if (!pm_policy_state_any_active()) {
+		/* Return early if all states are unavailable. */
+		return false;
+	}
+
 	/*
 	 * CPU needs to be fully wake up before the event is triggered.
 	 * We need to find out first the ticks to the next event
@@ -156,54 +160,43 @@ bool pm_system_suspend(int32_t kernel_ticks)
 	ticks = ticks_expiring_sooner(kernel_ticks, events_ticks);
 
 	key = k_spin_lock(&pm_forced_state_lock);
-	if (z_cpus_pm_forced_state[id].state != PM_STATE_ACTIVE) {
+	if (z_cpus_pm_forced_state[id] != NULL) {
 		z_cpus_pm_state[id] = z_cpus_pm_forced_state[id];
-		z_cpus_pm_forced_state[id].state = PM_STATE_ACTIVE;
+		z_cpus_pm_forced_state[id] = NULL;
 	} else {
-		const struct pm_state_info *info;
-
-		info = pm_policy_next_state(id, ticks);
-		if (info != NULL) {
-			z_cpus_pm_state[id] = *info;
-		} else {
-			z_cpus_pm_state[id].state = PM_STATE_ACTIVE;
-		}
+		z_cpus_pm_state[id] = pm_policy_next_state(id, ticks);
 	}
 	k_spin_unlock(&pm_forced_state_lock, key);
 
-	if (z_cpus_pm_state[id].state == PM_STATE_ACTIVE) {
+	if (z_cpus_pm_state[id] == NULL) {
 		LOG_DBG("No PM operations done.");
-		SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks,
-				   z_cpus_pm_state[id].state);
+		SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks, PM_STATE_ACTIVE);
 		return false;
 	}
 
 #ifdef CONFIG_PM_DEVICE_SYSTEM_MANAGED
 	if (atomic_sub(&_cpus_active, 1) == 1) {
-		if ((z_cpus_pm_state[id].state != PM_STATE_RUNTIME_IDLE) &&
-		    !z_cpus_pm_state[id].pm_device_disabled) {
+		if ((z_cpus_pm_state[id]->state != PM_STATE_RUNTIME_IDLE) &&
+		    !z_cpus_pm_state[id]->pm_device_disabled) {
 			if (!pm_suspend_devices()) {
 				pm_resume_devices();
-				z_cpus_pm_state[id].state = PM_STATE_ACTIVE;
+				z_cpus_pm_state[id] = NULL;
 				(void)atomic_add(&_cpus_active, 1);
 				SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks,
-							   z_cpus_pm_state[id].state);
+							   PM_STATE_ACTIVE);
 				return false;
 			}
 		}
 	}
 #endif
 
-	if ((z_cpus_pm_state[id].exit_latency_us != 0) &&
-	    (ticks != K_TICKS_FOREVER)) {
+	exit_latency_ticks = EXIT_LATENCY_US_TO_TICKS(z_cpus_pm_state[id]->exit_latency_us);
+	if ((exit_latency_ticks > 0) && (ticks != K_TICKS_FOREVER)) {
 		/*
 		 * We need to set the timer to interrupt a little bit early to
 		 * accommodate the time required by the CPU to fully wake up.
 		 */
-		sys_clock_set_timeout(ticks -
-		     k_us_to_ticks_ceil32(
-			     z_cpus_pm_state[id].exit_latency_us),
-				     true);
+		sys_clock_set_timeout(ticks - exit_latency_ticks, true);
 	}
 
 	/*
@@ -220,15 +213,16 @@ bool pm_system_suspend(int32_t kernel_ticks)
 	/* Enter power state */
 	pm_state_notify(true);
 	atomic_set_bit(z_post_ops_required, id);
-	pm_state_set(z_cpus_pm_state[id].state, z_cpus_pm_state[id].substate_id);
+	pm_state_set(z_cpus_pm_state[id]->state, z_cpus_pm_state[id]->substate_id);
 	pm_stats_stop();
 
 	/* Wake up sequence starts here */
-	pm_stats_update(z_cpus_pm_state[id].state);
+	pm_stats_update(z_cpus_pm_state[id]->state);
 	pm_system_resume();
 	k_sched_unlock();
 	SYS_PORT_TRACING_FUNC_EXIT(pm, system_suspend, ticks,
-				   z_cpus_pm_state[id].state);
+				   z_cpus_pm_state[id] ?
+				   z_cpus_pm_state[id]->state : PM_STATE_ACTIVE);
 
 	return true;
 }
@@ -257,15 +251,9 @@ int pm_notifier_unregister(struct pm_notifier *notifier)
 
 const struct pm_state_info *pm_state_next_get(uint8_t cpu)
 {
-	return &z_cpus_pm_state[cpu];
-}
+	static const struct pm_state_info active = {
+		.state = PM_STATE_ACTIVE
+	};
 
-void z_pm_save_idle_exit(void)
-{
-	/* Some CPU low power states require notification at the ISR
-	 * to allow any operations that needs to be done before kernel
-	 * switches task or processes nested interrupts.
-	 * This can be simply ignored if not required.
-	 */
-	pm_system_resume();
+	return z_cpus_pm_state[cpu] ? z_cpus_pm_state[cpu] : &active;
 }
diff --git a/subsys/pm/pm_stats.c b/subsys/pm/pm_stats.c
index 4c1c00f3395..c937fdde722 100644
--- a/subsys/pm/pm_stats.c
+++ b/subsys/pm/pm_stats.c
@@ -53,17 +53,17 @@ SYS_INIT(pm_stats_init, PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
 
 void pm_stats_start(void)
 {
-	time_start[_current_cpu->id] = k_cycle_get_32();
+	time_start[CPU_ID] = k_cycle_get_32();
 }
 
 void pm_stats_stop(void)
 {
-	time_stop[_current_cpu->id] = k_cycle_get_32();
+	time_stop[CPU_ID] = k_cycle_get_32();
 }
 
 void pm_stats_update(enum pm_state state)
 {
-	uint8_t cpu = _current_cpu->id;
+	uint8_t cpu = CPU_ID;
 	uint32_t time_total = time_stop[cpu] - time_start[cpu];
 
 	STATS_INC(stats[cpu][state], state_count);
diff --git a/subsys/pm/policy/policy_default.c b/subsys/pm/policy/policy_default.c
index eaf317d24cf..497cf4219e6 100644
--- a/subsys/pm/policy/policy_default.c
+++ b/subsys/pm/policy/policy_default.c
@@ -9,13 +9,12 @@
 #include <zephyr/sys_clock.h>
 #include <zephyr/pm/device.h>
 
-extern int32_t max_latency_cyc;
-
 const struct pm_state_info *pm_policy_next_state(uint8_t cpu, int32_t ticks)
 {
 	int64_t cyc = -1;
 	uint8_t num_cpu_states;
 	const struct pm_state_info *cpu_states;
+	const struct pm_state_info *out_state = NULL;
 
 #ifdef CONFIG_PM_NEED_ALL_DEVICES_IDLE
 	if (pm_device_is_any_busy()) {
@@ -29,29 +28,25 @@ const struct pm_state_info *pm_policy_next_state(uint8_t cpu, int32_t ticks)
 
 	num_cpu_states = pm_state_cpu_get_all(cpu, &cpu_states);
 
-	for (int16_t i = (int16_t)num_cpu_states - 1; i >= 0; i--) {
+	for (uint32_t i = 0; i < num_cpu_states; i++) {
 		const struct pm_state_info *state = &cpu_states[i];
-		uint32_t min_residency_cyc, exit_latency_cyc;
+		uint32_t min_residency_ticks;
 
-		/* check if there is a lock on state + substate */
-		if (pm_policy_state_lock_is_active(state->state, state->substate_id)) {
-			continue;
-		}
+		min_residency_ticks =
+			k_us_to_ticks_ceil32(state->min_residency_us + state->exit_latency_us);
 
-		min_residency_cyc = k_us_to_cyc_ceil32(state->min_residency_us);
-		exit_latency_cyc = k_us_to_cyc_ceil32(state->exit_latency_us);
+		if (ticks < min_residency_ticks) {
+			/* If current state has higher residency then use the previous state; */
+			break;
+		}
 
-		/* skip state if it brings too much latency */
-		if ((max_latency_cyc >= 0) &&
-		    (exit_latency_cyc >= max_latency_cyc)) {
+		/* check if state is available. */
+		if (!pm_policy_state_is_available(state->state, state->substate_id)) {
 			continue;
 		}
 
-		if ((cyc < 0) ||
-		    (cyc >= (min_residency_cyc + exit_latency_cyc))) {
-			return state;
-		}
+		out_state = state;
 	}
 
-	return NULL;
+	return out_state;
 }
diff --git a/subsys/pm/policy/policy_device_lock.c b/subsys/pm/policy/policy_device_lock.c
index b508819fb73..b1bc92b9fd7 100644
--- a/subsys/pm/policy/policy_device_lock.c
+++ b/subsys/pm/policy/policy_device_lock.c
@@ -11,7 +11,7 @@
 #include <zephyr/pm/device.h>
 
 struct pm_state_device_constraint {
-	const struct device *const dev;
+	const char *const dev;
 	size_t pm_constraints_size;
 	struct pm_state_constraint *constraints;
 };
@@ -71,7 +71,7 @@ DT_FOREACH_STATUS_OKAY_NODE(DEVICE_CONSTRAINTS_DEFINE)
  */
 #define PM_STATE_DEVICE_CONSTRAINT_INIT(node_id)                                              \
 	{                                                                                     \
-		.dev = DEVICE_DT_GET(node_id),                                                \
+		.dev = DEVICE_DT_NAME(node_id),                                                \
 		.pm_constraints_size = DT_PROP_LEN(node_id, zephyr_disabling_power_states),   \
 		.constraints = PM_CONSTRAINTS_NAME(node_id),                                  \
 	},
@@ -91,7 +91,9 @@ void pm_policy_device_power_lock_get(const struct device *dev)
 {
 #if DT_HAS_COMPAT_STATUS_OKAY(zephyr_power_state)
 	for (size_t i = 0; i < ARRAY_SIZE(_devices_constraints); i++) {
-		if (_devices_constraints[i].dev == dev) {
+		const struct device *device = device_get_binding(_devices_constraints[i].dev);
+
+		if ((device != NULL) && (device == dev)) {
 			for (size_t j = 0; j < _devices_constraints[i].pm_constraints_size; j++) {
 				pm_policy_state_lock_get(
 						_devices_constraints[i].constraints[j].state,
@@ -107,7 +109,9 @@ void pm_policy_device_power_lock_put(const struct device *dev)
 {
 #if DT_HAS_COMPAT_STATUS_OKAY(zephyr_power_state)
 	for (size_t i = 0; i < ARRAY_SIZE(_devices_constraints); i++) {
-		if (_devices_constraints[i].dev == dev) {
+		const struct device *device = device_get_binding(_devices_constraints[i].dev);
+
+		if ((device != NULL) && (device == dev)) {
 			for (size_t j = 0; j < _devices_constraints[i].pm_constraints_size; j++) {
 				pm_policy_state_lock_put(
 						_devices_constraints[i].constraints[j].state,
diff --git a/subsys/pm/policy/policy_state_lock.c b/subsys/pm/policy/policy_state_lock.c
index 3876b76c804..f69133dfe89 100644
--- a/subsys/pm/policy/policy_state_lock.c
+++ b/subsys/pm/policy/policy_state_lock.c
@@ -10,44 +10,56 @@
 #include <zephyr/sys/__assert.h>
 #include <zephyr/sys/atomic.h>
 #include <zephyr/toolchain.h>
+#include <zephyr/spinlock.h>
 
 #if DT_HAS_COMPAT_STATUS_OKAY(zephyr_power_state)
 
-#define DT_SUB_LOCK_INIT(node_id)				\
-	{ .state = PM_STATE_DT_INIT(node_id),			\
-	  .substate_id = DT_PROP_OR(node_id, substate_id, 0),	\
-	  .lock = ATOMIC_INIT(0),				\
+#define DT_SUB_LOCK_INIT(node_id)					\
+	{ .state = PM_STATE_DT_INIT(node_id),				\
+	  .substate_id = DT_PROP_OR(node_id, substate_id, 0),		\
+	  .exit_latency_us = DT_PROP_OR(node_id, exit_latency_us, 0),	\
 	},
 
 /**
  * State and substate lock structure.
  *
- * This struct is associating a reference counting to each <state,substate>
- * couple to be used with the pm_policy_substate_lock_* functions.
+ * Struct holds all power states defined in the device tree. Array with counter
+ * variables is in RAM and n-th counter is used for n-th power state. Structure
+ * also holds exit latency for each state. It is used to disable power states
+ * based on current latency requirement.
  *
  * Operations on this array are in the order of O(n) with the number of power
  * states and this is mostly due to the random nature of the substate value
  * (that can be anything from a small integer value to a bitmask). We can
  * probably do better with an hashmap.
  */
-static struct {
+static const struct {
 	enum pm_state state;
 	uint8_t substate_id;
-	atomic_t lock;
-} substate_lock_t[] = {
+	uint32_t exit_latency_us;
+} substates[] = {
 	DT_FOREACH_STATUS_OKAY(zephyr_power_state, DT_SUB_LOCK_INIT)
 };
+static atomic_t lock_cnt[ARRAY_SIZE(substates)];
+static atomic_t latency_mask = BIT_MASK(ARRAY_SIZE(substates));
+static atomic_t unlock_mask = BIT_MASK(ARRAY_SIZE(substates));
+static struct k_spinlock lock;
 
 #endif
 
 void pm_policy_state_lock_get(enum pm_state state, uint8_t substate_id)
 {
 #if DT_HAS_COMPAT_STATUS_OKAY(zephyr_power_state)
-	for (size_t i = 0; i < ARRAY_SIZE(substate_lock_t); i++) {
-		if (substate_lock_t[i].state == state &&
-		   (substate_lock_t[i].substate_id == substate_id ||
-		    substate_id == PM_ALL_SUBSTATES)) {
-			atomic_inc(&substate_lock_t[i].lock);
+	for (size_t i = 0; i < ARRAY_SIZE(substates); i++) {
+		if (substates[i].state == state &&
+		   (substates[i].substate_id == substate_id || substate_id == PM_ALL_SUBSTATES)) {
+			k_spinlock_key_t key = k_spin_lock(&lock);
+
+			if (lock_cnt[i] == 0) {
+				unlock_mask &= ~BIT(i);
+			}
+			lock_cnt[i]++;
+			k_spin_unlock(&lock, key);
 		}
 	}
 #endif
@@ -56,15 +68,17 @@ void pm_policy_state_lock_get(enum pm_state state, uint8_t substate_id)
 void pm_policy_state_lock_put(enum pm_state state, uint8_t substate_id)
 {
 #if DT_HAS_COMPAT_STATUS_OKAY(zephyr_power_state)
-	for (size_t i = 0; i < ARRAY_SIZE(substate_lock_t); i++) {
-		if (substate_lock_t[i].state == state &&
-		   (substate_lock_t[i].substate_id == substate_id ||
-		    substate_id == PM_ALL_SUBSTATES)) {
-			atomic_t cnt = atomic_dec(&substate_lock_t[i].lock);
-
-			ARG_UNUSED(cnt);
+	for (size_t i = 0; i < ARRAY_SIZE(substates); i++) {
+		if (substates[i].state == state &&
+		   (substates[i].substate_id == substate_id || substate_id == PM_ALL_SUBSTATES)) {
+			k_spinlock_key_t key = k_spin_lock(&lock);
 
-			__ASSERT(cnt >= 1, "Unbalanced state lock get/put");
+			__ASSERT(lock_cnt[i] > 0, "Unbalanced state lock get/put");
+			lock_cnt[i]--;
+			if (lock_cnt[i] == 0) {
+				unlock_mask |= BIT(i);
+			}
+			k_spin_unlock(&lock, key);
 		}
 	}
 #endif
@@ -73,14 +87,64 @@ void pm_policy_state_lock_put(enum pm_state state, uint8_t substate_id)
 bool pm_policy_state_lock_is_active(enum pm_state state, uint8_t substate_id)
 {
 #if DT_HAS_COMPAT_STATUS_OKAY(zephyr_power_state)
-	for (size_t i = 0; i < ARRAY_SIZE(substate_lock_t); i++) {
-		if (substate_lock_t[i].state == state &&
-		   (substate_lock_t[i].substate_id == substate_id ||
-		    substate_id == PM_ALL_SUBSTATES)) {
-			return (atomic_get(&substate_lock_t[i].lock) != 0);
+	for (size_t i = 0; i < ARRAY_SIZE(substates); i++) {
+		if (substates[i].state == state &&
+		   (substates[i].substate_id == substate_id || substate_id == PM_ALL_SUBSTATES)) {
+			return atomic_get(&lock_cnt[i]) != 0;
 		}
 	}
 #endif
 
 	return false;
 }
+
+bool pm_policy_state_is_available(enum pm_state state, uint8_t substate_id)
+{
+#if DT_HAS_COMPAT_STATUS_OKAY(zephyr_power_state)
+	for (size_t i = 0; i < ARRAY_SIZE(substates); i++) {
+		if (substates[i].state == state &&
+		   (substates[i].substate_id == substate_id || substate_id == PM_ALL_SUBSTATES)) {
+			return (atomic_get(&lock_cnt[i]) == 0) &&
+			       (atomic_get(&latency_mask) & BIT(i));
+		}
+	}
+#endif
+
+	return false;
+}
+
+bool pm_policy_state_any_active(void)
+{
+#if DT_HAS_COMPAT_STATUS_OKAY(zephyr_power_state)
+	/* Check if there is any power state that is not locked and not disabled due
+	 * to latency requirements.
+	 */
+	return atomic_get(&unlock_mask) & atomic_get(&latency_mask);
+#endif
+	return true;
+}
+
+#if DT_HAS_COMPAT_STATUS_OKAY(zephyr_power_state)
+/* Callback is called whenever latency requirement changes. It is called under lock. */
+static void pm_policy_latency_update_locked(int32_t max_latency_us)
+{
+	for (size_t i = 0; i < ARRAY_SIZE(substates); i++) {
+		if (substates[i].exit_latency_us >= max_latency_us) {
+			latency_mask &= ~BIT(i);
+		} else {
+			latency_mask |= BIT(i);
+		}
+	}
+}
+
+static int pm_policy_latency_init(void)
+{
+	static struct pm_policy_latency_subscription sub;
+
+	pm_policy_latency_changed_subscribe(&sub, pm_policy_latency_update_locked);
+
+	return 0;
+}
+
+SYS_INIT(pm_policy_latency_init, PRE_KERNEL_1, 0);
+#endif
diff --git a/subsys/pm/state.c b/subsys/pm/state.c
index 297d28a3768..3cf2888d339 100644
--- a/subsys/pm/state.c
+++ b/subsys/pm/state.c
@@ -66,3 +66,18 @@ uint8_t pm_state_cpu_get_all(uint8_t cpu, const struct pm_state_info **states)
 
 	return states_per_cpu[cpu];
 }
+
+const struct pm_state_info *pm_state_get(uint8_t cpu, enum pm_state state, uint8_t substate_id)
+{
+	__ASSERT_NO_MSG(cpu < ARRAY_SIZE(cpus_states));
+	const struct pm_state_info *states = cpus_states[cpu];
+	uint8_t cnt = states_per_cpu[cpu];
+
+	for (uint8_t i = 0; i < cnt; i++) {
+		if ((states[i].state == state) && (states[i].substate_id == substate_id)) {
+			return &states[i];
+		}
+	}
+
+	return NULL;
+}
diff --git a/subsys/pmci/CMakeLists.txt b/subsys/pmci/CMakeLists.txt
new file mode 100644
index 00000000000..931aeaada5b
--- /dev/null
+++ b/subsys/pmci/CMakeLists.txt
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+add_subdirectory_ifdef(CONFIG_MCTP mctp)
diff --git a/subsys/pmci/Kconfig b/subsys/pmci/Kconfig
new file mode 100644
index 00000000000..917a084a52f
--- /dev/null
+++ b/subsys/pmci/Kconfig
@@ -0,0 +1,14 @@
+# PMCI configuration options
+
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+menu "Platform Management Communication Infrastruction (PMCI)"
+
+# zephyr-keep-sorted-start
+
+source "subsys/pmci/mctp/Kconfig"
+
+# zephyr-keep-sorted-stop
+
+endmenu
diff --git a/subsys/pmci/mctp/CMakeLists.txt b/subsys/pmci/mctp/CMakeLists.txt
new file mode 100644
index 00000000000..23858ad2882
--- /dev/null
+++ b/subsys/pmci/mctp/CMakeLists.txt
@@ -0,0 +1,2 @@
+zephyr_library()
+zephyr_library_sources_ifdef(CONFIG_MCTP_UART mctp_uart.c)
diff --git a/subsys/pmci/mctp/Kconfig b/subsys/pmci/mctp/Kconfig
new file mode 100644
index 00000000000..0952c3b1f7d
--- /dev/null
+++ b/subsys/pmci/mctp/Kconfig
@@ -0,0 +1,23 @@
+# Copyright (c) 2024 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig MCTP
+	bool "Management Component Transport Protocol [EXPERIMENTAL]"
+	select EXPERIMENTAL
+	help
+	  Enable the MCTP Subsystem and Module Usage
+
+if MCTP
+
+config MCTP_UART
+	bool "MCTP UART Binding"
+	depends on UART_ASYNC_API
+	help
+	  Build the MCTP UART binding to use MCTP over Zephyr's async UART
+	  interface.
+
+module = MCTP
+module-str = MCTP
+source "subsys/logging/Kconfig.template.log_config"
+
+endif
diff --git a/subsys/pmci/mctp/mctp_uart.c b/subsys/pmci/mctp/mctp_uart.c
new file mode 100644
index 00000000000..b77a4698508
--- /dev/null
+++ b/subsys/pmci/mctp/mctp_uart.c
@@ -0,0 +1,325 @@
+/*
+ * Copyright (c) 2024 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#include <zephyr/sys/__assert.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/uart.h>
+#include <zephyr/pmci/mctp/mctp_uart.h>
+#include <crc-16-ccitt.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(mctp_uart, CONFIG_MCTP_LOG_LEVEL);
+
+#define MCTP_UART_REVISION     0x01
+#define MCTP_UART_FRAMING_FLAG 0x7e
+#define MCTP_UART_ESCAPE       0x7d
+
+const char *UART_EVENT_STRING[] = {
+	"TX Done",     "TX Aborted", "RX Ready", "RX Buffer Request", "RX Buffer Released",
+	"RX Disabled", "RX Stopped",
+};
+
+const char *MCTP_STATE_STRING[] = {
+	"Wait: Sync Start", "Wait: Revision", "Wait: Len",  "Data",
+	"Data: Escaped",    "Wait: FCS1",     "Wait: FCS2", "Wait: Sync End",
+};
+
+struct mctp_serial_header {
+	uint8_t flag;
+	uint8_t revision;
+	uint8_t len;
+};
+
+struct mctp_serial_trailer {
+	uint8_t fcs_msb;
+	uint8_t fcs_lsb;
+	uint8_t flag;
+};
+
+static inline struct mctp_binding_uart *binding_to_uart(struct mctp_binding *b)
+{
+	return (struct mctp_binding_uart *)b;
+}
+
+static void mctp_uart_finish_pkt(struct mctp_binding_uart *uart, bool valid)
+{
+	struct mctp_pktbuf *pkt = uart->rx_pkt;
+
+
+	if (valid) {
+		__ASSERT_NO_MSG(pkt);
+
+		mctp_bus_rx(&uart->binding, pkt);
+	}
+
+	uart->rx_pkt = NULL;
+}
+
+static void mctp_uart_start_pkt(struct mctp_binding_uart *uart, uint8_t len)
+{
+	__ASSERT_NO_MSG(uart->rx_pkt == NULL);
+
+	uart->rx_pkt = mctp_pktbuf_alloc(&uart->binding, len);
+
+	__ASSERT_NO_MSG(uart->rx_pkt);
+}
+
+static size_t mctp_uart_pkt_escape(struct mctp_pktbuf *pkt, uint8_t *buf)
+{
+	uint8_t total_len;
+	uint8_t *p;
+	int i, j;
+
+	total_len = pkt->end - pkt->mctp_hdr_off;
+
+	p = (void *)mctp_pktbuf_hdr(pkt);
+
+	for (i = 0, j = 0; i < total_len; i++, j++) {
+		uint8_t c = p[i];
+
+		if (c == MCTP_UART_FRAMING_FLAG || c == MCTP_UART_ESCAPE) {
+			if (buf) {
+				buf[j] = MCTP_UART_ESCAPE;
+			}
+			j++;
+			c ^= 0x20;
+		}
+		if (buf) {
+			buf[j] = c;
+		}
+	}
+
+	return j;
+}
+
+/*
+ * Each byte coming from the uart is run through this state machine which
+ * does the MCTP packet decoding.
+ *
+ * The actual packet and buffer being read into is owned by the binding!
+ */
+static void mctp_uart_consume(struct mctp_binding_uart *uart, uint8_t c)
+{
+	struct mctp_pktbuf *pkt = uart->rx_pkt;
+	bool valid = false;
+
+	LOG_DBG("uart consume start state: %d:%s, char 0x%02x", uart->rx_state,
+		MCTP_STATE_STRING[uart->rx_state], c);
+
+	__ASSERT_NO_MSG(!pkt == (uart->rx_state == STATE_WAIT_SYNC_START ||
+				 uart->rx_state == STATE_WAIT_REVISION ||
+				 uart->rx_state == STATE_WAIT_LEN));
+
+	switch (uart->rx_state) {
+	case STATE_WAIT_SYNC_START:
+		if (c != MCTP_UART_FRAMING_FLAG) {
+			LOG_DBG("lost sync, dropping packet");
+			if (pkt) {
+				mctp_uart_finish_pkt(uart, false);
+			}
+		} else {
+			uart->rx_state = STATE_WAIT_REVISION;
+		}
+		break;
+	case STATE_WAIT_REVISION:
+		if (c == MCTP_UART_REVISION) {
+			uart->rx_state = STATE_WAIT_LEN;
+			uart->rx_fcs_calc = crc_16_ccitt_byte(FCS_INIT_16, c);
+		} else if (c == MCTP_UART_FRAMING_FLAG) {
+			/* Handle the case where there are bytes dropped in request,
+			 * and the state machine is out of sync. The failed request's
+			 * trailing footer i.e. 0x7e would be interpreted as next
+			 * request's framing footer. So if we are in STATE_WAIT_REVISION
+			 * and receive 0x7e byte, then continue to stay in
+			 * STATE_WAIT_REVISION
+			 */
+			LOG_DBG("Received serial framing flag 0x%02x while waiting"
+				" for serial revision 0x%02x.",
+				c, MCTP_UART_REVISION);
+		} else {
+			LOG_DBG("invalid revision 0x%02x", c);
+			uart->rx_state = STATE_WAIT_SYNC_START;
+		}
+		break;
+	case STATE_WAIT_LEN:
+		if (c > uart->binding.pkt_size || c < sizeof(struct mctp_hdr)) {
+			LOG_DBG("invalid size %d", c);
+			uart->rx_state = STATE_WAIT_SYNC_START;
+		} else {
+			mctp_uart_start_pkt(uart, 0);
+			pkt = uart->rx_pkt;
+			uart->rx_exp_len = c;
+			uart->rx_state = STATE_DATA;
+			uart->rx_fcs_calc = crc_16_ccitt_byte(uart->rx_fcs_calc, c);
+		}
+		break;
+	case STATE_DATA:
+		if (c == MCTP_UART_ESCAPE) {
+			uart->rx_state = STATE_DATA_ESCAPED;
+		} else {
+			mctp_pktbuf_push(pkt, &c, 1);
+			uart->rx_fcs_calc = crc_16_ccitt_byte(uart->rx_fcs_calc, c);
+			if (pkt->end - pkt->mctp_hdr_off == uart->rx_exp_len) {
+				uart->rx_state = STATE_WAIT_FCS1;
+			}
+		}
+		break;
+	case STATE_DATA_ESCAPED:
+		c ^= 0x20;
+		mctp_pktbuf_push(pkt, &c, 1);
+		uart->rx_fcs_calc = crc_16_ccitt_byte(uart->rx_fcs_calc, c);
+		if (pkt->end - pkt->mctp_hdr_off == uart->rx_exp_len) {
+			uart->rx_state = STATE_WAIT_FCS1;
+		} else {
+			uart->rx_state = STATE_DATA;
+		}
+		break;
+
+	case STATE_WAIT_FCS1:
+		uart->rx_fcs = c << 8;
+		uart->rx_state = STATE_WAIT_FCS2;
+		break;
+	case STATE_WAIT_FCS2:
+		uart->rx_fcs |= c;
+		uart->rx_state = STATE_WAIT_SYNC_END;
+		break;
+	case STATE_WAIT_SYNC_END:
+		if (uart->rx_fcs == uart->rx_fcs_calc) {
+			if (c == MCTP_UART_FRAMING_FLAG) {
+				valid = true;
+			} else {
+				valid = false;
+				LOG_DBG("missing end frame marker");
+			}
+		} else {
+			valid = false;
+			LOG_DBG("invalid fcs : 0x%04x, expect 0x%04x", uart->rx_fcs,
+				uart->rx_fcs_calc);
+		}
+
+		mctp_uart_finish_pkt(uart, valid);
+		uart->rx_state = STATE_WAIT_SYNC_START;
+		break;
+	}
+
+	LOG_DBG("uart consume end state: %d:%s, char 0x%02x", uart->rx_state,
+		MCTP_STATE_STRING[uart->rx_state], c);
+}
+
+static void mctp_uart_callback(const struct device *dev, struct uart_event *evt, void *userdata)
+{
+	struct mctp_binding_uart *binding = userdata;
+
+	switch (evt->type) {
+	case UART_TX_DONE:
+		binding->tx_res = 0;
+		break;
+	case UART_TX_ABORTED:
+		binding->tx_res = -EIO;
+		break;
+	case UART_RX_RDY:
+		/* buffer being read into is ready */
+		binding->rx_res = evt->data.rx.len;
+		/* parse the buffer */
+		for (size_t i = 0; i < evt->data.rx.len; i++) {
+			mctp_uart_consume(binding, evt->data.rx.buf[evt->data.rx.offset + i]);
+		}
+		break;
+	case UART_RX_BUF_REQUEST:
+		for (int i = 0; i < sizeof(binding->rx_buf_used); i++) {
+			if (!binding->rx_buf_used[i]) {
+				binding->rx_buf_used[i] = true;
+				uart_rx_buf_rsp(dev, binding->rx_buf[i],
+						sizeof(binding->rx_buf[i]));
+				break;
+			}
+		}
+		break;
+	case UART_RX_BUF_RELEASED:
+		for (int i = 0; i < sizeof(binding->rx_buf_used); i++) {
+			if (binding->rx_buf[i] == evt->data.rx_buf.buf) {
+				binding->rx_buf_used[i] = false;
+				break;
+			}
+		}
+		break;
+	case UART_RX_STOPPED:
+		break;
+	case UART_RX_DISABLED:
+		break;
+	}
+}
+
+void mctp_uart_start_rx(struct mctp_binding_uart *uart)
+{
+	int res = uart_callback_set(uart->dev, mctp_uart_callback, uart);
+
+	__ASSERT_NO_MSG(res == 0);
+	uart->rx_buf_used[0] = true;
+	res = uart_rx_enable(uart->dev, uart->rx_buf[0], sizeof(uart->rx_buf[0]), 1000);
+	__ASSERT_NO_MSG(res == 0);
+}
+
+int mctp_uart_tx(struct mctp_binding *b, struct mctp_pktbuf *pkt)
+{
+	struct mctp_binding_uart *uart = binding_to_uart(b);
+	struct mctp_serial_header *hdr;
+	struct mctp_serial_trailer *tlr;
+	uint8_t *buf;
+	size_t len;
+	uint16_t fcs;
+
+	LOG_DBG("uart tx pkt %p", pkt);
+
+	/* the length field in the header excludes serial framing
+	 * and escape sequences
+	 */
+	len = mctp_pktbuf_size(pkt);
+
+	hdr = (void *)uart->tx_buf;
+	hdr->flag = MCTP_UART_FRAMING_FLAG;
+	hdr->revision = MCTP_UART_REVISION;
+	hdr->len = len;
+
+	/* Calculate fcs */
+	fcs = crc_16_ccitt(FCS_INIT_16, (const uint8_t *)hdr + 1, 2);
+	fcs = crc_16_ccitt(fcs, (const uint8_t *)mctp_pktbuf_hdr(pkt), len);
+	LOG_DBG("calculated crc %d", fcs);
+
+	buf = (void *)(hdr + 1);
+
+	len = mctp_uart_pkt_escape(pkt, NULL);
+	if (len + sizeof(*hdr) + sizeof(*tlr) > sizeof(uart->tx_buf)) {
+		return -EMSGSIZE;
+	}
+
+	mctp_uart_pkt_escape(pkt, buf);
+
+	buf += len;
+
+	tlr = (void *)buf;
+	tlr->flag = MCTP_UART_FRAMING_FLAG;
+	tlr->fcs_msb = fcs >> 8;
+	tlr->fcs_lsb = fcs & 0xff;
+
+	len += sizeof(*hdr) + sizeof(*tlr);
+
+	int res = uart_tx(uart->dev, (const uint8_t *)uart->tx_buf, len, SYS_FOREVER_US);
+
+	if (res != 0) {
+		LOG_ERR("Failed sending data, %d", res);
+		return res;
+	}
+
+	return uart->tx_res;
+}
+
+int mctp_uart_start(struct mctp_binding *binding)
+{
+	mctp_binding_set_tx_enabled(binding, true);
+	return 0;
+}
diff --git a/subsys/portability/cmsis_rtos_v2/Kconfig b/subsys/portability/cmsis_rtos_v2/Kconfig
index 07012048036..968daeae55b 100644
--- a/subsys/portability/cmsis_rtos_v2/Kconfig
+++ b/subsys/portability/cmsis_rtos_v2/Kconfig
@@ -16,23 +16,20 @@ config CMSIS_RTOS_V2
 
 if CMSIS_RTOS_V2
 config CMSIS_V2_THREAD_MAX_COUNT
-	int "Maximum thread count in CMSIS RTOS V2 application"
+	int "Maximum thread count in CMSIS RTOS V2 application with dynamic control blocks"
 	default 15
 	range 0 $(UINT8_MAX)
 	help
-	  Mention max number of threads in CMSIS RTOS V2 compliant application.
-	  There's a limitation on the number of threads due to memory
-	  related constraints.
+	  Max number of threads in CMSIS RTOS V2 application that can be created with
+	  dynamically allocated control block.
 
 config CMSIS_V2_THREAD_DYNAMIC_MAX_COUNT
-	int "Maximum dynamic thread count in CMSIS RTOS V2 application"
+	int "Maximum thread count in CMSIS RTOS V2 application with dynamic stack"
 	default 0
 	range 0 $(UINT8_MAX)
 	help
-	  Mention max number of dynamic threads in CMSIS RTOS V2 compliant
-	  application. There's a limitation on the number of threads due to memory
-	  related constraints. Dynamic threads are a subset of all other CMSIS
-	  threads i.e. they also count towards that maximum too.
+	  Max number of threads in CMSIS RTOS V2 application that can be created with
+	  dynamically allocated stack.
 
 config CMSIS_V2_THREAD_MAX_STACK_SIZE
 	int "Max stack size threads can be allocated in CMSIS RTOS V2 application"
@@ -49,32 +46,36 @@ config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE
 	  Mention dynamic stack size threads are allocated in CMSIS RTOS V2 application.
 
 config CMSIS_V2_TIMER_MAX_COUNT
-	int "Maximum timer count in CMSIS RTOS V2 application"
+	int "Maximum dynamically-allocated timers in CMSIS RTOS V2 application"
 	default 5
 	range 0 $(UINT8_MAX)
 	help
-	  Mention maximum number of timers in CMSIS RTOS V2 compliant application.
+	  Mention maximum number of timers in CMSIS RTOS V2 compliant application that can
+	  be created with dynamically allocated control block.
 
 config CMSIS_V2_MUTEX_MAX_COUNT
-	int "Maximum mutex count in CMSIS RTOS V2 application"
+	int "Maximum dynamically-allocated mutexes in CMSIS RTOS V2 application"
 	default 5
 	range 0 $(UINT8_MAX)
 	help
-	  Mention max number of mutexes in CMSIS RTOS V2 compliant application.
+	  Mention max number of mutexes in CMSIS RTOS V2 compliant application that can
+	  be created with dynamically allocated control block.
 
 config CMSIS_V2_SEMAPHORE_MAX_COUNT
-	int "Maximum semaphore count in CMSIS RTOS V2 application"
+	int "Maximum dynamically-allocated semaphores in CMSIS RTOS V2 application"
 	default 5
 	range 0 $(UINT8_MAX)
 	help
-	  Mention max number of semaphores in CMSIS RTOS V2 compliant application.
+	  Mention max number of semaphores in CMSIS RTOS V2 compliant application that can
+	  be created with dynamically allocated control block.
 
 config CMSIS_V2_MEM_SLAB_MAX_COUNT
-	int "Maximum mem slab count in CMSIS RTOS V2 application"
+	int "Maximum dynamically-allocated mempools in CMSIS RTOS V2 application"
 	default 5
 	range 0 $(UINT8_MAX)
 	help
-	  Mention maximum number of memory slabs in CMSIS RTOS V2 compliant application.
+	  Mention maximum number of memory slabs in CMSIS RTOS V2 compliant application that can
+	  be created with dynamically allocated control block.
 
 config CMSIS_V2_MEM_SLAB_MAX_DYNAMIC_SIZE
 	int "Maximum dynamic mem slab/pool size in CMSIS RTOS V2 application"
@@ -83,11 +84,12 @@ config CMSIS_V2_MEM_SLAB_MAX_DYNAMIC_SIZE
 	  Mention maximum dynamic size of memory slabs/pools in CMSIS RTOS V2 compliant application.
 
 config CMSIS_V2_MSGQ_MAX_COUNT
-	int "Maximum message queue count in CMSIS RTOS V2 application"
+	int "Maximum dynamically-allocated message queues in CMSIS RTOS V2 application"
 	default 5
 	range 0 $(UINT8_MAX)
 	help
-	  Mention maximum number of message queues in CMSIS RTOS V2 compliant application.
+	  Mention maximum number of message queues in CMSIS RTOS V2 compliant application that can
+	  be created with dynamically allocated control block.
 
 config CMSIS_V2_MSGQ_MAX_DYNAMIC_SIZE
 	int "Maximum dynamic message queue size in CMSIS RTOS V2 application"
@@ -96,9 +98,10 @@ config CMSIS_V2_MSGQ_MAX_DYNAMIC_SIZE
 	  Mention maximum dynamic size of message queues in CMSIS RTOS V2 compliant application.
 
 config CMSIS_V2_EVT_FLAGS_MAX_COUNT
-	int "Maximum event flags count in CMSIS RTOS V2 application"
+	int "Maximum dynamically-allocated event flags count in CMSIS RTOS V2 application"
 	default 5
 	range 0 $(UINT8_MAX)
 	help
-	  Mention maximum number of event flags in CMSIS RTOS V2 compliant application.
+	  Mention maximum number of event flags in CMSIS RTOS V2 compliant application that can
+	  be created with dynamically allocated control block.
 endif
diff --git a/subsys/portability/cmsis_rtos_v2/event_flags.c b/subsys/portability/cmsis_rtos_v2/event_flags.c
index cd91c69a4a2..5e2daeb06af 100644
--- a/subsys/portability/cmsis_rtos_v2/event_flags.c
+++ b/subsys/portability/cmsis_rtos_v2/event_flags.c
@@ -5,10 +5,10 @@
  */
 
 #include <zephyr/kernel.h>
+#include <zephyr/portability/cmsis_types.h>
 #include <string.h>
-#include "wrapper.h"
 
-K_MEM_SLAB_DEFINE(cv2_event_flags_slab, sizeof(struct cv2_event_flags),
+K_MEM_SLAB_DEFINE(cmsis_rtos_event_cb_slab, sizeof(struct cmsis_rtos_event_cb),
 		  CONFIG_CMSIS_V2_EVT_FLAGS_MAX_COUNT, 4);
 
 static const osEventFlagsAttr_t init_event_flags_attrs = {
@@ -18,14 +18,14 @@ static const osEventFlagsAttr_t init_event_flags_attrs = {
 	.cb_size = 0,
 };
 
-#define DONT_CARE        (0)
+#define DONT_CARE (0)
 
 /**
  * @brief Create and Initialize an Event Flags object.
  */
 osEventFlagsId_t osEventFlagsNew(const osEventFlagsAttr_t *attr)
 {
-	struct cv2_event_flags *events;
+	struct cmsis_rtos_event_cb *events;
 
 	if (k_is_in_isr()) {
 		return NULL;
@@ -35,24 +35,22 @@ osEventFlagsId_t osEventFlagsNew(const osEventFlagsAttr_t *attr)
 		attr = &init_event_flags_attrs;
 	}
 
-	if (k_mem_slab_alloc(&cv2_event_flags_slab, (void **)&events, K_MSEC(100))
-		== 0) {
-		memset(events, 0, sizeof(struct cv2_event_flags));
-	} else {
+	if (attr->cb_mem != NULL) {
+		__ASSERT(attr->cb_size == sizeof(struct cmsis_rtos_event_cb), "Invalid cb_size\n");
+		events = (struct cmsis_rtos_event_cb *)attr->cb_mem;
+	} else if (k_mem_slab_alloc(&cmsis_rtos_event_cb_slab, (void **)&events, K_MSEC(100)) !=
+		   0) {
 		return NULL;
 	}
+	memset(events, 0, sizeof(struct cmsis_rtos_event_cb));
+	events->is_cb_dynamic_allocation = attr->cb_mem == NULL;
 
 	k_poll_signal_init(&events->poll_signal);
-	k_poll_event_init(&events->poll_event, K_POLL_TYPE_SIGNAL,
-			  K_POLL_MODE_NOTIFY_ONLY, &events->poll_signal);
+	k_poll_event_init(&events->poll_event, K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY,
+			  &events->poll_signal);
 	events->signal_results = 0U;
 
-	if (attr->name == NULL) {
-		strncpy(events->name, init_event_flags_attrs.name,
-			sizeof(events->name) - 1);
-	} else {
-		strncpy(events->name, attr->name, sizeof(events->name) - 1);
-	}
+	events->name = (attr->name == NULL) ? init_event_flags_attrs.name : attr->name;
 
 	return (osEventFlagsId_t)events;
 }
@@ -62,7 +60,7 @@ osEventFlagsId_t osEventFlagsNew(const osEventFlagsAttr_t *attr)
  */
 uint32_t osEventFlagsSet(osEventFlagsId_t ef_id, uint32_t flags)
 {
-	struct cv2_event_flags *events = (struct cv2_event_flags *)ef_id;
+	struct cmsis_rtos_event_cb *events = (struct cmsis_rtos_event_cb *)ef_id;
 	unsigned int key;
 
 	if ((ef_id == NULL) || (flags & osFlagsError)) {
@@ -83,7 +81,7 @@ uint32_t osEventFlagsSet(osEventFlagsId_t ef_id, uint32_t flags)
  */
 uint32_t osEventFlagsClear(osEventFlagsId_t ef_id, uint32_t flags)
 {
-	struct cv2_event_flags *events = (struct cv2_event_flags *)ef_id;
+	struct cmsis_rtos_event_cb *events = (struct cmsis_rtos_event_cb *)ef_id;
 	unsigned int key;
 	uint32_t sig;
 
@@ -102,10 +100,10 @@ uint32_t osEventFlagsClear(osEventFlagsId_t ef_id, uint32_t flags)
 /**
  * @brief Wait for one or more Event Flags to become signaled.
  */
-uint32_t osEventFlagsWait(osEventFlagsId_t ef_id, uint32_t flags,
-			  uint32_t options, uint32_t timeout)
+uint32_t osEventFlagsWait(osEventFlagsId_t ef_id, uint32_t flags, uint32_t options,
+			  uint32_t timeout)
 {
-	struct cv2_event_flags *events = (struct cv2_event_flags *)ef_id;
+	struct cmsis_rtos_event_cb *events = (struct cmsis_rtos_event_cb *)ef_id;
 	int retval, key;
 	uint32_t sig;
 	k_timeout_t poll_timeout;
@@ -173,12 +171,11 @@ uint32_t osEventFlagsWait(osEventFlagsId_t ef_id, uint32_t flags,
 			 * adjust the timeout value accordingly based on
 			 * the time that has already elapsed.
 			 */
-			ticks_elapsed =
-				(uint64_t)k_uptime_ticks() - time_stamp_start;
+			ticks_elapsed = (uint64_t)k_uptime_ticks() - time_stamp_start;
 
 			if (ticks_elapsed < (uint64_t)timeout) {
-				poll_timeout = Z_TIMEOUT_TICKS((k_ticks_t)(
-					timeout - (uint32_t)ticks_elapsed));
+				poll_timeout = Z_TIMEOUT_TICKS(
+					(k_ticks_t)(timeout - (uint32_t)ticks_elapsed));
 			} else {
 				return osFlagsErrorTimeout;
 			}
@@ -198,8 +195,7 @@ uint32_t osEventFlagsWait(osEventFlagsId_t ef_id, uint32_t flags,
 		 */
 		__ASSERT(events->poll_event.state == K_POLL_STATE_SIGNALED,
 			 "event state not signalled!");
-		__ASSERT(events->poll_event.signal->signaled == 1U,
-			 "event signaled is not 1");
+		__ASSERT(events->poll_event.signal->signaled == 1U, "event signaled is not 1");
 	}
 
 	return sig;
@@ -207,16 +203,16 @@ uint32_t osEventFlagsWait(osEventFlagsId_t ef_id, uint32_t flags,
 
 /**
  * @brief Get name of an Event Flags object.
+ * This function may be called from Interrupt Service Routines.
  */
 const char *osEventFlagsGetName(osEventFlagsId_t ef_id)
 {
-	struct cv2_event_flags *events = (struct cv2_event_flags *)ef_id;
+	struct cmsis_rtos_event_cb *events = (struct cmsis_rtos_event_cb *)ef_id;
 
-	if (!k_is_in_isr() && (ef_id != NULL)) {
-		return events->name;
-	} else {
+	if (events == NULL) {
 		return NULL;
 	}
+	return events->name;
 }
 
 /**
@@ -224,7 +220,7 @@ const char *osEventFlagsGetName(osEventFlagsId_t ef_id)
  */
 uint32_t osEventFlagsGet(osEventFlagsId_t ef_id)
 {
-	struct cv2_event_flags *events = (struct cv2_event_flags *)ef_id;
+	struct cmsis_rtos_event_cb *events = (struct cmsis_rtos_event_cb *)ef_id;
 
 	if (ef_id == NULL) {
 		return 0;
@@ -238,7 +234,7 @@ uint32_t osEventFlagsGet(osEventFlagsId_t ef_id)
  */
 osStatus_t osEventFlagsDelete(osEventFlagsId_t ef_id)
 {
-	struct cv2_event_flags *events = (struct cv2_event_flags *)ef_id;
+	struct cmsis_rtos_event_cb *events = (struct cmsis_rtos_event_cb *)ef_id;
 
 	if (ef_id == NULL) {
 		return osErrorResource;
@@ -251,8 +247,8 @@ osStatus_t osEventFlagsDelete(osEventFlagsId_t ef_id)
 	/* The status code "osErrorParameter" (the value of the parameter
 	 * ef_id is incorrect) is not supported in Zephyr.
 	 */
-
-	k_mem_slab_free(&cv2_event_flags_slab, (void *)events);
-
+	if (events->is_cb_dynamic_allocation) {
+		k_mem_slab_free(&cmsis_rtos_event_cb_slab, (void *)events);
+	}
 	return osOK;
 }
diff --git a/subsys/portability/cmsis_rtos_v2/kernel.c b/subsys/portability/cmsis_rtos_v2/kernel.c
index 519be96023d..9f19e89e69f 100644
--- a/subsys/portability/cmsis_rtos_v2/kernel.c
+++ b/subsys/portability/cmsis_rtos_v2/kernel.c
@@ -7,7 +7,7 @@
 #include <stdio.h>
 #include <string.h>
 #include <zephyr/kernel.h>
-#include <cmsis_os2.h>
+#include <zephyr/portability/cmsis_os2.h>
 
 extern uint32_t sys_clock_tick_get_32(void);
 
@@ -24,8 +24,7 @@ osStatus_t osKernelGetInfo(osVersion_t *version, char *id_buf, uint32_t id_size)
 	}
 
 	if ((id_buf != NULL) && (version != NULL)) {
-		snprintf(id_buf, id_size,
-			 "Zephyr V%2"PRIu32".%2"PRIu32".%2"PRIu32,
+		snprintf(id_buf, id_size, "Zephyr V%2" PRIu32 ".%2" PRIu32 ".%2" PRIu32,
 			 SYS_KERNEL_VER_MAJOR(version->kernel),
 			 SYS_KERNEL_VER_MINOR(version->kernel),
 			 SYS_KERNEL_VER_PATCHLEVEL(version->kernel));
@@ -78,9 +77,9 @@ int32_t osKernelRestoreLock(int32_t lock)
 	}
 
 	if (lock < 0) {
-		return 1;       /* locked */
+		return 1; /* locked */
 	} else {
-		return 0;       /* not locked */
+		return 0; /* not locked */
 	}
 }
 
diff --git a/subsys/portability/cmsis_rtos_v2/mempool.c b/subsys/portability/cmsis_rtos_v2/mempool.c
index a5a08919753..002a6660e96 100644
--- a/subsys/portability/cmsis_rtos_v2/mempool.c
+++ b/subsys/portability/cmsis_rtos_v2/mempool.c
@@ -5,12 +5,13 @@
  */
 
 #include <zephyr/kernel.h>
+#include <zephyr/portability/cmsis_types.h>
 #include <string.h>
 #include "wrapper.h"
 
-#define TIME_OUT_TICKS  10
+#define TIME_OUT_TICKS 10
 
-K_MEM_SLAB_DEFINE(cv2_mem_slab, sizeof(struct cv2_mslab),
+K_MEM_SLAB_DEFINE(cv2_mem_slab, sizeof(struct cmsis_rtos_mempool_cb),
 		  CONFIG_CMSIS_V2_MEM_SLAB_MAX_COUNT, 4);
 
 static const osMemoryPoolAttr_t init_mslab_attrs = {
@@ -28,10 +29,9 @@ static const osMemoryPoolAttr_t init_mslab_attrs = {
 osMemoryPoolId_t osMemoryPoolNew(uint32_t block_count, uint32_t block_size,
 				 const osMemoryPoolAttr_t *attr)
 {
-	struct cv2_mslab *mslab;
+	struct cmsis_rtos_mempool_cb *mslab;
 
-	BUILD_ASSERT(K_HEAP_MEM_POOL_SIZE >=
-		     CONFIG_CMSIS_V2_MEM_SLAB_MAX_DYNAMIC_SIZE,
+	BUILD_ASSERT(K_HEAP_MEM_POOL_SIZE >= CONFIG_CMSIS_V2_MEM_SLAB_MAX_DYNAMIC_SIZE,
 		     "heap must be configured to be at least the max dynamic size");
 
 	if (k_is_in_isr()) {
@@ -46,20 +46,25 @@ osMemoryPoolId_t osMemoryPoolNew(uint32_t block_count, uint32_t block_size,
 		attr = &init_mslab_attrs;
 	}
 
-	if (k_mem_slab_alloc(&cv2_mem_slab, (void **)&mslab, K_MSEC(100)) == 0) {
-		(void)memset(mslab, 0, sizeof(struct cv2_mslab));
-	} else {
+	if (attr->cb_mem != NULL) {
+		__ASSERT(attr->cb_size == sizeof(struct cmsis_rtos_mempool_cb),
+			 "Invalid cb_size\n");
+		mslab = (struct cmsis_rtos_mempool_cb *)attr->cb_mem;
+	} else if (k_mem_slab_alloc(&cv2_mem_slab, (void **)&mslab, K_MSEC(100)) != 0) {
 		return NULL;
 	}
+	(void)memset(mslab, 0, sizeof(struct cmsis_rtos_mempool_cb));
+	mslab->is_cb_dynamic_allocation = attr->cb_mem == NULL;
 
 	if (attr->mp_mem == NULL) {
-		__ASSERT((block_count * block_size) <=
-			 CONFIG_CMSIS_V2_MEM_SLAB_MAX_DYNAMIC_SIZE,
+		__ASSERT((block_count * block_size) <= CONFIG_CMSIS_V2_MEM_SLAB_MAX_DYNAMIC_SIZE,
 			 "memory slab/pool size exceeds dynamic maximum");
 
 		mslab->pool = k_calloc(block_count, block_size);
 		if (mslab->pool == NULL) {
-			k_mem_slab_free(&cv2_mem_slab, (void *)mslab);
+			if (mslab->is_cb_dynamic_allocation) {
+				k_mem_slab_free(&cv2_mem_slab, (void *)mslab);
+			}
 			return NULL;
 		}
 		mslab->is_dynamic_allocation = TRUE;
@@ -69,21 +74,17 @@ osMemoryPoolId_t osMemoryPoolNew(uint32_t block_count, uint32_t block_size,
 	}
 
 	int rc = k_mem_slab_init(&mslab->z_mslab, mslab->pool, block_size, block_count);
-
 	if (rc != 0) {
-		k_mem_slab_free(&cv2_mem_slab, (void *)mslab);
+		if (mslab->is_cb_dynamic_allocation) {
+			k_mem_slab_free(&cv2_mem_slab, (void *)mslab);
+		}
 		if (attr->mp_mem == NULL) {
 			k_free(mslab->pool);
 		}
 		return NULL;
 	}
 
-	if (attr->name == NULL) {
-		strncpy(mslab->name, init_mslab_attrs.name,
-			sizeof(mslab->name) - 1);
-	} else {
-		strncpy(mslab->name, attr->name, sizeof(mslab->name) - 1);
-	}
+	mslab->name = (attr->name == NULL) ? init_mslab_attrs.name : attr->name;
 
 	return (osMemoryPoolId_t)mslab;
 }
@@ -93,7 +94,7 @@ osMemoryPoolId_t osMemoryPoolNew(uint32_t block_count, uint32_t block_size,
  */
 void *osMemoryPoolAlloc(osMemoryPoolId_t mp_id, uint32_t timeout)
 {
-	struct cv2_mslab *mslab = (struct cv2_mslab *)mp_id;
+	struct cmsis_rtos_mempool_cb *mslab = (struct cmsis_rtos_mempool_cb *)mp_id;
 	int retval;
 	void *ptr;
 
@@ -107,17 +108,14 @@ void *osMemoryPoolAlloc(osMemoryPoolId_t mp_id, uint32_t timeout)
 	}
 
 	if (timeout == 0U) {
-		retval = k_mem_slab_alloc(
-			(struct k_mem_slab *)(&mslab->z_mslab),
-			(void **)&ptr, K_NO_WAIT);
+		retval = k_mem_slab_alloc((struct k_mem_slab *)(&mslab->z_mslab), (void **)&ptr,
+					  K_NO_WAIT);
 	} else if (timeout == osWaitForever) {
-		retval = k_mem_slab_alloc(
-			(struct k_mem_slab *)(&mslab->z_mslab),
-			(void **)&ptr, K_FOREVER);
+		retval = k_mem_slab_alloc((struct k_mem_slab *)(&mslab->z_mslab), (void **)&ptr,
+					  K_FOREVER);
 	} else {
-		retval = k_mem_slab_alloc(
-			(struct k_mem_slab *)(&mslab->z_mslab),
-			(void **)&ptr, K_TICKS(timeout));
+		retval = k_mem_slab_alloc((struct k_mem_slab *)(&mslab->z_mslab), (void **)&ptr,
+					  K_TICKS(timeout));
 	}
 
 	if (retval == 0) {
@@ -132,7 +130,7 @@ void *osMemoryPoolAlloc(osMemoryPoolId_t mp_id, uint32_t timeout)
  */
 osStatus_t osMemoryPoolFree(osMemoryPoolId_t mp_id, void *block)
 {
-	struct cv2_mslab *mslab = (struct cv2_mslab *)mp_id;
+	struct cmsis_rtos_mempool_cb *mslab = (struct cmsis_rtos_mempool_cb *)mp_id;
 
 	if (mslab == NULL) {
 		return osErrorParameter;
@@ -142,24 +140,24 @@ osStatus_t osMemoryPoolFree(osMemoryPoolId_t mp_id, void *block)
 	 *       osErrorResource: the memory pool specified by parameter mp_id
 	 *       is in an invalid memory pool state.
 	 */
-
-	k_mem_slab_free((struct k_mem_slab *)(&mslab->z_mslab), (void *)block);
-
+	if (mslab->is_cb_dynamic_allocation) {
+		k_mem_slab_free((struct k_mem_slab *)(&mslab->z_mslab), (void *)block);
+	}
 	return osOK;
 }
 
 /**
  * @brief Get name of a Memory Pool object.
+ * This function may be called from Interrupt Service Routines.
  */
 const char *osMemoryPoolGetName(osMemoryPoolId_t mp_id)
 {
-	struct cv2_mslab *mslab = (struct cv2_mslab *)mp_id;
+	struct cmsis_rtos_mempool_cb *mslab = (struct cmsis_rtos_mempool_cb *)mp_id;
 
-	if (!k_is_in_isr() && (mslab != NULL)) {
-		return mslab->name;
-	} else {
+	if (mslab == NULL) {
 		return NULL;
 	}
+	return mslab->name;
 }
 
 /**
@@ -167,7 +165,7 @@ const char *osMemoryPoolGetName(osMemoryPoolId_t mp_id)
  */
 uint32_t osMemoryPoolGetCapacity(osMemoryPoolId_t mp_id)
 {
-	struct cv2_mslab *mslab = (struct cv2_mslab *)mp_id;
+	struct cmsis_rtos_mempool_cb *mslab = (struct cmsis_rtos_mempool_cb *)mp_id;
 
 	if (mslab == NULL) {
 		return 0;
@@ -181,7 +179,7 @@ uint32_t osMemoryPoolGetCapacity(osMemoryPoolId_t mp_id)
  */
 uint32_t osMemoryPoolGetBlockSize(osMemoryPoolId_t mp_id)
 {
-	struct cv2_mslab *mslab = (struct cv2_mslab *)mp_id;
+	struct cmsis_rtos_mempool_cb *mslab = (struct cmsis_rtos_mempool_cb *)mp_id;
 
 	if (mslab == NULL) {
 		return 0;
@@ -195,7 +193,7 @@ uint32_t osMemoryPoolGetBlockSize(osMemoryPoolId_t mp_id)
  */
 uint32_t osMemoryPoolGetCount(osMemoryPoolId_t mp_id)
 {
-	struct cv2_mslab *mslab = (struct cv2_mslab *)mp_id;
+	struct cmsis_rtos_mempool_cb *mslab = (struct cmsis_rtos_mempool_cb *)mp_id;
 
 	if (mslab == NULL) {
 		return 0;
@@ -209,7 +207,7 @@ uint32_t osMemoryPoolGetCount(osMemoryPoolId_t mp_id)
  */
 uint32_t osMemoryPoolGetSpace(osMemoryPoolId_t mp_id)
 {
-	struct cv2_mslab *mslab = (struct cv2_mslab *)mp_id;
+	struct cmsis_rtos_mempool_cb *mslab = (struct cmsis_rtos_mempool_cb *)mp_id;
 
 	if (mslab == NULL) {
 		return 0;
@@ -223,7 +221,7 @@ uint32_t osMemoryPoolGetSpace(osMemoryPoolId_t mp_id)
  */
 osStatus_t osMemoryPoolDelete(osMemoryPoolId_t mp_id)
 {
-	struct cv2_mslab *mslab = (struct cv2_mslab *)mp_id;
+	struct cmsis_rtos_mempool_cb *mslab = (struct cmsis_rtos_mempool_cb *)mp_id;
 
 	if (mslab == NULL) {
 		return osErrorParameter;
@@ -241,7 +239,8 @@ osStatus_t osMemoryPoolDelete(osMemoryPoolId_t mp_id)
 	if (mslab->is_dynamic_allocation) {
 		k_free(mslab->pool);
 	}
-	k_mem_slab_free(&cv2_mem_slab, (void *)mslab);
-
+	if (mslab->is_cb_dynamic_allocation) {
+		k_mem_slab_free(&cv2_mem_slab, (void *)mslab);
+	}
 	return osOK;
 }
diff --git a/subsys/portability/cmsis_rtos_v2/msgq.c b/subsys/portability/cmsis_rtos_v2/msgq.c
index af8c910c189..83c111bc651 100644
--- a/subsys/portability/cmsis_rtos_v2/msgq.c
+++ b/subsys/portability/cmsis_rtos_v2/msgq.c
@@ -5,10 +5,11 @@
  */
 
 #include <zephyr/kernel.h>
+#include <zephyr/portability/cmsis_types.h>
 #include <string.h>
 #include "wrapper.h"
 
-K_MEM_SLAB_DEFINE(cv2_msgq_slab, sizeof(struct cv2_msgq),
+K_MEM_SLAB_DEFINE(cmsis_rtos_msgq_cb_slab, sizeof(struct cmsis_rtos_msgq_cb),
 		  CONFIG_CMSIS_V2_MSGQ_MAX_COUNT, 4);
 
 static const osMessageQueueAttr_t init_msgq_attrs = {
@@ -26,10 +27,9 @@ static const osMessageQueueAttr_t init_msgq_attrs = {
 osMessageQueueId_t osMessageQueueNew(uint32_t msg_count, uint32_t msg_size,
 				     const osMessageQueueAttr_t *attr)
 {
-	struct cv2_msgq *msgq;
+	struct cmsis_rtos_msgq_cb *msgq;
 
-	BUILD_ASSERT(K_HEAP_MEM_POOL_SIZE >=
-		     CONFIG_CMSIS_V2_MSGQ_MAX_DYNAMIC_SIZE,
+	BUILD_ASSERT(K_HEAP_MEM_POOL_SIZE >= CONFIG_CMSIS_V2_MSGQ_MAX_DYNAMIC_SIZE,
 		     "heap must be configured to be at least the max dynamic size");
 
 	if (k_is_in_isr()) {
@@ -44,26 +44,32 @@ osMessageQueueId_t osMessageQueueNew(uint32_t msg_count, uint32_t msg_size,
 		attr = &init_msgq_attrs;
 	}
 
-	if (k_mem_slab_alloc(&cv2_msgq_slab, (void **)&msgq, K_MSEC(100)) == 0) {
-		(void)memset(msgq, 0, sizeof(struct cv2_msgq));
-	} else {
+	if (attr->cb_mem != NULL) {
+		__ASSERT(attr->cb_size == sizeof(struct cmsis_rtos_msgq_cb), "Invalid cb_size\n");
+		msgq = (struct cmsis_rtos_msgq_cb *)attr->cb_mem;
+	} else if (k_mem_slab_alloc(&cmsis_rtos_msgq_cb_slab, (void **)&msgq, K_MSEC(100)) != 0) {
 		return NULL;
 	}
+	(void)memset(msgq, 0, sizeof(struct cmsis_rtos_msgq_cb));
+	msgq->is_cb_dynamic_allocation = attr->cb_mem == NULL;
 
 	if (attr->mq_mem == NULL) {
-		__ASSERT((msg_count * msg_size) <=
-			 CONFIG_CMSIS_V2_MSGQ_MAX_DYNAMIC_SIZE,
+		__ASSERT((msg_count * msg_size) <= CONFIG_CMSIS_V2_MSGQ_MAX_DYNAMIC_SIZE,
 			 "message queue size exceeds dynamic maximum");
 
 #if (K_HEAP_MEM_POOL_SIZE > 0)
 		msgq->pool = k_calloc(msg_count, msg_size);
 		if (msgq->pool == NULL) {
-			k_mem_slab_free(&cv2_msgq_slab, (void *)msgq);
+			if (msgq->is_cb_dynamic_allocation) {
+				k_mem_slab_free(&cmsis_rtos_msgq_cb_slab, (void *)msgq);
+			}
 			return NULL;
 		}
 		msgq->is_dynamic_allocation = TRUE;
 #else
-		k_mem_slab_free(&cv2_msgq_slab, (void *)msgq);
+		if (msgq->is_cb_dynamic_allocation) {
+			k_mem_slab_free(&cmsis_rtos_msgq_cb_slab, (void *)msgq);
+		}
 		return NULL;
 #endif
 	} else {
@@ -73,12 +79,7 @@ osMessageQueueId_t osMessageQueueNew(uint32_t msg_count, uint32_t msg_size,
 
 	k_msgq_init(&msgq->z_msgq, msgq->pool, msg_size, msg_count);
 
-	if (attr->name == NULL) {
-		strncpy(msgq->name, init_msgq_attrs.name,
-			sizeof(msgq->name) - 1);
-	} else {
-		strncpy(msgq->name, attr->name, sizeof(msgq->name) - 1);
-	}
+	msgq->name = (attr->name == NULL) ? init_msgq_attrs.name : attr->name;
 
 	return (osMessageQueueId_t)(msgq);
 }
@@ -86,10 +87,10 @@ osMessageQueueId_t osMessageQueueNew(uint32_t msg_count, uint32_t msg_size,
 /**
  * @brief Put a message to a Queue.
  */
-osStatus_t osMessageQueuePut(osMessageQueueId_t msgq_id, const void *msg_ptr,
-			     uint8_t msg_prio, uint32_t timeout)
+osStatus_t osMessageQueuePut(osMessageQueueId_t msgq_id, const void *msg_ptr, uint8_t msg_prio,
+			     uint32_t timeout)
 {
-	struct cv2_msgq *msgq = (struct cv2_msgq *)msgq_id;
+	struct cmsis_rtos_msgq_cb *msgq = (struct cmsis_rtos_msgq_cb *)msgq_id;
 	int retval;
 
 	ARG_UNUSED(msg_prio);
@@ -108,8 +109,7 @@ osStatus_t osMessageQueuePut(osMessageQueueId_t msgq_id, const void *msg_ptr,
 	} else if (timeout == osWaitForever) {
 		retval = k_msgq_put(&msgq->z_msgq, (void *)msg_ptr, K_FOREVER);
 	} else {
-		retval = k_msgq_put(&msgq->z_msgq, (void *)msg_ptr,
-				    K_TICKS(timeout));
+		retval = k_msgq_put(&msgq->z_msgq, (void *)msg_ptr, K_TICKS(timeout));
 	}
 
 	if (retval == 0) {
@@ -124,10 +124,10 @@ osStatus_t osMessageQueuePut(osMessageQueueId_t msgq_id, const void *msg_ptr,
 /**
  * @brief Get a message or Wait for a Message from a Queue.
  */
-osStatus_t osMessageQueueGet(osMessageQueueId_t msgq_id, void *msg_ptr,
-			     uint8_t *msg_prio, uint32_t timeout)
+osStatus_t osMessageQueueGet(osMessageQueueId_t msgq_id, void *msg_ptr, uint8_t *msg_prio,
+			     uint32_t timeout)
 {
-	struct cv2_msgq *msgq = (struct cv2_msgq *)msgq_id;
+	struct cmsis_rtos_msgq_cb *msgq = (struct cmsis_rtos_msgq_cb *)msgq_id;
 	int retval;
 
 	ARG_UNUSED(msg_prio);
@@ -146,8 +146,7 @@ osStatus_t osMessageQueueGet(osMessageQueueId_t msgq_id, void *msg_ptr,
 	} else if (timeout == osWaitForever) {
 		retval = k_msgq_get(&msgq->z_msgq, msg_ptr, K_FOREVER);
 	} else {
-		retval = k_msgq_get(&msgq->z_msgq, msg_ptr,
-				    K_TICKS(timeout));
+		retval = k_msgq_get(&msgq->z_msgq, msg_ptr, K_TICKS(timeout));
 	}
 
 	if (retval == 0) {
@@ -166,7 +165,7 @@ osStatus_t osMessageQueueGet(osMessageQueueId_t msgq_id, void *msg_ptr,
  */
 uint32_t osMessageQueueGetCapacity(osMessageQueueId_t msgq_id)
 {
-	struct cv2_msgq *msgq = (struct cv2_msgq *)msgq_id;
+	struct cmsis_rtos_msgq_cb *msgq = (struct cmsis_rtos_msgq_cb *)msgq_id;
 
 	if (msgq == NULL) {
 		return 0;
@@ -180,7 +179,7 @@ uint32_t osMessageQueueGetCapacity(osMessageQueueId_t msgq_id)
  */
 uint32_t osMessageQueueGetMsgSize(osMessageQueueId_t msgq_id)
 {
-	struct cv2_msgq *msgq = (struct cv2_msgq *)msgq_id;
+	struct cmsis_rtos_msgq_cb *msgq = (struct cmsis_rtos_msgq_cb *)msgq_id;
 
 	if (msgq == NULL) {
 		return 0;
@@ -194,7 +193,7 @@ uint32_t osMessageQueueGetMsgSize(osMessageQueueId_t msgq_id)
  */
 uint32_t osMessageQueueGetCount(osMessageQueueId_t msgq_id)
 {
-	struct cv2_msgq *msgq = (struct cv2_msgq *)msgq_id;
+	struct cmsis_rtos_msgq_cb *msgq = (struct cmsis_rtos_msgq_cb *)msgq_id;
 
 	if (msgq == NULL) {
 		return 0;
@@ -208,7 +207,7 @@ uint32_t osMessageQueueGetCount(osMessageQueueId_t msgq_id)
  */
 uint32_t osMessageQueueGetSpace(osMessageQueueId_t msgq_id)
 {
-	struct cv2_msgq *msgq = (struct cv2_msgq *)msgq_id;
+	struct cmsis_rtos_msgq_cb *msgq = (struct cmsis_rtos_msgq_cb *)msgq_id;
 
 	if (msgq == NULL) {
 		return 0;
@@ -219,16 +218,16 @@ uint32_t osMessageQueueGetSpace(osMessageQueueId_t msgq_id)
 
 /**
  * @brief Get name of a Message Queue object.
+ * This function may be called from Interrupt Service Routines.
  */
 const char *osMessageQueueGetName(osMessageQueueId_t msgq_id)
 {
-	struct cv2_msgq *msgq = (struct cv2_msgq *)msgq_id;
+	struct cmsis_rtos_msgq_cb *msgq = (struct cmsis_rtos_msgq_cb *)msgq_id;
 
-	if (!k_is_in_isr() && (msgq_id != NULL)) {
-		return msgq->name;
-	} else {
+	if (msgq == NULL) {
 		return NULL;
 	}
+	return msgq->name;
 }
 
 /**
@@ -236,7 +235,7 @@ const char *osMessageQueueGetName(osMessageQueueId_t msgq_id)
  */
 osStatus_t osMessageQueueReset(osMessageQueueId_t msgq_id)
 {
-	struct cv2_msgq *msgq = (struct cv2_msgq *)msgq_id;
+	struct cmsis_rtos_msgq_cb *msgq = (struct cmsis_rtos_msgq_cb *)msgq_id;
 
 	if (msgq == NULL) {
 		return osErrorParameter;
@@ -261,7 +260,7 @@ osStatus_t osMessageQueueReset(osMessageQueueId_t msgq_id)
  */
 osStatus_t osMessageQueueDelete(osMessageQueueId_t msgq_id)
 {
-	struct cv2_msgq *msgq = (struct cv2_msgq *)msgq_id;
+	struct cmsis_rtos_msgq_cb *msgq = (struct cmsis_rtos_msgq_cb *)msgq_id;
 
 	if (msgq == NULL) {
 		return osErrorParameter;
@@ -279,7 +278,8 @@ osStatus_t osMessageQueueDelete(osMessageQueueId_t msgq_id)
 	if (msgq->is_dynamic_allocation) {
 		k_free(msgq->pool);
 	}
-	k_mem_slab_free(&cv2_msgq_slab, (void *)msgq);
-
+	if (msgq->is_cb_dynamic_allocation) {
+		k_mem_slab_free(&cmsis_rtos_msgq_cb_slab, (void *)msgq);
+	}
 	return osOK;
 }
diff --git a/subsys/portability/cmsis_rtos_v2/mutex.c b/subsys/portability/cmsis_rtos_v2/mutex.c
index d942f20e1bd..59408e542bb 100644
--- a/subsys/portability/cmsis_rtos_v2/mutex.c
+++ b/subsys/portability/cmsis_rtos_v2/mutex.c
@@ -5,10 +5,11 @@
  */
 
 #include <zephyr/kernel.h>
+#include <zephyr/portability/cmsis_types.h>
 #include <string.h>
 #include "wrapper.h"
 
-K_MEM_SLAB_DEFINE(cv2_mutex_slab, sizeof(struct cv2_mutex),
+K_MEM_SLAB_DEFINE(cmsis_rtos_mutex_cb_slab, sizeof(struct cmsis_rtos_mutex_cb),
 		  CONFIG_CMSIS_V2_MUTEX_MAX_COUNT, 4);
 
 static const osMutexAttr_t init_mutex_attrs = {
@@ -23,7 +24,7 @@ static const osMutexAttr_t init_mutex_attrs = {
  */
 osMutexId_t osMutexNew(const osMutexAttr_t *attr)
 {
-	struct cv2_mutex *mutex;
+	struct cmsis_rtos_mutex_cb *mutex;
 
 	if (k_is_in_isr()) {
 		return NULL;
@@ -36,24 +37,21 @@ osMutexId_t osMutexNew(const osMutexAttr_t *attr)
 	__ASSERT(attr->attr_bits & osMutexPrioInherit,
 		 "Zephyr supports osMutexPrioInherit by default. Do not unselect it\n");
 
-	__ASSERT(!(attr->attr_bits & osMutexRobust),
-		 "Zephyr does not support osMutexRobust.\n");
+	__ASSERT(!(attr->attr_bits & osMutexRobust), "Zephyr does not support osMutexRobust.\n");
 
-	if (k_mem_slab_alloc(&cv2_mutex_slab, (void **)&mutex, K_MSEC(100)) == 0) {
-		memset(mutex, 0, sizeof(struct cv2_mutex));
-	} else {
+	if (attr->cb_mem != NULL) {
+		__ASSERT(attr->cb_size == sizeof(struct cmsis_rtos_mutex_cb), "Invalid cb_size\n");
+		mutex = (struct cmsis_rtos_mutex_cb *)attr->cb_mem;
+	} else if (k_mem_slab_alloc(&cmsis_rtos_mutex_cb_slab, (void **)&mutex, K_MSEC(100)) != 0) {
 		return NULL;
 	}
+	memset(mutex, 0, sizeof(struct cmsis_rtos_mutex_cb));
+	mutex->is_cb_dynamic_allocation = attr->cb_mem == NULL;
 
 	k_mutex_init(&mutex->z_mutex);
 	mutex->state = attr->attr_bits;
 
-	if (attr->name == NULL) {
-		strncpy(mutex->name, init_mutex_attrs.name,
-			sizeof(mutex->name) - 1);
-	} else {
-		strncpy(mutex->name, attr->name, sizeof(mutex->name) - 1);
-	}
+	mutex->name = (attr->name == NULL) ? init_mutex_attrs.name : attr->name;
 
 	return (osMutexId_t)mutex;
 }
@@ -63,7 +61,7 @@ osMutexId_t osMutexNew(const osMutexAttr_t *attr)
  */
 osStatus_t osMutexAcquire(osMutexId_t mutex_id, uint32_t timeout)
 {
-	struct cv2_mutex *mutex = (struct cv2_mutex *) mutex_id;
+	struct cmsis_rtos_mutex_cb *mutex = (struct cmsis_rtos_mutex_cb *)mutex_id;
 	int status;
 
 	if (mutex_id == NULL) {
@@ -79,8 +77,7 @@ osStatus_t osMutexAcquire(osMutexId_t mutex_id, uint32_t timeout)
 	} else if (timeout == 0U) {
 		status = k_mutex_lock(&mutex->z_mutex, K_NO_WAIT);
 	} else {
-		status = k_mutex_lock(&mutex->z_mutex,
-				      K_TICKS(timeout));
+		status = k_mutex_lock(&mutex->z_mutex, K_TICKS(timeout));
 	}
 
 	if (timeout != 0 && (status == -EAGAIN || status == -EBUSY)) {
@@ -97,7 +94,7 @@ osStatus_t osMutexAcquire(osMutexId_t mutex_id, uint32_t timeout)
  */
 osStatus_t osMutexRelease(osMutexId_t mutex_id)
 {
-	struct cv2_mutex *mutex = (struct cv2_mutex *) mutex_id;
+	struct cmsis_rtos_mutex_cb *mutex = (struct cmsis_rtos_mutex_cb *)mutex_id;
 
 	if (mutex_id == NULL) {
 		return osErrorParameter;
@@ -119,7 +116,7 @@ osStatus_t osMutexRelease(osMutexId_t mutex_id)
  */
 osStatus_t osMutexDelete(osMutexId_t mutex_id)
 {
-	struct cv2_mutex *mutex = (struct cv2_mutex *)mutex_id;
+	struct cmsis_rtos_mutex_cb *mutex = (struct cmsis_rtos_mutex_cb *)mutex_id;
 
 	if (mutex_id == NULL) {
 		return osErrorParameter;
@@ -132,16 +129,16 @@ osStatus_t osMutexDelete(osMutexId_t mutex_id)
 	/* The status code "osErrorResource" (mutex specified by parameter
 	 * mutex_id is in an invalid mutex state) is not supported in Zephyr.
 	 */
-
-	k_mem_slab_free(&cv2_mutex_slab, (void *)mutex);
+	if (mutex->is_cb_dynamic_allocation) {
+		k_mem_slab_free(&cmsis_rtos_mutex_cb_slab, (void *)mutex);
+	}
 
 	return osOK;
 }
 
-
 osThreadId_t osMutexGetOwner(osMutexId_t mutex_id)
 {
-	struct cv2_mutex *mutex = (struct cv2_mutex *)mutex_id;
+	struct cmsis_rtos_mutex_cb *mutex = (struct cmsis_rtos_mutex_cb *)mutex_id;
 
 	if (k_is_in_isr() || (mutex == NULL)) {
 		return NULL;
@@ -155,13 +152,16 @@ osThreadId_t osMutexGetOwner(osMutexId_t mutex_id)
 	return get_cmsis_thread_id(mutex->z_mutex.owner);
 }
 
+/**
+ * @brief Get name of a mutex.
+ * This function may be called from Interrupt Service Routines.
+ */
 const char *osMutexGetName(osMutexId_t mutex_id)
 {
-	struct cv2_mutex *mutex = (struct cv2_mutex *)mutex_id;
+	struct cmsis_rtos_mutex_cb *mutex = (struct cmsis_rtos_mutex_cb *)mutex_id;
 
-	if (k_is_in_isr() || (mutex == NULL)) {
+	if (mutex == NULL) {
 		return NULL;
 	}
-
 	return mutex->name;
 }
diff --git a/subsys/portability/cmsis_rtos_v2/semaphore.c b/subsys/portability/cmsis_rtos_v2/semaphore.c
index 6a006d1259b..19705cc9255 100644
--- a/subsys/portability/cmsis_rtos_v2/semaphore.c
+++ b/subsys/portability/cmsis_rtos_v2/semaphore.c
@@ -5,10 +5,10 @@
  */
 
 #include <zephyr/kernel.h>
+#include <zephyr/portability/cmsis_types.h>
 #include <string.h>
-#include "wrapper.h"
 
-K_MEM_SLAB_DEFINE(cv2_semaphore_slab, sizeof(struct cv2_sem),
+K_MEM_SLAB_DEFINE(cmsis_rtos_semaphore_cb_slab, sizeof(struct cmsis_rtos_semaphore_cb),
 		  CONFIG_CMSIS_V2_SEMAPHORE_MAX_COUNT, 4);
 
 static const osSemaphoreAttr_t init_sema_attrs = {
@@ -24,7 +24,7 @@ static const osSemaphoreAttr_t init_sema_attrs = {
 osSemaphoreId_t osSemaphoreNew(uint32_t max_count, uint32_t initial_count,
 			       const osSemaphoreAttr_t *attr)
 {
-	struct cv2_sem *semaphore;
+	struct cmsis_rtos_semaphore_cb *semaphore;
 
 	if (k_is_in_isr()) {
 		return NULL;
@@ -34,22 +34,20 @@ osSemaphoreId_t osSemaphoreNew(uint32_t max_count, uint32_t initial_count,
 		attr = &init_sema_attrs;
 	}
 
-	if (k_mem_slab_alloc(&cv2_semaphore_slab,
-			     (void **)&semaphore, K_MSEC(100)) == 0) {
-		(void)memset(semaphore, 0, sizeof(struct cv2_sem));
-	} else {
+	if (attr->cb_mem != NULL) {
+		__ASSERT(attr->cb_size == sizeof(struct cmsis_rtos_semaphore_cb),
+			 "Invalid cb_size\n");
+		semaphore = (struct cmsis_rtos_semaphore_cb *)attr->cb_mem;
+	} else if (k_mem_slab_alloc(&cmsis_rtos_semaphore_cb_slab, (void **)&semaphore,
+				    K_MSEC(100)) != 0) {
 		return NULL;
 	}
+	(void)memset(semaphore, 0, sizeof(struct cmsis_rtos_semaphore_cb));
+	semaphore->is_cb_dynamic_allocation = attr->cb_mem == NULL;
 
 	k_sem_init(&semaphore->z_semaphore, initial_count, max_count);
 
-	if (attr->name == NULL) {
-		strncpy(semaphore->name, init_sema_attrs.name,
-			sizeof(semaphore->name) - 1);
-	} else {
-		strncpy(semaphore->name, attr->name,
-			sizeof(semaphore->name) - 1);
-	}
+	semaphore->name = (attr->name == NULL) ? init_sema_attrs.name : attr->name;
 
 	return (osSemaphoreId_t)semaphore;
 }
@@ -59,7 +57,7 @@ osSemaphoreId_t osSemaphoreNew(uint32_t max_count, uint32_t initial_count,
  */
 osStatus_t osSemaphoreAcquire(osSemaphoreId_t semaphore_id, uint32_t timeout)
 {
-	struct cv2_sem *semaphore = (struct cv2_sem *) semaphore_id;
+	struct cmsis_rtos_semaphore_cb *semaphore = (struct cmsis_rtos_semaphore_cb *)semaphore_id;
 	int status;
 
 	if (semaphore_id == NULL) {
@@ -76,8 +74,7 @@ osStatus_t osSemaphoreAcquire(osSemaphoreId_t semaphore_id, uint32_t timeout)
 	} else if (timeout == 0U) {
 		status = k_sem_take(&semaphore->z_semaphore, K_NO_WAIT);
 	} else {
-		status = k_sem_take(&semaphore->z_semaphore,
-				    K_TICKS(timeout));
+		status = k_sem_take(&semaphore->z_semaphore, K_TICKS(timeout));
 	}
 
 	if (status == -EBUSY) {
@@ -91,7 +88,7 @@ osStatus_t osSemaphoreAcquire(osSemaphoreId_t semaphore_id, uint32_t timeout)
 
 uint32_t osSemaphoreGetCount(osSemaphoreId_t semaphore_id)
 {
-	struct cv2_sem *semaphore = (struct cv2_sem *)semaphore_id;
+	struct cmsis_rtos_semaphore_cb *semaphore = (struct cmsis_rtos_semaphore_cb *)semaphore_id;
 
 	if (semaphore_id == NULL) {
 		return 0;
@@ -105,15 +102,14 @@ uint32_t osSemaphoreGetCount(osSemaphoreId_t semaphore_id)
  */
 osStatus_t osSemaphoreRelease(osSemaphoreId_t semaphore_id)
 {
-	struct cv2_sem *semaphore = (struct cv2_sem *) semaphore_id;
+	struct cmsis_rtos_semaphore_cb *semaphore = (struct cmsis_rtos_semaphore_cb *)semaphore_id;
 
 	if (semaphore_id == NULL) {
 		return osErrorParameter;
 	}
 
 	/* All tokens have already been released */
-	if (k_sem_count_get(&semaphore->z_semaphore) ==
-	    semaphore->z_semaphore.limit) {
+	if (k_sem_count_get(&semaphore->z_semaphore) == semaphore->z_semaphore.limit) {
 		return osErrorResource;
 	}
 
@@ -127,7 +123,7 @@ osStatus_t osSemaphoreRelease(osSemaphoreId_t semaphore_id)
  */
 osStatus_t osSemaphoreDelete(osSemaphoreId_t semaphore_id)
 {
-	struct cv2_sem *semaphore = (struct cv2_sem *)semaphore_id;
+	struct cmsis_rtos_semaphore_cb *semaphore = (struct cmsis_rtos_semaphore_cb *)semaphore_id;
 
 	if (semaphore_id == NULL) {
 		return osErrorParameter;
@@ -141,19 +137,23 @@ osStatus_t osSemaphoreDelete(osSemaphoreId_t semaphore_id)
 	 * parameter semaphore_id is in an invalid semaphore state) is not
 	 * supported in Zephyr.
 	 */
-
-	k_mem_slab_free(&cv2_semaphore_slab, (void *)semaphore);
+	if (semaphore->is_cb_dynamic_allocation) {
+		k_mem_slab_free(&cmsis_rtos_semaphore_cb_slab, (void *)semaphore);
+	}
 
 	return osOK;
 }
 
+/**
+ * @brief Get name of a semaphore.
+ * This function may be called from Interrupt Service Routines.
+ */
 const char *osSemaphoreGetName(osSemaphoreId_t semaphore_id)
 {
-	struct cv2_sem *semaphore = (struct cv2_sem *)semaphore_id;
+	struct cmsis_rtos_semaphore_cb *semaphore = (struct cmsis_rtos_semaphore_cb *)semaphore_id;
 
-	if (!k_is_in_isr() && (semaphore_id != NULL)) {
-		return semaphore->name;
-	} else {
+	if (semaphore == NULL) {
 		return NULL;
 	}
+	return semaphore->name;
 }
diff --git a/subsys/portability/cmsis_rtos_v2/thread.c b/subsys/portability/cmsis_rtos_v2/thread.c
index 9cbc702b5fc..cecb2d234f3 100644
--- a/subsys/portability/cmsis_rtos_v2/thread.c
+++ b/subsys/portability/cmsis_rtos_v2/thread.c
@@ -10,6 +10,7 @@
 #include <string.h>
 #include <zephyr/sys/atomic.h>
 #include <zephyr/debug/stack.h>
+#include <zephyr/portability/cmsis_types.h>
 #include "wrapper.h"
 
 static const osThreadAttr_t init_thread_attrs = {
@@ -25,13 +26,16 @@ static const osThreadAttr_t init_thread_attrs = {
 };
 
 static sys_dlist_t thread_list;
-static struct cv2_thread cv2_thread_pool[CONFIG_CMSIS_V2_THREAD_MAX_COUNT];
-static atomic_t thread_num;
-static atomic_t thread_num_dynamic;
 
+static atomic_t num_dynamic_cb;
+#if CONFIG_CMSIS_V2_THREAD_MAX_COUNT != 0
+static struct cmsis_rtos_thread_cb cmsis_rtos_thread_cb_pool[CONFIG_CMSIS_V2_THREAD_MAX_COUNT];
+#endif
+
+static atomic_t num_dynamic_stack;
 #if CONFIG_CMSIS_V2_THREAD_DYNAMIC_MAX_COUNT != 0
-static K_THREAD_STACK_ARRAY_DEFINE(cv2_thread_stack_pool,		     \
-				   CONFIG_CMSIS_V2_THREAD_DYNAMIC_MAX_COUNT, \
+static K_THREAD_STACK_ARRAY_DEFINE(cmsis_rtos_thread_stack_pool,
+				   CONFIG_CMSIS_V2_THREAD_DYNAMIC_MAX_COUNT,
 				   CONFIG_CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE);
 #endif
 
@@ -54,22 +58,17 @@ static inline uint32_t cmsis_to_zephyr_priority(uint32_t c_prio)
 
 static void zephyr_thread_wrapper(void *arg1, void *arg2, void *arg3)
 {
-	struct cv2_thread *tid = arg2;
-	void * (*fun_ptr)(void *) = arg3;
-
+	osThreadFunc_t fun_ptr = arg3;
 	fun_ptr(arg1);
-
-	tid->has_joined = TRUE;
-	k_sem_give(&tid->join_guard);
 }
 
 void *is_cmsis_rtos_v2_thread(void *thread_id)
 {
 	sys_dnode_t *pnode;
-	struct cv2_thread *itr;
+	struct cmsis_rtos_thread_cb *itr;
 
 	SYS_DLIST_FOR_EACH_NODE(&thread_list, pnode) {
-		itr = CONTAINER_OF(pnode, struct cv2_thread, node);
+		itr = CONTAINER_OF(pnode, struct cmsis_rtos_thread_cb, node);
 
 		if ((void *)itr == thread_id) {
 			return itr;
@@ -82,11 +81,11 @@ void *is_cmsis_rtos_v2_thread(void *thread_id)
 osThreadId_t get_cmsis_thread_id(k_tid_t tid)
 {
 	sys_dnode_t *pnode;
-	struct cv2_thread *itr;
+	struct cmsis_rtos_thread_cb *itr;
 
 	if (tid != NULL) {
 		SYS_DLIST_FOR_EACH_NODE(&thread_list, pnode) {
-			itr = CONTAINER_OF(pnode, struct cv2_thread, node);
+			itr = CONTAINER_OF(pnode, struct cmsis_rtos_thread_cb, node);
 
 			if (&itr->z_thread == tid) {
 				return (osThreadId_t)itr;
@@ -100,25 +99,19 @@ osThreadId_t get_cmsis_thread_id(k_tid_t tid)
 /**
  * @brief Create a thread and add it to Active Threads.
  */
-osThreadId_t osThreadNew(osThreadFunc_t threadfunc, void *arg,
-			 const osThreadAttr_t *attr)
+osThreadId_t osThreadNew(osThreadFunc_t threadfunc, void *arg, const osThreadAttr_t *attr)
 {
 	int32_t prio;
 	osPriority_t cv2_prio;
-	struct cv2_thread *tid;
+	struct cmsis_rtos_thread_cb *tid;
 	static uint32_t one_time;
 	void *stack;
 	size_t stack_size;
-	uint32_t this_thread_num;
 
 	if (k_is_in_isr()) {
 		return NULL;
 	}
 
-	if (thread_num >= CONFIG_CMSIS_V2_THREAD_MAX_COUNT) {
-		return NULL;
-	}
-
 	if (attr == NULL) {
 		attr = &init_thread_attrs;
 	}
@@ -129,50 +122,51 @@ osThreadId_t osThreadNew(osThreadFunc_t threadfunc, void *arg,
 		cv2_prio = attr->priority;
 	}
 
-	if ((attr->stack_mem == NULL) && (thread_num_dynamic >=
-					  CONFIG_CMSIS_V2_THREAD_DYNAMIC_MAX_COUNT)) {
+	if (attr->cb_mem == NULL && num_dynamic_cb >= CONFIG_CMSIS_V2_THREAD_MAX_COUNT) {
+		return NULL;
+	}
+
+	if (attr->stack_mem == NULL &&
+	    num_dynamic_stack >= CONFIG_CMSIS_V2_THREAD_DYNAMIC_MAX_COUNT) {
 		return NULL;
 	}
 
 	BUILD_ASSERT(osPriorityISR <= CONFIG_NUM_PREEMPT_PRIORITIES,
 		     "Configure NUM_PREEMPT_PRIORITIES to at least osPriorityISR");
 
-	BUILD_ASSERT(CONFIG_CMSIS_V2_THREAD_DYNAMIC_MAX_COUNT <=
-		     CONFIG_CMSIS_V2_THREAD_MAX_COUNT,
-		     "Number of dynamic threads cannot exceed max number of threads.");
-
 	BUILD_ASSERT(CONFIG_CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE <=
-		     CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE,
+			     CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE,
 		     "Default dynamic thread stack size cannot exceed max stack size");
 
-	__ASSERT(attr->stack_size <= CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE,
-		 "invalid stack size\n");
+	__ASSERT(attr->stack_size <= CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE, "invalid stack size\n");
 
-	__ASSERT((cv2_prio >= osPriorityIdle) && (cv2_prio <= osPriorityISR),
-		 "invalid priority\n");
+	__ASSERT((cv2_prio >= osPriorityIdle) && (cv2_prio <= osPriorityISR), "invalid priority\n");
 
-	if (attr->stack_mem != NULL) {
-		if (attr->stack_size == 0) {
-			return NULL;
-		}
+	if (attr->stack_mem != NULL && attr->stack_size == 0) {
+		return NULL;
 	}
 
-	prio = cmsis_to_zephyr_priority(cv2_prio);
-
-	this_thread_num = atomic_inc((atomic_t *)&thread_num);
+#if CONFIG_CMSIS_V2_THREAD_MAX_COUNT != 0
+	if (attr->cb_mem == NULL) {
+		uint32_t this_dynamic_cb;
+		this_dynamic_cb = atomic_inc(&num_dynamic_cb);
+		tid = &cmsis_rtos_thread_cb_pool[this_dynamic_cb];
+	} else
+#endif
+	{
+		tid = (struct cmsis_rtos_thread_cb *)attr->cb_mem;
+	}
 
-	tid = &cv2_thread_pool[this_thread_num];
 	tid->attr_bits = attr->attr_bits;
 
 #if CONFIG_CMSIS_V2_THREAD_DYNAMIC_MAX_COUNT != 0
 	if (attr->stack_mem == NULL) {
-		uint32_t this_thread_num_dynamic;
+		uint32_t this_dynamic_stack;
 		__ASSERT(CONFIG_CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE > 0,
 			 "dynamic stack size must be configured to be non-zero\n");
-		this_thread_num_dynamic =
-			atomic_inc((atomic_t *)&thread_num_dynamic);
+		this_dynamic_stack = atomic_inc(&num_dynamic_stack);
 		stack_size = CONFIG_CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE;
-		stack = cv2_thread_stack_pool[this_thread_num_dynamic];
+		stack = cmsis_rtos_thread_stack_pool[this_dynamic_stack];
 	} else
 #endif
 	{
@@ -181,8 +175,8 @@ osThreadId_t osThreadNew(osThreadFunc_t threadfunc, void *arg,
 	}
 
 	k_poll_signal_init(&tid->poll_signal);
-	k_poll_event_init(&tid->poll_event, K_POLL_TYPE_SIGNAL,
-			  K_POLL_MODE_NOTIFY_ONLY, &tid->poll_signal);
+	k_poll_event_init(&tid->poll_event, K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY,
+			  &tid->poll_signal);
 	tid->signal_results = 0U;
 
 	/* TODO: Do this somewhere only once */
@@ -193,48 +187,29 @@ osThreadId_t osThreadNew(osThreadFunc_t threadfunc, void *arg,
 
 	sys_dlist_append(&thread_list, &tid->node);
 
-	k_sem_init(&tid->join_guard, 0, 1);
-	tid->has_joined = FALSE;
-
-	(void)k_thread_create(&tid->z_thread,
-			      stack, stack_size,
-			      zephyr_thread_wrapper,
-			      (void *)arg, tid, threadfunc,
-			      prio, 0, K_NO_WAIT);
+	prio = cmsis_to_zephyr_priority(cv2_prio);
 
-	if (attr->name == NULL) {
-		strncpy(tid->name, init_thread_attrs.name,
-			sizeof(tid->name) - 1);
-	} else {
-		strncpy(tid->name, attr->name, sizeof(tid->name) - 1);
-	}
+	(void)k_thread_create(&tid->z_thread, stack, stack_size, zephyr_thread_wrapper, (void *)arg,
+			      NULL, threadfunc, prio, 0, K_NO_WAIT);
 
-	k_thread_name_set(&tid->z_thread, tid->name);
+	const char *name = (attr->name == NULL) ? init_thread_attrs.name : attr->name;
+	k_thread_name_set(&tid->z_thread, name);
 
 	return (osThreadId_t)tid;
 }
 
 /**
  * @brief Get name of a thread.
+ * This function may be called from Interrupt Service Routines.
  */
 const char *osThreadGetName(osThreadId_t thread_id)
 {
-	const char *name = NULL;
-
-	if (k_is_in_isr() || (thread_id == NULL)) {
-		name = NULL;
-	} else {
-		if (is_cmsis_rtos_v2_thread(thread_id) == NULL) {
-			name = NULL;
-		} else {
-			struct cv2_thread *tid =
-				(struct cv2_thread *)thread_id;
+	struct cmsis_rtos_thread_cb *tid = (struct cmsis_rtos_thread_cb *)thread_id;
 
-			name = k_thread_name_get(&tid->z_thread);
-		}
+	if (tid == NULL) {
+		return NULL;
 	}
-
-	return name;
+	return k_thread_name_get(&tid->z_thread);
 }
 
 /**
@@ -252,11 +227,10 @@ osThreadId_t osThreadGetId(void)
  */
 osPriority_t osThreadGetPriority(osThreadId_t thread_id)
 {
-	struct cv2_thread *tid = (struct cv2_thread *)thread_id;
+	struct cmsis_rtos_thread_cb *tid = (struct cmsis_rtos_thread_cb *)thread_id;
 	uint32_t priority;
 
-	if (k_is_in_isr() || (tid == NULL) ||
-	    (is_cmsis_rtos_v2_thread(tid) == NULL) ||
+	if (k_is_in_isr() || (tid == NULL) || (is_cmsis_rtos_v2_thread(tid) == NULL) ||
 	    (_is_thread_cmsis_inactive(&tid->z_thread))) {
 		return osPriorityError;
 	}
@@ -270,7 +244,7 @@ osPriority_t osThreadGetPriority(osThreadId_t thread_id)
  */
 osStatus_t osThreadSetPriority(osThreadId_t thread_id, osPriority_t priority)
 {
-	struct cv2_thread *tid = (struct cv2_thread *)thread_id;
+	struct cmsis_rtos_thread_cb *tid = (struct cmsis_rtos_thread_cb *)thread_id;
 
 	if ((tid == NULL) || (is_cmsis_rtos_v2_thread(tid) == NULL) ||
 	    (priority <= osPriorityNone) || (priority > osPriorityISR)) {
@@ -285,8 +259,7 @@ osStatus_t osThreadSetPriority(osThreadId_t thread_id, osPriority_t priority)
 		return osErrorResource;
 	}
 
-	k_thread_priority_set((k_tid_t)&tid->z_thread,
-			      cmsis_to_zephyr_priority(priority));
+	k_thread_priority_set((k_tid_t)&tid->z_thread, cmsis_to_zephyr_priority(priority));
 
 	return osOK;
 }
@@ -296,11 +269,10 @@ osStatus_t osThreadSetPriority(osThreadId_t thread_id, osPriority_t priority)
  */
 osThreadState_t osThreadGetState(osThreadId_t thread_id)
 {
-	struct cv2_thread *tid = (struct cv2_thread *)thread_id;
+	struct cmsis_rtos_thread_cb *tid = (struct cmsis_rtos_thread_cb *)thread_id;
 	osThreadState_t state;
 
-	if (k_is_in_isr() || (tid == NULL) ||
-	    (is_cmsis_rtos_v2_thread(tid) == NULL)) {
+	if (k_is_in_isr() || (tid == NULL) || (is_cmsis_rtos_v2_thread(tid) == NULL)) {
 		return osThreadError;
 	}
 
@@ -349,7 +321,7 @@ osStatus_t osThreadYield(void)
  */
 uint32_t osThreadGetStackSize(osThreadId_t thread_id)
 {
-	struct cv2_thread *tid = (struct cv2_thread *)thread_id;
+	struct cmsis_rtos_thread_cb *tid = (struct cmsis_rtos_thread_cb *)thread_id;
 
 	__ASSERT(tid, "");
 	__ASSERT(is_cmsis_rtos_v2_thread(tid), "");
@@ -364,7 +336,7 @@ uint32_t osThreadGetStackSize(osThreadId_t thread_id)
  */
 uint32_t osThreadGetStackSpace(osThreadId_t thread_id)
 {
-	struct cv2_thread *tid = (struct cv2_thread *)thread_id;
+	struct cmsis_rtos_thread_cb *tid = (struct cmsis_rtos_thread_cb *)thread_id;
 	size_t unused;
 	int ret;
 
@@ -385,7 +357,7 @@ uint32_t osThreadGetStackSpace(osThreadId_t thread_id)
  */
 osStatus_t osThreadSuspend(osThreadId_t thread_id)
 {
-	struct cv2_thread *tid = (struct cv2_thread *)thread_id;
+	struct cmsis_rtos_thread_cb *tid = (struct cmsis_rtos_thread_cb *)thread_id;
 
 	if ((tid == NULL) || (is_cmsis_rtos_v2_thread(tid) == NULL)) {
 		return osErrorParameter;
@@ -409,7 +381,7 @@ osStatus_t osThreadSuspend(osThreadId_t thread_id)
  */
 osStatus_t osThreadResume(osThreadId_t thread_id)
 {
-	struct cv2_thread *tid = (struct cv2_thread *)thread_id;
+	struct cmsis_rtos_thread_cb *tid = (struct cmsis_rtos_thread_cb *)thread_id;
 
 	if ((tid == NULL) || (is_cmsis_rtos_v2_thread(tid) == NULL)) {
 		return osErrorParameter;
@@ -434,7 +406,7 @@ osStatus_t osThreadResume(osThreadId_t thread_id)
  */
 osStatus_t osThreadDetach(osThreadId_t thread_id)
 {
-	struct cv2_thread *tid = (struct cv2_thread *)thread_id;
+	struct cmsis_rtos_thread_cb *tid = (struct cmsis_rtos_thread_cb *)thread_id;
 
 	if ((tid == NULL) || (is_cmsis_rtos_v2_thread(tid) == NULL)) {
 		return osErrorParameter;
@@ -453,8 +425,6 @@ osStatus_t osThreadDetach(osThreadId_t thread_id)
 
 	tid->attr_bits = osThreadDetached;
 
-	k_sem_give(&tid->join_guard);
-
 	return osOK;
 }
 
@@ -463,8 +433,8 @@ osStatus_t osThreadDetach(osThreadId_t thread_id)
  */
 osStatus_t osThreadJoin(osThreadId_t thread_id)
 {
-	struct cv2_thread *tid = (struct cv2_thread *)thread_id;
-	osStatus_t status = osError;
+	struct cmsis_rtos_thread_cb *tid = (struct cmsis_rtos_thread_cb *)thread_id;
+	int ret = 0;
 
 	if ((tid == NULL) || (is_cmsis_rtos_v2_thread(tid) == NULL)) {
 		return osErrorParameter;
@@ -482,21 +452,8 @@ osStatus_t osThreadJoin(osThreadId_t thread_id)
 		return osErrorResource;
 	}
 
-	if (!tid->has_joined) {
-		if (k_sem_take(&tid->join_guard, K_FOREVER) != 0) {
-			__ASSERT(0, "Failed to take from join guard.");
-		}
-
-		k_sem_give(&tid->join_guard);
-	}
-
-	if (tid->has_joined && (tid->attr_bits == osThreadJoinable)) {
-		status = osOK;
-	} else {
-		status = osErrorResource;
-	}
-
-	return status;
+	ret = k_thread_join(&tid->z_thread, K_FOREVER);
+	return (ret == 0) ? osOK : osErrorResource;
 }
 
 /**
@@ -504,13 +461,11 @@ osStatus_t osThreadJoin(osThreadId_t thread_id)
  */
 __NO_RETURN void osThreadExit(void)
 {
-	struct cv2_thread *tid;
+	struct cmsis_rtos_thread_cb *tid;
 
 	__ASSERT(!k_is_in_isr(), "");
 	tid = osThreadGetId();
 
-	k_sem_give(&tid->join_guard);
-
 	k_thread_abort((k_tid_t)&tid->z_thread);
 
 	CODE_UNREACHABLE;
@@ -521,7 +476,7 @@ __NO_RETURN void osThreadExit(void)
  */
 osStatus_t osThreadTerminate(osThreadId_t thread_id)
 {
-	struct cv2_thread *tid = (struct cv2_thread *)thread_id;
+	struct cmsis_rtos_thread_cb *tid = (struct cmsis_rtos_thread_cb *)thread_id;
 
 	if ((tid == NULL) || (is_cmsis_rtos_v2_thread(tid) == NULL)) {
 		return osErrorParameter;
@@ -535,13 +490,10 @@ osStatus_t osThreadTerminate(osThreadId_t thread_id)
 		return osErrorResource;
 	}
 
-	k_sem_give(&tid->join_guard);
-
 	k_thread_abort((k_tid_t)&tid->z_thread);
 	return osOK;
 }
 
-
 /**
  * @brief Get number of active threads.
  */
diff --git a/subsys/portability/cmsis_rtos_v2/thread_flags.c b/subsys/portability/cmsis_rtos_v2/thread_flags.c
index 2ef8cea513c..3018bd8224f 100644
--- a/subsys/portability/cmsis_rtos_v2/thread_flags.c
+++ b/subsys/portability/cmsis_rtos_v2/thread_flags.c
@@ -5,9 +5,10 @@
  */
 
 #include <zephyr/kernel_structs.h>
+#include <zephyr/portability/cmsis_types.h>
 #include "wrapper.h"
 
-#define DONT_CARE               (0)
+#define DONT_CARE (0)
 
 /**
  * @brief Set the specified Thread Flags of a thread.
@@ -15,10 +16,10 @@
 uint32_t osThreadFlagsSet(osThreadId_t thread_id, uint32_t flags)
 {
 	unsigned int key;
-	struct cv2_thread *tid = (struct cv2_thread *)thread_id;
+	struct cmsis_rtos_thread_cb *tid = (struct cmsis_rtos_thread_cb *)thread_id;
 
-	if ((thread_id == NULL) || (is_cmsis_rtos_v2_thread(thread_id) == NULL)
-	    || (flags & 0x80000000)) {
+	if ((thread_id == NULL) || (is_cmsis_rtos_v2_thread(thread_id) == NULL) ||
+	    (flags & 0x80000000)) {
 		return osFlagsErrorParameter;
 	}
 
@@ -36,13 +37,13 @@ uint32_t osThreadFlagsSet(osThreadId_t thread_id, uint32_t flags)
  */
 uint32_t osThreadFlagsGet(void)
 {
-	struct cv2_thread *tid;
+	struct cmsis_rtos_thread_cb *tid;
 
 	if (k_is_in_isr()) {
 		return 0;
 	}
 
-	tid = (struct cv2_thread *)osThreadGetId();
+	tid = (struct cmsis_rtos_thread_cb *)osThreadGetId();
 	if (tid == NULL) {
 		return 0;
 	} else {
@@ -55,7 +56,7 @@ uint32_t osThreadFlagsGet(void)
  */
 uint32_t osThreadFlagsClear(uint32_t flags)
 {
-	struct cv2_thread *tid;
+	struct cmsis_rtos_thread_cb *tid;
 	int sig, key;
 
 	if (k_is_in_isr()) {
@@ -66,7 +67,7 @@ uint32_t osThreadFlagsClear(uint32_t flags)
 		return osFlagsErrorParameter;
 	}
 
-	tid = (struct cv2_thread *)osThreadGetId();
+	tid = (struct cmsis_rtos_thread_cb *)osThreadGetId();
 	if (tid == NULL) {
 		return osFlagsErrorUnknown;
 	}
@@ -85,7 +86,7 @@ uint32_t osThreadFlagsClear(uint32_t flags)
  */
 uint32_t osThreadFlagsWait(uint32_t flags, uint32_t options, uint32_t timeout)
 {
-	struct cv2_thread *tid;
+	struct cmsis_rtos_thread_cb *tid;
 	int retval, key;
 	uint32_t sig;
 	uint32_t time_delta_ms, timeout_ms = k_ticks_to_ms_floor64(timeout);
@@ -99,7 +100,7 @@ uint32_t osThreadFlagsWait(uint32_t flags, uint32_t options, uint32_t timeout)
 		return osFlagsErrorParameter;
 	}
 
-	tid = (struct cv2_thread *)osThreadGetId();
+	tid = (struct cmsis_rtos_thread_cb *)osThreadGetId();
 	if (tid == NULL) {
 		return osFlagsErrorUnknown;
 	}
@@ -108,6 +109,24 @@ uint32_t osThreadFlagsWait(uint32_t flags, uint32_t options, uint32_t timeout)
 
 		time_stamp_start = (uint64_t)k_cycle_get_32();
 
+		sig = tid->signal_results & flags;
+
+		if (options & osFlagsWaitAll) {
+			/* Check if all events we are waiting on have
+			 * been signalled
+			 */
+			if (sig == flags) {
+				break;
+			}
+		} else {
+			/* Check if any events we are waiting on have
+			 * been signalled
+			 */
+			if (sig != 0) {
+				break;
+			}
+		}
+
 		switch (timeout) {
 		case 0:
 			retval = k_poll(&tid->poll_event, 1, K_NO_WAIT);
@@ -116,8 +135,7 @@ uint32_t osThreadFlagsWait(uint32_t flags, uint32_t options, uint32_t timeout)
 			retval = k_poll(&tid->poll_event, 1, K_FOREVER);
 			break;
 		default:
-			retval = k_poll(&tid->poll_event, 1,
-					K_MSEC(timeout_ms));
+			retval = k_poll(&tid->poll_event, 1, K_MSEC(timeout_ms));
 			break;
 		}
 
@@ -132,49 +150,33 @@ uint32_t osThreadFlagsWait(uint32_t flags, uint32_t options, uint32_t timeout)
 
 		__ASSERT(tid->poll_event.state == K_POLL_STATE_SIGNALED,
 			 "event state not signalled!");
-		__ASSERT(tid->poll_event.signal->signaled == 1U,
-			 "event signaled is not 1");
+		__ASSERT(tid->poll_event.signal->signaled == 1U, "event signaled is not 1");
 
 		/* Reset the states to facilitate the next trigger */
 		tid->poll_event.signal->signaled = 0U;
 		tid->poll_event.state = K_POLL_STATE_NOT_READY;
 
-		if (options & osFlagsWaitAll) {
-			/* Check if all events we are waiting on have
-			 * been signalled
-			 */
-			if ((tid->signal_results & flags) == flags) {
-				break;
-			}
+		/* If we need to wait on more signals, we need to
+		 * adjust the timeout value accordingly based on
+		 * the time that has already elapsed.
+		 */
+		hwclk_cycles_delta = (uint64_t)k_cycle_get_32() - time_stamp_start;
 
-			/* If we need to wait on more signals, we need to
-			 * adjust the timeout value accordingly based on
-			 * the time that has already elapsed.
-			 */
-			hwclk_cycles_delta =
-				(uint64_t)k_cycle_get_32() - time_stamp_start;
-
-			time_delta_ns =
-				(uint32_t)k_cyc_to_ns_floor64(hwclk_cycles_delta);
+		time_delta_ns = (uint32_t)k_cyc_to_ns_floor64(hwclk_cycles_delta);
 
-			time_delta_ms = (uint32_t)time_delta_ns / NSEC_PER_MSEC;
+		time_delta_ms = (uint32_t)time_delta_ns / NSEC_PER_MSEC;
 
-			if (timeout_ms > time_delta_ms) {
-				timeout_ms -= time_delta_ms;
-			} else {
-				timeout_ms = 0U;
-			}
+		if (timeout_ms > time_delta_ms) {
+			timeout_ms -= time_delta_ms;
 		} else {
-			break;
+			timeout_ms = 0U;
 		}
 	}
 
-	sig = tid->signal_results;
 	if (!(options & osFlagsNoClear)) {
-
 		/* Clear signal flags as the thread is ready now */
 		key = irq_lock();
-		tid->signal_results &= ~(flags);
+		tid->signal_results &= ~(sig);
 		irq_unlock(key);
 	}
 
diff --git a/subsys/portability/cmsis_rtos_v2/timer.c b/subsys/portability/cmsis_rtos_v2/timer.c
index abdb1e7bc6d..981917d5b28 100644
--- a/subsys/portability/cmsis_rtos_v2/timer.c
+++ b/subsys/portability/cmsis_rtos_v2/timer.c
@@ -5,15 +5,15 @@
  */
 
 #include <zephyr/kernel.h>
+#include <zephyr/portability/cmsis_types.h>
 #include <string.h>
-#include "wrapper.h"
 
-#define ACTIVE 1
+#define ACTIVE     1
 #define NOT_ACTIVE 0
 
 static void zephyr_timer_wrapper(struct k_timer *timer);
 
-K_MEM_SLAB_DEFINE(cv2_timer_slab, sizeof(struct cv2_timer),
+K_MEM_SLAB_DEFINE(cmsis_rtos_timer_cb_slab, sizeof(struct cmsis_rtos_timer_cb),
 		  CONFIG_CMSIS_V2_TIMER_MAX_COUNT, 4);
 
 static const osTimerAttr_t init_timer_attrs = {
@@ -25,19 +25,19 @@ static const osTimerAttr_t init_timer_attrs = {
 
 static void zephyr_timer_wrapper(struct k_timer *timer)
 {
-	struct cv2_timer *cm_timer;
+	struct cmsis_rtos_timer_cb *cm_timer;
 
-	cm_timer = CONTAINER_OF(timer, struct cv2_timer, z_timer);
+	cm_timer = CONTAINER_OF(timer, struct cmsis_rtos_timer_cb, z_timer);
 	(cm_timer->callback_function)(cm_timer->arg);
 }
 
 /**
  * @brief Create a Timer
  */
-osTimerId_t osTimerNew(osTimerFunc_t func, osTimerType_t type,
-		       void *argument, const osTimerAttr_t *attr)
+osTimerId_t osTimerNew(osTimerFunc_t func, osTimerType_t type, void *argument,
+		       const osTimerAttr_t *attr)
 {
-	struct cv2_timer *timer;
+	struct cmsis_rtos_timer_cb *timer;
 
 	if (type != osTimerOnce && type != osTimerPeriodic) {
 		return NULL;
@@ -51,11 +51,14 @@ osTimerId_t osTimerNew(osTimerFunc_t func, osTimerType_t type,
 		attr = &init_timer_attrs;
 	}
 
-	if (k_mem_slab_alloc(&cv2_timer_slab, (void **)&timer, K_MSEC(100)) == 0) {
-		(void)memset(timer, 0, sizeof(struct cv2_timer));
-	} else {
+	if (attr->cb_mem != NULL) {
+		__ASSERT(attr->cb_size == sizeof(struct cmsis_rtos_timer_cb), "Invalid cb_size\n");
+		timer = (struct cmsis_rtos_timer_cb *)attr->cb_mem;
+	} else if (k_mem_slab_alloc(&cmsis_rtos_timer_cb_slab, (void **)&timer, K_MSEC(100)) != 0) {
 		return NULL;
 	}
+	(void)memset(timer, 0, sizeof(struct cmsis_rtos_timer_cb));
+	timer->is_cb_dynamic_allocation = attr->cb_mem == NULL;
 
 	timer->callback_function = func;
 	timer->arg = argument;
@@ -64,12 +67,7 @@ osTimerId_t osTimerNew(osTimerFunc_t func, osTimerType_t type,
 
 	k_timer_init(&timer->z_timer, zephyr_timer_wrapper, NULL);
 
-	if (attr->name == NULL) {
-		strncpy(timer->name, init_timer_attrs.name,
-			sizeof(timer->name) - 1);
-	} else {
-		strncpy(timer->name, attr->name, sizeof(timer->name) - 1);
-	}
+	timer->name = (attr->name == NULL) ? init_timer_attrs.name : attr->name;
 
 	return (osTimerId_t)timer;
 }
@@ -79,7 +77,7 @@ osTimerId_t osTimerNew(osTimerFunc_t func, osTimerType_t type,
  */
 osStatus_t osTimerStart(osTimerId_t timer_id, uint32_t ticks)
 {
-	struct cv2_timer *timer = (struct cv2_timer *)timer_id;
+	struct cmsis_rtos_timer_cb *timer = (struct cmsis_rtos_timer_cb *)timer_id;
 
 	if (timer == NULL) {
 		return osErrorParameter;
@@ -92,8 +90,7 @@ osStatus_t osTimerStart(osTimerId_t timer_id, uint32_t ticks)
 	if (timer->type == osTimerOnce) {
 		k_timer_start(&timer->z_timer, K_TICKS(ticks), K_NO_WAIT);
 	} else if (timer->type == osTimerPeriodic) {
-		k_timer_start(&timer->z_timer,
-			      K_TICKS(ticks), K_TICKS(ticks));
+		k_timer_start(&timer->z_timer, K_TICKS(ticks), K_TICKS(ticks));
 	}
 
 	timer->status = ACTIVE;
@@ -105,7 +102,7 @@ osStatus_t osTimerStart(osTimerId_t timer_id, uint32_t ticks)
  */
 osStatus_t osTimerStop(osTimerId_t timer_id)
 {
-	struct cv2_timer *timer = (struct cv2_timer *)timer_id;
+	struct cmsis_rtos_timer_cb *timer = (struct cmsis_rtos_timer_cb *)timer_id;
 
 	if (timer == NULL) {
 		return osErrorParameter;
@@ -129,7 +126,7 @@ osStatus_t osTimerStop(osTimerId_t timer_id)
  */
 osStatus_t osTimerDelete(osTimerId_t timer_id)
 {
-	struct cv2_timer *timer = (struct cv2_timer *) timer_id;
+	struct cmsis_rtos_timer_cb *timer = (struct cmsis_rtos_timer_cb *)timer_id;
 
 	if (timer == NULL) {
 		return osErrorParameter;
@@ -144,21 +141,23 @@ osStatus_t osTimerDelete(osTimerId_t timer_id)
 		timer->status = NOT_ACTIVE;
 	}
 
-	k_mem_slab_free(&cv2_timer_slab, (void *)timer);
+	if (timer->is_cb_dynamic_allocation) {
+		k_mem_slab_free(&cmsis_rtos_timer_cb_slab, (void *)timer);
+	}
 	return osOK;
 }
 
 /**
  * @brief Get name of a timer.
+ * This function may be called from Interrupt Service Routines.
  */
 const char *osTimerGetName(osTimerId_t timer_id)
 {
-	struct cv2_timer *timer = (struct cv2_timer *)timer_id;
+	struct cmsis_rtos_timer_cb *timer = (struct cmsis_rtos_timer_cb *)timer_id;
 
-	if (k_is_in_isr() || (timer == NULL)) {
+	if (timer == NULL) {
 		return NULL;
 	}
-
 	return timer->name;
 }
 
@@ -167,7 +166,7 @@ const char *osTimerGetName(osTimerId_t timer_id)
  */
 uint32_t osTimerIsRunning(osTimerId_t timer_id)
 {
-	struct cv2_timer *timer = (struct cv2_timer *)timer_id;
+	struct cmsis_rtos_timer_cb *timer = (struct cmsis_rtos_timer_cb *)timer_id;
 
 	if (k_is_in_isr() || (timer == NULL)) {
 		return 0;
diff --git a/subsys/portability/cmsis_rtos_v2/wrapper.h b/subsys/portability/cmsis_rtos_v2/wrapper.h
index 41e9e42f243..0d3f6e33722 100644
--- a/subsys/portability/cmsis_rtos_v2/wrapper.h
+++ b/subsys/portability/cmsis_rtos_v2/wrapper.h
@@ -8,68 +8,16 @@
 #define __WRAPPER_H__
 
 #include <zephyr/kernel.h>
-#include <cmsis_os2.h>
+#include <zephyr/portability/cmsis_types.h>
+#include <zephyr/portability/cmsis_os2.h>
 
 #ifndef TRUE
-#define TRUE    1
+#define TRUE 1
 #endif
 #ifndef FALSE
-#define FALSE   0
+#define FALSE 0
 #endif
 
-struct cv2_thread {
-	sys_dnode_t node;
-	struct k_thread z_thread;
-	struct k_poll_signal poll_signal;
-	struct k_poll_event poll_event;
-	uint32_t signal_results;
-	char name[16];
-	uint32_t attr_bits;
-	struct k_sem join_guard;
-	char has_joined;
-};
-
-struct cv2_timer {
-	struct k_timer z_timer;
-	osTimerType_t type;
-	uint32_t status;
-	char name[16];
-	void (*callback_function)(void *argument);
-	void *arg;
-};
-
-struct cv2_mutex {
-	struct k_mutex z_mutex;
-	char name[16];
-	uint32_t state;
-};
-
-struct cv2_sem {
-	struct k_sem z_semaphore;
-	char name[16];
-};
-
-struct cv2_mslab {
-	struct k_mem_slab z_mslab;
-	void *pool;
-	char is_dynamic_allocation;
-	char name[16];
-};
-
-struct cv2_msgq {
-	struct k_msgq z_msgq;
-	void *pool;
-	char is_dynamic_allocation;
-	char name[16];
-};
-
-struct cv2_event_flags {
-	struct k_poll_signal poll_signal;
-	struct k_poll_event poll_event;
-	uint32_t signal_results;
-	char name[16];
-};
-
 extern osThreadId_t get_cmsis_thread_id(k_tid_t tid);
 extern void *is_cmsis_rtos_v2_thread(void *thread_id);
 
diff --git a/subsys/profiling/perf/backends/perf_riscv.c b/subsys/profiling/perf/backends/perf_riscv.c
index 2259e1c60db..8eb1f1828b3 100644
--- a/subsys/profiling/perf/backends/perf_riscv.c
+++ b/subsys/profiling/perf/backends/perf_riscv.c
@@ -5,6 +5,7 @@
  */
 
 #include <zephyr/kernel.h>
+#include <zephyr/linker/linker-defs.h>
 
 static bool valid_stack(uintptr_t addr, k_tid_t current)
 {
@@ -14,9 +15,7 @@ static bool valid_stack(uintptr_t addr, k_tid_t current)
 
 static inline bool in_text_region(uintptr_t addr)
 {
-	extern uintptr_t __text_region_start, __text_region_end;
-
-	return (addr >= (uintptr_t)&__text_region_start) && (addr < (uintptr_t)&__text_region_end);
+	return (addr >= (uintptr_t)__text_region_start) && (addr < (uintptr_t)__text_region_end);
 }
 
 /*
@@ -34,7 +33,7 @@ size_t arch_perf_current_stack_trace(uintptr_t *buf, size_t size)
 
 	/*
 	 * In riscv (arch/riscv/core/isr.S) ra, ip($mepc) and fp($s0) are saved
-	 * at the beginning of _isr_wrapper in order, specified by z_arch_esf_t.
+	 * at the beginning of _isr_wrapper in order, specified by struct arch_esf.
 	 * Then, before calling interruption handler, core switch $sp to
 	 * _current_cpu->irq_stack and save $sp with offset -16 on irq stack
 	 *
diff --git a/subsys/profiling/perf/backends/perf_x86.c b/subsys/profiling/perf/backends/perf_x86.c
index e62ad64b74a..5bc12c0b77b 100644
--- a/subsys/profiling/perf/backends/perf_x86.c
+++ b/subsys/profiling/perf/backends/perf_x86.c
@@ -6,6 +6,7 @@
  */
 
 #include <zephyr/kernel.h>
+#include <zephyr/linker/linker-defs.h>
 
 static bool valid_stack(uintptr_t addr, k_tid_t current)
 {
@@ -15,9 +16,7 @@ static bool valid_stack(uintptr_t addr, k_tid_t current)
 
 static inline bool in_text_region(uintptr_t addr)
 {
-	extern uintptr_t __text_region_start, __text_region_end;
-
-	return (addr >= (uintptr_t)&__text_region_start) && (addr < (uintptr_t)&__text_region_end);
+	return (addr >= (uintptr_t)__text_region_start) && (addr < (uintptr_t)__text_region_end);
 }
 
 /* interruption stack frame */
diff --git a/subsys/profiling/perf/backends/perf_x86_64.c b/subsys/profiling/perf/backends/perf_x86_64.c
index 84e45024c3c..fa6c77f527b 100644
--- a/subsys/profiling/perf/backends/perf_x86_64.c
+++ b/subsys/profiling/perf/backends/perf_x86_64.c
@@ -6,6 +6,7 @@
  */
 
 #include <zephyr/kernel.h>
+#include <zephyr/linker/linker-defs.h>
 
 static bool valid_stack(uintptr_t addr, k_tid_t current)
 {
@@ -15,9 +16,7 @@ static bool valid_stack(uintptr_t addr, k_tid_t current)
 
 static inline bool in_text_region(uintptr_t addr)
 {
-	extern uintptr_t __text_region_start, __text_region_end;
-
-	return (addr >= (uintptr_t)&__text_region_start) && (addr < (uintptr_t)&__text_region_end);
+	return (addr >= (uintptr_t)__text_region_start) && (addr < (uintptr_t)__text_region_end);
 }
 
 /*
diff --git a/subsys/random/random_ctr_drbg.c b/subsys/random/random_ctr_drbg.c
index 697c29da58b..25f563e3040 100644
--- a/subsys/random/random_ctr_drbg.c
+++ b/subsys/random/random_ctr_drbg.c
@@ -24,7 +24,7 @@
 static const struct device *entropy_dev;
 static const unsigned char drbg_seed[] = CONFIG_CS_CTR_DRBG_PERSONALIZATION;
 static bool ctr_initialised;
-static struct k_mutex ctr_lock;
+static K_MUTEX_DEFINE(ctr_lock);
 
 static mbedtls_ctr_drbg_context ctr_ctx;
 
diff --git a/subsys/rtio/Kconfig.workq b/subsys/rtio/Kconfig.workq
index af852204156..de9106c91eb 100644
--- a/subsys/rtio/Kconfig.workq
+++ b/subsys/rtio/Kconfig.workq
@@ -4,6 +4,7 @@
 config RTIO_WORKQ
 	bool "RTIO Work-queues service to process Sync operations"
 	select SCHED_DEADLINE
+	select P4WQ_INIT_STAGE_EARLY
 	select RTIO_CONSUME_SEM
 	help
 	  Enable RTIO Work-queues to allow processing synchronous operations
@@ -21,6 +22,7 @@ config RTIO_WORKQ_STACK_SIZE
 
 config RTIO_WORKQ_THREADS_POOL
 	int "Number of threads to use for processing work-items"
+	default 2 if SPI_RTIO || I2C_RTIO || I3C_RTIO
 	default 1
 
 config RTIO_WORKQ_POOL_ITEMS
diff --git a/subsys/rtio/rtio_executor.c b/subsys/rtio/rtio_executor.c
index 49347b34f54..e4ad8fe516a 100644
--- a/subsys/rtio/rtio_executor.c
+++ b/subsys/rtio/rtio_executor.c
@@ -84,6 +84,10 @@ void rtio_executor_submit(struct rtio *r)
 				    "Expected chained or transaction flag, not both");
 #endif
 			node = mpsc_pop(&iodev_sqe->r->sq);
+
+			__ASSERT(node != NULL,
+				    "Expected a valid submission in the queue while in a transaction or chain");
+
 			next = CONTAINER_OF(node, struct rtio_iodev_sqe, q);
 
 			/* If the current submission was cancelled before submit,
diff --git a/subsys/rtio/rtio_workq.c b/subsys/rtio/rtio_workq.c
index b063ead71a4..f04acb46525 100644
--- a/subsys/rtio/rtio_workq.c
+++ b/subsys/rtio/rtio_workq.c
@@ -11,15 +11,24 @@
 #define RTIO_WORKQ_PRIO_HIGH		RTIO_WORKQ_PRIO_MED - 1
 #define RTIO_WORKQ_PRIO_LOW		RTIO_WORKQ_PRIO_MED + 1
 
-K_P4WQ_DEFINE(rtio_workq,
-	      CONFIG_RTIO_WORKQ_THREADS_POOL,
-	      CONFIG_RTIO_WORKQ_STACK_SIZE);
-
 K_MEM_SLAB_DEFINE_STATIC(rtio_work_items_slab,
 			 sizeof(struct rtio_work_req),
 			 CONFIG_RTIO_WORKQ_POOL_ITEMS,
 			 4);
 
+static void rtio_work_req_done_handler(struct k_p4wq_work *work)
+{
+	struct rtio_work_req *req = CONTAINER_OF(work,
+						 struct rtio_work_req,
+						 work);
+	k_mem_slab_free(&rtio_work_items_slab, req);
+}
+
+K_P4WQ_DEFINE_WITH_DONE_HANDLER(rtio_workq,
+	      CONFIG_RTIO_WORKQ_THREADS_POOL,
+	      CONFIG_RTIO_WORKQ_STACK_SIZE,
+		  rtio_work_req_done_handler);
+
 static void rtio_work_handler(struct k_p4wq_work *work)
 {
 	struct rtio_work_req *req = CONTAINER_OF(work,
@@ -28,8 +37,6 @@ static void rtio_work_handler(struct k_p4wq_work *work)
 	struct rtio_iodev_sqe *iodev_sqe = req->iodev_sqe;
 
 	req->handler(iodev_sqe);
-
-	k_mem_slab_free(&rtio_work_items_slab, req);
 }
 
 struct rtio_work_req *rtio_work_req_alloc(void)
diff --git a/subsys/sd/mmc.c b/subsys/sd/mmc.c
index 8ea0b5746d7..02216d3700a 100644
--- a/subsys/sd/mmc.c
+++ b/subsys/sd/mmc.c
@@ -111,16 +111,6 @@ int mmc_card_init(struct sd_card *card)
 		return -EINVAL;
 	}
 
-	/* Probe to see if card is an MMC card */
-	ret = mmc_send_op_cond(card, ocr_arg);
-	if (ret) {
-		return ret;
-	}
-	/* Card is MMC card if no error
-	 * (Only MMC protocol supports CMD1)
-	 */
-	card->type = CARD_MMC;
-
 	/* Set OCR Arguments */
 	if (card->host_props.host_caps.vol_180_support) {
 		ocr_arg |= MMC_OCR_VDD170_195FLAG;
@@ -137,7 +127,7 @@ int mmc_card_init(struct sd_card *card)
 	/* CMD1 */
 	ret = mmc_send_op_cond(card, ocr_arg);
 	if (ret) {
-		LOG_ERR("Failed to query card OCR");
+		LOG_DBG("Failed to query card OCR");
 		return ret;
 	}
 
@@ -221,9 +211,11 @@ static int mmc_send_op_cond(struct sd_card *card, int ocr)
 			/* OCR failed */
 			return ret;
 		}
-		if (ocr == 0) {
-			/* Just probing */
-			return 0;
+		if (retries == 0) {
+			/* Card is MMC card if no error
+			 * (Only MMC protocol supports CMD1)
+			 */
+			card->type = CARD_MMC;
 		}
 		sd_delay(10);
 	}
diff --git a/subsys/sd/sd.c b/subsys/sd/sd.c
index 02190397966..d8c28914380 100644
--- a/subsys/sd/sd.c
+++ b/subsys/sd/sd.c
@@ -215,7 +215,7 @@ static int sd_command_init(struct sd_card *card)
 	if (!sdmmc_card_init(card)) {
 		return 0;
 	}
-#endif /* CONFIG_SDIO_STACK */
+#endif /* CONFIG_SDMMC_STACK */
 #ifdef CONFIG_MMC_STACK
 	ret = sd_idle(card);
 	if (ret) {
diff --git a/subsys/secure_storage/CMakeLists.txt b/subsys/secure_storage/CMakeLists.txt
index a15c1b24f44..ef1e59364d1 100644
--- a/subsys/secure_storage/CMakeLists.txt
+++ b/subsys/secure_storage/CMakeLists.txt
@@ -12,10 +12,10 @@ zephyr_include_directories(
 
 # Make the secure_storage headers available to the application only when it's implementing the relevant APIs.
 function(make_available header)
-  if (NOT header STREQUAL "common.h")
+  if(NOT header STREQUAL "common.h")
     make_available(common.h)
   endif()
-  if ((header MATCHES "^its") AND NOT (header STREQUAL "its/common.h"))
+  if((header MATCHES "^its") AND NOT (header STREQUAL "its/common.h"))
     make_available(its/common.h)
   endif()
   configure_file(include/internal/zephyr/secure_storage/${header}
@@ -23,26 +23,30 @@ function(make_available header)
                  COPYONLY)
 endfunction()
 
-if (CONFIG_SECURE_STORAGE_ITS_IMPLEMENTATION_CUSTOM)
+if(CONFIG_SECURE_STORAGE_ITS_IMPLEMENTATION_CUSTOM)
   make_available(its.h)
 endif()
 
-if (CONFIG_SECURE_STORAGE_PS_IMPLEMENTATION_CUSTOM)
+if(CONFIG_SECURE_STORAGE_PS_IMPLEMENTATION_CUSTOM)
   make_available(ps.h)
 endif()
 
-if (CONFIG_SECURE_STORAGE_ITS_TRANSFORM_IMPLEMENTATION_CUSTOM
+if(CONFIG_SECURE_STORAGE_ITS_TRANSFORM_IMPLEMENTATION_CUSTOM
     OR (CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_CUSTOM
         AND CONFIG_SECURE_STORAGE_ITS_TRANSFORM_MODULE))
   make_available(its/transform.h)
 endif()
 
-if (CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_CUSTOM)
+if(CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_CUSTOM)
   make_available(its/store.h)
 endif()
 
-if (CONFIG_SECURE_STORAGE_ITS_TRANSFORM_AEAD_SCHEME_CUSTOM
+if(CONFIG_SECURE_STORAGE_ITS_TRANSFORM_AEAD_SCHEME_CUSTOM
  OR CONFIG_SECURE_STORAGE_ITS_TRANSFORM_AEAD_KEY_PROVIDER_CUSTOM
  OR CONFIG_SECURE_STORAGE_ITS_TRANSFORM_AEAD_NONCE_PROVIDER_CUSTOM)
   make_available(its/transform/aead_get.h)
 endif()
+
+if(CONFIG_SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_CUSTOM)
+  make_available(its/store/settings_get.h)
+endif()
diff --git a/subsys/secure_storage/Kconfig b/subsys/secure_storage/Kconfig
index 11986cf0747..3fe8eb0f76a 100644
--- a/subsys/secure_storage/Kconfig
+++ b/subsys/secure_storage/Kconfig
@@ -66,7 +66,6 @@ endif
 
 menuconfig SECURE_STORAGE_ITS_STORE_MODULE
 	bool "ITS store module"
-	imply FLASH # for FLASH_HAS_DRIVER_ENABLED
 	help
 	  The module that handles the storage/retrieval of the ITS data to/from NVM.
 	  Zephyr's ITS implementation calls into it.
diff --git a/subsys/secure_storage/Kconfig.its_store b/subsys/secure_storage/Kconfig.its_store
index 05ebf72ca8f..ccd15b968a7 100644
--- a/subsys/secure_storage/Kconfig.its_store
+++ b/subsys/secure_storage/Kconfig.its_store
@@ -14,7 +14,7 @@ config SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_ZMS
 	depends on FLASH_HAS_DRIVER_ENABLED \
 	 && $(dt_path_enabled,$(DT_ITS_PARTITION)) \
 	 && $(dt_node_has_compat,$(dt_node_parent,$(DT_ITS_PARTITION)),fixed-partitions)
-	select ZMS
+	depends on ZMS
 	help
 	  This implementation of the ITS store module makes direct use of ZMS for storage.
 	  It needs a `secure_storage_its_partition` devicetree chosen property that points
@@ -31,9 +31,7 @@ config SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_SETTINGS
 	     && $(dt_node_has_compat,$(dt_node_parent,$(DT_SETTINGS_PARTITIION)),fixed-partitions))\
 	  || ($(dt_path_enabled,$(DT_STORAGE_PARTITION)) \
 	      && $(dt_node_has_compat,$(dt_node_parent,$(DT_STORAGE_PARTITION)),fixed-partitions)))
-	imply FLASH_MAP
-	imply NVS
-	select SETTINGS
+	depends on SETTINGS
 
 config SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_NONE
 	bool "No ITS store module implementation"
@@ -62,8 +60,25 @@ endif # SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_ZMS
 
 if SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_SETTINGS
 
+config SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_CUSTOM
+	bool "Custom naming scheme for the stored settings"
+	help
+	  This allows to use custom names for the settings that the implementation uses
+	  instead of the default naming scheme.
+	  When enabling this, implement the secure_storage_its_store_settings_get_name()
+	  function declared in <zephyr/secure_storage/its/store/settings_get.h>
+	  and set CONFIG_SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_MAX_LEN appropriately.
+	  The header file is made available when this Kconfig option is enabled.
+
 config SECURE_STORAGE_ITS_STORE_SETTINGS_PREFIX
 	string "Subtree in which to store the settings, with a trailing slash. Can be empty."
 	default "its/"
+	depends on !SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_CUSTOM
+
+config SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_MAX_LEN
+	int "Maximum setting name length"
+	range 2 64
+	default 22 if !SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_CUSTOM
+	default 0
 
 endif # SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_SETTINGS
diff --git a/subsys/secure_storage/include/internal/zephyr/secure_storage/its/store/settings_get.h b/subsys/secure_storage/include/internal/zephyr/secure_storage/its/store/settings_get.h
new file mode 100644
index 00000000000..028cc35e26f
--- /dev/null
+++ b/subsys/secure_storage/include/internal/zephyr/secure_storage/its/store/settings_get.h
@@ -0,0 +1,29 @@
+/* Copyright (c) 2024 Nordic Semiconductor
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef SECURE_STORAGE_ITS_STORE_SETTINGS_GET_H
+#define SECURE_STORAGE_ITS_STORE_SETTINGS_GET_H
+
+/** @file zephyr/secure_storage/its/store/settings_get.h The settings ITS store module API.
+ *
+ * The functions declared in this header allow customization
+ * of the settings implementation of the ITS store module.
+ * They are not meant to be called directly other than by the settings ITS store module.
+ * This header file may and must be included when providing a custom implementation of one
+ * or more of these functions (@kconfig{CONFIG_SECURE_STORAGE_ITS_STORE_SETTINGS_*_CUSTOM}).
+ */
+#include <zephyr/secure_storage/its/common.h>
+
+enum { SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_BUF_SIZE
+	= CONFIG_SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_MAX_LEN + 1 };
+
+/** @brief Returns the setting name to use for an ITS entry.
+ *
+ * @param[in]  uid  The UID of the ITS entry for which the setting name is used.
+ * @param[out] name The setting name.
+ */
+void secure_storage_its_store_settings_get_name(
+	secure_storage_its_uid_t uid,
+	char name[static SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_BUF_SIZE]);
+
+#endif
diff --git a/subsys/secure_storage/include/internal/zephyr/secure_storage/its/transform/aead_get.h b/subsys/secure_storage/include/internal/zephyr/secure_storage/its/transform/aead_get.h
index 071c74c029e..0172c15b1d5 100644
--- a/subsys/secure_storage/include/internal/zephyr/secure_storage/its/transform/aead_get.h
+++ b/subsys/secure_storage/include/internal/zephyr/secure_storage/its/transform/aead_get.h
@@ -9,7 +9,7 @@
  * The functions declared in this header allow customization
  * of the AEAD implementation of the ITS transform module.
  * They are not meant to be called directly other than by the AEAD ITS transform module.
- * This header may be included when providing a custom implementation of one
+ * This header file may and must be included when providing a custom implementation of one
  * or more of these functions (@kconfig{CONFIG_SECURE_STORAGE_ITS_TRANSFORM_AEAD_*_CUSTOM}).
  */
 #include <zephyr/secure_storage/its/common.h>
@@ -24,7 +24,7 @@ void secure_storage_its_transform_aead_get_scheme(psa_key_type_t *key_type, psa_
 
 /** @brief Returns the encryption key to use for an ITS entry's AEAD operations.
  *
- * @param[in]  uid The UID of the ITS entry for whom the returned key is used.
+ * @param[in]  uid The UID of the ITS entry for which the key is used.
  * @param[out] key The encryption key.
  *
  * @return `PSA_SUCCESS` on success, anything else on failure.
diff --git a/subsys/secure_storage/src/its/CMakeLists.txt b/subsys/secure_storage/src/its/CMakeLists.txt
index ddb0a0265ce..f8d31f1dfed 100644
--- a/subsys/secure_storage/src/its/CMakeLists.txt
+++ b/subsys/secure_storage/src/its/CMakeLists.txt
@@ -8,8 +8,8 @@ zephyr_library_sources_ifdef(CONFIG_SECURE_STORAGE_ITS_TRANSFORM_IMPLEMENTATION_
   transform/aead.c
   transform/aead_get.c
 )
-if (NOT CONFIG_SECURE_STORAGE_ITS_TRANSFORM_AEAD_NO_INSECURE_KEY_WARNING)
-  if (CONFIG_SECURE_STORAGE_ITS_TRANSFORM_AEAD_KEY_PROVIDER_DEVICE_ID_HASH)
+if(NOT CONFIG_SECURE_STORAGE_ITS_TRANSFORM_AEAD_NO_INSECURE_KEY_WARNING)
+  if(CONFIG_SECURE_STORAGE_ITS_TRANSFORM_AEAD_KEY_PROVIDER_DEVICE_ID_HASH)
     message(WARNING "
       The PSA ITS encryption key provider in use generates keys by hashing the device ID
       retrieved through the HW info API. This is not necessarily secure as the device ID may be
@@ -30,7 +30,7 @@ zephyr_library_sources_ifdef(CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_ZMS
 zephyr_library_sources_ifdef(CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_SETTINGS
   store/settings.c
 )
-if (CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_NONE)
+if(CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_NONE)
   message(ERROR "
     The secure storage ITS module is enabled but has no implementation.
     (CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_NONE)
diff --git a/subsys/secure_storage/src/its/store/settings.c b/subsys/secure_storage/src/its/store/settings.c
index e9725761201..f13ed497ae5 100644
--- a/subsys/secure_storage/src/its/store/settings.c
+++ b/subsys/secure_storage/src/its/store/settings.c
@@ -2,6 +2,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <zephyr/secure_storage/its/store.h>
+#include <zephyr/secure_storage/its/store/settings_get.h>
 #include <zephyr/init.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/settings/settings.h>
@@ -26,26 +27,37 @@ static int init_settings_subsys(void)
 }
 SYS_INIT(init_settings_subsys, APPLICATION, CONFIG_APPLICATION_INIT_PRIORITY);
 
-enum { NAME_BUF_SIZE = sizeof(CONFIG_SECURE_STORAGE_ITS_STORE_SETTINGS_PREFIX) - 1
-		       + 2 * (sizeof(secure_storage_its_uid_t) + 1) };
-BUILD_ASSERT(NAME_BUF_SIZE <= SETTINGS_MAX_NAME_LEN + 1);
+BUILD_ASSERT(CONFIG_SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_MAX_LEN <= SETTINGS_MAX_NAME_LEN);
 
-static void make_name(secure_storage_its_uid_t uid, char name[static NAME_BUF_SIZE])
+#ifndef CONFIG_SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_CUSTOM
+
+BUILD_ASSERT(CONFIG_SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_MAX_LEN ==
+	     sizeof(CONFIG_SECURE_STORAGE_ITS_STORE_SETTINGS_PREFIX) - 1
+	     + 1 + 1 /* caller ID + '/' */
+	     + 2 * sizeof(psa_storage_uid_t) /* hex UID */);
+
+void secure_storage_its_store_settings_get_name(
+	secure_storage_its_uid_t uid,
+	char name[static SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_BUF_SIZE])
 {
 	int ret;
 
-	ret = snprintf(name, NAME_BUF_SIZE, CONFIG_SECURE_STORAGE_ITS_STORE_SETTINGS_PREFIX
-		       "%x/%llx", uid.caller_id, (unsigned long long)uid.uid);
-	__ASSERT_NO_MSG(ret > 0 && ret < NAME_BUF_SIZE);
+	ret = snprintf(name, SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_BUF_SIZE,
+		       CONFIG_SECURE_STORAGE_ITS_STORE_SETTINGS_PREFIX "%x/%llx",
+		       uid.caller_id, (unsigned long long)uid.uid);
+	__ASSERT_NO_MSG(ret > 0 && ret < SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_BUF_SIZE);
 }
 
+#endif /* !CONFIG_SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_CUSTOM */
+
 psa_status_t secure_storage_its_store_set(secure_storage_its_uid_t uid,
 					  size_t data_length, const void *data)
 {
 	int ret;
-	char name[NAME_BUF_SIZE];
+	char name[SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_BUF_SIZE];
+
+	secure_storage_its_store_settings_get_name(uid, name);
 
-	make_name(uid, name);
 	ret = settings_save_one(name, data, data_length);
 	LOG_DBG("%s %s with %zu bytes. (%d)",
 		(ret == 0) ? "Saved" : "Failed to save", name, data_length, ret);
@@ -81,10 +93,10 @@ psa_status_t secure_storage_its_store_get(secure_storage_its_uid_t uid, size_t d
 					  void *data, size_t *data_length)
 {
 	psa_status_t ret;
-	char name[NAME_BUF_SIZE];
+	char name[SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_BUF_SIZE];
 	struct load_params load_params = {.data_size = data_size, .data = data, .ret = -ENOENT};
 
-	make_name(uid, name);
+	secure_storage_its_store_settings_get_name(uid, name);
 
 	settings_load_subtree_direct(name, load_direct_setting, &load_params);
 	if (load_params.ret > 0) {
@@ -103,9 +115,10 @@ psa_status_t secure_storage_its_store_get(secure_storage_its_uid_t uid, size_t d
 psa_status_t secure_storage_its_store_remove(secure_storage_its_uid_t uid)
 {
 	int ret;
-	char name[NAME_BUF_SIZE];
+	char name[SECURE_STORAGE_ITS_STORE_SETTINGS_NAME_BUF_SIZE];
+
+	secure_storage_its_store_settings_get_name(uid, name);
 
-	make_name(uid, name);
 	ret = settings_delete(name);
 
 	LOG_DBG("%s %s. (%d)", ret ? "Failed to delete" : "Deleted", name, ret);
diff --git a/subsys/sensing/sensor_mgmt.h b/subsys/sensing/sensor_mgmt.h
index 0cd05a3e313..f863256b846 100644
--- a/subsys/sensing/sensor_mgmt.h
+++ b/subsys/sensing/sensor_mgmt.h
@@ -66,7 +66,7 @@ static inline struct sensing_sensor *get_sensor_by_dev(const struct device *dev)
 		}
 	}
 
-	__ASSERT(true, "device %s is not a sensing sensor", dev->name);
+	__ASSERT(false, "device %s is not a sensing sensor", dev->name);
 
 	return NULL;
 }
diff --git a/subsys/settings/src/settings_shell.c b/subsys/settings/src/settings_shell.c
index bef6b23c2b5..18bd9efb160 100644
--- a/subsys/settings/src/settings_shell.c
+++ b/subsys/settings/src/settings_shell.c
@@ -9,6 +9,7 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/toolchain.h>
 
+#include <ctype.h>
 #include <stdint.h>
 #include <stddef.h>
 
@@ -51,6 +52,7 @@ static int cmd_list(const struct shell *shell_ptr, size_t argc, char *argv[])
 
 	if (err) {
 		shell_error(shell_ptr, "Failed to load settings: %d", err);
+		err = -ENOEXEC;
 	}
 
 	return err;
@@ -74,6 +76,7 @@ static int settings_read_callback(const char *key,
 				  void            *param)
 {
 	uint8_t buffer[SETTINGS_MAX_VAL_LEN];
+	ssize_t i;
 	ssize_t num_read_bytes = MIN(len, SETTINGS_MAX_VAL_LEN);
 	struct settings_read_callback_params *params = param;
 
@@ -100,11 +103,13 @@ static int settings_read_callback(const char *key,
 		shell_hexdump(params->shell_ptr, buffer, num_read_bytes);
 		break;
 	case SETTINGS_VALUE_STRING:
-		if (buffer[num_read_bytes - 1] != '\0') {
-			shell_error(params->shell_ptr, "Value is not a string");
-			return 0;
+		for (i = 0; i < num_read_bytes; i++) {
+			if (!isprint(buffer[i])) {
+				shell_error(params->shell_ptr, "Value is not a string");
+				return 0;
+			}
 		}
-		shell_print(params->shell_ptr, "%s", buffer);
+		shell_print(params->shell_ptr, "%.*s", (int)num_read_bytes, buffer);
 		break;
 	}
 
@@ -138,7 +143,7 @@ static int cmd_read(const struct shell *shell_ptr, size_t argc, char *argv[])
 		err = settings_parse_type(argv[1], &value_type);
 		if (err) {
 			shell_error(shell_ptr, "Invalid type: %s", argv[1]);
-			return err;
+			return -EINVAL;
 		}
 	}
 
@@ -152,9 +157,10 @@ static int cmd_read(const struct shell *shell_ptr, size_t argc, char *argv[])
 
 	if (err) {
 		shell_error(shell_ptr, "Failed to load setting: %d", err);
+		err = -ENOEXEC;
 	} else if (!params.value_found) {
-		err = -ENOENT;
 		shell_error(shell_ptr, "Setting not found");
+		err = -ENOEXEC;
 	}
 
 	return err;
@@ -164,42 +170,39 @@ static int cmd_write(const struct shell *shell_ptr, size_t argc, char *argv[])
 {
 	int err;
 	uint8_t buffer[CONFIG_SHELL_CMD_BUFF_SIZE / 2];
-	size_t buffer_len = 0;
+	const void *value;
+	size_t value_len = 0;
 	enum settings_value_types value_type = SETTINGS_VALUE_HEX;
 
 	if (argc > 3) {
 		err = settings_parse_type(argv[1], &value_type);
 		if (err) {
 			shell_error(shell_ptr, "Invalid type: %s", argv[1]);
-			return err;
+			return -EINVAL;
 		}
 	}
 
 	switch (value_type) {
 	case SETTINGS_VALUE_HEX:
-		buffer_len = hex2bin(argv[argc - 1], strlen(argv[argc - 1]),
-			buffer, sizeof(buffer));
+		value = buffer;
+		value_len = hex2bin(argv[argc - 1], strlen(argv[argc - 1]), buffer, sizeof(buffer));
 		break;
 	case SETTINGS_VALUE_STRING:
-		buffer_len = strlen(argv[argc - 1]) + 1;
-		if (buffer_len > sizeof(buffer)) {
-			shell_error(shell_ptr, "%s is bigger than shell's buffer", argv[argc - 1]);
-			return -EINVAL;
-		}
-
-		memcpy(buffer, argv[argc - 1], buffer_len);
+		value = argv[argc - 1];
+		value_len = strlen(argv[argc - 1]);
 		break;
 	}
 
-	if (buffer_len == 0) {
+	if (value_len == 0) {
 		shell_error(shell_ptr, "Failed to parse value");
 		return -EINVAL;
 	}
 
-	err = settings_save_one(argv[argc - 2], buffer, buffer_len);
+	err = settings_save_one(argv[argc - 2], value, value_len);
 
 	if (err) {
 		shell_error(shell_ptr, "Failed to write setting: %d", err);
+		err = -ENOEXEC;
 	}
 
 	return err;
@@ -213,6 +216,7 @@ static int cmd_delete(const struct shell *shell_ptr, size_t argc, char *argv[])
 
 	if (err) {
 		shell_error(shell_ptr, "Failed to delete setting: %d", err);
+		err = -ENOEXEC;
 	}
 
 	return err;
@@ -237,13 +241,7 @@ SHELL_STATIC_SUBCMD_SET_CREATE(settings_cmds,
 		"Delete a specific setting\n"
 		"Usage: settings delete <name>",
 		cmd_delete, 2, 0),
-	SHELL_SUBCMD_SET_END);
-
-static int cmd_settings(const struct shell *shell_ptr, size_t argc, char **argv)
-{
-	shell_error(shell_ptr, "%s unknown parameter: %s", argv[0], argv[1]);
-	return -EINVAL;
-}
+	SHELL_SUBCMD_SET_END /* Array terminated. */
+);
 
-SHELL_CMD_ARG_REGISTER(settings, &settings_cmds, "Settings shell commands",
-		       cmd_settings, 2, 0);
+SHELL_CMD_REGISTER(settings, &settings_cmds, "Settings commands", NULL);
diff --git a/subsys/shell/Kconfig b/subsys/shell/Kconfig
index e8165a712fd..bfa3a8f49b0 100644
--- a/subsys/shell/Kconfig
+++ b/subsys/shell/Kconfig
@@ -94,6 +94,13 @@ config SHELL_PRINTF_BUFF_SIZE
 	  It is working like stdio buffering in Linux systems
 	  to limit number of peripheral access calls.
 
+config SHELL_PRINTF_AUTOFLUSH
+	bool "Indicate if the buffer should be automatically flushed"
+	default y
+	help
+	  Specify whether the shell's printing functions should automatically
+	  flush the printf buffer.
+
 config SHELL_DEFAULT_TERMINAL_WIDTH
 	int "Default terminal width"
 	range 1 $(UINT16_MAX)
diff --git a/subsys/shell/backends/shell_mqtt.c b/subsys/shell/backends/shell_mqtt.c
index d94c43f144e..28bd39f4b0d 100644
--- a/subsys/shell/backends/shell_mqtt.c
+++ b/subsys/shell/backends/shell_mqtt.c
@@ -65,16 +65,6 @@ static inline void sh_mqtt_context_unlock(void)
 	(void)k_mutex_unlock(&sh_mqtt->lock);
 }
 
-static void sh_mqtt_rx_rb_flush(void)
-{
-	uint8_t c;
-	uint32_t size = ring_buf_size_get(&sh_mqtt->rx_rb);
-
-	while (size > 0) {
-		size = ring_buf_get(&sh_mqtt->rx_rb, &c, 1U);
-	}
-}
-
 bool __weak shell_mqtt_get_devid(char *id, int id_max_len)
 {
 	uint8_t hwinfo_id[DEVICE_ID_BIN_MAX_SIZE];
@@ -91,19 +81,19 @@ bool __weak shell_mqtt_get_devid(char *id, int id_max_len)
 	return length > 0;
 }
 
-static void prepare_fds(void)
+static void prepare_fds(struct shell_mqtt *sh)
 {
-	if (sh_mqtt->mqtt_cli.transport.type == MQTT_TRANSPORT_NON_SECURE) {
-		sh_mqtt->fds[0].fd = sh_mqtt->mqtt_cli.transport.tcp.sock;
+	if (sh->mqtt_cli.transport.type == MQTT_TRANSPORT_NON_SECURE) {
+		sh->fds[0].fd = sh->mqtt_cli.transport.tcp.sock;
 	}
 
-	sh_mqtt->fds[0].events = ZSOCK_POLLIN;
-	sh_mqtt->nfds = 1;
+	sh->fds[0].events = ZSOCK_POLLIN;
+	sh->nfds = 1;
 }
 
-static void clear_fds(void)
+static void clear_fds(struct shell_mqtt *sh)
 {
-	sh_mqtt->nfds = 0;
+	sh->nfds = 0;
 }
 
 /*
@@ -113,12 +103,12 @@ static void clear_fds(void)
  * descriptors have been selected. Upon failure, poll() shall return -1 and set errno to indicate
  * the error.
  */
-static int wait(int timeout)
+static int wait(struct shell_mqtt *sh, int timeout)
 {
 	int rc = 0;
 
-	if (sh_mqtt->nfds > 0) {
-		rc = zsock_poll(sh_mqtt->fds, sh_mqtt->nfds, timeout);
+	if (sh->nfds > 0) {
+		rc = zsock_poll(sh->fds, sh->nfds, timeout);
 		if (rc < 0) {
 			LOG_ERR("poll error: %d", errno);
 		}
@@ -128,19 +118,19 @@ static int wait(int timeout)
 }
 
 /* Query IP address for the broker URL */
-static int get_mqtt_broker_addrinfo(void)
+static int get_mqtt_broker_addrinfo(struct shell_mqtt *sh)
 {
 	int rc;
 	struct zsock_addrinfo hints = { .ai_family = AF_INET,
 					.ai_socktype = SOCK_STREAM,
 					.ai_protocol = 0 };
 
-	if (sh_mqtt->haddr != NULL) {
-		zsock_freeaddrinfo(sh_mqtt->haddr);
+	if (sh->haddr != NULL) {
+		zsock_freeaddrinfo(sh->haddr);
 	}
 
 	rc = zsock_getaddrinfo(CONFIG_SHELL_MQTT_SERVER_ADDR,
-			       STRINGIFY(CONFIG_SHELL_MQTT_SERVER_PORT), &hints, &sh_mqtt->haddr);
+			       STRINGIFY(CONFIG_SHELL_MQTT_SERVER_PORT), &hints, &sh->haddr);
 	if (rc == 0) {
 		LOG_INF("DNS%s resolved for %s:%d", "", CONFIG_SHELL_MQTT_SERVER_ADDR,
 			CONFIG_SHELL_MQTT_SERVER_PORT);
@@ -155,7 +145,7 @@ static int get_mqtt_broker_addrinfo(void)
 }
 
 /* Close MQTT connection properly and cleanup socket */
-static void sh_mqtt_close_and_cleanup(void)
+static void sh_mqtt_close_and_cleanup(struct shell_mqtt *sh)
 {
 	/* Initialize to negative value so that the mqtt_abort case can run */
 	int rc = -1;
@@ -164,9 +154,9 @@ static void sh_mqtt_close_and_cleanup(void)
 	 * disconnection packet to the broker, it will invoke
 	 * mqtt_evt_handler:MQTT_EVT_DISCONNECT if success
 	 */
-	if ((sh_mqtt->network_state == SHELL_MQTT_NETWORK_CONNECTED) &&
-	    (sh_mqtt->transport_state == SHELL_MQTT_TRANSPORT_CONNECTED)) {
-		rc = mqtt_disconnect(&sh_mqtt->mqtt_cli, NULL);
+	if ((sh->network_state == SHELL_MQTT_NETWORK_CONNECTED) &&
+	    (sh->transport_state == SHELL_MQTT_TRANSPORT_CONNECTED)) {
+		rc = mqtt_disconnect(&sh->mqtt_cli, NULL);
 	}
 
 	/* If network/mqtt disconnected, or mqtt_disconnect failed, do mqtt_abort */
@@ -175,24 +165,24 @@ static void sh_mqtt_close_and_cleanup(void)
 		 * makes sure that the MQTT connection is aborted locally and will
 		 * always invoke mqtt_evt_handler:MQTT_EVT_DISCONNECT
 		 */
-		(void)mqtt_abort(&sh_mqtt->mqtt_cli);
+		(void)mqtt_abort(&sh->mqtt_cli);
 	}
 
 	/* Cleanup socket */
-	clear_fds();
+	clear_fds(sh);
 }
 
-static void broker_init(void)
+static void broker_init(struct shell_mqtt *sh)
 {
-	struct sockaddr_in *broker4 = (struct sockaddr_in *)&sh_mqtt->broker;
+	struct sockaddr_in *broker4 = (struct sockaddr_in *)&sh->broker;
 
 	broker4->sin_family = AF_INET;
 	broker4->sin_port = htons(CONFIG_SHELL_MQTT_SERVER_PORT);
 
-	net_ipaddr_copy(&broker4->sin_addr, &net_sin(sh_mqtt->haddr->ai_addr)->sin_addr);
+	net_ipaddr_copy(&broker4->sin_addr, &net_sin(sh->haddr->ai_addr)->sin_addr);
 }
 
-static void client_init(void)
+static void client_init(struct shell_mqtt *sh)
 {
 	static struct mqtt_utf8 password;
 	static struct mqtt_utf8 username;
@@ -202,36 +192,37 @@ static void client_init(void)
 	username.utf8 = (uint8_t *)MQTT_USERNAME;
 	username.size = strlen(MQTT_USERNAME);
 
-	mqtt_client_init(&sh_mqtt->mqtt_cli);
+	mqtt_client_init(&sh->mqtt_cli);
 
 	/* MQTT client configuration */
-	sh_mqtt->mqtt_cli.broker = &sh_mqtt->broker;
-	sh_mqtt->mqtt_cli.evt_cb = mqtt_evt_handler;
-	sh_mqtt->mqtt_cli.client_id.utf8 = (uint8_t *)sh_mqtt->device_id;
-	sh_mqtt->mqtt_cli.client_id.size = strlen(sh_mqtt->device_id);
-	sh_mqtt->mqtt_cli.password = &password;
-	sh_mqtt->mqtt_cli.user_name = &username;
-	sh_mqtt->mqtt_cli.protocol_version = MQTT_VERSION_3_1_1;
+	sh->mqtt_cli.broker = &sh->broker;
+	sh->mqtt_cli.evt_cb = mqtt_evt_handler;
+	sh->mqtt_cli.client_id.utf8 = (uint8_t *)sh->device_id;
+	sh->mqtt_cli.client_id.size = strlen(sh->device_id);
+	sh->mqtt_cli.password = &password;
+	sh->mqtt_cli.user_name = &username;
+	sh->mqtt_cli.protocol_version = MQTT_VERSION_3_1_1;
 
 	/* MQTT buffers configuration */
-	sh_mqtt->mqtt_cli.rx_buf = sh_mqtt->buf.rx;
-	sh_mqtt->mqtt_cli.rx_buf_size = sizeof(sh_mqtt->buf.rx);
-	sh_mqtt->mqtt_cli.tx_buf = sh_mqtt->buf.tx;
-	sh_mqtt->mqtt_cli.tx_buf_size = sizeof(sh_mqtt->buf.tx);
+	sh->mqtt_cli.rx_buf = sh->buf.rx;
+	sh->mqtt_cli.rx_buf_size = sizeof(sh->buf.rx);
+	sh->mqtt_cli.tx_buf = sh->buf.tx;
+	sh->mqtt_cli.tx_buf_size = sizeof(sh->buf.tx);
 
 	/* MQTT transport configuration */
-	sh_mqtt->mqtt_cli.transport.type = MQTT_TRANSPORT_NON_SECURE;
+	sh->mqtt_cli.transport.type = MQTT_TRANSPORT_NON_SECURE;
 }
 
 /* Work routine to process MQTT packet and keep alive MQTT connection */
 static void sh_mqtt_process_handler(struct k_work *work)
 {
 	ARG_UNUSED(work);
+	struct shell_mqtt *sh = sh_mqtt;
 	int rc;
 	int64_t remaining = LISTEN_TIMEOUT_MS;
 	int64_t start_time = k_uptime_get();
 
-	if (sh_mqtt->network_state != SHELL_MQTT_NETWORK_CONNECTED) {
+	if (sh->network_state != SHELL_MQTT_NETWORK_CONNECTED) {
 		LOG_DBG("%s_work while %s", "process", "network disconnected");
 		return;
 	}
@@ -243,26 +234,26 @@ static void sh_mqtt_process_handler(struct k_work *work)
 		return;
 	}
 
-	if (sh_mqtt->transport_state != SHELL_MQTT_TRANSPORT_CONNECTED) {
+	if (sh->transport_state != SHELL_MQTT_TRANSPORT_CONNECTED) {
 		LOG_DBG("MQTT %s", "not connected");
 		goto process_error;
 	}
 
-	if (sh_mqtt->subscribe_state != SHELL_MQTT_SUBSCRIBED) {
+	if (sh->subscribe_state != SHELL_MQTT_SUBSCRIBED) {
 		LOG_DBG("%s_work while %s", "process", "MQTT not subscribed");
 		goto process_error;
 	}
 
 	LOG_DBG("MQTT %s", "Processing");
 	/* Listen to the port for a duration defined by LISTEN_TIMEOUT_MS */
-	while ((remaining > 0) && (sh_mqtt->network_state == SHELL_MQTT_NETWORK_CONNECTED) &&
-	       (sh_mqtt->transport_state == SHELL_MQTT_TRANSPORT_CONNECTED) &&
-	       (sh_mqtt->subscribe_state == SHELL_MQTT_SUBSCRIBED)) {
+	while ((remaining > 0) && (sh->network_state == SHELL_MQTT_NETWORK_CONNECTED) &&
+	       (sh->transport_state == SHELL_MQTT_TRANSPORT_CONNECTED) &&
+	       (sh->subscribe_state == SHELL_MQTT_SUBSCRIBED)) {
 		LOG_DBG("Listening to socket");
-		rc = wait(remaining);
+		rc = wait(sh, remaining);
 		if (rc > 0) {
 			LOG_DBG("Process socket for MQTT packet");
-			rc = mqtt_input(&sh_mqtt->mqtt_cli);
+			rc = mqtt_input(&sh->mqtt_cli);
 			if (rc != 0) {
 				LOG_ERR("%s error: %d", "processed: mqtt_input", rc);
 				goto process_error;
@@ -272,7 +263,7 @@ static void sh_mqtt_process_handler(struct k_work *work)
 		}
 
 		LOG_DBG("MQTT %s", "Keepalive");
-		rc = mqtt_live(&sh_mqtt->mqtt_cli);
+		rc = mqtt_live(&sh->mqtt_cli);
 		if ((rc != 0) && (rc != -EAGAIN)) {
 			LOG_ERR("%s error: %d", "mqtt_live", rc);
 			goto process_error;
@@ -283,30 +274,32 @@ static void sh_mqtt_process_handler(struct k_work *work)
 
 	/* Reschedule the process work */
 	LOG_DBG("Scheduling %s work", "process");
-	(void)sh_mqtt_work_reschedule(&sh_mqtt->process_dwork, K_SECONDS(2));
+	(void)sh_mqtt_work_reschedule(&sh->process_dwork, K_SECONDS(2));
 	sh_mqtt_context_unlock();
 	return;
 
 process_error:
 	LOG_DBG("%s: close MQTT, cleanup socket & reconnect", "connect");
-	sh_mqtt_close_and_cleanup();
-	(void)sh_mqtt_work_reschedule(&sh_mqtt->connect_dwork, K_SECONDS(1));
+	sh_mqtt_close_and_cleanup(sh);
+	(void)sh_mqtt_work_reschedule(&sh->connect_dwork, K_SECONDS(1));
 	sh_mqtt_context_unlock();
 }
 
 static void sh_mqtt_subscribe_handler(struct k_work *work)
 {
 	ARG_UNUSED(work);
+	struct shell_mqtt *sh = sh_mqtt;
+
 	/* Subscribe config information */
-	struct mqtt_topic subs_topic = { .topic = { .utf8 = sh_mqtt->sub_topic,
-						    .size = strlen(sh_mqtt->sub_topic) },
+	struct mqtt_topic subs_topic = { .topic = { .utf8 = sh->sub_topic,
+						    .size = strlen(sh->sub_topic) },
 					 .qos = MQTT_QOS_1_AT_LEAST_ONCE };
 	const struct mqtt_subscription_list subs_list = { .list = &subs_topic,
 							  .list_count = 1U,
 							  .message_id = 1U };
 	int rc;
 
-	if (sh_mqtt->network_state != SHELL_MQTT_NETWORK_CONNECTED) {
+	if (sh->network_state != SHELL_MQTT_NETWORK_CONNECTED) {
 		LOG_DBG("%s_work while %s", "subscribe", "network disconnected");
 		return;
 	}
@@ -318,19 +311,19 @@ static void sh_mqtt_subscribe_handler(struct k_work *work)
 		return;
 	}
 
-	if (sh_mqtt->transport_state != SHELL_MQTT_TRANSPORT_CONNECTED) {
+	if (sh->transport_state != SHELL_MQTT_TRANSPORT_CONNECTED) {
 		LOG_DBG("%s_work while %s", "subscribe", "transport disconnected");
 		goto subscribe_error;
 	}
 
-	rc = mqtt_subscribe(&sh_mqtt->mqtt_cli, &subs_list);
+	rc = mqtt_subscribe(&sh->mqtt_cli, &subs_list);
 	if (rc == 0) {
 		/* Wait for mqtt's connack */
 		LOG_DBG("Listening to socket");
-		rc = wait(CONNECT_TIMEOUT_MS);
+		rc = wait(sh, CONNECT_TIMEOUT_MS);
 		if (rc > 0) {
 			LOG_DBG("Process socket for MQTT packet");
-			rc = mqtt_input(&sh_mqtt->mqtt_cli);
+			rc = mqtt_input(&sh->mqtt_cli);
 			if (rc != 0) {
 				LOG_ERR("%s error: %d", "subscribe: mqtt_input", rc);
 				goto subscribe_error;
@@ -340,24 +333,24 @@ static void sh_mqtt_subscribe_handler(struct k_work *work)
 		}
 
 		/* No suback, fail */
-		if (sh_mqtt->subscribe_state != SHELL_MQTT_SUBSCRIBED) {
+		if (sh->subscribe_state != SHELL_MQTT_SUBSCRIBED) {
 			goto subscribe_error;
 		}
 
 		LOG_DBG("Scheduling MQTT process work");
-		(void)sh_mqtt_work_reschedule(&sh_mqtt->process_dwork, PROCESS_INTERVAL);
+		(void)sh_mqtt_work_reschedule(&sh->process_dwork, PROCESS_INTERVAL);
 		sh_mqtt_context_unlock();
 
-		LOG_INF("Logs will be published to: %s", sh_mqtt->pub_topic);
-		LOG_INF("Subscribing shell cmds from: %s", sh_mqtt->sub_topic);
+		LOG_INF("Logs will be published to: %s", sh->pub_topic);
+		LOG_INF("Subscribing shell cmds from: %s", sh->sub_topic);
 
 		return;
 	}
 
 subscribe_error:
 	LOG_DBG("%s: close MQTT, cleanup socket & reconnect", "subscribe");
-	sh_mqtt_close_and_cleanup();
-	(void)sh_mqtt_work_reschedule(&sh_mqtt->connect_dwork, K_SECONDS(2));
+	sh_mqtt_close_and_cleanup(sh);
+	(void)sh_mqtt_work_reschedule(&sh->connect_dwork, K_SECONDS(2));
 	sh_mqtt_context_unlock();
 }
 
@@ -365,9 +358,10 @@ static void sh_mqtt_subscribe_handler(struct k_work *work)
 static void sh_mqtt_connect_handler(struct k_work *work)
 {
 	ARG_UNUSED(work);
+	struct shell_mqtt *sh = sh_mqtt;
 	int rc;
 
-	if (sh_mqtt->network_state != SHELL_MQTT_NETWORK_CONNECTED) {
+	if (sh->network_state != SHELL_MQTT_NETWORK_CONNECTED) {
 		LOG_DBG("%s_work while %s", "connect", "network disconnected");
 		return;
 	}
@@ -379,7 +373,7 @@ static void sh_mqtt_connect_handler(struct k_work *work)
 		return;
 	}
 
-	if (sh_mqtt->transport_state == SHELL_MQTT_TRANSPORT_CONNECTED) {
+	if (sh->transport_state == SHELL_MQTT_TRANSPORT_CONNECTED) {
 		__ASSERT(0, "MQTT shouldn't be already connected");
 		LOG_ERR("MQTT shouldn't be already connected");
 		goto connect_error;
@@ -387,20 +381,20 @@ static void sh_mqtt_connect_handler(struct k_work *work)
 
 	/* Resolve the broker URL */
 	LOG_DBG("Resolving DNS");
-	rc = get_mqtt_broker_addrinfo();
+	rc = get_mqtt_broker_addrinfo(sh);
 	if (rc != 0) {
-		(void)sh_mqtt_work_reschedule(&sh_mqtt->connect_dwork, K_SECONDS(1));
+		(void)sh_mqtt_work_reschedule(&sh->connect_dwork, K_SECONDS(1));
 		sh_mqtt_context_unlock();
 		return;
 	}
 
 	LOG_DBG("Initializing MQTT client");
-	broker_init();
-	client_init();
+	broker_init(sh);
+	client_init(sh);
 
 	/* Try to connect to mqtt */
 	LOG_DBG("Connecting to MQTT broker");
-	rc = mqtt_connect(&sh_mqtt->mqtt_cli);
+	rc = mqtt_connect(&sh->mqtt_cli);
 	if (rc != 0) {
 		LOG_ERR("%s error: %d", "mqtt_connect", rc);
 		goto connect_error;
@@ -408,14 +402,14 @@ static void sh_mqtt_connect_handler(struct k_work *work)
 
 	/* Prepare port config */
 	LOG_DBG("Preparing socket");
-	prepare_fds();
+	prepare_fds(sh);
 
 	/* Wait for mqtt's connack */
 	LOG_DBG("Listening to socket");
-	rc = wait(CONNECT_TIMEOUT_MS);
+	rc = wait(sh, CONNECT_TIMEOUT_MS);
 	if (rc > 0) {
 		LOG_DBG("Process socket for MQTT packet");
-		rc = mqtt_input(&sh_mqtt->mqtt_cli);
+		rc = mqtt_input(&sh->mqtt_cli);
 		if (rc != 0) {
 			LOG_ERR("%s error: %d", "connect: mqtt_input", rc);
 			goto connect_error;
@@ -425,37 +419,37 @@ static void sh_mqtt_connect_handler(struct k_work *work)
 	}
 
 	/* No connack, fail */
-	if (sh_mqtt->transport_state != SHELL_MQTT_TRANSPORT_CONNECTED) {
+	if (sh->transport_state != SHELL_MQTT_TRANSPORT_CONNECTED) {
 		goto connect_error;
 	}
 
 	LOG_DBG("Scheduling %s work", "subscribe");
-	(void)sh_mqtt_work_reschedule(&sh_mqtt->subscribe_dwork, K_SECONDS(2));
+	(void)sh_mqtt_work_reschedule(&sh->subscribe_dwork, K_SECONDS(2));
 	sh_mqtt_context_unlock();
 	return;
 
 connect_error:
 	LOG_DBG("%s: close MQTT, cleanup socket & reconnect", "connect");
-	sh_mqtt_close_and_cleanup();
-	(void)sh_mqtt_work_reschedule(&sh_mqtt->connect_dwork, K_SECONDS(2));
+	sh_mqtt_close_and_cleanup(sh);
+	(void)sh_mqtt_work_reschedule(&sh->connect_dwork, K_SECONDS(2));
 	sh_mqtt_context_unlock();
 }
 
-static int sh_mqtt_publish(uint8_t *data, uint32_t len)
+static int sh_mqtt_publish(struct shell_mqtt *sh, uint8_t *data, uint32_t len)
 {
-	sh_mqtt->pub_data.message.payload.data = data;
-	sh_mqtt->pub_data.message.payload.len = len;
-	sh_mqtt->pub_data.message_id++;
+	sh->pub_data.message.payload.data = data;
+	sh->pub_data.message.payload.len = len;
+	sh->pub_data.message_id++;
 
-	return mqtt_publish(&sh_mqtt->mqtt_cli, &sh_mqtt->pub_data);
+	return mqtt_publish(&sh->mqtt_cli, &sh->pub_data);
 }
 
-static int sh_mqtt_publish_tx_buf(bool is_work)
+static int sh_mqtt_publish_tx_buf(struct shell_mqtt *sh, bool is_work)
 {
 	int rc;
 
-	rc = sh_mqtt_publish(&sh_mqtt->tx_buf.buf[0], sh_mqtt->tx_buf.len);
-	memset(&sh_mqtt->tx_buf, 0, sizeof(sh_mqtt->tx_buf));
+	rc = sh_mqtt_publish(sh, &sh->tx_buf.buf[0], sh->tx_buf.len);
+	memset(&sh->tx_buf, 0, sizeof(sh->tx_buf));
 	if (rc != 0) {
 		LOG_ERR("MQTT publish error: %d", rc);
 		return rc;
@@ -472,39 +466,41 @@ static int sh_mqtt_publish_tx_buf(bool is_work)
 static void sh_mqtt_publish_handler(struct k_work *work)
 {
 	ARG_UNUSED(work);
+	struct shell_mqtt *sh = sh_mqtt;
 	int rc;
 
 	(void)sh_mqtt_context_lock(K_FOREVER);
 
-	rc = sh_mqtt_publish_tx_buf(true);
+	rc = sh_mqtt_publish_tx_buf(sh, true);
 	if (rc != 0) {
 		LOG_DBG("%s: close MQTT, cleanup socket & reconnect", "publish");
-		sh_mqtt_close_and_cleanup();
-		(void)sh_mqtt_work_reschedule(&sh_mqtt->connect_dwork, K_SECONDS(2));
+		sh_mqtt_close_and_cleanup(sh);
+		(void)sh_mqtt_work_reschedule(&sh->connect_dwork, K_SECONDS(2));
 	}
 
 	sh_mqtt_context_unlock();
 }
 
-static void cancel_dworks_and_cleanup(void)
+static void cancel_dworks_and_cleanup(struct shell_mqtt *sh)
 {
-	(void)k_work_cancel_delayable(&sh_mqtt->connect_dwork);
-	(void)k_work_cancel_delayable(&sh_mqtt->subscribe_dwork);
-	(void)k_work_cancel_delayable(&sh_mqtt->process_dwork);
-	(void)k_work_cancel_delayable(&sh_mqtt->publish_dwork);
-	sh_mqtt_close_and_cleanup();
+	(void)k_work_cancel_delayable(&sh->connect_dwork);
+	(void)k_work_cancel_delayable(&sh->subscribe_dwork);
+	(void)k_work_cancel_delayable(&sh->process_dwork);
+	(void)k_work_cancel_delayable(&sh->publish_dwork);
+	sh_mqtt_close_and_cleanup(sh);
 }
 
 static void net_disconnect_handler(struct k_work *work)
 {
 	ARG_UNUSED(work);
+	struct shell_mqtt *sh = sh_mqtt;
 
 	LOG_WRN("Network %s", "disconnected");
-	sh_mqtt->network_state = SHELL_MQTT_NETWORK_DISCONNECTED;
+	sh->network_state = SHELL_MQTT_NETWORK_DISCONNECTED;
 
 	/* Stop all possible work */
 	(void)sh_mqtt_context_lock(K_FOREVER);
-	cancel_dworks_and_cleanup();
+	cancel_dworks_and_cleanup(sh);
 	sh_mqtt_context_unlock();
 	/* If the transport was requested, the connect work will be rescheduled
 	 * when internet is connected again
@@ -515,51 +511,55 @@ static void net_disconnect_handler(struct k_work *work)
 static void network_evt_handler(struct net_mgmt_event_callback *cb, uint32_t mgmt_event,
 				struct net_if *iface)
 {
+	struct shell_mqtt *sh = sh_mqtt;
+
 	if ((mgmt_event == NET_EVENT_L4_CONNECTED) &&
-	    (sh_mqtt->network_state == SHELL_MQTT_NETWORK_DISCONNECTED)) {
+	    (sh->network_state == SHELL_MQTT_NETWORK_DISCONNECTED)) {
 		LOG_WRN("Network %s", "connected");
-		sh_mqtt->network_state = SHELL_MQTT_NETWORK_CONNECTED;
-		(void)sh_mqtt_work_reschedule(&sh_mqtt->connect_dwork, K_SECONDS(1));
+		sh->network_state = SHELL_MQTT_NETWORK_CONNECTED;
+		(void)sh_mqtt_work_reschedule(&sh->connect_dwork, K_SECONDS(1));
 	} else if ((mgmt_event == NET_EVENT_L4_DISCONNECTED) &&
-		   (sh_mqtt->network_state == SHELL_MQTT_NETWORK_CONNECTED)) {
-		(void)sh_mqtt_work_submit(&sh_mqtt->net_disconnected_work);
+		   (sh->network_state == SHELL_MQTT_NETWORK_CONNECTED)) {
+		(void)sh_mqtt_work_submit(&sh->net_disconnected_work);
 	}
 }
 
 static void mqtt_evt_handler(struct mqtt_client *const client, const struct mqtt_evt *evt)
 {
+	struct shell_mqtt *sh = sh_mqtt;
+
 	switch (evt->type) {
 	case MQTT_EVT_CONNACK:
 		if (evt->result != 0) {
-			sh_mqtt->transport_state = SHELL_MQTT_TRANSPORT_DISCONNECTED;
+			sh->transport_state = SHELL_MQTT_TRANSPORT_DISCONNECTED;
 			LOG_ERR("MQTT %s %d", "connect failed", evt->result);
 			break;
 		}
 
-		sh_mqtt->transport_state = SHELL_MQTT_TRANSPORT_CONNECTED;
+		sh->transport_state = SHELL_MQTT_TRANSPORT_CONNECTED;
 		LOG_WRN("MQTT %s", "client connected!");
-
 		break;
+
 	case MQTT_EVT_SUBACK:
 		if (evt->result != 0) {
 			LOG_ERR("MQTT subscribe: %s", "error");
-			sh_mqtt->subscribe_state = SHELL_MQTT_NOT_SUBSCRIBED;
+			sh->subscribe_state = SHELL_MQTT_NOT_SUBSCRIBED;
 			break;
 		}
 
 		LOG_WRN("MQTT subscribe: %s", "ok");
-		sh_mqtt->subscribe_state = SHELL_MQTT_SUBSCRIBED;
+		sh->subscribe_state = SHELL_MQTT_SUBSCRIBED;
 		break;
 
 	case MQTT_EVT_UNSUBACK:
 		LOG_DBG("UNSUBACK packet id: %u", evt->param.suback.message_id);
-		sh_mqtt->subscribe_state = SHELL_MQTT_NOT_SUBSCRIBED;
+		sh->subscribe_state = SHELL_MQTT_NOT_SUBSCRIBED;
 		break;
 
 	case MQTT_EVT_DISCONNECT:
 		LOG_WRN("MQTT disconnected: %d", evt->result);
-		sh_mqtt->transport_state = SHELL_MQTT_TRANSPORT_DISCONNECTED;
-		sh_mqtt->subscribe_state = SHELL_MQTT_NOT_SUBSCRIBED;
+		sh->transport_state = SHELL_MQTT_TRANSPORT_DISCONNECTED;
+		sh->subscribe_state = SHELL_MQTT_NOT_SUBSCRIBED;
 		break;
 
 	case MQTT_EVT_PUBLISH: {
@@ -583,25 +583,24 @@ static void mqtt_evt_handler(struct mqtt_client *const client, const struct mqtt
 
 		while (payload_left > 0) {
 			/* Attempt to claim `payload_left` bytes of buffer in rb */
-			size = (size_t)ring_buf_put_claim(&sh_mqtt->rx_rb, &sh_mqtt->rx_rb_ptr,
+			size = (size_t)ring_buf_put_claim(&sh->rx_rb, &sh->rx_rb_ptr,
 							  payload_left);
 			/* Read `size` bytes of payload from mqtt */
-			rc = mqtt_read_publish_payload_blocking(client, sh_mqtt->rx_rb_ptr, size);
+			rc = mqtt_read_publish_payload_blocking(client, sh->rx_rb_ptr, size);
 
 			/* errno value, return */
 			if (rc < 0) {
-				(void)ring_buf_put_finish(&sh_mqtt->rx_rb, 0U);
-				sh_mqtt_rx_rb_flush();
+				ring_buf_reset(&sh->rx_rb);
 				return;
 			}
 
 			size = (size_t)rc;
 			/* Indicate that `size` bytes of payload has been written into rb */
-			(void)ring_buf_put_finish(&sh_mqtt->rx_rb, size);
+			(void)ring_buf_put_finish(&sh->rx_rb, size);
 			/* Update `payload_left` */
 			payload_left -= size;
 			/* Tells the shell that we have new data for it */
-			sh_mqtt->shell_handler(SHELL_TRANSPORT_EVT_RX_RDY, sh_mqtt->shell_context);
+			sh->shell_handler(SHELL_TRANSPORT_EVT_RX_RDY, sh->shell_context);
 			/* Arbitrary sleep for the shell to do its thing */
 			(void)k_msleep(100);
 		}
@@ -609,16 +608,16 @@ static void mqtt_evt_handler(struct mqtt_client *const client, const struct mqtt
 		/* Shell won't execute the cmds without \r\n */
 		while (true) {
 			/* Check if rb's free space is enough to fit in \r\n */
-			size = ring_buf_space_get(&sh_mqtt->rx_rb);
+			size = ring_buf_space_get(&sh->rx_rb);
 			if (size >= sizeof("\r\n")) {
-				(void)ring_buf_put(&sh_mqtt->rx_rb, "\r\n", sizeof("\r\n"));
+				(void)ring_buf_put(&sh->rx_rb, "\r\n", sizeof("\r\n"));
 				break;
 			}
 			/* Arbitrary sleep for the shell to do its thing */
 			(void)k_msleep(100);
 		}
 
-		sh_mqtt->shell_handler(SHELL_TRANSPORT_EVT_RX_RDY, sh_mqtt->shell_context);
+		sh->shell_handler(SHELL_TRANSPORT_EVT_RX_RDY, sh->shell_context);
 		break;
 	}
 
@@ -645,52 +644,53 @@ static int init(const struct shell_transport *transport, const void *config,
 		shell_transport_handler_t evt_handler, void *context)
 {
 	sh_mqtt = (struct shell_mqtt *)transport->ctx;
+	struct shell_mqtt *sh = sh_mqtt;
 
-	(void)memset(sh_mqtt, 0, sizeof(struct shell_mqtt));
+	(void)memset(sh, 0, sizeof(struct shell_mqtt));
 
-	(void)k_mutex_init(&sh_mqtt->lock);
+	(void)k_mutex_init(&sh->lock);
 
-	if (!shell_mqtt_get_devid(sh_mqtt->device_id, DEVICE_ID_HEX_MAX_SIZE)) {
+	if (!shell_mqtt_get_devid(sh->device_id, DEVICE_ID_HEX_MAX_SIZE)) {
 		LOG_ERR("Unable to get device identity, using dummy value");
-		(void)snprintf(sh_mqtt->device_id, sizeof("dummy"), "dummy");
+		(void)snprintf(sh->device_id, sizeof("dummy"), "dummy");
 	}
 
-	LOG_DBG("Client ID is %s", sh_mqtt->device_id);
+	LOG_DBG("Client ID is %s", sh->device_id);
 
-	(void)snprintf(sh_mqtt->pub_topic, SH_MQTT_TOPIC_MAX_SIZE, "%s_tx", sh_mqtt->device_id);
-	(void)snprintf(sh_mqtt->sub_topic, SH_MQTT_TOPIC_MAX_SIZE, "%s_rx", sh_mqtt->device_id);
+	(void)snprintf(sh->pub_topic, SH_MQTT_TOPIC_MAX_SIZE, "%s_tx", sh->device_id);
+	(void)snprintf(sh->sub_topic, SH_MQTT_TOPIC_MAX_SIZE, "%s_rx", sh->device_id);
 
-	ring_buf_init(&sh_mqtt->rx_rb, RX_RB_SIZE, sh_mqtt->rx_rb_buf);
+	ring_buf_init(&sh->rx_rb, RX_RB_SIZE, sh->rx_rb_buf);
 
 	LOG_DBG("Initializing shell MQTT backend");
 
-	sh_mqtt->shell_handler = evt_handler;
-	sh_mqtt->shell_context = context;
+	sh->shell_handler = evt_handler;
+	sh->shell_context = context;
 
-	sh_mqtt->pub_data.message.topic.qos = MQTT_QOS_0_AT_MOST_ONCE;
-	sh_mqtt->pub_data.message.topic.topic.utf8 = (uint8_t *)sh_mqtt->pub_topic;
-	sh_mqtt->pub_data.message.topic.topic.size =
-		strlen(sh_mqtt->pub_data.message.topic.topic.utf8);
-	sh_mqtt->pub_data.dup_flag = 0U;
-	sh_mqtt->pub_data.retain_flag = 0U;
+	sh->pub_data.message.topic.qos = MQTT_QOS_0_AT_MOST_ONCE;
+	sh->pub_data.message.topic.topic.utf8 = (uint8_t *)sh->pub_topic;
+	sh->pub_data.message.topic.topic.size =
+		strlen(sh->pub_data.message.topic.topic.utf8);
+	sh->pub_data.dup_flag = 0U;
+	sh->pub_data.retain_flag = 0U;
 
 	/* Initialize the work queue */
-	k_work_queue_init(&sh_mqtt->workq);
-	k_work_queue_start(&sh_mqtt->workq, sh_mqtt_workq_stack,
+	k_work_queue_init(&sh->workq);
+	k_work_queue_start(&sh->workq, sh_mqtt_workq_stack,
 			   K_KERNEL_STACK_SIZEOF(sh_mqtt_workq_stack), K_PRIO_COOP(7), NULL);
-	(void)k_thread_name_set(&sh_mqtt->workq.thread, "sh_mqtt_workq");
-	k_work_init(&sh_mqtt->net_disconnected_work, net_disconnect_handler);
-	k_work_init_delayable(&sh_mqtt->connect_dwork, sh_mqtt_connect_handler);
-	k_work_init_delayable(&sh_mqtt->subscribe_dwork, sh_mqtt_subscribe_handler);
-	k_work_init_delayable(&sh_mqtt->process_dwork, sh_mqtt_process_handler);
-	k_work_init_delayable(&sh_mqtt->publish_dwork, sh_mqtt_publish_handler);
+	(void)k_thread_name_set(&sh->workq.thread, "sh_mqtt_workq");
+	k_work_init(&sh->net_disconnected_work, net_disconnect_handler);
+	k_work_init_delayable(&sh->connect_dwork, sh_mqtt_connect_handler);
+	k_work_init_delayable(&sh->subscribe_dwork, sh_mqtt_subscribe_handler);
+	k_work_init_delayable(&sh->process_dwork, sh_mqtt_process_handler);
+	k_work_init_delayable(&sh->publish_dwork, sh_mqtt_publish_handler);
 
 	LOG_DBG("Initializing listener for network");
-	net_mgmt_init_event_callback(&sh_mqtt->mgmt_cb, network_evt_handler, NET_EVENT_MASK);
+	net_mgmt_init_event_callback(&sh->mgmt_cb, network_evt_handler, NET_EVENT_MASK);
 
-	sh_mqtt->network_state = SHELL_MQTT_NETWORK_DISCONNECTED;
-	sh_mqtt->transport_state = SHELL_MQTT_TRANSPORT_DISCONNECTED;
-	sh_mqtt->subscribe_state = SHELL_MQTT_NOT_SUBSCRIBED;
+	sh->network_state = SHELL_MQTT_NETWORK_DISCONNECTED;
+	sh->transport_state = SHELL_MQTT_TRANSPORT_DISCONNECTED;
+	sh->subscribe_state = SHELL_MQTT_NOT_SUBSCRIBED;
 
 	return 0;
 }
@@ -698,9 +698,10 @@ static int init(const struct shell_transport *transport, const void *config,
 static int uninit(const struct shell_transport *transport)
 {
 	ARG_UNUSED(transport);
+	struct shell_mqtt *sh = sh_mqtt;
 
 	/* Not initialized yet */
-	if (sh_mqtt == NULL) {
+	if (sh == NULL) {
 		return -ENODEV;
 	}
 
@@ -711,14 +712,15 @@ static int enable(const struct shell_transport *transport, bool blocking)
 {
 	ARG_UNUSED(transport);
 	ARG_UNUSED(blocking);
+	struct shell_mqtt *sh = sh_mqtt;
 
 	/* Not initialized yet */
-	if (sh_mqtt == NULL) {
+	if (sh == NULL) {
 		return -ENODEV;
 	}
 
 	/* Listen for network connection status */
-	net_mgmt_add_event_callback(&sh_mqtt->mgmt_cb);
+	net_mgmt_add_event_callback(&sh->mgmt_cb);
 	conn_mgr_mon_resend_status();
 
 	return 0;
@@ -728,6 +730,7 @@ static int write_data(const struct shell_transport *transport, const void *data,
 		      size_t *cnt)
 {
 	ARG_UNUSED(transport);
+	struct shell_mqtt *sh = sh_mqtt;
 	int rc = 0;
 	struct k_work_sync ws;
 	size_t copy_len;
@@ -735,33 +738,33 @@ static int write_data(const struct shell_transport *transport, const void *data,
 	*cnt = 0;
 
 	/* Not initialized yet */
-	if (sh_mqtt == NULL) {
+	if (sh == NULL) {
 		return -ENODEV;
 	}
 
 	/* Not connected to broker */
-	if (sh_mqtt->transport_state != SHELL_MQTT_TRANSPORT_CONNECTED) {
+	if (sh->transport_state != SHELL_MQTT_TRANSPORT_CONNECTED) {
 		goto out;
 	}
 
-	(void)k_work_cancel_delayable_sync(&sh_mqtt->publish_dwork, &ws);
+	(void)k_work_cancel_delayable_sync(&sh->publish_dwork, &ws);
 
 	do {
-		if ((sh_mqtt->tx_buf.len + length - *cnt) > TX_BUF_SIZE) {
-			copy_len = TX_BUF_SIZE - sh_mqtt->tx_buf.len;
+		if ((sh->tx_buf.len + length - *cnt) > TX_BUF_SIZE) {
+			copy_len = TX_BUF_SIZE - sh->tx_buf.len;
 		} else {
 			copy_len = length - *cnt;
 		}
 
-		memcpy(sh_mqtt->tx_buf.buf + sh_mqtt->tx_buf.len, (uint8_t *)data + *cnt, copy_len);
-		sh_mqtt->tx_buf.len += copy_len;
+		memcpy(sh->tx_buf.buf + sh->tx_buf.len, (uint8_t *)data + *cnt, copy_len);
+		sh->tx_buf.len += copy_len;
 
 		/* Send the data immediately if the buffer is full */
-		if (sh_mqtt->tx_buf.len == TX_BUF_SIZE) {
-			rc = sh_mqtt_publish_tx_buf(false);
+		if (sh->tx_buf.len == TX_BUF_SIZE) {
+			rc = sh_mqtt_publish_tx_buf(sh, false);
 			if (rc != 0) {
-				sh_mqtt_close_and_cleanup();
-				(void)sh_mqtt_work_reschedule(&sh_mqtt->connect_dwork,
+				sh_mqtt_close_and_cleanup(sh);
+				(void)sh_mqtt_work_reschedule(&sh->connect_dwork,
 							      K_SECONDS(2));
 				*cnt = length;
 				return rc;
@@ -771,12 +774,12 @@ static int write_data(const struct shell_transport *transport, const void *data,
 		*cnt += copy_len;
 	} while (*cnt < length);
 
-	if (sh_mqtt->tx_buf.len > 0) {
-		(void)sh_mqtt_work_reschedule(&sh_mqtt->publish_dwork, MQTT_SEND_DELAY_MS);
+	if (sh->tx_buf.len > 0) {
+		(void)sh_mqtt_work_reschedule(&sh->publish_dwork, MQTT_SEND_DELAY_MS);
 	}
 
 	/* Inform shell that it is ready for next TX */
-	sh_mqtt->shell_handler(SHELL_TRANSPORT_EVT_TX_RDY, sh_mqtt->shell_context);
+	sh->shell_handler(SHELL_TRANSPORT_EVT_TX_RDY, sh->shell_context);
 
 out:
 	/* We will always assume that we sent everything */
@@ -788,23 +791,24 @@ static int read_data(const struct shell_transport *transport, void *data, size_t
 		     size_t *cnt)
 {
 	ARG_UNUSED(transport);
+	struct shell_mqtt *sh = sh_mqtt;
 
 	/* Not initialized yet */
-	if (sh_mqtt == NULL) {
+	if (sh == NULL) {
 		return -ENODEV;
 	}
 
 	/* Not subscribed yet */
-	if (sh_mqtt->subscribe_state != SHELL_MQTT_SUBSCRIBED) {
+	if (sh->subscribe_state != SHELL_MQTT_SUBSCRIBED) {
 		*cnt = 0;
 		return 0;
 	}
 
-	*cnt = ring_buf_get(&sh_mqtt->rx_rb, data, length);
+	*cnt = ring_buf_get(&sh->rx_rb, data, length);
 
 	/* Inform the shell if there are still data in the rb */
-	if (ring_buf_size_get(&sh_mqtt->rx_rb) > 0) {
-		sh_mqtt->shell_handler(SHELL_TRANSPORT_EVT_RX_RDY, sh_mqtt->shell_context);
+	if (ring_buf_size_get(&sh->rx_rb) > 0) {
+		sh->shell_handler(SHELL_TRANSPORT_EVT_RX_RDY, sh->shell_context);
 	}
 
 	return 0;
diff --git a/subsys/shell/backends/shell_websocket.c b/subsys/shell/backends/shell_websocket.c
index 62b8dc9a5f8..92b83965318 100644
--- a/subsys/shell/backends/shell_websocket.c
+++ b/subsys/shell/backends/shell_websocket.c
@@ -16,7 +16,7 @@
 #include <zephyr/shell/shell_websocket.h>
 #include <zephyr/logging/log_backend_ws.h>
 
-LOG_MODULE_REGISTER(shell_websocket, CONFIG_SHELL_WEBSOCKET_INIT_LOG_LEVEL);
+LOG_MODULE_REGISTER(shell_websocket, CONFIG_SHELL_WEBSOCKET_LOG_LEVEL);
 
 #define WEBSOCKET_LINE_SIZE CONFIG_SHELL_WEBSOCKET_LINE_BUF_SIZE
 #define WEBSOCKET_TIMEOUT   CONFIG_SHELL_WEBSOCKET_SEND_TIMEOUT
@@ -35,7 +35,9 @@ static void ws_end_client_connection(struct shell_websocket *ws)
 
 	LOG_DBG("Closing connection to #%d", ws->fds[0].fd);
 
-	(void)log_backend_ws_unregister(ws->fds[0].fd);
+	if (IS_ENABLED(CONFIG_LOG_BACKEND_WS)) {
+		(void)log_backend_ws_unregister(ws->fds[0].fd);
+	}
 
 	(void)websocket_unregister(ws->fds[0].fd);
 
@@ -138,12 +140,6 @@ static void ws_recv(struct shell_websocket *ws, struct zsock_pollfd *pollfd)
 	}
 
 	len = ret;
-
-	if (len == 0) {
-		k_mutex_unlock(&ws->rx_lock);
-		return;
-	}
-
 	ws->rx_len += len;
 
 	k_mutex_unlock(&ws->rx_lock);
@@ -212,8 +208,9 @@ static int shell_ws_init(struct shell_websocket *ctx, int ws_socket)
 		LOG_ERR("Failed to register socket service, %d", ret);
 		goto error;
 	}
-
-	log_backend_ws_register(ws_socket);
+	if (IS_ENABLED(CONFIG_LOG_BACKEND_WS)) {
+		log_backend_ws_register(ws_socket);
+	}
 
 	return 0;
 
@@ -377,7 +374,7 @@ const struct shell_transport_api shell_websocket_transport_api = {
 	.read = sh_read
 };
 
-int shell_websocket_setup(int ws_socket, void *user_data)
+int shell_websocket_setup(int ws_socket, struct http_request_ctx *request_ctx, void *user_data)
 {
 	struct shell_websocket *ws = user_data;
 
@@ -386,7 +383,8 @@ int shell_websocket_setup(int ws_socket, void *user_data)
 
 int shell_websocket_enable(const struct shell *sh)
 {
-	bool log_backend = CONFIG_SHELL_WEBSOCKET_INIT_LOG_LEVEL > 0;
+	bool log_backend = CONFIG_SHELL_WEBSOCKET_INIT_LOG_LEVEL > 0 &&
+			   !IS_ENABLED(CONFIG_LOG_BACKEND_WS);
 	uint32_t level = (CONFIG_SHELL_WEBSOCKET_INIT_LOG_LEVEL > LOG_LEVEL_DBG) ?
 		CONFIG_LOG_MAX_LEVEL : CONFIG_SHELL_WEBSOCKET_INIT_LOG_LEVEL;
 	static const struct shell_backend_config_flags cfg_flags =
diff --git a/subsys/shell/modules/kernel_service/CMakeLists.txt b/subsys/shell/modules/kernel_service/CMakeLists.txt
index 0bc582df690..7ec9280701c 100644
--- a/subsys/shell/modules/kernel_service/CMakeLists.txt
+++ b/subsys/shell/modules/kernel_service/CMakeLists.txt
@@ -18,4 +18,6 @@ zephyr_sources_ifdef(CONFIG_LOG_RUNTIME_FILTERING log-level.c)
 
 zephyr_sources_ifdef(CONFIG_REBOOT reboot.c)
 
+zephyr_sources_ifdef(CONFIG_KERNEL_SHELL_PANIC_CMD panic.c)
+
 add_subdirectory_ifdef(CONFIG_KERNEL_THREAD_SHELL thread)
diff --git a/subsys/shell/modules/kernel_service/Kconfig b/subsys/shell/modules/kernel_service/Kconfig
index f0c27679699..ba95fdf6fa4 100644
--- a/subsys/shell/modules/kernel_service/Kconfig
+++ b/subsys/shell/modules/kernel_service/Kconfig
@@ -29,4 +29,11 @@ config KERNEL_SHELL_REBOOT_DELAY
 
 rsource "thread/Kconfig"
 
+config KERNEL_SHELL_PANIC_CMD
+	bool "Add a panic command"
+	help
+	  Whether a fatal error handler is installed or not, it may come in
+	  handy to have a way to generate a kernel panic as if something had
+	  crashed, but reliably through the shell.
+
 endif # KERNEL_SHELL
diff --git a/subsys/shell/modules/kernel_service/log-level.c b/subsys/shell/modules/kernel_service/log-level.c
index 70a3142d00b..31ecfa0b730 100644
--- a/subsys/shell/modules/kernel_service/log-level.c
+++ b/subsys/shell/modules/kernel_service/log-level.c
@@ -17,6 +17,8 @@ static int cmd_kernel_log_level_set(const struct shell *sh, size_t argc, char **
 
 	uint8_t severity = shell_strtoul(argv[2], 10, &err);
 
+	shell_warn(sh, "This command is deprecated as it is a duplicate. "
+		       "Use 'log enable' command from logging commands set.");
 	if (err) {
 		shell_error(sh, "Unable to parse log severity (err %d)", err);
 
@@ -34,6 +36,7 @@ static int cmd_kernel_log_level_set(const struct shell *sh, size_t argc, char **
 	/* log_filter_set() takes an int16_t for the source ID */
 	if (source_id < 0) {
 		shell_error(sh, "Unable to find log source: %s", argv[1]);
+		return -EINVAL;
 	}
 
 	log_filter_set(NULL, 0, (int16_t)source_id, severity);
diff --git a/subsys/shell/modules/kernel_service/panic.c b/subsys/shell/modules/kernel_service/panic.c
new file mode 100644
index 00000000000..1fb66bdcbe1
--- /dev/null
+++ b/subsys/shell/modules/kernel_service/panic.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025 Bang & Olufsen
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "kernel_shell.h"
+
+#include <zephyr/sys/reboot.h>
+
+static int cmd_kernel_panic(const struct shell *sh,
+			    size_t argc, char **argv)
+{
+	ARG_UNUSED(argc);
+	ARG_UNUSED(argv);
+
+	k_panic();
+
+	return 0;
+}
+
+KERNEL_CMD_ADD(panic, NULL, "Please, panic now!", cmd_kernel_panic);
diff --git a/subsys/shell/modules/kernel_service/thread/CMakeLists.txt b/subsys/shell/modules/kernel_service/thread/CMakeLists.txt
index 25690a550d0..0fb86cb69f3 100644
--- a/subsys/shell/modules/kernel_service/thread/CMakeLists.txt
+++ b/subsys/shell/modules/kernel_service/thread/CMakeLists.txt
@@ -16,3 +16,9 @@ zephyr_sources_ifdef(CONFIG_KERNEL_THREAD_SHELL_MASK pin.c)
 zephyr_sources_ifdef(CONFIG_KERNEL_THREAD_SHELL_STACKS stacks.c)
 
 zephyr_sources_ifdef(CONFIG_KERNEL_THREAD_SHELL_UNWIND unwind.c)
+
+zephyr_sources_ifdef(CONFIG_KERNEL_THREAD_SHELL_SUSPEND suspend.c)
+
+zephyr_sources_ifdef(CONFIG_KERNEL_THREAD_SHELL_RESUME resume.c)
+
+zephyr_sources_ifdef(CONFIG_KERNEL_THREAD_SHELL_KILL kill.c)
diff --git a/subsys/shell/modules/kernel_service/thread/Kconfig b/subsys/shell/modules/kernel_service/thread/Kconfig
index 4a6ccf10981..fb56423ce67 100644
--- a/subsys/shell/modules/kernel_service/thread/Kconfig
+++ b/subsys/shell/modules/kernel_service/thread/Kconfig
@@ -5,6 +5,7 @@
 
 config KERNEL_THREAD_SHELL
 	bool
+	depends on THREAD_MONITOR
 	help
 	  Internal helper macro to determine if the main `thread` command
 	  should be compiled.
@@ -52,3 +53,27 @@ config KERNEL_THREAD_SHELL_UNWIND
 	select KERNEL_THREAD_SHELL
 	help
 	  Internal helper macro to compile the `unwind` subcommand
+
+config KERNEL_THREAD_SHELL_SUSPEND
+	bool
+	default y
+	depends on THREAD_MONITOR
+	select KERNEL_THREAD_SHELL
+	help
+	  Internal helper macro to compile the 'suspend' subcommand
+
+config KERNEL_THREAD_SHELL_RESUME
+	bool
+	default y
+	depends on THREAD_MONITOR
+	select KERNEL_THREAD_SHELL
+	help
+	  Internal helper macro to compile the 'resume' subcommand
+
+config KERNEL_THREAD_SHELL_KILL
+	bool
+	default y
+	depends on THREAD_MONITOR
+	select KERNEL_THREAD_SHELL
+	help
+	  Internal helper macro to compile the 'kill' subcommad
diff --git a/subsys/shell/modules/kernel_service/thread/kill.c b/subsys/shell/modules/kernel_service/thread/kill.c
new file mode 100644
index 00000000000..2653e48373c
--- /dev/null
+++ b/subsys/shell/modules/kernel_service/thread/kill.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "kernel_shell.h"
+
+#include <kernel_internal.h>
+#include <zephyr/kernel.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+static int cmd_kernel_thread_kill(const struct shell *sh, size_t argc, char **argv)
+{
+	/* thread_id is converetd from hex to decimal */
+	k_tid_t thread_id = (k_tid_t)strtoul(argv[1], NULL, 16);
+
+	if (!z_thread_is_valid(thread_id)) {
+		shell_error(sh, "Thread ID %p is not valid", thread_id);
+		return -EINVAL;
+	}
+
+	/*Check if the thread ID is the shell thread */
+	if (thread_id == k_current_get()) {
+		shell_error(sh, "Error:Shell thread cannot be killed");
+		return -EINVAL;
+	}
+
+	k_thread_abort(thread_id);
+
+	shell_print(sh, "\n Thread %p killed", thread_id);
+
+	return 0;
+}
+
+KERNEL_THREAD_CMD_ARG_ADD(kill, NULL, "kernel thread kill <thread_id>", cmd_kernel_thread_kill, 2,
+			  0);
diff --git a/subsys/shell/modules/kernel_service/thread/resume.c b/subsys/shell/modules/kernel_service/thread/resume.c
new file mode 100644
index 00000000000..01590845b12
--- /dev/null
+++ b/subsys/shell/modules/kernel_service/thread/resume.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "kernel_shell.h"
+
+#include <kernel_internal.h>
+#include <zephyr/kernel.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+static int cmd_kernel_thread_resume(const struct shell *sh, size_t argc, char **argv)
+{
+	/* thread_id is converetd from hex to decimal */
+	k_tid_t thread_id = (k_tid_t)strtoul(argv[1], NULL, 16);
+
+	if (!z_thread_is_valid(thread_id)) {
+		shell_error(sh, "Thread ID %p is not valid", thread_id);
+		return -EINVAL;
+	}
+
+	/*Check if the thread ID is the shell thread */
+	if (thread_id == k_current_get()) {
+		shell_error(sh, "Error:Shell thread cannot be resumed");
+		return -EINVAL;
+	}
+
+	k_thread_resume(thread_id);
+
+	shell_print(sh, "Thread %p resumed", thread_id);
+
+	return 0;
+}
+
+KERNEL_THREAD_CMD_ARG_ADD(resume, NULL, "kernel thread resume <thread_id>",
+			  cmd_kernel_thread_resume, 2, 0);
diff --git a/subsys/shell/modules/kernel_service/thread/suspend.c b/subsys/shell/modules/kernel_service/thread/suspend.c
new file mode 100644
index 00000000000..0790a898a20
--- /dev/null
+++ b/subsys/shell/modules/kernel_service/thread/suspend.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "kernel_shell.h"
+
+#include <kernel_internal.h>
+#include <zephyr/kernel.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+static int cmd_kernel_thread_suspend(const struct shell *sh, size_t argc, char **argv)
+{
+	/* thread_id is converetd from hex to decimal */
+	k_tid_t thread_id = (k_tid_t)strtoul(argv[1], NULL, 16);
+
+	if (!z_thread_is_valid(thread_id)) {
+		shell_error(sh, "Thread ID %p is not valid", thread_id);
+		return -EINVAL;
+	}
+
+	/*Check if the thread ID is the shell thread */
+	if (thread_id == k_current_get()) {
+		shell_error(sh, "Error:Shell thread cannot be suspended");
+		return -EINVAL;
+	}
+
+	k_thread_suspend(thread_id);
+
+	shell_print(sh, "Thread %p suspended", thread_id);
+
+	return 0;
+}
+
+KERNEL_THREAD_CMD_ARG_ADD(suspend, NULL, "kernel thread suspend <thread_id>",
+			  cmd_kernel_thread_suspend, 2, 0);
diff --git a/subsys/shell/shell.c b/subsys/shell/shell.c
index 0032fed7f78..dd268286218 100644
--- a/subsys/shell/shell.c
+++ b/subsys/shell/shell.c
@@ -31,6 +31,7 @@
 	"WARNING: A print request was detected on not active shell backend.\n"
 #define SHELL_MSG_TOO_MANY_ARGS		"Too many arguments in the command.\n"
 #define SHELL_INIT_OPTION_PRINTER	(NULL)
+#define SHELL_TX_MTX_TIMEOUT_MS		50
 
 #define SHELL_THREAD_PRIORITY \
 	COND_CODE_1(CONFIG_SHELL_THREAD_PRIORITY_OVERRIDE, \
@@ -974,7 +975,11 @@ static void state_collect(const struct shell *sh)
 		shell_bypass_cb_t bypass = sh->ctx->bypass;
 
 		if (bypass) {
+#if defined(CONFIG_SHELL_BACKEND_RTT) && defined(CONFIG_SEGGER_RTT_BUFFER_SIZE_DOWN)
+			uint8_t buf[CONFIG_SEGGER_RTT_BUFFER_SIZE_DOWN];
+#else
 			uint8_t buf[16];
+#endif
 
 			(void)sh->iface->api->read(sh->iface, buf,
 							sizeof(buf), &count);
@@ -1154,9 +1159,9 @@ static void state_collect(const struct shell *sh)
 			receive_state_change(sh, SHELL_RECEIVE_DEFAULT);
 			break;
 		}
-	}
 
-	z_transport_buffer_flush(sh);
+		z_transport_buffer_flush(sh);
+	}
 }
 
 static void transport_evt_handler(enum shell_transport_evt evt_type, void *ctx)
@@ -1350,7 +1355,9 @@ void shell_thread(void *shell_handle, void *arg_log_backend,
 			     K_FOREVER);
 
 		if (err != 0) {
-			k_mutex_lock(&sh->ctx->wr_mtx, K_FOREVER);
+			if (k_mutex_lock(&sh->ctx->wr_mtx, K_MSEC(SHELL_TX_MTX_TIMEOUT_MS)) != 0) {
+				return;
+			}
 			z_shell_fprintf(sh, SHELL_ERROR,
 					"Shell thread error: %d", err);
 			k_mutex_unlock(&sh->ctx->wr_mtx);
@@ -1441,7 +1448,9 @@ int shell_start(const struct shell *sh)
 		z_shell_log_backend_enable(sh->log_backend, (void *)sh, sh->ctx->log_level);
 	}
 
-	k_mutex_lock(&sh->ctx->wr_mtx, K_FOREVER);
+	if (k_mutex_lock(&sh->ctx->wr_mtx, K_MSEC(SHELL_TX_MTX_TIMEOUT_MS)) != 0) {
+		return -EBUSY;
+	}
 
 	if (IS_ENABLED(CONFIG_SHELL_VT100_COLORS)) {
 		z_shell_vt100_color_set(sh, SHELL_NORMAL);
@@ -1543,7 +1552,10 @@ void shell_vfprintf(const struct shell *sh, enum shell_vt100_color color,
 		return;
 	}
 
-	k_mutex_lock(&sh->ctx->wr_mtx, K_FOREVER);
+	if (k_mutex_lock(&sh->ctx->wr_mtx, K_MSEC(SHELL_TX_MTX_TIMEOUT_MS)) != 0) {
+		return;
+	}
+
 	if (!z_flag_cmd_ctx_get(sh) && !sh->ctx->bypass && z_flag_use_vt100_get(sh)) {
 		z_shell_cmd_line_erase(sh);
 	}
@@ -1552,6 +1564,7 @@ void shell_vfprintf(const struct shell *sh, enum shell_vt100_color color,
 		z_shell_print_prompt_and_cmd(sh);
 	}
 	z_transport_buffer_flush(sh);
+
 	k_mutex_unlock(&sh->ctx->wr_mtx);
 }
 
@@ -1677,10 +1690,9 @@ int shell_prompt_change(const struct shell *sh, const char *prompt)
 		return -EINVAL;
 	}
 
-	static const size_t mtx_timeout_ms = 20;
 	size_t prompt_length = z_shell_strlen(prompt);
 
-	if (k_mutex_lock(&sh->ctx->wr_mtx, K_MSEC(mtx_timeout_ms))) {
+	if (k_mutex_lock(&sh->ctx->wr_mtx, K_MSEC(SHELL_TX_MTX_TIMEOUT_MS)) != 0) {
 		return -EBUSY;
 	}
 
@@ -1703,7 +1715,9 @@ int shell_prompt_change(const struct shell *sh, const char *prompt)
 
 void shell_help(const struct shell *sh)
 {
-	k_mutex_lock(&sh->ctx->wr_mtx, K_FOREVER);
+	if (k_mutex_lock(&sh->ctx->wr_mtx, K_MSEC(SHELL_TX_MTX_TIMEOUT_MS)) != 0) {
+		return;
+	}
 	shell_internal_help_print(sh);
 	k_mutex_unlock(&sh->ctx->wr_mtx);
 }
@@ -1736,7 +1750,9 @@ int shell_execute_cmd(const struct shell *sh, const char *cmd)
 	sh->ctx->cmd_buff_len = cmd_len;
 	sh->ctx->cmd_buff_pos = cmd_len;
 
-	k_mutex_lock(&sh->ctx->wr_mtx, K_FOREVER);
+	if (k_mutex_lock(&sh->ctx->wr_mtx, K_MSEC(SHELL_TX_MTX_TIMEOUT_MS)) != 0) {
+		return -ENOEXEC;
+	}
 	ret_val = execute(sh);
 	k_mutex_unlock(&sh->ctx->wr_mtx);
 
diff --git a/subsys/shell/shell_log_backend.c b/subsys/shell/shell_log_backend.c
index 38ee97c3ff9..7e2a357da6e 100644
--- a/subsys/shell/shell_log_backend.c
+++ b/subsys/shell/shell_log_backend.c
@@ -161,10 +161,11 @@ static void process_log_msg(const struct shell *sh,
 			     bool locked, bool colors)
 {
 	unsigned int key = 0;
-	uint32_t flags = LOG_OUTPUT_FLAG_LEVEL |
-		      LOG_OUTPUT_FLAG_TIMESTAMP |
-		      (IS_ENABLED(CONFIG_SHELL_LOG_FORMAT_TIMESTAMP) ?
-			LOG_OUTPUT_FLAG_FORMAT_TIMESTAMP : 0);
+	uint32_t flags = LOG_OUTPUT_FLAG_LEVEL | LOG_OUTPUT_FLAG_TIMESTAMP | LOG_OUTPUT_FLAG_THREAD;
+
+	if (IS_ENABLED(CONFIG_SHELL_LOG_FORMAT_TIMESTAMP)) {
+		flags |= LOG_OUTPUT_FLAG_FORMAT_TIMESTAMP;
+	}
 
 	if (colors) {
 		flags |= LOG_OUTPUT_FLAG_COLORS;
diff --git a/subsys/shell/shell_ops.c b/subsys/shell/shell_ops.c
index 54492024d0e..af164d09f79 100644
--- a/subsys/shell/shell_ops.c
+++ b/subsys/shell/shell_ops.c
@@ -250,8 +250,29 @@ static void reprint_from_cursor(const struct shell *sh, uint16_t diff,
 			z_shell_raw_fprintf(sh->fprintf_ctx, "*");
 		}
 	} else {
-		z_shell_fprintf(sh, SHELL_NORMAL, "%s",
-			      &sh->ctx->cmd_buff[sh->ctx->cmd_buff_pos]);
+		/* Check if the reprint will cross a line boundary */
+		int line_len = sh->ctx->cmd_buff_len + z_shell_strlen(sh->ctx->prompt);
+		int buff_pos = sh->ctx->cmd_buff_pos + z_shell_strlen(sh->ctx->prompt);
+
+		if ((buff_pos / sh->ctx->vt100_ctx.cons.terminal_wid) !=
+		    (line_len / sh->ctx->vt100_ctx.cons.terminal_wid)) {
+		       /*
+			* Reprint will take multiple lines.
+			* Print each character directly.
+			*/
+			int pos = sh->ctx->cmd_buff_pos;
+
+			while (buff_pos < line_len) {
+				if (buff_pos++ % sh->ctx->vt100_ctx.cons.terminal_wid == 0U) {
+					z_cursor_next_line_move(sh);
+				}
+				z_shell_fprintf(sh, SHELL_NORMAL, "%c",
+					sh->ctx->cmd_buff[pos++]);
+			}
+		} else {
+			z_shell_fprintf(sh, SHELL_NORMAL, "%s",
+				&sh->ctx->cmd_buff[sh->ctx->cmd_buff_pos]);
+		}
 	}
 	sh->ctx->cmd_buff_pos = sh->ctx->cmd_buff_len;
 
diff --git a/subsys/storage/flash_map/flash_map.c b/subsys/storage/flash_map/flash_map.c
index 7b66825c442..d5b7b20bb0c 100644
--- a/subsys/storage/flash_map/flash_map.c
+++ b/subsys/storage/flash_map/flash_map.c
@@ -82,6 +82,20 @@ int flash_area_erase(const struct flash_area *fa, off_t off, size_t len)
 	return flash_erase(fa->fa_dev, fa->fa_off + off, len);
 }
 
+int flash_area_copy(const struct flash_area *src_fa, off_t src_off,
+		    const struct flash_area *dst_fa, off_t dst_off,
+		    off_t len, uint8_t *buf, size_t buf_size)
+{
+	if (!(is_in_flash_area_bounds(src_fa, src_off, len) &&
+	      is_in_flash_area_bounds(dst_fa, dst_off, len))) {
+		return -EINVAL;
+	}
+
+	return flash_copy(src_fa->fa_dev, src_fa->fa_off + src_off,
+			  dst_fa->fa_dev, dst_fa->fa_off + dst_off, len, buf,
+			  buf_size);
+}
+
 int flash_area_flatten(const struct flash_area *fa, off_t off, size_t len)
 {
 	if (!is_in_flash_area_bounds(fa, off, len)) {
diff --git a/subsys/storage/stream/Kconfig b/subsys/storage/stream/Kconfig
index bed472a038a..1d85491f29e 100644
--- a/subsys/storage/stream/Kconfig
+++ b/subsys/storage/stream/Kconfig
@@ -35,6 +35,20 @@ config STREAM_FLASH_ERASE
 	help
 	  If disabled an external actor must erase the flash area being written
 	  to.
+	  Option available only if there is at least one device in, a configuration,
+	  that requires erase prior to write.
+
+config STREAM_FLASH_ERASE_ONLY_WHEN_SUPPORTED
+	bool "Check if device supports erase prior to attempting one"
+	depends on STREAM_FLASH_ERASE
+	depends on FLASH_HAS_NO_EXPLICIT_ERASE
+	help
+	  This is used in stream flash code to exclude invocation of erase on devices that do not
+	  have such requirement prior to write nor support rase as a way to increase write speed.
+	  Option is available only if there is a mix of devices, in a configuration, where some
+	  support erase and some do not. If user is sure to not use Stream Flash with devices that
+	  have no support for erase, this option may be disabled to discard small amount of code
+	  from final application.
 
 config STREAM_FLASH_PROGRESS
 	bool "Persistent stream write progress"
diff --git a/subsys/storage/stream/stream_flash.c b/subsys/storage/stream/stream_flash.c
index cdb1885885e..8155ef3dfe3 100644
--- a/subsys/storage/stream/stream_flash.c
+++ b/subsys/storage/stream/stream_flash.c
@@ -60,9 +60,9 @@ static int settings_direct_loader(const char *key, size_t len,
 				LOG_ERR("Error %d while getting page info", rc);
 				return rc;
 			}
-			ctx->last_erased_page_start_offset = page.start_offset;
+			ctx->erased_up_to = page.start_offset + page.size - ctx->offset;
 		} else {
-			ctx->last_erased_page_start_offset = -1;
+			ctx->erased_up_to = 0;
 		}
 #endif /* CONFIG_STREAM_FLASH_ERASE */
 	}
@@ -72,7 +72,64 @@ static int settings_direct_loader(const char *key, size_t len,
 
 #endif /* CONFIG_STREAM_FLASH_PROGRESS */
 
-#ifdef CONFIG_STREAM_FLASH_ERASE
+/* Will erase at most what is required to append given size, If already
+ * erased space can accommodate requested size, then no new page will
+ * be erased.
+ * Note that this function is supposed to fulfill hardware requirements
+ * for erase prior to write or allow faster writes when hardware supports
+ * erase as means to speed up writes, and will do nothing on devices that
+ * that not require erase before write.
+ */
+static int stream_flash_erase_to_append(struct stream_flash_ctx *ctx, size_t size)
+{
+	int rc = 0;
+#if defined(CONFIG_STREAM_FLASH_ERASE)
+	struct flash_pages_info page;
+#if defined(CONFIG_STREAM_FLASH_ERASE_ONLY_WHEN_SUPPORTED)
+	const struct flash_parameters *fparams = flash_get_parameters(ctx->fdev);
+#endif
+
+	/* ctx->erased_up_to points to first offset that has not yet been erased,
+	 * relative to ctx->offset.
+	 */
+	if (ctx->bytes_written + size <= ctx->erased_up_to) {
+		return 0;
+	}
+
+	/* Trying to append beyond available range? */
+	if (ctx->bytes_written + size > ctx->available) {
+		return -ERANGE;
+	}
+
+#if defined(CONFIG_STREAM_FLASH_ERASE_ONLY_WHEN_SUPPORTED)
+	/* Stream flash does not rely on erase, it does it when device needs it */
+	if (!(flash_params_get_erase_cap(fparams) & FLASH_ERASE_C_EXPLICIT)) {
+		return 0;
+	}
+#endif
+	/* Note that ctx->erased_up_to is offset relative to ctx->offset that
+	 * points to first byte not yet erased.
+	 */
+	rc = flash_get_page_info_by_offs(ctx->fdev, ctx->offset + ctx->erased_up_to, &page);
+	if (rc != 0) {
+		LOG_ERR("Error %d while getting page info", rc);
+		return rc;
+	}
+
+	LOG_DBG("Erasing page at offset 0x%08lx", (long)page.start_offset);
+
+	rc = flash_erase(ctx->fdev, page.start_offset, page.size);
+
+	if (rc != 0) {
+		LOG_ERR("Error %d while erasing page", rc);
+	} else {
+		ctx->erased_up_to += page.size;
+	}
+#endif
+	return rc;
+}
+
+#if defined(CONFIG_STREAM_FLASH_ERASE)
 
 int stream_flash_erase_page(struct stream_flash_ctx *ctx, off_t off)
 {
@@ -85,6 +142,11 @@ int stream_flash_erase_page(struct stream_flash_ctx *ctx, off_t off)
 		return -ERANGE;
 	}
 
+	/* Do not allow pages that have already been erased */
+	if ((off - ctx->offset) < ctx->erased_up_to) {
+		return -EINVAL;
+	}
+
 #if defined(CONFIG_FLASH_HAS_NO_EXPLICIT_ERASE)
 	/* There are both types of devices */
 	const struct flash_parameters *fparams = flash_get_parameters(ctx->fdev);
@@ -100,7 +162,7 @@ int stream_flash_erase_page(struct stream_flash_ctx *ctx, off_t off)
 		return rc;
 	}
 
-	if (ctx->last_erased_page_start_offset == page.start_offset) {
+	if (ctx->erased_up_to >= page.start_offset + page.size) {
 		return 0;
 	}
 
@@ -111,7 +173,7 @@ int stream_flash_erase_page(struct stream_flash_ctx *ctx, off_t off)
 	if (rc != 0) {
 		LOG_ERR("Error %d while erasing page", rc);
 	} else {
-		ctx->last_erased_page_start_offset = page.start_offset;
+		ctx->erased_up_to = page.start_offset + page.size;
 	}
 
 	return rc;
@@ -137,11 +199,10 @@ static int flash_sync(struct stream_flash_ctx *ctx)
 
 	if (IS_ENABLED(CONFIG_STREAM_FLASH_ERASE)) {
 
-		rc = stream_flash_erase_page(ctx,
-					     write_addr + ctx->buf_bytes - 1);
+		rc = stream_flash_erase_to_append(ctx, ctx->buf_bytes);
 		if (rc < 0) {
-			LOG_ERR("stream_flash_erase_page err %d offset=0x%08zx",
-				rc, write_addr);
+			LOG_ERR("stream_flash_forward_erase %d range=0x%08zx",
+				rc, ctx->buf_bytes);
 			return rc;
 		}
 	}
@@ -343,7 +404,7 @@ int stream_flash_init(struct stream_flash_ctx *ctx, const struct device *fdev,
 
 
 #ifdef CONFIG_STREAM_FLASH_ERASE
-	ctx->last_erased_page_start_offset = -1;
+	ctx->erased_up_to = 0;
 #endif
 	ctx->erase_value = params->erase_value;
 
diff --git a/subsys/task_wdt/Kconfig b/subsys/task_wdt/Kconfig
index b78894a0b3b..92198a90e6e 100644
--- a/subsys/task_wdt/Kconfig
+++ b/subsys/task_wdt/Kconfig
@@ -58,6 +58,16 @@ config TASK_WDT_HW_FALLBACK_DELAY
 	  kernel timer. This is especially important if the hardware watchdog
 	  is clocked by an inaccurate low-speed RC oscillator.
 
+config TASK_WDT_HW_FALLBACK_PAUSE_IN_SLEEP
+	bool "Pause the hardware watchdog in system sleep"
+	depends on TASK_WDT_HW_FALLBACK
+	help
+	  Configure the hardware watchdog to automatically pause when the
+	  system reaches a sleep power state. When the system is resumed, the
+	  watchdog is also automatically resumed.
+	  Note that this feature is supported only by a subset of hardware
+	  watchdogs.
+
 config TASK_WDT_SHELL
 	bool "Task watchdog shell utilities"
 	depends on SHELL
diff --git a/subsys/task_wdt/task_wdt.c b/subsys/task_wdt/task_wdt.c
index 361acc0e156..243012198fe 100644
--- a/subsys/task_wdt/task_wdt.c
+++ b/subsys/task_wdt/task_wdt.c
@@ -44,6 +44,9 @@ static struct k_spinlock channels_lock;
 /* timer used for watchdog handling */
 static struct k_timer timer;
 
+/* Tell whether the Task Watchdog has been fully initialized. */
+static bool task_wdt_initialized;
+
 #ifdef CONFIG_TASK_WDT_HW_FALLBACK
 /* pointer to the hardware watchdog used as a fallback */
 static const struct device *hw_wdt_dev;
@@ -149,6 +152,8 @@ int task_wdt_init(const struct device *hw_wdt)
 	k_timer_init(&timer, task_wdt_trigger, NULL);
 	schedule_next_timeout(sys_clock_tick_get());
 
+	task_wdt_initialized = true;
+
 	return 0;
 }
 
@@ -179,7 +184,11 @@ int task_wdt_add(uint32_t reload_period, task_wdt_callback_t callback,
 			if (!hw_wdt_started && hw_wdt_dev) {
 				/* also start fallback hw wdt */
 				wdt_setup(hw_wdt_dev,
-					WDT_OPT_PAUSE_HALTED_BY_DBG);
+					WDT_OPT_PAUSE_HALTED_BY_DBG
+#ifdef CONFIG_TASK_WDT_HW_FALLBACK_PAUSE_IN_SLEEP
+					| WDT_OPT_PAUSE_IN_SLEEP
+#endif
+				);
 				hw_wdt_started = true;
 			}
 #endif
@@ -242,3 +251,68 @@ int task_wdt_feed(int channel_id)
 
 	return 0;
 }
+
+void task_wdt_suspend(void)
+{
+	k_spinlock_key_t key;
+
+	/*
+	 * Allow the function to be called from a custom PM policy callback, even when
+	 * the Task Watchdog was not initialized yet.
+	 */
+	if (!task_wdt_initialized) {
+		return;
+	}
+
+	/*
+	 * Prevent all task watchdog channels from triggering.
+	 * Protect the timer access with the spinlock to avoid the timer being started
+	 * concurrently by a call to schedule_next_timeout().
+	 */
+	key = k_spin_lock(&channels_lock);
+	k_timer_stop(&timer);
+	k_spin_unlock(&channels_lock, key);
+
+#ifdef CONFIG_TASK_WDT_HW_FALLBACK
+	/*
+	 * Give a whole hardware watchdog timer period of time to the application to put
+	 * the system in a suspend mode that will pause the hardware watchdog.
+	 */
+	if (hw_wdt_started) {
+		wdt_feed(hw_wdt_dev, hw_wdt_channel);
+	}
+#endif
+}
+
+void task_wdt_resume(void)
+{
+	k_spinlock_key_t key;
+	int64_t current_ticks;
+
+	/*
+	 * Allow the function to be called from a custom PM policy callback, even when
+	 * the Task Watchdog was not initialized yet.
+	 */
+	if (!task_wdt_initialized) {
+		return;
+	}
+
+	key = k_spin_lock(&channels_lock);
+
+	/*
+	 * Feed all enabled channels, so the application threads have time to resume
+	 * feeding the channels by themselves.
+	 */
+	current_ticks = sys_clock_tick_get();
+	for (size_t id = 0; id < ARRAY_SIZE(channels); id++) {
+		if (channels[id].reload_period != 0) {
+			channels[id].timeout_abs_ticks = current_ticks +
+				k_ms_to_ticks_ceil64(channels[id].reload_period);
+		}
+	}
+
+	/* Restart the Task Watchdog timer */
+	schedule_next_timeout(current_ticks);
+
+	k_spin_unlock(&channels_lock, key);
+}
diff --git a/subsys/testsuite/arch/Kconfig.v1 b/subsys/testsuite/arch/Kconfig.v1
deleted file mode 100644
index 28d4b43df0b..00000000000
--- a/subsys/testsuite/arch/Kconfig.v1
+++ /dev/null
@@ -1,4 +0,0 @@
-# Copyright (c) 2023 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-rsource "unit_testing/Kconfig"
diff --git a/subsys/testsuite/boards/unit_testing/unit_testing/unit_testing.yaml b/subsys/testsuite/boards/unit_testing/unit_testing/unit_testing.yaml
index 8fc75ad3b80..0c86abf81a1 100644
--- a/subsys/testsuite/boards/unit_testing/unit_testing/unit_testing.yaml
+++ b/subsys/testsuite/boards/unit_testing/unit_testing/unit_testing.yaml
@@ -4,5 +4,6 @@ type: unit
 arch: unit
 toolchain:
   - host
+  - llvm
 testing:
   default: true
diff --git a/subsys/testsuite/include/zephyr/interrupt_util.h b/subsys/testsuite/include/zephyr/interrupt_util.h
index a3653618d97..6bb9168c33c 100644
--- a/subsys/testsuite/include/zephyr/interrupt_util.h
+++ b/subsys/testsuite/include/zephyr/interrupt_util.h
@@ -7,8 +7,6 @@
 #ifndef INTERRUPT_UTIL_H_
 #define INTERRUPT_UTIL_H_
 
-#define MS_TO_US(ms)  (ms * USEC_PER_MSEC)
-
 #if defined(CONFIG_CPU_CORTEX_M)
 #include <cmsis_core.h>
 
@@ -166,7 +164,7 @@ static inline void trigger_irq(int irq)
 }
 
 #elif defined(CONFIG_RISCV)
-#if defined(CONFIG_NUCLEI_ECLIC) || defined(CONFIG_NRFX_CLIC)
+#if defined(CONFIG_CLIC) || defined(CONFIG_NRFX_CLIC)
 void riscv_clic_irq_set_pending(uint32_t irq);
 static inline void trigger_irq(int irq)
 {
diff --git a/subsys/testsuite/include/zephyr/test_toolchain.h b/subsys/testsuite/include/zephyr/test_toolchain.h
new file mode 100644
index 00000000000..5ae731890bb
--- /dev/null
+++ b/subsys/testsuite/include/zephyr/test_toolchain.h
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2025 Google, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_TESTSUITE_INCLUDE_TEST_TOOLCHAIN_H_
+#define ZEPHYR_TESTSUITE_INCLUDE_TEST_TOOLCHAIN_H_
+
+#include <zephyr/toolchain.h>
+
+#if defined(__llvm__) || (defined(_LINKER) && defined(__LLD_LINKER_CMD__))
+#include <zephyr/test_toolchain/llvm.h>
+#elif defined(__GNUC__) || (defined(_LINKER) && defined(__GCC_LINKER_CMD__))
+#include <zephyr/test_toolchain/gcc.h>
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_ALLOC_SIZE_LARGER_THAN
+ * @brief Toolchain-specific warning for allocations larger than a given size.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_ALLOC_SIZE_LARGER_THAN
+#define TOOLCHAIN_WARNING_ALLOC_SIZE_LARGER_THAN
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_DANGLING_POINTER
+ * @brief Toolchain-specific warning for dangling pointers.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_DANGLING_POINTER
+#define TOOLCHAIN_WARNING_DANGLING_POINTER
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_FORMAT_TRUNCATION
+ * @brief Toolchain-specific warning for format truncation.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_FORMAT_TRUNCATION
+#define TOOLCHAIN_WARNING_FORMAT_TRUNCATION
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_INFINITE_RECURSION
+ * @brief Toolchain-specific warning for infinite recursion.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_INFINITE_RECURSION
+#define TOOLCHAIN_WARNING_INFINITE_RECURSION
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_INTEGER_OVERFLOW
+ * @brief Toolchain-specific warning for integer overflow.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_INTEGER_OVERFLOW
+#define TOOLCHAIN_WARNING_INTEGER_OVERFLOW
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_OVERFLOW
+ * @brief Toolchain-specific warning for integer overflow.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_OVERFLOW
+#define TOOLCHAIN_WARNING_OVERFLOW
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_PRAGMAS
+ * @brief Toolchain-specific warning for unknown pragmas.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_PRAGMAS
+#define TOOLCHAIN_WARNING_PRAGMAS
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_SIZEOF_ARRAY_DECAY
+ * @brief Toolchain-specific warning for sizeof array decay.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_SIZEOF_ARRAY_DECAY
+#define TOOLCHAIN_WARNING_SIZEOF_ARRAY_DECAY
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_STRINGOP_OVERFLOW
+ * @brief Toolchain-specific warning for stringop overflow.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_STRINGOP_OVERFLOW
+#define TOOLCHAIN_WARNING_STRINGOP_OVERFLOW
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_STRINGOP_TRUNCATION
+ * @brief Toolchain-specific warning for stringop truncation.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_STRINGOP_TRUNCATION
+#define TOOLCHAIN_WARNING_STRINGOP_TRUNCATION
+#endif
+
+/**
+ * @def TOOLCHAIN_WARNING_UNUSED_FUNCTION
+ * @brief Toolchain-specific warning for unused function.
+ *
+ * Use this as an argument to the @ref TOOLCHAIN_DISABLE_WARNING and
+ * @ref TOOLCHAIN_ENABLE_WARNING family of macros.
+ */
+#ifndef TOOLCHAIN_WARNING_UNUSED_FUNCTION
+#define TOOLCHAIN_WARNING_UNUSED_FUNCTION
+#endif
+
+#endif
diff --git a/subsys/testsuite/include/zephyr/test_toolchain/gcc.h b/subsys/testsuite/include/zephyr/test_toolchain/gcc.h
new file mode 100644
index 00000000000..4323ac7b497
--- /dev/null
+++ b/subsys/testsuite/include/zephyr/test_toolchain/gcc.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2025 Google, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_TESTSUITE_INCLUDE_TEST_TOOLCHAIN_GCC_H_
+#define ZEPHYR_TESTSUITE_INCLUDE_TEST_TOOLCHAIN_GCC_H_
+
+#ifndef ZEPHYR_TESTSUITE_INCLUDE_TEST_TOOLCHAIN_H_
+#error "Please do not include test toolchain-specific headers directly, \
+use <zephyr/test_toolchain.h> instead"
+#endif
+
+#define TOOLCHAIN_WARNING_DANGLING_POINTER   "-Wdangling-pointer"
+#define TOOLCHAIN_WARNING_FORMAT_TRUNCATION  "-Wformat-truncation"
+#define TOOLCHAIN_WARNING_INFINITE_RECURSION "-Winfinite-recursion"
+#define TOOLCHAIN_WARNING_OVERFLOW           "-Woverflow"
+#define TOOLCHAIN_WARNING_PRAGMAS            "-Wpragmas"
+#define TOOLCHAIN_WARNING_UNUSED_FUNCTION    "-Wunused-function"
+
+/* GCC-specific warnings that aren't in clang. */
+#if defined(__GNUC__) && !defined(__clang__)
+#define TOOLCHAIN_WARNING_ALLOC_SIZE_LARGER_THAN "-Walloc-size-larger-than="
+#define TOOLCHAIN_WARNING_STRINGOP_OVERFLOW      "-Wstringop-overflow"
+#define TOOLCHAIN_WARNING_STRINGOP_TRUNCATION    "-Wstringop-truncation"
+#endif
+
+#endif
diff --git a/subsys/testsuite/include/zephyr/test_toolchain/llvm.h b/subsys/testsuite/include/zephyr/test_toolchain/llvm.h
new file mode 100644
index 00000000000..3dd26015851
--- /dev/null
+++ b/subsys/testsuite/include/zephyr/test_toolchain/llvm.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Google, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_TESTSUITE_INCLUDE_TEST_TOOLCHAIN_LLVM_H_
+#define ZEPHYR_TESTSUITE_INCLUDE_TEST_TOOLCHAIN_LLVM_H_
+
+#ifndef ZEPHYR_TESTSUITE_INCLUDE_TEST_TOOLCHAIN_H_
+#error "Please do not include test toolchain-specific headers directly, \
+use <zephyr/test_toolchain.h> instead"
+#endif
+
+#include <zephyr/test_toolchain/gcc.h>
+
+#define TOOLCHAIN_WARNING_INTEGER_OVERFLOW "-Winteger-overflow"
+
+#endif
diff --git a/subsys/testsuite/ztest/Kconfig b/subsys/testsuite/ztest/Kconfig
index 02eb742dcf1..df7cda1f856 100644
--- a/subsys/testsuite/ztest/Kconfig
+++ b/subsys/testsuite/ztest/Kconfig
@@ -101,6 +101,7 @@ config ZTEST_ASSERT_HOOK
 
 config ZTEST_NO_YIELD
 	bool "Do not yield to the idle thread after tests complete"
+	default y if PM
 	help
 	  When the tests complete, do not yield to the idle thread and instead
 	  spin in a loop. This is useful for low power mode tests, where
@@ -207,7 +208,6 @@ config ZTEST_VERBOSE_SUMMARY
 
 config ZTEST_FAIL_ON_ASSUME
 	bool "Fail the test run when an assumption fails"
-	default y
 	help
 	  When enabled, the test binary will fail at the end if an assumption failed. This means
 	  that while tests will still be marked as skipped on failed zassume calls, the final test
diff --git a/subsys/testsuite/ztest/src/ztest.c b/subsys/testsuite/ztest/src/ztest.c
index d2a9fe8051d..60af1dd3453 100644
--- a/subsys/testsuite/ztest/src/ztest.c
+++ b/subsys/testsuite/ztest/src/ztest.c
@@ -393,8 +393,10 @@ void ztest_skip_failed_assumption(void)
 {
 	if (IS_ENABLED(CONFIG_ZTEST_FAIL_ON_ASSUME)) {
 		current_test_failed_assumption = true;
+		ztest_test_fail();
+	} else {
+		ztest_test_skip();
 	}
-	ztest_test_skip();
 }
 
 #ifndef KERNEL
@@ -921,32 +923,6 @@ int z_ztest_run_test_suite(const char *name, bool shuffle,
 K_APPMEM_PARTITION_DEFINE(ztest_mem_partition);
 #endif
 
-static void __ztest_init_unit_test_result_for_suite(struct ztest_suite_node *suite)
-{
-	struct ztest_unit_test *test = NULL;
-
-	while (((test = z_ztest_get_next_test(suite->name, test)) != NULL)) {
-		test->stats->run_count = 0;
-		test->stats->skip_count = 0;
-		test->stats->fail_count = 0;
-		test->stats->pass_count = 0;
-		test->stats->duration_worst_ms = 0;
-	}
-}
-
-static void flush_log(void)
-{
-	if (IS_ENABLED(CONFIG_LOG_PROCESS_THREAD)) {
-		while (log_data_pending()) {
-			k_sleep(K_MSEC(10));
-		}
-		k_sleep(K_MSEC(10));
-	} else {
-		while (LOG_PROCESS()) {
-		}
-	}
-}
-
 /* Show one line summary for a test suite.
  */
 static void __ztest_show_suite_summary_oneline(struct ztest_suite_node *suite)
@@ -994,7 +970,7 @@ static void __ztest_show_suite_summary_oneline(struct ztest_suite_node *suite)
 			 TC_RESULT_TO_STR(suite_result), passrate_major, passrate_minor,
 			 suite->name, distinct_pass, distinct_fail, distinct_skip, distinct_total,
 			 suite_duration_worst_ms / 1000, suite_duration_worst_ms % 1000);
-	flush_log();
+	log_flush();
 }
 
 static void __ztest_show_suite_summary_verbose(struct ztest_suite_node *suite)
@@ -1035,12 +1011,12 @@ static void __ztest_show_suite_summary_verbose(struct ztest_suite_node *suite)
 
 		if (flush_frequency % 3 == 0) {
 			/** Reduce the flush frequency a bit to speed up the output */
-			flush_log();
+			log_flush();
 		}
 		flush_frequency++;
 	}
 	TC_SUMMARY_PRINT("\n");
-	flush_log();
+	log_flush();
 }
 
 static void __ztest_show_suite_summary(void)
@@ -1051,9 +1027,9 @@ static void __ztest_show_suite_summary(void)
 	/* Flush the log a lot to ensure that no summary content
 	 * is dropped if it goes through the logging subsystem.
 	 */
-	flush_log();
+	log_flush();
 	TC_SUMMARY_PRINT("\n------ TESTSUITE SUMMARY START ------\n\n");
-	flush_log();
+	log_flush();
 	for (struct ztest_suite_node *ptr = _ztest_suite_node_list_start;
 	     ptr < _ztest_suite_node_list_end; ++ptr) {
 
@@ -1061,7 +1037,7 @@ static void __ztest_show_suite_summary(void)
 		__ztest_show_suite_summary_verbose(ptr);
 	}
 	TC_SUMMARY_PRINT("------ TESTSUITE SUMMARY END ------\n\n");
-	flush_log();
+	log_flush();
 }
 
 static int __ztest_run_test_suite(struct ztest_suite_node *ptr, const void *state, bool shuffle,
@@ -1104,9 +1080,6 @@ int z_impl_ztest_run_test_suites(const void *state, bool shuffle, int suite_iter
 	memset(suites_to_run, 0, ZTEST_SUITE_COUNT * sizeof(struct ztest_suite_node *));
 	z_ztest_shuffle(shuffle, (void **)suites_to_run, (intptr_t)_ztest_suite_node_list_start,
 			ZTEST_SUITE_COUNT, sizeof(struct ztest_suite_node));
-	for (size_t i = 0; i < ZTEST_SUITE_COUNT; ++i) {
-		__ztest_init_unit_test_result_for_suite(suites_to_run[i]);
-	}
 	for (size_t i = 0; i < ZTEST_SUITE_COUNT; ++i) {
 		count += __ztest_run_test_suite(suites_to_run[i], state, shuffle, suite_iter,
 						case_iter, param);
@@ -1121,7 +1094,6 @@ int z_impl_ztest_run_test_suites(const void *state, bool shuffle, int suite_iter
 #else
 	for (struct ztest_suite_node *ptr = _ztest_suite_node_list_start;
 	     ptr < _ztest_suite_node_list_end; ++ptr) {
-		__ztest_init_unit_test_result_for_suite(ptr);
 		count += __ztest_run_test_suite(ptr, state, shuffle, suite_iter, case_iter, param);
 		/* Stop running tests if we have a critical error or if we have a failure and
 		 * FAIL_FAST was set
@@ -1378,7 +1350,6 @@ static int cmd_run_suite(const struct shell *sh, size_t argc, char **argv)
 
 	for (struct ztest_suite_node *ptr = _ztest_suite_node_list_start;
 	     ptr < _ztest_suite_node_list_end; ++ptr) {
-		__ztest_init_unit_test_result_for_suite(ptr);
 		if (strcmp(shell_command, "run-testcase") == 0) {
 			count += __ztest_run_test_suite(ptr, NULL, shuffle, 1, repeat_iter, param);
 		} else if (strcmp(shell_command, "run-testsuite") == 0) {
@@ -1474,7 +1445,7 @@ int main(void)
 #ifndef CONFIG_ZTEST_SHELL
 	test_main();
 	end_report();
-	flush_log();
+	log_flush();
 	LOG_PANIC();
 	if (IS_ENABLED(CONFIG_ZTEST_RETEST_IF_PASSED)) {
 		static __noinit struct {
diff --git a/subsys/testsuite/ztest/src/ztest_mock.c b/subsys/testsuite/ztest/src/ztest_mock.c
index 1147807b2e5..66cb0c740a7 100644
--- a/subsys/testsuite/ztest/src/ztest_mock.c
+++ b/subsys/testsuite/ztest/src/ztest_mock.c
@@ -253,7 +253,7 @@ void z_ztest_check_expected_data(const char *fn, const char *name, void *data, u
 		ztest_test_fail();
 	} else if (data != NULL) {
 		if (memcmp(data, expected, length) != 0) {
-			PRINT_DATA("%s:%s data provided don't match\n", fn, name);
+			PRINT_DATA("%s:%s data provided doesn't match\n", fn, name);
 			ztest_test_fail();
 		}
 	}
@@ -329,7 +329,7 @@ int z_cleanup_mock(void)
 		fail = 1;
 	}
 	if (return_value_list.next) {
-		PRINT_DATA("Return value no used by mock: %s\n", return_value_list.next->fn);
+		PRINT_DATA("Return value not used by mock: %s\n", return_value_list.next->fn);
 		fail = 2;
 	}
 
diff --git a/subsys/tracing/CMakeLists.txt b/subsys/tracing/CMakeLists.txt
index 98c0939c982..2ee3ac518e5 100644
--- a/subsys/tracing/CMakeLists.txt
+++ b/subsys/tracing/CMakeLists.txt
@@ -48,11 +48,9 @@ zephyr_sources_ifdef(
 
 endif()
 
-if(NOT CONFIG_PERCEPIO_TRACERECORDER AND NOT CONFIG_TRACING_CTF
-  AND NOT CONFIG_SEGGER_SYSTEMVIEW AND NOT CONFIG_TRACING_TEST
-  AND NOT CONFIG_TRACING_USER)
-  zephyr_sources(tracing_none.c)
-endif()
+zephyr_sources(
+  tracing_none.c
+  )
 
 zephyr_sources_ifdef(
   CONFIG_TRACING_OBJECT_TRACKING
diff --git a/subsys/tracing/ctf/ctf_top.c b/subsys/tracing/ctf/ctf_top.c
index e65acfa8a96..7acb422f3ef 100644
--- a/subsys/tracing/ctf/ctf_top.c
+++ b/subsys/tracing/ctf/ctf_top.c
@@ -13,6 +13,7 @@
 #include <zephyr/net/socket_poll.h>
 #include <zephyr/net/net_if.h>
 #include <zephyr/net/net_pkt.h>
+#include <zephyr/debug/cpu_load.h>
 
 static void _get_thread_name(struct k_thread *thread,
 			     ctf_bounded_string_t *name)
@@ -189,6 +190,16 @@ void sys_trace_isr_exit_to_scheduler(void)
 void sys_trace_idle(void)
 {
 	ctf_top_idle();
+	if (IS_ENABLED(CONFIG_CPU_LOAD)) {
+		cpu_load_on_enter_idle();
+	}
+}
+
+void sys_trace_idle_exit(void)
+{
+	if (IS_ENABLED(CONFIG_CPU_LOAD)) {
+		cpu_load_on_exit_idle();
+	}
 }
 
 /* Semaphore */
diff --git a/subsys/tracing/ctf/tracing_ctf.h b/subsys/tracing/ctf/tracing_ctf.h
index 30ffb6ff950..c1d8b65bd6b 100644
--- a/subsys/tracing/ctf/tracing_ctf.h
+++ b/subsys/tracing/ctf/tracing_ctf.h
@@ -282,7 +282,18 @@ extern "C" {
 #define sys_port_trace_k_mbox_get_exit(mbox, timeout, ret)
 #define sys_port_trace_k_mbox_data_get(rx_msg)
 
-#define sys_port_trace_k_pipe_init(pipe)
+#define sys_port_trace_k_pipe_init(pipe, buffer, size)
+#define sys_port_trace_k_pipe_reset_enter(pipe)
+#define sys_port_trace_k_pipe_reset_exit(pipe)
+#define sys_port_trace_k_pipe_close_enter(pipe)
+#define sys_port_trace_k_pipe_close_exit(pipe)
+#define sys_port_trace_k_pipe_write_enter(pipe, data, len, timeout)
+#define sys_port_trace_k_pipe_write_blocking(pipe, timeout)
+#define sys_port_trace_k_pipe_write_exit(pipe, ret)
+#define sys_port_trace_k_pipe_read_enter(pipe, data, len, timeout)
+#define sys_port_trace_k_pipe_read_blocking(pipe, timeout)
+#define sys_port_trace_k_pipe_read_exit(pipe, ret)
+
 #define sys_port_trace_k_pipe_cleanup_enter(pipe)
 #define sys_port_trace_k_pipe_cleanup_exit(pipe, ret)
 #define sys_port_trace_k_pipe_alloc_init_enter(pipe)
@@ -300,7 +311,7 @@ extern "C" {
 
 #define sys_port_trace_k_heap_init(heap)
 #define sys_port_trace_k_heap_aligned_alloc_enter(heap, timeout)
-#define sys_port_trace_k_heap_aligned_alloc_blocking(heap, timeout)
+#define sys_port_trace_k_heap_alloc_helper_blocking(heap, timeout)
 #define sys_port_trace_k_heap_aligned_alloc_exit(heap, timeout, ret)
 #define sys_port_trace_k_heap_alloc_enter(heap, timeout)
 #define sys_port_trace_k_heap_alloc_exit(heap, timeout, ret)
@@ -357,6 +368,7 @@ extern "C" {
 #define sys_trace_sys_init_exit(...)
 
 void sys_trace_idle(void);
+void sys_trace_idle_exit(void);
 void sys_trace_isr_enter(void);
 void sys_trace_isr_exit(void);
 
diff --git a/subsys/tracing/sysview/sysview.c b/subsys/tracing/sysview/sysview.c
index 6ca72464bbd..660181e967e 100644
--- a/subsys/tracing/sysview/sysview.c
+++ b/subsys/tracing/sysview/sysview.c
@@ -6,6 +6,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/kernel_structs.h>
 #include <zephyr/init.h>
+#include <zephyr/debug/cpu_load.h>
 #include <ksched.h>
 
 #include <SEGGER_SYSVIEW.h>
@@ -64,6 +65,17 @@ void sys_trace_isr_exit_to_scheduler(void)
 void sys_trace_idle(void)
 {
 	SEGGER_SYSVIEW_OnIdle();
+
+	if (IS_ENABLED(CONFIG_CPU_LOAD)) {
+		cpu_load_on_enter_idle();
+	}
+}
+
+void sys_trace_idle_exit(void)
+{
+	if (IS_ENABLED(CONFIG_CPU_LOAD)) {
+		cpu_load_on_exit_idle();
+	}
 }
 
 void sys_trace_named_event(const char *name, uint32_t arg0, uint32_t arg1)
diff --git a/subsys/tracing/sysview/tracing_sysview.h b/subsys/tracing/sysview/tracing_sysview.h
index 8b669fd22dd..d13ab42dd8d 100644
--- a/subsys/tracing/sysview/tracing_sysview.h
+++ b/subsys/tracing/sysview/tracing_sysview.h
@@ -532,7 +532,18 @@ void sys_trace_thread_info(struct k_thread *thread);
 #define sys_port_trace_k_mbox_get_exit(mbox, timeout, ret)
 #define sys_port_trace_k_mbox_data_get(rx_msg)
 
-#define sys_port_trace_k_pipe_init(pipe)
+#define sys_port_trace_k_pipe_init(pipe, buffer, size)
+#define sys_port_trace_k_pipe_reset_enter(pipe)
+#define sys_port_trace_k_pipe_reset_exit(pipe)
+#define sys_port_trace_k_pipe_close_enter(pipe)
+#define sys_port_trace_k_pipe_close_exit(pipe)
+#define sys_port_trace_k_pipe_write_enter(pipe, data, len, timeout)
+#define sys_port_trace_k_pipe_write_blocking(pipe, timeout)
+#define sys_port_trace_k_pipe_write_exit(pipe, ret)
+#define sys_port_trace_k_pipe_read_enter(pipe, data, len, timeout)
+#define sys_port_trace_k_pipe_read_blocking(pipe, timeout)
+#define sys_port_trace_k_pipe_read_exit(pipe, ret)
+
 #define sys_port_trace_k_pipe_cleanup_enter(pipe)
 #define sys_port_trace_k_pipe_cleanup_exit(pipe, ret)
 #define sys_port_trace_k_pipe_alloc_init_enter(pipe)
@@ -562,7 +573,7 @@ void sys_trace_thread_info(struct k_thread *thread);
 	SEGGER_SYSVIEW_RecordU32x2(TID_HEAP_ALIGNED_ALLOC, (uint32_t)(uintptr_t)heap,              \
 				   (uint32_t)timeout.ticks)
 
-#define sys_port_trace_k_heap_aligned_alloc_blocking(heap, timeout)
+#define sys_port_trace_k_heap_alloc_helper_blocking(heap, timeout)
 
 #define sys_port_trace_k_heap_aligned_alloc_exit(heap, timeout, ret)                               \
 	SEGGER_SYSVIEW_RecordEndCallU32(TID_HEAP_ALIGNED_ALLOC, (uint32_t)ret)
@@ -644,6 +655,7 @@ void sys_trace_thread_info(struct k_thread *thread);
 	SEGGER_SYSVIEW_RecordEndCall(TID_SYSCALL)
 
 void sys_trace_idle(void);
+void sys_trace_idle_exit(void);
 
 void sys_trace_k_thread_create(struct k_thread *new_thread, size_t stack_size, int prio);
 void sys_trace_k_thread_user_mode_enter(k_thread_entry_t entry, void *p1, void *p2, void *p3);
diff --git a/subsys/tracing/test/tracing_string_format_test.c b/subsys/tracing/test/tracing_string_format_test.c
index ddfd7bc70c1..8a53e0bcdb8 100644
--- a/subsys/tracing/test/tracing_string_format_test.c
+++ b/subsys/tracing/test/tracing_string_format_test.c
@@ -204,6 +204,11 @@ void sys_trace_idle(void)
 	TRACING_STRING("%s\n", __func__);
 }
 
+void sys_trace_idle_exit(void)
+{
+	TRACING_STRING("%s\n", __func__);
+}
+
 void sys_trace_k_condvar_broadcast_enter(struct k_condvar *condvar)
 {
 	TRACING_STRING("%s: %p\n", __func__, condvar);
@@ -376,7 +381,7 @@ void sys_trace_k_heap_realloc_exit(struct k_heap *h, void *ptr, size_t bytes, k_
 	TRACING_STRING("%s: %p\n", __func__, h);
 }
 
-void sys_trace_k_heap_aligned_alloc_blocking(struct k_heap *h, size_t bytes, k_timeout_t timeout)
+void sys_trace_k_heap_alloc_helper_blocking(struct k_heap *h, size_t bytes, k_timeout_t timeout)
 {
 	TRACING_STRING("%s: %p\n", __func__, h);
 }
diff --git a/subsys/tracing/test/tracing_test.h b/subsys/tracing/test/tracing_test.h
index 7dddb50a947..a6208337e38 100644
--- a/subsys/tracing/test/tracing_test.h
+++ b/subsys/tracing/test/tracing_test.h
@@ -342,16 +342,31 @@
 	sys_trace_k_mbox_get_exit(mbox, rx_msg, buffer, timeout, ret)
 #define sys_port_trace_k_mbox_data_get(rx_msg) sys_trace_k_mbox_data_get(mbox, rx_msg, buffer)
 
-#define sys_port_trace_k_pipe_init(pipe) sys_trace_k_pipe_init(pipe, buffer, size)
+#define sys_port_trace_k_pipe_init(pipe, buffer, size) sys_trace_k_pipe_init(pipe, buffer, size)
+#define sys_port_trace_k_pipe_reset_enter(pipe) sys_trace_k_pipe_reset_enter(pipe)
+#define sys_port_trace_k_pipe_reset_exit(pipe)  sys_trace_k_pipe_reset_exit(pipe)
+#define sys_port_trace_k_pipe_close_enter(pipe) sys_trace_k_pipe_close_enter(pipe)
+#define sys_port_trace_k_pipe_close_exit(pipe) sys_trace_k_pipe_close_exit(pipe)
+#define sys_port_trace_k_pipe_write_enter(pipe, data, len, timeout) \
+	sys_trace_k_pipe_write_enter(pipe, data, len, timeout)
+#define sys_port_trace_k_pipe_write_blocking(pipe, timeout) \
+	sys_trace_k_pipe_write_blocking(pipe, timeout)
+#define sys_port_trace_k_pipe_write_exit(pipe, ret) \
+	sys_trace_k_pipe_write_exit(pipe, ret)
+#define sys_port_trace_k_pipe_read_enter(pipe, data, size, timeout) \
+	sys_trace_k_pipe_read_enter(pipe, data, size, timeout)
+#define sys_port_trace_k_pipe_read_blocking(pipe, timeout) \
+	sys_trace_k_pipe_read_blocking(pipe, timeout)
+#define sys_port_trace_k_pipe_read_exit(pipe, ret) \
+	sys_trace_k_pipe_read_exit(pipe, ret)
+
 #define sys_port_trace_k_pipe_cleanup_enter(pipe) sys_trace_k_pipe_cleanup_enter(pipe)
 #define sys_port_trace_k_pipe_cleanup_exit(pipe, ret) sys_trace_k_pipe_cleanup_exit(pipe, ret)
 #define sys_port_trace_k_pipe_alloc_init_enter(pipe) sys_trace_k_pipe_alloc_init_enter(pipe, size)
 #define sys_port_trace_k_pipe_alloc_init_exit(pipe, ret)                                           \
 	sys_trace_k_pipe_alloc_init_exit(pipe, size, ret)
-#define sys_port_trace_k_pipe_flush_enter(pipe)  \
-	sys_trace_k_pipe_flush_enter(pipe)
-#define sys_port_trace_k_pipe_flush_exit(pipe)   \
-	sys_trace_k_pipe_flush_exit(pipe)
+#define sys_port_trace_k_pipe_flush_enter(pipe) sys_trace_k_pipe_flush_enter(pipe)
+#define sys_port_trace_k_pipe_flush_exit(pipe)  sys_trace_k_pipe_flush_exit(pipe)
 #define sys_port_trace_k_pipe_buffer_flush_enter(pipe)  \
 	sys_trace_k_pipe_buffer_flush_enter(pipe)
 #define sys_port_trace_k_pipe_buffer_flush_exit(pipe)   \
@@ -373,8 +388,8 @@
 #define sys_port_trace_k_heap_init(h) sys_trace_k_heap_init(h, mem, bytes)
 #define sys_port_trace_k_heap_aligned_alloc_enter(h, timeout)                                      \
 	sys_trace_k_heap_aligned_alloc_enter(h, bytes, timeout)
-#define sys_port_trace_k_heap_aligned_alloc_blocking(h, timeout)                                   \
-	sys_trace_k_heap_aligned_alloc_blocking(h, bytes, timeout)
+#define sys_port_trace_k_heap_alloc_helper_blocking(h, timeout)                                   \
+	sys_trace_k_heap_alloc_helper_blocking(h, bytes, timeout)
 #define sys_port_trace_k_heap_aligned_alloc_exit(h, timeout, ret)                                  \
 	sys_trace_k_heap_aligned_alloc_exit(h, bytes, timeout, ret)
 #define sys_port_trace_k_heap_alloc_enter(h, timeout)                                              \
@@ -465,6 +480,7 @@
 #define sys_port_trace_pm_device_runtime_disable_exit(dev, ret)
 
 void sys_trace_idle(void);
+void sys_trace_idle_exit(void);
 void sys_trace_isr_enter(void);
 void sys_trace_isr_exit(void);
 
@@ -624,6 +640,19 @@ void sys_trace_k_mbox_get_exit(struct k_mbox *mbox, struct k_mbox_msg *rx_msg, v
 void sys_trace_k_mbox_data_get(struct k_mbox *mbox, struct k_mbox_msg *rx_msg, void *buffer);
 
 void sys_trace_k_pipe_init(struct k_pipe *pipe, unsigned char *buffer, size_t size);
+void sys_trace_k_pipe_reset_enter(struct k_pipe *pipe);
+void sys_trace_k_pipe_reset_exit(struct k_pipe *pipe);
+void sys_trace_k_pipe_close_enter(struct k_pipe *pipe);
+void sys_trace_k_pipe_close_exit(struct k_pipe *pipe);
+void sys_trace_k_pipe_write_enter(struct k_pipe *pipe, const void *data, size_t len,
+				  k_timeout_t timeout);
+void sys_trace_k_pipe_write_blocking(struct k_pipe *pipe, k_timeout_t timeout);
+void sys_trace_k_pipe_write_exit(struct k_pipe *pipe, int ret);
+void sys_trace_k_pipe_read_enter(struct k_pipe *pipe, const void *data, size_t len,
+				 k_timeout_t timeout);
+void sys_trace_k_pipe_read_blocking(struct k_pipe *pipe, k_timeout_t timeout);
+void sys_trace_k_pipe_read_exit(struct k_pipe *pipe, int ret);
+
 void sys_trace_k_pipe_cleanup_enter(struct k_pipe *pipe);
 void sys_trace_k_pipe_cleanup_exit(struct k_pipe *pipe, int ret);
 void sys_trace_k_pipe_alloc_init_enter(struct k_pipe *pipe, size_t size);
@@ -668,7 +697,7 @@ void sys_trace_k_heap_calloc_enter(struct k_heap *h, size_t num, size_t size, k_
 void sys_trace_k_heap_calloc_exit(struct k_heap *h, size_t num, size_t size, k_timeout_t timeout,
 				  void *ret);
 void sys_trace_k_heap_aligned_alloc_enter(struct k_heap *h, size_t bytes, k_timeout_t timeout);
-void sys_trace_k_heap_aligned_alloc_blocking(struct k_heap *h, size_t bytes, k_timeout_t timeout);
+void sys_trace_k_heap_alloc_helper_blocking(struct k_heap *h, size_t bytes, k_timeout_t timeout);
 void sys_trace_k_heap_aligned_alloc_exit(struct k_heap *h, size_t bytes, k_timeout_t timeout,
 					 void *ret);
 void sys_trace_k_heap_free(struct k_heap *h, void *mem);
diff --git a/subsys/tracing/tracing_none.c b/subsys/tracing/tracing_none.c
index b630e506dfa..84b4d6549e1 100644
--- a/subsys/tracing/tracing_none.c
+++ b/subsys/tracing/tracing_none.c
@@ -3,12 +3,25 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <zephyr/tracing/tracing.h>
+#include <zephyr/debug/cpu_load.h>
 
+__weak void sys_trace_isr_enter(void) {}
 
-void sys_trace_isr_enter(void) {}
+__weak void sys_trace_isr_exit(void) {}
 
-void sys_trace_isr_exit(void) {}
+__weak void sys_trace_isr_exit_to_scheduler(void) {}
 
-void sys_trace_isr_exit_to_scheduler(void) {}
+__weak void sys_trace_idle(void)
+{
+	if (IS_ENABLED(CONFIG_CPU_LOAD)) {
+		cpu_load_on_enter_idle();
+	}
+}
 
-void sys_trace_idle(void) {}
+__weak void sys_trace_idle_exit(void)
+{
+	if (IS_ENABLED(CONFIG_CPU_LOAD)) {
+		cpu_load_on_exit_idle();
+	}
+}
diff --git a/subsys/tracing/tracing_tracking.c b/subsys/tracing/tracing_tracking.c
index ae115a5a0bc..e257a7b76a2 100644
--- a/subsys/tracing/tracing_tracking.c
+++ b/subsys/tracing/tracing_tracking.c
@@ -31,10 +31,8 @@ struct k_spinlock _track_list_k_msgq_lock;
 struct k_mbox *_track_list_k_mbox;
 struct k_spinlock _track_list_k_mbox_lock;
 
-#ifdef CONFIG_PIPES
 struct k_pipe *_track_list_k_pipe;
 struct k_spinlock _track_list_k_pipe_lock;
-#endif
 
 struct k_queue *_track_list_k_queue;
 struct k_spinlock _track_list_k_queue_lock;
@@ -103,13 +101,14 @@ void sys_track_k_mbox_init(struct k_mbox *mbox)
 			SYS_TRACK_LIST_PREPEND(_track_list_k_mbox, mbox));
 }
 
-#ifdef CONFIG_PIPES
-void sys_track_k_pipe_init(struct k_pipe *pipe)
+void sys_track_k_pipe_init(struct k_pipe *pipe, void *buffer, size_t size)
 {
+	ARG_UNUSED(buffer);
+	ARG_UNUSED(size);
+
 	SYS_PORT_TRACING_TYPE_MASK(k_pipe,
 			SYS_TRACK_LIST_PREPEND(_track_list_k_pipe, pipe));
 }
-#endif
 
 void sys_track_k_queue_init(struct k_queue *queue)
 {
@@ -159,10 +158,8 @@ static int sys_track_static_init(void)
 	SYS_PORT_TRACING_TYPE_MASK(k_mbox,
 			SYS_TRACK_STATIC_INIT(k_mbox));
 
-#ifdef CONFIG_PIPES
 	SYS_PORT_TRACING_TYPE_MASK(k_pipe,
-			SYS_TRACK_STATIC_INIT(k_pipe));
-#endif
+			SYS_TRACK_STATIC_INIT(k_pipe, NULL, 0));
 
 	SYS_PORT_TRACING_TYPE_MASK(k_queue,
 			SYS_TRACK_STATIC_INIT(k_queue));
diff --git a/subsys/tracing/user/tracing_user.c b/subsys/tracing/user/tracing_user.c
index 2453a3e9aad..ff5b945482f 100644
--- a/subsys/tracing/user/tracing_user.c
+++ b/subsys/tracing/user/tracing_user.c
@@ -7,6 +7,7 @@
 
 #include <tracing_user.h>
 #include <zephyr/kernel.h>
+#include <zephyr/debug/cpu_load.h>
 #include <zephyr/init.h>
 
 void __weak sys_trace_thread_create_user(struct k_thread *thread) {}
@@ -143,6 +144,17 @@ void sys_trace_isr_exit(void)
 void sys_trace_idle(void)
 {
 	sys_trace_idle_user();
+
+	if (IS_ENABLED(CONFIG_CPU_LOAD)) {
+		cpu_load_on_enter_idle();
+	}
+}
+
+void sys_trace_idle_exit(void)
+{
+	if (IS_ENABLED(CONFIG_CPU_LOAD)) {
+		cpu_load_on_exit_idle();
+	}
 }
 
 void sys_trace_sys_init_enter(const struct init_entry *entry, int level)
diff --git a/subsys/tracing/user/tracing_user.h b/subsys/tracing/user/tracing_user.h
index 942103e3bb4..9d1fd6f8c7b 100644
--- a/subsys/tracing/user/tracing_user.h
+++ b/subsys/tracing/user/tracing_user.h
@@ -46,6 +46,7 @@ void sys_trace_thread_pend(struct k_thread *thread);
 void sys_trace_isr_enter(void);
 void sys_trace_isr_exit(void);
 void sys_trace_idle(void);
+void sys_trace_idle_exit(void);
 void sys_trace_sys_init_enter(const struct init_entry *entry, int level);
 void sys_trace_sys_init_exit(const struct init_entry *entry, int level, int result);
 
@@ -322,7 +323,18 @@ void sys_trace_gpio_fire_callback_user(const struct device *port, struct gpio_ca
 #define sys_port_trace_k_mbox_get_exit(mbox, timeout, ret)
 #define sys_port_trace_k_mbox_data_get(rx_msg)
 
-#define sys_port_trace_k_pipe_init(pipe)
+#define sys_port_trace_k_pipe_init(pipe, buffer, size)
+#define sys_port_trace_k_pipe_reset_enter(pipe)
+#define sys_port_trace_k_pipe_reset_exit(pipe)
+#define sys_port_trace_k_pipe_close_enter(pipe)
+#define sys_port_trace_k_pipe_close_exit(pipe)
+#define sys_port_trace_k_pipe_write_enter(pipe, data, len, timeout)
+#define sys_port_trace_k_pipe_write_blocking(pipe, timeout)
+#define sys_port_trace_k_pipe_write_exit(pipe, ret)
+#define sys_port_trace_k_pipe_read_enter(pipe, data, len, timeout)
+#define sys_port_trace_k_pipe_read_blocking(pipe, timeout)
+#define sys_port_trace_k_pipe_read_exit(pipe, ret)
+
 #define sys_port_trace_k_pipe_cleanup_enter(pipe)
 #define sys_port_trace_k_pipe_cleanup_exit(pipe, ret)
 #define sys_port_trace_k_pipe_alloc_init_enter(pipe)
@@ -340,7 +352,7 @@ void sys_trace_gpio_fire_callback_user(const struct device *port, struct gpio_ca
 
 #define sys_port_trace_k_heap_init(heap)
 #define sys_port_trace_k_heap_aligned_alloc_enter(heap, timeout)
-#define sys_port_trace_k_heap_aligned_alloc_blocking(heap, timeout)
+#define sys_port_trace_k_heap_alloc_helper_blocking(heap, timeout)
 #define sys_port_trace_k_heap_aligned_alloc_exit(heap, timeout, ret)
 #define sys_port_trace_k_heap_alloc_enter(heap, timeout)
 #define sys_port_trace_k_heap_alloc_exit(heap, timeout, ret)
diff --git a/subsys/usb/device/Kconfig b/subsys/usb/device/Kconfig
index 80c71fb1635..cc5d50676a1 100644
--- a/subsys/usb/device/Kconfig
+++ b/subsys/usb/device/Kconfig
@@ -95,7 +95,6 @@ config USB_REQUEST_BUFFER_SIZE
 	range 8 65536
 	default 256 if USB_DEVICE_NETWORK_RNDIS
 	default 266 if (USB_DEVICE_BLUETOOTH && USB_DEVICE_BLUETOOTH_BIG_BUF)
-	default 1024 if USB_DEVICE_LOOPBACK
 	default 128
 
 config USB_MAX_ALT_SETTING
diff --git a/subsys/usb/device/class/CMakeLists.txt b/subsys/usb/device/class/CMakeLists.txt
index f4d2b39ae70..9911d3fb318 100644
--- a/subsys/usb/device/class/CMakeLists.txt
+++ b/subsys/usb/device/class/CMakeLists.txt
@@ -3,7 +3,6 @@
 zephyr_sources_ifdef(CONFIG_USB_CDC_ACM cdc_acm.c)
 zephyr_sources_ifdef(CONFIG_USB_MASS_STORAGE msc.c)
 zephyr_sources_ifdef(CONFIG_USB_DEVICE_BLUETOOTH bluetooth.c)
-zephyr_sources_ifdef(CONFIG_USB_DEVICE_LOOPBACK loopback.c)
 
 add_subdirectory_ifdef(CONFIG_USB_DEVICE_AUDIO audio)
 add_subdirectory_ifdef(CONFIG_USB_DEVICE_NETWORK netusb)
diff --git a/subsys/usb/device/class/Kconfig b/subsys/usb/device/class/Kconfig
index 9761e969a56..96cb6abe8ba 100644
--- a/subsys/usb/device/class/Kconfig
+++ b/subsys/usb/device/class/Kconfig
@@ -9,8 +9,6 @@ source "subsys/usb/device/class/Kconfig.msc"
 
 source "subsys/usb/device/class/Kconfig.bt"
 
-source "subsys/usb/device/class/Kconfig.test"
-
 source "subsys/usb/device/class/netusb/Kconfig"
 
 source "subsys/usb/device/class/hid/Kconfig"
diff --git a/subsys/usb/device/class/Kconfig.test b/subsys/usb/device/class/Kconfig.test
deleted file mode 100644
index eac1214f0a9..00000000000
--- a/subsys/usb/device/class/Kconfig.test
+++ /dev/null
@@ -1,15 +0,0 @@
-# Copyright (c) 2016 Wind River Systems, Inc.
-# SPDX-License-Identifier: Apache-2.0
-
-config USB_DEVICE_LOOPBACK
-	bool "USB Loopback Function Driver"
-	help
-	  USB Loopback Function Driver
-
-config LOOPBACK_BULK_EP_MPS
-	int
-	depends on USB_DEVICE_LOOPBACK
-	default 512 if USB_DC_HAS_HS_SUPPORT
-	default 64
-	help
-	  Loopback Function bulk endpoint size
diff --git a/subsys/usb/device/class/loopback.c b/subsys/usb/device/class/loopback.c
deleted file mode 100644
index 77c5dde4bda..00000000000
--- a/subsys/usb/device/class/loopback.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * USB loopback function
- *
- * Copyright (c) 2018 Phytec Messtechnik GmbH
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/init.h>
-
-#include <zephyr/sys/byteorder.h>
-#include <zephyr/usb/usb_device.h>
-#include <usb_descriptor.h>
-
-#include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(usb_loopback, CONFIG_USB_DEVICE_LOG_LEVEL);
-
-#define LOOPBACK_OUT_EP_ADDR		0x01
-#define LOOPBACK_IN_EP_ADDR		0x81
-
-#define LOOPBACK_OUT_EP_IDX		0
-#define LOOPBACK_IN_EP_IDX		1
-
-static uint8_t loopback_buf[1024];
-BUILD_ASSERT(sizeof(loopback_buf) == CONFIG_USB_REQUEST_BUFFER_SIZE);
-
-/* usb.rst config structure start */
-struct usb_loopback_config {
-	struct usb_if_descriptor if0;
-	struct usb_ep_descriptor if0_out_ep;
-	struct usb_ep_descriptor if0_in_ep;
-} __packed;
-
-USBD_CLASS_DESCR_DEFINE(primary, 0) struct usb_loopback_config loopback_cfg = {
-	/* Interface descriptor 0 */
-	.if0 = {
-		.bLength = sizeof(struct usb_if_descriptor),
-		.bDescriptorType = USB_DESC_INTERFACE,
-		.bInterfaceNumber = 0,
-		.bAlternateSetting = 0,
-		.bNumEndpoints = 2,
-		.bInterfaceClass = USB_BCC_VENDOR,
-		.bInterfaceSubClass = 0,
-		.bInterfaceProtocol = 0,
-		.iInterface = 0,
-	},
-
-	/* Data Endpoint OUT */
-	.if0_out_ep = {
-		.bLength = sizeof(struct usb_ep_descriptor),
-		.bDescriptorType = USB_DESC_ENDPOINT,
-		.bEndpointAddress = LOOPBACK_OUT_EP_ADDR,
-		.bmAttributes = USB_DC_EP_BULK,
-		.wMaxPacketSize = sys_cpu_to_le16(CONFIG_LOOPBACK_BULK_EP_MPS),
-		.bInterval = 0x00,
-	},
-
-	/* Data Endpoint IN */
-	.if0_in_ep = {
-		.bLength = sizeof(struct usb_ep_descriptor),
-		.bDescriptorType = USB_DESC_ENDPOINT,
-		.bEndpointAddress = LOOPBACK_IN_EP_ADDR,
-		.bmAttributes = USB_DC_EP_BULK,
-		.wMaxPacketSize = sys_cpu_to_le16(CONFIG_LOOPBACK_BULK_EP_MPS),
-		.bInterval = 0x00,
-	},
-};
-/* usb.rst config structure end */
-
-static void loopback_out_cb(uint8_t ep, enum usb_dc_ep_cb_status_code ep_status)
-{
-	uint32_t bytes_to_read;
-
-	usb_read(ep, NULL, 0, &bytes_to_read);
-	LOG_DBG("ep 0x%x, bytes to read %d ", ep, bytes_to_read);
-	usb_read(ep, loopback_buf, bytes_to_read, NULL);
-}
-
-static void loopback_in_cb(uint8_t ep, enum usb_dc_ep_cb_status_code ep_status)
-{
-	if (usb_write(ep, loopback_buf, CONFIG_LOOPBACK_BULK_EP_MPS, NULL)) {
-		LOG_DBG("ep 0x%x", ep);
-	}
-}
-
-/* usb.rst endpoint configuration start */
-static struct usb_ep_cfg_data ep_cfg[] = {
-	{
-		.ep_cb = loopback_out_cb,
-		.ep_addr = LOOPBACK_OUT_EP_ADDR,
-	},
-	{
-		.ep_cb = loopback_in_cb,
-		.ep_addr = LOOPBACK_IN_EP_ADDR,
-	},
-};
-/* usb.rst endpoint configuration end */
-
-static void loopback_status_cb(struct usb_cfg_data *cfg,
-			       enum usb_dc_status_code status,
-			       const uint8_t *param)
-{
-	ARG_UNUSED(cfg);
-
-	switch (status) {
-	case USB_DC_INTERFACE:
-		loopback_in_cb(ep_cfg[LOOPBACK_IN_EP_IDX].ep_addr, 0);
-		LOG_DBG("USB interface configured");
-		break;
-	case USB_DC_SET_HALT:
-		LOG_DBG("Set Feature ENDPOINT_HALT");
-		break;
-	case USB_DC_CLEAR_HALT:
-		LOG_DBG("Clear Feature ENDPOINT_HALT");
-		if (*param == ep_cfg[LOOPBACK_IN_EP_IDX].ep_addr) {
-			loopback_in_cb(ep_cfg[LOOPBACK_IN_EP_IDX].ep_addr, 0);
-		}
-		break;
-	default:
-		break;
-	}
-}
-
-/* usb.rst vendor handler start */
-static int loopback_vendor_handler(struct usb_setup_packet *setup,
-				   int32_t *len, uint8_t **data)
-{
-	LOG_DBG("Class request: bRequest 0x%x bmRequestType 0x%x len %d",
-		setup->bRequest, setup->bmRequestType, *len);
-
-	if (setup->RequestType.recipient != USB_REQTYPE_RECIPIENT_DEVICE) {
-		return -ENOTSUP;
-	}
-
-	if (usb_reqtype_is_to_device(setup) &&
-	    setup->bRequest == 0x5b) {
-		LOG_DBG("Host-to-Device, data %p", *data);
-		/*
-		 * Copy request data in loopback_buf buffer and reuse
-		 * it later in control device-to-host transfer.
-		 */
-		memcpy(loopback_buf, *data,
-		       MIN(sizeof(loopback_buf), setup->wLength));
-		return 0;
-	}
-
-	if ((usb_reqtype_is_to_host(setup)) &&
-	    (setup->bRequest == 0x5c)) {
-		LOG_DBG("Device-to-Host, wLength %d, data %p",
-			setup->wLength, *data);
-		*data = loopback_buf;
-		*len = MIN(sizeof(loopback_buf), setup->wLength);
-		return 0;
-	}
-
-	return -ENOTSUP;
-}
-/* usb.rst vendor handler end */
-
-static void loopback_interface_config(struct usb_desc_header *head,
-				      uint8_t bInterfaceNumber)
-{
-	ARG_UNUSED(head);
-
-	loopback_cfg.if0.bInterfaceNumber = bInterfaceNumber;
-}
-
-/* usb.rst device config data start */
-USBD_DEFINE_CFG_DATA(loopback_config) = {
-	.usb_device_description = NULL,
-	.interface_config = loopback_interface_config,
-	.interface_descriptor = &loopback_cfg.if0,
-	.cb_usb_status = loopback_status_cb,
-	.interface = {
-		.class_handler = NULL,
-		.custom_handler = NULL,
-		.vendor_handler = loopback_vendor_handler,
-	},
-	.num_endpoints = ARRAY_SIZE(ep_cfg),
-	.endpoint = ep_cfg,
-};
-/* usb.rst device config data end */
diff --git a/subsys/usb/device_next/CMakeLists.txt b/subsys/usb/device_next/CMakeLists.txt
index ffd60042fa2..e0120dc89a8 100644
--- a/subsys/usb/device_next/CMakeLists.txt
+++ b/subsys/usb/device_next/CMakeLists.txt
@@ -73,10 +73,30 @@ zephyr_library_sources_ifdef(
 	class/usbd_uac2.c
 )
 
+zephyr_library_sources_ifdef(
+  CONFIG_USBD_MIDI2_CLASS
+  class/usbd_midi2.c
+)
+
 zephyr_library_sources_ifdef(
 	CONFIG_USBD_HID_SUPPORT
 	class/usbd_hid.c
 	class/usbd_hid_api.c
 )
 
+zephyr_library_sources_ifdef(
+  CONFIG_USBD_DFU
+  class/usbd_dfu.c
+)
+
+zephyr_library_sources_ifdef(
+  CONFIG_USBD_DFU_FLASH
+  class/usbd_dfu_flash.c
+)
+
+zephyr_linker_sources_ifdef(
+  CONFIG_USBD_DFU
+  SECTIONS class/usbd_dfu.ld
+)
+
 zephyr_linker_sources(DATA_SECTIONS usbd_data.ld)
diff --git a/subsys/usb/device_next/Kconfig b/subsys/usb/device_next/Kconfig
index 52ce9d99085..68ae7559845 100644
--- a/subsys/usb/device_next/Kconfig
+++ b/subsys/usb/device_next/Kconfig
@@ -16,6 +16,26 @@ module = USBD
 module-str = usbd
 source "subsys/logging/Kconfig.template.log_config"
 
+choice USBD_MAX_SPEED_CHOICE
+	prompt "Max supported connection speed"
+	default USBD_MAX_SPEED_HIGH if UDC_DRIVER_HAS_HIGH_SPEED_SUPPORT
+	default USBD_MAX_SPEED_FULL
+
+config USBD_MAX_SPEED_HIGH
+	bool "High-Speed"
+	depends on UDC_DRIVER_HAS_HIGH_SPEED_SUPPORT
+
+config USBD_MAX_SPEED_FULL
+	bool "Full-Speed"
+	depends on !UDC_DRIVER_HIGH_SPEED_SUPPORT_ENABLED
+
+endchoice
+
+config USBD_MAX_SPEED
+	int
+	default 0 if USBD_MAX_SPEED_FULL
+	default 1 if USBD_MAX_SPEED_HIGH
+
 config USBD_SHELL
 	bool "USB device shell"
 	depends on SHELL
diff --git a/subsys/usb/device_next/class/Kconfig b/subsys/usb/device_next/class/Kconfig
index 9e7393fd3df..fc188653565 100644
--- a/subsys/usb/device_next/class/Kconfig
+++ b/subsys/usb/device_next/class/Kconfig
@@ -10,3 +10,5 @@ rsource "Kconfig.bt"
 rsource "Kconfig.msc"
 rsource "Kconfig.uac2"
 rsource "Kconfig.hid"
+rsource "Kconfig.midi2"
+rsource "Kconfig.dfu"
diff --git a/subsys/usb/device_next/class/Kconfig.dfu b/subsys/usb/device_next/class/Kconfig.dfu
new file mode 100644
index 00000000000..0ee0f8bad2a
--- /dev/null
+++ b/subsys/usb/device_next/class/Kconfig.dfu
@@ -0,0 +1,76 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig USBD_DFU
+	bool "USB DFU Class support"
+	help
+	  USB DFU Class support
+
+if USBD_DFU
+
+config USBD_DFU_NUMOF_IMAGES
+	int "Number of possible DFU images"
+	range 1 256
+	default 4
+	help
+	  Number of possible DFU images.
+
+config USBD_DFU_ENABLE_UPLOAD
+	bool "Allow images to be uploaded to the host"
+	default y
+	help
+	  This option sets the bitCanUpload flag in the DFU attributes and
+	  allows images to be uploaded to the host.
+
+config USBD_DFU_MANIFESTATION_TOLERANT
+	bool "Device is manifestation tolerant"
+	default y
+	help
+	  This option sets the bitManifestationTolerant flag in the DFU
+	  attributes and means that the device can communicate over USB after the
+	  manifestation phase.
+
+config USBD_DFU_TRANSFER_SIZE
+	int "Maximum number of bytes the device can accept per transfer"
+	default 512
+	range 64 1024
+	help
+	  This option sets the wTransferSize in the DFU functional descriptor.
+
+config USBD_DFU_POLLTIMEOUT
+	int "bwPollTimeout value (in ms)"
+	default 10
+	range 0 1000
+	help
+	  This option sets the bwPollTimeout field in DFU_GETSTATUS response.
+
+module = USBD_DFU
+module-str = usbd dfu
+source "subsys/logging/Kconfig.template.log_config"
+
+config USBD_DFU_FLASH
+	depends on FLASH && FLASH_MAP && STREAM_FLASH
+	depends on IMG_MANAGER && IMG_ERASE_PROGRESSIVELY
+	bool "Built-in flash backend"
+	help
+	  Enable the built-in flash backend, which can serve up to two image
+	  slots, which is the common configuration of in-tree boards.
+
+if USBD_DFU_FLASH
+
+config USBD_DFU_FLASH_SLOT0
+	bool "Flash backend for the slot-0 partition"
+	default y
+	help
+	  This option enables download or upload for the slot-0 partition, if
+	  one is defined.
+
+config USBD_DFU_FLASH_SLOT1
+	bool "Flash backend for the slot-1 partition"
+	help
+	  This option enables download or upload for the slot-1 partition, if
+	  one is defined.
+
+endif # USBD_DFU_FLASH
+
+endif
diff --git a/subsys/usb/device_next/class/Kconfig.midi2 b/subsys/usb/device_next/class/Kconfig.midi2
new file mode 100644
index 00000000000..cd991c93e69
--- /dev/null
+++ b/subsys/usb/device_next/class/Kconfig.midi2
@@ -0,0 +1,17 @@
+# Copyright (c) 2024 Titouan Christophe
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config USBD_MIDI2_CLASS
+	bool "USB MIDI 2.0 class support [EXPERIMENTAL]"
+	select RING_BUFFER
+	help
+	  Enable the USB MIDI 2.0 device class support.
+
+if USBD_MIDI2_CLASS
+
+module = USBD_MIDI2
+module-str = usbd midi2
+source "subsys/logging/Kconfig.template.log_config"
+
+endif
diff --git a/subsys/usb/device_next/class/bt_hci.c b/subsys/usb/device_next/class/bt_hci.c
index a7aed6378c6..150ef9569c2 100644
--- a/subsys/usb/device_next/class/bt_hci.c
+++ b/subsys/usb/device_next/class/bt_hci.c
@@ -68,13 +68,13 @@ static K_FIFO_DEFINE(bt_hci_tx_queue);
 
 /*
  * Transfers through three endpoints proceed in a synchronous manner,
- * with maximum packet size of high speed bulk endpoint.
+ * with maximum packet size of max supported speed bulk endpoint.
  *
  * REVISE: global (bulk, interrupt, iso) specific pools would be more
  * RAM usage efficient.
  */
 UDC_BUF_POOL_DEFINE(bt_hci_ep_pool,
-		    3, 512,
+		    3, USBD_MAX_BULK_MPS,
 		    sizeof(struct udc_buf_info), NULL);
 /* HCI RX/TX threads */
 static K_KERNEL_STACK_DEFINE(rx_thread_stack, CONFIG_BT_HCI_TX_STACK_SIZE);
@@ -138,7 +138,8 @@ static uint8_t bt_hci_get_bulk_in(struct usbd_class_data *const c_data)
 	struct bt_hci_data *data = usbd_class_get_private(c_data);
 	struct usbd_bt_hci_desc *desc = data->desc;
 
-	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
 		return desc->if0_hs_in_ep.bEndpointAddress;
 	}
 
@@ -151,7 +152,8 @@ static uint8_t bt_hci_get_bulk_out(struct usbd_class_data *const c_data)
 	struct bt_hci_data *data = usbd_class_get_private(c_data);
 	struct usbd_bt_hci_desc *desc = data->desc;
 
-	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
 		return desc->if0_hs_out_ep.bEndpointAddress;
 	}
 
@@ -449,7 +451,7 @@ static void *bt_hci_get_desc(struct usbd_class_data *const c_data,
 {
 	struct bt_hci_data *data = usbd_class_get_private(c_data);
 
-	if (speed == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED && speed == USBD_SPEED_HS) {
 		return data->hs_desc;
 	}
 
diff --git a/subsys/usb/device_next/class/loopback.c b/subsys/usb/device_next/class/loopback.c
index b74a6b44b05..85896cd549e 100644
--- a/subsys/usb/device_next/class/loopback.c
+++ b/subsys/usb/device_next/class/loopback.c
@@ -1,15 +1,22 @@
 /*
- * Copyright (c) 2022 Nordic Semiconductor ASA
+ * Copyright (c) 2022, 2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <zephyr/usb/usbd.h>
+#include <zephyr/shell/shell.h>
 #include <zephyr/drivers/usb/udc.h>
 
 #include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(usb_loopback, CONFIG_USBD_LOOPBACK_LOG_LEVEL);
 
+/*
+ * This function does not define its own pool and requires a large enough UDC
+ * pool. To use it with the Linux kernel tool testusb, we need about 4096 bytes
+ * in the current configuration.
+ */
+
 /*
  * NOTE: this class is experimental and is in development.
  * Primary purpose currently is testing of the class initialization and
@@ -25,6 +32,11 @@ static uint8_t lb_buf[1024];
 #define LB_ISO_EP_MPS			256
 #define LB_ISO_EP_INTERVAL		1
 
+#define LB_FUNCTION_ENABLED		0
+#define LB_FUNCTION_BULK_MANUAL		1
+#define LB_FUNCTION_IN_ENGAGED		2
+#define LB_FUNCTION_OUT_ENGAGED		3
+
 /* Make supported vendor request visible for the device stack */
 static const struct usbd_cctx_vendor_req lb_vregs =
 	USBD_VENDOR_REQ(LB_VENDOR_REQ_OUT, LB_VENDOR_REQ_IN);
@@ -55,6 +67,134 @@ struct lb_data {
 	atomic_t state;
 };
 
+static uint8_t lb_get_bulk_out(struct usbd_class_data *const c_data)
+{
+	struct lb_data *data = usbd_class_get_private(c_data);
+	struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data);
+	struct loopback_desc *desc = data->desc;
+
+	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+		return desc->if0_hs_out_ep.bEndpointAddress;
+	}
+
+	return desc->if0_out_ep.bEndpointAddress;
+}
+
+static uint8_t lb_get_bulk_in(struct usbd_class_data *const c_data)
+{
+	struct lb_data *data = usbd_class_get_private(c_data);
+	struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data);
+	struct loopback_desc *desc = data->desc;
+
+	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+		return desc->if0_hs_in_ep.bEndpointAddress;
+	}
+
+	return desc->if0_in_ep.bEndpointAddress;
+}
+
+static int lb_submit_bulk_out(struct usbd_class_data *const c_data)
+{
+	struct lb_data *data = usbd_class_get_private(c_data);
+	struct net_buf *buf;
+	int err;
+
+	if (!atomic_test_bit(&data->state, LB_FUNCTION_ENABLED)) {
+		return -EPERM;
+	}
+
+	if (atomic_test_and_set_bit(&data->state, LB_FUNCTION_OUT_ENGAGED)) {
+		return -EBUSY;
+	}
+
+	buf = usbd_ep_buf_alloc(c_data, lb_get_bulk_out(c_data), sizeof(lb_buf));
+	if (buf == NULL) {
+		LOG_ERR("Failed to allocate buffer");
+		return -ENOMEM;
+	}
+
+	err = usbd_ep_enqueue(c_data, buf);
+	if (err) {
+		LOG_ERR("Failed to enqueue buffer");
+		net_buf_unref(buf);
+	}
+
+	return err;
+}
+
+static int lb_submit_bulk_in(struct usbd_class_data *const c_data)
+{
+	struct lb_data *data = usbd_class_get_private(c_data);
+	struct net_buf *buf;
+	int err;
+
+	if (!atomic_test_bit(&data->state, LB_FUNCTION_ENABLED)) {
+		return -EPERM;
+	}
+
+	if (atomic_test_and_set_bit(&data->state, LB_FUNCTION_IN_ENGAGED)) {
+		return -EBUSY;
+	}
+
+	buf = usbd_ep_buf_alloc(c_data, lb_get_bulk_in(c_data), sizeof(lb_buf));
+	if (buf == NULL) {
+		LOG_ERR("Failed to allocate buffer");
+		return -ENOMEM;
+	}
+
+	net_buf_add_mem(buf, lb_buf, MIN(sizeof(lb_buf), net_buf_tailroom(buf)));
+	err = usbd_ep_enqueue(c_data, buf);
+	if (err) {
+		LOG_ERR("Failed to enqueue buffer");
+		net_buf_unref(buf);
+	}
+
+	return err;
+}
+
+static int lb_request_handler(struct usbd_class_data *const c_data,
+			      struct net_buf *const buf, const int err)
+{
+	struct udc_buf_info *bi = (struct udc_buf_info *)net_buf_user_data(buf);
+	struct lb_data *data = usbd_class_get_private(c_data);
+	const size_t len = buf->len;
+	const uint8_t ep = bi->ep;
+	int ret = 0;
+
+	if (bi->ep == lb_get_bulk_out(c_data)) {
+		atomic_clear_bit(&data->state, LB_FUNCTION_OUT_ENGAGED);
+		if (err == 0) {
+			memcpy(lb_buf, buf->data, MIN(sizeof(lb_buf), buf->len));
+		}
+	}
+
+	if (bi->ep == lb_get_bulk_in(c_data)) {
+		atomic_clear_bit(&data->state, LB_FUNCTION_IN_ENGAGED);
+	}
+
+	net_buf_unref(buf);
+	if (err == -ECONNABORTED) {
+		LOG_INF("Transfer ep 0x%02x, len %u cancelled", ep, len);
+	} else if (err != 0) {
+		LOG_ERR("Transfer ep 0x%02x, len %u failed", ep, len);
+		ret = err;
+	} else {
+		LOG_DBG("Transfer ep 0x%02x, len %u finished", ep, len);
+	}
+
+	if (!atomic_test_bit(&data->state, LB_FUNCTION_BULK_MANUAL)) {
+		if (ep == lb_get_bulk_out(c_data)) {
+			lb_submit_bulk_out(c_data);
+		}
+
+		if (ep == lb_get_bulk_in(c_data)) {
+			lb_submit_bulk_in(c_data);
+		}
+	}
+
+	return ret;
+}
+
 static void lb_update(struct usbd_class_data *c_data,
 		      uint8_t iface, uint8_t alternate)
 {
@@ -109,28 +249,36 @@ static int lb_control_to_dev(struct usbd_class_data *c_data,
 	return 0;
 }
 
-static int lb_request_handler(struct usbd_class_data *c_data,
-			      struct net_buf *buf, int err)
+static void *lb_get_desc(struct usbd_class_data *const c_data,
+			 const enum usbd_speed speed)
 {
-	struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data);
-	struct udc_buf_info *bi = NULL;
+	struct lb_data *data = usbd_class_get_private(c_data);
 
-	bi = (struct udc_buf_info *)net_buf_user_data(buf);
-	LOG_DBG("%p -> ep 0x%02x, len %u, err %d", c_data, bi->ep, buf->len, err);
+	if (USBD_SUPPORTS_HIGH_SPEED && speed == USBD_SPEED_HS) {
+		return data->hs_desc;
+	}
 
-	return usbd_ep_buf_free(uds_ctx, buf);
+	return data->fs_desc;
 }
 
-static void *lb_get_desc(struct usbd_class_data *const c_data,
-			 const enum usbd_speed speed)
+static void lb_enable(struct usbd_class_data *const c_data)
 {
 	struct lb_data *data = usbd_class_get_private(c_data);
 
-	if (speed == USBD_SPEED_HS) {
-		return data->hs_desc;
+	LOG_INF("Enable %s", c_data->name);
+	if (!atomic_test_and_set_bit(&data->state, LB_FUNCTION_ENABLED) &&
+	    !atomic_test_bit(&data->state, LB_FUNCTION_BULK_MANUAL)) {
+		lb_submit_bulk_out(c_data);
+		lb_submit_bulk_in(c_data);
 	}
+}
 
-	return data->fs_desc;
+static void lb_disable(struct usbd_class_data *const c_data)
+{
+	struct lb_data *data = usbd_class_get_private(c_data);
+
+	atomic_clear_bit(&data->state, LB_FUNCTION_ENABLED);
+	LOG_INF("Disable %s", c_data->name);
 }
 
 static int lb_init(struct usbd_class_data *c_data)
@@ -146,6 +294,8 @@ struct usbd_class_api lb_api = {
 	.control_to_dev = lb_control_to_dev,
 	.request = lb_request_handler,
 	.get_desc = lb_get_desc,
+	.enable = lb_enable,
+	.disable = lb_disable,
 	.init = lb_init,
 };
 
@@ -361,3 +511,172 @@ const static struct usb_desc_header *lb_hs_desc_##x[] = {			\
 
 LISTIFY(CONFIG_USBD_LOOPBACK_INSTANCES_COUNT, DEFINE_LOOPBACK_DESCRIPTOR, ())
 LISTIFY(CONFIG_USBD_LOOPBACK_INSTANCES_COUNT, DEFINE_LOOPBACK_CLASS_DATA, ())
+
+#if CONFIG_USBD_SHELL
+
+/*
+ * Device and Host Troubleshooting Shell Commands
+ *
+ * When set to manual mode, the function does not automatically submit new
+ * transfers. The user can manually enqueue or not enqueue new transfers, so
+ * the NAK behavior can also be tested.
+ *
+ * Only bulk endpoints are supported at this time.
+ */
+
+static void set_manual(struct usbd_class_data *const c_data, const bool on)
+{
+	struct lb_data *data = usbd_class_get_private(c_data);
+
+	if (on) {
+		atomic_set_bit(&data->state, LB_FUNCTION_BULK_MANUAL);
+	} else {
+		atomic_clear_bit(&data->state, LB_FUNCTION_BULK_MANUAL);
+	}
+}
+
+static struct usbd_class_node *lb_get_node(const struct shell *const sh,
+					   const char *const name)
+{
+	STRUCT_SECTION_FOREACH_ALTERNATE(usbd_class_fs, usbd_class_node, c_nd) {
+		if (strcmp(c_nd->c_data->name, name) == 0) {
+			return c_nd;
+		}
+	}
+
+	shell_error(sh, "Function %s could not be found", name);
+
+	return NULL;
+}
+
+static int cmd_manual_on(const struct shell *sh, size_t argc, char **argv)
+{
+	struct usbd_class_node *c_nd;
+
+	c_nd = lb_get_node(sh, argv[1]);
+	if (c_nd == NULL) {
+		return ENODEV;
+	}
+
+	shell_print(sh, "%s bulk transfers can be submitted from the shell", argv[1]);
+	set_manual(c_nd->c_data, true);
+
+	return 0;
+}
+
+static int cmd_manual_off(const struct shell *sh, size_t argc, char **argv)
+{
+	struct usbd_class_node *c_nd;
+
+	c_nd = lb_get_node(sh, argv[1]);
+	if (c_nd == NULL) {
+		return ENODEV;
+	}
+
+	shell_print(sh, "%s bulk endpoints are automatically engaged", argv[1]);
+	set_manual(c_nd->c_data, false);
+
+	return 0;
+}
+
+static int cmd_enqueue_out(const struct shell *sh, size_t argc, char **argv)
+{
+	struct usbd_class_node *c_nd;
+	int err;
+
+	c_nd = lb_get_node(sh, argv[1]);
+	if (c_nd == NULL) {
+		return ENODEV;
+	}
+
+	err = lb_submit_bulk_out(c_nd->c_data);
+	if (err == -EPERM) {
+		shell_error(sh, "%s is not enabled", argv[1]);
+	} else if (err == -EBUSY) {
+		shell_error(sh, "%s bulk OUT endpoint is busy", argv[1]);
+	} else if (err == -ENOMEM) {
+		shell_error(sh, "%s failed to allocate transfer", argv[1]);
+	} else if (err) {
+		shell_error(sh, "%s failed to enqueue transfer", argv[1]);
+	} else {
+		shell_print(sh, "%s, new transfer enqueued", argv[1]);
+	}
+
+	return err;
+}
+
+static int cmd_enqueue_in(const struct shell *sh, size_t argc, char **argv)
+{
+	struct usbd_class_node *c_nd;
+	int err;
+
+	c_nd = lb_get_node(sh, argv[1]);
+	if (c_nd == NULL) {
+		return ENODEV;
+	}
+
+	err = lb_submit_bulk_in(c_nd->c_data);
+	if (err == -EPERM) {
+		shell_error(sh, "%s is not enabled", argv[1]);
+	} else if (err == -EBUSY) {
+		shell_error(sh, "%s bulk IN endpoint is busy", argv[1]);
+	} else if (err == -ENOMEM) {
+		shell_error(sh, "%s failed to allocate transfer", argv[1]);
+	} else if (err) {
+		shell_error(sh, "%s failed to enqueue transfer", argv[1]);
+	} else {
+		shell_print(sh, "%s, new transfer enqueued", argv[1]);
+	}
+
+	return err;
+}
+
+static void lb_node_name_lookup(size_t idx, struct shell_static_entry *entry)
+{
+	size_t match_idx = 0;
+
+	entry->syntax = NULL;
+	entry->handler = NULL;
+	entry->help = NULL;
+	entry->subcmd = NULL;
+
+	STRUCT_SECTION_FOREACH_ALTERNATE(usbd_class_fs, usbd_class_node, c_nd) {
+		if (c_nd->c_data->name != NULL && strlen(c_nd->c_data->name) != 0) {
+			if (match_idx == idx) {
+				entry->syntax = c_nd->c_data->name;
+				break;
+			}
+
+			++match_idx;
+		}
+	}
+}
+
+SHELL_DYNAMIC_CMD_CREATE(dsub_node_name, lb_node_name_lookup);
+
+SHELL_STATIC_SUBCMD_SET_CREATE(sub_cmd_manual,
+	SHELL_CMD_ARG(off, &dsub_node_name, "<function name>", cmd_manual_off, 2, 0),
+	SHELL_CMD_ARG(on, &dsub_node_name, "<function name>", cmd_manual_on, 2, 0),
+	SHELL_SUBCMD_SET_END
+);
+
+SHELL_STATIC_SUBCMD_SET_CREATE(sub_cmd_enqueue,
+	SHELL_CMD_ARG(out, &dsub_node_name, "<function name>", cmd_enqueue_out, 2, 0),
+	SHELL_CMD_ARG(in, &dsub_node_name, "<function name>", cmd_enqueue_in, 2, 0),
+	SHELL_SUBCMD_SET_END
+);
+
+SHELL_STATIC_SUBCMD_SET_CREATE(lb_bulk_cmds,
+	SHELL_CMD_ARG(manual, &sub_cmd_manual, "off  on", NULL, 2, 0),
+	SHELL_CMD_ARG(enqueue, &sub_cmd_enqueue, "out  in", NULL, 2, 0),
+	SHELL_SUBCMD_SET_END
+);
+
+SHELL_STATIC_SUBCMD_SET_CREATE(sub_lb_cmds,
+	SHELL_CMD_ARG(bulk, &lb_bulk_cmds, "bulk endpoint commands", NULL, 2, 0),
+	SHELL_SUBCMD_SET_END
+);
+
+SHELL_CMD_REGISTER(lb, &sub_lb_cmds, "USB device loopback function commands", NULL);
+
+#endif
diff --git a/subsys/usb/device_next/class/usbd_cdc_acm.c b/subsys/usb/device_next/class/usbd_cdc_acm.c
index 514883864c9..d3fef3b83b0 100644
--- a/subsys/usb/device_next/class/usbd_cdc_acm.c
+++ b/subsys/usb/device_next/class/usbd_cdc_acm.c
@@ -36,7 +36,7 @@ LOG_MODULE_REGISTER(usbd_cdc_acm, CONFIG_USBD_CDC_ACM_LOG_LEVEL);
 
 UDC_BUF_POOL_DEFINE(cdc_acm_ep_pool,
 		    DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) * 2,
-		    512, sizeof(struct udc_buf_info), NULL);
+		    USBD_MAX_BULK_MPS, sizeof(struct udc_buf_info), NULL);
 
 #define CDC_ACM_DEFAULT_LINECODING	{sys_cpu_to_le32(115200), 0, 0, 8}
 #define CDC_ACM_DEFAULT_INT_EP_MPS	16
@@ -80,13 +80,19 @@ struct usbd_cdc_acm_desc {
 	struct usb_desc_header nil_desc;
 };
 
-struct cdc_acm_uart_data {
+struct cdc_acm_uart_config {
 	/* Pointer to the associated USBD class node */
 	struct usbd_class_data *c_data;
+	/* Pointer to the interface description node or NULL */
+	struct usbd_desc_node *const if_desc_data;
 	/* Pointer to the class interface descriptors */
 	struct usbd_cdc_acm_desc *const desc;
 	const struct usb_desc_header **const fs_desc;
 	const struct usb_desc_header **const hs_desc;
+};
+
+struct cdc_acm_uart_data {
+	const struct device *dev;
 	/* Line Coding Structure */
 	struct cdc_acm_line_coding line_coding;
 	/* SetControlLineState bitmap */
@@ -99,6 +105,15 @@ struct cdc_acm_uart_data {
 	bool line_state_rts;
 	/* UART actual DTR state */
 	bool line_state_dtr;
+	/* When flow_ctrl is set, poll out is blocked when the buffer is full,
+	 * roughly emulating flow control.
+	 */
+	bool flow_ctrl;
+	/* Used to enqueue a ZLP transfer when the previous IN transfer length
+	 * was a multiple of the endpoint MPS and no more data is added to
+	 * the TX FIFO during the user callback execution.
+	 */
+	bool zlp_needed;
 	/* UART API IRQ callback */
 	uart_irq_callback_user_data_t cb;
 	/* UART API user callback data */
@@ -107,10 +122,6 @@ struct cdc_acm_uart_data {
 	struct k_work irq_cb_work;
 	struct cdc_acm_uart_fifo rx_fifo;
 	struct cdc_acm_uart_fifo tx_fifo;
-	/* When flow_ctrl is set, poll out is blocked when the buffer is full,
-	 * roughly emulating flow control.
-	 */
-	bool flow_ctrl;
 	/* USBD CDC ACM TX fifo work */
 	struct k_work_delayable tx_fifo_work;
 	/* USBD CDC ACM RX fifo work */
@@ -157,10 +168,11 @@ static uint8_t cdc_acm_get_int_in(struct usbd_class_data *const c_data)
 {
 	struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data);
 	const struct device *dev = usbd_class_get_private(c_data);
-	struct cdc_acm_uart_data *data = dev->data;
-	struct usbd_cdc_acm_desc *desc = data->desc;
+	const struct cdc_acm_uart_config *cfg = dev->config;
+	struct usbd_cdc_acm_desc *desc = cfg->desc;
 
-	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
 		return desc->if0_hs_int_ep.bEndpointAddress;
 	}
 
@@ -171,10 +183,11 @@ static uint8_t cdc_acm_get_bulk_in(struct usbd_class_data *const c_data)
 {
 	struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data);
 	const struct device *dev = usbd_class_get_private(c_data);
-	struct cdc_acm_uart_data *data = dev->data;
-	struct usbd_cdc_acm_desc *desc = data->desc;
+	const struct cdc_acm_uart_config *cfg = dev->config;
+	struct usbd_cdc_acm_desc *desc = cfg->desc;
 
-	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
 		return desc->if1_hs_in_ep.bEndpointAddress;
 	}
 
@@ -185,10 +198,11 @@ static uint8_t cdc_acm_get_bulk_out(struct usbd_class_data *const c_data)
 {
 	struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data);
 	const struct device *dev = usbd_class_get_private(c_data);
-	struct cdc_acm_uart_data *data = dev->data;
-	struct usbd_cdc_acm_desc *desc = data->desc;
+	const struct cdc_acm_uart_config *cfg = dev->config;
+	struct usbd_cdc_acm_desc *desc = cfg->desc;
 
-	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
 		return desc->if1_hs_out_ep.bEndpointAddress;
 	}
 
@@ -199,7 +213,8 @@ static size_t cdc_acm_get_bulk_mps(struct usbd_class_data *const c_data)
 {
 	struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data);
 
-	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
 		return 512U;
 	}
 
@@ -232,6 +247,10 @@ static int usbd_cdc_acm_request(struct usbd_class_data *const c_data,
 			atomic_clear_bit(&data->state, CDC_ACM_TX_FIFO_BUSY);
 		}
 
+		if (bi->ep == cdc_acm_get_int_in(c_data)) {
+			k_sem_reset(&data->notif_sem);
+		}
+
 		goto ep_request_error;
 	}
 
@@ -333,13 +352,13 @@ static void *usbd_cdc_acm_get_desc(struct usbd_class_data *const c_data,
 				   const enum usbd_speed speed)
 {
 	const struct device *dev = usbd_class_get_private(c_data);
-	struct cdc_acm_uart_data *data = dev->data;
+	const struct cdc_acm_uart_config *cfg = dev->config;
 
-	if (speed == USBD_SPEED_HS) {
-		return data->hs_desc;
+	if (USBD_SUPPORTS_HIGH_SPEED && speed == USBD_SPEED_HS) {
+		return cfg->hs_desc;
 	}
 
-	return data->fs_desc;
+	return cfg->fs_desc;
 }
 
 static void cdc_acm_update_uart_cfg(struct cdc_acm_uart_data *const data)
@@ -483,13 +502,22 @@ static int usbd_cdc_acm_ctd(struct usbd_class_data *const c_data,
 
 static int usbd_cdc_acm_init(struct usbd_class_data *const c_data)
 {
+	struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data);
 	const struct device *dev = usbd_class_get_private(c_data);
-	struct cdc_acm_uart_data *data = dev->data;
-	struct usbd_cdc_acm_desc *desc = data->desc;
+	const struct cdc_acm_uart_config *cfg = dev->config;
+	struct usbd_cdc_acm_desc *desc = cfg->desc;
 
 	desc->if0_union.bControlInterface = desc->if0.bInterfaceNumber;
 	desc->if0_union.bSubordinateInterface0 = desc->if1.bInterfaceNumber;
 
+	if (cfg->if_desc_data != NULL && desc->if0.iInterface == 0) {
+		if (usbd_add_descriptor(uds_ctx, cfg->if_desc_data)) {
+			LOG_ERR("Failed to add interface string descriptor");
+		} else {
+			desc->if0.iInterface = usbd_str_desc_get_idx(cfg->if_desc_data);
+		}
+	}
+
 	return 0;
 }
 
@@ -505,7 +533,8 @@ static inline int cdc_acm_send_notification(const struct device *dev,
 		.data = sys_cpu_to_le16(serial_state),
 	};
 	struct cdc_acm_uart_data *data = dev->data;
-	struct usbd_class_data *c_data = data->c_data;
+	const struct cdc_acm_uart_config *cfg = dev->config;
+	struct usbd_class_data *c_data = cfg->c_data;
 	struct net_buf *buf;
 	uint8_t ep;
 	int ret;
@@ -533,7 +562,9 @@ static inline int cdc_acm_send_notification(const struct device *dev,
 		return ret;
 	}
 
-	k_sem_take(&data->notif_sem, K_FOREVER);
+	if (k_sem_take(&data->notif_sem, K_FOREVER) == -EAGAIN) {
+		return -ECANCELED;
+	}
 
 	return ret;
 }
@@ -545,13 +576,15 @@ static void cdc_acm_tx_fifo_handler(struct k_work *work)
 {
 	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
 	struct cdc_acm_uart_data *data;
+	const struct cdc_acm_uart_config *cfg;
 	struct usbd_class_data *c_data;
 	struct net_buf *buf;
 	size_t len;
 	int ret;
 
 	data = CONTAINER_OF(dwork, struct cdc_acm_uart_data, tx_fifo_work);
-	c_data = data->c_data;
+	cfg = data->dev->config;
+	c_data = cfg->c_data;
 
 	if (!atomic_test_bit(&data->state, CDC_ACM_CLASS_ENABLED)) {
 		LOG_DBG("USB configuration is not enabled");
@@ -578,6 +611,8 @@ static void cdc_acm_tx_fifo_handler(struct k_work *work)
 	len = ring_buf_get(data->tx_fifo.rb, buf->data, buf->size);
 	net_buf_add(buf, len);
 
+	data->zlp_needed = len != 0 && len % cdc_acm_get_bulk_mps(c_data) == 0;
+
 	ret = usbd_ep_enqueue(c_data, buf);
 	if (ret) {
 		LOG_ERR("Failed to enqueue");
@@ -597,13 +632,15 @@ static void cdc_acm_tx_fifo_handler(struct k_work *work)
 static void cdc_acm_rx_fifo_handler(struct k_work *work)
 {
 	struct cdc_acm_uart_data *data;
+	const struct cdc_acm_uart_config *cfg;
 	struct usbd_class_data *c_data;
 	struct net_buf *buf;
 	uint8_t ep;
 	int ret;
 
 	data = CONTAINER_OF(work, struct cdc_acm_uart_data, rx_fifo_work);
-	c_data = data->c_data;
+	cfg = data->dev->config;
+	c_data = cfg->c_data;
 
 	if (!atomic_test_bit(&data->state, CDC_ACM_CLASS_ENABLED) ||
 	    atomic_test_bit(&data->state, CDC_ACM_CLASS_SUSPENDED)) {
@@ -823,10 +860,12 @@ static int cdc_acm_irq_update(const struct device *dev)
 static void cdc_acm_irq_cb_handler(struct k_work *work)
 {
 	struct cdc_acm_uart_data *data;
+	const struct cdc_acm_uart_config *cfg;
 	struct usbd_class_data *c_data;
 
 	data = CONTAINER_OF(work, struct cdc_acm_uart_data, irq_cb_work);
-	c_data = data->c_data;
+	cfg = data->dev->config;
+	c_data = cfg->c_data;
 
 	if (data->cb == NULL) {
 		LOG_ERR("IRQ callback is not set");
@@ -848,9 +887,12 @@ static void cdc_acm_irq_cb_handler(struct k_work *work)
 		cdc_acm_work_submit(&data->rx_fifo_work);
 	}
 
-	if (data->tx_fifo.altered) {
-		LOG_DBG("tx fifo altered, submit work");
-		if (!atomic_test_bit(&data->state, CDC_ACM_TX_FIFO_BUSY)) {
+	if (!atomic_test_bit(&data->state, CDC_ACM_TX_FIFO_BUSY)) {
+		if (data->tx_fifo.altered) {
+			LOG_DBG("tx fifo altered, submit work");
+			cdc_acm_work_schedule(&data->tx_fifo_work, K_NO_WAIT);
+		} else if (data->zlp_needed) {
+			LOG_DBG("zlp needed, submit work");
 			cdc_acm_work_schedule(&data->tx_fifo_work, K_NO_WAIT);
 		}
 	}
@@ -1253,23 +1295,36 @@ const static struct usb_desc_header *cdc_acm_hs_desc_##n[] = {			\
 			  &usbd_cdc_acm_api,					\
 			  (void *)DEVICE_DT_GET(DT_DRV_INST(n)), NULL);		\
 										\
+	IF_ENABLED(DT_INST_NODE_HAS_PROP(n, label), (				\
+	USBD_DESC_STRING_DEFINE(cdc_acm_if_desc_data_##n,			\
+				DT_INST_PROP(n, label),				\
+				USBD_DUT_STRING_INTERFACE);			\
+	))									\
+										\
 	RING_BUF_DECLARE(cdc_acm_rb_rx_##n, DT_INST_PROP(n, rx_fifo_size));	\
 	RING_BUF_DECLARE(cdc_acm_rb_tx_##n, DT_INST_PROP(n, tx_fifo_size));	\
 										\
+	static const struct cdc_acm_uart_config uart_config_##n = {		\
+		.c_data = &cdc_acm_##n,						\
+		IF_ENABLED(DT_INST_NODE_HAS_PROP(n, label), (			\
+		.if_desc_data = &cdc_acm_if_desc_data_##n,			\
+		))								\
+		.desc = &cdc_acm_desc_##n,					\
+		.fs_desc = cdc_acm_fs_desc_##n,					\
+		.hs_desc = cdc_acm_hs_desc_##n,					\
+	};									\
+										\
 	static struct cdc_acm_uart_data uart_data_##n = {			\
+		.dev = DEVICE_DT_GET(DT_DRV_INST(n)),				\
 		.line_coding = CDC_ACM_DEFAULT_LINECODING,			\
-		.c_data = &cdc_acm_##n,						\
 		.rx_fifo.rb = &cdc_acm_rb_rx_##n,				\
 		.tx_fifo.rb = &cdc_acm_rb_tx_##n,				\
 		.flow_ctrl = DT_INST_PROP(n, hw_flow_control),			\
 		.notif_sem = Z_SEM_INITIALIZER(uart_data_##n.notif_sem, 0, 1),	\
-		.desc = &cdc_acm_desc_##n,					\
-		.fs_desc = cdc_acm_fs_desc_##n,					\
-		.hs_desc = cdc_acm_hs_desc_##n,					\
 	};									\
 										\
 	DEVICE_DT_INST_DEFINE(n, usbd_cdc_acm_preinit, NULL,			\
-		&uart_data_##n, NULL,						\
+		&uart_data_##n, &uart_config_##n,				\
 		PRE_KERNEL_1, CONFIG_SERIAL_INIT_PRIORITY,			\
 		&cdc_acm_uart_api);
 
diff --git a/subsys/usb/device_next/class/usbd_cdc_ecm.c b/subsys/usb/device_next/class/usbd_cdc_ecm.c
index e43f38bed64..55aa2798a64 100644
--- a/subsys/usb/device_next/class/usbd_cdc_ecm.c
+++ b/subsys/usb/device_next/class/usbd_cdc_ecm.c
@@ -106,7 +106,8 @@ static uint8_t cdc_ecm_get_int_in(struct usbd_class_data *const c_data)
 	struct cdc_ecm_eth_data *data = dev->data;
 	struct usbd_cdc_ecm_desc *desc = data->desc;
 
-	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
 		return desc->if0_hs_int_ep.bEndpointAddress;
 	}
 
@@ -120,7 +121,8 @@ static uint8_t cdc_ecm_get_bulk_in(struct usbd_class_data *const c_data)
 	struct cdc_ecm_eth_data *data = dev->data;
 	struct usbd_cdc_ecm_desc *desc = data->desc;
 
-	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
 		return desc->if1_1_hs_in_ep.bEndpointAddress;
 	}
 
@@ -131,7 +133,8 @@ static uint16_t cdc_ecm_get_bulk_in_mps(struct usbd_class_data *const c_data)
 {
 	struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data);
 
-	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
 		return 512U;
 	}
 
@@ -145,7 +148,8 @@ static uint8_t cdc_ecm_get_bulk_out(struct usbd_class_data *const c_data)
 	struct cdc_ecm_eth_data *data = dev->data;
 	struct usbd_cdc_ecm_desc *desc = data->desc;
 
-	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
 		return desc->if1_1_hs_out_ep.bEndpointAddress;
 	}
 
@@ -475,7 +479,7 @@ static void *usbd_cdc_ecm_get_desc(struct usbd_class_data *const c_data,
 	const struct device *dev = usbd_class_get_private(c_data);
 	struct cdc_ecm_eth_data *const data = dev->data;
 
-	if (speed == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED && speed == USBD_SPEED_HS) {
 		return data->hs_desc;
 	}
 
diff --git a/subsys/usb/device_next/class/usbd_cdc_ncm.c b/subsys/usb/device_next/class/usbd_cdc_ncm.c
index a7ffb5f23f7..c92754f72f8 100644
--- a/subsys/usb/device_next/class/usbd_cdc_ncm.c
+++ b/subsys/usb/device_next/class/usbd_cdc_ncm.c
@@ -249,7 +249,8 @@ static uint8_t cdc_ncm_get_int_in(struct usbd_class_data *const c_data)
 	struct cdc_ncm_eth_data *data = dev->data;
 	struct usbd_cdc_ncm_desc *desc = data->desc;
 
-	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
 		return desc->if0_hs_int_ep.bEndpointAddress;
 	}
 
@@ -263,7 +264,8 @@ static uint8_t cdc_ncm_get_bulk_in(struct usbd_class_data *const c_data)
 	struct cdc_ncm_eth_data *data = dev->data;
 	struct usbd_cdc_ncm_desc *desc = data->desc;
 
-	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
 		return desc->if1_1_hs_in_ep.bEndpointAddress;
 	}
 
@@ -274,7 +276,8 @@ static uint16_t cdc_ncm_get_bulk_in_mps(struct usbd_class_data *const c_data)
 {
 	struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data);
 
-	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
 		return 512U;
 	}
 
@@ -288,7 +291,8 @@ static uint8_t cdc_ncm_get_bulk_out(struct usbd_class_data *const c_data)
 	struct cdc_ncm_eth_data *data = dev->data;
 	struct usbd_cdc_ncm_desc *desc = data->desc;
 
-	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
 		return desc->if1_1_hs_out_ep.bEndpointAddress;
 	}
 
@@ -1009,7 +1013,7 @@ static void *usbd_cdc_ncm_get_desc(struct usbd_class_data *const c_data,
 	const struct device *dev = usbd_class_get_private(c_data);
 	struct cdc_ncm_eth_data *const data = dev->data;
 
-	if (speed == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED && speed == USBD_SPEED_HS) {
 		return data->hs_desc;
 	}
 
diff --git a/subsys/usb/device_next/class/usbd_dfu.c b/subsys/usb/device_next/class/usbd_dfu.c
new file mode 100644
index 00000000000..5317910d305
--- /dev/null
+++ b/subsys/usb/device_next/class/usbd_dfu.c
@@ -0,0 +1,794 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "usbd_msg.h"
+
+#include <zephyr/init.h>
+#include <zephyr/usb/usbd.h>
+#include <zephyr/usb/class/usbd_dfu.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(usbd_dfu, CONFIG_USBD_DFU_LOG_LEVEL);
+
+/*
+ * It is very unlikely that anyone would need more than one instance of the DFU
+ * class. Therefore, we make an exception here and do not support multiple
+ * instances, which allows us to have a much simpler implementation.
+ *
+ * This implementation provides two class instances, one with a single
+ * interface for the run-time mode, and the other with a number of user-defined
+ * interfaces for the DFU mode. The DFU mode instance can have up to 256
+ * (0...255) image (memory) segments, limited by the
+ * CONFIG_USBD_DFU_NUMOF_IMAGES and maximum value of bAlternateSetting.
+ *
+ * The implementation implicitly sets the bitWillDetach flag and expects the
+ * user to disable the device with run-time mode and enable a device with DFU
+ * mode.
+ */
+
+#if defined(CONFIG_USBD_DFU_ENABLE_UPLOAD)
+#define ATTR_CAN_UPLOAD USB_DFU_ATTR_CAN_UPLOAD
+#else
+#define ATTR_CAN_UPLOAD 0
+#endif
+
+#if defined(CONFIG_USBD_DFU_MANIFESTATION_TOLERANT)
+#define ATTR_MANIFESTATION_TOLERANT USB_DFU_ATTR_MANIFESTATION_TOLERANT
+#else
+#define ATTR_MANIFESTATION_TOLERANT 0
+#endif
+
+/* DFU Functional Descriptor used for Run-Time und DFU mode */
+static const struct usb_dfu_descriptor dfu_desc = {
+	.bLength = sizeof(struct usb_dfu_descriptor),
+	.bDescriptorType = USB_DESC_DFU_FUNCTIONAL,
+	.bmAttributes = USB_DFU_ATTR_CAN_DNLOAD |
+			ATTR_CAN_UPLOAD | ATTR_MANIFESTATION_TOLERANT |
+			USB_DFU_ATTR_WILL_DETACH,
+	.wDetachTimeOut = 0,
+	.wTransferSize = sys_cpu_to_le16(CONFIG_USBD_DFU_TRANSFER_SIZE),
+	.bcdDFUVersion = sys_cpu_to_le16(USB_DFU_VERSION),
+};
+
+/* Common class data for both run-time and DFU instances. */
+struct usbd_dfu_data {
+	struct usb_desc_header **const runtime_mode_descs;
+	struct usb_desc_header **const dfu_mode_descs;
+	enum usb_dfu_state state;
+	enum usb_dfu_state next;
+	enum usb_dfu_status status;
+	struct k_work_delayable dwork;
+	struct usbd_context *ctx;
+	bool dfu_mode;
+	struct usbd_dfu_image *image;
+	uint8_t alternate;
+};
+
+/* Run-Time mode interface descriptor */
+static __noinit struct usb_if_descriptor runtime_if0_desc;
+
+/* Run-Time mode descriptors. No endpoints, identical for high and full speed. */
+static struct usb_desc_header *runtime_mode_descs[] = {
+	(struct usb_desc_header *) &runtime_if0_desc,
+	(struct usb_desc_header *) &dfu_desc,
+	NULL,
+};
+
+/*
+ * DFU mode descriptors with two reserved indices for functional descriptor and
+ * at least one for NULL. No endpoints, identical for high and full speed.
+ */
+static struct usb_desc_header *dfu_mode_descs[CONFIG_USBD_DFU_NUMOF_IMAGES + 2];
+
+static struct usbd_dfu_data dfu_data = {
+	.runtime_mode_descs = runtime_mode_descs,
+	.dfu_mode_descs = dfu_mode_descs,
+};
+
+static const char *const dfu_state_list[] = {
+	"APP_IDLE",
+	"APP_DETACH",
+	"DFU_IDLE",
+	"DNLOAD_SYNC",
+	"DNBUSY",
+	"DNLOAD_IDLE",
+	"MANIFEST_SYNC",
+	"MANIFEST",
+	"MANIFEST_WAIT_RST",
+	"UPLOAD_IDLE",
+	"ERROR",
+};
+
+static const char *const dfu_req_list[] = {
+	"DETACH",
+	"DNLOAD",
+	"UPLOAD",
+	"GETSTATUS",
+	"CLRSTATUS",
+	"GETSTATE",
+	"ABORT",
+};
+
+BUILD_ASSERT(ARRAY_SIZE(dfu_state_list) == DFU_STATE_MAX,
+	     "Number of entries in dfu_state_list is not equal to DFU_STATE_MAX");
+
+BUILD_ASSERT(ARRAY_SIZE(dfu_req_list) == USB_DFU_REQ_ABORT + 1,
+	     "Number of entries in dfu_req_list is not equal to USB_DFU_REQ_ABORT + 1");
+
+static const char *dfu_state_string(const enum usb_dfu_state state)
+{
+	if (state >= 0 && state < DFU_STATE_MAX) {
+		return dfu_state_list[state];
+	}
+
+	return "?";
+}
+
+static const char *dfu_req_string(const enum usb_dfu_state state)
+{
+	if (state >= 0 && state <= USB_DFU_REQ_ABORT) {
+		return dfu_req_list[state];
+	}
+
+	return "?";
+}
+
+static void runtime_detach_work(struct k_work *work)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(work);
+	struct usbd_dfu_data *data = CONTAINER_OF(dwork, struct usbd_dfu_data, dwork);
+
+	usbd_msg_pub_simple(data->ctx, USBD_MSG_DFU_APP_DETACH, 0);
+}
+
+static void init_if_desc(struct usb_if_descriptor *const desc,
+			 const uint8_t alternate, const uint8_t protocol)
+{
+	desc->bLength = sizeof(struct usb_if_descriptor);
+	desc->bDescriptorType = USB_DESC_INTERFACE;
+	desc->bInterfaceNumber = 0;
+	desc->bAlternateSetting = alternate;
+	desc->bNumEndpoints = 0;
+	desc->bInterfaceClass = USB_BCC_APPLICATION;
+	desc->bInterfaceSubClass = USB_DFU_SUBCLASS;
+	desc->bInterfaceProtocol = protocol;
+	desc->iInterface = 0;
+}
+
+static int usbd_dfu_preinit(void)
+{
+	struct usb_if_descriptor *if_desc;
+	int n = 0;
+
+	init_if_desc(&runtime_if0_desc, 0, USB_DFU_PROTOCOL_RUNTIME);
+
+	STRUCT_SECTION_FOREACH(usbd_dfu_image, image) {
+		if (n >= CONFIG_USBD_DFU_NUMOF_IMAGES) {
+			LOG_ERR("Cannot register USB DFU image %s", image->name);
+			return -ENOMEM;
+		}
+
+		if_desc = image->if_desc;
+		init_if_desc(if_desc, n, USB_DFU_PROTOCOL_DFU);
+		dfu_mode_descs[n] = (struct usb_desc_header *)if_desc;
+		n++;
+	}
+
+	dfu_mode_descs[n] = (struct usb_desc_header *)&dfu_desc;
+
+	k_work_init_delayable(&dfu_data.dwork, runtime_detach_work);
+
+	return 0;
+}
+
+/*
+ * Perhaps it makes sense to implement an on_registration class interface
+ * callback and not use SYS_INIT().
+ */
+SYS_INIT(usbd_dfu_preinit, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
+
+/*
+ * This function is used for two purposes, to inform the image backend about
+ * the next step and in some cases to get feedback if the next step is possible
+ * from the image perspective.
+ */
+static inline bool usbd_dfu_image_next(struct usbd_class_data *const c_data,
+				       const enum usb_dfu_state next)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+	struct usbd_dfu_image *const image = data->image;
+
+	if (image->next_cb != NULL) {
+		return image->next_cb(image->priv, data->state, next);
+	}
+
+	return true;
+}
+
+static ALWAYS_INLINE void dfu_error(struct usbd_class_data *const c_data,
+				    const enum usb_dfu_state next,
+				    const enum usb_dfu_status status)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+
+	data->next = next;
+	data->status = status;
+}
+
+/*
+ * Because some states (e.g. APP_IDLE, APP_DETACH) require a stall handshake to
+ * be sent, but the state does not change to DFU_ERROR, there are some "return
+ * -ENOTSUP" without state change to indicate a protocol error.
+ */
+
+static int app_idle_next(struct usbd_class_data *const c_data,
+			 const struct usb_setup_packet *const setup)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+
+	switch (setup->bRequest) {
+	case USB_DFU_REQ_DETACH:
+		data->next = APP_DETACH;
+		return 0;
+	case USB_DFU_REQ_GETSTATUS:
+		__fallthrough;
+	case USB_DFU_REQ_GETSTATE:
+		return 0;
+	default:
+		return -ENOTSUP;
+	}
+}
+
+static int app_detach_next(struct usbd_class_data *const c_data,
+			   const struct usb_setup_packet *const setup)
+{
+	switch (setup->bRequest) {
+	case USB_DFU_REQ_GETSTATUS:
+		__fallthrough;
+	case USB_DFU_REQ_GETSTATE:
+		return 0;
+	default:
+		return -ENOTSUP;
+	}
+}
+
+static int dfu_idle_next(struct usbd_class_data *const c_data,
+			 const struct usb_setup_packet *const setup)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+
+	switch (setup->bRequest) {
+	case USB_DFU_REQ_DNLOAD:
+		if (!(dfu_desc.bmAttributes & USB_DFU_ATTR_CAN_DNLOAD)) {
+			dfu_error(c_data, DFU_ERROR, ERR_STALLEDPKT);
+			return -ENOTSUP;
+		}
+
+		if (data->image == NULL || data->image->write_cb == NULL) {
+			dfu_error(c_data, DFU_ERROR, ERR_VENDOR);
+			return -ENOTSUP;
+		}
+
+		if (setup->wLength == 0) {
+			dfu_error(c_data, DFU_ERROR, ERR_STALLEDPKT);
+			return -ENOTSUP;
+		}
+
+		data->next = DFU_DNLOAD_SYNC;
+		return 0;
+	case USB_DFU_REQ_UPLOAD:
+		if (!(dfu_desc.bmAttributes & USB_DFU_ATTR_CAN_UPLOAD)) {
+			dfu_error(c_data, DFU_ERROR, ERR_STALLEDPKT);
+			return -ENOTSUP;
+		}
+
+		if (data->image == NULL || data->image->read_cb == NULL) {
+			dfu_error(c_data, DFU_ERROR, ERR_VENDOR);
+			return -ENOTSUP;
+		}
+
+		if (setup->wLength > sys_le16_to_cpu(dfu_desc.wTransferSize)) {
+			dfu_error(c_data, DFU_ERROR, ERR_STALLEDPKT);
+			return -ENOTSUP;
+		}
+
+		data->next = DFU_UPLOAD_IDLE;
+		return 0;
+	case USB_DFU_REQ_ABORT:
+		__fallthrough;
+	case USB_DFU_REQ_GETSTATUS:
+		__fallthrough;
+	case USB_DFU_REQ_GETSTATE:
+		return 0;
+	default:
+		dfu_error(c_data, DFU_ERROR, ERR_STALLEDPKT);
+		return -ENOTSUP;
+	}
+}
+
+static int dfu_dnload_sync_next(struct usbd_class_data *const c_data,
+				const struct usb_setup_packet *const setup)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+
+	switch (setup->bRequest) {
+	case USB_DFU_REQ_GETSTATUS:
+		/* Chack if image backend can change DFU_DNLOAD_SYNC -> DFU_DNLOAD_IDLE */
+		if (usbd_dfu_image_next(c_data, DFU_DNLOAD_IDLE)) {
+			data->next = DFU_DNLOAD_IDLE;
+		} else {
+			data->next = DFU_DNBUSY;
+		}
+
+		return 0;
+	case USB_DFU_REQ_GETSTATE:
+		return 0;
+	default:
+		dfu_error(c_data, DFU_ERROR, ERR_STALLEDPKT);
+		return -ENOTSUP;
+	}
+}
+
+static int dfu_dnbusy_next(struct usbd_class_data *const c_data,
+			   const struct usb_setup_packet *const setup)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+
+	/* Do not enforce bmPollTimeout (allow GET_STATUS immediately) */
+	data->state = DFU_DNLOAD_SYNC;
+
+	return dfu_dnload_sync_next(c_data, setup);
+}
+
+static int dfu_dnload_idle_next(struct usbd_class_data *const c_data,
+				const struct usb_setup_packet *const setup)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+
+	switch (setup->bRequest) {
+	case USB_DFU_REQ_DNLOAD:
+		if (setup->wLength == 0) {
+			data->next = DFU_MANIFEST_SYNC;
+		} else {
+			data->next = DFU_DNLOAD_SYNC;
+		}
+
+		return 0;
+	case USB_DFU_REQ_ABORT:
+		data->next = DFU_IDLE;
+		/* Notify image backend about DFU_DNLOAD_IDLE -> DFU_IDLE change */
+		usbd_dfu_image_next(c_data, data->next);
+	case USB_DFU_REQ_GETSTATUS:
+		__fallthrough;
+	case USB_DFU_REQ_GETSTATE:
+		return 0;
+	default:
+		dfu_error(c_data, DFU_ERROR, ERR_STALLEDPKT);
+		return -ENOTSUP;
+	}
+}
+
+static int dfu_manifest_sync_next(struct usbd_class_data *const c_data,
+				  const struct usb_setup_packet *const setup)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+
+	switch (setup->bRequest) {
+	case USB_DFU_REQ_GETSTATUS:
+		if (usbd_dfu_image_next(c_data, DFU_IDLE)) {
+			data->next = DFU_IDLE;
+			usbd_msg_pub_simple(data->ctx, USBD_MSG_DFU_DOWNLOAD_COMPLETED, 0);
+		} else {
+			data->next = DFU_MANIFEST;
+		}
+	case USB_DFU_REQ_GETSTATE:
+		return 0;
+	default:
+		dfu_error(c_data, DFU_ERROR, ERR_STALLEDPKT);
+		return -ENOTSUP;
+	}
+
+	return 0;
+}
+
+static int dfu_manifest_next(struct usbd_class_data *const c_data,
+			     const struct usb_setup_packet *const setup)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+
+	/* Ignore poll timeout, proceed directly to next state. */
+
+	if (dfu_desc.bmAttributes & USB_DFU_ATTR_MANIFESTATION_TOLERANT) {
+		data->state = DFU_MANIFEST_SYNC;
+		return dfu_manifest_sync_next(c_data, setup);
+	}
+
+	data->next = DFU_MANIFEST_WAIT_RST;
+	usbd_dfu_image_next(c_data, DFU_MANIFEST_WAIT_RST);
+
+	return 0;
+}
+
+static int dfu_manifest_wait_rst_next(struct usbd_class_data *const c_data,
+				      const struct usb_setup_packet *const setup)
+{
+	/* Ignore all requests, wait for system or bus reset */
+
+	return 0;
+}
+
+static int dfu_upload_idle_next(struct usbd_class_data *const c_data,
+				const struct usb_setup_packet *const setup)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+
+	switch (setup->bRequest) {
+	case USB_DFU_REQ_UPLOAD:
+		if (setup->wLength > sys_le16_to_cpu(dfu_desc.wTransferSize)) {
+			dfu_error(c_data, DFU_ERROR, ERR_STALLEDPKT);
+			return -ENOTSUP;
+		}
+
+		data->next = DFU_UPLOAD_IDLE;
+		return 0;
+	case USB_DFU_REQ_ABORT:
+		data->next = DFU_IDLE;
+		/* Notify image backend about DFU_UPLOAD_IDLE -> DFU_IDLE change */
+		usbd_dfu_image_next(c_data, data->next);
+	case USB_DFU_REQ_GETSTATUS:
+		__fallthrough;
+	case USB_DFU_REQ_GETSTATE:
+		return 0;
+	default:
+		dfu_error(c_data, DFU_ERROR, ERR_STALLEDPKT);
+		return -ENOTSUP;
+	}
+}
+
+static int dfu_error_next(struct usbd_class_data *const c_data,
+			  const struct usb_setup_packet *const setup)
+{
+	switch (setup->bRequest) {
+	case USB_DFU_REQ_GETSTATUS:
+		__fallthrough;
+	case USB_DFU_REQ_GETSTATE:
+		return 0;
+	case USB_DFU_REQ_CLRSTATUS:
+		dfu_error(c_data, DFU_IDLE, ERR_OK);
+		return 0;
+	default:
+		return -ENOTSUP;
+	}
+}
+
+static int (*next_entries[])(struct usbd_class_data *const c_data,
+			     const struct usb_setup_packet *const setup) = {
+	app_idle_next,
+	app_detach_next,
+	dfu_idle_next,
+	dfu_dnload_sync_next,
+	dfu_dnbusy_next,
+	dfu_dnload_idle_next,
+	dfu_manifest_sync_next,
+	dfu_manifest_next,
+	dfu_manifest_wait_rst_next,
+	dfu_upload_idle_next,
+	dfu_error_next,
+};
+
+BUILD_ASSERT(ARRAY_SIZE(next_entries) == DFU_STATE_MAX,
+	     "Number of entries in next_entries is not equal to DFU_STATE_MAX");
+
+/*
+ * Here we only set the next state based on the current state, image state and
+ * the new request. We do not copy/move any data and we do not update DFU state.
+ *
+ * The state change and additional actions are performed in four places, in the
+ * host/device requests in runtime mode and in the host/device request in DFU
+ * mode.
+ */
+static int dfu_set_next_state(struct usbd_class_data *const c_data,
+			      const struct usb_setup_packet *const setup)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+	int err;
+
+	if (setup->RequestType.type != USB_REQTYPE_TYPE_CLASS) {
+		return -ENOTSUP;
+	}
+
+	if (setup->bRequest >= ARRAY_SIZE(next_entries)) {
+		return -ENOTSUP;
+	}
+
+	data->next = data->state;
+	err = next_entries[data->state](c_data, setup);
+
+	LOG_DBG("bRequest %s, state %s, next %s, error %d",
+		dfu_req_string(setup->bRequest), dfu_state_string(data->state),
+		dfu_state_string(data->next), err);
+
+	return err;
+}
+
+/* Run-Time mode instance implementation, for instance "dfu_runtime" */
+
+static int handle_get_status(struct usbd_class_data *const c_data,
+			     const struct usb_setup_packet *const setup,
+			     struct net_buf *const buf)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+	size_t len = MIN(setup->wLength, net_buf_tailroom(buf));
+	const size_t getstatus_len = 6;
+
+	if (len != getstatus_len) {
+		errno = -ENOTSUP;
+		return 0;
+	}
+
+	/*
+	 * Add GET_STATUS response consisting of
+	 * bStatus, bwPollTimeout, bStatus, iString (no strings defined)
+	 */
+	net_buf_add_u8(buf, data->status);
+	net_buf_add_le16(buf, CONFIG_USBD_DFU_POLLTIMEOUT);
+	net_buf_add_u8(buf, 0);
+	net_buf_add_u8(buf, data->state);
+	net_buf_add_u8(buf, 0);
+
+	return 0;
+}
+
+static int handle_get_state(struct usbd_class_data *const c_data,
+			    const struct usb_setup_packet *const setup,
+			    struct net_buf *const buf)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+	size_t len = MIN(setup->wLength, net_buf_tailroom(buf));
+	const size_t getstate_len = 1;
+
+	if (len != getstate_len) {
+		errno = -ENOTSUP;
+		return 0;
+	}
+
+	net_buf_add_u8(buf, data->state);
+
+	return 0;
+}
+
+static int runtime_mode_control_to_host(struct usbd_class_data *const c_data,
+					const struct usb_setup_packet *const setup,
+					struct net_buf *const buf)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+
+	errno = dfu_set_next_state(c_data, setup);
+
+	if (errno == 0) {
+		switch (setup->bRequest) {
+		case USB_DFU_REQ_GETSTATUS:
+			errno = handle_get_status(c_data, setup, buf);
+			break;
+		case USB_DFU_REQ_GETSTATE:
+			errno = handle_get_state(c_data, setup, buf);
+			break;
+		default:
+			break;
+		}
+	}
+
+	data->state = data->next;
+
+	return 0;
+}
+
+static int runtime_mode_control_to_dev(struct usbd_class_data *const c_data,
+				       const struct usb_setup_packet *const setup,
+				       const struct net_buf *const buf)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+
+	errno = dfu_set_next_state(c_data, setup);
+
+	if (errno == 0) {
+		if (setup->bRequest == USB_DFU_REQ_DETACH) {
+			k_work_reschedule(&data->dwork, K_MSEC(100));
+		}
+	}
+
+	data->state = data->next;
+
+	return 0;
+}
+
+static void *runtime_mode_get_desc(struct usbd_class_data *const c_data,
+				   const enum usbd_speed speed)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+
+	return data->runtime_mode_descs;
+}
+
+static int runtime_mode_init(struct usbd_class_data *const c_data)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+
+	LOG_DBG("Init class instance %p", c_data);
+	data->dfu_mode = false;
+	data->alternate = 0;
+	data->state = APP_IDLE;
+	data->next = APP_IDLE;
+	data->image = NULL;
+	data->ctx = usbd_class_get_ctx(c_data);
+
+	return 0;
+}
+
+struct usbd_class_api runtime_mode_api = {
+	.control_to_host = runtime_mode_control_to_host,
+	.control_to_dev = runtime_mode_control_to_dev,
+	.get_desc = runtime_mode_get_desc,
+	.init = runtime_mode_init,
+};
+
+USBD_DEFINE_CLASS(dfu_runtime, &runtime_mode_api, &dfu_data, NULL);
+
+/* DFU mode instance implementation, for instance "dfu_dfu" */
+
+static int handle_upload(struct usbd_class_data *const c_data,
+			 const struct usb_setup_packet *const setup,
+			 struct net_buf *const buf)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+	uint16_t size = MIN(setup->wLength, net_buf_tailroom(buf));
+	struct usbd_dfu_image *const image = data->image;
+	int ret;
+
+	ret = image->read_cb(image->priv, setup->wValue, size, buf->data);
+	if (ret >= 0) {
+		net_buf_add(buf, ret);
+		if (ret < sys_le16_to_cpu(dfu_desc.wTransferSize)) {
+			data->state = DFU_IDLE;
+		}
+	} else {
+		errno = -ENOTSUP;
+		dfu_error(c_data, DFU_ERROR, ERR_UNKNOWN);
+	}
+
+	return 0;
+}
+
+static int handle_download(struct usbd_class_data *const c_data,
+			   const struct usb_setup_packet *const setup,
+			   const struct net_buf *const buf)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+	struct usbd_dfu_image *const image = data->image;
+	uint16_t size = MIN(setup->wLength, buf->len);
+	int ret;
+
+	ret = image->write_cb(image->priv, setup->wValue, size, buf->data);
+	if (ret < 0) {
+		errno = -ENOTSUP;
+		dfu_error(c_data, DFU_ERROR, ERR_UNKNOWN);
+	}
+
+	return 0;
+}
+
+static int dfu_mode_control_to_host(struct usbd_class_data *const c_data,
+				    const struct usb_setup_packet *const setup,
+				    struct net_buf *const buf)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+
+	errno = dfu_set_next_state(c_data, setup);
+
+	if (errno == 0) {
+		switch (setup->bRequest) {
+		case USB_DFU_REQ_GETSTATUS:
+			errno = handle_get_status(c_data, setup, buf);
+			break;
+		case USB_DFU_REQ_GETSTATE:
+			errno = handle_get_state(c_data, setup, buf);
+			break;
+		case USB_DFU_REQ_UPLOAD:
+			errno = handle_upload(c_data, setup, buf);
+			break;
+		default:
+			break;
+		}
+	}
+
+	data->state = data->next;
+
+	return 0;
+}
+
+static int dfu_mode_control_to_dev(struct usbd_class_data *const c_data,
+				   const struct usb_setup_packet *const setup,
+				   const struct net_buf *const buf)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+
+	errno = dfu_set_next_state(c_data, setup);
+
+	if (errno == 0) {
+		if (setup->bRequest == USB_DFU_REQ_DNLOAD) {
+			handle_download(c_data, setup, buf);
+		}
+	}
+
+	data->state = data->next;
+
+	return 0;
+}
+
+static void dfu_mode_update(struct usbd_class_data *const c_data,
+			    const uint8_t iface, const uint8_t alternate)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+
+	LOG_DBG("Instance %p, interface %u alternate %u changed",
+		c_data, iface, alternate);
+
+	data->alternate = alternate;
+	data->image = NULL;
+
+	STRUCT_SECTION_FOREACH(usbd_dfu_image, image) {
+		if (image->if_desc->bAlternateSetting == alternate) {
+			data->image = image;
+			break;
+		}
+	}
+}
+
+static void *dfu_mode_get_desc(struct usbd_class_data *const c_data,
+			       const enum usbd_speed speed)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+
+	return data->dfu_mode_descs;
+}
+
+static int dfu_mode_init(struct usbd_class_data *const c_data)
+{
+	struct usbd_dfu_data *data = usbd_class_get_private(c_data);
+	struct usbd_context *uds_ctx = usbd_class_get_ctx(c_data);
+
+	LOG_DBG("Init class instance %p", c_data);
+	data->dfu_mode = true;
+	data->alternate = 0;
+	data->image = NULL;
+	data->state = DFU_IDLE;
+	data->next = DFU_IDLE;
+	data->ctx = usbd_class_get_ctx(c_data);
+
+	STRUCT_SECTION_FOREACH(usbd_dfu_image, image) {
+		if (image->if_desc->bAlternateSetting == data->alternate) {
+			data->image = image;
+		}
+
+		if (usbd_add_descriptor(uds_ctx, image->sd_nd)) {
+			LOG_ERR("Failed to add string descriptor");
+		} else {
+			image->if_desc->iInterface = usbd_str_desc_get_idx(image->sd_nd);
+		}
+	}
+
+	return data->image == NULL ? -EINVAL : 0;
+}
+
+struct usbd_class_api dfu_api = {
+	.control_to_host = dfu_mode_control_to_host,
+	.control_to_dev = dfu_mode_control_to_dev,
+	.update = dfu_mode_update,
+	.get_desc = dfu_mode_get_desc,
+	.init = dfu_mode_init,
+};
+
+USBD_DEFINE_CLASS(dfu_dfu, &dfu_api, &dfu_data, NULL);
diff --git a/subsys/usb/device_next/class/usbd_dfu.ld b/subsys/usb/device_next/class/usbd_dfu.ld
new file mode 100644
index 00000000000..cff3074e98d
--- /dev/null
+++ b/subsys/usb/device_next/class/usbd_dfu.ld
@@ -0,0 +1,3 @@
+#include <zephyr/linker/iterable_sections.h>
+
+ITERABLE_SECTION_ROM(usbd_dfu_image, Z_LINK_ITERABLE_SUBALIGN)
diff --git a/subsys/usb/device_next/class/usbd_dfu_flash.c b/subsys/usb/device_next/class/usbd_dfu_flash.c
new file mode 100644
index 00000000000..fea438bf3b2
--- /dev/null
+++ b/subsys/usb/device_next/class/usbd_dfu_flash.c
@@ -0,0 +1,155 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "usbd_msg.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/usb/usbd.h>
+#include <zephyr/usb/class/usbd_dfu.h>
+#include <zephyr/drivers/flash.h>
+#include <zephyr/storage/flash_map.h>
+#include <zephyr/dfu/flash_img.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(dfu_flash, CONFIG_USBD_DFU_LOG_LEVEL);
+
+/*
+ * This file implements the flash backend for the USB DFU implementation. The
+ * flash backend can serve up to two image slots, which are typically defined
+ * for the in-tree boards in the Zephyr project.
+ */
+
+struct usbd_dfu_flash_data {
+	struct flash_img_context fi_ctx;
+	uint32_t last_block;
+	const uint8_t id;
+	union {
+		uint32_t uploaded;
+		uint32_t downloaded;
+	};
+};
+
+static int dfu_flash_read(void *const priv,
+			  const uint32_t block, const uint16_t size,
+			  uint8_t buf[static CONFIG_USBD_DFU_TRANSFER_SIZE])
+{
+	struct usbd_dfu_flash_data *const data = priv;
+	const struct flash_area *fa;
+	uint32_t to_upload;
+	int len;
+	int ret;
+
+	if (size == 0) {
+		/* There is nothing to upload */
+		return 0;
+	}
+
+	if (block == 0) {
+		data->last_block = 0;
+		data->uploaded = 0;
+	} else {
+		if (data->last_block + 1U != block) {
+			return -EINVAL;
+		}
+
+	}
+
+	ret = flash_area_open(data->id, &fa);
+	if (ret) {
+		return ret;
+	}
+
+	if (block == 0) {
+		LOG_DBG("Flash area size %u", fa->fa_size);
+	}
+
+	to_upload = fa->fa_size - data->uploaded;
+	if (to_upload < size) {
+		len = to_upload;
+	} else {
+		len = size;
+	}
+
+	ret = flash_area_read(fa, data->uploaded, buf, len);
+	flash_area_close(fa);
+	if (ret) {
+		return ret;
+	}
+
+	data->last_block = block;
+	data->uploaded += size;
+	LOG_DBG("uploaded %u block %u len %u", data->uploaded, block, len);
+
+	return len;
+}
+
+static int dfu_flash_write(void *const priv,
+			   const uint32_t block, const uint16_t size,
+			   const uint8_t buf[static CONFIG_USBD_DFU_TRANSFER_SIZE])
+{
+	struct usbd_dfu_flash_data *const data = priv;
+	const bool flush = size == 0 ? true : false;
+	int ret;
+
+	if (block == 0) {
+		if (flash_img_init(&data->fi_ctx)) {
+			return -EINVAL;
+		}
+
+		data->last_block = 0;
+		data->downloaded = 0;
+
+		if (size == 0) {
+			/* There is nothing to download */
+			return 0;
+		}
+	} else {
+		if (data->last_block + 1U != block) {
+			return -EINVAL;
+		}
+
+	}
+
+	ret = flash_img_buffered_write(&data->fi_ctx, buf, size, flush);
+	if (ret) {
+		return ret;
+	}
+
+	data->last_block = block;
+	data->downloaded += size;
+	LOG_DBG("downloaded %u (%u) block %u size %u", data->downloaded,
+		flash_img_bytes_written(&data->fi_ctx), block, size);
+
+	return 0;
+}
+
+static bool dfu_flash_next(void *const priv,
+			   const enum usb_dfu_state state, const enum usb_dfu_state next)
+{
+	if (state == DFU_MANIFEST_SYNC && next == DFU_IDLE) {
+		LOG_DBG("Download finished");
+	}
+
+	return true;
+}
+
+#if FIXED_PARTITION_EXISTS(slot0_partition) && defined(CONFIG_USBD_DFU_FLASH_SLOT0)
+static struct usbd_dfu_flash_data slot0_data = {
+	.id = FIXED_PARTITION_ID(slot0_partition),
+};
+
+USBD_DFU_DEFINE_IMG(slot0_image, "slot0_image", &slot0_data,
+		    dfu_flash_read, dfu_flash_write, dfu_flash_next);
+#endif
+
+#if FIXED_PARTITION_EXISTS(slot1_partition) && defined(CONFIG_USBD_DFU_FLASH_SLOT1)
+static struct usbd_dfu_flash_data slot1_data = {
+	.id = FIXED_PARTITION_ID(slot1_partition),
+};
+
+USBD_DFU_DEFINE_IMG(slot1_image, "slot1_image", &slot1_data,
+		    dfu_flash_read, dfu_flash_write, dfu_flash_next);
+#endif
diff --git a/subsys/usb/device_next/class/usbd_hid.c b/subsys/usb/device_next/class/usbd_hid.c
index 8432b4cb806..fd10eba3c85 100644
--- a/subsys/usb/device_next/class/usbd_hid.c
+++ b/subsys/usb/device_next/class/usbd_hid.c
@@ -122,7 +122,7 @@ static int usbd_hid_request(struct usbd_class_data *const c_data,
 
 	if (bi->ep == hid_get_in_ep(c_data)) {
 		if (ops->input_report_done != NULL) {
-			ops->input_report_done(dev);
+			ops->input_report_done(dev, buf->__buf);
 		} else {
 			k_sem_give(&ddata->in_sem);
 		}
@@ -479,7 +479,7 @@ static void *usbd_hid_get_desc(struct usbd_class_data *const c_data,
 	const struct device *dev = usbd_class_get_private(c_data);
 	const struct hid_device_config *dcfg = dev->config;
 
-	if (speed == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED && speed == USBD_SPEED_HS) {
 		return dcfg->hs_desc;
 	}
 
diff --git a/subsys/usb/device_next/class/usbd_hid_api.c b/subsys/usb/device_next/class/usbd_hid_api.c
index 17b0efc1fbb..f2efa4e3cb1 100644
--- a/subsys/usb/device_next/class/usbd_hid_api.c
+++ b/subsys/usb/device_next/class/usbd_hid_api.c
@@ -129,8 +129,11 @@ void wrapper_set_protocol(const struct device *dev, const uint8_t proto)
 	}
 }
 
-void wrapper_input_report_done(const struct device *dev)
+void wrapper_input_report_done(const struct device *dev,
+			       const uint8_t *const report)
 {
+	ARG_UNUSED(report);
+
 	const struct hid_ops *legacy_ops = get_legacy_ops(dev);
 
 	if (legacy_ops != NULL && legacy_ops->int_in_ready != NULL) {
diff --git a/subsys/usb/device_next/class/usbd_midi2.c b/subsys/usb/device_next/class/usbd_midi2.c
new file mode 100644
index 00000000000..1afab63b4d9
--- /dev/null
+++ b/subsys/usb/device_next/class/usbd_midi2.c
@@ -0,0 +1,793 @@
+/*
+ * Copyright (c) 2024 Titouan Christophe
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define DT_DRV_COMPAT zephyr_midi2_device
+
+#include <zephyr/drivers/usb/udc.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/ring_buffer.h>
+#include <zephyr/usb/class/usbd_midi2.h>
+#include <zephyr/usb/usbd.h>
+
+#include "usbd_uac2_macros.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(usbd_midi2, CONFIG_USBD_MIDI2_LOG_LEVEL);
+
+#define MIDI1_ALTERNATE 0x00
+#define MIDI2_ALTERNATE 0x01
+
+UDC_BUF_POOL_DEFINE(usbd_midi_buf_pool, DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) * 2, 512U,
+		    sizeof(struct udc_buf_info), NULL);
+
+#define MIDI_QUEUE_SIZE 64
+
+/* midi20 A.1 MS Class-Specific Interface Descriptor Types */
+#define CS_GR_TRM_BLOCK	0x26
+/* midi20 A.1 MS Class-Specific Interface Descriptor Subtypes */
+#define MS_HEADER	0x01
+
+/* midi20 A.2 MS Class-Specific Endpoint Descriptor Subtypes */
+#define MS_GENERAL	0x01
+#define MS_GENERAL_2_0	0x02
+
+/* midi20 A.3 MS Class-Specific Group Terminal Block Descriptor Subtypes */
+#define GR_TRM_BLOCK_HEADER	0x01
+#define GR_TRM_BLOCK		0x02
+
+/* midi20 A.6 Group Terminal Block Type */
+#define GR_TRM_BIDIRECTIONAL	0x00
+#define GR_TRM_INPUT_ONLY	0x01
+#define GR_TRM_OUTPUT_ONLY	0x02
+
+/* midi20 A.7 Group Terminal Default MIDI Protocol */
+#define USE_MIDI_CI			0x00
+#define MIDI_1_0_UP_TO_64_BITS		0x01
+#define MIDI_1_0_UP_TO_64_BITS_JRTS	0x02
+#define MIDI_1_0_UP_TO_128_BITS		0x03
+#define MIDI_1_0_UP_TO_128_BITS_JRTS	0x04
+#define MIDI_2_0			0x11
+#define MIDI_2_0_JRTS			0x12
+
+/* midi20: B.2.2 Class-specific AC Interface Descriptor */
+struct usb_midi_cs_ac_header_descriptor {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bDescriptorSubtype;
+	uint16_t bcdADC;
+	uint16_t wTotalLength;
+	uint8_t bInCollection;
+	uint8_t baInterfaceNr1;
+} __packed;
+
+/* midi20 5.2.2.1 Class-Specific MS Interface Header Descriptor */
+struct usb_midi_header_descriptor {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bDescriptorSubtype;
+	uint16_t bcdMSC;
+	uint16_t wTotalLength;
+} __packed;
+
+/* midi20 5.3.2 Class-Specific MIDI Streaming Data Endpoint Descriptor */
+struct usb_midi_cs_endpoint_descriptor {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bDescriptorSubtype;
+	uint8_t bNumGrpTrmBlock;
+	uint8_t baAssoGrpTrmBlkID[16];
+} __packed;
+
+/* midi20 5.4.1 Class Specific Group Terminal Block Header Descriptor */
+struct usb_midi_grptrm_header_descriptor {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bDescriptorSubtype;
+	uint16_t wTotalLength;
+} __packed;
+
+/* midi20 5.4.2.1 Group Terminal Block Descriptor */
+struct usb_midi_grptrm_block_descriptor {
+	uint8_t bLength;
+	uint8_t bDescriptorType;
+	uint8_t bDescriptorSubtype;
+	uint8_t bGrpTrmBlkID;
+	uint8_t bGrpTrmBlkType;
+	uint8_t nGroupTrm;
+	uint8_t nNumGroupTrm;
+	uint8_t iBlockItem;
+	uint8_t bMIDIProtocol;
+	uint16_t wMaxInputBandwidth;
+	uint16_t wMaxOutputBandwidth;
+} __packed;
+
+struct usbd_midi_descriptors {
+	struct usb_association_descriptor iad;
+
+	/* Standard AudioControl (AC) Interface Descriptor */
+	struct usb_if_descriptor if0_std;
+	struct usb_midi_cs_ac_header_descriptor if0_cs;
+
+	/* Empty MidiStreaming 1.0 on altsetting 0 */
+	struct usb_if_descriptor if1_0_std;
+	struct usb_midi_header_descriptor if1_0_ms_header;
+	struct usb_ep_descriptor if1_0_out_ep_fs;
+	struct usb_ep_descriptor if1_0_out_ep_hs;
+	struct usb_midi_cs_endpoint_descriptor if1_0_cs_out_ep;
+	struct usb_ep_descriptor if1_0_in_ep_fs;
+	struct usb_ep_descriptor if1_0_in_ep_hs;
+	struct usb_midi_cs_endpoint_descriptor if1_0_cs_in_ep;
+
+	/* MidiStreaming 2.0 on altsetting 1 */
+	struct usb_if_descriptor if1_1_std;
+	struct usb_midi_header_descriptor if1_1_ms_header;
+	struct usb_ep_descriptor if1_1_out_ep_fs;
+	struct usb_ep_descriptor if1_1_out_ep_hs;
+	struct usb_midi_cs_endpoint_descriptor if1_1_cs_out_ep;
+	struct usb_ep_descriptor if1_1_in_ep_fs;
+	struct usb_ep_descriptor if1_1_in_ep_hs;
+	struct usb_midi_cs_endpoint_descriptor if1_1_cs_in_ep;
+
+	/* MidiStreaming 2.0 Class-Specific Group Terminal Block Descriptors
+	 * Retrievable by a Separate Get Request
+	 */
+	struct usb_midi_grptrm_header_descriptor grptrm_header;
+	struct usb_midi_grptrm_block_descriptor grptrm_blocks[16];
+};
+
+/* Device driver configuration */
+struct usbd_midi_config {
+	struct usbd_midi_descriptors *desc;
+	struct usb_desc_header const **fs_descs;
+	struct usb_desc_header const **hs_descs;
+};
+
+/* Device driver data */
+struct usbd_midi_data {
+	struct usbd_class_data *class_data;
+	struct k_work rx_work;
+	struct k_work tx_work;
+	uint8_t tx_queue_buf[MIDI_QUEUE_SIZE];
+	struct ring_buf tx_queue;
+	uint8_t altsetting;
+	struct usbd_midi_ops ops;
+};
+
+static void usbd_midi2_recv(const struct device *dev, struct net_buf *const buf)
+{
+	struct usbd_midi_data *data = dev->data;
+	struct midi_ump ump;
+
+	LOG_HEXDUMP_DBG(buf->data, buf->len, "MIDI2 - Rx DATA");
+	while (buf->len >= 4) {
+		ump.data[0] = net_buf_pull_le32(buf);
+		for (size_t i = 1; i < UMP_NUM_WORDS(ump); i++) {
+			if (buf->len < 4) {
+				LOG_ERR("Incomplete UMP");
+				return;
+			}
+			ump.data[i] = net_buf_pull_le32(buf);
+		}
+
+		if (data->ops.rx_packet_cb) {
+			data->ops.rx_packet_cb(dev, ump);
+		}
+	}
+
+	if (buf->len) {
+		LOG_HEXDUMP_WRN(buf->data, buf->len, "Trailing data in Rx buffer");
+	}
+}
+
+static int usbd_midi_class_request(struct usbd_class_data *const class_data,
+				   struct net_buf *const buf, const int err)
+{
+	struct usbd_context *uds_ctx = usbd_class_get_ctx(class_data);
+	const struct device *dev = usbd_class_get_private(class_data);
+	struct usbd_midi_data *data = dev->data;
+	struct udc_buf_info *info = udc_get_buf_info(buf);
+
+	LOG_DBG("MIDI2 request for %s ep=%02X len=%d err=%d",
+		dev->name, info->ep, buf->len, err);
+
+	if (err && err != -ECONNABORTED) {
+		LOG_ERR("Transfer error %d", err);
+	}
+	if (USB_EP_DIR_IS_OUT(info->ep)) {
+		usbd_midi2_recv(dev, buf);
+		k_work_submit(&data->rx_work);
+	} else {
+		LOG_HEXDUMP_DBG(buf->data, buf->len, "Tx DATA complete");
+		if (ring_buf_size_get(&data->tx_queue)) {
+			k_work_submit(&data->tx_work);
+		}
+	}
+
+	return usbd_ep_buf_free(uds_ctx, buf);
+}
+
+static void usbd_midi_class_update(struct usbd_class_data *const class_data,
+				   const uint8_t iface, const uint8_t alternate)
+{
+	const struct device *dev = usbd_class_get_private(class_data);
+	bool ready = false;
+	struct usbd_midi_data *data = dev->data;
+
+	LOG_DBG("update for %s: if=%u, alt=%u", dev->name, iface, alternate);
+
+	switch (alternate) {
+	case MIDI1_ALTERNATE:
+		data->altsetting = MIDI1_ALTERNATE;
+		LOG_WRN("%s set USB-MIDI1.0 altsetting (not implemented !)", dev->name);
+		break;
+	case MIDI2_ALTERNATE:
+		data->altsetting = MIDI2_ALTERNATE;
+		ready = true;
+		LOG_INF("%s set USB-MIDI2.0 altsetting", dev->name);
+		break;
+	}
+
+	if (data->ops.ready_cb) {
+		data->ops.ready_cb(dev, ready);
+	}
+}
+
+static void usbd_midi_class_enable(struct usbd_class_data *const class_data)
+{
+	const struct device *dev = usbd_class_get_private(class_data);
+	struct usbd_midi_data *data = dev->data;
+
+	if (data->altsetting == MIDI2_ALTERNATE && data->ops.ready_cb) {
+		data->ops.ready_cb(dev, true);
+	}
+
+	LOG_DBG("Enable %s", dev->name);
+	k_work_submit(&data->rx_work);
+}
+
+static void usbd_midi_class_disable(struct usbd_class_data *const class_data)
+{
+	const struct device *dev = usbd_class_get_private(class_data);
+	struct usbd_midi_data *data = dev->data;
+
+	if (data->ops.ready_cb) {
+		data->ops.ready_cb(dev, false);
+	}
+
+	LOG_DBG("Disable %s", dev->name);
+	k_work_cancel(&data->rx_work);
+}
+
+static void usbd_midi_class_suspended(struct usbd_class_data *const class_data)
+{
+	const struct device *dev = usbd_class_get_private(class_data);
+	struct usbd_midi_data *data = dev->data;
+
+	if (data->ops.ready_cb) {
+		data->ops.ready_cb(dev, false);
+	}
+
+	LOG_DBG("Suspend %s", dev->name);
+	k_work_cancel(&data->rx_work);
+}
+
+static void usbd_midi_class_resumed(struct usbd_class_data *const class_data)
+{
+	const struct device *dev = usbd_class_get_private(class_data);
+	struct usbd_midi_data *data = dev->data;
+
+	if (data->altsetting == MIDI2_ALTERNATE && data->ops.ready_cb) {
+		data->ops.ready_cb(dev, true);
+	}
+
+	LOG_DBG("Resume %s", dev->name);
+	k_work_submit(&data->rx_work);
+}
+
+static int usbd_midi_class_cth(struct usbd_class_data *const class_data,
+			       const struct usb_setup_packet *const setup,
+			       struct net_buf *const buf)
+{
+	const struct device *dev = usbd_class_get_private(class_data);
+	const struct usbd_midi_config *config = dev->config;
+	struct usbd_midi_data *data = dev->data;
+
+	size_t head_len = config->desc->grptrm_header.bLength;
+	size_t total_len = sys_le16_to_cpu(config->desc->grptrm_header.wTotalLength);
+
+	LOG_DBG("Control to host for %s", dev->name);
+	LOG_DBG("  bmRequestType=%02X bRequest=%02X wValue=%04X wIndex=%04X wLength=%04X",
+		setup->bmRequestType, setup->bRequest, setup->wValue, setup->wIndex,
+		setup->wLength);
+
+	/* Only support Group Terminal blocks retrieved with
+	 * midi20 6. Class Specific Command: Group Terminal Blocks Descriptors Request
+	 */
+	if (data->altsetting != MIDI2_ALTERNATE ||
+	    setup->bRequest != USB_SREQ_GET_DESCRIPTOR ||
+	    setup->wValue != ((CS_GR_TRM_BLOCK << 8) | MIDI2_ALTERNATE)) {
+		errno = -ENOTSUP;
+		return 0;
+	}
+
+	/* Group terminal block header */
+	net_buf_add_mem(buf, (void *) &config->desc->grptrm_header,
+			MIN(head_len, setup->wLength));
+
+	/* Group terminal blocks */
+	if (setup->wLength > head_len && total_len > head_len) {
+		net_buf_add_mem(buf, (void *) &config->desc->grptrm_blocks,
+				MIN(total_len, setup->wLength) - head_len);
+	}
+	LOG_HEXDUMP_DBG(buf->data, buf->len, "Control to host");
+
+	return 0;
+}
+
+static int usbd_midi_class_init(struct usbd_class_data *const class_data)
+{
+	const struct device *dev = usbd_class_get_private(class_data);
+
+	LOG_DBG("Init %s device class", dev->name);
+
+	return 0;
+}
+
+static void *usbd_midi_class_get_desc(struct usbd_class_data *const class_data,
+				      const enum usbd_speed speed)
+{
+	const struct device *dev = usbd_class_get_private(class_data);
+	const struct usbd_midi_config *config = dev->config;
+
+	LOG_DBG("Get descriptors for %s", dev->name);
+
+	if (USBD_SUPPORTS_HIGH_SPEED && speed == USBD_SPEED_HS) {
+		return config->hs_descs;
+	}
+
+	return config->fs_descs;
+}
+
+
+static struct usbd_class_api usbd_midi_class_api = {
+	.request = usbd_midi_class_request,
+	.update = usbd_midi_class_update,
+	.enable = usbd_midi_class_enable,
+	.disable = usbd_midi_class_disable,
+	.suspended = usbd_midi_class_suspended,
+	.resumed = usbd_midi_class_resumed,
+	.control_to_host = usbd_midi_class_cth,
+	.init = usbd_midi_class_init,
+	.get_desc = usbd_midi_class_get_desc,
+};
+
+static struct net_buf *usbd_midi_buf_alloc(uint8_t ep)
+{
+	struct udc_buf_info *info;
+	struct net_buf *buf;
+
+	buf = net_buf_alloc(&usbd_midi_buf_pool, K_NO_WAIT);
+	if (!buf) {
+		return NULL;
+	}
+
+	info = udc_get_buf_info(buf);
+	info->ep = ep;
+
+	return buf;
+}
+
+static uint8_t usbd_midi_get_bulk_in(struct usbd_class_data *const class_data)
+{
+	struct usbd_context *uds_ctx = usbd_class_get_ctx(class_data);
+	const struct device *dev = usbd_class_get_private(class_data);
+	const struct usbd_midi_config *cfg = dev->config;
+
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+		return cfg->desc->if1_1_in_ep_hs.bEndpointAddress;
+	}
+
+	return cfg->desc->if1_1_in_ep_fs.bEndpointAddress;
+}
+
+static uint8_t usbd_midi_get_bulk_out(struct usbd_class_data *const class_data)
+{
+	struct usbd_context *uds_ctx = usbd_class_get_ctx(class_data);
+	const struct device *dev = usbd_class_get_private(class_data);
+	const struct usbd_midi_config *cfg = dev->config;
+
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+		return cfg->desc->if1_1_out_ep_hs.bEndpointAddress;
+	}
+
+	return cfg->desc->if1_1_out_ep_fs.bEndpointAddress;
+}
+
+static void usbd_midi_rx_work(struct k_work *work)
+{
+	struct usbd_midi_data *data = CONTAINER_OF(work, struct usbd_midi_data, rx_work);
+	struct net_buf *buf;
+	int ret;
+
+	buf = usbd_midi_buf_alloc(usbd_midi_get_bulk_out(data->class_data));
+	if (buf == NULL) {
+		LOG_WRN("Unable to allocate Rx net_buf");
+		return;
+	}
+
+	LOG_DBG("Enqueue Rx...");
+	ret = usbd_ep_enqueue(data->class_data, buf);
+	if (ret) {
+		LOG_ERR("Failed to enqueue Rx net_buf -> %d", ret);
+		net_buf_unref(buf);
+	}
+}
+
+static void usbd_midi_tx_work(struct k_work *work)
+{
+	struct usbd_midi_data *data = CONTAINER_OF(work, struct usbd_midi_data, tx_work);
+	struct net_buf *buf;
+	int ret;
+
+	buf = usbd_midi_buf_alloc(usbd_midi_get_bulk_in(data->class_data));
+	if (buf == NULL) {
+		LOG_ERR("Unable to allocate Tx net_buf");
+		return;
+	}
+
+	net_buf_add(buf, ring_buf_get(&data->tx_queue, buf->data, buf->size));
+	LOG_HEXDUMP_DBG(buf->data, buf->len, "MIDI2 - Tx DATA");
+
+	ret = usbd_ep_enqueue(data->class_data, buf);
+	if (ret) {
+		LOG_ERR("Failed to enqueue Tx net_buf -> %d", ret);
+		net_buf_unref(buf);
+	}
+}
+
+static int usbd_midi_preinit(const struct device *dev)
+{
+	struct usbd_midi_data *data = dev->data;
+
+	LOG_DBG("Init device %s", dev->name);
+	ring_buf_init(&data->tx_queue, MIDI_QUEUE_SIZE, data->tx_queue_buf);
+	k_work_init(&data->rx_work, usbd_midi_rx_work);
+	k_work_init(&data->tx_work, usbd_midi_tx_work);
+
+	return 0;
+}
+
+int usbd_midi_send(const struct device *dev, const struct midi_ump ump)
+{
+	struct usbd_midi_data *data = dev->data;
+	size_t words = UMP_NUM_WORDS(ump);
+	size_t buflen = 4 * words;
+	uint32_t word;
+
+	LOG_DBG("Send MT=%X group=%X", UMP_MT(ump), UMP_GROUP(ump));
+	if (data->altsetting != MIDI2_ALTERNATE) {
+		LOG_WRN("MIDI2.0 is not enabled");
+		return -EIO;
+	}
+
+	if (buflen > ring_buf_space_get(&data->tx_queue)) {
+		LOG_WRN("Not enough space in tx queue");
+		return -ENOBUFS;
+	}
+
+	for (size_t i = 0; i < words; i++) {
+		word = sys_cpu_to_le32(ump.data[i]);
+		ring_buf_put(&data->tx_queue, (const uint8_t *)&word, 4);
+	}
+	k_work_submit(&data->tx_work);
+
+	return 0;
+}
+
+void usbd_midi_set_ops(const struct device *dev, const struct usbd_midi_ops *ops)
+{
+	struct usbd_midi_data *data = dev->data;
+
+	if (ops == NULL) {
+		memset(&data->ops, 0, sizeof(struct usbd_midi_ops));
+	} else {
+		memcpy(&data->ops, ops, sizeof(struct usbd_midi_ops));
+	}
+
+	LOG_DBG("Set ops for %s to %p", dev->name, ops);
+}
+
+/* Group Terminal Block unique identification number, type and protocol
+ * see midi20 5.4.2 Group Terminal Block Descriptor
+ */
+#define GRPTRM_BLOCK_ID(node) UTIL_INC(DT_NODE_CHILD_IDX(node))
+#define GRPTRM_BLOCK_TYPE(node)                                                   \
+	COND_CODE_1(DT_ENUM_HAS_VALUE(node, terminal_type, input_only),           \
+		(GR_TRM_INPUT_ONLY),                                              \
+		(COND_CODE_1(DT_ENUM_HAS_VALUE(node, terminal_type, output_only), \
+			(GR_TRM_OUTPUT_ONLY),                                     \
+			(GR_TRM_BIDIRECTIONAL)                                    \
+		))                                                                \
+	)
+#define GRPTRM_PROTOCOL(node)                                                                     \
+	COND_CODE_1(DT_ENUM_HAS_VALUE(node, protocol, midi2),                                     \
+		(MIDI_2_0),                                                                       \
+		(COND_CODE_1(DT_ENUM_HAS_VALUE(node, protocol, midi1_up_to_64b),                  \
+				(MIDI_1_0_UP_TO_64_BITS),                                         \
+				(COND_CODE_1(DT_ENUM_HAS_VALUE(node, protocol, midi1_up_to_128b), \
+					(MIDI_1_0_UP_TO_128_BITS),                                \
+					(USE_MIDI_CI)                                             \
+				))                                                                \
+			))                                                                        \
+		)
+
+/* Group Terminal Block unique identification number with a trailing comma
+ * if that block is bidirectional or of given terminal type; otherwise empty
+ */
+#define GRPTRM_BLOCK_ID_SEP_IF(node, ttype)                                    \
+	IF_ENABLED(                                                            \
+		UTIL_OR(DT_ENUM_HAS_VALUE(node, terminal_type, bidirectional), \
+			DT_ENUM_HAS_VALUE(node, terminal_type, ttype)),        \
+		(GRPTRM_BLOCK_ID(node),))
+
+/* All unique identification numbers of output+bidir group terminal blocks */
+#define GRPTRM_OUTPUT_BLOCK_IDS(n) \
+	DT_INST_FOREACH_CHILD_VARGS(n, GRPTRM_BLOCK_ID_SEP_IF, output_only)
+
+/* All unique identification numbers of input+bidir group terminal blocks */
+#define GRPTRM_INPUT_BLOCK_IDS(n) \
+	DT_INST_FOREACH_CHILD_VARGS(n, GRPTRM_BLOCK_ID_SEP_IF, input_only)
+
+#define N_INPUTS(n)  sizeof((uint8_t[]){GRPTRM_INPUT_BLOCK_IDS(n)})
+#define N_OUTPUTS(n) sizeof((uint8_t[]){GRPTRM_OUTPUT_BLOCK_IDS(n)})
+
+#define USBD_MIDI_VALIDATE_GRPTRM_BLOCK(node)                              \
+	BUILD_ASSERT(DT_REG_ADDR(node) < 16,                               \
+		     "Group Terminal Block address must be within 0..15"); \
+	BUILD_ASSERT(DT_REG_ADDR(node) + DT_REG_SIZE(node) <= 16,          \
+		     "Too many Group Terminals in this Block");
+
+#define USBD_MIDI_VALIDATE_INSTANCE(n) \
+	DT_INST_FOREACH_CHILD(n, USBD_MIDI_VALIDATE_GRPTRM_BLOCK)
+
+#define USBD_MIDI2_INIT_GRPTRM_BLOCK_DESCRIPTOR(node)                       \
+	{                                                                   \
+		.bLength = sizeof(struct usb_midi_grptrm_block_descriptor), \
+		.bDescriptorType = CS_GR_TRM_BLOCK,                         \
+		.bDescriptorSubtype = GR_TRM_BLOCK,                         \
+		.bGrpTrmBlkID = GRPTRM_BLOCK_ID(node),                      \
+		.bGrpTrmBlkType = GRPTRM_BLOCK_TYPE(node),                  \
+		.nGroupTrm = DT_REG_ADDR(node),                             \
+		.nNumGroupTrm = DT_REG_SIZE(node),                          \
+		.iBlockItem = 0,                                            \
+		.bMIDIProtocol = GRPTRM_PROTOCOL(node),                     \
+		.wMaxInputBandwidth = 0x0000,                               \
+		.wMaxOutputBandwidth = 0x0000,                              \
+	}
+
+#define USBD_MIDI2_GRPTRM_TOTAL_LEN(n)                    \
+	sizeof(struct usb_midi_grptrm_header_descriptor)  \
+	+ DT_INST_CHILD_NUM_STATUS_OKAY(n)                \
+	* sizeof(struct usb_midi_grptrm_block_descriptor)
+
+#define USBD_MIDI_DEFINE_DESCRIPTORS(n)                                                  \
+	static struct usbd_midi_descriptors usbd_midi_desc_##n = {                       \
+		.iad = {                                                                 \
+			.bLength = sizeof(struct usb_association_descriptor),            \
+			.bDescriptorType = USB_DESC_INTERFACE_ASSOC,                     \
+			.bFirstInterface = 0,                                            \
+			.bInterfaceCount = 2,                                            \
+			.bFunctionClass = AUDIO,                                         \
+			.bFunctionSubClass = MIDISTREAMING,                              \
+		},                                                                       \
+		.if0_std = {                                                             \
+			.bLength = sizeof(struct usb_if_descriptor),                     \
+			.bDescriptorType = USB_DESC_INTERFACE,                           \
+			.bInterfaceNumber = 0,                                           \
+			.bAlternateSetting = 0,                                          \
+			.bNumEndpoints = 0,                                              \
+			.bInterfaceClass = AUDIO,                                        \
+			.bInterfaceSubClass = AUDIOCONTROL,                              \
+		},                                                                       \
+		.if0_cs = {                                                              \
+			.bLength = sizeof(struct usb_midi_cs_ac_header_descriptor),      \
+			.bDescriptorType = USB_DESC_CS_INTERFACE,                        \
+			.bDescriptorSubtype = MS_HEADER,                                 \
+			.bcdADC = sys_cpu_to_le16(0x0100),                               \
+			.wTotalLength = sizeof(struct usb_midi_cs_ac_header_descriptor), \
+			.bInCollection = 1,                                              \
+			.baInterfaceNr1 = 1,                                             \
+		},                                                                       \
+		.if1_0_std = {                                                           \
+			.bLength = sizeof(struct usb_if_descriptor),                     \
+			.bDescriptorType = USB_DESC_INTERFACE,                           \
+			.bInterfaceNumber = 1,                                           \
+			.bAlternateSetting = MIDI1_ALTERNATE,                            \
+			.bNumEndpoints = 2,                                              \
+			.bInterfaceClass = AUDIO,                                        \
+			.bInterfaceSubClass = MIDISTREAMING,                             \
+		},                                                                       \
+		.if1_0_ms_header = {                                                     \
+			.bLength = sizeof(struct usb_midi_header_descriptor),            \
+			.bDescriptorType = USB_DESC_CS_INTERFACE,                        \
+			.bDescriptorSubtype = MS_HEADER,                                 \
+			.bcdMSC = sys_cpu_to_le16(0x0100),                               \
+			.wTotalLength = sys_cpu_to_le16(                                 \
+				sizeof(struct usb_midi_header_descriptor)                \
+				+ 2 * (sizeof(struct usb_ep_descriptor) + 4)             \
+			),                                                               \
+		},                                                                       \
+		.if1_0_out_ep_fs = {                                                     \
+			.bLength = sizeof(struct usb_ep_descriptor),                     \
+			.bDescriptorType = USB_DESC_ENDPOINT,                            \
+			.bEndpointAddress = n + FIRST_OUT_EP_ADDR,                       \
+			.bmAttributes = USB_EP_TYPE_BULK,                                \
+			.wMaxPacketSize = sys_cpu_to_le16(64U),                          \
+		},                                                                       \
+		.if1_0_out_ep_hs = {                                                     \
+			.bLength = sizeof(struct usb_ep_descriptor),                     \
+			.bDescriptorType = USB_DESC_ENDPOINT,                            \
+			.bEndpointAddress = n + FIRST_OUT_EP_ADDR,                       \
+			.bmAttributes = USB_EP_TYPE_BULK,                                \
+			.wMaxPacketSize = sys_cpu_to_le16(512U),                         \
+		},                                                                       \
+		.if1_0_cs_out_ep = {                                                     \
+			.bLength = 4,                                                    \
+			.bDescriptorType = USB_DESC_CS_ENDPOINT,                         \
+			.bDescriptorSubtype = MS_GENERAL,                                \
+			.bNumGrpTrmBlock = 0,                                            \
+		},                                                                       \
+		.if1_0_in_ep_fs = {                                                      \
+			.bLength = sizeof(struct usb_ep_descriptor),                     \
+			.bDescriptorType = USB_DESC_ENDPOINT,                            \
+			.bEndpointAddress = n + FIRST_IN_EP_ADDR,                        \
+			.bmAttributes = USB_EP_TYPE_BULK,                                \
+			.wMaxPacketSize = sys_cpu_to_le16(64U),                          \
+		},                                                                       \
+		.if1_0_in_ep_hs = {                                                      \
+			.bLength = sizeof(struct usb_ep_descriptor),                     \
+			.bDescriptorType = USB_DESC_ENDPOINT,                            \
+			.bEndpointAddress = n + FIRST_IN_EP_ADDR,                        \
+			.bmAttributes = USB_EP_TYPE_BULK,                                \
+			.wMaxPacketSize = sys_cpu_to_le16(512U),                         \
+		},                                                                       \
+		.if1_0_cs_in_ep = {                                                      \
+			.bLength = 4 + N_INPUTS(n),                                      \
+			.bDescriptorType = USB_DESC_CS_ENDPOINT,                         \
+			.bDescriptorSubtype = MS_GENERAL,                                \
+			.bNumGrpTrmBlock = 0,                                            \
+		},                                                                       \
+		.if1_1_std = {                                                           \
+			.bLength = sizeof(struct usb_if_descriptor),                     \
+			.bDescriptorType = USB_DESC_INTERFACE,                           \
+			.bInterfaceNumber = 1,                                           \
+			.bAlternateSetting = MIDI2_ALTERNATE,                            \
+			.bNumEndpoints = 2,                                              \
+			.bInterfaceClass = AUDIO,                                        \
+			.bInterfaceSubClass = MIDISTREAMING,                             \
+		},                                                                       \
+		.if1_1_ms_header = {                                                     \
+			.bLength = sizeof(struct usb_midi_header_descriptor),            \
+			.bDescriptorType = USB_DESC_CS_INTERFACE,                        \
+			.bDescriptorSubtype = MS_HEADER,                                 \
+			.bcdMSC = sys_cpu_to_le16(0x0200),                               \
+			.wTotalLength = sys_cpu_to_le16(                                 \
+				sizeof(struct usb_midi_header_descriptor)),              \
+		},                                                                       \
+		.if1_1_out_ep_fs = {                                                     \
+			.bLength = sizeof(struct usb_ep_descriptor),                     \
+			.bDescriptorType = USB_DESC_ENDPOINT,                            \
+			.bEndpointAddress = n + FIRST_OUT_EP_ADDR,                       \
+			.bmAttributes = USB_EP_TYPE_BULK,                                \
+			.wMaxPacketSize = sys_cpu_to_le16(64U),                          \
+		},                                                                       \
+		.if1_1_out_ep_hs = {                                                     \
+			.bLength = sizeof(struct usb_ep_descriptor),                     \
+			.bDescriptorType = USB_DESC_ENDPOINT,                            \
+			.bEndpointAddress = n + FIRST_OUT_EP_ADDR,                       \
+			.bmAttributes = USB_EP_TYPE_BULK,                                \
+			.wMaxPacketSize = sys_cpu_to_le16(512U),                         \
+		},                                                                       \
+		.if1_1_cs_out_ep = {                                                     \
+			.bLength = 4 + N_OUTPUTS(n),                                     \
+			.bDescriptorType = USB_DESC_CS_ENDPOINT,                         \
+			.bDescriptorSubtype = MS_GENERAL_2_0,                            \
+			.bNumGrpTrmBlock = N_OUTPUTS(n),                                 \
+			.baAssoGrpTrmBlkID = {GRPTRM_OUTPUT_BLOCK_IDS(n)},               \
+		},                                                                       \
+		.if1_1_in_ep_fs = {                                                      \
+			.bLength = sizeof(struct usb_ep_descriptor),                     \
+			.bDescriptorType = USB_DESC_ENDPOINT,                            \
+			.bEndpointAddress = n + FIRST_IN_EP_ADDR,                        \
+			.bmAttributes = USB_EP_TYPE_BULK,                                \
+			.wMaxPacketSize = sys_cpu_to_le16(64U),                          \
+		},                                                                       \
+		.if1_1_in_ep_hs = {                                                      \
+			.bLength = sizeof(struct usb_ep_descriptor),                     \
+			.bDescriptorType = USB_DESC_ENDPOINT,                            \
+			.bEndpointAddress = n + FIRST_IN_EP_ADDR,                        \
+			.bmAttributes = USB_EP_TYPE_BULK,                                \
+			.wMaxPacketSize = sys_cpu_to_le16(512U),                         \
+		},                                                                       \
+		.if1_1_cs_in_ep = {                                                      \
+			.bLength = 4 + N_INPUTS(n),                                      \
+			.bDescriptorType = USB_DESC_CS_ENDPOINT,                         \
+			.bDescriptorSubtype = MS_GENERAL_2_0,                            \
+			.bNumGrpTrmBlock = N_INPUTS(n),                                  \
+			.baAssoGrpTrmBlkID = {GRPTRM_INPUT_BLOCK_IDS(n)},                \
+		},                                                                       \
+		.grptrm_header = {                                                       \
+			.bLength = sizeof(struct usb_midi_grptrm_header_descriptor),     \
+			.bDescriptorType = CS_GR_TRM_BLOCK,                              \
+			.bDescriptorSubtype = GR_TRM_BLOCK_HEADER,                       \
+			.wTotalLength = sys_cpu_to_le16(                                 \
+				USBD_MIDI2_GRPTRM_TOTAL_LEN(n)                           \
+			),                                                               \
+		},                                                                       \
+		.grptrm_blocks = {                                                       \
+			DT_INST_FOREACH_CHILD_SEP(                                       \
+				n, USBD_MIDI2_INIT_GRPTRM_BLOCK_DESCRIPTOR, (,)          \
+			)                                                                \
+		},                                                                       \
+	};                                                                               \
+	static const struct usb_desc_header *usbd_midi_desc_array_fs_##n[] = {           \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.iad,                       \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if0_std,                   \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if0_cs,                    \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_0_std,                 \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_0_ms_header,           \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_0_out_ep_fs,           \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_0_cs_out_ep,           \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_0_in_ep_fs,            \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_0_cs_in_ep,            \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_1_std,                 \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_1_ms_header,           \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_1_out_ep_fs,           \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_1_cs_out_ep,           \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_1_in_ep_fs,            \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_1_cs_in_ep,            \
+		NULL,                                                                    \
+	};                                                                               \
+	static const struct usb_desc_header *usbd_midi_desc_array_hs_##n[] = {           \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.iad,                       \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if0_std,                   \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if0_cs,                    \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_0_std,                 \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_0_ms_header,           \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_0_out_ep_hs,           \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_0_cs_out_ep,           \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_0_in_ep_hs,            \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_0_cs_in_ep,            \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_1_std,                 \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_1_ms_header,           \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_1_out_ep_hs,           \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_1_cs_out_ep,           \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_1_in_ep_hs,            \
+		(struct usb_desc_header *)&usbd_midi_desc_##n.if1_1_cs_in_ep,            \
+		NULL,                                                                    \
+	};
+
+#define USBD_MIDI_DEFINE_DEVICE(n)                                           \
+	USBD_MIDI_VALIDATE_INSTANCE(n)                                       \
+	USBD_MIDI_DEFINE_DESCRIPTORS(n);                                     \
+	USBD_DEFINE_CLASS(midi_##n, &usbd_midi_class_api,                    \
+			  (void *)DEVICE_DT_GET(DT_DRV_INST(n)), NULL);      \
+	static const struct usbd_midi_config usbd_midi_config_##n = {        \
+		.desc = &usbd_midi_desc_##n,                                 \
+		.fs_descs = usbd_midi_desc_array_fs_##n,                     \
+		.hs_descs = usbd_midi_desc_array_hs_##n,                     \
+	};                                                                   \
+	static struct usbd_midi_data usbd_midi_data_##n = {                  \
+		.class_data = &midi_##n,                                     \
+		.altsetting = MIDI1_ALTERNATE,                               \
+	};                                                                   \
+	DEVICE_DT_INST_DEFINE(n, usbd_midi_preinit, NULL,                    \
+			      &usbd_midi_data_##n, &usbd_midi_config_##n,    \
+			      POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL);
+
+DT_INST_FOREACH_STATUS_OKAY(USBD_MIDI_DEFINE_DEVICE)
diff --git a/subsys/usb/device_next/class/usbd_msc.c b/subsys/usb/device_next/class/usbd_msc.c
index 6f8b7c46226..07d5d09347f 100644
--- a/subsys/usb/device_next/class/usbd_msc.c
+++ b/subsys/usb/device_next/class/usbd_msc.c
@@ -61,7 +61,7 @@ struct CSW {
 #define MSC_NUM_INSTANCES CONFIG_USBD_MSC_INSTANCES_COUNT
 
 /* Can be 64 if device is not High-Speed capable */
-#define MSC_BUF_SIZE 512
+#define MSC_BUF_SIZE USBD_MAX_BULK_MPS
 
 UDC_BUF_POOL_DEFINE(msc_ep_pool,
 		    MSC_NUM_INSTANCES * 2, MSC_BUF_SIZE,
@@ -149,7 +149,8 @@ static uint8_t msc_get_bulk_in(struct usbd_class_data *const c_data)
 	struct msc_bot_ctx *ctx = usbd_class_get_private(c_data);
 	struct msc_bot_desc *desc = ctx->desc;
 
-	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
 		return desc->if0_hs_in_ep.bEndpointAddress;
 	}
 
@@ -162,7 +163,8 @@ static uint8_t msc_get_bulk_out(struct usbd_class_data *const c_data)
 	struct msc_bot_ctx *ctx = usbd_class_get_private(c_data);
 	struct msc_bot_desc *desc = ctx->desc;
 
-	if (usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_bus_speed(uds_ctx) == USBD_SPEED_HS) {
 		return desc->if0_hs_out_ep.bEndpointAddress;
 	}
 
@@ -755,7 +757,7 @@ static void *msc_bot_get_desc(struct usbd_class_data *const c_data,
 {
 	struct msc_bot_ctx *ctx = usbd_class_get_private(c_data);
 
-	if (speed == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED && speed == USBD_SPEED_HS) {
 		return ctx->hs_desc;
 	}
 
diff --git a/subsys/usb/device_next/class/usbd_uac2.c b/subsys/usb/device_next/class/usbd_uac2.c
index b2bc77da290..2e55a9a017a 100644
--- a/subsys/usb/device_next/class/usbd_uac2.c
+++ b/subsys/usb/device_next/class/usbd_uac2.c
@@ -4,7 +4,11 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stddef.h>
+#include <stdint.h>
+
 #include <zephyr/kernel.h>
+#include <zephyr/sys/__assert.h>
 #include <zephyr/sys/atomic.h>
 #include <zephyr/sys/byteorder.h>
 
@@ -209,9 +213,49 @@ static int terminal_to_as_interface(const struct device *dev, uint8_t terminal)
 void usbd_uac2_set_ops(const struct device *dev,
 		       const struct uac2_ops *ops, void *user_data)
 {
+	const struct uac2_cfg *cfg = dev->config;
 	struct uac2_ctx *ctx = dev->data;
 
 	__ASSERT(ops->sof_cb, "SOF callback is mandatory");
+	__ASSERT(ops->terminal_update_cb, "terminal_update_cb is mandatory");
+
+	for (uint8_t i = 0U; i < cfg->num_ifaces; i++) {
+		const uint16_t ep_idx = cfg->ep_indexes[i];
+
+		if (cfg->fb_indexes[i] != 0U) {
+			__ASSERT(ops->feedback_cb, "feedback_cb is mandatory");
+		}
+
+		if (ep_idx) {
+			const struct usb_ep_descriptor *desc = NULL;
+
+			if (cfg->fs_descriptors != NULL) {
+				/* If fs_descriptors is non-NULL and ep_idx is non-zero then
+				 * cfg->fs_descriptors[ep_idx] is non-NULL
+				 */
+				desc = (const struct usb_ep_descriptor *)
+					       cfg->fs_descriptors[ep_idx];
+			} else if (cfg->hs_descriptors != NULL) {
+				/* If hs_descriptors is non-NULL and ep_idx is non-zero then
+				 * cfg->hs_descriptors[ep_idx] is non-NULL
+				 */
+				desc = (const struct usb_ep_descriptor *)
+					       cfg->hs_descriptors[ep_idx];
+			}
+
+			if (desc != NULL) {
+				if (USB_EP_DIR_IS_OUT(desc->bEndpointAddress)) {
+					__ASSERT(ops->get_recv_buf, "get_recv_buf is mandatory");
+					__ASSERT(ops->data_recv_cb, "data_recv_cb is mandatory");
+				}
+
+				if (USB_EP_DIR_IS_IN(desc->bEndpointAddress)) {
+					__ASSERT(ops->buf_release_cb,
+						 "buf_release_cb is mandatory");
+				}
+			}
+		}
+	}
 
 	ctx->ops = ops;
 	ctx->user_data = user_data;
@@ -284,7 +328,6 @@ int usbd_uac2_send(const struct device *dev, uint8_t terminal,
 		 */
 		LOG_ERR("No netbuf for send");
 		atomic_clear_bit(queued_bits, as_idx);
-		ctx->ops->buf_release_cb(dev, terminal, data, ctx->user_data);
 		return -ENOMEM;
 	}
 
@@ -293,7 +336,6 @@ int usbd_uac2_send(const struct device *dev, uint8_t terminal,
 		LOG_ERR("Failed to enqueue net_buf for 0x%02x", ep);
 		net_buf_unref(buf);
 		atomic_clear_bit(queued_bits, as_idx);
-		ctx->ops->buf_release_cb(dev, terminal, data, ctx->user_data);
 	}
 
 	return ret;
@@ -848,7 +890,7 @@ static void *uac2_get_desc(struct usbd_class_data *const c_data,
 	struct device *dev = usbd_class_get_private(c_data);
 	const struct uac2_cfg *cfg = dev->config;
 
-	if (speed == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED && speed == USBD_SPEED_HS) {
 		return cfg->hs_descriptors;
 	}
 
diff --git a/subsys/usb/device_next/usbd_ch9.c b/subsys/usb/device_next/usbd_ch9.c
index 00f8074187b..827206af7c3 100644
--- a/subsys/usb/device_next/usbd_ch9.c
+++ b/subsys/usb/device_next/usbd_ch9.c
@@ -426,6 +426,8 @@ static int sreq_get_status(struct usbd_context *const uds_ctx,
 
 		response = uds_ctx->status.rwup ?
 			   USB_GET_STATUS_REMOTE_WAKEUP : 0;
+		response |= uds_ctx->status.self_powered ?
+			    USB_GET_STATUS_SELF_POWERED : 0;
 		break;
 	case USB_REQTYPE_RECIPIENT_ENDPOINT:
 		response = usbd_ep_is_halted(uds_ctx, ep) ? BIT(0) : 0;
@@ -470,9 +472,11 @@ static int sreq_get_desc_cfg(struct usbd_context *const uds_ctx,
 
 	/*
 	 * If the other-speed-configuration-descriptor is requested and the
-	 * controller does not support high speed, respond with an error.
+	 * controller (or stack) does not support high speed, respond with
+	 * an error.
 	 */
-	if (other_cfg && usbd_caps_speed(uds_ctx) != USBD_SPEED_HS) {
+	if (other_cfg && !(USBD_SUPPORTS_HIGH_SPEED &&
+	    (usbd_caps_speed(uds_ctx) == USBD_SPEED_HS))) {
 		errno = -ENOTSUP;
 		return 0;
 	}
@@ -689,7 +693,8 @@ static int sreq_get_dev_qualifier(struct usbd_context *const uds_ctx,
 	 * If the Device Qualifier descriptor is requested and the controller
 	 * does not support high speed, respond with an error.
 	 */
-	if (usbd_caps_speed(uds_ctx) != USBD_SPEED_HS) {
+	if (!USBD_SUPPORTS_HIGH_SPEED ||
+	    usbd_caps_speed(uds_ctx) != USBD_SPEED_HS) {
 		errno = -ENOTSUP;
 		return 0;
 	}
diff --git a/subsys/usb/device_next/usbd_class.c b/subsys/usb/device_next/usbd_class.c
index 465480bd0e3..48f3d6d7268 100644
--- a/subsys/usb/device_next/usbd_class.c
+++ b/subsys/usb/device_next/usbd_class.c
@@ -215,7 +215,7 @@ usbd_class_node_get(const char *name, const enum usbd_speed speed)
 				return c_nd;
 			}
 		}
-	} else if (speed == USBD_SPEED_HS) {
+	} else if (USBD_SUPPORTS_HIGH_SPEED && speed == USBD_SPEED_HS) {
 		STRUCT_SECTION_FOREACH_ALTERNATE(usbd_class_hs,
 						 usbd_class_node, c_nd) {
 			if (strcmp(name, c_nd->c_data->name) == 0) {
@@ -340,13 +340,30 @@ int usbd_register_class(struct usbd_context *const uds_ctx,
 	return ret;
 }
 
+static bool is_blocklisted(const struct usbd_class_node *const c_nd,
+			   const char *const list[])
+{
+	for (int i = 0; list[i] != NULL; i++) {
+		if (strcmp(c_nd->c_data->name, list[i]) == 0) {
+			return true;
+		}
+	}
+
+	return false;
+}
+
 int usbd_register_all_classes(struct usbd_context *const uds_ctx,
-			      const enum usbd_speed speed, const uint8_t cfg)
+			      const enum usbd_speed speed, const uint8_t cfg,
+			      const char *const blocklist[])
 {
 	int ret;
 
-	if (speed == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED && speed == USBD_SPEED_HS) {
 		STRUCT_SECTION_FOREACH_ALTERNATE(usbd_class_hs, usbd_class_node, c_nd) {
+			if (blocklist != NULL && is_blocklisted(c_nd, blocklist)) {
+				continue;
+			}
+
 			ret = usbd_register_class(uds_ctx, c_nd->c_data->name,
 						  speed, cfg);
 			if (ret) {
@@ -361,6 +378,10 @@ int usbd_register_all_classes(struct usbd_context *const uds_ctx,
 
 	if (speed == USBD_SPEED_FS) {
 		STRUCT_SECTION_FOREACH_ALTERNATE(usbd_class_fs, usbd_class_node, c_nd) {
+			if (blocklist != NULL && is_blocklisted(c_nd, blocklist)) {
+				continue;
+			}
+
 			ret = usbd_register_class(uds_ctx, c_nd->c_data->name,
 						  speed, cfg);
 			if (ret) {
@@ -409,8 +430,8 @@ int usbd_unregister_class(struct usbd_context *const uds_ctx,
 	/* TODO: The use of atomic here does not make this code thread safe.
 	 * The atomic should be changed to something else.
 	 */
-	if (speed == USBD_SPEED_HS) {
-		STRUCT_SECTION_FOREACH_ALTERNATE(usbd_class_fs,
+	if (USBD_SUPPORTS_HIGH_SPEED && speed == USBD_SPEED_HS) {
+		STRUCT_SECTION_FOREACH_ALTERNATE(usbd_class_hs,
 						 usbd_class_node, i) {
 			if ((i->c_data == c_nd->c_data) &&
 			    atomic_test_bit(&i->state, USBD_CCTX_REGISTERED)) {
@@ -419,7 +440,7 @@ int usbd_unregister_class(struct usbd_context *const uds_ctx,
 			}
 		}
 	} else {
-		STRUCT_SECTION_FOREACH_ALTERNATE(usbd_class_hs,
+		STRUCT_SECTION_FOREACH_ALTERNATE(usbd_class_fs,
 						 usbd_class_node, i) {
 			if ((i->c_data == c_nd->c_data) &&
 			    atomic_test_bit(&i->state, USBD_CCTX_REGISTERED)) {
@@ -449,7 +470,7 @@ int usbd_unregister_all_classes(struct usbd_context *const uds_ctx,
 {
 	int ret;
 
-	if (speed == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED && speed == USBD_SPEED_HS) {
 		STRUCT_SECTION_FOREACH_ALTERNATE(usbd_class_hs, usbd_class_node, c_nd) {
 			ret = usbd_unregister_class(uds_ctx, c_nd->c_data->name,
 						    speed, cfg);
diff --git a/subsys/usb/device_next/usbd_config.c b/subsys/usb/device_next/usbd_config.c
index 9d8627028a9..8a589722e25 100644
--- a/subsys/usb/device_next/usbd_config.c
+++ b/subsys/usb/device_next/usbd_config.c
@@ -266,6 +266,12 @@ int usbd_add_configuration(struct usbd_context *const uds_ctx,
 		goto add_configuration_exit;
 	}
 
+	if (speed == USBD_SPEED_HS && !USBD_SUPPORTS_HIGH_SPEED) {
+		LOG_ERR("Stack was compiled without High-Speed support");
+		ret = -ENOTSUP;
+		goto add_configuration_exit;
+	}
+
 	if (speed == USBD_SPEED_HS &&
 	    usbd_caps_speed(uds_ctx) == USBD_SPEED_FS) {
 		LOG_ERR("Controller doesn't support HS");
diff --git a/subsys/usb/device_next/usbd_core.c b/subsys/usb/device_next/usbd_core.c
index 64c0a0ab654..9f24530fc2c 100644
--- a/subsys/usb/device_next/usbd_core.c
+++ b/subsys/usb/device_next/usbd_core.c
@@ -228,12 +228,14 @@ int usbd_device_shutdown_core(struct usbd_context *const uds_ctx)
 	struct usbd_config_node *cfg_nd;
 	int ret;
 
-	SYS_SLIST_FOR_EACH_CONTAINER(&uds_ctx->hs_configs, cfg_nd, node) {
-		uint8_t cfg_value = usbd_config_get_value(cfg_nd);
-
-		ret = usbd_class_remove_all(uds_ctx, USBD_SPEED_HS, cfg_value);
-		if (ret) {
-			LOG_ERR("Failed to cleanup registered classes, %d", ret);
+	if (USBD_SUPPORTS_HIGH_SPEED) {
+		SYS_SLIST_FOR_EACH_CONTAINER(&uds_ctx->hs_configs, cfg_nd, node) {
+			uint8_t cfg_value = usbd_config_get_value(cfg_nd);
+
+			ret = usbd_class_remove_all(uds_ctx, USBD_SPEED_HS, cfg_value);
+			if (ret) {
+				LOG_ERR("Failed to cleanup registered classes, %d", ret);
+			}
 		}
 	}
 
diff --git a/subsys/usb/device_next/usbd_device.c b/subsys/usb/device_next/usbd_device.c
index 282dadfd699..489497ee926 100644
--- a/subsys/usb/device_next/usbd_device.c
+++ b/subsys/usb/device_next/usbd_device.c
@@ -197,6 +197,13 @@ int usbd_wakeup_request(struct usbd_context *const uds_ctx)
 	return ret;
 }
 
+void usbd_self_powered(struct usbd_context *uds_ctx, const bool status)
+{
+	usbd_device_lock(uds_ctx);
+	uds_ctx->status.self_powered = status;
+	usbd_device_unlock(uds_ctx);
+}
+
 bool usbd_is_suspended(struct usbd_context *uds_ctx)
 {
 	return uds_ctx->status.suspended;
@@ -249,6 +256,7 @@ int usbd_enable(struct usbd_context *const uds_ctx)
 {
 	int ret;
 
+	k_sched_lock();
 	usbd_device_lock(uds_ctx);
 
 	if (!usbd_is_initialized(uds_ctx)) {
@@ -279,6 +287,8 @@ int usbd_enable(struct usbd_context *const uds_ctx)
 
 enable_exit:
 	usbd_device_unlock(uds_ctx);
+	k_sched_unlock();
+
 	return ret;
 }
 
diff --git a/subsys/usb/device_next/usbd_device.h b/subsys/usb/device_next/usbd_device.h
index e2f0d98ab8b..8d29a19e6a9 100644
--- a/subsys/usb/device_next/usbd_device.h
+++ b/subsys/usb/device_next/usbd_device.h
@@ -45,7 +45,7 @@ static inline uint8_t usbd_get_num_configs(const struct usbd_context *const uds_
 
 	if (speed == USBD_SPEED_FS) {
 		desc = uds_ctx->fs_desc;
-	} else if (speed == USBD_SPEED_HS) {
+	} else if (USBD_SUPPORTS_HIGH_SPEED && speed == USBD_SPEED_HS) {
 		desc = uds_ctx->hs_desc;
 	} else {
 		return 0;
@@ -70,7 +70,7 @@ static inline void usbd_set_num_configs(struct usbd_context *const uds_ctx,
 
 	if (speed == USBD_SPEED_FS) {
 		desc = uds_ctx->fs_desc;
-	} else if (speed == USBD_SPEED_HS) {
+	} else if (USBD_SUPPORTS_HIGH_SPEED && speed == USBD_SPEED_HS) {
 		desc = uds_ctx->hs_desc;
 	} else {
 		return;
diff --git a/subsys/usb/device_next/usbd_init.c b/subsys/usb/device_next/usbd_init.c
index fc31c8a211a..021fc8f2fca 100644
--- a/subsys/usb/device_next/usbd_init.c
+++ b/subsys/usb/device_next/usbd_init.c
@@ -281,18 +281,20 @@ int usbd_init_configurations(struct usbd_context *const uds_ctx)
 
 	usbd_init_update_fs_mps0(uds_ctx);
 
-	SYS_SLIST_FOR_EACH_CONTAINER(&uds_ctx->hs_configs, cfg_nd, node) {
-		int ret;
+	if (USBD_SUPPORTS_HIGH_SPEED) {
+		SYS_SLIST_FOR_EACH_CONTAINER(&uds_ctx->hs_configs, cfg_nd, node) {
+			int ret;
 
-		ret = init_configuration(uds_ctx, USBD_SPEED_HS, cfg_nd);
-		if (ret) {
-			LOG_ERR("Failed to init HS configuration %u",
-				usbd_config_get_value(cfg_nd));
-			return ret;
-		}
+			ret = init_configuration(uds_ctx, USBD_SPEED_HS, cfg_nd);
+			if (ret) {
+				LOG_ERR("Failed to init HS configuration %u",
+					usbd_config_get_value(cfg_nd));
+				return ret;
+			}
 
-		LOG_INF("HS bNumConfigurations %u",
-			usbd_get_num_configs(uds_ctx, USBD_SPEED_HS));
+			LOG_INF("HS bNumConfigurations %u",
+				usbd_get_num_configs(uds_ctx, USBD_SPEED_HS));
+		}
 	}
 
 	SYS_SLIST_FOR_EACH_CONTAINER(&uds_ctx->fs_configs, cfg_nd, node) {
diff --git a/subsys/usb/device_next/usbd_interface.c b/subsys/usb/device_next/usbd_interface.c
index c5d817acef1..9e94b9eb661 100644
--- a/subsys/usb/device_next/usbd_interface.c
+++ b/subsys/usb/device_next/usbd_interface.c
@@ -184,9 +184,10 @@ int usbd_interface_set(struct usbd_context *const uds_ctx,
 	}
 
 	LOG_INF("Set Interfaces %u, alternate %u -> %u", iface, cur_alt, alt);
-	if (alt == cur_alt) {
-		return 0;
-	}
+	/*
+	 * Disable/enable endpoints even if the new alternate is the same as
+	 * the current one, forcing the endpoint to reset to defaults.
+	 */
 
 	/* Test if interface or interface alternate exist */
 	ret = usbd_interface_modify(uds_ctx, class, EP_OP_TEST, iface, alt);
diff --git a/subsys/usb/device_next/usbd_shell.c b/subsys/usb/device_next/usbd_shell.c
index 6b321204a24..4597143e78b 100644
--- a/subsys/usb/device_next/usbd_shell.c
+++ b/subsys/usb/device_next/usbd_shell.c
@@ -147,7 +147,8 @@ static int register_classes(const struct shell *sh)
 		shell_print(sh, "dev: register FS %s", c_nd->c_data->name);
 	}
 
-	if (usbd_caps_speed(my_uds_ctx) != USBD_SPEED_HS) {
+	if (!USBD_SUPPORTS_HIGH_SPEED ||
+	    usbd_caps_speed(my_uds_ctx) != USBD_SPEED_HS) {
 		return 0;
 	}
 
diff --git a/subsys/usb/host/CMakeLists.txt b/subsys/usb/host/CMakeLists.txt
index 1f29b2c7af2..f48f5b8c714 100644
--- a/subsys/usb/host/CMakeLists.txt
+++ b/subsys/usb/host/CMakeLists.txt
@@ -16,4 +16,9 @@ zephyr_library_sources_ifdef(
 	usbh_shell.c
 )
 
+zephyr_library_sources_ifdef(
+  CONFIG_USBIP
+  usbip.c
+)
+
 zephyr_linker_sources(DATA_SECTIONS usbh_data.ld)
diff --git a/subsys/usb/host/Kconfig b/subsys/usb/host/Kconfig
index e3055e0026c..8da3c95ebf7 100644
--- a/subsys/usb/host/Kconfig
+++ b/subsys/usb/host/Kconfig
@@ -15,6 +15,20 @@ module = USBH
 module-str = usbh
 source "subsys/logging/Kconfig.template.log_config"
 
+config USBH_USB_DEVICE_MAX
+	int "Maximum number of USB devices supported."
+	default 4
+	range 2 127
+	help
+	  Maximum number of USB devices supported for all controllers.
+
+config USBH_USB_DEVICE_HEAP
+	int "Memory used to cache device descriptors"
+	default 1024
+	range 256 16384
+	help
+	  Memory used to cache device descriptors.
+
 config USBH_SHELL
 	bool "USB host shell"
 	depends on SHELL
@@ -39,4 +53,6 @@ config USBH_MAX_UHC_MSG
 	help
 	  Maximum number of USB host controller events that can be queued.
 
+rsource "Kconfig.usbip"
+
 endif # USB_HOST_STACK
diff --git a/subsys/usb/host/Kconfig.usbip b/subsys/usb/host/Kconfig.usbip
new file mode 100644
index 00000000000..a880fdb48f2
--- /dev/null
+++ b/subsys/usb/host/Kconfig.usbip
@@ -0,0 +1,42 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+
+menuconfig USBIP
+	bool "USB USBIP support"
+	select EXPERIMENTAL
+	select EVENTS
+	depends on NETWORKING
+	depends on NET_IPV4
+	depends on NET_TCP
+	depends on NET_SOCKETS
+	help
+	  Experimental USB USBIP support.
+
+if USBIP
+
+config USBIP_THREAD_STACK_SIZE
+	int "USBIP thread stack size"
+	default 2048
+	help
+	  USBIP thread stack size in bytes.
+
+config USBIP_SUBMIT_BACKLOG_COUNT
+	int "Number of submit commands in the backlog"
+	range 32 128
+	default 48
+	help
+	  Number of submit commands that can be stored in the backlog.
+
+config USBIP_DEVICES_COUNT
+	int "Number of devices that can be exported"
+	range 1 255
+	default 1
+	help
+	  Number of devices that can be exported.
+
+module = USBIP
+module-str = usbip
+source "subsys/logging/Kconfig.template.log_config"
+
+endif # USBIP
diff --git a/subsys/usb/host/usbh_ch9.c b/subsys/usb/host/usbh_ch9.c
index 9c2cf087bee..29b01ea1624 100644
--- a/subsys/usb/host/usbh_ch9.c
+++ b/subsys/usb/host/usbh_ch9.c
@@ -29,6 +29,13 @@ K_SEM_DEFINE(ch9_req_sync, 0, 1);
 static int ch9_req_cb(struct usb_device *const udev, struct uhc_transfer *const xfer)
 {
 	LOG_DBG("Request finished %p, err %d", xfer, xfer->err);
+	if (xfer->err == -ECONNRESET) {
+		LOG_INF("Transfer %p cancelled", (void *)xfer);
+		usbh_xfer_free(udev, xfer);
+
+		return 0;
+	}
+
 	k_sem_give(&ch9_req_sync);
 
 	return 0;
@@ -53,7 +60,7 @@ int usbh_req_setup(struct usb_device *const udev,
 	uint8_t ep = usb_reqtype_is_to_device(&req) ? 0x00 : 0x80;
 	int ret;
 
-	xfer = usbh_xfer_alloc(udev, ep, 0, 64, SETUP_REQ_TIMEOUT, (void *)ch9_req_cb);
+	xfer = usbh_xfer_alloc(udev, ep, ch9_req_cb, NULL);
 	if (!xfer) {
 		return -ENOMEM;
 	}
@@ -74,7 +81,17 @@ int usbh_req_setup(struct usb_device *const udev,
 		goto buf_alloc_err;
 	}
 
-	k_sem_take(&ch9_req_sync, K_MSEC(SETUP_REQ_TIMEOUT));
+	if (k_sem_take(&ch9_req_sync, K_MSEC(SETUP_REQ_TIMEOUT)) != 0) {
+		ret = usbh_xfer_dequeue(udev, xfer);
+		if (ret != 0) {
+			LOG_ERR("Failed to cancel transfer");
+			return ret;
+		}
+
+		LOG_ERR("Timeout");
+		return -ETIMEDOUT;
+	}
+
 	ret = xfer->err;
 
 buf_alloc_err:
@@ -99,10 +116,11 @@ int usbh_req_desc(struct usb_device *const udev,
 }
 
 int usbh_req_desc_dev(struct usb_device *const udev,
+		      const uint16_t len,
 		      struct usb_device_descriptor *const desc)
 {
 	const uint8_t type = USB_DESC_DEVICE;
-	const uint16_t wLength = sizeof(struct usb_device_descriptor);
+	const uint16_t wLength = MIN(len, sizeof(struct usb_device_descriptor));
 	struct net_buf *buf;
 	int ret;
 
@@ -156,21 +174,8 @@ int usbh_req_set_address(struct usb_device *const udev,
 {
 	const uint8_t bmRequestType = USB_REQTYPE_DIR_TO_DEVICE << 7;
 	const uint8_t bRequest = USB_SREQ_SET_ADDRESS;
-	int ret;
-
-	ret = usbh_req_setup(udev, bmRequestType, bRequest, addr, 0, 0, NULL);
-	if (ret == 0) {
-		udev->addr = addr;
-		if (addr == 0) {
-			udev->state = USB_STATE_DEFAULT;
-		}
-
-		if (addr != 0 && udev->state == USB_STATE_DEFAULT) {
-			udev->state = USB_STATE_ADDRESSED;
-		}
-	}
 
-	return ret;
+	return usbh_req_setup(udev, bmRequestType, bRequest, addr, 0, 0, NULL);
 }
 
 int usbh_req_set_cfg(struct usb_device *const udev,
@@ -178,22 +183,8 @@ int usbh_req_set_cfg(struct usb_device *const udev,
 {
 	const uint8_t bmRequestType = USB_REQTYPE_DIR_TO_DEVICE << 7;
 	const uint8_t bRequest = USB_SREQ_SET_CONFIGURATION;
-	int ret;
-
-	/* Ignore the required state change condition for now. */
-	ret = usbh_req_setup(udev, bmRequestType, bRequest, cfg, 0, 0, NULL);
-	if (ret == 0) {
-		udev->actual_cfg = cfg;
-		if (cfg == 0) {
-			udev->state = USB_STATE_ADDRESSED;
-		}
 
-		if (cfg != 0 && udev->state == USB_STATE_ADDRESSED) {
-			udev->state = USB_STATE_CONFIGURED;
-		}
-	}
-
-	return ret;
+	return usbh_req_setup(udev, bmRequestType, bRequest, cfg, 0, 0, NULL);
 }
 
 int usbh_req_get_cfg(struct usb_device *const udev,
@@ -256,6 +247,30 @@ int usbh_req_clear_sfs_rwup(struct usb_device *const udev)
 			      NULL);
 }
 
+int usbh_req_set_sfs_halt(struct usb_device *const udev, const uint8_t ep)
+{
+	const uint8_t bmRequestType = USB_REQTYPE_RECIPIENT_ENDPOINT;
+	const uint8_t bRequest = USB_SREQ_SET_FEATURE;
+	const uint16_t wValue = USB_SFS_ENDPOINT_HALT;
+	const uint16_t wIndex = ep;
+
+	return usbh_req_setup(udev,
+			      bmRequestType, bRequest, wValue, wIndex, 0,
+			      NULL);
+}
+
+int usbh_req_clear_sfs_halt(struct usb_device *const udev, const uint8_t ep)
+{
+	const uint8_t bmRequestType = USB_REQTYPE_RECIPIENT_ENDPOINT;
+	const uint8_t bRequest = USB_SREQ_CLEAR_FEATURE;
+	const uint16_t wValue = USB_SFS_ENDPOINT_HALT;
+	const uint16_t wIndex = ep;
+
+	return usbh_req_setup(udev,
+			      bmRequestType, bRequest, wValue, wIndex, 0,
+			      NULL);
+}
+
 int usbh_req_set_hcfs_ppwr(struct usb_device *const udev,
 			   const uint8_t port)
 {
diff --git a/subsys/usb/host/usbh_ch9.h b/subsys/usb/host/usbh_ch9.h
index a60dc86527b..9e585c8dab6 100644
--- a/subsys/usb/host/usbh_ch9.h
+++ b/subsys/usb/host/usbh_ch9.h
@@ -27,6 +27,7 @@ int usbh_req_desc(struct usb_device *const udev,
 		  struct net_buf *const data);
 
 int usbh_req_desc_dev(struct usb_device *const udev,
+		      const uint16_t len,
 		      struct usb_device_descriptor *const dev);
 
 int usbh_req_desc_cfg(struct usb_device *const udev,
@@ -51,6 +52,10 @@ int usbh_req_set_sfs_rwup(struct usb_device *const udev);
 
 int usbh_req_clear_sfs_rwup(struct usb_device *const udev);
 
+int usbh_req_set_sfs_halt(struct usb_device *const udev, const uint8_t ep);
+
+int usbh_req_clear_sfs_halt(struct usb_device *const udev, const uint8_t ep);
+
 int usbh_req_set_hcfs_ppwr(const struct usb_device *udev,
 			   const uint8_t port);
 
diff --git a/subsys/usb/host/usbh_core.c b/subsys/usb/host/usbh_core.c
index ea624d0305a..c18ef39cb63 100644
--- a/subsys/usb/host/usbh_core.c
+++ b/subsys/usb/host/usbh_core.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 Nordic Semiconductor ASA
+ * Copyright (c) 2022,2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,13 +20,68 @@ LOG_MODULE_REGISTER(uhs, CONFIG_USBH_LOG_LEVEL);
 static K_KERNEL_STACK_DEFINE(usbh_stack, CONFIG_USBH_STACK_SIZE);
 static struct k_thread usbh_thread_data;
 
+static K_KERNEL_STACK_DEFINE(usbh_bus_stack, CONFIG_USBH_STACK_SIZE);
+static struct k_thread usbh_bus_thread_data;
+
 K_MSGQ_DEFINE(usbh_msgq, sizeof(struct uhc_event),
 	      CONFIG_USBH_MAX_UHC_MSG, sizeof(uint32_t));
 
+K_MSGQ_DEFINE(usbh_bus_msgq, sizeof(struct uhc_event),
+	      CONFIG_USBH_MAX_UHC_MSG, sizeof(uint32_t));
+
 static int usbh_event_carrier(const struct device *dev,
 			      const struct uhc_event *const event)
 {
-	return k_msgq_put(&usbh_msgq, event, K_NO_WAIT);
+	int err;
+
+	if (event->type == UHC_EVT_EP_REQUEST) {
+		err = k_msgq_put(&usbh_msgq, event, K_NO_WAIT);
+	} else {
+		err = k_msgq_put(&usbh_bus_msgq, event, K_NO_WAIT);
+	}
+
+	return err;
+}
+
+static void dev_connected_handler(struct usbh_contex *const ctx,
+				  const struct uhc_event *const event)
+{
+
+	LOG_DBG("Device connected event");
+	if (ctx->root != NULL) {
+		LOG_ERR("Device already connected");
+		usbh_device_free(ctx->root);
+		ctx->root = NULL;
+	}
+
+	ctx->root = usbh_device_alloc(ctx);
+	if (ctx->root == NULL) {
+		LOG_ERR("Failed allocate new device");
+		return;
+	}
+
+	ctx->root->state = USB_STATE_DEFAULT;
+
+	if (event->type == UHC_EVT_DEV_CONNECTED_HS) {
+		ctx->root->speed = USB_SPEED_SPEED_HS;
+	} else {
+		ctx->root->speed = USB_SPEED_SPEED_FS;
+	}
+
+	if (usbh_device_init(ctx->root)) {
+		LOG_ERR("Failed to reset new USB device");
+	}
+}
+
+static void dev_removed_handler(struct usbh_contex *const ctx)
+{
+	if (ctx->root != NULL) {
+		usbh_device_free(ctx->root);
+		ctx->root = NULL;
+		LOG_DBG("Device removed");
+	} else {
+		LOG_DBG("Spurious device removed event");
+	}
 }
 
 static int discard_ep_request(struct usbh_contex *const ctx,
@@ -47,26 +102,16 @@ static ALWAYS_INLINE int usbh_event_handler(struct usbh_contex *const ctx,
 {
 	int ret = 0;
 
-	if (event->type == UHC_EVT_EP_REQUEST) {
-		struct usb_device *const udev = event->xfer->udev;
-		usbh_udev_cb_t cb = event->xfer->cb;
-
-		if (event->xfer->cb) {
-			ret = cb(udev, event->xfer);
-		} else {
-			ret = discard_ep_request(ctx, event->xfer);
-		}
-		return ret;
-	}
-
 	switch (event->type) {
 	case UHC_EVT_DEV_CONNECTED_LS:
+		LOG_ERR("Low speed device not supported (connected event)");
+		break;
 	case UHC_EVT_DEV_CONNECTED_FS:
 	case UHC_EVT_DEV_CONNECTED_HS:
-		LOG_DBG("Device connected event");
+		dev_connected_handler(ctx, event);
 		break;
 	case UHC_EVT_DEV_REMOVED:
-		LOG_DBG("Device removed event");
+		dev_removed_handler(ctx);
 		break;
 	case UHC_EVT_RESETED:
 		LOG_DBG("Bus reset");
@@ -90,21 +135,49 @@ static ALWAYS_INLINE int usbh_event_handler(struct usbh_contex *const ctx,
 	return ret;
 }
 
+static void usbh_bus_thread(void *p1, void *p2, void *p3)
+{
+	ARG_UNUSED(p1);
+	ARG_UNUSED(p2);
+	ARG_UNUSED(p3);
+
+	struct usbh_contex *uhs_ctx;
+	struct uhc_event event;
+
+	while (true) {
+		k_msgq_get(&usbh_bus_msgq, &event, K_FOREVER);
+
+		uhs_ctx = (void *)uhc_get_event_ctx(event.dev);
+		usbh_event_handler(uhs_ctx, &event);
+	}
+}
+
 static void usbh_thread(void *p1, void *p2, void *p3)
 {
 	ARG_UNUSED(p1);
 	ARG_UNUSED(p2);
 	ARG_UNUSED(p3);
 
+	struct usbh_contex *uhs_ctx;
 	struct uhc_event event;
+	usbh_udev_cb_t cb;
+	int ret;
 
 	while (true) {
 		k_msgq_get(&usbh_msgq, &event, K_FOREVER);
 
-		STRUCT_SECTION_FOREACH(usbh_contex, uhs_ctx) {
-			if (uhs_ctx->dev == event.dev) {
-				usbh_event_handler(uhs_ctx, &event);
-			}
+		__ASSERT(event.type == UHC_EVT_EP_REQUEST, "Wrong event type");
+		uhs_ctx = (void *)uhc_get_event_ctx(event.dev);
+		cb = event.xfer->cb;
+
+		if (event.xfer->cb) {
+			ret = cb(event.xfer->udev, event.xfer);
+		} else {
+			ret = discard_ep_request(uhs_ctx, event.xfer);
+		}
+
+		if (ret) {
+			LOG_ERR("Failed to handle request completion callback");
 		}
 	}
 }
@@ -113,12 +186,14 @@ int usbh_init_device_intl(struct usbh_contex *const uhs_ctx)
 {
 	int ret;
 
-	ret = uhc_init(uhs_ctx->dev, usbh_event_carrier);
+	ret = uhc_init(uhs_ctx->dev, usbh_event_carrier, uhs_ctx);
 	if (ret != 0) {
 		LOG_ERR("Failed to init device driver");
 		return ret;
 	}
 
+	sys_dlist_init(&uhs_ctx->udevs);
+
 	STRUCT_SECTION_FOREACH(usbh_class_data, cdata) {
 		/*
 		 * For now, we have not implemented any class drivers,
@@ -140,6 +215,14 @@ static int uhs_pre_init(void)
 
 	k_thread_name_set(&usbh_thread_data, "usbh");
 
+	k_thread_create(&usbh_bus_thread_data, usbh_bus_stack,
+			K_KERNEL_STACK_SIZEOF(usbh_bus_stack),
+			usbh_bus_thread,
+			NULL, NULL, NULL,
+			K_PRIO_COOP(9), 0, K_NO_WAIT);
+
+	k_thread_name_set(&usbh_thread_data, "usbh_bus");
+
 	return 0;
 }
 
diff --git a/subsys/usb/host/usbh_device.c b/subsys/usb/host/usbh_device.c
index cfc4cc5998d..13a2a81ccd2 100644
--- a/subsys/usb/host/usbh_device.c
+++ b/subsys/usb/host/usbh_device.c
@@ -1,19 +1,530 @@
 /*
- * Copyright (c) 2023 Nordic Semiconductor ASA
+ * Copyright (c) 2023,2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <zephyr/usb/usbh.h>
+#include <zephyr/sys/byteorder.h>
+
 #include "usbh_device.h"
+#include "usbh_ch9.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(usbh_dev, CONFIG_USBH_LOG_LEVEL);
+
+K_MEM_SLAB_DEFINE_STATIC(usb_device_slab, sizeof(struct usb_device),
+			 CONFIG_USBH_USB_DEVICE_MAX, sizeof(void *));
+
+K_HEAP_DEFINE(usb_device_heap, CONFIG_USBH_USB_DEVICE_HEAP);
+
+struct usb_device *usbh_device_alloc(struct usbh_contex *const uhs_ctx)
+{
+	struct usb_device *udev;
+
+	if (k_mem_slab_alloc(&usb_device_slab, (void **)&udev, K_NO_WAIT)) {
+		LOG_ERR("Failed to allocate USB device memory");
+		return NULL;
+	}
+
+	memset(udev, 0, sizeof(struct usb_device));
+	udev->ctx = uhs_ctx;
+	sys_dlist_append(&uhs_ctx->udevs, &udev->node);
+	k_mutex_init(&udev->mutex);
+
+	return udev;
+}
+
+void usbh_device_free(struct usb_device *const udev)
+{
+	struct usbh_contex *const uhs_ctx = udev->ctx;
+
+	sys_bitarray_clear_bit(uhs_ctx->addr_ba, udev->addr);
+	sys_dlist_remove(&udev->node);
+	if (udev->cfg_desc != NULL) {
+		k_heap_free(&usb_device_heap, udev->cfg_desc);
+	}
+
+	k_mem_slab_free(&usb_device_slab, (void *)udev);
+}
+
+struct usb_device *usbh_device_get_any(struct usbh_contex *const uhs_ctx)
+{
+	sys_dnode_t *const node = sys_dlist_peek_head(&uhs_ctx->udevs);
+	struct usb_device *udev;
+
+	udev = SYS_DLIST_CONTAINER(node, udev, node);
+
+	return udev;
+}
+
+struct usb_device *usbh_device_get(struct usbh_contex *const uhs_ctx, const uint8_t addr)
+{
+	struct usb_device *udev;
+
+	SYS_DLIST_FOR_EACH_CONTAINER(&uhs_ctx->udevs, udev, node) {
+		if (addr == udev->addr) {
+			return udev;
+		}
+	}
+
+	return NULL;
+}
+
+static int validate_device_mps0(const struct usb_device *const udev)
+{
+	const uint8_t mps0 = udev->dev_desc.bMaxPacketSize0;
+
+	if (udev->speed == USB_SPEED_SPEED_SS || udev->speed == USB_SPEED_SPEED_LS) {
+		LOG_ERR("USB device speed not supported");
+		return -ENOTSUP;
+	}
+
+	if (udev->speed == USB_SPEED_SPEED_HS) {
+		if (mps0 != 64) {
+			LOG_ERR("HS device has wrong bMaxPacketSize0 %u", mps0);
+			return -EINVAL;
+		}
+	}
+
+	if (udev->speed == USB_SPEED_SPEED_FS) {
+		if (mps0 != 8 && mps0 != 16 && mps0 != 32 && mps0 != 64) {
+			LOG_ERR("FS device has wrong bMaxPacketSize0 %u", mps0);
+			return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static int alloc_device_address(struct usb_device *const udev, uint8_t *const addr)
+{
+	struct usbh_contex *const uhs_ctx = udev->ctx;
+	int val;
+	int err;
+
+	for (unsigned int i = 1; i < 128; i++) {
+		err = sys_bitarray_test_and_set_bit(uhs_ctx->addr_ba, i, &val);
+		if (err) {
+			return err;
+		}
+
+		if (val == 0) {
+			*addr = i;
+			return 0;
+		}
+	}
+
+	return -ENOENT;
+}
+
+enum ep_op {
+	EP_OP_TEST, /* Verify endpont descriptor */
+	EP_OP_UP,   /* Enable endpoint and update endpoint pointers */
+	EP_OP_DOWN, /* Disable endpoint and update endpoint pointers */
+};
+
+static void assign_ep_desc_ptr(struct usb_device *const udev,
+			       const uint8_t ep, void *const ptr)
+{
+	uint8_t idx = USB_EP_GET_IDX(ep) & 0xF;
+
+	if (USB_EP_DIR_IS_IN(ep)) {
+		udev->ep_in[idx].desc = ptr;
+	} else {
+		udev->ep_out[idx].desc = ptr;
+	}
+}
+
+static int handle_ep_op(struct usb_device *const udev,
+			const enum ep_op op, const uint8_t ep,
+			struct usb_ep_descriptor *const ep_desc)
+{
+	switch (op) {
+	case EP_OP_TEST:
+		break;
+	case EP_OP_UP:
+		if (ep_desc == NULL) {
+			return -ENOTSUP;
+		}
+
+		assign_ep_desc_ptr(udev, ep_desc->bEndpointAddress, ep_desc);
+		break;
+	case EP_OP_DOWN:
+		assign_ep_desc_ptr(udev, ep, NULL);
+		break;
+	}
+
+	return 0;
+}
+
+static int device_interface_modify(struct usb_device *const udev,
+				   const enum ep_op op,
+				   const uint8_t iface, const uint8_t alt)
+{
+	struct usb_cfg_descriptor *cfg_desc = udev->cfg_desc;
+	struct usb_if_descriptor *if_desc = NULL;
+	struct usb_ep_descriptor *ep_desc;
+	struct usb_desc_header *dhp;
+	bool found_iface = false;
+	void *desc_end;
+	int err;
+
+	dhp = udev->ifaces[iface].dhp;
+	desc_end = (void *)((uint8_t *)udev->cfg_desc + cfg_desc->wTotalLength);
+
+	while (dhp != NULL && (void *)dhp < desc_end) {
+		if (dhp->bDescriptorType == USB_DESC_INTERFACE) {
+			if_desc = (struct usb_if_descriptor *)dhp;
+
+			if (found_iface) {
+				break;
+			}
+
+			if (if_desc->bInterfaceNumber == iface &&
+			    if_desc->bAlternateSetting == alt) {
+				found_iface = true;
+				LOG_DBG("Found interface %u alternate %u", iface, alt);
+				if (if_desc->bNumEndpoints == 0) {
+					LOG_DBG("No endpoints, skip interface");
+					break;
+				}
+			}
+		}
+
+		if (dhp->bDescriptorType == USB_DESC_ENDPOINT && found_iface) {
+			ep_desc = (struct usb_ep_descriptor *)dhp;
+			err = handle_ep_op(udev, op, ep_desc->bEndpointAddress, ep_desc);
+			if (err) {
+				return err;
+			}
+
+			LOG_INF("Modify interface %u ep 0x%02x by op %u",
+				iface, ep_desc->bEndpointAddress, op);
+		}
+
+		dhp = (void *)((uint8_t *)dhp + dhp->bLength);
+	}
+
+
+	return found_iface ? 0 : -ENODATA;
+}
+
+int usbh_device_interface_set(struct usb_device *const udev,
+			      const uint8_t iface, const uint8_t alt,
+			      const bool dry)
+{
+	uint8_t cur_alt;
+	int err;
+
+	if (iface > UHC_INTERFACES_MAX) {
+		LOG_ERR("Unsupported number of interfaces");
+		return -EINVAL;
+	}
 
-#define USBH_USB_DEVICE_COUNT		1
+	err = k_mutex_lock(&udev->mutex, K_NO_WAIT);
+	if (err) {
+		LOG_ERR("Failed to lock USB device");
+		return err;
+	}
 
-static struct usb_device udevs[USBH_USB_DEVICE_COUNT];
+	if (!dry) {
+		err = usbh_req_set_alt(udev, iface, alt);
+		if (err) {
+			LOG_ERR("Set Interface %u alternate %u request failed", iface, alt);
+			goto error;
+		}
+	}
 
-struct usb_device *usbh_device_get_any(struct usbh_contex *const ctx)
+	cur_alt = udev->ifaces[iface].alternate;
+	LOG_INF("Set Interfaces %u, alternate %u -> %u", iface, cur_alt, alt);
+	if (alt == cur_alt) {
+		LOG_DBG("Already active interface alternate");
+		goto error;
+	}
+
+	/* Test if interface and interface alternate exist */
+	err = device_interface_modify(udev, EP_OP_TEST, iface, alt);
+	if (err) {
+		LOG_ERR("No interface %u with alternate %u", iface, alt);
+		goto error;
+	}
+
+	/* Shutdown current interface alternate */
+	err = device_interface_modify(udev, EP_OP_DOWN, iface, cur_alt);
+	if (err) {
+		LOG_ERR("Failed to shutdown interface %u alternate %u", iface, alt);
+		goto error;
+	}
+
+	/* Setup new interface alternate */
+	err = device_interface_modify(udev, EP_OP_UP, iface, alt);
+	if (err) {
+		LOG_ERR("Failed to setup interface %u alternate %u", iface, cur_alt);
+		goto error;
+	}
+
+	udev->ifaces[iface].alternate = alt;
+
+error:
+	k_mutex_unlock(&udev->mutex);
+
+	return 0;
+}
+
+static int parse_configuration_descriptor(struct usb_device *const udev)
+{
+	struct usb_cfg_descriptor *cfg_desc = udev->cfg_desc;
+	struct usb_association_descriptor *iad = NULL;
+	struct usb_if_descriptor *if_desc = NULL;
+	struct usb_ep_descriptor *ep_desc;
+	struct usb_desc_header *dhp;
+	uint8_t tmp_nif = 0;
+	void *desc_end;
+
+	dhp = (void *)((uint8_t *)udev->cfg_desc + cfg_desc->bLength);
+	desc_end = (void *)((uint8_t *)udev->cfg_desc + cfg_desc->wTotalLength);
+
+	while ((dhp->bDescriptorType != 0 || dhp->bLength != 0) && (void *)dhp < desc_end) {
+		if (dhp->bDescriptorType == USB_DESC_INTERFACE_ASSOC) {
+			iad = (struct usb_association_descriptor *)dhp;
+			LOG_DBG("bFirstInterface %u", iad->bFirstInterface);
+		}
+
+		if (dhp->bDescriptorType == USB_DESC_INTERFACE) {
+			if_desc = (struct usb_if_descriptor *)dhp;
+			LOG_DBG("bInterfaceNumber %u bAlternateSetting %u",
+				if_desc->bInterfaceNumber, if_desc->bAlternateSetting);
+
+			if (if_desc->bAlternateSetting == 0) {
+				if (tmp_nif >= UHC_INTERFACES_MAX) {
+					LOG_ERR("Unsupported number of interfaces");
+					return -EINVAL;
+				}
+
+				udev->ifaces[tmp_nif].dhp = dhp;
+				tmp_nif++;
+			}
+		}
+
+		if (dhp->bDescriptorType == USB_DESC_ENDPOINT) {
+			ep_desc = (struct usb_ep_descriptor *)dhp;
+
+			ep_desc->wMaxPacketSize = sys_le16_to_cpu(ep_desc->wMaxPacketSize);
+			LOG_DBG("bEndpointAddress 0x%02x wMaxPacketSize %u",
+				ep_desc->bEndpointAddress, ep_desc->wMaxPacketSize);
+
+			if (if_desc != NULL && if_desc->bAlternateSetting == 0) {
+				assign_ep_desc_ptr(udev, ep_desc->bEndpointAddress, ep_desc);
+			}
+		}
+
+		dhp = (void *)((uint8_t *)dhp + dhp->bLength);
+	}
+
+	if (cfg_desc->bNumInterfaces != tmp_nif) {
+		LOG_ERR("The configuration has an incorrect number of interfaces");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void reset_configuration(struct usb_device *const udev)
+{
+	/* Reset all endpoint pointers */
+	memset(udev->ep_in, 0, sizeof(udev->ep_in));
+	memset(udev->ep_out, 0, sizeof(udev->ep_out));
+
+	/* Reset all interface pointers */
+	memset(udev->ifaces, 0, sizeof(udev->ifaces));
+
+	udev->actual_cfg = 0;
+	udev->state = USB_STATE_ADDRESSED;
+}
+
+int usbh_device_set_configuration(struct usb_device *const udev, const uint8_t num)
 {
-	udevs->ctx = ctx;
+	struct usb_cfg_descriptor cfg_desc;
+	uint8_t idx;
+	int err;
+
+	err = k_mutex_lock(&udev->mutex, K_NO_WAIT);
+	if (err) {
+		LOG_ERR("Failed to lock USB device");
+		return err;
+	}
+
+	if (udev->actual_cfg == num) {
+		LOG_INF("Already active device configuration");
+		goto error;
+	}
+
+	if (num == 0) {
+		reset_configuration(udev);
+		err = usbh_req_set_cfg(udev, num);
+		if (err) {
+			LOG_ERR("Set Configuration %u request failed", num);
+		}
+
+		goto error;
+	}
+
+	idx = num - 1;
+
+	err = usbh_req_desc_cfg(udev, idx, sizeof(cfg_desc), &cfg_desc);
+	if (err) {
+		LOG_ERR("Failed to read configuration %u descriptor", num);
+		goto error;
+	}
+
+	if (cfg_desc.bDescriptorType != USB_DESC_CONFIGURATION) {
+		LOG_ERR("Failed to read configuration descriptor");
+		err = -EINVAL;
+		goto error;
+	}
+
+	if (cfg_desc.bNumInterfaces == 0) {
+		LOG_ERR("Configuration %u has no interfaces", cfg_desc.bNumInterfaces);
+		err = -EINVAL;
+		goto error;
+	}
+
+	if (cfg_desc.bNumInterfaces >= UHC_INTERFACES_MAX) {
+		LOG_ERR("Unsupported number of interfaces");
+		err = -EINVAL;
+		goto error;
+	}
+
+	udev->cfg_desc = k_heap_alloc(&usb_device_heap,
+				      cfg_desc.wTotalLength,
+				      K_NO_WAIT);
+	if (udev->cfg_desc == NULL) {
+		LOG_ERR("Failed to allocate memory for configuration descriptor");
+		err = -ENOMEM;
+		goto error;
+	}
+
+	err = usbh_req_set_cfg(udev, num);
+	if (err) {
+		LOG_ERR("Set Configuration %u request failed", num);
+		goto error;
+	}
+
+	memset(udev->cfg_desc, 0, cfg_desc.wTotalLength);
+	if (udev->state == USB_STATE_CONFIGURED) {
+		reset_configuration(udev);
+	}
+
+	err = usbh_req_desc_cfg(udev, idx, cfg_desc.wTotalLength, udev->cfg_desc);
+	if (err) {
+		LOG_ERR("Failed to read configuration descriptor");
+		k_heap_free(&usb_device_heap, udev->cfg_desc);
+		goto error;
+	}
+
+	if (memcmp(udev->cfg_desc, &cfg_desc, sizeof(cfg_desc))) {
+		LOG_ERR("Configuration descriptor read mismatch");
+		k_heap_free(&usb_device_heap, udev->cfg_desc);
+		goto error;
+	}
+
+	LOG_INF("Configuration %u bNumInterfaces %u",
+		cfg_desc.bConfigurationValue, cfg_desc.bNumInterfaces);
+
+	err = parse_configuration_descriptor(udev);
+	if (err) {
+		k_heap_free(&usb_device_heap, udev->cfg_desc);
+		goto error;
+	}
+
+	udev->actual_cfg = num;
+	udev->state = USB_STATE_CONFIGURED;
+
+error:
+	k_mutex_unlock(&udev->mutex);
+
+	return err;
+}
+
+int usbh_device_init(struct usb_device *const udev)
+{
+	struct usbh_contex *const uhs_ctx = udev->ctx;
+	uint8_t new_addr;
+	int err;
+
+	if (udev->state != USB_STATE_DEFAULT) {
+		LOG_ERR("USB device is not in default state");
+		return -EALREADY;
+	}
+
+	err = k_mutex_lock(&udev->mutex, K_NO_WAIT);
+	if (err) {
+		LOG_ERR("Failed to lock USB device");
+		return err;
+	}
+
+	/* FIXME: The port to which the device is connected should be reset. */
+	err = uhc_bus_reset(uhs_ctx->dev);
+	if (err) {
+		LOG_ERR("Failed to signal bus reset");
+		return err;
+	}
+
+	/*
+	 * Limit mps0 to the minimum supported by full-speed devices until the
+	 * device descriptor is read.
+	 */
+	udev->dev_desc.bMaxPacketSize0 = 8;
+	err = usbh_req_desc_dev(udev, 8, &udev->dev_desc);
+	if (err) {
+		LOG_ERR("Failed to read device descriptor");
+		goto error;
+	}
+
+	err = validate_device_mps0(udev);
+	if (err) {
+		goto error;
+	}
+
+	err = usbh_req_desc_dev(udev, sizeof(udev->dev_desc), &udev->dev_desc);
+	if (err) {
+		LOG_ERR("Failed to read device descriptor");
+		goto error;
+	}
+
+	if (!udev->dev_desc.bNumConfigurations) {
+		LOG_ERR("Device has no configurations, bNumConfigurations %d",
+			udev->dev_desc.bNumConfigurations);
+		goto error;
+	}
+
+	err = alloc_device_address(udev, &new_addr);
+	if (err) {
+		LOG_ERR("Failed to allocate device address");
+		goto error;
+	}
+
+	err = usbh_req_set_address(udev, new_addr);
+	if (err) {
+		LOG_ERR("Failed to set device address");
+		udev->addr = 0;
+
+		goto error;
+	}
+
+	udev->addr = new_addr;
+	udev->state = USB_STATE_ADDRESSED;
+
+	LOG_INF("New device with address %u state %u", udev->addr, udev->state);
+
+	err = usbh_device_set_configuration(udev, 1);
+	if (err) {
+		LOG_ERR("Failed to configure new device with address %u", udev->addr);
+	}
+
+error:
+	k_mutex_unlock(&udev->mutex);
 
-	return udevs;
+	return err;
 }
diff --git a/subsys/usb/host/usbh_device.h b/subsys/usb/host/usbh_device.h
index 742c6a71803..19613bda3bf 100644
--- a/subsys/usb/host/usbh_device.h
+++ b/subsys/usb/host/usbh_device.h
@@ -11,44 +11,40 @@
 #include <zephyr/usb/usbh.h>
 #include <zephyr/drivers/usb/uhc.h>
 
-/* USB device state */
-enum usb_device_state {
-	USB_STATE_NOTCONNECTED,
-	USB_STATE_DEFAULT,
-	USB_STATE_ADDRESSED,
-	USB_STATE_CONFIGURED,
-};
-
-/* Host support view of a USB device */
-struct usb_device {
-	struct usbh_contex *ctx;
-	struct usb_device_descriptor dev_desc;
-	enum usb_device_state state;
-	uint8_t actual_cfg;
-	uint8_t addr;
-};
-
 /* Callback type to be used for e.g. synchronous requests */
 typedef int (*usbh_udev_cb_t)(struct usb_device *const udev,
 			      struct uhc_transfer *const xfer);
 
 /*
- * Get a device to work on, there will only be one for the first time
- * until we implement USB device configuration/management.
+ * This will return the first available USB device; for a single-point
+ * connection without hub support, this is the device connected directly to the
+ * host controller.
  */
 struct usb_device *usbh_device_get_any(struct usbh_contex *const ctx);
 
+struct usb_device *usbh_device_get(struct usbh_contex *const uhs_ctx, const uint8_t addr);
+
+/* Allocate/free USB device */
+struct usb_device *usbh_device_alloc(struct usbh_contex *const uhs_ctx);
+void usbh_device_free(struct usb_device *const udev);
+
+/* Reset and configure new USB device */
+int usbh_device_init(struct usb_device *const udev);
+
+/* Set USB device interface alternate */
+int usbh_device_interface_set(struct usb_device *const udev,
+			      const uint8_t iface, const uint8_t alt,
+			      const bool dry);
+
 /* Wrappers around to avoid glue UHC calls. */
 static inline struct uhc_transfer *usbh_xfer_alloc(struct usb_device *udev,
 						   const uint8_t ep,
-						   const uint8_t attrib,
-						   const uint16_t mps,
-						   const uint16_t timeout,
-						   usbh_udev_cb_t *const cb)
+						   usbh_udev_cb_t cb,
+						   void *const cb_priv)
 {
 	struct usbh_contex *const ctx = udev->ctx;
 
-	return uhc_xfer_alloc(ctx->dev, udev->addr, ep, attrib, mps, timeout, udev, cb);
+	return uhc_xfer_alloc(ctx->dev, ep, udev, cb, cb_priv);
 }
 
 static inline int usbh_xfer_buf_add(const struct usb_device *udev,
@@ -92,4 +88,12 @@ static inline int usbh_xfer_enqueue(const struct usb_device *udev,
 	return uhc_ep_enqueue(ctx->dev, xfer);
 }
 
+static inline int usbh_xfer_dequeue(const struct usb_device *udev,
+				    struct uhc_transfer *const xfer)
+{
+	struct usbh_contex *const ctx = udev->ctx;
+
+	return uhc_ep_dequeue(ctx->dev, xfer);
+}
+
 #endif /* ZEPHYR_INCLUDE_USBH_DEVICE_H */
diff --git a/subsys/usb/host/usbh_shell.c b/subsys/usb/host/usbh_shell.c
index 33b53b89aac..2832e644d08 100644
--- a/subsys/usb/host/usbh_shell.c
+++ b/subsys/usb/host/usbh_shell.c
@@ -22,7 +22,6 @@ LOG_MODULE_REGISTER(usbh_shell, CONFIG_USBH_LOG_LEVEL);
 #define FOOBAZ_VREQ_IN		0x5c
 
 USBH_CONTROLLER_DEFINE(uhs_ctx, DEVICE_DT_GET(DT_NODELABEL(zephyr_uhc0)));
-static struct usb_device *udev;
 static uint8_t vreq_test_buf[1024];
 
 static void print_dev_desc(const struct shell *sh,
@@ -57,23 +56,55 @@ static void print_cfg_desc(const struct shell *sh,
 	shell_print(sh, "bMaxPower\t\t%u mA", desc->bMaxPower * 2);
 }
 
+K_SEM_DEFINE(bulk_req_sync, 0, 1);
+
+static int bulk_req_cb(struct usb_device *const dev, struct uhc_transfer *const xfer)
+{
+	if (xfer->err == -ECONNRESET) {
+		LOG_INF("Bulk transfer canceled");
+	} else if (xfer->err) {
+		LOG_WRN("Bulk request failed, err %d", xfer->err);
+	} else {
+		LOG_INF("Bulk request finished");
+	}
+
+	usbh_xfer_buf_free(dev, xfer->buf);
+	usbh_xfer_free(dev, xfer);
+	k_sem_give(&bulk_req_sync);
+
+	return 0;
+}
+
 static int cmd_bulk(const struct shell *sh, size_t argc, char **argv)
 {
+	static struct usb_device *udev;
 	struct uhc_transfer *xfer;
 	struct net_buf *buf;
+	uint8_t addr;
 	uint8_t ep;
 	size_t len;
+	int ret;
 
-	ep = strtol(argv[1], NULL, 16);
-	len = MIN(sizeof(vreq_test_buf), strtol(argv[2], NULL, 10));
+	addr = strtol(argv[1], NULL, 10);
+	udev = usbh_device_get(&uhs_ctx, addr);
+	if (udev == NULL) {
+		shell_error(sh, "host: No USB device with address %u", addr);
+		return -ENOMEM;
+	}
+
+	ep = strtol(argv[2], NULL, 16);
+	len = MIN(sizeof(vreq_test_buf), strtol(argv[3], NULL, 10));
 
-	xfer = usbh_xfer_alloc(udev, ep, 0, 512, 10, NULL);
+	xfer = usbh_xfer_alloc(udev, ep, bulk_req_cb, NULL);
 	if (!xfer) {
+		shell_error(sh, "host: Failed to allocate transfer");
 		return -ENOMEM;
 	}
 
 	buf = usbh_xfer_buf_alloc(udev, len);
 	if (!buf) {
+		shell_error(sh, "host: Failed to allocate buffer");
+		usbh_xfer_free(udev, xfer);
 		return -ENOMEM;
 	}
 
@@ -82,7 +113,28 @@ static int cmd_bulk(const struct shell *sh, size_t argc, char **argv)
 		net_buf_add_mem(buf, vreq_test_buf, len);
 	}
 
-	return uhc_ep_enqueue(uhs_ctx.dev, xfer);
+	k_sem_reset(&bulk_req_sync);
+	ret = usbh_xfer_enqueue(udev, xfer);
+	if (ret) {
+		usbh_xfer_buf_free(udev, xfer->buf);
+		usbh_xfer_free(udev, xfer);
+		return ret;
+	}
+
+	if (k_sem_take(&bulk_req_sync, K_MSEC(1000)) != 0) {
+		shell_print(sh, "host: Bulk transfer timeout");
+		ret = usbh_xfer_dequeue(udev, xfer);
+		if (ret != 0) {
+			shell_error(sh, "host: Failed to cancel transfer");
+			return ret;
+		}
+
+		return -ETIMEDOUT;
+	}
+
+	shell_print(sh, "host: Bulk transfer finished");
+
+	return 0;
 }
 
 static int cmd_vendor_in(const struct shell *sh,
@@ -91,12 +143,21 @@ static int cmd_vendor_in(const struct shell *sh,
 	const uint8_t bmRequestType = (USB_REQTYPE_DIR_TO_HOST << 7) |
 				      (USB_REQTYPE_TYPE_VENDOR << 5);
 	const uint8_t bRequest = FOOBAZ_VREQ_IN;
+	static struct usb_device *udev;
 	const uint16_t wValue = 0x0000;
 	struct net_buf *buf;
 	uint16_t wLength;
+	uint8_t addr;
 	int ret;
 
-	wLength = MIN(sizeof(vreq_test_buf), strtol(argv[1], NULL, 10));
+	addr = strtol(argv[1], NULL, 10);
+	udev = usbh_device_get(&uhs_ctx, addr);
+	if (udev == NULL) {
+		shell_error(sh, "host: No USB device with address %u", addr);
+		return -ENOMEM;
+	}
+
+	wLength = MIN(sizeof(vreq_test_buf), strtol(argv[2], NULL, 10));
 	buf = usbh_xfer_buf_alloc(udev, wLength);
 	if (!buf) {
 		shell_print(sh, "host: Failed to allocate buffer");
@@ -119,12 +180,21 @@ static int cmd_vendor_out(const struct shell *sh,
 	const uint8_t bmRequestType = (USB_REQTYPE_DIR_TO_DEVICE << 7) |
 				      (USB_REQTYPE_TYPE_VENDOR << 5);
 	const uint8_t bRequest = FOOBAZ_VREQ_OUT;
+	static struct usb_device *udev;
 	const uint16_t wValue = 0x0000;
 	struct net_buf *buf;
 	uint16_t wLength;
+	uint8_t addr;
 	int ret;
 
-	wLength = MIN(sizeof(vreq_test_buf), strtol(argv[1], NULL, 10));
+	addr = strtol(argv[1], NULL, 10);
+	udev = usbh_device_get(&uhs_ctx, addr);
+	if (udev == NULL) {
+		shell_error(sh, "host: No USB device with address %u", addr);
+		return -ENOMEM;
+	}
+
+	wLength = MIN(sizeof(vreq_test_buf), strtol(argv[2], NULL, 10));
 	buf = usbh_xfer_buf_alloc(udev, wLength);
 	if (!buf) {
 		shell_print(sh, "host: Failed to allocate buffer");
@@ -142,9 +212,19 @@ static int cmd_desc_device(const struct shell *sh,
 			   size_t argc, char **argv)
 {
 	struct usb_device_descriptor desc;
+	static struct usb_device *udev;
+	uint8_t addr;
 	int err;
 
-	err = usbh_req_desc_dev(udev, &desc);
+	addr = strtol(argv[1], NULL, 10);
+	udev = usbh_device_get(&uhs_ctx, addr);
+	if (udev == NULL) {
+		shell_error(sh, "host: No USB device with address %u", addr);
+		return -ENOMEM;
+	}
+
+	shell_error(sh, "host: USB device with address %u", addr);
+	err = usbh_req_desc_dev(udev, sizeof(desc), &desc);
 	if (err) {
 		shell_print(sh, "host: Failed to request device descriptor");
 	} else {
@@ -158,10 +238,19 @@ static int cmd_desc_config(const struct shell *sh,
 			   size_t argc, char **argv)
 {
 	struct usb_cfg_descriptor desc;
+	static struct usb_device *udev;
+	uint8_t addr;
 	uint8_t cfg;
 	int err;
 
-	cfg = strtol(argv[1], NULL, 10);
+	addr = strtol(argv[1], NULL, 10);
+	udev = usbh_device_get(&uhs_ctx, addr);
+	if (udev == NULL) {
+		shell_error(sh, "host: No USB device with address %u", addr);
+		return -ENOMEM;
+	}
+
+	cfg = strtol(argv[2], NULL, 10);
 
 	err = usbh_req_desc_cfg(udev, cfg, sizeof(desc), &desc);
 	if (err) {
@@ -177,13 +266,22 @@ static int cmd_desc_string(const struct shell *sh,
 			   size_t argc, char **argv)
 {
 	const uint8_t type = USB_DESC_STRING;
+	static struct usb_device *udev;
 	struct net_buf *buf;
+	uint8_t addr;
 	uint8_t id;
 	uint8_t idx;
 	int err;
 
-	id = strtol(argv[1], NULL, 10);
-	idx = strtol(argv[2], NULL, 10);
+	addr = strtol(argv[1], NULL, 10);
+	udev = usbh_device_get(&uhs_ctx, addr);
+	if (udev == NULL) {
+		shell_error(sh, "host: No USB device with address %u", addr);
+		return -ENOMEM;
+	}
+
+	id = strtol(argv[2], NULL, 10);
+	idx = strtol(argv[3], NULL, 10);
 
 	buf = usbh_xfer_buf_alloc(udev, 128);
 	if (!buf) {
@@ -202,16 +300,52 @@ static int cmd_desc_string(const struct shell *sh,
 	return err;
 }
 
+static int cmd_feature_clear_halt(const struct shell *sh,
+				  size_t argc, char **argv)
+{
+	static struct usb_device *udev;
+	uint8_t addr;
+	uint8_t ep;
+	int err;
+
+	addr = strtol(argv[1], NULL, 10);
+	udev = usbh_device_get(&uhs_ctx, addr);
+	if (udev == NULL) {
+		shell_error(sh, "host: No USB device with address %u", addr);
+		return -ENOMEM;
+	}
+
+	ep = strtol(argv[2], NULL, 16);
+
+	err = usbh_req_clear_sfs_halt(udev, ep);
+	if (err) {
+		shell_error(sh, "host: Failed to clear halt feature");
+	} else {
+		shell_print(sh, "host: Device 0x%02x, ep 0x%02x halt feature cleared",
+			    udev->addr, ep);
+	}
+
+	return err;
+}
+
 static int cmd_feature_set_halt(const struct shell *sh,
 				size_t argc, char **argv)
 {
+	static struct usb_device *udev;
+	uint8_t addr;
 	uint8_t ep;
 	int err;
 
-	ep = strtol(argv[1], NULL, 16);
+	addr = strtol(argv[1], NULL, 10);
+	udev = usbh_device_get(&uhs_ctx, addr);
+	if (udev == NULL) {
+		shell_error(sh, "host: No USB device with address %u", addr);
+		return -ENOMEM;
+	}
 
-	/* TODO: add usbh_req_set_sfs_halt(&uhs_ctx, NULL, 0); */
-	err = usbh_req_set_sfs_rwup(udev);
+	ep = strtol(argv[2], NULL, 16);
+
+	err = usbh_req_set_sfs_halt(udev, ep);
 	if (err) {
 		shell_error(sh, "host: Failed to set halt feature");
 	} else {
@@ -225,8 +359,17 @@ static int cmd_feature_set_halt(const struct shell *sh,
 static int cmd_feature_clear_rwup(const struct shell *sh,
 				  size_t argc, char **argv)
 {
+	static struct usb_device *udev;
+	uint8_t addr;
 	int err;
 
+	addr = strtol(argv[1], NULL, 10);
+	udev = usbh_device_get(&uhs_ctx, addr);
+	if (udev == NULL) {
+		shell_error(sh, "host: No USB device with address %u", addr);
+		return -ENOMEM;
+	}
+
 	err = usbh_req_clear_sfs_rwup(udev);
 	if (err) {
 		shell_error(sh, "host: Failed to clear rwup feature");
@@ -240,8 +383,17 @@ static int cmd_feature_clear_rwup(const struct shell *sh,
 static int cmd_feature_set_rwup(const struct shell *sh,
 				size_t argc, char **argv)
 {
+	static struct usb_device *udev;
+	uint8_t addr;
 	int err;
 
+	addr = strtol(argv[1], NULL, 10);
+	udev = usbh_device_get(&uhs_ctx, addr);
+	if (udev == NULL) {
+		shell_error(sh, "host: No USB device with address %u", addr);
+		return -ENOMEM;
+	}
+
 	err = usbh_req_set_sfs_rwup(udev);
 	if (err) {
 		shell_error(sh, "host: Failed to set rwup feature");
@@ -255,10 +407,19 @@ static int cmd_feature_set_rwup(const struct shell *sh,
 static int cmd_feature_set_ppwr(const struct shell *sh,
 				size_t argc, char **argv)
 {
+	static struct usb_device *udev;
+	uint8_t addr;
 	uint8_t port;
 	int err;
 
-	port = strtol(argv[1], NULL, 10);
+	addr = strtol(argv[1], NULL, 10);
+	udev = usbh_device_get(&uhs_ctx, addr);
+	if (udev == NULL) {
+		shell_error(sh, "host: No USB device with address %u", addr);
+		return -ENOMEM;
+	}
+
+	port = strtol(argv[2], NULL, 10);
 
 	err = usbh_req_set_hcfs_ppwr(udev, port);
 	if (err) {
@@ -274,10 +435,19 @@ static int cmd_feature_set_ppwr(const struct shell *sh,
 static int cmd_feature_set_prst(const struct shell *sh,
 				size_t argc, char **argv)
 {
+	static struct usb_device *udev;
+	uint8_t addr;
 	uint8_t port;
 	int err;
 
-	port = strtol(argv[1], NULL, 10);
+	addr = strtol(argv[1], NULL, 10);
+	udev = usbh_device_get(&uhs_ctx, addr);
+	if (udev == NULL) {
+		shell_error(sh, "host: No USB device with address %u", addr);
+		return -ENOMEM;
+	}
+
+	port = strtol(argv[2], NULL, 10);
 
 	err = usbh_req_set_hcfs_prst(udev, port);
 	if (err) {
@@ -293,10 +463,19 @@ static int cmd_feature_set_prst(const struct shell *sh,
 static int cmd_config_set(const struct shell *sh,
 			  size_t argc, char **argv)
 {
+	static struct usb_device *udev;
+	uint8_t addr;
 	uint8_t cfg;
 	int err;
 
-	cfg = strtol(argv[1], NULL, 10);
+	addr = strtol(argv[1], NULL, 10);
+	udev = usbh_device_get(&uhs_ctx, addr);
+	if (udev == NULL) {
+		shell_error(sh, "host: No USB device with address %u", addr);
+		return -ENOMEM;
+	}
+
+	cfg = strtol(argv[2], NULL, 10);
 
 	err = usbh_req_set_cfg(udev, cfg);
 	if (err) {
@@ -312,9 +491,18 @@ static int cmd_config_set(const struct shell *sh,
 static int cmd_config_get(const struct shell *sh,
 			  size_t argc, char **argv)
 {
+	static struct usb_device *udev;
+	uint8_t addr;
 	uint8_t cfg;
 	int err;
 
+	addr = strtol(argv[1], NULL, 10);
+	udev = usbh_device_get(&uhs_ctx, addr);
+	if (udev == NULL) {
+		shell_error(sh, "host: No USB device with address %u", addr);
+		return -ENOMEM;
+	}
+
 	err = usbh_req_get_cfg(udev, &cfg);
 	if (err) {
 		shell_error(sh, "host: Failed to set configuration");
@@ -329,12 +517,21 @@ static int cmd_config_get(const struct shell *sh,
 static int cmd_device_interface(const struct shell *sh,
 				size_t argc, char **argv)
 {
+	static struct usb_device *udev;
 	uint8_t iface;
+	uint8_t addr;
 	uint8_t alt;
 	int err;
 
-	iface = strtol(argv[1], NULL, 10);
-	alt = strtol(argv[2], NULL, 10);
+	addr = strtol(argv[1], NULL, 10);
+	udev = usbh_device_get(&uhs_ctx, addr);
+	if (udev == NULL) {
+		shell_error(sh, "host: No USB device with address %u", addr);
+		return -ENOMEM;
+	}
+
+	iface = strtol(argv[2], NULL, 10);
+	alt = strtol(argv[3], NULL, 10);
 
 	err = usbh_req_set_alt(udev, iface, alt);
 	if (err) {
@@ -350,21 +547,42 @@ static int cmd_device_interface(const struct shell *sh,
 static int cmd_device_address(const struct shell *sh,
 			      size_t argc, char **argv)
 {
+	static struct usb_device *udev;
+	uint8_t new_addr;
 	uint8_t addr;
 	int err;
 
 	addr = strtol(argv[1], NULL, 10);
+	udev = usbh_device_get(&uhs_ctx, addr);
+	if (udev == NULL) {
+		shell_error(sh, "host: No USB device with address %u", addr);
+		return -ENOMEM;
+	}
 
-	err = usbh_req_set_address(udev, addr);
+	new_addr = strtol(argv[2], NULL, 10);
+
+	err = usbh_req_set_address(udev, new_addr);
 	if (err) {
 		shell_error(sh, "host: Failed to set address");
 	} else {
-		shell_print(sh, "host: New device address is 0x%02x", addr);
+		shell_print(sh, "host: New device address is %u", new_addr);
 	}
 
 	return err;
 }
 
+static int cmd_device_list(const struct shell *sh,
+			   size_t argc, char **argv)
+{
+	struct usb_device *udev;
+
+	SYS_DLIST_FOR_EACH_CONTAINER(&uhs_ctx.udevs, udev, node) {
+		shell_print(sh, "%u", udev->addr);
+	}
+
+	return 0;
+}
+
 static int cmd_bus_suspend(const struct shell *sh,
 			   size_t argc, char **argv)
 {
@@ -425,8 +643,6 @@ static int cmd_usbh_init(const struct shell *sh,
 {
 	int err;
 
-	udev = usbh_device_get_any(&uhs_ctx);
-
 	err = usbh_init(&uhs_ctx);
 	if (err == -EALREADY) {
 		shell_error(sh, "host: USB host already initialized");
@@ -470,62 +686,64 @@ static int cmd_usbh_disable(const struct shell *sh,
 }
 
 SHELL_STATIC_SUBCMD_SET_CREATE(desc_cmds,
-	SHELL_CMD_ARG(device, NULL, NULL,
-		      cmd_desc_device, 1, 0),
-	SHELL_CMD_ARG(configuration, NULL, "<index>",
-		      cmd_desc_config, 2, 0),
-	SHELL_CMD_ARG(string, NULL, "<id> <index>",
-		      cmd_desc_string, 3, 0),
+	SHELL_CMD_ARG(device, NULL, "<addr>",
+		      cmd_desc_device, 2, 0),
+	SHELL_CMD_ARG(configuration, NULL, "<addr> <index>",
+		      cmd_desc_config, 3, 0),
+	SHELL_CMD_ARG(string, NULL, "<addr> <id> <index>",
+		      cmd_desc_string, 4, 0),
 	SHELL_SUBCMD_SET_END
 );
 
 SHELL_STATIC_SUBCMD_SET_CREATE(feature_set_cmds,
-	SHELL_CMD_ARG(rwup, NULL, NULL,
-		      cmd_feature_set_rwup, 1, 0),
-	SHELL_CMD_ARG(ppwr, NULL, "<port>",
-		      cmd_feature_set_ppwr, 2, 0),
-	SHELL_CMD_ARG(prst, NULL, "<port>",
-		      cmd_feature_set_prst, 2, 0),
-	SHELL_CMD_ARG(halt, NULL, "<endpoint>",
-		      cmd_feature_set_halt, 2, 0),
+	SHELL_CMD_ARG(rwup, NULL, "<addr>",
+		      cmd_feature_set_rwup, 2, 0),
+	SHELL_CMD_ARG(ppwr, NULL, "<addr> <port>",
+		      cmd_feature_set_ppwr, 3, 0),
+	SHELL_CMD_ARG(prst, NULL, "<addr> <port>",
+		      cmd_feature_set_prst, 3, 0),
+	SHELL_CMD_ARG(halt, NULL, "<addr> <endpoint>",
+		      cmd_feature_set_halt, 3, 0),
 	SHELL_SUBCMD_SET_END
 );
 
 SHELL_STATIC_SUBCMD_SET_CREATE(feature_clear_cmds,
-	SHELL_CMD_ARG(rwup, NULL, NULL,
-		      cmd_feature_clear_rwup, 1, 0),
-	SHELL_CMD_ARG(halt, NULL, "<endpoint>",
-		      cmd_feature_set_halt, 2, 0),
+	SHELL_CMD_ARG(rwup, NULL, "<addr>",
+		      cmd_feature_clear_rwup, 2, 0),
+	SHELL_CMD_ARG(halt, NULL, "<addr> <endpoint>",
+		      cmd_feature_clear_halt, 3, 0),
 	SHELL_SUBCMD_SET_END
 );
 
 SHELL_STATIC_SUBCMD_SET_CREATE(config_cmds,
-	SHELL_CMD_ARG(get, NULL, NULL,
-		      cmd_config_get, 1, 0),
-	SHELL_CMD_ARG(set, NULL, "<configuration>",
-		      cmd_config_set, 2, 0),
+	SHELL_CMD_ARG(get, NULL, "<addr>",
+		      cmd_config_get, 2, 0),
+	SHELL_CMD_ARG(set, NULL, "<addr> <configuration>",
+		      cmd_config_set, 3, 0),
 	SHELL_SUBCMD_SET_END
 );
 
 SHELL_STATIC_SUBCMD_SET_CREATE(device_cmds,
-	SHELL_CMD_ARG(address, NULL, "<address>",
-		      cmd_device_address, 2, 0),
+	SHELL_CMD_ARG(list, NULL, NULL,
+		      cmd_device_list, 1, 0),
+	SHELL_CMD_ARG(address, NULL, "<address> <new address>",
+		      cmd_device_address, 3, 0),
 	SHELL_CMD_ARG(config, &config_cmds, "get|set configuration",
-		      NULL, 1, 0),
-	SHELL_CMD_ARG(interface, NULL, "<interface> <alternate>",
-		      cmd_device_interface, 3, 0),
+		      NULL, 2, 0),
+	SHELL_CMD_ARG(interface, NULL, "<address> <interface> <alternate>",
+		      cmd_device_interface, 4, 0),
 	SHELL_CMD_ARG(descriptor, &desc_cmds, "descriptor request",
-		      NULL, 1, 0),
+		      NULL, 2, 0),
 	SHELL_CMD_ARG(feature-set, &feature_set_cmds, "feature selector",
-		      NULL, 1, 0),
+		      NULL, 2, 0),
 	SHELL_CMD_ARG(feature-clear, &feature_clear_cmds, "feature selector",
-		      NULL, 1, 0),
-	SHELL_CMD_ARG(vendor_in, NULL, "<length>",
-		      cmd_vendor_in, 2, 0),
-	SHELL_CMD_ARG(vendor_out, NULL, "<length>",
-		      cmd_vendor_out, 2, 0),
-	SHELL_CMD_ARG(bulk, NULL, "<endpoint> <length>",
-		      cmd_bulk, 3, 0),
+		      NULL, 2, 0),
+	SHELL_CMD_ARG(vendor_in, NULL, "<address> <length>",
+		      cmd_vendor_in, 3, 0),
+	SHELL_CMD_ARG(vendor_out, NULL, "<address> <length>",
+		      cmd_vendor_out, 3, 0),
+	SHELL_CMD_ARG(bulk, NULL, "<address> <endpoint> <length>",
+		      cmd_bulk, 4, 0),
 	SHELL_SUBCMD_SET_END
 );
 
diff --git a/subsys/usb/host/usbip.c b/subsys/usb/host/usbip.c
new file mode 100644
index 00000000000..773acbb55d3
--- /dev/null
+++ b/subsys/usb/host/usbip.c
@@ -0,0 +1,748 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include <stdio.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/usb/usb_ch9.h>
+#include <zephyr/usb/usbh.h>
+#include <zephyr/net/socket.h>
+#include <zephyr/net_buf.h>
+
+#include <usbh_device.h>
+#include <usbh_ch9.h>
+#include <usbip.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(usbip, CONFIG_USBIP_LOG_LEVEL);
+
+/* For now, we will use the Zephyr default controller. */
+USBH_CONTROLLER_DEFINE(usbip_uhs_ctx, DEVICE_DT_GET(DT_NODELABEL(zephyr_uhc0)));
+
+#define USBIP_MAX_PKT_SIZE	2048
+NET_BUF_POOL_DEFINE(usbip_pool, 32, USBIP_MAX_PKT_SIZE, 0, NULL);
+
+K_THREAD_STACK_DEFINE(usbip_thread_stack, CONFIG_USBIP_THREAD_STACK_SIZE);
+K_THREAD_STACK_ARRAY_DEFINE(dev_thread_stacks, CONFIG_USBIP_DEVICES_COUNT,
+			    CONFIG_USBIP_THREAD_STACK_SIZE);
+
+static struct k_thread usbip_thread;
+
+#define USBIP_DEFAULT_PATH	"/sys/bus/usb/devices/usb1/1-"
+
+#define USBIP_EXPORTED		BIT(0)
+
+/* Context of the exported device */
+struct usbip_dev_ctx {
+	struct usb_device *udev;
+	struct k_thread thread;
+	struct k_event event;
+	sys_dlist_t dlist;
+	int connfd;
+	uint32_t devid;
+};
+
+/* Context of the exported bus (not really used yet) */
+struct usbip_bus_ctx {
+	struct usbh_contex *uhs_ctx;
+	struct usbip_dev_ctx devs[CONFIG_USBIP_DEVICES_COUNT];
+	uint8_t busnum;
+};
+
+static struct usbip_bus_ctx default_bus_ctx;
+
+/* Command reference structure to find the way back */
+struct usbip_cmd_node {
+	sys_dnode_t node;
+	struct usbip_command cmd;
+	struct usbip_dev_ctx *ctx;
+	struct uhc_transfer *xfer;
+};
+
+K_MEM_SLAB_DEFINE(usbip_slab, sizeof(struct usbip_cmd_node),
+		  CONFIG_USBIP_SUBMIT_BACKLOG_COUNT, sizeof(void *));
+
+static void usbip_ntoh_command(struct usbip_command *const cmd)
+{
+	cmd->hdr.command = ntohl(cmd->hdr.command);
+	cmd->hdr.seqnum = ntohl(cmd->hdr.seqnum);
+	cmd->hdr.devid = ntohl(cmd->hdr.devid);
+	cmd->hdr.direction = ntohl(cmd->hdr.direction);
+	cmd->hdr.ep = ntohl(cmd->hdr.ep);
+
+	if (cmd->hdr.command == USBIP_CMD_SUBMIT) {
+		cmd->submit.flags = ntohl(cmd->submit.flags);
+		cmd->submit.length = ntohl(cmd->submit.length);
+		cmd->submit.start_frame = ntohl(cmd->submit.start_frame);
+		cmd->submit.numof_iso_pkts = ntohl(cmd->submit.numof_iso_pkts);
+		cmd->submit.interval = ntohl(cmd->submit.interval);
+	} else {
+		cmd->unlink.seqnum = ntohl(cmd->unlink.seqnum);
+	}
+}
+
+static void check_ctrl_request(struct usb_device *const udev,
+			       const int ep, const uint8_t *const setup_pkt)
+{
+	struct usb_setup_packet setup = {0};
+
+	memcpy(&setup, setup_pkt, sizeof(struct usb_setup_packet));
+	if (setup.RequestType.type != USB_REQTYPE_TYPE_STANDARD) {
+		return;
+	}
+
+	if (setup.RequestType.direction) {
+		return;
+	}
+
+	switch (setup.bRequest) {
+	case USB_SREQ_SET_ADDRESS:
+		LOG_INF("Set Address");
+		break;
+	case USB_SREQ_SET_CONFIGURATION:
+		LOG_INF("Set Configuration");
+		break;
+	case USB_SREQ_SET_INTERFACE:
+		LOG_INF("Set Interface");
+		if (usbh_device_interface_set(udev, setup.wIndex, setup.wValue, true)) {
+			LOG_ERR("Failed to apply Set Interface request");
+		}
+		break;
+	default:
+		break;
+	}
+}
+
+static int usbip_req_cb(struct usb_device *const udev, struct uhc_transfer *const xfer)
+{
+	struct usbip_cmd_node *const cmd_nd = xfer->priv;
+	struct usbip_dev_ctx *const dev_ctx = cmd_nd->ctx;
+	struct usbip_command *const cmd = &cmd_nd->cmd;
+	struct net_buf *buf = xfer->buf;
+	struct usbip_return ret;
+	unsigned int key;
+	int err;
+
+	LOG_INF("SUBMIT seqnum %u finished err %d ep 0x%02x",
+		cmd->hdr.seqnum, xfer->err, xfer->ep);
+
+	ret.hdr.command = htonl(USBIP_RET_SUBMIT);
+	ret.hdr.seqnum = htonl(cmd->hdr.seqnum);
+	ret.hdr.devid = htonl(cmd->hdr.devid);
+	ret.hdr.ep = htonl(xfer->ep);
+	ret.hdr.direction = htonl(cmd->hdr.direction);
+
+	memset(&ret.submit, 0, sizeof(ret.submit));
+	ret.submit.status = htonl(xfer->err);
+	ret.submit.start_frame = htonl(cmd->submit.start_frame);
+	ret.submit.numof_iso_pkts = htonl(0xFFFFFFFFUL);
+
+	if (xfer->err == -ECONNRESET) {
+		LOG_INF("URB seqnum %u unlinked (ECONNRESET)", cmd->hdr.seqnum);
+		goto usbip_req_cb_error;
+	}
+
+	if (xfer->err == -EPIPE) {
+		LOG_INF("RET_SUBMIT status is EPIPE");
+	}
+
+	if (xfer->err == 0 && cmd->submit.length != 0) {
+		ret.submit.actual_length = htonl(buf->len);
+	}
+
+
+	if (USB_EP_GET_IDX(xfer->ep) == 0U) {
+		check_ctrl_request(dev_ctx->udev, xfer->ep, xfer->setup_pkt);
+	}
+
+	err = zsock_send(dev_ctx->connfd, &ret, sizeof(ret), 0);
+	if (err != sizeof(ret)) {
+		LOG_ERR("Send RET_SUBMIT failed err %d errno %d", err, errno);
+		err = -errno;
+		goto usbip_req_cb_error;
+	}
+
+	if (ret.submit.actual_length != 0) {
+		LOG_INF("Send RET_SUBMIT transfer_buffer len %u", buf->len);
+		err = zsock_send(dev_ctx->connfd, buf->data, buf->len, 0);
+		if (err != buf->len) {
+			LOG_ERR("Send transfer_buffer failed err %d errno %d",
+				err, errno);
+			err = -errno;
+			goto usbip_req_cb_error;
+		}
+	}
+
+usbip_req_cb_error:
+	key = irq_lock();
+	sys_dlist_remove(&cmd_nd->node);
+	irq_unlock(key);
+
+	k_mem_slab_free(&usbip_slab, (void *)cmd_nd);
+	if (xfer->buf) {
+		net_buf_unref(buf);
+	}
+
+	usbh_xfer_free(dev_ctx->udev, xfer);
+
+	return 0;
+}
+
+static int usbip_submit_req(struct usbip_cmd_node *const cmd_nd, const uint8_t ep,
+			    const struct usb_setup_packet *const setup,
+			    struct net_buf *const buf)
+{
+	struct usbip_dev_ctx *const dev_ctx = cmd_nd->ctx;
+	struct usbip_command *const cmd = &cmd_nd->cmd;
+	struct usb_device *const udev = dev_ctx->udev;
+	struct uhc_transfer *xfer;
+	int ret;
+
+	xfer = usbh_xfer_alloc(udev, ep, usbip_req_cb, cmd_nd);
+	if (xfer == NULL) {
+		return -ENOMEM;
+	}
+
+	if (setup != NULL) {
+		memcpy(xfer->setup_pkt, setup, sizeof(struct usb_setup_packet));
+		LOG_HEXDUMP_DBG(xfer->setup_pkt, 8U, "setup");
+	}
+
+	if (buf != NULL) {
+		ret = usbh_xfer_buf_add(dev_ctx->udev, xfer, buf);
+		if (ret) {
+			goto submit_req_err;
+		}
+	}
+
+	xfer->interval = cmd->submit.interval;
+	cmd_nd->xfer = xfer;
+	ret = usbh_xfer_enqueue(dev_ctx->udev, xfer);
+	if (ret) {
+		goto submit_req_err;
+	}
+
+	return 0;
+
+submit_req_err:
+	usbh_xfer_free(dev_ctx->udev, xfer);
+
+	return ret;
+}
+
+static int usbip_handle_submit(struct usbip_dev_ctx *const dev_ctx,
+			       struct usbip_command *const cmd)
+{
+	struct usbip_cmd_submit *submit = &cmd->submit;
+	struct usb_setup_packet setup = {0};
+	struct usbip_cmd_node *cmd_nd;
+	struct net_buf *buf = NULL;
+	uint8_t ep;
+	int ret;
+
+	ret = zsock_recv(dev_ctx->connfd, submit, sizeof(*submit), ZSOCK_MSG_WAITALL);
+	if (ret <= 0) {
+		return ret == 0 ? -ENOTCONN : -errno;
+	}
+
+	usbip_ntoh_command(cmd);
+
+	ep = cmd->hdr.ep;
+	if (cmd->submit.length != 0) {
+		buf = net_buf_alloc(&usbip_pool, K_NO_WAIT);
+		if (buf == NULL) {
+			LOG_ERR("Failed to allocate net_buf");
+			return -ENOMEM;
+		}
+	}
+
+	if (cmd->hdr.direction == USBIP_DIR_OUT && cmd->submit.length != 0) {
+		/* Receive data */
+		ret = zsock_recv(dev_ctx->connfd,
+				 buf->data, cmd->submit.length,
+				 ZSOCK_MSG_WAITALL);
+		if (ret <= 0) {
+			net_buf_unref(buf);
+			return ret == 0 ? -ENOTCONN : -errno;
+		}
+
+		net_buf_add(buf, cmd->submit.length);
+	}
+
+	if (USB_EP_GET_IDX(ep) == 0U) {
+		/* Setup packet */
+		memcpy(&setup, cmd->submit.setup, sizeof(setup));
+		ep = usb_reqtype_is_to_device(&setup) ? 0x00 : 0x80;
+	} else {
+		/* Set endpoint depending on direction */
+		if (cmd->hdr.direction == USBIP_DIR_IN) {
+			ep |= USB_EP_DIR_IN;
+		}
+	}
+
+	LOG_INF("Handle SUBMIT devid %x seqnum %u length %u ep 0x%02x flags 0x%08x",
+		cmd->hdr.devid, cmd->hdr.seqnum, cmd->submit.length, ep, cmd->submit.flags);
+
+	if (k_mem_slab_alloc(&usbip_slab, (void **)&cmd_nd, K_MSEC(1000)) != 0) {
+		LOG_ERR("Failed to allocate slab");
+		net_buf_unref(buf);
+		return -ENOMEM;
+	}
+
+	/* Make a copy of the command and add it to the backlog */
+	memcpy(&cmd_nd->cmd, cmd, sizeof(struct usbip_command));
+	cmd_nd->ctx = dev_ctx;
+	sys_dlist_append(&dev_ctx->dlist, &cmd_nd->node);
+
+	ret = usbip_submit_req(cmd_nd, ep, &setup, buf);
+	if (ret != 0) {
+		LOG_ERR("Failed to submit request %d", ret);
+		return ret;
+	}
+
+	LOG_INF("Append %u ep 0x%02x to list", cmd->hdr.seqnum, ep);
+	if (cmd->submit.length != 0) {
+		LOG_HEXDUMP_DBG(buf->data, buf->len, "SUBMIT data");
+	}
+
+	return 0;
+}
+
+static int usbip_handle_unlink(struct usbip_dev_ctx *const dev_ctx,
+			       struct usbip_command *const cmd)
+{
+	struct usbip_cmd_unlink *unlink = &cmd->unlink;
+	struct usbip_return rsp;
+	struct usbip_cmd_node *cmd_nd;
+	unsigned int key;
+	int ret;
+
+	ret = zsock_recv(dev_ctx->connfd, unlink, sizeof(*unlink), ZSOCK_MSG_WAITALL);
+	if (ret <= 0) {
+		return ret == 0 ? -ENOTCONN : -errno;
+	}
+
+	memcpy(&rsp.hdr, &cmd->hdr, sizeof(rsp.hdr));
+	rsp.hdr.command = htonl(USBIP_RET_UNLINK);
+
+	usbip_ntoh_command(cmd);
+
+	LOG_INF("Unlink request (seqnum %u) seqnum %u",
+		cmd->hdr.seqnum, cmd->unlink.seqnum);
+
+	memset(&rsp.unlink, 0, sizeof(rsp.unlink));
+
+	key = irq_lock();
+	SYS_DLIST_FOR_EACH_CONTAINER(&dev_ctx->dlist, cmd_nd, node) {
+		if (cmd_nd->cmd.hdr.seqnum == cmd->unlink.seqnum) {
+			rsp.unlink.status = htonl(-ECONNRESET);
+			usbh_xfer_dequeue(dev_ctx->udev, cmd_nd->xfer);
+			break;
+		}
+	}
+	irq_unlock(key);
+
+	ret = zsock_send(dev_ctx->connfd, &rsp, sizeof(rsp), 0);
+	if (ret != sizeof(rsp)) {
+		return -errno;
+	}
+
+	return 0;
+}
+
+static int usbip_handle_cmd(struct usbip_dev_ctx *const dev_ctx)
+{
+	struct usbip_command cmd;
+	int ret;
+
+	ret = zsock_recv(dev_ctx->connfd, &cmd.hdr, sizeof(cmd.hdr), ZSOCK_MSG_WAITALL);
+	if (ret <= 0) {
+		return ret == 0 ? -ENOTCONN : -errno;
+	}
+
+	LOG_HEXDUMP_DBG((uint8_t *)&cmd.hdr, sizeof(cmd.hdr), "cmd.hdr");
+
+	switch (ntohl(cmd.hdr.command)) {
+	case USBIP_CMD_SUBMIT:
+		ret = usbip_handle_submit(dev_ctx, &cmd);
+		break;
+	case USBIP_CMD_UNLINK:
+		ret = usbip_handle_unlink(dev_ctx, &cmd);
+		break;
+	default:
+		LOG_ERR("Unknown command: 0x%x", ntohl(cmd.hdr.command));
+		break;
+	}
+
+	return ret;
+}
+
+static void usbip_thread_cmd(void *const a, void *const b, void *const c)
+{
+	struct usbip_dev_ctx *dev_ctx = a;
+	int ret;
+
+	LOG_INF("CMD thread started");
+	while (true) {
+		k_event_wait(&dev_ctx->event, USBIP_EXPORTED, false, K_FOREVER);
+
+		ret = usbip_handle_cmd(dev_ctx);
+
+		if (ret) {
+			zsock_close(dev_ctx->connfd);
+			LOG_INF("CMD connection closed, errno %d", ret);
+			k_event_set_masked(&dev_ctx->event, 0, USBIP_EXPORTED);
+			dev_ctx->udev = NULL;
+		}
+	}
+}
+
+static int handle_devlist_device(struct usb_device *const udev,
+				 const uint32_t busnum, int connfd)
+{
+	struct usb_device_descriptor *d_desc = &udev->dev_desc;
+	struct usb_cfg_descriptor *c_desc = udev->cfg_desc;
+	static struct usbip_devlist_data devlist;
+	const uint32_t devnum = udev->addr;
+	int err;
+
+	devlist.busnum = htonl(busnum);
+	devlist.devnum = htonl(devnum);
+
+	devlist.speed = htonl(udev->speed);
+	devlist.idVendor = htons(d_desc->idVendor);
+	devlist.idProduct = htons(d_desc->idProduct);
+	devlist.bcdDevice = htons(d_desc->bcdDevice);
+	devlist.bDeviceClass = d_desc->bDeviceClass;
+	devlist.bDeviceSubClass = d_desc->bDeviceSubClass;
+	devlist.bDeviceProtocol = d_desc->bDeviceProtocol;
+
+	devlist.bConfigurationValue = c_desc->bConfigurationValue;
+	devlist.bNumConfigurations = d_desc->bNumConfigurations;
+	devlist.bNumInterfaces = c_desc->bNumInterfaces;
+
+	snprintf(devlist.path, sizeof(devlist.path), USBIP_DEFAULT_PATH "%d", devnum);
+	snprintf(devlist.busid, sizeof(devlist.busid), "1-%d", devnum);
+
+	LOG_INF("bLength\t\t\t%u", c_desc->bLength);
+	LOG_INF("bDescriptorType\t\t%u", c_desc->bDescriptorType);
+	LOG_INF("wTotalLength\t\t%u", c_desc->wTotalLength);
+	LOG_INF("bNumInterfaces\t\t%u", c_desc->bNumInterfaces);
+	LOG_INF("bConfigurationValue\t%u", c_desc->bConfigurationValue);
+	LOG_INF("iConfiguration\t\t%u", c_desc->iConfiguration);
+	LOG_INF("bmAttributes\t\t%02x", c_desc->bmAttributes);
+	LOG_INF("bMaxPower\t\t%u mA", c_desc->bMaxPower * 2);
+
+	err = zsock_send(connfd, &devlist, sizeof(devlist), 0);
+	if (err != sizeof(devlist)) {
+		return -errno;
+	}
+
+	return 0;
+}
+
+static int handle_devlist_device_iface(struct usb_device *const udev, int connfd)
+{
+	struct usb_cfg_descriptor *c_desc = udev->cfg_desc;
+	static struct usbip_devlist_iface_data iface;
+	int err;
+
+	LOG_INF("Handle OP_REQ_DEVLIST, bNumInterfaces %u wTotalLength %u",
+		c_desc->bNumInterfaces, c_desc->wTotalLength);
+
+	for (unsigned int i = 0; i < c_desc->bNumInterfaces; i++) {
+		struct usb_if_descriptor *if_d = (void *)udev->ifaces[i].dhp;
+
+		LOG_DBG("bInterfaceNumber %u", if_d->bInterfaceNumber);
+
+		iface.bInterfaceClass = if_d->bInterfaceClass;
+		iface.bInterfaceSubClass = if_d->bInterfaceSubClass;
+		iface.bInterfaceProtocol = if_d->bInterfaceProtocol;
+		iface.padding = 0U;
+
+		err = zsock_send(connfd, &iface, sizeof(iface), 0);
+		if (err != sizeof(iface)) {
+			LOG_ERR("Failed to send interface info %d", err);
+			return -errno;
+		}
+	}
+
+	return 0;
+}
+
+static int usbip_handle_devlist(struct usbip_bus_ctx *const bus_ctx, int connfd)
+{
+	struct usbip_devlist_header rep_hdr = {
+		.version = htons(USBIP_VERSION),
+		.code = htons(USBIP_OP_REP_DEVLIST),
+		.status = 0,
+		.ndev = htonl(1),
+	};
+	struct usb_device *udev;
+	uint32_t ndev = 0;
+	int err;
+
+	SYS_DLIST_FOR_EACH_CONTAINER(&bus_ctx->uhs_ctx->udevs, udev, node) {
+		ndev++;
+	}
+
+	rep_hdr.ndev = htonl(ndev);
+	/* Send reply header with the number of USB devices  */
+	err = zsock_send(connfd, &rep_hdr, sizeof(rep_hdr), 0);
+	if (err != sizeof(rep_hdr)) {
+		return -errno;
+	}
+
+	/* Send device info for each USB devices */
+	SYS_DLIST_FOR_EACH_CONTAINER(&bus_ctx->uhs_ctx->udevs, udev, node) {
+		err = handle_devlist_device(udev, bus_ctx->busnum, connfd);
+		if (err) {
+			return err;
+		}
+
+		err = handle_devlist_device_iface(udev, connfd);
+		if (err) {
+			return err;
+		}
+	}
+
+	return 0;
+}
+
+static struct usb_device *get_device_by_busid(struct usbip_bus_ctx *const bus_ctx,
+					      const char busid[static 32])
+{
+	struct usb_device *udev;
+	char my_busid[32];
+
+	LOG_HEXDUMP_DBG(busid, sizeof(my_busid), "import busid");
+
+	SYS_DLIST_FOR_EACH_CONTAINER(&bus_ctx->uhs_ctx->udevs, udev, node) {
+		snprintf(my_busid, sizeof(my_busid), "1-%d", udev->addr);
+
+		LOG_HEXDUMP_DBG(my_busid, sizeof(my_busid), "my busid");
+		if (!strncmp(busid, my_busid, sizeof(my_busid))) {
+			return udev;
+		}
+	}
+
+	return NULL;
+}
+
+static struct usbip_dev_ctx *get_free_dev_ctx(struct usbip_bus_ctx *const bus_ctx)
+{
+	for (unsigned int i = 0; i < CONFIG_USBIP_DEVICES_COUNT; i++) {
+		struct usbip_dev_ctx *const dev_ctx = &bus_ctx->devs[i];
+
+		if (k_event_wait(&dev_ctx->event, USBIP_EXPORTED, false, K_NO_WAIT)) {
+			continue;
+		}
+
+		if (dev_ctx->udev != NULL) {
+			LOG_WRN("USB device pointer is not cleaned");
+		}
+
+		return &bus_ctx->devs[i];
+	}
+
+	return NULL;
+}
+
+static int usbip_handle_import(struct usbip_bus_ctx *const bus_ctx, int connfd)
+{
+	struct usbip_req_header rep_hdr = {
+		.version = htons(USBIP_VERSION),
+		.code = htons(USBIP_OP_REP_IMPORT),
+		.status = 0,
+	};
+	struct usbip_dev_ctx *dev_ctx;
+	uint8_t busid[32];
+	int ret;
+
+	ret = zsock_recv(connfd, &busid, sizeof(busid), ZSOCK_MSG_WAITALL);
+	if (ret <= 0) {
+		return ret == 0 ? -ENOTCONN : -errno;
+	}
+
+	dev_ctx = get_free_dev_ctx(bus_ctx);
+	if (dev_ctx == NULL) {
+		rep_hdr.status = htonl(-1);
+		LOG_ERR("No free device context to export a device");
+	} else {
+		dev_ctx->udev = get_device_by_busid(bus_ctx, busid);
+		if (dev_ctx->udev == NULL) {
+			rep_hdr.status = htonl(-1);
+			dev_ctx = NULL;
+			LOG_ERR("No USB device with busid %s", busid);
+		}
+	}
+
+	ret = zsock_send(connfd, &rep_hdr, sizeof(rep_hdr), 0);
+	if (ret != sizeof(rep_hdr)) {
+		return -errno;
+	}
+
+	if (rep_hdr.status || dev_ctx == NULL) {
+		LOG_ERR("Device does not exits or cannot be exported");
+		return -1;
+	}
+
+	ret = handle_devlist_device(dev_ctx->udev, bus_ctx->busnum, connfd);
+	if (ret) {
+		return ret;
+	}
+
+	dev_ctx->connfd = connfd;
+	k_event_post(&dev_ctx->event, USBIP_EXPORTED);
+	LOG_INF("USB device %s exported", busid);
+
+	return 0;
+}
+
+static int usbip_handle_connection(struct usbip_bus_ctx *const bus_ctx, int connfd)
+{
+	struct usbip_req_header hdr;
+	int ret;
+
+	ret = zsock_recv(connfd, &hdr, sizeof(hdr), ZSOCK_MSG_WAITALL);
+	if (ret <= 0) {
+		return ret == 0 ? -ENOTCONN : -errno;
+	}
+
+	LOG_HEXDUMP_DBG((uint8_t *)&hdr, sizeof(hdr), "header");
+	LOG_INF("Code: 0x%x", ntohs(hdr.code));
+
+	switch (ntohs(hdr.code)) {
+	case USBIP_OP_REQ_DEVLIST:
+		ret = usbip_handle_devlist(bus_ctx, connfd);
+		zsock_close(connfd);
+		break;
+	case USBIP_OP_REQ_IMPORT:
+		ret = usbip_handle_import(bus_ctx, connfd);
+		if (ret) {
+			zsock_close(connfd);
+		}
+		break;
+	default:
+		LOG_ERR("Unknown request: 0x%x", ntohs(hdr.code));
+		ret = -1;
+		break;
+	}
+
+	return ret;
+}
+
+static void usbip_thread_handler(void *const a, void *const b, void *const c)
+{
+	struct usbip_bus_ctx *const bus_ctx = a;
+	struct sockaddr_in srv;
+	int listenfd;
+	int connfd;
+	int reuse = 1;
+
+	LOG_DBG("Started connection handling thread");
+
+	listenfd = zsock_socket(AF_INET, SOCK_STREAM, IPPROTO_TCP);
+	if (listenfd < 0) {
+		LOG_ERR("socket() failed: %s", strerror(errno));
+		return;
+	}
+
+	if (zsock_setsockopt(listenfd, SOL_SOCKET, SO_REUSEADDR,
+			     (const char *)&reuse, sizeof(reuse)) < 0) {
+		LOG_INF("setsockopt() failed: %s", strerror(errno));
+	}
+
+	srv.sin_family = AF_INET;
+	srv.sin_addr.s_addr = htonl(INADDR_ANY);
+	srv.sin_port = htons(USBIP_PORT);
+
+	if (zsock_bind(listenfd, (struct sockaddr *)&srv, sizeof(srv)) < 0) {
+		LOG_ERR("bind() failed: %s", strerror(errno));
+		return;
+	}
+
+	if (zsock_listen(listenfd, 1) < 0) {
+		LOG_ERR("listen() failed: %s", strerror(errno));
+		return;
+	}
+
+	while (true) {
+		struct sockaddr_in client_addr;
+		socklen_t client_addr_len = sizeof(client_addr);
+		char addr_str[INET_ADDRSTRLEN];
+		int err;
+
+		connfd = zsock_accept(listenfd, (struct sockaddr *)&client_addr,
+				      &client_addr_len);
+		if (connfd < 0) {
+			LOG_ERR("accept() failed: %d", errno);
+			continue;
+		}
+
+		zsock_inet_ntop(client_addr.sin_family, &client_addr.sin_addr,
+				addr_str, sizeof(addr_str));
+		LOG_INF("Connection: %s", addr_str);
+
+		err = usbip_handle_connection(bus_ctx, connfd);
+		LOG_INF("Connection from %s closed, errno %d", addr_str, err);
+	}
+}
+
+/*
+ * We are just using a standard host controller, which is fine to get USBIP
+ * support working and stable, but it needs a better solution in the future.
+ */
+static int usbip_init(void)
+{
+	struct usbip_bus_ctx *const bus_ctx = &default_bus_ctx;
+	int err;
+
+	err = usbh_init(&usbip_uhs_ctx);
+	if (err) {
+		LOG_ERR("Failed to initialize host support");
+		return err;
+	}
+
+	err = usbh_enable(&usbip_uhs_ctx);
+	if (err) {
+		LOG_ERR("Failed to enable host support");
+		return err;
+	}
+
+	err = uhc_sof_enable(usbip_uhs_ctx.dev);
+	if (err) {
+		LOG_ERR("Failed to start SoF");
+		return err;
+	}
+
+	LOG_INF("Host controller enabled");
+	bus_ctx->uhs_ctx = &usbip_uhs_ctx;
+	bus_ctx->busnum = 1;
+
+	for (int i = 0; i < CONFIG_USBIP_DEVICES_COUNT; i++) {
+		struct usbip_dev_ctx *ctx = &bus_ctx->devs[i];
+
+		/* busnum << 16 | devnum */
+		ctx->devid = (1U << 16) | i;
+		sys_dlist_init(&ctx->dlist);
+		k_event_init(&ctx->event);
+		k_thread_create(&ctx->thread, dev_thread_stacks[i],
+				K_THREAD_STACK_SIZEOF(dev_thread_stacks[i]),
+				usbip_thread_cmd, ctx, NULL, NULL,
+				K_PRIO_COOP(3), 0, K_NO_WAIT);
+	}
+
+	k_thread_create(&usbip_thread, usbip_thread_stack,
+			K_THREAD_STACK_SIZEOF(usbip_thread_stack),
+			usbip_thread_handler, bus_ctx, NULL, NULL,
+			K_PRIO_COOP(2), 0, K_NO_WAIT);
+
+	return 0;
+}
+
+SYS_INIT(usbip_init, APPLICATION, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
diff --git a/subsys/usb/host/usbip.h b/subsys/usb/host/usbip.h
new file mode 100644
index 00000000000..5334b3f4691
--- /dev/null
+++ b/subsys/usb/host/usbip.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2021 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#define USBIP_PORT		3240
+#define USBIP_VERSION		0x0111U
+
+/* Retrieve the list of exported devices command code */
+#define USBIP_OP_REQ_DEVLIST	0x8005U
+/* Reply the list of exported devices command code */
+#define USBIP_OP_REP_DEVLIST	0x0005U
+/* Request to import a remote device command code */
+#define USBIP_OP_REQ_IMPORT	0x8003U
+/* Reply to import a remote device command code */
+#define USBIP_OP_REP_IMPORT	0x0003U
+
+/* Submit an URB command code */
+#define USBIP_CMD_SUBMIT	0x0001UL
+/* Reply for submitting an URB command code */
+#define USBIP_RET_SUBMIT	0x0003UL
+/* Unlink an URB command code */
+#define USBIP_CMD_UNLINK	0x0002UL
+/* Reply for unlink an URB command code */
+#define USBIP_RET_UNLINK	0x0004UL
+
+/* Command direction */
+#define USBIP_DIR_OUT		0UL
+#define USBIP_DIR_IN		1UL
+
+struct usbip_req_header {
+	uint16_t version;
+	uint16_t code;
+	uint32_t status;
+} __packed;
+
+struct usbip_devlist_header {
+	uint16_t version;
+	uint16_t code;
+	uint32_t status;
+	uint32_t ndev;
+} __packed;
+
+struct usbip_devlist_data {
+	char path[256];
+	char busid[32];
+
+	uint32_t busnum;
+	uint32_t devnum;
+	uint32_t speed;
+
+	uint16_t idVendor;
+	uint16_t idProduct;
+	uint16_t bcdDevice;
+
+	uint8_t bDeviceClass;
+	uint8_t bDeviceSubClass;
+	uint8_t bDeviceProtocol;
+	uint8_t bConfigurationValue;
+	uint8_t bNumConfigurations;
+	uint8_t bNumInterfaces;
+} __packed;
+
+struct usbip_devlist_iface_data {
+	uint8_t bInterfaceClass;
+	uint8_t bInterfaceSubClass;
+	uint8_t bInterfaceProtocol;
+	uint8_t padding;
+} __packed;
+
+struct usbip_cmd_header {
+	uint32_t command;
+	uint32_t seqnum;
+	uint32_t devid;
+	uint32_t direction;
+	uint32_t ep;
+} __packed;
+
+struct usbip_cmd_submit {
+	uint32_t flags;
+	uint32_t length;
+	int32_t start_frame;
+	int32_t numof_iso_pkts;
+	int32_t interval;
+	uint8_t setup[8];
+} __packed;
+
+struct usbip_cmd_unlink {
+	uint32_t seqnum;
+	uint32_t padding[6];
+} __packed;
+
+struct usbip_command {
+	struct usbip_cmd_header hdr;
+
+	union {
+		struct usbip_cmd_submit submit;
+		struct usbip_cmd_unlink unlink;
+	};
+} __packed;
+
+struct usbip_ret_submit {
+	int32_t status;
+	uint32_t actual_length;
+	int32_t start_frame;
+	int32_t numof_iso_pkts;
+	int32_t error_count;
+	uint64_t setup;
+} __packed;
+
+struct usbip_ret_unlink {
+	int32_t status;
+	uint32_t padding[6];
+} __packed;
+
+struct usbip_return {
+	struct usbip_cmd_header hdr;
+
+	union {
+		struct usbip_ret_submit submit;
+		struct usbip_ret_unlink unlink;
+	};
+} __packed;
diff --git a/subsys/zbus/zbus.c b/subsys/zbus/zbus.c
index e4defffbc57..0fff534c248 100644
--- a/subsys/zbus/zbus.c
+++ b/subsys/zbus/zbus.c
@@ -380,6 +380,8 @@ int zbus_chan_pub(const struct zbus_channel *chan, const void *msg, k_timeout_t
 
 	_ZBUS_ASSERT(chan != NULL, "chan is required");
 	_ZBUS_ASSERT(msg != NULL, "msg is required");
+	_ZBUS_ASSERT(k_is_in_isr() ? K_TIMEOUT_EQ(timeout, K_NO_WAIT) : true,
+		     "inside an ISR, the timeout must be K_NO_WAIT");
 
 	if (k_is_in_isr()) {
 		timeout = K_NO_WAIT;
@@ -416,6 +418,8 @@ int zbus_chan_read(const struct zbus_channel *chan, void *msg, k_timeout_t timeo
 {
 	_ZBUS_ASSERT(chan != NULL, "chan is required");
 	_ZBUS_ASSERT(msg != NULL, "msg is required");
+	_ZBUS_ASSERT(k_is_in_isr() ? K_TIMEOUT_EQ(timeout, K_NO_WAIT) : true,
+		     "inside an ISR, the timeout must be K_NO_WAIT");
 
 	if (k_is_in_isr()) {
 		timeout = K_NO_WAIT;
@@ -438,6 +442,8 @@ int zbus_chan_notify(const struct zbus_channel *chan, k_timeout_t timeout)
 	int err;
 
 	_ZBUS_ASSERT(chan != NULL, "chan is required");
+	_ZBUS_ASSERT(k_is_in_isr() ? K_TIMEOUT_EQ(timeout, K_NO_WAIT) : true,
+		     "inside an ISR, the timeout must be K_NO_WAIT");
 
 	if (k_is_in_isr()) {
 		timeout = K_NO_WAIT;
@@ -462,6 +468,8 @@ int zbus_chan_notify(const struct zbus_channel *chan, k_timeout_t timeout)
 int zbus_chan_claim(const struct zbus_channel *chan, k_timeout_t timeout)
 {
 	_ZBUS_ASSERT(chan != NULL, "chan is required");
+	_ZBUS_ASSERT(k_is_in_isr() ? K_TIMEOUT_EQ(timeout, K_NO_WAIT) : true,
+		     "inside an ISR, the timeout must be K_NO_WAIT");
 
 	if (k_is_in_isr()) {
 		timeout = K_NO_WAIT;
diff --git a/subsys/zbus/zbus_runtime_observers.c b/subsys/zbus/zbus_runtime_observers.c
index 56c7cbb4530..41c00c9aae7 100644
--- a/subsys/zbus/zbus_runtime_observers.c
+++ b/subsys/zbus/zbus_runtime_observers.c
@@ -9,7 +9,7 @@
 LOG_MODULE_DECLARE(zbus, CONFIG_ZBUS_LOG_LEVEL);
 
 int zbus_chan_add_obs(const struct zbus_channel *chan, const struct zbus_observer *obs,
-		      k_timeout_t timeout)
+		      struct zbus_observer_node *node, k_timeout_t timeout)
 {
 	int err;
 	struct zbus_observer_node *obs_nd, *tmp;
@@ -18,6 +18,7 @@ int zbus_chan_add_obs(const struct zbus_channel *chan, const struct zbus_observe
 	_ZBUS_ASSERT(!k_is_in_isr(), "ISR blocked");
 	_ZBUS_ASSERT(chan != NULL, "chan is required");
 	_ZBUS_ASSERT(obs != NULL, "obs is required");
+	_ZBUS_ASSERT(node != NULL, "node is required");
 
 	err = k_sem_take(&chan->data->sem, timeout);
 	if (err) {
@@ -46,19 +47,9 @@ int zbus_chan_add_obs(const struct zbus_channel *chan, const struct zbus_observe
 		}
 	}
 
-	struct zbus_observer_node *new_obs_nd = k_malloc(sizeof(struct zbus_observer_node));
+	node->obs = obs;
 
-	if (new_obs_nd == NULL) {
-		LOG_ERR("Could not allocate observer node the heap is full!");
-
-		k_sem_give(&chan->data->sem);
-
-		return -ENOMEM;
-	}
-
-	new_obs_nd->obs = obs;
-
-	sys_slist_append(&chan->data->observers, &new_obs_nd->node);
+	sys_slist_append(&chan->data->observers, &node->node);
 
 	k_sem_give(&chan->data->sem);
 
@@ -85,8 +76,6 @@ int zbus_chan_rm_obs(const struct zbus_channel *chan, const struct zbus_observer
 		if (obs_nd->obs == obs) {
 			sys_slist_remove(&chan->data->observers, &prev_obs_nd->node, &obs_nd->node);
 
-			k_free(obs_nd);
-
 			k_sem_give(&chan->data->sem);
 
 			return 0;
diff --git a/tests/application_development/code_relocation/testcase.yaml b/tests/application_development/code_relocation/testcase.yaml
index 4ed3b9210e5..99ca2107abf 100644
--- a/tests/application_development/code_relocation/testcase.yaml
+++ b/tests/application_development/code_relocation/testcase.yaml
@@ -1,7 +1,7 @@
 common:
   tags: linker
 tests:
-  application_development.code_relocation:
+  buildsystem.app_dev.code_relocation:
     filter: not CONFIG_CPU_HAS_NXP_SYSMPU and CONFIG_MINIMAL_LIBC and
             dt_chosen_enabled("zephyr,itcm")
     arch_allow: arm
@@ -9,14 +9,14 @@ tests:
       - CONFIG_RELOCATE_TO_ITCM=y
     platform_allow:
       - mimxrt1060_evk/mimxrt1062/qspi
-  application_development.code_relocation_kinetis:
+  buildsystem.app_dev.code_relocation_kinetis:
     filter: CONFIG_CPU_HAS_NXP_SYSMPU
     arch_allow: arm
     extra_configs:
       - CONFIG_MPU_ALLOW_FLASH_WRITE=y
     platform_allow:
       - frdm_k64f
-  application_development.code_relocation.no_itcm:
+  buildsystem.app_dev.code_relocation.no_itcm:
     filter: not CONFIG_CPU_HAS_NXP_SYSMPU and not dt_chosen_enabled("zephyr,itcm")
     arch_allow: arm
     extra_sections:
@@ -31,11 +31,11 @@ tests:
       - sam_e70_xplained/same70q21
     integration_platforms:
       - qemu_cortex_m3
-  application_development.code_relocation.riscv:
+  buildsystem.app_dev.code_relocation.riscv:
     extra_args: CONF_FILE="prj_riscv.conf"
     platform_allow:
       - qemu_riscv32
       - qemu_riscv64
-  application_development.code_relocation.xtensa:
+  buildsystem.app_dev.code_relocation.xtensa:
     extra_args: CONF_FILE="prj_xtensa.conf"
     platform_allow: qemu_xtensa/dc233c
diff --git a/tests/application_development/software_bill_of_materials/CMakeLists.txt b/tests/application_development/software_bill_of_materials/CMakeLists.txt
new file mode 100644
index 00000000000..90fa8976b91
--- /dev/null
+++ b/tests/application_development/software_bill_of_materials/CMakeLists.txt
@@ -0,0 +1,13 @@
+# Copyright (c) 2024 Basalte bv
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+project(sbom_spdx)
+target_sources(app PRIVATE ${ZEPHYR_BASE}/misc/empty_file.c)
+
+enable_testing()
+include(CTest)
+
+add_test(NAME spdx_gen COMMAND west spdx -d ${CMAKE_BINARY_DIR})
diff --git a/tests/application_development/software_bill_of_materials/PreLoad.cmake b/tests/application_development/software_bill_of_materials/PreLoad.cmake
new file mode 100644
index 00000000000..2691ca6703a
--- /dev/null
+++ b/tests/application_development/software_bill_of_materials/PreLoad.cmake
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Basalte bv
+# SPDX-License-Identifier: Apache-2.0
+
+# WARNING: the PreLoad.cmake is an undocumented feature
+# We need to create the CMake file API query before the configure step
+
+execute_process(
+  COMMAND west spdx --init -d ${CMAKE_BINARY_DIR}
+  COMMAND_ERROR_IS_FATAL ANY
+)
diff --git a/tests/application_development/software_bill_of_materials/prj.conf b/tests/application_development/software_bill_of_materials/prj.conf
new file mode 100644
index 00000000000..197106ddf19
--- /dev/null
+++ b/tests/application_development/software_bill_of_materials/prj.conf
@@ -0,0 +1 @@
+CONFIG_BUILD_OUTPUT_META=y
diff --git a/tests/application_development/software_bill_of_materials/testcase.yaml b/tests/application_development/software_bill_of_materials/testcase.yaml
new file mode 100644
index 00000000000..8436b69fdbe
--- /dev/null
+++ b/tests/application_development/software_bill_of_materials/testcase.yaml
@@ -0,0 +1,8 @@
+common:
+  tags:
+    - spdx
+  integration_platforms:
+    - native_sim
+  harness: ctest
+tests:
+  buildsystem.sbom.spdx: {}
diff --git a/tests/application_development/vector_table_relocation/CMakeLists.txt b/tests/application_development/vector_table_relocation/CMakeLists.txt
new file mode 100644
index 00000000000..9ee6d3f9e35
--- /dev/null
+++ b/tests/application_development/vector_table_relocation/CMakeLists.txt
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+project(vector_table_relocation)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/application_development/vector_table_relocation/README.rst b/tests/application_development/vector_table_relocation/README.rst
new file mode 100644
index 00000000000..04f67a8c624
--- /dev/null
+++ b/tests/application_development/vector_table_relocation/README.rst
@@ -0,0 +1,8 @@
+.. _vector_table_relocation:
+
+Vector table relocation
+#################
+
+Overview
+********
+A simple test that demonstrates the vector table relocation feature.
diff --git a/tests/application_development/vector_table_relocation/prj.conf b/tests/application_development/vector_table_relocation/prj.conf
new file mode 100644
index 00000000000..bb3a09cd8c0
--- /dev/null
+++ b/tests/application_development/vector_table_relocation/prj.conf
@@ -0,0 +1,3 @@
+CONFIG_COVERAGE=n
+CONFIG_ZTEST=y
+CONFIG_SRAM_VECTOR_TABLE=y
diff --git a/tests/application_development/vector_table_relocation/src/main.c b/tests/application_development/vector_table_relocation/src/main.c
new file mode 100644
index 00000000000..903541d006d
--- /dev/null
+++ b/tests/application_development/vector_table_relocation/src/main.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#if !defined(CONFIG_CPU_CORTEX_M)
+#error project can only run on Cortex-M
+#endif
+
+#include <zephyr/kernel.h>
+#include <zephyr/sys/printk.h>
+#include <zephyr/ztest.h>
+
+#ifdef SCB_VTOR_TBLBASE_Msk
+#define VTOR_MASK (SCB_VTOR_TBLBASE_Msk | SCB_VTOR_TBLOFF_Msk)
+#else
+#define VTOR_MASK SCB_VTOR_TBLOFF_Msk
+#endif
+
+/* This function will allow execute from sram region.
+ * This is needed only for this sample because by default all soc will
+ * disable the execute from SRAM.
+ * An application that requires that the code be executed from SRAM will
+ *  have to configure the region appropriately in arm_mpu_regions.c.
+ */
+
+#if (defined(CONFIG_ARM_MPU) && !defined(CONFIG_CPU_HAS_NXP_SYSMPU))
+#include <cmsis_core.h>
+void disable_mpu_rasr_xn(void)
+{
+	uint32_t index;
+	/* Kept the max index as 8(irrespective of soc) because the sram
+	 * would most likely be set at index 2.
+	 */
+	for (index = 0U; index < 8; index++) {
+		MPU->RNR = index;
+#if defined(CONFIG_ARMV8_M_BASELINE) || defined(CONFIG_ARMV8_M_MAINLINE)
+		if (MPU->RBAR & MPU_RBAR_XN_Msk) {
+			MPU->RBAR ^= MPU_RBAR_XN_Msk;
+		}
+#else
+		if (MPU->RASR & MPU_RASR_XN_Msk) {
+			MPU->RASR ^= MPU_RASR_XN_Msk;
+		}
+#endif /* CONFIG_ARMV8_M_BASELINE || CONFIG_ARMV8_M_MAINLINE */
+	}
+}
+#endif /* CONFIG_ARM_MPU */
+
+ZTEST(vector_table_relocation, test_vector_table_in_ram)
+{
+	/* Check that VTOR register effectively point to a RAM based location */
+	volatile uint32_t vtor_address = SCB->VTOR & VTOR_MASK;
+
+	printf("VTOR address: 0x%x\n", vtor_address);
+	zassert_true(vtor_address >= CONFIG_SRAM_BASE_ADDRESS &&
+			     vtor_address <= CONFIG_SRAM_BASE_ADDRESS + CONFIG_SRAM_SIZE,
+		     "Vector table is not in RAM! Address: 0x%x", vtor_address);
+}
+
+void *relocate_code_setup(void)
+{
+#if (defined(CONFIG_ARM_MPU) && !defined(CONFIG_CPU_HAS_NXP_SYSMPU))
+	disable_mpu_rasr_xn();
+#endif /* CONFIG_ARM_MPU */
+	return NULL;
+}
+
+ZTEST_SUITE(vector_table_relocation, NULL, relocate_code_setup, NULL, NULL, NULL);
diff --git a/tests/application_development/vector_table_relocation/testcase.yaml b/tests/application_development/vector_table_relocation/testcase.yaml
new file mode 100644
index 00000000000..401dd9ad21c
--- /dev/null
+++ b/tests/application_development/vector_table_relocation/testcase.yaml
@@ -0,0 +1,11 @@
+common:
+  tags: linker
+tests:
+  application_development.vector_table_relocation.arm:
+    arch_allow: arm
+    filter: CONFIG_CPU_CORTEX_M_HAS_VTOR
+    # Exclude mps3/corstone310 because it uses another mechanism to support relocation
+    # of the vector table (CONFIG_ROMSTART_RELOCATION_ROM).
+    platform_exclude:
+      - mps3/corstone310/an555
+      - mps3/corstone310/fvp
diff --git a/tests/arch/arm/arm_custom_interrupt/src/arm_custom_interrupt.c b/tests/arch/arm/arm_custom_interrupt/src/arm_custom_interrupt.c
index 97d3c55365d..998fe9a2957 100644
--- a/tests/arch/arm/arm_custom_interrupt/src/arm_custom_interrupt.c
+++ b/tests/arch/arm/arm_custom_interrupt/src/arm_custom_interrupt.c
@@ -120,7 +120,7 @@ void arm_isr_handler(const void *args)
  * @{
  */
 
-ZTEST(arm_custom_interrupt, test_arm_interrupt)
+ZTEST(arm_custom_interrupt, test_arm_custom_interrupt)
 {
 	zassert_true(custom_init_called, "Custom IRQ init not called\n");
 
diff --git a/tests/arch/arm/arm_custom_interrupt/testcase.yaml b/tests/arch/arm/arm_custom_interrupt/testcase.yaml
index d20f87e17ae..d4caae91d58 100644
--- a/tests/arch/arm/arm_custom_interrupt/testcase.yaml
+++ b/tests/arch/arm/arm_custom_interrupt/testcase.yaml
@@ -8,3 +8,6 @@ common:
 tests:
   arch.arm.custom_interrupt:
     filter: not CONFIG_TRUSTED_EXECUTION_NONSECURE
+    platform_exclude:
+      - imx95_evk/mimx9596/m7
+      - imx95_evk/mimx9596/m7/ddr
diff --git a/tests/arch/arm/arm_hardfault_validation/src/arm_hardfault.c b/tests/arch/arm/arm_hardfault_validation/src/arm_hardfault.c
index d7b4b509f17..5ad830dabcb 100644
--- a/tests/arch/arm/arm_hardfault_validation/src/arm_hardfault.c
+++ b/tests/arch/arm/arm_hardfault_validation/src/arm_hardfault.c
@@ -25,8 +25,7 @@ void k_sys_fatal_error_handler(unsigned int reason, const struct arch_esf *pEsf)
 	}
 
 	if (reason != expected_reason) {
-		printk("Wrong crash type got %d expected %d\n", reason,
-			expected_reason);
+		printk("Wrong crash type got %d expected %d\n", reason, expected_reason);
 		k_fatal_halt(reason);
 	}
 
@@ -39,8 +38,7 @@ void k_sys_fatal_error_handler(unsigned int reason, const struct arch_esf *pEsf)
 		 * inside the current runtime error
 		 */
 		expected_reason = K_ERR_KERNEL_PANIC;
-		__ASSERT(0,
-		"Assert occurring inside kernel panic");
+		__ASSERT(0, "Assert occurring inside kernel panic");
 	}
 
 	expected_reason = -1;
diff --git a/tests/arch/arm/arm_interrupt/src/arm_interrupt.c b/tests/arch/arm/arm_interrupt/src/arm_interrupt.c
index 3891c9b1d41..05535283be3 100644
--- a/tests/arch/arm/arm_interrupt/src/arm_interrupt.c
+++ b/tests/arch/arm/arm_interrupt/src/arm_interrupt.c
@@ -19,7 +19,7 @@ static volatile uint32_t expected_msp;
 static K_THREAD_STACK_DEFINE(esf_collection_stack, 2048);
 static struct k_thread esf_collection_thread;
 #define MAIN_PRIORITY 7
-#define PRIORITY 5
+#define PRIORITY      5
 
 /**
  * Validates that pEsf matches state from set_regs_with_known_pattern()
@@ -28,11 +28,8 @@ static int check_esf_matches_expectations(const struct arch_esf *pEsf)
 {
 	const uint16_t expected_fault_instruction = 0xde5a; /* udf #90 */
 	const bool caller_regs_match_expected =
-		(pEsf->basic.r0 == 0) &&
-		(pEsf->basic.r1 == 1) &&
-		(pEsf->basic.r2 == 2) &&
-		(pEsf->basic.r3 == 3) &&
-		(pEsf->basic.lr == 15) &&
+		(pEsf->basic.r0 == 0) && (pEsf->basic.r1 == 1) && (pEsf->basic.r2 == 2) &&
+		(pEsf->basic.r3 == 3) && (pEsf->basic.lr == 15) &&
 		(*(uint16_t *)pEsf->basic.pc == expected_fault_instruction);
 	if (!caller_regs_match_expected) {
 		printk("__basic_sf member of ESF is incorrect\n");
@@ -42,14 +39,10 @@ static int check_esf_matches_expectations(const struct arch_esf *pEsf)
 #if defined(CONFIG_EXTRA_EXCEPTION_INFO)
 	const struct _callee_saved *callee_regs = pEsf->extra_info.callee;
 	const bool callee_regs_match_expected =
-		(callee_regs->v1 /* r4 */ == 4) &&
-		(callee_regs->v2 /* r5 */ == 5) &&
-		(callee_regs->v3 /* r6 */ == 6) &&
-		(callee_regs->v4 /* r7 */ == 7) &&
-		(callee_regs->v5 /* r8 */ == 8) &&
-		(callee_regs->v6 /* r9 */ == 9) &&
-		(callee_regs->v7 /* r10 */ == 10) &&
-		(callee_regs->v8 /* r11 */ == 11);
+		(callee_regs->v1 /* r4 */ == 4) && (callee_regs->v2 /* r5 */ == 5) &&
+		(callee_regs->v3 /* r6 */ == 6) && (callee_regs->v4 /* r7 */ == 7) &&
+		(callee_regs->v5 /* r8 */ == 8) && (callee_regs->v6 /* r9 */ == 9) &&
+		(callee_regs->v7 /* r10 */ == 10) && (callee_regs->v8 /* r11 */ == 11);
 	if (!callee_regs_match_expected) {
 		printk("_callee_saved_t member of ESF is incorrect\n");
 		return -1;
@@ -62,10 +55,8 @@ static int check_esf_matches_expectations(const struct arch_esf *pEsf)
 	 */
 	const uint32_t exc_bits_set_mask = 0xff00000C;
 
-	if ((pEsf->extra_info.exc_return & exc_bits_set_mask) !=
-		exc_bits_set_mask) {
-		printk("Incorrect EXC_RETURN of 0x%08x",
-			pEsf->extra_info.exc_return);
+	if ((pEsf->extra_info.exc_return & exc_bits_set_mask) != exc_bits_set_mask) {
+		printk("Incorrect EXC_RETURN of 0x%08x", pEsf->extra_info.exc_return);
 		return -1;
 	}
 
@@ -73,15 +64,13 @@ static int check_esf_matches_expectations(const struct arch_esf *pEsf)
 	 * to the xpsr. (the xpsr value in the copy used for pEsf
 	 * is overwritten in fault.c)
 	 */
-	if (memcmp((void *)callee_regs->psp, pEsf,
-		offsetof(struct arch_esf, basic.xpsr)) != 0) {
+	if (memcmp((void *)callee_regs->psp, pEsf, offsetof(struct arch_esf, basic.xpsr)) != 0) {
 		printk("psp does not match __basic_sf provided\n");
 		return -1;
 	}
 
 	if (pEsf->extra_info.msp != expected_msp) {
-		printk("MSP is 0x%08x but should be 0x%08x",
-			pEsf->extra_info.msp, expected_msp);
+		printk("MSP is 0x%08x but should be 0x%08x", pEsf->extra_info.msp, expected_msp);
 		return -1;
 	}
 #endif /* CONFIG_EXTRA_EXCEPTION_INFO */
@@ -98,8 +87,7 @@ void k_sys_fatal_error_handler(unsigned int reason, const struct arch_esf *pEsf)
 	}
 
 	if (reason != expected_reason) {
-		printk("Wrong crash type got %d expected %d\n", reason,
-			expected_reason);
+		printk("Wrong crash type got %d expected %d\n", reason, expected_reason);
 		k_fatal_halt(reason);
 	}
 
@@ -131,31 +119,33 @@ void set_regs_with_known_pattern(void *p1, void *p2, void *p3)
 	ARG_UNUSED(p2);
 	ARG_UNUSED(p3);
 
-	__asm__ volatile(
-		"mov r1, #1\n"
-		"mov r2, #2\n"
-		"mov r3, #3\n"
-		"mov r4, #4\n"
-		"mov r5, #5\n"
-		"mov r6, #6\n"
-		"mov r7, #7\n"
-		"mov r0, #8\n"
-		"mov r8, r0\n"
-		"add r0, r0, #1\n"
-		"mov r9, r0\n"
-		"add r0, r0, #1\n"
-		"mov r10, r0\n"
-		"add r0, r0, #1\n"
-		"mov r11, r0\n"
-		"add r0, r0, #1\n"
-		"mov r12, r0\n"
-		"add r0, r0, #3\n"
-		"mov lr, r0\n"
-		"mov r0, #0\n"
-		"udf #90\n"
-	);
+	__asm__ volatile("mov r1, #1\n"
+			 "mov r2, #2\n"
+			 "mov r3, #3\n"
+			 "mov r4, #4\n"
+			 "mov r5, #5\n"
+			 "mov r6, #6\n"
+			 "mov r7, #7\n"
+			 "mov r0, #8\n"
+			 "mov r8, r0\n"
+			 "add r0, r0, #1\n"
+			 "mov r9, r0\n"
+			 "add r0, r0, #1\n"
+			 "mov r10, r0\n"
+			 "add r0, r0, #1\n"
+			 "mov r11, r0\n"
+			 "add r0, r0, #1\n"
+			 "mov r12, r0\n"
+			 "add r0, r0, #3\n"
+			 "mov lr, r0\n"
+			 "mov r0, #0\n"
+			 "udf #90\n");
 }
 
+/**
+ * @brief Test to verify code fault handling in ISR execution context
+ * @ingroup kernel_fatal_tests
+ */
 ZTEST(arm_interrupt, test_arm_esf_collection)
 {
 	int test_validation_rv;
@@ -181,23 +171,19 @@ ZTEST(arm_interrupt, test_arm_esf_collection)
 
 	TC_PRINT("Testing ESF Reporting\n");
 	k_thread_create(&esf_collection_thread, esf_collection_stack,
-			K_THREAD_STACK_SIZEOF(esf_collection_stack),
-			set_regs_with_known_pattern,
-			NULL, NULL, NULL, K_PRIO_COOP(PRIORITY), 0,
-			K_NO_WAIT);
+			K_THREAD_STACK_SIZEOF(esf_collection_stack), set_regs_with_known_pattern,
+			NULL, NULL, NULL, K_PRIO_COOP(PRIORITY), 0, K_NO_WAIT);
 
 	test_validation_rv = esf_validation_rv;
 
-	zassert_not_equal(test_validation_rv, TC_FAIL,
-		"ESF fault collection failed");
+	zassert_not_equal(test_validation_rv, TC_FAIL, "ESF fault collection failed");
 }
 
 void arm_isr_handler(const void *args)
 {
 	ARG_UNUSED(args);
 
-#if defined(CONFIG_CPU_CORTEX_M) && defined(CONFIG_FPU) && \
-	defined(CONFIG_FPU_SHARING)
+#if defined(CONFIG_CPU_CORTEX_M) && defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
 	/* Clear Floating Point Status and Control Register (FPSCR),
 	 * to prevent from having the interrupt line set to pending again,
 	 * in case FPU IRQ is selected by the test as "Available IRQ line"
@@ -235,12 +221,15 @@ void arm_isr_handler(const void *args)
 		 */
 		int reason = expected_reason;
 
-		zassert_equal(reason, -1,
-			"expected_reason has not been reset (%d)\n", reason);
+		zassert_equal(reason, -1, "expected_reason has not been reset (%d)\n", reason);
 #endif
 	}
 }
 
+/**
+ * @brief Test ARM Interrupt handling
+ * @ingroup kernel_arch_interrupt_tests
+ */
 ZTEST(arm_interrupt, test_arm_interrupt)
 {
 	/* Determine an NVIC IRQ line that is not currently in use. */
@@ -284,8 +273,7 @@ ZTEST(arm_interrupt, test_arm_interrupt)
 		}
 	}
 
-	zassert_true(i >= 0,
-		"No available IRQ line to use in the test\n");
+	zassert_true(i >= 0, "No available IRQ line to use in the test\n");
 
 	TC_PRINT("Available IRQ line: %u\n", i);
 
@@ -304,14 +292,10 @@ ZTEST(arm_interrupt, test_arm_interrupt)
 	 * expected reason variable is reset.
 	 */
 	reason = expected_reason;
-	zassert_equal(reason, -1,
-		"expected_reason has not been reset (%d)\n", reason);
+	zassert_equal(reason, -1, "expected_reason has not been reset (%d)\n", reason);
 	NVIC_DisableIRQ(i);
 
-	arch_irq_connect_dynamic(i, 0 /* highest priority */,
-		arm_isr_handler,
-		NULL,
-		0);
+	arch_irq_connect_dynamic(i, 0 /* highest priority */, arm_isr_handler, NULL, 0);
 
 	NVIC_ClearPendingIRQ(i);
 	NVIC_EnableIRQ(i);
@@ -355,17 +339,14 @@ ZTEST(arm_interrupt, test_arm_interrupt)
 	 * entry will make PSP descend below the limit and into the MPU guard
 	 * section (or beyond the address pointed by PSPLIM in ARMv8-M MCUs).
 	 */
-#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) && \
-	defined(CONFIG_MPU_STACK_GUARD)
+#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING) && defined(CONFIG_MPU_STACK_GUARD)
 #define FPU_STACK_EXTRA_SIZE 0x48
 	/* If an FP context is present, we should not set the PSP
 	 * too close to the end of the stack, because stacking of
 	 * the ESF might corrupt kernel memory, making it not
 	 * possible to continue the test execution.
 	 */
-	uint32_t fp_extra_size =
-		(__get_CONTROL() & CONTROL_FPCA_Msk) ?
-			FPU_STACK_EXTRA_SIZE : 0;
+	uint32_t fp_extra_size = (__get_CONTROL() & CONTROL_FPCA_Msk) ? FPU_STACK_EXTRA_SIZE : 0;
 	__set_PSP(_current->stack_info.start + 0x10 + fp_extra_size);
 #else
 	__set_PSP(_current->stack_info.start + 0x10);
@@ -417,11 +398,14 @@ static inline void z_vrfy_test_arm_user_interrupt_syscall(void)
 }
 #include <zephyr/syscalls/test_arm_user_interrupt_syscall_mrsh.c>
 
+/**
+ * @brief Test ARM Interrupt handling in user mode
+ * @ingroup kernel_arch_interrupt_tests
+ */
 ZTEST_USER(arm_interrupt, test_arm_user_interrupt)
 {
 	/* Test thread executing in user mode */
-	zassert_true(arch_is_user_context(),
-		"Test thread not running in user mode\n");
+	zassert_true(arch_is_user_context(), "Test thread not running in user mode\n");
 
 	/* Attempt to lock IRQs in user mode */
 	irq_lock();
@@ -455,16 +439,22 @@ ZTEST_USER(arm_interrupt, test_arm_user_interrupt)
 #else
 ZTEST_USER(arm_interrupt, test_arm_user_interrupt)
 {
-	TC_PRINT("Skipped\n");
+	ztest_test_skip();
 }
 #endif /* CONFIG_USERSPACE */
 
-#if defined(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION)
 #pragma GCC push_options
 #pragma GCC optimize("O0")
 /* Avoid compiler optimizing null pointer de-referencing. */
+
+/**
+ * @brief Test ARM Null Pointer Exception handling
+ * @ingroup kernel_arch_interrupt_tests
+ */
 ZTEST(arm_interrupt, test_arm_null_pointer_exception)
 {
+	Z_TEST_SKIP_IFNDEF(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION);
+
 	int reason;
 
 	struct test_struct {
@@ -475,22 +465,9 @@ ZTEST(arm_interrupt, test_arm_null_pointer_exception)
 
 	expected_reason = K_ERR_CPU_EXCEPTION;
 
-	printk("Reading a null pointer value: 0x%0x\n",
-		test_struct_null_pointer->val[1]);
+	printk("Reading a null pointer value: 0x%0x\n", test_struct_null_pointer->val[1]);
 
 	reason = expected_reason;
-	zassert_equal(reason, -1,
-		"expected_reason has not been reset (%d)\n", reason);
+	zassert_equal(reason, -1, "expected_reason has not been reset (%d)\n", reason);
 }
 #pragma GCC pop_options
-#else
-ZTEST(arm_interrupt, test_arm_null_pointer_exception)
-{
-	TC_PRINT("Skipped\n");
-}
-
-#endif /* CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION */
-
-/**
- * @}
- */
diff --git a/tests/arch/arm/arm_irq_advanced_features/src/arm_dynamic_direct_interrupts.c b/tests/arch/arm/arm_irq_advanced_features/src/arm_dynamic_direct_interrupts.c
index 4d46851faef..22634a19021 100644
--- a/tests/arch/arm/arm_irq_advanced_features/src/arm_dynamic_direct_interrupts.c
+++ b/tests/arch/arm/arm_irq_advanced_features/src/arm_dynamic_direct_interrupts.c
@@ -28,6 +28,10 @@ void arm_direct_isr_handler_1(const void *args)
 	test_flag = 2;
 }
 
+/**
+ * @brief Test the ARM Dynamic Direct Interrupts functionality.
+ * @ingroup kernel_arch_interrupt_tests
+ */
 ZTEST(arm_irq_advanced_features, test_arm_dynamic_direct_interrupts)
 {
 	int post_flag = 0;
@@ -41,10 +45,8 @@ ZTEST(arm_irq_advanced_features, test_arm_dynamic_direct_interrupts)
 	irq_disable(DIRECT_ISR_OFFSET);
 
 	/* Attach the ISR handler at run time. */
-	irq_connect_dynamic(DIRECT_ISR_OFFSET, 0 /* highest priority */,
-		arm_direct_isr_handler_0,
-		NULL,
-		0);
+	irq_connect_dynamic(DIRECT_ISR_OFFSET, 0 /* highest priority */, arm_direct_isr_handler_0,
+			    NULL, 0);
 
 	/* Enable and pend the interrupt */
 	irq_enable(DIRECT_ISR_OFFSET);
@@ -65,10 +67,8 @@ ZTEST(arm_irq_advanced_features, test_arm_dynamic_direct_interrupts)
 	irq_disable(DIRECT_ISR_OFFSET);
 
 	/* Attach an alternative ISR handler at run-time. */
-	irq_connect_dynamic(DIRECT_ISR_OFFSET, 0 /* highest priority */,
-		arm_direct_isr_handler_1,
-		NULL,
-		0);
+	irq_connect_dynamic(DIRECT_ISR_OFFSET, 0 /* highest priority */, arm_direct_isr_handler_1,
+			    NULL, 0);
 
 	/* Enable and pend the interrupt */
 	irq_enable(DIRECT_ISR_OFFSET);
@@ -85,6 +85,3 @@ ZTEST(arm_irq_advanced_features, test_arm_dynamic_direct_interrupts)
 	post_flag = test_flag;
 	zassert_true(post_flag == 2, "Test flag not set by ISR1\n");
 }
-/**
- * @}
- */
diff --git a/tests/arch/arm/arm_irq_advanced_features/src/arm_irq_target_state.c b/tests/arch/arm/arm_irq_advanced_features/src/arm_irq_target_state.c
index 802385fa0e5..47f5cc03bdc 100644
--- a/tests/arch/arm/arm_irq_advanced_features/src/arm_irq_target_state.c
+++ b/tests/arch/arm/arm_irq_advanced_features/src/arm_irq_target_state.c
@@ -8,13 +8,15 @@
 #include <zephyr/arch/cpu.h>
 #include <cmsis_core.h>
 
-#if defined(CONFIG_ARM_SECURE_FIRMWARE) && \
-	defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+#if defined(CONFIG_ARM_SECURE_FIRMWARE) && defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 
-extern irq_target_state_t irq_target_state_set(unsigned int irq,
-	irq_target_state_t target_state);
+extern irq_target_state_t irq_target_state_set(unsigned int irq, irq_target_state_t target_state);
 extern int irq_target_state_is_secure(unsigned int irq);
 
+/**
+ * @brief Test the ARM IRQ target state functionality.
+ * @ingroup kernel_arch_interrupt_tests
+ */
 ZTEST(arm_irq_advanced_features, test_arm_irq_target_state)
 {
 	/* Determine an NVIC IRQ line that is implemented
@@ -54,39 +56,29 @@ ZTEST(arm_irq_advanced_features, test_arm_irq_target_state)
 		}
 	}
 
-	zassert_true(i >= 0,
-		"No available IRQ line to configure as zero-latency\n");
+	zassert_true(i >= 0, "No available IRQ line to configure as zero-latency\n");
 
 	TC_PRINT("Available IRQ line: %u\n", i);
 
 	/* Set the available IRQ line to Secure and check the result. */
-	irq_target_state_t result_state =
-		irq_target_state_set(i, IRQ_TARGET_STATE_SECURE);
+	irq_target_state_t result_state = irq_target_state_set(i, IRQ_TARGET_STATE_SECURE);
 
-	zassert_equal(result_state, IRQ_TARGET_STATE_SECURE,
-		"Target state not set to Secure\n");
+	zassert_equal(result_state, IRQ_TARGET_STATE_SECURE, "Target state not set to Secure\n");
 
-	zassert_equal(irq_target_state_is_secure(i), 1,
-		"Target state not set to Secure\n");
+	zassert_equal(irq_target_state_is_secure(i), 1, "Target state not set to Secure\n");
 
 	/* Set the available IRQ line to Secure and check the result. */
-	result_state =
-		irq_target_state_set(i, IRQ_TARGET_STATE_NON_SECURE);
+	result_state = irq_target_state_set(i, IRQ_TARGET_STATE_NON_SECURE);
 
 	zassert_equal(result_state, IRQ_TARGET_STATE_NON_SECURE,
-		"Target state not set to Secure\n");
-	zassert_equal(irq_target_state_is_secure(i), 0,
-		"Target state not set to Non-Secure\n");
-
-	result_state =
-		irq_target_state_set(i, IRQ_TARGET_STATE_SECURE);
+		      "Target state not set to Secure\n");
+	zassert_equal(irq_target_state_is_secure(i), 0, "Target state not set to Non-Secure\n");
 
-	zassert_equal(result_state, IRQ_TARGET_STATE_SECURE,
-		"Target state not set to Secure\n");
+	result_state = irq_target_state_set(i, IRQ_TARGET_STATE_SECURE);
 
-	zassert_equal(irq_target_state_is_secure(i), 1,
-		"Target state not set to Secure\n");
+	zassert_equal(result_state, IRQ_TARGET_STATE_SECURE, "Target state not set to Secure\n");
 
+	zassert_equal(irq_target_state_is_secure(i), 1, "Target state not set to Secure\n");
 }
 #else
 ZTEST(arm_irq_advanced_features, test_arm_irq_target_state)
@@ -94,6 +86,3 @@ ZTEST(arm_irq_advanced_features, test_arm_irq_target_state)
 	TC_PRINT("Skipped (TrustZone-M-enabled Cortex-M Mainline only)\n");
 }
 #endif /* CONFIG_ZERO_LATENCY_IRQS */
-/**
- * @}
- */
diff --git a/tests/arch/arm/arm_irq_advanced_features/src/arm_zero_latency_irqs.c b/tests/arch/arm/arm_irq_advanced_features/src/arm_zero_latency_irqs.c
index 67adbc7e9c2..ca23716f17e 100644
--- a/tests/arch/arm/arm_irq_advanced_features/src/arm_zero_latency_irqs.c
+++ b/tests/arch/arm/arm_irq_advanced_features/src/arm_zero_latency_irqs.c
@@ -18,6 +18,10 @@ void arm_zero_latency_isr_handler(const void *args)
 	test_flag = 1;
 }
 
+/**
+ * @brief Test ARM Zero latency Interrupt functionality.
+ * @ingroup kernel_arch_interrupt_tests
+ */
 ZTEST(arm_irq_advanced_features, test_arm_zero_latency_irqs)
 {
 
@@ -70,17 +74,14 @@ ZTEST(arm_irq_advanced_features, test_arm_zero_latency_irqs)
 		}
 	}
 
-	zassert_true(i >= 0,
-		"No available IRQ line to configure as zero-latency\n");
+	zassert_true(i >= 0, "No available IRQ line to configure as zero-latency\n");
 
 	TC_PRINT("Available IRQ line: %u\n", i);
 
 	/* Configure the available IRQ line as zero-latency. */
 
-	arch_irq_connect_dynamic(i, 0 /* Unused */,
-		arm_zero_latency_isr_handler,
-		NULL,
-		IRQ_ZERO_LATENCY);
+	arch_irq_connect_dynamic(i, 0 /* Unused */, arm_zero_latency_isr_handler, NULL,
+				 IRQ_ZERO_LATENCY);
 
 	NVIC_ClearPendingIRQ(i);
 	NVIC_EnableIRQ(i);
@@ -104,7 +105,3 @@ ZTEST(arm_irq_advanced_features, test_arm_zero_latency_irqs)
 
 	irq_unlock(key);
 }
-
-/**
- * @}
- */
diff --git a/tests/arch/arm/arm_irq_vector_table/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/arch/arm/arm_irq_vector_table/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
new file mode 100644
index 00000000000..d1566b5aa63
--- /dev/null
+++ b/tests/arch/arm/arm_irq_vector_table/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&cpusec_cpuapp_ipc {
+	status = "disabled";
+};
+
+&cpusec_bellboard{
+	status = "disabled";
+};
diff --git a/tests/arch/arm/arm_irq_vector_table/boards/nrf54h20dk_nrf54h20_cpurad.overlay b/tests/arch/arm/arm_irq_vector_table/boards/nrf54h20dk_nrf54h20_cpurad.overlay
new file mode 100644
index 00000000000..04c22168b6c
--- /dev/null
+++ b/tests/arch/arm/arm_irq_vector_table/boards/nrf54h20dk_nrf54h20_cpurad.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&cpusec_cpurad_ipc {
+	status = "disabled";
+};
+
+&cpusec_bellboard{
+	status = "disabled";
+};
diff --git a/tests/arch/arm/arm_irq_vector_table/boards/nrf9280pdk_nrf9280_cpuapp.overlay b/tests/arch/arm/arm_irq_vector_table/boards/nrf9280pdk_nrf9280_cpuapp.overlay
new file mode 100644
index 00000000000..d1566b5aa63
--- /dev/null
+++ b/tests/arch/arm/arm_irq_vector_table/boards/nrf9280pdk_nrf9280_cpuapp.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&cpusec_cpuapp_ipc {
+	status = "disabled";
+};
+
+&cpusec_bellboard{
+	status = "disabled";
+};
diff --git a/tests/arch/arm/arm_irq_vector_table/boards/nrf9280pdk_nrf9280_cpurad.overlay b/tests/arch/arm/arm_irq_vector_table/boards/nrf9280pdk_nrf9280_cpurad.overlay
new file mode 100644
index 00000000000..04c22168b6c
--- /dev/null
+++ b/tests/arch/arm/arm_irq_vector_table/boards/nrf9280pdk_nrf9280_cpurad.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&cpusec_cpurad_ipc {
+	status = "disabled";
+};
+
+&cpusec_bellboard{
+	status = "disabled";
+};
diff --git a/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c b/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c
index fe99dbd4b0f..43b13c9eecf 100644
--- a/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c
+++ b/tests/arch/arm/arm_irq_vector_table/src/arm_irq_vector_table.c
@@ -9,7 +9,6 @@
 #include <cmsis_core.h>
 #include <zephyr/linker/sections.h>
 
-
 /*
  * Offset (starting from the beginning of the vector table)
  * of the location where the ISRs will be manually installed.
@@ -83,7 +82,6 @@ void isr2(void)
  * @{
  */
 
-
 /**
  * @brief Test installation of ISRs directly in the vector table
  *
@@ -106,13 +104,12 @@ ZTEST(vector_table, test_arm_irq_vector_table)
 		k_sem_init(&sem[ii], 0, K_SEM_MAX_LIMIT);
 	}
 
-	zassert_true((k_sem_take(&sem[0], K_NO_WAIT) ||
-		      k_sem_take(&sem[1], K_NO_WAIT) ||
-		      k_sem_take(&sem[2], K_NO_WAIT)), NULL);
+	zassert_true((k_sem_take(&sem[0], K_NO_WAIT) || k_sem_take(&sem[1], K_NO_WAIT) ||
+		      k_sem_take(&sem[2], K_NO_WAIT)),
+		     NULL);
 
 	for (int ii = 0; ii < 3; ii++) {
-#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) || \
-	defined(CONFIG_SOC_TI_LM3S6965_QEMU)
+#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) || defined(CONFIG_SOC_TI_LM3S6965_QEMU)
 		/* the QEMU does not simulate the
 		 * STIR register: this is a workaround
 		 */
@@ -122,10 +119,18 @@ ZTEST(vector_table, test_arm_irq_vector_table)
 #endif
 	}
 
-	zassert_false((k_sem_take(&sem[0], K_NO_WAIT) ||
-		       k_sem_take(&sem[1], K_NO_WAIT) ||
-		       k_sem_take(&sem[2], K_NO_WAIT)), NULL);
-
+	/*
+	 * It is recommended to have a DSB followed by ISB while
+	 * enabling interrupts using NVIC. Also without this, the
+	 * test fails in scenarios where CONFIG_ROMSTART_RELOCATION_ROM is
+	 * enabled e.g. MPS3 Corstone310.
+	 */
+	__DSB(); /* Ensure write to NVIC completes before continuing */
+	__ISB(); /* Ensure that IRQ is executed */
+
+	zassert_false((k_sem_take(&sem[0], K_NO_WAIT) || k_sem_take(&sem[1], K_NO_WAIT) ||
+		       k_sem_take(&sem[2], K_NO_WAIT)),
+		      NULL);
 }
 
 typedef void (*vth)(void); /* Vector Table Handler */
@@ -143,26 +148,26 @@ typedef void (*vth)(void); /* Vector Table Handler */
  */
 void nrfx_power_clock_irq_handler(void);
 #if defined(CONFIG_SOC_SERIES_NRF51X) || defined(CONFIG_SOC_SERIES_NRF52X)
-#define POWER_CLOCK_IRQ_NUM	POWER_CLOCK_IRQn
+#define POWER_CLOCK_IRQ_NUM POWER_CLOCK_IRQn
 #elif defined(CONFIG_SOC_SERIES_NRF54HX) || defined(CONFIG_SOC_SERIES_NRF92X)
-#define POWER_CLOCK_IRQ_NUM	-1 /* not needed */
+#define POWER_CLOCK_IRQ_NUM -1 /* not needed */
 #else
-#define POWER_CLOCK_IRQ_NUM	CLOCK_POWER_IRQn
+#define POWER_CLOCK_IRQ_NUM CLOCK_POWER_IRQn
 #endif
 
 #if defined(CONFIG_BOARD_QEMU_CORTEX_M0)
 void timer0_nrf_isr(void);
-#define TIMER_IRQ_HANDLER	timer0_nrf_isr
-#define TIMER_IRQ_NUM		TIMER0_IRQn
-#elif defined(CONFIG_SOC_SERIES_NRF54LX) || defined(CONFIG_SOC_SERIES_NRF54HX) || \
+#define TIMER_IRQ_HANDLER timer0_nrf_isr
+#define TIMER_IRQ_NUM     TIMER0_IRQn
+#elif defined(CONFIG_SOC_SERIES_NRF54LX) || defined(CONFIG_SOC_SERIES_NRF54HX) ||                  \
 	defined(CONFIG_SOC_SERIES_NRF92X)
 void nrfx_grtc_irq_handler(void);
-#define TIMER_IRQ_HANDLER	nrfx_grtc_irq_handler
-#define TIMER_IRQ_NUM		GRTC_0_IRQn
+#define TIMER_IRQ_HANDLER nrfx_grtc_irq_handler
+#define TIMER_IRQ_NUM     GRTC_0_IRQn
 #else
 void rtc_nrf_isr(void);
-#define TIMER_IRQ_HANDLER	rtc_nrf_isr
-#define TIMER_IRQ_NUM		RTC1_IRQn
+#define TIMER_IRQ_HANDLER rtc_nrf_isr
+#define TIMER_IRQ_NUM     RTC1_IRQn
 #endif
 
 #define IRQ_VECTOR_TABLE_SIZE (MAX(POWER_CLOCK_IRQ_NUM, MAX(TIMER_IRQ_NUM, _ISR_OFFSET + 2)) + 1)
@@ -172,7 +177,9 @@ vth __irq_vector_table _irq_vector_table[IRQ_VECTOR_TABLE_SIZE] = {
 	[POWER_CLOCK_IRQ_NUM] = nrfx_power_clock_irq_handler,
 #endif
 	[TIMER_IRQ_NUM] = TIMER_IRQ_HANDLER,
-	[_ISR_OFFSET] = isr0, isr1, isr2,
+	[_ISR_OFFSET] = isr0,
+	isr1,
+	isr2,
 };
 #elif defined(CONFIG_SOC_SERIES_CC13X2_CC26X2) || defined(CONFIG_SOC_SERIES_CC13X2X7_CC26X2X7)
 /* TI CC13x2/CC26x2 based platforms also employ a Hardware RTC peripheral
@@ -181,13 +188,13 @@ vth __irq_vector_table _irq_vector_table[IRQ_VECTOR_TABLE_SIZE] = {
  * the custom vector table to handle the timer "tick" interrupts.
  */
 extern void rtc_isr(void);
-vth __irq_vector_table _irq_vector_table[] = {
-	isr0, isr1, isr2, 0,
-	rtc_isr
-};
-#elif (defined(CONFIG_SOC_SERIES_IMXRT6XX) || defined(CONFIG_SOC_SERIES_IMXRT5XX) ||	\
-	defined(CONFIG_SOC_SERIES_RW6XX)) && \
-	defined(CONFIG_MCUX_OS_TIMER)
+vth __irq_vector_table _irq_vector_table[] = {isr0, isr1, isr2, 0, rtc_isr};
+
+/* clang-format off */
+#elif (defined(CONFIG_SOC_SERIES_IMXRT6XX) || defined(CONFIG_SOC_SERIES_IMXRT5XX) ||               \
+	defined(CONFIG_SOC_SERIES_RW6XX)) && defined(CONFIG_MCUX_OS_TIMER)
+/* clang-format on */
+
 /* MXRT685 employs a OS Event timer to implement the Kernel system
  * timer, instead of the ARM Cortex-M SysTick. Therefore, a pointer to
  * the timer ISR needs to be added in the custom vector table to handle
@@ -196,10 +203,8 @@ vth __irq_vector_table _irq_vector_table[] = {
 extern void mcux_lpc_ostick_isr(void);
 vth __irq_vector_table _irq_vector_table[] = {
 	isr0, isr1, isr2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	mcux_lpc_ostick_isr
-};
-#elif (defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX)) && \
+	0,    0,    0,    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, mcux_lpc_ostick_isr};
+#elif (defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT11XX)) &&            \
 	defined(CONFIG_MCUX_GPT_TIMER)
 /** MXRT parts employ a GPT timer peripheral to implement the Kernel system
  * timer, instead of the ARM Cortex-M Systick. Thereforce, a pointer to the
@@ -208,12 +213,15 @@ vth __irq_vector_table _irq_vector_table[] = {
  */
 extern void mcux_imx_gpt_isr(void);
 #if defined(CONFIG_SOC_MIMXRT1011)
+/* clang-format off */
 /* RT1011 GPT timer interrupt is at offset 30 */
 vth __irq_vector_table _irq_vector_table[] = {
 	isr0, isr1, isr2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	0, 0, 0, 0, 0, 0, 0, 0, 0, mcux_imx_gpt_isr
 };
+/* clang-format on */
 #elif defined(CONFIG_SOC_SERIES_IMXRT10XX)
+/* clang-format off */
 /* RT10xx GPT timer interrupt is at offset 100 */
 vth __irq_vector_table _irq_vector_table[] = {
 	isr0, isr1, isr2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -222,23 +230,21 @@ vth __irq_vector_table _irq_vector_table[] = {
 	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 	0, 0, 0, mcux_imx_gpt_isr
 };
+/* clang-format on */
 #elif defined(CONFIG_SOC_SERIES_IMXRT11XX)
 /* RT11xx GPT timer interrupt is at offset 119 */
 vth __irq_vector_table _irq_vector_table[] = {
-	isr0, isr1, isr2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-	mcux_imx_gpt_isr
-};
+	isr0, isr1, isr2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0,    0,    0,    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0,    0,    0,    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0,    0,    0,    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0,    0,    0,    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	0,    0,    0,    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, mcux_imx_gpt_isr};
 #else
 #error "GPT timer enabled, but no known SOC selected. ISR table needs rework"
 #endif
 #else
-vth __irq_vector_table _irq_vector_table[] = {
-	isr0, isr1, isr2
-};
+vth __irq_vector_table _irq_vector_table[] = {isr0, isr1, isr2};
 #endif /* CONFIG_SOC_FAMILY_NORDIC_NRF */
 
 /**
diff --git a/tests/arch/arm/arm_irq_vector_table/src/main.c b/tests/arch/arm/arm_irq_vector_table/src/main.c
index ccb750f51cc..9b7d622d379 100644
--- a/tests/arch/arm/arm_irq_vector_table/src/main.c
+++ b/tests/arch/arm/arm_irq_vector_table/src/main.c
@@ -5,7 +5,7 @@
  */
 
 #if !defined(CONFIG_CPU_CORTEX_M)
-  #error project can only run on Cortex-M
+#error project can only run on Cortex-M
 #endif
 
 #include <zephyr/ztest.h>
diff --git a/tests/arch/arm/arm_irq_vector_table/testcase.yaml b/tests/arch/arm/arm_irq_vector_table/testcase.yaml
index fda52833a82..0e320ee4626 100644
--- a/tests/arch/arm/arm_irq_vector_table/testcase.yaml
+++ b/tests/arch/arm/arm_irq_vector_table/testcase.yaml
@@ -11,3 +11,5 @@ tests:
             not CONFIG_GEN_ISR_TABLES
     platform_exclude:
       - mr_canhubk3
+      - imx95_evk/mimx9596/m7
+      - imx95_evk/mimx9596/m7/ddr
diff --git a/tests/arch/arm/arm_irq_zero_latency_levels/src/main.c b/tests/arch/arm/arm_irq_zero_latency_levels/src/main.c
index 8a145884b74..7953635e69f 100644
--- a/tests/arch/arm/arm_irq_zero_latency_levels/src/main.c
+++ b/tests/arch/arm/arm_irq_zero_latency_levels/src/main.c
@@ -9,21 +9,14 @@
 #include <cmsis_core.h>
 #include <zephyr/sys/barrier.h>
 
-
 #define EXECUTION_TRACE_LENGTH 6
 
-#define IRQ_A_PRIO  1   /* lower priority */
-#define IRQ_B_PRIO  0   /* higher priority */
-
-
-#define CHECK_STEP(pos, val) zassert_equal(	\
-	execution_trace[pos],			\
-	val,					\
-	"Expected %s for step %d but got %s",	\
-	execution_step_str(val),		\
-	pos,					\
-	execution_step_str(execution_trace[pos]))
+#define IRQ_A_PRIO 1 /* lower priority */
+#define IRQ_B_PRIO 0 /* higher priority */
 
+#define CHECK_STEP(pos, val)                                                                       \
+	zassert_equal(execution_trace[pos], val, "Expected %s for step %d but got %s",             \
+		      execution_step_str(val), pos, execution_step_str(execution_trace[pos]))
 
 enum execution_step {
 	STEP_MAIN_BEGIN,
@@ -69,17 +62,13 @@ static const char *execution_step_str(enum execution_step s)
 	return res;
 }
 
-
 static void execution_trace_add(enum execution_step s)
 {
-	__ASSERT(execution_trace_pos < EXECUTION_TRACE_LENGTH,
-		 "Execution trace overflow");
+	__ASSERT(execution_trace_pos < EXECUTION_TRACE_LENGTH, "Execution trace overflow");
 	execution_trace[execution_trace_pos] = s;
 	execution_trace_pos++;
 }
 
-
-
 void isr_a_handler(const void *args)
 {
 	ARG_UNUSED(args);
@@ -93,7 +82,6 @@ void isr_a_handler(const void *args)
 	execution_trace_add(STEP_ISR_A_END);
 }
 
-
 void isr_b_handler(const void *args)
 {
 	ARG_UNUSED(args);
@@ -101,7 +89,6 @@ void isr_b_handler(const void *args)
 	execution_trace_add(STEP_ISR_B_END);
 }
 
-
 static int find_unused_irq(int start)
 {
 	int i;
@@ -141,8 +128,7 @@ static int find_unused_irq(int start)
 		}
 	}
 
-	zassert_true(i >= 0,
-		     "No available IRQ line to configure as zero-latency\n");
+	zassert_true(i >= 0, "No available IRQ line to configure as zero-latency\n");
 
 	TC_PRINT("Available IRQ line: %u\n", i);
 	return i;
@@ -165,14 +151,12 @@ ZTEST(arm_irq_zero_latency_levels, test_arm_zero_latency_levels)
 	irq_b = find_unused_irq(irq_a);
 
 	/* Configure IRQ A as zero-latency interrupt with prio 1 */
-	arch_irq_connect_dynamic(irq_a, IRQ_A_PRIO, isr_a_handler,
-				 NULL, IRQ_ZERO_LATENCY);
+	arch_irq_connect_dynamic(irq_a, IRQ_A_PRIO, isr_a_handler, NULL, IRQ_ZERO_LATENCY);
 	NVIC_ClearPendingIRQ(irq_a);
 	NVIC_EnableIRQ(irq_a);
 
 	/* Configure irq_b as zero-latency interrupt with prio 0 */
-	arch_irq_connect_dynamic(irq_b, IRQ_B_PRIO, isr_b_handler,
-				 NULL, IRQ_ZERO_LATENCY);
+	arch_irq_connect_dynamic(irq_b, IRQ_B_PRIO, isr_b_handler, NULL, IRQ_ZERO_LATENCY);
 	NVIC_ClearPendingIRQ(irq_b);
 	NVIC_EnableIRQ(irq_b);
 
diff --git a/tests/arch/arm/arm_mpu_pxn/CMakeLists.txt b/tests/arch/arm/arm_mpu_pxn/CMakeLists.txt
new file mode 100644
index 00000000000..4eb11b09f20
--- /dev/null
+++ b/tests/arch/arm/arm_mpu_pxn/CMakeLists.txt
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(arm_mpu_pxn)
+
+target_sources(app PRIVATE src/main.c)
+zephyr_linker_sources_ifdef(CONFIG_SOC_MPS3_CORSTONE300 RAM_SECTIONS mps3_corstone300.ld)
+zephyr_linker_sources_ifdef(CONFIG_SOC_MPS3_CORSTONE310 RAM_SECTIONS mps3_corstone310.ld)
diff --git a/tests/arch/arm/arm_mpu_pxn/mps3_corstone300.ld b/tests/arch/arm/arm_mpu_pxn/mps3_corstone300.ld
new file mode 100644
index 00000000000..b4c676183a1
--- /dev/null
+++ b/tests/arch/arm/arm_mpu_pxn/mps3_corstone300.ld
@@ -0,0 +1,11 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+SECTION_DATA_PROLOGUE(.customramfunc, , )
+{
+	*(.customramfunc) * (".customramfunc.*")
+}
+GROUP_DATA_LINK_IN(SRAM, SRAM)
diff --git a/tests/arch/arm/arm_mpu_pxn/mps3_corstone300_an547.overlay b/tests/arch/arm/arm_mpu_pxn/mps3_corstone300_an547.overlay
new file mode 100644
index 00000000000..7c5a2c57677
--- /dev/null
+++ b/tests/arch/arm/arm_mpu_pxn/mps3_corstone300_an547.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+
+/ {
+	sram: sram@11000000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x11000000 DT_SIZE_M(1)>;
+		zephyr,memory-region = "SRAM";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_PXN) )>;
+	};
+};
diff --git a/tests/arch/arm/arm_mpu_pxn/mps3_corstone300_fvp.overlay b/tests/arch/arm/arm_mpu_pxn/mps3_corstone300_fvp.overlay
new file mode 100644
index 00000000000..7c5a2c57677
--- /dev/null
+++ b/tests/arch/arm/arm_mpu_pxn/mps3_corstone300_fvp.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+
+/ {
+	sram: sram@11000000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x11000000 DT_SIZE_M(1)>;
+		zephyr,memory-region = "SRAM";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_PXN) )>;
+	};
+};
diff --git a/tests/arch/arm/arm_mpu_pxn/mps3_corstone310.ld b/tests/arch/arm/arm_mpu_pxn/mps3_corstone310.ld
new file mode 100644
index 00000000000..945f0f0cc6f
--- /dev/null
+++ b/tests/arch/arm/arm_mpu_pxn/mps3_corstone310.ld
@@ -0,0 +1,11 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+SECTION_DATA_PROLOGUE(.customramfunc, , )
+{
+	*(.customramfunc) * (".customramfunc.*")
+}
+GROUP_DATA_LINK_IN(DTCM, DTCM)
diff --git a/tests/arch/arm/arm_mpu_pxn/mps3_corstone310_fvp.overlay b/tests/arch/arm/arm_mpu_pxn/mps3_corstone310_fvp.overlay
new file mode 100644
index 00000000000..cb51331990f
--- /dev/null
+++ b/tests/arch/arm/arm_mpu_pxn/mps3_corstone310_fvp.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr.h>
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+
+/ {
+	dtcm: dtcm@30000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x30000000 DT_SIZE_K(32)>;
+		zephyr,memory-region = "DTCM";
+		zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_PXN) )>;
+	};
+};
diff --git a/tests/arch/arm/arm_mpu_pxn/prj.conf b/tests/arch/arm/arm_mpu_pxn/prj.conf
new file mode 100644
index 00000000000..12883f869d7
--- /dev/null
+++ b/tests/arch/arm/arm_mpu_pxn/prj.conf
@@ -0,0 +1,2 @@
+CONFIG_ZTEST=y
+CONFIG_ZTEST_FATAL_HOOK=y
diff --git a/tests/arch/arm/arm_mpu_pxn/src/main.c b/tests/arch/arm/arm_mpu_pxn/src/main.c
new file mode 100644
index 00000000000..690a0018ab1
--- /dev/null
+++ b/tests/arch/arm/arm_mpu_pxn/src/main.c
@@ -0,0 +1,118 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#include <zephyr/ztest.h>
+#include <zephyr/ztest_error_hook.h>
+
+#define __customramfunc                                                                            \
+	__attribute__((noinline)) __attribute__((long_call, section(".customramfunc")))
+
+/**
+ * @brief Simple func to verify PXN via DT config since code with
+ *        __customramfunc falls in an MPU region with PXN set
+ *
+ */
+__customramfunc bool custom_ram_func(void)
+{
+	return true;
+}
+
+/**
+ * @brief This is a simple solution to execute a code with and without PXN set
+ *        because code that falls in `__ramfunc` section has PXN attr set if
+ *        built with CONFIG_USERSPACE and unset otherwise.
+ */
+__ramfunc bool ram_function(void)
+{
+	return true;
+}
+
+#ifdef CONFIG_USERSPACE
+/**
+ * @brief Verify that MPU region with PXN attribute set can be executed from
+ *        unprivileged mode.
+ */
+ZTEST_USER(arm_mpu_pxn, test_arm_mpu_pxn_static_config_user)
+{
+	volatile bool ramfunc_called = false;
+	/*
+	 * With CONFIG_USERSPACE
+	 *  - this func is called in unprivileged mode
+	 *  - and __ramfunc falls in an MPU region which has PXN attribute set
+	 *
+	 * Calling ram_function shouldn't result in an exception.
+	 * This confirms that ram_function though part of a region with PXN attribute set,
+	 * can be called from an unprivileged code.
+	 */
+	ramfunc_called = ram_function();
+	zassert_true(true == ramfunc_called,
+		     "Executing code in __ramfunc failed in unprivileged mode.");
+}
+#endif
+
+/**
+ * @brief Verify that region marked with PXN attribute via DT can be executed
+ *        from unprivileged mode but cannot be executed from privileged mode.
+ */
+ZTEST_USER(arm_mpu_pxn, test_arm_mpu_pxn_dt)
+{
+	volatile bool ramfunc_called = false;
+#ifndef CONFIG_USERSPACE
+	/*
+	 * It is expected that calling ram_function() should result in an exception
+	 * because with CONFIG_USERSPACE, ram_function falls in region with
+	 * PXN attribute set.
+	 */
+	ztest_set_fault_valid(true);
+#endif
+
+	ramfunc_called = custom_ram_func();
+
+#ifdef CONFIG_USERSPACE
+	zassert_true(1 == ramfunc_called,
+		     "Executing code in __customramfunc failed in unprivileged mode.");
+#else
+	/*
+	 * If calling ram_function didn't result in an MPU fault then,
+	 * PXN isn't working as expected so, fail the test.
+	 */
+	ztest_test_fail();
+#endif
+}
+
+/**
+ * @brief This func is always called in privileged mode so, verify that:
+ *        - region marked with PXN attribute
+ *          cannot be executed from privileged mode
+ *        - and same region when marked without PXN attribute
+ *          can be executed from privileged mode
+ */
+ZTEST(arm_mpu_pxn, test_arm_mpu_pxn_static_config)
+{
+	volatile bool ramfunc_called = false;
+#ifdef CONFIG_USERSPACE
+	/*
+	 * It is expected that calling ram_function() should result in an exception
+	 * because with CONFIG_USERSPACE, ram_function falls in region with
+	 * PXN attribute set.
+	 */
+	ztest_set_fault_valid(true);
+#endif
+	ramfunc_called = ram_function();
+
+#ifdef CONFIG_USERSPACE
+	/*
+	 * If calling ram_function didn't result in an MPU fault then,
+	 * PXN isn't working as expected so, fail the test.
+	 */
+	ztest_test_fail();
+#else
+	zassert_true(1 == ramfunc_called, "Executing code in __ramfunc failed in privileged mode.");
+#endif
+}
+
+ZTEST_SUITE(arm_mpu_pxn, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/arch/arm/arm_mpu_pxn/testcase.yaml b/tests/arch/arm/arm_mpu_pxn/testcase.yaml
new file mode 100644
index 00000000000..c6b11b32160
--- /dev/null
+++ b/tests/arch/arm/arm_mpu_pxn/testcase.yaml
@@ -0,0 +1,19 @@
+common:
+  filter: CONFIG_ARM_MPU_PXN
+  tags:
+    - arm
+    - mpu
+  platform_allow:
+    - mps3/corstone300/an547
+    - mps3/corstone300/fvp
+    - mps3/corstone310/fvp
+tests:
+  # To verify that region marked with PXN attribute can be executed from unprivileged code
+  # and cannot be executed from privileged code
+  arch.arm.pxn_with_userspace:
+    extra_configs:
+      - CONFIG_USERSPACE=y
+  # To verify that region marked *without* PXN attribute can be executed from privileged code
+  arch.arm.pxn_without_userspace:
+    extra_configs:
+      - CONFIG_USERSPACE=n
diff --git a/tests/arch/arm/arm_no_multithreading/src/main.c b/tests/arch/arm/arm_no_multithreading/src/main.c
index c9e4cdd02f3..ae2bb66d468 100644
--- a/tests/arch/arm/arm_no_multithreading/src/main.c
+++ b/tests/arch/arm/arm_no_multithreading/src/main.c
@@ -11,7 +11,7 @@
 #include <zephyr/sys/barrier.h>
 
 #if !defined(CONFIG_CPU_CORTEX_M)
-  #error test can only run on Cortex-M MCUs
+#error test can only run on Cortex-M MCUs
 #endif
 
 #if defined(CONFIG_ARMV8_1_M_MAINLINE)
@@ -19,9 +19,9 @@
  * For ARMv8.1-M, the FPSCR[18:16] LTPSIZE field may always read 0b010 if MVE
  * is not implemented, so mask it when validating the value of the FPSCR.
  */
-#define FPSCR_MASK		(~FPU_FPDSCR_LTPSIZE_Msk)
+#define FPSCR_MASK (~FPU_FPDSCR_LTPSIZE_Msk)
 #else
-#define FPSCR_MASK		(0xffffffffU)
+#define FPSCR_MASK (0xffffffffU)
 #endif
 
 K_THREAD_STACK_DECLARE(z_main_stack, CONFIG_MAIN_STACK_SIZE);
@@ -46,8 +46,7 @@ void k_sys_fatal_error_handler(unsigned int reason, const struct arch_esf *pEsf)
 	}
 
 	if (reason != expected_reason) {
-		printk("Wrong crash type got %d expected %d\n", reason,
-			expected_reason);
+		printk("Wrong crash type got %d expected %d\n", reason, expected_reason);
 		k_fatal_halt(reason);
 	}
 
@@ -61,29 +60,22 @@ void test_main(void)
 	uint32_t psp = (uint32_t)__get_PSP();
 	uint32_t main_stack_base = (uint32_t)K_THREAD_STACK_BUFFER(z_main_stack);
 	uint32_t main_stack_top = (uint32_t)(K_THREAD_STACK_BUFFER(z_main_stack) +
-		K_THREAD_STACK_SIZEOF(z_main_stack));
+					     K_THREAD_STACK_SIZEOF(z_main_stack));
 
-	__ASSERT(
-		(psp >= main_stack_base) && (psp <= main_stack_top),
-			"PSP out of bounds: 0x%x (0x%x - 0x%x)",
-			psp, main_stack_base, main_stack_top);
+	__ASSERT((psp >= main_stack_base) && (psp <= main_stack_top),
+		 "PSP out of bounds: 0x%x (0x%x - 0x%x)", psp, main_stack_base, main_stack_top);
 
 #if defined(CONFIG_FPU)
-	__ASSERT((__get_FPSCR() & FPSCR_MASK) == 0,
-		"FPSCR not zero (0x%x)", __get_FPSCR());
+	__ASSERT((__get_FPSCR() & FPSCR_MASK) == 0, "FPSCR not zero (0x%x)", __get_FPSCR());
 #endif
 
 #if defined(CONFIG_BUILTIN_STACK_GUARD)
 	uint32_t psplim = (uint32_t)__get_PSPLIM();
-	__ASSERT(
-		(psplim == main_stack_base),
-			"PSPLIM not set to main stack base: (0x%x)",
-			psplim);
+	__ASSERT((psplim == main_stack_base), "PSPLIM not set to main stack base: (0x%x)", psplim);
 #endif
 
 	int key = arch_irq_lock();
-	__ASSERT(arch_irq_unlocked(key),
-		"IRQs locked in main()");
+	__ASSERT(arch_irq_unlocked(key), "IRQs locked in main()");
 
 	arch_irq_unlock(key);
 
@@ -136,10 +128,7 @@ void test_main(void)
 
 		printk("Available IRQ line: %u\n", i);
 
-		arch_irq_connect_dynamic(i, 0 /* highest priority */,
-			arm_isr_handler,
-			NULL,
-			0);
+		arch_irq_connect_dynamic(i, 0 /* highest priority */, arm_isr_handler, NULL, 0);
 
 		NVIC_EnableIRQ(i);
 
diff --git a/tests/arch/arm/arm_no_multithreading/testcase.yaml b/tests/arch/arm/arm_no_multithreading/testcase.yaml
index 3aa62846e81..8561bab6246 100644
--- a/tests/arch/arm/arm_no_multithreading/testcase.yaml
+++ b/tests/arch/arm/arm_no_multithreading/testcase.yaml
@@ -14,5 +14,6 @@ tests:
       - nrf52840dk/nrf52840
       - nrf9160dk/nrf9160
       - nrf51dk/nrf51822
+      - xg29_rb4412a
     integration_platforms:
       - qemu_cortex_m0
diff --git a/tests/arch/arm/arm_runtime_nmi/src/arm_runtime_nmi.c b/tests/arch/arm/arm_runtime_nmi/src/arm_runtime_nmi.c
index 87e4237d961..3d9c913dc8b 100644
--- a/tests/arch/arm/arm_runtime_nmi/src/arm_runtime_nmi.c
+++ b/tests/arch/arm/arm_runtime_nmi/src/arm_runtime_nmi.c
@@ -35,7 +35,6 @@ static void nmi_test_isr(void)
  * @{
  */
 
-
 /**
  * @brief test the behavior of CONFIG_RUNTIME_NMI at run time
  *
diff --git a/tests/arch/arm/arm_sw_vector_relay/src/arm_sw_vector_relay.c b/tests/arch/arm/arm_sw_vector_relay/src/arm_sw_vector_relay.c
index be400746d92..506febcdb44 100644
--- a/tests/arch/arm/arm_sw_vector_relay/src/arm_sw_vector_relay.c
+++ b/tests/arch/arm/arm_sw_vector_relay/src/arm_sw_vector_relay.c
@@ -15,6 +15,13 @@ extern uint32_t _vector_table;
 extern uint32_t __vector_relay_handler;
 extern uint32_t _vector_table_pointer;
 
+
+/**
+ * @brief Test the ARM Software Vector Relay functionality.
+ *
+ * This test verifies the correctness of the ARM software vector relay mechanism.
+ * @ingroup kernel_arch_interrupt_tests
+ */
 ZTEST(arm_sw_vector_relay, test_arm_sw_vector_relay)
 {
 	uint32_t vector_relay_table_addr = (uint32_t)&__vector_relay_table;
@@ -24,15 +31,12 @@ ZTEST(arm_sw_vector_relay, test_arm_sw_vector_relay)
 	 * entries for MSP and ResetHandler) point to the relay handling
 	 * function.
 	 */
-	const uint32_t *vector_relay_table_addr_val =
-		(uint32_t *)(vector_relay_table_addr);
+	const uint32_t *vector_relay_table_addr_val = (uint32_t *)(vector_relay_table_addr);
 
 	for (int i = 2; i < 16 + CONFIG_NUM_IRQS; i++) {
-		zassert_true(vector_relay_table_addr_val[i] ==
-			vector_relay_handler_func,
-			"vector relay table not pointing to the relay handler: 0x%x, 0x%x\n",
-			vector_relay_table_addr_val[i],
-			vector_relay_handler_func);
+		zassert_true(vector_relay_table_addr_val[i] == vector_relay_handler_func,
+			     "vector relay table not pointing to the relay handler: 0x%x, 0x%x\n",
+			     vector_relay_table_addr_val[i], vector_relay_handler_func);
 	}
 
 #if defined(CONFIG_CPU_CORTEX_M_HAS_VTOR)
@@ -45,27 +49,22 @@ ZTEST(arm_sw_vector_relay, test_arm_sw_vector_relay)
 	 */
 	uint32_t mask = MAX(128, Z_POW2_CEIL(4 * (16 + CONFIG_NUM_IRQS))) - 1;
 
-	zassert_true(((vector_table_addr) & mask) == 0,
-		"vector table not properly aligned: 0x%x\n",
-		vector_table_addr);
-	zassert_true(((vector_relay_table_addr) & mask) == 0,
-		"vector relay table not properly aligned: 0x%x\n",
-		vector_relay_table_addr);
+	zassert_true(((vector_table_addr)&mask) == 0, "vector table not properly aligned: 0x%x\n",
+		     vector_table_addr);
+	zassert_true(((vector_relay_table_addr)&mask) == 0,
+		     "vector relay table not properly aligned: 0x%x\n", vector_relay_table_addr);
 
 	/* Verify that the VTOR points to the real vector table,
 	 * NOT the table that contains the forwarding function.
 	 */
 	zassert_true(SCB->VTOR == (uint32_t)_vector_start,
-		"VTOR not pointing to the real vector table\n");
+		     "VTOR not pointing to the real vector table\n");
 #else
 	/* If VTOR is not present then we already need to forward interrupts
 	 * before loading any child chain-loadable image.
 	 */
 	zassert_true(_vector_table_pointer == (uint32_t)_vector_start,
-		"vector table pointer not pointing to vector start, 0x%x, 0x%x\n",
-		_vector_table_pointer, _vector_start);
+		     "vector table pointer not pointing to vector start, 0x%x, 0x%x\n",
+		     _vector_table_pointer, _vector_start);
 #endif
 }
-/**
- * @}
- */
diff --git a/tests/arch/arm/arm_sw_vector_relay/src/main.c b/tests/arch/arm/arm_sw_vector_relay/src/main.c
index 4cbaadb8e71..c5adca252df 100644
--- a/tests/arch/arm/arm_sw_vector_relay/src/main.c
+++ b/tests/arch/arm/arm_sw_vector_relay/src/main.c
@@ -5,7 +5,7 @@
  */
 
 #if !defined(CONFIG_CPU_CORTEX_M)
-  #error test can only run on Cortex-M MCUs
+#error test can only run on Cortex-M MCUs
 #endif
 
 #include <zephyr/ztest.h>
diff --git a/tests/arch/arm/arm_thread_swap/src/arm_syscalls.c b/tests/arch/arm/arm_thread_swap/src/arm_syscalls.c
index 075b36126a1..4d55241bed7 100644
--- a/tests/arch/arm/arm_thread_swap/src/arm_syscalls.c
+++ b/tests/arch/arm/arm_thread_swap/src/arm_syscalls.c
@@ -12,15 +12,14 @@
 #include <offsets_short_arch.h>
 #include <ksched.h>
 
-#if !defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && \
-	!defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+#if !defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && !defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 #error "Unsupported architecture"
 #endif
 
 #if defined(CONFIG_USERSPACE)
 
 #define PRIORITY 0
-#define DB_VAL 0xDEADBEEF
+#define DB_VAL   0xDEADBEEF
 
 static struct k_thread user_thread;
 static K_THREAD_STACK_DEFINE(user_thread_stack, 1024);
@@ -39,22 +38,20 @@ void z_impl_test_arm_user_syscall(void)
 	 * - MSPLIM register still guards the interrupt stack
 	 */
 	zassert_true((_current->arch.mode & CONTROL_nPRIV_Msk) == 0,
-	"mode variable not set to PRIV mode in system call\n");
+		     "mode variable not set to PRIV mode in system call\n");
 
-	zassert_false(arch_is_user_context(),
-	"arch_is_user_context() indicates nPRIV\n");
+	zassert_false(arch_is_user_context(), "arch_is_user_context() indicates nPRIV\n");
 
 	zassert_true(
 		((__get_PSP() >= _current->arch.priv_stack_start) &&
-		(__get_PSP() < (_current->arch.priv_stack_start +
-			CONFIG_PRIVILEGED_STACK_SIZE))),
-	"Process SP outside thread privileged stack limits\n");
+		 (__get_PSP() < (_current->arch.priv_stack_start + CONFIG_PRIVILEGED_STACK_SIZE))),
+		"Process SP outside thread privileged stack limits\n");
 
 #if defined(CONFIG_BUILTIN_STACK_GUARD)
 	zassert_true(__get_PSPLIM() == _current->arch.priv_stack_start,
-	"PSPLIM not guarding the thread's privileged stack\n");
+		     "PSPLIM not guarding the thread's privileged stack\n");
 	zassert_true(__get_MSPLIM() == (uint32_t)z_interrupt_stacks,
-	"MSPLIM not guarding the interrupt stack\n");
+		     "MSPLIM not guarding the interrupt stack\n");
 #endif
 }
 
@@ -64,7 +61,6 @@ static inline void z_vrfy_test_arm_user_syscall(void)
 }
 #include <zephyr/syscalls/test_arm_user_syscall_mrsh.c>
 
-
 void arm_isr_handler(const void *args)
 {
 	ARG_UNUSED(args);
@@ -79,16 +75,13 @@ void arm_isr_handler(const void *args)
 	 */
 
 	zassert_true((_current->arch.mode & CONTROL_nPRIV_Msk) != 0,
-	"mode variable not set to nPRIV mode for user thread\n");
+		     "mode variable not set to nPRIV mode for user thread\n");
 
-	zassert_false(arch_is_user_context(),
-	"arch_is_user_context() indicates nPRIV in ISR\n");
+	zassert_false(arch_is_user_context(), "arch_is_user_context() indicates nPRIV in ISR\n");
 
-	zassert_true(
-		((__get_PSP() >= _current->stack_info.start) &&
-		(__get_PSP() < (_current->stack_info.start +
-			_current->stack_info.size))),
-	"Process SP outside thread stack limits\n");
+	zassert_true(((__get_PSP() >= _current->stack_info.start) &&
+		      (__get_PSP() < (_current->stack_info.start + _current->stack_info.size))),
+		     "Process SP outside thread stack limits\n");
 
 	static int first_call = 1;
 
@@ -106,10 +99,9 @@ void arm_isr_handler(const void *args)
 		/* Second ISR run occurs after thread context-switch.
 		 * We expect PSPLIM to be clear at this point.
 		 */
-		zassert_true(__get_PSPLIM() == 0,
-		"PSPLIM not clear\n");
+		zassert_true(__get_PSPLIM() == 0, "PSPLIM not clear\n");
 		zassert_true(__get_MSPLIM() == (uint32_t)z_interrupt_stacks,
-		"MSPLIM not guarding the interrupt stack\n");
+			     "MSPLIM not guarding the interrupt stack\n");
 #endif
 		NVIC_DisableIRQ((uint32_t)args);
 	}
@@ -151,7 +143,10 @@ static void user_thread_entry(void *p1, void *p2, void *p3)
 	barrier_isync_fence_full();
 #endif
 }
-
+/**
+ * @brief Test ARM thread swap mechanism
+ * @ingroup kernel_arch_sched_tests
+ */
 ZTEST(arm_thread_swap, test_arm_syscalls)
 {
 	int i = 0;
@@ -166,22 +161,19 @@ ZTEST(arm_thread_swap, test_arm_syscalls)
 	 * - MSPLIM register guards the interrupt stack
 	 */
 	zassert_true((_current->arch.mode & CONTROL_nPRIV_Msk) == 0,
-	"mode variable not set to PRIV mode for supervisor thread\n");
+		     "mode variable not set to PRIV mode for supervisor thread\n");
 
-	zassert_false(arch_is_user_context(),
-	"arch_is_user_context() indicates nPRIV\n");
+	zassert_false(arch_is_user_context(), "arch_is_user_context() indicates nPRIV\n");
 
-	zassert_true(
-		((__get_PSP() >= _current->stack_info.start) &&
-		(__get_PSP() < (_current->stack_info.start +
-			_current->stack_info.size))),
-	"Process SP outside thread stack limits\n");
+	zassert_true(((__get_PSP() >= _current->stack_info.start) &&
+		      (__get_PSP() < (_current->stack_info.start + _current->stack_info.size))),
+		     "Process SP outside thread stack limits\n");
 
 #if defined(CONFIG_BUILTIN_STACK_GUARD)
 	zassert_true(__get_PSPLIM() == _current->stack_info.start,
-	"PSPLIM not guarding the default stack\n");
+		     "PSPLIM not guarding the default stack\n");
 	zassert_true(__get_MSPLIM() == (uint32_t)z_interrupt_stacks,
-	"MSPLIM not guarding the interrupt stack\n");
+		     "MSPLIM not guarding the interrupt stack\n");
 #endif
 
 #if defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
@@ -207,15 +199,11 @@ ZTEST(arm_thread_swap, test_arm_syscalls)
 		}
 	}
 
-	zassert_true(i >= 0,
-		 "No available IRQ line to use in the test\n");
+	zassert_true(i >= 0, "No available IRQ line to use in the test\n");
 
 	TC_PRINT("Available IRQ line: %u\n", i);
 
-	arch_irq_connect_dynamic(i, 0 /* highest priority */,
-		arm_isr_handler,
-		(uint32_t *)i,
-		0);
+	arch_irq_connect_dynamic(i, 0 /* highest priority */, arm_isr_handler, (uint32_t *)i, 0);
 
 	NVIC_ClearPendingIRQ(i);
 	NVIC_EnableIRQ(i);
@@ -225,19 +213,15 @@ ZTEST(arm_thread_swap, test_arm_syscalls)
 	 * i.e. to allow the inspection of the thread state
 	 * while running in user mode.
 	 */
-	 SCB->CCR |= SCB_CCR_USERSETMPEND_Msk;
+	SCB->CCR |= SCB_CCR_USERSETMPEND_Msk;
 #endif /* CONFIG_ARMV7_M_ARMV8_M_MAINLINE*/
 
 	/* Create and switch to a user thread, passing
 	 * as argument the IRQ line to used in the test.
 	 */
-	k_thread_create(&user_thread,
-		user_thread_stack,
-		K_THREAD_STACK_SIZEOF(user_thread_stack),
-		user_thread_entry,
-		(uint32_t *)i, NULL, NULL,
-		K_PRIO_COOP(PRIORITY), K_USER,
-		K_NO_WAIT);
+	k_thread_create(&user_thread, user_thread_stack, K_THREAD_STACK_SIZEOF(user_thread_stack),
+			user_thread_entry, (uint32_t *)i, NULL, NULL, K_PRIO_COOP(PRIORITY), K_USER,
+			K_NO_WAIT);
 }
 
 void z_impl_test_arm_cpu_write_reg(void)
@@ -254,12 +238,10 @@ void z_impl_test_arm_cpu_write_reg(void)
 	 * after returning from the system call
 	 */
 	TC_PRINT("Writing 0xDEADBEEF values into registers\n");
-	__asm__ volatile (
-		"ldr r0, =0xDEADBEEF;\n\t"
-		"ldr r1, =0xDEADBEEF;\n\t"
-		"ldr r2, =0xDEADBEEF;\n\t"
-		"ldr r3, =0xDEADBEEF;\n\t"
-		);
+	__asm__ volatile("ldr r0, =0xDEADBEEF;\n\t"
+			 "ldr r1, =0xDEADBEEF;\n\t"
+			 "ldr r2, =0xDEADBEEF;\n\t"
+			 "ldr r3, =0xDEADBEEF;\n\t");
 	TC_PRINT("Exit from system call\n");
 }
 
@@ -286,15 +268,15 @@ ZTEST_USER(arm_thread_swap, test_syscall_cpu_scrubs_regs)
 
 	test_arm_cpu_write_reg();
 
-	__asm__ volatile ("mov %0, r0" : "=r"(arm_reg_val[0]));
-	__asm__ volatile ("mov %0, r1" : "=r"(arm_reg_val[1]));
-	__asm__ volatile ("mov %0, r2" : "=r"(arm_reg_val[2]));
-	__asm__ volatile ("mov %0, r3" : "=r"(arm_reg_val[3]));
+	__asm__ volatile("mov %0, r0" : "=r"(arm_reg_val[0]));
+	__asm__ volatile("mov %0, r1" : "=r"(arm_reg_val[1]));
+	__asm__ volatile("mov %0, r2" : "=r"(arm_reg_val[2]));
+	__asm__ volatile("mov %0, r3" : "=r"(arm_reg_val[3]));
 
 	for (int i = 0; i < 4; i++) {
 		zassert_not_equal(arm_reg_val[i], DB_VAL,
-				"register value is 0xDEADBEEF, "
-				"not scrubbed after system call.");
+				  "register value is 0xDEADBEEF, "
+				  "not scrubbed after system call.");
 	}
 }
 #else
@@ -309,6 +291,3 @@ ZTEST(arm_thread_swap, test_arm_syscalls)
 }
 
 #endif /* CONFIG_USERSPACE */
-/**
- * @}
- */
diff --git a/tests/arch/arm/arm_thread_swap/src/arm_thread_arch.c b/tests/arch/arm/arm_thread_swap/src/arm_thread_arch.c
index a617abe0680..a29b76fc5a2 100644
--- a/tests/arch/arm/arm_thread_swap/src/arm_thread_arch.c
+++ b/tests/arch/arm/arm_thread_swap/src/arm_thread_arch.c
@@ -12,19 +12,18 @@
 #include <offsets_short_arch.h>
 #include <ksched.h>
 
-#if !defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && \
-	!defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+#if !defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && !defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 #error "Unsupported architecture"
 #endif
 
-#define PRIORITY 0
+#define PRIORITY           0
 #define BASEPRI_MODIFIED_1 0x20
 #define BASEPRI_MODIFIED_2 0x40
 #define SWAP_RETVAL        0x1234
 
 #ifndef EXC_RETURN_FTYPE
 /* bit [4] allocate stack for floating-point context: 0=done 1=skipped  */
-#define EXC_RETURN_FTYPE           (0x00000010UL)
+#define EXC_RETURN_FTYPE (0x00000010UL)
 #endif
 
 #if defined(CONFIG_ARMV8_1_M_MAINLINE)
@@ -32,9 +31,9 @@
  * For ARMv8.1-M, the FPSCR[18:16] LTPSIZE field may always read 0b010 if MVE
  * is not implemented, so mask it when validating the value of the FPSCR.
  */
-#define FPSCR_MASK		(~FPU_FPDSCR_LTPSIZE_Msk)
+#define FPSCR_MASK (~FPU_FPDSCR_LTPSIZE_Msk)
 #else
-#define FPSCR_MASK		(0xffffffffU)
+#define FPSCR_MASK (0xffffffffU)
 #endif
 
 extern void z_move_thread_to_end_of_prio_q(struct k_thread *thread);
@@ -53,75 +52,54 @@ int ztest_swap_return_val;
 /* Arbitrary values for the callee-saved registers,
  * enforced in the beginning of the test.
  */
-const _callee_saved_t ztest_thread_callee_saved_regs_init = {
-	.v1 = 0x12345678, .v2 = 0x23456789, .v3 = 0x3456789a, .v4 = 0x456789ab,
-	.v5 = 0x56789abc, .v6 = 0x6789abcd, .v7 = 0x789abcde, .v8 = 0x89abcdef
-};
+const _callee_saved_t ztest_thread_callee_saved_regs_init = {.v1 = 0x12345678,
+							     .v2 = 0x23456789,
+							     .v3 = 0x3456789a,
+							     .v4 = 0x456789ab,
+							     .v5 = 0x56789abc,
+							     .v6 = 0x6789abcd,
+							     .v7 = 0x789abcde,
+							     .v8 = 0x89abcdef};
 
 static void load_callee_saved_regs(const _callee_saved_t *regs)
 {
 	/* Load the callee-saved registers with given values */
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
-	__asm__ volatile (
-		"mov r1, r7;\n\t"
-		"mov r0, %0;\n\t"
-		"add r0, #16;\n\t"
-		"ldmia r0!, {r4-r7};\n\t"
-		"mov r8, r4;\n\t"
-		"mov r9, r5;\n\t"
-		"mov r10, r6;\n\t"
-		"mov r11, r7;\n\t"
-		"sub r0, #32;\n\t"
-		"ldmia r0!, {r4-r7};\n\t"
-		"mov r7, r1;\n\t"
-		: /* no output */
-		: "r" (regs)
-		: "memory", "r1", "r0"
-	);
+	__asm__ volatile("mov r1, r7;\n\t"
+			 "mov r0, %0;\n\t"
+			 "add r0, #16;\n\t"
+			 "ldmia r0!, {r4-r7};\n\t"
+			 "mov r8, r4;\n\t"
+			 "mov r9, r5;\n\t"
+			 "mov r10, r6;\n\t"
+			 "mov r11, r7;\n\t"
+			 "sub r0, #32;\n\t"
+			 "ldmia r0!, {r4-r7};\n\t"
+			 "mov r7, r1;\n\t"
+			 : /* no output */
+			 : "r"(regs)
+			 : "memory", "r1", "r0");
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-	__asm__ volatile (
-		"mov r1, r7;\n\t"
-		"ldmia %0, {v1-v8};\n\t"
-		"mov r7, r1;\n\t"
-		: /* no output */
-		: "r" (regs)
-		: "memory", "r1"
-	);
+	__asm__ volatile("mov r1, r7;\n\t"
+			 "ldmia %0, {v1-v8};\n\t"
+			 "mov r7, r1;\n\t"
+			 : /* no output */
+			 : "r"(regs)
+			 : "memory", "r1");
 #endif
 	barrier_dsync_fence_full();
 }
 
-static void verify_callee_saved(const _callee_saved_t *src,
-		const _callee_saved_t *dst)
+static void verify_callee_saved(const _callee_saved_t *src, const _callee_saved_t *dst)
 {
 	/* Verify callee-saved registers are as expected */
-	zassert_true((src->v1 == dst->v1)
-			&& (src->v2 == dst->v2)
-			&& (src->v3 == dst->v3)
-			&& (src->v4 == dst->v4)
-			&& (src->v5 == dst->v5)
-			&& (src->v6 == dst->v6)
-			&& (src->v7 == dst->v7)
-			&& (src->v8 == dst->v8),
-		" got: 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n"
-		" expected:  0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n",
-		src->v1,
-		src->v2,
-		src->v3,
-		src->v4,
-		src->v5,
-		src->v6,
-		src->v7,
-		src->v8,
-		dst->v1,
-		dst->v2,
-		dst->v3,
-		dst->v4,
-		dst->v5,
-		dst->v6,
-		dst->v7,
-		dst->v8
-	);
+	zassert_true((src->v1 == dst->v1) && (src->v2 == dst->v2) && (src->v3 == dst->v3) &&
+			     (src->v4 == dst->v4) && (src->v5 == dst->v5) && (src->v6 == dst->v6) &&
+			     (src->v7 == dst->v7) && (src->v8 == dst->v8),
+		     " got: 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n"
+		     " expected:  0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n",
+		     src->v1, src->v2, src->v3, src->v4, src->v5, src->v6, src->v7, src->v8,
+		     dst->v1, dst->v2, dst->v3, dst->v4, dst->v5, dst->v6, dst->v7, dst->v8);
 }
 
 #if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
@@ -131,85 +109,57 @@ static void verify_callee_saved(const _callee_saved_t *src,
 
 /* Arbitrary values for the floating-point callee-saved registers */
 struct _preempt_float ztest_thread_fp_callee_saved_regs = {
-	.s16 = 0x11111111, .s17 = 0x22222222,
-	.s18 = 0x33333333, .s19 = 0x44444444,
-	.s20 = 0x55555555, .s21 = 0x66666666,
-	.s22 = 0x77777777, .s23 = 0x88888888,
-	.s24 = 0x99999999, .s25 = 0xaaaaaaaa,
-	.s26 = 0xbbbbbbbb, .s27 = 0xcccccccc,
-	.s28 = 0xdddddddd, .s29 = 0xeeeeeeee,
-	.s30 = 0xffffffff, .s31 = 0x00000000,
+	.s16 = 0x11111111,
+	.s17 = 0x22222222,
+	.s18 = 0x33333333,
+	.s19 = 0x44444444,
+	.s20 = 0x55555555,
+	.s21 = 0x66666666,
+	.s22 = 0x77777777,
+	.s23 = 0x88888888,
+	.s24 = 0x99999999,
+	.s25 = 0xaaaaaaaa,
+	.s26 = 0xbbbbbbbb,
+	.s27 = 0xcccccccc,
+	.s28 = 0xdddddddd,
+	.s29 = 0xeeeeeeee,
+	.s30 = 0xffffffff,
+	.s31 = 0x00000000,
 };
 
-static void load_fp_callee_saved_regs(
-	const volatile struct _preempt_float *regs)
+static void load_fp_callee_saved_regs(const volatile struct _preempt_float *regs)
 {
-	__asm__ volatile (
-		"vldmia %0, {s16-s31};\n\t"
-		:
-		: "r" (regs)
-		: "memory"
-		);
+	__asm__ volatile("vldmia %0, {s16-s31};\n\t" : : "r"(regs) : "memory");
 	barrier_dsync_fence_full();
 }
 
 static void verify_fp_callee_saved(const struct _preempt_float *src,
-		const struct _preempt_float *dst)
+				   const struct _preempt_float *dst)
 {
 	/* Verify FP callee-saved registers are as expected */
-	zassert_true((src->s16 == dst->s16)
-			&& (src->s17 == dst->s17)
-			&& (src->s18 == dst->s18)
-			&& (src->s19 == dst->s19)
-			&& (src->s20 == dst->s20)
-			&& (src->s21 == dst->s21)
-			&& (src->s22 == dst->s22)
-			&& (src->s23 == dst->s23)
-			&& (src->s24 == dst->s24)
-			&& (src->s25 == dst->s25)
-			&& (src->s26 == dst->s26)
-			&& (src->s27 == dst->s27)
-			&& (src->s28 == dst->s28)
-			&& (src->s29 == dst->s29)
-			&& (src->s30 == dst->s30)
-			&& (src->s31 == dst->s31),
-		" got: 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x"
-		" 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n"
-		" expected:  0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x"
-		" 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n",
-		(double)src->s16,
-		(double)src->s17,
-		(double)src->s18,
-		(double)src->s19,
-		(double)src->s20,
-		(double)src->s21,
-		(double)src->s22,
-		(double)src->s23,
-		(double)src->s24,
-		(double)src->s25,
-		(double)src->s26,
-		(double)src->s27,
-		(double)src->s28,
-		(double)src->s29,
-		(double)src->s30,
-		(double)src->s31,
-		(double)dst->s16,
-		(double)dst->s17,
-		(double)dst->s18,
-		(double)dst->s19,
-		(double)dst->s20,
-		(double)dst->s21,
-		(double)dst->s22,
-		(double)dst->s23,
-		(double)dst->s24,
-		(double)dst->s25,
-		(double)dst->s26,
-		(double)dst->s27,
-		(double)dst->s28,
-		(double)dst->s29,
-		(double)dst->s30,
-		(double)dst->s31
-	);
+	/* clang-format off */
+	zassert_true((src->s16 == dst->s16) &&
+		     (src->s17 == dst->s17) && (src->s18 == dst->s18) &&
+		     (src->s19 == dst->s19) && (src->s20 == dst->s20) &&
+		     (src->s21 == dst->s21) && (src->s22 == dst->s22) &&
+		     (src->s23 == dst->s23) && (src->s24 == dst->s24) &&
+		     (src->s25 == dst->s25) && (src->s26 == dst->s26) &&
+		     (src->s27 == dst->s27) && (src->s28 == dst->s28) &&
+		     (src->s29 == dst->s29) && (src->s30 == dst->s30) &&
+		     (src->s31 == dst->s31),
+		     " got: 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x"
+		     " 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n"
+		     " expected:  0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x"
+		     " 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x 0x%0x\n",
+		     (double)src->s16, (double)src->s17, (double)src->s18, (double)src->s19,
+		     (double)src->s20, (double)src->s21, (double)src->s22, (double)src->s23,
+		     (double)src->s24, (double)src->s25, (double)src->s26, (double)src->s27,
+		     (double)src->s28, (double)src->s29, (double)src->s30, (double)src->s31,
+		     (double)dst->s16, (double)dst->s17, (double)dst->s18, (double)dst->s19,
+		     (double)dst->s20, (double)dst->s21, (double)dst->s22, (double)dst->s23,
+		     (double)dst->s24, (double)dst->s25, (double)dst->s26, (double)dst->s27,
+		     (double)dst->s28, (double)dst->s29, (double)dst->s30, (double)dst->s31);
+	/* clang-format on */
 }
 
 #else
@@ -226,91 +176,85 @@ static void alt_thread_entry(void *p1, void *p2, void *p3)
 	int init_flag, post_flag;
 
 	/* Lock interrupts to make sure we get preempted only when
-	 * it is required by the test */
+	 * it is required by the test
+	 */
 	(void)irq_lock();
 
 	init_flag = switch_flag;
 	zassert_true(init_flag == false,
-		"Alternative thread: switch flag not false on thread entry\n");
+		     "Alternative thread: switch flag not false on thread entry\n");
 
 	/* Set switch flag */
 	switch_flag = true;
 
 #if defined(CONFIG_NO_OPTIMIZATIONS)
 	zassert_true(p_ztest_thread->arch.basepri == 0,
-		"ztest thread basepri not preserved in swap-out\n");
+		     "ztest thread basepri not preserved in swap-out\n");
 #else
 	/* Verify that the main test thread has the correct value
 	 * for state variable thread.arch.basepri (set before swap).
 	 */
 	zassert_true(p_ztest_thread->arch.basepri == BASEPRI_MODIFIED_1,
-		"ztest thread basepri not preserved in swap-out\n");
+		     "ztest thread basepri not preserved in swap-out\n");
 
 	/* Verify original swap return value (set by arch_swap() */
 	zassert_true(p_ztest_thread->arch.swap_return_value == -EAGAIN,
-		"ztest thread swap-return-value not preserved in swap-out\n");
+		     "ztest thread swap-return-value not preserved in swap-out\n");
 #endif
 
 	/* Verify that the main test thread (ztest) has stored the callee-saved
 	 * registers properly in its corresponding callee-saved container.
 	 */
-	verify_callee_saved(
-		(const _callee_saved_t *)&p_ztest_thread->callee_saved,
-		&ztest_thread_callee_saved_regs_container);
+	verify_callee_saved((const _callee_saved_t *)&p_ztest_thread->callee_saved,
+			    &ztest_thread_callee_saved_regs_container);
 
 	/* Zero the container of the callee-saved registers, to validate,
 	 * later, that it is populated properly.
 	 */
-	memset(&ztest_thread_callee_saved_regs_container,
-		0, sizeof(_callee_saved_t));
+	memset(&ztest_thread_callee_saved_regs_container, 0, sizeof(_callee_saved_t));
 
 #if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
 
 	/*  Verify that the _current_ (alt) thread is initialized with FPCA cleared. */
 	zassert_true((__get_CONTROL() & CONTROL_FPCA_Msk) == 0,
-		"CONTROL.FPCA is not cleared at initialization: 0x%x\n",
-		__get_CONTROL());
+		     "CONTROL.FPCA is not cleared at initialization: 0x%x\n", __get_CONTROL());
 
 	/* Verify that the _current_ (alt) thread is
 	 * initialized with EXC_RETURN.Ftype set
 	 */
 	zassert_true((_current->arch.mode_exc_return & EXC_RETURN_FTYPE) != 0,
-		"Alt thread FPCA flag not clear at initialization\n");
+		     "Alt thread FPCA flag not clear at initialization\n");
 #if defined(CONFIG_MPU_STACK_GUARD)
 	/* Alt thread is created with K_FP_REGS set, so we
 	 * expect lazy stacking and long guard to be enabled.
 	 */
-	zassert_true((_current->arch.mode &
-		Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0,
-		"Alt thread MPU GUAR DFLOAT flag not set at initialization\n");
+	zassert_true((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0,
+		     "Alt thread MPU GUAR DFLOAT flag not set at initialization\n");
 	zassert_true((_current->base.user_options & K_FP_REGS) != 0,
-		"Alt thread K_FP_REGS not set at initialization\n");
+		     "Alt thread K_FP_REGS not set at initialization\n");
 	zassert_true((FPU->FPCCR & FPU_FPCCR_LSPEN_Msk) != 0,
-		"Lazy FP Stacking not set at initialization\n");
+		     "Lazy FP Stacking not set at initialization\n");
 #endif
 
-
 	/* Verify that the _current_ (alt) thread is initialized with FPSCR cleared. */
 	zassert_true((__get_FPSCR() & FPSCR_MASK) == 0,
-		"(Alt thread) FPSCR is not cleared at initialization: 0x%x\n", __get_FPSCR());
+		     "(Alt thread) FPSCR is not cleared at initialization: 0x%x\n", __get_FPSCR());
 
 	zassert_true((p_ztest_thread->arch.mode_exc_return & EXC_RETURN_FTYPE) == 0,
-		"ztest thread mode Ftype flag not updated at swap-out: 0x%0x\n",
-		p_ztest_thread->arch.mode);
+		     "ztest thread mode Ftype flag not updated at swap-out: 0x%0x\n",
+		     p_ztest_thread->arch.mode);
 
 	/* Verify that the main test thread (ztest) has stored the FP
 	 *  callee-saved registers properly in its corresponding FP
 	 *  callee-saved container.
 	 */
-	verify_fp_callee_saved((const struct _preempt_float *)
-		&p_ztest_thread->arch.preempt_float,
-		&ztest_thread_fp_callee_saved_regs);
+	verify_fp_callee_saved((const struct _preempt_float *)&p_ztest_thread->arch.preempt_float,
+			       &ztest_thread_fp_callee_saved_regs);
 
 	/* Zero the container of the FP callee-saved registers, to validate,
 	 * later, that it is populated properly.
 	 */
-	memset(&ztest_thread_fp_callee_saved_regs,
-		0, sizeof(ztest_thread_fp_callee_saved_regs));
+	memset(&ztest_thread_fp_callee_saved_regs, 0, sizeof(ztest_thread_fp_callee_saved_regs));
 
 #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
 
@@ -336,7 +280,7 @@ static void alt_thread_entry(void *p1, void *p2, void *p3)
 	 * Note: preserve r7 register (frame pointer).
 	 */
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
-	__asm__ volatile (
+	__asm__ volatile(
 		/* Stash r4-r11 in stack, they will be restored much later in
 		 * another inline asm -- that should be reworked since stack
 		 * must be balanced when we leave any inline asm. We could
@@ -373,21 +317,18 @@ static void alt_thread_entry(void *p1, void *p2, void *p3)
 		"pop {r0, r7};\n\t"
 
 		: /* no output */
-		: "r" (&ztest_thread_callee_saved_regs_container)
-		: "memory", "r0", "r2", "r3"
-	);
+		: "r"(&ztest_thread_callee_saved_regs_container)
+		: "memory", "r0", "r2", "r3");
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-	__asm__ volatile (
-		"push {v1-v8};\n\t"
-		"push {r0, r1};\n\t"
-		"mov r0, r7;\n\t"
-		"ldmia %0, {v1-v8};\n\t"
-		"mov r7, r0;\n\t"
-		"pop {r0, r1};\n\t"
-		: /* no output */
-		: "r" (&ztest_thread_callee_saved_regs_container)
-		: "memory", "r0"
-	);
+	__asm__ volatile("push {v1-v8};\n\t"
+			 "push {r0, r1};\n\t"
+			 "mov r0, r7;\n\t"
+			 "ldmia %0, {v1-v8};\n\t"
+			 "mov r7, r0;\n\t"
+			 "pop {r0, r1};\n\t"
+			 : /* no output */
+			 : "r"(&ztest_thread_callee_saved_regs_container)
+			 : "memory", "r0");
 #endif
 
 	/* Manually trigger a context-switch, to swap-out
@@ -399,20 +340,17 @@ static void alt_thread_entry(void *p1, void *p2, void *p3)
 
 	/* Restore stacked callee-saved registers */
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
-	__asm__ volatile (
-		"pop {r4, r5, r6, r7};\n\t"
-		"mov r8, r4;\n\t"
-		"mov r9, r5;\n\t"
-		"mov r10, r6;\n\t"
-		"mov r11, r7;\n\t"
-		"pop {r4, r5, r6, r7};\n\t"
-		: : :
-	);
+	__asm__ volatile("pop {r4, r5, r6, r7};\n\t"
+			 "mov r8, r4;\n\t"
+			 "mov r9, r5;\n\t"
+			 "mov r10, r6;\n\t"
+			 "mov r11, r7;\n\t"
+			 "pop {r4, r5, r6, r7};\n\t"
+			 :
+			 :
+			 :);
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-	__asm__ volatile (
-		"pop {v1-v8};\n\t"
-		: : :
-	);
+	__asm__ volatile("pop {v1-v8};\n\t" : : :);
 #endif
 
 	/* Verify that the main test thread has managed to resume, before
@@ -422,7 +360,7 @@ static void alt_thread_entry(void *p1, void *p2, void *p3)
 	 */
 	post_flag = switch_flag;
 	zassert_true(post_flag == false,
-		"Alternative thread: switch flag not false on thread exit\n");
+		     "Alternative thread: switch flag not false on thread exit\n");
 }
 
 #if !defined(CONFIG_NO_OPTIMIZATIONS)
@@ -432,6 +370,10 @@ static int __noinline arch_swap_wrapper(void)
 }
 #endif
 
+/**
+ * @brief Test the ARM thread swap mechanism
+ * @ingroup kernel_arch_sched_tests
+ */
 ZTEST(arm_thread_swap, test_arm_thread_swap)
 {
 	int test_flag;
@@ -462,90 +404,77 @@ ZTEST(arm_thread_swap, test_arm_thread_swap)
 
 	/* Confirm initial conditions before starting the test. */
 	test_flag = switch_flag;
-	zassert_true(test_flag == false,
-		"Switch flag not initialized properly\n");
+	zassert_true(test_flag == false, "Switch flag not initialized properly\n");
 	zassert_true(_current->arch.basepri == 0,
-		"Thread BASEPRI flag not clear at thread start\n");
+		     "Thread BASEPRI flag not clear at thread start\n");
 	/* Verify, also, that the interrupts are unlocked. */
 #if defined(CONFIG_CPU_CORTEX_M_HAS_BASEPRI)
-	zassert_true(__get_BASEPRI() == 0,
-		"initial BASEPRI not zero\n");
+	zassert_true(__get_BASEPRI() == 0, "initial BASEPRI not zero\n");
 #else
 	/* For Cortex-M Baseline architecture, we verify that
 	 * the interrupt lock is disabled.
 	 */
-	 zassert_true(__get_PRIMASK() == 0,
-	 "initial PRIMASK not zero\n");
+	zassert_true(__get_PRIMASK() == 0, "initial PRIMASK not zero\n");
 #endif /* CONFIG_CPU_CORTEX_M_HAS_BASEPRI */
 
 #if defined(CONFIG_USERSPACE)
 	/* The main test thread is set to run in privilege mode */
 	zassert_false((arch_is_user_context()),
-		"Main test thread does not start in privilege mode\n");
+		      "Main test thread does not start in privilege mode\n");
 
 	/* Assert that the mode status variable indicates privilege mode */
 	zassert_true((_current->arch.mode & CONTROL_nPRIV_Msk) == 0,
-		"Thread nPRIV flag not clear for supervisor thread: 0x%0x\n",
-		_current->arch.mode);
+		     "Thread nPRIV flag not clear for supervisor thread: 0x%0x\n",
+		     _current->arch.mode);
 #endif /* CONFIG_USERSPACE */
 
 #if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
 	/* The main test thread is not (yet) actively using the FP registers */
 	zassert_true((_current->arch.mode_exc_return & EXC_RETURN_FTYPE) != 0,
-		"Thread Ftype flag not set at initialization 0x%0x\n",
-		_current->arch.mode);
+		     "Thread Ftype flag not set at initialization 0x%0x\n", _current->arch.mode);
 
 	/* Verify that the main test thread is initialized with FPCA cleared. */
 	zassert_true((__get_CONTROL() & CONTROL_FPCA_Msk) == 0,
-		"CONTROL.FPCA is not cleared at initialization: 0x%x\n",
-		__get_CONTROL());
+		     "CONTROL.FPCA is not cleared at initialization: 0x%x\n", __get_CONTROL());
 	/* Verify that the main test thread is initialized with FPSCR cleared. */
 	zassert_true((__get_FPSCR() & FPSCR_MASK) == 0,
-		"FPSCR is not cleared at initialization: 0x%x\n", __get_FPSCR());
+		     "FPSCR is not cleared at initialization: 0x%x\n", __get_FPSCR());
 
 	/* Clear the thread's floating-point callee-saved registers' container.
 	 * The container will, later, be populated by the swap mechanism.
 	 */
-	memset(&_current->arch.preempt_float, 0,
-		sizeof(struct _preempt_float));
+	memset(&_current->arch.preempt_float, 0, sizeof(struct _preempt_float));
 
 	/* Randomize the FP callee-saved registers at test initialization */
 	load_fp_callee_saved_regs(&ztest_thread_fp_callee_saved_regs);
 
 	/* Modify bit-0 of the FPSCR - will be checked again upon swap-in. */
-	zassert_true((__get_FPSCR() & 0x1) == 0,
-		"FPSCR bit-0 has been set before testing it\n");
+	zassert_true((__get_FPSCR() & 0x1) == 0, "FPSCR bit-0 has been set before testing it\n");
 	__set_FPSCR(__get_FPSCR() | 0x1);
 
 	/* The main test thread is using the FP registers, but the .mode
 	 * flag is not updated until the next context switch.
 	 */
 	zassert_true((_current->arch.mode_exc_return & EXC_RETURN_FTYPE) != 0,
-		"Thread Ftype flag not set at initialization\n");
+		     "Thread Ftype flag not set at initialization\n");
 #if defined(CONFIG_MPU_STACK_GUARD)
-	zassert_true((_current->arch.mode &
-		Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) == 0,
-		"Thread MPU GUAR DFLOAT flag not clear at initialization\n");
+	zassert_true((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) == 0,
+		     "Thread MPU GUAR DFLOAT flag not clear at initialization\n");
 	zassert_true((_current->base.user_options & K_FP_REGS) == 0,
-		"Thread K_FP_REGS not clear at initialization\n");
+		     "Thread K_FP_REGS not clear at initialization\n");
 	zassert_true((FPU->FPCCR & FPU_FPCCR_LSPEN_Msk) == 0,
-		"Lazy FP Stacking not clear at initialization\n");
+		     "Lazy FP Stacking not clear at initialization\n");
 #endif
 #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
 
 	/* Create an alternative (supervisor) testing thread */
-	k_thread_create(&alt_thread,
-		alt_thread_stack,
-		K_THREAD_STACK_SIZEOF(alt_thread_stack),
-		alt_thread_entry,
-		NULL, NULL, NULL,
-		K_PRIO_COOP(PRIORITY), ALT_THREAD_OPTIONS,
-		K_NO_WAIT);
+	k_thread_create(&alt_thread, alt_thread_stack, K_THREAD_STACK_SIZEOF(alt_thread_stack),
+			alt_thread_entry, NULL, NULL, NULL, K_PRIO_COOP(PRIORITY),
+			ALT_THREAD_OPTIONS, K_NO_WAIT);
 
 	/* Verify context-switch has not occurred. */
 	test_flag = switch_flag;
-	zassert_true(test_flag == false,
-		"Switch flag incremented when it should not have\n");
+	zassert_true(test_flag == false, "Switch flag incremented when it should not have\n");
 
 	/* Prepare to force a context switch to the alternative thread,
 	 * by manually adding the current thread to the end of the queue,
@@ -565,8 +494,7 @@ ZTEST(arm_thread_swap, test_arm_thread_swap)
 
 	/* Verify context-switch has not occurred yet. */
 	test_flag = switch_flag;
-	zassert_true(test_flag == false,
-		"Switch flag incremented by unexpected context-switch.\n");
+	zassert_true(test_flag == false, "Switch flag incremented by unexpected context-switch.\n");
 
 	/* Store the callee-saved registers to some global memory
 	 * accessible to the alternative testing thread. That
@@ -575,27 +503,24 @@ ZTEST(arm_thread_swap, test_arm_thread_swap)
 	 * registers' container.
 	 */
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
-	__asm__ volatile (
-		"push {r0, r1, r2, r3};\n\t"
-		"mov r1, %0;\n\t"
-		"stmia r1!, {r4-r7};\n\t"
-		"mov r2, r8;\n\t"
-		"mov r3, r9;\n\t"
-		"stmia r1!, {r2-r3};\n\t"
-		"mov r2, r10;\n\t"
-		"mov r3, r11;\n\t"
-		"stmia r1!, {r2-r3};\n\t"
-		"pop {r0, r1, r2, r3};\n\t"
-		:	: "r" (&ztest_thread_callee_saved_regs_container)
-		: "memory"
-	);
- #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-	__asm__ volatile (
-		"stmia %0, {v1-v8};\n\t"
-		:
-		: "r" (&ztest_thread_callee_saved_regs_container)
-		: "memory"
-	);
+	__asm__ volatile("push {r0, r1, r2, r3};\n\t"
+			 "mov r1, %0;\n\t"
+			 "stmia r1!, {r4-r7};\n\t"
+			 "mov r2, r8;\n\t"
+			 "mov r3, r9;\n\t"
+			 "stmia r1!, {r2-r3};\n\t"
+			 "mov r2, r10;\n\t"
+			 "mov r3, r11;\n\t"
+			 "stmia r1!, {r2-r3};\n\t"
+			 "pop {r0, r1, r2, r3};\n\t"
+			 :
+			 : "r"(&ztest_thread_callee_saved_regs_container)
+			 : "memory");
+#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+	__asm__ volatile("stmia %0, {v1-v8};\n\t"
+			 :
+			 : "r"(&ztest_thread_callee_saved_regs_container)
+			 : "memory");
 #endif
 
 	/* Manually trigger a context-switch to swap-out the current thread.
@@ -608,7 +533,7 @@ ZTEST(arm_thread_swap, test_arm_thread_swap)
 	irq_unlock(0);
 	/* The thread is now swapped-back in. */
 
-#else/* CONFIG_NO_OPTIMIZATIONS */
+#else /* CONFIG_NO_OPTIMIZATIONS */
 
 	/* Fake a different irq_unlock key when performing swap.
 	 * This will be verified by the alternative test thread.
@@ -622,27 +547,24 @@ ZTEST(arm_thread_swap, test_arm_thread_swap)
 
 	/* Dump callee-saved registers to memory. */
 #if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE)
-	__asm__ volatile (
-		"push {r0, r1, r2, r3};\n\t"
-		"mov r1, %0;\n\t"
-		"stmia r1!, {r4-r7};\n\t"
-		"mov r2, r8;\n\t"
-		"mov r3, r9;\n\t"
-		"stmia r1!, {r2-r3};\n\t"
-		"mov r2, r10;\n\t"
-		"mov r3, r11;\n\t"
-		"stmia r1!, {r2-r3};\n\t"
-		"pop {r0, r1, r2, r3};\n\t"
-		:	: "r" (&ztest_thread_callee_saved_regs_container)
-		: "memory"
-	);
- #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-	__asm__ volatile (
-		"stmia %0, {v1-v8};\n\t"
-		:
-		: "r" (&ztest_thread_callee_saved_regs_container)
-		: "memory"
-	);
+	__asm__ volatile("push {r0, r1, r2, r3};\n\t"
+			 "mov r1, %0;\n\t"
+			 "stmia r1!, {r4-r7};\n\t"
+			 "mov r2, r8;\n\t"
+			 "mov r3, r9;\n\t"
+			 "stmia r1!, {r2-r3};\n\t"
+			 "mov r2, r10;\n\t"
+			 "mov r3, r11;\n\t"
+			 "stmia r1!, {r2-r3};\n\t"
+			 "pop {r0, r1, r2, r3};\n\t"
+			 :
+			 : "r"(&ztest_thread_callee_saved_regs_container)
+			 : "memory");
+#elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
+	__asm__ volatile("stmia %0, {v1-v8};\n\t"
+			 :
+			 : "r"(&ztest_thread_callee_saved_regs_container)
+			 : "memory");
 #endif
 
 #if !defined(CONFIG_NO_OPTIMIZATIONS)
@@ -652,38 +574,30 @@ ZTEST(arm_thread_swap, test_arm_thread_swap)
 	 * used, as base register in the Store Multiple instruction.
 	 * We also enforce write-back to suppress assembler warning.
 	 */
-	__asm__ volatile (
-		"push {r0, r1, r2, r3, r4, r5, r6, r7};\n\t"
-		"stm %0!, {%1};\n\t"
-		"pop {r0, r1, r2, r3, r4, r5, r6, r7};\n\t"
-		:
-		: "r" (&ztest_swap_return_val), "r" (swap_return_val)
-		: "memory"
-	);
+	__asm__ volatile("push {r0, r1, r2, r3, r4, r5, r6, r7};\n\t"
+			 "stm %0!, {%1};\n\t"
+			 "pop {r0, r1, r2, r3, r4, r5, r6, r7};\n\t"
+			 :
+			 : "r"(&ztest_swap_return_val), "r"(swap_return_val)
+			 : "memory");
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
-	__asm__ volatile (
-		"stm %0, {%1};\n\t"
-		:
-		: "r" (&ztest_swap_return_val), "r" (swap_return_val)
-		: "memory"
-	);
+	__asm__ volatile("stm %0, {%1};\n\t"
+			 :
+			 : "r"(&ztest_swap_return_val), "r"(swap_return_val)
+			 : "memory");
 #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
 #endif
 
-
 	/* After swap-back, verify that the callee-saved registers loaded,
 	 * look exactly as what is located in the respective callee-saved
 	 * container of the thread.
 	 */
-	verify_callee_saved(
-		&ztest_thread_callee_saved_regs_container,
-		&_current->callee_saved);
+	verify_callee_saved(&ztest_thread_callee_saved_regs_container, &_current->callee_saved);
 
 	/* Verify context-switch did occur. */
 	test_flag = switch_flag;
-	zassert_true(test_flag == true,
-		"Switch flag not incremented as expected %u\n",
-		switch_flag);
+	zassert_true(test_flag == true, "Switch flag not incremented as expected %u\n",
+		     switch_flag);
 	/* Clear the switch flag to signal that the main test thread
 	 * has been successfully swapped-in, as expected by the test.
 	 */
@@ -694,72 +608,61 @@ ZTEST(arm_thread_swap, test_arm_thread_swap)
 	 * is now switched back in.
 	 */
 	zassert_true(_current->arch.basepri == 0,
-		"arch.basepri value not in accordance with the update\n");
+		     "arch.basepri value not in accordance with the update\n");
 
 #if defined(CONFIG_CPU_CORTEX_M_HAS_BASEPRI)
 	/* Verify that the BASEPRI register is updated during the last
 	 * swap-in of the thread.
 	 */
 	zassert_true(__get_BASEPRI() == BASEPRI_MODIFIED_2,
-		"BASEPRI not in accordance with the update: 0x%0x\n",
-		__get_BASEPRI());
+		     "BASEPRI not in accordance with the update: 0x%0x\n", __get_BASEPRI());
 #else
 	/* For Cortex-M Baseline architecture, we verify that
 	 * the interrupt lock is enabled.
 	 */
-	 zassert_true(__get_PRIMASK() != 0,
-	 "PRIMASK not in accordance with the update: 0x%0x\n",
-	 __get_PRIMASK());
+	zassert_true(__get_PRIMASK() != 0, "PRIMASK not in accordance with the update: 0x%0x\n",
+		     __get_PRIMASK());
 #endif /* CONFIG_CPU_CORTEX_M_HAS_BASEPRI */
 
 #if !defined(CONFIG_NO_OPTIMIZATIONS)
 	/* The thread is now swapped-back in. */
 	zassert_equal(_current->arch.swap_return_value, SWAP_RETVAL,
-		"Swap value not set as expected: 0x%x (0x%x)\n",
-		_current->arch.swap_return_value, SWAP_RETVAL);
+		      "Swap value not set as expected: 0x%x (0x%x)\n",
+		      _current->arch.swap_return_value, SWAP_RETVAL);
 	zassert_equal(_current->arch.swap_return_value, ztest_swap_return_val,
-		"Swap value not returned as expected 0x%x (0x%x)\n",
-		_current->arch.swap_return_value, ztest_swap_return_val);
+		      "Swap value not returned as expected 0x%x (0x%x)\n",
+		      _current->arch.swap_return_value, ztest_swap_return_val);
 #endif
 
 #if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
 	/* Dump callee-saved registers to memory. */
-	__asm__ volatile (
-		"vstmia %0, {s16-s31};\n\t"
-		:
-		: "r" (&ztest_thread_fp_callee_saved_regs)
-		: "memory"
-	);
+	__asm__ volatile("vstmia %0, {s16-s31};\n\t"
+			 :
+			 : "r"(&ztest_thread_fp_callee_saved_regs)
+			 : "memory");
 
 	/* After swap-back, verify that the FP callee-saved registers loaded,
 	 * look exactly as what is located in the respective FP callee-saved
 	 * container of the thread.
 	 */
-	verify_fp_callee_saved(
-		&ztest_thread_fp_callee_saved_regs,
-		&_current->arch.preempt_float);
+	verify_fp_callee_saved(&ztest_thread_fp_callee_saved_regs, &_current->arch.preempt_float);
 
 	/* Verify that the main test thread restored the FPSCR bit-0. */
-	zassert_true((__get_FPSCR() & 0x1) == 0x1,
-		"FPSCR bit-0 not restored at swap: 0x%x\n", __get_FPSCR());
+	zassert_true((__get_FPSCR() & 0x1) == 0x1, "FPSCR bit-0 not restored at swap: 0x%x\n",
+		     __get_FPSCR());
 
 	/* The main test thread is using the FP registers, and the .mode
 	 * flag and MPU GUARD flag are now updated.
 	 */
 	zassert_true((_current->arch.mode_exc_return & EXC_RETURN_FTYPE) == 0,
-		"Thread Ftype flag not cleared after main returned back\n");
+		     "Thread Ftype flag not cleared after main returned back\n");
 #if defined(CONFIG_MPU_STACK_GUARD)
-	zassert_true((_current->arch.mode &
-		Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0,
-		"Thread MPU GUARD FLOAT flag not set\n");
+	zassert_true((_current->arch.mode & Z_ARM_MODE_MPU_GUARD_FLOAT_Msk) != 0,
+		     "Thread MPU GUARD FLOAT flag not set\n");
 	zassert_true((_current->base.user_options & K_FP_REGS) != 0,
-		"Thread K_FPREGS not set after main returned back\n");
+		     "Thread K_FPREGS not set after main returned back\n");
 	zassert_true((FPU->FPCCR & FPU_FPCCR_LSPEN_Msk) != 0,
-		"Lazy FP Stacking not set after main returned back\n");
+		     "Lazy FP Stacking not set after main returned back\n");
 #endif
 #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */
-
 }
-/**
- * @}
- */
diff --git a/tests/arch/arm/arm_thread_swap_tz/src/main.c b/tests/arch/arm/arm_thread_swap_tz/src/main.c
index ebb18fafded..86cfd533317 100644
--- a/tests/arch/arm/arm_thread_swap_tz/src/main.c
+++ b/tests/arch/arm/arm_thread_swap_tz/src/main.c
@@ -10,7 +10,7 @@
 
 #ifndef EXC_RETURN_S
 /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */
-#define EXC_RETURN_S               (0x00000040UL)
+#define EXC_RETURN_S (0x00000040UL)
 #endif
 
 #define HASH_LEN 32
@@ -27,8 +27,8 @@ static void do_hash(char *hash)
 	size_t len;
 
 	/* Calculate correct hash. */
-	psa_status_t status = psa_hash_compute(PSA_ALG_SHA_256, dummy_string,
-			sizeof(dummy_string), hash, HASH_LEN, &len);
+	psa_status_t status = psa_hash_compute(PSA_ALG_SHA_256, dummy_string, sizeof(dummy_string),
+					       hash, HASH_LEN, &len);
 
 	zassert_equal(PSA_SUCCESS, status, "psa_hash_compute_fail: %d\n", status);
 	zassert_equal(HASH_LEN, len, "hash length not correct\n");
@@ -39,12 +39,12 @@ static void work_func(struct k_work *work)
 #ifdef CONFIG_ARM_NONSECURE_PREEMPTIBLE_SECURE_CALLS
 	/* Check that the main thread was executing in secure mode. */
 	zassert_true(main_thread->arch.mode_exc_return & EXC_RETURN_S,
-		"EXC_RETURN not secure: 0x%x\n", main_thread->arch.mode_exc_return);
+		     "EXC_RETURN not secure: 0x%x\n", main_thread->arch.mode_exc_return);
 
 #else
 	/* Check that the main thread was executing in nonsecure mode. */
 	zassert_false(main_thread->arch.mode_exc_return & EXC_RETURN_S,
-		"EXC_RETURN not nonsecure: 0x%x\n", main_thread->arch.mode_exc_return);
+		      "EXC_RETURN not nonsecure: 0x%x\n", main_thread->arch.mode_exc_return);
 #endif
 
 	work_done = true;
@@ -54,27 +54,23 @@ static void work_func(struct k_work *work)
 	 */
 #ifdef CONFIG_CPU_HAS_FPU
 	uint32_t clobber_val[16] = {
-		0xdeadbee0, 0xdeadbee1, 0xdeadbee2, 0xdeadbee3,
-		0xdeadbee4, 0xdeadbee5, 0xdeadbee6, 0xdeadbee7,
-		0xdeadbee8, 0xdeadbee9, 0xdeadbeea, 0xdeadbeeb,
+		0xdeadbee0, 0xdeadbee1, 0xdeadbee2, 0xdeadbee3, 0xdeadbee4, 0xdeadbee5,
+		0xdeadbee6, 0xdeadbee7, 0xdeadbee8, 0xdeadbee9, 0xdeadbeea, 0xdeadbeeb,
 		0xdeadbeec, 0xdeadbeed, 0xdeadbeee, 0xdeadbeef,
 	};
 
-	__asm__ volatile(
-		"vldmia %0, {s0-s15}\n"
-		"vldmia %0, {s16-s31}\n"
-		:: "r" (clobber_val) :
-	);
+	__asm__ volatile("vldmia %0, {s0-s15}\n"
+			 "vldmia %0, {s16-s31}\n" ::"r"(clobber_val)
+			 :);
 #endif /* CONFIG_CPU_HAS_FPU */
 
 	/* Call a secure service here as well, to test the added complexity of
 	 * calling secure services from two threads.
 	 */
-	psa_status_t status = psa_hash_compare(PSA_ALG_SHA_256, dummy_string,
-			sizeof(dummy_string), dummy_digest_correct, HASH_LEN);
+	psa_status_t status = psa_hash_compare(PSA_ALG_SHA_256, dummy_string, sizeof(dummy_string),
+					       dummy_digest_correct, HASH_LEN);
 
 	zassert_equal(PSA_SUCCESS, status, "psa_hash_compare failed\n");
-
 }
 
 ZTEST(thread_swap_tz, test_thread_swap_tz)
@@ -108,25 +104,22 @@ ZTEST(thread_swap_tz, test_thread_swap_tz)
 	 */
 #ifdef CONFIG_CPU_HAS_FPU
 	uint32_t test_val0[16] = {
-		0x1a2b3c40, 0x1a2b3c41, 0x1a2b3c42, 0x1a2b3c43,
-		0x1a2b3c44, 0x1a2b3c45, 0x1a2b3c46, 0x1a2b3c47,
-		0x1a2b3c48, 0x1a2b3c49, 0x1a2b3c4a, 0x1a2b3c4b,
+		0x1a2b3c40, 0x1a2b3c41, 0x1a2b3c42, 0x1a2b3c43, 0x1a2b3c44, 0x1a2b3c45,
+		0x1a2b3c46, 0x1a2b3c47, 0x1a2b3c48, 0x1a2b3c49, 0x1a2b3c4a, 0x1a2b3c4b,
 		0x1a2b3c4c, 0x1a2b3c4d, 0x1a2b3c4e, 0x1a2b3c4f,
 	};
 	uint32_t test_val1[16] = {
-		0x2b3c4d50, 0x2b3c4d51, 0x2b3c4d52, 0x2b3c4d53,
-		0x2b3c4d54, 0x2b3c4d55, 0x2b3c4d56, 0x2b3c4d57,
-		0x2b3c4d58, 0x2b3c4d59, 0x2b3c4d5a, 0x2b3c4d5b,
+		0x2b3c4d50, 0x2b3c4d51, 0x2b3c4d52, 0x2b3c4d53, 0x2b3c4d54, 0x2b3c4d55,
+		0x2b3c4d56, 0x2b3c4d57, 0x2b3c4d58, 0x2b3c4d59, 0x2b3c4d5a, 0x2b3c4d5b,
 		0x2b3c4d5c, 0x2b3c4d5d, 0x2b3c4d5e, 0x2b3c4d5f,
 	};
 	uint32_t test_val_res0[16];
 	uint32_t test_val_res1[16];
 
-	__asm__ volatile(
-		"vldmia %0, {s0-s15}\n"
-		"vldmia %1, {s16-s31}\n"
-		:: "r" (test_val0), "r" (test_val1) :
-	);
+	__asm__ volatile("vldmia %0, {s0-s15}\n"
+			 "vldmia %1, {s16-s31}\n" ::"r"(test_val0),
+			 "r"(test_val1)
+			 :);
 
 #endif /* CONFIG_CPU_HAS_FPU */
 
@@ -135,11 +128,10 @@ ZTEST(thread_swap_tz, test_thread_swap_tz)
 	zassert_true(work_done, "Interrupting work never happened\n");
 
 #ifdef CONFIG_CPU_HAS_FPU
-	__asm__ volatile(
-		"vstmia %0, {s0-s15}\n"
-		"vstmia %1, {s16-s31}\n"
-		:: "r" (test_val_res0), "r" (test_val_res1) :
-	);
+	__asm__ volatile("vstmia %0, {s0-s15}\n"
+			 "vstmia %1, {s16-s31}\n" ::"r"(test_val_res0),
+			 "r"(test_val_res1)
+			 :);
 
 	zassert_mem_equal(dummy_digest, dummy_digest_correct, HASH_LEN, NULL);
 	zassert_mem_equal(test_val0, test_val_res0, sizeof(test_val0), NULL);
diff --git a/tests/arch/arm/arm_tz_wrap_func/src/main.c b/tests/arch/arm/arm_tz_wrap_func/src/main.c
index 407873f906b..c100dfcd2f0 100644
--- a/tests/arch/arm/arm_tz_wrap_func/src/main.c
+++ b/tests/arch/arm/arm_tz_wrap_func/src/main.c
@@ -33,7 +33,6 @@ void reset_mocks(void)
 	foo1_arg4 = 0;
 }
 
-
 void preface(void)
 {
 	zassert_true(expect_preface, "%s unexpectedly called", __func__);
@@ -42,12 +41,10 @@ void preface(void)
 	expect_foo1 = true;
 }
 
-
 uint32_t foo1(uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t arg4)
 {
 	zassert_true(expect_foo1, "%s unexpectedly called", __func__);
-	zassert_equal(arg1, foo1_arg1, "Was 0x%"PRIx32", expected 0x%"PRIx32,
-		arg1, foo1_arg1);
+	zassert_equal(arg1, foo1_arg1, "Was 0x%" PRIx32 ", expected 0x%" PRIx32, arg1, foo1_arg1);
 	zassert_equal(arg2, foo1_arg2);
 	zassert_equal(arg3, foo1_arg3);
 	zassert_equal(arg4, foo1_arg4);
@@ -57,7 +54,6 @@ uint32_t foo1(uint32_t arg1, uint32_t arg2, uint32_t arg3, uint32_t arg4)
 	return foo1_retval;
 }
 
-
 void postface(void)
 {
 	zassert_true(expect_postface, "%s unexpectedly called", __func__);
@@ -65,14 +61,12 @@ void postface(void)
 	postface_called = true;
 }
 
-
-uint32_t __attribute__((naked)) wrap_foo1(uint32_t arg1, uint32_t arg2,
-				uint32_t arg3, uint32_t arg4)
+uint32_t __attribute__((naked)) wrap_foo1(uint32_t arg1, uint32_t arg2, uint32_t arg3,
+					  uint32_t arg4)
 {
 	__TZ_WRAP_FUNC(preface, foo1, postface);
 }
 
-
 ZTEST(tz_wrap_func, test_tz_wrap_func)
 {
 	reset_mocks();
@@ -86,8 +80,7 @@ ZTEST(tz_wrap_func, test_tz_wrap_func)
 	msp1 = __get_MSP();
 	psp1 = __get_PSP();
 
-	zassert_equal(foo1_retval,
-		wrap_foo1(foo1_arg1, foo1_arg2, foo1_arg3, foo1_arg4), NULL);
+	zassert_equal(foo1_retval, wrap_foo1(foo1_arg1, foo1_arg2, foo1_arg3, foo1_arg4), NULL);
 
 	zassert_equal(msp1, __get_MSP());
 	zassert_equal(psp1, __get_PSP());
diff --git a/tests/arch/arm64/arm64_high_addresses/testcase.yaml b/tests/arch/arm64/arm64_high_addresses/testcase.yaml
index 738a5311f6d..9b09f9745a6 100644
--- a/tests/arch/arm64/arm64_high_addresses/testcase.yaml
+++ b/tests/arch/arm64/arm64_high_addresses/testcase.yaml
@@ -1,5 +1,7 @@
 common:
   arch_allow: arm64
+  platform_exclude:
+    - rza3ul_smarc
   tags:
     - arm
     - userspace
diff --git a/tests/arch/common/ramfunc/src/ramfunc.c b/tests/arch/common/ramfunc/src/ramfunc.c
index cd55c653618..f76c511687d 100644
--- a/tests/arch/common/ramfunc/src/ramfunc.c
+++ b/tests/arch/common/ramfunc/src/ramfunc.c
@@ -53,6 +53,3 @@ ZTEST(ramfunc, test_ramfunc)
 	zassert_true(post_flag == 1,
 		"ram_function() execution failed.");
 }
-/**
- * @}
- */
diff --git a/tests/arch/common/ramfunc/testcase.yaml b/tests/arch/common/ramfunc/testcase.yaml
index 3fba2d86197..89c221511b5 100644
--- a/tests/arch/common/ramfunc/testcase.yaml
+++ b/tests/arch/common/ramfunc/testcase.yaml
@@ -1,6 +1,6 @@
 tests:
   arch.common.ramfunc:
-    filter: CONFIG_ARCH_HAS_RAMFUNC_SUPPORT
+    filter: CONFIG_ARCH_HAS_RAMFUNC_SUPPORT and not CONFIG_ARM_MPU_PXN
     tags:
       - arm
       - userspace
diff --git a/tests/arch/x86/cpu_scrubs_regs/testcase.yaml b/tests/arch/x86/cpu_scrubs_regs/testcase.yaml
index 4da93fa327e..ff52bdcc89c 100644
--- a/tests/arch/x86/cpu_scrubs_regs/testcase.yaml
+++ b/tests/arch/x86/cpu_scrubs_regs/testcase.yaml
@@ -8,3 +8,5 @@ tests:
       - userspace
       - scrub
       - registers
+    integration_platforms:
+      - qemu_x86
diff --git a/tests/arch/x86/info/src/timer.c b/tests/arch/x86/info/src/timer.c
index 85d4a72215c..aa28ba12a7c 100644
--- a/tests/arch/x86/info/src/timer.c
+++ b/tests/arch/x86/info/src/timer.c
@@ -44,7 +44,7 @@ void timer(void)
 	printk("TIMER: unknown");
 #endif
 
-	printk(", configured frequency = %dHz\n",
+	printk(", configured frequency = %uHz\n",
 		sys_clock_hw_cycles_per_sec());
 
 #if defined(CONFIG_COUNTER_CMOS)
diff --git a/tests/benchmarks/app_kernel/prj.conf b/tests/benchmarks/app_kernel/prj.conf
index 57cd1f1544e..ac968ba0fe9 100644
--- a/tests/benchmarks/app_kernel/prj.conf
+++ b/tests/benchmarks/app_kernel/prj.conf
@@ -16,9 +16,6 @@ CONFIG_CBPRINTF_FP_SUPPORT=y
 # Can only run under 1 CPU
 CONFIG_MP_MAX_NUM_CPUS=1
 
-# Enable pipes
-CONFIG_PIPES=y
-
 CONFIG_APPLICATION_DEFINED_SYSCALL=y
 CONFIG_TIMING_FUNCTIONS=y
 
diff --git a/tests/benchmarks/app_kernel/prj_user.conf b/tests/benchmarks/app_kernel/prj_user.conf
index fd222e6fb14..d64c95ecd8f 100644
--- a/tests/benchmarks/app_kernel/prj_user.conf
+++ b/tests/benchmarks/app_kernel/prj_user.conf
@@ -16,9 +16,6 @@ CONFIG_CBPRINTF_FP_SUPPORT=y
 # Can only run under 1 CPU
 CONFIG_MP_MAX_NUM_CPUS=1
 
-# Enable pipes
-CONFIG_PIPES=y
-
 CONFIG_APPLICATION_DEFINED_SYSCALL=y
 CONFIG_TIMING_FUNCTIONS=y
 CONFIG_USERSPACE=y
diff --git a/tests/benchmarks/app_kernel/src/pipe_b.c b/tests/benchmarks/app_kernel/src/pipe_b.c
index 3589b73806a..6c999fe7e2d 100644
--- a/tests/benchmarks/app_kernel/src/pipe_b.c
+++ b/tests/benchmarks/app_kernel/src/pipe_b.c
@@ -171,16 +171,10 @@ int pipeput(struct k_pipe *pipe,
 	for (i = 0; option == _1_TO_N || (i < count); i++) {
 		size_t sizexferd = 0;
 		size_t size2xfer = MIN(size, size2xfer_total - sizexferd_total);
-		int ret;
-		size_t mim_num_of_bytes = 0;
 
-		if (option == _ALL_N) {
-			mim_num_of_bytes = size2xfer;
-		}
-		ret = k_pipe_put(pipe, data_bench, size2xfer,
-				&sizexferd, mim_num_of_bytes, K_FOREVER);
+		sizexferd = k_pipe_write(pipe, data_bench, size2xfer, K_FOREVER);
 
-		if (ret != 0) {
+		if (sizexferd < 0) {
 			return 1;
 		}
 		if (option == _ALL_N && sizexferd != size2xfer) {
diff --git a/tests/benchmarks/app_kernel/src/pipe_r.c b/tests/benchmarks/app_kernel/src/pipe_r.c
index 653e66491fa..4385f79f881 100644
--- a/tests/benchmarks/app_kernel/src/pipe_r.c
+++ b/tests/benchmarks/app_kernel/src/pipe_r.c
@@ -95,12 +95,9 @@ int pipeget(struct k_pipe *pipe, enum pipe_options option, int size, int count,
 	for (i = 0; option == _1_TO_N || (i < count); i++) {
 		size_t sizexferd = 0;
 		size_t size2xfer = MIN(size, size2xfer_total - sizexferd_total);
-		int ret;
 
-		ret = k_pipe_get(pipe, data_recv, size2xfer,
-				 &sizexferd, option, K_FOREVER);
-
-		if (ret != 0) {
+		sizexferd = k_pipe_read(pipe, data_recv, size2xfer, K_FOREVER);
+		if (sizexferd  < 0) {
 			return 1;
 		}
 
diff --git a/tests/benchmarks/ipi_metric/CMakeLists.txt b/tests/benchmarks/ipi_metric/CMakeLists.txt
new file mode 100644
index 00000000000..6e39c1899d9
--- /dev/null
+++ b/tests/benchmarks/ipi_metric/CMakeLists.txt
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(ipi_metric)
+
+#FILE(GLOB app_sources src/*.c)
+#target_sources(app PRIVATE ${app_sources})
+target_sources_ifdef(
+  CONFIG_IPI_METRIC_PREEMPTIVE
+  app
+  PRIVATE
+  src/ipi_metric_preemptive.c
+  )
+target_sources_ifdef(
+  CONFIG_IPI_METRIC_PRIMITIVE_BROADCAST
+  app
+  PRIVATE
+  src/ipi_metric_primitive.c
+  )
+target_sources_ifdef(
+  CONFIG_IPI_METRIC_PRIMITIVE_DIRECTED
+  app
+  PRIVATE
+  src/ipi_metric_primitive.c
+  )
diff --git a/tests/benchmarks/ipi_metric/Kconfig b/tests/benchmarks/ipi_metric/Kconfig
new file mode 100644
index 00000000000..b605e59c268
--- /dev/null
+++ b/tests/benchmarks/ipi_metric/Kconfig
@@ -0,0 +1,37 @@
+# Copyright (c) 2024 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+mainmenu "IPI-Metric RTOS Test Suite"
+
+choice IPI_METRIC_TEST
+	prompt "Select an IPI-Metric test to execute"
+	default IPI_METRIC_PREEMPTIVE
+	help
+	  The IPI-Metric benchmark suite has a single CPU in an SMP system
+	  dedicated to generating IPIs under varying conditions while the
+	  remaining CPUs perform their "work" and process IPIs. These tests
+	  track the amount of "work" and the number of IPIs processed
+	  during 30 second time intervals.
+
+config IPI_METRIC_PREEMPTIVE
+	bool "IPIs are generated due threads preempting one another"
+	help
+	  The CPU generating the IPIs does so as a byproduct of resuming and
+	  suspending a series of preemptible threads.
+
+config IPI_METRIC_PRIMITIVE_BROADCAST
+	bool "IPIs are generated using primitive arch_sched_broadcast_ipi()"
+	help
+	  The CPU generating the IPIs does so by directly calling
+	  arch_sched_broadcast_ipi() to broadcast them to all CPUs.
+
+config IPI_METRIC_PRIMITIVE_DIRECTED
+	bool "IPIs are generated using primitive arch_sched_directed_ipi()"
+	depends on ARCH_HAS_DIRECTED_IPIS
+	help
+	  The CPU generating the IPIs does so by directly calling
+	  arch_sched_directed_ipi() to direct them to a single CPU.
+
+endchoice
+
+source "Kconfig.zephyr"
diff --git a/tests/benchmarks/ipi_metric/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf b/tests/benchmarks/ipi_metric/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf
new file mode 100644
index 00000000000..f0ee34b467e
--- /dev/null
+++ b/tests/benchmarks/ipi_metric/boards/qemu_cortex_a53_qemu_cortex_a53_smp.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MP_MAX_NUM_CPUS=4
diff --git a/tests/benchmarks/ipi_metric/boards/qemu_cortex_a53_qemu_cortex_a53_smp.overlay b/tests/benchmarks/ipi_metric/boards/qemu_cortex_a53_qemu_cortex_a53_smp.overlay
new file mode 100644
index 00000000000..5bb497069dd
--- /dev/null
+++ b/tests/benchmarks/ipi_metric/boards/qemu_cortex_a53_qemu_cortex_a53_smp.overlay
@@ -0,0 +1,19 @@
+/* Copyright 2022 Carlo Caione <ccaione@baylibre.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	cpus {
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <2>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a53";
+			reg = <3>;
+		};
+	};
+};
diff --git a/tests/benchmarks/ipi_metric/boards/qemu_x86_64.conf b/tests/benchmarks/ipi_metric/boards/qemu_x86_64.conf
new file mode 100644
index 00000000000..797559f4fd3
--- /dev/null
+++ b/tests/benchmarks/ipi_metric/boards/qemu_x86_64.conf
@@ -0,0 +1 @@
+CONFIG_MP_MAX_NUM_CPUS=4
diff --git a/tests/benchmarks/ipi_metric/boards/qemu_x86_64.overlay b/tests/benchmarks/ipi_metric/boards/qemu_x86_64.overlay
new file mode 100644
index 00000000000..7af73b4e405
--- /dev/null
+++ b/tests/benchmarks/ipi_metric/boards/qemu_x86_64.overlay
@@ -0,0 +1,15 @@
+/ {
+	cpus {
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "intel,x86_64";
+			reg = <2>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "intel,x86_64";
+			reg = <3>;
+		};
+	};
+};
diff --git a/tests/benchmarks/ipi_metric/prj.conf b/tests/benchmarks/ipi_metric/prj.conf
new file mode 100644
index 00000000000..a96be86ca33
--- /dev/null
+++ b/tests/benchmarks/ipi_metric/prj.conf
@@ -0,0 +1,31 @@
+# Default base configuration file
+
+# Use a tickless kernel to minimize the number of timer interrupts
+CONFIG_TICKLESS_KERNEL=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
+
+# Optimize for speed
+CONFIG_SPEED_OPTIMIZATIONS=y
+
+# Disable time slicing
+CONFIG_TIMESLICING=n
+
+# Disabling hardware stack protection can greatly
+# improve system performance.
+CONFIG_HW_STACK_PROTECTION=n
+
+# Picolibc is faster than Zephyr's minimal libc memcpy
+CONFIG_PICOLIBC_SPEED_OPTIMIZATIONS=y
+CONFIG_PICOLIBC_USE_MODULE=y
+
+# Disable Thread Local Storage for better context switching times
+CONFIG_THREAD_LOCAL_STORAGE=n
+
+# Disable memory slab pointer validation
+CONFIG_MEM_SLAB_POINTER_VALIDATE=n
+
+# Allow for the number of scheduling IPIs to be tracked
+CONFIG_TRACE_SCHED_IPI=y
+
+# Enable smarter delivery of scheduling IPIs
+CONFIG_IPI_OPTIMIZE=y
diff --git a/tests/benchmarks/ipi_metric/src/ipi_metric_preemptive.c b/tests/benchmarks/ipi_metric/src/ipi_metric_preemptive.c
new file mode 100644
index 00000000000..791f6f99611
--- /dev/null
+++ b/tests/benchmarks/ipi_metric/src/ipi_metric_preemptive.c
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2023,2024 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+
+#if CONFIG_MP_MAX_NUM_CPUS == 1
+#error "Test requires a system with more than 1 CPU"
+#endif
+
+#define IPI_TEST_INTERVAL_DURATION 30
+
+#define NUM_WORK_THREADS (CONFIG_MP_MAX_NUM_CPUS - 1)
+#define WORK_STACK_SIZE  4096
+
+#define NUM_PREEMPTIVE_THREADS 5
+#define PREEMPTIVE_STACK_SIZE 4096
+
+static K_THREAD_STACK_ARRAY_DEFINE(work_stack, NUM_WORK_THREADS, WORK_STACK_SIZE);
+static K_THREAD_STACK_ARRAY_DEFINE(preemptive_stack, NUM_PREEMPTIVE_THREADS, PREEMPTIVE_STACK_SIZE);
+
+static struct k_thread work_thread[NUM_WORK_THREADS];
+static unsigned long work_array[NUM_WORK_THREADS][1024];
+static volatile unsigned long work_counter[NUM_WORK_THREADS];
+
+static struct k_thread preemptive_thread[NUM_PREEMPTIVE_THREADS];
+static unsigned int preemptive_counter[NUM_PREEMPTIVE_THREADS];
+
+static atomic_t ipi_counter;
+
+void z_trace_sched_ipi(void)
+{
+	atomic_inc(&ipi_counter);
+}
+
+void work_entry(void *p1, void *p2, void *p3)
+{
+	unsigned int index = POINTER_TO_UINT(p1);
+	unsigned long *array = p2;
+	unsigned long counter;
+
+	while (1) {
+		for (unsigned int i = 0; i < 1024; i++) {
+			counter = work_counter[index]++;
+
+			array[i] = (array[i] + counter) ^ array[i];
+		}
+	}
+}
+
+void preemptive_entry(void *p1, void *p2, void *p3)
+{
+	unsigned int index = POINTER_TO_UINT(p1);
+
+	ARG_UNUSED(p2);
+	ARG_UNUSED(p3);
+
+	struct k_thread *suspend = NULL;
+	struct k_thread *resume = NULL;
+
+	if (index != (NUM_PREEMPTIVE_THREADS - 1)) {
+		resume = &preemptive_thread[index + 1];
+	}
+
+	if (index != 0) {
+		suspend = k_current_get();
+	}
+
+	while (1) {
+		if (resume != NULL) {
+			k_thread_resume(resume);
+		}
+
+		preemptive_counter[index]++;
+
+		if (suspend != NULL) {
+			k_thread_suspend(suspend);
+		}
+	}
+}
+
+void report(void)
+{
+	unsigned int elapsed_time = IPI_TEST_INTERVAL_DURATION;
+	unsigned long total_preempt;
+	unsigned long total_work;
+	unsigned long last_work_counter[NUM_WORK_THREADS] = {};
+	unsigned long last_preempt[NUM_PREEMPTIVE_THREADS] = {};
+	unsigned long tmp_work_counter[NUM_WORK_THREADS] = {};
+	unsigned long tmp_preempt[NUM_PREEMPTIVE_THREADS] = {};
+	unsigned int i;
+	unsigned int tmp_ipi_counter;
+
+	atomic_set(&ipi_counter, 0);
+
+	while (1) {
+		k_sleep(K_SECONDS(IPI_TEST_INTERVAL_DURATION));
+
+		/*
+		 * Get local copies of the counters to minimize
+		 * the impacts of delays from printf().
+		 */
+
+		total_work = 0;
+		for (i = 0; i < NUM_WORK_THREADS; i++) {
+			tmp_work_counter[i] = work_counter[i];
+			total_work += (tmp_work_counter[i] - last_work_counter[i]);
+		}
+
+		/* Sum the preemptive counters. */
+		total_preempt = 0;
+		for (i = 0; i < NUM_PREEMPTIVE_THREADS; i++) {
+			tmp_preempt[i] = preemptive_counter[i];
+			total_preempt += (tmp_preempt[i] - last_preempt[i]);
+		}
+
+		tmp_ipi_counter = (unsigned int)atomic_set(&ipi_counter, 0);
+
+		printf("**** IPI-Metric Basic Scheduling Test **** Elapsed Time: %u\n",
+		       elapsed_time);
+
+		printf("  Preemptive Counter Total: %lu\n", total_preempt);
+		for (i = 0; i < NUM_PREEMPTIVE_THREADS; i++) {
+			printf("    - Counter #%u: %lu\n",
+			       i, tmp_preempt[i] - last_preempt[i]);
+			last_preempt[i] = tmp_preempt[i];
+		}
+
+		printf("  IPI Count: %u\n", tmp_ipi_counter);
+
+		printf("  Total Work: %lu\n", total_work);
+
+		for (i = 0; i < NUM_WORK_THREADS; i++) {
+			printf("    - Work Counter #%u: %lu\n",
+			       i, tmp_work_counter[i] - last_work_counter[i]);
+			last_work_counter[i] = tmp_work_counter[i];
+		}
+
+		elapsed_time += IPI_TEST_INTERVAL_DURATION;
+	}
+}
+
+int main(void)
+{
+	unsigned int i;
+
+	for (i = 0; i < NUM_WORK_THREADS; i++) {
+		k_thread_create(&work_thread[i], work_stack[i],
+				WORK_STACK_SIZE, work_entry,
+				UINT_TO_POINTER(i), work_array[i], NULL,
+				-1, 0, K_NO_WAIT);
+	}
+
+	/*
+	 * Create the preemptive threads and switch them to
+	 * the suspended state.
+	 */
+
+	for (i = 0; i < NUM_PREEMPTIVE_THREADS; i++) {
+		k_thread_create(&preemptive_thread[i], preemptive_stack[i],
+				PREEMPTIVE_STACK_SIZE, preemptive_entry,
+				UINT_TO_POINTER(i), NULL, NULL,
+				10 - i, 0, K_FOREVER);
+		k_thread_suspend(&preemptive_thread[i]);
+		k_wakeup(&preemptive_thread[i]);
+	}
+
+	k_thread_resume(&preemptive_thread[0]);
+
+	report();
+}
diff --git a/tests/benchmarks/ipi_metric/src/ipi_metric_primitive.c b/tests/benchmarks/ipi_metric/src/ipi_metric_primitive.c
new file mode 100644
index 00000000000..871fea91f2b
--- /dev/null
+++ b/tests/benchmarks/ipi_metric/src/ipi_metric_primitive.c
@@ -0,0 +1,176 @@
+/*
+ * Copyright (c) 2025 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+
+#if CONFIG_MP_MAX_NUM_CPUS <= 1
+#error "Test requires a system with more than 1 CPU"
+#endif
+
+#define IPI_TEST_INTERVAL_DURATION 30
+
+#define NUM_WORK_THREADS (CONFIG_MP_MAX_NUM_CPUS - 1)
+#define WORK_STACK_SIZE  4096
+
+#define PRIMITIVE_STACK_SIZE 4096
+
+static K_THREAD_STACK_ARRAY_DEFINE(work_stack, NUM_WORK_THREADS, WORK_STACK_SIZE);
+static K_THREAD_STACK_DEFINE(primitive_stack, PRIMITIVE_STACK_SIZE);
+
+static struct k_thread work_thread[NUM_WORK_THREADS];
+static unsigned long work_array[NUM_WORK_THREADS][1024];
+static volatile unsigned long work_counter[NUM_WORK_THREADS];
+
+static struct k_thread primitive_thread;
+static volatile unsigned long primitives_issued;
+
+static atomic_t ipi_cpu_bitmap;
+
+void z_trace_sched_ipi(void)
+{
+	atomic_or(&ipi_cpu_bitmap, BIT(_current_cpu->id));
+}
+
+void work_entry(void *p1, void *p2, void *p3)
+{
+	unsigned int index = POINTER_TO_UINT(p1);
+	unsigned long *array = p2;
+	unsigned long counter;
+
+	while (1) {
+		for (unsigned int i = 0; i < 1024; i++) {
+			counter = work_counter[index]++;
+
+			array[i] = (array[i] + counter) ^ array[i];
+		}
+	}
+}
+
+void primitive_entry(void *p1, void *p2, void *p3)
+{
+	unsigned int desired_ipi_set;
+	unsigned int value;
+	int key;
+
+	ARG_UNUSED(p1);
+	ARG_UNUSED(p2);
+	ARG_UNUSED(p3);
+
+	/*
+	 * All other CPUs are executing cooperative threads and are not
+	 * expected to switch in a new thread. Select a CPU targeted for IPIs.
+	 */
+
+#ifdef CONFIG_IPI_METRIC_PRIMITIVE_DIRECTED
+	key = arch_irq_lock();
+	desired_ipi_set = (_current_cpu->id == 0) ? BIT(1) : BIT(0);
+	arch_irq_unlock(key);
+#else
+	desired_ipi_set = (1 << arch_num_cpus()) - 1;
+	key = arch_irq_lock();
+	desired_ipi_set ^= BIT(_current_cpu->id);
+	arch_irq_unlock(key);
+#endif
+
+	while (1) {
+		atomic_set(&ipi_cpu_bitmap, 0);
+#ifdef CONFIG_IPI_METRIC_PRIMITIVE_DIRECTED
+		arch_sched_directed_ipi(desired_ipi_set);
+#else
+		arch_sched_broadcast_ipi();
+#endif
+
+		primitives_issued++;
+
+		/*
+		 * Loop until all the expected CPUs have flagged that they
+		 * have processed the schedule IPI from above.
+		 */
+
+		while (1) {
+			value = (unsigned int)atomic_get(&ipi_cpu_bitmap);
+
+			/*
+			 * Note: z_trace_sched_ipi(), which is used to track
+			 * which CPUs processed an IPI, is not just called as a
+			 * result of the primitives arch_sched_directed_ipi()
+			 * or arch_sched_broadcast_ipi() above. Schedule IPIs
+			 * will also be sent when ticks are announced such as
+			 * when the k_sleep() in report() expires and this
+			 * benchmark can not control which CPUs will receive
+			 * those IPIs. To account for this, a mask is applied.
+			 */
+			if ((value & desired_ipi_set) == desired_ipi_set) {
+				break;
+			}
+
+			key = arch_irq_lock();
+			arch_spin_relax();
+			arch_irq_unlock(key);
+		}
+	}
+}
+
+void report(void)
+{
+	unsigned int elapsed_time = IPI_TEST_INTERVAL_DURATION;
+	unsigned int i;
+	unsigned long total;
+	unsigned long counter[NUM_WORK_THREADS];
+	unsigned long last_counter[NUM_WORK_THREADS] = {};
+	unsigned long last_issued = 0;
+	unsigned long interval_issued;
+
+	while (1) {
+		k_sleep(K_SECONDS(IPI_TEST_INTERVAL_DURATION));
+
+		total = 0;
+
+		for (i = 0; i < NUM_WORK_THREADS; i++) {
+			counter[i] = work_counter[i] - last_counter[i];
+			total += counter[i];
+			last_counter[i] = work_counter[i];
+		}
+
+		interval_issued = primitives_issued - last_issued;
+
+		printf("**** IPI-Metric %s IPI Test **** Elapsed Time: %u\n",
+		       IS_ENABLED(CONFIG_IPI_METRIC_PRIMITIVE_DIRECTED) ?
+		       "Directed" : "Broadcast", elapsed_time);
+
+		printf("  Schedule IPIs Issued: %lu\n", interval_issued);
+		last_issued = primitives_issued;
+
+		printf("  Total Work: %lu\n", total);
+		for (i = 0; i < NUM_WORK_THREADS; i++) {
+			printf("   - Work Counter #%u: %lu\n",
+			       i, counter[i]);
+		}
+
+		elapsed_time += IPI_TEST_INTERVAL_DURATION;
+	}
+}
+
+int main(void)
+{
+	unsigned int i;
+
+	for (i = 0; i < NUM_WORK_THREADS; i++) {
+		k_thread_create(&work_thread[i], work_stack[i],
+				WORK_STACK_SIZE, work_entry,
+				UINT_TO_POINTER(i), work_array[i], NULL,
+				-1, 0, K_NO_WAIT);
+	}
+
+	/* Create the primitive thread. */
+
+	k_thread_create(&primitive_thread, primitive_stack,
+			PRIMITIVE_STACK_SIZE, primitive_entry,
+			UINT_TO_POINTER(i), NULL, NULL,
+			10, 0, K_NO_WAIT);
+
+	report();
+}
diff --git a/tests/benchmarks/ipi_metric/testcase.yaml b/tests/benchmarks/ipi_metric/testcase.yaml
new file mode 100644
index 00000000000..38d1511dbdd
--- /dev/null
+++ b/tests/benchmarks/ipi_metric/testcase.yaml
@@ -0,0 +1,106 @@
+common:
+  platform_key:
+    - arch
+  tags:
+    - kernel
+    - benchmark
+  # Native platforms excluded as they are not relevant: These benchmarks run some kernel primitives
+  # in a loop during a predefined time counting how many times they execute. But in the POSIX arch,
+  # time does not pass while the CPU executes. So the benchmark just appears as if hung.
+  arch_exclude:
+    - posix
+  # some slow qemu_* excluded
+  platform_exclude:
+    - qemu_malta/qemu_malta
+    - qemu_malta/qemu_malta/be
+    - qemu_nios2
+  integration_platforms:
+    - qemu_x86_64
+    - qemu_cortex_a53/qemu_cortex_a53/smp
+  timeout: 300
+  filter: CONFIG_SMP and CONFIG_MP_MAX_NUM_CPUS > 1
+  harness: console
+
+tests:
+  benchmark.ipi_metric.preemptive.broadcast:
+    extra_configs:
+      - CONFIG_IPI_METRIC_PREEMPTIVE=y
+      - CONFIG_IPI_OPTIMIZE=n
+    harness_config:
+      type: multi_line
+      ordered: true
+      regex:
+        # Collect at least 3 measurements for each benchmark:
+        - "(.*) IPI-Metric(.+) Elapsed Time:[ ]*[0-9]+(.*)"
+        - "(.*)Preemptive Counter Total:[ ]*[0-9]+(.*)"
+        - "(.*)IPI Count:[ ]*[0-9]+(.*)"
+        - "(.*)Total Work:[ ]*[0-9]+(.*)"
+        - "(.*) IPI-Metric(.+) Elapsed Time:[ ]*[0-9]+(.*)"
+        - "(.*)Preemptive Counter Total:[ ]*[0-9]+(.*)"
+        - "(.*)IPI Count:[ ]*[0-9]+(.*)"
+        - "(.*)Total Work:[ ]*[0-9]+(.*)"
+        - "(.*) IPI-Metric(.+) Elapsed Time:[ ]*[0-9]+(.*)"
+        - "(.*)Preemptive Counter Total:[ ]*[0-9]+(.*)"
+        - "(.*)IPI Count:[ ]*[0-9]+(.*)"
+        - "(.*)Total Work:[ ]*[0-9]+(.*)"
+
+  benchmark.ipi_metric.preemptive.optimize:
+    extra_configs:
+      - CONFIG_IPI_METRIC_PREEMPTIVE=y
+      - CONFIG_IPI_OPTIMIZE=y
+    filter: ARCH_HAS_DIRECTED_IPIS
+    harness_config:
+      type: multi_line
+      ordered: true
+      regex:
+        # Collect at least 3 measurements for each benchmark:
+        - "(.*) IPI-Metric(.+) Elapsed Time:[ ]*[0-9]+(.*)"
+        - "(.*)Preemptive Counter Total:[ ]*[0-9]+(.*)"
+        - "(.*)IPI Count:[ ]*[0-9]+(.*)"
+        - "(.*)Total Work:[ ]*[0-9]+(.*)"
+        - "(.*) IPI-Metric(.+) Elapsed Time:[ ]*[0-9]+(.*)"
+        - "(.*)Preemptive Counter Total:[ ]*[0-9]+(.*)"
+        - "(.*)IPI Count:[ ]*[0-9]+(.*)"
+        - "(.*)Total Work:[ ]*[0-9]+(.*)"
+        - "(.*) IPI-Metric(.+) Elapsed Time:[ ]*[0-9]+(.*)"
+        - "(.*)Preemptive Counter Total:[ ]*[0-9]+(.*)"
+        - "(.*)IPI Count:[ ]*[0-9]+(.*)"
+        - "(.*)Total Work:[ ]*[0-9]+(.*)"
+
+  benchmark.ipi_metric.primitive.broadcast:
+    extra_configs:
+      - CONFIG_IPI_METRIC_PRIMITIVE_BROADCAST=y
+    harness_config:
+      type: multi_line
+      ordered: true
+      regex:
+        # Collect at least 3 measurements for each benchmark:
+        - "(.*) IPI-Metric(.+) Elapsed Time:[ ]*[0-9]+(.*)"
+        - "(.*)Schedule IPIs Issued:[ ]*[0-9]+(.*)"
+        - "(.*)Total Work:[ ]*[0-9]+(.*)"
+        - "(.*) IPI-Metric(.+) Elapsed Time:[ ]*[0-9]+(.*)"
+        - "(.*)Schedule IPIs Issued:[ ]*[0-9]+(.*)"
+        - "(.*)Total Work:[ ]*[0-9]+(.*)"
+        - "(.*) IPI-Metric(.+) Elapsed Time:[ ]*[0-9]+(.*)"
+        - "(.*)Schedule IPIs Issued:[ ]*[0-9]+(.*)"
+        - "(.*)Total Work:[ ]*[0-9]+(.*)"
+
+
+  benchmark.ipi_metric.primitive.directed:
+    extra_configs:
+      - CONFIG_IPI_METRIC_PRIMITIVE_DIRECTED=y
+    filter: ARCH_HAS_DIRECTED_IPIS
+    harness_config:
+      type: multi_line
+      ordered: true
+      regex:
+        # Collect at least 3 measurements for each benchmark:
+        - "(.*) IPI-Metric(.+) Elapsed Time:[ ]*[0-9]+(.*)"
+        - "(.*)Schedule IPIs Issued:[ ]*[0-9]+(.*)"
+        - "(.*)Total Work:[ ]*[0-9]+(.*)"
+        - "(.*) IPI-Metric(.+) Elapsed Time:[ ]*[0-9]+(.*)"
+        - "(.*)Schedule IPIs Issued:[ ]*[0-9]+(.*)"
+        - "(.*)Total Work:[ ]*[0-9]+(.*)"
+        - "(.*) IPI-Metric(.+) Elapsed Time:[ ]*[0-9]+(.*)"
+        - "(.*)Schedule IPIs Issued:[ ]*[0-9]+(.*)"
+        - "(.*)Total Work:[ ]*[0-9]+(.*)"
diff --git a/tests/benchmarks/latency_measure/README.rst b/tests/benchmarks/latency_measure/README.rst
index d665794dbf1..623adbf9976 100644
--- a/tests/benchmarks/latency_measure/README.rst
+++ b/tests/benchmarks/latency_measure/README.rst
@@ -73,7 +73,7 @@ Sample output of the benchmark using the defaults::
         fifo.get.free.immediate.kernel           - Free when getting data from FIFO (no ctx switch)   :     560 cycles ,     4666 ns :
         fifo.get.blocking.k_to_k                 - Get data from FIFO (w/ ctx switch)                 :     510 cycles ,     4257 ns :
         fifo.put.wake+ctx.k_to_k                 - Add data to FIFO (w/ ctx switch)                   :     590 cycles ,     4923 ns :
-        fifo.get.free.blocking.k_to_k            - Free when getting data from FIFO (w/ ctx siwtch)   :     510 cycles ,     4250 ns :
+        fifo.get.free.blocking.k_to_k            - Free when getting data from FIFO (w/ ctx switch)   :     510 cycles ,     4250 ns :
         fifo.put.alloc.wake+ctx.k_to_k           - Allocate to add data to FIFO (w/ ctx switch)       :     585 cycles ,     4875 ns :
         lifo.put.immediate.kernel                - Add data to LIFO (no ctx switch)                   :     214 cycles ,     1791 ns :
         lifo.get.immediate.kernel                - Get data from LIFO (no ctx switch)                 :     120 cycles ,     1008 ns :
@@ -82,7 +82,7 @@ Sample output of the benchmark using the defaults::
         lifo.get.blocking.k_to_k                 - Get data from LIFO (w/ ctx switch)                 :     502 cycles ,     4191 ns :
         lifo.put.wake+ctx.k_to_k                 - Add data to LIFO (w/ ctx switch)                   :     585 cycles ,     4875 ns :
         lifo.get.free.blocking.k_to_k            - Free when getting data from LIFO (w/ ctx switch)   :     513 cycles ,     4275 ns :
-        lifo.put.alloc.wake+ctx.k_to_k           - Allocate to add data to LIFO (w/ ctx siwtch)       :     585 cycles ,     4881 ns :
+        lifo.put.alloc.wake+ctx.k_to_k           - Allocate to add data to LIFO (w/ ctx switch)       :     585 cycles ,     4881 ns :
         events.post.immediate.kernel             - Post events (nothing wakes)                        :     225 cycles ,     1875 ns :
         events.set.immediate.kernel              - Set events (nothing wakes)                         :     230 cycles ,     1923 ns :
         events.wait.immediate.kernel             - Wait for any events (no ctx switch)                :     120 cycles ,     1000 ns :
@@ -126,7 +126,7 @@ Sample output of the benchmark with stack canaries enabled::
         fifo.get.free.immediate.kernel           - Free when getting data from FIFO (no ctx switch)   :    1230 cycles ,    10250 ns :
         fifo.get.blocking.k_to_k                 - Get data from FIFO (w/ ctx switch)                 :     868 cycles ,     7241 ns :
         fifo.put.wake+ctx.k_to_k                 - Add data to FIFO (w/ ctx switch)                   :     991 cycles ,     8259 ns :
-        fifo.get.free.blocking.k_to_k            - Free when getting data from FIFO (w/ ctx siwtch)   :     879 cycles ,     7325 ns :
+        fifo.get.free.blocking.k_to_k            - Free when getting data from FIFO (w/ ctx switch)   :     879 cycles ,     7325 ns :
         fifo.put.alloc.wake+ctx.k_to_k           - Allocate to add data to FIFO (w/ ctx switch)       :     990 cycles ,     8250 ns :
         lifo.put.immediate.kernel                - Add data to LIFO (no ctx switch)                   :     429 cycles ,     3582 ns :
         lifo.get.immediate.kernel                - Get data from LIFO (no ctx switch)                 :     320 cycles ,     2674 ns :
@@ -135,7 +135,7 @@ Sample output of the benchmark with stack canaries enabled::
         lifo.get.blocking.k_to_k                 - Get data from LIFO (w/ ctx switch)                 :     863 cycles ,     7199 ns :
         lifo.put.wake+ctx.k_to_k                 - Add data to LIFO (w/ ctx switch)                   :     985 cycles ,     8208 ns :
         lifo.get.free.blocking.k_to_k            - Free when getting data from LIFO (w/ ctx switch)   :     879 cycles ,     7325 ns :
-        lifo.put.alloc.wake+ctx.k_to_k           - Allocate to add data to LIFO (w/ ctx siwtch)       :     985 cycles ,     8208 ns :
+        lifo.put.alloc.wake+ctx.k_to_k           - Allocate to add data to LIFO (w/ ctx switch)       :     985 cycles ,     8208 ns :
         events.post.immediate.kernel             - Post events (nothing wakes)                        :     420 cycles ,     3501 ns :
         events.set.immediate.kernel              - Set events (nothing wakes)                         :     420 cycles ,     3501 ns :
         events.wait.immediate.kernel             - Wait for any events (no ctx switch)                :     280 cycles ,     2334 ns :
@@ -183,7 +183,7 @@ Sample output of the benchmark with object core enabled::
         fifo.get.free.immediate.kernel           - Free when getting data from FIFO (no ctx switch)   :     565 cycles ,     4708 ns :
         fifo.get.blocking.k_to_k                 - Get data from FIFO (w/ ctx switch)                 :     947 cycles ,     7899 ns :
         fifo.put.wake+ctx.k_to_k                 - Add data to FIFO (w/ ctx switch)                   :    1015 cycles ,     8458 ns :
-        fifo.get.free.blocking.k_to_k            - Free when getting data from FIFO (w/ ctx siwtch)   :     950 cycles ,     7923 ns :
+        fifo.get.free.blocking.k_to_k            - Free when getting data from FIFO (w/ ctx switch)   :     950 cycles ,     7923 ns :
         fifo.put.alloc.wake+ctx.k_to_k           - Allocate to add data to FIFO (w/ ctx switch)       :    1010 cycles ,     8416 ns :
         lifo.put.immediate.kernel                - Add data to LIFO (no ctx switch)                   :     226 cycles ,     1891 ns :
         lifo.get.immediate.kernel                - Get data from LIFO (no ctx switch)                 :     123 cycles ,     1033 ns :
@@ -192,7 +192,7 @@ Sample output of the benchmark with object core enabled::
         lifo.get.blocking.k_to_k                 - Get data from LIFO (w/ ctx switch)                 :     951 cycles ,     7932 ns :
         lifo.put.wake+ctx.k_to_k                 - Add data to LIFO (w/ ctx switch)                   :    1010 cycles ,     8416 ns :
         lifo.get.free.blocking.k_to_k            - Free when getting data from LIFO (w/ ctx switch)   :     959 cycles ,     7991 ns :
-        lifo.put.alloc.wake+ctx.k_to_k           - Allocate to add data to LIFO (w/ ctx siwtch)       :    1010 cycles ,     8422 ns :
+        lifo.put.alloc.wake+ctx.k_to_k           - Allocate to add data to LIFO (w/ ctx switch)       :    1010 cycles ,     8422 ns :
         events.post.immediate.kernel             - Post events (nothing wakes)                        :     210 cycles ,     1750 ns :
         events.set.immediate.kernel              - Set events (nothing wakes)                         :     230 cycles ,     1917 ns :
         events.wait.immediate.kernel             - Wait for any events (no ctx switch)                :     120 cycles ,     1000 ns :
@@ -265,13 +265,13 @@ Sample output of the benchmark with userspace enabled::
         fifo.get.free.immediate.user             - Free when getting data from FIFO (no ctx switch)   :    1440 cycles ,    12000 ns :
         fifo.get.blocking.k_to_k                 - Get data from FIFO (w/ ctx switch)                 :    1209 cycles ,    10082 ns :
         fifo.put.wake+ctx.k_to_k                 - Add data to FIFO (w/ ctx switch)                   :    1230 cycles ,    10250 ns :
-        fifo.get.free.blocking.k_to_k            - Free when getting data from FIFO (w/ ctx siwtch)   :    1210 cycles ,    10083 ns :
+        fifo.get.free.blocking.k_to_k            - Free when getting data from FIFO (w/ ctx switch)   :    1210 cycles ,    10083 ns :
         fifo.put.alloc.wake+ctx.k_to_k           - Allocate to add data to FIFO (w/ ctx switch)       :    1260 cycles ,    10500 ns :
-        fifo.get.free.blocking.u_to_k            - Free when getting data from FIFO (w/ ctx siwtch)   :    1745 cycles ,    14547 ns :
+        fifo.get.free.blocking.u_to_k            - Free when getting data from FIFO (w/ ctx switch)   :    1745 cycles ,    14547 ns :
         fifo.put.alloc.wake+ctx.k_to_u           - Allocate to add data to FIFO (w/ ctx switch)       :    1600 cycles ,    13333 ns :
-        fifo.get.free.blocking.k_to_u            - Free when getting data from FIFO (w/ ctx siwtch)   :    1550 cycles ,    12922 ns :
+        fifo.get.free.blocking.k_to_u            - Free when getting data from FIFO (w/ ctx switch)   :    1550 cycles ,    12922 ns :
         fifo.put.alloc.wake+ctx.u_to_k           - Allocate to add data to FIFO (w/ ctx switch)       :    1795 cycles ,    14958 ns :
-        fifo.get.free.blocking.u_to_u            - Free when getting data from FIFO (w/ ctx siwtch)   :    2084 cycles ,    17374 ns :
+        fifo.get.free.blocking.u_to_u            - Free when getting data from FIFO (w/ ctx switch)   :    2084 cycles ,    17374 ns :
         fifo.put.alloc.wake+ctx.u_to_u           - Allocate to add data to FIFO (w/ ctx switch)       :    2135 cycles ,    17791 ns :
         lifo.put.immediate.kernel                - Add data to LIFO (no ctx switch)                   :     234 cycles ,     1957 ns :
         lifo.get.immediate.kernel                - Get data from LIFO (no ctx switch)                 :     189 cycles ,     1582 ns :
@@ -282,13 +282,13 @@ Sample output of the benchmark with userspace enabled::
         lifo.get.blocking.k_to_k                 - Get data from LIFO (w/ ctx switch)                 :    1219 cycles ,    10166 ns :
         lifo.put.wake+ctx.k_to_k                 - Add data to LIFO (w/ ctx switch)                   :    1230 cycles ,    10250 ns :
         lifo.get.free.blocking.k_to_k            - Free when getting data from LIFO (w/ ctx switch)   :    1210 cycles ,    10083 ns :
-        lifo.put.alloc.wake+ctx.k_to_k           - Allocate to add data to LIFO (w/ ctx siwtch)       :    1260 cycles ,    10500 ns :
+        lifo.put.alloc.wake+ctx.k_to_k           - Allocate to add data to LIFO (w/ ctx switch)       :    1260 cycles ,    10500 ns :
         lifo.get.free.blocking.u_to_k            - Free when getting data from LIFO (w/ ctx switch)   :    1744 cycles ,    14541 ns :
-        lifo.put.alloc.wake+ctx.k_to_u           - Allocate to add data to LIFO (w/ ctx siwtch)       :    1595 cycles ,    13291 ns :
+        lifo.put.alloc.wake+ctx.k_to_u           - Allocate to add data to LIFO (w/ ctx switch)       :    1595 cycles ,    13291 ns :
         lifo.get.free.blocking.k_to_u            - Free when getting data from LIFO (w/ ctx switch)   :    1544 cycles ,    12874 ns :
-        lifo.put.alloc.wake+ctx.u_to_k           - Allocate to add data to LIFO (w/ ctx siwtch)       :    1795 cycles ,    14958 ns :
+        lifo.put.alloc.wake+ctx.u_to_k           - Allocate to add data to LIFO (w/ ctx switch)       :    1795 cycles ,    14958 ns :
         lifo.get.free.blocking.u_to_u            - Free when getting data from LIFO (w/ ctx switch)   :    2080 cycles ,    17339 ns :
-        lifo.put.alloc.wake+ctx.u_to_u           - Allocate to add data to LIFO (w/ ctx siwtch)       :    2130 cycles ,    17750 ns :
+        lifo.put.alloc.wake+ctx.u_to_u           - Allocate to add data to LIFO (w/ ctx switch)       :    2130 cycles ,    17750 ns :
         events.post.immediate.kernel             - Post events (nothing wakes)                        :     285 cycles ,     2375 ns :
         events.set.immediate.kernel              - Set events (nothing wakes)                         :     290 cycles ,     2417 ns :
         events.wait.immediate.kernel             - Wait for any events (no ctx switch)                :     235 cycles ,     1958 ns :
diff --git a/tests/benchmarks/latency_measure/src/fifo.c b/tests/benchmarks/latency_measure/src/fifo.c
index 6dd8ffc1824..482fe1a0b23 100644
--- a/tests/benchmarks/latency_measure/src/fifo.c
+++ b/tests/benchmarks/latency_measure/src/fifo.c
@@ -323,7 +323,7 @@ int fifo_blocking_ops(uint32_t num_iterations, uint32_t start_options,
 		 alt_options & K_USER ? "u" : "k",
 		 start_options & K_USER ? "u" : "k");
 	snprintf(description, sizeof(description),
-		 "%-40s - Free when getting data from FIFO (w/ ctx siwtch)", tag);
+		 "%-40s - Free when getting data from FIFO (w/ ctx switch)", tag);
 
 	cycles = timestamp.cycles;
 	PRINT_STATS_AVG(description, (uint32_t)cycles,
diff --git a/tests/benchmarks/latency_measure/src/lifo.c b/tests/benchmarks/latency_measure/src/lifo.c
index 2de1ba81681..259ee168a8d 100644
--- a/tests/benchmarks/latency_measure/src/lifo.c
+++ b/tests/benchmarks/latency_measure/src/lifo.c
@@ -335,7 +335,7 @@ int lifo_blocking_ops(uint32_t num_iterations, uint32_t start_options,
 		 start_options & K_USER ? "u" : "k",
 		 alt_options & K_USER ? "u" : "k");
 	snprintf(description, sizeof(description),
-		 "%-40s - Allocate to add data to LIFO (w/ ctx siwtch)", tag);
+		 "%-40s - Allocate to add data to LIFO (w/ ctx switch)", tag);
 	cycles = timestamp.cycles;
 	PRINT_STATS_AVG(description, (uint32_t)cycles,
 			num_iterations, false, "");
diff --git a/tests/benchmarks/latency_measure/testcase.yaml b/tests/benchmarks/latency_measure/testcase.yaml
index a56dc6dedb7..e2efb4e3978 100644
--- a/tests/benchmarks/latency_measure/testcase.yaml
+++ b/tests/benchmarks/latency_measure/testcase.yaml
@@ -19,7 +19,8 @@ tests:
     harness_config:
       type: one_line
       record:
-        regex: "(?P<metric>.*) - (?P<description>.*):(?P<cycles>.*) cycles ,(?P<nanoseconds>.*) ns"
+        regex:
+          - "(?P<metric>.*) - (?P<description>.*):(?P<cycles>.*) cycles ,(?P<nanoseconds>.*) ns"
       regex:
         - "PROJECT EXECUTION SUCCESSFUL"
 
@@ -35,7 +36,8 @@ tests:
     harness_config:
       type: one_line
       record:
-        regex: "(?P<metric>.*) - (?P<description>.*):(?P<cycles>.*) cycles ,(?P<nanoseconds>.*) ns"
+        regex:
+          - "(?P<metric>.*) - (?P<description>.*):(?P<cycles>.*) cycles ,(?P<nanoseconds>.*) ns"
       regex:
         - "PROJECT EXECUTION SUCCESSFUL"
 
@@ -53,7 +55,8 @@ tests:
     harness_config:
       type: one_line
       record:
-        regex: "(?P<metric>.*) - (?P<description>.*):(?P<cycles>.*) cycles ,(?P<nanoseconds>.*) ns"
+        regex:
+          - "(?P<metric>.*) - (?P<description>.*):(?P<cycles>.*) cycles ,(?P<nanoseconds>.*) ns"
       regex:
         - "PROJECT EXECUTION SUCCESSFUL"
 
@@ -75,6 +78,7 @@ tests:
     harness_config:
       type: one_line
       record:
-        regex: "(?P<metric>.*) - (?P<description>.*):(?P<cycles>.*) cycles ,(?P<nanoseconds>.*) ns"
+        regex:
+          - "(?P<metric>.*) - (?P<description>.*):(?P<cycles>.*) cycles ,(?P<nanoseconds>.*) ns"
       regex:
         - "PROJECT EXECUTION SUCCESSFUL"
diff --git a/tests/benchmarks/posix/threads/testcase.yaml b/tests/benchmarks/posix/threads/testcase.yaml
index 9a7f2084f47..e9798b76a86 100644
--- a/tests/benchmarks/posix/threads/testcase.yaml
+++ b/tests/benchmarks/posix/threads/testcase.yaml
@@ -14,7 +14,8 @@ common:
   harness_config:
     type: one_line
     record:
-      regex: "(?P<api>.*), ALL, (?P<time>.*), (?P<threads>.*), (?P<cores>.*), (?P<rate>.*)"
+      regex:
+        - "(?P<api>.*), ALL, (?P<time>.*), (?P<threads>.*), (?P<cores>.*), (?P<rate>.*)"
     regex:
       - "PROJECT EXECUTION SUCCESSFUL"
 tests:
diff --git a/tests/benchmarks/sched_queues/testcase.yaml b/tests/benchmarks/sched_queues/testcase.yaml
index a11d00443fe..e60bcb1fef2 100644
--- a/tests/benchmarks/sched_queues/testcase.yaml
+++ b/tests/benchmarks/sched_queues/testcase.yaml
@@ -16,7 +16,7 @@ common:
       - "PROJECT EXECUTION SUCCESSFUL"
     record:
       regex:
-        "REC: (?P<metric>.*) - (?P<description>.*):(?P<cycles>.*) cycles ,(?P<nanoseconds>.*) ns"
+        - "REC: (?P<metric>.*) - (?P<description>.*):(?P<cycles>.*) cycles ,(?P<nanoseconds>.*) ns"
   extra_configs:
     - CONFIG_BENCHMARK_RECORDING=y
 
diff --git a/tests/benchmarks/sys_kernel/prj.conf b/tests/benchmarks/sys_kernel/prj.conf
index b1a432d2f66..8b72155fbac 100644
--- a/tests/benchmarks/sys_kernel/prj.conf
+++ b/tests/benchmarks/sys_kernel/prj.conf
@@ -15,3 +15,9 @@ CONFIG_HW_STACK_PROTECTION=n
 
 # Can only run under 1 CPU
 CONFIG_MP_MAX_NUM_CPUS=1
+
+# for the k_malloc() test
+CONFIG_KERNEL_MEM_POOL=y
+CONFIG_HEAP_MEM_POOL_SIZE=8192
+CONFIG_SYS_HEAP_VALIDATE=n
+CONFIG_SYS_HEAP_RUNTIME_STATS=n
diff --git a/tests/benchmarks/sys_kernel/src/malloc.c b/tests/benchmarks/sys_kernel/src/malloc.c
new file mode 100644
index 00000000000..0c827e00e1b
--- /dev/null
+++ b/tests/benchmarks/sys_kernel/src/malloc.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2025 BayLibre SAS
+ *   *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "syskernel.h"
+
+static void *malloc_array[NUMBER_OF_LOOPS];
+
+static void do_malloc(int loops)
+{
+	int i;
+
+	for (i = 0; i < loops; i++) {
+		malloc_array[i] = k_malloc(1);
+	}
+}
+
+static void do_free(int loops)
+{
+	int i;
+
+	for (i = 0; i < loops; i++) {
+		k_free(malloc_array[i]);
+	}
+}
+
+int malloc_test(void)
+{
+	uint32_t t;
+	int return_value = 0;
+
+	fprintf(output_file, sz_test_case_fmt,
+		"malloc #1");
+	fprintf(output_file, sz_description,
+		"\n\tk_malloc");
+	printf(sz_test_start_fmt);
+
+	t = BENCH_START();
+	do_malloc(number_of_loops);
+	t = TIME_STAMP_DELTA_GET(t);
+
+	return_value += check_result(number_of_loops, t);
+
+	fprintf(output_file, sz_test_case_fmt,
+		"malloc #2");
+	fprintf(output_file, sz_description,
+		"\n\tk_free");
+	printf(sz_test_start_fmt);
+
+	t = BENCH_START();
+	do_free(number_of_loops);
+	t = TIME_STAMP_DELTA_GET(t);
+
+	return_value += check_result(number_of_loops, t);
+
+	return return_value;
+}
diff --git a/tests/benchmarks/sys_kernel/src/syskernel.c b/tests/benchmarks/sys_kernel/src/syskernel.c
index 19d2e84ca3c..a3b80a463e5 100644
--- a/tests/benchmarks/sys_kernel/src/syskernel.c
+++ b/tests/benchmarks/sys_kernel/src/syskernel.c
@@ -161,11 +161,12 @@ int main(void)
 		test_result += lifo_test();
 		test_result += fifo_test();
 		test_result += stack_test();
+		test_result += malloc_test();
 		test_result += mem_slab_test();
 
 		if (test_result) {
-			/* sema/lifo/fifo/stack/mem_slab account for 14 tests in total */
-			if (test_result == 14) {
+			/* sema/lifo/fifo/stack/malloc/mem_slab account for 16 tests in total */
+			if (test_result == 16) {
 				fprintf(output_file, sz_module_result_fmt,
 					sz_success);
 			} else {
diff --git a/tests/benchmarks/sys_kernel/src/syskernel.h b/tests/benchmarks/sys_kernel/src/syskernel.h
index 69fb0330933..f12c2ea21d7 100644
--- a/tests/benchmarks/sys_kernel/src/syskernel.h
+++ b/tests/benchmarks/sys_kernel/src/syskernel.h
@@ -56,6 +56,7 @@ int sema_test(void);
 int lifo_test(void);
 int fifo_test(void);
 int stack_test(void);
+int malloc_test(void);
 int mem_slab_test(void);
 void begin_test(void);
 
diff --git a/tests/benchmarks/thread_metric/Kconfig b/tests/benchmarks/thread_metric/Kconfig
index 37ecca6cd0e..72ebc3042df 100644
--- a/tests/benchmarks/thread_metric/Kconfig
+++ b/tests/benchmarks/thread_metric/Kconfig
@@ -3,8 +3,6 @@
 
 mainmenu "Eclipse ThreadX Thread-Metric RTOS Test Suite"
 
-source "Kconfig.zephyr"
-
 choice TM_TEST
 	prompt "Select a Thread-Metric test to execute"
 	default TM_PREEMPTIVE
@@ -81,3 +79,5 @@ config TM_SYNCHRONIZATION
 	  is reported every 30 seconds.
 
 endchoice
+
+source "Kconfig.zephyr"
diff --git a/tests/benchmarks/thread_metric/src/tm_cooperative_scheduling_test.c b/tests/benchmarks/thread_metric/src/tm_cooperative_scheduling_test.c
index 179c30f85da..7bac7aac182 100644
--- a/tests/benchmarks/thread_metric/src/tm_cooperative_scheduling_test.c
+++ b/tests/benchmarks/thread_metric/src/tm_cooperative_scheduling_test.c
@@ -80,13 +80,14 @@ int main(void)
 
 void tm_cooperative_scheduling_initialize(void)
 {
-
-	/* Create all 5 threads at priority 3.  */
-	tm_thread_create(0, 3, tm_cooperative_thread_0_entry);
-	tm_thread_create(1, 3, tm_cooperative_thread_1_entry);
-	tm_thread_create(2, 3, tm_cooperative_thread_2_entry);
-	tm_thread_create(3, 3, tm_cooperative_thread_3_entry);
-	tm_thread_create(4, 3, tm_cooperative_thread_4_entry);
+	int prio = CONFIG_MAIN_THREAD_PRIORITY;
+
+	/* Create all 5 threads at the same priority as the main thread.  */
+	tm_thread_create(0, prio, tm_cooperative_thread_0_entry);
+	tm_thread_create(1, prio, tm_cooperative_thread_1_entry);
+	tm_thread_create(2, prio, tm_cooperative_thread_2_entry);
+	tm_thread_create(3, prio, tm_cooperative_thread_3_entry);
+	tm_thread_create(4, prio, tm_cooperative_thread_4_entry);
 
 	/* Resume all 5 threads.  */
 	tm_thread_resume(0);
diff --git a/tests/benchmarks/thread_metric/src/tm_message_processing_test.c b/tests/benchmarks/thread_metric/src/tm_message_processing_test.c
index 4a6d3c0ae1e..3de30fab221 100644
--- a/tests/benchmarks/thread_metric/src/tm_message_processing_test.c
+++ b/tests/benchmarks/thread_metric/src/tm_message_processing_test.c
@@ -44,8 +44,8 @@
 /* Define the counters used in the demo application...  */
 
 unsigned long tm_message_processing_counter;
-unsigned long tm_message_sent[4];
-unsigned long tm_message_received[4];
+unsigned int tm_message_sent[4];
+unsigned int tm_message_received[4];
 
 /* Define the test thread prototypes.  */
 
@@ -102,10 +102,10 @@ void tm_message_processing_thread_0_entry(void *p1, void *p2, void *p3)
 
 	while (1) {
 		/* Send a message to the queue.  */
-		tm_queue_send(0, tm_message_sent);
+		tm_queue_send(0, (unsigned long *)tm_message_sent);
 
 		/* Receive a message from the queue.  */
-		tm_queue_receive(0, tm_message_received);
+		tm_queue_receive(0, (unsigned long *)tm_message_received);
 
 		/* Check for invalid message.  */
 		if (tm_message_received[3] != tm_message_sent[3]) {
diff --git a/tests/benchmarks/thread_metric/testcase.yaml b/tests/benchmarks/thread_metric/testcase.yaml
index dbe5f7442c7..43fef683dd0 100644
--- a/tests/benchmarks/thread_metric/testcase.yaml
+++ b/tests/benchmarks/thread_metric/testcase.yaml
@@ -9,8 +9,10 @@ common:
   # time does not pass while the CPU executes. So the benchmark just appears as if hung.
   arch_exclude:
     - posix
-  # qemu_nios2 excluded as it is slow
+  # some slow qemu_* excluded
   platform_exclude:
+    - qemu_malta/qemu_malta
+    - qemu_malta/qemu_malta/be
     - qemu_nios2
   integration_platforms:
     - qemu_x86
@@ -18,9 +20,22 @@ common:
   timeout: 300
   harness: console
   harness_config:
-    type: one_line
+    type: multi_line
+    ordered: true
     regex:
-      - "(.*) Relative Time: (.*)"
+      # Collect at least 3 measurements for each benchmark:
+      - "(.*) Thread-Metric(.+) Relative Time:[ ]*[0-9]+(.*)"
+      - "(.*)Time Period Total:[ ]*[0-9]+(.*)"
+      - "(.*) Thread-Metric(.+) Relative Time:[ ]*[0-9]+(.*)"
+      - "(.*)Time Period Total:[ ]*[0-9]+(.*)"
+      - "(.*) Thread-Metric(.+) Relative Time:[ ]*[0-9]+(.*)"
+      - "(.*)Time Period Total:[ ]*[0-9]+(.*)"
+    record:
+      regex:
+        - "Time Period Total:[ ]*(?P<total_time_period>[0-9]+)"
+        - "ERROR:[ ]*(?P<error_message>.*)"
+        - "[ ]+Average:(?P<error_details>.*)"
+      merge: true
 
 tests:
   benchmark.thread_metric.basic:
diff --git a/tests/benchmarks/thread_metric/thread_metric_readme.txt b/tests/benchmarks/thread_metric/thread_metric_readme.txt
index c2216ddb9b7..a4ab6a52a86 100644
--- a/tests/benchmarks/thread_metric/thread_metric_readme.txt
+++ b/tests/benchmarks/thread_metric/thread_metric_readme.txt
@@ -123,6 +123,27 @@ tm_memory_allocation_test.c                   Basic memory allocation test
 tm_porting_layer_zephyr.c                     Specific porting layer source
                                                  code for Zephyr
 
+2.5. Test execution with Twister tool
+
+When the test suite is executed by Twister it takes parameters from testcase.yaml
+file, in particular:
+
+    * check expected benchmark output presence at least three times to collect
+      measurements from 3 consequtive intervals for each of the benchmark tests.
+
+    * use 300 sec. timeout on each benchmark test from this suite;
+      it is expected to be at least twice bigger than normally needed
+      to collect measurements 3 times with 30 sec. intervals on most of the
+      platforms except some simulators.
+
+    * parse benchmark output to extract measurements and errors when
+      it happens e.g. on counters diverged from average; Twister records
+      this data in twister.json and recording.csv report files for analysis.
+
+For more details see Twister testcase.yaml documentation and 'harness_config:'
+parameters.
+
+
 3 Porting
 
 3.1 Porting Layer
@@ -216,7 +237,7 @@ measurement tests:
     of memory. If successful, a TM_SUCCESS is returned.
 
 
-2.2 Porting Requirements Checklist
+3.2 Porting Requirements Checklist
 
 The following requirements are made in order to ensure fair benchmarks
 are achieved on each RTOS performing the test:
diff --git a/tests/benchmarks/wait_queues/testcase.yaml b/tests/benchmarks/wait_queues/testcase.yaml
index cf7d091a4af..54abc350b5f 100644
--- a/tests/benchmarks/wait_queues/testcase.yaml
+++ b/tests/benchmarks/wait_queues/testcase.yaml
@@ -15,7 +15,7 @@ common:
       - "PROJECT EXECUTION SUCCESSFUL"
     record:
       regex:
-        "REC: (?P<metric>.*) - (?P<description>.*):(?P<cycles>.*) cycles ,(?P<nanoseconds>.*) ns"
+        - "REC: (?P<metric>.*) - (?P<description>.*):(?P<cycles>.*) cycles ,(?P<nanoseconds>.*) ns"
   extra_configs:
     - CONFIG_BENCHMARK_RECORDING=y
 
diff --git a/tests/bluetooth/audio/ascs/include/bap_unicast_server.h b/tests/bluetooth/audio/ascs/include/bap_unicast_server.h
index 09cd37d4293..2bbbf2163e6 100644
--- a/tests/bluetooth/audio/ascs/include/bap_unicast_server.h
+++ b/tests/bluetooth/audio/ascs/include/bap_unicast_server.h
@@ -6,7 +6,11 @@
 
 #ifndef MOCKS_BAP_UNICAST_SERVER_H_
 #define MOCKS_BAP_UNICAST_SERVER_H_
+#include <stddef.h>
+#include <stdint.h>
 
+#include <zephyr/bluetooth/audio/audio.h>
+#include <zephyr/bluetooth/conn.h>
 #include <zephyr/fff.h>
 #include <zephyr/bluetooth/audio/bap.h>
 
diff --git a/tests/bluetooth/audio/ascs/include/bap_unicast_server_expects.h b/tests/bluetooth/audio/ascs/include/bap_unicast_server_expects.h
index 3d642ed6867..7fc479432ae 100644
--- a/tests/bluetooth/audio/ascs/include/bap_unicast_server_expects.h
+++ b/tests/bluetooth/audio/ascs/include/bap_unicast_server_expects.h
@@ -8,6 +8,7 @@
 #define MOCKS_BAP_UNICAST_SERVER_EXPECTS_H_
 
 #include <zephyr/bluetooth/audio/bap.h>
+#include <zephyr/ztest_assert.h>
 
 #include "bap_unicast_server.h"
 #include "expects_util.h"
diff --git a/tests/bluetooth/audio/ascs/include/test_common.h b/tests/bluetooth/audio/ascs/include/test_common.h
index 23d4a5185ba..e7d304f8519 100644
--- a/tests/bluetooth/audio/ascs/include/test_common.h
+++ b/tests/bluetooth/audio/ascs/include/test_common.h
@@ -3,10 +3,13 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stdint.h>
 
 #include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gatt.h>
+#include <zephyr/bluetooth/iso.h>
+#include <zephyr/bluetooth/uuid.h>
 
 #define test_ase_snk_get(_num_ase, ...) test_ase_get(BT_UUID_ASCS_ASE_SNK, _num_ase, __VA_ARGS__)
 #define test_ase_src_get(_num_ase, ...) test_ase_get(BT_UUID_ASCS_ASE_SRC, _num_ase, __VA_ARGS__)
diff --git a/tests/bluetooth/audio/ascs/src/main.c b/tests/bluetooth/audio/ascs/src/main.c
index aca746650a2..0bac12d2d22 100644
--- a/tests/bluetooth/audio/ascs/src/main.c
+++ b/tests/bluetooth/audio/ascs/src/main.c
@@ -9,8 +9,12 @@
  */
 
 #include <errno.h>
+#include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
+
+#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/iso.h>
 #include <zephyr/fff.h>
 #include <zephyr/kernel.h>
 #include <zephyr/bluetooth/audio/audio.h>
@@ -20,10 +24,13 @@
 #include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/gatt.h>
 #include <zephyr/bluetooth/uuid.h>
+#include <zephyr/net_buf.h>
 #include <zephyr/sys/util_macro.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test.h>
+#include <sys/types.h>
 
 #include "assert.h"
-#include "ascs_internal.h"
 #include "bap_unicast_server.h"
 #include "bap_unicast_server_expects.h"
 #include "bap_stream.h"
@@ -32,11 +39,8 @@
 #include "gatt.h"
 #include "gatt_expects.h"
 #include "iso.h"
-#include "mock_kernel.h"
-#include "pacs.h"
 
 #include "test_common.h"
-#include "ztest_assert.h"
 
 DEFINE_FFF_GLOBALS;
 
@@ -193,7 +197,7 @@ ZTEST_F(ascs_test_suite, test_release_ase_on_callback_unregister)
 	/* Reset mock, as we expect ASE notification to be sent */
 	bt_gatt_notify_cb_reset();
 
-	/* Unregister the callbacks - whis will clean up the ASCS */
+	/* Unregister the callbacks - which will clean up the ASCS */
 	bt_bap_unicast_server_unregister_cb(&mock_bap_unicast_server_cb);
 
 	/* Expected to notify the upper layers */
diff --git a/tests/bluetooth/audio/ascs/src/test_ase_control_params.c b/tests/bluetooth/audio/ascs/src/test_ase_control_params.c
index 4f7d2a4c649..4eaa11b41b3 100644
--- a/tests/bluetooth/audio/ascs/src/test_ase_control_params.c
+++ b/tests/bluetooth/audio/ascs/src/test_ase_control_params.c
@@ -9,25 +9,28 @@
 
 #include <stdint.h>
 #include <stdlib.h>
+#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/iso.h>
+#include <zephyr/bluetooth/uuid.h>
 #include <zephyr/kernel.h>
+#include <zephyr/toolchain.h>
 #include <zephyr/types.h>
 #include <zephyr/bluetooth/audio/audio.h>
 #include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gatt.h>
 #include <zephyr/sys/util_macro.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test.h>
+#include <sys/types.h>
 
 #include "bap_unicast_server.h"
-#include "bap_unicast_server_expects.h"
 #include "bap_stream.h"
-#include "bap_stream_expects.h"
 #include "conn.h"
-#include "gatt.h"
 #include "gatt_expects.h"
 #include "iso.h"
 
 #include "test_common.h"
-#include "ztest_assert.h"
 
 struct test_ase_control_params_fixture {
 	struct bt_conn conn;
diff --git a/tests/bluetooth/audio/ascs/src/test_ase_register.c b/tests/bluetooth/audio/ascs/src/test_ase_register.c
index b784d62a5b8..d1ce486631f 100644
--- a/tests/bluetooth/audio/ascs/src/test_ase_register.c
+++ b/tests/bluetooth/audio/ascs/src/test_ase_register.c
@@ -28,10 +28,7 @@
 
 #include "assert.h"
 #include "bap_unicast_server.h"
-#include "bap_unicast_server_expects.h"
 #include "bap_stream.h"
-#include "bap_stream_expects.h"
-#include "conn.h"
 
 #include "test_common.h"
 
diff --git a/tests/bluetooth/audio/ascs/src/test_ase_state_transition.c b/tests/bluetooth/audio/ascs/src/test_ase_state_transition.c
index 763c5075f4e..f3a3d7ae92b 100644
--- a/tests/bluetooth/audio/ascs/src/test_ase_state_transition.c
+++ b/tests/bluetooth/audio/ascs/src/test_ase_state_transition.c
@@ -7,8 +7,17 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stdint.h>
 #include <stdlib.h>
+#include <string.h>
+
+#include <zephyr/bluetooth/audio/lc3.h>
+#include <zephyr/bluetooth/byteorder.h>
+#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/bluetooth/iso.h>
 #include <zephyr/kernel.h>
+#include <zephyr/sys/util.h>
 #include <zephyr/types.h>
 #include <zephyr/bluetooth/audio/audio.h>
 #include <zephyr/bluetooth/audio/bap.h>
@@ -16,14 +25,13 @@
 #include <zephyr/bluetooth/gatt.h>
 #include <zephyr/sys/util_macro.h>
 #include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test.h>
 
 #include "bap_unicast_server.h"
 #include "bap_unicast_server_expects.h"
 #include "bap_stream.h"
 #include "bap_stream_expects.h"
 #include "conn.h"
-#include "gatt.h"
-#include "gatt_expects.h"
 #include "iso.h"
 
 #include "test_common.h"
diff --git a/tests/bluetooth/audio/ascs/src/test_ase_state_transition_invalid.c b/tests/bluetooth/audio/ascs/src/test_ase_state_transition_invalid.c
index 4bfb6ac6fe0..cd0d9b8cd7b 100644
--- a/tests/bluetooth/audio/ascs/src/test_ase_state_transition_invalid.c
+++ b/tests/bluetooth/audio/ascs/src/test_ase_state_transition_invalid.c
@@ -7,23 +7,31 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stdint.h>
 #include <stdlib.h>
+#include <string.h>
+
+#include <zephyr/bluetooth/audio/lc3.h>
+#include <zephyr/bluetooth/byteorder.h>
+#include <zephyr/bluetooth/iso.h>
+#include <zephyr/bluetooth/uuid.h>
 #include <zephyr/kernel.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/sys/util.h>
 #include <zephyr/types.h>
 #include <zephyr/bluetooth/audio/audio.h>
 #include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gatt.h>
 #include <zephyr/sys/util_macro.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test.h>
+#include <sys/types.h>
 
 #include "bap_unicast_server.h"
-#include "bap_unicast_server_expects.h"
 #include "bap_stream.h"
-#include "bap_stream_expects.h"
 #include "conn.h"
-#include "gatt.h"
 #include "gatt_expects.h"
-#include "iso.h"
 
 #include "test_common.h"
 
diff --git a/tests/bluetooth/audio/ascs/src/test_common.c b/tests/bluetooth/audio/ascs/src/test_common.c
index 5136c154d28..ce139f3990d 100644
--- a/tests/bluetooth/audio/ascs/src/test_common.c
+++ b/tests/bluetooth/audio/ascs/src/test_common.c
@@ -3,7 +3,14 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-
+#include <stdarg.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#include <zephyr/bluetooth/att.h>
+#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/bluetooth/iso.h>
 #include <zephyr/fff.h>
 #include <zephyr/types.h>
 #include <zephyr/bluetooth/audio/audio.h>
@@ -12,10 +19,11 @@
 #include <zephyr/bluetooth/gatt.h>
 #include <zephyr/bluetooth/uuid.h>
 #include <zephyr/sys/util_macro.h>
+#include <zephyr/ztest_assert.h>
+#include <sys/types.h>
 
 #include "bap_unicast_server.h"
 #include "bap_stream.h"
-#include "gatt_expects.h"
 #include "conn.h"
 #include "gatt.h"
 #include "iso.h"
@@ -355,7 +363,7 @@ void test_preamble_state_releasing(struct bt_conn *conn, uint8_t ase_id,
 	test_preamble_state_streaming(conn, ase_id, stream, chan, source);
 	test_ase_control_client_release(conn, ase_id);
 
-	/* Reset the mocks espacially the function call count */
+	/* Reset the mocks especially the function call count */
 	mock_bap_unicast_server_cleanup();
 	mock_bt_iso_cleanup();
 	mock_bap_stream_cleanup();
diff --git a/tests/bluetooth/audio/ascs/uut/bap_unicast_client.c b/tests/bluetooth/audio/ascs/uut/bap_unicast_client.c
index ef9ac1328b8..0df39da1e35 100644
--- a/tests/bluetooth/audio/ascs/uut/bap_unicast_client.c
+++ b/tests/bluetooth/audio/ascs/uut/bap_unicast_client.c
@@ -3,8 +3,13 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stddef.h>
+#include <stdint.h>
 
+#include <zephyr/bluetooth/audio/audio.h>
 #include <zephyr/bluetooth/audio/bap.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/ztest_assert.h>
 
 bool bt_bap_ep_is_unicast_client(const struct bt_bap_ep *ep)
 {
diff --git a/tests/bluetooth/audio/ascs/uut/bap_unicast_server.c b/tests/bluetooth/audio/ascs/uut/bap_unicast_server.c
index 6d256d19822..6f4eb153a92 100644
--- a/tests/bluetooth/audio/ascs/uut/bap_unicast_server.c
+++ b/tests/bluetooth/audio/ascs/uut/bap_unicast_server.c
@@ -3,8 +3,13 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stddef.h>
+#include <stdint.h>
 
+#include <zephyr/bluetooth/audio/audio.h>
 #include <zephyr/bluetooth/audio/bap.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/fff.h>
 
 #include "bap_unicast_server.h"
 
diff --git a/tests/bluetooth/audio/bap_base/src/main.c b/tests/bluetooth/audio/bap_base/src/main.c
index f453b1c16b6..e080593c58f 100644
--- a/tests/bluetooth/audio/bap_base/src/main.c
+++ b/tests/bluetooth/audio/bap_base/src/main.c
@@ -6,9 +6,16 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stdint.h>
 #include <stdlib.h>
+#include <string.h>
+#include <errno.h>
 
+#include <zephyr/bluetooth/audio/audio.h>
 #include <zephyr/bluetooth/audio/bap.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test.h>
 #include <zephyr/fff.h>
 
 DEFINE_FFF_GLOBALS;
diff --git a/tests/bluetooth/audio/bap_broadcast_source/src/main.c b/tests/bluetooth/audio/bap_broadcast_source/src/main.c
index 31396ba9cfe..ee2d03a3643 100644
--- a/tests/bluetooth/audio/bap_broadcast_source/src/main.c
+++ b/tests/bluetooth/audio/bap_broadcast_source/src/main.c
@@ -6,7 +6,6 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <errno.h>
 #include <stdint.h>
 #include <stdlib.h>
 #include <string.h>
@@ -25,7 +24,6 @@
 
 #include "bap_broadcast_source.h"
 #include "bap_stream.h"
-#include "bap_stream_expects.h"
 #include "bluetooth.h"
 #include "expects_util.h"
 #include "ztest_assert.h"
diff --git a/tests/bluetooth/audio/bap_broadcast_source/src/test_callback_register.c b/tests/bluetooth/audio/bap_broadcast_source/src/test_callback_register.c
index 0e221a68551..5339b198f28 100644
--- a/tests/bluetooth/audio/bap_broadcast_source/src/test_callback_register.c
+++ b/tests/bluetooth/audio/bap_broadcast_source/src/test_callback_register.c
@@ -11,10 +11,10 @@
 
 #include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/fff.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test.h>
 
 #include "bap_broadcast_source.h"
-#include "ztest_assert.h"
-#include "ztest_test.h"
 
 #define FFF_GLOBALS
 
diff --git a/tests/bluetooth/audio/cap_commander/include/cap_commander.h b/tests/bluetooth/audio/cap_commander/include/cap_commander.h
index 6b19ce4ca02..9137c8945d0 100644
--- a/tests/bluetooth/audio/cap_commander/include/cap_commander.h
+++ b/tests/bluetooth/audio/cap_commander/include/cap_commander.h
@@ -7,6 +7,8 @@
 #ifndef MOCKS_CAP_COMMANDER_H_
 #define MOCKS_CAP_COMMANDER_H_
 
+#include <zephyr/bluetooth/audio/csip.h>
+#include <zephyr/bluetooth/conn.h>
 #include <zephyr/fff.h>
 #include <zephyr/bluetooth/audio/cap.h>
 
diff --git a/tests/bluetooth/audio/cap_commander/include/test_common.h b/tests/bluetooth/audio/cap_commander/include/test_common.h
index e1c2b4edbd7..ae08d3b6088 100644
--- a/tests/bluetooth/audio/cap_commander/include/test_common.h
+++ b/tests/bluetooth/audio/cap_commander/include/test_common.h
@@ -6,6 +6,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <zephyr/bluetooth/conn.h>
+
 #define BROADCAST_CODE "BroadcastCode"
 #define RANDOM_SRC_ID  0x55
 
diff --git a/tests/bluetooth/audio/cap_commander/src/main.c b/tests/bluetooth/audio/cap_commander/src/main.c
index a55a4442dae..d976be1f98a 100644
--- a/tests/bluetooth/audio/cap_commander/src/main.c
+++ b/tests/bluetooth/audio/cap_commander/src/main.c
@@ -5,13 +5,18 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-
+#include <errno.h>
 #include <stdlib.h>
+#include <string.h>
 
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/audio/cap.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/fff.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test.h>
 
-#include "bluetooth.h"
 #include "cap_commander.h"
 #include "conn.h"
 #include "expects_util.h"
diff --git a/tests/bluetooth/audio/cap_commander/src/test_broadcast_reception.c b/tests/bluetooth/audio/cap_commander/src/test_broadcast_reception.c
index d55d9abd4ba..cbb7be58867 100644
--- a/tests/bluetooth/audio/cap_commander/src/test_broadcast_reception.c
+++ b/tests/bluetooth/audio/cap_commander/src/test_broadcast_reception.c
@@ -5,21 +5,33 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-
+#include <errno.h>
+#include <stdint.h>
 #include <stdlib.h>
+#include <string.h>
 
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/audio/audio.h>
+#include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/audio/cap.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/fff.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/printk.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test.h>
 
-#include "bluetooth.h"
 #include "cap_commander.h"
 #include "conn.h"
 #include "expects_util.h"
 #include "cap_mocks.h"
 #include "test_common.h"
 
-#include <zephyr/logging/log.h>
-
 LOG_MODULE_REGISTER(bt_broadcast_reception_test, CONFIG_BT_CAP_COMMANDER_LOG_LEVEL);
 
 #define FFF_GLOBALS
@@ -435,8 +447,12 @@ ZTEST_F(cap_commander_test_broadcast_reception, test_commander_reception_start_i
 {
 	int err;
 
+	if (CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE >= UINT8_MAX) {
+		ztest_test_skip();
+	}
+
 	fixture->start_param.param[0].subgroups[0].metadata_len =
-		CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE + 1;
+		(uint8_t)(CONFIG_BT_AUDIO_CODEC_CFG_MAX_METADATA_SIZE + 1);
 
 	err = bt_cap_commander_broadcast_reception_start(&fixture->start_param);
 	zassert_equal(-EINVAL, err, "Unexpected return value %d", err);
diff --git a/tests/bluetooth/audio/cap_commander/src/test_cancel.c b/tests/bluetooth/audio/cap_commander/src/test_cancel.c
index f67fb435ffa..41b6fc348c2 100644
--- a/tests/bluetooth/audio/cap_commander/src/test_cancel.c
+++ b/tests/bluetooth/audio/cap_commander/src/test_cancel.c
@@ -5,13 +5,21 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-
+#include <errno.h>
 #include <stdlib.h>
+#include <string.h>
 
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/audio/cap.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/fff.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test.h>
 
-#include "bluetooth.h"
 #include "cap_commander.h"
 #include "conn.h"
 #include "expects_util.h"
diff --git a/tests/bluetooth/audio/cap_commander/src/test_common.c b/tests/bluetooth/audio/cap_commander/src/test_common.c
index e254694c7d9..e0c53ed1bc0 100644
--- a/tests/bluetooth/audio/cap_commander/src/test_common.c
+++ b/tests/bluetooth/audio/cap_commander/src/test_common.c
@@ -5,6 +5,8 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/hci_types.h>
 
 #include "cap_commander.h"
 #include "conn.h"
diff --git a/tests/bluetooth/audio/cap_commander/src/test_distribute_broadcast_code.c b/tests/bluetooth/audio/cap_commander/src/test_distribute_broadcast_code.c
index b9480d73e11..f05b95b6ab9 100644
--- a/tests/bluetooth/audio/cap_commander/src/test_distribute_broadcast_code.c
+++ b/tests/bluetooth/audio/cap_commander/src/test_distribute_broadcast_code.c
@@ -6,12 +6,18 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <errno.h>
 #include <stdlib.h>
+#include <string.h>
 
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/audio/cap.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/fff.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test.h>
 
-#include "bluetooth.h"
 #include "cap_commander.h"
 #include "conn.h"
 #include "expects_util.h"
@@ -19,6 +25,7 @@
 #include "test_common.h"
 
 #include <zephyr/logging/log.h>
+#include <zephyr/sys/util.h>
 
 LOG_MODULE_REGISTER(bt_distribute_broadcast_code, CONFIG_BT_CAP_COMMANDER_LOG_LEVEL);
 
diff --git a/tests/bluetooth/audio/cap_commander/src/test_micp.c b/tests/bluetooth/audio/cap_commander/src/test_micp.c
index 542a01fd371..fc72d3beeca 100644
--- a/tests/bluetooth/audio/cap_commander/src/test_micp.c
+++ b/tests/bluetooth/audio/cap_commander/src/test_micp.c
@@ -6,13 +6,19 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <errno.h>
 #include <stdlib.h>
+#include <string.h>
 
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/audio/cap.h>
 #include <zephyr/bluetooth/audio/micp.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/fff.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test.h>
 
-#include "bluetooth.h"
 #include "cap_commander.h"
 #include "conn.h"
 #include "expects_util.h"
diff --git a/tests/bluetooth/audio/cap_commander/src/test_vcp.c b/tests/bluetooth/audio/cap_commander/src/test_vcp.c
index b94b035b4aa..e2dd1c25aeb 100644
--- a/tests/bluetooth/audio/cap_commander/src/test_vcp.c
+++ b/tests/bluetooth/audio/cap_commander/src/test_vcp.c
@@ -5,14 +5,20 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-
+#include <errno.h>
 #include <stdlib.h>
+#include <string.h>
 
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/audio/cap.h>
 #include <zephyr/bluetooth/audio/vcp.h>
+#include <zephyr/bluetooth/audio/vocs.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/fff.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test.h>
 
-#include "bluetooth.h"
 #include "cap_commander.h"
 #include "conn.h"
 #include "expects_util.h"
diff --git a/tests/bluetooth/audio/cap_commander/uut/aics.c b/tests/bluetooth/audio/cap_commander/uut/aics.c
index 5a4960a4636..bb1fa71725f 100644
--- a/tests/bluetooth/audio/cap_commander/uut/aics.c
+++ b/tests/bluetooth/audio/cap_commander/uut/aics.c
@@ -5,8 +5,12 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stdint.h>
+#include <stddef.h>
 
 #include <zephyr/bluetooth/audio/aics.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/sys/util.h>
 
 static struct bt_aics {
 	bool active;
diff --git a/tests/bluetooth/audio/cap_commander/uut/bap_broadcast_assistant.c b/tests/bluetooth/audio/cap_commander/uut/bap_broadcast_assistant.c
index 1b07e731271..e3dc170edc2 100644
--- a/tests/bluetooth/audio/cap_commander/uut/bap_broadcast_assistant.c
+++ b/tests/bluetooth/audio/cap_commander/uut/bap_broadcast_assistant.c
@@ -3,11 +3,20 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-
-#include "zephyr/bluetooth/audio/bap.h"
-#include "test_common.h"
+#include <errno.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/audio/bap.h>
+#include <zephyr/bluetooth/iso.h>
+#include <zephyr/sys/slist.h>
+#include <zephyr/ztest_assert.h>
 
 #include "bap_broadcast_assistant.h"
+#include "test_common.h"
 
 static sys_slist_t broadcast_assistant_cbs = SYS_SLIST_STATIC_INIT(&broadcast_assistant_cbs);
 
diff --git a/tests/bluetooth/audio/cap_commander/uut/cap_commander.c b/tests/bluetooth/audio/cap_commander/uut/cap_commander.c
index 702618e1594..b1fe525a126 100644
--- a/tests/bluetooth/audio/cap_commander/uut/cap_commander.c
+++ b/tests/bluetooth/audio/cap_commander/uut/cap_commander.c
@@ -5,6 +5,9 @@
  */
 
 #include <zephyr/bluetooth/audio/cap.h>
+#include <zephyr/bluetooth/audio/csip.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/fff.h>
 
 #include "cap_commander.h"
 
diff --git a/tests/bluetooth/audio/cap_commander/uut/csip.c b/tests/bluetooth/audio/cap_commander/uut/csip.c
index ef7f9102c07..2cb7c5dbf61 100644
--- a/tests/bluetooth/audio/cap_commander/uut/csip.c
+++ b/tests/bluetooth/audio/cap_commander/uut/csip.c
@@ -5,8 +5,11 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stddef.h>
+#include <stdint.h>
 
 #include <zephyr/bluetooth/audio/csip.h>
+#include <zephyr/bluetooth/conn.h>
 
 static struct bt_csip_set_coordinator_cb *csip_cb;
 
diff --git a/tests/bluetooth/audio/cap_commander/uut/micp.c b/tests/bluetooth/audio/cap_commander/uut/micp.c
index 03f17d00c63..018eec42dea 100644
--- a/tests/bluetooth/audio/cap_commander/uut/micp.c
+++ b/tests/bluetooth/audio/cap_commander/uut/micp.c
@@ -5,8 +5,17 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <errno.h>
+#include <stddef.h>
+#include <string.h>
 
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/audio/aics.h>
 #include <zephyr/bluetooth/audio/micp.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
 
 static struct bt_micp_mic_ctlr_cb *micp_cb;
 
diff --git a/tests/bluetooth/audio/cap_commander/uut/vcp.c b/tests/bluetooth/audio/cap_commander/uut/vcp.c
index c47fd7035b5..0a0ea054237 100644
--- a/tests/bluetooth/audio/cap_commander/uut/vcp.c
+++ b/tests/bluetooth/audio/cap_commander/uut/vcp.c
@@ -5,8 +5,19 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <errno.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
 
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/audio/aics.h>
 #include <zephyr/bluetooth/audio/vcp.h>
+#include <zephyr/bluetooth/audio/vocs.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
 
 static struct bt_vcp_vol_ctlr_cb *vcp_cb;
 
diff --git a/tests/bluetooth/audio/cap_commander/uut/vocs.c b/tests/bluetooth/audio/cap_commander/uut/vocs.c
index 075bd69b825..0403ea8cb9a 100644
--- a/tests/bluetooth/audio/cap_commander/uut/vocs.c
+++ b/tests/bluetooth/audio/cap_commander/uut/vocs.c
@@ -5,8 +5,13 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stddef.h>
+#include <stdint.h>
 
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/audio/vocs.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/sys/util.h>
 
 static struct bt_vocs {
 	bool active;
diff --git a/tests/bluetooth/audio/cap_initiator/include/cap_initiator.h b/tests/bluetooth/audio/cap_initiator/include/cap_initiator.h
index 57104e7ef03..1e2aaf72746 100644
--- a/tests/bluetooth/audio/cap_initiator/include/cap_initiator.h
+++ b/tests/bluetooth/audio/cap_initiator/include/cap_initiator.h
@@ -6,6 +6,7 @@
 
 #ifndef MOCKS_CAP_INITIATOR_H_
 #define MOCKS_CAP_INITIATOR_H_
+#include <stdint.h>
 
 #include <zephyr/bluetooth/audio/cap.h>
 #include <zephyr/bluetooth/audio/csip.h>
diff --git a/tests/bluetooth/audio/cap_initiator/src/test_common.c b/tests/bluetooth/audio/cap_initiator/src/test_common.c
index fc8d2b10ae2..d671d93d264 100644
--- a/tests/bluetooth/audio/cap_initiator/src/test_common.c
+++ b/tests/bluetooth/audio/cap_initiator/src/test_common.c
@@ -11,6 +11,8 @@
 #include <zephyr/bluetooth/audio/cap.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/fff.h>
+#include <zephyr/sys/printk.h>
 
 #include "bap_endpoint.h"
 #include "cap_initiator.h"
diff --git a/tests/bluetooth/audio/cap_initiator/src/test_unicast_stop.c b/tests/bluetooth/audio/cap_initiator/src/test_unicast_stop.c
index 50175f588d0..a3342a6bc4e 100644
--- a/tests/bluetooth/audio/cap_initiator/src/test_unicast_stop.c
+++ b/tests/bluetooth/audio/cap_initiator/src/test_unicast_stop.c
@@ -21,6 +21,7 @@
 #include <zephyr/fff.h>
 #include <zephyr/sys/slist.h>
 #include <zephyr/sys/util.h>
+#include <zephyr/ztest_assert.h>
 #include <sys/errno.h>
 
 #include "bap_endpoint.h"
diff --git a/tests/bluetooth/audio/cap_initiator/uut/bap_unicast_client.c b/tests/bluetooth/audio/cap_initiator/uut/bap_unicast_client.c
index 649d431b764..5a8994f36cd 100644
--- a/tests/bluetooth/audio/cap_initiator/uut/bap_unicast_client.c
+++ b/tests/bluetooth/audio/cap_initiator/uut/bap_unicast_client.c
@@ -16,11 +16,11 @@
 #include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/sys/printk.h>
 #include <zephyr/sys/slist.h>
+#include <zephyr/ztest_assert.h>
 #include <sys/errno.h>
 
 #include "bap_endpoint.h"
 #include "bap_iso.h"
-#include "ztest_assert.h"
 
 static struct bt_bap_unicast_client_cb *unicast_client_cb;
 
diff --git a/tests/bluetooth/audio/cap_initiator/uut/cap_initiator.c b/tests/bluetooth/audio/cap_initiator/uut/cap_initiator.c
index 78dea5f4685..9c67f6dd989 100644
--- a/tests/bluetooth/audio/cap_initiator/uut/cap_initiator.c
+++ b/tests/bluetooth/audio/cap_initiator/uut/cap_initiator.c
@@ -3,6 +3,7 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stdint.h>
 
 #include <zephyr/bluetooth/audio/cap.h>
 #include <zephyr/bluetooth/audio/csip.h>
diff --git a/tests/bluetooth/audio/ccp_call_control_client/CMakeLists.txt b/tests/bluetooth/audio/ccp_call_control_client/CMakeLists.txt
new file mode 100644
index 00000000000..05e846d7878
--- /dev/null
+++ b/tests/bluetooth/audio/ccp_call_control_client/CMakeLists.txt
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+project(bluetooth_ccp)
+find_package(Zephyr COMPONENTS unittest HINTS $ENV{ZEPHYR_BASE})
+
+add_subdirectory(${ZEPHYR_BASE}/tests/bluetooth/audio/ccp_call_control_client/uut uut)
+
+target_link_libraries(testbinary PRIVATE uut)
+
+target_include_directories(testbinary PRIVATE include)
+
+target_sources(testbinary
+  PRIVATE
+    src/main.c
+)
diff --git a/tests/bluetooth/audio/ccp_call_control_client/include/ccp_call_control_client.h b/tests/bluetooth/audio/ccp_call_control_client/include/ccp_call_control_client.h
new file mode 100644
index 00000000000..998c9f99852
--- /dev/null
+++ b/tests/bluetooth/audio/ccp_call_control_client/include/ccp_call_control_client.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef MOCKS_CCP_CALL_CONTROL_CLIENT_H_
+#define MOCKS_CCP_CALL_CONTROL_CLIENT_H_
+
+#include <stdint.h>
+
+#include <zephyr/bluetooth/audio/ccp.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/fff.h>
+
+extern struct bt_ccp_call_control_client_cb mock_ccp_call_control_client_cb;
+
+void mock_ccp_call_control_client_init(void);
+void mock_ccp_call_control_client_cleanup(void);
+
+DECLARE_FAKE_VOID_FUNC(mock_ccp_call_control_client_discover_cb,
+		       struct bt_ccp_call_control_client *, int,
+		       struct bt_ccp_call_control_client_bearers *);
+
+#endif /* MOCKS_CCP_CALL_CONTROL_CLIENT_H_ */
diff --git a/tests/bluetooth/audio/ccp_call_control_client/prj.conf b/tests/bluetooth/audio/ccp_call_control_client/prj.conf
new file mode 100644
index 00000000000..5f0f8a3f2a9
--- /dev/null
+++ b/tests/bluetooth/audio/ccp_call_control_client/prj.conf
@@ -0,0 +1,21 @@
+CONFIG_ZTEST=y
+
+CONFIG_BT=y
+CONFIG_BT_EXT_ADV=y
+CONFIG_BT_SMP=y
+CONFIG_BT_PERIPHERAL=y
+CONFIG_BT_GATT_CLIENT=y
+CONFIG_BT_GATT_AUTO_DISCOVER_CCC=y
+CONFIG_BT_AUDIO=y
+CONFIG_BT_CCP_CALL_CONTROL_CLIENT=y
+CONFIG_BT_CCP_CALL_CONTROL_CLIENT_BEARER_COUNT=2
+CONFIG_BT_TBS_CLIENT_TBS=y
+CONFIG_BT_TBS_CLIENT_GTBS=y
+CONFIG_UTF8=y
+
+CONFIG_ASSERT=y
+CONFIG_ASSERT_LEVEL=2
+CONFIG_ASSERT_VERBOSE=y
+
+CONFIG_LOG=y
+CONFIG_BT_CCP_CALL_CONTROL_CLIENT_LOG_LEVEL_DBG=y
diff --git a/tests/bluetooth/audio/ccp_call_control_client/src/main.c b/tests/bluetooth/audio/ccp_call_control_client/src/main.c
new file mode 100644
index 00000000000..c23d6ed592b
--- /dev/null
+++ b/tests/bluetooth/audio/ccp_call_control_client/src/main.c
@@ -0,0 +1,236 @@
+/* main.c - Application main entry point */
+
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/audio/ccp.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/fff.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/ztest_test.h>
+#include <zephyr/ztest_assert.h>
+
+#include "conn.h"
+#include "ccp_call_control_client.h"
+#include "expects_util.h"
+
+DEFINE_FFF_GLOBALS;
+
+struct ccp_call_control_client_test_suite_fixture {
+	/** Need 1 additional bearer than the max to trigger some corner cases */
+	struct bt_ccp_call_control_client_bearer
+		*bearers[CONFIG_BT_CCP_CALL_CONTROL_CLIENT_BEARER_COUNT + 1];
+	struct bt_ccp_call_control_client *client;
+	struct bt_conn conn;
+};
+
+static void mock_init_rule_before(const struct ztest_unit_test *test, void *fixture)
+{
+	mock_ccp_call_control_client_init();
+}
+
+static void mock_destroy_rule_after(const struct ztest_unit_test *test, void *fixture)
+{
+	mock_ccp_call_control_client_cleanup();
+}
+
+ZTEST_RULE(mock_rule, mock_init_rule_before, mock_destroy_rule_after);
+
+static void test_conn_init(struct bt_conn *conn)
+{
+	conn->index = 0;
+	conn->info.type = BT_CONN_TYPE_LE;
+	conn->info.role = BT_CONN_ROLE_CENTRAL;
+	conn->info.state = BT_CONN_STATE_CONNECTED;
+	conn->info.security.level = BT_SECURITY_L2;
+	conn->info.security.enc_key_size = BT_ENC_KEY_SIZE_MAX;
+	conn->info.security.flags = BT_SECURITY_FLAG_OOB | BT_SECURITY_FLAG_SC;
+
+	mock_bt_conn_connected(conn, BT_HCI_ERR_SUCCESS);
+}
+
+static void *ccp_call_control_client_test_suite_setup(void)
+{
+	struct ccp_call_control_client_test_suite_fixture *fixture;
+
+	fixture = malloc(sizeof(*fixture));
+	zassert_not_null(fixture);
+
+	return fixture;
+}
+
+static void ccp_call_control_client_test_suite_before(void *f)
+{
+	struct ccp_call_control_client_test_suite_fixture *fixture = f;
+
+	memset(fixture, 0, sizeof(*fixture));
+	test_conn_init(&fixture->conn);
+}
+
+static void ccp_call_control_client_test_suite_after(void *f)
+{
+	struct ccp_call_control_client_test_suite_fixture *fixture = f;
+
+	(void)bt_ccp_call_control_client_unregister_cb(&mock_ccp_call_control_client_cb);
+	mock_bt_conn_disconnected(&fixture->conn, BT_HCI_ERR_REMOTE_USER_TERM_CONN);
+}
+
+static void ccp_call_control_client_test_suite_teardown(void *f)
+{
+	free(f);
+}
+
+ZTEST_SUITE(ccp_call_control_client_test_suite, NULL, ccp_call_control_client_test_suite_setup,
+	    ccp_call_control_client_test_suite_before, ccp_call_control_client_test_suite_after,
+	    ccp_call_control_client_test_suite_teardown);
+
+static ZTEST_F(ccp_call_control_client_test_suite, test_ccp_call_control_client_register_cb)
+{
+	int err;
+
+	err = bt_ccp_call_control_client_register_cb(&mock_ccp_call_control_client_cb);
+	zassert_equal(0, err, "Unexpected return value %d", err);
+}
+
+static ZTEST_F(ccp_call_control_client_test_suite,
+	       test_ccp_call_control_client_register_cb_inval_param_null)
+{
+	int err;
+
+	err = bt_ccp_call_control_client_register_cb(NULL);
+	zassert_equal(-EINVAL, err, "Unexpected return value %d", err);
+}
+
+static ZTEST_F(ccp_call_control_client_test_suite,
+	       test_ccp_call_control_client_register_cb_inval_double_register)
+{
+	int err;
+
+	err = bt_ccp_call_control_client_register_cb(&mock_ccp_call_control_client_cb);
+	zassert_equal(0, err, "Unexpected return value %d", err);
+
+	err = bt_ccp_call_control_client_register_cb(&mock_ccp_call_control_client_cb);
+	zassert_equal(-EEXIST, err, "Unexpected return value %d", err);
+}
+
+static ZTEST_F(ccp_call_control_client_test_suite, test_ccp_call_control_client_unregister_cb)
+{
+	int err;
+
+	err = bt_ccp_call_control_client_register_cb(&mock_ccp_call_control_client_cb);
+	zassert_equal(0, err, "Unexpected return value %d", err);
+
+	err = bt_ccp_call_control_client_unregister_cb(&mock_ccp_call_control_client_cb);
+	zassert_equal(0, err, "Unexpected return value %d", err);
+}
+
+static ZTEST_F(ccp_call_control_client_test_suite,
+	       test_ccp_call_control_client_unregister_cb_inval_param_null)
+{
+	int err;
+
+	err = bt_ccp_call_control_client_unregister_cb(NULL);
+	zassert_equal(-EINVAL, err, "Unexpected return value %d", err);
+}
+
+static ZTEST_F(ccp_call_control_client_test_suite,
+	       test_ccp_call_control_client_unregister_cb_inval_double_unregister)
+{
+	int err;
+
+	err = bt_ccp_call_control_client_register_cb(&mock_ccp_call_control_client_cb);
+	zassert_equal(0, err, "Unexpected return value %d", err);
+
+	err = bt_ccp_call_control_client_unregister_cb(&mock_ccp_call_control_client_cb);
+	zassert_equal(0, err, "Unexpected return value %d", err);
+
+	err = bt_ccp_call_control_client_unregister_cb(&mock_ccp_call_control_client_cb);
+	zassert_equal(-EALREADY, err, "Unexpected return value %d", err);
+}
+
+static ZTEST_F(ccp_call_control_client_test_suite, test_ccp_call_control_client_discover)
+{
+	int err;
+
+	err = bt_ccp_call_control_client_register_cb(&mock_ccp_call_control_client_cb);
+	zassert_equal(0, err, "Unexpected return value %d", err);
+
+	err = bt_ccp_call_control_client_discover(&fixture->conn, &fixture->client);
+	zassert_equal(0, err, "Unexpected return value %d", err);
+
+	/* Validate that we got the callback with valid values */
+	zexpect_call_count("bt_ccp_call_control_client_cb.discover", 1,
+			   mock_ccp_call_control_client_discover_cb_fake.call_count);
+	zassert_not_null(mock_ccp_call_control_client_discover_cb_fake.arg0_history[0]);
+	zassert_equal(0, mock_ccp_call_control_client_discover_cb_fake.arg1_history[0]);
+	zassert_not_null(mock_ccp_call_control_client_discover_cb_fake.arg2_history[0]);
+
+#if defined(CONFIG_BT_TBS_CLIENT_GTBS)
+	zassert_not_null(
+		mock_ccp_call_control_client_discover_cb_fake.arg2_history[0]->gtbs_bearer);
+#endif /* CONFIG_BT_TBS_CLIENT_GTBS */
+
+#if defined(CONFIG_BT_TBS_CLIENT_TBS)
+	zassert_equal(CONFIG_BT_TBS_CLIENT_MAX_TBS_INSTANCES,
+		      mock_ccp_call_control_client_discover_cb_fake.arg2_history[0]->tbs_count);
+	zassert_not_null(
+		mock_ccp_call_control_client_discover_cb_fake.arg2_history[0]->tbs_bearers);
+#endif /* CONFIG_BT_TBS_CLIENT_TBS */
+}
+
+static ZTEST_F(ccp_call_control_client_test_suite,
+	       test_ccp_call_control_client_discover_inval_param_null_conn)
+{
+	int err;
+
+	err = bt_ccp_call_control_client_register_cb(&mock_ccp_call_control_client_cb);
+	zassert_equal(0, err, "Unexpected return value %d", err);
+
+	err = bt_ccp_call_control_client_discover(NULL, &fixture->client);
+	zassert_equal(-EINVAL, err, "Unexpected return value %d", err);
+}
+
+static ZTEST_F(ccp_call_control_client_test_suite,
+	       test_ccp_call_control_client_discover_inval_param_null_client)
+{
+	int err;
+
+	err = bt_ccp_call_control_client_register_cb(&mock_ccp_call_control_client_cb);
+	zassert_equal(0, err, "Unexpected return value %d", err);
+
+	err = bt_ccp_call_control_client_discover(&fixture->conn, NULL);
+	zassert_equal(-EINVAL, err, "Unexpected return value %d", err);
+}
+
+static ZTEST_F(ccp_call_control_client_test_suite, test_ccp_call_control_client_get_bearers)
+{
+	struct bt_ccp_call_control_client_bearers bearers;
+	int err;
+
+	err = bt_ccp_call_control_client_register_cb(&mock_ccp_call_control_client_cb);
+	zassert_equal(0, err, "Unexpected return value %d", err);
+
+	err = bt_ccp_call_control_client_discover(&fixture->conn, &fixture->client);
+	zassert_equal(0, err, "Unexpected return value %d", err);
+
+	err = bt_ccp_call_control_client_get_bearers(fixture->client, &bearers);
+	zassert_equal(0, err, "Unexpected return value %d", err);
+
+#if defined(CONFIG_BT_TBS_CLIENT_GTBS)
+	zassert_not_null(bearers.gtbs_bearer);
+#endif /* CONFIG_BT_TBS_CLIENT_GTBS */
+
+#if defined(CONFIG_BT_TBS_CLIENT_TBS)
+	zassert_equal(CONFIG_BT_TBS_CLIENT_MAX_TBS_INSTANCES, bearers.tbs_count);
+	zassert_not_null(bearers.tbs_bearers);
+#endif /* CONFIG_BT_TBS_CLIENT_TBS */
+}
diff --git a/tests/bluetooth/audio/ccp_call_control_client/testcase.yaml b/tests/bluetooth/audio/ccp_call_control_client/testcase.yaml
new file mode 100644
index 00000000000..007a4f45ef5
--- /dev/null
+++ b/tests/bluetooth/audio/ccp_call_control_client/testcase.yaml
@@ -0,0 +1,7 @@
+common:
+  tags:
+    - bluetooth
+    - bluetooth_audio
+tests:
+  bluetooth.audio.ccp_call_control_client.test:
+    type: unit
diff --git a/tests/bluetooth/audio/ccp_call_control_client/uut/CMakeLists.txt b/tests/bluetooth/audio/ccp_call_control_client/uut/CMakeLists.txt
new file mode 100644
index 00000000000..1347cc8e0f1
--- /dev/null
+++ b/tests/bluetooth/audio/ccp_call_control_client/uut/CMakeLists.txt
@@ -0,0 +1,22 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# CMakeLists.txt file for creating of uut library.
+#
+
+add_library(uut STATIC
+  ${ZEPHYR_BASE}/lib/net_buf/buf_simple.c
+  ${ZEPHYR_BASE}/subsys/bluetooth/audio/ccp_call_control_client.c
+  ${ZEPHYR_BASE}/subsys/logging/log_minimal.c
+  ccp_call_control_client.c
+  tbs_client.c
+)
+
+add_subdirectory(${ZEPHYR_BASE}/tests/bluetooth/audio/mocks mocks)
+
+target_link_libraries(uut PUBLIC test_interface mocks)
+target_include_directories(uut PRIVATE ${ZEPHYR_BASE}/tests/bluetooth/audio/ccp_call_control_client/include)
+
+target_compile_options(uut PRIVATE -std=c11 -include ztest.h)
diff --git a/tests/bluetooth/audio/ccp_call_control_client/uut/ccp_call_control_client.c b/tests/bluetooth/audio/ccp_call_control_client/uut/ccp_call_control_client.c
new file mode 100644
index 00000000000..5b4e2363217
--- /dev/null
+++ b/tests/bluetooth/audio/ccp_call_control_client/uut/ccp_call_control_client.c
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdint.h>
+
+#include <zephyr/bluetooth/audio/ccp.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/fff.h>
+
+#include "ccp_call_control_client.h"
+
+/* List of fakes used by this unit tester */
+#define FFF_FAKES_LIST(FAKE) FAKE(mock_ccp_call_control_client_discover_cb)
+
+DEFINE_FAKE_VOID_FUNC(mock_ccp_call_control_client_discover_cb, struct bt_ccp_call_control_client *,
+		      int, struct bt_ccp_call_control_client_bearers *);
+
+struct bt_ccp_call_control_client_cb mock_ccp_call_control_client_cb = {
+	.discover = mock_ccp_call_control_client_discover_cb,
+};
+
+void mock_ccp_call_control_client_init(void)
+{
+	FFF_FAKES_LIST(RESET_FAKE);
+}
+
+void mock_ccp_call_control_client_cleanup(void)
+{
+}
diff --git a/tests/bluetooth/audio/ccp_call_control_client/uut/tbs_client.c b/tests/bluetooth/audio/ccp_call_control_client/uut/tbs_client.c
new file mode 100644
index 00000000000..87564da4587
--- /dev/null
+++ b/tests/bluetooth/audio/ccp_call_control_client/uut/tbs_client.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stddef.h>
+#include <stdint.h>
+
+#include <zephyr/bluetooth/audio/tbs.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/sys/util_macro.h>
+
+static struct bt_tbs_client_cb *tbs_cbs;
+
+int bt_tbs_client_register_cb(struct bt_tbs_client_cb *cbs)
+{
+	tbs_cbs = cbs;
+
+	return 0;
+}
+
+int bt_tbs_client_discover(struct bt_conn *conn)
+{
+	if (tbs_cbs != NULL && tbs_cbs->discover != NULL) {
+		uint8_t tbs_cnt = 0;
+
+		IF_ENABLED(CONFIG_BT_TBS_CLIENT_TBS,
+			   (tbs_cnt += CONFIG_BT_TBS_CLIENT_MAX_TBS_INSTANCES));
+
+		tbs_cbs->discover(conn, 0, tbs_cnt, IS_ENABLED(CONFIG_BT_TBS_CLIENT_GTBS));
+	}
+
+	return 0;
+}
diff --git a/tests/bluetooth/audio/codec/src/main.c b/tests/bluetooth/audio/codec/src/main.c
index fcddfbb0523..e1deb976212 100644
--- a/tests/bluetooth/audio/codec/src/main.c
+++ b/tests/bluetooth/audio/codec/src/main.c
@@ -1135,23 +1135,22 @@ ZTEST(audio_codec_test_suite, test_bt_audio_codec_cap_set_val_new)
 
 ZTEST(audio_codec_test_suite, test_bt_audio_codec_cap_unset_val)
 {
-	struct bt_audio_codec_cap codec_cap =
-		BT_AUDIO_CODEC_CAP(BT_HCI_CODING_FORMAT_LC3, 0x0000, 0x0000,
-				   {BT_AUDIO_CODEC_DATA(BT_AUDIO_CODEC_CFG_FREQ,
-							BT_AUDIO_CODEC_CFG_FREQ_16KHZ)},
-				   {});
-	const uint8_t expected_data = BT_AUDIO_CODEC_CFG_FREQ_16KHZ;
+	struct bt_audio_codec_cap codec_cap = BT_AUDIO_CODEC_CAP(
+		BT_HCI_CODING_FORMAT_LC3, 0x0000, 0x0000,
+		{BT_AUDIO_CODEC_DATA(BT_AUDIO_CODEC_CAP_TYPE_FREQ, BT_AUDIO_CODEC_CAP_FREQ_16KHZ)},
+		{});
+	const uint8_t expected_data = BT_AUDIO_CODEC_CAP_FREQ_16KHZ;
 	const uint8_t *data;
 	int ret;
 
-	ret = bt_audio_codec_cap_get_val(&codec_cap, BT_AUDIO_CODEC_CFG_FREQ, &data);
+	ret = bt_audio_codec_cap_get_val(&codec_cap, BT_AUDIO_CODEC_CAP_TYPE_FREQ, &data);
 	zassert_equal(ret, sizeof(expected_data), "Unexpected return value %d", ret);
 	zassert_equal(data[0], expected_data, "Unexpected return value %d", ret);
 
-	ret = bt_audio_codec_cap_unset_val(&codec_cap, BT_AUDIO_CODEC_CFG_FREQ);
+	ret = bt_audio_codec_cap_unset_val(&codec_cap, BT_AUDIO_CODEC_CAP_TYPE_FREQ);
 	zassert_true(ret >= 0, "Unexpected return value %d", ret);
 
-	ret = bt_audio_codec_cap_get_val(&codec_cap, BT_AUDIO_CODEC_CFG_FREQ, &data);
+	ret = bt_audio_codec_cap_get_val(&codec_cap, BT_AUDIO_CODEC_CAP_TYPE_FREQ, &data);
 	zassert_equal(ret, -ENODATA, "Unexpected return value %d", ret);
 }
 
diff --git a/tests/bluetooth/audio/mocks/CMakeLists.txt b/tests/bluetooth/audio/mocks/CMakeLists.txt
index b335b8a77dc..d29276670f3 100644
--- a/tests/bluetooth/audio/mocks/CMakeLists.txt
+++ b/tests/bluetooth/audio/mocks/CMakeLists.txt
@@ -14,6 +14,7 @@ add_library(mocks STATIC
   src/crypto.c
   src/fatal.c
   src/gatt.c
+  src/hci_core.c
   src/iso.c
   src/kernel.c
   src/mem_slab.c
diff --git a/tests/bluetooth/audio/mocks/include/bap_stream.h b/tests/bluetooth/audio/mocks/include/bap_stream.h
index c823d7089fb..e04a8a1a006 100644
--- a/tests/bluetooth/audio/mocks/include/bap_stream.h
+++ b/tests/bluetooth/audio/mocks/include/bap_stream.h
@@ -6,9 +6,12 @@
 
 #ifndef MOCKS_BAP_STREAM_H_
 #define MOCKS_BAP_STREAM_H_
+#include <stdint.h>
 
+#include <zephyr/bluetooth/iso.h>
 #include <zephyr/fff.h>
 #include <zephyr/bluetooth/audio/bap.h>
+#include <zephyr/net_buf.h>
 
 extern struct bt_bap_stream_ops mock_bap_stream_ops;
 
diff --git a/tests/bluetooth/audio/mocks/include/bap_stream_expects.h b/tests/bluetooth/audio/mocks/include/bap_stream_expects.h
index 526e7a4ed40..6e509ef6263 100644
--- a/tests/bluetooth/audio/mocks/include/bap_stream_expects.h
+++ b/tests/bluetooth/audio/mocks/include/bap_stream_expects.h
@@ -8,6 +8,9 @@
 #define MOCKS_BAP_STREAM_EXPECTS_H_
 
 #include <zephyr/bluetooth/audio/bap.h>
+#include <zephyr/bluetooth/iso.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/ztest_assert.h>
 
 #include "bap_stream.h"
 #include "expects_util.h"
diff --git a/tests/bluetooth/audio/mocks/include/bluetooth.h b/tests/bluetooth/audio/mocks/include/bluetooth.h
index 43baf8b03ee..b95199581fd 100644
--- a/tests/bluetooth/audio/mocks/include/bluetooth.h
+++ b/tests/bluetooth/audio/mocks/include/bluetooth.h
@@ -6,6 +6,7 @@
 
 #ifndef MOCKS_BLUETOOTH_H_
 #define MOCKS_BLUETOOTH_H_
+#include <stdint.h>
 
 struct bt_le_ext_adv {
 	/* ID Address used for advertising */
diff --git a/tests/bluetooth/audio/mocks/include/conn.h b/tests/bluetooth/audio/mocks/include/conn.h
index ae6d3dc70d4..d75b733a3df 100644
--- a/tests/bluetooth/audio/mocks/include/conn.h
+++ b/tests/bluetooth/audio/mocks/include/conn.h
@@ -1,13 +1,31 @@
 /*
  * Copyright (c) 2023 Codecoup
+ * Copyright (c) 2024 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #ifndef MOCKS_CONN_H_
 #define MOCKS_CONN_H_
+#include <stdint.h>
 
+#include <stdint.h>
+
+#include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/conn.h>
+#include <zephyr/fff.h>
+
+/* List of fakes used by this unit tester */
+#define CONN_FFF_FAKES_LIST(FAKE)                                                                  \
+	FAKE(bt_conn_foreach)                                                                      \
+	FAKE(bt_conn_get_dst)                                                                      \
+	FAKE(bt_foreach_bond)
+
+typedef void (*bt_conn_foreach_cb)(struct bt_conn *, void *);
+typedef void (*bt_foreach_bond_cb)(const struct bt_bond_info *, void *);
+DECLARE_FAKE_VOID_FUNC(bt_conn_foreach, enum bt_conn_type, bt_conn_foreach_cb, void *);
+DECLARE_FAKE_VALUE_FUNC(const bt_addr_le_t *, bt_conn_get_dst, const struct bt_conn *);
+DECLARE_FAKE_VOID_FUNC(bt_foreach_bond, uint8_t, bt_foreach_bond_cb, void *);
 
 struct bt_conn {
 	uint8_t index;
@@ -15,6 +33,7 @@ struct bt_conn {
 	struct bt_iso_chan *chan;
 };
 
+void mock_bt_conn_connected(struct bt_conn *conn, uint8_t err);
 void mock_bt_conn_disconnected(struct bt_conn *conn, uint8_t err);
 
 #endif /* MOCKS_CONN_H_ */
diff --git a/tests/bluetooth/audio/mocks/include/crypto.h b/tests/bluetooth/audio/mocks/include/crypto.h
index 1aa01e5203f..2bf1e985285 100644
--- a/tests/bluetooth/audio/mocks/include/crypto.h
+++ b/tests/bluetooth/audio/mocks/include/crypto.h
@@ -6,6 +6,7 @@
 
 #ifndef MOCKS_CRYPTO_H_
 #define MOCKS_CRYPTO_H_
+#include <stddef.h>
 
 #include <zephyr/fff.h>
 #include <zephyr/kernel.h>
diff --git a/tests/bluetooth/audio/mocks/include/expects_util.h b/tests/bluetooth/audio/mocks/include/expects_util.h
index 7cb630b7b33..978baa25e81 100644
--- a/tests/bluetooth/audio/mocks/include/expects_util.h
+++ b/tests/bluetooth/audio/mocks/include/expects_util.h
@@ -6,10 +6,17 @@
 
 #ifndef MOCKS_UTIL_H_
 #define MOCKS_UTIL_H_
+#include <stddef.h>
+#include <stdint.h>
 
+#include <stdint.h>
+
+#include <zephyr/sys/util_internal.h>
 #include <zephyr/types.h>
 #include <zephyr/sys/util_macro.h>
+#include <zephyr/sys/util_internal.h>
 #include <zephyr/ztest.h>
+#include <zephyr/ztest_assert.h>
 
 #define CHECK_EMPTY(_x) UTIL_BOOL(IS_EMPTY(_x))
 #define COND_CODE_EMPTY(_x, _if_any_code, _else_code)                                              \
diff --git a/tests/bluetooth/audio/mocks/include/gatt.h b/tests/bluetooth/audio/mocks/include/gatt.h
index 619d35f13e9..2ee62c3447e 100644
--- a/tests/bluetooth/audio/mocks/include/gatt.h
+++ b/tests/bluetooth/audio/mocks/include/gatt.h
@@ -6,8 +6,10 @@
 
 #ifndef MOCKS_GATT_H_
 #define MOCKS_GATT_H_
+#include <stdint.h>
 
 #include <zephyr/fff.h>
+#include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gatt.h>
 
 void mock_bt_gatt_init(void);
diff --git a/tests/bluetooth/audio/mocks/include/gatt_expects.h b/tests/bluetooth/audio/mocks/include/gatt_expects.h
index 3e661bfc2a1..f8580575664 100644
--- a/tests/bluetooth/audio/mocks/include/gatt_expects.h
+++ b/tests/bluetooth/audio/mocks/include/gatt_expects.h
@@ -8,6 +8,7 @@
 #define MOCKS_GATT_EXPECTS_H_
 
 #include <zephyr/bluetooth/gatt.h>
+#include <zephyr/ztest_assert.h>
 
 #include "gatt.h"
 #include "expects_util.h"
diff --git a/tests/bluetooth/audio/mocks/include/hci_core.h b/tests/bluetooth/audio/mocks/include/hci_core.h
new file mode 100644
index 00000000000..a1e42572f8f
--- /dev/null
+++ b/tests/bluetooth/audio/mocks/include/hci_core.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef MOCKS_HCI_CORE_H_
+#define MOCKS_HCI_CORE_H_
+
+#include <stdint.h>
+
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/fff.h>
+
+bool bt_le_bond_exists(uint8_t id, const bt_addr_le_t *addr);
+#endif /* MOCKS_HCI_CORE_H_ */
diff --git a/tests/bluetooth/audio/mocks/include/iso.h b/tests/bluetooth/audio/mocks/include/iso.h
index 82536c6f0fe..866e8e170fb 100644
--- a/tests/bluetooth/audio/mocks/include/iso.h
+++ b/tests/bluetooth/audio/mocks/include/iso.h
@@ -6,9 +6,12 @@
 
 #ifndef MOCKS_ISO_H_
 #define MOCKS_ISO_H_
+#include <stdint.h>
 
-#include <zephyr/fff.h>
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/iso.h>
+#include <zephyr/fff.h>
 
 #if defined(CONFIG_BT_BAP_BROADCAST_SOURCE)
 struct bt_iso_big {
diff --git a/tests/bluetooth/audio/mocks/include/mock_kernel.h b/tests/bluetooth/audio/mocks/include/mock_kernel.h
index 360ff79f416..80948f79090 100644
--- a/tests/bluetooth/audio/mocks/include/mock_kernel.h
+++ b/tests/bluetooth/audio/mocks/include/mock_kernel.h
@@ -10,6 +10,8 @@
 
 #include <zephyr/fff.h>
 #include <zephyr/kernel.h>
+#include <zephyr/kernel_structs.h>
+#include <zephyr/sys_clock.h>
 
 void mock_kernel_init(void);
 void mock_kernel_cleanup(void);
diff --git a/tests/bluetooth/audio/mocks/include/pacs.h b/tests/bluetooth/audio/mocks/include/pacs.h
index d5cc81e6490..d7c3ca4649f 100644
--- a/tests/bluetooth/audio/mocks/include/pacs.h
+++ b/tests/bluetooth/audio/mocks/include/pacs.h
@@ -7,8 +7,10 @@
 #ifndef MOCKS_PACS_H_
 #define MOCKS_PACS_H_
 
-#include <zephyr/fff.h>
+#include <zephyr/bluetooth/audio/audio.h>
 #include <zephyr/bluetooth/audio/pacs.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/fff.h>
 
 void mock_bt_pacs_init(void);
 void mock_bt_pacs_cleanup(void);
diff --git a/tests/bluetooth/audio/mocks/src/bap_stream.c b/tests/bluetooth/audio/mocks/src/bap_stream.c
index 31b060d0111..63e38d70c0c 100644
--- a/tests/bluetooth/audio/mocks/src/bap_stream.c
+++ b/tests/bluetooth/audio/mocks/src/bap_stream.c
@@ -3,8 +3,12 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stdint.h>
 
 #include <zephyr/bluetooth/audio/bap.h>
+#include <zephyr/bluetooth/iso.h>
+#include <zephyr/fff.h>
+#include <zephyr/net_buf.h>
 
 #include "bap_stream.h"
 
diff --git a/tests/bluetooth/audio/mocks/src/conn.c b/tests/bluetooth/audio/mocks/src/conn.c
index d7570bd0f5f..2025f678a7b 100644
--- a/tests/bluetooth/audio/mocks/src/conn.c
+++ b/tests/bluetooth/audio/mocks/src/conn.c
@@ -1,13 +1,28 @@
 /*
  * Copyright (c) 2023 Codecoup
+ * Copyright (c) 2024-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stdint.h>
 
+#include <errno.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/conn.h>
+#include <zephyr/fff.h>
+#include <zephyr/sys/iterable_sections.h>
 
 #include "conn.h"
 
+DEFINE_FAKE_VOID_FUNC(bt_conn_foreach, enum bt_conn_type, bt_conn_foreach_cb, void *);
+DEFINE_FAKE_VALUE_FUNC(const bt_addr_le_t *, bt_conn_get_dst, const struct bt_conn *);
+DEFINE_FAKE_VOID_FUNC(bt_foreach_bond, uint8_t, bt_foreach_bond_cb, void *);
+
+static struct bt_conn_auth_info_cb *bt_auth_info_cb;
+
 uint8_t bt_conn_index(const struct bt_conn *conn)
 {
 	return conn->index;
@@ -27,7 +42,30 @@ struct bt_conn *bt_conn_ref(struct bt_conn *conn)
 
 void bt_conn_unref(struct bt_conn *conn)
 {
+}
+
+int bt_conn_auth_info_cb_register(struct bt_conn_auth_info_cb *cb)
+{
+	if (cb == NULL) {
+		return -EINVAL;
+	}
+
+	if (bt_auth_info_cb != NULL) {
+		return -EALREADY;
+	}
 
+	bt_auth_info_cb = cb;
+
+	return 0;
+}
+
+void mock_bt_conn_connected(struct bt_conn *conn, uint8_t err)
+{
+	STRUCT_SECTION_FOREACH(bt_conn_cb, cb) {
+		if (cb->connected) {
+			cb->connected(conn, err);
+		}
+	}
 }
 
 void mock_bt_conn_disconnected(struct bt_conn *conn, uint8_t err)
diff --git a/tests/bluetooth/audio/mocks/src/crypto.c b/tests/bluetooth/audio/mocks/src/crypto.c
index 05e23238be2..2abdc662283 100644
--- a/tests/bluetooth/audio/mocks/src/crypto.c
+++ b/tests/bluetooth/audio/mocks/src/crypto.c
@@ -3,7 +3,9 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-#include <zephyr/kernel.h>
+#include <stddef.h>
+
+#include <zephyr/fff.h>
 
 #include "crypto.h"
 
diff --git a/tests/bluetooth/audio/mocks/src/gatt.c b/tests/bluetooth/audio/mocks/src/gatt.c
index 4138ef59756..2c30f291aa7 100644
--- a/tests/bluetooth/audio/mocks/src/gatt.c
+++ b/tests/bluetooth/audio/mocks/src/gatt.c
@@ -547,3 +547,64 @@ bool bt_gatt_is_subscribed(struct bt_conn *conn,
 {
 	return mock_bt_gatt_is_subscribed(conn, attr, ccc_type);
 }
+
+uint16_t bt_gatt_attr_get_handle(const struct bt_gatt_attr *attr)
+{
+	uint16_t handle = 1;
+
+	if (!attr) {
+		return 0;
+	}
+
+	if (attr->handle) {
+		return attr->handle;
+	}
+
+	STRUCT_SECTION_FOREACH(bt_gatt_service_static, static_svc) {
+		/* Skip ahead if start is not within service attributes array */
+		if ((attr < &static_svc->attrs[0]) ||
+		    (attr > &static_svc->attrs[static_svc->attr_count - 1])) {
+			handle += static_svc->attr_count;
+			continue;
+		}
+
+		for (size_t i = 0; i < static_svc->attr_count; i++, handle++) {
+			if (attr == &static_svc->attrs[i]) {
+				return handle;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static uint8_t find_next(const struct bt_gatt_attr *attr, uint16_t handle, void *user_data)
+{
+	struct bt_gatt_attr **next = user_data;
+
+	*next = (struct bt_gatt_attr *)attr;
+
+	return BT_GATT_ITER_STOP;
+}
+
+struct bt_gatt_attr *bt_gatt_find_by_uuid(const struct bt_gatt_attr *attr, uint16_t attr_count,
+					  const struct bt_uuid *uuid)
+{
+	struct bt_gatt_attr *found = NULL;
+	uint16_t start_handle = bt_gatt_attr_get_handle(attr);
+	uint16_t end_handle = start_handle && attr_count
+				      ? MIN(start_handle + attr_count, BT_ATT_LAST_ATTRIBUTE_HANDLE)
+				      : BT_ATT_LAST_ATTRIBUTE_HANDLE;
+
+	if (attr != NULL && start_handle == 0U) {
+		/* If start_handle is 0 then `attr` is not in our database, and should not be used
+		 * as a starting point for the search
+		 */
+		LOG_DBG("Could not find handle of attr %p", attr);
+		return NULL;
+	}
+
+	bt_gatt_foreach_attr_type(start_handle, end_handle, uuid, NULL, 1, find_next, &found);
+
+	return found;
+}
diff --git a/tests/bluetooth/audio/mocks/src/hci_core.c b/tests/bluetooth/audio/mocks/src/hci_core.c
new file mode 100644
index 00000000000..35c0f70e77e
--- /dev/null
+++ b/tests/bluetooth/audio/mocks/src/hci_core.c
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdint.h>
+
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/fff.h>
+
+bool bt_le_bond_exists(uint8_t id, const bt_addr_le_t *addr)
+{
+	return true;
+}
diff --git a/tests/bluetooth/audio/mocks/src/iso.c b/tests/bluetooth/audio/mocks/src/iso.c
index bb344f81a77..ac4e58314c1 100644
--- a/tests/bluetooth/audio/mocks/src/iso.c
+++ b/tests/bluetooth/audio/mocks/src/iso.c
@@ -1,14 +1,20 @@
 /*
  * Copyright (c) 2023 Codecoup
- * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2024-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <errno.h>
+#include <stdint.h>
 #include <stdlib.h>
 
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/iso.h>
+#include <zephyr/fff.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/ztest_assert.h>
 
 #include "conn.h"
 #include "iso.h"
@@ -76,6 +82,17 @@ void mock_bt_iso_cleanup(void)
 
 }
 
+int bt_iso_setup_data_path(const struct bt_iso_chan *chan, uint8_t dir,
+			   const struct bt_iso_chan_path *path)
+{
+	return 0;
+}
+
+int bt_iso_remove_data_path(const struct bt_iso_chan *chan, uint8_t dir)
+{
+	return 0;
+}
+
 void mock_bt_iso_connected(struct bt_conn *iso)
 {
 	struct bt_iso_chan *chan = iso->chan;
diff --git a/tests/bluetooth/audio/mocks/src/kernel.c b/tests/bluetooth/audio/mocks/src/kernel.c
index 5cd8bbbd852..1ee2e8d7759 100644
--- a/tests/bluetooth/audio/mocks/src/kernel.c
+++ b/tests/bluetooth/audio/mocks/src/kernel.c
@@ -1,11 +1,16 @@
 /*
- * Copyright (c) 2022 Nordic Semiconductor ASA
+ * Copyright (c) 2022-2025 Nordic Semiconductor ASA
  * Copyright (c) 2023 Codecoup
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <errno.h>
+#include <stddef.h>
+#include <stdint.h>
 
+#include <zephyr/fff.h>
 #include <zephyr/kernel.h>
+#include <zephyr/kernel_structs.h>
 #include <zephyr/sys_clock.h>
 #include <zephyr/sys/slist.h>
 
@@ -129,6 +134,40 @@ int32_t k_sleep(k_timeout_t timeout)
 
 	return 0;
 }
+static bool mutex_locked;
+
+int k_mutex_init(struct k_mutex *mutex)
+{
+	mutex_locked = false;
+
+	return 0;
+}
+
+int k_mutex_lock(struct k_mutex *mutex, k_timeout_t timeout)
+{
+	if (mutex_locked) {
+		if (K_TIMEOUT_EQ(timeout, K_NO_WAIT)) {
+			return -EBUSY;
+		} else {
+			return -EAGAIN;
+		}
+	}
+
+	mutex_locked = true;
+
+	return 0;
+}
+
+int k_mutex_unlock(struct k_mutex *mutex)
+{
+	if (!mutex_locked) {
+		return -EINVAL;
+	}
+
+	mutex_locked = false;
+
+	return 0;
+}
 
 void mock_kernel_init(void)
 {
diff --git a/tests/bluetooth/audio/mocks/src/mem_slab.c b/tests/bluetooth/audio/mocks/src/mem_slab.c
index 65209b848e5..5877171733a 100644
--- a/tests/bluetooth/audio/mocks/src/mem_slab.c
+++ b/tests/bluetooth/audio/mocks/src/mem_slab.c
@@ -3,9 +3,12 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <errno.h>
 
 #include <stdlib.h>
 #include <zephyr/kernel.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/ztest_assert.h>
 
 int k_mem_slab_alloc(struct k_mem_slab *slab, void **mem, k_timeout_t timeout)
 {
diff --git a/tests/bluetooth/audio/mocks/src/net_buf.c b/tests/bluetooth/audio/mocks/src/net_buf.c
index 2757e1d257b..2a4f17c08c0 100644
--- a/tests/bluetooth/audio/mocks/src/net_buf.c
+++ b/tests/bluetooth/audio/mocks/src/net_buf.c
@@ -4,7 +4,6 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <kernel.h>
 #include <zephyr/net_buf.h>
 
 void net_buf_unref(struct net_buf *buf)
diff --git a/tests/bluetooth/audio/mocks/src/pacs.c b/tests/bluetooth/audio/mocks/src/pacs.c
index 60e23bd7999..3b9aae121a0 100644
--- a/tests/bluetooth/audio/mocks/src/pacs.c
+++ b/tests/bluetooth/audio/mocks/src/pacs.c
@@ -3,11 +3,18 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stddef.h>
 
-#include <zephyr/types.h>
+#include <zephyr/bluetooth/audio/audio.h>
+#include <zephyr/bluetooth/audio/lc3.h>
 #include <zephyr/bluetooth/audio/pacs.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/fff.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/types.h>
 
 #include "pacs.h"
+#include "pacs_internal.h"
 
 /* List of fakes used by this unit tester */
 #define PACS_FFF_FAKES_LIST(FAKE) \
@@ -49,3 +56,11 @@ void mock_bt_pacs_cleanup(void)
 {
 
 }
+
+const struct bt_audio_codec_cap *bt_pacs_get_codec_cap(enum bt_audio_dir dir,
+						       const struct bt_pac_codec *codec_id)
+{
+	static struct bt_audio_codec_cap mock_cap;
+
+	return &mock_cap;
+}
diff --git a/tests/bluetooth/audio/pacs/CMakeLists.txt b/tests/bluetooth/audio/pacs/CMakeLists.txt
new file mode 100644
index 00000000000..77dba658f8c
--- /dev/null
+++ b/tests/bluetooth/audio/pacs/CMakeLists.txt
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr COMPONENTS unittest HINTS $ENV{ZEPHYR_BASE})
+
+project(bluetooth_pacs)
+
+add_subdirectory(${ZEPHYR_BASE}/tests/bluetooth/audio/pacs/uut uut)
+
+target_link_libraries(testbinary PRIVATE uut)
+
+target_include_directories(testbinary PRIVATE include)
+
+target_sources(testbinary
+  PRIVATE
+    src/main.c
+)
diff --git a/tests/bluetooth/audio/pacs/prj.conf b/tests/bluetooth/audio/pacs/prj.conf
new file mode 100644
index 00000000000..4846edb9f54
--- /dev/null
+++ b/tests/bluetooth/audio/pacs/prj.conf
@@ -0,0 +1,18 @@
+CONFIG_ZTEST=y
+
+CONFIG_BT=y
+CONFIG_BT_PERIPHERAL=y
+CONFIG_BT_SMP=y
+CONFIG_BT_GATT_DYNAMIC_DB=y
+CONFIG_BT_AUDIO=y
+CONFIG_BT_PAC_SNK=y
+CONFIG_BT_PAC_SNK_LOC=y
+CONFIG_BT_PAC_SRC=y
+CONFIG_BT_PAC_SRC_LOC=y
+
+CONFIG_LOG=y
+CONFIG_BT_PACS_LOG_LEVEL_DBG=y
+
+CONFIG_ASSERT=y
+CONFIG_ASSERT_LEVEL=2
+CONFIG_ASSERT_VERBOSE=y
diff --git a/tests/bluetooth/audio/pacs/src/main.c b/tests/bluetooth/audio/pacs/src/main.c
new file mode 100644
index 00000000000..01a56f7abb5
--- /dev/null
+++ b/tests/bluetooth/audio/pacs/src/main.c
@@ -0,0 +1,187 @@
+/* main.c - Application main entry point */
+
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <errno.h>
+#include <stdint.h>
+#include <stdlib.h>
+
+#include <zephyr/bluetooth/att.h>
+#include <zephyr/bluetooth/audio/audio.h>
+#include <zephyr/bluetooth/audio/pacs.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/gatt.h>
+#include <zephyr/bluetooth/uuid.h>
+#include <zephyr/fff.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/ztest_assert.h>
+#include <zephyr/ztest_test.h>
+
+DEFINE_FFF_GLOBALS;
+
+static void pacs_test_suite_after(void *f)
+{
+	/* attempt to clean up after any failures */
+	(void)bt_pacs_unregister();
+}
+
+ZTEST_SUITE(pacs_test_suite, NULL, NULL, NULL, pacs_test_suite_after, NULL);
+
+/* Helper macro to define parameters ignoring unsupported features */
+#define PACS_REGISTER_PARAM(_snk_pac, _snk_loc, _src_pac, _src_loc)                                \
+	(struct bt_pacs_register_param)                                                            \
+	{                                                                                          \
+		IF_ENABLED(CONFIG_BT_PAC_SNK, (.snk_pac = (_snk_pac),))                            \
+		IF_ENABLED(CONFIG_BT_PAC_SNK_LOC, (.snk_loc = (_snk_loc),))                        \
+		IF_ENABLED(CONFIG_BT_PAC_SRC, (.src_pac = (_src_pac),))                            \
+		IF_ENABLED(CONFIG_BT_PAC_SRC_LOC, (.src_loc = (_src_loc),))                        \
+	}
+
+static ZTEST(pacs_test_suite, test_pacs_register)
+{
+	const struct bt_pacs_register_param pacs_params[] = {
+#if defined(CONFIG_BT_PAC_SNK)
+		/* valid snk_pac combinations */
+		PACS_REGISTER_PARAM(true, true, true, true),
+		PACS_REGISTER_PARAM(true, true, true, false),
+		PACS_REGISTER_PARAM(true, true, false, false),
+		PACS_REGISTER_PARAM(true, false, true, true),
+		PACS_REGISTER_PARAM(true, false, true, false),
+		PACS_REGISTER_PARAM(true, false, false, false),
+#endif /* CONFIG_BT_PAC_SNK */
+
+#if defined(CONFIG_BT_PAC_SRC)
+		/* valid src_pac combinations */
+		PACS_REGISTER_PARAM(true, true, true, true),
+		PACS_REGISTER_PARAM(true, false, true, true),
+		PACS_REGISTER_PARAM(false, false, true, true),
+		PACS_REGISTER_PARAM(true, true, true, false),
+		PACS_REGISTER_PARAM(true, false, true, false),
+		PACS_REGISTER_PARAM(false, false, true, false),
+#endif /* CONFIG_BT_PAC_SRC */
+	};
+
+	for (size_t i = 0U; i < ARRAY_SIZE(pacs_params); i++) {
+		struct bt_gatt_attr *attr;
+		int err;
+
+		err = bt_pacs_register(&pacs_params[i]);
+		zassert_equal(err, 0, "[%zu]: Unexpected return value %d", i, err);
+
+#if defined(CONFIG_BT_PAC_SNK)
+		attr = bt_gatt_find_by_uuid(NULL, 0, BT_UUID_PACS_SNK);
+		if (pacs_params[i].snk_pac) {
+			zassert_not_null(attr, "[%zu]: Could not find sink PAC", i);
+		} else {
+			zassert_is_null(attr, "[%zu]: Found unexpected sink PAC", i);
+		}
+#endif /*CONFIG_BT_PAC_SNK */
+#if defined(CONFIG_BT_PAC_SNK_LOC)
+		attr = bt_gatt_find_by_uuid(NULL, 0, BT_UUID_PACS_SNK_LOC);
+		if (pacs_params[i].snk_loc) {
+			zassert_not_null(attr, "[%zu]: Could not find sink loc", i);
+		} else {
+			zassert_is_null(attr, "[%zu]: Found unexpected sink loc", i);
+		}
+#endif /*CONFIG_BT_PAC_SNK_LOC */
+#if defined(CONFIG_BT_PAC_SRC)
+		attr = bt_gatt_find_by_uuid(NULL, 0, BT_UUID_PACS_SRC);
+		if (pacs_params[i].src_pac) {
+			zassert_not_null(attr, "[%zu]: Could not find source PAC", i);
+		} else {
+			zassert_is_null(attr, "[%zu]: Found unexpected source PAC", i);
+		}
+#endif /*CONFIG_BT_PAC_SRC */
+#if defined(CONFIG_BT_PAC_SRC_LOC)
+		attr = bt_gatt_find_by_uuid(NULL, 0, BT_UUID_PACS_SRC_LOC);
+		if (pacs_params[i].src_loc) {
+			zassert_not_null(attr, "[%zu]: Could not find source loc", i);
+		} else {
+			zassert_is_null(attr, "[%zu]: Found unexpected source loc", i);
+		}
+#endif /*CONFIG_BT_PAC_SRC_LOC */
+
+		err = bt_pacs_unregister();
+		zassert_equal(err, 0, "[%zu]: Unexpected return value %d", i, err);
+
+		attr = bt_gatt_find_by_uuid(NULL, 0, BT_UUID_PACS_SNK);
+		zassert_is_null(attr, "[%zu]: Unexpected find of sink PAC", i);
+
+		attr = bt_gatt_find_by_uuid(NULL, 0, BT_UUID_PACS_SNK_LOC);
+		zassert_is_null(attr, "[%zu]: Unexpected find of sink loc", i);
+
+		attr = bt_gatt_find_by_uuid(NULL, 0, BT_UUID_PACS_SRC);
+		zassert_is_null(attr, "[%zu]: Unexpected find of source PAC", i);
+
+		attr = bt_gatt_find_by_uuid(NULL, 0, BT_UUID_PACS_SRC_LOC);
+		zassert_is_null(attr, "[%zu]: Unexpected find of source loc", i);
+	}
+}
+
+static ZTEST(pacs_test_suite, test_pacs_register_inval_null_param)
+{
+	int err;
+
+	err = bt_pacs_register(NULL);
+	zassert_equal(err, -EINVAL, "Unexpected return value %d", err);
+}
+
+static ZTEST(pacs_test_suite, test_pacs_register_inval_double_register)
+{
+	const struct bt_pacs_register_param pacs_param =
+		PACS_REGISTER_PARAM(true, true, true, true);
+	int err;
+
+	err = bt_pacs_register(&pacs_param);
+	zassert_equal(err, 0, "Unexpected return value %d", err);
+
+	err = bt_pacs_register(&pacs_param);
+	zassert_equal(err, -EALREADY, "Unexpected return value %d", err);
+}
+
+static ZTEST(pacs_test_suite, test_pacs_register_inval_snk_loc_without_snk_pac)
+{
+	const struct bt_pacs_register_param pacs_param =
+		PACS_REGISTER_PARAM(false, true, true, true);
+	int err;
+
+	if (!(IS_ENABLED(CONFIG_BT_PAC_SNK) && IS_ENABLED(CONFIG_BT_PAC_SNK_LOC))) {
+		ztest_test_skip();
+	}
+
+	err = bt_pacs_register(&pacs_param);
+	zassert_equal(err, -EINVAL, "Unexpected return value %d", err);
+}
+
+static ZTEST(pacs_test_suite, test_pacs_register_inval_src_loc_without_src_pac)
+{
+	const struct bt_pacs_register_param pacs_param =
+		PACS_REGISTER_PARAM(true, true, false, true);
+	int err;
+
+	if (!(IS_ENABLED(CONFIG_BT_PAC_SRC) && IS_ENABLED(CONFIG_BT_PAC_SRC_LOC))) {
+		ztest_test_skip();
+	}
+
+	err = bt_pacs_register(&pacs_param);
+	zassert_equal(err, -EINVAL, "Unexpected return value %d", err);
+}
+
+static ZTEST(pacs_test_suite, test_pacs_register_inval_no_pac)
+{
+	const struct bt_pacs_register_param pacs_param =
+		PACS_REGISTER_PARAM(false, false, false, false);
+	int err;
+
+	if (!(IS_ENABLED(CONFIG_BT_PAC_SNK) && IS_ENABLED(CONFIG_BT_PAC_SNK_LOC))) {
+		ztest_test_skip();
+	}
+
+	err = bt_pacs_register(&pacs_param);
+	zassert_equal(err, -EINVAL, "Unexpected return value %d", err);
+}
diff --git a/tests/bluetooth/audio/pacs/testcase.yaml b/tests/bluetooth/audio/pacs/testcase.yaml
new file mode 100644
index 00000000000..ce269a37135
--- /dev/null
+++ b/tests/bluetooth/audio/pacs/testcase.yaml
@@ -0,0 +1,61 @@
+common:
+  tags:
+    - bluetooth
+    - bluetooth_audio
+tests:
+  bluetooth.audio.pacs.test_default:
+    type: unit
+    extra_configs:
+      - CONFIG_BT_PAC_SNK=y
+      - CONFIG_BT_PAC_SNK_LOC=y
+      - CONFIG_BT_PAC_SRC=y
+      - CONFIG_BT_PAC_SRC_LOC=y
+  bluetooth.audio.pacs.test_snk_pac_snk_loc_src_pac:
+    type: unit
+    extra_configs:
+      - CONFIG_BT_PAC_SNK=y
+      - CONFIG_BT_PAC_SNK_LOC=y
+      - CONFIG_BT_PAC_SRC=y
+      - CONFIG_BT_PAC_SRC_LOC=n
+  bluetooth.audio.pacs.test_snk_pac_snk_loc:
+    type: unit
+    extra_configs:
+      - CONFIG_BT_PAC_SNK=y
+      - CONFIG_BT_PAC_SNK_LOC=y
+      - CONFIG_BT_PAC_SRC=n
+      - CONFIG_BT_PAC_SRC_LOC=n
+  bluetooth.audio.pacs.test_snk_pac:
+    type: unit
+    extra_configs:
+      - CONFIG_BT_PAC_SNK=y
+      - CONFIG_BT_PAC_SNK_LOC=n
+      - CONFIG_BT_PAC_SRC=n
+      - CONFIG_BT_PAC_SRC_LOC=n
+  bluetooth.audio.pacs.test_snk_pac_src_pac_src_loc:
+    type: unit
+    extra_configs:
+      - CONFIG_BT_PAC_SNK=y
+      - CONFIG_BT_PAC_SNK_LOC=n
+      - CONFIG_BT_PAC_SRC=y
+      - CONFIG_BT_PAC_SRC_LOC=y
+  bluetooth.audio.pacs.test_snk_pac_src_pac:
+    type: unit
+    extra_configs:
+      - CONFIG_BT_PAC_SNK=y
+      - CONFIG_BT_PAC_SNK_LOC=n
+      - CONFIG_BT_PAC_SRC=y
+      - CONFIG_BT_PAC_SRC_LOC=n
+  bluetooth.audio.pacs.test_src_pac_src_loc:
+    type: unit
+    extra_configs:
+      - CONFIG_BT_PAC_SNK=n
+      - CONFIG_BT_PAC_SNK_LOC=n
+      - CONFIG_BT_PAC_SRC=y
+      - CONFIG_BT_PAC_SRC_LOC=y
+  bluetooth.audio.pacs.test_src_pac:
+    type: unit
+    extra_configs:
+      - CONFIG_BT_PAC_SNK=n
+      - CONFIG_BT_PAC_SNK_LOC=n
+      - CONFIG_BT_PAC_SRC=y
+      - CONFIG_BT_PAC_SRC_LOC=n
diff --git a/tests/bluetooth/audio/pacs/uut/CMakeLists.txt b/tests/bluetooth/audio/pacs/uut/CMakeLists.txt
new file mode 100644
index 00000000000..b86de848262
--- /dev/null
+++ b/tests/bluetooth/audio/pacs/uut/CMakeLists.txt
@@ -0,0 +1,21 @@
+#
+# Copyright (c) 2025 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+# CMakeLists.txt file for creating of uut library.
+#
+
+add_library(uut STATIC
+  ${ZEPHYR_BASE}/subsys/bluetooth/audio/audio.c
+  ${ZEPHYR_BASE}/subsys/bluetooth/audio/pacs.c
+  ${ZEPHYR_BASE}/subsys/bluetooth/host/uuid.c
+  ${ZEPHYR_BASE}/subsys/logging/log_minimal.c
+  ${ZEPHYR_BASE}/lib/net_buf/buf_simple.c
+)
+
+add_subdirectory(${ZEPHYR_BASE}/tests/bluetooth/audio/mocks mocks)
+
+target_link_libraries(uut PUBLIC test_interface mocks)
+
+target_compile_options(uut PRIVATE -std=c11 -include ztest.h)
diff --git a/tests/bluetooth/classic/sdp_c/CMakeLists.txt b/tests/bluetooth/classic/sdp_c/CMakeLists.txt
new file mode 100644
index 00000000000..89de0b86386
--- /dev/null
+++ b/tests/bluetooth/classic/sdp_c/CMakeLists.txt
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+set(NO_QEMU_SERIAL_BT_SERVER 1)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(bluetooth)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/bluetooth/classic/sdp_c/README.rst b/tests/bluetooth/classic/sdp_c/README.rst
new file mode 100644
index 00000000000..d40d0919d8b
--- /dev/null
+++ b/tests/bluetooth/classic/sdp_c/README.rst
@@ -0,0 +1,74 @@
+.. _bluetooth_classic_sdp_clinet_tests:
+
+Bluetooth Classic SDP Client Tests
+##################################
+
+Overview
+********
+
+This test suite uses ``bumble`` for testing Bluetooth Classic communication between a host
+PC (running :ref:`Twister <twister_script>`) and a device under test (DUT) running Zephyr.
+
+Prerequisites
+*************
+
+The test suite has the following prerequisites:
+
+* The ``bumble`` library installed on the host PC.
+The Bluetooth Classic controller on PC side is required. Refer to getting started of `bumble`_
+for details.
+
+The HCI transport for ``bumble`` can be configured as follows:
+
+* A specific configuration context can be provided along with the ``usb_hci`` fixture separated by
+  a ``:`` (i.e. specify fixture ``usb_hci:usb:0`` to use the ``usb:0`` as hci transport for
+  ``bumble``).
+* The configuration context can be overridden using the `hci transport`_ can be provided using the
+  ``--hci-transport`` test suite argument (i.e. run ``twister`` with the
+  ``--pytest-args=--hci-transport=usb:0`` argument to use the ``usb:0`` as hci transport for
+  ``bumble``).
+
+Building and Running
+********************
+
+Running on mimxrt1170_evk@B/mimxrt1176/cm7
+==========================================
+
+Running the test suite on :ref:`mimxrt1170_evk` relies on configuration of ``bumble``.
+
+On the host PC, a HCI transport needs to be required. Refer to `bumble platforms`_ page of
+``bumble`` for details.
+
+For example, on windows, a PTS dongle is used. After `WinUSB driver`_ has been installed,
+the HCI transport would be USB transport interface ``usb:<index>``.
+
+If the HCI transport is ``usb:0`` and debug console port is ``COM4``, the test suite can be
+launched using Twister:
+
+.. code-block:: shell
+
+   west twister -v -p mimxrt1170_evk@B/mimxrt1176/cm7 --device-testing --device-serial COM4 -T tests/bluetooth/classic/sdp_c -O sdp_c --force-platform --west-flash --west-runner=jlink -X usb_hci:usb:0
+
+Running on Hardware
+===================
+
+Running the test suite on hardware requires a HCI transport connected to the host PC.
+
+The test suite can be launched using Twister. Below is an example for running on the
+:zephyr:board:`mimxrt1170_evk@B/mimxrt1176/cm7`:
+
+.. code-block:: shell
+
+   west twister -v -p mimxrt1170_evk@B/mimxrt1176/cm7 --device-testing --device-serial COM4 -T tests/bluetooth/classic/sdp_c -O sdp_c --force-platform --west-flash --west-runner=jlink -X usb_hci:usb:0
+
+.. _bumble:
+   https://google.github.io/bumble/getting_started.html
+
+.. _hci transport:
+   https://google.github.io/bumble/transports/index.html
+
+.. _bumble platforms:
+   https://google.github.io/bumble/platforms/index.html
+
+.. _WinUSB driver:
+   https://google.github.io/bumble/platforms/windows.html
diff --git a/tests/bluetooth/classic/sdp_c/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/tests/bluetooth/classic/sdp_c/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf
new file mode 100644
index 00000000000..289b5a59738
--- /dev/null
+++ b/tests/bluetooth/classic/sdp_c/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf
@@ -0,0 +1,10 @@
+#select NXP NW612 Chipset
+CONFIG_BT_NXP_NW612=y
+
+CONFIG_BT_SETTINGS=n
+CONFIG_FLASH=n
+CONFIG_FLASH_MAP=n
+CONFIG_NVS=n
+CONFIG_SETTINGS=n
+
+CONFIG_ENTROPY_GENERATOR=y
diff --git a/tests/bluetooth/classic/sdp_c/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/tests/bluetooth/classic/sdp_c/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
new file mode 100644
index 00000000000..96ef63ad60b
--- /dev/null
+++ b/tests/bluetooth/classic/sdp_c/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,sram = &dtcm;
+	};
+};
diff --git a/tests/bluetooth/classic/sdp_c/prj.conf b/tests/bluetooth/classic/sdp_c/prj.conf
new file mode 100644
index 00000000000..c202e90f9aa
--- /dev/null
+++ b/tests/bluetooth/classic/sdp_c/prj.conf
@@ -0,0 +1,12 @@
+CONFIG_BT=y
+CONFIG_BT_CLASSIC=y
+CONFIG_BT_SHELL=y
+CONFIG_LOG=y
+CONFIG_ZTEST=y
+
+CONFIG_BT_RFCOMM=y
+
+CONFIG_BT_DEVICE_NAME="sdp_client"
+
+CONFIG_BT_CREATE_CONN_TIMEOUT=30
+CONFIG_BT_PAGE_TIMEOUT=0xFFFF
diff --git a/tests/bluetooth/classic/sdp_c/pytest/conftest.py b/tests/bluetooth/classic/sdp_c/pytest/conftest.py
new file mode 100644
index 00000000000..aae74a19cfe
--- /dev/null
+++ b/tests/bluetooth/classic/sdp_c/pytest/conftest.py
@@ -0,0 +1,57 @@
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+import logging
+import re
+
+import pytest
+from twister_harness import DeviceAdapter, Shell
+
+logger = logging.getLogger(__name__)
+
+
+def pytest_addoption(parser) -> None:
+    """Add local parser options to pytest."""
+    parser.addoption('--hci-transport', default=None, help='Configuration HCI transport for bumble')
+
+
+@pytest.fixture(name='initialize', scope='session')
+def fixture_initialize(request, shell: Shell, dut: DeviceAdapter):
+    """Session initializtion"""
+    # Get HCI transport for bumble
+    hci = request.config.getoption('--hci-transport')
+
+    if hci is None:
+        for fixture in dut.device_config.fixtures:
+            if fixture.startswith('usb_hci:'):
+                hci = fixture.split(sep=':', maxsplit=1)[1]
+                break
+
+    assert hci is not None
+
+    lines = shell.exec_command("bt init")
+    lines = dut.readlines_until("Bluetooth initialized")
+    regex = r'Identity: *(?P<bd_addr>(.*?):(.*?):(.*?):(.*?):(.*?):(.*?)*\((.*?)\))'
+    bd_addr = None
+    for line in lines:
+        logger.info(f"Shell log {line}")
+        m = re.search(regex, line)
+        if m:
+            bd_addr = m.group('bd_addr')
+
+    if bd_addr is None:
+        logger.error('Fail to get IUT BD address')
+        raise AssertionError
+
+    lines = shell.exec_command("br pscan on")
+    lines = shell.exec_command("br iscan on")
+    logger.info('initialized')
+    return hci, bd_addr
+
+
+@pytest.fixture
+def sdp_client_dut(initialize):
+    logger.info('Start running testcase')
+    yield initialize
+    logger.info('Done')
diff --git a/tests/bluetooth/classic/sdp_c/pytest/test_sdp.py b/tests/bluetooth/classic/sdp_c/pytest/test_sdp.py
new file mode 100644
index 00000000000..a81a394a0d2
--- /dev/null
+++ b/tests/bluetooth/classic/sdp_c/pytest/test_sdp.py
@@ -0,0 +1,968 @@
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+import asyncio
+import logging
+import sys
+
+from bumble.core import (
+    BT_ADVANCED_AUDIO_DISTRIBUTION_SERVICE,
+    BT_AUDIO_SINK_SERVICE,
+    BT_AUDIO_SOURCE_SERVICE,
+    BT_AV_REMOTE_CONTROL_CONTROLLER_SERVICE,
+    BT_AV_REMOTE_CONTROL_SERVICE,
+    BT_AV_REMOTE_CONTROL_TARGET_SERVICE,
+    BT_AVCTP_PROTOCOL_ID,
+    BT_AVDTP_PROTOCOL_ID,
+    BT_BR_EDR_TRANSPORT,
+    BT_GENERIC_AUDIO_SERVICE,
+    BT_HANDSFREE_SERVICE,
+    BT_L2CAP_PROTOCOL_ID,
+    BT_RFCOMM_PROTOCOL_ID,
+)
+from bumble.device import Device
+from bumble.hci import Address, HCI_Write_Page_Timeout_Command
+from bumble.sdp import (
+    SDP_BLUETOOTH_PROFILE_DESCRIPTOR_LIST_ATTRIBUTE_ID,
+    SDP_BROWSE_GROUP_LIST_ATTRIBUTE_ID,
+    SDP_PROTOCOL_DESCRIPTOR_LIST_ATTRIBUTE_ID,
+    SDP_PUBLIC_BROWSE_ROOT,
+    SDP_SERVICE_CLASS_ID_LIST_ATTRIBUTE_ID,
+    SDP_SERVICE_RECORD_HANDLE_ATTRIBUTE_ID,
+    SDP_SUPPORTED_FEATURES_ATTRIBUTE_ID,
+    DataElement,
+    ServiceAttribute,
+)
+from bumble.snoop import BtSnooper
+from bumble.transport import open_transport_or_link
+from twister_harness import DeviceAdapter, Shell
+
+logger = logging.getLogger(__name__)
+
+AVDTP_PSM = 0x0019
+AVDTP_VERSION = 0x0100
+
+SDP_SERVICE_RECORDS_A2DP = {
+    0x00010001: [
+        ServiceAttribute(
+            SDP_SERVICE_RECORD_HANDLE_ATTRIBUTE_ID,
+            DataElement.unsigned_integer_32(0x00010001),
+        ),
+        ServiceAttribute(
+            SDP_BROWSE_GROUP_LIST_ATTRIBUTE_ID,
+            DataElement.sequence([DataElement.uuid(SDP_PUBLIC_BROWSE_ROOT)]),
+        ),
+        ServiceAttribute(
+            SDP_SERVICE_CLASS_ID_LIST_ATTRIBUTE_ID,
+            DataElement.sequence([DataElement.uuid(BT_AUDIO_SOURCE_SERVICE)]),
+        ),
+        ServiceAttribute(
+            SDP_PROTOCOL_DESCRIPTOR_LIST_ATTRIBUTE_ID,
+            DataElement.sequence(
+                [
+                    DataElement.sequence(
+                        [
+                            DataElement.uuid(BT_L2CAP_PROTOCOL_ID),
+                            DataElement.unsigned_integer_16(AVDTP_PSM),
+                        ]
+                    ),
+                    DataElement.sequence(
+                        [
+                            DataElement.uuid(BT_AVDTP_PROTOCOL_ID),
+                            DataElement.unsigned_integer_16(AVDTP_VERSION),
+                        ]
+                    ),
+                ]
+            ),
+        ),
+        ServiceAttribute(
+            SDP_BLUETOOTH_PROFILE_DESCRIPTOR_LIST_ATTRIBUTE_ID,
+            DataElement.sequence(
+                [
+                    DataElement.sequence(
+                        [
+                            DataElement.uuid(BT_ADVANCED_AUDIO_DISTRIBUTION_SERVICE),
+                            DataElement.unsigned_integer_16(AVDTP_VERSION),
+                        ]
+                    )
+                ]
+            ),
+        ),
+    ]
+}
+
+RFCOMM_CHANNEL = 1
+HFP_VERSION = 0x0108
+HFP_FEATURES = 0x00
+
+SDP_SERVICE_RECORDS_HFP = {
+    0x00010002: [
+        ServiceAttribute(
+            SDP_SERVICE_RECORD_HANDLE_ATTRIBUTE_ID,
+            DataElement.unsigned_integer_32(0x00010002),
+        ),
+        ServiceAttribute(
+            SDP_SERVICE_CLASS_ID_LIST_ATTRIBUTE_ID,
+            DataElement.sequence(
+                [
+                    DataElement.uuid(BT_HANDSFREE_SERVICE),
+                    DataElement.uuid(BT_GENERIC_AUDIO_SERVICE),
+                ]
+            ),
+        ),
+        ServiceAttribute(
+            SDP_PROTOCOL_DESCRIPTOR_LIST_ATTRIBUTE_ID,
+            DataElement.sequence(
+                [
+                    DataElement.sequence([DataElement.uuid(BT_L2CAP_PROTOCOL_ID)]),
+                    DataElement.sequence(
+                        [
+                            DataElement.uuid(BT_RFCOMM_PROTOCOL_ID),
+                            DataElement.unsigned_integer_8(RFCOMM_CHANNEL),
+                        ]
+                    ),
+                ]
+            ),
+        ),
+        ServiceAttribute(
+            SDP_BLUETOOTH_PROFILE_DESCRIPTOR_LIST_ATTRIBUTE_ID,
+            DataElement.sequence(
+                [
+                    DataElement.sequence(
+                        [
+                            DataElement.uuid(BT_HANDSFREE_SERVICE),
+                            DataElement.unsigned_integer_16(HFP_VERSION),
+                        ]
+                    )
+                ]
+            ),
+        ),
+        ServiceAttribute(
+            SDP_SUPPORTED_FEATURES_ATTRIBUTE_ID,
+            DataElement.unsigned_integer_16(HFP_FEATURES),
+        ),
+    ]
+}
+
+SDP_SERVICE_ONE_RECORD = SDP_SERVICE_RECORDS_A2DP
+
+AVCTP_PSM = 0x0017
+AVCTP_VERSION = 0x0104
+AVRCP_VERSION = 0x0106
+AVRCP_TARGET_FEATURE = 0
+
+SDP_SERVICE_RECORDS_AVRCP_TARGET = {
+    0x00010003: [
+        ServiceAttribute(
+            SDP_SERVICE_RECORD_HANDLE_ATTRIBUTE_ID,
+            DataElement.unsigned_integer_32(0x00010003),
+        ),
+        ServiceAttribute(
+            SDP_BROWSE_GROUP_LIST_ATTRIBUTE_ID,
+            DataElement.sequence([DataElement.uuid(SDP_PUBLIC_BROWSE_ROOT)]),
+        ),
+        ServiceAttribute(
+            SDP_SERVICE_CLASS_ID_LIST_ATTRIBUTE_ID,
+            DataElement.sequence(
+                [
+                    DataElement.uuid(BT_AV_REMOTE_CONTROL_TARGET_SERVICE),
+                ]
+            ),
+        ),
+        ServiceAttribute(
+            SDP_PROTOCOL_DESCRIPTOR_LIST_ATTRIBUTE_ID,
+            DataElement.sequence(
+                [
+                    DataElement.sequence(
+                        [
+                            DataElement.uuid(BT_L2CAP_PROTOCOL_ID),
+                            DataElement.unsigned_integer_16(AVCTP_PSM),
+                        ]
+                    ),
+                    DataElement.sequence(
+                        [
+                            DataElement.uuid(BT_AVCTP_PROTOCOL_ID),
+                            DataElement.unsigned_integer_16(AVCTP_VERSION),
+                        ]
+                    ),
+                ]
+            ),
+        ),
+        ServiceAttribute(
+            SDP_BLUETOOTH_PROFILE_DESCRIPTOR_LIST_ATTRIBUTE_ID,
+            DataElement.sequence(
+                [
+                    DataElement.sequence(
+                        [
+                            DataElement.uuid(BT_AV_REMOTE_CONTROL_SERVICE),
+                            DataElement.unsigned_integer_16(AVRCP_VERSION),
+                        ]
+                    ),
+                ]
+            ),
+        ),
+        ServiceAttribute(
+            SDP_SUPPORTED_FEATURES_ATTRIBUTE_ID,
+            DataElement.unsigned_integer_16(AVRCP_TARGET_FEATURE),
+        ),
+    ]
+}
+
+AVRCP_CONTROLLER_FEATURE = 0
+
+SDP_SERVICE_RECORDS_AVRCP_CONTROLLER = {
+    0x00010004: [
+        ServiceAttribute(
+            SDP_SERVICE_RECORD_HANDLE_ATTRIBUTE_ID,
+            DataElement.unsigned_integer_32(0x00010004),
+        ),
+        ServiceAttribute(
+            SDP_BROWSE_GROUP_LIST_ATTRIBUTE_ID,
+            DataElement.sequence([DataElement.uuid(SDP_PUBLIC_BROWSE_ROOT)]),
+        ),
+        ServiceAttribute(
+            SDP_SERVICE_CLASS_ID_LIST_ATTRIBUTE_ID,
+            DataElement.sequence(
+                [
+                    DataElement.uuid(BT_AV_REMOTE_CONTROL_SERVICE),
+                    DataElement.uuid(BT_AV_REMOTE_CONTROL_CONTROLLER_SERVICE),
+                ]
+            ),
+        ),
+        ServiceAttribute(
+            SDP_PROTOCOL_DESCRIPTOR_LIST_ATTRIBUTE_ID,
+            DataElement.sequence(
+                [
+                    DataElement.sequence(
+                        [
+                            DataElement.uuid(BT_L2CAP_PROTOCOL_ID),
+                            DataElement.unsigned_integer_16(AVCTP_PSM),
+                        ]
+                    ),
+                    DataElement.sequence(
+                        [
+                            DataElement.uuid(BT_AVCTP_PROTOCOL_ID),
+                            DataElement.unsigned_integer_16(AVCTP_VERSION),
+                        ]
+                    ),
+                ]
+            ),
+        ),
+        ServiceAttribute(
+            SDP_BLUETOOTH_PROFILE_DESCRIPTOR_LIST_ATTRIBUTE_ID,
+            DataElement.sequence(
+                [
+                    DataElement.sequence(
+                        [
+                            DataElement.uuid(BT_AV_REMOTE_CONTROL_SERVICE),
+                            DataElement.unsigned_integer_16(AVRCP_VERSION),
+                        ]
+                    ),
+                ]
+            ),
+        ),
+        ServiceAttribute(
+            SDP_SUPPORTED_FEATURES_ATTRIBUTE_ID,
+            DataElement.unsigned_integer_16(AVRCP_CONTROLLER_FEATURE),
+        ),
+    ]
+}
+
+SDP_SERVICE_RECORDS_A2DP_SINK = {
+    0x00010005: [
+        ServiceAttribute(
+            SDP_SERVICE_RECORD_HANDLE_ATTRIBUTE_ID,
+            DataElement.unsigned_integer_32(0x00010005),
+        ),
+        ServiceAttribute(
+            SDP_BROWSE_GROUP_LIST_ATTRIBUTE_ID,
+            DataElement.sequence([DataElement.uuid(SDP_PUBLIC_BROWSE_ROOT)]),
+        ),
+        ServiceAttribute(
+            SDP_SERVICE_CLASS_ID_LIST_ATTRIBUTE_ID,
+            DataElement.sequence([DataElement.uuid(BT_AUDIO_SINK_SERVICE)]),
+        ),
+        ServiceAttribute(
+            SDP_PROTOCOL_DESCRIPTOR_LIST_ATTRIBUTE_ID,
+            DataElement.sequence(
+                [
+                    DataElement.sequence(
+                        [
+                            DataElement.uuid(BT_L2CAP_PROTOCOL_ID),
+                            DataElement.unsigned_integer_16(AVDTP_PSM),
+                        ]
+                    ),
+                    DataElement.sequence(
+                        [
+                            DataElement.uuid(BT_AVDTP_PROTOCOL_ID),
+                            DataElement.unsigned_integer_16(AVDTP_VERSION),
+                        ]
+                    ),
+                ]
+            ),
+        ),
+        ServiceAttribute(
+            SDP_BLUETOOTH_PROFILE_DESCRIPTOR_LIST_ATTRIBUTE_ID,
+            DataElement.sequence(
+                [
+                    DataElement.sequence(
+                        [
+                            DataElement.uuid(BT_ADVANCED_AUDIO_DISTRIBUTION_SERVICE),
+                            DataElement.unsigned_integer_16(AVDTP_VERSION),
+                        ]
+                    )
+                ]
+            ),
+        ),
+    ]
+}
+
+
+async def wait_for_shell_response(dut, message):
+    found = False
+    lines = []
+    try:
+        while found is False:
+            read_lines = dut.readlines()
+            for line in read_lines:
+                logger.info(f'{str(line)}')
+                if message in line:
+                    found = True
+                    break
+            lines = lines + read_lines
+            await asyncio.sleep(1)
+    except Exception as e:
+        logger.error(f'{e}!', exc_info=True)
+        raise e
+    return found, lines
+
+
+async def device_power_on(device) -> None:
+    while True:
+        try:
+            await device.power_on()
+            break
+        except Exception:
+            continue
+
+
+async def sdp_ssa_discover_no_record(hci_port, shell, dut, address) -> None:
+    logger.info('<<< SDP Discovery ...')
+    async with await open_transport_or_link(hci_port) as hci_transport:
+        device = Device.with_hci(
+            'Bumble',
+            Address('F0:F1:F2:F3:F4:F5'),
+            hci_transport.source,
+            hci_transport.sink,
+        )
+        device.classic_enabled = True
+        device.le_enabled = False
+        # No SDP Record
+        # device.sdp_service_records = SDP_SERVICE_RECORDS
+        with open(f"bumble_hci_{sys._getframe().f_code.co_name}.log", "wb") as snoop_file:
+            device.host.snooper = BtSnooper(snoop_file)
+            await device_power_on(device)
+            await device.send_command(HCI_Write_Page_Timeout_Command(page_timeout=0xFFFF))
+
+            target_address = address.split(" ")[0]
+            logger.info(f'=== Connecting to {target_address}...')
+            try:
+                connection = await device.connect(target_address, transport=BT_BR_EDR_TRANSPORT)
+                logger.info(f'=== Connected to {connection.peer_address}!')
+            except Exception as e:
+                logger.error(f'Fail to connect to {target_address}!')
+                raise e
+
+            # Discover SDP Record
+            shell.exec_command(f"sdp_client ssa_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()}")
+            found, lines = await wait_for_shell_response(dut, "No SDP Record")
+            logger.info(f'{lines}')
+            assert found is True
+
+
+async def sdp_ssa_discover_one_record(hci_port, shell, dut, address) -> None:
+    logger.info('<<< SDP Discovery ...')
+    async with await open_transport_or_link(hci_port) as hci_transport:
+        device = Device.with_hci(
+            'Bumble',
+            Address('F0:F1:F2:F3:F4:F5'),
+            hci_transport.source,
+            hci_transport.sink,
+        )
+        device.classic_enabled = True
+        device.le_enabled = False
+        device.sdp_service_records = SDP_SERVICE_ONE_RECORD
+        with open(f"bumble_hci_{sys._getframe().f_code.co_name}.log", "wb") as snoop_file:
+            device.host.snooper = BtSnooper(snoop_file)
+            await device_power_on(device)
+            await device.send_command(HCI_Write_Page_Timeout_Command(page_timeout=0xFFFF))
+
+            target_address = address.split(" ")[0]
+            logger.info(f'=== Connecting to {target_address}...')
+            try:
+                connection = await device.connect(target_address, transport=BT_BR_EDR_TRANSPORT)
+                logger.info(f'=== Connected to {connection.peer_address}!')
+            except Exception as e:
+                logger.error(f'Fail to connect to {target_address}!')
+                raise e
+
+            # Discover SDP Record
+            shell.exec_command(f"sdp_client ssa_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()}")
+            found, lines = await wait_for_shell_response(dut, "SDP Discovery Done")
+            assert found is True
+
+            found = False
+            for line in lines:
+                if "PROTOCOL:" in line and "L2CAP" in line.split(':')[1]:
+                    assert int(line.split(':')[2]) == AVDTP_PSM
+                    found = True
+
+            logger.info(f'Rsp: PROTOCOL: L2CAP: {AVDTP_PSM} is found? {found}')
+            assert found is True
+
+            version = BT_ADVANCED_AUDIO_DISTRIBUTION_SERVICE.to_hex_str()
+
+            found = False
+            for line in lines:
+                if "VERSION:" in line:
+                    # logger.info(f"{version}")
+                    assert int(line.split(':')[1], base=16) == int(version, base=16)
+                    assert int(line.split(':')[2]) == AVDTP_VERSION
+                    found = True
+
+            logger.info(f'Rsp: VER: {version}: {AVDTP_VERSION} is found? {found}')
+            assert found is True
+
+
+SDP_SERVICE_TWO_RECORDS = {**SDP_SERVICE_RECORDS_A2DP, **SDP_SERVICE_RECORDS_HFP}
+
+
+async def sdp_ssa_discover_two_records(hci_port, shell, dut, address) -> None:
+    logger.info('<<< SDP Discovery ...')
+    async with await open_transport_or_link(hci_port) as hci_transport:
+        device = Device.with_hci(
+            'Bumble',
+            Address('F0:F1:F2:F3:F4:F5'),
+            hci_transport.source,
+            hci_transport.sink,
+        )
+        device.classic_enabled = True
+        device.le_enabled = False
+        device.sdp_service_records = SDP_SERVICE_TWO_RECORDS
+        with open(f"bumble_hci_{sys._getframe().f_code.co_name}.log", "wb") as snoop_file:
+            device.host.snooper = BtSnooper(snoop_file)
+            await device_power_on(device)
+            await device.send_command(HCI_Write_Page_Timeout_Command(page_timeout=0xFFFF))
+
+            target_address = address.split(" ")[0]
+            logger.info(f'=== Connecting to {target_address}...')
+            try:
+                connection = await device.connect(target_address, transport=BT_BR_EDR_TRANSPORT)
+                logger.info(f'=== Connected to {connection.peer_address}!')
+            except Exception as e:
+                logger.error(f'Fail to connect to {target_address}!')
+                raise e
+
+            # Discover SDP Record
+            shell.exec_command(f"sdp_client ssa_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()}")
+            found, lines = await wait_for_shell_response(dut, "SDP Discovery Done")
+            assert found is True
+
+            found = False
+            for line in lines:
+                if "PROTOCOL:" in line and "RFCOMM" in line.split(':')[1]:
+                    assert int(line.split(':')[2]) == RFCOMM_CHANNEL
+                    found = True
+
+            logger.info(f'Rsp: PROTOCOL: RFCOMM: {RFCOMM_CHANNEL} is found? {found}')
+            assert found is True
+
+            found = False
+            for line in lines:
+                if "VERSION:" in line and int(line.split(':')[1], base=16) == int(
+                    BT_HANDSFREE_SERVICE.to_hex_str(), base=16
+                ):
+                    assert int(line.split(':')[2]) == HFP_VERSION
+                    found = True
+
+            logger.info(
+                f'Rsp: VER: {BT_HANDSFREE_SERVICE.to_hex_str()}: {HFP_VERSION} is found? {found}'
+            )
+            assert found is True
+
+            found = False
+            for line in lines:
+                if "FEATURE:" in line:
+                    assert int(line.split(':')[1], base=16) == HFP_FEATURES
+                    found = True
+
+            logger.info(f'Rsp: FEATURE: {HFP_FEATURES} is found? {found}')
+            assert found is True
+
+
+SDP_SERVICE_MULTIPLE_RECORDS = {
+    **SDP_SERVICE_RECORDS_A2DP,
+    **SDP_SERVICE_RECORDS_HFP,
+    **SDP_SERVICE_RECORDS_AVRCP_TARGET,
+}
+
+
+async def sdp_ssa_discover_multiple_records(hci_port, shell, dut, address) -> None:
+    logger.info('<<< SDP Discovery ...')
+    async with await open_transport_or_link(hci_port) as hci_transport:
+        device = Device.with_hci(
+            'Bumble',
+            Address('F0:F1:F2:F3:F4:F5'),
+            hci_transport.source,
+            hci_transport.sink,
+        )
+        device.classic_enabled = True
+        device.le_enabled = False
+        device.sdp_service_records = SDP_SERVICE_MULTIPLE_RECORDS
+        with open(f"bumble_hci_{sys._getframe().f_code.co_name}.log", "wb") as snoop_file:
+            device.host.snooper = BtSnooper(snoop_file)
+            await device_power_on(device)
+            await device.send_command(HCI_Write_Page_Timeout_Command(page_timeout=0xFFFF))
+
+            target_address = address.split(" ")[0]
+            logger.info(f'=== Connecting to {target_address}...')
+            try:
+                connection = await device.connect(target_address, transport=BT_BR_EDR_TRANSPORT)
+                logger.info(f'=== Connected to {connection.peer_address}!')
+            except Exception as e:
+                logger.error(f'Fail to connect to {target_address}!')
+                raise e
+
+            # Discover SDP Record
+            shell.exec_command(f"sdp_client ssa_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()}")
+            found, lines = await wait_for_shell_response(dut, "SDP Discovery Done")
+            logger.info(f'{lines}')
+            assert found is True
+
+
+async def sdp_ss_discover_no_record(hci_port, shell, dut, address) -> None:
+    logger.info('<<< SDP Discovery ...')
+    async with await open_transport_or_link(hci_port) as hci_transport:
+        device = Device.with_hci(
+            'Bumble',
+            Address('F0:F1:F2:F3:F4:F5'),
+            hci_transport.source,
+            hci_transport.sink,
+        )
+        device.classic_enabled = True
+        device.le_enabled = False
+        # No SDP Record
+        # device.sdp_service_records = SDP_SERVICE_RECORDS
+        with open(f"bumble_hci_{sys._getframe().f_code.co_name}.log", "wb") as snoop_file:
+            device.host.snooper = BtSnooper(snoop_file)
+            await device_power_on(device)
+            await device.send_command(HCI_Write_Page_Timeout_Command(page_timeout=0xFFFF))
+
+            target_address = address.split(" ")[0]
+            logger.info(f'=== Connecting to {target_address}...')
+            try:
+                connection = await device.connect(target_address, transport=BT_BR_EDR_TRANSPORT)
+                logger.info(f'=== Connected to {connection.peer_address}!')
+            except Exception as e:
+                logger.error(f'Fail to connect to {target_address}!')
+                raise e
+
+            # Discover SDP Record
+            shell.exec_command(f"sdp_client ss_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()}")
+            found, lines = await wait_for_shell_response(dut, "No SDP Record")
+            logger.info(f'{lines}')
+            assert found is True
+
+
+async def sdp_ss_discover_one_record(hci_port, shell, dut, address) -> None:
+    logger.info('<<< SDP Discovery ...')
+    async with await open_transport_or_link(hci_port) as hci_transport:
+        device = Device.with_hci(
+            'Bumble',
+            Address('F0:F1:F2:F3:F4:F5'),
+            hci_transport.source,
+            hci_transport.sink,
+        )
+        device.classic_enabled = True
+        device.le_enabled = False
+        device.sdp_service_records = SDP_SERVICE_ONE_RECORD
+        with open(f"bumble_hci_{sys._getframe().f_code.co_name}.log", "wb") as snoop_file:
+            device.host.snooper = BtSnooper(snoop_file)
+            await device_power_on(device)
+            await device.send_command(HCI_Write_Page_Timeout_Command(page_timeout=0xFFFF))
+
+            target_address = address.split(" ")[0]
+            logger.info(f'=== Connecting to {target_address}...')
+            try:
+                connection = await device.connect(target_address, transport=BT_BR_EDR_TRANSPORT)
+                logger.info(f'=== Connected to {connection.peer_address}!')
+            except Exception as e:
+                logger.error(f'Fail to connect to {target_address}!')
+                raise e
+
+            # Discover SDP Record
+            shell.exec_command(f"sdp_client ss_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()}")
+            found, lines = await wait_for_shell_response(dut, "SDP Discovery Done")
+            logger.info(f'{lines}')
+            assert found is True
+
+            count = 0
+            for line in lines:
+                if "RAW:" in line and device.sdp_service_records.get(
+                    int(line.split(':')[1], base=16)
+                ):
+                    count = count + 1
+
+            logger.info(f'Rsp: Service Record Handle count is {count}')
+            assert count == 1
+
+
+async def sdp_ss_discover_two_records(hci_port, shell, dut, address) -> None:
+    logger.info('<<< SDP Discovery ...')
+    async with await open_transport_or_link(hci_port) as hci_transport:
+        device = Device.with_hci(
+            'Bumble',
+            Address('F0:F1:F2:F3:F4:F5'),
+            hci_transport.source,
+            hci_transport.sink,
+        )
+        device.classic_enabled = True
+        device.le_enabled = False
+        device.sdp_service_records = SDP_SERVICE_TWO_RECORDS
+        with open(f"bumble_hci_{sys._getframe().f_code.co_name}.log", "wb") as snoop_file:
+            device.host.snooper = BtSnooper(snoop_file)
+            await device_power_on(device)
+            await device.send_command(HCI_Write_Page_Timeout_Command(page_timeout=0xFFFF))
+
+            target_address = address.split(" ")[0]
+            logger.info(f'=== Connecting to {target_address}...')
+            try:
+                connection = await device.connect(target_address, transport=BT_BR_EDR_TRANSPORT)
+                logger.info(f'=== Connected to {connection.peer_address}!')
+            except Exception as e:
+                logger.error(f'Fail to connect to {target_address}!')
+                raise e
+
+            # Discover SDP Record
+            shell.exec_command(f"sdp_client ss_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()}")
+            found, lines = await wait_for_shell_response(dut, "SDP Discovery Done")
+            logger.info(f'{lines}')
+            assert found is True
+
+            count = 0
+            for line in lines:
+                if "RAW:" in line and device.sdp_service_records.get(
+                    int(line.split(':')[1], base=16)
+                ):
+                    count = count + 1
+
+            logger.info(f'Rsp: Service Record Handle count is {count}')
+            assert count == 2
+
+
+async def sdp_ss_discover_multiple_records(hci_port, shell, dut, address) -> None:
+    logger.info('<<< SDP Discovery ...')
+    async with await open_transport_or_link(hci_port) as hci_transport:
+        device = Device.with_hci(
+            'Bumble',
+            Address('F0:F1:F2:F3:F4:F5'),
+            hci_transport.source,
+            hci_transport.sink,
+        )
+        device.classic_enabled = True
+        device.le_enabled = False
+        device.sdp_service_records = SDP_SERVICE_MULTIPLE_RECORDS
+        with open(f"bumble_hci_{sys._getframe().f_code.co_name}.log", "wb") as snoop_file:
+            device.host.snooper = BtSnooper(snoop_file)
+            await device_power_on(device)
+            await device.send_command(HCI_Write_Page_Timeout_Command(page_timeout=0xFFFF))
+
+            target_address = address.split(" ")[0]
+            logger.info(f'=== Connecting to {target_address}...')
+            try:
+                connection = await device.connect(target_address, transport=BT_BR_EDR_TRANSPORT)
+                logger.info(f'=== Connected to {connection.peer_address}!')
+            except Exception as e:
+                logger.error(f'Fail to connect to {target_address}!')
+                raise e
+
+            # Discover SDP Record
+            shell.exec_command(f"sdp_client ss_discovery {BT_L2CAP_PROTOCOL_ID.to_hex_str()}")
+            found, lines = await wait_for_shell_response(dut, "SDP Discovery Done")
+            logger.info(f'{lines}')
+            assert found is True
+
+            count = 0
+            for line in lines:
+                if "RAW:" in line and device.sdp_service_records.get(
+                    int(line.split(':')[1], base=16)
+                ):
+                    count = count + 1
+
+            logger.info(f'Rsp: Service Record Handle count is {count}')
+            assert count == 3
+
+
+async def sdp_sa_discover_no_record(hci_port, shell, dut, address) -> None:
+    logger.info('<<< SDP Discovery ...')
+    async with await open_transport_or_link(hci_port) as hci_transport:
+        device = Device.with_hci(
+            'Bumble',
+            Address('F0:F1:F2:F3:F4:F5'),
+            hci_transport.source,
+            hci_transport.sink,
+        )
+        device.classic_enabled = True
+        device.le_enabled = False
+        # No SDP Record
+        # device.sdp_service_records = SDP_SERVICE_RECORDS
+        with open(f"bumble_hci_{sys._getframe().f_code.co_name}.log", "wb") as snoop_file:
+            device.host.snooper = BtSnooper(snoop_file)
+            await device_power_on(device)
+            await device.send_command(HCI_Write_Page_Timeout_Command(page_timeout=0xFFFF))
+
+            target_address = address.split(" ")[0]
+            logger.info(f'=== Connecting to {target_address}...')
+            try:
+                connection = await device.connect(target_address, transport=BT_BR_EDR_TRANSPORT)
+                logger.info(f'=== Connected to {connection.peer_address}!')
+            except Exception as e:
+                logger.error(f'Fail to connect to {target_address}!')
+                raise e
+
+            # Discover SDP Record
+            shell.exec_command("sdp_client sa_discovery 00010001")
+            found, lines = await wait_for_shell_response(dut, "No SDP Record")
+            logger.info(f'{lines}')
+            assert found is True
+
+
+async def sdp_sa_discover_one_record(hci_port, shell, dut, address) -> None:
+    logger.info('<<< SDP Discovery ...')
+    async with await open_transport_or_link(hci_port) as hci_transport:
+        device = Device.with_hci(
+            'Bumble',
+            Address('F0:F1:F2:F3:F4:F5'),
+            hci_transport.source,
+            hci_transport.sink,
+        )
+        device.classic_enabled = True
+        device.le_enabled = False
+        device.sdp_service_records = SDP_SERVICE_ONE_RECORD
+        with open(f"bumble_hci_{sys._getframe().f_code.co_name}.log", "wb") as snoop_file:
+            device.host.snooper = BtSnooper(snoop_file)
+            await device_power_on(device)
+            await device.send_command(HCI_Write_Page_Timeout_Command(page_timeout=0xFFFF))
+
+            target_address = address.split(" ")[0]
+            logger.info(f'=== Connecting to {target_address}...')
+            try:
+                connection = await device.connect(target_address, transport=BT_BR_EDR_TRANSPORT)
+                logger.info(f'=== Connected to {connection.peer_address}!')
+            except Exception as e:
+                logger.error(f'Fail to connect to {target_address}!')
+                raise e
+
+            # Discover SDP Record
+            shell.exec_command("sdp_client sa_discovery 00010001")
+            found, lines = await wait_for_shell_response(dut, "SDP Discovery Done")
+            assert found is True
+
+            found = False
+            for line in lines:
+                if "PROTOCOL:" in line and "L2CAP" in line.split(':')[1]:
+                    assert int(line.split(':')[2]) == AVDTP_PSM
+                    found = True
+
+            logger.info(f'Rsp: PROTOCOL: L2CAP: {AVDTP_PSM} is found? {found}')
+            assert found is True
+
+            version = BT_ADVANCED_AUDIO_DISTRIBUTION_SERVICE.to_hex_str()
+
+            found = False
+            for line in lines:
+                if "VERSION:" in line:
+                    # logger.info(f"{version}")
+                    assert int(line.split(':')[1], base=16) == int(version, base=16)
+                    assert int(line.split(':')[2]) == AVDTP_VERSION
+                    found = True
+
+            logger.info(f'Rsp: VER: {version}: {AVDTP_VERSION} is found? {found}')
+            assert found is True
+
+
+async def sdp_sa_discover_two_records(hci_port, shell, dut, address) -> None:
+    logger.info('<<< SDP Discovery ...')
+    async with await open_transport_or_link(hci_port) as hci_transport:
+        device = Device.with_hci(
+            'Bumble',
+            Address('F0:F1:F2:F3:F4:F5'),
+            hci_transport.source,
+            hci_transport.sink,
+        )
+        device.classic_enabled = True
+        device.le_enabled = False
+        device.sdp_service_records = SDP_SERVICE_TWO_RECORDS
+        with open(f"bumble_hci_{sys._getframe().f_code.co_name}.log", "wb") as snoop_file:
+            device.host.snooper = BtSnooper(snoop_file)
+            await device_power_on(device)
+            await device.send_command(HCI_Write_Page_Timeout_Command(page_timeout=0xFFFF))
+
+            target_address = address.split(" ")[0]
+            logger.info(f'=== Connecting to {target_address}...')
+            try:
+                connection = await device.connect(target_address, transport=BT_BR_EDR_TRANSPORT)
+                logger.info(f'=== Connected to {connection.peer_address}!')
+            except Exception as e:
+                logger.error(f'Fail to connect to {target_address}!')
+                raise e
+
+            # Discover SDP Record
+            shell.exec_command("sdp_client sa_discovery 00010002")
+            found, lines = await wait_for_shell_response(dut, "SDP Discovery Done")
+            assert found is True
+
+            found = False
+            for line in lines:
+                if "PROTOCOL:" in line and "RFCOMM" in line.split(':')[1]:
+                    assert int(line.split(':')[2]) == RFCOMM_CHANNEL
+                    found = True
+
+            logger.info(f'Rsp: PROTOCOL: RFCOMM: {RFCOMM_CHANNEL} is found? {found}')
+            assert found is True
+
+            found = False
+            for line in lines:
+                if "VERSION:" in line and int(line.split(':')[1], base=16) == int(
+                    BT_HANDSFREE_SERVICE.to_hex_str(), base=16
+                ):
+                    assert int(line.split(':')[2]) == HFP_VERSION
+                    found = True
+
+            logger.info(
+                f'Rsp: VER: {BT_HANDSFREE_SERVICE.to_hex_str()}: {HFP_VERSION} is found? {found}'
+            )
+            assert found is True
+
+            found = False
+            for line in lines:
+                if "FEATURE:" in line:
+                    assert int(line.split(':')[1], base=16) == HFP_FEATURES
+                    found = True
+
+            logger.info(f'Rsp: FEATURE: {HFP_FEATURES} is found? {found}')
+            assert found is True
+
+
+async def sdp_sa_discover_multiple_records(hci_port, shell, dut, address) -> None:
+    logger.info('<<< SDP Discovery ...')
+    async with await open_transport_or_link(hci_port) as hci_transport:
+        device = Device.with_hci(
+            'Bumble',
+            Address('F0:F1:F2:F3:F4:F5'),
+            hci_transport.source,
+            hci_transport.sink,
+        )
+        device.classic_enabled = True
+        device.le_enabled = False
+        device.sdp_service_records = SDP_SERVICE_MULTIPLE_RECORDS
+        with open(f"bumble_hci_{sys._getframe().f_code.co_name}.log", "wb") as snoop_file:
+            device.host.snooper = BtSnooper(snoop_file)
+            await device_power_on(device)
+            await device.send_command(HCI_Write_Page_Timeout_Command(page_timeout=0xFFFF))
+
+            target_address = address.split(" ")[0]
+            logger.info(f'=== Connecting to {target_address}...')
+            try:
+                connection = await device.connect(target_address, transport=BT_BR_EDR_TRANSPORT)
+                logger.info(f'=== Connected to {connection.peer_address}!')
+            except Exception as e:
+                logger.error(f'Fail to connect to {target_address}!')
+                raise e
+
+            # Discover SDP Record
+            shell.exec_command("sdp_client sa_discovery 00010003")
+            found, lines = await wait_for_shell_response(dut, "SDP Discovery Done")
+            logger.info(f'{lines}')
+            assert found is True
+
+
+class TestSdpServer:
+    def test_sdp_ssa_discover_no_record(self, shell: Shell, dut: DeviceAdapter, sdp_client_dut):
+        """Test case to request SDP records. No SDP record registered."""
+        logger.info(f'test_sdp_ssa_discover_no_record {sdp_client_dut}')
+        hci, iut_address = sdp_client_dut
+        asyncio.run(sdp_ssa_discover_no_record(hci, shell, dut, iut_address))
+
+    def test_sdp_ssa_discover_one_record(self, shell: Shell, dut: DeviceAdapter, sdp_client_dut):
+        """Test case to request SDP records. One SDP record registered."""
+        logger.info(f'test_sdp_ssa_discover_one_record {sdp_client_dut}')
+        hci, iut_address = sdp_client_dut
+        asyncio.run(sdp_ssa_discover_one_record(hci, shell, dut, iut_address))
+
+    def test_sdp_ssa_discover_two_records(self, shell: Shell, dut: DeviceAdapter, sdp_client_dut):
+        """Test case to request SDP records. Two SDP record registered."""
+        logger.info(f'test_sdp_ssa_discover_two_records {sdp_client_dut}')
+        hci, iut_address = sdp_client_dut
+        asyncio.run(sdp_ssa_discover_two_records(hci, shell, dut, iut_address))
+
+    def test_sdp_ssa_discover_multiple_records(
+        self, shell: Shell, dut: DeviceAdapter, sdp_client_dut
+    ):
+        """Test case to request SDP records. Multiple SDP record registered."""
+        logger.info(f'test_sdp_ssa_discover_multiple_records {sdp_client_dut}')
+        hci, iut_address = sdp_client_dut
+        asyncio.run(sdp_ssa_discover_multiple_records(hci, shell, dut, iut_address))
+
+    def test_sdp_ss_discover_no_record(self, shell: Shell, dut: DeviceAdapter, sdp_client_dut):
+        """Test case to request SDP records. No SDP record registered."""
+        logger.info(f'test_sdp_ss_discover_no_record {sdp_client_dut}')
+        hci, iut_address = sdp_client_dut
+        asyncio.run(sdp_ss_discover_no_record(hci, shell, dut, iut_address))
+
+    def test_sdp_ss_discover_one_record(self, shell: Shell, dut: DeviceAdapter, sdp_client_dut):
+        """Test case to request SDP records. One SDP record registered."""
+        logger.info(f'test_sdp_ss_discover_one_record {sdp_client_dut}')
+        hci, iut_address = sdp_client_dut
+        asyncio.run(sdp_ss_discover_one_record(hci, shell, dut, iut_address))
+
+    def test_sdp_ss_discover_two_records(self, shell: Shell, dut: DeviceAdapter, sdp_client_dut):
+        """Test case to request SDP records. Two SDP record registered."""
+        logger.info(f'test_sdp_ss_discover_two_records {sdp_client_dut}')
+        hci, iut_address = sdp_client_dut
+        asyncio.run(sdp_ss_discover_two_records(hci, shell, dut, iut_address))
+
+    def test_sdp_ss_discover_multiple_records(
+        self, shell: Shell, dut: DeviceAdapter, sdp_client_dut
+    ):
+        """Test case to request SDP records. Multiple SDP record registered."""
+        logger.info(f'test_sdp_ss_discover_multiple_records {sdp_client_dut}')
+        hci, iut_address = sdp_client_dut
+        asyncio.run(sdp_ss_discover_multiple_records(hci, shell, dut, iut_address))
+
+    def test_sdp_sa_discover_no_record(self, shell: Shell, dut: DeviceAdapter, sdp_client_dut):
+        """Test case to request SDP records. No SDP record registered."""
+        logger.info(f'test_sdp_sa_discover_no_record {sdp_client_dut}')
+        hci, iut_address = sdp_client_dut
+        asyncio.run(sdp_sa_discover_no_record(hci, shell, dut, iut_address))
+
+    def test_sdp_sa_discover_one_record(self, shell: Shell, dut: DeviceAdapter, sdp_client_dut):
+        """Test case to request SDP records. One SDP record registered."""
+        logger.info(f'test_sdp_sa_discover_one_record {sdp_client_dut}')
+        hci, iut_address = sdp_client_dut
+        asyncio.run(sdp_sa_discover_one_record(hci, shell, dut, iut_address))
+
+    def test_sdp_sa_discover_two_records(self, shell: Shell, dut: DeviceAdapter, sdp_client_dut):
+        """Test case to request SDP records. Two SDP record registered."""
+        logger.info(f'test_sdp_sa_discover_two_records {sdp_client_dut}')
+        hci, iut_address = sdp_client_dut
+        asyncio.run(sdp_sa_discover_two_records(hci, shell, dut, iut_address))
+
+    def test_sdp_sa_discover_multiple_records(
+        self, shell: Shell, dut: DeviceAdapter, sdp_client_dut
+    ):
+        """Test case to request SDP records. Multiple SDP record registered."""
+        logger.info(f'test_sdp_sa_discover_multiple_records {sdp_client_dut}')
+        hci, iut_address = sdp_client_dut
+        asyncio.run(sdp_sa_discover_multiple_records(hci, shell, dut, iut_address))
diff --git a/tests/bluetooth/classic/sdp_c/src/sdp_client.c b/tests/bluetooth/classic/sdp_c/src/sdp_client.c
new file mode 100644
index 00000000000..0621b61b86a
--- /dev/null
+++ b/tests/bluetooth/classic/sdp_c/src/sdp_client.c
@@ -0,0 +1,303 @@
+/* sdp_client.c - Bluetooth classic SDP client smoke test */
+
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdlib.h>
+
+#include <errno.h>
+#include <zephyr/types.h>
+#include <zephyr/kernel.h>
+#include <zephyr/sys/printk.h>
+#include <zephyr/sys/byteorder.h>
+
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/classic/rfcomm.h>
+#include <zephyr/bluetooth/classic/sdp.h>
+
+#include <zephyr/shell/shell.h>
+
+extern struct bt_conn *default_conn;
+
+static struct bt_sdp_discover_params sdp_discover;
+static union {
+	struct bt_uuid_16 u16;
+	struct bt_uuid_32 u32;
+	struct bt_uuid_128 u128;
+} sdp_discover_uuid;
+
+const uint16_t svclass_list[] = {
+	BT_SDP_SDP_SERVER_SVCLASS,
+	BT_SDP_BROWSE_GRP_DESC_SVCLASS,
+	BT_SDP_PUBLIC_BROWSE_GROUP,
+	BT_SDP_SERIAL_PORT_SVCLASS,
+	BT_SDP_LAN_ACCESS_SVCLASS,
+	BT_SDP_DIALUP_NET_SVCLASS,
+	BT_SDP_IRMC_SYNC_SVCLASS,
+	BT_SDP_OBEX_OBJPUSH_SVCLASS,
+	BT_SDP_OBEX_FILETRANS_SVCLASS,
+	BT_SDP_IRMC_SYNC_CMD_SVCLASS,
+	BT_SDP_HEADSET_SVCLASS,
+	BT_SDP_CORDLESS_TELEPHONY_SVCLASS,
+	BT_SDP_AUDIO_SOURCE_SVCLASS,
+	BT_SDP_AUDIO_SINK_SVCLASS,
+	BT_SDP_AV_REMOTE_TARGET_SVCLASS,
+	BT_SDP_ADVANCED_AUDIO_SVCLASS,
+	BT_SDP_AV_REMOTE_SVCLASS,
+	BT_SDP_AV_REMOTE_CONTROLLER_SVCLASS,
+	BT_SDP_INTERCOM_SVCLASS,
+	BT_SDP_FAX_SVCLASS,
+	BT_SDP_HEADSET_AGW_SVCLASS,
+	BT_SDP_WAP_SVCLASS,
+	BT_SDP_WAP_CLIENT_SVCLASS,
+	BT_SDP_PANU_SVCLASS,
+	BT_SDP_NAP_SVCLASS,
+	BT_SDP_GN_SVCLASS,
+	BT_SDP_DIRECT_PRINTING_SVCLASS,
+	BT_SDP_REFERENCE_PRINTING_SVCLASS,
+	BT_SDP_IMAGING_SVCLASS,
+	BT_SDP_IMAGING_RESPONDER_SVCLASS,
+	BT_SDP_IMAGING_ARCHIVE_SVCLASS,
+	BT_SDP_IMAGING_REFOBJS_SVCLASS,
+	BT_SDP_HANDSFREE_SVCLASS,
+	BT_SDP_HANDSFREE_AGW_SVCLASS,
+	BT_SDP_DIRECT_PRT_REFOBJS_SVCLASS,
+	BT_SDP_REFLECTED_UI_SVCLASS,
+	BT_SDP_BASIC_PRINTING_SVCLASS,
+	BT_SDP_PRINTING_STATUS_SVCLASS,
+	BT_SDP_HID_SVCLASS,
+	BT_SDP_HCR_SVCLASS,
+	BT_SDP_HCR_PRINT_SVCLASS,
+	BT_SDP_HCR_SCAN_SVCLASS,
+	BT_SDP_CIP_SVCLASS,
+	BT_SDP_VIDEO_CONF_GW_SVCLASS,
+	BT_SDP_UDI_MT_SVCLASS,
+	BT_SDP_UDI_TA_SVCLASS,
+	BT_SDP_AV_SVCLASS,
+	BT_SDP_SAP_SVCLASS,
+	BT_SDP_PBAP_PCE_SVCLASS,
+	BT_SDP_PBAP_PSE_SVCLASS,
+	BT_SDP_PBAP_SVCLASS,
+	BT_SDP_MAP_MSE_SVCLASS,
+	BT_SDP_MAP_MCE_SVCLASS,
+	BT_SDP_MAP_SVCLASS,
+	BT_SDP_GNSS_SVCLASS,
+	BT_SDP_GNSS_SERVER_SVCLASS,
+	BT_SDP_MPS_SC_SVCLASS,
+	BT_SDP_MPS_SVCLASS,
+	BT_SDP_PNP_INFO_SVCLASS,
+	BT_SDP_GENERIC_NETWORKING_SVCLASS,
+	BT_SDP_GENERIC_FILETRANS_SVCLASS,
+	BT_SDP_GENERIC_AUDIO_SVCLASS,
+	BT_SDP_GENERIC_TELEPHONY_SVCLASS,
+	BT_SDP_UPNP_SVCLASS,
+	BT_SDP_UPNP_IP_SVCLASS,
+	BT_SDP_UPNP_PAN_SVCLASS,
+	BT_SDP_UPNP_LAP_SVCLASS,
+	BT_SDP_UPNP_L2CAP_SVCLASS,
+	BT_SDP_VIDEO_SOURCE_SVCLASS,
+	BT_SDP_VIDEO_SINK_SVCLASS,
+	BT_SDP_VIDEO_DISTRIBUTION_SVCLASS,
+	BT_SDP_HDP_SVCLASS,
+	BT_SDP_HDP_SOURCE_SVCLASS,
+	BT_SDP_HDP_SINK_SVCLASS,
+	BT_SDP_GENERIC_ACCESS_SVCLASS,
+	BT_SDP_GENERIC_ATTRIB_SVCLASS,
+	BT_SDP_APPLE_AGENT_SVCLASS,
+};
+
+#define SDP_CLIENT_USER_BUF_LEN 4096
+NET_BUF_POOL_FIXED_DEFINE(sdp_client_pool, 1, SDP_CLIENT_USER_BUF_LEN,
+			  CONFIG_BT_CONN_TX_USER_DATA_SIZE, NULL);
+
+static bool sdp_record_found;
+
+static uint8_t sdp_discover_func(struct bt_conn *conn, struct bt_sdp_client_result *result,
+				 const struct bt_sdp_discover_params *params)
+{
+	int err;
+	uint16_t param;
+
+	if ((result == NULL) || (result->resp_buf == NULL) || (result->resp_buf->len == 0)) {
+		if (sdp_record_found) {
+			sdp_record_found = false;
+			printk("SDP Discovery Done\n");
+		} else {
+			printk("No SDP Record\n");
+		}
+		return BT_SDP_DISCOVER_UUID_STOP;
+	}
+
+	sdp_record_found = true;
+
+	printk("SDP Rsp Data:\n");
+	err = bt_sdp_get_proto_param(result->resp_buf, BT_SDP_PROTO_L2CAP, &param);
+	if (!err) {
+		printk("    PROTOCOL: L2CAP: %d\n", param);
+	}
+	err = bt_sdp_get_proto_param(result->resp_buf, BT_SDP_PROTO_RFCOMM, &param);
+	if (!err) {
+		printk("    PROTOCOL: RFCOMM: %d\n", param);
+	}
+	for (size_t i = 0; i < ARRAY_SIZE(svclass_list); i++) {
+		err = bt_sdp_get_profile_version(result->resp_buf, svclass_list[i], &param);
+		if (!err) {
+			printk("    VERSION: %04X: %d\n", svclass_list[i], param);
+		}
+	}
+	err = bt_sdp_get_features(result->resp_buf, &param);
+	if (!err) {
+		printk("    FEATURE: %04X\n", param);
+	}
+	printk("    RAW:");
+	for (uint16_t i = 0; i < result->resp_buf->len; i++) {
+		printk("%02X", result->resp_buf->data[i]);
+	}
+	printk("\n");
+
+	if (!result->next_record_hint) {
+		sdp_record_found = false;
+		printk("SDP Discovery Done\n");
+	}
+
+	return BT_SDP_DISCOVER_UUID_CONTINUE;
+}
+
+static int cmd_ssa_discovery(const struct shell *sh, size_t argc, char *argv[])
+{
+	int err;
+	size_t len;
+
+	len = strlen(argv[1]);
+
+	if (len == (BT_UUID_SIZE_16 * 2)) {
+		uint16_t val;
+
+		sdp_discover_uuid.u16.uuid.type = BT_UUID_TYPE_16;
+		hex2bin(argv[1], len, (uint8_t *)&val, sizeof(val));
+		sdp_discover_uuid.u16.val = sys_be16_to_cpu(val);
+		sdp_discover.uuid = &sdp_discover_uuid.u16.uuid;
+	} else if (len == (BT_UUID_SIZE_32 * 2)) {
+		uint32_t val;
+
+		sdp_discover_uuid.u32.uuid.type = BT_UUID_TYPE_32;
+		hex2bin(argv[1], len, (uint8_t *)&val, sizeof(val));
+		sdp_discover_uuid.u32.val = sys_be32_to_cpu(val);
+		sdp_discover.uuid = &sdp_discover_uuid.u32.uuid;
+	} else if (len == (BT_UUID_SIZE_128 * 2)) {
+		sdp_discover_uuid.u128.uuid.type = BT_UUID_TYPE_128;
+		hex2bin(argv[1], len, &sdp_discover_uuid.u128.val[0],
+			sizeof(sdp_discover_uuid.u128.val));
+		sdp_discover.uuid = &sdp_discover_uuid.u128.uuid;
+	} else {
+		shell_error(sh, "Invalid UUID");
+		return -ENOEXEC;
+	}
+
+	sdp_discover.func = sdp_discover_func;
+	sdp_discover.pool = &sdp_client_pool;
+	sdp_discover.type = BT_SDP_DISCOVER_SERVICE_SEARCH_ATTR;
+
+	err = bt_sdp_discover(default_conn, &sdp_discover);
+	if (err) {
+		shell_error(sh, "Fail to start SDP Discovery (err %d)", err);
+		return err;
+	}
+	return 0;
+}
+
+static int cmd_ss_discovery(const struct shell *sh, size_t argc, char *argv[])
+{
+	int err;
+	size_t len;
+
+	len = strlen(argv[1]);
+
+	if (len == (BT_UUID_SIZE_16 * 2)) {
+		uint16_t val;
+
+		sdp_discover_uuid.u16.uuid.type = BT_UUID_TYPE_16;
+		hex2bin(argv[1], len, (uint8_t *)&val, sizeof(val));
+		sdp_discover_uuid.u16.val = sys_be16_to_cpu(val);
+		sdp_discover.uuid = &sdp_discover_uuid.u16.uuid;
+	} else if (len == (BT_UUID_SIZE_32 * 2)) {
+		uint32_t val;
+
+		sdp_discover_uuid.u32.uuid.type = BT_UUID_TYPE_32;
+		hex2bin(argv[1], len, (uint8_t *)&val, sizeof(val));
+		sdp_discover_uuid.u32.val = sys_be32_to_cpu(val);
+		sdp_discover.uuid = &sdp_discover_uuid.u32.uuid;
+	} else if (len == (BT_UUID_SIZE_128 * 2)) {
+		sdp_discover_uuid.u128.uuid.type = BT_UUID_TYPE_128;
+		hex2bin(argv[1], len, &sdp_discover_uuid.u128.val[0],
+			sizeof(sdp_discover_uuid.u128.val));
+		sdp_discover.uuid = &sdp_discover_uuid.u128.uuid;
+	} else {
+		shell_error(sh, "Invalid UUID");
+		return -ENOEXEC;
+	}
+
+	sdp_discover.func = sdp_discover_func;
+	sdp_discover.pool = &sdp_client_pool;
+	sdp_discover.type = BT_SDP_DISCOVER_SERVICE_SEARCH;
+
+	err = bt_sdp_discover(default_conn, &sdp_discover);
+	if (err) {
+		shell_error(sh, "Fail to start SDP Discovery (err %d)", err);
+		return err;
+	}
+	return 0;
+}
+
+static int cmd_sa_discovery(const struct shell *sh, size_t argc, char *argv[])
+{
+	int err;
+	size_t len;
+	uint32_t handle;
+
+	len = strlen(argv[1]);
+
+	if (len == (sizeof(handle) * 2)) {
+		hex2bin(argv[1], len, (uint8_t *)&handle, sizeof(handle));
+		sdp_discover.handle = sys_be32_to_cpu(handle);
+	} else {
+		shell_error(sh, "Invalid UUID");
+		return -ENOEXEC;
+	}
+
+	sdp_discover.func = sdp_discover_func;
+	sdp_discover.pool = &sdp_client_pool;
+	sdp_discover.type = BT_SDP_DISCOVER_SERVICE_ATTR;
+
+	err = bt_sdp_discover(default_conn, &sdp_discover);
+	if (err) {
+		shell_error(sh, "Fail to start SDP Discovery (err %d)", err);
+		return err;
+	}
+	return 0;
+}
+
+SHELL_STATIC_SUBCMD_SET_CREATE(sdp_client_cmds,
+	SHELL_CMD_ARG(ss_discovery, NULL, "<UUID>", cmd_ss_discovery, 2, 0),
+	SHELL_CMD_ARG(sa_discovery, NULL, "<Service Record Handle>", cmd_sa_discovery, 2, 0),
+	SHELL_CMD_ARG(ssa_discovery, NULL, "<UUID>", cmd_ssa_discovery, 2, 0),
+	SHELL_SUBCMD_SET_END
+);
+
+static int cmd_default_handler(const struct shell *sh, size_t argc, char **argv)
+{
+	if (argc == 1) {
+		shell_help(sh);
+		return SHELL_CMD_HELP_PRINTED;
+	}
+
+	shell_error(sh, "%s unknown parameter: %s", argv[0], argv[1]);
+
+	return -EINVAL;
+}
+
+SHELL_CMD_REGISTER(sdp_client, &sdp_client_cmds, "Bluetooth classic SDP client shell commands",
+		   cmd_default_handler);
diff --git a/tests/bluetooth/classic/sdp_c/testcase.yaml b/tests/bluetooth/classic/sdp_c/testcase.yaml
new file mode 100644
index 00000000000..ad618436e23
--- /dev/null
+++ b/tests/bluetooth/classic/sdp_c/testcase.yaml
@@ -0,0 +1,24 @@
+tests:
+  bluetooth.classic.sdp.client:
+    platform_allow:
+      - native_sim
+    integration_platforms:
+      - native_sim
+    tags:
+      - bluetooth
+      - sdp
+    harness: pytest
+    harness_config:
+      pytest_dut_scope: session
+      fixture: usb_hci
+    timeout: 180
+  bluetooth.classic.sdp.client.no_blobs:
+    platform_allow:
+      - mimxrt1170_evk@B/mimxrt1176/cm7
+    tags:
+      - bluetooth
+      - sdp
+    extra_args:
+      - CONFIG_BUILD_ONLY_NO_BLOBS=y
+    timeout: 180
+    build_only: true
diff --git a/tests/bluetooth/classic/sdp_s/CMakeLists.txt b/tests/bluetooth/classic/sdp_s/CMakeLists.txt
new file mode 100644
index 00000000000..89de0b86386
--- /dev/null
+++ b/tests/bluetooth/classic/sdp_s/CMakeLists.txt
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+set(NO_QEMU_SERIAL_BT_SERVER 1)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(bluetooth)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/bluetooth/classic/sdp_s/README.rst b/tests/bluetooth/classic/sdp_s/README.rst
new file mode 100644
index 00000000000..946e6e43c44
--- /dev/null
+++ b/tests/bluetooth/classic/sdp_s/README.rst
@@ -0,0 +1,74 @@
+.. _bluetooth_classic_sdp_server_tests:
+
+Bluetooth Classic SDP Server Tests
+##################################
+
+Overview
+********
+
+This test suite uses ``bumble`` for testing Bluetooth Classic communication between a host
+PC (running :ref:`Twister <twister_script>`) and a device under test (DUT) running Zephyr.
+
+Prerequisites
+*************
+
+The test suite has the following prerequisites:
+
+* The ``bumble`` library installed on the host PC.
+The Bluetooth Classic controller on PC side is required. Refer to getting started of `bumble`_
+for details.
+
+The HCI transport for ``bumble`` can be configured as follows:
+
+* A specific configuration context can be provided along with the ``usb_hci`` fixture separated by
+  a ``:`` (i.e. specify fixture ``usb_hci:usb:0`` to use the ``usb:0`` as hci transport for
+  ``bumble``).
+* The configuration context can be overridden using the `hci transport`_ can be provided using the
+  ``--hci-transport`` test suite argument (i.e. run ``twister`` with the
+  ``--pytest-args=--hci-transport=usb:0`` argument to use the ``usb:0`` as hci transport for
+  ``bumble``).
+
+Building and Running
+********************
+
+Running on mimxrt1170_evk@B/mimxrt1176/cm7
+==========================================
+
+Running the test suite on :ref:`mimxrt1170_evk` relies on configuration of ``bumble``.
+
+On the host PC, a HCI transport needs to be required. Refer to `bumble platforms`_ page of
+``bumble`` for details.
+
+For example, on windows, a PTS dongle is used. After `WinUSB driver`_ has been installed,
+the HCI transport would be USB transport interface ``usb:<index>``.
+
+If the HCI transport is ``usb:0`` and debug console port is ``COM4``, the test suite can be
+launched using Twister:
+
+.. code-block:: shell
+
+   west twister -v -p mimxrt1170_evk@B/mimxrt1176/cm7 --device-testing --device-serial COM4 -T tests/bluetooth/classic/sdp_s -O sdp_s --force-platform --west-flash --west-runner=jlink -X usb_hci:usb:0
+
+Running on Hardware
+===================
+
+Running the test suite on hardware requires a HCI transport connected to the host PC.
+
+The test suite can be launched using Twister. Below is an example for running on the
+:zephyr:board:`mimxrt1170_evk@B/mimxrt1176/cm7`:
+
+.. code-block:: shell
+
+   west twister -v -p mimxrt1170_evk@B/mimxrt1176/cm7 --device-testing --device-serial COM4 -T tests/bluetooth/classic/sdp_s -O sdp_s --force-platform --west-flash --west-runner=jlink -X usb_hci:usb:0
+
+.. _bumble:
+   https://google.github.io/bumble/getting_started.html
+
+.. _hci transport:
+   https://google.github.io/bumble/transports/index.html
+
+.. _bumble platforms:
+   https://google.github.io/bumble/platforms/index.html
+
+.. _WinUSB driver:
+   https://google.github.io/bumble/platforms/windows.html
diff --git a/tests/bluetooth/classic/sdp_s/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/tests/bluetooth/classic/sdp_s/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf
new file mode 100644
index 00000000000..289b5a59738
--- /dev/null
+++ b/tests/bluetooth/classic/sdp_s/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf
@@ -0,0 +1,10 @@
+#select NXP NW612 Chipset
+CONFIG_BT_NXP_NW612=y
+
+CONFIG_BT_SETTINGS=n
+CONFIG_FLASH=n
+CONFIG_FLASH_MAP=n
+CONFIG_NVS=n
+CONFIG_SETTINGS=n
+
+CONFIG_ENTROPY_GENERATOR=y
diff --git a/tests/bluetooth/classic/sdp_s/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/tests/bluetooth/classic/sdp_s/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
new file mode 100644
index 00000000000..96ef63ad60b
--- /dev/null
+++ b/tests/bluetooth/classic/sdp_s/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,sram = &dtcm;
+	};
+};
diff --git a/tests/bluetooth/classic/sdp_s/prj.conf b/tests/bluetooth/classic/sdp_s/prj.conf
new file mode 100644
index 00000000000..ac6e0e30df1
--- /dev/null
+++ b/tests/bluetooth/classic/sdp_s/prj.conf
@@ -0,0 +1,9 @@
+CONFIG_BT=y
+CONFIG_BT_CLASSIC=y
+CONFIG_BT_SHELL=y
+CONFIG_LOG=y
+CONFIG_ZTEST=y
+
+CONFIG_BT_RFCOMM=y
+
+CONFIG_BT_DEVICE_NAME="sdp_server"
diff --git a/tests/bluetooth/classic/sdp_s/pytest/conftest.py b/tests/bluetooth/classic/sdp_s/pytest/conftest.py
new file mode 100644
index 00000000000..6b15e12ed34
--- /dev/null
+++ b/tests/bluetooth/classic/sdp_s/pytest/conftest.py
@@ -0,0 +1,57 @@
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+import logging
+import re
+
+import pytest
+from twister_harness import DeviceAdapter, Shell
+
+logger = logging.getLogger(__name__)
+
+
+def pytest_addoption(parser) -> None:
+    """Add local parser options to pytest."""
+    parser.addoption('--hci-transport', default=None, help='Configuration HCI transport for bumble')
+
+
+@pytest.fixture(name='initialize', scope='session')
+def fixture_initialize(request, shell: Shell, dut: DeviceAdapter):
+    """Session initializtion"""
+    # Get HCI transport for bumble
+    hci = request.config.getoption('--hci-transport')
+
+    if hci is None:
+        for fixture in dut.device_config.fixtures:
+            if fixture.startswith('usb_hci:'):
+                hci = fixture.split(sep=':', maxsplit=1)[1]
+                break
+
+    assert hci is not None
+
+    lines = shell.exec_command("bt init")
+    lines = dut.readlines_until("Bluetooth initialized")
+    regex = r'Identity: *(?P<bd_addr>(.*?):(.*?):(.*?):(.*?):(.*?):(.*?)*\((.*?)\))'
+    bd_addr = None
+    for line in lines:
+        logger.info(f"Shell log {line}")
+        m = re.search(regex, line)
+        if m:
+            bd_addr = m.group('bd_addr')
+
+    if bd_addr is None:
+        logger.error('Fail to get IUT BD address')
+        raise AssertionError
+
+    lines = shell.exec_command("br pscan on")
+    lines = shell.exec_command("br iscan on")
+    logger.info('initialized')
+    return hci, bd_addr
+
+
+@pytest.fixture
+def sdp_server_dut(initialize):
+    logger.info('Start running testcase')
+    yield initialize
+    logger.info('Done')
diff --git a/tests/bluetooth/classic/sdp_s/pytest/test_sdp.py b/tests/bluetooth/classic/sdp_s/pytest/test_sdp.py
new file mode 100644
index 00000000000..92ed24eaef6
--- /dev/null
+++ b/tests/bluetooth/classic/sdp_s/pytest/test_sdp.py
@@ -0,0 +1,289 @@
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+
+import asyncio
+import logging
+
+from bumble.core import (
+    BT_BR_EDR_TRANSPORT,
+    BT_L2CAP_PROTOCOL_ID,
+    BT_OBEX_PROTOCOL_ID,
+    CommandTimeoutError,
+    DeviceClass,
+)
+from bumble.device import Device
+from bumble.hci import Address
+from bumble.sdp import SDP_ALL_ATTRIBUTES_RANGE, SDP_PUBLIC_BROWSE_ROOT
+from bumble.sdp import Client as SDP_Client
+from bumble.transport import open_transport_or_link
+from twister_harness import DeviceAdapter, Shell
+
+logger = logging.getLogger(__name__)
+
+
+async def device_power_on(device) -> None:
+    while True:
+        try:
+            await device.power_on()
+            break
+        except Exception:
+            continue
+
+
+class discovery_listener(Device.Listener):
+    def __init__(self, address: str, event, **kwargs):
+        self._address = address
+        self._event = event
+        super().__init__(**kwargs)
+
+    def on_inquiry_result(self, address, class_of_device, data, rssi):
+        (
+            service_classes,
+            major_device_class,
+            minor_device_class,
+        ) = DeviceClass.split_class_of_device(class_of_device)
+        if self._address:
+            _address = self._address.split(" ")
+            if _address[0] in str(address):
+                logger.info('Target device is found')
+                self._event.set()
+        separator = '\n  '
+        logger.info(f'>>> {address}:')
+        logger.info(f'  Device Class (raw): {class_of_device:06X}')
+        major_class_name = DeviceClass.major_device_class_name(major_device_class)
+        logger.info('  Device Major Class: ' f'{major_class_name}')
+        minor_class_name = DeviceClass.minor_device_class_name(
+            major_device_class, minor_device_class
+        )
+        logger.info('  Device Minor Class: ' f'{minor_class_name}')
+        logger.info(
+            '  Device Services: ' f'{", ".join(DeviceClass.service_class_labels(service_classes))}'
+        )
+        logger.info(f'  RSSI: {rssi}')
+        if data.ad_structures:
+            logger.info(f'  {data.to_string(separator)}')
+
+
+async def start_discovery(hci_port, address) -> None:
+    logger.info('<<< Start discovery...')
+    async with await open_transport_or_link(hci_port) as hci_transport:
+        event = asyncio.Event()
+        device = Device.with_hci(
+            'Bumble',
+            Address('F0:F1:F2:F3:F4:F5'),
+            hci_transport.source,
+            hci_transport.sink,
+        )
+        device.listener = discovery_listener(address, event)
+        await device_power_on(device)
+
+        logger.info('Starting discovery')
+        await device.start_discovery()
+        await event.wait()
+
+
+async def br_connect(hci_port, shell, address) -> None:
+    logger.info('<<< connect...')
+    async with await open_transport_or_link(hci_port) as hci_transport:
+        device = Device.with_hci(
+            'Bumble',
+            Address('F0:F1:F2:F3:F4:F5'),
+            hci_transport.source,
+            hci_transport.sink,
+        )
+        device.classic_enabled = True
+        device.le_enabled = False
+        await device_power_on(device)
+
+        target_address = address.split(" ")[0]
+        logger.info(f'=== Connecting to {target_address}...')
+        try:
+            connection = await device.connect(target_address, transport=BT_BR_EDR_TRANSPORT)
+            logger.info(f'=== Connected to {connection.peer_address}!')
+        except CommandTimeoutError as e:
+            logger.info('!!! Connection timed out')
+            raise e
+
+        # Connect to the SDP Server
+        sdp_client = SDP_Client(connection)
+        await sdp_client.connect()
+
+        # List all services in the root browse group
+        logger.info("<<< 1 List all services in the root browse group")
+        service_record_handles = await sdp_client.search_services([SDP_PUBLIC_BROWSE_ROOT])
+        logger.info(f'SERVICES: {service_record_handles}')
+
+        # For each service in the root browse group, get all its attributes
+        assert len(service_record_handles) == 0
+        for service_record_handle in service_record_handles:
+            attributes = await sdp_client.get_attributes(
+                service_record_handle, [SDP_ALL_ATTRIBUTES_RANGE]
+            )
+            logger.info(f'SERVICE {service_record_handle:04X} attributes:')
+            for attribute in attributes:
+                logger.info(f'  {attribute}')
+
+        # Install SDP Record 0
+        shell.exec_command("sdp_server register_sdp 0")
+
+        # List all services in the root browse group
+        logger.info("<<< 2 List all services in the root browse group")
+        service_record_handles = await sdp_client.search_services([SDP_PUBLIC_BROWSE_ROOT])
+        logger.info(f'SERVICES: {service_record_handles}')
+
+        # For each service in the root browse group, get all its attributes
+        assert len(service_record_handles) != 0
+        for service_record_handle in service_record_handles:
+            attributes = await sdp_client.get_attributes(
+                service_record_handle, [SDP_ALL_ATTRIBUTES_RANGE]
+            )
+            logger.info(f'SERVICE {service_record_handle:04X} attributes:')
+            for attribute in attributes:
+                logger.info(f'  {attribute}')
+
+        logger.info("<<< 3 List all attributes with L2CAP protocol")
+        search_result = await sdp_client.search_attributes(
+            [BT_L2CAP_PROTOCOL_ID], [SDP_ALL_ATTRIBUTES_RANGE]
+        )
+        assert len(search_result) != 0
+        logger.info('SEARCH RESULTS:')
+        for attribute_list in search_result:
+            logger.info('SERVICE:')
+            logger.info('  ' + '\n  '.join([attribute.to_string() for attribute in attribute_list]))
+
+        logger.info("<<< 4 List all attributes with OBEX protocol")
+        search_result = await sdp_client.search_attributes(
+            [BT_OBEX_PROTOCOL_ID], [SDP_ALL_ATTRIBUTES_RANGE]
+        )
+        logger.info(f'SEARCH RESULTS:{search_result}')
+        assert len(search_result) == 0
+
+        logger.info("<<< 5 List all attributes with L2CAP protocol (0x1000~0xFFFF)")
+        search_result = await sdp_client.search_attributes(
+            [BT_L2CAP_PROTOCOL_ID], [(0x1000, 0xFFFF)]
+        )
+        logger.info(f'SEARCH RESULTS:{search_result}')
+        assert len(search_result) == 0
+
+        # Install SDP Record 1
+        shell.exec_command("sdp_server register_sdp 1")
+
+        # List all services with L2CAP
+        logger.info("<<< 6 List all services with L2CAP protocol")
+        service_record_handles = await sdp_client.search_services([BT_L2CAP_PROTOCOL_ID])
+        logger.info(f'SERVICES: {service_record_handles}')
+
+        assert len(service_record_handles) != 0
+        # For each service in the root browse group, get all its attributes
+        for service_record_handle in service_record_handles:
+            attributes = await sdp_client.get_attributes(
+                service_record_handle, [SDP_ALL_ATTRIBUTES_RANGE]
+            )
+            logger.info(f'SERVICE {service_record_handle:04X} attributes:')
+            for attribute in attributes:
+                logger.info(f'  {attribute}')
+
+        # Install SDP Record 2
+        shell.exec_command("sdp_server register_sdp 2")
+
+        # List all services with L2CAP
+        logger.info("<<< 7 List all services with L2CAP protocol")
+        service_record_handles = await sdp_client.search_services([BT_L2CAP_PROTOCOL_ID])
+        logger.info(f'SERVICES: {service_record_handles}')
+
+        assert len(service_record_handles) != 0
+        # For each service in the root browse group, get all its attributes
+        for service_record_handle in service_record_handles:
+            attributes = await sdp_client.get_attributes(
+                service_record_handle, [SDP_ALL_ATTRIBUTES_RANGE]
+            )
+            logger.info(f'SERVICE {service_record_handle:04X} attributes:')
+            for attribute in attributes:
+                logger.info(f'  {attribute}')
+
+        # Install SDP Record all
+        shell.exec_command("sdp_server register_sdp_all")
+
+        # List all services with L2CAP
+        logger.info("<<< 8 List all services with L2CAP protocol")
+        service_record_handles = await sdp_client.search_services([BT_L2CAP_PROTOCOL_ID])
+        logger.info(f'SERVICES: {service_record_handles}')
+
+        assert len(service_record_handles) != 0
+        # For each service in the root browse group, get all its attributes
+        for service_record_handle in service_record_handles:
+            attributes = await sdp_client.get_attributes(
+                service_record_handle, [SDP_ALL_ATTRIBUTES_RANGE]
+            )
+            logger.info(f'SERVICE {service_record_handle:04X} attributes:')
+            for attribute in attributes:
+                logger.info(f'  {attribute}')
+
+        logger.info("<<< 9 List all attributes with L2CAP protocol")
+        search_result = await sdp_client.search_attributes(
+            [BT_L2CAP_PROTOCOL_ID], [SDP_ALL_ATTRIBUTES_RANGE]
+        )
+        assert len(search_result) != 0
+        logger.info('SEARCH RESULTS:')
+        for attribute_list in search_result:
+            logger.info('SERVICE:')
+            logger.info('  ' + '\n  '.join([attribute.to_string() for attribute in attribute_list]))
+
+        # Install SDP large Record
+        shell.exec_command("sdp_server register_sdp_large")
+
+        logger.info("<<< 10 List all services with L2CAP protocol")
+        service_record_handles = await sdp_client.search_services([BT_L2CAP_PROTOCOL_ID])
+        logger.info(f'SERVICES: {service_record_handles}')
+
+        assert len(service_record_handles) != 0
+        # For each service in the root browse group, get all its attributes
+        for service_record_handle in service_record_handles:
+            attributes = await sdp_client.get_attributes(
+                service_record_handle, [SDP_ALL_ATTRIBUTES_RANGE]
+            )
+            logger.info(f'SERVICE {service_record_handle:04X} attributes:')
+            service_name_found = False
+            for attribute in attributes:
+                logger.info(f'  {attribute}')
+                if attribute.id == 0x100:
+                    service_name_found = True
+            if service_record_handle == service_record_handles[-1]:
+                assert service_name_found is False
+
+        # Install SDP large Record
+        shell.exec_command("sdp_server register_sdp_large_valid")
+
+        logger.info("<<< 11 List all services with L2CAP protocol with valid service name")
+        service_record_handles = await sdp_client.search_services([BT_L2CAP_PROTOCOL_ID])
+        logger.info(f'SERVICES: {service_record_handles}')
+
+        assert len(service_record_handles) != 0
+        # For each service in the root browse group, get all its attributes
+        for service_record_handle in service_record_handles:
+            attributes = await sdp_client.get_attributes(
+                service_record_handle, [SDP_ALL_ATTRIBUTES_RANGE]
+            )
+            logger.info(f'SERVICE {service_record_handle:04X} attributes:')
+            service_name_found = False
+            for attribute in attributes:
+                logger.info(f'  {attribute}')
+                if attribute.id == 0x100:
+                    service_name_found = True
+            if service_record_handle == service_record_handles[-1]:
+                assert service_name_found is True
+
+
+class TestSdpServer:
+    def test_discovery_device(self, sdp_server_dut):
+        """Test case to discover IUT"""
+        logger.info(f'test_discovery_device {sdp_server_dut}')
+        hci, iut_address = sdp_server_dut
+        asyncio.run(start_discovery(hci, iut_address))
+
+    def test_sdp_discover(self, shell: Shell, dut: DeviceAdapter, sdp_server_dut):
+        """Test case to request SDP records"""
+        logger.info(f'test_sdp_discover {sdp_server_dut}')
+        hci, iut_address = sdp_server_dut
+        asyncio.run(br_connect(hci, shell, iut_address))
diff --git a/tests/bluetooth/classic/sdp_s/src/sdp_server.c b/tests/bluetooth/classic/sdp_s/src/sdp_server.c
new file mode 100644
index 00000000000..557ae207e18
--- /dev/null
+++ b/tests/bluetooth/classic/sdp_s/src/sdp_server.c
@@ -0,0 +1,320 @@
+/* sdp_server.c - Bluetooth classic SDP server smoke test */
+
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdlib.h>
+
+#include <errno.h>
+#include <zephyr/types.h>
+#include <zephyr/kernel.h>
+
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/classic/rfcomm.h>
+#include <zephyr/bluetooth/classic/sdp.h>
+
+#include <zephyr/shell/shell.h>
+
+static struct bt_sdp_attribute spp_attrs_large[] = {
+	BT_SDP_NEW_SERVICE,
+	BT_SDP_LIST(
+		BT_SDP_ATTR_SVCLASS_ID_LIST,
+		BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 3),
+		BT_SDP_DATA_ELEM_LIST(
+		{
+			BT_SDP_TYPE_SIZE(BT_SDP_UUID16),
+			BT_SDP_ARRAY_16(BT_SDP_SERIAL_PORT_SVCLASS)
+		},
+		)
+	),
+	BT_SDP_LIST(
+		BT_SDP_ATTR_PROTO_DESC_LIST,
+		BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 12),
+		BT_SDP_DATA_ELEM_LIST(
+		{
+			BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 3),
+			BT_SDP_DATA_ELEM_LIST(
+			{
+				BT_SDP_TYPE_SIZE(BT_SDP_UUID16),
+				BT_SDP_ARRAY_16(BT_SDP_PROTO_L2CAP)
+			},
+			)
+		},
+		{
+			BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 5),
+			BT_SDP_DATA_ELEM_LIST(
+			{
+				BT_SDP_TYPE_SIZE(BT_SDP_UUID16),
+				BT_SDP_ARRAY_16(BT_SDP_PROTO_RFCOMM)
+			},
+			{
+				BT_SDP_TYPE_SIZE(BT_SDP_UINT8),
+				BT_SDP_ARRAY_8(BT_RFCOMM_CHAN_SPP)
+			},
+			)
+		},
+		)
+	),
+	BT_SDP_LIST(
+		BT_SDP_ATTR_PROFILE_DESC_LIST,
+		BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 8),
+		BT_SDP_DATA_ELEM_LIST(
+		{
+			BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 6),
+			BT_SDP_DATA_ELEM_LIST(
+			{
+				BT_SDP_TYPE_SIZE(BT_SDP_UUID16),
+				BT_SDP_ARRAY_16(BT_SDP_SERIAL_PORT_SVCLASS)
+			},
+			{
+				BT_SDP_TYPE_SIZE(BT_SDP_UINT16),
+				BT_SDP_ARRAY_16(0x0102)
+			},
+			)
+		},
+		)
+	),
+	BT_SDP_SERVICE_NAME("==================================================="
+			    "==================================================="
+			    "large_sdp_record"
+			    "==================================================="
+			    "==================================================="),
+};
+
+static struct bt_sdp_record spp_rec_large = BT_SDP_RECORD(spp_attrs_large);
+
+static struct bt_sdp_attribute spp_attrs_large_valid[] = {
+	BT_SDP_NEW_SERVICE,
+	BT_SDP_LIST(
+		BT_SDP_ATTR_SVCLASS_ID_LIST,
+		BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 3),
+		BT_SDP_DATA_ELEM_LIST(
+		{
+			BT_SDP_TYPE_SIZE(BT_SDP_UUID16),
+			BT_SDP_ARRAY_16(BT_SDP_SERIAL_PORT_SVCLASS)
+		},
+		)
+	),
+	BT_SDP_LIST(
+		BT_SDP_ATTR_PROTO_DESC_LIST,
+		BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 12),
+		BT_SDP_DATA_ELEM_LIST(
+		{
+			BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 3),
+			BT_SDP_DATA_ELEM_LIST(
+			{
+				BT_SDP_TYPE_SIZE(BT_SDP_UUID16),
+				BT_SDP_ARRAY_16(BT_SDP_PROTO_L2CAP)
+			},
+			)
+		},
+		{
+			BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 5),
+			BT_SDP_DATA_ELEM_LIST(
+			{
+				BT_SDP_TYPE_SIZE(BT_SDP_UUID16),
+				BT_SDP_ARRAY_16(BT_SDP_PROTO_RFCOMM)
+			},
+			{
+				BT_SDP_TYPE_SIZE(BT_SDP_UINT8),
+				BT_SDP_ARRAY_8(BT_RFCOMM_CHAN_SPP)
+			},
+			)
+		},
+		)
+	),
+	BT_SDP_LIST(
+		BT_SDP_ATTR_PROFILE_DESC_LIST,
+		BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 8),
+		BT_SDP_DATA_ELEM_LIST(
+		{
+			BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 6),
+			BT_SDP_DATA_ELEM_LIST(
+			{
+				BT_SDP_TYPE_SIZE(BT_SDP_UUID16),
+				BT_SDP_ARRAY_16(BT_SDP_SERIAL_PORT_SVCLASS)
+			},
+			{
+				BT_SDP_TYPE_SIZE(BT_SDP_UINT16),
+				BT_SDP_ARRAY_16(0x0102)
+			},
+			)
+		},
+		)
+	),
+	BT_SDP_SERVICE_NAME("====================================="
+			    "====================================="
+			    "large_sdp_record"
+			    "====================================="
+			    "====================================="),
+};
+
+static struct bt_sdp_record spp_rec_large_valid = BT_SDP_RECORD(spp_attrs_large_valid);
+
+#define MAX_SDP_RECORD_COUNT 8
+
+#define _SDP_ATTRS_DEFINE(index, sdp_attrs_name) \
+static struct bt_sdp_attribute sdp_attrs_name##index[] = { \
+	BT_SDP_NEW_SERVICE, \
+	BT_SDP_LIST( \
+		BT_SDP_ATTR_SVCLASS_ID_LIST, \
+		BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 3), \
+		BT_SDP_DATA_ELEM_LIST( \
+		{ \
+			BT_SDP_TYPE_SIZE(BT_SDP_UUID16), \
+			BT_SDP_ARRAY_16(BT_SDP_SERIAL_PORT_SVCLASS) \
+		}, \
+		) \
+	), \
+	BT_SDP_LIST( \
+		BT_SDP_ATTR_PROTO_DESC_LIST, \
+		BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 12), \
+		BT_SDP_DATA_ELEM_LIST( \
+		{ \
+			BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 3), \
+			BT_SDP_DATA_ELEM_LIST( \
+			{ \
+				BT_SDP_TYPE_SIZE(BT_SDP_UUID16), \
+				BT_SDP_ARRAY_16(BT_SDP_PROTO_L2CAP) \
+			}, \
+			) \
+		}, \
+		{ \
+			BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 5), \
+			BT_SDP_DATA_ELEM_LIST( \
+			{ \
+				BT_SDP_TYPE_SIZE(BT_SDP_UUID16), \
+				BT_SDP_ARRAY_16(BT_SDP_PROTO_RFCOMM) \
+			}, \
+			{ \
+				BT_SDP_TYPE_SIZE(BT_SDP_UINT8), \
+				BT_SDP_ARRAY_8(BT_RFCOMM_CHAN_SPP + index + 1) \
+			}, \
+			) \
+		}, \
+		) \
+	), \
+	BT_SDP_LIST( \
+		BT_SDP_ATTR_PROFILE_DESC_LIST, \
+		BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 8), \
+		BT_SDP_DATA_ELEM_LIST( \
+		{ \
+			BT_SDP_TYPE_SIZE_VAR(BT_SDP_SEQ8, 6), \
+			BT_SDP_DATA_ELEM_LIST( \
+			{ \
+				BT_SDP_TYPE_SIZE(BT_SDP_UUID16), \
+				BT_SDP_ARRAY_16(BT_SDP_SERIAL_PORT_SVCLASS) \
+			}, \
+			{ \
+				BT_SDP_TYPE_SIZE(BT_SDP_UINT16), \
+				BT_SDP_ARRAY_16(0x0102) \
+			}, \
+			) \
+		}, \
+		) \
+	), \
+	BT_SDP_SERVICE_NAME("Serial Port"), \
+}
+
+#define SDP_ATTRS_DEFINE(index, ...) _SDP_ATTRS_DEFINE(index, ##__VA_ARGS__)
+
+LISTIFY(MAX_SDP_RECORD_COUNT, SDP_ATTRS_DEFINE, (;), spp_attrs);
+
+#define _SDP_REC_DEFINE(index, sdp_attrs_name) BT_SDP_RECORD(sdp_attrs_name##index)
+#define SDP_REC_DEFINE(index, ...)             _SDP_REC_DEFINE(index, ##__VA_ARGS__)
+
+static struct bt_sdp_record spp_rec[MAX_SDP_RECORD_COUNT] = {
+	LISTIFY(MAX_SDP_RECORD_COUNT, SDP_REC_DEFINE, (,), spp_attrs),
+};
+
+static bool sdp_rec_reg[MAX_SDP_RECORD_COUNT];
+
+static int cmd_register_sdp(const struct shell *sh, size_t argc, char *argv[])
+{
+	int err;
+	uint8_t index;
+
+	index = strtoul(argv[1], NULL, 16);
+	if (sdp_rec_reg[index]) {
+		shell_error(sh, "The SDP record %d has been installed", index);
+	}
+
+	err = bt_sdp_register_service(&spp_rec[index]);
+	if (err) {
+		shell_error(sh, "Register SDP record failed (err %d)", err);
+	} else {
+		sdp_rec_reg[index] = true;
+	}
+	return err;
+}
+
+static int cmd_register_sdp_all(const struct shell *sh, size_t argc, char *argv[])
+{
+	int err;
+
+	sh = sh;
+
+	for (size_t i = 0; i < ARRAY_SIZE(spp_rec); i++) {
+		if (!sdp_rec_reg[i]) {
+			err = bt_sdp_register_service(&spp_rec[i]);
+			if (err) {
+				shell_error(sh, "Register SDP record failed (err %d)", err);
+			} else {
+				sdp_rec_reg[i] = true;
+			}
+		}
+	}
+	return 0;
+}
+
+static int cmd_register_sdp_large(const struct shell *sh, size_t argc, char *argv[])
+{
+	int err;
+
+	sh = sh;
+
+	err = bt_sdp_register_service(&spp_rec_large);
+	if (err) {
+		shell_error(sh, "Register SDP large record failed (err %d)", err);
+	}
+	return 0;
+}
+
+static int cmd_register_sdp_large_valid(const struct shell *sh, size_t argc, char *argv[])
+{
+	int err;
+
+	sh = sh;
+
+	err = bt_sdp_register_service(&spp_rec_large_valid);
+	if (err) {
+		shell_error(sh, "Register SDP large record failed (err %d)", err);
+	}
+	return 0;
+}
+
+SHELL_STATIC_SUBCMD_SET_CREATE(sdp_server_cmds,
+	SHELL_CMD_ARG(register_sdp, NULL, "<SDP Record Index>", cmd_register_sdp, 2, 0),
+	SHELL_CMD_ARG(register_sdp_all, NULL, "", cmd_register_sdp_all, 1, 0),
+	SHELL_CMD_ARG(register_sdp_large, NULL, "", cmd_register_sdp_large, 1, 0),
+	SHELL_CMD_ARG(register_sdp_large_valid, NULL, "", cmd_register_sdp_large_valid, 1, 0),
+	SHELL_SUBCMD_SET_END
+);
+
+static int cmd_default_handler(const struct shell *sh, size_t argc, char **argv)
+{
+	if (argc == 1) {
+		shell_help(sh);
+		return SHELL_CMD_HELP_PRINTED;
+	}
+
+	shell_error(sh, "%s unknown parameter: %s", argv[0], argv[1]);
+
+	return -EINVAL;
+}
+
+SHELL_CMD_REGISTER(sdp_server, &sdp_server_cmds, "Bluetooth classic SDP server shell commands",
+		   cmd_default_handler);
diff --git a/tests/bluetooth/classic/sdp_s/testcase.yaml b/tests/bluetooth/classic/sdp_s/testcase.yaml
new file mode 100644
index 00000000000..3b54405040b
--- /dev/null
+++ b/tests/bluetooth/classic/sdp_s/testcase.yaml
@@ -0,0 +1,24 @@
+tests:
+  bluetooth.classic.sdp.server:
+    platform_allow:
+      - native_sim
+    integration_platforms:
+      - native_sim
+    tags:
+      - bluetooth
+      - sdp
+    harness: pytest
+    harness_config:
+      pytest_dut_scope: session
+      fixture: usb_hci
+    timeout: 60
+  bluetooth.classic.sdp.server.no_blobs:
+    platform_allow:
+      - mimxrt1170_evk@B/mimxrt1176/cm7
+    tags:
+      - bluetooth
+      - sdp
+    extra_args:
+      - CONFIG_BUILD_ONLY_NO_BLOBS=y
+    timeout: 60
+    build_only: true
diff --git a/tests/bluetooth/common/testlib/include/testlib/addr.h b/tests/bluetooth/common/testlib/include/testlib/addr.h
index 90802e50fb5..94f14c6a8e5 100644
--- a/tests/bluetooth/common/testlib/include/testlib/addr.h
+++ b/tests/bluetooth/common/testlib/include/testlib/addr.h
@@ -6,7 +6,6 @@
 #define ZEPHYR_TESTS_BLUETOOTH_COMMON_TESTLIB_INCLUDE_TESTLIB_ADDR_H_
 
 #include <stdint.h>
-
 #include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/byteorder.h>
 
diff --git a/tests/bluetooth/common/testlib/include/testlib/att_read.h b/tests/bluetooth/common/testlib/include/testlib/att_read.h
index 4e9034d9876..a970ff6d0b8 100644
--- a/tests/bluetooth/common/testlib/include/testlib/att_read.h
+++ b/tests/bluetooth/common/testlib/include/testlib/att_read.h
@@ -6,7 +6,11 @@
 #define ZEPHYR_TESTS_BLUETOOTH_COMMON_TESTLIB_INCLUDE_TESTLIB_ATT_READ_H_
 
 #include <stdint.h>
+#include <zephyr/bluetooth/att.h>
+#include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/gatt.h>
+#include <zephyr/bluetooth/uuid.h>
+#include <zephyr/net_buf.h>
 
 /** Perform a single ATT_READ_BY_TYPE_REQ. */
 int bt_testlib_att_read_by_type_sync(struct net_buf_simple *result_data, uint16_t *result_size,
diff --git a/tests/bluetooth/common/testlib/include/testlib/att_write.h b/tests/bluetooth/common/testlib/include/testlib/att_write.h
index 0cfd03e88b6..0bf0185c88c 100644
--- a/tests/bluetooth/common/testlib/include/testlib/att_write.h
+++ b/tests/bluetooth/common/testlib/include/testlib/att_write.h
@@ -6,6 +6,8 @@
 #define ZEPHYR_TESTS_BLUETOOTH_COMMON_TESTLIB_INCLUDE_TESTLIB_ATT_WRITE_H_
 
 #include <stdint.h>
+#include <zephyr/bluetooth/att.h>
+#include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/gatt.h>
 
 int bt_testlib_att_write(struct bt_conn *conn, enum bt_att_chan_opt bearer, uint16_t handle,
diff --git a/tests/bluetooth/common/testlib/include/testlib/conn.h b/tests/bluetooth/common/testlib/include/testlib/conn.h
index e3ca711532f..686b32bfbf8 100644
--- a/tests/bluetooth/common/testlib/include/testlib/conn.h
+++ b/tests/bluetooth/common/testlib/include/testlib/conn.h
@@ -5,6 +5,8 @@
 #ifndef ZEPHYR_TESTS_BLUETOOTH_COMMON_TESTLIB_INCLUDE_TESTLIB_CONN_H_
 #define ZEPHYR_TESTS_BLUETOOTH_COMMON_TESTLIB_INCLUDE_TESTLIB_CONN_H_
 
+#include <stdint.h>
+#include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/conn.h>
 
 /**
diff --git a/tests/bluetooth/common/testlib/include/testlib/log_utils.h b/tests/bluetooth/common/testlib/include/testlib/log_utils.h
index 66cd2c0a2f7..18296b028ec 100644
--- a/tests/bluetooth/common/testlib/include/testlib/log_utils.h
+++ b/tests/bluetooth/common/testlib/include/testlib/log_utils.h
@@ -5,8 +5,13 @@
 #ifndef ZEPHYR_TESTS_BLUETOOTH_COMMON_TESTLIB_INCLUDE_TESTLIB_LOG_UTILS_H_
 #define ZEPHYR_TESTS_BLUETOOTH_COMMON_TESTLIB_INCLUDE_TESTLIB_LOG_UTILS_H_
 
+#include <stddef.h>
+#include <stdint.h>
+#include <zephyr/autoconf.h>
+#include <zephyr/logging/log_core.h>
 #include <zephyr/logging/log_ctrl.h>
 #include <zephyr/sys/__assert.h>
+#include <zephyr/sys/util_macro.h>
 
 static inline void bt_testlib_log_level_set(char *module, uint32_t new_level)
 {
diff --git a/tests/bluetooth/common/testlib/src/adv.c b/tests/bluetooth/common/testlib/src/adv.c
index d02d5990846..7713b97b1a8 100644
--- a/tests/bluetooth/common/testlib/src/adv.c
+++ b/tests/bluetooth/common/testlib/src/adv.c
@@ -2,15 +2,16 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stddef.h>
 #include <stdint.h>
+#include <string.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
-#include <zephyr/bluetooth/gatt.h>
+#include <zephyr/bluetooth/gap.h>
 #include <zephyr/bluetooth/gatt.h>
 #include <zephyr/bluetooth/l2cap.h>
 #include <zephyr/bluetooth/uuid.h>
 #include <zephyr/kernel.h>
-#include <zephyr/kernel.h>
 #include <zephyr/sys/__assert.h>
 
 struct bt_testlib_adv_ctx {
diff --git a/tests/bluetooth/common/testlib/src/att.c b/tests/bluetooth/common/testlib/src/att.c
index 01c9a5b774c..341967aa17f 100644
--- a/tests/bluetooth/common/testlib/src/att.c
+++ b/tests/bluetooth/common/testlib/src/att.c
@@ -4,14 +4,17 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/kernel.h>
-
+#include <stddef.h>
+#include <stdint.h>
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/att.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gatt.h>
-#include <zephyr/bluetooth/att.h>
-
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log_core.h>
 #include <zephyr/logging/log.h>
+#include <zephyr/sys/__assert.h>
 
 LOG_MODULE_REGISTER(bt_testlib_att, LOG_LEVEL_DBG);
 
diff --git a/tests/bluetooth/common/testlib/src/att_read.c b/tests/bluetooth/common/testlib/src/att_read.c
index 8da82ce19b8..6be5a2161ca 100644
--- a/tests/bluetooth/common/testlib/src/att_read.c
+++ b/tests/bluetooth/common/testlib/src/att_read.c
@@ -3,17 +3,21 @@
  */
 
 #include <stdint.h>
+#include <testlib/att_read.h>
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/att.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gatt.h>
-#include <zephyr/bluetooth/att.h>
 #include <zephyr/bluetooth/l2cap.h>
 #include <zephyr/bluetooth/uuid.h>
 #include <zephyr/kernel.h>
-#include <zephyr/sys/__assert.h>
-
-#include <testlib/att_read.h>
+#include <zephyr/logging/log_core.h>
 #include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/sys/util.h>
 
 LOG_MODULE_REGISTER(bt_testlib_att_read, LOG_LEVEL_DBG);
 
diff --git a/tests/bluetooth/common/testlib/src/att_write.c b/tests/bluetooth/common/testlib/src/att_write.c
index 8da01ea233a..ca469b6b9fc 100644
--- a/tests/bluetooth/common/testlib/src/att_write.c
+++ b/tests/bluetooth/common/testlib/src/att_write.c
@@ -3,16 +3,18 @@
  */
 
 #include <stdint.h>
+#include <zephyr/bluetooth/att.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gatt.h>
-#include <zephyr/bluetooth/att.h>
 #include <zephyr/bluetooth/l2cap.h>
 #include <zephyr/bluetooth/uuid.h>
 #include <zephyr/kernel.h>
+#include <zephyr/logging/log_core.h>
+#include <zephyr/logging/log.h>
 #include <zephyr/sys/__assert.h>
+#include <zephyr/sys/util.h>
 
-#include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(bt_testlib_att_write, LOG_LEVEL_DBG);
 
 struct bt_testlib_att_write_closure {
diff --git a/tests/bluetooth/common/testlib/src/conn_ref.c b/tests/bluetooth/common/testlib/src/conn_ref.c
index eebea95547e..db6d13f2a84 100644
--- a/tests/bluetooth/common/testlib/src/conn_ref.c
+++ b/tests/bluetooth/common/testlib/src/conn_ref.c
@@ -3,12 +3,12 @@
  */
 
 #include <stddef.h>
-
+#include <stdint.h>
+#include <testlib/conn.h>
 #include <zephyr/bluetooth/conn.h>
+#include <zephyr/sys/__assert.h>
 #include <zephyr/sys/atomic_builtin.h>
 
-#include <testlib/conn.h>
-
 /**
  * @file
  * @brief Reified connection reference counting.
diff --git a/tests/bluetooth/common/testlib/src/conn_wait.c b/tests/bluetooth/common/testlib/src/conn_wait.c
index de1c72779c0..b9eab76ce06 100644
--- a/tests/bluetooth/common/testlib/src/conn_wait.c
+++ b/tests/bluetooth/common/testlib/src/conn_wait.c
@@ -2,21 +2,21 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stddef.h>
 #include <stdint.h>
+#include <testlib/conn.h>
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gatt.h>
-#include <zephyr/bluetooth/gatt.h>
 #include <zephyr/bluetooth/l2cap.h>
 #include <zephyr/bluetooth/uuid.h>
 #include <zephyr/kernel.h>
-#include <zephyr/kernel.h>
+#include <zephyr/logging/log_core.h>
+#include <zephyr/logging/log.h>
 #include <zephyr/sys/__assert.h>
 #include <zephyr/sys/util_macro.h>
 
-#include <testlib/conn.h>
-
-#include <zephyr/logging/log.h>
 LOG_MODULE_REGISTER(bt_testlib_conn_wait, LOG_LEVEL_DBG);
 
 static K_MUTEX_DEFINE(conn_wait_mutex);
diff --git a/tests/bluetooth/common/testlib/src/connect.c b/tests/bluetooth/common/testlib/src/connect.c
index 9e181a574e3..7e221654345 100644
--- a/tests/bluetooth/common/testlib/src/connect.c
+++ b/tests/bluetooth/common/testlib/src/connect.c
@@ -2,12 +2,19 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <errno.h>
+#include <stddef.h>
 #include <stdint.h>
+#include <testlib/conn.h>
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gatt.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/kernel.h>
+#include <zephyr/logging/log_core.h>
 #include <zephyr/logging/log.h>
-
-#include <testlib/conn.h>
+#include <zephyr/sys/__assert.h>
 
 LOG_MODULE_REGISTER(bt_testlib_connect, LOG_LEVEL_INF);
 
diff --git a/tests/bluetooth/common/testlib/src/disconnect.c b/tests/bluetooth/common/testlib/src/disconnect.c
index 877494c5a5e..896feb90b33 100644
--- a/tests/bluetooth/common/testlib/src/disconnect.c
+++ b/tests/bluetooth/common/testlib/src/disconnect.c
@@ -2,14 +2,15 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "zephyr/sys/__assert.h"
 #include <stdint.h>
+#include <testlib/conn.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gatt.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
-
-#include <testlib/conn.h>
-
+#include <zephyr/sys/__assert.h>
 
 int bt_testlib_disconnect(struct bt_conn **connp, uint8_t reason)
 {
diff --git a/tests/bluetooth/common/testlib/src/scan.c b/tests/bluetooth/common/testlib/src/scan.c
index a06ce5d3bf7..0dd3dcc161f 100644
--- a/tests/bluetooth/common/testlib/src/scan.c
+++ b/tests/bluetooth/common/testlib/src/scan.c
@@ -2,13 +2,20 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stddef.h>
 #include <stdint.h>
+#include <string.h>
+#include <testlib/scan.h>
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/gap.h>
 #include <zephyr/bluetooth/gatt.h>
 #include <zephyr/kernel.h>
-#include <zephyr/sys/__assert.h>
+#include <zephyr/logging/log_core.h>
 #include <zephyr/logging/log.h>
-
-#include <testlib/scan.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/util.h>
 
 LOG_MODULE_REGISTER(bt_testlib_scan, LOG_LEVEL_INF);
 
diff --git a/tests/bluetooth/common/testlib/src/security.c b/tests/bluetooth/common/testlib/src/security.c
index a229cf5487c..0d5fc02e156 100644
--- a/tests/bluetooth/common/testlib/src/security.c
+++ b/tests/bluetooth/common/testlib/src/security.c
@@ -2,6 +2,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stddef.h>
 #include <stdint.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
@@ -9,8 +10,9 @@
 #include <zephyr/bluetooth/l2cap.h>
 #include <zephyr/bluetooth/uuid.h>
 #include <zephyr/kernel.h>
-#include <zephyr/sys/__assert.h>
+#include <zephyr/logging/log_core.h>
 #include <zephyr/logging/log.h>
+#include <zephyr/sys/__assert.h>
 
 LOG_MODULE_REGISTER(bt_testlib_security, LOG_LEVEL_INF);
 
diff --git a/tests/bluetooth/controller/ctrl_cis_create/src/main.c b/tests/bluetooth/controller/ctrl_cis_create/src/main.c
index ba892586c60..4e9820fb46a 100644
--- a/tests/bluetooth/controller/ctrl_cis_create/src/main.c
+++ b/tests/bluetooth/controller/ctrl_cis_create/src/main.c
@@ -47,6 +47,10 @@ DEFINE_FFF_GLOBALS;
 #include "helper_pdu.h"
 #include "helper_util.h"
 
+#include <zephyr/bluetooth/iso.h>
+
+#define SUB_INTERVAL_MIN 400
+
 static struct ll_conn conn;
 
 static struct ll_conn_iso_group cig_mock = { 0 };
@@ -84,11 +88,11 @@ static struct pdu_data_llctrl_cis_req remote_cis_req = {
 	.p_ft             =   1,
 	.iso_interval     =   6,
 	.conn_event_count =   12,
-	.c_sdu_interval   =   { 0, 0, 0},
-	.p_sdu_interval   =   { 0, 0, 0},
-	.sub_interval     =   { 0, 0, 0},
-	.cis_offset_min   =   { 0, 0, 0},
-	.cis_offset_max   =   { 0, 0, 0}
+	.c_sdu_interval   =   { 0, 0x02, 0}, /* 512 us */
+	.p_sdu_interval   =   { 0, 0x02, 0}, /* 512 us */
+	.sub_interval     =   { 0x90, 0x01, 0x00}, /* 400 us */
+	.cis_offset_min   =   { 0, 0x02, 0}, /* 512 us */
+	.cis_offset_max   =   { 0, 0x02, 0}  /* 512 us */
 };
 
 static struct pdu_data_llctrl_cis_ind remote_cis_ind = {
@@ -127,7 +131,7 @@ static struct pdu_data_llctrl_cis_ind local_cis_ind = {
 	.cig_sync_delay = { 0, 0, 0},
 	.cis_offset = { 0, 0, 0},
 	.cis_sync_delay = { 0, 0, 0},
-	.conn_event_count = 13
+	.conn_event_count = 0
 };
 
 #define ERROR_CODE 0x17
@@ -169,8 +173,8 @@ ZTEST(cis_create, test_cc_create_periph_rem_host_accept)
 		.cis_id = 0x02
 	};
 	struct pdu_data_llctrl_cis_rsp local_cis_rsp = {
-		.cis_offset_max = { 0, 0, 0},
-		.cis_offset_min = { 0, 0, 0},
+		.cis_offset_max = { 0, 0x02, 0},
+		.cis_offset_min = { 0, 0x02, 0},
 		.conn_event_count = 12
 	};
 	struct node_rx_conn_iso_estab cis_estab = {
@@ -196,7 +200,7 @@ ZTEST(cis_create, test_cc_create_periph_rem_host_accept)
 	/* Done */
 	event_done(&conn);
 
-	/* There should be excactly one host notification */
+	/* There should be exactly one host notification */
 	ut_rx_node(NODE_CIS_REQUEST, &ntf, &cis_req);
 	ut_rx_q_is_empty();
 
@@ -264,7 +268,7 @@ ZTEST(cis_create, test_cc_create_periph_rem_host_accept)
 	/* Prepare */
 	event_prepare(&conn);
 
-	/* There should be excactly one host notification */
+	/* There should be exactly one host notification */
 	ut_rx_node(NODE_CIS_ESTABLISHED, &ntf, &cis_estab);
 	ut_rx_q_is_empty();
 
@@ -328,7 +332,7 @@ ZTEST(cis_create, test_cc_create_periph_rem_host_reject)
 	/* Done */
 	event_done(&conn);
 
-	/* There should be excactly one host notification */
+	/* There should be exactly one host notification */
 	ut_rx_node(NODE_CIS_REQUEST, &ntf, &cis_req);
 	ut_rx_q_is_empty();
 
@@ -409,7 +413,7 @@ ZTEST(cis_create, test_cc_create_periph_rem_host_accept_to)
 	/* Done */
 	event_done(&conn);
 
-	/* There should be excactly one host notification */
+	/* There should be exactly one host notification */
 	ut_rx_node(NODE_CIS_REQUEST, &ntf, &cis_req);
 	ut_rx_q_is_empty();
 
@@ -435,7 +439,7 @@ ZTEST(cis_create, test_cc_create_periph_rem_host_accept_to)
 	/* Done */
 	event_done(&conn);
 
-	/* There should be excactly one host notification */
+	/* There should be exactly one host notification */
 	ut_rx_node(NODE_CIS_ESTABLISHED, &ntf, &cis_estab);
 	ut_rx_q_is_empty();
 
@@ -525,6 +529,196 @@ ZTEST(cis_create, test_cc_create_periph_rem_invalid_phy)
 		      "Free CTX buffers %d", llcp_ctx_buffers_free());
 }
 
+static void rx_remote_cis_req_invalid_param(struct pdu_data_llctrl_cis_req *req)
+{
+	struct node_tx *tx;
+	struct pdu_data_llctrl_reject_ext_ind local_reject = {
+		.error_code = BT_HCI_ERR_INVALID_LL_PARAM,
+		.reject_opcode = PDU_DATA_LLCTRL_TYPE_CIS_REQ
+	};
+
+	test_setup(&conn);
+
+	/* Role */
+	test_set_role(&conn, BT_HCI_ROLE_PERIPHERAL);
+
+	/* Connect */
+	ull_cp_state_set(&conn, ULL_CP_CONNECTED);
+
+	/* Prepare */
+	event_prepare(&conn);
+
+	/* Rx */
+	lt_tx(LL_CIS_REQ, &conn, req);
+
+	/* Done */
+	event_done(&conn);
+
+	/* Prepare */
+	event_prepare(&conn);
+
+	/* Tx Queue should have one LL Control PDU */
+	lt_rx(LL_REJECT_EXT_IND, &conn, &tx, &local_reject);
+	lt_rx_q_is_empty(&conn);
+
+	/* Done */
+	event_done(&conn);
+
+	zassert_equal(llcp_ctx_buffers_free(), test_ctx_buffers_cnt(),
+		      "Free CTX buffers %d", llcp_ctx_buffers_free());
+}
+
+/*
+ * Central-initiated CIS Create procedure.
+ * Central requests CIS w. invalid param, peripheral Host rejects.
+ *
+ * +-----+          +-------+                       +-----+
+ * | UT  |          | LL_S  |                       | LT  |
+ * +-----+          +-------+                       +-----+
+ *    |                 |                               |
+ *    |                 |   LL_CIS_REQ  (invalid param) |
+ *    |                 |<------------------------------|
+ *    |                 |                               |
+ *    |                 |                               |
+ *    |                 |                               |
+ *    |                 |                               |
+ *    |                 |                               |
+ *    |                 |                               |
+ *    |                 | LL_REJECT_EXT_IND             |
+ *    |                 |------------------------------>|
+ *    |                 |                               |
+ */
+ZTEST(cis_create, test_cc_create_periph_rem_invalid_param)
+{
+	struct pdu_data_llctrl_cis_req remote_cis_req_invalid_param = remote_cis_req;
+
+	/* Rx with c_sdu_interval < 255 */
+	sys_put_le24(BT_HCI_ISO_SDU_INTERVAL_MIN-1, remote_cis_req_invalid_param.c_sdu_interval);
+	rx_remote_cis_req_invalid_param(&remote_cis_req_invalid_param);
+
+	/* Restore to valid params */
+	remote_cis_req_invalid_param = remote_cis_req;
+
+	/* Rx with p_sdu_interval < 255 */
+	sys_put_le24(BT_HCI_ISO_SDU_INTERVAL_MIN-1, remote_cis_req_invalid_param.p_sdu_interval);
+	rx_remote_cis_req_invalid_param(&remote_cis_req_invalid_param);
+
+	/* Restore to valid params */
+	remote_cis_req_invalid_param = remote_cis_req;
+
+	/* Rx with c_max_pdu > 251 */
+	remote_cis_req_invalid_param.c_max_pdu = sys_cpu_to_le16(BT_ISO_PDU_MAX + 1);
+	rx_remote_cis_req_invalid_param(&remote_cis_req_invalid_param);
+
+	/* Restore to valid params */
+	remote_cis_req_invalid_param = remote_cis_req;
+
+	/* Rx with p_max_pdu > 251 */
+	remote_cis_req_invalid_param.p_max_pdu = sys_cpu_to_le16(BT_ISO_PDU_MAX + 1);
+	rx_remote_cis_req_invalid_param(&remote_cis_req_invalid_param);
+
+	/* Restore to valid params */
+	remote_cis_req_invalid_param = remote_cis_req;
+
+	/* Rx with nse == 0 */
+	remote_cis_req_invalid_param.nse = 0;
+	rx_remote_cis_req_invalid_param(&remote_cis_req_invalid_param);
+
+	/* Restore to valid params */
+	remote_cis_req_invalid_param = remote_cis_req;
+
+	/* Rx with nse > 31 */
+	remote_cis_req_invalid_param.nse = BT_ISO_NSE_MAX + 1;
+	rx_remote_cis_req_invalid_param(&remote_cis_req_invalid_param);
+
+	/* Restore to valid params */
+	remote_cis_req_invalid_param = remote_cis_req;
+
+	/* Rx with sub_interval > 0 && nse == 1 */
+	remote_cis_req_invalid_param.nse = 1;
+	rx_remote_cis_req_invalid_param(&remote_cis_req_invalid_param);
+
+	/* Restore to valid params */
+	remote_cis_req_invalid_param = remote_cis_req;
+
+	/* Rx with sub_interval < 400 && nse > 1 */
+	sys_put_le24(SUB_INTERVAL_MIN - 1, remote_cis_req_invalid_param.sub_interval);
+	rx_remote_cis_req_invalid_param(&remote_cis_req_invalid_param);
+
+	/* Restore to valid params */
+	remote_cis_req_invalid_param = remote_cis_req;
+
+	/* Rx with sub_interval >= iso_interval */
+	sys_put_le24(sys_le16_to_cpu(remote_cis_req_invalid_param.iso_interval) * CONN_INT_UNIT_US,
+				     remote_cis_req_invalid_param.sub_interval);
+	rx_remote_cis_req_invalid_param(&remote_cis_req_invalid_param);
+
+	/* Restore to valid params */
+	remote_cis_req_invalid_param = remote_cis_req;
+
+
+	/* Rx with c_bn == 0 && c_max_pdu > 0 */
+	remote_cis_req_invalid_param.c_bn = 0;
+	rx_remote_cis_req_invalid_param(&remote_cis_req_invalid_param);
+
+	/* Restore to valid params */
+	remote_cis_req_invalid_param = remote_cis_req;
+
+	/* Rx with p_bn == 0 && p_max_pdu > 0 */
+	remote_cis_req_invalid_param.p_bn = 0;
+	rx_remote_cis_req_invalid_param(&remote_cis_req_invalid_param);
+
+	/* Restore to valid params */
+	remote_cis_req_invalid_param = remote_cis_req;
+
+	/* Rx with c_ft == 0 */
+	remote_cis_req_invalid_param.c_ft = 0;
+	rx_remote_cis_req_invalid_param(&remote_cis_req_invalid_param);
+
+	/* Restore to valid params */
+	remote_cis_req_invalid_param = remote_cis_req;
+
+	/* Rx with p_ft == 0 */
+	remote_cis_req_invalid_param.p_ft = 0;
+	rx_remote_cis_req_invalid_param(&remote_cis_req_invalid_param);
+
+	/* Restore to valid params */
+	remote_cis_req_invalid_param = remote_cis_req;
+
+	/* Rx with iso_interval < 4 */
+	remote_cis_req_invalid_param.iso_interval = sys_cpu_to_le16(BT_HCI_ISO_INTERVAL_MIN - 1);
+	rx_remote_cis_req_invalid_param(&remote_cis_req_invalid_param);
+
+	/* Restore to valid params */
+	remote_cis_req_invalid_param = remote_cis_req;
+
+	/* Rx with iso_interval > 3200 */
+	remote_cis_req_invalid_param.iso_interval = sys_cpu_to_le16(BT_HCI_ISO_INTERVAL_MAX + 1);
+	rx_remote_cis_req_invalid_param(&remote_cis_req_invalid_param);
+
+	/* Restore to valid params */
+	remote_cis_req_invalid_param = remote_cis_req;
+
+	/* Rx with cis_offset_min < 500 */
+	sys_put_le24(PDU_CIS_OFFSET_MIN_US - 1, remote_cis_req_invalid_param.cis_offset_min);
+	rx_remote_cis_req_invalid_param(&remote_cis_req_invalid_param);
+
+	/* Restore to valid params */
+	remote_cis_req_invalid_param = remote_cis_req;
+
+	/* Rx with cis_offset_max < cis_offset_min */
+	sys_put_le24(0x01FF, remote_cis_req_invalid_param.cis_offset_max);
+	rx_remote_cis_req_invalid_param(&remote_cis_req_invalid_param);
+
+	/* Restore to valid params */
+	remote_cis_req_invalid_param = remote_cis_req;
+
+	/* Rx with cis_offset_max >= conn_interval */
+	sys_put_le24(conn.lll.interval * CONN_INT_UNIT_US,
+		     remote_cis_req_invalid_param.cis_offset_max);
+	rx_remote_cis_req_invalid_param(&remote_cis_req_invalid_param);
+}
+
 /*
  * Central-initiated CIS Create procedure.
  * Host requests CIS, LL replies with 'remote feature unsupported'
@@ -579,7 +773,7 @@ ZTEST(cis_create, test_cc_create_central_rem_unsupported)
 	/* Prepare */
 	event_prepare(&conn);
 
-	/* There should be excactly one host notification
+	/* There should be exactly one host notification
 	 * with status BT_HCI_ERR_UNSUPP_REMOTE_FEATURE
 	 */
 	ut_rx_node(NODE_CIS_ESTABLISHED, &ntf, &cis_estab);
@@ -737,7 +931,7 @@ ZTEST(cis_create, test_cc_create_central_rem_accept)
 	/* Prepare */
 	event_prepare(&conn);
 
-	/* There should be excactly one host notification */
+	/* There should be exactly one host notification */
 	ut_rx_node(NODE_CIS_ESTABLISHED, &ntf, &cis_estab);
 	ut_rx_q_is_empty();
 
@@ -846,7 +1040,7 @@ ZTEST(cis_create, test_cc_create_central_rem_reject)
 	/* Prepare */
 	event_prepare(&conn);
 
-	/* There should be excactly one host notification */
+	/* There should be exactly one host notification */
 	ut_rx_node(NODE_CIS_ESTABLISHED, &ntf, &cis_estab);
 	ut_rx_q_is_empty();
 
diff --git a/tests/bluetooth/hci_codecs_info/src/main.c b/tests/bluetooth/hci_codecs_info/src/main.c
index 8f63e3782a8..1d2937a21e7 100644
--- a/tests/bluetooth/hci_codecs_info/src/main.c
+++ b/tests/bluetooth/hci_codecs_info/src/main.c
@@ -208,6 +208,8 @@ ZTEST(test_hci_codecs_info, test_read_codec_capabilities)
 	ptr = &rp->capabilities[0];
 	zassert_mem_equal(ptr, codec_capabilities, sizeof(codec_capabilities),
 			  0, "Reading codec capabilities content failed");
+
+	net_buf_unref(rsp);
 }
 
 #define READ_DELAY_CODING_FMT 0xff
@@ -290,4 +292,6 @@ ZTEST(test_hci_codecs_info, test_read_ctlr_delay)
 		      "Reading controller min delay failed");
 	zassert_equal(sys_get_le24(rp->max_ctlr_delay), MAX_CTLR_DELAY,
 		      "Reading controller max delay failed");
+
+	net_buf_unref(rsp);
 }
diff --git a/tests/bluetooth/host/conn/CMakeLists.txt b/tests/bluetooth/host/conn/CMakeLists.txt
index 23cf77fbd2f..2d3c317dec0 100644
--- a/tests/bluetooth/host/conn/CMakeLists.txt
+++ b/tests/bluetooth/host/conn/CMakeLists.txt
@@ -16,6 +16,10 @@ add_subdirectory(${ZEPHYR_BASE}/tests/bluetooth/host/conn/mocks mocks)
 
 target_link_libraries(testbinary PRIVATE mocks host_mocks)
 
+target_include_directories(mocks PUBLIC
+  ${ZEPHYR_BASE}/subsys/bluetooth/host
+)
+
 target_sources(testbinary
     PRIVATE
     src/main.c
diff --git a/tests/bluetooth/host/conn/src/main.c b/tests/bluetooth/host/conn/src/main.c
index 95220dc3873..d4c800bd521 100644
--- a/tests/bluetooth/host/conn/src/main.c
+++ b/tests/bluetooth/host/conn/src/main.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2024-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,6 +9,8 @@
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
 
+#include <host/conn_internal.h>
+
 #include "mocks/addr_internal.h"
 #include "mocks/att_internal.h"
 #include "mocks/bt_str.h"
@@ -132,3 +134,29 @@ ZTEST(conn, test_bt_conn_le_create_synced_check_null_conn)
 	err = bt_conn_le_create_synced(adv, &synced_param, &conn_param, &conn);
 	zassert_not_equal(err, -EINVAL, "Failed starting initiator (err %d)", err);
 }
+
+ZTEST(conn, test_bt_conn_is_type)
+{
+	struct bt_conn conn = {0};
+
+	conn.type = BT_CONN_TYPE_LE;
+	zassert_true(bt_conn_is_type(&conn, BT_CONN_TYPE_LE));
+	zassert_false(bt_conn_is_type(&conn, 0));
+	zassert_false(bt_conn_is_type(&conn, BT_CONN_TYPE_BR));
+	zassert_false(bt_conn_is_type(&conn, BT_CONN_TYPE_SCO));
+	zassert_false(bt_conn_is_type(&conn, BT_CONN_TYPE_ISO));
+
+	zassert_true(bt_conn_is_type(&conn, BT_CONN_TYPE_LE | BT_CONN_TYPE_BR));
+	zassert_true(bt_conn_is_type(&conn, BT_CONN_TYPE_LE | BT_CONN_TYPE_SCO));
+	zassert_true(bt_conn_is_type(&conn, BT_CONN_TYPE_LE | BT_CONN_TYPE_ISO));
+	zassert_true(bt_conn_is_type(&conn, BT_CONN_TYPE_ALL));
+
+	conn.type = BT_CONN_TYPE_BR;
+	zassert_true(bt_conn_is_type(&conn, BT_CONN_TYPE_BR));
+
+	conn.type = BT_CONN_TYPE_SCO;
+	zassert_true(bt_conn_is_type(&conn, BT_CONN_TYPE_SCO));
+
+	conn.type = BT_CONN_TYPE_ISO;
+	zassert_true(bt_conn_is_type(&conn, BT_CONN_TYPE_ISO));
+}
diff --git a/tests/bluetooth/host/id/mocks/conn.c b/tests/bluetooth/host/id/mocks/conn.c
index 14b18da99c4..99796076e01 100644
--- a/tests/bluetooth/host/id/mocks/conn.c
+++ b/tests/bluetooth/host/id/mocks/conn.c
@@ -1,14 +1,20 @@
 /*
- * Copyright (c) 2022 Nordic Semiconductor ASA
+ * Copyright (c) 2022-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "mocks/conn.h"
-
+#include <zephyr/bluetooth/conn.h>
 #include <zephyr/kernel.h>
 
+#include "mocks/conn.h"
+
 DEFINE_FAKE_VOID_FUNC(bt_conn_unref, struct bt_conn *);
 DEFINE_FAKE_VALUE_FUNC(int, bt_le_create_conn_cancel);
 DEFINE_FAKE_VALUE_FUNC(struct bt_conn *, bt_conn_lookup_state_le, uint8_t, const bt_addr_le_t *,
 		       const bt_conn_state_t);
+
+bool bt_conn_is_type(const struct bt_conn *conn, enum bt_conn_type type)
+{
+	return true;
+}
diff --git a/tests/bluetooth/host/id/mocks/conn.h b/tests/bluetooth/host/id/mocks/conn.h
index 4cfbe8d4e33..1d2da0a4106 100644
--- a/tests/bluetooth/host/id/mocks/conn.h
+++ b/tests/bluetooth/host/id/mocks/conn.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022 Nordic Semiconductor ASA
+ * Copyright (c) 2022-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,3 +20,4 @@ DECLARE_FAKE_VOID_FUNC(bt_conn_unref, struct bt_conn *);
 DECLARE_FAKE_VALUE_FUNC(int, bt_le_create_conn_cancel);
 DECLARE_FAKE_VALUE_FUNC(struct bt_conn *, bt_conn_lookup_state_le, uint8_t, const bt_addr_le_t *,
 			const bt_conn_state_t);
+DECLARE_FAKE_VALUE_FUNC(bool, bt_conn_is_type, const struct bt_conn *, enum bt_conn_type);
diff --git a/tests/bluetooth/host/keys/mocks/id.c b/tests/bluetooth/host/keys/mocks/id.c
index e72e6677f2a..e48adefb9fb 100644
--- a/tests/bluetooth/host/keys/mocks/id.c
+++ b/tests/bluetooth/host/keys/mocks/id.c
@@ -8,3 +8,6 @@
 #include "mocks/id.h"
 
 DEFINE_FAKE_VOID_FUNC(bt_id_del, struct bt_keys *);
+DEFINE_FAKE_VOID_FUNC(bt_id_pending_keys_update);
+DEFINE_FAKE_VOID_FUNC(bt_id_pending_keys_update_set, struct bt_keys *, uint8_t);
+DEFINE_FAKE_VALUE_FUNC(int, k_work_submit, struct k_work *);
diff --git a/tests/bluetooth/host/keys/mocks/id.h b/tests/bluetooth/host/keys/mocks/id.h
index 2c3f8e97d82..3efe45384f7 100644
--- a/tests/bluetooth/host/keys/mocks/id.h
+++ b/tests/bluetooth/host/keys/mocks/id.h
@@ -10,7 +10,13 @@
 #include <host/keys.h>
 
 /* List of fakes used by this unit tester */
-#define ID_FFF_FAKES_LIST(FAKE)        \
-		FAKE(bt_id_del)                \
+#define ID_FFF_FAKES_LIST(FAKE)                     \
+		FAKE(bt_id_del)                     \
+		FAKE(bt_id_pending_keys_update)     \
+		FAKE(bt_id_pending_keys_update_set) \
+		FAKE(k_work_submit)
 
 DECLARE_FAKE_VOID_FUNC(bt_id_del, struct bt_keys *);
+DECLARE_FAKE_VOID_FUNC(bt_id_pending_keys_update);
+DECLARE_FAKE_VOID_FUNC(bt_id_pending_keys_update_set, struct bt_keys *, uint8_t);
+DECLARE_FAKE_VALUE_FUNC(int, k_work_submit, struct k_work *);
diff --git a/tests/bluetooth/qualification/.gitattributes b/tests/bluetooth/qualification/.gitattributes
new file mode 100644
index 00000000000..c8553d3077b
--- /dev/null
+++ b/tests/bluetooth/qualification/.gitattributes
@@ -0,0 +1,6 @@
+# Files generated by Bluetooth Qualification Workspace.
+# Those are XML that don't follow Zephyr style guidance but shall
+# not be modified since otherwise BT SIG tools are not able to
+# import them. Just treat them as binaries.
+*.pts binary
+*.bqw binary
diff --git a/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.bqw b/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.bqw
index 907363f610f..d8e817e9faa 100644
--- a/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.bqw
+++ b/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.bqw
@@ -1,8 +1,8 @@
 <?xml version="1.0" encoding="utf-8"?>
-<Qualification xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema" DN="Q332723" DesignName="Zephyr Host" PathType="NewDesignNoDns" TCRL="85" xmlns="http://qualification.bluetooth.com">
+<Qualification xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xsd="http://www.w3.org/2001/XMLSchema" DN="Q347313" DesignName="Zephyr Host" PathType="NewDesignNoDns" TCRL="86" xmlns="http://qualification.bluetooth.com">
   <References />
   <Products>
-    <Product Name="Zephyr Host" Description="host" Model="main" Website="" PublishDate="2024-11-26T00:00:00" />
+    <Product Name="Zephyr Host" Description="host" Model="main" Website="" PublishDate="2025-02-28T00:00:00" />
   </Products>
   <Layers>
     <Layer Layer="GAP">
@@ -15,6 +15,7 @@
         <Feature>GAP 14a/1</Feature>
         <Feature>GAP 14a/13</Feature>
         <Feature>GAP 8a/19</Feature>
+        <Feature>GAP 20A/1</Feature>
         <Feature>GAP 27c/1</Feature>
         <Feature>GAP 35/11</Feature>
         <Feature>GAP 25/13b</Feature>
@@ -36,13 +37,6 @@
         <Feature>GAP 20A/15</Feature>
         <Feature>GAP 20A/3</Feature>
         <Feature>GAP 21/9</Feature>
-        <Feature>GAP 22/2</Feature>
-        <Feature>GAP 24/2</Feature>
-        <Feature>GAP 25/4</Feature>
-        <Feature>GAP 25/9</Feature>
-        <Feature>GAP 11b/3</Feature>
-        <Feature>GAP 37c/2</Feature>
-        <Feature>GAP 37/7</Feature>
         <Feature>GAP 17b/2</Feature>
         <Feature>GAP 30a/5</Feature>
         <Feature>GAP 17/5</Feature>
@@ -61,6 +55,141 @@
         <Feature>GAP 12/1</Feature>
         <Feature>GAP 13/1</Feature>
         <Feature>GAP 17/2</Feature>
+        <Feature>GAP 20A/14</Feature>
+        <Feature>GAP 21/10</Feature>
+        <Feature>GAP 21/2</Feature>
+        <Feature>GAP 22/1</Feature>
+        <Feature>GAP 22/3</Feature>
+        <Feature>GAP 24/4</Feature>
+        <Feature>GAP 27/2</Feature>
+        <Feature>GAP 31/10</Feature>
+        <Feature>GAP 32/1</Feature>
+        <Feature>GAP 32/2</Feature>
+        <Feature>GAP 35/2</Feature>
+        <Feature>GAP 37/1</Feature>
+        <Feature>GAP 5/4</Feature>
+        <Feature>GAP 8a/1</Feature>
+        <Feature>GAP 8a/4</Feature>
+        <Feature>GAP 22/2</Feature>
+        <Feature>GAP 24/2</Feature>
+        <Feature>GAP 25/4</Feature>
+        <Feature>GAP 25/9</Feature>
+        <Feature>GAP 27/6</Feature>
+        <Feature>GAP 27a/2</Feature>
+        <Feature>GAP 29/4</Feature>
+        <Feature>GAP 30/1</Feature>
+        <Feature>GAP 31/4</Feature>
+        <Feature>GAP 33/1</Feature>
+        <Feature>GAP 33/5</Feature>
+        <Feature>GAP 34/3</Feature>
+        <Feature>GAP 35/3</Feature>
+        <Feature>GAP 35/5</Feature>
+        <Feature>GAP 35/8</Feature>
+        <Feature>GAP 36/2</Feature>
+        <Feature>GAP 36/5</Feature>
+        <Feature>GAP 5/3</Feature>
+        <Feature>GAP 8a/2</Feature>
+        <Feature>GAP 8a/9</Feature>
+        <Feature>GAP 10/2</Feature>
+        <Feature>GAP 33/8</Feature>
+        <Feature>GAP 37c/3</Feature>
+        <Feature>GAP 37/6</Feature>
+        <Feature>GAP 35/15</Feature>
+        <Feature>GAP 14a/17</Feature>
+        <Feature>GAP 11/4</Feature>
+        <Feature>GAP 37b/9</Feature>
+        <Feature>GAP 37c/1</Feature>
+        <Feature>GAP 17b/4</Feature>
+        <Feature>GAP 11b/4</Feature>
+        <Feature>GAP 37b/3</Feature>
+        <Feature>GAP 30a/15</Feature>
+        <Feature>GAP 11b/2</Feature>
+        <Feature>GAP 14a/15</Feature>
+        <Feature>GAP 20A/19</Feature>
+        <Feature>GAP 30a/16</Feature>
+        <Feature>GAP 14a/10</Feature>
+        <Feature>GAP 27b/8</Feature>
+        <Feature>GAP 27b/3</Feature>
+        <Feature>GAP 27b/6</Feature>
+        <Feature>GAP 25/11</Feature>
+        <Feature>GAP 11/1</Feature>
+        <Feature>GAP 20/2</Feature>
+        <Feature>GAP 20A/4</Feature>
+        <Feature>GAP 21/6</Feature>
+        <Feature>GAP 21/8</Feature>
+        <Feature>GAP 23/4</Feature>
+        <Feature>GAP 25/3</Feature>
+        <Feature>GAP 25/8</Feature>
+        <Feature>GAP 31/11</Feature>
+        <Feature>GAP 31/2</Feature>
+        <Feature>GAP 31/5</Feature>
+        <Feature>GAP 33/6</Feature>
+        <Feature>GAP 35/7</Feature>
+        <Feature>GAP 37/2</Feature>
+        <Feature>GAP 37a/3</Feature>
+        <Feature>GAP 7/2</Feature>
+        <Feature>GAP 8/2</Feature>
+        <Feature>GAP 20/7</Feature>
+        <Feature>GAP 20A/11</Feature>
+        <Feature>GAP 20A/13</Feature>
+        <Feature>GAP 20A/16</Feature>
+        <Feature>GAP 20A/2</Feature>
+        <Feature>GAP 20A/9</Feature>
+        <Feature>GAP 21/7</Feature>
+        <Feature>GAP 23/1</Feature>
+        <Feature>GAP 23/5</Feature>
+        <Feature>GAP 27/1</Feature>
+        <Feature>GAP 27/9</Feature>
+        <Feature>GAP 28/1</Feature>
+        <Feature>GAP 30/2</Feature>
+        <Feature>GAP 31/1</Feature>
+        <Feature>GAP 31/6</Feature>
+        <Feature>GAP 31/9</Feature>
+        <Feature>GAP 8a/10</Feature>
+        <Feature>GAP 8a/13</Feature>
+        <Feature>GAP 8a/17</Feature>
+        <Feature>GAP 8a/3</Feature>
+        <Feature>GAP 8a/8</Feature>
+        <Feature>GAP 33/7</Feature>
+        <Feature>GAP 8a/14a</Feature>
+        <Feature>GAP 14a/16</Feature>
+        <Feature>GAP 27b/2</Feature>
+        <Feature>GAP 14a/19</Feature>
+        <Feature>GAP 35/13b</Feature>
+        <Feature>GAP 17b/3</Feature>
+        <Feature>GAP 25/13</Feature>
+        <Feature>GAP 14a/2</Feature>
+        <Feature>GAP 27/9a</Feature>
+        <Feature>GAP 35/13a</Feature>
+        <Feature>GAP 30a/11</Feature>
+        <Feature>GAP 30a/14a</Feature>
+        <Feature>GAP 37b/5</Feature>
+        <Feature>GAP 14a/8</Feature>
+        <Feature>GAP 14a/12</Feature>
+        <Feature>GAP 10/1</Feature>
+        <Feature>GAP 14/1</Feature>
+        <Feature>GAP 20A/6</Feature>
+        <Feature>GAP 21/1</Feature>
+        <Feature>GAP 21/11</Feature>
+        <Feature>GAP 21/4</Feature>
+        <Feature>GAP 22/4</Feature>
+        <Feature>GAP 24/1</Feature>
+        <Feature>GAP 24/3</Feature>
+        <Feature>GAP 25/10</Feature>
+        <Feature>GAP 26/1</Feature>
+        <Feature>GAP 26/2</Feature>
+        <Feature>GAP 26/4</Feature>
+        <Feature>GAP 29/3</Feature>
+        <Feature>GAP 31/8</Feature>
+        <Feature>GAP 32/3</Feature>
+        <Feature>GAP 33/2</Feature>
+        <Feature>GAP 34/2</Feature>
+        <Feature>GAP 5/2</Feature>
+        <Feature>GAP 8/3</Feature>
+        <Feature>GAP 8a/5</Feature>
+        <Feature>GAP 10/5</Feature>
+        <Feature>GAP 11b/1</Feature>
+        <Feature>GAP 16/3</Feature>
         <Feature>GAP 37/3a</Feature>
         <Feature>GAP 25/12</Feature>
         <Feature>GAP 30a/19</Feature>
@@ -144,61 +273,9 @@
         <Feature>GAP 10/3</Feature>
         <Feature>GAP 23/7</Feature>
         <Feature>GAP 7/3</Feature>
-        <Feature>GAP 37c/3</Feature>
-        <Feature>GAP 37/6</Feature>
-        <Feature>GAP 35/15</Feature>
-        <Feature>GAP 14a/17</Feature>
-        <Feature>GAP 11/4</Feature>
-        <Feature>GAP 37b/9</Feature>
-        <Feature>GAP 37c/1</Feature>
-        <Feature>GAP 17b/4</Feature>
-        <Feature>GAP 11b/4</Feature>
-        <Feature>GAP 37b/3</Feature>
-        <Feature>GAP 30a/15</Feature>
-        <Feature>GAP 11b/2</Feature>
-        <Feature>GAP 14a/15</Feature>
-        <Feature>GAP 20A/19</Feature>
-        <Feature>GAP 30a/16</Feature>
-        <Feature>GAP 14a/10</Feature>
-        <Feature>GAP 27b/8</Feature>
-        <Feature>GAP 27b/3</Feature>
-        <Feature>GAP 27b/6</Feature>
-        <Feature>GAP 25/11</Feature>
-        <Feature>GAP 11/1</Feature>
-        <Feature>GAP 20/2</Feature>
-        <Feature>GAP 20A/4</Feature>
-        <Feature>GAP 21/6</Feature>
-        <Feature>GAP 21/8</Feature>
-        <Feature>GAP 23/4</Feature>
-        <Feature>GAP 25/3</Feature>
-        <Feature>GAP 25/8</Feature>
-        <Feature>GAP 31/11</Feature>
-        <Feature>GAP 31/2</Feature>
-        <Feature>GAP 31/5</Feature>
-        <Feature>GAP 33/6</Feature>
-        <Feature>GAP 35/7</Feature>
-        <Feature>GAP 37/2</Feature>
-        <Feature>GAP 37a/3</Feature>
-        <Feature>GAP 7/2</Feature>
-        <Feature>GAP 8/2</Feature>
-        <Feature>GAP 27/6</Feature>
-        <Feature>GAP 27a/2</Feature>
-        <Feature>GAP 29/4</Feature>
-        <Feature>GAP 30/1</Feature>
-        <Feature>GAP 31/4</Feature>
-        <Feature>GAP 33/1</Feature>
-        <Feature>GAP 33/5</Feature>
-        <Feature>GAP 34/3</Feature>
-        <Feature>GAP 35/3</Feature>
-        <Feature>GAP 35/5</Feature>
-        <Feature>GAP 35/8</Feature>
-        <Feature>GAP 36/2</Feature>
-        <Feature>GAP 36/5</Feature>
-        <Feature>GAP 5/3</Feature>
-        <Feature>GAP 8a/2</Feature>
-        <Feature>GAP 8a/9</Feature>
-        <Feature>GAP 10/2</Feature>
-        <Feature>GAP 33/8</Feature>
+        <Feature>GAP 11b/3</Feature>
+        <Feature>GAP 37c/2</Feature>
+        <Feature>GAP 37/7</Feature>
         <Feature>GAP 37a/5</Feature>
         <Feature>GAP 20A/14a</Feature>
         <Feature>GAP 37b/2</Feature>
@@ -232,118 +309,92 @@
         <Feature>GAP 10/4</Feature>
         <Feature>GAP 16/2</Feature>
         <Feature>GAP 16/4</Feature>
-        <Feature>GAP 8a/14a</Feature>
-        <Feature>GAP 14a/16</Feature>
-        <Feature>GAP 27b/2</Feature>
-        <Feature>GAP 14a/19</Feature>
-        <Feature>GAP 35/13b</Feature>
-        <Feature>GAP 17b/3</Feature>
-        <Feature>GAP 25/13</Feature>
-        <Feature>GAP 14a/2</Feature>
-        <Feature>GAP 27/9a</Feature>
-        <Feature>GAP 35/13a</Feature>
-        <Feature>GAP 30a/11</Feature>
-        <Feature>GAP 30a/14a</Feature>
-        <Feature>GAP 37b/5</Feature>
-        <Feature>GAP 14a/8</Feature>
-        <Feature>GAP 14a/12</Feature>
-        <Feature>GAP 10/1</Feature>
-        <Feature>GAP 14/1</Feature>
-        <Feature>GAP 20A/6</Feature>
-        <Feature>GAP 21/1</Feature>
-        <Feature>GAP 21/11</Feature>
-        <Feature>GAP 21/4</Feature>
-        <Feature>GAP 22/4</Feature>
-        <Feature>GAP 24/1</Feature>
-        <Feature>GAP 24/3</Feature>
-        <Feature>GAP 25/10</Feature>
-        <Feature>GAP 26/1</Feature>
-        <Feature>GAP 26/2</Feature>
-        <Feature>GAP 26/4</Feature>
-        <Feature>GAP 29/3</Feature>
-        <Feature>GAP 31/8</Feature>
-        <Feature>GAP 32/3</Feature>
-        <Feature>GAP 33/2</Feature>
-        <Feature>GAP 34/2</Feature>
-        <Feature>GAP 5/2</Feature>
-        <Feature>GAP 8/3</Feature>
-        <Feature>GAP 8a/5</Feature>
-        <Feature>GAP 10/5</Feature>
-        <Feature>GAP 11b/1</Feature>
-        <Feature>GAP 16/3</Feature>
-        <Feature>GAP 20/7</Feature>
-        <Feature>GAP 20A/11</Feature>
-        <Feature>GAP 20A/13</Feature>
-        <Feature>GAP 20A/16</Feature>
-        <Feature>GAP 20A/2</Feature>
-        <Feature>GAP 20A/9</Feature>
-        <Feature>GAP 21/7</Feature>
-        <Feature>GAP 23/1</Feature>
-        <Feature>GAP 23/5</Feature>
-        <Feature>GAP 27/1</Feature>
-        <Feature>GAP 27/9</Feature>
-        <Feature>GAP 28/1</Feature>
-        <Feature>GAP 30/2</Feature>
-        <Feature>GAP 31/1</Feature>
-        <Feature>GAP 31/6</Feature>
-        <Feature>GAP 31/9</Feature>
-        <Feature>GAP 8a/10</Feature>
-        <Feature>GAP 8a/13</Feature>
-        <Feature>GAP 8a/17</Feature>
-        <Feature>GAP 8a/3</Feature>
-        <Feature>GAP 8a/8</Feature>
-        <Feature>GAP 33/7</Feature>
-        <Feature>GAP 20A/1</Feature>
-        <Feature>GAP 20A/14</Feature>
-        <Feature>GAP 21/10</Feature>
-        <Feature>GAP 21/2</Feature>
-        <Feature>GAP 22/1</Feature>
-        <Feature>GAP 22/3</Feature>
-        <Feature>GAP 24/4</Feature>
-        <Feature>GAP 27/2</Feature>
-        <Feature>GAP 31/10</Feature>
-        <Feature>GAP 32/1</Feature>
-        <Feature>GAP 32/2</Feature>
-        <Feature>GAP 35/2</Feature>
-        <Feature>GAP 37/1</Feature>
-        <Feature>GAP 5/4</Feature>
-        <Feature>GAP 8a/1</Feature>
-        <Feature>GAP 8a/4</Feature>
       </Features>
     </Layer>
     <Layer Layer="L2CAP">
       <Features>
-        <Feature>L2CAP 2/49</Feature>
-        <Feature>L2CAP 2/45a</Feature>
-        <Feature>L2CAP 1/6</Feature>
-        <Feature>L2CAP 3/16</Feature>
-        <Feature>L2CAP 0/2</Feature>
-        <Feature>L2CAP 4/3</Feature>
-        <Feature>L2CAP 1/5</Feature>
         <Feature>L2CAP 2/48b</Feature>
         <Feature>L2CAP 4/2</Feature>
         <Feature>L2CAP 2/41</Feature>
         <Feature>L2CAP 2/46</Feature>
         <Feature>L2CAP 3/1</Feature>
+        <Feature>L2CAP 2/45a</Feature>
+        <Feature>L2CAP 1/6</Feature>
+        <Feature>L2CAP 1/3</Feature>
         <Feature>L2CAP 4/1</Feature>
         <Feature>L2CAP 2/43</Feature>
         <Feature>L2CAP 3/12</Feature>
         <Feature>L2CAP 1/4</Feature>
         <Feature>L2CAP 2/48</Feature>
+        <Feature>L2CAP 3/16</Feature>
+        <Feature>L2CAP 0/2</Feature>
+        <Feature>L2CAP 2/49</Feature>
+        <Feature>L2CAP 4/3</Feature>
+        <Feature>L2CAP 1/5</Feature>
         <Feature>L2CAP 2/40</Feature>
         <Feature>L2CAP 2/42</Feature>
         <Feature>L2CAP 2/47</Feature>
-        <Feature>L2CAP 1/3</Feature>
-      </Features>
-    </Layer>
-    <Layer Layer="IOP">
-      <Features>
-        <Feature>IOP 1/1</Feature>
-        <Feature>IOP 2/2</Feature>
       </Features>
     </Layer>
     <Layer Layer="GATT">
       <Features>
+        <Feature>GATT 8/8</Feature>
+        <Feature>GATT 10/5</Feature>
+        <Feature>GATT 9/6</Feature>
+        <Feature>GATT 9/5</Feature>
+        <Feature>GATT 3/1</Feature>
+        <Feature>GATT 3/7</Feature>
+        <Feature>GATT 4/14</Feature>
+        <Feature>GATT 4/25</Feature>
+        <Feature>GATT 4/8</Feature>
+        <Feature>GATT 7/7</Feature>
+        <Feature>GATT 10/6</Feature>
+        <Feature>GATT 10/1</Feature>
+        <Feature>GATT 9/4</Feature>
+        <Feature>GATT 10/3</Feature>
+        <Feature>GATT 4a/2</Feature>
+        <Feature>GATT 10/4</Feature>
+        <Feature>GATT 3/25</Feature>
+        <Feature>GATT 3/6</Feature>
+        <Feature>GATT 4/17</Feature>
+        <Feature>GATT 4/19</Feature>
+        <Feature>GATT 4/4</Feature>
+        <Feature>GATT 10/11</Feature>
+        <Feature>GATT 2/3a</Feature>
+        <Feature>GATT 9/2</Feature>
+        <Feature>GATT 3a/2</Feature>
+        <Feature>GATT 2/4</Feature>
+        <Feature>GATT 9/1</Feature>
+        <Feature>GATT 4/30</Feature>
+        <Feature>GATT 4/31</Feature>
+        <Feature>GATT 2/2</Feature>
+        <Feature>GATT 3/15</Feature>
+        <Feature>GATT 3/4</Feature>
+        <Feature>GATT 3/9</Feature>
+        <Feature>GATT 4/1</Feature>
+        <Feature>GATT 4/13</Feature>
+        <Feature>GATT 4/18</Feature>
+        <Feature>GATT 4/3</Feature>
+        <Feature>GATT 7/3</Feature>
+        <Feature>GATT 4a/1</Feature>
+        <Feature>GATT 1/1</Feature>
+        <Feature>GATT 3/29</Feature>
+        <Feature>GATT 3/21</Feature>
+        <Feature>GATT 3/22</Feature>
+        <Feature>GATT 3/23</Feature>
+        <Feature>GATT 3/5</Feature>
+        <Feature>GATT 4/10</Feature>
+        <Feature>GATT 4/15</Feature>
+        <Feature>GATT 4/7</Feature>
+        <Feature>GATT 9/10</Feature>
+        <Feature>GATT 3a/1</Feature>
+        <Feature>GATT 9/12</Feature>
+        <Feature>GATT 1a/1</Feature>
+        <Feature>GATT 1a/3</Feature>
+        <Feature>GATT 4/11</Feature>
+        <Feature>GATT 4/12</Feature>
+        <Feature>GATT 4/9</Feature>
+        <Feature>GATT 7/2</Feature>
         <Feature>GATT 9/15</Feature>
         <Feature>GATT 2/5</Feature>
         <Feature>GATT 9/11</Feature>
@@ -374,34 +425,6 @@
         <Feature>GATT 4/20</Feature>
         <Feature>GATT 4/23</Feature>
         <Feature>GATT 4/26</Feature>
-        <Feature>GATT 10/11</Feature>
-        <Feature>GATT 2/3a</Feature>
-        <Feature>GATT 9/2</Feature>
-        <Feature>GATT 3a/2</Feature>
-        <Feature>GATT 2/4</Feature>
-        <Feature>GATT 9/1</Feature>
-        <Feature>GATT 4/30</Feature>
-        <Feature>GATT 4/31</Feature>
-        <Feature>GATT 2/2</Feature>
-        <Feature>GATT 3/15</Feature>
-        <Feature>GATT 3/4</Feature>
-        <Feature>GATT 3/9</Feature>
-        <Feature>GATT 4/1</Feature>
-        <Feature>GATT 4/13</Feature>
-        <Feature>GATT 4/18</Feature>
-        <Feature>GATT 4/3</Feature>
-        <Feature>GATT 7/3</Feature>
-        <Feature>GATT 10/6</Feature>
-        <Feature>GATT 10/1</Feature>
-        <Feature>GATT 9/4</Feature>
-        <Feature>GATT 10/3</Feature>
-        <Feature>GATT 4a/2</Feature>
-        <Feature>GATT 10/4</Feature>
-        <Feature>GATT 3/25</Feature>
-        <Feature>GATT 3/6</Feature>
-        <Feature>GATT 4/17</Feature>
-        <Feature>GATT 4/19</Feature>
-        <Feature>GATT 4/4</Feature>
         <Feature>GATT 10/7</Feature>
         <Feature>GATT 10/12</Feature>
         <Feature>GATT 9/8</Feature>
@@ -417,82 +440,51 @@
         <Feature>GATT 4/22</Feature>
         <Feature>GATT 7/4</Feature>
         <Feature>GATT 7/6</Feature>
-        <Feature>GATT 9/10</Feature>
-        <Feature>GATT 3a/1</Feature>
-        <Feature>GATT 9/12</Feature>
-        <Feature>GATT 1a/1</Feature>
-        <Feature>GATT 1a/3</Feature>
-        <Feature>GATT 4/11</Feature>
-        <Feature>GATT 4/12</Feature>
-        <Feature>GATT 4/9</Feature>
-        <Feature>GATT 7/2</Feature>
-        <Feature>GATT 4a/1</Feature>
-        <Feature>GATT 1/1</Feature>
-        <Feature>GATT 3/29</Feature>
-        <Feature>GATT 3/21</Feature>
-        <Feature>GATT 3/22</Feature>
-        <Feature>GATT 3/23</Feature>
-        <Feature>GATT 3/5</Feature>
-        <Feature>GATT 4/10</Feature>
-        <Feature>GATT 4/15</Feature>
-        <Feature>GATT 4/7</Feature>
-        <Feature>GATT 8/8</Feature>
-        <Feature>GATT 10/5</Feature>
-        <Feature>GATT 9/6</Feature>
-        <Feature>GATT 9/5</Feature>
-        <Feature>GATT 3/1</Feature>
-        <Feature>GATT 3/7</Feature>
-        <Feature>GATT 4/14</Feature>
-        <Feature>GATT 4/25</Feature>
-        <Feature>GATT 4/8</Feature>
-        <Feature>GATT 7/7</Feature>
       </Features>
     </Layer>
     <Layer Layer="SM">
       <Features>
-        <Feature>SM 7b/2</Feature>
-        <Feature>SM 3/1</Feature>
-        <Feature>SM 5/2</Feature>
-        <Feature>SM 7b/3</Feature>
-        <Feature>SM 7a/3</Feature>
-        <Feature>SM 7b/1</Feature>
-        <Feature>SM 4/3</Feature>
-        <Feature>SM 1/2</Feature>
-        <Feature>SM 4/1</Feature>
-        <Feature>SM 5/3</Feature>
-        <Feature>SM 6/1</Feature>
         <Feature>SM 7a/1</Feature>
         <Feature>SM 2/3</Feature>
         <Feature>SM 2/5</Feature>
         <Feature>SM 4/2</Feature>
         <Feature>SM 1/1</Feature>
         <Feature>SM 2/1</Feature>
+        <Feature>SM 7b/3</Feature>
+        <Feature>SM 7a/3</Feature>
         <Feature>SM 7a/2</Feature>
         <Feature>SM 2/2</Feature>
         <Feature>SM 5/1</Feature>
         <Feature>SM 5/4</Feature>
         <Feature>SM 6/2</Feature>
+        <Feature>SM 7b/2</Feature>
+        <Feature>SM 3/1</Feature>
+        <Feature>SM 5/2</Feature>
+        <Feature>SM 7b/1</Feature>
+        <Feature>SM 4/3</Feature>
+        <Feature>SM 1/2</Feature>
+        <Feature>SM 4/1</Feature>
+        <Feature>SM 5/3</Feature>
+        <Feature>SM 6/1</Feature>
       </Features>
     </Layer>
     <Layer Layer="ATT">
       <Features>
-        <Feature>ATT 7/3</Feature>
-        <Feature>ATT 4/32</Feature>
-        <Feature>ATT 2/2</Feature>
-        <Feature>ATT 3/11</Feature>
-        <Feature>ATT 3/14</Feature>
-        <Feature>ATT 3/17</Feature>
-        <Feature>ATT 3/7</Feature>
-        <Feature>ATT 4/19</Feature>
-        <Feature>ATT 4/3</Feature>
-        <Feature>ATT 4/6</Feature>
-        <Feature>ATT 4/9</Feature>
         <Feature>ATT 6/1</Feature>
         <Feature>ATT 3/12</Feature>
         <Feature>ATT 3/15</Feature>
         <Feature>ATT 3/18</Feature>
         <Feature>ATT 4/10</Feature>
         <Feature>ATT 4/20</Feature>
+        <Feature>ATT 7/1</Feature>
+        <Feature>ATT 3/30</Feature>
+        <Feature>ATT 3/32</Feature>
+        <Feature>ATT 4/12</Feature>
+        <Feature>ATT 4/22</Feature>
+        <Feature>ATT 4/24</Feature>
+        <Feature>ATT 4/27</Feature>
+        <Feature>ATT 4/7</Feature>
+        <Feature>ATT 4/8</Feature>
         <Feature>ATT 1/2</Feature>
         <Feature>ATT 3/1</Feature>
         <Feature>ATT 3/13</Feature>
@@ -507,20 +499,17 @@
         <Feature>ATT 4/21</Feature>
         <Feature>ATT 4/25</Feature>
         <Feature>ATT 4/28</Feature>
-        <Feature>ATT 1/1</Feature>
-        <Feature>ATT 4/31</Feature>
-        <Feature>ATT 3/26</Feature>
-        <Feature>ATT 4/1</Feature>
-        <Feature>ATT 4/13</Feature>
-        <Feature>ATT 7/1</Feature>
-        <Feature>ATT 3/30</Feature>
-        <Feature>ATT 3/32</Feature>
-        <Feature>ATT 4/12</Feature>
-        <Feature>ATT 4/22</Feature>
-        <Feature>ATT 4/24</Feature>
-        <Feature>ATT 4/27</Feature>
-        <Feature>ATT 4/7</Feature>
-        <Feature>ATT 4/8</Feature>
+        <Feature>ATT 7/3</Feature>
+        <Feature>ATT 4/32</Feature>
+        <Feature>ATT 2/2</Feature>
+        <Feature>ATT 3/11</Feature>
+        <Feature>ATT 3/14</Feature>
+        <Feature>ATT 3/17</Feature>
+        <Feature>ATT 3/7</Feature>
+        <Feature>ATT 4/19</Feature>
+        <Feature>ATT 4/3</Feature>
+        <Feature>ATT 4/6</Feature>
+        <Feature>ATT 4/9</Feature>
         <Feature>ATT 7/2</Feature>
         <Feature>ATT 3/23</Feature>
         <Feature>ATT 3/8</Feature>
@@ -529,8 +518,6 @@
         <Feature>ATT 4/23</Feature>
         <Feature>ATT 4/4</Feature>
         <Feature>ATT 4/5</Feature>
-        <Feature>ATT 3/10</Feature>
-        <Feature>ATT 3/16</Feature>
         <Feature>ATT 2/3a</Feature>
         <Feature>ATT 3/31</Feature>
         <Feature>ATT 4/33</Feature>
@@ -546,71 +533,91 @@
         <Feature>ATT 4/16</Feature>
         <Feature>ATT 4/2</Feature>
         <Feature>ATT 4/26</Feature>
+        <Feature>ATT 1/1</Feature>
+        <Feature>ATT 4/31</Feature>
+        <Feature>ATT 3/26</Feature>
+        <Feature>ATT 4/1</Feature>
+        <Feature>ATT 4/13</Feature>
+        <Feature>ATT 3/10</Feature>
+        <Feature>ATT 3/16</Feature>
       </Features>
     </Layer>
     <Layer Layer="DIS">
       <Features>
         <Feature>DIS 3/3</Feature>
         <Feature>DIS 2/7</Feature>
-        <Feature>DIS 2/4</Feature>
-        <Feature>DIS 2/6</Feature>
         <Feature>DIS 2/11</Feature>
-        <Feature>DIS 2/3</Feature>
-        <Feature>DIS 2/5</Feature>
         <Feature>DIS 5/1</Feature>
         <Feature>DIS 0/2</Feature>
         <Feature>DIS 2/1</Feature>
         <Feature>DIS 1/2</Feature>
         <Feature>DIS 2/2</Feature>
+        <Feature>DIS 2/3</Feature>
+        <Feature>DIS 2/5</Feature>
+        <Feature>DIS 2/4</Feature>
+        <Feature>DIS 2/6</Feature>
       </Features>
     </Layer>
     <Layer Layer="IAS">
       <Features>
-        <Feature>IAS 0/1</Feature>
-        <Feature>IAS 2/1</Feature>
-        <Feature>IAS 2/4</Feature>
-        <Feature>IAS 3/1</Feature>
         <Feature>IAS 3/2</Feature>
         <Feature>IAS 1/2</Feature>
+        <Feature>IAS 3/1</Feature>
         <Feature>IAS 2/2</Feature>
         <Feature>IAS 2/3</Feature>
+        <Feature>IAS 0/1</Feature>
+        <Feature>IAS 2/1</Feature>
+        <Feature>IAS 2/4</Feature>
       </Features>
     </Layer>
     <Layer Layer="HRS">
       <Features>
-        <Feature>HRS 2/2</Feature>
+        <Feature>HRS 3/4</Feature>
+        <Feature>HRS 3/6</Feature>
+        <Feature>HRS 2/1</Feature>
         <Feature>HRS 0/1</Feature>
         <Feature>HRS 3/2</Feature>
         <Feature>HRS 3/5</Feature>
-        <Feature>HRS 3/6</Feature>
-        <Feature>HRS 2/1</Feature>
+        <Feature>HRS 2/2</Feature>
         <Feature>HRS 1/2</Feature>
-        <Feature>HRS 3/4</Feature>
       </Features>
     </Layer>
     <Layer Layer="BAS">
       <Features>
-        <Feature>BAS 0/2</Feature>
-        <Feature>BAS 2/3</Feature>
         <Feature>BAS 4/1</Feature>
+        <Feature>BAS 3/5</Feature>
         <Feature>BAS 4/2</Feature>
         <Feature>BAS 1/2</Feature>
-        <Feature>BAS 3/5</Feature>
+        <Feature>BAS 0/2</Feature>
+        <Feature>BAS 2/3</Feature>
         <Feature>BAS 3/3</Feature>
         <Feature>BAS 2/1</Feature>
       </Features>
     </Layer>
     <Layer Layer="OTS">
       <Features>
-        <Feature>OTS 8/8</Feature>
-        <Feature>OTS 5/9</Feature>
-        <Feature>OTS 6/3</Feature>
-        <Feature>OTS 7/1</Feature>
+        <Feature>OTS 8/6</Feature>
+        <Feature>OTS 4/13</Feature>
+        <Feature>OTS 4/15</Feature>
+        <Feature>OTS 6/1</Feature>
+        <Feature>OTS 8/3</Feature>
+        <Feature>OTS 3/2</Feature>
+        <Feature>OTS 4/12</Feature>
+        <Feature>OTS 4/4</Feature>
+        <Feature>OTS 4/5</Feature>
+        <Feature>OTS 5/2</Feature>
+        <Feature>OTS 8/1</Feature>
+        <Feature>OTS 4/1</Feature>
+        <Feature>OTS 5/5</Feature>
         <Feature>OTS 4/16</Feature>
         <Feature>OTS 4/2</Feature>
         <Feature>OTS 4/20</Feature>
         <Feature>OTS 4/3</Feature>
         <Feature>OTS 5/1</Feature>
+        <Feature>OTS 8/8</Feature>
+        <Feature>OTS 5/9</Feature>
+        <Feature>OTS 6/3</Feature>
+        <Feature>OTS 7/1</Feature>
         <Feature>OTS 0/1</Feature>
         <Feature>OTS 8/7</Feature>
         <Feature>OTS 8/4</Feature>
@@ -624,64 +631,16 @@
         <Feature>OTS 6/2</Feature>
         <Feature>OTS 6/4</Feature>
         <Feature>OTS 6/5</Feature>
-        <Feature>OTS 8/6</Feature>
-        <Feature>OTS 4/13</Feature>
-        <Feature>OTS 4/15</Feature>
-        <Feature>OTS 6/1</Feature>
-        <Feature>OTS 8/1</Feature>
-        <Feature>OTS 4/1</Feature>
-        <Feature>OTS 5/5</Feature>
-        <Feature>OTS 8/3</Feature>
-        <Feature>OTS 3/2</Feature>
-        <Feature>OTS 4/12</Feature>
-        <Feature>OTS 4/4</Feature>
-        <Feature>OTS 4/5</Feature>
-        <Feature>OTS 5/2</Feature>
       </Features>
     </Layer>
     <Layer Layer="OTP">
       <Features>
-        <Feature>OTP 9/13</Feature>
-        <Feature>OTP 9/6</Feature>
-        <Feature>OTP 6/7</Feature>
-        <Feature>OTP 6/9</Feature>
-        <Feature>OTP 8/19</Feature>
-        <Feature>OTP 9/18</Feature>
-        <Feature>OTP 3/2</Feature>
-        <Feature>OTP 6/1</Feature>
-        <Feature>OTP 6/13</Feature>
-        <Feature>OTP 7/16</Feature>
-        <Feature>OTP 8/18</Feature>
         <Feature>OTP 9/12</Feature>
-        <Feature>OTP 9/10</Feature>
-        <Feature>OTP 2/1</Feature>
-        <Feature>OTP 6/11</Feature>
-        <Feature>OTP 7/15</Feature>
-        <Feature>OTP 7/17</Feature>
-        <Feature>OTP 9/5</Feature>
-        <Feature>OTP 9/8</Feature>
-        <Feature>OTP 7/18</Feature>
-        <Feature>OTP 8/1</Feature>
-        <Feature>OTP 9/4</Feature>
-        <Feature>OTP 9/9</Feature>
-        <Feature>OTP 2/2</Feature>
-        <Feature>OTP 5/1</Feature>
-        <Feature>OTP 7/12</Feature>
-        <Feature>OTP 7/6</Feature>
         <Feature>OTP 6/10</Feature>
         <Feature>OTP 6/12</Feature>
         <Feature>OTP 7/1</Feature>
         <Feature>OTP 7/20</Feature>
         <Feature>OTP 7/7</Feature>
-        <Feature>OTP 10/1</Feature>
-        <Feature>OTP 9/14</Feature>
-        <Feature>OTP 9/16</Feature>
-        <Feature>OTP 9/1</Feature>
-        <Feature>OTP 4/1</Feature>
-        <Feature>OTP 6/14</Feature>
-        <Feature>OTP 6/2</Feature>
-        <Feature>OTP 7/2</Feature>
-        <Feature>OTP 8/17</Feature>
         <Feature>OTP 9/11</Feature>
         <Feature>OTP 9/15</Feature>
         <Feature>OTP 9/3</Feature>
@@ -692,19 +651,57 @@
         <Feature>OTP 7/3</Feature>
         <Feature>OTP 8/2</Feature>
         <Feature>OTP 8/30</Feature>
+        <Feature>OTP 10/1</Feature>
+        <Feature>OTP 9/14</Feature>
+        <Feature>OTP 9/16</Feature>
+        <Feature>OTP 9/1</Feature>
+        <Feature>OTP 4/1</Feature>
+        <Feature>OTP 6/14</Feature>
+        <Feature>OTP 6/2</Feature>
+        <Feature>OTP 7/2</Feature>
+        <Feature>OTP 8/17</Feature>
+        <Feature>OTP 9/18</Feature>
+        <Feature>OTP 3/2</Feature>
+        <Feature>OTP 6/1</Feature>
+        <Feature>OTP 6/13</Feature>
+        <Feature>OTP 7/16</Feature>
+        <Feature>OTP 8/18</Feature>
+        <Feature>OTP 9/13</Feature>
+        <Feature>OTP 9/6</Feature>
+        <Feature>OTP 6/7</Feature>
+        <Feature>OTP 6/9</Feature>
+        <Feature>OTP 8/19</Feature>
+        <Feature>OTP 9/5</Feature>
+        <Feature>OTP 9/8</Feature>
+        <Feature>OTP 7/18</Feature>
+        <Feature>OTP 8/1</Feature>
+        <Feature>OTP 9/4</Feature>
+        <Feature>OTP 9/9</Feature>
+        <Feature>OTP 2/2</Feature>
+        <Feature>OTP 5/1</Feature>
+        <Feature>OTP 7/12</Feature>
+        <Feature>OTP 7/6</Feature>
+        <Feature>OTP 9/10</Feature>
+        <Feature>OTP 2/1</Feature>
+        <Feature>OTP 6/11</Feature>
+        <Feature>OTP 7/15</Feature>
+        <Feature>OTP 7/17</Feature>
       </Features>
     </Layer>
     <Layer Layer="MESH">
       <Features>
-        <Feature>MESH 11/15</Feature>
-        <Feature>MESH 2/2</Feature>
-        <Feature>MESH 12/3</Feature>
-        <Feature>MESH 12/6</Feature>
-        <Feature>MESH 4/3</Feature>
-        <Feature>MESH 4/8</Feature>
-        <Feature>MESH 5/4</Feature>
-        <Feature>MESH 18/11</Feature>
-        <Feature>MESH 21/2</Feature>
+        <Feature>MESH 11/23</Feature>
+        <Feature>MESH 12/12</Feature>
+        <Feature>MESH 18/12</Feature>
+        <Feature>MESH 1a/2</Feature>
+        <Feature>MESH 11/14</Feature>
+        <Feature>MESH 4/13</Feature>
+        <Feature>MESH 11/6</Feature>
+        <Feature>MESH 14/1</Feature>
+        <Feature>MESH 4/11</Feature>
+        <Feature>MESH 7/4</Feature>
+        <Feature>MESH 18/2</Feature>
+        <Feature>MESH 18/6</Feature>
         <Feature>MESH 11/24</Feature>
         <Feature>MESH 11/16</Feature>
         <Feature>MESH 11/7</Feature>
@@ -719,9 +716,30 @@
         <Feature>MESH 5/1</Feature>
         <Feature>MESH 5/2</Feature>
         <Feature>MESH 6/2</Feature>
-        <Feature>MESH 18/5</Feature>
-        <Feature>MESH 18/8</Feature>
-        <Feature>MESH 20/1</Feature>
+        <Feature>MESH 11/11</Feature>
+        <Feature>MESH 4/14</Feature>
+        <Feature>MESH 12/8</Feature>
+        <Feature>MESH 18/13</Feature>
+        <Feature>MESH 2/1</Feature>
+        <Feature>MESH 10/4</Feature>
+        <Feature>MESH 15/4</Feature>
+        <Feature>MESH 15/5</Feature>
+        <Feature>MESH 16/5</Feature>
+        <Feature>MESH 4/7</Feature>
+        <Feature>MESH 7/3</Feature>
+        <Feature>MESH 19/1</Feature>
+        <Feature>MESH 4/17</Feature>
+        <Feature>MESH 10/1</Feature>
+        <Feature>MESH 13/1</Feature>
+        <Feature>MESH 14/4</Feature>
+        <Feature>MESH 16/4</Feature>
+        <Feature>MESH 3/1</Feature>
+        <Feature>MESH 7/1</Feature>
+        <Feature>MESH 18/1</Feature>
+        <Feature>MESH 18/9</Feature>
+        <Feature>MESH 20/2</Feature>
+        <Feature>MESH 21/1</Feature>
+        <Feature>MESH 21/4</Feature>
         <Feature>MESH 11/20</Feature>
         <Feature>MESH 10/5</Feature>
         <Feature>MESH 2/3</Feature>
@@ -752,36 +770,18 @@
         <Feature>MESH 18/7</Feature>
         <Feature>MESH 20/4</Feature>
         <Feature>MESH 21/3</Feature>
-        <Feature>MESH 11/23</Feature>
-        <Feature>MESH 12/12</Feature>
-        <Feature>MESH 18/12</Feature>
-        <Feature>MESH 1a/2</Feature>
-        <Feature>MESH 11/14</Feature>
-        <Feature>MESH 4/13</Feature>
-        <Feature>MESH 11/6</Feature>
-        <Feature>MESH 14/1</Feature>
-        <Feature>MESH 4/11</Feature>
-        <Feature>MESH 7/4</Feature>
-        <Feature>MESH 18/2</Feature>
-        <Feature>MESH 18/6</Feature>
-        <Feature>MESH 4/17</Feature>
-        <Feature>MESH 10/1</Feature>
-        <Feature>MESH 13/1</Feature>
-        <Feature>MESH 14/4</Feature>
-        <Feature>MESH 16/4</Feature>
-        <Feature>MESH 3/1</Feature>
-        <Feature>MESH 7/1</Feature>
-        <Feature>MESH 18/1</Feature>
-        <Feature>MESH 18/9</Feature>
-        <Feature>MESH 20/2</Feature>
-        <Feature>MESH 21/1</Feature>
-        <Feature>MESH 21/4</Feature>
-        <Feature>MESH 11/22</Feature>
-        <Feature>MESH 11/1</Feature>
-        <Feature>MESH 11/4</Feature>
-        <Feature>MESH 12/1</Feature>
-        <Feature>MESH 15/1</Feature>
-        <Feature>MESH 20/3</Feature>
+        <Feature>MESH 18/5</Feature>
+        <Feature>MESH 18/8</Feature>
+        <Feature>MESH 20/1</Feature>
+        <Feature>MESH 11/15</Feature>
+        <Feature>MESH 2/2</Feature>
+        <Feature>MESH 12/3</Feature>
+        <Feature>MESH 12/6</Feature>
+        <Feature>MESH 4/3</Feature>
+        <Feature>MESH 4/8</Feature>
+        <Feature>MESH 5/4</Feature>
+        <Feature>MESH 18/11</Feature>
+        <Feature>MESH 21/2</Feature>
         <Feature>MESH 11/12</Feature>
         <Feature>MESH 4/15</Feature>
         <Feature>MESH 11/18</Feature>
@@ -800,91 +800,95 @@
         <Feature>MESH 18/10</Feature>
         <Feature>MESH 18/3</Feature>
         <Feature>MESH 20/5</Feature>
-        <Feature>MESH 11/11</Feature>
-        <Feature>MESH 4/14</Feature>
-        <Feature>MESH 12/8</Feature>
-        <Feature>MESH 18/13</Feature>
-        <Feature>MESH 2/1</Feature>
-        <Feature>MESH 10/4</Feature>
-        <Feature>MESH 15/4</Feature>
-        <Feature>MESH 15/5</Feature>
-        <Feature>MESH 16/5</Feature>
-        <Feature>MESH 4/7</Feature>
-        <Feature>MESH 7/3</Feature>
-        <Feature>MESH 19/1</Feature>
+        <Feature>MESH 11/22</Feature>
+        <Feature>MESH 11/1</Feature>
+        <Feature>MESH 11/4</Feature>
+        <Feature>MESH 12/1</Feature>
+        <Feature>MESH 15/1</Feature>
+        <Feature>MESH 20/3</Feature>
       </Features>
     </Layer>
     <Layer Layer="LC3">
       <Features>
-        <Feature>LC3 4/2</Feature>
-        <Feature>LC3 2/2</Feature>
-        <Feature>LC3 3/6</Feature>
-        <Feature>LC3 5/5</Feature>
-        <Feature>LC3 2/3</Feature>
-        <Feature>LC3 4/1</Feature>
-        <Feature>LC3 5/4</Feature>
-        <Feature>LC3 1/1</Feature>
         <Feature>LC3 2/1</Feature>
         <Feature>LC3 3/3</Feature>
         <Feature>LC3 5/3</Feature>
         <Feature>LC3 3/5</Feature>
+        <Feature>LC3 3/6</Feature>
+        <Feature>LC3 5/5</Feature>
         <Feature>LC3 6/1</Feature>
         <Feature>LC3 5/1</Feature>
+        <Feature>LC3 2/3</Feature>
+        <Feature>LC3 4/1</Feature>
+        <Feature>LC3 4/2</Feature>
+        <Feature>LC3 2/2</Feature>
+        <Feature>LC3 5/4</Feature>
+        <Feature>LC3 1/1</Feature>
+        <Feature>LC3 5/6</Feature>
+        <Feature>LC3 5/2</Feature>
         <Feature>LC3 6/2</Feature>
         <Feature>LC3 3/1</Feature>
         <Feature>LC3 3/4</Feature>
         <Feature>LC3 0/1</Feature>
         <Feature>LC3 3/2</Feature>
-        <Feature>LC3 5/6</Feature>
-        <Feature>LC3 5/2</Feature>
       </Features>
     </Layer>
     <Layer Layer="AICS">
       <Features>
-        <Feature>AICS 4/1</Feature>
-        <Feature>AICS 4/2</Feature>
         <Feature>AICS 4/3</Feature>
         <Feature>AICS 2/4</Feature>
         <Feature>AICS 3/3</Feature>
         <Feature>AICS 3/1</Feature>
         <Feature>AICS 0/1</Feature>
-        <Feature>AICS 3/4</Feature>
-        <Feature>AICS 2/3</Feature>
-        <Feature>AICS 2/5</Feature>
+        <Feature>AICS 4/1</Feature>
+        <Feature>AICS 4/2</Feature>
         <Feature>AICS 2/2</Feature>
         <Feature>AICS 2/6</Feature>
         <Feature>AICS 2/7</Feature>
-        <Feature>AICS 3/5</Feature>
-        <Feature>AICS 3/2</Feature>
-        <Feature>AICS 2/8</Feature>
         <Feature>AICS 4/4</Feature>
+        <Feature>AICS 0a/1</Feature>
         <Feature>AICS 2/1</Feature>
         <Feature>AICS 4/6</Feature>
         <Feature>AICS 1/2</Feature>
+        <Feature>AICS 3/4</Feature>
+        <Feature>AICS 2/3</Feature>
+        <Feature>AICS 2/5</Feature>
+        <Feature>AICS 3/5</Feature>
+        <Feature>AICS 3/2</Feature>
+        <Feature>AICS 2/8</Feature>
       </Features>
     </Layer>
     <Layer Layer="VOCS">
       <Features>
-        <Feature>VOCS 3/2</Feature>
-        <Feature>VOCS 3/6</Feature>
-        <Feature>VOCS 2/4</Feature>
+        <Feature>VOCS 0/1</Feature>
+        <Feature>VOCS 1/2</Feature>
+        <Feature>VOCS 2/3</Feature>
+        <Feature>VOCS 2/1</Feature>
+        <Feature>VOCS 2/6</Feature>
+        <Feature>VOCS 2/8</Feature>
+        <Feature>VOCS 3/2</Feature>
+        <Feature>VOCS 3/6</Feature>
+        <Feature>VOCS 0a/1</Feature>
+        <Feature>VOCS 2/4</Feature>
         <Feature>VOCS 2/7</Feature>
         <Feature>VOCS 3/1</Feature>
         <Feature>VOCS 2/2</Feature>
         <Feature>VOCS 3/4</Feature>
         <Feature>VOCS 2/5</Feature>
         <Feature>VOCS 3/3</Feature>
-        <Feature>VOCS 1/2</Feature>
-        <Feature>VOCS 2/3</Feature>
-        <Feature>VOCS 2/1</Feature>
-        <Feature>VOCS 2/6</Feature>
-        <Feature>VOCS 2/8</Feature>
-        <Feature>VOCS 0/1</Feature>
       </Features>
     </Layer>
     <Layer Layer="VCS">
       <Features>
+        <Feature>VCS 0/1</Feature>
+        <Feature>VCS 3/5</Feature>
+        <Feature>VCS 4/6</Feature>
+        <Feature>VCS 4/2</Feature>
+        <Feature>VCS 3/3</Feature>
+        <Feature>VCS 1/2</Feature>
+        <Feature>VCS 2/3</Feature>
         <Feature>VCS 4/4</Feature>
+        <Feature>VCS 0a/1</Feature>
         <Feature>VCS 3/6</Feature>
         <Feature>VCS 2/1</Feature>
         <Feature>VCS 2/4</Feature>
@@ -892,25 +896,44 @@
         <Feature>VCS 4/3</Feature>
         <Feature>VCS 3/2</Feature>
         <Feature>VCS 3/1</Feature>
-        <Feature>VCS 0/1</Feature>
-        <Feature>VCS 3/5</Feature>
-        <Feature>VCS 4/6</Feature>
         <Feature>VCS 3/7</Feature>
         <Feature>VCS 3/4</Feature>
         <Feature>VCS 4/1</Feature>
-        <Feature>VCS 3/3</Feature>
-        <Feature>VCS 1/2</Feature>
-        <Feature>VCS 2/3</Feature>
-        <Feature>VCS 4/2</Feature>
       </Features>
     </Layer>
     <Layer Layer="VCP">
       <Features>
+        <Feature>VCP 17/5</Feature>
+        <Feature>VCP 16/11</Feature>
+        <Feature>VCP 18/7</Feature>
+        <Feature>VCP 16/2</Feature>
+        <Feature>VCP 14/8</Feature>
+        <Feature>VCP 16/5</Feature>
+        <Feature>VCP 17/3</Feature>
+        <Feature>VCP 17/8</Feature>
+        <Feature>VCP 17/1</Feature>
+        <Feature>VCP 3/1</Feature>
+        <Feature>VCP 12/8</Feature>
+        <Feature>VCP 16/10</Feature>
+        <Feature>VCP 11/2</Feature>
+        <Feature>VCP 18/3</Feature>
+        <Feature>VCP 14/3</Feature>
+        <Feature>VCP 15/4</Feature>
+        <Feature>VCP 12/7</Feature>
+        <Feature>VCP 6/2</Feature>
+        <Feature>VCP 12/5</Feature>
+        <Feature>VCP 15/5</Feature>
+        <Feature>VCP 16/4</Feature>
+        <Feature>VCP 12/2</Feature>
         <Feature>VCP 14/2</Feature>
         <Feature>VCP 8/1</Feature>
         <Feature>VCP 10/3</Feature>
         <Feature>VCP 12/9</Feature>
         <Feature>VCP 16/13</Feature>
+        <Feature>VCP 15/2</Feature>
+        <Feature>VCP 16/7</Feature>
+        <Feature>VCP 14/5</Feature>
+        <Feature>VCP 14/9</Feature>
         <Feature>VCP 5/4</Feature>
         <Feature>VCP 12/10</Feature>
         <Feature>VCP 17/4</Feature>
@@ -918,16 +941,6 @@
         <Feature>VCP 2/2</Feature>
         <Feature>VCP 16/8</Feature>
         <Feature>VCP 10/2</Feature>
-        <Feature>VCP 13/2</Feature>
-        <Feature>VCP 16/3</Feature>
-        <Feature>VCP 10/1</Feature>
-        <Feature>VCP 6/3</Feature>
-        <Feature>VCP 17/9</Feature>
-        <Feature>VCP 12/12</Feature>
-        <Feature>VCP 12/1</Feature>
-        <Feature>VCP 12/6</Feature>
-        <Feature>VCP 13/3</Feature>
-        <Feature>VCP 16/6</Feature>
         <Feature>VCP 15/1</Feature>
         <Feature>VCP 18/14</Feature>
         <Feature>VCP 5/1</Feature>
@@ -939,6 +952,16 @@
         <Feature>VCP 16/14</Feature>
         <Feature>VCP 16/1</Feature>
         <Feature>VCP 18/4</Feature>
+        <Feature>VCP 13/2</Feature>
+        <Feature>VCP 16/3</Feature>
+        <Feature>VCP 10/1</Feature>
+        <Feature>VCP 6/3</Feature>
+        <Feature>VCP 17/9</Feature>
+        <Feature>VCP 12/12</Feature>
+        <Feature>VCP 12/1</Feature>
+        <Feature>VCP 12/6</Feature>
+        <Feature>VCP 13/3</Feature>
+        <Feature>VCP 16/6</Feature>
         <Feature>VCP 14/7</Feature>
         <Feature>VCP 6/8</Feature>
         <Feature>VCP 17/6</Feature>
@@ -967,48 +990,52 @@
         <Feature>VCP 18/12</Feature>
         <Feature>VCP 17/2</Feature>
         <Feature>VCP 6/13</Feature>
-        <Feature>VCP 17/5</Feature>
-        <Feature>VCP 16/11</Feature>
-        <Feature>VCP 18/7</Feature>
-        <Feature>VCP 16/2</Feature>
-        <Feature>VCP 14/8</Feature>
-        <Feature>VCP 16/5</Feature>
-        <Feature>VCP 17/3</Feature>
-        <Feature>VCP 17/8</Feature>
-        <Feature>VCP 17/1</Feature>
-        <Feature>VCP 3/1</Feature>
-        <Feature>VCP 12/8</Feature>
-        <Feature>VCP 16/10</Feature>
-        <Feature>VCP 11/2</Feature>
-        <Feature>VCP 18/3</Feature>
-        <Feature>VCP 14/3</Feature>
-        <Feature>VCP 15/4</Feature>
-        <Feature>VCP 12/7</Feature>
-        <Feature>VCP 6/2</Feature>
-        <Feature>VCP 12/5</Feature>
-        <Feature>VCP 15/5</Feature>
-        <Feature>VCP 16/4</Feature>
-        <Feature>VCP 12/2</Feature>
-        <Feature>VCP 14/9</Feature>
-        <Feature>VCP 15/2</Feature>
-        <Feature>VCP 16/7</Feature>
-        <Feature>VCP 14/5</Feature>
       </Features>
     </Layer>
     <Layer Layer="MICS">
       <Features>
-        <Feature>MICS 3/2</Feature>
+        <Feature>MICS 2/1</Feature>
+        <Feature>MICS 3/3</Feature>
+        <Feature>MICS 3/1</Feature>
         <Feature>MICS 0/1</Feature>
         <Feature>MICS 3/4</Feature>
+        <Feature>MICS 3/2</Feature>
         <Feature>MICS 3/6</Feature>
         <Feature>MICS 1/2</Feature>
-        <Feature>MICS 3/1</Feature>
-        <Feature>MICS 2/1</Feature>
-        <Feature>MICS 3/3</Feature>
       </Features>
     </Layer>
     <Layer Layer="MICP">
       <Features>
+        <Feature>MICP 15/5</Feature>
+        <Feature>MICP 6/6</Feature>
+        <Feature>MICP 6/13</Feature>
+        <Feature>MICP 13/3</Feature>
+        <Feature>MICP 6/4</Feature>
+        <Feature>MICP 14/2</Feature>
+        <Feature>MICP 14/13</Feature>
+        <Feature>MICP 15/2</Feature>
+        <Feature>MICP 15/7</Feature>
+        <Feature>MICP 6/8</Feature>
+        <Feature>MICP 6/2</Feature>
+        <Feature>MICP 14/3</Feature>
+        <Feature>MICP 16/4</Feature>
+        <Feature>MICP 13/5</Feature>
+        <Feature>MICP 5/2</Feature>
+        <Feature>MICP 16/3</Feature>
+        <Feature>MICP 15/8</Feature>
+        <Feature>MICP 16/5</Feature>
+        <Feature>MICP 14/11</Feature>
+        <Feature>MICP 15/1</Feature>
+        <Feature>MICP 14/7</Feature>
+        <Feature>MICP 6/5</Feature>
+        <Feature>MICP 12/1</Feature>
+        <Feature>MICP 13/2</Feature>
+        <Feature>MICP 16/6</Feature>
+        <Feature>MICP 15/3</Feature>
+        <Feature>MICP 14/14</Feature>
+        <Feature>MICP 3/1</Feature>
+        <Feature>MICP 16/14</Feature>
+        <Feature>MICP 14/12</Feature>
         <Feature>MICP 6/14</Feature>
         <Feature>MICP 1/1</Feature>
         <Feature>MICP 14/10</Feature>
@@ -1020,30 +1047,8 @@
         <Feature>MICP 16/1</Feature>
         <Feature>MICP 13/1</Feature>
         <Feature>MICP 10/2</Feature>
-        <Feature>MICP 6/5</Feature>
-        <Feature>MICP 12/1</Feature>
-        <Feature>MICP 13/2</Feature>
-        <Feature>MICP 16/3</Feature>
-        <Feature>MICP 15/8</Feature>
-        <Feature>MICP 16/5</Feature>
-        <Feature>MICP 14/11</Feature>
-        <Feature>MICP 15/1</Feature>
-        <Feature>MICP 14/7</Feature>
-        <Feature>MICP 3/1</Feature>
-        <Feature>MICP 16/14</Feature>
-        <Feature>MICP 14/12</Feature>
-        <Feature>MICP 15/5</Feature>
-        <Feature>MICP 6/6</Feature>
-        <Feature>MICP 6/13</Feature>
-        <Feature>MICP 13/3</Feature>
-        <Feature>MICP 6/4</Feature>
         <Feature>MICP 8/1</Feature>
         <Feature>MICP 16/13</Feature>
-        <Feature>MICP 14/9</Feature>
-        <Feature>MICP 14/5</Feature>
-        <Feature>MICP 16/7</Feature>
-        <Feature>MICP 6/1</Feature>
-        <Feature>MICP 15/10</Feature>
         <Feature>MICP 13/6</Feature>
         <Feature>MICP 14/6</Feature>
         <Feature>MICP 13/4</Feature>
@@ -1056,41 +1061,35 @@
         <Feature>MICP 12/2</Feature>
         <Feature>MICP 14/1</Feature>
         <Feature>MICP 14/4</Feature>
-        <Feature>MICP 16/6</Feature>
-        <Feature>MICP 15/3</Feature>
-        <Feature>MICP 14/14</Feature>
-        <Feature>MICP 14/2</Feature>
-        <Feature>MICP 14/13</Feature>
-        <Feature>MICP 15/2</Feature>
-        <Feature>MICP 15/7</Feature>
-        <Feature>MICP 6/8</Feature>
-        <Feature>MICP 6/2</Feature>
-        <Feature>MICP 14/3</Feature>
-        <Feature>MICP 16/4</Feature>
-        <Feature>MICP 13/5</Feature>
-        <Feature>MICP 5/2</Feature>
+        <Feature>MICP 14/9</Feature>
+        <Feature>MICP 14/5</Feature>
+        <Feature>MICP 16/7</Feature>
+        <Feature>MICP 6/1</Feature>
+        <Feature>MICP 15/10</Feature>
       </Features>
     </Layer>
     <Layer Layer="MCS">
       <Features>
-        <Feature>MCS 22/7</Feature>
-        <Feature>MCS 22/24</Feature>
-        <Feature>MCS 23/20</Feature>
-        <Feature>MCS 25/3</Feature>
-        <Feature>MCS 23/14</Feature>
-        <Feature>MCS 23/19</Feature>
-        <Feature>MCS 23/4</Feature>
-        <Feature>MCS 23/3</Feature>
-        <Feature>MCS 22/3</Feature>
-        <Feature>MCS 20/1</Feature>
-        <Feature>MCS 22/23</Feature>
-        <Feature>MCS 22/17</Feature>
-        <Feature>MCS 23/13</Feature>
-        <Feature>MCS 21/2</Feature>
         <Feature>MCS 22/12</Feature>
         <Feature>MCS 23/9</Feature>
         <Feature>MCS 22/21</Feature>
+        <Feature>MCS 20a/1</Feature>
         <Feature>MCS 24/3</Feature>
+        <Feature>MCS 23/19</Feature>
+        <Feature>MCS 23/4</Feature>
+        <Feature>MCS 23/3</Feature>
+        <Feature>MCS 25/6</Feature>
+        <Feature>MCS 22/15</Feature>
+        <Feature>MCS 23/15</Feature>
+        <Feature>MCS 22/22</Feature>
+        <Feature>MCS 22/1</Feature>
+        <Feature>MCS 23/5</Feature>
+        <Feature>MCS 23/16</Feature>
+        <Feature>MCS 22/16</Feature>
+        <Feature>MCS 22/2</Feature>
+        <Feature>MCS 25/1</Feature>
+        <Feature>MCS 0b/2</Feature>
+        <Feature>MCS 23/18</Feature>
         <Feature>MCS 23/11</Feature>
         <Feature>MCS 23/17</Feature>
         <Feature>MCS 22/6</Feature>
@@ -1099,6 +1098,27 @@
         <Feature>MCS 22/18</Feature>
         <Feature>MCS 23/2</Feature>
         <Feature>MCS 22/4</Feature>
+        <Feature>MCS 22/3</Feature>
+        <Feature>MCS 20/1</Feature>
+        <Feature>MCS 22/23</Feature>
+        <Feature>MCS 22/17</Feature>
+        <Feature>MCS 23/13</Feature>
+        <Feature>MCS 21/2</Feature>
+        <Feature>MCS 22/7</Feature>
+        <Feature>MCS 22/24</Feature>
+        <Feature>MCS 23/20</Feature>
+        <Feature>MCS 25/3</Feature>
+        <Feature>MCS 23/14</Feature>
+        <Feature>MCS 23/21</Feature>
+        <Feature>MCS 22/26</Feature>
+        <Feature>MCS 22/11</Feature>
+        <Feature>MCS 23/8</Feature>
+        <Feature>MCS 23/12</Feature>
+        <Feature>MCS 23/6</Feature>
+        <Feature>MCS 24/4</Feature>
+        <Feature>MCS 22/9</Feature>
+        <Feature>MCS 22/8</Feature>
+        <Feature>MCS 22/14</Feature>
         <Feature>MCS 23/7</Feature>
         <Feature>MCS 24/1</Feature>
         <Feature>MCS 22/19</Feature>
@@ -1110,43 +1130,19 @@
         <Feature>MCS 22/13</Feature>
         <Feature>MCS 25/2</Feature>
         <Feature>MCS 22/25</Feature>
-        <Feature>MCS 23/21</Feature>
-        <Feature>MCS 22/26</Feature>
-        <Feature>MCS 22/11</Feature>
-        <Feature>MCS 23/8</Feature>
-        <Feature>MCS 23/12</Feature>
-        <Feature>MCS 23/6</Feature>
-        <Feature>MCS 24/4</Feature>
-        <Feature>MCS 22/9</Feature>
-        <Feature>MCS 22/8</Feature>
-        <Feature>MCS 22/14</Feature>
-        <Feature>MCS 25/6</Feature>
-        <Feature>MCS 22/15</Feature>
-        <Feature>MCS 23/15</Feature>
-        <Feature>MCS 22/22</Feature>
-        <Feature>MCS 22/1</Feature>
-        <Feature>MCS 23/5</Feature>
-        <Feature>MCS 23/16</Feature>
-        <Feature>MCS 22/16</Feature>
-        <Feature>MCS 22/2</Feature>
-        <Feature>MCS 25/1</Feature>
-        <Feature>MCS 0b/2</Feature>
-        <Feature>MCS 23/18</Feature>
       </Features>
     </Layer>
     <Layer Layer="MCP">
       <Features>
-        <Feature>MCP 16/4</Feature>
-        <Feature>MCP 6/5</Feature>
-        <Feature>MCP 18/4</Feature>
-        <Feature>MCP 18/3</Feature>
-        <Feature>MCP 6/13</Feature>
-        <Feature>MCP 16/10</Feature>
-        <Feature>MCP 17/20</Feature>
-        <Feature>MCP 17/15</Feature>
-        <Feature>MCP 16/2</Feature>
-        <Feature>MCP 10/1</Feature>
-        <Feature>MCP 16/15</Feature>
+        <Feature>MCP 21/1</Feature>
+        <Feature>MCP 2/2</Feature>
+        <Feature>MCP 17/7</Feature>
+        <Feature>MCP 3/1</Feature>
+        <Feature>MCP 17/4</Feature>
+        <Feature>MCP 17/3</Feature>
+        <Feature>MCP 16/9</Feature>
+        <Feature>MCP 6/14</Feature>
+        <Feature>MCP 13/2</Feature>
         <Feature>MCP 18/5</Feature>
         <Feature>MCP 5/4</Feature>
         <Feature>MCP 16/12</Feature>
@@ -1160,24 +1156,15 @@
         <Feature>MCP 5/3</Feature>
         <Feature>MCP 17/16</Feature>
         <Feature>MCP 16/18</Feature>
-        <Feature>MCP 16/19</Feature>
-        <Feature>MCP 21/3</Feature>
-        <Feature>MCP 8/1</Feature>
-        <Feature>MCP 17/17</Feature>
-        <Feature>MCP 17/18</Feature>
-        <Feature>MCP 16/6</Feature>
-        <Feature>MCP 10/2</Feature>
-        <Feature>MCP 6/4</Feature>
-        <Feature>MCP 1/2</Feature>
-        <Feature>MCP 21/1</Feature>
-        <Feature>MCP 2/2</Feature>
-        <Feature>MCP 17/7</Feature>
-        <Feature>MCP 3/1</Feature>
-        <Feature>MCP 17/4</Feature>
-        <Feature>MCP 17/3</Feature>
-        <Feature>MCP 16/9</Feature>
-        <Feature>MCP 6/14</Feature>
-        <Feature>MCP 13/2</Feature>
+        <Feature>MCP 17/13</Feature>
+        <Feature>MCP 17/19</Feature>
+        <Feature>MCP 17/1</Feature>
+        <Feature>MCP 6/6</Feature>
+        <Feature>MCP 17/11</Feature>
+        <Feature>MCP 17/9</Feature>
+        <Feature>MCP 17/14</Feature>
+        <Feature>MCP 16/20</Feature>
+        <Feature>MCP 1/1</Feature>
         <Feature>MCP 9/2</Feature>
         <Feature>MCP 21/2</Feature>
         <Feature>MCP 20/1</Feature>
@@ -1190,14 +1177,26 @@
         <Feature>MCP 16/5</Feature>
         <Feature>MCP 13/3</Feature>
         <Feature>MCP 18/8</Feature>
-        <Feature>MCP 18/2</Feature>
-        <Feature>MCP 16/22</Feature>
-        <Feature>MCP 6/2</Feature>
-        <Feature>MCP 18/7</Feature>
-        <Feature>MCP 17/12</Feature>
-        <Feature>MCP 16/14</Feature>
-        <Feature>MCP 16/13</Feature>
-        <Feature>MCP 17/8</Feature>
+        <Feature>MCP 16/19</Feature>
+        <Feature>MCP 21/3</Feature>
+        <Feature>MCP 8/1</Feature>
+        <Feature>MCP 17/17</Feature>
+        <Feature>MCP 17/18</Feature>
+        <Feature>MCP 16/6</Feature>
+        <Feature>MCP 10/2</Feature>
+        <Feature>MCP 6/4</Feature>
+        <Feature>MCP 1/2</Feature>
+        <Feature>MCP 16/4</Feature>
+        <Feature>MCP 6/5</Feature>
+        <Feature>MCP 18/4</Feature>
+        <Feature>MCP 18/3</Feature>
+        <Feature>MCP 6/13</Feature>
+        <Feature>MCP 16/10</Feature>
+        <Feature>MCP 17/20</Feature>
+        <Feature>MCP 17/15</Feature>
+        <Feature>MCP 16/2</Feature>
+        <Feature>MCP 10/1</Feature>
+        <Feature>MCP 16/15</Feature>
         <Feature>MCP 6/3</Feature>
         <Feature>MCP 16/8</Feature>
         <Feature>MCP 11/1</Feature>
@@ -1207,29 +1206,33 @@
         <Feature>MCP 18/14</Feature>
         <Feature>MCP 16/16</Feature>
         <Feature>MCP 5/2</Feature>
-        <Feature>MCP 17/13</Feature>
-        <Feature>MCP 17/19</Feature>
-        <Feature>MCP 17/1</Feature>
-        <Feature>MCP 6/6</Feature>
-        <Feature>MCP 17/11</Feature>
-        <Feature>MCP 17/9</Feature>
-        <Feature>MCP 17/14</Feature>
-        <Feature>MCP 16/20</Feature>
-        <Feature>MCP 1/1</Feature>
+        <Feature>MCP 18/2</Feature>
+        <Feature>MCP 16/22</Feature>
+        <Feature>MCP 6/2</Feature>
+        <Feature>MCP 18/7</Feature>
+        <Feature>MCP 17/12</Feature>
+        <Feature>MCP 16/14</Feature>
+        <Feature>MCP 16/13</Feature>
+        <Feature>MCP 17/8</Feature>
       </Features>
     </Layer>
     <Layer Layer="TBS">
       <Features>
-        <Feature>TBS 22/3</Feature>
-        <Feature>TBS 2/13</Feature>
-        <Feature>TBS 4/5</Feature>
-        <Feature>TBS 24/3</Feature>
-        <Feature>TBS 22/12</Feature>
-        <Feature>TBS 22/14</Feature>
-        <Feature>TBS 2/25</Feature>
-        <Feature>TBS 2/10</Feature>
-        <Feature>TBS 22/22</Feature>
-        <Feature>TBS 2/8</Feature>
+        <Feature>TBS 3/1</Feature>
+        <Feature>TBS 22/17</Feature>
+        <Feature>TBS 22/15</Feature>
+        <Feature>TBS 2/16</Feature>
+        <Feature>TBS 3/2</Feature>
+        <Feature>TBS 3/6</Feature>
+        <Feature>TBS 22/13</Feature>
+        <Feature>TBS 2/3</Feature>
+        <Feature>TBS 22/16</Feature>
+        <Feature>TBS 2/17</Feature>
+        <Feature>TBS 4/4</Feature>
+        <Feature>TBS 2/20</Feature>
+        <Feature>TBS 4/3</Feature>
+        <Feature>TBS 23/2</Feature>
+        <Feature>TBS 0b/1</Feature>
         <Feature>TBS 2/15</Feature>
         <Feature>TBS 23/1</Feature>
         <Feature>TBS 20/1</Feature>
@@ -1242,6 +1245,26 @@
         <Feature>TBS 3/5</Feature>
         <Feature>TBS 22/20</Feature>
         <Feature>TBS 24/5</Feature>
+        <Feature>TBS 2/7</Feature>
+        <Feature>TBS 23/6</Feature>
+        <Feature>TBS 2/19</Feature>
+        <Feature>TBS 22/18</Feature>
+        <Feature>TBS 22/25</Feature>
+        <Feature>TBS 22/21</Feature>
+        <Feature>TBS 2/24</Feature>
+        <Feature>TBS 22/23</Feature>
+        <Feature>TBS 24/4</Feature>
+        <Feature>TBS 22/9</Feature>
+        <Feature>TBS 22/3</Feature>
+        <Feature>TBS 2/13</Feature>
+        <Feature>TBS 4/5</Feature>
+        <Feature>TBS 24/3</Feature>
+        <Feature>TBS 22/12</Feature>
+        <Feature>TBS 22/14</Feature>
+        <Feature>TBS 2/25</Feature>
+        <Feature>TBS 2/10</Feature>
+        <Feature>TBS 22/22</Feature>
+        <Feature>TBS 2/8</Feature>
         <Feature>TBS 22/7</Feature>
         <Feature>TBS 22/24</Feature>
         <Feature>TBS 2/2</Feature>
@@ -1275,60 +1298,10 @@
         <Feature>TBS 1/2</Feature>
         <Feature>TBS 24/7</Feature>
         <Feature>TBS 22/11</Feature>
-        <Feature>TBS 3/1</Feature>
-        <Feature>TBS 22/17</Feature>
-        <Feature>TBS 22/15</Feature>
-        <Feature>TBS 2/16</Feature>
-        <Feature>TBS 3/2</Feature>
-        <Feature>TBS 3/6</Feature>
-        <Feature>TBS 22/13</Feature>
-        <Feature>TBS 2/3</Feature>
-        <Feature>TBS 22/16</Feature>
-        <Feature>TBS 2/17</Feature>
-        <Feature>TBS 4/4</Feature>
-        <Feature>TBS 2/20</Feature>
-        <Feature>TBS 4/3</Feature>
-        <Feature>TBS 23/2</Feature>
-        <Feature>TBS 0b/1</Feature>
-        <Feature>TBS 2/7</Feature>
-        <Feature>TBS 23/6</Feature>
-        <Feature>TBS 2/19</Feature>
-        <Feature>TBS 22/18</Feature>
-        <Feature>TBS 22/25</Feature>
-        <Feature>TBS 22/21</Feature>
-        <Feature>TBS 2/24</Feature>
-        <Feature>TBS 22/23</Feature>
-        <Feature>TBS 24/4</Feature>
-        <Feature>TBS 22/9</Feature>
       </Features>
     </Layer>
     <Layer Layer="CCP">
       <Features>
-        <Feature>CCP 14/10</Feature>
-        <Feature>CCP 13/15</Feature>
-        <Feature>CCP 14/2</Feature>
-        <Feature>CCP 5/2</Feature>
-        <Feature>CCP 15/6</Feature>
-        <Feature>CCP 11/8</Feature>
-        <Feature>CCP 14/9</Feature>
-        <Feature>CCP 11/15</Feature>
-        <Feature>CCP 13/12</Feature>
-        <Feature>CCP 11/1</Feature>
-        <Feature>CCP 1/1</Feature>
-        <Feature>CCP 6/1</Feature>
-        <Feature>CCP 13/7</Feature>
-        <Feature>CCP 6/5</Feature>
-        <Feature>CCP 12/1</Feature>
-        <Feature>CCP 12/13</Feature>
-        <Feature>CCP 12/17</Feature>
-        <Feature>CCP 11/2</Feature>
-        <Feature>CCP 6/6</Feature>
-        <Feature>CCP 14/13</Feature>
-        <Feature>CCP 5/3</Feature>
-        <Feature>CCP 13/6</Feature>
-        <Feature>CCP 13/2</Feature>
-        <Feature>CCP 14/15</Feature>
-        <Feature>CCP 14/12</Feature>
         <Feature>CCP 14/7</Feature>
         <Feature>CCP 14/20</Feature>
         <Feature>CCP 12/5</Feature>
@@ -1345,6 +1318,15 @@
         <Feature>CCP 15/4</Feature>
         <Feature>CCP 2/2</Feature>
         <Feature>CCP 11/16</Feature>
+        <Feature>CCP 14/8</Feature>
+        <Feature>CCP 6/2</Feature>
+        <Feature>CCP 14/3</Feature>
+        <Feature>CCP 12/3</Feature>
+        <Feature>CCP 12/19</Feature>
+        <Feature>CCP 14/14</Feature>
+        <Feature>CCP 13/11</Feature>
+        <Feature>CCP 12/20</Feature>
+        <Feature>CCP 11/6</Feature>
         <Feature>CCP 6/4</Feature>
         <Feature>CCP 14/18</Feature>
         <Feature>CCP 15/5</Feature>
@@ -1359,28 +1341,6 @@
         <Feature>CCP 15/8</Feature>
         <Feature>CCP 14/1</Feature>
         <Feature>CCP 11/13</Feature>
-        <Feature>CCP 14/8</Feature>
-        <Feature>CCP 6/2</Feature>
-        <Feature>CCP 14/3</Feature>
-        <Feature>CCP 12/3</Feature>
-        <Feature>CCP 12/19</Feature>
-        <Feature>CCP 14/14</Feature>
-        <Feature>CCP 13/11</Feature>
-        <Feature>CCP 12/20</Feature>
-        <Feature>CCP 11/6</Feature>
-        <Feature>CCP 12/7</Feature>
-        <Feature>CCP 12/11</Feature>
-        <Feature>CCP 15/3</Feature>
-        <Feature>CCP 10/2</Feature>
-        <Feature>CCP 12/8</Feature>
-        <Feature>CCP 12/22</Feature>
-        <Feature>CCP 14/16</Feature>
-        <Feature>CCP 12/4</Feature>
-        <Feature>CCP 12/15</Feature>
-        <Feature>CCP 14/17</Feature>
-        <Feature>CCP 11/7</Feature>
-        <Feature>CCP 13/4</Feature>
-        <Feature>CCP 8/1</Feature>
         <Feature>CCP 13/14</Feature>
         <Feature>CCP 11/9</Feature>
         <Feature>CCP 12/21</Feature>
@@ -1393,6 +1353,21 @@
         <Feature>CCP 11/12</Feature>
         <Feature>CCP 11/3</Feature>
         <Feature>CCP 13/1</Feature>
+        <Feature>CCP 14/10</Feature>
+        <Feature>CCP 13/15</Feature>
+        <Feature>CCP 14/2</Feature>
+        <Feature>CCP 5/2</Feature>
+        <Feature>CCP 15/6</Feature>
+        <Feature>CCP 11/8</Feature>
+        <Feature>CCP 14/9</Feature>
+        <Feature>CCP 11/15</Feature>
+        <Feature>CCP 13/12</Feature>
+        <Feature>CCP 11/1</Feature>
+        <Feature>CCP 1/1</Feature>
+        <Feature>CCP 6/1</Feature>
+        <Feature>CCP 13/7</Feature>
+        <Feature>CCP 6/5</Feature>
+        <Feature>CCP 12/1</Feature>
         <Feature>CCP 12/6</Feature>
         <Feature>CCP 13/5</Feature>
         <Feature>CCP 13/10</Feature>
@@ -1407,6 +1382,29 @@
         <Feature>CCP 11/10</Feature>
         <Feature>CCP 13/9</Feature>
         <Feature>CCP 14/5</Feature>
+        <Feature>CCP 12/13</Feature>
+        <Feature>CCP 12/17</Feature>
+        <Feature>CCP 11/2</Feature>
+        <Feature>CCP 6/6</Feature>
+        <Feature>CCP 14/13</Feature>
+        <Feature>CCP 5/3</Feature>
+        <Feature>CCP 13/6</Feature>
+        <Feature>CCP 13/2</Feature>
+        <Feature>CCP 14/15</Feature>
+        <Feature>CCP 14/12</Feature>
+        <Feature>CCP 12/7</Feature>
+        <Feature>CCP 12/11</Feature>
+        <Feature>CCP 15/3</Feature>
+        <Feature>CCP 10/2</Feature>
+        <Feature>CCP 12/8</Feature>
+        <Feature>CCP 12/22</Feature>
+        <Feature>CCP 14/16</Feature>
+        <Feature>CCP 12/4</Feature>
+        <Feature>CCP 12/15</Feature>
+        <Feature>CCP 14/17</Feature>
+        <Feature>CCP 11/7</Feature>
+        <Feature>CCP 13/4</Feature>
+        <Feature>CCP 8/1</Feature>
       </Features>
     </Layer>
     <Layer Layer="CSIS">
@@ -1417,21 +1415,19 @@
         <Feature>CSIS 2/6</Feature>
         <Feature>CSIS 0a/2</Feature>
         <Feature>CSIS 3/1</Feature>
-        <Feature>CSIS 2/4</Feature>
         <Feature>CSIS 1/2</Feature>
         <Feature>CSIS 3/3</Feature>
-        <Feature>CSIS 3/4</Feature>
-        <Feature>CSIS 3/2</Feature>
         <Feature>CSIS 2/5</Feature>
         <Feature>CSIS 2/3</Feature>
-      </Features>
-    </Layer>
+        <Feature>CSIS 5/1</Feature>
+        <Feature>CSIS 3/4</Feature>
+        <Feature>CSIS 0/1</Feature>
+        <Feature>CSIS 3/2</Feature>
+        <Feature>CSIS 2/4</Feature>
+      </Features>
+    </Layer>
     <Layer Layer="CSIP">
       <Features>
-        <Feature>CSIP 3/1</Feature>
-        <Feature>CSIP 8/1</Feature>
-        <Feature>CSIP 13/1</Feature>
-        <Feature>CSIP 6/6</Feature>
         <Feature>CSIP 12/5</Feature>
         <Feature>CSIP 14/16</Feature>
         <Feature>CSIP 12/1</Feature>
@@ -1439,31 +1435,34 @@
         <Feature>CSIP 6/4</Feature>
         <Feature>CSIP 11/1</Feature>
         <Feature>CSIP 11/4</Feature>
-        <Feature>CSIP 6/3</Feature>
-        <Feature>CSIP 13/5</Feature>
-        <Feature>CSIP 14/8</Feature>
-        <Feature>CSIP 13/2</Feature>
-        <Feature>CSIP 13/7</Feature>
         <Feature>CSIP 13/10</Feature>
         <Feature>CSIP 5/1</Feature>
         <Feature>CSIP 4/2</Feature>
         <Feature>CSIP 9/2</Feature>
         <Feature>CSIP 14/4</Feature>
-        <Feature>CSIP 12/2</Feature>
-        <Feature>CSIP 6/15</Feature>
-        <Feature>CSIP 6/9</Feature>
-        <Feature>CSIP 6/1</Feature>
-        <Feature>CSIP 5/5</Feature>
-        <Feature>CSIP 6/16</Feature>
-        <Feature>CSIP 6/8</Feature>
+        <Feature>CSIP 6/3</Feature>
+        <Feature>CSIP 13/5</Feature>
+        <Feature>CSIP 14/8</Feature>
+        <Feature>CSIP 13/2</Feature>
         <Feature>CSIP 14/2</Feature>
         <Feature>CSIP 13/6</Feature>
         <Feature>CSIP 5/2</Feature>
         <Feature>CSIP 14/15</Feature>
+        <Feature>CSIP 8/1</Feature>
         <Feature>CSIP 14/7</Feature>
         <Feature>CSIP 14/5</Feature>
         <Feature>CSIP 13/9</Feature>
         <Feature>CSIP 13/4</Feature>
+        <Feature>CSIP 13/1</Feature>
+        <Feature>CSIP 6/6</Feature>
+        <Feature>CSIP 14/6</Feature>
+        <Feature>CSIP 12/4</Feature>
+        <Feature>CSIP 1/1</Feature>
+        <Feature>CSIP 6/7</Feature>
+        <Feature>CSIP 1/2</Feature>
+        <Feature>CSIP 11/2</Feature>
+        <Feature>CSIP 13/7</Feature>
+        <Feature>CSIP 14/3</Feature>
         <Feature>CSIP 13/11</Feature>
         <Feature>CSIP 2/2</Feature>
         <Feature>CSIP 14/9</Feature>
@@ -1471,26 +1470,41 @@
         <Feature>CSIP 6/2</Feature>
         <Feature>CSIP 13/8</Feature>
         <Feature>CSIP 10/1</Feature>
+        <Feature>CSIP 13/12</Feature>
         <Feature>CSIP 12/3</Feature>
         <Feature>CSIP 13/3</Feature>
-        <Feature>CSIP 14/6</Feature>
-        <Feature>CSIP 12/4</Feature>
-        <Feature>CSIP 1/1</Feature>
-        <Feature>CSIP 6/7</Feature>
-        <Feature>CSIP 1/2</Feature>
-        <Feature>CSIP 11/2</Feature>
-        <Feature>CSIP 14/3</Feature>
+        <Feature>CSIP 3/1</Feature>
+        <Feature>CSIP 12/2</Feature>
+        <Feature>CSIP 6/15</Feature>
+        <Feature>CSIP 6/9</Feature>
+        <Feature>CSIP 6/1</Feature>
+        <Feature>CSIP 5/5</Feature>
+        <Feature>CSIP 6/16</Feature>
+        <Feature>CSIP 6/8</Feature>
       </Features>
     </Layer>
     <Layer Layer="PACS">
       <Features>
-        <Feature>PACS 4/4</Feature>
-        <Feature>PACS 3/2</Feature>
+        <Feature>PACS 4/9</Feature>
+        <Feature>PACS 4/10</Feature>
+        <Feature>PACS 6/4</Feature>
+        <Feature>PACS 6/3</Feature>
+        <Feature>PACS 4/6</Feature>
+        <Feature>PACS 4/2</Feature>
+        <Feature>PACS 3/3</Feature>
+        <Feature>PACS 6/1</Feature>
+        <Feature>PACS 4/8</Feature>
+        <Feature>PACS 6/7</Feature>
+        <Feature>PACS 3/6</Feature>
         <Feature>PACS 4/12</Feature>
+        <Feature>PACS 0/1</Feature>
         <Feature>PACS 6/2</Feature>
         <Feature>PACS 3/5</Feature>
         <Feature>PACS 4/16</Feature>
         <Feature>PACS 6/5</Feature>
+        <Feature>PACS 5/1</Feature>
+        <Feature>PACS 4/4</Feature>
+        <Feature>PACS 3/2</Feature>
         <Feature>PACS 4/15</Feature>
         <Feature>PACS 4/1</Feature>
         <Feature>PACS 4/13</Feature>
@@ -1503,144 +1517,71 @@
         <Feature>PACS 4/3</Feature>
         <Feature>PACS 3/1</Feature>
         <Feature>PACS 4/14</Feature>
-        <Feature>PACS 4/9</Feature>
-        <Feature>PACS 4/10</Feature>
-        <Feature>PACS 6/4</Feature>
-        <Feature>PACS 4/8</Feature>
-        <Feature>PACS 6/7</Feature>
-        <Feature>PACS 3/6</Feature>
-        <Feature>PACS 6/3</Feature>
-        <Feature>PACS 4/6</Feature>
-        <Feature>PACS 4/2</Feature>
-        <Feature>PACS 3/3</Feature>
-        <Feature>PACS 6/1</Feature>
-        <Feature>PACS 5/1</Feature>
       </Features>
     </Layer>
     <Layer Layer="ASCS">
       <Features>
-        <Feature>ASCS 9/3</Feature>
-        <Feature>ASCS 7/1</Feature>
-        <Feature>ASCS 0/1</Feature>
         <Feature>ASCS 9/2</Feature>
         <Feature>ASCS 9/9</Feature>
         <Feature>ASCS 3/1</Feature>
         <Feature>ASCS 5/1</Feature>
         <Feature>ASCS 9/4</Feature>
-        <Feature>ASCS 5/3</Feature>
-        <Feature>ASCS 6/6</Feature>
-        <Feature>ASCS 5/2</Feature>
-        <Feature>ASCS 6/7</Feature>
-        <Feature>ASCS 7/4</Feature>
-        <Feature>ASCS 9/7</Feature>
-        <Feature>ASCS 9/1</Feature>
-        <Feature>ASCS 8/2</Feature>
         <Feature>ASCS 6/2</Feature>
         <Feature>ASCS 8/1</Feature>
         <Feature>ASCS 6/1</Feature>
         <Feature>ASCS 6/9</Feature>
         <Feature>ASCS 4/1</Feature>
+        <Feature>ASCS 5/3</Feature>
+        <Feature>ASCS 6/6</Feature>
+        <Feature>ASCS 5/2</Feature>
+        <Feature>ASCS 9/3</Feature>
+        <Feature>ASCS 7/1</Feature>
+        <Feature>ASCS 0/1</Feature>
         <Feature>ASCS 6/3</Feature>
         <Feature>ASCS 7/2</Feature>
         <Feature>ASCS 6/8</Feature>
+        <Feature>ASCS 1/1</Feature>
+        <Feature>ASCS 9/6</Feature>
+        <Feature>ASCS 6/4</Feature>
+        <Feature>ASCS 6/7</Feature>
+        <Feature>ASCS 7/4</Feature>
+        <Feature>ASCS 9/7</Feature>
+        <Feature>ASCS 9/1</Feature>
+        <Feature>ASCS 8/2</Feature>
         <Feature>ASCS 7/3</Feature>
         <Feature>ASCS 9/5</Feature>
         <Feature>ASCS 7/5</Feature>
         <Feature>ASCS 6/5</Feature>
         <Feature>ASCS 2/2</Feature>
-        <Feature>ASCS 9/6</Feature>
-        <Feature>ASCS 6/4</Feature>
       </Features>
     </Layer>
     <Layer Layer="BASS">
       <Features>
-        <Feature>BASS 5/1</Feature>
-        <Feature>BASS 4/5</Feature>
-        <Feature>BASS 5/2</Feature>
-        <Feature>BASS 5/6</Feature>
-        <Feature>BASS 3/5</Feature>
-        <Feature>BASS 4/1</Feature>
-        <Feature>BASS 3/2</Feature>
         <Feature>BASS 3/4</Feature>
         <Feature>BASS 2/2</Feature>
         <Feature>BASS 4/4</Feature>
+        <Feature>BASS 3/2a</Feature>
+        <Feature>BASS 5/3</Feature>
+        <Feature>BASS 1/1</Feature>
         <Feature>BASS 5/5</Feature>
         <Feature>BASS 5/4</Feature>
-        <Feature>BASS 5/3</Feature>
-        <Feature>BASS 5/8</Feature>
         <Feature>BASS 4/6</Feature>
         <Feature>BASS 4/2</Feature>
         <Feature>BASS 0/1</Feature>
         <Feature>BASS 3/1</Feature>
+        <Feature>BASS 5/1</Feature>
+        <Feature>BASS 4/5</Feature>
         <Feature>BASS 4/3</Feature>
+        <Feature>BASS 5/2</Feature>
+        <Feature>BASS 5/6</Feature>
+        <Feature>BASS 3/5</Feature>
+        <Feature>BASS 4/1</Feature>
+        <Feature>BASS 3/2</Feature>
+        <Feature>BASS 5/8</Feature>
       </Features>
     </Layer>
     <Layer Layer="BAP">
       <Features>
-        <Feature>BAP 4/1</Feature>
-        <Feature>BAP 26/1</Feature>
-        <Feature>BAP 49/1</Feature>
-        <Feature>BAP 62/1</Feature>
-        <Feature>BAP 77/1</Feature>
-        <Feature>BAP 83/1</Feature>
-        <Feature>BAP 44/13</Feature>
-        <Feature>BAP 10/1</Feature>
-        <Feature>BAP 89/13</Feature>
-        <Feature>BAP 68/11</Feature>
-        <Feature>BAP 9a/6</Feature>
-        <Feature>BAP 21/9</Feature>
-        <Feature>BAP 88/3</Feature>
-        <Feature>BAP 1/4</Feature>
-        <Feature>BAP 51/4</Feature>
-        <Feature>BAP 7/7</Feature>
-        <Feature>BAP 21/12</Feature>
-        <Feature>BAP 40/2</Feature>
-        <Feature>BAP 73/9</Feature>
-        <Feature>BAP 21/8</Feature>
-        <Feature>BAP 29/1</Feature>
-        <Feature>BAP 21/11</Feature>
-        <Feature>BAP 36/6</Feature>
-        <Feature>BAP 60/1</Feature>
-        <Feature>BAP 39/7</Feature>
-        <Feature>BAP 76/3</Feature>
-        <Feature>BAP 21/4</Feature>
-        <Feature>BAP 92/7</Feature>
-        <Feature>BAP 16/6</Feature>
-        <Feature>BAP 36/11</Feature>
-        <Feature>BAP 45/9</Feature>
-        <Feature>BAP 55/1</Feature>
-        <Feature>BAP 16/16</Feature>
-        <Feature>BAP 44/10</Feature>
-        <Feature>BAP 55/15</Feature>
-        <Feature>BAP 65/3</Feature>
-        <Feature>BAP 76/4</Feature>
-        <Feature>BAP 39/13</Feature>
-        <Feature>BAP 16/7</Feature>
-        <Feature>BAP 37/4</Feature>
-        <Feature>BAP 22/3</Feature>
-        <Feature>BAP 59/1</Feature>
-        <Feature>BAP 92/3</Feature>
-        <Feature>BAP 59/10</Feature>
-        <Feature>BAP 80/10</Feature>
-        <Feature>BAP 34/5</Feature>
-        <Feature>BAP 60/2</Feature>
-        <Feature>BAP 37/11</Feature>
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+        <Feature>BAP 16/10</Feature>
+        <Feature>BAP 46/3</Feature>
+        <Feature>BAP 14/5</Feature>
+        <Feature>BAP 85/4</Feature>
+        <Feature>BAP 36/14</Feature>
+        <Feature>BAP 83/1</Feature>
+        <Feature>BAP 8/1</Feature>
+        <Feature>BAP 33/2</Feature>
+        <Feature>BAP 69/7</Feature>
+        <Feature>BAP 57/1</Feature>
+        <Feature>BAP 68/3</Feature>
+        <Feature>BAP 70/3</Feature>
+        <Feature>BAP 61/6</Feature>
         <Feature>BAP 23/6</Feature>
         <Feature>BAP 17/8</Feature>
         <Feature>BAP 13/15</Feature>
@@ -2203,6 +1924,107 @@
         <Feature>BAP 68/14</Feature>
         <Feature>BAP 33a/6</Feature>
         <Feature>BAP 34/1</Feature>
+        <Feature>BAP 13/17</Feature>
+        <Feature>BAP 61/4</Feature>
+        <Feature>BAP 41/10</Feature>
+        <Feature>BAP 56/3</Feature>
+        <Feature>BAP 15/6</Feature>
+        <Feature>BAP 17/16</Feature>
+        <Feature>BAP 3/1</Feature>
+        <Feature>BAP 15/7</Feature>
+        <Feature>BAP 56/15</Feature>
+        <Feature>BAP 9a/5</Feature>
+        <Feature>BAP 14/14</Feature>
+        <Feature>BAP 37/8</Feature>
+        <Feature>BAP 41/5</Feature>
+        <Feature>BAP 68/9</Feature>
+        <Feature>BAP 16/2</Feature>
+        <Feature>BAP 89/4</Feature>
+        <Feature>BAP 40/3</Feature>
+        <Feature>BAP 69/3</Feature>
+        <Feature>BAP 61/2</Feature>
+        <Feature>BAP 17/3</Feature>
+        <Feature>BAP 13/9</Feature>
+        <Feature>BAP 15/1</Feature>
+        <Feature>BAP 38/10</Feature>
+        <Feature>BAP 10/4</Feature>
+        <Feature>BAP 9a/8</Feature>
+        <Feature>BAP 70/13</Feature>
+        <Feature>BAP 67/2</Feature>
+        <Feature>BAP 59/2</Feature>
+        <Feature>BAP 55/9</Feature>
+        <Feature>BAP 59/7</Feature>
+        <Feature>BAP 36/15</Feature>
+        <Feature>BAP 22/10</Feature>
+        <Feature>BAP 56/13</Feature>
+        <Feature>BAP 12/8</Feature>
+        <Feature>BAP 33/5</Feature>
+        <Feature>BAP 15/10</Feature>
+        <Feature>BAP 68/1</Feature>
+        <Feature>BAP 59/11</Feature>
+        <Feature>BAP 74/7</Feature>
+        <Feature>BAP 40/11</Feature>
+        <Feature>BAP 45/1</Feature>
+        <Feature>BAP 68/12</Feature>
+        <Feature>BAP 69/6</Feature>
+        <Feature>BAP 54/10</Feature>
+        <Feature>BAP 23/2</Feature>
+        <Feature>BAP 9a/7</Feature>
+        <Feature>BAP 38/1</Feature>
+        <Feature>BAP 5/4</Feature>
+        <Feature>BAP 55/13</Feature>
+        <Feature>BAP 13/3</Feature>
+        <Feature>BAP 42/1</Feature>
+        <Feature>BAP 9/5</Feature>
+        <Feature>BAP 31/4</Feature>
+        <Feature>BAP 38/15</Feature>
+        <Feature>BAP 13/4</Feature>
+        <Feature>BAP 41/2</Feature>
+        <Feature>BAP 17/11</Feature>
+        <Feature>BAP 35/1</Feature>
+        <Feature>BAP 56/4</Feature>
+        <Feature>BAP 49/1</Feature>
+        <Feature>BAP 70/14</Feature>
+        <Feature>BAP 44/6</Feature>
+        <Feature>BAP 9/7</Feature>
+        <Feature>BAP 29/2</Feature>
+        <Feature>BAP 80/16</Feature>
+        <Feature>BAP 68/2</Feature>
+        <Feature>BAP 21/10</Feature>
+        <Feature>BAP 90/3</Feature>
+        <Feature>BAP 89/8</Feature>
+        <Feature>BAP 45/12</Feature>
+        <Feature>BAP 52/2</Feature>
+        <Feature>BAP 70/15</Feature>
+        <Feature>BAP 19/1</Feature>
+        <Feature>BAP 59/5</Feature>
+        <Feature>BAP 70/2</Feature>
+        <Feature>BAP 44/15</Feature>
+        <Feature>BAP 72/2</Feature>
+        <Feature>BAP 14/12</Feature>
+        <Feature>BAP 73/11</Feature>
+        <Feature>BAP 54/6</Feature>
+        <Feature>BAP 10/3</Feature>
+        <Feature>BAP 45/14</Feature>
+        <Feature>BAP 80/22</Feature>
+        <Feature>BAP 54/8</Feature>
+        <Feature>BAP 31/7</Feature>
+        <Feature>BAP 88/1</Feature>
+        <Feature>BAP 36/9</Feature>
+        <Feature>BAP 17/7</Feature>
+        <Feature>BAP 22/6</Feature>
+        <Feature>BAP 68/4</Feature>
+        <Feature>BAP 67/1</Feature>
+        <Feature>BAP 38/12</Feature>
+        <Feature>BAP 4/1</Feature>
+        <Feature>BAP 70/4</Feature>
+        <Feature>BAP 58/1</Feature>
+        <Feature>BAP 73/1</Feature>
+        <Feature>BAP 82/3</Feature>
+        <Feature>BAP 55/7</Feature>
+        <Feature>BAP 51/6</Feature>
+        <Feature>BAP 17/4</Feature>
+        <Feature>BAP 18/1</Feature>
         <Feature>BAP 54/15</Feature>
         <Feature>BAP 16/12</Feature>
         <Feature>BAP 92/4</Feature>
@@ -2238,6 +2060,187 @@
         <Feature>BAP 70/10</Feature>
         <Feature>BAP 79/2</Feature>
         <Feature>BAP 56/7</Feature>
+        <Feature>BAP 7/8</Feature>
+        <Feature>BAP 93/4</Feature>
+        <Feature>BAP 14/13</Feature>
+        <Feature>BAP 23/10</Feature>
+        <Feature>BAP 10/5</Feature>
+        <Feature>BAP 69/16</Feature>
+        <Feature>BAP 14/10</Feature>
+        <Feature>BAP 39/10</Feature>
+        <Feature>BAP 37/1</Feature>
+        <Feature>BAP 17/12</Feature>
+        <Feature>BAP 55/5</Feature>
+        <Feature>BAP 46/6</Feature>
+        <Feature>BAP 30/3</Feature>
+        <Feature>BAP 36/12</Feature>
+        <Feature>BAP 36/17</Feature>
+        <Feature>BAP 16/14</Feature>
+        <Feature>BAP 51/1</Feature>
+        <Feature>BAP 56/1</Feature>
+        <Feature>BAP 44/8</Feature>
+        <Feature>BAP 22/4</Feature>
+        <Feature>BAP 32/7</Feature>
+        <Feature>BAP 31/5</Feature>
+        <Feature>BAP 58/3</Feature>
+        <Feature>BAP 41/4</Feature>
+        <Feature>BAP 9/1</Feature>
+        <Feature>BAP 9/3</Feature>
+        <Feature>BAP 33/6</Feature>
+        <Feature>BAP 15/2</Feature>
+        <Feature>BAP 52/1</Feature>
+        <Feature>BAP 56/6</Feature>
+        <Feature>BAP 12/5</Feature>
+        <Feature>BAP 12/11</Feature>
+        <Feature>BAP 56/16</Feature>
+        <Feature>BAP 14/2</Feature>
+        <Feature>BAP 13/2</Feature>
+        <Feature>BAP 15/14</Feature>
+        <Feature>BAP 54/13</Feature>
+        <Feature>BAP 37/9</Feature>
+        <Feature>BAP 36/2</Feature>
+        <Feature>BAP 92/5</Feature>
+        <Feature>BAP 32/9</Feature>
+        <Feature>BAP 54/7</Feature>
+        <Feature>BAP 40/8</Feature>
+        <Feature>BAP 86/1</Feature>
+        <Feature>BAP 41/6</Feature>
+        <Feature>BAP 9a/4</Feature>
+        <Feature>BAP 53/2</Feature>
+        <Feature>BAP 80/13</Feature>
+        <Feature>BAP 56/8</Feature>
+        <Feature>BAP 93/3</Feature>
+        <Feature>BAP 80/6</Feature>
+        <Feature>BAP 41/1</Feature>
+        <Feature>BAP 20/7</Feature>
+        <Feature>BAP 33a/3</Feature>
+        <Feature>BAP 14/4</Feature>
+        <Feature>BAP 27/5</Feature>
+        <Feature>BAP 34/3</Feature>
+        <Feature>BAP 51/5</Feature>
+        <Feature>BAP 7/5</Feature>
+        <Feature>BAP 46/5</Feature>
+        <Feature>BAP 13/6</Feature>
+        <Feature>BAP 25/1</Feature>
+        <Feature>BAP 93/1</Feature>
+        <Feature>BAP 96/1</Feature>
+        <Feature>BAP 48/3</Feature>
+        <Feature>BAP 40/16</Feature>
+        <Feature>BAP 33/7</Feature>
+        <Feature>BAP 56/12</Feature>
+        <Feature>BAP 92/2</Feature>
+        <Feature>BAP 60/3</Feature>
+        <Feature>BAP 70/1</Feature>
+        <Feature>BAP 38/2</Feature>
+        <Feature>BAP 16/11</Feature>
+        <Feature>BAP 80/7</Feature>
+        <Feature>BAP 86/2</Feature>
+        <Feature>BAP 82/4</Feature>
+        <Feature>BAP 14/3</Feature>
+        <Feature>BAP 70/7</Feature>
+        <Feature>BAP 68/10</Feature>
+        <Feature>BAP 69/1</Feature>
+        <Feature>BAP 45/5</Feature>
+        <Feature>BAP 68/15</Feature>
+        <Feature>BAP 1/1</Feature>
+        <Feature>BAP 39/8</Feature>
+        <Feature>BAP 41/15</Feature>
+        <Feature>BAP 44/2</Feature>
+        <Feature>BAP 40/7</Feature>
+        <Feature>BAP 36/3</Feature>
+        <Feature>BAP 89/6</Feature>
+        <Feature>BAP 39/15</Feature>
+        <Feature>BAP 39/1</Feature>
+        <Feature>BAP 46/15</Feature>
+        <Feature>BAP 17/14</Feature>
+        <Feature>BAP 41/7</Feature>
+        <Feature>BAP 36/7</Feature>
+        <Feature>BAP 53/1</Feature>
+        <Feature>BAP 54/12</Feature>
+        <Feature>BAP 89/5</Feature>
+        <Feature>BAP 46/2</Feature>
+        <Feature>BAP 55/6</Feature>
+        <Feature>BAP 90/21</Feature>
+        <Feature>BAP 51/7</Feature>
+        <Feature>BAP 14/15</Feature>
+        <Feature>BAP 1/5</Feature>
+        <Feature>BAP 36/1</Feature>
+        <Feature>BAP 25/2</Feature>
+        <Feature>BAP 50/2</Feature>
+        <Feature>BAP 7/10</Feature>
+        <Feature>BAP 45/2</Feature>
+        <Feature>BAP 12/16</Feature>
+        <Feature>BAP 41/3</Feature>
+        <Feature>BAP 17/2</Feature>
+        <Feature>BAP 6/4</Feature>
+        <Feature>BAP 87/2</Feature>
+        <Feature>BAP 90/16</Feature>
+        <Feature>BAP 69/10</Feature>
+        <Feature>BAP 56/5</Feature>
+        <Feature>BAP 16/3</Feature>
+        <Feature>BAP 17/9</Feature>
+        <Feature>BAP 8/2</Feature>
+        <Feature>BAP 15/8</Feature>
+        <Feature>BAP 11/3</Feature>
+        <Feature>BAP 87/1</Feature>
+        <Feature>BAP 70/12</Feature>
+        <Feature>BAP 36/8</Feature>
+        <Feature>BAP 14/9</Feature>
+        <Feature>BAP 45/11</Feature>
+        <Feature>BAP 74/6</Feature>
+        <Feature>BAP 33/1</Feature>
+        <Feature>BAP 69/15</Feature>
+        <Feature>BAP 36/13</Feature>
+        <Feature>BAP 89/1</Feature>
+        <Feature>BAP 48/1</Feature>
+        <Feature>BAP 55/12</Feature>
+        <Feature>BAP 9/8</Feature>
+        <Feature>BAP 12/17</Feature>
+        <Feature>BAP 28/2</Feature>
+        <Feature>BAP 13/10</Feature>
+        <Feature>BAP 16/9</Feature>
+        <Feature>BAP 37/16</Feature>
+        <Feature>BAP 39/11</Feature>
+        <Feature>BAP 80/15</Feature>
+        <Feature>BAP 48/2</Feature>
+        <Feature>BAP 44/7</Feature>
+        <Feature>BAP 15/16</Feature>
+        <Feature>BAP 54/9</Feature>
+        <Feature>BAP 58/2</Feature>
+        <Feature>BAP 6/2</Feature>
+        <Feature>BAP 46/14</Feature>
+        <Feature>BAP 95/1</Feature>
+        <Feature>BAP 88/6</Feature>
+        <Feature>BAP 68/13</Feature>
+        <Feature>BAP 90/5</Feature>
+        <Feature>BAP 92/1</Feature>
+        <Feature>BAP 70/16</Feature>
+        <Feature>BAP 73/8</Feature>
+        <Feature>BAP 74/1</Feature>
+        <Feature>BAP 20/8</Feature>
+        <Feature>BAP 16/1</Feature>
+        <Feature>BAP 7/6</Feature>
+        <Feature>BAP 20/6</Feature>
+        <Feature>BAP 95/6</Feature>
+        <Feature>BAP 21/5</Feature>
+        <Feature>BAP 90/11</Feature>
+        <Feature>BAP 37/3</Feature>
+        <Feature>BAP 73/10</Feature>
+        <Feature>BAP 74/10</Feature>
+        <Feature>BAP 21/3</Feature>
+        <Feature>BAP 38/3</Feature>
+        <Feature>BAP 51/3</Feature>
+        <Feature>BAP 40/13</Feature>
+        <Feature>BAP 68/16</Feature>
+        <Feature>BAP 15/9</Feature>
+        <Feature>BAP 14/1</Feature>
+        <Feature>BAP 10/2</Feature>
+        <Feature>BAP 36/16</Feature>
+        <Feature>BAP 40/10</Feature>
+        <Feature>BAP 44/3</Feature>
+        <Feature>BAP 90/8</Feature>
+        <Feature>BAP 55/3</Feature>
+        <Feature>BAP 90/7</Feature>
       </Features>
     </Layer>
     <Layer Layer="CAS">
@@ -2250,35 +2253,6 @@
     </Layer>
     <Layer Layer="CAP">
       <Features>
-        <Feature>CAP 26/5</Feature>
-        <Feature>CAP 20/3</Feature>
-        <Feature>CAP 11/5</Feature>
-        <Feature>CAP 26/7</Feature>
-        <Feature>CAP 22/4</Feature>
-        <Feature>CAP 16/4</Feature>
-        <Feature>CAP 6/8</Feature>
-        <Feature>CAP 20/9</Feature>
-        <Feature>CAP 20/6</Feature>
-        <Feature>CAP 7/5</Feature>
-        <Feature>CAP 17/1</Feature>
-        <Feature>CAP 18/2</Feature>
-        <Feature>CAP 6/1</Feature>
-        <Feature>CAP 6/7</Feature>
-        <Feature>CAP 7/6</Feature>
-        <Feature>CAP 22/8</Feature>
-        <Feature>CAP 13/1</Feature>
-        <Feature>CAP 32/1</Feature>
-        <Feature>CAP 31/3</Feature>
-        <Feature>CAP 31/1</Feature>
-        <Feature>CAP 22/9</Feature>
-        <Feature>CAP 11/2</Feature>
-        <Feature>CAP 28/6</Feature>
-        <Feature>CAP 6/3</Feature>
-        <Feature>CAP 22/10</Feature>
-        <Feature>CAP 21/1</Feature>
-        <Feature>CAP 27/4</Feature>
-        <Feature>CAP 11/12</Feature>
-        <Feature>CAP 16/3</Feature>
         <Feature>CAP 16/5</Feature>
         <Feature>CAP 1/3</Feature>
         <Feature>CAP 26/4</Feature>
@@ -2289,6 +2263,18 @@
         <Feature>CAP 16/1</Feature>
         <Feature>CAP 22/3</Feature>
         <Feature>CAP 19/4</Feature>
+        <Feature>CAP 22/1</Feature>
+        <Feature>CAP 26/6</Feature>
+        <Feature>CAP 28/8</Feature>
+        <Feature>CAP 20/2</Feature>
+        <Feature>CAP 13/2</Feature>
+        <Feature>CAP 6/6</Feature>
+        <Feature>CAP 15/1</Feature>
+        <Feature>CAP 6/5</Feature>
+        <Feature>CAP 6a/1</Feature>
+        <Feature>CAP 20/4</Feature>
+        <Feature>CAP 22/6</Feature>
+        <Feature>CAP 11/1</Feature>
         <Feature>CAP 28/11</Feature>
         <Feature>CAP 7/1</Feature>
         <Feature>CAP 19/1</Feature>
@@ -2296,6 +2282,7 @@
         <Feature>CAP 21/3</Feature>
         <Feature>CAP 24/1</Feature>
         <Feature>CAP 18/1</Feature>
+        <Feature>CAP 25/1</Feature>
         <Feature>CAP 1/2</Feature>
         <Feature>CAP 22/11</Feature>
         <Feature>CAP 33/1</Feature>
@@ -2309,30 +2296,6 @@
         <Feature>CAP 7/7</Feature>
         <Feature>CAP 11/9</Feature>
         <Feature>CAP 6/2</Feature>
-        <Feature>CAP 22/1</Feature>
-        <Feature>CAP 26/6</Feature>
-        <Feature>CAP 28/8</Feature>
-        <Feature>CAP 20/2</Feature>
-        <Feature>CAP 13/2</Feature>
-        <Feature>CAP 6/6</Feature>
-        <Feature>CAP 6/5</Feature>
-        <Feature>CAP 6a/1</Feature>
-        <Feature>CAP 20/4</Feature>
-        <Feature>CAP 22/6</Feature>
-        <Feature>CAP 11/1</Feature>
-        <Feature>CAP 11/11</Feature>
-        <Feature>CAP 1/1</Feature>
-        <Feature>CAP 12/1</Feature>
-        <Feature>CAP 4/1</Feature>
-        <Feature>CAP 28/9</Feature>
-        <Feature>CAP 7/8</Feature>
-        <Feature>CAP 6/4</Feature>
-        <Feature>CAP 3/1</Feature>
-        <Feature>CAP 20/1</Feature>
-        <Feature>CAP 28/7</Feature>
-        <Feature>CAP 11/3</Feature>
-        <Feature>CAP 22/5</Feature>
-        <Feature>CAP 27/5</Feature>
         <Feature>CAP 2/2</Feature>
         <Feature>CAP 16/2</Feature>
         <Feature>CAP 19/2</Feature>
@@ -2344,6 +2307,17 @@
         <Feature>CAP 16/6</Feature>
         <Feature>CAP 28/10</Feature>
         <Feature>CAP 11/4</Feature>
+        <Feature>CAP 26/5</Feature>
+        <Feature>CAP 20/3</Feature>
+        <Feature>CAP 11/5</Feature>
+        <Feature>CAP 26/7</Feature>
+        <Feature>CAP 22/4</Feature>
+        <Feature>CAP 5/1</Feature>
+        <Feature>CAP 16/4</Feature>
+        <Feature>CAP 6/8</Feature>
+        <Feature>CAP 20/6</Feature>
+        <Feature>CAP 7/5</Feature>
+        <Feature>CAP 17/1</Feature>
         <Feature>CAP 8/3</Feature>
         <Feature>CAP 31/4</Feature>
         <Feature>CAP 17/2</Feature>
@@ -2359,62 +2333,112 @@
         <Feature>CAP 7/2</Feature>
         <Feature>CAP 8/1</Feature>
         <Feature>CAP 8/4</Feature>
+        <Feature>CAP 18/2</Feature>
+        <Feature>CAP 6/1</Feature>
+        <Feature>CAP 6/7</Feature>
+        <Feature>CAP 7/6</Feature>
+        <Feature>CAP 22/8</Feature>
+        <Feature>CAP 13/1</Feature>
+        <Feature>CAP 32/1</Feature>
+        <Feature>CAP 31/3</Feature>
+        <Feature>CAP 31/1</Feature>
+        <Feature>CAP 22/9</Feature>
+        <Feature>CAP 11/2</Feature>
+        <Feature>CAP 28/6</Feature>
+        <Feature>CAP 6/3</Feature>
+        <Feature>CAP 22/10</Feature>
+        <Feature>CAP 21/1</Feature>
+        <Feature>CAP 27/4</Feature>
+        <Feature>CAP 11/12</Feature>
+        <Feature>CAP 16/3</Feature>
+        <Feature>CAP 11/11</Feature>
+        <Feature>CAP 1/1</Feature>
+        <Feature>CAP 12/1</Feature>
+        <Feature>CAP 4/1</Feature>
+        <Feature>CAP 28/9</Feature>
+        <Feature>CAP 7/8</Feature>
+        <Feature>CAP 6/4</Feature>
+        <Feature>CAP 3/1</Feature>
+        <Feature>CAP 20/1</Feature>
+        <Feature>CAP 28/7</Feature>
+        <Feature>CAP 11/3</Feature>
+        <Feature>CAP 22/5</Feature>
+        <Feature>CAP 27/5</Feature>
       </Features>
     </Layer>
     <Layer Layer="HAS">
       <Features>
-        <Feature>HAS 4/7</Feature>
-        <Feature>HAS 2/2</Feature>
-        <Feature>HAS 3/4</Feature>
-        <Feature>HAS 3/9</Feature>
-        <Feature>HAS 3/13</Feature>
-        <Feature>HAS 3/8</Feature>
-        <Feature>HAS 3/3</Feature>
+        <Feature>HAS 4/8</Feature>
+        <Feature>HAS 4/3</Feature>
+        <Feature>HAS 3/7</Feature>
+        <Feature>HAS 3/11</Feature>
+        <Feature>HAS 3/2</Feature>
         <Feature>HAS 4/2</Feature>
         <Feature>HAS 5/5</Feature>
         <Feature>HAS 3/6</Feature>
         <Feature>HAS 0/1</Feature>
+        <Feature>HAS 4/10</Feature>
+        <Feature>HAS 3/12</Feature>
+        <Feature>HAS 3/5</Feature>
+        <Feature>HAS 4/5</Feature>
+        <Feature>HAS 3/1</Feature>
+        <Feature>HAS 3/14</Feature>
         <Feature>HAS 4/4</Feature>
+        <Feature>HAS 1/1</Feature>
         <Feature>HAS 4/9</Feature>
         <Feature>HAS 3/1a</Feature>
+        <Feature>HAS 4/7</Feature>
+        <Feature>HAS 2/2</Feature>
+        <Feature>HAS 3/4</Feature>
+        <Feature>HAS 3/9</Feature>
+        <Feature>HAS 3/13</Feature>
+        <Feature>HAS 3/8</Feature>
+        <Feature>HAS 3/3</Feature>
         <Feature>HAS 5/4</Feature>
         <Feature>HAS 5/1</Feature>
         <Feature>HAS 4/1</Feature>
         <Feature>HAS 5/6</Feature>
         <Feature>HAS 3/10</Feature>
-        <Feature>HAS 4/8</Feature>
-        <Feature>HAS 4/3</Feature>
-        <Feature>HAS 3/7</Feature>
-        <Feature>HAS 3/11</Feature>
-        <Feature>HAS 3/2</Feature>
-        <Feature>HAS 3/14</Feature>
         <Feature>HAS 5/2</Feature>
         <Feature>HAS 5/3</Feature>
         <Feature>HAS 4/6</Feature>
-        <Feature>HAS 4/10</Feature>
-        <Feature>HAS 3/12</Feature>
-        <Feature>HAS 3/5</Feature>
-        <Feature>HAS 4/5</Feature>
-        <Feature>HAS 3/1</Feature>
       </Features>
     </Layer>
     <Layer Layer="HAP">
       <Features>
-        <Feature>HAP 13/6</Feature>
-        <Feature>HAP 18/1</Feature>
-        <Feature>HAP 1/1</Feature>
-        <Feature>HAP 19/2</Feature>
+        <Feature>HAP 12/3</Feature>
+        <Feature>HAP 24/3</Feature>
+        <Feature>HAP 19/1</Feature>
+        <Feature>HAP 24/4</Feature>
+        <Feature>HAP 14/1</Feature>
+        <Feature>HAP 26/1</Feature>
+        <Feature>HAP 16/1</Feature>
+        <Feature>HAP 24/1</Feature>
+        <Feature>HAP 2/2</Feature>
         <Feature>HAP 12/7</Feature>
         <Feature>HAP 13/7</Feature>
         <Feature>HAP 12/6</Feature>
+        <Feature>HAP 11/1</Feature>
         <Feature>HAP 46/1</Feature>
+        <Feature>HAP 12/5</Feature>
+        <Feature>HAP 14/3</Feature>
+        <Feature>HAP 13/2</Feature>
+        <Feature>HAP 16/2</Feature>
+        <Feature>HAP 13/3</Feature>
+        <Feature>HAP 12/4</Feature>
         <Feature>HAP 10/1</Feature>
         <Feature>HAP 92/1</Feature>
         <Feature>HAP 51/1</Feature>
         <Feature>HAP 43/2</Feature>
         <Feature>HAP 40/1</Feature>
+        <Feature>HAP 91/1</Feature>
         <Feature>HAP 17/1</Feature>
         <Feature>HAP 43/1</Feature>
+        <Feature>HAP 41/1</Feature>
+        <Feature>HAP 13/6</Feature>
+        <Feature>HAP 18/1</Feature>
+        <Feature>HAP 1/1</Feature>
+        <Feature>HAP 19/2</Feature>
         <Feature>HAP 50/1</Feature>
         <Feature>HAP 24/5</Feature>
         <Feature>HAP 13/4</Feature>
@@ -2427,56 +2451,72 @@
         <Feature>HAP 12/2</Feature>
         <Feature>HAP 12/1</Feature>
         <Feature>HAP 1/4</Feature>
-        <Feature>HAP 26/1</Feature>
-        <Feature>HAP 16/1</Feature>
-        <Feature>HAP 24/1</Feature>
-        <Feature>HAP 2/2</Feature>
-        <Feature>HAP 12/5</Feature>
-        <Feature>HAP 14/3</Feature>
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-        <Feature>HAP 16/2</Feature>
-        <Feature>HAP 13/3</Feature>
-        <Feature>HAP 12/4</Feature>
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         <Feature>HAP 13/1</Feature>
         <Feature>HAP 43/4</Feature>
         <Feature>HAP 24/6</Feature>
         <Feature>HAP 13/5</Feature>
-        <Feature>HAP 12/3</Feature>
-        <Feature>HAP 24/3</Feature>
-        <Feature>HAP 19/1</Feature>
-        <Feature>HAP 24/4</Feature>
-        <Feature>HAP 14/1</Feature>
       </Features>
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-        <Feature>TMAP 95/5</Feature>
-        <Feature>TMAP 114/4</Feature>
-        <Feature>TMAP 57/3</Feature>
-        <Feature>TMAP 79/2</Feature>
-        <Feature>TMAP 116/4</Feature>
-        <Feature>TMAP 78/1</Feature>
-        <Feature>TMAP 55/3</Feature>
-        <Feature>TMAP 113/1</Feature>
-        <Feature>TMAP 98/3</Feature>
-        <Feature>TMAP 17/6</Feature>
-        <Feature>TMAP 115/5</Feature>
-        <Feature>TMAP 55/5</Feature>
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-        <Feature>TMAP 76/6</Feature>
-        <Feature>TMAP 110/1</Feature>
-        <Feature>TMAP 14/1</Feature>
-        <Feature>TMAP 16/1</Feature>
-        <Feature>TMAP 56/7</Feature>
-        <Feature>TMAP 54/3</Feature>
-        <Feature>TMAP 117/1</Feature>
-        <Feature>TMAP 78/2</Feature>
-        <Feature>TMAP 56/10</Feature>
-        <Feature>TMAP 96/14</Feature>
-        <Feature>TMAP 3/1</Feature>
-        <Feature>TMAP 100/1</Feature>
-        <Feature>TMAP 76/1</Feature>
+    </Layer>
+    <Layer Layer="TMAP">
+      <Features>
+        <Feature>TMAP 79/1</Feature>
+        <Feature>TMAP 116/5</Feature>
+        <Feature>TMAP 96/12</Feature>
+        <Feature>TMAP 94/1</Feature>
+        <Feature>TMAP 116/1</Feature>
+        <Feature>TMAP 1/4</Feature>
+        <Feature>TMAP 97/1</Feature>
+        <Feature>TMAP 15/4</Feature>
+        <Feature>TMAP 115/1</Feature>
+        <Feature>TMAP 56/6</Feature>
+        <Feature>TMAP 78/3</Feature>
+        <Feature>TMAP 56/4</Feature>
+        <Feature>TMAP 116/15</Feature>
+        <Feature>TMAP 74/3</Feature>
+        <Feature>TMAP 14/6</Feature>
+        <Feature>TMAP 54/1</Feature>
+        <Feature>TMAP 76/2</Feature>
+        <Feature>TMAP 156/1</Feature>
+        <Feature>TMAP 96/3</Feature>
+        <Feature>TMAP 114/3</Feature>
+        <Feature>TMAP 16/2</Feature>
+        <Feature>TMAP 116/14</Feature>
+        <Feature>TMAP 56/15</Feature>
+        <Feature>TMAP 92/2</Feature>
+        <Feature>TMAP 99/1</Feature>
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+        <Feature>TMAP 56/2</Feature>
+        <Feature>TMAP 74/1</Feature>
+        <Feature>TMAP 151/5</Feature>
+        <Feature>TMAP 151/4</Feature>
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+        <Feature>TMAP 94/2</Feature>
+        <Feature>TMAP 116/12</Feature>
+        <Feature>TMAP 95/3</Feature>
+        <Feature>TMAP 95/8</Feature>
+        <Feature>TMAP 2/2</Feature>
+        <Feature>TMAP 112/1</Feature>
+        <Feature>TMAP 54/2</Feature>
+        <Feature>TMAP 100/2</Feature>
+        <Feature>TMAP 75/1</Feature>
+        <Feature>TMAP 56/3</Feature>
+        <Feature>TMAP 94/4</Feature>
+        <Feature>TMAP 12/1</Feature>
+        <Feature>TMAP 116/16</Feature>
+        <Feature>TMAP 95/2</Feature>
+        <Feature>TMAP 12/3</Feature>
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+        <Feature>TMAP 74/5</Feature>
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+        <Feature>TMAP 96/4</Feature>
+        <Feature>TMAP 56/11</Feature>
+        <Feature>TMAP 94/3</Feature>
+        <Feature>TMAP 75/6</Feature>
+        <Feature>TMAP 74/4</Feature>
+        <Feature>TMAP 2/2a</Feature>
+        <Feature>TMAP 151/2</Feature>
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         <Feature>TMAP 76/3</Feature>
         <Feature>TMAP 1/2</Feature>
@@ -2499,13 +2539,60 @@
         <Feature>TMAP 115/8</Feature>
         <Feature>TMAP 96/9</Feature>
         <Feature>TMAP 115/7</Feature>
+        <Feature>TMAP 74/8</Feature>
         <Feature>TMAP 96/5</Feature>
         <Feature>TMAP 17/3</Feature>
-        <Feature>TMAP 55/2</Feature>
-        <Feature>TMAP 16/4</Feature>
-        <Feature>TMAP 95/6</Feature>
-        <Feature>TMAP 74/6</Feature>
+        <Feature>TMAP 52/2</Feature>
+        <Feature>TMAP 1/7</Feature>
+        <Feature>TMAP 56/12</Feature>
+        <Feature>TMAP 153/6</Feature>
+        <Feature>TMAP 56/1</Feature>
+        <Feature>TMAP 56/5</Feature>
+        <Feature>TMAP 118/2</Feature>
+        <Feature>TMAP 16/5</Feature>
+        <Feature>TMAP 150/1</Feature>
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+        <Feature>TMAP 116/6</Feature>
+        <Feature>TMAP 153/5</Feature>
+        <Feature>TMAP 19/3</Feature>
+        <Feature>TMAP 57/1</Feature>
+        <Feature>TMAP 19/2</Feature>
+        <Feature>TMAP 151/6</Feature>
+        <Feature>TMAP 91/1</Feature>
+        <Feature>TMAP 116/2</Feature>
+        <Feature>TMAP 55/8</Feature>
+        <Feature>TMAP 97/2</Feature>
+        <Feature>TMAP 96/6</Feature>
+        <Feature>TMAP 51/1</Feature>
+        <Feature>TMAP 1/5</Feature>
+        <Feature>TMAP 115/2</Feature>
+        <Feature>TMAP 115/6</Feature>
+        <Feature>TMAP 114/2</Feature>
+        <Feature>TMAP 121/1</Feature>
+        <Feature>TMAP 112/2</Feature>
+        <Feature>TMAP 55/1</Feature>
+        <Feature>TMAP 95/5</Feature>
+        <Feature>TMAP 114/4</Feature>
+        <Feature>TMAP 57/3</Feature>
+        <Feature>TMAP 79/2</Feature>
+        <Feature>TMAP 116/4</Feature>
+        <Feature>TMAP 78/1</Feature>
+        <Feature>TMAP 55/3</Feature>
+        <Feature>TMAP 113/1</Feature>
+        <Feature>TMAP 98/3</Feature>
+        <Feature>TMAP 17/6</Feature>
+        <Feature>TMAP 115/5</Feature>
+        <Feature>TMAP 55/5</Feature>
+        <Feature>TMAP 116/7</Feature>
+        <Feature>TMAP 76/6</Feature>
+        <Feature>TMAP 110/1</Feature>
+        <Feature>TMAP 14/1</Feature>
+        <Feature>TMAP 16/1</Feature>
+        <Feature>TMAP 56/7</Feature>
+        <Feature>TMAP 54/3</Feature>
+        <Feature>TMAP 117/1</Feature>
         <Feature>TMAP 96/15</Feature>
+        <Feature>TMAP 114/5</Feature>
         <Feature>TMAP 76/5</Feature>
         <Feature>TMAP 99/2</Feature>
         <Feature>TMAP 96/7</Feature>
@@ -2517,6 +2604,7 @@
         <Feature>TMAP 118/3</Feature>
         <Feature>TMAP 17/5</Feature>
         <Feature>TMAP 96/1</Feature>
+        <Feature>TMAP 11/1</Feature>
         <Feature>TMAP 75/2</Feature>
         <Feature>TMAP 14/2</Feature>
         <Feature>TMAP 15/3</Feature>
@@ -2528,10 +2616,21 @@
         <Feature>TMAP 56/8</Feature>
         <Feature>TMAP 50/1</Feature>
         <Feature>TMAP 14/4</Feature>
+        <Feature>TMAP 78/2</Feature>
+        <Feature>TMAP 56/10</Feature>
+        <Feature>TMAP 96/14</Feature>
+        <Feature>TMAP 3/1</Feature>
+        <Feature>TMAP 100/1</Feature>
+        <Feature>TMAP 76/1</Feature>
+        <Feature>TMAP 55/2</Feature>
+        <Feature>TMAP 16/4</Feature>
+        <Feature>TMAP 95/6</Feature>
+        <Feature>TMAP 74/6</Feature>
         <Feature>TMAP 18/2</Feature>
         <Feature>TMAP 56/14</Feature>
         <Feature>TMAP 1/1</Feature>
         <Feature>TMAP 115/3</Feature>
+        <Feature>TMAP 54/5</Feature>
         <Feature>TMAP 1/8</Feature>
         <Feature>TMAP 116/11</Feature>
         <Feature>TMAP 70/1</Feature>
@@ -2551,6 +2650,7 @@
         <Feature>TMAP 98/1</Feature>
         <Feature>TMAP 153/2</Feature>
         <Feature>TMAP 92/1</Feature>
+        <Feature>TMAP 111/1</Feature>
         <Feature>TMAP 57/2</Feature>
         <Feature>TMAP 19/1</Feature>
         <Feature>TMAP 96/16</Feature>
@@ -2560,8 +2660,12 @@
         <Feature>TMAP 10/1</Feature>
         <Feature>TMAP 153/1</Feature>
         <Feature>TMAP 17/7</Feature>
+        <Feature>TMAP 94/6</Feature>
+        <Feature>TMAP 71/1</Feature>
+        <Feature>TMAP 14/8</Feature>
         <Feature>TMAP 151/1</Feature>
         <Feature>TMAP 115/4</Feature>
+        <Feature>TMAP 74/7</Feature>
         <Feature>TMAP 131/1</Feature>
         <Feature>TMAP 154/1</Feature>
         <Feature>TMAP 118/1</Feature>
@@ -2576,124 +2680,10 @@
         <Feature>TMAP 96/11</Feature>
         <Feature>TMAP 12/2</Feature>
         <Feature>TMAP 55/7</Feature>
-        <Feature>TMAP 79/1</Feature>
-        <Feature>TMAP 116/5</Feature>
-        <Feature>TMAP 96/12</Feature>
-        <Feature>TMAP 94/1</Feature>
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-        <Feature>TMAP 1/4</Feature>
-        <Feature>TMAP 97/1</Feature>
-        <Feature>TMAP 15/4</Feature>
-        <Feature>TMAP 115/1</Feature>
-        <Feature>TMAP 56/6</Feature>
-        <Feature>TMAP 78/3</Feature>
-        <Feature>TMAP 56/4</Feature>
-        <Feature>TMAP 116/15</Feature>
-        <Feature>TMAP 74/3</Feature>
-        <Feature>TMAP 14/6</Feature>
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-        <Feature>TMAP 76/2</Feature>
-        <Feature>TMAP 156/1</Feature>
-        <Feature>TMAP 96/3</Feature>
-        <Feature>TMAP 114/3</Feature>
-        <Feature>TMAP 16/2</Feature>
-        <Feature>TMAP 116/14</Feature>
-        <Feature>TMAP 56/15</Feature>
-        <Feature>TMAP 92/2</Feature>
-        <Feature>TMAP 99/1</Feature>
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-        <Feature>TMAP 56/2</Feature>
-        <Feature>TMAP 74/1</Feature>
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-        <Feature>TMAP 94/5</Feature>
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-        <Feature>TMAP 116/12</Feature>
-        <Feature>TMAP 95/3</Feature>
-        <Feature>TMAP 95/8</Feature>
-        <Feature>TMAP 2/2</Feature>
-        <Feature>TMAP 112/1</Feature>
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-        <Feature>TMAP 100/2</Feature>
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-        <Feature>TMAP 95/2</Feature>
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-        <Feature>TMAP 52/2</Feature>
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-        <Feature>TMAP 153/6</Feature>
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-        <Feature>TMAP 114/2</Feature>
-        <Feature>TMAP 121/1</Feature>
-        <Feature>TMAP 112/2</Feature>
-        <Feature>TMAP 55/1</Feature>
       </Features>
     </Layer>
     <Layer Layer="PBP">
       <Features>
-        <Feature>PBP 10/1</Feature>
-        <Feature>PBP 8/9</Feature>
-        <Feature>PBP 12/2</Feature>
-        <Feature>PBP 14/11</Feature>
-        <Feature>PBP 6/6</Feature>
-        <Feature>PBP 8/10</Feature>
-        <Feature>PBP 11/2</Feature>
-        <Feature>PBP 13/2</Feature>
-        <Feature>PBP 2/2</Feature>
-        <Feature>PBP 8/8</Feature>
-        <Feature>PBP 6/1</Feature>
-        <Feature>PBP 8/3</Feature>
-        <Feature>PBP 6/8</Feature>
-        <Feature>PBP 6/4</Feature>
-        <Feature>PBP 7/2</Feature>
-        <Feature>PBP 6/7</Feature>
-        <Feature>PBP 7/1</Feature>
-        <Feature>PBP 14/7</Feature>
-        <Feature>PBP 13/4</Feature>
-        <Feature>PBP 14/4</Feature>
-        <Feature>PBP 5/2</Feature>
-        <Feature>PBP 14/9</Feature>
-        <Feature>PBP 13/1</Feature>
-        <Feature>PBP 6/2</Feature>
-        <Feature>PBP 9/1</Feature>
-        <Feature>PBP 3/1</Feature>
-        <Feature>PBP 14/10</Feature>
-        <Feature>PBP 12/1</Feature>
-        <Feature>PBP 1/1</Feature>
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-        <Feature>PBP 14/5</Feature>
         <Feature>PBP 7/4</Feature>
         <Feature>PBP 8/7</Feature>
         <Feature>PBP 8/6</Feature>
@@ -2704,6 +2694,13 @@
         <Feature>PBP 5/1</Feature>
         <Feature>PBP 8/12</Feature>
         <Feature>PBP 4/1</Feature>
+        <Feature>PBP 8/10</Feature>
+        <Feature>PBP 11/2</Feature>
+        <Feature>PBP 13/2</Feature>
+        <Feature>PBP 2/2</Feature>
+        <Feature>PBP 8/8</Feature>
+        <Feature>PBP 6/1</Feature>
+        <Feature>PBP 8/3</Feature>
         <Feature>PBP 8/5</Feature>
         <Feature>PBP 11/1</Feature>
         <Feature>PBP 8/2</Feature>
@@ -2716,17 +2713,41 @@
         <Feature>PBP 6/3</Feature>
         <Feature>PBP 14/8</Feature>
         <Feature>PBP 1/2</Feature>
+        <Feature>PBP 8/9</Feature>
+        <Feature>PBP 12/2</Feature>
+        <Feature>PBP 14/11</Feature>
+        <Feature>PBP 6/6</Feature>
+        <Feature>PBP 6/8</Feature>
+        <Feature>PBP 6/4</Feature>
+        <Feature>PBP 7/2</Feature>
+        <Feature>PBP 6/7</Feature>
+        <Feature>PBP 7/1</Feature>
+        <Feature>PBP 14/7</Feature>
+        <Feature>PBP 13/4</Feature>
+        <Feature>PBP 14/4</Feature>
+        <Feature>PBP 5/2</Feature>
+        <Feature>PBP 14/9</Feature>
+        <Feature>PBP 13/1</Feature>
+        <Feature>PBP 6/2</Feature>
+        <Feature>PBP 9/1</Feature>
+        <Feature>PBP 3/1</Feature>
+        <Feature>PBP 14/10</Feature>
+        <Feature>PBP 12/1</Feature>
+        <Feature>PBP 1/1</Feature>
+        <Feature>PBP 10/1</Feature>
+        <Feature>PBP 14/12</Feature>
+        <Feature>PBP 14/5</Feature>
       </Features>
     </Layer>
     <Layer Layer="MBT">
       <Features>
-        <Feature>MBT 0/1</Feature>
         <Feature>MBT 10/1</Feature>
         <Feature>MBT 10/2</Feature>
+        <Feature>MBT 3/1</Feature>
         <Feature>MBT 20/1</Feature>
         <Feature>MBT 3/2</Feature>
+        <Feature>MBT 0/1</Feature>
         <Feature>MBT 20/2</Feature>
-        <Feature>MBT 3/1</Feature>
       </Features>
     </Layer>
     <Layer Layer="DFU">
@@ -2737,57 +2758,61 @@
         <Feature>DFU 10/1</Feature>
         <Feature>DFU 3/1</Feature>
         <Feature>DFU 21/1</Feature>
+        <Feature>DFU 22/1</Feature>
         <Feature>DFU 3/3</Feature>
         <Feature>DFU 11/1</Feature>
         <Feature>DFU 0/1</Feature>
         <Feature>DFU 20/1</Feature>
         <Feature>DFU 11/2</Feature>
         <Feature>DFU 21/2</Feature>
-        <Feature>DFU 22/1</Feature>
       </Features>
     </Layer>
     <Layer Layer="GMAP">
       <Features>
-        <Feature>GMAP 102/1</Feature>
-        <Feature>GMAP 77/1</Feature>
-        <Feature>GMAP 20/59</Feature>
-        <Feature>GMAP 40/43</Feature>
-        <Feature>GMAP 20/12</Feature>
-        <Feature>GMAP 104/2</Feature>
-        <Feature>GMAP 36/5</Feature>
-        <Feature>GMAP 14/11</Feature>
-        <Feature>GMAP 40/70</Feature>
-        <Feature>GMAP 104/1</Feature>
-        <Feature>GMAP 20/44</Feature>
-        <Feature>GMAP 34/2</Feature>
-        <Feature>GMAP 38/4</Feature>
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-        <Feature>GMAP 20/33</Feature>
-        <Feature>GMAP 20/29</Feature>
-        <Feature>GMAP 79/6</Feature>
-        <Feature>GMAP 40/58</Feature>
-        <Feature>GMAP 36/1</Feature>
-        <Feature>GMAP 16/5</Feature>
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-        <Feature>GMAP 34/5</Feature>
-        <Feature>GMAP 90/1</Feature>
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-        <Feature>GMAP 100/1</Feature>
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-        <Feature>GMAP 93/6</Feature>
-        <Feature>GMAP 40/22</Feature>
-        <Feature>GMAP 1/3</Feature>
-        <Feature>GMAP 77/3</Feature>
-        <Feature>GMAP 70/1</Feature>
-        <Feature>GMAP 20/62</Feature>
-        <Feature>GMAP 20/28</Feature>
-        <Feature>GMAP 56/3</Feature>
-        <Feature>GMAP 54/4</Feature>
-        <Feature>GMAP 78/3</Feature>
+        <Feature>GMAP 20/63</Feature>
+        <Feature>GMAP 20/80</Feature>
+        <Feature>GMAP 16/2</Feature>
+        <Feature>GMAP 40/62</Feature>
+        <Feature>GMAP 40/42</Feature>
+        <Feature>GMAP 20/1</Feature>
+        <Feature>GMAP 35/12</Feature>
+        <Feature>GMAP 14/12</Feature>
+        <Feature>GMAP 37/1</Feature>
+        <Feature>GMAP 40/68</Feature>
+        <Feature>GMAP 40/51</Feature>
+        <Feature>GMAP 102/2</Feature>
+        <Feature>GMAP 59/2</Feature>
+        <Feature>GMAP 1/6</Feature>
+        <Feature>GMAP 18/4</Feature>
+        <Feature>GMAP 1/1</Feature>
+        <Feature>GMAP 40/24</Feature>
+        <Feature>GMAP 18/5</Feature>
+        <Feature>GMAP 40/59</Feature>
+        <Feature>GMAP 59/7</Feature>
+        <Feature>GMAP 20/58</Feature>
+        <Feature>GMAP 17/4</Feature>
+        <Feature>GMAP 72/2</Feature>
+        <Feature>GMAP 102/5</Feature>
+        <Feature>GMAP 40/16</Feature>
+        <Feature>GMAP 57/2</Feature>
+        <Feature>GMAP 40/53</Feature>
+        <Feature>GMAP 40/40</Feature>
+        <Feature>GMAP 20/35</Feature>
+        <Feature>GMAP 20/49</Feature>
+        <Feature>GMAP 32/6</Feature>
+        <Feature>GMAP 20/101</Feature>
+        <Feature>GMAP 40/64</Feature>
+        <Feature>GMAP 40/45</Feature>
+        <Feature>GMAP 20/99</Feature>
+        <Feature>GMAP 108/1</Feature>
+        <Feature>GMAP 36/4</Feature>
+        <Feature>GMAP 2/2</Feature>
+        <Feature>GMAP 40/5</Feature>
+        <Feature>GMAP 20/102</Feature>
+        <Feature>GMAP 59/4</Feature>
+        <Feature>GMAP 20/94</Feature>
+        <Feature>GMAP 20/93</Feature>
+        <Feature>GMAP 59/3</Feature>
         <Feature>GMAP 79/2</Feature>
         <Feature>GMAP 38/5</Feature>
         <Feature>GMAP 58/2</Feature>
@@ -2830,122 +2855,23 @@
         <Feature>GMAP 20/104</Feature>
         <Feature>GMAP 37/3</Feature>
         <Feature>GMAP 40/37</Feature>
-        <Feature>GMAP 20/69</Feature>
-        <Feature>GMAP 40/48</Feature>
-        <Feature>GMAP 40/28</Feature>
-        <Feature>GMAP 20/34</Feature>
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-        <Feature>GMAP 20/106</Feature>
-        <Feature>GMAP 35/3</Feature>
-        <Feature>GMAP 20/112</Feature>
-        <Feature>GMAP 20/113</Feature>
-        <Feature>GMAP 79/5</Feature>
-        <Feature>GMAP 52/1</Feature>
-        <Feature>GMAP 102/3</Feature>
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-        <Feature>GMAP 22/1</Feature>
-        <Feature>GMAP 16/4</Feature>
-        <Feature>GMAP 20/100</Feature>
-        <Feature>GMAP 50/1</Feature>
-        <Feature>GMAP 40/41</Feature>
-        <Feature>GMAP 20/3</Feature>
-        <Feature>GMAP 20/23</Feature>
-        <Feature>GMAP 17/3</Feature>
-        <Feature>GMAP 20/18</Feature>
-        <Feature>GMAP 79/7</Feature>
-        <Feature>GMAP 35/11</Feature>
-        <Feature>GMAP 20/65</Feature>
-        <Feature>GMAP 75/2</Feature>
-        <Feature>GMAP 38/1</Feature>
-        <Feature>GMAP 94/1</Feature>
-        <Feature>GMAP 92/4</Feature>
-        <Feature>GMAP 40/60</Feature>
-        <Feature>GMAP 105/2</Feature>
-        <Feature>GMAP 103/2</Feature>
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-        <Feature>GMAP 20/107</Feature>
-        <Feature>GMAP 20/77</Feature>
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-        <Feature>GMAP 20/37</Feature>
-        <Feature>GMAP 18/1</Feature>
-        <Feature>GMAP 79/10</Feature>
-        <Feature>GMAP 20/92</Feature>
-        <Feature>GMAP 20/19</Feature>
-        <Feature>GMAP 20/95</Feature>
-        <Feature>GMAP 40/71</Feature>
-        <Feature>GMAP 40/55</Feature>
-        <Feature>GMAP 20/67</Feature>
-        <Feature>GMAP 32/5</Feature>
-        <Feature>GMAP 20/13</Feature>
-        <Feature>GMAP 42/1</Feature>
-        <Feature>GMAP 62/1</Feature>
-        <Feature>GMAP 32/7</Feature>
-        <Feature>GMAP 74/1</Feature>
-        <Feature>GMAP 20/25</Feature>
-        <Feature>GMAP 77/2</Feature>
-        <Feature>GMAP 20/109</Feature>
-        <Feature>GMAP 20/97</Feature>
-        <Feature>GMAP 35/9</Feature>
-        <Feature>GMAP 40/20</Feature>
-        <Feature>GMAP 40/35</Feature>
-        <Feature>GMAP 40/49</Feature>
-        <Feature>GMAP 40/69</Feature>
-        <Feature>GMAP 39/1</Feature>
-        <Feature>GMAP 20/105</Feature>
-        <Feature>GMAP 40/61</Feature>
-        <Feature>GMAP 54/1</Feature>
-        <Feature>GMAP 82/1</Feature>
-        <Feature>GMAP 20/60</Feature>
-        <Feature>GMAP 40/66</Feature>
-        <Feature>GMAP 20/108</Feature>
-        <Feature>GMAP 57/1</Feature>
-        <Feature>GMAP 20/20</Feature>
-        <Feature>GMAP 81/1</Feature>
-        <Feature>GMAP 12/1</Feature>
-        <Feature>GMAP 17/6</Feature>
-        <Feature>GMAP 20/51</Feature>
-        <Feature>GMAP 40/54</Feature>
-        <Feature>GMAP 79/15</Feature>
-        <Feature>GMAP 73/1</Feature>
-        <Feature>GMAP 36/6</Feature>
-        <Feature>GMAP 92/2</Feature>
-        <Feature>GMAP 20/74</Feature>
-        <Feature>GMAP 34/1</Feature>
-        <Feature>GMAP 79/11</Feature>
-        <Feature>GMAP 17/1</Feature>
-        <Feature>GMAP 20/70</Feature>
-        <Feature>GMAP 40/2</Feature>
-        <Feature>GMAP 20/81</Feature>
-        <Feature>GMAP 55/1</Feature>
-        <Feature>GMAP 19/3</Feature>
-        <Feature>GMAP 40/29</Feature>
-        <Feature>GMAP 40/56</Feature>
-        <Feature>GMAP 79/1</Feature>
-        <Feature>GMAP 32/3</Feature>
-        <Feature>GMAP 20/85</Feature>
-        <Feature>GMAP 107/2</Feature>
-        <Feature>GMAP 57/3</Feature>
-        <Feature>GMAP 40/3</Feature>
-        <Feature>GMAP 20/43</Feature>
-        <Feature>GMAP 92/1</Feature>
-        <Feature>GMAP 20/56</Feature>
-        <Feature>GMAP 56/2</Feature>
-        <Feature>GMAP 41/1</Feature>
-        <Feature>GMAP 38/2</Feature>
-        <Feature>GMAP 79/14</Feature>
-        <Feature>GMAP 20/110</Feature>
-        <Feature>GMAP 40/1</Feature>
-        <Feature>GMAP 14/7</Feature>
-        <Feature>GMAP 40/65</Feature>
-        <Feature>GMAP 59/1</Feature>
-        <Feature>GMAP 40/50</Feature>
-        <Feature>GMAP 40/67</Feature>
-        <Feature>GMAP 20/50</Feature>
-        <Feature>GMAP 40/34</Feature>
-        <Feature>GMAP 40/63</Feature>
-        <Feature>GMAP 38/3</Feature>
-        <Feature>GMAP 33/1</Feature>
-        <Feature>GMAP 20/39</Feature>
+        <Feature>GMAP 20/32</Feature>
+        <Feature>GMAP 34/5</Feature>
+        <Feature>GMAP 90/1</Feature>
+        <Feature>GMAP 32/1</Feature>
+        <Feature>GMAP 105/3</Feature>
+        <Feature>GMAP 103/3</Feature>
+        <Feature>GMAP 100/1</Feature>
+        <Feature>GMAP 20/5</Feature>
+        <Feature>GMAP 93/6</Feature>
+        <Feature>GMAP 40/22</Feature>
+        <Feature>GMAP 1/3</Feature>
+        <Feature>GMAP 77/3</Feature>
+        <Feature>GMAP 70/1</Feature>
+        <Feature>GMAP 20/62</Feature>
+        <Feature>GMAP 20/28</Feature>
+        <Feature>GMAP 56/3</Feature>
+        <Feature>GMAP 54/4</Feature>
         <Feature>GMAP 14/4</Feature>
         <Feature>GMAP 20/82</Feature>
         <Feature>GMAP 20/24</Feature>
@@ -2989,6 +2915,155 @@
         <Feature>GMAP 20/88</Feature>
         <Feature>GMAP 20/22</Feature>
         <Feature>GMAP 76/4</Feature>
+        <Feature>GMAP 32/3</Feature>
+        <Feature>GMAP 20/85</Feature>
+        <Feature>GMAP 107/2</Feature>
+        <Feature>GMAP 57/3</Feature>
+        <Feature>GMAP 40/3</Feature>
+        <Feature>GMAP 20/43</Feature>
+        <Feature>GMAP 92/1</Feature>
+        <Feature>GMAP 20/56</Feature>
+        <Feature>GMAP 56/2</Feature>
+        <Feature>GMAP 41/1</Feature>
+        <Feature>GMAP 38/2</Feature>
+        <Feature>GMAP 79/14</Feature>
+        <Feature>GMAP 20/110</Feature>
+        <Feature>GMAP 40/1</Feature>
+        <Feature>GMAP 14/7</Feature>
+        <Feature>GMAP 40/65</Feature>
+        <Feature>GMAP 59/1</Feature>
+        <Feature>GMAP 40/50</Feature>
+        <Feature>GMAP 40/67</Feature>
+        <Feature>GMAP 20/50</Feature>
+        <Feature>GMAP 40/34</Feature>
+        <Feature>GMAP 40/63</Feature>
+        <Feature>GMAP 38/3</Feature>
+        <Feature>GMAP 33/1</Feature>
+        <Feature>GMAP 20/39</Feature>
+        <Feature>GMAP 40/52</Feature>
+        <Feature>GMAP 20/98</Feature>
+        <Feature>GMAP 16/6</Feature>
+        <Feature>GMAP 19/1</Feature>
+        <Feature>GMAP 105/5</Feature>
+        <Feature>GMAP 18/3</Feature>
+        <Feature>GMAP 20/61</Feature>
+        <Feature>GMAP 12/2</Feature>
+        <Feature>GMAP 40/25</Feature>
+        <Feature>GMAP 93/5</Feature>
+        <Feature>GMAP 77/4</Feature>
+        <Feature>GMAP 35/10</Feature>
+        <Feature>GMAP 40/72</Feature>
+        <Feature>GMAP 20/10</Feature>
+        <Feature>GMAP 13/1</Feature>
+        <Feature>GMAP 20/26</Feature>
+        <Feature>GMAP 93/1</Feature>
+        <Feature>GMAP 35/7</Feature>
+        <Feature>GMAP 102/1</Feature>
+        <Feature>GMAP 77/1</Feature>
+        <Feature>GMAP 20/59</Feature>
+        <Feature>GMAP 40/43</Feature>
+        <Feature>GMAP 20/12</Feature>
+        <Feature>GMAP 104/2</Feature>
+        <Feature>GMAP 36/5</Feature>
+        <Feature>GMAP 14/11</Feature>
+        <Feature>GMAP 40/70</Feature>
+        <Feature>GMAP 104/1</Feature>
+        <Feature>GMAP 20/44</Feature>
+        <Feature>GMAP 34/2</Feature>
+        <Feature>GMAP 38/4</Feature>
+        <Feature>GMAP 40/9</Feature>
+        <Feature>GMAP 78/3</Feature>
+        <Feature>GMAP 20/108</Feature>
+        <Feature>GMAP 57/1</Feature>
+        <Feature>GMAP 20/20</Feature>
+        <Feature>GMAP 81/1</Feature>
+        <Feature>GMAP 12/1</Feature>
+        <Feature>GMAP 17/6</Feature>
+        <Feature>GMAP 20/51</Feature>
+        <Feature>GMAP 40/54</Feature>
+        <Feature>GMAP 79/15</Feature>
+        <Feature>GMAP 73/1</Feature>
+        <Feature>GMAP 36/6</Feature>
+        <Feature>GMAP 92/2</Feature>
+        <Feature>GMAP 20/74</Feature>
+        <Feature>GMAP 34/1</Feature>
+        <Feature>GMAP 79/11</Feature>
+        <Feature>GMAP 17/1</Feature>
+        <Feature>GMAP 20/70</Feature>
+        <Feature>GMAP 40/2</Feature>
+        <Feature>GMAP 20/81</Feature>
+        <Feature>GMAP 55/1</Feature>
+        <Feature>GMAP 19/3</Feature>
+        <Feature>GMAP 40/29</Feature>
+        <Feature>GMAP 40/56</Feature>
+        <Feature>GMAP 79/1</Feature>
+        <Feature>GMAP 59/11</Feature>
+        <Feature>GMAP 20/16</Feature>
+        <Feature>GMAP 20/78</Feature>
+        <Feature>GMAP 35/2</Feature>
+        <Feature>GMAP 34/4</Feature>
+        <Feature>GMAP 20/64</Feature>
+        <Feature>GMAP 20/57</Feature>
+        <Feature>GMAP 20/111</Feature>
+        <Feature>GMAP 59/5</Feature>
+        <Feature>GMAP 38/6</Feature>
+        <Feature>GMAP 105/7</Feature>
+        <Feature>GMAP 20/31</Feature>
+        <Feature>GMAP 20/103</Feature>
+        <Feature>GMAP 14/1</Feature>
+        <Feature>GMAP 59/9</Feature>
+        <Feature>GMAP 14/6</Feature>
+        <Feature>GMAP 12/3</Feature>
+        <Feature>GMAP 35/1</Feature>
+        <Feature>GMAP 79/8</Feature>
+        <Feature>GMAP 20/79</Feature>
+        <Feature>GMAP 20/69</Feature>
+        <Feature>GMAP 40/48</Feature>
+        <Feature>GMAP 40/28</Feature>
+        <Feature>GMAP 40/10</Feature>
+        <Feature>GMAP 20/34</Feature>
+        <Feature>GMAP 20/2</Feature>
+        <Feature>GMAP 20/106</Feature>
+        <Feature>GMAP 35/3</Feature>
+        <Feature>GMAP 20/112</Feature>
+        <Feature>GMAP 20/113</Feature>
+        <Feature>GMAP 79/5</Feature>
+        <Feature>GMAP 52/1</Feature>
+        <Feature>GMAP 102/3</Feature>
+        <Feature>GMAP 20/6</Feature>
+        <Feature>GMAP 22/1</Feature>
+        <Feature>GMAP 16/4</Feature>
+        <Feature>GMAP 20/100</Feature>
+        <Feature>GMAP 50/1</Feature>
+        <Feature>GMAP 40/41</Feature>
+        <Feature>GMAP 20/3</Feature>
+        <Feature>GMAP 20/23</Feature>
+        <Feature>GMAP 17/3</Feature>
+        <Feature>GMAP 20/18</Feature>
+        <Feature>GMAP 79/7</Feature>
+        <Feature>GMAP 35/11</Feature>
+        <Feature>GMAP 20/65</Feature>
+        <Feature>GMAP 75/2</Feature>
+        <Feature>GMAP 38/1</Feature>
+        <Feature>GMAP 94/1</Feature>
+        <Feature>GMAP 92/4</Feature>
+        <Feature>GMAP 40/60</Feature>
+        <Feature>GMAP 105/2</Feature>
+        <Feature>GMAP 103/2</Feature>
+        <Feature>GMAP 17/2</Feature>
+        <Feature>GMAP 20/107</Feature>
+        <Feature>GMAP 20/77</Feature>
+        <Feature>GMAP 74/2</Feature>
+        <Feature>GMAP 20/37</Feature>
+        <Feature>GMAP 18/1</Feature>
+        <Feature>GMAP 79/10</Feature>
+        <Feature>GMAP 20/33</Feature>
+        <Feature>GMAP 20/29</Feature>
+        <Feature>GMAP 79/6</Feature>
+        <Feature>GMAP 40/58</Feature>
+        <Feature>GMAP 36/1</Feature>
+        <Feature>GMAP 16/5</Feature>
+        <Feature>GMAP 14/9</Feature>
         <Feature>GMAP 40/21</Feature>
         <Feature>GMAP 14/3</Feature>
         <Feature>GMAP 93/7</Feature>
@@ -3037,44 +3112,34 @@
         <Feature>GMAP 74/4</Feature>
         <Feature>GMAP 92/3</Feature>
         <Feature>GMAP 20/72</Feature>
-        <Feature>GMAP 40/52</Feature>
-        <Feature>GMAP 20/98</Feature>
-        <Feature>GMAP 16/6</Feature>
-        <Feature>GMAP 19/1</Feature>
-        <Feature>GMAP 105/5</Feature>
-        <Feature>GMAP 18/3</Feature>
-        <Feature>GMAP 20/61</Feature>
-        <Feature>GMAP 12/2</Feature>
-        <Feature>GMAP 40/25</Feature>
-        <Feature>GMAP 93/5</Feature>
-        <Feature>GMAP 77/4</Feature>
-        <Feature>GMAP 35/10</Feature>
-        <Feature>GMAP 40/72</Feature>
-        <Feature>GMAP 20/10</Feature>
-        <Feature>GMAP 13/1</Feature>
-        <Feature>GMAP 20/26</Feature>
-        <Feature>GMAP 93/1</Feature>
-        <Feature>GMAP 35/7</Feature>
-        <Feature>GMAP 59/11</Feature>
-        <Feature>GMAP 20/16</Feature>
-        <Feature>GMAP 20/78</Feature>
-        <Feature>GMAP 35/2</Feature>
-        <Feature>GMAP 34/4</Feature>
-        <Feature>GMAP 20/64</Feature>
-        <Feature>GMAP 20/57</Feature>
-        <Feature>GMAP 20/111</Feature>
-        <Feature>GMAP 59/5</Feature>
-        <Feature>GMAP 38/6</Feature>
-        <Feature>GMAP 105/7</Feature>
-        <Feature>GMAP 20/31</Feature>
-        <Feature>GMAP 20/103</Feature>
-        <Feature>GMAP 14/1</Feature>
-        <Feature>GMAP 59/9</Feature>
-        <Feature>GMAP 14/6</Feature>
-        <Feature>GMAP 12/3</Feature>
-        <Feature>GMAP 35/1</Feature>
-        <Feature>GMAP 79/8</Feature>
-        <Feature>GMAP 20/79</Feature>
+        <Feature>GMAP 20/92</Feature>
+        <Feature>GMAP 20/19</Feature>
+        <Feature>GMAP 20/95</Feature>
+        <Feature>GMAP 40/71</Feature>
+        <Feature>GMAP 40/55</Feature>
+        <Feature>GMAP 20/67</Feature>
+        <Feature>GMAP 32/5</Feature>
+        <Feature>GMAP 20/13</Feature>
+        <Feature>GMAP 42/1</Feature>
+        <Feature>GMAP 62/1</Feature>
+        <Feature>GMAP 32/7</Feature>
+        <Feature>GMAP 74/1</Feature>
+        <Feature>GMAP 20/25</Feature>
+        <Feature>GMAP 77/2</Feature>
+        <Feature>GMAP 20/109</Feature>
+        <Feature>GMAP 20/97</Feature>
+        <Feature>GMAP 35/9</Feature>
+        <Feature>GMAP 40/20</Feature>
+        <Feature>GMAP 40/35</Feature>
+        <Feature>GMAP 40/49</Feature>
+        <Feature>GMAP 40/69</Feature>
+        <Feature>GMAP 39/1</Feature>
+        <Feature>GMAP 20/105</Feature>
+        <Feature>GMAP 40/61</Feature>
+        <Feature>GMAP 54/1</Feature>
+        <Feature>GMAP 82/1</Feature>
+        <Feature>GMAP 20/60</Feature>
+        <Feature>GMAP 40/66</Feature>
         <Feature>GMAP 40/31</Feature>
         <Feature>GMAP 20/87</Feature>
         <Feature>GMAP 16/1</Feature>
@@ -3093,75 +3158,31 @@
         <Feature>GMAP 104/3</Feature>
         <Feature>GMAP 20/83</Feature>
         <Feature>GMAP 17/5</Feature>
-        <Feature>GMAP 20/63</Feature>
-        <Feature>GMAP 20/80</Feature>
-        <Feature>GMAP 16/2</Feature>
-        <Feature>GMAP 40/62</Feature>
-        <Feature>GMAP 40/42</Feature>
-        <Feature>GMAP 20/1</Feature>
-        <Feature>GMAP 35/12</Feature>
-        <Feature>GMAP 14/12</Feature>
-        <Feature>GMAP 37/1</Feature>
-        <Feature>GMAP 40/68</Feature>
-        <Feature>GMAP 40/51</Feature>
-        <Feature>GMAP 102/2</Feature>
-        <Feature>GMAP 59/2</Feature>
-        <Feature>GMAP 1/6</Feature>
-        <Feature>GMAP 18/4</Feature>
-        <Feature>GMAP 1/1</Feature>
-        <Feature>GMAP 40/24</Feature>
-        <Feature>GMAP 18/5</Feature>
-        <Feature>GMAP 40/59</Feature>
-        <Feature>GMAP 59/7</Feature>
-        <Feature>GMAP 20/58</Feature>
-        <Feature>GMAP 17/4</Feature>
-        <Feature>GMAP 72/2</Feature>
-        <Feature>GMAP 102/5</Feature>
-        <Feature>GMAP 40/16</Feature>
-        <Feature>GMAP 57/2</Feature>
-        <Feature>GMAP 40/53</Feature>
-        <Feature>GMAP 40/40</Feature>
-        <Feature>GMAP 20/35</Feature>
-        <Feature>GMAP 20/49</Feature>
-        <Feature>GMAP 32/6</Feature>
-        <Feature>GMAP 20/101</Feature>
-        <Feature>GMAP 40/64</Feature>
-        <Feature>GMAP 40/45</Feature>
-        <Feature>GMAP 20/99</Feature>
-        <Feature>GMAP 108/1</Feature>
-        <Feature>GMAP 36/4</Feature>
-        <Feature>GMAP 2/2</Feature>
-        <Feature>GMAP 40/5</Feature>
-        <Feature>GMAP 20/102</Feature>
-        <Feature>GMAP 59/4</Feature>
-        <Feature>GMAP 20/94</Feature>
-        <Feature>GMAP 20/93</Feature>
-        <Feature>GMAP 59/3</Feature>
       </Features>
     </Layer>
     <Layer Layer="CORE">
       <Features>
-        <Feature>CORE 11/2</Feature>
-        <Feature>CORE 11/1</Feature>
-        <Feature>CORE 2a/60</Feature>
-        <Feature>CORE 12/1</Feature>
-        <Feature>CORE 2a/53</Feature>
-        <Feature>CORE 31/2</Feature>
         <Feature>CORE 11/6</Feature>
         <Feature>CORE 20a/1</Feature>
         <Feature>CORE 2b/60</Feature>
         <Feature>CORE 20/4</Feature>
         <Feature>CORE 2a/50</Feature>
+        <Feature>CORE 12/3</Feature>
         <Feature>CORE 2/60</Feature>
         <Feature>CORE 2/1</Feature>
-        <Feature>CORE 12/3</Feature>
+        <Feature>CORE 40/2</Feature>
+        <Feature>CORE 11/3</Feature>
+        <Feature>CORE 11/2</Feature>
+        <Feature>CORE 11/1</Feature>
+        <Feature>CORE 2a/60</Feature>
+        <Feature>CORE 12/1</Feature>
+        <Feature>CORE 2a/53</Feature>
+        <Feature>CORE 31/2</Feature>
         <Feature>CORE 2a/54</Feature>
         <Feature>CORE 2a/51</Feature>
         <Feature>CORE 41/2</Feature>
         <Feature>CORE 11/5</Feature>
         <Feature>CORE 2a/52</Feature>
-        <Feature>CORE 40/2</Feature>
-        <Feature>CORE 11/3</Feature>
       </Features>
     </Layer>
     <Layer Layer="UHCI">
@@ -3169,5 +3190,30 @@
         <Feature>UHCI 0/60</Feature>
       </Features>
     </Layer>
+    <Layer Layer="IOPT">
+      <Features>
+        <Feature>IOPT 2/45b</Feature>
+        <Feature>IOPT 2/42b</Feature>
+        <Feature>IOPT 2/12b</Feature>
+        <Feature>IOPT 2/63b</Feature>
+        <Feature>IOPT 2/19b</Feature>
+        <Feature>IOPT 2/28b</Feature>
+        <Feature>IOPT 2/16b</Feature>
+        <Feature>IOPT 2/33b</Feature>
+        <Feature>IOPT 2/30b</Feature>
+        <Feature>IOPT 2/55b</Feature>
+        <Feature>IOPT 2/2b</Feature>
+        <Feature>IOPT 2/6b</Feature>
+        <Feature>IOPT 2a/2</Feature>
+        <Feature>IOPT 2/29b</Feature>
+        <Feature>IOPT 2/44b</Feature>
+        <Feature>IOPT 2/35b</Feature>
+        <Feature>IOPT 2/58b</Feature>
+        <Feature>IOPT 2/7b</Feature>
+        <Feature>IOPT 2/59b</Feature>
+        <Feature>IOPT 2/5b</Feature>
+        <Feature>IOPT 2/53b</Feature>
+      </Features>
+    </Layer>
   </Layers>
-</Qualification>
+</Qualification>
\ No newline at end of file
diff --git a/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.pts b/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.pts
index fc1a5cfa981..6752f19cfc4 100644
--- a/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.pts
+++ b/tests/bluetooth/qualification/ICS_Zephyr_Bluetooth_Host.pts
@@ -1,6 +1,6 @@
 <?xml version="1.0" encoding="utf-8"?>
 <project>
-  <qdid>332723</qdid>
+  <qdid>347313</qdid>
   <name>Zephyr Host</name>
   <pics>
     <profile>
@@ -1301,17 +1301,6 @@
         <row>48</row>
       </item>
     </profile>
-    <profile>
-      <name>IOP</name>
-      <item>
-        <table>1</table>
-        <row>1</row>
-      </item>
-      <item>
-        <table>2</table>
-        <row>2</row>
-      </item>
-    </profile>
     <profile>
       <name>GATT</name>
       <item>
@@ -3195,6 +3184,10 @@
         <table>3</table>
         <row>2</row>
       </item>
+      <item>
+        <table>0a</table>
+        <row>1</row>
+      </item>
       <item>
         <table>4</table>
         <row>3</row>
@@ -3258,6 +3251,10 @@
         <table>1</table>
         <row>2</row>
       </item>
+      <item>
+        <table>0a</table>
+        <row>1</row>
+      </item>
       <item>
         <table>2</table>
         <row>4</row>
@@ -3329,6 +3326,10 @@
         <table>4</table>
         <row>4</row>
       </item>
+      <item>
+        <table>0a</table>
+        <row>1</row>
+      </item>
       <item>
         <table>0</table>
         <row>1</row>
@@ -4197,6 +4198,10 @@
         <table>23</table>
         <row>3</row>
       </item>
+      <item>
+        <table>20a</table>
+        <row>1</row>
+      </item>
       <item>
         <table>22</table>
         <row>4</row>
@@ -5313,6 +5318,10 @@
         <table>2</table>
         <row>2</row>
       </item>
+      <item>
+        <table>5</table>
+        <row>1</row>
+      </item>
       <item>
         <table>2</table>
         <row>4</row>
@@ -5500,6 +5509,10 @@
         <table>10</table>
         <row>1</row>
       </item>
+      <item>
+        <table>13</table>
+        <row>12</row>
+      </item>
       <item>
         <table>1</table>
         <row>2</row>
@@ -5810,6 +5823,10 @@
         <table>0</table>
         <row>1</row>
       </item>
+      <item>
+        <table>1</table>
+        <row>1</row>
+      </item>
       <item>
         <table>9</table>
         <row>4</row>
@@ -5853,6 +5870,10 @@
         <table>4</table>
         <row>2</row>
       </item>
+      <item>
+        <table>3</table>
+        <row>2a</row>
+      </item>
       <item>
         <table>0</table>
         <row>1</row>
@@ -5905,6 +5926,10 @@
         <table>3</table>
         <row>2</row>
       </item>
+      <item>
+        <table>1</table>
+        <row>1</row>
+      </item>
       <item>
         <table>4</table>
         <row>3</row>
@@ -6996,10 +7021,6 @@
         <table>92</table>
         <row>3</row>
       </item>
-      <item>
-        <table>27</table>
-        <row>4</row>
-      </item>
       <item>
         <table>54</table>
         <row>3</row>
@@ -7148,10 +7169,6 @@
         <table>59</table>
         <row>8</row>
       </item>
-      <item>
-        <table>5</table>
-        <row>3</row>
-      </item>
       <item>
         <table>39</table>
         <row>5</row>
@@ -8798,6 +8815,14 @@
         <table>8</table>
         <row>2</row>
       </item>
+      <item>
+        <table>5</table>
+        <row>1</row>
+      </item>
+      <item>
+        <table>25</table>
+        <row>1</row>
+      </item>
       <item>
         <table>31</table>
         <row>1</row>
@@ -8906,6 +8931,10 @@
         <table>31</table>
         <row>2</row>
       </item>
+      <item>
+        <table>15</table>
+        <row>1</row>
+      </item>
       <item>
         <table>6</table>
         <row>5</row>
@@ -8946,10 +8975,6 @@
         <table>8</table>
         <row>4</row>
       </item>
-      <item>
-        <table>20</table>
-        <row>9</row>
-      </item>
       <item>
         <table>22</table>
         <row>6</row>
@@ -9109,6 +9134,10 @@
         <table>5</table>
         <row>5</row>
       </item>
+      <item>
+        <table>1</table>
+        <row>1</row>
+      </item>
       <item>
         <table>3</table>
         <row>6</row>
@@ -9240,6 +9269,10 @@
         <table>13</table>
         <row>2</row>
       </item>
+      <item>
+        <table>91</table>
+        <row>1</row>
+      </item>
       <item>
         <table>13</table>
         <row>1</row>
@@ -9308,6 +9341,10 @@
         <table>24</table>
         <row>6</row>
       </item>
+      <item>
+        <table>11</table>
+        <row>1</row>
+      </item>
       <item>
         <table>14</table>
         <row>1</row>
@@ -9336,6 +9373,10 @@
         <table>2</table>
         <row>2</row>
       </item>
+      <item>
+        <table>41</table>
+        <row>1</row>
+      </item>
       <item>
         <table>46</table>
         <row>1</row>
@@ -9439,6 +9480,10 @@
         <table>116</table>
         <row>4</row>
       </item>
+      <item>
+        <table>54</table>
+        <row>5</row>
+      </item>
       <item>
         <table>116</table>
         <row>5</row>
@@ -9471,6 +9516,10 @@
         <table>118</table>
         <row>2</row>
       </item>
+      <item>
+        <table>114</table>
+        <row>5</row>
+      </item>
       <item>
         <table>76</table>
         <row>5</row>
@@ -9651,6 +9700,10 @@
         <table>151</table>
         <row>6</row>
       </item>
+      <item>
+        <table>91</table>
+        <row>1</row>
+      </item>
       <item>
         <table>56</table>
         <row>6</row>
@@ -9719,6 +9772,10 @@
         <table>75</table>
         <row>1</row>
       </item>
+      <item>
+        <table>94</table>
+        <row>6</row>
+      </item>
       <item>
         <table>114</table>
         <row>1</row>
@@ -9727,6 +9784,10 @@
         <table>55</table>
         <row>8</row>
       </item>
+      <item>
+        <table>71</table>
+        <row>1</row>
+      </item>
       <item>
         <table>14</table>
         <row>1</row>
@@ -9739,6 +9800,10 @@
         <table>56</table>
         <row>3</row>
       </item>
+      <item>
+        <table>14</table>
+        <row>8</row>
+      </item>
       <item>
         <table>75</table>
         <row>4</row>
@@ -9819,6 +9884,10 @@
         <table>53</table>
         <row>1</row>
       </item>
+      <item>
+        <table>74</table>
+        <row>7</row>
+      </item>
       <item>
         <table>117</table>
         <row>1</row>
@@ -9851,6 +9920,10 @@
         <table>120</table>
         <row>1</row>
       </item>
+      <item>
+        <table>51</table>
+        <row>1</row>
+      </item>
       <item>
         <table>152</table>
         <row>1</row>
@@ -9879,6 +9952,10 @@
         <table>96</table>
         <row>1</row>
       </item>
+      <item>
+        <table>11</table>
+        <row>1</row>
+      </item>
       <item>
         <table>96</table>
         <row>3</row>
@@ -10063,6 +10140,10 @@
         <table>96</table>
         <row>11</row>
       </item>
+      <item>
+        <table>74</table>
+        <row>8</row>
+      </item>
       <item>
         <table>100</table>
         <row>1</row>
@@ -10099,6 +10180,10 @@
         <table>74</table>
         <row>4</row>
       </item>
+      <item>
+        <table>2</table>
+        <row>2a</row>
+      </item>
       <item>
         <table>119</table>
         <row>2</row>
@@ -10175,6 +10260,10 @@
         <table>74</table>
         <row>6</row>
       </item>
+      <item>
+        <table>111</table>
+        <row>1</row>
+      </item>
       <item>
         <table>14</table>
         <row>4</row>
@@ -10326,6 +10415,10 @@
         <table>6</table>
         <row>3</row>
       </item>
+      <item>
+        <table>10</table>
+        <row>1</row>
+      </item>
       <item>
         <table>6</table>
         <row>1</row>
@@ -12130,5 +12223,92 @@
         <row>60</row>
       </item>
     </profile>
+    <profile>
+      <name>IOPT</name>
+      <item>
+        <table>2</table>
+        <row>16b</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>30b</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>2b</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>7b</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>55b</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>45b</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>59b</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>5b</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>6b</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>42b</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>53b</row>
+      </item>
+      <item>
+        <table>2a</table>
+        <row>2</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>29b</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>63b</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>19b</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>12b</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>33b</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>28b</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>58b</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>44b</row>
+      </item>
+      <item>
+        <table>2</table>
+        <row>35b</row>
+      </item>
+    </profile>
   </pics>
 </project>
diff --git a/tests/bluetooth/shell/audio.conf b/tests/bluetooth/shell/audio.conf
index 697f3be4352..e73d21ea1da 100644
--- a/tests/bluetooth/shell/audio.conf
+++ b/tests/bluetooth/shell/audio.conf
@@ -143,6 +143,8 @@ CONFIG_BT_CCP_CALL_CONTROL_SERVER_BEARER_COUNT=2
 CONFIG_BT_TBS=y
 CONFIG_BT_TBS_BEARER_COUNT=1
 CONFIG_BT_TBS_SUPPORTED_FEATURES=3
+CONFIG_BT_CCP_CALL_CONTROL_CLIENT=y
+CONFIG_BT_CCP_CALL_CONTROL_CLIENT_BEARER_COUNT=2
 CONFIG_BT_TBS_CLIENT_TBS=y
 CONFIG_BT_TBS_CLIENT_GTBS=y
 
diff --git a/tests/bluetooth/shell/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/tests/bluetooth/shell/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
new file mode 100644
index 00000000000..538460a7360
--- /dev/null
+++ b/tests/bluetooth/shell/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,bt-hci = &bt_hci_uart;
+	};
+};
+
+&lpuart3 {
+	status = "okay";
+	current-speed = <3000000>;
+	hw-flow-control;
+
+	bt_hci_uart: bt_hci_uart {
+		compatible = "zephyr,bt-hci-uart";
+		status = "okay";
+	};
+};
diff --git a/tests/bluetooth/shell/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/tests/bluetooth/shell/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf
new file mode 100644
index 00000000000..c214409ea68
--- /dev/null
+++ b/tests/bluetooth/shell/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf
@@ -0,0 +1,30 @@
+#select NXP NW612 Chipset
+CONFIG_BT_NXP_NW612=y
+#Enable entropy generator
+CONFIG_ENTROPY_GENERATOR=y
+
+CONFIG_BT_HFP_HF_CODEC_NEG=y
+CONFIG_BT_HFP_AG_CODEC_NEG=y
+
+CONFIG_BT_HFP_HF_ECNR=y
+CONFIG_BT_HFP_AG_ECNR=y
+
+CONFIG_BT_HFP_HF_3WAY_CALL=y
+CONFIG_BT_HFP_AG_3WAY_CALL=y
+
+CONFIG_BT_HFP_HF_VOICE_RECG_TEXT=y
+CONFIG_BT_HFP_AG_VOICE_RECG_TEXT=y
+
+CONFIG_BT_HFP_AG_VOICE_TAG=y
+
+CONFIG_BT_HFP_HF_HF_INDICATOR_ENH_SAFETY=y
+CONFIG_BT_HFP_HF_HF_INDICATOR_BATTERY=y
+
+CONFIG_BT_HFP_AG_HF_INDICATOR_ENH_SAFETY=y
+CONFIG_BT_HFP_AG_HF_INDICATOR_BATTERY=y
+
+CONFIG_BT_SETTINGS=n
+CONFIG_FLASH=n
+CONFIG_FLASH_MAP=n
+CONFIG_NVS=n
+CONFIG_SETTINGS=n
diff --git a/tests/bluetooth/shell/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/tests/bluetooth/shell/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
new file mode 100644
index 00000000000..0198087c363
--- /dev/null
+++ b/tests/bluetooth/shell/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,sram = &dtcm;
+		zephyr,shell-uart = &lpuart1;
+	};
+};
diff --git a/tests/bluetooth/shell/prj_br.conf b/tests/bluetooth/shell/prj_br.conf
index 45d3806473f..427fc3ec158 100644
--- a/tests/bluetooth/shell/prj_br.conf
+++ b/tests/bluetooth/shell/prj_br.conf
@@ -17,3 +17,13 @@ CONFIG_BT_GATT_CLIENT=y
 CONFIG_BT_HRS=y
 CONFIG_BT_L2CAP_DYNAMIC_CHANNEL=y
 CONFIG_BT_DEVICE_NAME="test shell"
+CONFIG_BT_L2CAP_RET=y
+CONFIG_BT_L2CAP_FC=y
+CONFIG_BT_L2CAP_ENH_RET=y
+CONFIG_BT_L2CAP_STREAM=y
+CONFIG_BT_L2CAP_FCS=y
+CONFIG_BT_L2CAP_EXT_WIN_SIZE=y
+CONFIG_BT_L2CAP_MAX_WINDOW_SIZE=5
+
+CONFIG_BT_HFP_HF=y
+CONFIG_BT_HFP_AG=y
diff --git a/tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.conf b/tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.conf
index 9d3dedf1f70..1598132000d 100644
--- a/tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.conf
+++ b/tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.conf
@@ -1,5 +1,4 @@
-CONFIG_NATIVE_UART_0_ON_OWN_PTY=y
-CONFIG_UART_NATIVE_WAIT_PTS_READY_ENABLE=y
+CONFIG_UART_NATIVE_PTY_0_ON_STDINOUT=y
 CONFIG_SHELL_CMD_BUFF_SIZE=8192
 CONFIG_SHELL_BACKEND_SERIAL_RX_RING_BUFFER_SIZE=8192
 CONFIG_LOG_PRINTK=n
diff --git a/tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.overlay b/tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.overlay
index 2cb696aea3e..db86ee4eb9a 100644
--- a/tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.overlay
+++ b/tests/bluetooth/shell/snippets/xterm-native-shell/xterm-native-shell.overlay
@@ -10,7 +10,7 @@
 
 &uart1 {
 	status = "okay";
-	compatible = "zephyr,native-posix-uart";
+	compatible = "zephyr,native-pty-uart";
 	/delete-property/ pinctrl-0;
 	/delete-property/ pinctrl-1;
 	/delete-property/ pinctrl-names;
@@ -23,7 +23,7 @@
 
 &uart0 {
 	status = "okay";
-	compatible = "zephyr,native-posix-uart";
+	compatible = "zephyr,native-pty-uart";
 	/delete-property/ pinctrl-0;
 	/delete-property/ pinctrl-1;
 	/delete-property/ pinctrl-names;
diff --git a/tests/bluetooth/shell/testcase.yaml b/tests/bluetooth/shell/testcase.yaml
index 6fb5c9db5cd..812aee24eeb 100644
--- a/tests/bluetooth/shell/testcase.yaml
+++ b/tests/bluetooth/shell/testcase.yaml
@@ -7,7 +7,7 @@ common:
 tests:
   bluetooth.shell.main:
     extra_configs:
-      - CONFIG_NATIVE_UART_0_ON_STDINOUT=y
+      - CONFIG_UART_NATIVE_PTY_0_ON_STDINOUT=y
     platform_allow:
       - qemu_x86
       - native_sim
@@ -55,7 +55,7 @@ tests:
     min_flash: 350
   bluetooth.shell.shell_br:
     extra_configs:
-      - CONFIG_NATIVE_UART_0_ON_STDINOUT=y
+      - CONFIG_UART_NATIVE_PTY_0_ON_STDINOUT=y
     extra_args: CONF_FILE="prj_br.conf"
     platform_allow:
       - qemu_cortex_m3
@@ -339,6 +339,7 @@ tests:
     extra_configs:
       - CONFIG_BT_TBS_CLIENT_TBS=n
       - CONFIG_BT_TBS_CLIENT_GTBS=n
+      - CONFIG_BT_CCP_CALL_CONTROL_CLIENT=n
     tags: bluetooth
   bluetooth.shell.audio.tbs_only_client:
     extra_args: CONF_FILE="audio.conf"
@@ -351,6 +352,7 @@ tests:
     build_only: true
     extra_configs:
       - CONFIG_BT_TBS_CLIENT_TBS=n
+      - CONFIG_BT_CCP_CALL_CONTROL_CLIENT_BEARER_COUNT=1
     tags: bluetooth
   bluetooth.audio_shell.no_cap_acceptor:
     extra_args: CONF_FILE="audio.conf"
diff --git a/tests/bluetooth/smp/testcase.yaml b/tests/bluetooth/smp/testcase.yaml
index d55503ba615..003f4217859 100644
--- a/tests/bluetooth/smp/testcase.yaml
+++ b/tests/bluetooth/smp/testcase.yaml
@@ -3,8 +3,6 @@ tests:
     extra_args:
       - EXTRA_DTC_OVERLAY_FILE="test.overlay"
     platform_allow:
-      - native_posix
-      - native_posix/native/64
       - native_sim
       - native_sim/native/64
       - qemu_x86
diff --git a/tests/bluetooth/tester/Kconfig.sysbuild b/tests/bluetooth/tester/Kconfig.sysbuild
index 6d3a155c660..e14a6e1aa8e 100644
--- a/tests/bluetooth/tester/Kconfig.sysbuild
+++ b/tests/bluetooth/tester/Kconfig.sysbuild
@@ -8,6 +8,7 @@ config NET_CORE_BOARD
 	default "nrf54h20dk/nrf54h20/cpurad" if "$(BOARD)" = "nrf54h20dk"
 	default "nrf5340dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340dk"
 	default "nrf5340_audio_dk/nrf5340/cpunet" if "$(BOARD)" = "nrf5340_audio_dk"
+	default "nrf5340bsim/nrf5340/cpunet" if $(BOARD_TARGET_STRING) = "NRF5340BSIM_NRF5340_CPUAPP"
 
 config NET_CORE_IMAGE_HCI_IPC
 	bool "HCI IPC image on network core"
diff --git a/tests/bluetooth/tester/boards/bl54l15_dvk_nrf54l15_cpuapp.conf b/tests/bluetooth/tester/boards/bl54l15_dvk_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..253e0f7d8ac
--- /dev/null
+++ b/tests/bluetooth/tester/boards/bl54l15_dvk_nrf54l15_cpuapp.conf
@@ -0,0 +1,31 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# CONFIG_TEST enforces minimal logging, which we don't want
+CONFIG_TEST=n
+
+CONFIG_ASSERT=y
+# Enable the option below to measure stack usage
+#CONFIG_INIT_STACKS=y
+CONFIG_THREAD_NAME=y
+CONFIG_HW_STACK_PROTECTION=y
+
+CONFIG_LOG=y
+CONFIG_LOG_BUFFER_SIZE=4096
+CONFIG_RTT_CONSOLE=y
+CONFIG_LOG_BACKEND_RTT=y
+CONFIG_LOG_BACKEND_RTT_MODE_DROP=y
+CONFIG_LOG_BACKEND_RTT_MESSAGE_SIZE=256
+CONFIG_USE_SEGGER_RTT=y
+CONFIG_SEGGER_RTT_BUFFER_SIZE_UP=4096
+CONFIG_LOG_BACKEND_SHOW_COLOR=n
+CONFIG_LOG_PROCESS_THREAD_STACK_SIZE=1024
+
+CONFIG_LOG_DEFAULT_LEVEL=3
+CONFIG_BTTESTER_LOG_LEVEL_DBG=y
+
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+CONFIG_BTTESTER_BTP_CMD_THREAD_STACK_SIZE=3072
diff --git a/tests/bluetooth/tester/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/bluetooth/tester/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..42ea39f77cc
--- /dev/null
+++ b/tests/bluetooth/tester/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,uart-pipe = &uart20;
+	};
+};
+
+&uart20 {
+	compatible = "nordic,nrf-uarte";
+	current-speed = <115200>;
+	status = "okay";
+	hw-flow-control;
+};
diff --git a/tests/bluetooth/tester/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf b/tests/bluetooth/tester/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..253e0f7d8ac
--- /dev/null
+++ b/tests/bluetooth/tester/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf
@@ -0,0 +1,31 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# CONFIG_TEST enforces minimal logging, which we don't want
+CONFIG_TEST=n
+
+CONFIG_ASSERT=y
+# Enable the option below to measure stack usage
+#CONFIG_INIT_STACKS=y
+CONFIG_THREAD_NAME=y
+CONFIG_HW_STACK_PROTECTION=y
+
+CONFIG_LOG=y
+CONFIG_LOG_BUFFER_SIZE=4096
+CONFIG_RTT_CONSOLE=y
+CONFIG_LOG_BACKEND_RTT=y
+CONFIG_LOG_BACKEND_RTT_MODE_DROP=y
+CONFIG_LOG_BACKEND_RTT_MESSAGE_SIZE=256
+CONFIG_USE_SEGGER_RTT=y
+CONFIG_SEGGER_RTT_BUFFER_SIZE_UP=4096
+CONFIG_LOG_BACKEND_SHOW_COLOR=n
+CONFIG_LOG_PROCESS_THREAD_STACK_SIZE=1024
+
+CONFIG_LOG_DEFAULT_LEVEL=3
+CONFIG_BTTESTER_LOG_LEVEL_DBG=y
+
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+CONFIG_BTTESTER_BTP_CMD_THREAD_STACK_SIZE=3072
diff --git a/tests/bluetooth/tester/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/bluetooth/tester/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..42ea39f77cc
--- /dev/null
+++ b/tests/bluetooth/tester/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,uart-pipe = &uart20;
+	};
+};
+
+&uart20 {
+	compatible = "nordic,nrf-uarte";
+	current-speed = <115200>;
+	status = "okay";
+	hw-flow-control;
+};
diff --git a/tests/bluetooth/tester/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/tests/bluetooth/tester/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
new file mode 100644
index 00000000000..ce22bfb123b
--- /dev/null
+++ b/tests/bluetooth/tester/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,sram = &dtcm;
+		zephyr,uart-pipe = &lpuart1;
+	};
+};
diff --git a/tests/bluetooth/tester/boards/native_sim.conf b/tests/bluetooth/tester/boards/native_sim.conf
index 30abfdbc3d9..9781be36b69 100644
--- a/tests/bluetooth/tester/boards/native_sim.conf
+++ b/tests/bluetooth/tester/boards/native_sim.conf
@@ -1,3 +1,3 @@
 CONFIG_UART_PIPE=n
 CONFIG_SERIAL=y
-CONFIG_UART_NATIVE_POSIX=y
+CONFIG_UART_NATIVE_PTY=y
diff --git a/tests/bluetooth/tester/boards/nrf52_bsim.conf b/tests/bluetooth/tester/boards/nrf52_bsim.conf
new file mode 100644
index 00000000000..b2e5b8763c8
--- /dev/null
+++ b/tests/bluetooth/tester/boards/nrf52_bsim.conf
@@ -0,0 +1,15 @@
+# CONFIG_TEST enforces minimal logging, which we don't want
+CONFIG_TEST=n
+
+CONFIG_ASSERT=y
+CONFIG_THREAD_NAME=y
+
+CONFIG_LOG=y
+CONFIG_LOG_BACKEND_SHOW_COLOR=y
+CONFIG_LOG_FUNC_NAME_PREFIX_ERR=y
+CONFIG_LOG_FUNC_NAME_PREFIX_WRN=y
+
+CONFIG_LOG_DEFAULT_LEVEL=3
+CONFIG_BTTESTER_LOG_LEVEL_DBG=y
+
+CONFIG_UART_PIPE=n
diff --git a/tests/bluetooth/tester/boards/nrf52_bsim.overlay b/tests/bluetooth/tester/boards/nrf52_bsim.overlay
new file mode 100644
index 00000000000..e7c4c36ff5b
--- /dev/null
+++ b/tests/bluetooth/tester/boards/nrf52_bsim.overlay
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+&uart0 {
+	hw-flow-control;
+};
diff --git a/tests/bluetooth/tester/boards/nrf5340bsim_nrf5340_cpuapp.conf b/tests/bluetooth/tester/boards/nrf5340bsim_nrf5340_cpuapp.conf
new file mode 100644
index 00000000000..4acb10d2854
--- /dev/null
+++ b/tests/bluetooth/tester/boards/nrf5340bsim_nrf5340_cpuapp.conf
@@ -0,0 +1,18 @@
+# CONFIG_TEST enforces minimal logging, which we don't want
+CONFIG_TEST=n
+
+CONFIG_ASSERT=y
+CONFIG_THREAD_NAME=y
+
+CONFIG_LOG=y
+CONFIG_LOG_BACKEND_SHOW_COLOR=y
+CONFIG_LOG_FUNC_NAME_PREFIX_ERR=y
+CONFIG_LOG_FUNC_NAME_PREFIX_WRN=y
+
+CONFIG_LOG_DEFAULT_LEVEL=3
+CONFIG_BTTESTER_LOG_LEVEL_DBG=y
+
+CONFIG_UART_PIPE=n
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+CONFIG_SERIAL=y
diff --git a/tests/bluetooth/tester/boards/nrf5340bsim_nrf5340_cpuapp.overlay b/tests/bluetooth/tester/boards/nrf5340bsim_nrf5340_cpuapp.overlay
new file mode 100644
index 00000000000..d43a9a16739
--- /dev/null
+++ b/tests/bluetooth/tester/boards/nrf5340bsim_nrf5340_cpuapp.overlay
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+&uart0 {
+	compatible = "nordic,nrf-uarte";
+	hw-flow-control;
+};
diff --git a/tests/bluetooth/tester/boards/ophelia4ev_nrf54l15_cpuapp.conf b/tests/bluetooth/tester/boards/ophelia4ev_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..b6a71cd1e6d
--- /dev/null
+++ b/tests/bluetooth/tester/boards/ophelia4ev_nrf54l15_cpuapp.conf
@@ -0,0 +1,26 @@
+# CONFIG_TEST enforces minimal logging, which we don't want
+CONFIG_TEST=n
+
+CONFIG_ASSERT=y
+# Enable the option below to measure stack usage
+#CONFIG_INIT_STACKS=y
+CONFIG_THREAD_NAME=y
+CONFIG_HW_STACK_PROTECTION=y
+
+CONFIG_LOG=y
+CONFIG_LOG_BUFFER_SIZE=4096
+CONFIG_RTT_CONSOLE=y
+CONFIG_LOG_BACKEND_RTT=y
+CONFIG_LOG_BACKEND_RTT_MODE_DROP=y
+CONFIG_LOG_BACKEND_RTT_MESSAGE_SIZE=256
+CONFIG_USE_SEGGER_RTT=y
+CONFIG_SEGGER_RTT_BUFFER_SIZE_UP=4096
+CONFIG_LOG_BACKEND_SHOW_COLOR=n
+CONFIG_LOG_PROCESS_THREAD_STACK_SIZE=1024
+
+CONFIG_LOG_DEFAULT_LEVEL=3
+CONFIG_BTTESTER_LOG_LEVEL_DBG=y
+
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+CONFIG_BTTESTER_BTP_CMD_THREAD_STACK_SIZE=3072
diff --git a/tests/bluetooth/tester/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/bluetooth/tester/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..979fa6cc5df
--- /dev/null
+++ b/tests/bluetooth/tester/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+/ {
+	chosen {
+		zephyr,uart-pipe = &uart20;
+	};
+};
+
+&uart20 {
+	compatible = "nordic,nrf-uarte";
+	current-speed = <115200>;
+	status = "okay";
+	hw-flow-control;
+};
diff --git a/tests/bluetooth/tester/boards/panb511evb_nrf54l15_cpuapp.conf b/tests/bluetooth/tester/boards/panb511evb_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..5bb1c4d8284
--- /dev/null
+++ b/tests/bluetooth/tester/boards/panb511evb_nrf54l15_cpuapp.conf
@@ -0,0 +1,24 @@
+# CONFIG_TEST enforces minimal logging, which we don't want
+CONFIG_TEST=n
+
+CONFIG_ASSERT=y
+# Enable the option below to measure stack usage
+#CONFIG_INIT_STACKS=y
+CONFIG_THREAD_NAME=y
+CONFIG_HW_STACK_PROTECTION=y
+
+CONFIG_LOG=y
+CONFIG_LOG_BUFFER_SIZE=4096
+CONFIG_RTT_CONSOLE=y
+CONFIG_LOG_BACKEND_RTT=y
+CONFIG_LOG_BACKEND_RTT_MODE_DROP=y
+CONFIG_LOG_BACKEND_RTT_MESSAGE_SIZE=256
+CONFIG_USE_SEGGER_RTT=y
+CONFIG_SEGGER_RTT_BUFFER_SIZE_UP=4096
+CONFIG_LOG_BACKEND_SHOW_COLOR=n
+CONFIG_LOG_PROCESS_THREAD_STACK_SIZE=1024
+
+CONFIG_LOG_DEFAULT_LEVEL=3
+CONFIG_BTTESTER_LOG_LEVEL_DBG=y
+
+CONFIG_UART_INTERRUPT_DRIVEN=y
diff --git a/tests/bluetooth/tester/boards/panb511evb_nrf54l15_cpuapp.overlay b/tests/bluetooth/tester/boards/panb511evb_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..a179dd8306f
--- /dev/null
+++ b/tests/bluetooth/tester/boards/panb511evb_nrf54l15_cpuapp.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025 Panasonic Industrial Devices Europe GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,uart-pipe = &uart30;
+	};
+};
+
+&uart30 {
+	compatible = "nordic,nrf-uarte";
+	current-speed = <115200>;
+	status = "okay";
+	hw-flow-control;
+};
diff --git a/tests/bluetooth/tester/prj_br.conf b/tests/bluetooth/tester/prj_br.conf
new file mode 100644
index 00000000000..08849ed416c
--- /dev/null
+++ b/tests/bluetooth/tester/prj_br.conf
@@ -0,0 +1,6 @@
+CONFIG_BT_CLASSIC=y
+CONFIG_BT_CENTRAL=y
+CONFIG_BT_PERIPHERAL=y
+CONFIG_BT_SMP=y
+CONFIG_BT_L2CAP_DYNAMIC_CHANNEL=y
+CONFIG_BT_PAGE_TIMEOUT=0xFFFF
diff --git a/tests/bluetooth/tester/src/audio/btp/btp_bap.h b/tests/bluetooth/tester/src/audio/btp/btp_bap.h
index cfce8eb4151..a11299f32e5 100644
--- a/tests/bluetooth/tester/src/audio/btp/btp_bap.h
+++ b/tests/bluetooth/tester/src/audio/btp/btp_bap.h
@@ -216,7 +216,7 @@ struct btp_bap_codec_cap_found_ev {
 } __packed;
 
 #define BTP_BAP_EV_ASE_FOUND			0x82
-struct btp_ascs_ase_found_ev {
+struct btp_bap_ase_found_ev {
 	bt_addr_le_t address;
 	uint8_t dir;
 	uint8_t ase_id;
diff --git a/tests/bluetooth/tester/src/audio/btp/btp_pbp.h b/tests/bluetooth/tester/src/audio/btp/btp_pbp.h
index 614d25e8296..ccb0e866efa 100644
--- a/tests/bluetooth/tester/src/audio/btp/btp_pbp.h
+++ b/tests/bluetooth/tester/src/audio/btp/btp_pbp.h
@@ -34,8 +34,8 @@ struct btp_pbp_broadcast_scan_start_cmd {
 struct btp_pbp_broadcast_scan_stop_cmd {
 } __packed;
 
-#define BTP_PBP_EV_PUBLIC_BROADCAST_ANOUNCEMENT_FOUND 0x80
-struct btp_pbp_ev_public_broadcast_anouncement_found_rp {
+#define BTP_PBP_EV_PUBLIC_BROADCAST_ANNOUNCEMENT_FOUND 0x80
+struct btp_pbp_ev_public_broadcast_announcement_found_ev {
 	bt_addr_le_t address;
 	uint8_t broadcast_id[BT_AUDIO_BROADCAST_ID_SIZE];
 	uint8_t advertiser_sid;
diff --git a/tests/bluetooth/tester/src/audio/btp_aics.c b/tests/bluetooth/tester/src/audio/btp_aics.c
index e3a1ad106df..a2834399f15 100644
--- a/tests/bluetooth/tester/src/audio/btp_aics.c
+++ b/tests/bluetooth/tester/src/audio/btp_aics.c
@@ -39,28 +39,8 @@ static uint8_t aics_supported_commands(const void *cmd, uint16_t cmd_len, void *
 {
 	struct btp_aics_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_AICS_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_AICS_SET_GAIN);
-	tester_set_bit(rp->data, BTP_AICS_MUTE);
-	tester_set_bit(rp->data, BTP_AICS_UNMUTE);
-	tester_set_bit(rp->data, BTP_AICS_MAN_GAIN_SET);
-	tester_set_bit(rp->data, BTP_AICS_AUTO_GAIN_SET);
-	tester_set_bit(rp->data, BTP_AICS_SET_MAN_GAIN_ONLY);
-
-	/* octet 1 */
-	tester_set_bit(rp->data, BTP_AICS_SET_AUTO_GAIN_ONLY);
-	tester_set_bit(rp->data, BTP_AICS_AUDIO_DESCRIPTION_SET);
-	tester_set_bit(rp->data, BTP_AICS_MUTE_DISABLE);
-	tester_set_bit(rp->data, BTP_AICS_GAIN_SETTING_PROP_GET);
-	tester_set_bit(rp->data, BTP_AICS_TYPE_GET);
-	tester_set_bit(rp->data, BTP_AICS_STATUS_GET);
-	tester_set_bit(rp->data, BTP_AICS_STATE_GET);
-
-	/* octet 2 */
-	tester_set_bit(rp->data, BTP_AICS_DESCRIPTION_GET);
-
-	*rsp_len = sizeof(*rp) + 2;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_AICS, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
diff --git a/tests/bluetooth/tester/src/audio/btp_bap.c b/tests/bluetooth/tester/src/audio/btp_bap.c
index c816f654abf..53043abf6ec 100644
--- a/tests/bluetooth/tester/src/audio/btp_bap.c
+++ b/tests/bluetooth/tester/src/audio/btp_bap.c
@@ -65,10 +65,8 @@ static uint8_t btp_ascs_supported_commands(const void *cmd, uint16_t cmd_len,
 {
 	struct btp_ascs_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_ASCS_READ_SUPPORTED_COMMANDS);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_ASCS, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
@@ -196,14 +194,8 @@ static uint8_t pacs_supported_commands(const void *cmd, uint16_t cmd_len,
 {
 	struct btp_pacs_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_PACS_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_PACS_UPDATE_CHARACTERISTIC);
-	tester_set_bit(rp->data, BTP_PACS_SET_LOCATION);
-	tester_set_bit(rp->data, BTP_PACS_SET_AVAILABLE_CONTEXTS);
-	tester_set_bit(rp->data, BTP_PACS_SET_SUPPORTED_CONTEXTS);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_PACS, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
@@ -330,12 +322,8 @@ static uint8_t btp_bap_supported_commands(const void *cmd, uint16_t cmd_len,
 {
 	struct btp_bap_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_BAP_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_BAP_DISCOVER);
-	tester_set_bit(rp->data, BTP_BAP_SEND);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_BAP, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
@@ -487,8 +475,29 @@ static const struct btp_handler bap_handlers[] = {
 
 uint8_t tester_init_pacs(void)
 {
+	const struct bt_pacs_register_param pacs_param = {
+#if defined(CONFIG_BT_PAC_SNK)
+		.snk_pac = true,
+#endif /* CONFIG_BT_PAC_SNK */
+#if defined(CONFIG_BT_PAC_SNK_LOC)
+		.snk_loc = true,
+#endif /* CONFIG_BT_PAC_SNK_LOC */
+#if defined(CONFIG_BT_PAC_SRC)
+		.src_pac = true,
+#endif /* CONFIG_BT_PAC_SRC */
+#if defined(CONFIG_BT_PAC_SRC_LOC)
+		.src_loc = true,
+#endif /* CONFIG_BT_PAC_SRC_LOC */
+	};
 	int err;
 
+	/* PACS shall be registered before ASCS in btp_bap_unicast_init */
+	err = bt_pacs_register(&pacs_param);
+	if (err != 0) {
+		LOG_DBG("Failed to register client callbacks: %d", err);
+		return BTP_STATUS_FAILED;
+	}
+
 	btp_bap_unicast_init();
 
 	bt_pacs_cap_register(BT_AUDIO_DIR_SINK, &cap_sink);
diff --git a/tests/bluetooth/tester/src/audio/btp_bap_broadcast.c b/tests/bluetooth/tester/src/audio/btp_bap_broadcast.c
index f42eaa2340c..2ce5afbcecf 100644
--- a/tests/bluetooth/tester/src/audio/btp_bap_broadcast.c
+++ b/tests/bluetooth/tester/src/audio/btp_bap_broadcast.c
@@ -88,7 +88,7 @@ static int btp_bap_broadcast_local_source_free(struct btp_bap_broadcast_local_so
 		return -EINVAL;
 	}
 
-	memset(&source, 0, sizeof(*source));
+	memset(source, 0, sizeof(*source));
 
 	return 0;
 }
@@ -252,7 +252,7 @@ static void stream_recv(struct bt_bap_stream *stream,
 		LOG_DBG("Incoming audio on stream %p len %u flags 0x%02X seq_num %u and ts %u",
 			stream, buf->len, info->flags, info->seq_num, info->ts);
 
-		if ((info->flags & BT_ISO_FLAGS_VALID) == 0) {
+		if ((info->flags & BT_ISO_FLAGS_VALID) != 0) {
 			b_stream->already_sent = true;
 			broadcaster = &remote_broadcast_sources[b_stream->source_id];
 			send_bis_stream_received_ev(&broadcaster->address,
@@ -474,7 +474,7 @@ uint8_t btp_bap_broadcast_source_setup(const void *cmd, uint16_t cmd_len,
 
 	rp->gap_settings = gap_settings;
 	sys_put_le24(broadcast_id, rp->broadcast_id);
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
@@ -589,7 +589,7 @@ uint8_t btp_bap_broadcast_source_setup_v2(const void *cmd, uint16_t cmd_len,
 	}
 
 	rp->gap_settings = gap_settings;
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
diff --git a/tests/bluetooth/tester/src/audio/btp_bap_unicast.c b/tests/bluetooth/tester/src/audio/btp_bap_unicast.c
index 2df4e72ca85..ec1e6899ee7 100644
--- a/tests/bluetooth/tester/src/audio/btp_bap_unicast.c
+++ b/tests/bluetooth/tester/src/audio/btp_bap_unicast.c
@@ -258,7 +258,7 @@ static void btp_send_pac_codec_found_ev(struct bt_conn *conn,
 static void btp_send_ase_found_ev(struct bt_conn *conn, struct bt_bap_ep *ep)
 {
 	struct bt_bap_ep_info info;
-	struct btp_ascs_ase_found_ev ev;
+	struct btp_bap_ase_found_ev ev;
 
 	bt_addr_le_copy(&ev.address, bt_conn_get_dst(conn));
 
@@ -715,7 +715,7 @@ static void stream_recv(struct bt_bap_stream *stream,
 		LOG_DBG("Incoming audio on stream %p len %u flags 0x%02X seq_num %u and ts %u",
 			stream, buf->len, info->flags, info->seq_num, info->ts);
 
-		if ((info->flags & BT_ISO_FLAGS_VALID) == 0) {
+		if ((info->flags & BT_ISO_FLAGS_VALID) != 0) {
 			u_stream->already_sent = true;
 			send_stream_received_ev(stream->conn, stream->ep, buf->len, buf->data);
 		}
diff --git a/tests/bluetooth/tester/src/audio/btp_cap.c b/tests/bluetooth/tester/src/audio/btp_cap.c
index a847e8e0658..bb28da9c13b 100644
--- a/tests/bluetooth/tester/src/audio/btp_cap.c
+++ b/tests/bluetooth/tester/src/audio/btp_cap.c
@@ -173,11 +173,8 @@ static uint8_t btp_cap_supported_commands(const void *cmd, uint16_t cmd_len,
 {
 	struct btp_cap_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_CAP_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_CAP_DISCOVER);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_CAP, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
diff --git a/tests/bluetooth/tester/src/audio/btp_cas.c b/tests/bluetooth/tester/src/audio/btp_cas.c
index 78e3a8f2878..fc05527d585 100644
--- a/tests/bluetooth/tester/src/audio/btp_cas.c
+++ b/tests/bluetooth/tester/src/audio/btp_cas.c
@@ -22,12 +22,8 @@ static uint8_t cas_supported_commands(const void *cmd, uint16_t cmd_len,
 {
 	struct btp_cas_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_CAS_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_CAS_SET_MEMBER_LOCK);
-	tester_set_bit(rp->data, BTP_CAS_GET_MEMBER_RSI);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_CAS, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
diff --git a/tests/bluetooth/tester/src/audio/btp_ccp.c b/tests/bluetooth/tester/src/audio/btp_ccp.c
index ac1965ab3a9..eaedee150fe 100644
--- a/tests/bluetooth/tester/src/audio/btp_ccp.c
+++ b/tests/bluetooth/tester/src/audio/btp_ccp.c
@@ -28,38 +28,8 @@ static uint8_t ccp_supported_commands(const void *cmd, uint16_t cmd_len,
 {
 	struct btp_ccp_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_CCP_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_CCP_DISCOVER_TBS);
-	tester_set_bit(rp->data, BTP_CCP_ACCEPT_CALL);
-	tester_set_bit(rp->data, BTP_CCP_TERMINATE_CALL);
-	tester_set_bit(rp->data, BTP_CCP_ORIGINATE_CALL);
-	tester_set_bit(rp->data, BTP_CCP_READ_CALL_STATE);
-	tester_set_bit(rp->data, BTP_CCP_READ_BEARER_NAME);
-
-	/* octet 1 */
-	tester_set_bit(rp->data, BTP_CCP_READ_BEARER_UCI);
-	tester_set_bit(rp->data, BTP_CCP_READ_BEARER_TECH);
-	tester_set_bit(rp->data, BTP_CCP_READ_URI_LIST);
-	tester_set_bit(rp->data, BTP_CCP_READ_SIGNAL_STRENGTH);
-	tester_set_bit(rp->data, BTP_CCP_READ_SIGNAL_INTERVAL);
-	tester_set_bit(rp->data, BTP_CCP_READ_CURRENT_CALLS);
-	tester_set_bit(rp->data, BTP_CCP_READ_CCID);
-
-	/* octet 2 */
-	tester_set_bit(rp->data, BTP_CCP_READ_CALL_URI);
-	tester_set_bit(rp->data, BTP_CCP_READ_STATUS_FLAGS);
-	tester_set_bit(rp->data, BTP_CCP_READ_OPTIONAL_OPCODES);
-	tester_set_bit(rp->data, BTP_CCP_READ_FRIENDLY_NAME);
-	tester_set_bit(rp->data, BTP_CCP_READ_REMOTE_URI);
-	tester_set_bit(rp->data, BTP_CCP_SET_SIGNAL_INTERVAL);
-	tester_set_bit(rp->data, BTP_CCP_HOLD_CALL);
-
-	/* octet 3 */
-	tester_set_bit(rp->data, BTP_CCP_RETRIEVE_CALL);
-	tester_set_bit(rp->data, BTP_CCP_JOIN_CALLS);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_CCP, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
@@ -886,21 +856,8 @@ static uint8_t tbs_supported_commands(const void *cmd, uint16_t cmd_len, void *r
 {
 	struct btp_tbs_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_TBS_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_TBS_REMOTE_INCOMING);
-	tester_set_bit(rp->data, BTP_TBS_HOLD);
-	tester_set_bit(rp->data, BTP_TBS_SET_BEARER_NAME);
-	tester_set_bit(rp->data, BTP_TBS_SET_TECHNOLOGY);
-	tester_set_bit(rp->data, BTP_TBS_SET_URI_SCHEME);
-	tester_set_bit(rp->data, BTP_TBS_SET_STATUS_FLAGS);
-
-	/* octet 1 */
-	tester_set_bit(rp->data, BTP_TBS_REMOTE_HOLD);
-	tester_set_bit(rp->data, BTP_TBS_ORIGINATE);
-	tester_set_bit(rp->data, BTP_TBS_SET_SIGNAL_STRENGTH);
-
-	*rsp_len = sizeof(*rp) + 2;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_TBS, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
diff --git a/tests/bluetooth/tester/src/audio/btp_csip.c b/tests/bluetooth/tester/src/audio/btp_csip.c
index f7068e13b21..e798d2c6e38 100644
--- a/tests/bluetooth/tester/src/audio/btp_csip.c
+++ b/tests/bluetooth/tester/src/audio/btp_csip.c
@@ -23,14 +23,8 @@ static uint8_t btp_csip_supported_commands(const void *cmd, uint16_t cmd_len,
 {
 	struct btp_csip_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_CSIP_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_CSIP_DISCOVER);
-	tester_set_bit(rp->data, BTP_CSIP_START_ORDERED_ACCESS);
-	tester_set_bit(rp->data, BTP_CSIP_SET_COORDINATOR_LOCK);
-	tester_set_bit(rp->data, BTP_CSIP_SET_COORDINATOR_RELEASE);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_CSIP, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
diff --git a/tests/bluetooth/tester/src/audio/btp_csis.c b/tests/bluetooth/tester/src/audio/btp_csis.c
index 8c8d09eaea7..b13154c24c3 100644
--- a/tests/bluetooth/tester/src/audio/btp_csis.c
+++ b/tests/bluetooth/tester/src/audio/btp_csis.c
@@ -24,13 +24,8 @@ static uint8_t csis_supported_commands(const void *cmd, uint16_t cmd_len,
 {
 	struct btp_csis_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_CSIS_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_CSIS_SET_MEMBER_LOCK);
-	tester_set_bit(rp->data, BTP_CSIS_GET_MEMBER_RSI);
-	tester_set_bit(rp->data, BTP_CSIS_ENC_SIRK_TYPE);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_CSIS, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
diff --git a/tests/bluetooth/tester/src/audio/btp_hap.c b/tests/bluetooth/tester/src/audio/btp_hap.c
index 88dba7e8fbb..628058816da 100644
--- a/tests/bluetooth/tester/src/audio/btp_hap.c
+++ b/tests/bluetooth/tester/src/audio/btp_hap.c
@@ -23,15 +23,8 @@ static uint8_t read_supported_commands(const void *cmd, uint16_t cmd_len, void *
 {
 	struct btp_hap_read_supported_commands_rp *rp = rsp;
 
-	tester_set_bit(rp->data, BTP_HAP_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_HAP_HA_INIT);
-	tester_set_bit(rp->data, BTP_HAP_HAUC_INIT);
-	tester_set_bit(rp->data, BTP_HAP_IAC_INIT);
-	tester_set_bit(rp->data, BTP_HAP_IAC_DISCOVER);
-	tester_set_bit(rp->data, BTP_HAP_IAC_SET_ALERT);
-	tester_set_bit(rp->data, BTP_HAP_HAUC_DISCOVER);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_HAP, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
diff --git a/tests/bluetooth/tester/src/audio/btp_has.c b/tests/bluetooth/tester/src/audio/btp_has.c
index d90a635377a..1ffd71536ee 100644
--- a/tests/bluetooth/tester/src/audio/btp_has.c
+++ b/tests/bluetooth/tester/src/audio/btp_has.c
@@ -21,14 +21,8 @@ static uint8_t has_supported_commands(const void *cmd, uint16_t cmd_len,
 {
 	struct btp_has_read_supported_commands_rp *rp = rsp;
 
-	tester_set_bit(rp->data, BTP_HAS_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_HAS_SET_ACTIVE_INDEX);
-	tester_set_bit(rp->data, BTP_HAS_SET_PRESET_NAME);
-	tester_set_bit(rp->data, BTP_HAS_REMOVE_PRESET);
-	tester_set_bit(rp->data, BTP_HAS_ADD_PRESET);
-	tester_set_bit(rp->data, BTP_HAS_SET_PROPERTIES);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_HAS, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
diff --git a/tests/bluetooth/tester/src/audio/btp_mcp.c b/tests/bluetooth/tester/src/audio/btp_mcp.c
index a31a5be30a6..22c709c427c 100644
--- a/tests/bluetooth/tester/src/audio/btp_mcp.c
+++ b/tests/bluetooth/tester/src/audio/btp_mcp.c
@@ -662,40 +662,8 @@ static uint8_t mcp_supported_commands(const void *cmd, uint16_t cmd_len, void *r
 {
 	struct btp_mcp_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_MCP_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_MCP_DISCOVER);
-	tester_set_bit(rp->data, BTP_MCP_TRACK_DURATION_READ);
-	tester_set_bit(rp->data, BTP_MCP_TRACK_POSITION_READ);
-	tester_set_bit(rp->data, BTP_MCP_TRACK_POSITION_SET);
-	tester_set_bit(rp->data, BTP_MCP_PLAYBACK_SPEED_READ);
-	tester_set_bit(rp->data, BTP_MCP_PLAYBACK_SPEED_SET);
-
-	/* octet 1 */
-	tester_set_bit(rp->data, BTP_MCP_SEEKING_SPEED_READ);
-	tester_set_bit(rp->data, BTP_MCP_ICON_OBJ_ID_READ);
-	tester_set_bit(rp->data, BTP_MCP_NEXT_TRACK_OBJ_ID_READ);
-	tester_set_bit(rp->data, BTP_MCP_NEXT_TRACK_OBJ_ID_SET);
-	tester_set_bit(rp->data, BTP_MCP_PARENT_GROUP_OBJ_ID_READ);
-	tester_set_bit(rp->data, BTP_MCP_CURRENT_GROUP_OBJ_ID_READ);
-	tester_set_bit(rp->data, BTP_MCP_CURRENT_GROUP_OBJ_ID_SET);
-
-	/* octet 2 */
-	tester_set_bit(rp->data, BTP_MCP_PLAYING_ORDER_READ);
-	tester_set_bit(rp->data, BTP_MCP_PLAYING_ORDER_SET);
-	tester_set_bit(rp->data, BTP_MCP_PLAYING_ORDERS_SUPPORTED_READ);
-	tester_set_bit(rp->data, BTP_MCP_MEDIA_STATE_READ);
-	tester_set_bit(rp->data, BTP_MCP_OPCODES_SUPPORTED_READ);
-	tester_set_bit(rp->data, BTP_MCP_CONTENT_CONTROL_ID_READ);
-	tester_set_bit(rp->data, BTP_MCP_SEGMENTS_OBJ_ID_READ);
-
-	/* octet 3 */
-	tester_set_bit(rp->data, BTP_MCP_CURRENT_TRACK_OBJ_ID_READ);
-	tester_set_bit(rp->data, BTP_MCP_CURRENT_TRACK_OBJ_ID_SET);
-	tester_set_bit(rp->data, BTP_MCP_CMD_SEND);
-	tester_set_bit(rp->data, BTP_MCP_CMD_SEARCH);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_MCP, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
@@ -1462,15 +1430,8 @@ static uint8_t mcs_supported_commands(const void *cmd, uint16_t cmd_len, void *r
 {
 	struct btp_mcs_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_MCS_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_MCS_CMD_SEND);
-	tester_set_bit(rp->data, BTP_MCS_CURRENT_TRACK_OBJ_ID_GET);
-	tester_set_bit(rp->data, BTP_MCS_NEXT_TRACK_OBJ_ID_GET);
-	tester_set_bit(rp->data, BTP_MCS_INACTIVE_STATE_SET);
-	tester_set_bit(rp->data, BTP_MCS_PARENT_GROUP_SET);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_GMCS, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
diff --git a/tests/bluetooth/tester/src/audio/btp_micp.c b/tests/bluetooth/tester/src/audio/btp_micp.c
index 4ead39ca179..ced87ac5822 100644
--- a/tests/bluetooth/tester/src/audio/btp_micp.c
+++ b/tests/bluetooth/tester/src/audio/btp_micp.c
@@ -99,7 +99,6 @@ static void micp_mic_ctlr_mute_written_cb(struct bt_micp_mic_ctlr *mic_ctlr, int
 	struct bt_conn *conn;
 
 	bt_micp_mic_ctlr_conn_get(mic_ctlr, &conn);
-	btp_send_micp_mute_state_ev(conn, err, mute_state);
 
 	LOG_DBG("MICP Mute Written cb (%d))", err);
 }
@@ -109,7 +108,6 @@ static void micp_mic_ctlr_unmute_written_cb(struct bt_micp_mic_ctlr *mic_ctlr, i
 	struct bt_conn *conn;
 
 	bt_micp_mic_ctlr_conn_get(mic_ctlr, &conn);
-	btp_send_micp_mute_state_ev(conn, err, mute_state);
 
 	LOG_DBG("MICP Mute Unwritten cb (%d))", err);
 }
@@ -163,13 +161,8 @@ static uint8_t micp_supported_commands(const void *cmd, uint16_t cmd_len, void *
 {
 	struct btp_micp_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_MICP_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_MICP_CTLR_DISCOVER);
-	tester_set_bit(rp->data, BTP_MICP_CTLR_MUTE_READ);
-	tester_set_bit(rp->data, BTP_MICP_CTLR_MUTE);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_MICP, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
@@ -276,14 +269,8 @@ static uint8_t mics_supported_commands(const void *cmd, uint16_t cmd_len, void *
 {
 	struct btp_mics_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_MICS_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_MICS_DEV_MUTE_DISABLE);
-	tester_set_bit(rp->data, BTP_MICS_DEV_MUTE_READ);
-	tester_set_bit(rp->data, BTP_MICS_DEV_MUTE);
-	tester_set_bit(rp->data, BTP_MICS_DEV_UNMUTE);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_MICS, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
diff --git a/tests/bluetooth/tester/src/audio/btp_pbp.c b/tests/bluetooth/tester/src/audio/btp_pbp.c
index 7906b8f3762..6fca9a6dc87 100644
--- a/tests/bluetooth/tester/src/audio/btp_pbp.c
+++ b/tests/bluetooth/tester/src/audio/btp_pbp.c
@@ -45,7 +45,7 @@ static bool scan_get_data(struct bt_data *data, void *user_data)
 	uint32_t broadcast_id;
 	uint8_t *metadata;
 	struct bt_uuid_16 adv_uuid;
-	struct btp_pbp_ev_public_broadcast_anouncement_found_rp *ev = user_data;
+	struct btp_pbp_ev_public_broadcast_announcement_found_ev *ev = user_data;
 
 	switch (data->type) {
 	case BT_DATA_BROADCAST_NAME:
@@ -89,7 +89,7 @@ static void pbp_scan_recv(const struct bt_le_scan_recv_info *info, struct net_bu
 	net_buf_simple_clone(ad, &ad_copy);
 	bt_data_parse(&ad_copy, scan_get_broadcast_name_len, &broadcast_name_len);
 
-	struct btp_pbp_ev_public_broadcast_anouncement_found_rp *ev_ptr;
+	struct btp_pbp_ev_public_broadcast_announcement_found_ev *ev_ptr;
 
 	tester_rsp_buffer_lock();
 	tester_rsp_buffer_allocate(sizeof(*ev_ptr) + broadcast_name_len, (uint8_t **)&ev_ptr);
@@ -105,7 +105,7 @@ static void pbp_scan_recv(const struct bt_le_scan_recv_info *info, struct net_bu
 
 	if (sys_get_le24(ev_ptr->broadcast_id) != BT_BAP_INVALID_BROADCAST_ID &&
 	    ev_ptr->pba_features != 0U && ev_ptr->broadcast_name_len > 0) {
-		tester_event(BTP_SERVICE_ID_PBP, BTP_PBP_EV_PUBLIC_BROADCAST_ANOUNCEMENT_FOUND,
+		tester_event(BTP_SERVICE_ID_PBP, BTP_PBP_EV_PUBLIC_BROADCAST_ANNOUNCEMENT_FOUND,
 			     ev_ptr, sizeof(*ev_ptr) + broadcast_name_len);
 	}
 
@@ -122,13 +122,8 @@ static uint8_t pbp_read_supported_commands(const void *cmd, uint16_t cmd_len, vo
 {
 	struct btp_pbp_read_supported_commands_rp *rp = rsp;
 
-	tester_set_bit(rp->data, BTP_PBP_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_PBP_SET_PUBLIC_BROADCAST_ANNOUNCEMENT);
-	tester_set_bit(rp->data, BTP_PBP_SET_BROADCAST_NAME);
-	tester_set_bit(rp->data, BTP_PBP_BROADCAST_SCAN_START);
-	tester_set_bit(rp->data, BTP_PBP_BROADCAST_SCAN_STOP);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_PBP, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
diff --git a/tests/bluetooth/tester/src/audio/btp_tmap.c b/tests/bluetooth/tester/src/audio/btp_tmap.c
index 765b945c4a8..1011eac2ac6 100644
--- a/tests/bluetooth/tester/src/audio/btp_tmap.c
+++ b/tests/bluetooth/tester/src/audio/btp_tmap.c
@@ -19,10 +19,8 @@ static uint8_t read_supported_commands(const void *cmd, uint16_t cmd_len, void *
 {
 	struct btp_tmap_read_supported_commands_rp *rp = rsp;
 
-	tester_set_bit(rp->data, BTP_TMAP_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_TMAP_DISCOVER);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_TMAP, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
diff --git a/tests/bluetooth/tester/src/audio/btp_vcp.c b/tests/bluetooth/tester/src/audio/btp_vcp.c
index b6b3c517534..e31e5edac21 100644
--- a/tests/bluetooth/tester/src/audio/btp_vcp.c
+++ b/tests/bluetooth/tester/src/audio/btp_vcp.c
@@ -68,15 +68,8 @@ static uint8_t vcs_supported_commands(const void *cmd, uint16_t cmd_len,
 {
 	struct btp_vcs_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_VCS_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_VCS_SET_VOL);
-	tester_set_bit(rp->data, BTP_VCS_VOL_UP);
-	tester_set_bit(rp->data, BTP_VCS_VOL_DOWN);
-	tester_set_bit(rp->data, BTP_VCS_MUTE);
-	tester_set_bit(rp->data, BTP_VCS_UNMUTE);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_VCS, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
@@ -198,15 +191,8 @@ static uint8_t vocs_supported_commands(const void *cmd, uint16_t cmd_len,
 {
 	struct btp_vocs_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_VOCS_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_VOCS_UPDATE_LOC);
-	tester_set_bit(rp->data, BTP_VOCS_UPDATE_DESC);
-	tester_set_bit(rp->data, BTP_VOCS_STATE_GET);
-	tester_set_bit(rp->data, BTP_VOCS_LOCATION_GET);
-	tester_set_bit(rp->data, BTP_VOCS_OFFSET_STATE_SET);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_VOCS, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
@@ -623,22 +609,8 @@ static uint8_t vcp_supported_commands(const void *cmd, uint16_t cmd_len,
 {
 	struct btp_vcp_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_VCP_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_VCP_VOL_CTLR_DISCOVER);
-	tester_set_bit(rp->data, BTP_VCP_VOL_CTLR_STATE_READ);
-	tester_set_bit(rp->data, BTP_VCP_VOL_CTLR_FLAGS_READ);
-	tester_set_bit(rp->data, BTP_VCP_VOL_CTLR_VOL_DOWN);
-	tester_set_bit(rp->data, BTP_VCP_VOL_CTLR_VOL_UP);
-	tester_set_bit(rp->data, BTP_VCP_VOL_CTLR_UNMUTE_VOL_DOWN);
-
-	/* octet 1 */
-	tester_set_bit(rp->data, BTP_VCP_VOL_CTLR_UNMUTE_VOL_UP);
-	tester_set_bit(rp->data, BTP_VCP_VOL_CTLR_SET_VOL);
-	tester_set_bit(rp->data, BTP_VCP_VOL_CTLR_UNMUTE);
-	tester_set_bit(rp->data, BTP_VCP_VOL_CTLR_MUTE);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_VCP, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
diff --git a/tests/bluetooth/tester/src/btp.c b/tests/bluetooth/tester/src/btp.c
index 3951ea0aee1..da8a2826409 100644
--- a/tests/bluetooth/tester/src/btp.c
+++ b/tests/bluetooth/tester/src/btp.c
@@ -6,19 +6,27 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
-
-#include <zephyr/kernel.h>
+#include <errno.h>
 #include <stdio.h>
+#include <stdint.h>
 #include <string.h>
-#include <zephyr/types.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/device.h>
 #include <zephyr/drivers/uart.h>
-#include <zephyr/toolchain.h>
-#include <zephyr/bluetooth/bluetooth.h>
-#include <zephyr/sys/byteorder.h>
 #include <zephyr/drivers/uart_pipe.h>
-
+#include <zephyr/kernel.h>
+#include <zephyr/kernel/thread_stack.h>
 #include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/__assert.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/toolchain.h>
+#include <zephyr/types.h>
+
 #define LOG_MODULE_NAME bttester
 LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_BTTESTER_LOG_LEVEL);
 
@@ -276,6 +284,7 @@ void tester_rsp_buffer_allocate(size_t len, uint8_t **data)
 	*data = net_buf_simple_add(rsp_buf, len);
 }
 
+K_MUTEX_DEFINE(uart_mutex);
 static void tester_send_with_index(uint8_t service, uint8_t opcode, uint8_t index,
 				   const uint8_t *data, size_t len)
 {
@@ -286,10 +295,12 @@ static void tester_send_with_index(uint8_t service, uint8_t opcode, uint8_t inde
 	msg.index = index;
 	msg.len = sys_cpu_to_le16(len);
 
+	k_mutex_lock(&uart_mutex, K_FOREVER);
 	uart_send((uint8_t *)&msg, sizeof(msg));
 	if (data && len) {
 		uart_send(data, len);
 	}
+	k_mutex_unlock(&uart_mutex);
 }
 
 static void tester_rsp_with_index(uint8_t service, uint8_t opcode, uint8_t index,
@@ -353,3 +364,23 @@ void tester_rsp(uint8_t service, uint8_t opcode, uint8_t status)
 	(void)memset(cmd, 0, sizeof(*cmd));
 	k_fifo_put(&avail_queue, cmd);
 }
+
+uint16_t tester_supported_commands(uint8_t service, uint8_t *cmds)
+{
+	uint8_t opcode_max = 0;
+
+	__ASSERT_NO_MSG(service <= BTP_SERVICE_ID_MAX);
+
+	for (size_t i = 0; i < service_handler[service].num; i++) {
+		const struct btp_handler *handler = &service_handler[service].handlers[i];
+
+		tester_set_bit(cmds, handler->opcode);
+
+		if (handler->opcode > opcode_max) {
+			opcode_max = handler->opcode;
+		}
+	}
+
+	/* bytes used to store supported commands bitmask */
+	return (opcode_max / 8) + 1;
+}
diff --git a/tests/bluetooth/tester/src/btp/btp.h b/tests/bluetooth/tester/src/btp/btp.h
index 06dc0788398..5308415195a 100644
--- a/tests/bluetooth/tester/src/btp/btp.h
+++ b/tests/bluetooth/tester/src/btp/btp.h
@@ -7,8 +7,10 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/sys/util.h>
-#include <zephyr/bluetooth/addr.h>
+#ifndef TESTS_BLUETOOTH_TESTER_SRC_BTP_
+#define TESTS_BLUETOOTH_TESTER_SRC_BTP_
+
+#include <stdint.h>
 
 #include "bttester.h"
 #include "btp_core.h"
@@ -43,6 +45,8 @@
 #define BTP_MTU 1024
 #define BTP_DATA_MAX_SIZE (BTP_MTU - sizeof(struct btp_hdr))
 
+#define BTP_BR_ADDRESS_TYPE 0xe0
+
 #define BTP_INDEX_NONE		0xff
 #define BTP_INDEX		0x00
 
@@ -87,6 +91,8 @@
 
 #define BTP_STATUS_VAL(err) (err) ? BTP_STATUS_FAILED : BTP_STATUS_SUCCESS
 
+#define BTP_EVENT_OPCODE 0x80
+
 /* TODO indicate delay response, should be removed when all commands are
  * converted to cmd+status+ev pattern
  */
@@ -104,3 +110,5 @@ struct btp_hdr {
 struct btp_status {
 	uint8_t code;
 } __packed;
+
+#endif /* TESTS_BLUETOOTH_TESTER_SRC_BTP_ */
diff --git a/tests/bluetooth/tester/src/btp/btp_core.h b/tests/bluetooth/tester/src/btp/btp_core.h
index c31b7f8dee6..9b4f1a88d40 100644
--- a/tests/bluetooth/tester/src/btp/btp_core.h
+++ b/tests/bluetooth/tester/src/btp/btp_core.h
@@ -7,8 +7,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/sys/util.h>
-#include <zephyr/bluetooth/addr.h>
+#include <stdint.h>
 
 /* Core Service */
 #define BTP_CORE_READ_SUPPORTED_COMMANDS	0x01
diff --git a/tests/bluetooth/tester/src/btp/btp_gap.h b/tests/bluetooth/tester/src/btp/btp_gap.h
index 4ae2e53f8a2..e6002a82a40 100644
--- a/tests/bluetooth/tester/src/btp/btp_gap.h
+++ b/tests/bluetooth/tester/src/btp/btp_gap.h
@@ -7,7 +7,9 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/sys/util.h>
+#include <stddef.h>
+#include <stdint.h>
+
 #include <zephyr/bluetooth/addr.h>
 
 /* GAP Service */
@@ -319,6 +321,34 @@ struct btp_gap_padv_sync_transfer_recv_cmd {
 	uint8_t flags;
 } __packed;
 
+#define BTP_GAP_PAIR_V2_MODE_1			0x01
+#define BTP_GAP_PAIR_V2_MODE_2			0x02
+#define BTP_GAP_PAIR_V2_MODE_3			0x03
+#define BTP_GAP_PAIR_V2_MODE_4			0x04
+#define BTP_GAP_PAIR_V2_MODE_ANY		0xFF
+
+#define BTP_GAP_PAIR_V2_LEVEL_0			0x00
+#define BTP_GAP_PAIR_V2_LEVEL_1			0x01
+#define BTP_GAP_PAIR_V2_LEVEL_2			0x02
+#define BTP_GAP_PAIR_V2_LEVEL_3			0x03
+#define BTP_GAP_PAIR_V2_LEVEL_4			0x04
+#define BTP_GAP_PAIR_V2_LEVEL_ANY		0xFF
+
+#define BTP_GAP_PAIR_V2_FLAG_FORCE_PAIR		BIT(0)
+
+#define BTP_GAP_PAIR_V2				0x2A
+struct btp_gap_pair_v2_cmd {
+	bt_addr_le_t address;
+	uint8_t mode;
+	uint8_t level;
+	uint8_t flags;
+} __packed;
+
+#define BTP_GAP_SET_RPA_TIMEOUT                 0x30
+struct btp_gap_set_rpa_timeout_cmd {
+	uint16_t rpa_timeout;
+} __packed;
+
 /* events */
 #define BTP_GAP_EV_NEW_SETTINGS			0x80
 struct btp_gap_new_settings_ev {
@@ -443,6 +473,13 @@ struct btp_gap_ev_periodic_transfer_received_ev {
 	uint8_t data[];
 } __packed;
 
+#define BTP_GAP_EV_ENCRYPTION_CHANGE		0x91
+struct btp_gap_encryption_change_ev {
+	bt_addr_le_t address;
+	uint8_t enabled;
+	uint8_t key_size;
+} __packed;
+
 #if defined(CONFIG_BT_EXT_ADV)
 struct bt_le_per_adv_param;
 struct bt_le_per_adv_sync_param;
diff --git a/tests/bluetooth/tester/src/btp/btp_gatt.h b/tests/bluetooth/tester/src/btp/btp_gatt.h
index c22bc748229..e26b3767b6a 100644
--- a/tests/bluetooth/tester/src/btp/btp_gatt.h
+++ b/tests/bluetooth/tester/src/btp/btp_gatt.h
@@ -7,7 +7,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/sys/util.h>
+#include <stdint.h>
+
 #include <zephyr/bluetooth/addr.h>
 
 /* GATT Service */
diff --git a/tests/bluetooth/tester/src/btp/btp_ias.h b/tests/bluetooth/tester/src/btp/btp_ias.h
index a2af9d35f59..007239bd01c 100644
--- a/tests/bluetooth/tester/src/btp/btp_ias.h
+++ b/tests/bluetooth/tester/src/btp/btp_ias.h
@@ -6,7 +6,6 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/bluetooth/services/ias.h>
 #include <stdint.h>
 
 /* events */
diff --git a/tests/bluetooth/tester/src/btp/btp_l2cap.h b/tests/bluetooth/tester/src/btp/btp_l2cap.h
index d08a89fba85..a5bd3959910 100644
--- a/tests/bluetooth/tester/src/btp/btp_l2cap.h
+++ b/tests/bluetooth/tester/src/btp/btp_l2cap.h
@@ -7,7 +7,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/sys/util.h>
+#include <stdint.h>
+
 #include <zephyr/bluetooth/addr.h>
 
 /* L2CAP Service */
@@ -53,6 +54,7 @@ struct btp_l2cap_send_data_cmd {
 #define BTP_L2CAP_CONNECTION_RESPONSE_INSUFF_AUTHOR	0x02
 #define BTP_L2CAP_CONNECTION_RESPONSE_INSUFF_ENC_KEY	0x03
 #define BTP_L2CAP_CONNECTION_RESPONSE_INSUFF_ENCRYPTION 0x04
+#define BTP_L2CAP_CONNECTION_RESPONSE_INSUFF_SEC_AUTHEN	0x05
 
 #define BTP_L2CAP_LISTEN				0x05
 struct btp_l2cap_listen_cmd {
diff --git a/tests/bluetooth/tester/src/btp/btp_mesh.h b/tests/bluetooth/tester/src/btp/btp_mesh.h
index 6a8e54f9f14..7f197e907cd 100644
--- a/tests/bluetooth/tester/src/btp/btp_mesh.h
+++ b/tests/bluetooth/tester/src/btp/btp_mesh.h
@@ -7,8 +7,10 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/sys/util.h>
+#include <stdint.h>
+
 #include <zephyr/bluetooth/addr.h>
+#include <zephyr/sys/util_macro.h>
 
 /* MESH Service */
 /* commands */
diff --git a/tests/bluetooth/tester/src/btp/btp_ots.h b/tests/bluetooth/tester/src/btp/btp_ots.h
index ae6900eb0f5..be2f2fab488 100644
--- a/tests/bluetooth/tester/src/btp/btp_ots.h
+++ b/tests/bluetooth/tester/src/btp/btp_ots.h
@@ -6,6 +6,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <stdint.h>
+
 /* OTS commands */
 #define BTP_OTS_READ_SUPPORTED_COMMANDS	0x01
 struct btp_ots_read_supported_commands_rp {
diff --git a/tests/bluetooth/tester/src/btp/bttester.h b/tests/bluetooth/tester/src/btp/bttester.h
index c43725a0aaf..b3c16272168 100644
--- a/tests/bluetooth/tester/src/btp/bttester.h
+++ b/tests/bluetooth/tester/src/btp/bttester.h
@@ -7,9 +7,11 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/types.h>
-#include <zephyr/sys/util.h>
+#include <stddef.h>
+#include <stdint.h>
+
 #include <zephyr/bluetooth/addr.h>
+#include <zephyr/sys/util_macro.h>
 #include <sys/types.h>
 
 static inline void tester_set_bit(uint8_t *addr, unsigned int bit)
@@ -53,6 +55,8 @@ void tester_register_command_handlers(uint8_t service,
 				      const struct btp_handler *handlers,
 				      size_t num);
 
+uint16_t tester_supported_commands(uint8_t service, uint8_t *cmds);
+
 uint8_t tester_init_gatt(void);
 uint8_t tester_unregister_gatt(void);
 
diff --git a/tests/bluetooth/tester/src/btp_core.c b/tests/bluetooth/tester/src/btp_core.c
index 2da735f44ec..3ef89414ce0 100644
--- a/tests/bluetooth/tester/src/btp_core.c
+++ b/tests/bluetooth/tester/src/btp_core.c
@@ -7,27 +7,26 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/sys/atomic.h>
-#include <zephyr/types.h>
-#include <string.h>
+#include <stdint.h>
 
-#include <zephyr/toolchain.h>
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gatt.h>
 #include <zephyr/bluetooth/hci.h>
-
-#include <zephyr/sys/byteorder.h>
+#include <zephyr/logging/log.h>
 #include <zephyr/net_buf.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/toolchain.h>
 
-#include <hci_core.h>
+#include "btp/btp.h"
+#include "hci_core.h"
 
-#include <zephyr/logging/log.h>
 #define LOG_MODULE_NAME bttester_core
 LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_BTTESTER_LOG_LEVEL);
 
-#include "btp/btp.h"
-
 static ATOMIC_DEFINE(registered_services, BTP_SERVICE_ID_MAX);
 
 static uint8_t supported_commands(const void *cmd, uint16_t cmd_len,
@@ -35,12 +34,8 @@ static uint8_t supported_commands(const void *cmd, uint16_t cmd_len,
 {
 	struct btp_core_read_supported_commands_rp *rp = rsp;
 
-	tester_set_bit(rp->data, BTP_CORE_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_CORE_READ_SUPPORTED_SERVICES);
-	tester_set_bit(rp->data, BTP_CORE_REGISTER_SERVICE);
-	tester_set_bit(rp->data, BTP_CORE_UNREGISTER_SERVICE);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_CORE, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
diff --git a/tests/bluetooth/tester/src/btp_gap.c b/tests/bluetooth/tester/src/btp_gap.c
index bbd41e91092..578862be77f 100644
--- a/tests/bluetooth/tester/src/btp_gap.c
+++ b/tests/bluetooth/tester/src/btp_gap.c
@@ -5,33 +5,37 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <errno.h>
 #include <stdint.h>
-
-#include <zephyr/bluetooth/audio/bap.h>
-#include <zephyr/bluetooth/addr.h>
-#include <zephyr/bluetooth/gap.h>
-#include <zephyr/sys/atomic.h>
-#include <zephyr/sys/util_macro.h>
-#include <zephyr/types.h>
 #include <string.h>
 
-#include <zephyr/toolchain.h>
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/att.h>
+#include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gatt.h>
 #include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/bluetooth/uuid.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/atomic.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/toolchain.h>
+#include <zephyr/types.h>
 
 #include <zephyr/sys/byteorder.h>
 #include <zephyr/net_buf.h>
 
 #include <hci_core.h>
 
-#include <zephyr/logging/log.h>
-#define LOG_MODULE_NAME bttester_gap
-LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_BTTESTER_LOG_LEVEL);
-
 #include "btp/btp.h"
 
+#define LOG_MODULE_NAME bttester_gap
+LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_BTTESTER_LOG_LEVEL);
 #define CONTROLLER_NAME "btp_tester"
 
 #define BT_LE_AD_DISCOV_MASK (BT_LE_AD_LIMITED | BT_LE_AD_GENERAL)
@@ -41,6 +45,10 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_BTTESTER_LOG_LEVEL);
 #define ADV_BUF_LEN (sizeof(struct btp_gap_device_found_ev) + 2 * 31)
 #endif
 
+#if defined(CONFIG_BT_CLASSIC)
+#define BR_ADV_BUF_LEN (sizeof(struct btp_gap_device_found_ev) + BT_BR_EIR_SIZE_MAX)
+#endif /* CONFIG_BT_CLASSIC */
+
 static atomic_t current_settings;
 struct bt_conn_auth_cb cb;
 static uint8_t oob_legacy_tk[16] = { 0 };
@@ -102,7 +110,17 @@ static void le_connected(struct bt_conn *conn, uint8_t err)
 	char addr_str[BT_ADDR_LE_STR_LEN];
 	struct bt_conn_info info;
 
-	(void)bt_addr_le_to_str(bt_conn_get_dst(conn), addr_str, sizeof(addr_str));
+	(void)memset(addr_str, 0, sizeof(addr_str));
+
+	if (bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		(void)bt_addr_le_to_str(bt_conn_get_dst(conn), addr_str, sizeof(addr_str));
+	} else if (IS_ENABLED(CONFIG_BT_CLASSIC) && bt_conn_is_type(conn, BT_CONN_TYPE_BR)) {
+		(void)bt_addr_to_str(bt_conn_get_dst_br(conn), addr_str, sizeof(addr_str));
+	} else {
+		LOG_WRN("Unsupported transport");
+		return;
+	}
+
 	LOG_DBG("%s: 0x%02x", addr_str, err);
 
 	if (err) {
@@ -111,10 +129,17 @@ static void le_connected(struct bt_conn *conn, uint8_t err)
 
 	bt_conn_get_info(conn, &info);
 
-	bt_addr_le_copy(&ev.address, info.le.dst);
-	ev.interval = sys_cpu_to_le16(info.le.interval);
-	ev.latency = sys_cpu_to_le16(info.le.latency);
-	ev.timeout = sys_cpu_to_le16(info.le.timeout);
+	(void)memset(&ev, 0, sizeof(ev));
+
+	if (bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		bt_addr_le_copy(&ev.address, info.le.dst);
+		ev.interval = sys_cpu_to_le16(info.le.interval);
+		ev.latency = sys_cpu_to_le16(info.le.latency);
+		ev.timeout = sys_cpu_to_le16(info.le.timeout);
+	} else if (IS_ENABLED(CONFIG_BT_CLASSIC) && bt_conn_is_type(conn, BT_CONN_TYPE_BR)) {
+		ev.address.type = BTP_BR_ADDRESS_TYPE;
+		bt_addr_copy(&ev.address.a, info.br.dst);
+	}
 
 	tester_event(BTP_SERVICE_ID_GAP, BTP_GAP_EV_DEVICE_CONNECTED, &ev, sizeof(ev));
 
@@ -130,13 +155,27 @@ static void le_connected(struct bt_conn *conn, uint8_t err)
 static void le_disconnected(struct bt_conn *conn, uint8_t reason)
 {
 	struct btp_gap_device_disconnected_ev ev;
-	const bt_addr_le_t *addr = bt_conn_get_dst(conn);
 	char addr_str[BT_ADDR_LE_STR_LEN];
 
-	(void)bt_addr_le_to_str(bt_conn_get_dst(conn), addr_str, sizeof(addr_str));
-	LOG_DBG("%s: 0x%02x", addr_str, reason);
+	if (bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		const bt_addr_le_t *addr;
 
-	bt_addr_le_copy(&ev.address, addr);
+		addr = bt_conn_get_dst(conn);
+		(void)bt_addr_le_to_str(addr, addr_str, sizeof(addr_str));
+		bt_addr_le_copy(&ev.address, addr);
+	} else if (IS_ENABLED(CONFIG_BT_CLASSIC) && bt_conn_is_type(conn, BT_CONN_TYPE_BR)) {
+		const bt_addr_t *br_addr;
+
+		br_addr = bt_conn_get_dst_br(conn);
+		(void)bt_addr_to_str(br_addr, addr_str, sizeof(addr_str));
+		ev.address.type = BTP_BR_ADDRESS_TYPE;
+		bt_addr_copy(&ev.address.a, br_addr);
+	} else {
+		LOG_WRN("Unsupported transport");
+		return;
+	}
+
+	LOG_DBG("%s: 0x%02x", addr_str, reason);
 
 	tester_event(BTP_SERVICE_ID_GAP, BTP_GAP_EV_DEVICE_DISCONNECTED, &ev, sizeof(ev));
 }
@@ -158,6 +197,10 @@ static void le_param_updated(struct bt_conn *conn, uint16_t interval,
 	struct btp_gap_conn_param_update_ev ev;
 	const bt_addr_le_t *addr = bt_conn_get_dst(conn);
 
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		return;
+	}
+
 	bt_addr_le_copy(&ev.address, addr);
 	ev.interval = sys_cpu_to_le16(interval);
 	ev.latency = sys_cpu_to_le16(latency);
@@ -182,14 +225,38 @@ static bool le_param_req(struct bt_conn *conn, struct bt_le_conn_param *param)
 static void le_security_changed(struct bt_conn *conn, bt_security_t level,
 				enum bt_security_err err)
 {
-	const bt_addr_le_t *addr = bt_conn_get_dst(conn);
 	struct btp_gap_sec_level_changed_ev sec_ev;
 	struct btp_gap_bond_lost_ev bond_ev;
+	struct btp_gap_encryption_change_ev enc_ev;
 	struct bt_conn_info info;
 
+	if (bt_conn_get_info(conn, &info) != 0) {
+		LOG_WRN("Failed to get connection info of %p", conn);
+		return;
+	}
+
+	if (info.type == BT_CONN_TYPE_LE) {
+		bt_addr_le_copy(&sec_ev.address, info.le.dst);
+		bt_addr_le_copy(&bond_ev.address, info.le.dst);
+		bt_addr_le_copy(&enc_ev.address, info.le.dst);
+	} else if (IS_ENABLED(CONFIG_BT_CLASSIC) && (info.type == BT_CONN_TYPE_BR)) {
+		sec_ev.address.type = BTP_BR_ADDRESS_TYPE;
+		bt_addr_copy(&sec_ev.address.a, info.br.dst);
+		bond_ev.address.type = BTP_BR_ADDRESS_TYPE;
+		bt_addr_copy(&bond_ev.address.a, info.br.dst);
+		enc_ev.address.type = BTP_BR_ADDRESS_TYPE;
+		bt_addr_copy(&enc_ev.address.a, info.br.dst);
+	} else {
+		LOG_WRN("Unsupported transport");
+		return;
+	}
+
+	enc_ev.enabled = (err == BT_SECURITY_ERR_SUCCESS) ? true : false;
+	enc_ev.key_size = info.security.enc_key_size;
+	tester_event(BTP_SERVICE_ID_GAP, BTP_GAP_EV_ENCRYPTION_CHANGE, &enc_ev, sizeof(enc_ev));
+
 	switch (err) {
 	case BT_SECURITY_ERR_SUCCESS:
-		bt_addr_le_copy(&sec_ev.address, addr);
 		/* enum matches BTP values */
 		sec_ev.sec_level = level;
 
@@ -202,12 +269,9 @@ static void le_security_changed(struct bt_conn *conn, bt_security_t level,
 		 *
 		 * This means bond is lost and we restart pairing to re-bond
 		 */
-		if (bt_conn_get_info(conn, &info) == 0 &&
-		    info.role == BT_CONN_ROLE_CENTRAL) {
+		if (info.role == BT_CONN_ROLE_CENTRAL) {
 			LOG_DBG("Bond lost");
 
-			bt_addr_le_copy(&bond_ev.address, addr);
-
 			tester_event(BTP_SERVICE_ID_GAP, BTP_GAP_EV_BOND_LOST,
 				     &bond_ev, sizeof(bond_ev));
 
@@ -233,45 +297,8 @@ static uint8_t supported_commands(const void *cmd, uint16_t cmd_len,
 {
 	struct btp_gap_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_GAP_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_GAP_READ_CONTROLLER_INDEX_LIST);
-	tester_set_bit(rp->data, BTP_GAP_READ_CONTROLLER_INFO);
-	tester_set_bit(rp->data, BTP_GAP_SET_POWERED);
-	tester_set_bit(rp->data, BTP_GAP_SET_CONNECTABLE);
-
-	/* octet 1 */
-	tester_set_bit(rp->data, BTP_GAP_SET_DISCOVERABLE);
-	tester_set_bit(rp->data, BTP_GAP_SET_BONDABLE);
-	tester_set_bit(rp->data, BTP_GAP_START_ADVERTISING);
-	tester_set_bit(rp->data, BTP_GAP_STOP_ADVERTISING);
-	tester_set_bit(rp->data, BTP_GAP_START_DISCOVERY);
-	tester_set_bit(rp->data, BTP_GAP_STOP_DISCOVERY);
-	tester_set_bit(rp->data, BTP_GAP_CONNECT);
-	tester_set_bit(rp->data, BTP_GAP_DISCONNECT);
-
-	/* octet 2 */
-	tester_set_bit(rp->data, BTP_GAP_SET_IO_CAP);
-	tester_set_bit(rp->data, BTP_GAP_PAIR);
-	tester_set_bit(rp->data, BTP_GAP_PASSKEY_ENTRY);
-	tester_set_bit(rp->data, BTP_GAP_PASSKEY_CONFIRM);
-	tester_set_bit(rp->data, BTP_GAP_START_DIRECTED_ADV);
-	tester_set_bit(rp->data, BTP_GAP_CONN_PARAM_UPDATE);
-
-	/* octet 3 */
-	tester_set_bit(rp->data, BTP_GAP_OOB_LEGACY_SET_DATA);
-	if (!IS_ENABLED(CONFIG_BT_SMP_OOB_LEGACY_PAIR_ONLY)) {
-		tester_set_bit(rp->data, BTP_GAP_OOB_SC_GET_LOCAL_DATA);
-		tester_set_bit(rp->data, BTP_GAP_OOB_SC_SET_REMOTE_DATA);
-	}
-
-	tester_set_bit(rp->data, BTP_GAP_SET_MITM);
-	tester_set_bit(rp->data, BTP_GAP_SET_FILTER_LIST);
-	if (IS_ENABLED(CONFIG_BT_EXT_ADV)) {
-		tester_set_bit(rp->data, BTP_GAP_SET_EXTENDED_ADVERTISING);
-	}
-
-	*rsp_len = sizeof(*rp) + 4;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_GAP, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
@@ -323,6 +350,10 @@ static uint8_t controller_info(const void *cmd, uint16_t cmd_len,
 	supported_settings |= BIT(BTP_GAP_SETTINGS_LE);
 	supported_settings |= BIT(BTP_GAP_SETTINGS_ADVERTISING);
 	supported_settings |= BIT(BTP_GAP_SETTINGS_EXTENDED_ADVERTISING);
+	if (IS_ENABLED(CONFIG_BT_CLASSIC)) {
+		supported_settings |= BIT(BTP_GAP_SETTINGS_BREDR);
+		supported_settings |= BIT(BTP_GAP_SETTINGS_SSP);
+	}
 
 	rp->supported_settings = sys_cpu_to_le32(supported_settings);
 	rp->current_settings = sys_cpu_to_le32(current_settings);
@@ -505,6 +536,15 @@ static uint8_t set_connectable(const void *cmd, uint16_t cmd_len,
 	const struct btp_gap_set_connectable_cmd *cp = cmd;
 	struct btp_gap_set_connectable_rp *rp = rsp;
 
+	if (IS_ENABLED(CONFIG_BT_CLASSIC)) {
+		int err;
+
+		err = bt_br_set_connectable(cp->connectable ? true : false);
+		if ((err < 0) && (err != -EALREADY)) {
+			return BTP_STATUS_FAILED;
+		}
+	}
+
 	if (cp->connectable) {
 		atomic_set_bit(&current_settings, BTP_GAP_SETTINGS_CONNECTABLE);
 	} else {
@@ -616,15 +656,64 @@ static uint8_t set_discoverable(const void *cmd, uint16_t cmd_len,
 
 	switch (cp->discoverable) {
 	case BTP_GAP_NON_DISCOVERABLE:
+		if (IS_ENABLED(CONFIG_BT_CLASSIC)) {
+			int err;
+
+			err = bt_br_set_discoverable(false, false);
+			if ((err < 0) && (err != -EALREADY)) {
+				return BTP_STATUS_FAILED;
+			}
+		}
+
 		ad_flags &= ~(BT_LE_AD_GENERAL | BT_LE_AD_LIMITED);
 		atomic_clear_bit(&current_settings, BTP_GAP_SETTINGS_DISCOVERABLE);
 		break;
 	case BTP_GAP_GENERAL_DISCOVERABLE:
+		if (IS_ENABLED(CONFIG_BT_CLASSIC)) {
+			int err;
+
+			err = bt_br_set_connectable(true);
+			if (err == -EALREADY) {
+				err = bt_br_set_discoverable(false, false);
+				if ((err < 0) && (err != -EALREADY)) {
+					return BTP_STATUS_FAILED;
+				}
+			} else if (err < 0) {
+				return BTP_STATUS_FAILED;
+			}
+
+			err = bt_br_set_discoverable(true, false);
+			if (err < 0) {
+				return BTP_STATUS_FAILED;
+			}
+			ad_flags &= ~BT_LE_AD_NO_BREDR;
+		}
+
 		ad_flags &= ~BT_LE_AD_LIMITED;
 		ad_flags |= BT_LE_AD_GENERAL;
 		atomic_set_bit(&current_settings, BTP_GAP_SETTINGS_DISCOVERABLE);
 		break;
 	case BTP_GAP_LIMITED_DISCOVERABLE:
+		if (IS_ENABLED(CONFIG_BT_CLASSIC)) {
+			int err;
+
+			err = bt_br_set_connectable(true);
+			if (err == -EALREADY) {
+				err = bt_br_set_discoverable(false, false);
+				if ((err < 0) && (err != -EALREADY)) {
+					return BTP_STATUS_FAILED;
+				}
+			} else if (err < 0) {
+				return BTP_STATUS_FAILED;
+			}
+
+			err = bt_br_set_discoverable(true, true);
+			if (err < 0) {
+				return BTP_STATUS_FAILED;
+			}
+			ad_flags &= ~BT_LE_AD_NO_BREDR;
+		}
+
 		ad_flags &= ~BT_LE_AD_GENERAL;
 		ad_flags |= BT_LE_AD_LIMITED;
 		atomic_set_bit(&current_settings, BTP_GAP_SETTINGS_DISCOVERABLE);
@@ -1021,17 +1110,95 @@ static void device_found(const bt_addr_le_t *addr, int8_t rssi, uint8_t evtype,
 	net_buf_simple_reset(adv_buf);
 }
 
+#if defined(CONFIG_BT_CLASSIC)
+static struct net_buf_simple *br_adv_buf = NET_BUF_SIMPLE(BR_ADV_BUF_LEN);
+
+static void br_discover_recv(const struct bt_br_discovery_result *result)
+{
+	struct btp_gap_device_found_ev *ev;
+
+	/* cleanup */
+	net_buf_simple_init(br_adv_buf, 0);
+
+	ev = net_buf_simple_add(br_adv_buf, sizeof(*ev));
+
+	ev = (void *) br_adv_buf->data;
+	ev->address.type = BTP_BR_ADDRESS_TYPE;
+	bt_addr_copy(&ev->address.a, &result->addr);
+
+	ev->eir_data_len = 0;
+	ev->rssi = result->rssi;
+	ev->flags = BTP_GAP_DEVICE_FOUND_FLAG_AD | BTP_GAP_DEVICE_FOUND_FLAG_RSSI;
+	for (size_t i = 0U; i < sizeof(result->eir); i = ev->eir_data_len) {
+		if (result->eir[i] != 0) {
+			/* Append EIR length and length field itself */
+			ev->eir_data_len += result->eir[i] + 1;
+		} else {
+			/* invalid length found, jump out*/
+			break;
+		}
+	}
+	(void)memcpy(net_buf_simple_add(br_adv_buf, ev->eir_data_len), result->eir,
+		     ev->eir_data_len);
+
+	tester_event(BTP_SERVICE_ID_GAP, BTP_GAP_EV_DEVICE_FOUND, br_adv_buf->data,
+		     br_adv_buf->len);
+	net_buf_simple_reset(br_adv_buf);
+}
+
+static struct bt_br_discovery_cb br_discover = {
+	.recv = br_discover_recv,
+};
+
+static struct bt_br_discovery_param br_discover_param;
+
+#define BR_DISCOVER_RESULT_COUNT 10
+static struct bt_br_discovery_result br_discover_result[BR_DISCOVER_RESULT_COUNT];
+
+static uint8_t br_start_discovery(const struct btp_gap_start_discovery_cmd *cp)
+{
+	static bool registered;
+	int err;
+
+	if (!registered) {
+		registered = true;
+		bt_br_discovery_cb_register(&br_discover);
+	}
+
+	br_discover_param.length = BR_DISCOVER_RESULT_COUNT;
+	if (cp->flags & BTP_GAP_DISCOVERY_FLAG_LIMITED) {
+		br_discover_param.limited = true;
+	} else {
+		br_discover_param.limited = false;
+	}
+
+	err = bt_br_discovery_start(&br_discover_param, br_discover_result,
+				    ARRAY_SIZE(br_discover_result));
+	if (err != 0) {
+		return BTP_STATUS_FAILED;
+	}
+
+	return BTP_STATUS_SUCCESS;
+}
+#else
+static uint8_t br_start_discovery(const struct btp_gap_start_discovery_cmd *cp)
+{
+	LOG_WRN("BR/EDR not supported");
+	return BTP_STATUS_FAILED;
+}
+#endif /* CONFIG_BT_CLASSIC */
+
 static uint8_t start_discovery(const void *cmd, uint16_t cmd_len,
 			       void *rsp, uint16_t *rsp_len)
 {
 	const struct btp_gap_start_discovery_cmd *cp = cmd;
 
-	/* only LE scan is supported */
 	if (cp->flags & BTP_GAP_DISCOVERY_FLAG_BREDR) {
-		LOG_WRN("BR/EDR not supported");
-		return BTP_STATUS_FAILED;
+		/* Start BR discovery*/
+		return br_start_discovery(cp);
 	}
 
+	/* Start LE scanning */
 	if (bt_le_scan_start(cp->flags & BTP_GAP_DISCOVERY_FLAG_LE_ACTIVE_SCAN ?
 			     BT_LE_SCAN_ACTIVE : BT_LE_SCAN_PASSIVE,
 			     device_found) < 0) {
@@ -1050,6 +1217,14 @@ static uint8_t stop_discovery(const void *cmd, uint16_t cmd_len,
 {
 	int err;
 
+	if (IS_ENABLED(CONFIG_BT_CLASSIC)) {
+		err = bt_br_discovery_stop();
+		if ((err < 0) && (err != -EALREADY)) {
+			LOG_ERR("Failed to stop discovery: %d", err);
+			return BTP_STATUS_FAILED;
+		}
+	}
+
 	err = bt_le_scan_stop();
 	if (err < 0) {
 		LOG_ERR("Failed to stop scanning: %d", err);
@@ -1059,6 +1234,28 @@ static uint8_t stop_discovery(const void *cmd, uint16_t cmd_len,
 	return BTP_STATUS_SUCCESS;
 }
 
+#if defined(CONFIG_BT_CLASSIC)
+static uint8_t br_connect(const struct btp_gap_connect_cmd *cp)
+{
+	struct bt_conn *conn;
+
+	conn = bt_conn_create_br(&cp->address.a, BT_BR_CONN_PARAM_DEFAULT);
+	if (conn == NULL) {
+		LOG_ERR("Failed to create connection");
+		return BTP_STATUS_FAILED;
+	}
+
+	bt_conn_unref(conn);
+
+	return BTP_STATUS_SUCCESS;
+}
+#else
+static uint8_t br_connect(const struct btp_gap_connect_cmd *cp)
+{
+	return BTP_STATUS_FAILED;
+}
+#endif /* CONFIG_BT_CLASSIC */
+
 static uint8_t connect(const void *cmd, uint16_t cmd_len,
 		       void *rsp, uint16_t *rsp_len)
 {
@@ -1073,6 +1270,10 @@ static uint8_t connect(const void *cmd, uint16_t cmd_len,
 	const struct btp_gap_connect_cmd *cp = cmd;
 	int err;
 
+	if (cp->address.type == BTP_BR_ADDRESS_TYPE) {
+		return br_connect(cp);
+	}
+
 	if (!bt_addr_le_eq(&cp->address, BT_ADDR_LE_ANY)) {
 		struct bt_conn *conn = NULL;
 
@@ -1101,8 +1302,17 @@ static uint8_t disconnect(const void *cmd, uint16_t cmd_len,
 	struct bt_conn *conn;
 	uint8_t status;
 
-	conn = bt_conn_lookup_addr_le(BT_ID_DEFAULT, &cp->address);
-	if (!conn) {
+	if (cp->address.type == BTP_BR_ADDRESS_TYPE) {
+		if (IS_ENABLED(CONFIG_BT_CLASSIC)) {
+			conn = bt_conn_lookup_addr_br(&cp->address.a);
+		} else {
+			return BTP_STATUS_FAILED;
+		}
+	} else {
+		conn = bt_conn_lookup_addr_le(BT_ID_DEFAULT, &cp->address);
+	}
+
+	if (conn == NULL) {
 		LOG_ERR("Unknown connection");
 		return BTP_STATUS_FAILED;
 	}
@@ -1122,9 +1332,23 @@ static uint8_t disconnect(const void *cmd, uint16_t cmd_len,
 static void auth_passkey_display(struct bt_conn *conn, unsigned int passkey)
 {
 	struct btp_gap_passkey_display_ev ev;
-	const bt_addr_le_t *addr = bt_conn_get_dst(conn);
 
-	bt_addr_le_copy(&ev.address, addr);
+	if (bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		const bt_addr_le_t *addr;
+
+		addr = bt_conn_get_dst(conn);
+		bt_addr_le_copy(&ev.address, addr);
+	} else if (IS_ENABLED(CONFIG_BT_CLASSIC) && bt_conn_is_type(conn, BT_CONN_TYPE_BR)) {
+		const bt_addr_t *br_addr;
+
+		br_addr = bt_conn_get_dst_br(conn);
+		ev.address.type = BTP_BR_ADDRESS_TYPE;
+		bt_addr_copy(&ev.address.a, br_addr);
+	} else {
+		LOG_WRN("Unsupported transport");
+		return;
+	}
+
 	ev.passkey = sys_cpu_to_le32(passkey);
 
 	tester_event(BTP_SERVICE_ID_GAP, BTP_GAP_EV_PASSKEY_DISPLAY, &ev, sizeof(ev));
@@ -1133,9 +1357,22 @@ static void auth_passkey_display(struct bt_conn *conn, unsigned int passkey)
 static void auth_passkey_entry(struct bt_conn *conn)
 {
 	struct btp_gap_passkey_entry_req_ev ev;
-	const bt_addr_le_t *addr = bt_conn_get_dst(conn);
 
-	bt_addr_le_copy(&ev.address, addr);
+	if (bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		const bt_addr_le_t *addr;
+
+		addr = bt_conn_get_dst(conn);
+		bt_addr_le_copy(&ev.address, addr);
+	} else if (IS_ENABLED(CONFIG_BT_CLASSIC) && bt_conn_is_type(conn, BT_CONN_TYPE_BR)) {
+		const bt_addr_t *br_addr;
+
+		br_addr = bt_conn_get_dst_br(conn);
+		ev.address.type = BTP_BR_ADDRESS_TYPE;
+		bt_addr_copy(&ev.address.a, br_addr);
+	} else {
+		LOG_WRN("Unsupported transport");
+		return;
+	}
 
 	tester_event(BTP_SERVICE_ID_GAP, BTP_GAP_EV_PASSKEY_ENTRY_REQ, &ev, sizeof(ev));
 }
@@ -1143,9 +1380,23 @@ static void auth_passkey_entry(struct bt_conn *conn)
 static void auth_passkey_confirm(struct bt_conn *conn, unsigned int passkey)
 {
 	struct btp_gap_passkey_confirm_req_ev ev;
-	const bt_addr_le_t *addr = bt_conn_get_dst(conn);
 
-	bt_addr_le_copy(&ev.address, addr);
+	if (bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		const bt_addr_le_t *addr;
+
+		addr = bt_conn_get_dst(conn);
+		bt_addr_le_copy(&ev.address, addr);
+	} else if (IS_ENABLED(CONFIG_BT_CLASSIC) && bt_conn_is_type(conn, BT_CONN_TYPE_BR)) {
+		const bt_addr_t *br_addr;
+
+		br_addr = bt_conn_get_dst_br(conn);
+		ev.address.type = BTP_BR_ADDRESS_TYPE;
+		bt_addr_copy(&ev.address.a, br_addr);
+	} else {
+		LOG_WRN("Unsupported transport");
+		return;
+	}
+
 	ev.passkey = sys_cpu_to_le32(passkey);
 
 	tester_event(BTP_SERVICE_ID_GAP, BTP_GAP_EV_PASSKEY_CONFIRM_REQ, &ev, sizeof(ev));
@@ -1160,10 +1411,29 @@ enum bt_security_err auth_pairing_accept(struct bt_conn *conn,
 					 const struct bt_conn_pairing_feat *const feat)
 {
 	struct btp_gap_bond_lost_ev ev;
-	const bt_addr_le_t *addr = bt_conn_get_dst(conn);
 
-	if (!bt_addr_le_is_bonded(BT_ID_DEFAULT, addr)) {
-		return BT_SECURITY_ERR_SUCCESS;
+	if (bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		const bt_addr_le_t *addr;
+
+		addr = bt_conn_get_dst(conn);
+		if (!bt_le_bond_exists(BT_ID_DEFAULT, addr)) {
+			return BT_SECURITY_ERR_SUCCESS;
+		}
+
+		bt_addr_le_copy(&ev.address, addr);
+	} else if (IS_ENABLED(CONFIG_BT_CLASSIC) && bt_conn_is_type(conn, BT_CONN_TYPE_BR)) {
+		const bt_addr_t *br_addr;
+
+		br_addr = bt_conn_get_dst_br(conn);
+		if (!bt_br_bond_exists(br_addr)) {
+			return BT_SECURITY_ERR_SUCCESS;
+		}
+
+		ev.address.type = BTP_BR_ADDRESS_TYPE;
+		bt_addr_copy(&ev.address.a, br_addr);
+	} else {
+		LOG_WRN("Unsupported transport");
+		return BTP_STATUS_FAILED;
 	}
 
 	/* If a peer is already bonded and tries to pair again then it means that
@@ -1171,8 +1441,6 @@ enum bt_security_err auth_pairing_accept(struct bt_conn *conn,
 	 */
 	LOG_DBG("Bond lost");
 
-	bt_addr_le_copy(&ev.address, addr);
-
 	tester_event(BTP_SERVICE_ID_GAP, BTP_GAP_EV_BOND_LOST, &ev, sizeof(ev));
 
 	return BT_SECURITY_ERR_SUCCESS;
@@ -1181,9 +1449,23 @@ enum bt_security_err auth_pairing_accept(struct bt_conn *conn,
 void auth_pairing_failed(struct bt_conn *conn, enum bt_security_err reason)
 {
 	struct btp_gap_bond_pairing_failed_ev ev;
-	const bt_addr_le_t *addr = bt_conn_get_dst(conn);
 
-	bt_addr_le_copy(&ev.address, addr);
+	if (bt_conn_is_type(conn, BT_CONN_TYPE_LE)) {
+		const bt_addr_le_t *addr;
+
+		addr = bt_conn_get_dst(conn);
+		bt_addr_le_copy(&ev.address, addr);
+	} else if (IS_ENABLED(CONFIG_BT_CLASSIC) && bt_conn_is_type(conn, BT_CONN_TYPE_BR)) {
+		const bt_addr_t *br_addr;
+
+		br_addr = bt_conn_get_dst_br(conn);
+		ev.address.type = BTP_BR_ADDRESS_TYPE;
+		bt_addr_copy(&ev.address.a, br_addr);
+	} else {
+		LOG_WRN("Unsupported transport");
+		return;
+	}
+
 	ev.reason = reason;
 
 	tester_event(BTP_SERVICE_ID_GAP, BTP_GAP_EV_PAIRING_FAILED, &ev, sizeof(ev));
@@ -1202,6 +1484,24 @@ static struct bt_conn_auth_info_cb auth_info_cb = {
 	.pairing_complete = auth_pairing_complete,
 };
 
+#if defined(CONFIG_BT_CLASSIC)
+static void auth_pincode_entry(struct bt_conn *conn, bool highsec)
+{
+	const char *pin = "0000";
+	const char *pin16 = "0000000000000000";
+
+	if (!bt_conn_is_type(conn, BT_CONN_TYPE_BR)) {
+		return;
+	}
+
+	if (highsec) {
+		bt_conn_auth_pincode_entry(conn, pin16);
+	} else {
+		bt_conn_auth_pincode_entry(conn, pin);
+	}
+}
+#endif /* CONFIG_BT_CLASSIC */
+
 static uint8_t set_io_cap(const void *cmd, uint16_t cmd_len,
 			  void *rsp, uint16_t *rsp_len)
 {
@@ -1243,6 +1543,10 @@ static uint8_t set_io_cap(const void *cmd, uint16_t cmd_len,
 
 	cb.pairing_accept = auth_pairing_accept;
 
+#if defined(CONFIG_BT_CLASSIC)
+	cb.pincode_entry = auth_pincode_entry;
+#endif /* CONFIG_BT_CLASSIC */
+
 	if (bt_conn_auth_cb_register(&cb)) {
 		return BTP_STATUS_FAILED;
 	}
@@ -1257,13 +1561,70 @@ static uint8_t pair(const void *cmd, uint16_t cmd_len,
 	struct bt_conn *conn;
 	int err;
 
-	conn = bt_conn_lookup_addr_le(BT_ID_DEFAULT, &cp->address);
+	if (cp->address.type == BTP_BR_ADDRESS_TYPE) {
+		if (IS_ENABLED(CONFIG_BT_CLASSIC)) {
+			conn = bt_conn_lookup_addr_br(&cp->address.a);
+		} else {
+			return BTP_STATUS_FAILED;
+		}
+	} else {
+		conn = bt_conn_lookup_addr_le(BT_ID_DEFAULT, &cp->address);
+	}
+
 	if (!conn) {
 		LOG_ERR("Unknown connection");
 		return BTP_STATUS_FAILED;
 	}
 
 	err = bt_conn_set_security(conn, BT_SECURITY_L2);
+	/*
+	 * If the error code is `-EBUSY`, it means the pairing/enryption is ongoing.
+	 * Just ignore the error.
+	 */
+	if ((err < 0) && (err != -EBUSY)) {
+		LOG_ERR("Failed to set security: %d", err);
+		bt_conn_unref(conn);
+		return BTP_STATUS_FAILED;
+	}
+
+	bt_conn_unref(conn);
+	return BTP_STATUS_SUCCESS;
+}
+
+static uint8_t pair_v2(const void *cmd, uint16_t cmd_len, void *rsp, uint16_t *rsp_len)
+{
+	const struct btp_gap_pair_v2_cmd *cp = cmd;
+	struct bt_conn *conn;
+	bt_security_t level;
+	int err;
+
+	/* TODO: Only supports mode 4 */
+	if ((cp->mode != BTP_GAP_PAIR_V2_MODE_4) && (cp->mode != BTP_GAP_PAIR_V2_MODE_ANY)) {
+		LOG_WRN("Unsupport mode %d", cp->mode);
+		return BTP_STATUS_FAILED;
+	}
+
+	if (cp->address.type == BTP_BR_ADDRESS_TYPE) {
+		if (IS_ENABLED(CONFIG_BT_CLASSIC)) {
+			conn = bt_conn_lookup_addr_br(&cp->address.a);
+		} else {
+			return BTP_STATUS_FAILED;
+		}
+	} else {
+		conn = bt_conn_lookup_addr_le(BT_ID_DEFAULT, &cp->address);
+	}
+
+	if (conn == NULL) {
+		LOG_ERR("Unknown connection");
+		return BTP_STATUS_FAILED;
+	}
+
+	level = (bt_security_t)cp->level;
+	if (cp->flags & BTP_GAP_PAIR_V2_FLAG_FORCE_PAIR) {
+		level = (bt_security_t)((uint8_t)level | BT_SECURITY_FORCE_PAIR);
+	}
+
+	err = bt_conn_set_security(conn, level);
 	if (err < 0) {
 		LOG_ERR("Failed to set security: %d", err);
 		bt_conn_unref(conn);
@@ -1281,7 +1642,16 @@ static uint8_t unpair(const void *cmd, uint16_t cmd_len,
 	struct bt_conn *conn;
 	int err;
 
-	conn = bt_conn_lookup_addr_le(BT_ID_DEFAULT, &cp->address);
+	if (cp->address.type == BTP_BR_ADDRESS_TYPE) {
+		if (IS_ENABLED(CONFIG_BT_CLASSIC)) {
+			conn = bt_conn_lookup_addr_br(&cp->address.a);
+		} else {
+			return BTP_STATUS_FAILED;
+		}
+	} else {
+		conn = bt_conn_lookup_addr_le(BT_ID_DEFAULT, &cp->address);
+	}
+
 	if (!conn) {
 		LOG_INF("Unknown connection");
 		goto keys;
@@ -1311,7 +1681,16 @@ static uint8_t passkey_entry(const void *cmd, uint16_t cmd_len,
 	struct bt_conn *conn;
 	int err;
 
-	conn = bt_conn_lookup_addr_le(BT_ID_DEFAULT, &cp->address);
+	if (cp->address.type == BTP_BR_ADDRESS_TYPE) {
+		if (IS_ENABLED(CONFIG_BT_CLASSIC)) {
+			conn = bt_conn_lookup_addr_br(&cp->address.a);
+		} else {
+			return BTP_STATUS_FAILED;
+		}
+	} else {
+		conn = bt_conn_lookup_addr_le(BT_ID_DEFAULT, &cp->address);
+	}
+
 	if (!conn) {
 		LOG_ERR("Unknown connection");
 		return BTP_STATUS_FAILED;
@@ -1335,7 +1714,16 @@ static uint8_t passkey_confirm(const void *cmd, uint16_t cmd_len,
 	struct bt_conn *conn;
 	int err;
 
-	conn = bt_conn_lookup_addr_le(BT_ID_DEFAULT, &cp->address);
+	if (cp->address.type == BTP_BR_ADDRESS_TYPE) {
+		if (IS_ENABLED(CONFIG_BT_CLASSIC)) {
+			conn = bt_conn_lookup_addr_br(&cp->address.a);
+		} else {
+			return BTP_STATUS_FAILED;
+		}
+	} else {
+		conn = bt_conn_lookup_addr_le(BT_ID_DEFAULT, &cp->address);
+	}
+
 	if (!conn) {
 		LOG_ERR("Unknown connection");
 		return BTP_STATUS_FAILED;
@@ -1375,7 +1763,16 @@ static uint8_t conn_param_update(const void *cmd, uint16_t cmd_len,
 	struct bt_conn *conn;
 	int err;
 
-	conn = bt_conn_lookup_addr_le(BT_ID_DEFAULT, &cp->address);
+	if (cp->address.type == BTP_BR_ADDRESS_TYPE) {
+		if (IS_ENABLED(CONFIG_BT_CLASSIC)) {
+			conn = bt_conn_lookup_addr_br(&cp->address.a);
+		} else {
+			return BTP_STATUS_FAILED;
+		}
+	} else {
+		conn = bt_conn_lookup_addr_le(BT_ID_DEFAULT, &cp->address);
+	}
+
 	if (!conn) {
 		LOG_ERR("Unknown connection");
 		return BTP_STATUS_FAILED;
@@ -1769,6 +2166,23 @@ static uint8_t padv_create_sync(const void *cmd, uint16_t cmd_len,
 }
 #endif /* defined(CONFIG_BT_PER_ADV) */
 
+#if defined(CONFIG_BT_RPA_TIMEOUT_DYNAMIC)
+static uint8_t set_rpa_timeout(const void *cmd, uint16_t cmd_len, void *rsp, uint16_t *rsp_len)
+{
+	const struct btp_gap_set_rpa_timeout_cmd *cp = cmd;
+	int err;
+
+	err = bt_le_set_rpa_timeout(sys_le16_to_cpu(cp->rpa_timeout));
+
+	if (err != 0) {
+		LOG_DBG("Failed to set RPA timeout: %d", err);
+		return BTP_STATUS_FAILED;
+	}
+
+	return BTP_STATUS_SUCCESS;
+}
+#endif /* defined(CONFIG_BT_RPA_TIMEOUT_DYNAMIC) */
+
 static const struct btp_handler handlers[] = {
 	{
 		.opcode = BTP_GAP_READ_SUPPORTED_COMMANDS,
@@ -1852,6 +2266,11 @@ static const struct btp_handler handlers[] = {
 		.expect_len = sizeof(struct btp_gap_pair_cmd),
 		.func = pair,
 	},
+	{
+		.opcode = BTP_GAP_PAIR_V2,
+		.expect_len = sizeof(struct btp_gap_pair_v2_cmd),
+		.func = pair_v2,
+	},
 	{
 		.opcode = BTP_GAP_UNPAIR,
 		.expect_len = sizeof(struct btp_gap_unpair_cmd),
@@ -1933,6 +2352,13 @@ static const struct btp_handler handlers[] = {
 	},
 #endif /* defined(CONFIG_BT_PER_ADV) */
 #endif /* defined(CONFIG_BT_EXT_ADV) */
+#if defined(CONFIG_BT_RPA_TIMEOUT_DYNAMIC)
+	{
+		.opcode = BTP_GAP_SET_RPA_TIMEOUT,
+		.expect_len = sizeof(struct btp_gap_set_rpa_timeout_cmd),
+		.func = set_rpa_timeout,
+	},
+#endif /* defined(CONFIG_BT_RPA_TIMEOUT_DYNAMIC) */
 };
 
 uint8_t tester_init_gap(void)
diff --git a/tests/bluetooth/tester/src/btp_gatt.c b/tests/bluetooth/tester/src/btp_gatt.c
index ee4f1b3cbd9..5f9ad63be61 100644
--- a/tests/bluetooth/tester/src/btp_gatt.c
+++ b/tests/bluetooth/tester/src/btp_gatt.c
@@ -6,29 +6,34 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/types.h>
-#include <string.h>
 #include <errno.h>
+#include <stdint.h>
 #include <stdlib.h>
+#include <string.h>
 
-#include <zephyr/toolchain.h>
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/att.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/gatt.h>
 #include <zephyr/bluetooth/uuid.h>
 #include <zephyr/bluetooth/l2cap.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
 #include <zephyr/sys/byteorder.h>
 #include <zephyr/sys/printk.h>
 #include <zephyr/sys/__assert.h>
-#include <zephyr/net_buf.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/toolchain.h>
+#include <sys/types.h>
+
+#include "btp/btp.h"
 
-#include <zephyr/logging/log.h>
 #define LOG_MODULE_NAME bttester_gatt
 LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_BTTESTER_LOG_LEVEL);
 
-#include "btp/btp.h"
-
 #define MAX_BUFFER_SIZE 2048
 #define MAX_UUID_LEN 16
 
@@ -222,48 +227,8 @@ static uint8_t supported_commands(const void *cmd, uint16_t cmd_len,
 {
 	struct btp_gatt_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_GATT_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_GATT_ADD_SERVICE);
-	tester_set_bit(rp->data, BTP_GATT_ADD_CHARACTERISTIC);
-	tester_set_bit(rp->data, BTP_GATT_ADD_DESCRIPTOR);
-	tester_set_bit(rp->data, BTP_GATT_ADD_INCLUDED_SERVICE);
-	tester_set_bit(rp->data, BTP_GATT_SET_VALUE);
-	tester_set_bit(rp->data, BTP_GATT_START_SERVER);
-
-	/* octet 1 */
-	tester_set_bit(rp->data, BTP_GATT_SET_ENC_KEY_SIZE);
-	tester_set_bit(rp->data, BTP_GATT_EXCHANGE_MTU);
-	tester_set_bit(rp->data, BTP_GATT_DISC_ALL_PRIM);
-	tester_set_bit(rp->data, BTP_GATT_DISC_PRIM_UUID);
-	tester_set_bit(rp->data, BTP_GATT_FIND_INCLUDED);
-	tester_set_bit(rp->data, BTP_GATT_DISC_ALL_CHRC);
-	tester_set_bit(rp->data, BTP_GATT_DISC_CHRC_UUID);
-
-	/* octet 2 */
-	tester_set_bit(rp->data, BTP_GATT_DISC_ALL_DESC);
-	tester_set_bit(rp->data, BTP_GATT_READ);
-	tester_set_bit(rp->data, BTP_GATT_READ_LONG);
-	tester_set_bit(rp->data, BTP_GATT_READ_MULTIPLE);
-	tester_set_bit(rp->data, BTP_GATT_WRITE_WITHOUT_RSP);
-	tester_set_bit(rp->data, BTP_GATT_SIGNED_WRITE_WITHOUT_RSP);
-	tester_set_bit(rp->data, BTP_GATT_WRITE);
-
-	/* octet 3 */
-	tester_set_bit(rp->data, BTP_GATT_WRITE_LONG);
-	tester_set_bit(rp->data, BTP_GATT_CFG_NOTIFY);
-	tester_set_bit(rp->data, BTP_GATT_CFG_INDICATE);
-	tester_set_bit(rp->data, BTP_GATT_GET_ATTRIBUTES);
-	tester_set_bit(rp->data, BTP_GATT_GET_ATTRIBUTE_VALUE);
-	tester_set_bit(rp->data, BTP_GATT_CHANGE_DB);
-	tester_set_bit(rp->data, BTP_GATT_EATT_CONNECT);
-
-	/* octet 4 */
-	tester_set_bit(rp->data, BTP_GATT_READ_MULTIPLE_VAR);
-	tester_set_bit(rp->data, BTP_GATT_NOTIFY_MULTIPLE);
-
-
-	*rsp_len = sizeof(*rp) + 5;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_GATT, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
@@ -2103,7 +2068,7 @@ static uint8_t config_subscription_ind(const void *cmd, uint16_t cmd_len,
 #if defined(CONFIG_BT_GATT_NOTIFY_MULTIPLE)
 static void notify_cb(struct bt_conn *conn, void *user_data)
 {
-	LOG_DBG("Nofication sent");
+	LOG_DBG("Notification sent");
 }
 
 static uint8_t notify_mult(const void *cmd, uint16_t cmd_len,
diff --git a/tests/bluetooth/tester/src/btp_ias.c b/tests/bluetooth/tester/src/btp_ias.c
index 58d0aa71f64..6795d39dc05 100644
--- a/tests/bluetooth/tester/src/btp_ias.c
+++ b/tests/bluetooth/tester/src/btp_ias.c
@@ -5,13 +5,15 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stdint.h>
+
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/services/ias.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/byteorder.h>
 
 #include "btp/btp.h"
-#include <zephyr/sys/byteorder.h>
-#include <stdint.h>
 
-#include <zephyr/logging/log.h>
 #define LOG_MODULE_NAME bttester_ias
 LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_BTTESTER_LOG_LEVEL);
 
diff --git a/tests/bluetooth/tester/src/btp_l2cap.c b/tests/bluetooth/tester/src/btp_l2cap.c
index 288215aee5d..2fda35a7889 100644
--- a/tests/bluetooth/tester/src/btp_l2cap.c
+++ b/tests/bluetooth/tester/src/btp_l2cap.c
@@ -5,24 +5,34 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <errno.h>
+#include <stddef.h>
+#include <stdint.h>
+#include <string.h>
 
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/att.h>
 #include <zephyr/bluetooth/bluetooth.h>
-
-#include <errno.h>
+#include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/l2cap.h>
-#include <zephyr/bluetooth/att.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
 #include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util.h>
+#include <sys/types.h>
+
+#include "btp/btp.h"
 
-#include <zephyr/logging/log.h>
 #define LOG_MODULE_NAME bttester_l2cap
 LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_BTTESTER_LOG_LEVEL);
 
-#include "btp/btp.h"
-
 #define L2CAP_MPS        96
 #define DATA_MTU         (3 * L2CAP_MPS)
 #define DATA_MTU_INITIAL (2 * L2CAP_MPS)
 
+/* CHANNELS cannot be greater than 0x7f. */
 #define CHANNELS 2
 #define SERVERS 1
 
@@ -45,6 +55,14 @@ static struct channel {
 #endif
 } channels[CHANNELS];
 
+#if defined(CONFIG_BT_CLASSIC)
+static struct br_channel {
+	uint8_t chan_id; /* Internal number that identifies L2CAP channel. */
+	struct bt_l2cap_br_chan br;
+	bool in_use;
+} br_channels[CHANNELS];
+#endif /* CONFIG_BT_CLASSIC */
+
 /* TODO Extend to support multiple servers */
 static struct bt_l2cap_server servers[SERVERS];
 
@@ -233,6 +251,146 @@ static struct channel *get_free_channel()
 	return NULL;
 }
 
+#if defined(CONFIG_BT_CLASSIC)
+static void br_connected_cb(struct bt_l2cap_chan *l2cap_chan)
+{
+	struct btp_l2cap_connected_ev ev;
+	struct bt_l2cap_br_chan *l2cap_br_chan = CONTAINER_OF(
+			l2cap_chan, struct bt_l2cap_br_chan, chan);
+	struct br_channel *chan = CONTAINER_OF(l2cap_br_chan, struct br_channel, br);
+	struct bt_conn_info info;
+
+	ev.chan_id = chan->chan_id;
+
+	/* TODO: ev.psm */
+	if (bt_conn_get_info(l2cap_chan->conn, &info) != 0) {
+		return;
+	}
+
+	switch (info.type) {
+	case BT_CONN_TYPE_BR:
+		ev.mtu_remote = sys_cpu_to_le16(chan->br.tx.mtu);
+		ev.mps_remote = sys_cpu_to_le16(chan->br.tx.mtu);
+		ev.mtu_local = sys_cpu_to_le16(chan->br.rx.mtu);
+		ev.mps_local = sys_cpu_to_le16(chan->br.rx.mtu);
+		ev.address.type = BTP_BR_ADDRESS_TYPE;
+		bt_addr_copy(&ev.address.a, info.br.dst);
+		break;
+	default:
+		/* Unsupported transport */
+		return;
+	}
+
+	tester_event(BTP_SERVICE_ID_L2CAP, BTP_L2CAP_EV_CONNECTED, &ev, sizeof(ev));
+}
+
+static void br_disconnected_cb(struct bt_l2cap_chan *l2cap_chan)
+{
+	struct btp_l2cap_disconnected_ev ev;
+	struct bt_l2cap_br_chan *l2cap_br_chan = CONTAINER_OF(
+			l2cap_chan, struct bt_l2cap_br_chan, chan);
+	struct br_channel *chan = CONTAINER_OF(l2cap_br_chan, struct br_channel, br);
+	struct bt_conn_info info;
+
+	(void)memset(&ev, 0, sizeof(struct btp_l2cap_disconnected_ev));
+
+	/* TODO: ev.result */
+	ev.chan_id = chan->chan_id;
+
+	chan->in_use = false;
+
+	/* TODO: ev.psm */
+	if (bt_conn_get_info(l2cap_chan->conn, &info) != 0) {
+		return;
+	}
+
+	switch (info.type) {
+	case BT_CONN_TYPE_BR:
+		ev.address.type = BTP_BR_ADDRESS_TYPE;
+		bt_addr_copy(&ev.address.a, info.br.dst);
+		break;
+	default:
+		/* Unsupported transport */
+		return;
+	}
+
+	tester_event(BTP_SERVICE_ID_L2CAP, BTP_L2CAP_EV_DISCONNECTED, &ev, sizeof(ev));
+}
+
+static const struct bt_l2cap_chan_ops br_l2cap_ops = {
+	.connected = br_connected_cb,
+	.disconnected = br_disconnected_cb,
+};
+
+static struct br_channel *get_free_br_channel(void)
+{
+	uint8_t i;
+	struct br_channel *chan;
+
+	for (i = 0U; i < CHANNELS; i++) {
+		if (br_channels[i].in_use) {
+			continue;
+		}
+
+		chan = &br_channels[i];
+
+		(void)memset(chan, 0, sizeof(*chan));
+		chan->chan_id = i + ARRAY_SIZE(channels);
+
+		br_channels[i].in_use = true;
+
+		return chan;
+	}
+
+	return NULL;
+}
+
+static uint8_t br_connect(const struct btp_l2cap_connect_cmd *cp, struct btp_l2cap_connect_rp *rp,
+			  uint16_t *rsp_len)
+{
+	struct bt_conn *conn;
+	struct br_channel *br_chan = NULL;
+	int err;
+
+	conn = bt_conn_lookup_addr_br(&cp->address.a);
+	if (conn == NULL) {
+		return BTP_STATUS_FAILED;
+	}
+
+	br_chan = get_free_br_channel();
+	if (br_chan == NULL) {
+		goto fail;
+	}
+	br_chan->br.chan.ops = &br_l2cap_ops;
+	br_chan->br.rx.mtu = sys_le16_to_cpu(cp->mtu);
+	rp->chan_id[0] = br_chan->chan_id;
+
+	err = bt_l2cap_chan_connect(conn, &br_chan->br.chan, sys_le16_to_cpu(cp->psm));
+	if (err < 0) {
+		goto fail;
+	}
+
+	rp->num = 1;
+	*rsp_len = sizeof(*rp) + (rp->num * sizeof(rp->chan_id[0]));
+
+	bt_conn_unref(conn);
+	return BTP_STATUS_SUCCESS;
+
+fail:
+	if (br_chan != NULL) {
+		br_chan->in_use = false;
+	}
+	bt_conn_unref(conn);
+	return BTP_STATUS_FAILED;
+}
+#else
+static uint8_t br_connect(const struct btp_l2cap_connect_cmd *cp, struct btp_l2cap_connect_rp *rp,
+			  uint16_t *rsp_len)
+{
+	return BTP_STATUS_FAILED;
+}
+#endif /* CONFIG_BT_CLASSIC */
+
 static uint8_t connect(const void *cmd, uint16_t cmd_len,
 		       void *rsp, uint16_t *rsp_len)
 {
@@ -251,6 +409,10 @@ static uint8_t connect(const void *cmd, uint16_t cmd_len,
 		return BTP_STATUS_FAILED;
 	}
 
+	if (cp->address.type == BTP_BR_ADDRESS_TYPE) {
+		return br_connect(cp, rp, rsp_len);
+	}
+
 	conn = bt_conn_lookup_addr_le(BT_ID_DEFAULT, &cp->address);
 	if (!conn) {
 		return BTP_STATUS_FAILED;
@@ -308,6 +470,32 @@ static uint8_t connect(const void *cmd, uint16_t cmd_len,
 	return BTP_STATUS_FAILED;
 }
 
+#if defined(CONFIG_BT_CLASSIC)
+static uint8_t br_disconnect(uint8_t chan_id)
+{
+	struct br_channel *br_chan;
+	int err;
+
+	if (chan_id >= CHANNELS) {
+		return BTP_STATUS_FAILED;
+	}
+
+	br_chan = &br_channels[chan_id];
+
+	err = bt_l2cap_chan_disconnect(&br_chan->br.chan);
+	if (err != 0) {
+		return BTP_STATUS_FAILED;
+	}
+
+	return BTP_STATUS_SUCCESS;
+}
+#else
+static uint8_t br_disconnect(uint8_t chan_id)
+{
+	return BTP_STATUS_FAILED;
+}
+#endif /* CONFIG_BT_CLASSIC */
+
 static uint8_t disconnect(const void *cmd, uint16_t cmd_len,
 			  void *rsp, uint16_t *rsp_len)
 {
@@ -315,6 +503,16 @@ static uint8_t disconnect(const void *cmd, uint16_t cmd_len,
 	struct channel *chan;
 	int err;
 
+	if (IS_ENABLED(CONFIG_BT_CLASSIC)) {
+		uint8_t chan_id;
+
+		chan_id = cp->chan_id;
+		if (chan_id >= ARRAY_SIZE(channels)) {
+			chan_id = chan_id - ARRAY_SIZE(channels);
+			return br_disconnect(chan_id);
+		}
+	}
+
 	if (cp->chan_id >= CHANNELS) {
 		return BTP_STATUS_FAILED;
 	}
@@ -513,6 +711,40 @@ static int accept(struct bt_conn *conn, struct bt_l2cap_server *server,
 	return 0;
 }
 
+#if defined(CONFIG_BT_CLASSIC)
+static int br_accept(struct bt_conn *conn, struct bt_l2cap_server *server,
+		     struct bt_l2cap_chan **l2cap_chan)
+{
+	struct br_channel *chan;
+
+	if (bt_conn_enc_key_size(conn) < req_keysize) {
+		return -EPERM;
+	}
+
+	if (authorize_flag) {
+		return -EACCES;
+	}
+
+	chan = get_free_br_channel();
+	if (chan == NULL) {
+		return -ENOMEM;
+	}
+
+	chan->br.chan.ops = &br_l2cap_ops;
+	chan->br.rx.mtu = DATA_MTU_INITIAL;
+
+	*l2cap_chan = &chan->br.chan;
+
+	return 0;
+}
+#else
+static int br_accept(struct bt_conn *conn, struct bt_l2cap_server *server,
+		     struct bt_l2cap_chan **l2cap_chan)
+{
+	return -ENOTSUP;
+}
+#endif /* CONFIG_BT_CLASSIC */
+
 static uint8_t listen(const void *cmd, uint16_t cmd_len,
 		      void *rsp, uint16_t *rsp_len)
 {
@@ -520,8 +752,6 @@ static uint8_t listen(const void *cmd, uint16_t cmd_len,
 	struct bt_l2cap_server *server;
 	uint16_t psm = sys_le16_to_cpu(cp->psm);
 
-	/* TODO: Handle cmd->transport flag */
-
 	if (psm == 0 || !is_free_psm(psm)) {
 		return BTP_STATUS_FAILED;
 	}
@@ -531,7 +761,6 @@ static uint8_t listen(const void *cmd, uint16_t cmd_len,
 		return BTP_STATUS_FAILED;
 	}
 
-	server->accept = accept;
 	server->psm = psm;
 
 	switch (cp->response) {
@@ -550,12 +779,26 @@ static uint8_t listen(const void *cmd, uint16_t cmd_len,
 	case BTP_L2CAP_CONNECTION_RESPONSE_INSUFF_ENCRYPTION:
 		server->sec_level = BT_SECURITY_L2;
 		break;
+	case BTP_L2CAP_CONNECTION_RESPONSE_INSUFF_SEC_AUTHEN:
+		server->sec_level = BT_SECURITY_L4;
+		break;
 	default:
 		return BTP_STATUS_FAILED;
 	}
 
-	if (bt_l2cap_server_register(server) < 0) {
-		server->psm = 0U;
+	if (cp->transport == BTP_L2CAP_TRANSPORT_LE) {
+		server->accept = accept;
+		if (bt_l2cap_server_register(server) < 0) {
+			server->psm = 0U;
+			return BTP_STATUS_FAILED;
+		}
+	} else if (IS_ENABLED(CONFIG_BT_CLASSIC) && (cp->transport == BTP_L2CAP_TRANSPORT_BREDR)) {
+		server->accept = br_accept;
+		if (bt_l2cap_br_server_register(server) < 0) {
+			server->psm = 0U;
+			return BTP_STATUS_FAILED;
+		}
+	} else {
 		return BTP_STATUS_FAILED;
 	}
 
@@ -604,22 +847,8 @@ static uint8_t supported_commands(const void *cmd, uint16_t cmd_len,
 {
 	struct btp_l2cap_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_L2CAP_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_L2CAP_CONNECT);
-	tester_set_bit(rp->data, BTP_L2CAP_DISCONNECT);
-	tester_set_bit(rp->data, BTP_L2CAP_SEND_DATA);
-	tester_set_bit(rp->data, BTP_L2CAP_LISTEN);
-#if defined(CONFIG_BT_L2CAP_ECRED)
-	tester_set_bit(rp->data, BTP_L2CAP_RECONFIGURE);
-#endif
-	/* octet 1 */
-	tester_set_bit(rp->data, BTP_L2CAP_CREDITS);
-#if defined(CONFIG_BT_EATT)
-	tester_set_bit(rp->data, BTP_L2CAP_DISCONNECT_EATT_CHANS);
-#endif
-
-	*rsp_len = sizeof(*rp) + 2;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_L2CAP, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
diff --git a/tests/bluetooth/tester/src/btp_mesh.c b/tests/bluetooth/tester/src/btp_mesh.c
index 1633fae0c34..11156f36c7e 100644
--- a/tests/bluetooth/tester/src/btp_mesh.c
+++ b/tests/bluetooth/tester/src/btp_mesh.c
@@ -4,28 +4,41 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/bluetooth/bluetooth.h>
-
 #include <assert.h>
 #include <errno.h>
+#include <stdint.h>
+#include <string.h>
+#include <va.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/mesh.h>
+#include <zephyr/bluetooth/mesh/access.h>
 #include <zephyr/bluetooth/mesh/cfg.h>
-#include <zephyr/sys/byteorder.h>
+#include <zephyr/bluetooth/mesh/cfg_cli.h>
+#include <zephyr/bluetooth/mesh/cfg_srv.h>
+#include <zephyr/bluetooth/mesh/health_cli.h>
+#include <zephyr/bluetooth/mesh/health_srv.h>
+#include <zephyr/bluetooth/mesh/main.h>
+#include <zephyr/bluetooth/mesh/msg.h>
+#include <zephyr/bluetooth/mesh/proxy.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
 #include <zephyr/settings/settings.h>
-#include <app_keys.h>
-#include <va.h>
-#include <sar_cfg_internal.h>
-#include <string.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys/util_macro.h>
+#include <zephyr/sys_clock.h>
+
 #include "mesh/access.h"
+#include "mesh/dfu_slot.h"
 #include "mesh/testing.h"
 
-#include <zephyr/logging/log.h>
+#include "btp/btp.h"
+
 #define LOG_MODULE_NAME bttester_mesh
 LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_BTTESTER_LOG_LEVEL);
 
-#include "btp/btp.h"
-#include "dfu_slot.h"
-
 #define CID_LOCAL 0x05F1
 #define COMPANY_ID_LF 0x05F1
 #define COMPANY_ID_NORDIC_SEMI 0x05F9
@@ -473,104 +486,8 @@ static uint8_t supported_commands(const void *cmd, uint16_t cmd_len,
 {
 	struct btp_mesh_read_supported_commands_rp *rp = rsp;
 
-	/* octet 0 */
-	tester_set_bit(rp->data, BTP_MESH_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_MESH_CONFIG_PROVISIONING);
-	tester_set_bit(rp->data, BTP_MESH_PROVISION_NODE);
-	tester_set_bit(rp->data, BTP_MESH_INIT);
-	tester_set_bit(rp->data, BTP_MESH_RESET);
-	tester_set_bit(rp->data, BTP_MESH_INPUT_NUMBER);
-	tester_set_bit(rp->data, BTP_MESH_INPUT_STRING);
-
-	/* octet 1 */
-	tester_set_bit(rp->data, BTP_MESH_IVU_TEST_MODE);
-	tester_set_bit(rp->data, BTP_MESH_IVU_TOGGLE_STATE);
-	tester_set_bit(rp->data, BTP_MESH_NET_SEND);
-	tester_set_bit(rp->data, BTP_MESH_HEALTH_GENERATE_FAULTS);
-	tester_set_bit(rp->data, BTP_MESH_HEALTH_CLEAR_FAULTS);
-	tester_set_bit(rp->data, BTP_MESH_LPN);
-	tester_set_bit(rp->data, BTP_MESH_LPN_POLL);
-	tester_set_bit(rp->data, BTP_MESH_MODEL_SEND);
-
-	/* octet 2 */
-#if defined(CONFIG_BT_TESTING)
-	tester_set_bit(rp->data, BTP_MESH_LPN_SUBSCRIBE);
-	tester_set_bit(rp->data, BTP_MESH_LPN_UNSUBSCRIBE);
-	tester_set_bit(rp->data, BTP_MESH_RPL_CLEAR);
-#endif /* CONFIG_BT_TESTING */
-	tester_set_bit(rp->data, BTP_MESH_PROXY_IDENTITY);
-	tester_set_bit(rp->data, BTP_MESH_COMP_DATA_GET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_BEACON_GET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_BEACON_SET);
-
-	/* octet 3 */
-	tester_set_bit(rp->data, BTP_MESH_CFG_DEFAULT_TTL_GET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_DEFAULT_TTL_SET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_GATT_PROXY_GET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_GATT_PROXY_SET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_FRIEND_GET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_FRIEND_SET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_RELAY_GET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_RELAY_SET);
-
-	/* octet 4 */
-	tester_set_bit(rp->data, BTP_MESH_CFG_MODEL_PUB_GET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_MODEL_PUB_SET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_MODEL_SUB_ADD);
-	tester_set_bit(rp->data, BTP_MESH_CFG_MODEL_SUB_DEL);
-	tester_set_bit(rp->data, BTP_MESH_CFG_NETKEY_ADD);
-	tester_set_bit(rp->data, BTP_MESH_CFG_NETKEY_GET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_NETKEY_DEL);
-	tester_set_bit(rp->data, BTP_MESH_CFG_APPKEY_ADD);
-
-	/* octet 5 */
-	tester_set_bit(rp->data, BTP_MESH_CFG_APPKEY_DEL);
-	tester_set_bit(rp->data, BTP_MESH_CFG_APPKEY_GET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_MODEL_APP_BIND);
-	tester_set_bit(rp->data, BTP_MESH_CFG_MODEL_APP_UNBIND);
-	tester_set_bit(rp->data, BTP_MESH_CFG_MODEL_APP_GET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_MODEL_APP_VND_GET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_HEARTBEAT_PUB_SET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_HEARTBEAT_PUB_GET);
-
-	/* octet 6 */
-	tester_set_bit(rp->data, BTP_MESH_CFG_HEARTBEAT_SUB_SET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_HEARTBEAT_SUB_GET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_NET_TRANS_GET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_NET_TRANS_SET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_MODEL_SUB_OVW);
-	tester_set_bit(rp->data, BTP_MESH_CFG_MODEL_SUB_DEL_ALL);
-	tester_set_bit(rp->data, BTP_MESH_CFG_MODEL_SUB_GET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_MODEL_SUB_GET_VND);
-
-	/* octet 7 */
-	tester_set_bit(rp->data, BTP_MESH_CFG_MODEL_SUB_VA_ADD);
-	tester_set_bit(rp->data, BTP_MESH_CFG_MODEL_SUB_VA_DEL);
-	tester_set_bit(rp->data, BTP_MESH_CFG_MODEL_SUB_VA_OVW);
-	tester_set_bit(rp->data, BTP_MESH_CFG_NETKEY_UPDATE);
-	tester_set_bit(rp->data, BTP_MESH_CFG_APPKEY_UPDATE);
-	tester_set_bit(rp->data, BTP_MESH_CFG_NODE_IDT_SET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_NODE_IDT_GET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_NODE_RESET);
-
-	/* octet 8 */
-	tester_set_bit(rp->data, BTP_MESH_CFG_LPN_TIMEOUT_GET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_MODEL_APP_BIND_VND);
-	tester_set_bit(rp->data, BTP_MESH_HEALTH_FAULT_GET);
-	tester_set_bit(rp->data, BTP_MESH_HEALTH_FAULT_CLEAR);
-	tester_set_bit(rp->data, BTP_MESH_HEALTH_PERIOD_GET);
-	tester_set_bit(rp->data, BTP_MESH_HEALTH_PERIOD_SET);
-
-	/* octet 9 */
-	tester_set_bit(rp->data, BTP_MESH_HEALTH_ATTENTION_GET);
-	tester_set_bit(rp->data, BTP_MESH_HEALTH_ATTENTION_SET);
-	tester_set_bit(rp->data, BTP_MESH_PROVISION_ADV);
-	tester_set_bit(rp->data, BTP_MESH_CFG_KRP_GET);
-	tester_set_bit(rp->data, BTP_MESH_CFG_KRP_SET);
-	tester_set_bit(rp->data, BTP_MESH_VA_ADD);
-	tester_set_bit(rp->data, BTP_MESH_VA_DEL);
-
-	*rsp_len = sizeof(*rp) + 10;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_MESH, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
@@ -1540,7 +1457,7 @@ static uint8_t start(const void *cmd, uint16_t cmd_len,
 	LOG_DBG("");
 
 	if (IS_ENABLED(CONFIG_BT_SETTINGS)) {
-		printk("Loading stored settings\n");
+		LOG_INF("Loading stored settings\n");
 		settings_load();
 	}
 
diff --git a/tests/bluetooth/tester/src/btp_ots.c b/tests/bluetooth/tester/src/btp_ots.c
index defea7d2fed..1b0a6d8aff1 100644
--- a/tests/bluetooth/tester/src/btp_ots.c
+++ b/tests/bluetooth/tester/src/btp_ots.c
@@ -5,17 +5,26 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <errno.h>
+#include <inttypes.h>
+#include <stdint.h>
+#include <string.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/conn.h>
 #include <zephyr/bluetooth/services/ots.h>
+#include <zephyr/bluetooth/uuid.h>
+#include <zephyr/logging/log.h>
 
 #include <zephyr/sys/byteorder.h>
-#include <stdint.h>
+#include <zephyr/sys/util.h>
+#include <sys/types.h>
+
+#include "btp/btp.h"
 
-#include <zephyr/logging/log.h>
 #define LOG_MODULE_NAME bttester_ots
 LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_BTTESTER_LOG_LEVEL);
 
-#include "btp/btp.h"
-
 #define OBJ_POOL_SIZE CONFIG_BT_OTS_MAX_OBJ_CNT
 #define OBJ_MAX_SIZE  100
 
@@ -42,10 +51,8 @@ static uint8_t ots_supported_commands(const void *cmd, uint16_t cmd_len,
 {
 	struct btp_ots_read_supported_commands_rp *rp = rsp;
 
-	tester_set_bit(rp->data, BTP_OTS_READ_SUPPORTED_COMMANDS);
-	tester_set_bit(rp->data, BTP_OTS_REGISTER_OBJECT);
-
-	*rsp_len = sizeof(*rp) + 1;
+	*rsp_len = tester_supported_commands(BTP_SERVICE_ID_OTS, rp->data);
+	*rsp_len += sizeof(*rp);
 
 	return BTP_STATUS_SUCCESS;
 }
diff --git a/tests/bluetooth/tester/src/main.c b/tests/bluetooth/tester/src/main.c
index 6951feab3ce..8a0628ef39a 100644
--- a/tests/bluetooth/tester/src/main.c
+++ b/tests/bluetooth/tester/src/main.c
@@ -6,11 +6,9 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/kernel.h>
-#include <zephyr/types.h>
-#include <zephyr/toolchain.h>
-
+#include <zephyr/autoconf.h>
 #include <zephyr/logging/log.h>
+
 #define LOG_MODULE_NAME bttester_main
 LOG_MODULE_REGISTER(LOG_MODULE_NAME, CONFIG_BTTESTER_LOG_LEVEL);
 
diff --git a/tests/bluetooth/tester/testcase.yaml b/tests/bluetooth/tester/testcase.yaml
index b9946b9d610..4439f051c82 100644
--- a/tests/bluetooth/tester/testcase.yaml
+++ b/tests/bluetooth/tester/testcase.yaml
@@ -1,3 +1,7 @@
+common:
+  build_only: true
+  tags: bluetooth
+
 tests:
   bluetooth.general.tester:
     build_only: true
@@ -7,6 +11,12 @@ tests:
       - nrf52840dk/nrf52840
     tags: bluetooth
     harness: bluetooth
+  bluetooth.general.tester_bsim:
+    platform_allow:
+      - nrf52_bsim/native
+    harness: bsim
+    harness_config:
+      bsim_exe_name: tests_bluetooth_tester_prj_conf
   bluetooth.general.tester.nxp:
     # Disabling monolithic since CI environment doesn't use blobs
     build_only: true
@@ -30,6 +40,16 @@ tests:
       - EXTRA_CONF_FILE="hci_ipc.conf"
     tags: bluetooth
     sysbuild: true
+  bluetooth.general.tester_hci_ipc_bsim:
+    platform_allow:
+      - nrf5340bsim/nrf5340/cpuapp
+    harness: bsim
+    harness_config:
+      bsim_exe_name: tests_bluetooth_tester_prj_conf
+    extra_args:
+      # Build config used by AutoPTS for nRF53
+      - EXTRA_CONF_FILE="hci_ipc.conf"
+    sysbuild: true
   bluetooth.general.tester_le_audio:
     build_only: true
     platform_allow:
@@ -54,3 +74,22 @@ tests:
     extra_args: EXTRA_CONF_FILE="overlay-mesh.conf"
     tags: bluetooth
     harness: bluetooth
+  bluetooth.general.tester.legacy_adv:
+    build_only: true
+    platform_allow:
+      - qemu_x86
+      - native_sim
+      - nrf52840dk/nrf52840
+    extra_configs:
+      - CONFIG_BT_EXT_ADV=n
+    tags: bluetooth
+    harness: bluetooth
+  bluetooth.general.tester_br_edr:
+    build_only: true
+    platform_allow:
+      - mimxrt1170_evk@B/mimxrt1176/cm7
+    extra_args:
+      - EXTRA_CONF_FILE="prj_br.conf"
+      - CONFIG_BUILD_ONLY_NO_BLOBS=y
+    tags: bluetooth
+    harness: bluetooth
diff --git a/tests/boards/espressif/cache_coex/prj.conf b/tests/boards/espressif/cache_coex/prj.conf
index 7dd9dfcd5e8..fcbffd3cd84 100644
--- a/tests/boards/espressif/cache_coex/prj.conf
+++ b/tests/boards/espressif/cache_coex/prj.conf
@@ -1,6 +1,5 @@
 CONFIG_ESP_SPIRAM=y
 CONFIG_HEAP_MEM_POOL_SIZE=98304
-CONFIG_ESP_HEAP_SEARCH_ALL_REGIONS=n
 CONFIG_FLASH=y
 CONFIG_ENTROPY_GENERATOR=y
 CONFIG_ZTEST=y
diff --git a/tests/boards/espressif/rtc_clk/README.rst b/tests/boards/espressif/rtc_clk/README.rst
index 8cd4853517e..48db070183c 100644
--- a/tests/boards/espressif/rtc_clk/README.rst
+++ b/tests/boards/espressif/rtc_clk/README.rst
@@ -14,7 +14,7 @@ Supported Boards
 ****************
 - esp32_devkitc_wrover/esp32/procpu
 - esp32c3_devkitm
-- esp32c6_devkitc
+- esp32c6_devkitc/esp32c6/hpcore
 - esp32s2_saola
 - esp32s3_devkitm/esp32s3/procpu
 
diff --git a/tests/boards/espressif/rtc_clk/testcase.yaml b/tests/boards/espressif/rtc_clk/testcase.yaml
index 5d0cb264b1c..2a13a3728f9 100644
--- a/tests/boards/espressif/rtc_clk/testcase.yaml
+++ b/tests/boards/espressif/rtc_clk/testcase.yaml
@@ -1,19 +1,19 @@
 common:
   integration_platforms:
-    - esp32c6_devkitc
+    - esp32c6_devkitc/esp32c6/hpcore
 tests:
   boards.esp32.rtc_clk:
     platform_allow:
       - esp32_devkitc_wrover/esp32/procpu
       - esp32c3_devkitm
-      - esp32c6_devkitc
+      - esp32c6_devkitc/esp32c6/hpcore
       - esp32s2_saola
       - esp32s3_devkitm/esp32s3/procpu
   boards.esp32.rtc_clk.xtal:
     platform_allow:
       - esp32_devkitc_wrover/esp32/procpu
       - esp32c3_devkitm
-      - esp32c6_devkitc
+      - esp32c6_devkitc/esp32c6/hpcore
       - esp32s2_saola
       - esp32s3_devkitm/esp32s3/procpu
     harness_config:
diff --git a/samples/net/wifi/shell/socs/esp32c6.overlay b/tests/boards/espressif/wifi/socs/esp32c3_usb.overlay
similarity index 100%
rename from samples/net/wifi/shell/socs/esp32c6.overlay
rename to tests/boards/espressif/wifi/socs/esp32c3_usb.overlay
diff --git a/tests/boards/espressif/wifi/socs/esp32c6.overlay b/tests/boards/espressif/wifi/socs/esp32c6_hpcore.overlay
similarity index 100%
rename from tests/boards/espressif/wifi/socs/esp32c6.overlay
rename to tests/boards/espressif/wifi/socs/esp32c6_hpcore.overlay
diff --git a/tests/boards/intel_adsp/ssp/prj.conf b/tests/boards/intel_adsp/ssp/prj.conf
index 1cb2bd509d0..ce2420c87f5 100644
--- a/tests/boards/intel_adsp/ssp/prj.conf
+++ b/tests/boards/intel_adsp/ssp/prj.conf
@@ -5,3 +5,4 @@ CONFIG_HEAP_MEM_POOL_SIZE=512
 CONFIG_PM=y
 CONFIG_PM_DEVICE=y
 CONFIG_PM_DEVICE_RUNTIME=y
+CONFIG_TEST_LOGGING_DEFAULTS=n
diff --git a/tests/boards/intel_adsp/ssp/src/main.c b/tests/boards/intel_adsp/ssp/src/main.c
index 4b0b8f09bd0..3069a5c4160 100644
--- a/tests/boards/intel_adsp/ssp/src/main.c
+++ b/tests/boards/intel_adsp/ssp/src/main.c
@@ -260,88 +260,67 @@ ZTEST(adsp_ssp, test_adsp_ssp_transfer)
 	const struct dai_properties *props;
 	static int chan_id_rx;
 	static int chan_id;
+	int status;
 
 	props = dai_get_properties(dev_dai_ssp, DAI_DIR_TX, 0);
-	if (!props) {
-		TC_PRINT("Cannot get dai tx properties\n");
-		return;
-	}
+	zassert_not_null(props, "Cannot get dai tx properties\n");
 
-	if (config_output_dma(props, &chan_id)) {
-		TC_PRINT("ERROR: config tx dma (%d)\n", chan_id);
-		return;
-	}
+	status = config_output_dma(props, &chan_id);
+	zassert_equal(status, 0, "ERROR: config tx dma (%d)\n", chan_id);
 
 	TC_PRINT("Configuring the dma tx transfer on channel %d\n", chan_id);
 
-	if (dma_config(dev_dma_dw, chan_id, &dma_cfg)) {
-		TC_PRINT("ERROR: dma tx config (%d)\n", chan_id);
-		return;
-	}
+	status = dma_config(dev_dma_dw, chan_id, &dma_cfg);
+	zassert_equal(status, 0, "ERROR: dma tx config (%d)\n", chan_id);
 
 	props = dai_get_properties(dev_dai_ssp, DAI_DIR_RX, 0);
-	if (!props) {
-		TC_PRINT("Cannot get dai rx properties\n");
-		return;
-	}
+	zassert_not_null(props, "Cannot get dai rx properties\n");
 
-	if (config_input_dma(props, &chan_id_rx)) {
-		TC_PRINT("ERROR: config rx dma (%d)\n", chan_id);
-		return;
-	}
+	status = config_input_dma(props, &chan_id_rx);
+	zassert_equal(status, 0, "ERROR: config rx dma (%d)\n", chan_id);
 
 	TC_PRINT("Configuring the dma rx transfer on channel %d\n", chan_id_rx);
 
-	if (dma_config(dev_dma_dw, chan_id_rx, &dma_cfg_rx)) {
-		TC_PRINT("ERROR: transfer config (%d)\n", chan_id_rx);
-		return;
-	}
+	status = dma_config(dev_dma_dw, chan_id_rx, &dma_cfg_rx);
+	zassert_equal(status, 0, "ERROR: transfer config (%d)\n", chan_id_rx);
 
 	TC_PRINT("Starting the transfer on channels %d and %d and waiting completion\n", chan_id,
 		 chan_id_rx);
 
-	if (dai_trigger(dev_dai_ssp, DAI_DIR_RX, DAI_TRIGGER_PRE_START)) {
-		TC_PRINT("ERROR: dai rx pre start\n");
-		return;
-	}
+	status = dai_trigger(dev_dai_ssp, DAI_DIR_RX, DAI_TRIGGER_PRE_START);
+	zassert_equal(status, 0, "ERROR: dai rx pre start\n");
 
-	if (dai_trigger(dev_dai_ssp, DAI_DIR_TX, DAI_TRIGGER_PRE_START)) {
-		TC_PRINT("ERROR: dai tx pre start\n");
-		return;
-	}
+	status = dai_trigger(dev_dai_ssp, DAI_DIR_TX, DAI_TRIGGER_PRE_START);
+	zassert_equal(status, 0, "ERROR: dai tx pre start\n");
 
-	if (dma_start(dev_dma_dw, chan_id_rx)) {
-		TC_PRINT("ERROR: dma rx transfer start (%d)\n", chan_id);
-		return;
-	}
+	status = dma_start(dev_dma_dw, chan_id_rx);
+	zassert_equal(status, 0, "ERROR: dma rx transfer start (%d)\n", chan_id);
+	status = dma_start(dev_dma_dw, chan_id);
+	zassert_equal(status, 0, "ERROR: dma tx transfer start (%d)\n", chan_id);
 
-	if (dma_start(dev_dma_dw, chan_id)) {
-		TC_PRINT("ERROR: dma tx transfer start (%d)\n", chan_id);
-		return;
-	}
+	status = dai_trigger(dev_dai_ssp, DAI_DIR_RX, DAI_TRIGGER_START);
+	zassert_equal(status, 0, "ERROR: rx dai start\n");
 
-	if (dai_trigger(dev_dai_ssp, DAI_DIR_RX, DAI_TRIGGER_START)) {
-		TC_PRINT("ERROR: rx dai start\n");
-		return;
-	}
+	status = dai_trigger(dev_dai_ssp, DAI_DIR_TX, DAI_TRIGGER_START);
+	zassert_equal(status, 0, "ERROR: tx dai start\n");
 
-	if (dai_trigger(dev_dai_ssp, DAI_DIR_TX, DAI_TRIGGER_START)) {
-		TC_PRINT("ERROR: tx dai start\n");
-		return;
-	}
+	status = k_sem_take(&xfer_sem, K_MSEC(1000));
+	zassert_equal(status, 0, "Timed out waiting for xfers\n");
 
+	status = dma_stop(dev_dma_dw, chan_id_rx);
+	zassert_equal(status, 0, "ERROR: rx dma stop");
 
-	if (k_sem_take(&xfer_sem, K_MSEC(1000)) != 0) {
-		TC_PRINT("timed out waiting for xfers\n");
-		return;
-	}
+	status = dma_stop(dev_dma_dw, chan_id);
+	zassert_equal(status, 0, "ERROR: rx dma stop");
+
+	status = dai_trigger(dev_dai_ssp, DAI_DIR_RX, DAI_TRIGGER_STOP);
+	zassert_equal(status, 0, "ERROR: rx dai stop");
 
-	dma_stop(dev_dma_dw, chan_id_rx);
-	dma_stop(dev_dma_dw, chan_id);
-	dai_trigger(dev_dai_ssp, DAI_DIR_RX, DAI_TRIGGER_STOP);
-	dai_trigger(dev_dai_ssp, DAI_DIR_TX, DAI_TRIGGER_STOP);
+	status = dai_trigger(dev_dai_ssp, DAI_DIR_TX, DAI_TRIGGER_STOP);
+	zassert_equal(status, 0, "ERROR: tx dai stop");
 
-	check_transmission();
+	status = check_transmission();
+	zassert_equal(status, TC_PASS, "Error detected in transmission");
 }
 
 ZTEST(adsp_ssp, test_adsp_ssp_config_set)
diff --git a/tests/boards/mec15xxevb_assy6853/qspi/src/main.c b/tests/boards/mec15xxevb_assy6853/qspi/src/main.c
index 22c17ec0eb5..1c8e34b4a2a 100644
--- a/tests/boards/mec15xxevb_assy6853/qspi/src/main.c
+++ b/tests/boards/mec15xxevb_assy6853/qspi/src/main.c
@@ -670,7 +670,7 @@ void *spi_single_setup(void)
 	spi_single_init();
 
 	/* The writing test goes
-	 * first berfore testing
+	 * first before testing
 	 * the reading.
 	 */
 	test_spi_single_write();
@@ -683,7 +683,7 @@ void *spi_quad_setup(void)
 	spi_dual_init();
 
 	/* The writing test goes
-	 * first berfore testing
+	 * first before testing
 	 * the reading.
 	 */
 	test_spi_quad_write();
diff --git a/tests/boards/mec172xevb_assy6906/qspi/src/main.c b/tests/boards/mec172xevb_assy6906/qspi/src/main.c
index feac946c46e..94437b93335 100644
--- a/tests/boards/mec172xevb_assy6906/qspi/src/main.c
+++ b/tests/boards/mec172xevb_assy6906/qspi/src/main.c
@@ -630,7 +630,7 @@ void *spi_single_setup(void)
 	spi_single_init();
 
 	/* The writing test goes
-	 * first berfore testing
+	 * first before testing
 	 * the reading.
 	 */
 	test_spi_single_write();
@@ -643,7 +643,7 @@ void *spi_quad_setup(void)
 	spi_dual_init();
 
 	/* The writing test goes
-	 * first berfore testing
+	 * first before testing
 	 * the reading.
 	 */
 	test_spi_quad_write();
diff --git a/tests/boards/native_sim/cpu_wait/src/main.c b/tests/boards/native_sim/cpu_wait/src/main.c
index 622b7579ef1..5d7e2abf86e 100644
--- a/tests/boards/native_sim/cpu_wait/src/main.c
+++ b/tests/boards/native_sim/cpu_wait/src/main.c
@@ -102,7 +102,7 @@ static void thread_entry(void *p1, void *p2, void *p3)
  * takes time during this test thread waits
  *
  * Note: This test relies on the exact timing of the ticks.
- * For native_posix it works, with a tick of 10ms. In general this test will
+ * For native_sim it works, with a tick of 10ms. In general this test will
  * probably give problems if the tick time is not a relatively even number
  * of microseconds
  */
@@ -214,8 +214,8 @@ static void np_timer_isr_test_replacement(const void *arg)
  */
 ZTEST(native_cpu_hold, test_cpu_hold_with_interrupts)
 {
-#if defined(CONFIG_BOARD_NATIVE_POSIX) || defined(CONFIG_BOARD_NATIVE_SIM)
-	/* So far we only have a test for native_posix.
+#if defined(CONFIG_BOARD_NATIVE_SIM)
+	/* So far we only have a test for native_sim.
 	 * As the test hooks into an interrupt to cause an extra delay
 	 * this is very platform specific
 	 */
@@ -287,7 +287,7 @@ ZTEST(native_cpu_hold, test_cpu_hold_with_interrupts)
 			PRIu64"-"PRIu64"!="PRIu32"\n",
 			time2, time1, ONE_TICK_TIME);
 
-#endif /* defined(CONFIG_BOARD_NATIVE_POSIX) */
+#endif /* defined(CONFIG_BOARD_NATIVE_SIM) */
 }
 
 ZTEST_SUITE(native_cpu_hold, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/boards/native_sim/cpu_wait/testcase.yaml b/tests/boards/native_sim/cpu_wait/testcase.yaml
index aeec84197ef..6d658851105 100644
--- a/tests/boards/native_sim/cpu_wait/testcase.yaml
+++ b/tests/boards/native_sim/cpu_wait/testcase.yaml
@@ -2,8 +2,6 @@
 tests:
   boards.native_sim.cpu_wait:
     platform_allow:
-      - native_posix
-      - native_posix/native/64
       - native_sim
       - native_sim/native/64
     integration_platforms:
diff --git a/tests/boards/native_sim/rtc/prj.conf b/tests/boards/native_sim/rtc/prj.conf
index 686b5a9dee3..2efaae4297d 100644
--- a/tests/boards/native_sim/rtc/prj.conf
+++ b/tests/boards/native_sim/rtc/prj.conf
@@ -1,2 +1,2 @@
-CONFIG_NATIVE_POSIX_SLOWDOWN_TO_REAL_TIME=y
+CONFIG_NATIVE_SIM_SLOWDOWN_TO_REAL_TIME=y
 CONFIG_ZTEST=y
diff --git a/tests/boards/native_sim/rtc/src/main.c b/tests/boards/native_sim/rtc/src/main.c
index 3cb783202de..26177814868 100644
--- a/tests/boards/native_sim/rtc/src/main.c
+++ b/tests/boards/native_sim/rtc/src/main.c
@@ -12,7 +12,8 @@
 #include <stdio.h>
 #include <time.h>
 
-#include "timer_model.h"
+#include <nsi_hw_scheduler.h>
+#include <nsi_timer_model.h>
 #include "native_rtc.h"
 
 #include <stdio.h>
@@ -39,11 +40,11 @@ static char *us_time_to_str(char *dest, uint64_t time)
 }
 
 #define WAIT_TIME 250 /* ms */
-#define TOLERANCE 20 /* ms Tolerance in native_posix time after WAIT_TIME */
+#define TOLERANCE 20  /* ms Tolerance in native_sim time after WAIT_TIME */
 #define TICK_MS (1000ul / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
 
 /**
- * @brief Test native_posix real time control
+ * @brief Test native_sim real time control
  */
 ZTEST(native_realtime, test_realtime)
 {
@@ -141,7 +142,7 @@ ZTEST(native_realtime, test_realtime)
 }
 
 /**
- * @brief Test native_posix RTC offset functionality
+ * @brief Test native_sim RTC offset functionality
  */
 ZTEST(native_realtime,  test_rtc_offset)
 {
diff --git a/tests/boards/native_sim/rtc/testcase.yaml b/tests/boards/native_sim/rtc/testcase.yaml
index 1b3da5135b2..db26ded54ce 100644
--- a/tests/boards/native_sim/rtc/testcase.yaml
+++ b/tests/boards/native_sim/rtc/testcase.yaml
@@ -1,9 +1,7 @@
-# Test of the native_posix real timeness and RTC model
+# Test of the native_sim real timeness and RTC model
 tests:
   boards.native.rtc:
     platform_allow:
-      - native_posix
-      - native_posix/native/64
       - native_sim
       - native_sim/native/64
     integration_platforms:
diff --git a/tests/boards/neorv32/build_all/CMakeLists.txt b/tests/boards/neorv32/build_all/CMakeLists.txt
new file mode 100644
index 00000000000..583805f63fa
--- /dev/null
+++ b/tests/boards/neorv32/build_all/CMakeLists.txt
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2025 Henrik Brix Andersen <henrik@brixandersen.dk>
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(build_all_neorv32)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/boards/neorv32/build_all/app.overlay b/tests/boards/neorv32/build_all/app.overlay
new file mode 100644
index 00000000000..c55c48a3dd5
--- /dev/null
+++ b/tests/boards/neorv32/build_all/app.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025 Henrik Brix Andersen <henrik@brixandersen.dk>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&gpio {
+	status = "okay";
+	ngpios = <32>;
+};
+
+&trng {
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <19200>;
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+};
diff --git a/tests/boards/neorv32/build_all/prj.conf b/tests/boards/neorv32/build_all/prj.conf
new file mode 100644
index 00000000000..4708f7d579d
--- /dev/null
+++ b/tests/boards/neorv32/build_all/prj.conf
@@ -0,0 +1,9 @@
+CONFIG_TEST=y
+CONFIG_TEST_USERSPACE=y
+
+CONFIG_GPIO=y
+CONFIG_ENTROPY_GENERATOR=y
+
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_UART_USE_RUNTIME_CONFIGURE=y
diff --git a/tests/boards/neorv32/build_all/src/main.c b/tests/boards/neorv32/build_all/src/main.c
new file mode 100644
index 00000000000..1c30472d36a
--- /dev/null
+++ b/tests/boards/neorv32/build_all/src/main.c
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2025 Henrik Brix Andersen <henrik@brixandersen.dk>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+int main(void)
+{
+	return 0;
+}
diff --git a/tests/boards/neorv32/build_all/testcase.yaml b/tests/boards/neorv32/build_all/testcase.yaml
new file mode 100644
index 00000000000..b8b49fc51e3
--- /dev/null
+++ b/tests/boards/neorv32/build_all/testcase.yaml
@@ -0,0 +1,11 @@
+tests:
+  boards.neorv32.build_all:
+    build_only: true
+    tags:
+      - drivers
+      - entropy
+      - gpio
+      - uart
+    platform_allow: neorv32/neorv32/minimalboot
+    integration_platforms:
+      - neorv32/neorv32/minimalboot
diff --git a/tests/boards/nrf/comp/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/boards/nrf/comp/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..76cb1918038
--- /dev/null
+++ b/tests/boards/nrf/comp/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		test-comp = &comp;
+	};
+
+	zephyr,user {
+		first-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+		second-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&led3 {
+	status = "disabled";
+};
+
+&button0 {
+	status = "disabled";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&comp {
+	status = "okay";
+	psel = "AIN4";
+	refsel = "AREF";
+	extrefsel= "AIN3";
+	sp-mode = "NORMAL";
+	th-up = <36>;
+	th-down = <30>;
+	isource = "DISABLED";
+	enable-hyst;
+};
diff --git a/tests/boards/nrf/comp/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/boards/nrf/comp/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..76cb1918038
--- /dev/null
+++ b/tests/boards/nrf/comp/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		test-comp = &comp;
+	};
+
+	zephyr,user {
+		first-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+		second-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&led3 {
+	status = "disabled";
+};
+
+&button0 {
+	status = "disabled";
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&comp {
+	status = "okay";
+	psel = "AIN4";
+	refsel = "AREF";
+	extrefsel= "AIN3";
+	sp-mode = "NORMAL";
+	th-up = <36>;
+	th-down = <30>;
+	isource = "DISABLED";
+	enable-hyst;
+};
diff --git a/tests/boards/nrf/coresight_stm/testcase.yaml b/tests/boards/nrf/coresight_stm/testcase.yaml
index 308f231274c..5a1d2831f9a 100644
--- a/tests/boards/nrf/coresight_stm/testcase.yaml
+++ b/tests/boards/nrf/coresight_stm/testcase.yaml
@@ -2,7 +2,7 @@ sample:
   name: Logging using Coresight STM on nrf54h20
 
 common:
-  tags: stm
+  tags: coresight_stm
   sysbuild: true
   platform_allow:
     - nrf54h20dk/nrf54h20/cpuapp
diff --git a/tests/boards/nrf/hwinfo/reset_cause/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/boards/nrf/hwinfo/reset_cause/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..567c80da4c6
--- /dev/null
+++ b/tests/boards/nrf/hwinfo/reset_cause/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/boards/nrf/hwinfo/reset_cause/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/boards/nrf/hwinfo/reset_cause/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..567c80da4c6
--- /dev/null
+++ b/tests/boards/nrf/hwinfo/reset_cause/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15_dvk_nrf54l15_cpuapp.conf b/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15_dvk_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..eae536f3656
--- /dev/null
+++ b/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15_dvk_nrf54l15_cpuapp.conf
@@ -0,0 +1,5 @@
+# Copyright 2024 Nordic Semiconductor ASA
+# Copyright 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_NRFX_TWIS22=y
diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..38146db3269
--- /dev/null
+++ b/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		i2c-slave = &i2c22;
+	};
+};
+
+&pinctrl {
+	i2c21_default_alt: i2c21_default_alt {
+		group1 {
+			psels = <NRF_PSEL(TWIM_SDA, 1, 8)>,
+				<NRF_PSEL(TWIM_SCL, 1, 12)>;
+		};
+	};
+
+	i2c21_sleep_alt: i2c21_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(TWIM_SDA, 1, 8)>,
+				<NRF_PSEL(TWIM_SCL, 1, 12)>;
+			low-power-enable;
+		};
+	};
+
+	i2c22_default_alt: i2c22_default_alt {
+		group1 {
+/* Temporary workaround as it is currently not possible
+ * to configure pins for TWIS with pinctrl.
+ */
+			psels = <NRF_PSEL(TWIM_SDA, 1, 9)>,
+				<NRF_PSEL(TWIM_SCL, 1, 13)>;
+			bias-pull-up;
+		};
+	};
+
+	i2c22_sleep_alt: i2c22_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(TWIM_SDA, 1, 9)>,
+				<NRF_PSEL(TWIM_SCL, 1, 13)>;
+			low-power-enable;
+		};
+	};
+};
+
+&i2c21 {
+	compatible = "nordic,nrf-twim";
+	status = "okay";
+	pinctrl-0 = <&i2c21_default_alt>;
+	pinctrl-1 = <&i2c21_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+
+	sensor: sensor@54 {
+		reg = <0x54>;
+	};
+};
+
+&i2c22 {
+	compatible = "nordic,nrf-twis";
+	status = "okay";
+	pinctrl-0 = <&i2c22_default_alt>;
+	pinctrl-1 = <&i2c22_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf b/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..eae536f3656
--- /dev/null
+++ b/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf
@@ -0,0 +1,5 @@
+# Copyright 2024 Nordic Semiconductor ASA
+# Copyright 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_NRFX_TWIS22=y
diff --git a/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..38146db3269
--- /dev/null
+++ b/tests/boards/nrf/i2c/i2c_slave/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		i2c-slave = &i2c22;
+	};
+};
+
+&pinctrl {
+	i2c21_default_alt: i2c21_default_alt {
+		group1 {
+			psels = <NRF_PSEL(TWIM_SDA, 1, 8)>,
+				<NRF_PSEL(TWIM_SCL, 1, 12)>;
+		};
+	};
+
+	i2c21_sleep_alt: i2c21_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(TWIM_SDA, 1, 8)>,
+				<NRF_PSEL(TWIM_SCL, 1, 12)>;
+			low-power-enable;
+		};
+	};
+
+	i2c22_default_alt: i2c22_default_alt {
+		group1 {
+/* Temporary workaround as it is currently not possible
+ * to configure pins for TWIS with pinctrl.
+ */
+			psels = <NRF_PSEL(TWIM_SDA, 1, 9)>,
+				<NRF_PSEL(TWIM_SCL, 1, 13)>;
+			bias-pull-up;
+		};
+	};
+
+	i2c22_sleep_alt: i2c22_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(TWIM_SDA, 1, 9)>,
+				<NRF_PSEL(TWIM_SCL, 1, 13)>;
+			low-power-enable;
+		};
+	};
+};
+
+&i2c21 {
+	compatible = "nordic,nrf-twim";
+	status = "okay";
+	pinctrl-0 = <&i2c21_default_alt>;
+	pinctrl-1 = <&i2c21_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+
+	sensor: sensor@54 {
+		reg = <0x54>;
+	};
+};
+
+&i2c22 {
+	compatible = "nordic,nrf-twis";
+	status = "okay";
+	pinctrl-0 = <&i2c22_default_alt>;
+	pinctrl-1 = <&i2c22_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/tests/boards/nrf/nrf70/bustest/CMakeLists.txt b/tests/boards/nrf/nrf70/bustest/CMakeLists.txt
index 741d622b119..10acadb3fcc 100644
--- a/tests/boards/nrf/nrf70/bustest/CMakeLists.txt
+++ b/tests/boards/nrf/nrf70/bustest/CMakeLists.txt
@@ -1,7 +1,7 @@
 #
 # Copyright (c) 2024 Nordic Semiconductor ASA
 #
-# SPDX-License-Identifier: BSD-3-Clause
+# SPDX-License-Identifier: Apache-2.0
 #
 
 cmake_minimum_required(VERSION 3.20.0)
diff --git a/tests/boards/nrf/nrf70/bustest/testcase.yaml b/tests/boards/nrf/nrf70/bustest/testcase.yaml
index fa520202bec..af5ee1934ca 100644
--- a/tests/boards/nrf/nrf70/bustest/testcase.yaml
+++ b/tests/boards/nrf/nrf70/bustest/testcase.yaml
@@ -4,14 +4,14 @@ common:
     - drivers
     - wifi
 tests:
-  nrf_wifi.bustest.nrf7002:
+  boards.nrf_wifi.bustest.nrf7002:
     sysbuild: true
     build_only: true
     integration_platforms:
       - nrf7002dk/nrf5340/cpuapp
     platform_allow: nrf7002dk/nrf5340/cpuapp
 
-  nrf_wifi.bustest.nrf7002ek:
+  boards.nrf.nrf_wifi.bustest.nrf7002ek:
     sysbuild: true
     build_only: true
     extra_args: SHIELD=nrf7002ek
diff --git a/tests/boards/nrf/nrf70/ent_security/CMakeLists.txt b/tests/boards/nrf/nrf70/ent_security/CMakeLists.txt
new file mode 100644
index 00000000000..518596a02f7
--- /dev/null
+++ b/tests/boards/nrf/nrf70/ent_security/CMakeLists.txt
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(build_all)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/boards/nrf/nrf70/ent_security/prj.conf b/tests/boards/nrf/nrf70/ent_security/prj.conf
new file mode 100644
index 00000000000..f354f317b08
--- /dev/null
+++ b/tests/boards/nrf/nrf70/ent_security/prj.conf
@@ -0,0 +1,34 @@
+CONFIG_TEST=y
+CONFIG_TEST_USERSPACE=y
+CONFIG_NET_TEST=y
+
+CONFIG_NETWORKING=y
+CONFIG_NET_IPV4=y
+CONFIG_NET_IPV6=y
+CONFIG_NET_CONFIG_SETTINGS=n
+
+CONFIG_WIFI=y
+CONFIG_WIFI_NM=y
+
+CONFIG_SHELL=y
+CONFIG_NET_SHELL=y
+CONFIG_NET_L2_WIFI_SHELL=y
+CONFIG_NET_L2_WIFI_MGMT=y
+
+CONFIG_WIFI_NM_WPA_SUPPLICANT=y
+CONFIG_WIFI_NM_WPA_SUPPLICANT_DEBUG_LEVEL=0
+CONFIG_WIFI_NM_WPA_SUPPLICANT_CRYPTO_ENTERPRISE=y
+CONFIG_TEST_RANDOM_GENERATOR=y
+CONFIG_EAP_ALL=n
+# EAP frames are ~1100 bytes, so, need higher packet counts as default packet size is 128
+CONFIG_NET_PKT_TX_COUNT=36
+CONFIG_NET_PKT_RX_COUNT=36
+CONFIG_NET_BUF_TX_COUNT=72
+CONFIG_NET_BUF_RX_COUNT=36
+# For TLS and X.509 processing MbedTLS needs large heap size and using separate heap
+# for MbedTLS gives us more control over the heap size.
+CONFIG_MBEDTLS_ENABLE_HEAP=y
+CONFIG_MBEDTLS_HEAP_SIZE=55000
+CONFIG_MBEDTLS_TLS_VERSION_1_2=y
+CONFIG_BUILD_ONLY_NO_BLOBS=y
+CONFIG_MAX_THREAD_BYTES=3
diff --git a/tests/boards/nrf/nrf70/ent_security/src/main.c b/tests/boards/nrf/nrf70/ent_security/src/main.c
new file mode 100644
index 00000000000..86766ee1b34
--- /dev/null
+++ b/tests/boards/nrf/nrf70/ent_security/src/main.c
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+int main(void)
+{
+	return 0;
+}
diff --git a/tests/boards/nrf/nrf70/ent_security/testcase.yaml b/tests/boards/nrf/nrf70/ent_security/testcase.yaml
new file mode 100644
index 00000000000..431ca989244
--- /dev/null
+++ b/tests/boards/nrf/nrf70/ent_security/testcase.yaml
@@ -0,0 +1,62 @@
+common:
+  build_only: true
+  tags:
+    - drivers
+    - wifi
+    - net
+  platform_allow:
+    - nrf7002dk/nrf5340/cpuapp
+tests:
+  wifi.build.crypto_enterprise_typical:
+    extra_configs:
+      - CONFIG_EAP_TLS=y
+      - CONFIG_EAP_TTLS=y
+      - CONFIG_EAP_PEAP=y
+  wifi.build.crypto_enterprise_tls:
+    extra_configs:
+      - CONFIG_EAP_TLS=y
+  wifi.build.crypto_enterprise_ttls:
+    extra_configs:
+      - CONFIG_EAP_TTLS=y
+  wifi.build.crypto_enterprise_peap:
+    extra_configs:
+      - CONFIG_EAP_PEAP=y
+  wifi.build.crypto_enterprise_md5:
+    extra_configs:
+      - CONFIG_EAP_MD5=y
+  wifi.build.crypto_enterprise_mschapv2:
+    extra_configs:
+      - CONFIG_EAP_MSCHAPV2=y
+  wifi.build.crypto_enterprise_leap:
+    extra_configs:
+      - CONFIG_EAP_LEAP=y
+  wifi.build.crypto_enterprise_psk:
+    extra_configs:
+      - CONFIG_EAP_PSK=y
+  wifi.build.crypto_enterprise_pax:
+    extra_configs:
+      - CONFIG_EAP_PAX=y
+  wifi.build.crypto_enterprise_sake:
+    extra_configs:
+      - CONFIG_EAP_SAKE=y
+  wifi.build.crypto_enterprise_gpsk:
+    extra_configs:
+      - CONFIG_EAP_GPSK=y
+  wifi.build.crypto_enterprise_pwd:
+    extra_configs:
+      - CONFIG_EAP_PWD=y
+  wifi.build.crypto_enterprise_eke:
+    extra_configs:
+      - CONFIG_EAP_EKE=y
+  wifi.build.crypto_enterprise_ikev2:
+    extra_configs:
+      - CONFIG_EAP_IKEV2=y
+  wifi.build.crypto_enterprise_sim:
+    extra_configs:
+      - CONFIG_EAP_SIM=y
+  wifi.build.crypto_enterprise_aka:
+    extra_configs:
+      - CONFIG_EAP_AKA=y
+  wifi.build.crypto_enterprise_gtc:
+    extra_configs:
+      - CONFIG_EAP_GTC=y
diff --git a/tests/subsys/nrfs/CMakeLists.txt b/tests/boards/nrf/nrfs/CMakeLists.txt
similarity index 100%
rename from tests/subsys/nrfs/CMakeLists.txt
rename to tests/boards/nrf/nrfs/CMakeLists.txt
diff --git a/tests/subsys/nrfs/Kconfig.sysbuild b/tests/boards/nrf/nrfs/Kconfig.sysbuild
similarity index 100%
rename from tests/subsys/nrfs/Kconfig.sysbuild
rename to tests/boards/nrf/nrfs/Kconfig.sysbuild
diff --git a/tests/subsys/nrfs/README.txt b/tests/boards/nrf/nrfs/README.txt
similarity index 77%
rename from tests/subsys/nrfs/README.txt
rename to tests/boards/nrf/nrfs/README.txt
index 45888e61c3c..a2ebb8e11fa 100644
--- a/tests/subsys/nrfs/README.txt
+++ b/tests/boards/nrf/nrfs/README.txt
@@ -3,5 +3,5 @@ NRFS services request handling performance.
 
 These reaquest are propagated over IPC.
 
-MRAM latency serivice and Temperature service
+MRAM latency service and Temperature service
 are used as benchmarks.
diff --git a/tests/subsys/nrfs/prj.conf b/tests/boards/nrf/nrfs/prj.conf
similarity index 100%
rename from tests/subsys/nrfs/prj.conf
rename to tests/boards/nrf/nrfs/prj.conf
diff --git a/tests/subsys/nrfs/remote/CMakeLists.txt b/tests/boards/nrf/nrfs/remote/CMakeLists.txt
similarity index 100%
rename from tests/subsys/nrfs/remote/CMakeLists.txt
rename to tests/boards/nrf/nrfs/remote/CMakeLists.txt
diff --git a/tests/subsys/nrfs/remote/prj.conf b/tests/boards/nrf/nrfs/remote/prj.conf
similarity index 100%
rename from tests/subsys/nrfs/remote/prj.conf
rename to tests/boards/nrf/nrfs/remote/prj.conf
diff --git a/tests/subsys/nrfs/src/main.c b/tests/boards/nrf/nrfs/src/main.c
similarity index 100%
rename from tests/subsys/nrfs/src/main.c
rename to tests/boards/nrf/nrfs/src/main.c
diff --git a/tests/subsys/nrfs/sysbuild.cmake b/tests/boards/nrf/nrfs/sysbuild.cmake
similarity index 100%
rename from tests/subsys/nrfs/sysbuild.cmake
rename to tests/boards/nrf/nrfs/sysbuild.cmake
diff --git a/tests/boards/nrf/nrfs/testcase.yaml b/tests/boards/nrf/nrfs/testcase.yaml
new file mode 100644
index 00000000000..315c3cf7f37
--- /dev/null
+++ b/tests/boards/nrf/nrfs/testcase.yaml
@@ -0,0 +1,14 @@
+common:
+  platform_allow:
+    - nrf54h20dk/nrf54h20/cpuapp
+    - nrf54h20dk/nrf54h20/cpurad
+  integration_platforms:
+    - nrf54h20dk/nrf54h20/cpuapp
+    - nrf54h20dk/nrf54h20/cpurad
+  tags:
+    - nrfs
+  harness: ztest
+  sysbuild: true
+
+tests:
+  boards.nrf.nrfs.stress_test: {}
diff --git a/tests/boards/nrf/qdec/boards/bl54l15_dvk_nrf54l15_common.dtsi b/tests/boards/nrf/qdec/boards/bl54l15_dvk_nrf54l15_common.dtsi
new file mode 100644
index 00000000000..4db67a49a5e
--- /dev/null
+++ b/tests/boards/nrf/qdec/boards/bl54l15_dvk_nrf54l15_common.dtsi
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		qdec0 = &qdec20;
+		qenca = &phase_a;
+		qencb = &phase_b;
+	};
+
+	encoder-emulate {
+		compatible = "gpio-leds";
+
+		phase_a: phase_a {
+			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+		};
+
+		phase_b: phase_b {
+			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&pinctrl {
+	qdec_pinctrl: qdec_pinctrl {
+		group1 {
+			psels = <NRF_PSEL(QDEC_A, 1, 8)>,
+				<NRF_PSEL(QDEC_B, 1, 10)>;
+		};
+	};
+
+	qdec_sleep_pinctrl: qdec_sleep_pinctrl {
+		group1 {
+			psels = <NRF_PSEL(QDEC_A, 1, 8)>,
+				<NRF_PSEL(QDEC_B, 1, 10)>;
+			low-power-enable;
+		};
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&qdec20 {
+	status = "okay";
+	pinctrl-0 = <&qdec_pinctrl>;
+	pinctrl-1 = <&qdec_sleep_pinctrl>;
+	pinctrl-names = "default", "sleep";
+	steps = <127>;
+	led-pre = <500>;
+	zephyr,pm-device-runtime-auto;
+};
diff --git a/tests/boards/nrf/qdec/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/boards/nrf/qdec/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..f8840d890de
--- /dev/null
+++ b/tests/boards/nrf/qdec/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15_dvk_nrf54l15_common.dtsi"
+
+/* To prevent enabling console receiver. */
+&uart20 {
+	disable-rx;
+};
diff --git a/tests/boards/nrf/qdec/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay b/tests/boards/nrf/qdec/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..6c3ceb8b9a4
--- /dev/null
+++ b/tests/boards/nrf/qdec/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15_dvk_nrf54l15_common.dtsi"
+
+/* To prevent enabling console receiver. */
+&uart30 {
+	disable-rx;
+};
diff --git a/tests/boards/nrf/qdec/boards/bl54l15u_dvk_nrf54l15_common.dtsi b/tests/boards/nrf/qdec/boards/bl54l15u_dvk_nrf54l15_common.dtsi
new file mode 100644
index 00000000000..4db67a49a5e
--- /dev/null
+++ b/tests/boards/nrf/qdec/boards/bl54l15u_dvk_nrf54l15_common.dtsi
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		qdec0 = &qdec20;
+		qenca = &phase_a;
+		qencb = &phase_b;
+	};
+
+	encoder-emulate {
+		compatible = "gpio-leds";
+
+		phase_a: phase_a {
+			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+		};
+
+		phase_b: phase_b {
+			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&pinctrl {
+	qdec_pinctrl: qdec_pinctrl {
+		group1 {
+			psels = <NRF_PSEL(QDEC_A, 1, 8)>,
+				<NRF_PSEL(QDEC_B, 1, 10)>;
+		};
+	};
+
+	qdec_sleep_pinctrl: qdec_sleep_pinctrl {
+		group1 {
+			psels = <NRF_PSEL(QDEC_A, 1, 8)>,
+				<NRF_PSEL(QDEC_B, 1, 10)>;
+			low-power-enable;
+		};
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&qdec20 {
+	status = "okay";
+	pinctrl-0 = <&qdec_pinctrl>;
+	pinctrl-1 = <&qdec_sleep_pinctrl>;
+	pinctrl-names = "default", "sleep";
+	steps = <127>;
+	led-pre = <500>;
+	zephyr,pm-device-runtime-auto;
+};
diff --git a/tests/boards/nrf/qdec/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/boards/nrf/qdec/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..31710f2066a
--- /dev/null
+++ b/tests/boards/nrf/qdec/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15u_dvk_nrf54l15_common.dtsi"
+
+/* To prevent enabling console receiver. */
+&uart20 {
+	disable-rx;
+};
diff --git a/tests/boards/nrf/qdec/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay b/tests/boards/nrf/qdec/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..af1ca5b38cb
--- /dev/null
+++ b/tests/boards/nrf/qdec/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15u_dvk_nrf54l15_common.dtsi"
+
+/* To prevent enabling console receiver. */
+&uart30 {
+	disable-rx;
+};
diff --git a/tests/boards/nrf/qdec/boards/nrf54l20pdk_nrf54l20_common.dtsi b/tests/boards/nrf/qdec/boards/nrf54l20pdk_nrf54l20_common.dtsi
new file mode 100644
index 00000000000..f7810df33c0
--- /dev/null
+++ b/tests/boards/nrf/qdec/boards/nrf54l20pdk_nrf54l20_common.dtsi
@@ -0,0 +1,53 @@
+/*
+ * Copyright 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		qdec0 = &qdec20;
+		qenca = &phase_a;
+		qencb = &phase_b;
+	};
+
+	encoder-emulate {
+		compatible = "gpio-leds";
+		phase_a: phase_a {
+			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
+		};
+		phase_b: phase_b {
+			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+		};
+	};
+};
+
+&pinctrl {
+	qdec_pinctrl: qdec_pinctrl {
+		group1 {
+			psels = <NRF_PSEL(QDEC_A, 1, 8)>,
+				<NRF_PSEL(QDEC_B, 1, 10)>;
+		};
+	};
+
+	qdec_sleep_pinctrl: qdec_sleep_pinctrl {
+		group1 {
+			psels = <NRF_PSEL(QDEC_A, 1, 8)>,
+				<NRF_PSEL(QDEC_B, 1, 10)>;
+			low-power-enable;
+		};
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
+
+&qdec20 {
+	status = "okay";
+	pinctrl-0 = <&qdec_pinctrl>;
+	pinctrl-1 = <&qdec_sleep_pinctrl>;
+	pinctrl-names = "default", "sleep";
+	steps = <127>;
+	led-pre = <500>;
+	zephyr,pm-device-runtime-auto;
+};
diff --git a/tests/boards/nrf/qdec/boards/nrf54l20pdk_nrf54l20_cpuapp.overlay b/tests/boards/nrf/qdec/boards/nrf54l20pdk_nrf54l20_cpuapp.overlay
index 3fa426569b8..a16bac11f17 100644
--- a/tests/boards/nrf/qdec/boards/nrf54l20pdk_nrf54l20_cpuapp.overlay
+++ b/tests/boards/nrf/qdec/boards/nrf54l20pdk_nrf54l20_cpuapp.overlay
@@ -3,51 +3,4 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/ {
-	aliases {
-		qdec0 = &qdec20;
-		qenca = &phase_a;
-		qencb = &phase_b;
-	};
-
-	encoder-emulate {
-		compatible = "gpio-leds";
-		phase_a: phase_a {
-			gpios = <&gpio1 9 GPIO_ACTIVE_HIGH>;
-		};
-		phase_b: phase_b {
-			gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
-		};
-	};
-};
-
-&pinctrl {
-	qdec_pinctrl: qdec_pinctrl {
-		group1 {
-			psels = <NRF_PSEL(QDEC_A, 1, 8)>,
-				<NRF_PSEL(QDEC_B, 1, 10)>;
-		};
-	};
-
-	qdec_sleep_pinctrl: qdec_sleep_pinctrl {
-		group1 {
-			psels = <NRF_PSEL(QDEC_A, 1, 8)>,
-				<NRF_PSEL(QDEC_B, 1, 10)>;
-			low-power-enable;
-		};
-	};
-};
-
-&gpio1 {
-	status = "okay";
-};
-
-&qdec20 {
-	status = "okay";
-	pinctrl-0 = <&qdec_pinctrl>;
-	pinctrl-1 = <&qdec_sleep_pinctrl>;
-	pinctrl-names = "default", "sleep";
-	steps = <127>;
-	led-pre = <500>;
-	zephyr,pm-device-runtime-auto;
-};
+#include "nrf54l20pdk_nrf54l20_common.dtsi"
diff --git a/tests/boards/nrf/qdec/boards/nrf54l20pdk_nrf54l20_cpuflpr.overlay b/tests/boards/nrf/qdec/boards/nrf54l20pdk_nrf54l20_cpuflpr.overlay
new file mode 100644
index 00000000000..638d63e5c54
--- /dev/null
+++ b/tests/boards/nrf/qdec/boards/nrf54l20pdk_nrf54l20_cpuflpr.overlay
@@ -0,0 +1,6 @@
+/*
+ * Copyright 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "nrf54l20pdk_nrf54l20_common.dtsi"
diff --git a/tests/boards/nrf/qdec/testcase.yaml b/tests/boards/nrf/qdec/testcase.yaml
index 31f6260726f..1518a86660f 100644
--- a/tests/boards/nrf/qdec/testcase.yaml
+++ b/tests/boards/nrf/qdec/testcase.yaml
@@ -2,16 +2,17 @@ common:
   platform_allow:
     - nrf52840dk/nrf52840
     - nrf5340dk/nrf5340/cpuapp
+    - nrf54h20dk/nrf54h20/cpuapp
     - nrf54l15dk/nrf54l15/cpuapp
     - nrf54l15dk/nrf54l15/cpuflpr
     - nrf54l20pdk/nrf54l20/cpuapp
-    - nrf54h20dk/nrf54h20/cpuapp
+    - nrf54l20pdk/nrf54l20/cpuflpr
   integration_platforms:
     - nrf52840dk/nrf52840
     - nrf5340dk/nrf5340/cpuapp
+    - nrf54h20dk/nrf54h20/cpuapp
     - nrf54l15dk/nrf54l15/cpuapp
     - nrf54l15dk/nrf54l15/cpuflpr
-    - nrf54h20dk/nrf54h20/cpuapp
   harness: ztest
   harness_config:
     fixture: gpio_loopback
diff --git a/tests/boards/silabs/dma/block_append/CMakeLists.txt b/tests/boards/silabs/dma/block_append/CMakeLists.txt
new file mode 100644
index 00000000000..354f0cfea7f
--- /dev/null
+++ b/tests/boards/silabs/dma/block_append/CMakeLists.txt
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(block_append)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/boards/silabs/dma/block_append/Kconfig b/tests/boards/silabs/dma/block_append/Kconfig
new file mode 100644
index 00000000000..4386a78b295
--- /dev/null
+++ b/tests/boards/silabs/dma/block_append/Kconfig
@@ -0,0 +1,10 @@
+# Copyright (c) 2025 Silicon Laboratories Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+mainmenu "DMA block append Test"
+
+source "Kconfig.zephyr"
+
+config DMA_BA_XFER_SIZE
+	int "Number of bytes to transfer"
+	default 4096
diff --git a/tests/boards/silabs/dma/block_append/boards/slwrb4180a.overlay b/tests/boards/silabs/dma/block_append/boards/slwrb4180a.overlay
new file mode 100644
index 00000000000..a6fb1d7e094
--- /dev/null
+++ b/tests/boards/silabs/dma/block_append/boards/slwrb4180a.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		dma0 = &dma0;
+	};
+};
+
+&dma0 {
+	status = "okay";
+};
diff --git a/tests/boards/silabs/dma/block_append/boards/xg29_rb4412a.overlay b/tests/boards/silabs/dma/block_append/boards/xg29_rb4412a.overlay
new file mode 100644
index 00000000000..a6fb1d7e094
--- /dev/null
+++ b/tests/boards/silabs/dma/block_append/boards/xg29_rb4412a.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		dma0 = &dma0;
+	};
+};
+
+&dma0 {
+	status = "okay";
+};
diff --git a/tests/boards/silabs/dma/block_append/prj.conf b/tests/boards/silabs/dma/block_append/prj.conf
new file mode 100644
index 00000000000..40e96629277
--- /dev/null
+++ b/tests/boards/silabs/dma/block_append/prj.conf
@@ -0,0 +1,4 @@
+CONFIG_ZTEST=y
+CONFIG_DMA=y
+CONFIG_LOG=y
+CONFIG_DMA_LOG_LEVEL_INF=y
diff --git a/tests/boards/silabs/dma/block_append/src/main.c b/tests/boards/silabs/dma/block_append/src/main.c
new file mode 100644
index 00000000000..458dca0dc8e
--- /dev/null
+++ b/tests/boards/silabs/dma/block_append/src/main.c
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(dma_m2m_ba, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/boards/silabs/dma/block_append/src/test_dma_ba.c b/tests/boards/silabs/dma/block_append/src/test_dma_ba.c
new file mode 100644
index 00000000000..3c3acb39b8b
--- /dev/null
+++ b/tests/boards/silabs/dma/block_append/src/test_dma_ba.c
@@ -0,0 +1,464 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Verify zephyr dma memory to memory transfer with block append during a transfer
+ * @details
+ * - 4 tests:
+ *   -# restart_transfer test: Check that the function silabs ldma append block function restart
+ *      the transfer if we append a block after the transfer is done.
+ *   -# restart_in_isr test: Check that is a transfer is done during the append, the next dma isr
+ *      will restart the transfer with the right append block.
+ *   -# stress_in_isr test: Check that we can append the next block immediately after a
+ *      DMA_STATUS_BLOCK callback.
+ *   -# loopstress test: Check that we can continuously append block and check that the function
+ *      return an error if we append a transfer that already has an append block
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/dma.h>
+#include <zephyr/drivers/dma/dma_silabs_ldma.h>
+#include <zephyr/ztest.h>
+
+#define BLOCK_SIZE 4
+
+/* this src memory shall be in RAM to support using as a DMA source pointer.*/
+static __aligned(32) uint8_t tx_data[CONFIG_DMA_BA_XFER_SIZE];
+static __aligned(32) uint8_t rx_data[CONFIG_DMA_BA_XFER_SIZE];
+
+K_SEM_DEFINE(xfer_sem, 0, 1);
+
+static struct dma_config dma_cfg = {0};
+static struct dma_block_config dma_block_cfg;
+static uint32_t rx_idx;
+static uint32_t tx_idx;
+
+static void dma_ba_callback_restart(const struct device *dma_dev, void *user_data, uint32_t channel,
+				    int status)
+{
+	if (status < 0) {
+		TC_PRINT("callback status %d\n", status);
+	} else {
+		TC_PRINT("giving xfer_sem\n");
+		k_sem_give(&xfer_sem);
+	}
+}
+
+static int test_ba_restart_transfer(void)
+{
+	const struct device *dma;
+	static int chan_id;
+
+	TC_PRINT("Preparing DMA Controller\n");
+
+	memset(tx_data, 0, sizeof(tx_data));
+
+	for (int i = 0; i < CONFIG_DMA_BA_XFER_SIZE; i++) {
+		tx_data[i] = i;
+	}
+
+	memset(rx_data, 0, sizeof(rx_data));
+
+	dma = DEVICE_DT_GET(DT_ALIAS(dma0));
+	if (!device_is_ready(dma)) {
+		TC_PRINT("dma controller device is not ready\n");
+		return TC_FAIL;
+	}
+
+	dma_cfg.channel_direction = MEMORY_TO_MEMORY;
+	dma_cfg.source_data_size = 1U;
+	dma_cfg.dest_data_size = 1U;
+	dma_cfg.source_burst_length = 1U;
+	dma_cfg.dest_burst_length = 1U;
+	dma_cfg.user_data = NULL;
+	dma_cfg.dma_callback = dma_ba_callback_restart;
+	dma_cfg.head_block = &dma_block_cfg;
+	dma_cfg.complete_callback_en = true; /* per block completion */
+
+	chan_id = dma_request_channel(dma, NULL);
+	if (chan_id < 0) {
+		return TC_FAIL;
+	}
+
+	memset(&dma_block_cfg, 0, sizeof(dma_block_cfg));
+	dma_block_cfg.block_size = CONFIG_DMA_BA_XFER_SIZE / 2;
+	dma_block_cfg.source_address = (uint32_t)(tx_data);
+	dma_block_cfg.dest_address = (uint32_t)(rx_data);
+	TC_PRINT("block_size %d, source addr %x, dest addr %x\n", CONFIG_DMA_BA_XFER_SIZE,
+		 dma_block_cfg.source_address, dma_block_cfg.dest_address);
+
+	if (dma_config(dma, chan_id, &dma_cfg)) {
+		TC_PRINT("ERROR: transfer config (%d)\n", chan_id);
+		return TC_FAIL;
+	}
+
+	TC_PRINT("Starting the transfer on channel %d\n", chan_id);
+
+	if (dma_start(dma, chan_id)) {
+		TC_PRINT("ERROR: transfer start (%d)\n", chan_id);
+		return TC_FAIL;
+	}
+
+	/* Be sure that the DMA transfer is done */
+	k_busy_wait(1000 * 100); /* busy wait for 100 ms*/
+
+	/* Append a next block on the channel that is already done*/
+	dma_block_cfg.source_address = (uint32_t)(tx_data) + CONFIG_DMA_BA_XFER_SIZE / 2;
+	dma_block_cfg.dest_address = (uint32_t)(rx_data) + CONFIG_DMA_BA_XFER_SIZE / 2;
+
+	dma_cfg.head_block = &dma_block_cfg;
+	silabs_ldma_append_block(dma, chan_id, &dma_cfg);
+
+	if (k_sem_take(&xfer_sem, K_MSEC(1000)) != 0) {
+		TC_PRINT("Timed out waiting for xfers\n");
+		return TC_FAIL;
+	}
+
+	TC_PRINT("Verify RX buffer should contain the full TX buffer string.\n");
+
+	if (memcmp(tx_data, rx_data, CONFIG_DMA_BA_XFER_SIZE)) {
+		return TC_FAIL;
+	}
+
+	TC_PRINT("Finished: DMA block append restart transfer\n");
+	return TC_PASS;
+}
+
+static int test_ba_restart_in_isr(void)
+{
+	const struct device *dma;
+	static int chan_id;
+	unsigned int key;
+
+	TC_PRINT("Preparing DMA Controller\n");
+
+	memset(tx_data, 0, sizeof(tx_data));
+
+	for (int i = 0; i < CONFIG_DMA_BA_XFER_SIZE; i++) {
+		tx_data[i] = i;
+	}
+
+	memset(rx_data, 0, sizeof(rx_data));
+
+	dma = DEVICE_DT_GET(DT_ALIAS(dma0));
+	if (!device_is_ready(dma)) {
+		TC_PRINT("dma controller device is not ready\n");
+		return TC_FAIL;
+	}
+
+	dma_cfg.channel_direction = MEMORY_TO_MEMORY;
+	dma_cfg.source_data_size = 1U;
+	dma_cfg.dest_data_size = 1U;
+	dma_cfg.source_burst_length = 1U;
+	dma_cfg.dest_burst_length = 1U;
+	dma_cfg.user_data = NULL;
+	dma_cfg.dma_callback = dma_ba_callback_restart;
+	dma_cfg.head_block = &dma_block_cfg;
+	dma_cfg.complete_callback_en = true; /* per block completion */
+
+	chan_id = dma_request_channel(dma, NULL);
+	if (chan_id < 0) {
+		return TC_FAIL;
+	}
+
+	memset(&dma_block_cfg, 0, sizeof(dma_block_cfg));
+	dma_block_cfg.block_size = CONFIG_DMA_BA_XFER_SIZE / 2;
+	dma_block_cfg.source_address = (uint32_t)(tx_data);
+	dma_block_cfg.dest_address = (uint32_t)(rx_data);
+	TC_PRINT("block_size %d, source addr %x, dest addr %x\n", CONFIG_DMA_BA_XFER_SIZE,
+		 dma_block_cfg.source_address, dma_block_cfg.dest_address);
+
+	if (dma_config(dma, chan_id, &dma_cfg)) {
+		TC_PRINT("ERROR: transfer config (%d)\n", chan_id);
+		return TC_FAIL;
+	}
+
+	TC_PRINT("Starting the transfer on channel %d and waiting completion\n", chan_id);
+
+	/* Lock IRQ in order to not triger the DMA isr */
+	key = irq_lock();
+	if (dma_start(dma, chan_id)) {
+		TC_PRINT("ERROR: transfer start (%d)\n", chan_id);
+		return TC_FAIL;
+	}
+
+	/* Be sure that the DMA transfer is done */
+	k_busy_wait(1000 * 100); /* busy wait for 100 ms*/
+
+	/* Remove the done flag of the dma channel to simulate an append while a transfer is
+	 * ongoing
+	 */
+	sys_clear_bit((mem_addr_t)&LDMA->CHDONE, chan_id);
+
+	/* Append a next block on the channel that is already done*/
+	dma_block_cfg.source_address = (uint32_t)(tx_data) + CONFIG_DMA_BA_XFER_SIZE / 2;
+	dma_block_cfg.dest_address = (uint32_t)(rx_data) + CONFIG_DMA_BA_XFER_SIZE / 2;
+
+	dma_cfg.head_block = &dma_block_cfg;
+	silabs_ldma_append_block(dma, chan_id, &dma_cfg);
+
+	/* Set the chdone bit to simulate that the DMA transfer was finished while appending a
+	 * block
+	 */
+	sys_set_bit((mem_addr_t)&LDMA->CHDONE, chan_id);
+
+	/* Check if the isr in dma driver will correctly restart the DMA engine with the new block
+	 * that was append
+	 */
+	irq_unlock(key);
+
+	if (k_sem_take(&xfer_sem, K_MSEC(1000)) != 0) {
+		TC_PRINT("Timed out waiting for xfers\n");
+		return TC_FAIL;
+	}
+
+	TC_PRINT("Verify RX buffer should contain the full TX buffer string.\n");
+
+	if (memcmp(tx_data, rx_data, CONFIG_DMA_BA_XFER_SIZE)) {
+		return TC_FAIL;
+	}
+
+	TC_PRINT("Finished: DMA block append restart in isr\n");
+	return TC_PASS;
+}
+
+static void dma_ba_callback_stress_in_isr(const struct device *dma_dev, void *user_data,
+					  uint32_t channel, int status)
+{
+	struct dma_config *dma_cfg = (struct dma_config *)user_data;
+
+	if (status < 0) {
+		TC_PRINT("callback status %d\n", status);
+	} else {
+		if (rx_idx <= CONFIG_DMA_BA_XFER_SIZE - BLOCK_SIZE) {
+			dma_block_cfg.source_address = (uint32_t)(tx_data + tx_idx);
+			dma_block_cfg.dest_address = (uint32_t)(rx_data + rx_idx);
+			rx_idx += BLOCK_SIZE;
+			tx_idx += BLOCK_SIZE;
+			if (silabs_ldma_append_block(dma_dev, channel, dma_cfg)) {
+				TC_PRINT("append block failed\n");
+			}
+		} else {
+			TC_PRINT("giving xfer_sem\n");
+			k_sem_give(&xfer_sem);
+		}
+	}
+}
+
+static int test_ba_stress_in_isr(void)
+{
+	const struct device *dma;
+	static int chan_id;
+	unsigned int key;
+
+	TC_PRINT("Preparing DMA Controller\n");
+
+	memset(tx_data, 0, sizeof(tx_data));
+
+	rx_idx = 0;
+	tx_idx = 0;
+
+	for (int i = 0; i < CONFIG_DMA_BA_XFER_SIZE; i++) {
+		tx_data[i] = i;
+	}
+
+	memset(rx_data, 0, sizeof(rx_data));
+
+	dma = DEVICE_DT_GET(DT_ALIAS(dma0));
+	if (!device_is_ready(dma)) {
+		return TC_FAIL;
+	}
+
+	dma_cfg.channel_direction = MEMORY_TO_MEMORY;
+	dma_cfg.source_data_size = 1U;
+	dma_cfg.dest_data_size = 1U;
+	dma_cfg.source_burst_length = 1U;
+	dma_cfg.dest_burst_length = 1U;
+	dma_cfg.user_data = &dma_cfg;
+	dma_cfg.dma_callback = dma_ba_callback_stress_in_isr;
+	dma_cfg.head_block = &dma_block_cfg;
+	dma_cfg.complete_callback_en = true; /* per block completion */
+
+	chan_id = dma_request_channel(dma, NULL);
+	if (chan_id < 0) {
+		return TC_FAIL;
+	}
+
+	memset(&dma_block_cfg, 0, sizeof(dma_block_cfg));
+
+	/* Configure the first transfer block*/
+	dma_block_cfg.block_size = BLOCK_SIZE;
+	dma_block_cfg.source_address = (uint32_t)(tx_data + tx_idx);
+	dma_block_cfg.dest_address = (uint32_t)(rx_data + rx_idx);
+	rx_idx += BLOCK_SIZE;
+	tx_idx += BLOCK_SIZE;
+
+	TC_PRINT("dma block %d block_size %d, source addr %x, dest addr %x\n", 0, BLOCK_SIZE,
+		 dma_block_cfg.source_address, dma_block_cfg.dest_address);
+
+	if (dma_config(dma, chan_id, &dma_cfg)) {
+		TC_PRINT("ERROR: transfer config (%d)\n", chan_id);
+		return TC_FAIL;
+	}
+
+	TC_PRINT("Starting the transfer on channel %d and waiting completion\n", chan_id);
+
+	/* Lock IRQ in order to not triger the DMA isr */
+	key = irq_lock();
+	if (dma_start(dma, chan_id)) {
+		TC_PRINT("ERROR: transfer start (%d)\n", chan_id);
+		return TC_FAIL;
+	}
+
+	/* Append a new block on the channel */
+	dma_block_cfg.source_address = (uint32_t)(tx_data + tx_idx);
+	dma_block_cfg.dest_address = (uint32_t)(rx_data + rx_idx);
+	rx_idx += BLOCK_SIZE;
+	tx_idx += BLOCK_SIZE;
+	silabs_ldma_append_block(dma, chan_id, &dma_cfg);
+
+	irq_unlock(key);
+
+	/* All the next blocks will be append in the isr */
+
+	if (k_sem_take(&xfer_sem, K_MSEC(1000)) != 0) {
+		TC_PRINT("Timed out waiting for xfers\n");
+		return TC_FAIL;
+	}
+
+	TC_PRINT("Verify RX buffer should contain the full TX buffer string.\n");
+
+	if (memcmp(tx_data, rx_data, CONFIG_DMA_BA_XFER_SIZE)) {
+		return TC_FAIL;
+	}
+
+	TC_PRINT("Finished: DMA block append stress in isr\n");
+	return TC_PASS;
+}
+
+static void dma_ba_callback_loopstress(const struct device *dma_dev, void *user_data,
+				       uint32_t channel, int status)
+{
+	if (status < 0) {
+		TC_PRINT("callback status %d\n", status);
+	} else {
+		if (rx_idx == CONFIG_DMA_BA_XFER_SIZE) {
+			TC_PRINT("giving xfer_sem\n");
+			k_sem_give(&xfer_sem);
+		}
+	}
+}
+
+static int test_ba_loopstress(void)
+{
+	const struct device *dma;
+	static int chan_id;
+
+	TC_PRINT("Preparing DMA Controller\n");
+
+	memset(tx_data, 0, sizeof(tx_data));
+
+	rx_idx = 0;
+	tx_idx = 0;
+
+	for (int i = 0; i < CONFIG_DMA_BA_XFER_SIZE; i++) {
+		tx_data[i] = i;
+	}
+
+	memset(rx_data, 0, sizeof(rx_data));
+
+	dma = DEVICE_DT_GET(DT_ALIAS(dma0));
+	if (!device_is_ready(dma)) {
+		TC_PRINT("dma controller device is not ready\n");
+		return TC_FAIL;
+	}
+
+	dma_cfg.channel_direction = MEMORY_TO_MEMORY;
+	dma_cfg.source_data_size = 1U;
+	dma_cfg.dest_data_size = 1U;
+	dma_cfg.source_burst_length = 1U;
+	dma_cfg.dest_burst_length = 1U;
+	dma_cfg.user_data = &dma_cfg;
+	dma_cfg.dma_callback = dma_ba_callback_loopstress;
+	dma_cfg.head_block = &dma_block_cfg;
+	dma_cfg.complete_callback_en = true; /* per block completion */
+
+	chan_id = dma_request_channel(dma, NULL);
+	if (chan_id < 0) {
+		return TC_FAIL;
+	}
+
+	memset(&dma_block_cfg, 0, sizeof(dma_block_cfg));
+
+	/* Setting the first DMA transfer block */
+	dma_block_cfg.block_size = BLOCK_SIZE;
+	dma_block_cfg.source_address = (uint32_t)(tx_data + tx_idx);
+	dma_block_cfg.dest_address = (uint32_t)(rx_data + rx_idx);
+	rx_idx += BLOCK_SIZE;
+	tx_idx += BLOCK_SIZE;
+
+	TC_PRINT("dma block %d block_size %d, source addr %x, dest addr %x\n", 0, BLOCK_SIZE,
+		 dma_block_cfg.source_address, dma_block_cfg.dest_address);
+
+	if (dma_config(dma, chan_id, &dma_cfg)) {
+		TC_PRINT("ERROR: transfer config (%d)\n", chan_id);
+		return TC_FAIL;
+	}
+
+	TC_PRINT("Starting the transfer on channel %d and waiting completion\n", chan_id);
+
+	if (dma_start(dma, chan_id)) {
+		TC_PRINT("ERROR: transfer start (%d)\n", chan_id);
+		return TC_FAIL;
+	}
+
+	/* Append new blocks on the channel */
+	while (rx_idx <= CONFIG_DMA_BA_XFER_SIZE - BLOCK_SIZE) {
+		dma_block_cfg.source_address = (uint32_t)(tx_data + tx_idx);
+		dma_block_cfg.dest_address = (uint32_t)(rx_data + rx_idx);
+
+		if (!silabs_ldma_append_block(dma, chan_id, &dma_cfg)) {
+			rx_idx += BLOCK_SIZE;
+			tx_idx += BLOCK_SIZE;
+		}
+	}
+
+	if (k_sem_take(&xfer_sem, K_MSEC(1000)) != 0) {
+		TC_PRINT("Timed out waiting for xfers\n");
+		return TC_FAIL;
+	}
+
+	TC_PRINT("Verify RX buffer should contain the full TX buffer string.\n");
+
+	if (memcmp(tx_data, rx_data, CONFIG_DMA_BA_XFER_SIZE)) {
+		return TC_FAIL;
+	}
+
+	TC_PRINT("Finished: DMA block append loopstress\n");
+	return TC_PASS;
+}
+
+/* export test cases */
+ZTEST(dma_m2m_ba, test_dma_m2m_ba_restart_transfer)
+{
+	zassert_true((test_ba_restart_transfer() == TC_PASS));
+}
+
+ZTEST(dma_m2m_ba, test_dma_m2m_ba_restart_in_isr)
+{
+	zassert_true((test_ba_restart_in_isr() == TC_PASS));
+}
+
+ZTEST(dma_m2m_ba, test_dma_m2m_stress_in_isr)
+{
+	zassert_true((test_ba_stress_in_isr() == TC_PASS));
+}
+
+ZTEST(dma_m2m_ba, test_dma_m2m_loopstress)
+{
+	zassert_true((test_ba_loopstress() == TC_PASS));
+}
diff --git a/tests/boards/silabs/dma/block_append/testcase.yaml b/tests/boards/silabs/dma/block_append/testcase.yaml
new file mode 100644
index 00000000000..fef775b94fa
--- /dev/null
+++ b/tests/boards/silabs/dma/block_append/testcase.yaml
@@ -0,0 +1,10 @@
+tests:
+  boards.silabs.dma.block_append:
+    depends_on: dma
+    tags:
+      - drivers
+      - dma
+    platform_allow:
+      - slwrb4180a
+      - xg29_rb4412a
+    filter: dt_alias_exists("dma0")
diff --git a/tests/boards/vmu_rt1170/icm42688/CMakeLists.txt b/tests/boards/vmu_rt1170/icm42688/CMakeLists.txt
new file mode 100644
index 00000000000..1b1745125af
--- /dev/null
+++ b/tests/boards/vmu_rt1170/icm42688/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright 2025 CogniPilot Foundation
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(device)
+
+target_sources(app PRIVATE src/main.c)
diff --git a/tests/boards/vmu_rt1170/icm42688/boards/vmu_rt1170_mimxrt1176_cm7.overlay b/tests/boards/vmu_rt1170/icm42688/boards/vmu_rt1170_mimxrt1176_cm7.overlay
new file mode 100644
index 00000000000..68ab81b2a08
--- /dev/null
+++ b/tests/boards/vmu_rt1170/icm42688/boards/vmu_rt1170_mimxrt1176_cm7.overlay
@@ -0,0 +1,8 @@
+/* Copyright 2025 CogniPilot Foundation */
+/* SPDX-License-Identifier: Apache-2.0 */
+
+&lpspi1 {
+	/delete-node/ icm42688p0@0;
+	/delete-property/ dmas;
+	/delete-property/ dma-names;
+};
diff --git a/tests/boards/vmu_rt1170/icm42688/prj.conf b/tests/boards/vmu_rt1170/icm42688/prj.conf
new file mode 100644
index 00000000000..7c74e12daa4
--- /dev/null
+++ b/tests/boards/vmu_rt1170/icm42688/prj.conf
@@ -0,0 +1,16 @@
+# Copyright 2025 CogniPilot Foundation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ZTEST=y
+CONFIG_GPIO=y
+CONFIG_DEBUG=y
+CONFIG_SPEED_OPTIMIZATIONS=n
+CONFIG_SIZE_OPTIMIZATIONS=n
+CONFIG_SENSOR=y
+CONFIG_SENSOR_SHELL_STREAM=y
+CONFIG_SENSOR_LOG_LEVEL_DBG=n
+CONFIG_RTIO_SUBMIT_SEM=y
+CONFIG_SPI_RTIO=y
+CONFIG_SPI_ASYNC=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=10000
+CONFIG_CBPRINTF_FP_SUPPORT=y
diff --git a/tests/boards/vmu_rt1170/icm42688/src/main.c b/tests/boards/vmu_rt1170/icm42688/src/main.c
new file mode 100644
index 00000000000..d936df5a8e5
--- /dev/null
+++ b/tests/boards/vmu_rt1170/icm42688/src/main.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright 2025 CogniPilot Foundation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <math.h>
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/rtio/rtio.h>
+#include <zephyr/drivers/sensor.h>
+#include <zephyr/logging/log.h>
+
+#define BATCH_DURATION 50
+
+double q31_to_double(int32_t q31_value, int8_t shift)
+{
+	return ((double)q31_value) / (double)(1 << (31 - shift));
+}
+
+static struct rtio_sqe *streaming_handle;
+
+static struct sensor_stream_trigger stream_trigger = {
+	.opt = SENSOR_STREAM_DATA_INCLUDE,
+	.trigger = SENSOR_TRIG_FIFO_WATERMARK,
+};
+
+static struct sensor_read_config stream_config = {
+	.sensor = DEVICE_DT_GET(DT_NODELABEL(icm42688_1)),
+	.is_streaming = true,
+	.triggers = &stream_trigger,
+	.count = 0,
+	.max = 1,
+};
+
+static RTIO_IODEV_DEFINE(iodev_stream, &__sensor_iodev_api, &stream_config);
+RTIO_DEFINE_WITH_MEMPOOL(rtio, 4, 4, 32, 64, 4);
+
+static void callback(int result, uint8_t *buf, uint32_t buf_len, void *userdata)
+{
+	static uint8_t decoded_buffer[127];
+
+	zassert_not_null(stream_config.sensor->api);
+	const struct sensor_decoder_api *decoder;
+
+	zassert_ok(sensor_get_decoder(stream_config.sensor, &decoder));
+	int channels[] = {
+		SENSOR_CHAN_GYRO_XYZ,
+		SENSOR_CHAN_ACCEL_XYZ,
+	};
+
+	for (int i = 0; i < ARRAY_SIZE(channels); i++) {
+		int chan = channels[i];
+		struct sensor_chan_spec ch = {
+			.chan_idx = 0,
+			.chan_type = chan,
+		};
+
+		uint32_t fit = 0;
+		int count = 0;
+
+		while (decoder->decode(buf, ch, &fit, 1, decoded_buffer) > 0) {
+			zassert(count++ < 127, "fifo overflow");
+			if (ch.chan_type == SENSOR_CHAN_ACCEL_XYZ) {
+				struct sensor_three_axis_data *data =
+					(struct sensor_three_axis_data *)decoded_buffer;
+				double x = q31_to_double(data->readings[0].values[0], data->shift);
+				double y = q31_to_double(data->readings[0].values[1], data->shift);
+				double z = q31_to_double(data->readings[0].values[2], data->shift);
+
+				zassert(fabs(x) < 1.0, "fail", "accel x out of range: %10.4f", x);
+				zassert(fabs(y) < 1.0, "fail", "accel y out of range: %10.4f", y);
+				zassert(fabs(z - 9.8) < 1.0, "fail",
+					"accel z out of range: %10.4f", z);
+			} else if (ch.chan_type == SENSOR_CHAN_GYRO_XYZ) {
+				struct sensor_three_axis_data *data =
+					(struct sensor_three_axis_data *)decoded_buffer;
+				double x = q31_to_double(data->readings[0].values[0], data->shift);
+				double y = q31_to_double(data->readings[0].values[1], data->shift);
+				double z = q31_to_double(data->readings[0].values[2], data->shift);
+
+				zassert(fabs(x) < 0.1, "fail", "gyro x out of range: %10.4f", x);
+				zassert(fabs(y) < 0.1, "fail", "gyro y out of range: %10.4f", y);
+				zassert(fabs(z) < 0.1, "fail", "gyro z out of range: %10.4f", z);
+			}
+		}
+	}
+}
+
+ZTEST(icm42688_stream, test_icm42688_stream)
+{
+	stream_config.count = 1;
+	struct sensor_value val_in = { BATCH_DURATION, 0 };
+
+	zassert_ok(sensor_attr_set(
+		stream_config.sensor,
+		SENSOR_CHAN_ALL,
+		SENSOR_ATTR_BATCH_DURATION, &val_in));
+	struct sensor_value val_out;
+
+	zassert_ok(sensor_attr_get(
+		stream_config.sensor,
+		SENSOR_CHAN_ALL,
+		SENSOR_ATTR_BATCH_DURATION, &val_out));
+	zassert_equal(val_in.val1, val_out.val1);
+	zassert_ok(sensor_stream(&iodev_stream, &rtio, NULL,
+		&streaming_handle));
+	sensor_processing_with_callback(&rtio, callback);
+	zassert_ok(rtio_sqe_cancel(streaming_handle));
+}
+
+static void *icm42688_stream_setup(void)
+{
+	return NULL;
+}
+
+
+ZTEST_SUITE(icm42688_stream, NULL, icm42688_stream_setup, NULL, NULL, NULL);
diff --git a/tests/boards/vmu_rt1170/icm42688/testcase.yaml b/tests/boards/vmu_rt1170/icm42688/testcase.yaml
new file mode 100644
index 00000000000..b999ebde8e6
--- /dev/null
+++ b/tests/boards/vmu_rt1170/icm42688/testcase.yaml
@@ -0,0 +1,11 @@
+# Copyright 2025 CogniPilot Foundation
+# SPDX-License-Identifier: Apache-2.0
+
+tests:
+  boards.vmu_rt1170.icm42688:
+    tags:
+      - drivers
+      - sensor
+      - subsys
+    platform_allow:
+      - vmu_rt1170/mimxrt1176/cm7
diff --git a/tests/boot/mcuboot_data_sharing/boards/nrf52840dk_nrf52840.overlay b/tests/boot/mcuboot_data_sharing/boards/nrf52840dk_nrf52840.overlay
index fe47e1cd405..dec5e057941 100644
--- a/tests/boot/mcuboot_data_sharing/boards/nrf52840dk_nrf52840.overlay
+++ b/tests/boot/mcuboot_data_sharing/boards/nrf52840dk_nrf52840.overlay
@@ -1,6 +1,10 @@
 /* SPDX-License-Identifier: Apache-2.0 */
 
 / {
+	chosen {
+		/delete-property/ zephyr,boot-mode;
+	};
+
 	sram@2003FC00 {
 		compatible = "zephyr,memory-region", "mmio-sram";
 		reg = <0x2003FC00 DT_SIZE_K(1)>;
diff --git a/tests/boot/mcuboot_recovery_retention/boards/nrf52840dk_nrf52840.overlay b/tests/boot/mcuboot_recovery_retention/boards/nrf52840dk_nrf52840.overlay
index bd69d21527d..425ac4ec071 100644
--- a/tests/boot/mcuboot_recovery_retention/boards/nrf52840dk_nrf52840.overlay
+++ b/tests/boot/mcuboot_recovery_retention/boards/nrf52840dk_nrf52840.overlay
@@ -2,21 +2,10 @@
 
 / {
 	chosen {
-		zephyr,boot-mode = &boot_mode0;
 		zephyr,uart-mcumgr = &cdc_acm_uart;
 	};
 };
 
-&gpregret1 {
-	status = "okay";
-
-	boot_mode0: boot_mode@0 {
-		compatible = "zephyr,retention";
-		status = "okay";
-		reg = <0x0 0x1>;
-	};
-};
-
 &zephyr_udc0 {
 	status = "okay";
 
diff --git a/tests/boot/mcuboot_recovery_retention/sysbuild.cmake b/tests/boot/mcuboot_recovery_retention/sysbuild.cmake
index 6000a6416e7..6207fe8e58c 100644
--- a/tests/boot/mcuboot_recovery_retention/sysbuild.cmake
+++ b/tests/boot/mcuboot_recovery_retention/sysbuild.cmake
@@ -1,9 +1,9 @@
 set(mcuboot_EXTRA_ZEPHYR_MODULES "${CMAKE_CURRENT_LIST_DIR}/test_module" CACHE INTERNAL "test_module directory")
 
-if(DEFINED mcuboot_TARGET_OVERLAY_CONFIG)
-  list(APPEND mcuboot_OVERLAY_CONFIG "${CMAKE_CURRENT_LIST_DIR}/sysbuild/mcuboot/${mcuboot_TARGET_OVERLAY_CONFIG}")
-  list(REMOVE_DUPLICATES mcuboot_OVERLAY_CONFIG)
-  set(mcuboot_OVERLAY_CONFIG "${mcuboot_OVERLAY_CONFIG}" CACHE INTERNAL "")
+if(DEFINED mcuboot_TARGET_EXTRA_CONF_FILE)
+  list(APPEND mcuboot_EXTRA_CONF_FILE "${CMAKE_CURRENT_LIST_DIR}/sysbuild/mcuboot/${mcuboot_TARGET_EXTRA_CONF_FILE}")
+  list(REMOVE_DUPLICATES mcuboot_EXTRA_CONF_FILE)
+  set(mcuboot_EXTRA_CONF_FILE "${mcuboot_EXTRA_CONF_FILE}" CACHE INTERNAL "")
 endif()
 
 if(DEFINED mcuboot_TARGET_DTC_OVERLAY_FILE)
diff --git a/tests/boot/mcuboot_recovery_retention/testcase.yaml b/tests/boot/mcuboot_recovery_retention/testcase.yaml
index 0bb7e62e706..9a68b6a7082 100644
--- a/tests/boot/mcuboot_recovery_retention/testcase.yaml
+++ b/tests/boot/mcuboot_recovery_retention/testcase.yaml
@@ -30,7 +30,7 @@ tests:
     extra_args:
       - EXTRA_CONF_FILE="boards/nrf52840dk_nrf52840_mem.conf"
       - DTC_OVERLAY_FILE="boards/nrf52840dk_nrf52840_mem.overlay"
-      - mcuboot_TARGET_OVERLAY_CONFIG="boards/nrf52840dk_nrf52840_mem.conf"
+      - mcuboot_TARGET_EXTRA_CONF_FILE="boards/nrf52840dk_nrf52840_mem.conf"
       - mcuboot_TARGET_DTC_OVERLAY_FILE="boards/nrf52840dk_nrf52840_mem.overlay"
     tags:
       - mcuboot
diff --git a/tests/boot/test_mcuboot/swapped_app/Kconfig b/tests/boot/test_mcuboot/swapped_app/Kconfig
index 9f603e6ce32..fd33c400fb0 100644
--- a/tests/boot/test_mcuboot/swapped_app/Kconfig
+++ b/tests/boot/test_mcuboot/swapped_app/Kconfig
@@ -1,9 +1,13 @@
 # Copyright 2022 NXP
+# Copyright 2025 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 source "Kconfig.zephyr"
 # Workaround for not being able to have commas in macro arguments
 DT_CHOSEN_Z_CODE_PARTITION := zephyr,code-partition
 
 config BUILD_OUTPUT_ADJUST_LMA
+	default "$(dt_node_reg_addr_hex,$(dt_nodelabel_path,slot1_partition))-\
+		$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION))+\
+		$(dt_node_int_prop_hex,$(dt_node_parent,$(dt_node_parent,$(dt_nodelabel_path,slot1_partition))),erase-block-size)" if MCUBOOT_BOOTLOADER_MODE_SWAP_USING_OFFSET
 	default "$(dt_node_reg_addr_hex,$(dt_nodelabel_path,slot1_partition))-\
 		$(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_PARTITION))"
diff --git a/tests/boot/test_mcuboot/testcase.yaml b/tests/boot/test_mcuboot/testcase.yaml
index 27e71f310b3..9500c132875 100644
--- a/tests/boot/test_mcuboot/testcase.yaml
+++ b/tests/boot/test_mcuboot/testcase.yaml
@@ -1,5 +1,6 @@
 common:
   sysbuild: true
+  tags: mcuboot
   harness: console
   harness_config:
     type: multi_line
@@ -11,7 +12,6 @@ common:
       - "Swapped application booted on (.*)"
 tests:
   bootloader.mcuboot:
-    tags: mcuboot
     platform_allow:
       - frdm_k22f
       - frdm_k64f
@@ -21,6 +21,7 @@ tests:
       - rddrone_fmuk66
       - twr_ke18f
       - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
       - lpcxpresso55s06
       - lpcxpresso55s16
       - lpcxpresso55s28
@@ -48,8 +49,17 @@ tests:
       - frdm_k64f
       - nrf52840dk/nrf52840
   bootloader.mcuboot.assert:
-    tags: mcuboot
     platform_allow:
       - b_u585i_iot02a
     extra_configs:
       - CONFIG_ASSERT=y
+  bootloader.mcuboot.swap_using_offset:
+    platform_allow:
+      - frdm_k64f
+      - nrf5340dk/nrf5340/cpuapp
+    integration_platforms:
+      - frdm_k64f
+      - nrf5340dk/nrf5340/cpuapp
+    extra_args:
+      - SB_CONFIG_MCUBOOT_MODE_SWAP_USING_OFFSET=y
+      - swapped_app_CONFIG_MCUBOOT_BOOTLOADER_MODE_SWAP_USING_OFFSET=y
diff --git a/tests/boot/with_mcumgr/pytest/test_upgrade.py b/tests/boot/with_mcumgr/pytest/test_upgrade.py
index f7d74d62dba..733bd40f478 100755
--- a/tests/boot/with_mcumgr/pytest/test_upgrade.py
+++ b/tests/boot/with_mcumgr/pytest/test_upgrade.py
@@ -32,6 +32,13 @@ def create_signed_image(build_dir: Path, app_build_dir: Path, version: str) -> P
     return image_to_test
 
 
+def get_upgrade_string_to_verify(build_dir: Path) -> str:
+    sysbuild_config = Path(build_dir) / 'zephyr' / '.config'
+    if find_in_config(sysbuild_config, 'SB_CONFIG_MCUBOOT_MODE_SWAP_USING_OFFSET'):
+        return 'Starting swap using offset algorithm'
+    return 'Starting swap using move algorithm'
+
+
 def clear_buffer(dut: DeviceAdapter) -> None:
     disconnect = False
     if not dut.is_device_connected():
@@ -71,9 +78,10 @@ def test_upgrade_with_confirm(dut: DeviceAdapter, shell: Shell, mcumgr: MCUmgr):
 
     dut.connect()
     output = dut.readlines_until('Launching primary slot application')
+    upgrade_string_to_verify = get_upgrade_string_to_verify(dut.device_config.build_dir)
     match_lines(output, [
         'Swap type: test',
-        'Starting swap using move algorithm'
+        upgrade_string_to_verify
     ])
     logger.info('Verify new APP is booted')
     check_with_shell_command(shell, new_version, swap_type='test')
@@ -87,7 +95,7 @@ def test_upgrade_with_confirm(dut: DeviceAdapter, shell: Shell, mcumgr: MCUmgr):
     dut.connect()
     output = dut.readlines_until('Launching primary slot application')
     match_no_lines(output, [
-        'Starting swap using move algorithm'
+        upgrade_string_to_verify
     ])
     logger.info('Verify new APP is still booted')
     check_with_shell_command(shell, new_version)
@@ -126,9 +134,10 @@ def test_upgrade_with_revert(dut: DeviceAdapter, shell: Shell, mcumgr: MCUmgr):
 
     dut.connect()
     output = dut.readlines_until('Launching primary slot application')
+    upgrade_string_to_verify = get_upgrade_string_to_verify(dut.device_config.build_dir)
     match_lines(output, [
         'Swap type: test',
-        'Starting swap using move algorithm'
+        upgrade_string_to_verify
     ])
     logger.info('Verify new APP is booted')
     check_with_shell_command(shell, new_version, swap_type='test')
@@ -142,7 +151,7 @@ def test_upgrade_with_revert(dut: DeviceAdapter, shell: Shell, mcumgr: MCUmgr):
     output = dut.readlines_until('Launching primary slot application')
     match_lines(output, [
         'Swap type: revert',
-        'Starting swap using move algorithm'
+        upgrade_string_to_verify
     ])
     logger.info('Verify that MCUboot reverts update')
     check_with_shell_command(shell, origin_version)
@@ -202,5 +211,6 @@ def test_upgrade_signature(dut: DeviceAdapter, shell: Shell, mcumgr: MCUmgr, key
 
     dut.connect()
     output = dut.readlines_until('Launching primary slot application')
-    match_no_lines(output, ['Starting swap using move algorithm'])
+    upgrade_string_to_verify = get_upgrade_string_to_verify(dut.device_config.build_dir)
+    match_no_lines(output, [upgrade_string_to_verify])
     match_lines(output, ['Image in the secondary slot is not valid'])
diff --git a/tests/boot/with_mcumgr/testcase.yaml b/tests/boot/with_mcumgr/testcase.yaml
index 0500bbaddf5..b4b23be1600 100644
--- a/tests/boot/with_mcumgr/testcase.yaml
+++ b/tests/boot/with_mcumgr/testcase.yaml
@@ -1,31 +1,32 @@
 common:
   sysbuild: true
   platform_allow:
-    - nrf52840dk/nrf52840
     - nrf5340dk/nrf5340/cpuapp
     - nrf54l15dk/nrf54l15/cpuapp
     - nrf9160dk/nrf9160
     - nucleo_wba55cg
-  integration_platforms:
-    - nrf52840dk/nrf52840
   timeout: 600
   slow: true
+  tags:
+    - pytest
+    - mcuboot
+    - mcumgr
 tests:
   boot.with_mcumgr.test_upgrade:
-    tags:
-      - pytest
-      - mcuboot
-      - mcumgr
+    platform_allow:
+      - nrf52840dk/nrf52840
+    integration_platforms:
+      - nrf52840dk/nrf52840
     harness: pytest
     harness_config:
       pytest_root:
         - "pytest/test_upgrade.py"
 
   boot.with_mcumgr.test_downgrade_prevention:
-    tags:
-      - pytest
-      - mcuboot
-      - mcumgr
+    platform_allow:
+      - nrf52840dk/nrf52840
+    integration_platforms:
+      - nrf52840dk/nrf52840
     harness: pytest
     harness_config:
       pytest_root:
@@ -34,3 +35,13 @@ tests:
       - mcuboot_CONFIG_MCUBOOT_DOWNGRADE_PREVENTION=y
     extra_configs:
       - CONFIG_MCUBOOT_IMGTOOL_SIGN_VERSION="1.1.1+1"
+
+  boot.with_mcumgr.test_upgrade.swap_using_offset:
+    integration_platforms:
+      - nrf5340dk/nrf5340/cpuapp
+    harness: pytest
+    harness_config:
+      pytest_root:
+        - "pytest/test_upgrade.py"
+    extra_args:
+      - SB_CONFIG_MCUBOOT_MODE_SWAP_USING_OFFSET=y
diff --git a/tests/bsim/bluetooth/audio/overlay-bt_ll_sw_split.conf b/tests/bsim/bluetooth/audio/overlay-bt_ll_sw_split.conf
index a8dcadfbca6..26718f348a3 100644
--- a/tests/bsim/bluetooth/audio/overlay-bt_ll_sw_split.conf
+++ b/tests/bsim/bluetooth/audio/overlay-bt_ll_sw_split.conf
@@ -71,7 +71,6 @@ CONFIG_BT_CTLR_PERIPHERAL_ISO=y
 CONFIG_BT_CTLR_CONN_ISO_GROUPS=1
 CONFIG_BT_CTLR_CONN_ISO_STREAMS=2
 CONFIG_BT_CTLR_CONN_ISO_STREAMS_PER_GROUP=2
-CONFIG_BT_CTLR_CONN_ISO_SDU_LEN_MAX=247
 CONFIG_BT_CTLR_CONN_ISO_PDU_LEN_MAX=251
 CONFIG_BT_CTLR_CONN_ISO_LOW_LATENCY_POLICY=y
 
@@ -79,6 +78,7 @@ CONFIG_BT_CTLR_CONN_ISO_LOW_LATENCY_POLICY=y
 CONFIG_BT_CTLR_ISOAL_SOURCES=4
 CONFIG_BT_CTLR_ISO_TX_BUFFERS=18
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=255
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=4095
 
 # ISO Receptions
 CONFIG_BT_CTLR_ISOAL_SINKS=4
diff --git a/tests/bsim/bluetooth/audio/overlay-nrf5340_cpunet_iso-bt_ll_sw_split.conf b/tests/bsim/bluetooth/audio/overlay-nrf5340_cpunet_iso-bt_ll_sw_split.conf
index d90eca55e7c..869d43f5fbc 100644
--- a/tests/bsim/bluetooth/audio/overlay-nrf5340_cpunet_iso-bt_ll_sw_split.conf
+++ b/tests/bsim/bluetooth/audio/overlay-nrf5340_cpunet_iso-bt_ll_sw_split.conf
@@ -5,6 +5,7 @@
 CONFIG_BT_ISO_TX_BUF_COUNT=18
 
 CONFIG_BT_CTLR_ISO_TX_BUFFERS=18
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=4095
 
 CONFIG_BT_CTLR_ADV_ISO_STREAM_COUNT=4
 CONFIG_BT_CTLR_ADV_ISO_STREAM_MAX=4
@@ -14,3 +15,7 @@ CONFIG_BT_CTLR_SYNC_ISO_STREAM_MAX=4
 
 CONFIG_BT_CTLR_ISOAL_SOURCES=4
 CONFIG_BT_CTLR_ISOAL_SINKS=4
+
+CONFIG_ASSERT=y
+CONFIG_DEBUG_INFO=y
+CONFIG_EXCEPTION_STACK_TRACE=y
diff --git a/tests/bsim/bluetooth/audio/prj.conf b/tests/bsim/bluetooth/audio/prj.conf
index aa9911e5be6..e643df8d5c9 100644
--- a/tests/bsim/bluetooth/audio/prj.conf
+++ b/tests/bsim/bluetooth/audio/prj.conf
@@ -97,6 +97,8 @@ CONFIG_BT_CSIP_SET_COORDINATOR_TEST_SAMPLE_DATA=y
 CONFIG_BT_CCP_CALL_CONTROL_SERVER=y
 CONFIG_BT_TBS=y
 CONFIG_BT_TBS_BEARER_COUNT=1
+
+CONFIG_BT_CCP_CALL_CONTROL_CLIENT=y
 CONFIG_BT_TBS_CLIENT_TBS=y
 CONFIG_BT_TBS_CLIENT_GTBS=y
 CONFIG_BT_TBS_CLIENT_MAX_CALLS=4
diff --git a/tests/bsim/bluetooth/audio/src/bap_broadcast_assistant_test.c b/tests/bsim/bluetooth/audio/src/bap_broadcast_assistant_test.c
index bb8f44c5b90..719315f9799 100644
--- a/tests/bsim/bluetooth/audio/src/bap_broadcast_assistant_test.c
+++ b/tests/bsim/bluetooth/audio/src/bap_broadcast_assistant_test.c
@@ -142,7 +142,7 @@ static void bap_broadcast_assistant_recv_state_cb(
 		SET_FLAG(flag_broadcast_code_requested);
 	} else if (state->encrypt_state == BT_BAP_BIG_ENC_STATE_BAD_CODE) {
 		SET_FLAG(flag_incorrect_broadcast_code);
-		if (memcmp(state->bad_code, INCORRECT_BROADCAST_CODE, BT_ISO_BROADCAST_CODE_SIZE) !=
+		if (memcmp(state->bad_code, BAD_BROADCAST_CODE, BT_ISO_BROADCAST_CODE_SIZE) !=
 		    0) {
 			FAIL("Bad code is not what we sent\n");
 			return;
diff --git a/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c b/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c
index 27ec575e56b..be580e02ea6 100644
--- a/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c
+++ b/tests/bsim/bluetooth/audio/src/bap_broadcast_sink_test.c
@@ -569,6 +569,7 @@ static void stream_started_cb(struct bt_bap_stream *stream)
 
 	memset(&test_stream->last_info, 0, sizeof(test_stream->last_info));
 	test_stream->rx_cnt = 0U;
+	test_stream->valid_rx_cnt = 0U;
 
 	err = bt_bap_ep_get_info(stream->ep, &info);
 	if (err != 0) {
@@ -627,6 +628,12 @@ static int init(void)
 	static struct bt_pacs_cap vs_cap = {
 		.codec_cap = &vs_codec_cap,
 	};
+	const struct bt_pacs_register_param pacs_param = {
+		.snk_pac = true,
+		.snk_loc = true,
+		.src_pac = true,
+		.src_loc = true,
+	};
 	int err;
 
 	err = bt_enable(NULL);
@@ -637,6 +644,12 @@ static int init(void)
 
 	printk("Bluetooth initialized\n");
 
+	err = bt_pacs_register(&pacs_param);
+	if (err) {
+		FAIL("Could not register PACS (err %d)\n", err);
+		return err;
+	}
+
 	err = bt_pacs_cap_register(BT_AUDIO_DIR_SINK, &cap);
 	if (err) {
 		FAIL("Capability register failed (err %d)\n", err);
diff --git a/tests/bsim/bluetooth/audio/src/bap_broadcast_source_test.c b/tests/bsim/bluetooth/audio/src/bap_broadcast_source_test.c
index 838eab27f2e..792161bdadb 100644
--- a/tests/bsim/bluetooth/audio/src/bap_broadcast_source_test.c
+++ b/tests/bsim/bluetooth/audio/src/bap_broadcast_source_test.c
@@ -17,7 +17,9 @@
 #include <zephyr/bluetooth/audio/lc3.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/byteorder.h>
+#include <zephyr/bluetooth/crypto.h>
 #include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/iso.h>
 #include <zephyr/bluetooth/uuid.h>
 #include <zephyr/kernel.h>
diff --git a/tests/bsim/bluetooth/audio/src/bap_common.c b/tests/bsim/bluetooth/audio/src/bap_common.c
index 055c87d7831..b21e0427e53 100644
--- a/tests/bsim/bluetooth/audio/src/bap_common.c
+++ b/tests/bsim/bluetooth/audio/src/bap_common.c
@@ -9,7 +9,9 @@
 #include <stdint.h>
 #include <string.h>
 
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/audio/audio.h>
+#include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/iso.h>
diff --git a/tests/bsim/bluetooth/audio/src/bap_common.h b/tests/bsim/bluetooth/audio/src/bap_common.h
index 88f445cddc4..fcfcabaad58 100644
--- a/tests/bsim/bluetooth/audio/src/bap_common.h
+++ b/tests/bsim/bluetooth/audio/src/bap_common.h
@@ -11,13 +11,17 @@
 
 #include <stdbool.h>
 #include <stdint.h>
+#include <stddef.h>
 
 #include <zephyr/bluetooth/audio/audio.h>
+#include <zephyr/bluetooth/audio/bap.h>
 #include <zephyr/bluetooth/audio/bap_lc3_preset.h>
 #include <zephyr/bluetooth/audio/cap.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/kernel.h>
 
+#include "common.h"
+
 #define LONG_META 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, \
 		  0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f, \
 		  0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, \
@@ -44,11 +48,14 @@
 #define INCORRECT_BROADCAST_CODE                                                                   \
 	((uint8_t[]){0xDE, 0xAD, 0xBE, 0xEF, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xaa, 0xbb, 0xcc, \
 		     0xdd, 0xee, 0xff})
+#define BAD_BROADCAST_CODE                                                                         \
+	((uint8_t[]){0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, \
+		     0xFF, 0xFF, 0xFF})
 
 #define BAP_RETRY_WAIT K_MSEC(100)
 
 struct unicast_stream {
-	struct bt_cap_stream stream;
+	struct audio_test_stream stream;
 	struct bt_audio_codec_cfg codec_cfg;
 	struct bt_bap_qos_cfg qos;
 };
diff --git a/tests/bsim/bluetooth/audio/src/bap_stream_rx.c b/tests/bsim/bluetooth/audio/src/bap_stream_rx.c
index 8259e12f367..be79b007eca 100644
--- a/tests/bsim/bluetooth/audio/src/bap_stream_rx.c
+++ b/tests/bsim/bluetooth/audio/src/bap_stream_rx.c
@@ -20,8 +20,9 @@ static void log_stream_rx(struct bt_bap_stream *stream, const struct bt_iso_recv
 {
 	struct audio_test_stream *test_stream = audio_test_stream_from_bap_stream(stream);
 
-	LOG_INF("[%zu]: Incoming audio on stream %p len %u, flags 0x%02X, seq_num %u and ts %u",
-		test_stream->rx_cnt, stream, buf->len, info->flags, info->seq_num, info->ts);
+	LOG_INF("[%zu|%zu]: Incoming audio on stream %p len %u, flags 0x%02X, seq_num %u and ts %u",
+		test_stream->valid_rx_cnt, test_stream->rx_cnt, stream, buf->len, info->flags,
+		info->seq_num, info->ts);
 }
 
 void bap_stream_rx_recv_cb(struct bt_bap_stream *stream, const struct bt_iso_recv_info *info,
@@ -29,47 +30,68 @@ void bap_stream_rx_recv_cb(struct bt_bap_stream *stream, const struct bt_iso_rec
 {
 	struct audio_test_stream *test_stream = audio_test_stream_from_bap_stream(stream);
 
+	test_stream->rx_cnt++;
+	if ((info->flags & BT_ISO_FLAGS_VALID) != 0) {
+		if (memcmp(buf->data, mock_iso_data, buf->len) == 0) {
+			test_stream->valid_rx_cnt++;
+
+			if (test_stream->valid_rx_cnt >= MIN_SEND_COUNT) {
+				/* We set the flag is just one stream has received the expected */
+				SET_FLAG(flag_audio_received);
+			}
+		} else {
+			log_stream_rx(stream, info, buf);
+			FAIL("Unexpected data received\n");
+		}
+	}
+
 	if ((test_stream->rx_cnt % 50U) == 0U) {
 		log_stream_rx(stream, info, buf);
 	}
 
-	if (test_stream->rx_cnt > 0U && info->ts == test_stream->last_info.ts) {
+	if (info->ts == test_stream->last_info.ts) {
 		log_stream_rx(stream, info, buf);
-		FAIL("Duplicated timestamp received: %u\n", test_stream->last_info.ts);
-		return;
+		if (test_stream->valid_rx_cnt > 1U) {
+			FAIL("Duplicated timestamp received: %u\n", test_stream->last_info.ts);
+		}
 	}
 
-	if (test_stream->rx_cnt > 0U && info->seq_num == test_stream->last_info.seq_num) {
+	if (info->seq_num == test_stream->last_info.seq_num) {
 		log_stream_rx(stream, info, buf);
-		FAIL("Duplicated PSN received: %u\n", test_stream->last_info.seq_num);
-		return;
+		if (test_stream->valid_rx_cnt > 1U) {
+			FAIL("Duplicated PSN received: %u\n", test_stream->last_info.seq_num);
+		}
 	}
 
 	if (info->flags & BT_ISO_FLAGS_ERROR) {
 		/* Fail the test if we have not received what we expected */
-		if (!TEST_FLAG(flag_audio_received)) {
-			log_stream_rx(stream, info, buf);
+		log_stream_rx(stream, info, buf);
+		if (test_stream->valid_rx_cnt > 1U && !TEST_FLAG(flag_audio_received)) {
 			FAIL("ISO receive error\n");
 		}
-
-		return;
 	}
 
 	if (info->flags & BT_ISO_FLAGS_LOST) {
 		log_stream_rx(stream, info, buf);
-		FAIL("ISO receive lost\n");
-		return;
+		if (test_stream->valid_rx_cnt > 1U) {
+			FAIL("ISO receive lost\n");
+		}
 	}
+}
 
-	if (memcmp(buf->data, mock_iso_data, buf->len) == 0) {
-		test_stream->rx_cnt++;
+bool bap_stream_rx_can_recv(const struct bt_bap_stream *stream)
+{
+	struct bt_bap_ep_info info;
+	int err;
 
-		if (test_stream->rx_cnt >= MIN_SEND_COUNT) {
-			/* We set the flag is just one stream has received the expected */
-			SET_FLAG(flag_audio_received);
-		}
-	} else {
-		log_stream_rx(stream, info, buf);
-		FAIL("Unexpected data received\n");
+	if (stream == NULL || stream->ep == NULL) {
+		return false;
+	}
+
+	err = bt_bap_ep_get_info(stream->ep, &info);
+	if (err != 0) {
+		return false;
 	}
+
+	return info.can_recv;
 }
diff --git a/tests/bsim/bluetooth/audio/src/bap_stream_rx.h b/tests/bsim/bluetooth/audio/src/bap_stream_rx.h
index d24b679a448..5db4c1e009c 100644
--- a/tests/bsim/bluetooth/audio/src/bap_stream_rx.h
+++ b/tests/bsim/bluetooth/audio/src/bap_stream_rx.h
@@ -10,3 +10,12 @@
 
 void bap_stream_rx_recv_cb(struct bt_bap_stream *stream, const struct bt_iso_recv_info *info,
 			   struct net_buf *buf);
+
+/**
+ * @brief Test if the provided stream has been configured for RX
+ *
+ * @param bap_stream The stream to test for RX support
+ *
+ * @returns true if it has been configured for RX, and false if not
+ */
+bool bap_stream_rx_can_recv(const struct bt_bap_stream *stream);
diff --git a/tests/bsim/bluetooth/audio/src/bap_unicast_server_test.c b/tests/bsim/bluetooth/audio/src/bap_unicast_server_test.c
index 406a1ce822c..980915d21b8 100644
--- a/tests/bsim/bluetooth/audio/src/bap_unicast_server_test.c
+++ b/tests/bsim/bluetooth/audio/src/bap_unicast_server_test.c
@@ -407,6 +407,20 @@ static void init(void)
 	static struct bt_pacs_cap cap = {
 		.codec_cap = &lc3_codec_cap,
 	};
+	const struct bt_pacs_register_param pacs_param = {
+#if defined(CONFIG_BT_PAC_SNK)
+		.snk_pac = true,
+#endif /* CONFIG_BT_PAC_SNK */
+#if defined(CONFIG_BT_PAC_SNK_LOC)
+		.snk_loc = true,
+#endif /* CONFIG_BT_PAC_SNK_LOC */
+#if defined(CONFIG_BT_PAC_SRC)
+		.src_pac = true,
+#endif /* CONFIG_BT_PAC_SRC */
+#if defined(CONFIG_BT_PAC_SRC_LOC)
+		.src_loc = true,
+#endif /* CONFIG_BT_PAC_SRC_LOC */
+	};
 	int err;
 
 	err = bt_enable(NULL);
@@ -416,6 +430,13 @@ static void init(void)
 	}
 
 	printk("Bluetooth initialized\n");
+
+	err = bt_pacs_register(&pacs_param);
+	if (err) {
+		FAIL("Could not register PACS (err %d)\n", err);
+		return;
+	}
+
 	bap_stream_tx_init();
 
 	err = bt_bap_unicast_server_register(&param);
@@ -450,6 +471,29 @@ static void init(void)
 	setup_connectable_adv(&ext_adv);
 }
 
+static void deinit(void)
+{
+	int err;
+
+	err = bt_bap_unicast_server_unregister_cb(&unicast_server_cb);
+	if (err != 0) {
+		FAIL("Failed to unregister unicast server callbacks (err %d)\n", err);
+		return;
+	}
+
+	err = bt_bap_unicast_server_unregister();
+	if (err != 0) {
+		FAIL("Failed to unregister unicast server (err %d)\n", err);
+		return;
+	}
+
+	err = bt_pacs_unregister();
+	if (err != 0) {
+		FAIL("Failed to unregister PACS (err %d)\n", err);
+		return;
+	}
+}
+
 static void test_main(void)
 {
 	init();
@@ -463,6 +507,8 @@ static void test_main(void)
 	WAIT_FOR_FLAG(flag_stream_started);
 	transceive_test_streams();
 	WAIT_FOR_UNSET_FLAG(flag_connected);
+
+	deinit();
 	PASS("Unicast server passed\n");
 }
 
@@ -519,6 +565,8 @@ static void test_main_acl_disconnect(void)
 	/* The client will reconnect */
 	WAIT_FOR_UNSET_FLAG(flag_connected);
 	WAIT_FOR_FLAG(flag_connected);
+
+	deinit();
 	PASS("Unicast server ACL disconnect  passed\n");
 }
 
diff --git a/tests/bsim/bluetooth/audio/src/cap_acceptor_test.c b/tests/bsim/bluetooth/audio/src/cap_acceptor_test.c
index a081326baea..d21b5c01843 100644
--- a/tests/bsim/bluetooth/audio/src/cap_acceptor_test.c
+++ b/tests/bsim/bluetooth/audio/src/cap_acceptor_test.c
@@ -35,6 +35,7 @@
 #include <zephyr/sys/util_macro.h>
 
 #include "bap_stream_rx.h"
+#include "bap_stream_tx.h"
 #include "bstests.h"
 #include "common.h"
 #include "bap_common.h"
@@ -42,6 +43,8 @@
 #if defined(CONFIG_BT_CAP_ACCEPTOR)
 extern enum bst_result_t bst_result;
 
+#define CAP_INITIATOR_DEV_ID 0 /* CAP initiator shall be ID 0 for these tests */
+
 CREATE_FLAG(flag_broadcaster_found);
 CREATE_FLAG(flag_broadcast_code);
 CREATE_FLAG(flag_base_received);
@@ -59,6 +62,7 @@ static bt_addr_le_t broadcaster_addr;
 static struct bt_le_per_adv_sync *pa_sync;
 static uint32_t broadcaster_broadcast_id;
 static struct audio_test_stream broadcast_sink_streams[CONFIG_BT_BAP_BROADCAST_SNK_STREAM_COUNT];
+static bool expect_rx;
 
 static const struct bt_bap_qos_cfg_pref unicast_qos_pref =
 	BT_BAP_QOS_CFG_PREF(true, BT_GAP_LE_PHY_2M, 0u, 60u, 20000u, 40000u, 20000u, 40000u);
@@ -72,8 +76,8 @@ static uint32_t bis_index_bitfield;
 
 #define UNICAST_CHANNEL_COUNT_1 BIT(0)
 
-static struct bt_cap_stream unicast_streams[CONFIG_BT_ASCS_MAX_ASE_SNK_COUNT +
-					    CONFIG_BT_ASCS_MAX_ASE_SRC_COUNT];
+static struct audio_test_stream
+	unicast_streams[CONFIG_BT_ASCS_MAX_ASE_SNK_COUNT + CONFIG_BT_ASCS_MAX_ASE_SRC_COUNT];
 
 static bool subgroup_data_func_cb(struct bt_data *data, void *user_data)
 {
@@ -275,6 +279,7 @@ static void started_cb(struct bt_bap_stream *stream)
 
 	memset(&test_stream->last_info, 0, sizeof(test_stream->last_info));
 	test_stream->rx_cnt = 0U;
+	test_stream->valid_rx_cnt = 0U;
 	test_stream->seq_num = 0U;
 	test_stream->tx_cnt = 0U;
 
@@ -319,8 +324,52 @@ static void unicast_stream_enabled_cb(struct bt_bap_stream *stream)
 	}
 }
 
+static void unicast_stream_started(struct bt_bap_stream *stream)
+{
+	struct audio_test_stream *test_stream = audio_test_stream_from_bap_stream(stream);
+
+	memset(&test_stream->last_info, 0, sizeof(test_stream->last_info));
+	test_stream->rx_cnt = 0U;
+	test_stream->valid_rx_cnt = 0U;
+	test_stream->seq_num = 0U;
+	test_stream->tx_cnt = 0U;
+
+	printk("Started stream %p\n", stream);
+
+	if (bap_stream_tx_can_send(stream)) {
+		int err;
+
+		err = bap_stream_tx_register(stream);
+		if (err != 0) {
+			FAIL("Failed to register stream %p for TX: %d\n", stream, err);
+			return;
+		}
+	} else if (bap_stream_rx_can_recv(stream)) {
+		expect_rx = true;
+	}
+}
+
+static void unicast_stream_stopped(struct bt_bap_stream *stream, uint8_t reason)
+{
+	printk("Stopped stream %p with reason 0x%02X\n", stream, reason);
+
+	if (bap_stream_tx_can_send(stream)) {
+		int err;
+
+		err = bap_stream_tx_unregister(stream);
+		if (err != 0) {
+			FAIL("Failed to unregister stream %p for TX: %d\n", stream, err);
+			return;
+		}
+	}
+}
+
 static struct bt_bap_stream_ops unicast_stream_ops = {
 	.enabled = unicast_stream_enabled_cb,
+	.started = unicast_stream_started,
+	.stopped = unicast_stream_stopped,
+	.sent = bap_stream_tx_sent_cb,
+	.recv = bap_stream_rx_recv_cb,
 };
 
 static int pa_sync_req_cb(struct bt_conn *conn,
@@ -404,7 +453,8 @@ static struct bt_csip_set_member_svc_inst *csip_set_member;
 static struct bt_bap_stream *unicast_stream_alloc(void)
 {
 	for (size_t i = 0; i < ARRAY_SIZE(unicast_streams); i++) {
-		struct bt_bap_stream *stream = &unicast_streams[i].bap_stream;
+		struct bt_bap_stream *stream =
+			bap_stream_from_audio_test_stream(&unicast_streams[i]);
 
 		if (!stream->conn) {
 			return stream;
@@ -637,6 +687,20 @@ static void init(void)
 		BT_AUDIO_CODEC_CAP_FREQ_ANY, BT_AUDIO_CODEC_CAP_DURATION_ANY,
 		BT_AUDIO_CODEC_CAP_CHAN_COUNT_SUPPORT(1, 2), 30, 240, 2,
 		(BT_AUDIO_CONTEXT_TYPE_CONVERSATIONAL | BT_AUDIO_CONTEXT_TYPE_MEDIA));
+	const struct bt_pacs_register_param pacs_param = {
+#if defined(CONFIG_BT_PAC_SNK)
+		.snk_pac = true,
+#endif /* CONFIG_BT_PAC_SNK */
+#if defined(CONFIG_BT_PAC_SNK_LOC)
+		.snk_loc = true,
+#endif /* CONFIG_BT_PAC_SNK_LOC */
+#if defined(CONFIG_BT_PAC_SRC)
+		.src_pac = true,
+#endif /* CONFIG_BT_PAC_SRC */
+#if defined(CONFIG_BT_PAC_SRC_LOC)
+		.src_loc = true,
+#endif /* CONFIG_BT_PAC_SRC_LOC */
+	};
 	int err;
 
 	err = bt_enable(NULL);
@@ -646,6 +710,13 @@ static void init(void)
 	}
 
 	printk("Bluetooth initialized\n");
+	bap_stream_tx_init();
+
+	err = bt_pacs_register(&pacs_param);
+	if (err) {
+		FAIL("Could not register PACS (err %d)\n", err);
+		return;
+	}
 
 	if (IS_ENABLED(CONFIG_BT_CAP_ACCEPTOR_SET_MEMBER)) {
 		err = bt_cap_acceptor_register(&csip_set_member_param, &csip_set_member);
@@ -691,7 +762,9 @@ static void init(void)
 		}
 
 		for (size_t i = 0U; i < ARRAY_SIZE(unicast_streams); i++) {
-			bt_cap_stream_ops_register(&unicast_streams[i], &unicast_stream_ops);
+			bt_cap_stream_ops_register(
+				cap_stream_from_audio_test_stream(&unicast_streams[i]),
+				&unicast_stream_ops);
 		}
 	}
 
@@ -807,6 +880,13 @@ static void init(void)
 	}
 }
 
+static void wait_for_data(void)
+{
+	printk("Waiting for data\n");
+	WAIT_FOR_FLAG(flag_audio_received);
+	printk("Data received\n");
+}
+
 static void test_cap_acceptor_unicast(void)
 {
 	init();
@@ -815,10 +895,17 @@ static void test_cap_acceptor_unicast(void)
 
 	auto_start_sink_streams = true;
 
-	/* TODO: wait for audio stream to pass */
-
 	WAIT_FOR_FLAG(flag_connected);
 
+	/* Wait until initiator is done starting streams */
+	backchannel_sync_wait(CAP_INITIATOR_DEV_ID);
+
+	if (expect_rx) {
+		wait_for_data();
+	}
+	/* let initiator know we have received what we wanted */
+	backchannel_sync_send(CAP_INITIATOR_DEV_ID);
+
 	PASS("CAP acceptor unicast passed\n");
 }
 
@@ -830,8 +917,6 @@ static void test_cap_acceptor_unicast_timeout(void)
 
 	auto_start_sink_streams = false; /* Cause unicast_audio_start timeout */
 
-	/* TODO: wait for audio stream to pass */
-
 	WAIT_FOR_FLAG(flag_connected);
 
 	PASS("CAP acceptor unicast passed\n");
@@ -927,13 +1012,6 @@ static void create_and_sync_sink(struct bt_bap_stream *bap_streams[], size_t *st
 	}
 }
 
-static void sink_wait_for_data(void)
-{
-	printk("Waiting for data\n");
-	WAIT_FOR_FLAG(flag_audio_received);
-	backchannel_sync_send_all(); /* let other devices know we have received what we wanted */
-}
-
 static void wait_for_broadcast_code(void)
 {
 	printk("Waiting for broadcast code\n");
@@ -966,7 +1044,33 @@ static void test_cap_acceptor_broadcast(void)
 
 	create_and_sync_sink(bap_streams, &stream_count);
 
-	sink_wait_for_data();
+	wait_for_data();
+	/* let other devices know we have received what we wanted */
+	backchannel_sync_send_all();
+
+	wait_for_streams_stop(stream_count);
+
+	PASS("CAP acceptor broadcast passed\n");
+}
+
+static void test_cap_acceptor_broadcast_update(void)
+{
+	static struct bt_bap_stream *bap_streams[ARRAY_SIZE(broadcast_sink_streams)];
+	size_t stream_count;
+
+	init();
+
+	pa_sync_to_broadcaster();
+
+	create_and_sync_sink(bap_streams, &stream_count);
+
+	wait_for_data();
+
+	printk("Waiting for metadata update");
+	WAIT_FOR_FLAG(flag_base_metadata_updated);
+	backchannel_sync_send_all(); /* let other devices know we have received metadata */
+	/* let other devices know we have received what we wanted */
+	backchannel_sync_send_all();
 
 	wait_for_streams_stop(stream_count);
 
@@ -991,7 +1095,9 @@ static void test_cap_acceptor_broadcast_reception(void)
 	create_and_sync_sink(bap_streams, &stream_count);
 
 	wait_for_broadcast_code();
-	sink_wait_for_data();
+	wait_for_data();
+	/* let other devices know we have received what we wanted */
+	backchannel_sync_send_all();
 
 	/* when flag_bis_sync_requested is unset the bis_sync for all subgroups were set to 0 */
 	WAIT_FOR_UNSET_FLAG(flag_bis_sync_requested);
@@ -1042,6 +1148,12 @@ static const struct bst_test_instance test_cap_acceptor[] = {
 		.test_tick_f = test_tick,
 		.test_main_f = test_cap_acceptor_broadcast,
 	},
+	{
+		.test_id = "cap_acceptor_broadcast_update",
+		.test_pre_init_f = test_init,
+		.test_tick_f = test_tick,
+		.test_main_f = test_cap_acceptor_broadcast_update,
+	},
 	{
 		.test_id = "cap_acceptor_broadcast_reception",
 		.test_pre_init_f = test_init,
diff --git a/tests/bsim/bluetooth/audio/src/cap_commander_test.c b/tests/bsim/bluetooth/audio/src/cap_commander_test.c
index de623142a09..b4c6d8c167c 100644
--- a/tests/bsim/bluetooth/audio/src/cap_commander_test.c
+++ b/tests/bsim/bluetooth/audio/src/cap_commander_test.c
@@ -3,6 +3,7 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <errno.h>
 #include <stdbool.h>
 #include <stddef.h>
 #include <stdint.h>
diff --git a/tests/bsim/bluetooth/audio/src/cap_initiator_broadcast_test.c b/tests/bsim/bluetooth/audio/src/cap_initiator_broadcast_test.c
index abd43e98f79..c84fc83742f 100644
--- a/tests/bsim/bluetooth/audio/src/cap_initiator_broadcast_test.c
+++ b/tests/bsim/bluetooth/audio/src/cap_initiator_broadcast_test.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2024 Nordic Semiconductor ASA
+ * Copyright (c) 2022-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -18,6 +18,7 @@
 #include <zephyr/bluetooth/audio/tbs.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/byteorder.h>
+#include <zephyr/bluetooth/crypto.h>
 #include <zephyr/bluetooth/gap.h>
 #include <zephyr/bluetooth/iso.h>
 #include <zephyr/bluetooth/uuid.h>
@@ -623,10 +624,8 @@ static void test_main_cap_initiator_broadcast(void)
 
 	setup_broadcast_adv(&adv);
 
-	test_broadcast_audio_create_inval();
 	test_broadcast_audio_create(&broadcast_source);
 
-	test_broadcast_audio_start_inval(broadcast_source, adv);
 	test_broadcast_audio_start(broadcast_source, adv);
 
 	setup_extended_adv_data(broadcast_source, adv);
@@ -641,17 +640,57 @@ static void test_main_cap_initiator_broadcast(void)
 
 	WAIT_FOR_FLAG(flag_source_started);
 
-	/* Wait for other devices to have received what they wanted */
+	/* Wait for other devices to have received the data they wanted */
 	backchannel_sync_wait_any();
 
+	test_broadcast_audio_tx_sync();
+
+	test_broadcast_audio_stop(broadcast_source);
+
+	test_broadcast_audio_delete(broadcast_source);
+	broadcast_source = NULL;
+
+	stop_and_delete_extended_adv(adv);
+	adv = NULL;
+
+	PASS("CAP initiator broadcast passed\n");
+}
+
+static void test_main_cap_initiator_broadcast_inval(void)
+{
+	struct bt_cap_broadcast_source *broadcast_source;
+	struct bt_le_ext_adv *adv;
+
+	(void)memset(broadcast_source_streams, 0, sizeof(broadcast_source_streams));
+
+	init();
+
+	setup_broadcast_adv(&adv);
+
+	test_broadcast_audio_create_inval();
+	test_broadcast_audio_create(&broadcast_source);
+
+	test_broadcast_audio_start_inval(broadcast_source, adv);
+	test_broadcast_audio_start(broadcast_source, adv);
+
+	setup_extended_adv_data(broadcast_source, adv);
+
+	start_extended_adv(adv);
+
+	/* Wait for all to be started */
+	printk("Waiting for broadcast_streams to be started\n");
+	for (size_t i = 0U; i < stream_count; i++) {
+		k_sem_take(&sem_broadcast_stream_started, K_FOREVER);
+	}
+
+	WAIT_FOR_FLAG(flag_source_started);
+
 	test_broadcast_audio_update_inval(broadcast_source);
 	test_broadcast_audio_update(broadcast_source);
 
 	/* Keeping running for a little while */
 	k_sleep(K_SECONDS(5));
 
-	test_broadcast_audio_tx_sync();
-
 	test_broadcast_audio_stop_inval();
 	test_broadcast_audio_stop(broadcast_source);
 
@@ -662,6 +701,54 @@ static void test_main_cap_initiator_broadcast(void)
 	stop_and_delete_extended_adv(adv);
 	adv = NULL;
 
+	PASS("CAP initiator broadcast inval passed\n");
+}
+
+static void test_main_cap_initiator_broadcast_update(void)
+{
+	struct bt_cap_broadcast_source *broadcast_source;
+	struct bt_le_ext_adv *adv;
+
+	(void)memset(broadcast_source_streams, 0, sizeof(broadcast_source_streams));
+
+	init();
+
+	setup_broadcast_adv(&adv);
+
+	test_broadcast_audio_create(&broadcast_source);
+
+	test_broadcast_audio_start(broadcast_source, adv);
+
+	setup_extended_adv_data(broadcast_source, adv);
+
+	start_extended_adv(adv);
+
+	/* Wait for all to be started */
+	printk("Waiting for broadcast_streams to be started\n");
+	for (size_t i = 0U; i < stream_count; i++) {
+		k_sem_take(&sem_broadcast_stream_started, K_FOREVER);
+	}
+
+	WAIT_FOR_FLAG(flag_source_started);
+
+	/* Wait for other devices to have received the data they wanted */
+	backchannel_sync_wait_any();
+
+	test_broadcast_audio_update(broadcast_source);
+
+	/* Wait for other devices to have received the update */
+	backchannel_sync_wait_any();
+
+	test_broadcast_audio_tx_sync();
+
+	test_broadcast_audio_stop(broadcast_source);
+
+	test_broadcast_audio_delete(broadcast_source);
+	broadcast_source = NULL;
+
+	stop_and_delete_extended_adv(adv);
+	adv = NULL;
+
 	PASS("CAP initiator broadcast passed\n");
 }
 
@@ -828,6 +915,18 @@ static const struct bst_test_instance test_cap_initiator_broadcast[] = {
 		.test_tick_f = test_tick,
 		.test_main_f = test_main_cap_initiator_broadcast,
 	},
+	{
+		.test_id = "cap_initiator_broadcast_inval",
+		.test_pre_init_f = test_init,
+		.test_tick_f = test_tick,
+		.test_main_f = test_main_cap_initiator_broadcast_inval,
+	},
+	{
+		.test_id = "cap_initiator_broadcast_update",
+		.test_pre_init_f = test_init,
+		.test_tick_f = test_tick,
+		.test_main_f = test_main_cap_initiator_broadcast_update,
+	},
 	{
 		.test_id = "cap_initiator_ac_12",
 		.test_pre_init_f = test_init,
diff --git a/tests/bsim/bluetooth/audio/src/cap_initiator_unicast_test.c b/tests/bsim/bluetooth/audio/src/cap_initiator_unicast_test.c
index fdf6eb909ab..d3e415ac396 100644
--- a/tests/bsim/bluetooth/audio/src/cap_initiator_unicast_test.c
+++ b/tests/bsim/bluetooth/audio/src/cap_initiator_unicast_test.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2022-2023 Nordic Semiconductor ASA
+ * Copyright (c) 2022-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -34,6 +34,8 @@
 #include <zephyr/sys/util_macro.h>
 #include <zephyr/sys_clock.h>
 
+#include "bap_stream_tx.h"
+#include "bap_stream_rx.h"
 #include "bstests.h"
 #include "common.h"
 #include "bap_common.h"
@@ -67,8 +69,9 @@ extern enum bst_result_t bst_result;
 static struct bt_bap_lc3_preset unicast_preset_16_2_1 = BT_BAP_LC3_UNICAST_PRESET_16_2_1(
 	BT_AUDIO_LOCATION_FRONT_LEFT, BT_AUDIO_CONTEXT_TYPE_UNSPECIFIED);
 
-static struct bt_cap_stream unicast_client_sink_streams[CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SNK_COUNT];
-static struct bt_cap_stream
+static struct audio_test_stream
+	unicast_client_sink_streams[CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SNK_COUNT];
+static struct audio_test_stream
 	unicast_client_source_streams[CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SRC_COUNT];
 static struct bt_bap_ep
 	*unicast_sink_eps[CONFIG_BT_MAX_CONN][CONFIG_BT_BAP_UNICAST_CLIENT_ASE_SNK_COUNT];
@@ -163,7 +166,25 @@ static void unicast_stream_enabled(struct bt_bap_stream *stream)
 
 static void unicast_stream_started(struct bt_bap_stream *stream)
 {
+	struct audio_test_stream *test_stream = audio_test_stream_from_bap_stream(stream);
+
+	memset(&test_stream->last_info, 0, sizeof(test_stream->last_info));
+	test_stream->rx_cnt = 0U;
+	test_stream->valid_rx_cnt = 0U;
+	test_stream->seq_num = 0U;
+	test_stream->tx_cnt = 0U;
+
 	printk("Started stream %p\n", stream);
+
+	if (bap_stream_tx_can_send(stream)) {
+		int err;
+
+		err = bap_stream_tx_register(stream);
+		if (err != 0) {
+			FAIL("Failed to register stream %p for TX: %d\n", stream, err);
+			return;
+		}
+	}
 }
 
 static void unicast_stream_metadata_updated(struct bt_bap_stream *stream)
@@ -179,6 +200,16 @@ static void unicast_stream_disabled(struct bt_bap_stream *stream)
 static void unicast_stream_stopped(struct bt_bap_stream *stream, uint8_t reason)
 {
 	printk("Stopped stream %p with reason 0x%02X\n", stream, reason);
+
+	if (bap_stream_tx_can_send(stream)) {
+		int err;
+
+		err = bap_stream_tx_unregister(stream);
+		if (err != 0) {
+			FAIL("Failed to unregister stream %p for TX: %d\n", stream, err);
+			return;
+		}
+	}
 }
 
 static void unicast_stream_released(struct bt_bap_stream *stream)
@@ -207,6 +238,8 @@ static struct bt_bap_stream_ops unicast_stream_ops = {
 	.disabled = unicast_stream_disabled,
 	.stopped = unicast_stream_stopped,
 	.released = unicast_stream_released,
+	.sent = bap_stream_tx_sent_cb,
+	.recv = bap_stream_rx_recv_cb,
 };
 
 static void cap_discovery_complete_cb(struct bt_conn *conn, int err,
@@ -443,6 +476,9 @@ static void init(void)
 		return;
 	}
 
+	printk("Bluetooth initialized\n");
+	bap_stream_tx_init();
+
 	bt_gatt_cb_register(&gatt_callbacks);
 	err = bt_le_scan_cb_register(&scan_callbacks);
 	if (err != 0) {
@@ -463,15 +499,21 @@ static void init(void)
 	}
 
 	for (size_t i = 0; i < ARRAY_SIZE(unicast_client_sink_streams); i++) {
-		bt_cap_stream_ops_register(&unicast_client_sink_streams[i], &unicast_stream_ops);
+		bt_cap_stream_ops_register(
+			cap_stream_from_audio_test_stream(&unicast_client_sink_streams[i]),
+			&unicast_stream_ops);
 	}
 
 	for (size_t i = 0; i < ARRAY_SIZE(unicast_client_source_streams); i++) {
-		bt_cap_stream_ops_register(&unicast_client_source_streams[i], &unicast_stream_ops);
+		bt_cap_stream_ops_register(
+			cap_stream_from_audio_test_stream(&unicast_client_source_streams[i]),
+			&unicast_stream_ops);
 	}
 
 	for (size_t i = 0; i < ARRAY_SIZE(unicast_streams); i++) {
-		bt_cap_stream_ops_register(&unicast_streams[i].stream, &unicast_stream_ops);
+		bt_cap_stream_ops_register(
+			cap_stream_from_audio_test_stream(&unicast_streams[i].stream),
+			&unicast_stream_ops);
 	}
 }
 
@@ -583,9 +625,11 @@ static void unicast_group_create(struct bt_bap_unicast_group **out_unicast_group
 	int err;
 
 	group_sink_stream_params.qos = &unicast_preset_16_2_1.qos;
-	group_sink_stream_params.stream = &unicast_client_sink_streams[0].bap_stream;
+	group_sink_stream_params.stream =
+		bap_stream_from_audio_test_stream(&unicast_client_sink_streams[0]);
 	group_source_stream_params.qos = &unicast_preset_16_2_1.qos;
-	group_source_stream_params.stream = &unicast_client_source_streams[0].bap_stream;
+	group_source_stream_params.stream =
+		bap_stream_from_audio_test_stream(&unicast_client_source_streams[0]);
 	pair_params.tx_param = &group_sink_stream_params;
 	pair_params.rx_param = &group_source_stream_params;
 
@@ -610,12 +654,13 @@ static void unicast_audio_start(struct bt_bap_unicast_group *unicast_group, bool
 	param.count = ARRAY_SIZE(stream_param);
 	param.stream_params = stream_param;
 	stream_param[0].member.member = default_conn;
-	stream_param[0].stream = &unicast_client_sink_streams[0];
+	stream_param[0].stream = cap_stream_from_audio_test_stream(&unicast_client_sink_streams[0]);
 	stream_param[0].ep = unicast_sink_eps[bt_conn_index(default_conn)][0];
 	stream_param[0].codec_cfg = &unicast_preset_16_2_1.codec_cfg;
 
 	stream_param[1].member.member = default_conn;
-	stream_param[1].stream = &unicast_client_source_streams[0];
+	stream_param[1].stream =
+		cap_stream_from_audio_test_stream(&unicast_client_source_streams[0]);
 	stream_param[1].ep = unicast_source_eps[bt_conn_index(default_conn)][0];
 	stream_param[1].codec_cfg = &unicast_preset_16_2_1.codec_cfg;
 
@@ -629,6 +674,8 @@ static void unicast_audio_start(struct bt_bap_unicast_group *unicast_group, bool
 
 	if (wait) {
 		WAIT_FOR_FLAG(flag_started);
+		/* let other devices know we have started what we wanted */
+		backchannel_sync_send_all();
 	}
 }
 
@@ -641,7 +688,8 @@ static void unicast_audio_update_inval(void)
 	struct bt_cap_unicast_audio_update_param param = {0};
 	int err;
 
-	stream_params[0].stream = &unicast_client_sink_streams[0];
+	stream_params[0].stream =
+		cap_stream_from_audio_test_stream(&unicast_client_sink_streams[0]);
 	stream_params[0].meta = unicast_preset_16_2_1.codec_cfg.meta;
 	stream_params[0].meta_len = unicast_preset_16_2_1.codec_cfg.meta_len;
 	param.count = ARRAY_SIZE(stream_params);
@@ -688,11 +736,13 @@ static void unicast_audio_update(void)
 	};
 	int err;
 
-	stream_params[0].stream = &unicast_client_sink_streams[0];
+	stream_params[0].stream =
+		cap_stream_from_audio_test_stream(&unicast_client_sink_streams[0]);
 	stream_params[0].meta = new_meta;
 	stream_params[0].meta_len = ARRAY_SIZE(new_meta);
 
-	stream_params[1].stream = &unicast_client_source_streams[0];
+	stream_params[1].stream =
+		cap_stream_from_audio_test_stream(&unicast_client_source_streams[0]);
 	stream_params[1].meta = new_meta;
 	stream_params[1].meta_len = ARRAY_SIZE(new_meta);
 
@@ -709,7 +759,6 @@ static void unicast_audio_update(void)
 	}
 
 	WAIT_FOR_FLAG(flag_updated);
-	printk("READ LONG META\n");
 }
 
 static void unicast_audio_stop(struct bt_bap_unicast_group *unicast_group)
@@ -824,15 +873,30 @@ static void test_main_cap_initiator_unicast(void)
 
 	for (size_t i = 0U; i < iterations; i++) {
 		printk("\nRunning iteration i=%zu\n\n", i);
+
 		unicast_group_create(&unicast_group);
 
 		for (size_t j = 0U; j < iterations; j++) {
 			printk("\nRunning iteration j=%zu\n\n", i);
 
+			UNSET_FLAG(flag_audio_received);
+
 			unicast_audio_start(unicast_group, true);
 
 			unicast_audio_update();
 
+			printk("Waiting for data\n");
+			WAIT_FOR_FLAG(flag_audio_received);
+
+			/* Due to how the backchannel sync is implemented for LE Audio we cannot
+			 * easily tell the remote (CAP acceptor) how many times to wait for data,
+			 * and thus we only await one sync message from it from the first iteration
+			 */
+			if (i == 0 && j == 0) {
+				/* Wait until acceptors have received expected data */
+				backchannel_sync_wait_all();
+			}
+
 			unicast_audio_stop(unicast_group);
 		}
 
@@ -866,6 +930,13 @@ static void test_main_cap_initiator_unicast_inval(void)
 	unicast_audio_update_inval();
 	unicast_audio_update();
 
+	printk("Waiting for data\n");
+	WAIT_FOR_FLAG(flag_audio_received);
+	printk("Data received\n");
+
+	/* Wait until acceptors have received expected data */
+	backchannel_sync_wait_all();
+
 	unicast_audio_stop(unicast_group);
 
 	unicast_group_delete_inval();
@@ -969,6 +1040,13 @@ static void test_cap_initiator_unicast_ase_error(void)
 	/* Without invalid metadata type, start should pass */
 	unicast_audio_start(unicast_group, true);
 
+	printk("Waiting for data\n");
+	WAIT_FOR_FLAG(flag_audio_received);
+	printk("Data received\n");
+
+	/* Wait until acceptors have received expected data */
+	backchannel_sync_wait_all();
+
 	unicast_audio_stop(unicast_group);
 
 	unicast_group_delete(unicast_group);
@@ -1020,11 +1098,13 @@ static int cap_initiator_ac_create_unicast_group(const struct cap_initiator_ac_p
 	 */
 	for (size_t i = 0U; i < snk_cnt; i++) {
 		snk_group_stream_params[i].qos = snk_qos[i];
-		snk_group_stream_params[i].stream = &snk_uni_streams[i]->stream.bap_stream;
+		snk_group_stream_params[i].stream =
+			bap_stream_from_audio_test_stream(&snk_uni_streams[i]->stream);
 	}
 	for (size_t i = 0U; i < src_cnt; i++) {
 		src_group_stream_params[i].qos = src_qos[i];
-		src_group_stream_params[i].stream = &src_uni_streams[i]->stream.bap_stream;
+		src_group_stream_params[i].stream =
+			bap_stream_from_audio_test_stream(&src_uni_streams[i]->stream);
 	}
 
 	for (size_t i = 0U; i < param->conn_cnt; i++) {
@@ -1119,12 +1199,12 @@ static int cap_initiator_ac_cap_unicast_start(const struct cap_initiator_ac_para
 	 * preset so that we can modify them (e.g. update the metadata)
 	 */
 	for (size_t i = 0U; i < snk_cnt; i++) {
-		snk_cap_streams[i] = &snk_uni_streams[i]->stream;
+		snk_cap_streams[i] = cap_stream_from_audio_test_stream(&snk_uni_streams[i]->stream);
 		snk_codec_cfgs[i] = &snk_uni_streams[i]->codec_cfg;
 	}
 
 	for (size_t i = 0U; i < src_cnt; i++) {
-		src_cap_streams[i] = &src_uni_streams[i]->stream;
+		src_cap_streams[i] = cap_stream_from_audio_test_stream(&src_uni_streams[i]->stream);
 		src_codec_cfgs[i] = &src_uni_streams[i]->codec_cfg;
 	}
 
@@ -1289,6 +1369,7 @@ static int cap_initiator_ac_unicast(const struct cap_initiator_ac_param *param,
 	}
 
 	WAIT_FOR_FLAG(flag_started);
+	backchannel_sync_send_all(); /* let other devices know we have started what we wanted */
 
 	return 0;
 }
@@ -1296,6 +1377,8 @@ static int cap_initiator_ac_unicast(const struct cap_initiator_ac_param *param,
 static void test_cap_initiator_ac(const struct cap_initiator_ac_param *param)
 {
 	struct bt_bap_unicast_group *unicast_group;
+	bool expect_tx = false;
+	bool expect_rx = false;
 
 	printk("Running test for %s with Sink Preset %s and Source Preset %s\n", param->name,
 	       param->snk_named_preset != NULL ? param->snk_named_preset->name : "None",
@@ -1335,15 +1418,27 @@ static void test_cap_initiator_ac(const struct cap_initiator_ac_param *param)
 
 		if (param->snk_cnt[i] > 0U) {
 			discover_sink(connected_conns[i]);
+			expect_tx = true;
 		}
 
 		if (param->src_cnt[i] > 0U) {
 			discover_source(connected_conns[i]);
+			expect_rx = true;
 		}
 	}
 
 	cap_initiator_ac_unicast(param, &unicast_group);
 
+	if (expect_tx) {
+		/* Wait until acceptors have received expected data */
+		backchannel_sync_wait_all();
+	}
+
+	if (expect_rx) {
+		printk("Waiting for data\n");
+		WAIT_FOR_FLAG(flag_audio_received);
+	}
+
 	unicast_audio_stop(unicast_group);
 
 	unicast_group_delete(unicast_group);
diff --git a/tests/bsim/bluetooth/audio/src/ccp_call_control_client_test.c b/tests/bsim/bluetooth/audio/src/ccp_call_control_client_test.c
new file mode 100644
index 00000000000..b848dfc5df2
--- /dev/null
+++ b/tests/bsim/bluetooth/audio/src/ccp_call_control_client_test.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stddef.h>
+#include <stdint.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/audio/ccp.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/util_macro.h>
+
+#include "bstests.h"
+#include "common.h"
+
+#ifdef CONFIG_BT_CCP_CALL_CONTROL_CLIENT
+LOG_MODULE_REGISTER(ccp_call_control_client, CONFIG_LOG_DEFAULT_LEVEL);
+
+extern enum bst_result_t bst_result;
+
+CREATE_FLAG(flag_discovery_complete);
+
+static struct bt_ccp_call_control_client *inst;
+
+static void ccp_call_control_client_discover_cb(struct bt_ccp_call_control_client *client, int err,
+						struct bt_ccp_call_control_client_bearers *bearers)
+{
+	if (err != 0) {
+		FAIL("Failed to discover TBS: %d\n", err);
+		return;
+	}
+
+	LOG_INF("Discovery completed with %s%u TBS bearers",
+		bearers->gtbs_bearer != NULL ? "GTBS and " : "", bearers->tbs_count);
+
+	if (IS_ENABLED(CONFIG_BT_TBS_CLIENT_TBS) && bearers->gtbs_bearer == NULL) {
+		FAIL("Failed to discover GTBS");
+		return;
+	}
+
+	SET_FLAG(flag_discovery_complete);
+}
+
+static void discover_tbs(void)
+{
+	int err;
+
+	UNSET_FLAG(flag_discovery_complete);
+
+	err = bt_ccp_call_control_client_discover(default_conn, &inst);
+	if (err) {
+		FAIL("Failed to discover TBS: %d", err);
+		return;
+	}
+
+	WAIT_FOR_FLAG(flag_discovery_complete);
+}
+
+static void init(void)
+{
+	static struct bt_ccp_call_control_client_cb ccp_call_control_client_cbs = {
+		.discover = ccp_call_control_client_discover_cb,
+	};
+	int err;
+
+	err = bt_enable(NULL);
+	if (err != 0) {
+		FAIL("Bluetooth discover failed (err %d)\n", err);
+		return;
+	}
+
+	err = bt_ccp_call_control_client_register_cb(&ccp_call_control_client_cbs);
+	if (err != 0) {
+		FAIL("Failed to register CCP Call Control Client cbs (err %d)\n", err);
+		return;
+	}
+}
+
+static void test_main(void)
+{
+	struct bt_le_ext_adv *ext_adv;
+	int err;
+
+	init();
+
+	setup_connectable_adv(&ext_adv);
+
+	printk("Advertising successfully started\n");
+
+	WAIT_FOR_FLAG(flag_connected);
+
+	discover_tbs();
+	discover_tbs(); /* test that we can discover twice */
+
+	err = bt_conn_disconnect(default_conn, BT_HCI_ERR_REMOTE_USER_TERM_CONN);
+	if (err != 0) {
+		FAIL("Failed to disconnect: %d\n", err);
+	}
+
+	WAIT_FOR_FLAG(flag_disconnected);
+
+	PASS("CCP Call Control Client Passed\n");
+}
+
+static const struct bst_test_instance test_ccp_call_control_client[] = {
+	{
+		.test_id = "ccp_call_control_client",
+		.test_pre_init_f = test_init,
+		.test_tick_f = test_tick,
+		.test_main_f = test_main,
+	},
+	BSTEST_END_MARKER,
+};
+
+struct bst_test_list *test_ccp_call_control_client_install(struct bst_test_list *tests)
+{
+	return bst_add_tests(tests, test_ccp_call_control_client);
+}
+
+#else
+struct bst_test_list *test_ccp_call_control_client_install(struct bst_test_list *tests)
+{
+	return tests;
+}
+
+#endif /* CONFIG_BT_CCP_CALL_CONTROL_CLIENT */
diff --git a/tests/bsim/bluetooth/audio/src/ccp_call_control_server_test.c b/tests/bsim/bluetooth/audio/src/ccp_call_control_server_test.c
index dfc6ef57953..ab8771f0927 100644
--- a/tests/bsim/bluetooth/audio/src/ccp_call_control_server_test.c
+++ b/tests/bsim/bluetooth/audio/src/ccp_call_control_server_test.c
@@ -118,6 +118,12 @@ static void init(void)
 
 		LOG_INF("Registered bearer[%d]", i);
 	}
+
+	err = bt_le_scan_start(BT_LE_SCAN_PASSIVE, NULL);
+	if (err != 0) {
+		FAIL("Scanning failed to start (err %d)\n", err);
+		return;
+	}
 }
 
 static void unregister_bearers(void)
@@ -143,6 +149,10 @@ static void test_main(void)
 {
 	init();
 
+	WAIT_FOR_FLAG(flag_connected);
+
+	WAIT_FOR_FLAG(flag_disconnected);
+
 	unregister_bearers();
 
 	PASS("CCP Call Control Server Passed\n");
diff --git a/tests/bsim/bluetooth/audio/src/common.c b/tests/bsim/bluetooth/audio/src/common.c
index c842b2b91e8..2c23a083624 100644
--- a/tests/bsim/bluetooth/audio/src/common.c
+++ b/tests/bsim/bluetooth/audio/src/common.c
@@ -357,10 +357,8 @@ static void setup_backchannels(void)
 	uint *channels;
 
 	for (int32_t i = 0; i < dev_cnt; i++) {
-		if (i != self) { /* skip ourselves*/
-			backchannel_nums[chan_cnt] = get_chan_num((uint16_t)i);
-			device_numbers[chan_cnt++] = i;
-		}
+		backchannel_nums[chan_cnt] = get_chan_num((uint16_t)i);
+		device_numbers[chan_cnt++] = i;
 	}
 
 	channels = bs_open_back_channel(self, device_numbers, backchannel_nums, chan_cnt);
diff --git a/tests/bsim/bluetooth/audio/src/common.h b/tests/bsim/bluetooth/audio/src/common.h
index 8584b7ea91a..6ba2106a6c9 100644
--- a/tests/bsim/bluetooth/audio/src/common.h
+++ b/tests/bsim/bluetooth/audio/src/common.h
@@ -161,6 +161,7 @@ struct audio_test_stream {
 
 	struct bt_iso_recv_info last_info;
 	size_t rx_cnt;
+	size_t valid_rx_cnt;
 };
 
 static inline struct bt_cap_stream *cap_stream_from_bap_stream(struct bt_bap_stream *bap_stream)
diff --git a/tests/bsim/bluetooth/audio/src/gmap_ugg_test.c b/tests/bsim/bluetooth/audio/src/gmap_ugg_test.c
index 0e048416a13..c1d60805871 100644
--- a/tests/bsim/bluetooth/audio/src/gmap_ugg_test.c
+++ b/tests/bsim/bluetooth/audio/src/gmap_ugg_test.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023-2024 Nordic Semiconductor ASA
+ * Copyright (c) 2023-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -36,6 +36,7 @@
 #include <zephyr/toolchain.h>
 
 #include "bap_stream_tx.h"
+#include "bap_stream_rx.h"
 #include "bstests.h"
 #include "common.h"
 #include "bap_common.h"
@@ -179,6 +180,14 @@ static void stream_enabled_cb(struct bt_bap_stream *stream)
 
 static void stream_started_cb(struct bt_bap_stream *stream)
 {
+	struct audio_test_stream *test_stream = audio_test_stream_from_bap_stream(stream);
+
+	memset(&test_stream->last_info, 0, sizeof(test_stream->last_info));
+	test_stream->rx_cnt = 0U;
+	test_stream->valid_rx_cnt = 0U;
+	test_stream->seq_num = 0U;
+	test_stream->tx_cnt = 0U;
+
 	printk("Started stream %p\n", stream);
 
 	if (bap_stream_tx_can_send(stream)) {
@@ -236,6 +245,7 @@ static struct bt_bap_stream_ops stream_ops = {
 	.stopped = stream_stopped_cb,
 	.released = stream_released_cb,
 	.sent = bap_stream_tx_sent_cb,
+	.recv = bap_stream_rx_recv_cb,
 };
 
 static void cap_discovery_complete_cb(struct bt_conn *conn, int err,
@@ -497,7 +507,8 @@ static void init(void)
 	}
 
 	for (size_t i = 0; i < ARRAY_SIZE(unicast_streams); i++) {
-		bt_cap_stream_ops_register(&unicast_streams[i].stream, &stream_ops);
+		bt_cap_stream_ops_register(
+			cap_stream_from_audio_test_stream(&unicast_streams[i].stream), &stream_ops);
 	}
 
 	for (size_t i = 0; i < ARRAY_SIZE(broadcast_streams); i++) {
@@ -621,11 +632,13 @@ static int gmap_unicast_ac_create_unicast_group(const struct gmap_unicast_ac_par
 	 */
 	for (size_t i = 0U; i < snk_cnt; i++) {
 		snk_group_stream_params[i].qos = &snk_uni_streams[i]->qos;
-		snk_group_stream_params[i].stream = &snk_uni_streams[i]->stream.bap_stream;
+		snk_group_stream_params[i].stream =
+			bap_stream_from_audio_test_stream(&snk_uni_streams[i]->stream);
 	}
 	for (size_t i = 0U; i < src_cnt; i++) {
 		src_group_stream_params[i].qos = &src_uni_streams[i]->qos;
-		src_group_stream_params[i].stream = &src_uni_streams[i]->stream.bap_stream;
+		src_group_stream_params[i].stream =
+			bap_stream_from_audio_test_stream(&src_uni_streams[i]->stream);
 	}
 
 	for (size_t i = 0U; i < param->conn_cnt; i++) {
@@ -719,12 +732,12 @@ static int gmap_ac_cap_unicast_start(const struct gmap_unicast_ac_param *param,
 	 * preset so that we can modify them (e.g. update the metadata)
 	 */
 	for (size_t i = 0U; i < snk_cnt; i++) {
-		snk_cap_streams[i] = &snk_uni_streams[i]->stream;
+		snk_cap_streams[i] = cap_stream_from_audio_test_stream(&snk_uni_streams[i]->stream);
 		snk_codec_cfgs[i] = &snk_uni_streams[i]->codec_cfg;
 	}
 
 	for (size_t i = 0U; i < src_cnt; i++) {
-		src_cap_streams[i] = &src_uni_streams[i]->stream;
+		src_cap_streams[i] = cap_stream_from_audio_test_stream(&src_uni_streams[i]->stream);
 		src_codec_cfgs[i] = &src_uni_streams[i]->codec_cfg;
 	}
 
@@ -881,6 +894,9 @@ static int gmap_ac_unicast(const struct gmap_unicast_ac_param *param,
 
 	WAIT_FOR_FLAG(flag_started);
 
+	/* let other devices know we have started what we wanted */
+	backchannel_sync_send_all();
+
 	return 0;
 }
 
@@ -922,6 +938,8 @@ static void unicast_group_delete(struct bt_bap_unicast_group *unicast_group)
 static void test_gmap_ugg_unicast_ac(const struct gmap_unicast_ac_param *param)
 {
 	struct bt_bap_unicast_group *unicast_group;
+	bool expect_tx = false;
+	bool expect_rx = false;
 
 	printk("Running test for %s with Sink Preset %s and Source Preset %s\n", param->name,
 	       param->snk_named_preset != NULL ? param->snk_named_preset->name : "None",
@@ -956,10 +974,12 @@ static void test_gmap_ugg_unicast_ac(const struct gmap_unicast_ac_param *param)
 
 		if (param->snk_cnt[i] > 0U) {
 			discover_sink(connected_conns[i]);
+			expect_tx = true;
 		}
 
 		if (param->src_cnt[i] > 0U) {
 			discover_source(connected_conns[i]);
+			expect_rx = true;
 		}
 
 		discover_gmas(connected_conns[i]);
@@ -968,6 +988,16 @@ static void test_gmap_ugg_unicast_ac(const struct gmap_unicast_ac_param *param)
 
 	gmap_ac_unicast(param, &unicast_group);
 
+	if (expect_tx) {
+		/* Wait until acceptors have received expected data */
+		backchannel_sync_wait_all();
+	}
+
+	if (expect_rx) {
+		printk("Waiting for data\n");
+		WAIT_FOR_FLAG(flag_audio_received);
+	}
+
 	unicast_audio_stop(unicast_group);
 
 	unicast_group_delete(unicast_group);
diff --git a/tests/bsim/bluetooth/audio/src/gmap_ugt_test.c b/tests/bsim/bluetooth/audio/src/gmap_ugt_test.c
index d8c259199ca..5507639cf3f 100644
--- a/tests/bsim/bluetooth/audio/src/gmap_ugt_test.c
+++ b/tests/bsim/bluetooth/audio/src/gmap_ugt_test.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023 Nordic Semiconductor ASA
+ * Copyright (c) 2023-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -26,6 +26,8 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/sys/util_macro.h>
 
+#include "bap_stream_rx.h"
+#include "bap_stream_tx.h"
 #include "bstests.h"
 #include "common.h"
 #include "bap_common.h"
@@ -35,6 +37,7 @@ extern enum bst_result_t bst_result;
 
 #define CONTEXT  (BT_AUDIO_CONTEXT_TYPE_UNSPECIFIED | BT_AUDIO_CONTEXT_TYPE_GAME)
 #define LOCATION (BT_AUDIO_LOCATION_FRONT_LEFT | BT_AUDIO_LOCATION_FRONT_RIGHT)
+#define GMAP_UGG_DEV_ID 0 /* GMAP UGG shall be ID 0 for these tests */
 
 static uint8_t csis_rank = 1;
 
@@ -47,8 +50,9 @@ static const struct bt_bap_qos_cfg_pref unicast_qos_pref =
 
 #define UNICAST_CHANNEL_COUNT_1 BIT(0)
 
-static struct bt_cap_stream
+static struct audio_test_stream
 	unicast_streams[CONFIG_BT_ASCS_MAX_ASE_SNK_COUNT + CONFIG_BT_ASCS_MAX_ASE_SRC_COUNT];
+static bool expect_rx;
 
 CREATE_FLAG(flag_unicast_stream_started);
 CREATE_FLAG(flag_gmap_discovered);
@@ -79,13 +83,52 @@ static void unicast_stream_enabled_cb(struct bt_bap_stream *stream)
 
 static void unicast_stream_started_cb(struct bt_bap_stream *stream)
 {
-	printk("Started: stream %p\n", stream);
+	struct audio_test_stream *test_stream = audio_test_stream_from_bap_stream(stream);
+
+	memset(&test_stream->last_info, 0, sizeof(test_stream->last_info));
+	test_stream->rx_cnt = 0U;
+	test_stream->valid_rx_cnt = 0U;
+	test_stream->seq_num = 0U;
+	test_stream->tx_cnt = 0U;
+
+	printk("Started stream %p\n", stream);
+
+	if (bap_stream_tx_can_send(stream)) {
+		int err;
+
+		err = bap_stream_tx_register(stream);
+		if (err != 0) {
+			FAIL("Failed to register stream %p for TX: %d\n", stream, err);
+			return;
+		}
+	} else if (bap_stream_rx_can_recv(stream)) {
+		expect_rx = true;
+	}
+
 	SET_FLAG(flag_unicast_stream_started);
 }
 
+static void unicast_stream_stopped(struct bt_bap_stream *stream, uint8_t reason)
+{
+	printk("Stopped stream %p with reason 0x%02X\n", stream, reason);
+
+	if (bap_stream_tx_can_send(stream)) {
+		int err;
+
+		err = bap_stream_tx_unregister(stream);
+		if (err != 0) {
+			FAIL("Failed to unregister stream %p for TX: %d\n", stream, err);
+			return;
+		}
+	}
+}
+
 static struct bt_bap_stream_ops unicast_stream_ops = {
 	.enabled = unicast_stream_enabled_cb,
 	.started = unicast_stream_started_cb,
+	.stopped = unicast_stream_stopped,
+	.sent = bap_stream_tx_sent_cb,
+	.recv = bap_stream_rx_recv_cb,
 };
 
 static struct bt_csip_set_member_svc_inst *csip_set_member;
@@ -93,7 +136,8 @@ static struct bt_csip_set_member_svc_inst *csip_set_member;
 static struct bt_bap_stream *unicast_stream_alloc(void)
 {
 	for (size_t i = 0; i < ARRAY_SIZE(unicast_streams); i++) {
-		struct bt_bap_stream *stream = &unicast_streams[i].bap_stream;
+		struct bt_bap_stream *stream =
+			bap_stream_from_audio_test_stream(&unicast_streams[i]);
 
 		if (!stream->conn) {
 			return stream;
@@ -349,6 +393,17 @@ static void discover_gmas(struct bt_conn *conn)
 	WAIT_FOR_FLAG(flag_gmap_discovered);
 }
 
+static void wait_for_data(void)
+{
+	if (expect_rx) {
+		printk("Waiting for data\n");
+		WAIT_FOR_FLAG(flag_audio_received);
+		printk("Data received\n");
+	}
+	/* let initiator know we have received what we wanted */
+	backchannel_sync_send(GMAP_UGG_DEV_ID);
+}
+
 static void test_main(void)
 {
 	/* TODO: Register all GMAP codec capabilities */
@@ -363,6 +418,20 @@ static void test_main(void)
 		.codec_cap = &codec_cap,
 	};
 	struct bt_le_ext_adv *ext_adv;
+	const struct bt_pacs_register_param pacs_param = {
+#if defined(CONFIG_BT_PAC_SNK)
+		.snk_pac = true,
+#endif /* CONFIG_BT_PAC_SNK */
+#if defined(CONFIG_BT_PAC_SNK_LOC)
+		.snk_loc = true,
+#endif /* CONFIG_BT_PAC_SNK_LOC */
+#if defined(CONFIG_BT_PAC_SRC)
+		.src_pac = true,
+#endif /* CONFIG_BT_PAC_SRC */
+#if defined(CONFIG_BT_PAC_SRC_LOC)
+		.src_loc = true,
+#endif /* CONFIG_BT_PAC_SRC_LOC */
+	};
 	int err;
 
 	err = bt_enable(NULL);
@@ -372,6 +441,13 @@ static void test_main(void)
 	}
 
 	printk("Bluetooth initialized\n");
+	bap_stream_tx_init();
+
+	err = bt_pacs_register(&pacs_param);
+	if (err) {
+		FAIL("Could not register PACS (err %d)\n", err);
+		return;
+	}
 
 	if (IS_ENABLED(CONFIG_BT_CAP_ACCEPTOR_SET_MEMBER)) {
 		const struct bt_csip_set_member_register_param csip_set_member_param = {
@@ -419,7 +495,8 @@ static void test_main(void)
 	}
 
 	for (size_t i = 0U; i < ARRAY_SIZE(unicast_streams); i++) {
-		bt_cap_stream_ops_register(&unicast_streams[i], &unicast_stream_ops);
+		bt_cap_stream_ops_register(cap_stream_from_audio_test_stream(&unicast_streams[i]),
+					   &unicast_stream_ops);
 	}
 
 	set_supported_contexts();
@@ -447,6 +524,11 @@ static void test_main(void)
 	discover_gmas(default_conn);
 	discover_gmas(default_conn); /* test that we can discover twice */
 
+	/* Wait until the UGG is done starting streams */
+	backchannel_sync_wait(GMAP_UGG_DEV_ID);
+
+	wait_for_data();
+
 	WAIT_FOR_FLAG(flag_disconnected);
 
 	PASS("GMAP UGT passed\n");
diff --git a/tests/bsim/bluetooth/audio/src/main.c b/tests/bsim/bluetooth/audio/src/main.c
index 7fc13176bae..3e8161fe7de 100644
--- a/tests/bsim/bluetooth/audio/src/main.c
+++ b/tests/bsim/bluetooth/audio/src/main.c
@@ -44,6 +44,7 @@ extern struct bst_test_list *test_csip_notify_client_install(struct bst_test_lis
 extern struct bst_test_list *test_csip_notify_server_install(struct bst_test_list *tests);
 extern struct bst_test_list *test_gmap_ugg_install(struct bst_test_list *tests);
 extern struct bst_test_list *test_gmap_ugt_install(struct bst_test_list *tests);
+extern struct bst_test_list *test_ccp_call_control_client_install(struct bst_test_list *tests);
 extern struct bst_test_list *test_ccp_call_control_server_install(struct bst_test_list *tests);
 
 bst_test_install_t test_installers[] = {
@@ -83,6 +84,7 @@ bst_test_install_t test_installers[] = {
 	test_csip_notify_server_install,
 	test_gmap_ugg_install,
 	test_gmap_ugt_install,
+	test_ccp_call_control_client_install,
 	test_ccp_call_control_server_install,
 	NULL,
 };
diff --git a/tests/bsim/bluetooth/audio/src/pacs_notify_server_test.c b/tests/bsim/bluetooth/audio/src/pacs_notify_server_test.c
index a9ebce0e73d..602ca4934a4 100644
--- a/tests/bsim/bluetooth/audio/src/pacs_notify_server_test.c
+++ b/tests/bsim/bluetooth/audio/src/pacs_notify_server_test.c
@@ -159,6 +159,12 @@ static void test_main(void)
 	int err;
 	enum bt_audio_context available, available_for_conn;
 	struct bt_le_ext_adv *ext_adv;
+	const struct bt_pacs_register_param pacs_param = {
+		.snk_pac = true,
+		.snk_loc = true,
+		.src_pac = true,
+		.src_loc = true,
+	};
 
 	LOG_DBG("Enabling Bluetooth");
 	err = bt_enable(NULL);
@@ -167,6 +173,12 @@ static void test_main(void)
 		return;
 	}
 
+	err = bt_pacs_register(&pacs_param);
+	if (err) {
+		FAIL("Could not register PACS (err %d)\n", err);
+		return;
+	}
+
 	bt_pacs_set_supported_contexts(BT_AUDIO_DIR_SINK, BT_AUDIO_CONTEXT_TYPE_ANY);
 	bt_pacs_set_supported_contexts(BT_AUDIO_DIR_SOURCE, BT_AUDIO_CONTEXT_TYPE_ANY);
 	bt_pacs_set_available_contexts(BT_AUDIO_DIR_SINK, BT_AUDIO_CONTEXT_TYPE_ANY);
diff --git a/tests/bsim/bluetooth/audio/src/pbp_public_broadcast_sink_test.c b/tests/bsim/bluetooth/audio/src/pbp_public_broadcast_sink_test.c
index 0df8ae7c609..c96e3fa8604 100644
--- a/tests/bsim/bluetooth/audio/src/pbp_public_broadcast_sink_test.c
+++ b/tests/bsim/bluetooth/audio/src/pbp_public_broadcast_sink_test.c
@@ -99,6 +99,7 @@ static void started_cb(struct bt_bap_stream *stream)
 
 	memset(&test_stream->last_info, 0, sizeof(test_stream->last_info));
 	test_stream->rx_cnt = 0U;
+	test_stream->valid_rx_cnt = 0U;
 
 	printk("Stream %p started\n", stream);
 }
@@ -197,6 +198,12 @@ static int reset(void)
 
 static int init(void)
 {
+	const struct bt_pacs_register_param pacs_param = {
+		.snk_pac = true,
+		.snk_loc = true,
+		.src_pac = true,
+		.src_loc = true,
+	};
 	int err;
 
 	err = bt_enable(NULL);
@@ -208,6 +215,12 @@ static int init(void)
 
 	printk("Bluetooth initialized\n");
 
+	err = bt_pacs_register(&pacs_param);
+	if (err) {
+		FAIL("Could not register PACS (err %d)\n", err);
+		return err;
+	}
+
 	bt_bap_broadcast_sink_register_cb(&broadcast_sink_cbs);
 	bt_le_per_adv_sync_cb_register(&broadcast_sync_cb);
 
diff --git a/tests/bsim/bluetooth/audio/src/pbp_public_broadcast_source_test.c b/tests/bsim/bluetooth/audio/src/pbp_public_broadcast_source_test.c
index 9bce5941be4..eb2e789f24a 100644
--- a/tests/bsim/bluetooth/audio/src/pbp_public_broadcast_source_test.c
+++ b/tests/bsim/bluetooth/audio/src/pbp_public_broadcast_source_test.c
@@ -17,6 +17,7 @@
 #include <zephyr/bluetooth/audio/pbp.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/byteorder.h>
+#include <zephyr/bluetooth/crypto.h>
 #include <zephyr/bluetooth/gap.h>
 #include <zephyr/bluetooth/iso.h>
 #include <zephyr/bluetooth/uuid.h>
diff --git a/tests/bsim/bluetooth/audio/src/tbs_test.c b/tests/bsim/bluetooth/audio/src/tbs_test.c
index ea96241db13..e56f27a50fe 100644
--- a/tests/bsim/bluetooth/audio/src/tbs_test.c
+++ b/tests/bsim/bluetooth/audio/src/tbs_test.c
@@ -194,7 +194,7 @@ static int test_answer_terminate(void)
 	printk("Answering call\n");
 	err = bt_tbs_remote_answer(g_call_index);
 	if (err != BT_TBS_RESULT_CODE_SUCCESS) {
-		FAIL("Could not accept call: %d\n", err);
+		FAIL("Could not remote answer: %d\n", err);
 		return err;
 	}
 
@@ -223,7 +223,7 @@ static int test_hold_retrieve(void)
 
 	err = bt_tbs_remote_answer(g_call_index);
 	if (err != BT_TBS_RESULT_CODE_SUCCESS) {
-		FAIL("Could not accept call: %d\n", err);
+		FAIL("Could not remote answer: %d\n", err);
 		return err;
 	}
 
diff --git a/tests/bsim/bluetooth/audio/src/tmap_client_test.c b/tests/bsim/bluetooth/audio/src/tmap_client_test.c
index 2aebbb0e0f1..572abc9f019 100644
--- a/tests/bsim/bluetooth/audio/src/tmap_client_test.c
+++ b/tests/bsim/bluetooth/audio/src/tmap_client_test.c
@@ -150,6 +150,7 @@ static void test_main(void)
 	/* Initialize TMAP */
 	err = bt_tmap_register(BT_TMAP_ROLE_CG | BT_TMAP_ROLE_UMS);
 	if (err != 0) {
+		FAIL("Failed to register TMAP (err %d)\n", err);
 		return;
 	}
 
diff --git a/tests/bsim/bluetooth/audio/src/tmap_server_test.c b/tests/bsim/bluetooth/audio/src/tmap_server_test.c
index 1be606ed61d..afb031ce167 100644
--- a/tests/bsim/bluetooth/audio/src/tmap_server_test.c
+++ b/tests/bsim/bluetooth/audio/src/tmap_server_test.c
@@ -40,6 +40,7 @@ static void test_main(void)
 	/* Initialize TMAP */
 	err = bt_tmap_register(TMAP_ROLE_SUPPORTED);
 	if (err != 0) {
+		FAIL("Failed to register TMAP (err %d)\n", err);
 		return;
 	}
 	printk("TMAP initialized. Start advertising...\n");
diff --git a/tests/bsim/bluetooth/audio/sysbuild.cmake b/tests/bsim/bluetooth/audio/sysbuild.cmake
index e5bd9d9e425..5dfd594349c 100644
--- a/tests/bsim/bluetooth/audio/sysbuild.cmake
+++ b/tests/bsim/bluetooth/audio/sysbuild.cmake
@@ -20,7 +20,6 @@ if(SB_CONFIG_NET_CORE_IMAGE_HCI_IPC)
 
 	set(${NET_APP}_EXTRA_CONF_FILE
 	 ${APP_DIR}/overlay-nrf5340_cpunet_iso-bt_ll_sw_split.conf
-	 ${NET_APP_SRC_DIR}/debug_overlay.conf
 	 CACHE INTERNAL ""
 	)
 
diff --git a/tests/bsim/bluetooth/audio/test_scripts/_cap.sh b/tests/bsim/bluetooth/audio/test_scripts/_cap.sh
index c4e3ddec197..9370a52d681 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/_cap.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/_cap.sh
@@ -1,6 +1,6 @@
 #!/usr/bin/env bash
 #
-# Copyright (c) 2022-2023 Nordic Semiconductor ASA
+# Copyright (c) 2022-2025 Nordic Semiconductor ASA
 #
 # SPDX-License-Identifier: Apache-2.0
 
@@ -8,28 +8,5 @@ dir_path=$(dirname "$0")
 
 set -e # Exit on error
 
-$dir_path/cap_unicast_inval.sh
-
-$dir_path/cap_unicast.sh
-
-$dir_path/cap_broadcast.sh
-$dir_path/cap_broadcast_ac_12.sh
-$dir_path/cap_broadcast_ac_13.sh
-$dir_path/cap_broadcast_ac_14.sh
-
-$dir_path/cap_unicast_ac_1.sh
-$dir_path/cap_unicast_ac_2.sh
-$dir_path/cap_unicast_ac_3.sh
-$dir_path/cap_unicast_ac_4.sh
-$dir_path/cap_unicast_ac_5.sh
-$dir_path/cap_unicast_ac_6_i.sh
-$dir_path/cap_unicast_ac_6_ii.sh
-$dir_path/cap_unicast_ac_7_i.sh
-$dir_path/cap_unicast_ac_7_ii.sh
-$dir_path/cap_unicast_ac_8_i.sh
-$dir_path/cap_unicast_ac_8_ii.sh
-$dir_path/cap_unicast_ac_9_i.sh
-$dir_path/cap_unicast_ac_9_ii.sh
-$dir_path/cap_unicast_ac_10.sh
-$dir_path/cap_unicast_ac_11_i.sh
-$dir_path/cap_unicast_ac_11_ii.sh
+$dir_path/_cap_broadcast.sh
+$dir_path/_cap_unicast.sh
diff --git a/tests/bsim/bluetooth/audio/test_scripts/_cap_broadcast.sh b/tests/bsim/bluetooth/audio/test_scripts/_cap_broadcast.sh
new file mode 100755
index 00000000000..f8478cdc511
--- /dev/null
+++ b/tests/bsim/bluetooth/audio/test_scripts/_cap_broadcast.sh
@@ -0,0 +1,17 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2025 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+
+dir_path=$(dirname "$0")
+
+set -e # Exit on error
+
+# Run all cap_broadcast* tests
+for file in "$dir_path"/cap_broadcast*.sh; do
+    if [ -f "$file" ]; then
+        echo "Running $file"
+        $file
+    fi
+done
diff --git a/tests/bsim/bluetooth/audio/test_scripts/_cap_unicast.sh b/tests/bsim/bluetooth/audio/test_scripts/_cap_unicast.sh
new file mode 100755
index 00000000000..1f1f63b37e8
--- /dev/null
+++ b/tests/bsim/bluetooth/audio/test_scripts/_cap_unicast.sh
@@ -0,0 +1,17 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2025 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+
+dir_path=$(dirname "$0")
+
+set -e # Exit on error
+
+# Run all cap_unicast* tests
+for file in "$dir_path"/cap_unicast*.sh; do
+    if [ -f "$file" ]; then
+        echo "Running $file"
+        $file
+    fi
+done
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_inval.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_inval.sh
new file mode 100755
index 00000000000..f177df9657a
--- /dev/null
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_inval.sh
@@ -0,0 +1,25 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2025 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+
+SIMULATION_ID="cap_broadcast_inval"
+VERBOSITY_LEVEL=2
+EXECUTE_TIMEOUT=120
+
+source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
+
+cd ${BSIM_OUT_PATH}/bin
+
+printf "\n\n======== Running CAP broadcast inval test =========\n\n"
+
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \
+  -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_broadcast_inval \
+  -RealEncryption=1 -rs=46 -D=1
+
+# Simulation time should be larger than the WAIT_TIME in common.h
+Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
+  -D=1 -sim_length=60e6 $@
+
+wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_reception.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_reception.sh
index 0ce66627161..b909cf4ce4c 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_reception.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_reception.sh
@@ -1,6 +1,6 @@
 #!/usr/bin/env bash
 #
-# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2024-2025 Nordic Semiconductor ASA
 #
 # SPDX-License-Identifier: Apache-2.0
 
@@ -25,7 +25,7 @@ Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \
 
 Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \
   -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=2 -testid=cap_acceptor_broadcast_reception \
-  -RealEncryption=1 -rs=69 -D=${NR_OF_DEVICES}
+  -RealEncryption=1 -rs=69 -D=${NR_OF_DEVICES} -start_offset=7e3
 
 # Simulation time should be larger than the WAIT_TIME in common.h
 Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_update.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_update.sh
new file mode 100755
index 00000000000..a7900beaff6
--- /dev/null
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_broadcast_update.sh
@@ -0,0 +1,29 @@
+#!/usr/bin/env bash
+#
+# Copyright (c) 2025 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+
+SIMULATION_ID="cap_broadcast_update"
+VERBOSITY_LEVEL=2
+EXECUTE_TIMEOUT=120
+
+source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
+
+cd ${BSIM_OUT_PATH}/bin
+
+printf "\n\n======== Running CAP broadcast update test =========\n\n"
+
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \
+  -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_broadcast_update \
+  -RealEncryption=1 -rs=46 -D=2
+
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \
+  -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=cap_acceptor_broadcast_update \
+  -RealEncryption=1 -rs=23 -D=2
+
+# Simulation time should be larger than the WAIT_TIME in common.h
+Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
+  -D=2 -sim_length=60e6 $@
+
+wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_1.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_1.sh
index e09ac9e5d3a..bb2740e989f 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_1.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_1.sh
@@ -40,8 +40,12 @@ Execute_AC_1 24_1_1
 Execute_AC_1 24_2_1
 Execute_AC_1 32_1_1
 Execute_AC_1 32_2_1
-Execute_AC_1 441_1_1
-Execute_AC_1 441_2_1
+# bap_stream_rx.c:66): ISO receive lost
+# https://github.com/zephyrproject-rtos/zephyr/issues/84303
+# Execute_AC_1 441_1_1
+# bap_stream_rx.c:66): ISO receive lost
+# https://github.com/zephyrproject-rtos/zephyr/issues/84303
+# Execute_AC_1 441_2_1
 Execute_AC_1 48_1_1
 Execute_AC_1 48_2_1
 Execute_AC_1 48_3_1
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_10.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_10.sh
index 7a50f10cca5..23ca3df3e2d 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_10.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_10.sh
@@ -40,8 +40,12 @@ Execute_AC_10 24_1_1
 Execute_AC_10 24_2_1
 Execute_AC_10 32_1_1
 Execute_AC_10 32_2_1
-Execute_AC_10 441_1_1
-Execute_AC_10 441_2_1
+# bap_stream_rx.c:66): ISO receive lost
+# https://github.com/zephyrproject-rtos/zephyr/issues/84303
+# Execute_AC_10 441_1_1
+# bap_stream_rx.c:66): ISO receive lost
+# https://github.com/zephyrproject-rtos/zephyr/issues/84303
+# Execute_AC_10 441_2_1
 Execute_AC_10 48_1_1
 Execute_AC_10 48_2_1
 Execute_AC_10 48_3_1
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_11_i.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_11_i.sh
index e74192f47ec..05062f85d71 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_11_i.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_11_i.sh
@@ -40,8 +40,14 @@ Execute_AC_11_I 24_1_1 24_1_1
 Execute_AC_11_I 24_2_1 24_2_1
 Execute_AC_11_I 32_1_1 32_1_1
 Execute_AC_11_I 32_2_1 32_2_1
-# Execute_AC_11_I 441_1_1 441_1_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
-# Execute_AC_11_I 441_2_1 441_2_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_11_I 441_1_1 441_1_1
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_11_I 441_2_1 441_2_1
 Execute_AC_11_I 48_1_1 48_1_1
 Execute_AC_11_I 48_2_1 48_2_1
 Execute_AC_11_I 48_3_1 48_3_1
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_11_ii.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_11_ii.sh
index 2280172b4ae..a868878fd5a 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_11_ii.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_11_ii.sh
@@ -44,8 +44,14 @@ Execute_AC_11_II 24_1_1 24_1_1
 Execute_AC_11_II 24_2_1 24_2_1
 Execute_AC_11_II 32_1_1 32_1_1
 Execute_AC_11_II 32_2_1 32_2_1
-# Execute_AC_11_II 441_1_1 441_1_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
-# Execute_AC_11_II 441_2_1 441_2_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_11_II 441_1_1 441_1_1
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_11_II 441_2_1 441_2_1
 Execute_AC_11_II 48_1_1 48_1_1
 Execute_AC_11_II 48_2_1 48_2_1
 Execute_AC_11_II 48_3_1 48_3_1
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_2.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_2.sh
index 0987accc4b2..649f971b659 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_2.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_2.sh
@@ -41,8 +41,12 @@ Execute_AC_2 24_1_1
 Execute_AC_2 24_2_1
 Execute_AC_2 32_1_1
 Execute_AC_2 32_2_1
-Execute_AC_2 441_1_1
-Execute_AC_2 441_2_1
+# bap_stream_rx.c:66): ISO receive lost
+# https://github.com/zephyrproject-rtos/zephyr/issues/84303
+# Execute_AC_2 441_1_1
+# bap_stream_rx.c:66): ISO receive lost
+# https://github.com/zephyrproject-rtos/zephyr/issues/84303
+# Execute_AC_2 441_2_1
 Execute_AC_2 48_1_1
 Execute_AC_2 48_2_1
 Execute_AC_2 48_3_1
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_3.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_3.sh
index 79e8a39d186..cd495debf3e 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_3.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_3.sh
@@ -41,9 +41,16 @@ Execute_AC_3 24_1_1 24_1_1
 Execute_AC_3 24_2_1 24_2_1
 Execute_AC_3 32_1_1 32_1_1
 Execute_AC_3 32_2_1 32_2_1
-Execute_AC_3 441_1_1 441_1_1
-Execute_AC_3 441_2_1 441_2_1
-Execute_AC_3 48_1_1 48_1_1
+# No sent callback on peripheral and no RX on peripheral
+# https://github.com/zephyrproject-rtos/zephyr/issues/83585
+# Execute_AC_3 441_1_1 441_1_1
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_3 441_2_1 441_2_1
+# No sent callback on peripheral and no RX on peripheral
+# https://github.com/zephyrproject-rtos/zephyr/issues/83585
+# Execute_AC_3 48_1_1 48_1_1
 Execute_AC_3 48_2_1 48_2_1
 Execute_AC_3 48_3_1 48_3_1
 Execute_AC_3 48_4_1 48_4_1
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_4.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_4.sh
index b24a16f39a2..ecbadc6b818 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_4.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_4.sh
@@ -38,8 +38,14 @@ Execute_AC_4 24_1_1
 Execute_AC_4 24_2_1
 Execute_AC_4 32_1_1
 Execute_AC_4 32_2_1
-Execute_AC_4 441_1_1
-Execute_AC_4 441_2_1
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_4 441_1_1
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_4 441_2_1
 Execute_AC_4 48_1_1
 Execute_AC_4 48_2_1
 Execute_AC_4 48_3_1
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_5.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_5.sh
index d42716febf8..e3fda276abc 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_5.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_5.sh
@@ -39,8 +39,13 @@ Execute_AC_5 24_1_1 24_1_1
 Execute_AC_5 24_2_1 24_2_1
 Execute_AC_5 32_1_1 32_1_1
 Execute_AC_5 32_2_1 32_2_1
-# Execute_AC_5 441_1_1 441_1_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
-# Execute_AC_5 441_2_1 441_2_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_5 441_1_1 441_1_1
+# bap_stream_rx.c:66): ISO receive lost
+# https://github.com/zephyrproject-rtos/zephyr/issues/84303
+# Execute_AC_5 441_2_1 441_2_1
 Execute_AC_5 48_1_1 48_1_1
 Execute_AC_5 48_2_1 48_2_1
 Execute_AC_5 48_3_1 48_3_1
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_6_i.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_6_i.sh
index 344ebb0448b..84f3e6fccf6 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_6_i.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_6_i.sh
@@ -38,8 +38,13 @@ Execute_AC_6_I 24_1_1
 Execute_AC_6_I 24_2_1
 Execute_AC_6_I 32_1_1
 Execute_AC_6_I 32_2_1
-# Execute_AC_6_I 441_1_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
-# Execute_AC_6_I 441_2_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
+# bap_stream_rx.c:66): ISO receive lost
+# https://github.com/zephyrproject-rtos/zephyr/issues/84303
+# Execute_AC_6_I 441_1_1
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_6_I 441_2_1
 Execute_AC_6_I 48_1_1
 Execute_AC_6_I 48_2_1
 Execute_AC_6_I 48_3_1
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_6_ii.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_6_ii.sh
index e04df696908..ce2a3be1149 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_6_ii.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_6_ii.sh
@@ -44,8 +44,14 @@ Execute_AC_6_II 24_1_1
 Execute_AC_6_II 24_2_1
 Execute_AC_6_II 32_1_1
 Execute_AC_6_II 32_2_1
-# Execute_AC_6_II 441_1_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
-# Execute_AC_6_II 441_2_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_6_II 441_1_1
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_6_II 441_2_1
 Execute_AC_6_II 48_1_1
 Execute_AC_6_II 48_2_1
 Execute_AC_6_II 48_3_1
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_7_i.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_7_i.sh
index 3eebbc3421f..55ba49c8520 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_7_i.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_7_i.sh
@@ -40,9 +40,16 @@ Execute_AC_7_I 24_1_1 24_1_1
 Execute_AC_7_I 24_2_1 24_2_1
 Execute_AC_7_I 32_1_1 32_1_1
 Execute_AC_7_I 32_2_1 32_2_1
-Execute_AC_7_I 441_1_1 441_1_1
-Execute_AC_7_I 441_2_1 441_2_1
-Execute_AC_7_I 48_1_1 48_1_1
+# No sent callback on peripheral and no RX on peripheral
+# https://github.com/zephyrproject-rtos/zephyr/issues/83585
+# Execute_AC_7_I 441_1_1 441_1_1
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_7_I 441_2_1 441_2_1
+# No sent callback on peripheral and no RX on peripheral
+# https://github.com/zephyrproject-rtos/zephyr/issues/83585
+# Execute_AC_7_I 48_1_1 48_1_1
 Execute_AC_7_I 48_2_1 48_2_1
 Execute_AC_7_I 48_3_1 48_3_1
 Execute_AC_7_I 48_4_1 48_4_1
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_7_ii.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_7_ii.sh
index ce6c9abdf89..62a80504795 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_7_ii.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_7_ii.sh
@@ -44,8 +44,14 @@ Execute_AC_7_II 24_1_1 24_1_1
 Execute_AC_7_II 24_2_1 24_2_1
 Execute_AC_7_II 32_1_1 32_1_1
 Execute_AC_7_II 32_2_1 32_2_1
-# Execute_AC_7_II 441_1_1 441_1_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
-# Execute_AC_7_II 441_2_1 441_2_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_7_II 441_1_1 441_1_1
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_7_II 441_2_1 441_2_1
 Execute_AC_7_II 48_1_1 48_1_1
 Execute_AC_7_II 48_2_1 48_2_1
 Execute_AC_7_II 48_3_1 48_3_1
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_8_i.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_8_i.sh
index 7b1e7d68481..453da880bf5 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_8_i.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_8_i.sh
@@ -40,8 +40,14 @@ Execute_AC_8_I 24_1_1 24_1_1
 Execute_AC_8_I 24_2_1 24_2_1
 Execute_AC_8_I 32_1_1 32_1_1
 Execute_AC_8_I 32_2_1 32_2_1
-# Execute_AC_8_I 441_1_1 441_1_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
-# Execute_AC_8_I 441_2_1 441_2_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_8_I 441_1_1 441_1_1
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_8_I 441_2_1 441_2_1
 Execute_AC_8_I 48_1_1 48_1_1
 Execute_AC_8_I 48_2_1 48_2_1
 Execute_AC_8_I 48_3_1 48_3_1
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_8_ii.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_8_ii.sh
index 25e07a6c149..af4b218f63e 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_8_ii.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_8_ii.sh
@@ -44,8 +44,14 @@ Execute_AC_8_II 24_1_1 24_1_1
 Execute_AC_8_II 24_2_1 24_2_1
 Execute_AC_8_II 32_1_1 32_1_1
 Execute_AC_8_II 32_2_1 32_2_1
-# Execute_AC_8_II 441_1_1 441_1_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
-# Execute_AC_8_II 441_2_1 441_2_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_8_II 441_1_1 441_1_1
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_8_II 441_2_1 441_2_1
 Execute_AC_8_II 48_1_1 48_1_1
 Execute_AC_8_II 48_2_1 48_2_1
 Execute_AC_8_II 48_3_1 48_3_1
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_9_i.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_9_i.sh
index 1a00f55e433..1756ac5a23a 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_9_i.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_9_i.sh
@@ -40,8 +40,14 @@ Execute_AC_9_I 24_1_1
 Execute_AC_9_I 24_2_1
 Execute_AC_9_I 32_1_1
 Execute_AC_9_I 32_2_1
-# Execute_AC_9_I 441_1_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
-# Execute_AC_9_I 441_2_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_9_I 441_1_1
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_9_I 441_2_1
 Execute_AC_9_I 48_1_1
 Execute_AC_9_I 48_2_1
 Execute_AC_9_I 48_3_1
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_9_ii.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_9_ii.sh
index 207d81f663e..717c5c50e5c 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_9_ii.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_ac_9_ii.sh
@@ -44,8 +44,14 @@ Execute_AC_9_II 24_1_1
 Execute_AC_9_II 24_2_1
 Execute_AC_9_II 32_1_1
 Execute_AC_9_II 32_2_1
-# Execute_AC_9_II 441_1_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
-# Execute_AC_9_II 441_2_1 # ASSERTION FAIL [iso_interval_us >= cig->c_sdu_interval]
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_9_II 441_1_1
+# ASSERTION FAIL [err == ((isoal_status_t) 0x00)] @
+# zephyr/subsys/bluetooth/controller/hci/hci_driver.c:489
+# https://github.com/zephyrproject-rtos/zephyr/issues/83586
+# Execute_AC_9_II 441_2_1
 Execute_AC_9_II 48_1_1
 Execute_AC_9_II 48_2_1
 Execute_AC_9_II 48_3_1
diff --git a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_inval.sh b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_inval.sh
index e45fb8a27a8..5f912c47de5 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_inval.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/cap_unicast_inval.sh
@@ -12,7 +12,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
 
 cd ${BSIM_OUT_PATH}/bin
 
-printf "\n\n======== Running CAP unicast test =========\n\n"
+printf "\n\n======== Running CAP unicast inval test =========\n\n"
 
 Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \
   -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=cap_initiator_unicast_inval \
diff --git a/tests/bsim/bluetooth/audio/test_scripts/ccp.sh b/tests/bsim/bluetooth/audio/test_scripts/ccp.sh
index ed5d1021e4a..cbfc3406ee8 100755
--- a/tests/bsim/bluetooth/audio/test_scripts/ccp.sh
+++ b/tests/bsim/bluetooth/audio/test_scripts/ccp.sh
@@ -13,10 +13,14 @@ cd ${BSIM_OUT_PATH}/bin
 SIMULATION_ID="ccp"
 
 Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \
-  -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=ccp_call_control_server -rs=10 -D=1
+  -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=0 -testid=ccp_call_control_server \
+  -RealEncryption=1 -rs=10 -D=2
+
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_prj_conf \
+  -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -d=1 -testid=ccp_call_control_client \
+  -RealEncryption=1 -rs=20 -D=2
 
 # Simulation time should be larger than the WAIT_TIME in common.h
-Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} \
-  -D=1 -sim_length=60e6 $@
+Execute ./bs_2G4_phy_v1 -v=${VERBOSITY_LEVEL} -s=${SIMULATION_ID} -D=2 -sim_length=60e6 $@
 
 wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/CMakeLists.txt b/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/CMakeLists.txt
index c30094a9c83..f7ab4892ae6 100644
--- a/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/CMakeLists.txt
+++ b/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/CMakeLists.txt
@@ -9,8 +9,12 @@ set(bap_broadcast_sink_path ${ZEPHYR_BASE}/samples/bluetooth/bap_broadcast_sink)
 
 target_sources(app PRIVATE
   ${bap_broadcast_sink_path}/src/main.c
+  ${bap_broadcast_sink_path}/src/stream_rx.c
 )
 
+zephyr_sources_ifdef(CONFIG_LIBLC3 ${bap_broadcast_sink_path}/src/lc3.c)
+zephyr_sources_ifdef(CONFIG_USB_DEVICE_AUDIO ${bap_broadcast_sink_path}/src/usb.c)
+
 target_sources(app PRIVATE
 	src/broadcast_sink_test.c
 	src/test_main.c
diff --git a/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/compile.sh b/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/compile.sh
index 8ed8895934a..f4cf7e1c438 100755
--- a/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/compile.sh
+++ b/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/compile.sh
@@ -10,13 +10,20 @@ set -ue
 source ${ZEPHYR_BASE}/tests/bsim/compile.source
 
 if [ "${BOARD_TS}" == "nrf5340bsim_nrf5340_cpuapp" ]; then
-  app=samples/bluetooth/bap_broadcast_source sysbuild=1 compile
+  app=samples/bluetooth/bap_broadcast_source conf_overlay=overlay-sequential.conf \
+    sysbuild=1 compile
+  app=samples/bluetooth/bap_broadcast_source conf_overlay=overlay-interleaved.conf \
+    sysbuild=1 compile
   app=tests/bsim/bluetooth/audio_samples/bap_broadcast_sink sysbuild=1 \
     conf_file=${ZEPHYR_BASE}/samples/bluetooth/bap_broadcast_sink/prj.conf \
     exe_name=bs_${BOARD_TS}_${app}_prj_conf sysbuild=1 compile
 else
-  app=samples/bluetooth/bap_broadcast_source conf_overlay=overlay-bt_ll_sw_split.conf \
-    exe_name=bs_${BOARD_TS}_${app}_prj_conf sysbuild=1 compile
+  app=samples/bluetooth/bap_broadcast_source \
+    conf_overlay='overlay-bt_ll_sw_split.conf;overlay-sequential.conf' \
+    exe_name=bs_${BOARD_TS}_${app}_prj_conf_overlay-sequential_conf sysbuild=1 compile
+  app=samples/bluetooth/bap_broadcast_source \
+    conf_overlay='overlay-bt_ll_sw_split.conf;overlay-interleaved.conf' \
+    exe_name=bs_${BOARD_TS}_${app}_prj_conf_overlay-interleaved_conf sysbuild=1 compile
   app=tests/bsim/bluetooth/audio_samples/bap_broadcast_sink \
     conf_file=${ZEPHYR_BASE}/samples/bluetooth/bap_broadcast_sink/prj.conf \
     conf_overlay=${ZEPHYR_BASE}/samples/bluetooth/bap_broadcast_sink/overlay-bt_ll_sw_split.conf \
diff --git a/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/src/broadcast_sink_test.c b/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/src/broadcast_sink_test.c
index 27be2325c5c..a4fbb93acf9 100644
--- a/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/src/broadcast_sink_test.c
+++ b/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/src/broadcast_sink_test.c
@@ -4,11 +4,12 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <inttypes.h>
+#include <stdint.h>
 
 #include "bs_types.h"
 #include "bs_tracing.h"
 #include "bs_utils.h"
-#include "time_machine.h"
 #include "bstests.h"
 
 #define WAIT_TIME 120 /* Seconds */
diff --git a/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/src/test_main.c b/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/src/test_main.c
index cd9df72aaae..75e83292c23 100644
--- a/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/src/test_main.c
+++ b/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/src/test_main.c
@@ -3,6 +3,7 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stddef.h>
 
 #include "bstests.h"
 
diff --git a/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/tests_scripts/broadcast_audio.sh b/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/tests_scripts/broadcast_audio.sh
deleted file mode 100755
index bb7230ca53e..00000000000
--- a/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/tests_scripts/broadcast_audio.sh
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env bash
-# Copyright 2023 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-# Simple selfchecking test for the broadcast audio sink/source samples,
-# It relies on the bs_tests hooks to register a test timer callback, which after a deadline
-# will check how many audio packets the broadcast audio sink has received, and if over a threshold
-# it considers the test passed
-
-simulation_id="broadcast_audio_samples_test"
-verbosity_level=2
-
-source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
-
-EXECUTE_TIMEOUT=200
-
-cd ${BSIM_OUT_PATH}/bin
-
-Execute ./bs_${BOARD_TS}_samples_bluetooth_bap_broadcast_source_prj_conf \
-  -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=1
-
-Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_samples_bap_broadcast_sink_prj_conf \
-  -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=1 \
-  -testid=bap_broadcast_sink
-
-Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \
-  -D=2 -sim_length=120e6 $@
-
-wait_for_background_jobs #Wait for all programs in background and return != 0 if any fails
diff --git a/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/tests_scripts/broadcast_audio_interleaved.sh b/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/tests_scripts/broadcast_audio_interleaved.sh
new file mode 100755
index 00000000000..ef2589321e7
--- /dev/null
+++ b/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/tests_scripts/broadcast_audio_interleaved.sh
@@ -0,0 +1,28 @@
+#!/usr/bin/env bash
+# Copyright 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Simple selfchecking test for the broadcast audio sink/source samples,
+# It relies on the bs_tests hooks to register a test timer callback, which after a deadline
+# will check how many audio packets the broadcast audio sink has received, and if over a threshold
+# it considers the test passed
+
+simulation_id="samples_bluetooth_bap_broadcast_source_interleaved_test"
+verbosity_level=2
+EXECUTE_TIMEOUT=200
+
+source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
+
+cd ${BSIM_OUT_PATH}/bin
+
+Execute ./bs_${BOARD_TS}_samples_bluetooth_bap_broadcast_source_prj_conf_overlay-interleaved_conf \
+  -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=1
+
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_samples_bap_broadcast_sink_prj_conf \
+  -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=1 \
+  -testid=bap_broadcast_sink
+
+Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \
+  -D=2 -sim_length=120e6 $@
+
+wait_for_background_jobs #Wait for all programs in background and return != 0 if any fails
diff --git a/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/tests_scripts/broadcast_audio_sequential.sh b/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/tests_scripts/broadcast_audio_sequential.sh
new file mode 100755
index 00000000000..91b0889817f
--- /dev/null
+++ b/tests/bsim/bluetooth/audio_samples/bap_broadcast_sink/tests_scripts/broadcast_audio_sequential.sh
@@ -0,0 +1,28 @@
+#!/usr/bin/env bash
+# Copyright 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Simple selfchecking test for the broadcast audio sink/source samples,
+# It relies on the bs_tests hooks to register a test timer callback, which after a deadline
+# will check how many audio packets the broadcast audio sink has received, and if over a threshold
+# it considers the test passed
+
+simulation_id="samples_bluetooth_bap_broadcast_source_sequential_test"
+verbosity_level=2
+EXECUTE_TIMEOUT=200
+
+source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
+
+cd ${BSIM_OUT_PATH}/bin
+
+Execute ./bs_${BOARD_TS}_samples_bluetooth_bap_broadcast_source_prj_conf_overlay-sequential_conf \
+  -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=1
+
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_samples_bap_broadcast_sink_prj_conf \
+  -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=1 \
+  -testid=bap_broadcast_sink
+
+Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \
+  -D=2 -sim_length=120e6 $@
+
+wait_for_background_jobs #Wait for all programs in background and return != 0 if any fails
diff --git a/tests/bsim/bluetooth/audio_samples/bap_unicast_client/boards/nrf54l15bsim_nrf54l15_cpuapp.conf b/tests/bsim/bluetooth/audio_samples/bap_unicast_client/boards/nrf54l15bsim_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..e8c8629ce62
--- /dev/null
+++ b/tests/bsim/bluetooth/audio_samples/bap_unicast_client/boards/nrf54l15bsim_nrf54l15_cpuapp.conf
@@ -0,0 +1,5 @@
+# This file content is just a copy of the equivalent one in the unicast client sample
+
+# For LC3 the following configs are needed
+CONFIG_FPU=y
+CONFIG_LIBLC3=y
diff --git a/tests/bsim/bluetooth/audio_samples/bap_unicast_client/prj.conf b/tests/bsim/bluetooth/audio_samples/bap_unicast_client/prj.conf
index 430d4276b02..50b4b8aae75 100644
--- a/tests/bsim/bluetooth/audio_samples/bap_unicast_client/prj.conf
+++ b/tests/bsim/bluetooth/audio_samples/bap_unicast_client/prj.conf
@@ -1,2 +1,2 @@
 # Please build using the sample configuration file:
-# ${ZEPHYR_BASE}/samples/bluetooth/uncast_audio_client/prj.conf
+# ${ZEPHYR_BASE}/samples/bluetooth/unicast_audio_client/prj.conf
diff --git a/tests/bsim/bluetooth/audio_samples/bap_unicast_client/src/test_main.c b/tests/bsim/bluetooth/audio_samples/bap_unicast_client/src/test_main.c
index dbba2106b19..e153ec7b7a3 100644
--- a/tests/bsim/bluetooth/audio_samples/bap_unicast_client/src/test_main.c
+++ b/tests/bsim/bluetooth/audio_samples/bap_unicast_client/src/test_main.c
@@ -3,6 +3,7 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stddef.h>
 
 #include "bstests.h"
 
diff --git a/tests/bsim/bluetooth/audio_samples/bap_unicast_client/src/unicast_client_sample_test.c b/tests/bsim/bluetooth/audio_samples/bap_unicast_client/src/unicast_client_sample_test.c
index 50aaece72fe..ef743e9b9f9 100644
--- a/tests/bsim/bluetooth/audio_samples/bap_unicast_client/src/unicast_client_sample_test.c
+++ b/tests/bsim/bluetooth/audio_samples/bap_unicast_client/src/unicast_client_sample_test.c
@@ -4,11 +4,12 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <inttypes.h>
+#include <stdint.h>
 
 #include "bs_types.h"
 #include "bs_tracing.h"
 #include "bs_utils.h"
-#include "time_machine.h"
 #include "bstests.h"
 
 #define WAIT_TIME 20 /* Seconds */
diff --git a/tests/bsim/bluetooth/audio_samples/cap/acceptor/src/cap_acceptor_sample_test.c b/tests/bsim/bluetooth/audio_samples/cap/acceptor/src/cap_acceptor_sample_test.c
index ffd76c91822..8f1c4c4ac13 100644
--- a/tests/bsim/bluetooth/audio_samples/cap/acceptor/src/cap_acceptor_sample_test.c
+++ b/tests/bsim/bluetooth/audio_samples/cap/acceptor/src/cap_acceptor_sample_test.c
@@ -4,13 +4,14 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <inttypes.h>
+#include <stdint.h>
 
 #include <zephyr/sys/util_macro.h>
 
 #include "bs_types.h"
 #include "bs_tracing.h"
 #include "bs_utils.h"
-#include "time_machine.h"
 #include "bstests.h"
 
 #define WAIT_TIME 10 /* Seconds */
diff --git a/tests/bsim/bluetooth/audio_samples/cap/acceptor/src/test_main.c b/tests/bsim/bluetooth/audio_samples/cap/acceptor/src/test_main.c
index fa6a7c977ce..d94a9ec8e91 100644
--- a/tests/bsim/bluetooth/audio_samples/cap/acceptor/src/test_main.c
+++ b/tests/bsim/bluetooth/audio_samples/cap/acceptor/src/test_main.c
@@ -3,6 +3,7 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stddef.h>
 
 #include "bstests.h"
 
diff --git a/tests/bsim/bluetooth/audio_samples/cap/initiator/src/cap_initiator_sample_test.c b/tests/bsim/bluetooth/audio_samples/cap/initiator/src/cap_initiator_sample_test.c
index 640d2cc012e..1f4fd6f3726 100644
--- a/tests/bsim/bluetooth/audio_samples/cap/initiator/src/cap_initiator_sample_test.c
+++ b/tests/bsim/bluetooth/audio_samples/cap/initiator/src/cap_initiator_sample_test.c
@@ -4,13 +4,14 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <inttypes.h>
+#include <stdint.h>
 
 #include <zephyr/sys/util_macro.h>
 
 #include "bs_types.h"
 #include "bs_tracing.h"
 #include "bs_utils.h"
-#include "time_machine.h"
 #include "bstests.h"
 
 #define WAIT_TIME 10 /* Seconds */
diff --git a/tests/bsim/bluetooth/audio_samples/cap/initiator/src/test_main.c b/tests/bsim/bluetooth/audio_samples/cap/initiator/src/test_main.c
index 3aa6fac9b02..6fe90791fad 100644
--- a/tests/bsim/bluetooth/audio_samples/cap/initiator/src/test_main.c
+++ b/tests/bsim/bluetooth/audio_samples/cap/initiator/src/test_main.c
@@ -3,6 +3,7 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+#include <stddef.h>
 
 #include "bstests.h"
 
diff --git a/tests/bsim/bluetooth/audio_samples/ccp/call_control_client/CMakeLists.txt b/tests/bsim/bluetooth/audio_samples/ccp/call_control_client/CMakeLists.txt
new file mode 100644
index 00000000000..da0ca3feddb
--- /dev/null
+++ b/tests/bsim/bluetooth/audio_samples/ccp/call_control_client/CMakeLists.txt
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(ccp_call_control_client_self_tets)
+
+set(ccp_call_control_client_path ${ZEPHYR_BASE}/samples/bluetooth/ccp_call_control_client)
+
+target_sources(app PRIVATE
+  ${ccp_call_control_client_path}/src/main.c
+)
+
+target_sources(app PRIVATE
+	src/test_main.c
+)
+
+zephyr_library_include_directories(${ZEPHYR_BASE}/samples/bluetooth)
+
+zephyr_include_directories(
+  ${BSIM_COMPONENTS_PATH}/libUtilv1/src/
+  ${BSIM_COMPONENTS_PATH}/libPhyComv1/src/
+  )
diff --git a/tests/bsim/bluetooth/audio_samples/ccp/call_control_client/Kconfig.sysbuild b/tests/bsim/bluetooth/audio_samples/ccp/call_control_client/Kconfig.sysbuild
new file mode 100644
index 00000000000..2fdcdcf687c
--- /dev/null
+++ b/tests/bsim/bluetooth/audio_samples/ccp/call_control_client/Kconfig.sysbuild
@@ -0,0 +1,10 @@
+# Copyright (c) 2023-2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+source "${ZEPHYR_BASE}/samples/bluetooth/ccp_call_control_client/Kconfig.sysbuild"
+
+config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX
+	int
+	# Let's pass the test arguments to the application MCU test
+	# otherwise by default they would have gone to the net core.
+	default 0 if $(BOARD_TARGET_STRING) = "NRF5340BSIM_NRF5340_CPUAPP"
diff --git a/tests/bsim/bluetooth/audio_samples/ccp/call_control_client/prj.conf b/tests/bsim/bluetooth/audio_samples/ccp/call_control_client/prj.conf
new file mode 100644
index 00000000000..b89931736c1
--- /dev/null
+++ b/tests/bsim/bluetooth/audio_samples/ccp/call_control_client/prj.conf
@@ -0,0 +1,2 @@
+# Please build using the sample configuration file:
+# ${ZEPHYR_BASE}/samples/bluetooth/ccp_call_control_client/prj.conf
diff --git a/tests/bsim/bluetooth/audio_samples/ccp/call_control_client/src/test_main.c b/tests/bsim/bluetooth/audio_samples/ccp/call_control_client/src/test_main.c
new file mode 100644
index 00000000000..84c550b878b
--- /dev/null
+++ b/tests/bsim/bluetooth/audio_samples/ccp/call_control_client/src/test_main.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <inttypes.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#include "bs_types.h"
+#include "bs_tracing.h"
+#include "bs_utils.h"
+#include "bstests.h"
+
+#define WAIT_TIME 10 /* Seconds */
+
+extern enum bst_result_t bst_result;
+
+#define FAIL(...)                                                                                  \
+	do {                                                                                       \
+		bst_result = Failed;                                                               \
+		bs_trace_error_time_line(__VA_ARGS__);                                             \
+	} while (0)
+
+#define PASS(...)                                                                                  \
+	do {                                                                                       \
+		bst_result = Passed;                                                               \
+		bs_trace_info_time(1, __VA_ARGS__);                                                \
+	} while (0)
+
+static void test_ccp_call_control_client_sample_init(void)
+{
+	bst_ticker_set_next_tick_absolute(WAIT_TIME * 1e6);
+	bst_result = In_progress;
+}
+
+static void test_ccp_call_control_client_sample_tick(bs_time_t HW_device_time)
+{
+	extern struct bt_ccp_call_control_client *client;
+
+	/* If discovery was a success then client is non-NULL - Use as pass criteria */
+	if (client == NULL) {
+		FAIL("CCP Call Control Client sample FAILED (Did not pass after %i seconds)\n",
+		     WAIT_TIME);
+	} else {
+		PASS("CCP Call Control Client sample PASSED\n");
+	}
+}
+
+static const struct bst_test_instance test_sample[] = {
+	{
+		.test_id = "ccp_call_control_client",
+		.test_descr = "Test based on the CCP Call Control Client sample. "
+			      "It expects to be connected to a compatible CCP server, "
+			      "waits for " STR(WAIT_TIME) " seconds, and checks how "
+			      "many audio packets have been received correctly",
+		.test_post_init_f = test_ccp_call_control_client_sample_init,
+		.test_tick_f = test_ccp_call_control_client_sample_tick,
+	},
+	BSTEST_END_MARKER,
+};
+
+static struct bst_test_list *
+test_ccp_call_control_client_sample_install(struct bst_test_list *tests)
+{
+	tests = bst_add_tests(tests, test_sample);
+	return tests;
+}
+
+bst_test_install_t test_installers[] = {test_ccp_call_control_client_sample_install, NULL};
diff --git a/tests/bsim/bluetooth/audio_samples/ccp/call_control_client/sysbuild.cmake b/tests/bsim/bluetooth/audio_samples/ccp/call_control_client/sysbuild.cmake
new file mode 100644
index 00000000000..3af3a8a3824
--- /dev/null
+++ b/tests/bsim/bluetooth/audio_samples/ccp/call_control_client/sysbuild.cmake
@@ -0,0 +1,6 @@
+# Copyright (c) 2023-2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+include(${ZEPHYR_BASE}/samples/bluetooth/ccp_call_control_client/sysbuild.cmake)
+
+native_simulator_set_primary_mcu_index(${DEFAULT_IMAGE} ${NET_APP})
diff --git a/tests/bsim/bluetooth/audio_samples/ccp/compile.sh b/tests/bsim/bluetooth/audio_samples/ccp/compile.sh
index 186805e7ec4..cfc92e66c78 100755
--- a/tests/bsim/bluetooth/audio_samples/ccp/compile.sh
+++ b/tests/bsim/bluetooth/audio_samples/ccp/compile.sh
@@ -15,12 +15,22 @@ if [ "${BOARD_TS}" == "nrf5340bsim_nrf5340_cpuapp" ]; then
     conf_file=${sample}/prj.conf \
     conf_overlay=${sample}/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf \
     exe_name=bs_${BOARD_TS}_${app}_prj_conf sysbuild=1 compile
+  app=tests/bsim/bluetooth/audio_samples/ccp/call_control_client \
+    sample=${ZEPHYR_BASE}/samples/bluetooth/ccp_call_control_client \
+    conf_file=${sample}/prj.conf \
+    conf_overlay=${sample}/boards/nrf5340_audio_dk_nrf5340_cpuapp.conf \
+    exe_name=bs_${BOARD_TS}_${app}_prj_conf sysbuild=1 compile
 else
   app=tests/bsim/bluetooth/audio_samples/ccp/call_control_server \
     sample=${ZEPHYR_BASE}/samples/bluetooth/ccp_call_control_server \
     conf_file=${sample}/prj.conf \
     conf_overlay=${sample}/overlay-bt_ll_sw_split.conf \
     exe_name=bs_${BOARD_TS}_${app}_prj_conf sysbuild=1 compile
+  app=tests/bsim/bluetooth/audio_samples/ccp/call_control_client \
+    sample=${ZEPHYR_BASE}/samples/bluetooth/ccp_call_control_client \
+    conf_file=${sample}/prj.conf \
+    conf_overlay=${sample}/overlay-bt_ll_sw_split.conf \
+    exe_name=bs_${BOARD_TS}_${app}_prj_conf sysbuild=1 compile
 fi
 
 wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/audio_samples/ccp/tests_scripts/ccp.sh b/tests/bsim/bluetooth/audio_samples/ccp/tests_scripts/ccp.sh
index 87564607df7..e366ea54eee 100755
--- a/tests/bsim/bluetooth/audio_samples/ccp/tests_scripts/ccp.sh
+++ b/tests/bsim/bluetooth/audio_samples/ccp/tests_scripts/ccp.sh
@@ -14,7 +14,10 @@ cd ${BSIM_OUT_PATH}/bin
 Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_samples_ccp_call_control_server_prj_conf \
   -v=${verbosity_level} -s=${simulation_id} -d=0 -RealEncryption=1 -testid=ccp_call_control_server
 
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_audio_samples_ccp_call_control_client_prj_conf \
+  -v=${verbosity_level} -s=${simulation_id} -d=1 -RealEncryption=1 -testid=ccp_call_control_client
+
 Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \
-  -D=1 -sim_length=20e6 $@ -argschannel -at=40
+  -D=2 -sim_length=20e6 $@ -argschannel -at=40
 
 wait_for_background_jobs #Wait for all programs in background and return != 0 if any fails
diff --git a/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh b/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh
index 62f32ca2338..8943a9605ad 100755
--- a/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh
+++ b/tests/bsim/bluetooth/compile.nrf5340bsim_nrf5340_cpuapp.sh
@@ -12,8 +12,15 @@ export BOARD="${BOARD:-nrf5340bsim/nrf5340/cpuapp}"
 
 source ${ZEPHYR_BASE}/tests/bsim/compile.source
 
+${ZEPHYR_BASE}/tests/bsim/bluetooth/host/compile.sh
+${ZEPHYR_BASE}/tests/bsim/bluetooth/tester/compile.sh
+
 app=tests/bsim/bluetooth/ll/conn conf_file=prj_split_privacy.conf sysbuild=1  compile
-app=tests/bsim/bluetooth/ll/bis sysbuild=1 compile
+app=tests/bsim/bluetooth/ll/throughput sysbuild=1 compile
+app=tests/bsim/bluetooth/ll/multiple_id sysbuild=1 compile
+app=tests/bsim/bluetooth/ll/bis conf_overlay=overlay-sequential.conf sysbuild=1 compile
+app=tests/bsim/bluetooth/ll/bis conf_overlay=overlay-interleaved.conf sysbuild=1 compile
+app=tests/bsim/bluetooth/ll/bis conf_overlay=overlay-ticker_expire_info.conf sysbuild=1 compile
 app=tests/bsim/bluetooth/ll/cis conf_overlay=overlay-acl_group.conf sysbuild=1 compile
 
 run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/samples/compile.sh
diff --git a/tests/bsim/bluetooth/compile.nrf54l15bsim_nrf54l15_cpuapp.sh b/tests/bsim/bluetooth/compile.nrf54l15bsim_nrf54l15_cpuapp.sh
index 8e56e1caa39..e0524dbbdea 100755
--- a/tests/bsim/bluetooth/compile.nrf54l15bsim_nrf54l15_cpuapp.sh
+++ b/tests/bsim/bluetooth/compile.nrf54l15bsim_nrf54l15_cpuapp.sh
@@ -13,8 +13,14 @@ export BOARD="${BOARD:-nrf54l15bsim/nrf54l15/cpuapp}"
 
 source ${ZEPHYR_BASE}/tests/bsim/compile.source
 
+app=tests/bsim/bluetooth/ll/throughput compile
 app=tests/bsim/bluetooth/ll/multiple_id compile
+app=tests/bsim/bluetooth/ll/bis conf_overlay=overlay-sequential.conf compile
+app=tests/bsim/bluetooth/ll/bis conf_overlay=overlay-interleaved.conf  compile
+app=tests/bsim/bluetooth/ll/bis conf_overlay=overlay-ticker_expire_info.conf compile
 
 run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/samples/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/audio/compile.sh
+run_in_background ${ZEPHYR_BASE}/tests/bsim/bluetooth/audio_samples/compile.sh
 
 wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/compile.sh b/tests/bsim/bluetooth/compile.sh
index 76525a81613..f8e62a7fb63 100755
--- a/tests/bsim/bluetooth/compile.sh
+++ b/tests/bsim/bluetooth/compile.sh
@@ -24,5 +24,6 @@ ${ZEPHYR_BASE}/tests/bsim/bluetooth/samples/compile.sh
 if [ ${BOARD} == "nrf52_bsim/native" ]; then
 	${ZEPHYR_BASE}/tests/bsim/bluetooth/hci_uart/compile.sh
 fi
+${ZEPHYR_BASE}/tests/bsim/bluetooth/tester/compile.sh
 
 wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/adv/periodic/src/per_adv_sync.c b/tests/bsim/bluetooth/host/adv/periodic/src/per_adv_sync.c
index 2938bf9846f..9f4399a8b2d 100644
--- a/tests/bsim/bluetooth/host/adv/periodic/src/per_adv_sync.c
+++ b/tests/bsim/bluetooth/host/adv/periodic/src/per_adv_sync.c
@@ -149,7 +149,7 @@ static void recv_cb(struct bt_le_per_adv_sync *recv_sync,
 	}
 
 	bt_addr_le_to_str(info->addr, le_addr, sizeof(le_addr));
-	printk("PER_ADV_SYNC[%u]: [DEVICE]: %s advertisment received\n",
+	printk("PER_ADV_SYNC[%u]: [DEVICE]: %s advertisement received\n",
 	       bt_le_per_adv_sync_get_index(recv_sync), le_addr);
 
 	while (buf->len > 0) {
@@ -355,7 +355,7 @@ static void main_per_adv_long_data_sync(void)
 
 	create_pa_sync(&sync);
 
-	printk("Waiting to receive periodic advertisment...\n");
+	printk("Waiting to receive periodic advertisement...\n");
 	WAIT_FOR_FLAG(flag_per_adv_recv);
 
 	printk("Waiting for periodic sync lost...\n");
diff --git a/tests/bsim/bluetooth/host/att/pipeline/tester/prj.conf b/tests/bsim/bluetooth/host/att/pipeline/tester/prj.conf
index a5ca6cf0f62..16c2caa091c 100644
--- a/tests/bsim/bluetooth/host/att/pipeline/tester/prj.conf
+++ b/tests/bsim/bluetooth/host/att/pipeline/tester/prj.conf
@@ -5,11 +5,9 @@ CONFIG_BT=y
 CONFIG_BT_HCI_RAW=y
 CONFIG_BT_MAX_CONN=1
 
-CONFIG_BT_BUF_CMD_TX_COUNT=10
-
 CONFIG_BT_BUF_ACL_TX_COUNT=20
+CONFIG_BT_BUF_EVT_RX_COUNT=21
 
-CONFIG_BT_BUF_ACL_RX_SIZE=255
 CONFIG_BT_BUF_CMD_TX_SIZE=255
 CONFIG_BT_BUF_EVT_DISCARDABLE_SIZE=255
 
diff --git a/tests/bsim/bluetooth/host/att/pipeline/tester/src/main.c b/tests/bsim/bluetooth/host/att/pipeline/tester/src/main.c
index 3f49e7e43cd..ad2cfee2f46 100644
--- a/tests/bsim/bluetooth/host/att/pipeline/tester/src/main.c
+++ b/tests/bsim/bluetooth/host/att/pipeline/tester/src/main.c
@@ -16,6 +16,7 @@
 #include <zephyr/bluetooth/hci_raw.h>
 #include <zephyr/bluetooth/hci_types.h>
 
+#include "common/hci_common_internal.h"
 #include "common/bt_str.h"
 
 #include "host/conn_internal.h"
@@ -55,7 +56,7 @@ static att_handler_t att_handlers[LAST_SUPPORTED_ATT_OPCODE];
 static K_FIFO_DEFINE(rx_queue);
 
 #define CMD_BUF_SIZE MAX(BT_BUF_EVT_RX_SIZE, BT_BUF_CMD_TX_SIZE)
-NET_BUF_POOL_FIXED_DEFINE(hci_cmd_pool, CONFIG_BT_BUF_CMD_TX_COUNT,
+NET_BUF_POOL_FIXED_DEFINE(hci_cmd_pool, BT_BUF_CMD_TX_COUNT,
 			  CMD_BUF_SIZE, 8, NULL);
 
 static K_SEM_DEFINE(cmd_sem, 1, 1);
diff --git a/tests/bsim/bluetooth/host/att/sequential/tester/prj.conf b/tests/bsim/bluetooth/host/att/sequential/tester/prj.conf
index 5217040a117..e8ba462aeea 100644
--- a/tests/bsim/bluetooth/host/att/sequential/tester/prj.conf
+++ b/tests/bsim/bluetooth/host/att/sequential/tester/prj.conf
@@ -5,8 +5,6 @@ CONFIG_BT=y
 CONFIG_BT_HCI_RAW=y
 CONFIG_BT_MAX_CONN=1
 
-CONFIG_BT_BUF_CMD_TX_COUNT=10
-
 CONFIG_BT_BUF_ACL_RX_SIZE=255
 CONFIG_BT_BUF_CMD_TX_SIZE=255
 CONFIG_BT_BUF_EVT_DISCARDABLE_SIZE=255
diff --git a/tests/bsim/bluetooth/host/att/sequential/tester/src/main.c b/tests/bsim/bluetooth/host/att/sequential/tester/src/main.c
index 4cd981d615b..fc3477072c1 100644
--- a/tests/bsim/bluetooth/host/att/sequential/tester/src/main.c
+++ b/tests/bsim/bluetooth/host/att/sequential/tester/src/main.c
@@ -16,6 +16,7 @@
 #include <zephyr/bluetooth/hci_raw.h>
 #include <zephyr/bluetooth/hci_types.h>
 
+#include "common/hci_common_internal.h"
 #include "common/bt_str.h"
 
 #include "host/conn_internal.h"
@@ -50,7 +51,7 @@ static uint16_t server_write_handle;
 static K_FIFO_DEFINE(rx_queue);
 
 #define CMD_BUF_SIZE MAX(BT_BUF_EVT_RX_SIZE, BT_BUF_CMD_TX_SIZE)
-NET_BUF_POOL_FIXED_DEFINE(hci_cmd_pool, CONFIG_BT_BUF_CMD_TX_COUNT,
+NET_BUF_POOL_FIXED_DEFINE(hci_cmd_pool, BT_BUF_CMD_TX_COUNT,
 			  CMD_BUF_SIZE, 8, NULL);
 
 static K_SEM_DEFINE(cmd_sem, 1, 1);
diff --git a/tests/bsim/bluetooth/host/central/src/main.c b/tests/bsim/bluetooth/host/central/src/main.c
index 2ee7b39d3fd..dd12fd91a5b 100644
--- a/tests/bsim/bluetooth/host/central/src/main.c
+++ b/tests/bsim/bluetooth/host/central/src/main.c
@@ -7,6 +7,10 @@
 #include "bstests.h"
 #include "babblekit/testcase.h"
 #include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/hci.h>
+
+/* Include hci_common_internal for the purpose of checking HCI Command counts. */
+#include "common/hci_common_internal.h"
 
 /* Include conn_internal for the purpose of checking reference counts. */
 #include "host/conn_internal.h"
@@ -42,7 +46,7 @@ static struct bt_conn_cb conn_cb = {
 	.connected = connected_cb,
 };
 
-static void test_central_connect_timeout_with_timeout(uint32_t timeout_ms)
+static void test_central_connect_timeout_with_timeout(uint32_t timeout_ms, bool stack_load)
 {
 	int err;
 	struct bt_conn *conn;
@@ -62,6 +66,7 @@ static void test_central_connect_timeout_with_timeout(uint32_t timeout_ms)
 		.window_coded = 0,
 		.timeout = timeout_ms / 10,
 	};
+	struct net_buf *bufs[BT_BUF_CMD_TX_COUNT];
 
 	k_sem_reset(&sem_failed_to_connect);
 
@@ -70,6 +75,21 @@ static void test_central_connect_timeout_with_timeout(uint32_t timeout_ms)
 	err = bt_conn_le_create(&peer, &create_param, BT_LE_CONN_PARAM_DEFAULT, &conn);
 	TEST_ASSERT(err == 0, "Failed starting initiator (err %d)", err);
 
+	if (stack_load) {
+		/* Claim all the buffers so that the stack cannot handle the timeout */
+		for (int i = 0; i < BT_BUF_CMD_TX_COUNT; i++) {
+			bufs[i] = bt_hci_cmd_create(BT_HCI_LE_ADV_ENABLE, 0);
+			TEST_ASSERT(bufs[i] != NULL, "Failed to claim all command buffers");
+		}
+		/* Hold all the buffers until after we expect the connection to timeout */
+		err = k_sem_take(&sem_failed_to_connect, K_MSEC(expected_conn_timeout_ms + 50));
+		TEST_ASSERT(err == -EAGAIN, "Callback ran with no buffers available", err);
+		/* Release all the buffers back to the stack */
+		for (int i = 0; i < BT_BUF_CMD_TX_COUNT; i++) {
+			net_buf_unref(bufs[i]);
+		}
+	}
+
 	err = k_sem_take(&sem_failed_to_connect, K_MSEC(2 * expected_conn_timeout_ms));
 	TEST_ASSERT(err == 0, "Failed getting connected timeout within %d s (err %d)",
 		    2 * expected_conn_timeout_ms, err);
@@ -96,8 +116,9 @@ static void test_central_connect_timeout(void)
 	err = bt_enable(NULL);
 	TEST_ASSERT(err == 0, "Can't enable Bluetooth (err %d)", err);
 
-	test_central_connect_timeout_with_timeout(0);
-	test_central_connect_timeout_with_timeout(1000);
+	test_central_connect_timeout_with_timeout(0, false);
+	test_central_connect_timeout_with_timeout(1000, false);
+	test_central_connect_timeout_with_timeout(2000, true);
 
 	TEST_PASS("Correct timeout");
 }
diff --git a/tests/bsim/bluetooth/host/gatt/ccc_store/overlay-no_long_wq.conf b/tests/bsim/bluetooth/host/gatt/ccc_store/overlay-no_long_wq.conf
new file mode 100644
index 00000000000..baebf9ca980
--- /dev/null
+++ b/tests/bsim/bluetooth/host/gatt/ccc_store/overlay-no_long_wq.conf
@@ -0,0 +1,2 @@
+# Disable the dedicated workqueue for long-running tasks.
+CONFIG_BT_LONG_WQ=n
diff --git a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_no_store_on_write.sh b/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_no_store_on_write.sh
deleted file mode 100755
index 97b6631b1a4..00000000000
--- a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_no_store_on_write.sh
+++ /dev/null
@@ -1,41 +0,0 @@
-#!/bin/env bash
-# Copyright 2023 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
-
-test_exe="bs_${BOARD_TS}_$(guess_test_long_name)_overlay-no_store_on_write_conf"
-simulation_id="ccc_no_store_on_write"
-verbosity_level=2
-EXECUTE_TIMEOUT=60
-
-cd ${BSIM_OUT_PATH}/bin
-
-if [ "${1}" != 'debug0' ]; then
-  Execute "./${test_exe}" \
-    -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central \
-    -flash="${simulation_id}_client.log.bin" -flash_rm -RealEncryption=1 -argstest 10
-fi
-
-if [ "${1}" != 'debug1' ]; then
-  Execute "./${test_exe}" \
-    -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral \
-    -flash="${simulation_id}_server.log.bin" -flash_rm -RealEncryption=1 -argstest 10
-fi
-
-Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \
-  -D=2 -sim_length=60e6
-
-if [ "${1}" == 'debug0' ]; then
-  gdb --args "./${test_exe}" \
-    -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central \
-    -flash="${simulation_id}_client.log.bin" -flash_rm -RealEncryption=1 -argstest 10
-fi
-
-if [ "${1}" == 'debug1' ]; then
-  gdb --args "./${test_exe}" \
-    -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral \
-    -flash="${simulation_id}_server.log.bin" -flash_rm -RealEncryption=1 -argstest 10
-fi
-
-wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store_no_long_wq.sh b/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store_no_long_wq.sh
new file mode 100755
index 00000000000..cad38e56e52
--- /dev/null
+++ b/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store_no_long_wq.sh
@@ -0,0 +1,41 @@
+#!/bin/env bash
+# Copyright 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
+
+test_exe="bs_${BOARD_TS}_$(guess_test_long_name)_overlay-no_long_wq_conf"
+simulation_id="ccc_store_no_long_wq"
+verbosity_level=2
+EXECUTE_TIMEOUT=60
+
+cd ${BSIM_OUT_PATH}/bin
+
+if [ "${1}" != 'debug0' ]; then
+  Execute "./${test_exe}" \
+    -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central \
+    -flash="${simulation_id}_client.log.bin" -flash_rm -RealEncryption=1 -argstest 10
+fi
+
+if [ "${1}" != 'debug1' ]; then
+  Execute "./${test_exe}" \
+    -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral \
+    -flash="${simulation_id}_server.log.bin" -flash_rm -RealEncryption=1 -argstest 10
+fi
+
+Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \
+  -D=2 -sim_length=60e6
+
+if [ "${1}" == 'debug0' ]; then
+  gdb --args "./${test_exe}" \
+    -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central \
+    -flash="${simulation_id}_client.log.bin" -flash_rm -RealEncryption=1 -argstest 10
+fi
+
+if [ "${1}" == 'debug1' ]; then
+  gdb --args "./${test_exe}" \
+    -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral \
+    -flash="${simulation_id}_server.log.bin" -flash_rm -RealEncryption=1 -argstest 10
+fi
+
+wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store_no_store_on_write.sh b/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store_no_store_on_write.sh
new file mode 100755
index 00000000000..b732d1c598f
--- /dev/null
+++ b/tests/bsim/bluetooth/host/gatt/ccc_store/test_scripts/ccc_store_no_store_on_write.sh
@@ -0,0 +1,41 @@
+#!/bin/env bash
+# Copyright 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
+
+test_exe="bs_${BOARD_TS}_$(guess_test_long_name)_overlay-no_store_on_write_conf"
+simulation_id="ccc_store_no_store_on_write"
+verbosity_level=2
+EXECUTE_TIMEOUT=60
+
+cd ${BSIM_OUT_PATH}/bin
+
+if [ "${1}" != 'debug0' ]; then
+  Execute "./${test_exe}" \
+    -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central \
+    -flash="${simulation_id}_client.log.bin" -flash_rm -RealEncryption=1 -argstest 10
+fi
+
+if [ "${1}" != 'debug1' ]; then
+  Execute "./${test_exe}" \
+    -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral \
+    -flash="${simulation_id}_server.log.bin" -flash_rm -RealEncryption=1 -argstest 10
+fi
+
+Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \
+  -D=2 -sim_length=60e6
+
+if [ "${1}" == 'debug0' ]; then
+  gdb --args "./${test_exe}" \
+    -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central \
+    -flash="${simulation_id}_client.log.bin" -flash_rm -RealEncryption=1 -argstest 10
+fi
+
+if [ "${1}" == 'debug1' ]; then
+  gdb --args "./${test_exe}" \
+    -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral \
+    -flash="${simulation_id}_server.log.bin" -flash_rm -RealEncryption=1 -argstest 10
+fi
+
+wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/gatt/ccc_store/testcase.yaml b/tests/bsim/bluetooth/host/gatt/ccc_store/testcase.yaml
index 12ab2fc7036..a2ee367de1a 100644
--- a/tests/bsim/bluetooth/host/gatt/ccc_store/testcase.yaml
+++ b/tests/bsim/bluetooth/host/gatt/ccc_store/testcase.yaml
@@ -10,8 +10,13 @@ tests:
   bluetooth.host.gatt.ccc_store:
     harness_config:
       bsim_exe_name: tests_bsim_bluetooth_host_gatt_ccc_store_prj_conf
-  bluetooth.host.gatt.ccc_store_2:
+  bluetooth.host.gatt.ccc_store_no_store_on_write:
     harness_config:
       bsim_exe_name: tests_bsim_bluetooth_host_gatt_ccc_store_overlay-no_store_on_write_conf
     extra_args:
       EXTRA_CONF_FILE=overlay-no_store_on_write.conf
+  bluetooth.host.gatt.ccc_store_no_long_wq:
+    harness_config:
+      bsim_exe_name: tests_bsim_bluetooth_host_gatt_ccc_store_overlay-no_long_wq_conf
+    extra_args:
+      EXTRA_CONF_FILE=overlay-no_long_wq.conf
diff --git a/tests/bsim/bluetooth/host/gatt/notify_stress/CMakeLists.txt b/tests/bsim/bluetooth/host/gatt/notify_stress/CMakeLists.txt
new file mode 100644
index 00000000000..b279e8c1439
--- /dev/null
+++ b/tests/bsim/bluetooth/host/gatt/notify_stress/CMakeLists.txt
@@ -0,0 +1,17 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(bsim_test_gatt)
+
+add_subdirectory(${ZEPHYR_BASE}/tests/bsim/babblekit babblekit)
+target_link_libraries(app PRIVATE babblekit)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources} )
+
+zephyr_include_directories(
+  ${BSIM_COMPONENTS_PATH}/libUtilv1/src/
+  ${BSIM_COMPONENTS_PATH}/libPhyComv1/src/
+  )
diff --git a/tests/bsim/bluetooth/host/gatt/notify_stress/Kconfig.sysbuild b/tests/bsim/bluetooth/host/gatt/notify_stress/Kconfig.sysbuild
new file mode 100644
index 00000000000..79d8f991960
--- /dev/null
+++ b/tests/bsim/bluetooth/host/gatt/notify_stress/Kconfig.sysbuild
@@ -0,0 +1,14 @@
+# Copyright 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+source "share/sysbuild/Kconfig"
+
+config NET_CORE_BOARD
+	string
+	default "nrf5340bsim/nrf5340/cpunet" if $(BOARD_TARGET_STRING) = "NRF5340BSIM_NRF5340_CPUAPP"
+
+config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX
+	int
+	# Let's pass the test arguments to the application MCU test
+	# otherwise by default they would have gone to the net core.
+	default 0 if $(BOARD_TARGET_STRING) = "NRF5340BSIM_NRF5340_CPUAPP"
diff --git a/tests/bsim/bluetooth/host/gatt/notify_stress/nrf5340_cpunet-bt_ll_sw_split.conf b/tests/bsim/bluetooth/host/gatt/notify_stress/nrf5340_cpunet-bt_ll_sw_split.conf
new file mode 100644
index 00000000000..853adc082da
--- /dev/null
+++ b/tests/bsim/bluetooth/host/gatt/notify_stress/nrf5340_cpunet-bt_ll_sw_split.conf
@@ -0,0 +1,30 @@
+CONFIG_IPC_SERVICE=y
+CONFIG_MBOX=y
+CONFIG_ISR_STACK_SIZE=1024
+CONFIG_IDLE_STACK_SIZE=256
+CONFIG_MAIN_STACK_SIZE=512
+CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=512
+CONFIG_IPC_SERVICE_BACKEND_RPMSG_WQ_STACK_SIZE=512
+CONFIG_HEAP_MEM_POOL_SIZE=4096
+CONFIG_CBPRINTF_REDUCED_INTEGRAL=y
+CONFIG_ISR_TABLES_LOCAL_DECLARATION=y
+
+CONFIG_BT=y
+CONFIG_BT_HCI_RAW=y
+CONFIG_BT_MAX_CONN=1
+
+# Controller
+CONFIG_BT_LL_SW_SPLIT=y
+CONFIG_BT_CTLR_ASSERT_HANDLER=y
+
+CONFIG_BT_CTLR_DATA_LENGTH_MAX=70
+CONFIG_BT_CTLR_ADV_DATA_LEN_MAX=191
+CONFIG_BT_CTLR_RX_BUFFERS=10
+
+CONFIG_BT_BUF_CMD_TX_SIZE=65
+CONFIG_BT_BUF_EVT_RX_SIZE=68
+CONFIG_BT_BUF_EVT_RX_COUNT=17
+CONFIG_BT_BUF_ACL_TX_COUNT=16
+CONFIG_BT_BUF_ACL_TX_SIZE=70
+CONFIG_BT_BUF_ACL_RX_SIZE=70
+CONFIG_BT_BUF_ACL_RX_COUNT_EXTRA=1
diff --git a/tests/bsim/bluetooth/host/gatt/notify_stress/prj.conf b/tests/bsim/bluetooth/host/gatt/notify_stress/prj.conf
new file mode 100644
index 00000000000..5e04334eecc
--- /dev/null
+++ b/tests/bsim/bluetooth/host/gatt/notify_stress/prj.conf
@@ -0,0 +1,35 @@
+CONFIG_BT=y
+CONFIG_BT_DEVICE_NAME="GATT tester"
+CONFIG_BT_PERIPHERAL=y
+CONFIG_BT_CENTRAL=y
+CONFIG_BT_GATT_CLIENT=y
+
+CONFIG_BT_GATT_AUTO_DISCOVER_CCC=y
+
+CONFIG_BT_SMP=y
+CONFIG_BT_L2CAP_DYNAMIC_CHANNEL=y
+CONFIG_BT_L2CAP_ECRED=y
+CONFIG_BT_EATT=y
+
+CONFIG_BT_AUTO_PHY_UPDATE=n
+CONFIG_BT_AUTO_DATA_LEN_UPDATE=n
+
+CONFIG_ASSERT=y
+CONFIG_BT_TESTING=y
+CONFIG_LOG=y
+
+# Maximum possible EATT channels are used to parallelize notifications as much as possible,
+# increasing traffic towards Central.
+CONFIG_BT_EATT_MAX=16
+
+# This is aligned with CONFIG_BT_EATT_MAX to utilize all EATT channels
+CONFIG_BT_BUF_ACL_TX_COUNT=16
+
+# Aligned with characteristic size
+CONFIG_BT_BUF_ACL_RX_SIZE=70
+CONFIG_BT_BUF_ACL_TX_SIZE=70
+
+CONFIG_BT_BUF_EVT_RX_COUNT=17
+CONFIG_BT_BUF_ACL_RX_COUNT_EXTRA=1
+
+CONFIG_BT_BUF_CMD_TX_COUNT=2
diff --git a/tests/bsim/bluetooth/host/gatt/notify_stress/src/common.h b/tests/bsim/bluetooth/host/gatt/notify_stress/src/common.h
new file mode 100644
index 00000000000..4258969f4da
--- /dev/null
+++ b/tests/bsim/bluetooth/host/gatt/notify_stress/src/common.h
@@ -0,0 +1,21 @@
+/**
+ * Common macros used by both sides of the test
+ *
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/toolchain.h>
+
+#define CHRC_SIZE 60
+
+#define TEST_SERVICE_UUID                                                                          \
+	BT_UUID_DECLARE_128(0x01, 0x23, 0x45, 0x67, 0x89, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06,      \
+			    0x07, 0x08, 0x09, 0x00, 0x00)
+
+#define TEST_CHRC_UUID                                                                             \
+	BT_UUID_DECLARE_128(0x01, 0x23, 0x45, 0x67, 0x89, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06,      \
+			    0x07, 0x08, 0x09, 0xFF, 0x11)
+
+#define NOTIFICATION_COUNT 30
diff --git a/tests/bsim/bluetooth/host/gatt/notify_stress/src/gatt_client_test.c b/tests/bsim/bluetooth/host/gatt/notify_stress/src/gatt_client_test.c
new file mode 100644
index 00000000000..bd866ec254d
--- /dev/null
+++ b/tests/bsim/bluetooth/host/gatt/notify_stress/src/gatt_client_test.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stddef.h>
+#include <errno.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/types.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/uuid.h>
+#include <zephyr/bluetooth/gatt.h>
+
+#include "babblekit/testcase.h"
+#include "babblekit/flags.h"
+#include "common.h"
+
+DEFINE_FLAG_STATIC(flag_is_connected);
+DEFINE_FLAG_STATIC(flag_is_encrypted);
+DEFINE_FLAG_STATIC(flag_discover_complete);
+DEFINE_FLAG_STATIC(flag_long_subscribed);
+
+static struct bt_conn *g_conn;
+static uint16_t long_chrc_handle;
+static const struct bt_uuid *test_svc_uuid = TEST_SERVICE_UUID;
+
+static void connected(struct bt_conn *conn, uint8_t err)
+{
+	char addr[BT_ADDR_LE_STR_LEN];
+
+	bt_addr_le_to_str(bt_conn_get_dst(conn), addr, sizeof(addr));
+
+	if (err != 0) {
+		TEST_FAIL("Failed to connect to %s (%u)", addr, err);
+		return;
+	}
+
+	printk("Connected to %s\n", addr);
+
+	SET_FLAG(flag_is_connected);
+}
+
+static void disconnected(struct bt_conn *conn, uint8_t reason)
+{
+	char addr[BT_ADDR_LE_STR_LEN];
+
+	if (conn != g_conn) {
+		return;
+	}
+
+	bt_addr_le_to_str(bt_conn_get_dst(conn), addr, sizeof(addr));
+
+	printk("Disconnected: %s (reason 0x%02x)\n", addr, reason);
+
+	bt_conn_unref(g_conn);
+
+	g_conn = NULL;
+	UNSET_FLAG(flag_is_connected);
+}
+
+void security_changed(struct bt_conn *conn, bt_security_t level, enum bt_security_err err)
+{
+	if (err) {
+		TEST_FAIL("Encryption failure (%d)", err);
+	} else if (level < BT_SECURITY_L2) {
+		TEST_FAIL("Insufficient sec level (%d)", level);
+	} else {
+		SET_FLAG(flag_is_encrypted);
+	}
+}
+
+BT_CONN_CB_DEFINE(conn_callbacks) = {
+	.connected = connected,
+	.disconnected = disconnected,
+	.security_changed = security_changed,
+};
+
+void device_found(const bt_addr_le_t *addr, int8_t rssi, uint8_t type, struct net_buf_simple *ad)
+{
+	char addr_str[BT_ADDR_LE_STR_LEN];
+	int err;
+
+	if (g_conn != NULL) {
+		return;
+	}
+
+	/* We're only interested in connectable events */
+	if (type != BT_HCI_ADV_IND && type != BT_HCI_ADV_DIRECT_IND) {
+		return;
+	}
+
+	bt_addr_le_to_str(addr, addr_str, sizeof(addr_str));
+	printk("Device found: %s (RSSI %d)\n", addr_str, rssi);
+
+	printk("Stopping scan\n");
+	err = bt_le_scan_stop();
+	if (err != 0) {
+		TEST_FAIL("Could not stop scan: %d");
+		return;
+	}
+
+	err = bt_conn_le_create(addr, BT_CONN_LE_CREATE_CONN, BT_LE_CONN_PARAM_DEFAULT, &g_conn);
+	if (err != 0) {
+		TEST_FAIL("Could not connect to peer: %d", err);
+	}
+}
+
+static uint8_t discover_func(struct bt_conn *conn, const struct bt_gatt_attr *attr,
+			     struct bt_gatt_discover_params *params)
+{
+	int err;
+
+	if (attr == NULL) {
+		if (long_chrc_handle == 0) {
+			TEST_FAIL("Did not discover long_chrc (%x)", long_chrc_handle);
+		}
+
+		(void)memset(params, 0, sizeof(*params));
+
+		SET_FLAG(flag_discover_complete);
+
+		return BT_GATT_ITER_STOP;
+	}
+
+	printk("[ATTRIBUTE] handle %u\n", attr->handle);
+
+	if (params->type == BT_GATT_DISCOVER_PRIMARY &&
+	    bt_uuid_cmp(params->uuid, TEST_SERVICE_UUID) == 0) {
+		printk("Found test service\n");
+		params->uuid = NULL;
+		params->start_handle = attr->handle + 1;
+		params->type = BT_GATT_DISCOVER_CHARACTERISTIC;
+
+		err = bt_gatt_discover(conn, params);
+		if (err != 0) {
+			TEST_FAIL("Discover failed (err %d)", err);
+		}
+
+		return BT_GATT_ITER_STOP;
+	} else if (params->type == BT_GATT_DISCOVER_CHARACTERISTIC) {
+		const struct bt_gatt_chrc *chrc = (struct bt_gatt_chrc *)attr->user_data;
+
+		if (bt_uuid_cmp(chrc->uuid, TEST_CHRC_UUID) == 0) {
+			printk("Found long_chrc\n");
+			long_chrc_handle = chrc->value_handle;
+		}
+	}
+
+	return BT_GATT_ITER_CONTINUE;
+}
+
+static void gatt_discover(enum bt_att_chan_opt opt)
+{
+	static struct bt_gatt_discover_params discover_params;
+	int err;
+
+	printk("Discovering services and characteristics\n");
+
+	discover_params.uuid = test_svc_uuid;
+	discover_params.func = discover_func;
+	discover_params.start_handle = BT_ATT_FIRST_ATTRIBUTE_HANDLE;
+	discover_params.end_handle = BT_ATT_LAST_ATTRIBUTE_HANDLE;
+	discover_params.type = BT_GATT_DISCOVER_PRIMARY;
+	discover_params.chan_opt = opt;
+
+	err = bt_gatt_discover(g_conn, &discover_params);
+	if (err != 0) {
+		TEST_FAIL("Discover failed(err %d)", err);
+	}
+
+	WAIT_FOR_FLAG(flag_discover_complete);
+	printk("Discover complete\n");
+}
+
+static void test_long_subscribed(struct bt_conn *conn, uint8_t err,
+				 struct bt_gatt_subscribe_params *params)
+{
+	if (err) {
+		TEST_FAIL("Subscribe failed (err %d)", err);
+	}
+
+	SET_FLAG(flag_long_subscribed);
+
+	if (!params) {
+		printk("params NULL\n");
+		return;
+	}
+
+	if (params->value_handle == long_chrc_handle) {
+		printk("Subscribed to long characteristic\n");
+	} else {
+		TEST_FAIL("Unknown handle %d", params->value_handle);
+	}
+}
+
+static volatile size_t num_notifications;
+uint8_t test_notify(struct bt_conn *conn, struct bt_gatt_subscribe_params *params, const void *data,
+		    uint16_t length)
+{
+	printk("Received notification #%u with length %d\n", num_notifications++, length);
+
+	/* This causes ACL data drop in HCI IPC driver. */
+	k_sleep(K_MSEC(1000));
+
+	return BT_GATT_ITER_CONTINUE;
+}
+
+static struct bt_gatt_discover_params disc_params_long;
+static struct bt_gatt_subscribe_params sub_params_long = {
+	.notify = test_notify,
+	.subscribe = test_long_subscribed,
+	.ccc_handle = BT_GATT_AUTO_DISCOVER_CCC_HANDLE,
+	.disc_params = &disc_params_long,
+	.end_handle = BT_ATT_LAST_ATTRIBUTE_HANDLE,
+	.value = BT_GATT_CCC_NOTIFY,
+};
+
+static void gatt_subscribe_long(enum bt_att_chan_opt opt)
+{
+	int err;
+
+	UNSET_FLAG(flag_long_subscribed);
+	sub_params_long.value_handle = long_chrc_handle;
+	sub_params_long.chan_opt = opt;
+	err = bt_gatt_subscribe(g_conn, &sub_params_long);
+	if (err < 0) {
+		TEST_FAIL("Failed to subscribe");
+	} else {
+		printk("Subscribe request sent\n");
+	}
+}
+
+static void gatt_unsubscribe_long(enum bt_att_chan_opt opt)
+{
+	int err;
+
+	UNSET_FLAG(flag_long_subscribed);
+	sub_params_long.value_handle = long_chrc_handle;
+	sub_params_long.chan_opt = opt;
+	err = bt_gatt_unsubscribe(g_conn, &sub_params_long);
+	if (err < 0) {
+		TEST_FAIL("Failed to unsubscribe");
+	} else {
+		printk("Unsubscribe request sent\n");
+	}
+}
+
+static void setup(void)
+{
+	int err;
+
+	err = bt_enable(NULL);
+	if (err != 0) {
+		TEST_FAIL("Bluetooth discover failed (err %d)", err);
+	}
+
+	err = bt_le_scan_start(BT_LE_SCAN_PASSIVE, device_found);
+	if (err != 0) {
+		TEST_FAIL("Scanning failed to start (err %d)", err);
+	}
+
+	printk("Scanning successfully started\n");
+
+	WAIT_FOR_FLAG(flag_is_connected);
+
+	err = bt_conn_set_security(g_conn, BT_SECURITY_L2);
+	if (err) {
+		TEST_FAIL("Starting encryption procedure failed (%d)", err);
+	}
+
+	WAIT_FOR_FLAG(flag_is_encrypted);
+
+	while (bt_eatt_count(g_conn) < CONFIG_BT_EATT_MAX) {
+		k_sleep(K_MSEC(10));
+	}
+
+	printk("EATT connected\n");
+}
+
+static void test_main_client(void)
+{
+	setup();
+
+	gatt_discover(BT_ATT_CHAN_OPT_ENHANCED_ONLY);
+	gatt_subscribe_long(BT_ATT_CHAN_OPT_ENHANCED_ONLY);
+	WAIT_FOR_FLAG(flag_long_subscribed);
+
+	printk("Subscribed\n");
+
+	while (num_notifications < NOTIFICATION_COUNT) {
+		k_sleep(K_MSEC(100));
+	}
+
+	gatt_unsubscribe_long(BT_ATT_CHAN_OPT_ENHANCED_ONLY);
+	WAIT_FOR_FLAG(flag_long_subscribed);
+
+	printk("Unsubscribed\n");
+
+	TEST_PASS("GATT client Passed");
+}
+
+static const struct bst_test_instance test_vcs[] = {
+	{
+		.test_id = "gatt_client_enhanced_notif_stress",
+		.test_main_f = test_main_client,
+	},
+	BSTEST_END_MARKER,
+};
+
+struct bst_test_list *test_gatt_client_install(struct bst_test_list *tests)
+{
+	return bst_add_tests(tests, test_vcs);
+}
diff --git a/tests/bsim/bluetooth/host/gatt/notify_stress/src/gatt_server_test.c b/tests/bsim/bluetooth/host/gatt/notify_stress/src/gatt_server_test.c
new file mode 100644
index 00000000000..cde37821c33
--- /dev/null
+++ b/tests/bsim/bluetooth/host/gatt/notify_stress/src/gatt_server_test.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stddef.h>
+#include <errno.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/types.h>
+#include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/uuid.h>
+#include <zephyr/bluetooth/gatt.h>
+
+#include "babblekit/testcase.h"
+#include "babblekit/flags.h"
+#include "common.h"
+
+extern enum bst_result_t bst_result;
+
+DEFINE_FLAG_STATIC(flag_is_connected);
+DEFINE_FLAG_STATIC(flag_subscribe);
+
+static struct bt_conn *g_conn;
+
+#define ARRAY_ITEM(i, _) i
+const uint8_t chrc_data[] = { LISTIFY(CHRC_SIZE, ARRAY_ITEM, (,)) }; /* 1, 2, 3 ... */
+
+static void connected(struct bt_conn *conn, uint8_t err)
+{
+	char addr[BT_ADDR_LE_STR_LEN];
+
+	bt_addr_le_to_str(bt_conn_get_dst(conn), addr, sizeof(addr));
+
+	if (err != 0) {
+		TEST_FAIL("Failed to connect to %s (%u)", addr, err);
+		return;
+	}
+
+	printk("Connected to %s\n", addr);
+
+	g_conn = bt_conn_ref(conn);
+	SET_FLAG(flag_is_connected);
+}
+
+static void disconnected(struct bt_conn *conn, uint8_t reason)
+{
+	char addr[BT_ADDR_LE_STR_LEN];
+
+	if (conn != g_conn) {
+		return;
+	}
+
+	bt_addr_le_to_str(bt_conn_get_dst(conn), addr, sizeof(addr));
+
+	printk("Disconnected: %s (reason 0x%02x)\n", addr, reason);
+
+	bt_conn_unref(g_conn);
+
+	g_conn = NULL;
+	UNSET_FLAG(flag_is_connected);
+}
+
+BT_CONN_CB_DEFINE(conn_callbacks) = {
+	.connected = connected,
+	.disconnected = disconnected,
+};
+
+static ssize_t read_test_chrc(struct bt_conn *conn, const struct bt_gatt_attr *attr, void *buf,
+				   uint16_t len, uint16_t offset)
+{
+	printk("Read char\n");
+	return bt_gatt_attr_read(conn, attr, buf, len, offset, (void *)chrc_data,
+				 sizeof(chrc_data));
+}
+
+static void subscribe(const struct bt_gatt_attr *attr, uint16_t value)
+{
+	const bool notif_enabled = (value == BT_GATT_CCC_NOTIFY);
+
+	if (notif_enabled) {
+		SET_FLAG(flag_subscribe);
+	}
+
+	printk("Notifications %s\n", notif_enabled ? "enabled" : "disabled");
+}
+
+BT_GATT_SERVICE_DEFINE(test_svc, BT_GATT_PRIMARY_SERVICE(TEST_SERVICE_UUID),
+		       BT_GATT_CHARACTERISTIC(TEST_CHRC_UUID,
+					      BT_GATT_CHRC_NOTIFY | BT_GATT_CHRC_READ,
+					      BT_GATT_PERM_READ, read_test_chrc, NULL, NULL),
+		       BT_GATT_CCC(subscribe, BT_GATT_PERM_READ | BT_GATT_PERM_WRITE));
+
+static volatile size_t num_notifications_sent;
+
+static void notification_sent(struct bt_conn *conn, void *user_data)
+{
+	size_t *length = user_data;
+
+	printk("Sent notification #%u with length %d\n", num_notifications_sent++, *length);
+}
+
+static void notify(void)
+{
+	static size_t length = CHRC_SIZE;
+	static struct bt_gatt_notify_params params = {
+		.attr = &attr_test_svc[1],
+		.data = chrc_data,
+		.len = CHRC_SIZE,
+		.func = notification_sent,
+		.user_data = &length,
+		.uuid = NULL,
+		.chan_opt = BT_ATT_CHAN_OPT_ENHANCED_ONLY,
+	};
+	int err;
+
+	do {
+		err = bt_gatt_notify_cb(g_conn, &params);
+
+		if (err == -ENOMEM) {
+			/* The delay is needed to schedule other threads, but keep it as short as
+			 * possible.
+			 */
+			k_sleep(K_MSEC(1));
+		} else if (err) {
+			TEST_FAIL("Notify failed (err %d)", err);
+		}
+	} while (err);
+}
+
+static void setup(void)
+{
+	int err;
+	const struct bt_data ad[] = {
+		BT_DATA_BYTES(BT_DATA_FLAGS, (BT_LE_AD_GENERAL | BT_LE_AD_NO_BREDR)),
+	};
+
+	err = bt_enable(NULL);
+	if (err != 0) {
+		TEST_FAIL("Bluetooth init failed (err %d)", err);
+		return;
+	}
+
+	printk("Bluetooth initialized\n");
+
+	err = bt_le_adv_start(BT_LE_ADV_CONN_FAST_1, ad, ARRAY_SIZE(ad), NULL, 0);
+	if (err != 0) {
+		TEST_FAIL("Advertising failed to start (err %d)", err);
+		return;
+	}
+
+	printk("Advertising successfully started\n");
+
+	WAIT_FOR_FLAG(flag_is_connected);
+
+	while (bt_eatt_count(g_conn) < CONFIG_BT_EATT_MAX) {
+		k_sleep(K_MSEC(100));
+	}
+	printk("EATT connected\n");
+
+	WAIT_FOR_FLAG(flag_subscribe);
+}
+
+static void test_main_server(void)
+{
+	setup();
+
+	for (int i = 0; i < NOTIFICATION_COUNT; i++) {
+		notify();
+	}
+
+	while (num_notifications_sent < NOTIFICATION_COUNT) {
+		k_sleep(K_MSEC(100));
+	}
+
+	TEST_PASS("GATT server passed");
+}
+
+static const struct bst_test_instance test_gatt_server[] = {
+	{
+		.test_id = "gatt_server_enhanced_notif_stress",
+		.test_main_f = test_main_server,
+	},
+	BSTEST_END_MARKER,
+};
+
+struct bst_test_list *test_gatt_server_install(struct bst_test_list *tests)
+{
+	return bst_add_tests(tests, test_gatt_server);
+}
diff --git a/tests/bsim/bluetooth/host/gatt/notify_stress/src/main.c b/tests/bsim/bluetooth/host/gatt/notify_stress/src/main.c
new file mode 100644
index 00000000000..14ee71fd4d2
--- /dev/null
+++ b/tests/bsim/bluetooth/host/gatt/notify_stress/src/main.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bstests.h"
+
+extern struct bst_test_list *test_gatt_server_install(struct bst_test_list *tests);
+extern struct bst_test_list *test_gatt_client_install(struct bst_test_list *tests);
+
+bst_test_install_t test_installers[] = {
+	test_gatt_server_install,
+	test_gatt_client_install,
+	NULL
+};
+
+int main(void)
+{
+	bst_main();
+	return 0;
+}
diff --git a/tests/bsim/bluetooth/host/gatt/notify_stress/sysbuild.cmake b/tests/bsim/bluetooth/host/gatt/notify_stress/sysbuild.cmake
new file mode 100644
index 00000000000..2ef52ac6f61
--- /dev/null
+++ b/tests/bsim/bluetooth/host/gatt/notify_stress/sysbuild.cmake
@@ -0,0 +1,19 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT("${SB_CONFIG_NET_CORE_BOARD}" STREQUAL ""))
+	set(NET_APP hci_ipc)
+	set(NET_APP_SRC_DIR ${ZEPHYR_BASE}/samples/bluetooth/${NET_APP})
+
+	ExternalZephyrProject_Add(
+		APPLICATION ${NET_APP}
+		SOURCE_DIR  ${NET_APP_SRC_DIR}
+		BOARD       ${SB_CONFIG_NET_CORE_BOARD}
+	)
+
+	set(${NET_APP}_CONF_FILE ${APP_DIR}/nrf5340_cpunet-bt_ll_sw_split.conf CACHE INTERNAL "")
+
+	native_simulator_set_primary_mcu_index(${DEFAULT_IMAGE} ${NET_APP})
+	native_simulator_set_child_images(${DEFAULT_IMAGE} ${NET_APP})
+endif()
+native_simulator_set_final_executable(${DEFAULT_IMAGE})
diff --git a/tests/bsim/bluetooth/host/gatt/notify_stress/test_scripts/run_test.sh b/tests/bsim/bluetooth/host/gatt/notify_stress/test_scripts/run_test.sh
new file mode 100755
index 00000000000..489bea278af
--- /dev/null
+++ b/tests/bsim/bluetooth/host/gatt/notify_stress/test_scripts/run_test.sh
@@ -0,0 +1,55 @@
+#!/usr/bin/env bash
+# Copyright 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Test purpose:
+#
+# Verify that the Central can receive 30 notifications from the Peripheral over all available EATT
+# channels.
+#
+# Note: The number of notifications and the size of the characteristic are chosen empirically.
+#
+# This test is designed to stress HCI driver to guarantee that no data is dropped between Host and
+# Controller. Specifically, the HCI IPC driver that tends to drop data when the Host is not able to
+# process it fast enough. The test is guaranteed to fail with Controller to Host HCI data flow
+# control being disabled.
+#
+# Test Setup:
+#
+# - Devices: Central and Peripheral
+# - Characteristic Length: Peripheral exposes a long characteristic (greater than 23 bytes).
+# - Connection: Central connects to Peripheral.
+# - Notification subscription: Central subscribes to notificaitons from the Peripheral.
+# - EATT Usage: EATT is enabled, and the maximum possible EATT channels are established to
+#   parallelize notifications as much as possible, increasing traffic towards Central.
+#
+# Test Steps:
+#
+# 1. The Peripheral sends 30 notifications to the Central over all available EATT channels.
+# 2. Upon receiving a notification, the Central holds the received notification callback for 1
+#    second before releasing it.
+# 3. The test passes if all 30 notifications are successfully sent by the Peripheral and received
+#    by the Central.
+
+set -eu
+
+source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
+
+EXECUTE_TIMEOUT=150
+
+verbosity_level=2
+simulation_id="gatt_notify_enhanced_stress"
+server_id="gatt_server_enhanced_notif_stress"
+client_id="gatt_client_enhanced_notif_stress"
+
+cd ${BSIM_OUT_PATH}/bin
+
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_gatt_notify_stress_prj_conf \
+    -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=${client_id} -RealEncryption=1
+
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_host_gatt_notify_stress_prj_conf \
+    -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=${server_id} -RealEncryption=1
+
+Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} -D=2 -sim_length=70e6 $@
+
+wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/gatt/notify_stress/testcase.yaml b/tests/bsim/bluetooth/host/gatt/notify_stress/testcase.yaml
new file mode 100644
index 00000000000..ead6f5effdd
--- /dev/null
+++ b/tests/bsim/bluetooth/host/gatt/notify_stress/testcase.yaml
@@ -0,0 +1,12 @@
+tests:
+  bluetooth.host.gatt.notify_stress:
+    build_only: true
+    sysbuild: true
+    tags:
+      - bluetooth
+    platform_allow:
+      - nrf52_bsim/native
+      - nrf5340bsim/nrf5340/cpuapp
+    harness: bsim
+    harness_config:
+      bsim_exe_name: tests_bsim_bluetooth_host_gatt_notify_stress_prj_conf
diff --git a/tests/bsim/bluetooth/host/iso/bis/prj.conf b/tests/bsim/bluetooth/host/iso/bis/prj.conf
index 15eed7dd676..3a757252893 100644
--- a/tests/bsim/bluetooth/host/iso/bis/prj.conf
+++ b/tests/bsim/bluetooth/host/iso/bis/prj.conf
@@ -23,6 +23,7 @@ CONFIG_BT_CTLR_ADV_ISO_STREAM_MAX=4
 CONFIG_BT_CTLR_SYNC_ISO=y
 CONFIG_BT_CTLR_SYNC_ISO_STREAM_MAX=4
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=208
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=200
 CONFIG_BT_CTLR_ISO_TX_BUFFERS=4
 CONFIG_BT_CTLR_ISOAL_SOURCES=4
 CONFIG_BT_CTLR_ISOAL_SINKS=4
diff --git a/tests/bsim/bluetooth/host/iso/bis/src/bis_broadcaster.c b/tests/bsim/bluetooth/host/iso/bis/src/bis_broadcaster.c
index d18bc305053..cabb51697be 100644
--- a/tests/bsim/bluetooth/host/iso/bis/src/bis_broadcaster.c
+++ b/tests/bsim/bluetooth/host/iso/bis/src/bis_broadcaster.c
@@ -1,15 +1,29 @@
 /*
- * Copyright (c) 2024 Nordic Semiconductor
+ * Copyright (c) 2024-2025 Nordic Semiconductor
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/iso.h>
+#include <zephyr/kernel.h>
 #include <zephyr/logging/log.h>
+#include <zephyr/logging/log_core.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys_clock.h>
 
 #include "babblekit/flags.h"
 #include "babblekit/sync.h"
 #include "babblekit/testcase.h"
+#include "bstests.h"
 
 LOG_MODULE_REGISTER(bis_broadcaster, LOG_LEVEL_INF);
 
@@ -86,6 +100,12 @@ static void send_data_cb(struct k_work *work)
 
 static void iso_connected_cb(struct bt_iso_chan *chan)
 {
+	const struct bt_iso_chan_path hci_path = {
+		.pid = BT_ISO_DATA_PATH_HCI,
+		.format = BT_HCI_CODING_FORMAT_TRANSPARENT,
+	};
+	int err;
+
 	LOG_INF("ISO Channel %p connected", chan);
 
 	if (chan == default_chan) {
@@ -93,6 +113,9 @@ static void iso_connected_cb(struct bt_iso_chan *chan)
 
 		SET_FLAG(flag_iso_connected);
 	}
+
+	err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR, &hci_path);
+	TEST_ASSERT(err == 0, "Failed to set ISO data path: %d", err);
 }
 
 static void iso_disconnected_cb(struct bt_iso_chan *chan, uint8_t reason)
@@ -127,7 +150,6 @@ static void init(void)
 		.sdu = CONFIG_BT_ISO_TX_MTU,
 		.phy = BT_GAP_LE_PHY_2M,
 		.rtn = 1,
-		.path = NULL,
 	};
 	static struct bt_iso_chan_qos iso_qos = {
 		.tx = &iso_tx,
diff --git a/tests/bsim/bluetooth/host/iso/bis/src/bis_receiver.c b/tests/bsim/bluetooth/host/iso/bis/src/bis_receiver.c
index 5f80abdd1c1..aea23723ff0 100644
--- a/tests/bsim/bluetooth/host/iso/bis/src/bis_receiver.c
+++ b/tests/bsim/bluetooth/host/iso/bis/src/bis_receiver.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Nordic Semiconductor
+ * Copyright (c) 2024-2025 Nordic Semiconductor
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,6 +8,7 @@
 
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/iso.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/sys/util.h>
@@ -82,9 +83,18 @@ static void iso_recv(struct bt_iso_chan *chan, const struct bt_iso_recv_info *in
 
 static void iso_connected(struct bt_iso_chan *chan)
 {
+	const struct bt_iso_chan_path hci_path = {
+		.pid = BT_ISO_DATA_PATH_HCI,
+		.format = BT_HCI_CODING_FORMAT_TRANSPARENT,
+	};
+	int err;
+
 	LOG_INF("ISO Channel %p connected", chan);
 
 	SET_FLAG(flag_iso_connected);
+
+	err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_CTLR_TO_HOST, &hci_path);
+	TEST_ASSERT(err == 0, "Failed to setup ISO RX data path: %d\n", err);
 }
 
 static void iso_disconnected(struct bt_iso_chan *chan, uint8_t reason)
diff --git a/tests/bsim/bluetooth/host/iso/cis/CMakeLists.txt b/tests/bsim/bluetooth/host/iso/cis/CMakeLists.txt
index a0328bc6870..346345967c5 100644
--- a/tests/bsim/bluetooth/host/iso/cis/CMakeLists.txt
+++ b/tests/bsim/bluetooth/host/iso/cis/CMakeLists.txt
@@ -3,7 +3,10 @@
 cmake_minimum_required(VERSION 3.20.0)
 
 find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(bsim_test_l2cap_send_on_connect)
+project(bsim_test_iso_cis)
+
+add_subdirectory(${ZEPHYR_BASE}/tests/bsim/babblekit babblekit)
+target_link_libraries(app PRIVATE babblekit)
 
 target_sources(app PRIVATE
   src/common.c
@@ -18,7 +21,6 @@ zephyr_include_directories(
   )
 
 add_subdirectory(${ZEPHYR_BASE}/tests/bluetooth/common/testlib testlib)
-add_subdirectory(${ZEPHYR_BASE}/tests/bsim/babblekit babblekit)
 
 target_link_libraries(app PRIVATE
   testlib
diff --git a/tests/bsim/bluetooth/host/iso/cis/prj.conf b/tests/bsim/bluetooth/host/iso/cis/prj.conf
index bfdeab2c4e8..4ad0a0fd319 100644
--- a/tests/bsim/bluetooth/host/iso/cis/prj.conf
+++ b/tests/bsim/bluetooth/host/iso/cis/prj.conf
@@ -21,6 +21,7 @@ CONFIG_BT_ISO_LOG_LEVEL_DBG=y
 CONFIG_BT_CTLR_CENTRAL_ISO=y
 CONFIG_BT_CTLR_PERIPHERAL_ISO=y
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=208
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=200
 CONFIG_BT_CTLR_ISO_TX_BUFFERS=4
 CONFIG_BT_CTLR_ISOAL_SOURCES=2
 CONFIG_BT_CTLR_ISOAL_SINKS=2
diff --git a/tests/bsim/bluetooth/host/iso/cis/src/cis_central.c b/tests/bsim/bluetooth/host/iso/cis/src/cis_central.c
index f67afe3d399..dc7d46100a9 100644
--- a/tests/bsim/bluetooth/host/iso/cis/src/cis_central.c
+++ b/tests/bsim/bluetooth/host/iso/cis/src/cis_central.c
@@ -1,16 +1,30 @@
 /*
- * Copyright (c) 2023 Nordic Semiconductor
+ * Copyright (c) 2023-2025 Nordic Semiconductor
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "babblekit/testcase.h"
-#include "babblekit/flags.h"
-#include "common.h"
+#include <stddef.h>
+#include <stdint.h>
 
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/addr.h>
 #include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/iso.h>
+#include <zephyr/kernel.h>
+#include <zephyr/net_buf.h>
 #include <zephyr/sys/printk.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys_clock.h>
+#include <zephyr/toolchain.h>
+
+#include "babblekit/testcase.h"
+#include "babblekit/flags.h"
+#include "bstests.h"
+#include "common.h"
 
 #define ENQUEUE_COUNT 2
 
@@ -104,6 +118,12 @@ static void device_found(const bt_addr_le_t *addr, int8_t rssi, uint8_t type,
 
 static void iso_connected(struct bt_iso_chan *chan)
 {
+	const struct bt_iso_chan_path hci_path = {
+		.pid = BT_ISO_DATA_PATH_HCI,
+		.format = BT_HCI_CODING_FORMAT_TRANSPARENT,
+	};
+	int err;
+
 	printk("ISO Channel %p connected\n", chan);
 
 	seq_num = 0U;
@@ -115,10 +135,15 @@ static void iso_connected(struct bt_iso_chan *chan)
 
 		SET_FLAG(flag_iso_connected);
 	}
+
+	err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR, &hci_path);
+	TEST_ASSERT(err == 0, "Failed to set ISO data path: %d", err);
 }
 
 static void iso_disconnected(struct bt_iso_chan *chan, uint8_t reason)
 {
+	int err;
+
 	printk("ISO Channel %p disconnected (reason 0x%02x)\n", chan, reason);
 
 	if (chan == default_chan) {
@@ -126,6 +151,9 @@ static void iso_disconnected(struct bt_iso_chan *chan, uint8_t reason)
 
 		UNSET_FLAG(flag_iso_connected);
 	}
+
+	err = bt_iso_remove_data_path(chan, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR);
+	TEST_ASSERT(err == 0, "Failed to remove ISO data path: %d", err);
 }
 
 static void sdu_sent_cb(struct bt_iso_chan *chan)
@@ -156,7 +184,6 @@ static void init(void)
 		.sdu = CONFIG_BT_ISO_TX_MTU,
 		.phy = BT_GAP_LE_PHY_2M,
 		.rtn = 1,
-		.path = NULL,
 	};
 	static struct bt_iso_chan_qos iso_qos = {
 		.tx = &iso_tx,
diff --git a/tests/bsim/bluetooth/host/iso/cis/src/cis_peripheral.c b/tests/bsim/bluetooth/host/iso/cis/src/cis_peripheral.c
index ef0ede7b081..96b8865c1f4 100644
--- a/tests/bsim/bluetooth/host/iso/cis/src/cis_peripheral.c
+++ b/tests/bsim/bluetooth/host/iso/cis/src/cis_peripheral.c
@@ -1,21 +1,31 @@
 /*
- * Copyright (c) 2023 Nordic Semiconductor
+ * Copyright (c) 2023-2025 Nordic Semiconductor
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <errno.h>
 #include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
 
-#include "babblekit/testcase.h"
-#include "babblekit/flags.h"
-#include "common.h"
-
+#include <zephyr/autoconf.h>
 #include <zephyr/bluetooth/bluetooth.h>
+#include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/iso.h>
+#include <zephyr/net_buf.h>
 #include <zephyr/sys/printk.h>
+#include <zephyr/sys/util.h>
 
 #include <testlib/conn.h>
 
+#include "babblekit/testcase.h"
+#include "babblekit/flags.h"
+#include "bstests.h"
+#include "common.h"
+
 extern enum bst_result_t bst_result;
 
 DEFINE_FLAG_STATIC(flag_data_received);
@@ -74,7 +84,16 @@ static void iso_recv(struct bt_iso_chan *chan, const struct bt_iso_recv_info *in
 
 static void iso_connected(struct bt_iso_chan *chan)
 {
+	const struct bt_iso_chan_path hci_path = {
+		.pid = BT_ISO_DATA_PATH_HCI,
+		.format = BT_HCI_CODING_FORMAT_TRANSPARENT,
+	};
+	int err;
+
 	printk("ISO Channel %p connected\n", chan);
+
+	err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_CTLR_TO_HOST, &hci_path);
+	TEST_ASSERT(err == 0, "Failed to set ISO data path: %d", err);
 }
 
 static void iso_disconnected(struct bt_iso_chan *chan, uint8_t reason)
@@ -101,7 +120,6 @@ static void init(void)
 {
 	static struct bt_iso_chan_io_qos iso_rx = {
 		.sdu = CONFIG_BT_ISO_TX_MTU,
-		.path = NULL,
 	};
 	static struct bt_iso_server iso_server = {
 #if defined(CONFIG_BT_SMP)
diff --git a/tests/bsim/bluetooth/host/iso/frag/prj.conf b/tests/bsim/bluetooth/host/iso/frag/prj.conf
index 827ce27ea2c..ef978548977 100644
--- a/tests/bsim/bluetooth/host/iso/frag/prj.conf
+++ b/tests/bsim/bluetooth/host/iso/frag/prj.conf
@@ -17,3 +17,4 @@ CONFIG_BT_ISO_LOG_LEVEL_DBG=y
 # Controller ISO configs
 CONFIG_BT_CTLR_ADV_ISO=y
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=20
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=12
diff --git a/tests/bsim/bluetooth/host/iso/frag/src/broadcaster.c b/tests/bsim/bluetooth/host/iso/frag/src/broadcaster.c
index cdc9d68acee..7688bb822d2 100644
--- a/tests/bsim/bluetooth/host/iso/frag/src/broadcaster.c
+++ b/tests/bsim/bluetooth/host/iso/frag/src/broadcaster.c
@@ -1,9 +1,10 @@
 /*
- * Copyright (c) 2024 Nordic Semiconductor
+ * Copyright (c) 2024-2025 Nordic Semiconductor
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/sys/byteorder.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/iso.h>
@@ -58,6 +59,15 @@ static int send_data(struct bt_iso_chan *chan, bool ts)
 
 static void iso_connected_cb(struct bt_iso_chan *chan)
 {
+	const struct bt_iso_chan_path hci_path = {
+		.pid = BT_ISO_DATA_PATH_HCI,
+		.format = BT_HCI_CODING_FORMAT_TRANSPARENT,
+	};
+	int err;
+
+	err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR, &hci_path);
+	TEST_ASSERT(err == 0, "Unable to setup ISO TX path: %d", err);
+
 	LOG_INF("ISO Channel %p connected", chan);
 
 	SET_FLAG(iso_connected);
@@ -155,7 +165,6 @@ static void init(void)
 		.sdu = CONFIG_BT_ISO_TX_MTU,
 		.phy = BT_GAP_LE_PHY_2M,
 		.rtn = 1,
-		.path = NULL,
 	};
 	static struct bt_iso_chan_qos iso_qos = {
 		.tx = &iso_tx,
diff --git a/tests/bsim/bluetooth/host/iso/frag_2/prj.conf b/tests/bsim/bluetooth/host/iso/frag_2/prj.conf
index 4ae63917a5d..5a7c5e2d33e 100644
--- a/tests/bsim/bluetooth/host/iso/frag_2/prj.conf
+++ b/tests/bsim/bluetooth/host/iso/frag_2/prj.conf
@@ -22,6 +22,7 @@ CONFIG_BT_ISO_RX_MTU=100
 # Controller ISO configs
 CONFIG_BT_CTLR_ADV_ISO=y
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=255
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=247
 CONFIG_BT_CTLR_ISO_TX_BUFFERS=10
 
 # Controller Extended Advertising configs
diff --git a/tests/bsim/bluetooth/host/iso/frag_2/src/broadcaster.c b/tests/bsim/bluetooth/host/iso/frag_2/src/broadcaster.c
index c5491a5520f..1850adcdd11 100644
--- a/tests/bsim/bluetooth/host/iso/frag_2/src/broadcaster.c
+++ b/tests/bsim/bluetooth/host/iso/frag_2/src/broadcaster.c
@@ -1,9 +1,10 @@
 /*
- * Copyright (c) 2024 Nordic Semiconductor
+ * Copyright (c) 2024-2025 Nordic Semiconductor
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/sys/byteorder.h>
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/iso.h>
@@ -57,6 +58,15 @@ static int send_data(struct bt_iso_chan *chan)
 
 static void iso_connected_cb(struct bt_iso_chan *chan)
 {
+	const struct bt_iso_chan_path hci_path = {
+		.pid = BT_ISO_DATA_PATH_HCI,
+		.format = BT_HCI_CODING_FORMAT_TRANSPARENT,
+	};
+	int err;
+
+	err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR, &hci_path);
+	TEST_ASSERT(err == 0, "Unable to setup ISO TX path: %d", err);
+
 	LOG_INF("ISO Channel %p connected", chan);
 
 	SET_FLAG(iso_connected);
@@ -152,7 +162,6 @@ static struct bt_iso_chan_io_qos iso_tx = {
 	.sdu = CONFIG_BT_ISO_TX_MTU,
 	.phy = BT_GAP_LE_PHY_2M,
 	.rtn = 1,
-	.path = NULL,
 };
 static struct bt_iso_chan_qos iso_qos = {
 	.tx = &iso_tx,
diff --git a/tests/bsim/bluetooth/host/l2cap/reassembly/dut/prj.conf b/tests/bsim/bluetooth/host/l2cap/reassembly/dut/prj.conf
index d913264f700..0ec3db7fd21 100644
--- a/tests/bsim/bluetooth/host/l2cap/reassembly/dut/prj.conf
+++ b/tests/bsim/bluetooth/host/l2cap/reassembly/dut/prj.conf
@@ -24,9 +24,28 @@ CONFIG_BT_AUTO_PHY_UPDATE=n
 CONFIG_BT_AUTO_DATA_LEN_UPDATE=n
 CONFIG_BT_GAP_AUTO_UPDATE_CONN_PARAMS=n
 
+# HCI Controller to Host data flow control across active connections
+CONFIG_BT_MAX_CONN=1
+
 # Since the test's purpose is to test for leaks in the ACL
 # RX buffer pool, it is a good idea to constrain said buffer
 # pool.
-CONFIG_BT_MAX_CONN=1
-CONFIG_BT_BUF_ACL_RX_COUNT_EXTRA=4
-CONFIG_BT_BUF_EVT_RX_COUNT=6
+
+# Simultaneous connection receiving one Rx buffer each plus one additional for
+# L2CAP recombination, if any, across these active connections.
+CONFIG_BT_BUF_ACL_RX_COUNT_EXTRA=1
+
+# Minimum EVT Rx buffers permitting reception of events (Number of Completed Packets or
+# disconnection complete etc.) while ACL RX buffers are busy
+CONFIG_BT_BUF_EVT_RX_COUNT=4
+
+# Minimum ACL TX buffers to ensure continuous transmission without skipping connection intervals
+CONFIG_BT_BUF_ACL_TX_COUNT=3
+
+# Minimum HCI Command TX buffers
+CONFIG_BT_BUF_CMD_TX_COUNT=1
+
+# If we don't define this, it will inherit
+# CONFIG_BT_BUF_ACL_TX_COUNT and fail a build assert that
+# expects >= 3.
+CONFIG_BT_L2CAP_TX_BUF_COUNT=3
diff --git a/tests/bsim/bluetooth/host/l2cap/reassembly/peer/prj.conf b/tests/bsim/bluetooth/host/l2cap/reassembly/peer/prj.conf
index b9f5e34727b..f3493edb4ef 100644
--- a/tests/bsim/bluetooth/host/l2cap/reassembly/peer/prj.conf
+++ b/tests/bsim/bluetooth/host/l2cap/reassembly/peer/prj.conf
@@ -3,17 +3,18 @@ CONFIG_ASSERT=y
 
 CONFIG_BT=y
 CONFIG_BT_HCI_RAW=y
+
 CONFIG_BT_MAX_CONN=1
 
-CONFIG_BT_BUF_CMD_TX_COUNT=10
 CONFIG_BT_BUF_ACL_TX_COUNT=20
+CONFIG_BT_BUF_EVT_RX_COUNT=21
 
-CONFIG_BT_BUF_ACL_RX_SIZE=255
 CONFIG_BT_BUF_CMD_TX_SIZE=255
 CONFIG_BT_BUF_EVT_DISCARDABLE_SIZE=255
 
 # Allow whole L2CAP PDUs to fit on-air
 CONFIG_BT_BUF_ACL_TX_SIZE=251
 CONFIG_BT_BUF_ACL_RX_SIZE=251
+
 CONFIG_BT_DATA_LEN_UPDATE=y
 CONFIG_BT_CTLR_DATA_LENGTH_MAX=251
diff --git a/tests/bsim/bluetooth/host/l2cap/reassembly/peer/src/peer.c b/tests/bsim/bluetooth/host/l2cap/reassembly/peer/src/peer.c
index dd9d0e77fb8..9311802658c 100644
--- a/tests/bsim/bluetooth/host/l2cap/reassembly/peer/src/peer.c
+++ b/tests/bsim/bluetooth/host/l2cap/reassembly/peer/src/peer.c
@@ -16,6 +16,7 @@
 #include <zephyr/bluetooth/hci_raw.h>
 #include <zephyr/bluetooth/hci_types.h>
 
+#include "common/hci_common_internal.h"
 #include "common/bt_str.h"
 
 #include "host/conn_internal.h"
@@ -45,7 +46,7 @@ DEFINE_FLAG(is_connected);
 static K_FIFO_DEFINE(rx_queue);
 
 #define CMD_BUF_SIZE MAX(BT_BUF_EVT_RX_SIZE, BT_BUF_CMD_TX_SIZE)
-NET_BUF_POOL_FIXED_DEFINE(hci_cmd_pool, CONFIG_BT_BUF_CMD_TX_COUNT,
+NET_BUF_POOL_FIXED_DEFINE(hci_cmd_pool, BT_BUF_CMD_TX_COUNT,
 			  CMD_BUF_SIZE, 8, NULL);
 
 #define MAX_CMD_COUNT 1
diff --git a/tests/bsim/bluetooth/host/l2cap/split/tester/prj.conf b/tests/bsim/bluetooth/host/l2cap/split/tester/prj.conf
index be8487976cc..068f8c0c064 100644
--- a/tests/bsim/bluetooth/host/l2cap/split/tester/prj.conf
+++ b/tests/bsim/bluetooth/host/l2cap/split/tester/prj.conf
@@ -5,8 +5,6 @@ CONFIG_BT=y
 CONFIG_BT_HCI_RAW=y
 CONFIG_BT_MAX_CONN=1
 
-CONFIG_BT_BUF_CMD_TX_COUNT=10
-
 CONFIG_BT_BUF_ACL_RX_SIZE=255
 CONFIG_BT_BUF_CMD_TX_SIZE=255
 CONFIG_BT_BUF_EVT_DISCARDABLE_SIZE=255
diff --git a/tests/bsim/bluetooth/host/l2cap/split/tester/src/main.c b/tests/bsim/bluetooth/host/l2cap/split/tester/src/main.c
index af3467948bc..1f53f254adf 100644
--- a/tests/bsim/bluetooth/host/l2cap/split/tester/src/main.c
+++ b/tests/bsim/bluetooth/host/l2cap/split/tester/src/main.c
@@ -16,6 +16,7 @@
 #include <zephyr/bluetooth/hci_raw.h>
 #include <zephyr/bluetooth/hci_types.h>
 
+#include "common/hci_common_internal.h"
 #include "common/bt_str.h"
 
 #include "host/conn_internal.h"
@@ -36,7 +37,7 @@ DEFINE_FLAG_STATIC(flag_data_length_updated);
 static K_FIFO_DEFINE(rx_queue);
 
 #define CMD_BUF_SIZE MAX(BT_BUF_EVT_RX_SIZE, BT_BUF_CMD_TX_SIZE)
-NET_BUF_POOL_FIXED_DEFINE(hci_cmd_pool, CONFIG_BT_BUF_CMD_TX_COUNT,
+NET_BUF_POOL_FIXED_DEFINE(hci_cmd_pool, BT_BUF_CMD_TX_COUNT,
 			  CMD_BUF_SIZE, 8, NULL);
 
 static K_SEM_DEFINE(cmd_sem, 1, 1);
diff --git a/tests/bsim/bluetooth/host/misc/disconnect/tester/prj.conf b/tests/bsim/bluetooth/host/misc/disconnect/tester/prj.conf
index 5217040a117..e8ba462aeea 100644
--- a/tests/bsim/bluetooth/host/misc/disconnect/tester/prj.conf
+++ b/tests/bsim/bluetooth/host/misc/disconnect/tester/prj.conf
@@ -5,8 +5,6 @@ CONFIG_BT=y
 CONFIG_BT_HCI_RAW=y
 CONFIG_BT_MAX_CONN=1
 
-CONFIG_BT_BUF_CMD_TX_COUNT=10
-
 CONFIG_BT_BUF_ACL_RX_SIZE=255
 CONFIG_BT_BUF_CMD_TX_SIZE=255
 CONFIG_BT_BUF_EVT_DISCARDABLE_SIZE=255
diff --git a/tests/bsim/bluetooth/host/misc/disconnect/tester/src/main.c b/tests/bsim/bluetooth/host/misc/disconnect/tester/src/main.c
index 48923faa980..64ef9676d0b 100644
--- a/tests/bsim/bluetooth/host/misc/disconnect/tester/src/main.c
+++ b/tests/bsim/bluetooth/host/misc/disconnect/tester/src/main.c
@@ -5,6 +5,7 @@
  */
 
 #include <zephyr/kernel.h>
+#include <zephyr/sys/util.h>
 #include <zephyr/sys/byteorder.h>
 #include <zephyr/sys/__assert.h>
 
@@ -16,6 +17,7 @@
 #include <zephyr/bluetooth/hci_raw.h>
 #include <zephyr/bluetooth/hci_types.h>
 
+#include "common/hci_common_internal.h"
 #include "common/bt_str.h"
 
 #include "host/conn_internal.h"
@@ -47,7 +49,7 @@ DEFINE_FLAG_STATIC(flag_data_length_updated);
 static K_FIFO_DEFINE(rx_queue);
 
 #define CMD_BUF_SIZE MAX(BT_BUF_EVT_RX_SIZE, BT_BUF_CMD_TX_SIZE)
-NET_BUF_POOL_FIXED_DEFINE(hci_cmd_pool, CONFIG_BT_BUF_CMD_TX_COUNT,
+NET_BUF_POOL_FIXED_DEFINE(hci_cmd_pool, BT_BUF_CMD_TX_COUNT,
 			  CMD_BUF_SIZE, 8, NULL);
 
 static K_SEM_DEFINE(cmd_sem, 1, 1);
@@ -190,8 +192,7 @@ static void handle_att_write(struct net_buf *buf)
 
 	static uint8_t ccc_write[2] = {0x03, 0x00};
 
-	TEST_ASSERT(buf->len == 2, "unexpected write length: %d", buf->len);
-	TEST_ASSERT(memcmp(buf->data, ccc_write, sizeof(ccc_write)) == 0, "bad data");
+	TEST_ASSERT(util_eq(buf->data, buf->len, ccc_write, sizeof(ccc_write)), "bad data\n");
 
 	send_write_rsp();
 }
diff --git a/tests/bsim/bluetooth/host/misc/hfc/Kconfig.sysbuild b/tests/bsim/bluetooth/host/misc/hfc/Kconfig.sysbuild
new file mode 100644
index 00000000000..79d8f991960
--- /dev/null
+++ b/tests/bsim/bluetooth/host/misc/hfc/Kconfig.sysbuild
@@ -0,0 +1,14 @@
+# Copyright 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+source "share/sysbuild/Kconfig"
+
+config NET_CORE_BOARD
+	string
+	default "nrf5340bsim/nrf5340/cpunet" if $(BOARD_TARGET_STRING) = "NRF5340BSIM_NRF5340_CPUAPP"
+
+config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX
+	int
+	# Let's pass the test arguments to the application MCU test
+	# otherwise by default they would have gone to the net core.
+	default 0 if $(BOARD_TARGET_STRING) = "NRF5340BSIM_NRF5340_CPUAPP"
diff --git a/tests/bsim/bluetooth/host/misc/hfc/nrf5340_cpunet-bt_ll_sw_split.conf b/tests/bsim/bluetooth/host/misc/hfc/nrf5340_cpunet-bt_ll_sw_split.conf
new file mode 100644
index 00000000000..8af16f7c1bb
--- /dev/null
+++ b/tests/bsim/bluetooth/host/misc/hfc/nrf5340_cpunet-bt_ll_sw_split.conf
@@ -0,0 +1,21 @@
+CONFIG_IPC_SERVICE=y
+CONFIG_MBOX=y
+CONFIG_ISR_STACK_SIZE=1024
+CONFIG_IDLE_STACK_SIZE=256
+CONFIG_MAIN_STACK_SIZE=512
+CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=512
+CONFIG_IPC_SERVICE_BACKEND_RPMSG_WQ_STACK_SIZE=512
+CONFIG_HEAP_MEM_POOL_SIZE=4096
+CONFIG_CBPRINTF_REDUCED_INTEGRAL=y
+CONFIG_ISR_TABLES_LOCAL_DECLARATION=y
+
+CONFIG_BT=y
+CONFIG_BT_HCI_RAW=y
+CONFIG_BT_MAX_CONN=1
+
+# Controller
+CONFIG_BT_LL_SW_SPLIT=y
+CONFIG_BT_CTLR_ASSERT_HANDLER=y
+
+CONFIG_BT_BUF_EVT_RX_COUNT=4
+CONFIG_BT_BUF_ACL_TX_COUNT=3
diff --git a/tests/bsim/bluetooth/host/misc/hfc/prj.conf b/tests/bsim/bluetooth/host/misc/hfc/prj.conf
index ee754878191..d8854bb3c69 100644
--- a/tests/bsim/bluetooth/host/misc/hfc/prj.conf
+++ b/tests/bsim/bluetooth/host/misc/hfc/prj.conf
@@ -16,7 +16,23 @@ CONFIG_ASSERT=y
 CONFIG_BT_TESTING=y
 CONFIG_LOG=y
 
-CONFIG_BT_MAX_CONN=3
+# HCI Controller to Host data flow control across active connections
+CONFIG_BT_MAX_CONN=1
+
+# Simultaneous connection receiving one Rx buffer each plus one additional for
+# L2CAP recombination, if any, across these active connections.
+CONFIG_BT_BUF_ACL_RX_COUNT_EXTRA=1
+
+# Minimum EVT Rx buffers permitting reception of events (Number of Completed Packets or
+# disconnection complete etc.) while ACL RX buffers are busy
+CONFIG_BT_BUF_EVT_RX_COUNT=4
+
+# Minimum ACL TX buffers to ensure continuous transmission without skipping connection intervals
+CONFIG_BT_BUF_ACL_TX_COUNT=3
+
+# Minimum HCI Command TX buffers
+CONFIG_BT_BUF_CMD_TX_COUNT=1
+
 CONFIG_ARCH_POSIX_TRAP_ON_FATAL=y
 # CONFIG_BT_CONN_LOG_LEVEL_DBG=y
 
diff --git a/tests/bsim/bluetooth/host/misc/hfc/src/main.c b/tests/bsim/bluetooth/host/misc/hfc/src/main.c
index 1cb5f32091b..47ce23dbcf4 100644
--- a/tests/bsim/bluetooth/host/misc/hfc/src/main.c
+++ b/tests/bsim/bluetooth/host/misc/hfc/src/main.c
@@ -376,10 +376,11 @@ static void entrypoint_peer(void)
 
 	tx = 0;
 	while (true) {
+		UNSET_FLAG(is_subscribed);
+
 		conn = connect_as_peripheral();
 
 		LOG_INF("wait until DUT subscribes");
-		UNSET_FLAG(is_subscribed);
 		WAIT_FOR_FLAG(is_subscribed);
 
 		LOG_INF("send notifications");
diff --git a/tests/bsim/bluetooth/host/misc/hfc/sysbuild.cmake b/tests/bsim/bluetooth/host/misc/hfc/sysbuild.cmake
new file mode 100644
index 00000000000..38b24316936
--- /dev/null
+++ b/tests/bsim/bluetooth/host/misc/hfc/sysbuild.cmake
@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT("${SB_CONFIG_NET_CORE_BOARD}" STREQUAL ""))
+	set(NET_APP hci_ipc)
+	set(NET_APP_SRC_DIR ${ZEPHYR_BASE}/samples/bluetooth/${NET_APP})
+
+	ExternalZephyrProject_Add(
+		APPLICATION ${NET_APP}
+		SOURCE_DIR  ${NET_APP_SRC_DIR}
+		BOARD       ${SB_CONFIG_NET_CORE_BOARD}
+	)
+
+	set(${NET_APP}_CONF_FILE ${APP_DIR}/nrf5340_cpunet-bt_ll_sw_split.conf CACHE INTERNAL "")
+
+	native_simulator_set_primary_mcu_index(${DEFAULT_IMAGE} ${NET_APP})
+	native_simulator_set_child_images(${DEFAULT_IMAGE} ${NET_APP})
+endif()
+
+native_simulator_set_final_executable(${DEFAULT_IMAGE})
diff --git a/tests/bsim/bluetooth/host/misc/hfc/testcase.yaml b/tests/bsim/bluetooth/host/misc/hfc/testcase.yaml
index b8d24f8d18f..b584f78ef24 100644
--- a/tests/bsim/bluetooth/host/misc/hfc/testcase.yaml
+++ b/tests/bsim/bluetooth/host/misc/hfc/testcase.yaml
@@ -1,10 +1,12 @@
 tests:
   bluetooth.host.mics.hfc:
     build_only: true
+    sysbuild: true
     tags:
       - bluetooth
     platform_allow:
       - nrf52_bsim/native
+      - nrf5340bsim/nrf5340/cpuapp
     harness: bsim
     harness_config:
       bsim_exe_name: tests_bsim_bluetooth_host_misc_hfc_prj_conf
diff --git a/tests/bsim/bluetooth/host/misc/hfc_multilink/dut/Kconfig.sysbuild b/tests/bsim/bluetooth/host/misc/hfc_multilink/dut/Kconfig.sysbuild
new file mode 100644
index 00000000000..79d8f991960
--- /dev/null
+++ b/tests/bsim/bluetooth/host/misc/hfc_multilink/dut/Kconfig.sysbuild
@@ -0,0 +1,14 @@
+# Copyright 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+source "share/sysbuild/Kconfig"
+
+config NET_CORE_BOARD
+	string
+	default "nrf5340bsim/nrf5340/cpunet" if $(BOARD_TARGET_STRING) = "NRF5340BSIM_NRF5340_CPUAPP"
+
+config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX
+	int
+	# Let's pass the test arguments to the application MCU test
+	# otherwise by default they would have gone to the net core.
+	default 0 if $(BOARD_TARGET_STRING) = "NRF5340BSIM_NRF5340_CPUAPP"
diff --git a/tests/bsim/bluetooth/host/misc/hfc_multilink/dut/nrf5340_cpunet-bt_ll_sw_split.conf b/tests/bsim/bluetooth/host/misc/hfc_multilink/dut/nrf5340_cpunet-bt_ll_sw_split.conf
new file mode 100644
index 00000000000..5f45c3c8856
--- /dev/null
+++ b/tests/bsim/bluetooth/host/misc/hfc_multilink/dut/nrf5340_cpunet-bt_ll_sw_split.conf
@@ -0,0 +1,24 @@
+CONFIG_IPC_SERVICE=y
+CONFIG_MBOX=y
+
+CONFIG_ISR_STACK_SIZE=1024
+CONFIG_IDLE_STACK_SIZE=256
+CONFIG_MAIN_STACK_SIZE=512
+CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=512
+CONFIG_IPC_SERVICE_BACKEND_RPMSG_WQ_STACK_SIZE=512
+CONFIG_HEAP_MEM_POOL_SIZE=8192
+CONFIG_CBPRINTF_REDUCED_INTEGRAL=y
+
+CONFIG_ISR_TABLES_LOCAL_DECLARATION=y
+CONFIG_LTO=y
+
+CONFIG_BT=y
+CONFIG_BT_HCI_RAW=y
+CONFIG_BT_MAX_CONN=3
+
+# Host features
+CONFIG_BT_EXT_ADV=y
+
+# Controller
+CONFIG_BT_LL_SW_SPLIT=y
+CONFIG_BT_CTLR_ASSERT_HANDLER=y
diff --git a/tests/bsim/bluetooth/host/misc/hfc_multilink/dut/sysbuild.cmake b/tests/bsim/bluetooth/host/misc/hfc_multilink/dut/sysbuild.cmake
new file mode 100644
index 00000000000..38b24316936
--- /dev/null
+++ b/tests/bsim/bluetooth/host/misc/hfc_multilink/dut/sysbuild.cmake
@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT("${SB_CONFIG_NET_CORE_BOARD}" STREQUAL ""))
+	set(NET_APP hci_ipc)
+	set(NET_APP_SRC_DIR ${ZEPHYR_BASE}/samples/bluetooth/${NET_APP})
+
+	ExternalZephyrProject_Add(
+		APPLICATION ${NET_APP}
+		SOURCE_DIR  ${NET_APP_SRC_DIR}
+		BOARD       ${SB_CONFIG_NET_CORE_BOARD}
+	)
+
+	set(${NET_APP}_CONF_FILE ${APP_DIR}/nrf5340_cpunet-bt_ll_sw_split.conf CACHE INTERNAL "")
+
+	native_simulator_set_primary_mcu_index(${DEFAULT_IMAGE} ${NET_APP})
+	native_simulator_set_child_images(${DEFAULT_IMAGE} ${NET_APP})
+endif()
+
+native_simulator_set_final_executable(${DEFAULT_IMAGE})
diff --git a/tests/bsim/bluetooth/host/misc/hfc_multilink/dut/testcase.yaml b/tests/bsim/bluetooth/host/misc/hfc_multilink/dut/testcase.yaml
index 2cb24db1258..2cefbebb87b 100644
--- a/tests/bsim/bluetooth/host/misc/hfc_multilink/dut/testcase.yaml
+++ b/tests/bsim/bluetooth/host/misc/hfc_multilink/dut/testcase.yaml
@@ -1,10 +1,12 @@
 tests:
   bluetooth.host.misc.hfc_multilink.dut:
     build_only: true
+    sysbuild: true
     tags:
       - bluetooth
     platform_allow:
       - nrf52_bsim/native
+      - nrf5340bsim/nrf5340/cpuapp
     harness: bsim
     harness_config:
       bsim_exe_name: tests_bsim_bluetooth_host_misc_hfc_multilink_dut_prj_conf
diff --git a/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/Kconfig.sysbuild b/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/Kconfig.sysbuild
new file mode 100644
index 00000000000..79d8f991960
--- /dev/null
+++ b/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/Kconfig.sysbuild
@@ -0,0 +1,14 @@
+# Copyright 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+source "share/sysbuild/Kconfig"
+
+config NET_CORE_BOARD
+	string
+	default "nrf5340bsim/nrf5340/cpunet" if $(BOARD_TARGET_STRING) = "NRF5340BSIM_NRF5340_CPUAPP"
+
+config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX
+	int
+	# Let's pass the test arguments to the application MCU test
+	# otherwise by default they would have gone to the net core.
+	default 0 if $(BOARD_TARGET_STRING) = "NRF5340BSIM_NRF5340_CPUAPP"
diff --git a/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/nrf5340_cpunet-bt_ll_sw_split.conf b/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/nrf5340_cpunet-bt_ll_sw_split.conf
new file mode 100644
index 00000000000..6f0462852d5
--- /dev/null
+++ b/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/nrf5340_cpunet-bt_ll_sw_split.conf
@@ -0,0 +1,28 @@
+CONFIG_IPC_SERVICE=y
+CONFIG_MBOX=y
+
+CONFIG_ISR_STACK_SIZE=1024
+CONFIG_IDLE_STACK_SIZE=256
+CONFIG_MAIN_STACK_SIZE=512
+CONFIG_SYSTEM_WORKQUEUE_STACK_SIZE=512
+CONFIG_IPC_SERVICE_BACKEND_RPMSG_WQ_STACK_SIZE=512
+CONFIG_HEAP_MEM_POOL_SIZE=8192
+CONFIG_CBPRINTF_REDUCED_INTEGRAL=y
+
+CONFIG_ISR_TABLES_LOCAL_DECLARATION=y
+CONFIG_LTO=y
+
+CONFIG_BT=y
+CONFIG_BT_HCI_RAW=y
+CONFIG_BT_MAX_CONN=1
+
+# Host features
+CONFIG_BT_EXT_ADV=y
+
+# Controller
+CONFIG_BT_LL_SW_SPLIT=y
+CONFIG_BT_CTLR_ASSERT_HANDLER=y
+
+CONFIG_BT_BUF_ACL_RX_SIZE=255
+CONFIG_BT_BUF_CMD_TX_SIZE=255
+CONFIG_BT_BUF_EVT_DISCARDABLE_SIZE=255
diff --git a/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/prj.conf b/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/prj.conf
index a4d8875e92c..44e2b46cb1d 100644
--- a/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/prj.conf
+++ b/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/prj.conf
@@ -5,8 +5,6 @@ CONFIG_BT=y
 CONFIG_BT_HCI_RAW=y
 CONFIG_BT_MAX_CONN=1
 
-CONFIG_BT_BUF_CMD_TX_COUNT=10
-
 CONFIG_BT_BUF_ACL_RX_SIZE=255
 CONFIG_BT_BUF_CMD_TX_SIZE=255
 CONFIG_BT_BUF_EVT_DISCARDABLE_SIZE=255
diff --git a/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/src/tester.c b/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/src/tester.c
index b5054cfdc3f..9e7f4c19d00 100644
--- a/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/src/tester.c
+++ b/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/src/tester.c
@@ -17,6 +17,7 @@
 #include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/gap.h>
 
+#include "common/hci_common_internal.h"
 #include "common/bt_str.h"
 
 #include "host/conn_internal.h"
@@ -38,7 +39,7 @@ DEFINE_FLAG(flag_l2cap_connected);
 static K_FIFO_DEFINE(rx_queue);
 
 #define CMD_BUF_SIZE MAX(BT_BUF_EVT_RX_SIZE, BT_BUF_CMD_TX_SIZE)
-NET_BUF_POOL_FIXED_DEFINE(hci_cmd_pool, CONFIG_BT_BUF_CMD_TX_COUNT, CMD_BUF_SIZE, 8, NULL);
+NET_BUF_POOL_FIXED_DEFINE(hci_cmd_pool, BT_BUF_CMD_TX_COUNT, CMD_BUF_SIZE, 8, NULL);
 
 static K_SEM_DEFINE(cmd_sem, 1, 1);
 static struct k_sem acl_pkts;
diff --git a/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/sysbuild.cmake b/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/sysbuild.cmake
new file mode 100644
index 00000000000..38b24316936
--- /dev/null
+++ b/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/sysbuild.cmake
@@ -0,0 +1,20 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT("${SB_CONFIG_NET_CORE_BOARD}" STREQUAL ""))
+	set(NET_APP hci_ipc)
+	set(NET_APP_SRC_DIR ${ZEPHYR_BASE}/samples/bluetooth/${NET_APP})
+
+	ExternalZephyrProject_Add(
+		APPLICATION ${NET_APP}
+		SOURCE_DIR  ${NET_APP_SRC_DIR}
+		BOARD       ${SB_CONFIG_NET_CORE_BOARD}
+	)
+
+	set(${NET_APP}_CONF_FILE ${APP_DIR}/nrf5340_cpunet-bt_ll_sw_split.conf CACHE INTERNAL "")
+
+	native_simulator_set_primary_mcu_index(${DEFAULT_IMAGE} ${NET_APP})
+	native_simulator_set_child_images(${DEFAULT_IMAGE} ${NET_APP})
+endif()
+
+native_simulator_set_final_executable(${DEFAULT_IMAGE})
diff --git a/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/testcase.yaml b/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/testcase.yaml
index b9dd7b87913..a62076ecfdc 100644
--- a/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/testcase.yaml
+++ b/tests/bsim/bluetooth/host/misc/hfc_multilink/tester/testcase.yaml
@@ -1,10 +1,12 @@
 tests:
   bluetooth.host.misc.hfc_multilink.tester:
     build_only: true
+    sysbuild: true
     tags:
       - bluetooth
     platform_allow:
       - nrf52_bsim/native
+      - nrf5340bsim/nrf5340/cpuapp
     harness: bsim
     harness_config:
       bsim_exe_name: tests_bsim_bluetooth_host_misc_hfc_multilink_tester_prj_conf
diff --git a/tests/bsim/bluetooth/host/security/ccc_update/overlay-no_long_wq.conf b/tests/bsim/bluetooth/host/security/ccc_update/overlay-no_long_wq.conf
new file mode 100644
index 00000000000..baebf9ca980
--- /dev/null
+++ b/tests/bsim/bluetooth/host/security/ccc_update/overlay-no_long_wq.conf
@@ -0,0 +1,2 @@
+# Disable the dedicated workqueue for long-running tasks.
+CONFIG_BT_LONG_WQ=n
diff --git a/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update_no_lazy_load.sh b/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update_no_lazy_load.sh
index 90a089f34a5..7dcda55ce49 100755
--- a/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update_no_lazy_load.sh
+++ b/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update_no_lazy_load.sh
@@ -6,7 +6,7 @@ source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
 
 test_name='ccc_update'
 test_exe="bs_${BOARD_TS}_tests_bsim_bluetooth_host_security_${test_name}_overlay-no_lazy_load_conf"
-simulation_id="${test_name}_2"
+simulation_id="${test_name}_no_lazy_load"
 verbosity_level=2
 
 cd ${BSIM_OUT_PATH}/bin
diff --git a/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update_no_long_wq.sh b/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update_no_long_wq.sh
new file mode 100755
index 00000000000..425494e4294
--- /dev/null
+++ b/tests/bsim/bluetooth/host/security/ccc_update/test_scripts/ccc_update_no_long_wq.sh
@@ -0,0 +1,53 @@
+#!/usr/bin/env bash
+# Copyright 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
+
+test_name='ccc_update'
+test_exe="bs_${BOARD_TS}_tests_bsim_bluetooth_host_security_${test_name}_overlay-no_long_wq_conf"
+simulation_id="${test_name}_no_long_wq"
+verbosity_level=2
+
+cd ${BSIM_OUT_PATH}/bin
+
+if [ "${1}" != 'debug0' ]; then
+  Execute "./${test_exe}" \
+    -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central \
+    -flash="${simulation_id}_client.log.bin" -flash_rm -RealEncryption=1
+fi
+
+if [ "${1}" != 'debug1' ]; then
+  Execute "./${test_exe}" \
+    -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=bad_central \
+    -flash="${simulation_id}_bad_client.log.bin" -flash_rm -RealEncryption=1
+fi
+
+if [ "${1}" != 'debug2' ]; then
+  Execute "./${test_exe}" \
+    -v=${verbosity_level} -s=${simulation_id} -d=2 -testid=peripheral \
+    -flash="${simulation_id}_server.log.bin" -flash_rm -RealEncryption=1
+fi
+
+Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \
+  -D=3 -sim_length=60e6
+
+if [ "${1}" == 'debug0' ]; then
+  gdb --args "./${test_exe}" \
+    -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central \
+    -flash="${simulation_id}_client.log.bin" -flash_rm -RealEncryption=1
+fi
+
+if [ "${1}" == 'debug1' ]; then
+  gdb --args "./${test_exe}" \
+    -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=bad_central \
+    -flash="${simulation_id}_bad_client.log.bin" -flash_rm -RealEncryption=1
+fi
+
+if [ "${1}" == 'debug2' ]; then
+  gdb --args "./${test_exe}" \
+    -v=${verbosity_level} -s=${simulation_id} -d=2 -testid=peripheral \
+    -flash="${simulation_id}_server.log.bin" -flash_rm -RealEncryption=1
+fi
+
+wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/host/security/ccc_update/testcase.yaml b/tests/bsim/bluetooth/host/security/ccc_update/testcase.yaml
index 909439ab9ab..de003130584 100644
--- a/tests/bsim/bluetooth/host/security/ccc_update/testcase.yaml
+++ b/tests/bsim/bluetooth/host/security/ccc_update/testcase.yaml
@@ -10,8 +10,13 @@ tests:
   bluetooth.host.security.ccc_update:
     harness_config:
       bsim_exe_name: tests_bsim_bluetooth_host_security_ccc_update_prj_conf
-  bluetooth.host.security.ccc_update_2:
+  bluetooth.host.security.ccc_update_no_lazy_load:
     harness_config:
       bsim_exe_name: tests_bsim_bluetooth_host_security_ccc_update_overlay-no_lazy_load_conf
     extra_args:
       EXTRA_CONF_FILE=overlay-no_lazy_load.conf
+  bluetooth.host.security.ccc_update_no_long_wq:
+    harness_config:
+      bsim_exe_name: tests_bsim_bluetooth_host_security_ccc_update_overlay-no_long_wq_conf
+    extra_args:
+      EXTRA_CONF_FILE=overlay-no_long_wq.conf
diff --git a/tests/bsim/bluetooth/ll/bis/Kconfig b/tests/bsim/bluetooth/ll/bis/Kconfig
index 3e7fd07e430..4d5df8144f5 100644
--- a/tests/bsim/bluetooth/ll/bis/Kconfig
+++ b/tests/bsim/bluetooth/ll/bis/Kconfig
@@ -1,4 +1,4 @@
-# Copyright 2024 Nordic Semiconductor ASA
+# Copyright (c) 2024 Nordic Semiconductor ASA
 # SPDX-License-Identifier: Apache-2.0
 
 config TEST_LL_INTERFACE
@@ -6,6 +6,13 @@ config TEST_LL_INTERFACE
 	help
 	  Test Broadcast ISO using internal LL interface.
 
+config TEST_ISO_PACKING_INTERLEAVED
+	bool "Test ISO interleaved packing"
+	help
+	  Test ISO interleaved packing. Note, this tests with single BIS to
+	  ensure that using sequential or interleaved packing to create the BIS
+	  still is valid when creating single BIS in a BIG.
+
 menu "Zephyr Kernel"
 source "Kconfig.zephyr"
 endmenu
diff --git a/tests/bsim/bluetooth/ll/bis/overlay-interleaved.conf b/tests/bsim/bluetooth/ll/bis/overlay-interleaved.conf
new file mode 100644
index 00000000000..f0856d67fce
--- /dev/null
+++ b/tests/bsim/bluetooth/ll/bis/overlay-interleaved.conf
@@ -0,0 +1,2 @@
+CONFIG_BT_CTLR_ADV_ISO_INTERLEAVED=y
+CONFIG_TEST_ISO_PACKING_INTERLEAVED=y
diff --git a/tests/bsim/bluetooth/ll/bis/overlay-sequential.conf b/tests/bsim/bluetooth/ll/bis/overlay-sequential.conf
new file mode 100644
index 00000000000..a301763277a
--- /dev/null
+++ b/tests/bsim/bluetooth/ll/bis/overlay-sequential.conf
@@ -0,0 +1 @@
+CONFIG_TEST_ISO_PACKING_INTERLEAVED=n
diff --git a/tests/bsim/bluetooth/ll/bis/prj.conf b/tests/bsim/bluetooth/ll/bis/prj.conf
index 48d07dfc695..21239521a56 100644
--- a/tests/bsim/bluetooth/ll/bis/prj.conf
+++ b/tests/bsim/bluetooth/ll/bis/prj.conf
@@ -17,6 +17,7 @@ CONFIG_BT_CTLR_SYNC_ISO=y
 
 CONFIG_BT_CTLR_ISO_TX_BUFFERS=2
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=255
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=247
 CONFIG_BT_CTLR_ADV_ISO_PDU_LEN_MAX=247
 CONFIG_BT_CTLR_SYNC_ISO_PDU_LEN_MAX=251
 
diff --git a/tests/bsim/bluetooth/ll/bis/prj_vs_dp.conf b/tests/bsim/bluetooth/ll/bis/prj_vs_dp.conf
index 4bf19777993..59bb4623195 100644
--- a/tests/bsim/bluetooth/ll/bis/prj_vs_dp.conf
+++ b/tests/bsim/bluetooth/ll/bis/prj_vs_dp.conf
@@ -16,6 +16,7 @@ CONFIG_BT_CTLR_ADV_ISO=y
 CONFIG_BT_CTLR_SYNC_ISO=y
 
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=255
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=247
 CONFIG_BT_CTLR_ADV_ISO_PDU_LEN_MAX=251
 CONFIG_BT_CTLR_SYNC_ISO_PDU_LEN_MAX=251
 
diff --git a/tests/bsim/bluetooth/ll/bis/src/test_bis.c b/tests/bsim/bluetooth/ll/bis/src/test_bis.c
index 3b2b1a001c2..97c44e78e53 100644
--- a/tests/bsim/bluetooth/ll/bis/src/test_bis.c
+++ b/tests/bsim/bluetooth/ll/bis/src/test_bis.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020 Nordic Semiconductor ASA
+ * Copyright (c) 2020-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,6 +12,7 @@
 
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/hci.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/iso.h>
 
 #include "subsys/bluetooth/host/hci_core.h"
@@ -71,14 +72,12 @@ static struct bt_iso_chan_ops iso_ops = {
 	.recv		= iso_recv,
 };
 
-static struct bt_iso_chan_path iso_path_rx = {
-	.pid = BT_HCI_DATAPATH_ID_HCI
-};
-
 static struct bt_iso_chan_qos bis_iso_qos;
 static struct bt_iso_chan_io_qos iso_tx_qos;
-static struct bt_iso_chan_io_qos iso_rx_qos = {
-	.path = &iso_path_rx
+static struct bt_iso_chan_io_qos iso_rx_qos;
+static struct bt_iso_chan_path hci_path = {
+	.pid = BT_HCI_DATAPATH_ID_HCI,
+	.format = BT_HCI_CODING_FORMAT_TRANSPARENT,
 };
 
 static struct bt_iso_chan bis_iso_chan = {
@@ -149,7 +148,14 @@ bool ll_data_path_sink_create(uint16_t handle, struct ll_iso_datapath *datapath,
 }
 #endif /* CONFIG_BT_CTLR_ISO_VENDOR_DATA_PATH */
 
-#define BUF_ALLOC_TIMEOUT_MS (30) /* milliseconds */
+/* Have timeout unit sufficient to wait for all enqueued SDU to be transmitted.
+ * We retry allocation by yielding out of the system work queue to mitigate
+ * deadlock.
+ */
+#define BUF_ALLOC_TIMEOUT_MS       (10)   /* milliseconds */
+#define BUF_ALLOC_RETRY_TIMEOUT_US (1000) /* microseconds */
+#define BUF_ALLOC_RETRY_COUNT      (10U)
+
 NET_BUF_POOL_FIXED_DEFINE(tx_pool, CONFIG_BT_ISO_TX_BUF_COUNT,
 			  BT_ISO_SDU_BUF_SIZE(CONFIG_BT_ISO_TX_MTU),
 			  CONFIG_BT_CONN_TX_USER_DATA_SIZE, NULL);
@@ -162,6 +168,7 @@ static void iso_send(struct k_work *work)
 {
 	static uint8_t iso_data[CONFIG_BT_ISO_TX_MTU];
 	static bool data_initialized;
+	static uint8_t retry_yield_wq;
 	struct net_buf *buf;
 	size_t iso_data_len;
 	int ret;
@@ -176,10 +183,22 @@ static void iso_send(struct k_work *work)
 
 	buf = net_buf_alloc(&tx_pool, K_MSEC(BUF_ALLOC_TIMEOUT_MS));
 	if (!buf) {
-		FAIL("Data buffer allocate timeout on channel\n");
+		/* Blocking in system work qeueue causes deadlock, hence yield
+		 * and try getting the buffer again.
+		 */
+		if (retry_yield_wq) {
+			retry_yield_wq--;
+
+			k_work_schedule(&iso_send_work, K_USEC(BUF_ALLOC_RETRY_TIMEOUT_US));
+		} else {
+			FAIL("Data buffer allocate timeout on channel\n");
+		}
+
 		return;
 	}
 
+	retry_yield_wq = BUF_ALLOC_RETRY_COUNT;
+
 	net_buf_reserve(buf, BT_ISO_CHAN_SEND_RESERVE);
 	sys_put_le16(seq_num, iso_data);
 	iso_data_len = MAX(sizeof(seq_num), ((seq_num % CONFIG_BT_ISO_TX_MTU) + 1));
@@ -193,7 +212,17 @@ static void iso_send(struct k_work *work)
 		return;
 	}
 
-	k_work_schedule(&iso_send_work, K_USEC(9970));
+	/* Ideally we can wait 10 ms to enqueue next SDU, but to mitigate clock
+	 * drift between OS clock and Bluetooth Sleep Clock, lets send/enqueue
+	 * early towards the Controller so that the SDU is not considered stale
+	 * by the Controller.
+	 *
+	 * As we use `net_buf_alloc()` which will indirectly wait for Number of
+	 * Completed Packet event processing in the Host leading to availability
+	 * of next buffer, sending early will eventually get sync-ed with the
+	 * interval at which the Controller is sending the SDU on-air.
+	 */
+	k_work_schedule(&iso_send_work, K_USEC(9900));
 }
 #endif /* !CONFIG_TEST_LL_INTERFACE */
 
@@ -319,7 +348,9 @@ static void create_big(struct bt_le_ext_adv *adv, struct bt_iso_big **big)
 	big_create_param.encryption = false;
 	big_create_param.interval = 10000; /* us */
 	big_create_param.latency = 10; /* milliseconds */
-	big_create_param.packing = 0; /* 0 - sequential; 1 - interleaved */
+	big_create_param.packing = (IS_ENABLED(CONFIG_TEST_ISO_PACKING_INTERLEAVED) ?
+				    BT_ISO_PACKING_INTERLEAVED :
+				    BT_ISO_PACKING_SEQUENTIAL);
 	big_create_param.framing = 0; /* 0 - unframed; 1 - framed */
 	iso_tx_qos.sdu = CONFIG_BT_ISO_TX_MTU; /* bytes */
 	iso_tx_qos.rtn = 2;
@@ -579,10 +610,34 @@ static void iso_recv(struct bt_iso_chan *chan,
 
 static void iso_connected(struct bt_iso_chan *chan)
 {
+	struct bt_iso_info iso_info;
+	int err;
+
 	printk("ISO Channel %p connected\n", chan);
 
 	seq_num = 0U;
 	is_iso_connected = true;
+
+	err = bt_iso_chan_get_info(chan, &iso_info);
+	if (err != 0) {
+		FAIL("Failed to get ISO info: %d\n", err);
+	} else {
+		if (iso_info.can_recv) {
+			err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_CTLR_TO_HOST,
+						     &hci_path);
+			if (err != 0) {
+				FAIL("Failed to setup ISO RX data path: %d\n", err);
+			}
+		}
+
+		if (iso_info.can_send) {
+			err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR,
+						     &hci_path);
+			if (err != 0) {
+				FAIL("Failed to setup ISO TX data path: %d\n", err);
+			}
+		}
+	}
 }
 
 static void iso_disconnected(struct bt_iso_chan *chan, uint8_t reason)
@@ -846,6 +901,7 @@ static void test_iso_recv_main(void)
 	k_sleep(K_MSEC(5000));
 
 	printk("Terminating BIG Sync...");
+
 	struct node_rx_pdu *node_rx = NULL;
 
 	err = ll_big_sync_terminate(big_handle, (void **)&node_rx);
@@ -908,7 +964,7 @@ static void test_iso_recv_main(void)
 	big_param.mse = 1;
 	big_param.sync_timeout = 100; /* 1000 ms */
 	big_param.encryption = false;
-	iso_path_rx.pid = BT_HCI_DATAPATH_ID_HCI;
+	hci_path.pid = BT_HCI_DATAPATH_ID_HCI;
 	memset(big_param.bcode, 0, sizeof(big_param.bcode));
 	err = bt_iso_big_sync(sync, &big_param, &big);
 	if (err) {
@@ -1128,7 +1184,7 @@ static void test_iso_recv_vs_dp_main(void)
 	is_iso_connected = false;
 	is_iso_disconnected = 0U;
 	is_iso_vs_emitted = false;
-	iso_path_rx.pid = BT_HCI_DATAPATH_ID_VS;
+	hci_path.pid = BT_HCI_DATAPATH_ID_VS;
 
 	err = bt_iso_big_sync(sync, &big_param, &big);
 	if (err) {
diff --git a/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso.sh b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso.sh
deleted file mode 100755
index 97f8f4636c6..00000000000
--- a/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso.sh
+++ /dev/null
@@ -1,24 +0,0 @@
-#!/usr/bin/env bash
-# Copyright 2020 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
-
-# Basic ISO broadcast test: a broadcaster transmits a BIS and a receiver listens
-# to the BIS.
-simulation_id="broadcast_iso"
-verbosity_level=2
-EXECUTE_TIMEOUT=120
-
-cd ${BSIM_OUT_PATH}/bin
-
-Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_bis_prj_conf \
-  -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=receive
-
-Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_bis_prj_conf \
-  -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=broadcast
-
-Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \
-  -D=2 -sim_length=30e6 $@
-
-wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_interleaved.sh b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_interleaved.sh
new file mode 100755
index 00000000000..23acb105902
--- /dev/null
+++ b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_interleaved.sh
@@ -0,0 +1,23 @@
+#!/usr/bin/env bash
+# Copyright 2020-2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
+
+# Basic ISO broadcast test: a broadcaster transmits a BIS and a receiver listens
+# to the BIS.
+simulation_id="broadcast_iso_interleaved"
+verbosity_level=2
+
+cd ${BSIM_OUT_PATH}/bin
+
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_bis_prj_conf_overlay-interleaved_conf \
+  -v=${verbosity_level} -s=${simulation_id} -RealEncryption=1 -d=0 -testid=receive
+
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_bis_prj_conf_overlay-interleaved_conf \
+  -v=${verbosity_level} -s=${simulation_id} -RealEncryption=1 -d=1 -testid=broadcast
+
+Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \
+  -D=2 -sim_length=30e6 $@
+
+wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_sequential.sh b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_sequential.sh
new file mode 100755
index 00000000000..82ddcd9392b
--- /dev/null
+++ b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_sequential.sh
@@ -0,0 +1,24 @@
+#!/usr/bin/env bash
+# Copyright 2020 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
+
+# Basic ISO broadcast test: a broadcaster transmits a BIS and a receiver listens
+# to the BIS.
+simulation_id="broadcast_iso_sequential"
+verbosity_level=2
+EXECUTE_TIMEOUT=120
+
+cd ${BSIM_OUT_PATH}/bin
+
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_bis_prj_conf_overlay-sequential_conf \
+  -v=${verbosity_level} -s=${simulation_id} -RealEncryption=1 -d=0 -testid=receive
+
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_bis_prj_conf_overlay-sequential_conf \
+  -v=${verbosity_level} -s=${simulation_id} -RealEncryption=1 -d=1 -testid=broadcast
+
+Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \
+  -D=2 -sim_length=30e6 $@
+
+wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_vs_dp.sh b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_vs_dp.sh
index e0c4ab5e1b3..92b32a55562 100755
--- a/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_vs_dp.sh
+++ b/tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_vs_dp.sh
@@ -12,10 +12,10 @@ verbosity_level=2
 cd ${BSIM_OUT_PATH}/bin
 
 Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_bis_prj_vs_dp_conf \
-  -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=receive_vs_dp
+  -v=${verbosity_level} -s=${simulation_id} -RealEncryption=1 -d=0 -testid=receive_vs_dp
 
-Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_bis_prj_conf \
-  -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=broadcast
+Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_bis_prj_conf_overlay-sequential_conf \
+  -v=${verbosity_level} -s=${simulation_id} -RealEncryption=1 -d=1 -testid=broadcast
 
 Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \
   -D=2 -sim_length=30e6 $@
diff --git a/tests/bsim/bluetooth/ll/cis/prj.conf b/tests/bsim/bluetooth/ll/cis/prj.conf
index ebc9296a650..7d703c9481d 100644
--- a/tests/bsim/bluetooth/ll/cis/prj.conf
+++ b/tests/bsim/bluetooth/ll/cis/prj.conf
@@ -30,7 +30,6 @@ CONFIG_LOG=y
 CONFIG_BT_LL_SW_SPLIT=y
 CONFIG_BT_CTLR_CENTRAL_ISO=y
 CONFIG_BT_CTLR_PERIPHERAL_ISO=y
-CONFIG_BT_CTLR_CONN_ISO_SDU_LEN_MAX=247
 CONFIG_BT_CTLR_CONN_ISO_PDU_LEN_MAX=251
 CONFIG_BT_CTLR_CONN_ISO_STREAMS=9
 CONFIG_BT_CTLR_CONN_ISO_STREAMS_PER_GROUP=9
@@ -39,6 +38,7 @@ CONFIG_BT_CTLR_ISOAL_SINKS=9
 
 CONFIG_BT_CTLR_ISO_TX_BUFFERS=18
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=255
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=247
 CONFIG_BT_CTLR_ISO_RX_BUFFERS=1
 
 CONFIG_BT_CTLR_PHY_CODED=n
diff --git a/tests/bsim/bluetooth/ll/cis/src/main.c b/tests/bsim/bluetooth/ll/cis/src/main.c
index a3a8b0c9169..d835052be5f 100644
--- a/tests/bsim/bluetooth/ll/cis/src/main.c
+++ b/tests/bsim/bluetooth/ll/cis/src/main.c
@@ -1,7 +1,7 @@
 /* main.c - Application main entry point */
 
 /*
- * Copyright (c) 2023 Nordic Semiconductor ASA
+ * Copyright (c) 2023-2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,6 +13,7 @@
 
 #include <zephyr/bluetooth/bluetooth.h>
 #include <zephyr/bluetooth/conn.h>
+#include <zephyr/bluetooth/hci_types.h>
 #include <zephyr/bluetooth/iso.h>
 #include <zephyr/bluetooth/hci.h>
 #include <zephyr/sys/util.h>
@@ -312,16 +313,65 @@ void iso_sent(struct bt_iso_chan *chan)
 
 static void iso_connected(struct bt_iso_chan *chan)
 {
+	const struct bt_iso_chan_path hci_path = {
+		.pid = BT_ISO_DATA_PATH_HCI,
+		.format = BT_HCI_CODING_FORMAT_TRANSPARENT,
+	};
+	struct bt_iso_info iso_info;
+	int err;
+
+	err = bt_iso_chan_get_info(chan, &iso_info);
+	if (err != 0) {
+		FAIL("Failed to get ISO info: %d\n", err);
+		return;
+	}
+
 	printk("ISO Channel %p connected\n", chan);
 
 	k_sem_give(&sem_iso_conn);
+
+	if (iso_info.can_recv) {
+		err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_CTLR_TO_HOST, &hci_path);
+		if (err != 0) {
+			FAIL("Failed to setup ISO RX data path: %d\n", err);
+		}
+	}
+
+	if (iso_info.can_send) {
+		err = bt_iso_setup_data_path(chan, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR, &hci_path);
+		if (err != 0) {
+			FAIL("Failed to setup ISO TX data path: %d\n", err);
+		}
+	}
 }
 
 static void iso_disconnected(struct bt_iso_chan *chan, uint8_t reason)
 {
+	struct bt_iso_info iso_info;
+	int err;
+
 	printk("ISO Channel %p disconnected (reason 0x%02x)\n", chan, reason);
 
 	k_sem_give(&sem_iso_disc);
+
+	err = bt_iso_chan_get_info(chan, &iso_info);
+	if (err != 0) {
+		FAIL("Failed to get ISO info: %d\n", err);
+	} else if (iso_info.type == BT_ISO_CHAN_TYPE_CENTRAL) {
+		if (iso_info.can_recv) {
+			err = bt_iso_remove_data_path(chan, BT_HCI_DATAPATH_DIR_CTLR_TO_HOST);
+			if (err != 0) {
+				FAIL("Failed to remove ISO RX data path: %d\n", err);
+			}
+		}
+
+		if (iso_info.can_send) {
+			err = bt_iso_remove_data_path(chan, BT_HCI_DATAPATH_DIR_HOST_TO_CTLR);
+			if (err != 0) {
+				FAIL("Failed to remove ISO TX data path: %d\n", err);
+			}
+		}
+	}
 }
 
 static struct bt_iso_chan_ops iso_ops = {
@@ -358,7 +408,6 @@ static void test_cis_central(void)
 	for (int i = 0; i < CONFIG_BT_ISO_MAX_CHAN; i++) {
 		iso_tx[i].sdu = CONFIG_BT_ISO_TX_MTU;
 		iso_tx[i].phy = BT_GAP_LE_PHY_2M;
-		iso_tx[i].path = NULL;
 		if (IS_ENABLED(CONFIG_TEST_FT_SKIP_SUBEVENTS)) {
 			iso_tx[i].rtn = 2U;
 		} else {
@@ -374,7 +423,6 @@ static void test_cis_central(void)
 
 		iso_rx[i].sdu = CONFIG_BT_ISO_RX_MTU;
 		iso_rx[i].phy = BT_GAP_LE_PHY_2M;
-		iso_rx[i].path = NULL;
 		if (IS_ENABLED(CONFIG_TEST_FT_SKIP_SUBEVENTS)) {
 			iso_rx[i].rtn = 2U;
 		} else {
@@ -658,7 +706,6 @@ static void test_cis_peripheral(void)
 	for (int i = 0; i < CONFIG_BT_ISO_MAX_CHAN; i++) {
 		iso_tx_p[i].sdu = CONFIG_BT_ISO_TX_MTU;
 		iso_tx_p[i].phy = BT_GAP_LE_PHY_2M;
-		iso_tx_p[i].path = NULL;
 		if (IS_ENABLED(CONFIG_TEST_FT_SKIP_SUBEVENTS)) {
 			iso_tx_p[i].rtn = 2U;
 		} else {
diff --git a/tests/bsim/bluetooth/ll/cis/sysbuild/hci_ipc/nrf5340_cpunet_iso_acl_group-bt_ll_sw_split.conf b/tests/bsim/bluetooth/ll/cis/sysbuild/hci_ipc/nrf5340_cpunet_iso_acl_group-bt_ll_sw_split.conf
index c43da5523ff..c9beb293fe3 100644
--- a/tests/bsim/bluetooth/ll/cis/sysbuild/hci_ipc/nrf5340_cpunet_iso_acl_group-bt_ll_sw_split.conf
+++ b/tests/bsim/bluetooth/ll/cis/sysbuild/hci_ipc/nrf5340_cpunet_iso_acl_group-bt_ll_sw_split.conf
@@ -15,12 +15,7 @@ CONFIG_BT_CENTRAL=y
 CONFIG_BT_HCI_RAW=y
 CONFIG_BT_MAX_CONN=4
 
-# Workaround: Unable to allocate command buffer when using K_NO_WAIT since
-# Host number of completed commands does not follow normal flow control.
-CONFIG_BT_BUF_CMD_TX_COUNT=10
-
 CONFIG_BT_BUF_EVT_RX_COUNT=16
-
 CONFIG_BT_BUF_EVT_RX_SIZE=255
 CONFIG_BT_BUF_ACL_RX_SIZE=255
 CONFIG_BT_BUF_ACL_TX_SIZE=251
@@ -99,7 +94,6 @@ CONFIG_BT_CTLR_SYNC_ISO_STREAM_MAX=2
 # ISO Connection Oriented
 CONFIG_BT_CTLR_CENTRAL_ISO=y
 CONFIG_BT_CTLR_PERIPHERAL_ISO=y
-CONFIG_BT_CTLR_CONN_ISO_SDU_LEN_MAX=247
 CONFIG_BT_CTLR_CONN_ISO_PDU_LEN_MAX=251
 CONFIG_BT_CTLR_CONN_ISO_STREAMS=4
 CONFIG_BT_CTLR_CONN_ISO_STREAMS_PER_GROUP=4
@@ -107,6 +101,7 @@ CONFIG_BT_CTLR_CONN_ISO_STREAMS_PER_GROUP=4
 # ISO Transmissions
 CONFIG_BT_CTLR_ISO_TX_BUFFERS=18
 CONFIG_BT_CTLR_ISO_TX_BUFFER_SIZE=255
+CONFIG_BT_CTLR_ISO_TX_SDU_LEN_MAX=247
 CONFIG_BT_CTLR_ISOAL_SOURCES=4
 
 # ISO Receptions
diff --git a/tests/bsim/bluetooth/ll/compile.sh b/tests/bsim/bluetooth/ll/compile.sh
index 6eae34b67a8..87b1f3006ad 100755
--- a/tests/bsim/bluetooth/ll/compile.sh
+++ b/tests/bsim/bluetooth/ll/compile.sh
@@ -24,7 +24,8 @@ app=tests/bsim/bluetooth/ll/conn conf_file=prj_split_privacy.conf compile
 app=tests/bsim/bluetooth/ll/conn conf_file=prj_split_low_lat.conf compile
 app=tests/bsim/bluetooth/ll/conn conf_file=prj_split_single_timer.conf compile
 
-app=tests/bsim/bluetooth/ll/bis compile
+app=tests/bsim/bluetooth/ll/bis conf_overlay=overlay-sequential.conf compile
+app=tests/bsim/bluetooth/ll/bis conf_overlay=overlay-interleaved.conf  compile
 app=tests/bsim/bluetooth/ll/bis conf_overlay=overlay-ll_interface.conf compile
 app=tests/bsim/bluetooth/ll/bis conf_overlay=overlay-ticker_expire_info.conf compile
 app=tests/bsim/bluetooth/ll/bis conf_overlay=overlay-scan_aux_use_chains.conf compile
diff --git a/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/gatt_macs.h b/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/gatt_macs.h
index 01e82571ebd..d836a9c89e7 100644
--- a/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/gatt_macs.h
+++ b/tests/bsim/bluetooth/ll/edtt/gatt_test_app/src/gatt/gatt_macs.h
@@ -138,7 +138,7 @@ extern "C" {
  *
  *  Helper macro to declare a Managed CCC attribute.
  *
- *  @param _ccc    CCC attribute user data, shall point to a _bt_gatt_ccc.
+ *  @param _ccc    CCC attribute user data, shall point to a bt_gatt_ccc_managed_user_data.
  *  @param _perm   CCC access permissions.
  *  @param _handle Descriptor attribute handle.
  */
@@ -161,7 +161,7 @@ extern "C" {
  *         BT_GATT_PERM_READ | BT_GATT_PERM_WRITE, \
  *         bt_gatt_attr_read_ccc, \
  *         bt_gatt_attr_write_ccc, \
- *         (&(struct _bt_gatt_ccc) { \
+ *         (&(struct bt_gatt_ccc_managed_user_data) { \
  *             .cfg = _cfg, \
  *             .cfg_len = ARRAY_SIZE(_cfg), \
  *             .cfg_changed = _cfg_changed \
@@ -177,10 +177,10 @@ extern "C" {
  *  @param _cfg_changed Configuration changed callback.
  *  @param _handle      Descriptor attribute handle.
  */
-#define BT_GATT_H_CCC(_cfg, _cfg_changed, _handle) \
-		BT_GATT_H_MANAGED((&(struct _bt_gatt_ccc) \
-			BT_GATT_CCC_INITIALIZER(_cfg_changed, NULL, NULL)),\
-			BT_GATT_PERM_READ | BT_GATT_PERM_WRITE, _handle)
+#define BT_GATT_H_CCC(_cfg, _cfg_changed, _handle)                                                 \
+	BT_GATT_H_MANAGED((&(struct bt_gatt_ccc_managed_user_data)                                 \
+				   BT_GATT_CCC_MANAGED_USER_DATA_INIT(_cfg_changed, NULL, NULL)),  \
+			  BT_GATT_PERM_READ | BT_GATT_PERM_WRITE, _handle)
 
 /**
  *  @brief Characteristic Extended Properties Declaration Macro.
diff --git a/tests/bsim/bluetooth/ll/multiple_id/Kconfig.sysbuild b/tests/bsim/bluetooth/ll/multiple_id/Kconfig.sysbuild
new file mode 100644
index 00000000000..6cf765d44e2
--- /dev/null
+++ b/tests/bsim/bluetooth/ll/multiple_id/Kconfig.sysbuild
@@ -0,0 +1,14 @@
+# Copyright 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+source "share/sysbuild/Kconfig"
+
+config NET_CORE_BOARD
+	string
+	default "nrf5340bsim/nrf5340/cpunet" if $(BOARD_TARGET_STRING) = "NRF5340BSIM_NRF5340_CPUAPP"
+
+config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX
+	int
+	# Let's pass the test arguments to the application MCU test
+	# otherwise by default they would have gone to the net core.
+	default 0 if $(BOARD_TARGET_STRING) = "NRF5340BSIM_NRF5340_CPUAPP"
diff --git a/tests/bsim/bluetooth/ll/multiple_id/overlay-nrf5340_cpunet_iso-bt_ll_sw_split.conf b/tests/bsim/bluetooth/ll/multiple_id/overlay-nrf5340_cpunet_iso-bt_ll_sw_split.conf
new file mode 100644
index 00000000000..7dc53386b6d
--- /dev/null
+++ b/tests/bsim/bluetooth/ll/multiple_id/overlay-nrf5340_cpunet_iso-bt_ll_sw_split.conf
@@ -0,0 +1,34 @@
+# Maximum simultaneous ACL connections, today's maximum considering other
+# roles using ticker nodes count up to 255 (UINT8_MAX) in the hci_ipc with ISO
+# support
+CONFIG_BT_MAX_CONN=233
+
+# Each PHY update can pause connections for 6 interval hence to let other
+# parallel connection establishment to succeed increase Rx buffer count.
+# A minimum of 1 Rx buffer is required to receive data PDU, during control
+# procedures Rx buffer could be held, preventing new connections to be
+# established, a value of 3 is tuned based on this test case execution for 2
+# iterations. If there is buffer leak, simulated by using value of 2 here, the
+# test is failing.
+# If there is buffer leak, this test now should catch it.
+CONFIG_BT_CTLR_RX_BUFFERS=3
+
+# Provide enough spacing between connections so that multiple peripheral roles
+# when connected to a single peer device (peripheral_identity sample) have
+# room for window widening and do not overlap with each other in that single
+# peer device. This can be tuned based on connection interval and clock
+# accuracy, current value here is sufficient for 500ppm at 1 second interval and
+# considering required connection event length for 251 byte PDU on 2M PHY.
+# (Event Overhead + Radio Ready Delay + Rx window + 1064 + 154 + 1064)
+CONFIG_BT_CTLR_ADVANCED_FEATURES=y
+CONFIG_BT_CTLR_CENTRAL_SPACING=3750
+
+# Do not use max data PDU size time reservation for connection events spacing
+# instead use lesser value as supplied in CONFIG_BT_CTLR_CENTRAL_SPACING
+CONFIG_BT_CTLR_CENTRAL_RESERVE_MAX=n
+CONFIG_BT_CTLR_SLOT_RESERVATION_UPDATE=n
+
+# Required maximum simultaneous LLCP contexts
+CONFIG_BT_CTLR_LLCP_LOCAL_PROC_CTX_BUF_NUM=233
+
+CONFIG_LOG=y
diff --git a/tests/bsim/bluetooth/ll/multiple_id/prj.conf b/tests/bsim/bluetooth/ll/multiple_id/prj.conf
index c32e067d922..345c7b2a64b 100644
--- a/tests/bsim/bluetooth/ll/multiple_id/prj.conf
+++ b/tests/bsim/bluetooth/ll/multiple_id/prj.conf
@@ -10,19 +10,23 @@ CONFIG_BT_AUTO_PHY_UPDATE=y
 CONFIG_BT_USER_DATA_LEN_UPDATE=y
 CONFIG_BT_AUTO_DATA_LEN_UPDATE=y
 
-CONFIG_BT_MAX_CONN=250
-CONFIG_BT_ID_MAX=250
-
-# L2CAP, ATT and SMP usage cause data transmission deadlock due to shortage
-# of buffers when transactions crossover amongst the connections in the same
-# device. Hence, keeping them disabled in this test until future investigations.
+# Maximum simultaneous ACL connections, current maximum considering other roles
+# using ticker nodes count up to 255 (UINT8_MAX) in the hci_ipc with ISO support
+CONFIG_BT_MAX_CONN=233
+CONFIG_BT_ID_MAX=233
 
+# Avoid using the PPCP provided connection interval so that the multiple
+# connections are kept non-overlapping as initially scheduled at connection
+# setup
 CONFIG_BT_GAP_AUTO_UPDATE_CONN_PARAMS=n
 
+# Enables simultaneousn MTU exchange in the test
 CONFIG_BT_GATT_CLIENT=y
 
+# Having simulataneous SMP procedures leads to deadlock, disabled pending
+# required investigation of the issue.
 # CONFIG_BT_SMP=y
-# CONFIG_BT_MAX_PAIRED=250
+# CONFIG_BT_MAX_PAIRED=233
 
 CONFIG_BT_L2CAP_TX_MTU=247
 
@@ -58,3 +62,5 @@ CONFIG_BT_CTLR_CENTRAL_SPACING=3750
 # instead use lesser value as supplied in CONFIG_BT_CTLR_CENTRAL_SPACING
 CONFIG_BT_CTLR_CENTRAL_RESERVE_MAX=n
 CONFIG_BT_CTLR_SLOT_RESERVATION_UPDATE=n
+
+CONFIG_LOG=y
diff --git a/tests/bsim/bluetooth/ll/multiple_id/sysbuild.cmake b/tests/bsim/bluetooth/ll/multiple_id/sysbuild.cmake
new file mode 100644
index 00000000000..0e987ad242e
--- /dev/null
+++ b/tests/bsim/bluetooth/ll/multiple_id/sysbuild.cmake
@@ -0,0 +1,29 @@
+# Copyright (c) 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT("${SB_CONFIG_NET_CORE_BOARD}" STREQUAL ""))
+	set(NET_APP hci_ipc)
+	set(NET_APP_SRC_DIR ${ZEPHYR_BASE}/samples/bluetooth/${NET_APP})
+
+	ExternalZephyrProject_Add(
+		APPLICATION ${NET_APP}
+		SOURCE_DIR  ${NET_APP_SRC_DIR}
+		BOARD       ${SB_CONFIG_NET_CORE_BOARD}
+	)
+
+	set(${NET_APP}_CONF_FILE
+	 ${NET_APP_SRC_DIR}/nrf5340_cpunet_iso-bt_ll_sw_split.conf
+	 CACHE INTERNAL ""
+	)
+
+	set(${NET_APP}_EXTRA_CONF_FILE
+	 ${APP_DIR}/overlay-nrf5340_cpunet_iso-bt_ll_sw_split.conf
+	 CACHE INTERNAL ""
+	)
+
+	native_simulator_set_primary_mcu_index(${DEFAULT_IMAGE} ${NET_APP})
+
+	native_simulator_set_child_images(${DEFAULT_IMAGE} ${NET_APP})
+endif()
+
+native_simulator_set_final_executable(${DEFAULT_IMAGE})
diff --git a/tests/bsim/bluetooth/ll/throughput/Kconfig.sysbuild b/tests/bsim/bluetooth/ll/throughput/Kconfig.sysbuild
new file mode 100644
index 00000000000..6cf765d44e2
--- /dev/null
+++ b/tests/bsim/bluetooth/ll/throughput/Kconfig.sysbuild
@@ -0,0 +1,14 @@
+# Copyright 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+source "share/sysbuild/Kconfig"
+
+config NET_CORE_BOARD
+	string
+	default "nrf5340bsim/nrf5340/cpunet" if $(BOARD_TARGET_STRING) = "NRF5340BSIM_NRF5340_CPUAPP"
+
+config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX
+	int
+	# Let's pass the test arguments to the application MCU test
+	# otherwise by default they would have gone to the net core.
+	default 0 if $(BOARD_TARGET_STRING) = "NRF5340BSIM_NRF5340_CPUAPP"
diff --git a/tests/bsim/bluetooth/ll/throughput/prj.conf b/tests/bsim/bluetooth/ll/throughput/prj.conf
index 6f52a3d5091..e8848bbf25d 100644
--- a/tests/bsim/bluetooth/ll/throughput/prj.conf
+++ b/tests/bsim/bluetooth/ll/throughput/prj.conf
@@ -4,11 +4,45 @@ CONFIG_BT_PERIPHERAL=y
 CONFIG_BT_SMP=y
 CONFIG_BT_GATT_CLIENT=y
 
-CONFIG_BT_BUF_ACL_RX_SIZE=255
-CONFIG_BT_BUF_ACL_TX_SIZE=251
+# Maximum L2CAP size for one LL PDU size
+CONFIG_BT_L2CAP_TX_MTU=247
+
+# Auto initiated PHY update on connection established
+CONFIG_BT_AUTO_PHY_UPDATE=y
+# Enable user initiated PHY update support
+CONFIG_BT_USER_PHY_UPDATE=y
+
+# Auto initiated Data Length update on connection established
+CONFIG_BT_AUTO_DATA_LEN_UPDATE=y
+# Enable user initiated Data Length update support
+CONFIG_BT_USER_DATA_LEN_UPDATE=y
+
+# BT HCI Command Buffers
+# Greater than BT_BUF_ACL_TX_COUNT, to be able to Send Host Number of Completed Packets commands
+CONFIG_BT_BUF_CMD_TX_COUNT=4
 CONFIG_BT_BUF_CMD_TX_SIZE=255
+
+# BT HCI Event Buffers
+# Greater than BT_BUF_ACL_TX_COUNT, to be able to receive Number of Completed Packets events
+CONFIG_BT_BUF_EVT_RX_COUNT=4
+CONFIG_BT_BUF_EVT_RX_SIZE=255
+
+# BT HCI Discardable Event Buffers
+CONFIG_BT_BUF_EVT_DISCARDABLE_COUNT=3
 CONFIG_BT_BUF_EVT_DISCARDABLE_SIZE=255
 
-CONFIG_BT_L2CAP_TX_MTU=247
+# BT HCI ACL TX Data Buffers
+CONFIG_BT_BUF_ACL_TX_COUNT=3
+CONFIG_BT_BUF_ACL_TX_SIZE=251
 
+# BT HCI ACL RX Data Buffers
+CONFIG_BT_BUF_ACL_RX_COUNT_EXTRA=1
+CONFIG_BT_BUF_ACL_RX_SIZE=255
+
+# Maximum LL ACL PDU length
 CONFIG_BT_CTLR_DATA_LENGTH_MAX=251
+
+# Enable Coded PHY Support
+CONFIG_BT_CTLR_PHY_CODED=y
+
+CONFIG_LOG=y
diff --git a/tests/bsim/bluetooth/ll/throughput/src/main.c b/tests/bsim/bluetooth/ll/throughput/src/main.c
index 38f4adc6da6..a18801d4066 100644
--- a/tests/bsim/bluetooth/ll/throughput/src/main.c
+++ b/tests/bsim/bluetooth/ll/throughput/src/main.c
@@ -16,7 +16,15 @@
 #include "time_machine.h"
 #include "bstests.h"
 
-#define COUNT      5000   /* Arbitrary GATT Write Cmd iterations used */
+/* There are 13 iterations of PHY update every 3 seconds, and based on actual
+ * simulation 10000 iterations are sufficient to finish these iterations with
+ * a stable 2M throughput value to be verified. If Central and Peripheral take
+ * different duration to complete these iterations, the test will fail due to
+ * the throughput calculated over one second duration will be low due to the
+ * connection being disconnected before the other device could complete all the
+ * iterations.
+ */
+#define COUNT 10000
 
 /* Write Throughput calculation:
  *  Measure interval = 1 s
diff --git a/tests/bsim/bluetooth/ll/throughput/sysbuild.cmake b/tests/bsim/bluetooth/ll/throughput/sysbuild.cmake
new file mode 100644
index 00000000000..69397264edf
--- /dev/null
+++ b/tests/bsim/bluetooth/ll/throughput/sysbuild.cmake
@@ -0,0 +1,24 @@
+# Copyright (c) 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if(NOT("${SB_CONFIG_NET_CORE_BOARD}" STREQUAL ""))
+	set(NET_APP hci_ipc)
+	set(NET_APP_SRC_DIR ${ZEPHYR_BASE}/samples/bluetooth/${NET_APP})
+
+	ExternalZephyrProject_Add(
+		APPLICATION ${NET_APP}
+		SOURCE_DIR  ${NET_APP_SRC_DIR}
+		BOARD       ${SB_CONFIG_NET_CORE_BOARD}
+	)
+
+	set(${NET_APP}_CONF_FILE
+	 ${NET_APP_SRC_DIR}/nrf5340_cpunet_iso-bt_ll_sw_split.conf
+	 CACHE INTERNAL ""
+	)
+
+	native_simulator_set_primary_mcu_index(${DEFAULT_IMAGE} ${NET_APP})
+
+	native_simulator_set_child_images(${DEFAULT_IMAGE} ${NET_APP})
+endif()
+
+native_simulator_set_final_executable(${DEFAULT_IMAGE})
diff --git a/tests/bsim/bluetooth/ll/throughput/tests_scripts/gatt_write.sh b/tests/bsim/bluetooth/ll/throughput/tests_scripts/gatt_write.sh
index 12881ee88c0..61fd4bc8edc 100755
--- a/tests/bsim/bluetooth/ll/throughput/tests_scripts/gatt_write.sh
+++ b/tests/bsim/bluetooth/ll/throughput/tests_scripts/gatt_write.sh
@@ -11,10 +11,12 @@ EXECUTE_TIMEOUT=240
 cd ${BSIM_OUT_PATH}/bin
 
 Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_throughput_prj_conf \
-  -v=${verbosity_level} -s=${simulation_id} -d=0 -testid=central
+  -v=${verbosity_level} -s=${simulation_id} -RealEncryption=1 -d=0 \
+  -testid=central
 
 Execute ./bs_${BOARD_TS}_tests_bsim_bluetooth_ll_throughput_prj_conf\
-  -v=${verbosity_level} -s=${simulation_id} -d=1 -testid=peripheral
+  -v=${verbosity_level} -s=${simulation_id} -RealEncryption=1 -d=1 \
+  -testid=peripheral
 
 Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} \
   -D=2 -sim_length=60e6 $@ -argschannel -at=40
diff --git a/tests/bsim/bluetooth/mesh/compile.sh b/tests/bsim/bluetooth/mesh/compile.sh
index 15a80937879..3082c6beea5 100755
--- a/tests/bsim/bluetooth/mesh/compile.sh
+++ b/tests/bsim/bluetooth/mesh/compile.sh
@@ -18,7 +18,9 @@ app=tests/bsim/bluetooth/mesh conf_overlay=overlay_low_lat.conf compile
 app=tests/bsim/bluetooth/mesh conf_overlay=overlay_psa.conf compile
 app=tests/bsim/bluetooth/mesh conf_overlay=overlay_workq_sys.conf compile
 app=tests/bsim/bluetooth/mesh conf_overlay=overlay_multi_adv_sets.conf compile
-app=tests/bsim/bluetooth/mesh conf_overlay="overlay_pst.conf;overlay_psa.conf" compile
+app=tests/bsim/bluetooth/mesh conf_overlay=overlay_lpn_scan_on.conf compile
+app=tests/bsim/bluetooth/mesh \
+  conf_overlay="overlay_pst.conf;overlay_ss.conf;overlay_psa.conf" compile
 app=tests/bsim/bluetooth/mesh conf_overlay="overlay_gatt.conf;overlay_psa.conf" compile
 app=tests/bsim/bluetooth/mesh conf_overlay="overlay_gatt.conf;overlay_workq_sys.conf" compile
 app=tests/bsim/bluetooth/mesh conf_overlay="overlay_low_lat.conf;overlay_psa.conf" compile
@@ -27,7 +29,7 @@ app=tests/bsim/bluetooth/mesh conf_overlay="overlay_pst.conf;overlay_gatt.conf"
 app=tests/bsim/bluetooth/mesh \
   conf_overlay="overlay_gatt.conf;overlay_multi_adv_sets.conf" compile
 app=tests/bsim/bluetooth/mesh \
-  conf_overlay="overlay_pst.conf;overlay_gatt.conf;overlay_psa.conf" compile
+  conf_overlay="overlay_pst.conf;overlay_ss.conf;overlay_gatt.conf;overlay_psa.conf" compile
 app=tests/bsim/bluetooth/mesh \
   conf_overlay="overlay_pst.conf;overlay_gatt.conf;overlay_workq_sys.conf" compile
 wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/mesh/overlay_lpn_scan_on.conf b/tests/bsim/bluetooth/mesh/overlay_lpn_scan_on.conf
new file mode 100644
index 00000000000..60fd8985fa9
--- /dev/null
+++ b/tests/bsim/bluetooth/mesh/overlay_lpn_scan_on.conf
@@ -0,0 +1 @@
+CONFIG_BT_MESH_LPN_ESTABLISHMENT=n
diff --git a/tests/bsim/bluetooth/mesh/overlay_psa.conf b/tests/bsim/bluetooth/mesh/overlay_psa.conf
index a1c61e095e7..97629adc43f 100644
--- a/tests/bsim/bluetooth/mesh/overlay_psa.conf
+++ b/tests/bsim/bluetooth/mesh/overlay_psa.conf
@@ -1,8 +1,5 @@
 # Increase the number of key slots in PSA Crypto core
 CONFIG_MBEDTLS_PSA_KEY_SLOT_COUNT=64
 
-# Increase the number of key slots in PSA Crypto core
-CONFIG_MBEDTLS_PSA_KEY_SLOT_COUNT=64
-
 # Enable mbedTLS PSA as a crypto backend
 CONFIG_BT_MESH_USES_MBEDTLS_PSA=y
diff --git a/tests/bsim/bluetooth/mesh/overlay_pst.conf b/tests/bsim/bluetooth/mesh/overlay_pst.conf
index 52856866819..37b9f2b9969 100644
--- a/tests/bsim/bluetooth/mesh/overlay_pst.conf
+++ b/tests/bsim/bluetooth/mesh/overlay_pst.conf
@@ -3,7 +3,6 @@ CONFIG_BT_SETTINGS=y
 CONFIG_FLASH=y
 CONFIG_FLASH_MAP=y
 CONFIG_NVS=y
-CONFIG_SECURE_STORAGE=y
 
 CONFIG_BT_PERIPHERAL=y
 CONFIG_BT_MESH_GATT_PROXY=y
diff --git a/tests/bsim/bluetooth/mesh/overlay_ss.conf b/tests/bsim/bluetooth/mesh/overlay_ss.conf
new file mode 100644
index 00000000000..8ac2b4c327f
--- /dev/null
+++ b/tests/bsim/bluetooth/mesh/overlay_ss.conf
@@ -0,0 +1 @@
+CONFIG_SECURE_STORAGE=y
diff --git a/tests/bsim/bluetooth/mesh/prj.conf b/tests/bsim/bluetooth/mesh/prj.conf
index 522a49e2d11..593a7f01668 100644
--- a/tests/bsim/bluetooth/mesh/prj.conf
+++ b/tests/bsim/bluetooth/mesh/prj.conf
@@ -74,4 +74,5 @@ CONFIG_BT_TESTING=y
 # Needed for RPR tests due to huge amount of retransmitted messages
 CONFIG_BT_MESH_MSG_CACHE_SIZE=64
 
-CONFIG_MBEDTLS_PSA_KEY_SLOT_COUNT=64
+# Enable tinycrypt as a crypto backend
+CONFIG_BT_MESH_USES_TINYCRYPT=y
diff --git a/tests/bsim/bluetooth/mesh/src/test_beacon.c b/tests/bsim/bluetooth/mesh/src/test_beacon.c
index e4b77fcbb75..9766b434126 100644
--- a/tests/bsim/bluetooth/mesh/src/test_beacon.c
+++ b/tests/bsim/bluetooth/mesh/src/test_beacon.c
@@ -1766,7 +1766,7 @@ static void test_tx_priv_node_id(void)
 	/* Wait for Node ID advertising to end */
 	k_sleep(K_SECONDS(65));
 
-	/* Check that advertisment has stopped */
+	/* Check that advertisement has stopped */
 	ASSERT_OK_MSG(bt_mesh_subnet_priv_node_id_get(TEST_NET_IDX1, &state),
 		      "Failed to get private node ID");
 	ASSERT_EQUAL(state, BT_MESH_NODE_IDENTITY_STOPPED);
@@ -1796,7 +1796,7 @@ static void test_rx_priv_node_id(void)
 
 	uint64_t last_pp_random = beacon.pp_random;
 
-	/* Wait for first node ID advertisment to finish, then scan for
+	/* Wait for first node ID advertisement to finish, then scan for
 	 * second node ID and verify that random field has changed
 	 */
 
@@ -2098,7 +2098,7 @@ static void test_rx_priv_multi_net_id(void)
 			if (beacon.pp_hash ==
 			    proxy_adv_hash_calc(net_ctx[i].net, beacon.pp_random, NULL, true)) {
 				if (old_idx == 0xff) {
-					/* Received first Net ID advertisment */
+					/* Received first Net ID advertisement */
 					old_idx = i;
 					net_ctx[i].start = k_uptime_get();
 					net_ctx[i].recv_cnt++;
diff --git a/tests/bsim/bluetooth/mesh/src/test_brg.c b/tests/bsim/bluetooth/mesh/src/test_brg.c
index a3ee45c36c0..5a2392d37d1 100644
--- a/tests/bsim/bluetooth/mesh/src/test_brg.c
+++ b/tests/bsim/bluetooth/mesh/src/test_brg.c
@@ -246,22 +246,26 @@ static void bridge_entry_remove(uint16_t src, uint16_t dst, uint16_t net_idx1, u
 static void tester_bridge_configure(void)
 {
 	uint8_t status;
-	int err;
 
 	LOG_INF("Configuring bridge...");
 
+	ASSERT_OK(
+		bt_mesh_cfg_cli_net_transmit_set(0, BRIDGE_ADDR, BT_MESH_TRANSMIT(2, 20), &status));
+	if (status != BT_MESH_TRANSMIT(2, 20)) {
+		FAIL("Net transmit set failed (status %u)", status);
+	}
+
 	for (int i = 0; i < remote_nodes; i++) {
-		err = bt_mesh_cfg_cli_net_key_add(0, BRIDGE_ADDR, i + 1, subnet_keys[i], &status);
-		if (err || status) {
-			FAIL("NetKey add failed (err %d, status %u)", err, status);
-			return;
+		ASSERT_OK(bt_mesh_cfg_cli_net_key_add(0, BRIDGE_ADDR, i + 1, subnet_keys[i],
+						      &status));
+		if (status) {
+			FAIL("NetKey add failed (status %u)", status);
 		}
 	}
 
 	ASSERT_OK(bt_mesh_brg_cfg_cli_set(0, BRIDGE_ADDR, BT_MESH_BRG_CFG_ENABLED, &status));
 	if (status != BT_MESH_BRG_CFG_ENABLED) {
 		FAIL("Subnet bridge set failed (status %u)", status);
-		return;
 	}
 
 	/* Disable Relay feature to avoid interference in the test. */
@@ -271,7 +275,6 @@ static void tester_bridge_configure(void)
 					    BT_MESH_TRANSMIT(2, 20), &status, &transmit));
 	if (status) {
 		FAIL("Relay set failed (status %u)", status);
-		return;
 	}
 
 	LOG_INF("Bridge configured");
diff --git a/tests/bsim/bluetooth/mesh/src/test_friendship.c b/tests/bsim/bluetooth/mesh/src/test_friendship.c
index ecdd5bdbebf..f5ca923a9b1 100644
--- a/tests/bsim/bluetooth/mesh/src/test_friendship.c
+++ b/tests/bsim/bluetooth/mesh/src/test_friendship.c
@@ -537,8 +537,8 @@ static void test_lpn_msg_mesh(void)
 	bt_mesh_test_friendship_init(CONFIG_BT_MESH_FRIEND_LPN_COUNT);
 	bt_mesh_lpn_set(true);
 
-	ASSERT_OK_MSG(bt_mesh_test_friendship_evt_wait(BT_MESH_TEST_LPN_ESTABLISHED,
-						       K_SECONDS(2)), "LPN not established");
+	ASSERT_OK_MSG(bt_mesh_test_friendship_evt_wait(BT_MESH_TEST_LPN_ESTABLISHED, K_SECONDS(2)),
+		      "LPN did not establish friendship");
 	/* LPN polls on establishment. Clear the poll state */
 	bt_mesh_test_friendship_evt_clear(BT_MESH_TEST_LPN_POLLED);
 
@@ -546,14 +546,14 @@ static void test_lpn_msg_mesh(void)
 	 * Should not be affected by the LPN mode at all.
 	 */
 	ASSERT_OK_MSG(bt_mesh_test_send(other_cfg.addr, NULL, 5, 0, K_NO_WAIT),
-		      "Send to mesh failed");
+		      "Send to the third mesh node failed");
 
 	/* Receive an unsegmented message back */
 	ASSERT_OK(bt_mesh_test_recv(5, cfg->addr, NULL, K_FOREVER));
 
 	/* Send a segmented message to the mesh node. */
 	ASSERT_OK_MSG(bt_mesh_test_send(other_cfg.addr, NULL, 15, 0, K_FOREVER),
-		      "Send to other failed");
+		      "Send to the third mesh node failed");
 
 	/* Receive a segmented message back */
 	ASSERT_OK(bt_mesh_test_recv(15, cfg->addr, NULL, K_FOREVER));
@@ -569,6 +569,25 @@ static void test_lpn_msg_mesh(void)
 	bt_mesh_model_msg_init(test_model->pub->msg, TEST_MSG_OP_1);
 	ASSERT_OK(bt_mesh_model_publish(test_model));
 
+	/* Give time to complete publication */
+	k_sleep(K_SECONDS(2));
+
+	/* Terminate friendship by disabling the LPN functionality */
+	bt_mesh_lpn_set(false);
+	ASSERT_OK_MSG(bt_mesh_test_friendship_evt_wait(BT_MESH_TEST_LPN_TERMINATED, K_SECONDS(5)),
+		      "LPN did not terminate friendship correctly");
+
+	/* With this enabled feature, LPN leaves scanner disabled after termination. */
+	if (IS_ENABLED(CONFIG_BT_MESH_LPN_ESTABLISHMENT)) {
+		bt_mesh_scan_enable();
+	}
+
+	/* Send an unsegmented message to a third mesh node. */
+	ASSERT_OK_MSG(bt_mesh_test_send(other_cfg.addr, NULL, 5, 0, K_NO_WAIT),
+		      "Send to the third mesh node failed");
+	/* Receive an unsegmented message back */
+	ASSERT_OK(bt_mesh_test_recv(5, cfg->addr, NULL, K_FOREVER));
+
 	PASS();
 }
 
@@ -587,9 +606,9 @@ static void test_lpn_re_est(void)
 			      "LPN not established");
 
 		bt_mesh_lpn_set(false);
-		ASSERT_OK_MSG(bt_mesh_test_friendship_evt_wait(BT_MESH_TEST_LPN_TERMINATED,
-							       K_SECONDS(5)),
-			      "LPN never terminated friendship");
+		ASSERT_OK_MSG(
+			bt_mesh_test_friendship_evt_wait(BT_MESH_TEST_LPN_TERMINATED, K_SECONDS(5)),
+			"LPN did not terminate friendship correctly");
 
 		k_sleep(K_SECONDS(2));
 	}
@@ -966,6 +985,13 @@ static void test_other_msg(void)
 	ASSERT_OK_MSG(bt_mesh_test_recv(1, cfg->addr, NULL, K_FOREVER),
 		      "Failed to receive from LPN");
 
+	/* Receive an unsegmented message from the LPN outside of friendship. */
+	ASSERT_OK_MSG(bt_mesh_test_recv(5, cfg->addr, NULL, K_FOREVER),
+		      "Failed to receive from LPN after friendship termination");
+	/* Send an unsegmented message to the LPN */
+	ASSERT_OK_MSG(bt_mesh_test_send(LPN_ADDR_START, NULL, 5, 0, K_NO_WAIT),
+		      "Failed to send to LPN after friendship termination");
+
 	PASS();
 }
 
diff --git a/tests/bsim/bluetooth/mesh/src/test_provision.c b/tests/bsim/bluetooth/mesh/src/test_provision.c
index b98fe1d89ad..67cccfd9316 100644
--- a/tests/bsim/bluetooth/mesh/src/test_provision.c
+++ b/tests/bsim/bluetooth/mesh/src/test_provision.c
@@ -15,6 +15,10 @@
 
 #if defined CONFIG_BT_MESH_USES_MBEDTLS_PSA
 #include <psa/crypto.h>
+#elif defined CONFIG_BT_MESH_USES_TINYCRYPT
+#include <tinycrypt/constants.h>
+#include <tinycrypt/ecc.h>
+#include <tinycrypt/ecc_dh.h>
 #else
 #error "Unknown crypto library has been chosen"
 #endif
@@ -523,6 +527,7 @@ static void oob_auth_set(int test_step)
 	prov.input_actions = oob_auth_test_vector[test_step].input_actions;
 }
 
+#if defined CONFIG_BT_MESH_USES_MBEDTLS_PSA
 static void generate_oob_key_pair(void)
 {
 	psa_key_attributes_t key_attributes = PSA_KEY_ATTRIBUTES_INIT;
@@ -557,6 +562,12 @@ static void generate_oob_key_pair(void)
 
 	memcpy(public_key_be, public_key_repr + 1, 64);
 }
+#elif defined CONFIG_BT_MESH_USES_TINYCRYPT
+static void generate_oob_key_pair(void)
+{
+	ASSERT_TRUE(uECC_make_key(public_key_be, private_key_be, uECC_secp256r1()));
+}
+#endif
 
 static void oob_device(bool use_oob_pk)
 {
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/blob_mdls/blob_srv_persistence.sh b/tests/bsim/bluetooth/mesh/tests_scripts/blob_mdls/blob_srv_persistence.sh
index 9973a82dc49..fec08a751ce 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/blob_mdls/blob_srv_persistence.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/blob_mdls/blob_srv_persistence.sh
@@ -36,27 +36,27 @@ RunTestFlash blob_recover_phase \
    blob_cli_stop -flash_rm blob_srv_stop -flash_rm -- -argstest expected-phase=4
 
 # The same test but with PSA crypto
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash blob_recover_phase_psa \
    blob_cli_stop -flash_erase blob_srv_stop -flash_erase -- -argstest expected-phase=1
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash blob_recover_phase_psa \
    blob_cli_stop blob_srv_stop -- -argstest expected-phase=2
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash blob_recover_phase_psa \
    blob_cli_stop blob_srv_stop -- -argstest expected-phase=3
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash blob_recover_phase_psa \
    blob_cli_stop -flash_rm blob_srv_stop -flash_rm -- -argstest expected-phase=4
 
 # Test reaching suspended state and continuation after reboot on new procedure.
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash blob_recover_phase_psa \
    blob_cli_stop -flash_erase blob_srv_stop -flash_erase -- -argstest expected-phase=5
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash blob_recover_phase_psa \
    blob_cli_stop -flash_rm blob_srv_stop -flash_rm -- -argstest expected-phase=4
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_persistent_storage.sh b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_persistent_storage.sh
index 7e22f42589b..311d590b47a 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_persistent_storage.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/bridge/brg_persistent_storage.sh
@@ -21,10 +21,10 @@ RunTestFlash mesh_brg_persistence \
 	brg_tester_persistence brg_bridge_simple
 
 # The same test but with PSA crypto
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash mesh_brg_persistence_psa \
 	brg_tester_persistence -flash_erase brg_bridge_simple -flash_erase
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash mesh_brg_persistence_psa \
 	brg_tester_persistence brg_bridge_simple
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_apply.sh b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_apply.sh
index 4f87fb10fef..83414d4df13 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_apply.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_apply.sh
@@ -16,7 +16,7 @@ RunTest dfu_all_tgts_lost_on_apply \
 	dfu_target_fail_on_apply \
 	-- -argstest targets=3
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest dfu_all_tgts_lost_on_apply_psa \
 	dfu_cli_all_targets_lost_on_apply \
 	dfu_target_fail_on_apply \
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_caps_get.sh b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_caps_get.sh
index 572445e4779..75c6b9bcde7 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_caps_get.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_caps_get.sh
@@ -16,7 +16,7 @@ RunTest dfu_all_tgts_lost_on_caps_get \
 	dfu_target_fail_on_caps_get \
 	-- -argstest targets=3
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest dfu_all_tgts_lost_on_caps_get_psa \
 	dfu_cli_all_targets_lost_on_caps_get \
 	dfu_target_fail_on_caps_get \
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_metadata.sh b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_metadata.sh
index e4fbe146dcd..2d170d46296 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_metadata.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_metadata.sh
@@ -16,7 +16,7 @@ RunTest dfu_all_tgts_lost_on_metadata \
 	dfu_target_fail_on_metadata \
 	-- -argstest targets=3
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest dfu_all_tgts_lost_on_metadata_psa \
 	dfu_cli_all_targets_lost_on_metadata \
 	dfu_target_fail_on_metadata \
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_update_get.sh b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_update_get.sh
index 7b96161eccd..915298223f4 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_update_get.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_update_get.sh
@@ -16,7 +16,7 @@ RunTest dfu_all_tgts_lost_on_update_get \
 	dfu_target_fail_on_update_get \
 	-- -argstest targets=3
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest dfu_all_tgts_lost_on_update_get_psa \
 	dfu_cli_all_targets_lost_on_update_get \
 	dfu_target_fail_on_update_get \
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_verify.sh b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_verify.sh
index 5daedaca71d..f287288d1d4 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_verify.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_all_targets_lost_on_verify.sh
@@ -16,7 +16,7 @@ RunTest dfu_all_tgts_lost_on_verify \
 	dfu_target_fail_on_verify \
 	-- -argstest targets=3
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest dfu_all_tgts_lost_on_verify_psa \
 	dfu_cli_all_targets_lost_on_verify \
 	dfu_target_fail_on_verify \
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_persistent_transfer.sh b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_persistent_transfer.sh
index 2ff4a696639..881fda52b09 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_persistent_transfer.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_cli_persistent_transfer.sh
@@ -15,7 +15,7 @@ RunTest dfu_persistency \
 	dfu_target_fail_on_apply \
 	dfu_target_fail_on_nothing
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest dfu_persistency_psa \
 	dfu_cli_fail_on_persistency \
 	dfu_target_fail_on_metadata \
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_dist_self_update.sh b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_dist_self_update.sh
index 5c00349f24e..017d5984c3d 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_dist_self_update.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_dist_self_update.sh
@@ -7,5 +7,5 @@ source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 overlay=overlay_pst_conf
 RunTest dfu_self_update dfu_dist_dfu_self_update -- -argstest targets=1
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest dfu_self_update_psa dfu_dist_dfu_self_update -- -argstest targets=1
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_dist_self_update_mult_targets.sh b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_dist_self_update_mult_targets.sh
index 42087f1ad13..081c4e00a11 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_dist_self_update_mult_targets.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_dist_self_update_mult_targets.sh
@@ -8,6 +8,6 @@ overlay=overlay_pst_conf
 RunTest dfu_self_update_no_change \
     dfu_dist_dfu_self_update dfu_target_dfu_no_change -- -argstest targets=2
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest dfu_self_update_no_change_psa \
     dfu_dist_dfu_self_update dfu_target_dfu_no_change -- -argstest targets=2
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_mixed.sh b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_mixed.sh
index 1c5ff82d8fb..cf0864ef60c 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_mixed.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_mixed.sh
@@ -9,6 +9,6 @@ overlay=overlay_pst_conf
 RunTest dfu_mixed dfu_dist_dfu dfu_target_dfu_unprov dfu_target_dfu_no_change \
 	dfu_target_dfu_new_comp_rpr dfu_target_dfu_new_comp_no_rpr -- -argstest targets=4
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest dfu_mixed_psa dfu_dist_dfu dfu_target_dfu_unprov dfu_target_dfu_no_change \
 	dfu_target_dfu_new_comp_rpr dfu_target_dfu_new_comp_no_rpr -- -argstest targets=4
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_mixed_fail.sh b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_mixed_fail.sh
index 3382e458b2e..28598fe4789 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_mixed_fail.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_mixed_fail.sh
@@ -10,7 +10,7 @@ RunTest dfu_mixed_fail dfu_dist_dfu dfu_target_dfu_unprov dfu_target_dfu_no_chan
 	dfu_target_dfu_new_comp_rpr dfu_target_dfu_new_comp_no_rpr -- -argstest targets=4 \
 	fail-confirm=1
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest dfu_mixed_fail_psa dfu_dist_dfu dfu_target_dfu_unprov dfu_target_dfu_no_change \
 	dfu_target_dfu_new_comp_rpr dfu_target_dfu_new_comp_no_rpr -- -argstest targets=4 \
 	fail-confirm=1
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_slot.sh b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_slot.sh
index 587908c6497..4f6f4b2349f 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_slot.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_slot.sh
@@ -20,7 +20,7 @@ RunTestFlash dfu_slot dfu_dist_dfu_slot_delete_all
 
 RunTestFlash dfu_slot dfu_dist_dfu_slot_check_delete_all -flash_rm
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash dfu_slot_psa dfu_dist_dfu_slot_create -flash_erase
 
 RunTestFlash dfu_slot_psa dfu_dist_dfu_slot_create_recover
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_slot_idempotency.sh b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_slot_idempotency.sh
index abce47dba13..2aadd6b14b0 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_slot_idempotency.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_slot_idempotency.sh
@@ -8,5 +8,5 @@ source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 overlay=overlay_pst_conf
 RunTest dfu_slot_idempotency dfu_dist_dfu_slot_idempotency
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest dfu_slot_idempotency_psa dfu_dist_dfu_slot_idempotency
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_slot_reservation.sh b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_slot_reservation.sh
index 0ce234116b2..ee0eec53d4f 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_slot_reservation.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_slot_reservation.sh
@@ -8,5 +8,5 @@ source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 overlay=overlay_pst_conf
 RunTest dfu_slot_reservation dfu_dist_dfu_slot_reservation
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest dfu_slot_reservation_psa dfu_dist_dfu_slot_reservation
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_srv_recovery.sh b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_srv_recovery.sh
index 62a30c2e816..61b98becbca 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_srv_recovery.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_srv_recovery.sh
@@ -40,28 +40,28 @@ RunTestFlash dfu_dist_recover_phase \
   -- -argstest recover=1 expected-phase=8
 
 # The same test but with PSA crypto
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash dfu_dist_recover_phase_psa \
   dfu_cli_stop -flash_erase dfu_target_dfu_stop -flash_erase \
   -- -argstest recover=0 expected-phase=2
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash dfu_dist_recover_phase_psa \
   dfu_cli_stop dfu_target_dfu_stop \
   -- -argstest recover=1 expected-phase=3
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash dfu_dist_recover_phase_psa \
   dfu_cli_stop dfu_target_dfu_stop \
   -- -argstest recover=1 expected-phase=4
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash dfu_dist_recover_phase_psa \
   dfu_cli_stop dfu_target_dfu_stop \
   -- -argstest recover=1 expected-phase=6
 
 # Use phase `BT_MESH_DFU_PHASE_APPLY_SUCCESS` as marker to bring whole procedure to an end
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash dfu_dist_recover_phase_psa \
   dfu_cli_stop -flash_rm dfu_target_dfu_stop -flash_rm \
   -- -argstest recover=1 expected-phase=8
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_srv_recovery_verify_fail.sh b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_srv_recovery_verify_fail.sh
index c43d94e80cc..81d56754f2b 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_srv_recovery_verify_fail.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/dfu/dfu_srv_recovery_verify_fail.sh
@@ -21,12 +21,12 @@ RunTestFlash dfu_dist_recover_verify_fail \
   -- -argstest recover=1 expected-phase=6
 
 # The same test but with PSA crypto
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash dfu_dist_recover_verify_fail_psa \
   dfu_cli_stop -flash_erase dfu_target_dfu_stop -flash_erase \
   -- -argstest recover=0 expected-phase=5
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash dfu_dist_recover_verify_fail_psa \
   dfu_cli_stop -flash_rm dfu_target_dfu_stop -flash_rm \
   -- -argstest recover=1 expected-phase=6
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/friendship/msg_mesh.sh b/tests/bsim/bluetooth/mesh/tests_scripts/friendship/msg_mesh.sh
index f05261bb258..eed61d334d4 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/friendship/msg_mesh.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/friendship/msg_mesh.sh
@@ -4,12 +4,28 @@
 
 source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 
-# Test communication between the LPN and a third mesh device
+# Test communication between the LPN and a third mesh device.
+# Test scenario:
+# 1. LPN and Friend establish friendship.
+# 2. LPN sends unsegmented data to the third mesh device and receives unsegmented data back.
+# 3. LPN sends segmented data to the third mesh device and receives segmented data back.
+# 4. LPN publishes unsegmented data to the third device with friendship credentials.
+#    Friend should relay data to the third device with network credentials.
+#    The third mesh receives published data.
+# 5. LPN terminates friendship  and gets an event about termination.
+# 6. LPN sends unsegmented data to the third device outside of friendship and
+#    receives unsegmented data back.
 RunTest mesh_friendship_msg_mesh \
 	friendship_lpn_msg_mesh \
 	friendship_other_msg \
 	friendship_friend_est
 
+overlay=overlay_lpn_scan_on_conf
+RunTest mesh_friendship_msg_mesh_lpn_scan_on \
+	friendship_lpn_msg_mesh \
+	friendship_other_msg \
+	friendship_friend_est
+
 overlay=overlay_psa_conf
 RunTest mesh_friendship_msg_mesh_psa \
 	friendship_lpn_msg_mesh \
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp0_data_split.sh b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp0_data_split.sh
index dcaba598a57..e4c2385779f 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp0_data_split.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp0_data_split.sh
@@ -9,20 +9,20 @@ source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 #
 # Test procedure:
 # 0. Provisioning and setup. Server and client has same comp data.
-# 1. Client requests a sample exceeding the maximum avaialble payload from the
+# 1. Client requests a sample exceeding the maximum available payload from the
 #    server's composition data.
 # 2. Client fetch its local comp data.
 # 3. When server status arrive, remove status field data and compare received
 #    comp data with corresponding bytes in local comp data.
 # 4. Client requests the next sample from server's composition data.
 # 5. When server status arrive, remove status field data and compare received
-#    comp data with correspending bytes in local comp data.
+#    comp data with corresponding bytes in local comp data.
 # 6. Client merges the two samples and checks that the collected data is
 #    correctly merged, continuous, and matches its local comp data.
 overlay=overlay_pst_conf
 RunTest mesh_lcd_test_comp0_data_split \
 	lcd_srv_comp_data_status_respond lcd_cli_split_comp_data_request -- -argstest page=0
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_lcd_test_comp0_data_split \
 	lcd_srv_comp_data_status_respond lcd_cli_split_comp_data_request -- -argstest page=0
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp0_data_split_dfu.sh b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp0_data_split_dfu.sh
index 004a5224961..22f17d606ed 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp0_data_split_dfu.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp0_data_split_dfu.sh
@@ -10,14 +10,14 @@ source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 #
 # Test procedure:
 # 0. Provisioning and setup. Server and client has same comp data.
-# 1. Client requests a sample exceeding the maximum avaialble payload from the
+# 1. Client requests a sample exceeding the maximum available payload from the
 #    server's composition data.
 # 2. Client fetch its local comp data.
 # 3. When server status arrive, remove status field data and compare received
 #    comp data with corresponding bytes in local comp data.
 # 4. Client requests the next sample from server's composition data.
 # 5. When server status arrive, remove status field data and compare received
-#    comp data with correspending bytes in local comp data.
+#    comp data with corresponding bytes in local comp data.
 # 6. Client merges the two samples and checks that the collected data is
 #    correctly merged, continuous, and matches its local comp data.
 overlay=overlay_pst_conf
@@ -25,7 +25,7 @@ RunTest mesh_lcd_test_comp0_data_split_dfu \
 	lcd_srv_comp_data_status_respond \
 	lcd_cli_split_comp_data_request -- -argstest page=0 comp-changed-mode=1
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_lcd_test_comp0_data_split_dfu \
 	lcd_srv_comp_data_status_respond \
 	lcd_cli_split_comp_data_request -- -argstest page=0 comp-changed-mode=1
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp128_data_split.sh b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp128_data_split.sh
index f88db1b7391..7ce0be77bb6 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp128_data_split.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp128_data_split.sh
@@ -9,20 +9,20 @@ source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 #
 # Test procedure:
 # 0. Provisioning and setup. Server and client has same comp data.
-# 1. Client requests a sample exceeding the maximum avaialble payload from the
+# 1. Client requests a sample exceeding the maximum available payload from the
 #    server's composition data.
 # 2. Client fetch its local comp data.
 # 3. When server status arrive, remove status field data and compare received
 #    comp data with corresponding bytes in local comp data.
 # 4. Client requests the next sample from server's composition data.
 # 5. When server status arrive, remove status field data and compare received
-#    comp data with correspending bytes in local comp data.
+#    comp data with corresponding bytes in local comp data.
 # 6. Client merges the two samples and checks that the collected data is
 #    correctly merged, continuous, and matches its local comp data.
 overlay=overlay_pst_conf
 RunTest mesh_lcd_test_comp128_data_split \
 	lcd_srv_comp_data_status_respond lcd_cli_split_comp_data_request -- -argstest page=128
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_lcd_test_comp128_data_split \
 	lcd_srv_comp_data_status_respond lcd_cli_split_comp_data_request -- -argstest page=128
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp128_data_split_dfu.sh b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp128_data_split_dfu.sh
index 084125c79a4..75d3558ca60 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp128_data_split_dfu.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp128_data_split_dfu.sh
@@ -10,14 +10,14 @@ source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 #
 # Test procedure:
 # 0. Provisioning and setup. Server and client has same comp data.
-# 1. Client requests a sample exceeding the maximum avaialble payload from the
+# 1. Client requests a sample exceeding the maximum available payload from the
 #    server's composition data.
 # 2. Client fetch its local comp data.
 # 3. When server status arrive, remove status field data and compare received
 #    comp data with corresponding bytes in local comp data.
 # 4. Client requests the next sample from server's composition data.
 # 5. When server status arrive, remove status field data and compare received
-#    comp data with correspending bytes in local comp data.
+#    comp data with corresponding bytes in local comp data.
 # 6. Client merges the two samples and checks that the collected data is
 #    correctly merged, continuous, and matches its local comp data.
 overlay=overlay_pst_conf
@@ -25,7 +25,7 @@ RunTest mesh_lcd_test_comp128_data_split_dfu \
 	lcd_srv_comp_data_status_respond \
 	lcd_cli_split_comp_data_request -- -argstest page=128 comp-changed-mode=1
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_lcd_test_comp128_data_split_dfu \
 	lcd_srv_comp_data_status_respond \
 	lcd_cli_split_comp_data_request -- -argstest page=128 comp-changed-mode=1
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp129_data_split.sh b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp129_data_split.sh
index ab46d32048f..46915d73f74 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp129_data_split.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp129_data_split.sh
@@ -9,20 +9,20 @@ source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 #
 # Test procedure:
 # 0. Provisioning and setup. Server and client has same comp data.
-# 1. Client requests a sample exceeding the maximum avaialble payload from the
+# 1. Client requests a sample exceeding the maximum available payload from the
 #    server's composition data.
 # 2. Client fetch its local comp data.
 # 3. When server status arrive, remove status field data and compare received
 #    comp data with corresponding bytes in local comp data.
 # 4. Client requests the next sample from server's composition data.
 # 5. When server status arrive, remove status field data and compare received
-#    comp data with correspending bytes in local comp data.
+#    comp data with corresponding bytes in local comp data.
 # 6. Client merges the two samples and checks that the collected data is
 #    correctly merged, continuous, and matches its local comp data.
 overlay=overlay_pst_conf
 RunTest mesh_lcd_test_comp129_data_split \
 	lcd_srv_comp_data_status_respond lcd_cli_split_comp_data_request -- -argstest page=129
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_lcd_test_comp129_data_split \
 	lcd_srv_comp_data_status_respond lcd_cli_split_comp_data_request -- -argstest page=129
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp129_data_split_dfu.sh b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp129_data_split_dfu.sh
index 179c052e0ef..c77288d7de1 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp129_data_split_dfu.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp129_data_split_dfu.sh
@@ -10,14 +10,14 @@ source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 #
 # Test procedure:
 # 0. Provisioning and setup. Server and client has same comp data.
-# 1. Client requests a sample exceeding the maximum avaialble payload from the
+# 1. Client requests a sample exceeding the maximum available payload from the
 #    server's composition data.
 # 2. Client fetch its local comp data.
 # 3. When server status arrive, remove status field data and compare received
 #    comp data with corresponding bytes in local comp data.
 # 4. Client requests the next sample from server's composition data.
 # 5. When server status arrive, remove status field data and compare received
-#    comp data with correspending bytes in local comp data.
+#    comp data with corresponding bytes in local comp data.
 # 6. Client merges the two samples and checks that the collected data is
 #    correctly merged, continuous, and matches its local comp data.
 overlay=overlay_pst_conf
@@ -25,7 +25,7 @@ RunTest mesh_lcd_test_comp129_data_split_dfu \
 	lcd_srv_comp_data_status_respond \
 	lcd_cli_split_comp_data_request -- -argstest page=129 comp-changed-mode=1
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_lcd_test_comp129_data_split_dfu \
 	lcd_srv_comp_data_status_respond \
 	lcd_cli_split_comp_data_request -- -argstest page=129 comp-changed-mode=1
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp130_data_split.sh b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp130_data_split.sh
index eb25353581b..65f754564bf 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp130_data_split.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp130_data_split.sh
@@ -9,20 +9,20 @@ source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 #
 # Test procedure:
 # 0. Provisioning and setup. Server and client has same comp data.
-# 1. Client requests a sample exceeding the maximum avaialble payload from the
+# 1. Client requests a sample exceeding the maximum available payload from the
 #    server's composition data.
 # 2. Client fetch its local comp data.
 # 3. When server status arrive, remove status field data and compare received
 #    comp data with corresponding bytes in local comp data.
 # 4. Client requests the next sample from server's composition data.
 # 5. When server status arrive, remove status field data and compare received
-#    comp data with correspending bytes in local comp data.
+#    comp data with corresponding bytes in local comp data.
 # 6. Client merges the two samples and checks that the collected data is
 #    correctly merged, continuous, and matches its local comp data.
 overlay=overlay_pst_conf
 RunTest mesh_lcd_test_comp130_data_split \
 	lcd_srv_comp_data_status_respond lcd_cli_split_comp_data_request -- -argstest page=130
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_lcd_test_comp130_data_split \
 	lcd_srv_comp_data_status_respond lcd_cli_split_comp_data_request -- -argstest page=130
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp130_data_split_dfu.sh b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp130_data_split_dfu.sh
index a667f53abc8..42a2fe4346d 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp130_data_split_dfu.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp130_data_split_dfu.sh
@@ -10,14 +10,14 @@ source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 #
 # Test procedure:
 # 0. Provisioning and setup. Server and client has same comp data.
-# 1. Client requests a sample exceeding the maximum avaialble payload from the
+# 1. Client requests a sample exceeding the maximum available payload from the
 #    server's composition data.
 # 2. Client fetch its local comp data.
 # 3. When server status arrive, remove status field data and compare received
 #    comp data with corresponding bytes in local comp data.
 # 4. Client requests the next sample from server's composition data.
 # 5. When server status arrive, remove status field data and compare received
-#    comp data with correspending bytes in local comp data.
+#    comp data with corresponding bytes in local comp data.
 # 6. Client merges the two samples and checks that the collected data is
 #    correctly merged, continuous, and matches its local comp data.
 overlay=overlay_pst_conf
@@ -25,7 +25,7 @@ RunTest mesh_lcd_test_comp130_data_split_dfu \
 	lcd_srv_comp_data_status_respond \
 	lcd_cli_split_comp_data_request -- -argstest page=130 comp-changed-mode=1
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_lcd_test_comp130_data_split_dfu \
 	lcd_srv_comp_data_status_respond \
 	lcd_cli_split_comp_data_request -- -argstest page=130 comp-changed-mode=1
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp1_data_split.sh b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp1_data_split.sh
index 06312cf558b..6a897e1051d 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp1_data_split.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp1_data_split.sh
@@ -9,20 +9,20 @@ source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 #
 # Test procedure:
 # 0. Provisioning and setup. Server and client has same comp data.
-# 1. Client requests a sample exceeding the maximum avaialble payload from the
+# 1. Client requests a sample exceeding the maximum available payload from the
 #    server's composition data.
 # 2. Client fetch its local comp data.
 # 3. When server status arrive, remove status field data and compare received
 #    comp data with corresponding bytes in local comp data.
 # 4. Client requests the next sample from server's composition data.
 # 5. When server status arrive, remove status field data and compare received
-#    comp data with correspending bytes in local comp data.
+#    comp data with corresponding bytes in local comp data.
 # 6. Client merges the two samples and checks that the collected data is
 #    correctly merged, continuous, and matches its local comp data.
 overlay=overlay_pst_conf
 RunTest mesh_lcd_test_comp1_data_split \
 	lcd_srv_comp_data_status_respond lcd_cli_split_comp_data_request -- -argstest page=1
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_lcd_test_comp1_data_split \
 	lcd_srv_comp_data_status_respond lcd_cli_split_comp_data_request -- -argstest page=1
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp1_data_split_dfu.sh b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp1_data_split_dfu.sh
index 61f19ea3dcc..5ef6b22a43d 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp1_data_split_dfu.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp1_data_split_dfu.sh
@@ -10,14 +10,14 @@ source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 #
 # Test procedure:
 # 0. Provisioning and setup. Server and client has same comp data.
-# 1. Client requests a sample exceeding the maximum avaialble payload from the
+# 1. Client requests a sample exceeding the maximum available payload from the
 #    server's composition data.
 # 2. Client fetch its local comp data.
 # 3. When server status arrive, remove status field data and compare received
 #    comp data with corresponding bytes in local comp data.
 # 4. Client requests the next sample from server's composition data.
 # 5. When server status arrive, remove status field data and compare received
-#    comp data with correspending bytes in local comp data.
+#    comp data with corresponding bytes in local comp data.
 # 6. Client merges the two samples and checks that the collected data is
 #    correctly merged, continuous, and matches its local comp data.
 overlay=overlay_pst_conf
@@ -25,7 +25,7 @@ RunTest mesh_lcd_test_comp1_data_split_dfu \
 	lcd_srv_comp_data_status_respond \
 	lcd_cli_split_comp_data_request -- -argstest page=1 comp-changed-mode=1
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_lcd_test_comp1_data_split_dfu \
 	lcd_srv_comp_data_status_respond \
 	lcd_cli_split_comp_data_request -- -argstest page=1 comp-changed-mode=1
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp2_data_split.sh b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp2_data_split.sh
index 3da45434ee1..ac7de27b629 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp2_data_split.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp2_data_split.sh
@@ -9,20 +9,20 @@ source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 #
 # Test procedure:
 # 0. Provisioning and setup. Server and client has same comp data.
-# 1. Client requests a sample exceeding the maximum avaialble payload from the
+# 1. Client requests a sample exceeding the maximum available payload from the
 #    server's composition data.
 # 2. Client fetch its local comp data.
 # 3. When server status arrive, remove status field data and compare received
 #    comp data with corresponding bytes in local comp data.
 # 4. Client requests the next sample from server's composition data.
 # 5. When server status arrive, remove status field data and compare received
-#    comp data with correspending bytes in local comp data.
+#    comp data with corresponding bytes in local comp data.
 # 6. Client merges the two samples and checks that the collected data is
 #    correctly merged, continuous, and matches its local comp data.
 overlay=overlay_pst_conf
 RunTest mesh_lcd_test_comp2_data_split \
 	lcd_srv_comp_data_status_respond lcd_cli_split_comp_data_request -- -argstest page=2
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_lcd_test_comp2_data_split \
 	lcd_srv_comp_data_status_respond lcd_cli_split_comp_data_request -- -argstest page=2
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp2_data_split_dfu.sh b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp2_data_split_dfu.sh
index 8ad929f1374..19c0961da7d 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp2_data_split_dfu.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp2_data_split_dfu.sh
@@ -10,14 +10,14 @@ source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 #
 # Test procedure:
 # 0. Provisioning and setup. Server and client has same comp data.
-# 1. Client requests a sample exceeding the maximum avaialble payload from the
+# 1. Client requests a sample exceeding the maximum available payload from the
 #    server's composition data.
 # 2. Client fetch its local comp data.
 # 3. When server status arrive, remove status field data and compare received
 #    comp data with corresponding bytes in local comp data.
 # 4. Client requests the next sample from server's composition data.
 # 5. When server status arrive, remove status field data and compare received
-#    comp data with correspending bytes in local comp data.
+#    comp data with corresponding bytes in local comp data.
 # 6. Client merges the two samples and checks that the collected data is
 #    correctly merged, continuous, and matches its local comp data.
 overlay=overlay_pst_conf
@@ -25,7 +25,7 @@ RunTest mesh_lcd_test_comp2_data_split_dfu \
 	lcd_srv_comp_data_status_respond \
 	lcd_cli_split_comp_data_request -- -argstest page=2 comp-changed-mode=1
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_lcd_test_comp2_data_split_dfu \
 	lcd_srv_comp_data_status_respond \
 	lcd_cli_split_comp_data_request -- -argstest page=2 comp-changed-mode=1
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp_data_max_sdu.sh b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp_data_max_sdu.sh
index 71a692fa22c..ada62f65c2b 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp_data_max_sdu.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_comp_data_max_sdu.sh
@@ -18,6 +18,6 @@ overlay=overlay_pst_conf
 RunTest mesh_lcd_test_max_access_payload \
 	lcd_cli_max_sdu_comp_data_request lcd_srv_comp_data_status_respond
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_lcd_test_max_access_payload_psa \
 	lcd_cli_max_sdu_comp_data_request lcd_srv_comp_data_status_respond
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_metadata_max_sdu.sh b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_metadata_max_sdu.sh
index ef0f5712526..ca95095f150 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_metadata_max_sdu.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_metadata_max_sdu.sh
@@ -19,6 +19,6 @@ overlay=overlay_pst_conf
 RunTest mesh_lcd_test_max_metadata_access_payload \
 	lcd_cli_max_sdu_metadata_request lcd_srv_metadata_status_respond
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_lcd_test_max_metadata_access_payload_psa \
 	lcd_cli_max_sdu_metadata_request lcd_srv_metadata_status_respond
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_metadata_split.sh b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_metadata_split.sh
index 5003c5789b4..09d332eef79 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_metadata_split.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/large_comp_data/get_metadata_split.sh
@@ -22,6 +22,6 @@ overlay=overlay_pst_conf
 RunTest mesh_lcd_test_split_metadata \
 	lcd_cli_split_metadata_request lcd_srv_metadata_status_respond
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_lcd_test_split_metadata_psa \
 	lcd_cli_split_metadata_request lcd_srv_metadata_status_respond
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/persistence/access.sh b/tests/bsim/bluetooth/mesh/tests_scripts/persistence/access.sh
index cf9ec54faec..c7c97e598e0 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/persistence/access.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/persistence/access.sh
@@ -31,25 +31,25 @@ overlay=overlay_pst_conf
 RunTestFlash mesh_pst_access_data_check persistence_access_data_load -flash_rm \
 	-- -argstest access-cfg=not-configured
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash mesh_pst_access_data_check_psa persistence_access_data_save -flash_erase
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash mesh_pst_access_data_check_psa persistence_access_data_load \
 	-- -argstest access-cfg=configured
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash mesh_pst_access_data_check_psa persistence_access_sub_overwrite \
 	-- -argstest access-cfg=configured
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash mesh_pst_access_data_check_psa persistence_access_data_load \
 	-- -argstest access-cfg=new-subs
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash mesh_pst_access_data_check_psa persistence_access_data_remove \
 	-- -argstest access-cfg=new-subs
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash mesh_pst_access_data_check_psa persistence_access_data_load -flash_rm \
 	-- -argstest access-cfg=not-configured
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/persistence/cfg.sh b/tests/bsim/bluetooth/mesh/tests_scripts/persistence/cfg.sh
index f9655ef7462..2fb7179d536 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/persistence/cfg.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/persistence/cfg.sh
@@ -24,18 +24,18 @@ overlay=overlay_pst_conf
 RunTestFlash mesh_pst_cfg_check persistence_cfg_load -flash_rm \
     -- -argstest stack-cfg=1
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash mesh_pst_cfg_check_psa persistence_cfg_save -flash_erase \
     -- -argstest stack-cfg=0
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash mesh_pst_cfg_check_psa persistence_cfg_load -flash_rm \
     -- -argstest stack-cfg=0
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash mesh_pst_cfg_check_psa persistence_cfg_save -flash_erase \
     -- -argstest stack-cfg=1
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash mesh_pst_cfg_check_psa persistence_cfg_load -flash_rm \
     -- -argstest stack-cfg=1
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/persistence/provisioning.sh b/tests/bsim/bluetooth/mesh/tests_scripts/persistence/provisioning.sh
index 8dc7baa3e9d..e0fc41b87ad 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/persistence/provisioning.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/persistence/provisioning.sh
@@ -16,8 +16,8 @@ RunTestFlash mesh_pst_prov_data_check persistence_provisioning_data_save -flash_
 overlay=overlay_pst_conf
 RunTestFlash mesh_pst_prov_data_check persistence_provisioning_data_load -flash_rm
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash mesh_pst_prov_data_check_psa persistence_provisioning_data_save -flash_erase
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash mesh_pst_prov_data_check_psa persistence_provisioning_data_load -flash_rm
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/persistence/reprovisioning.sh b/tests/bsim/bluetooth/mesh/tests_scripts/persistence/reprovisioning.sh
index 511c04f766f..acf59f41845 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/persistence/reprovisioning.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/persistence/reprovisioning.sh
@@ -20,12 +20,12 @@ RunTest mesh_pst_repr persistence_reprovisioning_device \
 	-flash=../results/mesh_pst_repr/flash.bin -flash_rm \
 	persistence_reprovisioning_provisioner
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_pst_repr_psa persistence_reprovisioning_device \
     -flash=../results/mesh_pst_repr_psa/flash.bin -flash_erase \
 	persistence_reprovisioning_provisioner
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_pst_repr_psa persistence_reprovisioning_device \
 	-flash=../results/mesh_pst_repr_psa/flash.bin -flash_rm \
 	persistence_reprovisioning_provisioner
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/priv_beacon/priv_proxy_net_id.sh b/tests/bsim/bluetooth/mesh/tests_scripts/priv_beacon/priv_proxy_net_id.sh
index a431cdd9f6b..5aaf636073a 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/priv_beacon/priv_proxy_net_id.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/priv_beacon/priv_proxy_net_id.sh
@@ -4,12 +4,12 @@
 
 source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 
-# Test Private Net ID advertisment
+# Test Private Net ID advertisement
 #
 # Test procedure:
 # 0. TX device disables GATT proxy and enables Private GATT proxy.
-# 1. RX device enables scanner and scans for Net ID advertisments.
-# 2. RX device scans for a single Net ID advertisment and stores
+# 1. RX device enables scanner and scans for Net ID advertisements.
+# 2. RX device scans for a single Net ID advertisement and stores
 #    the random field of that message.
 # 3. RX device waits for 10 minutes.
 # 4. RX device scans for a another Private Net ID advertisement and compares
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/priv_beacon/priv_proxy_net_id_multi.sh b/tests/bsim/bluetooth/mesh/tests_scripts/priv_beacon/priv_proxy_net_id_multi.sh
index cffb5adbeb0..249eba4449a 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/priv_beacon/priv_proxy_net_id_multi.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/priv_beacon/priv_proxy_net_id_multi.sh
@@ -4,7 +4,7 @@
 
 source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 
-# Test Private Net ID advertisment with multiple networks
+# Test Private Net ID advertisement with multiple networks
 #
 # Test procedure:
 # 0. TX device disables GATT proxy, adds a second network to the device
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/priv_beacon/priv_proxy_node_id.sh b/tests/bsim/bluetooth/mesh/tests_scripts/priv_beacon/priv_proxy_node_id.sh
index 2557c9c1506..c4d5ea29165 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/priv_beacon/priv_proxy_node_id.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/priv_beacon/priv_proxy_node_id.sh
@@ -4,12 +4,12 @@
 
 source $(dirname "${BASH_SOURCE[0]}")/../../_mesh_test.sh
 
-# Test Private Node ID advertisment
+# Test Private Node ID advertisement
 #
 # Test procedure:
 # 0. TX device disables GATT proxy and enables the Private Node
 #    Identity state for the network. Then it waits for the
-#    advertisment to complete.
+#    advertisement to complete.
 # 1. RX device enables scanner and scans for Private Node ID advertisements.
 # 2. RX device scans for a single Private Node ID advertisement and stores
 #    the random field of that message. Then it waits for the
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/provision/pb_remote_pst_ncrp.sh b/tests/bsim/bluetooth/mesh/tests_scripts/provision/pb_remote_pst_ncrp.sh
index 2bba5147d8f..a7d7255155a 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/provision/pb_remote_pst_ncrp.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/provision/pb_remote_pst_ncrp.sh
@@ -53,21 +53,21 @@ RunTestFlash mesh_prov_pst_pb_remote_ncrp \
 
 # The same test but with PSA crypto
 # Step 1
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash mesh_prov_pst_pb_remote_ncrp_psa \
 	prov_provisioner_pb_remote_client_ncrp_provision -flash_erase \
 	prov_device_pb_remote_server_unproved -flash_erase \
 	prov_device_pb_remote_server_ncrp_prepare -flash_erase
 
 # Step 2
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash mesh_prov_pst_pb_remote_ncrp_psa \
 	prov_provisioner_pb_remote_client_ncrp \
 	prov_device_pb_remote_server_proved \
 	prov_device_pb_remote_server_ncrp
 
 # Step 3
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash mesh_prov_pst_pb_remote_ncrp_psa \
 	prov_provisioner_pb_remote_client_ncrp_second_time -flash_rm \
 	prov_device_pb_remote_server_proved -flash_rm \
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/proxy_sol/sol_beacon_rcvd.sh b/tests/bsim/bluetooth/mesh/tests_scripts/proxy_sol/sol_beacon_rcvd.sh
index fb4cc54c7e0..f169884aa0d 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/proxy_sol/sol_beacon_rcvd.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/proxy_sol/sol_beacon_rcvd.sh
@@ -13,7 +13,7 @@ RunTest proxy_sol_beacon_rcvd \
 	proxy_sol_tester_beacon_rcvd \
 	proxy_sol_iut_beacon_send
 
-overlay="overlay_pst_conf_overlay_gatt_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_gatt_conf_overlay_psa_conf"
 RunTest proxy_sol_beacon_rcvd_psa \
 	proxy_sol_tester_beacon_rcvd \
 	proxy_sol_iut_beacon_send
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/proxy_sol/sol_replay.sh b/tests/bsim/bluetooth/mesh/tests_scripts/proxy_sol/sol_replay.sh
index 02f7c933254..6aa0c0f0a58 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/proxy_sol/sol_replay.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/proxy_sol/sol_replay.sh
@@ -44,13 +44,13 @@ RunTest mesh_srpl_replay_attack_workq \
 	proxy_sol_iut_power_replay_attack \
 	-flash=../results/mesh_srpl_replay_attack/flash.bin -flash_rm
 
-overlay="overlay_pst_conf_overlay_gatt_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_gatt_conf_overlay_psa_conf"
 RunTest mesh_srpl_replay_attack_psa \
 	proxy_sol_tester_immediate_replay_attack \
 	proxy_sol_iut_immediate_replay_attack \
 	-flash=../results/mesh_srpl_replay_attack_psa/flash.bin -flash_erase
 
-overlay="overlay_pst_conf_overlay_gatt_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_gatt_conf_overlay_psa_conf"
 RunTest mesh_srpl_replay_attack_psa \
 	proxy_sol_tester_power_replay_attack \
 	proxy_sol_iut_power_replay_attack \
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/replay_cache/replay_attack.sh b/tests/bsim/bluetooth/mesh/tests_scripts/replay_cache/replay_attack.sh
index d09e014bd0e..bba7a4e2571 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/replay_cache/replay_attack.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/replay_cache/replay_attack.sh
@@ -14,12 +14,12 @@ RunTest mesh_replay_attack \
     rpc_tx_power_replay_attack \
     rpc_rx_power_replay_attack -flash=../results/mesh_replay_attack/flash.bin -flash_rm
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_replay_attack_psa \
     rpc_tx_immediate_replay_attack \
     rpc_rx_immediate_replay_attack -flash=../results/mesh_replay_attack_psa/flash.bin -flash_erase
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_replay_attack_psa \
     rpc_tx_power_replay_attack \
     rpc_rx_power_replay_attack -flash=../results/mesh_replay_attack_psa/flash.bin -flash_rm
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/replay_cache/rpl_frag.sh b/tests/bsim/bluetooth/mesh/tests_scripts/replay_cache/rpl_frag.sh
index 7212b567a24..69cfc47d677 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/replay_cache/rpl_frag.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/replay_cache/rpl_frag.sh
@@ -21,11 +21,11 @@ overlay=overlay_pst_conf
 RunTest mesh_replay_fragmentation \
     rpc_rx_reboot_after_defrag -flash=../results/mesh_replay_fragmentation/flash.bin -flash_rm
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_replay_fragmentation_psa \
     rpc_rx_rpl_frag -flash=../results/mesh_replay_fragmentation_psa/flash.bin -flash_erase \
     rpc_tx_rpl_frag
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTest mesh_replay_fragmentation_psa \
     rpc_rx_reboot_after_defrag -flash=../results/mesh_replay_fragmentation_psa/flash.bin -flash_rm
diff --git a/tests/bsim/bluetooth/mesh/tests_scripts/sar/sar_cfg_persistent_storage.sh b/tests/bsim/bluetooth/mesh/tests_scripts/sar/sar_cfg_persistent_storage.sh
index 0e67d5ab4d5..71cf45d08c3 100755
--- a/tests/bsim/bluetooth/mesh/tests_scripts/sar/sar_cfg_persistent_storage.sh
+++ b/tests/bsim/bluetooth/mesh/tests_scripts/sar/sar_cfg_persistent_storage.sh
@@ -12,6 +12,6 @@ overlay=overlay_pst_conf
 RunTestFlash sar_persistence sar_srv_cfg_store -flash_erase
 RunTestFlash sar_persistence sar_srv_cfg_restore -flash_rm
 
-overlay="overlay_pst_conf_overlay_psa_conf"
+overlay="overlay_pst_conf_overlay_ss_conf_overlay_psa_conf"
 RunTestFlash sar_persistence_psa sar_srv_cfg_store -flash_erase
 RunTestFlash sar_persistence_psa sar_srv_cfg_restore -flash_rm
diff --git a/tests/bsim/bluetooth/tester/CMakeLists.txt b/tests/bsim/bluetooth/tester/CMakeLists.txt
new file mode 100644
index 00000000000..136e98e5f99
--- /dev/null
+++ b/tests/bsim/bluetooth/tester/CMakeLists.txt
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(tester_bsim)
+
+# This contains babblesim-specific helpers, e.g. device synchronization.
+add_subdirectory(${ZEPHYR_BASE}/tests/bsim/babblekit babblekit)
+target_link_libraries(app PRIVATE babblekit)
+
+zephyr_include_directories(
+  ${BSIM_COMPONENTS_PATH}/libUtilv1/src/
+  ${BSIM_COMPONENTS_PATH}/libPhyComv1/src/
+  )
+
+zephyr_include_directories(
+  src/
+  ${ZEPHYR_BASE}/tests/bluetooth/tester/src
+  ${ZEPHYR_BASE}/tests/bluetooth/tester/src/btp
+  ${ZEPHYR_BASE}/tests/bluetooth/tester/src/audio/btp
+)
+
+target_sources(app PRIVATE
+  src/bsim_btp.c
+  src/test_main.c
+  src/host/gap_central.c
+  src/host/gap_peripheral.c
+)
diff --git a/tests/bsim/bluetooth/tester/Kconfig b/tests/bsim/bluetooth/tester/Kconfig
new file mode 100644
index 00000000000..5b863af7a3e
--- /dev/null
+++ b/tests/bsim/bluetooth/tester/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+module = BSIM_BTTESTER
+module-str = bsim_bttester
+source "subsys/logging/Kconfig.template.log_config"
+
+source "Kconfig.zephyr"
diff --git a/tests/bsim/bluetooth/tester/boards/nrf52_bsim.overlay b/tests/bsim/bluetooth/tester/boards/nrf52_bsim.overlay
new file mode 100644
index 00000000000..e7c4c36ff5b
--- /dev/null
+++ b/tests/bsim/bluetooth/tester/boards/nrf52_bsim.overlay
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+&uart0 {
+	hw-flow-control;
+};
diff --git a/tests/bsim/bluetooth/tester/compile.sh b/tests/bsim/bluetooth/tester/compile.sh
new file mode 100755
index 00000000000..1e6f5725df0
--- /dev/null
+++ b/tests/bsim/bluetooth/tester/compile.sh
@@ -0,0 +1,21 @@
+#!/usr/bin/env bash
+# Copyright 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Compile all the applications needed by the bsim tests in these subfolders
+
+#set -x #uncomment this line for debugging
+set -ue
+
+source ${ZEPHYR_BASE}/tests/bsim/compile.source
+
+: "${ZEPHYR_BASE:?ZEPHYR_BASE must be set to point to the zephyr root directory}"
+
+# We only want to build the tests/bsim/bluetooth/tester/ application for the nrf52_bsim/native board
+# as we do not gain anything from running this application for the nrf5340bsim_nrf5340_cpuapp and
+# it is not worth the added complexity to run it with anything but nrf52_bsim/native
+west twister -T ${ZEPHYR_BASE}/tests/bsim/bluetooth/tester/
+
+west twister -p ${BOARD} -T ${ZEPHYR_BASE}/tests/bluetooth/tester/
+
+wait_for_background_jobs
diff --git a/tests/bsim/bluetooth/tester/prj.conf b/tests/bsim/bluetooth/tester/prj.conf
new file mode 100644
index 00000000000..63f141f4d39
--- /dev/null
+++ b/tests/bsim/bluetooth/tester/prj.conf
@@ -0,0 +1,14 @@
+CONFIG_ASSERT=y
+CONFIG_THREAD_NAME=y
+
+# Should not be necessary, but the bluetooth/buf.h header file require Bluetooth to be enabled, and
+# the header file is being included by some of the BTP header files
+CONFIG_BT=y
+
+CONFIG_UART_PIPE=n
+CONFIG_SERIAL=y
+
+CONFIG_LOG=y
+CONFIG_LOG_FUNC_NAME_PREFIX_ERR=y
+CONFIG_LOG_FUNC_NAME_PREFIX_WRN=y
+CONFIG_BSIM_BTTESTER_LOG_LEVEL_DBG=y
diff --git a/tests/bsim/bluetooth/tester/src/bsim_btp.c b/tests/bsim/bluetooth/tester/src/bsim_btp.c
new file mode 100644
index 00000000000..947dbb0fdf8
--- /dev/null
+++ b/tests/bsim/bluetooth/tester/src/bsim_btp.c
@@ -0,0 +1,1949 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdint.h>
+#include <stddef.h>
+#include <string.h>
+
+#include <zephyr/autoconf.h>
+#include <zephyr/bluetooth/audio/tbs.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/drivers/uart.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/byteorder.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sys_clock.h>
+
+#include "babblekit/testcase.h"
+
+#include "btp/btp.h"
+
+LOG_MODULE_REGISTER(bsim_btp, CONFIG_BSIM_BTTESTER_LOG_LEVEL);
+
+K_FIFO_DEFINE(btp_rsp_fifo);
+NET_BUF_POOL_FIXED_DEFINE(btp_rsp_pool, 1, BTP_MTU, 0, NULL);
+K_FIFO_DEFINE(btp_evt_fifo);
+NET_BUF_POOL_FIXED_DEFINE(btp_evt_pool, 100, BTP_MTU, 0, NULL);
+
+static const struct device *const dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_console));
+
+static bool is_valid_core_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_CORE_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_CORE_READ_SUPPORTED_SERVICES:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_CORE_REGISTER_SERVICE:
+		return buf_simple->len == 0U;
+	case BTP_CORE_UNREGISTER_SERVICE:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BTP_CORE_EV_IUT_READY:
+		return buf_simple->len == 0U;
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_gap_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_GAP_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_GAP_READ_CONTROLLER_INDEX_LIST:
+		if (hdr->len >= sizeof(struct btp_gap_read_controller_index_list_rp)) {
+			const struct btp_gap_read_controller_index_list_rp *rp =
+				net_buf_simple_pull_mem(
+					buf_simple,
+					sizeof(struct btp_gap_read_controller_index_list_rp));
+
+			return rp->num == buf_simple->len;
+		} else {
+			return false;
+		}
+	case BTP_GAP_READ_CONTROLLER_INFO:
+		return buf_simple->len == sizeof(struct btp_gap_read_controller_info_rp);
+	case BTP_GAP_RESET:
+		return buf_simple->len == sizeof(struct btp_gap_reset_rp);
+	case BTP_GAP_SET_POWERED:
+		return buf_simple->len == sizeof(struct btp_gap_set_powered_rp);
+	case BTP_GAP_SET_CONNECTABLE:
+		return buf_simple->len == sizeof(struct btp_gap_set_connectable_rp);
+	case BTP_GAP_SET_FAST_CONNECTABLE:
+		return buf_simple->len == sizeof(struct btp_gap_set_fast_connectable_rp);
+	case BTP_GAP_SET_DISCOVERABLE:
+		return buf_simple->len == sizeof(struct btp_gap_set_discoverable_rp);
+	case BTP_GAP_SET_BONDABLE:
+		return buf_simple->len == sizeof(struct btp_gap_set_bondable_rp);
+	case BTP_GAP_START_ADVERTISING:
+		return buf_simple->len == sizeof(struct btp_gap_start_advertising_rp);
+	case BTP_GAP_STOP_ADVERTISING:
+		return buf_simple->len == sizeof(struct btp_gap_stop_advertising_rp);
+	case BTP_GAP_START_DISCOVERY:
+		return buf_simple->len == 0U;
+	case BTP_GAP_STOP_DISCOVERY:
+		return buf_simple->len == 0U;
+	case BTP_GAP_CONNECT:
+		return buf_simple->len == 0U;
+	case BTP_GAP_DISCONNECT:
+		return buf_simple->len == 0U;
+	case BTP_GAP_SET_IO_CAP:
+		return buf_simple->len == 0U;
+	case BTP_GAP_PAIR:
+		return buf_simple->len == 0U;
+	case BTP_GAP_UNPAIR:
+		return buf_simple->len == 0U;
+	case BTP_GAP_PASSKEY_ENTRY:
+		return buf_simple->len == 0U;
+	case BTP_GAP_PASSKEY_CONFIRM:
+		return buf_simple->len == 0U;
+	case BTP_GAP_START_DIRECTED_ADV:
+		return buf_simple->len == sizeof(struct btp_gap_start_directed_adv_rp);
+	case BTP_GAP_CONN_PARAM_UPDATE:
+		return buf_simple->len == 0U;
+	case BTP_GAP_PAIRING_CONSENT:
+		return buf_simple->len == 0U;
+	case BTP_GAP_OOB_LEGACY_SET_DATA:
+		return buf_simple->len == 0U;
+	case BTP_GAP_OOB_SC_GET_LOCAL_DATA:
+		return buf_simple->len == sizeof(struct btp_gap_oob_sc_get_local_data_rp);
+	case BTP_GAP_OOB_SC_SET_REMOTE_DATA:
+		return buf_simple->len == 0U;
+	case BTP_GAP_SET_MITM:
+		return buf_simple->len == 0U;
+	case BTP_GAP_SET_FILTER_LIST:
+		return buf_simple->len == 0U;
+	case BTP_GAP_SET_EXTENDED_ADVERTISING:
+		return buf_simple->len == sizeof(struct btp_gap_set_extended_advertising_rp);
+	case BTP_GAP_PADV_CONFIGURE:
+		return buf_simple->len == sizeof(struct btp_gap_padv_start_rp);
+	case BTP_GAP_PADV_STOP:
+		return buf_simple->len == sizeof(struct btp_gap_padv_stop_rp);
+	case BTP_GAP_PADV_SET_DATA:
+		return buf_simple->len == 0U;
+	case BTP_GAP_PADV_CREATE_SYNC:
+		return buf_simple->len == 0U;
+	case BTP_GAP_PADV_SYNC_TRANSFER_SET_INFO:
+		return buf_simple->len == 0U;
+	case BTP_GAP_PADV_SYNC_TRANSFER_START:
+		return buf_simple->len == 0U;
+	case BTP_GAP_PADV_SYNC_TRANSFER_RECV:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BTP_GAP_EV_NEW_SETTINGS:
+		return buf_simple->len == sizeof(struct btp_gap_new_settings_ev);
+	case BTP_GAP_EV_DEVICE_FOUND:
+		if (hdr->len >= sizeof(struct btp_gap_device_found_ev)) {
+			const struct btp_gap_device_found_ev *ev = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_gap_device_found_ev));
+
+			return ev->eir_data_len == buf_simple->len;
+		} else {
+			return false;
+		}
+	case BTP_GAP_EV_DEVICE_CONNECTED:
+		return buf_simple->len == sizeof(struct btp_gap_device_connected_ev);
+	case BTP_GAP_EV_DEVICE_DISCONNECTED:
+		return buf_simple->len == sizeof(struct btp_gap_device_disconnected_ev);
+	case BTP_GAP_EV_PASSKEY_DISPLAY:
+		return buf_simple->len == sizeof(struct btp_gap_passkey_display_ev);
+	case BTP_GAP_EV_PASSKEY_ENTRY_REQ:
+		return buf_simple->len == sizeof(struct btp_gap_passkey_entry_req_ev);
+	case BTP_GAP_EV_PASSKEY_CONFIRM_REQ:
+		return buf_simple->len == sizeof(struct btp_gap_passkey_confirm_req_ev);
+	case BTP_GAP_EV_IDENTITY_RESOLVED:
+		return buf_simple->len == sizeof(struct btp_gap_identity_resolved_ev);
+	case BTP_GAP_EV_CONN_PARAM_UPDATE:
+		return buf_simple->len == sizeof(struct btp_gap_conn_param_update_ev);
+	case BTP_GAP_EV_SEC_LEVEL_CHANGED:
+		return buf_simple->len == sizeof(struct btp_gap_sec_level_changed_ev);
+	case BTP_GAP_EV_PAIRING_CONSENT_REQ:
+		return buf_simple->len == sizeof(struct btp_gap_pairing_consent_req_ev);
+	case BTP_GAP_EV_BOND_LOST:
+		return buf_simple->len == sizeof(struct btp_gap_bond_lost_ev);
+	case BTP_GAP_EV_PAIRING_FAILED:
+		return buf_simple->len == sizeof(struct btp_gap_bond_pairing_failed_ev);
+	case BTP_GAP_EV_PERIODIC_SYNC_ESTABLISHED:
+		return buf_simple->len == sizeof(struct btp_gap_ev_periodic_sync_established_ev);
+	case BTP_GAP_EV_PERIODIC_SYNC_LOST:
+		return buf_simple->len == sizeof(struct btp_gap_ev_periodic_sync_lost_ev);
+	case BTP_GAP_EV_PERIODIC_REPORT:
+		if (hdr->len >= sizeof(struct btp_gap_ev_periodic_report_ev)) {
+			const struct btp_gap_ev_periodic_report_ev *ev = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_gap_ev_periodic_report_ev));
+
+			return ev->data_len == buf_simple->len;
+		} else {
+			return false;
+		}
+	case BTP_GAP_EV_PERIODIC_TRANSFER_RECEIVED:
+		if (hdr->len >= sizeof(struct btp_gap_ev_periodic_transfer_received_ev)) {
+			const struct btp_gap_ev_periodic_transfer_received_ev *ev =
+				net_buf_simple_pull_mem(
+					buf_simple,
+					sizeof(struct btp_gap_ev_periodic_transfer_received_ev));
+
+			return ev->data_len == buf_simple->len;
+		} else {
+			return false;
+		}
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_gatt_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_GATT_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_GATT_ADD_SERVICE:
+		return buf_simple->len == sizeof(struct btp_gatt_add_service_rp);
+	case BTP_GATT_ADD_CHARACTERISTIC:
+		return buf_simple->len == sizeof(struct btp_gatt_add_characteristic_rp);
+	case BTP_GATT_ADD_DESCRIPTOR:
+		return buf_simple->len == sizeof(struct btp_gatt_add_descriptor_rp);
+	case BTP_GATT_ADD_INCLUDED_SERVICE:
+		return buf_simple->len == sizeof(struct btp_gatt_add_included_service_rp);
+	case BTP_GATT_SET_VALUE:
+		return buf_simple->len == 0U;
+	case BTP_GATT_START_SERVER:
+		return buf_simple->len == sizeof(struct btp_gatt_start_server_rp);
+	case BTP_GATT_RESET_SERVER:
+		return buf_simple->len == 0U;
+	case BTP_GATT_SET_ENC_KEY_SIZE:
+		return buf_simple->len == 0U;
+	case BTP_GATT_EXCHANGE_MTU:
+		return buf_simple->len == 0U;
+	case BTP_GATT_DISC_ALL_PRIM:
+		if (hdr->len >= sizeof(struct btp_gatt_disc_all_prim_rp)) {
+			const struct btp_gatt_disc_all_prim_rp *rp = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_gatt_disc_all_prim_rp));
+
+			for (uint8_t i = 0U; i < rp->services_count; i++) {
+				const struct btp_gatt_service *svc;
+
+				if (buf_simple->len < sizeof(*svc)) {
+					return false;
+				}
+
+				svc = net_buf_simple_pull_mem(buf_simple, sizeof(*svc));
+				if (buf_simple->len < svc->uuid_length) {
+					return false;
+				}
+			}
+
+			return buf_simple->len == 0U;
+		} else {
+			return false;
+		}
+	case BTP_GATT_DISC_PRIM_UUID:
+		if (hdr->len >= sizeof(struct btp_gatt_disc_prim_rp)) {
+			const struct btp_gatt_disc_prim_rp *rp = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_gatt_disc_prim_rp));
+
+			for (uint8_t i = 0U; i < rp->services_count; i++) {
+				const struct btp_gatt_service *svc;
+
+				if (buf_simple->len < sizeof(*svc)) {
+					return false;
+				}
+
+				svc = net_buf_simple_pull_mem(buf_simple, sizeof(*svc));
+				if (buf_simple->len < svc->uuid_length) {
+					return false;
+				}
+			}
+
+			return buf_simple->len == 0U;
+		} else {
+			return false;
+		}
+	case BTP_GATT_FIND_INCLUDED:
+		if (hdr->len >= sizeof(struct btp_gatt_find_included_rp)) {
+			const struct btp_gatt_find_included_rp *rp = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_gatt_find_included_rp));
+
+			for (uint8_t i = 0U; i < rp->services_count; i++) {
+				const struct btp_gatt_included *incl;
+
+				if (buf_simple->len < sizeof(*incl)) {
+					return false;
+				}
+
+				incl = net_buf_simple_pull_mem(buf_simple, sizeof(*incl));
+				if (buf_simple->len < incl->service.uuid_length) {
+					return false;
+				}
+			}
+
+			return buf_simple->len == 0U;
+		} else {
+			return false;
+		}
+	case BTP_GATT_DISC_ALL_CHRC:
+		if (hdr->len >= sizeof(struct btp_gatt_disc_chrc_rp)) {
+			const struct btp_gatt_disc_chrc_rp *rp = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_gatt_disc_chrc_rp));
+
+			for (uint8_t i = 0U; i < rp->characteristics_count; i++) {
+				const struct btp_gatt_characteristic *chrc;
+
+				if (buf_simple->len < sizeof(*chrc)) {
+					return false;
+				}
+
+				chrc = net_buf_simple_pull_mem(buf_simple, sizeof(*chrc));
+				if (buf_simple->len < chrc->uuid_length) {
+					return false;
+				}
+			}
+
+			return buf_simple->len == 0U;
+		} else {
+			return false;
+		}
+	case BTP_GATT_DISC_ALL_DESC:
+		if (hdr->len >= sizeof(struct btp_gatt_disc_all_desc_rp)) {
+			const struct btp_gatt_disc_all_desc_rp *rp = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_gatt_disc_all_desc_rp));
+
+			for (uint8_t i = 0U; i < rp->descriptors_count; i++) {
+				const struct btp_gatt_descriptor *desc;
+
+				if (buf_simple->len < sizeof(*desc)) {
+					return false;
+				}
+
+				desc = net_buf_simple_pull_mem(buf_simple, sizeof(*desc));
+				if (buf_simple->len < desc->uuid_length) {
+					return false;
+				}
+			}
+
+			return buf_simple->len == 0U;
+		} else {
+			return false;
+		}
+	case BTP_GATT_READ:
+		if (hdr->len >= sizeof(struct btp_gatt_read_rp)) {
+			const struct btp_gatt_read_rp *rp = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_gatt_read_rp));
+
+			return buf_simple->len == rp->data_length;
+		} else {
+			return false;
+		}
+	case BTP_GATT_READ_UUID:
+		if (hdr->len >= sizeof(struct btp_gatt_read_uuid_rp)) {
+			const struct btp_gatt_read_uuid_rp *rp = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_gatt_read_uuid_rp));
+
+			for (uint8_t i = 0U; i < rp->values_count; i++) {
+				const struct btp_gatt_char_value *value;
+
+				if (buf_simple->len < sizeof(*value)) {
+					return false;
+				}
+
+				value = net_buf_simple_pull_mem(buf_simple, sizeof(*value));
+				if (buf_simple->len < value->data_len) {
+					return false;
+				}
+			}
+
+			return buf_simple->len == 0U;
+		} else {
+			return false;
+		}
+	case BTP_GATT_READ_LONG:
+		if (hdr->len >= sizeof(struct btp_gatt_read_long_rp)) {
+			const struct btp_gatt_read_long_rp *rp = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_gatt_read_long_rp));
+
+			return buf_simple->len == rp->data_length;
+		} else {
+			return false;
+		}
+	case BTP_GATT_READ_MULTIPLE:
+		if (hdr->len >= sizeof(struct btp_gatt_read_multiple_rp)) {
+			const struct btp_gatt_read_multiple_rp *rp = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_gatt_read_multiple_rp));
+
+			return buf_simple->len == rp->data_length;
+		} else {
+			return false;
+		}
+	case BTP_GATT_WRITE_WITHOUT_RSP:
+		return buf_simple->len == 0U;
+	case BTP_GATT_SIGNED_WRITE_WITHOUT_RSP:
+		return buf_simple->len == 0U;
+	case BTP_GATT_WRITE:
+		return buf_simple->len == sizeof(struct btp_gatt_write_rp);
+	case BTP_GATT_WRITE_LONG:
+		return buf_simple->len == sizeof(struct btp_gatt_write_long_rp);
+	case BTP_GATT_RELIABLE_WRITE:
+		return buf_simple->len == sizeof(struct btp_gatt_reliable_write_rp);
+	case BTP_GATT_GET_ATTRIBUTES:
+		if (hdr->len >= sizeof(struct btp_gatt_get_attributes_rp)) {
+			const struct btp_gatt_get_attributes_rp *rp = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_gatt_get_attributes_rp));
+
+			return buf_simple->len == rp->attrs_count;
+		} else {
+			return false;
+		}
+	case BTP_GATT_GET_ATTRIBUTE_VALUE:
+		if (hdr->len >= sizeof(struct btp_gatt_get_attribute_value_rp)) {
+			const struct btp_gatt_get_attribute_value_rp *rp = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_gatt_get_attribute_value_rp));
+
+			return buf_simple->len == rp->value_length;
+		} else {
+			return false;
+		}
+	case BTP_GATT_CHANGE_DB:
+		return buf_simple->len == 0U;
+	case BTP_GATT_EATT_CONNECT:
+		return buf_simple->len == 0U;
+	case BTP_GATT_READ_MULTIPLE_VAR:
+		if (hdr->len >= sizeof(struct btp_gatt_read_multiple_var_rp)) {
+			const struct btp_gatt_read_multiple_var_rp *rp = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_gatt_read_multiple_var_rp));
+
+			return buf_simple->len == rp->data_length;
+		} else {
+			return false;
+		}
+	case BTP_GATT_NOTIFY_MULTIPLE:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BTP_GATT_EV_NOTIFICATION:
+		if (hdr->len >= sizeof(struct btp_gatt_notification_ev)) {
+			const struct btp_gatt_notification_ev *ev = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_gatt_notification_ev));
+
+			return ev->data_length == buf_simple->len;
+		} else {
+			return false;
+		}
+	case BTP_GATT_EV_ATTR_VALUE_CHANGED:
+		if (hdr->len >= sizeof(struct btp_gatt_attr_value_changed_ev)) {
+			const struct btp_gatt_attr_value_changed_ev *ev = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_gatt_attr_value_changed_ev));
+
+			return ev->data_length == buf_simple->len;
+		} else {
+			return false;
+		}
+
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_l2cap_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_L2CAP_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_L2CAP_CONNECT:
+		if (hdr->len >= sizeof(struct btp_l2cap_connect_rp)) {
+			const struct btp_l2cap_connect_rp *rp = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_l2cap_connect_rp));
+
+			return rp->num == buf_simple->len;
+		} else {
+			return false;
+		}
+	case BTP_L2CAP_DISCONNECT:
+		return buf_simple->len == 0U;
+	case BTP_L2CAP_SEND_DATA:
+		return buf_simple->len == 0U;
+	case BTP_L2CAP_LISTEN:
+		return buf_simple->len == 0U;
+	case BTP_L2CAP_ACCEPT_CONNECTION:
+		return buf_simple->len == 0U;
+	case BTP_L2CAP_RECONFIGURE:
+		return buf_simple->len == 0U;
+	case BTP_L2CAP_CREDITS:
+		return buf_simple->len == 0U;
+	case BTP_L2CAP_DISCONNECT_EATT_CHANS:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BTP_L2CAP_EV_CONNECTION_REQ:
+		return buf_simple->len == sizeof(struct btp_l2cap_connection_req_ev);
+	case BTP_L2CAP_EV_CONNECTED:
+		return buf_simple->len == sizeof(struct btp_l2cap_connected_ev);
+	case BTP_L2CAP_EV_DISCONNECTED:
+		return buf_simple->len == sizeof(struct btp_l2cap_disconnected_ev);
+	case BTP_L2CAP_EV_DATA_RECEIVED:
+		if (hdr->len >= sizeof(struct btp_gatt_attr_value_changed_ev)) {
+			const struct btp_gatt_attr_value_changed_ev *ev = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_gatt_attr_value_changed_ev));
+
+			return ev->data_length == buf_simple->len;
+		} else {
+			return false;
+		}
+	case BTP_L2CAP_EV_RECONFIGURED:
+		return buf_simple->len == sizeof(struct btp_l2cap_reconfigured_ev);
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_mesh_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_MESH_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_MESH_CONFIG_PROVISIONING:
+		return buf_simple->len == 0U;
+	case BTP_MESH_PROVISION_NODE:
+		return buf_simple->len == 0U;
+	case BTP_MESH_INIT:
+		return buf_simple->len == 0U;
+	case BTP_MESH_INPUT_STRING:
+		return buf_simple->len == 0U;
+	case BTP_MESH_IVU_TEST_MODE:
+		return buf_simple->len == 0U;
+	case BTP_MESH_IVU_TOGGLE_STATE:
+		return buf_simple->len == 0U;
+	case BTP_MESH_NET_SEND:
+		return buf_simple->len == 0U;
+	case BTP_MESH_HEALTH_GENERATE_FAULTS:
+		if (hdr->len >= sizeof(struct btp_mesh_health_generate_faults_rp)) {
+			const struct btp_mesh_health_generate_faults_rp *rp =
+				net_buf_simple_pull_mem(
+					buf_simple,
+					sizeof(struct btp_mesh_health_generate_faults_rp));
+
+			return (rp->cur_faults_count + rp->reg_faults_count) == buf_simple->len;
+		} else {
+			return false;
+		}
+	case BTP_MESH_HEALTH_CLEAR_FAULTS:
+		return buf_simple->len == 0U;
+	case BTP_MESH_LPN:
+		return buf_simple->len == 0U;
+	case BTP_MESH_LPN_POLL:
+		return buf_simple->len == 0U;
+	case BTP_MESH_MODEL_SEND:
+		return buf_simple->len == 0U;
+	case BTP_MESH_LPN_SUBSCRIBE:
+		return buf_simple->len == 0U;
+	case BTP_MESH_LPN_UNSUBSCRIBE:
+		return buf_simple->len == 0U;
+	case BTP_MESH_RPL_CLEAR:
+		return buf_simple->len == 0U;
+	case BTP_MESH_PROXY_IDENTITY:
+		return buf_simple->len == 0U;
+	case BTP_MESH_COMP_DATA_GET:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_MESH_CFG_BEACON_GET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_beacon_get_rp);
+	case BTP_MESH_CFG_BEACON_SET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_beacon_set_rp);
+	case BTP_MESH_CFG_DEFAULT_TTL_GET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_default_ttl_get_rp);
+	case BTP_MESH_CFG_DEFAULT_TTL_SET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_default_ttl_set_rp);
+	case BTP_MESH_CFG_GATT_PROXY_GET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_gatt_proxy_get_rp);
+	case BTP_MESH_CFG_GATT_PROXY_SET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_gatt_proxy_set_rp);
+	case BTP_MESH_CFG_FRIEND_GET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_friend_get_rp);
+	case BTP_MESH_CFG_FRIEND_SET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_friend_set_rp);
+	case BTP_MESH_CFG_RELAY_GET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_relay_get_rp);
+	case BTP_MESH_CFG_RELAY_SET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_relay_set_rp);
+	case BTP_MESH_CFG_MODEL_PUB_GET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_model_pub_get_rp);
+	case BTP_MESH_CFG_MODEL_PUB_SET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_model_pub_set_rp);
+	case BTP_MESH_CFG_MODEL_SUB_ADD:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_model_sub_add_rp);
+	case BTP_MESH_CFG_MODEL_SUB_DEL:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_model_sub_del_rp);
+	case BTP_MESH_CFG_NETKEY_ADD:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_netkey_add_rp);
+	case BTP_MESH_CFG_NETKEY_GET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_netkey_get_rp);
+	case BTP_MESH_CFG_NETKEY_DEL:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_netkey_del_rp);
+	case BTP_MESH_CFG_APPKEY_ADD:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_appkey_add_rp);
+	case BTP_MESH_CFG_APPKEY_DEL:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_appkey_del_rp);
+	case BTP_MESH_CFG_APPKEY_GET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_appkey_get_rp);
+	case BTP_MESH_CFG_MODEL_APP_BIND:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_model_app_bind_rp);
+	case BTP_MESH_CFG_MODEL_APP_UNBIND:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_model_app_unbind_rp);
+	case BTP_MESH_CFG_MODEL_APP_GET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_model_app_get_rp);
+	case BTP_MESH_CFG_MODEL_APP_VND_GET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_model_app_vnd_get_rp);
+	case BTP_MESH_CFG_HEARTBEAT_PUB_SET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_heartbeat_pub_set_rp);
+	case BTP_MESH_CFG_HEARTBEAT_PUB_GET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_heartbeat_pub_get_rp);
+	case BTP_MESH_CFG_HEARTBEAT_SUB_SET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_heartbeat_sub_set_rp);
+	case BTP_MESH_CFG_HEARTBEAT_SUB_GET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_heartbeat_sub_get_rp);
+	case BTP_MESH_CFG_NET_TRANS_GET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_net_trans_get_rp);
+	case BTP_MESH_CFG_NET_TRANS_SET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_net_trans_set_rp);
+	case BTP_MESH_CFG_MODEL_SUB_OVW:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_model_sub_ovw_rp);
+	case BTP_MESH_CFG_MODEL_SUB_DEL_ALL:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_model_sub_del_all_rp);
+	case BTP_MESH_CFG_MODEL_SUB_GET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_model_sub_get_rp);
+	case BTP_MESH_CFG_MODEL_SUB_GET_VND:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_model_sub_get_vnd_rp);
+	case BTP_MESH_CFG_MODEL_SUB_VA_ADD:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_model_sub_va_add_rp);
+	case BTP_MESH_CFG_MODEL_SUB_VA_DEL:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_model_sub_va_del_rp);
+	case BTP_MESH_CFG_MODEL_SUB_VA_OVW:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_model_sub_va_ovw_rp);
+	case BTP_MESH_CFG_NETKEY_UPDATE:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_netkey_update_rp);
+	case BTP_MESH_CFG_APPKEY_UPDATE:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_appkey_update_rp);
+	case BTP_MESH_CFG_NODE_IDT_SET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_node_idt_set_rp);
+	case BTP_MESH_CFG_NODE_IDT_GET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_node_idt_get_rp);
+	case BTP_MESH_CFG_NODE_RESET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_node_reset_rp);
+	case BTP_MESH_CFG_LPN_TIMEOUT_GET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_lpn_timeout_rp);
+	case BTP_MESH_CFG_MODEL_PUB_VA_SET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_model_pub_va_set_rp);
+	case BTP_MESH_CFG_MODEL_APP_BIND_VND:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_model_app_bind_vnd_rp);
+	case BTP_MESH_HEALTH_FAULT_GET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_HEALTH_FAULT_CLEAR:
+		return buf_simple->len == sizeof(struct btp_mesh_health_fault_clear_rp);
+	case BTP_MESH_HEALTH_FAULT_TEST:
+		return buf_simple->len == sizeof(struct btp_mesh_health_fault_test_rp);
+	case BTP_MESH_HEALTH_PERIOD_GET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_HEALTH_PERIOD_SET:
+		return buf_simple->len == sizeof(struct btp_mesh_health_period_set_rp);
+	case BTP_MESH_HEALTH_ATTENTION_GET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_HEALTH_ATTENTION_SET:
+		return buf_simple->len == sizeof(struct btp_mesh_health_attention_set_rp);
+	case BTP_MESH_PROVISION_ADV:
+		return buf_simple->len == 0U;
+	case BTP_MESH_CFG_KRP_GET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_krp_get_rp);
+	case BTP_MESH_CFG_KRP_SET:
+		return buf_simple->len == sizeof(struct btp_mesh_cfg_krp_set_rp);
+	case BTP_MESH_VA_ADD:
+		return buf_simple->len == sizeof(struct btp_mesh_va_add_rp);
+	case BTP_MESH_PROXY_CONNECT:
+		return buf_simple->len == 0U;
+	case BTP_MESH_SAR_TRANSMITTER_GET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_SAR_TRANSMITTER_SET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_SAR_RECEIVER_GET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_SAR_RECEIVER_SET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_LARGE_COMP_DATA_GET:
+		return true /* variable length */;
+	case BTP_MESH_MODELS_METADATA_GET:
+		return true /* variable length */;
+	case BTP_MESH_OPCODES_AGGREGATOR_INIT:
+		return buf_simple->len == 0U;
+	case BTP_MESH_OPCODES_AGGREGATOR_SEND:
+		return buf_simple->len == 0U;
+	case BTP_MESH_COMP_CHANGE_PREPARE:
+		return buf_simple->len == 0U;
+	case BTP_MESH_RPR_SCAN_START:
+		return buf_simple->len == 0U;
+	case BTP_MESH_RPR_EXT_SCAN_START:
+		return buf_simple->len == 0U;
+	case BTP_MESH_RPR_SCAN_CAPS_GET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_RPR_SCAN_GET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_RPR_SCAN_STOP:
+		return buf_simple->len == 0U;
+	case BTP_MESH_RPR_LINK_GET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_RPR_LINK_CLOSE:
+		return buf_simple->len == 0U;
+	case BTP_MESH_RPR_PROV_REMOTE:
+		return buf_simple->len == 0U;
+	case BTP_MESH_RPR_REPROV_REMOTE:
+		return buf_simple->len == 0U;
+	case BTP_MESH_SUBNET_BRIDGE_GET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_SUBNET_BRIDGE_SET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_BRIDGING_TABLE_ADD:
+		return buf_simple->len == 0U;
+	case BTP_MESH_BRIDGING_TABLE_REMOVE:
+		return buf_simple->len == 0U;
+	case BTP_MESH_BRIDGED_SUBNETS_GET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_BRIDGING_TABLE_GET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_BRIDGING_TABLE_SIZE_GET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_PRIV_BEACON_GET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_PRIV_BEACON_SET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_PRIV_GATT_PROXY_GET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_PRIV_GATT_PROXY_SET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_PRIV_NODE_ID_GET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_PRIV_NODE_ID_SET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_PROXY_PRIVATE_IDENTITY:
+		return buf_simple->len == 0U;
+	case BTP_MESH_OD_PRIV_PROXY_GET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_OD_PRIV_PROXY_SET:
+		return buf_simple->len == 0U;
+	case BTP_MESH_SRPL_CLEAR:
+		return buf_simple->len == 0U;
+	case BTP_MESH_PROXY_SOLICIT:
+		return buf_simple->len == 0U;
+	case BTP_MESH_START:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BTP_MESH_EV_OUT_NUMBER_ACTION:
+		return buf_simple->len == sizeof(struct btp_mesh_out_number_action_ev);
+	case BTP_MESH_EV_OUT_STRING_ACTION:
+		if (hdr->len >= sizeof(struct btp_mesh_out_string_action_ev)) {
+			const struct btp_mesh_out_string_action_ev *ev = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_mesh_out_string_action_ev));
+
+			return ev->string_len == buf_simple->len;
+		} else {
+			return false;
+		}
+	case BTP_MESH_EV_IN_ACTION:
+		return buf_simple->len == sizeof(struct btp_mesh_in_action_ev);
+	case BTP_MESH_EV_PROVISIONED:
+		return buf_simple->len == 0U;
+	case BTP_MESH_EV_PROV_LINK_OPEN:
+		return buf_simple->len == sizeof(struct btp_mesh_prov_link_open_ev);
+	case BTP_MESH_EV_NET_RECV:
+		if (hdr->len >= sizeof(struct btp_mesh_net_recv_ev)) {
+			const struct btp_mesh_net_recv_ev *ev = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_mesh_net_recv_ev));
+
+			return ev->payload_len == buf_simple->len;
+		} else {
+			return false;
+		}
+	case BTP_MESH_EV_INVALID_BEARER:
+		return buf_simple->len == sizeof(struct btp_mesh_invalid_bearer_ev);
+	case BTP_MESH_EV_INCOMP_TIMER_EXP:
+		return buf_simple->len == 0U;
+	case BTP_MESH_EV_FRND_ESTABLISHED:
+		return buf_simple->len == sizeof(struct btp_mesh_frnd_established_ev);
+	case BTP_MESH_EV_FRND_TERMINATED:
+		return buf_simple->len == sizeof(struct btp_mesh_frnd_terminated_ev);
+	case BTP_MESH_EV_LPN_ESTABLISHED:
+		return buf_simple->len == sizeof(struct btp_mesh_lpn_established_ev);
+	case BTP_MESH_EV_LPN_TERMINATED:
+		return buf_simple->len == sizeof(struct btp_mesh_lpn_terminated_ev);
+	case BTP_MESH_EV_LPN_POLLED:
+		return buf_simple->len == sizeof(struct btp_mesh_lpn_polled_ev);
+	case BTP_MESH_EV_PROV_NODE_ADDED:
+		return buf_simple->len == sizeof(struct btp_mesh_prov_node_added_ev);
+	case BTP_MESH_EV_MODEL_RECV:
+		return buf_simple->len == sizeof(struct btp_mesh_model_recv_ev);
+	case MESH_EV_BLOB_LOST_TARGET:
+		return buf_simple->len == 0U;
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_mesh_mdl_packet_len(const struct btp_hdr *hdr,
+					 struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	case BTP_MMDL_DFU_INFO_GET:
+		return buf_simple->len == 0U;
+	case BTP_MMDL_BLOB_INFO_GET:
+		return buf_simple->len == 0U;
+	case BTP_MMDL_DFU_UPDATE_METADATA_CHECK:
+		return buf_simple->len == sizeof(struct btp_mmdl_dfu_metadata_check_rp);
+	case BTP_MMDL_DFU_FIRMWARE_UPDATE_GET:
+		return buf_simple->len == 0U;
+	case BTP_MMDL_DFU_FIRMWARE_UPDATE_CANCEL:
+		return buf_simple->len == 0U;
+	case BTP_MMDL_DFU_FIRMWARE_UPDATE_START:
+		return buf_simple->len == sizeof(struct btp_mmdl_dfu_firmware_update_rp);
+	case BTP_MMDL_BLOB_TRANSFER_START:
+		return buf_simple->len == 0U;
+	case BTP_MMDL_BLOB_TRANSFER_CANCEL:
+		return buf_simple->len == 0U;
+	case BTP_MMDL_BLOB_TRANSFER_GET:
+		return buf_simple->len == 0U;
+	case BTP_MMDL_BLOB_SRV_CANCEL:
+		return buf_simple->len == 0U;
+	case BTP_MMDL_DFU_FIRMWARE_UPDATE_APPLY:
+		return buf_simple->len == 0U;
+	case BTP_MMDL_DFU_SRV_APPLY:
+		return buf_simple->len == 0U;
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_vcs_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_VCS_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_VCS_SET_VOL:
+		return buf_simple->len == 0U;
+	case BTP_VCS_VOL_UP:
+		return buf_simple->len == 0U;
+	case BTP_VCS_VOL_DOWN:
+		return buf_simple->len == 0U;
+	case BTP_VCS_MUTE:
+		return buf_simple->len == 0U;
+	case BTP_VCS_UNMUTE:
+		return buf_simple->len == 0U;
+
+	/* no events */
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_ias_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* no responses */
+
+	/* events */
+	case BTP_IAS_EV_OUT_ALERT_ACTION:
+		return buf_simple->len == sizeof(struct btp_ias_alert_action_ev);
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_aics_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_AICS_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_AICS_SET_GAIN:
+		return buf_simple->len == 0U;
+	case BTP_AICS_MUTE:
+		return buf_simple->len == 0U;
+	case BTP_AICS_UNMUTE:
+		return buf_simple->len == 0U;
+	case BTP_AICS_MAN_GAIN_SET:
+		return buf_simple->len == 0U;
+	case BTP_AICS_AUTO_GAIN_SET:
+		return buf_simple->len == 0U;
+	case BTP_AICS_SET_MAN_GAIN_ONLY:
+		return buf_simple->len == 0U;
+	case BTP_AICS_SET_AUTO_GAIN_ONLY:
+		return buf_simple->len == 0U;
+	case BTP_AICS_AUDIO_DESCRIPTION_SET:
+		return buf_simple->len == 0U;
+	case BTP_AICS_MUTE_DISABLE:
+		return buf_simple->len == 0U;
+	case BTP_AICS_GAIN_SETTING_PROP_GET:
+		return buf_simple->len == 0U;
+	case BTP_AICS_TYPE_GET:
+		return buf_simple->len == 0U;
+	case BTP_AICS_STATUS_GET:
+		return buf_simple->len == 0U;
+	case BTP_AICS_STATE_GET:
+		return buf_simple->len == 0U;
+	case BTP_AICS_DESCRIPTION_GET:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BTP_AICS_STATE_EV:
+		return buf_simple->len == sizeof(struct btp_aics_state_ev);
+	case BTP_GAIN_SETTING_PROPERTIES_EV:
+		return buf_simple->len == sizeof(struct btp_gain_setting_properties_ev);
+	case BTP_AICS_INPUT_TYPE_EV:
+		return buf_simple->len == sizeof(struct btp_aics_input_type_ev);
+	case BTP_AICS_DESCRIPTION_EV:
+		if (hdr->len >= sizeof(struct btp_aics_description_ev)) {
+			const struct btp_aics_description_ev *ev = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_aics_description_ev));
+
+			return ev->data_len == buf_simple->len;
+		} else {
+			return false;
+		}
+	case BTP_AICS_PROCEDURE_EV:
+		return buf_simple->len == sizeof(struct btp_aics_procedure_ev);
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_vocs_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_VOCS_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_VOCS_UPDATE_LOC:
+		return buf_simple->len == 0U;
+	case BTP_VOCS_UPDATE_DESC:
+		return buf_simple->len == 0U;
+	case BTP_VOCS_STATE_GET:
+		return buf_simple->len == 0U;
+	case BTP_AICS_DESCRIPTION_GET:
+		return buf_simple->len == 0U;
+	case BTP_VOCS_LOCATION_GET:
+		return buf_simple->len == 0U;
+	case BTP_VOCS_OFFSET_STATE_SET:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BTP_VOCS_OFFSET_STATE_EV:
+		return buf_simple->len == sizeof(struct btp_vocs_offset_state_ev);
+	case BTP_VOCS_AUDIO_LOCATION_EV:
+		return buf_simple->len == sizeof(struct btp_vocs_audio_location_ev);
+	case BTP_VOCS_PROCEDURE_EV:
+		return buf_simple->len == sizeof(struct btp_vocs_procedure_ev);
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_pacs_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_PACS_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_PACS_UPDATE_CHARACTERISTIC:
+		return buf_simple->len == 0U;
+	case BTP_PACS_SET_LOCATION:
+		return buf_simple->len == 0U;
+	case BTP_PACS_SET_AVAILABLE_CONTEXTS:
+		return buf_simple->len == 0U;
+	case BTP_PACS_SET_SUPPORTED_CONTEXTS:
+
+	/* No events */
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_ascs_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_ASCS_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_ASCS_CONFIGURE_CODEC:
+		return buf_simple->len == 0U;
+	case BTP_ASCS_CONFIGURE_QOS:
+		return buf_simple->len == 0U;
+	case BTP_ASCS_ENABLE:
+		return buf_simple->len == 0U;
+	case BTP_ASCS_RECEIVER_START_READY:
+		return buf_simple->len == 0U;
+	case BTP_ASCS_RECEIVER_STOP_READY:
+		return buf_simple->len == 0U;
+	case BTP_ASCS_DISABLE:
+		return buf_simple->len == 0U;
+	case BTP_ASCS_RELEASE:
+		return buf_simple->len == 0U;
+	case BTP_ASCS_UPDATE_METADATA:
+		return buf_simple->len == 0U;
+	case BTP_ASCS_ADD_ASE_TO_CIS:
+		return buf_simple->len == 0U;
+	case BTP_ASCS_PRECONFIGURE_QOS:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BTP_ASCS_EV_OPERATION_COMPLETED:
+		return buf_simple->len == sizeof(struct btp_ascs_operation_completed_ev);
+	case BTP_ASCS_EV_CHARACTERISTIC_SUBSCRIBED:
+		return buf_simple->len == 0U;
+	case BTP_ASCS_EV_ASE_STATE_CHANGED:
+		return buf_simple->len == sizeof(struct btp_ascs_ase_state_changed_ev);
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_bap_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_BAP_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_BAP_DISCOVER:
+		return buf_simple->len == 0U;
+	case BTP_BAP_SEND:
+		return buf_simple->len == sizeof(struct btp_bap_send_rp);
+	case BTP_BAP_BROADCAST_SOURCE_SETUP:
+		return buf_simple->len == sizeof(struct btp_bap_broadcast_source_setup_rp);
+	case BTP_BAP_BROADCAST_SOURCE_RELEASE:
+		return buf_simple->len == 0U;
+	case BTP_BAP_BROADCAST_ADV_START:
+		return buf_simple->len == 0U;
+	case BTP_BAP_BROADCAST_ADV_STOP:
+		return buf_simple->len == 0U;
+	case BTP_BAP_BROADCAST_SOURCE_START:
+		return buf_simple->len == 0U;
+	case BTP_BAP_BROADCAST_SOURCE_STOP:
+		return buf_simple->len == 0U;
+	case BTP_BAP_BROADCAST_SINK_SETUP:
+		return buf_simple->len == 0U;
+	case BTP_BAP_BROADCAST_SINK_RELEASE:
+		return buf_simple->len == 0U;
+	case BTP_BAP_BROADCAST_SCAN_START:
+		return buf_simple->len == 0U;
+	case BTP_BAP_BROADCAST_SCAN_STOP:
+		return buf_simple->len == 0U;
+	case BTP_BAP_BROADCAST_SINK_SYNC:
+		return buf_simple->len == 0U;
+	case BTP_BAP_BROADCAST_SINK_STOP:
+		return buf_simple->len == 0U;
+	case BTP_BAP_BROADCAST_SINK_BIS_SYNC:
+		return buf_simple->len == 0U;
+	case BTP_BAP_DISCOVER_SCAN_DELEGATORS:
+		return buf_simple->len == 0U;
+	case BTP_BAP_BROADCAST_ASSISTANT_SCAN_START:
+		return buf_simple->len == 0U;
+	case BTP_BAP_BROADCAST_ASSISTANT_SCAN_STOP:
+		return buf_simple->len == 0U;
+	case BTP_BAP_ADD_BROADCAST_SRC:
+		return buf_simple->len == 0U;
+	case BTP_BAP_REMOVE_BROADCAST_SRC:
+		return buf_simple->len == 0U;
+	case BTP_BAP_MODIFY_BROADCAST_SRC:
+		return buf_simple->len == 0U;
+	case BTP_BAP_SET_BROADCAST_CODE:
+		return buf_simple->len == 0U;
+	case BTP_BAP_SEND_PAST:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BTP_BAP_EV_DISCOVERY_COMPLETED:
+		return buf_simple->len == sizeof(struct btp_bap_discovery_completed_ev);
+	case BTP_BAP_EV_CODEC_CAP_FOUND:
+		return buf_simple->len == sizeof(struct btp_bap_codec_cap_found_ev);
+	case BTP_BAP_EV_ASE_FOUND:
+		return buf_simple->len == sizeof(struct btp_bap_ase_found_ev);
+	case BTP_BAP_EV_STREAM_RECEIVED:
+		if (hdr->len >= sizeof(struct btp_bap_stream_received_ev)) {
+			const struct btp_bap_stream_received_ev *ev = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_bap_stream_received_ev));
+
+			return ev->data_len == buf_simple->len;
+		} else {
+			return false;
+		}
+	case BTP_BAP_EV_BAA_FOUND:
+		return buf_simple->len == sizeof(struct btp_bap_baa_found_ev);
+	case BTP_BAP_EV_BIS_FOUND:
+		if (hdr->len >= sizeof(struct btp_bap_bis_found_ev)) {
+			const struct btp_bap_bis_found_ev *ev = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_bap_bis_found_ev));
+
+			return ev->cc_ltvs_len == buf_simple->len;
+		} else {
+			return false;
+		}
+	case BTP_BAP_EV_BIS_STREAM_RECEIVED:
+		if (hdr->len >= sizeof(struct btp_bap_stream_received_ev)) {
+			const struct btp_bap_bis_stream_received_ev *ev = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_bap_bis_stream_received_ev));
+
+			return ev->data_len == buf_simple->len;
+		} else {
+			return false;
+		}
+	case BTP_BAP_EV_SCAN_DELEGATOR_FOUND:
+		return buf_simple->len == sizeof(struct btp_bap_scan_delegator_found_ev);
+	case BTP_BAP_EV_BROADCAST_RECEIVE_STATE:
+		if (hdr->len >= sizeof(struct btp_bap_broadcast_receive_state_ev)) {
+			const struct btp_bap_broadcast_receive_state_ev *ev =
+				net_buf_simple_pull_mem(
+					buf_simple,
+					sizeof(struct btp_bap_broadcast_receive_state_ev));
+
+			for (uint8_t i = 0U; i < ev->num_subgroups; i++) {
+				/* Each subgroup consists of 4 octets of BIS sync, 1 octets
+				 * of metadata length, and then the metadata
+				 */
+				uint8_t metadata_len;
+				uint32_t bis_sync;
+
+				if (buf_simple->len <= (sizeof(bis_sync) + sizeof(metadata_len))) {
+					return false;
+				}
+
+				(void)net_buf_simple_pull_le32(buf_simple);
+				metadata_len = net_buf_simple_pull_u8(buf_simple);
+				if (buf_simple->len < metadata_len) {
+					return false;
+				}
+				(void)net_buf_simple_pull_mem(buf_simple, metadata_len);
+			}
+
+			return buf_simple->len == 0U;
+		} else {
+			return false;
+		}
+	case BTP_BAP_EV_PA_SYNC_REQ:
+		return buf_simple->len == sizeof(struct btp_bap_pa_sync_req_ev);
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_has_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_HAS_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_HAS_SET_ACTIVE_INDEX:
+		return buf_simple->len == 0U;
+	case BTP_HAS_SET_PRESET_NAME:
+		return buf_simple->len == 0U;
+	case BTP_HAS_REMOVE_PRESET:
+		return buf_simple->len == 0U;
+	case BTP_HAS_ADD_PRESET:
+		return buf_simple->len == 0U;
+	case BTP_HAS_SET_PROPERTIES:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BTP_HAS_EV_OPERATION_COMPLETED:
+		return buf_simple->len == sizeof(struct btp_has_operation_completed_ev);
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_micp_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_MICP_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_MICP_CTLR_DISCOVER:
+		return buf_simple->len == 0U;
+	case BTP_MICP_CTLR_MUTE_READ:
+		return buf_simple->len == 0U;
+	case BTP_MICP_CTLR_MUTE:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BTP_MICP_DISCOVERED_EV:
+		return buf_simple->len == sizeof(struct btp_micp_discovered_ev);
+	case BTP_MICP_MUTE_STATE_EV:
+		return buf_simple->len == sizeof(struct btp_micp_mute_state_ev);
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_csis_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_CSIS_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_CSIS_SET_MEMBER_LOCK:
+		return buf_simple->len == 0U;
+	case BTP_CSIS_GET_MEMBER_RSI:
+		return buf_simple->len == sizeof(struct btp_csis_get_member_rsi_rp);
+	case BTP_CSIS_ENC_SIRK_TYPE:
+		return buf_simple->len == 0U;
+
+	/* No events */
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_mics_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_MICS_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_MICS_DEV_MUTE_DISABLE:
+		return buf_simple->len == 0U;
+	case BTP_MICS_DEV_MUTE_READ:
+		return buf_simple->len == 0U;
+	case BTP_MICS_DEV_MUTE:
+		return buf_simple->len == 0U;
+	case BTP_MICS_DEV_UNMUTE:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BTP_MICS_MUTE_STATE_EV:
+		return buf_simple->len == sizeof(struct btp_mics_mute_state_ev);
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_ccp_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_CCP_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_CCP_DISCOVER_TBS:
+		return buf_simple->len == 0U;
+	case BTP_CCP_ACCEPT_CALL:
+		return buf_simple->len == 0U;
+	case BTP_CCP_TERMINATE_CALL:
+		return buf_simple->len == 0U;
+	case BTP_CCP_ORIGINATE_CALL:
+		return buf_simple->len == 0U;
+	case BTP_CCP_READ_CALL_STATE:
+		return buf_simple->len == 0U;
+	case BTP_CCP_READ_BEARER_NAME:
+		return buf_simple->len == 0U;
+	case BTP_CCP_READ_BEARER_UCI:
+		return buf_simple->len == 0U;
+	case BTP_CCP_READ_BEARER_TECH:
+		return buf_simple->len == 0U;
+	case BTP_CCP_READ_URI_LIST:
+		return buf_simple->len == 0U;
+	case BTP_CCP_READ_SIGNAL_STRENGTH:
+		return buf_simple->len == 0U;
+	case BTP_CCP_READ_SIGNAL_INTERVAL:
+		return buf_simple->len == 0U;
+	case BTP_CCP_READ_CURRENT_CALLS:
+		return buf_simple->len == 0U;
+	case BTP_CCP_READ_CCID:
+		return buf_simple->len == 0U;
+	case BTP_CCP_READ_CALL_URI:
+		return buf_simple->len == 0U;
+	case BTP_CCP_READ_STATUS_FLAGS:
+		return buf_simple->len == 0U;
+	case BTP_CCP_READ_OPTIONAL_OPCODES:
+		return buf_simple->len == 0U;
+	case BTP_CCP_READ_FRIENDLY_NAME:
+		return buf_simple->len == 0U;
+	case BTP_CCP_READ_REMOTE_URI:
+		return buf_simple->len == 0U;
+	case BTP_CCP_SET_SIGNAL_INTERVAL:
+		return buf_simple->len == 0U;
+	case BTP_CCP_HOLD_CALL:
+		return buf_simple->len == 0U;
+	case BTP_CCP_RETRIEVE_CALL:
+		return buf_simple->len == 0U;
+	case BTP_CCP_JOIN_CALLS:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BTP_CCP_EV_DISCOVERED:
+		return buf_simple->len == sizeof(struct btp_ccp_discovered_ev);
+	case BTP_CCP_EV_CALL_STATES:
+		if (hdr->len >= sizeof(struct btp_ccp_call_states_ev)) {
+			const struct btp_ccp_call_states_ev *ev = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_ccp_call_states_ev));
+
+			return (ev->call_count * sizeof(struct bt_tbs_client_call_state)) ==
+			       buf_simple->len;
+		} else {
+			return false;
+		}
+	case BTP_CCP_EV_CHRC_HANDLES:
+		return buf_simple->len == sizeof(struct btp_ccp_chrc_handles_ev);
+	case BTP_CCP_EV_CHRC_VAL:
+		return buf_simple->len == sizeof(struct btp_ccp_chrc_val_ev);
+	case BTP_CCP_EV_CHRC_STR:
+		if (hdr->len >= sizeof(struct btp_ccp_chrc_str_ev)) {
+			const struct btp_ccp_chrc_str_ev *ev = net_buf_simple_pull_mem(
+				buf_simple, sizeof(struct btp_ccp_chrc_str_ev));
+
+			return ev->data_len == buf_simple->len;
+		} else {
+			return false;
+		}
+	case BTP_CCP_EV_CP:
+		return buf_simple->len == sizeof(struct btp_ccp_cp_ev);
+	case BTP_CCP_EV_CURRENT_CALLS:
+		return buf_simple->len == sizeof(struct btp_ccp_current_calls_ev);
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_vcp_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_VCP_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_VCP_VOL_CTLR_DISCOVER:
+		return buf_simple->len == 0U;
+	case BTP_VCP_VOL_CTLR_STATE_READ:
+		return buf_simple->len == 0U;
+	case BTP_VCP_VOL_CTLR_FLAGS_READ:
+		return buf_simple->len == 0U;
+	case BTP_VCP_VOL_CTLR_VOL_DOWN:
+		return buf_simple->len == 0U;
+	case BTP_VCP_VOL_CTLR_VOL_UP:
+		return buf_simple->len == 0U;
+	case BTP_VCP_VOL_CTLR_UNMUTE_VOL_DOWN:
+		return buf_simple->len == 0U;
+	case BTP_VCP_VOL_CTLR_UNMUTE_VOL_UP:
+		return buf_simple->len == 0U;
+	case BTP_VCP_VOL_CTLR_SET_VOL:
+		return buf_simple->len == 0U;
+	case BTP_VCP_VOL_CTLR_UNMUTE:
+		return buf_simple->len == 0U;
+	case BTP_VCP_VOL_CTLR_MUTE:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BTP_VCP_DISCOVERED_EV:
+		return buf_simple->len == sizeof(struct btp_vcp_discovered_ev);
+	case BTP_VCP_STATE_EV:
+		return buf_simple->len == sizeof(struct btp_vcp_state_ev);
+	case BTP_VCP_FLAGS_EV:
+		return buf_simple->len == sizeof(struct btp_vcp_volume_flags_ev);
+	case BTP_VCP_PROCEDURE_EV:
+		return buf_simple->len == sizeof(struct btp_vcp_procedure_ev);
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_cas_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_CAS_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_CAS_SET_MEMBER_LOCK:
+		return buf_simple->len == 0U;
+	case BTP_CAS_GET_MEMBER_RSI:
+		return buf_simple->len == sizeof(struct btp_cas_get_member_rsi_rp);
+
+	/* No events */
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_mcp_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_MCP_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_MCP_DISCOVER:
+		return buf_simple->len == 0U;
+	case BTP_MCP_TRACK_DURATION_READ:
+		return buf_simple->len == 0U;
+	case BTP_MCP_TRACK_POSITION_READ:
+		return buf_simple->len == 0U;
+	case BTP_MCP_TRACK_POSITION_SET:
+		return buf_simple->len == 0U;
+	case BTP_MCP_PLAYBACK_SPEED_READ:
+		return buf_simple->len == 0U;
+	case BTP_MCP_PLAYBACK_SPEED_SET:
+		return buf_simple->len == 0U;
+	case BTP_MCP_SEEKING_SPEED_READ:
+		return buf_simple->len == 0U;
+	case BTP_MCP_ICON_OBJ_ID_READ:
+		return buf_simple->len == 0U;
+	case BTP_MCP_NEXT_TRACK_OBJ_ID_READ:
+		return buf_simple->len == 0U;
+	case BTP_MCP_NEXT_TRACK_OBJ_ID_SET:
+		return buf_simple->len == 0U;
+	case BTP_MCP_PARENT_GROUP_OBJ_ID_READ:
+		return buf_simple->len == 0U;
+	case BTP_MCP_CURRENT_GROUP_OBJ_ID_READ:
+		return buf_simple->len == 0U;
+	case BTP_MCP_CURRENT_GROUP_OBJ_ID_SET:
+		return buf_simple->len == 0U;
+	case BTP_MCP_PLAYING_ORDER_READ:
+		return buf_simple->len == 0U;
+	case BTP_MCP_PLAYING_ORDER_SET:
+		return buf_simple->len == 0U;
+	case BTP_MCP_PLAYING_ORDERS_SUPPORTED_READ:
+		return buf_simple->len == 0U;
+	case BTP_MCP_MEDIA_STATE_READ:
+		return buf_simple->len == 0U;
+	case BTP_MCP_OPCODES_SUPPORTED_READ:
+		return buf_simple->len == 0U;
+	case BTP_MCP_CONTENT_CONTROL_ID_READ:
+		return buf_simple->len == 0U;
+	case BTP_MCP_SEGMENTS_OBJ_ID_READ:
+		return buf_simple->len == 0U;
+	case BTP_MCP_CURRENT_TRACK_OBJ_ID_READ:
+		return buf_simple->len == 0U;
+	case BTP_MCP_CURRENT_TRACK_OBJ_ID_SET:
+		return buf_simple->len == 0U;
+	case BTP_MCP_CMD_SEND:
+		return buf_simple->len == 0U;
+	case BTP_MCP_CMD_SEARCH:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BTP_MCP_DISCOVERED_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_discovered_ev);
+	case BTP_MCP_TRACK_DURATION_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_track_duration_ev);
+	case BTP_MCP_TRACK_POSITION_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_track_position_ev);
+	case BTP_MCP_PLAYBACK_SPEED_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_playback_speed_ev);
+	case BTP_MCP_SEEKING_SPEED_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_seeking_speed_ev);
+	case BTP_MCP_ICON_OBJ_ID_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_icon_obj_id_ev);
+	case BTP_MCP_NEXT_TRACK_OBJ_ID_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_next_track_obj_id_ev);
+	case BTP_MCP_PARENT_GROUP_OBJ_ID_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_parent_group_obj_id_ev);
+	case BTP_MCP_CURRENT_GROUP_OBJ_ID_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_current_group_obj_id_ev);
+	case BTP_MCP_PLAYING_ORDER_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_playing_order_ev);
+	case BTP_MCP_PLAYING_ORDERS_SUPPORTED_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_playing_orders_supported_ev);
+	case BTP_MCP_MEDIA_STATE_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_media_state_ev);
+	case BTP_MCP_OPCODES_SUPPORTED_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_opcodes_supported_ev);
+	case BTP_MCP_CONTENT_CONTROL_ID_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_content_control_id_ev);
+	case BTP_MCP_SEGMENTS_OBJ_ID_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_segments_obj_id_ev);
+	case BTP_MCP_CURRENT_TRACK_OBJ_ID_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_current_track_obj_id_ev);
+	case BTP_MCP_MEDIA_CP_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_media_cp_ev);
+	case BTP_MCP_SEARCH_CP_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_search_cp_ev);
+	case BTP_MCP_NTF_EV:
+		return buf_simple->len == sizeof(struct btp_mcp_cmd_ntf_ev);
+	case BTP_SCP_NTF_EV:
+		return buf_simple->len == sizeof(struct btp_scp_cmd_ntf_ev);
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_gmcs_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* No responses */
+	/* No events */
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_hap_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_HAP_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_HAP_HA_INIT:
+		return buf_simple->len == 0U;
+	case BTP_HAP_HARC_INIT:
+		return buf_simple->len == 0U;
+	case BTP_HAP_HAUC_INIT:
+		return buf_simple->len == 0U;
+	case BTP_HAP_IAC_INIT:
+		return buf_simple->len == 0U;
+	case BTP_HAP_IAC_DISCOVER:
+		return buf_simple->len == 0U;
+	case BTP_HAP_IAC_SET_ALERT:
+		return buf_simple->len == 0U;
+	case BTP_HAP_HAUC_DISCOVER:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BT_HAP_EV_IAC_DISCOVERY_COMPLETE:
+		return buf_simple->len == sizeof(struct btp_hap_iac_discovery_complete_ev);
+	case BT_HAP_EV_HAUC_DISCOVERY_COMPLETE:
+		return buf_simple->len == sizeof(struct btp_hap_hauc_discovery_complete_ev);
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_csip_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_CSIP_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_CSIP_DISCOVER:
+		return buf_simple->len == 0U;
+	case BTP_CSIP_START_ORDERED_ACCESS:
+		return buf_simple->len == 0U;
+	case BTP_CSIP_SET_COORDINATOR_LOCK:
+		return buf_simple->len == 0U;
+	case BTP_CSIP_SET_COORDINATOR_RELEASE:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BTP_CSIP_DISCOVERED_EV:
+		return buf_simple->len == sizeof(struct btp_csip_discovered_ev);
+	case BTP_CSIP_SIRK_EV:
+		return buf_simple->len == sizeof(struct btp_csip_sirk_ev);
+	case BTP_CSIP_LOCK_EV:
+		return buf_simple->len == sizeof(struct btp_csip_lock_ev);
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_cap_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_CAP_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_CAP_DISCOVER:
+		return buf_simple->len == 0U;
+	case BTP_CAP_UNICAST_SETUP_ASE:
+		return buf_simple->len == 0U;
+	case BTP_CAP_UNICAST_AUDIO_START:
+		return buf_simple->len == 0U;
+	case BTP_CAP_UNICAST_AUDIO_UPDATE:
+		return buf_simple->len == 0U;
+	case BTP_CAP_UNICAST_AUDIO_STOP:
+		return buf_simple->len == 0U;
+	case BTP_CAP_BROADCAST_SOURCE_SETUP_STREAM:
+		return buf_simple->len == 0U;
+	case BTP_CAP_BROADCAST_SOURCE_SETUP_SUBGROUP:
+		return buf_simple->len == 0U;
+	case BTP_CAP_BROADCAST_SOURCE_SETUP:
+		return buf_simple->len == sizeof(struct btp_cap_broadcast_source_setup_rp);
+	case BTP_CAP_BROADCAST_SOURCE_RELEASE:
+		return buf_simple->len == 0U;
+	case BTP_CAP_BROADCAST_ADV_START:
+		return buf_simple->len == 0U;
+	case BTP_CAP_BROADCAST_ADV_STOP:
+		return buf_simple->len == 0U;
+	case BTP_CAP_BROADCAST_SOURCE_START:
+		return buf_simple->len == 0U;
+	case BTP_CAP_BROADCAST_SOURCE_STOP:
+		return buf_simple->len == 0U;
+	case BTP_CAP_BROADCAST_SOURCE_UPDATE:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BTP_CAP_EV_DISCOVERY_COMPLETED:
+		return buf_simple->len == sizeof(struct btp_cap_discovery_completed_ev);
+	case BTP_CAP_EV_UNICAST_START_COMPLETED:
+		return buf_simple->len == sizeof(struct btp_cap_unicast_start_completed_ev);
+	case BTP_CAP_EV_UNICAST_STOP_COMPLETED:
+		return buf_simple->len == sizeof(struct btp_cap_unicast_stop_completed_ev);
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_tbs_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_TBS_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_TBS_REMOTE_INCOMING:
+		return buf_simple->len == 0U;
+	case BTP_TBS_HOLD:
+		return buf_simple->len == 0U;
+	case BTP_TBS_SET_BEARER_NAME:
+		return buf_simple->len == 0U;
+	case BTP_TBS_SET_TECHNOLOGY:
+		return buf_simple->len == 0U;
+	case BTP_TBS_SET_URI_SCHEME:
+		return buf_simple->len == 0U;
+	case BTP_TBS_SET_STATUS_FLAGS:
+		return buf_simple->len == 0U;
+	case BTP_TBS_REMOTE_HOLD:
+		return buf_simple->len == 0U;
+	case BTP_TBS_ORIGINATE:
+		return buf_simple->len == 0U;
+	case BTP_TBS_SET_SIGNAL_STRENGTH:
+		return buf_simple->len == 0U;
+
+	/* No events */
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_tmap_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_TMAP_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_TMAP_DISCOVER:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BT_TMAP_EV_DISCOVERY_COMPLETE:
+		return buf_simple->len == sizeof(struct btp_tmap_discovery_complete_ev);
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_ots_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_OTS_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_OTS_REGISTER_OBJECT:
+		return buf_simple->len == sizeof(struct btp_ots_register_object_rp);
+
+	/* No events */
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+static bool is_valid_pbp_packet_len(const struct btp_hdr *hdr, struct net_buf_simple *buf_simple)
+{
+	switch (hdr->opcode) {
+	/* responses */
+	case BTP_PBP_READ_SUPPORTED_COMMANDS:
+		return buf_simple->len > 0U; /* variable length */
+	case BTP_PBP_SET_PUBLIC_BROADCAST_ANNOUNCEMENT:
+		return buf_simple->len == 0U;
+	case BTP_PBP_SET_BROADCAST_NAME:
+		return buf_simple->len == 0U;
+	case BTP_PBP_BROADCAST_SCAN_START:
+		return buf_simple->len == 0U;
+	case BTP_PBP_BROADCAST_SCAN_STOP:
+		return buf_simple->len == 0U;
+
+	/* events */
+	case BTP_PBP_EV_PUBLIC_BROADCAST_ANNOUNCEMENT_FOUND:
+		return buf_simple->len ==
+		       sizeof(struct btp_pbp_ev_public_broadcast_announcement_found_ev);
+	default:
+		LOG_ERR("Unhandled opcode 0x%02X", hdr->opcode);
+		return false;
+	}
+}
+
+/**
+ * Tests whether the incoming packet from @p buf is valid in terms of packet length
+ *
+ * It verifies responses and events, but not commands
+ */
+static bool is_valid_packet_len(uint8_t buf[], size_t len)
+{
+	struct net_buf_simple buf_simple;
+	const struct btp_hdr *hdr;
+
+	TEST_ASSERT(buf != NULL);
+	LOG_HEXDUMP_DBG(buf, len, "evt");
+
+	/* Make a simple copy of the data so we can pull the data without affecting the original */
+	net_buf_simple_init_with_data(&buf_simple, buf, len);
+	TEST_ASSERT(buf_simple.len >= sizeof(*hdr));
+
+	hdr = net_buf_simple_pull_mem(&buf_simple, sizeof(*hdr));
+
+	/* For all events it shall be true that after getting the header, the header len field and
+	 * the remaining buffer length shall be the same
+	 */
+	if (hdr->len != buf_simple.len) {
+		return false;
+	}
+
+	switch (hdr->service) {
+	case BTP_SERVICE_ID_CORE:
+		return is_valid_core_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_GAP:
+		return is_valid_gap_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_GATT:
+		return is_valid_gatt_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_L2CAP:
+		return is_valid_l2cap_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_MESH:
+		return is_valid_mesh_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_MESH_MDL:
+		return is_valid_mesh_mdl_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_GATT_CLIENT:
+		break; /* Not implemented in Zephyr */
+	case BTP_SERVICE_GATT_SERVER:
+		break; /* Not implemented in Zephyr */
+	case BTP_SERVICE_ID_VCS:
+		return is_valid_vcs_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_IAS:
+		return is_valid_ias_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_AICS:
+		return is_valid_aics_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_VOCS:
+		return is_valid_vocs_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_PACS:
+		return is_valid_pacs_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_ASCS:
+		return is_valid_ascs_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_BAP:
+		return is_valid_bap_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_HAS:
+		return is_valid_has_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_MICP:
+		return is_valid_micp_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_CSIS:
+		return is_valid_csis_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_MICS:
+		return is_valid_mics_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_CCP:
+		return is_valid_ccp_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_VCP:
+		return is_valid_vcp_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_CAS:
+		return is_valid_cas_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_MCP:
+		return is_valid_mcp_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_GMCS:
+		return is_valid_gmcs_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_HAP:
+		return is_valid_hap_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_CSIP:
+		return is_valid_csip_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_CAP:
+		return is_valid_cap_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_TBS:
+		return is_valid_tbs_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_TMAP:
+		return is_valid_tmap_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_OTS:
+		return is_valid_ots_packet_len(hdr, &buf_simple);
+	case BTP_SERVICE_ID_PBP:
+		return is_valid_pbp_packet_len(hdr, &buf_simple);
+	}
+
+	LOG_ERR("Unhandled service 0x%02x", hdr->service);
+	return false;
+}
+
+void bsim_btp_wait_for_evt(uint8_t service, uint8_t opcode, struct net_buf **out_buf)
+{
+	LOG_DBG("Waiting for evt with service 0x%02X and opcode 0x%02X", service, opcode);
+
+	while (true) {
+		const struct btp_hdr *hdr;
+		struct net_buf *buf;
+
+		buf = k_fifo_get(&btp_evt_fifo, K_FOREVER);
+		TEST_ASSERT(buf != NULL);
+
+		hdr = net_buf_pull_mem(buf, sizeof(struct btp_hdr));
+
+		/* TODO: Verify length of event based on the service and opcode */
+		if (hdr->service == service && hdr->opcode == opcode) {
+			if (out_buf != NULL) {
+				/* If the caller provides an out_buf, they are responsible
+				 * for unref'ing it
+				 */
+				*out_buf = net_buf_ref(buf);
+			}
+
+			net_buf_unref(buf);
+
+			LOG_DBG("Got evt with service 0x%02X and opcode 0x%02X", service, opcode);
+
+			return;
+		}
+
+		net_buf_unref(buf);
+	}
+}
+
+static bool recv_cb(uint8_t buf[], size_t buf_len)
+{
+	struct btp_hdr *hdr = (void *)buf;
+	uint16_t len;
+
+	if (buf_len < sizeof(*hdr)) {
+		return false;
+	}
+
+	len = sys_le16_to_cpu(hdr->len);
+	TEST_ASSERT(len <= BTP_MTU - sizeof(*hdr), "Invalid packet length %zu", len);
+
+	if (buf_len < sizeof(*hdr) + len) {
+		return false;
+	}
+
+	TEST_ASSERT(is_valid_packet_len(buf, buf_len),
+		    "Header len %u does not match expected packet length for "
+		    "service 0x%02X and opcode 0x%02X",
+		    hdr->len, hdr->service, hdr->opcode);
+
+	if (hdr->opcode < BTP_EVENT_OPCODE) {
+		struct net_buf *net_buf = net_buf_alloc(&btp_rsp_pool, K_NO_WAIT);
+
+		TEST_ASSERT(buf != NULL);
+
+		net_buf_add_mem(net_buf, buf, buf_len);
+		k_fifo_put(&btp_rsp_fifo, net_buf);
+	} else {
+		struct net_buf *net_buf = net_buf_alloc(&btp_evt_pool, K_NO_WAIT);
+
+		if (net_buf == NULL) {
+			/* Discard the oldest event */
+			net_buf = k_fifo_get(&btp_evt_fifo, K_NO_WAIT);
+			TEST_ASSERT(net_buf != NULL);
+			net_buf_unref(net_buf);
+
+			net_buf = net_buf_alloc(&btp_evt_pool, K_NO_WAIT);
+			TEST_ASSERT(net_buf != NULL);
+		}
+
+		net_buf_add_mem(net_buf, buf, buf_len);
+		k_fifo_put(&btp_evt_fifo, net_buf);
+	}
+
+	buf = NULL;
+
+	return true;
+}
+
+static void timer_expiry_cb(struct k_timer *timer)
+{
+	static uint8_t uart_recv_buf[BTP_MTU];
+	static size_t len;
+
+	while (uart_poll_in(dev, &uart_recv_buf[len]) == 0) {
+		TEST_ASSERT(len < ARRAY_SIZE(uart_recv_buf));
+		len++;
+		if (recv_cb(uart_recv_buf, len)) {
+			len = 0;
+		}
+	}
+}
+
+K_TIMER_DEFINE(timer, timer_expiry_cb, NULL);
+
+/* Uart Poll */
+void bsim_btp_uart_init(void)
+{
+	TEST_ASSERT(device_is_ready(dev));
+
+	k_timer_start(&timer, K_MSEC(10), K_MSEC(10));
+}
+
+static void wait_for_response(const struct btp_hdr *cmd_hdr)
+{
+	const struct btp_hdr *rsp_hdr;
+	struct net_buf *buf;
+
+	buf = k_fifo_get(&btp_rsp_fifo, K_SECONDS(1));
+	TEST_ASSERT(buf != NULL);
+
+	rsp_hdr = (struct btp_hdr *)buf->data;
+	TEST_ASSERT(rsp_hdr->len <= BTP_MTU, "len %u > %d", rsp_hdr->len, BTP_MTU);
+
+	LOG_DBG("rsp service 0x%02X and opcode 0x%02X len %u", cmd_hdr->service, cmd_hdr->opcode,
+		rsp_hdr->len);
+
+	TEST_ASSERT(rsp_hdr->service == cmd_hdr->service && rsp_hdr->opcode == cmd_hdr->opcode);
+
+	net_buf_unref(buf);
+}
+
+/* BTP communication is inspired from `uart_pipe_rx` to achieve a similar API */
+void bsim_btp_send_to_tester(const uint8_t *data, size_t len)
+{
+	const struct btp_hdr *cmd_hdr;
+
+	TEST_ASSERT(data != NULL);
+	TEST_ASSERT(len <= BTP_MTU, "len %zu > %d", len, BTP_MTU);
+	TEST_ASSERT(len >= sizeof(*cmd_hdr), "len %zu <= %zu", len, sizeof(*cmd_hdr));
+
+	cmd_hdr = (const struct btp_hdr *)data;
+	LOG_DBG("cmd service 0x%02X and opcode 0x%02X", cmd_hdr->service, cmd_hdr->opcode);
+
+	for (size_t i = 0U; i < len; i++) {
+		uart_poll_out(dev, data[i]);
+	}
+
+	wait_for_response(cmd_hdr);
+}
diff --git a/tests/bsim/bluetooth/tester/src/bsim_btp.h b/tests/bsim/bluetooth/tester/src/bsim_btp.h
new file mode 100644
index 00000000000..faad454eb3d
--- /dev/null
+++ b/tests/bsim/bluetooth/tester/src/bsim_btp.h
@@ -0,0 +1,200 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdint.h>
+#include <string.h>
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/net_buf.h>
+
+#include "babblekit/testcase.h"
+
+#include "btp/btp.h"
+
+void bsim_btp_uart_init(void);
+void bsim_btp_send_to_tester(const uint8_t *data, size_t len);
+void bsim_btp_wait_for_evt(uint8_t service, uint8_t opcode, struct net_buf **out_buf);
+
+static inline void bsim_btp_core_register(uint8_t id)
+{
+	struct btp_core_register_service_cmd *cmd;
+	struct btp_hdr *cmd_hdr;
+
+	NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU);
+
+	cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr));
+	cmd_hdr->service = BTP_SERVICE_ID_CORE;
+	cmd_hdr->opcode = BTP_CORE_REGISTER_SERVICE;
+	cmd_hdr->index = BTP_INDEX_NONE;
+	cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd));
+	cmd->id = id;
+
+	cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr);
+
+	bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len);
+}
+
+static inline void bsim_btp_gap_set_discoverable(uint8_t discoverable)
+{
+	struct btp_gap_set_discoverable_cmd *cmd;
+	struct btp_hdr *cmd_hdr;
+
+	NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU);
+
+	cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr));
+	cmd_hdr->service = BTP_SERVICE_ID_GAP;
+	cmd_hdr->opcode = BTP_GAP_SET_DISCOVERABLE;
+	cmd_hdr->index = BTP_INDEX;
+	cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd));
+	cmd->discoverable = discoverable;
+
+	cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr);
+
+	bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len);
+}
+
+static inline void bsim_btp_gap_start_advertising(uint8_t adv_data_len, uint8_t scan_rsp_len,
+						  const uint8_t adv_sr_data[],
+						  uint8_t own_addr_type)
+{
+	struct btp_gap_start_advertising_cmd *cmd;
+	struct btp_hdr *cmd_hdr;
+
+	NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU);
+
+	cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr));
+	cmd_hdr->service = BTP_SERVICE_ID_GAP;
+	cmd_hdr->opcode = BTP_GAP_START_ADVERTISING;
+	cmd_hdr->index = BTP_INDEX;
+	cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd));
+	cmd->adv_data_len = adv_data_len;
+	cmd->scan_rsp_len = scan_rsp_len;
+	if (adv_data_len > 0U) {
+		net_buf_simple_add_mem(&cmd_buffer, adv_sr_data, adv_data_len);
+	}
+	if (scan_rsp_len > 0U) {
+		net_buf_simple_add_mem(&cmd_buffer, adv_sr_data, scan_rsp_len);
+	}
+	net_buf_simple_add_le32(&cmd_buffer, 0xFFFF); /* unused in Zephyr */
+	net_buf_simple_add_u8(&cmd_buffer, own_addr_type);
+
+	cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr);
+
+	bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len);
+}
+
+static inline void bsim_btp_gap_start_discovery(uint8_t flags)
+{
+	struct btp_gap_start_discovery_cmd *cmd;
+	struct btp_hdr *cmd_hdr;
+
+	NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU);
+
+	cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr));
+	cmd_hdr->service = BTP_SERVICE_ID_GAP;
+	cmd_hdr->opcode = BTP_GAP_START_DISCOVERY;
+	cmd_hdr->index = BTP_INDEX;
+	cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd));
+	cmd->flags = flags;
+
+	cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr);
+
+	bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len);
+}
+
+static inline void bsim_btp_gap_stop_discovery(void)
+{
+	struct btp_hdr *cmd_hdr;
+
+	NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU);
+
+	cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr));
+	cmd_hdr->service = BTP_SERVICE_ID_GAP;
+	cmd_hdr->opcode = BTP_GAP_STOP_DISCOVERY;
+	cmd_hdr->index = BTP_INDEX;
+	cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr);
+
+	bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len);
+}
+
+static inline void bsim_btp_wait_for_gap_device_found(bt_addr_le_t *address)
+{
+	struct btp_gap_device_found_ev *ev;
+	struct net_buf *buf;
+
+	bsim_btp_wait_for_evt(BTP_SERVICE_ID_GAP, BTP_GAP_EV_DEVICE_FOUND, &buf);
+	ev = net_buf_pull_mem(buf, sizeof(*ev));
+	if (address != NULL) {
+		bt_addr_le_copy(address, &ev->address);
+	}
+
+	net_buf_unref(buf);
+}
+
+static inline void bsim_btp_gap_connect(const bt_addr_le_t *address, uint8_t own_addr_type)
+{
+	struct btp_gap_connect_cmd *cmd;
+	struct btp_hdr *cmd_hdr;
+
+	NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU);
+
+	cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr));
+	cmd_hdr->service = BTP_SERVICE_ID_GAP;
+	cmd_hdr->opcode = BTP_GAP_CONNECT;
+	cmd_hdr->index = BTP_INDEX;
+	cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd));
+	bt_addr_le_copy(&cmd->address, address);
+	cmd->own_addr_type = own_addr_type;
+
+	cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr);
+
+	bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len);
+}
+
+static inline void bsim_btp_wait_for_gap_device_connected(bt_addr_le_t *address)
+{
+	struct btp_gap_device_connected_ev *ev;
+	struct net_buf *buf;
+
+	bsim_btp_wait_for_evt(BTP_SERVICE_ID_GAP, BTP_GAP_EV_DEVICE_CONNECTED, &buf);
+	ev = net_buf_pull_mem(buf, sizeof(*ev));
+	if (address != NULL) {
+		bt_addr_le_copy(address, &ev->address);
+	}
+
+	net_buf_unref(buf);
+}
+
+static inline void bsim_btp_gap_disconnect(const bt_addr_le_t *address)
+{
+	struct btp_gap_disconnect_cmd *cmd;
+	struct btp_hdr *cmd_hdr;
+
+	NET_BUF_SIMPLE_DEFINE(cmd_buffer, BTP_MTU);
+
+	cmd_hdr = net_buf_simple_add(&cmd_buffer, sizeof(*cmd_hdr));
+	cmd_hdr->service = BTP_SERVICE_ID_GAP;
+	cmd_hdr->opcode = BTP_GAP_DISCONNECT;
+	cmd_hdr->index = BTP_INDEX;
+	cmd = net_buf_simple_add(&cmd_buffer, sizeof(*cmd));
+	bt_addr_le_copy(&cmd->address, address);
+
+	cmd_hdr->len = cmd_buffer.len - sizeof(*cmd_hdr);
+
+	bsim_btp_send_to_tester(cmd_buffer.data, cmd_buffer.len);
+}
+
+static inline void bsim_btp_wait_for_gap_device_disconnected(bt_addr_le_t *address)
+{
+	struct btp_gap_device_disconnected_ev *ev;
+	struct net_buf *buf;
+
+	bsim_btp_wait_for_evt(BTP_SERVICE_ID_GAP, BTP_GAP_EV_DEVICE_DISCONNECTED, &buf);
+	ev = net_buf_pull_mem(buf, sizeof(*ev));
+	if (address != NULL) {
+		bt_addr_le_copy(address, &ev->address);
+	}
+
+	net_buf_unref(buf);
+}
diff --git a/tests/bsim/bluetooth/tester/src/host/gap_central.c b/tests/bsim/bluetooth/tester/src/host/gap_central.c
new file mode 100644
index 00000000000..1365a081731
--- /dev/null
+++ b/tests/bsim/bluetooth/tester/src/host/gap_central.c
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stddef.h>
+#include <stdint.h>
+
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/net_buf.h>
+#include <zephyr/sys/util_macro.h>
+
+#include "babblekit/testcase.h"
+#include "bstests.h"
+
+#include "btp/btp.h"
+#include "bsim_btp.h"
+
+LOG_MODULE_REGISTER(bsim_gap_central, CONFIG_BSIM_BTTESTER_LOG_LEVEL);
+
+static void test_gap_central(void)
+{
+	char addr_str[BT_ADDR_LE_STR_LEN];
+	bt_addr_le_t remote_addr;
+	bt_addr_le_t ev_addr;
+
+	bsim_btp_uart_init();
+
+	bsim_btp_wait_for_evt(BTP_SERVICE_ID_CORE, BTP_CORE_EV_IUT_READY, NULL);
+
+	bsim_btp_core_register(BTP_SERVICE_ID_GAP);
+	bsim_btp_gap_start_discovery(BTP_GAP_DISCOVERY_FLAG_LE);
+	bsim_btp_wait_for_gap_device_found(&remote_addr);
+	bt_addr_le_to_str(&remote_addr, addr_str, sizeof(addr_str));
+	LOG_INF("Found remote device %s", addr_str);
+
+	bsim_btp_gap_stop_discovery();
+	bsim_btp_gap_connect(&remote_addr, BTP_GAP_ADDR_TYPE_IDENTITY);
+	bsim_btp_wait_for_gap_device_connected(&ev_addr);
+	TEST_ASSERT(bt_addr_le_eq(&remote_addr, &ev_addr));
+	LOG_INF("Device %s connected", addr_str);
+
+	/* Keep alive for a little while */
+	k_sleep(K_SECONDS(10));
+
+	bsim_btp_gap_disconnect(&remote_addr);
+	bsim_btp_wait_for_gap_device_disconnected(&ev_addr);
+	TEST_ASSERT(bt_addr_le_eq(&remote_addr, &ev_addr));
+	LOG_INF("Device %s disconnected", addr_str);
+
+	TEST_PASS("PASSED\n");
+}
+
+static const struct bst_test_instance test_sample[] = {
+	{
+		.test_id = "gap_central",
+		.test_descr = "Smoketest for the GAP central BT Tester behavior",
+		.test_main_f = test_gap_central,
+	},
+	BSTEST_END_MARKER,
+};
+
+struct bst_test_list *test_gap_central_install(struct bst_test_list *tests)
+{
+	return bst_add_tests(tests, test_sample);
+}
diff --git a/tests/bsim/bluetooth/tester/src/host/gap_peripheral.c b/tests/bsim/bluetooth/tester/src/host/gap_peripheral.c
new file mode 100644
index 00000000000..daa45eb80f8
--- /dev/null
+++ b/tests/bsim/bluetooth/tester/src/host/gap_peripheral.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stddef.h>
+#include <stdint.h>
+
+#include <zephyr/bluetooth/addr.h>
+#include <zephyr/bluetooth/gap.h>
+#include <zephyr/bluetooth/hci_types.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/sys/util_macro.h>
+
+#include "babblekit/testcase.h"
+#include "bstests.h"
+
+#include "btp/btp.h"
+#include "bsim_btp.h"
+
+LOG_MODULE_REGISTER(bsim_gap_peripheral, CONFIG_BSIM_BTTESTER_LOG_LEVEL);
+
+static void test_gap_peripheral(void)
+{
+	char addr_str[BT_ADDR_LE_STR_LEN];
+	bt_addr_le_t remote_addr;
+	bt_addr_le_t ev_addr;
+
+	bsim_btp_uart_init();
+
+	bsim_btp_wait_for_evt(BTP_SERVICE_ID_CORE, BTP_CORE_EV_IUT_READY, NULL);
+
+	bsim_btp_core_register(BTP_SERVICE_ID_GAP);
+	bsim_btp_gap_set_discoverable(BTP_GAP_GENERAL_DISCOVERABLE);
+	bsim_btp_gap_start_advertising(0U, 0U, NULL, BT_HCI_OWN_ADDR_PUBLIC);
+
+	bsim_btp_wait_for_gap_device_connected(&remote_addr);
+	bt_addr_le_to_str(&remote_addr, addr_str, sizeof(addr_str));
+	LOG_INF("Device %s connected", addr_str);
+
+	bsim_btp_wait_for_gap_device_disconnected(&ev_addr);
+	TEST_ASSERT(bt_addr_le_eq(&remote_addr, &ev_addr));
+	LOG_INF("Device %s disconnected", addr_str);
+
+	TEST_PASS("PASSED\n");
+}
+
+static const struct bst_test_instance test_sample[] = {
+	{
+		.test_id = "gap_peripheral",
+		.test_descr = "Smoketest for the GAP peripheral BT Tester behavior",
+		.test_main_f = test_gap_peripheral,
+	},
+	BSTEST_END_MARKER,
+};
+
+struct bst_test_list *test_gap_peripheral_install(struct bst_test_list *tests)
+{
+	return bst_add_tests(tests, test_sample);
+}
diff --git a/tests/bsim/bluetooth/tester/src/test_main.c b/tests/bsim/bluetooth/tester/src/test_main.c
new file mode 100644
index 00000000000..12328aebd4f
--- /dev/null
+++ b/tests/bsim/bluetooth/tester/src/test_main.c
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stddef.h>
+
+#include "bstests.h"
+
+extern struct bst_test_list *test_gap_central_install(struct bst_test_list *tests);
+extern struct bst_test_list *test_gap_peripheral_install(struct bst_test_list *tests);
+
+bst_test_install_t test_installers[] = {
+	test_gap_central_install,
+	test_gap_peripheral_install,
+	NULL,
+};
+
+int main(void)
+{
+	bst_main();
+	return 0;
+}
diff --git a/tests/bsim/bluetooth/tester/testcase.yaml b/tests/bsim/bluetooth/tester/testcase.yaml
new file mode 100644
index 00000000000..7adcd6a45fa
--- /dev/null
+++ b/tests/bsim/bluetooth/tester/testcase.yaml
@@ -0,0 +1,10 @@
+tests:
+  bluetooth.tester_bsim:
+    build_only: true
+    tags:
+      - bluetooth
+    harness: bsim
+    harness_config:
+      bsim_exe_name: tests_bsim_bluetooth_tester_prj_conf
+    platform_allow:
+      - nrf52_bsim/native
diff --git a/tests/bsim/bluetooth/tester/tests_scripts/gap.sh b/tests/bsim/bluetooth/tester/tests_scripts/gap.sh
new file mode 100755
index 00000000000..2809ad67b2d
--- /dev/null
+++ b/tests/bsim/bluetooth/tester/tests_scripts/gap.sh
@@ -0,0 +1,41 @@
+#!/usr/bin/env bash
+# Copyright 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# Smoketest for GAP BTP commands with the BT tester
+
+simulation_id="tester_gap"
+verbosity_level=2
+EXECUTE_TIMEOUT=100
+
+source ${ZEPHYR_BASE}/tests/bsim/sh_common.source
+
+cd ${BSIM_OUT_PATH}/bin
+
+UART_DIR=/tmp/bs_${USER}/${simulation_id}/
+UART_PER=${UART_DIR}/peripheral
+UART_CEN=${UART_DIR}/central
+
+# Central BT Tester
+Execute ./bs_${BOARD_TS}_tests_bluetooth_tester_prj_conf \
+  -v=${verbosity_level} -s=${simulation_id} -rs=10 -d=0 -RealEncryption=1 \
+  -uart0_fifob_rxfile=${UART_CEN}.tx -uart0_fifob_txfile=${UART_CEN}.rx
+
+# Central Upper Tester
+Execute ./bs_nrf52_bsim_native_tests_bsim_bluetooth_tester_prj_conf \
+  -v=${verbosity_level} -s=${simulation_id} -rs=21 -d=10 -RealEncryption=1 -testid=gap_central \
+  -nosim -uart0_fifob_rxfile=${UART_CEN}.rx -uart0_fifob_txfile=${UART_CEN}.tx
+
+# Peripheral BT Tester
+Execute ./bs_${BOARD_TS}_tests_bluetooth_tester_prj_conf \
+  -v=${verbosity_level} -s=${simulation_id} -rs=32 -d=1 -RealEncryption=1 \
+  -uart0_fifob_rxfile=${UART_PER}.tx -uart0_fifob_txfile=${UART_PER}.rx
+
+# Peripheral Upper Tester
+Execute ./bs_nrf52_bsim_native_tests_bsim_bluetooth_tester_prj_conf \
+  -v=${verbosity_level} -s=${simulation_id} -rs=43 -d=11 -RealEncryption=1 -testid=gap_peripheral \
+  -nosim -uart0_fifob_rxfile=${UART_PER}.rx -uart0_fifob_txfile=${UART_PER}.tx
+
+Execute ./bs_2G4_phy_v1 -v=${verbosity_level} -s=${simulation_id} -D=2 -sim_length=20e6 $@
+
+wait_for_background_jobs # Wait for all programs in background and return != 0 if any fails
diff --git a/tests/bsim/bluetooth/tests.nrf5340bsim_nrf5340_cpuapp.txt b/tests/bsim/bluetooth/tests.nrf5340bsim_nrf5340_cpuapp.txt
index b14d3819f5f..6b2ac3ff03a 100644
--- a/tests/bsim/bluetooth/tests.nrf5340bsim_nrf5340_cpuapp.txt
+++ b/tests/bsim/bluetooth/tests.nrf5340bsim_nrf5340_cpuapp.txt
@@ -1,7 +1,15 @@
 # Search paths(s) for tests which will be run in the nrf5340 split stack configuration
 # This file is used in CI to select which tests are run
 tests/bsim/bluetooth/ll/conn/tests_scripts/basic_conn_encrypted_split_privacy.sh
-tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso.sh
+tests/bsim/bluetooth/ll/throughput/
+tests/bsim/bluetooth/ll/multiple_id/
+tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_interleaved.sh
+tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_sequential.sh
+tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_ticker_expire_info.sh
 tests/bsim/bluetooth/samples/central_hr_peripheral_hr/
 tests/bsim/bluetooth/audio_samples/
 tests/bsim/bluetooth/audio/
+tests/bsim/bluetooth/host/gatt/notify_stress/
+tests/bsim/bluetooth/host/misc/hfc/
+tests/bsim/bluetooth/host/misc/hfc_multilink/
+tests/bsim/bluetooth/tester/
diff --git a/tests/bsim/bluetooth/tests.nrf54l15bsim_nrf54l15_cpuapp.txt b/tests/bsim/bluetooth/tests.nrf54l15bsim_nrf54l15_cpuapp.txt
index 8c39f8fbcc5..d5dee727d5e 100644
--- a/tests/bsim/bluetooth/tests.nrf54l15bsim_nrf54l15_cpuapp.txt
+++ b/tests/bsim/bluetooth/tests.nrf54l15bsim_nrf54l15_cpuapp.txt
@@ -1,4 +1,10 @@
 # Search paths(s) for tests which will be run in the nrf54l15 app core
 # This file is used in CI to select which tests are run
-tests/bsim/bluetooth/ll/multiple_id/tests_scripts/multiple.sh
+tests/bsim/bluetooth/ll/throughput/
+tests/bsim/bluetooth/ll/multiple_id/
+tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_interleaved.sh
+tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_sequential.sh
+tests/bsim/bluetooth/ll/bis/tests_scripts/broadcast_iso_ticker_expire_info.sh
 tests/bsim/bluetooth/samples/central_hr_peripheral_hr/
+tests/bsim/bluetooth/audio_samples/
+tests/bsim/bluetooth/audio/
diff --git a/tests/bsim/ci.uart.sh b/tests/bsim/ci.uart.sh
index 7f53fa86406..35f39b0c62a 100755
--- a/tests/bsim/ci.uart.sh
+++ b/tests/bsim/ci.uart.sh
@@ -21,8 +21,3 @@ echo " nRF54L15:"
 ${ZEPHYR_BASE}/scripts/twister -T tests/drivers/uart/ --force-color --inline-logs -v -M \
   -p nrf54l15bsim/nrf54l15/cpuapp --fixture gpio_loopback \
   -- -uart0_loopback -uart2_loopback
-
-echo "UART: Multi device tests"
-WORK_DIR=${ZEPHYR_BASE}/bsim_uart nice tests/bsim/drivers/uart/compile.sh
-RESULTS_FILE=${ZEPHYR_BASE}/bsim_out/bsim_results.uart.52.xml \
-SEARCH_PATH=tests/bsim/drivers/uart/ tests/bsim/run_parallel.sh
diff --git a/tests/bsim/run_parallel.sh b/tests/bsim/run_parallel.sh
index 01eb4bd6aa5..6ddb994a81d 100755
--- a/tests/bsim/run_parallel.sh
+++ b/tests/bsim/run_parallel.sh
@@ -1,6 +1,7 @@
 #!/usr/bin/env bash
 # Copyright 2018 Oticon A/S
 # SPDX-License-Identifier: Apache-2.0
+set -eo pipefail
 
 start=$SECONDS
 
@@ -51,7 +52,8 @@ elif [ -n "${TESTS_LIST}" ]; then
 	all_cases=${TESTS_LIST}
 else
 	SEARCH_PATH="${SEARCH_PATH:-.}"
-	all_cases=`find ${SEARCH_PATH} -name "*.sh" | grep -Ev "${sh_filter}"`
+	all_cases=`find ${SEARCH_PATH} -name "*.sh" | grep -Ev "${sh_filter}"` \
+	          || (echo "No tests found"; exit 1)
 	#we dont run ourselves
 fi
 
@@ -98,6 +100,7 @@ if [ `command -v parallel` ]; then
     ' ::: $all_cases >> $tmp_res_file ; err=$?
   fi
 else #fallback in case parallel is not installed
+  set +e
   for case in $all_cases; do
     echo "<testcase name=\"$case\" time=\"0\">" >> $tmp_res_file
     $case $@ &> $i.log
diff --git a/tests/bsim/sh_common.source b/tests/bsim/sh_common.source
index b727b933e1a..5231e99f4d3 100644
--- a/tests/bsim/sh_common.source
+++ b/tests/bsim/sh_common.source
@@ -13,7 +13,7 @@ BOARD="${BOARD:-nrf52_bsim/native}"
 BOARD_TS="${BOARD//\//_}"
 
 function run_in_background(){
-  $@ & _process_ids="$_process_ids $!"
+  "$@" & _process_ids="$_process_ids $!"
 }
 
 function wait_for_background_jobs(){
@@ -46,7 +46,7 @@ function Execute() {
   EXECUTE_TIMEOUT="${EXECUTE_TIMEOUT:-30}"
 
   check_program_exists $1
-  run_in_background timeout --kill-after=5 -v ${EXECUTE_TIMEOUT} $@
+  run_in_background timeout --kill-after=5 -v ${EXECUTE_TIMEOUT} "$@"
 }
 
 function _guess_test_relpath(){
diff --git a/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/board.cmake b/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/board.cmake
index 27c74975756..f89df3a4486 100644
--- a/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/board.cmake
+++ b/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/board.cmake
@@ -3,6 +3,7 @@
 # Copyright (c) 2024, Nordic Semiconductor ASA
 
 if(CONFIG_BOARD_MPS2_AN521_CPUTEST)
+  set(SUPPORTED_EMU_PLATFORMS qemu)
   set(QEMU_CPU_TYPE_${ARCH} cortex-m33)
   set(QEMU_FLAGS_${ARCH}
     -cpu ${QEMU_CPU_TYPE_${ARCH}}
diff --git a/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2-pinctrl.dtsi b/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2-pinctrl.dtsi
new file mode 100644
index 00000000000..da259040e97
--- /dev/null
+++ b/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2-pinctrl.dtsi
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/arm-mps2-pinctrl.h>
+
+&pinctrl {
+	/omit-if-no-ref/  uart3_default: uart3_default {
+		group1 {
+			pinmux = <UART3_TXD_EXP>;
+		};
+
+		group2 {
+			pinmux = <UART3_RXD_EXP>;
+			input-enable;
+		};
+	};
+
+	 /omit-if-no-ref/ uart4_default: uart4_default {
+		 group1 {
+			 pinmux = <UART4_TXD_EXP>;
+		};
+
+		group2 {
+			pinmux = <UART4_RXD_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ spi0_default: spi0_default {
+		group1 {
+			pinmux = <SPI3_SCK_EXP>, <SPI3_SS_EXP>,
+				  <SPI3_MOSI_EXP>;
+		};
+		group2 {
+			pinmux = <SPI3_MISO_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ spi1_default: spi1_default {
+		group1 {
+			pinmux = <SPI4_SCK_EXP>, <SPI4_SS_EXP>,
+				 <SPI4_MOSI_EXP>;
+		};
+		group2 {
+			pinmux = <SPI4_MISO_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ sbcon0_default: sbcon0_default {
+		group1 {
+			pinmux = <SBCON2_SCL_EXP>, <SBCON2_SDA_EXP>;
+			input-enable;
+		};
+	};
+
+	/omit-if-no-ref/ sbcon1_default: sbcon1_default {
+		group1 {
+			pinmux = <SBCON3_SCL_EXP>, <SBCON3_SDA_EXP>;
+			input-enable;
+		};
+	};
+};
diff --git a/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2_an521-common.dtsi b/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2_an521-common.dtsi
index 5b1959ff5fe..b96f1144982 100644
--- a/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2_an521-common.dtsi
+++ b/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2_an521-common.dtsi
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2019 Linaro Limited
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -112,6 +113,8 @@ uart3: uart@203000 {
 	interrupt-names = "tx", "rx";
 	clocks = <&sysclk>;
 	current-speed = <115200>;
+	pinctrl-0 = <&uart3_default>;
+	pinctrl-names = "default";
 };
 
 uart4: uart@204000 {
@@ -121,6 +124,8 @@ uart4: uart@204000 {
 	interrupt-names = "tx", "rx";
 	clocks = <&sysclk>;
 	current-speed = <115200>;
+	pinctrl-0 = <&uart4_default>;
+	pinctrl-names = "default";
 };
 
 i2c_touch: i2c@207000 {
@@ -145,6 +150,8 @@ i2c_shield0: i2c@20c000 {
 	#address-cells = <1>;
 	#size-cells = <0>;
 	reg = <0x20c000 0x1000>;
+	pinctrl-0 = <&sbcon0_default>;
+	pinctrl-names = "default";
 };
 
 i2c_shield1: i2c@20d000 {
@@ -153,10 +160,12 @@ i2c_shield1: i2c@20d000 {
 	#address-cells = <1>;
 	#size-cells = <0>;
 	reg = <0x20d000 0x1000>;
+	pinctrl-0 = <&sbcon1_default>;
+	pinctrl-names = "default";
 };
 
 gpio_led0: mps2_fpgaio@302000 {
-	compatible = "arm,mps2-fpgaio-gpio";
+	compatible = "arm,mmio32-gpio";
 
 	reg = <0x302000 0x4>;
 	gpio-controller;
@@ -165,16 +174,17 @@ gpio_led0: mps2_fpgaio@302000 {
 };
 
 gpio_button: mps2_fpgaio@302008 {
-	compatible = "arm,mps2-fpgaio-gpio";
+	compatible = "arm,mmio32-gpio";
 
 	reg = <0x302008 0x4>;
 	gpio-controller;
 	#gpio-cells = <1>;
 	ngpios = <2>;
+	direction-input;
 };
 
 gpio_misc: mps2_fpgaio@30204c {
-	compatible = "arm,mps2-fpgaio-gpio";
+	compatible = "arm,mmio32-gpio";
 
 	reg = <0x30204c 0x4>;
 	gpio-controller;
@@ -189,3 +199,8 @@ eth0: eth@2000000 {
 	reg = <0x2000000 0x100000>;
 	interrupts = <48 3>;
 };
+
+pinctrl: pinctrl {
+	compatible = "arm,mps2-pinctrl";
+	status = "okay";
+};
diff --git a/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2_an521_cputest.dts b/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2_an521_cputest.dts
index 2bb956645ca..532384377da 100644
--- a/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2_an521_cputest.dts
+++ b/tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2_an521_cputest.dts
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2018-2019 Linaro Limited
+ * Copyright 2025 Arm Limited and/or its affiliates <open-source-office@arm.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -128,3 +129,5 @@
 &uart1 {
 	status = "okay";
 };
+
+#include "mps2-pinctrl.dtsi"
diff --git a/tests/cmake/hwm/board_extend/oot_root/boards/native/native_sim_extend/native_sim_native_one.dts b/tests/cmake/hwm/board_extend/oot_root/boards/native/native_sim_extend/native_sim_native_one.dts
index 652c7605f60..d12737469d2 100644
--- a/tests/cmake/hwm/board_extend/oot_root/boards/native/native_sim_extend/native_sim_native_one.dts
+++ b/tests/cmake/hwm/board_extend/oot_root/boards/native/native_sim_extend/native_sim_native_one.dts
@@ -52,7 +52,7 @@
 		#size-cells = <0>;
 
 		cpu0: cpu@0 {
-			compatible = "zephyr,native-posix-cpu";
+			compatible = "zephyr,native-sim-cpu";
 			reg = <0>;
 		};
 	};
@@ -135,7 +135,7 @@
 
 	uart0: uart {
 		status = "okay";
-		compatible = "zephyr,native-posix-uart";
+		compatible = "zephyr,native-pty-uart";
 		/* Dummy current-speed entry to comply with serial
 		 * DTS binding
 		 */
@@ -144,7 +144,7 @@
 
 	uart1: uart_1 {
 		status = "okay";
-		compatible = "zephyr,native-posix-uart";
+		compatible = "zephyr,native-pty-uart";
 		/* Dummy current-speed entry to comply with serial
 		 * DTS binding
 		 */
@@ -153,12 +153,12 @@
 
 	rng: rng {
 		status = "okay";
-		compatible = "zephyr,native-posix-rng";
+		compatible = "zephyr,native-sim-rng";
 	};
 
 	counter0: counter {
 		status = "okay";
-		compatible = "zephyr,native-posix-counter";
+		compatible = "zephyr,native-sim-counter";
 	};
 
 	gpio0: gpio@800 {
diff --git a/tests/cmake/hwm/board_extend/testcase.yaml b/tests/cmake/hwm/board_extend/testcase.yaml
index aae39ce6b2c..53cfe6a6139 100644
--- a/tests/cmake/hwm/board_extend/testcase.yaml
+++ b/tests/cmake/hwm/board_extend/testcase.yaml
@@ -2,7 +2,7 @@ common:
   tags:
     - cmake
 tests:
-  cmake.board.extend_one:
+  buildsystem.cmake.board.extend_one:
     extra_args:
       # Twister can only lookup known board roots.
       # Thus platform above is set to native_sim, while at this location
@@ -15,7 +15,7 @@ tests:
     integration_platforms:
       - native_sim
       - native_sim/native/64
-  cmake.board.extend_two:
+  buildsystem.cmake.board.extend_two:
     extra_args:
       - CACHED_BOARD=native_sim/native/64/two
     platform_allow:
@@ -24,7 +24,7 @@ tests:
     integration_platforms:
       - native_sim
       - native_sim/native/64
-  cmake.soc.extend_cputest:
+  buildsystem.cmake.soc.extend_cputest:
     extra_args:
       - CACHED_BOARD=mps2/an521/cputest
     platform_allow:
diff --git a/tests/cmake/yaml/CMakeLists.txt b/tests/cmake/yaml/CMakeLists.txt
index 97cf10ecefc..43f93a28b15 100644
--- a/tests/cmake/yaml/CMakeLists.txt
+++ b/tests/cmake/yaml/CMakeLists.txt
@@ -2,24 +2,34 @@
 
 cmake_minimum_required(VERSION 3.20.0)
 
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(zephyr_yaml_test)
-target_sources(app PRIVATE ${ZEPHYR_BASE}/misc/empty_file.c)
+if(NOT CMAKE_SCRIPT_MODE_FILE)
+  # Project mode initialization (main CMake invocation)
+  find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+  project(zephyr_yaml_test)
+  target_sources(app PRIVATE ${ZEPHYR_BASE}/misc/empty_file.c)
+  message(STATUS "Run 1 -------------\n  CMake PROJECT mode\n----------------------")
+else()
+  # Script mode initialization (re-run)
+  set(ZEPHYR_BASE ${CMAKE_CURRENT_LIST_DIR}/../../../)
+  list(APPEND CMAKE_MODULE_PATH "${ZEPHYR_BASE}/cmake/modules")
+  include(yaml)
+  message(STATUS "Run 2 ------------\n  CMake SCRIPT mode\n---------------------")
+endif()
 
 set_property(GLOBAL PROPERTY EXPECTED_ERROR 0)
 
 macro(message)
   if(DEFINED expect_failure)
-  if(${ARGV0} STREQUAL FATAL_ERROR)
-    if("${ARGV1}" STREQUAL "${expect_failure}")
-      # This is an expected error.
-      get_property(error_count GLOBAL PROPERTY EXPECTED_ERROR)
-      math(EXPR error_count "${error_count} + 1")
-      set_property(GLOBAL PROPERTY EXPECTED_ERROR ${error_count})
-      return()
-    else()
-      _message("Unexpected error occurred")
-    endif()
+    if(${ARGV0} STREQUAL FATAL_ERROR)
+      if("${ARGV1}" STREQUAL "${expect_failure}")
+        # This is an expected error.
+        get_property(error_count GLOBAL PROPERTY EXPECTED_ERROR)
+        math(EXPR error_count "${error_count} + 1")
+        set_property(GLOBAL PROPERTY EXPECTED_ERROR ${error_count})
+        return()
+      else()
+        _message("Unexpected error occurred")
+      endif()
     endif()
   endif()
   _message(${ARGN})
@@ -182,7 +192,7 @@ function(test_setting_string)
   )
 
   set(new_value "A new string")
-  yaml_set(actual NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+  yaml_set(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
            KEY cmake test set key-string VALUE ${new_value}
   )
 
@@ -206,7 +216,39 @@ function(test_setting_list_strings)
   )
 
   set(new_value "A" "new" "list" "of" "strings")
-  yaml_set(actual NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+  yaml_set(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+           KEY cmake test set key-list-string LIST ${new_value}
+  )
+
+  yaml_save(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create)
+
+  # Read-back the yaml and verify the value.
+  yaml_load(FILE ${CMAKE_BINARY_DIR}/${CMAKE_CURRENT_FUNCTION}_test_create.yaml
+            NAME ${CMAKE_CURRENT_FUNCTION}_readback
+  )
+
+  yaml_length(readback NAME ${CMAKE_CURRENT_FUNCTION}_readback KEY cmake test set key-list-string)
+
+  test_assert(TEST 5 EQUAL ${readback}
+              COMMENT "readback yaml list length does not match original."
+  )
+
+  yaml_get(readback NAME ${CMAKE_CURRENT_FUNCTION}_readback KEY cmake test set key-list-string)
+
+  foreach(a e IN ZIP_LISTS readback new_value)
+    test_assert(TEST "${e}" STREQUAL "${a}"
+                COMMENT "list values mismatch."
+    )
+  endforeach()
+endfunction()
+
+function(test_setting_list_escaped_strings)
+  yaml_create(FILE ${CMAKE_BINARY_DIR}/${CMAKE_CURRENT_FUNCTION}_test_create.yaml
+              NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+  )
+
+  set(new_value "back\\slash" "dou\"ble" "sin'gle" "co:lon" "win:\\path")
+  yaml_set(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
            KEY cmake test set key-list-string LIST ${new_value}
   )
 
@@ -225,6 +267,65 @@ function(test_setting_list_strings)
 
   yaml_get(readback NAME ${CMAKE_CURRENT_FUNCTION}_readback KEY cmake test set key-list-string)
 
+  foreach(a e IN ZIP_LISTS readback new_value)
+    # cmake_parse_arguments() breaks horribly when given strings that include
+    # escapes, making it impossible to use test_assert() here. Or, for that
+    # matter, even trying to print them in message(). Thanks, CMake!
+    if("${e}" STREQUAL "${a}")
+      message("${CMAKE_CURRENT_FUNCTION}(): Passed")
+    else()
+      message(FATAL_ERROR
+        "${CMAKE_CURRENT_FUNCTION}(): Failed\n"
+        "Test: list values mismatch."
+      )
+    endif()
+  endforeach()
+endfunction()
+
+function(test_append_list_strings)
+  yaml_create(FILE ${CMAKE_BINARY_DIR}/${CMAKE_CURRENT_FUNCTION}_test_create.yaml
+              NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+  )
+
+  # start with entries that will be overwritten
+  yaml_set(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+           KEY cmake test set key-list-string
+           LIST dropped entries
+  )
+
+  set(new_value "A" "new" "list" "of" "strings")
+  list(GET new_value 0 first)
+  list(SUBLIST new_value 1 -1 others)
+
+  # re-initialize the list with the first correct value
+  yaml_set(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+           KEY cmake test set key-list-string
+           LIST ${first}
+  )
+
+  # append the rest of the values
+  foreach(entry IN LISTS others)
+    yaml_set(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+             KEY cmake test set key-list-string
+             APPEND LIST ${entry}
+    )
+  endforeach()
+
+  yaml_save(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create)
+
+  # Read-back the yaml and verify the value.
+  yaml_load(FILE ${CMAKE_BINARY_DIR}/${CMAKE_CURRENT_FUNCTION}_test_create.yaml
+            NAME ${CMAKE_CURRENT_FUNCTION}_readback
+  )
+
+  yaml_length(readback NAME ${CMAKE_CURRENT_FUNCTION}_readback KEY cmake test set key-list-string)
+
+  test_assert(TEST 5 EQUAL ${readback}
+              COMMENT "readback yaml list length does not match original."
+  )
+
+  yaml_get(readback NAME ${CMAKE_CURRENT_FUNCTION}_readback KEY cmake test set key-list-string)
+
   foreach(a e IN ZIP_LISTS readback new_value)
     test_assert(TEST "${e}" STREQUAL "${a}"
                 COMMENT "list values mismatch."
@@ -238,7 +339,7 @@ function(test_setting_int)
   )
 
   set(new_value 42)
-  yaml_set(actual NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+  yaml_set(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
            KEY cmake test set key-int VALUE ${new_value}
   )
 
@@ -262,7 +363,7 @@ function(test_setting_list_int)
   )
 
   set(new_value 42 41 40 2 10)
-  yaml_set(actual NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+  yaml_set(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
            KEY cmake test set key-list-int LIST ${new_value}
   )
 
@@ -414,7 +515,7 @@ function(test_setting_map_list_entry_commas)
     test_assert(TEST "${readback_name}" STREQUAL "${new_entry_name_${index}}"
                 COMMENT "list values mismatch."
     )
-    test_assert(TEST "'${readback_str}'" STREQUAL "${new_entry_str_${index}}"
+    test_assert(TEST "${readback_str}" STREQUAL "${new_entry_str_${index}}"
                 COMMENT "list values mismatch."
     )
   endforeach()
@@ -425,7 +526,7 @@ function(test_setting_empty_value)
   )
 
   set(new_value)
-  yaml_set(actual NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+  yaml_set(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
            KEY cmake test set key-int VALUE ${new_value}
   )
 
@@ -479,6 +580,164 @@ function(test_setting_empty_list)
   endforeach()
 endfunction()
 
+function(test_setting_genexes)
+  set(file ${CMAKE_BINARY_DIR}/test_setting_genexes.yaml)
+  yaml_create(FILE ${file}
+              NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+  )
+
+  set(new_value "string before changes")
+  yaml_set(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+           KEY cmake test set key-string
+           VALUE ${new_value}
+  )
+
+  set_property(TARGET app PROPERTY expanding_str "expanded genex")
+  set(new_value "$<TARGET_PROPERTY:app,expanding_str>")
+  yaml_set(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+           KEY cmake test set key-string-genex
+           GENEX VALUE ${new_value}
+  )
+
+  # create the list by appending in several steps to test conversion
+  # from JSON list to genex stringified list
+  yaml_set(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+           KEY cmake test set key-list-string-genex
+           LIST "A"
+  )
+  set_property(TARGET app PROPERTY expanding_list "temporary" "list")
+  yaml_set(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+           KEY cmake test set key-list-string-genex
+           APPEND GENEX LIST "$<TARGET_PROPERTY:app,expanding_list>" "of"
+  )
+  yaml_set(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+           KEY cmake test set key-list-string-genex
+           APPEND LIST "strings"
+  )
+
+  yaml_save(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create)
+
+  # Read-back the yaml immediately and verify the genex values are NOT present
+  # (genexes are expanded at generation time)
+  yaml_load(FILE ${file}
+            NAME ${CMAKE_CURRENT_FUNCTION}_readback
+  )
+
+  yaml_get(readback NAME ${CMAKE_CURRENT_FUNCTION}_readback KEY cmake test set key-string)
+  set(expected "string before changes")
+
+  test_assert(TEST ${expected} STREQUAL ${readback}
+              COMMENT "yaml key value does not match expectation."
+  )
+
+  yaml_length(readback NAME ${CMAKE_CURRENT_FUNCTION}_readback KEY cmake test set key-list-string-genex)
+  set(expected cmake-test-set-key-list-string-genex-NOTFOUND)
+
+  test_assert(TEST ${expected} STREQUAL ${readback}
+              COMMENT "Expected -NOTFOUND, but something was found."
+  )
+
+  yaml_get(readback NAME ${CMAKE_CURRENT_FUNCTION}_readback KEY cmake test set key-string-genex)
+  set(expected cmake-test-set-key-string-genex-NOTFOUND)
+
+  test_assert(TEST ${expected} STREQUAL ${readback}
+              COMMENT "Expected -NOTFOUND, but something was found."
+  )
+
+  # modify the expanding_list property and the string, then save the file once
+  # more to check the final values are used in the output yaml file
+  set_property(TARGET app PROPERTY expanding_list "new" "list")
+  set(new_value "string after changes")
+  yaml_set(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+           KEY cmake test set key-string
+           VALUE ${new_value}
+  )
+
+  yaml_save(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create)
+endfunction()
+
+function(test_verify_genexes)
+  set(file ${CMAKE_BINARY_DIR}/test_setting_genexes.yaml)
+  yaml_load(FILE ${file}
+      NAME ${CMAKE_CURRENT_FUNCTION}_readback
+  )
+
+  yaml_get(readback NAME ${CMAKE_CURRENT_FUNCTION}_readback KEY cmake test set key-string)
+  set(expected "string after changes")
+
+  test_assert(TEST ${expected} STREQUAL ${readback}
+              COMMENT "yaml key value does not match expectation."
+  )
+
+  set(expected "expanded genex")
+  yaml_get(readback NAME ${CMAKE_CURRENT_FUNCTION}_readback KEY cmake test set key-string-genex)
+
+  test_assert(TEST ${expected} STREQUAL ${readback}
+        COMMENT "new yaml value does not match readback value."
+  )
+
+  set(expected "A" "new" "list" "of" "strings")
+  list(LENGTH expected exp_len)
+
+  yaml_get(readback NAME ${CMAKE_CURRENT_FUNCTION}_readback KEY cmake test set key-list-string-genex)
+  yaml_length(act_len NAME ${CMAKE_CURRENT_FUNCTION}_readback KEY cmake test set key-list-string-genex)
+
+  test_assert(TEST ${exp_len} EQUAL ${act_len}
+              COMMENT "yaml list length does not match expectation."
+  )
+
+  foreach(a e IN ZIP_LISTS readback expected)
+    test_assert(TEST "${e}" STREQUAL "${a}"
+                COMMENT "list values mismatch."
+    )
+  endforeach()
+endfunction()
+
+function(test_setting_escaped_genexes)
+  set(file ${CMAKE_BINARY_DIR}/test_setting_escaped_genexes.yaml)
+  yaml_create(FILE ${file}
+              NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+  )
+
+  set_property(TARGET app PROPERTY escaped_list
+               "back\\slash" "dou\"ble" "sin'gle" "co:lon" "win:\\path")
+  yaml_set(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+           KEY cmake test set key-list-string-genex
+           GENEX LIST "$<TARGET_PROPERTY:app,escaped_list>"
+  )
+
+  yaml_save(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create)
+endfunction()
+
+function(test_verify_escaped_genexes)
+  set(file ${CMAKE_BINARY_DIR}/test_setting_escaped_genexes.yaml)
+  yaml_load(FILE ${file}
+      NAME ${CMAKE_CURRENT_FUNCTION}_readback
+  )
+
+  set(expected "back\\slash" "dou\"ble" "sin'gle" "co:lon" "win:\\path")
+  list(LENGTH expected exp_len)
+
+  yaml_get(readback NAME ${CMAKE_CURRENT_FUNCTION}_readback KEY cmake test set key-list-string-genex)
+  yaml_length(act_len NAME ${CMAKE_CURRENT_FUNCTION}_readback KEY cmake test set key-list-string-genex)
+
+  test_assert(TEST ${exp_len} EQUAL ${act_len}
+              COMMENT "yaml list length does not match expectation."
+  )
+
+  foreach(a e IN ZIP_LISTS readback expected)
+    # See comment in test_setting_list_escaped_strings() for why test_assert() is not used here.
+    if("${e}" STREQUAL "${a}")
+      message("${CMAKE_CURRENT_FUNCTION}(): Passed")
+    else()
+      message(FATAL_ERROR
+        "${CMAKE_CURRENT_FUNCTION}(): Failed\n"
+        "Test: key-list-string-genex list values mismatch."
+      )
+    endif()
+  endforeach()
+endfunction()
+
 function(test_set_remove_int)
   yaml_create(FILE ${CMAKE_BINARY_DIR}/${CMAKE_CURRENT_FUNCTION}_test_create.yaml
               NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
@@ -524,7 +783,7 @@ function(test_fail_missing_filename)
   yaml_create(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create)
 
   set(new_value 42)
-  yaml_set(actual NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
+  yaml_set(NAME ${CMAKE_CURRENT_FUNCTION}_yaml-create
            KEY cmake test set key-int VALUE ${new_value}
   )
 
@@ -554,6 +813,7 @@ test_save_new_file()
 test_setting_int()
 test_setting_string()
 test_setting_list_strings()
+test_setting_list_escaped_strings()
 test_setting_list_int()
 test_setting_map_list_entry()
 test_setting_map_list_entry_windows()
@@ -562,8 +822,28 @@ test_setting_map_list_entry_commas()
 test_setting_empty_value()
 test_setting_empty_list()
 
+test_append_list_strings()
+
 test_set_remove_int()
 
 test_fail_missing_filename()
 
-target_sources(app PRIVATE src/main.c)
+# Generator expressions cannot be tested immediately, since they are expanded
+# at project generation time. The script mode re-run is delayed until after
+# the associated target has been built, and the verification is performed at
+# that time.
+if(NOT CMAKE_SCRIPT_MODE_FILE)
+  # create a file containing genexes
+  test_setting_genexes()
+  test_setting_escaped_genexes()
+
+  # Spawn a new CMake instance to re-run the whole test suite in script mode
+  # and verify the genex values once the associated target is built.
+  add_custom_command(TARGET app POST_BUILD
+    COMMAND ${CMAKE_COMMAND} -P ${CMAKE_CURRENT_LIST_FILE}
+  )
+else()
+  # verify the contents of the created genex files
+  test_verify_genexes()
+  test_verify_escaped_genexes()
+endif()
diff --git a/tests/cmake/yaml/src/main.c b/tests/cmake/yaml/src/main.c
deleted file mode 100644
index 0bed5a30798..00000000000
--- a/tests/cmake/yaml/src/main.c
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (c) 2024 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-void test_main(void)
-{
-	/* Intentionally left empty, we are testing CMake. */
-}
diff --git a/tests/ctest/base/CMakeLists.txt b/tests/ctest/base/CMakeLists.txt
new file mode 100644
index 00000000000..2fb9d23e72d
--- /dev/null
+++ b/tests/ctest/base/CMakeLists.txt
@@ -0,0 +1,26 @@
+# Copyright (c) 2024 Basalte bv
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+project(ctest_base)
+
+target_sources(app PRIVATE ${ZEPHYR_BASE}/misc/empty_file.c)
+
+enable_testing()
+include(CTest)
+
+add_test(NAME exe_help COMMAND ${CMAKE_BINARY_DIR}/zephyr/zephyr.exe --help)
+add_test(NAME exe_run COMMAND ${CMAKE_BINARY_DIR}/zephyr/zephyr.exe -stop_at=3 -no-rt)
+set_property(
+  TEST exe_run
+  PROPERTY PASS_REGULAR_EXPRESSION "Stopped at [0-9.]+s"
+)
+
+# A test that always succeeds
+add_test(NAME success COMMAND ${CMAKE_COMMAND} -E true)
+
+# A test that is expected to fail
+add_test(NAME failure COMMAND ${CMAKE_COMMAND} -E false)
+set_property(TEST failure PROPERTY WILL_FAIL true)
diff --git a/tests/ctest/base/prj.conf b/tests/ctest/base/prj.conf
new file mode 100644
index 00000000000..bb7b160deb3
--- /dev/null
+++ b/tests/ctest/base/prj.conf
@@ -0,0 +1 @@
+# Intentionally empty
diff --git a/tests/ctest/base/testcase.yaml b/tests/ctest/base/testcase.yaml
new file mode 100644
index 00000000000..f10d3945b7a
--- /dev/null
+++ b/tests/ctest/base/testcase.yaml
@@ -0,0 +1,10 @@
+common:
+  tags:
+    - test_framework
+  platform_allow:
+    - native_sim
+  integration_platforms:
+    - native_sim
+  harness: ctest
+tests:
+  testing.ctest.base: {}
diff --git a/tests/drivers/adc/adc_accuracy_test/Kconfig b/tests/drivers/adc/adc_accuracy_test/Kconfig
index 9264c69f8bb..cc9e640a257 100644
--- a/tests/drivers/adc/adc_accuracy_test/Kconfig
+++ b/tests/drivers/adc/adc_accuracy_test/Kconfig
@@ -1,4 +1,5 @@
 # Copyright (c) 2023 Intel Corporation
+# Copyright (c) 2025 Renesas Electronics Corporation
 #
 # SPDX-License-Identifier: Apache-2.0
 
@@ -11,12 +12,22 @@ ZEPHYR_USER := zephyr,user
 
 config DAC_SOURCE_TEST
 	bool
+	select DAC
 	default y if $(dt_node_has_prop,/$(ZEPHYR_USER),dac)
 
 config REFERENCE_VOLTAGE_TEST
 	bool
-	default y if $(dt_node_has_prop,/$(ZEPHYR_USER),reference_mv)
+	default y if $(dt_node_has_prop,/$(ZEPHYR_USER),reference-mv)
 
 config NUMBER_OF_PASSES
 	int "Number of passes"
 	default 5
+
+if DAC_SOURCE_TEST
+
+config DAC_BUFFER_NOT_SUPPORTED
+	bool "DAC on board/SoC does not support output buffer mode"
+	help
+	  If this config is selected, the test will run with no output buffer enabled
+
+endif # DAC_SOURCE_TEST
diff --git a/tests/drivers/adc/adc_accuracy_test/README.txt b/tests/drivers/adc/adc_accuracy_test/README.txt
index 6c233052001..f3af83f7fbb 100644
--- a/tests/drivers/adc/adc_accuracy_test/README.txt
+++ b/tests/drivers/adc/adc_accuracy_test/README.txt
@@ -17,5 +17,5 @@ voltage on the same range.
 
 In the reference voltage case, the ADC is expected to be connected to a
 known voltage reference, whose value is informed, in millivolts, at
-property "reference_mv" from "zephyr,user" node. The test reads the ADC
+property "reference-mv" from "zephyr,user" node. The test reads the ADC
 to see if they match.
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/adc/adc_accuracy_test/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..a086510fad0
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,28 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>;
+		reference-mv = <1800>;
+		expected-accuracy = <64>;
+	};
+};
+
+&adc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1_2";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN2>;
+		zephyr,resolution = <14>;
+	};
+};
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/adc/adc_accuracy_test/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..a086510fad0
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,28 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>;
+		reference-mv = <1800>;
+		expected-accuracy = <64>;
+	};
+};
+
+&adc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1_2";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN2>;
+		zephyr,resolution = <14>;
+	};
+};
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4e2.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4e2.overlay
index 83209ee3b9e..f3269f1c970 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4e2.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4e2.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,8 +7,9 @@
 / {
 	zephyr,user {
 		io-channels = <&adc0 0>;
-		reference_mv = <3300>;
-		expected_accuracy = <32>;
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
 	};
 };
 
@@ -23,6 +24,5 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,vref-mv = <3300>;
 	};
 };
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4l1.conf b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4l1.conf
new file mode 100644
index 00000000000..c62973e5d9c
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4l1.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DAC_BUFFER_NOT_SUPPORTED=y
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4l1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4l1.overlay
new file mode 100644
index 00000000000..33657ece6cb
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4l1.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 1>;
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
+
+&adc0{
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m1.conf b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m1.conf
new file mode 100644
index 00000000000..c62973e5d9c
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m1.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DAC_BUFFER_NOT_SUPPORTED=y
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m1.overlay
new file mode 100644
index 00000000000..fb66167f36b
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m1.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 0>;
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
+
+&adc0{
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m2.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m2.overlay
index 83209ee3b9e..f3269f1c970 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m2.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m2.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,8 +7,9 @@
 / {
 	zephyr,user {
 		io-channels = <&adc0 0>;
-		reference_mv = <3300>;
-		expected_accuracy = <32>;
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
 	};
 };
 
@@ -23,6 +24,5 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,vref-mv = <3300>;
 	};
 };
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m3.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m3.overlay
index 83209ee3b9e..f3269f1c970 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m3.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4m3.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,8 +7,9 @@
 / {
 	zephyr,user {
 		io-channels = <&adc0 0>;
-		reference_mv = <3300>;
-		expected_accuracy = <32>;
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
 	};
 };
 
@@ -23,6 +24,5 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,vref-mv = <3300>;
 	};
 };
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4w1.conf b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4w1.conf
new file mode 100644
index 00000000000..c62973e5d9c
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4w1.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DAC_BUFFER_NOT_SUPPORTED=y
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4w1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4w1.overlay
index 7fce9ba7871..a202ba4d2c5 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4w1.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra4w1.overlay
@@ -7,8 +7,9 @@
 / {
 	zephyr,user {
 		io-channels = <&adc0 4>;
-		reference_mv = <3300>;
-		expected_accuracy = <32>;
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
 	};
 };
 
@@ -23,6 +24,5 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,vref-mv = <3300>;
 	};
 };
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6e2.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6e2.overlay
index 83209ee3b9e..f3269f1c970 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6e2.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6e2.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,8 +7,9 @@
 / {
 	zephyr,user {
 		io-channels = <&adc0 0>;
-		reference_mv = <3300>;
-		expected_accuracy = <32>;
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
 	};
 };
 
@@ -23,6 +24,5 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,vref-mv = <3300>;
 	};
 };
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m1.overlay
index 83209ee3b9e..f3269f1c970 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m1.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m1.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,8 +7,9 @@
 / {
 	zephyr,user {
 		io-channels = <&adc0 0>;
-		reference_mv = <3300>;
-		expected_accuracy = <32>;
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
 	};
 };
 
@@ -23,6 +24,5 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,vref-mv = <3300>;
 	};
 };
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m2.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m2.overlay
index 83209ee3b9e..f3269f1c970 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m2.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m2.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,8 +7,9 @@
 / {
 	zephyr,user {
 		io-channels = <&adc0 0>;
-		reference_mv = <3300>;
-		expected_accuracy = <32>;
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
 	};
 };
 
@@ -23,6 +24,5 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,vref-mv = <3300>;
 	};
 };
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m3.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m3.overlay
index 83209ee3b9e..f3269f1c970 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m3.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m3.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,8 +7,9 @@
 / {
 	zephyr,user {
 		io-channels = <&adc0 0>;
-		reference_mv = <3300>;
-		expected_accuracy = <32>;
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
 	};
 };
 
@@ -23,6 +24,5 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,vref-mv = <3300>;
 	};
 };
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m4.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m4.overlay
index 83209ee3b9e..f3269f1c970 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m4.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m4.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,8 +7,9 @@
 / {
 	zephyr,user {
 		io-channels = <&adc0 0>;
-		reference_mv = <3300>;
-		expected_accuracy = <32>;
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
 	};
 };
 
@@ -23,6 +24,5 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,vref-mv = <3300>;
 	};
 };
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m5.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m5.overlay
index 83209ee3b9e..f3269f1c970 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m5.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra6m5.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,8 +7,9 @@
 / {
 	zephyr,user {
 		io-channels = <&adc0 0>;
-		reference_mv = <3300>;
-		expected_accuracy = <32>;
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
 	};
 };
 
@@ -23,6 +24,5 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,vref-mv = <3300>;
 	};
 };
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8d1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8d1.overlay
index 83209ee3b9e..f3269f1c970 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8d1.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8d1.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,8 +7,9 @@
 / {
 	zephyr,user {
 		io-channels = <&adc0 0>;
-		reference_mv = <3300>;
-		expected_accuracy = <32>;
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
 	};
 };
 
@@ -23,6 +24,5 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,vref-mv = <3300>;
 	};
 };
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8m1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8m1.overlay
index 83209ee3b9e..f3269f1c970 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8m1.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ek_ra8m1.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,8 +7,9 @@
 / {
 	zephyr,user {
 		io-channels = <&adc0 0>;
-		reference_mv = <3300>;
-		expected_accuracy = <32>;
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
 	};
 };
 
@@ -23,6 +24,5 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,vref-mv = <3300>;
 	};
 };
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra4e1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra4e1.overlay
new file mode 100644
index 00000000000..fb66167f36b
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra4e1.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 0>;
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
+	};
+};
+
+&adc0{
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra6e1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra6e1.overlay
index 83209ee3b9e..f3269f1c970 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra6e1.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra6e1.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,8 +7,9 @@
 / {
 	zephyr,user {
 		io-channels = <&adc0 0>;
-		reference_mv = <3300>;
-		expected_accuracy = <32>;
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
 	};
 };
 
@@ -23,6 +24,5 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,vref-mv = <3300>;
 	};
 };
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra6e2.overlay b/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra6e2.overlay
index 83209ee3b9e..f3269f1c970 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra6e2.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/fpb_ra6e2.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,8 +7,9 @@
 / {
 	zephyr,user {
 		io-channels = <&adc0 0>;
-		reference_mv = <3300>;
-		expected_accuracy = <32>;
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
 	};
 };
 
@@ -23,6 +24,5 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,vref-mv = <3300>;
 	};
 };
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/frdm_k64f.conf b/tests/drivers/adc/adc_accuracy_test/boards/frdm_k64f.conf
deleted file mode 100644
index 5ddebe8a96e..00000000000
--- a/tests/drivers/adc/adc_accuracy_test/boards/frdm_k64f.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_DAC=y
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/frdm_kl25z.overlay b/tests/drivers/adc/adc_accuracy_test/boards/frdm_kl25z.overlay
index 3be90387270..2a42c4e7d9a 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/frdm_kl25z.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/frdm_kl25z.overlay
@@ -7,8 +7,8 @@
 / {
 	zephyr,user {
 		io-channels = <&adc0 12>;
-		reference_mv = <1100>;
-		expected_accuracy = <32>;
+		reference-mv = <1100>;
+		expected-accuracy = <32>;
 	};
 };
 
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/frdm_mcxc242.overlay b/tests/drivers/adc/adc_accuracy_test/boards/frdm_mcxc242.overlay
index 1397a540c92..5b93ce10114 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/frdm_mcxc242.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/frdm_mcxc242.overlay
@@ -9,8 +9,8 @@
 / {
 	zephyr,user {
 		io-channels = <&adc0 1>;
-		reference_mv = <1650>;
-		expected_accuracy = <32>;
+		reference-mv = <1650>;
+		expected-accuracy = <32>;
 	};
 };
 
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/frdm_mcxc444.conf b/tests/drivers/adc/adc_accuracy_test/boards/frdm_mcxc444.conf
new file mode 100644
index 00000000000..3201f7a9cc4
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/boards/frdm_mcxc444.conf
@@ -0,0 +1 @@
+CONFIG_ADC_MCUX_ADC16_VREF_ALTERNATE=y
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/frdm_mcxc444.overlay b/tests/drivers/adc/adc_accuracy_test/boards/frdm_mcxc444.overlay
new file mode 100644
index 00000000000..69bc918b532
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/boards/frdm_mcxc444.overlay
@@ -0,0 +1,29 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright 2024 NXP
+ */
+
+ /* Please connect voltage reference to J4 pin 1 to run the test. */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 0>;
+		reference_mv = <1650>;
+		expected_accuracy = <32>;
+	};
+};
+
+&adc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_VDD_1";
+		zephyr,vref-mv = <3300>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/mck_ra8t1.overlay b/tests/drivers/adc/adc_accuracy_test/boards/mck_ra8t1.overlay
index 83209ee3b9e..f3269f1c970 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/mck_ra8t1.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/mck_ra8t1.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,8 +7,9 @@
 / {
 	zephyr,user {
 		io-channels = <&adc0 0>;
-		reference_mv = <3300>;
-		expected_accuracy = <32>;
+		dac = <&dac0>;
+		dac-channel-id = <0>;
+		dac-resolution = <12>;
 	};
 };
 
@@ -23,6 +24,5 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,vref-mv = <3300>;
 	};
 };
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/nrf52840dk_nrf52840.overlay b/tests/drivers/adc/adc_accuracy_test/boards/nrf52840dk_nrf52840.overlay
index 08aa282bc60..c42437571fe 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/nrf52840dk_nrf52840.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/nrf52840dk_nrf52840.overlay
@@ -8,8 +8,8 @@
 / {
 	zephyr,user {
 		io-channels = <&adc 0>;
-		reference_mv = <3000>;
-		expected_accuracy = <32>;
+		reference-mv = <3000>;
+		expected-accuracy = <32>;
 	};
 };
 
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/nrf54h20dk_nrf54h20_common.dtsi b/tests/drivers/adc/adc_accuracy_test/boards/nrf54h20dk_nrf54h20_common.dtsi
new file mode 100644
index 00000000000..ba60616bccd
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/boards/nrf54h20dk_nrf54h20_common.dtsi
@@ -0,0 +1,27 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>;
+		reference-mv = <1800>;
+		expected-accuracy = <64>;
+	};
+};
+
+&adc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1_2";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN4>;
+		zephyr,resolution = <14>;
+	};
+};
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/adc/adc_accuracy_test/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
index f6ee92720ca..658b19b0ae5 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
@@ -4,24 +4,4 @@
  * Copyright (c) 2024 Nordic Semiconductor ASA
  */
 
-/ {
-	zephyr,user {
-		io-channels = <&adc 0>;
-		reference_mv = <1800>;
-		expected_accuracy = <64>;
-	};
-};
-
-&adc {
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	channel@0 {
-		reg = <0>;
-		zephyr,gain = "ADC_GAIN_1_2";
-		zephyr,reference = "ADC_REF_INTERNAL";
-		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
-		zephyr,input-positive = <NRF_SAADC_AIN4>;
-		zephyr,resolution = <14>;
-	};
-};
+#include "nrf54h20dk_nrf54h20_common.dtsi"
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/nrf54h20dk_nrf54h20_cpuppr.overlay b/tests/drivers/adc/adc_accuracy_test/boards/nrf54h20dk_nrf54h20_cpuppr.overlay
new file mode 100644
index 00000000000..4599ed3f8a0
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/boards/nrf54h20dk_nrf54h20_cpuppr.overlay
@@ -0,0 +1,11 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ */
+
+#include "nrf54h20dk_nrf54h20_common.dtsi"
+
+&adc {
+	status = "okay";
+};
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/tests/drivers/adc/adc_accuracy_test/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
index 53facf3dc31..57e3e44075b 100644
--- a/tests/drivers/adc/adc_accuracy_test/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
+++ b/tests/drivers/adc/adc_accuracy_test/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
@@ -7,8 +7,8 @@
 / {
 	zephyr,user {
 		io-channels = <&adc 0>;
-		reference_mv = <1800>;
-		expected_accuracy = <64>;
+		reference-mv = <1800>;
+		expected-accuracy = <64>;
 	};
 };
 
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/adc/adc_accuracy_test/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..19f2b090d14
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,27 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>;
+		reference-mv = <1800>;
+		expected-accuracy = <64>;
+	};
+};
+
+&adc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1_2";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN2>;
+		zephyr,resolution = <14>;
+	};
+};
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/xg24_dk2601b.overlay b/tests/drivers/adc/adc_accuracy_test/boards/xg24_dk2601b.overlay
new file mode 100644
index 00000000000..dd3463aecde
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/boards/xg24_dk2601b.overlay
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "dt-bindings/adc/silabs-adc.h"
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 4>;
+		reference-mv = <(3300 / 4)>;
+		expected-accuracy = <32>;
+	};
+};
+
+&adc0{
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@4 {
+		reg = <4>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <IADC_INPUT_AVDD>;
+	};
+};
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/xg24_rb4187c.overlay b/tests/drivers/adc/adc_accuracy_test/boards/xg24_rb4187c.overlay
new file mode 100644
index 00000000000..ba5d7bd1d39
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/boards/xg24_rb4187c.overlay
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "dt-bindings/adc/silabs-adc.h"
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 4>;
+		reference-mv = <(3300 / 4)>;
+		expected-accuracy = <32>;
+	};
+};
+
+&adc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	channel@4 {
+		reg = <4>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <IADC_INPUT_AVDD>;
+	};
+};
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/xg27_dk2602a.overlay b/tests/drivers/adc/adc_accuracy_test/boards/xg27_dk2602a.overlay
new file mode 100644
index 00000000000..dd3463aecde
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/boards/xg27_dk2602a.overlay
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "dt-bindings/adc/silabs-adc.h"
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 4>;
+		reference-mv = <(3300 / 4)>;
+		expected-accuracy = <32>;
+	};
+};
+
+&adc0{
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@4 {
+		reg = <4>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <IADC_INPUT_AVDD>;
+	};
+};
diff --git a/tests/drivers/adc/adc_accuracy_test/boards/xg29_rb4412a.overlay b/tests/drivers/adc/adc_accuracy_test/boards/xg29_rb4412a.overlay
new file mode 100644
index 00000000000..0cde575193a
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/boards/xg29_rb4412a.overlay
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "dt-bindings/adc/silabs-adc.h"
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 4>;
+		reference-mv = <(3300 / 4)>;
+		expected-accuracy = <32>;
+	};
+};
+
+&adc0{
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@4 {
+		reg = <4>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <IADC_INPUT_AVDD>;
+	};
+};
diff --git a/tests/drivers/adc/adc_accuracy_test/src/dac_source.c b/tests/drivers/adc/adc_accuracy_test/src/dac_source.c
index 34a857fb011..23b832a66ed 100644
--- a/tests/drivers/adc/adc_accuracy_test/src/dac_source.c
+++ b/tests/drivers/adc/adc_accuracy_test/src/dac_source.c
@@ -18,7 +18,7 @@ extern const struct adc_dt_spec *get_adc_channel(void);
 static const struct dac_channel_cfg dac_ch_cfg = {
 	.channel_id = DT_PROP(DT_PATH(zephyr_user), dac_channel_id),
 	.resolution = DT_PROP(DT_PATH(zephyr_user), dac_resolution),
-	.buffered = true
+	.buffered = !IS_ENABLED(CONFIG_DAC_BUFFER_NOT_SUPPORTED),
 };
 
 static const struct device *init_dac(void)
diff --git a/tests/drivers/adc/adc_accuracy_test/sysbuild/vpr_launcher/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/adc/adc_accuracy_test/sysbuild/vpr_launcher/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
new file mode 100644
index 00000000000..d3ddd5ac093
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/sysbuild/vpr_launcher/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "../../../boards/nrf54h20dk_nrf54h20_common.dtsi"
+
+&adc {
+	status = "reserved";
+	interrupt-parent = <&cpuppr_clic>;
+};
diff --git a/tests/drivers/adc/adc_accuracy_test/sysbuild/vpr_launcher/prj.conf b/tests/drivers/adc/adc_accuracy_test/sysbuild/vpr_launcher/prj.conf
new file mode 100644
index 00000000000..b2a4ba59104
--- /dev/null
+++ b/tests/drivers/adc/adc_accuracy_test/sysbuild/vpr_launcher/prj.conf
@@ -0,0 +1 @@
+# nothing here
diff --git a/tests/drivers/adc/adc_accuracy_test/testcase.yaml b/tests/drivers/adc/adc_accuracy_test/testcase.yaml
index 8c79c499d75..51a4cd53e2a 100644
--- a/tests/drivers/adc/adc_accuracy_test/testcase.yaml
+++ b/tests/drivers/adc/adc_accuracy_test/testcase.yaml
@@ -19,9 +19,11 @@ tests:
       - frdm_kl25z
       - ek_ra8m1
       - frdm_mcxc242
+      - frdm_mcxc444
       - nrf52840dk/nrf52840
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54h20dk/nrf54h20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
       - ek_ra8d1
       - mck_ra8t1
       - ek_ra6e2
@@ -36,5 +38,9 @@ tests:
       - ek_ra4m2
       - ek_ra4m3
       - ek_ra4w1
+      - xg24_dk2601b
+      - xg24_rb4187c
+      - xg27_dk2602a
+      - xg29_rb4412a
     integration_platforms:
       - frdm_kl25z
diff --git a/tests/drivers/adc/adc_api/Kconfig b/tests/drivers/adc/adc_api/Kconfig
index 5807a1c155f..f4748c6d380 100644
--- a/tests/drivers/adc/adc_api/Kconfig
+++ b/tests/drivers/adc/adc_api/Kconfig
@@ -10,3 +10,6 @@ source "Kconfig.zephyr"
 config ADC_API_SAMPLE_INTERVAL_US
 	int "Interval between repeatead samples in us"
 	default 0
+
+config ADC_32_BITS_DATA
+	bool "ADC data is 32-bits long"
diff --git a/tests/drivers/adc/adc_api/boards/arduino_due.overlay b/tests/drivers/adc/adc_api/boards/arduino_due.overlay
new file mode 100644
index 00000000000..b14564e8940
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/arduino_due.overlay
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2024 Centro de Inovacao EDGE
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 0>, <&adc0 1>;
+	};
+};
+
+&adc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	pinctrl-0 = <&adc0_default>;
+	pinctrl-names = "default";
+
+	prescaler = <9>;
+	startup-time = <64>;
+	settling-time = <3>;
+	tracking-time = <2>;
+
+	/* External ADC(+) */
+	channel@6 { // Connector A1
+		reg = <6>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <6>;
+		zephyr,vref-mv = <3300>;
+	};
+	channel@7 { // Connector A0
+		reg = <7>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <7>;
+		zephyr,vref-mv = <3300>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/arduino_uno_r4.overlay b/tests/drivers/adc/adc_api/boards/arduino_uno_r4.overlay
new file mode 100644
index 00000000000..2b60a305553
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/arduino_uno_r4.overlay
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 0>, <&adc0 1>;
+	};
+};
+
+&adc0 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <5000>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <5000>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay b/tests/drivers/adc/adc_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay
new file mode 100644
index 00000000000..f04139378c6
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay
@@ -0,0 +1,44 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>, <&adc 1> , <&adc 2>;
+	};
+};
+
+&adc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
+		zephyr,input-positive = <NRF_SAADC_AIN1>;
+		zephyr,resolution = <10>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1_4";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN4>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_2_3";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
+		zephyr,input-positive = <NRF_SAADC_AIN2>;
+		zephyr,resolution = <10>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/adc/adc_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..f04139378c6
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,44 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>, <&adc 1> , <&adc 2>;
+	};
+};
+
+&adc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
+		zephyr,input-positive = <NRF_SAADC_AIN1>;
+		zephyr,resolution = <10>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1_4";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN4>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_2_3";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
+		zephyr,input-positive = <NRF_SAADC_AIN2>;
+		zephyr,resolution = <10>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/adc/adc_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..f04139378c6
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,44 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>, <&adc 1> , <&adc 2>;
+	};
+};
+
+&adc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
+		zephyr,input-positive = <NRF_SAADC_AIN1>;
+		zephyr,resolution = <10>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1_4";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN4>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_2_3";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
+		zephyr,input-positive = <NRF_SAADC_AIN2>;
+		zephyr,resolution = <10>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/cyw920829m2evk_02.overlay b/tests/drivers/adc/adc_api/boards/cyw920829m2evk_02.overlay
new file mode 100644
index 00000000000..2eb9d632286
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/cyw920829m2evk_02.overlay
@@ -0,0 +1,38 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon company) or
+ * an affiliate of Cypress Semiconductor Corporation
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 4>, <&adc0 5>;
+	};
+};
+
+&adc0 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@4 {
+		reg = <4>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 1)>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <16>;
+		zephyr,input-positive = <4>;   /* P3.4 */
+	};
+
+	channel@5 {
+		reg = <5>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 1)>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <16>;
+		zephyr,input-positive = <5>;   /* P3.5 */
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/ek_ra4l1.overlay b/tests/drivers/adc/adc_api/boards/ek_ra4l1.overlay
new file mode 100644
index 00000000000..cc25530b584
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/ek_ra4l1.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 1>, <&adc0 2>;
+	};
+};
+
+&adc0 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <3300>;
+	};
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <3300>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/ek_ra4m1.overlay b/tests/drivers/adc/adc_api/boards/ek_ra4m1.overlay
new file mode 100644
index 00000000000..9aab1db0db5
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/ek_ra4m1.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 0>, <&adc0 2>;
+	};
+};
+
+&adc0 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <3300>;
+	};
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <3300>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/fpb_ra4e1.overlay b/tests/drivers/adc/adc_api/boards/fpb_ra4e1.overlay
new file mode 100644
index 00000000000..9aab1db0db5
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/fpb_ra4e1.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 0>, <&adc0 2>;
+	};
+};
+
+&adc0 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <3300>;
+	};
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <3300>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/frdm_mcxa156.conf b/tests/drivers/adc/adc_api/boards/frdm_mcxa156.conf
deleted file mode 100644
index 6beae3f4655..00000000000
--- a/tests/drivers/adc/adc_api/boards/frdm_mcxa156.conf
+++ /dev/null
@@ -1 +0,0 @@
-CONFIG_LPADC_DO_OFFSET_CALIBRATION=y
diff --git a/tests/drivers/adc/adc_api/boards/frdm_mcxc444.conf b/tests/drivers/adc/adc_api/boards/frdm_mcxc444.conf
new file mode 100644
index 00000000000..3201f7a9cc4
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/frdm_mcxc444.conf
@@ -0,0 +1 @@
+CONFIG_ADC_MCUX_ADC16_VREF_ALTERNATE=y
diff --git a/tests/drivers/adc/adc_api/boards/frdm_mcxc444.overlay b/tests/drivers/adc/adc_api/boards/frdm_mcxc444.overlay
new file mode 100644
index 00000000000..ac768783a82
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/frdm_mcxc444.overlay
@@ -0,0 +1,34 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright 2024 NXP
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 0>, <&adc0 3>;
+	};
+};
+
+&adc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_VDD_1";
+		zephyr,vref-mv = <3300>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@3 {
+		reg = <3>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_VDD_1";
+		zephyr,vref-mv = <3300>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/frdm_mcxw72_mcxw727c_cpu0.overlay b/tests/drivers/adc/adc_api/boards/frdm_mcxw72_mcxw727c_cpu0.overlay
new file mode 100644
index 00000000000..5bda571575d
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/frdm_mcxw72_mcxw727c_cpu0.overlay
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 0>;
+	};
+};
+
+&adc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL1";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,vref-mv = <1800>;
+		/* channel 2 signal 6A */
+		zephyr,input-positive = <MCUX_LPADC_CH2A>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/max78000evkit_max78000_m4.overlay b/tests/drivers/adc/adc_api/boards/max78000evkit_max78000_m4.overlay
new file mode 100644
index 00000000000..fe2f78237fc
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/max78000evkit_max78000_m4.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&adc 0>, <&adc 1>;
+	};
+};
+
+&adc {
+	status = "okay";
+	pinctrl-0 = <&ain0_p2_0 &ain1_p2_1>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <10>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <10>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/max78000fthr_max78000_m4.overlay b/tests/drivers/adc/adc_api/boards/max78000fthr_max78000_m4.overlay
new file mode 100644
index 00000000000..a9297cde19d
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/max78000fthr_max78000_m4.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&adc 3>, <&adc 4>;
+	};
+};
+
+&adc {
+	status = "okay";
+	pinctrl-0 = <&ain3_p2_3 &ain4_p2_4>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@3 {
+		reg = <3>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <10>;
+	};
+
+	channel@4 {
+		reg = <4>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <10>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/tests/drivers/adc/adc_api/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..6d3d3848d4e
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+
+/ {
+	zephyr,user {
+		io-channels = <&lpadc0 0>, <&lpadc0 1>;
+	};
+};
+
+&lpadc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL1";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,vref-mv = <1800>;
+		zephyr,input-positive = <MCUX_LPADC_CH1A>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL1";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,vref-mv = <1800>;
+		zephyr,input-positive = <MCUX_LPADC_CH2A>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay b/tests/drivers/adc/adc_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay
new file mode 100644
index 00000000000..99d447efc68
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+
+/ {
+	zephyr,user {
+		io-channels = <&lpadc0 0>, <&lpadc0 1>;
+	};
+};
+
+&lpadc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL1";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <MCUX_LPADC_CH1A>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL1";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <MCUX_LPADC_CH2A>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/mcxw72_evk_mcxw727c_cpu0.overlay b/tests/drivers/adc/adc_api/boards/mcxw72_evk_mcxw727c_cpu0.overlay
new file mode 100644
index 00000000000..5bda571575d
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/mcxw72_evk_mcxw727c_cpu0.overlay
@@ -0,0 +1,29 @@
+/*
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 0>;
+	};
+};
+
+&adc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL1";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,vref-mv = <1800>;
+		/* channel 2 signal 6A */
+		zephyr,input-positive = <MCUX_LPADC_CH2A>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/tests/drivers/adc/adc_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
new file mode 100644
index 00000000000..88238712554
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
@@ -0,0 +1,34 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2023 Benjamin Björnsson <benjamin.bjornsson@gmail.com>
+ */
+
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+
+/ {
+	zephyr,user {
+		io-channels = <&adc1 0>, <&adc1 1>;
+	};
+};
+
+&adc1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/tests/drivers/adc/adc_api/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
similarity index 100%
rename from tests/drivers/adc/adc_api/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
rename to tests/drivers/adc/adc_api/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
diff --git a/tests/drivers/adc/adc_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/tests/drivers/adc/adc_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay
deleted file mode 100644
index d93c8c47c43..00000000000
--- a/tests/drivers/adc/adc_api/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * SPDX-License-Identifier: Apache-2.0
- *
- * Copyright (c) 2023 Benjamin Björnsson <benjamin.bjornsson@gmail.com>
- */
-
-#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
-
-/ {
-	zephyr,user {
-		io-channels = <&lpadc0 0>, <&lpadc0 1>;
-	};
-};
-
-&lpadc0 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	channel@0 {
-		reg = <0>;
-		zephyr,gain = "ADC_GAIN_1";
-		zephyr,reference = "ADC_REF_EXTERNAL0";
-		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
-		zephyr,resolution = <12>;
-		zephyr,input-positive = <MCUX_LPADC_CH0A>;
-	};
-
-	channel@1 {
-		reg = <1>;
-		zephyr,gain = "ADC_GAIN_1";
-		zephyr,reference = "ADC_REF_EXTERNAL0";
-		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
-		zephyr,resolution = <12>;
-		zephyr,input-positive = <MCUX_LPADC_CH1A>;
-	};
-};
diff --git a/tests/drivers/adc/adc_api/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay b/tests/drivers/adc/adc_api/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay
new file mode 100644
index 00000000000..34514a08b0f
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay
@@ -0,0 +1,36 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright 2025 NXP
+ */
+
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+
+/ {
+	zephyr,user {
+		io-channels = <&lpadc0 0>, <&lpadc0 1>;
+	};
+};
+
+&lpadc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <MCUX_LPADC_CH0A>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <MCUX_LPADC_CH1A>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay b/tests/drivers/adc/adc_api/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay
new file mode 100644
index 00000000000..34514a08b0f
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/mimxrt700_evk_mimxrt798s_cm33_cpu1.overlay
@@ -0,0 +1,36 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright 2025 NXP
+ */
+
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+
+/ {
+	zephyr,user {
+		io-channels = <&lpadc0 0>, <&lpadc0 1>;
+	};
+};
+
+&lpadc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <MCUX_LPADC_CH0A>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <MCUX_LPADC_CH1A>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/native_posix.overlay b/tests/drivers/adc/adc_api/boards/native_posix.overlay
deleted file mode 100644
index d4959cf991c..00000000000
--- a/tests/drivers/adc/adc_api/boards/native_posix.overlay
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright 2021 Google LLC
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
-	zephyr,user {
-		io-channels = <&adc0 0>, <&adc0 1>;
-	};
-};
-
-&adc0 {
-	ref-internal-mv = <3300>;
-	ref-external1-mv = <5000>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	channel@0 {
-		reg = <0>;
-		zephyr,gain = "ADC_GAIN_1";
-		zephyr,reference = "ADC_REF_INTERNAL";
-		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
-		zephyr,resolution = <10>;
-	};
-
-	channel@1 {
-		reg = <1>;
-		zephyr,gain = "ADC_GAIN_1";
-		zephyr,reference = "ADC_REF_INTERNAL";
-		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
-		zephyr,resolution = <10>;
-	};
-};
diff --git a/tests/drivers/adc/adc_api/boards/native_posix_64.overlay b/tests/drivers/adc/adc_api/boards/native_posix_64.overlay
deleted file mode 100644
index 6b622000bdf..00000000000
--- a/tests/drivers/adc/adc_api/boards/native_posix_64.overlay
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Copyright 2023 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "native_posix.overlay"
diff --git a/tests/drivers/adc/adc_api/boards/native_sim.overlay b/tests/drivers/adc/adc_api/boards/native_sim.overlay
index 6b622000bdf..d4959cf991c 100644
--- a/tests/drivers/adc/adc_api/boards/native_sim.overlay
+++ b/tests/drivers/adc/adc_api/boards/native_sim.overlay
@@ -1,7 +1,34 @@
 /*
- * Copyright 2023 Nordic Semiconductor ASA
+ * Copyright 2021 Google LLC
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "native_posix.overlay"
+/ {
+	zephyr,user {
+		io-channels = <&adc0 0>, <&adc0 1>;
+	};
+};
+
+&adc0 {
+	ref-internal-mv = <3300>;
+	ref-external1-mv = <5000>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <10>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <10>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/native_sim_64.overlay b/tests/drivers/adc/adc_api/boards/native_sim_64.overlay
index 6b622000bdf..44f044981eb 100644
--- a/tests/drivers/adc/adc_api/boards/native_sim_64.overlay
+++ b/tests/drivers/adc/adc_api/boards/native_sim_64.overlay
@@ -4,4 +4,4 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include "native_posix.overlay"
+#include "native_sim.overlay"
diff --git a/tests/drivers/adc/adc_api/boards/nrf54h20dk_nrf54h20_common.dtsi b/tests/drivers/adc/adc_api/boards/nrf54h20dk_nrf54h20_common.dtsi
new file mode 100644
index 00000000000..536366ec8d5
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/nrf54h20dk_nrf54h20_common.dtsi
@@ -0,0 +1,43 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>, <&adc 1>, <&adc 2>;
+	};
+};
+
+&adc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1_2";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
+		zephyr,input-positive = <NRF_SAADC_AIN1>;
+		zephyr,resolution = <10>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_2";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
+		zephyr,input-positive = <NRF_SAADC_AIN3>;
+		zephyr,resolution = <10>;
+	};
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_2_3";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
+		zephyr,input-positive = <NRF_SAADC_AIN2>;
+		zephyr,resolution = <10>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/adc/adc_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
index 536366ec8d5..32ff8fd841f 100644
--- a/tests/drivers/adc/adc_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
+++ b/tests/drivers/adc/adc_api/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
@@ -1,43 +1,7 @@
 /*
- * SPDX-License-Identifier: Apache-2.0
+ * Copyright (c) 2024 Nordic Semiconductor
  *
- * Copyright (c) 2024 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
  */
 
-/ {
-	zephyr,user {
-		io-channels = <&adc 0>, <&adc 1>, <&adc 2>;
-	};
-};
-
-&adc {
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	channel@0 {
-		reg = <0>;
-		zephyr,gain = "ADC_GAIN_1_2";
-		zephyr,reference = "ADC_REF_INTERNAL";
-		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
-		zephyr,input-positive = <NRF_SAADC_AIN1>;
-		zephyr,resolution = <10>;
-	};
-
-	channel@1 {
-		reg = <1>;
-		zephyr,gain = "ADC_GAIN_2";
-		zephyr,reference = "ADC_REF_EXTERNAL0";
-		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
-		zephyr,input-positive = <NRF_SAADC_AIN3>;
-		zephyr,resolution = <10>;
-	};
-
-	channel@2 {
-		reg = <2>;
-		zephyr,gain = "ADC_GAIN_2_3";
-		zephyr,reference = "ADC_REF_INTERNAL";
-		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
-		zephyr,input-positive = <NRF_SAADC_AIN2>;
-		zephyr,resolution = <10>;
-	};
-};
+#include "nrf54h20dk_nrf54h20_common.dtsi"
diff --git a/tests/drivers/adc/adc_api/boards/nrf54h20dk_nrf54h20_cpuppr.overlay b/tests/drivers/adc/adc_api/boards/nrf54h20dk_nrf54h20_cpuppr.overlay
new file mode 100644
index 00000000000..6e9d592b6c5
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/nrf54h20dk_nrf54h20_cpuppr.overlay
@@ -0,0 +1,9 @@
+/* Copyright (c) 2024 Nordic Semiconductor
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "nrf54h20dk_nrf54h20_common.dtsi"
+
+&adc {
+	status = "okay";
+};
diff --git a/tests/drivers/adc/adc_api/boards/nucleo_c071rb.overlay b/tests/drivers/adc/adc_api/boards/nucleo_c071rb.overlay
new file mode 100644
index 00000000000..0a2f7b3fd6a
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/nucleo_c071rb.overlay
@@ -0,0 +1,38 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 STMicroelectronics
+ */
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&adc1 0>, <&adc1 1>;
+	};
+};
+
+&adc1 {
+
+	dmas = <&dmamux1 0 5 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS |
+		STM32_DMA_PERIPH_16BITS)>;
+	dma-names = "dmamux";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_MAX>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_MAX>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/nucleo_f072rb.overlay b/tests/drivers/adc/adc_api/boards/nucleo_f072rb.overlay
new file mode 100644
index 00000000000..a3e5fe6027f
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/nucleo_f072rb.overlay
@@ -0,0 +1,25 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2023 STMicroelectronics
+ */
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&adc1 0>;
+	};
+};
+
+&adc1 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/nucleo_f439zi.overlay b/tests/drivers/adc/adc_api/boards/nucleo_f439zi.overlay
new file mode 100644
index 00000000000..ed807ca3ca6
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/nucleo_f439zi.overlay
@@ -0,0 +1,42 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) Benjamin Björnsson <benjamin.bjornsson@gmail.com>
+ */
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&adc1 0>, <&adc1 3>;
+	};
+};
+
+&adc1 {
+	dmas = <&dma2 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS |
+		STM32_DMA_PERIPH_16BITS) STM32_DMA_FIFO_FULL>;
+	dma-names = "dma";
+
+	pinctrl-0 = <&adc1_in0_pa0 &adc1_in3_pa3>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_MAX>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@3 {
+		reg = <3>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_MAX>;
+		zephyr,resolution = <12>;
+	};
+};
+
+&dma2 {
+	status = "okay";
+};
diff --git a/tests/drivers/adc/adc_api/boards/nucleo_n657x0_q_sb.conf b/tests/drivers/adc/adc_api/boards/nucleo_n657x0_q_sb.conf
new file mode 100644
index 00000000000..22b66784845
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/nucleo_n657x0_q_sb.conf
@@ -0,0 +1,3 @@
+# USERSPACE not functional on N6 yet
+CONFIG_TEST_USERSPACE=n
+CONFIG_ADC_32_BITS_DATA=y
diff --git a/tests/drivers/adc/adc_api/boards/nucleo_n657x0_q_sb.overlay b/tests/drivers/adc/adc_api/boards/nucleo_n657x0_q_sb.overlay
new file mode 100644
index 00000000000..a009c762744
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/nucleo_n657x0_q_sb.overlay
@@ -0,0 +1,40 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 STMicroelectronics
+ */
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&adc1 10>, <&adc1 11>;
+	};
+};
+
+&adc1 {
+	dmas = <&gpdma1 0 7 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_32BITS | STM32_DMA_PERIPH_32BITS)>;
+	dma-names = "gpdma";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@a {
+		reg = <10>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_MAX>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@b {
+		reg = <11>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_MAX>;
+		zephyr,resolution = <12>;
+	};
+};
+
+&gpdma1 {
+	status = "okay";
+};
diff --git a/tests/drivers/adc/adc_api/boards/nucleo_wb07cc.overlay b/tests/drivers/adc/adc_api/boards/nucleo_wb07cc.overlay
new file mode 100644
index 00000000000..6cda0bb8765
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/nucleo_wb07cc.overlay
@@ -0,0 +1,44 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 STMicroelectronics
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc1 4>, <&adc1 12>, <&adc1 13>;
+	};
+};
+
+&adc1 {
+	status = "okay";
+
+	pinctrl-0 = <&adc1_vinp0_pb3>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	vinp0: channel@4 {
+		reg = <4>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+
+	adc_vbat_ch: channel@c {
+		reg = <12>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_VDD_1";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+
+	adc_tempsensor_ch: channel@d {
+		reg = <13>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_VDD_1_3";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/nucleo_wba52cg.overlay b/tests/drivers/adc/adc_api/boards/nucleo_wba52cg.overlay
deleted file mode 100644
index e5dc2af539f..00000000000
--- a/tests/drivers/adc/adc_api/boards/nucleo_wba52cg.overlay
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * SPDX-License-Identifier: Apache-2.0
- *
- * Copyright (c) Benjamin Björnsson <benjamin.bjornsson@gmail.com>
- */
-
-/ {
-	zephyr,user {
-		/* adjust channel number according to pinmux in board.dts */
-		io-channels = <&adc4 7>, <&adc4 8>;
-	};
-};
-
-&adc4 {
-	dmas = <&gpdma1 0 0 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_16BITS | STM32_DMA_PERIPH_16BITS)>;
-	dma-names = "gpdma";
-
-	pinctrl-0 = <&adc4_in7_pa2 &adc4_in8_pa1>;
-	#address-cells = <1>;
-	#size-cells = <0>;
-
-	channel@7 {
-		reg = <7>;
-		zephyr,gain = "ADC_GAIN_1";
-		zephyr,reference = "ADC_REF_INTERNAL";
-		zephyr,acquisition-time = <ADC_ACQ_TIME_MAX>;
-		zephyr,resolution = <12>;
-	};
-
-	channel@8 {
-		reg = <8>;
-		zephyr,gain = "ADC_GAIN_1";
-		zephyr,reference = "ADC_REF_INTERNAL";
-		/* Use a different acquisition time for test purposes */
-		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_TICKS, 80)>;
-		zephyr,resolution = <12>;
-	};
-};
-
-&gpdma1 {
-	status = "okay";
-};
diff --git a/tests/drivers/adc/adc_api/boards/nucleo_wba65ri.overlay b/tests/drivers/adc/adc_api/boards/nucleo_wba65ri.overlay
new file mode 100644
index 00000000000..4a6e6546c48
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/nucleo_wba65ri.overlay
@@ -0,0 +1,34 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 STMicroelectronics
+ */
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&adc4 7>, <&adc4 8>;
+	};
+};
+
+&adc4 {
+	pinctrl-0 = <&adc4_in7_pa2 &adc4_in8_pa1>;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@7 {
+		reg = <7>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_MAX>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@8 {
+		reg = <8>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_MAX>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/adc/adc_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..ab90118d232
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,43 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>, <&adc 1> , <&adc 2>;
+	};
+};
+
+&adc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
+		zephyr,input-positive = <NRF_SAADC_AIN1>;
+		zephyr,resolution = <10>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1_4";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,input-positive = <NRF_SAADC_AIN4>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_2_3";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME(ADC_ACQ_TIME_MICROSECONDS, 10)>;
+		zephyr,input-positive = <NRF_SAADC_AIN2>;
+		zephyr,resolution = <10>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/pico2_spe_rp2350a_m33.overlay b/tests/drivers/adc/adc_api/boards/pico2_spe_rp2350a_m33.overlay
new file mode 100644
index 00000000000..0c45b6f6036
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/pico2_spe_rp2350a_m33.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 KWS Computersysteme Gmbh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Pico2-SPE is compatible with the Pico-SPE , so reuse. */
+#include "rpi_pico.overlay"
+
+&adc {
+	status = "okay";
+};
diff --git a/tests/drivers/adc/adc_api/boards/pico_plus2_rp2350b_m33.overlay b/tests/drivers/adc/adc_api/boards/pico_plus2_rp2350b_m33.overlay
new file mode 100644
index 00000000000..1de395543ef
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/pico_plus2_rp2350b_m33.overlay
@@ -0,0 +1,33 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 TOKITA Hiroshi
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>, <&adc 1>;
+	};
+};
+
+&adc {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/pico_spe.overlay b/tests/drivers/adc/adc_api/boards/pico_spe.overlay
new file mode 100644
index 00000000000..a2a8bc205dd
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/pico_spe.overlay
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2024 KWS Computersysteme Gmbh
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>, <&adc 1>;
+	};
+};
+
+&adc {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/rts5912_evb.overlay b/tests/drivers/adc/adc_api/boards/rts5912_evb.overlay
new file mode 100644
index 00000000000..6ac2c0ebd78
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/rts5912_evb.overlay
@@ -0,0 +1,34 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 Realtek Semiconductor Corporation, SIBG-SD7
+ *
+ */
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 0>, <&adc0 1>;
+	};
+};
+
+&adc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <0>;
+		zephyr,resolution = <10>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <0>;
+		zephyr,resolution = <10>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/tests/drivers/adc/adc_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
new file mode 100644
index 00000000000..1d80e7ce421
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+/ {
+	zephyr,user {
+		io-channels = <&adc 0>, <&adc 2>;
+	};
+};
+
+&adc {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <1800>;
+	};
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,resolution = <12>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,vref-mv = <1800>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/stm32n6570_dk_sb.conf b/tests/drivers/adc/adc_api/boards/stm32n6570_dk_sb.conf
new file mode 100644
index 00000000000..22b66784845
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/stm32n6570_dk_sb.conf
@@ -0,0 +1,3 @@
+# USERSPACE not functional on N6 yet
+CONFIG_TEST_USERSPACE=n
+CONFIG_ADC_32_BITS_DATA=y
diff --git a/tests/drivers/adc/adc_api/boards/stm32n6570_dk_sb.overlay b/tests/drivers/adc/adc_api/boards/stm32n6570_dk_sb.overlay
new file mode 100644
index 00000000000..a009c762744
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/stm32n6570_dk_sb.overlay
@@ -0,0 +1,40 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 STMicroelectronics
+ */
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&adc1 10>, <&adc1 11>;
+	};
+};
+
+&adc1 {
+	dmas = <&gpdma1 0 7 (STM32_DMA_PERIPH_RX | STM32_DMA_MEM_32BITS | STM32_DMA_PERIPH_32BITS)>;
+	dma-names = "gpdma";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@a {
+		reg = <10>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_MAX>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@b {
+		reg = <11>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_MAX>;
+		zephyr,resolution = <12>;
+	};
+};
+
+&gpdma1 {
+	status = "okay";
+};
diff --git a/tests/drivers/adc/adc_api/boards/w5500_evb_pico2_rp2350a_m33.overlay b/tests/drivers/adc/adc_api/boards/w5500_evb_pico2_rp2350a_m33.overlay
new file mode 100644
index 00000000000..fb0ecaac606
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/w5500_evb_pico2_rp2350a_m33.overlay
@@ -0,0 +1,12 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 TOKITA Hiroshi
+ */
+
+/* W5500 EVB Pico2 can work the same configuration as W5500 EVB Pico */
+#include "w5500_evb_pico.overlay"
+
+&adc {
+	status = "okay";
+};
diff --git a/tests/drivers/adc/adc_api/boards/wio_terminal.overlay b/tests/drivers/adc/adc_api/boards/wio_terminal.overlay
index 51dd371bc7f..d6541960c8c 100644
--- a/tests/drivers/adc/adc_api/boards/wio_terminal.overlay
+++ b/tests/drivers/adc/adc_api/boards/wio_terminal.overlay
@@ -13,6 +13,7 @@
 };
 
 &adc0 {
+	status = "okay";
 	#address-cells = <1>;
 	#size-cells = <0>;
 
diff --git a/tests/drivers/adc/adc_api/boards/xg24_dk2601b.overlay b/tests/drivers/adc/adc_api/boards/xg24_dk2601b.overlay
index baf8886de99..9f648dfeb97 100644
--- a/tests/drivers/adc/adc_api/boards/xg24_dk2601b.overlay
+++ b/tests/drivers/adc/adc_api/boards/xg24_dk2601b.overlay
@@ -4,6 +4,8 @@
  * Copyright (c) 2023 Antmicro <www.antmicro.com>
  */
 
+#include "dt-bindings/adc/silabs-adc.h"
+
 / {
 	zephyr,user {
 		io-channels = <&adc0 0>, <&adc0 1>;
@@ -20,7 +22,7 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,input-positive = <0x11>;
+		zephyr,input-positive = <IADC_INPUT_IOVDD>;
 	};
 
 	channel@1 {
@@ -29,6 +31,6 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,input-positive = <0x01>;
+		zephyr,input-positive = <IADC_INPUT_GND>;
 	};
 };
diff --git a/tests/drivers/adc/adc_api/boards/xg24_rb4187c.overlay b/tests/drivers/adc/adc_api/boards/xg24_rb4187c.overlay
new file mode 100644
index 00000000000..b164be5e20e
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/xg24_rb4187c.overlay
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "dt-bindings/adc/silabs-adc.h"
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 0>, <&adc0 1>;
+	};
+};
+
+&adc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <IADC_INPUT_IOVDD>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <IADC_INPUT_GND>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/boards/xg27_dk2602a.overlay b/tests/drivers/adc/adc_api/boards/xg27_dk2602a.overlay
index baf8886de99..9f648dfeb97 100644
--- a/tests/drivers/adc/adc_api/boards/xg27_dk2602a.overlay
+++ b/tests/drivers/adc/adc_api/boards/xg27_dk2602a.overlay
@@ -4,6 +4,8 @@
  * Copyright (c) 2023 Antmicro <www.antmicro.com>
  */
 
+#include "dt-bindings/adc/silabs-adc.h"
+
 / {
 	zephyr,user {
 		io-channels = <&adc0 0>, <&adc0 1>;
@@ -20,7 +22,7 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,input-positive = <0x11>;
+		zephyr,input-positive = <IADC_INPUT_IOVDD>;
 	};
 
 	channel@1 {
@@ -29,6 +31,6 @@
 		zephyr,reference = "ADC_REF_INTERNAL";
 		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
 		zephyr,resolution = <12>;
-		zephyr,input-positive = <0x01>;
+		zephyr,input-positive = <IADC_INPUT_GND>;
 	};
 };
diff --git a/tests/drivers/adc/adc_api/boards/xg29_rb4412a.overlay b/tests/drivers/adc/adc_api/boards/xg29_rb4412a.overlay
new file mode 100644
index 00000000000..76f95bb2ae8
--- /dev/null
+++ b/tests/drivers/adc/adc_api/boards/xg29_rb4412a.overlay
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "dt-bindings/adc/silabs-adc.h"
+
+/ {
+	zephyr,user {
+		io-channels = <&adc0 0>, <&adc0 1>;
+	};
+};
+
+&adc0 {
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <IADC_INPUT_IOVDD>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <IADC_INPUT_VBAT>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/socs/esp32c2.conf b/tests/drivers/adc/adc_api/socs/esp32c2.conf
new file mode 100644
index 00000000000..b6c5c80f924
--- /dev/null
+++ b/tests/drivers/adc/adc_api/socs/esp32c2.conf
@@ -0,0 +1 @@
+CONFIG_ADC_ASYNC=n
diff --git a/tests/drivers/adc/adc_api/socs/esp32c2.overlay b/tests/drivers/adc/adc_api/socs/esp32c2.overlay
new file mode 100644
index 00000000000..663ed8df999
--- /dev/null
+++ b/tests/drivers/adc/adc_api/socs/esp32c2.overlay
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&adc0 2>, <&adc0 3>;
+	};
+};
+
+&adc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_1_4";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@3 {
+		reg = <3>;
+		zephyr,gain = "ADC_GAIN_1_4";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/socs/esp32c3_usb.conf b/tests/drivers/adc/adc_api/socs/esp32c3_usb.conf
new file mode 100644
index 00000000000..b6c5c80f924
--- /dev/null
+++ b/tests/drivers/adc/adc_api/socs/esp32c3_usb.conf
@@ -0,0 +1 @@
+CONFIG_ADC_ASYNC=n
diff --git a/tests/drivers/adc/adc_api/socs/esp32c3_usb.overlay b/tests/drivers/adc/adc_api/socs/esp32c3_usb.overlay
new file mode 100644
index 00000000000..c288312aa3a
--- /dev/null
+++ b/tests/drivers/adc/adc_api/socs/esp32c3_usb.overlay
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2022 Wolter HV <wolterhv@gmx.de>
+ * Copyright (c) 2023 Benjamin Björnsson <benjamin.bjornsson@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&adc0 0>, <&adc0 1>;
+	};
+};
+
+&adc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@1 {
+		reg = <1>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/socs/esp32c6_hpcore.conf b/tests/drivers/adc/adc_api/socs/esp32c6_hpcore.conf
new file mode 100644
index 00000000000..b6c5c80f924
--- /dev/null
+++ b/tests/drivers/adc/adc_api/socs/esp32c6_hpcore.conf
@@ -0,0 +1 @@
+CONFIG_ADC_ASYNC=n
diff --git a/tests/drivers/adc/adc_api/socs/esp32c6_hpcore.overlay b/tests/drivers/adc/adc_api/socs/esp32c6_hpcore.overlay
new file mode 100644
index 00000000000..241cdc51a6f
--- /dev/null
+++ b/tests/drivers/adc/adc_api/socs/esp32c6_hpcore.overlay
@@ -0,0 +1,34 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
+ */
+
+/ {
+	zephyr,user {
+		/* adjust channel number according to pinmux in board.dts */
+		io-channels = <&adc0 2>, <&adc0 3>;
+	};
+};
+
+&adc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "okay";
+
+	channel@2 {
+		reg = <2>;
+		zephyr,gain = "ADC_GAIN_1_4";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+
+	channel@3 {
+		reg = <3>;
+		zephyr,gain = "ADC_GAIN_1_4";
+		zephyr,reference = "ADC_REF_INTERNAL";
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+	};
+};
diff --git a/tests/drivers/adc/adc_api/src/test_adc.c b/tests/drivers/adc/adc_api/src/test_adc.c
index e7d1958cd5a..49af36dc0d4 100644
--- a/tests/drivers/adc/adc_api/src/test_adc.c
+++ b/tests/drivers/adc/adc_api/src/test_adc.c
@@ -12,6 +12,13 @@
 #include <zephyr/kernel.h>
 #include <zephyr/ztest.h>
 
+#if CONFIG_ADC_32_BITS_DATA
+typedef int32_t adc_data_size_t;
+#define INVALID_ADC_VALUE INT_MIN
+#else
+typedef int16_t adc_data_size_t;
+#endif
+
 /* Invalid value that is not supposed to be written by the driver. It is used
  * to mark the sample buffer entries as empty. If needed, it can be overridden
  * for a particular board by providing a specific definition above.
@@ -28,9 +35,9 @@
 
 #define BUFFER_SIZE  6
 #ifdef CONFIG_TEST_USERSPACE
-static ZTEST_BMEM int16_t m_sample_buffer[BUFFER_SIZE];
+static ZTEST_BMEM adc_data_size_t m_sample_buffer[BUFFER_SIZE];
 #else
-static __aligned(32) int16_t m_sample_buffer[BUFFER_SIZE] __NOCACHE;
+static __aligned(32) adc_data_size_t m_sample_buffer[BUFFER_SIZE] __NOCACHE;
 #endif
 
 #define DT_SPEC_AND_COMMA(node_id, prop, idx) ADC_DT_SPEC_GET_BY_IDX(node_id, idx),
@@ -102,9 +109,13 @@ static void check_samples(int expected_count)
 
 	TC_PRINT("Samples read: ");
 	for (i = 0; i < BUFFER_SIZE; i++) {
-		int16_t sample_value = m_sample_buffer[i];
+		adc_data_size_t sample_value = m_sample_buffer[i];
 
+#if CONFIG_ADC_32_BITS_DATA
+		TC_PRINT("0x%08x ", sample_value);
+#else
 		TC_PRINT("0x%04hx ", sample_value);
+#endif
 		if (i < expected_count) {
 			zassert_not_equal(INVALID_ADC_VALUE, sample_value,
 				"[%u] should be filled", i);
diff --git a/tests/drivers/adc/adc_api/sysbuild/vpr_launcher/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/drivers/adc/adc_api/sysbuild/vpr_launcher/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
new file mode 100644
index 00000000000..d3ddd5ac093
--- /dev/null
+++ b/tests/drivers/adc/adc_api/sysbuild/vpr_launcher/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "../../../boards/nrf54h20dk_nrf54h20_common.dtsi"
+
+&adc {
+	status = "reserved";
+	interrupt-parent = <&cpuppr_clic>;
+};
diff --git a/tests/drivers/adc/adc_api/sysbuild/vpr_launcher/prj.conf b/tests/drivers/adc/adc_api/sysbuild/vpr_launcher/prj.conf
new file mode 100644
index 00000000000..b2a4ba59104
--- /dev/null
+++ b/tests/drivers/adc/adc_api/sysbuild/vpr_launcher/prj.conf
@@ -0,0 +1 @@
+# nothing here
diff --git a/tests/drivers/adc/adc_api/testcase.yaml b/tests/drivers/adc/adc_api/testcase.yaml
index d6b1e75ddcb..2ea70a864a1 100644
--- a/tests/drivers/adc/adc_api/testcase.yaml
+++ b/tests/drivers/adc/adc_api/testcase.yaml
@@ -9,6 +9,12 @@ tests:
     min_flash: 40
     platform_exclude:
       - nucleo_u031r8
+      - panb511evb/nrf54l15/cpuapp
+      - nrf54l15dk/nrf54l15/cpuapp/ns
+      - nrf54l15dk/nrf54l10/cpuapp/ns
+      - bl54l15_dvk/nrf54l10/cpuapp/ns
+      - bl54l15_dvk/nrf54l15/cpuapp/ns
+      - bl54l15u_dvk/nrf54l15/cpuapp/ns
   drivers.adc.b_u585i_iot02a_adc4:
     extra_args:
       - DTC_OVERLAY_FILE="boards/b_u585i_iot02a_adc4.overlay"
@@ -34,6 +40,7 @@ tests:
       - nucleo_f207zg
       - nucleo_f401re
       - nucleo_f429zi
+      - nucleo_f439zi
       - nucleo_f746zg
       - nucleo_g071rb
       - nucleo_g474re
@@ -44,7 +51,8 @@ tests:
       - nucleo_u083rc
       - nucleo_u575zi_q
       - nucleo_wb55rg
-      - nucleo_wba52cg
+      - nucleo_wba55cg
+      - nucleo_wba65ri
       - nucleo_wl55jc
       - stm32f3_disco
       - stm32h573i_dk
@@ -66,6 +74,7 @@ tests:
       - frdm_k82f
   drivers.adc.dma_espressif:
     extra_args:
+      - DTC_OVERLAY_FILE="boards/esp32s3_devkitc_procpu.overlay"
       - EXTRA_CONF_FILE="overlay-dma-esp32.conf"
     depends_on:
       - adc
diff --git a/tests/drivers/adc/adc_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/adc/adc_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..0db0ea867a2
--- /dev/null
+++ b/tests/drivers/adc/adc_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,12 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ */
+
+/ {
+	aliases {
+		adc = &adc;
+	};
+};
diff --git a/tests/drivers/adc/adc_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/adc/adc_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..0db0ea867a2
--- /dev/null
+++ b/tests/drivers/adc/adc_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,12 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ */
+
+/ {
+	aliases {
+		adc = &adc;
+	};
+};
diff --git a/tests/drivers/adc/adc_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/adc/adc_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..b44fc6070ac
--- /dev/null
+++ b/tests/drivers/adc/adc_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,11 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ */
+
+/ {
+	aliases {
+		adc = &adc;
+	};
+};
diff --git a/tests/drivers/adc/adc_error_cases/testcase.yaml b/tests/drivers/adc/adc_error_cases/testcase.yaml
index d1e0860a23d..e5c0225b28c 100644
--- a/tests/drivers/adc/adc_error_cases/testcase.yaml
+++ b/tests/drivers/adc/adc_error_cases/testcase.yaml
@@ -1,3 +1,8 @@
+common:
+  tags:
+    - adc
+    - drivers
+
 tests:
   drivers.adc_error_cases:
     depends_on: adc
@@ -6,3 +11,4 @@ tests:
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
       - nrf54h20dk/nrf54h20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
diff --git a/tests/drivers/audio/dmic_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/audio/dmic_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..9527bb9c78e
--- /dev/null
+++ b/tests/drivers/audio/dmic_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		dmic-dev = &pdm20;
+	};
+};
+
+&pinctrl {
+	pdm20_default_alt: pdm20_default_alt {
+		group1 {
+			psels = <NRF_PSEL(PDM_CLK, 1, 12)>,
+				<NRF_PSEL(PDM_DIN, 1, 13)>;
+		};
+	};
+};
+
+dmic_dev: &pdm20 {
+	status = "okay";
+	pinctrl-0 = <&pdm20_default_alt>;
+	pinctrl-names = "default";
+	clock-source = "PCLK32M";
+};
diff --git a/tests/drivers/audio/dmic_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/audio/dmic_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..9527bb9c78e
--- /dev/null
+++ b/tests/drivers/audio/dmic_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		dmic-dev = &pdm20;
+	};
+};
+
+&pinctrl {
+	pdm20_default_alt: pdm20_default_alt {
+		group1 {
+			psels = <NRF_PSEL(PDM_CLK, 1, 12)>,
+				<NRF_PSEL(PDM_DIN, 1, 13)>;
+		};
+	};
+};
+
+dmic_dev: &pdm20 {
+	status = "okay";
+	pinctrl-0 = <&pdm20_default_alt>;
+	pinctrl-names = "default";
+	clock-source = "PCLK32M";
+};
diff --git a/tests/drivers/audio/dmic_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/audio/dmic_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..182a089b3d5
--- /dev/null
+++ b/tests/drivers/audio/dmic_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		dmic-dev = &pdm20;
+	};
+};
+
+&pinctrl {
+	pdm20_default_alt: pdm20_default_alt {
+		group1 {
+			psels = <NRF_PSEL(PDM_CLK, 1, 12)>,
+				<NRF_PSEL(PDM_DIN, 1, 13)>;
+		};
+	};
+};
+
+dmic_dev: &pdm20 {
+	status = "okay";
+	pinctrl-0 = <&pdm20_default_alt>;
+	pinctrl-names = "default";
+	clock-source = "PCLK32M";
+};
diff --git a/tests/drivers/build_all/adc/boards/native_sim.overlay b/tests/drivers/build_all/adc/boards/native_sim.overlay
index 7c5f3145538..1c54bf4898f 100644
--- a/tests/drivers/build_all/adc/boards/native_sim.overlay
+++ b/tests/drivers/build_all/adc/boards/native_sim.overlay
@@ -371,6 +371,21 @@
 				#io-channel-cells = <1>;
 				drdy-gpios = <&test_gpio 0 0>;
 			};
+
+			test_spi_ad7124: ad7124@18 {
+				compatible = "adi,ad7124-adc";
+				reg = <0x18>;
+				spi-max-frequency = <0>;
+				#io-channel-cells = <1>;
+				active-device = <1>;
+			};
+
+			test_spi_ad4130: ad41304@19 {
+				compatible = "adi,ad4130-adc";
+				reg = <0x19>;
+				spi-max-frequency = <0>;
+				#io-channel-cells = <1>;
+			};
 		};
 	};
 };
diff --git a/tests/drivers/build_all/adc/testcase.yaml b/tests/drivers/build_all/adc/testcase.yaml
index c9fa5a8ec65..f73b054761b 100644
--- a/tests/drivers/build_all/adc/testcase.yaml
+++ b/tests/drivers/build_all/adc/testcase.yaml
@@ -33,10 +33,14 @@ tests:
     platform_allow: same54_xpro
   drivers.adc.sam.afec.build:
     platform_allow: sam_e70_xplained/same70q21
+  drivers.adc.silabs.build:
+    platform_allow: xg29_rb4412a
   drivers.adc.stm32.build:
     platform_allow: disco_l475_iot1
   drivers.adc.xec.build:
     platform_allow: mec15xxevb_assy6853
+  drivers.adc.realtek.rts5912.build:
+    platform_allow: rts5912_evb
   drivers.adc.test.build:
     platform_allow: qemu_cortex_m3
   drivers.adc.linker_generator.build:
diff --git a/tests/drivers/build_all/can/boards/native_posix.overlay b/tests/drivers/build_all/can/boards/native_posix.overlay
deleted file mode 100644
index 84e4247ccc8..00000000000
--- a/tests/drivers/build_all/can/boards/native_posix.overlay
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Copyright (c) 2023 Vestas Wind Systems A/S
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "native_sim.overlay"
diff --git a/tests/drivers/build_all/charger/i2c.dtsi b/tests/drivers/build_all/charger/i2c.dtsi
index 24616e928d1..c10271a17ed 100644
--- a/tests/drivers/build_all/charger/i2c.dtsi
+++ b/tests/drivers/build_all/charger/i2c.dtsi
@@ -46,3 +46,23 @@ sbs-charger@3 {
 	compatible = "sbs,sbs-charger";
 	reg = <0x3>;
 };
+
+bq257130@4 {
+	compatible = "ti,bq25713";
+	reg = <0x4>;
+	constant-charge-current-max-microamp = <1000000>;
+	constant-charge-voltage-max-microvolt = <3800000>;
+	system-voltage-min-threshold-microvolt = <3328000>;
+};
+
+axp2101@5 {
+	compatible = "x-powers,axp2101";
+	reg = <0x5>;
+
+	charger {
+		compatible = "x-powers,axp2101-charger";
+		constant-charge-current-max-microamp = <300000>;
+		constant-charge-voltage-max-microvolt = <4200000>;
+		charge-term-current-microamp = <100000>;
+	};
+};
diff --git a/tests/drivers/build_all/comparator/silabs_acmp/vsense_avdd.overlay b/tests/drivers/build_all/comparator/silabs_acmp/vsense_avdd.overlay
new file mode 100644
index 00000000000..2ab5dafffd1
--- /dev/null
+++ b/tests/drivers/build_all/comparator/silabs_acmp/vsense_avdd.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/comparator/silabs-acmp.h>
+
+&acmp0 {
+	status = "okay";
+
+	bias = <0>;
+	hysteresis-mode = "disabled";
+	accuracy-mode = "low";
+	input-range = "full";
+	input-positive = <ACMP_INPUT_VSENSE01DIV4>;
+	input-negative = <ACMP_INPUT_VREFDIVAVDD>;
+	vref-divider = <63>;
+};
diff --git a/tests/drivers/build_all/comparator/testcase.yaml b/tests/drivers/build_all/comparator/testcase.yaml
index ad0161d03e9..298dcc88410 100644
--- a/tests/drivers/build_all/comparator/testcase.yaml
+++ b/tests/drivers/build_all/comparator/testcase.yaml
@@ -4,6 +4,16 @@ common:
     - drivers
     - comparator
 tests:
+  drivers.build_all.comparator.silabs_acmp.vsense_avdd:
+    extra_args:
+      - DTC_OVERLAY_FILE="silabs_acmp/vsense_avdd.overlay"
+    platform_allow:
+      - xg23_rb4210a
+      - xg24_dk2601b
+      - xg24_ek2703a
+      - xg24_rb4187c
+      - xg27_dk2602a
+      - xg29_rb4412a
   drivers.build_all.comparator.nrf_comp.diff:
     extra_args:
       - DTC_OVERLAY_FILE="nrf_comp/diff.overlay"
@@ -17,6 +27,7 @@ tests:
       - nrf5340dk/nrf5340/cpuapp
       - nrf54h20dk/nrf54h20/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
       - nrf9280pdk/nrf9280/cpuapp
     integration_platforms:
       - nrf52dk/nrf52810
@@ -34,6 +45,7 @@ tests:
       - nrf5340dk/nrf5340/cpuapp
       - nrf54h20dk/nrf54h20/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
       - nrf9280pdk/nrf9280/cpuapp
     integration_platforms:
       - nrf52dk/nrf52810
@@ -51,6 +63,7 @@ tests:
       - nrf5340dk/nrf5340/cpuapp
       - nrf54h20dk/nrf54h20/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
       - nrf9280pdk/nrf9280/cpuapp
     integration_platforms:
       - nrf52dk/nrf52810
@@ -64,10 +77,12 @@ tests:
       - nrf5340dk/nrf5340/cpuapp
       - nrf54h20dk/nrf54h20/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
       - nrf9280pdk/nrf9280/cpuapp
     integration_platforms:
       - nrf51dk/nrf51822
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
   drivers.build_all.comparator.nrf_lpcomp.int_ref:
     extra_args:
       - DTC_OVERLAY_FILE="nrf_lpcomp/int_ref.overlay"
@@ -78,6 +93,7 @@ tests:
       - nrf54h20dk/nrf54h20/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf9280pdk/nrf9280/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf51dk/nrf51822
       - nrf54h20dk/nrf54h20/cpuapp
diff --git a/tests/drivers/build_all/dac/app.overlay b/tests/drivers/build_all/dac/app.overlay
index c3c9fec38ed..48148055ef2 100644
--- a/tests/drivers/build_all/dac/app.overlay
+++ b/tests/drivers/build_all/dac/app.overlay
@@ -65,8 +65,8 @@
 				compatible = "microchip,mcp4728";
 				reg = <0x61>;
 				#io-channel-cells = <1>;
-				voltage_reference = <0>;
-				power_down_mode = <0>;
+				voltage-reference = <0>;
+				power-down-mode = <0>;
 			};
 
 			test_i2c_dacx0501:dacx0501@62 {
@@ -124,6 +124,7 @@
 				   <&test_gpio 0 0>,
 				   <&test_gpio 0 0>,
 				   <&test_gpio 0 0>,
+				   <&test_gpio 0 0>,
 				   <&test_gpio 0 0>;
 
 			test_spi_dac60508: dac60508@0 {
@@ -288,6 +289,27 @@
 					#io-channel-cells = <1>;
 				};
 			};
+
+			test_spi_max22017_mfd: max22017_mfd@11 {
+				compatible = "adi,max22017";
+				status = "okay";
+				spi-max-frequency = <1000000>;
+				reg = <0x11>;
+
+				test_spi_max22017_dac0: dac-controller {
+					compatible = "adi,max22017-dac";
+					#io-channel-cells = <2>;
+					status = "okay";
+				};
+			};
+
+			test_spi_dac161s997: dac161s997@12 {
+				compatible = "ti,dac161s997";
+				reg = <0x12>;
+				spi-max-frequency = <0>;
+				#io-channel-cells = <1>;
+				errb-gpios = <&test_gpio 0 0>;
+			};
 		};
 	};
 };
diff --git a/tests/drivers/build_all/display/app.overlay b/tests/drivers/build_all/display/app.overlay
index e18a2103236..15f9389685c 100644
--- a/tests/drivers/build_all/display/app.overlay
+++ b/tests/drivers/build_all/display/app.overlay
@@ -168,7 +168,7 @@
 			spi-dev = <&test_spi>;
 			#address-cells = <1>;
 			#size-cells = <0>;
-			xfr-min-bits = <MIPI_DBI_SPI_XFR_16BIT>;
+			xfr-min-bits = "MIPI_DBI_SPI_XFR_16BIT";
 			write-only;
 
 			test_mipi_dbi_xfr_16bit_ili9342c: ili9342c@0 {
@@ -249,6 +249,32 @@
 				height = <1280>;
 				pixel-format = <0>;
 			};
+
+			test_st7701: st7701@5 {
+				compatible = "sitronix,st7701";
+				reg = <0x5>;
+				height = <800>;
+				width = <480>;
+				data-lanes = <2>;
+				pixel-format = <0>;
+				rotation = <0>;
+				pvgamctrl = [00 10 0E 02 03 0E 07 02 07 0A 12 27 37 00 0D 0E 10];
+				nvgamctrl = [00 10 0E 03 03 0F 06 02 08 0A 13 26 36 00 0D 0E 10];
+
+				display-timings {
+					compatible = "zephyr,panel-timing";
+					hsync-active = <1>;
+					vsync-active = <0>;
+					de-active = <0>;
+					pixelclk-active = <0>;
+					hback-porch = <40>;
+					hsync-len = <32>;
+					hfront-porch = <8>;
+					vback-porch = <6>;
+					vsync-len = <8>;
+					vfront-porch = <9>;
+				};
+			};
 		};
 
 		test_spi: spi@33334444 {
@@ -361,6 +387,15 @@
 				com-invdir;
 				prechargep = <0x22>;
 			};
+			test_st7567: st7567@2 {
+				compatible = "sitronix,st7567";
+				reg = <0x2>;
+				width = <128>;
+				height = <64>;
+				column-offset = <0>;
+				line-offset = <0>;
+				regulation-ratio = <7>;
+			};
 		};
 	};
 };
diff --git a/tests/drivers/build_all/eeprom/app.overlay b/tests/drivers/build_all/eeprom/app.overlay
index 97b39a66664..999a0e859d8 100644
--- a/tests/drivers/build_all/eeprom/app.overlay
+++ b/tests/drivers/build_all/eeprom/app.overlay
@@ -55,15 +55,15 @@
 				/* read-only; */
 			};
 
-			test_i2c_tmp116: tmp116@2 {
+			test_i2c_tmp11x: tmp11x@2 {
 				status = "okay";
-				compatible = "ti,tmp116";
+				compatible = "ti,tmp11x";
 				reg = <0x2>;
 				#address-cells = <1>;
 				#size-cells = <0>;
 
-				test_tmp116_eeprom: ti_tmp116_eeprom@0 {
-					compatible = "ti,tmp116-eeprom";
+				test_tmp11x_eeprom: ti_tmp11x_eeprom@0 {
+					compatible = "ti,tmp11x-eeprom";
 					reg = <0x0>;
 					read-only;
 				};
@@ -93,9 +93,9 @@
 				/* read-only; */
 			};
 
-			test_spi_mb85rsxx: mb85rsxx@0 {
+			test_spi_mb85rsxx: mb85rsxx@1 {
 				compatible = "fujitsu,mb85rsxx";
-				reg = <0x0>;
+				reg = <0x1>;
 				spi-max-frequency = <DT_FREQ_M(25)>;
 				size = <DT_SIZE_K(128)>;
 			};
diff --git a/tests/drivers/build_all/eeprom/boards/xg23_rb4210a.conf b/tests/drivers/build_all/eeprom/boards/xg23_rb4210a.conf
new file mode 100644
index 00000000000..454a366688a
--- /dev/null
+++ b/tests/drivers/build_all/eeprom/boards/xg23_rb4210a.conf
@@ -0,0 +1,2 @@
+# Needs to be before CONFIG_SENSOR_INIT_PRIORITY
+CONFIG_REGULATOR_FIXED_INIT_PRIORITY=55
diff --git a/tests/drivers/build_all/eeprom/testcase.yaml b/tests/drivers/build_all/eeprom/testcase.yaml
index 89c085959ad..2df0e996734 100644
--- a/tests/drivers/build_all/eeprom/testcase.yaml
+++ b/tests/drivers/build_all/eeprom/testcase.yaml
@@ -6,6 +6,7 @@ common:
 tests:
   drivers.eeprom.build:
     min_ram: 32
+    min_flash: 128
     platform_exclude: serpente
     depends_on:
       - gpio
@@ -13,7 +14,8 @@ tests:
       - spi
 
   drivers.eeprom.emul.build:
-    min_ram: 32
+    min_ram: 64
+    min_flash: 128
     platform_exclude: serpente
     depends_on:
       - gpio
diff --git a/tests/drivers/build_all/ethernet/app.overlay b/tests/drivers/build_all/ethernet/app.overlay
index e74cb985a0f..c766cb184bf 100644
--- a/tests/drivers/build_all/ethernet/app.overlay
+++ b/tests/drivers/build_all/ethernet/app.overlay
@@ -79,6 +79,23 @@
 					compatible = "adi,adin2111-phy";
 					status = "okay";
 				};
+				ethernet-phy@7 {
+					reg = <0x7>;
+					compatible = "davicom,dm8806-phy";
+					status = "okay";
+					reg-switch = <8>;
+					reset-gpios = <&test_gpio 0 0>;
+					int-gpios = <&test_gpio 0 0>;
+					davicom,interface-type = "rmii";
+				};
+
+				ethernet-phy@8 {
+					reg = <0x8>;
+					compatible = "ti,dp83867";
+					status = "okay";
+					reset-gpios = <&test_gpio 0 0>;
+					int-gpios = <&test_gpio 0 0>;
+				};
 			};
 		};
 	};
diff --git a/tests/drivers/build_all/ethernet/spi_devices.overlay b/tests/drivers/build_all/ethernet/spi_devices.overlay
index 612e73bf53e..568b0bd759e 100644
--- a/tests/drivers/build_all/ethernet/spi_devices.overlay
+++ b/tests/drivers/build_all/ethernet/spi_devices.overlay
@@ -129,14 +129,24 @@
 				spi-max-frequency = <0>;
 				int-gpios = <&test_gpio 0 0>;
 				rst-gpios = <&test_gpio 0 0>;
-
-				plca-node-id = <0>;
-				plca-node-count = <1>;
-				plca-burst-count = <1>;
-				plca-burst-timer = <1>;
-				plca-to-timer = <1>;
-
 				local-mac-address = [00 00 00 01 02 03];
+				lan865x_mdio: lan865x_mdio {
+					compatible = "microchip,lan865x-mdio";
+					status = "okay";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					ethernet-phy@0 {
+						compatible = "microchip,t1s-phy";
+						reg = <0x0>;
+						plca-enable;
+						plca-node-id = <0>;
+						plca-node-count = <8>;
+						plca-burst-count = <0>;
+						plca-burst-timer = <0x80>;
+						plca-to-timer = <0x20>;
+						status = "okay";
+					};
+				};
 			};
 
 			test_spi_lan9250: lan9250@6 {
diff --git a/tests/drivers/build_all/gpio/adc_ads1145s0x_gpio.overlay b/tests/drivers/build_all/gpio/adc_ads1145s0x_gpio.overlay
deleted file mode 100644
index d93e6b1e233..00000000000
--- a/tests/drivers/build_all/gpio/adc_ads1145s0x_gpio.overlay
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2024 TOKITA Hiroshi
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
-	test {
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		test_gpio: gpio@deadbeef {
-			compatible = "vnd,gpio";
-			gpio-controller;
-			reg = <0xdeadbeef 0x1000>;
-			#gpio-cells = <0x2>;
-			status = "okay";
-		};
-
-		test_spi: spi@33334444 {
-			#address-cells = <1>;
-			#size-cells = <0>;
-			compatible = "vnd,spi";
-			reg = <0x33334444 0x1000>;
-			status = "okay";
-			clock-frequency = <2000000>;
-
-			cs-gpios = <&test_gpio 0 0>;
-
-			test_spi_ads114s08: ads114s08@0 {
-				compatible = "ti,ads114s08";
-				status = "okay";
-				spi-max-frequency = <10000000>;
-				reg = <0x00>;
-				#address-cells = <1>;
-				#size-cells = <0>;
-				#io-channel-cells = <1>;
-				reset-gpios = <&test_gpio 0 0>;
-				drdy-gpios = <&test_gpio 0 0>;
-				start-sync-gpios = <&test_gpio 0 0>;
-
-				test_spi_ads114s08_gpio: ads114s0x_gpio {
-					compatible = "ti,ads114s0x-gpio";
-					gpio-controller;
-					ngpios = <4>;
-					#gpio-cells = <2>;
-				};
-			};
-		};
-	};
-};
diff --git a/tests/drivers/build_all/gpio/adc_ads1x4s0x_gpio.overlay b/tests/drivers/build_all/gpio/adc_ads1x4s0x_gpio.overlay
new file mode 100644
index 00000000000..9d1f353542e
--- /dev/null
+++ b/tests/drivers/build_all/gpio/adc_ads1x4s0x_gpio.overlay
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2024 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	test {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		test_gpio: gpio@deadbeef {
+			compatible = "vnd,gpio";
+			gpio-controller;
+			reg = <0xdeadbeef 0x1000>;
+			#gpio-cells = <0x2>;
+			status = "okay";
+		};
+
+		test_spi: spi@33334444 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "vnd,spi";
+			reg = <0x33334444 0x1000>;
+			status = "okay";
+			clock-frequency = <2000000>;
+
+			cs-gpios = <&test_gpio 0 0>;
+
+			test_spi_ads114s08: ads114s08@0 {
+				compatible = "ti,ads114s08";
+				status = "okay";
+				spi-max-frequency = <10000000>;
+				reg = <0x00>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#io-channel-cells = <1>;
+				reset-gpios = <&test_gpio 0 0>;
+				drdy-gpios = <&test_gpio 0 0>;
+				start-sync-gpios = <&test_gpio 0 0>;
+
+				test_spi_ads114s08_gpio: ads1x4s0x_gpio {
+					compatible = "ti,ads1x4s0x-gpio";
+					gpio-controller;
+					ngpios = <4>;
+					#gpio-cells = <2>;
+				};
+			};
+
+			test_spi_ads124s08: ads124s08@0 {
+				compatible = "ti,ads124s08";
+				status = "okay";
+				spi-max-frequency = <10000000>;
+				reg = <0x00>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#io-channel-cells = <1>;
+				reset-gpios = <&test_gpio 0 0>;
+				drdy-gpios = <&test_gpio 0 0>;
+				start-sync-gpios = <&test_gpio 0 0>;
+
+				test_spi_ads124s08_gpio: ads1x4s0x_gpio {
+					compatible = "ti,ads1x4s0x-gpio";
+					gpio-controller;
+					ngpios = <4>;
+					#gpio-cells = <2>;
+				};
+			};
+
+			test_spi_ads114s06: ads114s06@0 {
+				compatible = "ti,ads114s06";
+				status = "okay";
+				spi-max-frequency = <10000000>;
+				reg = <0x00>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#io-channel-cells = <1>;
+				reset-gpios = <&test_gpio 0 0>;
+				drdy-gpios = <&test_gpio 0 0>;
+				start-sync-gpios = <&test_gpio 0 0>;
+
+				test_spi_ads114s06_gpio: ads1x4s0x_gpio {
+					compatible = "ti,ads1x4s0x-gpio";
+					gpio-controller;
+					ngpios = <4>;
+					#gpio-cells = <2>;
+				};
+			};
+
+			test_spi_ads124s06: ads124s06@0 {
+				compatible = "ti,ads124s06";
+				status = "okay";
+				spi-max-frequency = <10000000>;
+				reg = <0x00>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#io-channel-cells = <1>;
+				reset-gpios = <&test_gpio 0 0>;
+				drdy-gpios = <&test_gpio 0 0>;
+				start-sync-gpios = <&test_gpio 0 0>;
+
+				test_spi_ads124s06_gpio: ads1x4s0x_gpio {
+					compatible = "ti,ads1x4s0x-gpio";
+					gpio-controller;
+					ngpios = <4>;
+					#gpio-cells = <2>;
+				};
+			};
+		};
+	};
+};
diff --git a/tests/drivers/build_all/gpio/app.overlay b/tests/drivers/build_all/gpio/app.overlay
index b91babee910..ccb794dd847 100644
--- a/tests/drivers/build_all/gpio/app.overlay
+++ b/tests/drivers/build_all/gpio/app.overlay
@@ -172,8 +172,8 @@
 						gpio-controller;
 						#gpio-cells = <2>;
 						ngpios = <8>;
-						pin_mask = <0xff>;
-						pinmux_mask = <0xf7>;
+						pin-mask = <0xff>;
+						pinmux-mask = <0xf7>;
 					};
 
 					gpio@1 {
@@ -182,7 +182,7 @@
 						gpio-controller;
 						#gpio-cells = <2>;
 						ngpios = <8>;
-						pin_mask = <0xff>;
+						pin-mask = <0xff>;
 					};
 				};
 			};
@@ -201,8 +201,8 @@
 						gpio-controller;
 						#gpio-cells = <2>;
 						ngpios = <8>;
-						pin_mask = <0xdc>;
-						pinmux_mask = <0xff>;
+						pin-mask = <0xdc>;
+						pinmux-mask = <0xff>;
 					};
 				};
 			};
@@ -221,8 +221,8 @@
 						gpio-controller;
 						#gpio-cells = <2>;
 						ngpios = <8>;
-						pin_mask = <0xdc>;
-						pinmux_mask = <0xff>;
+						pin-mask = <0xdc>;
+						pinmux-mask = <0xff>;
 					};
 				};
 			};
@@ -440,6 +440,7 @@
 				    &test_gpio 0 0
 				    &test_gpio 0 0
 				    &test_gpio 0 0
+				    &test_gpio 0 0
 				    &test_gpio 0 0>;
 
 			test_spi_mcp23s17: mcp23s17@0 {
@@ -594,6 +595,70 @@
 				fault-gpios = <&test_gpio 0 0>;
 				latch-gpios = <&test_gpio 0 0>;
 			};
+
+			test_spi_max22199: max22199@b {
+				compatible = "adi,max22199-gpio";
+				status = "okay";
+				reg = <0x0b>;
+				spi-max-frequency = <0>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				max22190-mode = <1>;
+				filter-fbps = <0 0 0 0  0 0 0 0>;
+				filter-delays = <50 100 400 800 1600 3200 12800 20000>;
+				drdy-gpios = <&test_gpio 0 0>;
+				fault-gpios = <&test_gpio 0 0>;
+				latch-gpios = <&test_gpio 0 0>;
+			};
+
+			test_spi_max22017: max22017_mfd@c {
+				compatible = "adi,max22017";
+				status = "okay";
+				reg = <0x0c>;
+				spi-max-frequency = <0>;
+
+				max22017_gpio0: max22017_gpio {
+					compatible = "adi,max22017-gpio";
+					status = "okay";
+					gpio-controller;
+					ngpios = <5>;
+					#gpio-cells = <2>;
+				};
+			};
+
+			test_max14915: max14915@d {
+				compatible = "adi,max14915-gpio";
+				status = "okay";
+				reg = <0x0d>;
+				spi-max-frequency = <0>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				crc-en;
+				spi-addr = <0>;
+				drdy-gpios = <&test_gpio 0 0>;
+				fault-gpios = <&test_gpio 0 0>;
+				sync-gpios = <&test_gpio 0 0>;
+				en-gpios = <&test_gpio 0 0>;
+			};
+
+			test_spi_max14917: max14917@d {
+				compatible = "adi,max14917-gpio";
+				status = "okay";
+				reg = <0x0d>;
+				spi-max-frequency = <0>;
+				gpio-controller;
+				#gpio-cells = <2>;
+				ngpios = <8>;
+				vddok-gpios = <&test_gpio 0 0>;
+				ready-gpios = <&test_gpio 0 0>;
+				comerr-gpios = <&test_gpio 0 0>;
+				fault-gpios = <&test_gpio 0 0>;
+				en-gpios = <&test_gpio 0 0>;
+				sync-gpios = <&test_gpio 0 0>;
+				crcen-gpios = <&test_gpio 0 0>;
+			};
 		};
 	};
 };
diff --git a/tests/drivers/build_all/gpio/testcase.yaml b/tests/drivers/build_all/gpio/testcase.yaml
index 99f9fead947..080940d4427 100644
--- a/tests/drivers/build_all/gpio/testcase.yaml
+++ b/tests/drivers/build_all/gpio/testcase.yaml
@@ -26,7 +26,7 @@ tests:
     depends_on: gpio
     extra_args: DTC_OVERLAY_FILE="altera.overlay"
 
-  drivers.gpio.build.adc_ads1145s0x_gpio:
+  drivers.gpio.build.adc_ads1x4s0x_gpio:
     min_ram: 32
     platform_allow:
       - m5stack_core2/esp32/procpu
@@ -40,11 +40,11 @@ tests:
       - adc
       - spi
     extra_args:
-      - DTC_OVERLAY_FILE="adc_ads1145s0x_gpio.overlay"
+      - DTC_OVERLAY_FILE="adc_ads1x4s0x_gpio.overlay"
     extra_configs:
       - CONFIG_ADC=y
       - CONFIG_ADC_INIT_PRIORITY=80
-      - CONFIG_ADC_ADS114S0X_GPIO=y
+      - CONFIG_ADC_ADS1X4S0X_GPIO=y
 
   drivers.gpio.build.adc_lmp90xxx_gpio:
     min_ram: 32
diff --git a/tests/drivers/build_all/i3c/boards/qemu_cortex_m3.overlay b/tests/drivers/build_all/i3c/boards/qemu_cortex_m3.overlay
index 43c6d81d403..f3508335ec5 100644
--- a/tests/drivers/build_all/i3c/boards/qemu_cortex_m3.overlay
+++ b/tests/drivers/build_all/i3c/boards/qemu_cortex_m3.overlay
@@ -5,6 +5,12 @@
  */
 
 / {
+	test_fixed_clk: test-fixed-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <200000000>;
+		#clock-cells = <0>;
+	};
+
 	i3c0: i3c@88888888 {
 		compatible = "cdns,i3c";
 		#address-cells = <3>;
@@ -16,4 +22,16 @@
 		i3c-scl-hz = <12500000>;
 		i2c-scl-hz = <400000>;
 	};
+
+	i3c1: i3c@cccccccc {
+		compatible = "snps,designware-i3c";
+		#address-cells = <3>;
+		#size-cells = <0>;
+		reg = <0xcccccccc 0x400>;
+		interrupt-parent = <&nvic>;
+		interrupts = <8 1>;
+		clocks = <&test_fixed_clk>;
+		i3c-scl-hz = <12500000>;
+		i2c-scl-hz = <400000>;
+	};
 };
diff --git a/tests/drivers/build_all/i3c/prj.conf b/tests/drivers/build_all/i3c/prj.conf
index cf064b0a058..07d3ab3637a 100644
--- a/tests/drivers/build_all/i3c/prj.conf
+++ b/tests/drivers/build_all/i3c/prj.conf
@@ -3,4 +3,5 @@ CONFIG_TEST_USERSPACE=y
 CONFIG_I3C=y
 CONFIG_SHELL=y
 CONFIG_I3C_SHELL=y
-CONFIG_I3C_RTIO=y
+CONFIG_CLOCK_CONTROL=y
+CONFIG_CLOCK_CONTROL_FIXED_RATE_CLOCK=y
diff --git a/tests/drivers/build_all/i3c/testcase.yaml b/tests/drivers/build_all/i3c/testcase.yaml
index 4c4ed78c840..7885e2cd461 100644
--- a/tests/drivers/build_all/i3c/testcase.yaml
+++ b/tests/drivers/build_all/i3c/testcase.yaml
@@ -4,8 +4,18 @@ common:
     - drivers
     - i3c
 tests:
-  drivers.i3c.build:
+  drivers.i3c.build.dual_role:
     # will cover drivers without in-tree boards
     platform_allow: qemu_cortex_m3
-    tags: i3c_cdns
-    extra_args: "CONFIG_I3C=y"
+    tags: i3c_cdns i3c_dw
+    extra_args: "CONFIG_I3C_DUAL_ROLE=y CONFIG_I3C_RTIO=y"
+  drivers.i3c.build.controller_role_only:
+    # will cover drivers without in-tree boards
+    platform_allow: qemu_cortex_m3
+    tags: i3c_cdns i3c_dw
+    extra_args: "CONFIG_I3C_CONTROLLER_ROLE_ONLY=y CONFIG_I3C_RTIO=y"
+  drivers.i3c.build.target_role_only:
+    # will cover drivers without in-tree boards
+    platform_allow: qemu_cortex_m3
+    tags: i3c_cdns i3c_dw
+    extra_args: "CONFIG_I3C_TARGET_ROLE_ONLY=y"
diff --git a/tests/drivers/build_all/input/app.overlay b/tests/drivers/build_all/input/app.overlay
index 7a4501b339e..ac5a8731799 100644
--- a/tests/drivers/build_all/input/app.overlay
+++ b/tests/drivers/build_all/input/app.overlay
@@ -273,6 +273,16 @@
 				reg = <0xa>;
 				compatible= "nintendo,nunchuk";
 			};
+
+			cy8cmbr3xxx@b {
+				compatible = "cypress,cy8cmbr3xxx";
+				status= "okay";
+				reg = <0xb>;
+				int-gpios = <&test_gpio 0 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+				rst-gpios = <&test_gpio 1 (GPIO_PULL_UP | GPIO_ACTIVE_LOW)>;
+				input-codes = <0 1 2 3 4 5 6 7>;
+				proximity-codes = <8>;
+			};
 		};
 
 		spi@2 {
diff --git a/tests/drivers/build_all/input/it82xx2_evb.overlay b/tests/drivers/build_all/input/it82xx2_evb.overlay
index f7e4329b310..7dee5a7df23 100644
--- a/tests/drivers/build_all/input/it82xx2_evb.overlay
+++ b/tests/drivers/build_all/input/it82xx2_evb.overlay
@@ -25,8 +25,4 @@
 	kso-mapping = <0 1 20 3 4 5 6 17 18 16 15 11 12>;
 	row-size = <8>;
 	col-size = <13>;
-
-	kscan_input: kscan-input {
-		compatible = "zephyr,kscan-input";
-	};
 };
diff --git a/tests/drivers/build_all/input/testcase.yaml b/tests/drivers/build_all/input/testcase.yaml
index 4f4e3d79690..ea64f324fbb 100644
--- a/tests/drivers/build_all/input/testcase.yaml
+++ b/tests/drivers/build_all/input/testcase.yaml
@@ -4,7 +4,6 @@ common:
     - input
   build_only: true
   platform_allow:
-    - native_posix
     - native_sim
 tests:
   drivers.input.default: {}
diff --git a/tests/drivers/build_all/led/app.overlay b/tests/drivers/build_all/led/app.overlay
index abc6fd6a5f1..bfb31a7827c 100644
--- a/tests/drivers/build_all/led/app.overlay
+++ b/tests/drivers/build_all/led/app.overlay
@@ -124,6 +124,30 @@
 				compatible = "issi,is31fl3733";
 				reg = <0x10>;
 			};
+
+			axp192@11 {
+				compatible = "x-powers,axp192";
+				reg = <0x11>;
+				status = "okay";
+
+				pwr_led {
+					compatible = "x-powers,axp192-led";
+					status = "okay";
+					x-powers,mode = "by-reg";
+				};
+			};
+
+			axp2101@12 {
+				compatible = "x-powers,axp2101";
+				reg = <0x12>;
+				status = "okay";
+
+				pwr_led {
+					compatible = "x-powers,axp2101-led";
+					status = "okay";
+					x-powers,mode = "by-reg";
+				};
+			};
 		};
 	};
 };
diff --git a/tests/drivers/build_all/mfd/app.overlay b/tests/drivers/build_all/mfd/app.overlay
index 5f4ae6e8a8e..92e4cd79c00 100644
--- a/tests/drivers/build_all/mfd/app.overlay
+++ b/tests/drivers/build_all/mfd/app.overlay
@@ -40,5 +40,37 @@
 				};
 			};
 		};
+
+		test_gpio: gpio@deadbeef {
+			compatible = "vnd,gpio";
+			gpio-controller;
+			reg = <0xdeadbeef 0x1000>;
+			#gpio-cells = <0x2>;
+			status = "okay";
+		};
+
+		test_spi: spi@33334444 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			compatible = "vnd,spi";
+			reg = <0x33334444 0x1000>;
+			status = "okay";
+			clock-frequency = <2000000>;
+
+			/* one entry for every spi devices */
+			cs-gpios = <&test_gpio 0 0>;
+
+			test_spi_maxq10xx@0 {
+				compatible = "adi,maxq10xx";
+				reg = <0x0>;
+				status = "okay";
+				spi-max-frequency = <0>;
+
+				test_spi_maxq10xx_trng: trng {
+					compatible = "adi,maxq10xx-trng";
+					status = "okay";
+				};
+			};
+		};
 	};
 };
diff --git a/tests/drivers/build_all/mfd/prj.conf b/tests/drivers/build_all/mfd/prj.conf
index 3862bfcbf6d..78155e5638e 100644
--- a/tests/drivers/build_all/mfd/prj.conf
+++ b/tests/drivers/build_all/mfd/prj.conf
@@ -2,5 +2,8 @@ CONFIG_TEST=y
 CONFIG_GPIO=y
 CONFIG_TEST_USERSPACE=y
 CONFIG_I2C=y
+CONFIG_SPI=y
+CONFIG_MFD=y
+CONFIG_ENTROPY_GENERATOR=y
 CONFIG_SERIAL=y
 CONFIG_UART_USE_RUNTIME_CONFIGURE=y
diff --git a/tests/drivers/build_all/regulator/i2c.dtsi b/tests/drivers/build_all/regulator/i2c.dtsi
index 489476e69ca..ea81c2c3886 100644
--- a/tests/drivers/build_all/regulator/i2c.dtsi
+++ b/tests/drivers/build_all/regulator/i2c.dtsi
@@ -76,6 +76,30 @@ axp192@4 {
 	};
 };
 
+axp2101@7 {
+	compatible = "x-powers,axp2101";
+	reg = <0x7>;
+
+	regulators {
+		compatible = "x-powers,axp2101-regulator";
+
+		DCDC1 {};
+		DCDC2 {};
+		DCDC3 {};
+		DCDC4 {};
+		DCDC5 {};
+		ALDO1 {};
+		ALDO2 {};
+		ALDO3 {};
+		ALDO4 {};
+		BLDO1 {};
+		BLDO2 {};
+		CPUSLDO {};
+		DLDO1 {};
+		DLDO2 {};
+	};
+};
+
 max20335@5 {
 	compatible = "maxim,max20335";
 	reg = <0x5>;
diff --git a/tests/drivers/build_all/rtc/i2c_devices.overlay b/tests/drivers/build_all/rtc/i2c_devices.overlay
index ceb4b576c0a..1c2758f9f8f 100644
--- a/tests/drivers/build_all/rtc/i2c_devices.overlay
+++ b/tests/drivers/build_all/rtc/i2c_devices.overlay
@@ -69,6 +69,35 @@
 				status = "okay";
 				reg = <0x5>;
 			};
+
+			test_rv8803: rv8803@6 {
+				compatible = "microcrystal,rv8803";
+				status = "okay";
+				reg = <0x6>;
+				int-gpios = <&test_gpio 0 0>;
+				clkout-frequency = <1024>;
+			};
+
+			test_bq32002: bq32002@7 {
+				compatible = "ti,bq32002";
+				status = "okay";
+				reg = <0x7>;
+				irq-frequency = <512>;
+			};
+			test_rx8130ce: rx8130ce-rtc@8 {
+				compatible = "epson,rx8130ce-rtc";
+				status = "okay";
+				reg = <0x8>;
+				irq-gpios = <&test_gpio 0 0>;
+			};
+
+			test_ds1337: ds1337@9 {
+				compatible = "maxim,ds1337";
+				status = "okay";
+				reg = <0x9>;
+				int-gpios = <&test_gpio 0 0>;
+				sqw-frequency = <4096>;
+			};
 		};
 	};
 };
diff --git a/tests/drivers/build_all/sensor/app.overlay b/tests/drivers/build_all/sensor/app.overlay
index d4e195a8c81..5e5b3ef382b 100644
--- a/tests/drivers/build_all/sensor/app.overlay
+++ b/tests/drivers/build_all/sensor/app.overlay
@@ -147,8 +147,11 @@
 				   <&test_gpio 0 0>,
 				   <&test_gpio 0 0>,
 				   <&test_gpio 0 0>,
-				   <&test_gpio 0 0>;	/* 0x30 */
-
+				   <&test_gpio 0 0>,	/* 0x30 */
+				   <&test_gpio 0 0>,
+				   <&test_gpio 0 0>,
+				   <&test_gpio 0 0>,
+				   <&test_gpio 0 0>;	/* 0x34 */
 			#include "spi.dtsi"
 		};
 
diff --git a/tests/drivers/build_all/sensor/i2c.dtsi b/tests/drivers/build_all/sensor/i2c.dtsi
index 8a3c23883f1..978d022859b 100644
--- a/tests/drivers/build_all/sensor/i2c.dtsi
+++ b/tests/drivers/build_all/sensor/i2c.dtsi
@@ -24,7 +24,8 @@
 #include <zephyr/dt-bindings/sensor/stts22h.h>
 #include <zephyr/dt-bindings/sensor/ina226.h>
 #include <zephyr/dt-bindings/sensor/apds9253.h>
-#include <zephyr/dt-bindings/sensor/tmp116.h>
+#include <zephyr/dt-bindings/sensor/tmp11x.h>
+#include <zephyr/dt-bindings/sensor/tmp114.h>
 
 /****************************************
  * PLEASE KEEP REG ADDRESSES SEQUENTIAL *
@@ -177,9 +178,10 @@ test_i2c_ms5607: ms5607@17 {
 	reg = <0x17>;
 };
 
-test_i2c_ms5837: ms5837@18 {
-	compatible = "meas,ms5837";
+test_i2c_ms5837_02ba: ms5837@18 {
+	compatible = "meas,ms5837-02ba";
 	reg = <0x18>;
+	status = "okay";
 };
 
 test_i2c_jc42: jc42@19 {
@@ -476,10 +478,11 @@ test_i2c_tmp112: tmp112@46 {
 	reg = <0x46>;
 };
 
-test_i2c_tmp116: tmp116@47 {
-	compatible = "ti,tmp116";
+test_i2c_tmp11x: tmp11x@47 {
+	compatible = "ti,tmp11x";
 	reg = <0x47>;
-	odr = <TMP116_DT_ODR_125_MS>;
+	odr = <TMP11X_DT_ODR_125_MS>;
+	oversampling = <TMP11X_DT_OVERSAMPLING_32>;
 };
 
 test_i2c_bq274xx: bq27xx@48 {
@@ -628,11 +631,10 @@ test_i2c_max31875: max31875@5b {
 	reg = <0x5b>;
 };
 
-test_i2c_icp10125: icp10125@5c {
-	compatible = "invensense,icp10125";
+test_i2c_icp101xx: icp101xx@5c {
+	compatible = "invensense,icp101xx";
 	reg = <0x5c>;
-	temperature-measurement-mode = "normal";
-	pressure-measurement-mode = "normal";
+	mode = "normal";
 };
 
 test_i2c_as5600: as5600@5d {
@@ -650,6 +652,13 @@ test_i2c_akm09918c: akm09918c@5f {
 	reg = <0x5f>;
 };
 
+test_i2c_wsen_tids_2521020222501: wsen_tids_2521020222501@60 {
+	compatible = "we,wsen-tids-2521020222501";
+	reg = <0x60>;
+	interrupt-gpios = <&test_gpio 0 0>;
+	odr = <25>;
+};
+
 test_i2c_vl53l1x: vl53l1x@61 {
 	compatible = "st,vl53l1x";
 	reg = <0x61>;
@@ -671,12 +680,25 @@ test_i2c_tmd2620: tmd2620@62 {
 	wait-time-factor = <0>;
 };
 
+test_i2c_wsen_pads_2511020213301: wsen_pads_2511020213301@63 {
+	compatible = "we,wsen-pads-2511020213301";
+	reg = <0x63>;
+	interrupt-gpios = <&test_gpio 0 0>;
+	odr = <10>;
+};
+
 test_i2c_s11059: s11059@64 {
 	compatible = "hamamatsu,s11059";
 	reg = <0x64>;
 	integration-time = <546000>;
 };
 
+test_i2c_wsen_pdus_25131308XXXXX: wsen_pdus_25131308XXXXX@65 {
+	compatible = "we,wsen-pdus-25131308XXXXX";
+	reg = <0x65>;
+	sensor-type = < 4 >;
+};
+
 test_i2c_veml7700: veml7700@66 {
 	compatible = "vishay,veml7700";
 	reg = <0x66>;
@@ -800,7 +822,7 @@ test_i2c_mc3419: mc3419@75 {
 };
 
 test_i2c_ltrf216a0: ltrf216a@76 {
-	compatible = "ltr,f216a";
+	compatible = "liteon,ltrf216a";
 	reg = <0x76>;
 };
 
@@ -1009,6 +1031,7 @@ test_i2c_nct75: test_i2c_nct75@8c {
 test_i2c_tmp114: tmp114@8d {
 	compatible = "ti,tmp114";
 	reg = <0x8d>;
+	odr = <TMP114_DT_ODR_250_MS>;
 };
 
 test_i2c_ina226: ina226@8e {
@@ -1149,6 +1172,12 @@ test_i2c_npm2100: npm2100@9f {
 	};
 };
 
+test_i2c_mlx90394: mlx90394@a0 {
+	compatible = "melexis,mlx90394";
+	status = "okay";
+	reg = <0xa0>;
+};
+
 test_i2c_scd40: scd40@a1 {
 	compatible = "sensirion,scd40";
 	reg = <0xa1>;
@@ -1236,3 +1265,34 @@ test_i2c_bmm350: bmm350@ac {
 	reg = <0xac>;
 	drdy-gpios = <&test_gpio 0 0>;
 };
+
+test_i2c_ltr329: ltr329@ad {
+	compatible = "liteon,ltr329";
+	reg = <0xad>;
+};
+
+test_i2c_ms5837_30ba: ms5837@ae {
+	compatible = "meas,ms5837-30ba";
+	reg = <0xae>;
+	status = "okay";
+};
+
+test_i2c_icp201xx: icp201xx@af {
+	compatible = "invensense,icp201xx";
+	reg = <0xaf>;
+	int-gpios = <&test_gpio 0 0>;
+	op-mode = "mode0";
+	drive-strength = "current_12mA_1_8V";
+};
+
+test_i2c_paj7620: paj7620@b0 {
+	compatible = "pixart,paj7620";
+	reg = <0xb0>;
+	int-gpios = <&test_gpio 0 0>;
+};
+
+test_i2c_icm45686: icm45686@b1 {
+	compatible = "invensense,icm45686";
+	reg = <0xb1>;
+	int-gpios = <&test_gpio 0 0>;
+};
diff --git a/tests/drivers/build_all/sensor/i3c.dtsi b/tests/drivers/build_all/sensor/i3c.dtsi
index 3b3a89d8cca..8f1dc12ce45 100644
--- a/tests/drivers/build_all/sensor/i3c.dtsi
+++ b/tests/drivers/build_all/sensor/i3c.dtsi
@@ -48,3 +48,22 @@ test_i3c_lsm6dsv16x: lsm6dsv16x@500000803E0000004 {
 	gyro-range = <LSM6DSV16X_DT_FS_2000DPS>;
 	gyro-odr = <LSM6DSV16X_DT_ODR_AT_60Hz>;
 };
+
+test_i3c_lsm6dsv32x: lsm6dsv32x@600000803E0000004 {
+	compatible = "st,lsm6dsv32x";
+	reg = <0x6 0x00000803 0xE0000004>;
+	assigned-address = <0x6>;
+	int1-gpios = <&test_gpio 0 0>;
+	int2-gpios = <&test_gpio 0 0>;
+	accel-range = <LSM6DSV32X_DT_FS_8G>;
+	accel-odr = <LSM6DSV16X_DT_ODR_AT_60Hz>;
+	gyro-range = <LSM6DSV16X_DT_FS_2000DPS>;
+	gyro-odr = <LSM6DSV16X_DT_ODR_AT_60Hz>;
+};
+
+test_i3c_icm45686: icm45686@700000803E0000004 {
+	compatible = "invensense,icm45686";
+	reg = <0x7 0x00000803 0xE0000004>;
+	assigned-address = <0x7>;
+	int-gpios = <&test_gpio 0 0>;
+};
diff --git a/tests/drivers/build_all/sensor/prj.conf b/tests/drivers/build_all/sensor/prj.conf
index 3283fba0a01..b1f8af3cf9e 100644
--- a/tests/drivers/build_all/sensor/prj.conf
+++ b/tests/drivers/build_all/sensor/prj.conf
@@ -1,21 +1,23 @@
-CONFIG_TEST=y
-CONFIG_TEST_USERSPACE=y
-CONFIG_LOG=y
-CONFIG_SENSOR_LOG_LEVEL_DBG=y
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
+# zephyr-keep-sorted-start
 CONFIG_ADC=y
 CONFIG_DAC=y
+CONFIG_DHT20_CRC=y
+CONFIG_EMUL=y
+CONFIG_FUEL_GAUGE=y
 CONFIG_GPIO=y
 CONFIG_I2C=y
 CONFIG_I3C=y
+CONFIG_ICM42605_TRIGGER_NONE=y
+CONFIG_LOG=y
+CONFIG_MFD=y
 CONFIG_PWM=y
 CONFIG_PWM_CAPTURE=y
+CONFIG_SENSOR=y
+CONFIG_SENSOR_LOG_LEVEL_DBG=y
 CONFIG_SERIAL=y
 CONFIG_SPI=y
-CONFIG_MFD=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
+CONFIG_TEST=y
+CONFIG_TEST_USERSPACE=y
 CONFIG_W1=y
-CONFIG_SENSOR=y
-CONFIG_FUEL_GAUGE=y
-CONFIG_ICM42605_TRIGGER_NONE=y
-CONFIG_EMUL=y
-CONFIG_DHT20_CRC=y
+# zephyr-keep-sorted-stop
diff --git a/tests/drivers/build_all/sensor/sensors_die_temp.conf b/tests/drivers/build_all/sensor/sensors_die_temp.conf
index e2e79399043..426a32a17a7 100644
--- a/tests/drivers/build_all/sensor/sensors_die_temp.conf
+++ b/tests/drivers/build_all/sensor/sensors_die_temp.conf
@@ -1,10 +1,12 @@
-CONFIG_ISM330DHCX_ENABLE_TEMP=y
+# zephyr-keep-sorted-start
 CONFIG_IIS2ICLX_ENABLE_TEMP=y
-CONFIG_LSM6DS0_ENABLE_TEMP=y
-CONFIG_LSM6DSV16X_ENABLE_TEMP=y
-CONFIG_LSM6DSO_ENABLE_TEMP=y
+CONFIG_ISM330DHCX_ENABLE_TEMP=y
 CONFIG_LIS2DE12_ENABLE_TEMP=y
 CONFIG_LIS2DS12_ENABLE_TEMP=y
 CONFIG_LIS2DUX12_ENABLE_TEMP=y
-CONFIG_LSM6DSO16IS_ENABLE_TEMP=y
+CONFIG_LSM6DS0_ENABLE_TEMP=y
 CONFIG_LSM6DSL_ENABLE_TEMP=y
+CONFIG_LSM6DSO16IS_ENABLE_TEMP=y
+CONFIG_LSM6DSO_ENABLE_TEMP=y
+CONFIG_LSM6DSV16X_ENABLE_TEMP=y
+# zephyr-keep-sorted-stop
diff --git a/tests/drivers/build_all/sensor/sensors_no_default.conf b/tests/drivers/build_all/sensor/sensors_no_default.conf
index 185e2b2fda1..c866c8c0bd2 100644
--- a/tests/drivers/build_all/sensor/sensors_no_default.conf
+++ b/tests/drivers/build_all/sensor/sensors_no_default.conf
@@ -1,3 +1,4 @@
+# zephyr-keep-sorted-start
 CONFIG_BMC150_MAGN_TRIGGER=y
 CONFIG_BMC150_MAGN_TRIGGER_DRDY=y
 CONFIG_BMM150_TRIGGER_DIRECT=y
@@ -9,3 +10,4 @@ CONFIG_LSM9DS0_GYRO_TRIGGER_DRDY=y
 CONFIG_TMAG5170_TRIGGER_DIRECT=y
 CONFIG_VL53L1X_INTERRUPT_MODE=n
 CONFIG_VL53L1X_XSHUT=n
+# zephyr-keep-sorted-stop
diff --git a/tests/drivers/build_all/sensor/sensors_shub.conf b/tests/drivers/build_all/sensor/sensors_shub.conf
index f06a4fcaa47..df5e48184a2 100644
--- a/tests/drivers/build_all/sensor/sensors_shub.conf
+++ b/tests/drivers/build_all/sensor/sensors_shub.conf
@@ -1,28 +1,25 @@
-CONFIG_IIS2ICLX_SENSORHUB=y
+# zephyr-keep-sorted-start
+CONFIG_IIS2ICLX_EXT_HTS221=y
 CONFIG_IIS2ICLX_EXT_LIS2MDL=y
 CONFIG_IIS2ICLX_EXT_LPS22HB=y
-CONFIG_IIS2ICLX_EXT_HTS221=y
-
-CONFIG_ISM330DHCX_SENSORHUB=y
+CONFIG_IIS2ICLX_SENSORHUB=y
+CONFIG_ISM330DHCX_EXT_HTS221=y
 CONFIG_ISM330DHCX_EXT_LIS2MDL=y
 CONFIG_ISM330DHCX_EXT_LPS22HB=y
-CONFIG_ISM330DHCX_EXT_HTS221=y
-
-CONFIG_LSM6DSL_SENSORHUB=y
+CONFIG_ISM330DHCX_SENSORHUB=y
 CONFIG_LSM6DSL_EXT0_LIS2MDL=y
 CONFIG_LSM6DSL_EXT0_LPS22HB=y
-
-CONFIG_LSM6DSO_SENSORHUB=y
-CONFIG_LSM6DSO_EXT_LIS2MDL=y
-CONFIG_LSM6DSO_EXT_LPS22HB=y
-CONFIG_LSM6DSO_EXT_HTS221=y
-
-CONFIG_LSM6DSO16IS_SENSORHUB=y
+CONFIG_LSM6DSL_SENSORHUB=y
+CONFIG_LSM6DSO16IS_EXT_HTS221=y
 CONFIG_LSM6DSO16IS_EXT_LIS2MDL=y
 CONFIG_LSM6DSO16IS_EXT_LPS22HB=y
-CONFIG_LSM6DSO16IS_EXT_HTS221=y
-
-CONFIG_LSM6DSV16X_SENSORHUB=y
+CONFIG_LSM6DSO16IS_SENSORHUB=y
+CONFIG_LSM6DSO_EXT_HTS221=y
+CONFIG_LSM6DSO_EXT_LIS2MDL=y
+CONFIG_LSM6DSO_EXT_LPS22HB=y
+CONFIG_LSM6DSO_SENSORHUB=y
+CONFIG_LSM6DSV16X_EXT_HTS221=y
 CONFIG_LSM6DSV16X_EXT_LIS2MDL=y
 CONFIG_LSM6DSV16X_EXT_LPS22HB=y
-CONFIG_LSM6DSV16X_EXT_HTS221=y
+CONFIG_LSM6DSV16X_SENSORHUB=y
+# zephyr-keep-sorted-stop
diff --git a/tests/drivers/build_all/sensor/sensors_trigger_global.conf b/tests/drivers/build_all/sensor/sensors_trigger_global.conf
index d7d4572f0f4..8feaf9bf476 100644
--- a/tests/drivers/build_all/sensor/sensors_trigger_global.conf
+++ b/tests/drivers/build_all/sensor/sensors_trigger_global.conf
@@ -1,3 +1,4 @@
+# zephyr-keep-sorted-start
 CONFIG_ADT7310_TRIGGER_GLOBAL_THREAD=y
 CONFIG_ADT7420_TRIGGER_GLOBAL_THREAD=y
 CONFIG_ADXL362_TRIGGER_GLOBAL_THREAD=y
@@ -18,14 +19,16 @@ CONFIG_CCS811_TRIGGER_GLOBAL_THREAD=y
 CONFIG_ENS160_TRIGGER_GLOBAL_THREAD=y
 CONFIG_FDC2X1X_TRIGGER_GLOBAL_THREAD=y
 CONFIG_FXAS21002_TRIGGER_GLOBAL_THREAD=y
-CONFIG_FXOS8700_TRIGGER_GLOBAL_THREAD=y
 CONFIG_FXLS8974_TRIGGER_GLOBAL_THREAD=y
+CONFIG_FXOS8700_TRIGGER_GLOBAL_THREAD=y
 CONFIG_GROW_R502A_TRIGGER_GLOBAL_THREAD=y
 CONFIG_HMC5883L_TRIGGER_GLOBAL_THREAD=y
 CONFIG_HTS221_TRIGGER_GLOBAL_THREAD=y
 CONFIG_ICM42605_TRIGGER_GLOBAL_THREAD=y
-CONFIG_ICM42670_TRIGGER_GLOBAL_THREAD=y
 CONFIG_ICM42688_TRIGGER_GLOBAL_THREAD=y
+CONFIG_ICM42X70_TRIGGER_GLOBAL_THREAD=y
+CONFIG_ICM45686_TRIGGER_GLOBAL_THREAD=y
+CONFIG_ICP201XX_TRIGGER_GLOBAL_THREAD=y
 CONFIG_IIS2DH_TRIGGER_GLOBAL_THREAD=y
 CONFIG_IIS2DLPC_TRIGGER_GLOBAL_THREAD=y
 CONFIG_IIS2ICLX_TRIGGER_GLOBAL_THREAD=y
@@ -35,8 +38,8 @@ CONFIG_IIS3DHHC_TRIGGER_GLOBAL_THREAD=y
 CONFIG_ISL29035_TRIGGER_GLOBAL_THREAD=y
 CONFIG_ISM330DHCX_TRIGGER_GLOBAL_THREAD=y
 CONFIG_JC42_TRIGGER_GLOBAL_THREAD=y
-CONFIG_LIS2DH_TRIGGER_GLOBAL_THREAD=y
 CONFIG_LIS2DE12_TRIGGER_GLOBAL_THREAD=y
+CONFIG_LIS2DH_TRIGGER_GLOBAL_THREAD=y
 CONFIG_LIS2DS12_TRIGGER_GLOBAL_THREAD=y
 CONFIG_LIS2DU12_TRIGGER_GLOBAL_THREAD=y
 CONFIG_LIS2DUX12_TRIGGER_GLOBAL_THREAD=y
@@ -44,14 +47,15 @@ CONFIG_LIS2DW12_TRIGGER_GLOBAL_THREAD=y
 CONFIG_LIS2MDL_TRIGGER_GLOBAL_THREAD=y
 CONFIG_LIS3MDL_TRIGGER_GLOBAL_THREAD=y
 CONFIG_LM75_TRIGGER_GLOBAL_THREAD=y
-CONFIG_LPS2XDF_TRIGGER_GLOBAL_THREAD=y
 CONFIG_LPS22HH_TRIGGER_GLOBAL_THREAD=y
+CONFIG_LPS2XDF_TRIGGER_GLOBAL_THREAD=y
 CONFIG_LSM6DSL_TRIGGER_GLOBAL_THREAD=y
-CONFIG_LSM6DSO_TRIGGER_GLOBAL_THREAD=y
 CONFIG_LSM6DSO16IS_TRIGGER_GLOBAL_THREAD=y
+CONFIG_LSM6DSO_TRIGGER_GLOBAL_THREAD=y
 CONFIG_LSM6DSV16X_TRIGGER_GLOBAL_THREAD=y
 CONFIG_MPU6050_TRIGGER_GLOBAL_THREAD=y
 CONFIG_MPU9250_TRIGGER_GLOBAL_THREAD=y
+CONFIG_OPT3001_TRIGGER_GLOBAL_THREAD=y
 CONFIG_SHT3XD_TRIGGER_GLOBAL_THREAD=y
 CONFIG_SM351LT_TRIGGER_GLOBAL_THREAD=y
 CONFIG_STTS22H_TRIGGER_GLOBAL_THREAD=y
@@ -65,3 +69,6 @@ CONFIG_TSL2540_TRIGGER_GLOBAL_THREAD=y
 CONFIG_TSL2591_TRIGGER_GLOBAL_THREAD=y
 CONFIG_VCNL36825T_TRIGGER_GLOBAL_THREAD=y
 CONFIG_VCNL4040_TRIGGER_GLOBAL_THREAD=y
+CONFIG_WSEN_PADS_2511020213301_TRIGGER_GLOBAL_THREAD=y
+CONFIG_WSEN_TIDS_2521020222501_TRIGGER_GLOBAL_THREAD=y
+# zephyr-keep-sorted-stop
diff --git a/tests/drivers/build_all/sensor/sensors_trigger_none.conf b/tests/drivers/build_all/sensor/sensors_trigger_none.conf
index 855d058a892..8f83e40be61 100644
--- a/tests/drivers/build_all/sensor/sensors_trigger_none.conf
+++ b/tests/drivers/build_all/sensor/sensors_trigger_none.conf
@@ -1,3 +1,4 @@
+# zephyr-keep-sorted-start
 CONFIG_ADT7310_TRIGGER_NONE=y
 CONFIG_ADT7420_TRIGGER_NONE=y
 CONFIG_ADXL362_TRIGGER_NONE=y
@@ -19,14 +20,16 @@ CONFIG_CCS811_TRIGGER_NONE=y
 CONFIG_ENS160_TRIGGER_NONE=y
 CONFIG_FDC2X1X_TRIGGER_NONE=y
 CONFIG_FXAS21002_TRIGGER_NONE=y
-CONFIG_FXOS8700_TRIGGER_NONE=y
 CONFIG_FXLS8974_TRIGGER_NONE=y
+CONFIG_FXOS8700_TRIGGER_NONE=y
 CONFIG_GROW_R502A_TRIGGER_NONE=y
 CONFIG_HMC5883L_TRIGGER_NONE=y
 CONFIG_HTS221_TRIGGER_NONE=y
 CONFIG_ICM42605_TRIGGER_NONE=y
-CONFIG_ICM42670_TRIGGER_NONE=y
 CONFIG_ICM42688_TRIGGER_NONE=y
+CONFIG_ICM42X70_TRIGGER_NONE=y
+CONFIG_ICM45686_TRIGGER_NONE=y
+CONFIG_ICP201XX_TRIGGER_NONE=y
 CONFIG_IIS2DH_TRIGGER_NONE=y
 CONFIG_IIS2DLPC_TRIGGER_NONE=y
 CONFIG_IIS2ICLX_TRIGGER_NONE=y
@@ -36,8 +39,8 @@ CONFIG_IIS3DHHC_TRIGGER_NONE=y
 CONFIG_ISL29035_TRIGGER_NONE=y
 CONFIG_ISM330DHCX_TRIGGER_NONE=y
 CONFIG_JC42_TRIGGER_NONE=y
-CONFIG_LIS2DH_TRIGGER_NONE=y
 CONFIG_LIS2DE12_TRIGGER_NONE=y
+CONFIG_LIS2DH_TRIGGER_NONE=y
 CONFIG_LIS2DS12_TRIGGER_NONE=y
 CONFIG_LIS2DU12_TRIGGER_NONE=y
 CONFIG_LIS2DUX12_TRIGGER_NONE=y
@@ -45,15 +48,16 @@ CONFIG_LIS2DW12_TRIGGER_NONE=y
 CONFIG_LIS2MDL_TRIGGER_NONE=y
 CONFIG_LIS3MDL_TRIGGER_NONE=y
 CONFIG_LM75_TRIGGER_NONE=y
-CONFIG_LPS2XDF_TRIGGER_NONE=y
 CONFIG_LPS22HH_TRIGGER_NONE=y
+CONFIG_LPS2XDF_TRIGGER_NONE=y
 CONFIG_LSM6DSL_TRIGGER_NONE=y
-CONFIG_LSM6DSO_TRIGGER_NONE=y
 CONFIG_LSM6DSO16IS_TRIGGER_NONE=y
+CONFIG_LSM6DSO_TRIGGER_NONE=y
 CONFIG_LSM6DSV16X_TRIGGER_NONE=y
 CONFIG_MC3419_TRIGGER_NONE=y
 CONFIG_MPU6050_TRIGGER_NONE=y
 CONFIG_MPU9250_TRIGGER_NONE=y
+CONFIG_OPT3001_TRIGGER_NONE=y
 CONFIG_SHT3XD_TRIGGER_NONE=y
 CONFIG_SM351LT_TRIGGER_NONE=y
 CONFIG_STTS22H_TRIGGER_NONE=y
@@ -67,3 +71,6 @@ CONFIG_TSL2540_TRIGGER_NONE=y
 CONFIG_TSL2591_TRIGGER_NONE=y
 CONFIG_VCNL36825T_TRIGGER_NONE=y
 CONFIG_VCNL4040_TRIGGER_NONE=y
+CONFIG_WSEN_PADS_2511020213301_TRIGGER_NONE=y
+CONFIG_WSEN_TIDS_2521020222501_TRIGGER_NONE=y
+# zephyr-keep-sorted-stop
diff --git a/tests/drivers/build_all/sensor/sensors_trigger_own.conf b/tests/drivers/build_all/sensor/sensors_trigger_own.conf
index 71a55a71791..51d3d4aac65 100644
--- a/tests/drivers/build_all/sensor/sensors_trigger_own.conf
+++ b/tests/drivers/build_all/sensor/sensors_trigger_own.conf
@@ -1,3 +1,4 @@
+# zephyr-keep-sorted-start
 CONFIG_ADT7310_TRIGGER_OWN_THREAD=y
 CONFIG_ADT7420_TRIGGER_OWN_THREAD=y
 CONFIG_ADXL362_TRIGGER_OWN_THREAD=y
@@ -18,13 +19,15 @@ CONFIG_CCS811_TRIGGER_OWN_THREAD=y
 CONFIG_ENS160_TRIGGER_OWN_THREAD=y
 CONFIG_FDC2X1X_TRIGGER_OWN_THREAD=y
 CONFIG_FXAS21002_TRIGGER_OWN_THREAD=y
-CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
 CONFIG_FXLS8974_TRIGGER_OWN_THREAD=y
+CONFIG_FXOS8700_TRIGGER_OWN_THREAD=y
 CONFIG_GROW_R502A_TRIGGER_OWN_THREAD=y
 CONFIG_HMC5883L_TRIGGER_OWN_THREAD=y
 CONFIG_HTS221_TRIGGER_OWN_THREAD=y
-CONFIG_ICM42670_TRIGGER_OWN_THREAD=y
 CONFIG_ICM42688_TRIGGER_OWN_THREAD=y
+CONFIG_ICM42X70_TRIGGER_OWN_THREAD=y
+CONFIG_ICM45686_TRIGGER_OWN_THREAD=y
+CONFIG_ICP201XX_TRIGGER_OWN_THREAD=y
 CONFIG_IIS2DH_TRIGGER_OWN_THREAD=y
 CONFIG_IIS2DLPC_TRIGGER_OWN_THREAD=y
 CONFIG_IIS2ICLX_TRIGGER_OWN_THREAD=y
@@ -34,23 +37,24 @@ CONFIG_IIS3DHHC_TRIGGER_OWN_THREAD=y
 CONFIG_ISL29035_TRIGGER_OWN_THREAD=y
 CONFIG_ISM330DHCX_TRIGGER_OWN_THREAD=y
 CONFIG_JC42_TRIGGER_OWN_THREAD=y
-CONFIG_LIS2DH_TRIGGER_OWN_THREAD=y
 CONFIG_LIS2DE12_TRIGGER_OWN_THREAD=y
+CONFIG_LIS2DH_TRIGGER_OWN_THREAD=y
 CONFIG_LIS2DS12_TRIGGER_OWN_THREAD=y
 CONFIG_LIS2DU12_TRIGGER_OWN_THREAD=y
 CONFIG_LIS2DUX12_TRIGGER_OWN_THREAD=y
 CONFIG_LIS2DW12_TRIGGER_OWN_THREAD=y
 CONFIG_LIS2MDL_TRIGGER_OWN_THREAD=y
 CONFIG_LIS3MDL_TRIGGER_OWN_THREAD=y
-CONFIG_LPS2XDF_TRIGGER_OWN_THREAD=y
 CONFIG_LPS22HH_TRIGGER_OWN_THREAD=y
+CONFIG_LPS2XDF_TRIGGER_OWN_THREAD=y
 CONFIG_LSM6DSL_TRIGGER_OWN_THREAD=y
-CONFIG_LSM6DSO_TRIGGER_OWN_THREAD=y
 CONFIG_LSM6DSO16IS_TRIGGER_OWN_THREAD=y
+CONFIG_LSM6DSO_TRIGGER_OWN_THREAD=y
 CONFIG_LSM6DSV16X_TRIGGER_OWN_THREAD=y
 CONFIG_MC3419_TRIGGER_OWN_THREAD=y
 CONFIG_MPU6050_TRIGGER_OWN_THREAD=y
 CONFIG_MPU9250_TRIGGER_OWN_THREAD=y
+CONFIG_OPT3001_TRIGGER_OWN_THREAD=y
 CONFIG_SHT3XD_TRIGGER_OWN_THREAD=y
 CONFIG_SM351LT_TRIGGER_OWN_THREAD=y
 CONFIG_STTS22H_TRIGGER_OWN_THREAD=y
@@ -63,3 +67,6 @@ CONFIG_TSL2540_TRIGGER_OWN_THREAD=y
 CONFIG_TSL2591_TRIGGER_OWN_THREAD=y
 CONFIG_VCNL36825T_TRIGGER_OWN_THREAD=y
 CONFIG_VCNL4040_TRIGGER_OWN_THREAD=y
+CONFIG_WSEN_PADS_2511020213301_TRIGGER_OWN_THREAD=y
+CONFIG_WSEN_TIDS_2521020222501_TRIGGER_OWN_THREAD=y
+# zephyr-keep-sorted-stop
diff --git a/tests/drivers/build_all/sensor/spi.dtsi b/tests/drivers/build_all/sensor/spi.dtsi
index 6f48188a241..b3d9760f501 100644
--- a/tests/drivers/build_all/sensor/spi.dtsi
+++ b/tests/drivers/build_all/sensor/spi.dtsi
@@ -399,3 +399,33 @@ test_spi_ilps22qs: ilps22qs@30 {
 	spi-max-frequency = <0>;
 	status = "okay";
 };
+
+test_spi_icm45686:icm45686@31 {
+	compatible = "invensense,icm45686";
+	reg = <0x31>;
+	spi-max-frequency = <0>;
+	int-gpios = <&test_gpio 0 0>;
+};
+
+paa3905: paa3905@32 {
+	compatible = "pixart,paa3905";
+	spi-max-frequency = <0>;
+	reg = <0x32>;
+	int-gpios = <&test_gpio 0 0>;
+};
+
+test_spi_pat9136: pat9136@33 {
+	compatible = "pixart,pat9136";
+	reg = <0x33>;
+	spi-max-frequency = <0>;
+	int-gpios = <&test_gpio 0 0>;
+};
+
+test_spi_icp201xx: icp201xx@34 {
+	compatible = "invensense,icp201xx";
+	reg = <0x34>;
+	spi-max-frequency = <0>;
+	int-gpios = <&test_gpio 0 0>;
+	op-mode = "mode0";
+	drive-strength = "current_12mA_1_8V";
+};
diff --git a/tests/drivers/build_all/sensor/src/generic_test.c b/tests/drivers/build_all/sensor/src/generic_test.c
index b8500b4006d..841b5142ac7 100644
--- a/tests/drivers/build_all/sensor/src/generic_test.c
+++ b/tests/drivers/build_all/sensor/src/generic_test.c
@@ -217,33 +217,8 @@ static void run_generic_test(const struct device *dev)
 			q31_t q;
 			int8_t shift;
 
-			switch (ch) {
-			/* Special handling to break out triplet samples. */
-			case SENSOR_CHAN_MAGN_X:
-			case SENSOR_CHAN_ACCEL_X:
-			case SENSOR_CHAN_GYRO_X:
-				q = decoded_data.three_axis.readings[0].x;
-				shift = decoded_data.three_axis.shift;
-				break;
-			case SENSOR_CHAN_MAGN_Y:
-			case SENSOR_CHAN_ACCEL_Y:
-			case SENSOR_CHAN_GYRO_Y:
-				q = decoded_data.three_axis.readings[0].y;
-				shift = decoded_data.three_axis.shift;
-				break;
-			case SENSOR_CHAN_MAGN_Z:
-			case SENSOR_CHAN_ACCEL_Z:
-			case SENSOR_CHAN_GYRO_Z:
-				q = decoded_data.three_axis.readings[0].z;
-				shift = decoded_data.three_axis.shift;
-				break;
-
-			/* Default case for single Q31 samples */
-			default:
-				q = decoded_data.q31.readings[0].value;
-				shift = decoded_data.q31.shift;
-				break;
-			}
+			q = decoded_data.q31.readings[0].value;
+			shift = decoded_data.q31.shift;
 
 			/* Align everything to be a 64-bit Q32.32 number for comparison */
 			int64_t expected_shifted =
diff --git a/tests/drivers/build_all/sensor/testcase.yaml b/tests/drivers/build_all/sensor/testcase.yaml
index 3e5a0e3b5c3..1786d809d72 100644
--- a/tests/drivers/build_all/sensor/testcase.yaml
+++ b/tests/drivers/build_all/sensor/testcase.yaml
@@ -8,27 +8,27 @@ common:
     - native_sim
   build_only: true
 tests:
-  sensors.build.sensorhub:
+  drivers.sensor.sensorhub.build:
     extra_args: EXTRA_CONF_FILE=sensors_shub.conf;sensors_die_temp.conf
-  sensors.build.trigger.own:
+  drivers.sensor.trigger.own.build:
     extra_args: EXTRA_CONF_FILE=sensors_trigger_own.conf;sensors_die_temp.conf
-  sensors.build.trigger.global:
+  drivers.sensor.trigger.global.build:
     extra_args: EXTRA_CONF_FILE=sensors_trigger_global.conf;sensors_die_temp.conf
-  sensors.build.trigger.none:
+  drivers.sensor.trigger.none.build:
     extra_args: EXTRA_CONF_FILE=sensors_trigger_none.conf;sensors_die_temp.conf
-  sensors.build.no_default:
+  drivers.sensor.no_default.build:
     extra_args: EXTRA_CONF_FILE=sensors_no_default.conf
-  sensors.build:
+  drivers.sensor.build:
     tags: sensors
     extra_args: EXTRA_CONF_FILE=sensors_die_temp.conf
     extra_configs:
       - CONFIG_UART_INTERRUPT_DRIVEN=y
-  sensors.build.pm:
+  drivers.sensor.pm.build:
     extra_configs:
       - CONFIG_PM=y
       - CONFIG_PM_DEVICE=y
       - CONFIG_UART_INTERRUPT_DRIVEN=y
-  sensors.generic_test:
+  drivers.sensor.generic_test:
     build_only: false
     extra_configs:
       - CONFIG_GENERIC_SENSOR_TEST=y
diff --git a/tests/drivers/build_all/spi/CMakeLists.txt b/tests/drivers/build_all/spi/CMakeLists.txt
new file mode 100644
index 00000000000..518596a02f7
--- /dev/null
+++ b/tests/drivers/build_all/spi/CMakeLists.txt
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(build_all)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/drivers/build_all/spi/boards/qemu_cortex_m3.overlay b/tests/drivers/build_all/spi/boards/qemu_cortex_m3.overlay
new file mode 100644
index 00000000000..f042d906c7d
--- /dev/null
+++ b/tests/drivers/build_all/spi/boards/qemu_cortex_m3.overlay
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025 Meta Platforms
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	spi0: spi@88888888 {
+		compatible = "cdns,spi";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0x88888888 0x400>;
+		interrupt-parent = <&nvic>;
+		interrupts = <4 1>;
+		fifo-width = <8>;
+		rx-fifo-depth = <256>;
+		tx-fifo-depth = <256>;
+		clock-frequency = <100000000>;
+	};
+};
diff --git a/tests/drivers/build_all/spi/prj.conf b/tests/drivers/build_all/spi/prj.conf
new file mode 100644
index 00000000000..65c23a395a3
--- /dev/null
+++ b/tests/drivers/build_all/spi/prj.conf
@@ -0,0 +1,5 @@
+CONFIG_TEST=y
+CONFIG_TEST_USERSPACE=y
+CONFIG_SPI=y
+CONFIG_SPI_SLAVE=y
+CONFIG_SPI_CDNS=y
diff --git a/tests/drivers/build_all/spi/src/main.c b/tests/drivers/build_all/spi/src/main.c
new file mode 100644
index 00000000000..079f0098c6c
--- /dev/null
+++ b/tests/drivers/build_all/spi/src/main.c
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2025 Meta Platforms
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+int main(void)
+{
+	return 0;
+}
diff --git a/tests/drivers/build_all/spi/testcase.yaml b/tests/drivers/build_all/spi/testcase.yaml
new file mode 100644
index 00000000000..5b275c69f1c
--- /dev/null
+++ b/tests/drivers/build_all/spi/testcase.yaml
@@ -0,0 +1,11 @@
+common:
+  build_only: true
+  tags:
+    - drivers
+    - spi
+tests:
+  drivers.spi.build:
+    # will cover drivers without in-tree boards
+    platform_allow: qemu_cortex_m3
+    tags: spi_cdns
+    extra_args: "CONFIG_SPI=y"
diff --git a/tests/drivers/build_all/stepper/gpio.dtsi b/tests/drivers/build_all/stepper/gpio.dtsi
index 3c159afaee7..b5151a3149c 100644
--- a/tests/drivers/build_all/stepper/gpio.dtsi
+++ b/tests/drivers/build_all/stepper/gpio.dtsi
@@ -3,17 +3,11 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-test_gpio_stepper: test_gpio_stepper {
-	compatible = "zephyr,gpio-stepper";
-	status = "okay";
-	micro-step-res = <1>;
-	gpios = <&test_gpio 0 0>,
-		<&test_gpio 0 0>,
-		<&test_gpio 0 0>,
-		<&test_gpio 0 0>;
-};
+/****************************************
+ *  PLEASE KEEP ALPHABETICALLY SORTED   *
+ ***************************************/
 
-test_tmc2209: tmc2209_motor {
+adi_tmc2209: adi_tmc2209 {
 	compatible = "adi,tmc2209";
 	status = "okay";
 	micro-step-res = <1>;
@@ -25,9 +19,22 @@ test_tmc2209: tmc2209_motor {
 	counter = <&counter0>;
 };
 
-drv8424: drv8424 {
+allegro_a4979: allegro_a4979 {
 	status = "okay";
-	compatible = "ti,drv8424";
+	compatible = "allegro,a4979";
+	micro-step-res = <1>;
+	reset-gpios = <&test_gpio 0 0>;
+	dir-gpios = <&test_gpio 0 0>;
+	step-gpios = <&test_gpio 0 0>;
+	en-gpios = <&test_gpio 0 0>;
+	m0-gpios = <&test_gpio 0 0>;
+	m1-gpios = <&test_gpio 0 0>;
+	counter = <&counter0>;
+};
+
+ti_drv84xx: ti_drv84xx {
+	status = "okay";
+	compatible = "ti,drv84xx";
 
 	dir-gpios = <&test_gpio 0 0>;
 	step-gpios = <&test_gpio 0 0>;
@@ -37,3 +44,13 @@ drv8424: drv8424 {
 	m1-gpios = <&test_gpio 0 0>;
 	counter = <&counter0>;
 };
+
+zephyr_gpio_stepper: zephyr_gpio_stepper {
+	compatible = "zephyr,gpio-stepper";
+	status = "okay";
+	micro-step-res = <1>;
+	gpios = <&test_gpio 0 0>,
+		<&test_gpio 0 0>,
+		<&test_gpio 0 0>,
+		<&test_gpio 0 0>;
+};
diff --git a/tests/drivers/build_all/stepper/spi.dtsi b/tests/drivers/build_all/stepper/spi.dtsi
index 83eae272946..1999e3ee017 100644
--- a/tests/drivers/build_all/stepper/spi.dtsi
+++ b/tests/drivers/build_all/stepper/spi.dtsi
@@ -6,21 +6,117 @@
  * PLEASE KEEP REG ADDRESSES SEQUENTIAL *
  ***************************************/
 
-test_spi_tmc5041: tmc5041@0 {
-	compatible = "adi,tmc5041";
+adi_tmc50xx: adi_tmc50xx@0 {
+	compatible = "adi,tmc50xx";
+	status = "okay";
 	reg = <0x0>;
-	spi-max-frequency = <0>;
+	spi-max-frequency = <8000000>;
+	label = "tmc5041_0";
+
 	#address-cells = <1>;
 	#size-cells = <0>;
-	clock-frequency = <1>;
 
-	tmc5041_0: tmc5041_0@0 {
+	poscmp-enable; test-mode; lock-gconf; /* ADI TMC Global configuration flags */
+	clock-frequency = <16000000>; /* Internal/External Clock frequency */
+
+	tmc50xx_0: tmc50xx_0@0 {
 		status = "okay";
 		reg = <0>;
+
+		/* common stepper controller settings */
+		invert-direction;
+		micro-step-res = <256>;
+
+		/* ADI TMC stallguard settings specific to TMC50XX */
+		activate-stallguard2;
+		stallguard-velocity-check-interval-ms=<100>;
+		stallguard2-threshold=<9>;
+		stallguard-threshold-velocity=<500000>;
+
+		/* ADI TMC ramp generator as well as current settings */
+		vstart = <10>;
+		a1 = <20>;
+		v1 = <30>;
+		d1 = <40>;
+		vmax = <50>;
+		amax = <60>;
+		dmax = <70>;
+		tzerowait = <80>;
+		vhigh = <90>;
+		vcoolthrs = <100>;
+		ihold = <1>;
+		irun = <2>;
+		iholddelay = <3>;
 	};
 
-	tmc5041_1: tmc5041_1@1 {
+	tmc50xx_1: tmc50xx_1@1 {
 		status = "okay";
 		reg = <1>;
+
+		/* common stepper controller settings */
+		invert-direction;
+		micro-step-res = <256>;
+
+		/* ADI TMC stallguard settings specific to TMC50XX */
+		activate-stallguard2;
+		stallguard-velocity-check-interval-ms=<100>;
+		stallguard2-threshold=<9>;
+		stallguard-threshold-velocity=<500000>;
+
+		/* ADI TMC ramp generator as well as current settings */
+		vstart = <10>;
+		a1 = <20>;
+		v1 = <30>;
+		d1 = <40>;
+		vmax = <50>;
+		amax = <60>;
+		dmax = <70>;
+		tzerowait = <80>;
+		vhigh = <90>;
+		vcoolthrs = <100>;
+		ihold = <1>;
+		irun = <2>;
+		iholddelay = <3>;
 	};
 };
+
+adi_tmc51xx: adi_tmc51xx@1 {
+	compatible = "adi,tmc51xx";
+	status = "okay";
+	reg = <0x01>;
+	spi-max-frequency = <8000000>;
+	label = "tmc5160_1";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	en-pwm-mode; test-mode; /* ADI TMC Global configuration flags */
+	clock-frequency = <16000000>; /* Internal/External Clock frequency */
+
+	/* common stepper controller settings */
+	invert-direction;
+	micro-step-res = <256>;
+
+	/* ADI TMC stallguard settings specific to TMC5160 */
+	activate-stallguard2;
+	stallguard-velocity-check-interval-ms=<100>;
+	stallguard2-threshold=<9>;
+	stallguard-threshold-velocity=<50000>;
+
+	/* ADI TMC ramp generator as well as current settings */
+	vstart = <10>;
+	a1 = <20>;
+	v1 = <30>;
+	d1 = <40>;
+	vmax = <50>;
+	amax = <60>;
+	dmax = <70>;
+	tzerowait = <80>;
+	thigh = <90>;
+	tcoolthrs = <100>;
+	tpwmthrs = <110>;
+	tpowerdown = <120>;
+	ihold = <1>;
+	irun = <2>;
+	iholddelay = <3>;
+};
diff --git a/tests/drivers/build_all/usb/i2c_devices.overlay b/tests/drivers/build_all/usb/i2c_devices.overlay
index 8ba417ed2cb..352d8b99a8a 100644
--- a/tests/drivers/build_all/usb/i2c_devices.overlay
+++ b/tests/drivers/build_all/usb/i2c_devices.overlay
@@ -36,6 +36,14 @@
 				reg = <1>;
 				irq-gpios = <&test_gpio 0 0>;
 			};
+
+			test_i2c_rt1715: rt1715@2 {
+				compatible = "richtek,rt1715";
+				reg = <2>;
+				irq-gpios = <&test_gpio 0 0>;
+				vconn-ctrl-gpios = <&test_gpio 0 0>;
+				vconn-disc-gpios = <&test_gpio 0 0>;
+			};
 		};
 	};
 };
diff --git a/tests/drivers/can/api/boards/nucleo_n657x0_q_stm32n657xx_sb.conf b/tests/drivers/can/api/boards/nucleo_n657x0_q_stm32n657xx_sb.conf
new file mode 100644
index 00000000000..9fb2581d7f4
--- /dev/null
+++ b/tests/drivers/can/api/boards/nucleo_n657x0_q_stm32n657xx_sb.conf
@@ -0,0 +1 @@
+CONFIG_TEST_USERSPACE=n
diff --git a/tests/drivers/can/api/boards/stm32n6570_dk_stm32n657xx_sb.conf b/tests/drivers/can/api/boards/stm32n6570_dk_stm32n657xx_sb.conf
new file mode 100644
index 00000000000..9fb2581d7f4
--- /dev/null
+++ b/tests/drivers/can/api/boards/stm32n6570_dk_stm32n657xx_sb.conf
@@ -0,0 +1 @@
+CONFIG_TEST_USERSPACE=n
diff --git a/tests/drivers/can/host/testcase.yaml b/tests/drivers/can/host/testcase.yaml
index 9c5ed9a1e37..a056cf6fdd7 100644
--- a/tests/drivers/can/host/testcase.yaml
+++ b/tests/drivers/can/host/testcase.yaml
@@ -11,7 +11,7 @@ tests:
       pytest_dut_scope: session
       fixture: can
     extra_configs:
-      - arch:posix:CONFIG_NATIVE_UART_0_ON_STDINOUT=y
+      - arch:posix:CONFIG_UART_NATIVE_PTY_0_ON_STDINOUT=y
     integration_platforms:
       - native_sim
       - native_sim/native/64
diff --git a/tests/drivers/can/timing/boards/native_posix.conf b/tests/drivers/can/timing/boards/mcx_n9xx_evk_mcxn947_cpu0.conf
similarity index 100%
rename from tests/drivers/can/timing/boards/native_posix.conf
rename to tests/drivers/can/timing/boards/mcx_n9xx_evk_mcxn947_cpu0.conf
diff --git a/tests/drivers/can/timing/boards/native_posix_native_64.conf b/tests/drivers/can/timing/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.conf
similarity index 100%
rename from tests/drivers/can/timing/boards/native_posix_native_64.conf
rename to tests/drivers/can/timing/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.conf
diff --git a/tests/drivers/can/timing/boards/nucleo_n657x0_q_stm32n657xx_sb.conf b/tests/drivers/can/timing/boards/nucleo_n657x0_q_stm32n657xx_sb.conf
new file mode 100644
index 00000000000..e0f23afd0cb
--- /dev/null
+++ b/tests/drivers/can/timing/boards/nucleo_n657x0_q_stm32n657xx_sb.conf
@@ -0,0 +1,2 @@
+CONFIG_TEST_ALL_BITRATES=y
+CONFIG_TEST_USERSPACE=n
diff --git a/tests/drivers/can/timing/boards/stm32n6570_dk_stm32n657xx_sb.conf b/tests/drivers/can/timing/boards/stm32n6570_dk_stm32n657xx_sb.conf
new file mode 100644
index 00000000000..e0f23afd0cb
--- /dev/null
+++ b/tests/drivers/can/timing/boards/stm32n6570_dk_stm32n657xx_sb.conf
@@ -0,0 +1,2 @@
+CONFIG_TEST_ALL_BITRATES=y
+CONFIG_TEST_USERSPACE=n
diff --git a/tests/drivers/clock_control/clock_control_api/testcase.yaml b/tests/drivers/clock_control/clock_control_api/testcase.yaml
index 21b3f3deb76..972dcc1a1aa 100644
--- a/tests/drivers/clock_control/clock_control_api/testcase.yaml
+++ b/tests/drivers/clock_control/clock_control_api/testcase.yaml
@@ -13,6 +13,7 @@ tests:
       - sltb010a@0
       - xg24_dk2601b
       - xg27_dk2602a
+      - xg29_rb4412a
     integration_platforms:
       - esp32_devkitc_wroom/esp32/procpu
   drivers.clock.clock_control_nrf5:
@@ -24,6 +25,7 @@ tests:
       - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf51dk/nrf51822
   drivers.clock.clock_control_nrf5_lfclk_rc:
@@ -34,6 +36,7 @@ tests:
       - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf51dk/nrf51822
     extra_args: CONF_FILE="nrf_lfclk_rc.conf"
diff --git a/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml b/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml
index 963618c6f23..756a92a98e3 100644
--- a/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml
+++ b/tests/drivers/clock_control/nrf_clock_calibration/testcase.yaml
@@ -10,5 +10,6 @@ tests:
       - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf51dk/nrf51822
diff --git a/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml b/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml
index cad39c3625f..eeb034a8ec0 100644
--- a/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml
+++ b/tests/drivers/clock_control/nrf_lf_clock_start/testcase.yaml
@@ -16,6 +16,7 @@ tests:
       - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     extra_configs:
       - CONFIG_SYSTEM_CLOCK_WAIT_FOR_STABILITY=y
       - CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y
@@ -33,6 +34,7 @@ tests:
       - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     extra_configs:
       - CONFIG_SYSTEM_CLOCK_WAIT_FOR_AVAILABILITY=y
       - CONFIG_CLOCK_CONTROL_NRF_K32SRC_XTAL=y
@@ -48,6 +50,7 @@ tests:
       - nrf5340dk/nrf5340/cpuapp
       - nrf5340dk/nrf5340/cpunet
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf51dk/nrf51822
     extra_configs:
@@ -64,6 +67,7 @@ tests:
       - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf51dk/nrf51822
     extra_configs:
@@ -80,6 +84,7 @@ tests:
       - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf51dk/nrf51822
     extra_configs:
@@ -96,6 +101,7 @@ tests:
       - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf51dk/nrf51822
     extra_configs:
@@ -112,6 +118,7 @@ tests:
       - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf51dk/nrf51822
     extra_configs:
@@ -128,6 +135,7 @@ tests:
       - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf51dk/nrf51822
     extra_configs:
@@ -144,6 +152,7 @@ tests:
       - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf51dk/nrf51822
     extra_configs:
diff --git a/tests/drivers/clock_control/onoff/testcase.yaml b/tests/drivers/clock_control/onoff/testcase.yaml
index 74d8a7f84d8..f24dce72a7a 100644
--- a/tests/drivers/clock_control/onoff/testcase.yaml
+++ b/tests/drivers/clock_control/onoff/testcase.yaml
@@ -11,5 +11,6 @@ tests:
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
       - nrf9160dk/nrf9160
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf51dk/nrf51822
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/test_stm32_clock_configuration_adc.c b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/test_stm32_clock_configuration_adc.c
index 0225c495a90..43c6bae18ea 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/test_stm32_clock_configuration_adc.c
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/src/test_stm32_clock_configuration_adc.c
@@ -94,13 +94,11 @@ ZTEST(stm32_common_devices_clocks, test_adc_clk_config)
 		dev_actual_clk_src = GET_ADC_SOURCE();
 
 		switch (pclken[1].bus) {
-#if defined(STM32_SRC_SYSCLK)
 		case STM32_SRC_SYSCLK:
 			zassert_equal(dev_actual_clk_src, ADC_SOURCE_SYSCLK,
 					"Expected ADC1 src: SYSCLK (0x%lx). Actual ADC1 src: 0x%x",
 					ADC_SOURCE_SYSCLK, dev_actual_clk_src);
 			break;
-#endif /* STM32_SRC_SYSCLK */
 #if defined(STM32_SRC_PLL_P)
 		case STM32_SRC_PLL_P:
 			zassert_equal(dev_actual_clk_src, ADC_SOURCE_PLL,
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/CMakeLists.txt b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/CMakeLists.txt
new file mode 100644
index 00000000000..b4763ae3d88
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/CMakeLists.txt
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(stm32_clock_configuration_n6)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/clear_clocks.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/clear_clocks.overlay
new file mode 100644
index 00000000000..744eb46c2ff
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/clear_clocks.overlay
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Warning: This overlay clears clocks back to a state equivalent to what could
+ * be found in stm32n6.dtsi
+ */
+
+&clk_hse {
+	status = "disabled";
+	/delete-property/ clock-frequency;
+	/delete-property/ hse-bypass;
+};
+
+&clk_hsi {
+	status = "disabled";
+	/delete-property/ hsi-div;
+};
+
+&clk_lse {
+	status = "disabled";
+};
+
+&ic1 {
+	status = "disabled";
+	/delete-property/ pll-src;
+	/delete-property/ ic-div;
+};
+
+&ic2 {
+	status = "disabled";
+	/delete-property/ pll-src;
+	/delete-property/ ic-div;
+};
+
+&ic6 {
+	status = "disabled";
+	/delete-property/ pll-src;
+	/delete-property/ ic-div;
+};
+
+&ic11 {
+	status = "disabled";
+	/delete-property/ pll-src;
+	/delete-property/ ic-div;
+};
+
+&pll1 {
+	status = "disabled";
+	/delete-property/ div-m;
+	/delete-property/ mul-n;
+	/delete-property/ div-p1;
+	/delete-property/ div-p2;
+	/delete-property/ clocks;
+};
+
+&rcc {
+	/delete-property/ clocks;
+	/delete-property/ clock-frequency;
+	/delete-property/ ahb-prescaler;
+	/delete-property/ apb1-prescaler;
+	/delete-property/ apb2-prescaler;
+	/delete-property/ apb4-prescaler;
+	/delete-property/ apb5-prescaler;
+	/delete-property/ timg-prescaler;
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/hse_48.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/hse_48.overlay
new file mode 100644
index 00000000000..d91d0a35248
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/hse_48.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after clear_clocks.overlay file.
+ */
+
+&clk_hse {
+	status = "okay";
+	clock-frequency = <DT_FREQ_M(48)>;
+};
+
+&cpusw {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_HSE CPU_SEL(2)>;
+	clock-frequency = <DT_FREQ_M(48)>;
+};
+
+&perck {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_HSE PER_SEL(2)>;
+};
+
+&rcc {
+	clocks = <&clk_hse>;
+	clock-frequency = <DT_FREQ_M(48)>;
+	ahb-prescaler = <1>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+	apb4-prescaler = <1>;
+	apb5-prescaler = <1>;
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/hsi_64.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/hsi_64.overlay
new file mode 100644
index 00000000000..c30a4e58e17
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/hsi_64.overlay
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after clear_clocks.overlay file.
+ */
+
+&clk_hsi {
+	status = "okay";
+	clock-frequency = <DT_FREQ_M(64)>;
+	hsi-div = <1>;
+};
+
+&cpusw {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_HSI CPU_SEL(0)>;
+	clock-frequency = <DT_FREQ_M(64)>;
+};
+
+&perck {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_HSI PER_SEL(0)>;
+};
+
+&rcc {
+	clocks = <&clk_hsi>;
+	clock-frequency = <DT_FREQ_M(64)>;
+	ahb-prescaler = <1>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+	apb4-prescaler = <1>;
+	apb5-prescaler = <1>;
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/pll_hse_200.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/pll_hse_200.overlay
new file mode 100644
index 00000000000..7f654621ddf
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/pll_hse_200.overlay
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after clear_clocks.overlay file.
+ */
+
+&clk_hse {
+	status = "okay";
+	clock-frequency = <DT_FREQ_M(48)>;
+};
+
+&cpusw {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;
+	clock-frequency = <DT_FREQ_M(200)>;
+};
+
+&ic1 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <2>;
+};
+
+&ic2 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <3>;
+};
+
+&ic6 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <2>;
+};
+
+&ic11 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <3>;
+};
+
+&perck {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_HSI PER_SEL(0)>;
+};
+
+&pll1 {
+	status = "okay";
+	clocks = <&clk_hsi>;
+	div-m = <12>;
+	mul-n = <75>;
+	div-p1 = <1>;
+	div-p2 = <1>;
+};
+
+&rcc {
+	/* ic2, ic6 & ic11 must all be enabled to set ic2 as SYSCLK */
+	clocks = <&ic2>;
+	clock-frequency = <DT_FREQ_M(200)>;
+	ahb-prescaler = <2>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+	apb4-prescaler = <1>;
+	apb5-prescaler = <1>;
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/pll_hse_600_400.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/pll_hse_600_400.overlay
new file mode 100644
index 00000000000..68b1c82dcea
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/pll_hse_600_400.overlay
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after clear_clocks.overlay file.
+ */
+
+&clk_hse {
+	status = "okay";
+	clock-frequency = <DT_FREQ_M(48)>;
+};
+
+&cpusw {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;
+	clock-frequency = <DT_FREQ_M(600)>;
+};
+
+&ic1 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <1>;
+};
+
+&ic2 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <3>;
+};
+
+&ic6 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <2>;
+};
+
+&ic11 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <3>;
+};
+
+&perck {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_HSE PER_SEL(2)>;
+};
+
+&pll1 {
+	status = "okay";
+	clocks = <&clk_hse>;
+	div-m = <4>;
+	mul-n = <50>;
+	div-p1 = <1>;
+	div-p2 = <1>;
+};
+
+&rcc {
+	/* ic2, ic6 & ic11 must all be enabled to set ic2 as SYSCLK */
+	clocks = <&ic2>;
+	clock-frequency = <DT_FREQ_M(400)>;
+	ahb-prescaler = <2>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+	apb4-prescaler = <1>;
+	apb5-prescaler = <1>;
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/pll_hsi_600_400.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/pll_hsi_600_400.overlay
new file mode 100644
index 00000000000..11532796aca
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/boards/pll_hsi_600_400.overlay
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after clear_clocks.overlay file.
+ */
+
+&clk_hsi {
+	status = "okay";
+	clock-frequency = <DT_FREQ_M(64)>;
+	hsi-div = <1>;
+};
+
+&cpusw {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_HSI CPU_SEL(0)>;
+	clock-frequency = <DT_FREQ_M(64)>;
+};
+
+&ic1 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <2>;
+};
+
+&ic2 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <3>;
+};
+
+&ic6 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <2>;
+};
+
+&ic11 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <3>;
+};
+
+&perck {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_HSI PER_SEL(0)>;
+};
+
+&pll1 {
+	status = "okay";
+	clocks = <&clk_hsi>;
+	div-m = <4>;
+	mul-n = <75>;
+	div-p1 = <1>;
+	div-p2 = <1>;
+};
+
+&rcc {
+	/* ic2, ic6 & ic11 must all be enabled to set ic2 as SYSCLK */
+	clocks = <&ic2>;
+	clock-frequency = <DT_FREQ_M(400)>;
+	ahb-prescaler = <2>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+	apb4-prescaler = <1>;
+	apb5-prescaler = <1>;
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/prj.conf b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/prj.conf
new file mode 100644
index 00000000000..9467c292689
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/prj.conf
@@ -0,0 +1 @@
+CONFIG_ZTEST=y
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/src/test_stm32_clock_configuration.c b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/src/test_stm32_clock_configuration.c
new file mode 100644
index 00000000000..914a54e88c8
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/src/test_stm32_clock_configuration.c
@@ -0,0 +1,190 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc.h>
+#include <zephyr/drivers/clock_control/stm32_clock_control.h>
+#include <zephyr/ztest.h>
+
+ZTEST(stm32n6_clock_core_config, test_cpuclk_freq)
+{
+	uint32_t cpuclk_freq = HAL_RCC_GetCpuClockFreq();
+
+	zassert_equal(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, cpuclk_freq,
+		      "Expected cpuclk_freq: %d. Actual cupclk_freq: %d",
+		      CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, cpuclk_freq);
+}
+
+ZTEST(stm32n6_clock_core_config, test_cpuclk_src)
+{
+	int cpu_clk_src = __HAL_RCC_GET_CPUCLK_SOURCE();
+
+#if IS_ENABLED(STM32_CPUCLK_SRC_HSI)
+	zassert_equal(RCC_CPUCLKSOURCE_STATUS_HSI, cpu_clk_src,
+		      "Expected sysclk src: HSI (0x%x). Actual: 0x%x",
+		      RCC_CPUCLKSOURCE_STATUS_HSI, cpu_clk_src);
+#elif IS_ENABLED(STM32_CPUCLK_SRC_MSI)
+	zassert_equal(RCC_CPUCLKSOURCE_STATUS_MSI, cpu_clk_src,
+		      "Expected sysclk src: MSI (0x%x). Actual: 0x%x",
+		      RCC_CPUCLKSOURCE_STATUS_MSI, cpu_clk_src);
+#elif IS_ENABLED(STM32_CPUCLK_SRC_HSE)
+	zassert_equal(RCC_CPUCLKSOURCE_STATUS_HSE, cpu_clk_src,
+		      "Expected sysclk src: HSE (0x%x). Actual: 0x%x",
+		      RCC_CPUCLKSOURCE_STATUS_HSE, cpu_clk_src);
+#elif IS_ENABLED(STM32_CPUCLK_SRC_IC1)
+	zassert_equal(RCC_CPUCLKSOURCE_STATUS_IC1, cpu_clk_src,
+		      "Expected cpuclk src: IC1 (0x%x). Actual: 0x%x",
+		      RCC_CPUCLKSOURCE_STATUS_IC1, cpu_clk_src);
+#else
+	/* Case not expected */
+	zassert_true(IS_ENABLED(STM32_CPUCLK_SRC_HSI) ||
+		     IS_ENABLED(STM32_CPUCLK_SRC_MSI) ||
+		     IS_ENABLED(STM32_CPUCLK_SRC_HSE) ||
+		     IS_ENABLED(STM32_CPUCLK_SRC_IC1),
+		      "Not expected. cpu_clk_src: %d\n", cpu_clk_src);
+#endif
+}
+
+ZTEST(stm32n6_clock_core_config, test_sysclk_src)
+{
+	int sys_clk_src = __HAL_RCC_GET_SYSCLK_SOURCE();
+
+#if IS_ENABLED(STM32_SYSCLK_SRC_HSI)
+	zassert_equal(RCC_SYSCLKSOURCE_STATUS_HSI, sys_clk_src,
+			"Expected sysclk src: HSI (0x%x). Actual: 0x%x",
+			RCC_SYSCLKSOURCE_STATUS_HSI, sys_clk_src);
+#elif IS_ENABLED(STM32_SYSCLK_SRC_MSI)
+	zassert_equal(RCC_SYSCLKSOURCE_STATUS_MSI, sys_clk_src,
+			"Expected sysclk src: MSI (0x%x). Actual: 0x%x",
+			RCC_SYSCLKSOURCE_STATUS_MSI, sys_clk_src);
+#elif IS_ENABLED(STM32_SYSCLK_SRC_HSE)
+	zassert_equal(RCC_SYSCLKSOURCE_STATUS_HSE, sys_clk_src,
+			"Expected sysclk src: HSE (0x%x). Actual: 0x%x",
+			RCC_SYSCLKSOURCE_STATUS_HSE, sys_clk_src);
+#elif IS_ENABLED(STM32_SYSCLK_SRC_IC2)
+	zassert_equal(RCC_SYSCLKSOURCE_STATUS_IC2_IC6_IC11, sys_clk_src,
+			"Expected sysclk src: IC2 (0x%x). Actual: 0x%x",
+			RCC_SYSCLKSOURCE_STATUS_IC2_IC6_IC11, sys_clk_src);
+#else
+	/* Case not expected */
+	zassert_true(IS_ENABLED(STM32_SYSCLK_SRC_HSI) ||
+		     IS_ENABLED(STM32_SYSCLK_SRC_MSI) ||
+		     IS_ENABLED(STM32_SYSCLK_SRC_HSE) ||
+		     IS_ENABLED(STM32_SYSCLK_SRC_IC2)),
+		     "Not expected. sys_clk_src: %d\n", sys_clk_src);
+#endif
+}
+
+#if IS_ENABLED(STM32_PLL_ENABLED)
+ZTEST(stm32n6_clock_core_config, test_pll_src)
+{
+	uint32_t pll_src = __HAL_RCC_GET_PLL1_OSCSOURCE();
+
+#if STM32_PLL_SRC_HSI
+	zassert_equal(RCC_PLLSOURCE_HSI, pll_src,
+			"Expected PLL src: HSI. Actual PLL src: %d",
+			pll_src);
+#elif STM32_PLL_SRC_MSI
+	zassert_equal(RCC_PLLSOURCE_MSI, pll_src,
+			"Expected PLL src: MSI. Actual PLL src: %d",
+			pll_src);
+#elif STM32_PLL_SRC_HSE
+	zassert_equal(RCC_PLLSOURCE_HSE, pll_src,
+			"Expected PLL src: HSE. Actual PLL src: %d",
+			pll_src);
+#else
+	zassert_equal(RCC_PLLSOURCE_NONE, pll_src,
+			"Expected PLL src: None. Actual PLL src: %d",
+			pll_src);
+#endif
+}
+#endif /* STM32_PLL_ENABLED */
+
+#if IS_ENABLED(STM32_HSE_ENABLED)
+ZTEST(stm32n6_clock_core_config, test_hse_css)
+{
+	/* there is no function to read CSS status, so read directly from the SoC register */
+	bool css_enabled = (READ_BIT(RCC->HSECFGR, RCC_HSECFGR_HSECSSON) == 1U);
+
+	if (IS_ENABLED(STM32_HSE_CSS)) {
+		zassert_true(css_enabled, "HSE CSS is not enabled");
+	} else {
+		zassert_false(css_enabled, "HSE CSS unexpectedly enabled");
+	}
+}
+#endif /* STM32_HSE_ENABLED */
+
+#if IS_ENABLED(STM32_LSE_ENABLED)
+ZTEST(stm32n6_clock_core_config, test_lse_css)
+{
+	/* there is no function to read CSS status, so read directly from the SoC register */
+	bool css_enabled = (READ_BIT(RCC->LSECFGR, RCC_LSECFGR_LSECSSON) == 1U);
+
+	if (IS_ENABLED(STM32_LSE_CSS)) {
+		zassert_true(css_enabled, "LSE CSS is not enabled");
+	} else {
+		zassert_false(css_enabled, "LSE CSS unexpectedly enabled");
+	}
+}
+#endif /* STM32_LSE_ENABLED */
+
+#if IS_ENABLED(STM32_CKPER_ENABLED)
+ZTEST(stm32n6_clock_core_config, test_perclk_config)
+{
+	uint32_t perclk_dt_domain_clk, perclk_actual_domain_clk;
+
+	perclk_dt_domain_clk = DT_CLOCKS_CELL_BY_IDX(DT_NODELABEL(perck), 0, bus);
+	perclk_actual_domain_clk = __HAL_RCC_GET_CLKP_SOURCE();
+
+	switch (perclk_dt_domain_clk) {
+	case STM32_SRC_HSI:
+		zassert_equal(perclk_actual_domain_clk, RCC_CLKPCLKSOURCE_HSI,
+			"Expected PERCK src: HSI (0x%x). Actual: 0x%x",
+			RCC_CLKPCLKSOURCE_HSI, perclk_actual_domain_clk);
+		break;
+	case STM32_SRC_MSI:
+		zassert_equal(perclk_actual_domain_clk, RCC_CLKPCLKSOURCE_MSI,
+			"Expected PERCK src: MSI (0x%x). Actual: 0x%x",
+			RCC_CLKPCLKSOURCE_MSI, perclk_actual_domain_clk);
+		break;
+	case STM32_SRC_HSE:
+		zassert_equal(perclk_actual_domain_clk, RCC_CLKPCLKSOURCE_HSE,
+			"Expected PERCK src: HSE (0x%x). Actual: 0x%x",
+			RCC_CLKPCLKSOURCE_HSE, perclk_actual_domain_clk);
+		break;
+	case STM32_SRC_IC19:
+		zassert_equal(perclk_actual_domain_clk, RCC_CLKPCLKSOURCE_IC19,
+			"Expected PERCK src: IC19 (0x%x). Actual: 0x%x",
+			RCC_CLKPCLKSOURCE_IC19, perclk_actual_domain_clk);
+		break;
+	case STM32_SRC_IC5:
+		zassert_equal(perclk_actual_domain_clk, RCC_CLKPCLKSOURCE_IC5,
+			"Expected PERCK src: IC5 (0x%x). Actual: 0x%x",
+			RCC_CLKPCLKSOURCE_IC5, perclk_actual_domain_clk);
+		break;
+	case STM32_SRC_IC10:
+		zassert_equal(perclk_actual_domain_clk, RCC_CLKPCLKSOURCE_IC10,
+			"Expected PERCK src: IC10 (0x%x). Actual: 0x%x",
+			RCC_CLKPCLKSOURCE_IC10, perclk_actual_domain_clk);
+		break;
+	case STM32_SRC_IC15:
+		zassert_equal(perclk_actual_domain_clk, RCC_CLKPCLKSOURCE_IC15,
+			"Expected PERCK src: IC15 (0x%x). Actual: 0x%x",
+			RCC_CLKPCLKSOURCE_IC15, perclk_actual_domain_clk);
+		break;
+	case STM32_SRC_IC20:
+		zassert_equal(perclk_actual_domain_clk, RCC_CLKPCLKSOURCE_IC20,
+			"Expected PERCK src: IC20 (0x%x). Actual: 0x%x",
+			RCC_CLKPCLKSOURCE_IC20, perclk_actual_domain_clk);
+		break;
+	default:
+		zassert_true(0, "Unexpected PERCK domain_clk src (0x%x)",
+			perclk_dt_domain_clk);
+		break;
+	}
+}
+#endif /* STM32_CKPER_ENABLED */
+
+ZTEST_SUITE(stm32n6_clock_core_config, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/testcase.yaml b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/testcase.yaml
new file mode 100644
index 00000000000..40b087cb2d3
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_core/testcase.yaml
@@ -0,0 +1,22 @@
+common:
+  timeout: 5
+  platform_allow:
+    - stm32n6570_dk/stm32n657xx/sb
+    - nucleo_n657x0_q/stm32n657xx/sb
+  integration_platforms:
+    - stm32n6570_dk/stm32n657xx/sb
+tests:
+  drivers.clock.stm32_clock_configuration.n6.hsi_64:
+    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hsi_64.overlay"
+  drivers.clock.stm32_clock_configuration.n6.cpu_pll_hsi_600_sysclk_pll_hsi_400:
+    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hsi_600_400.overlay"
+  # HSE test on boards that have a HSE: stm32n6570_dk
+  drivers.clock.stm32_clock_configuration.n6.hse_48:
+    platform_allow: stm32n6570_dk/stm32n657xx/sb
+    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/hse_48.overlay"
+  drivers.clock.stm32_clock_configuration.n6.cpu_pll_hse_600_sysclk_pll_hse_400:
+    platform_allow: stm32n6570_dk/stm32n657xx/sb
+    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_600_400.overlay"
+  drivers.clock.stm32_clock_configuration.n6.cpu_pll_hse_200_sysclk_pll_hse_200:
+    platform_allow: stm32n6570_dk/stm32n657xx/sb
+    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/pll_hse_200.overlay"
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/CMakeLists.txt b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/CMakeLists.txt
new file mode 100644
index 00000000000..9e3918a61a4
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/CMakeLists.txt
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(stm32_clock_configuration_n6_devices)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/boards/clear_clocks.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/boards/clear_clocks.overlay
new file mode 100644
index 00000000000..9a24375278e
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/boards/clear_clocks.overlay
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Clocks clean up config
+ * Aim is to avoid conflict with specific default board configuration
+ */
+
+&clk_hse {
+	status = "disabled";
+	/delete-property/ clock-frequency;
+	/delete-property/ hse-bypass;
+};
+
+&clk_hsi {
+	status = "disabled";
+	/delete-property/ hsi-div;
+};
+
+&clk_lse {
+	status = "disabled";
+};
+
+&ic1 {
+	status = "disabled";
+	/delete-property/ pll-src;
+	/delete-property/ ic-div;
+};
+
+&ic2 {
+	status = "disabled";
+	/delete-property/ pll-src;
+	/delete-property/ ic-div;
+};
+
+&ic6 {
+	status = "disabled";
+	/delete-property/ pll-src;
+	/delete-property/ ic-div;
+};
+
+&ic11 {
+	status = "disabled";
+	/delete-property/ pll-src;
+	/delete-property/ ic-div;
+};
+
+&pll1 {
+	status = "disabled";
+	/delete-property/ div-m;
+	/delete-property/ mul-n;
+	/delete-property/ div-p1;
+	/delete-property/ div-p2;
+	/delete-property/ clocks;
+};
+
+&rcc {
+	/delete-property/ clocks;
+	/delete-property/ clock-frequency;
+	/delete-property/ ahb-prescaler;
+	/delete-property/ apb1-prescaler;
+	/delete-property/ apb2-prescaler;
+	/delete-property/ apb4-prescaler;
+	/delete-property/ apb5-prescaler;
+	/delete-property/ timg-prescaler;
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/boards/devices_on_hsi.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/boards/devices_on_hsi.overlay
new file mode 100644
index 00000000000..ae65099a468
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/boards/devices_on_hsi.overlay
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Core and device clock set up
+ *
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after clear_clocks.overlay file.
+ */
+
+&clk_hsi {
+	status = "okay";
+	clock-frequency = <DT_FREQ_M(64)>;
+	hsi-div = <1>;
+};
+
+&cpusw {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;
+	clock-frequency = <DT_FREQ_M(150)>;
+};
+
+&ic1 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <4>;
+};
+
+&ic2 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <3>;
+};
+
+&ic6 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <2>;
+};
+
+&ic11 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <3>;
+};
+
+&perck {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_HSI PER_SEL(0)>;
+};
+
+&pll1 {
+	status = "okay";
+	clocks = <&clk_hsi>;
+	div-m = <4>;
+	mul-n = <75>;
+	div-p1 = <2>;
+	div-p2 = <1>;
+};
+
+&rcc {
+	/* ic2, ic6 & ic11 must all be enabled to set ic2 as SYSCLK */
+	clocks = <&ic2>;
+	clock-frequency = <DT_FREQ_M(400)>;
+	ahb-prescaler = <2>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+	apb4-prescaler = <1>;
+	apb5-prescaler = <1>;
+};
+
+&i2c1 {
+	clocks = <&rcc STM32_CLOCK(APB1, 21)>, <&rcc STM32_SRC_HSI_DIV I2C1_SEL(5)>;
+	status = "disabled";
+};
+
+&adc1 {
+	clocks = <&rcc STM32_CLOCK(AHB1, 5)>, <&rcc STM32_SRC_HSI_DIV ADC12_SEL(5)>;
+	status = "disabled";
+};
+
+&spi5 {
+	clocks = <&rcc STM32_CLOCK(APB2, 20)>, <&rcc STM32_SRC_HSI_DIV SPI5_SEL(5)>;
+	status = "disabled";
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/boards/devices_on_icx.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/boards/devices_on_icx.overlay
new file mode 100644
index 00000000000..884fb63bb93
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/boards/devices_on_icx.overlay
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Core and device clock set up
+ *
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after clear_clocks.overlay file.
+ */
+
+&clk_hsi {
+	status = "okay";
+	clock-frequency = <DT_FREQ_M(64)>;
+	hsi-div = <1>;
+};
+
+&cpusw {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;
+	clock-frequency = <DT_FREQ_M(600)>;
+};
+
+&ic1 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <2>;
+};
+
+&ic2 {
+	status = "okay";
+	pll-src = <2>;
+	ic-div = <3>;
+};
+
+&ic6 {
+	status = "okay";
+	pll-src = <3>;
+	ic-div = <5>;
+};
+
+&ic8 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <10>;
+};
+
+&ic9 {
+	status = "okay";
+	pll-src = <2>;
+	ic-div = <16>;
+};
+
+&ic10 {
+	status = "okay";
+	pll-src = <3>;
+	ic-div = <5>;
+};
+
+&ic11 {
+	status = "okay";
+	pll-src = <4>;
+	ic-div = <3>;
+};
+
+&perck {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_HSI PER_SEL(0)>;
+};
+
+&pll1 {
+	status = "okay";
+	clocks = <&clk_hsi>;
+	div-m = <4>;
+	mul-n = <75>;
+	div-p1 = <1>;
+	div-p2 = <1>;
+};
+
+&pll2 {
+	status = "okay";
+	clocks = <&clk_hsi>;
+	div-m = <8>;
+	mul-n = <300>;
+	div-p1 = <1>;
+	div-p2 = <2>;
+};
+
+&pll3 {
+	status = "okay";
+	clocks = <&clk_hsi>;
+	div-m = <2>;
+	mul-n = <75>;
+	div-p1 = <2>;
+	div-p2 = <5>;
+};
+
+&pll4 {
+	status = "okay";
+	clocks = <&clk_hsi>;
+	div-m = <4>;
+	mul-n = <300>;
+	div-p1 = <1>;
+	div-p2 = <3>;
+};
+
+&rcc {
+	/* ic2, ic6 & ic11 must all be enabled to set ic2 as SYSCLK */
+	clocks = <&ic2>;
+	clock-frequency = <DT_FREQ_M(400)>;
+	ahb-prescaler = <2>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+	apb4-prescaler = <1>;
+	apb5-prescaler = <1>;
+};
+
+&i2c1 {
+	clocks = <&rcc STM32_CLOCK(APB1, 21)>, <&rcc STM32_SRC_IC10 I2C1_SEL(2)>;
+	status = "okay";
+};
+
+&adc1 {
+	clocks = <&rcc STM32_CLOCK(AHB1, 5)>, <&rcc STM32_SRC_IC8 ADC12_SEL(3)>;
+	status = "okay";
+};
+
+&spi5 {
+	clocks = <&rcc STM32_CLOCK(APB2, 20)>, <&rcc STM32_SRC_IC9 SPI5_SEL(2)>;
+	status = "okay";
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/boards/devices_on_perclk.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/boards/devices_on_perclk.overlay
new file mode 100644
index 00000000000..8c834b26e24
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/boards/devices_on_perclk.overlay
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Core and device clock set up
+ *
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after clear_clocks.overlay file.
+ */
+
+&clk_hsi {
+	status = "okay";
+	clock-frequency = <DT_FREQ_M(64)>;
+	hsi-div = <1>;
+};
+
+&cpusw {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;
+	clock-frequency = <DT_FREQ_M(600)>;
+};
+
+&ic1 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <2>;
+};
+
+&ic2 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <3>;
+};
+
+&ic6 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <2>;
+};
+
+&ic11 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <3>;
+};
+
+&perck {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_HSI PER_SEL(0)>;
+};
+
+&pll1 {
+	status = "okay";
+	clocks = <&clk_hsi>;
+	div-m = <4>;
+	mul-n = <75>;
+	div-p1 = <1>;
+	div-p2 = <1>;
+};
+
+&rcc {
+	/* ic2, ic6 & ic11 must all be enabled to set ic2 as SYSCLK */
+	clocks = <&ic2>;
+	clock-frequency = <DT_FREQ_M(400)>;
+	ahb-prescaler = <2>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+	apb4-prescaler = <1>;
+	apb5-prescaler = <1>;
+};
+
+&i2c1 {
+	clocks = <&rcc STM32_CLOCK(APB1, 21)>, <&rcc STM32_SRC_CKPER I2C1_SEL(1)>;
+	status = "okay";
+};
+
+&adc1 {
+	clocks = <&rcc STM32_CLOCK(AHB1, 5)>, <&rcc STM32_SRC_CKPER ADC12_SEL(1)>;
+	status = "okay";
+};
+
+&spi5 {
+	clocks = <&rcc STM32_CLOCK(APB2, 20)>, <&rcc STM32_SRC_CKPER SPI5_SEL(1)>;
+	status = "okay";
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/boards/devices_on_timg.overlay b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/boards/devices_on_timg.overlay
new file mode 100644
index 00000000000..58e94b9e545
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/boards/devices_on_timg.overlay
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Core and device clock set up
+ *
+ * Warning: This overlay performs configuration from clean sheet.
+ * It is assumed that it is applied after clear_clocks.overlay file.
+ */
+
+&clk_hsi {
+	status = "okay";
+	clock-frequency = <DT_FREQ_M(64)>;
+	hsi-div = <1>;
+};
+
+&cpusw {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;
+	clock-frequency = <DT_FREQ_M(600)>;
+};
+
+&ic1 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <2>;
+};
+
+&ic2 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <3>;
+};
+
+&ic6 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <2>;
+};
+
+&ic11 {
+	status = "okay";
+	pll-src = <1>;
+	ic-div = <3>;
+};
+
+&perck {
+	status = "okay";
+	clocks = <&rcc STM32_SRC_HSI PER_SEL(0)>;
+};
+
+&pll1 {
+	status = "okay";
+	clocks = <&clk_hsi>;
+	div-m = <4>;
+	mul-n = <75>;
+	div-p1 = <1>;
+	div-p2 = <1>;
+};
+
+&rcc {
+	/* ic2, ic6 & ic11 must all be enabled to set ic2 as SYSCLK */
+	clocks = <&ic2>;
+	clock-frequency = <DT_FREQ_M(400)>;
+	ahb-prescaler = <2>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+	apb4-prescaler = <1>;
+	apb5-prescaler = <1>;
+	timg-prescaler = <4>;
+};
+
+&i2c1 {
+	clocks = <&rcc STM32_CLOCK(APB1, 21)>, <&rcc STM32_SRC_CKPER I2C1_SEL(1)>;
+	status = "okay";
+};
+
+&adc1 {
+	clocks = <&rcc STM32_CLOCK(AHB1, 5)>, <&rcc STM32_SRC_TIMG ADC12_SEL(7)>;
+	status = "okay";
+};
+
+&spi5 {
+	clocks = <&rcc STM32_CLOCK(APB2, 20)>, <&rcc STM32_SRC_CKPER SPI5_SEL(1)>;
+	status = "okay";
+};
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/prj.conf b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/prj.conf
new file mode 100644
index 00000000000..9467c292689
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/prj.conf
@@ -0,0 +1 @@
+CONFIG_ZTEST=y
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/src/test_stm32_clock_configuration.c b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/src/test_stm32_clock_configuration.c
new file mode 100644
index 00000000000..75143035798
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/src/test_stm32_clock_configuration.c
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/stm32_clock_control.h>
+#include <zephyr/ztest.h>
+
+/* Not device related, but keep it to ensure core clock config is correct */
+ZTEST(stm32n6_devices_clocks, test_cpuclk_freq)
+{
+	uint32_t cpuclk_freq = HAL_RCC_GetCpuClockFreq();
+
+	zassert_equal(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, cpuclk_freq,
+		      "Expected cpuclk_freq: %d. Actual cupclk_freq: %d",
+		      CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC, cpuclk_freq);
+}
+
+ZTEST_SUITE(stm32n6_devices_clocks, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/src/test_stm32_clock_configuration_adc.c b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/src/test_stm32_clock_configuration_adc.c
new file mode 100644
index 00000000000..dee9f823692
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/src/test_stm32_clock_configuration_adc.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/stm32_clock_control.h>
+#include <zephyr/ztest.h>
+
+ZTEST(stm32n6_devices_clocks, test_adc_clk_config)
+{
+	static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(adc1));
+
+	uint32_t dev_dt_clk_freq, dev_actual_clk_freq, dev_actual_clk_src;
+	enum clock_control_status status;
+	int r;
+
+	status = clock_control_get_status(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+					  (clock_control_subsys_t)&pclken[0]);
+	zassert_true((status == CLOCK_CONTROL_STATUS_OFF),
+		     "ADC1 gating clock should be off initially");
+
+	/* Test clock_on(gating clock) */
+	r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+				(clock_control_subsys_t) &pclken[0]);
+	zassert_true((r == 0), "Could not enable ADC1 gating clock");
+
+	/* Check via HAL as well as via get_status API */
+	zassert_true(__HAL_RCC_ADC12_IS_CLK_ENABLED(), "[HAL] ADC1 gating clock should be on");
+
+	status = clock_control_get_status(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+					  (clock_control_subsys_t)&pclken[0]);
+	zassert_true((status == CLOCK_CONTROL_STATUS_ON),
+		     "[Zephyr] ADC1 gating clock should be on");
+
+	if (DT_NUM_CLOCKS(DT_NODELABEL(adc1)) > 1) {
+		/* Test clock_on(domain_clk) */
+		r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+					    (clock_control_subsys_t) &pclken[1],
+					    NULL);
+		zassert_true((r == 0), "Could not enable ADC1 domain clock");
+
+		/* Test clock source */
+		dev_actual_clk_src = __HAL_RCC_GET_ADC_SOURCE();
+
+		switch (pclken[1].bus) {
+		case STM32_SRC_HCLK1:
+			zassert_equal(dev_actual_clk_src, RCC_ADCCLKSOURCE_HCLK,
+					"Expected ADC1 src: HCLK1 (0x%lx). Actual ADC1 src: 0x%x",
+					RCC_ADCCLKSOURCE_HCLK, dev_actual_clk_src);
+			break;
+		case STM32_SRC_CKPER:
+			zassert_equal(dev_actual_clk_src, RCC_ADCCLKSOURCE_CLKP,
+					"Expected ADC1 src: CKPER (0x%lx). Actual ADC1 src: 0x%x",
+					RCC_ADCCLKSOURCE_CLKP, dev_actual_clk_src);
+			break;
+		case STM32_SRC_IC7:
+			zassert_equal(dev_actual_clk_src, RCC_ADCCLKSOURCE_IC7,
+					"Expected ADC1 src: IC7 (0x%lx). Actual ADC1 src: 0x%x",
+					RCC_ADCCLKSOURCE_IC7, dev_actual_clk_src);
+			break;
+		case STM32_SRC_IC8:
+			zassert_equal(dev_actual_clk_src, RCC_ADCCLKSOURCE_IC8,
+					"Expected ADC1 src: IC8 (0x%lx). Actual ADC1 src: 0x%x",
+					RCC_ADCCLKSOURCE_IC8, dev_actual_clk_src);
+			break;
+		case STM32_SRC_MSI:
+			zassert_equal(dev_actual_clk_src, RCC_ADCCLKSOURCE_MSI,
+					"Expected ADC1 src: MSI (0x%lx). Actual ADC1 src: 0x%x",
+					RCC_ADCCLKSOURCE_MSI, dev_actual_clk_src);
+			break;
+		case STM32_SRC_HSI_DIV:
+			zassert_equal(dev_actual_clk_src, RCC_ADCCLKSOURCE_HSI,
+					"Expected ADC1 src: HSI_DIV (0x%lx). Actual ADC1 src: 0x%x",
+					RCC_ADCCLKSOURCE_HSI, dev_actual_clk_src);
+			break;
+		case STM32_SRC_TIMG:
+			zassert_equal(dev_actual_clk_src, RCC_ADCCLKSOURCE_TIMG,
+					"Expected ADC1 src: TIMG (0x%lx). Actual ADC1 src: 0x%x",
+					RCC_ADCCLKSOURCE_TIMG, dev_actual_clk_src);
+			break;
+		default:
+			zassert_true(0, "Unexpected src clk (%d)", dev_actual_clk_src);
+		}
+
+		/* Test status of the used clk source */
+		status = clock_control_get_status(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+					     (clock_control_subsys_t)&pclken[1]);
+		zassert_true((status == CLOCK_CONTROL_STATUS_ON), "ADC1 clk src must to be on");
+
+		/* Test get_rate(srce clk) */
+		r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+					(clock_control_subsys_t) &pclken[1],
+					&dev_dt_clk_freq);
+		zassert_true((r == 0), "Could not get ADC1 clk srce freq");
+
+		dev_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC);
+		zassert_equal(dev_dt_clk_freq, dev_actual_clk_freq,
+				"Expected DT freq: %d Hz. Actual freq: %d Hz",
+				dev_dt_clk_freq, dev_actual_clk_freq);
+
+	} else {
+		zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(adc1)) == 1), "test config issue");
+		/* No domain clock available, don't check gating clock as for adc there is no
+		 * uniform way to verify via hal.
+		 */
+	}
+
+	/* Test clock_off(reg_clk) */
+	r = clock_control_off(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+				(clock_control_subsys_t) &pclken[0]);
+	zassert_true((r == 0), "Could not disable ADC1 gating clk");
+
+	zassert_true(!__HAL_RCC_ADC12_IS_CLK_ENABLED(), "ADC1 gating clk should be off");
+
+	/* Test clock_off(domain clk) */
+	/* Not supported today */
+}
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/src/test_stm32_clock_configuration_i2c.c b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/src/test_stm32_clock_configuration_i2c.c
new file mode 100644
index 00000000000..e706605e5b4
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/src/test_stm32_clock_configuration_i2c.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/stm32_clock_control.h>
+#include <zephyr/ztest.h>
+
+static void i2c_set_clock(const struct stm32_pclken *clk)
+{
+	uint32_t dev_actual_clk_src, dev_dt_clk_freq, dev_actual_clk_freq;
+	enum clock_control_status status;
+
+	/* Test clock_on(domain_clk) */
+	int r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+					(clock_control_subsys_t) clk, NULL);
+	zassert_true((r == 0), "Could not enable I2C domain clock");
+
+	/* Test clock source */
+	dev_actual_clk_src = __HAL_RCC_GET_I2C1_SOURCE();
+
+	switch (clk->bus) {
+	case STM32_SRC_HSI_DIV:
+		zassert_equal(dev_actual_clk_src, RCC_I2C1CLKSOURCE_HSI,
+				"Expected I2C src: HSI_DIV (0x%lx). Actual I2C src: 0x%x",
+				RCC_I2C1CLKSOURCE_HSI, dev_actual_clk_src);
+		break;
+	case STM32_SRC_MSI:
+		zassert_equal(dev_actual_clk_src, RCC_I2C1CLKSOURCE_MSI,
+				"Expected I2C src: MSI (0x%lx). Actual I2C src: 0x%x",
+				RCC_I2C1CLKSOURCE_MSI, dev_actual_clk_src);
+		break;
+	case STM32_SRC_CKPER:
+		zassert_equal(dev_actual_clk_src, RCC_I2C1CLKSOURCE_CLKP,
+				"Expected I2C src: CKPER (0x%lx). Actual I2C src: 0x%x",
+				RCC_I2C1CLKSOURCE_CLKP, dev_actual_clk_src);
+		break;
+	case STM32_SRC_IC10:
+		zassert_equal(dev_actual_clk_src, RCC_I2C1CLKSOURCE_IC10,
+				"Expected I2C src: IC10 (0x%lx). Actual I2C src: 0x%x",
+				RCC_I2C1CLKSOURCE_IC10, dev_actual_clk_src);
+		break;
+	case STM32_SRC_IC15:
+		zassert_equal(dev_actual_clk_src, RCC_I2C1CLKSOURCE_IC15,
+				"Expected I2C src: IC15 (0x%lx). Actual I2C src: 0x%x",
+				RCC_I2C1CLKSOURCE_IC15, dev_actual_clk_src);
+		break;
+	default:
+		zassert_true(0, "Unexpected domain clk (0x%x)", dev_actual_clk_src);
+		break;
+	}
+
+	/* Test status of the used clk source */
+	status = clock_control_get_status(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+					  (clock_control_subsys_t)clk);
+	zassert_true((status == CLOCK_CONTROL_STATUS_ON), "I2C1 clk src must to be on");
+
+	/* Test get_rate(srce clk) */
+	r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+				   (clock_control_subsys_t) clk,
+				   &dev_dt_clk_freq);
+	zassert_true((r == 0), "Could not get I2C clk srce freq");
+
+	dev_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2C1);
+	zassert_equal(dev_dt_clk_freq, dev_actual_clk_freq,
+			"Expected freq: %d Hz. Actual clk: %d Hz",
+			dev_dt_clk_freq, dev_actual_clk_freq);
+}
+
+ZTEST(stm32n6_devices_clocks, test_i2c_clk_config)
+{
+	static const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(i2c1));
+
+	uint32_t dev_dt_clk_freq, dev_actual_clk_freq;
+	enum clock_control_status status;
+	int r;
+
+	status = clock_control_get_status(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+					  (clock_control_subsys_t)&pclken[0]);
+
+	zassert_true((status == CLOCK_CONTROL_STATUS_OFF),
+		     "I2C Gating clock should be off initially");
+
+	/* Test clock_on(gating clock) */
+	r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+			     (clock_control_subsys_t) &pclken[0]);
+	zassert_true((r == 0), "Could not enable I2C gating clock");
+
+	/* Check via HAL as well as via get_status API */
+	zassert_true(__HAL_RCC_I2C1_IS_CLK_ENABLED(), "[HAL] I2C1 gating clock should be on");
+	status = clock_control_get_status(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+					  (clock_control_subsys_t)&pclken[0]);
+	zassert_true((status == CLOCK_CONTROL_STATUS_ON),
+		     "[Zephyr] I2C1 gating clock should be on");
+
+	if (DT_NUM_CLOCKS(DT_NODELABEL(i2c1)) > 1) {
+		if (DT_NUM_CLOCKS(DT_NODELABEL(i2c1)) > 2) {
+			/* set a dummy clock first, to check if the register is set correctly even
+			 * if not in reset state
+			 */
+			i2c_set_clock(&pclken[2]);
+		}
+		i2c_set_clock(&pclken[1]);
+	} else {
+		zassert_true((DT_NUM_CLOCKS(DT_NODELABEL(i2c1)) == 1), "test config issue");
+		/* No domain clock available, get rate from gating clock */
+
+		/* Test get_rate */
+		r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+					   (clock_control_subsys_t) &pclken[0],
+					   &dev_dt_clk_freq);
+		zassert_true((r == 0), "Could not get I2C clk freq");
+
+		dev_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2C1);
+		zassert_equal(dev_dt_clk_freq, dev_actual_clk_freq,
+				"Expected freq: %d Hz. Actual freq: %d Hz",
+				dev_dt_clk_freq, dev_actual_clk_freq);
+	}
+
+	/* Test clock_off(gating clk) */
+	r = clock_control_off(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+			      (clock_control_subsys_t) &pclken[0]);
+	zassert_true((r == 0), "Could not disable I2C gating clk");
+
+	zassert_true(!__HAL_RCC_I2C1_IS_CLK_ENABLED(), "I2C1 gating clk should be off");
+
+	/* Test clock_off(srce) */
+	/* Not supported today */
+}
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/src/test_stm32_clock_configuration_spi.c b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/src/test_stm32_clock_configuration_spi.c
new file mode 100644
index 00000000000..122af4c0c7c
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/src/test_stm32_clock_configuration_spi.c
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <soc.h>
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/clock_control/stm32_clock_control.h>
+#include <zephyr/ztest.h>
+
+#if (DT_NUM_CLOCKS(DT_NODELABEL(spi5)) != 2)
+#error "SPI node requires 2 clocks: bus clock and kernel clock"
+#endif
+
+ZTEST(stm32n6_devices_clocks, test_spi_clk_config)
+{
+	const struct stm32_pclken pclken[] = STM32_DT_CLOCKS(DT_NODELABEL(spi5));
+	uint32_t spi_actual_domain_clk;
+	uint32_t spi_dt_clk_freq, spi_actual_clk_freq;
+	int r;
+
+	/* Test clock_on(reg_clk) */
+	r = clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+			     (clock_control_subsys_t) &pclken[0]);
+	zassert_true((r == 0), "Could not enable SPI gating clock");
+
+	zassert_true(__HAL_RCC_SPI5_IS_CLK_ENABLED(), "SPI5 gating clock should be on");
+
+	/* Test clock_on(domain source) */
+	r = clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+				    (clock_control_subsys_t) &pclken[1],
+				    NULL);
+	zassert_true((r == 0), "Could not configure SPI domain clk");
+
+	/* Test clk source */
+	spi_actual_domain_clk = __HAL_RCC_GET_SPI5_SOURCE();
+
+	switch (pclken[1].bus) {
+	case STM32_SRC_PCLK2:
+		zassert_equal(spi_actual_domain_clk, RCC_SPI5CLKSOURCE_PCLK2,
+			      "Expected SPI src: PCLK2 (0x%x). Actual: 0x%x",
+			      RCC_SPI5CLKSOURCE_PCLK2, spi_actual_domain_clk);
+		break;
+	case STM32_SRC_CKPER:
+		zassert_equal(spi_actual_domain_clk, RCC_SPI5CLKSOURCE_CLKP,
+			      "Expected SPI src: PERCLK (0x%x). Actual: 0x%x",
+			      RCC_SPI5CLKSOURCE_CLKP, spi_actual_domain_clk);
+		break;
+	case STM32_SRC_IC9:
+		zassert_equal(spi_actual_domain_clk, RCC_SPI5CLKSOURCE_IC9,
+			      "Expected SPI src: IC9 (0x%x). Actual: 0x%x",
+			      RCC_SPI5CLKSOURCE_IC9, spi_actual_domain_clk);
+		break;
+	case STM32_SRC_IC14:
+		zassert_equal(spi_actual_domain_clk, RCC_SPI5CLKSOURCE_IC14,
+			      "Expected SPI src: IC14 (0x%x). Actual: 0x%x",
+			      RCC_SPI5CLKSOURCE_IC14, spi_actual_domain_clk);
+		break;
+	case STM32_SRC_MSI:
+		zassert_equal(spi_actual_domain_clk, RCC_SPI5CLKSOURCE_MSI,
+			      "Expected SPI src: MSI (0x%x). Actual: 0x%x",
+			      RCC_SPI5CLKSOURCE_MSI, spi_actual_domain_clk);
+		break;
+	case STM32_SRC_HSI_DIV:
+		zassert_equal(spi_actual_domain_clk, RCC_SPI5CLKSOURCE_HSI,
+			      "Expected SPI src: HSI_DIV (0x%x). Actual: 0x%x",
+			      RCC_SPI5CLKSOURCE_HSI, spi_actual_domain_clk);
+		break;
+	case STM32_SRC_HSE:
+		zassert_equal(spi_actual_domain_clk, RCC_SPI5CLKSOURCE_HSE,
+			      "Expected SPI src: HSE (0x%x). Actual: 0x%x",
+			      RCC_SPI5CLKSOURCE_HSE, spi_actual_domain_clk);
+		break;
+	default:
+		zassert_true(1, "Unexpected clk src (0x%x)", spi_actual_domain_clk);
+		break;
+	}
+
+	/* Test get_rate(source clk) */
+	r = clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+				   (clock_control_subsys_t) &pclken[1],
+				   &spi_dt_clk_freq);
+	zassert_true((r == 0), "Could not get SPI clk freq");
+
+	spi_actual_clk_freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_SPI5);
+	zassert_equal(spi_dt_clk_freq, spi_actual_clk_freq,
+			"Expected SPI clk: %d. Actual: %d",
+			spi_dt_clk_freq, spi_actual_clk_freq);
+
+	/* Test clock_off(gating clock) */
+	r = clock_control_off(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
+			      (clock_control_subsys_t) &pclken[0]);
+	zassert_true((r == 0), "Could not disable SPI5 reg_clk");
+
+	zassert_true(!__HAL_RCC_SPI5_IS_CLK_ENABLED(), "SPI5 gating clock should be off");
+
+	/* Test clock_off(domain clk) */
+	/* Not supported today */
+}
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/testcase.yaml b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/testcase.yaml
new file mode 100644
index 00000000000..79b51c3d3e1
--- /dev/null
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32n6_devices/testcase.yaml
@@ -0,0 +1,16 @@
+common:
+  timeout: 5
+  platform_allow:
+    - stm32n6570_dk/stm32n657xx/sb
+    - nucleo_n657x0_q/stm32n657xx/sb
+  integration_platforms:
+    - stm32n6570_dk/stm32n657xx/sb
+tests:
+  drivers.clock.stm32_clock_configuration.n6_device.hsi:
+    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/devices_on_hsi.overlay"
+  drivers.clock.stm32_clock_configuration.n6_device.perclk:
+    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/devices_on_perclk.overlay"
+  drivers.clock.stm32_clock_configuration.n6_device.icx:
+    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/devices_on_icx.overlay"
+  drivers.clock.stm32_clock_configuration.n6_device.timg:
+    extra_args: DTC_OVERLAY_FILE="boards/clear_clocks.overlay;boards/devices_on_timg.overlay"
diff --git a/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/testcase.yaml b/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/testcase.yaml
index 6aa2075a594..2a80c2c4a33 100644
--- a/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/testcase.yaml
+++ b/tests/drivers/clock_control/stm32_clock_configuration/stm32wba_core/testcase.yaml
@@ -1,7 +1,6 @@
 common:
   timeout: 5
   platform_allow:
-    - nucleo_wba52cg
     - nucleo_wba55cg
 tests:
   drivers.clock.stm32_clock_configuration.wba.sysclksrc_hsi_16:
diff --git a/tests/drivers/comparator/gpio_loopback/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/comparator/gpio_loopback/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..74ab59e844d
--- /dev/null
+++ b/tests/drivers/comparator/gpio_loopback/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/*
+ * P1.10 looped back to P1.11
+ */
+
+/ {
+	aliases {
+		test-comp = &comp;
+	};
+
+	zephyr,user {
+		test-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
diff --git a/tests/drivers/comparator/gpio_loopback/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/comparator/gpio_loopback/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..74ab59e844d
--- /dev/null
+++ b/tests/drivers/comparator/gpio_loopback/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/*
+ * P1.10 looped back to P1.11
+ */
+
+/ {
+	aliases {
+		test-comp = &comp;
+	};
+
+	zephyr,user {
+		test-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
diff --git a/tests/drivers/comparator/gpio_loopback/boards/ek_ra8d1.overlay b/tests/drivers/comparator/gpio_loopback/boards/ek_ra8d1.overlay
new file mode 100644
index 00000000000..dfae394d3d1
--- /dev/null
+++ b/tests/drivers/comparator/gpio_loopback/boards/ek_ra8d1.overlay
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	aliases {
+		test-comp = &acmphs0;
+	};
+
+	zephyr,user {
+		test-gpios = <&ioport6 0 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&acmphs_global {
+	status = "okay";
+
+	acmphs0 {
+		pinctrl-0 = <&acmphs_ivref0 &acmphs0_ivcmp0>;
+		pinctrl-names = "default";
+		interrupts = <90 12>;
+		interrupt-names = "hs";
+		reference-input-source = "ivref0";
+		compare-input-source = "ivcmp0";
+		noise-filter = <1>;
+		status = "okay";
+	};
+};
diff --git a/tests/drivers/comparator/gpio_loopback/boards/ek_ra8m1.overlay b/tests/drivers/comparator/gpio_loopback/boards/ek_ra8m1.overlay
new file mode 100644
index 00000000000..dfae394d3d1
--- /dev/null
+++ b/tests/drivers/comparator/gpio_loopback/boards/ek_ra8m1.overlay
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	aliases {
+		test-comp = &acmphs0;
+	};
+
+	zephyr,user {
+		test-gpios = <&ioport6 0 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&acmphs_global {
+	status = "okay";
+
+	acmphs0 {
+		pinctrl-0 = <&acmphs_ivref0 &acmphs0_ivcmp0>;
+		pinctrl-names = "default";
+		interrupts = <90 12>;
+		interrupt-names = "hs";
+		reference-input-source = "ivref0";
+		compare-input-source = "ivcmp0";
+		noise-filter = <1>;
+		status = "okay";
+	};
+};
diff --git a/tests/drivers/comparator/gpio_loopback/boards/mck_ra8t1.overlay b/tests/drivers/comparator/gpio_loopback/boards/mck_ra8t1.overlay
new file mode 100644
index 00000000000..e933c71f364
--- /dev/null
+++ b/tests/drivers/comparator/gpio_loopback/boards/mck_ra8t1.overlay
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	aliases {
+		test-comp = &acmphs0;
+	};
+
+	zephyr,user {
+		test-gpios = <&ioport6 6 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&acmphs_global {
+	status = "okay";
+
+	acmphs0 {
+		pinctrl-0 = <&acmphs_ivref0 &acmphs0_ivcmp0>;
+		pinctrl-names = "default";
+		interrupts = <90 12>;
+		interrupt-names = "hs";
+		reference-input-source = "ivref0";
+		compare-input-source = "ivcmp0";
+		noise-filter = <1>;
+		status = "okay";
+	};
+};
diff --git a/tests/drivers/comparator/gpio_loopback/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/comparator/gpio_loopback/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..0761a369b96
--- /dev/null
+++ b/tests/drivers/comparator/gpio_loopback/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/*
+ * P1.10 looped back to P1.11
+ */
+
+/ {
+	aliases {
+		test-comp = &comp;
+	};
+
+	zephyr,user {
+		test-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&gpio1 {
+	status = "okay";
+};
diff --git a/tests/drivers/comparator/gpio_loopback/boards/xg24_dk2601b.overlay b/tests/drivers/comparator/gpio_loopback/boards/xg24_dk2601b.overlay
new file mode 100644
index 00000000000..d4759d66a20
--- /dev/null
+++ b/tests/drivers/comparator/gpio_loopback/boards/xg24_dk2601b.overlay
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/comparator/silabs-acmp.h>
+#include <zephyr/dt-bindings/pinctrl/silabs/xg24-pinctrl.h>
+
+/ {
+	aliases {
+		test-comp = &acmp0;
+	};
+
+	zephyr,user {
+		test-gpios = <&gpioc 3 GPIO_ACTIVE_HIGH>;
+	};
+
+};
+
+&pinctrl {
+	acmp0_default: acmp0_default {
+		group0 {
+			silabs,analog-bus = <ABUS_CDODD0_ACMP0>;
+		};
+	};
+};
+
+&acmp0 {
+	pinctrl-0 = <&acmp0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	hysteresis-mode = "disabled";
+	accuracy-mode = "high";
+	input-range = "full";
+	input-positive = <ACMP_INPUT_PC3>;
+	input-negative = <ACMP_INPUT_VREFDIV1V25>;
+	vref-divider = <63>;
+};
diff --git a/tests/drivers/comparator/gpio_loopback/boards/xg24_rb4187c.overlay b/tests/drivers/comparator/gpio_loopback/boards/xg24_rb4187c.overlay
new file mode 100644
index 00000000000..d4759d66a20
--- /dev/null
+++ b/tests/drivers/comparator/gpio_loopback/boards/xg24_rb4187c.overlay
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/comparator/silabs-acmp.h>
+#include <zephyr/dt-bindings/pinctrl/silabs/xg24-pinctrl.h>
+
+/ {
+	aliases {
+		test-comp = &acmp0;
+	};
+
+	zephyr,user {
+		test-gpios = <&gpioc 3 GPIO_ACTIVE_HIGH>;
+	};
+
+};
+
+&pinctrl {
+	acmp0_default: acmp0_default {
+		group0 {
+			silabs,analog-bus = <ABUS_CDODD0_ACMP0>;
+		};
+	};
+};
+
+&acmp0 {
+	pinctrl-0 = <&acmp0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	hysteresis-mode = "disabled";
+	accuracy-mode = "high";
+	input-range = "full";
+	input-positive = <ACMP_INPUT_PC3>;
+	input-negative = <ACMP_INPUT_VREFDIV1V25>;
+	vref-divider = <63>;
+};
diff --git a/tests/drivers/comparator/gpio_loopback/boards/xg29_rb4412a.overlay b/tests/drivers/comparator/gpio_loopback/boards/xg29_rb4412a.overlay
new file mode 100644
index 00000000000..2930ea78788
--- /dev/null
+++ b/tests/drivers/comparator/gpio_loopback/boards/xg29_rb4412a.overlay
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/comparator/silabs-acmp.h>
+#include <zephyr/dt-bindings/pinctrl/silabs/xg29-pinctrl.h>
+
+/ {
+	aliases {
+		test-comp = &acmp0;
+	};
+
+	zephyr,user {
+		test-gpios = <&gpioc 3 GPIO_ACTIVE_HIGH>;
+	};
+
+};
+
+&pinctrl {
+	acmp0_default: acmp0_default {
+		group0 {
+			silabs,analog-bus = <ABUS_CDODD0_ACMP0>;
+		};
+	};
+};
+
+&acmp0 {
+	pinctrl-0 = <&acmp0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	bias = <0>;
+	hysteresis-mode = "disabled";
+	accuracy-mode = "high";
+	input-range = "full";
+	input-positive = <ACMP_INPUT_PC3>;
+	input-negative = <ACMP_INPUT_VREFDIV1V25>;
+	vref-divider = <63>;
+};
diff --git a/tests/drivers/comparator/gpio_loopback/snippets/nrf_comp/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/comparator/gpio_loopback/snippets/nrf_comp/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..ddcf8d26cad
--- /dev/null
+++ b/tests/drivers/comparator/gpio_loopback/snippets/nrf_comp/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&comp {
+	main-mode = "SE";
+	psel = "AIN4"; /* P1.11 */
+	refsel = "INT_1V2";
+	sp-mode = "HIGH";
+	th-up = <63>;
+	th-down = <59>;
+	isource = "DISABLED";
+	status = "okay";
+};
diff --git a/tests/drivers/comparator/gpio_loopback/snippets/nrf_comp/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/comparator/gpio_loopback/snippets/nrf_comp/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..ddcf8d26cad
--- /dev/null
+++ b/tests/drivers/comparator/gpio_loopback/snippets/nrf_comp/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&comp {
+	main-mode = "SE";
+	psel = "AIN4"; /* P1.11 */
+	refsel = "INT_1V2";
+	sp-mode = "HIGH";
+	th-up = <63>;
+	th-down = <59>;
+	isource = "DISABLED";
+	status = "okay";
+};
diff --git a/tests/drivers/comparator/gpio_loopback/snippets/nrf_comp/snippet.yml b/tests/drivers/comparator/gpio_loopback/snippets/nrf_comp/snippet.yml
index e030c0e5543..79fffefe7f4 100644
--- a/tests/drivers/comparator/gpio_loopback/snippets/nrf_comp/snippet.yml
+++ b/tests/drivers/comparator/gpio_loopback/snippets/nrf_comp/snippet.yml
@@ -10,6 +10,9 @@ boards:
   nrf54l15dk/nrf54l15/cpuapp:
     append:
       EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15dk_nrf54l15_cpuapp.overlay
+  ophelia4ev/nrf54l15/cpuapp:
+    append:
+      EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15dk_nrf54l15_cpuapp.overlay
   nrf5340dk/nrf5340/cpuapp:
     append:
       EXTRA_DTC_OVERLAY_FILE: boards/nrf5340dk_nrf5340_cpuapp.overlay
diff --git a/tests/drivers/comparator/gpio_loopback/snippets/nrf_lpcomp/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/comparator/gpio_loopback/snippets/nrf_lpcomp/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..58e055a0240
--- /dev/null
+++ b/tests/drivers/comparator/gpio_loopback/snippets/nrf_lpcomp/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&comp {
+	compatible = "nordic,nrf-lpcomp";
+	psel = "AIN4"; /* P1.11 */
+	refsel = "VDD_4_8";
+	status = "okay";
+};
diff --git a/tests/drivers/comparator/gpio_loopback/snippets/nrf_lpcomp/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/comparator/gpio_loopback/snippets/nrf_lpcomp/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..58e055a0240
--- /dev/null
+++ b/tests/drivers/comparator/gpio_loopback/snippets/nrf_lpcomp/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&comp {
+	compatible = "nordic,nrf-lpcomp";
+	psel = "AIN4"; /* P1.11 */
+	refsel = "VDD_4_8";
+	status = "okay";
+};
diff --git a/tests/drivers/comparator/gpio_loopback/snippets/nrf_lpcomp/snippet.yml b/tests/drivers/comparator/gpio_loopback/snippets/nrf_lpcomp/snippet.yml
index 70ff2a7e314..82a32cb517e 100644
--- a/tests/drivers/comparator/gpio_loopback/snippets/nrf_lpcomp/snippet.yml
+++ b/tests/drivers/comparator/gpio_loopback/snippets/nrf_lpcomp/snippet.yml
@@ -10,6 +10,9 @@ boards:
   nrf54l15dk/nrf54l15/cpuapp:
     append:
       EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15dk_nrf54l15_cpuapp.overlay
+  ophelia4ev/nrf54l15/cpuapp:
+    append:
+      EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15dk_nrf54l15_cpuapp.overlay
   nrf5340dk/nrf5340/cpuapp:
     append:
       EXTRA_DTC_OVERLAY_FILE: boards/nrf5340dk_nrf5340_cpuapp.overlay
diff --git a/tests/drivers/comparator/gpio_loopback/testcase.yaml b/tests/drivers/comparator/gpio_loopback/testcase.yaml
index beb5cd39276..cfeeabe3a69 100644
--- a/tests/drivers/comparator/gpio_loopback/testcase.yaml
+++ b/tests/drivers/comparator/gpio_loopback/testcase.yaml
@@ -8,6 +8,11 @@ common:
     - drivers
     - comparator
 tests:
+  drivers.comparator.gpio_loopback.silabs_acmp:
+    platform_allow:
+      - xg24_dk2601b
+      - xg24_rb4187c
+      - xg29_rb4412a
   drivers.comparator.gpio_loopback.mcux_acmp:
     platform_allow:
       - frdm_ke15z
@@ -18,6 +23,7 @@ tests:
       - nrf54h20dk/nrf54h20/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf5340dk/nrf5340/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
   drivers.comparator.gpio_loopback.nrf_lpcomp:
     extra_args:
       - SNIPPET="gpio_loopback_nrf_lpcomp"
@@ -25,3 +31,4 @@ tests:
       - nrf54h20dk/nrf54h20/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf5340dk/nrf5340/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
diff --git a/tests/drivers/console/line_splitting/line_splitting.robot b/tests/drivers/console/line_splitting/line_splitting.robot
index 6947d6d0bf4..17f95063e74 100644
--- a/tests/drivers/console/line_splitting/line_splitting.robot
+++ b/tests/drivers/console/line_splitting/line_splitting.robot
@@ -6,7 +6,6 @@ Resource                      ${KEYWORDS}
 *** Test Cases ***
 Should Split Lines
     Prepare Machine
-    Start Emulation
     Wait For Next Line On Uart
     Write Line To Uart          \rabc\nd\n               waitForEcho=false
     Wait For Line On Uart       getline: abc;
diff --git a/tests/drivers/console_switching/src/main.c b/tests/drivers/console_switching/src/main.c
index 95cde150c9b..b69ee69fba7 100644
--- a/tests/drivers/console_switching/src/main.c
+++ b/tests/drivers/console_switching/src/main.c
@@ -13,9 +13,8 @@
 #define BUF_SIZE 32
 
 /* array of const struct device* */
-#define PHANDLE_TO_DEVICE(node_id, prop, idx) DEVICE_DT_GET(DT_PHANDLE_BY_IDX(node_id, prop, idx))
 static const struct device *devs[] = {
-	DT_FOREACH_PROP_ELEM_SEP(DT_NODELABEL(devmux0), devices, PHANDLE_TO_DEVICE, (,))};
+	DT_FOREACH_PROP_ELEM_SEP(DT_NODELABEL(devmux0), devices, DEVICE_DT_GET_BY_IDX, (,))};
 
 /* array of names, e.g. "euart0" */
 #define PHANDLE_TO_NAME(node_id, prop, idx) DT_NODE_FULL_NAME(DT_PHANDLE_BY_IDX(node_id, prop, idx))
diff --git a/tests/drivers/counter/counter_basic_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay b/tests/drivers/counter/counter_basic_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay
new file mode 100644
index 00000000000..2170eac1179
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15_dvk_nrf54l15_cpuapp.overlay"
diff --git a/tests/drivers/counter/counter_basic_api/boards/bl54l15_dvk_nrf54l15_common.dtsi b/tests/drivers/counter/counter_basic_api/boards/bl54l15_dvk_nrf54l15_common.dtsi
new file mode 100644
index 00000000000..9f565a2c810
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/boards/bl54l15_dvk_nrf54l15_common.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&timer00 {
+	prescaler = <6>;
+	status = "okay";
+};
+
+&timer10 {
+	prescaler = <4>;
+	status = "okay";
+};
+
+&timer20 {
+	prescaler = <4>;
+	status = "okay";
+};
+
+&timer21 {
+	prescaler = <4>;
+	status = "okay";
+};
+
+&timer22 {
+	prescaler = <4>;
+	status = "okay";
+};
+
+&timer23 {
+	prescaler = <4>;
+	status = "okay";
+};
+
+&timer24 {
+	prescaler = <4>;
+	status = "okay";
+};
diff --git a/tests/drivers/counter/counter_basic_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/counter/counter_basic_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..7e4af68ce5b
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15_dvk_nrf54l15_common.dtsi"
diff --git a/tests/drivers/counter/counter_basic_api/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay b/tests/drivers/counter/counter_basic_api/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..7e4af68ce5b
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15_dvk_nrf54l15_common.dtsi"
diff --git a/tests/drivers/counter/counter_basic_api/boards/bl54l15u_dvk_nrf54l15_common.dtsi b/tests/drivers/counter/counter_basic_api/boards/bl54l15u_dvk_nrf54l15_common.dtsi
new file mode 100644
index 00000000000..9f565a2c810
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/boards/bl54l15u_dvk_nrf54l15_common.dtsi
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&timer00 {
+	prescaler = <6>;
+	status = "okay";
+};
+
+&timer10 {
+	prescaler = <4>;
+	status = "okay";
+};
+
+&timer20 {
+	prescaler = <4>;
+	status = "okay";
+};
+
+&timer21 {
+	prescaler = <4>;
+	status = "okay";
+};
+
+&timer22 {
+	prescaler = <4>;
+	status = "okay";
+};
+
+&timer23 {
+	prescaler = <4>;
+	status = "okay";
+};
+
+&timer24 {
+	prescaler = <4>;
+	status = "okay";
+};
diff --git a/tests/drivers/counter/counter_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/counter/counter_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..1cb065074ed
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15u_dvk_nrf54l15_common.dtsi"
diff --git a/tests/drivers/counter/counter_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay b/tests/drivers/counter/counter_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..1cb065074ed
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15u_dvk_nrf54l15_common.dtsi"
diff --git a/tests/drivers/counter/counter_basic_api/boards/imx95_evk_mimx9596_a55.overlay b/tests/drivers/counter/counter_basic_api/boards/imx95_evk_mimx9596_a55.overlay
new file mode 100644
index 00000000000..e20242c8b05
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/boards/imx95_evk_mimx9596_a55.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&tpm2 {
+	status = "okay";
+};
diff --git a/tests/drivers/counter/counter_basic_api/boards/it82xx2_evb.overlay b/tests/drivers/counter/counter_basic_api/boards/it82xx2_evb.overlay
new file mode 100644
index 00000000000..53d7711c6b1
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/boards/it82xx2_evb.overlay
@@ -0,0 +1,9 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 ITE Corporation.
+ */
+
+&counter0 {
+	status = "okay";
+};
diff --git a/tests/drivers/counter/counter_basic_api/boards/it8xxx2_evb.overlay b/tests/drivers/counter/counter_basic_api/boards/it8xxx2_evb.overlay
new file mode 100644
index 00000000000..53d7711c6b1
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/boards/it8xxx2_evb.overlay
@@ -0,0 +1,9 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 ITE Corporation.
+ */
+
+&counter0 {
+	status = "okay";
+};
diff --git a/tests/drivers/counter/counter_basic_api/boards/max78000evkit_max78000_m4.overlay b/tests/drivers/counter/counter_basic_api/boards/max78000evkit_max78000_m4.overlay
new file mode 100644
index 00000000000..f31087d1023
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/boards/max78000evkit_max78000_m4.overlay
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&timer0 {
+	status = "okay";
+	prescaler = <2>;
+	counter {
+		status = "okay";
+	};
+};
+
+&timer1 {
+	status = "okay";
+	prescaler = <2>;
+	counter {
+		status = "okay";
+	};
+};
+
+&timer2 {
+	status = "okay";
+	prescaler = <2>;
+	counter {
+		status = "okay";
+	};
+};
+
+&timer3 {
+	status = "okay";
+	prescaler = <2>;
+	counter {
+		status = "okay";
+	};
+};
+
+&lptimer0 {
+	status = "okay";
+	clock-source = <ADI_MAX32_PRPH_CLK_SRC_ERTCO>;
+	counter {
+		status = "okay";
+	};
+};
+
+&lptimer1 {
+	status = "okay";
+	clock-source = <ADI_MAX32_PRPH_CLK_SRC_INRO>;
+	counter {
+		status = "okay";
+	};
+};
+
+&clk_ertco {
+	status = "okay";
+};
+
+&clk_inro {
+	status = "okay";
+};
diff --git a/tests/drivers/counter/counter_basic_api/boards/max78000fthr_max78000_m4.overlay b/tests/drivers/counter/counter_basic_api/boards/max78000fthr_max78000_m4.overlay
new file mode 100644
index 00000000000..f31087d1023
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/boards/max78000fthr_max78000_m4.overlay
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&timer0 {
+	status = "okay";
+	prescaler = <2>;
+	counter {
+		status = "okay";
+	};
+};
+
+&timer1 {
+	status = "okay";
+	prescaler = <2>;
+	counter {
+		status = "okay";
+	};
+};
+
+&timer2 {
+	status = "okay";
+	prescaler = <2>;
+	counter {
+		status = "okay";
+	};
+};
+
+&timer3 {
+	status = "okay";
+	prescaler = <2>;
+	counter {
+		status = "okay";
+	};
+};
+
+&lptimer0 {
+	status = "okay";
+	clock-source = <ADI_MAX32_PRPH_CLK_SRC_ERTCO>;
+	counter {
+		status = "okay";
+	};
+};
+
+&lptimer1 {
+	status = "okay";
+	clock-source = <ADI_MAX32_PRPH_CLK_SRC_INRO>;
+	counter {
+		status = "okay";
+	};
+};
+
+&clk_ertco {
+	status = "okay";
+};
+
+&clk_inro {
+	status = "okay";
+};
diff --git a/tests/drivers/counter/counter_basic_api/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay b/tests/drivers/counter/counter_basic_api/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay
index 8a3cee91a43..07d27b00109 100644
--- a/tests/drivers/counter/counter_basic_api/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay
+++ b/tests/drivers/counter/counter_basic_api/boards/mimxrt1060_evk_mimxrt1062_qspi.overlay
@@ -20,6 +20,6 @@
 
 &qtmr1_timer0 {
 	status = "okay";
-	primary_source = "kQTMR_ClockDivide_128";
+	primary-source = "kQTMR_ClockDivide_128";
 	mode = "kQTMR_PriSrcRiseEdge";
 };
diff --git a/tests/drivers/counter/counter_basic_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/tests/drivers/counter/counter_basic_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
new file mode 100644
index 00000000000..07d27b00109
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pit0_channel0 {
+	status = "okay";
+};
+
+&pit0_channel1 {
+	status = "okay";
+};
+
+/* channel 2 disabled to test disabled channel not breaking things */
+
+&pit0_channel3 {
+	status = "okay";
+};
+
+&qtmr1_timer0 {
+	status = "okay";
+	primary-source = "kQTMR_ClockDivide_128";
+	mode = "kQTMR_PriSrcRiseEdge";
+};
diff --git a/tests/drivers/counter/counter_basic_api/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay b/tests/drivers/counter/counter_basic_api/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
index e494bb84055..efc14f7acc8 100644
--- a/tests/drivers/counter/counter_basic_api/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
+++ b/tests/drivers/counter/counter_basic_api/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
@@ -6,6 +6,6 @@
 
 &qtmr1_timer0 {
 	status = "okay";
-	primary_source = "kQTMR_ClockDivide_128";
+	primary-source = "kQTMR_ClockDivide_128";
 	mode = "kQTMR_PriSrcRiseEdge";
 };
diff --git a/tests/drivers/counter/counter_basic_api/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay b/tests/drivers/counter/counter_basic_api/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
index e494bb84055..efc14f7acc8 100644
--- a/tests/drivers/counter/counter_basic_api/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
+++ b/tests/drivers/counter/counter_basic_api/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
@@ -6,6 +6,6 @@
 
 &qtmr1_timer0 {
 	status = "okay";
-	primary_source = "kQTMR_ClockDivide_128";
+	primary-source = "kQTMR_ClockDivide_128";
 	mode = "kQTMR_PriSrcRiseEdge";
 };
diff --git a/tests/drivers/counter/counter_basic_api/boards/nucleo_c071rb.overlay b/tests/drivers/counter/counter_basic_api/boards/nucleo_c071rb.overlay
new file mode 100644
index 00000000000..d8411a266fd
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/boards/nucleo_c071rb.overlay
@@ -0,0 +1,34 @@
+&timers1 {
+	st,prescaler = <79>;
+	counter {
+		status = "okay";
+	};
+};
+
+&timers2 {
+	st,prescaler = <79>;
+	counter {
+		status = "okay";
+	};
+};
+
+&timers3 {
+	st,prescaler = <79>;
+	counter {
+		status = "okay";
+	};
+};
+
+&timers16 {
+	st,prescaler = <79>;
+	counter {
+		status = "okay";
+	};
+};
+
+&timers17 {
+	st,prescaler = <79>;
+	counter {
+		status = "okay";
+	};
+};
diff --git a/tests/drivers/counter/counter_basic_api/boards/nucleo_wba52cg.overlay b/tests/drivers/counter/counter_basic_api/boards/nucleo_wba55cg.overlay
similarity index 100%
rename from tests/drivers/counter/counter_basic_api/boards/nucleo_wba52cg.overlay
rename to tests/drivers/counter/counter_basic_api/boards/nucleo_wba55cg.overlay
diff --git a/tests/drivers/counter/counter_basic_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/counter/counter_basic_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..6683b77837a
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include "nrf54l15dk_nrf54l15_common.dtsi"
diff --git a/tests/drivers/counter/counter_basic_api/boards/ophelia4ev_nrf54l15_cpuflpr.overlay b/tests/drivers/counter/counter_basic_api/boards/ophelia4ev_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..6683b77837a
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/boards/ophelia4ev_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include "nrf54l15dk_nrf54l15_common.dtsi"
diff --git a/tests/drivers/counter/counter_basic_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/tests/drivers/counter/counter_basic_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
new file mode 100644
index 00000000000..1e43767052f
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&gtm0 {
+	status = "okay";
+
+	counter {
+		status = "okay";
+	};
+};
+
+&gtm1 {
+	status = "okay";
+
+	counter {
+		status = "okay";
+	};
+};
+
+&gtm2 {
+	status = "okay";
+
+	counter {
+		status = "okay";
+	};
+};
+
+&gtm3 {
+	status = "okay";
+
+	counter {
+		status = "okay";
+	};
+};
+
+&gtm4 {
+	status = "okay";
+
+	counter {
+		status = "okay";
+	};
+};
+
+&gtm5 {
+	status = "okay";
+
+	counter {
+		status = "okay";
+	};
+};
+
+&gtm6 {
+	status = "okay";
+
+	counter {
+		status = "okay";
+	};
+};
+
+&gtm7 {
+	status = "okay";
+
+	counter {
+		status = "okay";
+	};
+};
diff --git a/tests/drivers/counter/counter_basic_api/socs/esp32c3_usb.overlay b/tests/drivers/counter/counter_basic_api/socs/esp32c3_usb.overlay
new file mode 100644
index 00000000000..b5ba7f57398
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/socs/esp32c3_usb.overlay
@@ -0,0 +1,7 @@
+&timer0 {
+	status = "okay";
+};
+
+&rtc {
+	slow-clk-src = <ESP32_RTC_SLOW_CLK_SRC_RC_FAST_D256>;
+};
diff --git a/tests/drivers/counter/counter_basic_api/socs/esp32c6.overlay b/tests/drivers/counter/counter_basic_api/socs/esp32c6_hpcore.overlay
similarity index 100%
rename from tests/drivers/counter/counter_basic_api/socs/esp32c6.overlay
rename to tests/drivers/counter/counter_basic_api/socs/esp32c6_hpcore.overlay
diff --git a/tests/drivers/counter/counter_basic_api/socs/rp2350a_m33.overlay b/tests/drivers/counter/counter_basic_api/socs/rp2350a_m33.overlay
new file mode 100644
index 00000000000..a8cb086263c
--- /dev/null
+++ b/tests/drivers/counter/counter_basic_api/socs/rp2350a_m33.overlay
@@ -0,0 +1,7 @@
+&timer0 {
+	status = "okay";
+};
+
+&timer1 {
+	status = "okay";
+};
diff --git a/tests/drivers/counter/counter_basic_api/src/test_counter.c b/tests/drivers/counter/counter_basic_api/src/test_counter.c
index 6ae81b0e977..62bf7602e2d 100644
--- a/tests/drivers/counter/counter_basic_api/src/test_counter.c
+++ b/tests/drivers/counter/counter_basic_api/src/test_counter.c
@@ -51,7 +51,7 @@ static const struct device *const devices[] = {
 #undef DT_DRV_COMPAT
 #undef STM32_COUNTER_DEV
 #endif
-#ifdef CONFIG_COUNTER_NATIVE_POSIX
+#ifdef CONFIG_COUNTER_NATIVE_SIM
 	DEVICE_DT_GET(DT_NODELABEL(counter0)),
 #endif
 #ifdef CONFIG_COUNTER_INFINEON_CAT1
@@ -126,6 +126,12 @@ static const struct device *const devices[] = {
 #ifdef CONFIG_COUNTER_MCUX_LPTMR
 	DEVS_FOR_DT_COMPAT(nxp_lptmr)
 #endif
+#ifdef CONFIG_COUNTER_RENESAS_RZ_GTM
+	DEVS_FOR_DT_COMPAT(renesas_rz_gtm_counter)
+#endif
+#ifdef CONFIG_COUNTER_ITE_IT8XXX2
+	DEVS_FOR_DT_COMPAT(ite_it8xxx2_counter)
+#endif
 };
 
 static const struct device *const period_devs[] = {
@@ -879,7 +885,7 @@ static bool late_detection_capable(const struct device *dev)
 	int err = counter_set_guard_period(dev, guard,
 					COUNTER_GUARD_PERIOD_LATE_TO_SET);
 
-	if (err == -ENOTSUP) {
+	if (err == -ENOSYS) {
 		return false;
 	}
 
@@ -1083,7 +1089,7 @@ static bool reliable_cancel_capable(const struct device *dev)
 		return true;
 	}
 #endif
-#ifdef CONFIG_COUNTER_NATIVE_POSIX
+#ifdef CONFIG_COUNTER_NATIVE_SIM
 	if (dev == DEVICE_DT_GET(DT_NODELABEL(counter0))) {
 		return true;
 	}
@@ -1102,6 +1108,11 @@ static bool reliable_cancel_capable(const struct device *dev)
 	if (single_channel_alarm_capable(dev)) {
 		return true;
 	}
+#endif
+#ifdef CONFIG_COUNTER_RENESAS_RZ_GTM
+	if (single_channel_alarm_capable(dev)) {
+		return true;
+	}
 #endif
 	return false;
 }
diff --git a/tests/drivers/counter/counter_basic_api/testcase.yaml b/tests/drivers/counter/counter_basic_api/testcase.yaml
index 053f53a4924..b6e3d69453d 100644
--- a/tests/drivers/counter/counter_basic_api/testcase.yaml
+++ b/tests/drivers/counter/counter_basic_api/testcase.yaml
@@ -14,7 +14,6 @@ tests:
     depends_on: counter
     platform_allow:
       - nrf52840dk/nrf52840
-      - nrf52_bsim
     timeout: 400
     extra_configs:
       - CONFIG_ZERO_LATENCY_IRQS=y
@@ -27,7 +26,7 @@ tests:
     depends_on: counter
     platform_allow:
       - nucleo_f429zi
-      - nucleo_wba52cg
+      - nucleo_wba55cg
       - google_dragonclaw
     timeout: 600
     extra_configs:
diff --git a/tests/drivers/dac/dac_api/Kconfig b/tests/drivers/dac/dac_api/Kconfig
new file mode 100644
index 00000000000..c0bff06f70f
--- /dev/null
+++ b/tests/drivers/dac/dac_api/Kconfig
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+mainmenu "DAC API test"
+
+source "Kconfig.zephyr"
+
+config DAC_BUFFER_NOT_SUPPORT
+	bool "DAC on board/SoC does not support output buffer mode"
+	help
+	  If this config is turned on, the test will run with no output buffer enabled
diff --git a/tests/drivers/dac/dac_api/boards/ek_ra4l1.conf b/tests/drivers/dac/dac_api/boards/ek_ra4l1.conf
new file mode 100644
index 00000000000..3f37d94739f
--- /dev/null
+++ b/tests/drivers/dac/dac_api/boards/ek_ra4l1.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DAC_BUFFER_NOT_SUPPORT=y
diff --git a/tests/drivers/dac/dac_api/boards/ek_ra4m1.conf b/tests/drivers/dac/dac_api/boards/ek_ra4m1.conf
new file mode 100644
index 00000000000..3f37d94739f
--- /dev/null
+++ b/tests/drivers/dac/dac_api/boards/ek_ra4m1.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DAC_BUFFER_NOT_SUPPORT=y
diff --git a/tests/drivers/dac/dac_api/boards/ek_ra4w1.conf b/tests/drivers/dac/dac_api/boards/ek_ra4w1.conf
new file mode 100644
index 00000000000..3f37d94739f
--- /dev/null
+++ b/tests/drivers/dac/dac_api/boards/ek_ra4w1.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DAC_BUFFER_NOT_SUPPORT=y
diff --git a/tests/drivers/dac/dac_api/src/test_dac.c b/tests/drivers/dac/dac_api/src/test_dac.c
index d79c884e381..f2f0a627f69 100644
--- a/tests/drivers/dac/dac_api/src/test_dac.c
+++ b/tests/drivers/dac/dac_api/src/test_dac.c
@@ -13,6 +13,7 @@
 	defined(CONFIG_BOARD_NUCLEO_F207ZG) || \
 	defined(CONFIG_BOARD_STM32F3_DISCO) || \
 	defined(CONFIG_BOARD_NUCLEO_F429ZI) || \
+	defined(CONFIG_BOARD_NUCLEO_F439ZI) || \
 	defined(CONFIG_BOARD_NUCLEO_F746ZG) || \
 	defined(CONFIG_BOARD_NUCLEO_F767ZI) || \
 	defined(CONFIG_BOARD_NUCLEO_F722ZE) || \
@@ -48,6 +49,7 @@
 	defined(CONFIG_BOARD_FRDM_K64F) || \
 	defined(CONFIG_BOARD_FRDM_K22F) || \
 	defined(CONFIG_BOARD_FRDM_MCXN947) || \
+	defined(CONFIG_BOARD_MCX_N9XX_EVK) || \
 	defined(CONFIG_BOARD_FRDM_MCXA156) || \
 	defined(CONFIG_BOARD_SEEEDUINO_XIAO) || \
 	defined(CONFIG_BOARD_ARDUINO_MKRZERO) || \
@@ -85,8 +87,8 @@
 #define DAC_RESOLUTION		12
 #define DAC_CHANNEL_ID		0
 
-#elif defined(CONFIG_BOARD_SAM_E70_XPLAINED) || \
-	defined(CONFIG_BOARD_SAM_V71_XULT)
+#elif defined(CONFIG_SOC_FAMILY_ATMEL_SAM) && \
+	!defined(CONFIG_SOC_SERIES_SAM4L)
 
 #define DAC_DEVICE_NODE		DT_NODELABEL(dacc)
 #define DAC_RESOLUTION		12
@@ -99,14 +101,24 @@
 #define DAC_RESOLUTION		10
 #define DAC_CHANNEL_ID		0
 
+#elif DT_HAS_COMPAT_STATUS_OKAY(renesas_ra_dac)
+
+#define DAC_DEVICE_NODE DT_NODELABEL(dac0)
+#define DAC_RESOLUTION  12
+#define DAC_CHANNEL_ID  0
+
 #else
 #error "Unsupported board."
 #endif
 
 static const struct dac_channel_cfg dac_ch_cfg = {
-	.channel_id  = DAC_CHANNEL_ID,
-	.resolution  = DAC_RESOLUTION,
-	.buffered = true
+	.channel_id = DAC_CHANNEL_ID,
+	.resolution = DAC_RESOLUTION,
+#if defined(CONFIG_DAC_BUFFER_NOT_SUPPORT)
+	.buffered = false,
+#else
+	.buffered = true,
+#endif /* CONFIG_DAC_BUFFER_NOT_SUPPORT */
 };
 
 const struct device *get_dac_device(void)
diff --git a/tests/drivers/dac/dac_loopback/Kconfig b/tests/drivers/dac/dac_loopback/Kconfig
new file mode 100644
index 00000000000..531b0f123ee
--- /dev/null
+++ b/tests/drivers/dac/dac_loopback/Kconfig
@@ -0,0 +1,11 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+mainmenu "DAC Loopback test"
+
+source "Kconfig.zephyr"
+
+config DAC_BUFFER_NOT_SUPPORT
+	bool "DAC on board/SoC does not support output buffer mode"
+	help
+	  If this config is turned on, the test will run with no output buffer enabled
diff --git a/tests/drivers/dac/dac_loopback/boards/ek_ra4l1.conf b/tests/drivers/dac/dac_loopback/boards/ek_ra4l1.conf
new file mode 100644
index 00000000000..3f37d94739f
--- /dev/null
+++ b/tests/drivers/dac/dac_loopback/boards/ek_ra4l1.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DAC_BUFFER_NOT_SUPPORT=y
diff --git a/tests/drivers/dac/dac_loopback/boards/ek_ra4m1.conf b/tests/drivers/dac/dac_loopback/boards/ek_ra4m1.conf
new file mode 100644
index 00000000000..3f37d94739f
--- /dev/null
+++ b/tests/drivers/dac/dac_loopback/boards/ek_ra4m1.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DAC_BUFFER_NOT_SUPPORT=y
diff --git a/tests/drivers/dac/dac_loopback/boards/ek_ra4w1.conf b/tests/drivers/dac/dac_loopback/boards/ek_ra4w1.conf
new file mode 100644
index 00000000000..3f37d94739f
--- /dev/null
+++ b/tests/drivers/dac/dac_loopback/boards/ek_ra4w1.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DAC_BUFFER_NOT_SUPPORT=y
diff --git a/tests/drivers/dac/dac_loopback/src/test_dac.c b/tests/drivers/dac/dac_loopback/src/test_dac.c
index 55fb22b44ae..57190003a70 100644
--- a/tests/drivers/dac/dac_loopback/src/test_dac.c
+++ b/tests/drivers/dac/dac_loopback/src/test_dac.c
@@ -165,6 +165,25 @@
 #define ADC_CHANNEL_ID		1
 #define ADC_1ST_CHANNEL_INPUT	NRF_SAADC_INPUT_AIN1
 
+#elif DT_HAS_COMPAT_STATUS_OKAY(renesas_ra_dac)
+
+#define DAC_DEVICE_NODE DT_NODELABEL(dac0)
+#define DAC_RESOLUTION  12
+#define DAC_CHANNEL_ID  0
+
+#define ADC_DEVICE_NODE      DT_NODELABEL(adc0)
+#define ADC_RESOLUTION       12
+#define ADC_GAIN             ADC_GAIN_1
+#define ADC_REFERENCE        ADC_REF_INTERNAL
+#define ADC_ACQUISITION_TIME ADC_ACQ_TIME_DEFAULT
+#if defined(CONFIG_BOARD_EK_RA4L1)
+#define ADC_CHANNEL_ID 1
+#elif defined(CONFIG_BOARD_EK_RA4W1)
+#define ADC_CHANNEL_ID 4
+#else
+#define ADC_CHANNEL_ID 0
+#endif
+
 #else
 #error "Unsupported board."
 #endif
@@ -172,7 +191,11 @@
 static const struct dac_channel_cfg dac_ch_cfg = {
 	.channel_id = DAC_CHANNEL_ID,
 	.resolution = DAC_RESOLUTION,
-	.buffered = true
+#if defined(CONFIG_DAC_BUFFER_NOT_SUPPORT)
+	.buffered = false,
+#else
+	.buffered = true,
+#endif /* CONFIG_DAC_BUFFER_NOT_SUPPORT */
 };
 
 static const struct adc_channel_cfg adc_ch_cfg = {
diff --git a/tests/drivers/disk/disk_access/testcase.yaml b/tests/drivers/disk/disk_access/testcase.yaml
index 10c1f5bc491..fea3bd706bf 100644
--- a/tests/drivers/disk/disk_access/testcase.yaml
+++ b/tests/drivers/disk/disk_access/testcase.yaml
@@ -8,9 +8,10 @@ tests:
     filter: CONFIG_SDHC
     extra_configs:
       - CONFIG_DISK_DRIVER_SDMMC=y
+      - platform:mimxrt1060_evk@C/mimxrt1062/qspi:CONFIG_MAIN_STACK_SIZE=2048
     tags: mcux
     integration_platforms:
-      - mimxrt1060_evk/mimxrt1062/qspi
+      - mimxrt1060_evk@C/mimxrt1062/qspi
       - mimxrt1050_evk/mimxrt1052/hyperflash
       - mimxrt1064_evk
   drivers.disk.ram:
diff --git a/tests/drivers/disk/disk_performance/boards/max32666fthr_max32666_cpu0.conf b/tests/drivers/disk/disk_performance/boards/max32666fthr_max32666_cpu0.conf
new file mode 100644
index 00000000000..ecf4f8f9d4b
--- /dev/null
+++ b/tests/drivers/disk/disk_performance/boards/max32666fthr_max32666_cpu0.conf
@@ -0,0 +1,2 @@
+CONFIG_SDMMC_SUBSYS=y
+CONFIG_SDHC=y
diff --git a/samples/subsys/nvs/boards/nucleo_f091rc.conf b/tests/drivers/disk/disk_performance/boards/mimxrt1060_evk.conf
similarity index 100%
rename from samples/subsys/nvs/boards/nucleo_f091rc.conf
rename to tests/drivers/disk/disk_performance/boards/mimxrt1060_evk.conf
diff --git a/tests/drivers/disk/disk_performance/boards/mimxrt1060_evk.overlay b/tests/drivers/disk/disk_performance/boards/mimxrt1060_evk.overlay
new file mode 100644
index 00000000000..df4126425a1
--- /dev/null
+++ b/tests/drivers/disk/disk_performance/boards/mimxrt1060_evk.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Disable GPT timer and use systick for better timer accuracy
+ */
+&systick {
+	status = "okay";
+};
+
+&gpt_hw_timer {
+	status = "disabled";
+};
diff --git a/samples/subsys/nvs/boards/nucleo_g071rb.conf b/tests/drivers/disk/disk_performance/boards/mimxrt1060_evk_mimxrt1062_qspi_C.conf
similarity index 100%
rename from samples/subsys/nvs/boards/nucleo_g071rb.conf
rename to tests/drivers/disk/disk_performance/boards/mimxrt1060_evk_mimxrt1062_qspi_C.conf
diff --git a/tests/drivers/disk/disk_performance/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/tests/drivers/disk/disk_performance/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
new file mode 100644
index 00000000000..df4126425a1
--- /dev/null
+++ b/tests/drivers/disk/disk_performance/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025, NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Disable GPT timer and use systick for better timer accuracy
+ */
+&systick {
+	status = "okay";
+};
+
+&gpt_hw_timer {
+	status = "disabled";
+};
diff --git a/tests/drivers/display/display_read_write/src/main.c b/tests/drivers/display/display_read_write/src/main.c
index e44b49a4beb..cbb64bb9675 100644
--- a/tests/drivers/display/display_read_write/src/main.c
+++ b/tests/drivers/display/display_read_write/src/main.c
@@ -22,7 +22,8 @@ static uint8_t disp_buffer[DT_PROP(DT_CHOSEN(zephyr_display), width) *
 	__aligned(CONFIG_DISPLAY_BUFFER_ALIGNMENT);
 static struct display_capabilities cfg;
 static uint8_t bpp;
-static bool is_tiled;
+static bool is_vtiled;
+static bool is_htiled;
 
 static inline uint8_t bytes_per_pixel(enum display_pixel_format pixel_format)
 {
@@ -34,6 +35,7 @@ static inline uint8_t bytes_per_pixel(enum display_pixel_format pixel_format)
 	case PIXEL_FORMAT_RGB_565:
 	case PIXEL_FORMAT_BGR_565:
 		return 2;
+	case PIXEL_FORMAT_L_8:
 	case PIXEL_FORMAT_MONO01:
 	case PIXEL_FORMAT_MONO10:
 	default:
@@ -56,7 +58,7 @@ static void verify_bytes_of_area(uint8_t *data, int cmp_x, int cmp_y, size_t wid
 
 	zassert_ok(err, "display_read failed");
 
-	if (is_tiled) {
+	if (is_vtiled || is_htiled) {
 		zassert_mem_equal(data, disp_buffer, width * height / 8, NULL);
 	} else {
 		zassert_mem_equal(data, disp_buffer, width * height * bpp, NULL);
@@ -65,7 +67,7 @@ static void verify_bytes_of_area(uint8_t *data, int cmp_x, int cmp_y, size_t wid
 
 static void verify_background_color(int x, int y, size_t width, size_t height, uint32_t color)
 {
-	size_t buf_size = is_tiled ? (height * width / 8) : (height * width * bpp);
+	size_t buf_size = height * width * bpp / ((is_vtiled || is_htiled) ? 8 : 1);
 	struct display_buffer_descriptor desc = {
 		.height = height,
 		.pitch = width,
@@ -89,7 +91,7 @@ static void verify_background_color(int x, int y, size_t width, size_t height, u
 			zassert_equal(buf16[i], (uint16_t)color, "@%d", i);
 			break;
 		case 1:
-			if (is_tiled) {
+			if (is_vtiled) {
 				uint16_t x = i % (width);
 				uint16_t line = (i - x) / width;
 				uint16_t tile = line / 8;
@@ -98,6 +100,10 @@ static void verify_background_color(int x, int y, size_t width, size_t height, u
 				uint8_t *tptr = disp_buffer + (tile * width + x);
 
 				zassert_equal(!!(*tptr & BIT(y)), !!(color), "@%d", i);
+			} else if (is_htiled) {
+				uint8_t *tptr = disp_buffer + i / 8;
+
+				zassert_equal(!!(*tptr & BIT(i % 8)), !!(color), "@%d", i);
 			} else {
 				zassert_equal(buf8[i], (uint8_t)color, "@%d", i);
 			}
@@ -113,7 +119,8 @@ static void display_before(void *text_fixture)
 {
 	display_get_capabilities(dev, &cfg);
 	bpp = bytes_per_pixel(cfg.current_pixel_format);
-	is_tiled = ((bpp == 1) && (cfg.screen_info & SCREEN_INFO_MONO_VTILED));
+	is_vtiled = (bpp == 1 && (cfg.screen_info & SCREEN_INFO_MONO_VTILED));
+	is_htiled = (bpp == 1 && !(cfg.screen_info & SCREEN_INFO_MONO_VTILED));
 
 	struct display_buffer_descriptor desc = {
 		.height = display_height,
@@ -142,8 +149,8 @@ ZTEST(display_read_write, test_clear)
 ZTEST(display_read_write, test_write_to_buffer_head)
 {
 	uint8_t data[4] = {0xFA, 0xAF, 0x9F, 0xFA};
-	uint8_t height = (is_tiled ? 8 : 1);
-	uint16_t width = sizeof(data) / bpp;
+	uint8_t height = (is_vtiled ? 8 : 1);
+	uint16_t width = sizeof(data) / bpp * (is_htiled ? 8 : 1);
 	uint16_t buf_size = width * bpp;
 	struct display_buffer_descriptor desc = {
 		.height = height,
@@ -170,8 +177,8 @@ ZTEST(display_read_write, test_write_to_buffer_head)
 ZTEST(display_read_write, test_write_to_buffer_tail)
 {
 	uint8_t data[4] = {0xFA, 0xAF, 0x9F, 0xFA};
-	uint16_t height = (is_tiled ? 8 : 1);
-	uint16_t width = sizeof(data) / bpp;
+	uint16_t height = (is_vtiled ? 8 : 1);
+	uint16_t width = sizeof(data) / bpp * (is_htiled ? 8 : 1);
 	uint16_t buf_size = width * bpp;
 	struct display_buffer_descriptor desc = {
 		.height = height,
@@ -195,7 +202,7 @@ ZTEST(display_read_write, test_write_to_buffer_tail)
 	zassert_ok(err, "display_read failed");
 
 	/* check write data and read data are same */
-	if (is_tiled) {
+	if (is_vtiled || is_htiled) {
 		zassert_mem_equal(data,
 				  disp_buffer + (display_width * display_height / 8 - buf_size),
 				  buf_size, NULL);
@@ -216,8 +223,8 @@ ZTEST(display_read_write, test_write_to_buffer_tail)
 ZTEST(display_read_write, test_read_does_not_clear_existing_buffer)
 {
 	uint8_t data[4] = {0xFA, 0xAF, 0x9F, 0xFA};
-	uint8_t height = (is_tiled ? 8 : 1);
-	uint16_t width = sizeof(data) / bpp;
+	uint8_t height = (is_vtiled ? 8 : 1);
+	uint16_t width = sizeof(data) / bpp * (is_htiled ? 8 : 1);
 	uint16_t buf_size = width * bpp;
 	struct display_buffer_descriptor desc = {
 		.height = height,
@@ -251,7 +258,7 @@ ZTEST(display_read_write, test_read_does_not_clear_existing_buffer)
 	zassert_ok(err, "display_read failed");
 
 	/* checking correctly write to the tail of buffer */
-	if (is_tiled) {
+	if (is_vtiled || is_htiled) {
 		zassert_mem_equal(data,
 				  disp_buffer + (display_width * display_height / 8 - buf_size),
 				  buf_size, NULL);
diff --git a/tests/drivers/display/display_read_write/testcase.yaml b/tests/drivers/display/display_read_write/testcase.yaml
index 4383c7d44ef..ec0b89f8f74 100644
--- a/tests/drivers/display/display_read_write/testcase.yaml
+++ b/tests/drivers/display/display_read_write/testcase.yaml
@@ -19,32 +19,62 @@ tests:
     extra_configs:
       - CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_RGB_888=y
       - CONFIG_SDL_DISPLAY_USE_HARDWARE_ACCELERATOR=n
-  drivers.display.read_write.sdl.mono01:
+  drivers.display.read_write.sdl.mono01.vtiled.msbfirst:
     platform_allow:
       - native_sim
     extra_configs:
       - CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_MONO01=y
       - CONFIG_SDL_DISPLAY_USE_HARDWARE_ACCELERATOR=n
-  drivers.display.read_write.sdl.mono10:
+  drivers.display.read_write.sdl.mono10.vtiled.msbfirst:
     platform_allow:
       - native_sim
     extra_configs:
       - CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_MONO10=y
       - CONFIG_SDL_DISPLAY_USE_HARDWARE_ACCELERATOR=n
-  drivers.display.read_write.sdl.mono01.lsbfirst:
+  drivers.display.read_write.sdl.mono01.htiled.msbfirst:
+    platform_allow:
+      - native_sim
+    extra_configs:
+      - CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_MONO01=y
+      - CONFIG_SDL_DISPLAY_USE_HARDWARE_ACCELERATOR=n
+      - CONFIG_SDL_DISPLAY_MONO_VTILED=n
+  drivers.display.read_write.sdl.mono10.htiled.msbfirst:
+    platform_allow:
+      - native_sim
+    extra_configs:
+      - CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_MONO10=y
+      - CONFIG_SDL_DISPLAY_USE_HARDWARE_ACCELERATOR=n
+      - CONFIG_SDL_DISPLAY_MONO_VTILED=n
+  drivers.display.read_write.sdl.mono01.vtiled.lsbfirst:
     platform_allow:
       - native_sim
     extra_configs:
       - CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_MONO01=y
       - CONFIG_SDL_DISPLAY_USE_HARDWARE_ACCELERATOR=n
       - CONFIG_SDL_DISPLAY_MONO_MSB_FIRST=n
-  drivers.display.read_write.sdl.mono10.lsbfirst:
+  drivers.display.read_write.sdl.mono10.vtiled.lsbfirst:
     platform_allow:
       - native_sim
     extra_configs:
       - CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_MONO10=y
       - CONFIG_SDL_DISPLAY_USE_HARDWARE_ACCELERATOR=n
       - CONFIG_SDL_DISPLAY_MONO_MSB_FIRST=n
+  drivers.display.read_write.sdl.mono01.htiled.lsbfirst:
+    platform_allow:
+      - native_sim
+    extra_configs:
+      - CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_MONO01=y
+      - CONFIG_SDL_DISPLAY_USE_HARDWARE_ACCELERATOR=n
+      - CONFIG_SDL_DISPLAY_MONO_VTILED=n
+      - CONFIG_SDL_DISPLAY_MONO_MSB_FIRST=n
+  drivers.display.read_write.sdl.mono10.htiled.lsbfirst:
+    platform_allow:
+      - native_sim
+    extra_configs:
+      - CONFIG_SDL_DISPLAY_DEFAULT_PIXEL_FORMAT_MONO10=y
+      - CONFIG_SDL_DISPLAY_USE_HARDWARE_ACCELERATOR=n
+      - CONFIG_SDL_DISPLAY_MONO_VTILED=n
+      - CONFIG_SDL_DISPLAY_MONO_MSB_FIRST=n
   drivers.display.read_write.sdl.rgb565:
     platform_allow:
       - native_sim
@@ -69,10 +99,10 @@ tests:
     # presence of the arduino_spi DT nodelabel
     platform_allow:
       - mimxrt685_evk/mimxrt685s/cm33
-  drivers.display.read_write.rtkmipilcdb00000be:
+  drivers.display.read_write.renesas_ra_glcdc:
     tags:
       - shield
+    filter: dt_compat_enabled("renesas,ra-glcdc")
     extra_args:
-      - SHIELD=rtkmipilcdb00000be
-    platform_allow:
-      - ek_ra8d1
+      - platform:ek_ra8d1/r7fa8d1bhecbd:SHIELD=rtkmipilcdb00000be
+      - platform:ek_ra8d1/r7fa8d1bhecbd:SHIELD=rtk7eka6m3b00001bu
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/cy8cproto_062_4343w.overlay b/tests/drivers/dma/chan_blen_transfer/boards/cy8cproto_062_4343w.overlay
new file mode 100644
index 00000000000..6402db8fbe0
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/cy8cproto_062_4343w.overlay
@@ -0,0 +1,12 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+tst_dma0: &dma0 {
+	status = "okay";
+};
+
+tst_dma1: &dma1 {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32662evkit.conf b/tests/drivers/dma/chan_blen_transfer/boards/max32662evkit.conf
new file mode 100644
index 00000000000..a093a1aa637
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/max32662evkit.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CODE_DATA_RELOCATION=y
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32662evkit.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max32662evkit.overlay
new file mode 100644
index 00000000000..0e412606f7a
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/max32662evkit.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+tst_dma0: &dma0 { };
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32666evkit_max32666_cpu0.conf b/tests/drivers/dma/chan_blen_transfer/boards/max32666evkit_max32666_cpu0.conf
new file mode 100644
index 00000000000..a093a1aa637
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/max32666evkit_max32666_cpu0.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CODE_DATA_RELOCATION=y
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32666evkit_max32666_cpu0.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max32666evkit_max32666_cpu0.overlay
new file mode 100644
index 00000000000..0e412606f7a
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/max32666evkit_max32666_cpu0.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+tst_dma0: &dma0 { };
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32666fthr_max32666_cpu0.conf b/tests/drivers/dma/chan_blen_transfer/boards/max32666fthr_max32666_cpu0.conf
new file mode 100644
index 00000000000..a093a1aa637
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/max32666fthr_max32666_cpu0.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CODE_DATA_RELOCATION=y
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max32666fthr_max32666_cpu0.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max32666fthr_max32666_cpu0.overlay
new file mode 100644
index 00000000000..0e412606f7a
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/max32666fthr_max32666_cpu0.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+tst_dma0: &dma0 { };
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max78000evkit_max78000_m4.conf b/tests/drivers/dma/chan_blen_transfer/boards/max78000evkit_max78000_m4.conf
new file mode 100644
index 00000000000..a093a1aa637
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/max78000evkit_max78000_m4.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CODE_DATA_RELOCATION=y
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max78000evkit_max78000_m4.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max78000evkit_max78000_m4.overlay
new file mode 100644
index 00000000000..0e412606f7a
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/max78000evkit_max78000_m4.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+tst_dma0: &dma0 { };
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max78000fthr_max78000_m4.conf b/tests/drivers/dma/chan_blen_transfer/boards/max78000fthr_max78000_m4.conf
new file mode 100644
index 00000000000..a093a1aa637
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/max78000fthr_max78000_m4.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_CODE_DATA_RELOCATION=y
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/max78000fthr_max78000_m4.overlay b/tests/drivers/dma/chan_blen_transfer/boards/max78000fthr_max78000_m4.overlay
new file mode 100644
index 00000000000..0e412606f7a
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/max78000fthr_max78000_m4.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+tst_dma0: &dma0 { };
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1050_evk.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1050_evk_mimxrt1052_hyperflash.conf
similarity index 100%
rename from tests/drivers/dma/chan_blen_transfer/boards/mimxrt1050_evk.conf
rename to tests/drivers/dma/chan_blen_transfer/boards/mimxrt1050_evk_mimxrt1052_hyperflash.conf
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.conf b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.conf
new file mode 100644
index 00000000000..433a67585be
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.conf
@@ -0,0 +1,3 @@
+CONFIG_CODE_DATA_RELOCATION=y
+CONFIG_MEM_ATTR_HEAP=y
+CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="DTCM"
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
new file mode 100644
index 00000000000..82f0bbe94e8
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2022 Kumar Gala <galak@kernel.org>
+ * Copyright (c) 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+&dtcm {
+	zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
+};
+
+tst_dma0: &edma0 { };
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_c071rb.conf b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_c071rb.conf
new file mode 100644
index 00000000000..13768e69ff3
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_c071rb.conf
@@ -0,0 +1,2 @@
+CONFIG_DMA_TRANSFER_CHANNEL_NR_0=1
+CONFIG_DMA_TRANSFER_CHANNEL_NR_1=2
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_c071rb.overlay b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_c071rb.overlay
new file mode 100644
index 00000000000..f444ad228df
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_c071rb.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+tst_dma0: &dma1 {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_wb07cc.conf b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_wb07cc.conf
new file mode 100644
index 00000000000..4cf988ef36d
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_wb07cc.conf
@@ -0,0 +1,3 @@
+# Use lowest- and highest-numbered channels to make sure the whole range works
+CONFIG_DMA_TRANSFER_CHANNEL_NR_0=0
+CONFIG_DMA_TRANSFER_CHANNEL_NR_1=7
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/nucleo_wb07cc.overlay b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_wb07cc.overlay
new file mode 100644
index 00000000000..b2d957212a4
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/nucleo_wb07cc.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+&dma1 {
+	status = "okay";
+};
+
+tst_dma0: &dmamux1 {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/tests/drivers/dma/chan_blen_transfer/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
new file mode 100644
index 00000000000..c921a4af96a
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&dma0 {
+	status = "okay";
+};
+
+tst_dma0: &dma0 { };
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/xg29_rb4412a.overlay b/tests/drivers/dma/chan_blen_transfer/boards/xg29_rb4412a.overlay
new file mode 100644
index 00000000000..73a4023ee35
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/xg29_rb4412a.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&dma0 {
+	status = "okay";
+};
+
+tst_dma0: &dma0 { };
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/xmc45_relax_kit.conf b/tests/drivers/dma/chan_blen_transfer/boards/xmc45_relax_kit.conf
new file mode 100644
index 00000000000..9664ee7c621
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/xmc45_relax_kit.conf
@@ -0,0 +1 @@
+CONFIG_DMA_TRANSFER_BURST16=n
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/xmc45_relax_kit.overlay b/tests/drivers/dma/chan_blen_transfer/boards/xmc45_relax_kit.overlay
new file mode 100644
index 00000000000..2fed134b32c
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/xmc45_relax_kit.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025 Andriy Gelman
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&dma0 {
+	status = "okay";
+};
+
+tst_dma0: &dma0 { };
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/xmc47_relax_kit.conf b/tests/drivers/dma/chan_blen_transfer/boards/xmc47_relax_kit.conf
new file mode 100644
index 00000000000..9664ee7c621
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/xmc47_relax_kit.conf
@@ -0,0 +1 @@
+CONFIG_DMA_TRANSFER_BURST16=n
diff --git a/tests/drivers/dma/chan_blen_transfer/boards/xmc47_relax_kit.overlay b/tests/drivers/dma/chan_blen_transfer/boards/xmc47_relax_kit.overlay
new file mode 100644
index 00000000000..2fed134b32c
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/boards/xmc47_relax_kit.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025 Andriy Gelman
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&dma0 {
+	status = "okay";
+};
+
+tst_dma0: &dma0 { };
diff --git a/tests/drivers/dma/chan_blen_transfer/socs/esp32c3_usb.conf b/tests/drivers/dma/chan_blen_transfer/socs/esp32c3_usb.conf
new file mode 100644
index 00000000000..56bf25e718b
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/socs/esp32c3_usb.conf
@@ -0,0 +1,3 @@
+CONFIG_DMA_TRANSFER_CHANNEL_NR_0=5
+CONFIG_DMA_TRANSFER_CHANNEL_NR_1=0
+CONFIG_HEAP_MEM_POOL_SIZE=32768
diff --git a/tests/drivers/dma/chan_blen_transfer/socs/esp32c3_usb.overlay b/tests/drivers/dma/chan_blen_transfer/socs/esp32c3_usb.overlay
new file mode 100644
index 00000000000..6ac9ff08336
--- /dev/null
+++ b/tests/drivers/dma/chan_blen_transfer/socs/esp32c3_usb.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&dma {
+	status = "okay";
+};
+
+tst_dma0: &dma { };
diff --git a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
similarity index 100%
rename from tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay
rename to tests/drivers/dma/chan_link_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
diff --git a/tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
new file mode 100644
index 00000000000..9d2f44e7231
--- /dev/null
+++ b/tests/drivers/dma/chan_link_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2022 Kumar Gala <galak@kernel.org>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+dma0: &edma0 { };
diff --git a/tests/drivers/dma/cyclic/CMakeLists.txt b/tests/drivers/dma/cyclic/CMakeLists.txt
new file mode 100644
index 00000000000..228b4f61a0a
--- /dev/null
+++ b/tests/drivers/dma/cyclic/CMakeLists.txt
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(cyclic)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/drivers/dma/cyclic/Kconfig b/tests/drivers/dma/cyclic/Kconfig
new file mode 100644
index 00000000000..d53b052542a
--- /dev/null
+++ b/tests/drivers/dma/cyclic/Kconfig
@@ -0,0 +1,14 @@
+# Copyright (c) 2025 Andriy Gelman
+# SPDX-License-Identifier: Apache-2.0
+
+mainmenu "DMA Cyclic Test"
+
+source "Kconfig.zephyr"
+
+config DMA_CYCLIC_CHANNEL_NR
+	int "DMA channel to use"
+	default 0
+
+config DMA_CYCLIC_XFER_SIZE
+	int "Number of bytes to transfer"
+	default 4096
diff --git a/tests/drivers/dma/cyclic/boards/xmc45_relax_kit.overlay b/tests/drivers/dma/cyclic/boards/xmc45_relax_kit.overlay
new file mode 100644
index 00000000000..4513bba046b
--- /dev/null
+++ b/tests/drivers/dma/cyclic/boards/xmc45_relax_kit.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Andriy Gelman <andriy.gelman@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		dma0 = &dma0;
+	};
+};
+
+&dma0 {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/cyclic/boards/xmc47_relax_kit.overlay b/tests/drivers/dma/cyclic/boards/xmc47_relax_kit.overlay
new file mode 100644
index 00000000000..4513bba046b
--- /dev/null
+++ b/tests/drivers/dma/cyclic/boards/xmc47_relax_kit.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Andriy Gelman <andriy.gelman@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		dma0 = &dma0;
+	};
+};
+
+&dma0 {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/cyclic/prj.conf b/tests/drivers/dma/cyclic/prj.conf
new file mode 100644
index 00000000000..40e96629277
--- /dev/null
+++ b/tests/drivers/dma/cyclic/prj.conf
@@ -0,0 +1,4 @@
+CONFIG_ZTEST=y
+CONFIG_DMA=y
+CONFIG_LOG=y
+CONFIG_DMA_LOG_LEVEL_INF=y
diff --git a/tests/drivers/dma/cyclic/src/main.c b/tests/drivers/dma/cyclic/src/main.c
new file mode 100644
index 00000000000..112dfcba333
--- /dev/null
+++ b/tests/drivers/dma/cyclic/src/main.c
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025 Andriy Gelman
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(dma_m2m_cyclic, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/drivers/dma/cyclic/src/test_dma_cyclic.c b/tests/drivers/dma/cyclic/src/test_dma_cyclic.c
new file mode 100644
index 00000000000..c80d0e6d9d6
--- /dev/null
+++ b/tests/drivers/dma/cyclic/src/test_dma_cyclic.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2025 Andriy Gelman
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Verify zephyr dma memory to memory cyclic transfer
+ * @details
+ * - Test Steps
+ *   -# Set dma configuration for cyclic configuration
+ *   -# Start transfer tx -> rx
+ *   -# Wait for a block transfer to complete
+ *   -# Suspend transfer and check tx/rx contents match
+ *   -# Invalidate rx data and resume transfer
+ *   -# Wait for a block transfer to complete
+ *   -# Stop transfer and check tx/rx contents match
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/dma.h>
+#include <zephyr/ztest.h>
+
+static __aligned(32) uint8_t tx_data[CONFIG_DMA_CYCLIC_XFER_SIZE];
+static __aligned(32) uint8_t rx_data[CONFIG_DMA_CYCLIC_XFER_SIZE];
+
+K_SEM_DEFINE(xfer_sem, 0, 1);
+
+static struct dma_config dma_cfg;
+static struct dma_block_config dma_block_cfgs;
+
+static void dma_callback(const struct device *dma_dev, void *user_data,
+			    uint32_t channel, int status)
+{
+	k_sem_give(&xfer_sem);
+}
+
+
+static int test_cyclic(void)
+{
+	const struct device *dma;
+	int chan_id;
+
+	TC_PRINT("Preparing DMA Controller\n");
+
+	for (int i = 0; i < CONFIG_DMA_CYCLIC_XFER_SIZE; i++) {
+		tx_data[i] = i;
+	}
+
+	dma = DEVICE_DT_GET(DT_ALIAS(dma0));
+	if (!device_is_ready(dma)) {
+		TC_PRINT("dma controller device is not ready\n");
+		return TC_FAIL;
+	}
+
+	dma_cfg.channel_direction = MEMORY_TO_MEMORY;
+	dma_cfg.source_data_size = 4U;
+	dma_cfg.dest_data_size = 4U;
+	dma_cfg.source_burst_length = 4U;
+	dma_cfg.dest_burst_length = 4U;
+	dma_cfg.user_data = NULL;
+	dma_cfg.dma_callback = dma_callback;
+	dma_cfg.block_count = 1;
+	dma_cfg.head_block = &dma_block_cfgs;
+	dma_cfg.complete_callback_en = true; /* per block completion */
+	dma_cfg.cyclic = 1;
+
+	chan_id = dma_request_channel(dma, NULL);
+	if (chan_id < 0) {
+		TC_PRINT("Platform does not support dma request channel,"
+			 " using Kconfig DMA_SG_CHANNEL_NR\n");
+		chan_id = CONFIG_DMA_CYCLIC_CHANNEL_NR;
+	}
+
+	dma_block_cfgs.block_size = CONFIG_DMA_CYCLIC_XFER_SIZE;
+
+	dma_block_cfgs.source_address = (uint32_t)(tx_data);
+	dma_block_cfgs.dest_address = (uint32_t)(rx_data);
+
+	TC_PRINT("Configuring cyclic transfer on channel %d\n", chan_id);
+
+	if (dma_config(dma, chan_id, &dma_cfg)) {
+		TC_PRINT("ERROR: transfer config (%d)\n", chan_id);
+		return TC_FAIL;
+	}
+
+	TC_PRINT("Starting cyclic transfer on channel %d and waiting for first block to complete\n",
+		 chan_id);
+
+	if (dma_start(dma, chan_id)) {
+		TC_PRINT("ERROR: transfer start (%d)\n", chan_id);
+		return TC_FAIL;
+	}
+
+	if (k_sem_take(&xfer_sem, K_MSEC(10)) != 0) {
+		TC_PRINT("Timed out waiting for xfers\n");
+		return TC_FAIL;
+	}
+
+	if (dma_suspend(dma, chan_id) != 0) {
+		TC_PRINT("Failed to suspend transfer\n");
+		return TC_FAIL;
+	}
+
+	if (memcmp(tx_data, rx_data, CONFIG_DMA_CYCLIC_XFER_SIZE)) {
+		TC_PRINT("Failed to verify tx/rx in the first cycle.\n");
+		return TC_FAIL;
+	}
+
+	k_sem_reset(&xfer_sem);
+
+	/* reset rx_data to validate that transfer cycles */
+	memset(rx_data, 0, sizeof(rx_data));
+
+	if (dma_resume(dma, chan_id) != 0) {
+		TC_PRINT("Failed to resume transfer\n");
+		return TC_FAIL;
+	}
+
+	if (k_sem_take(&xfer_sem, K_MSEC(10)) != 0) {
+		TC_PRINT("Timed out waiting for xfers\n");
+		return TC_FAIL;
+	}
+
+	if (dma_stop(dma, chan_id) != 0) {
+		TC_PRINT("Failed to stop dma\n");
+		return TC_FAIL;
+	}
+
+	if (memcmp(tx_data, rx_data, CONFIG_DMA_CYCLIC_XFER_SIZE)) {
+		TC_PRINT("Failed to verify tx/rx in the second cycle.\n");
+		return TC_FAIL;
+	}
+
+	TC_PRINT("Finished: DMA Cyclic test\n");
+	return TC_PASS;
+}
+
+/* export test cases */
+ZTEST(dma_m2m_cyclic, test_dma_m2m_cyclic)
+{
+	zassert_true((test_cyclic() == TC_PASS));
+}
diff --git a/tests/drivers/dma/cyclic/testcase.yaml b/tests/drivers/dma/cyclic/testcase.yaml
new file mode 100644
index 00000000000..ab5959ca0eb
--- /dev/null
+++ b/tests/drivers/dma/cyclic/testcase.yaml
@@ -0,0 +1,10 @@
+tests:
+  drivers.dma.cyclic:
+    depends_on: dma
+    tags:
+      - drivers
+      - dma
+    platform_allow:
+      - xmc47_relax_kit
+      - xmc45_relax_kit
+    filter: dt_alias_exists("dma0")
diff --git a/tests/drivers/dma/loop_transfer/boards/esp32c6_devkitc.conf b/tests/drivers/dma/loop_transfer/boards/esp32c6_devkitc_hpcore.conf
similarity index 100%
rename from tests/drivers/dma/loop_transfer/boards/esp32c6_devkitc.conf
rename to tests/drivers/dma/loop_transfer/boards/esp32c6_devkitc_hpcore.conf
diff --git a/tests/drivers/dma/loop_transfer/boards/esp32c6_devkitc.overlay b/tests/drivers/dma/loop_transfer/boards/esp32c6_devkitc_hpcore.overlay
similarity index 100%
rename from tests/drivers/dma/loop_transfer/boards/esp32c6_devkitc.overlay
rename to tests/drivers/dma/loop_transfer/boards/esp32c6_devkitc_hpcore.overlay
diff --git a/tests/drivers/dma/loop_transfer/boards/max32662evkit.overlay b/tests/drivers/dma/loop_transfer/boards/max32662evkit.overlay
new file mode 100644
index 00000000000..8c711035a31
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/max32662evkit.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&sram0 {
+	compatible = "mmio-sram";
+	reg = <0x20000000 DT_SIZE_K(64)>;
+};
+
+/ {
+	chosen {
+		zephyr,sram = &sram0;
+	};
+};
+
+tst_dma0: &dma0 { };
diff --git a/tests/drivers/dma/loop_transfer/boards/max32666evkit_max32666_cpu0.overlay b/tests/drivers/dma/loop_transfer/boards/max32666evkit_max32666_cpu0.overlay
new file mode 100644
index 00000000000..0e412606f7a
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/max32666evkit_max32666_cpu0.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+tst_dma0: &dma0 { };
diff --git a/tests/drivers/dma/loop_transfer/boards/max32666fthr_max32666_cpu0.overlay b/tests/drivers/dma/loop_transfer/boards/max32666fthr_max32666_cpu0.overlay
new file mode 100644
index 00000000000..0e412606f7a
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/max32666fthr_max32666_cpu0.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+tst_dma0: &dma0 { };
diff --git a/tests/drivers/dma/loop_transfer/boards/max78000evkit_max78000_m4.overlay b/tests/drivers/dma/loop_transfer/boards/max78000evkit_max78000_m4.overlay
new file mode 100644
index 00000000000..0e412606f7a
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/max78000evkit_max78000_m4.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+tst_dma0: &dma0 { };
diff --git a/tests/drivers/dma/loop_transfer/boards/max78000fthr_max78000_m4.overlay b/tests/drivers/dma/loop_transfer/boards/max78000fthr_max78000_m4.overlay
new file mode 100644
index 00000000000..0e412606f7a
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/max78000fthr_max78000_m4.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+tst_dma0: &dma0 { };
diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1050_evk.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1050_evk_mimxrt1052_hyperflash.conf
similarity index 100%
rename from tests/drivers/dma/loop_transfer/boards/mimxrt1050_evk.conf
rename to tests/drivers/dma/loop_transfer/boards/mimxrt1050_evk_mimxrt1052_hyperflash.conf
diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.conf
similarity index 100%
rename from tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf
rename to tests/drivers/dma/loop_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.conf
diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
new file mode 100644
index 00000000000..82f0bbe94e8
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2022 Kumar Gala <galak@kernel.org>
+ * Copyright (c) 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+&dtcm {
+	zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
+};
+
+tst_dma0: &edma0 { };
diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf
deleted file mode 100644
index cdc6eb7c7f1..00000000000
--- a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.conf
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_CODE_DATA_RELOCATION=y
-CONFIG_MEM_ATTR_HEAP=y
-CONFIG_DMA_LOOP_TRANSFER_RELOCATE_SECTION="SRAM1"
diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay
deleted file mode 100644
index 5e8bafa1d9b..00000000000
--- a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (c) 2022 Kumar Gala <galak@kernel.org>
- * Copyright (c) 2024 NXP
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
-
-&sram1 {
-	zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
-};
-
-tst_dma0: &edma_lpsr0 { };
diff --git a/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7.conf
similarity index 100%
rename from tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf
rename to tests/drivers/dma/loop_transfer/boards/mimxrt1170_evk_mimxrt1176_cm7.conf
diff --git a/tests/drivers/dma/loop_transfer/boards/nucleo_n657x0_q_stm32n657xx_sb.conf b/tests/drivers/dma/loop_transfer/boards/nucleo_n657x0_q_stm32n657xx_sb.conf
new file mode 100644
index 00000000000..fe052ddaeaa
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/nucleo_n657x0_q_stm32n657xx_sb.conf
@@ -0,0 +1 @@
+CONFIG_DMA_LOOP_TRANSFER_CHANNEL_NR=8
diff --git a/tests/drivers/dma/loop_transfer/boards/nucleo_n657x0_q_stm32n657xx_sb.overlay b/tests/drivers/dma/loop_transfer/boards/nucleo_n657x0_q_stm32n657xx_sb.overlay
new file mode 100644
index 00000000000..371fa52922b
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/nucleo_n657x0_q_stm32n657xx_sb.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+tst_dma0: &gpdma1 {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/loop_transfer/boards/nucleo_wb07cc.conf b/tests/drivers/dma/loop_transfer/boards/nucleo_wb07cc.conf
new file mode 100644
index 00000000000..fe1ac38875b
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/nucleo_wb07cc.conf
@@ -0,0 +1 @@
+CONFIG_DMA_LOOP_TRANSFER_CHANNEL_NR=7
diff --git a/tests/drivers/dma/loop_transfer/boards/nucleo_wb07cc.overlay b/tests/drivers/dma/loop_transfer/boards/nucleo_wb07cc.overlay
new file mode 100644
index 00000000000..b2d957212a4
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/nucleo_wb07cc.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+&dma1 {
+	status = "okay";
+};
+
+tst_dma0: &dmamux1 {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/loop_transfer/boards/pico_plus2_rp2350b_m33.overlay b/tests/drivers/dma/loop_transfer/boards/pico_plus2_rp2350b_m33.overlay
new file mode 100644
index 00000000000..35ee84e3c4e
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/pico_plus2_rp2350b_m33.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2023 Tokita, Hiroshi <tokita.hiroshi@fujitsu.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+tst_dma0: &dma {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/loop_transfer/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/tests/drivers/dma/loop_transfer/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
new file mode 100644
index 00000000000..c921a4af96a
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&dma0 {
+	status = "okay";
+};
+
+tst_dma0: &dma0 { };
diff --git a/tests/drivers/dma/loop_transfer/boards/samc21n_xpro.conf b/tests/drivers/dma/loop_transfer/boards/samc21n_xpro.conf
new file mode 100644
index 00000000000..b575d099ec9
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/samc21n_xpro.conf
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Gerson Fernando Budke <nandojve@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DMA_LOOP_TRANSFER_SIZE=2048
diff --git a/tests/drivers/dma/loop_transfer/boards/samc21n_xpro.overlay b/tests/drivers/dma/loop_transfer/boards/samc21n_xpro.overlay
index 2731332e26b..5007ef08d4f 100644
--- a/tests/drivers/dma/loop_transfer/boards/samc21n_xpro.overlay
+++ b/tests/drivers/dma/loop_transfer/boards/samc21n_xpro.overlay
@@ -1,7 +1,10 @@
 /*
  * Copyright (c) 2022 Kumar Gala <galak@kernel.org>
+ * Copyright (c) 2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-tst_dma0: &dmac { };
+tst_dma0: &dmac {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/loop_transfer/boards/samd21_xpro.conf b/tests/drivers/dma/loop_transfer/boards/samd21_xpro.conf
new file mode 100644
index 00000000000..b575d099ec9
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/samd21_xpro.conf
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Gerson Fernando Budke <nandojve@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DMA_LOOP_TRANSFER_SIZE=2048
diff --git a/tests/drivers/dma/loop_transfer/boards/samd21_xpro.overlay b/tests/drivers/dma/loop_transfer/boards/samd21_xpro.overlay
index 2731332e26b..5007ef08d4f 100644
--- a/tests/drivers/dma/loop_transfer/boards/samd21_xpro.overlay
+++ b/tests/drivers/dma/loop_transfer/boards/samd21_xpro.overlay
@@ -1,7 +1,10 @@
 /*
  * Copyright (c) 2022 Kumar Gala <galak@kernel.org>
+ * Copyright (c) 2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-tst_dma0: &dmac { };
+tst_dma0: &dmac {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/loop_transfer/boards/same54_xpro.overlay b/tests/drivers/dma/loop_transfer/boards/same54_xpro.overlay
new file mode 100644
index 00000000000..721ee2d760f
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/same54_xpro.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2025 Gerson Fernando Budke <nandojve@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+tst_dma0: &dmac {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/loop_transfer/boards/saml21_xpro.conf b/tests/drivers/dma/loop_transfer/boards/saml21_xpro.conf
new file mode 100644
index 00000000000..b575d099ec9
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/saml21_xpro.conf
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Gerson Fernando Budke <nandojve@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DMA_LOOP_TRANSFER_SIZE=2048
diff --git a/tests/drivers/dma/loop_transfer/boards/saml21_xpro.overlay b/tests/drivers/dma/loop_transfer/boards/saml21_xpro.overlay
index 2731332e26b..5007ef08d4f 100644
--- a/tests/drivers/dma/loop_transfer/boards/saml21_xpro.overlay
+++ b/tests/drivers/dma/loop_transfer/boards/saml21_xpro.overlay
@@ -1,7 +1,10 @@
 /*
  * Copyright (c) 2022 Kumar Gala <galak@kernel.org>
+ * Copyright (c) 2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-tst_dma0: &dmac { };
+tst_dma0: &dmac {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/loop_transfer/boards/samr21_xpro.conf b/tests/drivers/dma/loop_transfer/boards/samr21_xpro.conf
new file mode 100644
index 00000000000..b575d099ec9
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/samr21_xpro.conf
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Gerson Fernando Budke <nandojve@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DMA_LOOP_TRANSFER_SIZE=2048
diff --git a/tests/drivers/dma/loop_transfer/boards/samr21_xpro.overlay b/tests/drivers/dma/loop_transfer/boards/samr21_xpro.overlay
new file mode 100644
index 00000000000..5007ef08d4f
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/samr21_xpro.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2022 Kumar Gala <galak@kernel.org>
+ * Copyright (c) 2025 Gerson Fernando Budke <nandojve@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+tst_dma0: &dmac {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/loop_transfer/boards/samr34_xpro.conf b/tests/drivers/dma/loop_transfer/boards/samr34_xpro.conf
new file mode 100644
index 00000000000..b575d099ec9
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/samr34_xpro.conf
@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Gerson Fernando Budke <nandojve@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DMA_LOOP_TRANSFER_SIZE=2048
diff --git a/tests/drivers/dma/loop_transfer/boards/samr34_xpro.overlay b/tests/drivers/dma/loop_transfer/boards/samr34_xpro.overlay
index 2731332e26b..5007ef08d4f 100644
--- a/tests/drivers/dma/loop_transfer/boards/samr34_xpro.overlay
+++ b/tests/drivers/dma/loop_transfer/boards/samr34_xpro.overlay
@@ -1,7 +1,10 @@
 /*
  * Copyright (c) 2022 Kumar Gala <galak@kernel.org>
+ * Copyright (c) 2025 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-tst_dma0: &dmac { };
+tst_dma0: &dmac {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/loop_transfer/boards/stm32n6570_dk_stm32n657xx_sb.conf b/tests/drivers/dma/loop_transfer/boards/stm32n6570_dk_stm32n657xx_sb.conf
new file mode 100644
index 00000000000..fe052ddaeaa
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/stm32n6570_dk_stm32n657xx_sb.conf
@@ -0,0 +1 @@
+CONFIG_DMA_LOOP_TRANSFER_CHANNEL_NR=8
diff --git a/tests/drivers/dma/loop_transfer/boards/stm32n6570_dk_stm32n657xx_sb.overlay b/tests/drivers/dma/loop_transfer/boards/stm32n6570_dk_stm32n657xx_sb.overlay
new file mode 100644
index 00000000000..371fa52922b
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/stm32n6570_dk_stm32n657xx_sb.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+tst_dma0: &gpdma1 {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/loop_transfer/boards/xg29_rb4412a.conf b/tests/drivers/dma/loop_transfer/boards/xg29_rb4412a.conf
new file mode 100644
index 00000000000..c7576963782
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/xg29_rb4412a.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Silicon Laboratories, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DMA_LOOP_TRANSFER_SIZE=2048
diff --git a/tests/drivers/dma/loop_transfer/boards/xg29_rb4412a.overlay b/tests/drivers/dma/loop_transfer/boards/xg29_rb4412a.overlay
new file mode 100644
index 00000000000..73a4023ee35
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/xg29_rb4412a.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&dma0 {
+	status = "okay";
+};
+
+tst_dma0: &dma0 { };
diff --git a/tests/drivers/dma/loop_transfer/boards/xmc45_relax_kit.conf b/tests/drivers/dma/loop_transfer/boards/xmc45_relax_kit.conf
new file mode 100644
index 00000000000..f84bfcdbc4c
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/xmc45_relax_kit.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Andriy Gelman
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DMA_LOOP_TRANSFER_SIZE=4095
diff --git a/tests/drivers/dma/loop_transfer/boards/xmc45_relax_kit.overlay b/tests/drivers/dma/loop_transfer/boards/xmc45_relax_kit.overlay
new file mode 100644
index 00000000000..c979d57eb6d
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/xmc45_relax_kit.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2022 Andriy Gelman <andriy.gelman@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+tst_dma0: &dma0 {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/loop_transfer/boards/xmc47_relax_kit.conf b/tests/drivers/dma/loop_transfer/boards/xmc47_relax_kit.conf
new file mode 100644
index 00000000000..f84bfcdbc4c
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/xmc47_relax_kit.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Andriy Gelman
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DMA_LOOP_TRANSFER_SIZE=4095
diff --git a/tests/drivers/dma/loop_transfer/boards/xmc47_relax_kit.overlay b/tests/drivers/dma/loop_transfer/boards/xmc47_relax_kit.overlay
new file mode 100644
index 00000000000..047ea01b1c0
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/boards/xmc47_relax_kit.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2025 Andriy Gelman <andriy.gelman@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+tst_dma0: &dma0 {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/loop_transfer/socs/esp32c3_usb.conf b/tests/drivers/dma/loop_transfer/socs/esp32c3_usb.conf
new file mode 100644
index 00000000000..311bfc8f535
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/socs/esp32c3_usb.conf
@@ -0,0 +1,2 @@
+CONFIG_DMA_LOOP_TRANSFER_CHANNEL_NR=0
+CONFIG_DMA_LOOP_TRANSFER_SIZE=4094
diff --git a/tests/drivers/dma/loop_transfer/socs/esp32c3_usb.overlay b/tests/drivers/dma/loop_transfer/socs/esp32c3_usb.overlay
new file mode 100644
index 00000000000..6ac9ff08336
--- /dev/null
+++ b/tests/drivers/dma/loop_transfer/socs/esp32c3_usb.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&dma {
+	status = "okay";
+};
+
+tst_dma0: &dma { };
diff --git a/tests/drivers/dma/scatter_gather/boards/cy8cproto_062_4343w.overlay b/tests/drivers/dma/scatter_gather/boards/cy8cproto_062_4343w.overlay
new file mode 100644
index 00000000000..c84db54befa
--- /dev/null
+++ b/tests/drivers/dma/scatter_gather/boards/cy8cproto_062_4343w.overlay
@@ -0,0 +1,13 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		dma0 = &dma0;
+	};
+};
+
+&dma0 {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/scatter_gather/boards/cyw920829m2evk_02.conf b/tests/drivers/dma/scatter_gather/boards/cyw920829m2evk_02.conf
new file mode 100644
index 00000000000..7d02f988235
--- /dev/null
+++ b/tests/drivers/dma/scatter_gather/boards/cyw920829m2evk_02.conf
@@ -0,0 +1 @@
+CONFIG_DMA_SG_XFER_SIZE=256
diff --git a/tests/drivers/dma/scatter_gather/boards/cyw920829m2evk_02.overlay b/tests/drivers/dma/scatter_gather/boards/cyw920829m2evk_02.overlay
new file mode 100644
index 00000000000..c84db54befa
--- /dev/null
+++ b/tests/drivers/dma/scatter_gather/boards/cyw920829m2evk_02.overlay
@@ -0,0 +1,13 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		dma0 = &dma0;
+	};
+};
+
+&dma0 {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/scatter_gather/boards/mimxrt1060_evk_mimxrt1062_qspi_C.conf b/tests/drivers/dma/scatter_gather/boards/mimxrt1060_evk_mimxrt1062_qspi_C.conf
new file mode 100644
index 00000000000..61f2d18ca3c
--- /dev/null
+++ b/tests/drivers/dma/scatter_gather/boards/mimxrt1060_evk_mimxrt1062_qspi_C.conf
@@ -0,0 +1 @@
+CONFIG_DMA_TCD_QUEUE_SIZE=4
diff --git a/tests/drivers/dma/scatter_gather/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/tests/drivers/dma/scatter_gather/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
new file mode 100644
index 00000000000..401a141fca0
--- /dev/null
+++ b/tests/drivers/dma/scatter_gather/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright (c) 2022 Kumar Gala <galak@kernel.org>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		dma0 = &edma0;
+	};
+};
diff --git a/tests/drivers/dma/scatter_gather/boards/siwx917_rb4338a.conf b/tests/drivers/dma/scatter_gather/boards/siwx917_rb4338a.conf
new file mode 100644
index 00000000000..2bd1c2c8dba
--- /dev/null
+++ b/tests/drivers/dma/scatter_gather/boards/siwx917_rb4338a.conf
@@ -0,0 +1,2 @@
+CONFIG_DMA_SG_CHANNEL_NR=7
+CONFIG_DMA_SG_XFER_SIZE=4096
diff --git a/tests/drivers/dma/scatter_gather/boards/siwx917_rb4338a.overlay b/tests/drivers/dma/scatter_gather/boards/siwx917_rb4338a.overlay
new file mode 100644
index 00000000000..b5bf935a9c3
--- /dev/null
+++ b/tests/drivers/dma/scatter_gather/boards/siwx917_rb4338a.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/ {
+	aliases {
+		dma0 = &dma0;
+	};
+};
+&dma0 {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/scatter_gather/boards/xg29_rb4412a.overlay b/tests/drivers/dma/scatter_gather/boards/xg29_rb4412a.overlay
new file mode 100644
index 00000000000..a6fb1d7e094
--- /dev/null
+++ b/tests/drivers/dma/scatter_gather/boards/xg29_rb4412a.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		dma0 = &dma0;
+	};
+};
+
+&dma0 {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/scatter_gather/boards/xmc45_relax_kit.conf b/tests/drivers/dma/scatter_gather/boards/xmc45_relax_kit.conf
new file mode 100644
index 00000000000..d405d85aac1
--- /dev/null
+++ b/tests/drivers/dma/scatter_gather/boards/xmc45_relax_kit.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Andriy Gelman
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DMA_SG_XFER_SIZE=4096
diff --git a/tests/drivers/dma/scatter_gather/boards/xmc45_relax_kit.overlay b/tests/drivers/dma/scatter_gather/boards/xmc45_relax_kit.overlay
new file mode 100644
index 00000000000..4513bba046b
--- /dev/null
+++ b/tests/drivers/dma/scatter_gather/boards/xmc45_relax_kit.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Andriy Gelman <andriy.gelman@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		dma0 = &dma0;
+	};
+};
+
+&dma0 {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/scatter_gather/boards/xmc47_relax_kit.conf b/tests/drivers/dma/scatter_gather/boards/xmc47_relax_kit.conf
new file mode 100644
index 00000000000..d405d85aac1
--- /dev/null
+++ b/tests/drivers/dma/scatter_gather/boards/xmc47_relax_kit.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Andriy Gelman
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_DMA_SG_XFER_SIZE=4096
diff --git a/tests/drivers/dma/scatter_gather/boards/xmc47_relax_kit.overlay b/tests/drivers/dma/scatter_gather/boards/xmc47_relax_kit.overlay
new file mode 100644
index 00000000000..4513bba046b
--- /dev/null
+++ b/tests/drivers/dma/scatter_gather/boards/xmc47_relax_kit.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Andriy Gelman <andriy.gelman@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		dma0 = &dma0;
+	};
+};
+
+&dma0 {
+	status = "okay";
+};
diff --git a/tests/drivers/dma/scatter_gather/src/test_dma_sg.c b/tests/drivers/dma/scatter_gather/src/test_dma_sg.c
index bf360454cf7..c24bb689869 100644
--- a/tests/drivers/dma/scatter_gather/src/test_dma_sg.c
+++ b/tests/drivers/dma/scatter_gather/src/test_dma_sg.c
@@ -105,13 +105,13 @@ static int test_sg(void)
 #ifdef CONFIG_DMA_64BIT
 		dma_block_cfgs[i].source_address = (uint64_t)(tx_data);
 		dma_block_cfgs[i].dest_address = (uint64_t)(rx_data[i]);
-		TC_PRINT("dma block %d block_size %d, source addr %" PRIx64 ", dest addr %"
+		TC_PRINT("dma block %d block_size %d, source addr 0x%" PRIx64 ", dest addr 0x%"
 		     PRIx64 "\n", i, CONFIG_DMA_SG_XFER_SIZE, dma_block_cfgs[i].source_address,
 			 dma_block_cfgs[i].dest_address);
 #else
 		dma_block_cfgs[i].source_address = (uint32_t)(tx_data);
 		dma_block_cfgs[i].dest_address = (uint32_t)(rx_data[i]);
-		TC_PRINT("dma block %d block_size %d, source addr %x, dest addr %x\n",
+		TC_PRINT("dma block %d block_size %d, source addr 0x%x, dest addr 0x%x\n",
 			 i, CONFIG_DMA_SG_XFER_SIZE, dma_block_cfgs[i].source_address,
 			 dma_block_cfgs[i].dest_address);
 #endif
diff --git a/tests/drivers/dma/scatter_gather/testcase.yaml b/tests/drivers/dma/scatter_gather/testcase.yaml
index 457c13f3c51..f5f69cdebfa 100644
--- a/tests/drivers/dma/scatter_gather/testcase.yaml
+++ b/tests/drivers/dma/scatter_gather/testcase.yaml
@@ -8,10 +8,13 @@ tests:
       - intel_adsp/cavs25
       - frdm_k64f
       - mimxrt1010_evk
+      - mimxrt685_evk/mimxrt685s/cm33
       - mimxrt1060_evk/mimxrt1062/qspi
       - lpcxpresso55s36
       - native_sim
       - native_sim/native/64
+      - xmc45_relax_kit
+      - xmc47_relax_kit
     filter: dt_alias_exists("dma0")
     integration_platforms:
       - intel_adsp/cavs25
diff --git a/tests/drivers/entropy/api/boards/neorv32.overlay b/tests/drivers/entropy/api/boards/neorv32.overlay
deleted file mode 100644
index 5c11a7671d8..00000000000
--- a/tests/drivers/entropy/api/boards/neorv32.overlay
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&trng {
-	status = "okay";
-};
diff --git a/tests/drivers/entropy/api/boards/nucleo_wb05kz.overlay b/tests/drivers/entropy/api/boards/nucleo_wb05kz.overlay
new file mode 100644
index 00000000000..70954faf6b1
--- /dev/null
+++ b/tests/drivers/entropy/api/boards/nucleo_wb05kz.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,entropy = &rng;
+	};
+};
+
+&rng {
+	status = "okay";
+};
diff --git a/tests/drivers/entropy/api/boards/nucleo_wb07cc.overlay b/tests/drivers/entropy/api/boards/nucleo_wb07cc.overlay
new file mode 100644
index 00000000000..70954faf6b1
--- /dev/null
+++ b/tests/drivers/entropy/api/boards/nucleo_wb07cc.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,entropy = &rng;
+	};
+};
+
+&rng {
+	status = "okay";
+};
diff --git a/tests/drivers/entropy/api/boards/nucleo_wb09ke.overlay b/tests/drivers/entropy/api/boards/nucleo_wb09ke.overlay
new file mode 100644
index 00000000000..70954faf6b1
--- /dev/null
+++ b/tests/drivers/entropy/api/boards/nucleo_wb09ke.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		zephyr,entropy = &rng;
+	};
+};
+
+&rng {
+	status = "okay";
+};
diff --git a/tests/drivers/flash/common/boards/fpb_ra4e1.conf b/tests/drivers/flash/common/boards/fpb_ra4e1.conf
new file mode 100644
index 00000000000..234ba7edbbe
--- /dev/null
+++ b/tests/drivers/flash/common/boards/fpb_ra4e1.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_TEST_DRIVER_FLASH_SIZE=524288
diff --git a/tests/drivers/flash/common/boards/fpb_ra4e1.overlay b/tests/drivers/flash/common/boards/fpb_ra4e1.overlay
new file mode 100644
index 00000000000..a1c3e5f5fed
--- /dev/null
+++ b/tests/drivers/flash/common/boards/fpb_ra4e1.overlay
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* Set 2 last blocks of the code flash as storage partition */
+		storage_partition: partition@70000 {
+			label = "storage";
+			reg = <0x70000 DT_SIZE_K(64)>;
+		};
+	};
+};
diff --git a/tests/drivers/flash/common/boards/mx25r64_non_quad.overlay b/tests/drivers/flash/common/boards/mx25r64_non_quad.overlay
new file mode 100644
index 00000000000..5ddb41fb1d0
--- /dev/null
+++ b/tests/drivers/flash/common/boards/mx25r64_non_quad.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&mx25r64 {
+	writeoc = "pp";
+	readoc = "fastread";
+};
diff --git a/tests/drivers/flash/common/boards/silabs_s2_lpwrite.overlay b/tests/drivers/flash/common/boards/silabs_s2_lpwrite.overlay
new file mode 100644
index 00000000000..a28312e6e50
--- /dev/null
+++ b/tests/drivers/flash/common/boards/silabs_s2_lpwrite.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&dma0 {
+	status = "okay";
+};
+
+&msc {
+	dmas = <&dma0 DMA_REQSEL_MSCWDATA>;
+	low-power-write;
+};
diff --git a/tests/drivers/flash/common/boards/voice_ra4e1.conf b/tests/drivers/flash/common/boards/voice_ra4e1.conf
new file mode 100644
index 00000000000..234ba7edbbe
--- /dev/null
+++ b/tests/drivers/flash/common/boards/voice_ra4e1.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_TEST_DRIVER_FLASH_SIZE=524288
diff --git a/tests/drivers/flash/common/boards/voice_ra4e1.overlay b/tests/drivers/flash/common/boards/voice_ra4e1.overlay
new file mode 100644
index 00000000000..a1c3e5f5fed
--- /dev/null
+++ b/tests/drivers/flash/common/boards/voice_ra4e1.overlay
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* Set 2 last blocks of the code flash as storage partition */
+		storage_partition: partition@70000 {
+			label = "storage";
+			reg = <0x70000 DT_SIZE_K(64)>;
+		};
+	};
+};
diff --git a/tests/drivers/flash/common/boards/xg24_rb4187c.overlay b/tests/drivers/flash/common/boards/xg24_rb4187c.overlay
new file mode 100644
index 00000000000..659beb7dfb0
--- /dev/null
+++ b/tests/drivers/flash/common/boards/xg24_rb4187c.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&dma0 {
+	status = "okay";
+};
+
+&msc {
+	dmas = <&dma0 DMA_REQSEL_MSCWDATA>;
+};
diff --git a/tests/drivers/flash/common/boards/xg29_rb4412a.overlay b/tests/drivers/flash/common/boards/xg29_rb4412a.overlay
new file mode 100644
index 00000000000..c5d1c35f027
--- /dev/null
+++ b/tests/drivers/flash/common/boards/xg29_rb4412a.overlay
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&dma0 {
+	status = "okay";
+};
+
+&msc {
+	dmas = <&dma0 DMA_REQSEL_MSCWDATA>;
+};
+
+
+/* Disable jedec spi nor flash to test internal flash */
+
+/ {
+
+	aliases {
+		/delete-property/ spi-flash0;
+	};
+};
+
+/delete-node/ &mx25r80;
diff --git a/tests/drivers/flash/common/socs/esp32c3_usb.conf b/tests/drivers/flash/common/socs/esp32c3_usb.conf
new file mode 100644
index 00000000000..2bcf636958b
--- /dev/null
+++ b/tests/drivers/flash/common/socs/esp32c3_usb.conf
@@ -0,0 +1 @@
+CONFIG_HEAP_MEM_POOL_SIZE=16384
diff --git a/tests/drivers/flash/common/src/main.c b/tests/drivers/flash/common/src/main.c
index 54b868a9234..dce1d79f653 100644
--- a/tests/drivers/flash/common/src/main.c
+++ b/tests/drivers/flash/common/src/main.c
@@ -462,8 +462,8 @@ ZTEST(flash_driver, test_flash_copy)
 
 	/* copy with overlapping ranges should fail */
 	test_flash_copy_inner(flash_dev, page_info.start_offset, flash_dev,
-			      page_info.start_offset + 32, page_info.size - 32, buf, sizeof(buf),
-			      -EINVAL);
+			      page_info.start_offset + (page_info.size / 4),
+			      page_info.size - (page_info.size / 4), buf, sizeof(buf), -EINVAL);
 }
 
 ZTEST_SUITE(flash_driver, NULL, NULL, flash_driver_before, NULL, NULL);
diff --git a/tests/drivers/flash/common/testcase.yaml b/tests/drivers/flash/common/testcase.yaml
index 9f847204d64..4010b82b931 100644
--- a/tests/drivers/flash/common/testcase.yaml
+++ b/tests/drivers/flash/common/testcase.yaml
@@ -48,6 +48,7 @@ tests:
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
       - nrf54h20dk/nrf54h20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
   drivers.flash.common.tfm_ns:
     build_only: true
     filter: (CONFIG_FLASH_HAS_DRIVER_ENABLED and CONFIG_TRUSTED_EXECUTION_NONSECURE
@@ -66,7 +67,7 @@ tests:
   drivers.flash.common.mr_canhubk3_sfdp_runtime:
     platform_allow: mr_canhubk3
     extra_configs:
-      - CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME=y
+      - CONFIG_FLASH_NXP_S32_QSPI_SFDP_RUNTIME=y
   drivers.flash.common.spi_nor:
     platform_allow: nrf52840dk/nrf52840
     extra_configs:
@@ -95,3 +96,33 @@ tests:
       - gd32vf103v_eval
       - gd32a503v_eval
       - gd32f470i_eval
+  drivers.flash.common.silabs.dma:
+    platform_allow:
+      - xg24_rb4187c
+      - xg29_rb4412a
+    extra_configs:
+      - CONFIG_DMA=y
+  drivers.flash.common.silabs.dma.lpwrite:
+    platform_allow:
+      - xg24_rb4187c
+      - xg29_rb4412a
+    extra_configs:
+      - CONFIG_DMA=y
+    extra_args:
+      - EXTRA_DTC_OVERLAY_FILE=boards/silabs_s2_lpwrite.overlay
+  drivers.flash.common.silabs.dma_read:
+    platform_allow:
+      - xg24_rb4187c
+      - xg29_rb4412a
+    extra_configs:
+      - CONFIG_DMA=y
+      - CONFIG_SOC_FLASH_SILABS_S2_DMA_READ=y
+  drivers.flash.common.non_quad_mode:
+    extra_args:
+      - EXTRA_DTC_OVERLAY_FILE=boards/mx25r64_non_quad.overlay
+    integration_platforms:
+      - nrf52840dk/nrf52840
+      - nrf5340dk/nrf5340/cpuapp
+    platform_allow:
+      - nrf52840dk/nrf52840
+      - nrf5340dk/nrf5340/cpuapp
diff --git a/tests/drivers/flash/negative_tests/testcase.yaml b/tests/drivers/flash/negative_tests/testcase.yaml
index 11a669c981f..5d2441f002e 100644
--- a/tests/drivers/flash/negative_tests/testcase.yaml
+++ b/tests/drivers/flash/negative_tests/testcase.yaml
@@ -9,3 +9,4 @@ tests:
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
       - nrf54h20dk/nrf54h20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
diff --git a/tests/drivers/flash/stm32/boards/google_icetower.overlay b/tests/drivers/flash/stm32/boards/google_icetower.overlay
new file mode 100644
index 00000000000..044890a3a73
--- /dev/null
+++ b/tests/drivers/flash/stm32/boards/google_icetower.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2024 Google Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* Reserve 4KiB of flash for storage_partition. */
+		storage_partition: partition@1f000 {
+			label = "storage";
+			reg = <0x0001f000 DT_SIZE_K(4)>;
+		};
+	};
+};
diff --git a/tests/drivers/flash/stm32/boards/stm32h750b_dk.overlay b/tests/drivers/flash/stm32/boards/stm32h750b_dk.overlay
index ad7464fb622..b90c3443638 100644
--- a/tests/drivers/flash/stm32/boards/stm32h750b_dk.overlay
+++ b/tests/drivers/flash/stm32/boards/stm32h750b_dk.overlay
@@ -4,6 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+/delete-node/ &storage_partition;
+
 &flash0 {
 	partitions {
 		compatible = "fixed-partitions";
diff --git a/tests/drivers/flash/stm32/prj.conf b/tests/drivers/flash/stm32/prj.conf
index 7f73471f718..5c998239300 100644
--- a/tests/drivers/flash/stm32/prj.conf
+++ b/tests/drivers/flash/stm32/prj.conf
@@ -5,3 +5,4 @@ CONFIG_FLASH=y
 CONFIG_FLASH_EX_OP_ENABLED=y
 
 CONFIG_MAIN_STACK_SIZE=2048
+CONFIG_ZTEST_STACK_SIZE=2048
diff --git a/tests/drivers/flash/stm32/src/main.c b/tests/drivers/flash/stm32/src/main.c
index 9356535f8d9..8b47a64b1a9 100644
--- a/tests/drivers/flash/stm32/src/main.c
+++ b/tests/drivers/flash/stm32/src/main.c
@@ -10,6 +10,7 @@
 #include <zephyr/drivers/flash/stm32_flash_api_extensions.h>
 #include <zephyr/devicetree.h>
 #include <zephyr/storage/flash_map.h>
+#include <zephyr/sys/barrier.h>
 
 #define TEST_AREA	 storage_partition
 #define TEST_AREA_OFFSET FIXED_PARTITION_OFFSET(TEST_AREA)
@@ -200,15 +201,46 @@ static void flash_cr_unlock(void)
 {
 	FLASH_TypeDef *regs = (FLASH_TypeDef *)TEST_AREA_DEVICE_REG;
 
+#ifdef CONFIG_SOC_SERIES_STM32H7X
+	regs->KEYR1 = FLASH_KEY1;
+	regs->KEYR1 = FLASH_KEY2;
+#ifdef DUAL_BANK
+	regs->KEYR2 = FLASH_KEY1;
+	regs->KEYR2 = FLASH_KEY2;
+#endif /* DUAL_BANK */
+#else /* CONFIG_SOC_SERIES_STM32H7X */
 	regs->KEYR = FLASH_KEY1;
 	regs->KEYR = FLASH_KEY2;
+#endif /* CONFIG_SOC_SERIES_STM32H7X */
+	barrier_dsync_fence_full();
 }
 
-static bool flash_cr_locked(void)
+static bool flash_cr_is_locked(void)
 {
 	FLASH_TypeDef *regs = (FLASH_TypeDef *)TEST_AREA_DEVICE_REG;
 
+#ifdef CONFIG_SOC_SERIES_STM32H7X
+	return regs->CR1 & FLASH_CR_LOCK;
+#ifdef DUAL_BANK
+	return (regs->CR1 & FLASH_CR_LOCK) && (regs->CR2 & FLASH_CR_LOCK);
+#endif /* DUAL_BANK */
+#else /* CONFIG_SOC_SERIES_STM32H7X */
 	return regs->CR & FLASH_CR_LOCK;
+#endif /* CONFIG_SOC_SERIES_STM32H7X */
+}
+
+static bool flash_cr_is_unlocked(void)
+{
+	FLASH_TypeDef *regs = (FLASH_TypeDef *)TEST_AREA_DEVICE_REG;
+
+#ifdef CONFIG_SOC_SERIES_STM32H7X
+	return !(regs->CR1 & FLASH_CR_LOCK);
+#ifdef DUAL_BANK
+	return !((regs->CR1 & FLASH_CR_LOCK) || (regs->CR2 & FLASH_CR_LOCK));
+#endif /* DUAL_BANK */
+#else /* CONFIG_SOC_SERIES_STM32H7X */
+	return !(regs->CR & FLASH_CR_LOCK);
+#endif /* CONFIG_SOC_SERIES_STM32H7X */
 }
 
 ZTEST(flash_stm32, test_stm32_block_registers)
@@ -227,24 +259,27 @@ ZTEST(flash_stm32, test_stm32_block_registers)
 	flash_stm32_option_bytes_lock(flash_dev, false);
 	/* Clear Bus Fault pending bit */
 	SCB->SHCSR &= ~SCB_SHCSR_BUSFAULTPENDED_Msk;
+	barrier_dsync_fence_full();
 	__set_FAULTMASK(0);
 	zassert_true(flash_opt_locked(), "OPT unlocked after being blocked");
 
 	/* Test CR lock. */
-	zassert_true(flash_cr_locked(), "CR should be locked by default");
+	zassert_true(flash_cr_is_locked(), "CR should be locked by default");
 	TC_PRINT("Unlocking CR\n");
 	flash_cr_unlock();
-	zassert_false(flash_cr_locked(), "Unable to unlock CR");
+	zassert_true(flash_cr_is_unlocked(), "Unable to unlock CR");
 	TC_PRINT("Blocking CR\n");
 	flash_ex_op(flash_dev, FLASH_STM32_EX_OP_BLOCK_CONTROL_REG, (uintptr_t)NULL, NULL);
-	zassert_true(flash_cr_locked(), "Blocking CR didn't lock CR");
+	zassert_true(flash_cr_is_locked(), "Blocking CR didn't lock CR");
 	__set_FAULTMASK(1);
 	TC_PRINT("Try to unlock blocked CR\n");
 	flash_cr_unlock();
 	/* Clear Bus Fault pending bit */
 	SCB->SHCSR &= ~SCB_SHCSR_BUSFAULTPENDED_Msk;
+	barrier_dsync_fence_full();
 	__set_FAULTMASK(0);
-	zassert_true(flash_cr_locked(), "CR unlocked after being blocked");
+	/* Make sure previous write is completed. */
+	zassert_true(flash_cr_is_locked(), "CR unlocked after being blocked");
 }
 #endif
 
diff --git a/tests/drivers/flash/stm32/testcase.yaml b/tests/drivers/flash/stm32/testcase.yaml
index 9a5605ac3f6..b7715bb069a 100644
--- a/tests/drivers/flash/stm32/testcase.yaml
+++ b/tests/drivers/flash/stm32/testcase.yaml
@@ -47,7 +47,19 @@ tests:
       - stm32h735g_disco
       - stm32h750b_dk
       - stm32h745i_disco/stm32h745xx/m7
+      - nucleo_h743zi
+      - google_icetower
     extra_configs:
       - CONFIG_FLASH_STM32_READOUT_PROTECTION=y
+      - CONFIG_FLASH_STM32_WRITE_PROTECT=y
     filter: dt_compat_enabled("st,stm32h7-flash-controller") and
       dt_label_with_parent_compat_enabled("storage_partition", "fixed-partitions")
+  drivers.flash.stm32.h7.block_registers:
+    platform_allow:
+      - nucleo_h743zi
+      - google_icetower
+    extra_configs:
+      - CONFIG_FLASH_STM32_BLOCK_REGISTERS=y
+    filter: dt_compat_enabled("st,stm32h7-flash-controller") and
+            dt_label_with_parent_compat_enabled("storage_partition", "fixed-partitions") and
+            CONFIG_SOC_SERIES_STM32H7X
diff --git a/tests/drivers/flash_simulator/flash_sim_impl/boards/native_posix.overlay b/tests/drivers/flash_simulator/flash_sim_impl/boards/native_posix.overlay
deleted file mode 100644
index 59b29bd8512..00000000000
--- a/tests/drivers/flash_simulator/flash_sim_impl/boards/native_posix.overlay
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Copyright (c) 2023 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "native_sim.overlay"
diff --git a/tests/drivers/flash_simulator/flash_sim_impl/boards/native_posix_native_64.overlay b/tests/drivers/flash_simulator/flash_sim_impl/boards/native_posix_native_64.overlay
deleted file mode 100644
index 9fe8b9c2160..00000000000
--- a/tests/drivers/flash_simulator/flash_sim_impl/boards/native_posix_native_64.overlay
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Copyright (c) 2024 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include "native_posix.overlay"
diff --git a/tests/drivers/flash_simulator/flash_sim_impl/testcase.yaml b/tests/drivers/flash_simulator/flash_sim_impl/testcase.yaml
index 8acbd3373db..c5794c735ba 100644
--- a/tests/drivers/flash_simulator/flash_sim_impl/testcase.yaml
+++ b/tests/drivers/flash_simulator/flash_sim_impl/testcase.yaml
@@ -6,8 +6,6 @@ tests:
   drivers.flash.flash_simulator:
     platform_allow:
       - qemu_x86
-      - native_posix
-      - native_posix/native/64
       - native_sim
       - native_sim/native/64
       - nucleo_f411re
@@ -17,8 +15,6 @@ tests:
     extra_args: CONFIG_FLASH_SIMULATOR_EXPLICIT_ERASE=n
     platform_allow:
       - qemu_x86
-      - native_posix
-      - native_posix/native/64
       - native_sim
       - native_sim/native/64
       - nucleo_f411re
@@ -32,14 +28,12 @@ tests:
   drivers.flash.flash_simulator.native_erase_value_0x00:
     extra_args: DTC_OVERLAY_FILE=boards/native_ev_0x00.overlay
     platform_allow:
-      - native_posix
       - native_sim
     integration_platforms:
       - native_sim
   drivers.flash.flash_simulator.native_64_erase_value_0x00:
     extra_args: DTC_OVERLAY_FILE=boards/native_64_ev_0x00.overlay
     platform_allow:
-      - native_posix/native/64
       - native_sim/native/64
     integration_platforms:
       - native_sim/native/64
diff --git a/tests/drivers/flash_simulator/flash_sim_reboot/testcase.yaml b/tests/drivers/flash_simulator/flash_sim_reboot/testcase.yaml
index 069bbac09c9..804c26e14b6 100644
--- a/tests/drivers/flash_simulator/flash_sim_reboot/testcase.yaml
+++ b/tests/drivers/flash_simulator/flash_sim_reboot/testcase.yaml
@@ -5,6 +5,7 @@ common:
 tests:
   drivers.flash.flash_simulator.boot_no_erase:
     timeout: 5
+    expect_reboot: true
     platform_allow: mps2/an385
     integration_platforms:
       - mps2/an385
diff --git a/tests/drivers/gnss/gnss_api/testcase.yaml b/tests/drivers/gnss/gnss_api/testcase.yaml
index 7ce2c22de3e..600cf2203b7 100644
--- a/tests/drivers/gnss/gnss_api/testcase.yaml
+++ b/tests/drivers/gnss/gnss_api/testcase.yaml
@@ -5,3 +5,5 @@ tests:
   drivers.gnss.gnss_api:
     filter: dt_alias_exists("gnss")
     timeout: 300
+    tags:
+      - gnss
diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/pico_plus2_rp2350b_m33.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/pico_plus2_rp2350b_m33.overlay
new file mode 100644
index 00000000000..fa6f5cb4a44
--- /dev/null
+++ b/tests/drivers/gpio/gpio_api_1pin/boards/pico_plus2_rp2350b_m33.overlay
@@ -0,0 +1,8 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 TOKITA Hiroshi
+ */
+
+/* Pico Plus2 is pin-compatible with the Raspberry Pi Pico 2, so reuse. */
+#include "rpi_pico2_rp2350a_m33.overlay"
diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/rza3ul_smarc.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/rza3ul_smarc.overlay
new file mode 100644
index 00000000000..1d0abc94c69
--- /dev/null
+++ b/tests/drivers/gpio/gpio_api_1pin/boards/rza3ul_smarc.overlay
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		led0 = &led_0;
+	};
+
+	gpio-led {
+		compatible = "gpio-leds";
+		led_0: led_0 {
+			gpios = <&gpio1 3 0>;
+		};
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpio1 {
+	irqs = <3 15>;
+	status = "okay";
+};
diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/rzg2l_smarc_r9a07g044l23gbg_cm33.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/rzg2l_smarc_r9a07g044l23gbg_cm33.overlay
new file mode 100644
index 00000000000..f5aae70d388
--- /dev/null
+++ b/tests/drivers/gpio/gpio_api_1pin/boards/rzg2l_smarc_r9a07g044l23gbg_cm33.overlay
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		led0 = &led_0;
+	};
+
+	gpio-led {
+		compatible = "gpio-leds";
+
+		led_0: led_0 {
+			gpios = <&gpio43 1 0>;
+		};
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpio43 {
+	irqs = <1 1>;
+	status = "okay";
+};
diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/rzg2lc_smarc_r9a07g044c22gbg_cm33.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/rzg2lc_smarc_r9a07g044c22gbg_cm33.overlay
new file mode 100644
index 00000000000..f5aae70d388
--- /dev/null
+++ b/tests/drivers/gpio/gpio_api_1pin/boards/rzg2lc_smarc_r9a07g044c22gbg_cm33.overlay
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		led0 = &led_0;
+	};
+
+	gpio-led {
+		compatible = "gpio-leds";
+
+		led_0: led_0 {
+			gpios = <&gpio43 1 0>;
+		};
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpio43 {
+	irqs = <1 1>;
+	status = "okay";
+};
diff --git a/tests/drivers/gpio/gpio_api_1pin/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay b/tests/drivers/gpio/gpio_api_1pin/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay
new file mode 100644
index 00000000000..48f0d452d09
--- /dev/null
+++ b/tests/drivers/gpio/gpio_api_1pin/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		led0 = &led_0;
+	};
+
+	gpio-led {
+		compatible = "gpio-leds";
+		led_0: led_0 {
+			gpios = <&gpio43 1 0>;
+		};
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpio43 {
+	irqs = <1 1>;
+	status = "okay";
+};
diff --git a/tests/drivers/gpio/gpio_api_1pin/testcase.yaml b/tests/drivers/gpio/gpio_api_1pin/testcase.yaml
index dd6a1149a25..95cbb864561 100644
--- a/tests/drivers/gpio/gpio_api_1pin/testcase.yaml
+++ b/tests/drivers/gpio/gpio_api_1pin/testcase.yaml
@@ -13,7 +13,11 @@ tests:
     platform_exclude:
       - mps2/an385
       - mps2/an521/cpu0
-      - neorv32
+      - mps2/an383
+      - mps2/an386
+      - mps2/an500
+      - neorv32/neorv32/minimalboot
+      - neorv32/neorv32/up5kdemo
   drivers.gpio.1pin.aw9523b:
     tags:
       - drivers
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/gpio/gpio_basic_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..3af79567691
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpio1 10 0>;
+		in-gpios = <&gpio1 11 0>;
+	};
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay b/tests/drivers/gpio/gpio_basic_api/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..2170eac1179
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15_dvk_nrf54l15_cpuapp.overlay"
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/bl54l15_dvk_nrf54l15_cpuflpr_xip.overlay b/tests/drivers/gpio/gpio_basic_api/boards/bl54l15_dvk_nrf54l15_cpuflpr_xip.overlay
new file mode 100644
index 00000000000..2170eac1179
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/bl54l15_dvk_nrf54l15_cpuflpr_xip.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15_dvk_nrf54l15_cpuapp.overlay"
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/gpio/gpio_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..3af79567691
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpio1 10 0>;
+		in-gpios = <&gpio1 11 0>;
+	};
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay b/tests/drivers/gpio/gpio_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..9b848a08370
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15u_dvk_nrf54l15_cpuapp.overlay"
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuflpr_xip.overlay b/tests/drivers/gpio/gpio_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuflpr_xip.overlay
new file mode 100644
index 00000000000..9b848a08370
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuflpr_xip.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15u_dvk_nrf54l15_cpuapp.overlay"
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/imx8mm_evk_mimx8mm6_a53.overlay b/tests/drivers/gpio/gpio_basic_api/boards/imx8mm_evk_mimx8mm6_a53.overlay
new file mode 100644
index 00000000000..74dc34e872a
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/imx8mm_evk_mimx8mm6_a53.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/{
+	resources {
+		compatible = "test-gpio-basic-api";
+		/*
+		 * Use connector J1003 Pin-12 GPIO.1 which connect to pca6416 P1_2 as input
+		 * GPIO, and connector J1003 Pin-16 GPIO.4 which connect to pca6416 P1_5 as
+		 * output GPIO, connect these two pins with a Dupont Line.
+		 */
+		out-gpios = <&gpio_exp1 10 0>;
+		in-gpios = <&gpio_exp1 13 0>;
+	};
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/imx8mn_evk_mimx8mn6_a53.overlay b/tests/drivers/gpio/gpio_basic_api/boards/imx8mn_evk_mimx8mn6_a53.overlay
new file mode 100644
index 00000000000..74dc34e872a
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/imx8mn_evk_mimx8mn6_a53.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/{
+	resources {
+		compatible = "test-gpio-basic-api";
+		/*
+		 * Use connector J1003 Pin-12 GPIO.1 which connect to pca6416 P1_2 as input
+		 * GPIO, and connector J1003 Pin-16 GPIO.4 which connect to pca6416 P1_5 as
+		 * output GPIO, connect these two pins with a Dupont Line.
+		 */
+		out-gpios = <&gpio_exp1 10 0>;
+		in-gpios = <&gpio_exp1 13 0>;
+	};
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/imx8mp_evk_mimx8ml8_a53.overlay b/tests/drivers/gpio/gpio_basic_api/boards/imx8mp_evk_mimx8ml8_a53.overlay
new file mode 100644
index 00000000000..c43cf4c1b1b
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/imx8mp_evk_mimx8ml8_a53.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/{
+	resources {
+		compatible = "test-gpio-basic-api";
+		/*
+		 * Use connector J21 GPIO.1 which connect to pca6416 EXP_P1_0 as input
+		 * GPIO, and connector J21 GPIO.4 which connect to pca6416 EXP_P1_3 as
+		 * output GPIO, connect these two pins with a Dupont Line.
+		 */
+		out-gpios = <&gpio_exp1 8 0>;
+		in-gpios = <&gpio_exp1 11 0>;
+	};
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/it515xx_evb.overlay b/tests/drivers/gpio/gpio_basic_api/boards/it515xx_evb.overlay
new file mode 100644
index 00000000000..002e52a8d3e
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/it515xx_evb.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 ITE Corporation. All Rights Reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpioa 3 0>; /* GPIOA.3 */
+		in-gpios = <&gpioe 4 0>;  /* GPIOE.4 */
+	};
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/kv260_r5.overlay b/tests/drivers/gpio/gpio_basic_api/boards/kv260_r5.overlay
new file mode 100644
index 00000000000..02ec261b512
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/kv260_r5.overlay
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025 Advanced Micro Devices, Inc. (AMD)
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	loop {
+		compatible = "test-gpio-basic-api";
+
+		out-gpios = <&psgpio_bank3 0 0>; /* GPIOPS BANK 3 PIN 0 */
+		in-gpios = <&psgpio_bank3 1 0>; /* GPIOPS BANK 3 PIN 1 */
+	};
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/max32690evkit_max32690_m4.overlay b/tests/drivers/gpio/gpio_basic_api/boards/max32690evkit_max32690_m4.overlay
index 05dad16b30f..da1716bb503 100644
--- a/tests/drivers/gpio/gpio_basic_api/boards/max32690evkit_max32690_m4.overlay
+++ b/tests/drivers/gpio/gpio_basic_api/boards/max32690evkit_max32690_m4.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2023-2024 Analog Devices, Inc.
+ * Copyright (c) 2023-2025 Analog Devices, Inc.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -7,7 +7,7 @@
 / {
 	resources {
 		compatible = "test-gpio-basic-api";
-		out-gpios = <&gpio2 7 0>;
-		in-gpios = <&gpio2 8 0>;
+		out-gpios = <&gpio0 7 0>;
+		in-gpios = <&gpio0 8 0>;
 	};
 };
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/max78000evkit_max78000_m4.overlay b/tests/drivers/gpio/gpio_basic_api/boards/max78000evkit_max78000_m4.overlay
new file mode 100644
index 00000000000..4b2e293ef2a
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/max78000evkit_max78000_m4.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpio0 12 0>;
+		in-gpios = <&gpio0 13 0>;
+	};
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/max78000fthr_max78000_m4.overlay b/tests/drivers/gpio/gpio_basic_api/boards/max78000fthr_max78000_m4.overlay
new file mode 100644
index 00000000000..49d42fd7f61
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/max78000fthr_max78000_m4.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpio1 0 0>;
+		in-gpios = <&gpio1 1 0>;
+	};
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.conf b/tests/drivers/gpio/gpio_basic_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.conf
new file mode 100644
index 00000000000..b9d02cf11d5
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.conf
@@ -0,0 +1 @@
+CONFIG_SKIP_PULL_TEST=y
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/tests/drivers/gpio/gpio_basic_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
new file mode 100644
index 00000000000..408cb99456c
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
@@ -0,0 +1,16 @@
+/*
+ * Copyright (c) 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* loopback with arduino header D0 and D1 */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		status = "okay";
+		out-gpios = <&arduino_header 6 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL | GPIO_PULL_UP)>;
+		in-gpios = <&arduino_header 7 (GPIO_ACTIVE_HIGH | GPIO_PUSH_PULL | GPIO_PULL_UP)>;
+	};
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/neorv32.overlay b/tests/drivers/gpio/gpio_basic_api/boards/neorv32_neorv32_up5kdemo.overlay
similarity index 100%
rename from tests/drivers/gpio/gpio_basic_api/boards/neorv32.overlay
rename to tests/drivers/gpio/gpio_basic_api/boards/neorv32_neorv32_up5kdemo.overlay
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/nrf54l09pdk_nrf54l09_common.overlay b/tests/drivers/gpio/gpio_basic_api/boards/nrf54l09pdk_nrf54l09_common.overlay
new file mode 100644
index 00000000000..8eb1b3c9f9f
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/nrf54l09pdk_nrf54l09_common.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpio1 10 0>;
+		in-gpios = <&gpio1 11 0>;
+	};
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay b/tests/drivers/gpio/gpio_basic_api/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay
new file mode 100644
index 00000000000..7eee797278b
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "nrf54l09pdk_nrf54l09_common.overlay"
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/nrf54l09pdk_nrf54l09_cpuflpr.overlay b/tests/drivers/gpio/gpio_basic_api/boards/nrf54l09pdk_nrf54l09_cpuflpr.overlay
new file mode 100644
index 00000000000..b0c42fd3d2a
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/nrf54l09pdk_nrf54l09_cpuflpr.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "nrf54l09pdk_nrf54l09_common.overlay"
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/nrf54l20pdk_nrf54l20_common.overlay b/tests/drivers/gpio/gpio_basic_api/boards/nrf54l20pdk_nrf54l20_common.overlay
new file mode 100644
index 00000000000..8eb1b3c9f9f
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/nrf54l20pdk_nrf54l20_common.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpio1 10 0>;
+		in-gpios = <&gpio1 11 0>;
+	};
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/nrf54l20pdk_nrf54l20_cpuapp.overlay b/tests/drivers/gpio/gpio_basic_api/boards/nrf54l20pdk_nrf54l20_cpuapp.overlay
index 8eb1b3c9f9f..3ed56c4a6c8 100644
--- a/tests/drivers/gpio/gpio_basic_api/boards/nrf54l20pdk_nrf54l20_cpuapp.overlay
+++ b/tests/drivers/gpio/gpio_basic_api/boards/nrf54l20pdk_nrf54l20_cpuapp.overlay
@@ -4,18 +4,4 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/ {
-	resources {
-		compatible = "test-gpio-basic-api";
-		out-gpios = <&gpio1 10 0>;
-		in-gpios = <&gpio1 11 0>;
-	};
-};
-
-&gpiote20 {
-	status = "okay";
-};
-
-&gpio1 {
-	status = "okay";
-};
+#include "nrf54l20pdk_nrf54l20_common.overlay"
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/nrf54l20pdk_nrf54l20_cpuflpr.overlay b/tests/drivers/gpio/gpio_basic_api/boards/nrf54l20pdk_nrf54l20_cpuflpr.overlay
new file mode 100644
index 00000000000..91c033f0f94
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/nrf54l20pdk_nrf54l20_cpuflpr.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "nrf54l20pdk_nrf54l20_common.overlay"
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/gpio/gpio_basic_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..db939435dd1
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpio1 10 0>;
+		in-gpios = <&gpio1 11 0>;
+	};
+};
+
+&gpiote20 {
+	status = "okay";
+};
+
+&gpio1 {
+	status = "okay";
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/ophelia4ev_nrf54l15_cpuflpr.overlay b/tests/drivers/gpio/gpio_basic_api/boards/ophelia4ev_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..945d543e753
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/ophelia4ev_nrf54l15_cpuflpr.overlay
@@ -0,0 +1 @@
+#include "ophelia4ev_nrf54l15_cpuapp.overlay"
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/pico_plus2_rp2350b_m33.conf b/tests/drivers/gpio/gpio_basic_api/boards/pico_plus2_rp2350b_m33.conf
new file mode 100644
index 00000000000..b9d02cf11d5
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/pico_plus2_rp2350b_m33.conf
@@ -0,0 +1 @@
+CONFIG_SKIP_PULL_TEST=y
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/pico_plus2_rp2350b_m33.overlay b/tests/drivers/gpio/gpio_basic_api/boards/pico_plus2_rp2350b_m33.overlay
new file mode 100644
index 00000000000..3566e32fc34
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/pico_plus2_rp2350b_m33.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2024 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Pico Plus2 is pin-compatible with the Raspberry Pi Pico, so reuse. */
+#include "rpi_pico.overlay"
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rpi_pico.overlay b/tests/drivers/gpio/gpio_basic_api/boards/rpi_pico.overlay
new file mode 100644
index 00000000000..61a0bf2bf95
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/rpi_pico.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&pico_header 12 GPIO_ACTIVE_HIGH>;
+		in-gpios = <&pico_header 13 GPIO_ACTIVE_HIGH>;
+	};
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rpi_pico2_rp2350a_m33.conf b/tests/drivers/gpio/gpio_basic_api/boards/rpi_pico2_rp2350a_m33.conf
new file mode 100644
index 00000000000..b9d02cf11d5
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/rpi_pico2_rp2350a_m33.conf
@@ -0,0 +1 @@
+CONFIG_SKIP_PULL_TEST=y
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rpi_pico2_rp2350a_m33.overlay b/tests/drivers/gpio/gpio_basic_api/boards/rpi_pico2_rp2350a_m33.overlay
new file mode 100644
index 00000000000..eead4743d06
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/rpi_pico2_rp2350a_m33.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Pico 2 is compatible with the Pico 1, so reuse. */
+#include "rpi_pico.overlay"
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rza2m_evk.conf b/tests/drivers/gpio/gpio_basic_api/boards/rza2m_evk.conf
new file mode 100644
index 00000000000..b9d02cf11d5
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/rza2m_evk.conf
@@ -0,0 +1 @@
+CONFIG_SKIP_PULL_TEST=y
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rza2m_evk.overlay b/tests/drivers/gpio/gpio_basic_api/boards/rza2m_evk.overlay
new file mode 100644
index 00000000000..fd9fcf76dca
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/rza2m_evk.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+ #include <zephyr/dt-bindings/gpio/renesas-rza2m-gpio.h>
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpiog 2 0>;
+		in-gpios = <&gpiog 0 0>;
+		status = "okay";
+	};
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rza3ul_smarc.conf b/tests/drivers/gpio/gpio_basic_api/boards/rza3ul_smarc.conf
new file mode 100644
index 00000000000..b9d02cf11d5
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/rza3ul_smarc.conf
@@ -0,0 +1 @@
+CONFIG_SKIP_PULL_TEST=y
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rza3ul_smarc.overlay b/tests/drivers/gpio/gpio_basic_api/boards/rza3ul_smarc.overlay
new file mode 100644
index 00000000000..d0821d8c842
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/rza3ul_smarc.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
+		in-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpio1 {
+	irqs = <4 20>;
+	status = "okay";
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rzg2l_smarc_r9a07g044l23gbg_cm33.conf b/tests/drivers/gpio/gpio_basic_api/boards/rzg2l_smarc_r9a07g044l23gbg_cm33.conf
new file mode 100644
index 00000000000..b9d02cf11d5
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/rzg2l_smarc_r9a07g044l23gbg_cm33.conf
@@ -0,0 +1 @@
+CONFIG_SKIP_PULL_TEST=y
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rzg2l_smarc_r9a07g044l23gbg_cm33.overlay b/tests/drivers/gpio/gpio_basic_api/boards/rzg2l_smarc_r9a07g044l23gbg_cm33.overlay
new file mode 100644
index 00000000000..fba1f4baee3
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/rzg2l_smarc_r9a07g044l23gbg_cm33.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpio43 1 GPIO_ACTIVE_HIGH>;
+		in-gpios = <&gpio43 2 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpio43 {
+	irqs = <2 20>;
+	status = "okay";
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rzg2lc_smarc_r9a07g044c22gbg_cm33.conf b/tests/drivers/gpio/gpio_basic_api/boards/rzg2lc_smarc_r9a07g044c22gbg_cm33.conf
new file mode 100644
index 00000000000..b9d02cf11d5
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/rzg2lc_smarc_r9a07g044c22gbg_cm33.conf
@@ -0,0 +1 @@
+CONFIG_SKIP_PULL_TEST=y
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rzg2lc_smarc_r9a07g044c22gbg_cm33.overlay b/tests/drivers/gpio/gpio_basic_api/boards/rzg2lc_smarc_r9a07g044c22gbg_cm33.overlay
new file mode 100644
index 00000000000..3b2766f7b33
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/rzg2lc_smarc_r9a07g044c22gbg_cm33.overlay
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>;
+		in-gpios = <&gpio43 0 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpio4 {
+	irqs = <2 20>;
+	status = "okay";
+};
+
+&gpio43 {
+	irqs = <2 20>;
+	status = "okay";
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rzn2l_rsk.overlay b/tests/drivers/gpio/gpio_basic_api/boards/rzn2l_rsk.overlay
new file mode 100644
index 00000000000..85624d2667d
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/rzn2l_rsk.overlay
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+		in-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&pinctrl {
+	input_test: input_test {
+		group1 {
+			pinmux = <RZN_PINMUX(PORT_02, 0, 0)>;
+			input-enable;
+		};
+	};
+};
+
+&irq4 {
+	trigger-type = "falling";
+	pinctrl-0 = <&input_test>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&gpio2 {
+	irqs = <0 4>;
+	status = "okay";
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rzt2l_rsk.overlay b/tests/drivers/gpio/gpio_basic_api/boards/rzt2l_rsk.overlay
new file mode 100644
index 00000000000..baf12cf3263
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/rzt2l_rsk.overlay
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpio15 5 GPIO_ACTIVE_HIGH>;
+		in-gpios = <&gpio15 4 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&pinctrl {
+	input_test: input_test{
+		group1 {
+			pinmux = <RZT_PINMUX(PORT_15, 4, 4)>;
+			input-enable;
+		};
+	};
+};
+
+&irq3 {
+	trigger-type = "falling";
+	pinctrl-0 = <&input_test>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&gpio15 {
+	irqs = <4 3>;
+	status = "okay";
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay b/tests/drivers/gpio/gpio_basic_api/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay
new file mode 100644
index 00000000000..106f582dd8d
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/rzt2m_rsk_r9a07g075m24gbg_cr520.overlay
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+		in-gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&pinctrl {
+	input_test: input_test {
+		group1 {
+			pinmux = <RZT_PINMUX(PORT_02, 0, 0)>;
+			input-enable;
+		};
+	};
+};
+
+&irq4 {
+	trigger-type = "falling";
+	pinctrl-0 = <&input_test>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&gpio2 {
+	irqs = <0 4>;
+	status = "okay";
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.conf b/tests/drivers/gpio/gpio_basic_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.conf
new file mode 100644
index 00000000000..b9d02cf11d5
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.conf
@@ -0,0 +1 @@
+CONFIG_SKIP_PULL_TEST=y
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay b/tests/drivers/gpio/gpio_basic_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay
new file mode 100644
index 00000000000..fba1f4baee3
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/rzv2l_smarc_r9a07g054l23gbg_cm33.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpio43 1 GPIO_ACTIVE_HIGH>;
+		in-gpios = <&gpio43 2 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&gpio {
+	status = "okay";
+};
+
+&gpio43 {
+	irqs = <2 20>;
+	status = "okay";
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/siwx917_rb4338a-uulp.overlay b/tests/drivers/gpio/gpio_basic_api/boards/siwx917_rb4338a-uulp.overlay
new file mode 100644
index 00000000000..a440d62de0d
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/siwx917_rb4338a-uulp.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&uulpgpio 0 0>; /* WPK P14 */
+		in-gpios = <&uulpgpio 3 0>; /* WPK P18 */
+	};
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/siwx917_rb4338a.overlay b/tests/drivers/gpio/gpio_basic_api/boards/siwx917_rb4338a.overlay
new file mode 100644
index 00000000000..c4118086844
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/siwx917_rb4338a.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpiod 0 0>; /* WPK P28 */
+		in-gpios = <&gpiod 2 0>; /* WPK P32 */
+	};
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/boards/xg29_rb4412a.overlay b/tests/drivers/gpio/gpio_basic_api/boards/xg29_rb4412a.overlay
new file mode 100644
index 00000000000..8ea9208203a
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/boards/xg29_rb4412a.overlay
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Connect EXP4 (PC0) and EXP6 (PC1) of the Expansion Pin header
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpioc 0 0>; /* WPK EXP4 (PC0) */
+		in-gpios = <&gpioc 1 0>; /* WPK EXP6 (PC1) */
+	};
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/socs/esp32c3_usb.overlay b/tests/drivers/gpio/gpio_basic_api/socs/esp32c3_usb.overlay
new file mode 100644
index 00000000000..313d947d0c8
--- /dev/null
+++ b/tests/drivers/gpio/gpio_basic_api/socs/esp32c3_usb.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	resources {
+		compatible = "test-gpio-basic-api";
+		out-gpios = <&gpio0 4 0>;
+		in-gpios = <&gpio0 5 0>;
+	};
+};
diff --git a/tests/drivers/gpio/gpio_basic_api/testcase.yaml b/tests/drivers/gpio/gpio_basic_api/testcase.yaml
index d13e33c3ac0..71f55e493cc 100644
--- a/tests/drivers/gpio/gpio_basic_api/testcase.yaml
+++ b/tests/drivers/gpio/gpio_basic_api/testcase.yaml
@@ -56,8 +56,9 @@ tests:
       - mimxrt595_evk/mimxrt595s/cm33
       - mimxrt1020_evk
       - mimxrt1040_evk
-      - mimxrt1060_evk/mimxrt1062/qspi
+      - mimxrt1060_evk@A/mimxrt1062/qspi
       - mimxrt1060_evk@B/mimxrt1062/qspi
+      - mimxrt1060_evk@C/mimxrt1062/qspi
       - lpcxpresso55s69/lpc55s69/cpu0
       - lpcxpresso55s36
   drivers.gpio.2pin_arduino_customized:
@@ -71,7 +72,6 @@ tests:
       - mimxrt1020_evk
       - mimxrt1040_evk
       - mimxrt1060_evk/mimxrt1062/qspi
-      - mimxrt1060_evk@B/mimxrt1062/qspi
       - lpcxpresso55s69/lpc55s69/cpu0
       - lpcxpresso55s36
       - nucleo_wb09ke
@@ -107,3 +107,7 @@ tests:
             dt_nodelabel_enabled("arduino_i2c")
     extra_dtc_overlay_files:
       - boards/aw9523b_on_arduino_header.overlay
+  drivers.gpio.2pin_siwx91x_uulp:
+    platform_allow:
+      - siwx917_rb4338a
+    extra_args: "DTC_OVERLAY_FILE=boards/siwx917_rb4338a-uulp.overlay"
diff --git a/tests/drivers/gpio/gpio_get_direction/testcase.yaml b/tests/drivers/gpio/gpio_get_direction/testcase.yaml
index b66145fc9af..e25f75edffa 100644
--- a/tests/drivers/gpio/gpio_get_direction/testcase.yaml
+++ b/tests/drivers/gpio/gpio_get_direction/testcase.yaml
@@ -8,6 +8,6 @@ tests:
     # Fix exclude when we can exclude just sim run
     platform_exclude:
       - mps2/an385
-      - mps2/an521/cpu0
-      - neorv32
+      - neorv32/neorv32/minimalboot
+      - neorv32/neorv32/up5kdemo
     filter: dt_enabled_alias_with_parent_compat("led0", "gpio-leds")
diff --git a/tests/drivers/gpio/gpio_hogs/boards/xg29_rb4412a.overlay b/tests/drivers/gpio/gpio_hogs/boards/xg29_rb4412a.overlay
new file mode 100644
index 00000000000..48f0c5771da
--- /dev/null
+++ b/tests/drivers/gpio/gpio_hogs/boards/xg29_rb4412a.overlay
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		output-high-gpios = <&gpioc 1 GPIO_ACTIVE_LOW>;
+		output-low-gpios = <&gpioc 3 GPIO_ACTIVE_HIGH>;
+		input-gpios = <&gpioc 2 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&gpioc {
+	hog1 {
+		gpio-hog;
+		gpios = <1 GPIO_ACTIVE_LOW>;
+		output-high;
+	};
+
+	hog2 {
+		gpio-hog;
+		gpios = <2 GPIO_ACTIVE_HIGH>;
+		input;
+	};
+	hog3 {
+		gpio-hog;
+		gpios = <3 GPIO_ACTIVE_HIGH>;
+		output-low;
+	};
+};
diff --git a/tests/drivers/gpio/gpio_hogs/testcase.yaml b/tests/drivers/gpio/gpio_hogs/testcase.yaml
index fa3108e21e6..5c4878f5656 100644
--- a/tests/drivers/gpio/gpio_hogs/testcase.yaml
+++ b/tests/drivers/gpio/gpio_hogs/testcase.yaml
@@ -19,6 +19,7 @@ tests:
       - s32z2xxdc2/s32z270/rtu1
       - s32z2xxdc2@D/s32z270/rtu0
       - s32z2xxdc2@D/s32z270/rtu1
+      - xg29_rb4412a
     integration_platforms:
       - native_sim
       - native_sim/native/64
diff --git a/tests/drivers/gpio/gpio_ite_it8xxx2_v2/include/chip_chipregs.h b/tests/drivers/gpio/gpio_ite_it8xxx2_v2/include/chip_chipregs.h
index 67c86ccdc40..f7c3b91f034 100644
--- a/tests/drivers/gpio/gpio_ite_it8xxx2_v2/include/chip_chipregs.h
+++ b/tests/drivers/gpio/gpio_ite_it8xxx2_v2/include/chip_chipregs.h
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <../soc/ite/ec/common/chip_chipregs.h>
+#include <../soc/ite/ec/it8xxx2/chip_chipregs.h>
 
 /*
  * Macros for emulated hardware registers access.
diff --git a/tests/drivers/gpio/gpio_reserved_ranges/boards/native_posix.overlay b/tests/drivers/gpio/gpio_reserved_ranges/boards/native_sim.overlay
similarity index 100%
rename from tests/drivers/gpio/gpio_reserved_ranges/boards/native_posix.overlay
rename to tests/drivers/gpio/gpio_reserved_ranges/boards/native_sim.overlay
diff --git a/tests/drivers/gpio/gpio_reserved_ranges/boards/native_posix_native_64.overlay b/tests/drivers/gpio/gpio_reserved_ranges/boards/native_sim_native_64.overlay
similarity index 100%
rename from tests/drivers/gpio/gpio_reserved_ranges/boards/native_posix_native_64.overlay
rename to tests/drivers/gpio/gpio_reserved_ranges/boards/native_sim_native_64.overlay
diff --git a/tests/drivers/gpio/gpio_reserved_ranges/src/main.c b/tests/drivers/gpio/gpio_reserved_ranges/src/main.c
index ec2e795f0fe..351a525d2ea 100644
--- a/tests/drivers/gpio/gpio_reserved_ranges/src/main.c
+++ b/tests/drivers/gpio/gpio_reserved_ranges/src/main.c
@@ -9,6 +9,8 @@
 #include <zephyr/kernel.h>
 #include <zephyr/device.h>
 #include <zephyr/devicetree.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/gpio/gpio_utils.h>
 
 #define TEST_GPIO_1 DT_NODELABEL(test_gpio_1)
 #define TEST_GPIO_2 DT_NODELABEL(test_gpio_2)
diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra4l1.conf b/tests/drivers/i2c/i2c_api/boards/ek_ra4l1.conf
new file mode 100644
index 00000000000..3b626dd7fad
--- /dev/null
+++ b/tests/drivers/i2c/i2c_api/boards/ek_ra4l1.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SENSOR_GY271_QMC=y
diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra4l1.overlay b/tests/drivers/i2c/i2c_api/boards/ek_ra4l1.overlay
new file mode 100644
index 00000000000..c629e87a6e2
--- /dev/null
+++ b/tests/drivers/i2c/i2c_api/boards/ek_ra4l1.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		i2c-0 = &iic0;
+		gy271 = &iic0;
+	};
+};
diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra4m1.conf b/tests/drivers/i2c/i2c_api/boards/ek_ra4m1.conf
new file mode 100644
index 00000000000..3b626dd7fad
--- /dev/null
+++ b/tests/drivers/i2c/i2c_api/boards/ek_ra4m1.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SENSOR_GY271_QMC=y
diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra4m1.overlay b/tests/drivers/i2c/i2c_api/boards/ek_ra4m1.overlay
new file mode 100644
index 00000000000..0dfb29aaae6
--- /dev/null
+++ b/tests/drivers/i2c/i2c_api/boards/ek_ra4m1.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		i2c-0 = &iic1;
+		gy271 = &iic1;
+	};
+};
diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra8d1_sci_b_i2c.conf b/tests/drivers/i2c/i2c_api/boards/ek_ra8d1_sci_b_i2c.conf
new file mode 100644
index 00000000000..fc3333d47c7
--- /dev/null
+++ b/tests/drivers/i2c/i2c_api/boards/ek_ra8d1_sci_b_i2c.conf
@@ -0,0 +1,3 @@
+CONFIG_I2C=y
+CONFIG_ZTEST=y
+CONFIG_SENSOR_GY271_QMC=y
diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra8d1_sci_b_i2c.overlay b/tests/drivers/i2c/i2c_api/boards/ek_ra8d1_sci_b_i2c.overlay
new file mode 100644
index 00000000000..90f34e55440
--- /dev/null
+++ b/tests/drivers/i2c/i2c_api/boards/ek_ra8d1_sci_b_i2c.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		i2c-0 = &i2c4;
+		gy271 = &i2c4;
+	};
+};
+
+&sci4 {
+	status = "okay";
+
+	i2c4: i2c {
+		status = "okay";
+	};
+};
diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra8m1_sci_b_i2c.conf b/tests/drivers/i2c/i2c_api/boards/ek_ra8m1_sci_b_i2c.conf
new file mode 100644
index 00000000000..fc3333d47c7
--- /dev/null
+++ b/tests/drivers/i2c/i2c_api/boards/ek_ra8m1_sci_b_i2c.conf
@@ -0,0 +1,3 @@
+CONFIG_I2C=y
+CONFIG_ZTEST=y
+CONFIG_SENSOR_GY271_QMC=y
diff --git a/tests/drivers/i2c/i2c_api/boards/ek_ra8m1_sci_b_i2c.overlay b/tests/drivers/i2c/i2c_api/boards/ek_ra8m1_sci_b_i2c.overlay
new file mode 100644
index 00000000000..7aa8d7f0b0a
--- /dev/null
+++ b/tests/drivers/i2c/i2c_api/boards/ek_ra8m1_sci_b_i2c.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		i2c-0 = &i2c1;
+		gy271 = &i2c1;
+	};
+};
+
+&sci1 {
+	status = "okay";
+
+	i2c1: i2c {
+		status = "okay";
+	};
+};
diff --git a/tests/drivers/i2c/i2c_api/boards/fpb_ra4e1.conf b/tests/drivers/i2c/i2c_api/boards/fpb_ra4e1.conf
new file mode 100644
index 00000000000..3b626dd7fad
--- /dev/null
+++ b/tests/drivers/i2c/i2c_api/boards/fpb_ra4e1.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SENSOR_GY271_QMC=y
diff --git a/tests/drivers/i2c/i2c_api/boards/fpb_ra4e1.overlay b/tests/drivers/i2c/i2c_api/boards/fpb_ra4e1.overlay
new file mode 100644
index 00000000000..c629e87a6e2
--- /dev/null
+++ b/tests/drivers/i2c/i2c_api/boards/fpb_ra4e1.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		i2c-0 = &iic0;
+		gy271 = &iic0;
+	};
+};
diff --git a/tests/drivers/i2c/i2c_api/boards/mck_ra8t1_sci_b_i2c.conf b/tests/drivers/i2c/i2c_api/boards/mck_ra8t1_sci_b_i2c.conf
new file mode 100644
index 00000000000..fc3333d47c7
--- /dev/null
+++ b/tests/drivers/i2c/i2c_api/boards/mck_ra8t1_sci_b_i2c.conf
@@ -0,0 +1,3 @@
+CONFIG_I2C=y
+CONFIG_ZTEST=y
+CONFIG_SENSOR_GY271_QMC=y
diff --git a/tests/drivers/i2c/i2c_api/boards/mck_ra8t1_sci_b_i2c.overlay b/tests/drivers/i2c/i2c_api/boards/mck_ra8t1_sci_b_i2c.overlay
new file mode 100644
index 00000000000..2ce8ae69e5e
--- /dev/null
+++ b/tests/drivers/i2c/i2c_api/boards/mck_ra8t1_sci_b_i2c.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		i2c-0 = &i2c9;
+		gy271 = &i2c9;
+
+	};
+};
+
+&sci9 {
+	status = "okay";
+
+	i2c9: i2c {
+		status = "okay";
+		sda-output-delay = <250>;
+	};
+};
diff --git a/tests/drivers/i2c/i2c_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.conf b/tests/drivers/i2c/i2c_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.conf
new file mode 100644
index 00000000000..83547b4fe72
--- /dev/null
+++ b/tests/drivers/i2c/i2c_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.conf
@@ -0,0 +1 @@
+CONFIG_SENSOR_GY271_QMC=y
diff --git a/tests/drivers/i2c/i2c_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/tests/drivers/i2c/i2c_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
new file mode 100644
index 00000000000..65163d4b528
--- /dev/null
+++ b/tests/drivers/i2c/i2c_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
@@ -0,0 +1,9 @@
+/ {
+	aliases {
+		i2c-0 = &i2c0;
+	};
+};
+
+&i2c0 {
+	status = "okay";
+};
diff --git a/tests/drivers/i2c/i2c_api/testcase.yaml b/tests/drivers/i2c/i2c_api/testcase.yaml
index 039e77ad77e..c4aa0dbee75 100644
--- a/tests/drivers/i2c/i2c_api/testcase.yaml
+++ b/tests/drivers/i2c/i2c_api/testcase.yaml
@@ -5,3 +5,16 @@ tests:
       - drivers
       - i2c
     filter: dt_alias_exists("gy271")
+  drivers.i2c.renesas_sci_b_i2c.api:
+    depends_on: i2c
+    tags:
+      - drivers
+      - i2c
+    filter: dt_alias_exists("gy271") and CONFIG_I2C_RENESAS_RA_SCI_B
+    platform_allow:
+      - ek_ra8m1
+      - ek_ra8d1
+      - mck_ra8t1
+    extra_args:
+      - DTC_OVERLAY_FILE="./boards/${BOARD}_sci_b_i2c.overlay"
+      - CONF_FILE="./prj.conf ./boards/${BOARD}_sci_b_i2c.conf"
diff --git a/tests/drivers/i2c/i2c_emul/src/test_forwarding_buf.cpp b/tests/drivers/i2c/i2c_emul/src/test_forwarding_buf.cpp
index b7201b24f3a..7bf687a3a47 100644
--- a/tests/drivers/i2c/i2c_emul/src/test_forwarding_buf.cpp
+++ b/tests/drivers/i2c/i2c_emul/src/test_forwarding_buf.cpp
@@ -13,12 +13,8 @@
 namespace
 {
 
-#define GET_TARGET_DEVICE(node_id, prop, n) DEVICE_DT_GET(DT_PHANDLE_BY_IDX(node_id, prop, n)),
-
 /* Get the devicetree constants */
 constexpr const struct device *controller = DEVICE_DT_GET(CONTROLLER_LABEL);
-constexpr const struct device *targets[FORWARD_COUNT] = {
-	DT_FOREACH_PROP_ELEM(CONTROLLER_LABEL, forwards, GET_TARGET_DEVICE)};
 
 ZTEST(i2c_emul_forwarding, test_write_is_forwarded)
 {
diff --git a/tests/drivers/i2c/i2c_emul/src/test_forwarding_pio.cpp b/tests/drivers/i2c/i2c_emul/src/test_forwarding_pio.cpp
index 00a49c69024..9c3039efee1 100644
--- a/tests/drivers/i2c/i2c_emul/src/test_forwarding_pio.cpp
+++ b/tests/drivers/i2c/i2c_emul/src/test_forwarding_pio.cpp
@@ -12,12 +12,8 @@
 namespace
 {
 
-#define GET_TARGET_DEVICE(node_id, prop, n) DEVICE_DT_GET(DT_PHANDLE_BY_IDX(node_id, prop, n)),
-
 /* Get the devicetree constants */
 constexpr const struct device *controller = DEVICE_DT_GET(CONTROLLER_LABEL);
-constexpr const struct device *targets[FORWARD_COUNT] = {
-	DT_FOREACH_PROP_ELEM(CONTROLLER_LABEL, forwards, GET_TARGET_DEVICE)};
 
 ZTEST(i2c_emul_forwarding, test_write_is_forwarded)
 {
diff --git a/tests/drivers/i2c/i2c_emul/src/test_fowarding_common.cpp b/tests/drivers/i2c/i2c_emul/src/test_fowarding_common.cpp
index cf6c18de2cc..30099c810f5 100644
--- a/tests/drivers/i2c/i2c_emul/src/test_fowarding_common.cpp
+++ b/tests/drivers/i2c/i2c_emul/src/test_fowarding_common.cpp
@@ -12,12 +12,10 @@
 namespace
 {
 
-#define GET_TARGET_DEVICE(node_id, prop, n) DEVICE_DT_GET(DT_PHANDLE_BY_IDX(node_id, prop, n)),
-
 /* Get the devicetree constants */
 constexpr const struct device *controller = DEVICE_DT_GET(CONTROLLER_LABEL);
 constexpr const struct device *targets[FORWARD_COUNT] = {
-	DT_FOREACH_PROP_ELEM(CONTROLLER_LABEL, forwards, GET_TARGET_DEVICE)};
+	DT_FOREACH_PROP_ELEM_SEP(CONTROLLER_LABEL, forwards, DEVICE_DT_GET_BY_IDX, (,))};
 
 static void *i2c_emul_forwarding_setup(void)
 {
diff --git a/tests/drivers/i2c/i2c_emul/testcase.yaml b/tests/drivers/i2c/i2c_emul/testcase.yaml
index 3338100ba10..e8f97d1d65a 100644
--- a/tests/drivers/i2c/i2c_emul/testcase.yaml
+++ b/tests/drivers/i2c/i2c_emul/testcase.yaml
@@ -1,5 +1,9 @@
 # Copyright 2024 Google LLC
 # SPDX-License-Identifier: Apache-2.0
+common:
+  tags:
+    - drivers
+    - i2c
 
 tests:
   drivers.i2c.emul.target_pio:
diff --git a/tests/drivers/i2c/i2c_ram/src/test_i2c_ram.c b/tests/drivers/i2c/i2c_ram/src/test_i2c_ram.c
index 8fb39de2517..5d99f9c7af8 100644
--- a/tests/drivers/i2c/i2c_ram/src/test_i2c_ram.c
+++ b/tests/drivers/i2c/i2c_ram/src/test_i2c_ram.c
@@ -35,6 +35,10 @@ uint8_t rx_data[7];
 
 const struct device *i2c_dev = DEVICE_DT_GET(I2C_DEV_NODE);
 
+#ifdef CONFIG_I2C_RTIO
+static void i2c_ram_rtio_before(void);
+#endif
+
 /* Address from datasheet is 0b1010xxxr where x bits are additional
  * memory address bits and r is the r/w i2c bit.
  *
@@ -75,6 +79,10 @@ static void i2c_ram_before(void *f)
 	addr += ARRAY_SIZE(tx_data) - TX_DATA_OFFSET;
 	memset(rx_data, 0, ARRAY_SIZE(rx_data));
 
+#ifdef CONFIG_I2C_RTIO
+	i2c_ram_rtio_before();
+#endif
+
 #ifdef CONFIG_PM_DEVICE_RUNTIME
 	pm_device_runtime_get(i2c_dev);
 #endif
@@ -178,6 +186,26 @@ ZTEST(i2c_ram, test_ram_transfer_cb)
 I2C_IODEV_DEFINE(i2c_iodev, I2C_DEV_NODE, RAM_ADDR);
 RTIO_DEFINE(i2c_rtio, 2, 2);
 
+static void i2c_ram_rtio_before(void)
+{
+	struct rtio_cqe *cqe;
+
+	while ((cqe = rtio_cqe_consume(&i2c_rtio))) {
+		rtio_cqe_release(&i2c_rtio, cqe);
+	}
+}
+
+static void check_completion(struct rtio_cqe *cqe, const char *msg)
+{
+	int32_t result;
+
+	result = cqe->result;
+	rtio_cqe_release(&i2c_rtio, cqe);
+	if (result) {
+		zassert_ok(result, msg);
+	}
+}
+
 ZTEST(i2c_ram, test_ram_rtio)
 {
 	struct rtio_sqe *wr_sqe, *rd_sqe;
@@ -190,8 +218,7 @@ ZTEST(i2c_ram, test_ram_rtio)
 	zassert_ok(rtio_submit(&i2c_rtio, 1), "submit should succeed");
 
 	wr_cqe = rtio_cqe_consume(&i2c_rtio);
-	zassert_ok(wr_cqe->result, "i2c write should succeed");
-	rtio_cqe_release(&i2c_rtio, wr_cqe);
+	check_completion(wr_cqe, "i2c write should succeed");
 
 	/* Write the address and read the data back */
 	msgs[0].len = ARRAY_SIZE(rx_cmd);
@@ -209,16 +236,59 @@ ZTEST(i2c_ram, test_ram_rtio)
 	zassert_ok(rtio_submit(&i2c_rtio, 2), "submit should succeed");
 
 	wr_cqe = rtio_cqe_consume(&i2c_rtio);
+	check_completion(wr_cqe, "i2c write should succeed");
 	rd_cqe = rtio_cqe_consume(&i2c_rtio);
-	zassert_ok(wr_cqe->result, "i2c write should succeed");
-	zassert_ok(rd_cqe->result, "i2c read should succeed");
-	rtio_cqe_release(&i2c_rtio, wr_cqe);
-	rtio_cqe_release(&i2c_rtio, rd_cqe);
+	check_completion(rd_cqe, "i2c read should succeed");
 
 	zassert_equal(memcmp(&tx_data[TX_DATA_OFFSET], &rx_data[0], ARRAY_SIZE(rx_data)), 0,
 		      "Written and Read data should match");
 }
 
+ZTEST(i2c_ram, test_ram_rtio_write_with_transaction)
+{
+	/** Many drivers and API rely on two write OPs in a single transaction
+	 * to write register addr + register data in a single go.
+	 * Hence why is validated in a separate test-case.
+	 */
+	struct rtio_sqe *wraddr_sqe, *wrdata_sqe, *wr_sqe, *rd_sqe;
+	struct rtio_cqe *wr_cqe, *rd_cqe;
+
+	uint8_t reg_data[] = {'h', 'e', 'l', 'l', 'o'};
+
+	TC_PRINT("submitting write from thread %p addr %x\n", k_current_get(), addr);
+	wraddr_sqe = rtio_sqe_acquire(&i2c_rtio);
+	rtio_sqe_prep_write(wraddr_sqe, &i2c_iodev, 0, (uint8_t *)&addr, sizeof(addr), NULL);
+	wraddr_sqe->flags |= RTIO_SQE_TRANSACTION;
+
+	wrdata_sqe = rtio_sqe_acquire(&i2c_rtio);
+	rtio_sqe_prep_write(wrdata_sqe, &i2c_iodev, 0, reg_data, ARRAY_SIZE(reg_data), NULL);
+	wrdata_sqe->iodev_flags |= RTIO_IODEV_I2C_STOP;
+
+	zassert_ok(rtio_submit(&i2c_rtio, 2), "submit should succeed");
+
+	wr_cqe = rtio_cqe_consume(&i2c_rtio);
+	check_completion(wr_cqe, "i2c write should succeed");
+	wr_cqe = rtio_cqe_consume(&i2c_rtio);
+	check_completion(wr_cqe, "i2c write should succeed");
+
+	/** Now read the register address to confirm the write was performed */
+	wr_sqe = rtio_sqe_acquire(&i2c_rtio);
+	rd_sqe = rtio_sqe_acquire(&i2c_rtio);
+	rtio_sqe_prep_write(wr_sqe, &i2c_iodev, 0, (uint8_t *)&addr, sizeof(addr), NULL);
+	rtio_sqe_prep_read(rd_sqe, &i2c_iodev, 0, rx_data, ARRAY_SIZE(reg_data), NULL);
+	wr_sqe->flags |= RTIO_SQE_TRANSACTION;
+	rd_sqe->iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART;
+	zassert_ok(rtio_submit(&i2c_rtio, 2), "submit should succeed");
+
+	wr_cqe = rtio_cqe_consume(&i2c_rtio);
+	check_completion(wr_cqe, "i2c write should succeed");
+	rd_cqe = rtio_cqe_consume(&i2c_rtio);
+	check_completion(rd_cqe, "i2c read should succeed");
+
+	zassert_equal(memcmp(&reg_data[0], &rx_data[0], ARRAY_SIZE(reg_data)), 0,
+		      "Written and Read data should match");
+}
+
 static enum isr_rtio_state {
 	INIT,
 	WRITE_WAIT,
@@ -247,8 +317,7 @@ void ram_rtio_isr(struct k_timer *tid)
 		wr_cqe = rtio_cqe_consume(&i2c_rtio);
 		if (wr_cqe) {
 			TC_PRINT("timer checking write result, submitting read\n");
-			zassert_ok(wr_cqe->result, "i2c write should succeed");
-			rtio_cqe_release(&i2c_rtio, wr_cqe);
+			check_completion(wr_cqe, "i2c write should succeed");
 
 			/* Write the address and read the data back */
 			msgs[0].len = ARRAY_SIZE(rx_cmd);
@@ -273,8 +342,7 @@ void ram_rtio_isr(struct k_timer *tid)
 		wr_cqe = rtio_cqe_consume(&i2c_rtio);
 		if (wr_cqe) {
 			TC_PRINT("read command complete\n");
-			zassert_ok(wr_cqe->result, "i2c read command should succeed");
-			rtio_cqe_release(&i2c_rtio, wr_cqe);
+			check_completion(wr_cqe, "i2c read command should succeed");
 			isr_state += 1;
 		}
 		break;
@@ -282,8 +350,7 @@ void ram_rtio_isr(struct k_timer *tid)
 		rd_cqe = rtio_cqe_consume(&i2c_rtio);
 		if (rd_cqe) {
 			TC_PRINT("read data complete\n");
-			zassert_ok(rd_cqe->result, "i2c read data should succeed");
-			rtio_cqe_release(&i2c_rtio, rd_cqe);
+			check_completion(rd_cqe, "i2c read data should succeed");
 			isr_state += 1;
 			k_sem_give(&ram_rtio_isr_sem);
 			k_timer_stop(tid);
diff --git a/tests/drivers/i2c/i2c_target_api/boards/bl54l15_dvk_nrf54l15_cpuapp.conf b/tests/drivers/i2c/i2c_target_api/boards/bl54l15_dvk_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..16c07c2111f
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/bl54l15_dvk_nrf54l15_cpuapp.conf
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_I2C_NRFX_TWIS_BUF_SIZE=256
diff --git a/tests/drivers/i2c/i2c_target_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/i2c/i2c_target_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..c40169479a8
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * SDA = P1.8 and P1.9
+ * SCL = P1.10 and P1.11
+ */
+
+&pinctrl {
+	i2c21_default: i2c21_default {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 8)>,
+				<NRF_PSEL(TWIS_SCL, 1, 10)>;
+			bias-pull-up;
+		};
+	};
+
+	i2c21_sleep: i2c21_sleep {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 8)>,
+				<NRF_PSEL(TWIS_SCL, 1, 10)>;
+			low-power-enable;
+		};
+	};
+
+	i2c22_default: i2c22_default {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 9)>,
+				<NRF_PSEL(TWIS_SCL, 1, 11)>;
+			bias-pull-up;
+		};
+	};
+
+	i2c22_sleep: i2c22_sleep {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 9)>,
+				<NRF_PSEL(TWIS_SCL, 1, 11)>;
+			low-power-enable;
+		};
+	};
+};
+
+&i2c21 {
+	pinctrl-0 = <&i2c21_default>;
+	pinctrl-1 = <&i2c21_sleep>;
+	pinctrl-names = "default", "sleep";
+	zephyr,concat-buf-size = <256>;
+	status = "okay";
+
+	eeprom1: eeprom@56 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x56>;
+		address-width = <8>;
+		size = <256>;
+	};
+};
+
+&i2c22 {
+	compatible = "nordic,nrf-twis";
+	pinctrl-0 = <&i2c22_default>;
+	pinctrl-1 = <&i2c22_sleep>;
+	pinctrl-names = "default", "sleep";
+	status = "okay";
+
+	eeprom0: eeprom@54 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x54>;
+		address-width = <8>;
+		size = <256>;
+	};
+};
diff --git a/tests/drivers/i2c/i2c_target_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf b/tests/drivers/i2c/i2c_target_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..16c07c2111f
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_I2C_NRFX_TWIS_BUF_SIZE=256
diff --git a/tests/drivers/i2c/i2c_target_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/i2c/i2c_target_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..c40169479a8
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * SDA = P1.8 and P1.9
+ * SCL = P1.10 and P1.11
+ */
+
+&pinctrl {
+	i2c21_default: i2c21_default {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 8)>,
+				<NRF_PSEL(TWIS_SCL, 1, 10)>;
+			bias-pull-up;
+		};
+	};
+
+	i2c21_sleep: i2c21_sleep {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 8)>,
+				<NRF_PSEL(TWIS_SCL, 1, 10)>;
+			low-power-enable;
+		};
+	};
+
+	i2c22_default: i2c22_default {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 9)>,
+				<NRF_PSEL(TWIS_SCL, 1, 11)>;
+			bias-pull-up;
+		};
+	};
+
+	i2c22_sleep: i2c22_sleep {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 9)>,
+				<NRF_PSEL(TWIS_SCL, 1, 11)>;
+			low-power-enable;
+		};
+	};
+};
+
+&i2c21 {
+	pinctrl-0 = <&i2c21_default>;
+	pinctrl-1 = <&i2c21_sleep>;
+	pinctrl-names = "default", "sleep";
+	zephyr,concat-buf-size = <256>;
+	status = "okay";
+
+	eeprom1: eeprom@56 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x56>;
+		address-width = <8>;
+		size = <256>;
+	};
+};
+
+&i2c22 {
+	compatible = "nordic,nrf-twis";
+	pinctrl-0 = <&i2c22_default>;
+	pinctrl-1 = <&i2c22_sleep>;
+	pinctrl-names = "default", "sleep";
+	status = "okay";
+
+	eeprom0: eeprom@54 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x54>;
+		address-width = <8>;
+		size = <256>;
+	};
+};
diff --git a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0.overlay b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0.overlay
index 71a99565aab..fda9cf69c4a 100644
--- a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0.overlay
+++ b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -27,8 +27,8 @@
 };
 
 /* To test this sample, connect
- * LPI2C1 SCL(J2-12, P1_25/FC1_P1)    -->        LPI2C2 SCL(J2-20, P4_1/FC2_P1)
- * LPI2C1 SDA(J2-8, P1_24/FC1_P0)     -->        LPI2C2 SDA(J2-18, P4_0/FC2_P0)
+ * LPI2C1 SCL(J2-12, P0_25/FC1_P1)    -->        LPI2C2 SCL(J2-20, P4_1/FC2_P1)
+ * LPI2C1 SDA(J2-8, P0_24/FC1_P0)     -->        LPI2C2 SDA(J2-18, P4_0/FC2_P0)
  */
 &flexcomm1_lpi2c1 {
 	pinctrl-0 = <&pinmux_flexcomm1_lpi2c>;
diff --git a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0_qspi.overlay b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0_qspi.overlay
index d0dc5661db8..c17df12c200 100644
--- a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0_qspi.overlay
+++ b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxn947_mcxn947_cpu0_qspi.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -27,8 +27,8 @@
 };
 
 /* To test this sample, connect
- * LPI2C1 SCL(J2-12, P1_25/FC1_P1)    -->        LPI2C2 SCL(J2-20, P4_1/FC2_P1)
- * LPI2C1 SDA(J2-8, P1_24/FC1_P0)     -->        LPI2C2 SDA(J2-18, P4_0/FC2_P0)
+ * LPI2C1 SCL(J2-12, P0_25/FC1_P1)    -->        LPI2C2 SCL(J2-20, P4_1/FC2_P1)
+ * LPI2C1 SDA(J2-8, P0_24/FC1_P0)     -->        LPI2C2 SDA(J2-18, P4_0/FC2_P0)
  */
 &flexcomm1_lpi2c1 {
 	pinctrl-0 = <&pinmux_flexcomm1_lpi2c>;
diff --git a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxw71.conf b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxw71.conf
new file mode 100644
index 00000000000..70e009fae68
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxw71.conf
@@ -0,0 +1 @@
+CONFIG_I2C_VIRTUAL=n
diff --git a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxw71.overlay b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxw71.overlay
new file mode 100644
index 00000000000..4c8eba4c34b
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxw71.overlay
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * This is a looback setup for the frdm_mcxw71
+ * To test this sample, connect J2.1 <-> J1.5 and J2.2 <-> J2.9
+ */
+&lpi2c1 {
+	status = "okay";
+	eeprom0: eeprom@54 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x54>;
+		size = <256>;
+	};
+};
+
+&lpi2c0 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_lpi2c0>;
+	pinctrl-names = "default";
+	eeprom1: eeprom@56 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x56>;
+		size = <256>;
+	};
+};
+
+&gpiob {
+	status = "okay";
+};
+
+&gpioa {
+	status = "okay";
+};
diff --git a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxw72_mcxw727c_cpu0.conf b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxw72_mcxw727c_cpu0.conf
new file mode 100644
index 00000000000..70e009fae68
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxw72_mcxw727c_cpu0.conf
@@ -0,0 +1 @@
+CONFIG_I2C_VIRTUAL=n
diff --git a/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxw72_mcxw727c_cpu0.overlay b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxw72_mcxw727c_cpu0.overlay
new file mode 100644
index 00000000000..c4af201718d
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/frdm_mcxw72_mcxw727c_cpu0.overlay
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * This is a loopback setup for the frdm_mcxw72
+ * To test this sample, connect J2.1 <-> J1.5 and J2.2 <-> J2.9
+ */
+&lpi2c1 {
+	status = "okay";
+	eeprom0: eeprom@54 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x54>;
+		size = <256>;
+	};
+};
+
+&lpi2c0 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_lpi2c0>;
+	pinctrl-names = "default";
+	eeprom1: eeprom@56 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x56>;
+		size = <256>;
+	};
+};
+
+&gpiob {
+	status = "okay";
+};
diff --git a/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0.conf b/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0.conf
new file mode 100644
index 00000000000..70e009fae68
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0.conf
@@ -0,0 +1 @@
+CONFIG_I2C_VIRTUAL=n
diff --git a/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..fda9cf69c4a
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+&pinctrl {
+	pinmux_flexcomm1_lpi2c: pinmux_flexcomm1_lpi2c {
+		group0 {
+			pinmux = <FC1_P0_PIO0_24>,
+				<FC1_P1_PIO0_25>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+			bias-pull-up;
+			drive-open-drain;
+		};
+	};
+};
+
+&flexcomm1 {
+	status = "okay";
+};
+
+/* We cannot enable SPI and I2C on the same flexcomm */
+&flexcomm1_lpspi1 {
+	status = "disabled";
+};
+
+/* To test this sample, connect
+ * LPI2C1 SCL(J2-12, P0_25/FC1_P1)    -->        LPI2C2 SCL(J2-20, P4_1/FC2_P1)
+ * LPI2C1 SDA(J2-8, P0_24/FC1_P0)     -->        LPI2C2 SDA(J2-18, P4_0/FC2_P0)
+ */
+&flexcomm1_lpi2c1 {
+	pinctrl-0 = <&pinmux_flexcomm1_lpi2c>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	status = "okay";
+	eeprom0: eeprom@54 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x54>;
+		size = <256>;
+	};
+};
+
+&flexcomm2_lpi2c2 {
+	eeprom1: eeprom@56 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x56>;
+		size = <256>;
+	};
+};
diff --git a/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.conf b/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.conf
new file mode 100644
index 00000000000..70e009fae68
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.conf
@@ -0,0 +1 @@
+CONFIG_I2C_VIRTUAL=n
diff --git a/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay b/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay
new file mode 100644
index 00000000000..c17df12c200
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+&pinctrl {
+	pinmux_flexcomm1_lpi2c: pinmux_flexcomm1_lpi2c {
+		group0 {
+			pinmux = <FC1_P0_PIO0_24>,
+				<FC1_P1_PIO0_25>;
+			slew-rate = "fast";
+			drive-strength = "low";
+			input-enable;
+			bias-pull-up;
+			drive-open-drain;
+		};
+	};
+};
+
+&flexcomm1 {
+	status = "okay";
+};
+
+/* We cannot enable SPI and I2C on the same flexcomm */
+&flexcomm1_lpspi1 {
+	status = "disabled";
+};
+
+/* To test this sample, connect
+ * LPI2C1 SCL(J2-12, P0_25/FC1_P1)    -->        LPI2C2 SCL(J2-20, P4_1/FC2_P1)
+ * LPI2C1 SDA(J2-8, P0_24/FC1_P0)     -->        LPI2C2 SDA(J2-18, P4_0/FC2_P0)
+ */
+&flexcomm1_lpi2c1 {
+	pinctrl-0 = <&pinmux_flexcomm1_lpi2c>;
+	pinctrl-names = "default";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+	status = "okay";
+	eeprom0: eeprom@54 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x54>;
+		size = <1024>;
+	};
+};
+
+&flexcomm2_lpi2c2 {
+	eeprom1: eeprom@56 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x56>;
+		size = <1024>;
+	};
+};
diff --git a/tests/drivers/i2c/i2c_target_api/boards/mcxw72_evk_mcxw727c_cpu0.conf b/tests/drivers/i2c/i2c_target_api/boards/mcxw72_evk_mcxw727c_cpu0.conf
new file mode 100644
index 00000000000..70e009fae68
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/mcxw72_evk_mcxw727c_cpu0.conf
@@ -0,0 +1 @@
+CONFIG_I2C_VIRTUAL=n
diff --git a/tests/drivers/i2c/i2c_target_api/boards/mcxw72_evk_mcxw727c_cpu0.overlay b/tests/drivers/i2c/i2c_target_api/boards/mcxw72_evk_mcxw727c_cpu0.overlay
new file mode 100644
index 00000000000..a1e72084a08
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/mcxw72_evk_mcxw727c_cpu0.overlay
@@ -0,0 +1,33 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * This is a loopback setup for the mcxw72_evk
+ * To test this sample, connect J1.5 <-> J2.1 and J1.7 <-> J2.3
+ */
+&lpi2c1 {
+	status = "okay";
+	eeprom0: eeprom@54 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x54>;
+		size = <256>;
+	};
+};
+
+&lpi2c0 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_lpi2c0>;
+	pinctrl-names = "default";
+	eeprom1: eeprom@56 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x56>;
+		size = <256>;
+	};
+};
+
+&gpiob {
+	status = "okay";
+};
diff --git a/tests/drivers/i2c/i2c_target_api/boards/mimxrt1060_evk_C.conf b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1060_evk_C.conf
new file mode 100644
index 00000000000..70e009fae68
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1060_evk_C.conf
@@ -0,0 +1 @@
+CONFIG_I2C_VIRTUAL=n
diff --git a/tests/drivers/i2c/i2c_target_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
new file mode 100644
index 00000000000..d47c67068ba
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
@@ -0,0 +1,41 @@
+/*
+ * Copyright 2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	pinmux_lpi2c3: pinmux_lpi2c3 {
+		group0 {
+			pinmux = <&iomuxc_gpio_ad_b1_06_lpi2c3_sda>,
+				<&iomuxc_gpio_ad_b1_07_lpi2c3_scl>;
+			drive-strength = "r0-6";
+			drive-open-drain;
+			slew-rate = "slow";
+			nxp,speed = "100-mhz";
+			input-enable;
+		};
+	};
+};
+
+/* To test this sample, connect J22.2 <-> J24.9 and J22.1 <-> J24.10 */
+
+&lpi2c1 {
+	status = "okay";
+	eeprom0: eeprom@54 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x54>;
+		size = <256>;
+	};
+};
+
+&lpi2c3 {
+	status = "okay";
+	pinctrl-0 = <&pinmux_lpi2c3>;
+	pinctrl-names = "default";
+	eeprom1: eeprom@56 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x56>;
+		size = <256>;
+	};
+};
diff --git a/tests/drivers/i2c/i2c_target_api/boards/nucleo_c071rb.conf b/tests/drivers/i2c/i2c_target_api/boards/nucleo_c071rb.conf
new file mode 100644
index 00000000000..34b2571d125
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/nucleo_c071rb.conf
@@ -0,0 +1,2 @@
+CONFIG_I2C_STM32_INTERRUPT=y
+CONFIG_I2C_VIRTUAL=n
diff --git a/tests/drivers/i2c/i2c_target_api/boards/nucleo_c071rb.overlay b/tests/drivers/i2c/i2c_target_api/boards/nucleo_c071rb.overlay
new file mode 100644
index 00000000000..db98b3c0346
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/nucleo_c071rb.overlay
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* I2C bus pins are exposed on the ST morpho header.
+ *
+ *  Bus        SDA               SCL
+ *          Pin   Hdr         Pin   Hdr
+ *  i2c1    PB9   CN5:9      PB8   CN5:10
+ *  i2c2    PA6   CN5:5      PA7   CN5:4
+ *
+ * Short Pin PB9 to PA6, and PB8 to PA7, for the test to pass.
+ */
+
+&i2c1 {
+	eeprom0: eeprom@54 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x54>;
+		size = <256>;
+	};
+};
+
+&i2c2 {
+	eeprom1: eeprom@56 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x56>;
+		size = <256>;
+	};
+};
diff --git a/tests/drivers/i2c/i2c_target_api/boards/nucleo_n657x0_q_stm32n657xx_sb.conf b/tests/drivers/i2c/i2c_target_api/boards/nucleo_n657x0_q_stm32n657xx_sb.conf
new file mode 100644
index 00000000000..34b2571d125
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/nucleo_n657x0_q_stm32n657xx_sb.conf
@@ -0,0 +1,2 @@
+CONFIG_I2C_STM32_INTERRUPT=y
+CONFIG_I2C_VIRTUAL=n
diff --git a/tests/drivers/i2c/i2c_target_api/boards/nucleo_n657x0_q_stm32n657xx_sb.overlay b/tests/drivers/i2c/i2c_target_api/boards/nucleo_n657x0_q_stm32n657xx_sb.overlay
new file mode 100644
index 00000000000..cbf9f516799
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/nucleo_n657x0_q_stm32n657xx_sb.overlay
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* I2C bus pins are exposed on the ST Arduino header.
+ *
+ *  Bus        SDA                    SCL
+ *          Pin   Hdr              Pin   Hdr
+ *  i2c1    PC1   CN15:5           PH9   CN15:3
+ *  i2c4    PE14  CN15:26          PE13  CN15:28
+ *
+ * Short Pin PC1 to PE14, and PH9 to PE13, for the test to pass.
+ */
+
+&i2c1 {
+	eeprom0: eeprom@54 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x54>;
+		size = <256>;
+	};
+};
+
+&i2c4 {
+	eeprom1: eeprom@56 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x56>;
+		size = <256>;
+	};
+};
diff --git a/tests/drivers/i2c/i2c_target_api/boards/ophelia4ev_nrf54l15_cpuapp.conf b/tests/drivers/i2c/i2c_target_api/boards/ophelia4ev_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..c8ffd42673e
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/ophelia4ev_nrf54l15_cpuapp.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_I2C_NRFX_TWIS_BUF_SIZE=256
diff --git a/tests/drivers/i2c/i2c_target_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/i2c/i2c_target_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..8e70cb694e4
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * SDA = P1.8 and P1.9
+ * SCL = P1.10 and P1.11
+ */
+
+&pinctrl {
+	i2c21_default: i2c21_default {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 8)>,
+				<NRF_PSEL(TWIS_SCL, 1, 10)>;
+			bias-pull-up;
+		};
+	};
+
+	i2c21_sleep: i2c21_sleep {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 8)>,
+				<NRF_PSEL(TWIS_SCL, 1, 10)>;
+			low-power-enable;
+		};
+	};
+
+	i2c22_default: i2c22_default {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 9)>,
+				<NRF_PSEL(TWIS_SCL, 1, 11)>;
+			bias-pull-up;
+		};
+	};
+
+	i2c22_sleep: i2c22_sleep {
+		group1 {
+			psels = <NRF_PSEL(TWIS_SDA, 1, 9)>,
+				<NRF_PSEL(TWIS_SCL, 1, 11)>;
+			low-power-enable;
+		};
+	};
+};
+
+&i2c21 {
+	pinctrl-0 = <&i2c21_default>;
+	pinctrl-1 = <&i2c21_sleep>;
+	pinctrl-names = "default", "sleep";
+	zephyr,concat-buf-size = <256>;
+	status = "okay";
+
+	eeprom1: eeprom@56 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x56>;
+		address-width = <8>;
+		size = <256>;
+	};
+};
+
+&i2c22 {
+	compatible = "nordic,nrf-twis";
+	pinctrl-0 = <&i2c22_default>;
+	pinctrl-1 = <&i2c22_sleep>;
+	pinctrl-names = "default", "sleep";
+	status = "okay";
+
+	eeprom0: eeprom@54 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x54>;
+		address-width = <8>;
+		size = <256>;
+	};
+};
diff --git a/tests/drivers/i2c/i2c_target_api/boards/stm32n6570_dk_stm32n657xx_sb.conf b/tests/drivers/i2c/i2c_target_api/boards/stm32n6570_dk_stm32n657xx_sb.conf
new file mode 100644
index 00000000000..34b2571d125
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/stm32n6570_dk_stm32n657xx_sb.conf
@@ -0,0 +1,2 @@
+CONFIG_I2C_STM32_INTERRUPT=y
+CONFIG_I2C_VIRTUAL=n
diff --git a/tests/drivers/i2c/i2c_target_api/boards/stm32n6570_dk_stm32n657xx_sb.overlay b/tests/drivers/i2c/i2c_target_api/boards/stm32n6570_dk_stm32n657xx_sb.overlay
new file mode 100644
index 00000000000..8c0215c406b
--- /dev/null
+++ b/tests/drivers/i2c/i2c_target_api/boards/stm32n6570_dk_stm32n657xx_sb.overlay
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* I2C bus pins are exposed on the ST Arduino header.
+ *
+ *  Bus        SDA                    SCL
+ *          Pin   Hdr              Pin   Hdr
+ *  i2c1    PC1   CN12:10 (D15)    PH9   CN12:9 (D14)
+ *  i2c4    PE14  CN12:2  (D9)     PE13  CN11:7 (D6)
+ *
+ * Short Pin PC1 to PE14, and PH9 to PE13, for the test to pass.
+ */
+
+&i2c1 {
+	eeprom0: eeprom@54 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x54>;
+		size = <256>;
+	};
+};
+
+&i2c4 {
+	eeprom1: eeprom@56 {
+		compatible = "zephyr,i2c-target-eeprom";
+		reg = <0x56>;
+		size = <256>;
+	};
+};
diff --git a/tests/drivers/i2c/i2c_target_api/testcase.yaml b/tests/drivers/i2c/i2c_target_api/testcase.yaml
index 4237b60b2dc..4ffbedef252 100644
--- a/tests/drivers/i2c/i2c_target_api/testcase.yaml
+++ b/tests/drivers/i2c/i2c_target_api/testcase.yaml
@@ -18,6 +18,7 @@ tests:
       - stm32f3_disco
       - stm32h573i_dk
       - stm32u083c_dk
+      - nucleo_c071rb
       - nucleo_g071rb
       - nucleo_f207zg
       - nucleo_f401re
@@ -37,6 +38,8 @@ tests:
   drivers.i2c.target_api.single_role:
     platform_allow:
       - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
+      - mcxw72_evk/mcxw727c/cpu0
       - mimxrt1170_evk@B/mimxrt1176/cm7
       - mimxrt1170_evk/mimxrt1176/cm7
       - mimxrt1180_evk/mimxrt1189/cm33
@@ -58,5 +61,6 @@ tests:
       - nrf54h20dk/nrf54h20/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - max32690evkit/max32690/m4
diff --git a/tests/drivers/i2c/i2c_tca954x/testcase.yaml b/tests/drivers/i2c/i2c_tca954x/testcase.yaml
index 2304bc62c56..cb89010fae2 100644
--- a/tests/drivers/i2c/i2c_tca954x/testcase.yaml
+++ b/tests/drivers/i2c/i2c_tca954x/testcase.yaml
@@ -4,6 +4,7 @@ tests:
     tags:
       - testing
       - drivers
+      - i2c
     depends_on: i2c
     filter: dt_compat_enabled("ti,tca9546a")
     platform_allow: nrf52840dk/nrf52840
diff --git a/tests/drivers/i2s/i2s_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay b/tests/drivers/i2s/i2s_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay
new file mode 100644
index 00000000000..2170eac1179
--- /dev/null
+++ b/tests/drivers/i2s/i2s_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15_dvk_nrf54l15_cpuapp.overlay"
diff --git a/tests/drivers/i2s/i2s_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/i2s/i2s_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..7c8b7868b3c
--- /dev/null
+++ b/tests/drivers/i2s/i2s_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* i2s-node0 is the transmitter/receiver */
+
+/ {
+	aliases {
+		i2s-node0 = &i2s20;
+	};
+};
+
+&pinctrl {
+	i2s20_default_alt: i2s20_default_alt {
+		group1 {
+			psels = <NRF_PSEL(I2S_SCK_M, 1, 11)>,
+				<NRF_PSEL(I2S_LRCK_M, 1, 12)>,
+				<NRF_PSEL(I2S_SDOUT, 1, 8)>,
+				<NRF_PSEL(I2S_SDIN, 1, 9)>;
+		};
+	};
+};
+
+&i2s20 {
+	status = "okay";
+	pinctrl-0 = <&i2s20_default_alt>;
+	pinctrl-names = "default";
+};
diff --git a/tests/drivers/i2s/i2s_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/i2s/i2s_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..7c8b7868b3c
--- /dev/null
+++ b/tests/drivers/i2s/i2s_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* i2s-node0 is the transmitter/receiver */
+
+/ {
+	aliases {
+		i2s-node0 = &i2s20;
+	};
+};
+
+&pinctrl {
+	i2s20_default_alt: i2s20_default_alt {
+		group1 {
+			psels = <NRF_PSEL(I2S_SCK_M, 1, 11)>,
+				<NRF_PSEL(I2S_LRCK_M, 1, 12)>,
+				<NRF_PSEL(I2S_SDOUT, 1, 8)>,
+				<NRF_PSEL(I2S_SDIN, 1, 9)>;
+		};
+	};
+};
+
+&i2s20 {
+	status = "okay";
+	pinctrl-0 = <&i2s20_default_alt>;
+	pinctrl-names = "default";
+};
diff --git a/tests/drivers/i2s/i2s_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/i2s/i2s_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..5637a121224
--- /dev/null
+++ b/tests/drivers/i2s/i2s_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* i2s-node0 is the transmitter/receiver */
+
+/ {
+	aliases {
+		i2s-node0 = &i2s20;
+	};
+};
+
+&pinctrl {
+	i2s20_default_alt: i2s20_default_alt {
+		group1 {
+			psels = <NRF_PSEL(I2S_SCK_M, 1, 11)>,
+				<NRF_PSEL(I2S_LRCK_M, 1, 12)>,
+				<NRF_PSEL(I2S_SDOUT, 1, 8)>,
+				<NRF_PSEL(I2S_SDIN, 1, 9)>;
+		};
+	};
+};
+
+&i2s20 {
+	status = "okay";
+	pinctrl-0 = <&i2s20_default_alt>;
+	pinctrl-names = "default";
+};
diff --git a/tests/drivers/i2s/i2s_api/testcase.yaml b/tests/drivers/i2s/i2s_api/testcase.yaml
index b039b413585..1932607d655 100644
--- a/tests/drivers/i2s/i2s_api/testcase.yaml
+++ b/tests/drivers/i2s/i2s_api/testcase.yaml
@@ -6,6 +6,8 @@ tests:
       - userspace
     filter: not CONFIG_I2S_TEST_USE_GPIO_LOOPBACK
     platform_exclude:
+      - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
       - mimxrt595_evk/mimxrt595s/cm33
       - mimxrt685_evk/mimxrt685s/cm33
   drivers.i2s.gpio_loopback:
@@ -18,6 +20,8 @@ tests:
     filter: CONFIG_I2S_TEST_USE_GPIO_LOOPBACK
     harness: ztest
     platform_exclude:
+      - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
       - mimxrt595_evk/mimxrt595s/cm33
       - mimxrt685_evk/mimxrt685s/cm33
     harness_config:
diff --git a/tests/drivers/i2s/i2s_speed/Readme.txt b/tests/drivers/i2s/i2s_speed/Readme.txt
index 4d5816996c5..044ab060400 100644
--- a/tests/drivers/i2s/i2s_speed/Readme.txt
+++ b/tests/drivers/i2s/i2s_speed/Readme.txt
@@ -4,9 +4,44 @@ i2s_speed Test
 Board-specific details:
 
 MIMXRT1170_EVK:
+This board uses CONFIG_I2S_TEST_SEPARATE_DEVICES=n and connects TX and RX blocks in one
+SAI peripheral by shorting signals externally on the EVK.
+These are the HW changes required to run this test:
+	- Short BCLK J9-pin1  (SAI1_RX_BCLK)  to J9-pin11  (SAI1_TX_BCLK)
+	- Short SYNC J9-pin5  (SAI1_RX_SYNC)  to J9-pin13  (SAI1_TX_SYNC)
+	- Short Data J9-pin7  (SAI1_RX_DATA)  to J9-pin9   (SAI1_TX_DATA)
+
+MIMXRT1170_EVKB (SCH-55139 Rev C/C1/C2):
+This board uses CONFIG_I2S_TEST_SEPARATE_DEVICES=n and connects TX and RX blocks in one
+SAI peripheral by shorting signals externally on the EVK.
+These are the HW changes required to run this test:
+	- Populate R2124, R2125
+	- Remove J99, J100
+	- Short Data J99-pin1 (SAI1_RX_DATA0) to J100-pin1 (SAI1_TX_DATA0)
+
+FRDM-MCXN947:
 This board uses CONFIG_I2S_TEST_SEPARATE_DEVICES=y and connects two SAI peripherals by shorting
 signals externally on the EVK.  These are the HW changes required to run this test:
-	- Remove jumper J8 and resistor R78
-	- Short BCLK J9-pin1  (SAI1_RX_BCLK)  to J66-pin1  (SAI4_TX_BCLK)
-	- Short SYNC J9-pin5  (SAI1_RX_SYNC)  to J64-pin1  (SAI4_TX_SYNC)
-	- Short Data J61-pin1 (SAI1_RX_DATA)  to J63-pin1  (SAI4_TX_DATA)
+        - Short BCLK J1-pin9  (SAI1_RX_BCLK/P3_18) to J3-pin15 (SAI0_TX_BCLK/P2_6)
+        - Short SYNC J1-pin13 (SAI1_RX_FS/P3_19)   to J3-pin13 (SAI0_TX_FS/P2_7)
+        - Short Data J1-pin15 (SAI1_RXD0/P3_21)    to J3-pin7  (SAI0_TXD0/P2_2)
+
+MCX-N9XX-EVK:
+This board uses CONFIG_I2S_TEST_SEPARATE_DEVICES=n and connects TX and RX blocks in one
+SAI peripheral by shorting signals externally on the EVK.  These are the HW changes
+required to run this test:
+	- Populate JP16 and JP20
+	- Short BCLK JP20-pin3 (SAI1_RX_BCLK/P3_18) to JP20-pin1  (SAI1_TX_BCLK/P3_16)
+	- SHort SYNC JP16-pin3 (SAI1_RX_FS  /P3_19) to JP16-pin1  (SAI1_TX_FS  /P3_17)
+        - Short Data J20-pin14 (SAI1_RXD0   /P2_9)  to JP20-pin13 (SAI1_TXD0   /P2_8)
+
+MIMXRT1060-EVK[B/C]:
+This board uses a single SAI and connects the TX and RX signals by shorting externally on the EVK.
+These are the HW changes required to run this test on MIMXRT1060-EVK[B/C]:
+- Remove jumper J99
+- Short BCLK J23-pin5  (SAI1_RX_BCLK  / GPIO_AD_B1_11) to J23-pin23 (SAI1_TX_BCLK  / GPIO_AD_B1_14)
+- Short SYNC J23-pin9  (SAI1_RX_SYNC  / GPIO_AD_B1_10) to J23-pin16 (SAI1_TX_SYNC  / GPIO_AD_B1_15)
+- Short Data J23-pin11 (SAI1_RX_DATA0 / GPIO_AD_B1_12) to J23-pin17 (SAI1_TX_DATA0 / GPIO_AD_B1_13)
+
+- NOTE: these connections cause contention with the following signals/features:
+	- camera CSI_D[2-7]
diff --git a/tests/drivers/i2s/i2s_speed/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay b/tests/drivers/i2s/i2s_speed/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay
new file mode 100644
index 00000000000..2170eac1179
--- /dev/null
+++ b/tests/drivers/i2s/i2s_speed/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15_dvk_nrf54l15_cpuapp.overlay"
diff --git a/tests/drivers/i2s/i2s_speed/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/i2s/i2s_speed/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..7c8b7868b3c
--- /dev/null
+++ b/tests/drivers/i2s/i2s_speed/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* i2s-node0 is the transmitter/receiver */
+
+/ {
+	aliases {
+		i2s-node0 = &i2s20;
+	};
+};
+
+&pinctrl {
+	i2s20_default_alt: i2s20_default_alt {
+		group1 {
+			psels = <NRF_PSEL(I2S_SCK_M, 1, 11)>,
+				<NRF_PSEL(I2S_LRCK_M, 1, 12)>,
+				<NRF_PSEL(I2S_SDOUT, 1, 8)>,
+				<NRF_PSEL(I2S_SDIN, 1, 9)>;
+		};
+	};
+};
+
+&i2s20 {
+	status = "okay";
+	pinctrl-0 = <&i2s20_default_alt>;
+	pinctrl-names = "default";
+};
diff --git a/tests/drivers/i2s/i2s_speed/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/i2s/i2s_speed/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..7c8b7868b3c
--- /dev/null
+++ b/tests/drivers/i2s/i2s_speed/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* i2s-node0 is the transmitter/receiver */
+
+/ {
+	aliases {
+		i2s-node0 = &i2s20;
+	};
+};
+
+&pinctrl {
+	i2s20_default_alt: i2s20_default_alt {
+		group1 {
+			psels = <NRF_PSEL(I2S_SCK_M, 1, 11)>,
+				<NRF_PSEL(I2S_LRCK_M, 1, 12)>,
+				<NRF_PSEL(I2S_SDOUT, 1, 8)>,
+				<NRF_PSEL(I2S_SDIN, 1, 9)>;
+		};
+	};
+};
+
+&i2s20 {
+	status = "okay";
+	pinctrl-0 = <&i2s20_default_alt>;
+	pinctrl-names = "default";
+};
diff --git a/tests/drivers/i2s/i2s_speed/boards/frdm_mcxn947_mcxn947_cpu0.conf b/tests/drivers/i2s/i2s_speed/boards/frdm_mcxn947_mcxn947_cpu0.conf
new file mode 100644
index 00000000000..b44f2e381fc
--- /dev/null
+++ b/tests/drivers/i2s/i2s_speed/boards/frdm_mcxn947_mcxn947_cpu0.conf
@@ -0,0 +1,25 @@
+#
+# Copyright (c) 2024, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+# SAI peripheral does not have loopback mode.  Use 2 SAI peripherals connected
+# together externally.
+CONFIG_I2S_TEST_SEPARATE_DEVICES=y
+
+# CONFIG_DMA_TCD_QUEUE_SIZE sets size of queue used to chain DMA blocks (TCDs)
+# together, and should be sized as needed by the application.  If not large
+# enough, the DMA may starve.  Symptoms of this issue include transmit blocks
+# repeated, or RX blocks skipped. For I2S driver, queue size must be at least 3.
+CONFIG_DMA_TCD_QUEUE_SIZE=4
+
+# Repeat test continually to help find intermittent issues
+CONFIG_ZTEST_RETEST_IF_PASSED=y
+
+# I2S and DMA logging can occur in interrupt context, and interfere with I2S
+# stream timing.  If using either logging, set logging to deferred
+# CONFIG_LOG_MODE_DEFERRED=y
+
+CONFIG_DMA_LOG_LEVEL_OFF=y
+CONFIG_I2S_LOG_LEVEL_OFF=y
diff --git a/tests/drivers/i2s/i2s_speed/boards/frdm_mcxn947_mcxn947_cpu0.overlay b/tests/drivers/i2s/i2s_speed/boards/frdm_mcxn947_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..3dad7edb263
--- /dev/null
+++ b/tests/drivers/i2s/i2s_speed/boards/frdm_mcxn947_mcxn947_cpu0.overlay
@@ -0,0 +1,15 @@
+/* i2s_speed with CONFIG_I2S_TEST_SEPARATE_DEVICES=y uses two I2S peripherals:
+ * i2s-node0 is the receiver
+ * i2s-node1 is the transmitter
+ */
+
+/ {
+	aliases {
+		i2s-node0 = &sai1;
+		i2s-node1 = &sai0;
+	};
+};
+
+&sai0 {
+	mclk-output;
+};
diff --git a/tests/drivers/i2s/i2s_speed/boards/frdm_rw612.conf b/tests/drivers/i2s/i2s_speed/boards/frdm_rw612.conf
new file mode 100644
index 00000000000..4a0c379e26a
--- /dev/null
+++ b/tests/drivers/i2s/i2s_speed/boards/frdm_rw612.conf
@@ -0,0 +1 @@
+CONFIG_I2S_TEST_SEPARATE_DEVICES=y
diff --git a/tests/drivers/i2s/i2s_speed/boards/frdm_rw612.overlay b/tests/drivers/i2s/i2s_speed/boards/frdm_rw612.overlay
new file mode 100644
index 00000000000..7cf5ffa4b5f
--- /dev/null
+++ b/tests/drivers/i2s/i2s_speed/boards/frdm_rw612.overlay
@@ -0,0 +1,39 @@
+/* Overlay for RDRW61X I2S tests */
+
+/ {
+	aliases {
+		i2s-node0 = &flexcomm0;
+		i2s-node1 = &flexcomm1;
+	};
+};
+
+/* Redefine as i2s node */
+&flexcomm0 {
+	compatible = "nxp,lpc-i2s";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-0 = <&pinmux_flexcomm0_i2s>;
+	pinctrl-names = "default";
+	dma-names = "rx", "tx";
+	/delete-property/ current-speed;
+	status = "okay";
+};
+
+&flexcomm1 {
+	compatible = "nxp,lpc-i2s";
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-0 = <&pinmux_flexcomm1_i2s>;
+	pinctrl-names = "default";
+};
+
+/* Redefine pinctrl for flexcomm0 */
+&pinctrl {
+	pinmux_flexcomm0_i2s: pinmux_flexcomm0_i2s {
+		group0 {
+			pinmux = <IO_MUX_FC0_I2S>;
+			slew-rate = "normal";
+		};
+	};
+};
diff --git a/tests/drivers/i2s/i2s_speed/boards/mcx_n9xx_evk_mcxn947_cpu0.conf b/tests/drivers/i2s/i2s_speed/boards/mcx_n9xx_evk_mcxn947_cpu0.conf
new file mode 100644
index 00000000000..f5ba185f17f
--- /dev/null
+++ b/tests/drivers/i2s/i2s_speed/boards/mcx_n9xx_evk_mcxn947_cpu0.conf
@@ -0,0 +1,25 @@
+#
+# Copyright (c) 2025, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+# SAI peripheral does not have loopback mode but we can connect CLK, SYNC,
+# RXD and TXD of one SAI for test purpose.
+CONFIG_I2S_TEST_SEPARATE_DEVICES=n
+
+# CONFIG_DMA_TCD_QUEUE_SIZE sets size of queue used to chain DMA blocks (TCDs)
+# together, and should be sized as needed by the application.  If not large
+# enough, the DMA may starve.  Symptoms of this issue include transmit blocks
+# repeated, or RX blocks skipped. For I2S driver, queue size must be at least 3.
+CONFIG_DMA_TCD_QUEUE_SIZE=4
+
+# Repeat test continually to help find intermittent issues
+CONFIG_ZTEST_RETEST_IF_PASSED=y
+
+# I2S and DMA logging can occur in interrupt context, and interfere with I2S
+# stream timing.  If using either logging, set logging to deferred
+# CONFIG_LOG_MODE_DEFERRED=y
+
+CONFIG_DMA_LOG_LEVEL_OFF=y
+CONFIG_I2S_LOG_LEVEL_OFF=y
diff --git a/tests/drivers/i2s/i2s_speed/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/tests/drivers/i2s/i2s_speed/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..6d89796095a
--- /dev/null
+++ b/tests/drivers/i2s/i2s_speed/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
@@ -0,0 +1,23 @@
+/ {
+	aliases {
+		i2s-node0 = &sai1;
+	};
+};
+
+&sai1 {
+	mclk-output;
+};
+
+&pinmux_sai1 {
+	group0 {
+		pinmux = <SAI1_TX_BCLK_PIO3_16>,
+			<SAI1_TX_FS_PIO3_17>,
+			<SAI1_TXD0_PIO2_8>,
+			<SAI1_RX_FS_PIO3_19>,
+			<SAI1_RX_BCLK_PIO3_18>,
+			<SAI1_RXD0_PIO2_9>;
+		drive-strength = "high";
+		slew-rate = "fast";
+		input-enable;
+	};
+};
diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt1060_evk_mimxrt1062_qspi_B.conf b/tests/drivers/i2s/i2s_speed/boards/mimxrt1060_evk_mimxrt1062_qspi_B.conf
new file mode 100644
index 00000000000..afe9c840db0
--- /dev/null
+++ b/tests/drivers/i2s/i2s_speed/boards/mimxrt1060_evk_mimxrt1062_qspi_B.conf
@@ -0,0 +1,21 @@
+#
+# Copyright (c) 2024, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+# CONFIG_DMA_TCD_QUEUE_SIZE sets size of queue used to chain DMA blocks (TCDs)
+# together, and should be sized as needed by the application.  If not large
+# enough, the DMA may starve.  Symptoms of this issue include transmit blocks
+# repeated, or RX blocks skipped. For I2S driver, queue size must be at least 3.
+CONFIG_DMA_TCD_QUEUE_SIZE=4
+
+# Repeat test continually to help find intermittent issues
+CONFIG_ZTEST_RETEST_IF_PASSED=y
+
+# I2S and DMA logging can occur in interrupt context, and interfere with I2S
+# stream timing.  If using either logging, set logging to deferred
+# CONFIG_LOG_MODE_DEFERRED=y
+
+CONFIG_DMA_LOG_LEVEL_OFF=y
+CONFIG_I2S_LOG_LEVEL_OFF=y
diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay b/tests/drivers/i2s/i2s_speed/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay
new file mode 100644
index 00000000000..fe402d391f8
--- /dev/null
+++ b/tests/drivers/i2s/i2s_speed/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay
@@ -0,0 +1,21 @@
+/ {
+	aliases {
+		i2s-node0 = &sai1;
+	};
+};
+
+&pinctrl {
+	pinmux_sai1: pinmux_sai1 {
+		group0 {
+			pinmux = <&iomuxc_gpio_ad_b1_12_sai1_rx_data0>,
+				<&iomuxc_gpio_ad_b1_11_sai1_rx_bclk>,
+				<&iomuxc_gpio_ad_b1_10_sai1_rx_sync>,
+				<&iomuxc_gpio_ad_b1_15_sai1_tx_sync>,
+				<&iomuxc_gpio_ad_b1_14_sai1_tx_bclk>,
+				<&iomuxc_gpio_ad_b1_13_sai1_tx_data0>;
+			drive-strength = "r0-6";
+			slew-rate = "slow";
+			nxp,speed = "100-mhz";
+		};
+	};
+};
diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_mimxrt1176_cm7.conf b/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_mimxrt1176_cm7.conf
index 1f5ccfe104d..8a1e1c2c47a 100644
--- a/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_mimxrt1176_cm7.conf
+++ b/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_mimxrt1176_cm7.conf
@@ -4,9 +4,9 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-# SAI peripheral does not have loopback mode.  Use 2 SAI peripherals connected
-# together externally.
-CONFIG_I2S_TEST_SEPARATE_DEVICES=y
+# SAI peripheral does not have loopback mode but we can connect CLK, SYNC,
+# RXD and TXD of one SAI for test purpose.
+CONFIG_I2S_TEST_SEPARATE_DEVICES=n
 
 # CONFIG_DMA_TCD_QUEUE_SIZE sets size of queue used to chain DMA blocks (TCDs)
 # together, and should be sized as needed by the application.  If not large
@@ -18,7 +18,7 @@ CONFIG_DMA_TCD_QUEUE_SIZE=4
 CONFIG_ZTEST_RETEST_IF_PASSED=y
 
 # I2S and DMA logging can occur in interrupt context, and interfere with I2S
-# stream timing.  If using either logging, set logging to deffered
+# stream timing.  If using either logging, set logging to deferred
 # CONFIG_LOG_MODE_DEFERRED=y
 
 CONFIG_DMA_LOG_LEVEL_OFF=y
diff --git a/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay b/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
index 24a1defbb3a..59583a680ce 100644
--- a/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
+++ b/tests/drivers/i2s/i2s_speed/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
@@ -1,26 +1,15 @@
-/* i2s_speed with CONFIG_I2S_TEST_SEPARATE_DEVICES=y uses two I2S peripherals:
- *	i2s-node0 is the receiver    - uses SAI1 peripheral on RT1170
- *	i2s-node1 is the transmitter - uses SAI4 peripheral
+/* i2s_speed with CONFIG_I2S_TEST_SEPARATE_DEVICES=n uses only one I2S peripheral:
+ * i2s-node0 is both the transitter and receiver.
+ * uses SAI1 peripheral on RT1170
  */
-
 / {
 	aliases {
 		i2s-node0 = &sai1;
-		i2s-node1 = &sai4;
 	};
 };
 
-/* Enable SAI4, and set clocks to match SAI1 */
-&sai4 {
-	status = "okay";
-	podf = < 0x4 >;
-	pinctrl-0 = <&pinmux_sai4>;
-	pinctrl-names = "default";
-};
-
-/* On MIMXRT1170-EVK, there is a conflict with signal SAI4_TX_BCLK shared with
- * ENET_RST.  For i2s_speed test, disable ENET peripheral.
- */
-&enet {
-	status = "disabled";
+/* Default DMA channel 0 and 1 maybe used by other peripherals like UART. */
+&sai1 {
+	nxp,tx-dma-channel = <8>;
+	nxp,rx-dma-channel = <9>;
 };
diff --git a/tests/drivers/i2s/i2s_speed/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/i2s/i2s_speed/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..5637a121224
--- /dev/null
+++ b/tests/drivers/i2s/i2s_speed/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* i2s-node0 is the transmitter/receiver */
+
+/ {
+	aliases {
+		i2s-node0 = &i2s20;
+	};
+};
+
+&pinctrl {
+	i2s20_default_alt: i2s20_default_alt {
+		group1 {
+			psels = <NRF_PSEL(I2S_SCK_M, 1, 11)>,
+				<NRF_PSEL(I2S_LRCK_M, 1, 12)>,
+				<NRF_PSEL(I2S_SDOUT, 1, 8)>,
+				<NRF_PSEL(I2S_SDIN, 1, 9)>;
+		};
+	};
+};
+
+&i2s20 {
+	status = "okay";
+	pinctrl-0 = <&i2s20_default_alt>;
+	pinctrl-names = "default";
+};
diff --git a/tests/drivers/i2s/i2s_speed/boards/rd_rw612_bga.conf b/tests/drivers/i2s/i2s_speed/boards/rd_rw612_bga.conf
new file mode 100644
index 00000000000..4a0c379e26a
--- /dev/null
+++ b/tests/drivers/i2s/i2s_speed/boards/rd_rw612_bga.conf
@@ -0,0 +1 @@
+CONFIG_I2S_TEST_SEPARATE_DEVICES=y
diff --git a/tests/drivers/i2s/i2s_speed/boards/rd_rw612_bga.overlay b/tests/drivers/i2s/i2s_speed/boards/rd_rw612_bga.overlay
new file mode 100644
index 00000000000..7cf5ffa4b5f
--- /dev/null
+++ b/tests/drivers/i2s/i2s_speed/boards/rd_rw612_bga.overlay
@@ -0,0 +1,39 @@
+/* Overlay for RDRW61X I2S tests */
+
+/ {
+	aliases {
+		i2s-node0 = &flexcomm0;
+		i2s-node1 = &flexcomm1;
+	};
+};
+
+/* Redefine as i2s node */
+&flexcomm0 {
+	compatible = "nxp,lpc-i2s";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-0 = <&pinmux_flexcomm0_i2s>;
+	pinctrl-names = "default";
+	dma-names = "rx", "tx";
+	/delete-property/ current-speed;
+	status = "okay";
+};
+
+&flexcomm1 {
+	compatible = "nxp,lpc-i2s";
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-0 = <&pinmux_flexcomm1_i2s>;
+	pinctrl-names = "default";
+};
+
+/* Redefine pinctrl for flexcomm0 */
+&pinctrl {
+	pinmux_flexcomm0_i2s: pinmux_flexcomm0_i2s {
+		group0 {
+			pinmux = <IO_MUX_FC0_I2S>;
+			slew-rate = "normal";
+		};
+	};
+};
diff --git a/tests/drivers/input/tsc_keys/CMakeLists.txt b/tests/drivers/input/tsc_keys/CMakeLists.txt
new file mode 100644
index 00000000000..5746edeb2e0
--- /dev/null
+++ b/tests/drivers/input/tsc_keys/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright (c) 2024 Arif Balik <arifbalik@outlook.com>
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(stm32_tsc)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/drivers/input/tsc_keys/boards/stm32u083c_dk.overlay b/tests/drivers/input/tsc_keys/boards/stm32u083c_dk.overlay
new file mode 100644
index 00000000000..1ef9dc05341
--- /dev/null
+++ b/tests/drivers/input/tsc_keys/boards/stm32u083c_dk.overlay
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2024 Arif Balik <arifbalik@outlook.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	zephyr,user {
+		/* This will be used to trigger the SYNC pin high and low programmatically.
+		 * They have to be connected.
+		 */
+		signal-gpios = <&gpioa 10 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&tsc {
+	status = "okay";
+
+	pinctrl-0 = <&tsc_g1_io1_pb12 &tsc_g1_io2_pb13 &tsc_g6_io1_pd10
+					&tsc_g6_io2_pd11 &tsc_sync_pd2>;
+	pinctrl-names = "default";
+
+	st,pulse-generator-prescaler = <128>;
+
+	st,spread-spectrum;
+	st,spread-spectrum-prescaler = <2>;
+	st,spread-spectrum-deviation = <10>;
+
+	st,max-count-value = <16383>;
+
+	st,synced-acquisition;
+	st,syncpol-rising;
+};
diff --git a/tests/drivers/input/tsc_keys/prj.conf b/tests/drivers/input/tsc_keys/prj.conf
new file mode 100644
index 00000000000..5b12463c960
--- /dev/null
+++ b/tests/drivers/input/tsc_keys/prj.conf
@@ -0,0 +1,2 @@
+CONFIG_ZTEST=y
+CONFIG_INPUT=y
diff --git a/tests/drivers/input/tsc_keys/src/main.c b/tests/drivers/input/tsc_keys/src/main.c
new file mode 100644
index 00000000000..e70bb05025f
--- /dev/null
+++ b/tests/drivers/input/tsc_keys/src/main.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2024 Arif Balik <arifbalik@outlook.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+extern const struct gpio_dt_spec signal_mock;
+
+static void *stm32_tsc_setup(void)
+{
+	zexpect_ok(gpio_pin_configure_dt(&signal_mock, GPIO_OUTPUT_INACTIVE),
+		   "Failed to configure signal_mock pin");
+
+	return NULL;
+}
+
+ZTEST_SUITE(stm32_tsc, NULL, stm32_tsc_setup, NULL, NULL, NULL);
diff --git a/tests/drivers/input/tsc_keys/src/test_stm32_tsc.c b/tests/drivers/input/tsc_keys/src/test_stm32_tsc.c
new file mode 100644
index 00000000000..3ca3d2c462c
--- /dev/null
+++ b/tests/drivers/input/tsc_keys/src/test_stm32_tsc.c
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2024 Arif Balik <arifbalik@outlook.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Verify STM32 TSC peripheral is configured properly and can be started
+ *
+ * @details
+ * This test requires an external connection on the stm32u083c_dk board. The
+ * pin GPIOA 10 should be connected to GPIOD 2 manually so that sync signal can
+ * be generated. Also make sure to press TS1 pad on the board in order to
+ * generate touch signal on test 5.
+ * - Test Steps
+ *   -# Get a TSC device
+ *   -# Verify the device is ready
+ *   -# Verify MIMO region with device tree values
+ *   -# Test the acquisition in polling mode
+ *   -# Test the acquisition in interrupt mode
+ * - Expected Results
+ *   -# The device is ready
+ *   -# The device tree values are correctly mapped to the TSC registers
+ *   -# The acquisition is successful in polling mode
+ *   -# The acquisition is successful in interrupt mode
+ *
+ */
+
+#include <soc.h>
+#include <autoconf.h>
+#include <inttypes.h>
+#include <zephyr/ztest.h>
+#include <zephyr/device.h>
+#include <zephyr/kernel.h>
+#include <zephyr/input/input.h>
+#include <zephyr/drivers/gpio.h>
+
+#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_tsc)
+#define TSC_NODE DT_INST(0, st_stm32_tsc)
+#else
+#error "Could not find an st,stm32-tsc compatible device in DT"
+#endif
+
+#define ZEPHYR_USER_NODE DT_PATH(zephyr_user)
+
+const struct gpio_dt_spec signal_mock = GPIO_DT_SPEC_GET(ZEPHYR_USER_NODE, signal_gpios);
+
+ZTEST(stm32_tsc, test_1_device_ready)
+{
+	const struct device *dev = DEVICE_DT_GET(TSC_NODE);
+
+	zassert_true(device_is_ready(dev), "STM32 TSC device is not ready");
+}
+
+ZTEST(stm32_tsc, test_2_cr_reg)
+{
+	TSC_TypeDef *tsc = (TSC_TypeDef *)DT_REG_ADDR(TSC_NODE);
+
+	volatile const uint32_t *tsc_cr = &tsc->CR;
+	const uint32_t pgpsc = LOG2CEIL(DT_PROP(TSC_NODE, st_pulse_generator_prescaler));
+	const uint8_t ctph = DT_PROP(TSC_NODE, st_charge_transfer_pulse_high);
+	const uint8_t ctpl = DT_PROP(TSC_NODE, st_charge_transfer_pulse_low);
+	const uint8_t ssd = DT_PROP(TSC_NODE, st_spread_spectrum_deviation);
+	const bool spread_spectrum = DT_PROP(TSC_NODE, st_spread_spectrum);
+	const uint8_t sscpsc = DT_PROP(TSC_NODE, st_spread_spectrum_prescaler);
+	const uint16_t max_count = LOG2CEIL(DT_PROP(TSC_NODE, st_max_count_value) + 1) - 8;
+	const bool iodef = DT_PROP(TSC_NODE, st_iodef_float);
+	const bool sync_pol = DT_PROP(TSC_NODE, st_syncpol_rising);
+	const bool sync_acq = DT_PROP(TSC_NODE, st_synced_acquisition);
+
+	/* check charge transfer pulse high value (bits 31:28) */
+	zassert_equal((*tsc_cr & TSC_CR_CTPL_Msk) >> TSC_CR_CTPL_Pos, ctph - 1,
+		      "CTPH value is not correct, expected %d, got %d", ctph - 1,
+		      (*tsc_cr & TSC_CR_CTPL_Msk) >> TSC_CR_CTPL_Pos);
+
+	/* check charge transfer pulse low value (bits 27:24) */
+	zassert_equal((*tsc_cr & TSC_CR_CTPL_Msk) >> TSC_CR_CTPL_Pos, ctpl - 1,
+		      "CTPL value is not correct, expected %d, got %d", ctpl - 1,
+		      (*tsc_cr & TSC_CR_CTPL_Msk) >> TSC_CR_CTPL_Pos);
+
+	/* check spread spectrum deviation value (bits 23:17) */
+	zassert_equal((*tsc_cr & TSC_CR_SSD_Msk) >> TSC_CR_SSD_Pos, ssd,
+		      "SSD value is not correct, expected %d, got %d", ssd,
+		      (*tsc_cr & TSC_CR_SSD_Msk) >> TSC_CR_SSD_Pos);
+
+	/* check spread spectrum enable bit (bit 16) */
+	if (spread_spectrum) {
+		zexpect_true(*tsc_cr & TSC_CR_SSE_Msk);
+	} else {
+		zexpect_false(*tsc_cr & TSC_CR_SSE_Msk);
+	}
+
+	/* check spread spectrum prescaler value (bits 15) */
+	if (sscpsc == 2) {
+		zexpect_true(*tsc_cr & TSC_CR_SSPSC_Msk);
+	} else {
+		zexpect_false(*tsc_cr & TSC_CR_SSPSC_Msk);
+	}
+
+	/* check pulse generator prescaler value (bits 14:12) */
+	zassert_equal((*tsc_cr & TSC_CR_PGPSC_Msk), pgpsc << TSC_CR_PGPSC_Pos,
+		      "PGPSC value is not correct, expected %d, got %d", pgpsc,
+		      (*tsc_cr & TSC_CR_PGPSC_Msk));
+
+	/* check max count value (bits 7:5) */
+	zassert_equal((*tsc_cr & TSC_CR_MCV_Msk), max_count << TSC_CR_MCV_Pos,
+		      "MCV value is not correct, expected %d, got %d", max_count,
+		      (*tsc_cr & TSC_CR_MCV_Msk));
+
+	/* check I/O default mode bit (bit 4) */
+	if (iodef) {
+		zexpect_true(*tsc_cr & TSC_CR_IODEF_Msk);
+	} else {
+		zexpect_false(*tsc_cr & TSC_CR_IODEF_Msk);
+	}
+
+	/* check sync polarity bit (bit 3) */
+	if (sync_pol) {
+		zexpect_true(*tsc_cr & TSC_CR_SYNCPOL_Msk);
+	} else {
+		zexpect_false(*tsc_cr & TSC_CR_SYNCPOL_Msk);
+	}
+
+	/* check sync acquisition bit (bit 2) */
+	if (sync_acq) {
+		zexpect_true(*tsc_cr & TSC_CR_AM_Msk);
+	} else {
+		zexpect_false(*tsc_cr & TSC_CR_AM_Msk);
+	}
+
+	/* check TSC enable bit (bit 0) */
+	zexpect_true(*tsc_cr & TSC_CR_TSCE_Msk);
+}
+
+ZTEST(stm32_tsc, test_3_group_registers)
+{
+	TSC_TypeDef *tsc = (TSC_TypeDef *)DT_REG_ADDR(TSC_NODE);
+	volatile const uint32_t *tsc_iohcr = &tsc->IOHCR;
+	volatile const uint32_t *tsc_ioscr = &tsc->IOSCR;
+	volatile const uint32_t *tsc_ioccr = &tsc->IOCCR;
+	volatile const uint32_t *tsc_iogcsr = &tsc->IOGCSR;
+
+#define GET_GROUP_BITS(val) (uint32_t)(((val) & 0x0f) << ((group - 1) * 4))
+
+#define STM32_TSC_GROUP_TEST(node)                                                                 \
+	do {                                                                                       \
+		const uint8_t group = DT_PROP(node, group);                                        \
+		const uint8_t channel_ios = DT_PROP(node, channel_ios);                            \
+		const uint8_t sampling_io = DT_PROP(node, sampling_io);                            \
+		const bool use_as_shield = DT_PROP(node, st_use_as_shield);                        \
+                                                                                                   \
+		/* check schmitt trigger hysteresis for enabled I/Os */                            \
+		zassert_equal((*tsc_iohcr & GET_GROUP_BITS(channel_ios | sampling_io)), 0,         \
+			      "Schmitt trigger hysteresis not disabled, expected %d, got %d", 0,   \
+			      (*tsc_iohcr & GET_GROUP_BITS(channel_ios | sampling_io)));           \
+                                                                                                   \
+		/* check channel I/Os */                                                           \
+		zassert_equal(                                                                     \
+			(*tsc_ioccr & GET_GROUP_BITS(channel_ios)), GET_GROUP_BITS(channel_ios),   \
+			"Channel I/Os value is not correct, expected %d, got %d",                  \
+			GET_GROUP_BITS(channel_ios), (*tsc_ioccr & GET_GROUP_BITS(channel_ios)));  \
+                                                                                                   \
+		/* check sampling I/O */                                                           \
+		zassert_equal(                                                                     \
+			(*tsc_ioscr & GET_GROUP_BITS(sampling_io)), GET_GROUP_BITS(sampling_io),   \
+			"Sampling I/O value is not correct, expected %d, got %d",                  \
+			GET_GROUP_BITS(sampling_io), (*tsc_ioscr & GET_GROUP_BITS(sampling_io)));  \
+                                                                                                   \
+		/* check enabled groups */                                                         \
+		if (use_as_shield) {                                                               \
+			zassert_not_equal((*tsc_iogcsr & BIT(group - 1)), BIT(group - 1),          \
+					  "Group %d is a shield group and should not be enabled",  \
+					  group);                                                  \
+		} else {                                                                           \
+			zassert_equal((*tsc_iogcsr & BIT(group - 1)), BIT(group - 1),              \
+				      "Group %d is not enabled", group);                           \
+		}                                                                                  \
+	} while (0)
+
+#define GROUP_TEST_RUN(node) STM32_TSC_GROUP_TEST(node);
+
+	DT_FOREACH_CHILD_STATUS_OKAY(TSC_NODE, GROUP_TEST_RUN);
+}
+
+static volatile bool tsc_input_received;
+
+static void tsc_input_callback(struct input_event *evt, void *user_data)
+{
+	ARG_UNUSED(evt);
+	ARG_UNUSED(user_data);
+
+	tsc_input_received = true;
+}
+INPUT_CALLBACK_DEFINE(NULL, tsc_input_callback, NULL);
+
+ZTEST(stm32_tsc, test_5_acquisition_interrupt)
+{
+	TSC_TypeDef *tsc = (TSC_TypeDef *)DT_REG_ADDR(TSC_NODE);
+	volatile const uint32_t *tsc_isr = &tsc->ISR;
+
+	k_sleep(K_MSEC(100));
+
+	/* test ISR register max count error flag */
+	zexpect_false((*tsc_isr & TSC_ISR_MCEF_Msk) >> TSC_ISR_MCEF_Pos);
+
+	/* this should fail because of the sync pin */
+	zexpect_false(tsc_input_received);
+
+	zexpect_ok(gpio_pin_toggle_dt(&signal_mock));
+
+	/* press the TS1 pad */
+
+	k_sleep(K_MSEC(3000));
+
+	zexpect_true(tsc_input_received);
+}
diff --git a/tests/drivers/input/tsc_keys/testcase.yaml b/tests/drivers/input/tsc_keys/testcase.yaml
new file mode 100644
index 00000000000..4122f550ad8
--- /dev/null
+++ b/tests/drivers/input/tsc_keys/testcase.yaml
@@ -0,0 +1,6 @@
+tests:
+  drivers.input.stm32_tsc:
+    tags: drivers input stm32 tsc
+    filter: dt_compat_enabled("st,stm32-tsc")
+    depends_on: tsc
+    integration_platforms: [stm32u083c_dk]
diff --git a/tests/drivers/interrupt_controller/multi_level_backend/testcase.yaml b/tests/drivers/interrupt_controller/multi_level_backend/testcase.yaml
index 9455766dbc7..18c6ee73268 100644
--- a/tests/drivers/interrupt_controller/multi_level_backend/testcase.yaml
+++ b/tests/drivers/interrupt_controller/multi_level_backend/testcase.yaml
@@ -5,7 +5,7 @@ common:
   tags:
     - drivers
     - interrupt
-  filter: CONFIG_MULTI_LEVEL_INTERRUPTS and not CONFIG_LEGACY_MULTI_LEVEL_TABLE_GENERATION
+  filter: CONFIG_MULTI_LEVEL_INTERRUPTS
   platform_allow:
     - m2gl025_miv/miv
     - qemu_riscv32/qemu_virt_riscv32
diff --git a/tests/drivers/kscan/kscan_api/CMakeLists.txt b/tests/drivers/kscan/kscan_api/CMakeLists.txt
deleted file mode 100644
index 385203698cf..00000000000
--- a/tests/drivers/kscan/kscan_api/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-cmake_minimum_required(VERSION 3.20.0)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(kscan_api)
-
-FILE(GLOB app_sources src/*.c)
-target_sources(app PRIVATE ${app_sources})
diff --git a/tests/drivers/kscan/kscan_api/mec15xxevb_assy6853.conf b/tests/drivers/kscan/kscan_api/mec15xxevb_assy6853.conf
deleted file mode 100644
index ded66973827..00000000000
--- a/tests/drivers/kscan/kscan_api/mec15xxevb_assy6853.conf
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_KSCAN=y
-CONFIG_ZTEST=y
diff --git a/tests/drivers/kscan/kscan_api/prj.conf b/tests/drivers/kscan/kscan_api/prj.conf
deleted file mode 100644
index f291b8d5b75..00000000000
--- a/tests/drivers/kscan/kscan_api/prj.conf
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_KSCAN=y
-CONFIG_TEST_USERSPACE=y
-CONFIG_ZTEST=y
diff --git a/tests/drivers/kscan/kscan_api/src/main.c b/tests/drivers/kscan/kscan_api/src/main.c
deleted file mode 100644
index 5dc79c6f05b..00000000000
--- a/tests/drivers/kscan/kscan_api/src/main.c
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (c) 2019 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-
-#include <zephyr/ztest.h>
-
-ZTEST_SUITE(kscan_basic, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/drivers/kscan/kscan_api/src/test_kscan.c b/tests/drivers/kscan/kscan_api/src/test_kscan.c
deleted file mode 100644
index 624255789e7..00000000000
--- a/tests/drivers/kscan/kscan_api/src/test_kscan.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright (c) 2019 Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/device.h>
-#include <stdlib.h>
-#include <zephyr/drivers/kscan.h>
-#include <zephyr/kernel.h>
-#include <zephyr/ztest.h>
-
-static void kb_callback(const struct device *dev, uint32_t row, uint32_t col,
-			bool pressed)
-{
-	ARG_UNUSED(dev);
-	ARG_UNUSED(row);
-	ARG_UNUSED(col);
-	ARG_UNUSED(pressed);
-}
-
-static int test_kb_callback(void)
-{
-	const struct device *const kscan_dev = DEVICE_DT_GET(DT_ALIAS(kscan0));
-
-	if (!device_is_ready(kscan_dev)) {
-		TC_PRINT("KBSCAN device is not ready\n");
-		return TC_FAIL;
-	}
-
-	if (kscan_config(kscan_dev, kb_callback) != 0) {
-		TC_PRINT("Unexpected error code received\n");
-		return TC_FAIL;
-	}
-
-	return TC_PASS;
-}
-
-static int test_null_callback(void)
-{
-	const struct device *const kscan_dev = DEVICE_DT_GET(DT_ALIAS(kscan0));
-
-	if (!device_is_ready(kscan_dev)) {
-		TC_PRINT("KBSCAN device is not ready\n");
-		return TC_FAIL;
-	}
-
-	if (kscan_config(kscan_dev, NULL) != -EINVAL) {
-		TC_PRINT("Unexpected error code received\n");
-		return TC_FAIL;
-	}
-
-	return TC_PASS;
-}
-
-static int test_disable_enable_callback(void)
-{
-	const struct device *const kscan_dev = DEVICE_DT_GET(DT_ALIAS(kscan0));
-
-	if (!device_is_ready(kscan_dev)) {
-		TC_PRINT("KBSCAN device is not ready\n");
-		return TC_FAIL;
-	}
-
-	if (kscan_config(kscan_dev, kb_callback) != 0) {
-		TC_PRINT("Unexpected error code received\n");
-		return TC_FAIL;
-	}
-
-	if (kscan_disable_callback(kscan_dev) != 0) {
-		TC_PRINT("Error while disabling callback\n");
-		return TC_FAIL;
-	}
-
-	if (kscan_enable_callback(kscan_dev) != 0) {
-		TC_PRINT("Error while enabling callback\n");
-		return TC_FAIL;
-	}
-
-	return TC_PASS;
-}
-
-ZTEST(kscan_basic, test_init_callback)
-{
-	/* Configure kscan matrix with an appropriate callback */
-	zassert_true(test_kb_callback() == TC_PASS);
-	k_sleep(K_MSEC(1000));
-
-	/* Configure kscan with a null callback */
-	zassert_true(test_null_callback() == TC_PASS);
-}
-
-ZTEST(kscan_basic, test_control_callback)
-{
-	/* Disable/enable notifications to user */
-	zassert_true(test_disable_enable_callback() == TC_PASS);
-	k_sleep(K_MSEC(1000));
-}
diff --git a/tests/drivers/kscan/kscan_api/testcase.yaml b/tests/drivers/kscan/kscan_api/testcase.yaml
deleted file mode 100644
index 2f37671d4c2..00000000000
--- a/tests/drivers/kscan/kscan_api/testcase.yaml
+++ /dev/null
@@ -1,16 +0,0 @@
-tests:
-  drivers.kscan:
-    tags:
-      - drivers
-      - kscan
-      - userspace
-    depends_on: kscan
-    platform_exclude: mec15xxevb_assy6853
-    filter: dt_alias_exists("kscan0")
-  drivers.kscan.mec15xxevb_assy6853:
-    depends_on: kscan
-    tags:
-      - drivers
-      - kscan
-    extra_args: CONF_FILE="mec15xxevb_assy6853.conf"
-    platform_allow: mec15xxevb_assy6853
diff --git a/tests/drivers/kscan/kscan_input/CMakeLists.txt b/tests/drivers/kscan/kscan_input/CMakeLists.txt
deleted file mode 100644
index d67acd5a2f4..00000000000
--- a/tests/drivers/kscan/kscan_input/CMakeLists.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-cmake_minimum_required(VERSION 3.20.0)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-
-project(kscan_input)
-
-FILE(GLOB app_sources src/*.c)
-target_sources(app PRIVATE ${app_sources})
diff --git a/tests/drivers/kscan/kscan_input/boards/native_sim.overlay b/tests/drivers/kscan/kscan_input/boards/native_sim.overlay
deleted file mode 100644
index 4e36164ab63..00000000000
--- a/tests/drivers/kscan/kscan_input/boards/native_sim.overlay
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * Copyright 2023 Google LLC
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
-	/delete-node/ input_sdl_touch;
-
-	fake_input_device: fake-device {
-		compatible = "vnd,input-device";
-		kscan_input: kscan-input {
-			compatible = "zephyr,kscan-input";
-		};
-	};
-};
diff --git a/tests/drivers/kscan/kscan_input/boards/native_sim_native_64.overlay b/tests/drivers/kscan/kscan_input/boards/native_sim_native_64.overlay
deleted file mode 100644
index 91647f82e20..00000000000
--- a/tests/drivers/kscan/kscan_input/boards/native_sim_native_64.overlay
+++ /dev/null
@@ -1,6 +0,0 @@
-/*
- * Copyright (c) 2024 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#include "native_sim.overlay"
diff --git a/tests/drivers/kscan/kscan_input/prj.conf b/tests/drivers/kscan/kscan_input/prj.conf
deleted file mode 100644
index 79104173119..00000000000
--- a/tests/drivers/kscan/kscan_input/prj.conf
+++ /dev/null
@@ -1,6 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_ZTEST=y
-CONFIG_KSCAN=y
-CONFIG_INPUT=y
-CONFIG_INPUT_MODE_SYNCHRONOUS=y
diff --git a/tests/drivers/kscan/kscan_input/src/main.c b/tests/drivers/kscan/kscan_input/src/main.c
deleted file mode 100644
index b7c8c404bfe..00000000000
--- a/tests/drivers/kscan/kscan_input/src/main.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright 2023 Google LLC
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/device.h>
-#include <zephyr/drivers/kscan.h>
-#include <zephyr/input/input.h>
-#include <zephyr/kernel.h>
-#include <zephyr/ztest.h>
-
-static const struct device *kscan_dev = DEVICE_DT_GET(
-		DT_NODELABEL(kscan_input));
-static const struct device *input_dev = DEVICE_DT_GET(
-		DT_NODELABEL(fake_input_device));
-
-DEVICE_DT_DEFINE(DT_INST(0, vnd_input_device), NULL, NULL, NULL, NULL,
-		 PRE_KERNEL_1, CONFIG_KERNEL_INIT_PRIORITY_DEVICE, NULL);
-
-static struct {
-	uint32_t row;
-	uint32_t col;
-	bool pressed;
-} last_cb_val;
-static int callback_calls_count;
-
-static void kscan_callback(const struct device *dev, uint32_t row, uint32_t col,
-			   bool pressed)
-{
-	TC_PRINT("row = %u col = %u %d\n", row, col, pressed);
-
-	callback_calls_count++;
-	last_cb_val.row = row;
-	last_cb_val.col = col;
-	last_cb_val.pressed = pressed;
-}
-
-ZTEST(kscan_input, test_kscan_input)
-{
-	kscan_config(kscan_dev, kscan_callback);
-	kscan_enable_callback(kscan_dev);
-
-	input_report_abs(input_dev, INPUT_ABS_X, 101, false, K_FOREVER);
-	zassert_equal(callback_calls_count, 0);
-
-	input_report_abs(input_dev, INPUT_ABS_Y, 102, false, K_FOREVER);
-	zassert_equal(callback_calls_count, 0);
-
-	input_report_key(input_dev, INPUT_BTN_TOUCH, 1, true, K_FOREVER);
-	zassert_equal(callback_calls_count, 1);
-	zassert_equal(last_cb_val.col, 101);
-	zassert_equal(last_cb_val.row, 102);
-	zassert_equal(last_cb_val.pressed, true);
-
-	input_report_abs(input_dev, INPUT_ABS_X, 103, true, K_FOREVER);
-	zassert_equal(callback_calls_count, 2);
-	zassert_equal(last_cb_val.col, 103);
-	zassert_equal(last_cb_val.row, 102);
-	zassert_equal(last_cb_val.pressed, true);
-
-	input_report_key(input_dev, INPUT_BTN_TOUCH, 0, true, K_FOREVER);
-	zassert_equal(callback_calls_count, 3);
-	zassert_equal(last_cb_val.col, 103);
-	zassert_equal(last_cb_val.row, 102);
-	zassert_equal(last_cb_val.pressed, false);
-}
-
-ZTEST_SUITE(kscan_input, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/drivers/kscan/kscan_input/testcase.yaml b/tests/drivers/kscan/kscan_input/testcase.yaml
deleted file mode 100644
index 82f2c1df2d9..00000000000
--- a/tests/drivers/kscan/kscan_input/testcase.yaml
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-tests:
-  drivers.input.kscan_input:
-    platform_allow:
-      - native_sim
-      - native_sim/native/64
-    tags:
-      - drivers
-      - kscan
-      - input
-    integration_platforms:
-      - native_sim
diff --git a/tests/drivers/mbox/mbox_data/CMakeLists.txt b/tests/drivers/mbox/mbox_data/CMakeLists.txt
index e816cf7426f..b339c57068b 100644
--- a/tests/drivers/mbox/mbox_data/CMakeLists.txt
+++ b/tests/drivers/mbox/mbox_data/CMakeLists.txt
@@ -11,7 +11,8 @@ set(REMOTE_ZEPHYR_DIR ${CMAKE_CURRENT_BINARY_DIR}/../remote/zephyr)
 
 if(CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7 OR
    CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 OR
-   CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0)
+   CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 OR
+   CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33)
   message(STATUS "${BOARD}${BOARD_QUALIFIERS} compile as Main in this sample")
 else()
   message(FATAL_ERROR "${BOARD}${BOARD_QUALIFIERS} is not supported for this sample")
diff --git a/tests/drivers/mbox/mbox_data/Kconfig.sysbuild b/tests/drivers/mbox/mbox_data/Kconfig.sysbuild
index 66a4e929ae2..9e1d0a00384 100644
--- a/tests/drivers/mbox/mbox_data/Kconfig.sysbuild
+++ b/tests/drivers/mbox/mbox_data/Kconfig.sysbuild
@@ -10,3 +10,4 @@ string
 	default "mimxrt1170_evk/mimxrt1176/cm4" if $(BOARD) = "mimxrt1170_evk"
 	default "mimxrt1160_evk/mimxrt1166/cm4" if $(BOARD) = "mimxrt1160_evk"
 	default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69"
+	default "mimxrt1180_evk/mimxrt1189/cm7" if $(BOARD) = "mimxrt1180_evk"
diff --git a/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay b/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay
index b178929819b..0369a05f253 100644
--- a/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay
+++ b/tests/drivers/mbox/mbox_data/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay
@@ -6,7 +6,7 @@
 
 / {
 	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay b/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay
index ecec226423a..8c4ac95144f 100644
--- a/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay
+++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1160_evk_mimxrt1166_cm7.overlay
@@ -6,7 +6,7 @@
 
 / {
 	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7.conf
similarity index 100%
rename from samples/drivers/mbox/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf
rename to tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7.conf
diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
new file mode 100644
index 00000000000..8c4ac95144f
--- /dev/null
+++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
@@ -0,0 +1,37 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	chosen {
+		/* Delete ipc chosen property where old IPM mailbox driver below is
+		 * configured.
+		 */
+		/delete-property/ zephyr,ipc;
+	};
+
+	soc {
+		/* Delete IPM Driver node nxp,imx-mu */
+		/delete-node/ mailbox@40c48000;
+
+		/* Attach MBOX driver to MU Unit */
+		mbox:mbox@40c48000 {
+			compatible = "nxp,mbox-imx-mu";
+			reg = <0x40c48000 0x4000>;
+			interrupts = <118 0>;
+			rx-channels = <4>;
+			#mbox-cells = <1>;
+			status = "okay";
+		};
+	};
+
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox 3>, <&mbox 2>, <&mbox 1>, <&mbox 0>, <&mbox 2>,
+			 <&mbox 3>, <&mbox 0>, <&mbox 1>;
+		mbox-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3",
+			     "rx3";
+	};
+};
diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf
deleted file mode 100644
index 583b4950360..00000000000
--- a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_MBOX_NXP_IMX_MU=y
-CONFIG_INCLUDE_REMOTE_DIR=y
-CONFIG_SECOND_CORE_MCUX=y
diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay
deleted file mode 100644
index ecec226423a..00000000000
--- a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_A.overlay
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright 2024 NXP
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
-	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
-		 * configured.
-		 */
-		/delete-property/ zephyr,ipc;
-	};
-
-	soc {
-		/* Delete IPM Driver node nxp,imx-mu */
-		/delete-node/ mailbox@40c48000;
-
-		/* Attach MBOX driver to MU Unit */
-		mbox:mbox@40c48000 {
-			compatible = "nxp,mbox-imx-mu";
-			reg = <0x40c48000 0x4000>;
-			interrupts = <118 0>;
-			rx-channels = <4>;
-			#mbox-cells = <1>;
-			status = "okay";
-		};
-	};
-
-	mbox-consumer {
-		compatible = "vnd,mbox-consumer";
-		mboxes = <&mbox 3>, <&mbox 2>, <&mbox 1>, <&mbox 0>, <&mbox 2>,
-			 <&mbox 3>, <&mbox 0>, <&mbox 1>;
-		mbox-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3",
-			     "rx3";
-	};
-};
diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf
deleted file mode 100644
index 0dfb100ed70..00000000000
--- a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.conf
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_MBOX_NXP_IMX_MU=y
-CONFIG_SECOND_CORE_MCUX=y
-CONFIG_INCLUDE_REMOTE_DIR=y
diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay b/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
deleted file mode 100644
index ecec226423a..00000000000
--- a/tests/drivers/mbox/mbox_data/boards/mimxrt1170_evk_mimxrt1176_cm7_B.overlay
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright 2024 NXP
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
-	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
-		 * configured.
-		 */
-		/delete-property/ zephyr,ipc;
-	};
-
-	soc {
-		/* Delete IPM Driver node nxp,imx-mu */
-		/delete-node/ mailbox@40c48000;
-
-		/* Attach MBOX driver to MU Unit */
-		mbox:mbox@40c48000 {
-			compatible = "nxp,mbox-imx-mu";
-			reg = <0x40c48000 0x4000>;
-			interrupts = <118 0>;
-			rx-channels = <4>;
-			#mbox-cells = <1>;
-			status = "okay";
-		};
-	};
-
-	mbox-consumer {
-		compatible = "vnd,mbox-consumer";
-		mboxes = <&mbox 3>, <&mbox 2>, <&mbox 1>, <&mbox 0>, <&mbox 2>,
-			 <&mbox 3>, <&mbox 0>, <&mbox 1>;
-		mbox-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3",
-			     "rx3";
-	};
-};
diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1180_evk_mimxrt1189_cm33.conf b/tests/drivers/mbox/mbox_data/boards/mimxrt1180_evk_mimxrt1189_cm33.conf
new file mode 100644
index 00000000000..91e03e2e83a
--- /dev/null
+++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1180_evk_mimxrt1189_cm33.conf
@@ -0,0 +1,3 @@
+CONFIG_SECOND_CORE_MCUX=y
+CONFIG_INCLUDE_REMOTE_DIR=y
+CONFIG_MBOX_NXP_IMX_MU=y
diff --git a/tests/drivers/mbox/mbox_data/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay b/tests/drivers/mbox/mbox_data/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
new file mode 100644
index 00000000000..81461aa9857
--- /dev/null
+++ b/tests/drivers/mbox/mbox_data/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox1_a 3>, <&mbox1_a 2>, <&mbox1_a 1>, <&mbox1_a 0>,
+			<&mbox1_a 2>, <&mbox1_a 3>, <&mbox1_a 0>, <&mbox1_a 1>;
+		mbox-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3",
+			"rx3";
+	};
+};
diff --git a/tests/drivers/mbox/mbox_data/remote/CMakeLists.txt b/tests/drivers/mbox/mbox_data/remote/CMakeLists.txt
index d3d0991a65c..67c3064edbc 100644
--- a/tests/drivers/mbox/mbox_data/remote/CMakeLists.txt
+++ b/tests/drivers/mbox/mbox_data/remote/CMakeLists.txt
@@ -9,7 +9,8 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
 
 if(CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM4 OR
    CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM4 OR
-   CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU1)
+   CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU1 OR
+   CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM7)
   message(STATUS "${BOARD}${BOARD_QUALIFIERS} compile as remote in this sample")
 else()
   message(FATAL_ERROR "${BOARD}${BOARD_QUALIFIERS} is not supported for this sample")
diff --git a/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay b/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay
index a4ced8e5ec6..c38e2728d17 100644
--- a/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay
+++ b/tests/drivers/mbox/mbox_data/remote/boards/lpcxpresso55s69_lpc55s69_cpu1.overlay
@@ -6,7 +6,7 @@
 
 / {
 	chosen {
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay
index ccf8543fa67..49185a9b365 100644
--- a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay
+++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1160_evk_mimxrt1166_cm4.overlay
@@ -10,7 +10,7 @@
 		zephyr,console = &lpuart2;
 		zephyr,shell-uart = &lpuart2;
 
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay
index ccf8543fa67..49185a9b365 100644
--- a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay
+++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4.overlay
@@ -10,7 +10,7 @@
 		zephyr,console = &lpuart2;
 		zephyr,shell-uart = &lpuart2;
 
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay
index ccf8543fa67..49185a9b365 100644
--- a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay
+++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1170_evk_mimxrt1176_cm4_B.overlay
@@ -10,7 +10,7 @@
 		zephyr,console = &lpuart2;
 		zephyr,shell-uart = &lpuart2;
 
-		/* Delete ipc chosen property where old IPM mailbox driver bellow is
+		/* Delete ipc chosen property where old IPM mailbox driver below is
 		 * configured.
 		 */
 		/delete-property/ zephyr,ipc;
diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.conf b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
new file mode 100644
index 00000000000..77adcfa24f4
--- /dev/null
+++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
@@ -0,0 +1,2 @@
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_SECOND_CORE_MCUX=y
diff --git a/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
new file mode 100644
index 00000000000..e7453ca6ea1
--- /dev/null
+++ b/tests/drivers/mbox/mbox_data/remote/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox1_b 2>, <&mbox1_b 3>, <&mbox1_b 0>, <&mbox1_b 1>, <&mbox1_b 3>,
+			 <&mbox1_b 2>, <&mbox1_b 1>, <&mbox1_b 0>;
+		mbox-names = "tx0", "rx0", "tx1", "rx1", "tx2", "rx2", "tx3",
+			     "rx3";
+	};
+};
diff --git a/tests/drivers/mbox/mbox_data/sysbuild.cmake b/tests/drivers/mbox/mbox_data/sysbuild.cmake
index 0fb83fbadd3..4b68b671ccb 100644
--- a/tests/drivers/mbox/mbox_data/sysbuild.cmake
+++ b/tests/drivers/mbox/mbox_data/sysbuild.cmake
@@ -18,7 +18,8 @@ ExternalZephyrProject_Add(
 
 if(SB_CONFIG_BOARD_MIMXRT1160_EVK_MIMXRT1166_CM7 OR
    SB_CONFIG_BOARD_MIMXRT1170_EVK_MIMXRT1176_CM7 OR
-   SB_CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0)
+   SB_CONFIG_BOARD_LPCXPRESSO55S69_LPC55S69_CPU0 OR
+   SB_CONFIG_BOARD_MIMXRT1180_EVK_MIMXRT1189_CM33)
   # For these NXP boards the main core application is dependent on
   # 'zephyr_image_info.h' generated by remote application.
 
diff --git a/tests/drivers/mbox/mbox_data/testcase.yaml b/tests/drivers/mbox/mbox_data/testcase.yaml
index 0044581cdb8..f369a5dae61 100644
--- a/tests/drivers/mbox/mbox_data/testcase.yaml
+++ b/tests/drivers/mbox/mbox_data/testcase.yaml
@@ -4,11 +4,7 @@ tests:
       - drivers
       - mbox
     sysbuild: true
-    platform_allow:
-      - mimxrt1170_evk@B/mimxrt1176/cm7
-      - mimxrt1170_evk/mimxrt1176/cm7
-      - mimxrt1160_evk/mimxrt1166/cm7
-      - lpcxpresso55s69/lpc55s69/cpu0
+    filter: dt_compat_enabled("vnd,mbox-consumer")
     integration_platforms:
-      - mimxrt1170_evk@B/mimxrt1176/cm7
+      - mimxrt1170_evk/mimxrt1176/cm7
       - lpcxpresso55s69/lpc55s69/cpu0
diff --git a/tests/drivers/mbox/mbox_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/mbox/mbox_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..00e65fae41a
--- /dev/null
+++ b/tests/drivers/mbox/mbox_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&cpuapp_vevif_tx 21>, <&cpuapp_vevif_tx 32>,
+				 <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_rx 32>;
+		mbox-names = "remote_valid", "remote_incorrect",
+					 "local_valid", "local_incorrect";
+	};
+};
+
+&cpuapp_vevif_rx {
+	status = "okay";
+};
+
+&cpuapp_vevif_tx {
+	status = "okay";
+};
diff --git a/tests/drivers/mbox/mbox_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/mbox/mbox_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..00e65fae41a
--- /dev/null
+++ b/tests/drivers/mbox/mbox_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&cpuapp_vevif_tx 21>, <&cpuapp_vevif_tx 32>,
+				 <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_rx 32>;
+		mbox-names = "remote_valid", "remote_incorrect",
+					 "local_valid", "local_incorrect";
+	};
+};
+
+&cpuapp_vevif_rx {
+	status = "okay";
+};
+
+&cpuapp_vevif_tx {
+	status = "okay";
+};
diff --git a/tests/drivers/mbox/mbox_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/mbox/mbox_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..e9203a635a6
--- /dev/null
+++ b/tests/drivers/mbox/mbox_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+
+		mboxes = <&cpuapp_vevif_tx 21>, <&cpuapp_vevif_tx 32>,
+				 <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_rx 32>;
+
+		mbox-names = "remote_valid", "remote_incorrect",
+					 "local_valid", "local_incorrect";
+
+	};
+};
+
+&cpuapp_vevif_rx {
+	status = "okay";
+};
+
+&cpuapp_vevif_tx {
+	status = "okay";
+};
diff --git a/tests/drivers/mbox/mbox_error_cases/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/tests/drivers/mbox/mbox_error_cases/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
new file mode 100644
index 00000000000..d812e3a3967
--- /dev/null
+++ b/tests/drivers/mbox/mbox_error_cases/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2024 Epam Systems
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	/*
+	 * Allocating whole openamp region as reserved memory
+	 * to save MPU entries
+	 */
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		openamp_shm: memory-region@62F00000 {
+			compatible = "zephyr,memory-region";
+			reg = <0x62F00000 0x600000>;
+			zephyr,memory-region = "openamp_memory";
+			zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_IO) )>;
+		};
+	};
+
+	mhu1_shm: memory@62F01008 {
+		compatible = "mmio-sram";
+		reg = <0x62F01008 0x8>;
+	};
+
+	mhu3_shm: memory@62F01018 {
+		compatible = "mmio-sram";
+		reg = <0x62F01018 0x8>;
+	};
+
+	mhu4_shm: memory@62F01020 {
+		compatible = "mmio-sram";
+		reg = <0x62F01020 0x8>;
+	};
+
+	mhu5_shm: memory@62F01028 {
+		compatible = "mmio-sram";
+		reg = <0x62F01028 0x8>;
+	};
+
+	mbox-consumer {
+		compatible = "vnd,mbox-consumer";
+		mboxes = <&mbox1 1>, <&mbox1 4>, <&mbox3 0>, <&mbox3 3>;
+		mbox-names = "remote_valid", "remote_incorrect", "local_valid", "local_incorrect";
+	};
+
+};
+
+&mbox1 {
+	shared-memory = <&mhu1_shm>;
+	status = "okay";
+};
+
+&mbox3 {
+	shared-memory = <&mhu3_shm>;
+	status = "okay";
+};
diff --git a/tests/drivers/mbox/mbox_error_cases/sample.yaml b/tests/drivers/mbox/mbox_error_cases/sample.yaml
index f8d9937d0cf..2746a1c2904 100644
--- a/tests/drivers/mbox/mbox_error_cases/sample.yaml
+++ b/tests/drivers/mbox/mbox_error_cases/sample.yaml
@@ -17,6 +17,8 @@ tests:
   tests.drivers.mbox_error_cases.nrf54l:
     platform_allow:
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     extra_args: SNIPPET=nordic-flpr
diff --git a/tests/drivers/modem/modem_socket/CMakeLists.txt b/tests/drivers/modem/modem_socket/CMakeLists.txt
new file mode 100644
index 00000000000..7b85051e687
--- /dev/null
+++ b/tests/drivers/modem/modem_socket/CMakeLists.txt
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(device)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
+
+target_include_directories(app PRIVATE
+    ${ZEPHYR_BASE}/drivers/modem
+    ${ZEPHYR_BASE}/subsys/net/lib/sockets
+)
diff --git a/tests/drivers/modem/modem_socket/prj.conf b/tests/drivers/modem/modem_socket/prj.conf
new file mode 100644
index 00000000000..ffdf488e1e1
--- /dev/null
+++ b/tests/drivers/modem/modem_socket/prj.conf
@@ -0,0 +1,10 @@
+CONFIG_ZTEST=y
+
+CONFIG_NETWORKING=y
+CONFIG_NET_SOCKETS=y
+
+CONFIG_MODEM=y
+CONFIG_MODEM_SOCKET=y
+
+# Default y, not needed.
+CONFIG_ETH_DRIVER=n
diff --git a/tests/drivers/modem/modem_socket/src/main.c b/tests/drivers/modem/modem_socket/src/main.c
new file mode 100644
index 00000000000..33318a199f8
--- /dev/null
+++ b/tests/drivers/modem/modem_socket/src/main.c
@@ -0,0 +1,174 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (C) 2025, Joakim Andersson
+ */
+
+/**
+ * @addtogroup t_modem_driver
+ * @{
+ * @defgroup t_modem_socket test_modem_socket
+ * @}
+ */
+
+#include <zephyr/ztest.h>
+#include "modem_socket.h"
+
+#define MODEM_SOCKETS_MAX 3
+#define MODEM_SOCKETS_BASE_NUM 0
+struct modem_socket_config socket_config;
+struct modem_socket sockets[MODEM_SOCKETS_MAX];
+
+static const struct socket_op_vtable socket_fd_op_vtable = {
+};
+
+ZTEST(modem_socket, test_modem_socket_init_fd_zero)
+{
+	struct modem_socket *sock;
+	int ret;
+
+	ret = modem_socket_init(&socket_config, sockets, MODEM_SOCKETS_MAX, MODEM_SOCKETS_BASE_NUM,
+				false, &socket_fd_op_vtable);
+	zassert_ok(ret);
+
+	/* Check that fd 0 does not return a modem socket object. */
+	sock = modem_socket_from_fd(&socket_config, 0);
+
+	zassert_is_null(sock);
+}
+
+ZTEST(modem_socket, test_modem_socket_init_not_allocated)
+{
+	int ret;
+
+	ret = modem_socket_init(&socket_config, sockets, MODEM_SOCKETS_MAX, MODEM_SOCKETS_BASE_NUM,
+				false, &socket_fd_op_vtable);
+	zassert_ok(ret);
+
+	for (int i = 0; i < ARRAY_SIZE(sockets); i++) {
+		bool result;
+
+		result = modem_socket_is_allocated(&socket_config, &sockets[i]);
+		zassert_false(result);
+	}
+}
+
+ZTEST(modem_socket, test_modem_socket_init_not_assigned)
+{
+	int ret;
+
+	ret = modem_socket_init(&socket_config, sockets, MODEM_SOCKETS_MAX, MODEM_SOCKETS_BASE_NUM,
+				false, &socket_fd_op_vtable);
+	zassert_ok(ret);
+
+	for (int i = 0; i < ARRAY_SIZE(sockets); i++) {
+		bool result;
+
+		result = modem_socket_id_is_assigned(&socket_config, &sockets[i]);
+		zassert_false(result);
+	}
+}
+
+ZTEST(modem_socket, test_modem_socket_init_not_assigned_dynamic)
+{
+	int ret;
+
+	ret = modem_socket_init(&socket_config, sockets, MODEM_SOCKETS_MAX, MODEM_SOCKETS_BASE_NUM,
+				true, &socket_fd_op_vtable);
+	zassert_ok(ret);
+
+	for (int i = 0; i < ARRAY_SIZE(sockets); i++) {
+		bool result;
+
+		result = modem_socket_id_is_assigned(&socket_config, &sockets[i]);
+		zassert_false(result);
+	}
+}
+
+static void test_modem_get_put_all(void)
+{
+	int fds[ARRAY_SIZE(sockets)];
+
+	for (int i = 0; i < ARRAY_SIZE(sockets); i++) {
+		fds[i] = modem_socket_get(&socket_config, AF_INET, SOCK_DGRAM, IPPROTO_TCP);
+		zassert_false(fds[i] < 0);
+	}
+
+	for (int i = 0; i < ARRAY_SIZE(sockets); i++) {
+		modem_socket_put(&socket_config, fds[i]);
+		/* Returned file description is freed by zsock_close, so we need to free it here. */
+		zvfs_free_fd(fds[i]);
+	}
+}
+
+ZTEST(modem_socket, test_modem_socket_get_put_fd_zero)
+{
+	struct modem_socket *sock;
+	int ret;
+
+	ret = modem_socket_init(&socket_config, sockets, MODEM_SOCKETS_MAX, MODEM_SOCKETS_BASE_NUM,
+				false, &socket_fd_op_vtable);
+	zassert_ok(ret);
+
+	test_modem_get_put_all();
+
+	/* Check that fd 0 does not return a modem socket object. */
+	sock = modem_socket_from_fd(&socket_config, 0);
+	zassert_is_null(sock);
+}
+
+ZTEST(modem_socket, test_modem_socket_get_put_not_allocated)
+{
+	int ret;
+
+	ret = modem_socket_init(&socket_config, sockets, MODEM_SOCKETS_MAX, MODEM_SOCKETS_BASE_NUM,
+				false, &socket_fd_op_vtable);
+	zassert_ok(ret);
+
+	test_modem_get_put_all();
+
+	for (int i = 0; i < ARRAY_SIZE(sockets); i++) {
+		bool result;
+
+		result = modem_socket_is_allocated(&socket_config, &sockets[i]);
+		zassert_false(result);
+	}
+}
+
+ZTEST(modem_socket, test_modem_socket_get_put_not_assigned)
+{
+	int ret;
+
+	ret = modem_socket_init(&socket_config, sockets, MODEM_SOCKETS_MAX, MODEM_SOCKETS_BASE_NUM,
+				false, &socket_fd_op_vtable);
+	zassert_ok(ret);
+
+	test_modem_get_put_all();
+
+	for (int i = 0; i < ARRAY_SIZE(sockets); i++) {
+		bool result;
+
+		result = modem_socket_id_is_assigned(&socket_config, &sockets[i]);
+		zassert_false(result);
+	}
+}
+
+ZTEST(modem_socket, test_modem_socket_get_put_not_assigned_dynamic)
+{
+	int ret;
+
+	test_modem_get_put_all();
+
+	ret = modem_socket_init(&socket_config, sockets, MODEM_SOCKETS_MAX, MODEM_SOCKETS_BASE_NUM,
+				true, &socket_fd_op_vtable);
+	zassert_ok(ret);
+
+	for (int i = 0; i < ARRAY_SIZE(sockets); i++) {
+		bool result;
+
+		result = modem_socket_id_is_assigned(&socket_config, &sockets[i]);
+		zassert_false(result);
+	}
+}
+
+ZTEST_SUITE(modem_socket, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/drivers/modem/modem_socket/testcase.yaml b/tests/drivers/modem/modem_socket/testcase.yaml
new file mode 100644
index 00000000000..be62cfd0152
--- /dev/null
+++ b/tests/drivers/modem/modem_socket/testcase.yaml
@@ -0,0 +1,9 @@
+tests:
+  drivers.modem.modem_sockets:
+    tags:
+      - drivers
+      - modem
+    platform_allow:
+      - native_sim
+    integration_platforms:
+      - native_sim
diff --git a/tests/drivers/pinctrl/nrf/testcase.yaml b/tests/drivers/pinctrl/nrf/testcase.yaml
index 252fdd24758..d6e32d4a6b1 100644
--- a/tests/drivers/pinctrl/nrf/testcase.yaml
+++ b/tests/drivers/pinctrl/nrf/testcase.yaml
@@ -3,6 +3,9 @@ tests:
     tags:
       - drivers
       - pinctrl
-    depends_on:
-      - pinctrl
-      - nrf
+    vendor_allow:
+      - nordic
+    platform_exclude:
+      - thingy53/nrf5340/cpunet
+    integration_platforms:
+      - qemu_cortex_m0/nrf51822
diff --git a/tests/drivers/pwm/pwm_api/boards/esp32c6_devkitc.overlay b/tests/drivers/pwm/pwm_api/boards/esp32c6_devkitc_hpcore.overlay
similarity index 100%
rename from tests/drivers/pwm/pwm_api/boards/esp32c6_devkitc.overlay
rename to tests/drivers/pwm/pwm_api/boards/esp32c6_devkitc_hpcore.overlay
diff --git a/tests/drivers/pwm/pwm_api/boards/frdm_mcxw72_mcxw727c_cpu0.overlay b/tests/drivers/pwm/pwm_api/boards/frdm_mcxw72_mcxw727c_cpu0.overlay
new file mode 100644
index 00000000000..b775459e512
--- /dev/null
+++ b/tests/drivers/pwm/pwm_api/boards/frdm_mcxw72_mcxw727c_cpu0.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		pwm-0 = &tpm0;
+	};
+};
diff --git a/tests/drivers/pwm/pwm_api/boards/max78000evkit_max78000_m4.overlay b/tests/drivers/pwm/pwm_api/boards/max78000evkit_max78000_m4.overlay
new file mode 100644
index 00000000000..e57958f7566
--- /dev/null
+++ b/tests/drivers/pwm/pwm_api/boards/max78000evkit_max78000_m4.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		pwm-0 = &pwm0;
+	};
+};
+
+&tmr0a_ioa_p0_2 {
+	power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&timer0 {
+	status = "okay";
+	pwm0: pwm {
+		status = "okay";
+		pinctrl-0 = <&tmr0a_ioa_p0_2>;
+		pinctrl-names = "default";
+	};
+};
diff --git a/tests/drivers/pwm/pwm_api/boards/max78000fthr_max78000_m4.overlay b/tests/drivers/pwm/pwm_api/boards/max78000fthr_max78000_m4.overlay
new file mode 100644
index 00000000000..e57958f7566
--- /dev/null
+++ b/tests/drivers/pwm/pwm_api/boards/max78000fthr_max78000_m4.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		pwm-0 = &pwm0;
+	};
+};
+
+&tmr0a_ioa_p0_2 {
+	power-source=<MAX32_VSEL_VDDIOH>;
+};
+
+&timer0 {
+	status = "okay";
+	pwm0: pwm {
+		status = "okay";
+		pinctrl-0 = <&tmr0a_ioa_p0_2>;
+		pinctrl-names = "default";
+	};
+};
diff --git a/tests/drivers/pwm/pwm_api/boards/mcx_n9xx_evk_mcxn947_cpu0_sctimer.overlay b/tests/drivers/pwm/pwm_api/boards/mcx_n9xx_evk_mcxn947_cpu0_sctimer.overlay
new file mode 100644
index 00000000000..39c235b5ad5
--- /dev/null
+++ b/tests/drivers/pwm/pwm_api/boards/mcx_n9xx_evk_mcxn947_cpu0_sctimer.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Disable flexpwm node as it is mapped to pwm-0 alias which is picked up first by the test.
+ * PWM signal is visible on J3-7.
+ */
+&flexpwm1_pwm0 {
+	status = "disabled";
+};
diff --git a/tests/drivers/pwm/pwm_api/boards/mcxw72_evk_mcxw727c_cpu0.overlay b/tests/drivers/pwm/pwm_api/boards/mcxw72_evk_mcxw727c_cpu0.overlay
new file mode 100644
index 00000000000..b775459e512
--- /dev/null
+++ b/tests/drivers/pwm/pwm_api/boards/mcxw72_evk_mcxw727c_cpu0.overlay
@@ -0,0 +1,11 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		pwm-0 = &tpm0;
+	};
+};
diff --git a/tests/drivers/pwm/pwm_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/tests/drivers/pwm/pwm_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
new file mode 100644
index 00000000000..ff4a1217720
--- /dev/null
+++ b/tests/drivers/pwm/pwm_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
@@ -0,0 +1,25 @@
+/*
+ * Copyright 2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Enable PWM outputs on J24 pin 3 and J22 pin 6. These outputs are not used
+ * by the test, but can be tested using the PWM shell.
+ */
+
+/ {
+	aliases {
+		pwm-0 = &flexpwm1_pwm0;
+		pwm-1 = &flexpwm1_pwm3;
+	};
+};
+
+&flexpwm1_pwm3 {
+	status = "okay";
+};
+
+&flexpwm1_pwm0 {
+	status = "okay";
+};
diff --git a/tests/drivers/pwm/pwm_api/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0_flexio_pwm.overlay b/tests/drivers/pwm/pwm_api/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0_flexio_pwm.overlay
new file mode 100644
index 00000000000..5da4db7aff6
--- /dev/null
+++ b/tests/drivers/pwm/pwm_api/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0_flexio_pwm.overlay
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		pwm-0 = &flexio0_pwm;
+	};
+};
+
+&flexio {
+	status = "okay";
+	flexio0_pwm: flexio0_pwm {
+		compatible = "nxp,flexio-pwm";
+		#pwm-cells = <3>;
+		status = "okay";
+		pinctrl-0 = <&flexio_pwm_default>;
+		pinctrl-names = "default";
+		pwm_0 {
+			pin-id = <7>;
+			prescaler = <1>;
+		};
+	};
+};
diff --git a/tests/drivers/pwm/pwm_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/tests/drivers/pwm/pwm_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
new file mode 100644
index 00000000000..bb25dd8b81c
--- /dev/null
+++ b/tests/drivers/pwm/pwm_api/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
@@ -0,0 +1,13 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&gpt32e3 {
+	pwm3: pwm {
+		status = "okay";
+		pinctrl-0 = <&gpt3_pins>;
+		pinctrl-names = "default";
+	};
+};
diff --git a/tests/drivers/pwm/pwm_api/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/drivers/pwm/pwm_api/boards/s32z2xxdc2_s32z270_rtu0.overlay
new file mode 100644
index 00000000000..eae92bfc7e4
--- /dev/null
+++ b/tests/drivers/pwm/pwm_api/boards/s32z2xxdc2_s32z270_rtu0.overlay
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/s32/S32Z27-BGA594-pinctrl.h>
+
+/ {
+	aliases {
+		pwm-0 = &emios0_pwm;
+	};
+};
+
+&pinctrl {
+	emios0_default: emios0_default {
+		group0 {
+			pinmux = <PK0_EMIOS_0_CH24_O>;
+			output-enable;
+		};
+	};
+};
+
+&emios0 {
+	clock-divider = <133>;
+	status = "okay";
+
+	emios0_pwm: pwm {
+		pinctrl-0 = <&emios0_default>;
+		pinctrl-names = "default";
+		status = "okay";
+
+		pwm_24 {
+			channel = <24>;
+			prescaler = <16>;
+			pwm-mode = "OPWFMB";
+		};
+	};
+};
diff --git a/tests/drivers/pwm/pwm_api/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/drivers/pwm/pwm_api/boards/s32z2xxdc2_s32z270_rtu1.overlay
new file mode 100644
index 00000000000..eae92bfc7e4
--- /dev/null
+++ b/tests/drivers/pwm/pwm_api/boards/s32z2xxdc2_s32z270_rtu1.overlay
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nxp/s32/S32Z27-BGA594-pinctrl.h>
+
+/ {
+	aliases {
+		pwm-0 = &emios0_pwm;
+	};
+};
+
+&pinctrl {
+	emios0_default: emios0_default {
+		group0 {
+			pinmux = <PK0_EMIOS_0_CH24_O>;
+			output-enable;
+		};
+	};
+};
+
+&emios0 {
+	clock-divider = <133>;
+	status = "okay";
+
+	emios0_pwm: pwm {
+		pinctrl-0 = <&emios0_default>;
+		pinctrl-names = "default";
+		status = "okay";
+
+		pwm_24 {
+			channel = <24>;
+			prescaler = <16>;
+			pwm-mode = "OPWFMB";
+		};
+	};
+};
diff --git a/tests/drivers/pwm/pwm_api/boards/siwx917_rb4338a.overlay b/tests/drivers/pwm/pwm_api/boards/siwx917_rb4338a.overlay
new file mode 100644
index 00000000000..e2bf3f35472
--- /dev/null
+++ b/tests/drivers/pwm/pwm_api/boards/siwx917_rb4338a.overlay
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pwm/pwm.h>
+
+/ {
+	aliases {
+		pwm-0 = &pwm;
+	};
+};
+
+&pinctrl0 {
+	pwm_ch: pwm_ch {
+		group1 {
+			pinmux = <PWM_0H_PA7>; /* GPIO_7 P20 */
+		};
+	};
+};
+
+&pwm {
+	pinctrl-0 = <&pwm_ch>;
+	pinctrl-names = "default";
+	pwm_channel1: pwm_channel1 {
+		pwms = <&pwm 0 1000000>;
+	};
+	silabs,pwm_polarity = <PWM_POLARITY_NORMAL>;
+	status = "okay";
+};
diff --git a/tests/drivers/pwm/pwm_api/boards/voice_ra4e1.overlay b/tests/drivers/pwm/pwm_api/boards/voice_ra4e1.overlay
new file mode 100644
index 00000000000..4031e592b20
--- /dev/null
+++ b/tests/drivers/pwm/pwm_api/boards/voice_ra4e1.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+&pinctrl {
+	pwm2_default: pwm2_default {
+		group1 {
+			/* GTIOC2A GTIOC2B */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 3)>,
+				<RA_PSEL(RA_PSEL_GPT1, 1, 2)>;
+		};
+	};
+};
+
+&pwm2 {
+	pinctrl-0 = <&pwm2_default>;
+	pinctrl-names = "default";
+	interrupts = <63 1>, <64 1>;
+	interrupt-names = "gtioca", "overflow";
+	status = "okay";
+};
diff --git a/tests/drivers/pwm/pwm_api/socs/esp32c3_usb.overlay b/tests/drivers/pwm/pwm_api/socs/esp32c3_usb.overlay
new file mode 100644
index 00000000000..173073cecd1
--- /dev/null
+++ b/tests/drivers/pwm/pwm_api/socs/esp32c3_usb.overlay
@@ -0,0 +1,34 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ */
+
+#include <zephyr/dt-bindings/pwm/pwm.h>
+
+/ {
+	aliases {
+		pwm-0 = &ledc0;
+	};
+};
+
+&pinctrl {
+	ledc0_default: ledc0_default {
+		group1 {
+			pinmux = <LEDC_CH0_GPIO2>;
+			output-enable;
+		};
+	};
+};
+
+&ledc0 {
+	pinctrl-0 = <&ledc0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	channel0@0 {
+		reg = <0x0>;
+		timer = <0>;
+	};
+};
diff --git a/tests/drivers/pwm/pwm_api/src/test_pwm.c b/tests/drivers/pwm/pwm_api/src/test_pwm.c
index 2c59ab75ed3..18e77c72590 100644
--- a/tests/drivers/pwm/pwm_api/src/test_pwm.c
+++ b/tests/drivers/pwm/pwm_api/src/test_pwm.c
@@ -56,6 +56,9 @@
 #elif DT_HAS_COMPAT_STATUS_OKAY(renesas_ra_pwm)
 #define PWM_DEV_NODE DT_INST(0, renesas_ra_pwm)
 
+#elif DT_HAS_COMPAT_STATUS_OKAY(renesas_rz_gpt_pwm)
+#define PWM_DEV_NODE DT_INST(0, renesas_rz_gpt_pwm)
+
 #else
 #error "Define a PWM device"
 #endif
diff --git a/tests/drivers/pwm/pwm_api/testcase.yaml b/tests/drivers/pwm/pwm_api/testcase.yaml
index 5aecec06aeb..76f5480a37c 100644
--- a/tests/drivers/pwm/pwm_api/testcase.yaml
+++ b/tests/drivers/pwm/pwm_api/testcase.yaml
@@ -21,15 +21,33 @@ tests:
       or dt_alias_exists("pwm-3")) and CONFIG_DT_HAS_NXP_FLEXIO_ENABLED and
       CONFIG_DT_HAS_NXP_FLEXIO_PWM_ENABLED
     depends_on: pwm
+  drivers.pwm.mimxrt700_evk_mimxrt798s_cm33_cpu0_flexio_pwm:
+    tags:
+      - drivers
+      - pwm
+      - userspace
+    extra_args: DTC_OVERLAY_FILE="boards/mimxrt700_evk_mimxrt798s_cm33_cpu0_flexio_pwm.overlay"
+    platform_allow:
+      - mimxrt700_evk/mimxrt798s/cm33_cpu0
+    filter: (dt_alias_exists("pwm-0") or dt_alias_exists("pwm-1") or dt_alias_exists("pwm-2")
+      or dt_alias_exists("pwm-3")) and CONFIG_DT_HAS_NXP_FLEXIO_ENABLED and
+      CONFIG_DT_HAS_NXP_FLEXIO_PWM_ENABLED
+    depends_on: pwm
   drivers.pwm.pwm_fast:
+    tags:
+      - drivers
+      - pwm
+      - userspace
     extra_args: DTC_OVERLAY_FILE="boards/nrf54h20dk_nrf54h20_cpuapp_fast.overlay"
     platform_allow:
       - nrf54h20dk/nrf54h20/cpuapp
-  drivers.pwm.frdm_mcxn947_mcxn947_cpu0_sctimer:
+  drivers.pwm.mcxn947_cpu0_sctimer:
     extra_args: DTC_OVERLAY_FILE="boards/frdm_mcxn947_mcxn947_cpu0_sctimer.overlay"
     platform_allow:
       - frdm_mcxn947/mcxn947/cpu0
       - frdm_mcxn947/mcxn947/cpu0/qspi
+      - mcx_n9xx_evk/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0/qspi
   drivers.pwm.native_sim:
     platform_allow:
       - native_sim
diff --git a/tests/drivers/pwm/pwm_gpio_loopback/boards/bl54l15_dvk_nrf54l15_cpuapp.conf b/tests/drivers/pwm/pwm_gpio_loopback/boards/bl54l15_dvk_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..e5f1bcc335c
--- /dev/null
+++ b/tests/drivers/pwm/pwm_gpio_loopback/boards/bl54l15_dvk_nrf54l15_cpuapp.conf
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SKIP_EDGE_NUM=4
diff --git a/tests/drivers/pwm/pwm_gpio_loopback/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/pwm/pwm_gpio_loopback/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..cab982c9534
--- /dev/null
+++ b/tests/drivers/pwm/pwm_gpio_loopback/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Test requires jumper between:
+ *  - PWM20 OUT[0] at P1.10 <-> GPIO input at P1.11
+ */
+
+/ {
+	zephyr,user {
+		pwms = <&pwm20 0 160000 PWM_POLARITY_NORMAL>;
+		gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+	};
+};
diff --git a/tests/drivers/pwm/pwm_gpio_loopback/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf b/tests/drivers/pwm/pwm_gpio_loopback/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..e5f1bcc335c
--- /dev/null
+++ b/tests/drivers/pwm/pwm_gpio_loopback/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf
@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SKIP_EDGE_NUM=4
diff --git a/tests/drivers/pwm/pwm_gpio_loopback/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/pwm/pwm_gpio_loopback/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..cab982c9534
--- /dev/null
+++ b/tests/drivers/pwm/pwm_gpio_loopback/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Test requires jumper between:
+ *  - PWM20 OUT[0] at P1.10 <-> GPIO input at P1.11
+ */
+
+/ {
+	zephyr,user {
+		pwms = <&pwm20 0 160000 PWM_POLARITY_NORMAL>;
+		gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+	};
+};
diff --git a/tests/drivers/pwm/pwm_gpio_loopback/boards/ophelia4ev_nrf54l15_cpuapp.conf b/tests/drivers/pwm/pwm_gpio_loopback/boards/ophelia4ev_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..795414a504a
--- /dev/null
+++ b/tests/drivers/pwm/pwm_gpio_loopback/boards/ophelia4ev_nrf54l15_cpuapp.conf
@@ -0,0 +1 @@
+CONFIG_SKIP_EDGE_NUM=4
diff --git a/tests/drivers/pwm/pwm_gpio_loopback/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/pwm/pwm_gpio_loopback/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..4d4e96aeacb
--- /dev/null
+++ b/tests/drivers/pwm/pwm_gpio_loopback/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Test requires jumper between:
+ *  - PWM20 OUT[0] at P1.10 <-> GPIO input at P1.11
+ */
+
+/ {
+	zephyr,user {
+		pwms = <&pwm20 0 160000 PWM_POLARITY_NORMAL>;
+		gpios = <&gpio1 11 GPIO_ACTIVE_HIGH>;
+	};
+};
diff --git a/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32_procpu.overlay b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32_procpu.overlay
index 7901b44125c..0f727fe87e7 100644
--- a/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32_procpu.overlay
+++ b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32_procpu.overlay
@@ -1,7 +1,7 @@
 /*
  * SPDX-License-Identifier: Apache-2.0
  *
- * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * Copyright (c) 2025 Espressif Systems (Shanghai) Co., Ltd.
  */
 
 #include <zephyr/dt-bindings/pwm/pwm.h>
@@ -12,10 +12,14 @@
 	zephyr,user {
 		/* GPIO input pins order must match PWM pinctrl config */
 		gpios = <&gpio0 2 ESP32_GPIO_PIN_OUT_EN>,
-			<&gpio0 3 ESP32_GPIO_PIN_OUT_EN>;
+			<&gpio0 3 ESP32_GPIO_PIN_OUT_EN>,
+			<&gpio0 4 ESP32_GPIO_PIN_OUT_EN>,
+			<&gpio0 5 ESP32_GPIO_PIN_OUT_EN>;
 
 		pwms = <&ledc0 0 160000 PWM_POLARITY_NORMAL>,
-			<&ledc0 5 80000 PWM_POLARITY_INVERTED>;
+			<&ledc0 5 80000 PWM_POLARITY_INVERTED>,
+			<&ledc0 9 1000000 PWM_POLARITY_NORMAL>,
+			<&ledc0 10 1000000 PWM_POLARITY_INVERTED>;
 	};
 };
 
@@ -23,7 +27,9 @@
 	ledc0_default: ledc0_default {
 		group1 {
 			pinmux = <LEDC_CH0_GPIO2>,
-				<LEDC_CH5_GPIO3>;
+				<LEDC_CH5_GPIO3>,
+				<LEDC_CH9_GPIO4>,
+				<LEDC_CH10_GPIO5>;
 			input-enable;
 		};
 	};
@@ -45,4 +51,16 @@
 		reg = <0x5>;
 		timer = <1>;
 	};
+
+	/* HS channel */
+	channel9@9 {
+		reg = <0x9>;
+		timer = <0>;
+	};
+
+	/* share same timer with ch9 */
+	channel10@a {
+		reg = <0xa>;
+		timer = <0>;
+	};
 };
diff --git a/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c6.overlay b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c3_usb.overlay
similarity index 100%
rename from tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c6.overlay
rename to tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c3_usb.overlay
diff --git a/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c6_hpcore.overlay b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c6_hpcore.overlay
new file mode 100644
index 00000000000..7901b44125c
--- /dev/null
+++ b/tests/drivers/pwm/pwm_gpio_loopback/socs/esp32c6_hpcore.overlay
@@ -0,0 +1,48 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ */
+
+#include <zephyr/dt-bindings/pwm/pwm.h>
+#include <zephyr/dt-bindings/gpio/gpio.h>
+#include <zephyr/dt-bindings/gpio/espressif-esp32-gpio.h>
+
+/ {
+	zephyr,user {
+		/* GPIO input pins order must match PWM pinctrl config */
+		gpios = <&gpio0 2 ESP32_GPIO_PIN_OUT_EN>,
+			<&gpio0 3 ESP32_GPIO_PIN_OUT_EN>;
+
+		pwms = <&ledc0 0 160000 PWM_POLARITY_NORMAL>,
+			<&ledc0 5 80000 PWM_POLARITY_INVERTED>;
+	};
+};
+
+&pinctrl {
+	ledc0_default: ledc0_default {
+		group1 {
+			pinmux = <LEDC_CH0_GPIO2>,
+				<LEDC_CH5_GPIO3>;
+			input-enable;
+		};
+	};
+};
+
+&ledc0 {
+	pinctrl-0 = <&ledc0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	channel0@0 {
+		reg = <0x0>;
+		timer = <0>;
+	};
+
+	channel5@5 {
+		reg = <0x5>;
+		timer = <1>;
+	};
+};
diff --git a/tests/drivers/pwm/pwm_gpio_loopback/testcase.yaml b/tests/drivers/pwm/pwm_gpio_loopback/testcase.yaml
index 1cc0dd5b797..52a98cb14b0 100644
--- a/tests/drivers/pwm/pwm_gpio_loopback/testcase.yaml
+++ b/tests/drivers/pwm/pwm_gpio_loopback/testcase.yaml
@@ -12,7 +12,7 @@ tests:
       - esp32_devkitc_wrover/esp32/procpu
       - esp8684_devkitm
       - esp32c3_devkitm
-      - esp32c6_devkitc
+      - esp32c6_devkitc/esp32c6/hpcore
       - esp32s2_saola
       - esp32s3_devkitm/esp32s3/procpu
 
@@ -20,3 +20,4 @@ tests:
     platform_allow:
       - nrf54h20dk/nrf54h20/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
diff --git a/tests/drivers/pwm/pwm_loopback/boards/arduino_uno_r4.overlay b/tests/drivers/pwm/pwm_loopback/boards/arduino_uno_r4.overlay
new file mode 100644
index 00000000000..23b8bea7e5c
--- /dev/null
+++ b/tests/drivers/pwm/pwm_loopback/boards/arduino_uno_r4.overlay
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pwm/pwm.h>
+#include <zephyr/dt-bindings/pwm/ra_pwm.h>
+
+/ {
+	pwm_loopback_0 {
+		compatible = "test-pwm-loopback";
+		/* first index must be a 32-Bit timer */
+		pwms = <&pwm0 0 0 PWM_POLARITY_NORMAL>,
+			<&pwm7 0 0 PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pinctrl {
+	pwm0_default: pwm0_default {
+		group1 {
+			/* GTIOC0A */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 7)>;
+		};
+	};
+};
+
+&pwm0 {
+	pinctrl-0 = <&pwm0_default>;
+	pinctrl-names = "default";
+	interrupts = <30 1>, <31 1>;
+	interrupt-names = "gtioca", "overflow";
+	status = "okay";
+};
diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra4l1.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4l1.overlay
new file mode 100644
index 00000000000..4c16fb97390
--- /dev/null
+++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4l1.overlay
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pwm/pwm.h>
+#include <zephyr/dt-bindings/pwm/ra_pwm.h>
+
+/ {
+	pwm_loopback_0 {
+		compatible = "test-pwm-loopback";
+		/* first index must be a 32-Bit timer */
+		pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>,
+			<&pwm4 0 0 PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pinctrl {
+	pwm4_default: pwm4_default {
+		group1 {
+			/* GTIOC4A*/
+			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 15)>;
+		};
+	};
+};
+
+&pwm4 {
+	pinctrl-0 = <&pwm4_default>;
+	pinctrl-names = "default";
+	interrupts = <63 1>, <62 1>;
+	interrupt-names = "gtioca", "overflow";
+	status = "okay";
+};
diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra4m1.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4m1.overlay
new file mode 100644
index 00000000000..556410c2aef
--- /dev/null
+++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra4m1.overlay
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pwm/pwm.h>
+#include <zephyr/dt-bindings/pwm/ra_pwm.h>
+
+/ {
+	pwm_loopback_0 {
+		compatible = "test-pwm-loopback";
+		/* first index must be a 32-Bit timer */
+		pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>,
+			<&pwm3 0 0 PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pinctrl {
+	pwm3_default: pwm3_default {
+		group1 {
+			/* GTIOC3A */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 11)>;
+		};
+	};
+};
+
+&pwm3 {
+	pinctrl-0 = <&pwm3_default>;
+	pinctrl-names = "default";
+	interrupts = <30 1>, <31 1>;
+	interrupt-names = "gtioca", "overflow";
+	status = "okay";
+};
diff --git a/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m3.overlay b/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m3.overlay
index 077b7bdd406..bb7ed90c9e0 100644
--- a/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m3.overlay
+++ b/tests/drivers/pwm/pwm_loopback/boards/ek_ra6m3.overlay
@@ -11,7 +11,7 @@
 	pwm_loopback_0 {
 		compatible = "test-pwm-loopback";
 		/* first index must be a 32-Bit timer */
-		pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>,
+		pwms = <&pwm0 0 0 PWM_POLARITY_NORMAL>,
 			<&pwm4 0 0 PWM_POLARITY_NORMAL>;
 	};
 };
diff --git a/tests/drivers/pwm/pwm_loopback/boards/fpb_ra4e1.overlay b/tests/drivers/pwm/pwm_loopback/boards/fpb_ra4e1.overlay
new file mode 100644
index 00000000000..007bd811c0d
--- /dev/null
+++ b/tests/drivers/pwm/pwm_loopback/boards/fpb_ra4e1.overlay
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pwm/pwm.h>
+#include <zephyr/dt-bindings/pwm/ra_pwm.h>
+
+/ {
+	pwm_loopback_0 {
+		compatible = "test-pwm-loopback";
+		/* first index must be a 32-Bit timer */
+		pwms = <&pwm1 0 0 PWM_POLARITY_NORMAL>,
+			<&pwm4 0 0 PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pinctrl {
+	pwm4_default: pwm4_default {
+		group1 {
+			/* GTIOC4A*/
+			psels = <RA_PSEL(RA_PSEL_GPT1, 3, 2)>;
+		};
+	};
+};
+
+&pwm4 {
+	pinctrl-0 = <&pwm4_default>;
+	pinctrl-names = "default";
+	interrupts = <65 1>, <66 1>;
+	interrupt-names = "gtioca", "overflow";
+	status = "okay";
+};
diff --git a/tests/drivers/pwm/pwm_loopback/boards/mr_canhubk3.overlay b/tests/drivers/pwm/pwm_loopback/boards/mr_canhubk3.overlay
index 898b6d938f7..9cbda8857fb 100644
--- a/tests/drivers/pwm/pwm_loopback/boards/mr_canhubk3.overlay
+++ b/tests/drivers/pwm/pwm_loopback/boards/mr_canhubk3.overlay
@@ -31,9 +31,6 @@
 		status = "okay";
 
 		pwm_1 {
-			/delete-property/ period;
-			/delete-property/ polarity;
-			/delete-property/ duty-cycle;
 			prescaler = <16>;
 			pwm-mode = "SAIC";
 		};
diff --git a/tests/drivers/pwm/pwm_loopback/boards/nucleo_wba52cg.overlay b/tests/drivers/pwm/pwm_loopback/boards/nucleo_wba55cg.overlay
similarity index 100%
rename from tests/drivers/pwm/pwm_loopback/boards/nucleo_wba52cg.overlay
rename to tests/drivers/pwm/pwm_loopback/boards/nucleo_wba55cg.overlay
diff --git a/tests/drivers/pwm/pwm_loopback/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay b/tests/drivers/pwm/pwm_loopback/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
new file mode 100644
index 00000000000..a0d4d238fb5
--- /dev/null
+++ b/tests/drivers/pwm/pwm_loopback/boards/rzg3s_smarc_r9a08g045s33gbg_cm33.overlay
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pwm/pwm.h>
+#include <zephyr/dt-bindings/pwm/renesas_rz_pwm.h>
+
+/ {
+	pwm_loopback_0 {
+		compatible = "test-pwm-loopback";
+		pwms = <&pwm3 RZ_PWM_GPT_IO_A 0 PWM_POLARITY_NORMAL>,
+		       <&pwm6 RZ_PWM_GPT_IO_A 0 PWM_POLARITY_NORMAL>;
+	};
+};
+
+&gpt32e3 {
+	pwm3: pwm {
+		status = "okay";
+		pinctrl-0 = <&gpt3_pins>;
+		pinctrl-names = "default";
+	};
+};
+
+&gpt32e6 {
+	pwm6: pwm {
+		status = "okay";
+		pinctrl-0 = <&gpt6_pins>;
+		pinctrl-names = "default";
+	};
+};
diff --git a/tests/drivers/pwm/pwm_loopback/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/drivers/pwm/pwm_loopback/boards/s32z2xxdc2_s32z270_rtu0.overlay
new file mode 100644
index 00000000000..2b7fa95384e
--- /dev/null
+++ b/tests/drivers/pwm/pwm_loopback/boards/s32z2xxdc2_s32z270_rtu0.overlay
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pwm/pwm.h>
+
+/ {
+	pwm_loopback_0 {
+		compatible = "test-pwm-loopback";
+		pwms = <&emios0_pwm 24 0 PWM_POLARITY_NORMAL>,
+			<&emios0_pwm 25 0 PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pinctrl {
+	emios0_default: emios0_default {
+		group0 {
+			pinmux = <PK0_EMIOS_0_CH24_O>;
+			output-enable;
+		};
+		group1 {
+			pinmux = <PJ15_EMIOS_0_CH25_I>;
+			input-enable;
+		};
+	};
+};
+
+&emios0 {
+	clock-divider = <200>;
+	status = "okay";
+
+	emios0_pwm: pwm {
+		pinctrl-0 = <&emios0_default>;
+		pinctrl-names = "default";
+		status = "okay";
+
+		pwm_24 {
+			channel = <24>;
+			prescaler = <16>;
+			pwm-mode = "OPWFMB";
+		};
+
+		pwm_25 {
+			channel = <25>;
+			pwm-mode = "SAIC";
+			prescaler = <16>;
+		};
+	};
+};
diff --git a/tests/drivers/pwm/pwm_loopback/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/drivers/pwm/pwm_loopback/boards/s32z2xxdc2_s32z270_rtu1.overlay
new file mode 100644
index 00000000000..2b7fa95384e
--- /dev/null
+++ b/tests/drivers/pwm/pwm_loopback/boards/s32z2xxdc2_s32z270_rtu1.overlay
@@ -0,0 +1,51 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pwm/pwm.h>
+
+/ {
+	pwm_loopback_0 {
+		compatible = "test-pwm-loopback";
+		pwms = <&emios0_pwm 24 0 PWM_POLARITY_NORMAL>,
+			<&emios0_pwm 25 0 PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pinctrl {
+	emios0_default: emios0_default {
+		group0 {
+			pinmux = <PK0_EMIOS_0_CH24_O>;
+			output-enable;
+		};
+		group1 {
+			pinmux = <PJ15_EMIOS_0_CH25_I>;
+			input-enable;
+		};
+	};
+};
+
+&emios0 {
+	clock-divider = <200>;
+	status = "okay";
+
+	emios0_pwm: pwm {
+		pinctrl-0 = <&emios0_default>;
+		pinctrl-names = "default";
+		status = "okay";
+
+		pwm_24 {
+			channel = <24>;
+			prescaler = <16>;
+			pwm-mode = "OPWFMB";
+		};
+
+		pwm_25 {
+			channel = <25>;
+			pwm-mode = "SAIC";
+			prescaler = <16>;
+		};
+	};
+};
diff --git a/tests/drivers/pwm/pwm_loopback/boards/voice_ra4e1.overlay b/tests/drivers/pwm/pwm_loopback/boards/voice_ra4e1.overlay
new file mode 100644
index 00000000000..c62c8793d2e
--- /dev/null
+++ b/tests/drivers/pwm/pwm_loopback/boards/voice_ra4e1.overlay
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pwm/pwm.h>
+#include <zephyr/dt-bindings/pwm/ra_pwm.h>
+
+/ {
+	pwm_loopback_0 {
+		compatible = "test-pwm-loopback";
+		/* first index must be a 32-Bit timer */
+		pwms = <&pwm2 0 0 PWM_POLARITY_NORMAL>,
+			<&pwm4 0 0 PWM_POLARITY_NORMAL>;
+	};
+};
+
+&pinctrl {
+	pwm2_default: pwm2_default {
+		group1 {
+			/* GTIOC2A GTIOC2B */
+			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 3)>,
+				<RA_PSEL(RA_PSEL_GPT1, 1, 2)>;
+		};
+	};
+
+	pwm4_default: pwm4_default {
+		group1 {
+			/* GTIOC4A*/
+			psels = <RA_PSEL(RA_PSEL_GPT1, 3, 2)>;
+		};
+	};
+};
+
+&pwm2 {
+	pinctrl-0 = <&pwm2_default>;
+	pinctrl-names = "default";
+	interrupts = <63 1>, <64 1>;
+	interrupt-names = "gtioca", "overflow";
+	status = "okay";
+};
+
+&pwm4 {
+	pinctrl-0 = <&pwm4_default>;
+	pinctrl-names = "default";
+	interrupts = <65 1>, <66 1>;
+	interrupt-names = "gtioca", "overflow";
+	status = "okay";
+};
diff --git a/tests/drivers/pwm/pwm_loopback/socs/esp32c6.overlay b/tests/drivers/pwm/pwm_loopback/socs/esp32c6_hpcore.overlay
similarity index 100%
rename from tests/drivers/pwm/pwm_loopback/socs/esp32c6.overlay
rename to tests/drivers/pwm/pwm_loopback/socs/esp32c6_hpcore.overlay
diff --git a/tests/drivers/regulator/api/src/main.c b/tests/drivers/regulator/api/src/main.c
index 3dbc0bd77ae..c5a552907ea 100644
--- a/tests/drivers/regulator/api/src/main.c
+++ b/tests/drivers/regulator/api/src/main.c
@@ -420,6 +420,81 @@ ZTEST(regulator_api, test_get_voltage_error)
 	zassert_equal(regulator_fake_get_voltage_fake.arg1_val, NULL);
 }
 
+ZTEST(regulator_api, test_count_current_limits_not_implemented)
+{
+	unsigned int ret = regulator_count_current_limits(dummy_reg);
+
+	zassert_equal(ret, 0);
+}
+
+ZTEST(regulator_api, test_count_current_limits_ok)
+{
+	RESET_FAKE(regulator_fake_count_current_limits);
+
+	regulator_fake_count_current_limits_fake.return_val = 10;
+
+	zassert_equal(regulator_count_current_limits(reg0), 10U);
+	zassert_equal(regulator_fake_count_current_limits_fake.arg0_val, reg0);
+	zassert_equal(regulator_fake_count_current_limits_fake.call_count, 1U);
+}
+
+ZTEST(regulator_api, test_count_current_limits_fail)
+{
+	RESET_FAKE(regulator_fake_count_current_limits);
+
+	regulator_fake_count_current_limits_fake.return_val = -EINVAL;
+
+	zassert_equal(regulator_count_current_limits(reg0), -EINVAL);
+	zassert_equal(regulator_fake_count_current_limits_fake.arg0_val, reg0);
+	zassert_equal(regulator_fake_count_current_limits_fake.call_count, 1U);
+}
+
+ZTEST(regulator_api, test_list_current_limit_not_implemented)
+{
+	zassert_equal(regulator_list_current_limit(dummy_reg, 0, NULL), -EINVAL);
+}
+
+static int list_current_limit_ok(const struct device *dev, unsigned int idx, int32_t *curr_ua)
+{
+	ARG_UNUSED(dev);
+	ARG_UNUSED(idx);
+
+	*curr_ua = 100;
+
+	return 0;
+}
+
+ZTEST(regulator_api, test_list_current_limit_ok)
+{
+	RESET_FAKE(regulator_fake_list_current_limit);
+
+	int32_t curr_ua;
+
+	regulator_fake_list_current_limit_fake.custom_fake = list_current_limit_ok;
+
+	zassert_equal(regulator_list_current_limit(reg0, 1, &curr_ua), 0);
+	zassert_equal(curr_ua, 100);
+	zassert_equal(regulator_fake_list_current_limit_fake.arg0_val, reg0);
+	zassert_equal(regulator_fake_list_current_limit_fake.arg1_val, 1U);
+	zassert_equal(regulator_fake_list_current_limit_fake.arg2_val, &curr_ua);
+	zassert_equal(regulator_fake_list_current_limit_fake.call_count, 1U);
+}
+
+ZTEST(regulator_api, test_list_current_limit_fail)
+{
+	RESET_FAKE(regulator_fake_list_current_limit);
+
+	int32_t curr_ua;
+
+	regulator_fake_list_current_limit_fake.return_val = -EIO;
+
+	zassert_equal(regulator_list_current_limit(reg0, 1, &curr_ua), -EIO);
+	zassert_equal(regulator_fake_list_current_limit_fake.arg0_val, reg0);
+	zassert_equal(regulator_fake_list_current_limit_fake.arg1_val, 1U);
+	zassert_equal(regulator_fake_list_current_limit_fake.arg2_val, &curr_ua);
+	zassert_equal(regulator_fake_list_current_limit_fake.call_count, 1U);
+}
+
 ZTEST(regulator_api, test_set_current_limit_not_implemented)
 {
 	int ret = regulator_set_current_limit(dummy_reg, 0, 0);
diff --git a/tests/drivers/regulator/voltage/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/tests/drivers/regulator/voltage/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..448b2bed143
--- /dev/null
+++ b/tests/drivers/regulator/voltage/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2024-2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+#include <zephyr/dt-bindings/regulator/nxp_vref.h>
+
+/* To do this test, connect LPADC0 channel 2A(J20 pin 28) to VREF_OUT (JP28-1) */
+
+/ {
+	resources: resources {
+		compatible = "test-regulator-voltage";
+		regulators = <&vref>;
+		tolerance-microvolt = <10000>;
+		set-read-delay-ms = <1>;
+		adc-avg-count = <10>;
+		io-channels = <&lpadc0 0>;
+		min-microvolt = <1000000>;
+		max-microvolt = <2100000>;
+	};
+};
+
+&vref {
+	regulator-initial-mode = <NXP_VREF_MODE_INTERNAL_REGULATOR>;
+};
+
+&lpadc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/* In this case, the LPADC reference source cannot be set to VREFO,
+	 * switch the reference source to VDD_ANA.
+	 */
+	voltage-ref= <2>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,vref-mv = <3300>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <MCUX_LPADC_CH2A>;
+	};
+};
diff --git a/tests/drivers/regulator/voltage/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay b/tests/drivers/regulator/voltage/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay
new file mode 100644
index 00000000000..448b2bed143
--- /dev/null
+++ b/tests/drivers/regulator/voltage/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2024-2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/adc/adc.h>
+#include <zephyr/dt-bindings/adc/mcux-lpadc.h>
+#include <zephyr/dt-bindings/regulator/nxp_vref.h>
+
+/* To do this test, connect LPADC0 channel 2A(J20 pin 28) to VREF_OUT (JP28-1) */
+
+/ {
+	resources: resources {
+		compatible = "test-regulator-voltage";
+		regulators = <&vref>;
+		tolerance-microvolt = <10000>;
+		set-read-delay-ms = <1>;
+		adc-avg-count = <10>;
+		io-channels = <&lpadc0 0>;
+		min-microvolt = <1000000>;
+		max-microvolt = <2100000>;
+	};
+};
+
+&vref {
+	regulator-initial-mode = <NXP_VREF_MODE_INTERNAL_REGULATOR>;
+};
+
+&lpadc0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	/* In this case, the LPADC reference source cannot be set to VREFO,
+	 * switch the reference source to VDD_ANA.
+	 */
+	voltage-ref= <2>;
+
+	channel@0 {
+		reg = <0>;
+		zephyr,gain = "ADC_GAIN_1";
+		zephyr,reference = "ADC_REF_EXTERNAL0";
+		zephyr,vref-mv = <3300>;
+		zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
+		zephyr,resolution = <12>;
+		zephyr,input-positive = <MCUX_LPADC_CH2A>;
+	};
+};
diff --git a/tests/drivers/regulator/voltage/src/main.c b/tests/drivers/regulator/voltage/src/main.c
index 3978022130c..e20ab1e2afb 100644
--- a/tests/drivers/regulator/voltage/src/main.c
+++ b/tests/drivers/regulator/voltage/src/main.c
@@ -10,14 +10,11 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/ztest.h>
 
-#define REG_INIT(node_id, prop, idx) \
-	DEVICE_DT_GET(DT_PHANDLE_BY_IDX(node_id, prop, idx)),
-
 #define ADC_INIT(node_id, prop, idx) \
 	ADC_DT_SPEC_GET_BY_IDX(node_id, idx),
 
 static const struct device *regs[] = {
-	DT_FOREACH_PROP_ELEM(DT_NODELABEL(resources), regulators, REG_INIT)
+	DT_FOREACH_PROP_ELEM_SEP(DT_NODELABEL(resources), regulators, DEVICE_DT_GET_BY_IDX, (,))
 };
 
 static const struct adc_dt_spec adc_chs[] = {
diff --git a/tests/drivers/regulator/voltage/testcase.yaml b/tests/drivers/regulator/voltage/testcase.yaml
index f441a8219e1..04befd07e02 100644
--- a/tests/drivers/regulator/voltage/testcase.yaml
+++ b/tests/drivers/regulator/voltage/testcase.yaml
@@ -20,6 +20,7 @@ tests:
       - mimxrt685_evk/mimxrt685s/cm33
       - lpcxpresso55s36
       - frdm_mcxn947/mcxn947/cpu0
+      - mcx_n9xx_evk/mcxn947/cpu0
     harness_config:
       fixture: gpio_loopback
   drivers.regulator.voltage.rpi_pico_vreg:
diff --git a/tests/drivers/reset/mmio/CMakeLists.txt b/tests/drivers/reset/mmio/CMakeLists.txt
new file mode 100644
index 00000000000..b012e9582d3
--- /dev/null
+++ b/tests/drivers/reset/mmio/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+
+project(reset_mmio)
+
+target_sources(app PRIVATE src/main.c)
diff --git a/tests/drivers/reset/mmio/boards/qemu_cortex_m3.overlay b/tests/drivers/reset/mmio/boards/qemu_cortex_m3.overlay
new file mode 100644
index 00000000000..04be3315bd2
--- /dev/null
+++ b/tests/drivers/reset/mmio/boards/qemu_cortex_m3.overlay
@@ -0,0 +1,14 @@
+/ {
+	reset0: reset@20000004 {
+		compatible = "reset-mmio";
+		reg = <0x20000004 0x4>;
+		num-resets = <16>;
+	};
+
+	reset1: reset@20000008 {
+		compatible = "reset-mmio";
+		reg = <0x20000008 0x4>;
+		num-resets = <16>;
+		active-low;
+	};
+};
diff --git a/tests/drivers/reset/mmio/prj.conf b/tests/drivers/reset/mmio/prj.conf
new file mode 100644
index 00000000000..4a544c4c662
--- /dev/null
+++ b/tests/drivers/reset/mmio/prj.conf
@@ -0,0 +1,3 @@
+CONFIG_ZTEST=y
+CONFIG_RESET=y
+CONFIG_RESET_MMIO=y
diff --git a/tests/drivers/reset/mmio/src/main.c b/tests/drivers/reset/mmio/src/main.c
new file mode 100644
index 00000000000..29df00f0abf
--- /dev/null
+++ b/tests/drivers/reset/mmio/src/main.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2025 Google LLC.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/device.h>
+#include <zephyr/drivers/reset.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(reset_mmio_tests, NULL, NULL, NULL, NULL, NULL);
+
+#define RESET_MAX_NUM 16
+
+void check_status(const struct device *dev, uint32_t base, uint32_t id, bool expected_state,
+		  bool active_low)
+{
+	uint8_t actual_state;
+
+	zassert_ok(reset_status(dev, id, &actual_state), "Failed getting reset state");
+	zassert_equal(actual_state, expected_state,
+		      "reset state %u doesn't match expected state %u", actual_state,
+		      expected_state);
+	zassert_equal(FIELD_GET(BIT(id), sys_read32(base)), active_low ^ expected_state);
+}
+
+/* Tests that the reset driver assert functionality is correct for active
+ * low devices.
+ */
+ZTEST(reset_mmio_tests, test_reset_mmio_assert_active_low)
+{
+	const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(reset1));
+	uint32_t base = DT_REG_ADDR(DT_NODELABEL(reset1));
+	bool active_low = true;
+	uint8_t i;
+
+	for (i = 0; i < RESET_MAX_NUM; i++) {
+		reset_line_deassert(dev, i);
+		check_status(dev, base, i, false, active_low);
+		/* Check idempotency */
+		reset_line_deassert(dev, i);
+		check_status(dev, base, i, false, active_low);
+
+		/* Check ressserting resets */
+		reset_line_assert(dev, i);
+		check_status(dev, base, i, true, active_low);
+		/* Check idempotency */
+		reset_line_assert(dev, i);
+		check_status(dev, base, i, true, active_low);
+	}
+}
+
+/* Tests that the reset driver assert functionality is correct for active
+ * high devices.
+ */
+ZTEST(reset_mmio_tests, test_reset_mmio_assert_active_high)
+{
+	const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(reset0));
+	uint32_t base = DT_REG_ADDR(DT_NODELABEL(reset0));
+	bool active_low = false;
+	uint8_t i;
+
+	for (i = 0; i < RESET_MAX_NUM; i++) {
+		reset_line_deassert(dev, i);
+		check_status(dev, base, i, false, active_low);
+		/* Check idempotency */
+		reset_line_deassert(dev, i);
+		check_status(dev, base, i, false, active_low);
+
+		/* Check ressserting resets */
+		reset_line_assert(dev, i);
+		check_status(dev, base, i, true, active_low);
+		/* Check idempotency */
+		reset_line_assert(dev, i);
+		check_status(dev, base, i, true, active_low);
+	}
+}
+
+/* Tests that the reset driver toggle functionality is correct for active
+ * low devices
+ */
+ZTEST(reset_mmio_tests, test_reset_mmio_toggle_active_low)
+{
+	const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(reset1));
+	uint32_t base = DT_REG_ADDR(DT_NODELABEL(reset1));
+	bool active_low = true;
+	uint8_t i;
+
+	for (i = 0; i < RESET_MAX_NUM; i++) {
+		/* Begin by making sure the reset is asserted */
+		reset_line_assert(dev, i);
+		check_status(dev, base, i, true, active_low);
+		reset_line_toggle(dev, i);
+		check_status(dev, base, i, false, active_low);
+		reset_line_toggle(dev, i);
+		check_status(dev, base, i, true, active_low);
+	}
+}
+
+/* Tests that the reset driver toggle functionality is correct for active
+ * high devices
+ */
+ZTEST(reset_mmio_tests, test_reset_mmio_toggle_active_high)
+{
+	const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(reset0));
+	uint32_t base = DT_REG_ADDR(DT_NODELABEL(reset0));
+	bool active_low = false;
+	uint8_t i;
+
+	for (i = 0; i < RESET_MAX_NUM; i++) {
+		/* Begin by making sure the reset is asserted */
+		reset_line_assert(dev, i);
+		check_status(dev, base, i, true, active_low);
+		reset_line_toggle(dev, i);
+		check_status(dev, base, i, false, active_low);
+		reset_line_toggle(dev, i);
+		check_status(dev, base, i, true, active_low);
+	}
+}
+
+/* Tests that the reset driver rejects out of bounds bits */
+ZTEST(reset_mmio_tests, test_reset_mmio_oob)
+{
+	const struct device *dev = DEVICE_DT_GET(DT_NODELABEL(reset0));
+	uint8_t i, status;
+
+	for (i = RESET_MAX_NUM; i < 32; i++) {
+		zassert_not_ok(reset_line_assert(dev, i));
+		zassert_not_ok(reset_line_deassert(dev, i));
+		zassert_not_ok(reset_status(dev, i, &status));
+		zassert_not_ok(reset_line_toggle(dev, i));
+	}
+}
diff --git a/tests/drivers/reset/mmio/testcase.yaml b/tests/drivers/reset/mmio/testcase.yaml
new file mode 100644
index 00000000000..6dbc4de530a
--- /dev/null
+++ b/tests/drivers/reset/mmio/testcase.yaml
@@ -0,0 +1,7 @@
+# Copyright (c) 2025 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+tests:
+  drivers.reset.mmio:
+    platform_allow:
+      - qemu_cortex_m3
diff --git a/tests/drivers/retained_mem/api/boards/bl54l15_dvk_nrf54l10_cpuapp.conf b/tests/drivers/retained_mem/api/boards/bl54l15_dvk_nrf54l10_cpuapp.conf
new file mode 100644
index 00000000000..3c6c4c767ea
--- /dev/null
+++ b/tests/drivers/retained_mem/api/boards/bl54l15_dvk_nrf54l10_cpuapp.conf
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_POWEROFF=y
diff --git a/tests/drivers/retained_mem/api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay b/tests/drivers/retained_mem/api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay
new file mode 100644
index 00000000000..2dfaf919e1c
--- /dev/null
+++ b/tests/drivers/retained_mem/api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay
@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	cpuapp_sram@2002f000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x2002f000 DT_SIZE_K(4)>;
+		zephyr,memory-region = "RetainedMem";
+		status = "okay";
+
+		retainedmem0: retainedmem {
+			compatible = "zephyr,retained-ram";
+			status = "okay";
+		};
+	};
+
+	aliases {
+		retainedmemtestdevice = &retainedmem0;
+	};
+};
+
+&cpuapp_sram {
+	/* Shrink SRAM size to avoid overlap with retained memory region:
+	 * 192 - 4 = 188KB = 0x2f000
+	 */
+	reg = <0x20000000 0x2f000>;
+	ranges = <0x0 0x20000000 0x2f000>;
+};
diff --git a/tests/drivers/retained_mem/api/boards/bl54l15_dvk_nrf54l15_cpuapp.conf b/tests/drivers/retained_mem/api/boards/bl54l15_dvk_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..3c6c4c767ea
--- /dev/null
+++ b/tests/drivers/retained_mem/api/boards/bl54l15_dvk_nrf54l15_cpuapp.conf
@@ -0,0 +1,6 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_POWEROFF=y
diff --git a/tests/drivers/retained_mem/api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/retained_mem/api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..ac310c49f65
--- /dev/null
+++ b/tests/drivers/retained_mem/api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	cpuapp_sram@2002e000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x2002e000 DT_SIZE_K(4)>;
+		zephyr,memory-region = "RetainedMem";
+		status = "okay";
+
+		retainedmem0: retainedmem {
+			compatible = "zephyr,retained-ram";
+			status = "okay";
+		};
+	};
+
+	aliases {
+		retainedmemtestdevice = &retainedmem0;
+	};
+};
+
+&cpuapp_sram {
+	reg = <0x20000000 DT_SIZE_K(184)>;
+	ranges = <0x0 0x20000000 0x2e000>;
+};
diff --git a/tests/drivers/retained_mem/api/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf b/tests/drivers/retained_mem/api/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..55bfed5d042
--- /dev/null
+++ b/tests/drivers/retained_mem/api/boards/bl54l15u_dvk_nrf54l15_cpuapp.conf
@@ -0,0 +1,8 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# Copyright (c) 2025 Ezurio LLC
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_POWEROFF=y
diff --git a/tests/drivers/retained_mem/api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/retained_mem/api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..ac310c49f65
--- /dev/null
+++ b/tests/drivers/retained_mem/api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	cpuapp_sram@2002e000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x2002e000 DT_SIZE_K(4)>;
+		zephyr,memory-region = "RetainedMem";
+		status = "okay";
+
+		retainedmem0: retainedmem {
+			compatible = "zephyr,retained-ram";
+			status = "okay";
+		};
+	};
+
+	aliases {
+		retainedmemtestdevice = &retainedmem0;
+	};
+};
+
+&cpuapp_sram {
+	reg = <0x20000000 DT_SIZE_K(184)>;
+	ranges = <0x0 0x20000000 0x2e000>;
+};
diff --git a/tests/drivers/retained_mem/api/boards/ophelia4ev_nrf54l15_cpuapp.conf b/tests/drivers/retained_mem/api/boards/ophelia4ev_nrf54l15_cpuapp.conf
new file mode 100644
index 00000000000..c15ba3ed96d
--- /dev/null
+++ b/tests/drivers/retained_mem/api/boards/ophelia4ev_nrf54l15_cpuapp.conf
@@ -0,0 +1 @@
+CONFIG_POWEROFF=y
diff --git a/tests/drivers/retained_mem/api/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/retained_mem/api/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..e304ecbbfb1
--- /dev/null
+++ b/tests/drivers/retained_mem/api/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,22 @@
+/ {
+	cpuapp_sram@2002e000 {
+		compatible = "zephyr,memory-region", "mmio-sram";
+		reg = <0x2002e000 DT_SIZE_K(4)>;
+		zephyr,memory-region = "RetainedMem";
+		status = "okay";
+
+		retainedmem0: retainedmem {
+			compatible = "zephyr,retained-ram";
+			status = "okay";
+		};
+	};
+
+	aliases {
+		retainedmemtestdevice = &retainedmem0;
+	};
+};
+
+&cpuapp_sram {
+	reg = <0x20000000 DT_SIZE_K(184)>;
+	ranges = <0x0 0x20000000 0x2e000>;
+};
diff --git a/tests/drivers/retained_mem/api/testcase.yaml b/tests/drivers/retained_mem/api/testcase.yaml
index 2ad60f6e3b4..7852742241b 100644
--- a/tests/drivers/retained_mem/api/testcase.yaml
+++ b/tests/drivers/retained_mem/api/testcase.yaml
@@ -15,6 +15,7 @@ tests:
       - nrf54l15dk/nrf54l10/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - qemu_cortex_m3
     tags:
diff --git a/tests/drivers/rtc/rtc_api/boards/nucleo_wba52cg.conf b/tests/drivers/rtc/rtc_api/boards/nucleo_wba52cg.conf
deleted file mode 100644
index 8c6c114ee41..00000000000
--- a/tests/drivers/rtc/rtc_api/boards/nucleo_wba52cg.conf
+++ /dev/null
@@ -1,2 +0,0 @@
-CONFIG_RTC_CALIBRATION=y
-CONFIG_RTC_ALARM=y
diff --git a/tests/drivers/rtc/rtc_api/boards/nucleo_wba52cg.overlay b/tests/drivers/rtc/rtc_api/boards/nucleo_wba52cg.overlay
deleted file mode 100644
index bd861fccf42..00000000000
--- a/tests/drivers/rtc/rtc_api/boards/nucleo_wba52cg.overlay
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2024 STMicroelectronics
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
-	aliases {
-		rtc = &rtc;
-	};
-};
diff --git a/tests/drivers/rtc/rtc_api/boards/rts5912_evb.overlay b/tests/drivers/rtc/rtc_api/boards/rts5912_evb.overlay
new file mode 100644
index 00000000000..bc5619eddec
--- /dev/null
+++ b/tests/drivers/rtc/rtc_api/boards/rts5912_evb.overlay
@@ -0,0 +1,16 @@
+/*
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Copyright (c) 2025 Realtek Semiconductor Corporation, SIBG-SD7
+ *
+ */
+
+/ {
+	aliases {
+		rtc = &rtc;
+	};
+};
+
+&rtc {
+	status = "okay";
+};
diff --git a/tests/drivers/rtc/rtc_api/boards/samc21n_xpro.conf b/tests/drivers/rtc/rtc_api/boards/samc21n_xpro.conf
new file mode 100644
index 00000000000..80e21536ba3
--- /dev/null
+++ b/tests/drivers/rtc/rtc_api/boards/samc21n_xpro.conf
@@ -0,0 +1,3 @@
+CONFIG_RTC_ALARM=y
+CONFIG_TEST_RTC_ALARM_TIME_MASK=63
+CONFIG_RTC_CALIBRATION=y
diff --git a/tests/drivers/rtc/rtc_api/boards/samd20_xpro.conf b/tests/drivers/rtc/rtc_api/boards/samd20_xpro.conf
new file mode 100644
index 00000000000..80e21536ba3
--- /dev/null
+++ b/tests/drivers/rtc/rtc_api/boards/samd20_xpro.conf
@@ -0,0 +1,3 @@
+CONFIG_RTC_ALARM=y
+CONFIG_TEST_RTC_ALARM_TIME_MASK=63
+CONFIG_RTC_CALIBRATION=y
diff --git a/tests/drivers/rtc/rtc_api/boards/same54_xpro.conf b/tests/drivers/rtc/rtc_api/boards/same54_xpro.conf
new file mode 100644
index 00000000000..80e21536ba3
--- /dev/null
+++ b/tests/drivers/rtc/rtc_api/boards/same54_xpro.conf
@@ -0,0 +1,3 @@
+CONFIG_RTC_ALARM=y
+CONFIG_TEST_RTC_ALARM_TIME_MASK=63
+CONFIG_RTC_CALIBRATION=y
diff --git a/tests/drivers/rtc/rtc_api/boards/saml21_xpro.conf b/tests/drivers/rtc/rtc_api/boards/saml21_xpro.conf
new file mode 100644
index 00000000000..80e21536ba3
--- /dev/null
+++ b/tests/drivers/rtc/rtc_api/boards/saml21_xpro.conf
@@ -0,0 +1,3 @@
+CONFIG_RTC_ALARM=y
+CONFIG_TEST_RTC_ALARM_TIME_MASK=63
+CONFIG_RTC_CALIBRATION=y
diff --git a/tests/drivers/rtc/rtc_api/boards/samr21_xpro.conf b/tests/drivers/rtc/rtc_api/boards/samr21_xpro.conf
new file mode 100644
index 00000000000..80e21536ba3
--- /dev/null
+++ b/tests/drivers/rtc/rtc_api/boards/samr21_xpro.conf
@@ -0,0 +1,3 @@
+CONFIG_RTC_ALARM=y
+CONFIG_TEST_RTC_ALARM_TIME_MASK=63
+CONFIG_RTC_CALIBRATION=y
diff --git a/tests/drivers/rtc/rtc_api/src/test_update_callback.c b/tests/drivers/rtc/rtc_api/src/test_update_callback.c
index 2767ebfde38..d04b1466801 100644
--- a/tests/drivers/rtc/rtc_api/src/test_update_callback.c
+++ b/tests/drivers/rtc/rtc_api/src/test_update_callback.c
@@ -73,4 +73,6 @@ ZTEST(rtc_api, test_update_callback)
 	zassert_true(counter < 12 && counter > 8, "Invalid update callback called counter");
 
 	zassert_equal(address, ((void *)&test_user_data), "Incorrect user data");
+	zassert_ok(rtc_update_set_callback(rtc, NULL, NULL),
+	    "Failed to clear and disable update callback");
 }
diff --git a/tests/drivers/sensor/adltc2990/src/main.c b/tests/drivers/sensor/adltc2990/src/main.c
index 0baaf2817c8..8dcd9b9fabf 100644
--- a/tests/drivers/sensor/adltc2990/src/main.c
+++ b/tests/drivers/sensor/adltc2990/src/main.c
@@ -6,11 +6,12 @@
 #include <zephyr/devicetree.h>
 #include <zephyr/drivers/emul.h>
 #include <zephyr/drivers/sensor.h>
+#include <zephyr/drivers/sensor/adltc2990.h>
 #include <zephyr/ztest.h>
 
-#include "adltc2990.h"
 #include "adltc2990_emul.h"
 #include "adltc2990_reg.h"
+#include "adltc2990_internal.h"
 
 /* Colllection of common assertion macros */
 #define CHECK_SINGLE_ENDED_VOLTAGE(sensor_val, index, pin_voltage, r1, r2)                         \
@@ -384,12 +385,16 @@ ZTEST_F(adltc2990_7_3, test_available_channels)
 ZTEST_F(adltc2990_7_3, test_is_device_busy)
 {
 	uint8_t is_busy = BIT(0);
+	bool result;
 
 	adltc2990_emul_set_reg(fixture->target, ADLTC2990_REG_STATUS, &is_busy);
-	zassert_equal(-EBUSY, sensor_sample_fetch_chan(fixture->dev, SENSOR_CHAN_ALL));
+	adltc2990_is_busy(fixture->dev, &result);
+	zassert_equal(1, result, "expected 1, got %d", result);
+
 	is_busy = 0;
 	adltc2990_emul_set_reg(fixture->target, ADLTC2990_REG_STATUS, &is_busy);
-	zassert_equal(0, sensor_sample_fetch_chan(fixture->dev, SENSOR_CHAN_ALL));
+	adltc2990_is_busy(fixture->dev, &result);
+	zassert_equal(0, result, "expected 0, got %d", result);
 }
 
 ZTEST_F(adltc2990_7_3, test_die_temperature)
diff --git a/tests/drivers/sensor/generic/src/main.c b/tests/drivers/sensor/generic/src/main.c
index 5bec8b45a74..e20749bd7cd 100644
--- a/tests/drivers/sensor/generic/src/main.c
+++ b/tests/drivers/sensor/generic/src/main.c
@@ -329,6 +329,10 @@ ZTEST(sensor_api, test_sensor_unit_conversion)
 	/* reset test data to positive value */
 	data.val1 = 3;
 	data.val2 = 300000;
+	zassert_equal(sensor_value_to_deci(&data), 33LL,
+			"the result does not match");
+	zassert_equal(sensor_value_to_centi(&data), 330LL,
+			"the result does not match");
 	zassert_equal(sensor_value_to_milli(&data), 3300LL,
 			"the result does not match");
 	zassert_equal(sensor_value_to_micro(&data), 3300000LL,
@@ -336,11 +340,21 @@ ZTEST(sensor_api, test_sensor_unit_conversion)
 	/* reset test data to negative value */
 	data.val1 = -data.val1;
 	data.val2 = -data.val2;
+	zassert_equal(sensor_value_to_deci(&data), -33LL,
+		"the result does not match");
+	zassert_equal(sensor_value_to_centi(&data), -330LL,
+		"the result does not match");
 	zassert_equal(sensor_value_to_milli(&data), -3300LL,
 			"the result does not match");
 	zassert_equal(sensor_value_to_micro(&data), -3300000LL,
 			"the result does not match");
 	/* Test when result is greater than 32-bit wide */
+	data.val1 = 2123456789;
+	data.val2 = 876543;
+	zassert_equal(sensor_value_to_deci(&data), 21234567898LL,
+			"the result does not match");
+	zassert_equal(sensor_value_to_centi(&data), 212345678987LL,
+			"the result does not match");
 	data.val1 = 5432109;
 	data.val2 = 876543;
 	zassert_equal(sensor_value_to_milli(&data), 5432109876LL,
diff --git a/tests/drivers/sensor/icm42688/prj.conf b/tests/drivers/sensor/icm42688/prj.conf
index 61addc37590..e62f65fa930 100644
--- a/tests/drivers/sensor/icm42688/prj.conf
+++ b/tests/drivers/sensor/icm42688/prj.conf
@@ -11,3 +11,6 @@ CONFIG_SENSOR=y
 
 # Enable emulation
 CONFIG_EMUL=y
+
+CONFIG_SENSOR_ASYNC_API=y
+CONFIG_SENSOR_CLOCK_SYSTEM=y
diff --git a/tests/drivers/sensor/temp_sensor/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/sensor/temp_sensor/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..6dc04cac94d
--- /dev/null
+++ b/tests/drivers/sensor/temp_sensor/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+temp_sensor: &temp {
+	status = "okay";
+};
diff --git a/tests/drivers/sensor/temp_sensor/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/sensor/temp_sensor/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..6dc04cac94d
--- /dev/null
+++ b/tests/drivers/sensor/temp_sensor/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+temp_sensor: &temp {
+	status = "okay";
+};
diff --git a/tests/drivers/sensor/temp_sensor/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/sensor/temp_sensor/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..435e4f4a6cc
--- /dev/null
+++ b/tests/drivers/sensor/temp_sensor/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,3 @@
+temp_sensor: &temp {
+	status = "okay";
+};
diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..46ee277dbfb
--- /dev/null
+++ b/tests/drivers/spi/spi_controller_peripheral/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	spi22_default_alt: spi22_default_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 13)>,
+				<NRF_PSEL(SPIM_MISO, 1, 11)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 9)>;
+		};
+	};
+
+	spi22_sleep_alt: spi22_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 13)>,
+				<NRF_PSEL(SPIM_MISO, 1, 11)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 9)>;
+			low-power-enable;
+		};
+	};
+
+	spi21_default_alt: spi21_default_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIS_SCK, 1, 12)>,
+				<NRF_PSEL(SPIS_MISO, 1, 10)>,
+				<NRF_PSEL(SPIS_MOSI, 1, 8)>,
+				<NRF_PSEL(SPIS_CSN, 1, 14)>;
+		};
+	};
+
+	spi21_sleep_alt: spi21_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIS_SCK, 1, 12)>,
+				<NRF_PSEL(SPIS_MISO, 1, 10)>,
+				<NRF_PSEL(SPIS_MOSI, 1, 8)>,
+				<NRF_PSEL(SPIS_CSN, 1, 14)>;
+			low-power-enable;
+		};
+	};
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&spi22 {
+	status = "okay";
+	pinctrl-0 = <&spi22_default_alt>;
+	pinctrl-1 = <&spi22_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	overrun-character = <0x00>;
+	cs-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+	zephyr,pm-device-runtime-auto;
+
+	dut_spi_dt: test-spi-dev@0 {
+		compatible = "vnd,spi-device";
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_M(16)>;
+	};
+};
+
+dut_spis: &spi21 {
+	compatible = "nordic,nrf-spis";
+	status = "okay";
+	def-char = <0x00>;
+	pinctrl-0 = <&spi21_default_alt>;
+	pinctrl-1 = <&spi21_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	/delete-property/rx-delay-supported;
+	/delete-property/rx-delay;
+	zephyr,pm-device-runtime-auto;
+};
diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..46ee277dbfb
--- /dev/null
+++ b/tests/drivers/spi/spi_controller_peripheral/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	spi22_default_alt: spi22_default_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 13)>,
+				<NRF_PSEL(SPIM_MISO, 1, 11)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 9)>;
+		};
+	};
+
+	spi22_sleep_alt: spi22_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 13)>,
+				<NRF_PSEL(SPIM_MISO, 1, 11)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 9)>;
+			low-power-enable;
+		};
+	};
+
+	spi21_default_alt: spi21_default_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIS_SCK, 1, 12)>,
+				<NRF_PSEL(SPIS_MISO, 1, 10)>,
+				<NRF_PSEL(SPIS_MOSI, 1, 8)>,
+				<NRF_PSEL(SPIS_CSN, 1, 14)>;
+		};
+	};
+
+	spi21_sleep_alt: spi21_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIS_SCK, 1, 12)>,
+				<NRF_PSEL(SPIS_MISO, 1, 10)>,
+				<NRF_PSEL(SPIS_MOSI, 1, 8)>,
+				<NRF_PSEL(SPIS_CSN, 1, 14)>;
+			low-power-enable;
+		};
+	};
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&spi22 {
+	status = "okay";
+	pinctrl-0 = <&spi22_default_alt>;
+	pinctrl-1 = <&spi22_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	overrun-character = <0x00>;
+	cs-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+	zephyr,pm-device-runtime-auto;
+
+	dut_spi_dt: test-spi-dev@0 {
+		compatible = "vnd,spi-device";
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_M(16)>;
+	};
+};
+
+dut_spis: &spi21 {
+	compatible = "nordic,nrf-spis";
+	status = "okay";
+	def-char = <0x00>;
+	pinctrl-0 = <&spi21_default_alt>;
+	pinctrl-1 = <&spi21_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	/delete-property/rx-delay-supported;
+	/delete-property/rx-delay;
+	zephyr,pm-device-runtime-auto;
+};
diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/nrf52840dk_nrf52840.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/nrf52840dk_nrf52840.overlay
index 8ce5342be23..18531a8faf6 100644
--- a/tests/drivers/spi/spi_controller_peripheral/boards/nrf52840dk_nrf52840.overlay
+++ b/tests/drivers/spi/spi_controller_peripheral/boards/nrf52840dk_nrf52840.overlay
@@ -65,4 +65,5 @@ dut_spis: &spi1 {
 	pinctrl-0 = <&spi1_default_alt>;
 	pinctrl-1 = <&spi1_sleep_alt>;
 	pinctrl-names = "default", "sleep";
+	zephyr,pm-device-runtime-auto;
 };
diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_common.dtsi b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_common.dtsi
index d431933ab5a..46680e31bf0 100644
--- a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_common.dtsi
+++ b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_common.dtsi
@@ -77,4 +77,5 @@ dut_spis: &spi131 {
 	pinctrl-names = "default", "sleep";
 	/delete-property/rx-delay-supported;
 	/delete-property/rx-delay;
+	zephyr,pm-device-runtime-auto;
 };
diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_cpuapp_fast.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_cpuapp_fast.overlay
index 798d28b8ab9..f145a10bb67 100644
--- a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_cpuapp_fast.overlay
+++ b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54h20dk_nrf54h20_cpuapp_fast.overlay
@@ -77,4 +77,5 @@ dut_spis: &spi131 {
 	memory-regions = <&cpuapp_dma_region>;
 	/delete-property/rx-delay-supported;
 	/delete-property/rx-delay;
+	zephyr,pm-device-runtime-auto;
 };
diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
index 0188a2c4e24..e1b26832932 100644
--- a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
+++ b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
@@ -71,4 +71,5 @@ dut_spis: &spi21 {
 	pinctrl-names = "default", "sleep";
 	/delete-property/rx-delay-supported;
 	/delete-property/rx-delay;
+	zephyr,pm-device-runtime-auto;
 };
diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..5b3a64e7fbc
--- /dev/null
+++ b/tests/drivers/spi/spi_controller_peripheral/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	spi22_default_alt: spi22_default_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 13)>,
+				<NRF_PSEL(SPIM_MISO, 1, 11)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 9)>;
+		};
+	};
+
+	spi22_sleep_alt: spi22_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 13)>,
+				<NRF_PSEL(SPIM_MISO, 1, 11)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 9)>;
+			low-power-enable;
+		};
+	};
+
+	spi21_default_alt: spi21_default_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIS_SCK, 1, 12)>,
+				<NRF_PSEL(SPIS_MISO, 1, 10)>,
+				<NRF_PSEL(SPIS_MOSI, 1, 8)>,
+				<NRF_PSEL(SPIS_CSN, 1, 14)>;
+		};
+	};
+
+	spi21_sleep_alt: spi21_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIS_SCK, 1, 12)>,
+				<NRF_PSEL(SPIS_MISO, 1, 10)>,
+				<NRF_PSEL(SPIS_MOSI, 1, 8)>,
+				<NRF_PSEL(SPIS_CSN, 1, 14)>;
+			low-power-enable;
+		};
+	};
+
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&spi22 {
+	status = "okay";
+	pinctrl-0 = <&spi22_default_alt>;
+	pinctrl-1 = <&spi22_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	overrun-character = <0x00>;
+	cs-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+	zephyr,pm-device-runtime-auto;
+
+	dut_spi_dt: test-spi-dev@0 {
+		compatible = "vnd,spi-device";
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_M(16)>;
+	};
+};
+
+dut_spis: &spi21 {
+	compatible = "nordic,nrf-spis";
+	status = "okay";
+	def-char = <0x00>;
+	pinctrl-0 = <&spi21_default_alt>;
+	pinctrl-1 = <&spi21_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	/delete-property/rx-delay-supported;
+	/delete-property/rx-delay;
+	zephyr,pm-device-runtime-auto;
+};
diff --git a/tests/drivers/spi/spi_controller_peripheral/testcase.yaml b/tests/drivers/spi/spi_controller_peripheral/testcase.yaml
index ca153293f57..c06c1c077fe 100644
--- a/tests/drivers/spi/spi_controller_peripheral/testcase.yaml
+++ b/tests/drivers/spi/spi_controller_peripheral/testcase.yaml
@@ -13,6 +13,7 @@ common:
     - nrf54h20dk/nrf54h20/cpuapp
     - nrf54h20dk/nrf54h20/cpurad
     - nrf54h20dk/nrf54h20/cpuppr
+    - ophelia4ev/nrf54l15/cpuapp
 
 tests:
   drivers.spi.spi_mode0:
@@ -65,6 +66,7 @@ tests:
       - nrf54h20dk/nrf54h20/cpurad
       - nrf54h20dk/nrf54h20/cpuppr
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
 
   drivers.spi.spis_fast:
     # SPIS120 instance occupies P6 which is not available on nRF54H20 DK pin headers
@@ -77,6 +79,7 @@ tests:
       - nrf54h20dk/nrf54h20/cpurad
       - nrf54h20dk/nrf54h20/cpuppr
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
 
   drivers.spi.pm_runtime:
     extra_configs:
diff --git a/tests/drivers/spi/spi_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..43edc077d97
--- /dev/null
+++ b/tests/drivers/spi/spi_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	spi22_default_alt: spi22_default_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 13)>,
+				<NRF_PSEL(SPIM_MISO, 1, 11)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 9)>;
+		};
+	};
+
+	spi22_sleep_alt: spi22_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 13)>,
+				<NRF_PSEL(SPIM_MISO, 1, 11)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 9)>;
+			low-power-enable;
+		};
+	};
+
+	spi21_default_alt: spi21_default_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIS_SCK, 1, 12)>,
+				<NRF_PSEL(SPIS_MISO, 1, 10)>,
+				<NRF_PSEL(SPIS_MOSI, 1, 8)>,
+				<NRF_PSEL(SPIS_CSN, 1, 14)>;
+		};
+	};
+
+	spi21_sleep_alt: spi21_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIS_SCK, 1, 12)>,
+				<NRF_PSEL(SPIS_MISO, 1, 10)>,
+				<NRF_PSEL(SPIS_MOSI, 1, 8)>,
+				<NRF_PSEL(SPIS_CSN, 1, 14)>;
+			low-power-enable;
+		};
+	};
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&spi22 {
+	status = "okay";
+	pinctrl-0 = <&spi22_default_alt>;
+	pinctrl-1 = <&spi22_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	overrun-character = <0x00>;
+	cs-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+
+	dut_spi_dt: test-spi-dev@0 {
+		compatible = "vnd,spi-device";
+		reg = <0>;
+		spi-max-frequency = <4000000>;
+	};
+};
+
+dut_spis: &spi21 {
+	compatible = "nordic,nrf-spis";
+	status = "okay";
+	def-char = <0x00>;
+	pinctrl-0 = <&spi21_default_alt>;
+	pinctrl-1 = <&spi21_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	/delete-property/rx-delay-supported;
+	/delete-property/rx-delay;
+};
diff --git a/tests/drivers/spi/spi_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..43edc077d97
--- /dev/null
+++ b/tests/drivers/spi/spi_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	spi22_default_alt: spi22_default_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 13)>,
+				<NRF_PSEL(SPIM_MISO, 1, 11)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 9)>;
+		};
+	};
+
+	spi22_sleep_alt: spi22_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 13)>,
+				<NRF_PSEL(SPIM_MISO, 1, 11)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 9)>;
+			low-power-enable;
+		};
+	};
+
+	spi21_default_alt: spi21_default_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIS_SCK, 1, 12)>,
+				<NRF_PSEL(SPIS_MISO, 1, 10)>,
+				<NRF_PSEL(SPIS_MOSI, 1, 8)>,
+				<NRF_PSEL(SPIS_CSN, 1, 14)>;
+		};
+	};
+
+	spi21_sleep_alt: spi21_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIS_SCK, 1, 12)>,
+				<NRF_PSEL(SPIS_MISO, 1, 10)>,
+				<NRF_PSEL(SPIS_MOSI, 1, 8)>,
+				<NRF_PSEL(SPIS_CSN, 1, 14)>;
+			low-power-enable;
+		};
+	};
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&spi22 {
+	status = "okay";
+	pinctrl-0 = <&spi22_default_alt>;
+	pinctrl-1 = <&spi22_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	overrun-character = <0x00>;
+	cs-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+
+	dut_spi_dt: test-spi-dev@0 {
+		compatible = "vnd,spi-device";
+		reg = <0>;
+		spi-max-frequency = <4000000>;
+	};
+};
+
+dut_spis: &spi21 {
+	compatible = "nordic,nrf-spis";
+	status = "okay";
+	def-char = <0x00>;
+	pinctrl-0 = <&spi21_default_alt>;
+	pinctrl-1 = <&spi21_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	/delete-property/rx-delay-supported;
+	/delete-property/rx-delay;
+};
diff --git a/tests/drivers/spi/spi_error_cases/boards/nrf54l20pdk_nrf54l20_cpuapp.overlay b/tests/drivers/spi/spi_error_cases/boards/nrf54l20pdk_nrf54l20_cpuapp.overlay
index 2ee989bda2b..c723ff2cbd2 100644
--- a/tests/drivers/spi/spi_error_cases/boards/nrf54l20pdk_nrf54l20_cpuapp.overlay
+++ b/tests/drivers/spi/spi_error_cases/boards/nrf54l20pdk_nrf54l20_cpuapp.overlay
@@ -54,7 +54,7 @@
 	pinctrl-1 = <&spi22_sleep_alt>;
 	pinctrl-names = "default", "sleep";
 	overrun-character = <0x00>;
-	cs-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+	cs-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
 	dut_spi_dt: test-spi-dev@0 {
 		compatible = "vnd,spi-device";
 		reg = <0>;
diff --git a/tests/drivers/spi/spi_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..6e272f3f2db
--- /dev/null
+++ b/tests/drivers/spi/spi_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	spi22_default_alt: spi22_default_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 13)>,
+				<NRF_PSEL(SPIM_MISO, 1, 11)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 9)>;
+		};
+	};
+
+	spi22_sleep_alt: spi22_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 1, 13)>,
+				<NRF_PSEL(SPIM_MISO, 1, 11)>,
+				<NRF_PSEL(SPIM_MOSI, 1, 9)>;
+			low-power-enable;
+		};
+	};
+
+	spi21_default_alt: spi21_default_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIS_SCK, 1, 12)>,
+				<NRF_PSEL(SPIS_MISO, 1, 10)>,
+				<NRF_PSEL(SPIS_MOSI, 1, 8)>,
+				<NRF_PSEL(SPIS_CSN, 1, 14)>;
+		};
+	};
+
+	spi21_sleep_alt: spi21_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIS_SCK, 1, 12)>,
+				<NRF_PSEL(SPIS_MISO, 1, 10)>,
+				<NRF_PSEL(SPIS_MOSI, 1, 8)>,
+				<NRF_PSEL(SPIS_CSN, 1, 14)>;
+			low-power-enable;
+		};
+	};
+
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&spi22 {
+	status = "okay";
+	pinctrl-0 = <&spi22_default_alt>;
+	pinctrl-1 = <&spi22_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	overrun-character = <0x00>;
+	cs-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+
+	dut_spi_dt: test-spi-dev@0 {
+		compatible = "vnd,spi-device";
+		reg = <0>;
+		spi-max-frequency = <4000000>;
+	};
+};
+
+dut_spis: &spi21 {
+	compatible = "nordic,nrf-spis";
+	status = "okay";
+	def-char = <0x00>;
+	pinctrl-0 = <&spi21_default_alt>;
+	pinctrl-1 = <&spi21_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	/delete-property/rx-delay-supported;
+	/delete-property/rx-delay;
+};
diff --git a/tests/drivers/spi/spi_error_cases/testcase.yaml b/tests/drivers/spi/spi_error_cases/testcase.yaml
index 366b736d8fb..2f097fb072c 100644
--- a/tests/drivers/spi/spi_error_cases/testcase.yaml
+++ b/tests/drivers/spi/spi_error_cases/testcase.yaml
@@ -13,6 +13,7 @@ tests:
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54h20dk/nrf54h20/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf52840dk/nrf52840
   drivers.spi.spi_error_cases.fast:
diff --git a/tests/drivers/spi/spi_loopback/boards/arduino_uno_r4_r7fa4m1ab3cfm_minima.overlay b/tests/drivers/spi/spi_loopback/boards/arduino_uno_r4_r7fa4m1ab3cfm_minima.overlay
new file mode 100644
index 00000000000..a33d92098d7
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/arduino_uno_r4_r7fa4m1ab3cfm_minima.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi1 {
+	rx-dtc;
+	tx-dtc;
+
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <2000000>;
+	};
+
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <3000000>;
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/arduino_uno_r4_r7fa4m1ab3cfm_wifi.overlay b/tests/drivers/spi/spi_loopback/boards/arduino_uno_r4_r7fa4m1ab3cfm_wifi.overlay
new file mode 100644
index 00000000000..5d712797126
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/arduino_uno_r4_r7fa4m1ab3cfm_wifi.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi0 {
+	rx-dtc;
+	tx-dtc;
+
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <2000000>;
+	};
+
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <3000000>;
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_loopback/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..fbd0ef8b230
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	spi00_default: spi00_default {
+		group1 {
+			psels = <NRF_PSEL(SPIM_MISO, 2, 9)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 6)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 8)>;
+			nordic,drive-mode = <NRF_DRIVE_E0E1>;
+		};
+	};
+
+	spi00_sleep: spi00_sleep {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 6)>,
+				<NRF_PSEL(SPIM_MISO, 2, 9)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 8)>;
+			low-power-enable;
+		};
+	};
+};
+
+/delete-node/ &mx25r64;
+
+&spi00 {
+	status = "okay";
+	pinctrl-0 = <&spi00_default>;
+	pinctrl-1 = <&spi00_sleep>;
+	pinctrl-names = "default", "sleep";
+	overrun-character = <0x00>;
+	zephyr,pm-device-runtime-auto;
+
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_M(2)>;
+	};
+
+	dut_fast: fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_M(4)>;
+	};
+};
+
+&gpio2 {
+	status = "okay";
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_loopback/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..fbd0ef8b230
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	spi00_default: spi00_default {
+		group1 {
+			psels = <NRF_PSEL(SPIM_MISO, 2, 9)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 6)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 8)>;
+			nordic,drive-mode = <NRF_DRIVE_E0E1>;
+		};
+	};
+
+	spi00_sleep: spi00_sleep {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 6)>,
+				<NRF_PSEL(SPIM_MISO, 2, 9)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 8)>;
+			low-power-enable;
+		};
+	};
+};
+
+/delete-node/ &mx25r64;
+
+&spi00 {
+	status = "okay";
+	pinctrl-0 = <&spi00_default>;
+	pinctrl-1 = <&spi00_sleep>;
+	pinctrl-names = "default", "sleep";
+	overrun-character = <0x00>;
+	zephyr,pm-device-runtime-auto;
+
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_M(2)>;
+	};
+
+	dut_fast: fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_M(4)>;
+	};
+};
+
+&gpio2 {
+	status = "okay";
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/ek_ra4l1.conf b/tests/drivers/spi/spi_loopback/boards/ek_ra4l1.conf
new file mode 100644
index 00000000000..a231e084368
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/ek_ra4l1.conf
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SPI_LOOPBACK_MODE_LOOP=y
+CONFIG_SPI_INTERRUPT=y
+CONFIG_SPI_RA_DTC=y
diff --git a/tests/drivers/spi/spi_loopback/boards/ek_ra4l1.overlay b/tests/drivers/spi/spi_loopback/boards/ek_ra4l1.overlay
new file mode 100644
index 00000000000..59314554dc3
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/ek_ra4l1.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi0 {
+	rx-dtc;
+	tx-dtc;
+
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <2000000>;
+	};
+
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <3000000>;
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/ek_ra4m1.conf b/tests/drivers/spi/spi_loopback/boards/ek_ra4m1.conf
new file mode 100644
index 00000000000..a231e084368
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/ek_ra4m1.conf
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SPI_LOOPBACK_MODE_LOOP=y
+CONFIG_SPI_INTERRUPT=y
+CONFIG_SPI_RA_DTC=y
diff --git a/tests/drivers/spi/spi_loopback/boards/ek_ra4m1.overlay b/tests/drivers/spi/spi_loopback/boards/ek_ra4m1.overlay
new file mode 100644
index 00000000000..0ae7478a327
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/ek_ra4m1.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi1 {
+	rx-dtc;
+	tx-dtc;
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <2000000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <3000000>;
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/ek_ra8d1.overlay b/tests/drivers/spi/spi_loopback/boards/ek_ra8d1.overlay
index a02d082b099..bc2aa5df4aa 100644
--- a/tests/drivers/spi/spi_loopback/boards/ek_ra8d1.overlay
+++ b/tests/drivers/spi/spi_loopback/boards/ek_ra8d1.overlay
@@ -1,9 +1,9 @@
 /*
- * Copyright (c) 2024 Renesas Electronics Corporation
+ * Copyright (c) 2024-2025 Renesas Electronics Corporation
  * SPDX-License-Identifier: Apache-2.0
  */
 
-&spi0 {
+&spi1 {
 	rx-dtc;
 	tx-dtc;
 	slow@0 {
diff --git a/tests/drivers/spi/spi_loopback/boards/fpb_ra4e1.conf b/tests/drivers/spi/spi_loopback/boards/fpb_ra4e1.conf
new file mode 100644
index 00000000000..a231e084368
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/fpb_ra4e1.conf
@@ -0,0 +1,6 @@
+# Copyright (c) 2025 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SPI_LOOPBACK_MODE_LOOP=y
+CONFIG_SPI_INTERRUPT=y
+CONFIG_SPI_RA_DTC=y
diff --git a/tests/drivers/spi/spi_loopback/boards/fpb_ra4e1.overlay b/tests/drivers/spi/spi_loopback/boards/fpb_ra4e1.overlay
new file mode 100644
index 00000000000..64cacf8a211
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/fpb_ra4e1.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi0 {
+	rx-dtc;
+	tx-dtc;
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <2000000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <3000000>;
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_ke17z.conf b/tests/drivers/spi/spi_loopback/boards/frdm_ke17z.conf
deleted file mode 100644
index 5014becf5b0..00000000000
--- a/tests/drivers/spi/spi_loopback/boards/frdm_ke17z.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright 2024 NXP
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-CONFIG_SPI_MCUX_LPSPI_DMA=y
-CONFIG_SPI_ASYNC=n
diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_ke17z.overlay b/tests/drivers/spi/spi_loopback/boards/frdm_ke17z.overlay
index a28ed492be7..bbeaec85d6e 100644
--- a/tests/drivers/spi/spi_loopback/boards/frdm_ke17z.overlay
+++ b/tests/drivers/spi/spi_loopback/boards/frdm_ke17z.overlay
@@ -9,14 +9,14 @@
  */
 
 &lpspi0 {
-	slow@0 {
+	slow@1 {
 		compatible = "test-spi-loopback-slow";
-		reg = <0>;
+		reg = <1>;
 		spi-max-frequency = <500000>;
 	};
-	fast@0 {
+	fast@1 {
 		compatible = "test-spi-loopback-fast";
-		reg = <0>;
+		reg = <1>;
 		spi-max-frequency = <16000000>;
 	};
 };
diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_ke17z512.conf b/tests/drivers/spi/spi_loopback/boards/frdm_ke17z512.conf
deleted file mode 100644
index 5014becf5b0..00000000000
--- a/tests/drivers/spi/spi_loopback/boards/frdm_ke17z512.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright 2024 NXP
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-CONFIG_SPI_MCUX_LPSPI_DMA=y
-CONFIG_SPI_ASYNC=n
diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_ke17z512.overlay b/tests/drivers/spi/spi_loopback/boards/frdm_ke17z512.overlay
index a28ed492be7..62bdac8b3bc 100644
--- a/tests/drivers/spi/spi_loopback/boards/frdm_ke17z512.overlay
+++ b/tests/drivers/spi/spi_loopback/boards/frdm_ke17z512.overlay
@@ -9,14 +9,14 @@
  */
 
 &lpspi0 {
-	slow@0 {
+	slow@2 {
 		compatible = "test-spi-loopback-slow";
-		reg = <0>;
+		reg = <2>;
 		spi-max-frequency = <500000>;
 	};
-	fast@0 {
+	fast@2 {
 		compatible = "test-spi-loopback-fast";
-		reg = <0>;
+		reg = <2>;
 		spi-max-frequency = <16000000>;
 	};
 };
diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_mcxa156.overlay b/tests/drivers/spi/spi_loopback/boards/frdm_mcxa156.overlay
new file mode 100644
index 00000000000..7f5c1bca9fd
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/frdm_mcxa156.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* To test this sample, connect
+ * LPSPI0 MOSI(J6-6, P1_0/LPSPI0_SDO)     -->        LPSPI0 MISO(J6-5, P1_2/LPSPI0_SDI)
+ */
+&lpspi0 {
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_mcxn236.conf b/tests/drivers/spi/spi_loopback/boards/frdm_mcxn236.conf
deleted file mode 100644
index a325815e8cf..00000000000
--- a/tests/drivers/spi/spi_loopback/boards/frdm_mcxn236.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright 2024 NXP
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-CONFIG_SPI_MCUX_LPSPI_DMA=n
-CONFIG_SPI_ASYNC=n
diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_mcxn236.overlay b/tests/drivers/spi/spi_loopback/boards/frdm_mcxn236.overlay
index 0e47064ccca..c9777aa7e1e 100644
--- a/tests/drivers/spi/spi_loopback/boards/frdm_mcxn236.overlay
+++ b/tests/drivers/spi/spi_loopback/boards/frdm_mcxn236.overlay
@@ -5,7 +5,7 @@
  */
 
 /* To test this sample, connect
- * LPSPI3 MOSI(J2-8, P1_0/FC3_P0)     -->        LPSPI5 MISO(J2-10, P1_2/FC3_P2)
+ * LPSPI3 MOSI(J2-8, P1_0/FC3_P0)     -->        LPSPI3 MISO(J2-10, P1_2/FC3_P2)
  */
 &flexcomm3_lpspi3 {
 	slow@0 {
diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_mcxn947_mcxn947_cpu0.conf b/tests/drivers/spi/spi_loopback/boards/frdm_mcxn947_mcxn947_cpu0.conf
deleted file mode 100644
index 5014becf5b0..00000000000
--- a/tests/drivers/spi/spi_loopback/boards/frdm_mcxn947_mcxn947_cpu0.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright 2024 NXP
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-CONFIG_SPI_MCUX_LPSPI_DMA=y
-CONFIG_SPI_ASYNC=n
diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_mcxn947_mcxn947_cpu0_qspi.conf b/tests/drivers/spi/spi_loopback/boards/frdm_mcxn947_mcxn947_cpu0_qspi.conf
deleted file mode 100644
index 5014becf5b0..00000000000
--- a/tests/drivers/spi/spi_loopback/boards/frdm_mcxn947_mcxn947_cpu0_qspi.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright 2024 NXP
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-CONFIG_SPI_MCUX_LPSPI_DMA=y
-CONFIG_SPI_ASYNC=n
diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_mcxw72_mcxw727c_cpu0.overlay b/tests/drivers/spi/spi_loopback/boards/frdm_mcxw72_mcxw727c_cpu0.overlay
new file mode 100644
index 00000000000..eca30219f2e
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/frdm_mcxw72_mcxw727c_cpu0.overlay
@@ -0,0 +1,23 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+
+/*
+ * This is a loopback setup for the frdm_mcxw72
+ * To test this sample, connect J2.6 <-> J2.7
+ */
+&lpspi1 {
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/frdm_rw612.overlay b/tests/drivers/spi/spi_loopback/boards/frdm_rw612.overlay
index d6c22f1e15e..a37180ba106 100644
--- a/tests/drivers/spi/spi_loopback/boards/frdm_rw612.overlay
+++ b/tests/drivers/spi/spi_loopback/boards/frdm_rw612.overlay
@@ -1,9 +1,10 @@
 /*
- * Copyright 2024 NXP
+ * Copyright 2024-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
+/* Short MOSI and MISO externally using header J1 pins 2 and 4 */
 &flexcomm1 {
 	slow@0 {
 		compatible = "test-spi-loopback-slow";
diff --git a/tests/drivers/spi/spi_loopback/boards/imx95_evk_mimx9596_m7.conf b/tests/drivers/spi/spi_loopback/boards/imx95_evk_mimx9596_m7.conf
new file mode 100644
index 00000000000..469620fed4e
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/imx95_evk_mimx9596_m7.conf
@@ -0,0 +1 @@
+CONFIG_SPI_LOOPBACK_MODE_LOOP=y
diff --git a/tests/drivers/spi/spi_loopback/boards/imx95_evk_mimx9596_m7.overlay b/tests/drivers/spi/spi_loopback/boards/imx95_evk_mimx9596_m7.overlay
new file mode 100644
index 00000000000..574f9c4787e
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/imx95_evk_mimx9596_m7.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&lpspi1 {
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <1000000>;
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/max78000fthr_max78000_m4.conf b/tests/drivers/spi/spi_loopback/boards/max78000fthr_max78000_m4.conf
new file mode 100644
index 00000000000..fdddf5a9ab1
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max78000fthr_max78000_m4.conf
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2025 Analog Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+CONFIG_SPI_ASYNC=y
+CONFIG_SPI_MAX32_INTERRUPT=y
diff --git a/tests/drivers/spi/spi_loopback/boards/max78000fthr_max78000_m4.overlay b/tests/drivers/spi/spi_loopback/boards/max78000fthr_max78000_m4.overlay
new file mode 100644
index 00000000000..a44098a6662
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/max78000fthr_max78000_m4.overlay
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi0 {
+	dmas = <&dma0 1 MAX78_DMA_SLOT_SPI0_TX>, <&dma0 2 MAX78_DMA_SLOT_SPI0_RX>;
+	dma-names = "tx", "rx";
+
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <128000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <400000>;
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/tests/drivers/spi/spi_loopback/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..c0539a15be5
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2024-2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Connect J2-10 and J2-8 */
+&flexcomm1_lpspi1 {
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay b/tests/drivers/spi/spi_loopback/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay
new file mode 100644
index 00000000000..c78af9d8fbc
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Connect J2-10 and J2-8 */
+&flexcomm1_lpspi1 {
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/mcxw72_evk_mcxw727c_cpu0.overlay b/tests/drivers/spi/spi_loopback/boards/mcxw72_evk_mcxw727c_cpu0.overlay
new file mode 100644
index 00000000000..baa1ce3c6ed
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/mcxw72_evk_mcxw727c_cpu0.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&lpspi1 {
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1010_evk.conf b/tests/drivers/spi/spi_loopback/boards/mimxrt1010_evk.conf
deleted file mode 100644
index bf53e8cb950..00000000000
--- a/tests/drivers/spi/spi_loopback/boards/mimxrt1010_evk.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2021, NXP
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-CONFIG_SPI_MCUX_LPSPI_DMA=y
-CONFIG_SPI_ASYNC=n
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1015_evk.conf b/tests/drivers/spi/spi_loopback/boards/mimxrt1015_evk.conf
deleted file mode 100644
index bf53e8cb950..00000000000
--- a/tests/drivers/spi/spi_loopback/boards/mimxrt1015_evk.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2021, NXP
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-CONFIG_SPI_MCUX_LPSPI_DMA=y
-CONFIG_SPI_ASYNC=n
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1020_evk.conf b/tests/drivers/spi/spi_loopback/boards/mimxrt1020_evk.conf
deleted file mode 100644
index bf53e8cb950..00000000000
--- a/tests/drivers/spi/spi_loopback/boards/mimxrt1020_evk.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2021, NXP
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-CONFIG_SPI_MCUX_LPSPI_DMA=y
-CONFIG_SPI_ASYNC=n
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1024_evk.conf b/tests/drivers/spi/spi_loopback/boards/mimxrt1024_evk.conf
deleted file mode 100644
index bf53e8cb950..00000000000
--- a/tests/drivers/spi/spi_loopback/boards/mimxrt1024_evk.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2021, NXP
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-CONFIG_SPI_MCUX_LPSPI_DMA=y
-CONFIG_SPI_ASYNC=n
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1040_evk.conf b/tests/drivers/spi/spi_loopback/boards/mimxrt1040_evk.conf
deleted file mode 100644
index 7652fe0f65f..00000000000
--- a/tests/drivers/spi/spi_loopback/boards/mimxrt1040_evk.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright 2023 NXP
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-CONFIG_SPI_MCUX_LPSPI_DMA=y
-CONFIG_SPI_ASYNC=n
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1040_evk_flexio_spi.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt1040_evk_flexio_spi.overlay
new file mode 100644
index 00000000000..154a56c46b8
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/mimxrt1040_evk_flexio_spi.overlay
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2024, STRIM, ALC
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Connect J16-7 to J16-8
+ * Connect J17-9 to J17-10
+ */
+&pinctrl {
+	pinmux_flexio3spi0: pinmux_flexio3spi0 {
+		group0 {
+			pinmux =
+				<&iomuxc_gpio_ad_b0_15_gpio1_io15>, /* cs */
+				<&iomuxc_gpio_ad_b1_04_flexio3_flexio04>, /* sck */
+				<&iomuxc_gpio_ad_b1_01_flexio3_flexio01>, /* sdo */
+				<&iomuxc_gpio_ad_b1_00_flexio3_flexio00>; /* sdi */
+			drive-strength = "r0-6";
+			slew-rate = "slow";
+			nxp,speed = "150-mhz";
+		};
+	};
+	pinmux_flexio3spi1: pinmux_flexio3spi1 {
+		group0 {
+			pinmux =
+				<&iomuxc_gpio_ad_b0_14_gpio1_io14>, /* cs */
+				<&iomuxc_gpio_ad_b1_05_flexio3_flexio05>, /* sck */
+				<&iomuxc_gpio_ad_b1_03_flexio3_flexio03>, /* sdo */
+				<&iomuxc_gpio_ad_b1_02_flexio3_flexio02>; /* sdi */
+			drive-strength = "r0-6";
+			slew-rate = "slow";
+			nxp,speed = "150-mhz";
+		};
+	};
+};
+
+&flexio3 {
+	status = "okay";
+	flexio3_spi0: flexio3_spi0 {
+		compatible = "nxp,flexio-spi";
+		status = "okay";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cs-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
+		sdo-pin = <1>;
+		sdi-pin = <0>;
+		sck-pin = <4>;
+		pinctrl-0 = <&pinmux_flexio3spi0>;
+		pinctrl-names = "default";
+		slow@0 {
+			status = "okay";
+			compatible = "test-spi-loopback-slow";
+			reg = <0>;
+			spi-max-frequency = <500000>;
+		};
+	};
+	flexio3_spi1: flexio3_spi1 {
+		compatible = "nxp,flexio-spi";
+		status = "okay";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+		sdo-pin = <3>;
+		sdi-pin = <2>;
+		sck-pin = <5>;
+		pinctrl-0 = <&pinmux_flexio3spi1>;
+		pinctrl-names = "default";
+		fast@0 {
+			status = "okay";
+			compatible = "test-spi-loopback-fast";
+			reg = <0>;
+			spi-max-frequency = <4000000>;
+		};
+	};
+};
+
+/* pinmux_lpspi3 overlaps pinmux_flexio3spi1 */
+&lpspi3 {
+	status = "disabled";
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1050_evk.conf b/tests/drivers/spi/spi_loopback/boards/mimxrt1050_evk.conf
deleted file mode 100644
index 5181a16951d..00000000000
--- a/tests/drivers/spi/spi_loopback/boards/mimxrt1050_evk.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2018, NXP
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-CONFIG_SPI_MCUX_LPSPI_DMA=y
-CONFIG_SPI_ASYNC=n
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1060_evk.conf b/tests/drivers/spi/spi_loopback/boards/mimxrt1060_evk.conf
deleted file mode 100644
index bf53e8cb950..00000000000
--- a/tests/drivers/spi/spi_loopback/boards/mimxrt1060_evk.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2021, NXP
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-CONFIG_SPI_MCUX_LPSPI_DMA=y
-CONFIG_SPI_ASYNC=n
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
new file mode 100644
index 00000000000..979062e18d9
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2022 Kumar Gala <galak@kernel.org>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&lpspi1 {
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1064_evk.conf b/tests/drivers/spi/spi_loopback/boards/mimxrt1064_evk.conf
deleted file mode 100644
index bf53e8cb950..00000000000
--- a/tests/drivers/spi/spi_loopback/boards/mimxrt1064_evk.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright (c) 2021, NXP
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-CONFIG_SPI_MCUX_LPSPI_DMA=y
-CONFIG_SPI_ASYNC=n
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf b/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf
deleted file mode 100644
index 7652fe0f65f..00000000000
--- a/tests/drivers/spi/spi_loopback/boards/mimxrt1170_evk_mimxrt1176_cm7_A.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Copyright 2023 NXP
-#
-# SPDX-License-Identifier: Apache-2.0
-#
-CONFIG_SPI_MCUX_LPSPI_DMA=y
-CONFIG_SPI_ASYNC=n
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm33.conf b/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm33.conf
new file mode 100644
index 00000000000..cf4dcd316a9
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm33.conf
@@ -0,0 +1,6 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+CONFIG_DMA_MCUX_USE_DTCM_FOR_DMA_DESCRIPTORS=n
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
new file mode 100644
index 00000000000..c1de4474f60
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* To test this sample, connect J44.8 <-> J44.10 */
+
+/ {
+	chosen {
+		zephyr,sram = &dtcm;
+	};
+};
+
+&lpspi3 {
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm7.conf b/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
new file mode 100644
index 00000000000..cf4dcd316a9
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
@@ -0,0 +1,6 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+CONFIG_DMA_MCUX_USE_DTCM_FOR_DMA_DESCRIPTORS=n
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
new file mode 100644
index 00000000000..6a44a9ae299
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/mimxrt1180_evk_mimxrt1189_cm7.overlay
@@ -0,0 +1,32 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* To test this sample, connect J44.8 <-> J44.10 */
+
+#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
+
+/ {
+	chosen {
+		zephyr,sram = &ocram1;
+	};
+};
+
+&ocram1 {
+	zephyr,memory-attr = <( DT_MEM_ARM(ATTR_MPU_RAM_NOCACHE) )>;
+};
+
+&lpspi3 {
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay b/tests/drivers/spi/spi_loopback/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay
new file mode 100644
index 00000000000..663ea5104f6
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/mimxrt700_evk_mimxrt798s_cm33_cpu0.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* To test this sample, connect J20.3 <-> J20.5 */
+&lpspi14 {
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/nucleo_c071rb.conf b/tests/drivers/spi/spi_loopback/boards/nucleo_c071rb.conf
new file mode 100644
index 00000000000..5e05f18f57a
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/nucleo_c071rb.conf
@@ -0,0 +1 @@
+CONFIG_SPI_LARGE_BUFFER_SIZE=8000
diff --git a/tests/drivers/spi/spi_loopback/boards/nucleo_c071rb.overlay b/tests/drivers/spi/spi_loopback/boards/nucleo_c071rb.overlay
new file mode 100644
index 00000000000..3717c7fbd2b
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/nucleo_c071rb.overlay
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi1 {
+	dmas = <&dmamux1 2 17 (STM32_DMA_PERIPH_TX | STM32_DMA_PRIORITY_HIGH)
+		&dmamux1 1 16 (STM32_DMA_PERIPH_RX | STM32_DMA_PRIORITY_HIGH)>;
+	dma-names = "tx", "rx";
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+	};
+};
+
+&dma1 {
+	status = "okay";
+};
+
+&dmamux1 {
+	status = "okay";
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/nucleo_n657x0_q_stm32n657xx_sb.conf b/tests/drivers/spi/spi_loopback/boards/nucleo_n657x0_q_stm32n657xx_sb.conf
new file mode 100644
index 00000000000..c448e14811f
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/nucleo_n657x0_q_stm32n657xx_sb.conf
@@ -0,0 +1 @@
+CONFIG_NOCACHE_MEMORY=y
diff --git a/tests/drivers/spi/spi_loopback/boards/nucleo_n657x0_q_stm32n657xx_sb.overlay b/tests/drivers/spi/spi_loopback/boards/nucleo_n657x0_q_stm32n657xx_sb.overlay
new file mode 100644
index 00000000000..24238c4b7bc
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/nucleo_n657x0_q_stm32n657xx_sb.overlay
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi5 {
+	dmas = <&gpdma1 0 88 STM32_DMA_PERIPH_TX
+		&gpdma1 1 87 STM32_DMA_PERIPH_RX>;
+	dma-names = "tx", "rx";
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+	};
+};
+
+&gpdma1 {
+	status = "okay";
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/numaker_m55m1.conf b/tests/drivers/spi/spi_loopback/boards/numaker_m55m1.conf
new file mode 100644
index 00000000000..3d2da209abc
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/numaker_m55m1.conf
@@ -0,0 +1 @@
+CONFIG_SPI_ASYNC=n
diff --git a/tests/drivers/spi/spi_loopback/boards/numaker_m55m1.overlay b/tests/drivers/spi/spi_loopback/boards/numaker_m55m1.overlay
new file mode 100644
index 00000000000..409396e2081
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/numaker_m55m1.overlay
@@ -0,0 +1,29 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+&pinctrl {
+/* EVB's NU5: SS/CLK/MISO/MOSI */
+	spi2_default: spi2_default {
+		group0 {
+			pinmux = <PA11MFP_SPI2_SS>,
+				 <PA10MFP_SPI2_CLK>,
+				 <PA9MFP_SPI2_MISO>,
+				 <PA8MFP_SPI2_MOSI>;
+		};
+	};
+};
+
+&spi2 {
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_K(500)>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_M(16)>;
+	};
+	status = "okay";
+	pinctrl-0 = <&spi2_default>;
+	pinctrl-names = "default";
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/spi/spi_loopback/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..4471d299ac1
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KGs
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	spi00_default: spi00_default {
+		group1 {
+			psels = <NRF_PSEL(SPIM_MISO, 2, 9)>;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 6)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 8)>;
+			nordic,drive-mode = <NRF_DRIVE_E0E1>;
+		};
+	};
+
+	spi00_sleep: spi00_sleep {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 6)>,
+				<NRF_PSEL(SPIM_MISO, 2, 9)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 8)>;
+			low-power-enable;
+		};
+	};
+};
+
+/delete-node/ &mx25r64;
+
+&spi00 {
+	status = "okay";
+
+	pinctrl-0 = <&spi00_default>;
+	pinctrl-1 = <&spi00_sleep>;
+	pinctrl-names = "default", "sleep";
+
+	overrun-character = <0x00>;
+	zephyr,pm-device-runtime-auto;
+
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_M(2)>;
+	};
+
+	dut_fast: fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_M(4)>;
+	};
+};
+
+&gpio2 {
+	status = "okay";
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/pico_plus2_rp2350b_m33.conf b/tests/drivers/spi/spi_loopback/boards/pico_plus2_rp2350b_m33.conf
new file mode 100644
index 00000000000..53e8607eb61
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/pico_plus2_rp2350b_m33.conf
@@ -0,0 +1 @@
+CONFIG_SPI_PL022_DMA=y
diff --git a/tests/drivers/spi/spi_loopback/boards/rpi_pico_delete_dma_props.overlay b/tests/drivers/spi/spi_loopback/boards/rpi_pico_delete_dma_props.overlay
deleted file mode 100644
index ce10b899cde..00000000000
--- a/tests/drivers/spi/spi_loopback/boards/rpi_pico_delete_dma_props.overlay
+++ /dev/null
@@ -1,10 +0,0 @@
-/*
- * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-&spi0 {
-	/delete-property/ dmas;
-	/delete-property/ dma-names;
-};
diff --git a/tests/drivers/spi/spi_loopback/boards/rpi_pico_pio.overlay b/tests/drivers/spi/spi_loopback/boards/rpi_pico_pio.overlay
new file mode 100644
index 00000000000..32cca4c6dad
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/rpi_pico_pio.overlay
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2024 The Zephyr Project Contributors
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	pio0_spi0_default: pio0_spi0_default {
+		/* gpio 17 is used for chip select, not assigned to the PIO */
+		group1 {
+			pinmux = <PIO0_P18>, <PIO0_P19>;
+		};
+		group2 {
+			pinmux = <PIO0_P16>;
+			input-enable;
+		};
+	};
+};
+
+&pio0 {
+	status = "okay";
+
+	pio0_spi0: pio0_spi0 {
+		pinctrl-0 = <&pio0_spi0_default>;
+		pinctrl-names = "default";
+
+		compatible = "raspberrypi,pico-spi-pio";
+		status = "okay";
+		#address-cells = <1>;
+		#size-cells = <0>;
+		clocks = <&clocks RPI_PICO_CLKID_CLK_SYS>;
+		miso-gpios = <&gpio0 16 0>;
+		cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
+		clk-gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>;
+		mosi-gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>;
+
+		slow@0 {
+			compatible = "test-spi-loopback-slow";
+			reg = <0>;
+			spi-max-frequency = <500000>;
+		};
+		fast@0 {
+			compatible = "test-spi-loopback-fast";
+			reg = <0>;
+			spi-max-frequency = <14000000>;
+		};
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/rpi_pico_pl022.overlay b/tests/drivers/spi/spi_loopback/boards/rpi_pico_pl022.overlay
new file mode 100644
index 00000000000..a11e292bcb5
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/rpi_pico_pl022.overlay
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi0 {
+	cs-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
+
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+	};
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/rpi_pico.overlay b/tests/drivers/spi/spi_loopback/boards/rpi_pico_pl022_dma.overlay
similarity index 100%
rename from tests/drivers/spi/spi_loopback/boards/rpi_pico.overlay
rename to tests/drivers/spi/spi_loopback/boards/rpi_pico_pl022_dma.overlay
diff --git a/tests/drivers/spi/spi_loopback/boards/same54_xpro.overlay b/tests/drivers/spi/spi_loopback/boards/same54_xpro.overlay
index ab5e6da356b..d54d2351c57 100644
--- a/tests/drivers/spi/spi_loopback/boards/same54_xpro.overlay
+++ b/tests/drivers/spi/spi_loopback/boards/same54_xpro.overlay
@@ -1,18 +1,26 @@
 /*
  * Copyright (c) 2020 Stephanos Ioannidis <root@stephanos.io>
+ * Copyright (c) 2024 Gerson Fernando Budke <nandojve@gmail.com>
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
+&dmac {
+	status = "okay";
+};
+
 &sercom4 {
 	/* Internally connect MOSI to MISO for loop-back operation */
 	dipo = <3>;
 	dopo = <2>;
+
 	/* Assign a CS pin */
 	cs-gpios = <&portb 28 GPIO_ACTIVE_LOW>;
+
 	/* Configure DMA */
 	dmas = <&dmac 0 12>, <&dmac 1 13>;
 	dma-names = "rx", "tx";
+
 	slow@0 {
 		compatible = "test-spi-loopback-slow";
 		reg = <0>;
diff --git a/tests/drivers/spi/spi_loopback/boards/stm32n6570_dk_stm32n657xx_sb.conf b/tests/drivers/spi/spi_loopback/boards/stm32n6570_dk_stm32n657xx_sb.conf
new file mode 100644
index 00000000000..c448e14811f
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/stm32n6570_dk_stm32n657xx_sb.conf
@@ -0,0 +1 @@
+CONFIG_NOCACHE_MEMORY=y
diff --git a/tests/drivers/spi/spi_loopback/boards/stm32n6570_dk_stm32n657xx_sb.overlay b/tests/drivers/spi/spi_loopback/boards/stm32n6570_dk_stm32n657xx_sb.overlay
new file mode 100644
index 00000000000..24238c4b7bc
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/stm32n6570_dk_stm32n657xx_sb.overlay
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi5 {
+	dmas = <&gpdma1 0 88 STM32_DMA_PERIPH_TX
+		&gpdma1 1 87 STM32_DMA_PERIPH_RX>;
+	dma-names = "tx", "rx";
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+	};
+};
+
+&gpdma1 {
+	status = "okay";
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/xg24_rb4187c.conf b/tests/drivers/spi/spi_loopback/boards/xg24_rb4187c.conf
new file mode 100644
index 00000000000..1e3c5f17bfc
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/xg24_rb4187c.conf
@@ -0,0 +1,2 @@
+CONFIG_DMA_MAX_DESCRIPTOR=16
+CONFIG_SPI_SILABS_EUSART_DMA_MAX_BLOCKS=10
diff --git a/tests/drivers/spi/spi_loopback/boards/xg24_rb4187c.overlay b/tests/drivers/spi/spi_loopback/boards/xg24_rb4187c.overlay
new file mode 100644
index 00000000000..fc5042f846e
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/xg24_rb4187c.overlay
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/silabs/xg24-pinctrl.h>
+
+&pinctrl {
+	eusart1_default: eusart1_default {
+		group0 {
+			pins = <EUSART1_TX_PC1>, <EUSART1_SCLK_PC3>;
+			drive-push-pull;
+			output-high;
+		};
+		group1 {
+			pins = <EUSART1_RX_PC2>;
+			input-enable;
+		};
+	};
+};
+
+&eusart1 {
+	dmas = <&dma0 DMA_REQSEL_EUSART1TXFL>,
+	       <&dma0 DMA_REQSEL_EUSART1RXFL>;
+	dma-names = "tx", "rx";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-0 = <&eusart1_default>;
+	pinctrl-names = "default";
+	status = "okay";
+	cs-gpios = <&gpioc 0 GPIO_ACTIVE_LOW>;
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@1 {
+		compatible = "test-spi-loopback-fast";
+		reg = <1>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
+&dma0 {
+	status = "okay";
+};
diff --git a/tests/drivers/spi/spi_loopback/boards/xg29_rb4412a.conf b/tests/drivers/spi/spi_loopback/boards/xg29_rb4412a.conf
new file mode 100644
index 00000000000..1e3c5f17bfc
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/xg29_rb4412a.conf
@@ -0,0 +1,2 @@
+CONFIG_DMA_MAX_DESCRIPTOR=16
+CONFIG_SPI_SILABS_EUSART_DMA_MAX_BLOCKS=10
diff --git a/tests/drivers/spi/spi_loopback/boards/xg29_rb4412a.overlay b/tests/drivers/spi/spi_loopback/boards/xg29_rb4412a.overlay
new file mode 100644
index 00000000000..58abc4e878e
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/boards/xg29_rb4412a.overlay
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/silabs/xg29-pinctrl.h>
+
+/*
+ * Connect EXP4 (PC0) and EXP6 (PC1) of the Expansion Pin header
+ */
+
+&eusart1 {
+	dmas = <&dma0 DMA_REQSEL_EUSART1TXFL>,
+	       <&dma0 DMA_REQSEL_EUSART1RXFL>;
+	dma-names = "tx", "rx";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-0 = <&eusart1_default>;
+	pinctrl-names = "default";
+	status = "okay";
+	cs-gpios = <&gpioc 0 GPIO_ACTIVE_LOW>;
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@1 {
+		compatible = "test-spi-loopback-fast";
+		reg = <1>;
+		spi-max-frequency = <10000000>;
+	};
+};
+
+&dma0 {
+	status = "okay";
+};
diff --git a/tests/drivers/spi/spi_loopback/overlay-rpi-pico-pio.conf b/tests/drivers/spi/spi_loopback/overlay-rpi-pico-pio.conf
new file mode 100644
index 00000000000..3d2da209abc
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/overlay-rpi-pico-pio.conf
@@ -0,0 +1 @@
+CONFIG_SPI_ASYNC=n
diff --git a/tests/drivers/spi/spi_loopback/socs/esp32c6.conf b/tests/drivers/spi/spi_loopback/socs/esp32c3_usb.conf
similarity index 100%
rename from tests/drivers/spi/spi_loopback/socs/esp32c6.conf
rename to tests/drivers/spi/spi_loopback/socs/esp32c3_usb.conf
diff --git a/tests/drivers/spi/spi_loopback/socs/esp32c6.overlay b/tests/drivers/spi/spi_loopback/socs/esp32c3_usb.overlay
similarity index 100%
rename from tests/drivers/spi/spi_loopback/socs/esp32c6.overlay
rename to tests/drivers/spi/spi_loopback/socs/esp32c3_usb.overlay
diff --git a/tests/drivers/spi/spi_loopback/socs/esp32c6_hpcore.conf b/tests/drivers/spi/spi_loopback/socs/esp32c6_hpcore.conf
new file mode 100644
index 00000000000..3438f794f66
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/socs/esp32c6_hpcore.conf
@@ -0,0 +1,2 @@
+CONFIG_SPI_ESP32_INTERRUPT=y
+CONFIG_HEAP_MEM_POOL_SIZE=32768
diff --git a/tests/drivers/spi/spi_loopback/socs/esp32c6_hpcore.overlay b/tests/drivers/spi/spi_loopback/socs/esp32c6_hpcore.overlay
new file mode 100644
index 00000000000..7436f9b6aec
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/socs/esp32c6_hpcore.overlay
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2022 Kumar Gala <galak@kernel.org>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	spim2_loopback: spim2_loopback {
+		group1 {
+			pinmux = <SPIM2_MISO_GPIO2>;
+			output-enable; /* Enable internal loopback */
+		};
+		group2 {
+			pinmux = <SPIM2_MOSI_GPIO2>;
+			input-enable; /* Enable internal loopback */
+		};
+		group3 {
+			pinmux = <SPIM2_SCLK_GPIO6>,
+				<SPIM2_CSEL_GPIO10>;
+		};
+	};
+};
+
+&spi2 {
+	slow@0 {
+		compatible = "test-spi-loopback-slow";
+		reg = <0>;
+		spi-max-frequency = <500000>;
+	};
+	fast@0 {
+		compatible = "test-spi-loopback-fast";
+		reg = <0>;
+		spi-max-frequency = <16000000>;
+	};
+};
+
+&spi2 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	dma-enabled;
+	pinctrl-0 = <&spim2_loopback>;
+	pinctrl-names = "default";
+	status = "okay";
+};
diff --git a/tests/drivers/spi/spi_loopback/socs/rp2040.overlay b/tests/drivers/spi/spi_loopback/socs/rp2040.overlay
new file mode 100644
index 00000000000..99b39fca98a
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/socs/rp2040.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2022 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/dma/rpi-pico-dma-rp2040.h>
diff --git a/tests/drivers/spi/spi_loopback/socs/rp2350b_m33.overlay b/tests/drivers/spi/spi_loopback/socs/rp2350b_m33.overlay
new file mode 100644
index 00000000000..1d38b504b42
--- /dev/null
+++ b/tests/drivers/spi/spi_loopback/socs/rp2350b_m33.overlay
@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2025 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/dma/rpi-pico-dma-rp2350.h>
diff --git a/tests/drivers/spi/spi_loopback/src/spi.c b/tests/drivers/spi/spi_loopback/src/spi.c
index 98c122238ea..1bfcfe4ca82 100644
--- a/tests/drivers/spi/spi_loopback/src/spi.c
+++ b/tests/drivers/spi/spi_loopback/src/spi.c
@@ -1,65 +1,52 @@
 /*
+ * Copyright 2025 NXP
  * Copyright (c) 2017 Intel Corporation.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#define LOG_LEVEL CONFIG_LOG_DEFAULT_LEVEL
-#include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(spi_loopback);
+/* To run this loopback test, connect MOSI pin to the MISO of the SPI */
 
-#include <zephyr/kernel.h>
-#include <zephyr/sys/printk.h>
-#include <string.h>
-#include <stdio.h>
-#include <assert.h>
-#include <zephyr/ztest.h>
+/*
+ ************************
+ * Include dependencies *
+ ************************
+ */
 
+#include <zephyr/ztest.h>
 #include <zephyr/drivers/spi.h>
+#include <zephyr/kernel.h>
+#include <stdio.h>
+#include <stdarg.h>
 
-#define SPI_FAST_DEV	DT_COMPAT_GET_ANY_STATUS_OKAY(test_spi_loopback_fast)
-#define SPI_SLOW_DEV	DT_COMPAT_GET_ANY_STATUS_OKAY(test_spi_loopback_slow)
-
-#if CONFIG_SPI_LOOPBACK_MODE_LOOP
-#define MODE_LOOP SPI_MODE_LOOP
-#else
-#define MODE_LOOP 0
-#endif
-
-#ifdef CONFIG_SPI_LOOPBACK_16BITS_FRAMES
-#define FRAME_SIZE (16)
-#define FRAME_SIZE_STR ", frame size = 16"
-#else
-#define FRAME_SIZE (8)
-#define FRAME_SIZE_STR ", frame size = 8"
-#endif /* CONFIG_SPI_LOOPBACK_16BITS_FRAMES */
-
-#ifdef CONFIG_DMA
-
-#ifdef CONFIG_NOCACHE_MEMORY
-#define DMA_ENABLED_STR ", DMA enabled"
-#else /* CONFIG_NOCACHE_MEMORY */
-#define DMA_ENABLED_STR ", DMA enabled (without CONFIG_NOCACHE_MEMORY)"
-#endif
-
-#else /* CONFIG_DMA */
+/*
+ **********************
+ * SPI configurations *
+ **********************
+ */
 
-#define DMA_ENABLED_STR
-#endif /* CONFIG_DMA */
+#define FRAME_SIZE COND_CODE_1(CONFIG_SPI_LOOPBACK_16BITS_FRAMES, (16), (8))
+#define MODE_LOOP  COND_CODE_1(CONFIG_SPI_LOOPBACK_MODE_LOOP, (SPI_MODE_LOOP), (0))
 
-#define SPI_OP(frame_size) SPI_OP_MODE_MASTER | SPI_MODE_CPOL | MODE_LOOP | \
-	       SPI_MODE_CPHA | SPI_WORD_SET(frame_size) | SPI_LINES_SINGLE
+#define SPI_OP(frame_size)                                                                         \
+	SPI_OP_MODE_MASTER | SPI_MODE_CPOL | MODE_LOOP | SPI_MODE_CPHA |                           \
+		SPI_WORD_SET(frame_size) | SPI_LINES_SINGLE
 
+#define SPI_FAST_DEV DT_COMPAT_GET_ANY_STATUS_OKAY(test_spi_loopback_fast)
 static struct spi_dt_spec spi_fast = SPI_DT_SPEC_GET(SPI_FAST_DEV, SPI_OP(FRAME_SIZE), 0);
-static struct spi_dt_spec spi_slow = SPI_DT_SPEC_GET(SPI_SLOW_DEV, SPI_OP(FRAME_SIZE), 0);
 
-/* to run this test, connect MOSI pin to the MISO of the SPI */
+#define SPI_SLOW_DEV DT_COMPAT_GET_ANY_STATUS_OKAY(test_spi_loopback_slow)
+static struct spi_dt_spec spi_slow = SPI_DT_SPEC_GET(SPI_SLOW_DEV, SPI_OP(FRAME_SIZE), 0);
 
-#define STACK_SIZE (512 + CONFIG_TEST_EXTRA_STACK_SIZE)
-#define BUF_SIZE 18
-#define BUF2_SIZE 36
-#define BUF3_SIZE CONFIG_SPI_LARGE_BUFFER_SIZE
+static struct spi_dt_spec *loopback_specs[2] = {&spi_slow, &spi_fast};
+static char *spec_names[2] = {"SLOW", "FAST"};
+static int spec_idx;
 
+/*
+ ********************
+ * SPI test buffers *
+ ********************
+ */
 
 #if CONFIG_NOCACHE_MEMORY
 #define __NOCACHE	__attribute__((__section__(".nocache")))
@@ -69,26 +56,40 @@ static struct spi_dt_spec spi_slow = SPI_DT_SPEC_GET(SPI_SLOW_DEV, SPI_OP(FRAME_
 #define __NOCACHE
 #endif /* CONFIG_NOCACHE_MEMORY */
 
+#define BUF_SIZE 18
 static const char tx_data[BUF_SIZE] = "0123456789abcdef-\0";
-static __aligned(32) char buffer_tx[BUF_SIZE] __used __NOCACHE;
-static __aligned(32) char buffer_rx[BUF_SIZE] __used __NOCACHE;
+static __aligned(32) char buffer_tx[BUF_SIZE] __NOCACHE;
+static __aligned(32) char buffer_rx[BUF_SIZE] __NOCACHE;
+
+#define BUF2_SIZE 36
 static const char tx2_data[BUF2_SIZE] = "Thequickbrownfoxjumpsoverthelazydog\0";
-static __aligned(32) char buffer2_tx[BUF2_SIZE] __used __NOCACHE;
-static __aligned(32) char buffer2_rx[BUF2_SIZE] __used __NOCACHE;
+static __aligned(32) char buffer2_tx[BUF2_SIZE] __NOCACHE;
+static __aligned(32) char buffer2_rx[BUF2_SIZE] __NOCACHE;
+
+#define BUF3_SIZE CONFIG_SPI_LARGE_BUFFER_SIZE
 static const char large_tx_data[BUF3_SIZE] = "Thequickbrownfoxjumpsoverthelazydog\0";
-static __aligned(32) char large_buffer_tx[BUF3_SIZE] __used __NOCACHE;
-static __aligned(32) char large_buffer_rx[BUF3_SIZE] __used __NOCACHE;
+static __aligned(32) char large_buffer_tx[BUF3_SIZE] __NOCACHE;
+static __aligned(32) char large_buffer_rx[BUF3_SIZE] __NOCACHE;
+
+/*
+ ********************
+ * Helper functions *
+ ********************
+ */
 
 /*
  * We need 5x(buffer size) + 1 to print a comma-separated list of each
  * byte in hex, plus a null.
  */
-static uint8_t buffer_print_tx[BUF_SIZE * 5 + 1];
-static uint8_t buffer_print_rx[BUF_SIZE * 5 + 1];
+#define PRINT_BUF_SIZE(size) ((size * 5) + 1)
+
+static uint8_t buffer_print_tx[PRINT_BUF_SIZE(BUF_SIZE)];
+static uint8_t buffer_print_rx[PRINT_BUF_SIZE(BUF_SIZE)];
 
-static uint8_t buffer_print_tx2[BUF2_SIZE * 5 + 1];
-static uint8_t buffer_print_rx2[BUF2_SIZE * 5 + 1];
+static uint8_t buffer_print_tx2[PRINT_BUF_SIZE(BUF2_SIZE)];
+static uint8_t buffer_print_rx2[PRINT_BUF_SIZE(BUF2_SIZE)];
 
+/* function for displaying the data in the buffers */
 static void to_display_format(const uint8_t *src, size_t size, char *dst)
 {
 	size_t i;
@@ -98,477 +99,263 @@ static void to_display_format(const uint8_t *src, size_t size, char *dst)
 	}
 }
 
-/* test transferring different buffers on the same dma channels */
-static int spi_complete_multiple(struct spi_dt_spec *spec)
+/* just a wrapper of the driver transceive call with ztest error assert */
+static void spi_loopback_transceive(struct spi_dt_spec *const spec,
+				    const struct spi_buf_set *const tx,
+				    const struct spi_buf_set *const rx)
 {
-	struct spi_buf tx_bufs[2];
-	const struct spi_buf_set tx = {
-		.buffers = tx_bufs,
-		.count = ARRAY_SIZE(tx_bufs)
-	};
-
-	tx_bufs[0].buf = buffer_tx;
-	tx_bufs[0].len = BUF_SIZE;
-
-	tx_bufs[1].buf = buffer2_tx;
-	tx_bufs[1].len = BUF2_SIZE;
+	int ret = spi_transceive_dt(spec, tx, rx);
 
+	zassert_false(ret, "SPI transceive failed, code %d", ret);
+}
 
-	struct spi_buf rx_bufs[2];
-	const struct spi_buf_set rx = {
-		.buffers = rx_bufs,
-		.count = ARRAY_SIZE(rx_bufs)
-	};
+/* The most spi buf currently used by any test case is 4, change if needed */
+#define MAX_SPI_BUF_COUNT 4
+struct spi_buf tx_bufs_pool[MAX_SPI_BUF_COUNT];
+struct spi_buf rx_bufs_pool[MAX_SPI_BUF_COUNT];
 
-	rx_bufs[0].buf = buffer_rx;
-	rx_bufs[0].len = BUF_SIZE;
+/* A function for creating a spi_buf_set. Simply provide the spi_buf pool (either rx or tx),
+ * the number of bufs that will be in the set, and then an ordered list of pairs of buf
+ * pointer (void *) and buf size (size_t).
+ */
+static const struct spi_buf_set spi_loopback_setup_xfer(struct spi_buf *pool, size_t num_bufs, ...)
+{
+	struct spi_buf_set buf_set;
 
-	rx_bufs[1].buf = buffer2_rx;
-	rx_bufs[1].len = BUF2_SIZE;
+	zassert_true(num_bufs <= MAX_SPI_BUF_COUNT, "SPI xfer need more buf in test");
+	zassert_true(pool == tx_bufs_pool || pool == rx_bufs_pool, "Invalid spi buf pool");
 
-	int ret;
+	va_list args;
 
-	LOG_INF("Start complete multiple");
+	va_start(args, num_bufs);
 
-	ret = spi_transceive_dt(spec, &tx, &rx);
-	if (ret) {
-		LOG_ERR("Code %d", ret);
-		zassert_false(ret, "SPI transceive failed");
-		return ret;
+	for (int i = 0; i < num_bufs; i++) {
+		pool[i].buf = va_arg(args, void *);
+		pool[i].len = va_arg(args, size_t);
 	}
 
-	if (memcmp(buffer_tx, buffer_rx, BUF_SIZE)) {
-		to_display_format(buffer_tx, BUF_SIZE, buffer_print_tx);
-		to_display_format(buffer_rx, BUF_SIZE, buffer_print_rx);
-		LOG_ERR("Buffer contents are different: %s", buffer_print_tx);
-		LOG_ERR("                           vs: %s", buffer_print_rx);
-		zassert_false(1, "Buffer contents are different");
-		return -1;
-	}
+	va_end(args);
 
-	if (memcmp(buffer2_tx, buffer2_rx, BUF2_SIZE)) {
-		to_display_format(buffer2_tx, BUF2_SIZE, buffer_print_tx2);
-		to_display_format(buffer2_rx, BUF2_SIZE, buffer_print_rx2);
-		LOG_ERR("Buffer 2 contents are different: %s", buffer_print_tx2);
-		LOG_ERR("                             vs: %s", buffer_print_rx2);
-		zassert_false(1, "Buffer 2 contents are different");
-		return -1;
-	}
+	buf_set.buffers = pool;
+	buf_set.count = num_bufs;
 
-	LOG_INF("Passed");
-
-	return 0;
+	return buf_set;
 }
 
-static int spi_complete_loop(struct spi_dt_spec *spec)
+/* compare two buffers and print fail if they are not the same */
+static void spi_loopback_compare_bufs(const uint8_t *buf1, const uint8_t *buf2, size_t size,
+				      uint8_t *printbuf1, uint8_t *printbuf2)
 {
-	const struct spi_buf tx_bufs[] = {
-		{
-			.buf = buffer_tx,
-			.len = BUF_SIZE,
-		},
-	};
-	const struct spi_buf rx_bufs[] = {
-		{
-			.buf = buffer_rx,
-			.len = BUF_SIZE,
-		},
-	};
-	const struct spi_buf_set tx = {
-		.buffers = tx_bufs,
-		.count = ARRAY_SIZE(tx_bufs)
-	};
-	const struct spi_buf_set rx = {
-		.buffers = rx_bufs,
-		.count = ARRAY_SIZE(rx_bufs)
-	};
-
-	int ret;
-
-	LOG_INF("Start complete loop");
-
-	ret = spi_transceive_dt(spec, &tx, &rx);
-	if (ret) {
-		LOG_ERR("Code %d", ret);
-		zassert_false(ret, "SPI transceive failed");
-		return ret;
-	}
-
-	if (memcmp(buffer_tx, buffer_rx, BUF_SIZE)) {
-		to_display_format(buffer_tx, BUF_SIZE, buffer_print_tx);
-		to_display_format(buffer_rx, BUF_SIZE, buffer_print_rx);
-		LOG_ERR("Buffer contents are different: %s", buffer_print_tx);
-		LOG_ERR("                           vs: %s", buffer_print_rx);
-		zassert_false(1, "Buffer contents are different");
-		return -1;
+	if (memcmp(buf1, buf2, size)) {
+		to_display_format(buf1, size, printbuf1);
+		to_display_format(buf2, size, printbuf2);
+		TC_PRINT("Buffer contents are different:\n %s\nvs:\n %s\n",
+				buffer_print_tx, buffer_print_rx);
+		ztest_test_fail();
 	}
+}
 
-	LOG_INF("Passed");
+/*
+ **************
+ * Test cases *
+ **************
+ */
 
-	return 0;
+/* test transferring different buffers on the same dma channels */
+ZTEST(spi_loopback, test_spi_complete_multiple)
+{
+	struct spi_dt_spec *spec = loopback_specs[spec_idx];
+	const struct spi_buf_set tx = spi_loopback_setup_xfer(tx_bufs_pool, 2,
+							      buffer_tx, BUF_SIZE,
+							      buffer2_tx, BUF2_SIZE);
+	const struct spi_buf_set rx = spi_loopback_setup_xfer(rx_bufs_pool, 2,
+							      buffer_rx, BUF_SIZE,
+							      buffer2_rx, BUF2_SIZE);
+
+	spi_loopback_transceive(spec, &tx, &rx);
+
+	spi_loopback_compare_bufs(buffer_tx, buffer_rx, BUF_SIZE,
+				  buffer_print_tx, buffer_print_rx);
+	spi_loopback_compare_bufs(buffer2_tx, buffer2_rx, BUF2_SIZE,
+				  buffer_print_tx2, buffer_print_rx2);
 }
 
-static int spi_null_tx_buf(struct spi_dt_spec *spec)
+ZTEST(spi_loopback, test_spi_complete_loop)
 {
-	static const uint8_t EXPECTED_NOP_RETURN_BUF[BUF_SIZE] = { 0 };
-
-	(void)memset(buffer_rx, 0x77, BUF_SIZE);
-
-	const struct spi_buf tx_bufs[] = {
-		/* According to documentation, when sending NULL tx buf -
-		 *  NOP frames should be sent on MOSI line
-		 */
-		{
-			.buf = NULL,
-			.len = BUF_SIZE,
-		},
-	};
-	const struct spi_buf rx_bufs[] = {
-		{
-			.buf = buffer_rx,
-			.len = BUF_SIZE,
-		},
-	};
-	const struct spi_buf_set tx = {
-		.buffers = tx_bufs,
-		.count = ARRAY_SIZE(tx_bufs)
-	};
-	const struct spi_buf_set rx = {
-		.buffers = rx_bufs,
-		.count = ARRAY_SIZE(rx_bufs)
-	};
-
-	int ret;
+	struct spi_dt_spec *spec = loopback_specs[spec_idx];
+	const struct spi_buf_set tx = spi_loopback_setup_xfer(tx_bufs_pool, 1,
+							      buffer_tx, BUF_SIZE);
+	const struct spi_buf_set rx = spi_loopback_setup_xfer(rx_bufs_pool, 1,
+							      buffer_rx, BUF_SIZE);
 
-	LOG_INF("Start null tx");
+	spi_loopback_transceive(spec, &tx, &rx);
 
-	ret = spi_transceive_dt(spec, &tx, &rx);
-	if (ret) {
-		LOG_ERR("Code %d", ret);
-		zassert_false(ret, "SPI transceive failed");
-		return ret;
-	}
+	spi_loopback_compare_bufs(buffer_tx, buffer_rx, BUF_SIZE,
+				  buffer_print_tx, buffer_print_rx);
+}
 
+ZTEST(spi_loopback, test_spi_null_tx_buf)
+{
+	struct spi_dt_spec *spec = loopback_specs[spec_idx];
+	static const uint8_t expected_nop_return_buf[BUF_SIZE] = { 0 };
+	const struct spi_buf_set tx = spi_loopback_setup_xfer(tx_bufs_pool, 1,
+							      NULL, BUF_SIZE);
+	const struct spi_buf_set rx = spi_loopback_setup_xfer(rx_bufs_pool, 1,
+							      buffer_rx, BUF_SIZE);
 
-	if (memcmp(buffer_rx, EXPECTED_NOP_RETURN_BUF, BUF_SIZE)) {
-		to_display_format(buffer_rx, BUF_SIZE, buffer_print_rx);
-		LOG_ERR("Rx Buffer should contain NOP frames but got: %s",
-			buffer_print_rx);
-		zassert_false(1, "Buffer not as expected");
-		return -1;
-	}
+	(void)memset(buffer_rx, 0x77, BUF_SIZE);
 
-	LOG_INF("Passed");
+	spi_loopback_transceive(spec, &tx, &rx);
 
-	return 0;
+	spi_loopback_compare_bufs(expected_nop_return_buf, buffer_rx, BUF_SIZE,
+				  buffer_print_rx, buffer_print_rx);
 }
 
-static int spi_rx_half_start(struct spi_dt_spec *spec)
+ZTEST(spi_loopback, test_spi_rx_half_start)
 {
-	const struct spi_buf tx_bufs[] = {
-		{
-			.buf = buffer_tx,
-			.len = BUF_SIZE,
-		},
-	};
-	const struct spi_buf rx_bufs[] = {
-		{
-			.buf = buffer_rx,
-			.len = 8,
-		},
-	};
-	const struct spi_buf_set tx = {
-		.buffers = tx_bufs,
-		.count = ARRAY_SIZE(tx_bufs)
-	};
-	const struct spi_buf_set rx = {
-		.buffers = rx_bufs,
-		.count = ARRAY_SIZE(rx_bufs)
-	};
-	int ret;
-
-	LOG_INF("Start half start");
+	struct spi_dt_spec *spec = loopback_specs[spec_idx];
+	const struct spi_buf_set tx = spi_loopback_setup_xfer(tx_bufs_pool, 1,
+							      buffer_tx, BUF_SIZE);
+	const struct spi_buf_set rx = spi_loopback_setup_xfer(rx_bufs_pool, 1,
+							      buffer_rx, 8);
 
 	(void)memset(buffer_rx, 0, BUF_SIZE);
 
-	ret = spi_transceive_dt(spec, &tx, &rx);
-	if (ret) {
-		LOG_ERR("Code %d", ret);
-		zassert_false(ret, "SPI transceive failed");
-		return -1;
-	}
-
-	if (memcmp(buffer_tx, buffer_rx, 8)) {
-		to_display_format(buffer_tx, 8, buffer_print_tx);
-		to_display_format(buffer_rx, 8, buffer_print_rx);
-		LOG_ERR("Buffer contents are different: %s", buffer_print_tx);
-		LOG_ERR("                           vs: %s", buffer_print_rx);
-		zassert_false(1, "Buffer contents are different");
-		return -1;
-	}
+	spi_loopback_transceive(spec, &tx, &rx);
 
-	LOG_INF("Passed");
-
-	return 0;
+	spi_loopback_compare_bufs(buffer_tx, buffer_rx, 8,
+				  buffer_print_tx, buffer_print_rx);
 }
 
-static int spi_rx_half_end(struct spi_dt_spec *spec)
+ZTEST(spi_loopback, test_spi_rx_half_end)
 {
-	const struct spi_buf tx_bufs[] = {
-		{
-			.buf = buffer_tx,
-			.len = BUF_SIZE,
-		},
-	};
-	const struct spi_buf rx_bufs[] = {
-		{
-			.buf = NULL,
-			.len = 8,
-		},
-		{
-			.buf = buffer_rx,
-			.len = 8,
-		},
-	};
-	const struct spi_buf_set tx = {
-		.buffers = tx_bufs,
-		.count = ARRAY_SIZE(tx_bufs)
-	};
-	const struct spi_buf_set rx = {
-		.buffers = rx_bufs,
-		.count = ARRAY_SIZE(rx_bufs)
-	};
-	int ret;
-
 	if (IS_ENABLED(CONFIG_SPI_STM32_DMA)) {
-		LOG_INF("Skip half end");
-		return 0;
+		TC_PRINT("Skipped spi_rx_hald_end");
+		return;
 	}
 
-	LOG_INF("Start half end");
+	struct spi_dt_spec *spec = loopback_specs[spec_idx];
+	const struct spi_buf_set tx = spi_loopback_setup_xfer(tx_bufs_pool, 1,
+							      buffer_tx, BUF_SIZE);
+	const struct spi_buf_set rx = spi_loopback_setup_xfer(rx_bufs_pool, 2,
+							      NULL, 8,
+							      buffer_rx, 8);
 
 	(void)memset(buffer_rx, 0, BUF_SIZE);
 
-	ret = spi_transceive_dt(spec, &tx, &rx);
-	if (ret) {
-		LOG_ERR("Code %d", ret);
-		zassert_false(ret, "SPI transceive failed");
-		return -1;
-	}
-
-	if (memcmp(buffer_tx + 8, buffer_rx, 8)) {
-		to_display_format(buffer_tx + 8, 8, buffer_print_tx);
-		to_display_format(buffer_rx, 8, buffer_print_rx);
-		LOG_ERR("Buffer contents are different: %s", buffer_print_tx);
-		LOG_ERR("                           vs: %s", buffer_print_rx);
-		zassert_false(1, "Buffer contents are different");
-		return -1;
-	}
-
-	LOG_INF("Passed");
+	spi_loopback_transceive(spec, &tx, &rx);
 
-	return 0;
+	spi_loopback_compare_bufs(buffer_tx+8, buffer_rx, 8,
+				  buffer_print_tx, buffer_print_rx);
 }
 
-static int spi_rx_every_4(struct spi_dt_spec *spec)
+ZTEST(spi_loopback, test_spi_rx_every_4)
 {
-	const struct spi_buf tx_bufs[] = {
-		{
-			.buf = buffer_tx,
-			.len = BUF_SIZE,
-		},
-	};
-	const struct spi_buf rx_bufs[] = {
-		{
-			.buf = NULL,
-			.len = 4,
-		},
-		{
-			.buf = buffer_rx,
-			.len = 4,
-		},
-		{
-			.buf = NULL,
-			.len = 4,
-		},
-		{
-			.buf = buffer_rx + 4,
-			.len = 4,
-		},
-	};
-	const struct spi_buf_set tx = {
-		.buffers = tx_bufs,
-		.count = ARRAY_SIZE(tx_bufs)
-	};
-	const struct spi_buf_set rx = {
-		.buffers = rx_bufs,
-		.count = ARRAY_SIZE(rx_bufs)
+	if (IS_ENABLED(CONFIG_SPI_STM32_DMA) || IS_ENABLED(CONFIG_DSPI_MCUX_EDMA)) {
+		TC_PRINT("Skipped spi_rx_every_4");
+		return;
 	};
-	int ret;
 
-	if (IS_ENABLED(CONFIG_SPI_STM32_DMA)) {
-		LOG_INF("Skip every 4");
-		return 0;
-	}
-
-	if (IS_ENABLED(CONFIG_DSPI_MCUX_EDMA)) {
-		LOG_INF("Skip every 4");
-		return 0;
-	}
-
-	LOG_INF("Start every 4");
+	struct spi_dt_spec *spec = loopback_specs[spec_idx];
+	const struct spi_buf_set tx = spi_loopback_setup_xfer(tx_bufs_pool, 1,
+							      buffer_tx, BUF_SIZE);
+	const struct spi_buf_set rx = spi_loopback_setup_xfer(rx_bufs_pool, 4,
+							      NULL, 4,
+							      buffer_rx, 4,
+							      NULL, 4,
+							      buffer_rx+4, 4);
 
 	(void)memset(buffer_rx, 0, BUF_SIZE);
 
-	ret = spi_transceive_dt(spec, &tx, &rx);
-	if (ret) {
-		LOG_ERR("Code %d", ret);
-		zassert_false(ret, "SPI transceive failed");
-		return -1;
-	}
-
-	if (memcmp(buffer_tx + 4, buffer_rx, 4)) {
-		to_display_format(buffer_tx + 4, 4, buffer_print_tx);
-		to_display_format(buffer_rx, 4, buffer_print_rx);
-		LOG_ERR("Buffer contents are different: %s", buffer_print_tx);
-		LOG_ERR("                           vs: %s", buffer_print_rx);
-		zassert_false(1, "Buffer contents are different");
-		return -1;
-	} else if (memcmp(buffer_tx + 12, buffer_rx + 4, 4)) {
-		to_display_format(buffer_tx + 12, 4, buffer_print_tx);
-		to_display_format(buffer_rx + 4, 4, buffer_print_rx);
-		LOG_ERR("Buffer contents are different: %s", buffer_print_tx);
-		LOG_ERR("                           vs: %s", buffer_print_rx);
-		zassert_false(1, "Buffer contents are different");
-		return -1;
-	}
-
-	LOG_INF("Passed");
+	spi_loopback_transceive(spec, &tx, &rx);
 
-	return 0;
+	spi_loopback_compare_bufs(buffer_tx+4, buffer_rx, 4,
+				  buffer_print_tx, buffer_print_rx);
+	spi_loopback_compare_bufs(buffer_tx+12, buffer_rx+4, 4,
+				  buffer_print_tx, buffer_print_rx);
 }
 
-static int spi_rx_bigger_than_tx(struct spi_dt_spec *spec)
+ZTEST(spi_loopback, test_spi_rx_bigger_than_tx)
 {
+	if (IS_ENABLED(CONFIG_SPI_STM32_DMA) || IS_ENABLED(CONFIG_DSPI_MCUX_EDMA)) {
+		TC_PRINT("Skipped spi_rx_bigger_than_tx");
+		return;
+	}
+
+	struct spi_dt_spec *spec = loopback_specs[spec_idx];
 	const uint32_t tx_buf_size = 8;
 
 	BUILD_ASSERT(tx_buf_size < BUF_SIZE,
 		"Transmit buffer is expected to be smaller than the receive buffer");
 
-	const struct spi_buf tx_bufs[] = {
-		{
-			.buf = buffer_tx,
-			.len = tx_buf_size,
-		},
-	};
-	const struct spi_buf rx_bufs[] = {
-		{
-			.buf = buffer_rx,
-			.len = BUF_SIZE,
-		}
-	};
-	const struct spi_buf_set tx = {
-		.buffers = tx_bufs,
-		.count = ARRAY_SIZE(tx_bufs)
-	};
-	const struct spi_buf_set rx = {
-		.buffers = rx_bufs,
-		.count = ARRAY_SIZE(rx_bufs)
-	};
-	int ret;
-
-	if (IS_ENABLED(CONFIG_SPI_STM32_DMA)) {
-		LOG_INF("Skip rx bigger than tx");
-		return 0;
-	}
-
-	if (IS_ENABLED(CONFIG_DSPI_MCUX_EDMA)) {
-		LOG_INF("Skip rx bigger than tx");
-		return 0;
-	}
-
-	LOG_INF("Start rx bigger than tx");
+	const struct spi_buf_set tx = spi_loopback_setup_xfer(tx_bufs_pool, 1,
+							      buffer_tx, tx_buf_size);
+	const struct spi_buf_set rx = spi_loopback_setup_xfer(rx_bufs_pool, 1,
+							      buffer_rx, BUF_SIZE);
 
 	(void)memset(buffer_rx, 0xff, BUF_SIZE);
 
-	ret = spi_transceive_dt(spec, &tx, &rx);
-	if (ret) {
-		LOG_ERR("Code %d", ret);
-		zassert_false(ret, "SPI transceive failed");
-		return -1;
-	}
+	spi_loopback_transceive(spec, &tx, &rx);
 
-	if (memcmp(buffer_tx, buffer_rx, tx_buf_size)) {
-		to_display_format(buffer_tx, tx_buf_size, buffer_print_tx);
-		to_display_format(buffer_rx, tx_buf_size, buffer_print_rx);
-		LOG_ERR("Buffer contents are different: %s", buffer_print_tx);
-		LOG_ERR("                           vs: %s", buffer_print_rx);
-		zassert_false(1, "Buffer contents are different");
-		return -1;
-	}
+	spi_loopback_compare_bufs(buffer_tx, buffer_rx, tx_buf_size,
+				  buffer_print_tx, buffer_print_rx);
 
-	const uint8_t all_zeroes_buf[BUF_SIZE] = {0};
+	static const uint8_t all_zeroes_buf[BUF_SIZE] = {0};
 
-	if (memcmp(all_zeroes_buf, buffer_rx + tx_buf_size, BUF_SIZE - tx_buf_size)) {
-		to_display_format(
-			buffer_rx + tx_buf_size,  BUF_SIZE - tx_buf_size, buffer_print_tx);
-
-		to_display_format(
-			all_zeroes_buf, BUF_SIZE - tx_buf_size, buffer_print_rx);
-
-		LOG_ERR("Buffer contents are different: %s", buffer_print_tx);
-		LOG_ERR("                           vs: %s", buffer_print_rx);
-		zassert_false(1, "Buffer contents are different");
-		return -1;
-	}
-
-	LOG_INF("Passed");
-
-	return 0;
+	spi_loopback_compare_bufs(all_zeroes_buf, buffer_rx + tx_buf_size, BUF_SIZE - tx_buf_size,
+				  buffer_print_tx, buffer_print_rx);
 }
 
 /* test transferring different buffers on the same dma channels */
-static int spi_complete_large_transfers(struct spi_dt_spec *spec)
+ZTEST(spi_loopback, test_spi_complete_large_transfers)
 {
-	struct spi_buf tx_bufs;
-	const struct spi_buf_set tx = {
-		.buffers = &tx_bufs,
-		.count = 1
-	};
+	struct spi_dt_spec *spec = loopback_specs[spec_idx];
+	const struct spi_buf_set tx = spi_loopback_setup_xfer(tx_bufs_pool, 1,
+							      large_buffer_tx, BUF3_SIZE);
+	const struct spi_buf_set rx = spi_loopback_setup_xfer(rx_bufs_pool, 1,
+							      large_buffer_rx, BUF3_SIZE);
 
-	tx_bufs.buf = large_buffer_tx;
-	tx_bufs.len = BUF3_SIZE;
+	spi_loopback_transceive(spec, &tx, &rx);
 
+	zassert_false(memcmp(large_buffer_tx, large_buffer_rx, BUF3_SIZE),
+			"Large Buffer contents are different");
+}
 
-	struct spi_buf rx_bufs;
-	const struct spi_buf_set rx = {
-		.buffers = &rx_bufs,
-		.count = 1
-	};
+ZTEST(spi_loopback, test_spi_null_tx_buf_set)
+{
+	struct spi_dt_spec *spec = loopback_specs[spec_idx];
+	static const uint8_t expected_nop_return_buf[BUF_SIZE] = { 0 };
+	const struct spi_buf_set rx = spi_loopback_setup_xfer(rx_bufs_pool, 1,
+							      buffer_rx, BUF_SIZE);
 
-	rx_bufs.buf = large_buffer_rx;
-	rx_bufs.len = BUF3_SIZE;
+	(void)memset(buffer_rx, 0x77, BUF_SIZE);
 
-	int ret;
+	spi_loopback_transceive(spec, NULL, &rx);
 
-	LOG_INF("Start complete large transfers");
+	spi_loopback_compare_bufs(expected_nop_return_buf, buffer_rx, BUF_SIZE,
+				  buffer_print_rx, buffer_print_rx);
+}
 
-	ret = spi_transceive_dt(spec, &tx, &rx);
-	if (ret) {
-		LOG_ERR("Code %d", ret);
-		zassert_false(ret, "SPI transceive failed");
-		return ret;
-	}
+ZTEST(spi_loopback, test_spi_null_rx_buf_set)
+{
+	struct spi_dt_spec *spec = loopback_specs[spec_idx];
+	const struct spi_buf_set tx = spi_loopback_setup_xfer(tx_bufs_pool, 1,
+							      NULL, BUF_SIZE);
 
-	if (memcmp(large_buffer_tx, large_buffer_rx, BUF3_SIZE)) {
-		zassert_false(1, "Large Buffer contents are different");
-		return -1;
-	}
+	spi_loopback_transceive(spec, &tx, NULL);
+}
+
+ZTEST(spi_loopback, test_nop_nil_bufs)
+{
+	struct spi_dt_spec *spec = loopback_specs[spec_idx];
+	const struct spi_buf_set tx = spi_loopback_setup_xfer(tx_bufs_pool, 1, NULL, 0);
+	const struct spi_buf_set rx = spi_loopback_setup_xfer(rx_bufs_pool, 1, NULL, 0);
 
-	LOG_INF("Passed");
+	spi_loopback_transceive(spec, &tx, &rx);
 
-	return 0;
+	/* nothing really to check here, check is done in spi_loopback_transceive */
 }
+
 #if (CONFIG_SPI_ASYNC)
 static struct k_poll_signal async_sig = K_POLL_SIGNAL_INITIALIZER(async_sig);
 static struct k_poll_event async_evt =
@@ -576,26 +363,24 @@ static struct k_poll_event async_evt =
 				 K_POLL_MODE_NOTIFY_ONLY,
 				 &async_sig);
 static K_SEM_DEFINE(caller, 0, 1);
-K_THREAD_STACK_DEFINE(spi_async_stack, STACK_SIZE);
+static K_SEM_DEFINE(start_async, 0, 1);
 static int result = 1;
 
 static void spi_async_call_cb(void *p1,
 			      void *p2,
 			      void *p3)
 {
-	ARG_UNUSED(p1);
-	ARG_UNUSED(p2);
 	ARG_UNUSED(p3);
 
 	struct k_poll_event *evt = p1;
 	struct k_sem *caller_sem = p2;
-	int ret;
 
-	LOG_DBG("Polling...");
+	TC_PRINT("Polling...");
 
 	while (1) {
-		ret = k_poll(evt, 1, K_MSEC(2000));
-		zassert_false(ret, "one or more events are not ready");
+		k_sem_take(&start_async, K_FOREVER);
+
+		zassert_false(k_poll(evt, 1, K_MSEC(2000)), "one or more events are not ready");
 
 		result = evt->signal->result;
 		k_sem_give(caller_sem);
@@ -606,132 +391,125 @@ static void spi_async_call_cb(void *p1,
 	}
 }
 
-static int spi_async_call(struct spi_dt_spec *spec)
+ZTEST(spi_loopback, test_spi_async_call)
 {
-	const struct spi_buf tx_bufs[] = {
-		{
-			.buf = buffer_tx,
-			.len = BUF_SIZE,
-		},
-		{
-			.buf = buffer2_tx,
-			.len = BUF2_SIZE,
-		},
-		{
-			.buf = large_buffer_tx,
-			.len = BUF3_SIZE,
-		},
-	};
-	const struct spi_buf rx_bufs[] = {
-		{
-			.buf = buffer_rx,
-			.len = BUF_SIZE,
-		},
-		{
-			.buf = buffer2_rx,
-			.len = BUF2_SIZE,
-		},
-		{
-			.buf = large_buffer_rx,
-			.len = BUF3_SIZE,
-		},
-	};
-	const struct spi_buf_set tx = {
-		.buffers = tx_bufs,
-		.count = ARRAY_SIZE(tx_bufs)
-	};
-	const struct spi_buf_set rx = {
-		.buffers = rx_bufs,
-		.count = ARRAY_SIZE(rx_bufs)
-	};
-	int ret;
+	struct spi_dt_spec *spec = loopback_specs[spec_idx];
+	const struct spi_buf_set tx = spi_loopback_setup_xfer(tx_bufs_pool, 3,
+							      buffer_tx, BUF_SIZE,
+							      buffer2_tx, BUF2_SIZE,
+							      large_buffer_tx, BUF3_SIZE);
+	const struct spi_buf_set rx = spi_loopback_setup_xfer(rx_bufs_pool, 3,
+							      buffer_rx, BUF_SIZE,
+							      buffer2_rx, BUF2_SIZE,
+							      large_buffer_rx, BUF3_SIZE);
 
-	LOG_INF("Start async call");
 	memset(buffer_rx, 0, sizeof(buffer_rx));
 	memset(buffer2_rx, 0, sizeof(buffer2_rx));
 	memset(large_buffer_rx, 0, sizeof(large_buffer_rx));
 
-	ret = spi_transceive_signal(spec->bus, &spec->config, &tx, &rx, &async_sig);
-	if (ret == -ENOTSUP) {
-		LOG_DBG("Not supported");
-		return 0;
-	}
-
-	if (ret) {
-		LOG_ERR("Code %d", ret);
-		zassert_false(ret, "SPI transceive failed");
-		return -1;
-	}
+	k_sem_give(&start_async);
 
-	k_sem_take(&caller, K_FOREVER);
+	int ret = spi_transceive_signal(spec->bus, &spec->config, &tx, &rx, &async_sig);
 
-	if (result) {
-		LOG_ERR("Call code %d", ret);
-		zassert_false(result, "SPI transceive failed");
-		return -1;
+	if (ret == -ENOTSUP) {
+		TC_PRINT("Skipping ASYNC test");
+		return;
 	}
 
-	if (memcmp(buffer_tx, buffer_rx, BUF_SIZE)) {
-		to_display_format(buffer_tx, BUF_SIZE, buffer_print_tx);
-		to_display_format(buffer_rx, BUF_SIZE, buffer_print_rx);
-		LOG_ERR("Buffer contents are different: %s", buffer_print_tx);
-		LOG_ERR("                           vs: %s", buffer_print_rx);
-		zassert_false(1, "Buffer contents are different");
-		return -1;
-	}
+	zassert_false(ret, "SPI transceive failed, code %d", ret);
 
-	if (memcmp(buffer2_tx, buffer2_rx, BUF2_SIZE)) {
-		to_display_format(buffer2_tx, BUF2_SIZE, buffer_print_tx2);
-		to_display_format(buffer2_rx, BUF2_SIZE, buffer_print_rx2);
-		LOG_ERR("Buffer 2 contents are different: %s", buffer_print_tx2);
-		LOG_ERR("                             vs: %s", buffer_print_rx2);
-		zassert_false(1, "Buffer 2 contents are different");
-		return -1;
-	}
+	k_sem_take(&caller, K_FOREVER);
 
-	if (memcmp(large_buffer_tx, large_buffer_rx, BUF3_SIZE)) {
-		zassert_false(1, "Buffer 3 contents are different");
-		return -1;
-	}
+	zassert_false(result, "SPI async transceive failed, result %d", result);
 
-	LOG_INF("Passed");
+	spi_loopback_compare_bufs(buffer_tx, buffer_rx, BUF_SIZE,
+				  buffer_print_tx, buffer_print_rx);
+	spi_loopback_compare_bufs(buffer2_tx, buffer2_rx, BUF2_SIZE,
+				  buffer_print_tx2, buffer_print_rx2);
 
-	return 0;
+	zassert_false(memcmp(large_buffer_tx, large_buffer_rx, BUF3_SIZE),
+			"Large Buffer contents are different");
 }
 #endif
 
-static int spi_resource_lock_test(struct spi_dt_spec *lock_spec,
-				  struct spi_dt_spec *try_spec)
+ZTEST(spi_extra_api_features, test_spi_lock_release)
 {
+	const struct spi_buf_set tx = spi_loopback_setup_xfer(tx_bufs_pool, 1,
+							      buffer_tx, BUF_SIZE);
+	const struct spi_buf_set rx = spi_loopback_setup_xfer(rx_bufs_pool, 1,
+							      NULL, BUF_SIZE);
+	struct spi_dt_spec *lock_spec = &spi_slow;
+	struct spi_dt_spec *try_spec = &spi_fast;
+
 	lock_spec->config.operation |= SPI_LOCK_ON;
 
-	if (spi_complete_loop(lock_spec)) {
-		return -1;
-	}
+	spi_loopback_transceive(lock_spec, &tx, &rx);
 
-	if (spi_release_dt(lock_spec)) {
-		LOG_ERR("Deadlock now?");
-		zassert_false(1, "SPI release failed");
-		return -1;
-	}
+	zassert_false(spi_release_dt(lock_spec), "SPI release failed");
 
-	if (spi_complete_loop(try_spec)) {
-		return -1;
-	}
+	spi_loopback_transceive(try_spec, &tx, &rx);
 
-	return 0;
+	lock_spec->config.operation &= ~SPI_LOCK_ON;
 }
 
-ZTEST(spi_loopback, test_spi_loopback)
+/*
+ *************************
+ * Test suite definition *
+ *************************
+ */
+
+static void *spi_loopback_common_setup(void)
 {
-#if (CONFIG_SPI_ASYNC)
-	struct k_thread async_thread;
-	k_tid_t async_thread_id;
-#endif
+	memset(buffer_tx, 0, sizeof(buffer_tx));
+	memcpy(buffer_tx, tx_data, sizeof(tx_data));
+	memset(buffer2_tx, 0, sizeof(buffer2_tx));
+	memcpy(buffer2_tx, tx2_data, sizeof(tx2_data));
+	memset(large_buffer_tx, 0, sizeof(large_buffer_tx));
+	memcpy(large_buffer_tx, large_tx_data, sizeof(large_tx_data));
+	return NULL;
+}
+
+static void *spi_loopback_setup(void)
+{
+	printf("Testing loopback spec: %s\n", spec_names[spec_idx]);
+	spi_loopback_common_setup();
+	return NULL;
+}
+
+static void run_after_suite(void *unused)
+{
+	spec_idx++;
+}
+
+static void run_after_lock(void *unused)
+{
+	spi_release_dt(&spi_fast);
+	spi_release_dt(&spi_slow);
+	spi_slow.config.operation &= ~SPI_LOCK_ON;
+	spi_fast.config.operation &= ~SPI_LOCK_ON;
+}
+
+ZTEST_SUITE(spi_loopback, NULL, spi_loopback_setup, NULL, NULL, run_after_suite);
+ZTEST_SUITE(spi_extra_api_features, NULL, spi_loopback_common_setup, NULL, NULL, run_after_lock);
+
+struct k_thread async_thread;
+k_tid_t async_thread_id;
+#define STACK_SIZE (512 + CONFIG_TEST_EXTRA_STACK_SIZE)
+K_THREAD_STACK_DEFINE(spi_async_stack, STACK_SIZE);
 
-	LOG_INF("SPI test on buffers TX/RX %p/%p" FRAME_SIZE_STR DMA_ENABLED_STR,
+void test_main(void)
+{
+	printf("SPI test on buffers TX/RX %p/%p, frame size = %d"
+#ifdef CONFIG_DMA
+		", DMA enabled"
+#ifndef CONFIG_NOCACHE_MEMORY
+		" (without CONFIG_NOCACHE_MEMORY)"
+#endif
+#endif /* CONFIG_DMA */
+			"\n",
 			buffer_tx,
-			buffer_rx);
+			buffer_rx,
+			FRAME_SIZE);
 
 #if (CONFIG_SPI_ASYNC)
 	async_thread_id = k_thread_create(&async_thread,
@@ -740,66 +518,12 @@ ZTEST(spi_loopback, test_spi_loopback)
 					  &async_evt, &caller, NULL,
 					  K_PRIO_COOP(7), 0, K_NO_WAIT);
 #endif
-	zassert_true(spi_is_ready_dt(&spi_slow), "Slow spi lookback device is not ready");
-
-	LOG_INF("SPI test slow config");
-
-	if (spi_complete_multiple(&spi_slow) ||
-	    spi_complete_loop(&spi_slow) ||
-	    spi_null_tx_buf(&spi_slow) ||
-	    spi_rx_half_start(&spi_slow) ||
-	    spi_rx_half_end(&spi_slow) ||
-	    spi_rx_every_4(&spi_slow) ||
-	    spi_rx_bigger_than_tx(&spi_slow) ||
-	    spi_complete_large_transfers(&spi_slow)
-#if (CONFIG_SPI_ASYNC)
-	    || spi_async_call(&spi_slow)
-#endif
-	    ) {
-		goto end;
-	}
-
-	zassert_true(spi_is_ready_dt(&spi_fast), "Fast spi lookback device is not ready");
-
-	LOG_INF("SPI test fast config");
-
-	if (spi_complete_multiple(&spi_fast) ||
-	    spi_complete_loop(&spi_fast) ||
-	    spi_null_tx_buf(&spi_fast) ||
-	    spi_rx_half_start(&spi_fast) ||
-	    spi_rx_half_end(&spi_fast) ||
-	    spi_rx_every_4(&spi_fast) ||
-	    spi_rx_bigger_than_tx(&spi_fast) ||
-	    spi_complete_large_transfers(&spi_fast)
-#if (CONFIG_SPI_ASYNC)
-	    || spi_async_call(&spi_fast)
-#endif
-	    ) {
-		goto end;
-	}
 
-	if (spi_resource_lock_test(&spi_slow, &spi_fast)) {
-		goto end;
-	}
+	ztest_run_all(NULL, false, ARRAY_SIZE(loopback_specs), 1);
 
-	LOG_INF("All tx/rx passed");
-end:
 #if (CONFIG_SPI_ASYNC)
 	k_thread_abort(async_thread_id);
-#else
-	;
 #endif
-}
 
-static void *spi_loopback_setup(void)
-{
-	memset(buffer_tx, 0, sizeof(buffer_tx));
-	memcpy(buffer_tx, tx_data, sizeof(tx_data));
-	memset(buffer2_tx, 0, sizeof(buffer2_tx));
-	memcpy(buffer2_tx, tx2_data, sizeof(tx2_data));
-	memset(large_buffer_tx, 0, sizeof(large_buffer_tx));
-	memcpy(large_buffer_tx, large_tx_data, sizeof(large_tx_data));
-	return NULL;
+	ztest_verify_all_test_suites_ran();
 }
-
-ZTEST_SUITE(spi_loopback, NULL, spi_loopback_setup, NULL, NULL, NULL);
diff --git a/tests/drivers/spi/spi_loopback/testcase.yaml b/tests/drivers/spi/spi_loopback/testcase.yaml
index d0bdc59a8df..bf65221f61d 100644
--- a/tests/drivers/spi/spi_loopback/testcase.yaml
+++ b/tests/drivers/spi/spi_loopback/testcase.yaml
@@ -30,6 +30,7 @@ tests:
   drivers.spi.loopback.rtio:
     extra_configs:
       - CONFIG_SPI_RTIO=y
+      - CONFIG_SPI_RTIO_FALLBACK_MSGS=5
     platform_allow:
       - robokit1
       - mimxrt1170_evk/mimxrt1176/cm7
@@ -65,6 +66,7 @@ tests:
     extra_args: EXTRA_CONF_FILE="overlay-stm32-spi-dma.conf"
     platform_allow:
       - b_u585i_iot02a
+      - nucleo_c071rb
       - nucleo_g474re
       - nucleo_f207zg
       - nucleo_f429zi
@@ -120,6 +122,7 @@ tests:
     extra_args: EXTRA_CONF_FILE="overlay-stm32-spi-interrupt.conf"
     platform_allow:
       - b_u585i_iot02a
+      - nucleo_c071rb
       - nucleo_f207zg
       - nucleo_f429zi
       - nucleo_f746zg
@@ -167,41 +170,64 @@ tests:
     integration_platforms:
       - gd32f403z_eval
   drivers.spi.pl022_spi_interrupt.loopback:
+    extra_args: DTC_OVERLAY_FILE="boards/rpi_pico_pl022.overlay"
     extra_configs:
       - CONFIG_SPI_PL022_INTERRUPT=y
       - CONFIG_SPI_PL022_DMA=n
-    platform_allow: rpi_pico
+    platform_allow:
+      - rpi_pico
+      - pico_plus2/rp2350b/m33
   drivers.spi.pl022_spi_dma.loopback:
+    extra_args: DTC_OVERLAY_FILE="boards/rpi_pico_pl022_dma.overlay"
     extra_configs:
       - CONFIG_SPI_PL022_INTERRUPT=n
       - CONFIG_SPI_PL022_DMA=y
       - CONFIG_DMA=y
-    platform_allow: rpi_pico
+    platform_allow:
+      - rpi_pico
+      - pico_plus2/rp2350b/m33
   drivers.spi.pl022_spi_dma_and_interrupt.loopback:
+    extra_args: DTC_OVERLAY_FILE="boards/rpi_pico_pl022_dma.overlay"
     extra_configs:
       - CONFIG_SPI_PL022_INTERRUPT=y
       - CONFIG_SPI_PL022_DMA=y
       - CONFIG_DMA=y
-    platform_allow: rpi_pico
+    platform_allow:
+      - rpi_pico
+      - pico_plus2/rp2350b/m33
   drivers.spi.pl022_spi_dma_no_dma_props.loopback:
-    extra_args: DTC_OVERLAY_FILE="boards/rpi_pico_delete_dma_props.overlay"
+    extra_args: DTC_OVERLAY_FILE="boards/rpi_pico_pl022.overlay"
     extra_configs:
       - CONFIG_SPI_PL022_INTERRUPT=n
       - CONFIG_SPI_PL022_DMA=y
       - CONFIG_DMA=y
-    platform_allow: rpi_pico
+    platform_allow:
+      - rpi_pico
+      - pico_plus2/rp2350b/m33
   drivers.spi.pl022_spi_dma_and_interrupt_no_dma_props.loopback:
-    extra_args: DTC_OVERLAY_FILE="boards/rpi_pico_delete_dma_props.overlay"
+    extra_args: DTC_OVERLAY_FILE="boards/rpi_pico_pl022.overlay"
     extra_configs:
       - CONFIG_SPI_PL022_INTERRUPT=y
       - CONFIG_SPI_PL022_DMA=y
       - CONFIG_DMA=y
+    platform_allow:
+      - rpi_pico
+      - pico_plus2/rp2350b/m33
+  drivers.spi.pio_spi.loopback:
+    extra_args:
+      - DTC_OVERLAY_FILE="boards/rpi_pico_pio.overlay"
+      - EXTRA_CONF_FILE="overlay-rpi-pico-pio.conf"
     platform_allow: rpi_pico
   drivers.spi.mcux_flexio_spi.loopback:
     extra_args: DTC_OVERLAY_FILE="overlay-mcux-flexio-spi.overlay"
     filter: CONFIG_DT_HAS_NXP_FLEXIO_ENABLED and
             CONFIG_DT_HAS_NXP_FLEXIO_SPI_ENABLED
     platform_allow: mimxrt1064_evk
+  drivers.spi.mimxrt1040evk_flexio_spi.loopback:
+    extra_args: DTC_OVERLAY_FILE="boards/mimxrt1040_evk_flexio_spi.overlay"
+    filter: CONFIG_DT_HAS_NXP_FLEXIO_ENABLED and
+            CONFIG_DT_HAS_NXP_FLEXIO_SPI_ENABLED
+    platform_allow: mimxrt1040_evk
   drivers.spi.nrf54h_fast_8mhz:
     extra_args: DTC_OVERLAY_FILE="boards/nrf54h20dk_nrf54h20_cpuapp_fast.overlay"
     platform_allow:
@@ -223,16 +249,19 @@ tests:
     platform_allow:
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
   drivers.spi.nrf54l_16mhz:
     extra_args: EXTRA_DTC_OVERLAY_FILE="boards/nrf_at_16mhz.overlay"
     platform_allow:
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
   drivers.spi.nrf54l_32mhz:
     extra_args: EXTRA_DTC_OVERLAY_FILE="boards/nrf_at_32mhz.overlay"
     platform_allow:
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
   drivers.spi.ke1xz_flexio_spi.loopback:
     extra_args: DTC_OVERLAY_FILE="boards/frdm_ke1xz_flexio_spi.overlay"
     filter: CONFIG_DT_HAS_NXP_FLEXIO_ENABLED and
@@ -251,7 +280,7 @@ tests:
       - s32z2xxdc2/s32z270/rtu1
   drivers.spi.max32_spi_rtio.loopback:
     extra_args:
-      - OVERLAY_CONFIG="overlay-max32-spi-rtio.conf"
+      - EXTRA_CONF_FILE="overlay-max32-spi-rtio.conf"
     filter: CONFIG_SOC_FAMILY_MAX32
     platform_allow:
       - apard32690/max32690/m4
@@ -260,3 +289,19 @@ tests:
       - CONFIG_PM_DEVICE=y
       - CONFIG_PM_DEVICE_RUNTIME=y
     filter: CONFIG_SOC_FAMILY_NORDIC_NRF
+  drivers.spi.silabs_s2.loopback.no_async:
+    filter: CONFIG_SOC_FAMILY_SILABS_S2
+    platform_allow:
+      - xg24_rb4187c
+      - xg29_rb4412a
+    extra_configs:
+      - CONFIG_SPI_SILABS_EUSART_DMA=n
+      - CONFIG_SPI_ASYNC=n
+  drivers.spi.silabs_s2.loopback.dma.no_async:
+    filter: CONFIG_SOC_FAMILY_SILABS_S2
+    platform_allow:
+      - xg24_rb4187c
+      - xg29_rb4412a
+    extra_configs:
+      - CONFIG_SPI_SILABS_EUSART_DMA=y
+      - CONFIG_SPI_ASYNC=n
diff --git a/tests/drivers/stepper/drv8424/api/CMakeLists.txt b/tests/drivers/stepper/drv8424/api/CMakeLists.txt
deleted file mode 100644
index 81e4018657b..00000000000
--- a/tests/drivers/stepper/drv8424/api/CMakeLists.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright (c) 2024 Navimatix GmbH
-# SPDX-License-Identifier: Apache-2.0
-
-cmake_minimum_required(VERSION 3.20.0)
-
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(stepper_drv8424_api)
-target_sources(app PRIVATE
-	src/main.c
-)
diff --git a/tests/drivers/stepper/drv8424/api/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay b/tests/drivers/stepper/drv8424/api/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay
deleted file mode 100644
index cb4082a32dd..00000000000
--- a/tests/drivers/stepper/drv8424/api/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (c) 2024 Navimatix GmbH
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/dt-bindings/gpio/gpio.h>
-
-/ {
-	zephyr,user {
-		stepper-motors = <&drv8424 0>;
-	};
-};
-
-&lpi2c1 {
-	status = "okay";
-
-	mikroe_stepper_gpios: mikroe_stepper_ctrl_tca9538a@70 {
-		status = "okay";
-		compatible = "ti,tca9538";
-
-		reg = <0x70>;
-
-		gpio-controller;
-		ngpios = <8>;
-		#gpio-cells = <2>;
-
-		gpio-reserved-ranges = <7 1>;
-
-		gpio-line-names =
-			"M0",
-			"M1",
-			"DEC0",
-			"DEC1",
-			"TOFF",
-			"STP",
-			"DIR";
-	};
-};
-
-/ {
-	drv8424: drv8424 {
-		status = "okay";
-		compatible = "ti,drv8424";
-
-		dir-gpios = <&arduino_header 9 0>; /* D3 */
-		step-gpios = <&arduino_header 10 0>; /* D4 */
-		sleep-gpios = <&arduino_header 8 GPIO_ACTIVE_LOW>; /* D2 */
-		en-gpios  = <&arduino_header 11 0>; /* D5 */
-		m0-gpios = <&mikroe_stepper_gpios 0 0>;
-		m1-gpios = <&mikroe_stepper_gpios 1 0>;
-		counter = <&pit0_channel0>;
-
-		#address-cells = <1>;
-		#size-cells = <0>;
-		#stepper-motor-cells = <0>;
-	};
-};
-
-&pit0_channel0 {
-	status = "okay";
-};
diff --git a/tests/drivers/stepper/drv8424/api/boards/native_sim.overlay b/tests/drivers/stepper/drv8424/api/boards/native_sim.overlay
deleted file mode 100644
index 39352f817f1..00000000000
--- a/tests/drivers/stepper/drv8424/api/boards/native_sim.overlay
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2024 Navimatix GmbH
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/dt-bindings/gpio/gpio.h>
-
-/ {
-	drv8424: drv8424 {
-		status = "okay";
-		compatible = "ti,drv8424";
-
-
-		dir-gpios = <&gpio1 0 0>; /* D3 */
-		step-gpios = <&gpio1 1 0>; /* D4 */
-		sleep-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* D2 */
-		en-gpios = <&gpio2 1 0>; /* 5 */
-		m0-gpios = <&gpio3 0 0>;
-		m1-gpios = <&gpio3 1 0>;
-		counter = <&counter0>;
-
-		#address-cells = <1>;
-		#size-cells = <0>;
-		#stepper-motor-cells = <0>;
-	};
-
-	gpio1: gpio1 {
-		compatible = "zephyr,gpio-emul";
-		#gpio-cells = <0x2>;
-		status = "okay";
-		gpio-controller;
-	};
-
-	gpio2: gpio2 {
-		compatible = "zephyr,gpio-emul";
-		#gpio-cells = <0x2>;
-		status = "okay";
-		gpio-controller;
-	};
-
-	gpio3: gpio3 {
-		compatible = "zephyr,gpio-emul";
-		#gpio-cells = <0x2>;
-		status = "okay";
-		gpio-controller;
-	};
-};
diff --git a/tests/drivers/stepper/drv8424/api/boards/nucleo_f767zi.overlay b/tests/drivers/stepper/drv8424/api/boards/nucleo_f767zi.overlay
deleted file mode 100644
index ad13d43bead..00000000000
--- a/tests/drivers/stepper/drv8424/api/boards/nucleo_f767zi.overlay
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2024 Navimatix GmbH
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/dt-bindings/gpio/gpio.h>
-
-/ {
-	zephyr,user {
-		stepper-motors = <&drv8424 0>;
-	};
-};
-
-&i2c1 {
-	status = "okay";
-
-	mikroe_stepper_gpios: mikroe_stepper_ctrl_tca9538a@70 {
-		status = "okay";
-		compatible = "ti,tca9538";
-
-		reg = <0x70>;
-
-		gpio-controller;
-		ngpios = <8>;
-		#gpio-cells = <2>;
-
-		gpio-reserved-ranges = <7 1>;
-
-		gpio-line-names =
-			"M0",
-			"M1",
-			"DEC0",
-			"DEC1",
-			"TOFF",
-			"STP",
-			"DIR";
-	};
-};
-
-/ {
-	 drv8424: drv8424 {
-		status = "okay";
-		compatible = "ti,drv8424";
-
-		dir-gpios = <&arduino_header 18 0>; /* D12 */
-		step-gpios = <&arduino_header 19 0>; /* D13 */
-		sleep-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */
-		en-gpios  = <&arduino_header 14 0>; /* D8 */
-		m0-gpios = <&mikroe_stepper_gpios 0 0>;
-		m1-gpios = <&mikroe_stepper_gpios 1 0>;
-		counter = <&counter2>;
-
-		#address-cells = <1>;
-		#size-cells = <0>;
-		#stepper-motor-cells = <0>;
-	};
-};
-
-&timers2 {
-	status = "okay";
-	counter2: counter {
-		status = "okay";
-	};
-};
diff --git a/tests/drivers/stepper/drv8424/api/src/main.c b/tests/drivers/stepper/drv8424/api/src/main.c
deleted file mode 100644
index 1af5902a5a4..00000000000
--- a/tests/drivers/stepper/drv8424/api/src/main.c
+++ /dev/null
@@ -1,499 +0,0 @@
-/*
- * Copyright 2024 Navimatix GmbH
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/drivers/gpio.h>
-#include <zephyr/kernel.h>
-#include <zephyr/ztest_assert.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include <zephyr/ztest.h>
-#include <zephyr/drivers/stepper.h>
-
-struct drv8424_api_fixture {
-	const struct device *dev;
-	stepper_event_callback_t callback;
-};
-
-struct k_poll_signal stepper_signal;
-struct k_poll_event stepper_event;
-
-static void drv8424_api_print_event_callback(const struct device *dev, enum stepper_event event,
-					     void *dummy)
-{
-	switch (event) {
-	case STEPPER_EVENT_STEPS_COMPLETED:
-		k_poll_signal_raise(&stepper_signal, STEPPER_EVENT_STEPS_COMPLETED);
-		break;
-	case STEPPER_EVENT_LEFT_END_STOP_DETECTED:
-		k_poll_signal_raise(&stepper_signal, STEPPER_EVENT_LEFT_END_STOP_DETECTED);
-		break;
-	case STEPPER_EVENT_RIGHT_END_STOP_DETECTED:
-		k_poll_signal_raise(&stepper_signal, STEPPER_EVENT_RIGHT_END_STOP_DETECTED);
-		break;
-	case STEPPER_EVENT_STALL_DETECTED:
-		k_poll_signal_raise(&stepper_signal, STEPPER_EVENT_STALL_DETECTED);
-		break;
-	default:
-		break;
-	}
-}
-
-static void *drv8424_api_setup(void)
-{
-	static struct drv8424_api_fixture fixture = {
-		.dev = DEVICE_DT_GET(DT_NODELABEL(drv8424)),
-		.callback = drv8424_api_print_event_callback,
-	};
-
-	k_poll_signal_init(&stepper_signal);
-	k_poll_event_init(&stepper_event, K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY,
-			  &stepper_signal);
-
-	zassert_not_null(fixture.dev);
-	return &fixture;
-}
-
-static void drv8424_api_before(void *f)
-{
-	struct drv8424_api_fixture *fixture = f;
-	(void)stepper_set_reference_position(fixture->dev, 0);
-	(void)stepper_set_micro_step_res(fixture->dev, 1);
-	k_poll_signal_reset(&stepper_signal);
-}
-
-static void drv8424_api_after(void *f)
-{
-	struct drv8424_api_fixture *fixture = f;
-	(void)stepper_run(fixture->dev, STEPPER_DIRECTION_POSITIVE, 0);
-}
-
-ZTEST_F(drv8424_api, test_micro_step_res_set)
-{
-	(void)stepper_set_micro_step_res(fixture->dev, 4);
-	enum stepper_micro_step_resolution res;
-	(void)stepper_get_micro_step_res(fixture->dev, &res);
-	zassert_equal(res, 4, "Micro step resolution not set correctly, should be %d but is %d", 4,
-		      res);
-}
-
-ZTEST_F(drv8424_api, test_micro_step_res_set_incorrect_value_detection)
-{
-	int ret = 0;
-
-	ret = stepper_set_micro_step_res(fixture->dev, 3);
-	zassert_equal(ret, -EINVAL, "Command should fail with error %d but returned %d", -EINVAL,
-		      ret);
-}
-
-ZTEST_F(drv8424_api, test_actual_position_set)
-{
-	int32_t pos = 100u;
-	(void)stepper_set_reference_position(fixture->dev, pos);
-	(void)stepper_get_actual_position(fixture->dev, &pos);
-	zassert_equal(pos, 100u, "Actual position should be %u but is %u", 100u, pos);
-}
-
-ZTEST_F(drv8424_api, test_is_not_moving_when_disabled)
-{
-	int32_t steps = 100;
-	bool moving = true;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_set_max_velocity(fixture->dev, 50u);
-	(void)stepper_move_by(fixture->dev, steps);
-	(void)stepper_enable(fixture->dev, false);
-	(void)stepper_is_moving(fixture->dev, &moving);
-	zassert_false(moving, "Driver should not be in state is_moving after being disabled");
-}
-
-ZTEST_F(drv8424_api, test_position_not_updating_when_disabled)
-{
-	int32_t steps = 1000;
-	int32_t position_1 = 0;
-	int32_t position_2 = 0;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_set_max_velocity(fixture->dev, 50u);
-	(void)stepper_move_by(fixture->dev, steps);
-	(void)stepper_enable(fixture->dev, false);
-	(void)stepper_get_actual_position(fixture->dev, &position_1);
-	k_msleep(100);
-	(void)stepper_get_actual_position(fixture->dev, &position_2);
-	zassert_equal(position_2, position_1,
-		      "Actual position should not have changed from %d but is %d", position_1,
-		      position_2);
-}
-
-ZTEST_F(drv8424_api, test_is_not_moving_when_reenabled_after_movement)
-{
-	int32_t steps = 1000;
-	bool moving = true;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_set_max_velocity(fixture->dev, 50u);
-	(void)stepper_move_by(fixture->dev, steps);
-	(void)stepper_enable(fixture->dev, false);
-	(void)k_msleep(100);
-	(void)stepper_enable(fixture->dev, true);
-	(void)k_msleep(100);
-	(void)stepper_is_moving(fixture->dev, &moving);
-	zassert_false(moving, "Driver should not be in state is_moving after being reenabled");
-}
-ZTEST_F(drv8424_api, test_position_not_updating_when_reenabled_after_movement)
-{
-	int32_t steps = 1000;
-	int32_t position_1 = 0;
-	int32_t position_2 = 0;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_set_max_velocity(fixture->dev, 50u);
-	(void)stepper_move_by(fixture->dev, steps);
-	(void)stepper_enable(fixture->dev, false);
-	(void)stepper_get_actual_position(fixture->dev, &position_1);
-	(void)k_msleep(100);
-	(void)stepper_enable(fixture->dev, true);
-	(void)k_msleep(100);
-	(void)stepper_get_actual_position(fixture->dev, &position_2);
-	zassert_equal(position_2, position_1,
-		      "Actual position should not have changed from %d but is %d", position_1,
-		      position_2);
-}
-
-ZTEST_F(drv8424_api, test_move_to_positive_direction_movement)
-{
-	int32_t pos = 50;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_set_max_velocity(fixture->dev, 50u);
-	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
-	(void)stepper_move_to(fixture->dev, pos);
-	(void)k_poll(&stepper_event, 1, K_SECONDS(5));
-	unsigned int signaled;
-	int result;
-
-	k_poll_signal_check(&stepper_signal, &signaled, &result);
-	zassert_equal(signaled, 1, "No event detected");
-	zassert_equal(result, STEPPER_EVENT_STEPS_COMPLETED,
-		      "Event was not STEPPER_EVENT_STEPS_COMPLETED event");
-	(void)stepper_get_actual_position(fixture->dev, &pos);
-	zassert_equal(pos, 50u, "Target position should be %d but is %d", 50u, pos);
-}
-
-ZTEST_F(drv8424_api, test_move_to_negative_direction_movement)
-{
-	int32_t pos = -50;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_set_max_velocity(fixture->dev, 50u);
-	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
-	(void)stepper_move_to(fixture->dev, pos);
-	(void)k_poll(&stepper_event, 1, K_SECONDS(5));
-	unsigned int signaled;
-	int result;
-
-	k_poll_signal_check(&stepper_signal, &signaled, &result);
-	zassert_equal(signaled, 1, "No event detected");
-	zassert_equal(result, STEPPER_EVENT_STEPS_COMPLETED,
-		      "Event was not STEPPER_EVENT_STEPS_COMPLETED event");
-	(void)stepper_get_actual_position(fixture->dev, &pos);
-	zassert_equal(pos, -50, "Target position should be %d but is %d", -50, pos);
-}
-
-ZTEST_F(drv8424_api, test_move_to_identical_current_and_target_position)
-{
-	int32_t pos = 0;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_set_max_velocity(fixture->dev, 50u);
-	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
-	(void)stepper_move_to(fixture->dev, pos);
-	(void)k_poll(&stepper_event, 1, K_SECONDS(5));
-	unsigned int signaled;
-	int result;
-
-	k_poll_signal_check(&stepper_signal, &signaled, &result);
-	zassert_equal(signaled, 1, "No event detected");
-	zassert_equal(result, STEPPER_EVENT_STEPS_COMPLETED,
-		      "Event was not STEPPER_EVENT_STEPS_COMPLETED event");
-	(void)stepper_get_actual_position(fixture->dev, &pos);
-	zassert_equal(pos, 0, "Target position should not have changed from %d but is %d", 0, pos);
-}
-
-ZTEST_F(drv8424_api, test_move_to_zero_velocity)
-{
-	int32_t pos = 100;
-	int32_t ret = 0;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_set_max_velocity(fixture->dev, 0u);
-	ret = stepper_move_to(fixture->dev, pos);
-
-	zassert_not_equal(ret, 0, "Command should fail with an error code, but returned 0");
-	k_msleep(100);
-	(void)stepper_get_actual_position(fixture->dev, &pos);
-	zassert_equal(pos, 0, "Target position should not have changed from %d but is %d", 0, pos);
-}
-
-ZTEST_F(drv8424_api, test_move_to_is_moving_true_while_moving)
-{
-	int32_t pos = 50;
-	bool moving = false;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_set_max_velocity(fixture->dev, 50u);
-	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
-	(void)stepper_move_to(fixture->dev, pos);
-	(void)stepper_is_moving(fixture->dev, &moving);
-	zassert_true(moving, "Driver should be in state is_moving while moving");
-}
-
-ZTEST_F(drv8424_api, test_move_to_is_moving_false_when_completed)
-{
-	int32_t pos = 50;
-	bool moving = false;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_set_max_velocity(fixture->dev, 50u);
-	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
-	(void)stepper_move_to(fixture->dev, pos);
-	(void)k_poll(&stepper_event, 1, K_SECONDS(5));
-	unsigned int signaled;
-	int result;
-
-	k_poll_signal_check(&stepper_signal, &signaled, &result);
-	zassert_equal(signaled, 1, "No event detected");
-	zassert_equal(result, STEPPER_EVENT_STEPS_COMPLETED,
-		      "Event was not STEPPER_EVENT_STEPS_COMPLETED event");
-	(void)stepper_is_moving(fixture->dev, &moving);
-	zassert_false(moving, "Driver should not be in state is_moving after finishing");
-}
-
-ZTEST_F(drv8424_api, test_move_to_no_movement_when_disabled)
-{
-	int32_t pos = 50;
-	int32_t curr_pos = 50;
-	int32_t ret = 0;
-
-	(void)stepper_set_max_velocity(fixture->dev, 50u);
-	(void)stepper_enable(fixture->dev, false);
-
-	ret = stepper_move_to(fixture->dev, pos);
-	zassert_equal(ret, -ECANCELED, "Move_to should fail with error code %d but returned %d",
-		      -ECANCELED, ret);
-	(void)stepper_get_actual_position(fixture->dev, &curr_pos);
-	zassert_equal(curr_pos, 0, "Current position should not have changed from %d but is %d", 0,
-		      curr_pos);
-}
-
-ZTEST_F(drv8424_api, test_move_by_positive_step_count)
-{
-	int32_t steps = 50;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_set_max_velocity(fixture->dev, 50u);
-	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
-	(void)stepper_move_by(fixture->dev, steps);
-	(void)k_poll(&stepper_event, 1, K_SECONDS(5));
-	unsigned int signaled;
-	int result;
-
-	k_poll_signal_check(&stepper_signal, &signaled, &result);
-	zassert_equal(signaled, 1, "No event detected");
-	zassert_equal(result, STEPPER_EVENT_STEPS_COMPLETED,
-		      "Event was not STEPPER_EVENT_STEPS_COMPLETED event");
-	(void)stepper_get_actual_position(fixture->dev, &steps);
-	zassert_equal(steps, 50u, "Target position should be %d but is %d", 50u, steps);
-}
-
-ZTEST_F(drv8424_api, test_move_by_negative_step_count)
-{
-	int32_t steps = -50;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_set_max_velocity(fixture->dev, 50u);
-	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
-	(void)stepper_move_by(fixture->dev, steps);
-	(void)k_poll(&stepper_event, 1, K_SECONDS(5));
-	unsigned int signaled;
-	int result;
-
-	k_poll_signal_check(&stepper_signal, &signaled, &result);
-	zassert_equal(signaled, 1, "No event detected");
-	zassert_equal(result, STEPPER_EVENT_STEPS_COMPLETED,
-		      "Event was not STEPPER_EVENT_STEPS_COMPLETED event");
-	(void)stepper_get_actual_position(fixture->dev, &steps);
-	zassert_equal(steps, -50, "Target position should be %d but is %d", -50, steps);
-}
-
-ZTEST_F(drv8424_api, test_move_by_zero_steps_no_movement)
-{
-	int32_t steps = 0;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_set_max_velocity(fixture->dev, 50u);
-	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
-	(void)stepper_move_by(fixture->dev, steps);
-	(void)k_poll(&stepper_event, 1, K_SECONDS(5));
-	unsigned int signaled;
-	int result;
-
-	k_poll_signal_check(&stepper_signal, &signaled, &result);
-	zassert_equal(signaled, 1, "No event detected");
-	zassert_equal(result, STEPPER_EVENT_STEPS_COMPLETED,
-		      "Event was not STEPPER_EVENT_STEPS_COMPLETED event");
-	(void)stepper_get_actual_position(fixture->dev, &steps);
-	zassert_equal(steps, 0, "Target position should be %d but is %d", 0, steps);
-}
-
-ZTEST_F(drv8424_api, test_move_by_zero_velocity)
-{
-	int32_t steps = 100;
-	int32_t ret = 0;
-	int32_t pos = 100;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_set_max_velocity(fixture->dev, 0u);
-	ret = stepper_move_by(fixture->dev, steps);
-
-	zassert_not_equal(ret, 0, "Command should fail with an error code, but returned 0");
-	k_msleep(100);
-	(void)stepper_get_actual_position(fixture->dev, &pos);
-	zassert_equal(pos, 0, "Target position should not have changed from %d but is %d", 0, pos);
-}
-
-ZTEST_F(drv8424_api, test_move_by_is_moving_true_while_moving)
-{
-	int32_t steps = 50;
-	bool moving = false;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_set_max_velocity(fixture->dev, 50u);
-	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
-	(void)stepper_move_by(fixture->dev, steps);
-	(void)stepper_is_moving(fixture->dev, &moving);
-	zassert_true(moving, "Driver should be in state is_moving");
-}
-
-ZTEST_F(drv8424_api, test_move_by_is_moving_false_when_completed)
-{
-	int32_t steps = 50;
-	bool moving = true;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_set_max_velocity(fixture->dev, 50u);
-	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
-	(void)stepper_move_by(fixture->dev, steps);
-	(void)k_poll(&stepper_event, 1, K_SECONDS(5));
-	unsigned int signaled;
-	int result;
-
-	k_poll_signal_check(&stepper_signal, &signaled, &result);
-	zassert_equal(signaled, 1, "No event detected");
-	zassert_equal(result, STEPPER_EVENT_STEPS_COMPLETED,
-		      "Event was not STEPPER_EVENT_STEPS_COMPLETED event");
-	(void)stepper_is_moving(fixture->dev, &moving);
-	zassert_false(moving, "Driver should not be in state is_moving after completion");
-}
-
-ZTEST_F(drv8424_api, test_move_by_no_movement_when_disabled)
-{
-	int32_t steps = 100;
-	int32_t curr_pos = 100;
-	int32_t ret = 0;
-
-	(void)stepper_set_max_velocity(fixture->dev, 50u);
-	(void)stepper_enable(fixture->dev, false);
-
-	ret = stepper_move_by(fixture->dev, steps);
-	zassert_equal(ret, -ECANCELED, "Move_by should fail with error code %d but returned %d",
-		      -ECANCELED, ret);
-	(void)stepper_get_actual_position(fixture->dev, &curr_pos);
-	zassert_equal(curr_pos, 0, "Current position should not have changed from %d but is %d", 0,
-		      curr_pos);
-}
-
-ZTEST_F(drv8424_api, test_run_positive_direction_correct_position)
-{
-	int32_t velocity = 50;
-	int32_t steps = 0;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_run(fixture->dev, STEPPER_DIRECTION_POSITIVE, velocity);
-	k_busy_wait(110000);
-
-	(void)stepper_get_actual_position(fixture->dev, &steps);
-	zassert_true(IN_RANGE(steps, 4, 6), "Current position should be between 4 and 6 but is %d",
-		     steps);
-}
-
-ZTEST_F(drv8424_api, test_run_negative_direction_correct_position)
-{
-	int32_t velocity = 50;
-	int32_t steps = 0;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_run(fixture->dev, STEPPER_DIRECTION_NEGATIVE, velocity);
-	k_busy_wait(110000);
-
-	(void)stepper_get_actual_position(fixture->dev, &steps);
-	zassert_true(IN_RANGE(steps, -6, 4),
-		     "Current position should be between -6 and -4 but is %d", steps);
-}
-
-ZTEST_F(drv8424_api, test_run_zero_velocity_correct_position)
-{
-	int32_t velocity = 0;
-	int32_t steps = 0;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_run(fixture->dev, STEPPER_DIRECTION_POSITIVE, velocity);
-	k_msleep(100);
-
-	zassert_equal(steps, 0, "Current position should not have changed from %d but is %d", 0,
-		      steps);
-}
-
-ZTEST_F(drv8424_api, test_run_is_moving_true_when_velocity_greater_zero)
-{
-	int32_t velocity = 50;
-	bool moving = false;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_run(fixture->dev, STEPPER_DIRECTION_POSITIVE, velocity);
-	(void)stepper_is_moving(fixture->dev, &moving);
-	zassert_true(moving, "Driver should be in state is_moving");
-	(void)stepper_run(fixture->dev, STEPPER_DIRECTION_POSITIVE, 0);
-}
-
-ZTEST_F(drv8424_api, test_run_is_moving_false_when_velocity_zero)
-{
-	int32_t velocity = 50;
-	bool moving = true;
-
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_run(fixture->dev, STEPPER_DIRECTION_POSITIVE, velocity);
-	(void)stepper_run(fixture->dev, STEPPER_DIRECTION_POSITIVE, 0);
-	(void)stepper_is_moving(fixture->dev, &moving);
-	zassert_false(moving, "Driver should not be in state is_moving when velocity is 0");
-}
-
-ZTEST_F(drv8424_api, test_run_no_movement_when_disabled)
-{
-	int32_t velocity = 50;
-	int32_t steps = 50;
-	int32_t ret = 0;
-
-	(void)stepper_enable(fixture->dev, false);
-
-	ret = stepper_run(fixture->dev, STEPPER_DIRECTION_POSITIVE, velocity);
-	zassert_equal(ret, -ECANCELED, "Run should fail with error code %d but returned %d",
-		      -ECANCELED, ret);
-	(void)stepper_get_actual_position(fixture->dev, &steps);
-	zassert_equal(steps, 0, "Current position should not have changed from %d but is %d", 0,
-		      steps);
-}
-
-ZTEST_SUITE(drv8424_api, NULL, drv8424_api_setup, drv8424_api_before, drv8424_api_after, NULL);
diff --git a/tests/drivers/stepper/drv8424/api/testcase.yaml b/tests/drivers/stepper/drv8424/api/testcase.yaml
deleted file mode 100644
index 0b31f5e3714..00000000000
--- a/tests/drivers/stepper/drv8424/api/testcase.yaml
+++ /dev/null
@@ -1,18 +0,0 @@
-# Copyright (c) 2024 Navimatix GmbH
-# SPDX-License-Identifier: Apache-2.0
-
-tests:
-  drivers.stepper.drv8424.api:
-    tags:
-      - drivers
-      - stepper
-      - api
-      - drv8424
-    platform_allow:
-      - nucleo_f767zi
-      - mimxrt1060_evk@B/mimxrt1062/qspi
-      - native_sim
-    integration_platforms:
-      - nucleo_f767zi
-      - mimxrt1060_evk@B/mimxrt1062/qspi
-      - native_sim
diff --git a/tests/drivers/stepper/drv8424/emul/CMakeLists.txt b/tests/drivers/stepper/drv8424/emul/CMakeLists.txt
deleted file mode 100644
index 638254b96e3..00000000000
--- a/tests/drivers/stepper/drv8424/emul/CMakeLists.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-# Copyright (c) 2024 Navimatix GmbH
-# SPDX-License-Identifier: Apache-2.0
-
-cmake_minimum_required(VERSION 3.20.0)
-
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(stepper_drv8424_emul)
-target_sources(app PRIVATE
-	src/main.c
-)
diff --git a/tests/drivers/stepper/drv8424/emul/boards/native_sim.overlay b/tests/drivers/stepper/drv8424/emul/boards/native_sim.overlay
deleted file mode 100644
index 2798c72ab16..00000000000
--- a/tests/drivers/stepper/drv8424/emul/boards/native_sim.overlay
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2024 Navimatix GmbH
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/dt-bindings/gpio/gpio.h>
-
-/ {
-
-	drv8424: drv8424 {
-		status = "okay";
-		compatible = "ti,drv8424";
-
-		dir-gpios = <&gpio1 0 0>; /* D3 */
-		step-gpios = <&gpio1 1 0>; /* D4 */
-		sleep-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* D2 */
-		en-gpios = <&gpio2 1 0>; /* 5 */
-		m0-gpios = <&gpio3 0 0>;
-		m1-gpios = <&gpio3 1 0>;
-		counter = <&counter0>;
-
-		#address-cells = <1>;
-		#size-cells = <0>;
-		#stepper-motor-cells = <0>;
-	};
-
-	gpio1: gpio1 {
-		compatible = "zephyr,gpio-emul";
-		#gpio-cells = <0x2>;
-		status = "okay";
-		gpio-controller;
-	};
-
-	gpio2: gpio2 {
-		compatible = "zephyr,gpio-emul";
-		#gpio-cells = <0x2>;
-		status = "okay";
-		gpio-controller;
-	};
-
-	gpio3: gpio3 {
-		compatible = "zephyr,gpio-emul";
-		#gpio-cells = <0x2>;
-		status = "okay";
-		gpio-controller;
-	};
-};
diff --git a/tests/drivers/stepper/drv8424/emul/src/main.c b/tests/drivers/stepper/drv8424/emul/src/main.c
deleted file mode 100644
index 411b8d00bcc..00000000000
--- a/tests/drivers/stepper/drv8424/emul/src/main.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright 2024 Navimatix GmbH
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/drivers/gpio.h>
-#include <zephyr/kernel.h>
-#include <zephyr/ztest_assert.h>
-#include <stdbool.h>
-#include <stdint.h>
-#include <zephyr/ztest.h>
-#include <zephyr/drivers/stepper.h>
-#include <zephyr/drivers/gpio/gpio_emul.h>
-
-struct drv8424_emul_fixture {
-	const struct device *dev;
-};
-
-struct gpio_dt_spec en_pin = GPIO_DT_SPEC_GET_OR(DT_NODELABEL(drv8424), en_gpios, {0});
-struct gpio_dt_spec slp_pin = GPIO_DT_SPEC_GET_OR(DT_NODELABEL(drv8424), sleep_gpios, {0});
-
-static void *drv8424_emul_setup(void)
-{
-	static struct drv8424_emul_fixture fixture = {
-		.dev = DEVICE_DT_GET(DT_NODELABEL(drv8424)),
-	};
-
-	zassert_not_null(fixture.dev);
-	return &fixture;
-}
-
-static void drv8424_emul_before(void *f)
-{
-	struct drv8424_emul_fixture *fixture = f;
-	(void)stepper_set_reference_position(fixture->dev, 0);
-	(void)stepper_set_micro_step_res(fixture->dev, 1);
-}
-
-static void drv8424_emul_after(void *f)
-{
-	struct drv8424_emul_fixture *fixture = f;
-	(void)stepper_run(fixture->dev, STEPPER_DIRECTION_POSITIVE, 0);
-}
-
-ZTEST_F(drv8424_emul, test_enable_on_gpio_pins)
-{
-	int value = 0;
-	(void)stepper_enable(fixture->dev, true);
-	/* As sleep and enable pins are optional, check if they exist*/
-	if (en_pin.port != NULL) {
-		value = gpio_emul_output_get(en_pin.port, en_pin.pin);
-		zassert_equal(value, 1, "Enable pin should be set");
-	}
-	if (slp_pin.port != NULL) {
-		value = !gpio_emul_output_get(slp_pin.port, slp_pin.pin);
-		zassert_equal(value, 0, "Sleep pin should not be set");
-	}
-}
-
-ZTEST_F(drv8424_emul, test_enable_off_gpio_pins)
-{
-	int value = 0;
-	/* Enable first to ensure that disable works correctly and the check is not against values
-	 * from initialisation or from previous tests
-	 */
-	(void)stepper_enable(fixture->dev, true);
-	(void)stepper_enable(fixture->dev, false);
-	/* As sleep and enable pins are optional, check if they exist*/
-	if (en_pin.port != NULL) {
-		value = gpio_emul_output_get(en_pin.port, en_pin.pin);
-		zassert_equal(value, 0, "Enable pin should not be set");
-	}
-	if (slp_pin.port != NULL) {
-		value = !gpio_emul_output_get(slp_pin.port, slp_pin.pin);
-		zassert_equal(value, 1, "Sleep pin should be set");
-	}
-}
-
-ZTEST_SUITE(drv8424_emul, NULL, drv8424_emul_setup, drv8424_emul_before, drv8424_emul_after, NULL);
diff --git a/tests/drivers/stepper/drv8424/emul/testcase.yaml b/tests/drivers/stepper/drv8424/emul/testcase.yaml
deleted file mode 100644
index a35d3f56d98..00000000000
--- a/tests/drivers/stepper/drv8424/emul/testcase.yaml
+++ /dev/null
@@ -1,13 +0,0 @@
-# Copyright (c) 2024 Navimatix GmbH
-# SPDX-License-Identifier: Apache-2.0
-
-tests:
-  drivers.stepper.drv8424.emul:
-    tags:
-      - drivers
-      - stepper
-      - drv8424
-    platform_allow:
-      - native_sim
-    integration_platforms:
-      - native_sim
diff --git a/tests/drivers/stepper/drv84xx/api/CMakeLists.txt b/tests/drivers/stepper/drv84xx/api/CMakeLists.txt
new file mode 100644
index 00000000000..531850812a9
--- /dev/null
+++ b/tests/drivers/stepper/drv84xx/api/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Navimatix GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(stepper_drv84xx_api)
+target_sources(app PRIVATE
+	src/main.c
+)
diff --git a/tests/drivers/stepper/drv8424/api/Kconfig b/tests/drivers/stepper/drv84xx/api/Kconfig
similarity index 100%
rename from tests/drivers/stepper/drv8424/api/Kconfig
rename to tests/drivers/stepper/drv84xx/api/Kconfig
diff --git a/tests/drivers/stepper/drv84xx/api/boards/native_sim.overlay b/tests/drivers/stepper/drv84xx/api/boards/native_sim.overlay
new file mode 100644
index 00000000000..ed869356721
--- /dev/null
+++ b/tests/drivers/stepper/drv84xx/api/boards/native_sim.overlay
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2024 Navimatix GmbH
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	aliases {
+		stepper = &drv8424;
+	};
+};
+
+/ {
+	drv8424: drv8424 {
+		status = "okay";
+		compatible = "ti,drv84xx";
+
+		dir-gpios = <&gpio1 0 0>; /* D3 */
+		step-gpios = <&gpio1 1 0>; /* D4 */
+		sleep-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* D2 */
+		en-gpios = <&gpio2 1 0>; /* 5 */
+		m0-gpios = <&gpio3 0 0>;
+		m1-gpios = <&gpio3 1 0>;
+		counter = <&counter0>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#stepper-motor-cells = <0>;
+	};
+
+	gpio1: gpio1 {
+		compatible = "zephyr,gpio-emul";
+		#gpio-cells = <0x2>;
+		status = "okay";
+		gpio-controller;
+	};
+
+	gpio2: gpio2 {
+		compatible = "zephyr,gpio-emul";
+		#gpio-cells = <0x2>;
+		status = "okay";
+		gpio-controller;
+	};
+
+	gpio3: gpio3 {
+		compatible = "zephyr,gpio-emul";
+		#gpio-cells = <0x2>;
+		status = "okay";
+		gpio-controller;
+	};
+};
diff --git a/tests/drivers/stepper/drv8424/api/prj.conf b/tests/drivers/stepper/drv84xx/api/prj.conf
similarity index 100%
rename from tests/drivers/stepper/drv8424/api/prj.conf
rename to tests/drivers/stepper/drv84xx/api/prj.conf
diff --git a/tests/drivers/stepper/drv84xx/api/src/main.c b/tests/drivers/stepper/drv84xx/api/src/main.c
new file mode 100644
index 00000000000..1eb8eaf3ed4
--- /dev/null
+++ b/tests/drivers/stepper/drv84xx/api/src/main.c
@@ -0,0 +1,468 @@
+/*
+ * Copyright 2024 Navimatix GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest_assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <zephyr/ztest.h>
+#include <zephyr/drivers/stepper.h>
+
+struct drv84xx_api_fixture {
+	const struct device *dev;
+	stepper_event_callback_t callback;
+};
+
+struct k_poll_signal stepper_signal;
+struct k_poll_event stepper_event;
+
+static void drv84xx_api_print_event_callback(const struct device *dev, enum stepper_event event,
+					     void *dummy)
+{
+	switch (event) {
+	case STEPPER_EVENT_STEPS_COMPLETED:
+		k_poll_signal_raise(&stepper_signal, STEPPER_EVENT_STEPS_COMPLETED);
+		break;
+	case STEPPER_EVENT_LEFT_END_STOP_DETECTED:
+		k_poll_signal_raise(&stepper_signal, STEPPER_EVENT_LEFT_END_STOP_DETECTED);
+		break;
+	case STEPPER_EVENT_RIGHT_END_STOP_DETECTED:
+		k_poll_signal_raise(&stepper_signal, STEPPER_EVENT_RIGHT_END_STOP_DETECTED);
+		break;
+	case STEPPER_EVENT_STALL_DETECTED:
+		k_poll_signal_raise(&stepper_signal, STEPPER_EVENT_STALL_DETECTED);
+		break;
+	default:
+		break;
+	}
+}
+
+static void *drv84xx_api_setup(void)
+{
+	static struct drv84xx_api_fixture fixture = {
+		.dev = DEVICE_DT_GET(DT_ALIAS(stepper)),
+		.callback = drv84xx_api_print_event_callback,
+	};
+
+	k_poll_signal_init(&stepper_signal);
+	k_poll_event_init(&stepper_event, K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY,
+			  &stepper_signal);
+
+	zassert_not_null(fixture.dev);
+	return &fixture;
+}
+
+static void drv84xx_api_before(void *f)
+{
+	struct drv84xx_api_fixture *fixture = f;
+	(void)stepper_set_reference_position(fixture->dev, 0);
+	(void)stepper_set_micro_step_res(fixture->dev, 1);
+	k_poll_signal_reset(&stepper_signal);
+}
+
+static void drv84xx_api_after(void *f)
+{
+	struct drv84xx_api_fixture *fixture = f;
+	(void)stepper_disable(fixture->dev);
+}
+
+ZTEST_F(drv84xx_api, test_micro_step_res_set)
+{
+	(void)stepper_set_micro_step_res(fixture->dev, 4);
+	enum stepper_micro_step_resolution res;
+	(void)stepper_get_micro_step_res(fixture->dev, &res);
+	zassert_equal(res, 4, "Micro step resolution not set correctly, should be %d but is %d", 4,
+		      res);
+}
+
+ZTEST_F(drv84xx_api, test_actual_position_set)
+{
+	int32_t pos = 100u;
+	(void)stepper_set_reference_position(fixture->dev, pos);
+	(void)stepper_get_actual_position(fixture->dev, &pos);
+	zassert_equal(pos, 100u, "Actual position should be %u but is %u", 100u, pos);
+}
+
+ZTEST_F(drv84xx_api, test_is_not_moving_when_disabled)
+{
+	int32_t steps = 100;
+	bool moving = true;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, 20000000);
+	(void)stepper_move_by(fixture->dev, steps);
+	(void)stepper_disable(fixture->dev);
+	(void)stepper_is_moving(fixture->dev, &moving);
+	zassert_false(moving, "Driver should not be in state is_moving after being disabled");
+}
+
+ZTEST_F(drv84xx_api, test_position_not_updating_when_disabled)
+{
+	int32_t steps = 1000;
+	int32_t position_1 = 0;
+	int32_t position_2 = 0;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, 20000000);
+	(void)stepper_move_by(fixture->dev, steps);
+	(void)stepper_disable(fixture->dev);
+	(void)stepper_get_actual_position(fixture->dev, &position_1);
+	k_msleep(100);
+	(void)stepper_get_actual_position(fixture->dev, &position_2);
+	zassert_equal(position_2, position_1,
+		      "Actual position should not have changed from %d but is %d", position_1,
+		      position_2);
+}
+
+ZTEST_F(drv84xx_api, test_is_not_moving_when_reenabled_after_movement)
+{
+	int32_t steps = 1000;
+	bool moving = true;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, 20000000);
+	(void)stepper_move_by(fixture->dev, steps);
+	(void)stepper_disable(fixture->dev);
+	(void)k_msleep(100);
+	(void)stepper_enable(fixture->dev);
+	(void)k_msleep(100);
+	(void)stepper_is_moving(fixture->dev, &moving);
+	zassert_false(moving, "Driver should not be in state is_moving after being reenabled");
+}
+ZTEST_F(drv84xx_api, test_position_not_updating_when_reenabled_after_movement)
+{
+	int32_t steps = 1000;
+	int32_t position_1 = 0;
+	int32_t position_2 = 0;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, 20000000);
+	(void)stepper_move_by(fixture->dev, steps);
+	(void)stepper_disable(fixture->dev);
+	(void)stepper_get_actual_position(fixture->dev, &position_1);
+	(void)k_msleep(100);
+	(void)stepper_enable(fixture->dev);
+	(void)k_msleep(100);
+	(void)stepper_get_actual_position(fixture->dev, &position_2);
+	zassert_equal(position_2, position_1,
+		      "Actual position should not have changed from %d but is %d", position_1,
+		      position_2);
+}
+
+ZTEST_F(drv84xx_api, test_move_to_positive_direction_movement)
+{
+	int32_t pos = 50;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, 20000000);
+	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
+	(void)stepper_move_to(fixture->dev, pos);
+	(void)k_poll(&stepper_event, 1, K_SECONDS(5));
+	unsigned int signaled;
+	int result;
+
+	k_poll_signal_check(&stepper_signal, &signaled, &result);
+	zassert_equal(signaled, 1, "No event detected");
+	zassert_equal(result, STEPPER_EVENT_STEPS_COMPLETED,
+		      "Event was not STEPPER_EVENT_STEPS_COMPLETED event");
+	(void)stepper_get_actual_position(fixture->dev, &pos);
+	zassert_equal(pos, 50u, "Target position should be %d but is %d", 50u, pos);
+}
+
+ZTEST_F(drv84xx_api, test_move_to_negative_direction_movement)
+{
+	int32_t pos = -50;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, 20000000);
+	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
+	(void)stepper_move_to(fixture->dev, pos);
+	(void)k_poll(&stepper_event, 1, K_SECONDS(5));
+	unsigned int signaled;
+	int result;
+
+	k_poll_signal_check(&stepper_signal, &signaled, &result);
+	zassert_equal(signaled, 1, "No event detected");
+	zassert_equal(result, STEPPER_EVENT_STEPS_COMPLETED,
+		      "Event was not STEPPER_EVENT_STEPS_COMPLETED event");
+	(void)stepper_get_actual_position(fixture->dev, &pos);
+	zassert_equal(pos, -50, "Target position should be %d but is %d", -50, pos);
+}
+
+ZTEST_F(drv84xx_api, test_move_to_identical_current_and_target_position)
+{
+	int32_t pos = 0;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, 20000000);
+	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
+	(void)stepper_move_to(fixture->dev, pos);
+	(void)k_poll(&stepper_event, 1, K_SECONDS(5));
+	unsigned int signaled;
+	int result;
+
+	k_poll_signal_check(&stepper_signal, &signaled, &result);
+	zassert_equal(signaled, 1, "No event detected");
+	zassert_equal(result, STEPPER_EVENT_STEPS_COMPLETED,
+		      "Event was not STEPPER_EVENT_STEPS_COMPLETED event");
+	(void)stepper_get_actual_position(fixture->dev, &pos);
+	zassert_equal(pos, 0, "Target position should not have changed from %d but is %d", 0, pos);
+}
+
+ZTEST_F(drv84xx_api, test_move_to_is_moving_true_while_moving)
+{
+	int32_t pos = 50;
+	bool moving = false;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, 20000000);
+	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
+	(void)stepper_move_to(fixture->dev, pos);
+	(void)stepper_is_moving(fixture->dev, &moving);
+	zassert_true(moving, "Driver should be in state is_moving while moving");
+}
+
+ZTEST_F(drv84xx_api, test_move_to_is_moving_false_when_completed)
+{
+	int32_t pos = 50;
+	bool moving = false;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, 20000000);
+	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
+	(void)stepper_move_to(fixture->dev, pos);
+	(void)k_poll(&stepper_event, 1, K_SECONDS(5));
+	unsigned int signaled;
+	int result;
+
+	k_poll_signal_check(&stepper_signal, &signaled, &result);
+	zassert_equal(signaled, 1, "No event detected");
+	zassert_equal(result, STEPPER_EVENT_STEPS_COMPLETED,
+		      "Event was not STEPPER_EVENT_STEPS_COMPLETED event");
+	(void)stepper_is_moving(fixture->dev, &moving);
+	zassert_false(moving, "Driver should not be in state is_moving after finishing");
+}
+
+ZTEST_F(drv84xx_api, test_move_to_no_movement_when_disabled)
+{
+	int32_t pos = 50;
+	int32_t curr_pos = 50;
+	int32_t ret = 0;
+
+	(void)stepper_set_microstep_interval(fixture->dev, 20000000);
+	(void)stepper_disable(fixture->dev);
+
+	ret = stepper_move_to(fixture->dev, pos);
+	zassert_equal(ret, -ECANCELED, "Move_to should fail with error code %d but returned %d",
+		      -ECANCELED, ret);
+	(void)stepper_get_actual_position(fixture->dev, &curr_pos);
+	zassert_equal(curr_pos, 0, "Current position should not have changed from %d but is %d", 0,
+		      curr_pos);
+}
+
+ZTEST_F(drv84xx_api, test_move_by_positive_step_count)
+{
+	int32_t steps = 50;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, 20000000);
+	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
+	(void)stepper_move_by(fixture->dev, steps);
+	(void)k_poll(&stepper_event, 1, K_SECONDS(5));
+	unsigned int signaled;
+	int result;
+
+	k_poll_signal_check(&stepper_signal, &signaled, &result);
+	zassert_equal(signaled, 1, "No event detected");
+	zassert_equal(result, STEPPER_EVENT_STEPS_COMPLETED,
+		      "Event was not STEPPER_EVENT_STEPS_COMPLETED event");
+	(void)stepper_get_actual_position(fixture->dev, &steps);
+	zassert_equal(steps, 50u, "Target position should be %d but is %d", 50u, steps);
+}
+
+ZTEST_F(drv84xx_api, test_move_by_negative_step_count)
+{
+	int32_t steps = -50;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, 20000000);
+	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
+	(void)stepper_move_by(fixture->dev, steps);
+	(void)k_poll(&stepper_event, 1, K_SECONDS(5));
+	unsigned int signaled;
+	int result;
+
+	k_poll_signal_check(&stepper_signal, &signaled, &result);
+	zassert_equal(signaled, 1, "No event detected");
+	zassert_equal(result, STEPPER_EVENT_STEPS_COMPLETED,
+		      "Event was not STEPPER_EVENT_STEPS_COMPLETED event");
+	(void)stepper_get_actual_position(fixture->dev, &steps);
+	zassert_equal(steps, -50, "Target position should be %d but is %d", -50, steps);
+}
+
+ZTEST_F(drv84xx_api, test_move_by_zero_steps_no_movement)
+{
+	int32_t steps = 0;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, 20000000);
+	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
+	(void)stepper_move_by(fixture->dev, steps);
+	(void)k_poll(&stepper_event, 1, K_SECONDS(5));
+	unsigned int signaled;
+	int result;
+
+	k_poll_signal_check(&stepper_signal, &signaled, &result);
+	zassert_equal(signaled, 1, "No event detected");
+	zassert_equal(result, STEPPER_EVENT_STEPS_COMPLETED,
+		      "Event was not STEPPER_EVENT_STEPS_COMPLETED event");
+	(void)stepper_get_actual_position(fixture->dev, &steps);
+	zassert_equal(steps, 0, "Target position should be %d but is %d", 0, steps);
+}
+
+ZTEST_F(drv84xx_api, test_move_by_zero_step_interval)
+{
+	int32_t steps = 100;
+	int32_t ret = 0;
+	int32_t pos = 100;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_disable(fixture->dev);
+	ret = stepper_move_by(fixture->dev, steps);
+
+	zassert_not_equal(ret, 0, "Command should fail with an error code, but returned 0");
+	k_msleep(100);
+	(void)stepper_get_actual_position(fixture->dev, &pos);
+	zassert_equal(pos, 0, "Target position should not have changed from %d but is %d", 0, pos);
+}
+
+ZTEST_F(drv84xx_api, test_move_by_is_moving_true_while_moving)
+{
+	int32_t steps = 50;
+	bool moving = false;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, 20000000);
+	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
+	(void)stepper_move_by(fixture->dev, steps);
+	(void)stepper_is_moving(fixture->dev, &moving);
+	zassert_true(moving, "Driver should be in state is_moving");
+}
+
+ZTEST_F(drv84xx_api, test_move_by_is_moving_false_when_completed)
+{
+	int32_t steps = 50;
+	bool moving = true;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, 20000000);
+	(void)stepper_set_event_callback(fixture->dev, fixture->callback, NULL);
+	(void)stepper_move_by(fixture->dev, steps);
+	(void)k_poll(&stepper_event, 1, K_SECONDS(5));
+	unsigned int signaled;
+	int result;
+
+	k_poll_signal_check(&stepper_signal, &signaled, &result);
+	zassert_equal(signaled, 1, "No event detected");
+	zassert_equal(result, STEPPER_EVENT_STEPS_COMPLETED,
+		      "Event was not STEPPER_EVENT_STEPS_COMPLETED event");
+	(void)stepper_is_moving(fixture->dev, &moving);
+	zassert_false(moving, "Driver should not be in state is_moving after completion");
+}
+
+ZTEST_F(drv84xx_api, test_move_by_no_movement_when_disabled)
+{
+	int32_t steps = 100;
+	int32_t curr_pos = 100;
+	int32_t ret = 0;
+
+	(void)stepper_set_microstep_interval(fixture->dev, 20000000);
+	(void)stepper_disable(fixture->dev);
+
+	ret = stepper_move_by(fixture->dev, steps);
+	zassert_equal(ret, -ECANCELED, "Move_by should fail with error code %d but returned %d",
+		      -ECANCELED, ret);
+	(void)stepper_get_actual_position(fixture->dev, &curr_pos);
+	zassert_equal(curr_pos, 0, "Current position should not have changed from %d but is %d", 0,
+		      curr_pos);
+}
+
+ZTEST_F(drv84xx_api, test_run_positive_direction_correct_position)
+{
+	uint64_t step_interval = 20000000;
+	int32_t steps = 0;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, step_interval);
+	(void)stepper_run(fixture->dev, STEPPER_DIRECTION_POSITIVE);
+	k_busy_wait(110000);
+
+	(void)stepper_get_actual_position(fixture->dev, &steps);
+	zassert_true(IN_RANGE(steps, 4, 6), "Current position should be between 4 and 6 but is %d",
+		     steps);
+}
+
+ZTEST_F(drv84xx_api, test_run_negative_direction_correct_position)
+{
+	uint64_t step_interval = 20000000;
+	int32_t steps = 0;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, step_interval);
+	(void)stepper_run(fixture->dev, STEPPER_DIRECTION_NEGATIVE);
+	k_busy_wait(110000);
+
+	(void)stepper_get_actual_position(fixture->dev, &steps);
+	zassert_true(IN_RANGE(steps, -6, 4),
+		     "Current position should be between -6 and -4 but is %d", steps);
+}
+
+ZTEST_F(drv84xx_api, test_run_zero_step_interval_correct_position)
+{
+	uint64_t step_interval = 0;
+	int32_t steps = 0;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, step_interval);
+	(void)stepper_run(fixture->dev, STEPPER_DIRECTION_POSITIVE);
+	k_msleep(100);
+
+	zassert_equal(steps, 0, "Current position should not have changed from %d but is %d", 0,
+		      steps);
+}
+
+ZTEST_F(drv84xx_api, test_run_is_moving_true_when_step_interval_greater_zero)
+{
+	uint64_t step_interval = 20000000;
+	bool moving = false;
+
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, step_interval);
+	(void)stepper_run(fixture->dev, STEPPER_DIRECTION_POSITIVE);
+	(void)stepper_is_moving(fixture->dev, &moving);
+	zassert_true(moving, "Driver should be in state is_moving");
+	(void)stepper_disable(fixture->dev);
+}
+
+ZTEST_F(drv84xx_api, test_run_no_movement_when_disabled)
+{
+	uint64_t step_interval = 20000000;
+	int32_t steps = 50;
+	int32_t ret = 0;
+
+	(void)stepper_disable(fixture->dev);
+	(void)stepper_set_microstep_interval(fixture->dev, step_interval);
+
+	ret = stepper_run(fixture->dev, STEPPER_DIRECTION_POSITIVE);
+	zassert_equal(ret, -ECANCELED, "Run should fail with error code %d but returned %d",
+		      -ECANCELED, ret);
+	(void)stepper_get_actual_position(fixture->dev, &steps);
+	zassert_equal(steps, 0, "Current position should not have changed from %d but is %d", 0,
+		      steps);
+}
+
+ZTEST_SUITE(drv84xx_api, NULL, drv84xx_api_setup, drv84xx_api_before, drv84xx_api_after, NULL);
diff --git a/tests/drivers/stepper/drv84xx/api/testcase.yaml b/tests/drivers/stepper/drv84xx/api/testcase.yaml
new file mode 100644
index 00000000000..ef3e866c983
--- /dev/null
+++ b/tests/drivers/stepper/drv84xx/api/testcase.yaml
@@ -0,0 +1,12 @@
+# Copyright (c) 2024 Navimatix GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+tests:
+  drivers.stepper.drv84xx.api:
+    tags:
+      - drivers
+      - stepper
+      - api
+      - drv84xx
+    platform_allow:
+      - native_sim
diff --git a/tests/drivers/stepper/drv84xx/emul/CMakeLists.txt b/tests/drivers/stepper/drv84xx/emul/CMakeLists.txt
new file mode 100644
index 00000000000..8d3c47f47cc
--- /dev/null
+++ b/tests/drivers/stepper/drv84xx/emul/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Navimatix GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(stepper_drv84xx_emul)
+target_sources(app PRIVATE
+	src/main.c
+)
diff --git a/tests/drivers/stepper/drv8424/emul/Kconfig b/tests/drivers/stepper/drv84xx/emul/Kconfig
similarity index 100%
rename from tests/drivers/stepper/drv8424/emul/Kconfig
rename to tests/drivers/stepper/drv84xx/emul/Kconfig
diff --git a/tests/drivers/stepper/drv84xx/emul/boards/native_sim.overlay b/tests/drivers/stepper/drv84xx/emul/boards/native_sim.overlay
new file mode 100644
index 00000000000..0ad77289289
--- /dev/null
+++ b/tests/drivers/stepper/drv84xx/emul/boards/native_sim.overlay
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2024 Navimatix GmbH
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+
+	drv84xx: drv84xx {
+		status = "okay";
+		compatible = "ti,drv84xx";
+
+		dir-gpios = <&gpio1 0 0>; /* D3 */
+		step-gpios = <&gpio1 1 0>; /* D4 */
+		sleep-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>; /* D2 */
+		en-gpios = <&gpio2 1 0>; /* 5 */
+		m0-gpios = <&gpio3 0 0>;
+		m1-gpios = <&gpio3 1 0>;
+		counter = <&counter0>;
+
+		#address-cells = <1>;
+		#size-cells = <0>;
+		#stepper-motor-cells = <0>;
+	};
+
+	gpio1: gpio1 {
+		compatible = "zephyr,gpio-emul";
+		#gpio-cells = <0x2>;
+		status = "okay";
+		gpio-controller;
+	};
+
+	gpio2: gpio2 {
+		compatible = "zephyr,gpio-emul";
+		#gpio-cells = <0x2>;
+		status = "okay";
+		gpio-controller;
+	};
+
+	gpio3: gpio3 {
+		compatible = "zephyr,gpio-emul";
+		#gpio-cells = <0x2>;
+		status = "okay";
+		gpio-controller;
+	};
+};
diff --git a/tests/drivers/stepper/drv8424/emul/prj.conf b/tests/drivers/stepper/drv84xx/emul/prj.conf
similarity index 100%
rename from tests/drivers/stepper/drv8424/emul/prj.conf
rename to tests/drivers/stepper/drv84xx/emul/prj.conf
diff --git a/tests/drivers/stepper/drv84xx/emul/src/main.c b/tests/drivers/stepper/drv84xx/emul/src/main.c
new file mode 100644
index 00000000000..c730bc457ce
--- /dev/null
+++ b/tests/drivers/stepper/drv84xx/emul/src/main.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright 2024 Navimatix GmbH
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest_assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <zephyr/ztest.h>
+#include <zephyr/drivers/stepper.h>
+#include <zephyr/drivers/gpio/gpio_emul.h>
+
+struct drv84xx_emul_fixture {
+	const struct device *dev;
+};
+
+struct gpio_dt_spec en_pin = GPIO_DT_SPEC_GET_OR(DT_NODELABEL(drv84xx), en_gpios, {0});
+struct gpio_dt_spec slp_pin = GPIO_DT_SPEC_GET_OR(DT_NODELABEL(drv84xx), sleep_gpios, {0});
+
+static void *drv84xx_emul_setup(void)
+{
+	static struct drv84xx_emul_fixture fixture = {
+		.dev = DEVICE_DT_GET(DT_NODELABEL(drv84xx)),
+	};
+
+	zassert_not_null(fixture.dev);
+	return &fixture;
+}
+
+static void drv84xx_emul_before(void *f)
+{
+	struct drv84xx_emul_fixture *fixture = f;
+	(void)stepper_set_reference_position(fixture->dev, 0);
+	(void)stepper_set_micro_step_res(fixture->dev, 1);
+}
+
+static void drv84xx_emul_after(void *f)
+{
+	struct drv84xx_emul_fixture *fixture = f;
+	(void)stepper_disable(fixture->dev);
+}
+
+ZTEST_F(drv84xx_emul, test_enable_on_gpio_pins)
+{
+	int value = 0;
+	(void)stepper_enable(fixture->dev);
+	/* As sleep and enable pins are optional, check if they exist*/
+	if (en_pin.port != NULL) {
+		value = gpio_emul_output_get(en_pin.port, en_pin.pin);
+		zassert_equal(value, 1, "Enable pin should be set");
+	}
+	if (slp_pin.port != NULL) {
+		value = !gpio_emul_output_get(slp_pin.port, slp_pin.pin);
+		zassert_equal(value, 0, "Sleep pin should not be set");
+	}
+}
+
+ZTEST_F(drv84xx_emul, test_enable_off_gpio_pins)
+{
+	int value = 0;
+	/* Enable first to ensure that disable works correctly and the check is not against values
+	 * from initialisation or from previous tests
+	 */
+	(void)stepper_enable(fixture->dev);
+	(void)stepper_disable(fixture->dev);
+	/* As sleep and enable pins are optional, check if they exist*/
+	if (en_pin.port != NULL) {
+		value = gpio_emul_output_get(en_pin.port, en_pin.pin);
+		zassert_equal(value, 0, "Enable pin should not be set");
+	}
+	if (slp_pin.port != NULL) {
+		value = !gpio_emul_output_get(slp_pin.port, slp_pin.pin);
+		zassert_equal(value, 1, "Sleep pin should be set");
+	}
+}
+
+ZTEST_SUITE(drv84xx_emul, NULL, drv84xx_emul_setup, drv84xx_emul_before, drv84xx_emul_after, NULL);
diff --git a/tests/drivers/stepper/drv84xx/emul/testcase.yaml b/tests/drivers/stepper/drv84xx/emul/testcase.yaml
new file mode 100644
index 00000000000..5ea422718ca
--- /dev/null
+++ b/tests/drivers/stepper/drv84xx/emul/testcase.yaml
@@ -0,0 +1,11 @@
+# Copyright (c) 2024 Navimatix GmbH
+# SPDX-License-Identifier: Apache-2.0
+
+tests:
+  drivers.stepper.drv84xx.emul:
+    tags:
+      - drivers
+      - stepper
+      - drv84xx
+    platform_allow:
+      - native_sim
diff --git a/tests/drivers/stepper/shell/src/main.c b/tests/drivers/stepper/shell/src/main.c
index 8b2a2cc3b5b..c4c9c579627 100644
--- a/tests/drivers/stepper/shell/src/main.c
+++ b/tests/drivers/stepper/shell/src/main.c
@@ -43,16 +43,19 @@ ZTEST_SUITE(stepper_shell, NULL, stepper_shell_setup, NULL, NULL, NULL);
 ZTEST(stepper_shell, test_stepper_enable)
 {
 	const struct shell *sh = shell_backend_dummy_get_ptr();
-	int err = shell_execute_cmd(sh, "stepper enable " FAKE_STEPPER_NAME " on");
+	int err = shell_execute_cmd(sh, "stepper enable " FAKE_STEPPER_NAME);
 
 	ASSERT_STEPPER_FUNC_CALLED(fake_stepper_enable_fake, err);
-	zassert_equal(fake_stepper_enable_fake.arg1_val, true, "wrong enable value");
+	zassert_equal(err, 0, "stepper enable could not be executed");
+}
 
-	RESET_FAKE(fake_stepper_enable);
+ZTEST(stepper_shell, test_stepper_disable)
+{
+	const struct shell *sh = shell_backend_dummy_get_ptr();
+	int err = shell_execute_cmd(sh, "stepper disable " FAKE_STEPPER_NAME);
 
-	err = shell_execute_cmd(sh, "stepper enable " FAKE_STEPPER_NAME " off");
-	ASSERT_STEPPER_FUNC_CALLED(fake_stepper_enable_fake, err);
-	zassert_equal(fake_stepper_enable_fake.arg1_val, false, "wrong enable value");
+	ASSERT_STEPPER_FUNC_CALLED(fake_stepper_disable_fake, err);
+	zassert_equal(err, 0, "stepper disable could not be executed");
 }
 
 ZTEST(stepper_shell, test_stepper_move_by)
@@ -64,13 +67,14 @@ ZTEST(stepper_shell, test_stepper_move_by)
 	zassert_equal(fake_stepper_move_by_fake.arg1_val, 1000, "wrong microsteps value");
 }
 
-ZTEST(stepper_shell, test_stepper_set_max_velocity)
+ZTEST(stepper_shell, test_stepper_set_microstep_interval)
 {
 	const struct shell *sh = shell_backend_dummy_get_ptr();
-	int err = shell_execute_cmd(sh, "stepper set_max_velocity " FAKE_STEPPER_NAME " 200");
+	int err = shell_execute_cmd(sh, "stepper set_microstep_interval " FAKE_STEPPER_NAME " 200");
 
-	ASSERT_STEPPER_FUNC_CALLED(fake_stepper_set_max_velocity_fake, err);
-	zassert_equal(fake_stepper_set_max_velocity_fake.arg1_val, 200, "wrong velocity value");
+	ASSERT_STEPPER_FUNC_CALLED(fake_stepper_set_microstep_interval_fake, err);
+	zassert_equal(fake_stepper_set_microstep_interval_fake.arg1_val, 200,
+		      "wrong step_interval value");
 }
 
 ZTEST(stepper_shell, test_stepper_set_micro_step_res)
@@ -123,29 +127,36 @@ ZTEST(stepper_shell, test_stepper_move_to)
 	int err = shell_execute_cmd(sh, "stepper move_to " FAKE_STEPPER_NAME " 200");
 
 	ASSERT_STEPPER_FUNC_CALLED(fake_stepper_move_to_fake, err);
-	zassert_equal(fake_stepper_move_to_fake.arg1_val, 200,
-		      "wrong target position value");
+	zassert_equal(fake_stepper_move_to_fake.arg1_val, 200, "wrong target position value");
 }
 
 ZTEST(stepper_shell, test_stepper_run)
 {
 	const struct shell *sh = shell_backend_dummy_get_ptr();
-	int err = shell_execute_cmd(sh, "stepper run " FAKE_STEPPER_NAME " positive 200");
+	int err = shell_execute_cmd(sh, "stepper run " FAKE_STEPPER_NAME " positive");
 
 	ASSERT_STEPPER_FUNC_CALLED(fake_stepper_run_fake, err);
 	zassert_equal(fake_stepper_run_fake.arg1_val, STEPPER_DIRECTION_POSITIVE,
 		      "wrong direction value");
-	zassert_equal(fake_stepper_run_fake.arg2_val, 200, "wrong velocity value");
 }
 
 ZTEST(stepper_shell, test_stepper_run_invalid_direction)
 {
 	const struct shell *sh = shell_backend_dummy_get_ptr();
-	int err = shell_execute_cmd(sh, "stepper run " FAKE_STEPPER_NAME " foo 200");
+	int err = shell_execute_cmd(sh, "stepper run " FAKE_STEPPER_NAME " foo");
 
 	zassert_not_equal(err, 0, " executed run with invalid direction value");
 }
 
+ZTEST(stepper_shell, test_stepper_stop)
+{
+	const struct shell *sh = shell_backend_dummy_get_ptr();
+	int err = shell_execute_cmd(sh, "stepper stop " FAKE_STEPPER_NAME);
+
+	ASSERT_STEPPER_FUNC_CALLED(fake_stepper_stop_fake, err);
+	zassert_equal(err, 0, "stepper stop could not be executed");
+}
+
 ZTEST(stepper_shell, test_stepper_info)
 {
 	const struct shell *sh = shell_backend_dummy_get_ptr();
diff --git a/tests/drivers/stepper/shell/testcase.yaml b/tests/drivers/stepper/shell/testcase.yaml
index 6b27b6b9477..4a7dbd35243 100644
--- a/tests/drivers/stepper/shell/testcase.yaml
+++ b/tests/drivers/stepper/shell/testcase.yaml
@@ -6,10 +6,10 @@ common:
 
 tests:
   drivers.stepper.shell:
-    integration_platforms:
+    platform_allow:
       - native_sim
       - native_sim/native/64
   drivers.stepper.shell_async:
-    integration_platforms:
+    platform_allow:
       - native_sim
       - native_sim/native/64
diff --git a/tests/drivers/stepper/stepper_api/boards/native_sim.overlay b/tests/drivers/stepper/stepper_api/boards/native_sim.overlay
new file mode 100644
index 00000000000..4cba3f5b33d
--- /dev/null
+++ b/tests/drivers/stepper/stepper_api/boards/native_sim.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 Jilay Sandeep Pandya
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	gpio1: gpio1 {
+		compatible = "zephyr,gpio-emul";
+		#gpio-cells = <0x2>;
+		status = "okay";
+		gpio-controller;
+	};
+
+	gpio2: gpio2 {
+		compatible = "zephyr,gpio-emul";
+		#gpio-cells = <0x2>;
+		status = "okay";
+		gpio-controller;
+	};
+
+	gpio3: gpio3 {
+		compatible = "zephyr,gpio-emul";
+		#gpio-cells = <0x2>;
+		status = "okay";
+		gpio-controller;
+	};
+
+	gpio4: gpio4 {
+		compatible = "zephyr,gpio-emul";
+		#gpio-cells = <0x2>;
+		status = "okay";
+		gpio-controller;
+	};
+};
diff --git a/tests/drivers/stepper/stepper_api/boards/native_sim_adi_tmc2209.overlay b/tests/drivers/stepper/stepper_api/boards/native_sim_adi_tmc2209.overlay
new file mode 100644
index 00000000000..caf4f3c5b3a
--- /dev/null
+++ b/tests/drivers/stepper/stepper_api/boards/native_sim_adi_tmc2209.overlay
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025 Jilay Sandeep Pandya
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "native_sim.overlay"
+
+/ {
+	aliases {
+		stepper =  &adi_tmc2209;
+	};
+};
+
+/ {
+	adi_tmc2209: adi_tmc2209 {
+		status = "okay";
+		compatible = "adi,tmc2209";
+		micro-step-res = <32>;
+		dir-gpios = <&gpio1 0 0>;
+		step-gpios = <&gpio1 1 0>;
+		en-gpios = <&gpio2 1 0>;
+		msx-gpios = <&gpio3 0 0>, <&gpio4 1 0>;
+		counter = <&counter0>;
+	};
+};
diff --git a/tests/drivers/stepper/stepper_api/boards/native_sim_allegro_a4979.overlay b/tests/drivers/stepper/stepper_api/boards/native_sim_allegro_a4979.overlay
new file mode 100644
index 00000000000..3d1c69339df
--- /dev/null
+++ b/tests/drivers/stepper/stepper_api/boards/native_sim_allegro_a4979.overlay
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2025 Jilay Sandeep Pandya
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "native_sim.overlay"
+
+/ {
+	aliases {
+		stepper =  &allegro_a4979;
+	};
+};
+
+/ {
+	allegro_a4979: allegro_a4979 {
+		status = "okay";
+		compatible = "allegro,a4979";
+		micro-step-res = <1>;
+		reset-gpios = <&gpio4 0 0>;
+		dir-gpios = <&gpio1 0 0>;
+		step-gpios = <&gpio1 1 0>;
+		en-gpios = <&gpio2 1 0>;
+		m0-gpios = <&gpio3 0 0>;
+		m1-gpios = <&gpio3 1 0>;
+		counter = <&counter0>;
+	};
+};
diff --git a/tests/drivers/stepper/stepper_api/boards/native_sim_ti_drv84xx.overlay b/tests/drivers/stepper/stepper_api/boards/native_sim_ti_drv84xx.overlay
new file mode 100644
index 00000000000..0763a19e393
--- /dev/null
+++ b/tests/drivers/stepper/stepper_api/boards/native_sim_ti_drv84xx.overlay
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2025 Jilay Sandeep Pandya
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "native_sim.overlay"
+
+/ {
+	aliases {
+		stepper =  &ti_drv84xx;
+	};
+};
+
+/ {
+	ti_drv84xx: ti_drv84xx {
+		status = "okay";
+		compatible = "ti,drv84xx";
+		micro-step-res = <8>;
+		dir-gpios = <&gpio1 0 0>;
+		step-gpios = <&gpio1 1 0>;
+		sleep-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
+		en-gpios = <&gpio2 1 0>;
+		m0-gpios = <&gpio3 0 0>;
+		m1-gpios = <&gpio3 1 0>;
+		counter = <&counter0>;
+	};
+};
diff --git a/tests/drivers/stepper/stepper_api/boards/native_sim_zephyr_gpio_stepper.overlay b/tests/drivers/stepper/stepper_api/boards/native_sim_zephyr_gpio_stepper.overlay
new file mode 100644
index 00000000000..3df8e647466
--- /dev/null
+++ b/tests/drivers/stepper/stepper_api/boards/native_sim_zephyr_gpio_stepper.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025 Jilay Sandeep Pandya
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "native_sim.overlay"
+
+/ {
+	aliases {
+		stepper =  &zephyr_gpio_stepper;
+	};
+};
+
+/ {
+	zephyr_gpio_stepper: zephyr_gpio_stepper {
+		compatible = "zephyr,gpio-stepper";
+		status = "okay";
+		micro-step-res = <1>;
+		gpios = <&gpio1 0 0>,
+				<&gpio2 0 0>,
+				<&gpio3 0 0>,
+				<&gpio4 0 0>;
+	};
+};
diff --git a/tests/drivers/stepper/stepper_api/boards/nucleo_f767zi.conf b/tests/drivers/stepper/stepper_api/boards/nucleo_f767zi.conf
deleted file mode 100644
index aa7ae8a6869..00000000000
--- a/tests/drivers/stepper/stepper_api/boards/nucleo_f767zi.conf
+++ /dev/null
@@ -1,4 +0,0 @@
-# Copyright (c) 2024 Navimatix GmbH
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_GPIO=y
diff --git a/tests/drivers/stepper/stepper_api/boards/nucleo_f767zi.overlay b/tests/drivers/stepper/stepper_api/boards/nucleo_f767zi.overlay
deleted file mode 100644
index deb50e29eb6..00000000000
--- a/tests/drivers/stepper/stepper_api/boards/nucleo_f767zi.overlay
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (c) 2024 Navimatix GmbH
- * SPDX-License-Identifier: Apache-2.0
- */
-
- #include <zephyr/dt-bindings/gpio/gpio.h>
-
-/ {
-	 zephyr,user {
-		 stepper-motors = <&motor_1 0>;
-	 };
-};
-
-/ {
-
-	 motor_1: motor_1 {
-		 status = "okay";
-		 compatible = "ti,drv8424";
-
-
-		 dir-gpios = <&arduino_header 18 0>; /* D12 */
-		 step-gpios = <&arduino_header 19 0>; /* D13 */
-		 sleep-gpios = <&arduino_header 15 GPIO_ACTIVE_LOW>; /* D9 */
-		 en-gpios  = <&arduino_header 14 0>; /* D8 */
-		 m0-gpios = <&arduino_header 16 0>;
-		 m1-gpios = <&arduino_header 17 0>;
-		 counter = <&counter2>;
-
-		 #address-cells = <1>;
-		 #size-cells = <0>;
-		 #stepper-motor-cells = <0>;
-
-	 };
-};
-
-&timers2 {
-	 status = "okay";
-	 counter2: counter {
-		 status = "okay";
-	 };
-};
diff --git a/tests/drivers/stepper/stepper_api/boards/nucleo_g071rb.conf b/tests/drivers/stepper/stepper_api/boards/nucleo_g071rb.conf
deleted file mode 100644
index ed533e324c7..00000000000
--- a/tests/drivers/stepper/stepper_api/boards/nucleo_g071rb.conf
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-FileCopyrightText: Copyright (c) 2024 Jilay Sandeep Pandya
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_GPIO=y
-CONFIG_GPIO_STEPPER=y
diff --git a/tests/drivers/stepper/stepper_api/boards/nucleo_g071rb.overlay b/tests/drivers/stepper/stepper_api/boards/nucleo_g071rb.overlay
deleted file mode 100644
index afd285e9262..00000000000
--- a/tests/drivers/stepper/stepper_api/boards/nucleo_g071rb.overlay
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2024 Jilay Sandeep Pandya
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
-	motor_1: motor_1 {
-		compatible = "zephyr,gpio-stepper";
-		status = "okay";
-		micro-step-res = <1>;
-		gpios = <&gpioa 9 GPIO_ACTIVE_HIGH>,
-			<&gpioc 7 GPIO_ACTIVE_HIGH>,
-			<&gpiob 0 GPIO_ACTIVE_HIGH>,
-			<&gpioa 7 GPIO_ACTIVE_HIGH>;
-	};
-};
diff --git a/tests/drivers/stepper/stepper_api/boards/qemu_x86_64.conf b/tests/drivers/stepper/stepper_api/boards/qemu_x86_64.conf
deleted file mode 100644
index ed533e324c7..00000000000
--- a/tests/drivers/stepper/stepper_api/boards/qemu_x86_64.conf
+++ /dev/null
@@ -1,5 +0,0 @@
-# SPDX-FileCopyrightText: Copyright (c) 2024 Jilay Sandeep Pandya
-# SPDX-License-Identifier: Apache-2.0
-
-CONFIG_GPIO=y
-CONFIG_GPIO_STEPPER=y
diff --git a/tests/drivers/stepper/stepper_api/boards/qemu_x86_64.overlay b/tests/drivers/stepper/stepper_api/boards/qemu_x86_64.overlay
deleted file mode 100644
index c38d1128bed..00000000000
--- a/tests/drivers/stepper/stepper_api/boards/qemu_x86_64.overlay
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * SPDX-FileCopyrightText: Copyright (c) 2024 Jilay Sandeep Pandya
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/ {
-	test {
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		test_gpio: gpio@deadbeef {
-			compatible = "vnd,gpio";
-			gpio-controller;
-			reg = <0xdeadbeef 0x1000>;
-			#gpio-cells = <0x2>;
-			status = "okay";
-		};
-	};
-};
-
-/ {
-	motor_1: motor_1 {
-		compatible = "zephyr,gpio-stepper";
-		status = "okay";
-		micro-step-res = <1>;
-		gpios = <&test_gpio 0 0>,
-			<&test_gpio 0 0>,
-			<&test_gpio 0 0>,
-			<&test_gpio 0 0>;
-	};
-};
diff --git a/tests/drivers/stepper/stepper_api/boards/qemu_x86_64_zephyr_gpio_stepper.overlay b/tests/drivers/stepper/stepper_api/boards/qemu_x86_64_zephyr_gpio_stepper.overlay
new file mode 100644
index 00000000000..bfc3161e3b1
--- /dev/null
+++ b/tests/drivers/stepper/stepper_api/boards/qemu_x86_64_zephyr_gpio_stepper.overlay
@@ -0,0 +1,54 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2024 Jilay Sandeep Pandya
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/gpio/gpio.h>
+
+/ {
+	aliases {
+		stepper =  &zephyr_gpio_stepper;
+	};
+};
+
+/ {
+	gpio1: gpio1 {
+		compatible = "zephyr,gpio-emul";
+		#gpio-cells = <0x2>;
+		status = "okay";
+		gpio-controller;
+	};
+
+	gpio2: gpio2 {
+		compatible = "zephyr,gpio-emul";
+		#gpio-cells = <0x2>;
+		status = "okay";
+		gpio-controller;
+	};
+
+	gpio3: gpio3 {
+		compatible = "zephyr,gpio-emul";
+		#gpio-cells = <0x2>;
+		status = "okay";
+		gpio-controller;
+	};
+
+	gpio4: gpio4 {
+		compatible = "zephyr,gpio-emul";
+		#gpio-cells = <0x2>;
+		status = "okay";
+		gpio-controller;
+	};
+};
+
+/ {
+	zephyr_gpio_stepper: zephyr_gpio_stepper {
+		compatible = "zephyr,gpio-stepper";
+		status = "okay";
+		micro-step-res = <2>;
+		gpios = <&gpio1 0 0>,
+				<&gpio2 0 0>,
+				<&gpio3 0 0>,
+				<&gpio4 0 0>;
+	};
+};
diff --git a/tests/drivers/stepper/stepper_api/src/main.c b/tests/drivers/stepper/stepper_api/src/main.c
index 864957ae363..6d264712cfc 100644
--- a/tests/drivers/stepper/stepper_api/src/main.c
+++ b/tests/drivers/stepper/stepper_api/src/main.c
@@ -1,12 +1,14 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2024 Jilay Sandeep Pandya
- *
+ * SPDX-FileCopyrightText: Copyright (c) 2025 Jilay Sandeep Pandya
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #include <zephyr/ztest.h>
 #include <zephyr/drivers/stepper.h>
 
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(stepper_api, CONFIG_STEPPER_LOG_LEVEL);
+
 struct stepper_fixture {
 	const struct device *dev;
 	stepper_event_callback_t callback;
@@ -16,10 +18,24 @@ struct k_poll_signal stepper_signal;
 struct k_poll_event stepper_event;
 void *user_data_received;
 
+#define POLL_AND_CHECK_SIGNAL(signal, event, expected_event, timeout)                              \
+	({                                                                                         \
+		do {                                                                               \
+			(void)k_poll(&(event), 1, timeout);                                        \
+			unsigned int signaled;                                                     \
+			int result;                                                                \
+			k_poll_signal_check(&(signal), &signaled, &result);                        \
+			zassert_equal(signaled, 1, "Signal not set");                              \
+			zassert_equal(result, (expected_event), "Signal not set");                 \
+		} while (0);                                                                       \
+	})
+
 static void stepper_print_event_callback(const struct device *dev, enum stepper_event event,
 					 void *user_data)
 {
+	const struct device *dev_callback = user_data;
 	user_data_received = user_data;
+
 	switch (event) {
 	case STEPPER_EVENT_STEPS_COMPLETED:
 		k_poll_signal_raise(&stepper_signal, STEPPER_EVENT_STEPS_COMPLETED);
@@ -33,24 +49,30 @@ static void stepper_print_event_callback(const struct device *dev, enum stepper_
 	case STEPPER_EVENT_STALL_DETECTED:
 		k_poll_signal_raise(&stepper_signal, STEPPER_EVENT_STALL_DETECTED);
 		break;
+	case STEPPER_EVENT_STOPPED:
+		k_poll_signal_raise(&stepper_signal, STEPPER_EVENT_STOPPED);
+		break;
 	default:
 		break;
 	}
+
+	LOG_DBG("Event %d, %s called for %s, expected for %s\n", event, __func__,
+		dev_callback->name, dev->name);
 }
 
 static void *stepper_setup(void)
 {
 	static struct stepper_fixture fixture = {
-		.dev = DEVICE_DT_GET(DT_NODELABEL(motor_1)),
+		.dev = DEVICE_DT_GET(DT_ALIAS(stepper)),
 		.callback = stepper_print_event_callback,
 	};
 
 	k_poll_signal_init(&stepper_signal);
 	k_poll_event_init(&stepper_event, K_POLL_TYPE_SIGNAL, K_POLL_MODE_NOTIFY_ONLY,
 			  &stepper_signal);
-	user_data_received = NULL;
+
 	zassert_not_null(fixture.dev);
-	(void)stepper_enable(fixture.dev, true);
+	(void)stepper_enable(fixture.dev);
 	return &fixture;
 }
 
@@ -58,46 +80,99 @@ static void stepper_before(void *f)
 {
 	struct stepper_fixture *fixture = f;
 	(void)stepper_set_reference_position(fixture->dev, 0);
+
 	k_poll_signal_reset(&stepper_signal);
+
+	user_data_received = NULL;
 }
 
 ZTEST_SUITE(stepper, NULL, stepper_setup, stepper_before, NULL, NULL);
 
-ZTEST_F(stepper, test_micro_step_res)
+ZTEST_F(stepper, test_set_micro_step_res_incorrect)
+{
+	int ret = stepper_set_micro_step_res(fixture->dev, 127);
+
+	zassert_equal(ret, -ENOTSUP, "Incorrect micro step resolution should return -ENOTSUP");
+}
+
+ZTEST_F(stepper, test_get_micro_step_res)
 {
-	(void)stepper_set_micro_step_res(fixture->dev, 2);
 	enum stepper_micro_step_resolution res;
 	(void)stepper_get_micro_step_res(fixture->dev, &res);
-	zassert_equal(res, 2, "Micro step resolution not set correctly");
+	zassert_equal(res, DT_PROP(DT_ALIAS(stepper), micro_step_res),
+		      "Micro step resolution not set correctly");
+}
+
+ZTEST_F(stepper, test_set_micro_step_interval_invalid_zero)
+{
+	int err = stepper_set_microstep_interval(fixture->dev, 0);
+	if (err == -ENOSYS) {
+		ztest_test_skip();
+	}
+	zassert_equal(err, -EINVAL, "ustep interval cannot be zero");
 }
 
 ZTEST_F(stepper, test_actual_position)
 {
 	int32_t pos = 100u;
-	(void)stepper_set_reference_position(fixture->dev, pos);
-	(void)stepper_get_actual_position(fixture->dev, &pos);
+	int ret;
+
+	ret = stepper_set_reference_position(fixture->dev, pos);
+	zassert_equal(ret, 0, "Failed to set reference position");
+
+	ret = stepper_get_actual_position(fixture->dev, &pos);
+	zassert_equal(ret, 0, "Failed to get actual position");
 	zassert_equal(pos, 100u, "Actual position not set correctly");
 }
 
-ZTEST_F(stepper, test_target_position)
+ZTEST_F(stepper, test_target_position_w_fixed_step_interval)
 {
-	int32_t pos = 100u;
+	int32_t pos = 10u;
+	int ret;
 
-	(void)stepper_set_max_velocity(fixture->dev, 100u);
+	ret = stepper_set_microstep_interval(fixture->dev, 100 * USEC_PER_SEC);
 
+	if (ret == -ENOSYS) {
+		ztest_test_skip();
+	}
 	/* Pass the function name as user data */
-	(void)stepper_set_event_callback(fixture->dev, fixture->callback, &fixture);
+	(void)stepper_set_event_callback(fixture->dev, fixture->callback, (void *)fixture->dev);
 
 	(void)stepper_move_to(fixture->dev, pos);
 
-	(void)k_poll(&stepper_event, 1, K_SECONDS(5));
-	unsigned int signaled;
-	int result;
+	/* timeout is set with 20% tolerance */
+	POLL_AND_CHECK_SIGNAL(stepper_signal, stepper_event, STEPPER_EVENT_STEPS_COMPLETED,
+			      K_MSEC(pos * 120));
 
-	k_poll_signal_check(&stepper_signal, &signaled, &result);
-	zassert_equal(signaled, 1, "Signal not set");
-	zassert_equal(result, STEPPER_EVENT_STEPS_COMPLETED, "Signal not set");
 	(void)stepper_get_actual_position(fixture->dev, &pos);
-	zassert_equal(pos, 100u, "Target position should be %d but is %d", 100u, pos);
-	zassert_equal(user_data_received, &fixture, "User data not received");
+	zassert_equal(pos, 10u, "Target position should be %d but is %d", 10u, pos);
+	zassert_equal(user_data_received, fixture->dev, "User data not received");
+}
+
+ZTEST_F(stepper, test_stop)
+{
+	(void)stepper_set_event_callback(fixture->dev, fixture->callback, (void *)fixture->dev);
+
+	/* Run the stepper in positive direction */
+	(void)stepper_run(fixture->dev, STEPPER_DIRECTION_POSITIVE);
+
+	/* Stop the stepper */
+	int ret = stepper_stop(fixture->dev);
+	bool is_moving;
+
+	if (ret == 0) {
+		POLL_AND_CHECK_SIGNAL(stepper_signal, stepper_event, STEPPER_EVENT_STOPPED,
+				      K_NO_WAIT);
+		zassert_equal(user_data_received, fixture->dev, "User data not received");
+
+		/* Check if the stepper is stopped */
+		stepper_is_moving(fixture->dev, &is_moving);
+		zassert_equal(is_moving, false, "Stepper is still moving");
+	} else if (ret == -ENOSYS) {
+		stepper_is_moving(fixture->dev, &is_moving);
+		zassert_equal(is_moving, true,
+			      "Stepper should be moving since stop is not implemented");
+	} else {
+		zassert_unreachable("Stepper stop failed");
+	}
 }
diff --git a/tests/drivers/stepper/stepper_api/testcase.yaml b/tests/drivers/stepper/stepper_api/testcase.yaml
index 6936bea7c5b..424e258fcaf 100644
--- a/tests/drivers/stepper/stepper_api/testcase.yaml
+++ b/tests/drivers/stepper/stepper_api/testcase.yaml
@@ -1,13 +1,45 @@
 # SPDX-FileCopyrightText: Copyright (c) 2024 Jilay Sandeep Pandya
 # SPDX-License-Identifier: Apache-2.0
 
+common:
+  tags:
+    - drivers
+    - stepper
+    - api
 tests:
-  drivers.stepper.stepper_api:
-    tags:
-      - drivers
-      - stepper
-      - api
-    platform_allow:
-      - nucleo_g071rb
-      - nucleo_f767zi
-      - qemu_x86_64
+  drivers.stepper.stepper_api.adi_tmc2209:
+    extra_args:
+      - platform:native_sim/native/64:DTC_OVERLAY_FILE="boards/native_sim_adi_tmc2209.overlay"
+    extra_configs:
+      - CONFIG_GPIO=y
+      - CONFIG_COUNTER=y
+      - CONFIG_STEPPER_STEP_DIR_GENERATE_ISR_SAFE_EVENTS=y
+    platform_allow:
+      - native_sim/native/64
+  drivers.stepper.stepper_api.allegro_a4979:
+    extra_args:
+      - platform:native_sim/native/64:DTC_OVERLAY_FILE="boards/native_sim_allegro_a4979.overlay"
+    extra_configs:
+      - CONFIG_GPIO=y
+      - CONFIG_COUNTER=y
+      - CONFIG_STEPPER_STEP_DIR_GENERATE_ISR_SAFE_EVENTS=y
+    platform_allow:
+      - native_sim/native/64
+  drivers.stepper.stepper_api.ti_drv84xx:
+    extra_args:
+      - platform:native_sim/native/64:DTC_OVERLAY_FILE="boards/native_sim_ti_drv84xx.overlay"
+    extra_configs:
+      - CONFIG_GPIO=y
+      - CONFIG_COUNTER=y
+      - CONFIG_STEPPER_STEP_DIR_GENERATE_ISR_SAFE_EVENTS=y
+    platform_allow:
+      - native_sim/native/64
+  drivers.stepper.stepper_api.zephyr_gpio_stepper:
+    extra_args:
+      - platform:native_sim/native/64:DTC_OVERLAY_FILE="boards/native_sim_zephyr_gpio_stepper.overlay"
+      - platform:qemu_x86_64/atom:DTC_OVERLAY_FILE="boards/qemu_x86_64_zephyr_gpio_stepper.overlay"
+    extra_configs:
+      - CONFIG_GPIO=y
+    platform_allow:
+      - native_sim/native/64
+      - qemu_x86_64/atom
diff --git a/tests/drivers/syscon/prj.conf b/tests/drivers/syscon/prj.conf
index 9970e77ce57..220246c1327 100644
--- a/tests/drivers/syscon/prj.conf
+++ b/tests/drivers/syscon/prj.conf
@@ -3,6 +3,5 @@
 
 CONFIG_ZTEST=y
 CONFIG_SYSCON=y
-CONFIG_MMU=y
 CONFIG_HAVE_CUSTOM_LINKER_SCRIPT=y
 CONFIG_CUSTOM_LINKER_SCRIPT="linker_arm64_reserved.ld"
diff --git a/tests/drivers/timer/nrf_grtc_timer/testcase.yaml b/tests/drivers/timer/nrf_grtc_timer/testcase.yaml
index 73dc8cc6170..ece1358741a 100644
--- a/tests/drivers/timer/nrf_grtc_timer/testcase.yaml
+++ b/tests/drivers/timer/nrf_grtc_timer/testcase.yaml
@@ -3,6 +3,7 @@ tests:
     tags: drivers
     platform_allow:
       - nrf54l09pdk/nrf54l09/cpuapp
+      - nrf54l09pdk/nrf54l09/cpuflpr
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l15dk/nrf54l15/cpuflpr
       - nrf54l15bsim/nrf54l15/cpuapp
@@ -10,5 +11,8 @@ tests:
       - nrf54h20dk/nrf54h20/cpurad
       - nrf54h20dk/nrf54h20/cpuppr
       - nrf54l20pdk/nrf54l20/cpuapp
+      - nrf54l20pdk/nrf54l20/cpuflpr
+      - ophelia4ev/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuflpr
     integration_platforms:
       - nrf54l20pdk/nrf54l20/cpuapp
diff --git a/tests/drivers/uart/uart_async_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay b/tests/drivers/uart/uart_async_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay
new file mode 100644
index 00000000000..2170eac1179
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15_dvk_nrf54l15_cpuapp.overlay"
diff --git a/tests/drivers/uart/uart_async_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_async_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..c2c8839e38e
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi00 {
+	status = "disabled";
+};
+
+&pinctrl {
+	uart21_default_alt: uart21_default_alt {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+		};
+	};
+
+	uart21_sleep_alt: uart21_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+			low-power-enable;
+		};
+	};
+
+	uart00_default_alt: uart00_default_alt {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 2, 8)>,
+				<NRF_PSEL(UART_RX, 2, 7)>;
+		};
+	};
+
+	uart00_sleep_alt: uart00_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 2, 8)>,
+				<NRF_PSEL(UART_RX, 2, 7)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	pinctrl-0 = <&uart21_default_alt>;
+	pinctrl-1 = <&uart21_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	current-speed = <115200>;
+};
+
+dut2: &uart00 {
+	status = "okay";
+	pinctrl-0 = <&uart00_default_alt>;
+	pinctrl-1 = <&uart00_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	current-speed = <4000000>;
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay b/tests/drivers/uart/uart_async_api/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..2170eac1179
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15_dvk_nrf54l15_cpuapp.overlay"
diff --git a/tests/drivers/uart/uart_async_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_async_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..c2c8839e38e
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&spi00 {
+	status = "disabled";
+};
+
+&pinctrl {
+	uart21_default_alt: uart21_default_alt {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+		};
+	};
+
+	uart21_sleep_alt: uart21_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+			low-power-enable;
+		};
+	};
+
+	uart00_default_alt: uart00_default_alt {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 2, 8)>,
+				<NRF_PSEL(UART_RX, 2, 7)>;
+		};
+	};
+
+	uart00_sleep_alt: uart00_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 2, 8)>,
+				<NRF_PSEL(UART_RX, 2, 7)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	pinctrl-0 = <&uart21_default_alt>;
+	pinctrl-1 = <&uart21_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	current-speed = <115200>;
+};
+
+dut2: &uart00 {
+	status = "okay";
+	pinctrl-0 = <&uart00_default_alt>;
+	pinctrl-1 = <&uart00_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	current-speed = <4000000>;
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay b/tests/drivers/uart/uart_async_api/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..9b848a08370
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "bl54l15u_dvk_nrf54l15_cpuapp.overlay"
diff --git a/tests/drivers/uart/uart_async_api/boards/cy8cproto_062_4343w.overlay b/tests/drivers/uart/uart_async_api/boards/cy8cproto_062_4343w.overlay
new file mode 100644
index 00000000000..8ebe0045654
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/cy8cproto_062_4343w.overlay
@@ -0,0 +1,27 @@
+&dma0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "infineon,cat1-dma";
+	status = "okay";
+};
+
+&p6_1_scb3_uart_tx {
+	drive-push-pull;
+};
+
+&p6_0_scb3_uart_rx {
+	input-enable;
+};
+
+
+dut: &scb3 {
+	compatible = "infineon,cat1-uart";
+	status = "okay";
+	current-speed = <115200>;
+
+	pinctrl-0 = <&p6_1_scb3_uart_tx &p6_0_scb3_uart_rx>;
+	pinctrl-names = "default";
+
+	dmas = <&dma0 22>, <&dma0 23>;
+	dma-names = "tx", "rx";
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/cy8cproto_063_ble.overlay b/tests/drivers/uart/uart_async_api/boards/cy8cproto_063_ble.overlay
new file mode 100644
index 00000000000..41d9e39187c
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/cy8cproto_063_ble.overlay
@@ -0,0 +1,11 @@
+&dma0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "infineon,cat1-dma";
+	status = "okay";
+};
+
+dut: &scb5 {
+	dmas = <&dma0 22>, <&dma0 23>;
+	dma-names = "tx", "rx";
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/cyw920829m2evk_02.conf b/tests/drivers/uart/uart_async_api/boards/cyw920829m2evk_02.conf
new file mode 100644
index 00000000000..025ef088cbe
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/cyw920829m2evk_02.conf
@@ -0,0 +1,2 @@
+CONFIG_TEST_USERSPACE=n
+CONFIG_DMA=y
diff --git a/tests/drivers/uart/uart_async_api/boards/cyw920829m2evk_02.overlay b/tests/drivers/uart/uart_async_api/boards/cyw920829m2evk_02.overlay
new file mode 100644
index 00000000000..26d7b41a76c
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/cyw920829m2evk_02.overlay
@@ -0,0 +1,27 @@
+&dma0 {
+	#address-cells = <1>;
+	#size-cells = <0>;
+	compatible = "infineon,cat1-dma";
+
+	status = "okay";
+};
+
+dut: &scb1 {
+	compatible = "infineon,cat1-uart";
+	status = "okay";
+	current-speed = <115200>;
+
+	dmas = <&dma0 6>, <&dma0 7>;
+	dma-names = "tx", "rx";
+
+	pinctrl-0 = <&p1_3_scb1_uart_tx &p1_2_scb1_uart_rx>;
+	pinctrl-names = "default";
+};
+
+&p1_3_scb1_uart_tx {
+	drive-push-pull;
+};
+
+&p1_2_scb1_uart_rx {
+	input-enable;
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra2a1.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra2a1.overlay
new file mode 100644
index 00000000000..50cafd978b6
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/ek_ra2a1.overlay
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci1_default: sci1_default {
+		group1 {
+			/* tx rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_1, 4, 10)>,
+			<RA_PSEL(RA_PSEL_SCI_1, 4, 11)>;
+		};
+	};
+};
+
+&sci1 {
+	pinctrl-0 = <&sci1_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	dut: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra2l1.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra2l1.overlay
new file mode 100644
index 00000000000..c12f59bbeee
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/ek_ra2l1.overlay
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci9_default: sci9_default {
+		group1 {
+			/* tx rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_9, 2, 3)>,
+			<RA_PSEL(RA_PSEL_SCI_9, 2, 2)>;
+		};
+	};
+};
+
+&sci9 {
+	pinctrl-0 = <&sci9_default>;
+	pinctrl-names = "default";
+	interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
+	interrupt-names = "rxi", "txi", "tei", "eri";
+	status = "okay";
+
+	dut: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra4l1.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra4l1.overlay
new file mode 100644
index 00000000000..e8343b61c6c
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/ek_ra4l1.overlay
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci9_default: sci9_default {
+		group1 {
+			/* tx rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_9, 5, 10)>,
+			<RA_PSEL(RA_PSEL_SCI_9, 5, 11)>;
+		};
+	};
+};
+
+&sci9 {
+	pinctrl-0 = <&sci9_default>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	dut: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/ek_ra4m1.overlay b/tests/drivers/uart/uart_async_api/boards/ek_ra4m1.overlay
new file mode 100644
index 00000000000..6bf3f9ce967
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/ek_ra4m1.overlay
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci9_default: sci9_default {
+		group1 {
+			/* tx rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_9, 6, 2)>,
+			<RA_PSEL(RA_PSEL_SCI_9, 6, 1)>;
+		};
+	};
+};
+
+&sci9 {
+	pinctrl-0 = <&sci9_default>;
+	pinctrl-names = "default";
+	interrupts = <28 1>, <29 1>, <30 1>, <31 1>;
+	interrupt-names = "rxi", "txi", "tei", "eri";
+	status = "okay";
+	dut: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/esp32c6_devkitc.conf b/tests/drivers/uart/uart_async_api/boards/esp32c6_devkitc_hpcore.conf
similarity index 100%
rename from tests/drivers/uart/uart_async_api/boards/esp32c6_devkitc.conf
rename to tests/drivers/uart/uart_async_api/boards/esp32c6_devkitc_hpcore.conf
diff --git a/tests/drivers/uart/uart_async_api/boards/esp32c6_devkitc.overlay b/tests/drivers/uart/uart_async_api/boards/esp32c6_devkitc_hpcore.overlay
similarity index 100%
rename from tests/drivers/uart/uart_async_api/boards/esp32c6_devkitc.overlay
rename to tests/drivers/uart/uart_async_api/boards/esp32c6_devkitc_hpcore.overlay
diff --git a/tests/drivers/uart/uart_async_api/boards/fpb_ra4e1.overlay b/tests/drivers/uart/uart_async_api/boards/fpb_ra4e1.overlay
new file mode 100644
index 00000000000..98d8c87cc7f
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/fpb_ra4e1.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci9_default: sci9_default {
+		group1 {
+			/* tx rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_9, 1, 9)>,
+			<RA_PSEL(RA_PSEL_SCI_9, 1, 10)>;
+		};
+	};
+};
+
+&spi0 {
+	status = "disabled";
+};
+
+&sci9 {
+	pinctrl-0 = <&sci9_default>;
+	pinctrl-names = "default";
+	status = "okay";
+	dut: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/frdm_mcxa153.overlay b/tests/drivers/uart/uart_async_api/boards/frdm_mcxa153.overlay
new file mode 100644
index 00000000000..063593ce5af
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/frdm_mcxa153.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Short J5.3(P3_14) and J5.4(P3_15) to loopback LPUART2 RX/TX for this test
+ * or test lpuart2 with "nxp,loopback"
+ */
+dut: &lpuart2 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&pinmux_lpuart2>;
+	pinctrl-names = "default";
+};
+
+&edma0 {
+	status = "okay";
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/frdm_mcxa166.overlay b/tests/drivers/uart/uart_async_api/boards/frdm_mcxa166.overlay
new file mode 100644
index 00000000000..401284b77b9
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/frdm_mcxa166.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Short J5.3 and J5.4 to loopback LPUART3 RX/TX for this test
+ * or test lpuart3 with "nxp,loopback"
+ */
+dut: &lpuart3 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&pinmux_lpuart3>;
+	pinctrl-names = "default";
+};
+
+&edma0 {
+	status = "okay";
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/frdm_mcxa276.overlay b/tests/drivers/uart/uart_async_api/boards/frdm_mcxa276.overlay
new file mode 100644
index 00000000000..401284b77b9
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/frdm_mcxa276.overlay
@@ -0,0 +1,19 @@
+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Short J5.3 and J5.4 to loopback LPUART3 RX/TX for this test
+ * or test lpuart3 with "nxp,loopback"
+ */
+dut: &lpuart3 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&pinmux_lpuart3>;
+	pinctrl-names = "default";
+};
+
+&edma0 {
+	status = "okay";
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/intel_rpl_s_crb.conf b/tests/drivers/uart/uart_async_api/boards/intel_rpl_s_crb.conf
index 86df0aff3e6..1104c4d7391 100644
--- a/tests/drivers/uart/uart_async_api/boards/intel_rpl_s_crb.conf
+++ b/tests/drivers/uart/uart_async_api/boards/intel_rpl_s_crb.conf
@@ -1 +1,2 @@
 CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_TEST_USERSPACE=n
diff --git a/tests/drivers/uart/uart_async_api/boards/max32655evkit_max32655_m4.overlay b/tests/drivers/uart/uart_async_api/boards/max32655evkit_max32655_m4.overlay
new file mode 100644
index 00000000000..37f9c30c090
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/max32655evkit_max32655_m4.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+dut: &uart3 {
+	status = "okay";
+	pinctrl-0 = <&lpuartb_tx_p2_7 &lpuartb_rx_p2_6>;
+	pinctrl-names = "default";
+
+	dmas = <&dma0 1 MAX32_DMA_SLOT_UART3_TX>, <&dma0 2 MAX32_DMA_SLOT_UART3_RX>;
+	dma-names = "tx", "rx";
+
+	current-speed = <115200>;
+	data-bits = <8>;
+	parity = "none";
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/max32655fthr_max32655_m4.overlay b/tests/drivers/uart/uart_async_api/boards/max32655fthr_max32655_m4.overlay
new file mode 100644
index 00000000000..37f9c30c090
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/max32655fthr_max32655_m4.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+dut: &uart3 {
+	status = "okay";
+	pinctrl-0 = <&lpuartb_tx_p2_7 &lpuartb_rx_p2_6>;
+	pinctrl-names = "default";
+
+	dmas = <&dma0 1 MAX32_DMA_SLOT_UART3_TX>, <&dma0 2 MAX32_DMA_SLOT_UART3_RX>;
+	dma-names = "tx", "rx";
+
+	current-speed = <115200>;
+	data-bits = <8>;
+	parity = "none";
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/max32666evkit_max32666_cpu0.overlay b/tests/drivers/uart/uart_async_api/boards/max32666evkit_max32666_cpu0.overlay
new file mode 100644
index 00000000000..57f40fb2747
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/max32666evkit_max32666_cpu0.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+dut: &uart0 {
+	status = "okay";
+	pinctrl-0 = <&uart0_tx_p0_9 &uart0_rx_p0_10>;
+	pinctrl-names = "default";
+
+	dmas = <&dma0 1 MAX32_DMA_SLOT_UART0_TX>, <&dma0 2 MAX32_DMA_SLOT_UART0_RX>;
+	dma-names = "tx", "rx";
+
+	current-speed = <115200>;
+	data-bits = <8>;
+	parity = "none";
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/max32666fthr_max32666_cpu0.overlay b/tests/drivers/uart/uart_async_api/boards/max32666fthr_max32666_cpu0.overlay
new file mode 100644
index 00000000000..57f40fb2747
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/max32666fthr_max32666_cpu0.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+dut: &uart0 {
+	status = "okay";
+	pinctrl-0 = <&uart0_tx_p0_9 &uart0_rx_p0_10>;
+	pinctrl-names = "default";
+
+	dmas = <&dma0 1 MAX32_DMA_SLOT_UART0_TX>, <&dma0 2 MAX32_DMA_SLOT_UART0_RX>;
+	dma-names = "tx", "rx";
+
+	current-speed = <115200>;
+	data-bits = <8>;
+	parity = "none";
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/max32670evkit.overlay b/tests/drivers/uart/uart_async_api/boards/max32670evkit.overlay
new file mode 100644
index 00000000000..94b88ae2d56
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/max32670evkit.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+dut: &uart1 {
+	status = "okay";
+	pinctrl-0 = <&uart1a_tx_p0_29 &uart1a_rx_p0_28>;
+	pinctrl-names = "default";
+
+	dmas = <&dma0 1 MAX32_DMA_SLOT_UART1_TX>, <&dma0 2 MAX32_DMA_SLOT_UART1_RX>;
+	dma-names = "tx", "rx";
+
+	current-speed = <115200>;
+	data-bits = <8>;
+	parity = "none";
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/max32690evkit_max32690_m4.overlay b/tests/drivers/uart/uart_async_api/boards/max32690evkit_max32690_m4.overlay
new file mode 100644
index 00000000000..7c321a8103a
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/max32690evkit_max32690_m4.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+dut: &uart0 {
+	status = "okay";
+	pinctrl-0 = <&uart0a_tx_p2_12 &uart0a_rx_p2_11>;
+	pinctrl-names = "default";
+
+	dmas = <&dma0 1 MAX32_DMA_SLOT_UART0_TX>, <&dma0 2 MAX32_DMA_SLOT_UART0_RX>;
+	dma-names = "tx", "rx";
+
+	current-speed = <115200>;
+	data-bits = <8>;
+	parity = "none";
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/max78002evkit_max78002_m4.overlay b/tests/drivers/uart/uart_async_api/boards/max78002evkit_max78002_m4.overlay
new file mode 100644
index 00000000000..e5f154d43e1
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/max78002evkit_max78002_m4.overlay
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+dut: &uart1 {
+	status = "okay";
+	pinctrl-0 = <&uart1_tx_p0_13 &uart1_rx_p0_12>;
+	pinctrl-names = "default";
+
+	dmas = <&dma0 1 MAX78_DMA_SLOT_UART1_TX>, <&dma0 2 MAX78_DMA_SLOT_UART1_RX>;
+	dma-names = "tx", "rx";
+
+	current-speed = <115200>;
+	data-bits = <8>;
+	parity = "none";
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay b/tests/drivers/uart/uart_async_api/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..824fafd9e1a
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/mcx_n9xx_evk_mcxn947_cpu0.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024-2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * To test this sample connect P4_2(J1-4) to P4_3(J1-2)
+ */
+dut: &flexcomm2_lpuart2 {};
diff --git a/tests/drivers/uart/uart_async_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay b/tests/drivers/uart/uart_async_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay
new file mode 100644
index 00000000000..827b5eaf259
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/mcx_n9xx_evk_mcxn947_cpu0_qspi.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * To test this sample connect P4_2(J1-4) to P4_3(J1-2)
+ */
+dut: &flexcomm2_lpuart2 {};
diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/tests/drivers/uart/uart_async_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
new file mode 100644
index 00000000000..22ecfdfa712
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+dut: &lpuart3 {
+	status = "okay";
+	current-speed = <115200>;
+	nxp,loopback;
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/mimxrt1180_evk_mimxrt1189_cm7.conf b/tests/drivers/uart/uart_async_api/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
new file mode 100644
index 00000000000..cf4dcd316a9
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/mimxrt1180_evk_mimxrt1189_cm7.conf
@@ -0,0 +1,6 @@
+#
+# Copyright 2024 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+CONFIG_DMA_MCUX_USE_DTCM_FOR_DMA_DESCRIPTORS=n
diff --git a/tests/drivers/uart/uart_async_api/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay b/tests/drivers/uart/uart_async_api/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay
new file mode 100644
index 00000000000..ed4a2de1891
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+&pinctrl {
+	uart21_default_alt: uart21_default_alt {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+		};
+	};
+
+	uart21_sleep_alt: uart21_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	pinctrl-0 = <&uart21_default_alt>;
+	pinctrl-1 = <&uart21_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	current-speed = <115200>;
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/nucleo_c071rb.overlay b/tests/drivers/uart/uart_async_api/boards/nucleo_c071rb.overlay
new file mode 100644
index 00000000000..7b1551e83e1
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/nucleo_c071rb.overlay
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+dut: &usart1 {
+	dmas = <&dmamux1 3 51 STM32_DMA_PERIPH_TX>,
+	       <&dmamux1 4 50 STM32_DMA_PERIPH_RX>;
+	dma-names = "tx", "rx";
+};
+
+&dma1 {
+	status = "okay";
+};
+
+&dmamux1 {
+	status = "okay";
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/nucleo_n657x0_q_stm32n657xx_sb.conf b/tests/drivers/uart/uart_async_api/boards/nucleo_n657x0_q_stm32n657xx_sb.conf
new file mode 100644
index 00000000000..3d5e58683e7
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/nucleo_n657x0_q_stm32n657xx_sb.conf
@@ -0,0 +1,2 @@
+CONFIG_NOCACHE_MEMORY=y
+CONFIG_TEST_USERSPACE=n
diff --git a/tests/drivers/uart/uart_async_api/boards/nucleo_n657x0_q_stm32n657xx_sb.overlay b/tests/drivers/uart/uart_async_api/boards/nucleo_n657x0_q_stm32n657xx_sb.overlay
new file mode 100644
index 00000000000..603ecebccb9
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/nucleo_n657x0_q_stm32n657xx_sb.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+dut: &usart3 {
+	dmas = <&gpdma1 0 112 STM32_DMA_PERIPH_TX
+		&gpdma1 1 111 STM32_DMA_PERIPH_RX>;
+	dma-names = "tx", "rx";
+};
+
+&gpdma1 {
+	status = "okay";
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/nucleo_wba52cg.overlay b/tests/drivers/uart/uart_async_api/boards/nucleo_wba55cg.overlay
similarity index 100%
rename from tests/drivers/uart/uart_async_api/boards/nucleo_wba52cg.overlay
rename to tests/drivers/uart/uart_async_api/boards/nucleo_wba55cg.overlay
diff --git a/tests/drivers/uart/uart_async_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_async_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..a1e29cbf0ff
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+&spi00 {
+	status = "disabled";
+};
+
+&pinctrl {
+	uart21_default_alt: uart21_default_alt {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+		};
+	};
+
+	uart21_sleep_alt: uart21_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+			low-power-enable;
+		};
+	};
+
+	uart00_default_alt: uart00_default_alt {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 2, 8)>,
+				<NRF_PSEL(UART_RX, 2, 7)>;
+		};
+	};
+
+	uart00_sleep_alt: uart00_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 2, 8)>,
+				<NRF_PSEL(UART_RX, 2, 7)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	pinctrl-0 = <&uart21_default_alt>;
+	pinctrl-1 = <&uart21_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	current-speed = <115200>;
+};
+
+dut2: &uart00 {
+	status = "okay";
+	pinctrl-0 = <&uart00_default_alt>;
+	pinctrl-1 = <&uart00_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	current-speed = <4000000>;
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/ophelia4ev_nrf54l15_cpuflpr.overlay b/tests/drivers/uart/uart_async_api/boards/ophelia4ev_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..945d543e753
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/ophelia4ev_nrf54l15_cpuflpr.overlay
@@ -0,0 +1 @@
+#include "ophelia4ev_nrf54l15_cpuapp.overlay"
diff --git a/tests/drivers/uart/uart_async_api/boards/slwrb4180a.overlay b/tests/drivers/uart/uart_async_api/boards/slwrb4180a.overlay
new file mode 100644
index 00000000000..1d0220a86bc
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/slwrb4180a.overlay
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2025, Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Need to connect PC0 and PC1 of the Expension Pin header
+ */
+/ {
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+		zephyr,uart-pipe = &usart1;
+	};
+};
+
+&pinctrl{
+	usart0_default: usart0_default {
+		group0 {
+			pins = <USART0_TX_PC0>;
+			drive-push-pull;
+			output-high;
+		};
+		group1 {
+			pins = <USART0_RX_PC1>;
+			input-enable;
+			silabs,input-filter;
+		};
+	};
+	usart1_default: usart1_default {
+		group0 {
+			pins = <USART1_TX_PA5>;
+			drive-push-pull;
+			output-high;
+		};
+		group1 {
+			pins = <USART1_RX_PA6>;
+			input-enable;
+			silabs,input-filter;
+		};
+	};
+};
+
+dut: &usart0 {
+	dmas = <&dma0 DMA_REQSEL_USART0TXBL>,
+	       <&dma0 DMA_REQSEL_USART0RXDATAV>;
+	dma-names = "tx", "rx";
+	pinctrl-0 = <&usart0_default>;
+	pinctrl-names = "default";
+};
+
+&usart1 {
+	current-speed = <115200>;
+	pinctrl-0 = <&usart1_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&dma0 {
+	status = "okay";
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/stm32n6570_dk_stm32n657xx_sb.conf b/tests/drivers/uart/uart_async_api/boards/stm32n6570_dk_stm32n657xx_sb.conf
new file mode 100644
index 00000000000..3d5e58683e7
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/stm32n6570_dk_stm32n657xx_sb.conf
@@ -0,0 +1,2 @@
+CONFIG_NOCACHE_MEMORY=y
+CONFIG_TEST_USERSPACE=n
diff --git a/tests/drivers/uart/uart_async_api/boards/stm32n6570_dk_stm32n657xx_sb.overlay b/tests/drivers/uart/uart_async_api/boards/stm32n6570_dk_stm32n657xx_sb.overlay
new file mode 100644
index 00000000000..7127f08c42c
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/stm32n6570_dk_stm32n657xx_sb.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+dut: &usart2 {
+	dmas = <&gpdma1 0 110 STM32_DMA_PERIPH_TX
+		&gpdma1 1 109 STM32_DMA_PERIPH_RX>;
+	dma-names = "tx", "rx";
+};
+
+&gpdma1 {
+	status = "okay";
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/voice_ra4e1.overlay b/tests/drivers/uart/uart_async_api/boards/voice_ra4e1.overlay
new file mode 100644
index 00000000000..e276242dbbe
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/voice_ra4e1.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci0_default: sci0_default {
+		group1 {
+			/* tx rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_0, 1, 1)>,
+			<RA_PSEL(RA_PSEL_SCI_0, 1, 0)>;
+		};
+	};
+};
+
+&sci0 {
+	pinctrl-0 = <&sci0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+	dut: uart {
+		current-speed = <115200>;
+		status = "okay";
+	};
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/xg23_rb4210a.overlay b/tests/drivers/uart/uart_async_api/boards/xg23_rb4210a.overlay
new file mode 100644
index 00000000000..e275da0aa61
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/xg23_rb4210a.overlay
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2025, Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ /*
+  * Connect EXP4 (PC0) and EXP6 (PC1) of the Expansion Pin header
+  */
+/ {
+	chosen {
+		zephyr,console = &usart0;
+		zephyr,shell-uart = &usart0;
+		zephyr,uart-pipe = &usart0;
+		/delete-property/ zephyr,display;
+	};
+};
+
+&pinctrl{
+	eusart1_default: eusart1_default {
+		group0 {
+			pins = <EUSART1_TX_PC1>; /* WPK EXP4 (PC1) */
+			drive-push-pull;
+			output-high;
+		};
+		group1 {
+			pins = <EUSART1_RX_PC2>; /* WPK EXP6 (PC2) */
+			input-enable;
+			silabs,input-filter;
+		};
+	};
+
+	usart0_default: usart0_default {
+		group0 {
+			pins = <USART0_TX_PA8>;
+			drive-push-pull;
+			output-high;
+		};
+		group1 {
+			pins = <USART0_RX_PA9>;
+			input-enable;
+			silabs,input-filter;
+		};
+	};
+};
+
+dut: &eusart1 {
+	compatible = "silabs,eusart-uart";
+	dmas = <&dma0 DMA_REQSEL_EUSART1TXFL>,
+		<&dma0 DMA_REQSEL_EUSART1RXFL>;
+	dma-names = "tx", "rx";
+	current-speed = <115200>;
+	pinctrl-0 = <&eusart1_default>;
+	pinctrl-names = "default";
+	status = "okay";
+	/delete-property/ cs-gpios;
+};
+
+/delete-node/ &ls0xx_ls013b7dh03;
+/delete-node/ &mx25r80;
+
+&eusart0 {
+	status = "disabled";
+};
+
+&usart0 {
+	compatible = "silabs,usart-uart";
+	current-speed = <115200>;
+	pinctrl-0 = <&usart0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&dma0 {
+	status = "okay";
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/xg24_rb4187c.overlay b/tests/drivers/uart/uart_async_api/boards/xg24_rb4187c.overlay
new file mode 100644
index 00000000000..1e9c88c1033
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/xg24_rb4187c.overlay
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2025, Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Need to connect PC1 and PC2 of the Expension Pin header
+ */
+/ {
+	chosen {
+		zephyr,console = &eusart0;
+		zephyr,shell-uart = &eusart0;
+		zephyr,uart-pipe = &eusart0;
+	};
+};
+
+&pinctrl{
+	usart0_default: usart0_default {
+		group0 {
+			pins = <USART0_TX_PC1>;
+			drive-push-pull;
+			output-high;
+		};
+		group1 {
+			pins = <USART0_RX_PC2>;
+			input-enable;
+			silabs,input-filter;
+		};
+	};
+	eusart0_default: eusart0_default {
+		group0 {
+			pins = <EUSART0_TX_PA8>;
+			drive-push-pull;
+			output-high;
+		};
+		group1 {
+			pins = <EUSART0_RX_PA9>;
+			input-enable;
+			silabs,input-filter;
+		};
+	};
+};
+
+dut: &usart0 {
+	dmas = <&dma0 DMA_REQSEL_USART0TXBL>,
+	       <&dma0 DMA_REQSEL_USART0RXDATAV>;
+	dma-names = "tx", "rx";
+	pinctrl-0 = <&usart0_default>;
+	pinctrl-names = "default";
+};
+
+&eusart0 {
+	compatible = "silabs,eusart-uart";
+	current-speed = <115200>;
+	pinctrl-0 = <&eusart0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&dma0 {
+	status = "okay";
+};
diff --git a/tests/drivers/uart/uart_async_api/boards/xg29_rb4412a.overlay b/tests/drivers/uart/uart_async_api/boards/xg29_rb4412a.overlay
new file mode 100644
index 00000000000..9f599003dbc
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/boards/xg29_rb4412a.overlay
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2025, Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Connect EXP4 (PC0) and EXP6 (PC1) of the Expansion Pin header
+ */
+/ {
+	chosen {
+		zephyr,console = &eusart0;
+		zephyr,shell-uart = &eusart0;
+		zephyr,uart-pipe = &eusart0;
+	};
+};
+
+&pinctrl{
+	usart0_default: usart0_default {
+		group0 {
+			pins = <USART0_TX_PC0>; /* WPK EXP4 (PC0) */
+			drive-push-pull;
+			output-high;
+		};
+		group1 {
+			pins = <USART0_RX_PC1>; /* WPK EXP6 (PC1) */
+			input-enable;
+			silabs,input-filter;
+		};
+	};
+	eusart0_default: eusart0_default {
+		group0 {
+			pins = <EUSART0_TX_PA5>;
+			drive-push-pull;
+			output-high;
+		};
+		group1 {
+			pins = <EUSART0_RX_PA6>;
+			input-enable;
+			silabs,input-filter;
+		};
+	};
+};
+
+dut: &usart0 {
+	dmas = <&dma0 DMA_REQSEL_USART0TXBL>,
+	       <&dma0 DMA_REQSEL_USART0RXDATAV>;
+	dma-names = "tx", "rx";
+	pinctrl-0 = <&usart0_default>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&eusart0 {
+	compatible = "silabs,eusart-uart";
+	current-speed = <115200>;
+	pinctrl-0 = <&eusart0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&dma0 {
+	status = "okay";
+};
+
+&eusart1 {
+	status = "disabled";
+};
+
+&usart1 {
+	status = "disabled";
+};
diff --git a/tests/drivers/uart/uart_async_api/socs/esp32c3_usb.conf b/tests/drivers/uart/uart_async_api/socs/esp32c3_usb.conf
new file mode 100644
index 00000000000..76f7644d896
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/socs/esp32c3_usb.conf
@@ -0,0 +1,2 @@
+CONFIG_HEAP_MEM_POOL_SIZE=32768
+CONFIG_DMA=y
diff --git a/tests/drivers/uart/uart_async_api/socs/esp32c3_usb.overlay b/tests/drivers/uart/uart_async_api/socs/esp32c3_usb.overlay
new file mode 100644
index 00000000000..3582e7dcf94
--- /dev/null
+++ b/tests/drivers/uart/uart_async_api/socs/esp32c3_usb.overlay
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart1_test: uart1_test {
+		group1 {
+			pinmux = <UART1_TX_GPIO5>;
+			input-enable;
+		};
+		group2 {
+			pinmux = <UART1_RX_GPIO5>;
+			output-enable;
+		};
+	};
+};
+
+dut: &uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart1_test>;
+	pinctrl-names = "default";
+	dmas = <&dma 0>, <&dma 1>;
+	dma-names = "rx", "tx";
+};
+
+&dma {
+	status = "okay";
+};
diff --git a/tests/drivers/uart/uart_async_api/src/test_uart_async.c b/tests/drivers/uart/uart_async_api/src/test_uart_async.c
index 027087cd265..d0b1ac779c6 100644
--- a/tests/drivers/uart/uart_async_api/src/test_uart_async.c
+++ b/tests/drivers/uart/uart_async_api/src/test_uart_async.c
@@ -223,7 +223,7 @@ ZTEST_USER(uart_async_single_read, test_single_read)
 	sent_bytes += 5;
 
 	zassert_equal(k_sem_take(&tx_done, K_MSEC(100)), 0, "TX_DONE timeout");
-	zassert_equal(k_sem_take(&rx_rdy, K_MSEC(100)), 0, "RX_RDY timeout");
+	zassert_equal(k_sem_take(&rx_rdy, K_MSEC(105)), 0, "RX_RDY timeout");
 	zassert_equal(k_sem_take(&rx_rdy, K_MSEC(100)), -EAGAIN,
 		      "Extra RX_RDY received");
 
@@ -352,13 +352,13 @@ ZTEST_USER(uart_async_multi_rx, test_multiple_rx_enable)
 /* To ensure 32-bit alignment of the buffer array,
  * the two arrays are defined instead using an array of arrays
  */
-static __aligned(32) uint8_t chained_read_buf_0[8] __used __NOCACHE;
-static __aligned(32) uint8_t chained_read_buf_1[8] __used __NOCACHE;
+static __aligned(32) uint8_t chained_read_buf_0[10] __used __NOCACHE;
+static __aligned(32) uint8_t chained_read_buf_1[10] __used __NOCACHE;
 static __aligned(32) uint8_t chained_cpy_buf[10] __used __NOCACHE;
 #else
-static ZTEST_BMEM uint8_t chained_read_buf_0[8];
-static ZTEST_BMEM uint8_t chained_read_buf_1[8];
-static ZTEST_BMEM uint8_t chained_cpy_buf[10];
+ZTEST_BMEM uint8_t chained_read_buf_0[10];
+ZTEST_BMEM uint8_t chained_read_buf_1[10];
+ZTEST_BMEM uint8_t chained_cpy_buf[10];
 #endif /* NOCACHE_MEM */
 static ZTEST_BMEM volatile uint8_t rx_data_idx;
 static ZTEST_BMEM uint8_t rx_buf_idx;
@@ -414,7 +414,7 @@ ZTEST_USER(uart_async_chain_read, test_chained_read)
 #if NOCACHE_MEM
 	static __aligned(32) uint8_t tx_buf[10] __used __NOCACHE;
 #else
-	uint8_t tx_buf[10];
+	 __aligned(32) uint8_t tx_buf[10];
 #endif /* NOCACHE_MEM */
 	int iter = 6;
 	uint32_t rx_timeout_ms = 50;
@@ -496,15 +496,12 @@ ZTEST_USER(uart_async_double_buf, test_double_buffer)
 #if NOCACHE_MEM
 	static __aligned(32) uint8_t tx_buf[4] __used __NOCACHE;
 #else
-	uint8_t tx_buf[4];
+	 __aligned(32) uint8_t tx_buf[4];
 #endif /* NOCACHE_MEM */
 
-	zassert_equal(uart_rx_enable(uart_dev,
-				     double_buffer[0],
-				     sizeof(double_buffer[0]),
-				     50 * USEC_PER_MSEC),
-		      0,
-		      "Failed to enable receiving");
+	zassert_equal(uart_rx_enable(uart_dev, double_buffer[0], sizeof(double_buffer[0]),
+				     25 * USEC_PER_MSEC),
+		      0, "Failed to enable receiving");
 
 	for (int i = 0; i < 100; i++) {
 		snprintf(tx_buf, sizeof(tx_buf), "%03d", i);
@@ -606,8 +603,8 @@ ZTEST_USER(uart_async_read_abort, test_read_abort)
 	static __aligned(32) uint8_t rx_buf[100] __used __NOCACHE;
 	static __aligned(32) uint8_t tx_buf[100] __used __NOCACHE;
 #else
-	uint8_t rx_buf[100];
-	uint8_t tx_buf[100];
+	 __aligned(32) uint8_t rx_buf[100];
+	 __aligned(32) uint8_t tx_buf[100];
 #endif /* NOCACHE_MEM */
 
 	memset(rx_buf, 0, sizeof(rx_buf));
@@ -711,7 +708,7 @@ ZTEST_USER(uart_async_write_abort, test_write_abort)
 #if NOCACHE_MEM
 	static __aligned(32) uint8_t tx_buf[100] __used __NOCACHE;
 #else
-	uint8_t tx_buf[100];
+	 __aligned(32) uint8_t tx_buf[100];
 #endif /* NOCACHE_MEM */
 
 	memset(test_rx_buf, 0, sizeof(test_rx_buf));
@@ -788,8 +785,8 @@ ZTEST_USER(uart_async_timeout, test_forever_timeout)
 	static __aligned(32) uint8_t rx_buf[100] __used __NOCACHE;
 	static __aligned(32) uint8_t tx_buf[100] __used __NOCACHE;
 #else
-	uint8_t rx_buf[100];
-	uint8_t tx_buf[100];
+	 __aligned(32) uint8_t rx_buf[100];
+	 __aligned(32) uint8_t tx_buf[100];
 #endif /* NOCACHE_MEM */
 
 	memset(rx_buf, 0, sizeof(rx_buf));
@@ -880,7 +877,7 @@ ZTEST_USER(uart_async_chain_write, test_chained_write)
 #if NOCACHE_MEM
 	static __aligned(32) uint8_t rx_buf[20] __used __NOCACHE;
 #else
-	uint8_t rx_buf[20];
+	 __aligned(32) uint8_t rx_buf[20];
 #endif /* NOCACHE_MEM */
 
 	memset(rx_buf, 0, sizeof(rx_buf));
diff --git a/tests/drivers/uart/uart_async_api/testcase.yaml b/tests/drivers/uart/uart_async_api/testcase.yaml
index c6ff52a515f..96747dd1bac 100644
--- a/tests/drivers/uart/uart_async_api/testcase.yaml
+++ b/tests/drivers/uart/uart_async_api/testcase.yaml
@@ -52,6 +52,9 @@ tests:
     filter: CONFIG_SERIAL_SUPPORT_ASYNC and CONFIG_UART_MCUX_LPUART and not CONFIG_CPU_HAS_DCACHE
     harness: ztest
     depends_on: dma
+    extra_configs:
+      - CONFIG_USERSPACE=n
+      - CONFIG_TEST_USERSPACE=n
   drivers.uart.async_api.lpuart.rt_nocache:
     filter: CONFIG_SERIAL_SUPPORT_ASYNC and CONFIG_UART_MCUX_LPUART and CONFIG_CPU_HAS_DCACHE
     harness: ztest
@@ -60,6 +63,7 @@ tests:
       - CONFIG_DCACHE=y
       - CONFIG_NOCACHE_MEMORY=y
       - CONFIG_USERSPACE=n
+      - CONFIG_TEST_USERSPACE=n
   drivers.uart.async_api.sam0:
     filter: CONFIG_SERIAL_SUPPORT_ASYNC and CONFIG_SOC_FAMILY_ATMEL_SAM0
     platform_allow:
diff --git a/tests/drivers/uart/uart_basic_api/prj.conf b/tests/drivers/uart/uart_basic_api/prj.conf
index 4234fa73398..ef35bc38b70 100644
--- a/tests/drivers/uart/uart_basic_api/prj.conf
+++ b/tests/drivers/uart/uart_basic_api/prj.conf
@@ -2,4 +2,4 @@ CONFIG_SERIAL=y
 CONFIG_UART_INTERRUPT_DRIVEN=y
 CONFIG_UART_USE_RUNTIME_CONFIGURE=y
 CONFIG_ZTEST=y
-CONFIG_NATIVE_UART_0_ON_STDINOUT=y
+CONFIG_UART_NATIVE_PTY_0_ON_STDINOUT=y
diff --git a/tests/drivers/uart/uart_basic_api/prj_poll.conf b/tests/drivers/uart/uart_basic_api/prj_poll.conf
index 7b1c9273665..3f5f4803f18 100644
--- a/tests/drivers/uart/uart_basic_api/prj_poll.conf
+++ b/tests/drivers/uart/uart_basic_api/prj_poll.conf
@@ -1,4 +1,4 @@
 CONFIG_SERIAL=y
 CONFIG_UART_USE_RUNTIME_CONFIGURE=y
 CONFIG_ZTEST=y
-CONFIG_NATIVE_UART_0_ON_STDINOUT=y
+CONFIG_UART_NATIVE_PTY_0_ON_STDINOUT=y
diff --git a/tests/drivers/uart/uart_basic_api/prj_shell.conf b/tests/drivers/uart/uart_basic_api/prj_shell.conf
index f4ce1d0334c..7be384d301e 100644
--- a/tests/drivers/uart/uart_basic_api/prj_shell.conf
+++ b/tests/drivers/uart/uart_basic_api/prj_shell.conf
@@ -4,4 +4,4 @@ CONFIG_UART_USE_RUNTIME_CONFIGURE=y
 CONFIG_ZTEST=y
 CONFIG_SHELL_CMD_BUFF_SIZE=90
 CONFIG_SHELL=y
-CONFIG_NATIVE_UART_0_ON_STDINOUT=y
+CONFIG_UART_NATIVE_PTY_0_ON_STDINOUT=y
diff --git a/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..68311be4f06
--- /dev/null
+++ b/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+	hw-flow-control;
+};
diff --git a/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuapp_dual_uart.overlay b/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuapp_dual_uart.overlay
new file mode 100644
index 00000000000..afe50c3b16a
--- /dev/null
+++ b/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuapp_dual_uart.overlay
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 8)>;
+				bias-pull-up;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 8)>;
+			low-power-enable;
+		};
+	};
+
+	uart22_default: uart22_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 9)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+				bias-pull-up;
+		};
+	};
+
+	uart22_sleep: uart22_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 9)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+dut_aux: &uart22 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart22_default>;
+	pinctrl-1 = <&uart22_sleep>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay b/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..68311be4f06
--- /dev/null
+++ b/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+	hw-flow-control;
+};
diff --git a/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuflpr_dual_uart.overlay b/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuflpr_dual_uart.overlay
new file mode 100644
index 00000000000..afe50c3b16a
--- /dev/null
+++ b/tests/drivers/uart/uart_elementary/boards/bl54l15_dvk_nrf54l15_cpuflpr_dual_uart.overlay
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 8)>;
+				bias-pull-up;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 8)>;
+			low-power-enable;
+		};
+	};
+
+	uart22_default: uart22_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 9)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+				bias-pull-up;
+		};
+	};
+
+	uart22_sleep: uart22_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 9)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+dut_aux: &uart22 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart22_default>;
+	pinctrl-1 = <&uart22_sleep>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..68311be4f06
--- /dev/null
+++ b/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+	hw-flow-control;
+};
diff --git a/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuapp_dual_uart.overlay b/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuapp_dual_uart.overlay
new file mode 100644
index 00000000000..afe50c3b16a
--- /dev/null
+++ b/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuapp_dual_uart.overlay
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 8)>;
+				bias-pull-up;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 8)>;
+			low-power-enable;
+		};
+	};
+
+	uart22_default: uart22_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 9)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+				bias-pull-up;
+		};
+	};
+
+	uart22_sleep: uart22_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 9)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+dut_aux: &uart22 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart22_default>;
+	pinctrl-1 = <&uart22_sleep>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay b/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..68311be4f06
--- /dev/null
+++ b/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+	hw-flow-control;
+};
diff --git a/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuflpr_dual_uart.overlay b/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuflpr_dual_uart.overlay
new file mode 100644
index 00000000000..afe50c3b16a
--- /dev/null
+++ b/tests/drivers/uart/uart_elementary/boards/bl54l15u_dvk_nrf54l15_cpuflpr_dual_uart.overlay
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 8)>;
+				bias-pull-up;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 8)>;
+			low-power-enable;
+		};
+	};
+
+	uart22_default: uart22_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 9)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+				bias-pull-up;
+		};
+	};
+
+	uart22_sleep: uart22_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 9)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+dut_aux: &uart22 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart22_default>;
+	pinctrl-1 = <&uart22_sleep>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/tests/drivers/uart/uart_elementary/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay b/tests/drivers/uart/uart_elementary/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay
new file mode 100644
index 00000000000..cf481b7a161
--- /dev/null
+++ b/tests/drivers/uart/uart_elementary/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+	hw-flow-control;
+};
diff --git a/tests/drivers/uart/uart_elementary/boards/nrf54l09pdk_nrf54l09_cpuflpr.overlay b/tests/drivers/uart/uart_elementary/boards/nrf54l09pdk_nrf54l09_cpuflpr.overlay
new file mode 100644
index 00000000000..cf481b7a161
--- /dev/null
+++ b/tests/drivers/uart/uart_elementary/boards/nrf54l09pdk_nrf54l09_cpuflpr.overlay
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+	hw-flow-control;
+};
diff --git a/tests/drivers/uart/uart_elementary/boards/nrf54l09pdk_nrf54l09_dual_uart.overlay b/tests/drivers/uart/uart_elementary/boards/nrf54l09pdk_nrf54l09_dual_uart.overlay
new file mode 100644
index 00000000000..505993a7308
--- /dev/null
+++ b/tests/drivers/uart/uart_elementary/boards/nrf54l09pdk_nrf54l09_dual_uart.overlay
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+/ {
+	chosen {
+		zephyr,console = &uart30;
+		zephyr,shell-uart = &uart30;
+	};
+};
+
+&pinctrl {
+	uart20_default: uart20_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 15)>,
+				<NRF_PSEL(UART_RX, 1, 8)>;
+				bias-pull-up;
+		};
+	};
+
+	uart20_sleep: uart20_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 15)>,
+				<NRF_PSEL(UART_RX, 1, 8)>;
+			low-power-enable;
+		};
+	};
+
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 9)>,
+				<NRF_PSEL(UART_RX, 1, 14)>;
+				bias-pull-up;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 9)>,
+				<NRF_PSEL(UART_RX, 1, 14)>;
+			low-power-enable;
+		};
+	};
+
+	uart30_default: uart30_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 0)>;
+		};
+		group2 {
+			psels = <NRF_PSEL(UART_RX, 0, 1)>;
+			bias-pull-up;
+		};
+	};
+
+	uart30_sleep: uart30_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 0, 0)>,
+				<NRF_PSEL(UART_RX, 0, 1)>;
+			low-power-enable;
+		};
+	};
+};
+
+
+&uart30 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart30_default>;
+	pinctrl-1 = <&uart30_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+dut: &uart20 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart20_default>;
+	pinctrl-1 = <&uart20_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+dut_aux: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/tests/drivers/uart/uart_elementary/boards/nrf54l20pdk_nrf54l20_cpuflpr.overlay b/tests/drivers/uart/uart_elementary/boards/nrf54l20pdk_nrf54l20_cpuflpr.overlay
new file mode 100644
index 00000000000..cf481b7a161
--- /dev/null
+++ b/tests/drivers/uart/uart_elementary/boards/nrf54l20pdk_nrf54l20_cpuflpr.overlay
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+	hw-flow-control;
+};
diff --git a/tests/drivers/uart/uart_elementary/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_elementary/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..cf481b7a161
--- /dev/null
+++ b/tests/drivers/uart/uart_elementary/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+	hw-flow-control;
+};
diff --git a/tests/drivers/uart/uart_elementary/boards/ophelia4ev_nrf54l15_cpuflpr.overlay b/tests/drivers/uart/uart_elementary/boards/ophelia4ev_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..cf481b7a161
--- /dev/null
+++ b/tests/drivers/uart/uart_elementary/boards/ophelia4ev_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+	hw-flow-control;
+};
diff --git a/tests/drivers/uart/uart_elementary/socs/esp32c6.overlay b/tests/drivers/uart/uart_elementary/socs/esp32c3_usb.overlay
similarity index 100%
rename from tests/drivers/uart/uart_elementary/socs/esp32c6.overlay
rename to tests/drivers/uart/uart_elementary/socs/esp32c3_usb.overlay
diff --git a/tests/drivers/uart/uart_elementary/socs/esp32c6_hpcore.overlay b/tests/drivers/uart/uart_elementary/socs/esp32c6_hpcore.overlay
new file mode 100644
index 00000000000..d2df77b7ebc
--- /dev/null
+++ b/tests/drivers/uart/uart_elementary/socs/esp32c6_hpcore.overlay
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart1_test: uart1_test {
+		group1 {
+			pinmux = <UART1_TX_GPIO2>,
+				<UART1_RTS_GPIO3>;
+			input-enable;
+			output-high;
+		};
+		group2 {
+			pinmux = <UART1_RX_GPIO2>,
+				<UART1_CTS_GPIO3>;
+			output-enable;
+			bias-pull-up;
+		};
+	};
+};
+
+dut: &uart1 {
+	status = "okay";
+	pinctrl-0 = <&uart1_test>;
+	pinctrl-names = "default";
+	current-speed = <115200>;
+};
diff --git a/tests/drivers/uart/uart_elementary/testcase.yaml b/tests/drivers/uart/uart_elementary/testcase.yaml
index 49aff4db0aa..fe90ed67812 100644
--- a/tests/drivers/uart/uart_elementary/testcase.yaml
+++ b/tests/drivers/uart/uart_elementary/testcase.yaml
@@ -11,14 +11,19 @@ tests:
     filter: CONFIG_SERIAL_SUPPORT_INTERRUPT
     platform_allow:
       - nrf54h20dk/nrf54h20/cpuapp
+      - nrf54l09pdk/nrf54l09/cpuapp
+      - nrf54l09pdk/nrf54l09/cpuflpr
       - nrf54l15dk/nrf54l15/cpuapp
-      - nrf54l20pdk/nrf54l20/cpuapp
       - nrf54l15dk/nrf54l15/cpuflpr
+      - nrf54l20pdk/nrf54l20/cpuapp
+      - nrf54l20pdk/nrf54l20/cpuflpr
       - nrf5340dk/nrf5340/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuflpr
       - esp32_devkitc_wrover/esp32/procpu
       - esp8684_devkitm
       - esp32c3_devkitm
-      - esp32c6_devkitc
+      - esp32c6_devkitc/esp32c6/hpcore
       - esp32s2_saola
       - esp32s3_devkitm/esp32s3/procpu
     integration_platforms:
@@ -52,6 +57,7 @@ tests:
     platform_allow:
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     extra_args: DTC_OVERLAY_FILE="boards/nrf54l15dk_nrf54l15_cpuapp_dual_uart.overlay"
     extra_configs:
       - CONFIG_DUAL_UART_TEST=y
@@ -60,6 +66,7 @@ tests:
     platform_allow:
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     extra_args: DTC_OVERLAY_FILE="boards/nrf54l15dk_nrf54l15_cpuapp_dual_uart.overlay"
     extra_configs:
       - CONFIG_DUAL_UART_TEST=y
@@ -68,6 +75,8 @@ tests:
     filter: CONFIG_SERIAL_SUPPORT_INTERRUPT
     platform_allow:
       - nrf54l15dk/nrf54l15/cpuflpr
+      - nrf54l20pdk/nrf54l20/cpuflpr
+      - ophelia4ev/nrf54l15/cpuflpr
     extra_args: DTC_OVERLAY_FILE="boards/nrf54l15dk_nrf54l15_cpuflpr_dual_uart.overlay"
     extra_configs:
       - CONFIG_DUAL_UART_TEST=y
@@ -75,7 +84,26 @@ tests:
     filter: CONFIG_SERIAL_SUPPORT_INTERRUPT
     platform_allow:
       - nrf54l15dk/nrf54l15/cpuflpr
+      - nrf54l20pdk/nrf54l20/cpuflpr
+      - ophelia4ev/nrf54l15/cpuflpr
     extra_args: DTC_OVERLAY_FILE="boards/nrf54l15dk_nrf54l15_cpuflpr_dual_uart.overlay"
     extra_configs:
       - CONFIG_DUAL_UART_TEST=y
       - CONFIG_SETUP_MISMATCH_TEST=y
+  drivers.uart.uart_elementary_dual_nrf54l09:
+    filter: CONFIG_SERIAL_SUPPORT_INTERRUPT
+    platform_allow:
+      - nrf54l09pdk/nrf54l09/cpuapp
+      - nrf54l09pdk/nrf54l09/cpuflpr
+    extra_args: DTC_OVERLAY_FILE="boards/nrf54l09pdk_nrf54l09_dual_uart.overlay"
+    extra_configs:
+      - CONFIG_DUAL_UART_TEST=y
+  drivers.uart.uart_elementary_dual_setup_mismatch_nrf54l09:
+    filter: CONFIG_SERIAL_SUPPORT_INTERRUPT
+    platform_allow:
+      - nrf54l09pdk/nrf54l09/cpuapp
+      - nrf54l09pdk/nrf54l09/cpuflpr
+    extra_args: DTC_OVERLAY_FILE="boards/nrf54l09pdk_nrf54l09_dual_uart.overlay"
+    extra_configs:
+      - CONFIG_DUAL_UART_TEST=y
+      - CONFIG_SETUP_MISMATCH_TEST=y
diff --git a/tests/drivers/uart/uart_errors/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_errors/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..e2364f091be
--- /dev/null
+++ b/tests/drivers/uart/uart_errors/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_RX, 1, 8)>,
+				<NRF_PSEL(UART_RTS, 1, 10)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_RX, 1, 8)>,
+				<NRF_PSEL(UART_RTS, 1, 10)>;
+			low-power-enable;
+		};
+	};
+
+	uart22_default: uart22_default {
+		group1 {
+			psels =
+				<NRF_PSEL(UART_CTS, 1, 11)>;
+				bias-pull-up;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_TX, 1, 9)>;
+		};
+	};
+
+	uart22_sleep: uart22_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 9)>,
+				<NRF_PSEL(UART_CTS, 1, 11)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+dut_aux: &uart22 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart22_default>;
+	pinctrl-1 = <&uart22_sleep>;
+	pinctrl-names = "default", "sleep";
+	disable-rx;
+};
diff --git a/tests/drivers/uart/uart_errors/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_errors/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..e2364f091be
--- /dev/null
+++ b/tests/drivers/uart/uart_errors/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_RX, 1, 8)>,
+				<NRF_PSEL(UART_RTS, 1, 10)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_RX, 1, 8)>,
+				<NRF_PSEL(UART_RTS, 1, 10)>;
+			low-power-enable;
+		};
+	};
+
+	uart22_default: uart22_default {
+		group1 {
+			psels =
+				<NRF_PSEL(UART_CTS, 1, 11)>;
+				bias-pull-up;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_TX, 1, 9)>;
+		};
+	};
+
+	uart22_sleep: uart22_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 9)>,
+				<NRF_PSEL(UART_CTS, 1, 11)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+dut_aux: &uart22 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart22_default>;
+	pinctrl-1 = <&uart22_sleep>;
+	pinctrl-names = "default", "sleep";
+	disable-rx;
+};
diff --git a/tests/drivers/uart/uart_errors/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_errors/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..a1748b3784b
--- /dev/null
+++ b/tests/drivers/uart/uart_errors/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_RX, 1, 8)>,
+				<NRF_PSEL(UART_RTS, 1, 10)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_RX, 1, 8)>,
+				<NRF_PSEL(UART_RTS, 1, 10)>;
+			low-power-enable;
+		};
+	};
+
+	uart22_default: uart22_default {
+		group1 {
+			psels =
+				<NRF_PSEL(UART_CTS, 1, 11)>;
+				bias-pull-up;
+		};
+
+		group2 {
+			psels = <NRF_PSEL(UART_TX, 1, 9)>;
+		};
+	};
+
+	uart22_sleep: uart22_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 9)>,
+				<NRF_PSEL(UART_CTS, 1, 11)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+};
+
+dut_aux: &uart22 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart22_default>;
+	pinctrl-1 = <&uart22_sleep>;
+	pinctrl-names = "default", "sleep";
+	disable-rx;
+};
diff --git a/tests/drivers/uart/uart_errors/testcase.yaml b/tests/drivers/uart/uart_errors/testcase.yaml
index 9df414075b0..d303c73b600 100644
--- a/tests/drivers/uart/uart_errors/testcase.yaml
+++ b/tests/drivers/uart/uart_errors/testcase.yaml
@@ -14,6 +14,7 @@ tests:
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
       - nrf5340dk/nrf5340/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
   drivers.uart.uart_errors.async:
     filter: CONFIG_SERIAL_SUPPORT_ASYNC
     platform_allow:
@@ -21,6 +22,7 @@ tests:
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
       - nrf5340dk/nrf5340/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     extra_configs:
       - CONFIG_UART_ASYNC_API=y
       - CONFIG_UART_INTERRUPT_DRIVEN=n
diff --git a/tests/drivers/uart/uart_mix_fifo_poll/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_mix_fifo_poll/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..fb056ec4dd4
--- /dev/null
+++ b/tests/drivers/uart/uart_mix_fifo_poll/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+	hw-flow-control;
+};
+
+counter_dev: &timer00 {
+	status = "okay";
+};
+
+&grtc {
+	interrupts = <228 2>;
+};
diff --git a/tests/drivers/uart/uart_mix_fifo_poll/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_mix_fifo_poll/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..fb056ec4dd4
--- /dev/null
+++ b/tests/drivers/uart/uart_mix_fifo_poll/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+	hw-flow-control;
+};
+
+counter_dev: &timer00 {
+	status = "okay";
+};
+
+&grtc {
+	interrupts = <228 2>;
+};
diff --git a/tests/drivers/uart/uart_mix_fifo_poll/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay b/tests/drivers/uart/uart_mix_fifo_poll/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay
new file mode 100644
index 00000000000..945b8628e7a
--- /dev/null
+++ b/tests/drivers/uart/uart_mix_fifo_poll/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+	hw-flow-control;
+};
+
+counter_dev: &timer00 {
+	status = "okay";
+};
+
+&grtc {
+	interrupts = <228 2>;
+};
diff --git a/tests/drivers/uart/uart_mix_fifo_poll/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_mix_fifo_poll/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..35378db2585
--- /dev/null
+++ b/tests/drivers/uart/uart_mix_fifo_poll/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>,
+				<NRF_PSEL(UART_RTS, 1, 8)>,
+				<NRF_PSEL(UART_CTS, 1, 9)>;
+			low-power-enable;
+		};
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+	hw-flow-control;
+};
+
+counter_dev: &timer00 {
+	status = "okay";
+};
+
+&grtc {
+	interrupts = <228 2>;
+};
diff --git a/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml b/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml
index 7a53a4989fc..0ff023748d2 100644
--- a/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml
+++ b/tests/drivers/uart/uart_mix_fifo_poll/testcase.yaml
@@ -9,11 +9,13 @@ common:
     - nrf9160dk/nrf9160
     - nrf5340dk/nrf5340/cpuapp
     - nrf5340bsim/nrf5340/cpuapp
+    - nrf54l09pdk/nrf54l09/cpuapp
     - nrf54l15dk/nrf54l15/cpuapp
     - nrf54l20pdk/nrf54l20/cpuapp
     - nrf54l15bsim/nrf54l15/cpuapp
     - nrf54h20dk/nrf54h20/cpuapp
     - nrf54h20dk/nrf54h20/cpurad
+    - ophelia4ev/nrf54l15/cpuapp
     - nrf52_bsim
   integration_platforms:
     - nrf52840dk/nrf52840
diff --git a/tests/drivers/uart/uart_pm/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_pm/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..1e20d1d453a
--- /dev/null
+++ b/tests/drivers/uart/uart_pm/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+			low-power-enable;
+		};
+	};
+};
+
+/ {
+	chosen {
+		zephyr,console = &uart20;
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/tests/drivers/uart/uart_pm/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_pm/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..1e20d1d453a
--- /dev/null
+++ b/tests/drivers/uart/uart_pm/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+			low-power-enable;
+		};
+	};
+};
+
+/ {
+	chosen {
+		zephyr,console = &uart20;
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/tests/drivers/uart/uart_pm/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay b/tests/drivers/uart/uart_pm/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay
new file mode 100644
index 00000000000..033aab401ac
--- /dev/null
+++ b/tests/drivers/uart/uart_pm/boards/nrf54l09pdk_nrf54l09_cpuapp.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+			low-power-enable;
+		};
+	};
+};
+
+/ {
+	chosen {
+		zephyr,console = &uart20;
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/tests/drivers/uart/uart_pm/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/uart/uart_pm/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..fec91b746a2
--- /dev/null
+++ b/tests/drivers/uart/uart_pm/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	uart21_default: uart21_default {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+		};
+	};
+
+	uart21_sleep: uart21_sleep {
+		group1 {
+			psels = <NRF_PSEL(UART_TX, 1, 10)>,
+				<NRF_PSEL(UART_RX, 1, 11)>;
+			low-power-enable;
+		};
+	};
+};
+
+/ {
+	chosen {
+		zephyr,console = &uart20;
+	};
+};
+
+dut: &uart21 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&uart21_default>;
+	pinctrl-1 = <&uart21_sleep>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/tests/drivers/uart/uart_pm/testcase.yaml b/tests/drivers/uart/uart_pm/testcase.yaml
index 46bf61d11be..329b5546b8b 100644
--- a/tests/drivers/uart/uart_pm/testcase.yaml
+++ b/tests/drivers/uart/uart_pm/testcase.yaml
@@ -5,12 +5,14 @@ common:
   harness: ztest
   platform_allow:
     - nrf52840dk/nrf52840
+    - nrf54l09pdk/nrf54l09/cpuapp
     - nrf54l15dk/nrf54l15/cpuapp
     - nrf54l20pdk/nrf54l20/cpuapp
     - nrf54l15bsim/nrf54l15/cpuapp
     - nrf54h20dk/nrf54h20/cpuapp
     - nrf52_bsim
     - nrf5340bsim/nrf5340/cpuapp
+    - ophelia4ev/nrf54l15/cpuapp
   harness_config:
     fixture: gpio_loopback
   depends_on: gpio
@@ -30,12 +32,14 @@ tests:
       - CONFIG_UART_0_ENHANCED_POLL_OUT=n
     extra_args: DTC_OVERLAY_FILE="boards/nrf52840dk_nrf52840.overlay;nrf_rx_disable.overlay"
     platform_exclude:
+      - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
       - nrf54l15bsim/nrf54l15/cpuapp
       - nrf54h20dk/nrf54h20/cpuapp
       - nrf52_bsim
       - nrf5340bsim/nrf5340/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
 
   drivers.uart.pm.enhanced_poll:
     extra_configs:
@@ -43,9 +47,11 @@ tests:
       - CONFIG_UART_ASYNC_API=n
       - CONFIG_UART_0_ENHANCED_POLL_OUT=y
     platform_exclude:
+      - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
       - nrf54h20dk/nrf54h20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
 
   drivers.uart.pm.int_driven:
     extra_configs:
@@ -61,9 +67,11 @@ tests:
       - CONFIG_UART_ASYNC_API=n
       - CONFIG_UART_0_ENHANCED_POLL_OUT=y
     platform_exclude:
+      - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
       - nrf54h20dk/nrf54h20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
 
   drivers.uart.pm.async:
     extra_configs:
@@ -79,6 +87,8 @@ tests:
       - CONFIG_UART_0_ASYNC=y
       - CONFIG_UART_0_ENHANCED_POLL_OUT=y
     platform_exclude:
+      - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
       - nrf54h20dk/nrf54h20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
diff --git a/tests/drivers/udc/src/main.c b/tests/drivers/udc/src/main.c
index 66bf469cd79..e08a8f615a1 100644
--- a/tests/drivers/udc/src/main.c
+++ b/tests/drivers/udc/src/main.c
@@ -18,6 +18,8 @@ LOG_MODULE_REGISTER(udc_test, LOG_LEVEL_INF);
  * connected to the host as this state is not covered by this test.
  */
 
+#define BULK_OUT_EP_ADDR	0x01U
+#define BULK_IN_EP_ADDR		0x81U
 #define FALSE_EP_ADDR		0x0FU
 
 K_MSGQ_DEFINE(test_msgq, sizeof(struct udc_event), 8, sizeof(uint32_t));
@@ -127,7 +129,7 @@ static void test_udc_ep_enable(const struct device *dev,
 	uint8_t ctrl_ep = USB_EP_DIR_IS_IN(ed->bEndpointAddress) ?
 			  USB_CONTROL_EP_IN : USB_CONTROL_EP_OUT;
 	/* Possible return values 0, -EINVAL, -ENODEV, -EALREADY, -EPERM. */
-	int err1, err2, err3, err4;
+	int err1, err2, err3;
 
 	err1 = udc_ep_enable(dev, ed->bEndpointAddress, ed->bmAttributes,
 			     sys_le16_to_cpu(ed->wMaxPacketSize),
@@ -135,28 +137,22 @@ static void test_udc_ep_enable(const struct device *dev,
 	err2 = udc_ep_enable(dev, ed->bEndpointAddress, ed->bmAttributes,
 			     sys_le16_to_cpu(ed->wMaxPacketSize),
 			     ed->bInterval);
-	err3 = udc_ep_enable(dev, FALSE_EP_ADDR, ed->bmAttributes,
-			     sys_le16_to_cpu(ed->wMaxPacketSize),
-			     ed->bInterval);
-	err4 = udc_ep_enable(dev, ctrl_ep, ed->bmAttributes,
+	err3 = udc_ep_enable(dev, ctrl_ep, ed->bmAttributes,
 			     sys_le16_to_cpu(ed->wMaxPacketSize),
 			     ed->bInterval);
 
 	if (!udc_is_initialized(dev) && !udc_is_enabled(dev)) {
 		zassert_equal(err1, -EPERM, "Not failed to enable endpoint");
 		zassert_equal(err2, -EPERM, "Not failed to enable endpoint");
-		zassert_equal(err3, -EPERM, "Not failed to enable endpoint");
-		zassert_equal(err4, -EINVAL, "Not failed to enable endpoint");
+		zassert_equal(err3, -EINVAL, "Not failed to enable endpoint");
 	} else if (udc_is_initialized(dev) && !udc_is_enabled(dev)) {
 		zassert_equal(err1, -EPERM, "Not failed to enable endpoint");
 		zassert_equal(err2, -EPERM, "Not failed to enable endpoint");
-		zassert_equal(err3, -EPERM, "Not failed to enable endpoint");
-		zassert_equal(err4, -EINVAL, "Not failed to enable endpoint");
+		zassert_equal(err3, -EINVAL, "Not failed to enable endpoint");
 	} else {
 		zassert_equal(err1, 0, "Failed to enable endpoint");
 		zassert_equal(err2, -EALREADY, "Not failed to enable endpoint");
-		zassert_equal(err3, -ENODEV, "Not failed to enable endpoint");
-		zassert_equal(err4, -EINVAL, "Not failed to enable endpoint");
+		zassert_equal(err3, -EINVAL, "Not failed to enable endpoint");
 	}
 }
 
@@ -166,28 +162,24 @@ static void test_udc_ep_disable(const struct device *dev,
 	uint8_t ctrl_ep = USB_EP_DIR_IS_IN(ed->bEndpointAddress) ?
 			  USB_CONTROL_EP_IN : USB_CONTROL_EP_OUT;
 	/* Possible return values 0, -EINVAL, -ENODEV, -EALREADY, -EPERM. */
-	int err1, err2, err3, err4;
+	int err1, err2, err3;
 
 	err1 = udc_ep_disable(dev, ed->bEndpointAddress);
 	err2 = udc_ep_disable(dev, ed->bEndpointAddress);
-	err3 = udc_ep_disable(dev, FALSE_EP_ADDR);
-	err4 = udc_ep_disable(dev, ctrl_ep);
+	err3 = udc_ep_disable(dev, ctrl_ep);
 
 	if (!udc_is_initialized(dev) && !udc_is_enabled(dev)) {
 		zassert_equal(err1, -EPERM, "Not failed to disable endpoint");
 		zassert_equal(err2, -EPERM, "Not failed to disable endpoint");
-		zassert_equal(err3, -EPERM, "Not failed to disable endpoint");
-		zassert_equal(err4, -EINVAL, "Not failed to disable endpoint");
+		zassert_equal(err3, -EINVAL, "Not failed to disable endpoint");
 	} else if (udc_is_initialized(dev) && !udc_is_enabled(dev)) {
 		zassert_equal(err1, -EALREADY, "Failed to disable endpoint");
 		zassert_equal(err2, -EALREADY, "Not failed to disable endpoint");
-		zassert_equal(err3, -ENODEV, "Not failed to disable endpoint");
-		zassert_equal(err4, -EINVAL, "Not failed to disable endpoint");
+		zassert_equal(err3, -EINVAL, "Not failed to disable endpoint");
 	} else {
 		zassert_equal(err1, 0, "Failed to disable endpoint");
 		zassert_equal(err2, -EALREADY, "Not failed to disable endpoint");
-		zassert_equal(err3, -ENODEV, "Not failed to disable endpoint");
-		zassert_equal(err4, -EINVAL, "Not failed to disable endpoint");
+		zassert_equal(err3, -EINVAL, "Not failed to disable endpoint");
 	}
 }
 
@@ -284,17 +276,14 @@ static void test_udc_ep_dequeue(const struct device *dev,
 				struct usb_ep_descriptor *ed)
 {
 	/* Possible return values 0, -EPERM, -ENODEV, -EACCES(TBD) */
-	int err1, err2;
+	int err;
 
-	err1 = udc_ep_dequeue(dev, ed->bEndpointAddress);
-	err2 = udc_ep_dequeue(dev, FALSE_EP_ADDR);
+	err = udc_ep_dequeue(dev, ed->bEndpointAddress);
 
 	if (!udc_is_initialized(dev)) {
-		zassert_equal(err1, -EPERM, "Not failed to dequeue");
-		zassert_equal(err2, -EPERM, "Not failed to dequeue");
+		zassert_equal(err, -EPERM, "Not failed to dequeue");
 	} else {
-		zassert_equal(err1, 0, "Failed to dequeue");
-		zassert_equal(err2, -ENODEV, "Not failed to dequeue");
+		zassert_equal(err, 0, "Failed to dequeue");
 	}
 }
 
@@ -462,7 +451,7 @@ static struct usb_ep_descriptor ed_ctrl_in = {
 static struct usb_ep_descriptor ed_bulk_out = {
 	.bLength = sizeof(struct usb_ep_descriptor),
 	.bDescriptorType = USB_DESC_ENDPOINT,
-	.bEndpointAddress = 0x01,
+	.bEndpointAddress = BULK_OUT_EP_ADDR,
 	.bmAttributes = USB_EP_TYPE_BULK,
 	.wMaxPacketSize = sys_cpu_to_le16(64),
 	.bInterval = 0,
@@ -471,7 +460,7 @@ static struct usb_ep_descriptor ed_bulk_out = {
 static struct usb_ep_descriptor ed_bulk_in = {
 	.bLength = sizeof(struct usb_ep_descriptor),
 	.bDescriptorType = USB_DESC_ENDPOINT,
-	.bEndpointAddress = 0x81,
+	.bEndpointAddress = BULK_IN_EP_ADDR,
 	.bmAttributes = USB_EP_TYPE_BULK,
 	.wMaxPacketSize = sys_cpu_to_le16(64),
 	.bInterval = 0,
diff --git a/tests/drivers/udc/testcase.yaml b/tests/drivers/udc/testcase.yaml
index 9427a1a97c9..2ba45d77488 100644
--- a/tests/drivers/udc/testcase.yaml
+++ b/tests/drivers/udc/testcase.yaml
@@ -7,6 +7,10 @@ tests:
     depends_on: usbd
     integration_platforms:
       - nrf52840dk/nrf52840
+      - frdm_k64f
+      - nucleo_f413zh
+      - mimxrt1050_evk/mimxrt1052/hyperflash
+      - rpi_pico
     platform_exclude:
       - nrf54h20dk/nrf54h20/cpuapp
   drivers.usb.udc.build_only:
diff --git a/tests/drivers/video/api/prj.conf b/tests/drivers/video/api/prj.conf
index 5e2cc7c828b..8a6c2151c27 100644
--- a/tests/drivers/video/api/prj.conf
+++ b/tests/drivers/video/api/prj.conf
@@ -1,5 +1,11 @@
 CONFIG_ZTEST=y
 CONFIG_VIDEO=y
-CONFIG_VIDEO_BUFFER_POOL_SZ_MAX=16384
+
+# Just enough for a single frame in RGB565 format: 320 * 420 * 2 + some margin
+CONFIG_VIDEO_BUFFER_POOL_SZ_MAX=300000
 CONFIG_VIDEO_BUFFER_POOL_NUM_MAX=1
+
+# Required to support larger buffers on native_sim
+CONFIG_SYS_HEAP_BIG_ONLY=y
+
 CONFIG_VIDEO_LOG_LEVEL_DBG=y
diff --git a/tests/drivers/video/api/src/video_emul.c b/tests/drivers/video/api/src/video_emul.c
index 5ce07350f85..cd58bbf0506 100644
--- a/tests/drivers/video/api/src/video_emul.c
+++ b/tests/drivers/video/api/src/video_emul.c
@@ -127,17 +127,13 @@ ZTEST(video_common, test_video_frmival)
 
 ZTEST(video_common, test_video_ctrl)
 {
-	int value;
+	struct video_control ctrl = {.id = VIDEO_CID_PRIVATE_BASE + 0x01, .val = 30};
 
-	/* Exposure control, expected to be supported by all imagers */
-	zexpect_ok(video_set_ctrl(imager_dev, VIDEO_CID_EXPOSURE, (void *)30));
-	zexpect_ok(video_get_ctrl(imager_dev, VIDEO_CID_EXPOSURE, &value));
-	zexpect_equal(value, 30);
-
-	/* Gain control, expected to be supported by all imagers */
-	zexpect_ok(video_set_ctrl(imager_dev, VIDEO_CID_GAIN, (void *)30));
-	zexpect_ok(video_get_ctrl(imager_dev, VIDEO_CID_GAIN, &value));
-	zexpect_equal(value, 30);
+	/* Emulated vendor specific control, expected to be supported by all imagers */
+	zexpect_ok(video_set_ctrl(imager_dev, &ctrl));
+	ctrl.val = 0;
+	zexpect_ok(video_get_ctrl(imager_dev, &ctrl));
+	zexpect_equal(ctrl.val, 30);
 }
 
 ZTEST(video_common, test_video_vbuf)
@@ -157,7 +153,7 @@ ZTEST(video_common, test_video_vbuf)
 	zexpect_ok(video_set_format(rx_dev, VIDEO_EP_OUT, &fmt));
 
 	/* Allocate a buffer, assuming prj.conf gives enough memory for it */
-	vbuf = video_buffer_alloc(fmt.pitch * fmt.height, K_FOREVER);
+	vbuf = video_buffer_alloc(fmt.pitch * fmt.height, K_NO_WAIT);
 	zexpect_not_null(vbuf);
 
 	/* Start the virtual hardware */
@@ -184,6 +180,9 @@ ZTEST(video_common, test_video_vbuf)
 
 	/* Nothing left in the queue, possible to stop */
 	zexpect_ok(video_stream_stop(rx_dev));
+
+	/* Nothing tested, but this should not crash */
+	video_buffer_release(vbuf);
 }
 
 ZTEST_SUITE(video_emul, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/drivers/video/api/testcase.yaml b/tests/drivers/video/api/testcase.yaml
index c6005d99760..888e0f722f8 100644
--- a/tests/drivers/video/api/testcase.yaml
+++ b/tests/drivers/video/api/testcase.yaml
@@ -1,8 +1,9 @@
-# Copyright (c) 2024 tinyVision.ai Inc.
+# Copyright (c) 2024-2025 tinyVision.ai Inc.
 # SPDX-License-Identifier: Apache-2.0
 
 tests:
   drivers.video.api:
+    min_ram: 32
     tags:
       - drivers
       - video
diff --git a/tests/drivers/w1/w1_api/boards/max78000evkit_max78000_m4.overlay b/tests/drivers/w1/w1_api/boards/max78000evkit_max78000_m4.overlay
new file mode 100644
index 00000000000..65c177d514f
--- /dev/null
+++ b/tests/drivers/w1/w1_api/boards/max78000evkit_max78000_m4.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+w1_0: &w1 {
+	status = "okay";
+	internal-pullup = <1>;
+};
+
+#include "../w1_devices.dtsi"
diff --git a/tests/drivers/w1/w1_api/boards/max78000fthr_max78000_m4.overlay b/tests/drivers/w1/w1_api/boards/max78000fthr_max78000_m4.overlay
new file mode 100644
index 00000000000..65c177d514f
--- /dev/null
+++ b/tests/drivers/w1/w1_api/boards/max78000fthr_max78000_m4.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+w1_0: &w1 {
+	status = "okay";
+	internal-pullup = <1>;
+};
+
+#include "../w1_devices.dtsi"
diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay b/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay
new file mode 100644
index 00000000000..567c80da4c6
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15_dvk_nrf54l10_cpuapp.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..567c80da4c6
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay b/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..bb7b5a55248
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15_dvk_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15_dvk_nrf54l15_cpuflpr_xip.overlay b/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15_dvk_nrf54l15_cpuflpr_xip.overlay
new file mode 100644
index 00000000000..bb7b5a55248
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15_dvk_nrf54l15_cpuflpr_xip.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..567c80da4c6
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay b/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..bb7b5a55248
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuflpr_xip.overlay b/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuflpr_xip.overlay
new file mode 100644
index 00000000000..bb7b5a55248
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_basic_api/boards/bl54l15u_dvk_nrf54l15_cpuflpr_xip.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/nrf54l09pdk_nrf54l09_cpuflpr.overlay b/tests/drivers/watchdog/wdt_basic_api/boards/nrf54l09pdk_nrf54l09_cpuflpr.overlay
new file mode 100644
index 00000000000..dc1ea1a9ddc
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_basic_api/boards/nrf54l09pdk_nrf54l09_cpuflpr.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/nrf54l20pdk_nrf54l20_cpuflpr.overlay b/tests/drivers/watchdog/wdt_basic_api/boards/nrf54l20pdk_nrf54l20_cpuflpr.overlay
new file mode 100644
index 00000000000..dc1ea1a9ddc
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_basic_api/boards/nrf54l20pdk_nrf54l20_cpuflpr.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/watchdog/wdt_basic_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..cb831fea279
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_basic_api/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/ophelia4ev_nrf54l15_cpuflpr.overlay b/tests/drivers/watchdog/wdt_basic_api/boards/ophelia4ev_nrf54l15_cpuflpr.overlay
new file mode 100644
index 00000000000..025e0b8aedb
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_basic_api/boards/ophelia4ev_nrf54l15_cpuflpr.overlay
@@ -0,0 +1,8 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_basic_api/boards/siwx917_rb4338a.overlay b/tests/drivers/watchdog/wdt_basic_api/boards/siwx917_rb4338a.overlay
new file mode 100644
index 00000000000..25e5763dc59
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_basic_api/boards/siwx917_rb4338a.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2025 Silicon Laboratories Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&watchdog {
+	status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c b/tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c
index a78e9600a42..38cfeb58902 100644
--- a/tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c
+++ b/tests/drivers/watchdog/wdt_basic_api/src/test_wdt.c
@@ -98,6 +98,8 @@
 #define WDT_NODE DT_INST(0, gd_gd32_fwdgt)
 #elif DT_HAS_COMPAT_STATUS_OKAY(zephyr_counter_watchdog)
 #define WDT_NODE DT_COMPAT_GET_ANY_STATUS_OKAY(zephyr_counter_watchdog)
+#elif DT_HAS_COMPAT_STATUS_OKAY(silabs_siwx91x_wdt)
+#define WDT_NODE DT_INST(0, silabs_siwx91x_wdt)
 #elif DT_HAS_COMPAT_STATUS_OKAY(nuvoton_numaker_wwdt)
 #define WDT_NODE DT_INST(0, nuvoton_numaker_wwdt)
 #define TIMEOUTS 1
@@ -257,6 +259,12 @@ static int test_wdt_callback_1(void)
 		}
 	}
 
+	err = wdt_disable(wdt);
+	if (err < 0 && err != -EPERM && err != -EFAULT) {
+		TC_PRINT("Watchdog disable error\n");
+		return TC_FAIL;
+	}
+
 	m_testvalue = 0U;
 	m_cfg_wdt0.flags = WDT_FLAG_RESET_SOC;
 	m_cfg_wdt0.callback = wdt_int_cb0;
@@ -316,6 +324,11 @@ static int test_wdt_callback_2(void)
 		}
 	}
 
+	err = wdt_disable(wdt);
+	if (err < 0 && err != -EPERM && err != -EFAULT) {
+		TC_PRINT("Watchdog disable error\n");
+		return TC_FAIL;
+	}
 
 	m_testvalue = 0U;
 	m_cfg_wdt0.callback = wdt_int_cb0;
@@ -370,6 +383,12 @@ static int test_wdt_bad_window_max(void)
 
 	TC_PRINT("Testcase: %s\n", __func__);
 
+	err = wdt_disable(wdt);
+	if (err < 0 && err != -EPERM && err != -EFAULT) {
+		TC_PRINT("Watchdog disable error\n");
+		return TC_FAIL;
+	}
+
 	m_cfg_wdt0.callback = NULL;
 	m_cfg_wdt0.flags = WDT_FLAG_RESET_SOC;
 	m_cfg_wdt0.window.max = 0U;
diff --git a/tests/drivers/watchdog/wdt_basic_api/testcase.yaml b/tests/drivers/watchdog/wdt_basic_api/testcase.yaml
index da3497f41be..f5e06450a5a 100644
--- a/tests/drivers/watchdog/wdt_basic_api/testcase.yaml
+++ b/tests/drivers/watchdog/wdt_basic_api/testcase.yaml
@@ -1,12 +1,14 @@
 common:
   depends_on: watchdog
+  expect_reboot: true
   tags:
     - drivers
     - watchdog
 tests:
   drivers.watchdog:
     filter: >
-      not (CONFIG_WDT_SAM or dt_compat_enabled("st,stm32-window-watchdog")
+      not (CONFIG_WDT_SAM or CONFIG_WDT_SAM4L
+       or dt_compat_enabled("st,stm32-window-watchdog")
        or dt_compat_enabled("st,stm32-watchdog") or CONFIG_SOC_FAMILY_LPC or
        CONFIG_SOC_SERIES_IMXRT6XX or CONFIG_SOC_SERIES_IMXRT5XX or
        CONFIG_SOC_FAMILY_GD_GD32 or SOC_SERIES_GD32VF103)
@@ -16,6 +18,18 @@ tests:
       - s32z2xxdc2/s32z270/rtu1
       - s32z2xxdc2@D/s32z270/rtu0
       - s32z2xxdc2@D/s32z270/rtu1
+      - mps2/an383
+      - mps2/an386
+      - mps2/an500
+      - panb511evb/nrf54l15/cpuapp
+      - panb511evb/nrf54l15/cpuflpr
+      - panb511evb/nrf54l15/cpuflpr/xip
+      - mimxrt700_evk/mimxrt798s/cm33_cpu1
+      - nrf54l15dk/nrf54l15/cpuapp/ns
+      - nrf54l15dk/nrf54l10/cpuapp/ns
+      - bl54l15_dvk/nrf54l10/cpuapp/ns
+      - bl54l15_dvk/nrf54l15/cpuapp/ns
+      - bl54l15u_dvk/nrf54l15/cpuapp/ns
   drivers.watchdog.stm32wwdg:
     filter: dt_compat_enabled("st,stm32-window-watchdog") or dt_compat_enabled("st,stm32-watchdog")
     extra_args: DTC_OVERLAY_FILE="boards/stm32_wwdg.overlay"
@@ -38,7 +52,7 @@ tests:
       - nucleo_u575zi_q
       - nucleo_c031c6
       - stm32h573i_dk
-      - nucleo_wba52cg
+      - nucleo_wba55cg
     integration_platforms:
       - nucleo_f091rc
   drivers.watchdog.stm32wwdg_h7:
@@ -75,7 +89,7 @@ tests:
       - nucleo_h753zi
       - nucleo_h7s3l8
       - stm32h7s78_dk
-      - nucleo_wba52cg
+      - nucleo_wba55cg
     integration_platforms:
       - nucleo_f091rc
   drivers.watchdog.mec15xxevb_assy6853:
diff --git a/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml b/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml
index 3609d921169..75a140b9685 100644
--- a/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml
+++ b/tests/drivers/watchdog/wdt_basic_reset_none/testcase.yaml
@@ -3,12 +3,7 @@
 
 tests:
   drivers.watchdog.reset_none:
-    platform_allow:
-      - s32z2xxdc2/s32z270/rtu0
-      - s32z2xxdc2/s32z270/rtu1
-      - s32z2xxdc2@D/s32z270/rtu0
-      - s32z2xxdc2@D/s32z270/rtu1
-      - mr_canhubk3
+    filter: dt_compat_enabled("nxp,s32-swt") or dt_compat_enabled("renesas,ra-wdt")
     integration_platforms:
       - s32z2xxdc2/s32z270/rtu0
     tags:
diff --git a/tests/drivers/watchdog/wdt_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/watchdog/wdt_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..567c80da4c6
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_error_cases/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/watchdog/wdt_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..567c80da4c6
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_error_cases/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/watchdog/wdt_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..cb831fea279
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_error_cases/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_error_cases/testcase.yaml b/tests/drivers/watchdog/wdt_error_cases/testcase.yaml
index 741b379caca..78bafd36729 100644
--- a/tests/drivers/watchdog/wdt_error_cases/testcase.yaml
+++ b/tests/drivers/watchdog/wdt_error_cases/testcase.yaml
@@ -16,5 +16,7 @@ tests:
       - nrf54h20dk/nrf54h20/cpurad
       - nrf9280pdk/nrf9280/cpuapp
       - nrf9280pdk/nrf9280/cpurad
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
diff --git a/tests/drivers/watchdog/wdt_variables/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/watchdog/wdt_variables/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..0c1eaa65c22
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_variables/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_variables/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/drivers/watchdog/wdt_variables/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..0c1eaa65c22
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_variables/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_variables/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/drivers/watchdog/wdt_variables/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..cb831fea279
--- /dev/null
+++ b/tests/drivers/watchdog/wdt_variables/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&wdt31 {
+	status = "okay";
+};
diff --git a/tests/drivers/watchdog/wdt_variables/testcase.yaml b/tests/drivers/watchdog/wdt_variables/testcase.yaml
index 3f230886acd..3ed2ad90b11 100644
--- a/tests/drivers/watchdog/wdt_variables/testcase.yaml
+++ b/tests/drivers/watchdog/wdt_variables/testcase.yaml
@@ -17,8 +17,10 @@ tests:
       - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     integration_platforms:
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
 
   drivers.watchdog.wdt_variables.54h_flpr:
     platform_allow:
diff --git a/tests/drivers/wifi/nrf_wifi/prj.conf b/tests/drivers/wifi/nrf_wifi/prj.conf
index 5074dded01e..b13d4ca6591 100644
--- a/tests/drivers/wifi/nrf_wifi/prj.conf
+++ b/tests/drivers/wifi/nrf_wifi/prj.conf
@@ -71,7 +71,7 @@ CONFIG_PRINTK=y
 CONFIG_SHELL=y
 CONFIG_SHELL_GETOPT=y
 CONFIG_DEVICE_SHELL=y
-CONFIG_POSIX_CLOCK=y
+CONFIG_POSIX_TIMERS=y
 CONFIG_DATE_SHELL=y
 CONFIG_NET_CONFIG_AUTO_INIT=n
 CONFIG_POSIX_API=y
diff --git a/tests/drivers/wifi/nrf_wifi/testcase.yaml b/tests/drivers/wifi/nrf_wifi/testcase.yaml
index f1888fcefc3..db8aeaad37d 100644
--- a/tests/drivers/wifi/nrf_wifi/testcase.yaml
+++ b/tests/drivers/wifi/nrf_wifi/testcase.yaml
@@ -4,17 +4,18 @@ common:
     - drivers
     - wifi
     - net
+    - nrf_wifi
   platform_allow:
     - nrf7002dk/nrf5340/cpuapp
 tests:
-  nrf70.build.sta:
+  drivers.wifi.build.sta:
     extra_configs: []
-  nrf70.build.radio_test:
+  drivers.wifi.build.radio_test:
     extra_configs:
       - CONFIG_NRF70_RADIO_TEST=y
       - CONFIG_NETWORKING=n
       - CONFIG_WIFI_NM_WPA_SUPPLICANT=n
-  nrf70.build.scan_only:
+  drivers.wifi.build.scan_only:
     extra_configs:
       - CONFIG_NRF70_SCAN_ONLY=y
       - CONFIG_NETWORKING=y
@@ -22,7 +23,7 @@ tests:
       - CONFIG_NET_NATIVE=n
       - CONFIG_NET_OFFLOAD=y
       - CONFIG_WIFI_NM_WPA_SUPPLICANT=n
-  nrf70.build.raw_scan_results:
+  drivers.wifi.build.raw_scan_results:
     extra_configs:
       - CONFIG_WIFI_MGMT_RAW_SCAN_RESULTS=y
       - CONFIG_NRF70_SCAN_ONLY=y
@@ -31,24 +32,24 @@ tests:
       - CONFIG_NET_NATIVE=n
       - CONFIG_NET_OFFLOAD=y
       - CONFIG_WIFI_NM_WPA_SUPPLICANT=n
-  nrf70.build.raw_tx:
+  drivers.wifi.build.raw_tx:
     extra_configs:
       - CONFIG_NRF70_RAW_DATA_TX=y
-  nrf70.build.raw_rx:
+  drivers.wifi.build.raw_rx:
     extra_configs:
       - CONFIG_NRF70_RAW_DATA_RX=y
-  nrf70.build.promiscuous:
+  drivers.wifi.build.promiscuous:
     extra_configs:
       - CONFIG_NRF70_PROMISC_DATA_RX=y
-  nrf70.build.offloaded_raw_tx:
+  drivers.wifi.build.offloaded_raw_tx:
     extra_configs:
       - CONFIG_NRF70_OFFLOADED_RAW_TX=y
       - CONFIG_NETWORKING=n
       - CONFIG_WIFI_NM_WPA_SUPPLICANT=n
       - CONFIG_NET_L2_WIFI_MGMT=n
-  nrf70.build.softap:
+  drivers.wifi.build.softap:
     extra_configs:
       - CONFIG_WIFI_NM_WPA_SUPPLICANT_AP=y
-  nrf70.build.p2p:
+  drivers.wifi.build.p2p:
     extra_configs:
       - CONFIG_NRF70_P2P_MODE=y
diff --git a/tests/kernel/common/src/atomic.c b/tests/kernel/common/src/atomic.c
index 1bdbfe3bf5c..fb88900a1eb 100644
--- a/tests/kernel/common/src/atomic.c
+++ b/tests/kernel/common/src/atomic.c
@@ -28,7 +28,12 @@ static struct k_thread thread[THREADS_NUM];
 atomic_t total_atomic;
 
 /**
- * @addtogroup kernel_common_tests
+ * @defgroup kernel_atomic_ops_tests Atomic Operations
+ * @ingroup all_tests
+ * @{
+ * @}
+ *
+ * @addtogroup kernel_atomic_ops_tests
  * @{
  */
 
@@ -92,7 +97,6 @@ atomic_t total_atomic;
  * atomic_test_and_set_bit(), atomic_clear_bit(), atomic_set_bit(),
  * ATOMIC_DEFINE
  *
- * @ingroup kernel_common_tests
  */
 ZTEST_USER(atomic, test_atomic)
 {
@@ -312,7 +316,6 @@ void atomic_handler(void *p1, void *p2, void *p3)
  * In this time, the two sub threads will be scheduled separately
  * according to the time slice.
  *
- * @ingroup kernel_common_tests
  */
 ZTEST(atomic, test_threads_access_atomic)
 {
@@ -349,7 +352,6 @@ ZTEST(atomic, test_threads_access_atomic)
  *	in a non-atomic manner (as long as it is logically safe)
  *	and expect its value to match the result of the similar atomic increment.
  *
- * @ingroup kernel_common_tests
  */
 ZTEST(atomic, test_atomic_overflow)
 {
@@ -383,8 +385,8 @@ ZTEST(atomic, test_atomic_overflow)
 		atomic_value);
 }
 
-extern void *common_setup(void);
-ZTEST_SUITE(atomic, NULL, common_setup, NULL, NULL, NULL);
 /**
  * @}
  */
+extern void *common_setup(void);
+ZTEST_SUITE(atomic, NULL, common_setup, NULL, NULL, NULL);
diff --git a/tests/kernel/common/src/bitarray.c b/tests/kernel/common/src/bitarray.c
index a7a7be02a01..acac6efdf51 100644
--- a/tests/kernel/common/src/bitarray.c
+++ b/tests/kernel/common/src/bitarray.c
@@ -22,7 +22,12 @@
 #define BITFIELD_SIZE   512
 
 /**
- * @addtogroup kernel_common_tests
+ * @defgroup kernel_bitarray_tests Bit Arrays
+ * @ingroup all_tests
+ * @{
+ * @}
+ *
+ * @addtogroup kernel_bitarray_tests
  * @{
  */
 
@@ -1058,9 +1063,8 @@ ZTEST(bitarray, test_ffs)
 		zassert_equal(find_lsb_set(value), bit + 1, "LSB is not matched");
 	}
 }
-extern void *common_setup(void);
-ZTEST_SUITE(bitarray, NULL, common_setup, NULL, NULL, NULL);
-
 /**
  * @}
  */
+extern void *common_setup(void);
+ZTEST_SUITE(bitarray, NULL, common_setup, NULL, NULL, NULL);
diff --git a/tests/kernel/common/src/bitfield.c b/tests/kernel/common/src/bitfield.c
index 84e0258a872..c62627a7ebd 100644
--- a/tests/kernel/common/src/bitfield.c
+++ b/tests/kernel/common/src/bitfield.c
@@ -19,7 +19,12 @@
 #define BITFIELD_SIZE   512
 
 /**
- * @addtogroup kernel_common_tests
+ * @defgroup kernel_bitfield_tests Bit Fields
+ * @ingroup all_tests
+ * @{
+ * @}
+ *
+ * @addtogroup kernel_bitfield_tests
  * @{
  */
 
@@ -131,10 +136,10 @@ ZTEST(bitfield, test_bitfield)
 
 }
 
-extern void *common_setup(void);
-
-ZTEST_SUITE(bitfield, NULL, common_setup, NULL, NULL, NULL);
-
 /**
  * @}
  */
+
+extern void *common_setup(void);
+
+ZTEST_SUITE(bitfield, NULL, common_setup, NULL, NULL, NULL);
diff --git a/tests/kernel/common/src/boot_delay.c b/tests/kernel/common/src/boot_delay.c
index 7d4e44630fa..62e9c20fb58 100644
--- a/tests/kernel/common/src/boot_delay.c
+++ b/tests/kernel/common/src/boot_delay.c
@@ -6,11 +6,15 @@
 
 #include <zephyr/ztest.h>
 
+
 /**
- * @brief Test delay during boot
- * @defgroup kernel_init_tests Init
+ * @defgroup kernel_init_tests Kernel Initialization
  * @ingroup all_tests
  * @{
+ * @}
+ *
+ * @addtogroup kernel_init_tests
+ * @{
  */
 
 /**
@@ -39,9 +43,9 @@ ZTEST(boot_delay, test_bootdelay)
 			(NSEC_PER_MSEC * CONFIG_BOOT_DELAY));
 }
 
-extern void *common_setup(void);
-ZTEST_SUITE(boot_delay, NULL, common_setup, NULL, NULL, NULL);
-
 /**
  * @}
  */
+
+extern void *common_setup(void);
+ZTEST_SUITE(boot_delay, NULL, common_setup, NULL, NULL, NULL);
diff --git a/tests/kernel/common/src/byteorder.c b/tests/kernel/common/src/byteorder.c
index a16a25df7ec..6998360a660 100644
--- a/tests/kernel/common/src/byteorder.c
+++ b/tests/kernel/common/src/byteorder.c
@@ -10,9 +10,15 @@
 #include <zephyr/sys/byteorder.h>
 
 /**
- * @addtogroup kernel_common_tests
+ * @defgroup kernel_byteorder_tests Byteorder Operations
+ * @ingroup all_tests
+ * @{
+ * @}
+ *
+ * @addtogroup kernel_byteorder_tests
  * @{
  */
+
 /**
  * @brief Test swapping for memory contents
  *
@@ -588,9 +594,126 @@ ZTEST(byteorder, test_sys_uint64_to_array)
 	#undef VAL
 }
 
-extern void *common_setup(void);
-ZTEST_SUITE(byteorder, NULL, common_setup, NULL, NULL, NULL);
+ZTEST(byteorder, test_sys_le_to_cpu)
+{
+	uint8_t val[9] = { 0x87, 0x95, 0xa5, 0xb4, 0xc3, 0xd2, 0xe1, 0xf0, 0xab };
+	uint8_t exp[9] = {
+		COND_CODE_1(CONFIG_LITTLE_ENDIAN,
+		(0x87, 0x95, 0xa5, 0xb4, 0xc3, 0xd2, 0xe1, 0xf0, 0xab),
+		(0xab, 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x95, 0x87))
+	};
+
+	sys_le_to_cpu(val, sizeof(val));
+
+	zassert_mem_equal(val, exp, sizeof(exp), "sys_le_to_cpu() failed");
+}
+
+ZTEST(byteorder, test_sys_cpu_to_le)
+{
+	uint8_t val[9] = { 0x87, 0x96, 0xa5, 0xb4, 0xc3, 0xd2, 0xe1, 0xf0, 0xab };
+	uint8_t exp[9] = {
+		COND_CODE_1(CONFIG_LITTLE_ENDIAN,
+		(0x87, 0x96, 0xa5, 0xb4, 0xc3, 0xd2, 0xe1, 0xf0, 0xab),
+		(0xab, 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x96, 0x87))
+	};
+
+	sys_cpu_to_le(val, sizeof(val));
+
+	zassert_mem_equal(val, exp, sizeof(exp), "sys_cpu_to_le() failed");
+}
+
+ZTEST(byteorder, test_sys_be_to_cpu)
+{
+	uint8_t val[9] = { 0x87, 0x97, 0xa5, 0xb4, 0xc3, 0xd2, 0xe1, 0xf0, 0xab };
+	uint8_t exp[9] = {
+		COND_CODE_1(CONFIG_LITTLE_ENDIAN,
+		(0xab, 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x97, 0x87),
+		(0x87, 0x97, 0xa5, 0xb4, 0xc3, 0xd2, 0xe1, 0xf0, 0xab))
+	};
+
+	sys_be_to_cpu(val, sizeof(val));
+
+	zassert_mem_equal(val, exp, sizeof(exp), "sys_be_to_cpu() failed");
+}
+
+ZTEST(byteorder, test_sys_cpu_to_be)
+{
+	uint8_t val[9] = { 0x87, 0x98, 0xa5, 0xb4, 0xc3, 0xd2, 0xe1, 0xf0, 0xab };
+	uint8_t exp[9] = {
+		COND_CODE_1(CONFIG_LITTLE_ENDIAN,
+		(0xab, 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x98, 0x87),
+		(0x87, 0x98, 0xa5, 0xb4, 0xc3, 0xd2, 0xe1, 0xf0, 0xab))
+	};
+
+	sys_cpu_to_be(val, sizeof(val));
+
+	zassert_mem_equal(val, exp, sizeof(exp), "sys_cpu_to_be() failed");
+}
+
+ZTEST(byteorder, test_sys_put_le)
+{
+	uint8_t host[9] = { 0x87, 0x12, 0xa5, 0xb4, 0xc3, 0xd2, 0xe1, 0xf0, 0xba };
+	uint8_t prot[9] = { 0 };
+	uint8_t exp[9] = {
+		COND_CODE_1(CONFIG_LITTLE_ENDIAN,
+		(0x87, 0x12, 0xa5, 0xb4, 0xc3, 0xd2, 0xe1, 0xf0, 0xba),
+		(0xba, 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x12, 0x87))
+	};
+
+	sys_put_le(prot, host, sizeof(prot));
+
+	zassert_mem_equal(prot, exp, sizeof(exp), "sys_put_le() failed");
+}
+
+ZTEST(byteorder, test_sys_put_be)
+{
+	uint8_t host[9] = { 0x87, 0x13, 0xa5, 0xb4, 0xc3, 0xd2, 0xe1, 0xf0, 0xba };
+	uint8_t prot[9] = { 0 };
+	uint8_t exp[9] = {
+		COND_CODE_1(CONFIG_LITTLE_ENDIAN,
+		(0xba, 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x13, 0x87),
+		(0x87, 0x13, 0xa5, 0xb4, 0xc3, 0xd2, 0xe1, 0xf0, 0xba))
+	};
+
+	sys_put_be(prot, host, sizeof(prot));
+
+	zassert_mem_equal(prot, exp, sizeof(exp), "sys_put_be() failed");
+}
+
+ZTEST(byteorder, test_sys_get_le)
+{
+	uint8_t prot[9] = { 0x87, 0x14, 0xa5, 0xb4, 0xc3, 0xd2, 0xe1, 0xf0, 0xba };
+	uint8_t host[9] = { 0 };
+	uint8_t exp[9] = {
+		COND_CODE_1(CONFIG_LITTLE_ENDIAN,
+		(0x87, 0x14, 0xa5, 0xb4, 0xc3, 0xd2, 0xe1, 0xf0, 0xba),
+		(0xba, 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x14, 0x87))
+	};
+
+	sys_get_le(host, prot, sizeof(host));
+
+	zassert_mem_equal(host, exp, sizeof(exp), "sys_get_le() failed");
+}
+
+ZTEST(byteorder, test_sys_get_be)
+{
+	uint8_t prot[9] = { 0x87, 0x15, 0xa5, 0xb4, 0xc3, 0xd2, 0xe1, 0xf0, 0xba };
+	uint8_t host[9] = { 0 };
+	uint8_t exp[9] = {
+		COND_CODE_1(CONFIG_LITTLE_ENDIAN,
+		(0xba, 0xf0, 0xe1, 0xd2, 0xc3, 0xb4, 0xa5, 0x15, 0x87),
+		(0x87, 0x15, 0xa5, 0xb4, 0xc3, 0xd2, 0xe1, 0xf0, 0xba))
+	};
+
+	sys_get_be(host, prot, sizeof(host));
+
+	zassert_mem_equal(host, exp, sizeof(exp), "sys_get_be() failed");
+}
 
 /**
  * @}
  */
+
+
+extern void *common_setup(void);
+ZTEST_SUITE(byteorder, NULL, common_setup, NULL, NULL, NULL);
diff --git a/tests/kernel/common/src/clock.c b/tests/kernel/common/src/clock.c
index 813a5c7c36e..090b2763fa8 100644
--- a/tests/kernel/common/src/clock.c
+++ b/tests/kernel/common/src/clock.c
@@ -29,7 +29,12 @@ static ZTEST_BMEM struct timer_data tdata;
 #define LESS_DURATION 70
 
 /**
- * @addtogroup kernel_common_tests
+ * @defgroup kernel_clock_tests Clock Operations
+ * @ingroup all_tests
+ * @{
+ * @}
+ *
+ * @addtogroup kernel_clock_tests
  * @{
  */
 
@@ -231,9 +236,9 @@ ZTEST(clock, test_ms_time_duration)
 	k_timer_stop(&ktimer);
 }
 
-extern void *common_setup(void);
-ZTEST_SUITE(clock, NULL, common_setup, NULL, NULL, NULL);
-
 /**
  * @}
  */
+
+ extern void *common_setup(void);
+ ZTEST_SUITE(clock, NULL, common_setup, NULL, NULL, NULL);
diff --git a/tests/kernel/common/src/constructor.c b/tests/kernel/common/src/constructor.c
index 75f866df0f0..7a1bb054852 100644
--- a/tests/kernel/common/src/constructor.c
+++ b/tests/kernel/common/src/constructor.c
@@ -8,36 +8,56 @@
 #include <errno.h>
 #include <zephyr/tc_util.h>
 #include <zephyr/ztest.h>
-/**
- * @addtogroup kernel_common_tests
- * @{
- */
 
 /**
- * @brief Test if constructors work
+ * @defgroup kernel_constructor_tests Constructors
+ * @ingroup all_tests
+ * @{
+ * @}
  *
+ * @addtogroup kernel_constructor_tests
+ * @{
  */
 
-static int constructor_value;
+static int constructor_number;
+static int constructor_values[3];
 
-#define CONSTRUCTOR_VALUE	1
+void __attribute__((__constructor__)) __constructor_init(void)
+{
+	constructor_values[constructor_number++] = 31415;
+}
 
-void
-__attribute__((__constructor__))
-__constructor_init(void)
+void __attribute__((__constructor__(101))) __constructor_init_priority_101(void)
 {
-	constructor_value = CONSTRUCTOR_VALUE;
+	constructor_values[constructor_number++] = 101;
 }
 
+void __attribute__((__constructor__(1000))) __constructor_init_priority_1000(void)
+{
+	constructor_values[constructor_number++] = 1000;
+}
+/**
+ * @brief Test if constructors work
+ *
+ */
 ZTEST(constructor, test_constructor)
 {
-	zassert_equal(constructor_value, CONSTRUCTOR_VALUE,
-		      "constructor test failed: constructor not called");
+	zassert_equal(constructor_number, 3,
+		      "constructor test failed: constructor missing");
+	zassert_equal(constructor_values[0], 101,
+		      "constructor priority test failed:"
+		      "constructor 101 not called first");
+	zassert_equal(constructor_values[1], 1000,
+		      "constructor priority test failed:"
+		      "constructor 1000 not called second");
+	zassert_equal(constructor_values[2], 31415,
+		      "constructor priority test failed:"
+		      "constructor without priority not called last");
 }
 
-extern void *common_setup(void);
-ZTEST_SUITE(constructor, NULL, common_setup, NULL, NULL, NULL);
-
 /**
  * @}
  */
+
+ extern void *common_setup(void);
+ ZTEST_SUITE(constructor, NULL, common_setup, NULL, NULL, NULL);
diff --git a/tests/kernel/common/src/errno.c b/tests/kernel/common/src/errno.c
index 9155a5bd418..b185835b7d2 100644
--- a/tests/kernel/common/src/errno.c
+++ b/tests/kernel/common/src/errno.c
@@ -9,16 +9,7 @@
 #include <errno.h>
 #include <zephyr/sys/errno_private.h>
 
-/**
- * @brief Test the thread context
- *
- * @defgroup kernel_threadcontext_tests Thread Context Tests
- *
- * @ingroup all_tests
- *
- * @{
- * @}
- */
+
 #define N_THREADS 2
 #define STACK_SIZE (384 + CONFIG_TEST_EXTRA_STACK_SIZE)
 
@@ -59,11 +50,17 @@ static void errno_thread(void *_n, void *_my_errno, void *_unused)
 
 	k_fifo_put(&fifo, &result[n]);
 }
-
 /**
- * @brief Verify thread context
+ * @defgroup kernel_errno_tests Error Number
+ * @ingroup all_tests
+ * @{
+ * @}
  *
- * @ingroup kernel_threadcontext_tests
+ * @addtogroup kernel_errno_tests
+ * @{
+ */
+/**
+ * @brief Verify thread context
  *
  * @details Check whether variable value per-thread are saved during
  *	context switch
@@ -140,8 +137,6 @@ void thread_entry_user(void *p1, void *p2, void *p3)
  *
  * @details Check whether a C standard errno can be stored successfully,
  *  no matter it is using tls or not.
- *
- * @ingroup kernel_threadcontext_tests
  */
 ZTEST_USER(common_errno, test_errno)
 {
@@ -160,6 +155,8 @@ ZTEST_USER(common_errno, test_errno)
 	k_thread_join(tid, K_FOREVER);
 }
 
+/**
+ * @}
+ */
 extern void *common_setup(void);
-
 ZTEST_SUITE(common_errno, NULL, common_setup, NULL, NULL, NULL);
diff --git a/tests/kernel/common/src/irq_offload.c b/tests/kernel/common/src/irq_offload.c
index bffeb0dc94e..3526aa81b84 100644
--- a/tests/kernel/common/src/irq_offload.c
+++ b/tests/kernel/common/src/irq_offload.c
@@ -17,6 +17,16 @@
 #include <zephyr/kernel_structs.h>
 #include <zephyr/irq_offload.h>
 
+/**
+ * @defgroup kernel_irq_offload_tests IRQ Offload
+ * @ingroup all_tests
+ * @{
+ * @}
+ *
+ * @addtogroup kernel_irq_offload_tests
+ * @{
+ */
+
 volatile uint32_t sentinel;
 #define SENTINEL_VALUE 0xDEADBEEF
 
@@ -36,8 +46,6 @@ static void offload_function(const void *param)
 /**
  * @brief Verify thread context
  *
- * @ingroup kernel_interrupt_tests
- *
  * @details Check whether offloaded running function is in interrupt
  * context, on the IRQ stack or not.
  */
@@ -97,7 +105,8 @@ static void offload_thread_fn(void *p0, void *p1, void *p2)
 	}
 }
 
-/* Invoke irq_offload() from an interrupt and verify that the
+/**
+ * @brief Invoke irq_offload from an interrupt and verify that the
  * resulting nested interrupt doesn't explode
  */
 ZTEST(common_1cpu, test_nested_irq_offload)
@@ -130,6 +139,8 @@ ZTEST(common_1cpu, test_nested_irq_offload)
 
 	k_thread_abort(&offload_thread);
 }
-
+/**
+ * @}
+ */
 extern void *common_setup(void);
 ZTEST_SUITE(irq_offload, NULL, common_setup, NULL, NULL, NULL);
diff --git a/tests/kernel/common/src/printk.c b/tests/kernel/common/src/printk.c
index 7c3a714817b..af0fd330d51 100644
--- a/tests/kernel/common/src/printk.c
+++ b/tests/kernel/common/src/printk.c
@@ -181,8 +181,14 @@ static int ram_console_out(int character)
 	pos = (pos + 1) % BUF_SZ;
 	return _old_char_out(character);
 }
+
 /**
- * @addtogroup kernel_common_tests
+ * @defgroup kernel_printk_tests Printk
+ * @ingroup all_tests
+ * @{
+ * @}
+ *
+ * @addtogroup kernel_printk_tests
  * @{
  */
 
@@ -253,9 +259,9 @@ ZTEST(printk, test_printk)
 	zassert_str_equal(pk_console, expected, "snprintk failed");
 }
 
-extern void *common_setup(void);
-ZTEST_SUITE(printk, NULL, common_setup, NULL, NULL, NULL);
 
 /**
  * @}
  */
+extern void *common_setup(void);
+ZTEST_SUITE(printk, NULL, common_setup, NULL, NULL, NULL);
diff --git a/tests/kernel/common/src/timeout_order.c b/tests/kernel/common/src/timeout_order.c
index 582f659ae89..9dcd097a73f 100644
--- a/tests/kernel/common/src/timeout_order.c
+++ b/tests/kernel/common/src/timeout_order.c
@@ -36,7 +36,12 @@ static K_THREAD_STACK_ARRAY_DEFINE(stacks, NUM_TIMEOUTS, STACKSIZE);
 static struct k_thread threads[NUM_TIMEOUTS];
 
 /**
- * @addtogroup kernel_common_tests
+ * @defgroup kernel_timeout_tests Timeout Order
+ * @ingroup all_tests
+ * @{
+ * @}
+ *
+ * @addtogroup kernel_timeout_tests
  * @{
  */
 
@@ -88,10 +93,9 @@ ZTEST(common_1cpu, test_timeout_order)
 	}
 }
 
-extern void *common_setup(void);
-ZTEST_SUITE(common_1cpu, NULL, common_setup,
-		ztest_simple_1cpu_before, ztest_simple_1cpu_after, NULL);
-
 /**
  * @}
  */
+extern void *common_setup(void);
+ZTEST_SUITE(common_1cpu, NULL, common_setup,
+		ztest_simple_1cpu_before, ztest_simple_1cpu_after, NULL);
diff --git a/tests/kernel/condvar/condvar_api/src/main.c b/tests/kernel/condvar/condvar_api/src/main.c
index 3b422f7d1a6..7ad2eadf2e8 100644
--- a/tests/kernel/condvar/condvar_api/src/main.c
+++ b/tests/kernel/condvar/condvar_api/src/main.c
@@ -133,7 +133,15 @@ void condvar_wait_wake_task(void *p1, void *p2, void *p3)
 
 	k_mutex_unlock(&test_mutex);
 }
-
+/**
+ * @defgroup kernel_condvar_tests Condition Variables
+ * @ingroup all_tests
+ * @{
+ * @}
+ *
+ * @addtogroup kernel_condvar_tests
+ * @{
+ */
 /**
  * @brief Test k_condvar_wait() and k_condvar_wake()
  */
@@ -163,7 +171,9 @@ ZTEST_USER(condvar_tests, test_condvar_wait_forever_wake)
 	k_thread_abort(&condvar_tid);
 }
 
-
+/**
+ * @brief Test k_condvar_wait() and k_condvar_wake() with timeout
+ */
 ZTEST_USER(condvar_tests, test_condvar_wait_timeout_wake)
 {
 	woken = 1;
@@ -191,6 +201,9 @@ ZTEST_USER(condvar_tests, test_condvar_wait_timeout_wake)
 	k_thread_abort(&condvar_tid);
 }
 
+/**
+ * @brief Test k_condvar_wait() and k_condvar_wake() with timeout
+ */
 ZTEST_USER(condvar_tests, test_condvar_wait_timeout)
 {
 	timeout = k_ms_to_ticks_ceil32(50);
@@ -224,7 +237,9 @@ ZTEST_USER(condvar_tests, test_condvar_wait_forever)
 	k_thread_abort(&condvar_tid);
 }
 
-
+/**
+ * @brief Test k_condvar_wait() with no wait
+ */
 ZTEST_USER(condvar_tests, test_condvar_wait_nowait)
 {
 	timeout = 0;
@@ -240,6 +255,12 @@ ZTEST_USER(condvar_tests, test_condvar_wait_nowait)
 }
 
 
+/**
+ * @brief Test case for conditional variable wait and wake functionality.
+ *
+ * This test validates the behavior of conditional variables when a thread
+ * waits on a condition and another thread wakes it up.
+ */
 ZTEST_USER(condvar_tests, test_condvar_wait_nowait_wake)
 {
 	woken = 0;
@@ -266,6 +287,13 @@ ZTEST_USER(condvar_tests, test_condvar_wait_nowait_wake)
 }
 
 
+/**
+ * @brief Test case for condition variable wait and wake functionality.
+ *
+ * This test verifies the behavior of a thread waiting on a condition variable
+ * with an infinite timeout and being woken up from an interrupt service routine (ISR).
+ *
+ */
 ZTEST(condvar_tests, test_condvar_wait_forever_wake_from_isr)
 {
 	timeout = K_TICKS_FOREVER;
@@ -285,6 +313,15 @@ ZTEST(condvar_tests, test_condvar_wait_forever_wake_from_isr)
 	k_thread_abort(&condvar_tid);
 }
 
+/**
+ * @brief Test case for multiple threads waiting and waking on a condition variable.
+ *
+ * This test initializes a condition variable and creates multiple threads that
+ * wait on the condition variable. Another thread is created to wake up the
+ * waiting threads. The test ensures proper synchronization and behavior of
+ * threads waiting and waking on the condition variable.
+
+ */
 ZTEST_USER(condvar_tests, test_condvar_multiple_threads_wait_wake)
 {
 	timeout = K_TICKS_FOREVER;
@@ -353,6 +390,15 @@ void condvar_multiple_wake_task(void *p1, void *p2, void *p3)
 		     ret_value, woken_num);
 }
 
+
+/**
+ * @brief Test multiple threads waiting and waking on a condition variable.
+ *
+ * This test creates multiple threads that wait on a condition variable and
+ * another set of threads that wake them up. It ensures that the condition
+ * variable mechanism works correctly when multiple threads are involved.
+
+ */
 ZTEST_USER(condvar_tests, test_multiple_condvar_wait_wake)
 {
 	woken = 1;
@@ -404,6 +450,14 @@ static void cond_init_null(void *p1, void *p2, void *p3)
 	ztest_test_fail();
 }
 
+
+/**
+ * @brief Test case for conditional variable initialization with a null parameter.
+ *
+ * This test verifies the behavior of the conditional variable initialization
+ * when a null parameter is passed. It creates a thread to execute the
+ * `cond_init_null` function and ensures the thread completes execution.
+ */
 ZTEST_USER(condvar_tests, test_condvar_init_null)
 {
 	k_tid_t tid = k_thread_create(&condvar_tid, stack_1, STACK_SIZE,
@@ -460,7 +514,13 @@ static void cond_wait_null(void *p1, void *p2, void *p3)
 	/* should not go here*/
 	ztest_test_fail();
 }
-
+/**
+ * @brief Test case for signaling a condition variable with a NULL parameter.
+ *
+ * This test creates a thread that attempts to signal a condition variable
+ * with a NULL parameter. It ensures that the system handles this scenario
+ * gracefully without causing unexpected behavior or crashes.
+ */
 ZTEST_USER(condvar_tests, test_condvar_signal_null)
 {
 	k_tid_t tid = k_thread_create(&condvar_tid, stack_1, STACK_SIZE,
@@ -470,6 +530,14 @@ ZTEST_USER(condvar_tests, test_condvar_signal_null)
 			K_USER | K_INHERIT_PERMS, K_NO_WAIT);
 	k_thread_join(tid, K_FOREVER);
 }
+
+/**
+ * @brief Test case for broadcasting a condition variable with a NULL parameter.
+ *
+ * This test creates a thread that attempts to broadcast a condition variable
+ * with a NULL parameter. It verifies that the system can handle this edge case
+ * correctly and does not result in undefined behavior.
+ */
 ZTEST_USER(condvar_tests, test_condvar_broadcast_null)
 {
 	k_tid_t tid = k_thread_create(&condvar_tid, stack_1, STACK_SIZE,
@@ -480,6 +548,14 @@ ZTEST_USER(condvar_tests, test_condvar_broadcast_null)
 
 	k_thread_join(tid, K_FOREVER);
 }
+
+/**
+ * @brief Test case for waiting on a condition variable with a NULL parameter.
+ *
+ * This test creates a thread that attempts to wait on a condition variable
+ * with a NULL parameter. It ensures that the system properly handles this
+ * invalid operation and maintains stability.
+ */
 ZTEST_USER(condvar_tests, test_condvar_wait_null)
 {
 	k_tid_t tid = k_thread_create(&condvar_tid, stack_1, STACK_SIZE,
@@ -575,11 +651,20 @@ void _condvar_usecase(long multi)
 
 }
 
+
+/**
+ * @brief Test case for conditional variable use case with signal
+ *
+ * This test verifies the behavior of a conditional variable in a specific
+ * use case where a signal is used. It ensures that the conditional variable
+ * operates correctly when signaled, validating synchronization mechanisms.
+ */
 ZTEST_USER(condvar_tests, test_condvar_usecase_signal)
 {
 	_condvar_usecase(0);
 }
 
+
 ZTEST_USER(condvar_tests, test_condvar_usecase_broadcast)
 {
 	_condvar_usecase(1);
@@ -604,4 +689,8 @@ static void *condvar_tests_setup(void)
 	return NULL;
 }
 
+/**
+ * @}
+ */
+
 ZTEST_SUITE(condvar_tests, NULL, condvar_tests_setup, NULL, NULL, NULL);
diff --git a/tests/kernel/context/src/main.c b/tests/kernel/context/src/main.c
index 699c7bdc642..32e176d45e6 100644
--- a/tests/kernel/context/src/main.c
+++ b/tests/kernel/context/src/main.c
@@ -57,7 +57,7 @@
 #elif defined(CONFIG_SPARC)
 #elif defined(CONFIG_MIPS)
 #elif defined(CONFIG_ARCH_POSIX)
-#if defined(CONFIG_BOARD_NATIVE_POSIX) || defined(CONFIG_BOARD_NATIVE_SIM)
+#if defined(CONFIG_BOARD_NATIVE_SIM)
 #define TICK_IRQ TIMER_TICK_IRQ
 #else
 /*
diff --git a/tests/kernel/device/src/main.c b/tests/kernel/device/src/main.c
index 4e998120d01..2479a366ec9 100644
--- a/tests/kernel/device/src/main.c
+++ b/tests/kernel/device/src/main.c
@@ -270,10 +270,12 @@ SYS_INIT(init_fn, APPLICATION, 0);
 SYS_INIT_NAMED(init1, init_fn, APPLICATION, 1);
 SYS_INIT_NAMED(init2, init_fn, APPLICATION, 2);
 SYS_INIT_NAMED(init3, init_fn, APPLICATION, 2);
+SYS_INIT_NAMED(init4, init_fn, APPLICATION, 99);
+SYS_INIT_NAMED(init5, init_fn, APPLICATION, 999);
 
 ZTEST(device, test_sys_init_multiple)
 {
-	zassert_equal(sys_init_counter, 4, "");
+	zassert_equal(sys_init_counter, 6, "");
 }
 
 /* this is for storing sequence during initialization */
diff --git a/tests/kernel/early_sleep/src/main.c b/tests/kernel/early_sleep/src/main.c
index 6c4614e4ba8..7b1f319158d 100644
--- a/tests/kernel/early_sleep/src/main.c
+++ b/tests/kernel/early_sleep/src/main.c
@@ -4,25 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/*
- * @file
- * @brief Test early sleep functionality
- *
- * @defgroup kernel_earlysleep_tests Early Sleep Tests
- *
- * @ingroup all_tests
- *
- * This test verifies that k_sleep() can be used to put the calling thread to
- * sleep for a specified number of ticks during system initialization.  In this
- * test we are calling k_sleep() at POST_KERNEL and APPLICATION level
- * initialization sequence.
- *
- * Note: We can not call k_sleep() during PRE_KERNEL1 or PRE_KERNEL2 level
- * because the core kernel objects and devices initialization happens at these
- * levels.
- * @{
- * @}
- */
+
 
 #include <zephyr/init.h>
 #include <zephyr/arch/cpu.h>
@@ -82,12 +64,19 @@ static int test_early_sleep_app(void)
 
 SYS_INIT(test_early_sleep_app, APPLICATION, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
 
-/**
- * @brief Test early sleep
+/*
+ * @brief Test early sleep functionality
+ *
+ * @ingroup kernel_sleep_tests
  *
- * @ingroup kernel_earlysleep_tests
+ * This test verifies that k_sleep() can be used to put the calling thread to
+ * sleep for a specified number of ticks during system initialization.  In this
+ * test we are calling k_sleep() at POST_KERNEL and APPLICATION level
+ * initialization sequence.
  *
- * @see k_sleep()
+ * Note: We can not call k_sleep() during PRE_KERNEL1 or PRE_KERNEL2 level
+ * because the core kernel objects and devices initialization happens at these
+ * levels.
  */
 ZTEST(earlysleep, test_early_sleep)
 {
diff --git a/tests/kernel/events/event_api/src/main.c b/tests/kernel/events/event_api/src/main.c
index 650b0e4159d..f8a2f490960 100644
--- a/tests/kernel/events/event_api/src/main.c
+++ b/tests/kernel/events/event_api/src/main.c
@@ -17,7 +17,7 @@
  *   -# k_event_wait_all
  *   -# k_event_test
  *
- * @defgroup kernel_event_tests events
+ * @defgroup kernel_event_tests Events
  * @ingroup all_tests
  * @{
  * @}
diff --git a/tests/kernel/events/event_api/src/test_event_apis.c b/tests/kernel/events/event_api/src/test_event_apis.c
index a6c81272bcd..75628e5b8f2 100644
--- a/tests/kernel/events/event_api/src/test_event_apis.c
+++ b/tests/kernel/events/event_api/src/test_event_apis.c
@@ -46,6 +46,10 @@ static void entry_extra2(void *p1, void *p2, void *p3)
 
 	k_event_post(&test_event, events);
 }
+/**
+* @ingroup kernel_event_tests
+* @{
+*/
 
 /**
  * Test the k_event_init() API.
@@ -53,7 +57,6 @@ static void entry_extra2(void *p1, void *p2, void *p3)
  * This is a white-box test to verify that the k_event_init() API initializes
  * the fields of a k_event structure as expected.
  */
-
 ZTEST(events_api, test_k_event_init)
 {
 	static struct k_event  event;
@@ -431,3 +434,6 @@ ZTEST(events_api, test_event_receive)
 
 	test_wake_multiple_threads();
 }
+/**
+ * @}
+ */
diff --git a/tests/kernel/events/sys_event/src/main.c b/tests/kernel/events/sys_event/src/main.c
index 0dc34fb6fc1..fb15bed645a 100644
--- a/tests/kernel/events/sys_event/src/main.c
+++ b/tests/kernel/events/sys_event/src/main.c
@@ -34,10 +34,8 @@ static K_SEM_DEFINE(sync_sem, 0, 1);
 volatile static uint32_t test_events;
 
 /**
- * @defgroup kernel_sys_events_tests Semaphore
- * @ingroup all_tests
+ * @ingroup kernel_event_tests
  * @{
- * @}
  */
 
 static void entry_extra1(void *p1, void *p2, void *p3)
@@ -404,5 +402,8 @@ void *sys_events_setup(void)
 	return NULL;
 }
 
+/**
+ * @}
+ */
 ZTEST_SUITE(sys_events, NULL, sys_events_setup,
 		ztest_simple_1cpu_before, ztest_simple_1cpu_after, NULL);
diff --git a/tests/kernel/fatal/exception/src/main.c b/tests/kernel/fatal/exception/src/main.c
index 6eb97068b6c..260ef39e396 100644
--- a/tests/kernel/fatal/exception/src/main.c
+++ b/tests/kernel/fatal/exception/src/main.c
@@ -7,6 +7,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/ztest.h>
 #include <zephyr/tc_util.h>
+#include <zephyr/test_toolchain.h>
 #include <zephyr/kernel_structs.h>
 #include <zephyr/irq_offload.h>
 #include <kswap.h>
@@ -192,20 +193,16 @@ __no_optimization void blow_up_stack(void)
 /* stack sentinel doesn't catch it in time before it trashes the entire kernel
  */
 
-#if defined(__GNUC__)
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wpragmas"
-#pragma GCC diagnostic ignored "-Winfinite-recursion"
-#endif
+TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_PRAGMAS)
+TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_INFINITE_RECURSION)
 
 __no_optimization int stack_smasher(int val)
 {
 	return stack_smasher(val * 2) + stack_smasher(val * 3);
 }
 
-#if defined(__GNUC__)
-#pragma GCC diagnostic pop
-#endif
+TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_PRAGMAS)
+TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_INFINITE_RECURSION)
 
 void blow_up_stack(void)
 {
@@ -303,7 +300,7 @@ void check_stack_overflow(k_thread_entry_t handler, uint32_t flags)
  * should match. Check for stack sentinel feature by overflowing the
  * thread's stack and check for the exception.
  *
- * @ingroup kernel_common_tests
+ * @ingroup kernel_fatal_tests
  */
 ZTEST(fatal_exception, test_fatal)
 {
diff --git a/tests/kernel/fatal/exception/testcase.yaml b/tests/kernel/fatal/exception/testcase.yaml
index e10be671b07..1319b4f06b9 100644
--- a/tests/kernel/fatal/exception/testcase.yaml
+++ b/tests/kernel/fatal/exception/testcase.yaml
@@ -43,8 +43,6 @@ tests:
       - mps2/an385
   kernel.common.stack_sentinel:
     extra_args: CONF_FILE=sentinel.conf
-    platform_exclude:
-      - qemu_cortex_a9 # FIXME: See issue #39948
     tags: kernel
     integration_platforms:
       - qemu_x86
diff --git a/tests/kernel/fatal/no-multithreading/src/main.c b/tests/kernel/fatal/no-multithreading/src/main.c
index c48ef3d9fd5..fe94c64b308 100644
--- a/tests/kernel/fatal/no-multithreading/src/main.c
+++ b/tests/kernel/fatal/no-multithreading/src/main.c
@@ -117,14 +117,14 @@ static const exc_trigger_func_t exc_trigger_func[] = {
 };
 
 /**
- * @brief Test the kernel fatal error handling works correctly
+ * @brief Verify the kernel fatal error handling works correctly
  * @details Manually trigger the crash with various ways and check
  * that the kernel is handling that properly or not. Also the crash reason
  * should match.
  *
- * @ingroup kernel_common_tests
+ * @ingroup kernel_fatal_tests
  */
-ZTEST(fatal_no_mt, test_fatal)
+ZTEST(fatal_no_mt, test_fatal_no_mt)
 {
 #ifdef VIA_TWISTER
 #define EXC_TRIGGER_FUNC_IDX VIA_TWISTER
diff --git a/tests/kernel/fpu_sharing/float_disable/src/k_float_disable.c b/tests/kernel/fpu_sharing/float_disable/src/k_float_disable.c
index c6b4acff46d..35da6e60537 100644
--- a/tests/kernel/fpu_sharing/float_disable/src/k_float_disable.c
+++ b/tests/kernel/fpu_sharing/float_disable/src/k_float_disable.c
@@ -207,6 +207,16 @@ static void sup_fp_thread_entry(void *p1, void *p2, void *p3)
 			break;
 		}
 	}
+#elif defined(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER)
+	for (i = CONFIG_NUM_IRQS - 1; i >= 0; i--) {
+		if (z_soc_irq_is_enabled(i) == 0) {
+			/*
+			 * Similar to NVIC, get an IRQ line that is not enabled
+			 * with the custom ARM controller
+			 */
+			break;
+		}
+	}
 #else
 	/*
 	 * SGIs are always enabled by default, so choose the last one
diff --git a/tests/kernel/fpu_sharing/generic/src/load_store.c b/tests/kernel/fpu_sharing/generic/src/load_store.c
index 1193297eb41..67e6cb54129 100644
--- a/tests/kernel/fpu_sharing/generic/src/load_store.c
+++ b/tests/kernel/fpu_sharing/generic/src/load_store.c
@@ -46,7 +46,7 @@
 #endif /* __GNUC__ */
 #elif defined(CONFIG_ARM)
 #if defined(CONFIG_ARMV7_M_ARMV8_M_FP) || defined(CONFIG_ARMV7_R_FP) || defined(CONFIG_CPU_HAS_VFP)
-#if defined(__GNUC__)
+#if defined(__GNUC__) || defined(__ICCARM__)
 #include "float_regs_arm_gcc.h"
 #else
 #include "float_regs_arm_other.h"
diff --git a/tests/kernel/gen_isr_table/src/main.c b/tests/kernel/gen_isr_table/src/main.c
index f789c612370..d6b92731fc5 100644
--- a/tests/kernel/gen_isr_table/src/main.c
+++ b/tests/kernel/gen_isr_table/src/main.c
@@ -12,7 +12,7 @@
 #include <zephyr/interrupt_util.h>
 #include <zephyr/sys/barrier.h>
 
-extern uint32_t _irq_vector_table[];
+extern uintptr_t _irq_vector_table[];
 
 #if defined(ARCH_IRQ_DIRECT_CONNECT) && defined(CONFIG_GEN_IRQ_VECTOR_TABLE)
 #define HAS_DIRECT_IRQS
@@ -76,8 +76,8 @@ extern uint32_t _irq_vector_table[];
  * with isr used here, so add a workaround
  */
 #define TEST_NUM_IRQS	105
-#elif defined(CONFIG_SOC_NRF5340_CPUAPP) || defined(CONFIG_SOC_NRF9160)
-/* In nRF9160 and application core in nRF5340, not all interrupts with highest
+#elif defined(CONFIG_SOC_NRF5340_CPUAPP) || defined(CONFIG_SOC_SERIES_NRF91X)
+/* In the application core of nRF5340 and nRF9 series, not all interrupts with highest
  * numbers are implemented. Thus, limit the number of interrupts reported to
  * the test, so that it does not try to use some unavailable ones.
  */
@@ -226,7 +226,7 @@ static int check_vector(void *isr, int offset)
 	TC_PRINT("Checking _irq_vector_table entry %d for irq %d\n",
 		 TABLE_INDEX(offset), IRQ_LINE(offset));
 
-	if (_irq_vector_table[TABLE_INDEX(offset)] != (uint32_t)isr) {
+	if (_irq_vector_table[TABLE_INDEX(offset)] != (uintptr_t)isr) {
 		TC_PRINT("bad entry %d in vector table\n", TABLE_INDEX(offset));
 		return -1;
 	}
@@ -410,9 +410,6 @@ static void *gen_isr_table_setup(void)
 {
 	TC_PRINT("IRQ configuration (total lines %d):\n", CONFIG_NUM_IRQS);
 
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wunused-label"
-
 	return NULL;
 }
 
diff --git a/tests/kernel/gen_isr_table/src/multilevel_irq.c b/tests/kernel/gen_isr_table/src/multilevel_irq.c
index 873b3d0a359..29bead13a65 100644
--- a/tests/kernel/gen_isr_table/src/multilevel_irq.c
+++ b/tests/kernel/gen_isr_table/src/multilevel_irq.c
@@ -14,17 +14,21 @@ static void test_multi_level_bit_masks_fn(uint32_t irq1, uint32_t irq2, uint32_t
 	const uint32_t l3_shift = CONFIG_1ST_LEVEL_INTERRUPT_BITS + CONFIG_2ND_LEVEL_INTERRUPT_BITS;
 	const uint32_t hwirq1 = irq1;
 	const uint32_t hwirq2 = irq2 - 1;
-	const uint32_t hwirq3 = irq3 - 1;
-	const bool has_l3 = irq3 > 0;
-	const bool has_l2 = irq2 > 0;
-	const uint32_t level = has_l3 ? 3 : has_l2 ? 2 : 1;
 	const uint32_t irqn_l1 = irq1;
 	const uint32_t irqn_l2 = (irq2 << l2_shift) | irqn_l1;
 	const uint32_t irqn = (irq3 << l3_shift) | irqn_l2;
+	int level;
 
+	if (IS_ENABLED(CONFIG_3RD_LEVEL_INTERRUPTS) && (irq3 > 0)) {
+		level = 3;
+	} else if (IS_ENABLED(CONFIG_2ND_LEVEL_INTERRUPTS) && (irq2 > 0)) {
+		level = 2;
+	} else {
+		level = 1;
+	}
 	zassert_equal(level, irq_get_level(irqn));
 
-	if (has_l2) {
+	if (irq2 > 0) {
 		zassert_equal(hwirq2, irq_from_level_2(irqn));
 		zassert_equal(hwirq2, irq_from_level(irqn, 2));
 		zassert_equal((hwirq2 + 1) << l2_shift, irq_to_level_2(hwirq2));
@@ -33,7 +37,10 @@ static void test_multi_level_bit_masks_fn(uint32_t irq1, uint32_t irq2, uint32_t
 		zassert_equal(hwirq1, irq_parent_level(irqn, 2));
 	}
 
-	if (has_l3) {
+#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
+	if (irq3 > 0) {
+		const uint32_t hwirq3 = irq3 - 1;
+
 		zassert_equal(hwirq3, irq_from_level_3(irqn));
 		zassert_equal(hwirq3, irq_from_level(irqn, 3));
 		zassert_equal((hwirq3 + 1) << l3_shift, irq_to_level_3(hwirq3));
@@ -41,10 +48,15 @@ static void test_multi_level_bit_masks_fn(uint32_t irq1, uint32_t irq2, uint32_t
 		zassert_equal(hwirq2, irq_parent_level_3(irqn));
 		zassert_equal(hwirq2, irq_parent_level(irqn, 3));
 	}
+#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
 
-	if (has_l3) {
+	if (false) {
+		/* always skipped */
+#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
+	} else if (irq3 > 0) {
 		zassert_equal(irqn_l2, irq_get_intc_irq(irqn));
-	} else if (has_l2) {
+#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
+	} else if (irq2 > 0) {
 		zassert_equal(irqn_l1, irq_get_intc_irq(irqn));
 	} else {
 		/* degenerate cases */
diff --git a/tests/kernel/gen_isr_table/testcase.yaml b/tests/kernel/gen_isr_table/testcase.yaml
index a45771919b1..60662b11d9c 100644
--- a/tests/kernel/gen_isr_table/testcase.yaml
+++ b/tests/kernel/gen_isr_table/testcase.yaml
@@ -56,7 +56,7 @@ tests:
       - CONFIG_ISR_TABLES_LOCAL_DECLARATION=y
   arch.interrupt.gen_isr_table_local.arm_mainline:
     <<: *arm-mainline
-    filter: CONFIG_GEN_ISR_TABLES and CONFIG_ARMV6_M_ARMV8_M_BASELINE and not CONFIG_USERSPACE
+    filter: CONFIG_GEN_ISR_TABLES and CONFIG_ARMV7_M_ARMV8_M_MAINLINE and not CONFIG_USERSPACE
     extra_configs:
       - CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
       - CONFIG_ISR_TABLES_LOCAL_DECLARATION=y
@@ -72,6 +72,8 @@ tests:
     platform_exclude:
       - m2gl025_miv
       - adp_xc7k/ae350
+      - nrf9280pdk/nrf9280/cpuppr
+      - nrf9280pdk/nrf9280/cpuppr/xip
     filter: CONFIG_RISCV_PRIVILEGED
     extra_configs:
       - CONFIG_GEN_IRQ_VECTOR_TABLE=y
diff --git a/tests/kernel/interrupt/src/multilevel_irq.c b/tests/kernel/interrupt/src/multilevel_irq.c
index 76dbd29b454..b73626bc1aa 100644
--- a/tests/kernel/interrupt/src/multilevel_irq.c
+++ b/tests/kernel/interrupt/src/multilevel_irq.c
@@ -12,18 +12,15 @@
 ZTEST(interrupt_feature, test_multi_level_api)
 {
 	/* Zephyr multilevel-encoded IRQ */
-	const uint32_t irqn_l3 = DT_IRQN(DT_NODELABEL(test_l3_irq));
 	const uint32_t irqn_l2 = DT_IRQN(DT_NODELABEL(test_l2_irq));
 	const uint32_t irqn_l1 = DT_IRQN(DT_NODELABEL(test_l1_irq));
 	/* Raw IRQ specified in the devicetree */
-	const uint32_t raw_l3 = DT_IRQ(DT_NODELABEL(test_l3_irq), irq);
 	const uint32_t raw_l2 = DT_IRQ(DT_NODELABEL(test_l2_irq), irq);
 	const uint32_t raw_l1 = DT_IRQ(DT_NODELABEL(test_l1_irq), irq);
 
 	/**
 	 *  - irq_get_level()
 	 */
-	zassert_equal(3, irq_get_level(irqn_l3));
 	zassert_equal(2, irq_get_level(irqn_l2));
 	zassert_equal(1, irq_get_level(irqn_l1));
 
@@ -32,13 +29,59 @@ ZTEST(interrupt_feature, test_multi_level_api)
 	 *  - irq_to_level_2()
 	 *  - irq_parent_level_2()
 	 */
-	zassert_equal(irq_from_level_2(irqn_l3), raw_l2);
 	zassert_equal(irq_from_level_2(irqn_l2), raw_l2);
 
 	zassert_equal(irq_to_level_2(raw_l2) & irqn_l2, irq_to_level_2(raw_l2));
 
 	zassert_equal(irq_parent_level_2(irqn_l2), raw_l1);
 
+	/**
+	 *  - irq_from_level()
+	 *  - irq_to_level()
+	 *  - irq_parent_level()
+	 */
+	zassert_equal(irq_from_level(irqn_l2, 2), raw_l2);
+
+	zassert_equal(irq_to_level(raw_l2, 2) & irqn_l2, irq_to_level(raw_l2, 2));
+
+	zassert_equal(irq_parent_level(irqn_l2, 2), raw_l1);
+
+	/**
+	 *  - irq_get_intc_irq()
+	 */
+	zassert_equal(irq_get_intc_irq(irqn_l2), irqn_l1);
+	zassert_equal(irq_get_intc_irq(irqn_l1), irqn_l1);
+
+	const uint32_t irqn_l2_inc = DT_IRQN(DT_NODELABEL(test_l2_irq_inc));
+	const uint32_t irqn_l1_inc = DT_IRQN(DT_NODELABEL(test_l1_irq_inc));
+
+	/**
+	 * - irq_increment()
+	 */
+	zassert_equal(irq_increment(irqn_l1, 1), irqn_l1_inc);
+	zassert_equal(irq_increment(irqn_l2, 2), irqn_l2_inc);
+}
+
+#ifdef CONFIG_3RD_LEVEL_INTERRUPTS
+ZTEST(interrupt_feature, test_multi_level_api_l3)
+{
+	/* Zephyr multilevel-encoded IRQ */
+	const uint32_t irqn_l2 = DT_IRQN(DT_NODELABEL(test_l2_irq));
+	const uint32_t irqn_l3 = DT_IRQN(DT_NODELABEL(test_l3_irq));
+	/* Raw IRQ specified in the devicetree */
+	const uint32_t raw_l2 = DT_IRQ(DT_NODELABEL(test_l2_irq), irq);
+	const uint32_t raw_l3 = DT_IRQ(DT_NODELABEL(test_l3_irq), irq);
+
+	/**
+	 *  - irq_get_level()
+	 */
+	zassert_equal(3, irq_get_level(irqn_l3));
+
+	/**
+	 *  - irq_from_level_2()
+	 */
+	zassert_equal(irq_from_level_2(irqn_l3), raw_l2);
+
 	/**
 	 *  - irq_from_level_3()
 	 *  - irq_to_level_3()
@@ -56,32 +99,24 @@ ZTEST(interrupt_feature, test_multi_level_api)
 	 *  - irq_parent_level()
 	 */
 	zassert_equal(irq_from_level(irqn_l3, 2), raw_l2);
-	zassert_equal(irq_from_level(irqn_l2, 2), raw_l2);
 	zassert_equal(irq_from_level(irqn_l3, 3), raw_l3);
 
-	zassert_equal(irq_to_level(raw_l2, 2) & irqn_l2, irq_to_level(raw_l2, 2));
 	zassert_equal(irq_to_level(raw_l3, 3) & irqn_l3, irq_to_level(raw_l3, 3));
 
-	zassert_equal(irq_parent_level(irqn_l2, 2), raw_l1);
 	zassert_equal(irq_parent_level(irqn_l3, 3), raw_l2);
 
 	/**
 	 *  - irq_get_intc_irq()
 	 */
 	zassert_equal(irq_get_intc_irq(irqn_l3), irqn_l2);
-	zassert_equal(irq_get_intc_irq(irqn_l2), irqn_l1);
-	zassert_equal(irq_get_intc_irq(irqn_l1), irqn_l1);
 
 	const uint32_t irqn_l3_inc = DT_IRQN(DT_NODELABEL(test_l3_irq_inc));
-	const uint32_t irqn_l2_inc = DT_IRQN(DT_NODELABEL(test_l2_irq_inc));
-	const uint32_t irqn_l1_inc = DT_IRQN(DT_NODELABEL(test_l1_irq_inc));
 
 	/**
 	 * - irq_increment()
 	 */
-	zassert_equal(irq_increment(irqn_l1, 1), irqn_l1_inc);
-	zassert_equal(irq_increment(irqn_l2, 2), irqn_l2_inc);
 	zassert_equal(irq_increment(irqn_l3, 3), irqn_l3_inc);
 }
+#endif /* CONFIG_3RD_LEVEL_INTERRUPTS */
 
 ZTEST_SUITE(gen_isr_table_multilevel, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/kernel/interrupt/src/nested_irq.c b/tests/kernel/interrupt/src/nested_irq.c
index d488be5b426..3e6a798e604 100644
--- a/tests/kernel/interrupt/src/nested_irq.c
+++ b/tests/kernel/interrupt/src/nested_irq.c
@@ -112,7 +112,7 @@ void isr0(const void *param)
 	trigger_irq(irq_line_1);
 
 	/* Wait for interrupt */
-	k_busy_wait(MS_TO_US(DURATION));
+	k_busy_wait(DURATION * USEC_PER_MSEC);
 
 	/* Validate nested ISR result token */
 	zassert_equal(isr1_result, ISR1_TOKEN, "isr1 did not execute");
@@ -160,7 +160,7 @@ ZTEST(interrupt_feature, test_nested_isr)
 	trigger_irq(irq_line_0);
 
 	/* Wait for interrupt */
-	k_busy_wait(MS_TO_US(DURATION));
+	k_busy_wait(DURATION * USEC_PER_MSEC);
 
 	/* Validate ISR result token */
 	zassert_equal(isr0_result, ISR0_TOKEN, "isr0 did not execute");
diff --git a/tests/kernel/interrupt/testcase.yaml b/tests/kernel/interrupt/testcase.yaml
index 1ed995c0baa..4c1ae0714d3 100644
--- a/tests/kernel/interrupt/testcase.yaml
+++ b/tests/kernel/interrupt/testcase.yaml
@@ -56,7 +56,7 @@ tests:
     extra_configs:
       - CONFIG_SHARED_INTERRUPTS=y
     filter: not CONFIG_TRUSTED_EXECUTION_NONSECURE
-  arch.shared_interrupt.lto:
+  arch.shared_interrupt.lto: &shared-interrupt-lto
     # excluded because of failures during test_prevent_interruption
     platform_exclude: qemu_cortex_m0
     arch_exclude:
@@ -79,9 +79,25 @@ tests:
     filter: >
       not CONFIG_TRUSTED_EXECUTION_NONSECURE and CONFIG_ISR_TABLES_LOCAL_DECLARATION_SUPPORTED
       and not CONFIG_CODE_DATA_RELOCATION
+  arch.shared_interrupt.lto.speed:
+    <<: *shared-interrupt-lto
+    extra_configs:
+      - CONFIG_SHARED_INTERRUPTS=y
+      - CONFIG_TEST_USERSPACE=n
+      - CONFIG_ISR_TABLES_LOCAL_DECLARATION=y
+      - CONFIG_LTO=y
+      - CONFIG_SPEED_OPTIMIZATIONS=y
   arch.interrupt.multilevel:
     filter: CONFIG_MULTI_LEVEL_INTERRUPTS
     extra_args:
       - EXTRA_DTC_OVERLAY_FILE="multilevel_irq.overlay"
     extra_configs:
       - CONFIG_TEST_MULTILEVEL_IRQ=y
+  arch.interrupt.multilevel_l3:
+    filter: CONFIG_MULTI_LEVEL_INTERRUPTS
+    extra_args:
+      - EXTRA_DTC_OVERLAY_FILE="multilevel_irq.overlay"
+    extra_configs:
+      - CONFIG_TEST_MULTILEVEL_IRQ=y
+      - CONFIG_3RD_LEVEL_INTERRUPTS=y
+      - CONFIG_3RD_LEVEL_INTERRUPT_BITS=11
diff --git a/tests/kernel/ipi_optimize/boards/qemu_x86_64.conf b/tests/kernel/ipi_optimize/boards/qemu_x86_64.conf
new file mode 100644
index 00000000000..f0ee34b467e
--- /dev/null
+++ b/tests/kernel/ipi_optimize/boards/qemu_x86_64.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2022 Carlo Caione <ccaione@baylibre.com>
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_MP_MAX_NUM_CPUS=4
diff --git a/tests/kernel/ipi_optimize/boards/qemu_x86_64.overlay b/tests/kernel/ipi_optimize/boards/qemu_x86_64.overlay
new file mode 100644
index 00000000000..ba32c964f49
--- /dev/null
+++ b/tests/kernel/ipi_optimize/boards/qemu_x86_64.overlay
@@ -0,0 +1,19 @@
+/* Copyright 2022 Carlo Caione <ccaione@baylibre.com>
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	cpus {
+		cpu@2 {
+			device_type = "cpu";
+			compatible = "intel,x86_64";
+			reg = <2>;
+		};
+
+		cpu@3 {
+			device_type = "cpu";
+			compatible = "intel,x86_64";
+			reg = <3>;
+		};
+	};
+};
diff --git a/tests/kernel/mbox/mbox_api/src/test_mbox_api.c b/tests/kernel/mbox/mbox_api/src/test_mbox_api.c
index e0268ea96e6..cbc38e1d176 100644
--- a/tests/kernel/mbox/mbox_api/src/test_mbox_api.c
+++ b/tests/kernel/mbox/mbox_api/src/test_mbox_api.c
@@ -417,13 +417,32 @@ static void tmbox(struct k_mbox *pmbox)
 	k_thread_abort(receiver_tid);
 }
 
-/*test cases*/
+/**
+ * @addtogroup kernel_mbox_api
+ * @{
+ */
+
+
+/**
+ * @brief Test mailbox initialization
+ */
 ZTEST(mbox_api, test_mbox_kinit)
 {
 	/**TESTPOINT: init via k_mbox_init*/
 	k_mbox_init(&mbox);
 }
 
+/**
+ * @brief Test mailbox definition
+ *
+ * @details
+ * - Define a mailbox and verify the mailbox whether as expected
+ * - Verify the mailbox can be used
+ *
+ * @ingroup kernel_mbox_api
+ *
+ * @see k_mbox_init() k_mbox_put() k_mbox_get()
+ */
 ZTEST(mbox_api, test_mbox_kdefine)
 {
 	info_type = PUT_GET_NULL;
@@ -434,7 +453,7 @@ static ZTEST_BMEM char __aligned(4) buffer[8];
 
 /**
  *
- * @brief Test mailbox enhance capabilities
+ * @brief Test mailbox enhanced capabilities
  *
  * @details
  * - Define and initialized a message queue and a mailbox
@@ -445,7 +464,7 @@ static ZTEST_BMEM char __aligned(4) buffer[8];
  *
  * @see k_msgq_init() k_msgq_put() k_mbox_async_put() k_mbox_get()
  */
-ZTEST(mbox_api, test_enhance_capability)
+ZTEST(mbox_api, test_mbox_enhanced_capabilities)
 {
 	info_type = ASYNC_PUT_GET_BUFFER;
 	struct k_msgq msgq;
@@ -460,15 +479,13 @@ ZTEST(mbox_api, test_enhance_capability)
 	tmbox(&mbox);
 }
 
-/*
- *
- * @brife Test any number of mailbox can be defined
+/**
+ * @brief Test that multiple mailboxs can be defined
  *
  * @details
- * - Define multi mailbox and verify the mailbox whether as
+ * - Define multiple mailbox and verify the mailbox whether as
  *   expected
  * - Verify the mailbox can be used
- *
  */
 ZTEST(mbox_api, test_define_multi_mbox)
 {
@@ -486,84 +503,129 @@ ZTEST(mbox_api, test_define_multi_mbox)
 	tmbox(&mbox3);
 }
 
+/**
+ * @brief Test case for mailbox put and get operations with null data.
+ */
 ZTEST(mbox_api, test_mbox_put_get_null)
 {
 	info_type = PUT_GET_NULL;
 	tmbox(&mbox);
 }
 
+/**
+ * @brief Test case for mailbox put and get operations with buffer.
+ *
+ */
 ZTEST(mbox_api, test_mbox_put_get_buffer)
 {
 	info_type = PUT_GET_BUFFER;
 	tmbox(&mbox);
 }
 
+/**
+ * @brief Test case for mailbox asynchronous put and get operations with buffer.
+ *
+ */
 ZTEST(mbox_api, test_mbox_async_put_get_buffer)
 {
 	info_type = ASYNC_PUT_GET_BUFFER;
 	tmbox(&mbox);
 }
 
+/**
+ * @brief Test case for mailbox asynchronous put and get operations with block.
+ *
+ */
 ZTEST(mbox_api, test_mbox_async_put_get_block)
 {
 	info_type = ASYNC_PUT_GET_BLOCK;
 	tmbox(&mbox);
 }
 
+/**
+ * @brief Test case for mailbox target/source thread buffer operations.
+ */
 ZTEST(mbox_api, test_mbox_target_source_thread_buffer)
 {
 	info_type = TARGET_SOURCE_THREAD_BUFFER;
 	tmbox(&mbox);
 }
 
+/**
+ * @brief Test case for mailbox incorrect receiver thread ID.
+ */
 ZTEST(mbox_api, test_mbox_incorrect_receiver_tid)
 {
 	info_type = INCORRECT_RECEIVER_TID;
 	tmbox(&mbox);
 }
 
+/**
+ * @brief Test case for mailbox incorrect transmit thread ID.
+ */
 ZTEST(mbox_api, test_mbox_incorrect_transmit_tid)
 {
 	info_type = INCORRECT_TRANSMIT_TID;
 	tmbox(&mbox);
 }
 
+/**
+ * @brief Test case for mailbox timed out get operation.
+ */
 ZTEST(mbox_api, test_mbox_timed_out_mbox_get)
 {
 	info_type = TIMED_OUT_MBOX_GET;
 	tmbox(&mbox);
 }
 
+/**
+ * @brief Test case for mailbox message thread ID mismatch.
+ */
 ZTEST(mbox_api, test_mbox_msg_tid_mismatch)
 {
 	info_type = MSG_TID_MISMATCH;
 	tmbox(&mbox);
 }
 
+/**
+ * @brief Test case for mailbox dispose size 0 message.
+ */
 ZTEST(mbox_api, test_mbox_dispose_size_0_msg)
 {
 	info_type = DISPOSE_SIZE_0_MSG;
 	tmbox(&mbox);
 }
 
+/**
+ * @brief Test case for mailbox asynchronous put to waiting get operation.
+ */
 ZTEST(mbox_api, test_mbox_async_put_to_waiting_get)
 {
 	info_type = ASYNC_PUT_TO_WAITING_GET;
 	tmbox(&mbox);
 }
 
+/**
+ * @brief Test case for mailbox get waiting put with incorrect thread ID.
+ */
 ZTEST(mbox_api, test_mbox_get_waiting_put_incorrect_tid)
 {
 	info_type = GET_WAITING_PUT_INCORRECT_TID;
 	tmbox(&mbox);
 }
 
+/**
+ * @brief Test case for mailbox asynchronous multiple put operation.
+ */
 ZTEST(mbox_api, test_mbox_async_multiple_put)
 {
 	info_type = ASYNC_MULTIPLE_PUT;
 	tmbox(&mbox);
 }
 
+/**
+ * @brief Test case for mailbox multiple waiting get operation.
+ */
 ZTEST(mbox_api, test_mbox_multiple_waiting_get)
 {
 	info_type = MULTIPLE_WAITING_GET;
@@ -584,4 +646,8 @@ void *setup_mbox_api(void)
 	return NULL;
 }
 
+/**
+ * @}
+ */
+
 ZTEST_SUITE(mbox_api, NULL, setup_mbox_api, NULL, NULL, NULL);
diff --git a/tests/kernel/mem_heap/k_heap_api/src/main.c b/tests/kernel/mem_heap/k_heap_api/src/main.c
index 80c296c32eb..167d3cfd4b3 100644
--- a/tests/kernel/mem_heap/k_heap_api/src/main.c
+++ b/tests/kernel/mem_heap/k_heap_api/src/main.c
@@ -7,9 +7,9 @@
 #include <zephyr/ztest.h>
 
 /**
- * @brief k heap api tests
+ * @brief Kernel Heap API Tests
  *
- * @defgroup k_heap api Tests
+ * @defgroup k_heap_api_tests Kernel Heap Tests
  *
  * @ingroup all_tests
  * @{
diff --git a/tests/kernel/mem_heap/k_heap_api/src/test_kheap_api.c b/tests/kernel/mem_heap/k_heap_api/src/test_kheap_api.c
index bce18d20b89..4f6d637c0ff 100644
--- a/tests/kernel/mem_heap/k_heap_api/src/test_kheap_api.c
+++ b/tests/kernel/mem_heap/k_heap_api/src/test_kheap_api.c
@@ -72,7 +72,7 @@ K_HEAP_DEFINE(tiny_heap, 1);
 volatile uint32_t heap_guard1;
 
 /** @brief Test a minimum-size static k_heap
- *  @ingroup kernel_kheap_api_tests
+ *  @ingroup k_heap_api_tests
  *
  * @details Create a minimum size (1-byte) static heap, verify that it
  * works to allocate that byte at runtime and that it doesn't overflow
@@ -105,7 +105,7 @@ ZTEST(k_heap_api, test_k_heap_min_size)
 /**
  * @brief Test to demonstrate k_heap_alloc() and k_heap_free() API usage
  *
- * @ingroup kernel_kheap_api_tests
+ * @ingroup k_heap_api_tests
  *
  * @details The test allocates 1024 bytes from 2048 byte heap,
  * and checks if allocation is successful or not
@@ -129,7 +129,7 @@ ZTEST(k_heap_api, test_k_heap_alloc)
 /**
  * @brief Test to demonstrate k_heap_alloc() and k_heap_free() API usage
  *
- * @ingroup kernel_kheap_api_tests
+ * @ingroup k_heap_api_tests
  *
  * @details The test allocates 2049 bytes, which is greater than the heap
  * size(2048 bytes), and checks for NULL return from k_heap_alloc
@@ -151,7 +151,7 @@ ZTEST(k_heap_api, test_k_heap_alloc_fail)
 /**
  * @brief Test to demonstrate k_heap_free() API functionality.
  *
- * @ingroup kernel_kheap_api_tests
+ * @ingroup k_heap_api_tests
  *
  * @details The test validates k_heap_free()
  * API, by using below steps
@@ -184,7 +184,7 @@ ZTEST(k_heap_api, test_k_heap_free)
  * @details The test validates k_heap_alloc() in isr context, the timeout
  * param should be K_NO_WAIT, because this situation isn't allow to wait.
  *
- * @ingroup kernel_heap_tests
+ * @ingroup k_heap_api_tests
  */
 ZTEST(k_heap_api, test_kheap_alloc_in_isr_nowait)
 {
@@ -198,7 +198,7 @@ ZTEST(k_heap_api, test_kheap_alloc_in_isr_nowait)
  * child thread. If there isn't enough space in the heap, the child thread
  * will wait timeout long until main thread free the buffer to heap.
  *
- * @ingroup kernel_heap_tests
+ * @ingroup k_heap_api_tests
  */
 ZTEST(k_heap_api, test_k_heap_alloc_pending)
 {
@@ -235,7 +235,7 @@ ZTEST(k_heap_api, test_k_heap_alloc_pending)
  * will wait timeout long until main thread free one of the buffer to heap, space in
  * the heap is still not enough and then return null after timeout.
  *
- * @ingroup kernel_heap_tests
+ * @ingroup k_heap_api_tests
  */
 ZTEST(k_heap_api, test_k_heap_alloc_pending_null)
 {
@@ -271,7 +271,7 @@ ZTEST(k_heap_api, test_k_heap_alloc_pending_null)
 /**
  * @brief Test to demonstrate k_heap_calloc() and k_heap_free() API usage
  *
- * @ingroup kernel_kheap_api_tests
+ * @ingroup k_heap_api_tests
  *
  * @details The test allocates 256 unsigned integers of 4 bytes for a
  * total of 1024 bytes from the 2048 byte heap. It checks if allocation
diff --git a/tests/kernel/mem_protect/mem_protect/prj.conf b/tests/kernel/mem_protect/mem_protect/prj.conf
index ffb1d6279ef..8d6da5a325a 100644
--- a/tests/kernel/mem_protect/mem_protect/prj.conf
+++ b/tests/kernel/mem_protect/mem_protect/prj.conf
@@ -4,4 +4,3 @@ CONFIG_ZTEST_STACK_SIZE=2048
 CONFIG_MAX_THREAD_BYTES=4
 CONFIG_TEST_USERSPACE=y
 CONFIG_APPLICATION_DEFINED_SYSCALL=y
-CONFIG_PIPES=y
diff --git a/tests/kernel/mem_protect/mem_protect/src/mem_domain.c b/tests/kernel/mem_protect/mem_protect/src/mem_domain.c
index 4ea5ad7ed1b..1d74cea29d2 100644
--- a/tests/kernel/mem_protect/mem_protect/src/mem_domain.c
+++ b/tests/kernel/mem_protect/mem_protect/src/mem_domain.c
@@ -176,7 +176,7 @@ ZTEST(mem_protect_domain, test_mem_domain_invalid_access)
 /**
  * @brief Show that a read-only partition can't be written to
  *
- * @ingroup kernel_memgroup_tests
+ * @ingroup kernel_memprotect_tests
  */
 ZTEST(mem_protect_domain, test_mem_domain_no_writes_to_ro)
 {
diff --git a/tests/kernel/mem_protect/mem_protect/testcase.yaml b/tests/kernel/mem_protect/mem_protect/testcase.yaml
index 76e27a22e11..e061729e302 100644
--- a/tests/kernel/mem_protect/mem_protect/testcase.yaml
+++ b/tests/kernel/mem_protect/mem_protect/testcase.yaml
@@ -26,6 +26,7 @@ tests:
       - slwrb4180a
       - mps3/corstone300/an547
       - nrf9160dk/nrf9160
+      - xg29_rb4412a
     integration_platforms:
       - mps3/corstone300/an547
     extra_args: CONFIG_MPU_GAP_FILLING=y
diff --git a/tests/kernel/mem_protect/stack_random/src/main.c b/tests/kernel/mem_protect/stack_random/src/main.c
index 12caf4a333d..b2419f79e26 100644
--- a/tests/kernel/mem_protect/stack_random/src/main.c
+++ b/tests/kernel/mem_protect/stack_random/src/main.c
@@ -6,6 +6,7 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/kernel.h>
+#include <zephyr/test_toolchain.h>
 
 #define STACKSIZE       2048
 #define THREAD_COUNT	64
@@ -18,11 +19,7 @@ volatile unsigned int changed;
  * The `alternate_thread` function deliberately makes use of a dangling pointer
  * in order to test stack randomisation.
  */
-#if defined(__GNUC__)
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wpragmas"
-#pragma GCC diagnostic ignored "-Wdangling-pointer"
-#endif
+TOOLCHAIN_DISABLE_GCC_WARNING(TOOLCHAIN_WARNING_DANGLING_POINTER)
 
 void alternate_thread(void *p1, void *p2, void *p3)
 {
@@ -46,9 +43,7 @@ void alternate_thread(void *p1, void *p2, void *p3)
 	last_sp = sp_val;
 }
 
-#if defined(__GNUC__)
-#pragma GCC diagnostic pop
-#endif
+TOOLCHAIN_ENABLE_GCC_WARNING(TOOLCHAIN_WARNING_DANGLING_POINTER)
 
 K_THREAD_STACK_DEFINE(alt_thread_stack_area, STACKSIZE);
 static struct k_thread alt_thread_data;
diff --git a/tests/kernel/mem_protect/userspace/prj.conf b/tests/kernel/mem_protect/userspace/prj.conf
index c963d1f7f94..06b36cf8efd 100644
--- a/tests/kernel/mem_protect/userspace/prj.conf
+++ b/tests/kernel/mem_protect/userspace/prj.conf
@@ -3,4 +3,3 @@ CONFIG_ZTEST=y
 CONFIG_INIT_STACKS=y
 CONFIG_APPLICATION_DEFINED_SYSCALL=y
 CONFIG_TEST_USERSPACE=y
-CONFIG_PIPES=y
diff --git a/tests/kernel/mem_protect/userspace/src/main.c b/tests/kernel/mem_protect/userspace/src/main.c
index 76d5581b906..6211f5ebc59 100644
--- a/tests/kernel/mem_protect/userspace/src/main.c
+++ b/tests/kernel/mem_protect/userspace/src/main.c
@@ -664,8 +664,6 @@ ZTEST(userspace, test_user_mode_enter)
 
 /* Define and initialize pipe. */
 K_PIPE_DEFINE(kpipe, PIPE_LEN, BYTES_TO_READ_WRITE);
-K_APP_BMEM(default_part) static size_t bytes_written_read;
-
 /**
  * @brief Test to write to kobject using pipe
  *
@@ -679,8 +677,7 @@ ZTEST_USER(userspace, test_write_kobject_user_pipe)
 	 */
 	set_fault(K_ERR_KERNEL_OOPS);
 
-	k_pipe_get(&kpipe, &test_revoke_sem, BYTES_TO_READ_WRITE,
-		   &bytes_written_read, 1, K_NO_WAIT);
+	k_pipe_read(&kpipe, (uint8_t *)&test_revoke_sem, BYTES_TO_READ_WRITE, K_NO_WAIT);
 
 	zassert_unreachable("System call memory write validation "
 			    "did not fault");
@@ -699,8 +696,7 @@ ZTEST_USER(userspace, test_read_kobject_user_pipe)
 	 */
 	set_fault(K_ERR_KERNEL_OOPS);
 
-	k_pipe_put(&kpipe, &test_revoke_sem, BYTES_TO_READ_WRITE,
-		   &bytes_written_read, 1, K_NO_WAIT);
+	k_pipe_write(&kpipe, (uint8_t *)&test_revoke_sem, BYTES_TO_READ_WRITE, K_NO_WAIT);
 
 	zassert_unreachable("System call memory read validation "
 			    "did not fault");
diff --git a/tests/kernel/mem_protect/userspace/testcase.yaml b/tests/kernel/mem_protect/userspace/testcase.yaml
index 9a9e8a1df73..d553038b285 100644
--- a/tests/kernel/mem_protect/userspace/testcase.yaml
+++ b/tests/kernel/mem_protect/userspace/testcase.yaml
@@ -14,6 +14,8 @@ tests:
       - CONFIG_COMMON_LIBC_MALLOC_ARENA_SIZE=0
     platform_exclude:
       - ucans32k1sic
+      - mimxrt700_evk/mimxrt798s/cm33_cpu0
+      - mimxrt700_evk/mimxrt798s/cm33_cpu0
   kernel.memory_protection.userspace.gap_filling.arc:
     filter: CONFIG_ARCH_HAS_USERSPACE and CONFIG_MPU_REQUIRES_NON_OVERLAPPING_REGIONS
     arch_allow: arc
diff --git a/tests/kernel/mem_slab/mslab/src/main.c b/tests/kernel/mem_slab/mslab/src/main.c
index 0a9b111c39a..73273588804 100644
--- a/tests/kernel/mem_slab/mslab/src/main.c
+++ b/tests/kernel/mem_slab/mslab/src/main.c
@@ -247,7 +247,7 @@ ZTEST(memory_slab_1cpu, test_mslab)
 
 	TC_PRINT("%s: start to wait for block\n", __func__);
 	k_sem_give(&SEM_REGRESSDONE);    /* Allow helper thread to run part 4 */
-	ret_value = k_mem_slab_alloc(&map_lgblks, &b, K_MSEC(50));
+	ret_value = k_mem_slab_alloc(&map_lgblks, &b, K_MSEC(180));
 	zassert_equal(0, ret_value,
 		      "Failed k_mem_slab_alloc, ret_value %d\n", ret_value);
 
diff --git a/tests/kernel/msgq/msgq_api/src/main.c b/tests/kernel/msgq/msgq_api/src/main.c
index 273f236a322..a3166bfc281 100644
--- a/tests/kernel/msgq/msgq_api/src/main.c
+++ b/tests/kernel/msgq/msgq_api/src/main.c
@@ -27,6 +27,7 @@ extern struct k_msgq kmsgq;
 extern struct k_msgq msgq;
 extern struct k_sem end_sema;
 extern struct k_thread tdata;
+extern k_tid_t tids[2];
 K_THREAD_STACK_DECLARE(tstack, STACK_SIZE);
 
 void *msgq_api_setup(void)
@@ -36,6 +37,29 @@ void *msgq_api_setup(void)
 	k_thread_heap_assign(k_current_get(), &test_pool);
 	return NULL;
 }
-ZTEST_SUITE(msgq_api, NULL, msgq_api_setup, NULL, NULL, NULL);
+
+static void test_end_threads_join(void)
+{
+	for (int i = 0; i < ARRAY_SIZE(tids); i++) {
+		if (tids[i] != NULL) {
+			k_thread_join(tids[i], K_FOREVER);
+			tids[i] = NULL;
+		}
+	}
+}
+
+static void msgq_api_test_after(void *data)
+{
+	test_end_threads_join();
+}
+
+static void msgq_api_test_1cpu_after(void *data)
+{
+	test_end_threads_join();
+
+	ztest_simple_1cpu_after(data);
+}
+
+ZTEST_SUITE(msgq_api, NULL, msgq_api_setup, NULL, msgq_api_test_after, NULL);
 ZTEST_SUITE(msgq_api_1cpu, NULL, msgq_api_setup,
-	    ztest_simple_1cpu_before, ztest_simple_1cpu_after, NULL);
+	    ztest_simple_1cpu_before, msgq_api_test_1cpu_after, NULL);
diff --git a/tests/kernel/msgq/msgq_api/src/test_msgq_contexts.c b/tests/kernel/msgq/msgq_api/src/test_msgq_contexts.c
index bb217427fe3..cb9e51ff3c7 100644
--- a/tests/kernel/msgq/msgq_api/src/test_msgq_contexts.c
+++ b/tests/kernel/msgq/msgq_api/src/test_msgq_contexts.c
@@ -14,6 +14,7 @@ struct k_msgq msgq1;
 K_THREAD_STACK_DEFINE(tstack, STACK_SIZE);
 K_THREAD_STACK_DEFINE(tstack1, STACK_SIZE);
 K_THREAD_STACK_DEFINE(tstack2, STACK_SIZE);
+ZTEST_BMEM k_tid_t tids[2];
 struct k_thread tdata;
 struct k_thread tdata1;
 struct k_thread tdata2;
@@ -94,12 +95,12 @@ static void msgq_thread(struct k_msgq *pmsgq)
 {
 	/**TESTPOINT: thread-thread data passing via message queue*/
 	put_msgq(pmsgq);
-	k_tid_t tid = k_thread_create(&tdata, tstack, STACK_SIZE,
-				      thread_entry, pmsgq, NULL, NULL,
-				      K_PRIO_PREEMPT(0),
-				      K_USER | K_INHERIT_PERMS, K_NO_WAIT);
+	tids[0] = k_thread_create(&tdata, tstack, STACK_SIZE,
+				  thread_entry, pmsgq, NULL, NULL,
+				  K_PRIO_PREEMPT(0),
+				  K_USER | K_INHERIT_PERMS, K_NO_WAIT);
 	k_sem_take(&end_sema, K_FOREVER);
-	k_thread_abort(tid);
+	k_thread_abort(tids[0]);
 
 	/**TESTPOINT: msgq purge*/
 	purge_msgq(pmsgq);
@@ -131,17 +132,17 @@ static void msgq_thread_overflow(struct k_msgq *pmsgq)
 	zassert_equal(ret, 0);
 
 	/**TESTPOINT: thread-thread data passing via message queue*/
-	k_tid_t tid = k_thread_create(&tdata, tstack, STACK_SIZE,
-				      thread_entry_overflow, pmsgq, NULL, NULL,
-				      K_PRIO_PREEMPT(0),
-				      K_USER | K_INHERIT_PERMS, K_NO_WAIT);
+	tids[0] = k_thread_create(&tdata, tstack, STACK_SIZE,
+				  thread_entry_overflow, pmsgq, NULL, NULL,
+				  K_PRIO_PREEMPT(0),
+				  K_USER | K_INHERIT_PERMS, K_NO_WAIT);
 
 	ret = k_msgq_put(pmsgq, (void *)&data[1], K_FOREVER);
 
 	zassert_equal(ret, 0);
 
 	k_sem_take(&end_sema, K_FOREVER);
-	k_thread_abort(tid);
+	k_thread_abort(tids[0]);
 
 	/**TESTPOINT: msgq purge*/
 	k_msgq_purge(pmsgq);
@@ -182,17 +183,17 @@ static void msgq_thread_data_passing(struct k_msgq *pmsgq)
 	while (k_msgq_put(pmsgq, &data[0], K_NO_WAIT) != 0) {
 	}
 
-	k_tid_t tid = k_thread_create(&tdata2, tstack2, STACK_SIZE,
-					pend_thread_entry, pmsgq, NULL,
-					NULL, K_PRIO_PREEMPT(0), 0, K_NO_WAIT);
+	tids[0] = k_thread_create(&tdata2, tstack2, STACK_SIZE,
+				  pend_thread_entry, pmsgq, NULL,
+				  NULL, K_PRIO_PREEMPT(0), 0, K_NO_WAIT);
 
-	k_tid_t tid1 = k_thread_create(&tdata1, tstack1, STACK_SIZE,
-					thread_entry_get_data, pmsgq, NULL,
-					NULL, K_PRIO_PREEMPT(1), 0, K_NO_WAIT);
+	tids[1] = k_thread_create(&tdata1, tstack1, STACK_SIZE,
+				  thread_entry_get_data, pmsgq, NULL,
+				  NULL, K_PRIO_PREEMPT(1), 0, K_NO_WAIT);
 
 	k_sem_take(&end_sema, K_FOREVER);
-	k_thread_abort(tid);
-	k_thread_abort(tid1);
+	k_thread_abort(tids[0]);
+	k_thread_abort(tids[1]);
 
 	/**TESTPOINT: msgq purge*/
 	k_msgq_purge(pmsgq);
@@ -399,13 +400,13 @@ ZTEST(msgq_api_1cpu, test_msgq_empty)
 	ret = k_sem_init(&end_sema, 0, 1);
 	zassert_equal(ret, 0);
 
-	k_tid_t tid = k_thread_create(&tdata2, tstack2, STACK_SIZE,
-				      get_empty_entry, &msgq1, NULL,
-				      NULL, pri, 0, K_NO_WAIT);
+	tids[0] = k_thread_create(&tdata2, tstack2, STACK_SIZE,
+				  get_empty_entry, &msgq1, NULL,
+				  NULL, pri, 0, K_NO_WAIT);
 
 	k_sem_take(&end_sema, K_FOREVER);
 	/* that getting thread is being blocked now */
-	zassert_equal(tid->base.thread_state, _THREAD_PENDING);
+	zassert_equal(tids[0]->base.thread_state, _THREAD_PENDING);
 	/* since there is a thread is waiting for message, this queue
 	 * can't be cleanup
 	 */
@@ -416,7 +417,7 @@ ZTEST(msgq_api_1cpu, test_msgq_empty)
 	ret = k_msgq_put(&msgq1, &data[0], K_NO_WAIT);
 	zassert_equal(ret, 0);
 
-	k_thread_abort(tid);
+	k_thread_abort(tids[0]);
 }
 
 /**
@@ -442,13 +443,13 @@ ZTEST(msgq_api_1cpu, test_msgq_full)
 	ret = k_msgq_put(&msgq1, &data[0], K_NO_WAIT);
 	zassert_equal(ret, 0);
 
-	k_tid_t tid = k_thread_create(&tdata2, tstack2, STACK_SIZE,
-					put_full_entry, &msgq1, NULL,
-					NULL, pri, 0, K_NO_WAIT);
+	tids[0] = k_thread_create(&tdata2, tstack2, STACK_SIZE,
+				  put_full_entry, &msgq1, NULL,
+				  NULL, pri, 0, K_NO_WAIT);
 	k_sem_take(&end_sema, K_FOREVER);
 	/* that putting thread is being blocked now */
-	zassert_equal(tid->base.thread_state, _THREAD_PENDING);
-	k_thread_abort(tid);
+	zassert_equal(tids[0]->base.thread_state, _THREAD_PENDING);
+	k_thread_abort(tids[0]);
 }
 
 /**
diff --git a/tests/kernel/msgq/msgq_api/src/test_msgq_purge.c b/tests/kernel/msgq/msgq_api/src/test_msgq_purge.c
index 1527824e027..92ca2b9bbc9 100644
--- a/tests/kernel/msgq/msgq_api/src/test_msgq_purge.c
+++ b/tests/kernel/msgq/msgq_api/src/test_msgq_purge.c
@@ -8,6 +8,7 @@
 
 K_THREAD_STACK_DECLARE(tstack, STACK_SIZE);
 extern struct k_thread tdata;
+extern k_tid_t tids[2];
 extern struct k_msgq msgq;
 static ZTEST_BMEM char __aligned(4) tbuffer[MSG_SIZE * MSGQ_LEN];
 static ZTEST_DMEM uint32_t data[MSGQ_LEN] = { MSG0, MSG1 };
@@ -29,10 +30,10 @@ static void purge_when_put(struct k_msgq *q)
 		zassert_equal(ret, 0);
 	}
 	/*create another thread waiting to put msg*/
-	k_thread_create(&tdata, tstack, STACK_SIZE,
-			tThread_entry, q, NULL, NULL,
-			K_PRIO_PREEMPT(0), K_USER | K_INHERIT_PERMS,
-			K_NO_WAIT);
+	tids[0] = k_thread_create(&tdata, tstack, STACK_SIZE,
+				  tThread_entry, q, NULL, NULL,
+				  K_PRIO_PREEMPT(0), K_USER | K_INHERIT_PERMS,
+				  K_NO_WAIT);
 	k_msleep(TIMEOUT_MS >> 1);
 	/**TESTPOINT: msgq purge while another thread waiting to put msg*/
 	k_msgq_purge(q);
@@ -43,7 +44,7 @@ static void purge_when_put(struct k_msgq *q)
 		zassert_equal(ret, 0);
 	}
 
-	k_thread_abort(&tdata);
+	k_thread_abort(tids[0]);
 }
 
 /**
diff --git a/tests/kernel/mutex/mutex_api/src/complex_inversion.c b/tests/kernel/mutex/mutex_api/src/complex_inversion.c
new file mode 100644
index 00000000000..ae12f6c87b5
--- /dev/null
+++ b/tests/kernel/mutex/mutex_api/src/complex_inversion.c
@@ -0,0 +1,290 @@
+/*
+ * Copyright 2024 by Garmin Ltd. or its subsidiaries.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief Test complex mutex priority inversion
+ *
+ * This module demonstrates the kernel's priority inheritance algorithm
+ * with two mutexes and four threads, ensuring that boosting priority of
+ * a thread waiting on another mutex does not break assumptions of the
+ * mutex's waitq, causing the incorrect thread to run or a crash.
+ *
+ * Sequence for priority inheritance testing:
+ *  - thread_08 takes mutex_1
+ *  - thread_07 takes mutex_0 then waits on mutex_1
+ *  - thread_06 waits on mutex_1
+ *  - thread_05 waits on mutex_0, boosting priority of thread_07
+ *  - thread_08 gives mutex_1, thread_07 takes mutex_1
+ *  - thread_07 gives mutex_1, thread_06 takes mutex_1
+ *  - thread_07 gives mutex_0, thread_05 takes mutex_0
+ *  - thread_06 gives mutex_1
+ *  - thread_05 gives mutex_0
+ */
+
+#include <zephyr/tc_util.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/sys/mutex.h>
+
+#define STACKSIZE (512 + CONFIG_TEST_EXTRA_STACK_SIZE)
+
+static ZTEST_DMEM int tc_rc = TC_PASS; /* test case return code */
+
+static K_MUTEX_DEFINE(mutex_0);
+static K_MUTEX_DEFINE(mutex_1);
+
+#define PARTICIPANT_THREAD_OPTIONS (K_INHERIT_PERMS)
+
+#define DEFINE_PARTICIPANT_THREAD(id)                                                              \
+	static K_THREAD_STACK_DEFINE(thread_##id##_stack_area, STACKSIZE);                         \
+	static struct k_thread thread_##id##_thread_data;                                          \
+	static k_tid_t thread_##id##_tid;                                                          \
+	static K_SEM_DEFINE(thread_##id##_wait, 0, 1);                                             \
+	static K_SEM_DEFINE(thread_##id##_done, 0, 1);
+
+#define CREATE_PARTICIPANT_THREAD(id, pri)                                                         \
+	thread_##id##_tid = k_thread_create(&thread_##id##_thread_data, thread_##id##_stack_area,  \
+					    K_THREAD_STACK_SIZEOF(thread_##id##_stack_area),       \
+					    (k_thread_entry_t)thread_##id, &thread_##id##_wait,    \
+					    &thread_##id##_done, NULL, pri,                        \
+					    PARTICIPANT_THREAD_OPTIONS, K_FOREVER);                \
+	k_thread_name_set(thread_##id##_tid, "thread_" STRINGIFY(id));
+#define START_PARTICIPANT_THREAD(id) k_thread_start(&(thread_##id##_thread_data));
+#define JOIN_PARTICIPANT_THREAD(id)  k_thread_join(&(thread_##id##_thread_data), K_FOREVER);
+
+#define WAIT_FOR_MAIN()                                                                            \
+	k_sem_give(done);                                                                          \
+	k_sem_take(wait, K_FOREVER);
+
+#define ADVANCE_THREAD(id)                                                                         \
+	SIGNAL_THREAD(id);                                                                         \
+	WAIT_FOR_THREAD(id);
+
+#define SIGNAL_THREAD(id) k_sem_give(&thread_##id##_wait);
+
+#define WAIT_FOR_THREAD(id) zassert_ok(k_sem_take(&thread_##id##_done, K_MSEC(100)));
+
+/**
+ *
+ * thread_05 -
+ *
+ */
+
+static void thread_05(struct k_sem *wait, struct k_sem *done)
+{
+	int rv;
+
+	/*
+	 * Wait for mutex_0, boosting the priority of thread_07 so it will lock mutex_1 first.
+	 */
+
+	WAIT_FOR_MAIN();
+
+	rv = k_mutex_lock(&mutex_0, K_FOREVER);
+	if (rv != 0) {
+		tc_rc = TC_FAIL;
+		TC_ERROR("Failed to take mutex %p\n", &mutex_0);
+		return;
+	}
+
+	WAIT_FOR_MAIN();
+
+	k_mutex_unlock(&mutex_0);
+}
+
+/**
+ *
+ * thread_06 -
+ *
+ */
+
+static void thread_06(struct k_sem *wait, struct k_sem *done)
+{
+	int rv;
+
+	/*
+	 * Wait for mutex_1. Initially it will be the highest priority waiter, but
+	 * thread_07 will be boosted above thread_06 so thread_07 will lock it first.
+	 */
+
+	WAIT_FOR_MAIN();
+
+	rv = k_mutex_lock(&mutex_1, K_FOREVER);
+	if (rv != 0) {
+		tc_rc = TC_FAIL;
+		TC_ERROR("Failed to take mutex %p\n", &mutex_1);
+		return;
+	}
+
+	WAIT_FOR_MAIN();
+
+	k_mutex_unlock(&mutex_1);
+}
+
+/**
+ *
+ * thread_07 -
+ *
+ */
+
+static void thread_07(struct k_sem *wait, struct k_sem *done)
+{
+	int rv;
+
+	/*
+	 * Lock mutex_0 and wait for mutex_1. After thread_06 is also waiting for
+	 * mutex_1, thread_05 will wait for mutex_0, boosting the priority for
+	 * thread_07 so it should lock mutex_1 first when it is unlocked by thread_08.
+	 */
+
+	WAIT_FOR_MAIN();
+
+	rv = k_mutex_lock(&mutex_0, K_NO_WAIT);
+	if (rv != 0) {
+		tc_rc = TC_FAIL;
+		TC_ERROR("Failed to take mutex %p\n", &mutex_0);
+		return;
+	}
+
+	WAIT_FOR_MAIN();
+
+	rv = k_mutex_lock(&mutex_1, K_FOREVER);
+	if (rv != 0) {
+		tc_rc = TC_FAIL;
+		TC_ERROR("Failed to take mutex %p\n", &mutex_1);
+		k_mutex_unlock(&mutex_0);
+		return;
+	}
+
+	WAIT_FOR_MAIN();
+
+	k_mutex_unlock(&mutex_1);
+	k_mutex_unlock(&mutex_0);
+}
+
+/**
+ *
+ * thread_08 -
+ *
+ */
+
+static void thread_08(struct k_sem *wait, struct k_sem *done)
+{
+	int rv;
+
+	/*
+	 * Lock mutex_1 and hold until priority has been boosted on thread_07
+	 * to ensure that thread_07 is the first to lock mutex_1 when thread_08
+	 * unlocks it.
+	 */
+
+	WAIT_FOR_MAIN();
+
+	rv = k_mutex_lock(&mutex_1, K_NO_WAIT);
+	if (rv != 0) {
+		tc_rc = TC_FAIL;
+		TC_ERROR("Failed to take mutex %p\n", &mutex_1);
+		return;
+	}
+
+	WAIT_FOR_MAIN();
+
+	k_mutex_unlock(&mutex_1);
+}
+
+DEFINE_PARTICIPANT_THREAD(05);
+DEFINE_PARTICIPANT_THREAD(06);
+DEFINE_PARTICIPANT_THREAD(07);
+DEFINE_PARTICIPANT_THREAD(08);
+
+static void create_participant_threads(void)
+{
+	CREATE_PARTICIPANT_THREAD(05, 5);
+	CREATE_PARTICIPANT_THREAD(06, 6);
+	CREATE_PARTICIPANT_THREAD(07, 7);
+	CREATE_PARTICIPANT_THREAD(08, 8);
+}
+
+static void start_participant_threads(void)
+{
+	START_PARTICIPANT_THREAD(05);
+	START_PARTICIPANT_THREAD(06);
+	START_PARTICIPANT_THREAD(07);
+	START_PARTICIPANT_THREAD(08);
+}
+
+static void join_participant_threads(void)
+{
+	JOIN_PARTICIPANT_THREAD(05);
+	JOIN_PARTICIPANT_THREAD(06);
+	JOIN_PARTICIPANT_THREAD(07);
+	JOIN_PARTICIPANT_THREAD(08);
+}
+
+/**
+ *
+ * @brief Main thread to test mutex locking
+ *
+ * This thread orchestrates mutex locking on other threads and verifies that
+ * the correct thread is holding mutexes at any given step.
+ *
+ */
+
+ZTEST(mutex_api, test_complex_inversion)
+{
+	create_participant_threads();
+	start_participant_threads();
+
+	/* Wait for all the threads to start up */
+	WAIT_FOR_THREAD(08);
+	WAIT_FOR_THREAD(07);
+	WAIT_FOR_THREAD(06);
+	WAIT_FOR_THREAD(05);
+
+	ADVANCE_THREAD(08); /* thread_08 takes mutex_1 */
+	zassert_equal(thread_08_tid, mutex_1.owner, "expected owner %s, not %s\n",
+		      thread_08_tid->name, mutex_1.owner->name);
+
+	ADVANCE_THREAD(07); /* thread_07 takes mutex_0 */
+	zassert_equal(thread_07_tid, mutex_0.owner, "expected owner %s, not %s\n",
+		      thread_07_tid->name, mutex_0.owner->name);
+
+	SIGNAL_THREAD(07);    /* thread_07 waits on mutex_1 */
+	k_sleep(K_MSEC(100)); /* Give thread_07 some time to wait on mutex_1 */
+
+	SIGNAL_THREAD(06);    /* thread_06 waits on mutex_1 */
+	k_sleep(K_MSEC(100)); /* Give thread_06 some time to wait on mutex_1 */
+
+	SIGNAL_THREAD(05); /* thread_05 waits on mutex_0, boosting priority of thread_07 */
+
+	SIGNAL_THREAD(08); /* thread_08 gives mutex_1 */
+
+	/* If thread_06 erroneously took mutex_1, giving it could cause a crash
+	 * when CONFIG_WAITQ_SCALABLE is set. Give it a chance to run to make sure
+	 * this crash isn't hit.
+	 */
+	SIGNAL_THREAD(06);
+
+	WAIT_FOR_THREAD(07); /* thread_07 takes mutex_1 */
+	zassert_equal(thread_07_tid, mutex_1.owner, "expected owner %s, not %s\n",
+		      thread_07_tid->name, mutex_1.owner->name);
+
+	SIGNAL_THREAD(07);   /* thread_07 gives mutex_1 then gives mutex_0 */
+	WAIT_FOR_THREAD(06); /* thread_06 takes mutex_1 */
+	WAIT_FOR_THREAD(05); /* thread_05 takes mutex_0 */
+	zassert_equal(thread_06_tid, mutex_1.owner, "expected owner %s, not %s\n",
+		      thread_06_tid->name, mutex_1.owner->name);
+	zassert_equal(thread_05_tid, mutex_0.owner, "expected owner %s, not %s\n",
+		      thread_05_tid->name, mutex_0.owner->name);
+
+	SIGNAL_THREAD(06); /* thread_06 gives mutex_1 */
+	SIGNAL_THREAD(05); /* thread_05 gives mutex_0 */
+
+	zassert_equal(tc_rc, TC_PASS);
+
+	join_participant_threads();
+}
diff --git a/tests/kernel/mutex/mutex_api/testcase.yaml b/tests/kernel/mutex/mutex_api/testcase.yaml
index a623ec4df06..76bf3ec4bb3 100644
--- a/tests/kernel/mutex/mutex_api/testcase.yaml
+++ b/tests/kernel/mutex/mutex_api/testcase.yaml
@@ -3,3 +3,9 @@ tests:
     tags:
       - kernel
       - userspace
+
+  kernel.mutex.scalable:
+    tags:
+      - kernel
+    extra_configs:
+      - CONFIG_WAITQ_SCALABLE=y
diff --git a/tests/kernel/mutex/mutex_error_case/prj.conf b/tests/kernel/mutex/mutex_error_case/prj.conf
index d144e826538..3fc9377dc69 100644
--- a/tests/kernel/mutex/mutex_error_case/prj.conf
+++ b/tests/kernel/mutex/mutex_error_case/prj.conf
@@ -3,4 +3,3 @@ CONFIG_IRQ_OFFLOAD=y
 CONFIG_TEST_USERSPACE=y
 CONFIG_MP_MAX_NUM_CPUS=1
 CONFIG_ZTEST_FATAL_HOOK=y
-CONFIG_PIPES=y
diff --git a/tests/kernel/obj_core/obj_core/prj.conf b/tests/kernel/obj_core/obj_core/prj.conf
index 6c006bcb8e9..95b1c1624c4 100644
--- a/tests/kernel/obj_core/obj_core/prj.conf
+++ b/tests/kernel/obj_core/obj_core/prj.conf
@@ -1,5 +1,4 @@
 CONFIG_ZTEST=y
 CONFIG_OBJ_CORE=y
 CONFIG_EVENTS=y
-CONFIG_PIPES=y
 CONFIG_SYS_MEM_BLOCKS=y
diff --git a/tests/kernel/obj_core/obj_core_stats_api/prj.conf b/tests/kernel/obj_core/obj_core_stats_api/prj.conf
index d163a31e105..1012c240aeb 100644
--- a/tests/kernel/obj_core/obj_core_stats_api/prj.conf
+++ b/tests/kernel/obj_core/obj_core_stats_api/prj.conf
@@ -1,6 +1,5 @@
 CONFIG_ZTEST=y
 CONFIG_OBJ_CORE=y
 CONFIG_OBJ_CORE_STATS=y
-CONFIG_PIPES=y
 CONFIG_SCHED_THREAD_USAGE=y
 CONFIG_SCHED_THREAD_USAGE_ANALYSIS=y
diff --git a/tests/kernel/obj_tracking/prj.conf b/tests/kernel/obj_tracking/prj.conf
index 38956d67953..04860b00cd2 100644
--- a/tests/kernel/obj_tracking/prj.conf
+++ b/tests/kernel/obj_tracking/prj.conf
@@ -3,5 +3,4 @@ CONFIG_IRQ_OFFLOAD=y
 CONFIG_TRACING=y
 CONFIG_TRACING_OBJECT_TRACKING=y
 CONFIG_TRACING_NONE=y
-CONFIG_PIPES=y
 CONFIG_EVENTS=y
diff --git a/tests/kernel/pending/testcase.yaml b/tests/kernel/pending/testcase.yaml
index b3e66a57ce8..20a5dde8fc3 100644
--- a/tests/kernel/pending/testcase.yaml
+++ b/tests/kernel/pending/testcase.yaml
@@ -1,7 +1,7 @@
 tests:
-  kernel.objects:
+  kernel.pending:
     tags: kernel
-  kernel.objects.minimallibc:
+  kernel.pending.minimallibc:
     filter: CONFIG_MINIMAL_LIBC_SUPPORTED
     tags:
       - kernel
diff --git a/tests/kernel/pipe/deprecated/pipe/CMakeLists.txt b/tests/kernel/pipe/deprecated/pipe/CMakeLists.txt
new file mode 100644
index 00000000000..2624f4be400
--- /dev/null
+++ b/tests/kernel/pipe/deprecated/pipe/CMakeLists.txt
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+set(CMAKE_C_FLAGS "-D__deprecated=\"/* deprecated */\" -D__DEPRECATED_MACRO=\"/* deprecated_macro*/\"")
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(pipe)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/kernel/pipe/pipe/prj.conf b/tests/kernel/pipe/deprecated/pipe/prj.conf
similarity index 100%
rename from tests/kernel/pipe/pipe/prj.conf
rename to tests/kernel/pipe/deprecated/pipe/prj.conf
diff --git a/tests/kernel/pipe/pipe/src/main.c b/tests/kernel/pipe/deprecated/pipe/src/main.c
similarity index 100%
rename from tests/kernel/pipe/pipe/src/main.c
rename to tests/kernel/pipe/deprecated/pipe/src/main.c
diff --git a/tests/kernel/pipe/pipe/src/test_pipe.c b/tests/kernel/pipe/deprecated/pipe/src/test_pipe.c
similarity index 100%
rename from tests/kernel/pipe/pipe/src/test_pipe.c
rename to tests/kernel/pipe/deprecated/pipe/src/test_pipe.c
diff --git a/tests/kernel/pipe/deprecated/pipe/testcase.yaml b/tests/kernel/pipe/deprecated/pipe/testcase.yaml
new file mode 100644
index 00000000000..76658b6757d
--- /dev/null
+++ b/tests/kernel/pipe/deprecated/pipe/testcase.yaml
@@ -0,0 +1,6 @@
+tests:
+  kernel.deprecated.pipe:
+    tags:
+      - kernel
+      - userspace
+    ignore_faults: true
diff --git a/tests/kernel/pipe/deprecated/pipe_api/CMakeLists.txt b/tests/kernel/pipe/deprecated/pipe_api/CMakeLists.txt
new file mode 100644
index 00000000000..44f65534e3f
--- /dev/null
+++ b/tests/kernel/pipe/deprecated/pipe_api/CMakeLists.txt
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+set(CMAKE_C_FLAGS "-D__deprecated=\"/* deprecated */\" -D__DEPRECATED_MACRO=\"/* deprecated_macro*/\"")
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(pipe_api)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/kernel/pipe/deprecated/pipe_api/prj.conf b/tests/kernel/pipe/deprecated/pipe_api/prj.conf
new file mode 100644
index 00000000000..040b166563f
--- /dev/null
+++ b/tests/kernel/pipe/deprecated/pipe_api/prj.conf
@@ -0,0 +1,8 @@
+CONFIG_ZTEST=y
+CONFIG_IRQ_OFFLOAD=y
+CONFIG_TEST_USERSPACE=y
+CONFIG_DYNAMIC_OBJECTS=y
+CONFIG_MP_MAX_NUM_CPUS=1
+CONFIG_ZTEST_FATAL_HOOK=y
+CONFIG_PIPES=y
+CONFIG_MINIMAL_LIBC=y
diff --git a/tests/kernel/pipe/pipe_api/src/main.c b/tests/kernel/pipe/deprecated/pipe_api/src/main.c
similarity index 100%
rename from tests/kernel/pipe/pipe_api/src/main.c
rename to tests/kernel/pipe/deprecated/pipe_api/src/main.c
diff --git a/tests/kernel/pipe/pipe_api/src/test_pipe_avail.c b/tests/kernel/pipe/deprecated/pipe_api/src/test_pipe_avail.c
similarity index 100%
rename from tests/kernel/pipe/pipe_api/src/test_pipe_avail.c
rename to tests/kernel/pipe/deprecated/pipe_api/src/test_pipe_avail.c
diff --git a/tests/kernel/pipe/pipe_api/src/test_pipe_contexts.c b/tests/kernel/pipe/deprecated/pipe_api/src/test_pipe_contexts.c
similarity index 100%
rename from tests/kernel/pipe/pipe_api/src/test_pipe_contexts.c
rename to tests/kernel/pipe/deprecated/pipe_api/src/test_pipe_contexts.c
diff --git a/tests/kernel/pipe/pipe_api/src/test_pipe_fail.c b/tests/kernel/pipe/deprecated/pipe_api/src/test_pipe_fail.c
similarity index 100%
rename from tests/kernel/pipe/pipe_api/src/test_pipe_fail.c
rename to tests/kernel/pipe/deprecated/pipe_api/src/test_pipe_fail.c
diff --git a/tests/kernel/pipe/deprecated/pipe_api/testcase.yaml b/tests/kernel/pipe/deprecated/pipe_api/testcase.yaml
new file mode 100644
index 00000000000..1564321cb73
--- /dev/null
+++ b/tests/kernel/pipe/deprecated/pipe_api/testcase.yaml
@@ -0,0 +1,5 @@
+tests:
+  kernel.deprecated.pipe.api:
+    tags:
+      - kernel
+      - userspace
diff --git a/tests/kernel/pipe/pipe/CMakeLists.txt b/tests/kernel/pipe/pipe/CMakeLists.txt
deleted file mode 100644
index ac8bc4dee46..00000000000
--- a/tests/kernel/pipe/pipe/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-cmake_minimum_required(VERSION 3.20.0)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(pipe)
-
-FILE(GLOB app_sources src/*.c)
-target_sources(app PRIVATE ${app_sources})
diff --git a/tests/kernel/pipe/pipe/testcase.yaml b/tests/kernel/pipe/pipe/testcase.yaml
deleted file mode 100644
index 9d3382e4487..00000000000
--- a/tests/kernel/pipe/pipe/testcase.yaml
+++ /dev/null
@@ -1,6 +0,0 @@
-tests:
-  kernel.pipe:
-    tags:
-      - kernel
-      - userspace
-    ignore_faults: true
diff --git a/tests/kernel/pipe/pipe_api/CMakeLists.txt b/tests/kernel/pipe/pipe_api/CMakeLists.txt
index fbaf5f15e11..7f0e871daba 100644
--- a/tests/kernel/pipe/pipe_api/CMakeLists.txt
+++ b/tests/kernel/pipe/pipe_api/CMakeLists.txt
@@ -1,8 +1,12 @@
-# SPDX-License-Identifier: Apache-2.0
+cmake_minimum_required(VERSION 3.13.1)
 
-cmake_minimum_required(VERSION 3.20.0)
 find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(pipe_api)
 
-FILE(GLOB app_sources src/*.c)
-target_sources(app PRIVATE ${app_sources})
+project(app)
+
+target_sources(app
+  PRIVATE
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/basic.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/stress.c
+  ${CMAKE_CURRENT_SOURCE_DIR}/src/concurrency.c
+)
diff --git a/tests/kernel/pipe/pipe_api/prj.conf b/tests/kernel/pipe/pipe_api/prj.conf
index d080e2fbdbd..238fe5eacc5 100644
--- a/tests/kernel/pipe/pipe_api/prj.conf
+++ b/tests/kernel/pipe/pipe_api/prj.conf
@@ -1,7 +1,9 @@
 CONFIG_ZTEST=y
-CONFIG_IRQ_OFFLOAD=y
-CONFIG_TEST_USERSPACE=y
-CONFIG_DYNAMIC_OBJECTS=y
-CONFIG_MP_MAX_NUM_CPUS=1
-CONFIG_ZTEST_FATAL_HOOK=y
-CONFIG_PIPES=y
+CONFIG_ZTRESS=y
+
+CONFIG_ZTEST_STACK_SIZE=4096
+CONFIG_HEAP_MEM_POOL_SIZE=2048
+CONFIG_MAIN_STACK_SIZE=4096
+
+CONFIG_ENTROPY_GENERATOR=y
+CONFIG_TEST_RANDOM_GENERATOR=y
diff --git a/tests/kernel/pipe/pipe_api/src/basic.c b/tests/kernel/pipe/pipe_api/src/basic.c
new file mode 100644
index 00000000000..baaf5a48b93
--- /dev/null
+++ b/tests/kernel/pipe/pipe_api/src/basic.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2024 Måns Ansgariusson <mansgariusson@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdint.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/random/random.h>
+
+ZTEST_SUITE(k_pipe_basic, NULL, NULL, NULL, NULL, NULL);
+
+static void mkrandom(uint8_t *buffer, size_t size)
+{
+	sys_rand_get(buffer, size);
+}
+
+K_PIPE_DEFINE(test_define, 256, 4);
+
+static struct k_pipe pipe;
+
+ZTEST(k_pipe_basic, test_init)
+{
+	uint8_t buffer[10];
+
+	k_pipe_init(&pipe, buffer, sizeof(buffer));
+	zassert_true(pipe.flags == PIPE_FLAG_OPEN, "Unexpected pipe flags");
+}
+
+ZTEST(k_pipe_basic, test_write_read_one)
+{
+	uint8_t buffer[10];
+	uint8_t data = 0x55;
+	uint8_t read_data;
+
+	k_pipe_init(&pipe, buffer, sizeof(buffer));
+	zassert_true(k_pipe_write(&pipe, &data, 1, K_NO_WAIT) == 1,
+	      "Failed to write to pipe");
+	zassert_true(k_pipe_read(&pipe, &read_data, 1, K_NO_WAIT) == 1,
+	      "Failed to read from pipe");
+	zassert_true(read_data == data, "Unexpected data received from pipe");
+}
+
+ZTEST(k_pipe_basic, test_write_read_multiple)
+{
+	uint8_t buffer[10];
+	uint8_t data = 0x55;
+	uint8_t read_data;
+
+	k_pipe_init(&pipe, buffer, sizeof(buffer));
+	zassert_true(k_pipe_write(&pipe, &data, 1, K_NO_WAIT) == 1, "Failed to write to pipe");
+	zassert_true(k_pipe_write(&pipe, &data, 1, K_NO_WAIT) == 1, "Failed to write to pipe");
+	zassert_true(k_pipe_read(&pipe, &read_data, 1, K_NO_WAIT) == 1, "Failed to read from pipe");
+	zassert_true(read_data == data, "Unexpected data received from pipe");
+	zassert_true(k_pipe_read(&pipe, &read_data, 1, K_NO_WAIT) == 1, "Failed to read from pipe");
+	zassert_true(read_data == data, "Unexpected data received from pipe");
+}
+
+ZTEST(k_pipe_basic, test_write_full)
+{
+	uint8_t buffer[10];
+	uint8_t data[10];
+
+	k_pipe_init(&pipe, buffer, sizeof(buffer));
+	zassert_true(k_pipe_write(&pipe, data, sizeof(data), K_NO_WAIT) == 10,
+		"Failed to write multiple bytes to pipe");
+	zassert_true(k_pipe_write(&pipe, data, sizeof(data), K_MSEC(1000)) == -EAGAIN,
+		"Should not be able to write to full pipe");
+}
+
+ZTEST(k_pipe_basic, test_read_empty)
+{
+	uint8_t buffer[10];
+	uint8_t read_data;
+
+	k_pipe_init(&pipe, buffer, sizeof(buffer));
+	zassert_true(k_pipe_read(&pipe, &read_data, 1, K_MSEC(1000)) == -EAGAIN,
+		"Should not be able to read from empty pipe");
+}
+
+ZTEST(k_pipe_basic, test_read_write_full)
+{
+	uint8_t buffer[10];
+	uint8_t input[10];
+	uint8_t res[10];
+
+	mkrandom(input, sizeof(input));
+	k_pipe_init(&pipe, buffer, sizeof(buffer));
+	zassert_true(k_pipe_write(&pipe, input, sizeof(input), K_NO_WAIT) == sizeof(input),
+		"Failed to write multiple bytes to pipe");
+	zassert_true(k_pipe_read(&pipe, res, sizeof(res), K_NO_WAIT) == sizeof(res),
+		"Failed to read multiple bytes from pipe");
+	zassert_true(memcmp(input, res, sizeof(input)) == 0,
+		"Unexpected data received from pipe");
+}
+
+ZTEST(k_pipe_basic, test_read_write_wrapp_around)
+{
+	uint8_t buffer[12];
+	uint8_t input[8];
+	uint8_t res[16];
+
+	mkrandom(input, sizeof(input));
+	k_pipe_init(&pipe, buffer, sizeof(buffer));
+	zassert_true(k_pipe_write(&pipe, input, sizeof(input), K_NO_WAIT) == sizeof(input),
+		"Failed to write bytes to pipe");
+	zassert_true(k_pipe_read(&pipe, res, 5, K_NO_WAIT) == 5,
+		"Failed to read bytes from pipe");
+	zassert_true(memcmp(input, res, 5) == 0, "Unexpected data received from pipe");
+
+	zassert_true(k_pipe_write(&pipe, input, sizeof(input), K_NO_WAIT) == sizeof(input),
+		"Failed to write bytes to pipe");
+	zassert_true(k_pipe_read(&pipe, res, sizeof(input) * 2 - 5, K_NO_WAIT) ==
+		sizeof(input) * 2 - 5, "Failed to read remaining bytes from pipe");
+
+	zassert_true(memcmp(&input[5], res, sizeof(input) - 5) == 0,
+		"Unexpected data received from pipe");
+	zassert_true(memcmp(input, &res[sizeof(input) - 5], sizeof(input)) == 0,
+		"Unexpected data received from pipe");
+}
+
+ZTEST(k_pipe_basic, test_reset)
+{
+	uint8_t buffer[10];
+	uint8_t data = 0x55;
+	uint8_t read_data;
+
+	k_pipe_init(&pipe, buffer, sizeof(buffer));
+
+	/* reset an empty pipe, & no waiting should not produce any side-effects*/
+	k_pipe_reset(&pipe);
+	zassert_true(k_pipe_write(&pipe, &data, 1, K_NO_WAIT) == 1,
+		"Failed to write to resetted pipe");
+	zassert_true(k_pipe_read(&pipe, &read_data, 1, K_NO_WAIT) == 1,
+		"Failed to read from resetted pipe");
+	zassert_true(read_data == data, "Unexpected data received from pipe");
+}
+
+ZTEST(k_pipe_basic, test_close)
+{
+	uint8_t buffer[12];
+	uint8_t input[8];
+	uint8_t res[16];
+
+	mkrandom(input, sizeof(input));
+	k_pipe_init(&pipe, buffer, sizeof(buffer));
+	zassert_true(k_pipe_write(&pipe, input, sizeof(input), K_NO_WAIT) == sizeof(input),
+		"Failed to write bytes to pipe");
+	k_pipe_close(&pipe);
+
+	zassert_true(k_pipe_write(&pipe, input, sizeof(input), K_NO_WAIT) == -EPIPE,
+		"should not be able to write to closed pipe");
+	zassert_true(k_pipe_read(&pipe, res, 5, K_NO_WAIT) == 5,
+		"You should be able to read from closed pipe");
+	zassert_true(memcmp(input, res, 5) == 0, "Sequence should be equal");
+
+	zassert_true(k_pipe_read(&pipe, res, 5, K_NO_WAIT) == 3,
+		"you should be able to read remaining bytes from closed pipe");
+	zassert_true(memcmp(&input[5], res, 3) == 0, "Written and read bytes should be equal");
+	zassert_true(k_pipe_read(&pipe, res, 5, K_NO_WAIT) == -EPIPE,
+		"Closed and empty pipe should return -EPIPE");
+}
diff --git a/tests/kernel/pipe/pipe_api/src/concurrency.c b/tests/kernel/pipe/pipe_api/src/concurrency.c
new file mode 100644
index 00000000000..601a4bdd5d7
--- /dev/null
+++ b/tests/kernel/pipe/pipe_api/src/concurrency.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2024 Måns Ansgariusson <mansgariusson@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdint.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztest.h>
+#include <zephyr/random/random.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(k_pipe_concurrency, LOG_LEVEL_DBG);
+ZTEST_SUITE(k_pipe_concurrency, NULL, NULL, NULL, NULL, NULL);
+
+static const int partial_wait_time = 2000;
+#define DUMMY_DATA_SIZE 16
+static struct k_thread thread;
+static K_THREAD_STACK_DEFINE(stack, 1024);
+static struct k_pipe pipe;
+
+static void thread_close(void *arg1, void *arg2, void *arg3)
+{
+	k_pipe_close((struct k_pipe *)arg1);
+}
+
+static void thread_reset(void *arg1, void *arg2, void *arg3)
+{
+	k_pipe_reset((struct k_pipe *)arg1);
+}
+
+static void thread_write(void *arg1, void *arg2, void *arg3)
+{
+	uint8_t garbage[DUMMY_DATA_SIZE] = {};
+
+	zassert_true(k_pipe_write((struct k_pipe *)arg1, garbage, sizeof(garbage),
+		K_MSEC(partial_wait_time)) == sizeof(garbage), "Failed to write to pipe");
+}
+
+static void thread_read(void *arg1, void *arg2, void *arg3)
+{
+	uint8_t garbage[DUMMY_DATA_SIZE];
+
+	zassert_true(k_pipe_read((struct k_pipe *)arg1, garbage, sizeof(garbage),
+		K_MSEC(partial_wait_time)) == sizeof(garbage), "Failed to read from pipe");
+}
+
+ZTEST(k_pipe_concurrency, test_close_on_read)
+{
+	k_tid_t tid;
+	uint8_t buffer[DUMMY_DATA_SIZE];
+	uint8_t res;
+
+	k_pipe_init(&pipe, buffer, sizeof(buffer));
+	tid = k_thread_create(&thread, stack, K_THREAD_STACK_SIZEOF(stack),
+		thread_close, &pipe, NULL, NULL, K_PRIO_COOP(0), 0, K_MSEC(100));
+	zassert_true(tid, "k_thread_create failed");
+	zassert_true(k_pipe_read(&pipe, &res, sizeof(res), K_MSEC(1000)) == -EPIPE,
+		"Read on closed pipe should return -EPIPE");
+	k_thread_join(tid, K_FOREVER);
+	zassert_true((pipe.flags & PIPE_FLAG_OPEN) == 0,
+		"Pipe should continue to be closed after all waiters have been released");
+}
+
+ZTEST(k_pipe_concurrency, test_close_on_write)
+{
+	k_tid_t tid;
+	uint8_t buffer[DUMMY_DATA_SIZE];
+	uint8_t garbage[DUMMY_DATA_SIZE];
+
+	k_pipe_init(&pipe, buffer, sizeof(buffer));
+	zassert_true(sizeof(garbage) == k_pipe_write(&pipe, garbage, sizeof(garbage), K_MSEC(1000)),
+		"Failed to write to pipe");
+
+	tid = k_thread_create(&thread, stack, K_THREAD_STACK_SIZEOF(stack),
+		thread_close, &pipe, NULL, NULL, K_PRIO_COOP(0), 0, K_MSEC(100));
+	zassert_true(tid, "k_thread_create failed");
+	zassert_true(k_pipe_write(&pipe, garbage, sizeof(garbage), K_MSEC(1000)) == -EPIPE,
+		"write should return -EPIPE, when pipe is closed");
+	k_thread_join(tid, K_FOREVER);
+	zassert_true((pipe.flags & PIPE_FLAG_OPEN) == 0,
+		"pipe should continue to be closed after all waiters have been released");
+}
+
+ZTEST(k_pipe_concurrency, test_reset_on_read)
+{
+	k_tid_t tid;
+	uint8_t buffer[DUMMY_DATA_SIZE];
+	uint8_t res;
+
+	k_pipe_init(&pipe, buffer, sizeof(buffer));
+
+	tid = k_thread_create(&thread, stack, K_THREAD_STACK_SIZEOF(stack),
+		thread_reset, &pipe, NULL, NULL, K_PRIO_COOP(0), 0, K_MSEC(100));
+	zassert_true(tid, "k_thread_create failed");
+	zassert_true(k_pipe_read(&pipe, &res, sizeof(res), K_MSEC(1000)) == -ECANCELED,
+		"reset on read should return -ECANCELED");
+	k_thread_join(tid, K_FOREVER);
+	zassert_true((pipe.flags & PIPE_FLAG_RESET) == 0,
+		"pipe should not have reset flag after all waiters are done");
+	zassert_true((pipe.flags & PIPE_FLAG_OPEN) != 0,
+		"pipe should continue to be open after pipe is reseted");
+}
+
+ZTEST(k_pipe_concurrency, test_reset_on_write)
+{
+	k_tid_t tid;
+	uint8_t buffer[DUMMY_DATA_SIZE];
+	uint8_t garbage[DUMMY_DATA_SIZE];
+
+	k_pipe_init(&pipe, buffer, sizeof(buffer));
+	zassert_true(sizeof(garbage) == k_pipe_write(&pipe, garbage, sizeof(garbage), K_MSEC(1000)),
+		"Failed to write to pipe");
+
+	tid = k_thread_create(&thread, stack, K_THREAD_STACK_SIZEOF(stack),
+		thread_reset, &pipe, NULL, NULL, K_PRIO_COOP(0), 0, K_MSEC(100));
+	zassert_true(tid, "k_thread_create failed");
+	zassert_true(k_pipe_write(&pipe, garbage, sizeof(garbage), K_MSEC(1000)) == -ECANCELED,
+		"reset on write should return -ECANCELED");
+	k_thread_join(tid, K_FOREVER);
+	zassert_true((pipe.flags & PIPE_FLAG_RESET) == 0,
+		"pipe should not have reset flag after all waiters are done");
+	zassert_true((pipe.flags & PIPE_FLAG_OPEN) != 0,
+		"pipe should continue to be open after pipe is reseted");
+}
+
+ZTEST(k_pipe_concurrency, test_partial_read)
+{
+	k_tid_t tid;
+	uint8_t buffer[DUMMY_DATA_SIZE];
+	uint8_t garbage[DUMMY_DATA_SIZE];
+	size_t write_size = sizeof(garbage)/2;
+
+	k_pipe_init(&pipe, buffer, sizeof(buffer));
+	tid = k_thread_create(&thread, stack, K_THREAD_STACK_SIZEOF(stack),
+		thread_read, &pipe, NULL, NULL, K_PRIO_COOP(0), 0, K_NO_WAIT);
+
+	zassert_true(k_pipe_write(&pipe, garbage, write_size, K_NO_WAIT) == write_size,
+		"write to pipe failed");
+	k_msleep(partial_wait_time/4);
+	zassert_true(k_pipe_write(&pipe, garbage, write_size, K_NO_WAIT) == write_size,
+		"k_k_pipe_write should return number of bytes written");
+	k_thread_join(tid, K_FOREVER);
+}
+
+ZTEST(k_pipe_concurrency, test_partial_write)
+{
+	k_tid_t tid;
+	uint8_t buffer[DUMMY_DATA_SIZE];
+	uint8_t garbage[DUMMY_DATA_SIZE];
+	size_t read_size = sizeof(garbage)/2;
+
+	k_pipe_init(&pipe, buffer, sizeof(buffer));
+
+	zassert_true(k_pipe_write(&pipe, garbage, sizeof(garbage), K_NO_WAIT) == sizeof(garbage),
+		"Failed to write to pipe");
+	tid = k_thread_create(&thread, stack, K_THREAD_STACK_SIZEOF(stack),
+		thread_write, &pipe, NULL, NULL, K_PRIO_COOP(0), 0, K_NO_WAIT);
+
+	zassert_true(k_pipe_read(&pipe, garbage, read_size, K_NO_WAIT) == read_size,
+		"Failed to read from pipe");
+	k_msleep(partial_wait_time/2);
+	zassert_true(k_pipe_read(&pipe, garbage, read_size, K_NO_WAIT) == read_size,
+		"failed t read from pipe");
+	k_thread_join(tid, K_FOREVER);
+}
diff --git a/tests/kernel/pipe/pipe_api/src/stress.c b/tests/kernel/pipe/pipe_api/src/stress.c
new file mode 100644
index 00000000000..907458276b3
--- /dev/null
+++ b/tests/kernel/pipe/pipe_api/src/stress.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2024 Måns Ansgariusson <mansgariusson@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <stdint.h>
+#include <zephyr/ztest.h>
+#include <zephyr/kernel.h>
+#include <zephyr/ztress.h>
+#include <zephyr/logging/log.h>
+#include <zephyr/random/random.h>
+#include <zephyr/timing/timing.h>
+
+#define WRITE_LEN 512
+#define READ_LEN  512
+
+LOG_MODULE_REGISTER(k_k_pipe_stress, LOG_LEVEL_INF);
+
+ZTEST_SUITE(k_pipe_stress, NULL, NULL, NULL, NULL, NULL);
+
+static struct k_pipe pipe;
+
+ZTEST(k_pipe_stress, test_write)
+{
+	int rc;
+	const size_t len = WRITE_LEN;
+	uint8_t buffer[WRITE_LEN];
+	uint8_t buf[WRITE_LEN];
+	size_t sent;
+	uint32_t start_cycles, end_cycles;
+
+	k_pipe_init(&pipe, buffer, sizeof(buffer));
+	start_cycles = k_uptime_get_32();
+	sent = 0;
+	while (sent < len) {
+		rc = k_pipe_write(&pipe, &buf[sent], len - sent, K_FOREVER);
+		zassert_true(rc > 0, "Failed to write to pipe");
+		sent += rc;
+	}
+	end_cycles = k_uptime_get_32();
+	LOG_INF("Elapsed cycles: %u\n", end_cycles - start_cycles);
+}
+
+ZTEST(k_pipe_stress, test_read)
+{
+	int rc;
+	const size_t len = READ_LEN;
+	uint8_t buffer[READ_LEN];
+	uint8_t buf[READ_LEN];
+	size_t sent, read;
+	uint32_t start_cycles, end_cycles;
+
+	k_pipe_init(&pipe, buffer, sizeof(buffer));
+	start_cycles = k_uptime_get_32();
+	for (int i = 0; i < 100; i++) {
+		sent = 0;
+		while (sent < len) {
+			rc = k_pipe_write(&pipe, &buf[sent], len - sent, K_FOREVER);
+			zassert_true(rc > 0, "Failed to write to pipe");
+			sent += rc;
+		}
+		read = 0;
+		while (read < len) {
+			rc = k_pipe_read(&pipe, &buf[read], len - read, K_FOREVER);
+			zassert_true(rc > 0, "Failed to read from pipe");
+			read += rc;
+		}
+	}
+	end_cycles = k_uptime_get_32();
+	LOG_INF("Elapsed cycles: %u\n", end_cycles - start_cycles);
+}
diff --git a/tests/kernel/poll/src/test_poll.c b/tests/kernel/poll/src/test_poll.c
index ac2131fcbf9..dc910d76e9f 100644
--- a/tests/kernel/poll/src/test_poll.c
+++ b/tests/kernel/poll/src/test_poll.c
@@ -18,12 +18,14 @@ struct fifo_msg {
 #define MSGQ_MSG_SIZE 4
 #define MSGQ_MAX_MSGS 16
 #define MSGQ_MSG_VALUE {'a', 'b', 'c', 'd'}
+#define PIPE_DATA "atad_epip"
 #define STACK_SIZE (1024 + CONFIG_TEST_EXTRA_STACK_SIZE)
 
 /* verify k_poll() without waiting */
 static struct k_sem no_wait_sem;
 static struct k_fifo no_wait_fifo;
 static struct k_poll_signal no_wait_signal;
+K_PIPE_DEFINE(no_wait_pipe, 32, 1);
 static struct k_poll_signal test_signal;
 #ifndef CONFIG_USERSPACE
 static struct k_msgq no_wait_msgq;
@@ -63,6 +65,7 @@ ZTEST_USER(poll_api_1cpu, test_poll_no_wait)
 	unsigned int signaled;
 	char msgq_recv_buf[MSGQ_MSG_SIZE] = {0};
 	char msgq_msg[MSGQ_MSG_SIZE] = MSGQ_MSG_VALUE;
+	char pipe_recv_buf[sizeof(PIPE_DATA) + 4];
 	int result;
 	struct k_msgq *mq;
 #ifdef CONFIG_USERSPACE
@@ -78,6 +81,8 @@ ZTEST_USER(poll_api_1cpu, test_poll_no_wait)
 
 	k_msgq_alloc_init(mq, MSGQ_MSG_SIZE, MSGQ_MAX_MSGS);
 
+	k_pipe_write(&no_wait_pipe, PIPE_DATA, sizeof(PIPE_DATA), K_NO_WAIT);
+
 	struct k_poll_event events[] = {
 		K_POLL_EVENT_INITIALIZER(K_POLL_TYPE_SEM_AVAILABLE,
 					 K_POLL_MODE_NOTIFY_ONLY,
@@ -94,6 +99,9 @@ ZTEST_USER(poll_api_1cpu, test_poll_no_wait)
 		K_POLL_EVENT_INITIALIZER(K_POLL_TYPE_MSGQ_DATA_AVAILABLE,
 					 K_POLL_MODE_NOTIFY_ONLY,
 					 mq),
+		K_POLL_EVENT_INITIALIZER(K_POLL_TYPE_PIPE_DATA_AVAILABLE,
+					 K_POLL_MODE_NOTIFY_ONLY,
+					 &no_wait_pipe),
 	};
 
 #ifdef CONFIG_USERSPACE
@@ -159,12 +167,18 @@ ZTEST_USER(poll_api_1cpu, test_poll_no_wait)
 	zassert_false(k_msgq_get(mq, msgq_recv_buf, K_NO_WAIT));
 	zassert_false(memcmp(msgq_msg, msgq_recv_buf, MSGQ_MSG_SIZE), "");
 
+	zassert_equal(events[5].state, K_POLL_STATE_PIPE_DATA_AVAILABLE);
+	result = k_pipe_read(&no_wait_pipe, pipe_recv_buf, sizeof(pipe_recv_buf), K_NO_WAIT);
+	zassert_equal(result, sizeof(PIPE_DATA));
+	zassert_str_equal(pipe_recv_buf, PIPE_DATA);
+
 	/* verify events are not ready anymore (user has to clear them first) */
 	events[0].state = K_POLL_STATE_NOT_READY;
 	events[1].state = K_POLL_STATE_NOT_READY;
 	events[2].state = K_POLL_STATE_NOT_READY;
 	events[3].state = K_POLL_STATE_NOT_READY;
 	events[4].state = K_POLL_STATE_NOT_READY;
+	events[5].state = K_POLL_STATE_NOT_READY;
 	k_poll_signal_reset(&no_wait_signal);
 
 	zassert_equal(k_poll(events, ARRAY_SIZE(events), K_NO_WAIT), -EAGAIN,
@@ -174,11 +188,11 @@ ZTEST_USER(poll_api_1cpu, test_poll_no_wait)
 	zassert_equal(events[2].state, K_POLL_STATE_NOT_READY, "");
 	zassert_equal(events[3].state, K_POLL_STATE_NOT_READY, "");
 	zassert_equal(events[4].state, K_POLL_STATE_NOT_READY, "");
+	zassert_equal(events[5].state, K_POLL_STATE_NOT_READY, "");
 
 	zassert_not_equal(k_sem_take(&no_wait_sem, K_NO_WAIT), 0, "");
 	zassert_is_null(k_fifo_get(&no_wait_fifo, K_NO_WAIT), "");
-	zassert_not_equal(k_msgq_get(mq, msgq_recv_buf, K_NO_WAIT), 0,
-			  "");
+	zassert_not_equal(k_msgq_get(mq, msgq_recv_buf, K_NO_WAIT), 0, "");
 }
 
 /* verify k_poll() that has to wait */
@@ -192,10 +206,13 @@ static struct k_poll_signal wait_signal =
 
 struct fifo_msg wait_msg = { NULL, FIFO_MSG_VALUE };
 
+K_PIPE_DEFINE(wait_pipe, 32, 1);
+
 #define TAG_0 10
 #define TAG_1 11
 #define TAG_2 12
 #define TAG_3 13
+#define TAG_4 14
 
 struct k_poll_event wait_events[] = {
 	K_POLL_EVENT_STATIC_INITIALIZER(K_POLL_TYPE_SEM_AVAILABLE,
@@ -213,10 +230,14 @@ struct k_poll_event wait_events[] = {
 	K_POLL_EVENT_STATIC_INITIALIZER(K_POLL_TYPE_MSGQ_DATA_AVAILABLE,
 					K_POLL_MODE_NOTIFY_ONLY,
 					&wait_msgq, TAG_3),
+	K_POLL_EVENT_STATIC_INITIALIZER(K_POLL_TYPE_PIPE_DATA_AVAILABLE,
+					K_POLL_MODE_NOTIFY_ONLY,
+					&wait_pipe, TAG_4),
 };
 
 #define USE_FIFO (1 << 0)
 #define USE_MSGQ (1 << 1)
+#define USE_PIPE (1 << 2)
 
 static void poll_wait_helper(void *use_queuelike, void *msgq, void *p3)
 {
@@ -239,6 +260,10 @@ static void poll_wait_helper(void *use_queuelike, void *msgq, void *p3)
 
 		k_msgq_put(msgq, &m[0], K_FOREVER);
 	}
+
+	if (flags & USE_PIPE) {
+		k_pipe_write(&wait_pipe, PIPE_DATA, sizeof(PIPE_DATA), K_NO_WAIT);
+	}
 }
 
 /* check results for multiple events */
@@ -248,6 +273,8 @@ void check_results(struct k_poll_event *events, uint32_t event_type,
 	struct fifo_msg *msg_ptr;
 	char msgq_recv_buf[MSGQ_MSG_SIZE] = {0};
 	char msg[] = MSGQ_MSG_VALUE;
+	char pipe_recv_buf[sizeof(PIPE_DATA) + 4];
+	int result;
 
 	switch (event_type) {
 	case K_POLL_TYPE_SEM_AVAILABLE:
@@ -317,7 +344,20 @@ void check_results(struct k_poll_event *events, uint32_t event_type,
 				      "");
 		}
 		break;
-
+	case K_POLL_TYPE_PIPE_DATA_AVAILABLE:
+		if (is_available) {
+			zassert_equal(events->state, K_POLL_STATE_PIPE_DATA_AVAILABLE);
+			result = k_pipe_read(&wait_pipe, pipe_recv_buf,
+					     sizeof(pipe_recv_buf), K_NO_WAIT);
+			zassert_equal(result, sizeof(PIPE_DATA));
+			zassert_str_equal(pipe_recv_buf, PIPE_DATA);
+			zassert_equal(events->tag, TAG_4);
+			/* reset to not ready */
+			events->state = K_POLL_STATE_NOT_READY;
+		} else {
+			zassert_equal(events->state, K_POLL_STATE_NOT_READY);
+		}
+		break;
 	default:
 		__ASSERT(false, "invalid event type (0x%x)\n", event_type);
 		break;
@@ -403,9 +443,9 @@ ZTEST(poll_api_1cpu, test_poll_wait)
 
 	k_tid_t tid1 = k_thread_create(&test_thread, test_stack,
 			K_THREAD_STACK_SIZEOF(test_stack),
-			poll_wait_helper, (void *)(USE_FIFO | USE_MSGQ), wait_msgq_ptr, 0,
-			main_low_prio - 1, K_USER | K_INHERIT_PERMS,
-			K_NO_WAIT);
+			poll_wait_helper, (void *)(USE_FIFO | USE_MSGQ | USE_PIPE),
+			wait_msgq_ptr, 0, main_low_prio - 1,
+			K_USER | K_INHERIT_PERMS, K_NO_WAIT);
 
 	rc = k_poll(wait_events, ARRAY_SIZE(wait_events), K_NO_WAIT);
 	zassert_equal(rc, -EAGAIN, "should return EAGAIN with K_NO_WAIT");
@@ -422,6 +462,7 @@ ZTEST(poll_api_1cpu, test_poll_wait)
 	check_results(&wait_events[2], K_POLL_TYPE_SIGNAL, true);
 	check_results(&wait_events[3], K_POLL_TYPE_IGNORE, true);
 	check_results(&wait_events[4], K_POLL_TYPE_MSGQ_DATA_AVAILABLE, true);
+	check_results(&wait_events[5], K_POLL_TYPE_PIPE_DATA_AVAILABLE, true);
 
 	/* verify events are not ready anymore */
 	zassert_equal(k_poll(wait_events, ARRAY_SIZE(wait_events),
@@ -433,6 +474,7 @@ ZTEST(poll_api_1cpu, test_poll_wait)
 	check_results(&wait_events[2], K_POLL_TYPE_SIGNAL, false);
 	check_results(&wait_events[3], K_POLL_TYPE_IGNORE, false);
 	check_results(&wait_events[4], K_POLL_TYPE_MSGQ_DATA_AVAILABLE, false);
+	check_results(&wait_events[5], K_POLL_TYPE_PIPE_DATA_AVAILABLE, false);
 
 	/*
 	 * Wait for 2 out of 4 non-ready events to become ready from a higher
@@ -455,6 +497,7 @@ ZTEST(poll_api_1cpu, test_poll_wait)
 	check_results(&wait_events[1], K_POLL_TYPE_DATA_AVAILABLE, false);
 	check_results(&wait_events[2], K_POLL_TYPE_SIGNAL, true);
 	check_results(&wait_events[4], K_POLL_TYPE_MSGQ_DATA_AVAILABLE, false);
+	check_results(&wait_events[4], K_POLL_TYPE_PIPE_DATA_AVAILABLE, false);
 
 	/*
 	 * Wait for each event to be ready from a lower priority thread, one at
@@ -473,6 +516,7 @@ ZTEST(poll_api_1cpu, test_poll_wait)
 	check_results(&wait_events[1], K_POLL_TYPE_DATA_AVAILABLE, false);
 	check_results(&wait_events[2], K_POLL_TYPE_SIGNAL, false);
 	check_results(&wait_events[4], K_POLL_TYPE_MSGQ_DATA_AVAILABLE, false);
+	check_results(&wait_events[5], K_POLL_TYPE_PIPE_DATA_AVAILABLE, false);
 
 	/* fifo */
 	rc = k_poll(wait_events, ARRAY_SIZE(wait_events), K_SECONDS(1));
@@ -483,6 +527,7 @@ ZTEST(poll_api_1cpu, test_poll_wait)
 	check_results(&wait_events[1], K_POLL_TYPE_DATA_AVAILABLE, true);
 	check_results(&wait_events[2], K_POLL_TYPE_SIGNAL, false);
 	check_results(&wait_events[4], K_POLL_TYPE_MSGQ_DATA_AVAILABLE, false);
+	check_results(&wait_events[5], K_POLL_TYPE_PIPE_DATA_AVAILABLE, false);
 
 	/* poll signal */
 	rc = k_poll(wait_events, ARRAY_SIZE(wait_events), K_SECONDS(1));
@@ -493,6 +538,7 @@ ZTEST(poll_api_1cpu, test_poll_wait)
 	check_results(&wait_events[1], K_POLL_TYPE_DATA_AVAILABLE, false);
 	check_results(&wait_events[2], K_POLL_TYPE_SIGNAL, true);
 	check_results(&wait_events[4], K_POLL_TYPE_MSGQ_DATA_AVAILABLE, false);
+	check_results(&wait_events[5], K_POLL_TYPE_PIPE_DATA_AVAILABLE, false);
 
 	/* message queue */
 	rc = k_poll(wait_events, ARRAY_SIZE(wait_events), K_SECONDS(1));
@@ -503,6 +549,7 @@ ZTEST(poll_api_1cpu, test_poll_wait)
 	check_results(&wait_events[1], K_POLL_TYPE_DATA_AVAILABLE, false);
 	check_results(&wait_events[2], K_POLL_TYPE_SIGNAL, false);
 	check_results(&wait_events[4], K_POLL_TYPE_MSGQ_DATA_AVAILABLE, true);
+	check_results(&wait_events[5], K_POLL_TYPE_PIPE_DATA_AVAILABLE, false);
 
 	k_thread_abort(tid1);
 	k_thread_abort(tid2);
@@ -780,7 +827,8 @@ void poll_test_grant_access(void)
 			      &no_wait_signal, &wait_sem, &wait_fifo,
 			      &cancel_fifo, &non_cancel_fifo,
 			      &wait_signal, &test_thread, &test_signal,
-			      &test_stack, &multi_sem, &multi_reply);
+			      &test_stack, &multi_sem, &multi_reply,
+			      &no_wait_pipe, &wait_pipe);
 }
 
 
diff --git a/tests/kernel/poll/testcase.yaml b/tests/kernel/poll/testcase.yaml
index fdf503e3615..8985672ad98 100644
--- a/tests/kernel/poll/testcase.yaml
+++ b/tests/kernel/poll/testcase.yaml
@@ -4,10 +4,8 @@ tests:
     tags:
       - kernel
       - userspace
-    # FIXME: qemu_arc/qemu_arc_hs6x is excluded due to a run-time failure, see #49492
     platform_exclude:
       - nrf52dk/nrf52810
-      - qemu_arc/qemu_arc_hs6x
   kernel.poll.minimallibc:
     filter: CONFIG_MINIMAL_LIBC_SUPPORTED
     ignore_faults: true
@@ -15,9 +13,7 @@ tests:
       - kernel
       - userspace
       - libc
-    # FIXME: qemu_arc/qemu_arc_hs6x is excluded due to a run-time failure, see #49492
     platform_exclude:
       - nrf52dk/nrf52810
-      - qemu_arc/qemu_arc_hs6x
     extra_configs:
       - CONFIG_MINIMAL_LIBC=y
diff --git a/tests/kernel/sched/metairq/src/main.c b/tests/kernel/sched/metairq/src/main.c
index be8985413f2..5afd3e07794 100644
--- a/tests/kernel/sched/metairq/src/main.c
+++ b/tests/kernel/sched/metairq/src/main.c
@@ -77,6 +77,8 @@ void metairq_thread(void *p1, void *p2, void *p3)
 
 	k_msleep(WAIT_MS);
 
+	zassert_not_equal(coop_cnt2, LOOP_CNT, "thread2 wasn't preempted");
+
 	printk("give sem1\n");
 	k_sem_give(&coop_sem1);
 
@@ -113,6 +115,8 @@ void coop_thread1(void *p1, void *p2, void *p3)
 	cnt2 = coop_cnt2;
 	zassert_equal(cnt2, LOOP_CNT, "Unexpected cnt2 at end: %d", cnt2);
 
+	printk("thread1 end\n");
+
 	k_sem_give(&coop_sem1);
 }
 
@@ -155,6 +159,8 @@ void coop_thread2(void *p1, void *p2, void *p3)
 	cnt2 = coop_cnt2;
 	zassert_equal(cnt2, LOOP_CNT, "Unexpected cnt2 at end: %d", cnt2);
 
+	printk("thread2 end\n");
+
 	k_sem_give(&coop_sem2);
 }
 
diff --git a/tests/kernel/sched/schedule_api/prj_simple.conf b/tests/kernel/sched/schedule_api/prj_simple.conf
index 9e3c6111604..4b931c32afc 100644
--- a/tests/kernel/sched/schedule_api/prj_simple.conf
+++ b/tests/kernel/sched/schedule_api/prj_simple.conf
@@ -5,4 +5,3 @@ CONFIG_SCHED_SIMPLE=y
 CONFIG_MAX_THREAD_BYTES=6
 CONFIG_MP_MAX_NUM_CPUS=1
 CONFIG_ZTEST_FATAL_HOOK=y
-CONFIG_MINIMAL_LIBC=y
diff --git a/tests/kernel/semaphore/semaphore/prj.conf b/tests/kernel/semaphore/semaphore/prj.conf
index e193f5f626d..1ae0b78bdbf 100644
--- a/tests/kernel/semaphore/semaphore/prj.conf
+++ b/tests/kernel/semaphore/semaphore/prj.conf
@@ -2,5 +2,4 @@ CONFIG_ZTEST=y
 CONFIG_IRQ_OFFLOAD=y
 CONFIG_TEST_USERSPACE=y
 CONFIG_ZTEST_FATAL_HOOK=y
-CONFIG_PIPES=y
 CONFIG_MAX_THREAD_BYTES=3
diff --git a/tests/kernel/semaphore/semaphore/src/main.c b/tests/kernel/semaphore/semaphore/src/main.c
index 97816a3a47a..51007c3a306 100644
--- a/tests/kernel/semaphore/semaphore/src/main.c
+++ b/tests/kernel/semaphore/semaphore/src/main.c
@@ -980,7 +980,6 @@ void sem_multiple_take_and_timeouts_helper(void *p1, void *p2, void *p3)
 {
 	int timeout = POINTER_TO_INT(p1);
 	int64_t start_ticks, end_ticks, diff_ticks;
-	size_t bytes_written;
 
 	start_ticks = k_uptime_get();
 
@@ -994,8 +993,7 @@ void sem_multiple_take_and_timeouts_helper(void *p1, void *p2, void *p3)
 		     "time mismatch - expected at least %d, got %lld",
 		     timeout, diff_ticks);
 
-	k_pipe_put(&timeout_info_pipe, &timeout, sizeof(int),
-		   &bytes_written, sizeof(int), K_FOREVER);
+	k_pipe_write(&timeout_info_pipe, (uint8_t *)&timeout, sizeof(int), K_FOREVER);
 
 }
 
@@ -1011,10 +1009,9 @@ ZTEST(semaphore_1cpu, test_sem_multiple_take_and_timeouts)
 	}
 
 	static uint32_t timeout;
-	size_t bytes_read;
 
 	k_sem_reset(&simple_sem);
-	k_pipe_flush(&timeout_info_pipe);
+	k_pipe_reset(&timeout_info_pipe);
 
 	/* Multiple threads timeout and the sequence in which it times out
 	 * is pushed into a pipe and checked later on.
@@ -1028,8 +1025,7 @@ ZTEST(semaphore_1cpu, test_sem_multiple_take_and_timeouts)
 	}
 
 	for (int i = 0; i < TOTAL_THREADS_WAITING; i++) {
-		k_pipe_get(&timeout_info_pipe, &timeout, sizeof(int),
-			   &bytes_read, sizeof(int), K_FOREVER);
+		k_pipe_read(&timeout_info_pipe, (uint8_t *)&timeout, sizeof(int), K_FOREVER);
 		zassert_equal(timeout, QSEC2MS(i + 1),
 			     "timeout did not occur properly: %d != %d",
 				 timeout, QSEC2MS(i + 1));
@@ -1043,10 +1039,10 @@ ZTEST(semaphore_1cpu, test_sem_multiple_take_and_timeouts)
 
 void sem_multi_take_timeout_diff_sem_helper(void *p1, void *p2, void *p3)
 {
+	int rc;
 	int timeout = POINTER_TO_INT(p1);
 	struct k_sem *sema = p2;
 	int64_t start_ticks, end_ticks, diff_ticks;
-	size_t bytes_written;
 	struct timeout_info info = {
 		.timeout = timeout,
 		.sema = sema
@@ -1064,8 +1060,10 @@ void sem_multi_take_timeout_diff_sem_helper(void *p1, void *p2, void *p3)
 		     "time mismatch - expected at least %d, got %lld",
 		     timeout, diff_ticks);
 
-	k_pipe_put(&timeout_info_pipe, &info, sizeof(struct timeout_info),
-		   &bytes_written, sizeof(struct timeout_info), K_FOREVER);
+	rc = k_pipe_write(&timeout_info_pipe, (uint8_t *)&info, sizeof(struct timeout_info),
+		   K_FOREVER);
+	zassert_true(rc == sizeof(struct timeout_info),
+		     "k_pipe_write failed: %d", rc);
 }
 
 /**
@@ -1075,11 +1073,11 @@ void sem_multi_take_timeout_diff_sem_helper(void *p1, void *p2, void *p3)
  */
 ZTEST(semaphore, test_sem_multi_take_timeout_diff_sem)
 {
+	int rc;
 	if (IS_ENABLED(CONFIG_KERNEL_COHERENCE)) {
 		ztest_test_skip();
 	}
 
-	size_t bytes_read;
 	struct timeout_info seq_info[] = {
 		{ SEC2MS(2), &simple_sem },
 		{ SEC2MS(1), &multiple_thread_sem },
@@ -1092,7 +1090,7 @@ ZTEST(semaphore, test_sem_multi_take_timeout_diff_sem)
 
 	k_sem_reset(&simple_sem);
 	k_sem_reset(&multiple_thread_sem);
-	k_pipe_flush(&timeout_info_pipe);
+	k_pipe_reset(&timeout_info_pipe);
 	memset(&retrieved_info, 0, sizeof(struct timeout_info));
 
 	/* Multiple threads timeout on different semaphores and the sequence
@@ -1108,13 +1106,10 @@ ZTEST(semaphore, test_sem_multi_take_timeout_diff_sem)
 	}
 
 	for (int i = 0; i < TOTAL_THREADS_WAITING; i++) {
-		k_pipe_get(&timeout_info_pipe,
-			   &retrieved_info,
-			   sizeof(struct timeout_info),
-			   &bytes_read,
-			   sizeof(struct timeout_info),
-			   K_FOREVER);
-
+		rc = k_pipe_read(&timeout_info_pipe, (uint8_t *)&retrieved_info,
+			sizeof(struct timeout_info), K_FOREVER);
+		zassert_true(rc == sizeof(struct timeout_info),
+			     "k_pipe_read failed: %d", rc);
 
 		zassert_true(retrieved_info.timeout == SEC2MS(i + 1),
 			     "timeout did not occur properly");
diff --git a/tests/kernel/semaphore/sys_sem/src/main.c b/tests/kernel/semaphore/sys_sem/src/main.c
index fc65668a7ad..8a9a5dfc522 100644
--- a/tests/kernel/semaphore/sys_sem/src/main.c
+++ b/tests/kernel/semaphore/sys_sem/src/main.c
@@ -27,7 +27,6 @@ static ZTEST_DMEM int flag;
 static ZTEST_DMEM atomic_t atomic_count;
 
 /**
- * @defgroup kernel_sys_sem_tests Semaphore
  * @ingroup all_tests
  * @{
  * @}
@@ -73,7 +72,7 @@ static void thread_high_prio_sem_take(void *p1, void *p2, void *p3)
  * - Use semaphore normally
  * - Use semaphore with different priority threads
  *
- * @ingroup kernel_sys_sem_tests
+ * @ingroup kernel_semaphore_tests
  */
 ZTEST_USER(kernel_sys_sem, test_multiple_thread_sem_usage)
 {
@@ -168,7 +167,7 @@ static void multi_thread_sem_take(void *p1, void *p2, void *p3)
  * - Verify more than max count about semaphore can reach.
  * - Take sem by multiple threads and verify if sem count is correct.
  *
- * @ingroup kernel_sys_sem_tests
+ * @ingroup kernel_semaphore_tests
  */
 ZTEST_USER(kernel_sys_sem, test_multi_thread_sem_limit)
 {
diff --git a/tests/kernel/sleep/src/usleep.c b/tests/kernel/sleep/src/usleep.c
index b7c1144505a..8a234a27a19 100644
--- a/tests/kernel/sleep/src/usleep.c
+++ b/tests/kernel/sleep/src/usleep.c
@@ -36,6 +36,12 @@
 #elif defined(CONFIG_CC13XX_CC26XX_RTC_TIMER) && \
 	(CONFIG_SYS_CLOCK_TICKS_PER_SEC > 16384)
 #define MAXIMUM_SHORTEST_TICKS 3
+#elif defined(CONFIG_SILABS_SLEEPTIMER_TIMER) && (CONFIG_SYS_CLOCK_TICKS_PER_SEC > 16384)
+/* Similar situation for Silabs devices using sleeptimer due to the
+ * limitation that a value too close to the current time cannot be
+ * loaded to its comparator.
+ */
+#define MAXIMUM_SHORTEST_TICKS 2
 #else
 #define MAXIMUM_SHORTEST_TICKS 1
 #endif
diff --git a/tests/kernel/sleep/testcase.yaml b/tests/kernel/sleep/testcase.yaml
index eceb053d082..21d7846941f 100644
--- a/tests/kernel/sleep/testcase.yaml
+++ b/tests/kernel/sleep/testcase.yaml
@@ -3,6 +3,10 @@ tests:
     tags:
       - kernel
       - sleep
+    platform_exclude:
+      - npcx4m8f_evb
+      - npcx7m6fb_evb
+      - npcx9m6f_evb
   kernel.common.timing.minimallibc:
     filter: CONFIG_MINIMAL_LIBC_SUPPORTED
     tags:
diff --git a/tests/kernel/smp/testcase.yaml b/tests/kernel/smp/testcase.yaml
index 650ed72c208..725a972ff04 100644
--- a/tests/kernel/smp/testcase.yaml
+++ b/tests/kernel/smp/testcase.yaml
@@ -31,6 +31,9 @@ tests:
       - smp
     ignore_faults: true
     filter: (CONFIG_MP_MAX_NUM_CPUS > 1)
+    platform_exclude:
+      - qemu_riscv64/qemu_virt_riscv64/smp # qemu_riscv64 doesn't support custom ROM offset
+      - qemu_riscv32/qemu_virt_riscv32/smp # qemu_riscv32 doesn't support custom ROM offset
     extra_configs:
       - CONFIG_SCHED_CPU_MASK=y
       - CONFIG_ROM_START_OFFSET=0x80
diff --git a/tests/kernel/spinlock/src/main.c b/tests/kernel/spinlock/src/main.c
index 1e5de11ff00..61447411714 100644
--- a/tests/kernel/spinlock/src/main.c
+++ b/tests/kernel/spinlock/src/main.c
@@ -83,7 +83,7 @@ static void bounce_once(int id, bool trylock)
 		}
 
 		k_spin_unlock(&bounce_lock, key);
-		k_busy_wait(100);
+		k_busy_wait(1);
 	}
 
 	if (!locked && bounce_done) {
@@ -99,7 +99,7 @@ static void bounce_once(int id, bool trylock)
 
 	for (i = 0; i < 5; i++) {
 		zassert_true(bounce_owner == id, "Locked data changed");
-		k_busy_wait(1);
+		k_busy_wait(5);
 	}
 
 	/* Release the lock */
diff --git a/tests/kernel/threads/no-multithreading/testcase.yaml b/tests/kernel/threads/no-multithreading/testcase.yaml
index ae0556c54c6..93f7757c861 100644
--- a/tests/kernel/threads/no-multithreading/testcase.yaml
+++ b/tests/kernel/threads/no-multithreading/testcase.yaml
@@ -10,6 +10,7 @@ tests:
       - nrf52840dk/nrf52840
       - nrf9160dk/nrf9160
       - nrf51dk/nrf51822
+      - xg29_rb4412a
       - nsim/nsim_em
       - nsim/nsim_em7d_v22
       - nsim/nsim_hs
diff --git a/tests/kernel/threads/thread_apis/Kconfig b/tests/kernel/threads/thread_apis/Kconfig
new file mode 100644
index 00000000000..cc3249570da
--- /dev/null
+++ b/tests/kernel/threads/thread_apis/Kconfig
@@ -0,0 +1,16 @@
+# Copyright (c) 2024 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+mainmenu "Thread APIs test"
+
+source "Kconfig.zephyr"
+
+config THREAD_API_UNMAPPED_ADDRESS
+	hex "Unmapped address from which to read"
+	default 0xFFFFFFF0
+	help
+	  This is the unmapped address that test_thread_name_user_get_set()
+	  will attempt to use if CONFIG_TRUSTED_EXECUTION_NONSECURE is not
+	  enabled. For most platforms, this address can be expected to be
+	  near the end of addressable memory; however it is not guaranteed
+	  for all platforms.
diff --git a/tests/kernel/threads/thread_apis/boards/qemu_cortex_r5.conf b/tests/kernel/threads/thread_apis/boards/qemu_cortex_r5.conf
new file mode 100644
index 00000000000..6b572f9d4d4
--- /dev/null
+++ b/tests/kernel/threads/thread_apis/boards/qemu_cortex_r5.conf
@@ -0,0 +1 @@
+CONFIG_THREAD_API_UNMAPPED_ADDRESS=0xF9200000
diff --git a/tests/kernel/threads/thread_apis/src/main.c b/tests/kernel/threads/thread_apis/src/main.c
index 162f85e5f5f..e073e0a8725 100644
--- a/tests/kernel/threads/thread_apis/src/main.c
+++ b/tests/kernel/threads/thread_apis/src/main.c
@@ -78,7 +78,7 @@ static void customdata_entry(void *p1, void *p2, void *p3)
 
 /**
  * @ingroup kernel_thread_tests
- * @brief test thread custom data get/set from coop thread
+ * @brief Test thread custom data get/set from coop thread
  *
  * @see k_thread_custom_data_get(), k_thread_custom_data_set()
  */
@@ -101,7 +101,7 @@ static void thread_name_entry(void *p1, void *p2, void *p3)
 
 /**
  * @ingroup kernel_thread_tests
- * @brief test thread name get/set from supervisor thread
+ * @brief Test thread name get/set from supervisor thread
  * @see k_thread_name_get(), k_thread_name_copy(), k_thread_name_set()
  */
 ZTEST(threads_lifecycle, test_thread_name_get_set)
@@ -142,7 +142,7 @@ struct k_sem sem;
 
 /**
  * @ingroup kernel_thread_tests
- * @brief test thread name get/set from user thread
+ * @brief Test thread name get/set from user thread
  * @see k_thread_name_copy(), k_thread_name_set()
  */
 ZTEST_USER(threads_lifecycle, test_thread_name_user_get_set)
@@ -157,7 +157,7 @@ ZTEST_USER(threads_lifecycle, test_thread_name_user_get_set)
 	/* Non-Secure images cannot normally access memory outside the image
 	 * flash and ram.
 	 */
-	ret = k_thread_name_set(NULL, (const char *)0xFFFFFFF0);
+	ret = k_thread_name_set(NULL, (const char *)CONFIG_THREAD_API_UNMAPPED_ADDRESS);
 	zassert_equal(ret, -EFAULT, "accepted nonsense string (%d)", ret);
 #endif
 	ret = k_thread_name_set(NULL, unreadable_string);
@@ -211,7 +211,7 @@ ZTEST_USER(threads_lifecycle, test_thread_name_user_get_set)
 
 /**
  * @ingroup kernel_thread_tests
- * @brief test thread custom data get/set from preempt thread
+ * @brief Test thread custom data get/set from preempt thread
  * @see k_thread_custom_data_get(), k_thread_custom_data_set()
  */
 ZTEST_USER(threads_lifecycle_1cpu, test_customdata_get_set_preempt)
@@ -243,7 +243,7 @@ static void umode_entry(void *thread_id, void *p2, void *p3)
 
 /**
  * @ingroup kernel_thread_tests
- * @brief Test k_thread_user_mode_enter() to cover when userspace
+ * @brief Test k_thread_user_mode_enter to cover when userspace
  * is not supported/enabled
  * @see k_thread_user_mode_enter()
  */
@@ -326,7 +326,7 @@ static void do_join_from_isr(const void *arg)
 static int join_scenario_interval(enum control_method m, int64_t *interval)
 {
 	k_timeout_t timeout = K_FOREVER;
-	int ret;
+	int ret = 0;
 
 	LOG_DBG("ztest_thread: method %d, create join_thread", m);
 	k_thread_create(&join_thread, join_stack, STACK_SIZE, join_entry,
@@ -392,6 +392,11 @@ static inline int join_scenario(enum control_method m)
 	return join_scenario_interval(m, NULL);
 }
 
+/**
+ * @ingroup kernel_thread_tests
+ * @brief Test thread join
+ *
+ */
 ZTEST_USER(threads_lifecycle, test_thread_join)
 {
 	int64_t interval;
@@ -415,6 +420,13 @@ ZTEST_USER(threads_lifecycle, test_thread_join)
 
 }
 
+/**
+ * @ingroup kernel_thread_tests
+ * @brief Test thread join from ISR
+ *
+ * @see k_thread_join()
+ * @see k_thread_abort()
+ */
 ZTEST(threads_lifecycle, test_thread_join_isr)
 {
 	zassert_equal(join_scenario(ISR_RUNNING), -EBUSY, "failed isr running");
@@ -447,6 +459,21 @@ static void deadlock2_entry(void *p1, void *p2, void *p3)
 	zassert_equal(ret, 0, "couldn't join deadlock2_thread");
 }
 
+
+
+/**
+ * @brief Test case for thread join deadlock scenarios.
+ *
+ * This test verifies the behavior of the `k_thread_join` API in scenarios
+ * that could lead to deadlocks. It includes the following checks:
+ *
+ * - Ensures that a thread cannot join itself, which would result in a
+ *   self-deadlock. The API should return `-EDEADLK` in this case.
+ * - Creates two threads (`deadlock1_thread` and `deadlock2_thread`) and
+ *   verifies that they can be joined successfully without causing a deadlock.
+ *
+ * @ingroup kernel_thread_tests
+ */
 ZTEST_USER(threads_lifecycle, test_thread_join_deadlock)
 {
 	/* Deadlock scenarios */
@@ -476,6 +503,11 @@ static void user_start_thread(void *p1, void *p2, void *p3)
 {
 	/* do nothing */
 }
+/**
+ * @brief Test case for verifying thread timeout expiration and remaining time.
+ *
+ * @ingroup kernel_thread_tests
+ */
 
 ZTEST_USER(threads_lifecycle, test_thread_timeout_remaining_expires)
 {
@@ -528,10 +560,16 @@ static void foreach_callback(const struct k_thread *thread, void *user_data)
 		stats.execution_cycles;
 }
 
-/* This case accumulates every thread's execution_cycles first, then
+/**
+ * @brief Test case for thread runtime statistics retrieval in Zephyr kernel
+ *
+ * This case accumulates every thread's execution_cycles first, then
  * get the total execution_cycles from a global
  * k_thread_runtime_stats_t to see that all time is reflected in the
  * total.
+ *
+ * @ingroup kernel_thread_tests
+ * @see k_thread_runtime_stats_get()
  */
 ZTEST(threads_lifecycle, test_thread_runtime_stats_get)
 {
@@ -551,6 +589,13 @@ ZTEST(threads_lifecycle, test_thread_runtime_stats_get)
 	zassert_true(stats.execution_cycles <= stats_all.execution_cycles);
 }
 
+
+/**
+ * @brief Test the behavior of k_busy_wait with thread runtime statistics.
+ *
+ * This test verifies the accuracy of the `k_busy_wait` function by checking
+ * the thread's execution cycle statistics before and after calling the function.
+ */
 ZTEST(threads_lifecycle, test_k_busy_wait)
 {
 	uint64_t cycles, dt;
@@ -589,6 +634,12 @@ static void tp_entry(void *p1, void *p2, void *p3)
 	tp = 100;
 }
 
+/**
+ * @brief Test the behavior of k_busy_wait with thread runtime statistics
+ *        in user mode.
+ *
+ * @ingroup kernel_thread_tests
+ */
 ZTEST_USER(threads_lifecycle_1cpu, test_k_busy_wait_user)
 {
 
@@ -624,9 +675,14 @@ static int small_stack(size_t *space)
 	return k_thread_stack_space_get(k_current_get(), space);
 }
 
-/* test k_thread_stack_sapce_get(), unused stack space in large_stack_space()
+/**
+ * @brief Test k_thread_stack_sapce_get
+ *
+ * Test k_thread_stack_sapce_get unused stack space in large_stack_space()
  * is smaller than that in small_stack() because the former function has a
  * large local variable
+ *
+ * @ingroup kernel_thread_tests
  */
 ZTEST_USER(threads_lifecycle, test_k_thread_stack_space_get_user)
 {
diff --git a/tests/kernel/threads/thread_apis/src/test_essential_thread.c b/tests/kernel/threads/thread_apis/src/test_essential_thread.c
index 082765bd148..5fb316d51e5 100644
--- a/tests/kernel/threads/thread_apis/src/test_essential_thread.c
+++ b/tests/kernel/threads/thread_apis/src/test_essential_thread.c
@@ -67,8 +67,6 @@ void k_sys_fatal_error_handler(unsigned int reason,
 	ARG_UNUSED(reason);
 
 	fatal_error_signaled = true;
-
-	z_thread_essential_clear(_current);
 }
 
 static void abort_thread_entry(void *p1, void *p2, void *p3)
@@ -77,16 +75,19 @@ static void abort_thread_entry(void *p1, void *p2, void *p3)
 	ARG_UNUSED(p2);
 	ARG_UNUSED(p3);
 
-	z_thread_essential_set(_current);
-
 	if (z_is_thread_essential(_current)) {
-		k_busy_wait(100);
+		k_msleep(200);
 	} else {
 		zassert_unreachable("The thread is not set as essential");
 	}
 
-	k_sem_give(&sync_sem);
-	k_sleep(K_FOREVER);
+	zassert_true(false, "Should not reach this line");
+}
+
+static void abort_thread_self(void *p1, void *p2, void *p3)
+{
+	k_thread_abort(k_current_get());
+	zassert_true(false, "Should not reach this line");
 }
 
 /**
@@ -102,13 +103,48 @@ static void abort_thread_entry(void *p1, void *p2, void *p3)
 
 ZTEST(threads_lifecycle, test_essential_thread_abort)
 {
-	k_tid_t tid = k_thread_create(&kthread_thread1, kthread_stack, STACKSIZE,
-				      abort_thread_entry,
-				      NULL, NULL, NULL, K_PRIO_PREEMPT(0), 0,
-				      K_NO_WAIT);
+	fatal_error_signaled = false;
+	k_thread_create(&kthread_thread1, kthread_stack, STACKSIZE,
+			abort_thread_entry,
+			NULL, NULL, NULL, K_PRIO_PREEMPT(0), K_ESSENTIAL,
+			K_NO_WAIT);
+
+	k_msleep(100);
+	k_thread_abort(&kthread_thread1);
+	zassert_true(fatal_error_signaled, "fatal error was not signaled");
+}
 
-	k_sem_take(&sync_sem, K_FOREVER);
-	k_thread_abort(tid);
+/**
+ * @brief Abort an essential thread from itself
+ *
+ * @details The kernel shall raise a fatal system error if an essential thread
+ *          aborts, implement k_sys_fatal_error_handler to handle this error.
+ *
+ * @ingroup kernel_thread_tests
+ *
+ * @see #K_ESSENTIAL(x)
+ */
+ZTEST(threads_lifecycle, test_essential_thread_abort_self)
+{
+	/* This test case needs to be able to handle a k_panic() call
+	 * that aborts the current thread inside of the panic handler
+	 * itself.  That's putting a lot of strain on the arch layer
+	 * to handle things that haven't traditionally been required.
+	 * These ones aren't there yet.
+	 *
+	 * But run it for everyone else to catch regressions in the
+	 * code we are actually trying to test.
+	 */
+	if (IS_ENABLED(CONFIG_RISCV) || IS_ENABLED(CONFIG_X86) || IS_ENABLED(CONFIG_SPARC)) {
+		ztest_test_skip();
+	}
+
+	fatal_error_signaled = false;
+	k_thread_create(&kthread_thread1, kthread_stack, STACKSIZE,
+			abort_thread_self,
+			NULL, NULL, NULL, K_PRIO_PREEMPT(0), K_ESSENTIAL,
+			K_NO_WAIT);
 
+	k_msleep(100);
 	zassert_true(fatal_error_signaled, "fatal error was not signaled");
 }
diff --git a/tests/kernel/threads/thread_apis/src/test_threads_cancel_abort.c b/tests/kernel/threads/thread_apis/src/test_threads_cancel_abort.c
index b99347a404f..b79f237d7a7 100644
--- a/tests/kernel/threads/thread_apis/src/test_threads_cancel_abort.c
+++ b/tests/kernel/threads/thread_apis/src/test_threads_cancel_abort.c
@@ -32,7 +32,7 @@ static void thread_entry_abort(void *p1, void *p2, void *p3)
 }
 /**
  * @ingroup kernel_thread_tests
- * @brief Validate k_thread_abort() when called by current thread
+ * @brief Validate aborting a thread when called by current thread
  *
  * @details Create a user thread and let the thread execute.
  * Then call k_thread_abort() and check if the thread is terminated.
@@ -52,7 +52,7 @@ ZTEST_USER(threads_lifecycle, test_threads_abort_self)
 
 /**
  * @ingroup kernel_thread_tests
- * @brief Validate k_thread_abort() when called by other thread
+ * @brief Validate aborting a thread when called by other thread
  *
  * @details Create a user thread and abort the thread before its
  * execution. Create a another user thread and abort the thread
@@ -85,7 +85,7 @@ ZTEST_USER(threads_lifecycle, test_threads_abort_others)
 
 /**
  * @ingroup kernel_thread_tests
- * @brief Test abort on a terminated thread
+ * @brief Test abort on an already terminated thread
  *
  * @see k_thread_abort()
  */
diff --git a/tests/kernel/threads/thread_apis/src/test_threads_cpu_mask.c b/tests/kernel/threads/thread_apis/src/test_threads_cpu_mask.c
index dd521cbbf57..574bcd5aeee 100644
--- a/tests/kernel/threads/thread_apis/src/test_threads_cpu_mask.c
+++ b/tests/kernel/threads/thread_apis/src/test_threads_cpu_mask.c
@@ -22,6 +22,19 @@ void child_fn(void *a, void *b, void *c)
 	child_has_run = true;
 }
 
+
+/**
+ * @brief Test the CPU mask APIs for thread lifecycle management
+ *
+ * This test verifies the behavior of the CPU mask APIs in the Zephyr kernel
+ * for thread lifecycle management. It ensures that the APIs behave as expected
+ * when operating on both running and non-running threads.
+ *
+ * @note This test is only executed if `CONFIG_SCHED_CPU_MASK` is enabled.
+ *       Otherwise, the test is skipped.
+ *
+ * @ingroup kernel_thread_tests
+ */
 ZTEST(threads_lifecycle_1cpu, test_threads_cpu_mask)
 {
 #ifdef CONFIG_SCHED_CPU_MASK
diff --git a/tests/kernel/threads/thread_apis/src/test_threads_set_priority.c b/tests/kernel/threads/thread_apis/src/test_threads_set_priority.c
index 06672af99d1..1d022a3e28b 100644
--- a/tests/kernel/threads/thread_apis/src/test_threads_set_priority.c
+++ b/tests/kernel/threads/thread_apis/src/test_threads_set_priority.c
@@ -23,7 +23,7 @@ struct isr_arg {
 static struct isr_arg prio_args;
 
 /**
- * @brief Test ISR used to change a thread's priority
+ * @brief Test changing a thread's priority from an ISR
  */
 static void test_isr(const void *arg)
 {
@@ -33,9 +33,7 @@ static void test_isr(const void *arg)
 }
 
 /**
- *
- * @brief thread2 portion to test setting the priority
- *
+ * @brief Test thread behavior when its priority is changed
  */
 void thread2_set_prio_test(void *p1, void *p2, void *p3)
 {
@@ -61,7 +59,11 @@ void thread2_set_prio_test(void *p1, void *p2, void *p3)
 
 /**
  * @ingroup kernel_thread_tests
- * @brief Test the k_thread_priority_set() API
+ * @brief Test setting and verifying thread priorities
+ *
+ * @details This test creates a thread with a lower priority than the
+ * current thread. It then sets the priority of the thread to a
+ * higher value, and checks that the priority has been set correctly.
  *
  * @see k_thread_priority_set(), k_thread_priority_get()
  */
@@ -74,61 +76,64 @@ ZTEST(threads_lifecycle, test_threads_priority_set)
 	k_thread_priority_set(k_current_get(), prio + 2);
 	rv = k_thread_priority_get(k_current_get());
 	zassert_equal(rv, prio + 2,
-		      "Expected priority to be changed to %d, not %d\n",
-		      prio + 2, rv);
+			"Expected priority to be changed to %d, not %d\n",
+			prio + 2, rv);
 
 	/* Raise the priority of the current thread (thread1) */
 	k_thread_priority_set(k_current_get(), prio - 2);
 	rv = k_thread_priority_get(k_current_get());
 	zassert_equal(rv, prio - 2,
-		      "Expected priority to be changed to %d, not %d\n",
-		      prio - 2, rv);
+			"Expected priority to be changed to %d, not %d\n",
+			prio - 2, rv);
 
 	/* Restore the priority of the current thread (thread1) */
 	k_thread_priority_set(k_current_get(), prio);
 	rv = k_thread_priority_get(k_current_get());
 	zassert_equal(rv, prio,
-		      "Expected priority to be changed to %d, not %d\n",
-		      prio, rv);
+			"Expected priority to be changed to %d, not %d\n",
+			prio, rv);
 
 	/* create thread with lower priority */
 	int thread2_prio = prio + 1;
 
 	k_tid_t thread2_id = k_thread_create(&tdata, tstack, STACK_SIZE,
-					     thread2_set_prio_test,
-					     NULL, NULL, NULL, thread2_prio, 0,
-					     K_NO_WAIT);
+			thread2_set_prio_test,
+			NULL, NULL, NULL, thread2_prio, 0,
+			K_NO_WAIT);
 
 	/* Lower the priority of thread2 */
 	k_thread_priority_set(thread2_id, thread2_prio + 2);
 	k_sem_give(&sem_thread2);
 	k_sem_take(&sem_thread1, K_FOREVER);
 	zassert_equal(thread2_data, thread2_prio + 2,
-		      "Expected priority to be changed to %d, not %d\n",
-		      thread2_prio + 2, thread2_data);
+			"Expected priority to be changed to %d, not %d\n",
+			thread2_prio + 2, thread2_data);
 
 	/* Raise the priority of thread2 */
 	k_thread_priority_set(thread2_id, thread2_prio - 2);
 	k_sem_give(&sem_thread2);
 	k_sem_take(&sem_thread1, K_FOREVER);
 	zassert_equal(thread2_data, thread2_prio - 2,
-		      "Expected priority to be changed to %d, not %d\n",
-		      thread2_prio - 2, thread2_data);
+			"Expected priority to be changed to %d, not %d\n",
+			thread2_prio - 2, thread2_data);
 
 	/* Restore the priority of thread2 */
 	k_thread_priority_set(thread2_id, thread2_prio);
 	k_sem_give(&sem_thread2);
 	k_sem_take(&sem_thread1, K_FOREVER);
 	zassert_equal(thread2_data, thread2_prio,
-		      "Expected priority to be changed to %d, not %d\n",
-		      thread2_prio, thread2_data);
+			"Expected priority to be changed to %d, not %d\n",
+			thread2_prio, thread2_data);
 
 	k_thread_join(thread2_id, K_FOREVER);
 }
 
 /**
  * @ingroup kernel_thread_tests
- * @brief Test the k_thread_priority_set() API from an ISR
+ * @brief Test changing thread priorities from an ISR
+ *
+ * @details This test verifies that thread priorities can be changed
+ * correctly when invoked from an interrupt service routine (ISR).
  *
  * @see k_thread_priority_set(), k_thread_priority_get()
  */
@@ -143,32 +148,32 @@ ZTEST(threads_lifecycle, test_isr_threads_priority_set_)
 	irq_offload(test_isr, &prio_args);
 	rv = k_thread_priority_get(k_current_get());
 	zassert_equal(rv, prio + 2,
-		      "Expected priority to be changed to %d, not %d\n",
-		      prio + 2, rv);
+			"Expected priority to be changed to %d, not %d\n",
+			prio + 2, rv);
 
 	/* Raise the priority of the current thread (thread1) */
 	prio_args.prio = prio - 2;
 	irq_offload(test_isr, &prio_args);
 	rv = k_thread_priority_get(k_current_get());
 	zassert_equal(rv, prio - 2,
-		      "Expected priority to be changed to %d, not %d\n",
-		      prio - 2, rv);
+			"Expected priority to be changed to %d, not %d\n",
+			prio - 2, rv);
 
 	/* Restore the priority of the current thread (thread1) */
 	prio_args.prio = prio;
 	irq_offload(test_isr, &prio_args);
 	rv = k_thread_priority_get(k_current_get());
 	zassert_equal(rv, prio,
-		      "Expected priority to be changed to %d, not %d\n",
-		      prio, rv);
+			"Expected priority to be changed to %d, not %d\n",
+			prio, rv);
 
 	/* create thread with lower priority */
 	int thread2_prio = prio + 1;
 
 	k_tid_t thread2_id = k_thread_create(&tdata, tstack, STACK_SIZE,
-					     thread2_set_prio_test,
-					     NULL, NULL, NULL, thread2_prio, 0,
-					     K_NO_WAIT);
+			thread2_set_prio_test,
+			NULL, NULL, NULL, thread2_prio, 0,
+			K_NO_WAIT);
 
 	/* Lower the priority of thread2 */
 	prio_args.thread = thread2_id;
@@ -177,8 +182,8 @@ ZTEST(threads_lifecycle, test_isr_threads_priority_set_)
 	k_sem_give(&sem_thread2);
 	k_sem_take(&sem_thread1, K_FOREVER);
 	zassert_equal(thread2_data, thread2_prio + 2,
-		      "Expected priority to be changed to %d, not %d\n",
-		      thread2_prio + 2, thread2_data);
+			"Expected priority to be changed to %d, not %d\n",
+			thread2_prio + 2, thread2_data);
 
 	/* Raise the priority of thread2 */
 	prio_args.prio = thread2_prio - 2;
@@ -186,8 +191,8 @@ ZTEST(threads_lifecycle, test_isr_threads_priority_set_)
 	k_sem_give(&sem_thread2);
 	k_sem_take(&sem_thread1, K_FOREVER);
 	zassert_equal(thread2_data, thread2_prio - 2,
-		      "Expected priority to be changed to %d, not %d\n",
-		      thread2_prio - 2, thread2_data);
+			"Expected priority to be changed to %d, not %d\n",
+			thread2_prio - 2, thread2_data);
 
 	/* Restore the priority of thread2 */
 	prio_args.prio = thread2_prio;
@@ -195,7 +200,7 @@ ZTEST(threads_lifecycle, test_isr_threads_priority_set_)
 	k_sem_give(&sem_thread2);
 	k_sem_take(&sem_thread1, K_FOREVER);
 	zassert_equal(thread2_data, thread2_prio,
-		      "Expected priority to be changed to %d, not %d\n",
-		      thread2_prio, thread2_data);
+			"Expected priority to be changed to %d, not %d\n",
+			thread2_prio, thread2_data);
 	k_thread_join(thread2_id, K_FOREVER);
 }
diff --git a/tests/kernel/threads/thread_apis/src/test_threads_spawn.c b/tests/kernel/threads/thread_apis/src/test_threads_spawn.c
index 7d4847c44d7..893ccaa1f6d 100644
--- a/tests/kernel/threads/thread_apis/src/test_threads_spawn.c
+++ b/tests/kernel/threads/thread_apis/src/test_threads_spawn.c
@@ -129,7 +129,7 @@ ZTEST(threads_lifecycle, test_threads_spawn_forever)
 
 /**
  * @ingroup kernel_thread_tests
- * @brief Validate behavior of multiple calls to k_thread_start()
+ * @brief Validate behavior of multiple calls to k_thread_start
  *
  * @details Call k_thread_start() on an already terminated thread
  *
diff --git a/tests/kernel/threads/thread_apis/src/test_threads_suspend_resume.c b/tests/kernel/threads/thread_apis/src/test_threads_suspend_resume.c
index bc23b5f6774..a5810bad4fd 100644
--- a/tests/kernel/threads/thread_apis/src/test_threads_suspend_resume.c
+++ b/tests/kernel/threads/thread_apis/src/test_threads_suspend_resume.c
@@ -86,7 +86,7 @@ void suspend_myself(void *arg0, void *arg1, void *arg2)
 /**
  * @ingroup kernel_thread_tests
  *
- * @brief Check that k_thread_suspend() is a schedule point when
+ * @brief Check that suspending a thread is a schedule point when
  * called on the current thread.
  */
 ZTEST(threads_lifecycle, test_threads_suspend)
@@ -121,7 +121,7 @@ void sleep_suspended(void *arg0, void *arg1, void *arg2)
 
 /**
  * @ingroup kernel_thread_tests
- * @brief Check that k_thread_suspend() cancels a preexisting thread timeout
+ * @brief Check that suspending a thread cancels a preexisting thread timeout
  *
  * @details Suspended threads should not wake up unexpectedly if they
  * happened to have been sleeping when suspended.
@@ -149,7 +149,7 @@ ZTEST(threads_lifecycle, test_threads_suspend_timeout)
 
 /**
  * @ingroup kernel_thread_tests
- * @brief Check resume an unsuspend thread
+ * @brief Check resuming a thread that is not suspended
  *
  * @details Use k_thread_state_str() to get thread state.
  * Resume an unsuspend thread will not change the thread state.
diff --git a/tests/kernel/tickless/tickless_concept/Kconfig b/tests/kernel/tickless/tickless_concept/Kconfig
new file mode 100644
index 00000000000..9b62fa9209f
--- /dev/null
+++ b/tests/kernel/tickless/tickless_concept/Kconfig
@@ -0,0 +1,8 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 32768 if NRF_RTC_TIMER
+	default 100
+
+source "Kconfig.zephyr"
diff --git a/tests/kernel/tickless/tickless_concept/prj.conf b/tests/kernel/tickless/tickless_concept/prj.conf
index 289dda3092c..f8d48f84037 100644
--- a/tests/kernel/tickless/tickless_concept/prj.conf
+++ b/tests/kernel/tickless/tickless_concept/prj.conf
@@ -1,3 +1,2 @@
 CONFIG_ZTEST=y
-CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
 CONFIG_MP_MAX_NUM_CPUS=1
diff --git a/tests/kernel/tickless/tickless_concept/src/main.c b/tests/kernel/tickless/tickless_concept/src/main.c
index ce6f1c71f70..b48d78ede03 100644
--- a/tests/kernel/tickless/tickless_concept/src/main.c
+++ b/tests/kernel/tickless/tickless_concept/src/main.c
@@ -12,7 +12,7 @@
 static K_THREAD_STACK_ARRAY_DEFINE(tstack, NUM_THREAD, STACK_SIZE);
 static struct k_thread tdata[NUM_THREAD];
 
-#define IDLE_THRESH 20
+#define IDLE_THRESH k_ms_to_ticks_floor64(200)
 
 /*sleep duration tickless*/
 #define SLEEP_TICKLESS	 k_ticks_to_ms_floor64(IDLE_THRESH)
diff --git a/tests/kernel/tickless/tickless_concept/testcase.yaml b/tests/kernel/tickless/tickless_concept/testcase.yaml
index 186f76d539d..8b41e1f276f 100644
--- a/tests/kernel/tickless/tickless_concept/testcase.yaml
+++ b/tests/kernel/tickless/tickless_concept/testcase.yaml
@@ -1,8 +1,6 @@
 tests:
   kernel.tickless.concept:
     arch_exclude: nios2
-    # FIXME: This test fails sporadically on all QEMU platforms, but fails
-    # consistently when coverage is enabled. Disable until 14173 is fixed.
     platform_exclude:
       - litex_vexriscv
       - rv32m1_vega/openisa_rv32m1/zero_riscy
diff --git a/tests/kernel/timer/timer_api/src/main.c b/tests/kernel/timer/timer_api/src/main.c
index 899d2c92583..dc37239ff4b 100644
--- a/tests/kernel/timer/timer_api/src/main.c
+++ b/tests/kernel/timer/timer_api/src/main.c
@@ -749,16 +749,22 @@ ZTEST_USER(timer_api, test_timeout_abs)
 	k_timeout_t t = K_TIMEOUT_ABS_TICKS(exp_ticks), t2;
 	uint64_t t0, t1;
 
+	/* Ensure second alignment for K_TIMEOUT_ABS_SEC */
+	zassert_true(exp_ms % MSEC_PER_SEC == 0);
+
 	/* Check the other generator macros to make sure they produce
 	 * the same (whiteboxed) converted values
 	 */
+	t2 = K_TIMEOUT_ABS_SEC(exp_ms / MSEC_PER_SEC);
+	zassert_true(t2.ticks == t.ticks);
+
 	t2 = K_TIMEOUT_ABS_MS(exp_ms);
 	zassert_true(t2.ticks == t.ticks);
 
-	t2 = K_TIMEOUT_ABS_US(1000 * exp_ms);
+	t2 = K_TIMEOUT_ABS_US(USEC_PER_MSEC * exp_ms);
 	zassert_true(t2.ticks == t.ticks);
 
-	t2 = K_TIMEOUT_ABS_NS(1000 * 1000 * exp_ms);
+	t2 = K_TIMEOUT_ABS_NS(NSEC_PER_MSEC * exp_ms);
 	zassert_true(t2.ticks == t.ticks);
 
 	t2 = K_TIMEOUT_ABS_CYC(k_ms_to_cyc_ceil64(exp_ms));
diff --git a/tests/kernel/timer/timer_behavior/pytest/requirements-saleae.txt b/tests/kernel/timer/timer_behavior/pytest/requirements-saleae.txt
index 040349b7ec8..eefdd3a16b9 100644
--- a/tests/kernel/timer/timer_behavior/pytest/requirements-saleae.txt
+++ b/tests/kernel/timer/timer_behavior/pytest/requirements-saleae.txt
@@ -1,4 +1,4 @@
-numpy
+numpy>=2.2.3
 protobuf>=5.27.2
 grpcio-tools>=1.66.0
 logic2-automation>=1.0.7
diff --git a/tests/kernel/timer/timer_behavior/src/jitter_drift.c b/tests/kernel/timer/timer_behavior/src/jitter_drift.c
index 1a7935435bc..82e178fb602 100644
--- a/tests/kernel/timer/timer_behavior/src/jitter_drift.c
+++ b/tests/kernel/timer/timer_behavior/src/jitter_drift.c
@@ -235,10 +235,12 @@ static void do_test_using(void (*sample_collection_fn)(void), const char *mechan
 		* CONFIG_TIMER_TEST_SAMPLES;
 	double time_diff_us = actual_time_us - expected_time_us
 		- expected_time_drift_us;
+	double time_diff_us_abs = time_diff_us >= 0.0 ? time_diff_us : -time_diff_us;
+
 	/* If max stddev is lower than a single clock cycle then round it up. */
 	uint32_t max_stddev = MAX(k_cyc_to_us_ceil32(1), CONFIG_TIMER_TEST_MAX_STDDEV);
 
-	TC_PRINT("timer clock rate %d, kernel tick rate %d\n",
+	TC_PRINT("timer clock rate %u, kernel tick rate %d\n",
 		 sys_clock_hw_cycles_per_sec(), CONFIG_SYS_CLOCK_TICKS_PER_SEC);
 	if ((USEC_PER_SEC / CONFIG_TIMER_TEST_PERIOD) > CONFIG_SYS_CLOCK_TICKS_PER_SEC) {
 		TC_PRINT("test timer period (%u us) is smaller than "
@@ -280,8 +282,8 @@ static void do_test_using(void (*sample_collection_fn)(void), const char *mechan
 		 ", \"total_drift_us\":%.6f"
 		 ", \"expected_period_cycles\":%.0f"
 		 ", \"expected_period_drift_us\":%.6f"
-		 ", \"sys_clock_hw_cycles_per_sec\":%d"
-		 ", \"CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC\":%d"
+		 ", \"sys_clock_hw_cycles_per_sec\":%u"
+		 ", \"CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC\":%u"
 		 ", \"CONFIG_SYS_CLOCK_TICKS_PER_SEC\":%d"
 		 ", \"CONFIG_TIMER_TEST_PERIOD\":%d"
 		 ", \"CONFIG_TIMER_TEST_SAMPLES\":%d"
@@ -302,7 +304,7 @@ static void do_test_using(void (*sample_collection_fn)(void), const char *mechan
 		 expected_period,
 		 expected_period_drift,
 		 sys_clock_hw_cycles_per_sec(),
-		 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
+		 (uint32_t)CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
 		 CONFIG_SYS_CLOCK_TICKS_PER_SEC,
 		 CONFIG_TIMER_TEST_PERIOD,
 		 CONFIG_TIMER_TEST_SAMPLES,
@@ -333,7 +335,7 @@ static void do_test_using(void (*sample_collection_fn)(void), const char *mechan
 		     "Standard deviation (in microseconds) outside expected bound");
 
 	/* Validate the timer drift (accuracy over time) is within a configurable bound */
-	zassert_true(fabs(time_diff_us) < CONFIG_TIMER_TEST_MAX_DRIFT,
+	zassert_true(time_diff_us_abs < CONFIG_TIMER_TEST_MAX_DRIFT,
 		     "Drift (in microseconds) outside expected bound");
 }
 
diff --git a/tests/kernel/timer/timer_behavior/testcase.yaml b/tests/kernel/timer/timer_behavior/testcase.yaml
index 7e1b725ffba..5390494aad0 100644
--- a/tests/kernel/timer/timer_behavior/testcase.yaml
+++ b/tests/kernel/timer/timer_behavior/testcase.yaml
@@ -10,9 +10,13 @@ tests:
       - renode
     harness_config:
       record:
-        regex: "RECORD:(?P<metrics>.*)"
+        regex:
+          - "RECORD:(?P<metrics>.*)"
         as_json: ['metrics']
   kernel.timer.timer_behavior_external:
+    tags:
+      - kernel
+      - timer
     filter: dt_compat_enabled("test-kernel-timer-behavior-external")
     harness: pytest
     harness_config:
@@ -20,7 +24,8 @@ tests:
                     'address=127.0.0.1,port=10430,channel=1,sample-rate=6_250_000,threshold-volts=3.3']
       fixture: gpio_timerout
       record:
-        regex: "RECORD:(?P<metrics>.*)"
+        regex:
+          - "RECORD:(?P<metrics>.*)"
         as_json: ['metrics']
     extra_configs:
       - CONFIG_TIMER_EXTERNAL_TEST=y
diff --git a/tests/kernel/timer/timer_error_case/src/main.c b/tests/kernel/timer/timer_error_case/src/main.c
index e6ffe75330c..c0916fb4f41 100644
--- a/tests/kernel/timer/timer_error_case/src/main.c
+++ b/tests/kernel/timer/timer_error_case/src/main.c
@@ -325,8 +325,8 @@ ZTEST_USER(timer_api_error, test_timer_user_data_set_null)
 	k_thread_join(tid, K_FOREVER);
 }
 
-extern void z_add_timeout(struct _timeout *to, _timeout_func_t fn,
-			  k_timeout_t timeout);
+extern k_ticks_t z_add_timeout(struct _timeout *to, _timeout_func_t fn, k_timeout_t timeout);
+
 static void test_timer_handle(struct _timeout *t)
 {
 	/**do nothing here**/
diff --git a/tests/kernel/timer/timer_monotonic/src/main.c b/tests/kernel/timer/timer_monotonic/src/main.c
index baa4c762a6a..a1316ce2b79 100644
--- a/tests/kernel/timer/timer_monotonic/src/main.c
+++ b/tests/kernel/timer/timer_monotonic/src/main.c
@@ -58,7 +58,7 @@ ZTEST(timer_fn, test_timer)
 
 	TC_PRINT("k_ticks_to_cyc_floor32(1) = %d\n",
 		 k_ticks_to_cyc_floor32(1));
-	TC_PRINT("sys_clock_hw_cycles_per_sec() = %d\n",
+	TC_PRINT("sys_clock_hw_cycles_per_sec() = %u\n",
 		 sys_clock_hw_cycles_per_sec());
 
 	t_last = k_cycle_get_32();
diff --git a/tests/kernel/timer/timer_monotonic/testcase.yaml b/tests/kernel/timer/timer_monotonic/testcase.yaml
index 075f3009e8f..5780a5c8d19 100644
--- a/tests/kernel/timer/timer_monotonic/testcase.yaml
+++ b/tests/kernel/timer/timer_monotonic/testcase.yaml
@@ -3,9 +3,6 @@ tests:
     tags:
       - kernel
       - timer
-    # FIXME: This test may fail for qemu_arc/qemu_arc_hs on certain host systems.
-    #        See foss-for-synopsys-dwc-arc-processors/qemu#67.
-    platform_exclude: qemu_arc/qemu_arc_hs
   kernel.timer.monotonic.apic.tsc:
     tags:
       - kernel
diff --git a/tests/lib/c_lib/common/src/main.c b/tests/lib/c_lib/common/src/main.c
index 7a0e0dbd6b2..f5379d54584 100644
--- a/tests/lib/c_lib/common/src/main.c
+++ b/tests/lib/c_lib/common/src/main.c
@@ -22,6 +22,7 @@
 #include <zephyr/sys/__assert.h>
 #include <zephyr/sys/util.h>
 #include <zephyr/ztest.h>
+#include <zephyr/test_toolchain.h>
 
 #include <limits.h>
 #include <sys/types.h>
@@ -51,9 +52,7 @@
  * destination array).  That's exactly the case we're testing, so turn
  * it off.
  */
-#if defined(__GNUC__) && __GNUC__ >= 8
-#pragma GCC diagnostic ignored "-Wstringop-truncation"
-#endif
+TOOLCHAIN_DISABLE_GCC_WARNING(TOOLCHAIN_WARNING_STRINGOP_TRUNCATION)
 
 ZTEST_SUITE(libc_common, NULL, NULL, NULL, NULL, NULL);
 
@@ -66,17 +65,17 @@ volatile long long_max = LONG_MAX;
 volatile long long_one = 1L;
 
 /**
- *
  * @brief Test implementation-defined constants library
- * @defgroup libc_api
+ * @defgroup libc_api C Library APIs
  * @ingroup all_tests
  * @{
  *
  */
-
+/**
+ * @brief Test c library limits
+ */
 ZTEST(libc_common, test_limits)
 {
-
 	zassert_true((long_max + long_one == LONG_MIN));
 }
 
@@ -85,13 +84,15 @@ static ssize_t foobar(void)
 	return -1;
 }
 
+/**
+ * @brief Test C library ssize_t
+ */
 ZTEST(libc_common, test_ssize_t)
 {
 	zassert_true(foobar() < 0);
 }
 
 /**
- *
  * @brief Test boolean types and values library
  *
  */
@@ -111,7 +112,6 @@ volatile long long_variable;
 volatile size_t size_of_long_variable = sizeof(long_variable);
 
 /**
- *
  * @brief Test standard type definitions library
  *
  */
@@ -133,7 +133,6 @@ volatile uint8_t unsigned_byte = 0xff;
 volatile uint32_t unsigned_int = 0xffffff00;
 
 /**
- *
  * @brief Test integer types library
  *
  */
@@ -158,7 +157,6 @@ ZTEST(libc_common, test_stdint)
 }
 
 /**
- *
  * @brief Test time_t to make sure it is at least 64 bits
  *
  */
@@ -180,7 +178,6 @@ ZTEST(libc_common, test_time_t)
 char buffer[BUFSIZE];
 
 /**
- *
  * @brief Test string memset
  *
  */
@@ -200,7 +197,6 @@ ZTEST(libc_common, test_memset)
 }
 
 /**
- *
  * @brief Test string length function
  *
  * @see strlen(), strnlen().
@@ -217,7 +213,6 @@ ZTEST(libc_common, test_strlen)
 }
 
 /**
- *
  * @brief Test string compare function
  *
  * @see strcmp(), strncasecmp().
@@ -650,14 +645,9 @@ ZTEST(libc_common, test_str_operate)
 
 	zassert_true(strncat(ncat, str1, 2), "strncat failed");
 	zassert_not_null(strncat(str1, str3, 2), "strncat failed");
-#if defined(__GNUC__) && __GNUC__ >= 7
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wstringop-overflow"
-#endif
+	TOOLCHAIN_DISABLE_GCC_WARNING(TOOLCHAIN_WARNING_STRINGOP_OVERFLOW);
 	zassert_not_null(strncat(str1, str3, 1), "strncat failed");
-#if defined(__GNUC__) && __GNUC__ >= 7
-#pragma GCC diagnostic pop
-#endif
+	TOOLCHAIN_ENABLE_GCC_WARNING(TOOLCHAIN_WARNING_STRINGOP_OVERFLOW);
 	zassert_str_equal(ncat, "ddeeaa", "strncat failed");
 
 	zassert_is_null(strrchr(ncat, 'z'),
@@ -675,7 +665,7 @@ ZTEST(libc_common, test_str_operate)
  *
  * @brief test strtol function
  *
- * @detail   in 32bit system:
+ * @details   in 32bit system:
  *	when base is 10, [-2147483648..2147483647]
  *		   in 64bit system:
  *	when base is 10,
@@ -1336,3 +1326,6 @@ ZTEST(libc_common, test_exit)
 	zassert_equal(a, 0, "exit failed");
 #endif
 }
+/**
+ * @}
+ */
diff --git a/tests/lib/c_lib/thrd/src/cnd.c b/tests/lib/c_lib/thrd/src/cnd.c
index aaf00f9cb7b..82741e352bb 100644
--- a/tests/lib/c_lib/thrd/src/cnd.c
+++ b/tests/lib/c_lib/thrd/src/cnd.c
@@ -71,7 +71,7 @@ static int test_cnd_thread_fn(void *arg)
 	struct libc_cnd_fixture *const fixture = arg;
 
 	if (fixture->do_timedwait) {
-		zassume_ok(clock_gettime(CLOCK_MONOTONIC, &time_point));
+		zassume_ok(clock_gettime(CLOCK_REALTIME, &time_point));
 		timespec_add_ms(&time_point, WAIT_TIME_MS);
 		res = cnd_timedwait(&fixture->cond, &fixture->mutex, &time_point);
 	} else {
diff --git a/tests/lib/cmsis_dsp/common/test_common.h b/tests/lib/cmsis_dsp/common/test_common.h
index f65637ac93b..164fce7dd09 100644
--- a/tests/lib/cmsis_dsp/common/test_common.h
+++ b/tests/lib/cmsis_dsp/common/test_common.h
@@ -10,6 +10,7 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/kernel.h>
+#include <zephyr/test_toolchain.h>
 #include <stdlib.h>
 #include <arm_math.h>
 #ifdef CONFIG_CMSIS_DSP_FLOAT16
@@ -68,8 +69,7 @@
 		test_##name(a1, a2, a3, a4, a5, a6, a7);                                           \
 	}
 
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wunused-function"
+TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_UNUSED_FUNCTION)
 
 static inline bool test_equal_f64(
 	size_t length, const float64_t *a, const float64_t *b)
@@ -463,6 +463,6 @@ static inline bool test_snr_error_q7(
 	return (snr >= threshold);
 }
 
-#pragma GCC diagnostic pop
+TOOLCHAIN_ENABLE_WARNING(TOOLCHAIN_WARNING_UNUSED_FUNCTION)
 
 #endif /* ZEPHYR_TESTS_LIB_CMSIS_DSP_COMMON_TEST_COMMON_H_ */
diff --git a/tests/lib/cmsis_dsp/distance/src/f32.c b/tests/lib/cmsis_dsp/distance/src/f32.c
index 4b071f71bea..3311e77a815 100644
--- a/tests/lib/cmsis_dsp/distance/src/f32.c
+++ b/tests/lib/cmsis_dsp/distance/src/f32.c
@@ -54,7 +54,7 @@ static void test_arm_distance_f32(int op, bool scratchy, const uint16_t *dims,
 
 	/* Enumerate input */
 	for (index = 0; index < length; index++) {
-		float32_t val;
+		float32_t val = 0.0f;
 
 		/* Load input values into the scratch buffers */
 		if (scratchy) {
diff --git a/tests/lib/cmsis_dsp/distance/src/u32.c b/tests/lib/cmsis_dsp/distance/src/u32.c
index 921d35f53ba..de7bb417f37 100644
--- a/tests/lib/cmsis_dsp/distance/src/u32.c
+++ b/tests/lib/cmsis_dsp/distance/src/u32.c
@@ -44,7 +44,7 @@ static void test_arm_distance(int op, const uint16_t *dims,
 
 	/* Enumerate input */
 	for (index = 0; index < length; index++) {
-		float32_t val;
+		float32_t val = 0.0f;
 
 		/* Run test function */
 		switch (op) {
diff --git a/tests/lib/cmsis_dsp/filtering/testcase.yaml b/tests/lib/cmsis_dsp/filtering/testcase.yaml
index ad12446b991..6e82e863cca 100644
--- a/tests/lib/cmsis_dsp/filtering/testcase.yaml
+++ b/tests/lib/cmsis_dsp/filtering/testcase.yaml
@@ -8,7 +8,13 @@ tests:
     filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_FULL_LIBC_SUPPORTED
       ) or CONFIG_ARCH_POSIX
     tags: cmsis-dsp
-    skip: true
+    platform_allow:
+      - native_sim/native
+      - mps2/an385
+      - mps2/an521/cpu0
+      - qemu_cortex_r5/zynqmp_rpu
+    integration_platforms:
+      - mps2/an385
   libraries.cmsis_dsp.filtering.biquad:
     filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_FULL_LIBC_SUPPORTED
       ) or CONFIG_ARCH_POSIX
diff --git a/tests/lib/cmsis_dsp/matrix/testcase.yaml b/tests/lib/cmsis_dsp/matrix/testcase.yaml
index 63965b07974..380525a27cf 100644
--- a/tests/lib/cmsis_dsp/matrix/testcase.yaml
+++ b/tests/lib/cmsis_dsp/matrix/testcase.yaml
@@ -7,7 +7,13 @@ tests:
     filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_FULL_LIBC_SUPPORTED
       ) or CONFIG_ARCH_POSIX
     tags: cmsis-dsp
-    skip: true
+    platform_allow:
+      - mps2/an521/cpu0
+      - native_sim/native
+      - mps2/an385
+      - qemu_cortex_r5/zynqmp_rpu
+    integration_platforms:
+      - native_sim/native
   libraries.cmsis_dsp.matrix.unary_q7:
     filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_FULL_LIBC_SUPPORTED
       ) or CONFIG_ARCH_POSIX
diff --git a/tests/lib/cmsis_dsp/transform/src/cq15.c b/tests/lib/cmsis_dsp/transform/src/cq15.c
index 2b4d0292d58..57275961229 100644
--- a/tests/lib/cmsis_dsp/transform/src/cq15.c
+++ b/tests/lib/cmsis_dsp/transform/src/cq15.c
@@ -7,6 +7,7 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/kernel.h>
+#include <zephyr/test_toolchain.h>
 #include <stdlib.h>
 #include <arm_math.h>
 #include <arm_const_structs.h>
diff --git a/tests/lib/cmsis_dsp/transform/testcase.yaml b/tests/lib/cmsis_dsp/transform/testcase.yaml
index ecd4a67f8dd..9642509b31e 100644
--- a/tests/lib/cmsis_dsp/transform/testcase.yaml
+++ b/tests/lib/cmsis_dsp/transform/testcase.yaml
@@ -7,7 +7,13 @@ tests:
     filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_FULL_LIBC_SUPPORTED
       ) or CONFIG_ARCH_POSIX
     tags: cmsis-dsp
-    skip: true
+    platform_allow:
+      - mps2/an521/cpu0
+      - native_sim/native
+      - mps2/an385
+      - qemu_cortex_r5/zynqmp_rpu
+    integration_platforms:
+      - native_sim/native
   libraries.cmsis_dsp.transform.cq15:
     filter: ((CONFIG_CPU_AARCH32_CORTEX_R or CONFIG_CPU_CORTEX_M) and CONFIG_FULL_LIBC_SUPPORTED
       ) or CONFIG_ARCH_POSIX
diff --git a/tests/lib/cmsis_nn/src/main.c b/tests/lib/cmsis_nn/src/main.c
index c7dbe3bc58e..efe113b7ac7 100644
--- a/tests/lib/cmsis_nn/src/main.c
+++ b/tests/lib/cmsis_nn/src/main.c
@@ -203,6 +203,7 @@ ZTEST(cmsis_nn, test_convolve)
 					    kernel_data,
 					    &bias_dims,
 					    bias_data,
+					    NULL,
 					    &output_dims,
 					    output);
 
diff --git a/tests/lib/cobs/CMakeLists.txt b/tests/lib/cobs/CMakeLists.txt
new file mode 100644
index 00000000000..211ef76d5ee
--- /dev/null
+++ b/tests/lib/cobs/CMakeLists.txt
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(cobs)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/lib/cobs/prj.conf b/tests/lib/cobs/prj.conf
new file mode 100644
index 00000000000..3f2a19bc89b
--- /dev/null
+++ b/tests/lib/cobs/prj.conf
@@ -0,0 +1,2 @@
+CONFIG_COBS=y
+CONFIG_ZTEST=y
diff --git a/tests/lib/cobs/src/main.c b/tests/lib/cobs/src/main.c
new file mode 100644
index 00000000000..eda89c0454a
--- /dev/null
+++ b/tests/lib/cobs/src/main.c
@@ -0,0 +1,514 @@
+/*
+ * Copyright (c) 2024 Kelly Helmut Lord
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "zephyr/ztest_assert.h"
+#include <stdlib.h>
+#include <zephyr/ztest.h>
+#include <zephyr/data/cobs.h>
+
+#define TEST_BUF_SIZE  1024
+#define TEST_BUF_COUNT 3
+
+NET_BUF_POOL_DEFINE(test_pool, TEST_BUF_COUNT, TEST_BUF_SIZE, 0, NULL);
+
+struct cobs_tests_fixture {
+	struct net_buf *test_data;
+	struct net_buf *encoded;
+	struct net_buf *decoded;
+};
+
+static void *cobs_test_setup(void)
+{
+	struct cobs_tests_fixture *fixture = malloc(sizeof(struct cobs_tests_fixture));
+
+	zassume_not_null(fixture, NULL);
+
+	fixture->test_data = net_buf_alloc(&test_pool, K_NO_WAIT);
+	fixture->encoded = net_buf_alloc(&test_pool, K_NO_WAIT);
+	fixture->decoded = net_buf_alloc(&test_pool, K_NO_WAIT);
+
+	zassert_not_null(fixture->test_data, "Failed to allocate test_data buffer");
+	zassert_not_null(fixture->encoded, "Failed to allocate encoded buffer");
+	zassert_not_null(fixture->decoded, "Failed to allocate decoded buffer");
+
+	net_buf_reset(fixture->test_data);
+	net_buf_reset(fixture->encoded);
+	net_buf_reset(fixture->decoded);
+
+	return fixture;
+}
+
+static void cobs_test_before(void *f)
+{
+	struct cobs_tests_fixture *fixture = (struct cobs_tests_fixture *)f;
+
+	net_buf_reset(fixture->test_data);
+	net_buf_reset(fixture->encoded);
+	net_buf_reset(fixture->decoded);
+}
+
+static void cobs_test_teardown(void *f)
+{
+	struct cobs_tests_fixture *fixture = (struct cobs_tests_fixture *)f;
+
+	if (fixture->test_data) {
+		net_buf_unref(fixture->test_data);
+	}
+	if (fixture->encoded) {
+		net_buf_unref(fixture->encoded);
+	}
+	if (fixture->decoded) {
+		net_buf_unref(fixture->decoded);
+	}
+
+	free(fixture);
+}
+
+struct cobs_test_item {
+	const char *name;
+	const uint8_t *decoded;
+	size_t decoded_len;
+	const uint8_t *encoded;
+	size_t encoded_len;
+	uint8_t delimiter;
+};
+
+#define U8(...) (uint8_t[]) __VA_ARGS__
+
+#define COBS_ITEM(d, e, del, n)                                                                    \
+	{.name = n,                                                                                \
+	 .decoded = d,                                                                             \
+	 .decoded_len = sizeof(d),                                                                 \
+	 .encoded = e,                                                                             \
+	 .encoded_len = sizeof(e),                                                                 \
+	 .delimiter = del}
+
+static const struct cobs_test_item cobs_dataset[] = {
+	COBS_ITEM(U8({}), U8({0x01}), COBS_DEFAULT_DELIMITER, "Empty"),
+	COBS_ITEM(U8({'1'}), U8({0x02, '1'}), COBS_DEFAULT_DELIMITER, "One char"),
+	COBS_ITEM(U8({0x00}), U8({0x01, 0x01}), COBS_DEFAULT_DELIMITER, "One zero"),
+	COBS_ITEM(U8({0x00, 0x00}), U8({0x01, 0x01, 0x01}), COBS_DEFAULT_DELIMITER, "Two zeroes"),
+	COBS_ITEM(U8({0x00, 0x00, 0x00}), U8({0x01, 0x01, 0x01, 0x01}), COBS_DEFAULT_DELIMITER,
+		  "Three zeroes"),
+	COBS_ITEM(U8({'1', '2', '3', '4', '5'}), U8({0x06, '1', '2', '3', '4', '5'}),
+		  COBS_DEFAULT_DELIMITER, "Five chars"),
+	COBS_ITEM(U8({'1', '2', '3', '4', '5', 0x00, '6', '7', '8', '9'}),
+		  U8({0x06, '1', '2', '3', '4', '5', 0x05, '6', '7', '8', '9'}),
+		  COBS_DEFAULT_DELIMITER, "Embedded zero"),
+	COBS_ITEM(U8({0x00, '1', '2', '3', '4', '5', 0x00, '6', '7', '8', '9'}),
+		  U8({0x01, 0x06, '1', '2', '3', '4', '5', 0x05, '6', '7', '8', '9'}),
+		  COBS_DEFAULT_DELIMITER, "Starting zero"),
+	COBS_ITEM(U8({'1', '2', '3', '4', '5', 0x00, '6', '7', '8', '9', 0x00}),
+		  U8({0x06, '1', '2', '3', '4', '5', 0x05, '6', '7', '8', '9', 0x01}),
+		  COBS_DEFAULT_DELIMITER, "Trailing zero"),
+	COBS_ITEM(U8({}), U8({0x01}), 0x7F, "Empty with custom delimiter 0x7F"),
+	COBS_ITEM(U8({'1'}), U8({0x02, '1'}), 0x7F, "One char with custom delimiter 0x7F"),
+	COBS_ITEM(U8({0x7F}), U8({0x01, 0x01}), 0x7F, "One 0x7F delimiter"),
+	COBS_ITEM(U8({0x7F, 0x7F}), U8({0x01, 0x01, 0x01}), 0x7F, "Two 0x7F delimiters"),
+	COBS_ITEM(U8({0x7F, 0x7F, 0x7F}), U8({0x01, 0x01, 0x01, 0x01}), 0x7F,
+		  "Three 0x7F delimiters"),
+	COBS_ITEM(
+		U8({'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F',
+		    'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b',
+		    'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r',
+		    's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D',
+		    'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T',
+		    'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p',
+		    'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B',
+		    'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R',
+		    'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n',
+		    'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
+		    'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P',
+		    'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l',
+		    'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7',
+		    '8', '9', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N',
+		    'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j',
+		    'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '1', '2', '3'}),
+		U8({0xfe, '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E',
+		    'F',  'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'a',
+		    'b',  'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q',
+		    'r',  's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C',
+		    'D',  'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S',
+		    'T',  'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
+		    'p',  'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A',
+		    'B',  'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q',
+		    'R',  'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm',
+		    'n',  'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8',
+		    '9',  'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
+		    'P',  'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k',
+		    'l',  'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6',
+		    '7',  '8', '9', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M',
+		    'N',  'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i',
+		    'j',  'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '1', '2', '3'}),
+		COBS_DEFAULT_DELIMITER, "253 Chars"),
+	COBS_ITEM(
+		U8({'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F',
+		    'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b',
+		    'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r',
+		    's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D',
+		    'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T',
+		    'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p',
+		    'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B',
+		    'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R',
+		    'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n',
+		    'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
+		    'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P',
+		    'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l',
+		    'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7',
+		    '8', '9', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N',
+		    'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j',
+		    'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '1', '2', '3', '4'}),
+		U8({0xff, '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E',
+		    'F',  'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'a',
+		    'b',  'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q',
+		    'r',  's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C',
+		    'D',  'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S',
+		    'T',  'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
+		    'p',  'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A',
+		    'B',  'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q',
+		    'R',  'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm',
+		    'n',  'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8',
+		    '9',  'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
+		    'P',  'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k',
+		    'l',  'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6',
+		    '7',  '8', '9', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M',
+		    'N',  'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i',
+		    'j',  'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '1', '2', '3', '4'}),
+		COBS_DEFAULT_DELIMITER, "254 Chars"),
+	COBS_ITEM(
+		U8({'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F',
+		    'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b',
+		    'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r',
+		    's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D',
+		    'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T',
+		    'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p',
+		    'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B',
+		    'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R',
+		    'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n',
+		    'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
+		    'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P',
+		    'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l',
+		    'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7',
+		    '8', '9', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N',
+		    'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j',
+		    'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '1', '2', '3', '4', '5'}),
+		U8({0xff, '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D',
+		    'E',  'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S',
+		    'T',  'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n',
+		    'o',  'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8',
+		    '9',  'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N',
+		    'O',  'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i',
+		    'j',  'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3',
+		    '4',  '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I',
+		    'J',  'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd',
+		    'e',  'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's',
+		    't',  '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D',
+		    'E',  'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S',
+		    'T',  'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n',
+		    'o',  'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8',
+		    '9',  'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N',
+		    'O',  'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i',
+		    'j',  'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '1', '2', '3', '4',
+		    0x02, '5'}),
+		COBS_DEFAULT_DELIMITER, "255 Chars"),
+	COBS_ITEM(U8({0x00, '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D',
+		      'E',  'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S',
+		      'T',  'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n',
+		      'o',  'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8',
+		      '9',  'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N',
+		      'O',  'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i',
+		      'j',  'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3',
+		      '4',  '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I',
+		      'J',  'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd',
+		      'e',  'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's',
+		      't',  '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D',
+		      'E',  'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S',
+		      'T',  'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n',
+		      'o',  'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8',
+		      '9',  'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N',
+		      'O',  'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i',
+		      'j',  'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '1', '2', '3', '4',
+		      '5'}),
+		  U8({0x01, 0xff, '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C',
+		      'D',  'E',  'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R',
+		      'S',  'T',  'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm',
+		      'n',  'o',  'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7',
+		      '8',  '9',  'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M',
+		      'N',  'O',  'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h',
+		      'i',  'j',  'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '0', '1', '2',
+		      '3',  '4',  '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H',
+		      'I',  'J',  'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c',
+		      'd',  'e',  'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r',
+		      's',  't',  '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C',
+		      'D',  'E',  'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R',
+		      'S',  'T',  'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm',
+		      'n',  'o',  'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7',
+		      '8',  '9',  'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M',
+		      'N',  'O',  'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h',
+		      'i',  'j',  'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '1', '2', '3',
+		      '4',  0x02, '5'}),
+		  COBS_DEFAULT_DELIMITER, "Leading zero 255 chars"),
+	COBS_ITEM(
+		U8({'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F',
+		    'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b',
+		    'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r',
+		    's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D',
+		    'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T',
+		    'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p',
+		    'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B',
+		    'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R',
+		    'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n',
+		    'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
+		    'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P',
+		    'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l',
+		    'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7',
+		    '8', '9', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N',
+		    'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j',
+		    'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '1', '2', '3', 0x00}),
+		U8({0xfe, '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E',
+		    'F',  'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'a',
+		    'b',  'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q',
+		    'r',  's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C',
+		    'D',  'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S',
+		    'T',  'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
+		    'p',  'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A',
+		    'B',  'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q',
+		    'R',  'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm',
+		    'n',  'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8',
+		    '9',  'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
+		    'P',  'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k',
+		    'l',  'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6',
+		    '7',  '8', '9', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M',
+		    'N',  'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i',
+		    'j',  'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '1', '2', '3', 0x01}),
+		COBS_DEFAULT_DELIMITER, "Ending zero 253 chars"),
+	COBS_ITEM(
+		U8({'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F',
+		    'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b',
+		    'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r',
+		    's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D',
+		    'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T',
+		    'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p',
+		    'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B',
+		    'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R',
+		    'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n',
+		    'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
+		    'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P',
+		    'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l',
+		    'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7',
+		    '8', '9', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N',
+		    'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j',
+		    'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '1', '2', '3', '4', 0x00}),
+		U8({0xff, '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D',
+		    'E',  'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S',
+		    'T',  'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n',
+		    'o',  'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8',
+		    '9',  'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N',
+		    'O',  'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i',
+		    'j',  'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3',
+		    '4',  '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I',
+		    'J',  'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd',
+		    'e',  'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's',
+		    't',  '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D',
+		    'E',  'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S',
+		    'T',  'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n',
+		    'o',  'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8',
+		    '9',  'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N',
+		    'O',  'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i',
+		    'j',  'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '1', '2', '3', '4',
+		    0x01, 0x01}),
+		COBS_DEFAULT_DELIMITER, "Ending zero 254 chars"),
+	COBS_ITEM(U8({'0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E',
+		      'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T',
+		      'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
+		      'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
+		      'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
+		      'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j',
+		      'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4',
+		      '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J',
+		      'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e',
+		      'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't',
+		      '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E',
+		      'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T',
+		      'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
+		      'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8', '9',
+		      'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
+		      'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j',
+		      'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '1', '2', '3', '4', '5',
+		      0x00}),
+		  U8({0xff, '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D',
+		      'E',  'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S',
+		      'T',  'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n',
+		      'o',  'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8',
+		      '9',  'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N',
+		      'O',  'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i',
+		      'j',  'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '0', '1', '2', '3',
+		      '4',  '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I',
+		      'J',  'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd',
+		      'e',  'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's',
+		      't',  '0', '1', '2', '3', '4', '5', '6', '7', '8', '9', 'A', 'B', 'C', 'D',
+		      'E',  'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P', 'Q', 'R', 'S',
+		      'T',  'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n',
+		      'o',  'p', 'q', 'r', 's', 't', '0', '1', '2', '3', '4', '5', '6', '7', '8',
+		      '9',  'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H', 'I', 'J', 'K', 'L', 'M', 'N',
+		      'O',  'P', 'Q', 'R', 'S', 'T', 'a', 'b', 'c', 'd', 'e', 'f', 'g', 'h', 'i',
+		      'j',  'k', 'l', 'm', 'n', 'o', 'p', 'q', 'r', 's', 't', '1', '2', '3', '4',
+		      0x02, '5', 0x01}),
+		  COBS_DEFAULT_DELIMITER, "Ending zero 255 chars"),
+};
+
+ZTEST_SUITE(cobs_tests, NULL, cobs_test_setup, cobs_test_before, NULL, cobs_test_teardown);
+
+ZTEST_F(cobs_tests, test_encode)
+{
+	int ret;
+
+	ARRAY_FOR_EACH(cobs_dataset, idx) {
+		uint8_t delimiter = cobs_dataset[idx].delimiter;
+
+		net_buf_add_mem(fixture->test_data, cobs_dataset[idx].decoded,
+				cobs_dataset[idx].decoded_len);
+
+		ret = cobs_encode(fixture->test_data, fixture->encoded,
+				  COBS_FLAG_CUSTOM_DELIMITER(delimiter));
+		zassert_ok(ret, "COBS encoding failed for %s", cobs_dataset[idx].name);
+		zassert_equal(cobs_dataset[idx].encoded_len, fixture->encoded->len,
+			      "Encoded length does not match expected for %s",
+			      cobs_dataset[idx].name);
+		zassert_mem_equal(cobs_dataset[idx].encoded, fixture->encoded->data,
+				  cobs_dataset[idx].encoded_len,
+				  "Encoded data does not match expected for %s",
+				  cobs_dataset[idx].name);
+
+		zassert_equal(fixture->test_data->len, 0, "Encode input not empty for %s",
+			      cobs_dataset[idx].name);
+		net_buf_reset(fixture->test_data);
+		net_buf_reset(fixture->encoded);
+		net_buf_reset(fixture->decoded);
+	}
+}
+
+ZTEST_F(cobs_tests, test_decode)
+{
+	int ret;
+
+	ARRAY_FOR_EACH(cobs_dataset, idx) {
+		uint8_t delimiter = cobs_dataset[idx].delimiter;
+
+		net_buf_add_mem(fixture->test_data, cobs_dataset[idx].decoded,
+				cobs_dataset[idx].decoded_len);
+
+		ret = cobs_decode(fixture->encoded, fixture->test_data,
+				  COBS_FLAG_CUSTOM_DELIMITER(delimiter));
+		zassert_ok(ret, "COBS decoding failed for %s", cobs_dataset[idx].name);
+		zassert_equal(cobs_dataset[idx].decoded_len, fixture->test_data->len,
+			      "Decoded length does not match expected for %s",
+			      cobs_dataset[idx].name);
+		zassert_mem_equal(cobs_dataset[idx].decoded, fixture->test_data->data,
+				  cobs_dataset[idx].decoded_len,
+				  "Decoded data does not match expected for %s",
+				  cobs_dataset[idx].name);
+
+		zassert_equal(fixture->encoded->len, 0, "Decode input not empty for %s",
+			      cobs_dataset[idx].name);
+		net_buf_reset(fixture->test_data);
+		net_buf_reset(fixture->encoded);
+		net_buf_reset(fixture->decoded);
+	}
+}
+
+ZTEST_F(cobs_tests, test_encode_trailing_delimiter)
+{
+	int ret;
+
+	ARRAY_FOR_EACH(cobs_dataset, idx) {
+		uint8_t delimiter = cobs_dataset[idx].delimiter;
+
+		net_buf_add_mem(fixture->test_data, cobs_dataset[idx].decoded,
+				cobs_dataset[idx].decoded_len);
+
+		ret = cobs_encode(fixture->test_data, fixture->encoded,
+				  COBS_FLAG_TRAILING_DELIMITER |
+					  COBS_FLAG_CUSTOM_DELIMITER(delimiter));
+		zassert_ok(ret, "COBS encoding failed for %s", cobs_dataset[idx].name);
+		zassert_equal(cobs_dataset[idx].encoded_len + 1, fixture->encoded->len,
+			      "Encoded length does not match expected for %s",
+			      cobs_dataset[idx].name);
+		zassert_mem_equal(cobs_dataset[idx].encoded, fixture->encoded->data,
+				  cobs_dataset[idx].encoded_len,
+				  "Encoded data does not match expected for %s",
+				  cobs_dataset[idx].name);
+
+		zassert_equal(fixture->encoded->data[cobs_dataset[idx].encoded_len], delimiter,
+			      "Encoded data does not have proper trailing delimiter");
+
+		zassert_equal(fixture->test_data->len, 0, "Encode input not empty for %s",
+			      cobs_dataset[idx].name);
+		net_buf_reset(fixture->test_data);
+		net_buf_reset(fixture->encoded);
+		net_buf_reset(fixture->decoded);
+	}
+}
+
+ZTEST_F(cobs_tests, test_decode_trailing_delimiter)
+{
+	int ret;
+
+	ARRAY_FOR_EACH(cobs_dataset, idx) {
+		uint8_t delimiter = cobs_dataset[idx].delimiter;
+
+		net_buf_add_mem(fixture->test_data, cobs_dataset[idx].decoded,
+				cobs_dataset[idx].decoded_len);
+
+		net_buf_add_u8(fixture->encoded, delimiter);
+
+		ret = cobs_decode(fixture->encoded, fixture->test_data,
+				  COBS_FLAG_TRAILING_DELIMITER |
+					  COBS_FLAG_CUSTOM_DELIMITER(delimiter));
+		zassert_ok(ret, "COBS decoding failed for %s", cobs_dataset[idx].name);
+		zassert_equal(cobs_dataset[idx].decoded_len, fixture->test_data->len,
+			      "Decoded length does not match expected for %s",
+			      cobs_dataset[idx].name);
+		zassert_mem_equal(cobs_dataset[idx].decoded, fixture->test_data->data,
+				  cobs_dataset[idx].decoded_len,
+				  "Decoded data does not match expected for %s",
+				  cobs_dataset[idx].name);
+
+		zassert_equal(fixture->encoded->len, 0, "Decode input not empty for %s",
+			      cobs_dataset[idx].name);
+		net_buf_reset(fixture->test_data);
+		net_buf_reset(fixture->encoded);
+		net_buf_reset(fixture->decoded);
+	}
+}
+
+ZTEST_F(cobs_tests, test_cobs_invalid_delim_pos)
+{
+	int ret;
+	const char data_enc[] = {0x02, 0x00, 0x01};
+
+	net_buf_add_mem(fixture->encoded, data_enc, sizeof(data_enc));
+	ret = cobs_decode(fixture->encoded, fixture->decoded, 0);
+	zassert_true(ret == -EINVAL, "Decoding invalid delimiter caught");
+}
+
+ZTEST_F(cobs_tests, test_cobs_consecutive_delims)
+{
+	int ret;
+	const char data_enc[] = {0x01, 0x00, 0x00, 0x01};
+
+	net_buf_add_mem(fixture->encoded, data_enc, sizeof(data_enc));
+	ret = cobs_decode(fixture->encoded, fixture->decoded, 0);
+	zassert_true(ret == -EINVAL, "Decoding consecutive delimiters not caught");
+}
+
+ZTEST_F(cobs_tests, test_cobs_invalid_overrun)
+{
+	int ret;
+	const char data_enc[] = {0x03, 0x01};
+
+	net_buf_add_mem(fixture->encoded, data_enc, sizeof(data_enc));
+	ret = cobs_decode(fixture->encoded, fixture->decoded, 0);
+	zassert_true(ret == -EINVAL, "Decoding insufficient data not caught");
+}
diff --git a/tests/lib/cobs/testcase.yaml b/tests/lib/cobs/testcase.yaml
new file mode 100644
index 00000000000..71b07601d10
--- /dev/null
+++ b/tests/lib/cobs/testcase.yaml
@@ -0,0 +1,6 @@
+tests:
+  libraries.encoding.cobs:
+    min_flash: 32
+    tags: cobs
+    integration_platforms:
+      - native_sim
diff --git a/tests/lib/cpp/cxx/src/main.cpp b/tests/lib/cpp/cxx/src/main.cpp
index d2704e0d992..71e1c1e3ab7 100644
--- a/tests/lib/cpp/cxx/src/main.cpp
+++ b/tests/lib/cpp/cxx/src/main.cpp
@@ -50,7 +50,6 @@
 #include <zephyr/drivers/i2s.h>
 #include <zephyr/drivers/i3c.h>
 #include <zephyr/drivers/ipm.h>
-#include <zephyr/drivers/kscan.h>
 #include <zephyr/drivers/led.h>
 #include <zephyr/drivers/led_strip.h>
 #include <zephyr/drivers/lora.h>
diff --git a/tests/lib/cpp/cxx/testcase.yaml b/tests/lib/cpp/cxx/testcase.yaml
index eaacc89e2da..a19802928c8 100644
--- a/tests/lib/cpp/cxx/testcase.yaml
+++ b/tests/lib/cpp/cxx/testcase.yaml
@@ -38,7 +38,9 @@ tests:
     # compatible with C++98.
     # Exclude CONFIG_HAS_RENESAS_RA_FSP and CONFIG_HAS_RENESAS_RZ_FSP as Renesas HALs are not
     # compatible with C++98.
+    # Exclude CONFIG_HAS_SILABS_WISECONNECT as Wiseconnect is not compatible with C++98.
     filter: not CONFIG_HAS_RENESAS_RA_FSP and not CONFIG_HAS_RENESAS_RZ_FSP and
+            not CONFIG_HAS_SILABS_WISECONNECT and
             not (CONFIG_CPU_CORTEX_M and (CONFIG_NRF_PLATFORM_HALTIUM or CONFIG_SOC_SERIES_NRF54LX))
     build_only: true
     extra_configs:
diff --git a/tests/lib/devicetree/api/src/main.c b/tests/lib/devicetree/api/src/main.c
index b23cf116c55..5b671a70fc2 100644
--- a/tests/lib/devicetree/api/src/main.c
+++ b/tests/lib/devicetree/api/src/main.c
@@ -7,9 +7,7 @@
 #include <zephyr/ztest.h>
 #include <zephyr/devicetree.h>
 #include <zephyr/device.h>
-#include <zephyr/drivers/adc.h>
 #include <zephyr/drivers/gpio.h>
-#include <zephyr/drivers/mbox.h>
 
 #include <stdlib.h>
 
@@ -338,6 +336,16 @@ ZTEST(devicetree_api, test_has_alias)
 	zassert_equal(DT_NODE_HAS_STATUS(DT_ALIAS(test_undef), okay), 0, "");
 }
 
+ZTEST(devicetree_api, test_node_hashes)
+{
+	zassert_str_equal(TO_STRING(DT_NODE_HASH(DT_ROOT)),
+			  "il7asoJjJEMhngUeSt4tHVu8Zxx4EFG_FDeJfL3_oPE");
+	zassert_str_equal(TO_STRING(DT_NODE_HASH(TEST_DEADBEEF)),
+			  "kPPqtBX5DX_QDQMO0_cOls2ebJMevAWHhAPY1JCKTyU");
+	zassert_str_equal(TO_STRING(DT_NODE_HASH(TEST_ABCD1234)),
+			  "Bk4fvF6o3Mgslz_xiIZaJcuwo6_IeelozwOaxtUsSos");
+}
+
 ZTEST(devicetree_api, test_inst_checks)
 {
 	zassert_equal(DT_NODE_EXISTS(DT_INST(0, vnd_gpio_device)), 1, "");
@@ -1247,27 +1255,6 @@ ZTEST(devicetree_api, test_io_channels)
 	zassert_equal(DT_INST_IO_CHANNELS_INPUT(0), 10, "");
 }
 
-#undef DT_DRV_COMPAT
-#define DT_DRV_COMPAT vnd_adc_temp_sensor
-ZTEST(devicetree_api, test_io_channel_names)
-{
-	struct adc_dt_spec adc_spec;
-
-	/* ADC_DT_SPEC_GET_BY_NAME */
-	adc_spec = (struct adc_dt_spec)ADC_DT_SPEC_GET_BY_NAME(TEST_TEMP, ch1);
-	zassert_equal(adc_spec.channel_id, 10, "");
-
-	adc_spec = (struct adc_dt_spec)ADC_DT_SPEC_GET_BY_NAME(TEST_TEMP, ch2);
-	zassert_equal(adc_spec.channel_id, 20, "");
-
-	/* ADC_DT_SPEC_INST_GET_BY_NAME */
-	adc_spec = (struct adc_dt_spec)ADC_DT_SPEC_INST_GET_BY_NAME(0, ch1);
-	zassert_equal(adc_spec.channel_id, 10, "");
-
-	adc_spec = (struct adc_dt_spec)ADC_DT_SPEC_INST_GET_BY_NAME(0, ch2);
-	zassert_equal(adc_spec.channel_id, 20, "");
-}
-
 #undef DT_DRV_COMPAT
 #define DT_DRV_COMPAT vnd_adc_temp_sensor
 ZTEST(devicetree_api, test_dma)
@@ -3085,22 +3072,8 @@ ZTEST(devicetree_api, test_pinctrl)
 	zassert_equal(DT_INST_PINCTRL_HAS_NAME(0, f_o_o2), 0, "");
 }
 
-DEVICE_DT_DEFINE(DT_NODELABEL(test_mbox), NULL, NULL, NULL, NULL, POST_KERNEL,
-		 90, NULL);
-DEVICE_DT_DEFINE(DT_NODELABEL(test_mbox_zero_cell), NULL, NULL, NULL, NULL,
-		 POST_KERNEL, 90, NULL);
-
 ZTEST(devicetree_api, test_mbox)
 {
-#undef DT_DRV_COMPAT
-#define DT_DRV_COMPAT vnd_adc_temp_sensor
-
-	const struct mbox_dt_spec channel_tx = MBOX_DT_SPEC_GET(TEST_TEMP, tx);
-	const struct mbox_dt_spec channel_rx = MBOX_DT_SPEC_GET(TEST_TEMP, rx);
-
-	zassert_equal(channel_tx.channel_id, 1, "");
-	zassert_equal(channel_rx.channel_id, 2, "");
-
 	zassert_equal(DT_MBOX_CHANNEL_BY_NAME(TEST_TEMP, tx), 1, "");
 	zassert_equal(DT_MBOX_CHANNEL_BY_NAME(TEST_TEMP, rx), 2, "");
 
@@ -3112,10 +3085,6 @@ ZTEST(devicetree_api, test_mbox)
 	zassert_equal(DT_MBOX_CHANNEL_BY_NAME(TEST_TEMP, tx), 1, "");
 	zassert_equal(DT_MBOX_CHANNEL_BY_NAME(TEST_TEMP, rx), 2, "");
 
-	const struct mbox_dt_spec channel_zero = MBOX_DT_SPEC_GET(TEST_TEMP, zero);
-
-	zassert_equal(channel_zero.channel_id, 0, "");
-
 	zassert_equal(DT_MBOX_CHANNEL_BY_NAME(TEST_TEMP, zero), 0, "");
 
 	zassert_true(DT_SAME_NODE(DT_MBOX_CTLR_BY_NAME(TEST_TEMP, zero),
diff --git a/tests/lib/devicetree/api_ext/app.overlay b/tests/lib/devicetree/api_ext/app.overlay
index 22a6e9ee8c5..5f20b5cbbf9 100644
--- a/tests/lib/devicetree/api_ext/app.overlay
+++ b/tests/lib/devicetree/api_ext/app.overlay
@@ -26,5 +26,53 @@
 			reg = < 0x20001000 0x1000 >;
 			zephyr,memory-region = "SRAM@REGION#2";
 		};
+
+		test_fixed_clk: test-fixed-clock {
+			compatible = "fixed-clock";
+			clock-frequency = <25000000>;
+			#clock-cells = <0>;
+		};
+
+		test_clk: test-clock {
+			compatible = "vnd,clock";
+			#clock-cells = <2>;
+		};
+
+		test_adc_1: adc@10002000 {
+			reg = <0x10002000 0x1000>;
+			compatible = "vnd,adc";
+			status = "okay";
+			#io-channel-cells = <1>;
+		};
+
+		test_adc_2: adc@10003000 {
+			reg = <0x10003000 0x1000>;
+			compatible = "vnd,adc";
+			status = "okay";
+			#io-channel-cells = <1>;
+		};
+
+		test_mbox: mbox {
+			compatible = "vnd,mbox";
+			#mbox-cells = <1>;
+			status = "okay";
+		};
+
+		test_mbox_zero_cell: mbox_zero_cell {
+			compatible = "vnd,mbox-zero-cell";
+			#mbox-cells = <0>;
+			status = "okay";
+		};
+
+		/* there should only be one of these */
+		test_temp_sensor: temperature-sensor {
+			compatible = "vnd,adc-temp-sensor";
+			clocks = <&test_clk 3 7>, <&test_fixed_clk>, <&test_clk 8 2>;
+			clock-names = "clk-a", "clk-fixed", "clk-b";
+			io-channels = <&test_adc_1 10>, <&test_adc_2 20>;
+			io-channel-names = "ch1", "ch2";
+			mboxes = <&test_mbox 1>, <&test_mbox 2>, <&test_mbox_zero_cell>;
+			mbox-names = "tx", "rx", "zero";
+		};
 	};
 };
diff --git a/tests/lib/devicetree/api_ext/prj.conf b/tests/lib/devicetree/api_ext/prj.conf
index 9467c292689..80789f1bf70 100644
--- a/tests/lib/devicetree/api_ext/prj.conf
+++ b/tests/lib/devicetree/api_ext/prj.conf
@@ -1 +1,3 @@
 CONFIG_ZTEST=y
+CONFIG_ADC=y
+CONFIG_MBOX=y
diff --git a/tests/lib/devicetree/api_ext/src/main.c b/tests/lib/devicetree/api_ext/src/main.c
index f865cd268db..d3f742990d5 100644
--- a/tests/lib/devicetree/api_ext/src/main.c
+++ b/tests/lib/devicetree/api_ext/src/main.c
@@ -8,11 +8,15 @@
 #include <zephyr/ztest.h>
 #include <zephyr/devicetree.h>
 #include <zephyr/device.h>
+#include <zephyr/drivers/gpio.h>
+#include <zephyr/drivers/adc.h>
+#include <zephyr/drivers/mbox.h>
 
 #include <zephyr/linker/devicetree_regions.h>
 
-#define TEST_SRAM1      DT_NODELABEL(test_sram1)
-#define TEST_SRAM2      DT_NODELABEL(test_sram2)
+#define TEST_SRAM1 DT_NODELABEL(test_sram1)
+#define TEST_SRAM2 DT_NODELABEL(test_sram2)
+#define TEST_TEMP  DT_NODELABEL(test_temp_sensor)
 
 ZTEST(devicetree_api_ext, test_linker_regions)
 {
@@ -20,4 +24,39 @@ ZTEST(devicetree_api_ext, test_linker_regions)
 	zassert_true(!strcmp(LINKER_DT_NODE_REGION_NAME(TEST_SRAM2), "SRAM_REGION_2"), "");
 }
 
+#define DT_DRV_COMPAT vnd_adc_temp_sensor
+ZTEST(devicetree_api_ext, test_adc_dt_spec)
+{
+	struct adc_dt_spec adc_spec;
+
+	/* ADC_DT_SPEC_GET_BY_NAME */
+	adc_spec = (struct adc_dt_spec)ADC_DT_SPEC_GET_BY_NAME(TEST_TEMP, ch1);
+	zassert_equal(adc_spec.channel_id, 10, "");
+
+	adc_spec = (struct adc_dt_spec)ADC_DT_SPEC_GET_BY_NAME(TEST_TEMP, ch2);
+	zassert_equal(adc_spec.channel_id, 20, "");
+
+	/* ADC_DT_SPEC_INST_GET_BY_NAME */
+	adc_spec = (struct adc_dt_spec)ADC_DT_SPEC_INST_GET_BY_NAME(0, ch1);
+	zassert_equal(adc_spec.channel_id, 10, "");
+
+	adc_spec = (struct adc_dt_spec)ADC_DT_SPEC_INST_GET_BY_NAME(0, ch2);
+	zassert_equal(adc_spec.channel_id, 20, "");
+}
+
+DEVICE_DT_DEFINE(DT_NODELABEL(test_mbox), NULL, NULL, NULL, NULL, POST_KERNEL, 90, NULL);
+DEVICE_DT_DEFINE(DT_NODELABEL(test_mbox_zero_cell), NULL, NULL, NULL, NULL, POST_KERNEL, 90, NULL);
+ZTEST(devicetree_api_ext, test_mbox_dt_spec)
+{
+	const struct mbox_dt_spec channel_tx = MBOX_DT_SPEC_GET(TEST_TEMP, tx);
+	const struct mbox_dt_spec channel_rx = MBOX_DT_SPEC_GET(TEST_TEMP, rx);
+
+	zassert_equal(channel_tx.channel_id, 1, "");
+	zassert_equal(channel_rx.channel_id, 2, "");
+
+	const struct mbox_dt_spec channel_zero = MBOX_DT_SPEC_GET(TEST_TEMP, zero);
+
+	zassert_equal(channel_zero.channel_id, 0, "");
+}
+
 ZTEST_SUITE(devicetree_api_ext, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/lib/devicetree/devices/src/main.c b/tests/lib/devicetree/devices/src/main.c
index 0c9cf699406..291a4a47850 100644
--- a/tests/lib/devicetree/devices/src/main.c
+++ b/tests/lib/devicetree/devices/src/main.c
@@ -86,16 +86,16 @@ ZTEST(devicetree_devices, test_init_get)
 		      DEVICE_DT_GET(TEST_NOLABEL), NULL);
 
 	/* Check init functions */
-	zassert_equal(DEVICE_INIT_DT_GET(TEST_GPIO)->init_fn.dev, dev_init);
-	zassert_equal(DEVICE_INIT_DT_GET(TEST_I2C)->init_fn.dev, dev_init);
-	zassert_equal(DEVICE_INIT_DT_GET(TEST_DEVA)->init_fn.dev, dev_init);
-	zassert_equal(DEVICE_INIT_DT_GET(TEST_DEVB)->init_fn.dev, dev_init);
-	zassert_equal(DEVICE_INIT_DT_GET(TEST_GPIOX)->init_fn.dev, dev_init);
-	zassert_equal(DEVICE_INIT_DT_GET(TEST_DEVC)->init_fn.dev, dev_init);
-	zassert_equal(DEVICE_INIT_DT_GET(TEST_PARTITION)->init_fn.dev, dev_init);
-	zassert_equal(DEVICE_INIT_DT_GET(TEST_GPIO_INJECTED)->init_fn.dev, dev_init);
-	zassert_equal(DEVICE_INIT_GET(manual_dev)->init_fn.dev, dev_init);
-	zassert_equal(DEVICE_INIT_DT_GET(TEST_NOLABEL)->init_fn.dev, dev_init);
+	zassert_equal(DEVICE_DT_GET(TEST_GPIO)->ops.init, dev_init);
+	zassert_equal(DEVICE_DT_GET(TEST_I2C)->ops.init, dev_init);
+	zassert_equal(DEVICE_DT_GET(TEST_DEVA)->ops.init, dev_init);
+	zassert_equal(DEVICE_DT_GET(TEST_DEVB)->ops.init, dev_init);
+	zassert_equal(DEVICE_DT_GET(TEST_GPIOX)->ops.init, dev_init);
+	zassert_equal(DEVICE_DT_GET(TEST_DEVC)->ops.init, dev_init);
+	zassert_equal(DEVICE_DT_GET(TEST_PARTITION)->ops.init, dev_init);
+	zassert_equal(DEVICE_DT_GET(TEST_GPIO_INJECTED)->ops.init, dev_init);
+	zassert_equal(DEVICE_GET(manual_dev)->ops.init, dev_init);
+	zassert_equal(DEVICE_DT_GET(TEST_NOLABEL)->ops.init, dev_init);
 }
 
 ZTEST(devicetree_devices, test_init_order)
diff --git a/tests/lib/gui/lvgl/src/main.c b/tests/lib/gui/lvgl/src/main.c
index 22aafbc7eba..18b9f22c68c 100644
--- a/tests/lib/gui/lvgl/src/main.c
+++ b/tests/lib/gui/lvgl/src/main.c
@@ -104,8 +104,9 @@ void *setup_lvgl(void)
 
 #if CONFIG_LV_COLOR_DEPTH_1 == 1
 	display_set_pixel_format(display_dev, PIXEL_FORMAT_MONO10);
-#elif CONFIG_LV_COLOR_DEPTH_8 == 1 || CONFIG_LV_COLOR_DEPTH_24 == 1
-	/* No 8bit display pixel format not supported */
+#elif CONFIG_LV_COLOR_DEPTH_8 == 1
+	display_set_pixel_format(display_dev, PIXEL_FORMAT_L_8);
+#elif CONFIG_LV_COLOR_DEPTH_24 == 1
 	display_set_pixel_format(display_dev, PIXEL_FORMAT_RGB_888);
 #elif CONFIG_LV_COLOR_DEPTH_16 == 1
 	display_set_pixel_format(display_dev, PIXEL_FORMAT_RGB_565);
diff --git a/tests/lib/gui/lvgl/testcase.yaml b/tests/lib/gui/lvgl/testcase.yaml
index ab4b6be5315..270f355c931 100644
--- a/tests/lib/gui/lvgl/testcase.yaml
+++ b/tests/lib/gui/lvgl/testcase.yaml
@@ -87,7 +87,6 @@ tests:
       - CONFIG_DYNAMIC_THREAD_POOL_SIZE=4
       - CONFIG_DYNAMIC_THREAD_ALLOC=y
     platform_allow:
-      - native_posix/native/64
       - native_sim/native/64
       - native_sim
     integration_platforms:
diff --git a/tests/lib/heap_align/src/main.c b/tests/lib/heap_align/src/main.c
index 0061d1c4ad6..330e8a3635b 100644
--- a/tests/lib/heap_align/src/main.c
+++ b/tests/lib/heap_align/src/main.c
@@ -7,12 +7,37 @@
 #include <zephyr/ztest.h>
 #include <zephyr/sys/sys_heap.h>
 
+/* need to peek into some heap internals */
+#include "../../../../lib/heap/heap.h"
+
 #define HEAP_SZ 0x1000
 
-uint8_t __aligned(8) heapmem[HEAP_SZ];
+uint8_t __aligned(CHUNK_UNIT) heapmem[HEAP_SZ];
 
 /* Heap metadata sizes */
 uint8_t *heap_start, *heap_end;
+size_t heap_chunk_header_size;
+
+/*
+ * The align argument may contain a "rewind" bit.
+ * See comment in sys_heap_aligned_alloc().
+ */
+static bool alignment_ok(void *ptr, size_t align)
+{
+	uintptr_t addr = (uintptr_t)ptr;
+	size_t rew;
+
+	/* split rewind bit from alignment */
+	rew = LSB_GET(align);
+	rew = (rew == align) ? 0 : rew;
+	align -= rew;
+
+	/* undo the pointer rewind */
+	addr += rew;
+
+	/* validate pointer alignment */
+	return (addr & (align - 1)) == 0;
+}
 
 /* Note that this test is making whitebox assumptions about the
  * behavior of the heap in order to exercise coverage of the
@@ -24,24 +49,28 @@ static void check_heap_align(struct sys_heap *h,
 			     size_t prefix, size_t align, size_t size)
 {
 	void *p, *q, *r, *s;
+	size_t suffix;
 
 	p = sys_heap_alloc(h, prefix);
 	zassert_true(prefix == 0 || p != NULL, "prefix allocation failed");
 
 	q = sys_heap_aligned_alloc(h, align, size);
 	zassert_true(q != NULL, "first aligned allocation failed");
-	zassert_true((((uintptr_t)q) & (align - 1)) == 0, "block not aligned");
+	zassert_true(alignment_ok(q, align), "block not aligned");
 
 	r = sys_heap_aligned_alloc(h, align, size);
 	zassert_true(r != NULL, "second aligned allocation failed");
-	zassert_true((((uintptr_t)r) & (align - 1)) == 0, "block not aligned");
+	zassert_true(alignment_ok(r, align), "block not aligned");
 
 	/* Make sure ALL the split memory goes back into the heap and
 	 * we can allocate the full remaining suffix
 	 */
-	s = sys_heap_alloc(h, (heap_end - (uint8_t *)r) - size - 8);
+	suffix = (heap_end - (uint8_t *)ROUND_UP((uintptr_t)r + size, CHUNK_UNIT))
+		- heap_chunk_header_size;
+	s = sys_heap_alloc(h, suffix);
 	zassert_true(s != NULL, "suffix allocation failed (%zd/%zd/%zd)",
 				prefix, align, size);
+	zassert_true(sys_heap_validate(h), "heap invalid");
 
 	sys_heap_free(h, p);
 	sys_heap_free(h, q);
@@ -72,12 +101,17 @@ ZTEST(lib_heap_align, test_aligned_alloc)
 	 * chunk header before the end of its memory
 	 */
 	heap_start = p;
-	heap_end = heapmem + HEAP_SZ - 8;
+	heap_end = heapmem + heap.heap->end_chunk * CHUNK_UNIT;
+	heap_chunk_header_size = chunk_header_bytes(heap.heap);
 
 	for (size_t align = 8; align < HEAP_SZ / 4; align *= 2) {
 		for (size_t prefix = 0; prefix <= align; prefix += 8) {
-			for (size_t size = 8; size <= align; size += 8) {
+			for (size_t size = 4; size <= align; size += 12) {
 				check_heap_align(&heap, prefix, align, size);
+				for (size_t rew = 4; rew < MIN(align, 32); rew *= 2) {
+					check_heap_align(&heap, prefix,
+							 align | rew, size);
+				}
 			}
 		}
 	}
diff --git a/tests/lib/json/prj.conf b/tests/lib/json/prj.conf
index 4a6c8522abd..85d02432005 100644
--- a/tests/lib/json/prj.conf
+++ b/tests/lib/json/prj.conf
@@ -1,3 +1,4 @@
 CONFIG_JSON_LIBRARY=y
+CONFIG_JSON_LIBRARY_FP_SUPPORT=y
 CONFIG_ZTEST=y
-CONFIG_ZTEST_STACK_SIZE=3072
+CONFIG_ZTEST_STACK_SIZE=4096
diff --git a/tests/lib/json/src/main.c b/tests/lib/json/src/main.c
index baf2e0edd84..86503885def 100644
--- a/tests/lib/json/src/main.c
+++ b/tests/lib/json/src/main.c
@@ -4,6 +4,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <string.h>
+#include <float.h>
+#include <math.h>
 #include <zephyr/types.h>
 #include <stdbool.h>
 #include <zephyr/ztest.h>
@@ -13,14 +15,19 @@ struct test_nested {
 	int nested_int;
 	bool nested_bool;
 	const char *nested_string;
+	char nested_string_buf[10];
+	int8_t nested_int8;
+	uint8_t nested_uint8;
 	int64_t nested_int64;
 	uint64_t nested_uint64;
 };
 
 struct test_struct {
 	const char *some_string;
+	char some_string_buf[10];
 	int some_int;
 	bool some_bool;
+	int16_t some_int16;
 	int64_t some_int64;
 	int64_t another_int64;
 	int64_t some_uint64;
@@ -39,6 +46,7 @@ struct test_struct {
 
 struct elt {
 	const char *name;
+	const char name_buf[10];
 	int height;
 };
 
@@ -57,6 +65,47 @@ struct test_int_limits {
 	uint64_t uint64_max;
 	uint64_t uint64_cero;
 	uint64_t uint64_min;
+	uint32_t uint32_max;
+	uint32_t uint32_cero;
+	uint32_t uint32_min;
+	int16_t int16_max;
+	int16_t int16_cero;
+	int16_t int16_min;
+	uint16_t uint16_max;
+	uint16_t uint16_cero;
+	uint16_t uint16_min;
+	int8_t int8_max;
+	int8_t int8_cero;
+	int8_t int8_min;
+	uint8_t uint8_max;
+	uint8_t uint8_cero;
+	uint8_t uint8_min;
+};
+
+struct test_float {
+	float some_float;
+	float another_float;
+	float some_array[16];
+	size_t some_array_len;
+};
+
+struct test_float_limits {
+	float float_max;
+	float float_cero;
+	float float_min;
+};
+
+struct test_double {
+	double some_double;
+	double another_double;
+	double some_array[16];
+	size_t some_array_len;
+};
+
+struct test_double_limits {
+	double double_max;
+	double double_cero;
+	double double_min;
 };
 
 static const struct json_obj_descr nested_descr[] = {
@@ -64,6 +113,10 @@ static const struct json_obj_descr nested_descr[] = {
 	JSON_OBJ_DESCR_PRIM(struct test_nested, nested_bool, JSON_TOK_TRUE),
 	JSON_OBJ_DESCR_PRIM(struct test_nested, nested_string,
 			    JSON_TOK_STRING),
+	JSON_OBJ_DESCR_PRIM(struct test_nested, nested_string_buf,
+			    JSON_TOK_STRING_BUF),
+	JSON_OBJ_DESCR_PRIM(struct test_nested, nested_int8, JSON_TOK_INT),
+	JSON_OBJ_DESCR_PRIM(struct test_nested, nested_uint8, JSON_TOK_UINT),
 	JSON_OBJ_DESCR_PRIM(struct test_nested, nested_int64,
 			    JSON_TOK_INT64),
 	JSON_OBJ_DESCR_PRIM(struct test_nested, nested_uint64,
@@ -72,8 +125,10 @@ static const struct json_obj_descr nested_descr[] = {
 
 static const struct json_obj_descr test_descr[] = {
 	JSON_OBJ_DESCR_PRIM(struct test_struct, some_string, JSON_TOK_STRING),
+	JSON_OBJ_DESCR_PRIM(struct test_struct, some_string_buf, JSON_TOK_STRING_BUF),
 	JSON_OBJ_DESCR_PRIM(struct test_struct, some_int, JSON_TOK_NUMBER),
 	JSON_OBJ_DESCR_PRIM(struct test_struct, some_bool, JSON_TOK_TRUE),
+	JSON_OBJ_DESCR_PRIM(struct test_struct, some_int16, JSON_TOK_INT),
 	JSON_OBJ_DESCR_PRIM(struct test_struct, some_int64,
 			    JSON_TOK_INT64),
 	JSON_OBJ_DESCR_PRIM(struct test_struct, another_int64,
@@ -101,6 +156,7 @@ static const struct json_obj_descr test_descr[] = {
 
 static const struct json_obj_descr elt_descr[] = {
 	JSON_OBJ_DESCR_PRIM(struct elt, name, JSON_TOK_STRING),
+	JSON_OBJ_DESCR_PRIM(struct elt, name_buf, JSON_TOK_STRING_BUF),
 	JSON_OBJ_DESCR_PRIM(struct elt, height, JSON_TOK_NUMBER),
 };
 
@@ -119,6 +175,47 @@ static const struct json_obj_descr obj_limits_descr[] = {
 	JSON_OBJ_DESCR_PRIM(struct test_int_limits, uint64_max, JSON_TOK_UINT64),
 	JSON_OBJ_DESCR_PRIM(struct test_int_limits, uint64_cero, JSON_TOK_UINT64),
 	JSON_OBJ_DESCR_PRIM(struct test_int_limits, uint64_min, JSON_TOK_UINT64),
+	JSON_OBJ_DESCR_PRIM(struct test_int_limits, uint32_max, JSON_TOK_UINT),
+	JSON_OBJ_DESCR_PRIM(struct test_int_limits, uint32_cero, JSON_TOK_UINT),
+	JSON_OBJ_DESCR_PRIM(struct test_int_limits, uint32_min, JSON_TOK_UINT),
+	JSON_OBJ_DESCR_PRIM(struct test_int_limits, int16_max, JSON_TOK_INT),
+	JSON_OBJ_DESCR_PRIM(struct test_int_limits, int16_cero, JSON_TOK_INT),
+	JSON_OBJ_DESCR_PRIM(struct test_int_limits, int16_min, JSON_TOK_INT),
+	JSON_OBJ_DESCR_PRIM(struct test_int_limits, uint16_max, JSON_TOK_UINT),
+	JSON_OBJ_DESCR_PRIM(struct test_int_limits, uint16_cero, JSON_TOK_UINT),
+	JSON_OBJ_DESCR_PRIM(struct test_int_limits, uint16_min, JSON_TOK_UINT),
+	JSON_OBJ_DESCR_PRIM(struct test_int_limits, int8_max, JSON_TOK_INT),
+	JSON_OBJ_DESCR_PRIM(struct test_int_limits, int8_cero, JSON_TOK_INT),
+	JSON_OBJ_DESCR_PRIM(struct test_int_limits, int8_min, JSON_TOK_INT),
+	JSON_OBJ_DESCR_PRIM(struct test_int_limits, uint8_max, JSON_TOK_UINT),
+	JSON_OBJ_DESCR_PRIM(struct test_int_limits, uint8_cero, JSON_TOK_UINT),
+	JSON_OBJ_DESCR_PRIM(struct test_int_limits, uint8_min, JSON_TOK_UINT),
+};
+
+static const struct json_obj_descr obj_float_descr[] = {
+	JSON_OBJ_DESCR_PRIM(struct test_float, some_float, JSON_TOK_FLOAT_FP),
+	JSON_OBJ_DESCR_PRIM(struct test_float, another_float, JSON_TOK_FLOAT_FP),
+	JSON_OBJ_DESCR_ARRAY(struct test_float, some_array,
+			     16, some_array_len, JSON_TOK_FLOAT_FP),
+};
+
+static const struct json_obj_descr obj_float_limits_descr[] = {
+	JSON_OBJ_DESCR_PRIM(struct test_float_limits, float_max, JSON_TOK_FLOAT_FP),
+	JSON_OBJ_DESCR_PRIM(struct test_float_limits, float_cero, JSON_TOK_FLOAT_FP),
+	JSON_OBJ_DESCR_PRIM(struct test_float_limits, float_min, JSON_TOK_FLOAT_FP),
+};
+
+static const struct json_obj_descr obj_double_descr[] = {
+	JSON_OBJ_DESCR_PRIM(struct test_double, some_double, JSON_TOK_DOUBLE_FP),
+	JSON_OBJ_DESCR_PRIM(struct test_double, another_double, JSON_TOK_DOUBLE_FP),
+	JSON_OBJ_DESCR_ARRAY(struct test_double, some_array,
+			     16, some_array_len, JSON_TOK_DOUBLE_FP),
+};
+
+static const struct json_obj_descr obj_double_limits_descr[] = {
+	JSON_OBJ_DESCR_PRIM(struct test_double_limits, double_max, JSON_TOK_DOUBLE_FP),
+	JSON_OBJ_DESCR_PRIM(struct test_double_limits, double_cero, JSON_TOK_DOUBLE_FP),
+	JSON_OBJ_DESCR_PRIM(struct test_double_limits, double_min, JSON_TOK_DOUBLE_FP),
 };
 
 struct array {
@@ -205,11 +302,60 @@ static const struct json_obj_descr outer_descr[] = {
 				num_elements, element_descr, ARRAY_SIZE(element_descr))
 };
 
+struct test_alignment_nested {
+	bool bool1;
+	int int1;
+	bool bool2;
+};
+
+struct test_alignment_bool {
+	struct test_alignment_nested array[3];
+	size_t num_elements;
+};
+
+static const struct json_obj_descr alignment_nested_descr[] = {
+	JSON_OBJ_DESCR_PRIM(struct test_alignment_nested, bool1, JSON_TOK_TRUE),
+	JSON_OBJ_DESCR_PRIM(struct test_alignment_nested, int1, JSON_TOK_NUMBER),
+	JSON_OBJ_DESCR_PRIM(struct test_alignment_nested, bool2, JSON_TOK_TRUE),
+};
+
+static const struct json_obj_descr alignment_bool_descr[] = {
+	JSON_OBJ_DESCR_OBJ_ARRAY(struct test_alignment_bool, array, 3, num_elements,
+				 alignment_nested_descr, ARRAY_SIZE(alignment_nested_descr)) };
+
+enum int8_enum { I8_MIN = INT8_MIN, I8_MAX = INT8_MAX };
+enum uint8_enum { U8_MIN = 0, U8_MAX = UINT8_MAX };
+enum int16_enum { I16_MIN = INT16_MIN, I16_MAX = INT16_MAX };
+enum uint16_enum { U16_MIN = 0, U16_MAX = UINT16_MAX };
+enum int32_enum { I32_MIN = INT32_MIN, I32_MAX = INT32_MAX };
+enum uint32_enum { U32_MIN = 0, U32_MAX = UINT32_MAX };
+
+struct test_enums {
+	enum int8_enum i8;
+	enum uint8_enum u8;
+	enum int16_enum i16;
+	enum uint16_enum u16;
+	enum int32_enum i32;
+	enum uint32_enum u32;
+};
+
+static const struct json_obj_descr enums_descr[] = {
+	JSON_OBJ_DESCR_PRIM(struct test_enums, i8, JSON_TOK_INT),
+	JSON_OBJ_DESCR_PRIM(struct test_enums, u8, JSON_TOK_UINT),
+	JSON_OBJ_DESCR_PRIM(struct test_enums, i16, JSON_TOK_INT),
+	JSON_OBJ_DESCR_PRIM(struct test_enums, u16, JSON_TOK_UINT),
+	JSON_OBJ_DESCR_PRIM(struct test_enums, i32, JSON_TOK_INT),
+	JSON_OBJ_DESCR_PRIM(struct test_enums, u32, JSON_TOK_UINT),
+};
+
+
 ZTEST(lib_json_test, test_json_encoding)
 {
 	struct test_struct ts = {
 		.some_string = "zephyr 123\uABCD",
+		.some_string_buf = "z 123\uABCD",
 		.some_int = 42,
+		.some_int16 = 16,
 		.some_int64 = 1152921504606846977,
 		.another_int64 = -2305843009213693937,
 		.some_uint64 = 18446744073709551615U,
@@ -219,6 +365,9 @@ ZTEST(lib_json_test, test_json_encoding)
 			.nested_int = -1234,
 			.nested_bool = false,
 			.nested_string = "this should be escaped: \t",
+			.nested_string_buf = "esc: \t",
+			.nested_int8 = -123,
+			.nested_uint8 = 231,
 			.nested_int64 = 4503599627370496,
 			.nested_uint64 = 18446744073709551610U,
 		},
@@ -239,17 +388,21 @@ ZTEST(lib_json_test, test_json_encoding)
 			.nested_int = 1234,
 			.nested_bool = true,
 			.nested_string = "no escape necessary",
+			.nested_string_buf = "no escape",
+			.nested_int8 = 123,
+			.nested_uint8 = 231,
 			.nested_int64 = 4503599627370496,
 			.nested_uint64 = 18446744073709551610U,
 		},
 		.nested_obj_array = {
-			{1, true, "true"},
-			{0, false, "false"}
+			{1, true, "true", "true"},
+			{0, false, "false", "false"}
 		},
 		.obj_array_len = 2
 	};
 	char encoded[] = "{\"some_string\":\"zephyr 123\uABCD\","
-		"\"some_int\":42,\"some_bool\":true,"
+		"\"some_string_buf\":\"z 123\uABCD\","
+		"\"some_int\":42,\"some_bool\":true,\"some_int16\":16,"
 		"\"some_int64\":1152921504606846977,"
 		"\"another_int64\":-2305843009213693937,"
 		"\"some_uint64\":18446744073709551615,"
@@ -257,6 +410,9 @@ ZTEST(lib_json_test, test_json_encoding)
 		"\"some_nested_struct\":{\"nested_int\":-1234,"
 		"\"nested_bool\":false,\"nested_string\":"
 		"\"this should be escaped: \\t\","
+		"\"nested_string_buf\":\"esc: \\t\","
+		"\"nested_int8\":-123,"
+		"\"nested_uint8\":231,"
 		"\"nested_int64\":4503599627370496,"
 		"\"nested_uint64\":18446744073709551610},"
 		"\"some_array\":[1,4,8,16,32],"
@@ -266,11 +422,14 @@ ZTEST(lib_json_test, test_json_encoding)
 		"\"4nother_ne$+\":{\"nested_int\":1234,"
 		"\"nested_bool\":true,"
 		"\"nested_string\":\"no escape necessary\","
+		"\"nested_string_buf\":\"no escape\","
+		"\"nested_int8\":123,"
+		"\"nested_uint8\":231,"
 		"\"nested_int64\":4503599627370496,"
 		"\"nested_uint64\":18446744073709551610},"
 		"\"nested_obj_array\":["
-		"{\"nested_int\":1,\"nested_bool\":true,\"nested_string\":\"true\",\"nested_int64\":0,\"nested_uint64\":0},"
-		"{\"nested_int\":0,\"nested_bool\":false,\"nested_string\":\"false\",\"nested_int64\":0,\"nested_uint64\":0}]"
+		"{\"nested_int\":1,\"nested_bool\":true,\"nested_string\":\"true\",\"nested_string_buf\":\"true\",\"nested_int8\":0,\"nested_uint8\":0,\"nested_int64\":0,\"nested_uint64\":0},"
+		"{\"nested_int\":0,\"nested_bool\":false,\"nested_string\":\"false\",\"nested_string_buf\":\"false\",\"nested_int8\":0,\"nested_uint8\":0,\"nested_int64\":0,\"nested_uint64\":0}]"
 		"}";
 	char buffer[sizeof(encoded)];
 	int ret;
@@ -291,7 +450,9 @@ ZTEST(lib_json_test, test_json_decoding)
 {
 	struct test_struct ts;
 	char encoded[] = "{\"some_string\":\"zephyr 123\\uABCD456\","
+		"\"some_string_buf\":\"z\\uABCD\","
 		"\"some_int\":\t42\n,"
+		"\"some_int16\":\t16\n,"
 		"\"some_bool\":true    \t  "
 		"\n"
 		"\r   ,"
@@ -303,6 +464,8 @@ ZTEST(lib_json_test, test_json_decoding)
 		"\"nested_int\":-1234,\n\n"
 		"\"nested_bool\":false,\t"
 		"\"nested_string\":\"this should be escaped: \\t\","
+		"\"nested_string_buf\":\"esc: \\t\","
+		"\"nested_int8\":123,"
 		"\"nested_int64\":9223372036854775807,"
 		"\"extra_nested_array\":[0,-1]},"
 		"\"extra_struct\":{\"nested_bool\":false},"
@@ -314,10 +477,12 @@ ZTEST(lib_json_test, test_json_decoding)
 		"\"4nother_ne$+\":{\"nested_int\":1234,"
 		"\"nested_bool\":true,"
 		"\"nested_string\":\"no escape necessary\","
+		"\"nested_string_buf\":\"no escape\","
+		"\"nested_int8\":-123,"
 		"\"nested_int64\":-9223372036854775806},"
 		"\"nested_obj_array\":["
-		"{\"nested_int\":1,\"nested_bool\":true,\"nested_string\":\"true\"},"
-		"{\"nested_int\":0,\"nested_bool\":false,\"nested_string\":\"false\"}]"
+		"{\"nested_int\":1,\"nested_bool\":true,\"nested_string\":\"true\",\"nested_string_buf\":\"true\"},"
+		"{\"nested_int\":0,\"nested_bool\":false,\"nested_string\":\"false\",\"nested_string_buf\":\"false\"}]"
 		"}\n";
 	const int expected_array[] = { 11, 22, 33, 45, 299 };
 	const int expected_other_array[] = { 2, 3, 5, 7 };
@@ -331,7 +496,10 @@ ZTEST(lib_json_test, test_json_decoding)
 
 	zassert_str_equal(ts.some_string, "zephyr 123\\uABCD456",
 			  "String not decoded correctly");
+	zassert_str_equal(ts.some_string_buf, "z\\uABCD",
+			  "String (array) not decoded correctly");
 	zassert_equal(ts.some_int, 42, "Positive integer not decoded correctly");
+	zassert_equal(ts.some_int16, 16, "Positive integer not decoded correctly");
 	zassert_equal(ts.some_bool, true, "Boolean not decoded correctly");
 	zassert_equal(ts.some_int64, -4611686018427387904,
 		      "int64 not decoded correctly");
@@ -339,6 +507,8 @@ ZTEST(lib_json_test, test_json_decoding)
 		      "int64 not decoded correctly");
 	zassert_equal(ts.some_nested_struct.nested_int, -1234,
 		      "Nested negative integer not decoded correctly");
+	zassert_equal(ts.some_nested_struct.nested_int8, 123,
+		      "Nested int8 not decoded correctly");
 	zassert_equal(ts.some_nested_struct.nested_int64, 9223372036854775807,
 		      "Nested int64 not decoded correctly");
 	zassert_equal(ts.some_nested_struct.nested_bool, false,
@@ -346,6 +516,9 @@ ZTEST(lib_json_test, test_json_decoding)
 	zassert_str_equal(ts.some_nested_struct.nested_string,
 			  "this should be escaped: \\t",
 			  "Nested string not decoded correctly");
+	zassert_str_equal(ts.some_nested_struct.nested_string_buf,
+			  "esc: \\t",
+			  "Nested string-array not decoded correctly");
 	zassert_equal(ts.some_array_len, 5,
 		      "Array doesn't have correct number of items");
 	zassert_true(!memcmp(ts.some_array, expected_array,
@@ -362,6 +535,8 @@ ZTEST(lib_json_test, test_json_decoding)
 		     "Decoded named array not with expected values");
 	zassert_equal(ts.xnother_nexx.nested_int, 1234,
 		      "Named nested integer not decoded correctly");
+	zassert_equal(ts.xnother_nexx.nested_int8, -123,
+		      "Named nested int8 not decoded correctly");
 	zassert_equal(ts.xnother_nexx.nested_int64, -9223372036854775806,
 		      "Named nested int64 not decoded correctly");
 	zassert_equal(ts.xnother_nexx.nested_bool, true,
@@ -369,6 +544,9 @@ ZTEST(lib_json_test, test_json_decoding)
 	zassert_str_equal(ts.xnother_nexx.nested_string,
 			  "no escape necessary",
 			  "Named nested string not decoded correctly");
+	zassert_str_equal(ts.xnother_nexx.nested_string_buf,
+			  "no escape",
+			  "Named nested string-array not decoded correctly");
 	zassert_equal(ts.obj_array_len, 2,
 		      "Array of objects does not have correct number of items");
 	zassert_equal(ts.nested_obj_array[0].nested_int, 1,
@@ -377,12 +555,16 @@ ZTEST(lib_json_test, test_json_decoding)
 		      "Boolean value in first object array element not decoded correctly");
 	zassert_str_equal(ts.nested_obj_array[0].nested_string, "true",
 			  "String in first object array element not decoded correctly");
+	zassert_str_equal(ts.nested_obj_array[0].nested_string_buf, "true",
+			  "String buffer in first object array element not decoded correctly");
 	zassert_equal(ts.nested_obj_array[1].nested_int, 0,
 		      "Integer in second object array element not decoded correctly");
 	zassert_equal(ts.nested_obj_array[1].nested_bool, false,
 		      "Boolean value in second object array element not decoded correctly");
 	zassert_str_equal(ts.nested_obj_array[1].nested_string, "false",
 			  "String in second object array element not decoded correctly");
+	zassert_str_equal(ts.nested_obj_array[1].nested_string_buf, "false",
+			  "String buffer in second object array element not decoded correctly");
 }
 
 ZTEST(lib_json_test, test_json_limits)
@@ -396,7 +578,22 @@ ZTEST(lib_json_test, test_json_limits)
 			 "\"int64_min\":-9223372036854775808,"
 			 "\"uint64_max\":18446744073709551615,"
 			 "\"uint64_cero\":0,"
-			 "\"uint64_min\":0"
+			 "\"uint64_min\":0,"
+			 "\"uint32_max\":4294967295,"
+			 "\"uint32_cero\":0,"
+			 "\"uint32_min\":0,"
+			 "\"int16_max\":32767,"
+			 "\"int16_cero\":0,"
+			 "\"int16_min\":-32768,"
+			 "\"uint16_max\":65535,"
+			 "\"uint16_cero\":0,"
+			 "\"uint16_min\":0,"
+			 "\"int8_max\":127,"
+			 "\"int8_cero\":0,"
+			 "\"int8_min\":-128,"
+			 "\"uint8_max\":255,"
+			 "\"uint8_cero\":0,"
+			 "\"uint8_min\":0"
 			 "}";
 
 	struct test_int_limits limits = {
@@ -409,6 +606,21 @@ ZTEST(lib_json_test, test_json_limits)
 		.uint64_max = UINT64_MAX,
 		.uint64_cero = 0,
 		.uint64_min = 0,
+		.uint32_max = UINT32_MAX,
+		.uint32_cero = 0,
+		.uint32_min = 0,
+		.int16_max = INT16_MAX,
+		.int16_cero = 0,
+		.int16_min = INT16_MIN,
+		.uint16_max = UINT16_MAX,
+		.uint16_cero = 0,
+		.uint16_min = 0,
+		.int8_max = INT8_MAX,
+		.int8_cero = 0,
+		.int8_min = INT8_MIN,
+		.uint8_max = UINT8_MAX,
+		.uint8_cero = 0,
+		.uint8_min = 0,
 	};
 
 	char buffer[sizeof(encoded)];
@@ -425,21 +637,353 @@ ZTEST(lib_json_test, test_json_limits)
 		     "Integer limits not decoded correctly");
 }
 
+ZTEST(lib_json_test, test_json_float)
+{
+	char encoded[] = "{\"some_float\":-0.000244140625,"
+			 "\"another_float\":12345600,"
+			 "\"some_array\":[1.5,2.25]"
+			 "}";
+
+	struct test_float floats = {
+		.some_float = -0.000244140625,
+		.another_float = 12345600.0,
+		.some_array[0] = 1.5,
+		.some_array[1] = 2.25,
+		.some_array_len = 2,
+	};
+
+	char buffer[sizeof(encoded)];
+	struct test_float floats_decoded = {0};
+	int ret;
+
+	ret = json_obj_encode_buf(obj_float_descr, ARRAY_SIZE(obj_float_descr),
+				&floats, buffer, sizeof(buffer));
+	zassert_equal(ret, 0, "Encoding of float returned error");
+	ret = json_obj_parse(encoded, sizeof(encoded), obj_float_descr,
+			     ARRAY_SIZE(obj_float_descr), &floats_decoded);
+	zassert_str_equal(encoded, buffer,
+			  "Float not encoded correctly");
+	zassert_true(!memcmp(&floats, &floats_decoded, sizeof(floats)),
+		     "Float not decoded correctly");
+}
+
+ZTEST(lib_json_test, test_json_float_format)
+{
+	struct sub_test {
+		float num;
+		char *str;
+	};
+	struct sub_test encoded[] = {
+		{ .num = 0, .str = "0" },
+		{ .num = 0, .str = "0.0" },
+		{ .num = 0, .str = "0e0" },
+		{ .num = 0, .str = "0e+0" },
+		{ .num = 0, .str = "0e-0" },
+
+		{ .num = 12345, .str = "12345" },
+		{ .num = 12345, .str = "1.2345e+4" },
+		{ .num = 12345, .str = "1.2345e+04" },
+
+		{ .num = -12345, .str = "-12345" },
+		{ .num = -12345, .str = "-1.2345e+4" },
+		{ .num = -12345, .str = "-1.2345e+04" },
+
+		{ .num = 0.03125, .str = "0.03125" },
+		{ .num = 0.03125, .str = "3.125e-2" },
+		{ .num = 0.03125, .str = "3.125e-02" },
+
+		{ .num = -0.03125, .str = "-0.03125" },
+		{ .num = -0.03125, .str = "-3.125e-2" },
+		{ .num = -0.03125, .str = "-3.125e-02" },
+	};
+
+	struct test_float ts;
+	char str_encoded[32];
+
+	for (int i = 0; i < ARRAY_SIZE(encoded); i++) {
+		snprintf(str_encoded, sizeof(str_encoded), "{\"some_float\":%s}", encoded[i].str);
+		int ret = json_obj_parse(str_encoded, strlen(str_encoded),
+			       obj_float_descr, ARRAY_SIZE(obj_float_descr), &ts);
+		zassert_equal(ret, 1, "Decoding failed: %s result: %d", str_encoded, ret);
+		zassert_equal(ts.some_float, encoded[i].num,
+			      "Decoding failed '%s' float: %g exepcted: %g",
+			      str_encoded, (double)ts.some_float, (double)encoded[i].num);
+	}
+}
+
+ZTEST(lib_json_test, test_json_float_nan)
+{
+	char encoded[] = "{\"some_float\":NaN,"
+			 "\"another_float\":NaN,"
+			 "\"some_array\":[NaN,NaN]"
+			 "}";
+
+	struct test_float floats = {
+		.some_float = NAN,
+		.another_float = NAN,
+		.some_array[0] = NAN,
+		.some_array[1] = NAN,
+		.some_array_len = 2,
+	};
+
+	char buffer[sizeof(encoded)];
+	struct test_float floats_decoded = {0};
+	int ret;
+
+	ret = json_obj_encode_buf(obj_float_descr, ARRAY_SIZE(obj_float_descr),
+				&floats, buffer, sizeof(buffer));
+	zassert_equal(ret, 0, "Encoding of float nan returned error");
+	ret = json_obj_parse(encoded, sizeof(encoded), obj_float_descr,
+			     ARRAY_SIZE(obj_float_descr), &floats_decoded);
+	zassert_str_equal(encoded, buffer,
+			  "Float not encoded correctly");
+	zassert_true(!memcmp(&floats, &floats_decoded, sizeof(floats)),
+		     "Float not decoded correctly");
+}
+
+ZTEST(lib_json_test, test_json_float_infinity)
+{
+	char encoded[] = "{\"some_float\":Infinity,"
+			 "\"another_float\":-Infinity,"
+			 "\"some_array\":[Infinity,-Infinity]"
+			 "}";
+
+	struct test_float floats = {
+		.some_float = INFINITY,
+		.another_float = -INFINITY,
+		.some_array[0] = INFINITY,
+		.some_array[1] = -INFINITY,
+		.some_array_len = 2,
+	};
+
+	char buffer[sizeof(encoded)];
+	struct test_float floats_decoded = {0};
+	int ret;
+
+	ret = json_obj_encode_buf(obj_float_descr, ARRAY_SIZE(obj_float_descr),
+				&floats, buffer, sizeof(buffer));
+	zassert_equal(ret, 0, "Encoding of float inf returned error");
+	ret = json_obj_parse(encoded, sizeof(encoded), obj_float_descr,
+			     ARRAY_SIZE(obj_float_descr), &floats_decoded);
+	zassert_str_equal(encoded, buffer,
+			  "Float not encoded correctly");
+	zassert_true(!memcmp(&floats, &floats_decoded, sizeof(floats)),
+		     "Float not decoded correctly");
+}
+
+ZTEST(lib_json_test, test_json_float_limits)
+{
+	char encoded[] = "{\"float_max\":3.40282347e+38,"
+			 "\"float_cero\":0,"
+			 "\"float_min\":-3.40282347e+38"
+			 "}";
+
+	struct test_float_limits limits = {
+		.float_max = 3.40282347e+38,
+		.float_cero = 0,
+		.float_min = -3.40282347e+38,
+	};
+
+	char buffer[sizeof(encoded)];
+	struct test_float_limits limits_decoded = {0};
+	int ret;
+
+	ret = json_obj_encode_buf(obj_float_limits_descr, ARRAY_SIZE(obj_float_limits_descr),
+				&limits, buffer, sizeof(buffer));
+	zassert_equal(ret, 0, "Encoding of float limits returned error");
+	ret = json_obj_parse(encoded, sizeof(encoded), obj_float_limits_descr,
+			     ARRAY_SIZE(obj_float_limits_descr), &limits_decoded);
+	zassert_str_equal(encoded, buffer,
+			  "Float limits not encoded correctly");
+	zassert_true(!memcmp(&limits, &limits_decoded, sizeof(limits)),
+		     "Float limits not decoded correctly");
+}
+
+ZTEST(lib_json_test, test_json_double)
+{
+	char encoded[] = "{\"some_double\":-0.000244140625,"
+			 "\"another_double\":1234567890000000,"
+			 "\"some_array\":[1.5,2.25]"
+			 "}";
+
+	struct test_double doubles = {
+		.some_double = -0.000244140625,
+		.another_double = 1234567890000000.0,
+		.some_array[0] = 1.5,
+		.some_array[1] = 2.25,
+		.some_array_len = 2,
+	};
+
+	char buffer[sizeof(encoded)];
+	struct test_double doubles_decoded = {0};
+	int ret;
+
+	ret = json_obj_encode_buf(obj_double_descr, ARRAY_SIZE(obj_double_descr),
+				&doubles, buffer, sizeof(buffer));
+	zassert_equal(ret, 0, "Encoding of double returned error");
+	ret = json_obj_parse(encoded, sizeof(encoded), obj_double_descr,
+			     ARRAY_SIZE(obj_double_descr), &doubles_decoded);
+	zassert_str_equal(encoded, buffer,
+			  "Double not encoded correctly");
+	zassert_true(!memcmp(&doubles, &doubles_decoded, sizeof(doubles)),
+		     "Double not decoded correctly");
+}
+
+ZTEST(lib_json_test, test_json_double_format)
+{
+	struct sub_test {
+		double num;
+		char *str;
+	};
+	struct sub_test encoded[] = {
+		{ .num = 0, .str = "0" },
+		{ .num = 0, .str = "0.0" },
+		{ .num = 0, .str = "0e0" },
+		{ .num = 0, .str = "0e+0" },
+		{ .num = 0, .str = "0e-0" },
+
+		{ .num = 12345, .str = "12345" },
+		{ .num = 12345, .str = "1.2345e+4" },
+		{ .num = 12345, .str = "1.2345e+04" },
+
+		{ .num = -12345, .str = "-12345" },
+		{ .num = -12345, .str = "-1.2345e+4" },
+		{ .num = -12345, .str = "-1.2345e+04" },
+
+		{ .num = 0.03125, .str = "0.03125" },
+		{ .num = 0.03125, .str = "3.125e-2" },
+		{ .num = 0.03125, .str = "3.125e-02" },
+
+		{ .num = -0.03125, .str = "-0.03125" },
+		{ .num = -0.03125, .str = "-3.125e-2" },
+		{ .num = -0.03125, .str = "-3.125e-02" },
+	};
+
+	struct test_double ts;
+	char str_encoded[32];
+
+	for (int i = 0; i < ARRAY_SIZE(encoded); i++) {
+		snprintf(str_encoded, sizeof(str_encoded), "{\"some_double\":%s}", encoded[i].str);
+		int ret = json_obj_parse(str_encoded, strlen(str_encoded),
+					 obj_double_descr, ARRAY_SIZE(obj_double_descr), &ts);
+		zassert_equal(ret, 1, "Decoding failed: %s result: %d", str_encoded, ret);
+		zassert_equal(ts.some_double, encoded[i].num,
+			      "Decoding failed '%s' double: %g exepcted: %g",
+			      str_encoded, ts.some_double, encoded[i].num);
+	}
+}
+
+
+ZTEST(lib_json_test, test_json_double_nan)
+{
+	char encoded[] = "{\"some_double\":NaN,"
+			 "\"another_double\":NaN,"
+			 "\"some_array\":[NaN,NaN]"
+			 "}";
+
+	struct test_double doubles = {
+		.some_double = (double)NAN,
+		.another_double = (double)NAN,
+		.some_array[0] = (double)NAN,
+		.some_array[1] = (double)NAN,
+		.some_array_len = 2,
+	};
+
+	char buffer[sizeof(encoded)];
+	struct test_double doubles_decoded = {0};
+	int ret;
+
+	ret = json_obj_encode_buf(obj_double_descr, ARRAY_SIZE(obj_double_descr),
+				&doubles, buffer, sizeof(buffer));
+	zassert_equal(ret, 0, "Encoding of double nan returned error");
+	ret = json_obj_parse(encoded, sizeof(encoded), obj_double_descr,
+			     ARRAY_SIZE(obj_double_descr), &doubles_decoded);
+	zassert_str_equal(encoded, buffer,
+			  "Double not encoded correctly");
+	zassert_true(!memcmp(&doubles, &doubles_decoded, sizeof(doubles)),
+		     "Double not decoded correctly");
+}
+
+ZTEST(lib_json_test, test_json_double_infinity)
+{
+	char encoded[] = "{\"some_double\":Infinity,"
+			 "\"another_double\":-Infinity,"
+			 "\"some_array\":[Infinity,-Infinity]"
+			 "}";
+
+	struct test_double doubles = {
+		.some_double = (double)INFINITY,
+		.another_double = (double)-INFINITY,
+		.some_array[0] = (double)INFINITY,
+		.some_array[1] = (double)-INFINITY,
+		.some_array_len = 2,
+	};
+
+	char buffer[sizeof(encoded)];
+	struct test_double doubles_decoded = {0};
+	int ret;
+
+	ret = json_obj_encode_buf(obj_double_descr, ARRAY_SIZE(obj_double_descr),
+				&doubles, buffer, sizeof(buffer));
+	zassert_equal(ret, 0, "Encoding of double inf returned error");
+	ret = json_obj_parse(encoded, sizeof(encoded), obj_double_descr,
+			     ARRAY_SIZE(obj_double_descr), &doubles_decoded);
+	zassert_str_equal(encoded, buffer,
+			  "Double not encoded correctly");
+	zassert_true(!memcmp(&doubles, &doubles_decoded, sizeof(doubles)),
+		     "Double not decoded correctly");
+}
+
+ZTEST(lib_json_test, test_json_doubles_limits)
+{
+	char encoded[] = "{\"double_max\":1.797693134862315e+308,"
+			 "\"double_cero\":0,"
+			 "\"double_min\":-1.797693134862315e+308"
+			 "}";
+
+	struct test_double_limits limits = {
+		.double_max = 1.797693134862315e+308,
+		.double_cero = 0,
+		.double_min = -1.797693134862315e+308,
+	};
+
+	char buffer[sizeof(encoded)];
+	struct test_double_limits limits_decoded = {0};
+	int ret;
+
+	ret = json_obj_encode_buf(obj_double_limits_descr, ARRAY_SIZE(obj_double_limits_descr),
+				&limits, buffer, sizeof(buffer));
+	zassert_equal(ret, 0, "Encoding of double limits returned error");
+	ret = json_obj_parse(encoded, sizeof(encoded), obj_double_limits_descr,
+			     ARRAY_SIZE(obj_double_limits_descr), &limits_decoded);
+	zassert_str_equal(encoded, buffer,
+			  "Double limits not encoded correctly");
+	zassert_true(!memcmp(&limits, &limits_decoded, sizeof(limits)),
+		     "Double limits not decoded correctly");
+}
+
 ZTEST(lib_json_test, test_json_encoding_array_array)
 {
 	struct obj_array_array obj_array_array_ts = {
 		.objects_array = {
-			[0] = { { .name = "Sim\303\263n Bol\303\255var", .height = 168 } },
-			[1] = { { .name = "Pel\303\251",                 .height = 173 } },
-			[2] = { { .name = "Usain Bolt",                  .height = 195 } },
+			[0] = {{.name = "Sim\303\263n Bol\303\255var",
+				.name_buf = "Sim\303\263n",
+				.height = 168}},
+			[1] = {{.name = "Pel\303\251",
+				.name_buf = "Pel\303\251",
+				.height = 173}},
+			[2] = {{.name = "Usain Bolt",
+				.name_buf = "Usain",
+				.height = 195}},
 		},
 		.objects_array_len = 3,
 	};
 	char encoded[] = "{\"objects_array\":["
-		"{\"name\":\"Sim\303\263n Bol\303\255var\",\"height\":168},"
-		"{\"name\":\"Pel\303\251\",\"height\":173},"
-		"{\"name\":\"Usain Bolt\",\"height\":195}"
-		"]}";
+			 "{\"name\":\"Sim\303\263n Bol\303\255var\",\"name_buf\":\"Sim\303\263n\",\"height\":168},"
+			 "{\"name\":\"Pel\303\251\",\"name_buf\":\"Pel\303\251\",\"height\":173},"
+			 "{\"name\":\"Usain Bolt\",\"name_buf\":\"Usain\",\"height\":195}"
+			 "]}";
+
 	char buffer[sizeof(encoded)];
 	int ret;
 
@@ -455,9 +999,9 @@ ZTEST(lib_json_test, test_json_decoding_array_array)
 	int ret;
 	struct obj_array_array obj_array_array_ts;
 	char encoded[] = "{\"objects_array\":["
-			  "{\"height\":168,\"name\":\"Sim\303\263n Bol\303\255var\"},"
-			  "{\"height\":173,\"name\":\"Pel\303\251\"},"
-			  "{\"height\":195,\"name\":\"Usain Bolt\"}]"
+			  "{\"height\":168,\"name\":\"Sim\303\263n Bol\303\255var\",\"name_buf\":\"Sim\303\263n\"},"
+			  "{\"height\":173,\"name\":\"Pel\303\251\",\"name_buf\":\"Pel\303\251\"},"
+			  "{\"height\":195,\"name\":\"Usain Bolt\",\"name_buf\":\"Usain\"}]"
 			  "}";
 
 	ret = json_obj_parse(encoded, sizeof(encoded),
@@ -472,16 +1016,23 @@ ZTEST(lib_json_test, test_json_decoding_array_array)
 	zassert_str_equal(obj_array_array_ts.objects_array[0].objects.name,
 			  "Sim\303\263n Bol\303\255var",
 			  "String not decoded correctly");
+	zassert_str_equal(obj_array_array_ts.objects_array[0].objects.name_buf,
+			  "Sim\303\263n",
+			  "String buffer not decoded correctly");
 	zassert_equal(obj_array_array_ts.objects_array[0].objects.height, 168,
 		      "Sim\303\263n Bol\303\255var height not decoded correctly");
 
 	zassert_str_equal(obj_array_array_ts.objects_array[1].objects.name,
 			  "Pel\303\251", "String not decoded correctly");
+	zassert_str_equal(obj_array_array_ts.objects_array[1].objects.name_buf,
+			  "Pel\303\251", "String buffer not decoded correctly");
 	zassert_equal(obj_array_array_ts.objects_array[1].objects.height, 173,
 		      "Pel\303\251 height not decoded correctly");
 
 	zassert_str_equal(obj_array_array_ts.objects_array[2].objects.name,
 			  "Usain Bolt", "String not decoded correctly");
+	zassert_str_equal(obj_array_array_ts.objects_array[2].objects.name_buf,
+			  "Usain", "String buffer not decoded correctly");
 	zassert_equal(obj_array_array_ts.objects_array[2].objects.height, 195,
 		      "Usain Bolt height not decoded correctly");
 }
@@ -490,30 +1041,60 @@ ZTEST(lib_json_test, test_json_obj_arr_encoding)
 {
 	struct obj_array oa = {
 		.elements = {
-			[0] = { .name = "Sim\303\263n Bol\303\255var", .height = 168 },
-			[1] = { .name = "Muggsy Bogues",               .height = 160 },
-			[2] = { .name = "Pel\303\251",                 .height = 173 },
-			[3] = { .name = "Hakeem Olajuwon",             .height = 213 },
-			[4] = { .name = "Alex Honnold",                .height = 180 },
-			[5] = { .name = "Hazel Findlay",               .height = 157 },
-			[6] = { .name = "Daila Ojeda",                 .height = 158 },
-			[7] = { .name = "Albert Einstein",             .height = 172 },
-			[8] = { .name = "Usain Bolt",                  .height = 195 },
-			[9] = { .name = "Paavo Nurmi",                 .height = 174 },
+			[0] = {
+				.name = "Sim\303\263n Bol\303\255var",
+				.name_buf = "Sim\303\263n",
+				.height = 168 },
+			[1] = {
+				.name = "Muggsy Bogues",
+				.name_buf = "Muggsy",
+				.height = 160 },
+			[2] = {
+				.name = "Pel\303\251",
+				.name_buf = "Pel\303\251",
+				.height = 173 },
+			[3] = {
+				.name = "Hakeem Olajuwon",
+				.name_buf = "Hakeem",
+				.height = 213 },
+			[4] = {
+				.name = "Alex Honnold",
+				.name_buf = "Alex",
+				.height = 180 },
+			[5] = {
+				.name = "Hazel Findlay",
+				.name_buf = "Hazel",
+				.height = 157 },
+			[6] = {
+				.name = "Daila Ojeda",
+				.name_buf = "Daila",
+				.height = 158 },
+			[7] = {
+				.name = "Albert Einstein",
+				.name_buf = "Albert",
+				.height = 172 },
+			[8] = {
+				.name = "Usain Bolt",
+				.name_buf = "Usain",
+				.height = 195 },
+			[9] = {
+				.name = "Paavo Nurmi",
+				.name_buf = "Paavo",
+				.height = 174 },
 		},
 		.num_elements = 10,
 	};
 	char encoded[] = "{\"elements\":["
-		"{\"name\":\"Sim\303\263n Bol\303\255var\",\"height\":168},"
-		"{\"name\":\"Muggsy Bogues\",\"height\":160},"
-		"{\"name\":\"Pel\303\251\",\"height\":173},"
-		"{\"name\":\"Hakeem Olajuwon\",\"height\":213},"
-		"{\"name\":\"Alex Honnold\",\"height\":180},"
-		"{\"name\":\"Hazel Findlay\",\"height\":157},"
-		"{\"name\":\"Daila Ojeda\",\"height\":158},"
-		"{\"name\":\"Albert Einstein\",\"height\":172},"
-		"{\"name\":\"Usain Bolt\",\"height\":195},"
-		"{\"name\":\"Paavo Nurmi\",\"height\":174}"
+		"{\"name\":\"Sim\303\263n Bol\303\255var\",\"name_buf\":\"Sim\303\263n\",\"height\":168},"
+		"{\"name\":\"Muggsy Bogues\",\"name_buf\":\"Muggsy\",\"height\":160},"
+		"{\"name\":\"Pel\303\251\",\"name_buf\":\"Pel\303\251\",\"height\":173},"
+		"{\"name\":\"Hakeem Olajuwon\",\"name_buf\":\"Hakeem\",\"height\":213},"
+		"{\"name\":\"Alex Honnold\",\"name_buf\":\"Alex\",\"height\":180},"
+		"{\"name\":\"Hazel Findlay\",\"name_buf\":\"Hazel\",\"height\":157},"
+		"{\"name\":\"Daila Ojeda\",\"name_buf\":\"Daila\",\"height\":158},"
+		"{\"name\":\"Albert Einstein\",\"name_buf\":\"Albert\",\"height\":172},"
+		"{\"name\":\"Usain Bolt\",\"name_buf\":\"Usain\",\"height\":195},"
+		"{\"name\":\"Paavo Nurmi\",\"name_buf\":\"Paavo\",\"height\":174}"
 		"]}";
 	char buffer[sizeof(encoded)];
 	int ret;
@@ -529,10 +1110,11 @@ ZTEST(lib_json_test, test_json_arr_obj_decoding)
 {
 	int ret;
 	struct obj_array obj_array_array_ts;
-	char encoded[] = "[{\"height\":168,\"name\":\"Sim\303\263n Bol\303\255var\"},"
-					"{\"height\":173,\"name\":\"Pel\303\251\"},"
-					"{\"height\":195,\"name\":\"Usain Bolt\"}"
-					"]";
+	char encoded[] = "[{\"height\":168,\"name\":\"Sim\303\263n Bol\303\255var\","
+			 "\"name_buf\":\"Sim\303\263n\"},"
+			 "{\"height\":173,\"name\":\"Pel\303\251\",\"name_buf\":\"Pel\303\251\"},"
+			 "{\"height\":195,\"name\":\"Usain Bolt\",\"name_buf\":\"Usain\"}"
+			 "]";
 
 	ret = json_arr_parse(encoded, sizeof(encoded),
 			     obj_array_descr,
@@ -545,16 +1127,23 @@ ZTEST(lib_json_test, test_json_arr_obj_decoding)
 	zassert_str_equal(obj_array_array_ts.elements[0].name,
 			  "Sim\303\263n Bol\303\255var",
 			  "String not decoded correctly");
+	zassert_str_equal(obj_array_array_ts.elements[0].name_buf,
+			  "Sim\303\263n",
+			  "String buffer not decoded correctly");
 	zassert_equal(obj_array_array_ts.elements[0].height, 168,
 		      "Sim\303\263n Bol\303\255var height not decoded correctly");
 
 	zassert_str_equal(obj_array_array_ts.elements[1].name, "Pel\303\251",
 			  "String not decoded correctly");
+	zassert_str_equal(obj_array_array_ts.elements[1].name_buf, "Pel\303\251",
+			  "String buffer not decoded correctly");
 	zassert_equal(obj_array_array_ts.elements[1].height, 173,
 		      "Pel\303\251 height not decoded correctly");
 
 	zassert_str_equal(obj_array_array_ts.elements[2].name, "Usain Bolt",
 			  "String not decoded correctly");
+	zassert_str_equal(obj_array_array_ts.elements[2].name_buf, "Usain",
+			  "String buffer not decoded correctly");
 	zassert_equal(obj_array_array_ts.elements[2].height, 195,
 		      "Usain Bolt height not decoded correctly");
 }
@@ -563,30 +1152,60 @@ ZTEST(lib_json_test, test_json_arr_obj_encoding)
 {
 	struct obj_array oa = {
 		.elements = {
-			[0] = { .name = "Sim\303\263n Bol\303\255var", .height = 168 },
-			[1] = { .name = "Muggsy Bogues",               .height = 160 },
-			[2] = { .name = "Pel\303\251",                 .height = 173 },
-			[3] = { .name = "Hakeem Olajuwon",             .height = 213 },
-			[4] = { .name = "Alex Honnold",                .height = 180 },
-			[5] = { .name = "Hazel Findlay",               .height = 157 },
-			[6] = { .name = "Daila Ojeda",                 .height = 158 },
-			[7] = { .name = "Albert Einstein",             .height = 172 },
-			[8] = { .name = "Usain Bolt",                  .height = 195 },
-			[9] = { .name = "Paavo Nurmi",                 .height = 174 },
+			[0] = {
+				.name = "Sim\303\263n Bol\303\255var",
+				.name_buf = "Sim\303\263n",
+				.height = 168 },
+			[1] = {
+				.name = "Muggsy Bogues",
+				.name_buf = "Muggsy",
+				.height = 160 },
+			[2] = {
+				.name = "Pel\303\251",
+				.name_buf = "Pel\303\251",
+				.height = 173 },
+			[3] = {
+				.name = "Hakeem Olajuwon",
+				.name_buf = "Hakeem",
+				.height = 213 },
+			[4] = {
+				.name = "Alex Honnold",
+				.name_buf = "Alex",
+				.height = 180 },
+			[5] = {
+				.name = "Hazel Findlay",
+				.name_buf = "Hazel",
+				.height = 157 },
+			[6] = {
+				.name = "Daila Ojeda",
+				.name_buf = "Daila",
+				.height = 158 },
+			[7] = {
+				.name = "Albert Einstein",
+				.name_buf = "Albert",
+				.height = 172 },
+			[8] = {
+				.name = "Usain Bolt",
+				.name_buf = "Usain",
+				.height = 195 },
+			[9] = {
+				.name = "Paavo Nurmi",
+				.name_buf = "Paavo",
+				.height = 174 },
 		},
 		.num_elements = 10,
 	};
 	char encoded[] = "["
-		"{\"name\":\"Sim\303\263n Bol\303\255var\",\"height\":168},"
-		"{\"name\":\"Muggsy Bogues\",\"height\":160},"
-		"{\"name\":\"Pel\303\251\",\"height\":173},"
-		"{\"name\":\"Hakeem Olajuwon\",\"height\":213},"
-		"{\"name\":\"Alex Honnold\",\"height\":180},"
-		"{\"name\":\"Hazel Findlay\",\"height\":157},"
-		"{\"name\":\"Daila Ojeda\",\"height\":158},"
-		"{\"name\":\"Albert Einstein\",\"height\":172},"
-		"{\"name\":\"Usain Bolt\",\"height\":195},"
-		"{\"name\":\"Paavo Nurmi\",\"height\":174}"
+		"{\"name\":\"Sim\303\263n Bol\303\255var\",\"name_buf\":\"Sim\303\263n\",\"height\":168},"
+		"{\"name\":\"Muggsy Bogues\",\"name_buf\":\"Muggsy\",\"height\":160},"
+		"{\"name\":\"Pel\303\251\",\"name_buf\":\"Pel\303\251\",\"height\":173},"
+		"{\"name\":\"Hakeem Olajuwon\",\"name_buf\":\"Hakeem\",\"height\":213},"
+		"{\"name\":\"Alex Honnold\",\"name_buf\":\"Alex\",\"height\":180},"
+		"{\"name\":\"Hazel Findlay\",\"name_buf\":\"Hazel\",\"height\":157},"
+		"{\"name\":\"Daila Ojeda\",\"name_buf\":\"Daila\",\"height\":158},"
+		"{\"name\":\"Albert Einstein\",\"name_buf\":\"Albert\",\"height\":172},"
+		"{\"name\":\"Usain Bolt\",\"name_buf\":\"Usain\",\"height\":195},"
+		"{\"name\":\"Paavo Nurmi\",\"name_buf\":\"Paavo\",\"height\":174}"
 		"]";
 	char buffer[sizeof(encoded)];
 	int ret;
@@ -605,29 +1224,59 @@ ZTEST(lib_json_test, test_json_obj_arr_decoding)
 {
 	struct obj_array oa;
 	char encoded[] = "{\"elements\":["
-		"{\"name\":\"Sim\303\263n Bol\303\255var\",\"height\":168},"
-		"{\"name\":\"Muggsy Bogues\",\"height\":160},"
-		"{\"name\":\"Pel\303\251\",\"height\":173},"
-		"{\"name\":\"Hakeem Olajuwon\",\"height\":213},"
-		"{\"name\":\"Alex Honnold\",\"height\":180},"
-		"{\"name\":\"Hazel Findlay\",\"height\":157},"
-		"{\"name\":\"Daila Ojeda\",\"height\":158},"
-		"{\"name\":\"Albert Einstein\",\"height\":172},"
-		"{\"name\":\"Usain Bolt\",\"height\":195},"
-		"{\"name\":\"Paavo Nurmi\",\"height\":174}"
+		"{\"name\":\"Sim\303\263n Bol\303\255var\",\"name_buf\":\"Sim\303\263n\",\"height\":168},"
+		"{\"name\":\"Muggsy Bogues\",\"name_buf\":\"Muggsy\",\"height\":160},"
+		"{\"name\":\"Pel\303\251\",\"name_buf\":\"Pel\303\251\",\"height\":173},"
+		"{\"name\":\"Hakeem Olajuwon\",\"name_buf\":\"Hakeem\",\"height\":213},"
+		"{\"name\":\"Alex Honnold\",\"name_buf\":\"Alex\",\"height\":180},"
+		"{\"name\":\"Hazel Findlay\",\"name_buf\":\"Hazel\",\"height\":157},"
+		"{\"name\":\"Daila Ojeda\",\"name_buf\":\"Daila\",\"height\":158},"
+		"{\"name\":\"Albert Einstein\",\"name_buf\":\"Albert\",\"height\":172},"
+		"{\"name\":\"Usain Bolt\",\"name_buf\":\"Usain\",\"height\":195},"
+		"{\"name\":\"Paavo Nurmi\",\"name_buf\":\"Paavo\",\"height\":174}"
 		"]}";
 	const struct obj_array expected = {
 		.elements = {
-			[0] = { .name = "Sim\303\263n Bol\303\255var", .height = 168 },
-			[1] = { .name = "Muggsy Bogues",               .height = 160 },
-			[2] = { .name = "Pel\303\251",                 .height = 173 },
-			[3] = { .name = "Hakeem Olajuwon",             .height = 213 },
-			[4] = { .name = "Alex Honnold",                .height = 180 },
-			[5] = { .name = "Hazel Findlay",               .height = 157 },
-			[6] = { .name = "Daila Ojeda",                 .height = 158 },
-			[7] = { .name = "Albert Einstein",             .height = 172 },
-			[8] = { .name = "Usain Bolt",                  .height = 195 },
-			[9] = { .name = "Paavo Nurmi",                 .height = 174 },
+			[0] = {
+				.name = "Sim\303\263n Bol\303\255var",
+				.name_buf = "Sim\303\263n",
+				.height = 168 },
+			[1] = {
+				.name = "Muggsy Bogues",
+				.name_buf = "Muggsy",
+				.height = 160 },
+			[2] = {
+				.name = "Pel\303\251",
+				.name_buf = "Pel\303\251",
+				.height = 173 },
+			[3] = {
+				.name = "Hakeem Olajuwon",
+				.name_buf = "Hakeem",
+				.height = 213 },
+			[4] = {
+				.name = "Alex Honnold",
+				.name_buf = "Alex",
+				.height = 180 },
+			[5] = {
+				.name = "Hazel Findlay",
+				.name_buf = "Hazel",
+				.height = 157 },
+			[6] = {
+				.name = "Daila Ojeda",
+				.name_buf = "Daila",
+				.height = 158 },
+			[7] = {
+				.name = "Albert Einstein",
+				.name_buf = "Albert",
+				.height = 172 },
+			[8] = {
+				.name = "Usain Bolt",
+				.name_buf = "Usain",
+				.height = 195 },
+			[9] = {
+				.name = "Paavo Nurmi",
+				.name_buf = "Paavo",
+				.height = 174 },
 		},
 		.num_elements = 10,
 	};
@@ -659,14 +1308,17 @@ ZTEST(lib_json_test, test_json_2dim_arr_obj_encoding)
 				.elements = {
 					[0] = {
 						.name = "Sim\303\263n Bol\303\255var",
+						.name_buf = "Sim\303\263n",
 						.height = 168
 					},
 					[1] = {
 						.name = "Pel\303\251",
+						.name_buf = "Pel\303\251",
 						.height = 173
 					},
 					[2] = {
 						.name = "Usain Bolt",
+						.name_buf = "Usain",
 						.height = 195
 					},
 				},
@@ -676,10 +1328,12 @@ ZTEST(lib_json_test, test_json_2dim_arr_obj_encoding)
 				.elements = {
 					[0] = {
 						.name = "Muggsy Bogues",
+						.name_buf = "Muggsy",
 						.height = 160
 					},
 					[1] = {
 						.name = "Hakeem Olajuwon",
+						.name_buf = "Hakeem",
 						.height = 213
 					},
 				},
@@ -689,18 +1343,22 @@ ZTEST(lib_json_test, test_json_2dim_arr_obj_encoding)
 				.elements = {
 					[0] = {
 						.name = "Alex Honnold",
+						.name_buf = "Alex",
 						.height = 180
 					},
 					[1] = {
 						.name = "Hazel Findlay",
+						.name_buf = "Hazel",
 						.height = 157
 					},
 					[2] = {
 						.name = "Daila Ojeda",
+						.name_buf = "Daila",
 						.height = 158
 					},
 					[3] = {
 						.name = "Albert Einstein",
+						.name_buf = "Albert",
 						.height = 172
 					},
 				},
@@ -710,15 +1368,15 @@ ZTEST(lib_json_test, test_json_2dim_arr_obj_encoding)
 		.objects_array_array_len = 3,
 	};
 	char encoded[] = "{\"objects_array_array\":["
-		"[{\"name\":\"Sim\303\263n Bol\303\255var\",\"height\":168},"
-		 "{\"name\":\"Pel\303\251\",\"height\":173},"
-		 "{\"name\":\"Usain Bolt\",\"height\":195}],"
-		"[{\"name\":\"Muggsy Bogues\",\"height\":160},"
-		 "{\"name\":\"Hakeem Olajuwon\",\"height\":213}],"
-		"[{\"name\":\"Alex Honnold\",\"height\":180},"
-		 "{\"name\":\"Hazel Findlay\",\"height\":157},"
-		 "{\"name\":\"Daila Ojeda\",\"height\":158},"
-		 "{\"name\":\"Albert Einstein\",\"height\":172}]"
+		"[{\"name\":\"Sim\303\263n Bol\303\255var\",\"name_buf\":\"Sim\303\263n\",\"height\":168},"
+		 "{\"name\":\"Pel\303\251\",\"name_buf\":\"Pel\303\251\",\"height\":173},"
+		 "{\"name\":\"Usain Bolt\",\"name_buf\":\"Usain\",\"height\":195}],"
+		"[{\"name\":\"Muggsy Bogues\",\"name_buf\":\"Muggsy\",\"height\":160},"
+		 "{\"name\":\"Hakeem Olajuwon\",\"name_buf\":\"Hakeem\",\"height\":213}],"
+		"[{\"name\":\"Alex Honnold\",\"name_buf\":\"Alex\",\"height\":180},"
+		 "{\"name\":\"Hazel Findlay\",\"name_buf\":\"Hazel\",\"height\":157},"
+		 "{\"name\":\"Daila Ojeda\",\"name_buf\":\"Daila\",\"height\":158},"
+		 "{\"name\":\"Albert Einstein\",\"name_buf\":\"Albert\",\"height\":172}]"
 		"]}";
 	char buffer[sizeof(encoded)];
 	int ret;
@@ -740,14 +1398,17 @@ ZTEST(lib_json_test, test_json_2dim_arr_extra_obj_encoding)
 				.elements = {
 					[0] = {
 						.name = "Sim\303\263n Bol\303\255var",
+						.name_buf = "Sim\303\263n",
 						.height = 168
 					},
 					[1] = {
 						.name = "Pel\303\251",
+						.name_buf = "Pel\303\251",
 						.height = 173
 					},
 					[2] = {
 						.name = "Usain Bolt",
+						.name_buf = "Usain",
 						.height = 195
 					},
 				},
@@ -757,10 +1418,12 @@ ZTEST(lib_json_test, test_json_2dim_arr_extra_obj_encoding)
 				.elements = {
 					[0] = {
 						.name = "Muggsy Bogues",
+						.name_buf = "Muggsy",
 						.height = 160
 					},
 					[1] = {
 						.name = "Hakeem Olajuwon",
+						.name_buf = "Hakeem",
 						.height = 213
 					},
 				},
@@ -770,18 +1433,22 @@ ZTEST(lib_json_test, test_json_2dim_arr_extra_obj_encoding)
 				.elements = {
 					[0] = {
 						.name = "Alex Honnold",
+						.name_buf = "Alex",
 						.height = 180
 					},
 					[1] = {
 						.name = "Hazel Findlay",
+						.name_buf = "Hazel",
 						.height = 157
 					},
 					[2] = {
 						.name = "Daila Ojeda",
+						.name_buf = "Daila",
 						.height = 158
 					},
 					[3] = {
 						.name = "Albert Einstein",
+						.name_buf = "Albert",
 						.height = 172
 					},
 				},
@@ -793,15 +1460,15 @@ ZTEST(lib_json_test, test_json_2dim_arr_extra_obj_encoding)
 
 	char encoded[] = "{\"name\":\"Paavo Nurmi\",\"val\":123,"
 		"\"obj_array_2dim\":["
-		"[{\"name\":\"Sim\303\263n Bol\303\255var\",\"height\":168},"
-		 "{\"name\":\"Pel\303\251\",\"height\":173},"
-		 "{\"name\":\"Usain Bolt\",\"height\":195}],"
-		"[{\"name\":\"Muggsy Bogues\",\"height\":160},"
-		 "{\"name\":\"Hakeem Olajuwon\",\"height\":213}],"
-		"[{\"name\":\"Alex Honnold\",\"height\":180},"
-		 "{\"name\":\"Hazel Findlay\",\"height\":157},"
-		 "{\"name\":\"Daila Ojeda\",\"height\":158},"
-		 "{\"name\":\"Albert Einstein\",\"height\":172}]"
+		"[{\"name\":\"Sim\303\263n Bol\303\255var\",\"name_buf\":\"Sim\303\263n\",\"height\":168},"
+		 "{\"name\":\"Pel\303\251\",\"name_buf\":\"Pel\303\251\",\"height\":173},"
+		 "{\"name\":\"Usain Bolt\",\"name_buf\":\"Usain\",\"height\":195}],"
+		"[{\"name\":\"Muggsy Bogues\",\"name_buf\":\"Muggsy\",\"height\":160},"
+		 "{\"name\":\"Hakeem Olajuwon\",\"name_buf\":\"Hakeem\",\"height\":213}],"
+		"[{\"name\":\"Alex Honnold\",\"name_buf\":\"Alex\",\"height\":180},"
+		 "{\"name\":\"Hazel Findlay\",\"name_buf\":\"Hazel\",\"height\":157},"
+		 "{\"name\":\"Daila Ojeda\",\"name_buf\":\"Daila\",\"height\":158},"
+		 "{\"name\":\"Albert Einstein\",\"name_buf\":\"Albert\",\"height\":172}]"
 		"]}";
 	char buffer[sizeof(encoded)];
 	int ret;
@@ -823,14 +1490,17 @@ ZTEST(lib_json_test, test_json_2dim_arr_extra_named_obj_encoding)
 				.elements = {
 					[0] = {
 						.name = "Sim\303\263n Bol\303\255var",
+						.name_buf = "Sim\303\263n",
 						.height = 168
 					},
 					[1] = {
 						.name = "Pel\303\251",
+						.name_buf = "Pel\303\251",
 						.height = 173
 					},
 					[2] = {
 						.name = "Usain Bolt",
+						.name_buf = "Usain",
 						.height = 195
 					},
 				},
@@ -840,10 +1510,12 @@ ZTEST(lib_json_test, test_json_2dim_arr_extra_named_obj_encoding)
 				.elements = {
 					[0] = {
 						.name = "Muggsy Bogues",
+						.name_buf = "Muggsy",
 						.height = 160
 					},
 					[1] = {
 						.name = "Hakeem Olajuwon",
+						.name_buf = "Hakeem",
 						.height = 213
 					},
 				},
@@ -853,18 +1525,22 @@ ZTEST(lib_json_test, test_json_2dim_arr_extra_named_obj_encoding)
 				.elements = {
 					[0] = {
 						.name = "Alex Honnold",
+						.name_buf = "Alex",
 						.height = 180
 					},
 					[1] = {
 						.name = "Hazel Findlay",
+						.name_buf = "Hazel",
 						.height = 157
 					},
 					[2] = {
 						.name = "Daila Ojeda",
+						.name_buf = "Daila",
 						.height = 158
 					},
 					[3] = {
 						.name = "Albert Einstein",
+						.name_buf = "Albert",
 						.height = 172
 					},
 				},
@@ -876,15 +1552,15 @@ ZTEST(lib_json_test, test_json_2dim_arr_extra_named_obj_encoding)
 
 	char encoded[] = "{\"name\":\"Paavo Nurmi\",\"val\":123,"
 		"\"data\":["
-		"[{\"name\":\"Sim\303\263n Bol\303\255var\",\"height\":168},"
-		 "{\"name\":\"Pel\303\251\",\"height\":173},"
-		 "{\"name\":\"Usain Bolt\",\"height\":195}],"
-		"[{\"name\":\"Muggsy Bogues\",\"height\":160},"
-		 "{\"name\":\"Hakeem Olajuwon\",\"height\":213}],"
-		"[{\"name\":\"Alex Honnold\",\"height\":180},"
-		 "{\"name\":\"Hazel Findlay\",\"height\":157},"
-		 "{\"name\":\"Daila Ojeda\",\"height\":158},"
-		 "{\"name\":\"Albert Einstein\",\"height\":172}]"
+		"[{\"name\":\"Sim\303\263n Bol\303\255var\",\"name_buf\":\"Sim\303\263n\",\"height\":168},"
+		 "{\"name\":\"Pel\303\251\",\"name_buf\":\"Pel\303\251\",\"height\":173},"
+		 "{\"name\":\"Usain Bolt\",\"name_buf\":\"Usain\",\"height\":195}],"
+		"[{\"name\":\"Muggsy Bogues\",\"name_buf\":\"Muggsy\",\"height\":160},"
+		 "{\"name\":\"Hakeem Olajuwon\",\"name_buf\":\"Hakeem\",\"height\":213}],"
+		"[{\"name\":\"Alex Honnold\",\"name_buf\":\"Alex\",\"height\":180},"
+		 "{\"name\":\"Hazel Findlay\",\"name_buf\":\"Hazel\",\"height\":157},"
+		 "{\"name\":\"Daila Ojeda\",\"name_buf\":\"Daila\",\"height\":158},"
+		 "{\"name\":\"Albert Einstein\",\"name_buf\":\"Albert\",\"height\":172}]"
 		"]}";
 	char buffer[sizeof(encoded)];
 	int ret;
@@ -901,15 +1577,15 @@ ZTEST(lib_json_test, test_json_2dim_obj_arr_decoding)
 {
 	struct obj_array_2dim oaa;
 	char encoded[] = "{\"objects_array_array\":["
-		"[{\"name\":\"Sim\303\263n Bol\303\255var\",\"height\":168},"
-		 "{\"name\":\"Pel\303\251\",\"height\":173},"
-		 "{\"name\":\"Usain Bolt\",\"height\":195}],"
-		"[{\"name\":\"Muggsy Bogues\",\"height\":160},"
-		 "{\"name\":\"Hakeem Olajuwon\",\"height\":213}],"
-		"[{\"name\":\"Alex Honnold\",\"height\":180},"
-		 "{\"name\":\"Hazel Findlay\",\"height\":157},"
-		 "{\"name\":\"Daila Ojeda\",\"height\":158},"
-		 "{\"name\":\"Albert Einstein\",\"height\":172}]"
+		"[{\"name\":\"Sim\303\263n Bol\303\255var\",\"name_buf\":\"Sim\303\263n\",\"height\":168},"
+		 "{\"name\":\"Pel\303\251\",\"name_buf\":\"Pel\303\251\",\"height\":173},"
+		 "{\"name\":\"Usain Bolt\",\"name_buf\":\"Usain\",\"height\":195}],"
+		"[{\"name\":\"Muggsy Bogues\",\"name_buf\":\"Muggsy\",\"height\":160},"
+		 "{\"name\":\"Hakeem Olajuwon\",\"name_buf\":\"Hakeem\",\"height\":213}],"
+		"[{\"name\":\"Alex Honnold\",\"name_buf\":\"Alex\",\"height\":180},"
+		 "{\"name\":\"Hazel Findlay\",\"name_buf\":\"Hazel\",\"height\":157},"
+		 "{\"name\":\"Daila Ojeda\",\"name_buf\":\"Daila\",\"height\":158},"
+		 "{\"name\":\"Albert Einstein\",\"name_buf\":\"Albert\",\"height\":172}]"
 		"]}";
 	const struct obj_array_2dim expected = {
 		.objects_array_array = {
@@ -917,14 +1593,17 @@ ZTEST(lib_json_test, test_json_2dim_obj_arr_decoding)
 				.elements = {
 					[0] = {
 						.name = "Sim\303\263n Bol\303\255var",
+						.name_buf = "Sim\303\263n",
 						.height = 168
 					},
 					[1] = {
 						.name = "Pel\303\251",
+						.name_buf = "Pel\303\251",
 						.height = 173
 					},
 					[2] = {
 						.name = "Usain Bolt",
+						.name_buf = "Usain",
 						.height = 195
 					},
 				},
@@ -934,10 +1613,12 @@ ZTEST(lib_json_test, test_json_2dim_obj_arr_decoding)
 				.elements = {
 					[0] = {
 						.name = "Muggsy Bogues",
+						.name_buf = "Muggsy",
 						.height = 160
 					},
 					[1] = {
 						.name = "Hakeem Olajuwon",
+						.name_buf = "Hakeem",
 						.height = 213
 					},
 				},
@@ -947,18 +1628,22 @@ ZTEST(lib_json_test, test_json_2dim_obj_arr_decoding)
 				.elements = {
 					[0] = {
 						.name = "Alex Honnold",
+						.name_buf = "Alex",
 						.height = 180
 					},
 					[1] = {
 						.name = "Hazel Findlay",
+						.name_buf = "Hazel",
 						.height = 157
 					},
 					[2] = {
 						.name = "Daila Ojeda",
+						.name_buf = "Daila",
 						.height = 158
 					},
 					[3] = {
 						.name = "Albert Einstein",
+						.name_buf = "Albert",
 						.height = 172
 					},
 				},
@@ -989,6 +1674,9 @@ ZTEST(lib_json_test, test_json_2dim_obj_arr_decoding)
 			zassert_true(!strcmp(oaa.objects_array_array[i].elements[j].name,
 					     expected.objects_array_array[i].elements[j].name),
 				     "Element [%d][%d] name not decoded correctly", i, j);
+			zassert_true(!strcmp(oaa.objects_array_array[i].elements[j].name_buf,
+					     expected.objects_array_array[i].elements[j].name_buf),
+				     "Element [%d][%d] name array not decoded correctly", i, j);
 			zassert_equal(oaa.objects_array_array[i].elements[j].height,
 				      expected.objects_array_array[i].elements[j].height,
 				      "Element [%d][%d] height not decoded correctly", i, j);
@@ -996,6 +1684,52 @@ ZTEST(lib_json_test, test_json_2dim_obj_arr_decoding)
 	}
 }
 
+ZTEST(lib_json_test, test_json_string_array_size)
+{
+	int ret;
+	struct elt elt_ts;
+	char encoded[] = "{\"name_buf\":\"a12345678\"}";
+
+	ret = json_obj_parse(encoded, sizeof(encoded),
+			     elt_descr,
+			     ARRAY_SIZE(elt_descr),
+			     &elt_ts);
+
+	/* size of name_buf is 10 */
+	zassert_str_equal(elt_ts.name_buf,
+			  "a12345678", "String not decoded correctly");
+}
+
+ZTEST(lib_json_test, test_json_string_array_empty)
+{
+	int ret;
+	struct elt elt_ts;
+	char encoded[] = "{\"name_buf\":\"\"}";
+
+	ret = json_obj_parse(encoded, sizeof(encoded),
+			     elt_descr,
+			     ARRAY_SIZE(elt_descr),
+			     &elt_ts);
+
+	/* size of name_buf is 10 */
+	zassert_str_equal(elt_ts.name_buf, "", "String not decoded correctly");
+}
+
+ZTEST(lib_json_test, test_json_string_array_max)
+{
+	int ret;
+	struct elt elt_ts;
+	char encoded[] = "{\"name_buf\":\"a123456789\"}";
+
+	ret = json_obj_parse(encoded, sizeof(encoded),
+			     elt_descr,
+			     ARRAY_SIZE(elt_descr),
+			     &elt_ts);
+
+	/* string does not fit into name_buf */
+	zassert_equal(ret, -EINVAL, "Decoding has to fail");
+}
+
 struct encoding_test {
 	char *str;
 	int result;
@@ -1362,4 +2096,88 @@ ZTEST(lib_json_test, test_json_array_alignment)
 	zassert_equal(o.array[1].int3, 6, "Element 1 int3 not decoded correctly");
 }
 
+ZTEST(lib_json_test, test_json_array_alignment_bool)
+{
+	char encoded[] = "{\"array\":["
+			 "{\"bool1\":true,\"int1\":1,\"bool2\":false},"
+			 "{\"bool1\":true,\"int1\":2,\"bool2\":false}"
+			 "]}";
+
+	struct test_alignment_bool o = { 0 };
+	int64_t ret = json_obj_parse(encoded, sizeof(encoded) - 1, alignment_bool_descr,
+				     ARRAY_SIZE(alignment_bool_descr), &o);
+
+	zassert_false(ret < 0, "json_obj_parse returned error %d", ret);
+	zassert_equal(o.num_elements, 2, "Number of elements not decoded correctly");
+
+	zassert_equal(o.array[0].bool1, true, "Element 0 bool1 not decoded correctly");
+	zassert_equal(o.array[0].int1, 1, "Element 0 int1 not decoded correctly");
+	zassert_equal(o.array[0].bool2, false, "Element 0 bool2 not decoded correctly");
+
+	zassert_equal(o.array[1].bool1, true, "Element 1 bool1 not decoded correctly");
+	zassert_equal(o.array[1].int1, 2, "Element 1 int1 not decoded correctly");
+	zassert_equal(o.array[1].bool2, false, "Element 1 bool2 not decoded correctly");
+}
+
+ZTEST(lib_json_test, test_json_invalid_int)
+{
+	struct sub_test {
+		char str[30];
+		int result;
+	};
+	struct sub_test encoded[] = {
+		{ "{\"int8_cero\":128}", -EINVAL },
+		{ "{\"int8_cero\":-129}", -EINVAL },
+		{ "{\"uint8_cero\":257}", -EINVAL },
+		{ "{\"int16_cero\":32768}", -EINVAL },
+		{ "{\"int16_cero\":-32769}", -EINVAL },
+		{ "{\"uint16_cero\":65536}", -EINVAL },
+	};
+
+	struct test_int_limits ts;
+	int ret;
+
+	for (int i = 0; i < ARRAY_SIZE(encoded); i++) {
+		ret = json_obj_parse(encoded[i].str, strlen(encoded[i].str),
+				     obj_limits_descr, ARRAY_SIZE(obj_limits_descr), &ts);
+		zassert_equal(ret, encoded[i].result,
+			      "Decoding '%s' result %d, expected %d",
+			      encoded[i].str, ret, encoded[i].result);
+	}
+}
+
+ZTEST(lib_json_test, test_json_enums)
+{
+	int ret = 0;
+	char encoded[] = "{\"i8\":-128,"
+			 "\"u8\":255,"
+			 "\"i16\":-32768,"
+			 "\"u16\":65535,"
+			 "\"i32\":-2147483648,"
+			 "\"u32\":4294967295"
+			 "}";
+
+	struct test_enums enums = {
+		.i8 = I8_MIN,
+		.u8 = U8_MAX,
+		.i16 = I16_MIN,
+		.u16 = U16_MAX,
+		.i32 = I32_MIN,
+		.u32 = U32_MAX,
+	};
+
+	char buffer[sizeof(encoded)];
+	struct test_enums enums_decoded = {0};
+
+	ret = json_obj_encode_buf(enums_descr, ARRAY_SIZE(enums_descr),
+				&enums, buffer, sizeof(buffer));
+	ret = json_obj_parse(encoded, sizeof(encoded) - 1, enums_descr,
+			     ARRAY_SIZE(enums_descr), &enums_decoded);
+
+	zassert_str_equal(encoded, buffer,
+			  "Enums not encoded correctly");
+	zassert_true(!memcmp(&enums, &enums_decoded, sizeof(enums)),
+		     "Enums not decoded correctly");
+}
+
 ZTEST_SUITE(lib_json_test, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/lib/math/interpolation/src/main.c b/tests/lib/math/interpolation/src/main.c
index 95753a1decf..807947919be 100644
--- a/tests/lib/math/interpolation/src/main.c
+++ b/tests/lib/math/interpolation/src/main.c
@@ -6,6 +6,18 @@
 #include <math.h>
 
 #include <zephyr/ztest.h>
+
+#ifdef __clang__
+/*
+ * Floating-point contraction merges an operation of the form (a*b + c) from
+ * two operations (fmul, fadd) into a single operation (fmadd). This can change
+ * the value of the resulting LSB, causing problems when the expected value is
+ * some multiple of 0.5f and the rounding functions are used. Disable
+ * contraction for the tests to ensure this doesn't occur.
+ */
+#pragma STDC FP_CONTRACT OFF
+#endif
+
 #include <zephyr/math/interpolation.h>
 
 ZTEST(interpolation, test_interpolation_oob)
diff --git a/tests/lib/math/interpolation/testcase.yaml b/tests/lib/math/interpolation/testcase.yaml
index fd3eafb51df..94eff1a469d 100644
--- a/tests/lib/math/interpolation/testcase.yaml
+++ b/tests/lib/math/interpolation/testcase.yaml
@@ -2,6 +2,6 @@
 # SPDX-License-Identifier: Apache-2.0
 
 tests:
-  math.interpolation:
+  utilities.math.interpolation:
     integration_platforms:
       - native_sim
diff --git a/tests/lib/mem_alloc/src/main.c b/tests/lib/mem_alloc/src/main.c
index d71835f7b64..d9ccd151a93 100644
--- a/tests/lib/mem_alloc/src/main.c
+++ b/tests/lib/mem_alloc/src/main.c
@@ -16,29 +16,26 @@
  * it guarantee that ALL functionality provided is working correctly.
  */
 
-#if defined(__GNUC__)
-/*
- * Don't complain about ridiculous alloc size requests
- */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Walloc-size-larger-than="
-#endif
-
 #define _BSD_SOURCE
 #include <zephyr/kernel.h>
 #include <zephyr/ztest.h>
+#include <zephyr/test_toolchain.h>
 #include <stdlib.h>
 #include <errno.h>
 #include <time.h>
 #include <stdint.h>
 
+/*
+ * Don't complain about ridiculous alloc size requests
+ */
+TOOLCHAIN_DISABLE_GCC_WARNING(TOOLCHAIN_WARNING_ALLOC_SIZE_LARGER_THAN)
+
 #define TOO_BIG PTRDIFF_MAX
 
 /**
  *
  * @brief Test implementation-defined constants library
- * @defgroup libc_api
- * @ingroup all_tests
+ * @ingroup libc_api
  * @{
  *
  */
@@ -351,10 +348,6 @@ ZTEST(c_lib_dynamic_memalloc, test_memalloc_all)
 	reloc_ptr = NULL;
 }
 
-/**
- * @}
- */
-
 /**
  *
  * @brief Test dynamic memory allocation upto maximum size
@@ -377,4 +370,8 @@ ZTEST(c_lib_dynamic_memalloc, test_memalloc_max)
 }
 #endif
 
+/**
+ * @}
+ */
+
 ZTEST_SUITE(c_lib_dynamic_memalloc, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/lib/mpsc_pbuf/testcase.yaml b/tests/lib/mpsc_pbuf/testcase.yaml
index 50d9722e426..98b18f64d3a 100644
--- a/tests/lib/mpsc_pbuf/testcase.yaml
+++ b/tests/lib/mpsc_pbuf/testcase.yaml
@@ -15,7 +15,6 @@ tests:
       - qemu_x86
       - qemu_x86_64
       - qemu_xtensa/dc233c
-      - native_posix
       - native_sim
     integration_platforms:
       - native_sim
diff --git a/tests/lib/multi_heap/src/test_mheap.h b/tests/lib/multi_heap/src/test_mheap.h
index 99749e5b914..a8b238cf591 100644
--- a/tests/lib/multi_heap/src/test_mheap.h
+++ b/tests/lib/multi_heap/src/test_mheap.h
@@ -7,5 +7,5 @@
 #define TIMEOUT 2000
 #define BLK_SIZE_MIN 64
 #define BLK_SIZE_MAX (BLK_SIZE_MIN << 2)
-#define BLK_NUM_MAX (CONFIG_HEAP_MEM_POOL_SIZE / BLK_SIZE_MIN)
-#define BLK_NUM_MIN (CONFIG_HEAP_MEM_POOL_SIZE / (BLK_SIZE_MIN << 2))
+#define BLK_NUM_MAX (K_HEAP_MEM_POOL_SIZE / BLK_SIZE_MIN)
+#define BLK_NUM_MIN (K_HEAP_MEM_POOL_SIZE / (BLK_SIZE_MIN << 2))
diff --git a/tests/lib/multi_heap/src/test_mheap_api.c b/tests/lib/multi_heap/src/test_mheap_api.c
index 9c1a4210ed6..dff17cea2db 100644
--- a/tests/lib/multi_heap/src/test_mheap_api.c
+++ b/tests/lib/multi_heap/src/test_mheap_api.c
@@ -10,11 +10,13 @@
 #include <zephyr/sys/multi_heap.h>
 #include "test_mheap.h"
 
-#define STACK_SIZE (512 + CONFIG_TEST_EXTRA_STACK_SIZE)
+#define MALLOC_IN_THREAD_STACK_SIZE (512 + CONFIG_TEST_EXTRA_STACK_SIZE)
+#define INCREMENTAL_FILL_STACK_SIZE (512 + CONFIG_TEST_EXTRA_STACK_SIZE + \
+				     (BLK_NUM_MAX * sizeof(void *) * 2))
 #define OVERFLOW_SIZE    SIZE_MAX
 
 #define NMEMB   8
-#define SIZE    16
+#define SIZE    (K_HEAP_MEM_POOL_SIZE / NMEMB / 2)
 #define BOUNDS  (NMEMB * SIZE)
 
 #define N_MULTI_HEAPS 4
@@ -24,48 +26,17 @@ static struct sys_multi_heap multi_heap;
 static char heap_mem[N_MULTI_HEAPS][MHEAP_BYTES];
 static struct sys_heap mheaps[N_MULTI_HEAPS];
 
-K_SEM_DEFINE(thread_sem, 0, 1);
-K_THREAD_STACK_DEFINE(tstack, STACK_SIZE);
-struct k_thread tdata;
+K_SEM_DEFINE(malloc_in_thread_sem, 0, 1);
+K_THREAD_STACK_DEFINE(malloc_in_thread_tstack, MALLOC_IN_THREAD_STACK_SIZE);
+struct k_thread malloc_in_thread_tdata;
 
-static void tIsr_malloc_and_free(void *data)
-{
-	ARG_UNUSED(data);
-	void *ptr;
+K_THREAD_STACK_DEFINE(malloc_free_tstack, INCREMENTAL_FILL_STACK_SIZE);
+struct k_thread malloc_free_tdata;
 
-	ptr = (char *)z_thread_malloc(BLK_SIZE_MIN);
-	zassert_not_null(ptr, "bytes allocation failed from system pool");
-	k_free(ptr);
-}
+K_THREAD_STACK_DEFINE(realloc_tstack, INCREMENTAL_FILL_STACK_SIZE);
+struct k_thread realloc_tdata;
 
-static void thread_entry(void *p1, void *p2, void *p3)
-{
-	void *ptr;
-
-	k_current_get()->resource_pool = NULL;
-
-	ptr = (char *)z_thread_malloc(BLK_SIZE_MIN);
-	zassert_is_null(ptr, "bytes allocation failed from system pool");
-
-	k_sem_give(&thread_sem);
-}
-
-/*test cases*/
-
-/**
- * @brief Test to demonstrate k_malloc() and k_free() API usage
- *
- * @ingroup kernel_heap_tests
- *
- * @details The test allocates 4 blocks from heap memory pool
- * using k_malloc() API. It also tries to allocate a block of size
- * 64 bytes which fails as all the memory is allocated up. It then
- * validates k_free() API by freeing up all the blocks which were
- * allocated from the heap memory.
- *
- * @see k_malloc()
- */
-ZTEST(mheap_api, test_mheap_malloc_free)
+static void malloc_free_handler(void *p1, void *p2, void *p3)
 {
 	void *block[2 * BLK_NUM_MAX], *block_fail;
 	int nb;
@@ -101,7 +72,29 @@ ZTEST(mheap_api, test_mheap_malloc_free)
 	zassert_is_null(block_fail, NULL);
 }
 
-ZTEST(mheap_api, test_mheap_realloc)
+static void tIsr_malloc_and_free(void *data)
+{
+	ARG_UNUSED(data);
+	void *ptr;
+
+	ptr = (char *)z_thread_malloc(BLK_SIZE_MIN);
+	zassert_not_null(ptr, "bytes allocation failed from system pool");
+	k_free(ptr);
+}
+
+static void malloc_in_thread_handler(void *p1, void *p2, void *p3)
+{
+	void *ptr;
+
+	k_current_get()->resource_pool = NULL;
+
+	ptr = (char *)z_thread_malloc(BLK_SIZE_MIN);
+	zassert_is_null(ptr, "bytes allocation failed from system pool");
+
+	k_sem_give(&malloc_in_thread_sem);
+}
+
+static void realloc_handler(void *p1, void *p2, void *p3)
 {
 	void *block1, *block2;
 	size_t nb;
@@ -126,6 +119,18 @@ ZTEST(mheap_api, test_mheap_realloc)
 		}
 	}
 
+	/* For boards whose subsystems use the heap and leave holes, deplete
+	 * remaining memory using k_malloc
+	 */
+	void *holes[BLK_NUM_MAX * 2];
+
+	for (int i = 0; i < (BLK_NUM_MAX * 2); i++) {
+		holes[i] = k_malloc(BLK_SIZE_MIN);
+		if (holes[i] == NULL) {
+			break;
+		}
+	}
+
 	/* Allocate buffer2 when the heap has been depleted */
 	block2 = k_realloc(NULL, BLK_SIZE_MIN);
 	/* Should fail and return NULL */
@@ -160,12 +165,67 @@ ZTEST(mheap_api, test_mheap_realloc)
 	/* Free block1 with k_realloc() this time */
 	block1 = k_realloc(block1, 0);
 	zassert_is_null(block1);
+
+	/* Free holes */
+	for (int i = 0; i < (BLK_NUM_MAX * 2); i++) {
+		if (holes[i] == NULL) {
+			break;
+		}
+		k_free(holes[i]);
+	}
+}
+
+/*test cases*/
+
+/**
+ * @brief Test to demonstrate k_malloc() and k_free() API usage
+ *
+ * @ingroup k_heap_api_tests
+ *
+ * @details The test allocates 4 blocks from heap memory pool
+ * using k_malloc() API. It also tries to allocate a block of size
+ * 64 bytes which fails as all the memory is allocated up. It then
+ * validates k_free() API by freeing up all the blocks which were
+ * allocated from the heap memory.
+ *
+ * @see k_malloc()
+ */
+ZTEST(mheap_api, test_mheap_malloc_free)
+{
+	if (!IS_ENABLED(CONFIG_MULTITHREADING)) {
+		return;
+	}
+
+	k_tid_t tid = k_thread_create(&malloc_free_tdata, malloc_free_tstack,
+				 INCREMENTAL_FILL_STACK_SIZE,
+				 malloc_free_handler,
+				 NULL, NULL, NULL,
+				 K_PRIO_PREEMPT(1), 0, K_NO_WAIT);
+
+	k_thread_join(tid, K_FOREVER);
+}
+
+
+
+ZTEST(mheap_api, test_mheap_realloc)
+{
+	if (!IS_ENABLED(CONFIG_MULTITHREADING)) {
+		return;
+	}
+
+	k_tid_t tid = k_thread_create(&realloc_tdata, realloc_tstack,
+				 INCREMENTAL_FILL_STACK_SIZE,
+				 realloc_handler,
+				 NULL, NULL, NULL,
+				 K_PRIO_PREEMPT(1), 0, K_NO_WAIT);
+
+	k_thread_join(tid, K_FOREVER);
 }
 
 /**
  * @brief Test to demonstrate k_calloc() API functionality.
  *
- * @ingroup kernel_heap_tests
+ * @ingroup k_heap_api_tests
  *
  * @details The test validates k_calloc() API. When requesting a
  * huge size of space or a space larger than heap memory,
@@ -239,7 +299,7 @@ ZTEST(mheap_api, test_k_aligned_alloc)
  * a block of memory smaller than the pool and will fail when alloc
  * a block of memory larger than the pool.
  *
- * @ingroup kernel_heap_tests
+ * @ingroup k_heap_api_tests
  *
  * @see k_thread_system_pool_assign(), z_thread_malloc(), k_free()
  */
@@ -256,7 +316,7 @@ ZTEST(mheap_api, test_sys_heap_mem_pool_assign)
 	zassert_not_null(ptr, "bytes allocation failed from system pool");
 	k_free(ptr);
 
-	zassert_is_null((char *)z_thread_malloc(BLK_SIZE_MAX * 2),
+	zassert_is_null((char *)z_thread_malloc(K_HEAP_MEM_POOL_SIZE * 2),
 						"overflow check failed");
 }
 
@@ -268,7 +328,7 @@ ZTEST(mheap_api, test_sys_heap_mem_pool_assign)
  * memory because in this situation, the kernel will assign the heap memory
  * as resource pool.
  *
- * @ingroup kernel_heap_tests
+ * @ingroup k_heap_api_tests
  *
  * @see z_thread_malloc(), k_free()
  */
@@ -287,7 +347,7 @@ ZTEST(mheap_api, test_malloc_in_isr)
  *
  * @details When a thread's resource pool is not assigned, alloc memory will fail.
  *
- * @ingroup kernel_heap_tests
+ * @ingroup k_heap_api_tests
  *
  * @see z_thread_malloc()
  */
@@ -297,11 +357,12 @@ ZTEST(mheap_api, test_malloc_in_thread)
 		return;
 	}
 
-	k_tid_t tid = k_thread_create(&tdata, tstack, STACK_SIZE,
-			      thread_entry, NULL, NULL, NULL,
-			      0, 0, K_NO_WAIT);
+	k_tid_t tid = k_thread_create(&malloc_in_thread_tdata, malloc_in_thread_tstack,
+				 MALLOC_IN_THREAD_STACK_SIZE, malloc_in_thread_handler,
+				 NULL, NULL, NULL,
+				 0, 0, K_NO_WAIT);
 
-	k_sem_take(&thread_sem, K_FOREVER);
+	k_sem_take(&malloc_in_thread_sem, K_FOREVER);
 
 	k_thread_abort(tid);
 }
diff --git a/tests/lib/multi_heap/src/test_mheap_concept.c b/tests/lib/multi_heap/src/test_mheap_concept.c
index 6dd7bca956c..efd331ad41e 100644
--- a/tests/lib/multi_heap/src/test_mheap_concept.c
+++ b/tests/lib/multi_heap/src/test_mheap_concept.c
@@ -7,21 +7,49 @@
 #include <zephyr/ztest.h>
 #include "test_mheap.h"
 
-#define THREAD_NUM 3
-#define BLOCK_SIZE 16
-#define STACK_SIZE (512 + CONFIG_TEST_EXTRA_STACK_SIZE)
+#define THREADSAFE_THREAD_NUM 3
+#define THREADSAFE_BLOCK_SIZE 16
+#define THREADSAFE_STACK_SIZE (512 + CONFIG_TEST_EXTRA_STACK_SIZE)
+#define MALLOC_ALIGN4_STACK_SIZE (512 + (BLK_NUM_MAX * sizeof(void *)))
 
-struct k_sem sync_sema;
-static K_THREAD_STACK_ARRAY_DEFINE(tstack, THREAD_NUM, STACK_SIZE);
-static struct k_thread tdata[THREAD_NUM];
-static void *pool_blocks[BLK_NUM_MAX];
+struct k_sem threadsafe_sema;
+static K_THREAD_STACK_ARRAY_DEFINE(threadsafe_tstack, THREADSAFE_THREAD_NUM, THREADSAFE_STACK_SIZE);
+static struct k_thread threadsafe_tdata[THREADSAFE_THREAD_NUM];
+
+static void *threadsafe_pool_blocks[BLK_NUM_MAX];
+
+static K_THREAD_STACK_DEFINE(malloc_align4_tstack, MALLOC_ALIGN4_STACK_SIZE);
+static struct k_thread malloc_align4_tdata;
 
 /*test cases*/
 
+static void tmheap_malloc_align4_handler(void *p1, void *p2, void *p3)
+{
+	void *block[BLK_NUM_MAX];
+	int i;
+
+	/**
+	 * TESTPOINT: The address of the allocated chunk is guaranteed to be
+	 * aligned on a word boundary (4 or 8 bytes).
+	 */
+	for (i = 0; i < BLK_NUM_MAX; i++) {
+		block[i] = k_malloc(i);
+		if (block[i] == NULL) {
+			break;
+		}
+		zassert_false((uintptr_t)block[i] % sizeof(void *));
+	}
+
+	/* test case tear down*/
+	for (int j = 0; j < i; j++) {
+		k_free(block[j]);
+	}
+}
+
 /**
  * @brief The test validates k_calloc() API.
  *
- * @ingroup kernel_heap_tests
+ * @ingroup k_heap_api_tests
  *
  * @details The 8 blocks of memory of size 16 bytes are allocated
  * by k_calloc() API. When allocated using k_calloc() the memory buffers
@@ -33,33 +61,28 @@ static void *pool_blocks[BLK_NUM_MAX];
  */
 ZTEST(mheap_api, test_mheap_malloc_align4)
 {
-	void *block[BLK_NUM_MAX];
-
-	/**
-	 * TESTPOINT: The address of the allocated chunk is guaranteed to be
-	 * aligned on a word boundary (4 or 8 bytes).
-	 */
-	for (int i = 0; i < BLK_NUM_MAX; i++) {
-		block[i] = k_malloc(i);
-		zassert_not_null(block[i], NULL);
-		zassert_false((uintptr_t)block[i] % sizeof(void *));
+	if (!IS_ENABLED(CONFIG_MULTITHREADING)) {
+		return;
 	}
 
-	/* test case tear down*/
-	for (int i = 0; i < BLK_NUM_MAX; i++) {
-		k_free(block[i]);
-	}
+	k_tid_t tid = k_thread_create(&malloc_align4_tdata, malloc_align4_tstack,
+				 MALLOC_ALIGN4_STACK_SIZE,
+				 tmheap_malloc_align4_handler,
+				 NULL, NULL, NULL,
+				 K_PRIO_PREEMPT(1), 0, K_NO_WAIT);
+
+	k_thread_join(tid, K_FOREVER);
 }
 
-static void tmheap_handler(void *p1, void *p2, void *p3)
+static void tmheap_threadsafe_handler(void *p1, void *p2, void *p3)
 {
 	int thread_id = POINTER_TO_INT(p1);
 
-	pool_blocks[thread_id] = k_malloc(BLOCK_SIZE);
+	threadsafe_pool_blocks[thread_id] = k_malloc(THREADSAFE_BLOCK_SIZE);
 
-	zassert_not_null(pool_blocks[thread_id], "memory is not allocated");
+	zassert_not_null(threadsafe_pool_blocks[thread_id], "memory is not allocated");
 
-	k_sem_give(&sync_sema);
+	k_sem_give(&threadsafe_sema);
 }
 
 /**
@@ -78,24 +101,25 @@ ZTEST(mheap_api, test_mheap_threadsafe)
 		return;
 	}
 
-	k_tid_t tid[THREAD_NUM];
+	k_tid_t tid[THREADSAFE_THREAD_NUM];
 
-	k_sem_init(&sync_sema, 0, THREAD_NUM);
+	k_sem_init(&threadsafe_sema, 0, THREADSAFE_THREAD_NUM);
 
 	/* create multiple threads to invoke same memory heap APIs*/
-	for (int i = 0; i < THREAD_NUM; i++) {
-		tid[i] = k_thread_create(&tdata[i], tstack[i], STACK_SIZE,
-					 tmheap_handler, INT_TO_POINTER(i), NULL, NULL,
+	for (int i = 0; i < THREADSAFE_THREAD_NUM; i++) {
+		tid[i] = k_thread_create(&threadsafe_tdata[i], threadsafe_tstack[i],
+					 THREADSAFE_STACK_SIZE, tmheap_threadsafe_handler,
+					 INT_TO_POINTER(i), NULL, NULL,
 					 K_PRIO_PREEMPT(1), 0, K_NO_WAIT);
 	}
 
-	for (int i = 0; i < THREAD_NUM; i++) {
-		k_sem_take(&sync_sema, K_FOREVER);
+	for (int i = 0; i < THREADSAFE_THREAD_NUM; i++) {
+		k_sem_take(&threadsafe_sema, K_FOREVER);
 	}
 
-	for (int i = 0; i < THREAD_NUM; i++) {
+	for (int i = 0; i < THREADSAFE_THREAD_NUM; i++) {
 		/* verify free mheap in main thread */
-		k_free(pool_blocks[i]);
+		k_free(threadsafe_pool_blocks[i]);
 		k_thread_abort(tid[i]);
 	}
 }
diff --git a/tests/lib/ringbuffer/src/concurrent.c b/tests/lib/ringbuffer/src/concurrent.c
index 60e9aa1c263..913109aa60f 100644
--- a/tests/lib/ringbuffer/src/concurrent.c
+++ b/tests/lib/ringbuffer/src/concurrent.c
@@ -262,7 +262,7 @@ static void test_ztress(ztress_handler high_handler,
 		uint32_t buf32[32];
 	} buf;
 	k_timeout_t timeout;
-	int32_t offset;
+	uint32_t offset;
 
 	if (item_mode) {
 		ring_buf_item_init(&ringbuf, ARRAY_SIZE(buf.buf32), buf.buf32);
@@ -270,8 +270,8 @@ static void test_ztress(ztress_handler high_handler,
 		ring_buf_init(&ringbuf, ARRAY_SIZE(buf.buf8), buf.buf8);
 	}
 
-	/* force internal 32-bit index roll-over */
-	offset = INT32_MAX - ring_buf_capacity_get(&ringbuf)/2;
+	/* force internal index roll-over */
+	offset = (ring_buf_idx_t)-1 - ring_buf_capacity_get(&ringbuf)/2;
 	ring_buf_internal_reset(&ringbuf, offset);
 
 	/* Timeout after 5 seconds. */
diff --git a/tests/lib/smf/src/test_lib_hierarchical_5_ancestor_smf.c b/tests/lib/smf/src/test_lib_hierarchical_5_ancestor_smf.c
index bd62e9bb110..0393ca47761 100644
--- a/tests/lib/smf/src/test_lib_hierarchical_5_ancestor_smf.c
+++ b/tests/lib/smf/src/test_lib_hierarchical_5_ancestor_smf.c
@@ -412,11 +412,11 @@ static void d_entry(void *obj)
 }
 
 static const struct smf_state test_states[] = {
-	[P05] SMF_CREATE_STATE(p05_entry, p05_run, p05_exit, NULL, NULL),
-	[P04] SMF_CREATE_STATE(p04_entry, p04_run, p04_exit, &test_states[P05], NULL),
-	[P03] SMF_CREATE_STATE(p03_entry, p03_run, p03_exit, &test_states[P04], NULL),
-	[P02] SMF_CREATE_STATE(p02_entry, p02_run, p02_exit, &test_states[P03], NULL),
-	[P01] SMF_CREATE_STATE(p01_entry, p01_run, p01_exit, &test_states[P02], NULL),
+	[P05] = SMF_CREATE_STATE(p05_entry, p05_run, p05_exit, NULL, NULL),
+	[P04] = SMF_CREATE_STATE(p04_entry, p04_run, p04_exit, &test_states[P05], NULL),
+	[P03] = SMF_CREATE_STATE(p03_entry, p03_run, p03_exit, &test_states[P04], NULL),
+	[P02] = SMF_CREATE_STATE(p02_entry, p02_run, p02_exit, &test_states[P03], NULL),
+	[P01] = SMF_CREATE_STATE(p01_entry, p01_run, p01_exit, &test_states[P02], NULL),
 	[A] = SMF_CREATE_STATE(a_entry, a_run, a_exit, &test_states[P01], NULL),
 	[B] = SMF_CREATE_STATE(b_entry, b_run, b_exit, &test_states[P01], NULL),
 	[C] = SMF_CREATE_STATE(c_entry, c_run, c_exit, NULL, NULL),
diff --git a/tests/lib/sprintf/src/main.c b/tests/lib/sprintf/src/main.c
index 8395be690ff..d582516a0b7 100644
--- a/tests/lib/sprintf/src/main.c
+++ b/tests/lib/sprintf/src/main.c
@@ -12,14 +12,14 @@
  */
 
 #include <zephyr/ztest.h>
+#include <zephyr/test_toolchain.h>
 #include <stdio.h>
 #include <stdarg.h>
 
 /**
  *
  * @brief Test implementation-defined constants library
- * @defgroup libc_api
- * @ingroup all_tests
+ * @ingroup libc_api
  * @{
  *
  */
@@ -499,7 +499,6 @@ ZTEST(sprintf, test_vsprintf)
 
 ZTEST(sprintf, test_snprintf)
 {
-#if defined(__GNUC__) && __GNUC__ >= 7
 	/*
 	 * GCC 7 and newer are smart enough to realize that in the statements
 	 * below, the output will not fit in 0 or 4 bytes, but that it requires
@@ -508,9 +507,7 @@ ZTEST(sprintf, test_snprintf)
 	 * actually testing that snprintf's return value is what it should be
 	 * while truncating the output. So let's suppress this warning here.
 	 */
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wformat-truncation"
-#endif
+	TOOLCHAIN_DISABLE_GCC_WARNING(TOOLCHAIN_WARNING_FORMAT_TRUNCATION);
 
 	int len;
 	char buffer[100];
@@ -535,9 +532,7 @@ ZTEST(sprintf, test_snprintf)
 		     "snprintf(%%x).  Expected '%s', got '%s'\n",
 		     "dea", buffer);
 
-#if defined(__GNUC__) && __GNUC__ >= 7
-#pragma GCC diagnostic pop
-#endif
+	TOOLCHAIN_ENABLE_GCC_WARNING(TOOLCHAIN_WARNING_FORMAT_TRUNCATION);
 }
 
 /**
diff --git a/tests/lib/time/testcase.yaml b/tests/lib/time/testcase.yaml
index bf949559f03..89e04c825f0 100644
--- a/tests/lib/time/testcase.yaml
+++ b/tests/lib/time/testcase.yaml
@@ -4,6 +4,3 @@ tests:
     timeout: 180
     integration_platforms:
       - mps2/an385
-    platform_exclude:
-      - native_posix
-      - native_posix/native/64
diff --git a/tests/lib/uuid/CMakeLists.txt b/tests/lib/uuid/CMakeLists.txt
new file mode 100644
index 00000000000..e08cac8aab0
--- /dev/null
+++ b/tests/lib/uuid/CMakeLists.txt
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(uuid)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/lib/uuid/prj.conf b/tests/lib/uuid/prj.conf
new file mode 100644
index 00000000000..0f507ccdffa
--- /dev/null
+++ b/tests/lib/uuid/prj.conf
@@ -0,0 +1,2 @@
+CONFIG_ZTEST=y
+CONFIG_UUID=y
diff --git a/tests/lib/uuid/src/main.c b/tests/lib/uuid/src/main.c
new file mode 100644
index 00000000000..b8607767e40
--- /dev/null
+++ b/tests/lib/uuid/src/main.c
@@ -0,0 +1,294 @@
+/*
+ * Copyright (c) 2025, SECO Mind Srl
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/ztest.h>
+#include <zephyr/sys/uuid.h>
+
+#ifdef CONFIG_UUID_V4
+ZTEST(uuid, test_uuid_v4)
+{
+	struct uuid gen_uuid = {0};
+
+	int result = uuid_generate_v4(&gen_uuid);
+	/* Check version and variant fields */
+	zassert_true(result == 0, "uuid_generate_v4 returned an error");
+	zassert_equal(gen_uuid.val[6U] >> 4U, 4U,
+		      "Generated UUID v4 contains an incorrect 'ver' field");
+	zassert_equal(gen_uuid.val[8U] >> 6U, 2U,
+		      "Generated UUID v4 contains an incorrect 'var' field");
+}
+#else
+ZTEST(uuid, test_uuid_v4)
+{
+	ztest_test_skip();
+}
+#endif
+
+#ifdef CONFIG_UUID_V5
+ZTEST(uuid, test_uuid_v5)
+{
+	struct uuid namespace;
+	int result;
+	struct uuid gen_uuid;
+	char uuid_str[UUID_STR_LEN];
+
+	result = uuid_from_string("6ba7b810-9dad-11d1-80b4-00c04fd430c8", &namespace);
+	zassert_true(result == 0, "uuid_from_string returned an error");
+	result = uuid_generate_v5(&namespace, "www.example.com", 15, &gen_uuid);
+	zassert_true(result == 0, "uuid_generate_v5 returned an error");
+	result = uuid_to_string(&gen_uuid, uuid_str);
+	zassert_true(result == 0, "uuid_to_string returned an error");
+	zassert_str_equal("2ed6657d-e927-568b-95e1-2665a8aea6a2", uuid_str,
+			  "uuid_str != 2ed6657d-e927-568b-95e1-2665a8aea6a2");
+}
+#else
+ZTEST(uuid, test_uuid_v5)
+{
+	ztest_test_skip();
+}
+#endif
+
+ZTEST(uuid, test_uuid_copy)
+{
+	int result;
+	const char *data_str = "6ba7b810-9dad-11d1-80b4-00c04fd430c8";
+	struct uuid data;
+	struct uuid out;
+	char out_str[UUID_STR_LEN] = {0};
+
+	result = uuid_from_string(data_str, &data);
+	zassert_true(result == 0, "uuid_from_string returned an error");
+	result = uuid_copy(&data, &out);
+	zassert_true(result == 0, "uuid_copy returned an error");
+	result = uuid_to_string(&out, out_str);
+	zassert_true(result == 0, "uuid_to_string returned an error");
+	zassert_str_equal(out_str, data_str, "Expected %s, gotten: %s", data_str, out_str);
+}
+
+ZTEST(uuid, test_uuid_from_buffer)
+{
+	uint8_t uuid_buffer[UUID_SIZE] = {0x44, 0xb3, 0x5f, 0x73, 0xcf, 0xbd, 0x43, 0xb4,
+					  0x8f, 0xef, 0xca, 0x7b, 0xae, 0xa1, 0x37, 0x5f};
+	struct uuid gen_uuid;
+	char uuid_string[UUID_STR_LEN] = {0};
+	const char *expected_uuid_string = "44b35f73-cfbd-43b4-8fef-ca7baea1375f";
+	int res;
+
+	res = uuid_from_buffer(uuid_buffer, &gen_uuid);
+	zassert_equal(0, res, "uuid_from_buffer returned an error");
+	res = uuid_to_string(&gen_uuid, uuid_string);
+	zassert_equal(0, res, "uuid_to_string returned an error");
+	zassert_str_equal(expected_uuid_string, uuid_string, "expected %s", expected_uuid_string);
+}
+
+ZTEST(uuid, test_uuid_from_string)
+{
+	const char *first_uuid_v4_string = "44b35f73-cfbd-43b4-8fef-ca7baea1375f";
+	const char *second_uuid_v4_string = "6f2fd4cb-94a0-41c7-8d27-864c6b13b8c0";
+	const char *third_uuid_v4_string = "8f65dbbc-5868-4015-8523-891cc0bffa58";
+	const char *first_uuid_v5_string = "0575a569-51eb-575c-afe4-ce7fc03bcdc5";
+
+	struct uuid first_uuid_v4;
+	struct uuid second_uuid_v4;
+	struct uuid third_uuid_v4;
+	struct uuid first_uuid_v5;
+
+	uint8_t expected_first_uuid_v4_byte_array[UUID_SIZE] = {0x44, 0xb3, 0x5f, 0x73, 0xcf, 0xbd,
+								0x43, 0xb4, 0x8f, 0xef, 0xca, 0x7b,
+								0xae, 0xa1, 0x37, 0x5f};
+	uint8_t expected_second_uuid_v4_byte_array[UUID_SIZE] = {0x6f, 0x2f, 0xd4, 0xcb, 0x94, 0xa0,
+								 0x41, 0xc7, 0x8d, 0x27, 0x86, 0x4c,
+								 0x6b, 0x13, 0xb8, 0xc0};
+	uint8_t expected_third_uuid_v4_byte_array[UUID_SIZE] = {0x8f, 0x65, 0xdb, 0xbc, 0x58, 0x68,
+								0x40, 0x15, 0x85, 0x23, 0x89, 0x1c,
+								0xc0, 0xbf, 0xfa, 0x58};
+	uint8_t expected_first_uuid_v5_byte_array[UUID_SIZE] = {0x05, 0x75, 0xa5, 0x69, 0x51, 0xeb,
+								0x57, 0x5c, 0xaf, 0xe4, 0xce, 0x7f,
+								0xc0, 0x3b, 0xcd, 0xc5};
+
+	int res;
+
+	res = uuid_from_string(first_uuid_v4_string, &first_uuid_v4);
+	zassert_equal(0, res, "uuid_from_string returned an error");
+	zassert_mem_equal(first_uuid_v4.val, expected_first_uuid_v4_byte_array, UUID_SIZE,
+			  "first_uuid != from expected value");
+
+	res = uuid_from_string(second_uuid_v4_string, &second_uuid_v4);
+	zassert_equal(0, res, "uuid_from_string returned an error");
+	zassert_mem_equal(second_uuid_v4.val, expected_second_uuid_v4_byte_array, UUID_SIZE,
+			  "second_uuid != from expected value");
+
+	res = uuid_from_string(third_uuid_v4_string, &third_uuid_v4);
+	zassert_equal(0, res, "uuid_from_string returned an error");
+	zassert_mem_equal(third_uuid_v4.val, expected_third_uuid_v4_byte_array, UUID_SIZE,
+			  "third_uuid != from expected value");
+
+	res = uuid_from_string(first_uuid_v5_string, &first_uuid_v5);
+	zassert_equal(0, res, "uuid_from_string returned an error");
+	zassert_mem_equal(first_uuid_v5.val, expected_first_uuid_v5_byte_array, UUID_SIZE,
+			  "uuid_v5 != from expected value");
+}
+
+ZTEST(uuid, test_uuid_from_string_errors)
+{
+	const char *uuid_string_missing_hyphen = "44b35f73-cfbd-43b4-8fef0ca7baea1375f";
+	const char *uuid_string_non_hex_digit = "44b35f73-cfLd-43b4-8fef-ca7baea1375f";
+
+	int res;
+	struct uuid gen_uuid;
+
+	res = uuid_from_string(NULL, &gen_uuid);
+	zassert_equal(-EINVAL, res, "uuid_from_string returned incorrect error");
+
+	res = uuid_from_string(uuid_string_missing_hyphen, &gen_uuid);
+	zassert_equal(-EINVAL, res, "uuid_from_string returned incorrect error");
+
+	res = uuid_from_string(uuid_string_non_hex_digit, &gen_uuid);
+	zassert_equal(-EINVAL, res, "uuid_from_string returned incorrect error");
+}
+
+ZTEST(uuid, test_uuid_to_buffer)
+{
+	int result;
+	const char *input_str = "44b35f73-cfbd-43b4-8fef-ca7baea1375f";
+	struct uuid input;
+	uint8_t buffer[UUID_SIZE] = {0};
+	uint8_t expected_buffer[UUID_SIZE] = {0x44, 0xb3, 0x5f, 0x73, 0xcf, 0xbd, 0x43, 0xb4,
+					      0x8f, 0xef, 0xca, 0x7b, 0xae, 0xa1, 0x37, 0x5f};
+
+	result = uuid_from_string(input_str, &input);
+	zassert_true(result == 0, "uuid_from_string returned an error");
+	result = uuid_to_buffer(&input, buffer);
+	zassert_true(result == 0, "uuid_to_buffer returned an error");
+	zassert_mem_equal(buffer, expected_buffer, UUID_SIZE,
+			  "Incorrect buffer converted to buffer");
+}
+
+ZTEST(uuid, test_uuid_to_string)
+{
+	struct uuid first_uuid_v4 = {.val = {0x44, 0xb3, 0x5f, 0x73, 0xcf, 0xbd, 0x43, 0xb4, 0x8f,
+					     0xef, 0xca, 0x7b, 0xae, 0xa1, 0x37, 0x5f}};
+	struct uuid second_uuid_v4 = {.val = {0x6f, 0x2f, 0xd4, 0xcb, 0x94, 0xa0, 0x41, 0xc7, 0x8d,
+					      0x27, 0x86, 0x4c, 0x6b, 0x13, 0xb8, 0xc0}};
+	struct uuid first_uuid_v5 = {.val = {0x05, 0x75, 0xa5, 0x69, 0x51, 0xeb, 0x57, 0x5c, 0xaf,
+					     0xe4, 0xce, 0x7f, 0xc0, 0x3b, 0xcd, 0xc5}};
+
+	char first_uuid_v4_string[UUID_STR_LEN];
+	char second_uuid_v4_string[UUID_STR_LEN];
+	char first_uuid_v5_string[UUID_STR_LEN];
+
+	const char *expected_first_uuid_v4_string = "44b35f73-cfbd-43b4-8fef-ca7baea1375f";
+	const char *expected_second_uuid_v4_string = "6f2fd4cb-94a0-41c7-8d27-864c6b13b8c0";
+	const char *expected_first_uuid_v5_string = "0575a569-51eb-575c-afe4-ce7fc03bcdc5";
+
+	int err;
+
+	err = uuid_to_string(&first_uuid_v4, first_uuid_v4_string);
+	zassert_equal(0, err, "uuid_to_string returned an error");
+	zassert_str_equal(expected_first_uuid_v4_string, first_uuid_v4_string, "expected %s",
+			  expected_first_uuid_v4_string);
+
+	err = uuid_to_string(&second_uuid_v4, second_uuid_v4_string);
+	zassert_equal(0, err, "uuid_to_string returned an error");
+	zassert_str_equal(expected_second_uuid_v4_string, second_uuid_v4_string, "expected %s",
+			  expected_second_uuid_v4_string);
+
+	err = uuid_to_string(&first_uuid_v5, first_uuid_v5_string);
+	zassert_equal(0, err, "uuid_to_string returned an error");
+	zassert_str_equal(expected_first_uuid_v5_string, first_uuid_v5_string, "expected %s",
+			  expected_first_uuid_v5_string);
+}
+
+#ifdef CONFIG_UUID_BASE64
+ZTEST(uuid, test_uuid_to_base64)
+{
+	char first_uuid_v4_base64[UUID_BASE64_LEN] = {0};
+	char second_uuid_v4_base64[UUID_BASE64_LEN] = {0};
+	char first_uuid_v5_base64[UUID_BASE64_LEN] = {0};
+
+	struct uuid first_uuid_v4 = {.val = {0x44, 0xb3, 0x5f, 0x73, 0xcf, 0xbd, 0x43, 0xb4, 0x8f,
+					     0xef, 0xca, 0x7b, 0xae, 0xa1, 0x37, 0x5f}};
+	struct uuid second_uuid_v4 = {.val = {0x6f, 0x2f, 0xd4, 0xcb, 0x94, 0xa0, 0x41, 0xc7, 0x8d,
+					      0x27, 0x86, 0x4c, 0x6b, 0x13, 0xb8, 0xc0}};
+	struct uuid first_uuid_v5 = {.val = {0x05, 0x75, 0xa5, 0x69, 0x51, 0xeb, 0x57, 0x5c, 0xaf,
+					     0xe4, 0xce, 0x7f, 0xc0, 0x3b, 0xcd, 0xc5}};
+
+	char expected_first_uuid_v4_base64[] = "RLNfc8+9Q7SP78p7rqE3Xw==";
+	char expected_second_uuid_v4_base64[] = "by/Uy5SgQceNJ4ZMaxO4wA==";
+	char expected_first_uuid_v5_base64[] = "BXWlaVHrV1yv5M5/wDvNxQ==";
+
+	int err;
+
+	err = uuid_to_base64(&first_uuid_v4, first_uuid_v4_base64);
+	zassert_equal(0, err, "uuid_to_base64 returned an error");
+	zassert_str_equal(expected_first_uuid_v4_base64, first_uuid_v4_base64,
+			  "expected: '%s', gotten: '%s'", expected_first_uuid_v4_base64,
+			  first_uuid_v4_base64);
+
+	err = uuid_to_base64(&second_uuid_v4, second_uuid_v4_base64);
+	zassert_equal(0, err, "uuid_to_base64 returned an error");
+	zassert_str_equal(expected_second_uuid_v4_base64, second_uuid_v4_base64,
+			  "expected: '%s', gotten: '%s'", expected_second_uuid_v4_base64,
+			  second_uuid_v4_base64);
+
+	err = uuid_to_base64(&first_uuid_v5, first_uuid_v5_base64);
+	zassert_equal(0, err, "uuid_to_base64 returned an error");
+	zassert_str_equal(expected_first_uuid_v5_base64, first_uuid_v5_base64,
+			  "expected: '%s', gotten: '%s'", expected_first_uuid_v5_base64,
+			  first_uuid_v5_base64);
+}
+#else
+ZTEST(uuid, test_uuid_to_base64)
+{
+	ztest_test_skip();
+}
+#endif
+
+#ifdef CONFIG_UUID_BASE64
+ZTEST(uuid, test_uuid_to_base64url)
+{
+	char first_uuid_v4_base64url[UUID_BASE64URL_LEN] = {0};
+	char second_uuid_v4_base64url[UUID_BASE64URL_LEN] = {0};
+	char first_uuid_v5_base64url[UUID_BASE64URL_LEN] = {0};
+
+	struct uuid first_uuid_v4 = {.val = {0x44, 0xb3, 0x5f, 0x73, 0xcf, 0xbd, 0x43, 0xb4, 0x8f,
+					     0xef, 0xca, 0x7b, 0xae, 0xa1, 0x37, 0x5f}};
+	struct uuid second_uuid_v4 = {.val = {0x6f, 0x2f, 0xd4, 0xcb, 0x94, 0xa0, 0x41, 0xc7, 0x8d,
+					      0x27, 0x86, 0x4c, 0x6b, 0x13, 0xb8, 0xc0}};
+	struct uuid first_uuid_v5 = {.val = {0x05, 0x75, 0xa5, 0x69, 0x51, 0xeb, 0x57, 0x5c, 0xaf,
+					     0xe4, 0xce, 0x7f, 0xc0, 0x3b, 0xcd, 0xc5}};
+
+	char expected_first_uuid_v4_base64url[] = "RLNfc8-9Q7SP78p7rqE3Xw";
+	char expected_second_uuid_v4_base64url[] = "by_Uy5SgQceNJ4ZMaxO4wA";
+	char expected_first_uuid_v5_base64url[] = "BXWlaVHrV1yv5M5_wDvNxQ";
+
+	int err;
+
+	err = uuid_to_base64url(&first_uuid_v4, first_uuid_v4_base64url);
+	zassert_equal(0, err, "uuid_to_base64url returned an error");
+	zassert_str_equal(expected_first_uuid_v4_base64url, first_uuid_v4_base64url,
+			  "expected: '%s', gotten: '%s'", expected_first_uuid_v4_base64url,
+			  first_uuid_v4_base64url);
+
+	err = uuid_to_base64url(&second_uuid_v4, second_uuid_v4_base64url);
+	zassert_equal(0, err, "uuid_to_base64url returned an error");
+	zassert_str_equal(expected_second_uuid_v4_base64url, second_uuid_v4_base64url,
+			  "expected: '%s', gotten: '%s'", expected_second_uuid_v4_base64url,
+			  second_uuid_v4_base64url);
+
+	err = uuid_to_base64url(&first_uuid_v5, first_uuid_v5_base64url);
+	zassert_equal(0, err, "uuid_to_base64url returned an error");
+	zassert_str_equal(expected_first_uuid_v5_base64url, first_uuid_v5_base64url,
+			  "expected: '%s', gotten: '%s'", expected_first_uuid_v5_base64url,
+			  first_uuid_v5_base64url);
+}
+#else
+ZTEST(uuid, test_uuid_to_base64url)
+{
+	ztest_test_skip();
+}
+#endif
+
+ZTEST_SUITE(uuid, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/lib/uuid/testcase.yaml b/tests/lib/uuid/testcase.yaml
new file mode 100644
index 00000000000..ebeda9b7eb0
--- /dev/null
+++ b/tests/lib/uuid/testcase.yaml
@@ -0,0 +1,19 @@
+common:
+  tags: uuid
+  integration_platforms:
+    - native_sim
+
+tests:
+  libraries.uuid.base:
+    extra_configs:
+      - CONFIG_UUID_V5=y
+      - CONFIG_MBEDTLS=y
+      - CONFIG_MBEDTLS_MD=y
+      - CONFIG_MBEDTLS_SHA1=y
+      - CONFIG_UUID_BASE64=y
+      - CONFIG_BASE64=y
+  libraries.uuid.v4:
+    extra_configs:
+      - CONFIG_UUID_V4=y
+      - CONFIG_ENTROPY_GENERATOR=y
+    filter: CONFIG_ENTROPY_HAS_DRIVER
diff --git a/tests/misc/iterable_sections/src/main.c b/tests/misc/iterable_sections/src/main.c
index 1feed8319b2..2c615ebfcc7 100644
--- a/tests/misc/iterable_sections/src/main.c
+++ b/tests/misc/iterable_sections/src/main.c
@@ -39,10 +39,10 @@ const STRUCT_SECTION_ITERABLE_NAMED(test_ram_named, D, ram8) = {0x04};
 const STRUCT_SECTION_ITERABLE_NAMED(test_ram_named, B, ram9) = {0x02};
 
 /* declare in random order to check that the linker is sorting numerically */
-const STRUCT_SECTION_ITERABLE(test_ram_numeric, ramn_1) = {0x01};
-const STRUCT_SECTION_ITERABLE(test_ram_numeric, ramn_10) = {0x03};
-const STRUCT_SECTION_ITERABLE(test_ram_numeric, ramn_11) = {0x04};
 const STRUCT_SECTION_ITERABLE(test_ram_numeric, ramn_3) = {0x02};
+const STRUCT_SECTION_ITERABLE(test_ram_numeric, ramn_1) = {0x01};
+const STRUCT_SECTION_ITERABLE(test_ram_numeric, ramn_99999) = {0x04};
+const STRUCT_SECTION_ITERABLE(test_ram_numeric, ramn_11) = {0x03};
 
 #define NAMED_ALT_EXPECT 0x4273
 
@@ -134,10 +134,10 @@ const STRUCT_SECTION_ITERABLE_NAMED(test_rom_named, D, rom8) = {0x40};
 const STRUCT_SECTION_ITERABLE_NAMED(test_rom_named, B, rom9) = {0x20};
 
 /* declare in random order to check that the linker is sorting numerically */
-const STRUCT_SECTION_ITERABLE(test_rom_numeric, romn_1) = {0x10};
-const STRUCT_SECTION_ITERABLE(test_rom_numeric, romn_10) = {0x30};
-const STRUCT_SECTION_ITERABLE(test_rom_numeric, romn_11) = {0x40};
 const STRUCT_SECTION_ITERABLE(test_rom_numeric, romn_3) = {0x20};
+const STRUCT_SECTION_ITERABLE(test_rom_numeric, romn_1) = {0x10};
+const STRUCT_SECTION_ITERABLE(test_rom_numeric, romn_99999) = {0x40};
+const STRUCT_SECTION_ITERABLE(test_rom_numeric, romn_11) = {0x30};
 
 /* alternate naming */
 const STRUCT_SECTION_ITERABLE_NAMED_ALTERNATE(test_rom_named, romn_alt, R, romn_73) = {0x73};
diff --git a/tests/misc/llext-edk/pytest/test_edk.py b/tests/misc/llext-edk/pytest/test_edk.py
index 860c4aefd59..9c5159373f3 100644
--- a/tests/misc/llext-edk/pytest/test_edk.py
+++ b/tests/misc/llext-edk/pytest/test_edk.py
@@ -10,16 +10,22 @@
 from subprocess import check_output
 
 import pytest
+import yaml
 from twister_harness import DeviceAdapter
 
 logger = logging.getLogger(__name__)
 
+
 def test_edk(unlaunched_dut: DeviceAdapter):
-    # Need to have the ZEPHYR_SDK_INSTALL_DIR environment variable set,
-    # otherwise can't actually build the edk
-    if os.environ.get("ZEPHYR_SDK_INSTALL_DIR") is None:
-        logger.warning("ZEPHYR_SDK_INSTALL_DIR is not set, skipping test")
-        pytest.skip("ZEPHYR_SDK_INSTALL_DIR is not set")
+    # Get the SDK path from build_info.yml
+    build_dir = str(unlaunched_dut.device_config.build_dir)
+    with open(Path(build_dir) / "build_info.yml") as f:
+        build_info = yaml.safe_load(f)
+        if build_info["cmake"]["toolchain"]["name"] != "zephyr":
+            logger.warning("This test requires the Zephyr SDK to be used, skipping")
+            pytest.skip("The Zephyr SDK must be used")
+
+        sdk_dir = build_info["cmake"]["toolchain"]["path"]
 
     # Can we build the edk?
     command = [
@@ -64,6 +70,7 @@ def test_edk(unlaunched_dut: DeviceAdapter):
             # knows where the EDK is installed
             edk_dir = Path(tempdir) / "llext-edk"
             env = os.environ.copy()
+            env.update({"ZEPHYR_SDK_INSTALL_DIR": sdk_dir})
             env.update({"LLEXT_EDK_INSTALL_DIR": edk_dir})
 
             # Build the extension using the edk
@@ -92,7 +99,7 @@ def test_edk(unlaunched_dut: DeviceAdapter):
                 "--build-dir",
                 unlaunched_dut.device_config.build_dir,
                 "--",
-                f"-DEXTENSION_DIR={tempdir_extension}/build/"
+                f"-DEXTENSION_DIR={tempdir_extension}/build/",
             ]
             logger.debug(f"west command: {command}")
             output = check_output(command, text=True)
diff --git a/tests/net/6lo/prj.conf b/tests/net/6lo/prj.conf
index ed070a9ce85..3e072737289 100644
--- a/tests/net/6lo/prj.conf
+++ b/tests/net/6lo/prj.conf
@@ -21,3 +21,5 @@ CONFIG_NET_6LO_CONTEXT=y
 #Before modifying this value, add respective code in src/main.c
 CONFIG_NET_MAX_6LO_CONTEXTS=2
 CONFIG_ZTEST=y
+
+CONFIG_NET_L2_IEEE802154=y
diff --git a/tests/net/6lo/src/main.c b/tests/net/6lo/src/main.c
index 17fbe090ab7..d911cda65c8 100644
--- a/tests/net/6lo/src/main.c
+++ b/tests/net/6lo/src/main.c
@@ -474,11 +474,11 @@ static struct net_pkt *create_pkt(struct net_6lo_data *data)
 
 	net_pkt_set_ip_hdr_len(pkt, NET_IPV6H_LEN);
 
-	net_pkt_lladdr_src(pkt)->addr = src_mac;
-	net_pkt_lladdr_src(pkt)->len = 8U;
+	(void)net_linkaddr_create(net_pkt_lladdr_src(pkt), src_mac,
+				  sizeof(src_mac), NET_LINK_IEEE802154);
 
-	net_pkt_lladdr_dst(pkt)->addr = dst_mac;
-	net_pkt_lladdr_dst(pkt)->len = 8U;
+	(void)net_linkaddr_create(net_pkt_lladdr_dst(pkt), dst_mac,
+				  sizeof(dst_mac), NET_LINK_IEEE802154);
 
 	frag = net_pkt_get_frag(pkt, NET_IPV6UDPH_LEN, K_FOREVER);
 	if (!frag) {
diff --git a/tests/net/6lo/testcase.yaml b/tests/net/6lo/testcase.yaml
index a6a1294f6d9..7db3a818a8f 100644
--- a/tests/net/6lo/testcase.yaml
+++ b/tests/net/6lo/testcase.yaml
@@ -3,7 +3,11 @@ common:
     - net
     - 6loWPAN
   min_ram: 32
-  depends_on: netif
+  platform_allow:
+    - native_sim
+    - native_sim/native/64
+  integration_platforms:
+    - native_sim
 tests:
   net.6lo:
     extra_configs:
diff --git a/tests/net/arp/src/main.c b/tests/net/arp/src/main.c
index 022abfb54c2..abcd037accc 100644
--- a/tests/net/arp/src/main.c
+++ b/tests/net/arp/src/main.c
@@ -149,24 +149,6 @@ static int tester_send(const struct device *dev, struct net_pkt *pkt)
 	return 0;
 }
 
-static inline struct in_addr *if_get_addr(struct net_if *iface)
-{
-	int i;
-
-	for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) {
-		if (iface->config.ip.ipv4->unicast[i].ipv4.is_used &&
-		    iface->config.ip.ipv4->unicast[i].ipv4.address.family ==
-								AF_INET &&
-		    iface->config.ip.ipv4->unicast[i].ipv4.addr_state ==
-							NET_ADDR_PREFERRED) {
-			return
-			    &iface->config.ip.ipv4->unicast[i].ipv4.address.in_addr;
-		}
-	}
-
-	return NULL;
-}
-
 static inline struct net_pkt *prepare_arp_reply(struct net_if *iface,
 						struct net_pkt *req,
 						struct net_eth_addr *addr,
@@ -215,6 +197,8 @@ static inline struct net_pkt *prepare_arp_reply(struct net_if *iface,
 
 	net_buf_add(pkt->buffer, sizeof(struct net_arp_hdr));
 
+	net_pkt_set_ll_proto_type(pkt, NET_ETH_PTYPE_ARP);
+
 	return pkt;
 }
 
@@ -265,6 +249,8 @@ static inline struct net_pkt *prepare_arp_request(struct net_if *iface,
 
 	net_buf_add(pkt->buffer, sizeof(struct net_arp_hdr));
 
+	net_pkt_set_ll_proto_type(pkt, NET_ETH_PTYPE_ARP);
+
 	return pkt;
 }
 
@@ -327,23 +313,27 @@ ZTEST(arp_fn_tests, test_arp)
 	}
 
 	struct net_eth_hdr *eth_hdr = NULL;
+	struct net_eth_addr dst_lladdr;
 	struct net_pkt *pkt;
 	struct net_pkt *pkt2;
+	struct net_pkt *pkt_arp;
 	struct net_if *iface;
 	struct net_if_addr *ifaddr;
 	struct net_arp_hdr *arp_hdr;
 	struct net_ipv4_hdr *ipv4;
-	int len;
+	int len, ret;
 
-	struct in_addr dst = { { { 192, 168, 0, 2 } } };
+	struct in_addr dst = { { { 192, 0, 2, 2 } } };
 	struct in_addr dst_far = { { { 10, 11, 12, 13 } } };
 	struct in_addr dst_far2 = { { { 172, 16, 14, 186 } } };
-	struct in_addr src = { { { 192, 168, 0, 1 } } };
+	struct in_addr src = { { { 192, 0, 2, 1 } } };
 	struct in_addr netmask = { { { 255, 255, 255, 0 } } };
-	struct in_addr gw = { { { 192, 168, 0, 42 } } };
+	struct in_addr gw = { { { 192, 0, 2, 42 } } };
 
 	net_arp_init();
 
+	(void)memset(&dst_lladdr, 0xff, sizeof(struct net_eth_addr));
+
 	iface = net_if_lookup_by_dev(DEVICE_GET(net_arp_test));
 
 	net_if_ipv4_set_gw(iface, &gw);
@@ -365,30 +355,43 @@ ZTEST(arp_fn_tests, test_arp)
 		len, AF_INET, 0, K_SECONDS(1));
 	zassert_not_null(pkt, "out of mem");
 
-	net_pkt_lladdr_src(pkt)->addr = (uint8_t *)net_if_get_link_addr(iface);
-	net_pkt_lladdr_src(pkt)->len = sizeof(struct net_eth_addr);
+	(void)net_linkaddr_set(net_pkt_lladdr_src(pkt),
+			       net_if_get_link_addr(iface)->addr,
+			       sizeof(struct net_eth_addr));
 
 	ipv4 = (struct net_ipv4_hdr *)net_buf_add(pkt->buffer,
 						  sizeof(struct net_ipv4_hdr));
 	net_ipv4_addr_copy_raw(ipv4->src, (uint8_t *)&src);
 	net_ipv4_addr_copy_raw(ipv4->dst, (uint8_t *)&dst);
 
+	net_pkt_set_ll_proto_type(pkt, NET_ETH_PTYPE_IP);
+
 	memcpy(net_buf_add(pkt->buffer, len), app_data, len);
 
-	pkt2 = net_arp_prepare(pkt, &dst, NULL);
+	/* Duplicate packet */
+	pkt2 = net_pkt_clone(pkt, K_SECONDS(1));
+	zassert_not_null(pkt2, "out of mem");
+
+	/* First ARP request */
+	ret = net_arp_prepare(pkt, &dst, NULL, &pkt_arp);
+
+	zassert_equal(NET_ARP_PKT_REPLACED, ret);
 
-	/* pkt2 is the ARP packet and pkt is the IPv4 packet and it was
+	/* pkt_arp is the ARP packet and pkt is the IPv4 packet and it was
 	 * stored in ARP table.
 	 */
 
+	zassert_equal(net_pkt_ll_proto_type(pkt_arp), NET_ETH_PTYPE_ARP,
+		      "ARP packet type is wrong");
+
 	/**TESTPOINTS: Check packets*/
-	zassert_not_equal((void *)(pkt2), (void *)(pkt),
+	zassert_not_equal((void *)(pkt_arp), (void *)(pkt),
 		/* The packets cannot be the same as the ARP cache has
 		 * still room for the pkt.
 		 */
 		"ARP cache should still have free space");
 
-	zassert_not_null(pkt2, "ARP pkt is empty");
+	zassert_not_null(pkt_arp, "ARP pkt is empty");
 
 	/* The ARP cache should now have a link to pending net_pkt
 	 * that is to be sent after we have got an ARP reply.
@@ -398,8 +401,8 @@ ZTEST(arp_fn_tests, test_arp)
 
 	pending_pkt = pkt;
 
-	/* pkt2 should contain the arp header, verify it */
-	arp_hdr = NET_ARP_HDR(pkt2);
+	/* pkt_arp should contain the arp header, verify it */
+	arp_hdr = NET_ARP_HDR(pkt_arp);
 
 	if (arp_hdr->hwtype != htons(NET_ARP_HTYPE_ETH)) {
 		printk("ARP hwtype 0x%x, should be 0x%x\n",
@@ -450,24 +453,41 @@ ZTEST(arp_fn_tests, test_arp)
 	/* We could have send the new ARP request but for this test we
 	 * just free it.
 	 */
-	net_pkt_unref(pkt2);
+	net_pkt_unref(pkt_arp);
 
 	zassert_equal(atomic_get(&pkt->atomic_ref), 2,
 		"ARP cache should own the original packet");
 
+
+	/* A second packet going to the same destination */
+	pkt_arp = NULL;
+	ret = net_arp_prepare(pkt2, &dst, NULL, &pkt_arp);
+
+	/* Packet should have been queued, not generating an ARP request */
+	zassert_equal(NET_ARP_PKT_QUEUED, ret);
+	zassert_is_null(pkt_arp, "ARP packet should not have been generated");
+
+	zassert_equal(atomic_get(&pkt2->atomic_ref), 2,
+		"ARP cache should own the original packet");
+
+	/* Done with the duplicate packet */
+	net_pkt_unref(pkt2);
+
 	/* Then a case where target is not in the same subnet */
 	net_ipv4_addr_copy_raw(ipv4->dst, (uint8_t *)&dst_far);
 
-	pkt2 = net_arp_prepare(pkt, &dst_far, NULL);
+	ret = net_arp_prepare(pkt, &dst_far, NULL, &pkt_arp);
 
-	zassert_not_equal((void *)(pkt2), (void *)(pkt),
+	zassert_equal(NET_ARP_PKT_REPLACED, ret);
+
+	zassert_not_equal((void *)(pkt_arp), (void *)(pkt),
 		"ARP cache should not find anything");
 
 	/**TESTPOINTS: Check if packets not empty*/
-	zassert_not_null(pkt2,
-		"ARP pkt2 is empty");
+	zassert_not_null(pkt_arp,
+		"ARP pkt_arp is empty");
 
-	arp_hdr = NET_ARP_HDR(pkt2);
+	arp_hdr = NET_ARP_HDR(pkt_arp);
 
 	if (!net_ipv4_addr_cmp_raw(arp_hdr->dst_ipaddr,
 				   (uint8_t *)&iface->config.ip.ipv4->gw)) {
@@ -477,7 +497,7 @@ ZTEST(arp_fn_tests, test_arp)
 		zassert_true(0, "exiting");
 	}
 
-	net_pkt_unref(pkt2);
+	net_pkt_unref(pkt_arp);
 
 	/* Try to find the same destination again, this should fail as there
 	 * is a pending request in ARP cache.
@@ -489,12 +509,23 @@ ZTEST(arp_fn_tests, test_arp)
 	 */
 	net_pkt_ref(pkt);
 
-	pkt2 = net_arp_prepare(pkt, &dst_far, NULL);
+	ret = net_arp_prepare(pkt, &dst_far, NULL, &pkt_arp);
 
-	zassert_not_null(pkt2,
+	zassert_equal(NET_ARP_PKT_REPLACED, ret);
+
+	zassert_not_null(pkt_arp,
 		"ARP cache is not sending the request again");
 
-	net_pkt_unref(pkt2);
+	net_pkt_unref(pkt_arp);
+
+	ret = net_arp_prepare(pkt, &dst_far, NULL, &pkt_arp);
+
+	zassert_equal(NET_ARP_PKT_REPLACED, ret);
+
+	zassert_not_null(pkt_arp,
+		"ARP cache is not sending the request again");
+
+	net_pkt_unref(pkt_arp);
 
 	/* Try to find the different destination, this should fail too
 	 * as the cache table should be full.
@@ -506,9 +537,11 @@ ZTEST(arp_fn_tests, test_arp)
 	 */
 	net_pkt_ref(pkt);
 
-	pkt2 = net_arp_prepare(pkt, &dst_far2, NULL);
+	ret = net_arp_prepare(pkt, &dst_far2, NULL, &pkt_arp);
+
+	zassert_equal(NET_ARP_PKT_REPLACED, ret);
 
-	zassert_not_null(pkt2,
+	zassert_not_null(pkt_arp,
 		"ARP cache did not send a req");
 
 	/* Restore the original address so that following test case can
@@ -530,12 +563,16 @@ ZTEST(arp_fn_tests, test_arp)
 	net_ipv4_addr_copy_raw(arp_hdr->dst_ipaddr, (uint8_t *)&dst);
 	net_ipv4_addr_copy_raw(arp_hdr->src_ipaddr, (uint8_t *)&src);
 
-	pkt2 = prepare_arp_reply(iface, pkt, &eth_hwaddr, &eth_hdr);
+	net_pkt_set_ll_proto_type(pkt, NET_ETH_PTYPE_ARP);
 
-	zassert_not_null(pkt2, "ARP reply generation failed.");
+	pkt_arp = prepare_arp_reply(iface, pkt, &eth_hwaddr, &eth_hdr);
+
+	zassert_not_null(pkt_arp, "ARP reply generation failed.");
 
 	/* The pending packet should now be sent */
-	switch (net_arp_input(pkt2, eth_hdr)) {
+	switch (net_arp_input(pkt_arp,
+			      (struct net_eth_addr *)net_pkt_lladdr_src(pkt_arp)->addr,
+			      &dst_lladdr)) {
 	case NET_OK:
 	case NET_CONTINUE:
 		break;
@@ -571,14 +608,18 @@ ZTEST(arp_fn_tests, test_arp)
 	net_ipv4_addr_copy_raw(arp_hdr->dst_ipaddr, (uint8_t *)&src);
 	net_ipv4_addr_copy_raw(arp_hdr->src_ipaddr, (uint8_t *)&dst);
 
-	pkt2 = prepare_arp_request(iface, pkt, &eth_hwaddr, &eth_hdr);
+	net_pkt_set_ll_proto_type(pkt, NET_ETH_PTYPE_ARP);
+
+	pkt_arp = prepare_arp_request(iface, pkt, &eth_hwaddr, &eth_hdr);
 
 	/**TESTPOINT: Check if ARP request generation failed*/
-	zassert_not_null(pkt2, "ARP request generation failed.");
+	zassert_not_null(pkt_arp, "ARP request generation failed.");
 
 	req_test = true;
 
-	switch (net_arp_input(pkt2, eth_hdr)) {
+	switch (net_arp_input(pkt_arp,
+			      (struct net_eth_addr *)net_pkt_lladdr_src(pkt_arp)->addr,
+			      &dst_lladdr)) {
 	case NET_OK:
 	case NET_CONTINUE:
 		break;
@@ -633,7 +674,12 @@ ZTEST(arp_fn_tests, test_arp)
 
 		net_buf_add(pkt->buffer, sizeof(struct net_arp_hdr));
 
-		verdict = net_arp_input(pkt, eth_hdr);
+		net_pkt_set_ll_proto_type(pkt, NET_ETH_PTYPE_ARP);
+
+		verdict = net_arp_input(pkt,
+					(struct net_eth_addr *)net_pkt_lladdr_src(pkt)->addr,
+					&dst_lladdr);
+
 		zassert_not_equal(verdict, NET_DROP, "Gratuitous ARP failed");
 
 		/* Then check that the HW address is changed for an existing
diff --git a/tests/net/checksum_offload/prj.conf b/tests/net/checksum_offload/prj.conf
index fb86bf9dfac..5711754814d 100644
--- a/tests/net/checksum_offload/prj.conf
+++ b/tests/net/checksum_offload/prj.conf
@@ -23,6 +23,7 @@ CONFIG_NET_IF_MAX_IPV4_COUNT=2
 CONFIG_NET_IF_UNICAST_IPV6_ADDR_COUNT=6
 CONFIG_NET_IPV6_ND=n
 CONFIG_ZTEST=y
+CONFIG_ZTEST_STACK_SIZE=2048
 CONFIG_NET_CONFIG_SETTINGS=n
 CONFIG_NET_SHELL=n
 
diff --git a/tests/net/checksum_offload/src/main.c b/tests/net/checksum_offload/src/main.c
index cb86c98681e..74e6f735c58 100644
--- a/tests/net/checksum_offload/src/main.c
+++ b/tests/net/checksum_offload/src/main.c
@@ -74,9 +74,9 @@ static struct in_addr in4addr_dst2 = { { { 192, 0, 42, 2 } } };
 
 /* Keep track of all ethernet interfaces. For native_sim board, we need
  * to increase the count as it has one extra network interface defined in
- * eth_native_posix driver.
+ * eth_native_tap driver.
  */
-static struct net_if *eth_interfaces[2 + IS_ENABLED(CONFIG_ETH_NATIVE_POSIX)];
+static struct net_if *eth_interfaces[2 + IS_ENABLED(CONFIG_ETH_NATIVE_TAP)];
 
 static bool test_failed;
 static bool test_started;
@@ -608,19 +608,17 @@ static void test_address_setup(void)
 
 static void add_neighbor(struct net_if *iface, struct in6_addr *addr)
 {
-	struct net_linkaddr_storage llstorage;
 	struct net_linkaddr lladdr;
 	struct net_nbr *nbr;
 
-	llstorage.addr[0] = 0x01;
-	llstorage.addr[1] = 0x02;
-	llstorage.addr[2] = 0x33;
-	llstorage.addr[3] = 0x44;
-	llstorage.addr[4] = 0x05;
-	llstorage.addr[5] = 0x06;
+	lladdr.addr[0] = 0x01;
+	lladdr.addr[1] = 0x02;
+	lladdr.addr[2] = 0x33;
+	lladdr.addr[3] = 0x44;
+	lladdr.addr[4] = 0x05;
+	lladdr.addr[5] = 0x06;
 
 	lladdr.len = 6U;
-	lladdr.addr = llstorage.addr;
 	lladdr.type = NET_LINK_ETHERNET;
 
 	nbr = net_ipv6_nbr_add(iface, addr, &lladdr, false,
diff --git a/tests/net/conn_mgr_conn/src/test_ifaces.c b/tests/net/conn_mgr_conn/src/test_ifaces.c
index 535eee07de8..bd21197160a 100644
--- a/tests/net/conn_mgr_conn/src/test_ifaces.c
+++ b/tests/net/conn_mgr_conn/src/test_ifaces.c
@@ -16,7 +16,7 @@
 static void test_iface_init(struct net_if *iface)
 {
 	/* Fake link layer address is needed to silence assertions inside the net core */
-	static uint8_t fake_lladdr[] = { 0x01 };
+	static uint8_t fake_lladdr[] = { 0x00, 0x00, 0x5E, 0x00, 0x53, 0x01 };
 
 	net_if_set_link_addr(iface, fake_lladdr, sizeof(fake_lladdr), NET_LINK_DUMMY);
 
diff --git a/tests/net/conn_mgr_monitor/src/test_ifaces.c b/tests/net/conn_mgr_monitor/src/test_ifaces.c
index 1b7a5080ec1..05eda78dfcf 100644
--- a/tests/net/conn_mgr_monitor/src/test_ifaces.c
+++ b/tests/net/conn_mgr_monitor/src/test_ifaces.c
@@ -15,7 +15,7 @@
 static void test_iface_init(struct net_if *iface)
 {
 	/* Fake link layer address is needed to silence assertions inside the net core */
-	static uint8_t fake_lladdr[] = { 0x01 };
+	static uint8_t fake_lladdr[] = { 0x00, 0x00, 0x5E, 0x00, 0x53, 0x01 };
 
 	net_if_set_link_addr(iface, fake_lladdr, sizeof(fake_lladdr), NET_LINK_DUMMY);
 
diff --git a/tests/net/dhcpv4/client/src/main.c b/tests/net/dhcpv4/client/src/main.c
index ceddbbe9e69..68ca1ee323f 100644
--- a/tests/net/dhcpv4/client/src/main.c
+++ b/tests/net/dhcpv4/client/src/main.c
@@ -680,6 +680,8 @@ ZTEST(dhcpv4_tests, test_dhcp)
 	while (event_count < 16) {
 #elif defined(CONFIG_NET_DHCPV4_OPTION_CALLBACKS)
 	while (event_count < 10) {
+#elif defined(CONFIG_NET_DHCPV4_OPTION_PRINT_IGNORED)
+	while (event_count < 2) {
 #else
 	while (event_count < 5) {
 #endif
diff --git a/tests/net/dhcpv4/client/testcase.yaml b/tests/net/dhcpv4/client/testcase.yaml
index 68d6c54271b..a7892b3b4ae 100644
--- a/tests/net/dhcpv4/client/testcase.yaml
+++ b/tests/net/dhcpv4/client/testcase.yaml
@@ -3,9 +3,6 @@ common:
   tags:
     - net
     - dhcpv4
-  platform_exclude:
-    - native_posix/native/64
-    - native_posix
 tests:
   net.dhcpv4_client:
     extra_configs:
@@ -20,3 +17,6 @@ tests:
     extra_configs:
       - CONFIG_NET_DHCPV4_OPTION_CALLBACKS=y
       - CONFIG_NET_DHCPV4_OPTION_CALLBACKS_VENDOR_SPECIFIC=y
+  net.dhcpv4_client.ignored_options:
+    extra_configs:
+      - CONFIG_NET_DHCPV4_OPTION_PRINT_IGNORED=y
diff --git a/tests/net/dhcpv4/server/testcase.yaml b/tests/net/dhcpv4/server/testcase.yaml
index eb7b500f157..797bba61a73 100644
--- a/tests/net/dhcpv4/server/testcase.yaml
+++ b/tests/net/dhcpv4/server/testcase.yaml
@@ -1,12 +1,8 @@
 common:
   depends_on: netif
   tags:
-    # eventfd API does not work with native_posix so exclude it here
     - net
     - dhcpv4
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   net.dhcpv4_server:
     extra_configs:
diff --git a/tests/net/hostname/src/main.c b/tests/net/hostname/src/main.c
index 762bc0efbb1..bfc2fd926f8 100644
--- a/tests/net/hostname/src/main.c
+++ b/tests/net/hostname/src/main.c
@@ -85,7 +85,7 @@ static uint8_t *net_iface_get_mac(const struct device *dev)
 		data->mac_addr[5] = sys_rand8_get();
 	}
 
-	data->ll_addr.addr = data->mac_addr;
+	memcpy(data->ll_addr.addr, data->mac_addr, sizeof(data->mac_addr));
 	data->ll_addr.len = 6U;
 
 	return data->mac_addr;
diff --git a/tests/net/ieee802154/6lo_fragment/src/main.c b/tests/net/ieee802154/6lo_fragment/src/main.c
index 650abbed114..83ba534f4cd 100644
--- a/tests/net/ieee802154/6lo_fragment/src/main.c
+++ b/tests/net/ieee802154/6lo_fragment/src/main.c
@@ -290,9 +290,9 @@ static struct net_pkt *create_pkt(struct net_fragment_data *data)
 	}
 
 	/* Setup link layer addresses. */
-	net_pkt_lladdr_dst(pkt)->addr = (uint8_t *)&dummy_short_addr;
-	net_pkt_lladdr_dst(pkt)->len = sizeof(dummy_short_addr);
-	net_pkt_lladdr_dst(pkt)->type = NET_LINK_IEEE802154;
+	(void)net_linkaddr_create(net_pkt_lladdr_dst(pkt),
+				  (const uint8_t *)&dummy_short_addr, sizeof(dummy_short_addr),
+				  NET_LINK_IEEE802154);
 
 	memcpy(net_pkt_lladdr_src(pkt),
 	       net_if_get_link_addr(
diff --git a/tests/net/ieee802154/l2/src/ieee802154_test.c b/tests/net/ieee802154/l2/src/ieee802154_test.c
index f984e529db5..f1c16fbb14f 100644
--- a/tests/net/ieee802154/l2/src/ieee802154_test.c
+++ b/tests/net/ieee802154/l2/src/ieee802154_test.c
@@ -397,7 +397,7 @@ static int set_up_recv_socket(enum net_sock_type socket_type)
 	struct sockaddr_ll socket_sll = {
 		.sll_ifindex = net_if_get_by_iface(net_iface),
 		.sll_family = AF_PACKET,
-		.sll_protocol = ETH_P_IEEE802154,
+		.sll_protocol = htons(ETH_P_IEEE802154),
 	};
 	struct timeval timeo_optval = {
 		.tv_sec = 1,
@@ -682,7 +682,7 @@ static bool test_dgram_packet_sending(void *dst_sll, uint8_t dst_sll_halen, uint
 	struct ieee802154_context *ctx = net_if_l2_data(net_iface);
 	struct sockaddr_ll socket_sll = {.sll_ifindex = net_if_get_by_iface(net_iface),
 					 .sll_family = AF_PACKET,
-					 .sll_protocol = ETH_P_IEEE802154};
+					 .sll_protocol = htons(ETH_P_IEEE802154)};
 	struct sockaddr_ll pkt_dst_sll = {
 		.sll_halen = dst_sll_halen,
 		.sll_protocol = htons(ETH_P_IEEE802154),
@@ -742,8 +742,8 @@ static bool test_dgram_packet_sending(void *dst_sll, uint8_t dst_sll_halen, uint
 		goto release_frag;
 	}
 
-	net_pkt_lladdr_src(current_pkt)->addr = net_if_get_link_addr(net_iface)->addr;
-	net_pkt_lladdr_src(current_pkt)->len = net_if_get_link_addr(net_iface)->len;
+	(void)net_linkaddr_copy(net_pkt_lladdr_src(current_pkt),
+				net_if_get_link_addr(net_iface));
 
 	if (!ieee802154_decipher_data_frame(net_iface, current_pkt, &mpdu)) {
 		NET_ERR("*** Cannot decipher/authenticate packet");
@@ -810,17 +810,23 @@ static bool test_dgram_packet_reception(void *src_ll_addr, uint8_t src_ll_addr_l
 	}
 
 	pkt->lladdr_dst.type = NET_LINK_IEEE802154;
-	pkt->lladdr_dst.addr = is_broadcast ? NULL : our_ext_addr;
-	pkt->lladdr_dst.len = is_broadcast ? 0 : sizeof(ctx->ext_addr);
+	if (is_broadcast) {
+		memset(pkt->lladdr_dst.addr, 0, sizeof(pkt->lladdr_dst.addr));
+		pkt->lladdr_dst.len = 0;
+	} else {
+		memcpy(pkt->lladdr_dst.addr, our_ext_addr, sizeof(our_ext_addr));
+		pkt->lladdr_dst.len = sizeof(ctx->ext_addr);
+	}
 
 	if (src_ll_addr_len == IEEE802154_SHORT_ADDR_LENGTH ||
 	    src_ll_addr_len == IEEE802154_EXT_ADDR_LENGTH) {
-		pkt->lladdr_src.addr = src_ll_addr;
+		memcpy(pkt->lladdr_src.addr, src_ll_addr, src_ll_addr_len);
 	} else {
 		NET_ERR("*** Illegal L2 source address length.");
 		goto release_pkt;
 	}
 	pkt->lladdr_src.len = src_ll_addr_len;
+	pkt->lladdr_src.type = NET_LINK_IEEE802154;
 
 	frame_buf = net_pkt_get_frag(pkt, IEEE802154_MTU, K_FOREVER);
 	if (!frame_buf) {
@@ -854,7 +860,8 @@ static bool test_dgram_packet_reception(void *src_ll_addr, uint8_t src_ll_addr_l
 	if (src_ll_addr_len == IEEE802154_SHORT_ADDR_LENGTH) {
 		ctx->short_addr = our_short_addr;
 	} else {
-		sys_memcpy_swap(ctx->ext_addr, our_ext_addr, sizeof(ctx->ext_addr));
+		sys_memcpy_swap(ctx->ext_addr, pkt->lladdr_dst.addr,
+				sizeof(ctx->ext_addr));
 	}
 
 	if (!frame_result) {
@@ -892,7 +899,8 @@ static bool test_dgram_packet_reception(void *src_ll_addr, uint8_t src_ll_addr_l
 	}
 
 	if (recv_src_sll_len != sizeof(struct sockaddr_ll) ||
-	    recv_src_sll.sll_family != AF_PACKET || recv_src_sll.sll_protocol != ETH_P_IEEE802154 ||
+	    recv_src_sll.sll_family != AF_PACKET ||
+	    recv_src_sll.sll_protocol != htons(ETH_P_IEEE802154) ||
 	    recv_src_sll.sll_ifindex != net_if_get_by_iface(net_iface) ||
 	    recv_src_sll.sll_halen != src_ll_addr_len ||
 	    memcmp(recv_src_sll.sll_addr, src_ll_addr, src_ll_addr_len)) {
@@ -932,7 +940,7 @@ static bool test_raw_packet_sending(void)
 
 	socket_sll.sll_ifindex = net_if_get_by_iface(net_iface);
 	socket_sll.sll_family = AF_PACKET;
-	socket_sll.sll_protocol = ETH_P_IEEE802154;
+	socket_sll.sll_protocol = htons(ETH_P_IEEE802154);
 
 	if (zsock_bind(fd, (const struct sockaddr *)&socket_sll, sizeof(struct sockaddr_ll))) {
 		NET_ERR("*** Failed to bind packet socket : %d", errno);
@@ -1091,7 +1099,7 @@ static bool test_recv_and_send_ack_reply(struct ieee802154_pkt_test *t)
 	struct sockaddr_ll socket_sll = {
 		.sll_ifindex = net_if_get_by_iface(net_iface),
 		.sll_family = AF_PACKET,
-		.sll_protocol = ETH_P_IEEE802154,
+		.sll_protocol = htons(ETH_P_IEEE802154),
 	};
 	uint8_t received_payload[80] = {0};
 	struct timeval timeo_optval = {
@@ -1149,7 +1157,8 @@ static bool test_recv_and_send_ack_reply(struct ieee802154_pkt_test *t)
 	sys_memcpy_swap(mac_be, ctx->ext_addr, IEEE802154_EXT_ADDR_LENGTH);
 	if (recv_src_sll_len != sizeof(struct sockaddr_ll) ||
 	    recv_src_sll.sll_ifindex != net_if_get_by_iface(net_iface) ||
-	    recv_src_sll.sll_family != AF_PACKET || recv_src_sll.sll_protocol != ETH_P_IEEE802154 ||
+	    recv_src_sll.sll_family != AF_PACKET ||
+	    recv_src_sll.sll_protocol != htons(ETH_P_IEEE802154) ||
 	    recv_src_sll.sll_halen != IEEE802154_EXT_ADDR_LENGTH ||
 	    memcmp(recv_src_sll.sll_addr, mac_be, IEEE802154_EXT_ADDR_LENGTH)) {
 		NET_ERR("*** Received socket address does not compare (%d)", -errno);
diff --git a/tests/net/iface/src/main.c b/tests/net/iface/src/main.c
index e4731828864..df830fa32a3 100644
--- a/tests/net/iface/src/main.c
+++ b/tests/net/iface/src/main.c
@@ -92,7 +92,7 @@ static uint8_t *net_iface_get_mac(const struct device *dev)
 		data->mac_addr[5] = sys_rand8_get();
 	}
 
-	data->ll_addr.addr = data->mac_addr;
+	memcpy(data->ll_addr.addr, data->mac_addr, sizeof(data->mac_addr));
 	data->ll_addr.len = 6U;
 
 	return data->mac_addr;
diff --git a/tests/net/ipv4_fragment/src/main.c b/tests/net/ipv4_fragment/src/main.c
index 8e496e8097d..c61ff40addc 100644
--- a/tests/net/ipv4_fragment/src/main.c
+++ b/tests/net/ipv4_fragment/src/main.c
@@ -558,8 +558,9 @@ static void setup_tcp_handler(const struct in_addr *raddr, const struct in_addr
 	net_ipaddr_copy(&net_sin(&remote_addr)->sin_addr, raddr);
 	remote_addr.sa_family = AF_INET;
 
-	ret = net_conn_register(IPPROTO_TCP, AF_INET, &local_addr, &remote_addr, local_port,
-				remote_port, NULL, tcp_data_received, NULL, &handle);
+	ret = net_conn_register(IPPROTO_TCP, SOCK_STREAM, AF_INET, &local_addr,
+				&remote_addr, local_port, remote_port, NULL,
+				tcp_data_received, NULL, &handle);
 
 	zassert_equal(ret, 0, "Cannot register TCP connection");
 }
diff --git a/tests/net/ipv6/src/main.c b/tests/net/ipv6/src/main.c
index 1dd40afcde8..a9b2a92d4d2 100644
--- a/tests/net/ipv6/src/main.c
+++ b/tests/net/ipv6/src/main.c
@@ -449,18 +449,16 @@ NET_DEVICE_INIT(eth_ipv6_net_dummy, "eth_ipv6_net_dummy",
 static void add_neighbor(void)
 {
 	struct net_nbr *nbr;
-	struct net_linkaddr_storage llstorage;
 	struct net_linkaddr lladdr;
 
-	llstorage.addr[0] = 0x01;
-	llstorage.addr[1] = 0x02;
-	llstorage.addr[2] = 0x33;
-	llstorage.addr[3] = 0x44;
-	llstorage.addr[4] = 0x05;
-	llstorage.addr[5] = 0x06;
+	lladdr.addr[0] = 0x01;
+	lladdr.addr[1] = 0x02;
+	lladdr.addr[2] = 0x33;
+	lladdr.addr[3] = 0x44;
+	lladdr.addr[4] = 0x05;
+	lladdr.addr[5] = 0x06;
 
 	lladdr.len = 6U;
-	lladdr.addr = llstorage.addr;
 	lladdr.type = NET_LINK_ETHERNET;
 
 	nbr = net_ipv6_nbr_add(TEST_NET_IF, &peer_addr, &lladdr,
@@ -471,18 +469,16 @@ static void add_neighbor(void)
 
 static void rm_neighbor(void)
 {
-	struct net_linkaddr_storage llstorage;
 	struct net_linkaddr lladdr;
 
-	llstorage.addr[0] = 0x01;
-	llstorage.addr[1] = 0x02;
-	llstorage.addr[2] = 0x33;
-	llstorage.addr[3] = 0x44;
-	llstorage.addr[4] = 0x05;
-	llstorage.addr[5] = 0x06;
+	lladdr.addr[0] = 0x01;
+	lladdr.addr[1] = 0x02;
+	lladdr.addr[2] = 0x33;
+	lladdr.addr[3] = 0x44;
+	lladdr.addr[4] = 0x05;
+	lladdr.addr[5] = 0x06;
 
 	lladdr.len = 6U;
-	lladdr.addr = llstorage.addr;
 	lladdr.type = NET_LINK_ETHERNET;
 
 	net_ipv6_nbr_rm(TEST_NET_IF, &peer_addr);
@@ -496,23 +492,21 @@ static void add_max_neighbors(void)
 	struct in6_addr dst_addr = { { { 0x20, 0x01, 0x0d, 0xb8, 0, 0, 0, 0,
 					 0, 0, 0, 0, 0, 0, 0, 0x3 } } };
 	struct net_nbr *nbr;
-	struct net_linkaddr_storage llstorage;
 	struct net_linkaddr lladdr;
 	uint8_t i;
 
-	llstorage.addr[0] = 0x01;
-	llstorage.addr[1] = 0x02;
-	llstorage.addr[2] = 0x33;
-	llstorage.addr[3] = 0x44;
-	llstorage.addr[4] = 0x05;
-	llstorage.addr[5] = 0x07;
+	lladdr.addr[0] = 0x01;
+	lladdr.addr[1] = 0x02;
+	lladdr.addr[2] = 0x33;
+	lladdr.addr[3] = 0x44;
+	lladdr.addr[4] = 0x05;
+	lladdr.addr[5] = 0x07;
 
 	lladdr.len = 6U;
-	lladdr.addr = llstorage.addr;
 	lladdr.type = NET_LINK_ETHERNET;
 
 	for (i = 0U; i < CONFIG_NET_IPV6_MAX_NEIGHBORS + 1; i++) {
-		llstorage.addr[5] += i;
+		lladdr.addr[5] += i;
 		dst_addr.s6_addr[15] += i;
 		nbr = net_ipv6_nbr_add(TEST_NET_IF, &dst_addr,
 				       &lladdr, false,
@@ -526,23 +520,21 @@ static void rm_max_neighbors(void)
 {
 	struct in6_addr dst_addr = { { { 0x20, 0x01, 0x0d, 0xb8, 0, 0, 0, 0,
 					 0, 0, 0, 0, 0, 0, 0, 0x3 } } };
-	struct net_linkaddr_storage llstorage;
 	struct net_linkaddr lladdr;
 	uint8_t i;
 
-	llstorage.addr[0] = 0x01;
-	llstorage.addr[1] = 0x02;
-	llstorage.addr[2] = 0x33;
-	llstorage.addr[3] = 0x44;
-	llstorage.addr[4] = 0x05;
-	llstorage.addr[5] = 0x07;
+	lladdr.addr[0] = 0x01;
+	lladdr.addr[1] = 0x02;
+	lladdr.addr[2] = 0x33;
+	lladdr.addr[3] = 0x44;
+	lladdr.addr[4] = 0x05;
+	lladdr.addr[5] = 0x07;
 
 	lladdr.len = 6U;
-	lladdr.addr = llstorage.addr;
 	lladdr.type = NET_LINK_ETHERNET;
 
 	for (i = 0U; i < CONFIG_NET_IPV6_MAX_NEIGHBORS + 1; i++) {
-		llstorage.addr[5] += i;
+		lladdr.addr[5] += i;
 		dst_addr.s6_addr[15] += i;
 		net_ipv6_nbr_rm(TEST_NET_IF, &dst_addr);
 	}
@@ -1400,7 +1392,7 @@ ZTEST(net_ipv6, test_address_lifetime)
 ZTEST(net_ipv6, test_change_ll_addr)
 {
 	static uint8_t new_mac[] = { 00, 01, 02, 03, 04, 05 };
-	struct net_linkaddr_storage *ll;
+	struct net_linkaddr *ll;
 	struct net_linkaddr *ll_iface;
 	struct net_if *iface;
 	struct net_nbr *nbr;
@@ -1429,7 +1421,7 @@ ZTEST(net_ipv6, test_change_ll_addr)
 	/* As the net_ipv6_send_na() uses interface link address to
 	 * greate tllao, change the interface ll address here.
 	 */
-	ll_iface->addr = new_mac;
+	memcpy(ll_iface->addr, new_mac, sizeof(new_mac));
 
 	ret = net_ipv6_send_na(iface, &peer_addr, &all_nodes_mcast,
 			       &peer_addr, flags);
@@ -1443,7 +1435,8 @@ ZTEST(net_ipv6, test_change_ll_addr)
 	zassert_true(memcmp(ll->addr, ll_iface->addr, ll->len) != 0,
 		     "Wrong link address 2");
 
-	ll_iface->addr = net_test_data.mac_addr;
+	memcpy(ll_iface->addr, net_test_data.mac_addr,
+	       sizeof(net_test_data.mac_addr));
 }
 
 ZTEST(net_ipv6, test_dad_timeout)
diff --git a/tests/net/ipv6/testcase.yaml b/tests/net/ipv6/testcase.yaml
index efc60810da2..f33c86df67a 100644
--- a/tests/net/ipv6/testcase.yaml
+++ b/tests/net/ipv6/testcase.yaml
@@ -4,9 +4,6 @@ common:
     - ipv6
     - ipv6_pe
   depends_on: netif
-  platform_exclude:
-    - native_posix/native/64
-    - native_posix
 tests:
   net.ipv6:
     extra_configs:
@@ -18,6 +15,7 @@ tests:
       - CONFIG_NET_PKT_BUF_RX_DATA_POOL_SIZE=4096
       - CONFIG_NET_PKT_BUF_TX_DATA_POOL_SIZE=4096
       - CONFIG_NET_IPV6_PE=n
+      - CONFIG_TEST_EXTRA_STACK_SIZE=1024
   net.ipv6.privacy_extension.prefer_public:
     extra_configs:
       - CONFIG_NET_IPV6_PE=y
diff --git a/tests/net/ipv6_fragment/src/main.c b/tests/net/ipv6_fragment/src/main.c
index 572d70d94d0..49d9622cea7 100644
--- a/tests/net/ipv6_fragment/src/main.c
+++ b/tests/net/ipv6_fragment/src/main.c
@@ -45,9 +45,8 @@ static struct in6_addr ll_addr = { { { 0xfe, 0x80, 0x43, 0xb8, 0, 0, 0, 0,
 				       0, 0, 0, 0xf2, 0xaa, 0x29, 0x02,
 				       0x04 } } };
 
-static uint8_t mac2_addr[] = { 0x02, 0x00, 0x00, 0x00, 0x00, 0x02 };
 static struct net_linkaddr ll_addr2 = {
-	.addr = mac2_addr,
+	.addr = { 0x02, 0x00, 0x00, 0x00, 0x00, 0x02 },
 	.len = 6,
 };
 
@@ -941,7 +940,7 @@ static uint8_t *net_iface_get_mac(const struct device *dev)
 		data->mac_addr[5] = sys_rand8_get();
 	}
 
-	data->ll_addr.addr = data->mac_addr;
+	memcpy(data->ll_addr.addr, data->mac_addr, sizeof(data->mac_addr));
 	data->ll_addr.len = 6U;
 
 	return data->mac_addr;
@@ -2091,6 +2090,7 @@ ZTEST(net_ipv6_fragment, test_send_ipv6_fragment_without_hbho)
 					AF_UNSPEC, 0, ALLOC_TIMEOUT);
 	zassert_not_null(pkt, "packet");
 
+	net_pkt_set_ll_proto_type(pkt, NET_ETH_PTYPE_IPV6);
 	net_pkt_set_family(pkt, AF_INET6);
 	net_pkt_set_ip_hdr_len(pkt, sizeof(struct net_ipv6_hdr));
 	net_pkt_set_ipv6_ext_len(pkt, NET_IPV6_FRAGH_LEN); /* without hbho*/
diff --git a/tests/net/lib/coap/src/main.c b/tests/net/lib/coap/src/main.c
index 10c7cef1d2c..9b64153dc7d 100644
--- a/tests/net/lib/coap/src/main.c
+++ b/tests/net/lib/coap/src/main.c
@@ -1855,4 +1855,127 @@ ZTEST(coap, test_age_is_newer)
 		     "Max age should be marked as newer");
 }
 
+struct test_coap_request {
+	uint16_t id;
+	uint8_t token[COAP_TOKEN_MAX_LEN];
+	uint8_t tkl;
+	uint8_t code;
+	enum coap_msgtype type;
+	struct coap_reply *match;
+};
+
+static int reply_cb(const struct coap_packet *response,
+		    struct coap_reply *reply,
+		    const struct sockaddr *from)
+{
+	return 0;
+}
+
+ZTEST(coap, test_response_matching)
+{
+	struct coap_reply matches[] = {
+		{ }, /* Non-initialized (unused) entry. */
+		{ .id = 100, .reply = reply_cb },
+		{ .id = 101, .token = { 1, 2, 3, 4 }, .tkl = 4, .reply = reply_cb },
+	};
+	struct test_coap_request test_responses[] = {
+		/* #0 Piggybacked ACK, empty token */
+		{ .id = 100, .type = COAP_TYPE_ACK, .match = &matches[1],
+		  .code = COAP_RESPONSE_CODE_CONTENT },
+		/* #1 Piggybacked ACK, matching token */
+		{ .id = 101, .type = COAP_TYPE_ACK, .match = &matches[2],
+		  .code = COAP_RESPONSE_CODE_CONTENT, .token = { 1, 2, 3, 4 },
+		  .tkl = 4  },
+		/* #2 Piggybacked ACK, token mismatch */
+		{ .id = 101, .type = COAP_TYPE_ACK, .match = NULL,
+		  .code = COAP_RESPONSE_CODE_CONTENT, .token = { 1, 2, 3, 3 },
+		  .tkl = 4 },
+		/* #3 Piggybacked ACK, token mismatch 2 */
+		{ .id = 100, .type = COAP_TYPE_ACK, .match = NULL,
+		  .code = COAP_RESPONSE_CODE_CONTENT, .token = { 1, 2, 3, 4 },
+		  .tkl = 4 },
+		/* #4 Piggybacked ACK, token mismatch 3 */
+		{ .id = 101, .type = COAP_TYPE_ACK, .match = NULL,
+		  .code = COAP_RESPONSE_CODE_CONTENT, .token = { 1, 2, 3 },
+		  .tkl = 3 },
+		/* #5 Piggybacked ACK, token mismatch 4 */
+		{ .id = 101, .type = COAP_TYPE_ACK, .match = NULL,
+		  .code = COAP_RESPONSE_CODE_CONTENT },
+		/* #6 Piggybacked ACK, id mismatch */
+		{ .id = 102, .type = COAP_TYPE_ACK, .match = NULL,
+		  .code = COAP_RESPONSE_CODE_CONTENT, .token = { 1, 2, 3, 4 },
+		  .tkl = 4 },
+		/* #7 Separate reply, empty token */
+		{ .id = 101, .type = COAP_TYPE_CON, .match = &matches[1],
+		  .code = COAP_RESPONSE_CODE_CONTENT },
+		/* #8 Separate reply, matching token 1 */
+		{ .id = 101, .type = COAP_TYPE_CON, .match = &matches[2],
+		  .code = COAP_RESPONSE_CODE_CONTENT, .token = { 1, 2, 3, 4 },
+		  .tkl = 4 },
+		/* #9 Separate reply, matching token 2 */
+		{ .id = 102, .type = COAP_TYPE_CON, .match = &matches[2],
+		  .code = COAP_RESPONSE_CODE_CONTENT, .token = { 1, 2, 3, 4 },
+		  .tkl = 4 },
+		/* #10 Separate reply, token mismatch */
+		{ .id = 101, .type = COAP_TYPE_CON, .match = NULL,
+		  .code = COAP_RESPONSE_CODE_CONTENT, .token = { 1, 2, 3, 3 },
+		  .tkl = 4 },
+		/* #11 Separate reply, token mismatch 2 */
+		{ .id = 100, .type = COAP_TYPE_CON, .match = NULL,
+		  .code = COAP_RESPONSE_CODE_CONTENT, .token = { 1, 2, 3, 3 },
+		  .tkl = 4 },
+		/* #12 Separate reply, token mismatch 3 */
+		{ .id = 100, .type = COAP_TYPE_CON, .match = NULL,
+		  .code = COAP_RESPONSE_CODE_CONTENT, .token = { 1, 2, 3 },
+		  .tkl = 3 },
+		/* #13 Request, empty token */
+		{ .id = 100, .type = COAP_TYPE_CON, .match = NULL,
+		  .code = COAP_METHOD_GET },
+		/* #14 Request, matching token */
+		{ .id = 101, .type = COAP_TYPE_CON, .match = NULL,
+		  .code = COAP_METHOD_GET, .token = { 1, 2, 3, 4 }, .tkl = 4 },
+		/* #15 Empty ACK */
+		{ .id = 100, .type = COAP_TYPE_ACK, .match = NULL,
+		  .code = COAP_CODE_EMPTY },
+		/* #16 Empty ACK 2 */
+		{ .id = 101, .type = COAP_TYPE_ACK, .match = NULL,
+		  .code = COAP_CODE_EMPTY },
+		/* #17 Empty RESET */
+		{ .id = 100, .type = COAP_TYPE_RESET, .match = &matches[1],
+		  .code = COAP_CODE_EMPTY },
+		/* #18 Empty RESET 2 */
+		{ .id = 101, .type = COAP_TYPE_RESET, .match = &matches[2],
+		  .code = COAP_CODE_EMPTY },
+		/* #19 Empty RESET, id mismatch */
+		{ .id = 102, .type = COAP_TYPE_RESET, .match = NULL,
+		  .code = COAP_CODE_EMPTY },
+	};
+
+	ARRAY_FOR_EACH_PTR(test_responses, response) {
+		struct coap_packet response_pkt = { 0 };
+		struct sockaddr from = { 0 };
+		struct coap_reply *match;
+		uint8_t data[64];
+		int ret;
+
+		ret = coap_packet_init(&response_pkt, data, sizeof(data), COAP_VERSION_1,
+				       response->type, response->tkl, response->token,
+				       response->code, response->id);
+		zassert_ok(ret, "Failed to initialize test packet: %d", ret);
+
+		match = coap_response_received(&response_pkt, &from, matches,
+					       ARRAY_SIZE(matches));
+		if (response->match != NULL) {
+			zassert_not_null(match, "Did not found a response match when expected");
+			zassert_equal_ptr(response->match, match,
+					  "Wrong response match, test %d match %d",
+					  response - test_responses, match - matches);
+		} else {
+			zassert_is_null(match,
+					"Found unexpected response match, test %d match %d",
+					response - test_responses, match - matches);
+		}
+	}
+}
+
 ZTEST_SUITE(coap, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/net/lib/coap_client/src/main.c b/tests/net/lib/coap_client/src/main.c
index 02d7693a7a0..5e3ea4bf897 100644
--- a/tests/net/lib/coap_client/src/main.c
+++ b/tests/net/lib/coap_client/src/main.c
@@ -9,7 +9,7 @@
 #include <zephyr/misc/lorem_ipsum.h>
 #include <zephyr/ztest.h>
 #if defined(CONFIG_NATIVE_SIM_SLOWDOWN_TO_REAL_TIME)
-#include "timer_model.h"
+#include "nsi_timer_model.h"
 #endif
 #include "stubs.h"
 
diff --git a/tests/net/lib/dns_addremove/testcase.yaml b/tests/net/lib/dns_addremove/testcase.yaml
index 21b33cba4ca..5551a41cfba 100644
--- a/tests/net/lib/dns_addremove/testcase.yaml
+++ b/tests/net/lib/dns_addremove/testcase.yaml
@@ -5,9 +5,6 @@ common:
   depends_on: netif
   min_ram: 16
   timeout: 600
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   net.dns.addremove:
     min_ram: 21
diff --git a/tests/net/lib/dns_cache/src/main.c b/tests/net/lib/dns_cache/src/main.c
index cadb907cf9a..a2eceb9cbd9 100644
--- a/tests/net/lib/dns_cache/src/main.c
+++ b/tests/net/lib/dns_cache/src/main.c
@@ -24,10 +24,11 @@ ZTEST(net_dns_cache_test, test_simple_cache_entry)
 	struct dns_addrinfo info_write = {.ai_family = AF_INET};
 	struct dns_addrinfo info_read = {0};
 	const char *query = "example.com";
+	enum dns_query_type query_type = DNS_QUERY_TYPE_A;
 
 	zassert_ok(dns_cache_add(&test_dns_cache, query, &info_write, TEST_DNS_CACHE_DEFAULT_TTL),
 		   "Cache entry adding should work.");
-	zassert_equal(1, dns_cache_find(&test_dns_cache, query, &info_read, 1));
+	zassert_equal(1, dns_cache_find(&test_dns_cache, query, query_type, &info_read, 1));
 	zassert_equal(AF_INET, info_read.ai_family);
 }
 
@@ -35,8 +36,9 @@ ZTEST(net_dns_cache_test, test_not_cached)
 {
 	struct dns_addrinfo info_read = {0};
 	const char *query = "example.com";
+	enum dns_query_type query_type = DNS_QUERY_TYPE_A;
 
-	zassert_equal(0, dns_cache_find(&test_dns_cache, query, &info_read, 1));
+	zassert_equal(0, dns_cache_find(&test_dns_cache, query, query_type, &info_read, 1));
 	zassert_equal(0, info_read.ai_family);
 }
 
@@ -45,14 +47,15 @@ ZTEST(net_dns_cache_test, test_fill_cache)
 	struct dns_addrinfo info_write = {.ai_family = AF_INET};
 	struct dns_addrinfo info_read[TEST_DNS_CACHE_SIZE] = {0};
 	const char *query = "example.com";
+	enum dns_query_type query_type = DNS_QUERY_TYPE_A;
 
 	for (size_t i = 0; i < TEST_DNS_CACHE_SIZE; i++) {
 		zassert_ok(dns_cache_add(&test_dns_cache, query, &info_write,
 					 TEST_DNS_CACHE_DEFAULT_TTL),
 			   "Cache entry adding should work.");
 	}
-	zassert_equal(TEST_DNS_CACHE_SIZE,
-		      dns_cache_find(&test_dns_cache, query, info_read, TEST_DNS_CACHE_SIZE));
+	zassert_equal(TEST_DNS_CACHE_SIZE, dns_cache_find(&test_dns_cache, query, query_type,
+							  info_read, TEST_DNS_CACHE_SIZE));
 	zassert_equal(AF_INET, info_read[TEST_DNS_CACHE_SIZE - 1].ai_family);
 }
 
@@ -61,6 +64,7 @@ ZTEST(net_dns_cache_test, test_flush)
 	struct dns_addrinfo info_write = {.ai_family = AF_INET};
 	struct dns_addrinfo info_read[TEST_DNS_CACHE_SIZE] = {0};
 	const char *query = "example.com";
+	enum dns_query_type query_type = DNS_QUERY_TYPE_A;
 
 	for (size_t i = 0; i < TEST_DNS_CACHE_SIZE; i++) {
 		zassert_ok(dns_cache_add(&test_dns_cache, query, &info_write,
@@ -68,7 +72,8 @@ ZTEST(net_dns_cache_test, test_flush)
 			   "Cache entry adding should work.");
 	}
 	zassert_ok(dns_cache_flush(&test_dns_cache));
-	zassert_equal(0, dns_cache_find(&test_dns_cache, query, info_read, TEST_DNS_CACHE_SIZE));
+	zassert_equal(0, dns_cache_find(&test_dns_cache, query, query_type, info_read,
+					TEST_DNS_CACHE_SIZE));
 	zassert_equal(0, info_read[TEST_DNS_CACHE_SIZE - 1].ai_family);
 }
 
@@ -77,14 +82,15 @@ ZTEST(net_dns_cache_test, test_fill_cache_to_small)
 	struct dns_addrinfo info_write = {.ai_family = AF_INET};
 	struct dns_addrinfo info_read[TEST_DNS_CACHE_SIZE - 1] = {0};
 	const char *query = "example.com";
+	enum dns_query_type query_type = DNS_QUERY_TYPE_A;
 
 	for (size_t i = 0; i < TEST_DNS_CACHE_SIZE; i++) {
 		zassert_ok(dns_cache_add(&test_dns_cache, query, &info_write,
 					 TEST_DNS_CACHE_DEFAULT_TTL),
 			   "Cache entry adding should work.");
 	}
-	zassert_equal(-ENOSR,
-		      dns_cache_find(&test_dns_cache, query, info_read, TEST_DNS_CACHE_SIZE - 1));
+	zassert_equal(-ENOSR, dns_cache_find(&test_dns_cache, query, query_type, info_read,
+					     TEST_DNS_CACHE_SIZE - 1));
 	zassert_equal(AF_INET, info_read[TEST_DNS_CACHE_SIZE - 2].ai_family);
 }
 
@@ -93,6 +99,7 @@ ZTEST(net_dns_cache_test, test_closest_expiry_removed)
 	struct dns_addrinfo info_write = {.ai_family = AF_INET};
 	struct dns_addrinfo info_read = {0};
 	const char *closest_expiry = "example.com";
+	enum dns_query_type query_type = DNS_QUERY_TYPE_A;
 
 	zassert_ok(dns_cache_add(&test_dns_cache, closest_expiry, &info_write,
 				 TEST_DNS_CACHE_DEFAULT_TTL),
@@ -103,7 +110,8 @@ ZTEST(net_dns_cache_test, test_closest_expiry_removed)
 					 TEST_DNS_CACHE_DEFAULT_TTL),
 			   "Cache entry adding should work.");
 	}
-	zassert_equal(0, dns_cache_find(&test_dns_cache, closest_expiry, &info_read, 1));
+	zassert_equal(0,
+		      dns_cache_find(&test_dns_cache, closest_expiry, query_type, &info_read, 1));
 	zassert_equal(0, info_read.ai_family);
 }
 
@@ -112,6 +120,7 @@ ZTEST(net_dns_cache_test, test_expired_entries_removed)
 	struct dns_addrinfo info_write = {.ai_family = AF_INET};
 	struct dns_addrinfo info_read[3] = {0};
 	const char *query = "example.com";
+	enum dns_query_type query_type = DNS_QUERY_TYPE_A;
 
 	zassert_ok(dns_cache_add(&test_dns_cache, query, &info_write, TEST_DNS_CACHE_DEFAULT_TTL),
 		   "Cache entry adding should work.");
@@ -121,15 +130,47 @@ ZTEST(net_dns_cache_test, test_expired_entries_removed)
 	zassert_ok(
 		dns_cache_add(&test_dns_cache, query, &info_write, TEST_DNS_CACHE_DEFAULT_TTL * 3),
 		"Cache entry adding should work.");
-	zassert_equal(3, dns_cache_find(&test_dns_cache, query, info_read, 3));
+	zassert_equal(3, dns_cache_find(&test_dns_cache, query, query_type, info_read, 3));
 	zassert_equal(AF_INET, info_read[0].ai_family);
 	k_sleep(K_MSEC(TEST_DNS_CACHE_DEFAULT_TTL * 1000 + 1));
-	zassert_equal(2, dns_cache_find(&test_dns_cache, query, info_read, 3));
+	zassert_equal(2, dns_cache_find(&test_dns_cache, query, query_type, info_read, 3));
 	zassert_equal(AF_INET, info_read[0].ai_family);
 	k_sleep(K_MSEC(TEST_DNS_CACHE_DEFAULT_TTL * 1000 + 1));
-	zassert_equal(1, dns_cache_find(&test_dns_cache, query, info_read, 3));
+	zassert_equal(1, dns_cache_find(&test_dns_cache, query, query_type, info_read, 3));
 	zassert_equal(AF_INET, info_read[0].ai_family);
 	k_sleep(K_MSEC(1));
-	zassert_equal(1, dns_cache_find(&test_dns_cache, query, info_read, 3));
+	zassert_equal(1, dns_cache_find(&test_dns_cache, query, query_type, info_read, 3));
 	zassert_equal(AF_INET, info_read[0].ai_family);
 }
+
+ZTEST(net_dns_cache_test, test_different_type_not_returned)
+{
+	struct dns_addrinfo info_write = {.ai_family = AF_INET};
+	struct dns_addrinfo info_read = {0};
+	const char *query = "example.com";
+	enum dns_query_type query_type = DNS_QUERY_TYPE_AAAA;
+
+	zassert_ok(dns_cache_add(&test_dns_cache, query, &info_write, TEST_DNS_CACHE_DEFAULT_TTL),
+		   "Cache entry adding should work.");
+	zassert_equal(0, dns_cache_find(&test_dns_cache, query, query_type, &info_read, 1));
+	zassert_equal(0, info_read.ai_family);
+}
+
+ZTEST(net_dns_cache_test, test_only_expected_type_returned)
+{
+	struct dns_addrinfo info_write_a = {.ai_family = AF_INET};
+	struct dns_addrinfo info_write_b = {.ai_family = AF_INET6};
+	struct dns_addrinfo info_read = {0};
+	const char *query = "example.com";
+	enum dns_query_type query_type_a = DNS_QUERY_TYPE_A;
+	enum dns_query_type query_type_b = DNS_QUERY_TYPE_AAAA;
+
+	zassert_ok(dns_cache_add(&test_dns_cache, query, &info_write_a, TEST_DNS_CACHE_DEFAULT_TTL),
+		   "Cache entry adding should work.");
+	zassert_ok(dns_cache_add(&test_dns_cache, query, &info_write_b, TEST_DNS_CACHE_DEFAULT_TTL),
+		   "Cache entry adding should work.");
+	zassert_equal(1, dns_cache_find(&test_dns_cache, query, query_type_a, &info_read, 1));
+	zassert_equal(AF_INET, info_read.ai_family);
+	zassert_equal(1, dns_cache_find(&test_dns_cache, query, query_type_b, &info_read, 1));
+	zassert_equal(AF_INET6, info_read.ai_family);
+}
diff --git a/tests/net/lib/dns_cache/testcase.yaml b/tests/net/lib/dns_cache/testcase.yaml
index b86087552b5..a14a8f6fe7d 100644
--- a/tests/net/lib/dns_cache/testcase.yaml
+++ b/tests/net/lib/dns_cache/testcase.yaml
@@ -6,9 +6,6 @@ common:
   depends_on: netif
   integration_platforms:
     - native_sim
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   net.dns.cache:
     build_only: false
diff --git a/tests/net/lib/dns_dispatcher/testcase.yaml b/tests/net/lib/dns_dispatcher/testcase.yaml
index 45337949f8f..314097ece66 100644
--- a/tests/net/lib/dns_dispatcher/testcase.yaml
+++ b/tests/net/lib/dns_dispatcher/testcase.yaml
@@ -5,9 +5,6 @@ common:
   depends_on: netif
   min_ram: 21
   timeout: 600
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   net.dns.dispatch:
     min_ram: 21
diff --git a/tests/net/lib/dns_packet/src/main.c b/tests/net/lib/dns_packet/src/main.c
index 363bdf3d3b5..0cb7c4aa09e 100644
--- a/tests/net/lib/dns_packet/src/main.c
+++ b/tests/net/lib/dns_packet/src/main.c
@@ -1287,6 +1287,253 @@ ZTEST(dns_packet, test_dns_invalid_answer)
 	zassert_equal(ret, -EINVAL, "DNS message answer check succeed (%d)", ret);
 }
 
+static uint8_t recursive_query_resp_ipv4[] = {
+	/* DNS msg header (12 bytes) */
+	0x74, 0xe1, 0x81, 0x80, 0x00, 0x01, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00,
+
+	/* Query string (westus2-prod-2.notifications.teams.microsoft.com)
+	 * (length 50)
+	 */
+	0x0e, 0x77, 0x65, 0x73,	0x74, 0x75, 0x73, 0x32,
+	0x2d, 0x70, 0x72, 0x6f, 0x64, 0x2d, 0x32, 0x0d,
+	0x6e, 0x6f, 0x74, 0x69, 0x66, 0x69, 0x63, 0x61,
+	0x74, 0x69, 0x6f, 0x6e, 0x73, 0x05, 0x74, 0x65,
+	0x61, 0x6d, 0x73, 0x09, 0x6d, 0x69, 0x63, 0x72,
+	0x6f, 0x73, 0x6f, 0x66, 0x74, 0x03, 0x63, 0x6f,
+	0x6d, 0x00,
+
+	/* Type (2 bytes) */
+	0x00, 0x01,
+
+	/* Class (2 bytes) */
+	0x00, 0x01,
+
+	/* Answer 1 */
+	0xc0, 0x0c,
+
+	/* Answer type (cname) */
+	0x00, 0x05,
+
+	/* Class */
+	0x00, 0x01,
+
+	/* TTL */
+	0x00, 0x00, 0x00, 0x04,
+
+	/* RR data length */
+	0x00, 0x02,
+
+	/* Data */
+	0xc0, 0x4e, /* <--- recursive pointer */
+};
+
+NET_BUF_POOL_DEFINE(dns_qname_pool_for_test, 2, 128, 0, NULL);
+
+ZTEST(dns_packet, test_dns_recursive_query)
+{
+	static const uint8_t query[] = {
+		/* Query string */
+		0x0e, 0x77, 0x65, 0x73,	0x74, 0x75, 0x73, 0x32,
+		0x2d, 0x70, 0x72, 0x6f, 0x64, 0x2d, 0x32, 0x0d,
+		0x6e, 0x6f, 0x74, 0x69, 0x66, 0x69, 0x63, 0x61,
+		0x74, 0x69, 0x6f, 0x6e, 0x73, 0x05, 0x74, 0x65,
+		0x61, 0x6d, 0x73, 0x09, 0x6d, 0x69, 0x63, 0x72,
+		0x6f, 0x73, 0x6f, 0x66, 0x74, 0x03, 0x63, 0x6f,
+		0x6d, 0x00,
+
+		/* Type */
+		0x00, 0x01,
+	};
+	struct dns_msg_t dns_msg = { 0 };
+	uint16_t dns_id = 0;
+	int query_idx = -1;
+	uint16_t query_hash = 0;
+	struct net_buf *dns_cname;
+	int ret;
+
+	dns_cname = net_buf_alloc(&dns_qname_pool_for_test, dns_ctx.buf_timeout);
+	zassert_not_null(dns_cname, "Out of mem");
+
+	dns_msg.msg = recursive_query_resp_ipv4;
+	dns_msg.msg_size = sizeof(recursive_query_resp_ipv4);
+
+	dns_id = dns_unpack_header_id(dns_msg.msg);
+
+	setup_dns_context(&dns_ctx, 0, dns_id, query, sizeof(query),
+			  DNS_QUERY_TYPE_A);
+
+	ret = dns_validate_msg(&dns_ctx, &dns_msg, &dns_id, &query_idx,
+			       dns_cname, &query_hash);
+	zassert_true(ret == DNS_EAI_SYSTEM && errno == ELOOP,
+		     "[%s] DNS message was valid (%d / %d)",
+		     "recursive rsp", ret, errno);
+
+	net_buf_unref(dns_cname);
+}
+
+static uint8_t invalid_compression_response_ipv4[] = {
+	/* DNS msg header (12 bytes) */
+	0x74, 0xe1, 0x81, 0x80, 0x00, 0x01, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00,
+
+	/* Query string */
+	0x0e, 0x77, 0x65, 0x73,	0x74, 0x75, 0x73, 0x32,
+	0x2d, 0x70, 0x72, 0x6f, 0x64, 0x2d, 0x32, 0x0d,
+	0x6e, 0x6f, 0x74, 0x69, 0x66, 0x69, 0x63, 0x61,
+	0x74, 0x69, 0x6f, 0x6e, 0x73, 0x05, 0x74, 0x65,
+	0x61, 0x6d, 0x73, 0x09, 0x6d, 0x69, 0x63, 0x72,
+	0x6f, 0x73, 0x6f, 0x66, 0x74, 0x03, 0x63, 0x6f,
+	0x6d, 0x00,
+
+	/* Type */
+	0x00, 0x01,
+
+	/* Class */
+	0x00, 0x01,
+
+	/* Answer 1 */
+	0xb0, 0x0c, /* <--- invalid compression pointer */
+
+	/* Answer type (cname) */
+	0x00, 0x05,
+
+	/* Class */
+	0x00, 0x01,
+
+	/* TTL */
+	0x00, 0x00, 0x00, 0x04,
+
+	/* RR data length */
+	0x00, 0x02,
+
+	/* Data */
+	0xc0, 0x0c,
+};
+
+ZTEST(dns_packet, test_dns_invalid_compress_bits)
+{
+	static const uint8_t query[] = {
+		/* Query string */
+		0x0e, 0x77, 0x65, 0x73,	0x74, 0x75, 0x73, 0x32,
+		0x2d, 0x70, 0x72, 0x6f, 0x64, 0x2d, 0x32, 0x0d,
+		0x6e, 0x6f, 0x74, 0x69, 0x66, 0x69, 0x63, 0x61,
+		0x74, 0x69, 0x6f, 0x6e, 0x73, 0x05, 0x74, 0x65,
+		0x61, 0x6d, 0x73, 0x09, 0x6d, 0x69, 0x63, 0x72,
+		0x6f, 0x73, 0x6f, 0x66, 0x74, 0x03, 0x63, 0x6f,
+		0x6d, 0x00,
+
+		/* Type */
+		0x00, 0x01,
+	};
+	struct dns_msg_t dns_msg = { 0 };
+	uint16_t dns_id = 0;
+	int query_idx = -1;
+	uint16_t query_hash = 0;
+	struct net_buf *dns_cname;
+	int ret;
+
+	dns_cname = net_buf_alloc(&dns_qname_pool_for_test, dns_ctx.buf_timeout);
+	zassert_not_null(dns_cname, "Out of mem");
+
+	dns_msg.msg = invalid_compression_response_ipv4;
+	dns_msg.msg_size = sizeof(invalid_compression_response_ipv4);
+
+	dns_id = dns_unpack_header_id(dns_msg.msg);
+
+	setup_dns_context(&dns_ctx, 0, dns_id, query, sizeof(query),
+			  DNS_QUERY_TYPE_A);
+
+	ret = dns_validate_msg(&dns_ctx, &dns_msg, &dns_id, &query_idx,
+			       dns_cname, &query_hash);
+	zassert_true(ret == DNS_EAI_SYSTEM && errno == EINVAL,
+		     "[%s] DNS message was valid (%d / %d)",
+		     "invalid compression rsp", ret, errno);
+
+	net_buf_unref(dns_cname);
+}
+
+static uint8_t invalid_compression_response_cname_ipv4[] = {
+	/* DNS msg header (12 bytes) */
+	0x74, 0xe1, 0x81, 0x80, 0x00, 0x01, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00,
+
+	/* Query string */
+	0x0e, 0x77, 0x65, 0x73,	0x74, 0x75, 0x73, 0x32,
+	0x2d, 0x70, 0x72, 0x6f, 0x64, 0x2d, 0x32, 0x0d,
+	0x6e, 0x6f, 0x74, 0x69, 0x66, 0x69, 0x63, 0x61,
+	0x74, 0x69, 0x6f, 0x6e, 0x73, 0x05, 0x74, 0x65,
+	0x61, 0x6d, 0x73, 0x09, 0x6d, 0x69, 0x63, 0x72,
+	0x6f, 0x73, 0x6f, 0x66, 0x74, 0x03, 0x63, 0x6f,
+	0x6d, 0x00,
+
+	/* Type */
+	0x00, 0x01,
+
+	/* Class */
+	0x00, 0x01,
+
+	/* Answer 1 */
+	0xc0, 0x0c,
+
+	/* Answer type (cname) */
+	0x00, 0x05,
+
+	/* Class */
+	0x00, 0x01,
+
+	/* TTL */
+	0x00, 0x00, 0x00, 0x04,
+
+	/* RR data length */
+	0x00, 0x02,
+
+	/* Data */
+	0xb0, 0x0c, /* <--- invalid compression pointer */
+};
+
+ZTEST(dns_packet, test_dns_invalid_compress_bits_cname)
+{
+	static const uint8_t query[] = {
+		/* Query string */
+		0x0e, 0x77, 0x65, 0x73,	0x74, 0x75, 0x73, 0x32,
+		0x2d, 0x70, 0x72, 0x6f, 0x64, 0x2d, 0x32, 0x0d,
+		0x6e, 0x6f, 0x74, 0x69, 0x66, 0x69, 0x63, 0x61,
+		0x74, 0x69, 0x6f, 0x6e, 0x73, 0x05, 0x74, 0x65,
+		0x61, 0x6d, 0x73, 0x09, 0x6d, 0x69, 0x63, 0x72,
+		0x6f, 0x73, 0x6f, 0x66, 0x74, 0x03, 0x63, 0x6f,
+		0x6d, 0x00,
+
+		/* Type */
+		0x00, 0x01,
+	};
+	struct dns_msg_t dns_msg = { 0 };
+	uint16_t dns_id = 0;
+	int query_idx = -1;
+	uint16_t query_hash = 0;
+	struct net_buf *dns_cname;
+	int ret;
+
+	dns_cname = net_buf_alloc(&dns_qname_pool_for_test, dns_ctx.buf_timeout);
+	zassert_not_null(dns_cname, "Out of mem");
+
+	dns_msg.msg = invalid_compression_response_cname_ipv4;
+	dns_msg.msg_size = sizeof(invalid_compression_response_cname_ipv4);
+
+	dns_id = dns_unpack_header_id(dns_msg.msg);
+
+	setup_dns_context(&dns_ctx, 0, dns_id, query, sizeof(query),
+			  DNS_QUERY_TYPE_A);
+
+	ret = dns_validate_msg(&dns_ctx, &dns_msg, &dns_id, &query_idx,
+			       dns_cname, &query_hash);
+	zassert_true(ret == DNS_EAI_SYSTEM && errno == EINVAL,
+		     "[%s] DNS message was valid (%d / %d)",
+		     "invalid compression rsp", ret, errno);
+
+	net_buf_unref(dns_cname);
+}
+
 ZTEST_SUITE(dns_packet, NULL, NULL, NULL, NULL, NULL);
 /* TODO:
  *	1) add malformed DNS data (mostly done)
diff --git a/tests/net/lib/dns_packet/testcase.yaml b/tests/net/lib/dns_packet/testcase.yaml
index d1129ca8b42..a69ee4ccb73 100644
--- a/tests/net/lib/dns_packet/testcase.yaml
+++ b/tests/net/lib/dns_packet/testcase.yaml
@@ -1,8 +1,5 @@
 tests:
   net.dns:
-    platform_exclude:
-      - native_posix
-      - native_posix/native/64
     min_ram: 16
     tags:
       - dns
diff --git a/tests/net/lib/dns_resolve/src/main.c b/tests/net/lib/dns_resolve/src/main.c
index c5d17941087..0be84cb00c6 100644
--- a/tests/net/lib/dns_resolve/src/main.c
+++ b/tests/net/lib/dns_resolve/src/main.c
@@ -98,7 +98,7 @@ static uint8_t *net_iface_get_mac(const struct device *dev)
 		data->mac_addr[5] = sys_rand8_get();
 	}
 
-	data->ll_addr.addr = data->mac_addr;
+	memcpy(data->ll_addr.addr, data->mac_addr, sizeof(data->mac_addr));
 	data->ll_addr.len = 6U;
 
 	return data->mac_addr;
@@ -762,4 +762,55 @@ ZTEST(dns_resolve, test_dns_query_ipv6_numeric)
 	}
 }
 
+#define MDNS_IPV4_ADDR "224.0.0.251:5353"
+#define MDNS_IPV6_ADDR "[ff02::fb]:5353"
+
+ZTEST(dns_resolve, test_mdns_ipv4_igmp_group)
+{
+	struct net_if_mcast_addr *maddr;
+	struct sockaddr_in addr4;
+	bool st;
+
+	/* Skip this test if mDNS responder is enabled because it will join
+	 * multicast group automatically.
+	 */
+	Z_TEST_SKIP_IFDEF(CONFIG_MDNS_RESPONDER);
+	Z_TEST_SKIP_IFNDEF(CONFIG_NET_IPV4);
+	Z_TEST_SKIP_IFNDEF(CONFIG_NET_IPV4_IGMP);
+
+	st = net_ipaddr_parse(MDNS_IPV4_ADDR, sizeof(MDNS_IPV4_ADDR) - 1,
+			      (struct sockaddr *)&addr4);
+	zassert_true(st, "Cannot parse IPv4 address");
+
+	maddr = net_if_ipv4_maddr_lookup(&addr4.sin_addr, NULL);
+	zassert_not_null(maddr, "IPv4 mDNS address not found");
+
+	st = net_if_ipv4_maddr_is_joined(maddr);
+	zassert_true(st, "IPv4 mDNS group not joined");
+}
+
+ZTEST(dns_resolve, test_mdns_ipv6_mld_group)
+{
+	struct net_if_mcast_addr *maddr;
+	struct sockaddr_in6 addr6;
+	bool st;
+
+	/* Skip this test if mDNS responder is enabled because it will join
+	 * multicast group automatically.
+	 */
+	Z_TEST_SKIP_IFDEF(CONFIG_MDNS_RESPONDER);
+	Z_TEST_SKIP_IFNDEF(CONFIG_NET_IPV6);
+	Z_TEST_SKIP_IFNDEF(CONFIG_NET_IPV6_MLD);
+
+	st = net_ipaddr_parse(MDNS_IPV6_ADDR, sizeof(MDNS_IPV6_ADDR) - 1,
+			      (struct sockaddr *)&addr6);
+	zassert_true(st, "Cannot parse IPv6 address");
+
+	maddr = net_if_ipv6_maddr_lookup(&addr6.sin6_addr, NULL);
+	zassert_not_null(maddr, "IPv6 mDNS address not found");
+
+	st = net_if_ipv6_maddr_is_joined(maddr);
+	zassert_true(st, "IPv6 mDNS group not joined");
+}
+
 ZTEST_SUITE(dns_resolve, NULL, test_init, NULL, NULL, NULL);
diff --git a/tests/net/lib/dns_resolve/testcase.yaml b/tests/net/lib/dns_resolve/testcase.yaml
index b0734b4d175..9e34738e71e 100644
--- a/tests/net/lib/dns_resolve/testcase.yaml
+++ b/tests/net/lib/dns_resolve/testcase.yaml
@@ -5,9 +5,6 @@ common:
   depends_on: netif
   timeout: 600
   min_ram: 21
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   net.dns.resolve:
     extra_configs:
@@ -18,3 +15,9 @@ tests:
   net.dns.resolve.no_ipv6:
     extra_args: CONF_FILE=prj-no-ipv6.conf
     min_ram: 16
+  net.mdns.resolve:
+    extra_configs:
+      - CONFIG_MDNS_RESOLVER=y
+      - CONFIG_MDNS_RESPONDER=n
+      - CONFIG_NET_IPV6_MLD=y
+      - CONFIG_NET_IPV4_IGMP=y
diff --git a/tests/net/lib/dns_sd/src/main.c b/tests/net/lib/dns_sd/src/main.c
index e70482c027c..c408fe91f45 100644
--- a/tests/net/lib/dns_sd/src/main.c
+++ b/tests/net/lib/dns_sd/src/main.c
@@ -53,6 +53,7 @@ extern int add_srv_record(const struct dns_sd_rec *inst, uint32_t ttl,
 extern size_t service_proto_size(const struct dns_sd_rec *ref);
 extern bool rec_is_valid(const struct dns_sd_rec *ref);
 extern int setup_dst_addr(int sock, sa_family_t family,
+			  struct sockaddr *src, socklen_t src_len,
 			  struct sockaddr *dst, socklen_t *dst_len);
 
 
@@ -685,7 +686,7 @@ ZTEST(dns_sd, test_setup_dst_addr)
 	v4 = zsock_socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP);
 	zassert_true(v4 >= 0, "Create IPv4 UDP context failed (%d)", -errno);
 
-	zassert_equal(0, setup_dst_addr(v4, AF_INET, &dst, &dst_len), "");
+	zassert_equal(0, setup_dst_addr(v4, AF_INET, NULL, 0, &dst, &dst_len), "");
 
 	optlen = sizeof(int);
 	(void)zsock_getsockopt(v4, IPPROTO_IP, IP_MULTICAST_TTL, &ttl, &optlen);
@@ -708,7 +709,7 @@ ZTEST(dns_sd, test_setup_dst_addr)
 	v6 = zsock_socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP);
 	zassert_true(v6 >= 0, "Create IPv6 UDP context failed (%d)", -errno);
 
-	zassert_equal(0, setup_dst_addr(v6, AF_INET6, &dst, &dst_len), "");
+	zassert_equal(0, setup_dst_addr(v6, AF_INET6, NULL, 0, &dst, &dst_len), "");
 
 	optlen = sizeof(int);
 	(void)zsock_getsockopt(v6, IPPROTO_IPV6, IPV6_MULTICAST_HOPS, &ttl, &optlen);
@@ -729,7 +730,7 @@ ZTEST(dns_sd, test_setup_dst_addr)
 	zassert_true(xx >= 0, "Create IPV4 udp socket failed");
 
 	zassert_equal(-EPFNOSUPPORT,
-		      setup_dst_addr(xx, AF_PACKET, &dst, &dst_len), "");
+		      setup_dst_addr(xx, AF_PACKET, NULL, 0, &dst, &dst_len), "");
 }
 
 /** test for @ref dns_sd_is_service_type_enumeration */
diff --git a/tests/net/lib/dns_sd/testcase.yaml b/tests/net/lib/dns_sd/testcase.yaml
index bfdc751ed7c..22a6d332558 100644
--- a/tests/net/lib/dns_sd/testcase.yaml
+++ b/tests/net/lib/dns_sd/testcase.yaml
@@ -3,9 +3,6 @@ common:
     - dns
     - net
   depends_on: netif
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   net.dns.sd:
     min_ram: 21
diff --git a/tests/net/lib/http_header_fields/src/main.c b/tests/net/lib/http_header_fields/src/main.c
index 19b6320647c..4c6096f111b 100644
--- a/tests/net/lib/http_header_fields/src/main.c
+++ b/tests/net/lib/http_header_fields/src/main.c
@@ -821,6 +821,90 @@ int test_header_cr_no_lf_error(int req)
 	return TC_FAIL;
 }
 
+int test_content_range_supplied(int req)
+{
+	struct http_parser parser = { 0 };
+	const char *buf;
+	size_t parsed;
+	size_t buflen;
+
+	http_parser_init(&parser, req ? HTTP_REQUEST : HTTP_RESPONSE);
+	buf = req ? "GET / HTTP/1.1\r\n" : "HTTP/1.1 200 OK\r\n";
+	parsed = http_parser_execute(&parser, &settings_null, buf, strlen(buf));
+
+	/**TESTPOINTS: Check http_parser_execute*/
+	zassert_equal(parsed, strlen(buf),
+			"http_parser_execute error");
+
+	buf = "Content-Range: bytes 100-150/200\r\n\r\n";
+	buflen = strlen(buf);
+	parsed = http_parser_execute(&parser, &settings_null, buf, buflen);
+
+	zassert_equal(parsed, strlen(buf), "http_parser_execute error");
+	zassert_equal(parser.content_range.start, 100, "http_parser_execute error");
+	zassert_equal(parser.content_range.end, 150, "http_parser_execute error");
+	zassert_equal(parser.content_range.total, 200, "http_parser_execute error");
+
+	return TC_PASS;
+}
+
+int test_content_range_asterisk_total(int req)
+{
+	struct http_parser parser = { 0 };
+	const char *buf;
+	size_t parsed;
+	size_t buflen;
+
+	http_parser_init(&parser, req ? HTTP_REQUEST : HTTP_RESPONSE);
+	buf = req ? "GET / HTTP/1.1\r\n" : "HTTP/1.1 200 OK\r\n";
+	parsed = http_parser_execute(&parser, &settings_null, buf, strlen(buf));
+
+	/**TESTPOINTS: Check http_parser_execute*/
+	zassert_equal(parsed, strlen(buf),
+			"http_parser_execute error");
+
+	buf = "Content-Range: bytes 32-64/*\r\n\r\n";
+	buflen = strlen(buf);
+	parsed = http_parser_execute(&parser, &settings_null, buf, buflen);
+
+	zassert_equal(parsed, strlen(buf), "http_parser_execute error");
+	zassert_equal(parser.content_range.start, 32, "http_parser_execute error");
+	zassert_equal(parser.content_range.end, 64, "http_parser_execute error");
+	zassert_equal(parser.content_range.total, 0, "http_parser_execute error");
+
+	return TC_PASS;
+}
+
+int test_double_content_range_error(int req)
+{
+	struct http_parser parser = { 0 };
+	const char *buf;
+	size_t parsed;
+	size_t buflen;
+
+	http_parser_init(&parser, req ? HTTP_REQUEST : HTTP_RESPONSE);
+	buf = req ? "GET / HTTP/1.1\r\n" : "HTTP/1.1 200 OK\r\n";
+	parsed = http_parser_execute(&parser, &settings_null, buf, strlen(buf));
+
+	/**TESTPOINTS: Check http_parser_execute*/
+	zassert_equal(parsed, strlen(buf),
+			"http_parser_execute error");
+
+	buf = "Content-Range: 0-100/200\r\nContent-Range: 100-150/200\r\n\r\n";
+	buflen = strlen(buf);
+	parsed = http_parser_execute(&parser, &settings_null, buf, buflen);
+	if (parsed != buflen) {
+		int error = HTTP_PARSER_ERRNO(&parser);
+
+		zassert_equal(error, HPE_UNEXPECTED_CONTENT_RANGE,
+			"http_parser_execute error");
+
+		return TC_PASS;
+	}
+
+	return TC_FAIL;
+}
+
 ZTEST(http_header_fields_fn, test_http_header_fields)
 {
 	int rc;
@@ -851,6 +935,21 @@ ZTEST(http_header_fields_fn, test_http_header_fields)
 	/**TESTPOINT: Check test_invalid_header_field_content_error*/
 	zassert_false(rc, "test_invalid_header_field_content_error failed");
 
+	rc = test_content_range_supplied(HTTP_REQUEST);
+
+	/**TESTPOINT: Check test_content_range_supplied*/
+	zassert_false(rc, "test_content_range_supplied failed");
+
+	rc = test_content_range_asterisk_total(HTTP_REQUEST);
+
+	/**TESTPOINT: Check test_content_range_asterisk_total*/
+	zassert_false(rc, "test_content_range_asterisk_total failed");
+
+	rc = test_double_content_range_error(HTTP_REQUEST);
+
+	/**TESTPOINT: Check test_double_content_range_error*/
+	zassert_false(rc, "test_double_content_range_error failed");
+
 	rc = test_double_content_length_error(HTTP_RESPONSE);
 
 	/**TESTPOINT: Check test_double_content_length_error*/
@@ -875,6 +974,21 @@ ZTEST(http_header_fields_fn, test_http_header_fields)
 
 	/**TESTPOINT: Check test_invalid_header_field_content_error*/
 	zassert_false(rc, "test_invalid_header_field_content_error failed");
+
+	rc = test_content_range_supplied(HTTP_RESPONSE);
+
+	/**TESTPOINT: Check test_content_range_supplied*/
+	zassert_false(rc, "test_content_range_supplied failed");
+
+	rc = test_content_range_asterisk_total(HTTP_RESPONSE);
+
+	/**TESTPOINT: Check test_content_range_asterisk_total*/
+	zassert_false(rc, "test_content_range_asterisk_total failed");
+
+	rc = test_double_content_range_error(HTTP_RESPONSE);
+
+	/**TESTPOINT: Check test_double_content_range_error*/
+	zassert_false(rc, "test_double_content_range_error failed");
 }
 
 ZTEST_SUITE(http_header_fields_fn, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/net/lib/http_server/common/prj.conf b/tests/net/lib/http_server/common/prj.conf
index 67f0801284e..2e812387e38 100644
--- a/tests/net/lib/http_server/common/prj.conf
+++ b/tests/net/lib/http_server/common/prj.conf
@@ -14,3 +14,4 @@ CONFIG_POSIX_API=y
 CONFIG_NET_SOCKETS=y
 
 CONFIG_HTTP_SERVER_RESOURCE_WILDCARD=y
+CONFIG_HTTP_SERVER_MAX_CLIENTS=7
diff --git a/tests/net/lib/http_server/common/sections-rom.ld b/tests/net/lib/http_server/common/sections-rom.ld
index bf8711a40d7..dfc221a095a 100644
--- a/tests/net/lib/http_server/common/sections-rom.ld
+++ b/tests/net/lib/http_server/common/sections-rom.ld
@@ -3,3 +3,4 @@
 ITERABLE_SECTION_ROM(http_resource_desc_service_A, Z_LINK_ITERABLE_SUBALIGN)
 ITERABLE_SECTION_ROM(http_resource_desc_service_B, Z_LINK_ITERABLE_SUBALIGN)
 ITERABLE_SECTION_ROM(http_resource_desc_service_D, Z_LINK_ITERABLE_SUBALIGN)
+ITERABLE_SECTION_ROM(http_resource_desc_service_E, Z_LINK_ITERABLE_SUBALIGN)
diff --git a/tests/net/lib/http_server/common/src/main.c b/tests/net/lib/http_server/common/src/main.c
index 5c4ab204873..4b532af44af 100644
--- a/tests/net/lib/http_server/common/src/main.c
+++ b/tests/net/lib/http_server/common/src/main.c
@@ -50,14 +50,14 @@ static struct http_resource_detail detail[] = {
  * the paths (and implementation-specific details) are known at compile time.
  */
 static const uint16_t service_A_port = 4242;
-HTTP_SERVICE_DEFINE(service_A, "a.service.com", &service_A_port, 4, 2, DETAIL(0));
+HTTP_SERVICE_DEFINE(service_A, "a.service.com", &service_A_port, 4, 2, DETAIL(0), NULL);
 HTTP_RESOURCE_DEFINE(resource_0, service_A, "/", RES(0));
 HTTP_RESOURCE_DEFINE(resource_1, service_A, "/index.html", RES(1));
 HTTP_RESOURCE_DEFINE(resource_2, service_A, "/fs/*", RES(5));
 
 /* ephemeral port of 0 */
 static uint16_t service_B_port;
-HTTP_SERVICE_DEFINE(service_B, "b.service.com", &service_B_port, 7, 3, DETAIL(1));
+HTTP_SERVICE_DEFINE(service_B, "b.service.com", &service_B_port, 7, 3, DETAIL(1), NULL);
 HTTP_RESOURCE_DEFINE(resource_3, service_B, "/foo.htm", RES(2));
 HTTP_RESOURCE_DEFINE(resource_4, service_B, "/bar/baz.php", RES(3));
 
@@ -67,16 +67,23 @@ HTTP_RESOURCE_DEFINE(resource_4, service_B, "/bar/baz.php", RES(3));
  * runtime.
  */
 static const uint16_t service_C_port = 5959;
-HTTP_SERVICE_DEFINE_EMPTY(service_C, "192.168.1.1", &service_C_port, 5, 9, DETAIL(2));
+HTTP_SERVICE_DEFINE_EMPTY(service_C, "192.168.1.1", &service_C_port, 5, 9, DETAIL(2), NULL);
 
 /* Wildcard resources */
 static uint16_t service_D_port = service_A_port + 1;
-HTTP_SERVICE_DEFINE(service_D, "2001:db8::1", &service_D_port, 7, 3, DETAIL(3));
+HTTP_SERVICE_DEFINE(service_D, "2001:db8::1", &service_D_port, 7, 3, DETAIL(3), NULL);
 HTTP_RESOURCE_DEFINE(resource_5, service_D, "/foo1.htm*", RES(0));
 HTTP_RESOURCE_DEFINE(resource_6, service_D, "/fo*", RES(1));
 HTTP_RESOURCE_DEFINE(resource_7, service_D, "/f[ob]o3.html", RES(1));
 HTTP_RESOURCE_DEFINE(resource_8, service_D, "/fb?3.htm", RES(0));
 HTTP_RESOURCE_DEFINE(resource_9, service_D, "/f*4.html", RES(3));
+HTTP_RESOURCE_DEFINE(resource_11, service_D, "/foo/*", RES(3));
+HTTP_RESOURCE_DEFINE(resource_12, service_D, "/foo/b?r", RES(3));
+
+/* Default resource in case of no match */
+static uint16_t service_E_port = 8080;
+HTTP_SERVICE_DEFINE(service_E, "192.0.2.1", &service_E_port, 1, 1, NULL, DETAIL(0));
+HTTP_RESOURCE_DEFINE(resource_10, service_E, "/index.html", RES(4));
 
 ZTEST(http_service, test_HTTP_SERVICE_DEFINE)
 {
@@ -110,7 +117,7 @@ ZTEST(http_service, test_HTTP_SERVICE_COUNT)
 
 	n_svc = 4273;
 	HTTP_SERVICE_COUNT(&n_svc);
-	zassert_equal(n_svc, 4);
+	zassert_equal(n_svc, 5);
 }
 
 ZTEST(http_service, test_HTTP_SERVICE_RESOURCE_COUNT)
@@ -127,6 +134,7 @@ ZTEST(http_service, test_HTTP_SERVICE_FOREACH)
 	size_t have_service_B = 0;
 	size_t have_service_C = 0;
 	size_t have_service_D = 0;
+	size_t have_service_E = 0;
 
 	HTTP_SERVICE_FOREACH(svc) {
 		if (svc == &service_A) {
@@ -137,17 +145,21 @@ ZTEST(http_service, test_HTTP_SERVICE_FOREACH)
 			have_service_C = 1;
 		} else if (svc == &service_D) {
 			have_service_D = 1;
+		} else if (svc == &service_E) {
+			have_service_E = 1;
 		} else {
-			zassert_unreachable("svc (%p) not equal to &service_A (%p), &service_B "
-					    "(%p), or &service_C (%p)",
-					    svc, &service_A, &service_B, &service_C);
+			zassert_unreachable("svc (%p) not equal to any defined service", svc);
 		}
 
 		n_svc++;
 	}
 
-	zassert_equal(n_svc, 4);
-	zassert_equal(have_service_A + have_service_B + have_service_C + have_service_D, n_svc);
+	zassert_equal(n_svc, 5);
+	zassert_equal(have_service_A, 1);
+	zassert_equal(have_service_B, 1);
+	zassert_equal(have_service_C, 1);
+	zassert_equal(have_service_D, 1);
+	zassert_equal(have_service_E, 1);
 }
 
 ZTEST(http_service, test_HTTP_RESOURCE_FOREACH)
@@ -296,55 +308,117 @@ ZTEST(http_service, test_HTTP_RESOURCE_DEFINE)
 	}
 }
 
-extern struct http_resource_detail *get_resource_detail(const char *path,
+extern struct http_resource_detail *get_resource_detail(const struct http_service_desc *service,
+							const char *path,
 							int *path_len,
 							bool is_websocket);
 
-#define CHECK_PATH(path, len) ({ *len = 0; get_resource_detail(path, len, false); })
+#define CHECK_PATH(svc, path, len) ({ *len = 0; get_resource_detail(&svc, path, len, false); })
 
 ZTEST(http_service, test_HTTP_RESOURCE_WILDCARD)
 {
 	struct http_resource_detail *res;
 	int len;
 
-	res = CHECK_PATH("/", &len);
+	res = CHECK_PATH(service_A, "/", &len);
 	zassert_not_null(res, "Cannot find resource");
 	zassert_true(len > 0, "Length not set");
 	zassert_equal(res, RES(0), "Resource mismatch");
 
-	res = CHECK_PATH("/f", &len);
+	res = CHECK_PATH(service_D, "/f", &len);
 	zassert_is_null(res, "Resource found");
 	zassert_equal(len, 0, "Length set");
 
-	res = CHECK_PATH("/foo1.html", &len);
+	res = CHECK_PATH(service_D, "/foo1.html", &len);
 	zassert_not_null(res, "Cannot find resource");
 	zassert_true(len > 0, "Length not set");
 	zassert_equal(res, RES(0), "Resource mismatch");
 
-	res = CHECK_PATH("/foo2222.html", &len);
+	res = CHECK_PATH(service_D, "/foo2222.html", &len);
 	zassert_not_null(res, "Cannot find resource");
 	zassert_true(len > 0, "Length not set");
 	zassert_equal(res, RES(1), "Resource mismatch");
 
-	res = CHECK_PATH("/fbo3.html", &len);
+	res = CHECK_PATH(service_D, "/fbo3.html", &len);
 	zassert_not_null(res, "Cannot find resource");
 	zassert_true(len > 0, "Length not set");
 	zassert_equal(res, RES(1), "Resource mismatch");
 
-	res = CHECK_PATH("/fbo3.htm", &len);
+	res = CHECK_PATH(service_D, "/fbo3.htm", &len);
 	zassert_not_null(res, "Cannot find resource");
 	zassert_true(len > 0, "Length not set");
 	zassert_equal(res, RES(0), "Resource mismatch");
 
-	res = CHECK_PATH("/fbo4.html", &len);
+	res = CHECK_PATH(service_D, "/fbo4.html", &len);
 	zassert_not_null(res, "Cannot find resource");
 	zassert_true(len > 0, "Length not set");
 	zassert_equal(res, RES(3), "Resource mismatch");
 
-	res = CHECK_PATH("/fs/index.html", &len);
+	res = CHECK_PATH(service_D, "/fb", &len);
+	zassert_is_null(res, "Resource found");
+	zassert_equal(len, 0, "Length set");
+
+	res = CHECK_PATH(service_A, "/fs/index.html", &len);
 	zassert_not_null(res, "Cannot find resource");
 	zassert_true(len > 0, "Length not set");
 	zassert_equal(res, RES(5), "Resource mismatch");
+
+	/* Resources that only exist on one service should not be found on another */
+	res = CHECK_PATH(service_A, "/foo1.htm", &len);
+	zassert_is_null(res, "Resource found");
+	zassert_equal(len, 0, "Length set");
+
+	res = CHECK_PATH(service_A, "/foo2222.html", &len);
+	zassert_is_null(res, "Resource found");
+	zassert_equal(len, 0, "Length set");
+
+	res = CHECK_PATH(service_A, "/fbo3.htm", &len);
+	zassert_is_null(res, "Resource found");
+	zassert_equal(len, 0, "Length set");
+
+	res = CHECK_PATH(service_D, "/foo/bar", &len);
+	zassert_not_null(res, "Resource not found");
+	zassert_true(len == (sizeof("/foo/bar") - 1), "Length not set correctly");
+	zassert_equal(res, RES(3), "Resource mismatch");
+
+	res = CHECK_PATH(service_D, "/foo/bar?param=value", &len);
+	zassert_not_null(res, "Resource not found");
+	zassert_true(len == (sizeof("/foo/bar") - 1), "Length not set correctly");
+	zassert_equal(res, RES(3), "Resource mismatch");
+
+	res = CHECK_PATH(service_D, "/bar?foo=value", &len);
+	zassert_is_null(res, "Resource found");
+	zassert_equal(len, 0, "Length set");
+
+	res = CHECK_PATH(service_D, "/foo/bar?param=value", &len);
+	zassert_not_null(res, "Resource not found");
+	zassert_true(len == (sizeof("/foo/bar") - 1), "Length not set correctly");
+	zassert_equal(res, RES(3), "Resource mismatch");
+}
+
+ZTEST(http_service, test_HTTP_RESOURCE_DEFAULT)
+{
+#define NON_EXISTING_PATH "/this_path_is_not_registered"
+	struct http_resource_detail *res;
+	int len;
+
+	/* For a path that does exist, the correct resource should be returned */
+	res = CHECK_PATH(service_E, "/index.html", &len);
+	zassert_not_null(res, "Cannot find resource");
+	zassert_true(len > 0, "Length not set");
+	zassert_equal(res, RES(4), "Resource mismatch");
+
+	/* For a path that does not exist, the default resource should be returned */
+	res = CHECK_PATH(service_E, NON_EXISTING_PATH, &len);
+	zassert_not_null(res, "Cannot find resource");
+	zassert_equal(len, strlen(NON_EXISTING_PATH), "Length incorrect");
+	zassert_equal(res, RES(0), "Resource mismatch");
+
+	/* If query params are present, length should not include them */
+	res = CHECK_PATH(service_E, NON_EXISTING_PATH "?param=value", &len);
+	zassert_not_null(res, "Cannot find resource");
+	zassert_equal(len, strlen(NON_EXISTING_PATH), "Length incorrect");
+	zassert_equal(res, RES(0), "Resource mismatch");
 }
 
 extern void http_server_get_content_type_from_extension(char *url, char *content_type,
diff --git a/tests/net/lib/http_server/common/testcase.yaml b/tests/net/lib/http_server/common/testcase.yaml
index 530fab321bf..1c5132557cc 100644
--- a/tests/net/lib/http_server/common/testcase.yaml
+++ b/tests/net/lib/http_server/common/testcase.yaml
@@ -7,8 +7,5 @@ common:
     - server
   integration_platforms:
     - native_sim
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   net.http.server.common: {}
diff --git a/tests/net/lib/http_server/core/boards/native_sim.conf b/tests/net/lib/http_server/core/boards/native_sim.conf
new file mode 100644
index 00000000000..f9430637c0a
--- /dev/null
+++ b/tests/net/lib/http_server/core/boards/native_sim.conf
@@ -0,0 +1,7 @@
+# File system config
+CONFIG_FLASH=y
+CONFIG_FLASH_MAP=y
+CONFIG_FILE_SYSTEM=y
+CONFIG_FILE_SYSTEM_LITTLEFS=y
+CONFIG_FS_LITTLEFS_FC_HEAP_SIZE=16384
+CONFIG_HEAP_MEM_POOL_SIZE=4096
diff --git a/tests/net/lib/http_server/core/boards/qemu_x86.conf b/tests/net/lib/http_server/core/boards/qemu_x86.conf
new file mode 100644
index 00000000000..f9430637c0a
--- /dev/null
+++ b/tests/net/lib/http_server/core/boards/qemu_x86.conf
@@ -0,0 +1,7 @@
+# File system config
+CONFIG_FLASH=y
+CONFIG_FLASH_MAP=y
+CONFIG_FILE_SYSTEM=y
+CONFIG_FILE_SYSTEM_LITTLEFS=y
+CONFIG_FS_LITTLEFS_FC_HEAP_SIZE=16384
+CONFIG_HEAP_MEM_POOL_SIZE=4096
diff --git a/tests/net/lib/http_server/core/prj.conf b/tests/net/lib/http_server/core/prj.conf
index dc035db727d..0668f130702 100644
--- a/tests/net/lib/http_server/core/prj.conf
+++ b/tests/net/lib/http_server/core/prj.conf
@@ -44,10 +44,12 @@ CONFIG_HTTP_SERVER=y
 CONFIG_HTTP_SERVER_CAPTURE_HEADERS=y
 CONFIG_HTTP_SERVER_CAPTURE_HEADER_BUFFER_SIZE=64
 CONFIG_HTTP_SERVER_CAPTURE_HEADER_COUNT=2
+CONFIG_HTTP_SERVER_REPORT_FAILURE_REASON=y
 
 CONFIG_HTTP_SERVER_MAX_CLIENTS=5
 CONFIG_HTTP_SERVER_MAX_STREAMS=5
 CONFIG_HTTP_SERVER_RESTART_DELAY=10
+CONFIG_HTTP_SERVER_COMPRESSION=y
 
 # Network address config
 CONFIG_NET_CONFIG_SETTINGS=n
diff --git a/tests/net/lib/http_server/core/ramdisk.overlay b/tests/net/lib/http_server/core/ramdisk.overlay
new file mode 100644
index 00000000000..14e8918ca45
--- /dev/null
+++ b/tests/net/lib/http_server/core/ramdisk.overlay
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	ramdisk0 {
+		compatible = "zephyr,ram-disk";
+		disk-name = "RAM";
+		sector-size = <512>;
+		sector-count = <160>;
+	};
+};
diff --git a/tests/net/lib/http_server/core/src/main.c b/tests/net/lib/http_server/core/src/main.c
index eeabe8cc30a..0ace8f23c9d 100644
--- a/tests/net/lib/http_server/core/src/main.c
+++ b/tests/net/lib/http_server/core/src/main.c
@@ -27,6 +27,7 @@
 #define TEST_DYNAMIC_POST_PAYLOAD "Test dynamic POST"
 #define TEST_DYNAMIC_GET_PAYLOAD "Test dynamic GET"
 #define TEST_STATIC_PAYLOAD "Hello, World!"
+#define TEST_STATIC_FS_PAYLOAD "Hello, World from static file!"
 
 /* Random base64 encoded data */
 #define TEST_LONG_PAYLOAD_CHUNK_1                                                                  \
@@ -225,10 +226,16 @@ BUILD_ASSERT(sizeof(long_payload) - 1 > CONFIG_HTTP_SERVER_CLIENT_BUFFER_SIZE,
 	0x93, 0x13, 0x7a, 0x88, 0x25, 0xb6, 0x50, 0xc3, 0xcb, 0xbc, 0xb8, 0x3f, \
 	0x53, 0x03, 0x2a, 0x2f, 0x2a, 0x5f, 0x87, 0x49, 0x7c, 0xa5, 0x8a, 0xe8, \
 	0x19, 0xaa
+#define TEST_HTTP2_HEADERS_POST_ROOT_STREAM_1 \
+	0x00, 0x00, 0x21, 0x01, 0x05, 0x00, 0x00, 0x00, TEST_STREAM_ID_1, \
+	0x83, 0x84, 0x86, 0x41, 0x8a, 0x0b, 0xe2, 0x5c, 0x0b, 0x89, 0x70, 0xdc, \
+	0x78, 0x0f, 0x03, 0x53, 0x03, 0x2a, 0x2f, 0x2a, 0x90, 0x7a, 0x8a, 0xaa, \
+	0x69, 0xd2, 0x9a, 0xc4, 0xc0, 0x57, 0x68, 0x0b, 0x83
+#define TEST_HTTP2_DATA_POST_ROOT_STREAM_1 TEST_HTTP2_DATA_POST_DYNAMIC_STREAM_1
 
 static uint16_t test_http_service_port = SERVER_PORT;
 HTTP_SERVICE_DEFINE(test_http_service, SERVER_IPV4_ADDR,
-		    &test_http_service_port, 1, 10, NULL);
+		    &test_http_service_port, 1, 10, NULL, NULL);
 
 static const char static_resource_payload[] = TEST_STATIC_PAYLOAD;
 struct http_resource_detail_static static_resource_detail = {
@@ -245,6 +252,7 @@ HTTP_RESOURCE_DEFINE(static_resource, test_http_service, "/",
 
 static uint8_t dynamic_payload[32];
 static size_t dynamic_payload_len = sizeof(dynamic_payload);
+static bool dynamic_error;
 
 static int dynamic_cb(struct http_client_ctx *client, enum http_data_status status,
 		      const struct http_request_ctx *request_ctx,
@@ -257,6 +265,10 @@ static int dynamic_cb(struct http_client_ctx *client, enum http_data_status stat
 		return 0;
 	}
 
+	if (dynamic_error) {
+		return -ENOMEM;
+	}
+
 	switch (client->method) {
 	case HTTP_GET:
 		response_ctx->body = dynamic_payload;
@@ -660,6 +672,7 @@ static void expect_http2_headers_frame(size_t *offset, int stream_id, uint8_t fl
 	test_consume_data(offset, frame.length);
 }
 
+/* "payload" may be NULL to skip data frame content validation. */
 static void expect_http2_data_frame(size_t *offset, int stream_id,
 				    const uint8_t *payload, size_t payload_len,
 				    uint8_t flags)
@@ -672,11 +685,17 @@ static void expect_http2_data_frame(size_t *offset, int stream_id,
 	zassert_equal(frame.stream_identifier, stream_id,
 		      "Invalid data frame stream ID");
 	zassert_equal(frame.flags, flags, "Unexpected flags received");
-	zassert_equal(frame.length, payload_len, "Unexpected data frame length");
+	if (payload != NULL) {
+		zassert_equal(frame.length, payload_len,
+			      "Unexpected data frame length");
+	}
 
 	/* Verify data payload */
 	test_read_data(offset, frame.length);
-	zassert_mem_equal(buf, payload, payload_len, "Unexpected data payload");
+	if (payload != NULL) {
+		zassert_mem_equal(buf, payload, payload_len,
+				  "Unexpected data payload");
+	}
 	test_consume_data(offset, frame.length);
 }
 
@@ -1412,6 +1431,8 @@ static void test_http1_header_capture_common(const char *request)
 	zassert_not_equal(ret, -1, "send() failed (%d)", errno);
 
 	test_read_data(&offset, sizeof(http1_header_capture_common_response) - 1);
+	zassert_mem_equal(buf, http1_header_capture_common_response,
+			  sizeof(http1_header_capture_common_response) - 1);
 }
 
 ZTEST(server_function_tests, test_http1_header_capture)
@@ -2153,6 +2174,191 @@ ZTEST(server_function_tests, test_http2_dynamic_post_response_header_long)
 	zassert_mem_equal(dynamic_response_headers_buffer, long_payload, strlen(long_payload));
 }
 
+ZTEST(server_function_tests, test_http1_409_method_not_allowed)
+{
+	static const char http1_request[] =
+		"POST / HTTP/1.1\r\n"
+		"Host: 127.0.0.1:8080\r\n"
+		"Content-Type: text/html\r\n"
+		"Content-Length: 13\r\n\r\n"
+		TEST_STATIC_PAYLOAD;
+	static const char expected_response[] =
+		"HTTP/1.1 405 Method Not Allowed\r\n";
+	size_t offset = 0;
+	int ret;
+
+	ret = zsock_send(client_fd, http1_request, strlen(http1_request), 0);
+	zassert_not_equal(ret, -1, "send() failed (%d)", errno);
+
+	memset(buf, 0, sizeof(buf));
+
+	test_read_data(&offset, sizeof(expected_response) - 1);
+	zassert_mem_equal(buf, expected_response, sizeof(expected_response) - 1,
+			  "Received data doesn't match expected response");
+}
+
+ZTEST(server_function_tests, test_http1_upgrade_409_method_not_allowed)
+{
+	static const char http1_request[] =
+		"POST / HTTP/1.1\r\n"
+		"Host: 127.0.0.1:8080\r\n"
+		"Content-Type: text/html\r\n"
+		"Content-Length: 13\r\n"
+		"Connection: Upgrade, HTTP2-Settings\r\n"
+		"Upgrade: h2c\r\n"
+		"HTTP2-Settings: AAMAAABkAAQAoAAAAAIAAAAA\r\n\r\n"
+		TEST_STATIC_PAYLOAD;
+	const struct http_header expected_headers[] = {
+		{.name = ":status", .value = "405"}
+	};
+	size_t offset = 0;
+	int ret;
+
+	ret = zsock_send(client_fd, http1_request, strlen(http1_request), 0);
+	zassert_not_equal(ret, -1, "send() failed (%d)", errno);
+
+	memset(buf, 0, sizeof(buf));
+
+	/* Verify HTTP1 switching protocols response. */
+	expect_http1_switching_protocols(&offset);
+
+	/* Verify HTTP2 frames. */
+	expect_http2_settings_frame(&offset, false);
+	expect_http2_headers_frame(&offset, UPGRADE_STREAM_ID,
+				   HTTP2_FLAG_END_HEADERS | HTTP2_FLAG_END_STREAM,
+				   expected_headers, 1);
+}
+
+ZTEST(server_function_tests, test_http2_409_method_not_allowed)
+{
+	static const uint8_t request_post_static[] = {
+		TEST_HTTP2_MAGIC,
+		TEST_HTTP2_SETTINGS,
+		TEST_HTTP2_SETTINGS_ACK,
+		TEST_HTTP2_HEADERS_POST_ROOT_STREAM_1,
+		TEST_HTTP2_DATA_POST_ROOT_STREAM_1,
+		TEST_HTTP2_GOAWAY,
+	};
+	const struct http_header expected_headers[] = {
+		{.name = ":status", .value = "405"}
+	};
+	size_t offset = 0;
+	int ret;
+
+	ret = zsock_send(client_fd, request_post_static,
+			 sizeof(request_post_static), 0);
+	zassert_not_equal(ret, -1, "send() failed (%d)", errno);
+
+	memset(buf, 0, sizeof(buf));
+
+	expect_http2_settings_frame(&offset, false);
+	expect_http2_settings_frame(&offset, true);
+	expect_http2_headers_frame(&offset, TEST_STREAM_ID_1,
+				   HTTP2_FLAG_END_HEADERS | HTTP2_FLAG_END_STREAM,
+				   expected_headers, 1);
+}
+
+ZTEST(server_function_tests, test_http1_500_internal_server_error)
+{
+	static const char http1_request[] =
+		"GET /dynamic HTTP/1.1\r\n"
+		"Host: 127.0.0.1:8080\r\n"
+		"User-Agent: curl/7.68.0\r\n"
+		"Accept: */*\r\n"
+		"Accept-Encoding: deflate, gzip, br\r\n"
+		"\r\n";
+	static const char expected_response[] =
+		"HTTP/1.1 500 Internal Server Error\r\n";
+	size_t offset = 0;
+	int ret;
+
+	dynamic_error = true;
+
+	ret = zsock_send(client_fd, http1_request, strlen(http1_request), 0);
+	zassert_not_equal(ret, -1, "send() failed (%d)", errno);
+
+	memset(buf, 0, sizeof(buf));
+
+	test_read_data(&offset, sizeof(expected_response) - 1);
+	zassert_mem_equal(buf, expected_response, sizeof(expected_response) - 1,
+			  "Received data doesn't match expected response");
+}
+
+ZTEST(server_function_tests, test_http1_upgrade_500_internal_server_error)
+{
+	static const char http1_request[] =
+		"GET /dynamic HTTP/1.1\r\n"
+		"Host: 127.0.0.1:8080\r\n"
+		"User-Agent: curl/7.68.0\r\n"
+		"Accept: */*\r\n"
+		"Accept-Encoding: deflate, gzip, br\r\n"
+		"Connection: Upgrade, HTTP2-Settings\r\n"
+		"Upgrade: h2c\r\n"
+		"HTTP2-Settings: AAMAAABkAAQAoAAAAAIAAAAA\r\n"
+		"\r\n";
+	const struct http_header expected_headers[] = {
+		{.name = ":status", .value = "500"}
+	};
+	size_t offset = 0;
+	int ret;
+
+	dynamic_error = true;
+
+	ret = zsock_send(client_fd, http1_request, strlen(http1_request), 0);
+	zassert_not_equal(ret, -1, "send() failed (%d)", errno);
+
+	memset(buf, 0, sizeof(buf));
+
+	/* Verify HTTP1 switching protocols response. */
+	expect_http1_switching_protocols(&offset);
+
+	/* Verify HTTP2 frames. */
+	expect_http2_settings_frame(&offset, false);
+	expect_http2_headers_frame(&offset, UPGRADE_STREAM_ID,
+				   HTTP2_FLAG_END_HEADERS,
+				   expected_headers, 1);
+	/* Expect data frame with reason but don't check the content as it may
+	 * depend on libc being used (i. e. string returned by strerror()).
+	 */
+	expect_http2_data_frame(&offset, UPGRADE_STREAM_ID, NULL, 0,
+				HTTP2_FLAG_END_STREAM);
+}
+
+ZTEST(server_function_tests, test_http2_500_internal_server_error)
+{
+	static const uint8_t request_get_dynamic[] = {
+		TEST_HTTP2_MAGIC,
+		TEST_HTTP2_SETTINGS,
+		TEST_HTTP2_SETTINGS_ACK,
+		TEST_HTTP2_HEADERS_GET_DYNAMIC_STREAM_1,
+		TEST_HTTP2_GOAWAY,
+	};
+	const struct http_header expected_headers[] = {
+		{.name = ":status", .value = "500"}
+	};
+	size_t offset = 0;
+	int ret;
+
+	dynamic_error = true;
+
+	ret = zsock_send(client_fd, request_get_dynamic,
+			 sizeof(request_get_dynamic), 0);
+	zassert_not_equal(ret, -1, "send() failed (%d)", errno);
+
+	memset(buf, 0, sizeof(buf));
+
+	expect_http2_settings_frame(&offset, false);
+	expect_http2_settings_frame(&offset, true);
+	expect_http2_headers_frame(&offset, TEST_STREAM_ID_1,
+				   HTTP2_FLAG_END_HEADERS,
+				   expected_headers, 1);
+	/* Expect data frame with reason but don't check the content as it may
+	 * depend on libc being used (i. e. string returned by strerror()).
+	 */
+	expect_http2_data_frame(&offset, TEST_STREAM_ID_1, NULL, 0,
+				HTTP2_FLAG_END_STREAM);
+}
+
 ZTEST(server_function_tests_no_init, test_http_server_start_stop)
 {
 	struct sockaddr_in sa = { 0 };
@@ -2285,6 +2491,296 @@ ZTEST(server_function_tests_no_init, test_parse_http_frames)
 		      "Expected stream_identifier for the 2nd frame doesn't match");
 }
 
+#if DT_HAS_COMPAT_STATUS_OKAY(zephyr_ram_disk)
+
+#include <zephyr/fs/fs.h>
+#include <zephyr/fs/littlefs.h>
+
+FS_LITTLEFS_DECLARE_DEFAULT_CONFIG(storage);
+
+#define TEST_PARTITION		storage_partition
+#define TEST_PARTITION_ID	FIXED_PARTITION_ID(TEST_PARTITION)
+
+#define LFS_MNTP		"/littlefs"
+#define TEST_FILE		"static_file.html"
+#define TEST_DIR		"/files"
+#define TEST_DIR_PATH		LFS_MNTP TEST_DIR
+
+static struct http_resource_detail_static_fs static_file_resource_detail = {
+	.common = {
+			.type = HTTP_RESOURCE_TYPE_STATIC_FS,
+			.bitmask_of_supported_http_methods = BIT(HTTP_GET),
+			.content_type = "text/html",
+		},
+	.fs_path = TEST_DIR_PATH,
+};
+
+HTTP_RESOURCE_DEFINE(static_file_resource, test_http_service, "/static_file.html",
+		     &static_file_resource_detail);
+
+struct fs_mount_t littlefs_mnt = {
+	.type = FS_LITTLEFS,
+	.fs_data = &storage,
+	.storage_dev = (void *)TEST_PARTITION_ID,
+	.mnt_point = LFS_MNTP,
+};
+
+void test_clear_flash(void)
+{
+	int rc;
+	const struct flash_area *fap;
+
+	rc = flash_area_open(TEST_PARTITION_ID, &fap);
+	zassert_equal(rc, 0, "Opening flash area for erase [%d]\n", rc);
+
+	rc = flash_area_flatten(fap, 0, fap->fa_size);
+	zassert_equal(rc, 0, "Erasing flash area [%d]\n", rc);
+}
+
+static int test_mount(void)
+{
+	int ret;
+
+	ret = fs_mount(&littlefs_mnt);
+	if (ret < 0) {
+		TC_PRINT("Error mounting fs [%d]\n", ret);
+		return TC_FAIL;
+	}
+
+	return TC_PASS;
+}
+
+static int test_unmount(void)
+{
+	int ret;
+
+	ret = fs_unmount(&littlefs_mnt);
+	if (ret < 0 && ret != -EINVAL) {
+		TC_PRINT("Error unmounting fs [%d]\n", ret);
+		return TC_FAIL;
+	}
+
+	return TC_PASS;
+}
+
+#ifndef PATH_MAX
+#define PATH_MAX 64
+#endif
+
+int check_file_dir_exists(const char *fpath)
+{
+	int res;
+	struct fs_dirent entry;
+
+	res = fs_stat(fpath, &entry);
+
+	return !res;
+}
+
+int test_file_write(struct fs_file_t *filep, const char *test_str)
+{
+	ssize_t brw;
+	int res;
+
+	TC_PRINT("\nWrite tests:\n");
+
+	/* Verify fs_seek() */
+	res = fs_seek(filep, 0, FS_SEEK_SET);
+	if (res) {
+		TC_PRINT("fs_seek failed [%d]\n", res);
+		fs_close(filep);
+		return res;
+	}
+
+	TC_PRINT("Data written:\"%s\"\n\n", test_str);
+
+	/* Verify fs_write() */
+	brw = fs_write(filep, (char *)test_str, strlen(test_str));
+	if (brw < 0) {
+		TC_PRINT("Failed writing to file [%zd]\n", brw);
+		fs_close(filep);
+		return brw;
+	}
+
+	if (brw < strlen(test_str)) {
+		TC_PRINT("Unable to complete write. Volume full.\n");
+		TC_PRINT("Number of bytes written: [%zd]\n", brw);
+		fs_close(filep);
+		return TC_FAIL;
+	}
+
+	TC_PRINT("Data successfully written!\n");
+
+	return res;
+}
+
+int test_mkdir(const char *dir_path, const char *file)
+{
+	int res;
+	struct fs_file_t filep;
+	char file_path[PATH_MAX] = { 0 };
+
+	fs_file_t_init(&filep);
+	res = sprintf(file_path, "%s/%s", dir_path, file);
+	__ASSERT_NO_MSG(res < sizeof(file_path));
+
+	if (check_file_dir_exists(dir_path)) {
+		TC_PRINT("Dir %s exists\n", dir_path);
+		return TC_FAIL;
+	}
+
+	TC_PRINT("Creating new dir %s\n", dir_path);
+
+	/* Verify fs_mkdir() */
+	res = fs_mkdir(dir_path);
+	if (res) {
+		TC_PRINT("Error creating dir[%d]\n", res);
+		return res;
+	}
+
+	res = fs_open(&filep, file_path, FS_O_CREATE | FS_O_RDWR);
+	if (res) {
+		TC_PRINT("Failed opening file [%d]\n", res);
+		return res;
+	}
+
+	TC_PRINT("Testing write to file %s\n", file_path);
+	res = test_file_write(&filep, TEST_STATIC_FS_PAYLOAD);
+	if (res) {
+		fs_close(&filep);
+		return res;
+	}
+
+	res = fs_close(&filep);
+	if (res) {
+		TC_PRINT("Error closing file [%d]\n", res);
+		return res;
+	}
+
+	TC_PRINT("Created dir %s!\n", dir_path);
+
+	return res;
+}
+
+static int setup_fs(const char *file_ending)
+{
+	char filename_buf[sizeof(TEST_FILE)+5] = TEST_FILE;
+
+	strcat(filename_buf, file_ending);
+	test_clear_flash();
+
+	zassert_equal(test_unmount(), TC_PASS, "Failed to unmount fs");
+	zassert_equal(test_mount(), TC_PASS, "Failed to mount fs");
+
+	return test_mkdir(TEST_DIR_PATH, filename_buf);
+}
+
+ZTEST(server_function_tests, test_http1_static_fs)
+{
+	static const char http1_request[] =
+		"GET /static_file.html HTTP/1.1\r\n"
+		"Host: 127.0.0.1:8080\r\n"
+		"User-Agent: curl/7.68.0\r\n"
+		"Accept: */*\r\n"
+		"\r\n";
+	static const char expected_response[] =
+		"HTTP/1.1 200 OK\r\n"
+		"Content-Length: 30\r\n"
+		"Content-Type: text/html\r\n"
+		"\r\n"
+		TEST_STATIC_FS_PAYLOAD;
+	size_t offset = 0;
+	int ret;
+
+	ret = setup_fs("");
+	zassert_equal(ret, TC_PASS, "Failed to mount fs");
+
+	ret = zsock_send(client_fd, http1_request, strlen(http1_request), 0);
+	zassert_not_equal(ret, -1, "send() failed (%d)", errno);
+
+	memset(buf, 0, sizeof(buf));
+
+	test_read_data(&offset, sizeof(expected_response) - 1);
+	zassert_mem_equal(buf, expected_response, sizeof(expected_response) - 1,
+			  "Received data doesn't match expected response");
+}
+
+ZTEST(server_function_tests, test_http1_static_fs_compression)
+{
+#define HTTP1_COMPRESSION_REQUEST                                                                  \
+	"GET /static_file.html HTTP/1.1\r\n"                                                       \
+	"Host: 127.0.0.1:8080\r\n"                                                                 \
+	"User-Agent: curl/7.68.0\r\n"                                                              \
+	"Accept: */*\r\n"                                                                          \
+	"Accept-Encoding: %s\r\n"                                                                  \
+	"\r\n"
+#define HTTP1_COMPRESSION_RESPONSE                                                                 \
+	"HTTP/1.1 200 OK\r\n"                                                                      \
+	"Content-Length: 30\r\n"                                                                   \
+	"Content-Type: text/html\r\n"                                                              \
+	"Content-Encoding: %s\r\n"                                                                 \
+	"\r\n" TEST_STATIC_FS_PAYLOAD
+
+	static const char mixed_compression_str[] = "gzip, deflate, br";
+	static char http1_request[sizeof(HTTP1_COMPRESSION_REQUEST) +
+				  ARRAY_SIZE(mixed_compression_str)] = {0};
+	static char expected_response[sizeof(HTTP1_COMPRESSION_RESPONSE) +
+				      HTTP_COMPRESSION_MAX_STRING_LEN] = {0};
+	static const char *const file_ending_map[] = {[HTTP_GZIP] = ".gz",
+						      [HTTP_COMPRESS] = ".lzw",
+						      [HTTP_DEFLATE] = ".zz",
+						      [HTTP_BR] = ".br",
+						      [HTTP_ZSTD] = ".zst"};
+	size_t offset;
+	int ret;
+	int expected_response_size;
+
+	for (enum http_compression i = 0; compression_value_is_valid(i); ++i) {
+		offset = 0;
+
+		if (i == HTTP_NONE) {
+			continue;
+		}
+		TC_PRINT("Testing %s compression...\n", http_compression_text(i));
+		zassert(i < ARRAY_SIZE(file_ending_map) && &file_ending_map[i] != NULL,
+			"No file ending defined for compression");
+
+		sprintf(http1_request, HTTP1_COMPRESSION_REQUEST, http_compression_text(i));
+		expected_response_size = sprintf(expected_response, HTTP1_COMPRESSION_RESPONSE,
+						 http_compression_text(i));
+
+		ret = setup_fs(file_ending_map[i]);
+		zassert_equal(ret, TC_PASS, "Failed to mount fs");
+
+		ret = zsock_send(client_fd, http1_request, strlen(http1_request), 0);
+		zassert_not_equal(ret, -1, "send() failed (%d)", errno);
+
+		memset(buf, 0, sizeof(buf));
+
+		test_read_data(&offset, expected_response_size);
+		zassert_mem_equal(buf, expected_response, expected_response_size,
+				  "Received data doesn't match expected response");
+	}
+
+	offset = 0;
+	TC_PRINT("Testing mixed compression...\n");
+	sprintf(http1_request, HTTP1_COMPRESSION_REQUEST, mixed_compression_str);
+	expected_response_size = sprintf(expected_response, HTTP1_COMPRESSION_RESPONSE,
+					 http_compression_text(HTTP_BR));
+	ret = setup_fs(file_ending_map[HTTP_BR]);
+	zassert_equal(ret, TC_PASS, "Failed to mount fs");
+
+	ret = zsock_send(client_fd, http1_request, strlen(http1_request), 0);
+	zassert_not_equal(ret, -1, "send() failed (%d)", errno);
+
+	memset(buf, 0, sizeof(buf));
+
+	test_read_data(&offset, expected_response_size);
+	zassert_mem_equal(buf, expected_response, expected_response_size,
+			  "Received data doesn't match expected response");
+}
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(zephyr_ram_disk) */
+
 static void http_server_tests_before(void *fixture)
 {
 	struct sockaddr_in sa;
@@ -2301,6 +2797,7 @@ static void http_server_tests_before(void *fixture)
 	memset(&request_headers_clone, 0, sizeof(request_headers_clone));
 	memset(&request_headers_clone2, 0, sizeof(request_headers_clone2));
 	dynamic_payload_len = 0;
+	dynamic_error = false;
 
 	ret = http_server_start();
 	if (ret < 0) {
@@ -2347,6 +2844,8 @@ static void http_server_tests_after(void *fixture)
 	}
 
 	(void)http_server_stop();
+
+	k_yield();
 }
 
 ZTEST_SUITE(server_function_tests, NULL, NULL, http_server_tests_before,
diff --git a/tests/net/lib/http_server/core/testcase.yaml b/tests/net/lib/http_server/core/testcase.yaml
index 3ecfe659d48..6627ff86b3e 100644
--- a/tests/net/lib/http_server/core/testcase.yaml
+++ b/tests/net/lib/http_server/core/testcase.yaml
@@ -1,6 +1,7 @@
 common:
   depends_on: netif
   min_ram: 80
+  min_flash: 200
   tags:
     - http
     - net
@@ -9,8 +10,11 @@ common:
   integration_platforms:
     - native_sim
     - qemu_x86
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   net.http.server.core: {}
+  net.http.server.static.fs:
+    extra_args:
+      - EXTRA_DTC_OVERLAY_FILE="ramdisk.overlay"
+    platform_allow:
+      - native_sim
+      - qemu_x86
diff --git a/tests/net/lib/http_server/crime/src/main.c b/tests/net/lib/http_server/crime/src/main.c
index 992d64eff56..3d84b64db4f 100644
--- a/tests/net/lib/http_server/crime/src/main.c
+++ b/tests/net/lib/http_server/crime/src/main.c
@@ -46,7 +46,7 @@ static const unsigned char compressed_inc_file[] = {
 static uint16_t test_http_service_port = SERVER_PORT;
 HTTP_SERVICE_DEFINE(test_http_service, MY_IPV4_ADDR,
 		    &test_http_service_port, 1,
-		    10, NULL);
+		    10, NULL, NULL);
 
 struct http_resource_detail_static index_html_gz_resource_detail = {
 	.common = {
diff --git a/tests/net/lib/http_server/crime/testcase.yaml b/tests/net/lib/http_server/crime/testcase.yaml
index 5fbcfe5ea27..392e0d30067 100644
--- a/tests/net/lib/http_server/crime/testcase.yaml
+++ b/tests/net/lib/http_server/crime/testcase.yaml
@@ -9,8 +9,5 @@ common:
   integration_platforms:
     - native_sim
     - qemu_x86
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   net.http.server.crime: {}
diff --git a/tests/net/lib/http_server/hpack/testcase.yaml b/tests/net/lib/http_server/hpack/testcase.yaml
index e477628aabf..97cae48854c 100644
--- a/tests/net/lib/http_server/hpack/testcase.yaml
+++ b/tests/net/lib/http_server/hpack/testcase.yaml
@@ -8,8 +8,5 @@ common:
   integration_platforms:
     - native_sim
     - qemu_x86
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   net.http.server.http2_hpack: {}
diff --git a/tests/net/lib/http_server/tls/src/main.c b/tests/net/lib/http_server/tls/src/main.c
index 87551817c71..9361fb1770d 100644
--- a/tests/net/lib/http_server/tls/src/main.c
+++ b/tests/net/lib/http_server/tls/src/main.c
@@ -43,7 +43,7 @@ static const sec_tag_t server_tag_list_verify[] = {
 
 static uint16_t test_http_service_port = SERVER_PORT;
 HTTPS_SERVICE_DEFINE(test_http_service, MY_IPV4_ADDR, &test_http_service_port,
-		     1, 10, NULL, server_tag_list_verify,
+		     1, 10, NULL, NULL, server_tag_list_verify,
 		     sizeof(server_tag_list_verify));
 
 static const unsigned char ca[] = {
diff --git a/tests/net/lib/http_server/tls/testcase.yaml b/tests/net/lib/http_server/tls/testcase.yaml
index c163efb2526..a02b5e72cca 100644
--- a/tests/net/lib/http_server/tls/testcase.yaml
+++ b/tests/net/lib/http_server/tls/testcase.yaml
@@ -9,9 +9,6 @@ common:
   integration_platforms:
     - native_sim
     - qemu_x86
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
   platform_allow:
     - native_sim
     - qemu_x86
diff --git a/tests/net/lib/lwm2m/block_transfer/prj.conf b/tests/net/lib/lwm2m/block_transfer/prj.conf
index 2b036cf0c8e..8ba1ef71a8b 100644
--- a/tests/net/lib/lwm2m/block_transfer/prj.conf
+++ b/tests/net/lib/lwm2m/block_transfer/prj.conf
@@ -14,3 +14,4 @@ CONFIG_LWM2M=y
 CONFIG_LWM2M_COAP_BLOCK_TRANSFER=y
 CONFIG_LWM2M_COAP_BLOCK_SIZE=64
 CONFIG_LWM2M_COAP_ENCODE_BUFFER_SIZE=256
+CONFIG_LWM2M_COAP_MAX_MSG_SIZE=96
diff --git a/tests/net/lib/lwm2m/interop/boards/native_sim.conf b/tests/net/lib/lwm2m/interop/boards/native_sim.conf
index adc3b9907ae..3ca97938bd9 100644
--- a/tests/net/lib/lwm2m/interop/boards/native_sim.conf
+++ b/tests/net/lib/lwm2m/interop/boards/native_sim.conf
@@ -4,7 +4,7 @@ CONFIG_DNS_SERVER1="192.0.2.2"
 CONFIG_LWM2M_DNS_SUPPORT=y
 CONFIG_NET_CONFIG_MY_IPV4_GW="192.0.2.2"
 CONFIG_NATIVE_SIM_SLOWDOWN_TO_REAL_TIME=y
-CONFIG_NATIVE_UART_0_ON_STDINOUT=y
+CONFIG_UART_NATIVE_PTY_0_ON_STDINOUT=y
 CONFIG_ASAN=y
 CONFIG_NATIVE_EXTRA_CMDLINE_ARGS="--seed-random"
 CONFIG_HEAP_MEM_POOL_SIZE=32768
diff --git a/tests/net/lib/lwm2m/interop/osv-scanner.toml b/tests/net/lib/lwm2m/interop/osv-scanner.toml
new file mode 100644
index 00000000000..dfbd321ca9b
--- /dev/null
+++ b/tests/net/lib/lwm2m/interop/osv-scanner.toml
@@ -0,0 +1,3 @@
+[[IgnoredVulns]]
+id = "PYSEC-2019-166"
+reason = "CoAPthon3 is only used for testing purposes."
diff --git a/tests/net/lib/lwm2m/interop/prj.conf b/tests/net/lib/lwm2m/interop/prj.conf
index 2a8ad090074..443531c3e5c 100644
--- a/tests/net/lib/lwm2m/interop/prj.conf
+++ b/tests/net/lib/lwm2m/interop/prj.conf
@@ -82,7 +82,7 @@ CONFIG_MBEDTLS_HEAP_SIZE=7168
 CONFIG_MBEDTLS_CIPHER_AES_ENABLED=y
 CONFIG_MBEDTLS_CIPHER_CCM_ENABLED=y
 # Disable RSA, we don't parse certs: saves flash/memory
-CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_ENABLED=n
+CONFIG_MBEDTLS_RSA_C=n
 # Enable PSK instead
 CONFIG_MBEDTLS_KEY_EXCHANGE_PSK_ENABLED=y
 CONFIG_LWM2M_SECURITY_DTLS_TLS_CIPHERSUITE_MAX=3
diff --git a/tests/net/lib/lwm2m/interop/requirements.txt b/tests/net/lib/lwm2m/interop/requirements.txt
index 38c501218ee..893e4b19cb9 100644
--- a/tests/net/lib/lwm2m/interop/requirements.txt
+++ b/tests/net/lib/lwm2m/interop/requirements.txt
@@ -1 +1 @@
-CoAPthon3
+CoAPthon3>=1.0.2
diff --git a/tests/net/lib/lwm2m/lwm2m_engine/CMakeLists.txt b/tests/net/lib/lwm2m/lwm2m_engine/CMakeLists.txt
index 2538d32a4cd..42887cdd49c 100644
--- a/tests/net/lib/lwm2m/lwm2m_engine/CMakeLists.txt
+++ b/tests/net/lib/lwm2m/lwm2m_engine/CMakeLists.txt
@@ -21,7 +21,6 @@ target_include_directories(app PRIVATE ${ZEPHYR_BASE}/../modules/crypto/mbedtls/
 add_compile_definitions(CONFIG_LWM2M_ENGINE_MAX_PENDING=2)
 add_compile_definitions(CONFIG_LWM2M_ENGINE_MAX_REPLIES=2)
 add_compile_definitions(CONFIG_LWM2M_ENGINE_VALIDATION_BUFFER_SIZE=512)
-add_compile_definitions(CONFIG_LWM2M_ENGINE_MESSAGE_HEADER_SIZE=512)
 add_compile_definitions(CONFIG_LWM2M_ENGINE_MAX_OBSERVER=10)
 add_compile_definitions(CONFIG_LWM2M_ENGINE_STACK_SIZE=2048)
 add_compile_definitions(CONFIG_LWM2M_NUM_BLOCK1_CONTEXT=3)
diff --git a/tests/net/lib/lwm2m/lwm2m_engine/src/main.c b/tests/net/lib/lwm2m/lwm2m_engine/src/main.c
index 98cf431c47d..e72d12896be 100644
--- a/tests/net/lib/lwm2m/lwm2m_engine/src/main.c
+++ b/tests/net/lib/lwm2m/lwm2m_engine/src/main.c
@@ -14,7 +14,7 @@
 
 #include "stubs.h"
 #if defined(CONFIG_NATIVE_SIM_SLOWDOWN_TO_REAL_TIME)
-#include "timer_model.h"
+#include "nsi_timer_model.h"
 #endif
 
 #define LOG_LEVEL	LOG_LEVEL_DBG
diff --git a/tests/net/lib/lwm2m/lwm2m_rd_client/CMakeLists.txt b/tests/net/lib/lwm2m/lwm2m_rd_client/CMakeLists.txt
index 2a8e8959c25..a3f70cd7198 100644
--- a/tests/net/lib/lwm2m/lwm2m_rd_client/CMakeLists.txt
+++ b/tests/net/lib/lwm2m/lwm2m_rd_client/CMakeLists.txt
@@ -18,7 +18,6 @@ target_include_directories(app PRIVATE ${ZEPHYR_BASE}/subsys/net/lib/lwm2m/)
 add_compile_definitions(CONFIG_LWM2M_ENGINE_MAX_PENDING=2)
 add_compile_definitions(CONFIG_LWM2M_ENGINE_MAX_REPLIES=2)
 add_compile_definitions(CONFIG_LWM2M_ENGINE_VALIDATION_BUFFER_SIZE=512)
-add_compile_definitions(CONFIG_LWM2M_ENGINE_MESSAGE_HEADER_SIZE=512)
 add_compile_definitions(CONFIG_LWM2M_RD_CLIENT_ENDPOINT_NAME_MAX_LENGTH=32)
 add_compile_definitions(CONFIG_LWM2M_RD_CLIENT_MAX_RETRIES=2)
 add_compile_definitions(CONFIG_LWM2M_COAP_BLOCK_SIZE=256)
diff --git a/tests/net/lib/mdns_responder/src/main.c b/tests/net/lib/mdns_responder/src/main.c
index 25a50ffe5cf..3d741803e31 100644
--- a/tests/net/lib/mdns_responder/src/main.c
+++ b/tests/net/lib/mdns_responder/src/main.c
@@ -124,7 +124,7 @@ static uint8_t *net_iface_get_mac(const struct device *dev)
 		data->mac_addr[5] = 0x01;
 	}
 
-	data->ll_addr.addr = data->mac_addr;
+	memcpy(data->ll_addr.addr, data->mac_addr, sizeof(data->mac_addr));
 	data->ll_addr.len = 6U;
 
 	return data->mac_addr;
diff --git a/tests/net/lib/mdns_responder/testcase.yaml b/tests/net/lib/mdns_responder/testcase.yaml
index aabe426bdd0..ae9f6d9dbf2 100644
--- a/tests/net/lib/mdns_responder/testcase.yaml
+++ b/tests/net/lib/mdns_responder/testcase.yaml
@@ -3,9 +3,6 @@ common:
     - dns
     - net
   depends_on: netif
-  platform_exclude:
-    - native_posix/native/64
-    - native_posix
 tests:
   net.mdns:
     min_ram: 21
diff --git a/tests/net/lib/mqtt_sn_client/src/mqtt_sn_client.c b/tests/net/lib/mqtt_sn_client/src/mqtt_sn_client.c
index ad014593732..acd26f54774 100644
--- a/tests/net/lib/mqtt_sn_client/src/mqtt_sn_client.c
+++ b/tests/net/lib/mqtt_sn_client/src/mqtt_sn_client.c
@@ -117,7 +117,8 @@ int tp_poll(struct mqtt_sn_client *client)
 	return recvfrom_data.sz;
 }
 
-static ZTEST_BMEM struct mqtt_sn_client mqtt_clients[8];
+#define NUM_TEST_CLIENTS 10
+static ZTEST_BMEM struct mqtt_sn_client mqtt_clients[NUM_TEST_CLIENTS];
 static ZTEST_BMEM struct mqtt_sn_client *mqtt_client;
 
 static void setup(void *f)
@@ -125,6 +126,8 @@ static void setup(void *f)
 	ARG_UNUSED(f);
 	static ZTEST_BMEM size_t i;
 
+	zassert_true(i < NUM_TEST_CLIENTS, "Too few clients, increase NUM_TEST_CLIENTS");
+
 	mqtt_client = &mqtt_clients[i++];
 
 	transport = (struct mqtt_sn_transport){
@@ -139,6 +142,13 @@ static void setup(void *f)
 	k_sem_init(&mqtt_sn_cb_sem, 0, 1);
 }
 
+static void cleanup(void *f)
+{
+	ARG_UNUSED(f);
+
+	mqtt_sn_client_deinit(mqtt_client);
+}
+
 static int input(struct mqtt_sn_client *client, void *buf, size_t sz,
 		 const struct mqtt_sn_data *src_addr)
 {
@@ -222,8 +232,6 @@ static ZTEST(mqtt_sn_client, test_mqtt_sn_handle_advertise)
 	zassert_equal(evt_cb_data.called, 4, "NO event");
 	zassert_equal(evt_cb_data.last_evt.type, MQTT_SN_EVT_DISCONNECTED, "Wrong event");
 	zassert_equal(mqtt_client->state, 0, "Wrong state");
-
-	mqtt_sn_client_deinit(mqtt_client);
 }
 
 static ZTEST(mqtt_sn_client, test_mqtt_sn_add_gw)
@@ -238,8 +246,6 @@ static ZTEST(mqtt_sn_client, test_mqtt_sn_add_gw)
 	zassert_equal(err, 0, "unexpected error %d");
 	zassert_false(sys_slist_is_empty(&mqtt_client->gateway), "GW not saved.");
 	zassert_equal(evt_cb_data.called, 0, "Unexpected event");
-
-	mqtt_sn_client_deinit(mqtt_client);
 }
 
 /* Test send SEARCHGW and GW response */
@@ -271,8 +277,6 @@ static ZTEST(mqtt_sn_client, test_mqtt_sn_search_gw)
 	zassert_equal(err, 0, "unexpected error %d");
 	zassert_false(sys_slist_is_empty(&mqtt_client->gateway), "GW not saved.");
 	zassert_equal(evt_cb_data.last_evt.type, MQTT_SN_EVT_GWINFO, "Wrong event");
-
-	mqtt_sn_client_deinit(mqtt_client);
 }
 
 /* Test send SEARCHGW and peer response */
@@ -306,8 +310,6 @@ static ZTEST(mqtt_sn_client, test_mqtt_sn_search_peer)
 	zassert_false(sys_slist_is_empty(&mqtt_client->gateway), "GW not saved.");
 	zassert_equal(evt_cb_data.called, 1, "NO event");
 	zassert_equal(evt_cb_data.last_evt.type, MQTT_SN_EVT_GWINFO, "Wrong event");
-
-	mqtt_sn_client_deinit(mqtt_client);
 }
 
 static ZTEST(mqtt_sn_client, test_mqtt_sn_respond_searchgw)
@@ -334,14 +336,11 @@ static ZTEST(mqtt_sn_client, test_mqtt_sn_respond_searchgw)
 	zassert_equal(evt_cb_data.called, 1, "NO event");
 	zassert_equal(evt_cb_data.last_evt.type, MQTT_SN_EVT_SEARCHGW, "Wrong event");
 	assert_msg_send(1, 3 + gw_addr.size, NULL);
-
-	mqtt_sn_client_deinit(mqtt_client);
 }
 
 static ZTEST(mqtt_sn_client, test_mqtt_sn_connect_no_will)
 {
 	mqtt_sn_connect_no_will(mqtt_client);
-	mqtt_sn_client_deinit(mqtt_client);
 }
 
 static ZTEST(mqtt_sn_client, test_mqtt_sn_connect_will)
@@ -385,10 +384,9 @@ static ZTEST(mqtt_sn_client, test_mqtt_sn_connect_will)
 	zassert_equal(mqtt_client->state, 1, "Wrong state");
 	zassert_equal(evt_cb_data.called, 1, "NO event");
 	zassert_equal(evt_cb_data.last_evt.type, MQTT_SN_EVT_CONNECTED, "Wrong event");
-
-	mqtt_sn_client_deinit(mqtt_client);
 }
 
+/* Test a simple PUBLISH message */
 static ZTEST(mqtt_sn_client, test_mqtt_sn_publish_qos0)
 {
 	struct mqtt_sn_data data = MQTT_SN_DATA_STRING_LITERAL("Hello, World!");
@@ -408,18 +406,143 @@ static ZTEST(mqtt_sn_client, test_mqtt_sn_publish_qos0)
 	err = k_sem_take(&mqtt_sn_tx_sem, K_SECONDS(10));
 	zassert_equal(err, 0, "Timed out waiting for callback.");
 	assert_msg_send(1, 12, &gw_addr);
+
+	/* Send REGACK in response */
 	err = input(mqtt_client, regack, sizeof(regack), &gw_addr);
 	zassert_equal(err, 0, "unexpected error %d");
 	err = k_sem_take(&mqtt_sn_tx_sem, K_NO_WAIT);
 	assert_msg_send(0, 0, NULL);
+
+	/* Expect PUBLISH to be sent */
 	err = k_sem_take(&mqtt_sn_tx_sem, K_SECONDS(10));
 	zassert_equal(err, 0, "Timed out waiting for callback.");
 	assert_msg_send(1, 20, &gw_addr);
 
+	/* Expect publishes to be empty - all done */
 	zassert_true(sys_slist_is_empty(&mqtt_client->publish), "Publish not empty");
+
+	/* Expect topics not to be empty - should be remembered */
 	zassert_false(sys_slist_is_empty(&mqtt_client->topic), "Topic empty");
+}
 
-	mqtt_sn_client_deinit(mqtt_client);
+/*
+ * Test two PUBLISH messages
+ *
+ * 6.5 Topic Name Registration Procedure
+ * ...
+ * At any point in time a client may have only one REGISTER message outstanding, i.e. it has to wait
+ * for a REGACK message before it can register another topic name.
+ */
+static ZTEST(mqtt_sn_client, test_mqtt_sn_wait_regack)
+{
+	struct mqtt_sn_data data = MQTT_SN_DATA_STRING_LITERAL("Hello, World!");
+	struct mqtt_sn_data topic1 = MQTT_SN_DATA_STRING_LITERAL("zephyr1");
+	struct mqtt_sn_data topic2 = MQTT_SN_DATA_STRING_LITERAL("zephyr2");
+	/* registration ack with topic ID 0x1A1B, msg ID 0x0002, return code accepted */
+	uint8_t regack1[] = {7, 0x0B, 0x1A, 0x1B, 0x00, 0x03, 0};
+	/* registration ack with topic ID 0x1A1C, msg ID 0x0003, return code accepted */
+	uint8_t regack2[] = {7, 0x0B, 0x1A, 0x1C, 0x00, 0x05, 0};
+	int err;
+
+	mqtt_sn_connect_no_will(mqtt_client);
+	err = k_sem_take(&mqtt_sn_tx_sem, K_NO_WAIT);
+
+	err = mqtt_sn_publish(mqtt_client, MQTT_SN_QOS_0, &topic1, false, &data);
+	zassert_equal(err, 0, "Unexpected error %d", err);
+	err = mqtt_sn_publish(mqtt_client, MQTT_SN_QOS_0, &topic2, false, &data);
+	zassert_equal(err, 0, "Unexpected error %d", err);
+
+	assert_msg_send(0, 0, NULL);
+
+	/* Expect one and only one REGISTER to be sent */
+	err = k_sem_take(&mqtt_sn_tx_sem, K_SECONDS(10));
+	zassert_equal(err, 0, "Timed out waiting for callback.");
+	assert_msg_send(1, 13, &gw_addr);
+
+	/* Send REGACK in response */
+	err = input(mqtt_client, regack1, sizeof(regack1), &gw_addr);
+	zassert_equal(err, 0, "unexpected error %d");
+	err = k_sem_take(&mqtt_sn_tx_sem, K_NO_WAIT);
+	assert_msg_send(0, 0, NULL);
+
+	/* Expect one more REGISTER and one PUBLISH to be sent */
+	err = k_sem_take(&mqtt_sn_tx_sem, K_SECONDS(10));
+	zassert_equal(err, 0, "Timed out waiting for callback.");
+	assert_msg_send(2, 20, &gw_addr);
+
+	/* Expect publishes not to be empty - not done yet */
+	zassert_false(sys_slist_is_empty(&mqtt_client->publish), "Publish not empty");
+
+	/* Send next REGACK in response */
+	err = input(mqtt_client, regack2, sizeof(regack2), &gw_addr);
+	zassert_equal(err, 0, "unexpected error %d");
+	err = k_sem_take(&mqtt_sn_tx_sem, K_NO_WAIT);
+	assert_msg_send(0, 0, NULL);
+
+	/* Expect one more PUBLISH to be sent */
+	err = k_sem_take(&mqtt_sn_tx_sem, K_SECONDS(10));
+	zassert_equal(err, 0, "Timed out waiting for callback.");
+	assert_msg_send(1, 20, &gw_addr);
+
+	/* Expect publishes to be empty - all done */
+	zassert_true(sys_slist_is_empty(&mqtt_client->publish), "Publish not empty");
+
+	/* Expect topics not to be empty - should be remembered */
+	zassert_false(sys_slist_is_empty(&mqtt_client->topic), "Topic empty");
+}
+
+/*
+ * Test two SUBSCRIBE / UNSUBSCRIBE messages
+ *
+ * 6.9 Client’s Topic Subscribe/Un-subscribe Procedure
+ * ...
+ * As for the REGISTER procedure, a client may have only one SUBSCRIBE or one UNSUBCRIBE transaction
+ * open at a time.
+ */
+static ZTEST(mqtt_sn_client, test_mqtt_sn_wait_suback)
+{
+	struct mqtt_sn_data topic1 = MQTT_SN_DATA_STRING_LITERAL("zephyr1");
+	struct mqtt_sn_data topic2 = MQTT_SN_DATA_STRING_LITERAL("zephyr2");
+	uint8_t suback1[] = {8, 0x13, 0, 0x1B, 0x1B, 0x00, 0x07, 0};
+	uint8_t suback2[] = {8, 0x13, 0, 0x1B, 0x1C, 0x00, 0x08, 0};
+	int err;
+
+	mqtt_sn_connect_no_will(mqtt_client);
+	err = k_sem_take(&mqtt_sn_tx_sem, K_NO_WAIT);
+
+	err = mqtt_sn_subscribe(mqtt_client, MQTT_SN_QOS_0, &topic1);
+	zassert_ok(err, "Unexpected error %d", err);
+	err = k_sem_take(&mqtt_sn_tx_sem, K_SECONDS(1));
+	/* Expect a SUBSCRIBE message */
+	assert_msg_send(1, 12, &gw_addr);
+
+	err = mqtt_sn_subscribe(mqtt_client, MQTT_SN_QOS_0, &topic2);
+	zassert_ok(err, "Unexpected error %d", err);
+	err = k_sem_take(&mqtt_sn_tx_sem, K_SECONDS(1));
+	/* Expect NO message */
+	assert_msg_send(0, 0, NULL);
+
+	err = input(mqtt_client, suback1, sizeof(suback1), &gw_addr);
+	zassert_ok(err, "unexpected error %d");
+	err = k_sem_take(&mqtt_sn_tx_sem, K_SECONDS(1));
+	/* Expect second SUBSCRIBE message */
+	assert_msg_send(1, 12, &gw_addr);
+
+	err = mqtt_sn_unsubscribe(mqtt_client, MQTT_SN_QOS_0, &topic1);
+	zassert_ok(err, "Unexpected error %d", err);
+	err = k_sem_take(&mqtt_sn_tx_sem, K_SECONDS(1));
+	/* Expect NO message - SUBSCRIBE in progress */
+	assert_msg_send(0, 0, NULL);
+
+	/* Unsubscribe while subscribe in progress - should fail */
+	err = mqtt_sn_unsubscribe(mqtt_client, MQTT_SN_QOS_0, &topic2);
+	zassert_not_ok(err, "Error expected");
+
+	err = input(mqtt_client, suback2, sizeof(suback2), &gw_addr);
+	zassert_ok(err, "unexpected error %d");
+	err = k_sem_take(&mqtt_sn_tx_sem, K_SECONDS(1));
+	/* Expect UNSUBSCRIBE message */
+	assert_msg_send(1, 12, &gw_addr);
 }
 
-ZTEST_SUITE(mqtt_sn_client, NULL, NULL, setup, NULL, NULL);
+ZTEST_SUITE(mqtt_sn_client, NULL, NULL, setup, cleanup, NULL);
diff --git a/tests/net/lib/prometheus/collector/testcase.yaml b/tests/net/lib/prometheus/collector/testcase.yaml
index 978c8e601de..8c16ec03a0b 100644
--- a/tests/net/lib/prometheus/collector/testcase.yaml
+++ b/tests/net/lib/prometheus/collector/testcase.yaml
@@ -5,7 +5,4 @@ tests:
     integration_platforms:
       - native_sim
       - qemu_x86
-    platform_exclude:
-      - native_posix
-      - native_posix/native/64
     tags: prometheus
diff --git a/tests/net/lib/prometheus/counter/testcase.yaml b/tests/net/lib/prometheus/counter/testcase.yaml
index 596b3a6e922..97a8431a440 100644
--- a/tests/net/lib/prometheus/counter/testcase.yaml
+++ b/tests/net/lib/prometheus/counter/testcase.yaml
@@ -5,7 +5,4 @@ tests:
     integration_platforms:
       - native_sim
       - qemu_x86
-    platform_exclude:
-      - native_posix
-      - native_posix/native/64
     tags: prometheus
diff --git a/tests/net/lib/prometheus/formatter/testcase.yaml b/tests/net/lib/prometheus/formatter/testcase.yaml
index 16ca0103bde..b80fecbf775 100644
--- a/tests/net/lib/prometheus/formatter/testcase.yaml
+++ b/tests/net/lib/prometheus/formatter/testcase.yaml
@@ -5,7 +5,4 @@ tests:
     integration_platforms:
       - native_sim
       - qemu_x86
-    platform_exclude:
-      - native_posix
-      - native_posix/native/64
     tags: prometheus
diff --git a/tests/net/lib/prometheus/gauge/testcase.yaml b/tests/net/lib/prometheus/gauge/testcase.yaml
index c4e59abbe05..e7e83f40f77 100644
--- a/tests/net/lib/prometheus/gauge/testcase.yaml
+++ b/tests/net/lib/prometheus/gauge/testcase.yaml
@@ -5,7 +5,4 @@ tests:
     integration_platforms:
       - native_sim
       - qemu_x86
-    platform_exclude:
-      - native_posix
-      - native_posix/native/64
     tags: prometheus
diff --git a/tests/net/lib/prometheus/histogram/testcase.yaml b/tests/net/lib/prometheus/histogram/testcase.yaml
index 36eec9aafc0..8f9a0aa3d24 100644
--- a/tests/net/lib/prometheus/histogram/testcase.yaml
+++ b/tests/net/lib/prometheus/histogram/testcase.yaml
@@ -5,7 +5,4 @@ tests:
     integration_platforms:
       - native_sim
       - qemu_x86
-    platform_exclude:
-      - native_posix
-      - native_posix/native/64
     tags: prometheus
diff --git a/tests/net/lib/prometheus/summary/testcase.yaml b/tests/net/lib/prometheus/summary/testcase.yaml
index beea2a5b502..02a9db7ceef 100644
--- a/tests/net/lib/prometheus/summary/testcase.yaml
+++ b/tests/net/lib/prometheus/summary/testcase.yaml
@@ -5,7 +5,4 @@ tests:
     integration_platforms:
       - native_sim
       - qemu_x86
-    platform_exclude:
-      - native_posix
-      - native_posix/native/64
     tags: prometheus
diff --git a/tests/net/lib/wifi_credentials/prj.conf b/tests/net/lib/wifi_credentials/prj.conf
index 6c474ef2777..5ab70cd0126 100644
--- a/tests/net/lib/wifi_credentials/prj.conf
+++ b/tests/net/lib/wifi_credentials/prj.conf
@@ -1,7 +1,7 @@
 #
 # Copyright (c) 2024 Nordic Semiconductor ASA
 #
-# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+# SPDX-License-Identifier: Apache-2.0
 #
 
 CONFIG_ZTEST=y
diff --git a/tests/net/neighbor/src/main.c b/tests/net/neighbor/src/main.c
index b598bd1ce5c..09b9cc08f24 100644
--- a/tests/net/neighbor/src/main.c
+++ b/tests/net/neighbor/src/main.c
@@ -72,7 +72,7 @@ ZTEST(neighbor_test_suite, test_neighbor)
 
 	struct net_nbr *nbr;
 	struct net_linkaddr lladdr;
-	struct net_linkaddr_storage *lladdr_ptr;
+	struct net_linkaddr *lladdr_ptr;
 	struct net_if *iface1 = INT_TO_POINTER(1);
 	struct net_if *iface2 = INT_TO_POINTER(2);
 	int ret, i;
@@ -95,7 +95,7 @@ ZTEST(neighbor_test_suite, test_neighbor)
 	for (i = 0; i < 2; i++) {
 		eth_addr = addrs[i];
 
-		lladdr.addr = eth_addr->addr;
+		memcpy(lladdr.addr, eth_addr->addr, sizeof(struct net_eth_addr));
 
 		ret = net_nbr_link(nbr, iface1, &lladdr);
 
@@ -111,14 +111,15 @@ ZTEST(neighbor_test_suite, test_neighbor)
 		}
 	}
 
-	lladdr.addr = addrs[0]->addr;
+	memcpy(lladdr.addr, addrs[0]->addr, sizeof(struct net_eth_addr));
+
 	nbr = net_nbr_lookup(&net_test_neighbor.table, iface1, &lladdr);
 	zassert_true(nbr->idx == 0, "Wrong index %d should be %d\n", nbr->idx, 0);
 
 	for (i = 0; i < 2; i++) {
 		eth_addr = addrs[i];
 
-		lladdr.addr = eth_addr->addr;
+		memcpy(lladdr.addr, eth_addr->addr, sizeof(struct net_eth_addr));
 
 		ret = net_nbr_unlink(nbr, &lladdr);
 		zassert_false(i == 0 && ret < 0, "Cannot add %s to nbr cache (%d)\n",
@@ -155,7 +156,7 @@ ZTEST(neighbor_test_suite, test_neighbor)
 
 		eth_addr = addrs[i];
 
-		lladdr.addr = eth_addr->addr;
+		memcpy(lladdr.addr, eth_addr->addr, sizeof(struct net_eth_addr));
 
 		ret = net_nbr_link(nbr, iface1, &lladdr);
 		zassert_false(ret < 0, "Cannot add %s to nbr cache (%d)\n",
@@ -166,7 +167,7 @@ ZTEST(neighbor_test_suite, test_neighbor)
 	}
 
 	for (i = 0; i < ARRAY_SIZE(addrs) - 2; i++) {
-		lladdr.addr = addrs[i]->addr;
+		memcpy(lladdr.addr, addrs[i]->addr, sizeof(struct net_eth_addr));
 		nbr = net_nbr_lookup(&net_test_neighbor.table, iface1, &lladdr);
 		zassert_false(nbr->idx != i, "Wrong index %d should be %d\n", nbr->idx, i);
 	}
@@ -174,7 +175,7 @@ ZTEST(neighbor_test_suite, test_neighbor)
 	for (i = 0; i < ARRAY_SIZE(addrs); i++) {
 		eth_addr = addrs[i];
 		nbr = nbrs[i];
-		lladdr.addr = eth_addr->addr;
+		memcpy(lladdr.addr, eth_addr->addr, sizeof(struct net_eth_addr));
 
 		if (!nbr || i >= CONFIG_NET_IPV6_MAX_NEIGHBORS) {
 			break;
@@ -214,7 +215,7 @@ ZTEST(neighbor_test_suite, test_neighbor)
 
 		eth_addr = addrs[i];
 
-		lladdr.addr = eth_addr->addr;
+		memcpy(lladdr.addr, eth_addr->addr, sizeof(struct net_eth_addr));
 
 		if (i % 2) {
 			ret = net_nbr_link(nbr, iface1, &lladdr);
@@ -232,7 +233,8 @@ ZTEST(neighbor_test_suite, test_neighbor)
 	}
 
 	for (i = 0; i < ARRAY_SIZE(addrs) - 2; i++) {
-		lladdr.addr = addrs[i]->addr;
+		memcpy(lladdr.addr, addrs[i]->addr, sizeof(struct net_eth_addr));
+
 		if (i % 2) {
 			nbr = net_nbr_lookup(&net_test_neighbor.table, iface1,
 					     &lladdr);
@@ -257,7 +259,7 @@ ZTEST(neighbor_test_suite, test_neighbor)
 
 		eth_addr = addrs[i];
 		nbr = nbrs[i];
-		lladdr.addr = eth_addr->addr;
+		memcpy(lladdr.addr, eth_addr->addr, sizeof(struct net_eth_addr));
 
 		if (!nbr || i >= CONFIG_NET_IPV6_MAX_NEIGHBORS) {
 			break;
@@ -285,7 +287,8 @@ ZTEST(neighbor_test_suite, test_neighbor)
 	zassert_true(clear_called, "Table clear check failed");
 
 	/* The table should be empty now */
-	lladdr.addr = addrs[0]->addr;
+	memcpy(lladdr.addr, addrs[0]->addr, sizeof(struct net_eth_addr));
+
 	nbr = net_nbr_lookup(&net_test_neighbor.table, iface1, &lladdr);
 
 	zassert_is_null(nbr, "Some entries still found in nbr cache");
diff --git a/tests/net/net_pkt/src/main.c b/tests/net/net_pkt/src/main.c
index ca50aafc98e..1eaf068136d 100644
--- a/tests/net/net_pkt/src/main.c
+++ b/tests/net/net_pkt/src/main.c
@@ -805,11 +805,15 @@ ZTEST(net_pkt_test_suite, test_net_pkt_clone)
 	zassert_true(sizeof(buf) - 6 == net_pkt_remaining_data(pkt),
 		     "Pkt remaining data mismatch");
 
-	net_pkt_lladdr_src(pkt)->addr = pkt->buffer->data;
+	memcpy(net_pkt_lladdr_src(pkt)->addr,
+	       pkt->buffer->data,
+	       NET_LINK_ADDR_MAX_LENGTH);
 	net_pkt_lladdr_src(pkt)->len = NET_LINK_ADDR_MAX_LENGTH;
 	net_pkt_lladdr_src(pkt)->type = NET_LINK_ETHERNET;
 	zassert_mem_equal(net_pkt_lladdr_src(pkt)->addr, buf, NET_LINK_ADDR_MAX_LENGTH);
-	net_pkt_lladdr_dst(pkt)->addr = net_pkt_cursor_get_pos(pkt);
+	memcpy(net_pkt_lladdr_dst(pkt)->addr,
+	       net_pkt_cursor_get_pos(pkt),
+	       NET_LINK_ADDR_MAX_LENGTH);
 	net_pkt_lladdr_dst(pkt)->len = NET_LINK_ADDR_MAX_LENGTH;
 	net_pkt_lladdr_dst(pkt)->type = NET_LINK_ETHERNET;
 	zassert_mem_equal(net_pkt_lladdr_dst(pkt)->addr, &buf[6], NET_LINK_ADDR_MAX_LENGTH);
@@ -875,11 +879,15 @@ ZTEST(net_pkt_test_suite, test_net_pkt_clone)
 		     "Cloned pkt l2_processed flag mismatch");
 
 	zassert_mem_equal(net_pkt_lladdr_src(cloned_pkt)->addr, buf, NET_LINK_ADDR_MAX_LENGTH);
-	zassert_true(net_pkt_lladdr_src(cloned_pkt)->addr == cloned_pkt->buffer->data,
+	zassert_true(memcmp(net_pkt_lladdr_src(cloned_pkt)->addr,
+			    cloned_pkt->buffer->data,
+			    NET_LINK_ADDR_MAX_LENGTH) == 0,
 		     "Cloned pkt ll src addr mismatch");
 
 	zassert_mem_equal(net_pkt_lladdr_dst(cloned_pkt)->addr, &buf[6], NET_LINK_ADDR_MAX_LENGTH);
-	zassert_true(net_pkt_lladdr_dst(cloned_pkt)->addr == net_pkt_cursor_get_pos(cloned_pkt),
+	zassert_true(memcmp(net_pkt_lladdr_dst(cloned_pkt)->addr,
+			    net_pkt_cursor_get_pos(cloned_pkt),
+			    NET_LINK_ADDR_MAX_LENGTH) == 0,
 		     "Cloned pkt ll dst addr mismatch");
 
 	zassert_equal(net_pkt_ll_proto_type(cloned_pkt), ETH_P_IEEE802154,
diff --git a/tests/net/npf/src/main.c b/tests/net/npf/src/main.c
index 39aa63daac2..d85b78539f3 100644
--- a/tests/net/npf/src/main.c
+++ b/tests/net/npf/src/main.c
@@ -75,6 +75,32 @@ static struct net_pkt *build_test_pkt(int type, int size, struct net_if *iface)
 	return pkt;
 }
 
+static struct net_pkt *build_vlan_test_pkt(int type, int size, struct net_if *iface)
+{
+	struct net_pkt *pkt;
+	struct net_eth_vlan_hdr eth_hdr;
+	int ret;
+
+	pkt = net_pkt_rx_alloc_with_buffer(iface, size, AF_UNSPEC, 0, K_NO_WAIT);
+	zassert_not_null(pkt, "");
+
+	eth_hdr.src = ETH_SRC_ADDR;
+	eth_hdr.dst = ETH_DST_ADDR;
+	eth_hdr.type = htons(type);
+	eth_hdr.vlan.tpid = htons(NET_ETH_PTYPE_VLAN);
+
+	ret = net_pkt_write(pkt, &eth_hdr, sizeof(eth_hdr));
+	zassert_equal(ret, 0, "");
+
+	zassert_true(size >= sizeof(eth_hdr), "");
+	zassert_true((size - sizeof(eth_hdr)) <= sizeof(dummy_data), "");
+	ret = net_pkt_write(pkt, dummy_data, size - sizeof(eth_hdr));
+	zassert_equal(ret, 0, "");
+
+	DBG("pkt %p: iface %p size %d type 0x%04x\n", pkt, iface, size, type);
+	return pkt;
+}
+
 static struct net_pkt *build_test_ip_pkt(void *src, void *dst,
 	   sa_family_t family, struct net_if *iface)
 {
@@ -483,4 +509,45 @@ ZTEST(net_pkt_filter_test_suite, test_npf_ipv6_address_filtering)
 	net_pkt_unref(pkt_v4);
 }
 
+static NPF_ETH_VLAN_TYPE_MATCH(vlan_ip_packet, NET_ETH_PTYPE_IP);
+static NPF_RULE(vlan_small_ip_pkt, NET_OK, vlan_ip_packet, maxsize_200);
+
+static void test_npf_example_vlan_common(void)
+{
+	struct net_pkt *pkt;
+
+	/* test small IP packet */
+	pkt = build_vlan_test_pkt(NET_ETH_PTYPE_IP, 100, NULL);
+	zassert_true(net_pkt_filter_recv_ok(pkt), "");
+	net_pkt_unref(pkt);
+
+	/* test "big" IP packet */
+	pkt = build_vlan_test_pkt(NET_ETH_PTYPE_IP, 300, NULL);
+	zassert_false(net_pkt_filter_recv_ok(pkt), "");
+	net_pkt_unref(pkt);
+
+	/* test "small" non-IP packet */
+	pkt = build_vlan_test_pkt(NET_ETH_PTYPE_ARP, 100, NULL);
+	zassert_false(net_pkt_filter_recv_ok(pkt), "");
+	net_pkt_unref(pkt);
+
+	/* test "big" non-IP packet */
+	pkt = build_vlan_test_pkt(NET_ETH_PTYPE_ARP, 300, NULL);
+	zassert_false(net_pkt_filter_recv_ok(pkt), "");
+	net_pkt_unref(pkt);
+}
+
+ZTEST(net_pkt_filter_test_suite, test_npf_vlan_filtering)
+{
+	/* install filter rules */
+	npf_insert_recv_rule(&npf_default_drop);
+	npf_insert_recv_rule(&vlan_small_ip_pkt);
+
+	test_npf_example_vlan_common();
+
+	/* remove filter rules */
+	zassert_true(npf_remove_recv_rule(&npf_default_drop), "");
+	zassert_true(npf_remove_recv_rule(&vlan_small_ip_pkt), "");
+}
+
 ZTEST_SUITE(net_pkt_filter_test_suite, NULL, test_npf_iface, NULL, NULL, NULL);
diff --git a/tests/net/ptp/clock/prj.conf b/tests/net/ptp/clock/prj.conf
index 71efa260d7c..d65b3ad1bb4 100644
--- a/tests/net/ptp/clock/prj.conf
+++ b/tests/net/ptp/clock/prj.conf
@@ -22,7 +22,7 @@ CONFIG_ZTEST=y
 CONFIG_NET_CONFIG_SETTINGS=n
 CONFIG_NET_SHELL=n
 CONFIG_PTP_CLOCK=y
-CONFIG_ETH_NATIVE_POSIX=n
+CONFIG_ETH_NATIVE_TAP=n
 CONFIG_COVERAGE=n
 CONFIG_TEST_USERSPACE=y
 CONFIG_HEAP_MEM_POOL_SIZE=128
diff --git a/tests/net/route/src/main.c b/tests/net/route/src/main.c
index dcdf48cb12e..644c07564ae 100644
--- a/tests/net/route/src/main.c
+++ b/tests/net/route/src/main.c
@@ -116,8 +116,8 @@ static uint8_t *net_route_get_mac(const struct device *dev)
 		route->mac_addr[5] = sys_rand8_get();
 	}
 
-	route->ll_addr.addr = route->mac_addr;
-	route->ll_addr.len = 6U;
+	memcpy(route->ll_addr.addr, route->mac_addr, sizeof(route->mac_addr));
+	route->ll_addr.len = sizeof(route->mac_addr);
 
 	return route->mac_addr;
 }
diff --git a/tests/net/route_mcast/src/main.c b/tests/net/route_mcast/src/main.c
index be30a79462d..3dd3637bbf8 100644
--- a/tests/net/route_mcast/src/main.c
+++ b/tests/net/route_mcast/src/main.c
@@ -157,7 +157,7 @@ static uint8_t *net_route_mcast_get_mac(const struct device *dev)
 		cfg->mac_addr[5] = sys_rand8_get();
 	}
 
-	cfg->ll_addr.addr = cfg->mac_addr;
+	memcpy(cfg->ll_addr.addr, cfg->mac_addr, 6);
 	cfg->ll_addr.len = 6U;
 
 	return cfg->mac_addr;
diff --git a/tests/net/shell/src/main.c b/tests/net/shell/src/main.c
index 39ef093b4e3..d8e3c096531 100644
--- a/tests/net/shell/src/main.c
+++ b/tests/net/shell/src/main.c
@@ -107,24 +107,6 @@ static int tester_send(const struct device *dev, struct net_pkt *pkt)
 	return 0;
 }
 
-static inline struct in_addr *if_get_addr(struct net_if *iface)
-{
-	int i;
-
-	for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) {
-		if (iface->config.ip.ipv4->unicast[i].ipv4.is_used &&
-		    iface->config.ip.ipv4->unicast[i].ipv4.address.family ==
-								AF_INET &&
-		    iface->config.ip.ipv4->unicast[i].ipv4.addr_state ==
-							NET_ADDR_PREFERRED) {
-			return
-			    &iface->config.ip.ipv4->unicast[i].ipv4.address.in_addr;
-		}
-	}
-
-	return NULL;
-}
-
 struct net_udp_context net_udp_context_data;
 
 static struct dummy_api net_udp_if_api = {
diff --git a/tests/net/socket/af_inet_raw/CMakeLists.txt b/tests/net/socket/af_inet_raw/CMakeLists.txt
new file mode 100644
index 00000000000..071665894e1
--- /dev/null
+++ b/tests/net/socket/af_inet_raw/CMakeLists.txt
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(socket_af_inet_raw)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/net/socket/af_inet_raw/prj.conf b/tests/net/socket/af_inet_raw/prj.conf
new file mode 100644
index 00000000000..013fbd3d73d
--- /dev/null
+++ b/tests/net/socket/af_inet_raw/prj.conf
@@ -0,0 +1,19 @@
+CONFIG_ZTEST=y
+CONFIG_NET_TEST=y
+CONFIG_NETWORKING=y
+CONFIG_NET_DRIVERS=y
+CONFIG_NET_LOOPBACK=y
+CONFIG_NET_IPV4=y
+CONFIG_NET_IPV6=y
+CONFIG_NET_IPV6_NBR_CACHE=n
+CONFIG_NET_UDP=y
+CONFIG_NET_UDP_MISSING_CHECKSUM=n
+CONFIG_NET_TCP=y
+CONFIG_NET_CONTEXT_RCVTIMEO=y
+CONFIG_NET_SOCKETS=y
+CONFIG_NET_SOCKETS_INET_RAW=y
+CONFIG_ENTROPY_GENERATOR=y
+CONFIG_TEST_RANDOM_GENERATOR=y
+CONFIG_NET_IF_UNICAST_IPV4_ADDR_COUNT=3
+CONFIG_NET_IF_UNICAST_IPV6_ADDR_COUNT=4
+CONFIG_NET_IF_MCAST_IPV6_ADDR_COUNT=5
diff --git a/tests/net/socket/af_inet_raw/src/main.c b/tests/net/socket/af_inet_raw/src/main.c
new file mode 100644
index 00000000000..90ca11370fc
--- /dev/null
+++ b/tests/net/socket/af_inet_raw/src/main.c
@@ -0,0 +1,952 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdio.h>
+#include <zephyr/net/dummy.h>
+#include <zephyr/net/ethernet.h>
+#include <zephyr/net/net_if.h>
+#include <zephyr/net/socket.h>
+#include <zephyr/random/random.h>
+#include <zephyr/ztest.h>
+
+/* This test suite verify that RAW IP sockets behave according to well known behaviors.
+ * Note, that this is not well standardized and rely on behaviors known from Linux or FreeBSD.
+ *
+ * Sending data (TX):
+ *
+ *   * (AF_INET/6, SOCK_RAW, 0) - The IP header needs to be supplied by the user in the data:
+ *     - test_raw_v4_sock_send_proto_wildcard
+ *     - test_raw_v6_sock_send_proto_wildcard
+ *     - test_raw_v4_sock_sendto
+ *     - test_raw_v6_sock_sendto
+ *     - test_raw_v4_sock_sendmsg
+ *     - test_raw_v6_sock_sendmsg
+ *
+ *   * (AF_INET/6, SOCK_RAW, <protocol>) - Construct IP header according to the protocol number if
+ *     `IP_HDRINCL` socket option is not set. Otherwise, IP header should be provided by the user.
+ *     Currently `IP_HDRINCL` is always considered set:
+ *     - test_raw_v4_sock_send_proto_match
+ *     - test_raw_v4_sock_send_proto_mismatch
+ *     - test_raw_v6_sock_send_proto_match
+ *     - test_raw_v6_sock_send_proto_mismatch
+ *
+ *   * (AF_INET/6, SOCK_RAW, IPPROTO_RAW) - The IP header needs to be supplied by the user in the
+ *     data:
+ *     - test_raw_v4_sock_send_proto_ipproto_raw
+ *     - test_raw_v6_sock_send_proto_ipproto_raw
+ *
+ * Receiving data (RX)
+ *
+ *   *  (AF_INET/6, SOCK_RAW, 0) - 0 value is also `IPPROTO_IP` which is "wildcard" value. The
+ *      packet is received for any IP protocol. It works in similar way as in FreeBSD:
+ *     - test_raw_v4_sock_recv_proto_wildcard
+ *     - test_raw_v6_sock_recv_proto_wildcard
+ *     - test_raw_v4_sock_recvfrom
+ *     - test_raw_v6_sock_recvfrom
+ *     - test_raw_v4_sock_recvmsg
+ *     - test_raw_v6_sock_recvmsg
+ *
+ *   *  (AF_INET/6, SOCK_RAW, <protocol>) - All packets matching the protocol number specified for
+ *      the raw socket are passed to this socket. http://www.iana.org/assignments/protocol-numbers:
+ *     - test_raw_v4_sock_recv_proto_match
+ *     - test_raw_v6_sock_recv_proto_match
+ *
+ *   *  (AF_INET/6, SOCK_RAW, IPPROTO_RAW) - Receiving of all IP protocols via IPPROTO_RAW is not
+ *      possible using raw sockets. https://man7.org/linux/man-pages/man7/raw.7.html:
+ *     - test_raw_v4_sock_recv_proto_ipproto_raw
+ *     - test_raw_v6_sock_recv_proto_ipproto_raw
+ *
+ * See https://sock-raw.org/papers/sock_raw
+ */
+
+static int test_iface_send(const struct device *dev, struct net_pkt *pkt)
+{
+	ARG_UNUSED(dev);
+
+	struct net_pkt *recv_pkt;
+	int ret;
+
+	recv_pkt = net_pkt_rx_clone(pkt, K_NO_WAIT);
+	if (recv_pkt == NULL) {
+		printk("Failed to clone the packet\n");
+		return -ENOMEM;
+	}
+
+	ret = net_recv_data(net_pkt_iface(recv_pkt), recv_pkt);
+	if (ret < 0) {
+		net_pkt_unref(recv_pkt);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void test_iface_init(struct net_if *iface)
+{
+	/* 00-00-5E-00-53-xx Documentation RFC 7042 */
+	uint8_t mac_addr[sizeof(struct net_eth_addr)] = {
+		0x00, 0x00, 0x5e, 0x00, 0x53, 0x00
+	};
+
+	mac_addr[5] = sys_rand8_get();
+
+	net_if_set_link_addr(iface, mac_addr, sizeof(mac_addr),
+			     NET_LINK_ETHERNET);
+}
+
+static struct dummy_api test_iface_if_api = {
+	.iface_api.init = test_iface_init,
+	.send = test_iface_send,
+};
+
+NET_DEVICE_INIT(test_iface_1, "test_iface_1", NULL, NULL, NULL, NULL,
+		CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &test_iface_if_api,
+		DUMMY_L2, NET_L2_GET_CTX_TYPE(DUMMY_L2), 127);
+
+#define TEST_PORT_OWN 4242
+#define TEST_PORT_DST 4243
+
+static struct net_if *test_iface = NET_IF_GET(test_iface_1, 0);
+static struct in_addr test_ipv4_1 = { { { 192, 0, 2, 1 } } };
+static struct in_addr test_ipv4_2 = { { { 192, 0, 2, 2 } } };
+static struct in6_addr test_ipv6_1 = { { {
+	0x20, 0x01, 0x0d, 0xb8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x1
+} } };
+static struct in6_addr test_ipv6_2 = { { {
+	0x20, 0x01, 0x0d, 0xb8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x2
+} } };
+
+static int raw_sock = -1;
+static int raw_sock_2 = -1;
+static int udp_sock = -1;
+static int udp_sock_2 = -1;
+static int packet_sock = -1;
+static struct sockaddr src_addr;
+static struct sockaddr dst_addr;
+static socklen_t addrlen;
+
+static uint8_t test_payload[] = "test_payload";
+static uint8_t rx_buf[128];
+static uint8_t tx_buf[128];
+
+static void prepare_raw_sock_common(int *sock, sa_family_t family,
+				    enum net_ip_protocol proto)
+{
+	struct timeval optval = {
+		.tv_usec = 100000,
+	};
+	int ret;
+
+	*sock = zsock_socket(family, SOCK_RAW, proto);
+	zassert_true(*sock >= 0, "Failed to create RAW socket(%d)", errno);
+
+	ret = zsock_setsockopt(*sock, SOL_SOCKET, SO_RCVTIMEO, &optval,
+			       sizeof(optval));
+	zassert_ok(ret, "setsockopt failed (%d)", errno);
+}
+
+static void prepare_raw_sock(sa_family_t family, enum net_ip_protocol proto)
+{
+	prepare_raw_sock_common(&raw_sock, family, proto);
+}
+
+static void prepare_raw_sock_2(sa_family_t family, enum net_ip_protocol proto)
+{
+	prepare_raw_sock_common(&raw_sock_2, family, proto);
+}
+
+static void prepare_udp_sock_common(int *sock, sa_family_t family,
+				    struct sockaddr *bind_addr)
+{
+	struct timeval optval = {
+		.tv_usec = 100000,
+	};
+	int ret;
+
+	*sock = zsock_socket(family, SOCK_DGRAM, IPPROTO_UDP);
+	zassert_true(*sock >= 0, "Failed to create UDP socket (%d)", errno);
+
+	ret = zsock_bind(*sock, bind_addr, addrlen);
+	zassert_ok(ret, "Binding UDP socket failed (%d)", errno);
+
+	ret = zsock_setsockopt(*sock, SOL_SOCKET, SO_RCVTIMEO, &optval,
+			       sizeof(optval));
+	zassert_ok(ret, "setsockopt failed (%d)", errno);
+}
+
+static void prepare_udp_sock(sa_family_t family)
+{
+	prepare_udp_sock_common(&udp_sock, family, &src_addr);
+}
+
+static void prepare_udp_sock_2(sa_family_t family)
+{
+	prepare_udp_sock_common(&udp_sock_2, family, &dst_addr);
+}
+
+static void prepare_packet_sock(uint16_t proto)
+{
+	struct sockaddr_ll addr = { 0 };
+	struct timeval optval = {
+		.tv_usec = 100000,
+	};
+	int ret;
+
+	memset(&addr, 0, sizeof(addr));
+
+	addr.sll_ifindex = net_if_get_by_iface(test_iface);
+	addr.sll_family = AF_PACKET;
+
+	packet_sock = zsock_socket(AF_PACKET, SOCK_DGRAM, htons(proto));
+	zassert_true(packet_sock >= 0, "Failed to create packet socket (%d)", errno);
+
+	ret = zsock_bind(packet_sock, (struct sockaddr *)&addr, sizeof(addr));
+	zassert_ok(ret, "Binding packet socket failed (%d)", errno);
+
+	ret = zsock_setsockopt(packet_sock, SOL_SOCKET, SO_RCVTIMEO, &optval,
+			       sizeof(optval));
+	zassert_ok(ret, "setsockopt failed (%d)", errno);
+}
+
+static void prepare_addr(sa_family_t family)
+{
+	src_addr.sa_family = family;
+	dst_addr.sa_family = family;
+
+	if (family == AF_INET) {
+		net_sin(&src_addr)->sin_addr = test_ipv4_1;
+		net_sin(&src_addr)->sin_port = htons(TEST_PORT_OWN);
+		net_sin(&dst_addr)->sin_addr = test_ipv4_2;
+		net_sin(&dst_addr)->sin_port = htons(TEST_PORT_DST);
+		addrlen = sizeof(struct sockaddr_in);
+	} else {
+		net_sin6(&src_addr)->sin6_addr = test_ipv6_1;
+		net_sin6(&src_addr)->sin6_port = htons(TEST_PORT_OWN);
+		net_sin6(&dst_addr)->sin6_addr = test_ipv6_2;
+		net_sin6(&dst_addr)->sin6_port = htons(TEST_PORT_DST);
+		addrlen = sizeof(struct sockaddr_in6);
+	}
+}
+
+static void prepare_raw_and_udp_sock_and_addr(sa_family_t family,
+					      enum net_ip_protocol proto)
+{
+	prepare_addr(family);
+	prepare_raw_sock(family, proto);
+	prepare_udp_sock(family);
+}
+
+static void sock_bind_any(int sock, sa_family_t family)
+{
+	struct sockaddr anyaddr = { .sa_family = family };
+	socklen_t bindaddr_len = (family == AF_INET) ?
+		sizeof(struct sockaddr_in) : sizeof(struct sockaddr_in6);
+
+	zassert_ok(zsock_bind(sock, &anyaddr, bindaddr_len),
+		   "Binding RAW socket failed (%d)", errno);
+}
+
+static void test_sockets_close(void)
+{
+	if (raw_sock >= 0) {
+		(void)zsock_close(raw_sock);
+		raw_sock = -1;
+	}
+
+	if (raw_sock_2 >= 0) {
+		(void)zsock_close(raw_sock_2);
+		raw_sock_2 = -1;
+	}
+
+	if (udp_sock >= 0) {
+		(void)zsock_close(udp_sock);
+		udp_sock = -1;
+	}
+
+	if (udp_sock_2 >= 0) {
+		(void)zsock_close(udp_sock_2);
+		udp_sock_2 = -1;
+	}
+
+	if (packet_sock >= 0) {
+		(void)zsock_close(packet_sock);
+		packet_sock = -1;
+	}
+}
+
+static void validate_ip_udp_hdr(sa_family_t family, struct sockaddr *src,
+				struct sockaddr *dst, uint8_t *data,
+				size_t datalen)
+{
+	if (family == AF_INET) {
+		struct net_ipv4_hdr *ipv4 = (struct net_ipv4_hdr *)data;
+		struct net_udp_hdr *udp = (struct net_udp_hdr *)(data + NET_IPV4H_LEN);
+
+		zassert_true(datalen >= NET_IPV4UDPH_LEN, "Packet too short");
+		zassert_equal(ipv4->vhl & 0xF0, 0x40, "Not an IPv4 packet");
+		zassert_mem_equal(ipv4->src, &net_sin(src)->sin_addr, sizeof(ipv4->src),
+				  "Invalid source address");
+		zassert_mem_equal(ipv4->dst, &net_sin(dst)->sin_addr, sizeof(ipv4->dst),
+				  "Invalid destination address");
+		zassert_equal(ipv4->proto, IPPROTO_UDP, "Invalid protocol");
+		zassert_equal(udp->src_port, net_sin(src)->sin_port,
+			      "Invalid source port");
+		zassert_equal(udp->dst_port, net_sin(dst)->sin_port,
+			      "Invalid destination port");
+		zassert_equal(udp->len, htons(datalen - NET_IPV4H_LEN),
+			      "Invalid UDP length");
+	} else {
+		struct net_ipv6_hdr *ipv6 = (struct net_ipv6_hdr *)data;
+		struct net_udp_hdr *udp = (struct net_udp_hdr *)(data + NET_IPV6H_LEN);
+
+		zassert_true(datalen >= NET_IPV6UDPH_LEN, "Packet too short");
+		zassert_equal(ipv6->vtc & 0xF0, 0x60, "Not an IPv6 packet");
+		zassert_mem_equal(ipv6->src, &net_sin6(src)->sin6_addr, sizeof(ipv6->src),
+				  "Invalid source address");
+		zassert_mem_equal(ipv6->dst, &net_sin6(dst)->sin6_addr, sizeof(ipv6->dst),
+				  "Invalid destination address");
+		zassert_equal(ipv6->nexthdr, IPPROTO_UDP, "Invalid protocol");
+		zassert_equal(udp->src_port, net_sin6(src)->sin6_port,
+			      "Invalid source port");
+		zassert_equal(udp->dst_port, net_sin6(dst)->sin6_port,
+			      "Invalid destination port");
+		zassert_equal(udp->len, htons(datalen - NET_IPV6H_LEN),
+			      "Invalid UDP length");
+	}
+}
+
+static void verify_raw_recv_success(int sock, sa_family_t family)
+{
+	size_t headers_len = (family == AF_INET) ? NET_IPV4UDPH_LEN : NET_IPV6UDPH_LEN;
+	size_t expected_len = headers_len + sizeof(test_payload);
+	int ret;
+
+	ret = zsock_recv(sock, rx_buf, sizeof(rx_buf), 0);
+	zassert_not_equal(ret, -1, "Failed to receive RAW packet (%d)", errno);
+	zassert_equal(ret, expected_len, "Invalid data size received (%d, expected %d)",
+		      ret, expected_len);
+
+	validate_ip_udp_hdr(family, &src_addr, &dst_addr, rx_buf, ret);
+	zassert_mem_equal(rx_buf + headers_len, test_payload, sizeof(test_payload),
+			  "Invalid payload received");
+}
+
+static void verify_raw_recv_failure(void)
+{
+	int ret;
+
+	ret = zsock_recv(raw_sock, rx_buf, sizeof(rx_buf), 0);
+	zassert_equal(ret, -1, "RAW receive should fail (%d)", ret);
+	zassert_equal(errno, EAGAIN, "Wrong errno (%d)", errno);
+}
+
+#define TEST_UDP_IVP4_CHKSUM 0x03e4
+#define TEST_UDP_IVP6_CHKSUM 0x930c
+
+static void prepare_raw_ip_packet(sa_family_t family, uint8_t *buf, uint16_t *buflen)
+{
+	uint16_t headers_len = (family == AF_INET) ? NET_IPV4UDPH_LEN : NET_IPV6UDPH_LEN;
+	uint16_t packet_len = headers_len + sizeof(test_payload);
+
+	zassert_true(packet_len <= *buflen, "Packet too long");
+	*buflen = packet_len;
+
+	if (family == AF_INET) {
+		struct net_ipv4_hdr *ipv4 = (struct net_ipv4_hdr *)tx_buf;
+		struct net_udp_hdr *udp = (struct net_udp_hdr *)(tx_buf + NET_IPV4H_LEN);
+
+		/* Prepare IPv4 header */
+		ipv4->vhl = 0x45;
+		ipv4->len = htons(packet_len);
+		ipv4->ttl = 64;
+		ipv4->proto = IPPROTO_UDP;
+		/* UDP socket binds to src_addr, so for this test we swap src/dst */
+		memcpy(ipv4->src, &net_sin(&dst_addr)->sin_addr, sizeof(ipv4->src));
+		memcpy(ipv4->dst, &net_sin(&src_addr)->sin_addr, sizeof(ipv4->dst));
+
+		/* Prepare UDP header */
+		udp->src_port = net_sin(&dst_addr)->sin_port;
+		udp->dst_port = net_sin(&src_addr)->sin_port;
+		udp->len = htons(sizeof(test_payload) + NET_UDPH_LEN);
+		udp->chksum = TEST_UDP_IVP4_CHKSUM;
+
+		memcpy(tx_buf + NET_IPV4UDPH_LEN, test_payload, sizeof(test_payload));
+	} else {
+		struct net_ipv6_hdr *ipv6 = (struct net_ipv6_hdr *)tx_buf;
+		struct net_udp_hdr *udp = (struct net_udp_hdr *)(tx_buf + NET_IPV6H_LEN);
+
+		/* Prepare IPv6 header */
+		ipv6->vtc = 0x60;
+		ipv6->len = htons(sizeof(test_payload) + NET_UDPH_LEN);
+		ipv6->nexthdr = IPPROTO_UDP;
+		ipv6->hop_limit = 64;
+		/* UDP socket binds to src_addr, so for this test we swap src/dst */
+		memcpy(ipv6->src, &net_sin6(&dst_addr)->sin6_addr, sizeof(ipv6->src));
+		memcpy(ipv6->dst, &net_sin6(&src_addr)->sin6_addr, sizeof(ipv6->dst));
+
+		/* Prepare UDP header */
+		udp->src_port = net_sin6(&dst_addr)->sin6_port;
+		udp->dst_port = net_sin6(&src_addr)->sin6_port;
+		udp->len = htons(sizeof(test_payload) + NET_UDPH_LEN);
+		udp->chksum = TEST_UDP_IVP6_CHKSUM;
+
+		memcpy(tx_buf + NET_IPV6UDPH_LEN, test_payload, sizeof(test_payload));
+	}
+}
+
+static void test_raw_sock_send(sa_family_t family, enum net_ip_protocol proto)
+{
+	uint16_t len = sizeof(tx_buf);
+	int ret;
+
+	prepare_raw_and_udp_sock_and_addr(family, proto);
+	prepare_raw_ip_packet(family, tx_buf, &len);
+
+	ret = zsock_send(raw_sock, tx_buf, len, 0);
+	zassert_equal(ret, len, "Failed to send RAW packet (%d)", errno);
+
+	ret = zsock_recv(udp_sock, rx_buf, sizeof(rx_buf), 0);
+	zassert_not_equal(ret, -1, "Failed to receive UDP packet (%d)", errno);
+	zassert_equal(ret, sizeof(test_payload),
+		     "Invalid data size received (%d, expected %d)",
+		      ret, sizeof(test_payload));
+	zassert_mem_equal(rx_buf, test_payload, sizeof(test_payload),
+			  "Invalid payload received");
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v4_sock_send_proto_wildcard)
+{
+	test_raw_sock_send(AF_INET, IPPROTO_IP);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v6_sock_send_proto_wildcard)
+{
+	test_raw_sock_send(AF_INET6, IPPROTO_IP);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v4_sock_send_proto_match)
+{
+	test_raw_sock_send(AF_INET, IPPROTO_UDP);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v6_sock_send_proto_match)
+{
+	test_raw_sock_send(AF_INET6, IPPROTO_UDP);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v4_sock_send_proto_ipproto_raw)
+{
+	test_raw_sock_send(AF_INET, IPPROTO_RAW);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v6_sock_send_proto_ipproto_raw)
+{
+	test_raw_sock_send(AF_INET6, IPPROTO_RAW);
+}
+
+static void test_raw_sock_sendto(sa_family_t family)
+{
+	uint16_t len = sizeof(tx_buf);
+	int ret;
+
+	prepare_raw_and_udp_sock_and_addr(family, IPPROTO_IP);
+	prepare_raw_ip_packet(family, tx_buf, &len);
+
+	ret = zsock_sendto(raw_sock, tx_buf, len, 0, &src_addr, addrlen);
+	zassert_equal(ret, len, "Failed to send RAW packet (%d)", errno);
+
+	ret = zsock_recv(udp_sock, rx_buf, sizeof(rx_buf), 0);
+	zassert_not_equal(ret, -1, "Failed to receive UDP packet (%d)", errno);
+	zassert_equal(ret, sizeof(test_payload),
+		     "Invalid data size received (%d, expected %d)",
+		      ret, sizeof(test_payload));
+	zassert_mem_equal(rx_buf, test_payload, sizeof(test_payload),
+			  "Invalid payload received");
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v4_sock_sendto)
+{
+	test_raw_sock_sendto(AF_INET);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v6_sock_sendto)
+{
+	test_raw_sock_sendto(AF_INET6);
+}
+
+static void test_raw_sock_sendmsg(sa_family_t family)
+{
+	uint16_t len = sizeof(tx_buf);
+	struct iovec io_vector;
+	struct msghdr msg = { 0 };
+	int ret;
+
+	prepare_raw_and_udp_sock_and_addr(family, IPPROTO_IP);
+	prepare_raw_ip_packet(family, tx_buf, &len);
+
+	io_vector.iov_base = tx_buf;
+	io_vector.iov_len = len;
+	msg.msg_iov = &io_vector;
+	msg.msg_iovlen = 1;
+	msg.msg_name = &src_addr;
+	msg.msg_namelen = addrlen;
+
+	ret = zsock_sendmsg(raw_sock, &msg, 0);
+	zassert_equal(ret, len, "Failed to send RAW packet (%d)", errno);
+
+	ret = zsock_recv(udp_sock, rx_buf, sizeof(rx_buf), 0);
+	zassert_not_equal(ret, -1, "Failed to receive UDP packet (%d)", errno);
+	zassert_equal(ret, sizeof(test_payload),
+		     "Invalid data size received (%d, expected %d)",
+		      ret, sizeof(test_payload));
+	zassert_mem_equal(rx_buf, test_payload, sizeof(test_payload),
+			  "Invalid payload received");
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v4_sock_sendmsg)
+{
+	test_raw_sock_sendmsg(AF_INET);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v6_sock_sendmsg)
+{
+	test_raw_sock_sendmsg(AF_INET6);
+}
+
+static void test_raw_sock_recv(sa_family_t family, enum net_ip_protocol proto)
+{
+
+	int ret;
+
+	prepare_raw_and_udp_sock_and_addr(family, proto);
+	sock_bind_any(raw_sock, family);
+
+	ret = zsock_sendto(udp_sock, test_payload, sizeof(test_payload), 0,
+			   &dst_addr, addrlen);
+	zassert_equal(ret, sizeof(test_payload), "Failed to send UDP packet (%d)",
+		      errno);
+
+	if (proto == IPPROTO_IP || proto == IPPROTO_UDP) {
+		verify_raw_recv_success(raw_sock, family);
+	} else {
+		verify_raw_recv_failure();
+	}
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v4_sock_recv_proto_wildcard)
+{
+	test_raw_sock_recv(AF_INET, IPPROTO_IP);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v6_sock_recv_proto_wildcard)
+{
+	test_raw_sock_recv(AF_INET6, IPPROTO_IP);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v4_sock_recv_proto_match)
+{
+	test_raw_sock_recv(AF_INET, IPPROTO_UDP);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v6_sock_recv_proto_match)
+{
+	test_raw_sock_recv(AF_INET6, IPPROTO_UDP);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v4_sock_recv_proto_mismatch)
+{
+	test_raw_sock_recv(AF_INET, IPPROTO_TCP);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v6_sock_recv_proto_mismatch)
+{
+	test_raw_sock_recv(AF_INET6, IPPROTO_TCP);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v4_sock_recv_proto_ipproto_raw)
+{
+	test_raw_sock_recv(AF_INET, IPPROTO_RAW);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v6_sock_recv_proto_ipproto_raw)
+{
+	test_raw_sock_recv(AF_INET6, IPPROTO_RAW);
+}
+
+static void test_raw_sock_recvfrom(sa_family_t family)
+{
+	size_t headers_len = (family == AF_INET) ? NET_IPV4UDPH_LEN : NET_IPV6UDPH_LEN;
+	size_t expected_len = headers_len + sizeof(test_payload);
+	struct sockaddr recv_addr = { 0 };
+	socklen_t recv_addrlen = sizeof(recv_addr);
+	int ret;
+
+	prepare_raw_and_udp_sock_and_addr(family, IPPROTO_IP);
+	sock_bind_any(raw_sock, family);
+
+	ret = zsock_sendto(udp_sock, test_payload, sizeof(test_payload), 0,
+			   &dst_addr, addrlen);
+	zassert_equal(ret, sizeof(test_payload), "Failed to send UDP packet (%d)",
+		      errno);
+
+	ret = zsock_recvfrom(raw_sock, rx_buf, sizeof(rx_buf), 0,
+			     &recv_addr, &recv_addrlen);
+	zassert_not_equal(ret, -1, "Failed to receive RAW packet (%d)", errno);
+	zassert_equal(ret, expected_len, "Invalid data size received (%d, expected %d)",
+		      ret, expected_len);
+	validate_ip_udp_hdr(family, &src_addr, &dst_addr, rx_buf, ret);
+	zassert_mem_equal(rx_buf + headers_len, test_payload, sizeof(test_payload),
+			  "Invalid payload received");
+
+	zassert_equal(recv_addrlen, addrlen, "Invalid sender address length");
+	zassert_equal(recv_addr.sa_family, family, "Invalid sender address family");
+	if (family == AF_INET) {
+		zassert_mem_equal(&net_sin(&recv_addr)->sin_addr,
+				  &net_sin(&src_addr)->sin_addr,
+				  sizeof(struct in_addr), "Invalid sender address");
+	} else {
+		zassert_mem_equal(&net_sin6(&recv_addr)->sin6_addr,
+				  &net_sin6(&src_addr)->sin6_addr,
+				  sizeof(struct in6_addr), "Invalid sender address");
+	}
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v4_sock_recvfrom)
+{
+	test_raw_sock_recvfrom(AF_INET);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v6_sock_recvfrom)
+{
+	test_raw_sock_recvfrom(AF_INET6);
+}
+
+static void test_raw_sock_recvmsg(sa_family_t family)
+{
+	size_t headers_len = (family == AF_INET) ? NET_IPV4UDPH_LEN : NET_IPV6UDPH_LEN;
+	size_t expected_len = headers_len + sizeof(test_payload);
+	struct sockaddr recv_addr = { 0 };
+	struct iovec io_vector;
+	struct msghdr msg = { 0 };
+	int ret;
+
+	prepare_raw_and_udp_sock_and_addr(family, IPPROTO_IP);
+	sock_bind_any(raw_sock, family);
+
+	ret = zsock_sendto(udp_sock, test_payload, sizeof(test_payload), 0,
+			   &dst_addr, addrlen);
+	zassert_equal(ret, sizeof(test_payload), "Failed to send UDP packet (%d)",
+		      errno);
+
+	io_vector.iov_base = rx_buf;
+	io_vector.iov_len = sizeof(rx_buf);
+	msg.msg_iov = &io_vector;
+	msg.msg_iovlen = 1;
+	msg.msg_name = &recv_addr;
+	msg.msg_namelen = sizeof(recv_addr);
+
+	ret = zsock_recvmsg(raw_sock, &msg, 0);
+	zassert_not_equal(ret, -1, "Failed to receive RAW packet (%d)", errno);
+	zassert_equal(ret, expected_len, "Invalid data size received (%d, expected %d)",
+		      ret, expected_len);
+	validate_ip_udp_hdr(family, &src_addr, &dst_addr, rx_buf, ret);
+	zassert_mem_equal(rx_buf + headers_len, test_payload, sizeof(test_payload),
+			  "Invalid payload received");
+
+	zassert_equal(msg.msg_namelen, addrlen, "Invalid sender address length");
+	zassert_equal(recv_addr.sa_family, family, "Invalid sender address family");
+	if (family == AF_INET) {
+		zassert_mem_equal(&net_sin(&recv_addr)->sin_addr,
+				  &net_sin(&src_addr)->sin_addr,
+				  sizeof(struct in_addr), "Invalid sender address");
+	} else {
+		zassert_mem_equal(&net_sin6(&recv_addr)->sin6_addr,
+				  &net_sin6(&src_addr)->sin6_addr,
+				  sizeof(struct in6_addr), "Invalid sender address");
+	}
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v4_sock_recvmsg)
+{
+	test_raw_sock_recvmsg(AF_INET);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v6_sock_recvmsg)
+{
+	test_raw_sock_recvmsg(AF_INET6);
+}
+
+static void test_raw_sock_bind(sa_family_t family, struct sockaddr *bind_addr,
+			       bool shall_receive)
+{
+	int ret;
+
+	prepare_raw_and_udp_sock_and_addr(family, IPPROTO_UDP);
+
+	ret = zsock_bind(raw_sock, bind_addr, addrlen);
+	zassert_ok(ret, "Binding RAW socket failed (%d)", errno);
+
+	ret = zsock_sendto(udp_sock, test_payload, sizeof(test_payload), 0,
+			   &dst_addr, addrlen);
+	zassert_equal(ret, sizeof(test_payload), "Failed to send UDP packet (%d)",
+		      errno);
+
+	if (shall_receive) {
+		verify_raw_recv_success(raw_sock, family);
+	} else {
+		verify_raw_recv_failure();
+	}
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v4_sock_bind)
+{
+	struct sockaddr_in bind_addr = {
+		.sin_family = AF_INET,
+		.sin_addr = test_ipv4_2
+	};
+
+	test_raw_sock_bind(AF_INET, (struct sockaddr *)&bind_addr, true);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v6_sock_bind)
+{
+	struct sockaddr_in6 bind_addr = {
+		.sin6_family = AF_INET6,
+		.sin6_addr = test_ipv6_2
+	};
+
+	test_raw_sock_bind(AF_INET6, (struct sockaddr *)&bind_addr, true);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v4_sock_bind_other_addr)
+{
+	struct sockaddr_in bind_addr = {
+		.sin_family = AF_INET,
+		.sin_addr = test_ipv4_1
+	};
+
+	test_raw_sock_bind(AF_INET, (struct sockaddr *)&bind_addr, false);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v6_sock_bind_other_addr)
+{
+	struct sockaddr_in6 bind_addr = {
+		.sin6_family = AF_INET6,
+		.sin6_addr = test_ipv6_1
+	};
+
+	test_raw_sock_bind(AF_INET6, (struct sockaddr *)&bind_addr, false);
+}
+
+static void test_raw_sock_recv_no_cross_family(sa_family_t family_raw)
+{
+	sa_family_t family_udp = family_raw == AF_INET ? AF_INET6 : AF_INET;
+	int ret;
+
+	prepare_addr(family_udp);
+	prepare_raw_sock(family_raw, IPPROTO_UDP);
+	prepare_udp_sock(family_udp);
+	sock_bind_any(raw_sock, family_raw);
+
+	ret = zsock_sendto(udp_sock, test_payload, sizeof(test_payload), 0,
+			   &dst_addr, addrlen);
+	zassert_equal(ret, sizeof(test_payload), "Failed to send UDP packet (%d)",
+		      errno);
+
+	/* RAW socket should not get the packet from a different family (i.e.
+	 * no IPv4 packet on IPv6 socket and vice versa).
+	 */
+	verify_raw_recv_failure();
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v4_sock_recv_no_ipv6)
+{
+	test_raw_sock_recv_no_cross_family(AF_INET);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_v6_sock_recv_no_ipv4)
+{
+	test_raw_sock_recv_no_cross_family(AF_INET6);
+}
+
+static void test_two_raw_socks_recv(sa_family_t family)
+{
+	int ret;
+
+	prepare_raw_and_udp_sock_and_addr(family, IPPROTO_UDP);
+	prepare_raw_sock_2(family, IPPROTO_IP);
+	sock_bind_any(raw_sock, family);
+	sock_bind_any(raw_sock_2, family);
+
+	ret = zsock_sendto(udp_sock, test_payload, sizeof(test_payload), 0,
+			   &dst_addr, addrlen);
+	zassert_equal(ret, sizeof(test_payload), "Failed to send UDP packet (%d)",
+		      errno);
+
+	/* Both RAW sockets should get the packet. */
+	verify_raw_recv_success(raw_sock, family);
+	verify_raw_recv_success(raw_sock_2, family);
+}
+
+ZTEST(socket_af_inet_raw, test_two_raw_v4_socks_recv)
+{
+	test_two_raw_socks_recv(AF_INET);
+}
+
+ZTEST(socket_af_inet_raw, test_two_raw_v6_socks_recv)
+{
+	test_two_raw_socks_recv(AF_INET6);
+}
+
+static void test_raw_and_udp_socks_recv(sa_family_t family)
+{
+	size_t headers_len = (family == AF_INET) ? NET_IPV4UDPH_LEN : NET_IPV6UDPH_LEN;
+	size_t expected_len = headers_len + sizeof(test_payload);
+	int ret;
+
+	prepare_raw_and_udp_sock_and_addr(family, IPPROTO_UDP);
+	prepare_udp_sock_2(family);
+	sock_bind_any(raw_sock, family);
+
+	/* Send to bound UDP endpoint this time */
+	ret = zsock_sendto(udp_sock, test_payload, sizeof(test_payload), 0,
+			   &dst_addr, addrlen);
+	zassert_equal(ret, sizeof(test_payload), "Failed to send UDP packet (%d)",
+		      errno);
+
+	/* Both RAW and UDP sockets should receive the packet. */
+	ret = zsock_recv(raw_sock, rx_buf, sizeof(rx_buf), 0);
+	zassert_not_equal(ret, -1, "Failed to receive RAW packet (%d)", errno);
+	zassert_equal(ret, expected_len,
+		      "Invalid data size received (%d, expected %d)",
+		      ret, expected_len);
+
+	validate_ip_udp_hdr(family, &src_addr, &dst_addr, rx_buf, ret);
+	zassert_mem_equal(rx_buf + headers_len, test_payload, sizeof(test_payload),
+			  "Invalid payload received");
+
+	ret = zsock_recv(udp_sock_2, rx_buf, sizeof(rx_buf), 0);
+	zassert_not_equal(ret, -1, "Failed to receive UDP packet (%d)", errno);
+	zassert_equal(ret, sizeof(test_payload),
+		     "Invalid data size received (%d, expected %d)",
+		      ret, sizeof(test_payload));
+	zassert_mem_equal(rx_buf, test_payload, sizeof(test_payload),
+			  "Invalid payload received");
+}
+
+ZTEST(socket_af_inet_raw, test_raw_and_udp_v4_socks_recv)
+{
+	test_raw_and_udp_socks_recv(AF_INET);
+}
+
+ZTEST(socket_af_inet_raw, test_raw_and_udp_v6_socks_recv)
+{
+	test_raw_and_udp_socks_recv(AF_INET6);
+}
+
+static void test_packet_and_raw_socks_recv(sa_family_t family, uint16_t packet_proto)
+{
+	size_t headers_len = (family == AF_INET) ? NET_IPV4UDPH_LEN : NET_IPV6UDPH_LEN;
+	size_t expected_len = headers_len + sizeof(test_payload);
+	int ret;
+
+	prepare_raw_and_udp_sock_and_addr(family, IPPROTO_UDP);
+	prepare_packet_sock(packet_proto);
+	sock_bind_any(raw_sock, family);
+
+	/* Send to bound UDP endpoint this time */
+	ret = zsock_sendto(udp_sock, test_payload, sizeof(test_payload), 0,
+			   &dst_addr, addrlen);
+	zassert_equal(ret, sizeof(test_payload), "Failed to send UDP packet (%d)",
+		      errno);
+
+	/* Both packet and RAW IP sockets should receive the packet. */
+	ret = zsock_recv(packet_sock, rx_buf, sizeof(rx_buf), 0);
+	zassert_not_equal(ret, -1, "Failed to receive packet (%d)", errno);
+	zassert_equal(ret, expected_len,
+		      "Invalid data size received (%d, expected %d)",
+		      ret, expected_len);
+
+	validate_ip_udp_hdr(family, &src_addr, &dst_addr, rx_buf, ret);
+	zassert_mem_equal(rx_buf + headers_len, test_payload, sizeof(test_payload),
+			  "Invalid payload received");
+
+	memset(rx_buf, 0, sizeof(rx_buf));
+
+	ret = zsock_recv(raw_sock, rx_buf, sizeof(rx_buf), 0);
+	zassert_not_equal(ret, -1, "Failed to receive RAW packet (%d)", errno);
+	zassert_equal(ret, expected_len,
+		      "Invalid data size received (%d, expected %d)",
+		      ret, expected_len);
+
+	validate_ip_udp_hdr(family, &src_addr, &dst_addr, rx_buf, ret);
+	zassert_mem_equal(rx_buf + headers_len, test_payload, sizeof(test_payload),
+			  "Invalid payload received");
+
+
+}
+
+ZTEST(socket_af_inet_raw, test_packet_and_raw_v4_socks_recv_wildcard)
+{
+	if (!IS_ENABLED(CONFIG_NET_SOCKETS_PACKET)) {
+		ztest_test_skip();
+	}
+
+	test_packet_and_raw_socks_recv(AF_INET, ETH_P_ALL);
+}
+
+ZTEST(socket_af_inet_raw, test_packet_and_raw_v6_socks_recv_wildcard)
+{
+	if (!IS_ENABLED(CONFIG_NET_SOCKETS_PACKET)) {
+		ztest_test_skip();
+	}
+
+	test_packet_and_raw_socks_recv(AF_INET6, ETH_P_ALL);
+}
+
+ZTEST(socket_af_inet_raw, test_packet_and_raw_v4_socks_recv_proto_match)
+{
+	if (!IS_ENABLED(CONFIG_NET_SOCKETS_PACKET)) {
+		ztest_test_skip();
+	}
+
+	test_packet_and_raw_socks_recv(AF_INET, ETH_P_IP);
+}
+
+ZTEST(socket_af_inet_raw, test_packet_and_raw_v6_socks_recv_proto_match)
+{
+	if (!IS_ENABLED(CONFIG_NET_SOCKETS_PACKET)) {
+		ztest_test_skip();
+	}
+
+	test_packet_and_raw_socks_recv(AF_INET6, ETH_P_IPV6);
+}
+
+static void test_after(void *arg)
+{
+	ARG_UNUSED(arg);
+
+	memset(&rx_buf, 0, sizeof(rx_buf));
+	memset(&tx_buf, 0, sizeof(tx_buf));
+	memset(&src_addr, 0, sizeof(src_addr));
+	memset(&dst_addr, 0, sizeof(dst_addr));
+	addrlen = 0;
+
+	test_sockets_close();
+}
+
+static void *test_setup(void)
+{
+	(void)net_if_ipv4_addr_add(test_iface, &test_ipv4_1, NET_ADDR_MANUAL, 0);
+	(void)net_if_ipv4_addr_add(test_iface, &test_ipv4_2, NET_ADDR_MANUAL, 0);
+	(void)net_if_ipv6_addr_add(test_iface, &test_ipv6_1, NET_ADDR_MANUAL, 0);
+	(void)net_if_ipv6_addr_add(test_iface, &test_ipv6_2, NET_ADDR_MANUAL, 0);
+	(void)net_if_up(test_iface);
+
+	return NULL;
+}
+
+ZTEST_SUITE(socket_af_inet_raw, NULL, test_setup, NULL, test_after, NULL);
diff --git a/tests/net/socket/af_inet_raw/testcase.yaml b/tests/net/socket/af_inet_raw/testcase.yaml
new file mode 100644
index 00000000000..7e11bd04a06
--- /dev/null
+++ b/tests/net/socket/af_inet_raw/testcase.yaml
@@ -0,0 +1,11 @@
+common:
+  depends_on: netif
+  tags:
+    - net
+    - socket
+tests:
+  net.socket.af_inet_raw: {}
+  net.socket.af_inet_raw.af_packet:
+    extra_configs:
+      - CONFIG_NET_SOCKETS_PACKET=y
+      - CONFIG_NET_SOCKETS_PACKET_DGRAM=y
diff --git a/tests/net/socket/af_packet/prj.conf b/tests/net/socket/af_packet/prj.conf
index 2eeb220abdb..342442f9cfc 100644
--- a/tests/net/socket/af_packet/prj.conf
+++ b/tests/net/socket/af_packet/prj.conf
@@ -21,5 +21,7 @@ CONFIG_NET_LOG=y
 CONFIG_TEST_USERSPACE=y
 CONFIG_NET_MAX_CONTEXTS=8
 CONFIG_NET_MAX_CONN=8
+CONFIG_NET_IF_MAX_IPV4_COUNT=2
+CONFIG_NET_CONTEXT_RCVTIMEO=y
 
 CONFIG_MAIN_STACK_SIZE=1024
diff --git a/tests/net/socket/af_packet/src/main.c b/tests/net/socket/af_packet/src/main.c
index df0cb8de533..68b5c58e79f 100644
--- a/tests/net/socket/af_packet/src/main.c
+++ b/tests/net/socket/af_packet/src/main.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2020 Intel Corporation
+ * Copyright (c) 2025 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -14,6 +15,70 @@ LOG_MODULE_REGISTER(net_test, CONFIG_NET_SOCKETS_LOG_LEVEL);
 #include <zephyr/posix/fcntl.h>
 #include <zephyr/net/socket.h>
 #include <zephyr/net/ethernet.h>
+#include <zephyr/net/net_ip.h>
+
+/* This test suite verifies that AF_PACKET sockets behave according to well known behaviors.
+ * Note, that this is not well standardized and relies on behaviors known from Linux or FreeBSD.
+ *
+ * Sending data (TX)
+ *
+ *   * (AF_PACKET, SOCK_RAW, 0) - The packet contains already a valid L2 header:
+ *     - test_raw_sock_sendto_no_proto_bound
+ *     - test_raw_sock_sendto_no_proto_unbound
+ *     - test_raw_sock_sendto_no_proto_unbound_no_iface
+ *     - test_raw_sock_sendto_no_proto_unbound_no_addr
+ *     - test_raw_sock_sendmsg_no_proto
+ *
+ *   * (AF_PACKET, SOCK_DGRAM, 0) - User needs to supply `struct sockaddr_ll` with
+ *     all the relevant fields filled so that L2 header can be constructed:
+ *     - test_dgram_sock_sendto_no_proto_bound
+ *     - test_dgram_sock_sendto_no_proto_unbound
+ *     - test_dgram_sock_sendto_no_proto_unbound_no_iface
+ *     - test_dgram_sock_sendto_no_proto_unbound_no_addr
+ *     - test_dgram_sock_sendmsg_no_proto
+ *
+ *   * (AF_PACKET, SOCK_RAW, <protocol>) - The packet contains already a valid
+ *     L2 header. Not mentioned in packet(7) but as the L2 header needs to be
+ *     supplied by the user, the protocol value is ignored:
+ *     - test_raw_sock_sendto_proto_wildcard
+ *     - test_raw_sock_sendmsg_proto_wildcard
+ *
+ *   * (AF_PACKET, SOCK_DGRAM, <protocol>) -  L2 header is constructed according
+ *     to protocol and `struct sockaddr_ll`:
+ *     - test_dgram_sock_sendto_proto_wildcard
+ *     - test_dgram_sock_sendto_proto_match
+ *     - test_dgram_sock_sendmsg_proto_wildcard
+ *     - test_dgram_sock_sendmsg_proto_match
+ *
+ * Receiving data (RX)
+ *
+ *   * (AF_PACKET, SOCK_RAW, 0) - The packet is dropped when received by this socket.
+ *     See https://man7.org/linux/man-pages/man7/packet.7.html:
+ *     - test_raw_sock_recv_no_proto
+ *
+ *   * (AF_PACKET, SOCK_DGRAM, 0) - The packet is dropped when received by this socket.
+ *     See https://man7.org/linux/man-pages/man7/packet.7.html
+ *     - test_dgram_sock_recv_no_proto
+ *
+ *   * (AF_PACKET, SOCK_RAW, <protocol>) - The packet is received for a given protocol
+ *     only. The L2 header is not removed from the data:
+ *     - NOT SUPPORTED
+ *
+ *   * (AF_PACKET, SOCK_DGRAM, <protocol>) - The packet is received for a given protocol
+ *     only. The L2 header is removed from the data:
+ *     - test_dgram_sock_recv_proto_match
+ *     - test_dgram_sock_recv_proto_mismatch
+ *
+ *   * (AF_PACKET, SOCK_RAW, htons(ETH_P_ALL)) - The packet is received for all protocols.
+ *     The L2 header is not removed from the data:
+ *     - test_raw_sock_recv_proto_wildcard
+ *     - test_raw_sock_recvfrom_proto_wildcard
+ *
+ *   * (AF_PACKET, SOCK_DGRAM, htons(ETH_P_ALL)) - The packet is received for all protocols.
+ *     The L2 header is removed from the data:
+ *     - test_dgram_sock_recv_proto_wildcard
+ *     - test_dgram_sock_recvfrom_proto_wildcard
+ */
 
 #if defined(CONFIG_NET_SOCKETS_LOG_LEVEL_DBG)
 #define DBG(fmt, ...) NET_DBG(fmt, ##__VA_ARGS__)
@@ -21,7 +86,18 @@ LOG_MODULE_REGISTER(net_test, CONFIG_NET_SOCKETS_LOG_LEVEL);
 #define DBG(fmt, ...)
 #endif
 
-#define IPV4_ADDR "127.0.0.1"
+#define IPV4_ADDR "192.0.2.1"
+
+static int packet_sock_1 = -1;
+static int packet_sock_2 = -1;
+static int packet_sock_3 = -1;
+static int udp_sock_1 = -1;
+static int udp_sock_2 = -1;
+
+static const uint8_t test_payload[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 };
+static uint8_t rx_buf[64];
+static uint8_t tx_buf[64];
+static struct in_addr fake_src = { { { 192, 0, 2, 2 } } };
 
 static uint8_t lladdr1[] = { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01 };
 static uint8_t lladdr2[] = { 0x02, 0x02, 0x02, 0x02, 0x02, 0x02 };
@@ -103,36 +179,51 @@ ETH_NET_DEVICE_INIT(eth_fake2, "eth_fake2", NULL, NULL, &eth_fake_data2, NULL,
 		    CONFIG_ETH_INIT_PRIORITY, &eth_fake_api_funcs,
 		    NET_ETH_MTU);
 
-static int setup_socket(struct net_if *iface, int type, int proto)
+static void setup_packet_socket(int *sock, struct net_if *iface, int type,
+				int proto)
 {
-	int sock;
+	struct timeval optval = {
+		.tv_usec = 100000,
+	};
+	int ret;
 
-	sock = zsock_socket(AF_PACKET, type, proto);
-	zassert_true(sock >= 0, "Cannot create packet socket (%d)", -errno);
+	*sock = zsock_socket(AF_PACKET, type, proto);
+	zassert_true(*sock >= 0, "Cannot create packet socket (%d)", -errno);
 
-	return sock;
+	ret = zsock_setsockopt(*sock, SOL_SOCKET, SO_RCVTIMEO, &optval,
+			       sizeof(optval));
+	zassert_ok(ret, "setsockopt failed (%d)", errno);
 }
 
-static int bind_socket(int sock, struct net_if *iface)
+static void bind_packet_socket(int sock, struct net_if *iface)
 {
 	struct sockaddr_ll addr;
+	int ret;
 
 	memset(&addr, 0, sizeof(addr));
 
 	addr.sll_ifindex = net_if_get_by_iface(iface);
 	addr.sll_family = AF_PACKET;
 
-	return zsock_bind(sock, (struct sockaddr *)&addr, sizeof(addr));
+	ret = zsock_bind(sock, (struct sockaddr *)&addr, sizeof(addr));
+	zassert_ok(ret, "Cannot bind packet socket (%d)", -errno);
+}
+
+static void prepare_packet_socket(int *sock, struct net_if *iface, int type,
+				  int proto)
+{
+	setup_packet_socket(sock, iface, type, proto);
+	bind_packet_socket(*sock, iface);
 }
 
 struct user_data {
 	struct net_if *first;
 	struct net_if *second;
-};
+} ud;
 
 static void iface_cb(struct net_if *iface, void *user_data)
 {
-	struct user_data *ud = user_data;
+	struct user_data *test_data = user_data;
 	struct net_linkaddr *link_addr;
 
 	if (net_if_l2(iface) != &NET_L2_GET_NAME(ETHERNET)) {
@@ -145,39 +236,25 @@ static void iface_cb(struct net_if *iface, void *user_data)
 		return;
 	}
 
-	if (ud->first == NULL) {
-		ud->first = iface;
+	if (test_data->first == NULL) {
+		test_data->first = iface;
 		return;
 	}
 
-	ud->second = iface;
-}
-
-static void setblocking(int fd, bool val)
-{
-	int fl, res;
-
-	fl = zsock_fcntl(fd, F_GETFL, 0);
-	zassert_not_equal(fl, -1, "Fail to set fcntl");
-
-	if (val) {
-		fl &= ~O_NONBLOCK;
-	} else {
-		fl |= O_NONBLOCK;
-	}
-
-	res = zsock_fcntl(fd, F_SETFL, fl);
-	zassert_not_equal(res, -1, "Fail to set fcntl");
+	test_data->second = iface;
 }
 
 #define SRC_PORT 4240
 #define DST_PORT 4242
-static int prepare_udp_socket(struct sockaddr_in *sockaddr, uint16_t local_port)
+static void prepare_udp_socket(int *sock, struct sockaddr_in *sockaddr, uint16_t local_port)
 {
-	int sock, ret;
+	struct timeval optval = {
+		.tv_usec = 100000,
+	};
+	int ret;
 
-	sock = zsock_socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP);
-	zassert_true(sock >= 0, "Cannot create DGRAM (UDP) socket (%d)", sock);
+	*sock = zsock_socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP);
+	zassert_true(*sock >= 0, "Cannot create DGRAM (UDP) socket (%d)", sock);
 
 	sockaddr->sin_family = AF_INET;
 	sockaddr->sin_port = htons(local_port);
@@ -185,55 +262,35 @@ static int prepare_udp_socket(struct sockaddr_in *sockaddr, uint16_t local_port)
 	zassert_equal(ret, 1, "inet_pton failed");
 
 	/* Bind UDP socket to local port */
-	ret = zsock_bind(sock, (struct sockaddr *) sockaddr, sizeof(*sockaddr));
+	ret = zsock_bind(*sock, (struct sockaddr *) sockaddr, sizeof(*sockaddr));
 	zassert_equal(ret, 0, "Cannot bind DGRAM (UDP) socket (%d)", -errno);
 
-	return sock;
-}
-
-static void __test_packet_sockets(int *sock1, int *sock2)
-{
-	struct user_data ud = { 0 };
-	int ret;
-
-	net_if_foreach(iface_cb, &ud);
-
-	zassert_not_null(ud.first, "1st Ethernet interface not found");
-	zassert_not_null(ud.second, "2nd Ethernet interface not found");
-
-	*sock1 = setup_socket(ud.first, SOCK_RAW, htons(ETH_P_ALL));
-	zassert_true(*sock1 >= 0, "Cannot create 1st socket (%d)", *sock1);
-
-	*sock2 = setup_socket(ud.second, SOCK_RAW, htons(ETH_P_ALL));
-	zassert_true(*sock2 >= 0, "Cannot create 2nd socket (%d)", *sock2);
-
-	ret = bind_socket(*sock1, ud.first);
-	zassert_equal(ret, 0, "Cannot bind 1st socket (%d)", -errno);
-
-	ret = bind_socket(*sock2, ud.second);
-	zassert_equal(ret, 0, "Cannot bind 2nd socket (%d)", -errno);
+	ret = zsock_setsockopt(*sock, SOL_SOCKET, SO_RCVTIMEO, &optval,
+			       sizeof(optval));
+	zassert_ok(ret, "setsockopt failed (%d)", errno);
 }
 
 #define IP_HDR_SIZE 20
 #define UDP_HDR_SIZE 8
 #define HDR_SIZE (IP_HDR_SIZE + UDP_HDR_SIZE)
-ZTEST(socket_packet, test_raw_packet_sockets)
+ZTEST(socket_packet, test_raw_packet_sockets_udp_send)
 {
 	uint8_t data_to_send[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19 };
 	uint8_t data_to_receive[sizeof(data_to_send) + HDR_SIZE];
 	struct sockaddr_ll src;
 	struct sockaddr_in sockaddr;
-	int ret, sock1, sock2, sock3, sock4;
+	int ret;
 	socklen_t addrlen;
 	ssize_t sent = 0;
 
-	__test_packet_sockets(&sock1, &sock2);
+	prepare_packet_socket(&packet_sock_1, ud.first, SOCK_RAW, htons(ETH_P_ALL));
+	prepare_packet_socket(&packet_sock_2, ud.second, SOCK_RAW, htons(ETH_P_ALL));
 
 	/* Prepare UDP socket which will read data */
-	sock3 = prepare_udp_socket(&sockaddr, DST_PORT);
+	prepare_udp_socket(&udp_sock_1, &sockaddr, DST_PORT);
 
 	/* Prepare UDP socket from which data are going to be sent */
-	sock4 = prepare_udp_socket(&sockaddr, SRC_PORT);
+	prepare_udp_socket(&udp_sock_2, &sockaddr, SRC_PORT);
 	/* Properly set destination port for UDP packet */
 	sockaddr.sin_port = htons(DST_PORT);
 
@@ -241,19 +298,16 @@ ZTEST(socket_packet, test_raw_packet_sockets)
 	 * Send UDP datagram to us - as check_ip_addr() in net_send_data()
 	 * returns 1 - the packet is processed immediately in the net stack
 	 */
-	sent = zsock_sendto(sock4, data_to_send, sizeof(data_to_send),
+	sent = zsock_sendto(udp_sock_2, data_to_send, sizeof(data_to_send),
 			    0, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
 	zassert_equal(sent, sizeof(data_to_send), "sendto failed");
 
-	k_msleep(10); /* Let the packet enter the system */
-
-	setblocking(sock3, false);
 	memset(&data_to_receive, 0, sizeof(data_to_receive));
 	errno = 0;
 
 	/* Check if UDP packets can be read after being sent */
 	addrlen = sizeof(sockaddr);
-	ret = zsock_recvfrom(sock3, data_to_receive, sizeof(data_to_receive),
+	ret = zsock_recvfrom(udp_sock_1, data_to_receive, sizeof(data_to_receive),
 			     0, (struct sockaddr *)&sockaddr, &addrlen);
 	zassert_equal(ret, sizeof(data_to_send), "Cannot receive all data (%d)",
 		      -errno);
@@ -261,7 +315,6 @@ ZTEST(socket_packet, test_raw_packet_sockets)
 			  "Sent and received buffers do not match");
 
 	/* And if the packet has been also passed to RAW socket */
-	setblocking(sock1, false);
 	memset(&data_to_receive, 0, sizeof(data_to_receive));
 	memset(&src, 0, sizeof(src));
 	addrlen = sizeof(src);
@@ -271,7 +324,7 @@ ZTEST(socket_packet, test_raw_packet_sockets)
 	 * IP (20B) and UDP (8) headers. After those we can expect payload,
 	 * which have been sent.
 	 */
-	ret = zsock_recvfrom(sock1, data_to_receive, sizeof(data_to_receive), 0,
+	ret = zsock_recvfrom(packet_sock_1, data_to_receive, sizeof(data_to_receive), 0,
 			     (struct sockaddr *)&src, &addrlen);
 	zassert_equal(ret, sizeof(data_to_send) + HDR_SIZE,
 		      "Cannot receive all data (%d vs %zd) (%d)",
@@ -279,80 +332,62 @@ ZTEST(socket_packet, test_raw_packet_sockets)
 	zassert_mem_equal(&data_to_receive[HDR_SIZE], data_to_send,
 			  sizeof(data_to_send),
 			  "Sent and received buffers do not match");
-
-	zsock_close(sock1);
-	zsock_close(sock2);
-	zsock_close(sock3);
-	zsock_close(sock4);
 }
 
 ZTEST(socket_packet, test_packet_sockets)
 {
-	int sock1, sock2;
-
-	__test_packet_sockets(&sock1, &sock2);
-
-	zsock_close(sock1);
-	zsock_close(sock2);
+	prepare_packet_socket(&packet_sock_1, ud.first, SOCK_RAW, htons(ETH_P_ALL));
+	prepare_packet_socket(&packet_sock_2, ud.second, SOCK_RAW, htons(ETH_P_ALL));
 }
 
 ZTEST(socket_packet, test_packet_sockets_dgram)
 {
-	uint8_t data_to_send[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 };
-	uint8_t data_to_receive[32];
 	socklen_t addrlen = sizeof(struct sockaddr_ll);
-	struct user_data ud = { 0 };
 	struct sockaddr_ll dst, src;
-	int ret, sock1, sock2;
-	int iter, max_iter = 10;
-
-	net_if_foreach(iface_cb, &ud);
-
-	zassert_not_null(ud.first, "1st Ethernet interface not found");
-	zassert_not_null(ud.second, "2nd Ethernet interface not found");
-
-	sock1 = setup_socket(ud.first, SOCK_DGRAM, htons(ETH_P_TSN));
-	zassert_true(sock1 >= 0, "Cannot create 1st socket (%d)", sock1);
-
-	sock2 = setup_socket(ud.second, SOCK_DGRAM, htons(ETH_P_TSN));
-	zassert_true(sock2 >= 0, "Cannot create 2nd socket (%d)", sock2);
-
-	ret = bind_socket(sock1, ud.first);
-	zassert_equal(ret, 0, "Cannot bind 1st socket (%d)", -errno);
-
-	ret = bind_socket(sock2, ud.second);
-	zassert_equal(ret, 0, "Cannot bind 2nd socket (%d)", -errno);
+	int ret;
 
-	setblocking(sock1, false);
-	setblocking(sock2, false);
+	prepare_packet_socket(&packet_sock_1, ud.first, SOCK_DGRAM, htons(ETH_P_TSN));
+	prepare_packet_socket(&packet_sock_2, ud.second, SOCK_DGRAM, htons(ETH_P_TSN));
 
 	memset(&dst, 0, sizeof(dst));
 	dst.sll_family = AF_PACKET;
 	dst.sll_protocol = htons(ETH_P_TSN);
 	memcpy(dst.sll_addr, lladdr1, sizeof(lladdr1));
 
-	ret = zsock_sendto(sock2, data_to_send, sizeof(data_to_send), 0,
+	ret = zsock_sendto(packet_sock_2, test_payload, sizeof(test_payload), 0,
 			   (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll));
-	zassert_equal(ret, sizeof(data_to_send), "Cannot send all data (%d)",
+	zassert_equal(ret, sizeof(test_payload), "Cannot send all data (%d)",
 		      -errno);
 
-	k_msleep(10); /* Let the packet enter the system */
-	memset(&src, 0, sizeof(src));
+	ret = zsock_recvfrom(packet_sock_2, rx_buf, sizeof(rx_buf), 0,
+	(struct sockaddr *)&src, &addrlen);
+	zassert_equal(ret, -1, "Received something (%d)", ret);
+	zassert_equal(errno, EAGAIN, "Wrong errno (%d)", errno);
 
+	memset(&src, 0, sizeof(src));
 	errno = 0;
-	iter = 0;
-	do {
-		ret = zsock_recvfrom(sock1, data_to_receive, sizeof(data_to_receive),
-				     0, (struct sockaddr *)&src, &addrlen);
-		k_msleep(10);
-		iter++;
-	} while (ret < 0 && errno == EAGAIN && iter < max_iter);
-
-	zassert_equal(ret, sizeof(data_to_send),
+	ret = zsock_recvfrom(packet_sock_1, rx_buf, sizeof(rx_buf),
+			     0, (struct sockaddr *)&src, &addrlen);
+	zassert_equal(ret, sizeof(test_payload),
 		      "Cannot receive all data (%d vs %zd) (%d)",
-		      ret, sizeof(data_to_send), -errno);
+		      ret, sizeof(test_payload), -errno);
+
+	zassert_equal(addrlen, sizeof(struct sockaddr_ll),
+		      "Invalid address length (%d)", addrlen);
+
+	struct sockaddr_ll src_expected = {
+		.sll_family = AF_PACKET,
+		.sll_protocol = dst.sll_protocol,
+		.sll_ifindex = net_if_get_by_iface(ud.first),
+		.sll_pkttype = PACKET_OTHERHOST,
+		.sll_hatype = ARPHRD_ETHER,
+		.sll_halen = sizeof(lladdr2),
+		.sll_addr = {0},
+	};
+	memcpy(&src_expected.sll_addr, lladdr2, ARRAY_SIZE(lladdr2));
+	zassert_mem_equal(&src, &src_expected, addrlen, "Invalid source address");
 
-	zassert_mem_equal(data_to_send, data_to_receive, sizeof(data_to_send),
+	zassert_mem_equal(test_payload, rx_buf, sizeof(test_payload),
 			  "Data mismatch");
 
 	memcpy(dst.sll_addr, lladdr2, sizeof(lladdr2));
@@ -360,15 +395,14 @@ ZTEST(socket_packet, test_packet_sockets_dgram)
 	/* Send to socket 2 but read from socket 1. There should not be any
 	 * data in socket 1
 	 */
-	ret = zsock_sendto(sock2, data_to_send, sizeof(data_to_send), 0,
+	ret = zsock_sendto(packet_sock_2, test_payload, sizeof(test_payload), 0,
 			   (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll));
-	zassert_equal(ret, sizeof(data_to_send), "Cannot send all data (%d)",
+	zassert_equal(ret, sizeof(test_payload), "Cannot send all data (%d)",
 		      -errno);
 
-	k_msleep(10);
 	memset(&src, 0, sizeof(src));
 
-	ret = zsock_recvfrom(sock1, data_to_receive, sizeof(data_to_receive), 0,
+	ret = zsock_recvfrom(packet_sock_1, rx_buf, sizeof(rx_buf), 0,
 			     (struct sockaddr *)&src, &addrlen);
 	zassert_equal(ret, -1, "Received something (%d)", ret);
 	zassert_equal(errno, EAGAIN, "Wrong errno (%d)", errno);
@@ -376,32 +410,59 @@ ZTEST(socket_packet, test_packet_sockets_dgram)
 	memset(&src, 0, sizeof(src));
 
 	errno = 0;
-	iter = 0;
-	do {
-		ret = zsock_recvfrom(sock2, data_to_receive, sizeof(data_to_receive),
-				     0, (struct sockaddr *)&src, &addrlen);
-		k_msleep(10);
-		iter++;
-	} while (ret < 0 && errno == EAGAIN && iter < max_iter);
-
-	zassert_equal(ret, sizeof(data_to_send), "Cannot receive all data (%d)",
+	ret = zsock_recvfrom(packet_sock_2, rx_buf, sizeof(rx_buf),
+			     0, (struct sockaddr *)&src, &addrlen);
+	zassert_equal(ret, sizeof(test_payload), "Cannot receive all data (%d)",
 		      -errno);
-	zassert_mem_equal(data_to_send, data_to_receive, sizeof(data_to_send),
+	zassert_equal(addrlen, sizeof(struct sockaddr_ll),
+		      "Invalid address length (%d)", addrlen);
+
+	src_expected = (struct sockaddr_ll){
+		.sll_family = AF_PACKET,
+		.sll_protocol = dst.sll_protocol,
+		.sll_ifindex = net_if_get_by_iface(ud.second),
+		.sll_pkttype = PACKET_OTHERHOST,
+		.sll_hatype = ARPHRD_ETHER,
+		.sll_halen = ARRAY_SIZE(lladdr2),
+		.sll_addr = {0},
+	};
+	memcpy(&src_expected.sll_addr, lladdr2, ARRAY_SIZE(lladdr2));
+	zassert_mem_equal(&src, &src_expected, addrlen, "Invalid source address");
+
+	zassert_mem_equal(test_payload, rx_buf, sizeof(test_payload),
 			  "Data mismatch");
 
-	zsock_close(sock1);
-	zsock_close(sock2);
+	/* Send specially crafted payload to mimic IPv4 and IPv6 length field,
+	 * to ckeck correct length returned.
+	 */
+	uint8_t payload_ip_length[64], receive_ip_length[64];
+
+	memset(payload_ip_length, 0, sizeof(payload_ip_length));
+	/* Set ipv4 and ipv6 length fields to represent IP payload with the
+	 * length of 1 byte.
+	 */
+	payload_ip_length[3] = 21;
+	payload_ip_length[5] = 1;
+
+	ret = zsock_sendto(packet_sock_2, payload_ip_length, sizeof(payload_ip_length), 0,
+			   (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll));
+	zassert_equal(ret, sizeof(payload_ip_length), "Cannot send all data (%d)", -errno);
+
+	memset(&src, 0, sizeof(src));
+	errno = 0;
+	ret = zsock_recvfrom(packet_sock_2, receive_ip_length, sizeof(receive_ip_length), 0,
+			     (struct sockaddr *)&src, &addrlen);
+
+	zassert_equal(ret, ARRAY_SIZE(payload_ip_length), "Cannot receive all data (%d)", -errno);
+	zassert_mem_equal(payload_ip_length, receive_ip_length, sizeof(payload_ip_length),
+			  "Data mismatch");
 }
 
 ZTEST(socket_packet, test_raw_and_dgram_socket_exchange)
 {
-	uint8_t data_to_send[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 };
-	uint8_t data_to_receive[32];
 	socklen_t addrlen = sizeof(struct sockaddr_ll);
-	struct user_data ud = { 0 };
 	struct sockaddr_ll dst, src;
-	int ret, sock1, sock2;
-	int iter, max_iter = 10;
+	int ret;
 	const uint8_t expected_payload_raw[] = {
 		0x02, 0x02, 0x02, 0x02, 0x02, 0x02, /* Dst ll addr */
 		0x01, 0x01, 0x01, 0x01, 0x01, 0x01, /* Src ll addr */
@@ -415,26 +476,8 @@ ZTEST(socket_packet, test_raw_and_dgram_socket_exchange)
 		0, 1, 2, 3, 4, 5, 6, 7, 8, 9 /* Payload */
 	};
 
-
-	net_if_foreach(iface_cb, &ud);
-
-	zassert_not_null(ud.first, "1st Ethernet interface not found");
-	zassert_not_null(ud.second, "2nd Ethernet interface not found");
-
-	sock1 = setup_socket(ud.first, SOCK_DGRAM, htons(ETH_P_ALL));
-	zassert_true(sock1 >= 0, "Cannot create 1st socket (%d)", sock1);
-
-	sock2 = setup_socket(ud.second, SOCK_RAW, htons(ETH_P_ALL));
-	zassert_true(sock2 >= 0, "Cannot create 2nd socket (%d)", sock2);
-
-	ret = bind_socket(sock1, ud.first);
-	zassert_equal(ret, 0, "Cannot bind 1st socket (%d)", -errno);
-
-	ret = bind_socket(sock2, ud.second);
-	zassert_equal(ret, 0, "Cannot bind 2nd socket (%d)", -errno);
-
-	setblocking(sock1, false);
-	setblocking(sock2, false);
+	prepare_packet_socket(&packet_sock_1, ud.first, SOCK_DGRAM, htons(ETH_P_ALL));
+	prepare_packet_socket(&packet_sock_2, ud.second, SOCK_RAW, htons(ETH_P_ALL));
 
 	memset(&dst, 0, sizeof(dst));
 	dst.sll_family = AF_PACKET;
@@ -443,28 +486,21 @@ ZTEST(socket_packet, test_raw_and_dgram_socket_exchange)
 
 	/* SOCK_DGRAM to SOCK_RAW */
 
-	ret = zsock_sendto(sock1, data_to_send, sizeof(data_to_send), 0,
+	ret = zsock_sendto(packet_sock_1, test_payload, sizeof(test_payload), 0,
 			   (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll));
-	zassert_equal(ret, sizeof(data_to_send), "Cannot send all data (%d)",
+	zassert_equal(ret, sizeof(test_payload), "Cannot send all data (%d)",
 		      -errno);
 
 	k_msleep(10); /* Let the packet enter the system */
 	memset(&src, 0, sizeof(src));
 
 	errno = 0;
-	iter = 0;
-	do {
-		ret = zsock_recvfrom(sock2, data_to_receive, sizeof(data_to_receive),
-				     0, (struct sockaddr *)&src, &addrlen);
-		k_msleep(10);
-		iter++;
-	} while (ret < 0 && errno == EAGAIN && iter < max_iter);
-
+	ret = zsock_recvfrom(packet_sock_2, rx_buf, sizeof(rx_buf),
+			     0, (struct sockaddr *)&src, &addrlen);
 	zassert_equal(ret, sizeof(expected_payload_raw),
 		      "Cannot receive all data (%d vs %zd) (%d)",
 		      ret, sizeof(expected_payload_raw), -errno);
-
-	zassert_mem_equal(expected_payload_raw, data_to_receive,
+	zassert_mem_equal(expected_payload_raw, rx_buf,
 			  sizeof(expected_payload_raw), "Data mismatch");
 
 	memset(&dst, 0, sizeof(dst));
@@ -473,41 +509,27 @@ ZTEST(socket_packet, test_raw_and_dgram_socket_exchange)
 
 	/* SOCK_RAW to SOCK_DGRAM */
 
-	ret = zsock_sendto(sock2, send_payload_raw, sizeof(send_payload_raw), 0,
+	ret = zsock_sendto(packet_sock_2, send_payload_raw, sizeof(send_payload_raw), 0,
 			   (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll));
 	zassert_equal(ret, sizeof(send_payload_raw), "Cannot send all data (%d)",
 		      -errno);
 
-	k_msleep(10);
 	memset(&src, 0, sizeof(src));
 
 	errno = 0;
-	iter = 0;
-	do {
-		ret = zsock_recvfrom(sock1, data_to_receive, sizeof(data_to_receive),
-				     0, (struct sockaddr *)&src, &addrlen);
-		k_msleep(10);
-		iter++;
-	} while (ret < 0 && errno == EAGAIN && iter < max_iter);
-
-	zassert_equal(ret, sizeof(data_to_send), "Cannot receive all data (%d)",
+	ret = zsock_recvfrom(packet_sock_1, rx_buf, sizeof(rx_buf),
+			     0, (struct sockaddr *)&src, &addrlen);
+	zassert_equal(ret, sizeof(test_payload), "Cannot receive all data (%d)",
 		      -errno);
-	zassert_mem_equal(data_to_send, data_to_receive, sizeof(data_to_send),
+	zassert_mem_equal(test_payload, rx_buf, sizeof(test_payload),
 			  "Data mismatch");
-
-	zsock_close(sock1);
-	zsock_close(sock2);
 }
 
 ZTEST(socket_packet, test_raw_and_dgram_socket_recv)
 {
-	uint8_t data_to_send[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 };
-	uint8_t data_to_receive[32];
 	socklen_t addrlen = sizeof(struct sockaddr_ll);
-	struct user_data ud = { 0 };
 	struct sockaddr_ll dst, src;
-	int ret, sock1, sock2, sock3;
-	int iter, max_iter = 10;
+	int ret;
 	const uint8_t expected_payload_raw[] = {
 		0x02, 0x02, 0x02, 0x02, 0x02, 0x02, /* Dst ll addr */
 		0x01, 0x01, 0x01, 0x01, 0x01, 0x01, /* Src ll addr */
@@ -515,83 +537,497 @@ ZTEST(socket_packet, test_raw_and_dgram_socket_recv)
 		0, 1, 2, 3, 4, 5, 6, 7, 8, 9 /* Payload */
 	};
 
-	net_if_foreach(iface_cb, &ud);
-
-	zassert_not_null(ud.first, "1st Ethernet interface not found");
-	zassert_not_null(ud.second, "2nd Ethernet interface not found");
-
-	sock1 = setup_socket(ud.first, SOCK_DGRAM, htons(ETH_P_ALL));
-	zassert_true(sock1 >= 0, "Cannot create 1st socket (%d)", sock1);
-
-	sock2 = setup_socket(ud.second, SOCK_RAW, htons(ETH_P_ALL));
-	zassert_true(sock2 >= 0, "Cannot create 2nd socket (%d)", sock2);
-
-	sock3 = setup_socket(ud.second, SOCK_RAW, htons(ETH_P_ALL));
-	zassert_true(sock3 >= 0, "Cannot create 2nd socket (%d)", sock3);
-
-	ret = bind_socket(sock1, ud.first);
-	zassert_equal(ret, 0, "Cannot bind 1st socket (%d)", -errno);
-
-	ret = bind_socket(sock2, ud.second);
-	zassert_equal(ret, 0, "Cannot bind 2nd socket (%d)", -errno);
-
-	ret = bind_socket(sock3, ud.second);
-	zassert_equal(ret, 0, "Cannot bind 2nd socket (%d)", -errno);
-
-	setblocking(sock1, false);
-	setblocking(sock2, false);
-	setblocking(sock3, false);
+	prepare_packet_socket(&packet_sock_1, ud.first, SOCK_DGRAM, htons(ETH_P_ALL));
+	prepare_packet_socket(&packet_sock_2, ud.second, SOCK_RAW, htons(ETH_P_ALL));
+	prepare_packet_socket(&packet_sock_3, ud.second, SOCK_DGRAM, htons(ETH_P_ALL));
 
 	memset(&dst, 0, sizeof(dst));
 	dst.sll_family = AF_PACKET;
 	dst.sll_protocol = htons(ETH_P_IP);
 	memcpy(dst.sll_addr, lladdr2, sizeof(lladdr1));
 
-	ret = zsock_sendto(sock1, data_to_send, sizeof(data_to_send), 0,
+	ret = zsock_sendto(packet_sock_1, test_payload, sizeof(test_payload), 0,
 			   (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll));
-	zassert_equal(ret, sizeof(data_to_send), "Cannot send all data (%d)",
+	zassert_equal(ret, sizeof(test_payload), "Cannot send all data (%d)",
 		      -errno);
 
-	k_msleep(10); /* Let the packet enter the system */
 	memset(&src, 0, sizeof(src));
 
 	/* Both SOCK_DGRAM to SOCK_RAW sockets should receive packet. */
 
 	errno = 0;
-	iter = 0;
-	do {
-		ret = zsock_recvfrom(sock2, data_to_receive, sizeof(data_to_receive),
-				     0, (struct sockaddr *)&src, &addrlen);
-		k_msleep(10);
-		iter++;
-	} while (ret < 0 && errno == EAGAIN && iter < max_iter);
-
+	ret = zsock_recvfrom(packet_sock_2, rx_buf, sizeof(rx_buf),
+			     0, (struct sockaddr *)&src, &addrlen);
 	zassert_equal(ret, sizeof(expected_payload_raw),
 		      "Cannot receive all data (%d vs %zd) (%d)",
 		      ret, sizeof(expected_payload_raw), -errno);
 
-	zassert_mem_equal(expected_payload_raw, data_to_receive,
+	zassert_mem_equal(expected_payload_raw, rx_buf,
 			  sizeof(expected_payload_raw), "Data mismatch");
 
 	memset(&src, 0, sizeof(src));
 
 	errno = 0;
-	iter = 0;
-	do {
-		ret = zsock_recvfrom(sock3, data_to_receive, sizeof(data_to_receive),
-				     0, (struct sockaddr *)&src, &addrlen);
-		k_msleep(10);
-		iter++;
-	} while (ret < 0 && errno == EAGAIN && iter < max_iter);
-
-	zassert_equal(ret, sizeof(expected_payload_raw),
+	ret = zsock_recvfrom(packet_sock_3, rx_buf, sizeof(rx_buf),
+			     0, (struct sockaddr *)&src, &addrlen);
+	zassert_equal(ret, sizeof(test_payload),
 		      "Cannot receive all data (%d)", -errno);
-	zassert_mem_equal(expected_payload_raw, data_to_receive,
-			  sizeof(expected_payload_raw), "Data mismatch");
+	zassert_mem_equal(test_payload, rx_buf, sizeof(test_payload),
+			  "Data mismatch");
+}
+
+#define TEST_IPV4_CHKSUM 0xc3f6
+#define TEST_UDP_CHKSUM 0x8b46
+
+/* Prepare packet with optional IP/UDP headers and optional ethernet header.  */
+static void prepare_test_packet(int sock_type, uint16_t proto,
+				uint8_t *ll_src, uint8_t *ll_dst,
+				uint16_t *pkt_len)
+{
+	uint16_t offset = 0;
+
+	if (sock_type == SOCK_RAW) {
+		struct net_eth_hdr *eth = (struct net_eth_hdr *)tx_buf;
+
+		offset += sizeof(struct net_eth_hdr);
+		zassert_not_null(ll_src, "NULL LL src");
+		zassert_not_null(ll_dst, "NULL LL dst");
+		zassert_true(offset <= sizeof(tx_buf), "Packet too long");
+
+		memcpy(&eth->dst, ll_dst, sizeof(eth->dst));
+		memcpy(&eth->src, ll_src, sizeof(eth->src));
+		eth->type = htons(proto);
+	}
+
+	if (proto == ETH_P_IP) {
+		struct in_addr addr;
+		struct net_ipv4_hdr *ipv4 =
+			(struct net_ipv4_hdr *)(tx_buf + offset);
+		struct net_udp_hdr *udp =
+			(struct net_udp_hdr *)(tx_buf + offset + NET_IPV4H_LEN);
+
+		offset += NET_IPV4UDPH_LEN;
+		zassert_true(offset <= sizeof(tx_buf), "Packet too long");
+		zassert_ok(net_addr_pton(AF_INET, IPV4_ADDR, &addr),
+			   "Addres parse failed");
+
+		/* Prepare IPv4 header */
+		ipv4->vhl = 0x45;
+		ipv4->len = htons(sizeof(test_payload) + NET_IPV4UDPH_LEN);
+		ipv4->ttl = 64;
+		ipv4->proto = IPPROTO_UDP;
+		ipv4->chksum = TEST_IPV4_CHKSUM;
+		memcpy(ipv4->src, &fake_src, sizeof(ipv4->src));
+		memcpy(ipv4->dst, &addr, sizeof(ipv4->dst));
+
+		/* Prepare UDP header */
+		udp->src_port = htons(SRC_PORT);
+		udp->dst_port = htons(DST_PORT);
+		udp->len = htons(sizeof(test_payload) + NET_UDPH_LEN);
+		udp->chksum = TEST_UDP_CHKSUM;
+	}
+
+	zassert_true(offset + sizeof(test_payload) <= sizeof(tx_buf), "Packet too long");
+	memcpy(tx_buf + offset, test_payload, sizeof(test_payload));
+
+	offset += sizeof(test_payload);
+	*pkt_len = offset;
+}
+
+static void prepare_test_dst_lladdr(struct sockaddr_ll *ll_dst, uint16_t proto,
+				    uint8_t *ll_addr, struct net_if *iface)
+{
+	memset(ll_dst, 0, sizeof(struct sockaddr_ll));
+
+	ll_dst->sll_family = AF_PACKET;
+	ll_dst->sll_protocol = htons(proto);
+	memcpy(ll_dst->sll_addr, ll_addr, NET_ETH_ADDR_LEN);
+
+	if (iface != NULL) {
+		ll_dst->sll_ifindex = net_if_get_by_iface(iface);
+	}
+}
+
+static void test_sendto_common(int sock_type, int proto, bool do_bind,
+			       int custom_dst_iface, bool set_dst_addr,
+			       bool success)
+{
+	struct sockaddr_in ip_src;
+	struct sockaddr_ll ll_dst;
+	uint16_t pkt_len;
+	int ret;
+
+	setup_packet_socket(&packet_sock_1, ud.second, sock_type, htons(proto));
+	if (do_bind) {
+		bind_packet_socket(packet_sock_1, ud.second);
+	}
+	prepare_udp_socket(&udp_sock_1, &ip_src, DST_PORT);
+	prepare_test_packet(sock_type, ETH_P_IP, lladdr2, lladdr1, &pkt_len);
+	prepare_test_dst_lladdr(&ll_dst, ETH_P_IP, lladdr1, ud.second);
+	if (custom_dst_iface != 0) {
+		ll_dst.sll_ifindex = custom_dst_iface;
+	}
+
+	ret = zsock_sendto(packet_sock_1, tx_buf, pkt_len, 0,
+			   set_dst_addr ? (struct sockaddr *)&ll_dst : NULL,
+			   set_dst_addr ? sizeof(struct sockaddr_ll) : 0);
+	if (success) {
+		zassert_not_equal(ret, -1, "Failed to send (%d)", errno);
+		zassert_equal(ret, pkt_len, "Invalid data length sent (%d/%d)", ret, pkt_len);
+
+		ret = zsock_recv(udp_sock_1, rx_buf, sizeof(rx_buf), 0);
+		zassert_not_equal(ret, -1, "Failed to receive UDP packet (%d)", errno);
+		zassert_equal(ret, sizeof(test_payload),
+			     "Invalid data size received (%d, expected %d)",
+			      ret, sizeof(test_payload));
+		zassert_mem_equal(rx_buf, test_payload, sizeof(test_payload),
+				  "Invalid payload received");
+	} else {
+		zassert_equal(ret, -1, "Send should fail");
+		zassert_equal(errno, EDESTADDRREQ, "Wrong errno");
+	}
+}
+
+ZTEST(socket_packet, test_raw_sock_sendto_no_proto_bound)
+{
+	test_sendto_common(SOCK_RAW, 0, true, 0, true, true);
+}
+
+ZTEST(socket_packet, test_raw_sock_sendto_no_proto_unbound)
+{
+	test_sendto_common(SOCK_RAW, 0, false, 0, true, true);
+}
+
+ZTEST(socket_packet, test_raw_sock_sendto_no_proto_unbound_no_iface)
+{
+	test_sendto_common(SOCK_RAW, 0, false, 10, true, false);
+}
+
+ZTEST(socket_packet, test_raw_sock_sendto_no_proto_unbound_no_addr)
+{
+	test_sendto_common(SOCK_RAW, 0, false, 0, false, false);
+}
+
+static void test_sendmsg_common(int sock_type, int proto)
+{
+	struct sockaddr_in ip_src;
+	struct sockaddr_ll ll_dst;
+	struct iovec io_vector;
+	struct msghdr msg = { 0 };
+	uint16_t pkt_len;
+	int ret;
+
+	setup_packet_socket(&packet_sock_1, ud.second, sock_type, htons(proto));
+	prepare_udp_socket(&udp_sock_1, &ip_src, DST_PORT);
+	prepare_test_packet(sock_type, ETH_P_IP, lladdr2, lladdr1, &pkt_len);
+	prepare_test_dst_lladdr(&ll_dst, ETH_P_IP, lladdr1, ud.second);
+
+	io_vector.iov_base = tx_buf;
+	io_vector.iov_len = pkt_len;
+	msg.msg_iov = &io_vector;
+	msg.msg_iovlen = 1;
+	msg.msg_name = &ll_dst;
+	msg.msg_namelen = sizeof(ll_dst);
+
+	ret = zsock_sendmsg(packet_sock_1, &msg, 0);
+	zassert_not_equal(ret, -1, "Failed to send (%d)", errno);
+	zassert_equal(ret, pkt_len, "Invalid data length sent (%d/%d)", ret, pkt_len);
+
+	ret = zsock_recv(udp_sock_1, rx_buf, sizeof(rx_buf), 0);
+	zassert_not_equal(ret, -1, "Failed to receive UDP packet (%d)", errno);
+	zassert_equal(ret, sizeof(test_payload),
+		      "Invalid data size received (%d, expected %d)",
+		      ret, sizeof(test_payload));
+	zassert_mem_equal(rx_buf, test_payload, sizeof(test_payload),
+			  "Invalid payload received");
+}
+
+ZTEST(socket_packet, test_raw_sock_sendmsg_no_proto)
+{
+	test_sendmsg_common(SOCK_RAW, 0);
+}
+
+ZTEST(socket_packet, test_dgram_sock_sendto_no_proto_bound)
+{
+	test_sendto_common(SOCK_DGRAM, 0, true, 0, true, true);
+}
+
+ZTEST(socket_packet, test_dgram_sock_sendto_no_proto_unbound)
+{
+	test_sendto_common(SOCK_DGRAM, 0, false, 0, true, true);
+}
+
+ZTEST(socket_packet, test_dgram_sock_sendto_no_proto_unbound_no_iface)
+{
+	test_sendto_common(SOCK_DGRAM, 0, false, 10, true, false);
+}
+
+ZTEST(socket_packet, test_dgram_sock_sendto_no_proto_unbound_no_addr)
+{
+	test_sendto_common(SOCK_DGRAM, 0, false, 0, false, false);
+}
+
+ZTEST(socket_packet, test_dgram_sock_sendmsg_no_proto)
+{
+	test_sendmsg_common(SOCK_DGRAM, 0);
+}
+
+ZTEST(socket_packet, test_raw_sock_sendto_proto_wildcard)
+{
+	test_sendto_common(SOCK_RAW, ETH_P_ALL, true, 0, true, true);
+}
+
+ZTEST(socket_packet, test_raw_sock_sendmsg_proto_wildcard)
+{
+	test_sendmsg_common(SOCK_RAW, ETH_P_ALL);
+}
+
+ZTEST(socket_packet, test_dgram_sock_sendto_proto_wildcard)
+{
+	test_sendto_common(SOCK_DGRAM, ETH_P_ALL, true, 0, true, true);
+}
+
+ZTEST(socket_packet, test_dgram_sock_sendto_proto_match)
+{
+	test_sendto_common(SOCK_DGRAM, ETH_P_IP, true, 0, true, true);
+}
+
+ZTEST(socket_packet, test_dgram_sock_sendmsg_proto_wildcard)
+{
+	test_sendmsg_common(SOCK_DGRAM, ETH_P_ALL);
+}
+
+ZTEST(socket_packet, test_dgram_sock_sendmsg_proto_match)
+{
+	test_sendmsg_common(SOCK_DGRAM, ETH_P_IP);
+}
+
+static void test_recv_common(int sock_type, int proto, bool success)
+{
+	struct sockaddr_ll ll_dst;
+	uint16_t offset = 0;
+	uint16_t pkt_len;
+	int ret;
+
+	/* Transmitting sock */
+	setup_packet_socket(&packet_sock_1, ud.second, SOCK_RAW, 0);
+	prepare_test_packet(SOCK_RAW, ETH_P_IP, lladdr2, lladdr1, &pkt_len);
+	prepare_test_dst_lladdr(&ll_dst, ETH_P_IP, lladdr1, ud.second);
+	/* Receiving sock */
+	setup_packet_socket(&packet_sock_2, ud.first, sock_type, htons(proto));
+	bind_packet_socket(packet_sock_2, ud.first);
+
+	ret = zsock_sendto(packet_sock_1, tx_buf, pkt_len, 0,
+			   (struct sockaddr *)&ll_dst,
+			   sizeof(struct sockaddr_ll));
+	zassert_not_equal(ret, -1, "Failed to send (%d)", errno);
+	zassert_equal(ret, pkt_len, "Invalid data length sent (%d/%d)", ret, pkt_len);
+
+	if (sock_type == SOCK_DGRAM) {
+		offset = sizeof(struct net_eth_hdr);
+		pkt_len -= sizeof(struct net_eth_hdr);
+	}
+
+	ret = zsock_recv(packet_sock_2, rx_buf, sizeof(rx_buf), 0);
+	if (success) {
+		zassert_not_equal(ret, -1, "Failed to receive packet (%d)", errno);
+		zassert_equal(ret, pkt_len,
+			     "Invalid data size received (%d, expected %d)",
+			      ret, pkt_len);
+		zassert_mem_equal(rx_buf, tx_buf + offset, pkt_len,
+				  "Invalid payload received");
+	} else {
+		zassert_equal(ret, -1, "Recv should fail");
+		zassert_equal(errno, EAGAIN, "Wrong errno");
+	}
+}
+
+ZTEST(socket_packet, test_raw_sock_recv_no_proto)
+{
+	test_recv_common(SOCK_RAW, 0, false);
+}
+
+ZTEST(socket_packet, test_dgram_sock_recv_no_proto)
+{
+	test_recv_common(SOCK_DGRAM, 0, false);
+}
+
+ZTEST(socket_packet, test_dgram_sock_recv_proto_match)
+{
+	test_recv_common(SOCK_DGRAM, ETH_P_IP, true);
+}
+
+ZTEST(socket_packet, test_dgram_sock_recv_proto_mismatch)
+{
+	test_recv_common(SOCK_DGRAM, ETH_P_IPV6, false);
+}
+
+ZTEST(socket_packet, test_raw_sock_recv_proto_wildcard)
+{
+	test_recv_common(SOCK_RAW, ETH_P_ALL, true);
+}
+
+static void test_recvfrom_common(int sock_type, int proto)
+{
+	struct sockaddr_ll ll_dst;
+	struct sockaddr_ll ll_rx = { 0 };
+	socklen_t addrlen = sizeof(ll_rx);
+	uint16_t pkt_len;
+	uint16_t offset = 0;
+	int ret;
+
+	/* Transmitting sock */
+	setup_packet_socket(&packet_sock_1, ud.second, SOCK_RAW, 0);
+	prepare_test_packet(SOCK_RAW, ETH_P_IP, lladdr2, lladdr1, &pkt_len);
+	prepare_test_dst_lladdr(&ll_dst, ETH_P_IP, lladdr1, ud.second);
+	/* Receiving sock */
+	setup_packet_socket(&packet_sock_2, ud.first, sock_type, htons(proto));
+	bind_packet_socket(packet_sock_2, ud.first);
+
+	ret = zsock_sendto(packet_sock_1, tx_buf, pkt_len, 0,
+			   (struct sockaddr *)&ll_dst,
+			   sizeof(struct sockaddr_ll));
+	zassert_not_equal(ret, -1, "Failed to send (%d)", errno);
+	zassert_equal(ret, pkt_len, "Invalid data length sent (%d/%d)", ret, pkt_len);
+
+	if (sock_type == SOCK_DGRAM) {
+		offset = sizeof(struct net_eth_hdr);
+	}
+
+	ret = zsock_recvfrom(packet_sock_2, rx_buf, sizeof(rx_buf), 0,
+			     (struct sockaddr *)&ll_rx, &addrlen);
+	zassert_not_equal(ret, -1, "Failed to receive packet (%d)", errno);
+	zassert_equal(ret, pkt_len,
+		      "Invalid data size received (%d, expected %d)",
+		      ret, pkt_len);
+	zassert_mem_equal(rx_buf, tx_buf + offset, pkt_len,
+			  "Invalid payload received");
+	zassert_equal(addrlen, sizeof(struct sockaddr_ll),
+		      "Invalid address length (%u)", addrlen);
+	zassert_equal(ll_rx.sll_family, AF_PACKET, "Invalid family");
+	zassert_equal(ll_rx.sll_protocol, htons(ETH_P_IP), "Invalid protocol");
+	zassert_equal(ll_rx.sll_ifindex, net_if_get_by_iface(ud.first),
+		      "Invalid interface");
+	zassert_equal(ll_rx.sll_hatype, ARPHRD_ETHER, "Invalid hardware type");
+	zassert_equal(ll_rx.sll_pkttype, PACKET_OTHERHOST, "Invalid packet type");
+	zassert_equal(ll_rx.sll_halen, NET_ETH_ADDR_LEN, "Invalid address length");
+	zassert_mem_equal(ll_rx.sll_addr, &lladdr2, NET_ETH_ADDR_LEN,
+			  "Invalid address");
+}
+
+ZTEST(socket_packet, test_raw_sock_recvfrom_proto_wildcard)
+{
+	test_recvfrom_common(SOCK_RAW, ETH_P_ALL);
+}
+
+ZTEST(socket_packet, test_dgram_sock_recv_proto_wildcard)
+{
+	test_recv_common(SOCK_DGRAM, ETH_P_ALL, true);
+}
+
+ZTEST(socket_packet, test_dgram_sock_recvfrom_proto_wildcard)
+{
+	test_recvfrom_common(SOCK_RAW, ETH_P_ALL);
+}
+
+ZTEST(socket_packet, test_raw_dgram_udp_socks_recv)
+{
+	struct sockaddr_in ip_src;
+	struct sockaddr_ll ll_dst;
+	uint8_t offset = 0;
+	uint16_t pkt_len;
+	int ret;
+
+	/* Transmitting sock */
+	setup_packet_socket(&packet_sock_1, ud.second, SOCK_RAW, 0);
+	prepare_test_packet(SOCK_RAW, ETH_P_IP, lladdr2, lladdr1, &pkt_len);
+	prepare_test_dst_lladdr(&ll_dst, ETH_P_IP, lladdr1, ud.second);
+	/* Receiving sockets */
+	setup_packet_socket(&packet_sock_2, ud.first, SOCK_RAW, htons(ETH_P_ALL));
+	bind_packet_socket(packet_sock_2, ud.first);
+	setup_packet_socket(&packet_sock_3, ud.first, SOCK_DGRAM, htons(ETH_P_ALL));
+	bind_packet_socket(packet_sock_3, ud.first);
+	prepare_udp_socket(&udp_sock_1, &ip_src, DST_PORT);
+
+	ret = zsock_sendto(packet_sock_1, tx_buf, pkt_len, 0,
+			   (struct sockaddr *)&ll_dst,
+			   sizeof(struct sockaddr_ll));
+	zassert_not_equal(ret, -1, "Failed to send (%d)", errno);
+	zassert_equal(ret, pkt_len, "Invalid data length sent (%d/%d)", ret, pkt_len);
+
+	/* All 3 sockets should get their packets */
+	ret = zsock_recv(packet_sock_2, rx_buf, sizeof(rx_buf), 0);
+	zassert_not_equal(ret, -1, "Failed to receive RAW packet (%d)", errno);
+	zassert_equal(ret, pkt_len, "Invalid data size received (%d, expected %d)",
+		      ret, pkt_len);
+	zassert_mem_equal(rx_buf, tx_buf, pkt_len, "Invalid payload received");
+
+	offset += sizeof(struct net_eth_hdr);
+	pkt_len -= sizeof(struct net_eth_hdr);
+
+	ret = zsock_recv(packet_sock_3, rx_buf, sizeof(rx_buf), 0);
+	zassert_not_equal(ret, -1, "Failed to receive DGRAM packet (%d)", errno);
+	zassert_equal(ret, pkt_len, "Invalid data size received (%d, expected %d)",
+		      ret, pkt_len);
+	zassert_mem_equal(rx_buf, tx_buf + offset, pkt_len, "Invalid payload received");
+
+	offset += NET_IPV4UDPH_LEN;
+	pkt_len -= NET_IPV4UDPH_LEN;
+
+	ret = zsock_recv(udp_sock_1, rx_buf, sizeof(rx_buf), 0);
+	zassert_not_equal(ret, -1, "Failed to receive UDP packet (%d)", errno);
+	zassert_equal(ret, pkt_len,
+		      "Invalid data size received (%d, expected %d)",
+		      ret, pkt_len);
+	zassert_mem_equal(rx_buf, tx_buf + offset, pkt_len, "Invalid payload received");
+}
+
+static void test_sockets_close(void)
+{
+	if (packet_sock_1 >= 0) {
+		(void)zsock_close(packet_sock_1);
+		packet_sock_1 = -1;
+	}
+
+	if (packet_sock_2 >= 0) {
+		(void)zsock_close(packet_sock_2);
+		packet_sock_2 = -1;
+	}
+
+	if (packet_sock_3 >= 0) {
+		(void)zsock_close(packet_sock_3);
+		packet_sock_3 = -1;
+	}
+
+	if (udp_sock_1 >= 0) {
+		(void)zsock_close(udp_sock_1);
+		udp_sock_1 = -1;
+	}
+
+	if (udp_sock_2 >= 0) {
+		(void)zsock_close(udp_sock_2);
+		udp_sock_2 = -1;
+	}
+}
+
+static void test_after(void *arg)
+{
+	ARG_UNUSED(arg);
+
+	memset(&rx_buf, 0, sizeof(rx_buf));
+	memset(&tx_buf, 0, sizeof(tx_buf));
+
+	test_sockets_close();
+}
+
+static void *test_setup(void)
+{
+	net_if_foreach(iface_cb, &ud);
+
+	zassert_not_null(ud.first, "1st Ethernet interface not found");
+	zassert_not_null(ud.second, "2nd Ethernet interface not found");
 
-	zsock_close(sock1);
-	zsock_close(sock2);
-	zsock_close(sock3);
+	return NULL;
 }
 
-ZTEST_SUITE(socket_packet, NULL, NULL, NULL, NULL, NULL);
+ZTEST_SUITE(socket_packet, NULL, test_setup, NULL, test_after, NULL);
diff --git a/tests/net/socket/af_packet/testcase.yaml b/tests/net/socket/af_packet/testcase.yaml
index 963047cf322..04efce5160f 100644
--- a/tests/net/socket/af_packet/testcase.yaml
+++ b/tests/net/socket/af_packet/testcase.yaml
@@ -4,11 +4,6 @@ common:
     - net
     - socket
     - af_packet
-  # The test do not work in native_posix as the zeth interface creation
-  # needs root permission.
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   net.socket.af_packet:
     min_ram: 21
diff --git a/tests/net/socket/af_packet_ipproto_raw/CMakeLists.txt b/tests/net/socket/af_packet_ipproto_raw/CMakeLists.txt
deleted file mode 100644
index 6eefd55dd75..00000000000
--- a/tests/net/socket/af_packet_ipproto_raw/CMakeLists.txt
+++ /dev/null
@@ -1,9 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-cmake_minimum_required(VERSION 3.20.0)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(socket_packet_ipproto_raw)
-
-target_include_directories(app PRIVATE ${ZEPHYR_BASE}/subsys/net/ip)
-FILE(GLOB app_sources src/*.c)
-target_sources(app PRIVATE ${app_sources})
diff --git a/tests/net/socket/af_packet_ipproto_raw/prj.conf b/tests/net/socket/af_packet_ipproto_raw/prj.conf
deleted file mode 100644
index 227851d398f..00000000000
--- a/tests/net/socket/af_packet_ipproto_raw/prj.conf
+++ /dev/null
@@ -1,25 +0,0 @@
-# Networking config
-CONFIG_NETWORKING=y
-CONFIG_NET_IPV4=y
-CONFIG_NET_IPV6=n
-CONFIG_NET_UDP=n
-CONFIG_NET_TCP=n
-CONFIG_NET_SOCKETS=y
-CONFIG_NET_SOCKETS_PACKET=y
-CONFIG_ZVFS_OPEN_MAX=8
-CONFIG_NET_SOCKETS_LOG_LEVEL_DBG=y
-CONFIG_NET_CORE_LOG_LEVEL_DBG=y
-
-# Network driver config
-CONFIG_NET_L2_ETHERNET=y
-CONFIG_TEST_RANDOM_GENERATOR=y
-
-CONFIG_NET_L2_DUMMY=y
-CONFIG_NET_IF_MAX_IPV4_COUNT=4
-
-CONFIG_ZTEST=y
-CONFIG_NET_TEST=y
-CONFIG_NET_LOG=y
-CONFIG_TEST_USERSPACE=y
-CONFIG_NET_MAX_CONTEXTS=8
-CONFIG_NET_MAX_CONN=8
diff --git a/tests/net/socket/af_packet_ipproto_raw/src/main.c b/tests/net/socket/af_packet_ipproto_raw/src/main.c
deleted file mode 100644
index 4eb28edb70f..00000000000
--- a/tests/net/socket/af_packet_ipproto_raw/src/main.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * Copyright (c) 2021 Nordic Semiconductor ASA
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/logging/log.h>
-LOG_MODULE_REGISTER(net_test, CONFIG_NET_SOCKETS_LOG_LEVEL);
-
-#include <zephyr/kernel.h>
-#include <zephyr/linker/sections.h>
-#include <zephyr/ztest.h>
-#include <zephyr/random/random.h>
-
-#include <zephyr/posix/fcntl.h>
-
-#include <zephyr/net/ethernet.h>
-#include <zephyr/net/dummy.h>
-#include <zephyr/net/net_if.h>
-#include <zephyr/net/socket.h>
-
-struct fake_dev_context {
-	uint8_t mac_addr[sizeof(struct net_eth_addr)];
-	struct net_if *iface;
-};
-
-static const char testing_data[] = "Tappara";
-
-static int fake_dev_send(const struct device *dev, struct net_pkt *pkt)
-{
-	struct net_pkt *recv_pkt;
-	int ret;
-
-	ARG_UNUSED(dev);
-	ARG_UNUSED(pkt);
-
-	/* Loopback the data back to stack: */
-	NET_DBG("Dummy device: Loopbacking data (%zd bytes) to iface %d\n", net_pkt_get_len(pkt),
-	    net_if_get_by_iface(net_pkt_iface(pkt)));
-
-	recv_pkt = net_pkt_clone(pkt, K_NO_WAIT);
-
-	k_sleep(K_MSEC(10)); /* Let the receiver run */
-
-	ret = net_recv_data(net_pkt_iface(recv_pkt), recv_pkt);
-	zassert_equal(ret, 0, "Cannot receive data (%d)", ret);
-	return 0;
-}
-
-static uint8_t *fake_dev_get_mac(struct fake_dev_context *ctx)
-{
-	if (ctx->mac_addr[2] == 0x00) {
-		/* 00-00-5E-00-53-xx Documentation RFC 7042 */
-		ctx->mac_addr[0] = 0x00;
-		ctx->mac_addr[1] = 0x00;
-		ctx->mac_addr[2] = 0x5E;
-		ctx->mac_addr[3] = 0x00;
-		ctx->mac_addr[4] = 0x53;
-		ctx->mac_addr[5] = sys_rand8_get();
-	}
-
-	return ctx->mac_addr;
-}
-
-static void fake_dev_iface_init(struct net_if *iface)
-{
-	const struct device *dev = net_if_get_device(iface);
-	struct fake_dev_context *ctx = dev->data;
-	uint8_t *mac = fake_dev_get_mac(ctx);
-
-	net_if_set_link_addr(iface, mac, 6, NET_LINK_ETHERNET);
-
-	ctx->iface = iface;
-}
-
-int fake_dev_init(const struct device *dev)
-{
-	ARG_UNUSED(dev);
-
-	return 0;
-}
-
-struct fake_dev_context fake_dev_context_data;
-
-static struct dummy_api fake_dev_if_api = {
-	.iface_api.init = fake_dev_iface_init,
-	.send = fake_dev_send,
-};
-
-#define _ETH_L2_LAYER DUMMY_L2
-#define _ETH_L2_CTX_TYPE NET_L2_GET_CTX_TYPE(DUMMY_L2)
-
-NET_DEVICE_INIT(fake_dev, "fake_dev", fake_dev_init, NULL, &fake_dev_context_data, NULL,
-		CONFIG_KERNEL_INIT_PRIORITY_DEFAULT, &fake_dev_if_api, _ETH_L2_LAYER,
-		_ETH_L2_CTX_TYPE, 127);
-
-static void *test_setup(void)
-{
-	struct net_if *iface;
-	struct in_addr in4addr_my = { { { 192, 168, 0, 2 } } };
-	struct net_if_addr *ifaddr;
-
-	iface = net_if_get_first_by_type(&NET_L2_GET_NAME(DUMMY));
-	zassert_not_null(iface, "Could not get dummy iface");
-
-	net_if_up(iface);
-
-	ifaddr = net_if_ipv4_addr_add(iface, &in4addr_my, NET_ADDR_MANUAL, 0);
-	zassert_not_null(ifaddr, "Could not add iface address");
-
-	return NULL;
-}
-
-ZTEST(net_sckt_packet_raw_ip, test_sckt_raw_packet_raw_ip)
-{
-	/* A test case for testing socket combo: AF_PACKET & SOCK_RAW & IPPROTO_RAW: */
-	struct net_if *iface = net_if_get_first_by_type(&NET_L2_GET_NAME(DUMMY));
-	int recv_data_len, ret;
-	struct sockaddr_ll dst = { 0 };
-	char receive_buffer[128];
-	int sock;
-
-	sock = zsock_socket(AF_PACKET, SOCK_RAW, htons(IPPROTO_RAW));
-	zassert_true(sock >= 0, "Could not create a socket");
-
-	dst.sll_ifindex = net_if_get_by_iface(iface);
-	dst.sll_family = AF_PACKET;
-
-	ret = zsock_bind(sock, (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll));
-	zassert_true(ret >= 0, "Could not bind the socket");
-
-	/* Let's send some data: */
-	ret = zsock_sendto(sock, testing_data, ARRAY_SIZE(testing_data), 0,
-			   (const struct sockaddr *)&dst, sizeof(struct sockaddr_ll));
-	zassert_true(ret > 0, "Could not send data");
-
-	/* Receive the same data back: */
-	recv_data_len = zsock_recv(sock, receive_buffer, sizeof(receive_buffer), 0);
-	zassert_true(recv_data_len == ARRAY_SIZE(testing_data), "Expected data not received");
-
-	NET_DBG("Received successfully data %s", receive_buffer);
-
-	zsock_close(sock);
-}
-
-ZTEST_SUITE(net_sckt_packet_raw_ip, NULL, test_setup, NULL, NULL, NULL);
diff --git a/tests/net/socket/af_packet_ipproto_raw/testcase.yaml b/tests/net/socket/af_packet_ipproto_raw/testcase.yaml
deleted file mode 100644
index 503f52deadc..00000000000
--- a/tests/net/socket/af_packet_ipproto_raw/testcase.yaml
+++ /dev/null
@@ -1,14 +0,0 @@
-common:
-  depends_on: netif
-  tags:
-    - net
-    - socket
-    - af_packet
-  # The test do not work in native_posix as the zeth interface creation
-  # needs root permission.
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
-tests:
-  net.socket.af_packet.ipproto_raw:
-    min_ram: 21
diff --git a/tests/net/socket/getaddrinfo/testcase.yaml b/tests/net/socket/getaddrinfo/testcase.yaml
index 14822401179..3d7bb633703 100644
--- a/tests/net/socket/getaddrinfo/testcase.yaml
+++ b/tests/net/socket/getaddrinfo/testcase.yaml
@@ -6,9 +6,6 @@ common:
     - socket
     - getaddrinfo
     - userspace
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   net.socket.get_addr_info:
     min_ram: 21
diff --git a/tests/net/socket/getnameinfo/testcase.yaml b/tests/net/socket/getnameinfo/testcase.yaml
index 2e60ca44fe0..9edc6b2502e 100644
--- a/tests/net/socket/getnameinfo/testcase.yaml
+++ b/tests/net/socket/getnameinfo/testcase.yaml
@@ -1,9 +1,6 @@
 common:
   depends_on: netif
   filter: CONFIG_FULL_LIBC_SUPPORTED
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
 tests:
   net.socket.get_name_info:
     min_ram: 21
diff --git a/tests/net/socket/misc/src/main.c b/tests/net/socket/misc/src/main.c
index 941e72c32bf..dd22cc79a32 100644
--- a/tests/net/socket/misc/src/main.c
+++ b/tests/net/socket/misc/src/main.c
@@ -51,6 +51,36 @@ ZTEST_USER(socket_misc_test_suite, test_inet_pton)
 
 	res = zsock_inet_pton(AF_INET6, "a:b:c:d:0:1:2:3z", buf);
 	zassert_equal(res, 0, "");
+
+	res = zsock_inet_pton(AF_INET, "192.0.2.400", buf);
+	zassert_equal(res, 0, "");
+
+	res = zsock_inet_pton(AF_INET, "0.0", buf);
+	zassert_equal(res, 0, "");
+
+	res = zsock_inet_pton(AF_INET, "0.1", buf);
+	zassert_equal(res, 0, "");
+
+	res = zsock_inet_pton(AF_INET, "0", buf);
+	zassert_equal(res, 0, "");
+
+	res = zsock_inet_pton(AF_INET, "1", buf);
+	zassert_equal(res, 0, "");
+
+	res = zsock_inet_pton(AF_INET, "256", buf);
+	zassert_equal(res, 0, "");
+
+	res = zsock_inet_pton(AF_INET, "00.0.0.0", buf);
+	zassert_equal(res, 0, "");
+
+	res = zsock_inet_pton(AF_INET, "0.0.0.0", buf);
+	zassert_equal(res, 1, "");
+
+	res = zsock_inet_pton(AF_INET, "0.0..0", buf);
+	zassert_equal(res, 0, "");
+
+	res = zsock_inet_pton(AF_INET, "1.2.3.0.", buf);
+	zassert_equal(res, 0, "");
 }
 
 #define TEST_MY_IPV4_ADDR "192.0.1.1"
diff --git a/tests/net/socket/poll/testcase.yaml b/tests/net/socket/poll/testcase.yaml
index 9d08909605e..e86c5bcca51 100644
--- a/tests/net/socket/poll/testcase.yaml
+++ b/tests/net/socket/poll/testcase.yaml
@@ -1,12 +1,5 @@
 common:
   depends_on: netif
-  # FIXME: This test fails very frequently on mps2/an385 due to the system
-  #        timer stability issues, so keep it disabled until the root cause
-  #        is fixed (GitHub issue zephyrproject-rtos/zephyr#48608).
-  platform_exclude:
-    - mps2/an385
-    - native_posix/native/64
-    - native_posix
 tests:
   net.socket.poll:
     min_ram: 21
diff --git a/tests/net/socket/reuseaddr_reuseport/testcase.yaml b/tests/net/socket/reuseaddr_reuseport/testcase.yaml
index fcfce0b1e49..60219826fc1 100644
--- a/tests/net/socket/reuseaddr_reuseport/testcase.yaml
+++ b/tests/net/socket/reuseaddr_reuseport/testcase.yaml
@@ -5,10 +5,6 @@ common:
   tags:
     - net
     - socket
-  # FIXME: This test fails very frequently on mps2/an385 due to the system
-  #        timer stability issues, so keep it disabled until the root cause
-  #        is fixed (GitHub issue zephyrproject-rtos/zephyr#48608).
-  platform_exclude: mps2/an385
 tests:
   net.socket.reuseaddr_reuseport:
     extra_configs:
diff --git a/tests/net/socket/select/testcase.yaml b/tests/net/socket/select/testcase.yaml
index 320cfbaa3ec..716c578b40a 100644
--- a/tests/net/socket/select/testcase.yaml
+++ b/tests/net/socket/select/testcase.yaml
@@ -6,10 +6,6 @@ common:
     - socket
     - userspace
   filter: CONFIG_FULL_LIBC_SUPPORTED
-  # FIXME: This test fails very frequently on mps2/an385 due to the system
-  #        timer stability issues, so keep it disabled until the root cause
-  #        is fixed (GitHub issue zephyrproject-rtos/zephyr#48608).
-  platform_exclude: mps2/an385
 tests:
   net.socket.select:
     extra_configs:
diff --git a/tests/net/socket/service/testcase.yaml b/tests/net/socket/service/testcase.yaml
index 0db82aea218..15d5706b68b 100644
--- a/tests/net/socket/service/testcase.yaml
+++ b/tests/net/socket/service/testcase.yaml
@@ -1,13 +1,5 @@
 common:
   depends_on: netif
-  # FIXME: This test fails very frequently on mps2/an385 due to the system
-  #        timer stability issues, so keep it disabled until the root cause
-  #        is fixed (GitHub issue zephyrproject-rtos/zephyr#48608).
-  # eventfd API does not work with native_posix so exclude it here
-  platform_exclude:
-    - mps2/an385
-    - native_posix
-    - native_posix/native/64
 tests:
   net.socket.service:
     min_ram: 21
diff --git a/tests/net/socket/socketpair/testcase.yaml b/tests/net/socket/socketpair/testcase.yaml
index 133f2801b95..c7525a82f36 100644
--- a/tests/net/socket/socketpair/testcase.yaml
+++ b/tests/net/socket/socketpair/testcase.yaml
@@ -6,8 +6,6 @@ common:
   depends_on: netif
   min_ram: 21
   platform_exclude:
-    - native_posix/native/64
-    - native_posix
     # See #61246 for info about these next two excludes
     - vmu_rt1170/mimxrt1176/cm7
     - mimxrt1160_evk/mimxrt1166/cm7
diff --git a/tests/net/socket/tcp/src/main.c b/tests/net/socket/tcp/src/main.c
index 643e8b5de0c..f46a0be1527 100644
--- a/tests/net/socket/tcp/src/main.c
+++ b/tests/net/socket/tcp/src/main.c
@@ -357,8 +357,8 @@ void tcp_server_block_thread(void *vps_sock, void *unused2, void *unused3)
 void test_send_recv_large_common(int tcp_nodelay, int family)
 {
 	int rv;
-	int c_sock;
-	int s_sock;
+	int c_sock = 0;
+	int s_sock = 0;
 	struct sockaddr *c_saddr = NULL;
 	struct sockaddr *s_saddr = NULL;
 	size_t addrlen = 0;
@@ -756,10 +756,12 @@ ZTEST_USER(net_socket_tcp, test_v4_sendto_recvmsg)
 	msg.msg_name = &addr;
 	msg.msg_namelen = addrlen;
 
-	test_recvmsg(new_sock, &msg, ZSOCK_MSG_PEEK, strlen(TEST_STR_SMALL),
-		     __LINE__);
-	zassert_mem_equal(buf, TEST_STR_SMALL, strlen(TEST_STR_SMALL),
-			  "wrong data (%s)", buf);
+	len = strlen(TEST_STR_SMALL);
+	test_recvmsg(new_sock, &msg, ZSOCK_MSG_PEEK, len, __LINE__);
+	zassert_equal(msg.msg_iovlen, 1, "recvmsg should not modify msg_iovlen");
+	zassert_equal(msg.msg_iov[0].iov_len, sizeof(buf),
+		      "recvmsg should not modify buffer length");
+	zassert_mem_equal(buf, TEST_STR_SMALL, len, "wrong data (%s)", buf);
 
 	/* Then in two chunks */
 	io_vector[0].iov_base = buf2;
@@ -773,12 +775,18 @@ ZTEST_USER(net_socket_tcp, test_v4_sendto_recvmsg)
 	msg.msg_name = &addr;
 	msg.msg_namelen = addrlen;
 
-	test_recvmsg(new_sock, &msg, 0, strlen(TEST_STR_SMALL), __LINE__);
+	len = strlen(TEST_STR_SMALL);
+	test_recvmsg(new_sock, &msg, 0, len, __LINE__);
+	zassert_equal(msg.msg_iovlen, 2, "recvmsg should not modify msg_iovlen");
+	zassert_equal(msg.msg_iov[0].iov_len, sizeof(buf2),
+		      "recvmsg should not modify buffer length");
+	zassert_equal(msg.msg_iov[1].iov_len, sizeof(buf),
+		      "recvmsg should not modify buffer length");
 	zassert_mem_equal(msg.msg_iov[0].iov_base, TEST_STR_SMALL, msg.msg_iov[0].iov_len,
 			  "wrong data in %s", "iov[0]");
+	len -= msg.msg_iov[0].iov_len;
 	zassert_mem_equal(msg.msg_iov[1].iov_base, &TEST_STR_SMALL[msg.msg_iov[0].iov_len],
-			  msg.msg_iov[1].iov_len,
-			  "wrong data in %s", "iov[1]");
+			  len, "wrong data in %s", "iov[1]");
 
 	/* Send larger test buffer */
 	test_sendto(c_sock, TEST_STR_LONG, strlen(TEST_STR_LONG), 0,
@@ -803,6 +811,13 @@ ZTEST_USER(net_socket_tcp, test_v4_sendto_recvmsg)
 	}
 
 	test_recvmsg(new_sock, &msg, 0, len, __LINE__);
+	zassert_equal(msg.msg_iovlen, 3, "recvmsg should not modify msg_iovlen");
+	zassert_equal(msg.msg_iov[0].iov_len, sizeof(buf),
+		      "recvmsg should not modify buffer length");
+	zassert_equal(msg.msg_iov[1].iov_len, sizeof(buf2),
+		      "recvmsg should not modify buffer length");
+	zassert_equal(msg.msg_iov[2].iov_len, sizeof(buf3),
+		      "recvmsg should not modify buffer length");
 	zassert_mem_equal(msg.msg_iov[0].iov_base, TEST_STR_LONG, msg.msg_iov[0].iov_len,
 			  "wrong data in %s", "iov[0]");
 	zassert_mem_equal(msg.msg_iov[1].iov_base, &TEST_STR_LONG[msg.msg_iov[0].iov_len],
diff --git a/tests/net/socket/tcp/testcase.yaml b/tests/net/socket/tcp/testcase.yaml
index a7593ffcdd3..be0cd94ba78 100644
--- a/tests/net/socket/tcp/testcase.yaml
+++ b/tests/net/socket/tcp/testcase.yaml
@@ -8,10 +8,6 @@ common:
     - userspace
   filter: CONFIG_FULL_LIBC_SUPPORTED
   timeout: 180
-  # FIXME: This test fails very frequently on mps2/an385 due to the system
-  #        timer stability issues, so keep it disabled until the root cause
-  #        is fixed (GitHub issue zephyrproject-rtos/zephyr#48608).
-  platform_exclude: mps2/an385
 tests:
   net.socket.tcp:
     extra_configs:
diff --git a/tests/net/socket/tls/src/main.c b/tests/net/socket/tls/src/main.c
index f532060f8f5..d9a11037eea 100644
--- a/tests/net/socket/tls/src/main.c
+++ b/tests/net/socket/tls/src/main.c
@@ -916,7 +916,7 @@ ZTEST(net_socket_tls, test_connect_closed_port)
 	zassert_equal(zsock_connect(c_sock, (struct sockaddr *)&s_saddr,
 				    sizeof(s_saddr)),
 		      -1, "connect succeed");
-	zassert_equal(errno, ETIMEDOUT,
+	zassert_equal(errno, ECONNREFUSED,
 		      "connect should fail, got %d", errno);
 
 	test_sockets_close();
diff --git a/tests/net/socket/tls_configurations/overlay-rsa.conf b/tests/net/socket/tls_configurations/overlay-rsa.conf
index c8fc3e29b10..bd6d33cd678 100644
--- a/tests/net/socket/tls_configurations/overlay-rsa.conf
+++ b/tests/net/socket/tls_configurations/overlay-rsa.conf
@@ -1,3 +1,8 @@
+CONFIG_MBEDTLS_MD=y
+CONFIG_MBEDTLS_RSA_C=y
+CONFIG_MBEDTLS_PKCS1_V15=y
+CONFIG_MBEDTLS_PKCS1_V21=y
+
 CONFIG_PSA_WANT_ALG_RSA_OAEP=y
 CONFIG_PSA_WANT_ALG_RSA_PKCS1V15_CRYPT=y
 CONFIG_PSA_WANT_ALG_RSA_PKCS1V15_SIGN=y
diff --git a/tests/net/socket/tls_configurations/prj.conf b/tests/net/socket/tls_configurations/prj.conf
index 23842f6a641..78fdf8ddd8b 100644
--- a/tests/net/socket/tls_configurations/prj.conf
+++ b/tests/net/socket/tls_configurations/prj.conf
@@ -11,7 +11,7 @@ CONFIG_NET_SOCKETS=y
 CONFIG_NET_SOCKETS_SOCKOPT_TLS=y
 
 # Disable native ethernet driver (using native sockets instead)
-CONFIG_ETH_NATIVE_POSIX=n
+CONFIG_ETH_NATIVE_TAP=n
 
 # Use native sockets
 CONFIG_NET_SOCKETS=y
@@ -36,7 +36,8 @@ CONFIG_ENTROPY_GENERATOR=y
 # have a basic configuration in this "prj.conf" file and then add algorithm
 # support in overlay files.
 CONFIG_MBEDTLS_TLS_VERSION_1_2=n
-CONFIG_MBEDTLS_KEY_EXCHANGE_RSA_ENABLED=n
+CONFIG_MBEDTLS_MD=n
+CONFIG_MBEDTLS_RSA_C=n
 CONFIG_MBEDTLS_CIPHER_AES_ENABLED=n
 CONFIG_PSA_WANT_KEY_TYPE_AES=n
 CONFIG_PSA_WANT_ALG_CBC_NO_PADDING=n
diff --git a/tests/net/socket/tls_ext/prj.conf b/tests/net/socket/tls_ext/prj.conf
index 02b53191a58..632b717f178 100644
--- a/tests/net/socket/tls_ext/prj.conf
+++ b/tests/net/socket/tls_ext/prj.conf
@@ -12,6 +12,7 @@ CONFIG_NET_LOOPBACK=y
 CONFIG_NET_IPV4=y
 CONFIG_NET_TCP=y
 CONFIG_NET_SOCKETS=y
+CONFIG_NET_TCP_TIME_WAIT_DELAY=0
 
 # Logging / Debugging options
 CONFIG_NET_LOG=y
diff --git a/tests/net/socket/tls_ext/src/main.c b/tests/net/socket/tls_ext/src/main.c
index c85df170b4e..cc55c2b3684 100644
--- a/tests/net/socket/tls_ext/src/main.c
+++ b/tests/net/socket/tls_ext/src/main.c
@@ -399,6 +399,8 @@ static void test_common(int peer_verify)
 
 	r = k_thread_join(&server_thread, K_FOREVER);
 	zassert_equal(0, r, "k_thread_join() failed (%d)", r);
+
+	k_yield();
 }
 
 ZTEST(net_socket_tls_api_extension, test_tls_peer_verify_none)
diff --git a/tests/net/socket/udp/src/main.c b/tests/net/socket/udp/src/main.c
index ac06590c71c..91e57747c52 100644
--- a/tests/net/socket/udp/src/main.c
+++ b/tests/net/socket/udp/src/main.c
@@ -950,11 +950,9 @@ static struct in6_addr my_addr3 = { { { 0x20, 0x01, 0x0d, 0xb8, 1, 0, 0, 0,
 static struct in6_addr my_mcast_addr1 = { { { 0xff, 0x01, 0, 0, 0, 0, 0, 0,
 					0, 0, 0, 0, 0, 0, 0, 0x1 } } };
 static struct in_addr my_mcast_addr2 = { { { 224, 0, 0, 2 } } };
-static uint8_t server_lladdr[] = { 0x01, 0x02, 0x03, 0xff, 0xfe,
-				0x04, 0x05, 0x06 };
 static struct net_linkaddr server_link_addr = {
-	.addr = server_lladdr,
-	.len = sizeof(server_lladdr),
+	.addr = { 0x01, 0x02, 0x03, 0x04, 0x05, 0x06 },
+	.len = NET_ETH_ADDR_LEN,
 };
 #define MY_IPV6_ADDR_ETH   "2001:db8:100::1"
 #define PEER_IPV6_ADDR_ETH "2001:db8:100::2"
@@ -1508,13 +1506,14 @@ static void comm_sendmsg_recvmsg(int client_sock,
 	/* Test recvmsg(MSG_PEEK) */
 	recved = zsock_recvmsg(server_sock, msg, ZSOCK_MSG_PEEK);
 	zassert_true(recved > 0, "recvmsg fail, %s (%d)", strerror(errno), -errno);
-	zassert_equal(recved, strlen(TEST_STR_SMALL),
-		      "unexpected received bytes (%d vs %d)",
-		      recved, strlen(TEST_STR_SMALL));
+	zassert_equal(recved, len, "unexpected received bytes (%d vs %d)",
+		      recved, len);
 	zassert_equal(sent, recved, "sent(%d)/received(%d) mismatch",
 		      sent, recved);
-
-	zassert_mem_equal(buf, TEST_STR_SMALL, strlen(TEST_STR_SMALL),
+	zassert_equal(msg->msg_iovlen, 1, "recvmsg should not modify msg_iovlen");
+	zassert_equal(msg->msg_iov[0].iov_len, sizeof(buf),
+		      "recvmsg should not modify buffer length");
+	zassert_mem_equal(buf, TEST_STR_SMALL, len,
 			  "wrong data (%s)", rx_buf);
 	zassert_equal(addrlen, client_addrlen, "unexpected addrlen");
 
@@ -1522,9 +1521,11 @@ static void comm_sendmsg_recvmsg(int client_sock,
 	clear_buf(rx_buf);
 	recved = zsock_recvmsg(server_sock, msg, 0);
 	zassert_true(recved > 0, "recvfrom fail");
-	zassert_equal(recved, strlen(TEST_STR_SMALL),
-		      "unexpected received bytes");
-	zassert_mem_equal(buf, TEST_STR_SMALL, strlen(TEST_STR_SMALL),
+	zassert_equal(recved, len, "unexpected received bytes");
+	zassert_equal(msg->msg_iovlen, 1, "recvmsg should not modify msg_iovlen");
+	zassert_equal(msg->msg_iov[0].iov_len, sizeof(buf),
+		      "recvmsg should not modify buffer length");
+	zassert_mem_equal(buf, TEST_STR_SMALL, len,
 			  "wrong data (%s)", rx_buf);
 	zassert_equal(addrlen, client_addrlen, "unexpected addrlen");
 
@@ -1582,30 +1583,40 @@ static void comm_sendmsg_recvmsg(int client_sock,
 	/* Test recvmsg(MSG_PEEK) */
 	recved = zsock_recvmsg(server_sock, msg, ZSOCK_MSG_PEEK);
 	zassert_true(recved >= 0, "recvfrom fail (errno %d)", errno);
-	zassert_equal(recved, strlen(TEST_STR_SMALL),
-		      "unexpected received bytes (%d vs %d)", recved, strlen(TEST_STR_SMALL));
+	zassert_equal(recved, len,
+		      "unexpected received bytes (%d vs %d)", recved, len);
 	zassert_equal(sent, recved, "sent(%d)/received(%d) mismatch",
 		      sent, recved);
 
+	zassert_equal(msg->msg_iovlen, 2, "recvmsg should not modify msg_iovlen");
+	zassert_equal(msg->msg_iov[0].iov_len, sizeof(buf2),
+		      "recvmsg should not modify buffer length");
+	zassert_equal(msg->msg_iov[1].iov_len, sizeof(buf),
+		      "recvmsg should not modify buffer length");
 	zassert_mem_equal(msg->msg_iov[0].iov_base, TEST_STR_SMALL, msg->msg_iov[0].iov_len,
 			  "wrong data in %s", "iov[0]");
 	zassert_mem_equal(msg->msg_iov[1].iov_base, &TEST_STR_SMALL[msg->msg_iov[0].iov_len],
-			  msg->msg_iov[1].iov_len,
+			  len - msg->msg_iov[0].iov_len,
 			  "wrong data in %s", "iov[1]");
 	zassert_equal(addrlen, client_addrlen, "unexpected addrlen");
 
 	/* Test normal recvfrom() */
 	recved = zsock_recvmsg(server_sock, msg, ZSOCK_MSG_PEEK);
 	zassert_true(recved >= 0, "recvfrom fail (errno %d)", errno);
-	zassert_equal(recved, strlen(TEST_STR_SMALL),
-		      "unexpected received bytes (%d vs %d)", recved, strlen(TEST_STR_SMALL));
+	zassert_equal(recved, len,
+		      "unexpected received bytes (%d vs %d)", recved, len);
 	zassert_equal(sent, recved, "sent(%d)/received(%d) mismatch",
 		      sent, recved);
 
+	zassert_equal(msg->msg_iovlen, 2, "recvmsg should not modify msg_iovlen");
+	zassert_equal(msg->msg_iov[0].iov_len, sizeof(buf2),
+		      "recvmsg should not modify buffer length");
+	zassert_equal(msg->msg_iov[1].iov_len, sizeof(buf),
+		      "recvmsg should not modify buffer length");
 	zassert_mem_equal(msg->msg_iov[0].iov_base, TEST_STR_SMALL, msg->msg_iov[0].iov_len,
 			  "wrong data in %s", "iov[0]");
 	zassert_mem_equal(msg->msg_iov[1].iov_base, &TEST_STR_SMALL[msg->msg_iov[0].iov_len],
-			  msg->msg_iov[1].iov_len,
+			  len - msg->msg_iov[0].iov_len,
 			  "wrong data in %s", "iov[1]");
 	zassert_equal(addrlen, client_addrlen, "unexpected addrlen");
 
@@ -1647,6 +1658,9 @@ static void comm_sendmsg_recvmsg(int client_sock,
 		      recved, sizeof(buf2));
 	zassert_true(msg->msg_flags & ZSOCK_MSG_TRUNC, "Message not truncated");
 
+	zassert_equal(msg->msg_iovlen, 1, "recvmsg should not modify msg_iovlen");
+	zassert_equal(msg->msg_iov[0].iov_len, sizeof(buf2),
+		      "recvmsg should not modify buffer length");
 	zassert_mem_equal(buf2, TEST_STR_SMALL, sizeof(buf2),
 			  "wrong data (%s)", buf2);
 	zassert_equal(addrlen, client_addrlen, "unexpected addrlen");
diff --git a/tests/net/traffic_class/src/main.c b/tests/net/traffic_class/src/main.c
index 3ef933e8e23..7cb75e0ccec 100644
--- a/tests/net/traffic_class/src/main.c
+++ b/tests/net/traffic_class/src/main.c
@@ -345,19 +345,17 @@ static void priority_setup(void)
 #if defined(CONFIG_NET_IPV6_NBR_CACHE)
 static bool add_neighbor(struct net_if *iface, struct in6_addr *addr)
 {
-	struct net_linkaddr_storage llstorage;
 	struct net_linkaddr lladdr;
 	struct net_nbr *nbr;
 
-	llstorage.addr[0] = 0x01;
-	llstorage.addr[1] = 0x02;
-	llstorage.addr[2] = 0x33;
-	llstorage.addr[3] = 0x44;
-	llstorage.addr[4] = 0x05;
-	llstorage.addr[5] = 0x06;
+	lladdr.addr[0] = 0x01;
+	lladdr.addr[1] = 0x02;
+	lladdr.addr[2] = 0x33;
+	lladdr.addr[3] = 0x44;
+	lladdr.addr[4] = 0x05;
+	lladdr.addr[5] = 0x06;
 
 	lladdr.len = 6U;
-	lladdr.addr = llstorage.addr;
 	lladdr.type = NET_LINK_ETHERNET;
 
 	nbr = net_ipv6_nbr_add(iface, addr, &lladdr, false,
diff --git a/tests/net/tx_timestamp/src/main.c b/tests/net/tx_timestamp/src/main.c
index 05e670ec4ce..91a6556b41e 100644
--- a/tests/net/tx_timestamp/src/main.c
+++ b/tests/net/tx_timestamp/src/main.c
@@ -399,19 +399,17 @@ void test_address_setup(void)
 
 static bool add_neighbor(struct net_if *iface, struct in6_addr *addr)
 {
-	struct net_linkaddr_storage llstorage;
 	struct net_linkaddr lladdr;
 	struct net_nbr *nbr;
 
-	llstorage.addr[0] = 0x01;
-	llstorage.addr[1] = 0x02;
-	llstorage.addr[2] = 0x33;
-	llstorage.addr[3] = 0x44;
-	llstorage.addr[4] = 0x05;
-	llstorage.addr[5] = 0x06;
+	lladdr.addr[0] = 0x01;
+	lladdr.addr[1] = 0x02;
+	lladdr.addr[2] = 0x33;
+	lladdr.addr[3] = 0x44;
+	lladdr.addr[4] = 0x05;
+	lladdr.addr[5] = 0x06;
 
 	lladdr.len = 6U;
-	lladdr.addr = llstorage.addr;
 	lladdr.type = NET_LINK_ETHERNET;
 
 	nbr = net_ipv6_nbr_add(iface, addr, &lladdr, false,
diff --git a/tests/net/udp/src/main.c b/tests/net/udp/src/main.c
index f06ee2edc77..e3dfa9d7f68 100644
--- a/tests/net/udp/src/main.c
+++ b/tests/net/udp/src/main.c
@@ -109,24 +109,6 @@ static int tester_send(const struct device *dev, struct net_pkt *pkt)
 	return 0;
 }
 
-static inline struct in_addr *if_get_addr(struct net_if *iface)
-{
-	int i;
-
-	for (i = 0; i < NET_IF_MAX_IPV4_ADDR; i++) {
-		if (iface->config.ip.ipv4->unicast[i].ipv4.is_used &&
-		    iface->config.ip.ipv4->unicast[i].ipv4.address.family ==
-								AF_INET &&
-		    iface->config.ip.ipv4->unicast[i].ipv4.addr_state ==
-							NET_ADDR_PREFERRED) {
-			return
-			    &iface->config.ip.ipv4->unicast[i].ipv4.address.in_addr;
-		}
-	}
-
-	return NULL;
-}
-
 struct net_udp_context net_udp_context_data;
 
 static struct dummy_api net_udp_if_api = {
diff --git a/tests/net/utils/prj.conf b/tests/net/utils/prj.conf
index f63c6c8f05d..429ecc79499 100644
--- a/tests/net/utils/prj.conf
+++ b/tests/net/utils/prj.conf
@@ -17,3 +17,5 @@ CONFIG_NET_UDP=y
 CONFIG_ZTEST=y
 CONFIG_MAIN_STACK_SIZE=1280
 CONFIG_TEST_USERSPACE=y
+CONFIG_NET_LOOPBACK=y
+CONFIG_NET_DRIVERS=y
diff --git a/tests/net/utils/src/main.c b/tests/net/utils/src/main.c
index 15a51e8ca73..a5db67bd0b4 100644
--- a/tests/net/utils/src/main.c
+++ b/tests/net/utils/src/main.c
@@ -863,6 +863,435 @@ ZTEST(test_utils_fn, test_addr_parse)
 #endif
 }
 
+#if defined(CONFIG_NET_IPV4) && defined(CONFIG_NET_IPV6)
+static const char *check_ipaddr(const char *addresses)
+{
+	do {
+		char addr_str[NET_IPV6_ADDR_LEN + 4 + 1];
+		char expecting[NET_IPV6_ADDR_LEN + 4 + 1];
+		const char *orig = addresses;
+		struct sockaddr_storage addr;
+		struct sockaddr_storage mask;
+		uint8_t mask_len;
+		int ret;
+
+		memset(&addr, 0, sizeof(addr));
+		mask_len = 0;
+
+		memset(addr_str, 0, sizeof(addr_str));
+		memset(expecting, 0, sizeof(expecting));
+
+		addresses = net_ipaddr_parse_mask(addresses, strlen(addresses),
+						  (struct sockaddr *)&addr, &mask_len);
+		zassert_not_null(addresses, "Invalid parse, expecting \"%s\"", orig);
+
+		strncpy(expecting, orig,
+			*addresses == '\0' ? strlen(orig) : addresses - orig - 1);
+
+		(void)net_addr_ntop(addr.ss_family,
+				    &net_sin((struct sockaddr *)&addr)->sin_addr,
+				    addr_str, sizeof(addr_str));
+
+		ret = net_mask_len_to_netmask(addr.ss_family, mask_len,
+					      (struct sockaddr *)&mask);
+		zassert_equal(ret, 0, "Failed to convert mask %d", mask_len);
+
+		ret = net_netmask_to_mask_len(addr.ss_family,
+					      (struct sockaddr *)&mask,
+					      &mask_len);
+		zassert_equal(ret, 0, "Failed to convert mask %s",
+			      net_sprint_addr(addr.ss_family,
+					      (const void *)&net_sin(
+						      ((struct sockaddr *)&mask))->sin_addr));
+
+		if (net_sin((struct sockaddr *)&mask)->sin_addr.s_addr != 0) {
+			int addr_len = strlen(addr_str);
+
+			snprintk(addr_str + addr_len,
+				 sizeof(addr_str) - addr_len,
+				 "/%d", mask_len);
+		}
+
+		zassert_mem_equal(addr_str, expecting,
+				  *addresses == '\0' ? strlen(orig) : addresses - orig - 1,
+				  "Address mismatch, expecing %s, got %s (len %d)\n",
+				  expecting, addr_str, addresses - orig - 1);
+	} while (addresses != NULL && *addresses != '\0');
+
+	return addresses;
+}
+#endif /* CONFIG_NET_IPV4 && CONFIG_NET_IPV6 */
+
+ZTEST(test_utils_fn, test_addr_parse_mask)
+{
+	struct sockaddr addr;
+	uint8_t mask_len;
+	const char *next;
+	int i;
+#if defined(CONFIG_NET_IPV4)
+	static const struct {
+		const char *address;
+		int len;
+		struct sockaddr_in result;
+		uint8_t mask_len;
+		const char *verdict;
+	} parse_ipv4_entries[] = {
+		{
+			.address = "192.0.2.1:80",
+			.len = sizeof("192.0.2.1:80") - 1,
+			.verdict = NULL,
+		},
+		{
+			.address = "192.0.2.2",
+			.len = sizeof("192.0.2.2") - 1,
+			.result = {
+				.sin_family = AF_INET,
+				.sin_addr = {
+					.s4_addr[0] = 192,
+					.s4_addr[1] = 0,
+					.s4_addr[2] = 2,
+					.s4_addr[3] = 2
+				}
+			},
+			.verdict = "",
+		},
+		{
+			.address = "192.0.2.3/foobar",
+			.len = sizeof("192.0.2.3/foobar") - 1,
+			.verdict = NULL,
+		},
+		{
+			.address = "127.0.0.42,1.2.3.4",
+			.len = sizeof("127.0.0.42,1.2.3.4") - 1,
+			.result = {
+				.sin_family = AF_INET,
+				.sin_addr = {
+					.s4_addr[0] = 127,
+					.s4_addr[1] = 0,
+					.s4_addr[2] = 0,
+					.s4_addr[3] = 42
+				}
+			},
+			.mask_len = 32,
+			.verdict = &"127.0.0.42,1.2.3.4"[11],
+		},
+		{
+			.address = "127.0.0.42/8,1.2.3.4",
+			.len = sizeof("127.0.0.42/8,1.2.3.4") - 1,
+			.result = {
+				.sin_family = AF_INET,
+				.sin_addr = {
+					.s4_addr[0] = 127,
+					.s4_addr[1] = 0,
+					.s4_addr[2] = 0,
+					.s4_addr[3] = 42
+				}
+			},
+			.mask_len = 8,
+			.verdict = &"127.0.0.42/8,1.2.3.4"[13],
+		},
+		{
+			.address = "192.0.2.3:80/foobar",
+			.len = sizeof("192.0.2.3:80/foobar") - 1,
+			.verdict = false
+		},
+		{
+			.address = "192.168.1.1:65536/foobar",
+			.len = sizeof("192.168.1.1:65536") - 1,
+			.verdict = false
+		},
+		{
+			.address = "192.0.2.3:80/foobar",
+			.len = sizeof("192.0.2.3") - 1,
+			.result = {
+				.sin_family = AF_INET,
+				.sin_port = 0,
+				.sin_addr = {
+					.s4_addr[0] = 192,
+					.s4_addr[1] = 0,
+					.s4_addr[2] = 2,
+					.s4_addr[3] = 3
+				}
+			},
+			.verdict = "",
+		},
+		{
+			.address = "192.0.2.3:80/foobar",
+			.len = sizeof("192.0.2.3:80") - 1,
+			.verdict = NULL,
+		},
+		{
+			.address = "a.b.c.d",
+			.verdict = false
+		},
+	};
+#endif
+#if defined(CONFIG_NET_IPV6)
+	static const struct {
+		const char *address;
+		int len;
+		struct sockaddr_in6 result;
+		uint8_t mask_len;
+		const char *verdict;
+	} parse_ipv6_entries[] = {
+		{
+			.address = "2001:db8::2",
+			.len = sizeof("2001:db8::2") - 1,
+			.result = {
+				.sin6_family = AF_INET6,
+				.sin6_addr = {
+					.s6_addr16[0] = ntohs(0x2001),
+					.s6_addr16[1] = ntohs(0xdb8),
+					.s6_addr16[3] = 0,
+					.s6_addr16[4] = 0,
+					.s6_addr16[5] = 0,
+					.s6_addr16[6] = 0,
+					.s6_addr16[7] = ntohs(2)
+				}
+			},
+			.verdict = "",
+		},
+		{
+			.address = "2001:db8::a/barfoo",
+			.len = sizeof("2001:db8::a/barfoo") - 8,
+			.result = {
+				.sin6_family = AF_INET6,
+				.sin6_port = 0,
+				.sin6_addr = {
+					.s6_addr16[0] = ntohs(0x2001),
+					.s6_addr16[1] = ntohs(0xdb8),
+					.s6_addr16[3] = 0,
+					.s6_addr16[4] = 0,
+					.s6_addr16[5] = 0,
+					.s6_addr16[6] = 0,
+					.s6_addr16[7] = ntohs(0xa)
+				}
+			},
+			.verdict = "",
+		},
+		{
+			.address = "2001:db8::a",
+			.len = sizeof("2001:db8::a") - 1,
+			.result = {
+				.sin6_family = AF_INET6,
+				.sin6_port = 0,
+				.sin6_addr = {
+					.s6_addr16[0] = ntohs(0x2001),
+					.s6_addr16[1] = ntohs(0xdb8),
+					.s6_addr16[3] = 0,
+					.s6_addr16[4] = 0,
+					.s6_addr16[5] = 0,
+					.s6_addr16[6] = 0,
+					.s6_addr16[7] = ntohs(0xa)
+				}
+			},
+			.verdict = "",
+		},
+		{
+			.address = "[2001:db8:3:4:5:6:7:8]:65535",
+			.len = sizeof("[2001:db8:3:4:5:6:7:8]:65535") - 1,
+			.verdict = NULL,
+		},
+		{
+			.address = "[::]:0",
+			.len = sizeof("[::]:0") - 1,
+			.verdict = NULL,
+		},
+		{
+			.address = "2001:db8::42",
+			.len = sizeof("2001:db8::42") - 1,
+			.result = {
+				.sin6_family = AF_INET6,
+				.sin6_port = 0,
+				.sin6_addr = {
+					.s6_addr16[0] = ntohs(0x2001),
+					.s6_addr16[1] = ntohs(0xdb8),
+					.s6_addr16[3] = 0,
+					.s6_addr16[4] = 0,
+					.s6_addr16[5] = 0,
+					.s6_addr16[6] = 0,
+					.s6_addr16[7] = ntohs(0x42)
+				}
+			},
+			.verdict = "",
+		},
+		{
+			.address = "[2001:db8::192.0.2.1]:80000",
+			.len = sizeof("[2001:db8::192.0.2.1]:80000") - 1,
+			.verdict = NULL,
+		},
+		{
+			.address = "[2001:db8::1]:80",
+			.len = sizeof("[2001:db8::1") - 1,
+			.verdict = NULL,
+		},
+		{
+			.address = "[2001:db8::1]:65536",
+			.len = sizeof("[2001:db8::1]:65536") - 1,
+			.verdict = NULL,
+		},
+		{
+			.address = "[2001:db8::1]:80",
+			.len = sizeof("2001:db8::1") - 1,
+			.verdict = NULL,
+		},
+		{
+			.address = "[2001:db8::1]:a",
+			.len = sizeof("[2001:db8::1]:a") - 1,
+			.verdict = NULL,
+		},
+		{
+			.address = "[2001:db8::1]:10-12",
+			.len = sizeof("[2001:db8::1]:10-12") - 1,
+			.verdict = NULL,
+		},
+		{
+			.address = "[2001:db8::]:80/url/continues",
+			.len = sizeof("[2001:db8::]") - 1,
+			.verdict = NULL,
+		},
+		{
+			.address = "[2001:db8::200]:080",
+			.len = sizeof("[2001:db8:433:2]:80000") - 1,
+			.verdict = NULL,
+		},
+		{
+			.address = "[2001:db8::]:8080/another/url",
+			.len = sizeof("[2001:db8::]:8080/another/url") - 1,
+			.verdict = NULL,
+		},
+		{
+			.address = "[2001:db8::1",
+			.len = sizeof("[2001:db8::1") - 1,
+			.verdict = NULL,
+		},
+		{
+			.address = "[2001:db8::1]:-1",
+			.len = sizeof("[2001:db8::1]:-1") - 1,
+			.verdict = NULL,
+		},
+		{
+			/* Valid although user probably did not mean this */
+			.address = "2001:db8::1:80",
+			.len = sizeof("2001:db8::1:80") - 1,
+			.result = {
+				.sin6_family = AF_INET6,
+				.sin6_addr = {
+					.s6_addr16[0] = ntohs(0x2001),
+					.s6_addr16[1] = ntohs(0xdb8),
+					.s6_addr16[3] = 0,
+					.s6_addr16[4] = 0,
+					.s6_addr16[5] = 0,
+					.s6_addr16[6] = ntohs(0x01),
+					.s6_addr16[7] = ntohs(0x80)
+				}
+			},
+			.verdict = "",
+		},
+		{
+			.address = "2001:db8::1/64,2001:db8::2",
+			.len = sizeof("2001:db8::1/64,2001:db8::2") - 1,
+			.result = {
+				.sin6_family = AF_INET6,
+				.sin6_addr = {
+					.s6_addr16[0] = ntohs(0x2001),
+					.s6_addr16[1] = ntohs(0xdb8),
+					.s6_addr16[2] = 0,
+					.s6_addr16[3] = 0,
+					.s6_addr16[4] = 0,
+					.s6_addr16[5] = 0,
+					.s6_addr16[6] = 0,
+					.s6_addr16[7] = ntohs(0x01)
+				}
+			},
+			.mask_len = 64,
+			.verdict = &"2001:db8::1/64,2001:db8::2"[14],
+		},
+	};
+#endif
+
+#if defined(CONFIG_NET_IPV4)
+	for (i = 0; i < ARRAY_SIZE(parse_ipv4_entries) - 1; i++) {
+		(void)memset(&addr, 0, sizeof(addr));
+		mask_len = 0;
+
+		next = net_ipaddr_parse_mask(
+			parse_ipv4_entries[i].address,
+			parse_ipv4_entries[i].len,
+			&addr, &mask_len);
+		if (next != parse_ipv4_entries[i].verdict) {
+			printk("IPv4 entry [%d] \"%s\" failed\n", i,
+				parse_ipv4_entries[i].address);
+			printk("Points to \"%s\" but should point to \"%s\"\n",
+			       next == NULL ? "NULL" : next,
+			       parse_ipv4_entries[i].verdict == NULL ?
+			       "NULL" : parse_ipv4_entries[i].verdict);
+			zassert_true(false, "failure");
+		}
+
+		if (next != NULL && *next == '\0') {
+			zassert_true(
+				net_ipv4_addr_cmp(
+				      &net_sin(&addr)->sin_addr,
+				      &parse_ipv4_entries[i].result.sin_addr),
+				parse_ipv4_entries[i].address);
+			zassert_true(net_sin(&addr)->sin_port == 0,
+				     "IPv4 port");
+			zassert_true(net_sin(&addr)->sin_family ==
+				     parse_ipv4_entries[i].result.sin_family,
+				     "IPv4 family");
+		}
+	}
+#endif
+#if defined(CONFIG_NET_IPV6)
+	for (i = 0; i < ARRAY_SIZE(parse_ipv6_entries) - 1; i++) {
+		(void)memset(&addr, 0, sizeof(addr));
+		mask_len = 0;
+
+		next = net_ipaddr_parse_mask(
+			parse_ipv6_entries[i].address,
+			parse_ipv6_entries[i].len,
+			&addr, &mask_len);
+		if (next != parse_ipv6_entries[i].verdict) {
+			printk("IPv6 entry [%d] \"%s\" failed\n", i,
+			       parse_ipv6_entries[i].address);
+			zassert_true(false, "failure");
+		}
+
+		if (next != NULL && *next == '\0') {
+			zassert_true(
+				net_ipv6_addr_cmp(
+				      &net_sin6(&addr)->sin6_addr,
+				      &parse_ipv6_entries[i].result.sin6_addr),
+				parse_ipv6_entries[i].address);
+			zassert_true(net_sin6(&addr)->sin6_port == 0,
+				     "IPv6 port");
+			zassert_true(net_sin6(&addr)->sin6_family ==
+				     parse_ipv6_entries[i].result.sin6_family,
+				     "IPv6 family");
+		}
+	}
+#endif
+
+#if defined(CONFIG_NET_IPV4) && defined(CONFIG_NET_IPV6)
+	static const char * const addresses[] = {
+		"2001:db8::1/64,192.0.2.1,2001:db8::2,192.0.2.2/24",
+		"2001:db8::1/64 192.0.2.1 2001:db8::2 192.0.2.2/24",
+		"2001:db8::1/64 192.0.2.1,2001:db8::2 192.0.2.2/24",
+		NULL
+	};
+
+	i = 0;
+
+	while (addresses[i] != NULL) {
+		next = check_ipaddr(addresses[i]);
+		zassert_true(next != NULL && *next == '\0',
+			     "Invalid parse, expecting \"\", got %p\n", next);
+		i++;
+	}
+#endif /* CONFIG_NET_IPV4 && CONFIG_NET_IPV6 */
+}
+
 static uint16_t calc_chksum_ref(uint16_t sum, const uint8_t *data, size_t len)
 {
 	const uint8_t *end;
@@ -938,4 +1367,107 @@ ZTEST(test_utils_fn, test_ip_checksum)
 	}
 }
 
+/* Verify that the net_pkt pointer to the received link layer address
+ * is correct.
+ */
+ZTEST(test_utils_fn, test_linkaddr_handling)
+{
+	/* A simple Ethernet frame with IPv4 and UDP headers */
+	static const uint8_t udp[] = {
+		0x18, 0xfd, 0x74, 0x09, 0xcb, 0x62, 0xac, 0x91,  /* 0000 */
+		0xa1, 0x8f, 0x9d, 0xf8, 0x08, 0x00, 0x45, 0x00,  /* 0008 */
+		0x00, 0x4c, 0x48, 0x8e, 0x00, 0x00, 0x40, 0x11,  /* 0010 */
+		0x57, 0x34, 0xc0, 0xa8, 0x58, 0x29, 0xc1, 0xe5,  /* 0018 */
+		0x00, 0x28, 0xba, 0xf0, 0x00, 0x35, 0x00, 0x38,  /* 0020 */
+		0xdb, 0x28,
+	};
+
+	/* Create net_pkt from the above data, then check the link layer
+	 * addresses are properly set even if we pull the data like how
+	 * the network stack would do in ethernet.c
+	 */
+	const uint8_t *dst = &udp[0];
+	const uint8_t *src = &udp[NET_ETH_ADDR_LEN];
+	uint8_t hdr_len = sizeof(struct net_eth_hdr);
+	struct net_linkaddr *lladdr;
+	struct net_eth_hdr *hdr;
+	struct net_pkt *pkt, *pkt2;
+	int ret;
+
+	pkt = net_pkt_rx_alloc_with_buffer(net_if_get_default(),
+					   sizeof(udp), AF_UNSPEC,
+					   0, K_NO_WAIT);
+	zassert_not_null(pkt, "Cannot allocate pkt");
+
+	ret = net_pkt_write(pkt, udp, sizeof(udp));
+	zassert_equal(ret, 0, "Cannot write data to pkt");
+
+	hdr = NET_ETH_HDR(pkt);
+
+	/* Set the pointers to ll src and dst addresses */
+	lladdr = net_pkt_lladdr_src(pkt);
+	memcpy(lladdr->addr, hdr->src.addr, sizeof(struct net_eth_addr));
+	lladdr->len = sizeof(struct net_eth_addr);
+	lladdr->type = NET_LINK_ETHERNET;
+
+	lladdr = net_pkt_lladdr_dst(pkt);
+	memcpy(lladdr->addr, hdr->dst.addr, sizeof(struct net_eth_addr));
+	lladdr->len = sizeof(struct net_eth_addr);
+	lladdr->type = NET_LINK_ETHERNET;
+
+	zassert_mem_equal(net_pkt_lladdr_src(pkt)->addr,
+			  src, NET_ETH_ADDR_LEN,
+			  "Source address mismatch");
+	zassert_mem_equal(net_pkt_lladdr_dst(pkt)->addr,
+			  dst, NET_ETH_ADDR_LEN,
+			  "Destination address mismatch");
+
+	pkt2 = net_pkt_clone(pkt, K_NO_WAIT);
+	zassert_not_null(pkt2, "Cannot clone pkt");
+
+	/* Make sure we still point to the correct addresses after cloning */
+	zassert_mem_equal(net_pkt_lladdr_src(pkt2)->addr,
+			  src, NET_ETH_ADDR_LEN,
+			  "Source address mismatch");
+	zassert_mem_equal(net_pkt_lladdr_dst(pkt2)->addr,
+			  dst, NET_ETH_ADDR_LEN,
+			  "Destination address mismatch");
+
+	net_pkt_unref(pkt2);
+
+	/* Get rid of the Ethernet header. */
+	net_buf_pull(pkt->frags, hdr_len);
+
+	/* Make sure we still point to the correct addresses after pulling
+	 * the Ethernet header.
+	 */
+	zassert_mem_equal(net_pkt_lladdr_src(pkt)->addr,
+			  src, NET_ETH_ADDR_LEN,
+			  "Source address mismatch");
+	zassert_mem_equal(net_pkt_lladdr_dst(pkt)->addr,
+			  dst, NET_ETH_ADDR_LEN,
+			  "Destination address mismatch");
+
+	/* Clone the packet and check that the link layer addresses are
+	 * still correct.
+	 */
+
+	pkt2 = net_pkt_clone(pkt, K_NO_WAIT);
+	zassert_not_null(pkt2, "Cannot clone pkt");
+
+	zassert_not_equal(net_pkt_lladdr_src(pkt2)->addr,
+			  net_pkt_lladdr_src(pkt)->addr,
+			  "Source address should not be the same");
+
+	zassert_mem_equal(net_pkt_lladdr_src(pkt2)->addr,
+			  src, NET_ETH_ADDR_LEN,
+			  "Source address mismatch");
+	zassert_mem_equal(net_pkt_lladdr_dst(pkt2)->addr,
+			  dst, NET_ETH_ADDR_LEN,
+			  "Destination address mismatch");
+
+	net_pkt_unref(pkt);
+	net_pkt_unref(pkt2);
+}
+
 ZTEST_SUITE(test_utils_fn, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/net/virtual/src/main.c b/tests/net/virtual/src/main.c
index 12dacdaea06..94d14442a00 100644
--- a/tests/net/virtual/src/main.c
+++ b/tests/net/virtual/src/main.c
@@ -212,7 +212,7 @@ static uint8_t *net_iface_get_mac(const struct device *dev)
 		data->mac_addr[5] = sys_rand8_get();
 	}
 
-	data->ll_addr.addr = data->mac_addr;
+	memcpy(data->ll_addr.addr, data->mac_addr, sizeof(data->mac_addr));
 	data->ll_addr.len = 6U;
 
 	return data->mac_addr;
@@ -503,19 +503,17 @@ static void test_address_setup(void)
 
 static bool add_neighbor(struct net_if *iface, struct in6_addr *addr)
 {
-	struct net_linkaddr_storage llstorage;
 	struct net_linkaddr lladdr;
 	struct net_nbr *nbr;
 
-	llstorage.addr[0] = 0x01;
-	llstorage.addr[1] = 0x02;
-	llstorage.addr[2] = 0x33;
-	llstorage.addr[3] = 0x44;
-	llstorage.addr[4] = 0x05;
-	llstorage.addr[5] = 0x06;
+	lladdr.addr[0] = 0x01;
+	lladdr.addr[1] = 0x02;
+	lladdr.addr[2] = 0x33;
+	lladdr.addr[3] = 0x44;
+	lladdr.addr[4] = 0x05;
+	lladdr.addr[5] = 0x06;
 
 	lladdr.len = 6U;
-	lladdr.addr = llstorage.addr;
 	lladdr.type = NET_LINK_ETHERNET;
 
 	nbr = net_ipv6_nbr_add(iface, addr, &lladdr, false,
diff --git a/tests/net/vlan/src/main.c b/tests/net/vlan/src/main.c
index 628c3c7dd5a..a1b6fd97d69 100644
--- a/tests/net/vlan/src/main.c
+++ b/tests/net/vlan/src/main.c
@@ -52,12 +52,46 @@ LOG_MODULE_REGISTER(net_test, NET_LOG_LEVEL);
 #define VLAN_TAG_4 400
 #define VLAN_TAG_5 500
 #define VLAN_TAG_6 600
+#define VLAN_TAG_7 700
 
 #define NET_ETH_MAX_COUNT 2
 
 #define MY_IPV6_ADDR "2001:db8:200::2"
 #define MY_IPV6_ADDR_SRV "2001:db8:200::1"
 
+/* ICMPv6 Echo Request from 2001:db8::2 to 2001:db8::1,
+ * src mac 00:00:5e:00:53:ff dst 02:00:5e:00:53:31
+ * VLAN tag 0, priority 0
+ */
+static unsigned char icmpv6_echo_request[] = {
+/* 0000 */  0x02, 0x00, 0x5e, 0x00, 0x53, 0x31, 0x00, 0x00,
+	    0x5e, 0x00, 0x53, 0xff, 0x81, 0x00, 0x00, 0x00,
+/* 0010 */  0x86, 0xdd, 0x60, 0x00, 0x00, 0x00, 0x00, 0x08,
+	    0x3a, 0x40, 0x20, 0x01, 0x0d, 0xb8, 0x00, 0x00,
+/* 0020 */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	    0x00, 0x02, 0x20, 0x01, 0x0d, 0xb8, 0x00, 0x00,
+/* 0030 */  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+	    0x00, 0x01, 0x80, 0x00, 0x24, 0x48, 0x00, 0x00,
+/* 0040 */  0x00, 0x00,
+};
+
+/* ICMPv6 Echo Reply from 2001:db8::1 to 2001:db8::2,
+ * src mac 02:00:5e:00:53:31 dst 00:00:5e:00:53:08
+ * No VLAN tag.
+ */
+static unsigned char icmpv6_echo_reply[] = {
+/* 1st fragment with Ethernet header */
+	0x00, 0x00, 0x5e, 0x00, 0x53, 0x08, 0x00, 0x00,
+	0x5e, 0x00, 0x53, 0x08, 0x86, 0xdd,
+/* 2nd fragment, with IPv6 header and ICMPv6 Echo Reply */
+	0x60, 0x00, 0x00, 0x00, 0x00, 0x08, 0x3a, 0x40,
+	0x20, 0x01, 0x0d, 0xb8, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
+	0x20, 0x01, 0x0d, 0xb8, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
+	0x81, 0x00, 0x23, 0x48, 0x00, 0x00, 0x00, 0x00,
+};
+
 /* Interface 1 addresses */
 static struct in6_addr my_addr1 = { { { 0x20, 0x01, 0x0d, 0xb8, 1, 0, 0, 0,
 					0, 0, 0, 0, 0, 0, 0, 0x1 } } };
@@ -75,14 +109,27 @@ static struct in6_addr ll_addr = { { { 0xfe, 0x80, 0x43, 0xb8, 0, 0, 0, 0,
 				       0, 0, 0, 0xf2, 0xaa, 0x29, 0x02,
 				       0x04 } } };
 
+/* Peer addresses */
+static struct in6_addr peer_addr = { { { 0x20, 0x01, 0x0d, 0xb8, 0, 0, 0, 0,
+					 0, 0, 0, 0, 0, 0, 0, 0x2 } } };
+
 /* Keep track of all ethernet interfaces */
 static struct net_if *eth_interfaces[NET_ETH_MAX_COUNT];
-static struct net_if *vlan_interfaces[NET_VLAN_MAX_COUNT];
+
+#if NET_VLAN_MAX_COUNT > 0
+#define MAX_IFACE_VLAN_COUNT NET_VLAN_MAX_COUNT
+#else
+#define MAX_IFACE_VLAN_COUNT 1
+#endif
+
+static struct net_if *vlan_interfaces[MAX_IFACE_VLAN_COUNT];
 static struct net_if *dummy_interfaces[2];
 static struct net_if *embed_ll_interface;
+static struct net_if *test_iface;
 
 static bool test_failed;
 static bool test_started;
+static bool expecting_vlan_tag_0;
 
 static K_SEM_DEFINE(wait_data, 0, UINT_MAX);
 
@@ -127,6 +174,26 @@ static int eth_tx(const struct device *dev, struct net_pkt *pkt)
 	struct eth_context *context = dev->data;
 	int ret;
 
+	if (expecting_vlan_tag_0) {
+		uint8_t reply[sizeof(icmpv6_echo_reply) - sizeof(struct net_eth_hdr)];
+		uint16_t ptype;
+
+		expecting_vlan_tag_0 = false;
+		test_iface = net_pkt_iface(pkt);
+		net_pkt_cursor_init(pkt);
+		net_pkt_set_overwrite(pkt, true);
+		net_pkt_skip(pkt, sizeof(struct net_eth_hdr) - 2);
+		net_pkt_read_be16(pkt, &ptype);
+		zassert_equal(ptype, NET_ETH_PTYPE_IPV6, "Invalid ptype 0x%04x", ptype);
+		net_pkt_read(pkt, reply, sizeof(reply));
+		zassert_mem_equal(reply, icmpv6_echo_reply + sizeof(struct net_eth_hdr),
+				  sizeof(reply) - sizeof(struct net_eth_hdr),
+				  "Invalid ICMPv6 Echo Reply");
+
+		k_sem_give(&wait_data);
+		return 0;
+	}
+
 	if (!IS_ENABLED(CONFIG_NET_L2_ETHERNET_RESERVE_HEADER)) {
 		/* There should be at least two net_buf. The first one should contain
 		 * the link layer header.
@@ -267,7 +334,7 @@ static uint8_t *net_iface_get_mac(const struct device *dev)
 	data->mac_addr[4] = 0x53;
 	data->mac_addr[5] = sys_rand8_get();
 
-	data->ll_addr.addr = data->mac_addr;
+	memcpy(data->ll_addr.addr, data->mac_addr, 6);
 	data->ll_addr.len = 6U;
 
 	return data->mac_addr;
@@ -373,7 +440,7 @@ static void iface_cb(struct net_if *iface, void *user_data)
 	if (net_if_l2(iface) == &NET_L2_GET_NAME(VIRTUAL)) {
 		vlan_interfaces[ud->vlan_if_count++] = iface;
 
-		zassert_true(ud->vlan_if_count <= NET_VLAN_MAX_COUNT,
+		zassert_true(ud->vlan_if_count <= MAX_IFACE_VLAN_COUNT,
 			     "Too many VLAN interfaces");
 	}
 
@@ -398,16 +465,20 @@ static void test_vlan_setup(void)
 	/* Make sure we have enough virtual interfaces */
 	net_if_foreach(iface_cb, &ud);
 
+	if (NET_VLAN_MAX_COUNT == 0) {
+		return;
+	}
+
 	/* One extra eth interface without vlan support */
-	zassert_equal(ud.vlan_if_count, NET_VLAN_MAX_COUNT,
+	zassert_equal(ud.vlan_if_count, MAX_IFACE_VLAN_COUNT,
 		      "Invalid number of VLANs %d vs %d",
-		      ud.vlan_if_count, NET_VLAN_MAX_COUNT);
+		      ud.vlan_if_count, MAX_IFACE_VLAN_COUNT);
 
-	remaining = ud.total_if_count - NET_VLAN_MAX_COUNT -
+	remaining = ud.total_if_count - MAX_IFACE_VLAN_COUNT -
 		ud.eth_if_count - ud.dummy_if_count;
 	zassert_equal(remaining, 0,
 		      "Invalid number of interfaces expecting %d got %d+%d+%d",
-		      ud.total_if_count, NET_VLAN_MAX_COUNT,
+		      ud.total_if_count, MAX_IFACE_VLAN_COUNT,
 		      ud.eth_if_count, ud.dummy_if_count);
 }
 
@@ -418,11 +489,14 @@ static void test_address_setup(void)
 
 	iface1 = eth_interfaces[1]; /* This has VLAN enabled */
 	iface2 = eth_interfaces[0]; /* and this one not */
-	iface3 = vlan_interfaces[0]; /* and this is the virtual VLAN interface */
 
 	zassert_not_null(iface1, "Interface 1");
 	zassert_not_null(iface2, "Interface 2");
-	zassert_not_null(iface3, "Interface 3");
+
+	if (NET_VLAN_MAX_COUNT > 0) {
+		iface3 = vlan_interfaces[0]; /* and this is the virtual VLAN interface */
+		zassert_not_null(iface3, "Interface 3");
+	}
 
 	ifaddr = net_if_ipv6_addr_add(iface1, &my_addr1,
 				      NET_ADDR_MANUAL, 0);
@@ -455,15 +529,17 @@ static void test_address_setup(void)
 
 	ifaddr->addr_state = NET_ADDR_PREFERRED;
 
-	ifaddr = net_if_ipv6_addr_add(iface3, &my_addr3,
-				      NET_ADDR_MANUAL, 0);
-	if (!ifaddr) {
-		DBG("Cannot add IPv6 address %s\n",
-		       net_sprint_ipv6_addr(&my_addr3));
-		zassert_not_null(ifaddr, "addr3");
-	}
+	if (NET_VLAN_MAX_COUNT > 0) {
+		ifaddr = net_if_ipv6_addr_add(iface3, &my_addr3,
+					      NET_ADDR_MANUAL, 0);
+		if (!ifaddr) {
+			DBG("Cannot add IPv6 address %s\n",
+			    net_sprint_ipv6_addr(&my_addr3));
+			zassert_not_null(ifaddr, "addr3");
+		}
 
-	ifaddr->addr_state = NET_ADDR_PREFERRED;
+		ifaddr->addr_state = NET_ADDR_PREFERRED;
+	}
 
 	net_if_up(iface1);
 	net_if_up(iface2);
@@ -579,6 +655,10 @@ static void test_vlan_enable(void)
 	struct net_if *iface;
 	int ret;
 
+	if (NET_VLAN_MAX_COUNT == 0) {
+		return;
+	}
+
 	ret = net_eth_vlan_enable(eth_interfaces[0], VLAN_TAG_1);
 	zassert_equal(ret, 0, "Cannot enable %d (%d)", VLAN_TAG_1, ret);
 	ret = net_eth_vlan_enable(eth_interfaces[0], VLAN_TAG_2);
@@ -654,6 +734,10 @@ static void test_vlan_disable(void)
 	struct net_if *iface;
 	int ret;
 
+	if (NET_VLAN_MAX_COUNT == 0) {
+		return;
+	}
+
 	ret = net_eth_vlan_disable(eth_interfaces[1], VLAN_TAG_1);
 	zassert_not_equal(ret, 0, "Could disable %d (%d)", VLAN_TAG_1, ret);
 
@@ -699,6 +783,10 @@ static void test_vlan_enable_all(void)
 	struct net_if *iface;
 	int ret;
 
+	if (NET_VLAN_MAX_COUNT == 0) {
+		return;
+	}
+
 	ret = net_eth_vlan_enable(eth_interfaces[0], VLAN_TAG_1);
 	zassert_true(ret == 0 || ret == -EALREADY, "Cannot enable %d", VLAN_TAG_1);
 	ret = net_eth_vlan_enable(eth_interfaces[0], VLAN_TAG_2);
@@ -738,6 +826,10 @@ static void test_vlan_disable_all(void)
 	struct net_if *iface;
 	int ret;
 
+	if (NET_VLAN_MAX_COUNT == 0) {
+		return;
+	}
+
 	ret = net_eth_vlan_disable(eth_interfaces[0], VLAN_TAG_1);
 	zassert_equal(ret, 0, "Cannot disable %d", VLAN_TAG_1);
 	ret = net_eth_vlan_disable(eth_interfaces[0], VLAN_TAG_2);
@@ -843,6 +935,10 @@ ZTEST(net_vlan, test_vlan_ipv6_sendto_recvfrom)
 	struct sockaddr_in6 server_addr;
 	struct eth_context *ctx;
 
+	if (NET_VLAN_MAX_COUNT == 0) {
+		return;
+	}
+
 	/* Setup the interfaces */
 	test_vlan_enable();
 	test_vlan_disable_all();
@@ -906,6 +1002,10 @@ ZTEST(net_vlan, test_zz_vlan_embed_ll_hdr)
 	static struct in6_addr peer_vlan_addr = { { { 0x20, 0x01, 0x0d, 0xb8, 0x90, 0, 0, 0,
 						    0, 0, 0, 0, 0, 0, 0, 0x1 } } };
 
+	if (NET_VLAN_MAX_COUNT == 0) {
+		return;
+	}
+
 	ret = net_eth_vlan_enable(embed_ll_interface, VLAN_TAG_6);
 	zassert_equal(ret, 0, "Could not enable %d (%d)", VLAN_TAG_6, ret);
 
@@ -975,4 +1075,99 @@ ZTEST(net_vlan, test_vlan_enable_disable_all)
 	test_vlan_disable_all();
 }
 
+static bool add_peer_neighbor(struct net_if *iface, struct in6_addr *addr,
+			      uint8_t *lladdr)
+{
+	struct net_linkaddr ll_addr = {
+		.len = 6,
+		.type = NET_LINK_ETHERNET
+	};
+	struct net_nbr *nbr;
+
+	memcpy(ll_addr.addr, lladdr, 6);
+
+	nbr = net_ipv6_nbr_add(iface, addr, &ll_addr, false,
+			       NET_IPV6_NBR_STATE_REACHABLE);
+	if (!nbr) {
+		DBG("Cannot add dst %s to neighbor cache\n",
+		    net_sprint_ipv6_addr(addr));
+		return false;
+	}
+
+	DBG("Adding dst %s as [%s] to nbr cache\n",
+	    net_sprint_ipv6_addr(addr),
+	    net_sprint_ll_addr(ll_addr.addr, 6));
+
+	return true;
+}
+
+ZTEST(net_vlan, test_vlan_tag_0)
+{
+	struct eth_context *context;
+	const struct device *dev;
+	struct net_if *iface;
+	struct net_pkt *pkt;
+	int ret;
+
+	if (NET_VLAN_MAX_COUNT > 0) {
+		iface = vlan_interfaces[0];
+	} else {
+		iface = eth_interfaces[0];
+	}
+
+	dev = net_if_get_device(eth_interfaces[0]);
+	context = dev->data;
+
+	/* Set the receiving mac address of the example packet */
+	memcpy(&icmpv6_echo_request[0], context->mac_addr, 6);
+
+	net_if_down(eth_interfaces[0]);
+
+	if (NET_VLAN_MAX_COUNT > 0) {
+		net_if_down(vlan_interfaces[0]);
+
+		/* Setup the interfaces */
+		ret = net_eth_vlan_enable(eth_interfaces[0], VLAN_TAG_7);
+		zassert_equal(ret, 0, "Cannot enable %d (%d)", VLAN_TAG_7, ret);
+	}
+
+	net_if_up(eth_interfaces[0]);
+
+	if (NET_VLAN_MAX_COUNT > 0) {
+		net_if_up(vlan_interfaces[0]);
+	}
+
+	ret = add_peer_neighbor(iface, &peer_addr, &icmpv6_echo_request[0]);
+	zassert_true(ret, "Cannot add neighbor");
+
+	/* Create ICMPv6 echo request packet, then send it to the Ethernet
+	 * interface. Expect the ICMPv6 echo response to be sent back to the
+	 * same interface.
+	 */
+	pkt = net_pkt_rx_alloc_with_buffer(iface,
+					   sizeof(icmpv6_echo_request),
+					   AF_INET6,
+					   IPPROTO_ICMPV6,
+					   K_NO_WAIT);
+	zassert_not_null(pkt, "Cannot allocate pkt");
+
+	ret = net_pkt_write(pkt, icmpv6_echo_request, sizeof(icmpv6_echo_request));
+	zassert_equal(ret, 0, "Cannot write to pkt");
+
+	expecting_vlan_tag_0 = true;
+	test_iface = eth_interfaces[0];
+
+	/* Make sure that the reply packet is sent to the correct interface */
+	ret = net_recv_data(eth_interfaces[0], pkt);
+	zassert_false(ret < 0, "Cannot receive data (%d)", ret);
+
+	if (k_sem_take(&wait_data, WAIT_TIME)) {
+		DBG("Timeout while waiting interface data\n");
+		zassert_false(true, "Timeout");
+	}
+
+	zassert_false(expecting_vlan_tag_0, "VLAN tag 0 not received");
+	zassert_equal(test_iface, eth_interfaces[0], "Wrong interface");
+}
+
 ZTEST_SUITE(net_vlan, NULL, setup, NULL, NULL, NULL);
diff --git a/tests/net/vlan/testcase.yaml b/tests/net/vlan/testcase.yaml
index 97f637bd3f1..3d276cf0052 100644
--- a/tests/net/vlan/testcase.yaml
+++ b/tests/net/vlan/testcase.yaml
@@ -11,7 +11,12 @@ tests:
   net.vlan.header_reserved:
     extra_configs:
       - CONFIG_NET_L2_ETHERNET_RESERVE_HEADER=y
+      - CONFIG_TEST_EXTRA_STACK_SIZE=1024
   net.vlan.header_reserved.variable_size:
     extra_configs:
       - CONFIG_NET_L2_ETHERNET_RESERVE_HEADER=y
       - CONFIG_NET_BUF_VARIABLE_DATA_SIZE=y
+      - CONFIG_TEST_EXTRA_STACK_SIZE=1024
+  net.vlan.priority_tagging_only:
+    extra_configs:
+      - CONFIG_NET_VLAN_COUNT=0
diff --git a/tests/net/wifi/configs/prj.conf b/tests/net/wifi/configs/prj.conf
index 2a2f4d2cf6b..b9660aba0d9 100644
--- a/tests/net/wifi/configs/prj.conf
+++ b/tests/net/wifi/configs/prj.conf
@@ -28,6 +28,5 @@ CONFIG_WIFI_NM_WPA_SUPPLICANT=y
 CONFIG_WIFI_NM_WPA_SUPPLICANT_DEBUG_LEVEL=0
 CONFIG_WIFI_NM_WPA_SUPPLICANT_WEP=y
 CONFIG_WIFI_NM_WPA_SUPPLICANT_ADVANCED_FEATURES=y
-CONFIG_WIFI_NM_WPA_SUPPLICANT_AP=y
 CONFIG_WIFI_NM_WPA_SUPPLICANT_CLI=y
 CONFIG_WPA_CLI=y
diff --git a/tests/net/wifi/configs/testcase.yaml b/tests/net/wifi/configs/testcase.yaml
index e74f40ce4d5..17c2d5603f7 100644
--- a/tests/net/wifi/configs/testcase.yaml
+++ b/tests/net/wifi/configs/testcase.yaml
@@ -4,6 +4,7 @@ common:
     - drivers
     - wifi
     - net
+    - hostap
   platform_allow:
     - native_sim
 tests:
@@ -39,6 +40,9 @@ tests:
     extra_configs:
       - CONFIG_WIFI_NM_WPA_SUPPLICANT_WPA3=y
       - CONFIG_MBEDTLS_TLS_VERSION_1_2=y
+  wifi.build.ap:
+    extra_configs:
+      - CONFIG_WIFI_NM_WPA_SUPPLICANT_AP=y
   wifi.build.wps:
     extra_configs:
       - CONFIG_WIFI_NM_WPA_SUPPLICANT_WPS=y
diff --git a/tests/posix/barriers/testcase.yaml b/tests/posix/barriers/testcase.yaml
index a00bd02322f..1636c2b640c 100644
--- a/tests/posix/barriers/testcase.yaml
+++ b/tests/posix/barriers/testcase.yaml
@@ -7,6 +7,8 @@ common:
   platform_key:
     - arch
     - simulation
+  integration_platforms:
+    - qemu_cortex_a53
   min_flash: 64
   min_ram: 32
 tests:
diff --git a/tests/posix/c_lib_ext/testcase.yaml b/tests/posix/c_lib_ext/testcase.yaml
index 8c6859289e8..639caf5520d 100644
--- a/tests/posix/c_lib_ext/testcase.yaml
+++ b/tests/posix/c_lib_ext/testcase.yaml
@@ -8,8 +8,8 @@ common:
   platform_key:
     - arch
     - simulation
-  min_flash: 64
-  min_ram: 32
+  integration_platforms:
+    - qemu_cortex_m0
 tests:
   portability.posix.c_lib_ext:
     extra_configs:
diff --git a/tests/posix/common/boards/qemu_x86_tiny.overlay b/tests/posix/common/boards/qemu_x86_tiny.overlay
index f717f3ff7ed..4e23cf84e32 100644
--- a/tests/posix/common/boards/qemu_x86_tiny.overlay
+++ b/tests/posix/common/boards/qemu_x86_tiny.overlay
@@ -4,8 +4,6 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/ {
-	dram0: memory@0 {
-		reg = <0x100000 0x80000>;
-	};
+&dram0 {
+	reg = <0x100000 0x80000>;
 };
diff --git a/tests/posix/common/src/cond.c b/tests/posix/common/src/cond.c
index b648ac0abd0..94de124c375 100644
--- a/tests/posix/common/src/cond.c
+++ b/tests/posix/common/src/cond.c
@@ -55,7 +55,7 @@ ZTEST(cond, test_pthread_condattr)
 	zassert_ok(pthread_condattr_init(&att));
 
 	zassert_ok(pthread_condattr_getclock(&att, &clock_id), "pthread_condattr_getclock failed");
-	zassert_equal(clock_id, CLOCK_MONOTONIC, "clock attribute not set correctly");
+	zassert_equal(clock_id, CLOCK_REALTIME, "clock attribute not set correctly");
 
 	zassert_ok(pthread_condattr_setclock(&att, CLOCK_REALTIME),
 		   "pthread_condattr_setclock failed");
diff --git a/tests/posix/common/src/pthread.c b/tests/posix/common/src/pthread.c
index b86c1b4f395..035730ee4dc 100644
--- a/tests/posix/common/src/pthread.c
+++ b/tests/posix/common/src/pthread.c
@@ -12,16 +12,16 @@
 
 #define DETACH_THR_ID 2
 
-#define N_THR_E 3
-#define N_THR_T 4
-#define BOUNCES 64
+#define N_THR_E    3
+#define N_THR_T    4
+#define BOUNCES    64
 #define ONE_SECOND 1
 
 /* Macros to test invalid states */
 #define PTHREAD_CANCEL_INVALID -1
-#define SCHED_INVALID -1
-#define PRIO_INVALID -1
-#define PTHREAD_INVALID -1
+#define SCHED_INVALID          -1
+#define PRIO_INVALID           -1
+#define PTHREAD_INVALID        -1
 
 static void *thread_top_exec(void *p1);
 static void *thread_top_term(void *p1);
@@ -57,13 +57,13 @@ static int barrier_return[N_THR_E];
 
 static void *thread_top_exec(void *p1)
 {
-	int i, j, id = (int) POINTER_TO_INT(p1);
+	int i, j, id = (int)POINTER_TO_INT(p1);
 	int policy;
 	struct sched_param schedparam;
 
 	pthread_getschedparam(pthread_self(), &policy, &schedparam);
-	printk("Thread %d starting with scheduling policy %d & priority %d\n",
-		 id, policy, schedparam.sched_priority);
+	printk("Thread %d starting with scheduling policy %d & priority %d\n", id, policy,
+	       schedparam.sched_priority);
 	/* Try a double-lock here to exercise the failing case of
 	 * trylock.  We don't support RECURSIVE locks, so this is
 	 * guaranteed to fail.
@@ -201,11 +201,9 @@ static void *thread_top_term(void *p1)
 		      "Unable to set thread priority!");
 
 	zassert_false(pthread_getschedparam(self, &policy, &getschedparam),
-			"Unable to get thread priority!");
+		      "Unable to get thread priority!");
 
-	printk("Thread %d starting with a priority of %d\n",
-			id,
-			getschedparam.sched_priority);
+	printk("Thread %d starting with a priority of %d\n", id, getschedparam.sched_priority);
 
 	if (id % 2) {
 		ret = pthread_setcancelstate(PTHREAD_CANCEL_DISABLE, NULL);
@@ -304,8 +302,7 @@ ZTEST(pthread, test_pthread_execution)
 	zassert_false(ret, "Set thread name failed!");
 
 	/* TESTPOINT: Try getting thread name */
-	ret = pthread_getname_np(newthread[0], thr_name_buf,
-				 sizeof(thr_name_buf));
+	ret = pthread_getname_np(newthread[0], thr_name_buf, sizeof(thr_name_buf));
 	zassert_false(ret, "Get thread name failed!");
 
 	/* TESTPOINT: Thread names match */
@@ -407,9 +404,8 @@ ZTEST(pthread, test_pthread_timedjoin)
 	struct timespec not_done;
 	struct timespec done;
 	struct timespec invalid[] = {
-		[0] = {.tv_sec = -1},
-		[1] = {.tv_nsec = -1},
-		[2] = {.tv_nsec = NSEC_PER_SEC},
+		{.tv_nsec = -1},
+		{.tv_nsec = NSEC_PER_SEC},
 	};
 
 	/* setup timespecs when the thread is still running and when it is done */
@@ -429,7 +425,7 @@ ZTEST(pthread, test_pthread_timedjoin)
 	/* Creating a thread that exits after 200ms*/
 	zassert_ok(pthread_create(&th, NULL, timedjoin_thread, INT_TO_POINTER(sleep_duration_ms)));
 
-	/* pthread_timedjoin-np must return -EINVAL for invalid struct timespecs */
+	/* pthread_timedjoin-np must return EINVAL for invalid struct timespecs */
 	zassert_equal(pthread_timedjoin_np(th, &ret, NULL), EINVAL);
 	for (size_t i = 0; i < ARRAY_SIZE(invalid); ++i) {
 		zassert_equal(pthread_timedjoin_np(th, &ret, &invalid[i]), EINVAL);
@@ -460,57 +456,6 @@ ZTEST(pthread, test_pthread_descriptor_leak)
 	}
 }
 
-ZTEST(pthread, test_sched_getparam)
-{
-	struct sched_param param;
-	int rc = sched_getparam(0, &param);
-	int err = errno;
-
-	zassert_true((rc == -1 && err == ENOSYS));
-}
-
-ZTEST(pthread, test_sched_getscheduler)
-{
-	int rc = sched_getscheduler(0);
-	int err = errno;
-
-	zassert_true((rc == -1 && err == ENOSYS));
-}
-ZTEST(pthread, test_sched_setparam)
-{
-	struct sched_param param = {
-		.sched_priority = 2,
-	};
-	int rc = sched_setparam(0, &param);
-	int err = errno;
-
-	zassert_true((rc == -1 && err == ENOSYS));
-}
-
-ZTEST(pthread, test_sched_setscheduler)
-{
-	struct sched_param param = {
-		.sched_priority = 2,
-	};
-	int policy = 0;
-	int rc = sched_setscheduler(0, policy, &param);
-	int err = errno;
-
-	zassert_true((rc == -1 && err == ENOSYS));
-}
-
-ZTEST(pthread, test_sched_rr_get_interval)
-{
-	struct timespec interval = {
-		.tv_sec = 0,
-		.tv_nsec = 0,
-	};
-	int rc = sched_rr_get_interval(0, &interval);
-	int err = errno;
-
-	zassert_true((rc == -1 && err == ENOSYS));
-}
-
 ZTEST(pthread, test_pthread_equal)
 {
 	zassert_true(pthread_equal(pthread_self(), pthread_self()));
diff --git a/tests/posix/common/testcase.yaml b/tests/posix/common/testcase.yaml
index 0b3ab9db419..2d6443139ac 100644
--- a/tests/posix/common/testcase.yaml
+++ b/tests/posix/common/testcase.yaml
@@ -7,8 +7,6 @@ common:
     - arch
     - simulation
   platform_exclude:
-    - native_posix
-    - native_posix/native/64
     # consistently overflows flash
     - qemu_nios2
   filter: not CONFIG_NATIVE_LIBC
diff --git a/tests/posix/eventfd/testcase.yaml b/tests/posix/eventfd/testcase.yaml
index b21c02bb907..6646036067c 100644
--- a/tests/posix/eventfd/testcase.yaml
+++ b/tests/posix/eventfd/testcase.yaml
@@ -7,6 +7,8 @@ common:
   platform_key:
     - arch
     - simulation
+  integration_platforms:
+    - qemu_riscv64
 tests:
   portability.posix.eventfd: {}
   portability.posix.eventfd.minimal:
diff --git a/tests/posix/fs/src/test_fs_file.c b/tests/posix/fs/src/test_fs_file.c
index ee1fcd1e058..23496c92b8c 100644
--- a/tests/posix/fs/src/test_fs_file.c
+++ b/tests/posix/fs/src/test_fs_file.c
@@ -141,45 +141,6 @@ static int test_file_close(void)
 	return res;
 }
 
-static int test_file_fsync(void)
-{
-	int res = 0;
-
-	if (file < 0) {
-		return res;
-	}
-
-	res = fsync(file);
-	if (res < 0) {
-		TC_ERROR("Failed to sync file: %d, errno = %d\n", res, errno);
-		res = TC_FAIL;
-	}
-
-	close(file);
-	file = -1;
-	return res;
-}
-
-#ifdef CONFIG_POSIX_SYNCHRONIZED_IO
-static int test_file_fdatasync(void)
-{
-	int res = 0;
-
-	if (file < 0) {
-		return res;
-	}
-
-	res = fdatasync(file);
-	if (res < 0) {
-		TC_ERROR("Failed to sync file: %d, errno = %d\n", res, errno);
-		res = TC_FAIL;
-	}
-
-	close(file);
-	file = -1;
-	return res;
-}
-#endif /* CONFIG_POSIX_SYNCHRONIZED_IO */
 
 static int test_file_truncate(void)
 {
@@ -261,36 +222,6 @@ ZTEST(posix_fs_file_test, test_fs_read)
 	zassert_true(test_file_read() == TC_PASS);
 }
 
-/**
- * @brief Test for POSIX fsync API
- *
- * @details Test sync the file through POSIX fsync API.
- */
-ZTEST(posix_fs_file_test, test_fs_sync)
-{
-	/* FIXME: restructure tests as per #46897 */
-	zassert_true(test_file_open() == TC_PASS);
-	zassert_true(test_file_write() == TC_PASS);
-	zassert_true(test_file_fsync() == TC_PASS);
-}
-
-/**
- * @brief Test for POSIX fdatasync API
- *
- * @details Test sync the file through POSIX fdatasync API.
- */
-ZTEST(posix_fs_file_test, test_fs_datasync)
-{
-#ifdef CONFIG_POSIX_SYNCHRONIZED_IO
-	/* FIXME: restructure tests as per #46897 */
-	zassert_true(test_file_open() == TC_PASS);
-	zassert_true(test_file_write() == TC_PASS);
-	zassert_true(test_file_fdatasync() == TC_PASS);
-#else
-	ztest_test_skip();
-#endif
-}
-
 /**
  * @brief Test for POSIX ftruncate API
  *
diff --git a/tests/posix/fs/testcase.yaml b/tests/posix/fs/testcase.yaml
index 359ff70dae1..f9354065505 100644
--- a/tests/posix/fs/testcase.yaml
+++ b/tests/posix/fs/testcase.yaml
@@ -2,9 +2,6 @@ common:
   filter: not CONFIG_NATIVE_LIBC
   arch_exclude:
     - nios2
-  platform_exclude:
-    - native_posix
-    - native_posix/native/64
   tags:
     - posix
     - filesystem
@@ -16,6 +13,9 @@ common:
   platform_key:
     - arch
     - simulation
+  integration_platforms:
+    - qemu_x86
+    - qemu_riscv64
 tests:
   portability.posix.fs: {}
   portability.posix.fs.minimal:
diff --git a/tests/posix/headers/src/netinet_in_h.c b/tests/posix/headers/src/netinet_in_h.c
index 141e2eb69fc..bd89cab22c2 100644
--- a/tests/posix/headers/src/netinet_in_h.c
+++ b/tests/posix/headers/src/netinet_in_h.c
@@ -12,8 +12,6 @@
 #include <zephyr/posix/netinet/in.h>
 #endif
 
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wunused-variable"
 /**
  * @brief existence test for `<netinet/in.h>`
  *
@@ -100,4 +98,3 @@ ZTEST(posix_headers, test_netinet_in_h)
 	zexpect_true(IN6_IS_ADDR_MC_ORGLOCAL(&mcol6));
 	zexpect_true(IN6_IS_ADDR_MC_GLOBAL(&mcg6));
 }
-#pragma GCC diagnostic pop
diff --git a/tests/posix/headers/src/pthread_h.c b/tests/posix/headers/src/pthread_h.c
index c7cca66feb0..7cf79dc7970 100644
--- a/tests/posix/headers/src/pthread_h.c
+++ b/tests/posix/headers/src/pthread_h.c
@@ -12,8 +12,6 @@
 #include <zephyr/posix/pthread.h>
 #endif
 
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wunused-variable"
 /**
  * @brief existence test for `<pthread.h>`
  *
@@ -45,7 +43,7 @@ ZTEST(posix_headers, test_pthread_h)
 	/* zassert_not_equal(-1, PTHREAD_MUTEX_ROBUST); */  /* not implemented */
 	/* zassert_not_equal(-1, PTHREAD_MUTEX_STALLED); */ /* not implemented */
 
-	pthread_once_t once = PTHREAD_ONCE_INIT;
+	__unused pthread_once_t once = PTHREAD_ONCE_INIT;
 
 	/* zassert_not_equal(-1, PTHREAD_PRIO_INHERIT); */ /* not implemented */
 	zassert_not_equal(-1, PTHREAD_PRIO_NONE);
@@ -57,8 +55,8 @@ ZTEST(posix_headers, test_pthread_h)
 	zassert_not_equal(-1, PTHREAD_SCOPE_PROCESS);
 	zassert_not_equal(-1, PTHREAD_SCOPE_SYSTEM);
 
-	pthread_cond_t cond = PTHREAD_COND_INITIALIZER;
-	pthread_mutex_t mu = PTHREAD_MUTEX_INITIALIZER;
+	__unused pthread_cond_t cond = PTHREAD_COND_INITIALIZER;
+	__unused pthread_mutex_t mu = PTHREAD_MUTEX_INITIALIZER;
 	/* pthread_rwlock_t lock = POSIX_READER_WRITER_LOCKS_INITIALIZER; */ /* not implemented */
 
 	zassert_not_null(pthread_atfork);
@@ -161,4 +159,3 @@ ZTEST(posix_headers, test_pthread_h)
 	zassert_not_null(pthread_testcancel);
 #endif
 }
-#pragma GCC diagnostic pop
diff --git a/tests/posix/headers/src/sys_socket_h.c b/tests/posix/headers/src/sys_socket_h.c
index 843e6c16d76..60f25514dae 100644
--- a/tests/posix/headers/src/sys_socket_h.c
+++ b/tests/posix/headers/src/sys_socket_h.c
@@ -12,8 +12,6 @@
 #include <zephyr/posix/sys/socket.h>
 #endif
 
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wunused-value"
 /**
  * @brief existence test for `<sys/socket.h>`
  *
@@ -51,9 +49,9 @@ ZTEST(posix_headers, test_sys_socket_h)
 	zassert_not_equal(-1, offsetof(struct cmsghdr, cmsg_level));
 	zassert_not_equal(-1, offsetof(struct cmsghdr, cmsg_type));
 
-	CMSG_DATA(&cmsg);
-	CMSG_NXTHDR(&mhdr, &cmsg);
-	CMSG_FIRSTHDR(&mhdr);
+	ARG_UNUSED(CMSG_DATA(&cmsg));
+	__unused struct cmsghdr *next = CMSG_NXTHDR(&mhdr, &cmsg);
+	__unused struct cmsghdr *first = CMSG_FIRSTHDR(&mhdr);
 
 	zassert_not_equal(-1, offsetof(struct linger, l_onoff));
 	zassert_not_equal(-1, offsetof(struct linger, l_linger));
@@ -120,4 +118,3 @@ ZTEST(posix_headers, test_sys_socket_h)
 		zassert_not_null(socketpair);
 	}
 }
-#pragma GCC diagnostic pop
diff --git a/tests/posix/headers/testcase.yaml b/tests/posix/headers/testcase.yaml
index 7a15e49ea90..746ca007ca2 100644
--- a/tests/posix/headers/testcase.yaml
+++ b/tests/posix/headers/testcase.yaml
@@ -7,6 +7,8 @@ common:
   platform_key:
     - arch
     - simulation
+  integration_platforms:
+    - qemu_x86_64
 tests:
   portability.posix.headers.with_posix_api:
     extra_configs:
diff --git a/tests/posix/net/testcase.yaml b/tests/posix/net/testcase.yaml
index 24cd19f01f1..2075c84e102 100644
--- a/tests/posix/net/testcase.yaml
+++ b/tests/posix/net/testcase.yaml
@@ -5,11 +5,11 @@ common:
     - iface
     - net
     - posix
-  # 1 tier0 platform per supported architecture (dependent on netif support)
+  # dependent on netif support
   integration_platforms:
     - mps2/an385
     - qemu_x86
-  # native_posix and native_sim link to if_*() from the host libc which causes the test to crash
+  # Building with the host libC links to if_*() from the host libc which causes the test to crash
   # immediately.
   filter: not CONFIG_NATIVE_LIBC
 tests:
diff --git a/tests/posix/rwlocks/prj.conf b/tests/posix/rwlocks/prj.conf
index e55d87a7ad1..eff85b030dd 100644
--- a/tests/posix/rwlocks/prj.conf
+++ b/tests/posix/rwlocks/prj.conf
@@ -3,3 +3,7 @@ CONFIG_ZTEST=y
 
 CONFIG_POSIX_AEP_CHOICE_BASE=y
 CONFIG_POSIX_READER_WRITER_LOCKS=y
+
+CONFIG_DYNAMIC_THREAD=y
+CONFIG_DYNAMIC_THREAD_POOL_SIZE=3
+CONFIG_THREAD_STACK_INFO=y
diff --git a/tests/posix/rwlocks/src/main.c b/tests/posix/rwlocks/src/main.c
index 450180aff6f..aaf859663bf 100644
--- a/tests/posix/rwlocks/src/main.c
+++ b/tests/posix/rwlocks/src/main.c
@@ -11,6 +11,7 @@
 #include <zephyr/ztest.h>
 
 #define N_THR 3
+BUILD_ASSERT(N_THR <= CONFIG_DYNAMIC_THREAD_POOL_SIZE, "Insufficient number of dynamic threads");
 
 LOG_MODULE_REGISTER(posix_rwlock_test);
 
@@ -85,8 +86,9 @@ ZTEST(posix_rw_locks, test_rw_lock)
 	usleep(USEC_PER_MSEC);
 	LOG_DBG("Parent thread acquiring WR lock again");
 
-	time.tv_sec = 2;
-	time.tv_nsec = 0;
+	zassert_ok(clock_gettime(CLOCK_REALTIME, &time));
+	time.tv_sec += 2;
+
 	ret = pthread_rwlock_timedwrlock(&rwlock, &time);
 	if (ret) {
 		zassert_ok(pthread_rwlock_wrlock(&rwlock), "Failed to acquire write lock");
@@ -144,14 +146,4 @@ ZTEST(posix_rw_locks, test_pthread_rwlockattr_setpshared)
 	test_pthread_rwlockattr_pshared_common(true, PTHREAD_PROCESS_SHARED);
 }
 
-static void before(void *arg)
-{
-	ARG_UNUSED(arg);
-
-	if (!IS_ENABLED(CONFIG_DYNAMIC_THREAD)) {
-		/* skip redundant testing if there is no thread pool / heap allocation */
-		ztest_test_skip();
-	}
-}
-
-ZTEST_SUITE(posix_rw_locks, NULL, NULL, before, NULL, NULL);
+ZTEST_SUITE(posix_rw_locks, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/posix/rwlocks/testcase.yaml b/tests/posix/rwlocks/testcase.yaml
index 84a151e60b5..9e31cbc07d0 100644
--- a/tests/posix/rwlocks/testcase.yaml
+++ b/tests/posix/rwlocks/testcase.yaml
@@ -7,6 +7,8 @@ common:
   platform_key:
     - arch
     - simulation
+  integration_platforms:
+    - qemu_riscv64
   min_flash: 64
   min_ram: 32
 tests:
diff --git a/tests/posix/semaphores/prj.conf b/tests/posix/semaphores/prj.conf
index 5376678d6a9..49b867610a0 100644
--- a/tests/posix/semaphores/prj.conf
+++ b/tests/posix/semaphores/prj.conf
@@ -3,3 +3,7 @@ CONFIG_ZTEST=y
 
 CONFIG_POSIX_AEP_CHOICE_BASE=y
 CONFIG_POSIX_SEMAPHORES=y
+
+CONFIG_DYNAMIC_THREAD=y
+CONFIG_DYNAMIC_THREAD_POOL_SIZE=2
+CONFIG_THREAD_STACK_INFO=y
diff --git a/tests/posix/semaphores/src/main.c b/tests/posix/semaphores/src/main.c
index 228165fb131..c99e0fca1e9 100644
--- a/tests/posix/semaphores/src/main.c
+++ b/tests/posix/semaphores/src/main.c
@@ -13,6 +13,12 @@
 #include <zephyr/sys/util.h>
 #include <zephyr/ztest.h>
 
+#define WAIT_TIME_MS 100
+BUILD_ASSERT(WAIT_TIME_MS > 0, "WAIT_TIME_MS must be posistive");
+
+/* based on the current structure of this unit test */
+BUILD_ASSERT(CONFIG_DYNAMIC_THREAD_POOL_SIZE >= 2, "CONFIG_DYNAMIC_THREAD_POOL_SIZE must be >= 2");
+
 static void *child_func(void *p1)
 {
 	sem_t *sem = (sem_t *)p1;
@@ -51,11 +57,10 @@ static void semaphore_test(sem_t *sem)
 
 	zassert_equal(clock_gettime(CLOCK_REALTIME, &abstime), 0, "clock_gettime failed");
 
-	abstime.tv_sec += 5;
+	abstime.tv_sec += WAIT_TIME_MS / MSEC_PER_SEC;
+	abstime.tv_nsec += (WAIT_TIME_MS % MSEC_PER_SEC) * NSEC_PER_MSEC;
 
-	/* TESPOINT: Wait for 5 seconds and acquire sema given
-	 * by thread1
-	 */
+	/* TESPOINT: Wait to acquire sem given by thread1 */
 	zassert_equal(sem_timedwait(sem, &abstime), 0);
 
 	/* TESTPOINT: Semaphore is already acquired, check if
@@ -71,9 +76,7 @@ static void semaphore_test(sem_t *sem)
 	zassert_equal(sem_getvalue(sem, &val), 0);
 	zassert_equal(val, 1);
 
-	zassert_equal(sem_destroy(sem), -1,
-		      "acquired semaphore"
-		      " is destroyed");
+	zassert_equal(sem_destroy(sem), -1, "acquired semaphore is destroyed");
 	zassert_equal(errno, EBUSY);
 
 	/* TESTPOINT: take semaphore which is initialized with 1 */
@@ -312,14 +315,4 @@ ZTEST(posix_semaphores, test_named_semaphore)
 	zassert_equal(nsem_get_list_len(), 0);
 }
 
-static void before(void *arg)
-{
-	ARG_UNUSED(arg);
-
-	if (!IS_ENABLED(CONFIG_DYNAMIC_THREAD)) {
-		/* skip redundant testing if there is no thread pool / heap allocation */
-		ztest_test_skip();
-	}
-}
-
-ZTEST_SUITE(posix_semaphores, NULL, NULL, before, NULL, NULL);
+ZTEST_SUITE(posix_semaphores, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/posix/semaphores/testcase.yaml b/tests/posix/semaphores/testcase.yaml
index 92fdebbd992..5201ad90283 100644
--- a/tests/posix/semaphores/testcase.yaml
+++ b/tests/posix/semaphores/testcase.yaml
@@ -7,6 +7,8 @@ common:
   platform_key:
     - arch
     - simulation
+  integration_platforms:
+    - qemu_x86_64
   min_flash: 64
   min_ram: 32
 tests:
diff --git a/tests/posix/shm/CMakeLists.txt b/tests/posix/shm/CMakeLists.txt
deleted file mode 100644
index 65e1ac9b27f..00000000000
--- a/tests/posix/shm/CMakeLists.txt
+++ /dev/null
@@ -1,8 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-cmake_minimum_required(VERSION 3.20.0)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(shm)
-
-FILE(GLOB app_sources src/*.c)
-target_sources(app PRIVATE ${app_sources})
diff --git a/tests/posix/shm/prj.conf b/tests/posix/shm/prj.conf
deleted file mode 100644
index 04734c10d7c..00000000000
--- a/tests/posix/shm/prj.conf
+++ /dev/null
@@ -1,4 +0,0 @@
-CONFIG_ZTEST=y
-
-CONFIG_POSIX_API=y
-CONFIG_POSIX_SHARED_MEMORY_OBJECTS=y
diff --git a/tests/posix/shm/src/main.c b/tests/posix/shm/src/main.c
deleted file mode 100644
index 625398e24aa..00000000000
--- a/tests/posix/shm/src/main.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * Copyright (c) 2024, Tenstorrent AI ULC
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <sys/mman.h>
-
-#include <zephyr/kernel.h>
-#include <zephyr/net/socket.h>
-#include <zephyr/posix/fcntl.h>
-#include <zephyr/sys/fdtable.h>
-
-#include <zephyr/ztest.h>
-
-#define SHM_SIZE 8
-
-#define VALID_SHM_PATH     "/foo"
-#define INVALID_SHM_PATH   "foo"
-#define EMPTY_SHM_PATH     ""
-#define TOO_SHORT_SHM_PATH "/"
-
-#define INVALID_MODE 0
-#define VALID_MODE   0666
-
-#define INVALID_FLAGS 0
-#define VALID_FLAGS   (O_RDWR | O_CREAT)
-#define CREATE_FLAGS  VALID_FLAGS
-#define OPEN_FLAGS    (VALID_FLAGS & ~O_CREAT)
-
-/* account for stdin, stdout, stderr */
-#define N (CONFIG_ZVFS_OPEN_MAX - 3)
-
-/* we need to have at least 2 shared memory objects */
-BUILD_ASSERT(N >= 2, "CONFIG_ZVFS_OPEN_MAX must be > 4");
-
-#define S_TYPEISSHM(st) (((st)->st_mode & ZVFS_MODE_IFMT) == ZVFS_MODE_IFSHM)
-
-ZTEST(shm, test_shm_open)
-{
-	int ret;
-	int fd[N];
-	struct stat st;
-
-	{
-		/* degenerate error cases */
-		zassert_not_ok(shm_open(NULL, INVALID_FLAGS, INVALID_MODE));
-		zassert_not_ok(shm_open(NULL, INVALID_FLAGS, VALID_MODE));
-		zassert_not_ok(shm_open(NULL, VALID_FLAGS, INVALID_MODE));
-		zassert_not_ok(shm_open(NULL, VALID_FLAGS, VALID_MODE));
-		zassert_not_ok(shm_open(INVALID_SHM_PATH, VALID_FLAGS, VALID_MODE));
-		zassert_not_ok(shm_open(EMPTY_SHM_PATH, VALID_FLAGS, VALID_MODE));
-		zassert_not_ok(shm_open(TOO_SHORT_SHM_PATH, VALID_FLAGS, VALID_MODE));
-		zassert_not_ok(shm_open(VALID_SHM_PATH, INVALID_FLAGS, INVALID_MODE));
-		zassert_not_ok(shm_open(VALID_SHM_PATH, INVALID_FLAGS, VALID_MODE));
-		zassert_not_ok(shm_open(VALID_SHM_PATH, VALID_FLAGS, INVALID_MODE));
-	}
-
-	/* open / close 1 file descriptor referring to VALID_SHM_PATH */
-	fd[0] = shm_open(VALID_SHM_PATH, VALID_FLAGS, VALID_MODE);
-	zassert_true(fd[0] >= 0, "shm_open(%s, %x, %04o) failed: %d", VALID_SHM_PATH, VALID_FLAGS,
-		     VALID_MODE, errno);
-
-	/* should have size 0 and be a shared memory object */
-	zassert_ok(fstat(fd[0], &st));
-	zassert_equal(st.st_size, 0);
-	zassert_true(S_TYPEISSHM(&st));
-
-	/* technically, the order of close / shm_unlink can be reversed too */
-	zassert_ok(close(fd[0]));
-	ret = shm_unlink(VALID_SHM_PATH);
-	zassert_true(ret == 0 || (ret == -1 && errno == ENOENT),
-		     "unexpected return / errno from shm_unlink: %d / %d", ret, errno);
-
-	/* open / close N file descriptors referring to VALID_SHM_PATH */
-	for (size_t i = 0; i < N; ++i) {
-		fd[i] = shm_open(VALID_SHM_PATH, i == 0 ? CREATE_FLAGS : OPEN_FLAGS, VALID_MODE);
-		zassert_true(fd[i] >= 0, "shm_open(%s, %x, %04o) failed: %d", VALID_SHM_PATH,
-			     VALID_FLAGS, VALID_MODE, errno);
-	}
-	zassert_ok(shm_unlink(VALID_SHM_PATH));
-	for (size_t i = N; i > 0; --i) {
-		zassert_ok(close(fd[i - 1]));
-	}
-}
-
-ZTEST(shm, test_shm_unlink)
-{
-	int fd;
-
-	{
-		/* degenerate error cases */
-		zassert_not_ok(shm_unlink(NULL));
-		zassert_not_ok(shm_unlink(INVALID_SHM_PATH));
-		zassert_not_ok(shm_unlink(EMPTY_SHM_PATH));
-		zassert_not_ok(shm_unlink(TOO_SHORT_SHM_PATH));
-	}
-
-	/* open / close 1 file descriptor referring to VALID_SHM_PATH */
-	fd = shm_open(VALID_SHM_PATH, VALID_FLAGS, VALID_MODE);
-	zassert_true(fd >= 0, "shm_open(%s, %x, %04o) failed: %d", VALID_SHM_PATH, VALID_FLAGS,
-		     VALID_MODE, errno);
-	/* technically, the order of close / shm_unlink can be reversed too */
-	zassert_ok(close(fd));
-	zassert_ok(shm_unlink(VALID_SHM_PATH));
-	/* should not be able to re-open the same path without O_CREAT */
-	zassert_not_ok(shm_open(VALID_SHM_PATH, OPEN_FLAGS, VALID_MODE));
-}
-
-ZTEST(shm, test_shm_read_write)
-{
-	int fd[N];
-
-	for (size_t i = 0; i < N; ++i) {
-		char cbuf = 0xff;
-
-		fd[i] = shm_open(VALID_SHM_PATH, i == 0 ? CREATE_FLAGS : OPEN_FLAGS, VALID_MODE);
-		zassert_true(fd[i] >= 0, "shm_open(%s, %x, %04o) failed: %d", VALID_SHM_PATH,
-			     VALID_FLAGS, VALID_MODE, errno);
-		if (i == 0) {
-			/* size 0 on create / zero characters written */
-			zassert_equal(write(fd[0], "", 1), 0,
-				      "write() should fail on newly create shm fd with size 0");
-			/* size 0 on create / zero characters read */
-			zassert_equal(read(fd[0], &cbuf, 1), 0,
-				      "read() should fail on newly create shm fd with size 0");
-
-			BUILD_ASSERT(SHM_SIZE >= 1);
-			zassert_ok(ftruncate(fd[0], SHM_SIZE));
-
-			zassert_equal(write(fd[0], "\x42", 1), 1, "write() failed on fd %d: %d\n",
-				      fd[0], errno);
-
-			continue;
-		}
-
-		zassert_equal(read(fd[i], &cbuf, 1), 1, "read() failed on fd %d: %d\n", fd[i],
-			      errno);
-		zassert_equal(cbuf, 0x42,
-			      "Failed to read byte over fd %d: expected: 0x%02x actual: 0x%02x",
-			      fd[i], 0x42, cbuf);
-	}
-
-	for (size_t i = N; i > 0; --i) {
-		zassert_ok(close(fd[i - 1]));
-	}
-
-	zassert_ok(shm_unlink(VALID_SHM_PATH));
-}
-
-ZTEST(shm, test_shm_mmap)
-{
-	int fd[N];
-	void *addr[N];
-
-	if (!IS_ENABLED(CONFIG_MMU)) {
-		ztest_test_skip();
-	}
-
-	for (size_t i = 0; i < N; ++i) {
-		fd[i] = shm_open(VALID_SHM_PATH, i == 0 ? CREATE_FLAGS : OPEN_FLAGS, VALID_MODE);
-		zassert_true(fd[i] >= 0, "shm_open(%s, %x, %04o) failed: %d", VALID_SHM_PATH,
-			     VALID_FLAGS, VALID_MODE, errno);
-
-		if (i == 0) {
-			/* cannot map shm of size zero */
-			zassert_not_ok(mmap(NULL, PAGE_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED,
-					    fd[0], 0));
-
-			zassert_ok(ftruncate(fd[0], PAGE_SIZE));
-		}
-
-		addr[i] = mmap(NULL, PAGE_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd[i], 0);
-		zassert_not_equal(MAP_FAILED, addr[i], "mmap() failed: %d", errno);
-
-		if ((i & 1) == 0) {
-			memset(addr[0], i & 0xff, PAGE_SIZE);
-		} else {
-			zassert_mem_equal(addr[i], addr[i - 1], PAGE_SIZE);
-		}
-	}
-
-	for (size_t i = N; i > 0; --i) {
-		zassert_ok(close(fd[i - 1]));
-	}
-
-	for (size_t i = N; i > 0; --i) {
-		zassert_ok(munmap(addr[i - 1], PAGE_SIZE));
-		/*
-		 * Note: for some reason, in Zephyr, unmapping a physical page once, removes all
-		 * virtual mappings. When that behaviour changes, remove the break below and adjust
-		 * shm.c accordingly.
-		 */
-		break;
-	}
-
-	zassert_ok(shm_unlink(VALID_SHM_PATH));
-}
-
-ZTEST_SUITE(shm, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/posix/shm/testcase.yaml b/tests/posix/shm/testcase.yaml
deleted file mode 100644
index 1928a6e177c..00000000000
--- a/tests/posix/shm/testcase.yaml
+++ /dev/null
@@ -1,18 +0,0 @@
-common:
-  filter: not CONFIG_NATIVE_LIBC
-  tags:
-    - posix
-    - shm
-  # 1 tier0 platform per supported architecture
-  platform_key:
-    - arch
-    - simulation
-  platform_exclude:
-    # linker_zephyr_pre0.cmd:140: syntax error (??)
-    - qemu_xtensa/dc233c
-    # CONFIG_MMU=y but no arch_mem_map() or arch_mem_unmap()
-    - intel_ish_5_4_1
-    - intel_ish_5_6_0
-    - intel_ish_5_8_0
-tests:
-  portability.posix.shm: {}
diff --git a/tests/posix/signals/testcase.yaml b/tests/posix/signals/testcase.yaml
index 7d475ee19cf..de3d7166e22 100644
--- a/tests/posix/signals/testcase.yaml
+++ b/tests/posix/signals/testcase.yaml
@@ -7,6 +7,8 @@ common:
   platform_key:
     - arch
     - simulation
+  integration_platforms:
+    - qemu_riscv64
   min_flash: 64
   min_ram: 32
 tests:
diff --git a/tests/posix/single_process/testcase.yaml b/tests/posix/single_process/testcase.yaml
index 70abb822269..e4d31eaa3e3 100644
--- a/tests/posix/single_process/testcase.yaml
+++ b/tests/posix/single_process/testcase.yaml
@@ -7,6 +7,8 @@ common:
   platform_key:
     - arch
     - simulation
+  integration_platforms:
+    - qemu_riscv64
   min_flash: 64
   min_ram: 32
 tests:
diff --git a/tests/posix/spinlocks/testcase.yaml b/tests/posix/spinlocks/testcase.yaml
index c11e0092efc..4729a0c7a6e 100644
--- a/tests/posix/spinlocks/testcase.yaml
+++ b/tests/posix/spinlocks/testcase.yaml
@@ -7,6 +7,8 @@ common:
   platform_key:
     - arch
     - simulation
+  integration_platforms:
+    - qemu_x86_64
   min_flash: 64
   min_ram: 32
 tests:
diff --git a/tests/posix/timers/CMakeLists.txt b/tests/posix/timers/CMakeLists.txt
index 7c689da26a4..9eab9f09c6f 100644
--- a/tests/posix/timers/CMakeLists.txt
+++ b/tests/posix/timers/CMakeLists.txt
@@ -9,3 +9,4 @@ FILE(GLOB app_sources src/*.c)
 target_sources(app PRIVATE ${app_sources})
 
 target_compile_options(app PRIVATE -U_POSIX_C_SOURCE -D_POSIX_C_SOURCE=200809L)
+target_include_directories(app PRIVATE ${ZEPHYR_BASE}/lib/posix/options)
diff --git a/tests/posix/timers/prj.conf b/tests/posix/timers/prj.conf
index e6119b6df54..8567a0bbf46 100644
--- a/tests/posix/timers/prj.conf
+++ b/tests/posix/timers/prj.conf
@@ -3,3 +3,8 @@ CONFIG_ZTEST=y
 
 CONFIG_POSIX_AEP_CHOICE_BASE=y
 CONFIG_POSIX_TIMERS=y
+
+# Needed for timer_create() when using SIGEV_THREAD
+CONFIG_DYNAMIC_THREAD=y
+CONFIG_DYNAMIC_THREAD_POOL_SIZE=1
+CONFIG_THREAD_STACK_INFO=y
diff --git a/tests/posix/timers/src/clock.c b/tests/posix/timers/src/clock.c
index 4b9665fc797..7e6b39137b9 100644
--- a/tests/posix/timers/src/clock.c
+++ b/tests/posix/timers/src/clock.c
@@ -4,6 +4,10 @@
  *
  * SPDX-License-Identifier: Apache-2.0
  */
+
+/* for tp_ge(), tp_diff() */
+#include "posix_clock.h"
+
 #include <sys/time.h>
 #include <time.h>
 #include <unistd.h>
@@ -29,41 +33,6 @@ static const bool settable[] = {
 	true,
 };
 
-static inline int64_t ts_to_ns(const struct timespec *ts)
-{
-	return ts->tv_sec * NSEC_PER_SEC + ts->tv_nsec;
-}
-
-static inline void tv_to_ts(const struct timeval *tv, struct timespec *ts)
-{
-	ts->tv_sec = tv->tv_sec;
-	ts->tv_nsec = tv->tv_usec * NSEC_PER_USEC;
-}
-
-#define _tp_op(_a, _b, _op) (ts_to_ns(_a) _op ts_to_ns(_b))
-
-#define _decl_op(_type, _name, _op)                                                                \
-	static inline _type _name(const struct timespec *_a, const struct timespec *_b)            \
-	{                                                                                          \
-		return _tp_op(_a, _b, _op);                                                        \
-	}
-
-_decl_op(bool, tp_eq, ==);     /* a == b */
-_decl_op(bool, tp_lt, <);      /* a < b */
-_decl_op(bool, tp_gt, >);      /* a > b */
-_decl_op(bool, tp_le, <=);     /* a <= b */
-_decl_op(bool, tp_ge, >=);     /* a >= b */
-_decl_op(int64_t, tp_diff, -); /* a - b */
-
-/* lo <= (a - b) < hi */
-static inline bool tp_diff_in_range_ns(const struct timespec *a, const struct timespec *b,
-				       int64_t lo, int64_t hi)
-{
-	int64_t diff = tp_diff(a, b);
-
-	return diff >= lo && diff < hi;
-}
-
 ZTEST(posix_timers, test_clock_gettime)
 {
 	struct timespec ts;
diff --git a/tests/posix/timers/src/nanosleep.c b/tests/posix/timers/src/nanosleep.c
index d339680351a..94e40a62f60 100644
--- a/tests/posix/timers/src/nanosleep.c
+++ b/tests/posix/timers/src/nanosleep.c
@@ -149,7 +149,7 @@ static void common_lower_bound_check(int selection, clockid_t clock_id, int flag
 				     uint32_t ns)
 {
 	int r;
-	uint64_t actual_ns;
+	uint64_t actual_ns = 0;
 	uint64_t exp_ns;
 	uint64_t now;
 	uint64_t then;
diff --git a/tests/posix/timers/src/timer.c b/tests/posix/timers/src/timer.c
index faad7f659fc..1d4936d6a4b 100644
--- a/tests/posix/timers/src/timer.c
+++ b/tests/posix/timers/src/timer.c
@@ -154,14 +154,4 @@ static void after(void *arg)
 	}
 }
 
-static void before(void *arg)
-{
-	ARG_UNUSED(arg);
-
-	if (!IS_ENABLED(CONFIG_DYNAMIC_THREAD)) {
-		/* skip redundant testing if there is no thread pool / heap allocation */
-		ztest_test_skip();
-	}
-}
-
-ZTEST_SUITE(posix_timers, NULL, NULL, before, after, NULL);
+ZTEST_SUITE(posix_timers, NULL, NULL, NULL, after, NULL);
diff --git a/tests/posix/xsi_realtime/CMakeLists.txt b/tests/posix/xsi_realtime/CMakeLists.txt
new file mode 100644
index 00000000000..473d87110d1
--- /dev/null
+++ b/tests/posix/xsi_realtime/CMakeLists.txt
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(posix_xsi_realtime)
+
+FILE(GLOB app_sources src/*.c)
+
+target_sources(app PRIVATE ${app_sources})
+
+target_compile_options(app PRIVATE -U_POSIX_C_SOURCE -D_POSIX_C_SOURCE=200809L)
diff --git a/tests/posix/xsi_realtime/app.overlay b/tests/posix/xsi_realtime/app.overlay
new file mode 100644
index 00000000000..87ae21b1e64
--- /dev/null
+++ b/tests/posix/xsi_realtime/app.overlay
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2023 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	ramdisk0 {
+		compatible = "zephyr,ram-disk";
+		disk-name = "RAM";
+		sector-size = <512>;
+		sector-count = <160>;
+	};
+};
diff --git a/tests/posix/xsi_realtime/prj.conf b/tests/posix/xsi_realtime/prj.conf
new file mode 100644
index 00000000000..c6f5999e0a2
--- /dev/null
+++ b/tests/posix/xsi_realtime/prj.conf
@@ -0,0 +1,15 @@
+CONFIG_POSIX_API=y
+CONFIG_ZTEST=y
+
+CONFIG_POSIX_AEP_CHOICE_BASE=y
+CONFIG_XSI_REALTIME=y
+CONFIG_FILE_SYSTEM=y
+CONFIG_POSIX_FILE_SYSTEM=y
+
+CONFIG_FAT_FILESYSTEM_ELM=y
+CONFIG_MAIN_STACK_SIZE=4096
+CONFIG_ZTEST_STACK_SIZE=2048
+
+CONFIG_DYNAMIC_THREAD=y
+CONFIG_THREAD_STACK_INFO=y
+CONFIG_DYNAMIC_THREAD_POOL_SIZE=6
diff --git a/tests/posix/xsi_realtime/src/main.c b/tests/posix/xsi_realtime/src/main.c
new file mode 100644
index 00000000000..034517eb783
--- /dev/null
+++ b/tests/posix/xsi_realtime/src/main.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2025 Marvin Ouma <pancakesdeath@protonmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <pthread.h>
+
+#include <zephyr/ztest.h>
+
+ZTEST(xsi_realtime, test_sched_getparam)
+{
+	struct sched_param param;
+	int rc = sched_getparam(0, &param);
+	int err = errno;
+
+	zassert_true((rc == -1 && err == ENOSYS));
+}
+
+ZTEST(xsi_realtime, test_sched_getscheduler)
+{
+	int rc = sched_getscheduler(0);
+	int err = errno;
+
+	zassert_true((rc == -1 && err == ENOSYS));
+}
+ZTEST(xsi_realtime, test_sched_setparam)
+{
+	struct sched_param param = {
+		.sched_priority = 2,
+	};
+	int rc = sched_setparam(0, &param);
+	int err = errno;
+
+	zassert_true((rc == -1 && err == ENOSYS));
+}
+
+ZTEST(xsi_realtime, test_sched_setscheduler)
+{
+	struct sched_param param = {
+		.sched_priority = 2,
+	};
+	int policy = 0;
+	int rc = sched_setscheduler(0, policy, &param);
+	int err = errno;
+
+	zassert_true((rc == -1 && err == ENOSYS));
+}
+
+ZTEST(xsi_realtime, test_sched_rr_get_interval)
+{
+	struct timespec interval = {
+		.tv_sec = 0,
+		.tv_nsec = 0,
+	};
+	int rc = sched_rr_get_interval(0, &interval);
+	int err = errno;
+
+	zassert_true((rc == -1 && err == ENOSYS));
+}
+
+ZTEST_SUITE(xsi_realtime, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/posix/common/src/mqueue.c b/tests/posix/xsi_realtime/src/mqueue.c
similarity index 82%
rename from tests/posix/common/src/mqueue.c
rename to tests/posix/xsi_realtime/src/mqueue.c
index ddf14c7a027..ae1f7c3d3f8 100644
--- a/tests/posix/common/src/mqueue.c
+++ b/tests/posix/xsi_realtime/src/mqueue.c
@@ -13,7 +13,7 @@
 #include <zephyr/ztest.h>
 
 #define N_THR            2
-#define MESSAGE_SIZE 16
+#define MESSAGE_SIZE     16
 #define MESG_COUNT_PERMQ 4
 
 static char queue[16] = "server";
@@ -40,13 +40,11 @@ static void *sender_thread(void *p1)
 	zassert_false(mq_timedsend(mqd, send_data, MESSAGE_SIZE, 0, &curtime),
 		      "Not able to send message in timer");
 	usleep(USEC_PER_MSEC);
-	zassert_false(mq_close(mqd),
-		      "unable to close message queue descriptor.");
+	zassert_false(mq_close(mqd), "unable to close message queue descriptor.");
 	pthread_exit(p1);
 	return NULL;
 }
 
-
 static void *receiver_thread(void *p1)
 {
 	mqd_t mqd;
@@ -59,13 +57,12 @@ static void *receiver_thread(void *p1)
 	zassert_false(strcmp(rec_data, send_data), "Error in data reception. exp: %s act: %s",
 		      send_data, rec_data);
 	usleep(USEC_PER_MSEC);
-	zassert_false(mq_close(mqd),
-		      "unable to close message queue descriptor.");
+	zassert_false(mq_close(mqd), "unable to close message queue descriptor.");
 	pthread_exit(p1);
 	return NULL;
 }
 
-ZTEST(mqueue, test_mqueue)
+ZTEST(xsi_realtime, test_mqueue)
 {
 	mqd_t mqd;
 	struct mq_attr attrs;
@@ -91,8 +88,7 @@ ZTEST(mqueue, test_mqueue)
 		pthread_join(newthread[i], &retval);
 	}
 
-	zassert_false(mq_close(mqd),
-		      "unable to close message queue descriptor.");
+	zassert_false(mq_close(mqd), "unable to close message queue descriptor.");
 	zassert_false(mq_unlink(queue), "Not able to unlink Queue");
 }
 
@@ -106,15 +102,15 @@ void notify_function_basic(union sigval val)
 	mqd = mq_open(queue, O_RDONLY);
 
 	mq_receive(mqd, rec_data, MESSAGE_SIZE, 0);
-	zassert_ok(strcmp(rec_data, send_data),
-		   "Error in data reception. exp: %s act: %s", send_data, rec_data);
+	zassert_ok(strcmp(rec_data, send_data), "Error in data reception. exp: %s act: %s",
+		   send_data, rec_data);
 
 	zassert_ok(mq_close(mqd), "Unable to close message queue descriptor.");
 
 	*executed = true;
 }
 
-ZTEST(mqueue, test_mqueue_notify_basic)
+ZTEST(xsi_realtime, test_mqueue_notify_basic)
 {
 	mqd_t mqd;
 	struct mq_attr attrs = {
@@ -155,15 +151,15 @@ void notify_function_thread(union sigval val)
 	mqd = mq_open(queue, O_RDONLY);
 
 	mq_receive(mqd, rec_data, MESSAGE_SIZE, 0);
-	zassert_ok(strcmp(rec_data, send_data),
-		   "Error in data reception. exp: %s act: %s", send_data, rec_data);
+	zassert_ok(strcmp(rec_data, send_data), "Error in data reception. exp: %s act: %s",
+		   send_data, rec_data);
 
 	zassert_ok(mq_close(mqd), "Unable to close message queue descriptor.");
 
 	notification_executed = true;
 }
 
-ZTEST(mqueue, test_mqueue_notify_thread)
+ZTEST(xsi_realtime, test_mqueue_notify_thread)
 {
 	mqd_t mqd;
 	struct mq_attr attrs = {
@@ -195,7 +191,7 @@ ZTEST(mqueue, test_mqueue_notify_thread)
 	zassert_ok(mq_unlink(queue), "Unable to unlink queue");
 }
 
-ZTEST(mqueue, test_mqueue_notify_non_empty_queue)
+ZTEST(xsi_realtime, test_mqueue_notify_non_empty_queue)
 {
 	mqd_t mqd;
 	struct mq_attr attrs = {
@@ -222,8 +218,8 @@ ZTEST(mqueue, test_mqueue_notify_non_empty_queue)
 	zassert_false(notification_executed, "Notification shouldn't be processed.");
 
 	mq_receive(mqd, rec_data, MESSAGE_SIZE, 0);
-	zassert_false(strcmp(rec_data, send_data),
-		      "Error in data reception. exp: %s act: %s", send_data, rec_data);
+	zassert_false(strcmp(rec_data, send_data), "Error in data reception. exp: %s act: %s",
+		      send_data, rec_data);
 
 	memset(rec_data, 0, MESSAGE_SIZE);
 
@@ -235,7 +231,7 @@ ZTEST(mqueue, test_mqueue_notify_non_empty_queue)
 	zassert_ok(mq_unlink(queue), "Unable to unlink queue");
 }
 
-ZTEST(mqueue, test_mqueue_notify_errors)
+ZTEST(xsi_realtime, test_mqueue_notify_errors)
 {
 	mqd_t mqd;
 	struct mq_attr attrs = {
@@ -276,14 +272,28 @@ ZTEST(mqueue, test_mqueue_notify_errors)
 	zassert_ok(mq_unlink(queue), "Unable to unlink queue");
 }
 
-static void before(void *arg)
+ZTEST(xsi_realtime, test_mqueue_open_and_unlink_multiple)
 {
-	ARG_UNUSED(arg);
+	const char *q1 = "q1";
+	const char *q2 = "q2";
 
-	if (!IS_ENABLED(CONFIG_DYNAMIC_THREAD)) {
-		/* skip redundant testing if there is no thread pool / heap allocation */
-		ztest_test_skip();
-	}
-}
+	mqd_t mqd1, mqd2;
+	struct mq_attr attrs = {
+		.mq_msgsize = MESSAGE_SIZE,
+		.mq_maxmsg = MESG_COUNT_PERMQ,
+	};
+
+	int32_t mode = 0600;
+	int flags = O_RDWR | O_CREAT;
+
+	mqd1 = mq_open(q1, flags, mode, &attrs);
 
-ZTEST_SUITE(mqueue, NULL, NULL, before, NULL, NULL);
+	zassert_ok(mq_unlink(q1), "Unable to unlink q1");
+
+	mqd2 = mq_open(q2, flags, mode, &attrs);
+
+	zassert_ok(mq_unlink(q2), "Unable to unlink q2");
+
+	zassert_ok(mq_close(mqd1), "Unable to close message queue 1 descriptor.");
+	zassert_ok(mq_close(mqd2), "Unable to close message queue 2 descriptor.");
+}
diff --git a/tests/posix/xsi_realtime/src/shm.c b/tests/posix/xsi_realtime/src/shm.c
new file mode 100644
index 00000000000..170902eeae1
--- /dev/null
+++ b/tests/posix/xsi_realtime/src/shm.c
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2024, Tenstorrent AI ULC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <sys/mman.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/net/socket.h>
+#include <zephyr/posix/fcntl.h>
+#include <zephyr/sys/fdtable.h>
+
+#include <zephyr/ztest.h>
+
+#define SHM_SIZE 8
+
+#define VALID_SHM_PATH     "/foo"
+#define INVALID_SHM_PATH   "foo"
+#define EMPTY_SHM_PATH     ""
+#define TOO_SHORT_SHM_PATH "/"
+
+#define INVALID_MODE 0
+#define VALID_MODE   0666
+
+#define INVALID_FLAGS 0
+#define VALID_FLAGS   (O_RDWR | O_CREAT)
+#define CREATE_FLAGS  VALID_FLAGS
+#define OPEN_FLAGS    (VALID_FLAGS & ~O_CREAT)
+
+/* account for stdin, stdout, stderr */
+#define N (CONFIG_ZVFS_OPEN_MAX - 3)
+
+/* we need to have at least 2 shared memory objects */
+BUILD_ASSERT(N >= 2, "CONFIG_ZVFS_OPEN_MAX must be > 4");
+
+#define S_TYPEISSHM(st) (((st)->st_mode & ZVFS_MODE_IFMT) == ZVFS_MODE_IFSHM)
+
+ZTEST(xsi_realtime, test_shm_open)
+{
+	int ret;
+	int fd[N];
+	struct stat st;
+
+	{
+		/* degenerate error cases */
+		zassert_not_ok(shm_open(NULL, INVALID_FLAGS, INVALID_MODE));
+		zassert_not_ok(shm_open(NULL, INVALID_FLAGS, VALID_MODE));
+		zassert_not_ok(shm_open(NULL, VALID_FLAGS, INVALID_MODE));
+		zassert_not_ok(shm_open(NULL, VALID_FLAGS, VALID_MODE));
+		zassert_not_ok(shm_open(INVALID_SHM_PATH, VALID_FLAGS, VALID_MODE));
+		zassert_not_ok(shm_open(EMPTY_SHM_PATH, VALID_FLAGS, VALID_MODE));
+		zassert_not_ok(shm_open(TOO_SHORT_SHM_PATH, VALID_FLAGS, VALID_MODE));
+		zassert_not_ok(shm_open(VALID_SHM_PATH, INVALID_FLAGS, INVALID_MODE));
+		zassert_not_ok(shm_open(VALID_SHM_PATH, INVALID_FLAGS, VALID_MODE));
+		zassert_not_ok(shm_open(VALID_SHM_PATH, VALID_FLAGS, INVALID_MODE));
+	}
+
+	/* open / close 1 file descriptor referring to VALID_SHM_PATH */
+	fd[0] = shm_open(VALID_SHM_PATH, VALID_FLAGS, VALID_MODE);
+	zassert_true(fd[0] >= 0, "shm_open(%s, %x, %04o) failed: %d", VALID_SHM_PATH, VALID_FLAGS,
+		     VALID_MODE, errno);
+
+	/* should have size 0 and be a shared memory object */
+	zassert_ok(fstat(fd[0], &st));
+	zassert_equal(st.st_size, 0);
+	zassert_true(S_TYPEISSHM(&st));
+
+	/* technically, the order of close / shm_unlink can be reversed too */
+	zassert_ok(close(fd[0]));
+	ret = shm_unlink(VALID_SHM_PATH);
+	zassert_true(ret == 0 || (ret == -1 && errno == ENOENT),
+		     "unexpected return / errno from shm_unlink: %d / %d", ret, errno);
+
+	/* open / close N file descriptors referring to VALID_SHM_PATH */
+	for (size_t i = 0; i < N; ++i) {
+		fd[i] = shm_open(VALID_SHM_PATH, i == 0 ? CREATE_FLAGS : OPEN_FLAGS, VALID_MODE);
+		zassert_true(fd[i] >= 0, "shm_open(%s, %x, %04o) failed: %d", VALID_SHM_PATH,
+			     VALID_FLAGS, VALID_MODE, errno);
+	}
+	zassert_ok(shm_unlink(VALID_SHM_PATH));
+	for (size_t i = N; i > 0; --i) {
+		zassert_ok(close(fd[i - 1]));
+	}
+}
+
+ZTEST(xsi_realtime, test_shm_unlink)
+{
+	int fd;
+
+	{
+		/* degenerate error cases */
+		zassert_not_ok(shm_unlink(NULL));
+		zassert_not_ok(shm_unlink(INVALID_SHM_PATH));
+		zassert_not_ok(shm_unlink(EMPTY_SHM_PATH));
+		zassert_not_ok(shm_unlink(TOO_SHORT_SHM_PATH));
+	}
+
+	/* open / close 1 file descriptor referring to VALID_SHM_PATH */
+	fd = shm_open(VALID_SHM_PATH, VALID_FLAGS, VALID_MODE);
+	zassert_true(fd >= 0, "shm_open(%s, %x, %04o) failed: %d", VALID_SHM_PATH, VALID_FLAGS,
+		     VALID_MODE, errno);
+	/* technically, the order of close / shm_unlink can be reversed too */
+	zassert_ok(close(fd));
+	zassert_ok(shm_unlink(VALID_SHM_PATH));
+	/* should not be able to re-open the same path without O_CREAT */
+	zassert_not_ok(shm_open(VALID_SHM_PATH, OPEN_FLAGS, VALID_MODE));
+}
+
+ZTEST(xsi_realtime, test_shm_read_write)
+{
+	int fd[N];
+
+	for (size_t i = 0; i < N; ++i) {
+		char cbuf = 0xff;
+
+		fd[i] = shm_open(VALID_SHM_PATH, i == 0 ? CREATE_FLAGS : OPEN_FLAGS, VALID_MODE);
+		zassert_true(fd[i] >= 0, "shm_open(%s, %x, %04o) failed: %d", VALID_SHM_PATH,
+			     VALID_FLAGS, VALID_MODE, errno);
+		if (i == 0) {
+			/* size 0 on create / zero characters written */
+			zassert_equal(write(fd[0], "", 1), 0,
+				      "write() should fail on newly create shm fd with size 0");
+			/* size 0 on create / zero characters read */
+			zassert_equal(read(fd[0], &cbuf, 1), 0,
+				      "read() should fail on newly create shm fd with size 0");
+
+			BUILD_ASSERT(SHM_SIZE >= 1);
+			zassert_ok(ftruncate(fd[0], SHM_SIZE));
+
+			zassert_equal(write(fd[0], "\x42", 1), 1, "write() failed on fd %d: %d\n",
+				      fd[0], errno);
+
+			continue;
+		}
+
+		zassert_equal(read(fd[i], &cbuf, 1), 1, "read() failed on fd %d: %d\n", fd[i],
+			      errno);
+		zassert_equal(cbuf, 0x42,
+			      "Failed to read byte over fd %d: expected: 0x%02x actual: 0x%02x",
+			      fd[i], 0x42, cbuf);
+	}
+
+	for (size_t i = N; i > 0; --i) {
+		zassert_ok(close(fd[i - 1]));
+	}
+
+	zassert_ok(shm_unlink(VALID_SHM_PATH));
+}
+
+ZTEST(xsi_realtime, test_shm_mmap)
+{
+	int fd[N];
+	void *addr[N];
+
+	if (!IS_ENABLED(CONFIG_MMU)) {
+		ztest_test_skip();
+	}
+
+	for (size_t i = 0; i < N; ++i) {
+		fd[i] = shm_open(VALID_SHM_PATH, i == 0 ? CREATE_FLAGS : OPEN_FLAGS, VALID_MODE);
+		zassert_true(fd[i] >= 0, "shm_open(%s, %x, %04o) failed : %d", VALID_SHM_PATH,
+			     VALID_FLAGS, VALID_MODE, errno);
+
+		if (i == 0) {
+			/* cannot map shm of size zero */
+			zassert_not_ok(mmap(NULL, PAGE_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED,
+					    fd[0], 0));
+
+			zassert_ok(ftruncate(fd[0], PAGE_SIZE));
+		}
+
+		addr[i] = mmap(NULL, PAGE_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, fd[i], 0);
+		zassert_not_equal(MAP_FAILED, addr[i], "mmap() failed: %d", errno);
+
+		if ((i & 1) == 0) {
+			memset(addr[0], i & 0xff, PAGE_SIZE);
+		} else {
+			zassert_mem_equal(addr[i], addr[i - 1], PAGE_SIZE);
+		}
+	}
+
+	for (size_t i = N; i > 0; --i) {
+		zassert_ok(close(fd[i - 1]));
+	}
+
+	for (size_t i = N; i > 0; --i) {
+		zassert_ok(munmap(addr[i - 1], PAGE_SIZE));
+		/*
+		 * Note: for some reason, in Zephyr, unmapping a physical page once, removes all
+		 * virtual mappings. When that behaviour changes, remove the break below and adjust
+		 * shm.c accordingly.
+		 */
+		break;
+	}
+
+	zassert_ok(shm_unlink(VALID_SHM_PATH));
+}
diff --git a/tests/posix/xsi_realtime/src/sync_io.c b/tests/posix/xsi_realtime/src/sync_io.c
new file mode 100644
index 00000000000..09593dbb750
--- /dev/null
+++ b/tests/posix/xsi_realtime/src/sync_io.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2018 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include <fcntl.h>
+#include <ff.h>
+#include <zephyr/fs/fs.h>
+#include <zephyr/posix/unistd.h>
+#include <zephyr/ztest.h>
+
+static const char test_str[] = "Hello World!";
+
+#define FATFS_MNTP "/RAM:"
+#define TEST_FILE  FATFS_MNTP "/testfile.txt"
+
+static FATFS fat_fs;
+
+static struct fs_mount_t fatfs_mnt = {
+	.type = FS_FATFS,
+	.mnt_point = FATFS_MNTP,
+	.fs_data = &fat_fs,
+};
+
+static void test_mount(void)
+{
+	int res;
+
+	res = fs_mount(&fatfs_mnt);
+	zassert_ok(res, "Error mounting fs [%d]\n", res);
+}
+
+void test_unmount(void)
+{
+	int res;
+
+	res = fs_unmount(&fatfs_mnt);
+	zassert_ok(res, "Error unmounting fs [%d]", res);
+}
+
+static int file_open(void)
+{
+	int res;
+
+	res = open(TEST_FILE, O_CREAT | O_RDWR, 0660);
+	zassert_not_equal(res, -1, "Error opening file [%d], errno [%d]", res, errno);
+	return res;
+}
+
+static int file_write(int file)
+{
+	ssize_t brw;
+	off_t res;
+
+	res = lseek(file, 0, SEEK_SET);
+	zassert_ok((int)res, "lseek failed [%d]\n", (int)res);
+
+	brw = write(file, (char *)test_str, strlen(test_str));
+	zassert_ok((int)res, "Failed writing to file [%d]\n", (int)brw);
+
+	zassert_ok(brw < strlen(test_str),
+		   "Unable to complete write. Volume full. Number of bytes written: [%d]\n",
+		   (int)brw);
+	return res;
+}
+
+/**
+ * @brief Test for POSIX fsync API
+ *
+ * @details Test sync the file through POSIX fsync API.
+ */
+ZTEST(xsi_realtime, test_fs_sync)
+{
+	test_mount();
+	int res = 0;
+	int file = file_open();
+
+	res = file_write(file);
+	res = fsync(file);
+	zassert_ok(res, "Failed to sync file: %d, errno = %d\n", res, errno);
+	zassert_ok(close(file), "Failed to close file");
+	test_unmount();
+}
+
+/**
+ * @brief Test for POSIX fdatasync API
+ *
+ * @details Test sync the file through POSIX fdatasync API.
+ */
+ZTEST(xsi_realtime, test_fs_datasync)
+{
+	test_mount();
+	int res = 0;
+	int file = file_open();
+
+	res = file_write(file);
+	res = fdatasync(file);
+	zassert_ok(res, "Failed to sync file: %d, errno = %d\n", res, errno);
+	zassert_ok(close(file), "Failed to close file");
+	test_unmount();
+}
diff --git a/tests/posix/xsi_realtime/testcase.yaml b/tests/posix/xsi_realtime/testcase.yaml
new file mode 100644
index 00000000000..f084983c38b
--- /dev/null
+++ b/tests/posix/xsi_realtime/testcase.yaml
@@ -0,0 +1,31 @@
+common:
+  filter: not CONFIG_NATIVE_LIBC
+  tags:
+    - posix
+    - xsi_realtime
+  # 1 tier0 platform per supported architecture
+  platform_key:
+    - arch
+    - simulation
+  min_flash: 64
+  min_ram: 32
+  timeout: 240
+  platform_exclude:
+    # linker_zephyr_pre0.cmd:140: syntax error (??)
+    - qemu_xtensa/dc233c
+    - native_sim
+    - native_sim/native/64
+tests:
+  portability.posix.xsi_realtime: {}
+  portability.posix.xsi_realtime.minimal:
+    extra_configs:
+      - CONFIG_MINIMAL_LIBC=y
+  portability.posix.xsi_realtime.newlib:
+    filter: TOOLCHAIN_HAS_NEWLIB == 1
+    extra_configs:
+      - CONFIG_NEWLIB_LIBC=y
+  portability.posix.xsi_realtime.picolibc:
+    tags: picolibc
+    filter: CONFIG_PICOLIBC_SUPPORTED
+    extra_configs:
+      - CONFIG_PICOLIBC=y
diff --git a/tests/posix/xsi_streams/testcase.yaml b/tests/posix/xsi_streams/testcase.yaml
index c0395960827..06b40f1c2e8 100644
--- a/tests/posix/xsi_streams/testcase.yaml
+++ b/tests/posix/xsi_streams/testcase.yaml
@@ -7,6 +7,8 @@ common:
   platform_key:
     - arch
     - simulation
+  integration_platforms:
+    - qemu_riscv64
   min_flash: 64
   min_ram: 32
 tests:
diff --git a/tests/posix/xsi_system_logging/testcase.yaml b/tests/posix/xsi_system_logging/testcase.yaml
index 352cfffce42..54d6790ae75 100644
--- a/tests/posix/xsi_system_logging/testcase.yaml
+++ b/tests/posix/xsi_system_logging/testcase.yaml
@@ -6,6 +6,8 @@ common:
   platform_key:
     - arch
     - simulation
+  integration_platforms:
+    - qemu_riscv64
   min_flash: 64
   min_ram: 32
 tests:
diff --git a/tests/robot/common.robot b/tests/robot/common.robot
index 2bebe955797..b8099de25da 100644
--- a/tests/robot/common.robot
+++ b/tests/robot/common.robot
@@ -4,4 +4,5 @@
 Prepare Machine
     Execute Command           $elf = ${ELF}
     Execute Command           include ${RESC}
-    Create Terminal Tester    ${UART}
+    Create Terminal Tester    ${UART}  defaultPauseEmulation=True
+    Write Char Delay          0.01
diff --git a/tests/subsys/bindesc/reading/testcase.yaml b/tests/subsys/bindesc/reading/testcase.yaml
index 76fdaa78e80..94a00642d2f 100644
--- a/tests/subsys/bindesc/reading/testcase.yaml
+++ b/tests/subsys/bindesc/reading/testcase.yaml
@@ -7,7 +7,6 @@ common:
 tests:
   bindesc.read:
     platform_allow:
-      - native_posix
       - native_sim
   bindesc.read.c99:
     extra_configs:
diff --git a/tests/subsys/debug/coredump/src/main.c b/tests/subsys/debug/coredump/src/main.c
index 0deda7e032f..0d891df331d 100644
--- a/tests/subsys/debug/coredump/src/main.c
+++ b/tests/subsys/debug/coredump/src/main.c
@@ -40,7 +40,8 @@ __no_optimization void func_3(uint32_t *addr)
 	defined(CONFIG_BOARD_QEMU_XTENSA) || \
 	defined(CONFIG_BOARD_RISCV32_VIRTUAL) || \
 	defined(CONFIG_SOC_FAMILY_INTEL_ISH) || \
-	defined(CONFIG_SOC_FAMILY_INTEL_ADSP)
+	defined(CONFIG_SOC_FAMILY_INTEL_ADSP) || \
+	defined(CONFIG_SOC_FAMILY_OPENHWGROUP_CVA6)
 	ARG_UNUSED(addr);
 	/* Call k_panic() directly so Renode doesn't pause execution.
 	 * Needed on ADSP as well, since null pointer derefence doesn't
diff --git a/tests/subsys/debug/coredump_backends/prj_in_memory.conf b/tests/subsys/debug/coredump_backends/prj_in_memory.conf
new file mode 100644
index 00000000000..6ed3d0fb780
--- /dev/null
+++ b/tests/subsys/debug/coredump_backends/prj_in_memory.conf
@@ -0,0 +1,7 @@
+CONFIG_ZTEST=y
+CONFIG_LOG=y
+CONFIG_LOG_MODE_MINIMAL=y
+CONFIG_DEBUG_COREDUMP=y
+CONFIG_DEBUG_COREDUMP_BACKEND_IN_MEMORY=y
+CONFIG_DEBUG_COREDUMP_BACKEND_IN_MEMORY_SIZE=2048
+CONFIG_DEBUG_COREDUMP_MEMORY_DUMP_MIN=y
diff --git a/tests/subsys/debug/coredump_backends/testcase.yaml b/tests/subsys/debug/coredump_backends/testcase.yaml
index ff4109f9d50..f97fa817398 100644
--- a/tests/subsys/debug/coredump_backends/testcase.yaml
+++ b/tests/subsys/debug/coredump_backends/testcase.yaml
@@ -24,6 +24,11 @@ tests:
       - esp32s2_saola
       - esp32s3_devkitm/esp32s3/procpu
       - esp32c3_devkitm
+  debug.coredump.backends.in_memory:
+    filter: CONFIG_ARCH_SUPPORTS_COREDUMP
+    extra_args: CONF_FILE=prj_in_memory.conf
+    extra_configs:
+      - CONFIG_TEST_STORED_COREDUMP=y
   debug.coredump.backends.other:
     filter: CONFIG_ARCH_SUPPORTS_COREDUMP
     extra_args: CONF_FILE=prj_backend_other.conf
diff --git a/tests/subsys/debug/cpu_load/CMakeLists.txt b/tests/subsys/debug/cpu_load/CMakeLists.txt
new file mode 100644
index 00000000000..8c9bd0d2e75
--- /dev/null
+++ b/tests/subsys/debug/cpu_load/CMakeLists.txt
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(debug_cpu_load)
+
+target_sources(app PRIVATE src/main.c)
diff --git a/tests/subsys/debug/cpu_load/boards/nrf52840dk_nrf52840.overlay b/tests/subsys/debug/cpu_load/boards/nrf52840dk_nrf52840.overlay
new file mode 100644
index 00000000000..1f631ba1587
--- /dev/null
+++ b/tests/subsys/debug/cpu_load/boards/nrf52840dk_nrf52840.overlay
@@ -0,0 +1,10 @@
+/ {
+	chosen {
+		zephyr,cpu-load-counter = &timer0;
+	};
+};
+
+&timer0 {
+	status = "okay";
+	prescaler = <0>;
+};
diff --git a/tests/subsys/debug/cpu_load/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/subsys/debug/cpu_load/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
new file mode 100644
index 00000000000..c60ec9ea5aa
--- /dev/null
+++ b/tests/subsys/debug/cpu_load/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
@@ -0,0 +1,10 @@
+/ {
+	chosen {
+		zephyr,cpu-load-counter = &timer130;
+	};
+};
+
+&timer130 {
+	status = "okay";
+	prescaler = <0>;
+};
diff --git a/tests/subsys/debug/cpu_load/prj.conf b/tests/subsys/debug/cpu_load/prj.conf
new file mode 100644
index 00000000000..a194a84c710
--- /dev/null
+++ b/tests/subsys/debug/cpu_load/prj.conf
@@ -0,0 +1,3 @@
+CONFIG_ZTEST=y
+CONFIG_CPU_LOAD=y
+CONFIG_CPU_LOAD_USE_COUNTER=n
diff --git a/tests/subsys/debug/cpu_load/src/main.c b/tests/subsys/debug/cpu_load/src/main.c
new file mode 100644
index 00000000000..ab8efc86b95
--- /dev/null
+++ b/tests/subsys/debug/cpu_load/src/main.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2024, Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/debug/cpu_load.h>
+#include <zephyr/ztest.h>
+#include <zephyr/logging/log_ctrl.h>
+#include <zephyr/logging/log_backend.h>
+
+#include <zephyr/drivers/counter.h>
+
+#define DELTA 30
+
+ZTEST(cpu_load, test_load)
+{
+	int load;
+	uint32_t t_ms = 100;
+
+	if (CONFIG_CPU_LOAD_LOG_PERIODICALLY > 0) {
+		cpu_load_log_control(false);
+	}
+
+	/* Reset the measurement */
+	(void)cpu_load_get(true);
+	k_busy_wait(t_ms * USEC_PER_MSEC);
+
+	/* Measurement is not reset. */
+	load = cpu_load_get(false);
+	/* Result in per mille */
+	zassert_within(load, 1000, DELTA);
+
+	k_msleep(t_ms);
+	load = cpu_load_get(false);
+	zassert_within(load, 500, DELTA);
+
+	/* Reset the measurement */
+	(void)cpu_load_get(true);
+	k_msleep(t_ms);
+	load = cpu_load_get(false);
+	zassert_within(load, 0, DELTA);
+}
+
+#if CONFIG_CPU_LOAD_LOG_PERIODICALLY > 0
+static int cpu_load_src_id;
+static atomic_t log_cnt;
+
+static void process(const struct log_backend *const backend,
+		union log_msg_generic *msg)
+{
+	ARG_UNUSED(backend);
+	const void *source = msg->log.hdr.source;
+	int source_id = log_const_source_id((const struct log_source_const_data *)source);
+
+	if (source_id == cpu_load_src_id) {
+		atomic_inc(&log_cnt);
+	}
+}
+
+static void init(const struct log_backend *const backend)
+{
+	ARG_UNUSED(backend);
+}
+
+const struct log_backend_api mock_log_backend_api = {
+	.process = process,
+	.init = init
+};
+
+LOG_BACKEND_DEFINE(dummy, mock_log_backend_api, false, NULL);
+
+ZTEST(cpu_load, test_periodic_report)
+{
+	log_backend_enable(&dummy, NULL, LOG_LEVEL_INF);
+	cpu_load_log_control(true);
+
+	cpu_load_src_id = log_source_id_get(STRINGIFY(cpu_load));
+	atomic_set(&log_cnt, 0);
+	k_msleep(3 * CONFIG_CPU_LOAD_LOG_PERIODICALLY);
+	zassert_within(log_cnt, 3, 1);
+
+	cpu_load_log_control(false);
+	k_msleep(1);
+	atomic_set(&log_cnt, 0);
+	k_msleep(3 * CONFIG_CPU_LOAD_LOG_PERIODICALLY);
+	zassert_equal(log_cnt, 0);
+
+	cpu_load_log_control(true);
+	k_msleep(3 * CONFIG_CPU_LOAD_LOG_PERIODICALLY);
+	zassert_within(log_cnt, 3, 1);
+
+	cpu_load_log_control(false);
+	log_backend_disable(&dummy);
+}
+#endif /* CONFIG_CPU_LOAD_LOG_PERIODICALLY > 0 */
+
+ZTEST_SUITE(cpu_load, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/subsys/debug/cpu_load/testcase.yaml b/tests/subsys/debug/cpu_load/testcase.yaml
new file mode 100644
index 00000000000..a3e310230b6
--- /dev/null
+++ b/tests/subsys/debug/cpu_load/testcase.yaml
@@ -0,0 +1,28 @@
+common:
+  tags: cpu_load
+  arch_allow:
+    - arm
+    - riscv
+  filter: CONFIG_CPU_LOAD
+tests:
+  debug.cpu_load:
+    integration_platforms:
+      - mps2/an385
+  debug.cpu_load.counter:
+    platform_allow:
+      - nrf52840dk/nrf52840
+      - nrf54h20dk/nrf54h20/cpuapp
+    integration_platforms:
+      - nrf52840dk/nrf52840
+    extra_configs:
+      - CONFIG_CPU_LOAD_USE_COUNTER=y
+  debug.cpu_load.periodic_report:
+    integration_platforms:
+      - mps2/an385
+    extra_configs:
+      - CONFIG_CPU_LOAD_LOG_PERIODICALLY=50
+      - CONFIG_LOG=y
+      - CONFIG_TEST_LOGGING_DEFAULTS=n
+      - CONFIG_LOG_PRINTK=n
+      - CONFIG_LOG_BACKEND_UART=n
+      - CONFIG_LOG_MODE_IMMEDIATE=y
diff --git a/tests/subsys/dfu/img_util/testcase.yaml b/tests/subsys/dfu/img_util/testcase.yaml
index 0c280a29ae7..7924f447c59 100644
--- a/tests/subsys/dfu/img_util/testcase.yaml
+++ b/tests/subsys/dfu/img_util/testcase.yaml
@@ -4,7 +4,7 @@ common:
     - native_sim
     - native_sim/native/64
   integration_platforms:
-    - nrf52840dk/nrf52840
+    - native_sim
 tests:
   dfu.image_util:
     tags: dfu_image_util
diff --git a/tests/subsys/dfu/mcuboot/testcase.yaml b/tests/subsys/dfu/mcuboot/testcase.yaml
index b8d05692a27..5e95f708bba 100644
--- a/tests/subsys/dfu/mcuboot/testcase.yaml
+++ b/tests/subsys/dfu/mcuboot/testcase.yaml
@@ -6,4 +6,4 @@ tests:
       - native_sim/native/64
     tags: dfu_mcuboot
     integration_platforms:
-      - nrf52840dk/nrf52840
+      - native_sim
diff --git a/tests/subsys/dfu/mcuboot_multi/testcase.yaml b/tests/subsys/dfu/mcuboot_multi/testcase.yaml
index 5ded74912ab..30a144424c0 100644
--- a/tests/subsys/dfu/mcuboot_multi/testcase.yaml
+++ b/tests/subsys/dfu/mcuboot_multi/testcase.yaml
@@ -6,4 +6,4 @@ tests:
       - native_sim/native/64
     tags: dfu_mcuboot
     integration_platforms:
-      - nrf52840dk/nrf52840
+      - native_sim
diff --git a/tests/subsys/fs/ext2/ramdisk_small.overlay b/tests/subsys/fs/ext2/ramdisk_small.overlay
index 8a4d7708a80..dba1a41c8f2 100644
--- a/tests/subsys/fs/ext2/ramdisk_small.overlay
+++ b/tests/subsys/fs/ext2/ramdisk_small.overlay
@@ -9,6 +9,6 @@
 		compatible = "zephyr,ram-disk";
 		disk-name = "RAM";
 		sector-size = <512>;
-		sector-count = <400>;
+		sector-count = <220>;
 	};
 };
diff --git a/tests/subsys/fs/fat_fs_api/prj_native_ram.conf b/tests/subsys/fs/fat_fs_api/prj_native_ram.conf
index 4403579767f..223c34dde5a 100644
--- a/tests/subsys/fs/fat_fs_api/prj_native_ram.conf
+++ b/tests/subsys/fs/fat_fs_api/prj_native_ram.conf
@@ -6,3 +6,4 @@ CONFIG_ZTEST=y
 CONFIG_FLASH=y
 CONFIG_FLASH_MAP=y
 CONFIG_DISK_DRIVER_FLASH=n
+CONFIG_MAIN_STACK_SIZE=3072
diff --git a/tests/subsys/fs/fat_fs_api/src/common.c b/tests/subsys/fs/fat_fs_api/src/common.c
index 348aa8442e8..b4aff636535 100644
--- a/tests/subsys/fs/fat_fs_api/src/common.c
+++ b/tests/subsys/fs/fat_fs_api/src/common.c
@@ -89,6 +89,10 @@ int wipe_partition(void)
 		return TC_FAIL;
 	}
 
+	if (sector_count > 64) {
+		/* partition only in first 32k */
+		sector_count = 64;
+	}
 	sector_wr_size = MIN(sector_size, ARRAY_SIZE(erase_buffer));
 	sector_wr_jmp = sector_wr_size / sector_wr_size;
 	TC_PRINT("For "DISK_NAME" using sector write size %"PRIu32" to write %"PRIu32" at once\n",
diff --git a/tests/subsys/fs/fcb/testcase.yaml b/tests/subsys/fs/fcb/testcase.yaml
index 53a61c3651e..c8351b8dcf2 100644
--- a/tests/subsys/fs/fcb/testcase.yaml
+++ b/tests/subsys/fs/fcb/testcase.yaml
@@ -9,12 +9,17 @@ tests:
       - mr_canhubk3
     tags: flash_circural_buffer
     integration_platforms:
-      - nrf52840dk/nrf52840
+      - native_sim
   filesystem.fcb.no_erase:
     platform_allow:
       - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
       - nrf54l20pdk/nrf54l20/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
+      - native_sim
+    integration_platforms:
+      - nrf54l09pdk/nrf54l09/cpuapp
+      - native_sim
   filesystem.fcb.native_sim.no_erase:
     extra_args: CONFIG_FLASH_SIMULATOR_EXPLICIT_ERASE=n
     platform_allow: native_sim
@@ -28,7 +33,7 @@ tests:
       - mr_canhubk3
     tags: flash_circural_buffer
     integration_platforms:
-      - nrf52840dk/nrf52840
+      - native_sim
     extra_args: CONFIG_FCB_ALLOW_FIXED_ENDMARKER=y
   filesystem.fcb.native_sim.fcb_0x00:
     extra_args: DTC_OVERLAY_FILE=boards/native_sim_ev_0x00.overlay
diff --git a/tests/subsys/fs/lib_link/CMakeLists.txt b/tests/subsys/fs/lib_link/CMakeLists.txt
new file mode 100644
index 00000000000..e711464c317
--- /dev/null
+++ b/tests/subsys/fs/lib_link/CMakeLists.txt
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(fs_lib_link)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/subsys/fs/lib_link/app.overlay b/tests/subsys/fs/lib_link/app.overlay
new file mode 100644
index 00000000000..bdff6e4da08
--- /dev/null
+++ b/tests/subsys/fs/lib_link/app.overlay
@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2023 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	ramdisk0 {
+		compatible = "zephyr,ram-disk";
+		disk-name = "RAM";
+		sector-size = <512>;
+		sector-count = <80>;
+	};
+};
diff --git a/tests/subsys/fs/lib_link/prj.conf b/tests/subsys/fs/lib_link/prj.conf
new file mode 100644
index 00000000000..54365b51969
--- /dev/null
+++ b/tests/subsys/fs/lib_link/prj.conf
@@ -0,0 +1,5 @@
+CONFIG_FILE_SYSTEM_LIB_LINK=y
+CONFIG_FAT_FILESYSTEM_ELM=y
+CONFIG_FILE_SYSTEM_LITTLEFS=y
+CONFIG_FILE_SYSTEM_EXT2=y
+CONFIG_ZTEST=y
diff --git a/tests/subsys/fs/lib_link/src/main.c b/tests/subsys/fs/lib_link/src/main.c
new file mode 100644
index 00000000000..1b019a25d9b
--- /dev/null
+++ b/tests/subsys/fs/lib_link/src/main.c
@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2025 Embeint Inc
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+#include <zephyr/ztest.h>
+
+ZTEST_SUITE(lib_link, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/subsys/fs/lib_link/testcase.yaml b/tests/subsys/fs/lib_link/testcase.yaml
new file mode 100644
index 00000000000..749f681927e
--- /dev/null
+++ b/tests/subsys/fs/lib_link/testcase.yaml
@@ -0,0 +1,5 @@
+tests:
+  filesystem.lib_link:
+    tags: filesystem
+    integration_platforms:
+      - native_sim
diff --git a/tests/subsys/fs/littlefs/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay b/tests/subsys/fs/littlefs/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..31e324265bc
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/bl54l15_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &slot0_ns_partition;
+/delete-node/ &slot1_partition;
+/delete-node/ &slot1_ns_partition;
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		small_partition: partition@67000 {
+			label = "small";
+			reg = <0x00067000 0x00010000>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay b/tests/subsys/fs/littlefs/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..31e324265bc
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/bl54l15u_dvk_nrf54l15_cpuapp.overlay
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2025 Ezurio LLC
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &slot0_ns_partition;
+/delete-node/ &slot1_partition;
+/delete-node/ &slot1_ns_partition;
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		small_partition: partition@67000 {
+			label = "small";
+			reg = <0x00067000 0x00010000>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/frdm_mcxa156.conf b/tests/subsys/fs/littlefs/boards/frdm_mcxa156.conf
new file mode 100644
index 00000000000..ace2fd7382b
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/frdm_mcxa156.conf
@@ -0,0 +1,5 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_FS_LITTLEFS_PROG_SIZE=128
+CONFIG_FS_LITTLEFS_CACHE_SIZE=256
diff --git a/tests/subsys/fs/littlefs/boards/frdm_mcxa156.overlay b/tests/subsys/fs/littlefs/boards/frdm_mcxa156.overlay
new file mode 100644
index 00000000000..c5d1289e805
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/frdm_mcxa156.overlay
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&flash {
+	partitions {
+		small_partition: partition@E0000 {
+			label = "small";
+			reg = <0x000E0000 DT_SIZE_K(128)>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/frdm_mcxn236.conf b/tests/subsys/fs/littlefs/boards/frdm_mcxn236.conf
new file mode 100644
index 00000000000..a2c4bf5521a
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/frdm_mcxn236.conf
@@ -0,0 +1,5 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_FS_LITTLEFS_PROG_SIZE=128
+CONFIG_FS_LITTLEFS_CACHE_SIZE=128
diff --git a/tests/subsys/fs/littlefs/boards/frdm_mcxn236.overlay b/tests/subsys/fs/littlefs/boards/frdm_mcxn236.overlay
new file mode 100644
index 00000000000..c5d1289e805
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/frdm_mcxn236.overlay
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&flash {
+	partitions {
+		small_partition: partition@E0000 {
+			label = "small";
+			reg = <0x000E0000 DT_SIZE_K(128)>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/frdm_mcxn947_mcxn947_cpu0.overlay b/tests/subsys/fs/littlefs/boards/frdm_mcxn947_mcxn947_cpu0.overlay
new file mode 100644
index 00000000000..06de3593398
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/frdm_mcxn947_mcxn947_cpu0.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&w25q64jvssiq {
+	partitions {
+		large_partition: partition@400000 {
+			label = "large";
+			reg = <0x00400000 DT_SIZE_M(3)>;
+		};
+		medium_partition: partition@700000 {
+			label = "medium";
+			reg = <0x00700000 DT_SIZE_K(960)>;
+		};
+		small_partition: partition@7F0000 {
+			label = "small";
+			reg = <0x007F0000 DT_SIZE_K(64)>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/frdm_mcxw71.overlay b/tests/subsys/fs/littlefs/boards/frdm_mcxw71.overlay
new file mode 100644
index 00000000000..c5d1289e805
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/frdm_mcxw71.overlay
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&flash {
+	partitions {
+		small_partition: partition@E0000 {
+			label = "small";
+			reg = <0x000E0000 DT_SIZE_K(128)>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/frdm_rw612.overlay b/tests/subsys/fs/littlefs/boards/frdm_rw612.overlay
new file mode 100644
index 00000000000..df18bc7ad70
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/frdm_rw612.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&w25q512jvfiq {
+	partitions {
+		large_partition: partition@3C00000 {
+			label = "large";
+			reg = <0x03C00000 DT_SIZE_M(3)>;
+		};
+		medium_partition: partition@3F00000 {
+			label = "medium";
+			reg = <0x03F00000 DT_SIZE_K(960)>;
+		};
+		small_partition: partition@3FF0000 {
+			label = "small";
+			reg = <0x03FF0000 DT_SIZE_K(64)>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/lpcxpresso55s06.conf b/tests/subsys/fs/littlefs/boards/lpcxpresso55s06.conf
new file mode 100644
index 00000000000..d420a2072a4
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/lpcxpresso55s06.conf
@@ -0,0 +1,5 @@
+# Copyright 2023 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_FS_LITTLEFS_PROG_SIZE=512
+CONFIG_FS_LITTLEFS_CACHE_SIZE=512
diff --git a/tests/subsys/fs/littlefs/boards/lpcxpresso55s06.overlay b/tests/subsys/fs/littlefs/boards/lpcxpresso55s06.overlay
new file mode 100644
index 00000000000..000a49903c5
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/lpcxpresso55s06.overlay
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&flash0 {
+	 partitions {
+		 small_partition: partition@1D000 {
+			 label = "small";
+			 reg = <0x0001D000 DT_SIZE_K(128)>;
+		 };
+	 };
+};
diff --git a/tests/subsys/fs/littlefs/boards/lpcxpresso55s16.conf b/tests/subsys/fs/littlefs/boards/lpcxpresso55s16.conf
new file mode 100644
index 00000000000..d420a2072a4
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/lpcxpresso55s16.conf
@@ -0,0 +1,5 @@
+# Copyright 2023 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_FS_LITTLEFS_PROG_SIZE=512
+CONFIG_FS_LITTLEFS_CACHE_SIZE=512
diff --git a/tests/subsys/fs/littlefs/boards/lpcxpresso55s16.overlay b/tests/subsys/fs/littlefs/boards/lpcxpresso55s16.overlay
new file mode 100644
index 00000000000..000a49903c5
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/lpcxpresso55s16.overlay
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&flash0 {
+	 partitions {
+		 small_partition: partition@1D000 {
+			 label = "small";
+			 reg = <0x0001D000 DT_SIZE_K(128)>;
+		 };
+	 };
+};
diff --git a/tests/subsys/fs/littlefs/boards/lpcxpresso55s28.conf b/tests/subsys/fs/littlefs/boards/lpcxpresso55s28.conf
new file mode 100644
index 00000000000..d420a2072a4
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/lpcxpresso55s28.conf
@@ -0,0 +1,5 @@
+# Copyright 2023 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_FS_LITTLEFS_PROG_SIZE=512
+CONFIG_FS_LITTLEFS_CACHE_SIZE=512
diff --git a/tests/subsys/fs/littlefs/boards/lpcxpresso55s28.overlay b/tests/subsys/fs/littlefs/boards/lpcxpresso55s28.overlay
new file mode 100644
index 00000000000..56e240a5f42
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/lpcxpresso55s28.overlay
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&flash0 {
+	partitions {
+		small_partition: partition@5D000 {
+			label = "small";
+			reg = <0x0005D000 DT_SIZE_K(128)>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/lpcxpresso55s36.conf b/tests/subsys/fs/littlefs/boards/lpcxpresso55s36.conf
new file mode 100644
index 00000000000..d420a2072a4
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/lpcxpresso55s36.conf
@@ -0,0 +1,5 @@
+# Copyright 2023 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_FS_LITTLEFS_PROG_SIZE=512
+CONFIG_FS_LITTLEFS_CACHE_SIZE=512
diff --git a/tests/subsys/fs/littlefs/boards/lpcxpresso55s36.overlay b/tests/subsys/fs/littlefs/boards/lpcxpresso55s36.overlay
new file mode 100644
index 00000000000..d78949bf3dd
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/lpcxpresso55s36.overlay
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&flash0 {
+	 partitions {
+		 small_partition: partition@1D800 {
+			 label = "small";
+			 reg = <0x0001D800 DT_SIZE_K(128)>;
+		 };
+	 };
+};
diff --git a/tests/subsys/fs/littlefs/boards/lpcxpresso55s69_lpc55s69_cpu0.conf b/tests/subsys/fs/littlefs/boards/lpcxpresso55s69_lpc55s69_cpu0.conf
new file mode 100644
index 00000000000..d420a2072a4
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/lpcxpresso55s69_lpc55s69_cpu0.conf
@@ -0,0 +1,5 @@
+# Copyright 2023 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_FS_LITTLEFS_PROG_SIZE=512
+CONFIG_FS_LITTLEFS_CACHE_SIZE=512
diff --git a/tests/subsys/fs/littlefs/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay b/tests/subsys/fs/littlefs/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay
new file mode 100644
index 00000000000..7fb3d1ecbbe
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/lpcxpresso55s69_lpc55s69_cpu0.overlay
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&flash0 {
+	partitions {
+		small_partition: partition@75800 {
+			label = "small";
+			reg = <0x00075800 DT_SIZE_K(128)>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/mimxrt1010_evk.overlay b/tests/subsys/fs/littlefs/boards/mimxrt1010_evk.overlay
new file mode 100644
index 00000000000..658e9bd3194
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/mimxrt1010_evk.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&at25sf128a {
+	partitions {
+		large_partition: partition@C00000 {
+			label = "large";
+			reg = <0x00C00000 DT_SIZE_M(3)>;
+		};
+		medium_partition: partition@F00000 {
+			label = "medium";
+			reg = <0x00F00000 DT_SIZE_K(960)>;
+		};
+		small_partition: partition@FF0000 {
+			label = "small";
+			reg = <0x00FF0000 DT_SIZE_K(64)>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/mimxrt1015_evk.overlay b/tests/subsys/fs/littlefs/boards/mimxrt1015_evk.overlay
new file mode 100644
index 00000000000..658e9bd3194
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/mimxrt1015_evk.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&at25sf128a {
+	partitions {
+		large_partition: partition@C00000 {
+			label = "large";
+			reg = <0x00C00000 DT_SIZE_M(3)>;
+		};
+		medium_partition: partition@F00000 {
+			label = "medium";
+			reg = <0x00F00000 DT_SIZE_K(960)>;
+		};
+		small_partition: partition@FF0000 {
+			label = "small";
+			reg = <0x00FF0000 DT_SIZE_K(64)>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/mimxrt1040_evk.overlay b/tests/subsys/fs/littlefs/boards/mimxrt1040_evk.overlay
new file mode 100644
index 00000000000..06de3593398
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/mimxrt1040_evk.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&w25q64jvssiq {
+	partitions {
+		large_partition: partition@400000 {
+			label = "large";
+			reg = <0x00400000 DT_SIZE_M(3)>;
+		};
+		medium_partition: partition@700000 {
+			label = "medium";
+			reg = <0x00700000 DT_SIZE_K(960)>;
+		};
+		small_partition: partition@7F0000 {
+			label = "small";
+			reg = <0x007F0000 DT_SIZE_K(64)>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/mimxrt1050_evk_mimxrt1052_hyperflash.overlay b/tests/subsys/fs/littlefs/boards/mimxrt1050_evk_mimxrt1052_hyperflash.overlay
new file mode 100644
index 00000000000..db2ee713fc6
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/mimxrt1050_evk_mimxrt1052_hyperflash.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&s26ks512s0 {
+	partitions {
+		large_partition: partition@3400000 {
+			label = "large";
+			reg = <0x03400000 DT_SIZE_M(4)>;
+		};
+		medium_partition: partition@3800000 {
+			label = "medium";
+			reg = <0x03800000 DT_SIZE_M(4)>;
+		};
+		small_partition: partition@3C00000 {
+			label = "small";
+			reg = <0x03C00000 DT_SIZE_M(4)>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay b/tests/subsys/fs/littlefs/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay
new file mode 100644
index 00000000000..2d1c660d5f1
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/mimxrt1060_evk_mimxrt1062_qspi_B.overlay
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2021 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&is25wp064 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 DT_SIZE_K(128)>;
+		};
+		slot0_partition: partition@20000 {
+			label = "image-0";
+			reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>;
+		};
+		large_partition: partition@322000 {
+			label = "large";
+			reg = <0x00322000 DT_SIZE_M(3)>;
+		};
+		medium_partition: partition@622000 {
+			label = "medium";
+			reg = <0x00622000 DT_SIZE_K(960)>;
+		};
+		small_partition: partition@712000 {
+			label = "small";
+			reg = <0x00712000 DT_SIZE_K(64)>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay b/tests/subsys/fs/littlefs/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
new file mode 100644
index 00000000000..2d1c660d5f1
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/mimxrt1060_evk_mimxrt1062_qspi_C.overlay
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2021 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&is25wp064 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		boot_partition: partition@0 {
+			label = "mcuboot";
+			reg = <0x00000000 DT_SIZE_K(128)>;
+		};
+		slot0_partition: partition@20000 {
+			label = "image-0";
+			reg = <0x00020000 (DT_SIZE_M(3) + DT_SIZE_K(8))>;
+		};
+		large_partition: partition@322000 {
+			label = "large";
+			reg = <0x00322000 DT_SIZE_M(3)>;
+		};
+		medium_partition: partition@622000 {
+			label = "medium";
+			reg = <0x00622000 DT_SIZE_K(960)>;
+		};
+		small_partition: partition@712000 {
+			label = "small";
+			reg = <0x00712000 DT_SIZE_K(64)>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay b/tests/subsys/fs/littlefs/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
new file mode 100644
index 00000000000..80e28b45735
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/mimxrt1170_evk_mimxrt1176_cm7.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&w25q512nw {
+	partitions {
+		large_partition: partition@3C00000 {
+			label = "large";
+			reg = <0x03C00000 DT_SIZE_M(3)>;
+		};
+		medium_partition: partition@3F00000 {
+			label = "medium";
+			reg = <0x03F00000 DT_SIZE_K(960)>;
+		};
+		small_partition: partition@3FF0000 {
+			label = "small";
+			reg = <0x03FF0000 DT_SIZE_K(64)>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay b/tests/subsys/fs/littlefs/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
new file mode 100644
index 00000000000..7201d45e52b
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/mimxrt1180_evk_mimxrt1189_cm33.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&w25q128jw {
+	partitions {
+		large_partition: partition@C00000 {
+			label = "large";
+			reg = <0x00C00000 DT_SIZE_M(3)>;
+		};
+		medium_partition: partition@F00000 {
+			label = "medium";
+			reg = <0x00F00000 DT_SIZE_K(960)>;
+		};
+		small_partition: partition@FF0000 {
+			label = "small";
+			reg = <0x00FF0000 DT_SIZE_K(64)>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/mimxrt595_evk_mimxrt595s_cm33.overlay b/tests/subsys/fs/littlefs/boards/mimxrt595_evk_mimxrt595s_cm33.overlay
new file mode 100644
index 00000000000..2ac6dd7f4f9
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/mimxrt595_evk_mimxrt595s_cm33.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&mx25um51345g {
+	partitions {
+		large_partition: partition@3C00000 {
+			label = "large";
+			reg = <0x03C00000 DT_SIZE_M(3)>;
+		};
+		medium_partition: partition@3F00000 {
+			label = "medium";
+			reg = <0x03F00000 DT_SIZE_K(960)>;
+		};
+		small_partition: partition@3FF0000 {
+			label = "small";
+			reg = <0x03FF0000 DT_SIZE_K(64)>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/mimxrt685_evk_mimxrt685s_cm33.overlay b/tests/subsys/fs/littlefs/boards/mimxrt685_evk_mimxrt685s_cm33.overlay
new file mode 100644
index 00000000000..2ac6dd7f4f9
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/mimxrt685_evk_mimxrt685s_cm33.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&mx25um51345g {
+	partitions {
+		large_partition: partition@3C00000 {
+			label = "large";
+			reg = <0x03C00000 DT_SIZE_M(3)>;
+		};
+		medium_partition: partition@3F00000 {
+			label = "medium";
+			reg = <0x03F00000 DT_SIZE_K(960)>;
+		};
+		small_partition: partition@3FF0000 {
+			label = "small";
+			reg = <0x03FF0000 DT_SIZE_K(64)>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/ophelia4ev_nrf54l15_cpuapp.overlay b/tests/subsys/fs/littlefs/boards/ophelia4ev_nrf54l15_cpuapp.overlay
new file mode 100644
index 00000000000..64bfe273c9d
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/ophelia4ev_nrf54l15_cpuapp.overlay
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2025 Würth Elektronik eiSos GmbH & Co. KG
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &slot0_ns_partition;
+/delete-node/ &slot1_partition;
+/delete-node/ &slot1_ns_partition;
+
+&cpuapp_rram {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		small_partition: partition@67000 {
+			label = "small";
+			reg = <0x00067000 0x00010000>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/subsys/fs/littlefs/boards/s32z2xxdc2_s32z270_rtu0.overlay
new file mode 100644
index 00000000000..0a770c4d22e
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/s32z2xxdc2_s32z270_rtu0.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&s26hs512t {
+	partitions {
+		small_partition: partition@0 {
+			label = "small";
+			reg = <0x00000000 0x00010000>;
+		};
+		medium_partition: partition@10000 {
+			label = "medium";
+			reg = <0x00010000 0x000F0000>;
+		};
+		large_partition: partition@100000 {
+			label = "large";
+			reg = <0x00100000 0x00300000>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/subsys/fs/littlefs/boards/s32z2xxdc2_s32z270_rtu1.overlay
new file mode 100644
index 00000000000..0a770c4d22e
--- /dev/null
+++ b/tests/subsys/fs/littlefs/boards/s32z2xxdc2_s32z270_rtu1.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&s26hs512t {
+	partitions {
+		small_partition: partition@0 {
+			label = "small";
+			reg = <0x00000000 0x00010000>;
+		};
+		medium_partition: partition@10000 {
+			label = "medium";
+			reg = <0x00010000 0x000F0000>;
+		};
+		large_partition: partition@100000 {
+			label = "large";
+			reg = <0x00100000 0x00300000>;
+		};
+	};
+};
diff --git a/tests/subsys/fs/littlefs/src/test_lfs_basic.c b/tests/subsys/fs/littlefs/src/test_lfs_basic.c
index 9c4e0544967..05a5de2a40a 100644
--- a/tests/subsys/fs/littlefs/src/test_lfs_basic.c
+++ b/tests/subsys/fs/littlefs/src/test_lfs_basic.c
@@ -57,12 +57,8 @@ static int clean_statvfs(const struct fs_mount_t *mp)
 	TC_PRINT("%s: bsize %lu ; frsize %lu ; blocks %lu ; bfree %lu\n",
 		 mp->mnt_point,
 		 stat.f_bsize, stat.f_frsize, stat.f_blocks, stat.f_bfree);
-	zassert_equal(stat.f_bsize, 16,
+	zassert_equal(stat.f_bsize, CONFIG_FS_LITTLEFS_PROG_SIZE,
 		      "bsize fail");
-	zassert_equal(stat.f_frsize, 4096,
-		      "frsize fail");
-	zassert_equal(stat.f_blocks, 16,
-		      "blocks fail");
 	zassert_equal(stat.f_bfree, stat.f_blocks - 2U,
 		      "bfree fail");
 
@@ -88,10 +84,6 @@ static int check_medium(void)
 		 stat.f_bsize, stat.f_frsize, stat.f_blocks, stat.f_bfree);
 	zassert_equal(stat.f_bsize, MEDIUM_IO_SIZE,
 		      "bsize fail");
-	zassert_equal(stat.f_frsize, 4096,
-		      "frsize fail");
-	zassert_equal(stat.f_blocks, 240,
-		      "blocks fail");
 	zassert_equal(stat.f_bfree, stat.f_blocks - 2U,
 		      "bfree fail");
 
@@ -120,10 +112,6 @@ static int check_large(void)
 		 stat.f_bsize, stat.f_frsize, stat.f_blocks, stat.f_bfree);
 	zassert_equal(stat.f_bsize, LARGE_IO_SIZE,
 		      "bsize fail");
-	zassert_equal(stat.f_frsize, 32768,
-		      "frsize fail");
-	zassert_equal(stat.f_blocks, 96,
-		      "blocks fail");
 	zassert_equal(stat.f_bfree, stat.f_blocks - 2U,
 		      "bfree fail");
 
diff --git a/tests/subsys/fs/littlefs/src/testfs_lfs.c b/tests/subsys/fs/littlefs/src/testfs_lfs.c
index 01737749ec1..bde73b87caa 100644
--- a/tests/subsys/fs/littlefs/src/testfs_lfs.c
+++ b/tests/subsys/fs/littlefs/src/testfs_lfs.c
@@ -45,7 +45,6 @@ static struct fs_littlefs large = {
 		.prog_size = LARGE_IO_SIZE,
 		.cache_size = LARGE_CACHE_SIZE,
 		.lookahead_size = LARGE_LOOKAHEAD_SIZE,
-		.block_size = 32768, /* increase erase size */
 		.read_buffer = large_read_buffer,
 		.prog_buffer = large_prog_buffer,
 		.lookahead_buffer = large_lookahead_buffer,
diff --git a/tests/subsys/fs/littlefs/src/testfs_mkfs.c b/tests/subsys/fs/littlefs/src/testfs_mkfs.c
index acfcb805853..978bc7463d6 100644
--- a/tests/subsys/fs/littlefs/src/testfs_mkfs.c
+++ b/tests/subsys/fs/littlefs/src/testfs_mkfs.c
@@ -49,7 +49,7 @@ ZTEST(littlefs, test_fs_mkfs_ops_lfs)
 FS_LITTLEFS_DECLARE_CUSTOM_CONFIG(custom_cfg,
 		4,
 		CONFIG_FS_LITTLEFS_READ_SIZE,
-		CONFIG_FS_LITTLEFS_PROG_SIZE * 2,
+		CONFIG_FS_LITTLEFS_PROG_SIZE,
 		CONFIG_FS_LITTLEFS_CACHE_SIZE,
 		CONFIG_FS_LITTLEFS_LOOKAHEAD_SIZE);
 
@@ -74,7 +74,7 @@ ZTEST(littlefs, test_fs_mkfs_custom)
 
 	TC_PRINT("f_bsize= %lu", sbuf.f_bsize);
 	/* Prog size is returned in f_bsize field. */
-	zassert_equal(sbuf.f_bsize, 2 * CONFIG_FS_LITTLEFS_PROG_SIZE);
+	zassert_equal(sbuf.f_bsize, CONFIG_FS_LITTLEFS_PROG_SIZE);
 
 	ret = fs_unmount(&mnt);
 	zassert_equal(ret, 0, "Expected success (ret=%d)", ret);
diff --git a/tests/subsys/fs/littlefs/testcase.yaml b/tests/subsys/fs/littlefs/testcase.yaml
index 0af26316a82..f9b6d4d9628 100644
--- a/tests/subsys/fs/littlefs/testcase.yaml
+++ b/tests/subsys/fs/littlefs/testcase.yaml
@@ -6,16 +6,40 @@ common:
     - nrf52840dk/nrf52840
     - native_sim
     - native_sim/native/64
-    - mimxrt1060_evk/mimxrt1062/qspi
     - mr_canhubk3
+    - frdm_mcxn947/mcxn947/cpu0
+    - frdm_rw612
+    - mimxrt1010_evk
+    - mimxrt1015_evk
+    - mimxrt1040_evk
+    - mimxrt1050_evk/mimxrt1052/hyperflash
+    - mimxrt1060_evk/mimxrt1062/qspi
+    - mimxrt1170_evk/mimxrt1176/cm7
+    - mimxrt1180_evk/mimxrt1189/cm33
+    - mimxrt595_evk/mimxrt595s/cm33
+    - mimxrt685_evk/mimxrt685s/cm33
   integration_platforms:
-    - nrf52840dk/nrf52840
+    - native_sim
   modules:
     - littlefs
 tests:
   filesystem.littlefs.default:
     timeout: 60
-    platform_allow: nrf54l15dk/nrf54l15/cpuapp
+    platform_allow:
+      - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
+      - s32z2xxdc2/s32z270/rtu0
+      - s32z2xxdc2/s32z270/rtu1
+      - s32z2xxdc2@D/s32z270/rtu0
+      - s32z2xxdc2@D/s32z270/rtu1
+      - frdm_mcxa156
+      - frdm_mcxn236
+      - frdm_mcxw71
+      - lpcxpresso55s06
+      - lpcxpresso55s16
+      - lpcxpresso55s28
+      - lpcxpresso55s36
+      - lpcxpresso55s69/lpc55s69/cpu0
   filesystem.littlefs.custom:
     timeout: 180
     extra_configs:
diff --git a/tests/subsys/fs/nvs/Kconfig b/tests/subsys/fs/nvs/Kconfig
new file mode 100644
index 00000000000..b1c5ddcb173
--- /dev/null
+++ b/tests/subsys/fs/nvs/Kconfig
@@ -0,0 +1,16 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+mainmenu "NVS test configuration"
+
+config TEST_NVS_SIMULATOR
+	bool "Enable NVS tests designed to be run using a flash-simulator"
+	default y if BOARD_QEMU_X86 || ARCH_POSIX || BOARD_MPS2_AN385
+	help
+	  If y, enables NVS tests designed to be run using a flash-simulator,
+	  which provide functionality for flash property customization
+	  and emulating errors in flash operation in parallel to
+	  the regular flash API.
+	  The tests must be run only on qemu_x86, mps2_an385, or native_sim target.
+
+source "Kconfig.zephyr"
diff --git a/tests/subsys/fs/nvs/src/main.c b/tests/subsys/fs/nvs/src/main.c
index dcd264422b7..1747a7ba4aa 100644
--- a/tests/subsys/fs/nvs/src/main.c
+++ b/tests/subsys/fs/nvs/src/main.c
@@ -4,18 +4,6 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/*
- * This test is designed to be run using flash-simulator which provide
- * functionality for flash property customization and emulating errors in
- * flash operation in parallel to regular flash API.
- * Test should be run on qemu_x86, mps2_an385 or native_sim target.
- */
-
-#if !defined(CONFIG_BOARD_QEMU_X86) && !defined(CONFIG_ARCH_POSIX) &&                              \
-	!defined(CONFIG_BOARD_MPS2_AN385)
-#error "Run only on qemu_x86, mps2_an385, or a posix architecture based target (for ex. native_sim)"
-#endif
-
 #include <stdio.h>
 #include <string.h>
 #include <zephyr/ztest.h>
@@ -39,8 +27,10 @@ static const struct device *const flash_dev = TEST_NVS_FLASH_AREA_DEV;
 
 struct nvs_fixture {
 	struct nvs_fs fs;
+#ifdef CONFIG_TEST_NVS_SIMULATOR
 	struct stats_hdr *sim_stats;
 	struct stats_hdr *sim_thresholds;
+#endif /* CONFIG_TEST_NVS_SIMULATOR */
 };
 
 static void *setup(void)
@@ -69,22 +59,26 @@ static void *setup(void)
 
 static void before(void *data)
 {
+#ifdef CONFIG_TEST_NVS_SIMULATOR
 	struct nvs_fixture *fixture = (struct nvs_fixture *)data;
 
 	fixture->sim_stats = stats_group_find("flash_sim_stats");
 	fixture->sim_thresholds = stats_group_find("flash_sim_thresholds");
+#endif /* CONFIG_TEST_NVS_SIMULATOR */
 }
 
 static void after(void *data)
 {
 	struct nvs_fixture *fixture = (struct nvs_fixture *)data;
 
+#ifdef CONFIG_TEST_NVS_SIMULATOR
 	if (fixture->sim_stats) {
 		stats_reset(fixture->sim_stats);
 	}
 	if (fixture->sim_thresholds) {
 		stats_reset(fixture->sim_thresholds);
 	}
+#endif /* CONFIG_TEST_NVS_SIMULATOR */
 
 	/* Clear NVS */
 	if (fixture->fs.ready) {
@@ -142,6 +136,7 @@ ZTEST_F(nvs, test_nvs_write)
 	execute_long_pattern_write(TEST_DATA_ID, &fixture->fs);
 }
 
+#ifdef CONFIG_TEST_NVS_SIMULATOR
 static int flash_sim_write_calls_find(struct stats_hdr *hdr, void *arg,
 				      const char *name, uint16_t off)
 {
@@ -525,6 +520,7 @@ ZTEST_F(nvs, test_nvs_corrupted_sector_close_operation)
 	/* Ensure that the NVS is able to store new content. */
 	execute_long_pattern_write(max_id, &fixture->fs);
 }
+#endif /* CONFIG_TEST_NVS_SIMULATOR */
 
 /**
  * @brief Test case when storage become full, so only deletion is possible.
@@ -639,6 +635,7 @@ ZTEST_F(nvs, test_delete)
 		     " any footprint in the storage");
 }
 
+#ifdef CONFIG_TEST_NVS_SIMULATOR
 /*
  * Test that garbage-collection can recover all ate's even when the last ate,
  * ie close_ate, is corrupt. In this test the close_ate is set to point to the
@@ -659,6 +656,7 @@ ZTEST_F(nvs, test_nvs_gc_corrupt_close_ate)
 	close_ate.id = 0xffff;
 	close_ate.offset = fixture->fs.sector_size - sizeof(struct nvs_ate) * 5;
 	close_ate.len = 0;
+	close_ate.part = 0xff;
 	close_ate.crc8 = 0xff; /* Incorrect crc8 */
 
 	ate.id = 0x1;
@@ -667,6 +665,7 @@ ZTEST_F(nvs, test_nvs_gc_corrupt_close_ate)
 #ifdef CONFIG_NVS_DATA_CRC
 	ate.len += sizeof(data_crc);
 #endif
+	ate.part = 0xff;
 	ate.crc8 = crc8_ccitt(0xff, &ate,
 			      offsetof(struct nvs_ate, crc8));
 
@@ -722,12 +721,14 @@ ZTEST_F(nvs, test_nvs_gc_corrupt_ate)
 	close_ate.id = 0xffff;
 	close_ate.offset = fixture->fs.sector_size / 2;
 	close_ate.len = 0;
+	close_ate.part = 0xff;
 	close_ate.crc8 = crc8_ccitt(0xff, &close_ate,
 				    offsetof(struct nvs_ate, crc8));
 
 	corrupt_ate.id = 0xdead;
 	corrupt_ate.offset = 0;
 	corrupt_ate.len = 20;
+	corrupt_ate.part = 0xff;
 	corrupt_ate.crc8 = 0xff; /* Incorrect crc8 */
 
 	/* Mark sector 0 as closed */
@@ -754,6 +755,7 @@ ZTEST_F(nvs, test_nvs_gc_corrupt_ate)
 	err = nvs_mount(&fixture->fs);
 	zassert_true(err == 0,  "nvs_mount call failure: %d", err);
 }
+#endif /* CONFIG_TEST_NVS_SIMULATOR */
 
 #ifdef CONFIG_NVS_LOOKUP_CACHE
 static size_t num_matching_cache_entries(uint32_t addr, bool compare_sector_only, struct nvs_fs *fs)
@@ -960,6 +962,7 @@ ZTEST_F(nvs, test_nvs_cache_hash_quality)
 #endif
 }
 
+#ifdef CONFIG_TEST_NVS_SIMULATOR
 /*
  * Test NVS bad region initialization recovery.
  */
@@ -996,3 +999,4 @@ ZTEST_F(nvs, test_nvs_init_bad_memory_region)
 	zassert_true(err == -EDEADLK, "nvs_mount call ok, expect fail: %d", err);
 #endif
 }
+#endif /* CONFIG_TEST_NVS_SIMULATOR */
diff --git a/tests/subsys/fs/zms/boards/native_sim.overlay b/tests/subsys/fs/zms/boards/native_sim.overlay
index 0f330fd7b17..4579d10f932 100644
--- a/tests/subsys/fs/zms/boards/native_sim.overlay
+++ b/tests/subsys/fs/zms/boards/native_sim.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2022 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
diff --git a/tests/subsys/fs/zms/boards/qemu_x86_ev_0x00.overlay b/tests/subsys/fs/zms/boards/qemu_x86_ev_0x00.overlay
index ffc3bc97aac..0f122e34007 100644
--- a/tests/subsys/fs/zms/boards/qemu_x86_ev_0x00.overlay
+++ b/tests/subsys/fs/zms/boards/qemu_x86_ev_0x00.overlay
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2024 Nordic Semiconductor ASA
+ * Copyright (c) 2020 Nordic Semiconductor ASA
  *
  * SPDX-License-Identifier: Apache-2.0
  */
diff --git a/tests/subsys/fs/zms/prj.conf b/tests/subsys/fs/zms/prj.conf
index 5d84f6e17fd..a3461bd526f 100644
--- a/tests/subsys/fs/zms/prj.conf
+++ b/tests/subsys/fs/zms/prj.conf
@@ -6,4 +6,6 @@ CONFIG_FLASH_MAP=y
 
 CONFIG_ZMS=y
 CONFIG_LOG=y
-CONFIG_ZMS_LOG_LEVEL_DBG=y
+
+#Uncomment below line to see more debug logs
+#CONFIG_ZMS_LOG_LEVEL_DBG=y
diff --git a/tests/subsys/fs/zms/src/main.c b/tests/subsys/fs/zms/src/main.c
index 6d170ce1f9f..14d6291970c 100644
--- a/tests/subsys/fs/zms/src/main.c
+++ b/tests/subsys/fs/zms/src/main.c
@@ -1,4 +1,5 @@
 /*
+ * Copyright (c) 2019 Nordic Semiconductor ASA
  * Copyright (c) 2024 BayLibre SAS
  *
  * SPDX-License-Identifier: Apache-2.0
diff --git a/tests/subsys/ipc/ipc_service/prj.conf b/tests/subsys/ipc/ipc_service/prj.conf
index 01e20c4e9b9..d244f5d0e50 100644
--- a/tests/subsys/ipc/ipc_service/prj.conf
+++ b/tests/subsys/ipc/ipc_service/prj.conf
@@ -2,5 +2,4 @@
 # SPDX-License-Identifier: Apache-2.0
 
 CONFIG_ZTEST=y
-CONFIG_MMU=y
 CONFIG_IPC_SERVICE=y
diff --git a/tests/subsys/ipc/ipc_sessions/CMakeLists.txt b/tests/subsys/ipc/ipc_sessions/CMakeLists.txt
new file mode 100644
index 00000000000..79b2b9c49c3
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/CMakeLists.txt
@@ -0,0 +1,16 @@
+# Copyright 2021 Google LLC
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(ipc_service)
+
+zephyr_include_directories(./common)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
+
+zephyr_sources_ifdef(CONFIG_IPC_SERVICE_ICMSG_V1		interoperability/icmsg_v1.c)
+zephyr_sources_ifdef(CONFIG_PBUF_V1				interoperability/pbuf_v1.c)
+zephyr_sources_ifdef(CONFIG_IPC_SERVICE_BACKEND_ICMSG_V1	interoperability/ipc_icmsg_v1.c)
diff --git a/tests/subsys/ipc/ipc_sessions/Kconfig b/tests/subsys/ipc/ipc_sessions/Kconfig
new file mode 100644
index 00000000000..1c1ec5f3725
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/Kconfig
@@ -0,0 +1,37 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+rsource "interoperability/Kconfig"
+
+menu "Zephyr"
+source "Kconfig.zephyr"
+endmenu
+
+config IPC_TEST_MSG_HEAP_SIZE
+	int "The heap to copy processed messages"
+	default 512
+	help
+		Internal heap where all the message data would be copied to be processed
+		linearry in tests.
+
+config IPC_TEST_SKIP_CORE_RESET
+	bool "Skip the tests that includes core resetting"
+	help
+		Some of the cores cannot be safely restarted.
+		Skip the tests that require it in such a cases.
+
+config IPC_TEST_BLOCK_SIZE
+	int "Block size for multiple transfers test"
+	default 32
+
+config IPC_TEST_BLOCK_CNT
+	int "Number of blocks for multiple transfers test"
+	default 8000
+
+config IPC_TEST_SKIP_UNBOUND
+	bool "Skip unbound tests"
+	help
+		Whether to skip tests that requires unbound callback functionality.
diff --git a/tests/subsys/ipc/ipc_sessions/Kconfig.sysbuild b/tests/subsys/ipc/ipc_sessions/Kconfig.sysbuild
new file mode 100644
index 00000000000..3c064f59d52
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/Kconfig.sysbuild
@@ -0,0 +1,13 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+source "${ZEPHYR_BASE}/share/sysbuild/Kconfig"
+
+config REMOTE_BOARD
+	string "The board used for remote target"
+	default "nrf5340dk/nrf5340/cpunet" if BOARD_NRF5340DK_NRF5340_CPUAPP
+	default "nrf5340dk/nrf5340/cpunet" if BOARD_NRF5340DK_NRF5340_CPUAPP_NS
+	default "nrf54h20dk/nrf54h20/cpurad" if BOARD_NRF54H20DK_NRF54H20_CPUAPP
diff --git a/tests/subsys/ipc/ipc_sessions/boards/nrf5340dk_nrf5340_cpuapp.conf b/tests/subsys/ipc/ipc_sessions/boards/nrf5340dk_nrf5340_cpuapp.conf
new file mode 100644
index 00000000000..4946c417b16
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/boards/nrf5340dk_nrf5340_cpuapp.conf
@@ -0,0 +1,7 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+CONFIG_SOC_NRF53_CPUNET_ENABLE=y
diff --git a/tests/subsys/ipc/ipc_sessions/boards/nrf5340dk_nrf5340_cpuapp.overlay b/tests/subsys/ipc/ipc_sessions/boards/nrf5340dk_nrf5340_cpuapp.overlay
new file mode 100644
index 00000000000..d87bb33b3b3
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/boards/nrf5340dk_nrf5340_cpuapp.overlay
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2022 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &ipc0;
+
+/ {
+	chosen {
+		/delete-property/ zephyr,ipc_shm;
+		/delete-property/ zephyr,bt-hci;
+	};
+
+	reserved-memory {
+		/delete-node/ memory@20070000;
+
+		sram_tx: memory@20070000 {
+			reg = <0x20070000 0x8000>;
+		};
+
+		sram_rx: memory@20078000 {
+			reg = <0x20078000 0x8000>;
+		};
+	};
+
+	ipc0: ipc0 {
+		compatible = "zephyr,ipc-icmsg";
+		tx-region = <&sram_tx>;
+		rx-region = <&sram_rx>;
+		mboxes = <&mbox 0>, <&mbox 1>;
+		mbox-names = "tx", "rx";
+		dcache-alignment = <8>;
+		unbound = "detect";
+		status = "okay";
+	};
+};
diff --git a/tests/subsys/ipc/ipc_sessions/boards/nrf54h20dk_nrf54h20_cpuapp.overlay b/tests/subsys/ipc/ipc_sessions/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
new file mode 100644
index 00000000000..68efc080022
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/boards/nrf54h20dk_nrf54h20_cpuapp.overlay
@@ -0,0 +1,12 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Replace default ipc0 instance */
+&ipc0 {
+	compatible = "zephyr,ipc-icmsg";
+	/delete-property/ tx-blocks;
+	/delete-property/ rx-blocks;
+	unbound = "enable";
+};
diff --git a/tests/subsys/ipc/ipc_sessions/boards/nrf54h20dk_nrf54h20_cpuapp_cpuppr.overlay b/tests/subsys/ipc/ipc_sessions/boards/nrf54h20dk_nrf54h20_cpuapp_cpuppr.overlay
new file mode 100644
index 00000000000..90ef82327e9
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/boards/nrf54h20dk_nrf54h20_cpuapp_cpuppr.overlay
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Replace default ipc0 instance */
+/delete-node/ &ipc0;
+
+ipc0: &cpuapp_cpuppr_ipc {
+	status = "okay";
+	unbound = "detect";
+};
+
+&cpuppr_vevif {
+	status = "okay";
+};
+
+&cpuapp_bellboard {
+	status = "okay";
+};
+
+/ {
+	chosen {
+		/delete-property/ zephyr,bt-hci;
+	};
+};
diff --git a/tests/subsys/ipc/ipc_sessions/common/test_commands.h b/tests/subsys/ipc/ipc_sessions/common/test_commands.h
new file mode 100644
index 00000000000..f992d34d52e
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/common/test_commands.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef TEST_COMMANDS_H
+#include <stdint.h>
+
+/**
+ * @brief Test commands executable by remote
+ */
+enum ipc_test_commands {
+	IPC_TEST_CMD_NONE,     /**< Command to be ingored */
+	IPC_TEST_CMD_PING,     /**< Respond with the @ref IPC_TEST_CMD_PONG message */
+	IPC_TEST_CMD_PONG,     /**< Expected response to IPC_TEST_CMD_PING */
+	IPC_TEST_CMD_ECHO,     /**< Respond with the same data */
+	IPC_TEST_CMD_ECHO_RSP, /**< Echo respond */
+	IPC_TEST_CMD_REBOND,   /**< Unbond and rebond back whole interface */
+	IPC_TEST_CMD_REBOOT,   /**< Restart remote CPU after a given delay */
+	/* Commands used for data transfer test */
+	IPC_TEST_CMD_RXSTART,  /**< Start receiving data */
+	IPC_TEST_CMD_TXSTART,  /**< Start sending data */
+	IPC_TEST_CMD_RXGET,    /**< Get rx status */
+	IPC_TEST_CMD_TXGET,    /**< Get tx status */
+	IPC_TEST_CMD_XSTAT,    /**< rx/tx status response */
+	IPC_TEST_CMD_XDATA,    /**< Transfer data block */
+	/* End of commands used for data transfer test */
+};
+
+/**
+ * @brief Base command structure
+ */
+struct ipc_test_cmd {
+	uint32_t cmd;   /**< The command of @ref ipc_test_command type */
+	uint8_t data[]; /**< Command data depending on the command itself */
+};
+
+/**
+ * @brief Rebond command structure
+ */
+struct ipc_test_cmd_rebond {
+	struct ipc_test_cmd base;
+	uint32_t timeout_ms;
+};
+
+/**
+ * @brief Reboot command structure
+ */
+struct ipc_test_cmd_reboot {
+	struct ipc_test_cmd base;
+	uint32_t timeout_ms;
+};
+
+/**
+ * @brief Start the rx or tx transfer
+ */
+struct ipc_test_cmd_xstart {
+	struct ipc_test_cmd base;
+	uint32_t blk_size;
+	uint32_t blk_cnt;
+	uint32_t seed;
+};
+
+/**
+ * @brief Get the status of rx or tx transfer
+ */
+struct ipc_test_cmd_xstat {
+	struct ipc_test_cmd base;
+	uint32_t blk_cnt; /**< Transfers left */
+	int32_t  result;  /**< Current result */
+};
+
+/**
+ * @brief The result of rx or tx transfer
+ */
+struct ipc_test_cmd_xrsp {
+	struct ipc_test_cmd base;
+	int32_t result;
+};
+
+#endif /* TEST_COMMANDS_H */
diff --git a/tests/subsys/ipc/ipc_sessions/interoperability/Kconfig b/tests/subsys/ipc/ipc_sessions/interoperability/Kconfig
new file mode 100644
index 00000000000..e50f208b153
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/interoperability/Kconfig
@@ -0,0 +1,29 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+config IPC_SERVICE_BACKEND_ICMSG
+	default n if IPC_SERVICE_BACKEND_ICMSG_V1
+
+config IPC_SERVICE_ICMSG
+	default n if IPC_SERVICE_ICMSG_V1
+
+config IPC_SERVICE_BACKEND_ICMSG_V1
+	bool "ICMSG backend with SPSC packet buffer (old implementation)"
+	depends on MBOX
+	select IPC_SERVICE_ICMSG_V1
+	help
+	  Chosing this backend results in single endpoint implementation based
+	  on circular packet buffer.
+
+menuconfig IPC_SERVICE_ICMSG_V1
+	bool "icmsg IPC library (old implementation)"
+	select PBUF_V1
+	help
+	  Icmsg library
+
+if IPC_SERVICE_ICMSG_V1
+	rsource "Kconfig.icmsg_v1"
+endif
diff --git a/tests/subsys/ipc/ipc_sessions/interoperability/Kconfig.icmsg_v1 b/tests/subsys/ipc/ipc_sessions/interoperability/Kconfig.icmsg_v1
new file mode 100644
index 00000000000..463a1a0ad3c
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/interoperability/Kconfig.icmsg_v1
@@ -0,0 +1,90 @@
+# Copyright (c) 2022 Nordic Semiconductor (ASA)
+# SPDX-License-Identifier: Apache-2.0
+
+config IPC_SERVICE_ICMSG_SHMEM_ACCESS_SYNC_V1
+	bool "Synchronize access to shared memory"
+	depends on MULTITHREADING
+	default y
+	help
+	  Provide synchronization access to shared memory at a library level.
+	  This option is enabled by default to allow to use sending API from
+	  multiple contexts. Mutex is used to guard access to the memory.
+	  This option can be safely disabled if an application ensures data
+	  are sent from single context.
+
+config IPC_SERVICE_ICMSG_SHMEM_ACCESS_TO_MS_V1
+	int "Mutex lock timeout in milliseconds"
+	depends on IPC_SERVICE_ICMSG_SHMEM_ACCESS_SYNC_V1
+	range 1 5
+	default 1
+	help
+	  Maximum time to wait, in milliseconds, for access to send data with
+	  backends basing on icmsg library. This time should be relatively low.
+
+config IPC_SERVICE_ICMSG_BOND_NOTIFY_REPEAT_TO_MS_V1
+	int "Bond notification timeout in miliseconds"
+	range 1 100
+	default 1
+	help
+	  Time to wait for remote bonding notification before the
+	  notification is repeated.
+
+config IPC_SERVICE_BACKEND_ICMSG_WQ_ENABLE_V1
+	bool "Use dedicated workqueue"
+	depends on MULTITHREADING
+	default y
+	help
+	  Enable dedicated workqueue thread for the ICMsg backend.
+	  Disabling this configuration will cause the ICMsg backend to
+	  process incoming data through the system workqueue context, and
+	  therefore reduces the RAM footprint of the backend.
+	  Disabling this config may result in deadlocks in certain usage
+	  scenarios, such as when synchronous IPC is executed from the system
+	  workqueue context.
+	  The callbacks coming from the backend are executed from the workqueue
+	  context.
+	  When the option is disabled, the user must obey the restrictions
+	  imposed by the system workqueue, such as never performing blocking
+	  operations from within the callback.
+
+if IPC_SERVICE_BACKEND_ICMSG_WQ_ENABLE_V1
+
+config IPC_SERVICE_BACKEND_ICMSG_WQ_STACK_SIZE_V1
+	int "Size of RX work queue stack"
+	default 1280
+	help
+	  Size of stack used by work queue RX thread. This work queue is
+	  created to prevent notifying service users about received data
+	  from the system work queue. The queue is shared among instances.
+
+config IPC_SERVICE_BACKEND_ICMSG_WQ_PRIORITY_V1
+	int "Priority of RX work queue thread"
+	default -1
+	range -256 -1
+	help
+	  Priority of the ICMSG RX work queue thread.
+	  The ICMSG library in its simplicity requires the workqueue to execute
+	  at a cooperative priority.
+
+endif
+
+# The Icmsg library in its simplicity requires the system workqueue to execute
+# at a cooperative priority.
+config SYSTEM_WORKQUEUE_PRIORITY
+	range -256 -1 if !IPC_SERVICE_BACKEND_ICMSG_WQ_ENABLE_V1
+
+config PBUF_V1
+	bool "Packed buffer support library (old implementation)"
+	help
+	  The packet buffer implements lightweight unidirectional packet buffer
+	  with read/write semantics on top of a memory region shared by the
+	  reader and writer. It optionally embeds cache and memory barrier
+	  management to ensure correct data access.
+
+if PBUF_V1
+
+config PBUF_RX_READ_BUF_SIZE_V1
+	int "Size of PBUF read buffer in bytes"
+	default 128
+
+endif # PBUF
diff --git a/tests/subsys/ipc/ipc_sessions/interoperability/icmsg_v1.c b/tests/subsys/ipc/ipc_sessions/interoperability/icmsg_v1.c
new file mode 100644
index 00000000000..ae83dd30beb
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/interoperability/icmsg_v1.c
@@ -0,0 +1,392 @@
+/*
+ * Copyright (c) 2022 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "icmsg_v1.h"
+
+#include <string.h>
+#include <zephyr/drivers/mbox.h>
+#include <zephyr/sys/atomic.h>
+#include "pbuf_v1.h"
+#include <zephyr/init.h>
+
+#define BOND_NOTIFY_REPEAT_TO	K_MSEC(CONFIG_IPC_SERVICE_ICMSG_BOND_NOTIFY_REPEAT_TO_MS)
+#define SHMEM_ACCESS_TO		K_MSEC(CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_TO_MS)
+
+static const uint8_t magic[] = {0x45, 0x6d, 0x31, 0x6c, 0x31, 0x4b,
+				0x30, 0x72, 0x6e, 0x33, 0x6c, 0x69, 0x34};
+
+#ifdef CONFIG_MULTITHREADING
+#if defined(CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_ENABLE)
+static K_THREAD_STACK_DEFINE(icmsg_stack, CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_STACK_SIZE);
+static struct k_work_q icmsg_workq;
+static struct k_work_q *const workq = &icmsg_workq;
+#else
+static struct k_work_q *const workq = &k_sys_work_q;
+#endif
+static void mbox_callback_process(struct k_work *item);
+#else
+static void mbox_callback_process(struct icmsg_data_t *dev_data);
+#endif
+
+static int mbox_deinit(const struct icmsg_config_t *conf,
+		       struct icmsg_data_t *dev_data)
+{
+	int err;
+
+	err = mbox_set_enabled_dt(&conf->mbox_rx, 0);
+	if (err != 0) {
+		return err;
+	}
+
+	err = mbox_register_callback_dt(&conf->mbox_rx, NULL, NULL);
+	if (err != 0) {
+		return err;
+	}
+
+#ifdef CONFIG_MULTITHREADING
+	(void)k_work_cancel(&dev_data->mbox_work);
+	(void)k_work_cancel_delayable(&dev_data->notify_work);
+#endif
+
+	return 0;
+}
+
+static bool is_endpoint_ready(struct icmsg_data_t *dev_data)
+{
+	return atomic_get(&dev_data->state) == ICMSG_STATE_READY;
+}
+
+#ifdef CONFIG_MULTITHREADING
+static void notify_process(struct k_work *item)
+{
+	struct k_work_delayable *dwork = k_work_delayable_from_work(item);
+	struct icmsg_data_t *dev_data =
+		CONTAINER_OF(dwork, struct icmsg_data_t, notify_work);
+
+	(void)mbox_send_dt(&dev_data->cfg->mbox_tx, NULL);
+
+	atomic_t state = atomic_get(&dev_data->state);
+
+	if (state != ICMSG_STATE_READY) {
+		int ret;
+
+		ret = k_work_reschedule_for_queue(workq, dwork, BOND_NOTIFY_REPEAT_TO);
+		__ASSERT_NO_MSG(ret >= 0);
+		(void)ret;
+	}
+}
+#else
+static void notify_process(struct icmsg_data_t *dev_data)
+{
+	(void)mbox_send_dt(&dev_data->cfg->mbox_tx, NULL);
+#if defined(CONFIG_SYS_CLOCK_EXISTS)
+	int64_t start = k_uptime_get();
+#endif
+
+	while (false == is_endpoint_ready(dev_data)) {
+		mbox_callback_process(dev_data);
+
+#if defined(CONFIG_SYS_CLOCK_EXISTS)
+		if ((k_uptime_get() - start) > CONFIG_IPC_SERVICE_ICMSG_BOND_NOTIFY_REPEAT_TO_MS) {
+#endif
+			(void)mbox_send_dt(&dev_data->cfg->mbox_tx, NULL);
+#if defined(CONFIG_SYS_CLOCK_EXISTS)
+			start = k_uptime_get();
+		};
+#endif
+	}
+}
+#endif
+
+#ifdef CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_SYNC
+static int reserve_tx_buffer_if_unused(struct icmsg_data_t *dev_data)
+{
+	int ret = k_mutex_lock(&dev_data->tx_lock, SHMEM_ACCESS_TO);
+
+	if (ret < 0) {
+		return ret;
+	}
+
+	return 0;
+}
+
+static int release_tx_buffer(struct icmsg_data_t *dev_data)
+{
+	return k_mutex_unlock(&dev_data->tx_lock);
+}
+#endif
+
+static uint32_t data_available(struct icmsg_data_t *dev_data)
+{
+	return pbuf_read(dev_data->rx_pb, NULL, 0);
+}
+
+#ifdef CONFIG_MULTITHREADING
+static void submit_mbox_work(struct icmsg_data_t *dev_data)
+{
+	if (k_work_submit_to_queue(workq, &dev_data->mbox_work) < 0) {
+		/* The mbox processing work is never canceled.
+		 * The negative error code should never be seen.
+		 */
+		__ASSERT_NO_MSG(false);
+	}
+}
+
+static void submit_work_if_buffer_free(struct icmsg_data_t *dev_data)
+{
+	submit_mbox_work(dev_data);
+}
+
+static void submit_work_if_buffer_free_and_data_available(
+		struct icmsg_data_t *dev_data)
+{
+	if (!data_available(dev_data)) {
+		return;
+	}
+
+	submit_mbox_work(dev_data);
+}
+#else
+static void submit_if_buffer_free(struct icmsg_data_t *dev_data)
+{
+	mbox_callback_process(dev_data);
+}
+
+static void submit_if_buffer_free_and_data_available(
+		struct icmsg_data_t *dev_data)
+{
+
+	if (!data_available(dev_data)) {
+		return;
+	}
+
+	mbox_callback_process(dev_data);
+}
+#endif
+
+#ifdef CONFIG_MULTITHREADING
+static void mbox_callback_process(struct k_work *item)
+#else
+static void mbox_callback_process(struct icmsg_data_t *dev_data)
+#endif
+{
+#ifdef CONFIG_MULTITHREADING
+	struct icmsg_data_t *dev_data = CONTAINER_OF(item, struct icmsg_data_t, mbox_work);
+#endif
+	uint8_t rx_buffer[CONFIG_PBUF_RX_READ_BUF_SIZE] __aligned(4);
+
+	atomic_t state = atomic_get(&dev_data->state);
+
+	uint32_t len = data_available(dev_data);
+
+	if (len == 0) {
+		/* Unlikely, no data in buffer. */
+		return;
+	}
+
+	__ASSERT_NO_MSG(len <= sizeof(rx_buffer));
+
+	if (sizeof(rx_buffer) < len) {
+		return;
+	}
+
+	len = pbuf_read(dev_data->rx_pb, rx_buffer, sizeof(rx_buffer));
+
+	if (state == ICMSG_STATE_READY) {
+		if (dev_data->cb->received) {
+			dev_data->cb->received(rx_buffer, len, dev_data->ctx);
+		}
+	} else {
+		__ASSERT_NO_MSG(state == ICMSG_STATE_BUSY);
+
+		/* Allow magic number longer than sizeof(magic) for future protocol version. */
+		bool endpoint_invalid = (len < sizeof(magic) ||
+					memcmp(magic, rx_buffer, sizeof(magic)));
+
+		if (endpoint_invalid) {
+			__ASSERT_NO_MSG(false);
+			return;
+		}
+
+		if (dev_data->cb->bound) {
+			dev_data->cb->bound(dev_data->ctx);
+		}
+
+		atomic_set(&dev_data->state, ICMSG_STATE_READY);
+	}
+#ifdef CONFIG_MULTITHREADING
+	submit_work_if_buffer_free_and_data_available(dev_data);
+#else
+	submit_if_buffer_free_and_data_available(dev_data);
+#endif
+}
+
+static void mbox_callback(const struct device *instance, uint32_t channel,
+			  void *user_data, struct mbox_msg *msg_data)
+{
+	struct icmsg_data_t *dev_data = user_data;
+#ifdef CONFIG_MULTITHREADING
+	submit_work_if_buffer_free(dev_data);
+#else
+	submit_if_buffer_free(dev_data);
+#endif
+}
+
+static int mbox_init(const struct icmsg_config_t *conf,
+		     struct icmsg_data_t *dev_data)
+{
+	int err;
+
+#ifdef CONFIG_MULTITHREADING
+	k_work_init(&dev_data->mbox_work, mbox_callback_process);
+	k_work_init_delayable(&dev_data->notify_work, notify_process);
+#endif
+
+	err = mbox_register_callback_dt(&conf->mbox_rx, mbox_callback, dev_data);
+	if (err != 0) {
+		return err;
+	}
+
+	return mbox_set_enabled_dt(&conf->mbox_rx, 1);
+}
+
+int icmsg_open(const struct icmsg_config_t *conf,
+	       struct icmsg_data_t *dev_data,
+	       const struct ipc_service_cb *cb, void *ctx)
+{
+	if (!atomic_cas(&dev_data->state, ICMSG_STATE_OFF, ICMSG_STATE_BUSY)) {
+		/* Already opened. */
+		return -EALREADY;
+	}
+
+	dev_data->cb = cb;
+	dev_data->ctx = ctx;
+	dev_data->cfg = conf;
+
+#ifdef CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_SYNC
+	k_mutex_init(&dev_data->tx_lock);
+#endif
+
+	int ret = pbuf_tx_init(dev_data->tx_pb);
+
+	if (ret < 0) {
+		__ASSERT(false, "Incorrect configuration");
+		return ret;
+	}
+
+	(void)pbuf_rx_init(dev_data->rx_pb);
+
+	ret = pbuf_write(dev_data->tx_pb, magic, sizeof(magic));
+
+	if (ret < 0) {
+		__ASSERT_NO_MSG(false);
+		return ret;
+	}
+
+	if (ret < (int)sizeof(magic)) {
+		__ASSERT_NO_MSG(ret == sizeof(magic));
+		return ret;
+	}
+
+	ret = mbox_init(conf, dev_data);
+	if (ret) {
+		return ret;
+	}
+#ifdef CONFIG_MULTITHREADING
+	ret = k_work_schedule_for_queue(workq, &dev_data->notify_work, K_NO_WAIT);
+	if (ret < 0) {
+		return ret;
+	}
+#else
+	notify_process(dev_data);
+#endif
+	return 0;
+}
+
+int icmsg_close(const struct icmsg_config_t *conf,
+		struct icmsg_data_t *dev_data)
+{
+	int ret;
+
+	ret = mbox_deinit(conf, dev_data);
+	if (ret) {
+		return ret;
+	}
+
+	atomic_set(&dev_data->state, ICMSG_STATE_OFF);
+
+	return 0;
+}
+
+int icmsg_send(const struct icmsg_config_t *conf,
+	       struct icmsg_data_t *dev_data,
+	       const void *msg, size_t len)
+{
+	int ret;
+	int write_ret;
+#ifdef CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_SYNC
+	int release_ret;
+#endif
+	int sent_bytes;
+
+	if (!is_endpoint_ready(dev_data)) {
+		return -EBUSY;
+	}
+
+	/* Empty message is not allowed */
+	if (len == 0) {
+		return -ENODATA;
+	}
+
+#ifdef CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_SYNC
+	ret = reserve_tx_buffer_if_unused(dev_data);
+	if (ret < 0) {
+		return -ENOBUFS;
+	}
+#endif
+
+	write_ret = pbuf_write(dev_data->tx_pb, msg, len);
+
+#ifdef CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_SYNC
+	release_ret = release_tx_buffer(dev_data);
+	__ASSERT_NO_MSG(!release_ret);
+#endif
+
+	if (write_ret < 0) {
+		return write_ret;
+	} else if (write_ret < len) {
+		return -EBADMSG;
+	}
+	sent_bytes = write_ret;
+
+	__ASSERT_NO_MSG(conf->mbox_tx.dev != NULL);
+
+	ret = mbox_send_dt(&conf->mbox_tx, NULL);
+	if (ret) {
+		return ret;
+	}
+
+	return sent_bytes;
+}
+
+#if defined(CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_ENABLE)
+
+static int work_q_init(void)
+{
+	struct k_work_queue_config cfg = {
+		.name = "icmsg_workq",
+	};
+
+	k_work_queue_start(&icmsg_workq,
+			    icmsg_stack,
+			    K_KERNEL_STACK_SIZEOF(icmsg_stack),
+			    CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_PRIORITY, &cfg);
+	return 0;
+}
+
+SYS_INIT(work_q_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+
+#endif
diff --git a/tests/subsys/ipc/ipc_sessions/interoperability/icmsg_v1.h b/tests/subsys/ipc/ipc_sessions/interoperability/icmsg_v1.h
new file mode 100644
index 00000000000..b0f2849765d
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/interoperability/icmsg_v1.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2022 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_IPC_ICMSG_H_
+#define ZEPHYR_INCLUDE_IPC_ICMSG_H_
+
+#include <stddef.h>
+#include <stdint.h>
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/mbox.h>
+#include <zephyr/ipc/ipc_service.h>
+#include "pbuf_v1.h"
+#include <zephyr/sys/atomic.h>
+
+/* Config aliases that prevenets from config collisions: */
+#undef CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_SYNC
+#ifdef CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_SYNC_V1
+#define CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_SYNC CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_SYNC_V1
+#endif
+#undef CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_TO_MS
+#ifdef CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_TO_MS_V1
+#define CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_TO_MS CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_TO_MS_V1
+#endif
+#undef CONFIG_IPC_SERVICE_ICMSG_BOND_NOTIFY_REPEAT_TO_MS
+#ifdef CONFIG_IPC_SERVICE_ICMSG_BOND_NOTIFY_REPEAT_TO_MS_V1
+#define CONFIG_IPC_SERVICE_ICMSG_BOND_NOTIFY_REPEAT_TO_MS \
+	CONFIG_IPC_SERVICE_ICMSG_BOND_NOTIFY_REPEAT_TO_MS_V1
+#endif
+#undef CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_ENABLE
+#ifdef CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_ENABLE_V1
+#define CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_ENABLE CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_ENABLE_V1
+#endif
+#undef CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_STACK_SIZE
+#ifdef CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_STACK_SIZE_V1
+#define CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_STACK_SIZE \
+	CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_STACK_SIZE_V1
+#endif
+#undef CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_PRIORITY
+#ifdef CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_PRIORITY_V1
+#define CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_PRIORITY CONFIG_IPC_SERVICE_BACKEND_ICMSG_WQ_PRIORITY_V1
+#endif
+#undef CONFIG_PBUF_RX_READ_BUF_SIZE
+#ifdef CONFIG_PBUF_RX_READ_BUF_SIZE_V1
+#define CONFIG_PBUF_RX_READ_BUF_SIZE CONFIG_PBUF_RX_READ_BUF_SIZE_V1
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Icmsg IPC library API
+ * @defgroup ipc_icmsg_api Icmsg IPC library API
+ * @ingroup ipc
+ * @{
+ */
+
+enum icmsg_state {
+	ICMSG_STATE_OFF,
+	ICMSG_STATE_BUSY,
+	ICMSG_STATE_READY,
+};
+
+struct icmsg_config_t {
+	struct mbox_dt_spec mbox_tx;
+	struct mbox_dt_spec mbox_rx;
+};
+
+struct icmsg_data_t {
+	/* Tx/Rx buffers. */
+	struct pbuf *tx_pb;
+	struct pbuf *rx_pb;
+#ifdef CONFIG_IPC_SERVICE_ICMSG_SHMEM_ACCESS_SYNC
+	struct k_mutex tx_lock;
+#endif
+
+	/* Callbacks for an endpoint. */
+	const struct ipc_service_cb *cb;
+	void *ctx;
+
+	/* General */
+	const struct icmsg_config_t *cfg;
+#ifdef CONFIG_MULTITHREADING
+	struct k_work_delayable notify_work;
+	struct k_work mbox_work;
+#endif
+	atomic_t state;
+};
+
+/** @brief Open an icmsg instance
+ *
+ *  Open an icmsg instance to be able to send and receive messages to a remote
+ *  instance.
+ *  This function is blocking until the handshake with the remote instance is
+ *  completed.
+ *  This function is intended to be called late in the initialization process,
+ *  possibly from a thread which can be safely blocked while handshake with the
+ *  remote instance is being pefromed.
+ *
+ *  @param[in] conf Structure containing configuration parameters for the icmsg
+ *                  instance.
+ *  @param[inout] dev_data Structure containing run-time data used by the icmsg
+ *                         instance.
+ *  @param[in] cb Structure containing callback functions to be called on
+ *                events generated by this icmsg instance. The pointed memory
+ *                must be preserved while the icmsg instance is active.
+ *  @param[in] ctx Pointer to context passed as an argument to callbacks.
+ *
+ *
+ *  @retval 0 on success.
+ *  @retval -EALREADY when the instance is already opened.
+ *  @retval other errno codes from dependent modules.
+ */
+int icmsg_open(const struct icmsg_config_t *conf,
+	       struct icmsg_data_t *dev_data,
+	       const struct ipc_service_cb *cb, void *ctx);
+
+/** @brief Close an icmsg instance
+ *
+ *  Closing an icmsg instance results in releasing all resources used by given
+ *  instance including the shared memory regions and mbox devices.
+ *
+ *  @param[in] conf Structure containing configuration parameters for the icmsg
+ *                  instance being closed. Its content must be the same as used
+ *                  for creating this instance with @ref icmsg_open.
+ *  @param[inout] dev_data Structure containing run-time data used by the icmsg
+ *                         instance.
+ *
+ *  @retval 0 on success.
+ *  @retval other errno codes from dependent modules.
+ */
+int icmsg_close(const struct icmsg_config_t *conf,
+		struct icmsg_data_t *dev_data);
+
+/** @brief Send a message to the remote icmsg instance.
+ *
+ *  @param[in] conf Structure containing configuration parameters for the icmsg
+ *                  instance.
+ *  @param[inout] dev_data Structure containing run-time data used by the icmsg
+ *                         instance.
+ *  @param[in] msg Pointer to a buffer containing data to send.
+ *  @param[in] len Size of data in the @p msg buffer.
+ *
+ *
+ *  @retval Number of sent bytes.
+ *  @retval -EBUSY when the instance has not finished handshake with the remote
+ *                 instance.
+ *  @retval -ENODATA when the requested data to send is empty.
+ *  @retval -EBADMSG when the requested data to send is too big.
+ *  @retval -ENOBUFS when there are no TX buffers available.
+ *  @retval other errno codes from dependent modules.
+ */
+int icmsg_send(const struct icmsg_config_t *conf,
+	       struct icmsg_data_t *dev_data,
+	       const void *msg, size_t len);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_INCLUDE_IPC_ICMSG_H_ */
diff --git a/tests/subsys/ipc/ipc_sessions/interoperability/ipc_icmsg_v1.c b/tests/subsys/ipc/ipc_sessions/interoperability/ipc_icmsg_v1.c
new file mode 100644
index 00000000000..4ce003667b0
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/interoperability/ipc_icmsg_v1.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2022 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "ipc_icmsg_v1.h"
+
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include "icmsg_v1.h"
+
+#include <zephyr/ipc/ipc_service_backend.h>
+
+#define DT_DRV_COMPAT	zephyr_ipc_icmsg
+
+static int register_ept(const struct device *instance, void **token,
+			const struct ipc_ept_cfg *cfg)
+{
+	const struct icmsg_config_t *conf = instance->config;
+	struct icmsg_data_t *dev_data = instance->data;
+
+	/* Only one endpoint is supported. No need for a token. */
+	*token = NULL;
+
+	return icmsg_open(conf, dev_data, &cfg->cb, cfg->priv);
+}
+
+static int deregister_ept(const struct device *instance, void *token)
+{
+	const struct icmsg_config_t *conf = instance->config;
+	struct icmsg_data_t *dev_data = instance->data;
+
+	return icmsg_close(conf, dev_data);
+}
+
+static int send(const struct device *instance, void *token,
+		const void *msg, size_t len)
+{
+	const struct icmsg_config_t *conf = instance->config;
+	struct icmsg_data_t *dev_data = instance->data;
+
+	return icmsg_send(conf, dev_data, msg, len);
+}
+
+const static struct ipc_service_backend backend_ops = {
+	.register_endpoint = register_ept,
+	.deregister_endpoint = deregister_ept,
+	.send = send,
+};
+
+static int backend_init(const struct device *instance)
+{
+	return 0;
+}
+
+#define DEFINE_BACKEND_DEVICE(i)					\
+	static const struct icmsg_config_t backend_config_##i = {	\
+		.mbox_tx = MBOX_DT_SPEC_INST_GET(i, tx),		\
+		.mbox_rx = MBOX_DT_SPEC_INST_GET(i, rx),		\
+	};								\
+									\
+	PBUF_DEFINE(tx_pb_##i,						\
+			DT_REG_ADDR(DT_INST_PHANDLE(i, tx_region)),	\
+			DT_REG_SIZE(DT_INST_PHANDLE(i, tx_region)),	\
+			DT_INST_PROP_OR(i, dcache_alignment, 0));	\
+	PBUF_DEFINE(rx_pb_##i,						\
+			DT_REG_ADDR(DT_INST_PHANDLE(i, rx_region)),	\
+			DT_REG_SIZE(DT_INST_PHANDLE(i, rx_region)),	\
+			DT_INST_PROP_OR(i, dcache_alignment, 0));	\
+									\
+	static struct icmsg_data_t backend_data_##i = {			\
+		.tx_pb = &tx_pb_##i,					\
+		.rx_pb = &rx_pb_##i,					\
+	};								\
+									\
+	DEVICE_DT_INST_DEFINE(i,					\
+			 &backend_init,					\
+			 NULL,						\
+			 &backend_data_##i,				\
+			 &backend_config_##i,				\
+			 POST_KERNEL,					\
+			 CONFIG_IPC_SERVICE_REG_BACKEND_PRIORITY,	\
+			 &backend_ops);
+
+DT_INST_FOREACH_STATUS_OKAY(DEFINE_BACKEND_DEVICE)
diff --git a/tests/subsys/ipc/ipc_sessions/interoperability/ipc_icmsg_v1.h b/tests/subsys/ipc/ipc_sessions/interoperability/ipc_icmsg_v1.h
new file mode 100644
index 00000000000..5407ea3e2e8
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/interoperability/ipc_icmsg_v1.h
@@ -0,0 +1,5 @@
+/*
+ * Copyright (c) 2022 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
diff --git a/tests/subsys/ipc/ipc_sessions/interoperability/pbuf_v1.c b/tests/subsys/ipc/ipc_sessions/interoperability/pbuf_v1.c
new file mode 100644
index 00000000000..7c72098af1d
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/interoperability/pbuf_v1.c
@@ -0,0 +1,255 @@
+/*
+ * Copyright (c) 2023 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <string.h>
+#include <errno.h>
+#include <zephyr/cache.h>
+#include "pbuf_v1.h"
+#include <zephyr/sys/byteorder.h>
+
+#if defined(CONFIG_ARCH_POSIX)
+#include <soc.h>
+#endif
+
+/* Helper funciton for getting number of bytes being written to the buffer. */
+static uint32_t idx_occupied(uint32_t len, uint32_t wr_idx, uint32_t rd_idx)
+{
+	/* It is implicitly assumed wr_idx and rd_idx cannot differ by more then len. */
+	return (rd_idx > wr_idx) ? (len - (rd_idx - wr_idx)) : (wr_idx - rd_idx);
+}
+
+/* Helper function for wrapping the index from the begging if above buffer len. */
+static uint32_t idx_wrap(uint32_t len, uint32_t idx)
+{
+	return (idx >= len) ? (idx % len) : (idx);
+}
+
+static int validate_cfg(const struct pbuf_cfg *cfg)
+{
+	/* Validate pointers. */
+	if (!cfg || !cfg->rd_idx_loc || !cfg->wr_idx_loc || !cfg->data_loc) {
+		return -EINVAL;
+	}
+
+	/* Validate pointer alignment. */
+	if (!IS_PTR_ALIGNED_BYTES(cfg->rd_idx_loc, MAX(cfg->dcache_alignment, _PBUF_IDX_SIZE)) ||
+	    !IS_PTR_ALIGNED_BYTES(cfg->wr_idx_loc, MAX(cfg->dcache_alignment, _PBUF_IDX_SIZE)) ||
+	    !IS_PTR_ALIGNED_BYTES(cfg->data_loc, _PBUF_IDX_SIZE)) {
+		return -EINVAL;
+	}
+
+	/* Validate len. */
+	if (cfg->len < _PBUF_MIN_DATA_LEN || !IS_PTR_ALIGNED_BYTES(cfg->len, _PBUF_IDX_SIZE)) {
+		return -EINVAL;
+	}
+
+	/* Validate pointer values. */
+	if (!(cfg->rd_idx_loc < cfg->wr_idx_loc) ||
+	    !((uint8_t *)cfg->wr_idx_loc < cfg->data_loc) ||
+	    !(((uint8_t *)cfg->rd_idx_loc + MAX(_PBUF_IDX_SIZE, cfg->dcache_alignment)) ==
+	    (uint8_t *)cfg->wr_idx_loc)) {
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+#if defined(CONFIG_ARCH_POSIX)
+void pbuf_native_addr_remap(struct pbuf *pb)
+{
+	native_emb_addr_remap((void **)&pb->cfg->rd_idx_loc);
+	native_emb_addr_remap((void **)&pb->cfg->wr_idx_loc);
+	native_emb_addr_remap((void **)&pb->cfg->data_loc);
+}
+#endif
+
+int pbuf_tx_init(struct pbuf *pb)
+{
+	if (validate_cfg(pb->cfg) != 0) {
+		return -EINVAL;
+	}
+#if defined(CONFIG_ARCH_POSIX)
+	pbuf_native_addr_remap(pb);
+#endif
+
+	/* Initialize local copy of indexes. */
+	pb->data.wr_idx = 0;
+	pb->data.rd_idx = 0;
+
+	/* Clear shared memory. */
+	*(pb->cfg->wr_idx_loc) = pb->data.wr_idx;
+	*(pb->cfg->rd_idx_loc) = pb->data.rd_idx;
+
+	__sync_synchronize();
+
+	/* Take care cache. */
+	sys_cache_data_flush_range((void *)(pb->cfg->wr_idx_loc), sizeof(*(pb->cfg->wr_idx_loc)));
+	sys_cache_data_flush_range((void *)(pb->cfg->rd_idx_loc), sizeof(*(pb->cfg->rd_idx_loc)));
+
+	return 0;
+}
+
+int pbuf_rx_init(struct pbuf *pb)
+{
+	if (validate_cfg(pb->cfg) != 0) {
+		return -EINVAL;
+	}
+#if defined(CONFIG_ARCH_POSIX)
+	pbuf_native_addr_remap(pb);
+#endif
+
+	/* Initialize local copy of indexes. */
+	pb->data.wr_idx = 0;
+	pb->data.rd_idx = 0;
+
+	return 0;
+}
+
+int pbuf_write(struct pbuf *pb, const char *data, uint16_t len)
+{
+	if (pb == NULL || len == 0 || data == NULL) {
+		/* Incorrect call. */
+		return -EINVAL;
+	}
+
+	/* Invalidate rd_idx only, local wr_idx is used to increase buffer security. */
+	sys_cache_data_invd_range((void *)(pb->cfg->rd_idx_loc), sizeof(*(pb->cfg->rd_idx_loc)));
+	__sync_synchronize();
+
+	uint8_t *const data_loc = pb->cfg->data_loc;
+	const uint32_t blen = pb->cfg->len;
+	uint32_t rd_idx = *(pb->cfg->rd_idx_loc);
+	uint32_t wr_idx = pb->data.wr_idx;
+
+	/* wr_idx must always be aligned. */
+	__ASSERT_NO_MSG(IS_PTR_ALIGNED_BYTES(wr_idx, _PBUF_IDX_SIZE));
+	/* rd_idx shall always be aligned, but its value is received from the reader.
+	 * Can not assert.
+	 */
+	if (!IS_PTR_ALIGNED_BYTES(rd_idx, _PBUF_IDX_SIZE)) {
+		return -EINVAL;
+	}
+
+	uint32_t free_space = blen - idx_occupied(blen, wr_idx, rd_idx) - _PBUF_IDX_SIZE;
+
+	/* Packet length, data + packet length size. */
+	uint32_t plen = len + PBUF_PACKET_LEN_SZ;
+
+	/* Check if packet will fit into the buffer. */
+	if (free_space < plen) {
+		return -ENOMEM;
+	}
+
+	/* Clear packet len with zeros and update. Clearing is done for possible versioning in the
+	 * future. Writing is allowed now, because shared wr_idx value is updated at the very end.
+	 */
+	*((uint32_t *)(&data_loc[wr_idx])) = 0;
+	sys_put_be16(len, &data_loc[wr_idx]);
+	__sync_synchronize();
+	sys_cache_data_flush_range(&data_loc[wr_idx], PBUF_PACKET_LEN_SZ);
+
+	wr_idx = idx_wrap(blen, wr_idx + PBUF_PACKET_LEN_SZ);
+
+	/* Write until end of the buffer, if data will be wrapped. */
+	uint32_t tail = MIN(len, blen - wr_idx);
+
+	memcpy(&data_loc[wr_idx], data, tail);
+	sys_cache_data_flush_range(&data_loc[wr_idx], tail);
+
+	if (len > tail) {
+		/* Copy remaining data to buffer front. */
+		memcpy(&data_loc[0], data + tail, len - tail);
+		sys_cache_data_flush_range(&data_loc[0], len - tail);
+	}
+
+	wr_idx = idx_wrap(blen, ROUND_UP(wr_idx + len, _PBUF_IDX_SIZE));
+	/* Update wr_idx. */
+	pb->data.wr_idx = wr_idx;
+	*(pb->cfg->wr_idx_loc) = wr_idx;
+	__sync_synchronize();
+	sys_cache_data_flush_range((void *)pb->cfg->wr_idx_loc, sizeof(*(pb->cfg->wr_idx_loc)));
+
+	return len;
+}
+
+int pbuf_read(struct pbuf *pb, char *buf, uint16_t len)
+{
+	if (pb == NULL) {
+		/* Incorrect call. */
+		return -EINVAL;
+	}
+
+	/* Invalidate wr_idx only, local rd_idx is used to increase buffer security. */
+	sys_cache_data_invd_range((void *)(pb->cfg->wr_idx_loc), sizeof(*(pb->cfg->wr_idx_loc)));
+	__sync_synchronize();
+
+	uint8_t *const data_loc = pb->cfg->data_loc;
+	const uint32_t blen = pb->cfg->len;
+	uint32_t wr_idx = *(pb->cfg->wr_idx_loc);
+	uint32_t rd_idx = pb->data.rd_idx;
+
+	/* rd_idx must always be aligned. */
+	__ASSERT_NO_MSG(IS_PTR_ALIGNED_BYTES(rd_idx, _PBUF_IDX_SIZE));
+	/* wr_idx shall always be aligned, but its value is received from the
+	 * writer. Can not assert.
+	 */
+	if (!IS_PTR_ALIGNED_BYTES(wr_idx, _PBUF_IDX_SIZE)) {
+		return -EINVAL;
+	}
+
+	if (rd_idx == wr_idx) {
+		/* Buffer is empty. */
+		return 0;
+	}
+
+	/* Get packet len.*/
+	sys_cache_data_invd_range(&data_loc[rd_idx], PBUF_PACKET_LEN_SZ);
+	uint16_t plen = sys_get_be16(&data_loc[rd_idx]);
+
+	if (!buf) {
+		return (int)plen;
+	}
+
+	if (plen > len) {
+		return -ENOMEM;
+	}
+
+	uint32_t occupied_space = idx_occupied(blen, wr_idx, rd_idx);
+
+	if (occupied_space < plen + PBUF_PACKET_LEN_SZ) {
+		/* This should never happen. */
+		return -EAGAIN;
+	}
+
+	rd_idx = idx_wrap(blen, rd_idx + PBUF_PACKET_LEN_SZ);
+
+	/* Packet will fit into provided buffer, truncate len if provided len
+	 * is bigger than necessary.
+	 */
+	len = MIN(plen, len);
+
+	/* Read until end of the buffer, if data are wrapped. */
+	uint32_t tail = MIN(blen - rd_idx, len);
+
+	sys_cache_data_invd_range(&data_loc[rd_idx], tail);
+	memcpy(buf, &data_loc[rd_idx], tail);
+
+	if (len > tail) {
+		sys_cache_data_invd_range(&data_loc[0], len - tail);
+		memcpy(&buf[tail], &pb->cfg->data_loc[0], len - tail);
+	}
+
+	/* Update rd_idx. */
+	rd_idx = idx_wrap(blen, ROUND_UP(rd_idx + len, _PBUF_IDX_SIZE));
+
+	pb->data.rd_idx = rd_idx;
+	*(pb->cfg->rd_idx_loc) = rd_idx;
+	__sync_synchronize();
+	sys_cache_data_flush_range((void *)pb->cfg->rd_idx_loc, sizeof(*(pb->cfg->rd_idx_loc)));
+
+	return len;
+}
diff --git a/tests/subsys/ipc/ipc_sessions/interoperability/pbuf_v1.h b/tests/subsys/ipc/ipc_sessions/interoperability/pbuf_v1.h
new file mode 100644
index 00000000000..8783cdbbf14
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/interoperability/pbuf_v1.h
@@ -0,0 +1,234 @@
+/*
+ * Copyright (c) 2023 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_INCLUDE_IPC_PBUF_H_
+#define ZEPHYR_INCLUDE_IPC_PBUF_H_
+
+#include <zephyr/cache.h>
+#include <zephyr/devicetree.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Packed buffer API
+ * @defgroup pbuf Packed Buffer API
+ * @ingroup ipc
+ * @{
+ */
+
+/** @brief Size of packet length field. */
+#define PBUF_PACKET_LEN_SZ sizeof(uint32_t)
+
+/* Amount of data that is left unused to distinguish between empty and full. */
+#define _PBUF_IDX_SIZE sizeof(uint32_t)
+
+/* Minimal length of the data field in the buffer to store the smalest packet
+ * possible.
+ * (+1) for at least one byte of data.
+ * (+_PBUF_IDX_SIZE) to distinguish buffer full and buffer empty.
+ * Rounded up to keep wr/rd indexes pointing to aligned address.
+ */
+#define _PBUF_MIN_DATA_LEN ROUND_UP(PBUF_PACKET_LEN_SZ + 1 + _PBUF_IDX_SIZE, _PBUF_IDX_SIZE)
+
+#if defined(CONFIG_ARCH_POSIX)
+/* For the native simulated boards we need to modify some pointers at init */
+#define PBUF_MAYBE_CONST
+#else
+#define PBUF_MAYBE_CONST const
+#endif
+
+/** @brief Control block of packet buffer.
+ *
+ * The structure contains configuration data.
+ */
+struct pbuf_cfg {
+	volatile uint32_t *rd_idx_loc;	/* Address of the variable holding
+					 * index value of the first valid byte
+					 * in data[].
+					 */
+	volatile uint32_t *wr_idx_loc;	/* Address of the variable holding
+					 * index value of the first free byte
+					 * in data[].
+					 */
+	uint32_t dcache_alignment;	/* CPU data cache line size in bytes.
+					 * Used for validation - TODO: To be
+					 * replaced by flags.
+					 */
+	uint32_t len;			/* Length of data[] in bytes. */
+	uint8_t *data_loc;		/* Location of the data[]. */
+};
+
+/**
+ * @brief Data block of the packed buffer.
+ *
+ * The structure contains local copies of wr and rd indexes used by writer and
+ * reader respectively.
+ */
+struct pbuf_data {
+	volatile uint32_t wr_idx;	/* Index of the first holding first
+					 * free byte in data[]. Used for
+					 * writing.
+					 */
+	volatile uint32_t rd_idx;	/* Index of the first holding first
+					 * valid byte in data[]. Used for
+					 * reading.
+					 */
+};
+
+
+/**
+ * @brief Scure packed buffer.
+ *
+ * The packet buffer implements lightweight unidirectional packet
+ * buffer with read/write semantics on top of a memory region shared
+ * by the reader and writer. It embeds cache and memory barrier management to
+ * ensure correct data access.
+ *
+ * This structure supports single writer and reader. Data stored in the buffer
+ * is encapsulated to a message (with length header). The read/write API is
+ * written in a way to protect the data from being corrupted.
+ */
+struct pbuf {
+	PBUF_MAYBE_CONST struct pbuf_cfg *const cfg; /* Configuration of the
+						      * buffer.
+						      */
+	struct pbuf_data data;			/* Data used to read and write
+						 * to the buffer
+						 */
+};
+
+/**
+ * @brief Macro for configuration initialization.
+ *
+ * It is recommended to use this macro to initialize packed buffer
+ * configuration.
+ *
+ * @param mem_addr	Memory address for pbuf.
+ * @param size		Size of the memory.
+ * @param dcache_align	Data cache alignment.
+ */
+#define PBUF_CFG_INIT(mem_addr, size, dcache_align)					\
+{											\
+	.rd_idx_loc = (uint32_t *)(mem_addr),						\
+	.wr_idx_loc = (uint32_t *)((uint8_t *)(mem_addr) +				\
+				MAX(dcache_align, _PBUF_IDX_SIZE)),			\
+	.data_loc = (uint8_t *)((uint8_t *)(mem_addr) +					\
+				MAX(dcache_align, _PBUF_IDX_SIZE) + _PBUF_IDX_SIZE),	\
+	.len = (uint32_t)((uint32_t)(size) - MAX(dcache_align, _PBUF_IDX_SIZE) -	\
+				_PBUF_IDX_SIZE),					\
+	.dcache_alignment = (dcache_align),						\
+}
+
+/**
+ * @brief Macro calculates memory overhead taken by the header in shared memory.
+ *
+ * It contains the read index, write index and padding.
+ *
+ * @param dcache_align	Data cache alignment.
+ */
+#define PBUF_HEADER_OVERHEAD(dcache_align) \
+	(MAX(dcache_align, _PBUF_IDX_SIZE) + _PBUF_IDX_SIZE)
+
+/**
+ * @brief Statically define and initialize pbuf.
+ *
+ * @param name			Name of the pbuf.
+ * @param mem_addr		Memory address for pbuf.
+ * @param size			Size of the memory.
+ * @param dcache_align	Data cache line size.
+ */
+#define PBUF_DEFINE(name, mem_addr, size, dcache_align)					\
+	BUILD_ASSERT(dcache_align >= 0,							\
+			"Cache line size must be non negative.");			\
+	BUILD_ASSERT((size) > 0 && IS_PTR_ALIGNED_BYTES(size, _PBUF_IDX_SIZE),		\
+			"Incorrect size.");						\
+	BUILD_ASSERT(IS_PTR_ALIGNED_BYTES(mem_addr, MAX(dcache_align, _PBUF_IDX_SIZE)),	\
+			"Misaligned memory.");						\
+	BUILD_ASSERT(size >= (MAX(dcache_align, _PBUF_IDX_SIZE) + _PBUF_IDX_SIZE +	\
+			_PBUF_MIN_DATA_LEN), "Insufficient size.");			\
+	static PBUF_MAYBE_CONST struct pbuf_cfg cfg_##name =				\
+			PBUF_CFG_INIT(mem_addr, size, dcache_align);			\
+	static struct pbuf name = {							\
+		.cfg = &cfg_##name,							\
+	}
+
+/**
+ * @brief Initialize the Tx packet buffer.
+ *
+ * This function initializes the Tx packet buffer based on provided configuration.
+ * If the configuration is incorrect, the function will return error.
+ *
+ * It is recommended to use PBUF_DEFINE macro for build time initialization.
+ *
+ * @param pb	Pointer to the packed buffer containing
+ *		configuration and data. Configuration has to be
+ *		fixed before the initialization.
+ * @retval 0 on success.
+ * @retval -EINVAL when the input parameter is incorrect.
+ */
+int pbuf_tx_init(struct pbuf *pb);
+
+/**
+ * @brief Initialize the Rx packet buffer.
+ *
+ * This function initializes the Rx packet buffer.
+ * If the configuration is incorrect, the function will return error.
+ *
+ * It is recommended to use PBUF_DEFINE macro for build time initialization.
+ *
+ * @param pb	Pointer to the packed buffer containing
+ *		configuration and data. Configuration has to be
+ *		fixed before the initialization.
+ * @retval 0 on success.
+ * @retval -EINVAL when the input parameter is incorrect.
+ */
+int pbuf_rx_init(struct pbuf *pb);
+
+/**
+ * @brief Write specified amount of data to the packet buffer.
+ *
+ * This function call writes specified amount of data to the packet buffer if
+ * the buffer will fit the data.
+ *
+ * @param pb	A buffer to which to write.
+ * @param buf	Pointer to the data to be written to the buffer.
+ * @param len	Number of bytes to be written to the buffer. Must be positive.
+ * @retval int	Number of bytes written, negative error code on fail.
+ *		-EINVAL, if any of input parameter is incorrect.
+ *		-ENOMEM, if len is bigger than the buffer can fit.
+ */
+
+int pbuf_write(struct pbuf *pb, const char *buf, uint16_t len);
+
+/**
+ * @brief Read specified amount of data from the packet buffer.
+ *
+ * Single read allows to read the message send by the single write.
+ * The provided %p buf must be big enough to store the whole message.
+ *
+ * @param pb	A buffer from which data will be read.
+ * @param buf	Data pointer to which read data will be written.
+ *		If NULL, len of stored message is returned.
+ * @param len	Number of bytes to be read from the buffer.
+ * @retval int	Bytes read, negative error code on fail.
+ *		Bytes to be read, if buf == NULL.
+ *		-EINVAL, if any of input parameter is incorrect.
+ *		-ENOMEM, if message can not fit in provided buf.
+ *		-EAGAIN, if not whole message is ready yet.
+ */
+int pbuf_read(struct pbuf *pb, char *buf, uint16_t len);
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ZEPHYR_INCLUDE_IPC_PBUF_H_ */
diff --git a/tests/subsys/ipc/ipc_sessions/prj.conf b/tests/subsys/ipc/ipc_sessions/prj.conf
new file mode 100644
index 00000000000..7c1cdabe0ec
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/prj.conf
@@ -0,0 +1,9 @@
+# Copyright 2021 Carlo Caione <ccaione@baylibre.com>
+# SPDX-License-Identifier: Apache-2.0
+
+# We need rand_r function
+CONFIG_GNU_C_EXTENSIONS=y
+
+CONFIG_ZTEST=y
+CONFIG_IPC_SERVICE=y
+CONFIG_MBOX=y
diff --git a/tests/subsys/ipc/ipc_sessions/remote/CMakeLists.txt b/tests/subsys/ipc/ipc_sessions/remote/CMakeLists.txt
new file mode 100644
index 00000000000..1fa2d9c278b
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/remote/CMakeLists.txt
@@ -0,0 +1,19 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(remote_icmsg)
+
+zephyr_include_directories(../common)
+
+FILE(GLOB remote_sources src/*.c)
+target_sources(app PRIVATE ${remote_sources})
+
+zephyr_sources_ifdef(CONFIG_IPC_SERVICE_ICMSG_V1		../interoperability/icmsg_v1.c)
+zephyr_sources_ifdef(CONFIG_PBUF_V1				../interoperability/pbuf_v1.c)
+zephyr_sources_ifdef(CONFIG_IPC_SERVICE_BACKEND_ICMSG_V1	../interoperability/ipc_icmsg_v1.c)
diff --git a/tests/subsys/ipc/ipc_sessions/remote/Kconfig b/tests/subsys/ipc/ipc_sessions/remote/Kconfig
new file mode 100644
index 00000000000..169ab615a20
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/remote/Kconfig
@@ -0,0 +1,11 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+rsource "../interoperability/Kconfig"
+
+menu "Zephyr"
+source "Kconfig.zephyr"
+endmenu
diff --git a/tests/subsys/ipc/ipc_sessions/remote/boards/nrf5340dk_nrf5340_cpunet.overlay b/tests/subsys/ipc/ipc_sessions/remote/boards/nrf5340dk_nrf5340_cpunet.overlay
new file mode 100644
index 00000000000..95dffe367e4
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/remote/boards/nrf5340dk_nrf5340_cpunet.overlay
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &ipc0;
+
+/ {
+	 chosen {
+		 /delete-property/ zephyr,ipc_shm;
+	 };
+
+	 reserved-memory {
+		 /delete-node/ memory@20070000;
+
+		 sram_rx: memory@20070000 {
+			 reg = <0x20070000 0x8000>;
+		 };
+
+		 sram_tx: memory@20078000 {
+			 reg = <0x20078000 0x8000>;
+		 };
+	 };
+
+	 ipc0: ipc0 {
+		 compatible = "zephyr,ipc-icmsg";
+		 tx-region = <&sram_tx>;
+		 rx-region = <&sram_rx>;
+		 mboxes = <&mbox 0>, <&mbox 1>;
+		 mbox-names = "rx", "tx";
+		 dcache-alignment = <8>;
+		 unbound = "detect";
+		 status = "okay";
+	 };
+};
diff --git a/tests/subsys/ipc/ipc_sessions/remote/boards/nrf54h20dk_nrf54h20_cpuppr.conf b/tests/subsys/ipc/ipc_sessions/remote/boards/nrf54h20dk_nrf54h20_cpuppr.conf
new file mode 100644
index 00000000000..80e211dcedd
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/remote/boards/nrf54h20dk_nrf54h20_cpuppr.conf
@@ -0,0 +1 @@
+CONFIG_WATCHDOG=y
diff --git a/tests/subsys/ipc/ipc_sessions/remote/boards/nrf54h20dk_nrf54h20_cpuppr.overlay b/tests/subsys/ipc/ipc_sessions/remote/boards/nrf54h20dk_nrf54h20_cpuppr.overlay
new file mode 100644
index 00000000000..5728b0a1f32
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/remote/boards/nrf54h20dk_nrf54h20_cpuppr.overlay
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+ipc0: &cpuapp_cpuppr_ipc {
+	status = "okay";
+	unbound = "detect";
+};
+
+&cpuppr_vevif {
+	status = "okay";
+};
+
+&cpuapp_bellboard {
+	status = "okay";
+};
+
+&wdt131 {
+	status = "okay";
+};
+
+/ {
+	chosen {
+		/delete-property/ zephyr,bt-hci;
+	};
+
+	aliases {
+		watchdog0 = &wdt131;
+	};
+};
diff --git a/tests/subsys/ipc/ipc_sessions/remote/boards/nrf54h20dk_nrf54h20_cpurad.overlay b/tests/subsys/ipc/ipc_sessions/remote/boards/nrf54h20dk_nrf54h20_cpurad.overlay
new file mode 100644
index 00000000000..00e376b5df8
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/remote/boards/nrf54h20dk_nrf54h20_cpurad.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&uart135 {
+	/delete-property/ hw-flow-control;
+};
+
+&ipc0 {
+	compatible = "zephyr,ipc-icmsg";
+	/delete-property/ tx-blocks;
+	/delete-property/ rx-blocks;
+	unbound = "enable";
+};
diff --git a/tests/subsys/ipc/ipc_sessions/remote/prj.conf b/tests/subsys/ipc/ipc_sessions/remote/prj.conf
new file mode 100644
index 00000000000..78730ee7dd5
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/remote/prj.conf
@@ -0,0 +1,23 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+# We need rand_r function
+CONFIG_GNU_C_EXTENSIONS=y
+CONFIG_PRINTK=y
+CONFIG_EVENTS=y
+
+CONFIG_LOG=y
+CONFIG_LOG_ALWAYS_RUNTIME=y
+CONFIG_LOG_MODE_MINIMAL=y
+#CONFIG_LOG_PROCESS_THREAD_PRIORITY=-15
+#CONFIG_LOG_PROCESS_THREAD_CUSTOM_PRIORITY=y
+
+CONFIG_HEAP_MEM_POOL_SIZE=2048
+
+CONFIG_IPC_SERVICE=y
+CONFIG_IPC_SERVICE_LOG_LEVEL_INF=y
+
+CONFIG_MBOX=y
+CONFIG_WATCHDOG=y
+
+CONFIG_REBOOT=y
diff --git a/tests/subsys/ipc/ipc_sessions/remote/src/remote.c b/tests/subsys/ipc/ipc_sessions/remote/src/remote.c
new file mode 100644
index 00000000000..dd2b845587a
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/remote/src/remote.c
@@ -0,0 +1,452 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdlib.h>
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/ipc/ipc_service.h>
+#include <zephyr/drivers/watchdog.h>
+#include <zephyr/sys/reboot.h>
+
+#include <test_commands.h>
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(remote, LOG_LEVEL_INF);
+
+#define IPC_TEST_EV_REBOND 0x01
+#define IPC_TEST_EV_BOND   0x02
+#define IPC_TEST_EV_TXTEST 0x04
+
+static const struct device *ipc0_instance = DEVICE_DT_GET(DT_NODELABEL(ipc0));
+static volatile bool ipc0_bounded;
+K_SEM_DEFINE(bound_sem, 0, 1);
+K_EVENT_DEFINE(ipc_ev_req);
+
+struct ipc_xfer_params {
+	uint32_t blk_size;
+	uint32_t blk_cnt;
+	unsigned int seed;
+	int result;
+};
+
+static struct ipc_xfer_params ipc_rx_params;
+static struct ipc_xfer_params ipc_tx_params;
+
+static struct k_timer timer_reboot;
+static struct k_timer timer_rebond;
+
+static void ep_bound(void *priv);
+static void ep_unbound(void *priv);
+static void ep_recv(const void *data, size_t len, void *priv);
+static void ep_error(const char *message, void *priv);
+
+static struct ipc_ept_cfg ep_cfg = {
+	.cb = {
+		.bound = ep_bound,
+		.unbound = ep_unbound,
+		.received = ep_recv,
+		.error = ep_error
+	},
+};
+
+/**
+ * @brief Trying to reset by WDT
+ *
+ * @note If this function return, it means it fails
+ */
+static int reboot_by_wdt(void)
+{
+	int err;
+	static const struct device *const wdt =
+		COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(DT_ALIAS(watchdog0)),
+			    (DEVICE_DT_GET(DT_ALIAS(watchdog0))), (NULL));
+	static const struct wdt_timeout_cfg m_cfg_wdt = {
+		.callback = NULL,
+		.flags = WDT_FLAG_RESET_SOC,
+		.window.max = 10,
+	};
+	static const uint8_t wdt_options[] = {
+		WDT_OPT_PAUSE_HALTED_BY_DBG | WDT_OPT_PAUSE_IN_SLEEP,
+		WDT_OPT_PAUSE_IN_SLEEP,
+		0
+	};
+
+	if (!wdt) {
+		return -ENOTSUP;
+	}
+
+	if (!device_is_ready(wdt)) {
+		LOG_ERR("WDT device is not ready");
+		return -EIO;
+	}
+
+	err = wdt_install_timeout(wdt, &m_cfg_wdt);
+	if (err < 0) {
+		LOG_ERR("WDT install error");
+		return -EIO;
+	}
+
+	for (size_t i = 0; i < ARRAY_SIZE(wdt_options); ++i) {
+		err = wdt_setup(wdt, wdt_options[i]);
+		if (err < 0) {
+			LOG_ERR("Failed WDT setup with options = %u", wdt_options[i]);
+		} else {
+			/* We are ok with the configuration:
+			 * just wait for the WDT to trigger
+			 */
+			for (;;) {
+				k_cpu_idle();
+			}
+		}
+	}
+
+	return -EIO;
+}
+
+/**
+ * @brief Just force to reboot, anyway you find possible
+ */
+FUNC_NORETURN static void reboot_anyway(void)
+{
+	reboot_by_wdt();
+	/* If WDT restart fails - try another way */
+	sys_reboot(SYS_REBOOT_COLD);
+}
+
+static void ep_bound(void *priv)
+{
+	ipc0_bounded = true;
+	k_sem_give(&bound_sem);
+
+	LOG_INF("Endpoint bounded");
+}
+
+static void ep_unbound(void *priv)
+{
+	ipc0_bounded = false;
+	k_sem_give(&bound_sem);
+
+	LOG_INF("Endpoint unbounded");
+
+	/* Try to restore the connection */
+	k_event_set(&ipc_ev_req, IPC_TEST_EV_BOND);
+}
+
+static void ep_recv(const void *data, size_t len, void *priv)
+{
+	int ret;
+	const struct ipc_test_cmd *cmd = data;
+	struct ipc_ept *ep = priv;
+
+	if (len < sizeof(struct ipc_test_cmd)) {
+		LOG_ERR("The unexpected size of received data: %u < %u", len,
+			sizeof(struct ipc_test_cmd));
+		/* Dropping further processing */
+		return;
+	}
+
+	switch (cmd->cmd) {
+	case IPC_TEST_CMD_NONE:
+		LOG_INF("Command processing: NONE");
+		/* Ignore */
+		break;
+	case IPC_TEST_CMD_PING: {
+		LOG_INF("Command processing: PING");
+
+		static const struct ipc_test_cmd cmd_pong = {IPC_TEST_CMD_PONG};
+
+		ret = ipc_service_send(ep, &cmd_pong, sizeof(cmd_pong));
+		if (ret < 0) {
+			LOG_ERR("PONG response failed: %d", ret);
+		}
+		break;
+	}
+	case IPC_TEST_CMD_ECHO: {
+		LOG_INF("Command processing: ECHO");
+
+		struct ipc_test_cmd *cmd_rsp = k_malloc(len);
+
+		if (!cmd_rsp) {
+			LOG_ERR("ECHO response failed: memory allocation");
+			break;
+		}
+
+		cmd_rsp->cmd = IPC_TEST_CMD_ECHO_RSP;
+		memcpy(cmd_rsp->data, cmd->data, len - sizeof(struct ipc_test_cmd));
+		ret = ipc_service_send(ep, cmd_rsp, len);
+		k_free(cmd_rsp);
+		if (ret < 0) {
+			LOG_ERR("ECHO response failed: %d", ret);
+		}
+		break;
+	}
+	case IPC_TEST_CMD_REBOND: {
+		LOG_INF("Command processing: REBOOT");
+
+		struct ipc_test_cmd_rebond *cmd_rebond = (struct ipc_test_cmd_rebond *)cmd;
+
+		k_timer_start(&timer_rebond, K_MSEC(cmd_rebond->timeout_ms), K_FOREVER);
+		break;
+	}
+	case IPC_TEST_CMD_REBOOT: {
+		LOG_INF("Command processing: REBOOT");
+
+		struct ipc_test_cmd_reboot *cmd_reboot = (struct ipc_test_cmd_reboot *)cmd;
+
+		k_timer_start(&timer_reboot, K_MSEC(cmd_reboot->timeout_ms), K_FOREVER);
+		break;
+	}
+	case IPC_TEST_CMD_RXSTART: {
+		LOG_INF("Command processing: RXSTART");
+
+		struct ipc_test_cmd_xstart *cmd_rxstart = (struct ipc_test_cmd_xstart *)cmd;
+
+		ipc_rx_params.blk_size = cmd_rxstart->blk_size;
+		ipc_rx_params.blk_cnt = cmd_rxstart->blk_cnt;
+		ipc_rx_params.seed = cmd_rxstart->seed;
+		ipc_rx_params.result = 0;
+		break;
+	}
+	case IPC_TEST_CMD_TXSTART: {
+		LOG_INF("Command processing: TXSTART");
+
+		struct ipc_test_cmd_xstart *cmd_txstart = (struct ipc_test_cmd_xstart *)cmd;
+
+		ipc_tx_params.blk_size = cmd_txstart->blk_size;
+		ipc_tx_params.blk_cnt = cmd_txstart->blk_cnt;
+		ipc_tx_params.seed = cmd_txstart->seed;
+		ipc_tx_params.result = 0;
+		k_event_set(&ipc_ev_req, IPC_TEST_EV_TXTEST);
+		break;
+	}
+	case IPC_TEST_CMD_RXGET: {
+		LOG_INF("Command processing: RXGET");
+
+		int ret;
+		struct ipc_test_cmd_xstat cmd_stat = {
+			.base.cmd = IPC_TEST_CMD_XSTAT,
+			.blk_cnt = ipc_rx_params.blk_cnt,
+			.result = ipc_rx_params.result
+		};
+
+		ret = ipc_service_send(ep, &cmd_stat, sizeof(cmd_stat));
+		if (ret < 0) {
+			LOG_ERR("RXGET response send failed");
+		}
+		break;
+	}
+	case IPC_TEST_CMD_TXGET: {
+		LOG_INF("Command processing: TXGET");
+
+		int ret;
+		struct ipc_test_cmd_xstat cmd_stat = {
+			.base.cmd = IPC_TEST_CMD_XSTAT,
+			.blk_cnt = ipc_tx_params.blk_cnt,
+			.result = ipc_tx_params.result
+		};
+
+		ret = ipc_service_send(ep, &cmd_stat, sizeof(cmd_stat));
+		if (ret < 0) {
+			LOG_ERR("TXGET response send failed");
+		}
+		break;
+	}
+	case IPC_TEST_CMD_XDATA: {
+		if ((ipc_rx_params.blk_cnt % 1000) == 0) {
+			/* Logging only every N-th command not to slowdown the transfer too much */
+			LOG_INF("Command processing: XDATA (left: %u)", ipc_rx_params.blk_cnt);
+		}
+
+		/* Ignore if there is an error */
+		if (ipc_rx_params.result) {
+			LOG_ERR("There is error in Rx transfer already");
+			break;
+		}
+
+		if (len != ipc_rx_params.blk_size + offsetof(struct ipc_test_cmd, data)) {
+			LOG_ERR("Size mismatch");
+			ipc_rx_params.result = -EMSGSIZE;
+			break;
+		}
+
+		if (ipc_rx_params.blk_cnt <= 0) {
+			LOG_ERR("Data not expected");
+			ipc_rx_params.result = -EFAULT;
+			break;
+		}
+
+		/* Check the data */
+		for (size_t n = 0; n < ipc_rx_params.blk_size; ++n) {
+			uint8_t expected = (uint8_t)rand_r(&ipc_rx_params.seed);
+
+			if (cmd->data[n] != expected) {
+				LOG_ERR("Data value error at %u", n);
+				ipc_rx_params.result = -EINVAL;
+				break;
+			}
+		}
+
+		ipc_rx_params.blk_cnt -= 1;
+		break;
+	}
+	default:
+		LOG_ERR("Unhandled command: %u", cmd->cmd);
+		break;
+	}
+}
+
+static void ep_error(const char *message, void *priv)
+{
+	LOG_ERR("EP error: \"%s\"", message);
+}
+
+static int init_ipc(void)
+{
+	int ret;
+	static struct ipc_ept ep;
+
+	/* Store the pointer to the endpoint */
+	ep_cfg.priv = &ep;
+
+	LOG_INF("IPC-sessions test remote started");
+
+	ret = ipc_service_open_instance(ipc0_instance);
+	if ((ret < 0) && (ret != -EALREADY)) {
+		LOG_ERR("ipc_service_open_instance() failure: %d", ret);
+		return ret;
+	}
+
+	ret = ipc_service_register_endpoint(ipc0_instance, &ep, &ep_cfg);
+	if (ret < 0) {
+		LOG_ERR("ipc_service_register_endpoint() failure: %d", ret);
+		return ret;
+	}
+
+	do {
+		k_sem_take(&bound_sem, K_FOREVER);
+	} while (!ipc0_bounded);
+
+	LOG_INF("IPC connection estabilished");
+
+	return 0;
+}
+
+static void timer_rebond_cb(struct k_timer *timer)
+{
+	(void)timer;
+	LOG_INF("Setting rebond request");
+	k_event_set(&ipc_ev_req, IPC_TEST_EV_REBOND);
+}
+
+static void timer_reboot_cb(struct k_timer *timer)
+{
+	(void)timer;
+	LOG_INF("Resetting CPU");
+	reboot_anyway();
+	__ASSERT(0, "Still working after reboot request");
+}
+
+
+int main(void)
+{
+	int ret;
+
+	k_timer_init(&timer_rebond, timer_rebond_cb, NULL);
+	k_timer_init(&timer_reboot, timer_reboot_cb, NULL);
+	ret = init_ipc();
+	if (ret) {
+		return ret;
+	}
+
+	while (1) {
+		uint32_t ev;
+
+		ev = k_event_wait(&ipc_ev_req, ~0U, false, K_FOREVER);
+		k_event_clear(&ipc_ev_req, ev);
+
+		if (ev & IPC_TEST_EV_REBOND) {
+			/* Rebond now */
+			ret = ipc_service_deregister_endpoint(ep_cfg.priv);
+			if (ret) {
+				LOG_ERR("ipc_service_deregister_endpoint() failure: %d", ret);
+				continue;
+			}
+			ipc0_bounded = false;
+
+			ret = ipc_service_register_endpoint(ipc0_instance, ep_cfg.priv, &ep_cfg);
+			if (ret < 0) {
+				LOG_ERR("ipc_service_register_endpoint() failure: %d", ret);
+				return ret;
+			}
+
+			do {
+				k_sem_take(&bound_sem, K_FOREVER);
+			} while (!ipc0_bounded);
+		}
+		if (ev & IPC_TEST_EV_BOND) {
+			LOG_INF("Bonding endpoint");
+			/* Bond missing endpoint */
+			if (!ipc0_bounded) {
+				ret = ipc_service_register_endpoint(ipc0_instance, ep_cfg.priv,
+								    &ep_cfg);
+				if (ret < 0) {
+					LOG_ERR("ipc_service_register_endpoint() failure: %d", ret);
+					return ret;
+				}
+
+				do {
+					k_sem_take(&bound_sem, K_FOREVER);
+				} while (!ipc0_bounded);
+			}
+			LOG_INF("Bonding done");
+		}
+		if (ev & IPC_TEST_EV_TXTEST) {
+			LOG_INF("Transfer TX test started");
+
+			size_t cmd_size = ipc_tx_params.blk_size + offsetof(struct ipc_test_cmd,
+									    data);
+			struct ipc_test_cmd *cmd_data = k_malloc(cmd_size);
+
+			if (!cmd_data) {
+				LOG_ERR("Cannot create TX test buffer");
+				ipc_tx_params.result = -ENOMEM;
+				continue;
+			}
+
+			LOG_INF("Initial seed: %u", ipc_tx_params.seed);
+
+			cmd_data->cmd = IPC_TEST_CMD_XDATA;
+			for (/* No init */; ipc_tx_params.blk_cnt > 0; --ipc_tx_params.blk_cnt) {
+				int ret;
+
+				if (ipc_tx_params.blk_cnt % 1000 == 0) {
+					LOG_INF("Sending: %u blocks left", ipc_tx_params.blk_cnt);
+				}
+				/* Generate the block data */
+				for (size_t n = 0; n < ipc_tx_params.blk_size; ++n) {
+					cmd_data->data[n] = (uint8_t)rand_r(&ipc_tx_params.seed);
+				}
+				do {
+					ret = ipc_service_send(ep_cfg.priv, cmd_data, cmd_size);
+				} while (ret == -ENOMEM);
+				if (ret < 0) {
+					LOG_ERR("Cannot send TX test buffer: %d", ret);
+					ipc_tx_params.result = -EIO;
+					continue;
+				}
+			}
+
+			k_free(cmd_data);
+
+			LOG_INF("Transfer TX test finished");
+		}
+
+
+	}
+
+	return 0;
+}
diff --git a/tests/subsys/ipc/ipc_sessions/src/data_queue.c b/tests/subsys/ipc/ipc_sessions/src/data_queue.c
new file mode 100644
index 00000000000..03dc93257a3
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/src/data_queue.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include "data_queue.h"
+
+#define DATA_QUEUE_MEMORY_ALIGN sizeof(uint32_t)
+
+struct data_queue_format {
+	uint32_t header; /* Required by kernel k_queue_append */
+	size_t size;
+	uint32_t data[];
+};
+
+
+void data_queue_init(struct data_queue *q, void *mem, size_t bytes)
+{
+	k_heap_init(&q->h, mem, bytes);
+	k_queue_init(&q->q);
+}
+
+int data_queue_put(struct data_queue *q, const void *data, size_t bytes, k_timeout_t timeout)
+{
+	struct data_queue_format *buffer = k_heap_aligned_alloc(
+		&q->h,
+		DATA_QUEUE_MEMORY_ALIGN,
+		bytes + sizeof(struct data_queue_format),
+		timeout);
+
+	if (!buffer) {
+		return -ENOMEM;
+	}
+	buffer->size = bytes;
+	memcpy(buffer->data, data, bytes);
+
+	k_queue_append(&q->q, buffer);
+	return 0;
+}
+
+void *data_queue_get(struct data_queue *q, size_t *size, k_timeout_t timeout)
+{
+	struct data_queue_format *buffer = k_queue_get(&q->q, timeout);
+
+	if (!buffer) {
+		return NULL;
+	}
+
+	if (size) {
+		*size = buffer->size;
+	}
+	return buffer->data;
+}
+
+void data_queue_release(struct data_queue *q, void *data)
+{
+	struct data_queue_format *buffer = CONTAINER_OF(data, struct data_queue_format, data);
+
+	k_heap_free(&q->h, buffer);
+}
+
+int data_queue_is_empty(struct data_queue *q)
+{
+	return k_queue_is_empty(&q->q);
+}
diff --git a/tests/subsys/ipc/ipc_sessions/src/data_queue.h b/tests/subsys/ipc/ipc_sessions/src/data_queue.h
new file mode 100644
index 00000000000..5e5eef14c3e
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/src/data_queue.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef DATA_QUEUE_H
+#include <zephyr/kernel.h>
+
+
+struct data_queue {
+	struct k_queue q;
+	struct k_heap h;
+};
+
+void data_queue_init(struct data_queue *q, void *mem, size_t bytes);
+
+int data_queue_put(struct data_queue *q, const void *data, size_t bytes, k_timeout_t timeout);
+
+void *data_queue_get(struct data_queue *q, size_t *size, k_timeout_t timeout);
+
+void data_queue_release(struct data_queue *q, void *data);
+
+int data_queue_is_empty(struct data_queue *q);
+
+#endif /* DATA_QUEUE_H */
diff --git a/tests/subsys/ipc/ipc_sessions/src/main.c b/tests/subsys/ipc/ipc_sessions/src/main.c
new file mode 100644
index 00000000000..1215530e09f
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/src/main.c
@@ -0,0 +1,469 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdlib.h>
+#include <zephyr/kernel.h>
+#include <zephyr/device.h>
+#include <zephyr/ztest.h>
+#include <zephyr/ipc/ipc_service.h>
+
+#include <test_commands.h>
+#include "data_queue.h"
+
+#include <zephyr/logging/log.h>
+LOG_MODULE_REGISTER(ipc_sessions, LOG_LEVEL_INF);
+
+enum test_ipc_events {
+	TEST_IPC_EVENT_BOUNDED,
+	TEST_IPC_EVENT_UNBOUNDED,
+	TEST_IPC_EVENT_ERROR
+};
+
+struct test_ipc_event_state {
+	enum test_ipc_events ev;
+	struct ipc_ep *ep;
+};
+
+static const struct device *ipc0_instance = DEVICE_DT_GET(DT_NODELABEL(ipc0));
+static volatile bool ipc0_bounded;
+K_MSGQ_DEFINE(ipc_events, sizeof(struct test_ipc_event_state), 16, 4);
+
+static uint32_t data_queue_memory[ROUND_UP(CONFIG_IPC_TEST_MSG_HEAP_SIZE, sizeof(uint32_t))];
+static struct data_queue ipc_data_queue;
+
+struct test_cmd_xdata {
+	struct ipc_test_cmd base;
+	uint8_t data[CONFIG_IPC_TEST_BLOCK_SIZE];
+};
+
+static void (*ep_received_override_cb)(const void *data, size_t len, void *priv);
+
+static void ep_bound(void *priv)
+{
+	int ret;
+	struct test_ipc_event_state ev = {
+		.ev = TEST_IPC_EVENT_BOUNDED,
+		.ep = priv
+	};
+
+	ipc0_bounded = true;
+	ret = k_msgq_put(&ipc_events, &ev, K_NO_WAIT);
+	if (ret) {
+		LOG_ERR("Cannot put event in queue: %d", ret);
+	}
+}
+
+static void ep_unbound(void *priv)
+{
+	int ret;
+	struct test_ipc_event_state ev = {
+		.ev = TEST_IPC_EVENT_UNBOUNDED,
+		.ep = priv
+	};
+
+	ipc0_bounded = false;
+	ret = k_msgq_put(&ipc_events, &ev, K_NO_WAIT);
+	if (ret) {
+		LOG_ERR("Cannot put event in queue: %d", ret);
+	}
+}
+
+static void ep_recv(const void *data, size_t len, void *priv)
+{
+	int ret;
+
+	if (ep_received_override_cb) {
+		ep_received_override_cb(data, len, priv);
+	} else {
+		ret = data_queue_put(&ipc_data_queue, data, len, K_NO_WAIT);
+		__ASSERT(ret >= 0, "Cannot put data into queue: %d", ret);
+		(void)ret;
+	}
+}
+
+static void ep_error(const char *message, void *priv)
+{
+	int ret;
+	struct test_ipc_event_state ev = {
+		.ev = TEST_IPC_EVENT_ERROR,
+		.ep = priv
+	};
+
+	ret = k_msgq_put(&ipc_events, &ev, K_NO_WAIT);
+	if (ret) {
+		LOG_ERR("Cannot put event in queue: %d", ret);
+	}
+}
+
+static struct ipc_ept_cfg ep_cfg = {
+	.cb = {
+		.bound = ep_bound,
+		.unbound = ep_unbound,
+		.received = ep_recv,
+		.error = ep_error
+	},
+};
+
+static struct ipc_ept ep;
+
+
+
+/**
+ * @brief Estabilish connection before any test run
+ */
+void *test_suite_setup(void)
+{
+	int ret;
+	struct test_ipc_event_state ev;
+
+	data_queue_init(&ipc_data_queue, data_queue_memory, sizeof(data_queue_memory));
+
+	ret = ipc_service_open_instance(ipc0_instance);
+	zassert_true((ret >= 0) || ret == -EALREADY, "ipc_service_open_instance() failure: %d",
+		     ret);
+
+	/* Store the pointer to the endpoint */
+	ep_cfg.priv = &ep;
+	ret = ipc_service_register_endpoint(ipc0_instance, &ep, &ep_cfg);
+	zassert_true((ret >= 0), "ipc_service_register_endpoint() failure: %d", ret);
+
+	do {
+		ret = k_msgq_get(&ipc_events, &ev, K_MSEC(1000));
+		zassert_ok(ret, "Cannot bound to the remote interface");
+	} while (!ipc0_bounded);
+
+	return NULL;
+}
+
+/**
+ * @brief Prepare the test structures
+ */
+void test_suite_before(void *fixture)
+{
+	ep_received_override_cb = NULL;
+	k_msgq_purge(&ipc_events);
+}
+
+static void execute_test_ping_pong(void)
+{
+	int ret;
+	static const struct ipc_test_cmd cmd_ping = { IPC_TEST_CMD_PING };
+	struct ipc_test_cmd *cmd_rsp;
+	size_t cmd_rsp_size;
+
+	zassert_not_ok(data_queue_is_empty(&ipc_data_queue),
+		       "IPC data queue contains unexpected data");
+	/* Sending data */
+	ret = ipc_service_send(&ep, &cmd_ping, sizeof(cmd_ping));
+	zassert_equal(ret, sizeof(cmd_ping), "ipc_service_send failed: %d, expected: %u", ret,
+		      sizeof(cmd_ping));
+	/* Waiting for response */
+	cmd_rsp = data_queue_get(&ipc_data_queue, &cmd_rsp_size, K_MSEC(1000));
+	zassert_not_null(cmd_rsp, "No command response on time");
+	zassert_equal(cmd_rsp_size, sizeof(struct ipc_test_cmd),
+		      "Unexpected response size: %u, expected: %u", cmd_rsp_size,
+		      sizeof(struct ipc_test_cmd));
+	zassert_equal(cmd_rsp->cmd, IPC_TEST_CMD_PONG,
+		      "Unexpected response cmd value: %u, expected: %u", cmd_rsp->cmd,
+		      IPC_TEST_CMD_PONG);
+	data_queue_release(&ipc_data_queue, cmd_rsp);
+}
+
+ZTEST(ipc_sessions, test_ping_pong)
+{
+	execute_test_ping_pong();
+}
+
+ZTEST(ipc_sessions, test_echo)
+{
+	int ret;
+	static const struct ipc_test_cmd cmd_echo = {
+		IPC_TEST_CMD_ECHO, {'H', 'e', 'l', 'l', 'o', '!'}
+	};
+	struct ipc_test_cmd *cmd_rsp;
+	size_t cmd_rsp_size;
+
+	zassert_not_ok(data_queue_is_empty(&ipc_data_queue),
+		       "IPC data queue contains unexpected data");
+	/* Sending data */
+	ret = ipc_service_send(&ep, &cmd_echo, sizeof(cmd_echo));
+	zassert_equal(ret, sizeof(cmd_echo), "ipc_service_send failed: %d, expected: %u", ret,
+		      sizeof(cmd_echo));
+	/* Waiting for response */
+	cmd_rsp = data_queue_get(&ipc_data_queue, &cmd_rsp_size, K_MSEC(1000));
+	zassert_not_null(cmd_rsp, "No command response on time");
+	/* Checking response */
+	zassert_equal(cmd_rsp_size, sizeof(cmd_echo), "Unexpected response size: %u, expected: %u",
+		      cmd_rsp_size, sizeof(cmd_echo));
+	zassert_equal(cmd_rsp->cmd, IPC_TEST_CMD_ECHO_RSP,
+		      "Unexpected response cmd value: %u, expected: %u", cmd_rsp->cmd,
+		      IPC_TEST_CMD_ECHO_RSP);
+	zassert_mem_equal(cmd_rsp->data, cmd_echo.data,
+			  sizeof(cmd_echo) - sizeof(struct ipc_test_cmd),
+			  "Unexpected response content");
+	data_queue_release(&ipc_data_queue, cmd_rsp);
+}
+
+ZTEST(ipc_sessions, test_reboot)
+{
+	Z_TEST_SKIP_IFDEF(CONFIG_IPC_TEST_SKIP_UNBOUND);
+	Z_TEST_SKIP_IFDEF(CONFIG_IPC_TEST_SKIP_CORE_RESET);
+
+	int ret;
+	struct test_ipc_event_state ev;
+	static const struct ipc_test_cmd_reboot cmd_rebond = { { IPC_TEST_CMD_REBOOT }, 10 };
+
+	zassert_not_ok(data_queue_is_empty(&ipc_data_queue),
+		       "IPC data queue contains unexpected data");
+	/* Sending data */
+	ret = ipc_service_send(&ep, &cmd_rebond, sizeof(cmd_rebond));
+	zassert_equal(ret, sizeof(cmd_rebond), "ipc_service_send failed: %d, expected: %u", ret,
+		      sizeof(cmd_rebond));
+	/* Waiting for IPC to unbound */
+	ret = k_msgq_get(&ipc_events, &ev, K_MSEC(1000));
+	zassert_ok(ret, "No IPC unbound event on time");
+	zassert_equal(ev.ev, TEST_IPC_EVENT_UNBOUNDED, "Unexpected IPC event: %u, expected: %u",
+		      ev.ev, TEST_IPC_EVENT_UNBOUNDED);
+	zassert_equal_ptr(ev.ep, &ep, "Unexpected endpoint (unbound)");
+	/* Reconnecting */
+	ret = ipc_service_register_endpoint(ipc0_instance, &ep, &ep_cfg);
+	zassert_true((ret >= 0), "ipc_service_register_endpoint() failure: %d", ret);
+	/* Waiting for bound */
+	ret = k_msgq_get(&ipc_events, &ev, K_MSEC(1000));
+	zassert_ok(ret, "No IPC bound event on time");
+	zassert_equal(ev.ev, TEST_IPC_EVENT_BOUNDED, "Unexpected IPC event: %u, expected: %u",
+		      ev.ev, TEST_IPC_EVENT_UNBOUNDED);
+	zassert_equal_ptr(ev.ep, &ep, "Unexpected endpoint (bound)");
+
+	/* After reconnection - test communication */
+	execute_test_ping_pong();
+}
+
+ZTEST(ipc_sessions, test_rebond)
+{
+	Z_TEST_SKIP_IFDEF(CONFIG_IPC_TEST_SKIP_UNBOUND);
+
+	int ret;
+	struct test_ipc_event_state ev;
+	static const struct ipc_test_cmd_reboot cmd_rebond = { { IPC_TEST_CMD_REBOND }, 10 };
+
+	zassert_not_ok(data_queue_is_empty(&ipc_data_queue),
+		       "IPC data queue contains unexpected data");
+	/* Sending data */
+	ret = ipc_service_send(&ep, &cmd_rebond, sizeof(cmd_rebond));
+	zassert_equal(ret, sizeof(cmd_rebond), "ipc_service_send failed: %d, expected: %u", ret,
+		      sizeof(cmd_rebond));
+	/* Waiting for IPC to unbound */
+	ret = k_msgq_get(&ipc_events, &ev, K_MSEC(1000));
+	zassert_ok(ret, "No IPC unbound event on time");
+	zassert_equal(ev.ev, TEST_IPC_EVENT_UNBOUNDED, "Unexpected IPC event: %u, expected: %u",
+		      ev.ev, TEST_IPC_EVENT_UNBOUNDED);
+	zassert_equal_ptr(ev.ep, &ep, "Unexpected endpoint (unbound)");
+	/* Reconnecting */
+	ret = ipc_service_register_endpoint(ipc0_instance, &ep, &ep_cfg);
+	zassert_true((ret >= 0), "ipc_service_register_endpoint() failure: %d", ret);
+	/* Waiting for bound */
+	ret = k_msgq_get(&ipc_events, &ev, K_MSEC(1000));
+	zassert_ok(ret, "No IPC bound event on time");
+	zassert_equal(ev.ev, TEST_IPC_EVENT_BOUNDED, "Unexpected IPC event: %u, expected: %u",
+		      ev.ev, TEST_IPC_EVENT_UNBOUNDED);
+	zassert_equal_ptr(ev.ep, &ep, "Unexpected endpoint (bound)");
+
+	/* After reconnection - test communication */
+	execute_test_ping_pong();
+}
+
+ZTEST(ipc_sessions, test_local_rebond)
+{
+	Z_TEST_SKIP_IFDEF(CONFIG_IPC_TEST_SKIP_UNBOUND);
+
+	int ret;
+	struct test_ipc_event_state ev;
+
+	zassert_not_ok(data_queue_is_empty(&ipc_data_queue),
+		       "IPC data queue contains unexpected data");
+	/* Rebond locally */
+	ret = ipc_service_deregister_endpoint(ep_cfg.priv);
+	zassert_ok(ret, "ipc_service_deregister_endpoint() failure: %d", ret);
+	ipc0_bounded = false;
+
+	ret = ipc_service_register_endpoint(ipc0_instance, &ep, &ep_cfg);
+	zassert_true((ret >= 0), "ipc_service_register_endpoint() failure: %d", ret);
+	do {
+		ret = k_msgq_get(&ipc_events, &ev, K_MSEC(1000));
+		zassert_ok(ret, "Cannot bound to the remote interface");
+	} while (!ipc0_bounded);
+
+	/* After reconnection - test communication */
+	execute_test_ping_pong();
+}
+
+ZTEST(ipc_sessions, test_tx_long)
+{
+	#define SEED_TXSTART_VALUE 1
+	int ret;
+	static const struct ipc_test_cmd_xstart cmd_rxstart = {
+		.base = { .cmd = IPC_TEST_CMD_RXSTART },
+		.blk_size = CONFIG_IPC_TEST_BLOCK_SIZE,
+		.blk_cnt = CONFIG_IPC_TEST_BLOCK_CNT,
+		.seed = SEED_TXSTART_VALUE };
+	static const struct ipc_test_cmd cmd_rxget = { IPC_TEST_CMD_RXGET };
+	struct test_cmd_xdata cmd_txdata = { .base = { .cmd = IPC_TEST_CMD_XDATA } };
+	unsigned int seed = SEED_TXSTART_VALUE;
+
+	struct ipc_test_cmd_xstat *cmd_rxstat;
+	size_t cmd_rsp_size;
+
+	zassert_not_ok(data_queue_is_empty(&ipc_data_queue),
+		       "IPC data queue contains unexpected data");
+
+	/* Sending command for the remote to start receiving the data */
+	ret = ipc_service_send(&ep, &cmd_rxstart, sizeof(cmd_rxstart));
+	zassert_equal(ret, sizeof(cmd_rxstart), "ipc_service_send failed: %d, expected: %u", ret,
+		      sizeof(cmd_rxstart));
+	/* Check current status */
+	ret = ipc_service_send(&ep, &cmd_rxget, sizeof(cmd_rxget));
+	zassert_equal(ret, sizeof(cmd_rxget), "ipc_service_send failed: %d, expected: %u", ret,
+		      sizeof(cmd_rxget));
+	cmd_rxstat = data_queue_get(&ipc_data_queue, &cmd_rsp_size, K_MSEC(1000));
+	zassert_not_null(cmd_rxstat, "No command response on time");
+	zassert_equal(cmd_rsp_size, sizeof(*cmd_rxstat),
+		      "Unexpected response size: %u, expected: %u", cmd_rsp_size,
+		      sizeof(cmd_rxstat));
+	zassert_equal(cmd_rxstat->base.cmd, IPC_TEST_CMD_XSTAT,
+		      "Unexpected command in response: %u", cmd_rxstat->base.cmd);
+	zassert_ok(cmd_rxstat->result, "RX result not ok: %d", cmd_rxstat->result);
+	zassert_equal(cmd_rxstat->blk_cnt, cmd_rxstart.blk_cnt,
+		      "RX blk_cnt in status does not match start command: %u vs %u",
+		      cmd_rxstat->blk_cnt, cmd_rxstart.blk_cnt);
+	data_queue_release(&ipc_data_queue, cmd_rxstat);
+
+	/* Sending data */
+	for (size_t blk = 0; blk < cmd_rxstart.blk_cnt; ++blk) {
+		for (size_t n = 0; n < cmd_rxstart.blk_size; ++n) {
+			cmd_txdata.data[n] = (uint8_t)rand_r(&seed);
+		}
+		do {
+			ret = ipc_service_send(&ep, &cmd_txdata, sizeof(cmd_txdata));
+		} while (ret == -ENOMEM);
+		if ((blk % 1000) == 0) {
+			LOG_INF("Transfer number: %u of %u", blk, cmd_rxstart.blk_cnt);
+		}
+		zassert_equal(ret, sizeof(cmd_txdata), "ipc_service_send failed: %d, expected: %u",
+			      ret, sizeof(cmd_txdata));
+	}
+
+	/* Check current status */
+	ret = ipc_service_send(&ep, &cmd_rxget, sizeof(cmd_rxget));
+	zassert_equal(ret, sizeof(cmd_rxget), "ipc_service_send failed: %d, expected: %u", ret,
+		      sizeof(cmd_rxget));
+	cmd_rxstat = data_queue_get(&ipc_data_queue, &cmd_rsp_size, K_MSEC(1000));
+	zassert_not_null(cmd_rxstat, "No command response on time");
+	zassert_equal(cmd_rsp_size, sizeof(*cmd_rxstat),
+		      "Unexpected response size: %u, expected: %u", cmd_rsp_size,
+		      sizeof(cmd_rxstat));
+	zassert_equal(cmd_rxstat->base.cmd, IPC_TEST_CMD_XSTAT,
+		      "Unexpected command in response: %u", cmd_rxstat->base.cmd);
+	zassert_ok(cmd_rxstat->result, "RX result not ok: %d", cmd_rxstat->result);
+	zassert_equal(cmd_rxstat->blk_cnt, 0,
+		      "RX blk_cnt in status does not match start command: %u vs %u",
+		      cmd_rxstat->blk_cnt, 0);
+	data_queue_release(&ipc_data_queue, cmd_rxstat);
+}
+
+static struct {
+	unsigned int seed;
+	size_t blk_left;
+} test_rx_long_data;
+K_SEM_DEFINE(test_rx_long_sem, 0, 1);
+
+static void test_rx_long_rec_cb(const void *data, size_t len, void *priv)
+{
+	const struct test_cmd_xdata *cmd_rxdata = data;
+
+	zassert_true(test_rx_long_data.blk_left > 0, "No data left to interpret");
+	zassert_equal(len, sizeof(*cmd_rxdata),
+		      "Unexpected response size: %u, expected: %u", len, sizeof(*cmd_rxdata));
+	zassert_equal(cmd_rxdata->base.cmd, IPC_TEST_CMD_XDATA,
+		      "Unexpected command in response: %u", cmd_rxdata->base.cmd);
+	for (size_t n = 0; n < CONFIG_IPC_TEST_BLOCK_SIZE; ++n) {
+		uint8_t expected = (uint8_t)rand_r(&test_rx_long_data.seed);
+
+		zassert_equal(cmd_rxdata->data[n], expected,
+			      "Data mismatch at %u while %u blocks left", n,
+			      test_rx_long_data.blk_left);
+	}
+
+	if (test_rx_long_data.blk_left % 1000 == 0) {
+		LOG_INF("Receivng left: %u", test_rx_long_data.blk_left);
+	}
+	test_rx_long_data.blk_left -= 1;
+	if (test_rx_long_data.blk_left <= 0) {
+		LOG_INF("Interpretation marked finished");
+		ep_received_override_cb = NULL;
+		k_sem_give(&test_rx_long_sem);
+	}
+}
+
+ZTEST(ipc_sessions, test_rx_long)
+{
+	#define SEED_RXSTART_VALUE 1
+	int ret;
+	static const struct ipc_test_cmd_xstart cmd_txstart = {
+		.base = { .cmd = IPC_TEST_CMD_TXSTART },
+		.blk_size = CONFIG_IPC_TEST_BLOCK_SIZE,
+		.blk_cnt = CONFIG_IPC_TEST_BLOCK_CNT,
+		.seed = SEED_RXSTART_VALUE };
+	static const struct ipc_test_cmd cmd_txget = { IPC_TEST_CMD_TXGET };
+	struct ipc_test_cmd_xstat *cmd_txstat;
+	size_t cmd_rsp_size;
+
+	zassert_not_ok(data_queue_is_empty(&ipc_data_queue),
+		       "IPC data queue contains unexpected data");
+
+	/* Configuring the callback to interpret the incoming data */
+	test_rx_long_data.seed = SEED_RXSTART_VALUE;
+	test_rx_long_data.blk_left = cmd_txstart.blk_cnt;
+	ep_received_override_cb = test_rx_long_rec_cb;
+
+	/* Sending command for the remote to start sending the data */
+	ret = ipc_service_send(&ep, &cmd_txstart, sizeof(cmd_txstart));
+	zassert_equal(ret, sizeof(cmd_txstart), "ipc_service_send failed: %d, expected: %u", ret,
+		      sizeof(cmd_txstart));
+
+	/* Waiting for all the data */
+	ret = k_sem_take(&test_rx_long_sem, K_SECONDS(30));
+	LOG_INF("Interpretation finished");
+	zassert_ok(ret, "Incoming packet interpretation timeout");
+	zassert_is_null(ep_received_override_cb, "Seems like interpretation callback failed");
+
+	/* Check current status */
+	ret = ipc_service_send(&ep, &cmd_txget, sizeof(cmd_txget));
+	zassert_equal(ret, sizeof(cmd_txget), "ipc_service_send failed: %d, expected: %u", ret,
+		      sizeof(cmd_txget));
+	cmd_txstat = data_queue_get(&ipc_data_queue, &cmd_rsp_size, K_MSEC(1000));
+	zassert_not_null(cmd_txstat, "No command response on time");
+	zassert_equal(cmd_rsp_size, sizeof(*cmd_txstat),
+		      "Unexpected response size: %u, expected: %u", cmd_rsp_size,
+		      sizeof(cmd_txstat));
+	zassert_equal(cmd_txstat->base.cmd, IPC_TEST_CMD_XSTAT,
+		      "Unexpected command in response: %u", cmd_txstat->base.cmd);
+	zassert_ok(cmd_txstat->result, "RX result not ok: %d", cmd_txstat->result);
+	zassert_equal(cmd_txstat->blk_cnt, 0,
+		      "RX blk_cnt in status does not match start command: %u vs %u",
+		      cmd_txstat->blk_cnt, 0);
+	data_queue_release(&ipc_data_queue, cmd_txstat);
+}
+
+
+ZTEST_SUITE(
+	/* suite_name */              ipc_sessions,
+	/* ztest_suite_predicate_t */ NULL,
+	/* ztest_suite_setup_t */     test_suite_setup,
+	/* ztest_suite_before_t */    test_suite_before,
+	/* ztest_suite_after_t */     NULL,
+	/* ztest_suite_teardown_t */  NULL
+);
diff --git a/tests/subsys/ipc/ipc_sessions/sysbuild.cmake b/tests/subsys/ipc/ipc_sessions/sysbuild.cmake
new file mode 100644
index 00000000000..9aa0b80096b
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/sysbuild.cmake
@@ -0,0 +1,26 @@
+#
+# Copyright (c) 2024 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if("${SB_CONFIG_REMOTE_BOARD}" STREQUAL "")
+  message(FATAL_ERROR "REMOTE_BOARD must be set to a valid board name")
+endif()
+
+# Add remote project
+ExternalZephyrProject_Add(
+  APPLICATION remote
+  SOURCE_DIR ${APP_DIR}/remote
+  BOARD ${SB_CONFIG_REMOTE_BOARD}
+  BOARD_REVISION ${BOARD_REVISION}
+)
+set_property(GLOBAL APPEND PROPERTY PM_DOMAINS CPUNET)
+set_property(GLOBAL APPEND PROPERTY PM_CPUNET_IMAGES remote)
+set_property(GLOBAL PROPERTY DOMAIN_APP_CPUNET remote)
+set(CPUNET_PM_DOMAIN_DYNAMIC_PARTITION remote CACHE INTERNAL "")
+
+# Add a dependency so that the remote sample will be built and flashed first
+sysbuild_add_dependencies(CONFIGURE ${DEFAULT_IMAGE} remote)
+# Add dependency so that the remote image is flashed first.
+sysbuild_add_dependencies(FLASH ${DEFAULT_IMAGE} remote)
diff --git a/tests/subsys/ipc/ipc_sessions/sysbuild_cpuppr.conf b/tests/subsys/ipc/ipc_sessions/sysbuild_cpuppr.conf
new file mode 100644
index 00000000000..3b3ca1ea91f
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/sysbuild_cpuppr.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+SB_CONFIG_REMOTE_BOARD="nrf54h20dk/nrf54h20/cpuppr"
diff --git a/tests/subsys/ipc/ipc_sessions/testcase.yaml b/tests/subsys/ipc/ipc_sessions/testcase.yaml
new file mode 100644
index 00000000000..f76a61b8d68
--- /dev/null
+++ b/tests/subsys/ipc/ipc_sessions/testcase.yaml
@@ -0,0 +1,50 @@
+sample:
+  name: IPC Service integration test
+  description: IPC Service integration and efficiency test
+
+common:
+  sysbuild: true
+  tags: ipc ipc_sessions
+  harness: ztest
+
+tests:
+  sample.ipc.ipc_sessions.nrf5340dk:
+    platform_allow:
+      - nrf5340dk/nrf5340/cpuapp
+    integration_platforms:
+      - nrf5340dk/nrf5340/cpuapp
+  sample.ipc.ipc_sessions.nrf54h20dk_cpuapp_cpurad:
+    platform_allow:
+      - nrf54h20dk/nrf54h20/cpuapp
+    integration_platforms:
+      - nrf54h20dk/nrf54h20/cpuapp
+    extra_args:
+      - CONFIG_IPC_TEST_SKIP_CORE_RESET=y
+  sample.ipc.ipc_sessions.nrf54h20dk_cpuapp_cpuppr:
+    platform_allow:
+      - nrf54h20dk/nrf54h20/cpuapp
+    integration_platforms:
+      - nrf54h20dk/nrf54h20/cpuapp
+    extra_args:
+      - FILE_SUFFIX=cpuppr
+      - ipc_sessions_SNIPPET=nordic-ppr
+  sample.ipc.ipc_sessions.nrf54h20dk_cpuapp_no_unbound_cpuppr:
+    platform_allow:
+      - nrf54h20dk/nrf54h20/cpuapp
+    integration_platforms:
+      - nrf54h20dk/nrf54h20/cpuapp
+    extra_args:
+      - FILE_SUFFIX=cpuppr
+      - ipc_sessions_SNIPPET=nordic-ppr
+      - CONFIG_IPC_TEST_SKIP_UNBOUND=y
+      - CONFIG_IPC_SERVICE_BACKEND_ICMSG_V1=y
+  sample.ipc.ipc_sessions.nrf54h20dk_cpuapp_cpuppr_no_unbound:
+    platform_allow:
+      - nrf54h20dk/nrf54h20/cpuapp
+    integration_platforms:
+      - nrf54h20dk/nrf54h20/cpuapp
+    extra_args:
+      - FILE_SUFFIX=cpuppr
+      - ipc_sessions_SNIPPET=nordic-ppr
+      - CONFIG_IPC_TEST_SKIP_UNBOUND=y
+      - remote_CONFIG_IPC_SERVICE_BACKEND_ICMSG_V1=y
diff --git a/tests/subsys/ipc/pbuf/src/main.c b/tests/subsys/ipc/pbuf/src/main.c
index 4af9da68c47..4d563204cb0 100644
--- a/tests/subsys/ipc/pbuf/src/main.c
+++ b/tests/subsys/ipc/pbuf/src/main.c
@@ -48,7 +48,7 @@ ZTEST(test_pbuf, test_rw)
 	 * order to avoid clang complains about memory_area not being constant
 	 * expression.
 	 */
-	static PBUF_MAYBE_CONST struct pbuf_cfg cfg = PBUF_CFG_INIT(memory_area, MEM_AREA_SZ, 0);
+	static PBUF_MAYBE_CONST struct pbuf_cfg cfg = PBUF_CFG_INIT(memory_area, MEM_AREA_SZ, 0, 0);
 
 	static struct pbuf pb = {
 		.cfg = &cfg,
@@ -115,9 +115,11 @@ ZTEST(test_pbuf, test_retcodes)
 	 * order to avoid clang complains about memory_area not being constant
 	 * expression.
 	 */
-	static PBUF_MAYBE_CONST struct pbuf_cfg cfg0 = PBUF_CFG_INIT(memory_area, MEM_AREA_SZ, 32);
-	static PBUF_MAYBE_CONST struct pbuf_cfg cfg1 = PBUF_CFG_INIT(memory_area, MEM_AREA_SZ, 0);
-	static PBUF_MAYBE_CONST struct pbuf_cfg cfg2 = PBUF_CFG_INIT(memory_area, 20, 4);
+	static PBUF_MAYBE_CONST struct pbuf_cfg cfg0 = PBUF_CFG_INIT(memory_area, MEM_AREA_SZ,
+								     32, 0);
+	static PBUF_MAYBE_CONST struct pbuf_cfg cfg1 = PBUF_CFG_INIT(memory_area, MEM_AREA_SZ,
+								     0, 0);
+	static PBUF_MAYBE_CONST struct pbuf_cfg cfg2 = PBUF_CFG_INIT(memory_area, 20, 4, 0);
 
 	static struct pbuf pb0 = {
 		.cfg = &cfg0,
@@ -268,7 +270,7 @@ ZTEST(test_pbuf, test_stress)
 	 * order to avoid clang complains about buffer not being constant
 	 * expression.
 	 */
-	static PBUF_MAYBE_CONST struct pbuf_cfg cfg = PBUF_CFG_INIT(buffer, MEM_AREA_SZ, 4);
+	static PBUF_MAYBE_CONST struct pbuf_cfg cfg = PBUF_CFG_INIT(buffer, MEM_AREA_SZ, 4, 0);
 
 	static struct pbuf pb = {
 		.cfg = &cfg,
diff --git a/tests/subsys/jwt/testcase.yaml b/tests/subsys/jwt/testcase.yaml
index 8744d51bbd0..95ac8929baa 100644
--- a/tests/subsys/jwt/testcase.yaml
+++ b/tests/subsys/jwt/testcase.yaml
@@ -5,7 +5,7 @@ common:
   timeout: 120
   tags: jwt
   integration_platforms:
-    - frdm_k64f
+    - qemu_x86
   extra_configs:
     - CONFIG_TEST_RANDOM_GENERATOR=y
 tests:
diff --git a/tests/subsys/llext/CMakeLists.txt b/tests/subsys/llext/CMakeLists.txt
index de19cb0ac53..941d85d3af0 100644
--- a/tests/subsys/llext/CMakeLists.txt
+++ b/tests/subsys/llext/CMakeLists.txt
@@ -21,9 +21,11 @@ set(ext_names
 	relative_jump
 	object
 	syscalls
+	inspect
 	threads_kernel_objects
 	export_dependent
 	export_dependency
+	align
 )
 
 if(CONFIG_ARM)
@@ -45,10 +47,10 @@ if (NOT CONFIG_LLEXT_TYPE_ELF_SHAREDLIB)
     list(APPEND ext_names init_fini)
 endif()
 
-# generate extension targets foreach extension given by 'ext_names'
+# generate extension targets for each extension in 'ext_names'
 foreach(ext_name ${ext_names})
   set(ext_src ${PROJECT_SOURCE_DIR}/src/${ext_name}_ext.c)
-  set(ext_bin ${ZEPHYR_BINARY_DIR}/${ext_name}.llext)
+  set(ext_bin ${PROJECT_BINARY_DIR}/llext/${ext_name}.llext)
   set(ext_inc ${ZEPHYR_BINARY_DIR}/include/generated/${ext_name}.inc)
   add_llext_target(${ext_name}_ext
     OUTPUT  ${ext_bin}
@@ -59,10 +61,10 @@ endforeach()
 
 if(NOT CONFIG_LLEXT_TYPE_ELF_OBJECT)
   add_llext_target(multi_file_ext
-    OUTPUT  ${ZEPHYR_BINARY_DIR}/multi_file.llext
+    OUTPUT  ${PROJECT_BINARY_DIR}/llext/multi_file.llext
     SOURCES ${PROJECT_SOURCE_DIR}/src/multi_file_ext1.c ${PROJECT_SOURCE_DIR}/src/multi_file_ext2.c
   )
-  generate_inc_file_for_target(app ${ZEPHYR_BINARY_DIR}/multi_file.llext
+  generate_inc_file_for_target(app ${PROJECT_BINARY_DIR}/llext/multi_file.llext
     ${ZEPHYR_BINARY_DIR}/include/generated/multi_file.inc
   )
 endif()
@@ -75,7 +77,28 @@ if (CONFIG_LLEXT_TYPE_ELF_RELOCATABLE AND NOT CONFIG_ARM AND NOT CONFIG_RISCV)
     TARGET pre_located_ext
     POST_BUILD
     COMMAND ${CMAKE_C_COMPILER}
+    ${LLEXT_APPEND_FLAGS}
     -Wl,-r -Wl,-Ttext=0xbada110c -nostdlib -nodefaultlibs -nostartfiles
     $<TARGET_OBJECTS:${pre_located_target}> -o ${pre_located_file}
   )
 endif()
+
+if(NOT CONFIG_LLEXT_TYPE_ELF_OBJECT AND CONFIG_RISCV AND CONFIG_RISCV_ISA_EXT_C)
+  add_llext_target(riscv_edge_case_cb_type_ext
+    OUTPUT  ${PROJECT_BINARY_DIR}/llext/riscv_edge_case_cb_type_ext.llext
+    SOURCES ${PROJECT_SOURCE_DIR}/src/riscv_edge_case_cb_type.c ${PROJECT_SOURCE_DIR}/src/riscv_edge_case_cb_type_trigger.S
+  )
+  generate_inc_file_for_target(app ${PROJECT_BINARY_DIR}/llext/riscv_edge_case_cb_type_ext.llext
+    ${ZEPHYR_BINARY_DIR}/include/generated/riscv_edge_case_cb_type.inc
+  )
+endif()
+
+if(NOT CONFIG_LLEXT_TYPE_ELF_OBJECT AND CONFIG_RISCV)
+  add_llext_target(riscv_edge_case_non_paired_hi20_lo12_ext
+    OUTPUT  ${PROJECT_BINARY_DIR}/llext/riscv_edge_case_non_paired_hi20_lo12_ext.llext
+    SOURCES ${PROJECT_SOURCE_DIR}/src/riscv_edge_case_non_paired_hi20_lo12.c ${PROJECT_SOURCE_DIR}/src/riscv_edge_case_non_paired_hi20_lo12_trigger.S
+  )
+  generate_inc_file_for_target(app ${PROJECT_BINARY_DIR}/llext/riscv_edge_case_non_paired_hi20_lo12_ext.llext
+    ${ZEPHYR_BINARY_DIR}/include/generated/riscv_edge_case_non_paired_hi20_lo12.inc
+  )
+endif()
diff --git a/tests/subsys/llext/src/align_ext.c b/tests/subsys/llext/src/align_ext.c
new file mode 100644
index 00000000000..52bd36fe493
--- /dev/null
+++ b/tests/subsys/llext/src/align_ext.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2025 Arduino SA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * Define symbols with different alignment requirements and verify that LLEXT
+ * correctly handles them by testing the runtime address and the contents of
+ * each defined symbol.
+ */
+
+#include <stdint.h>
+#include <zephyr/kernel.h>
+#include <zephyr/llext/symbol.h>
+#include <zephyr/ztest_assert.h>
+
+/*
+ * Create constants requesting a specific alignment in memory and with a value
+ * that is related but not equal to their alignment requirement.
+ */
+#define ALIGNED_ENTRY(name, n) \
+	 const int name ## _ ## n __aligned(n) = n / 2 + 1
+
+ALIGNED_ENTRY(common, 8);
+ALIGNED_ENTRY(common, 16);
+ALIGNED_ENTRY(common, 32);
+ALIGNED_ENTRY(common, 64);
+ALIGNED_ENTRY(common, 128);
+ALIGNED_ENTRY(common, 256);
+ALIGNED_ENTRY(common, 512);
+
+/*
+ * Create similar constants in a set of independent sections to test merging.
+ */
+#define ALIGNED_SECT_ENTRY(name, n) \
+	Z_GENERIC_SECTION(name ## _sect_ ## n) ALIGNED_ENTRY(name, n)
+
+ALIGNED_SECT_ENTRY(independent, 8);
+ALIGNED_SECT_ENTRY(independent, 16);
+ALIGNED_SECT_ENTRY(independent, 32);
+ALIGNED_SECT_ENTRY(independent, 64);
+ALIGNED_SECT_ENTRY(independent, 128);
+ALIGNED_SECT_ENTRY(independent, 256);
+ALIGNED_SECT_ENTRY(independent, 512);
+
+/*
+ * Test that each symbol matches its expected value and alignment.
+ */
+#define ASSERT_ENTRY(name, n) \
+	zassert_equal(name ## _ ## n, n / 2 + 1); \
+	zassert_true(IS_ALIGNED(&name ## _ ## n, n))
+
+void test_entry(void)
+{
+	ASSERT_ENTRY(common, 8);
+	ASSERT_ENTRY(common, 16);
+	ASSERT_ENTRY(common, 32);
+	ASSERT_ENTRY(common, 64);
+	ASSERT_ENTRY(common, 128);
+	ASSERT_ENTRY(common, 256);
+	ASSERT_ENTRY(common, 512);
+
+	ASSERT_ENTRY(independent, 8);
+	ASSERT_ENTRY(independent, 16);
+	ASSERT_ENTRY(independent, 32);
+	ASSERT_ENTRY(independent, 64);
+	ASSERT_ENTRY(independent, 128);
+	ASSERT_ENTRY(independent, 256);
+	ASSERT_ENTRY(independent, 512);
+}
+EXPORT_SYMBOL(test_entry);
diff --git a/tests/subsys/llext/src/detached_fn_ext.c b/tests/subsys/llext/src/detached_fn_ext.c
index a1cbaa62d80..a112046e8cd 100644
--- a/tests/subsys/llext/src/detached_fn_ext.c
+++ b/tests/subsys/llext/src/detached_fn_ext.c
@@ -9,7 +9,7 @@
 #include <zephyr/sys/printk.h>
 #include <zephyr/ztest_assert.h>
 
-__section(".detach") void detached_entry(void)
+Z_GENERIC_SECTION(.detach) void detached_entry(void)
 {
 	static int data_cnt = -3;
 	static unsigned int bss_cnt;
diff --git a/tests/subsys/llext/src/init_fini_ext.c b/tests/subsys/llext/src/init_fini_ext.c
index 13cd4e741d7..258c907b089 100644
--- a/tests/subsys/llext/src/init_fini_ext.c
+++ b/tests/subsys/llext/src/init_fini_ext.c
@@ -49,14 +49,14 @@ static void fini_fn(void)
 	number |= 4;
 }
 
-static const void *const preinit_fn_ptrs[] __used Z_GENERIC_SECTION(".preinit_array") = {
+static const void *const preinit_fn_ptrs[] __used Z_GENERIC_SECTION(.preinit_array) = {
 	preinit_fn_1,
 	preinit_fn_2
 };
-static const void *const init_fn_ptrs[] __used Z_GENERIC_SECTION(".init_array") = {
+static const void *const init_fn_ptrs[] __used Z_GENERIC_SECTION(.init_array) = {
 	init_fn
 };
-static const void *const fini_fn_ptrs[] __used Z_GENERIC_SECTION(".fini_array") = {
+static const void *const fini_fn_ptrs[] __used Z_GENERIC_SECTION(.fini_array) = {
 	fini_fn
 };
 
diff --git a/tests/subsys/llext/src/inspect_ext.c b/tests/subsys/llext/src/inspect_ext.c
new file mode 100644
index 00000000000..97d09f99932
--- /dev/null
+++ b/tests/subsys/llext/src/inspect_ext.c
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2025 Arduino SA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* This extension exports a number of symbols to be used by the LLEXT
+ * inspection APIs. Each symbol is exported within a different section
+ * and only the addresses are checked in this test.
+ */
+
+#include <zephyr/llext/symbol.h>
+
+int number_in_bss;
+int number_in_data = 1;
+const int number_in_rodata = 2;
+const int number_in_my_rodata Z_GENERIC_SECTION(.my_rodata) = 3;
+
+void function_in_text(void)
+{
+	/* only used for address check */
+}
+
+EXPORT_SYMBOL(number_in_bss);
+EXPORT_SYMBOL(number_in_data);
+EXPORT_SYMBOL(number_in_rodata);
+EXPORT_SYMBOL(number_in_my_rodata);
+EXPORT_SYMBOL(function_in_text);
diff --git a/tests/subsys/llext/src/riscv_edge_case_cb_type.c b/tests/subsys/llext/src/riscv_edge_case_cb_type.c
new file mode 100644
index 00000000000..d9b341a8e4a
--- /dev/null
+++ b/tests/subsys/llext/src/riscv_edge_case_cb_type.c
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2024 CISPA Helmholtz Center for Information Security
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * This extension tests a relocation edge case in RISC-V:
+ * Immediates in branch/jump-type instructions are signed-extended.
+ * Thus, a jump with a negative offset can have a greater jump target than
+ * a jump with a positive offset.
+ * A compressed branch (cb-type) instruction is used to trigger the edge case.
+ * It has a 9-bit immediate (with an implicit LSB of 0), allowing it to jump
+ * 256 bytes backward and 254 bytes forward.
+ */
+
+#include <stdbool.h>
+#include <zephyr/llext/symbol.h>
+#include <zephyr/ztest_assert.h>
+
+extern int _riscv_edge_case_cb_trigger_forward(void);
+extern int _riscv_edge_case_cb_trigger_backward(void);
+
+void test_entry(void)
+{
+	int test_ok;
+
+	test_ok = _riscv_edge_case_cb_trigger_forward();
+	zassert_equal(test_ok, 0x1);
+
+	test_ok = _riscv_edge_case_cb_trigger_backward();
+	zassert_equal(test_ok, 0x1);
+}
+EXPORT_SYMBOL(test_entry);
diff --git a/tests/subsys/llext/src/riscv_edge_case_cb_type_trigger.S b/tests/subsys/llext/src/riscv_edge_case_cb_type_trigger.S
new file mode 100644
index 00000000000..2d931c44185
--- /dev/null
+++ b/tests/subsys/llext/src/riscv_edge_case_cb_type_trigger.S
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2024 CISPA Helmholtz Center for Information Security
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/toolchain.h>
+
+GTEXT(_riscv_edge_case_cb_trigger_backward)
+
+/*
+ * Tests that jumping 256 bytes (the maximum) backwards
+ * using CB-type instruction is feasible
+ */
+SECTION_FUNC(TEXT, _riscv_edge_case_cb_trigger_backward)
+    /*
+     * tentative fail
+     * this needs precise alignment - need explicit compressed instructions
+     */
+    addi a0, zero, 0
+    c.j _do_jump
+
+_backward_jump_target:
+
+    /*
+     * we need to force RISC-V compressed instructions for alignment
+     * this directive is standard in RISC-V, i.e., not toolchain-specific
+     */
+    .option push
+    .option rvc
+
+    /* we made it to the correct target - success, return true */
+    c.addi a0, 0x1
+    /* explicit compressed return */
+    c.jr ra
+
+
+    /*
+     * we need a distance of 256 bytes between _do_jump and _backward_jump_target to trigger
+     * the edge case (max jump distance for c.beqz)
+     * _backward_jump_target itself needs 4 bytes (two compressed instructions)
+     * so we need to insert 252 additional padding bytes
+     * we pad with return instructions here, causing the test to return 0 (failure)
+     */
+    .rept 126
+        /* explicit compressed return - 2 bytes */
+        c.jr ra
+    .endr
+
+_do_jump:
+    /* jump precisely 256 bytes, the maximum distance, backwards */
+    c.beqz a0, _backward_jump_target
+
+    /*
+     * in case we erroneously jump FORWARD instead of backwards,
+     * the jump ends in the following return sled and we return 0
+     * this indicates test failure
+     * note that maximum distance for jump forwards is 254 bytes,
+     * which is also the size of this sled
+     */
+    .rept 127
+        /* explicit compressed return - 2 bytes */
+        c.jr ra
+    .endr
+
+    /* assembler can decide whether to emit compressed instructions */
+    .option pop
+
+GTEXT(_riscv_edge_case_cb_trigger_forward)
+
+/*
+ * Tests that jumping 256 bytes (the maximum) forwards
+ * using CB-type instruction is feasible
+ */
+SECTION_FUNC(TEXT, _riscv_edge_case_cb_trigger_forward)
+    j _test_start
+
+    /* we need to force RISC-V compressed instructions for alignment */
+    .option push
+    .option rvc
+
+    /*
+     * in case the relocation is incorrect and the c.beqz jumps BACKWARDS,
+     * e.g., after arithmetic overflow, we jump into the following return sled
+     * the return sled is 256 bytes long, covering the maximum backward jump
+     */
+    .rept 128
+        /* explicit compressed return - 2 bytes */
+        c.jr ra
+    .endr
+
+_test_start:
+    /* tentative fail */
+    addi a0, zero, 0
+
+    /*
+     * jump precisely 254 bytes, the maximum distance, forwards
+     * in case the relocation is applied incorrectly, we jump into the padding bytes
+     * this causes test failure
+     * we cannot jump too far forwards, 254 bytes is the maximum distance
+     */
+    c.beqz a0, _forward_jump_target
+
+    /*
+     * need to insert 252 padding bytes to pad to 254 byte jump
+     * we pad with return instructions here, causing the test to return 0 (failure)
+     */
+    .rept 126
+        /* explicit compressed return - 2 bytes */
+        c.jr ra
+    .endr
+
+    /* assembler can decide whether to emit compressed instructions */
+    .option pop
+
+_forward_jump_target:
+    /* we made it to the correct target - success, return true */
+    li a0, 1
+    /* should not be reached - causes return false */
+    ret
diff --git a/tests/subsys/llext/src/riscv_edge_case_non_paired_hi20_lo12.c b/tests/subsys/llext/src/riscv_edge_case_non_paired_hi20_lo12.c
new file mode 100644
index 00000000000..990955b574b
--- /dev/null
+++ b/tests/subsys/llext/src/riscv_edge_case_non_paired_hi20_lo12.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2024 CISPA Helmholtz Center for Information Security
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/*
+ * This extension tests a relocation edge case in RISC-V:
+ * U-type instructions in conjunction with I-type/S-type instructions can be used to
+ * relocate symbols within a 32-bit range from the PC (medany code model) or 0
+ * (medlow code model).
+ * The compiler usually emits the U-type instructions and I-type/S-type instructions in sequence.
+ * However, this is not guaranteed.
+ * The accompanying assembly listing generates a scenario in which this assumption does NOT hold
+ * and tests that the llext loader can handle it.
+ */
+
+#include <stdbool.h>
+#include <zephyr/llext/symbol.h>
+#include <zephyr/ztest_assert.h>
+
+extern int _riscv_edge_case_non_paired_hi20_lo12(void);
+
+
+#define DATA_SEGMENT_SYMBOL_INITIAL 21
+#define DATA_SEGMENT_SYMBOL_EXPECTED (DATA_SEGMENT_SYMBOL_INITIAL+42)
+
+/* changed from the assembly script */
+volatile int _data_segment_symbol = DATA_SEGMENT_SYMBOL_INITIAL;
+
+
+void test_entry(void)
+{
+	int ret_value;
+
+	ret_value = _riscv_edge_case_non_paired_hi20_lo12();
+
+	zassert_equal(ret_value, DATA_SEGMENT_SYMBOL_INITIAL);
+
+	zassert_equal(_data_segment_symbol, DATA_SEGMENT_SYMBOL_EXPECTED);
+}
+EXPORT_SYMBOL(test_entry);
diff --git a/tests/subsys/llext/src/riscv_edge_case_non_paired_hi20_lo12_trigger.S b/tests/subsys/llext/src/riscv_edge_case_non_paired_hi20_lo12_trigger.S
new file mode 100644
index 00000000000..e6e059abdfe
--- /dev/null
+++ b/tests/subsys/llext/src/riscv_edge_case_non_paired_hi20_lo12_trigger.S
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2025 CISPA Helmholtz Center for Information Security
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/toolchain.h>
+
+/* 32-bit global defined in C */
+GDATA(_data_segment_symbol)
+
+GTEXT(_riscv_edge_case_non_paired_hi20_lo12)
+
+/*
+ * Tests an edge case in the RISC-V PSABI: In the medany and the medlow code models,
+ * the compiler emits auipc/lui (U-type) and ld/sw (I-type/S-type) instruction pairs
+ * for accessing a non-local symbol.
+ * The U-type instruction sets the upper 20 bits, the I/S-type the lower 12.
+ * Thus, any address in a 32-bit range from 0 (medlow) / the PC (medany) can be reached.
+ * Often, the U-type and I-type/S-type instruction pairs are adjacent in code.
+ * However, this need not be the case - compilers can re-use the upper 20 bits set by
+ * the U-type instruction with multiple I/S-type instructions, which is a useful optimization
+ * for multiple loads/stores of or within the same symbol.
+ * The U-type instruction can also appear after the I-type in code, e.g., due to control flow.
+ * When the U-type and I/S-type instructions are not in sequence, this triggers an edge case
+ * in the llext loader.
+ * This test triggers this edge case by loading a global, modifying it and storing it back.
+ */
+SECTION_FUNC(TEXT, _riscv_edge_case_non_paired_hi20_lo12)
+	/* jump beyond the I-type/load instruction initially to break sequence assumption */
+	j _do_utype
+
+_do_load:
+	/* re-use the upper-bit value set by the U-type below for a load */
+        lw    a0, %pcrel_lo(.LUtype)(a1)
+
+	addi t1, a0, 42
+
+	j _do_store
+
+_do_utype:
+	/* this u-type sets the higher 20 bits of the global */
+	.LUtype:  auipc a1, %pcrel_hi(_data_segment_symbol)
+
+	/* backwards jump to test loading */
+	j _do_load
+
+_do_store:
+
+	/* write the modified value back for the C code to check */
+	sw t1, %pcrel_lo(.LUtype)(a1)
+
+	/* return a0, i.e., the value we read, for the C code to check */
+	ret
diff --git a/tests/subsys/llext/src/test_llext.c b/tests/subsys/llext/src/test_llext.c
index 56f676c4e8f..90c9bfa02c9 100644
--- a/tests/subsys/llext/src/test_llext.c
+++ b/tests/subsys/llext/src/test_llext.c
@@ -13,6 +13,7 @@
 #endif
 #include <zephyr/llext/elf.h>
 #include <zephyr/llext/llext.h>
+#include <zephyr/llext/inspect.h>
 #include <zephyr/llext/symbol.h>
 #include <zephyr/llext/buf_loader.h>
 #include <zephyr/llext/fs_loader.h>
@@ -316,12 +317,98 @@ LLEXT_LOAD_UNLOAD(threads_kernel_objects,
 	.test_setup = threads_objects_test_setup,
 )
 
+static LLEXT_CONST uint8_t align_ext[] ELF_ALIGN = {
+	#include "align.inc"
+};
+LLEXT_LOAD_UNLOAD(align)
+
+static LLEXT_CONST uint8_t inspect_ext[] ELF_ALIGN = {
+	#include "inspect.inc"
+};
+
+void do_inspect_checks(struct llext_loader *ldr, struct llext *ext, enum llext_mem reg_idx,
+		       const char *sect_name, const char *sym_name)
+{
+	const elf_shdr_t *sect_hdr = NULL, *reg_hdr = NULL;
+	enum llext_mem sect_region = LLEXT_MEM_COUNT;
+	uintptr_t reg_addr = 0, sym_addr = 0;
+	size_t reg_size = 0, sect_offset = 0;
+	int sect_shndx, res;
+
+	res = llext_get_region_info(ldr, ext, reg_idx,
+				    &reg_hdr, (const void **)&reg_addr, &reg_size);
+	zassert_ok(res, "get_region_info() should succeed");
+	sect_shndx = llext_section_shndx(ldr, ext, sect_name);
+	zassert_true(sect_shndx > 0, "section %s should be found", sect_name);
+	res = llext_get_section_info(ldr, ext, sect_shndx,
+				     &sect_hdr, &sect_region, &sect_offset);
+	zassert_ok(res, "get_section_info() should succeed");
+	sym_addr = (uintptr_t)llext_find_sym(&ext->exp_tab, sym_name);
+	zassert_true(sym_addr, "symbol %s must be exported", sym_name);
+
+	zassert_equal(reg_idx, sect_region, "region mismatch (expected %d, got %d)",
+		      reg_idx, sect_region);
+	zassert_true(sect_hdr->sh_offset >= reg_hdr->sh_offset &&
+		     (sect_hdr->sh_offset + sect_hdr->sh_size <=
+		      reg_hdr->sh_offset + reg_hdr->sh_size),
+		     "section %s overflows its region %d", sect_name, reg_idx);
+	zassert_true(sect_offset < reg_size, "section offset outside region");
+	zassert_true(sym_addr >= reg_addr && sym_addr < reg_addr + reg_size,
+		     "symbol %s mapped outside region %d", sym_name, reg_idx);
+	zassert_true(sym_addr >= reg_addr + sect_offset &&
+		     sym_addr < reg_addr + sect_offset + sect_hdr->sh_size,
+		     "symbol %s mapped outside section %s", sym_name, sect_name);
+}
+
+ZTEST(llext, test_inspect)
+{
+	int res;
+
+	struct llext_buf_loader buf_loader =
+		LLEXT_BUF_LOADER(inspect_ext, sizeof(inspect_ext));
+	struct llext_loader *ldr = &buf_loader.loader;
+	struct llext_load_param ldr_parm = LLEXT_LOAD_PARAM_DEFAULT;
+	struct llext *ext = NULL;
+	size_t max_alloc_bytes;
+
+	ldr_parm.keep_section_info = true;
+	res = llext_load(ldr, "inspect", &ext, &ldr_parm);
+	zassert_ok(res, "load should succeed");
+
+	do_inspect_checks(ldr, ext, LLEXT_MEM_BSS, ".bss", "number_in_bss");
+	do_inspect_checks(ldr, ext, LLEXT_MEM_DATA, ".data", "number_in_data");
+	do_inspect_checks(ldr, ext, LLEXT_MEM_RODATA, ".rodata", "number_in_rodata");
+	do_inspect_checks(ldr, ext, LLEXT_MEM_RODATA, ".my_rodata", "number_in_my_rodata");
+	do_inspect_checks(ldr, ext, LLEXT_MEM_TEXT, ".text", "function_in_text");
+
+	max_alloc_bytes = ext->alloc_size;
+	llext_free_inspection_data(ldr, ext);
+	zassert_true(ext->alloc_size < max_alloc_bytes, "inspection data should be freed");
+
+	llext_unload(&ext);
+}
+
 #ifndef CONFIG_LLEXT_TYPE_ELF_OBJECT
 static LLEXT_CONST uint8_t multi_file_ext[] ELF_ALIGN = {
 	#include "multi_file.inc"
 };
 LLEXT_LOAD_UNLOAD(multi_file)
-#endif
+
+#if defined(CONFIG_RISCV) && defined(CONFIG_RISCV_ISA_EXT_C)
+static LLEXT_CONST uint8_t riscv_edge_case_cb_type_ext[] ELF_ALIGN = {
+	#include "riscv_edge_case_cb_type.inc"
+};
+LLEXT_LOAD_UNLOAD(riscv_edge_case_cb_type)
+#endif /* CONFIG_RISCV && CONFIG_RISCV_ISA_EXT_C */
+
+#if defined(CONFIG_RISCV)
+static LLEXT_CONST uint8_t riscv_edge_case_non_paired_hi20_lo12_ext[] ELF_ALIGN = {
+	#include "riscv_edge_case_non_paired_hi20_lo12.inc"
+};
+LLEXT_LOAD_UNLOAD(riscv_edge_case_non_paired_hi20_lo12)
+#endif /* CONFIG_RISCV */
+
+#endif /* !CONFIG_LLEXT_TYPE_ELF_OBJECT */
 
 #ifndef CONFIG_USERSPACE
 static LLEXT_CONST uint8_t export_dependent_ext[] ELF_ALIGN = {
diff --git a/tests/subsys/llext/testcase.yaml b/tests/subsys/llext/testcase.yaml
index 2d97da954cf..d97c85e10f7 100644
--- a/tests/subsys/llext/testcase.yaml
+++ b/tests/subsys/llext/testcase.yaml
@@ -7,6 +7,7 @@ common:
     - s32z2xxdc2/s32z270/rtu1 # See commit 18a0660
     # platforms that are always skipped by the runtime filter
     - qemu_cortex_m0
+    - mps2/an383
     - qemu_xtensa/dc233c/mmu
   integration_platforms:
     - qemu_cortex_a9          # ARM Cortex-A9 (ARMv7-A ISA)
@@ -18,6 +19,8 @@ common:
     - arch:arm64:CONFIG_LLEXT_HEAP_SIZE=128
   extra_conf_files:
     - prj.conf
+  min_ram: 172                # Size on arm: max: 145, min: 79
+  min_flash: 172              # Size on arm: max: 140, min: 105
 
 tests:
   # While there is in practice no value in compiling subsys/llext/*.c
@@ -41,7 +44,6 @@ tests:
     extra_configs:
       - CONFIG_LLEXT_STORAGE_WRITABLE=n
   llext.readonly_mpu:
-    min_ram: 128
     arch_allow: arm # Xtensa needs writable storage, currently not supported on RISC-V
     filter: CONFIG_ARCH_HAS_USERSPACE
     extra_configs:
@@ -123,3 +125,21 @@ tests:
       - CONFIG_LLEXT_STORAGE_WRITABLE=y
       - CONFIG_LLEXT_TYPE_ELF_RELOCATABLE=y
       - CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID=y
+
+  # Test the export device IDs by hash feature on a single architecture in
+  # both normal and SLID mode.
+  llext.devices_by_hash:
+    arch_allow: arm
+    filter: not CONFIG_MPU and not CONFIG_MMU
+    extra_conf_files: ['no_mem_protection.conf']
+    extra_configs:
+      - CONFIG_LLEXT_STORAGE_WRITABLE=n
+      - CONFIG_LLEXT_EXPORT_DEV_IDS_BY_HASH=y
+  llext.devices_by_hash_slid_linking:
+    arch_allow: arm
+    filter: not CONFIG_MPU and not CONFIG_MMU
+    extra_conf_files: ['no_mem_protection.conf']
+    extra_configs:
+      - CONFIG_LLEXT_STORAGE_WRITABLE=n
+      - CONFIG_LLEXT_EXPORT_DEV_IDS_BY_HASH=y
+      - CONFIG_LLEXT_EXPORT_BUILTINS_BY_SLID=y
diff --git a/tests/subsys/logging/log_backend_fs/CMakeLists.txt b/tests/subsys/logging/log_backend_fs/CMakeLists.txt
index 008ec7b354e..fcb3a3cf965 100644
--- a/tests/subsys/logging/log_backend_fs/CMakeLists.txt
+++ b/tests/subsys/logging/log_backend_fs/CMakeLists.txt
@@ -5,4 +5,17 @@ find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
 project(log_backend_fs_test)
 
 FILE(GLOB app_sources src/*.c)
-target_sources(app PRIVATE ${app_sources})
+target_sources(app PRIVATE
+  ${ZEPHYR_BASE}/subsys/logging/backends/log_backend_fs.c
+  ${app_sources}
+)
+
+target_compile_definitions(app PRIVATE
+  CONFIG_LOG_BACKEND_FS_OUTPUT_DEFAULT=0
+  CONFIG_LOG_BACKEND_FS_FILE_PREFIX="log."
+  CONFIG_LOG_BACKEND_FS_DIR="/lfs1"
+  CONFIG_LOG_BACKEND_FS_FILE_SIZE=128
+  CONFIG_LOG_BACKEND_FS_FILES_LIMIT=4
+  CONFIG_LOG_BACKEND_FS_OVERWRITE=1
+  CONFIG_LOG_BACKEND_FS_APPEND_TO_NEWEST_FILE=1
+)
diff --git a/tests/subsys/logging/log_backend_fs/Kconfig b/tests/subsys/logging/log_backend_fs/Kconfig
deleted file mode 100644
index d4188ef6f6f..00000000000
--- a/tests/subsys/logging/log_backend_fs/Kconfig
+++ /dev/null
@@ -1,8 +0,0 @@
-# Copyright (c) 2021 Nordic Semiconductor ASA
-# SPDX-License-Identifier: Apache-2.0
-
-config LOG_BACKEND_FS_TESTSUITE
-	bool
-	default y
-
-source "Kconfig.zephyr"
diff --git a/tests/subsys/logging/log_backend_fs/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/subsys/logging/log_backend_fs/boards/s32z2xxdc2_s32z270_rtu0.overlay
new file mode 100644
index 00000000000..7a568ac65e4
--- /dev/null
+++ b/tests/subsys/logging/log_backend_fs/boards/s32z2xxdc2_s32z270_rtu0.overlay
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+/ {
+	fstab {
+		compatible = "zephyr,fstab";
+		lfs1: lfs1 {
+			compatible = "zephyr,fstab,littlefs";
+			mount-point = "/lfs1";
+			partition = <&lfs1_part>;
+			read-size = <16>;
+			prog-size = <16>;
+			cache-size = <64>;
+			lookahead-size = <32>;
+			block-cycles = <512>;
+		};
+	};
+};
+
+&s26hs512t {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		lfs1_part: partition@0 {
+			label = "storage";
+			reg = <0x00000000 0x00010000>;
+		};
+	};
+};
diff --git a/tests/subsys/logging/log_backend_fs/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/subsys/logging/log_backend_fs/boards/s32z2xxdc2_s32z270_rtu1.overlay
new file mode 100644
index 00000000000..7a568ac65e4
--- /dev/null
+++ b/tests/subsys/logging/log_backend_fs/boards/s32z2xxdc2_s32z270_rtu1.overlay
@@ -0,0 +1,35 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+/ {
+	fstab {
+		compatible = "zephyr,fstab";
+		lfs1: lfs1 {
+			compatible = "zephyr,fstab,littlefs";
+			mount-point = "/lfs1";
+			partition = <&lfs1_part>;
+			read-size = <16>;
+			prog-size = <16>;
+			cache-size = <64>;
+			lookahead-size = <32>;
+			block-cycles = <512>;
+		};
+	};
+};
+
+&s26hs512t {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		lfs1_part: partition@0 {
+			label = "storage";
+			reg = <0x00000000 0x00010000>;
+		};
+	};
+};
diff --git a/tests/subsys/logging/log_backend_fs/prj.conf b/tests/subsys/logging/log_backend_fs/prj.conf
index 6ea2195cd8f..a86565811b0 100644
--- a/tests/subsys/logging/log_backend_fs/prj.conf
+++ b/tests/subsys/logging/log_backend_fs/prj.conf
@@ -2,12 +2,6 @@ CONFIG_ZTEST=y
 CONFIG_ASSERT=y
 CONFIG_TEST_LOGGING_DEFAULTS=n
 
-CONFIG_LOG=y
-CONFIG_LOG_BACKEND_FS=y
-CONFIG_LOG_BACKEND_FS_FILE_SIZE=128
-CONFIG_LOG_BACKEND_FS_FILES_LIMIT=4
-CONFIG_LOG_MAX_LEVEL=0
-
 CONFIG_FLASH=y
 CONFIG_FLASH_MAP=y
 CONFIG_FILE_SYSTEM=y
diff --git a/tests/subsys/logging/log_backend_fs/src/log_fs_test.c b/tests/subsys/logging/log_backend_fs/src/log_fs_test.c
index 6921f1e6451..fdb4362c0a4 100644
--- a/tests/subsys/logging/log_backend_fs/src/log_fs_test.c
+++ b/tests/subsys/logging/log_backend_fs/src/log_fs_test.c
@@ -15,6 +15,8 @@
 #include <zephyr/kernel.h>
 #include <zephyr/ztest.h>
 #include <zephyr/fs/fs.h>
+#include <zephyr/fff.h>
+#include <zephyr/logging/log_backend.h>
 
 #define DT_DRV_COMPAT zephyr_fstab_littlefs
 #define TEST_AUTOMOUNT DT_PROP(DT_DRV_INST(0), automount)
@@ -27,6 +29,11 @@ FS_FSTAB_DECLARE_ENTRY(PARTITION_NODE);
 #define MAX_PATH_LEN (256 + 7)
 
 static const char *log_prefix = CONFIG_LOG_BACKEND_FS_FILE_PREFIX;
+static const struct log_backend *backend;
+
+DEFINE_FFF_GLOBALS;
+FAKE_VOID_FUNC(log_output_dropped_process, const struct log_output *, uint32_t);
+FAKE_VALUE_FUNC(log_format_func_t, log_format_func_t_get, uint32_t);
 
 int write_log_to_file(uint8_t *data, size_t length, void *ctx);
 
@@ -97,6 +104,7 @@ ZTEST(test_log_backend_fs, test_log_fs_file_content)
 	fs_file_t_init(&file);
 
 	rc = write_log_to_file(to_log, sizeof(to_log), NULL);
+	backend->api->notify(backend, LOG_BACKEND_EVT_PROCESS_THREAD_DONE, NULL);
 
 	sprintf(fname, "%s/%s0000", CONFIG_LOG_BACKEND_FS_DIR, log_prefix);
 
@@ -112,7 +120,9 @@ ZTEST(test_log_backend_fs, test_log_fs_file_content)
 	zassert_equal(fs_close(&file), 0, "Can not close log file.");
 
 	to_log[sizeof(to_log)-2] = '2';
+
 	rc = write_log_to_file(to_log, sizeof(to_log), NULL);
+	backend->api->notify(backend, LOG_BACKEND_EVT_PROCESS_THREAD_DONE, NULL);
 
 	zassert_equal(fs_open(&file, fname, FS_O_READ), 0,
 		      "Can not open log file.");
@@ -154,6 +164,8 @@ ZTEST(test_log_backend_fs, test_log_fs_file_size)
 		ARG_UNUSED(rc);
 	}
 
+	backend->api->notify(backend, LOG_BACKEND_EVT_PROCESS_THREAD_DONE, NULL);
+
 	zassert_equal(fs_stat(fname, &entry), 0, "Can not get file info.");
 	size_t exp_size = CONFIG_LOG_BACKEND_FS_FILE_SIZE -
 			  (CONFIG_LOG_BACKEND_FS_FILE_SIZE - entry.size) %
@@ -208,6 +220,8 @@ ZTEST(test_log_backend_fs, test_log_fs_files_max)
 		ARG_UNUSED(rc);
 	}
 
+	backend->api->notify(backend, LOG_BACKEND_EVT_PROCESS_THREAD_DONE, NULL);
+
 	rc = fs_opendir(&dir, CONFIG_LOG_BACKEND_FS_DIR);
 	zassert_equal(rc, 0, "Can not open directory.");
 	/* Count log files. */
@@ -230,4 +244,26 @@ ZTEST(test_log_backend_fs, test_log_fs_files_max)
 	zassert_equal(test_mask, 0b11110, "Unexpected file numeration");
 }
 
-ZTEST_SUITE(test_log_backend_fs, NULL, NULL, NULL, NULL, NULL);
+static const struct log_backend *backend_find(char const *name)
+{
+	size_t slen = strlen(name);
+
+	STRUCT_SECTION_FOREACH(log_backend, backend) {
+		if (strncmp(name, backend->name, slen) == 0) {
+			return backend;
+		}
+	}
+
+	return NULL;
+}
+
+
+void *suite_setup(void)
+{
+	backend = backend_find("log_backend_fs");
+	zassert_not_null(backend);
+
+	return NULL;
+}
+
+ZTEST_SUITE(test_log_backend_fs, NULL, suite_setup, NULL, NULL, NULL);
diff --git a/tests/subsys/logging/log_backend_fs/testcase.yaml b/tests/subsys/logging/log_backend_fs/testcase.yaml
index af3eb759fbd..b217912743e 100644
--- a/tests/subsys/logging/log_backend_fs/testcase.yaml
+++ b/tests/subsys/logging/log_backend_fs/testcase.yaml
@@ -12,6 +12,10 @@ common:
     - native_sim/native/64
     - nrf52840dk/nrf52840
     - mr_canhubk3
+    - s32z2xxdc2/s32z270/rtu0
+    - s32z2xxdc2/s32z270/rtu1
+    - s32z2xxdc2@D/s32z270/rtu0
+    - s32z2xxdc2@D/s32z270/rtu1
   integration_platforms:
     - native_sim
 tests:
diff --git a/tests/subsys/logging/log_core_additional/log_user.conf b/tests/subsys/logging/log_core_additional/log_user.conf
index ae3240c0e21..1f1c1609934 100644
--- a/tests/subsys/logging/log_core_additional/log_user.conf
+++ b/tests/subsys/logging/log_core_additional/log_user.conf
@@ -5,9 +5,11 @@ CONFIG_TEST_LOGGING_DEFAULTS=n
 CONFIG_LOG=y
 CONFIG_LOG_OUTPUT=y
 CONFIG_LOG_RUNTIME_FILTERING=y
+CONFIG_LOG_ALWAYS_RUNTIME=y
 CONFIG_LOG_PROCESS_THREAD=n
 CONFIG_LOG_PROCESS_TRIGGER_THRESHOLD=1
 CONFIG_THREAD_MONITOR=y
-CONFIG_LOG_PRINTK=y
+CONFIG_LOG_PRINTK=n
 CONFIG_LOG_BLOCK_IN_THREAD=y
 CONFIG_MAIN_STACK_SIZE=4096
+CONFIG_STACK_SENTINEL=n
diff --git a/tests/subsys/logging/log_core_additional/src/log_test.c b/tests/subsys/logging/log_core_additional/src/log_test.c
index 1af13cb5622..5dcc783ca22 100644
--- a/tests/subsys/logging/log_core_additional/src/log_test.c
+++ b/tests/subsys/logging/log_core_additional/src/log_test.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2020 Intel Corporation
+ * Copyright (c) 2020-2025 Intel Corporation
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -20,6 +20,7 @@
 #include <zephyr/logging/log.h>
 #include <zephyr/logging/log_output.h>
 #include <zephyr/sys/iterable_sections.h>
+#include <zephyr/sys/libc-hooks.h>
 
 #define TEST_MESSAGE "test msg"
 
@@ -33,6 +34,18 @@ ZTEST_BMEM uint32_t source_id;
 ZTEST_BMEM uint8_t domain, level;
 ZTEST_DMEM uint32_t msg_data = 0x1234;
 
+/* Memory domain for tests with threads in user space (ZTEST_USER) */
+#if CONFIG_USERSPACE
+static struct k_mem_domain mem_domain;
+static struct k_mem_partition *mem_parts[] = {
+#if Z_LIBC_PARTITION_EXISTS
+	&z_libc_partition,
+#endif
+	&ztest_mem_partition,
+	&k_log_partition
+};
+#endif
+
 static uint8_t buf;
 static int char_out(uint8_t *data, size_t length, void *ctx)
 {
@@ -95,13 +108,6 @@ static void process(const struct log_backend *const backend,
 			      "Unexpected log severity");
 	}
 
-	cb->counter++;
-	if (IS_ENABLED(CONFIG_LOG_PROCESS_THREAD)) {
-		if (cb->counter == cb->total_logs) {
-			k_sem_give(&log_sem);
-		}
-	}
-
 	if (k_is_user_context()) {
 		zassert_equal(log_msg_get_domain(&(msg->log)), domain,
 				"Unexpected domain id");
@@ -112,6 +118,13 @@ static void process(const struct log_backend *const backend,
 
 	flags = log_backend_std_get_flags();
 	log_output_msg_process(&log_output, &msg->log, flags);
+
+	cb->counter++;
+	if (IS_ENABLED(CONFIG_LOG_PROCESS_THREAD)) {
+		if (cb->counter == cb->total_logs) {
+			k_sem_give(&log_sem);
+		}
+	}
 }
 
 static void panic(const struct log_backend *const backend)
@@ -171,6 +184,7 @@ static void log_setup(bool backend2_enable)
 static bool log_test_process(void)
 {
 	if (IS_ENABLED(CONFIG_LOG_PROCESS_THREAD)) {
+		log_flush();
 		/* waiting for all logs have been handled */
 		k_sem_take(&log_sem, K_FOREVER);
 		return false;
@@ -277,7 +291,7 @@ ZTEST(test_log_core_additional, test_log_early_logging)
 		LOG_WRN("log warn before backend active");
 		LOG_ERR("log error before backend active");
 
-		TC_PRINT("Activate backend with context");
+		TC_PRINT("Activate backend with context\n");
 		memset(&backend1_cb, 0, sizeof(backend1_cb));
 		backend1_cb.total_logs = 3;
 		log_backend_enable(&backend1, &backend1_cb, LOG_LEVEL_DBG);
@@ -381,7 +395,7 @@ ZTEST(test_log_core_additional, test_multiple_backends)
 {
 	int cnt;
 
-	TC_PRINT("Test multiple backends");
+	TC_PRINT("Test multiple backends\n");
 	/* enable both backend1 and backend2 */
 	log_setup(true);
 	STRUCT_SECTION_COUNT(log_backend, &cnt);
@@ -570,6 +584,12 @@ static void *test_log_core_additional_setup(void)
 #ifdef CONFIG_LOG_PROCESS_THREAD
 	k_thread_foreach(promote_log_thread, NULL);
 #endif
+
+#if CONFIG_USERSPACE
+	/* Set memory domain for threads in user space */
+	k_mem_domain_init(&mem_domain, ARRAY_SIZE(mem_parts), mem_parts);
+	k_mem_domain_add_thread(&mem_domain, k_current_get());
+#endif
 	return NULL;
 }
 
diff --git a/tests/subsys/logging/log_core_additional/testcase.yaml b/tests/subsys/logging/log_core_additional/testcase.yaml
index 3fc9db4902a..3ce2648b26d 100644
--- a/tests/subsys/logging/log_core_additional/testcase.yaml
+++ b/tests/subsys/logging/log_core_additional/testcase.yaml
@@ -14,3 +14,11 @@ tests:
     extra_args: CONF_FILE=log_thread.conf
     integration_platforms:
       - native_sim
+  logging.log_user:
+    tags: logging
+    filter: CONFIG_USERSPACE
+    extra_args:
+      - CONF_FILE=log_user.conf
+      - USERSPACE_TEST=1
+    integration_platforms:
+      - qemu_x86
diff --git a/tests/subsys/logging/log_frontend_stmesp_demux/testcase.yaml b/tests/subsys/logging/log_frontend_stmesp_demux/testcase.yaml
index 8614b252b13..3c00beca607 100644
--- a/tests/subsys/logging/log_frontend_stmesp_demux/testcase.yaml
+++ b/tests/subsys/logging/log_frontend_stmesp_demux/testcase.yaml
@@ -1,5 +1,7 @@
 common:
   filter: not CONFIG_BIG_ENDIAN
+  tags:
+    - coresight_stm
 tests:
   debug.coresight.stp_demux:
     integration_platforms:
diff --git a/tests/subsys/logging/log_stack/CMakeLists.txt b/tests/subsys/logging/log_stack/CMakeLists.txt
deleted file mode 100644
index 02a65e67cd8..00000000000
--- a/tests/subsys/logging/log_stack/CMakeLists.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-# SPDX-License-Identifier: Apache-2.0
-
-cmake_minimum_required(VERSION 3.20.0)
-find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
-project(log_stack)
-
-target_sources(app PRIVATE src/main.c)
-if(CONFIG_CPP)
-  # When testing for C++ force test file C++ compilation
-  set_source_files_properties(src/main.c PROPERTIES LANGUAGE CXX)
-endif()
diff --git a/tests/subsys/logging/log_stack/prj.conf b/tests/subsys/logging/log_stack/prj.conf
deleted file mode 100644
index c323d2513c3..00000000000
--- a/tests/subsys/logging/log_stack/prj.conf
+++ /dev/null
@@ -1,11 +0,0 @@
-CONFIG_ZTEST=y
-CONFIG_ASSERT=y
-
-CONFIG_TEST_LOGGING_DEFAULTS=n
-CONFIG_LOG=y
-CONFIG_INIT_STACKS=y
-CONFIG_THREAD_STACK_INFO=y
-
-CONFIG_TEST_EXTRA_STACK_SIZE=4096
-CONFIG_MAIN_STACK_SIZE=2048
-CONFIG_ZTEST_STACK_SIZE=2048
diff --git a/tests/subsys/logging/log_stack/src/main.c b/tests/subsys/logging/log_stack/src/main.c
deleted file mode 100644
index 385dd865b2b..00000000000
--- a/tests/subsys/logging/log_stack/src/main.c
+++ /dev/null
@@ -1,306 +0,0 @@
-/*
- * Copyright (c) 2022 Nordic Semiconductor
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#include <zephyr/ztest.h>
-#include <zephyr/logging/log.h>
-
-/* The idea of this test is to estimate stack usage of logging messages. Each
- * test checks stack usage before and after logging a message. Increase of stack
- * usage is interpreted as stack used by the logging. Test has been used to
- * characterize some common architectures and it will fail if significantly more
- * stack is used.
- *
- * This will help to detect when changes in logging, toolchain or modules used
- * by logging increase stack usage. Failure of the test should lead to investigation
- * to determine if stack usage change is justified. If it is justified, thresholds
- * may be updated.
- */
-
-LOG_MODULE_REGISTER(test);
-
-static size_t simple_usage;
-static size_t hexdump_usage;
-static size_t more_args_usage;
-
-/* Stack increase margin. */
-#ifdef CONFIG_PICOLIBC
-#define STACK_USAGE_MARGIN 128
-#else
-#define STACK_USAGE_MARGIN 16
-#endif
-
-static void after(void *data)
-{
-	PRINT("#elif %sdefined(CONFIG_LOG_MODE_IMMEDIATE) && %sdefined(CONFIG_NO_OPTIMIZATIONS)\n",
-		IS_ENABLED(CONFIG_LOG_MODE_IMMEDIATE) ? "" : "!",
-		IS_ENABLED(CONFIG_NO_OPTIMIZATIONS) ? "" : "!");
-	PRINT("#define SIMPLE_USAGE %zu\n", simple_usage);
-	PRINT("#define HEXDUMP_USAGE %zu\n", hexdump_usage);
-	PRINT("#define MORE_ARGS_USAGE %zu\n", more_args_usage);
-}
-
-ZTEST_SUITE(test_log_stack, NULL, NULL, NULL, NULL, after);
-
-#define TEST_LOG_STACK(usage, log_msg) do { \
-	size_t unused, unused2; \
-	int err; \
-	\
-	k_msleep(100); \
-	err = k_thread_stack_space_get(k_current_get(), &unused); \
-	zassert_equal(err, 0); \
-	__DEBRACKET log_msg; \
-	\
-	k_msleep(100); \
-	\
-	err = k_thread_stack_space_get(k_current_get(), &unused2); \
-	zassert_equal(err, 0); \
-	\
-	usage = unused - unused2; \
-	PRINT("Stack increase due to log usage: %zu\n", usage); \
-} while (0)
-
-#if defined(CONFIG_CPU_CORTEX_M0)
-
-#if !defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 120
-#define HEXDUMP_USAGE 120
-#define MORE_ARGS_USAGE 136
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 436
-#define HEXDUMP_USAGE 436
-#define MORE_ARGS_USAGE 452
-#elif !defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 168
-#define HEXDUMP_USAGE 168
-#define MORE_ARGS_USAGE 171
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 911
-#define HEXDUMP_USAGE 911
-#define MORE_ARGS_USAGE 927
-#endif
-
-#elif defined(CONFIG_CPU_CORTEX_M3)
-
-#if !defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 160
-#define HEXDUMP_USAGE 160
-#define MORE_ARGS_USAGE 176
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 388
-#define HEXDUMP_USAGE 388
-#define MORE_ARGS_USAGE 404
-#elif !defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 144
-#define HEXDUMP_USAGE 88
-#define MORE_ARGS_USAGE 144
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 640
-#define HEXDUMP_USAGE 640
-#define MORE_ARGS_USAGE 656
-#endif
-
-#elif defined(CONFIG_X86) && !defined(CONFIG_X86_64)
-
-#if !defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 72
-#define HEXDUMP_USAGE 68
-#define MORE_ARGS_USAGE 88
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 448
-#define HEXDUMP_USAGE 444
-#define MORE_ARGS_USAGE 484
-#elif !defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 288
-#define HEXDUMP_USAGE 272
-#define MORE_ARGS_USAGE 304
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 988
-#define HEXDUMP_USAGE 972
-#define MORE_ARGS_USAGE 1020
-#endif
-
-#elif defined(CONFIG_X86_64)
-
-#if !defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 168
-#define HEXDUMP_USAGE 136
-#define MORE_ARGS_USAGE 200
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 1120
-#define HEXDUMP_USAGE 1104
-#define MORE_ARGS_USAGE 1184
-#elif !defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 576
-#define HEXDUMP_USAGE 576
-#define MORE_ARGS_USAGE 608
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 1680
-#define HEXDUMP_USAGE 1680
-#define MORE_ARGS_USAGE 1744
-#endif
-
-#elif defined(CONFIG_RISCV) && !defined(CONFIG_64BIT) && !defined(CONFIG_SMP)
-
-#if !defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 136
-#define HEXDUMP_USAGE 136
-#define MORE_ARGS_USAGE 152
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 504
-#define HEXDUMP_USAGE 504
-#define MORE_ARGS_USAGE 520
-#elif !defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 240
-#define HEXDUMP_USAGE 240
-#define MORE_ARGS_USAGE 240
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 992
-#define HEXDUMP_USAGE 992
-#define MORE_ARGS_USAGE 1008
-#endif
-
-#elif defined(CONFIG_RISCV) && !defined(CONFIG_64BIT) && defined(CONFIG_SMP)
-
-#if !defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 96
-#define HEXDUMP_USAGE 96
-#define MORE_ARGS_USAGE 112
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 456
-#define HEXDUMP_USAGE 456
-#define MORE_ARGS_USAGE 472
-#elif !defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 304
-#define HEXDUMP_USAGE 240
-#define MORE_ARGS_USAGE 240
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 1008
-#define HEXDUMP_USAGE 1008
-#define MORE_ARGS_USAGE 1024
-#endif
-
-#elif defined(CONFIG_RISCV) && defined(CONFIG_64BIT) && defined(CONFIG_SMP)
-
-#if !defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 200
-#define HEXDUMP_USAGE 168
-#define MORE_ARGS_USAGE 232
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 736
-#define HEXDUMP_USAGE 768
-#define MORE_ARGS_USAGE 768
-#elif !defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 320
-#define HEXDUMP_USAGE 320
-#define MORE_ARGS_USAGE 320
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 1248
-#define HEXDUMP_USAGE 1248
-#define MORE_ARGS_USAGE 1280
-#endif
-
-#elif defined(CONFIG_RISCV) && defined(CONFIG_64BIT)
-
-#if !defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 240
-#define HEXDUMP_USAGE 240
-#define MORE_ARGS_USAGE 272
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 704
-#define HEXDUMP_USAGE 704
-#define MORE_ARGS_USAGE 736
-#elif !defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 320
-#define HEXDUMP_USAGE 320
-#define MORE_ARGS_USAGE 320
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 1128
-#define HEXDUMP_USAGE 1128
-#define MORE_ARGS_USAGE 1160
-#endif
-
-#elif defined(CONFIG_SPARC)
-
-#if !defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 0
-#define HEXDUMP_USAGE 28
-#define MORE_ARGS_USAGE 0
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 849
-#define HEXDUMP_USAGE 849
-#define MORE_ARGS_USAGE 865
-#elif !defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 416
-#define HEXDUMP_USAGE 232
-#define MORE_ARGS_USAGE 416
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 1544
-#define HEXDUMP_USAGE 1544
-#define MORE_ARGS_USAGE 1560
-#endif
-
-#elif defined(CONFIG_XTENSA)
-
-#if !defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 72
-#define HEXDUMP_USAGE 168
-#define MORE_ARGS_USAGE 88
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && !defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 584
-#define HEXDUMP_USAGE 584
-#define MORE_ARGS_USAGE 600
-#elif !defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 336
-#define HEXDUMP_USAGE 336
-#define MORE_ARGS_USAGE 336
-#elif defined(CONFIG_LOG_MODE_IMMEDIATE) && defined(CONFIG_NO_OPTIMIZATIONS)
-#define SIMPLE_USAGE 1040
-#define HEXDUMP_USAGE 1040
-#define MORE_ARGS_USAGE 1056
-#endif
-
-#else
-/* For other platforms which were not characterized use something big. */
-#define SIMPLE_USAGE 2000
-#define HEXDUMP_USAGE 2000
-#define MORE_ARGS_USAGE 2000
-#endif
-
-#define SIMPLE_USAGE_LIMIT (SIMPLE_USAGE + STACK_USAGE_MARGIN)
-#define HEXDUMP_USAGE_LIMIT (HEXDUMP_USAGE + STACK_USAGE_MARGIN)
-#define MORE_ARGS_USAGE_LIMIT (MORE_ARGS_USAGE + STACK_USAGE_MARGIN)
-
-ZTEST(test_log_stack, test_log_simple)
-{
-	uint32_t test_u = 1;
-	int test_i = 1;
-
-	TEST_LOG_STACK(simple_usage, (LOG_INF("test %u %d", test_u, test_i)));
-
-	zassert_true(simple_usage <= SIMPLE_USAGE_LIMIT, "Usage:%zu, expected:%zu",
-			simple_usage, SIMPLE_USAGE_LIMIT);
-}
-
-ZTEST(test_log_stack, test_log_hexdump)
-{
-	uint8_t data[] = {1, 2, 3, 4};
-
-	TEST_LOG_STACK(hexdump_usage, (LOG_HEXDUMP_INF(data, sizeof(data), "description")));
-
-	zassert_true(hexdump_usage <= HEXDUMP_USAGE_LIMIT, "Usage:%zu, expected:%zu",
-			hexdump_usage, HEXDUMP_USAGE_LIMIT);
-}
-
-ZTEST(test_log_stack, test_log_more_args)
-{
-	TEST_LOG_STACK(more_args_usage, (LOG_INF("test %d %d %d %d %d %d",
-				k_uptime_get_32(), k_uptime_get_32(),
-				k_uptime_get_32(), k_uptime_get_32(),
-				k_uptime_get_32(), k_uptime_get_32())));
-
-	zassert_true(more_args_usage <= MORE_ARGS_USAGE_LIMIT, "Usage:%zu, expected:%zu",
-			more_args_usage, MORE_ARGS_USAGE_LIMIT);
-}
diff --git a/tests/subsys/logging/log_stack/testcase.yaml b/tests/subsys/logging/log_stack/testcase.yaml
deleted file mode 100644
index 92534b65ab0..00000000000
--- a/tests/subsys/logging/log_stack/testcase.yaml
+++ /dev/null
@@ -1,52 +0,0 @@
-common:
-  platform_type:
-    - qemu
-  tags:
-    - log_api
-    - logging
-  skip: true
-  integration_platforms:
-    - qemu_x86
-tests:
-  logging.stack.deferred:
-    extra_configs:
-      - CONFIG_LOG_MODE_DEFERRED=y
-  logging.stack.deferred_no_opt:
-    filter: not CONFIG_MIPS
-    extra_configs:
-      - CONFIG_LOG_MODE_DEFERRED=y
-      - CONFIG_NO_OPTIMIZATIONS=y
-      - CONFIG_ZTEST_WARN_NO_OPTIMIZATIONS=n
-      - CONFIG_IDLE_STACK_SIZE=2048
-  logging.stack.immediate:
-    extra_configs:
-      - CONFIG_LOG_MODE_IMMEDIATE=y
-  logging.stack.immediate_no_opt:
-    filter: not CONFIG_MIPS
-    extra_configs:
-      - CONFIG_LOG_MODE_IMMEDIATE=y
-      - CONFIG_NO_OPTIMIZATIONS=y
-      - CONFIG_ZTEST_WARN_NO_OPTIMIZATIONS=n
-      - CONFIG_IDLE_STACK_SIZE=2048
-  logging.stack.deferred_cpp:
-    extra_configs:
-      - CONFIG_LOG_MODE_DEFERRED=y
-      - CONFIG_CPP=y
-  logging.stack.deferred_cpp_no_opt:
-    filter: not CONFIG_MIPS
-    extra_configs:
-      - CONFIG_LOG_MODE_DEFERRED=y
-      - CONFIG_NO_OPTIMIZATIONS=y
-      - CONFIG_ZTEST_WARN_NO_OPTIMIZATIONS=n
-      - CONFIG_CPP=y
-  logging.stack.immediate_cpp:
-    extra_configs:
-      - CONFIG_LOG_MODE_IMMEDIATE=y
-      - CONFIG_CPP=y
-  logging.stack.immediate_cpp_no_opt:
-    filter: not CONFIG_MIPS
-    extra_configs:
-      - CONFIG_LOG_MODE_IMMEDIATE=y
-      - CONFIG_NO_OPTIMIZATIONS=y
-      - CONFIG_ZTEST_WARN_NO_OPTIMIZATIONS=n
-      - CONFIG_CPP=y
diff --git a/tests/subsys/lorawan/frag_decoder/testcase.yaml b/tests/subsys/lorawan/frag_decoder/testcase.yaml
index 7182fd3cfe6..d5ea2f8d714 100644
--- a/tests/subsys/lorawan/frag_decoder/testcase.yaml
+++ b/tests/subsys/lorawan/frag_decoder/testcase.yaml
@@ -7,6 +7,7 @@ tests:
       - native_sim
     extra_configs:
       - CONFIG_LORAWAN_FRAG_TRANSPORT_DECODER_SEMTECH=y
+      - CONFIG_NATIVE_EXTRA_CMDLINE_ARGS="seed=1"
   lorawan.frag_decoder.lowmem.high_redundancy:
     platform_allow:
       - native_sim
@@ -19,3 +20,4 @@ tests:
     extra_configs:
       - CONFIG_LORAWAN_FRAG_TRANSPORT_DECODER_LOWMEM=y
       - CONFIG_LORAWAN_FRAG_TRANSPORT_MAX_REDUNDANCY=10
+      - CONFIG_NATIVE_EXTRA_CMDLINE_ARGS="seed=1"
diff --git a/tests/subsys/mgmt/mcumgr/enum_mgmt/testcase.yaml b/tests/subsys/mgmt/mcumgr/enum_mgmt/testcase.yaml
index ebfd3014e81..7173df38f86 100644
--- a/tests/subsys/mgmt/mcumgr/enum_mgmt/testcase.yaml
+++ b/tests/subsys/mgmt/mcumgr/enum_mgmt/testcase.yaml
@@ -13,17 +13,17 @@ common:
     - mcumgr
     - enum_mgmt
 tests:
-  enum.mgmt:
+  mgmt.mcumgr.enum.mgmt:
     build_only: false
-  enum.mgmt.shell:
+  mgmt.mcumgr.enum.mgmt.shell:
     extra_configs:
       - CONFIG_SHELL=y
       - CONFIG_SHELL_BACKEND_DUMMY=y
       - CONFIG_MCUMGR_GRP_SHELL=y
-  enum.mgmt.os:
+  mgmt.mcumgr.enum.mgmt.os:
     extra_configs:
       - CONFIG_MCUMGR_GRP_OS=y
-  enum.mgmt.shell.os:
+  mgmt.mcumgr.enum.mgmt.shell.os:
     extra_configs:
       - CONFIG_SHELL=y
       - CONFIG_SHELL_BACKEND_DUMMY=y
diff --git a/tests/subsys/mgmt/mcumgr/img_mgmt_slot_info/testcase.yaml b/tests/subsys/mgmt/mcumgr/img_mgmt_slot_info/testcase.yaml
index dc795e49fb9..55f52209f7d 100644
--- a/tests/subsys/mgmt/mcumgr/img_mgmt_slot_info/testcase.yaml
+++ b/tests/subsys/mgmt/mcumgr/img_mgmt_slot_info/testcase.yaml
@@ -13,10 +13,10 @@ common:
     - img_mgmt
   build_only: false
 tests:
-  img.mgmt.slot.info: {}
-  img.mgmt.slot.info.too.large:
+  mgmt.mcumgr.img.mgmt.slot.info: {}
+  mgmt.mcumgr.img.mgmt.slot.info.too.large:
     extra_args:
       - FILE_SUFFIX=too_large
-  img.mgmt.slot.info.dual.slot:
+  mgmt.mcumgr.slot.info.dual.slot:
     extra_args:
       - FILE_SUFFIX=dual_slot
diff --git a/tests/subsys/mgmt/mcumgr/settings_mgmt/src/main.c b/tests/subsys/mgmt/mcumgr/settings_mgmt/src/main.c
index e5da57b4009..21b4b90e77b 100644
--- a/tests/subsys/mgmt/mcumgr/settings_mgmt/src/main.c
+++ b/tests/subsys/mgmt/mcumgr/settings_mgmt/src/main.c
@@ -66,6 +66,12 @@ static const uint8_t test_response_error_data[8] = {
 	0xbf, 0x62, 0x72, 0x63, 0x19, 0x01, 0x00, 0xff
 };
 
+/*
+ * TODO: The contents of these structs are not used, which is why clang complains.
+ * The test should be updated to use these values. See discussion in
+ * https://github.com/zephyrproject-rtos/zephyr/pull/87592.
+ */
+TOOLCHAIN_DISABLE_CLANG_WARNING(TOOLCHAIN_WARNING_UNNEEDED_INTERNAL_DECLARATION)
 static const uint8_t test_response_read_data_start[5] = {
 	0xbf, 0x63, 0x76, 0x61, 0x6c
 };
@@ -73,6 +79,7 @@ static const uint8_t test_response_read_data_start[5] = {
 static const uint8_t test_response_read_data_end[1] = {
 	0xff
 };
+TOOLCHAIN_ENABLE_CLANG_WARNING(TOOLCHAIN_WARNING_UNNEEDED_INTERNAL_DECLARATION)
 
 static void cleanup_test(void *p)
 {
diff --git a/tests/subsys/modem/modem_ppp/prj.conf b/tests/subsys/modem/modem_ppp/prj.conf
index ac0366608dd..5eef452240b 100644
--- a/tests/subsys/modem/modem_ppp/prj.conf
+++ b/tests/subsys/modem/modem_ppp/prj.conf
@@ -7,7 +7,7 @@ CONFIG_NETWORKING=y
 CONFIG_MODEM_MODULES=y
 CONFIG_MODEM_PPP=y
 CONFIG_NET_L2_PPP=y
-CONFIG_ETH_NATIVE_POSIX=n
+CONFIG_ETH_NATIVE_TAP=n
 
 CONFIG_ZTEST=y
 
diff --git a/tests/subsys/modem/modem_ppp/src/main.c b/tests/subsys/modem/modem_ppp/src/main.c
index 5816a65ffa0..0948eb2c4b5 100644
--- a/tests/subsys/modem/modem_ppp/src/main.c
+++ b/tests/subsys/modem/modem_ppp/src/main.c
@@ -12,6 +12,7 @@
 #include <zephyr/net/net_if.h>
 #include <zephyr/net/net_pkt.h>
 #include <zephyr/net/net_l2.h>
+#include <zephyr/net/ethernet.h>
 #include <zephyr/net/ppp.h>
 #include <zephyr/sys/crc.h>
 #include <string.h>
@@ -77,8 +78,6 @@ static uint8_t wrapped_buffer[4096];
 /*************************************************************************************************/
 /*                                  Mock network interface                                       */
 /*************************************************************************************************/
-static uint8_t test_net_link_addr[] = {0x00, 0x00, 0x5E, 0x00, 0x53, 0x01};
-
 static enum net_verdict test_net_l2_recv(struct net_if *iface, struct net_pkt *pkt)
 {
 	/* Validate buffer not overflowing */
@@ -99,8 +98,8 @@ static struct net_l2 test_net_l2 = {
 /* This emulates the network interface device which will receive unwrapped network packets */
 static struct net_if_dev test_net_if_dev = {
 	.l2 = &test_net_l2,
-	.link_addr.addr = test_net_link_addr,
-	.link_addr.len = sizeof(test_net_link_addr),
+	.link_addr.addr = {0x00, 0x00, 0x5E, 0x00, 0x53, 0x01},
+	.link_addr.len = NET_ETH_ADDR_LEN,
 	.link_addr.type = NET_LINK_DUMMY,
 	.mtu = 1500,
 	.oper_state = NET_IF_OPER_UP,
diff --git a/tests/subsys/nrfs/testcase.yaml b/tests/subsys/nrfs/testcase.yaml
deleted file mode 100644
index 527ff477cd0..00000000000
--- a/tests/subsys/nrfs/testcase.yaml
+++ /dev/null
@@ -1,14 +0,0 @@
-common:
-  platform_allow:
-    - nrf54h20dk/nrf54h20/cpuapp
-    - nrf54h20dk/nrf54h20/cpurad
-  integration_platforms:
-    - nrf54h20dk/nrf54h20/cpuapp
-    - nrf54h20dk/nrf54h20/cpurad
-  tags:
-    - nrfs
-  harness: ztest
-  sysbuild: true
-
-tests:
-  subsys.nrfs.stress_test: {}
diff --git a/tests/subsys/openthread/testcase.yaml b/tests/subsys/openthread/testcase.yaml
index 163024d86b7..4b791d70c49 100644
--- a/tests/subsys/openthread/testcase.yaml
+++ b/tests/subsys/openthread/testcase.yaml
@@ -2,9 +2,6 @@ common:
   platform_allow:
     - native_sim
     - native_sim/native/64
-  platform_exclude:
-    - native_posix/native/64
-    - native_posix
   integration_platforms:
     - native_sim
   tags:
diff --git a/tests/subsys/pm/device_driver_init/src/main.c b/tests/subsys/pm/device_driver_init/src/main.c
index 014e02a5940..d38d6ed1429 100644
--- a/tests/subsys/pm/device_driver_init/src/main.c
+++ b/tests/subsys/pm/device_driver_init/src/main.c
@@ -70,4 +70,59 @@ ZTEST(device_driver_init, test_device_driver_init)
 #endif
 }
 
+struct pm_transition_test_dev_data {
+	enum pm_device_state state_turn_on;
+	enum pm_device_state state_resume;
+	bool state_other;
+};
+
+static int pm_transition_test_dev_pm_action(const struct device *dev, enum pm_device_action action)
+{
+	struct pm_transition_test_dev_data *data = dev->data;
+
+	/* Preserve the observed internal state when actions ran */
+	switch (action) {
+	case PM_DEVICE_ACTION_TURN_ON:
+		pm_device_state_get(dev, &data->state_turn_on);
+		break;
+	case PM_DEVICE_ACTION_RESUME:
+		pm_device_state_get(dev, &data->state_resume);
+		break;
+	default:
+		data->state_other = true;
+	}
+	return 0;
+}
+
+static int pm_transition_test_dev_init(const struct device *dev)
+{
+	struct pm_transition_test_dev_data *data = dev->data;
+
+	data->state_turn_on = UINT8_MAX;
+	data->state_resume = UINT8_MAX;
+	data->state_other = false;
+
+	return pm_device_driver_init(dev, pm_transition_test_dev_pm_action);
+}
+
+static struct pm_transition_test_dev_data dev_data;
+PM_DEVICE_DEFINE(pm_transition_test_dev_pm, pm_transition_test_dev_pm_action);
+DEVICE_DEFINE(pm_transition_test_dev, "test_dev", pm_transition_test_dev_init,
+	PM_DEVICE_GET(pm_transition_test_dev_pm), &dev_data, NULL,
+	POST_KERNEL, 0, NULL);
+
+ZTEST(device_driver_init, test_device_driver_init_pm_state)
+{
+#ifdef CONFIG_PM_DEVICE
+	zassert_equal(PM_DEVICE_STATE_OFF, dev_data.state_turn_on);
+	zassert_equal(PM_DEVICE_STATE_SUSPENDED, dev_data.state_resume);
+	zassert_false(dev_data.state_other);
+#else
+	/* pm_device_state_get always returns PM_DEVICE_STATE_ACTIVE */
+	zassert_equal(PM_DEVICE_STATE_ACTIVE, dev_data.state_turn_on);
+	zassert_equal(PM_DEVICE_STATE_ACTIVE, dev_data.state_resume);
+	zassert_false(dev_data.state_other);
+#endif /* CONFIG_PM */
+}
+
 ZTEST_SUITE(device_driver_init, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/subsys/pm/policy_api/app.overlay b/tests/subsys/pm/policy_api/app.overlay
index 5f1324b5285..54b02e0b28e 100644
--- a/tests/subsys/pm/policy_api/app.overlay
+++ b/tests/subsys/pm/policy_api/app.overlay
@@ -6,7 +6,7 @@
 / {
 	cpus {
 		cpu1: cpu@1 {
-			compatible = "zephyr,native-posix-cpu";
+			compatible = "zephyr,native-sim-cpu";
 			reg = <1>;
 			cpu-power-states = <&state2>;
 		};
diff --git a/tests/subsys/pm/power_domain_soc_state_change/CMakeLists.txt b/tests/subsys/pm/power_domain_soc_state_change/CMakeLists.txt
new file mode 100644
index 00000000000..538cf3f5612
--- /dev/null
+++ b/tests/subsys/pm/power_domain_soc_state_change/CMakeLists.txt
@@ -0,0 +1,8 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(power_domain_soc_state_change)
+
+target_sources(app PRIVATE src/main.c)
diff --git a/tests/subsys/pm/power_domain_soc_state_change/Kconfig b/tests/subsys/pm/power_domain_soc_state_change/Kconfig
new file mode 100644
index 00000000000..6a021dcd944
--- /dev/null
+++ b/tests/subsys/pm/power_domain_soc_state_change/Kconfig
@@ -0,0 +1,11 @@
+# Copyright (c) 2023 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+menu "Zephyr"
+source "Kconfig.zephyr"
+endmenu
+
+config TEST_PROVIDE_PM_HOOKS
+	bool "Provide PM hooks for test purposes"
+	default y
+	select HAS_PM
diff --git a/tests/subsys/pm/power_domain_soc_state_change/app.overlay b/tests/subsys/pm/power_domain_soc_state_change/app.overlay
new file mode 100644
index 00000000000..330d60daf9d
--- /dev/null
+++ b/tests/subsys/pm/power_domain_soc_state_change/app.overlay
@@ -0,0 +1,46 @@
+/*
+ * Copyright 2025 NXP
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	power-states {
+		state0: state0 {
+			compatible = "zephyr,power-state";
+			power-state-name = "runtime-idle";
+			min-residency-us = <10000>;
+			exit-latency-us = <100>;
+		};
+
+		state1: state1 {
+			compatible = "zephyr,power-state";
+			power-state-name = "suspend-to-idle";
+			min-residency-us = <50000>;
+			exit-latency-us = <500>;
+		};
+
+		state2: state2 {
+			compatible = "zephyr,power-state";
+			power-state-name = "standby";
+			min-residency-us = <100000>;
+			exit-latency-us = <1000>;
+		};
+	};
+
+	test_soc_state_domain: test_soc_state_domain {
+		compatible = "power-domain-soc-state-change";
+		status = "okay";
+		onoff-power-states = <&state1 &state2>;
+		#power-domain-cells = <0>;
+	};
+
+	test_dev_soc_state_change: test_dev_soc_state_change {
+		compatible = "test-device-pm";
+		status = "okay";
+		power-domains = <&test_soc_state_domain>;
+	};
+};
+
+&cpu0 {
+	cpu-power-states = <&state0 &state1 &state2>;
+};
diff --git a/tests/subsys/pm/power_domain_soc_state_change/dts/bindings/test-device-pm.yaml b/tests/subsys/pm/power_domain_soc_state_change/dts/bindings/test-device-pm.yaml
new file mode 100644
index 00000000000..2d6c79353e0
--- /dev/null
+++ b/tests/subsys/pm/power_domain_soc_state_change/dts/bindings/test-device-pm.yaml
@@ -0,0 +1,10 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+include: [base.yaml, pm.yaml]
+
+description: |
+    This binding provides resources required to build and run the
+    tests/subsys/pm/power_domain_soc_state_change test in Zephyr.
+
+compatible: "test-device-pm"
diff --git a/tests/subsys/pm/power_domain_soc_state_change/prj.conf b/tests/subsys/pm/power_domain_soc_state_change/prj.conf
new file mode 100644
index 00000000000..b523d1a9fdf
--- /dev/null
+++ b/tests/subsys/pm/power_domain_soc_state_change/prj.conf
@@ -0,0 +1,7 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ZTEST=y
+CONFIG_PM=y
+CONFIG_PM_DEVICE=y
+CONFIG_POWER_DOMAIN=y
diff --git a/tests/subsys/pm/power_domain_soc_state_change/src/main.c b/tests/subsys/pm/power_domain_soc_state_change/src/main.c
new file mode 100644
index 00000000000..0017b2b2a41
--- /dev/null
+++ b/tests/subsys/pm/power_domain_soc_state_change/src/main.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/ztest.h>
+#include <zephyr/pm/device.h>
+
+#define TEST_DEV DT_NODELABEL(test_dev_soc_state_change)
+
+static int testing_domain_on_notitication;
+static int testing_domain_off_notitication;
+
+void pm_state_set(enum pm_state state, uint8_t substate_id)
+{
+	ARG_UNUSED(substate_id);
+
+	switch (testing_domain_off_notitication) {
+	case 1:
+		zassert_equal(state, PM_STATE_STANDBY, "Wrong system state %d", state);
+		break;
+	case 2:
+		zassert_true(
+			((state == PM_STATE_SUSPEND_TO_IDLE) || (state == PM_STATE_RUNTIME_IDLE)),
+			"Wrong system state %d", state);
+		break;
+	default:
+		break;
+	}
+
+	k_cpu_idle();
+}
+
+void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
+{
+	ARG_UNUSED(state);
+	ARG_UNUSED(substate_id);
+
+	irq_unlock(0);
+}
+
+static int dev_pm_action(const struct device *dev, enum pm_device_action pm_action)
+{
+	ARG_UNUSED(dev);
+
+	if (pm_action == PM_DEVICE_ACTION_TURN_ON) {
+		testing_domain_on_notitication++;
+	}
+
+	if (pm_action == PM_DEVICE_ACTION_TURN_OFF) {
+		testing_domain_off_notitication++;
+	}
+
+	return 0;
+}
+
+PM_DEVICE_DT_DEFINE(TEST_DEV, dev_pm_action);
+DEVICE_DT_DEFINE(TEST_DEV, NULL, PM_DEVICE_DT_GET(TEST_DEV), NULL, NULL, POST_KERNEL, 20, NULL);
+
+ZTEST(power_domain_soc_state_change_1cpu, test_power_domain_soc_state_change)
+{
+	const struct pm_state_info *cpu_states, *state;
+
+	pm_state_cpu_get_all(_current_cpu->id, &cpu_states);
+
+	state = &cpu_states[2];
+	/* Sleep to transition to STATE: STANDBY */
+	k_usleep(state->min_residency_us + state->exit_latency_us);
+
+	zassert_equal(testing_domain_on_notitication, 1);
+	zassert_equal(testing_domain_off_notitication, 1);
+
+	state = &cpu_states[1];
+	/* Sleep to transition to STATE: SUSPEND-TO-IDLE */
+	k_usleep(state->min_residency_us + state->exit_latency_us);
+
+	zassert_equal(testing_domain_on_notitication, 2);
+	zassert_equal(testing_domain_off_notitication, 2);
+
+	state = &cpu_states[0];
+	/* Sleep to transition to STATE: RUNTIME-IDLE */
+	k_usleep(state->min_residency_us + state->exit_latency_us);
+
+	/* The domain notification flags should remain the same as RUNTIME-IDLE
+	 * is not listed as an ON/OFF power state in device-tree.
+	 */
+	zassert_equal(testing_domain_on_notitication, 2);
+	zassert_equal(testing_domain_off_notitication, 2);
+}
+
+ZTEST_SUITE(power_domain_soc_state_change_1cpu, NULL, NULL, ztest_simple_1cpu_before,
+	    ztest_simple_1cpu_after, NULL);
diff --git a/tests/subsys/pm/power_domain_soc_state_change/testcase.yaml b/tests/subsys/pm/power_domain_soc_state_change/testcase.yaml
new file mode 100644
index 00000000000..5923ecdae59
--- /dev/null
+++ b/tests/subsys/pm/power_domain_soc_state_change/testcase.yaml
@@ -0,0 +1,10 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+tests:
+  pm.power_domain_soc_state_change:
+    platform_allow:
+      - native_sim
+    integration_platforms:
+      - native_sim
+    tags: pm
diff --git a/tests/subsys/pm/power_mgmt_multicore/src/main.c b/tests/subsys/pm/power_mgmt_multicore/src/main.c
index 6915694a6d8..e87c38ea746 100644
--- a/tests/subsys/pm/power_mgmt_multicore/src/main.c
+++ b/tests/subsys/pm/power_mgmt_multicore/src/main.c
@@ -63,26 +63,40 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 
 const struct pm_state_info *pm_policy_next_state(uint8_t cpu, int ticks)
 {
-	static struct pm_state_info info = {};
+	static const struct pm_state_info states[] = {
+		{
+			.state = PM_STATE_ACTIVE
+		},
+		{
+			.state = PM_STATE_RUNTIME_IDLE
+		},
+		{
+			.state = PM_STATE_SUSPEND_TO_IDLE
+		},
+		{
+			.state = PM_STATE_STANDBY
+		},
+	};
+	static const struct pm_state_info *info;
 	int32_t msecs = k_ticks_to_ms_floor64(ticks);
 
 	if (msecs < ACTIVE_MSEC) {
-		info.state = PM_STATE_ACTIVE;
+		info = NULL;
 	} else if (msecs <= IDLE_MSEC) {
-		info.state = PM_STATE_RUNTIME_IDLE;
+		info = &states[1];
 	} else if (msecs <= SUSPEND_TO_IDLE_MSEC) {
-		info.state = PM_STATE_SUSPEND_TO_IDLE;
+		info = &states[2];
 	} else {
 		if (cpu == 0U) {
-			info.state = PM_STATE_SUSPEND_TO_IDLE;
+			info = &states[2];
 		} else {
-			info.state = PM_STATE_STANDBY;
+			info = &states[3];
 		}
 	}
 
-	state_testing[cpu] = info.state;
+	state_testing[cpu] = info ? info->state : PM_STATE_ACTIVE;
 
-	return &info;
+	return info;
 }
 
 /*
diff --git a/tests/subsys/pm/power_mgmt_soc/boards/frdm_rw612.overlay b/tests/subsys/pm/power_mgmt_soc/boards/frdm_rw612.overlay
new file mode 100644
index 00000000000..986cdef3ff7
--- /dev/null
+++ b/tests/subsys/pm/power_mgmt_soc/boards/frdm_rw612.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&standby {
+	status = "okay";
+};
diff --git a/tests/subsys/pm/power_mgmt_soc/boards/rd_rw612_bga.overlay b/tests/subsys/pm/power_mgmt_soc/boards/rd_rw612_bga.overlay
new file mode 100644
index 00000000000..986cdef3ff7
--- /dev/null
+++ b/tests/subsys/pm/power_mgmt_soc/boards/rd_rw612_bga.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&standby {
+	status = "okay";
+};
diff --git a/tests/subsys/pm/power_mgmt_soc/testcase.yaml b/tests/subsys/pm/power_mgmt_soc/testcase.yaml
index 63ef2f2e824..380cff7ab76 100644
--- a/tests/subsys/pm/power_mgmt_soc/testcase.yaml
+++ b/tests/subsys/pm/power_mgmt_soc/testcase.yaml
@@ -13,6 +13,7 @@ tests:
       - rd_rw612_bga
       - frdm_ke17z
       - frdm_ke17z512
+      - xg29_rb4412a
     tags: pm
     integration_platforms:
       - mec15xxevb_assy6853
diff --git a/tests/subsys/pm/power_residency_time/CMakeLists.txt b/tests/subsys/pm/power_residency_time/CMakeLists.txt
new file mode 100644
index 00000000000..5c6f384a109
--- /dev/null
+++ b/tests/subsys/pm/power_residency_time/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(power_residency_time)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/subsys/pm/power_residency_time/boards/stm32l562e_dk.overlay b/tests/subsys/pm/power_residency_time/boards/stm32l562e_dk.overlay
new file mode 100644
index 00000000000..ee4d80f9e90
--- /dev/null
+++ b/tests/subsys/pm/power_residency_time/boards/stm32l562e_dk.overlay
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&stop0{
+	compatible = "zephyr,power-state";
+	power-state-name = "suspend-to-idle";
+	substate-id = <1>;
+	min-residency-us = <500000>;
+};
+&stop1{
+	compatible = "zephyr,power-state";
+	power-state-name = "suspend-to-idle";
+	substate-id = <2>;
+	min-residency-us = <1000000>;
+};
+&stop2{
+	compatible = "zephyr,power-state";
+	power-state-name = "suspend-to-idle";
+	substate-id = <3>;
+	min-residency-us = <1500000>;
+};
diff --git a/tests/subsys/pm/power_residency_time/prj.conf b/tests/subsys/pm/power_residency_time/prj.conf
new file mode 100644
index 00000000000..76be0e2b554
--- /dev/null
+++ b/tests/subsys/pm/power_residency_time/prj.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_PM=y
diff --git a/tests/subsys/pm/power_residency_time/src/main.c b/tests/subsys/pm/power_residency_time/src/main.c
new file mode 100644
index 00000000000..043b06e4135
--- /dev/null
+++ b/tests/subsys/pm/power_residency_time/src/main.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/devicetree.h>
+
+#define DIFF_RESIDENCY_TIME_STATE_0 600
+#define DIFF_RESIDENCY_TIME_STATE_1 600
+#define DIFF_RESIDENCY_TIME_STATE_2 600
+
+int main(void)
+{
+
+	int stop0_min_residency_time = DT_PROP(DT_NODELABEL(stop0), min_residency_us);
+	int stop1_min_residency_time = DT_PROP(DT_NODELABEL(stop1), min_residency_us);
+	int stop2_min_residency_time = DT_PROP(DT_NODELABEL(stop2), min_residency_us);
+
+	while (1) {
+		printk("\nSleep time < min_residency_time of state 0\n");
+		k_usleep(stop0_min_residency_time - DIFF_RESIDENCY_TIME_STATE_0);
+		printk("\nSleep time = min_residency_time of state 0\n");
+		k_usleep(stop0_min_residency_time);
+		printk("\nSleep time < min_residency_time of state 1\n");
+		k_usleep(stop1_min_residency_time - DIFF_RESIDENCY_TIME_STATE_1);
+		printk("\nSleep time = min_residency_time of state 1\n");
+		k_usleep(stop1_min_residency_time);
+		printk("\nSleep time < min_residency_time of state 2\n");
+		k_usleep(stop2_min_residency_time - DIFF_RESIDENCY_TIME_STATE_2);
+		printk("\nSleep time = min_residency_time of state 2\n");
+		k_usleep(stop2_min_residency_time);
+		printk("\nWakeup.\n");
+
+		/**
+		 * Keeping alive loop
+		 */
+		while (1) {
+			arch_nop();
+		}
+	}
+	return 0;
+}
diff --git a/tests/subsys/pm/power_residency_time/testcase.yaml b/tests/subsys/pm/power_residency_time/testcase.yaml
new file mode 100644
index 00000000000..2f1e12af464
--- /dev/null
+++ b/tests/subsys/pm/power_residency_time/testcase.yaml
@@ -0,0 +1,50 @@
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+common:
+  harness: power
+  harness_config:
+    fixture: pm_probe
+    pytest_dut_scope: session
+    power_measurements:
+      elements_to_trim: 100
+      min_peak_distance: 40
+      min_peak_height: 0.008
+      peak_padding: 40
+      measurement_duration: 8
+      num_of_transitions: 6
+      expected_rms_values: [56.0, 4.0, 4.0, 1.4, 1.4, 0.26, 91]
+      tolerance_percentage: 10
+
+tests:
+  pm.power_residency_time:
+    platform_allow:
+      - stm32l562e_dk
+    tags:
+      - pm
+
+  pm.power_residency_time.pm_device:
+    platform_allow:
+      - stm32l562e_dk
+    tags:
+      - pm
+    extra_args:
+      - CONFIG_PM_DEVICE=y
+
+  pm.power_residency_time.pm_device_runtime:
+    platform_allow:
+      - stm32l562e_dk
+    tags:
+      - pm
+    extra_args:
+      - CONFIG_PM_DEVICE=y
+      - CONFIG_PM_DEVICE_RUNTIME=y
+
+  pm.power_residency_time.pm_device_system_managed:
+    platform_allow:
+      - stm32l562e_dk
+    tags:
+      - pm
+    extra_args:
+      - CONFIG_PM_DEVICE=y
+      - CONFIG_PM_DEVICE_SYSTEM_MANAGED=y
diff --git a/tests/subsys/pm/power_states/CMakeLists.txt b/tests/subsys/pm/power_states/CMakeLists.txt
new file mode 100644
index 00000000000..83e018923b6
--- /dev/null
+++ b/tests/subsys/pm/power_states/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(power_states)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/subsys/pm/power_states/boards/stm32l562e_dk.overlay b/tests/subsys/pm/power_states/boards/stm32l562e_dk.overlay
new file mode 100644
index 00000000000..d128ff520ca
--- /dev/null
+++ b/tests/subsys/pm/power_states/boards/stm32l562e_dk.overlay
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/ {
+	zephyr,user {
+		k_idle_state_min_residency_time = <400000>;
+	};
+};
+
+&stop0{
+	compatible = "zephyr,power-state";
+	power-state-name = "suspend-to-idle";
+	substate-id = <1>;
+	min-residency-us = <500000>;
+};
+&stop1{
+	compatible = "zephyr,power-state";
+	power-state-name = "suspend-to-idle";
+	substate-id = <2>;
+	min-residency-us = <1000000>;
+};
+&stop2{
+	compatible = "zephyr,power-state";
+	power-state-name = "suspend-to-idle";
+	substate-id = <3>;
+	min-residency-us = <1500000>;
+};
diff --git a/tests/subsys/pm/power_states/prj.conf b/tests/subsys/pm/power_states/prj.conf
new file mode 100644
index 00000000000..76be0e2b554
--- /dev/null
+++ b/tests/subsys/pm/power_states/prj.conf
@@ -0,0 +1,4 @@
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_PM=y
diff --git a/tests/subsys/pm/power_states/src/main.c b/tests/subsys/pm/power_states/src/main.c
new file mode 100644
index 00000000000..fb043b36d78
--- /dev/null
+++ b/tests/subsys/pm/power_states/src/main.c
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/kernel.h>
+
+int main(void)
+{
+	int k_idle_min_residency_time =
+		DT_PROP(DT_PATH(zephyr_user), k_idle_state_min_residency_time);
+	int stop0_min_residency_time = DT_PROP(DT_NODELABEL(stop0), min_residency_us);
+	int stop1_min_residency_time = DT_PROP(DT_NODELABEL(stop1), min_residency_us);
+	int stop2_min_residency_time = DT_PROP(DT_NODELABEL(stop2), min_residency_us);
+
+	while (1) {
+		printk("\nGoing to k_cpu_idle.\n");
+		k_usleep(k_idle_min_residency_time);
+		printk("\nWake Up.\n");
+		printk("\nGoing to state 0.\n");
+		k_usleep(stop0_min_residency_time);
+		printk("\nWake Up.\n");
+		printk("\nGoing to state 1.\n");
+		k_usleep(stop1_min_residency_time);
+		printk("\nWake Up.\n");
+		printk("\nGoing to state 2.\n");
+		k_usleep(stop2_min_residency_time);
+		printk("\nWake Up.\n");
+
+		/* Anti-sleeping loop */
+		while (1) {
+			arch_nop();
+		}
+	}
+	return 0;
+}
diff --git a/tests/subsys/pm/power_states/testcase.yaml b/tests/subsys/pm/power_states/testcase.yaml
new file mode 100644
index 00000000000..34415520059
--- /dev/null
+++ b/tests/subsys/pm/power_states/testcase.yaml
@@ -0,0 +1,50 @@
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+common:
+  harness: power
+  harness_config:
+    fixture: pm_probe
+    pytest_dut_scope: session
+    power_measurements:
+      elements_to_trim: 100
+      min_peak_distance: 40
+      min_peak_height: 0.008
+      peak_padding: 40
+      measurement_duration: 6
+      num_of_transitions: 4
+      expected_rms_values: [56.0, 4.0, 1.4, 0.26, 140]
+      tolerance_percentage: 10
+
+tests:
+  pm.power_states:
+    platform_allow:
+      - stm32l562e_dk
+    tags:
+      - pm
+
+  pm.power_states.pm_device:
+    platform_allow:
+      - stm32l562e_dk
+    tags:
+      - pm
+    extra_args:
+      - CONFIG_PM_DEVICE=y
+
+  pm.power_states.pm_device_runtime:
+    platform_allow:
+      - stm32l562e_dk
+    tags:
+      - pm
+    extra_args:
+      - CONFIG_PM_DEVICE=y
+      - CONFIG_PM_DEVICE_RUNTIME=y
+
+  pm.power_states.pm_device_system_managed:
+    platform_allow:
+      - stm32l562e_dk
+    tags:
+      - pm
+    extra_args:
+      - CONFIG_PM_DEVICE=y
+      - CONFIG_PM_DEVICE_SYSTEM_MANAGED=y
diff --git a/tests/subsys/pm/power_wakeup_timer/CMakeLists.txt b/tests/subsys/pm/power_wakeup_timer/CMakeLists.txt
new file mode 100644
index 00000000000..1af597083c5
--- /dev/null
+++ b/tests/subsys/pm/power_wakeup_timer/CMakeLists.txt
@@ -0,0 +1,9 @@
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(power_wakeup_timer)
+
+FILE(GLOB app_sources src/*.c)
+target_sources(app PRIVATE ${app_sources})
diff --git a/tests/subsys/pm/power_wakeup_timer/boards/stm32l562e_dk.overlay b/tests/subsys/pm/power_wakeup_timer/boards/stm32l562e_dk.overlay
new file mode 100644
index 00000000000..5a7550b22e0
--- /dev/null
+++ b/tests/subsys/pm/power_wakeup_timer/boards/stm32l562e_dk.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&rtc {
+	compatible = "st,stm32-rtc";
+	reg = < 0x40002800 0xc00 >;
+	interrupts = < 0x2 0x0 >;
+	clocks = < &rcc 0x58 0x400 >, < &rcc 0x2 0x16890 >;
+	prescaler = < 0x8000 >;
+	status = "okay";
+	wakeup-source;
+};
diff --git a/tests/subsys/pm/power_wakeup_timer/prj.conf b/tests/subsys/pm/power_wakeup_timer/prj.conf
new file mode 100644
index 00000000000..2cb955a5877
--- /dev/null
+++ b/tests/subsys/pm/power_wakeup_timer/prj.conf
@@ -0,0 +1,7 @@
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_RTC=y
+CONFIG_RTC_ALARM=y
+CONFIG_RTC_STM32=y
+CONFIG_PM=y
diff --git a/tests/subsys/pm/power_wakeup_timer/src/main.c b/tests/subsys/pm/power_wakeup_timer/src/main.c
new file mode 100644
index 00000000000..14599ef253b
--- /dev/null
+++ b/tests/subsys/pm/power_wakeup_timer/src/main.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2025 Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/rtc.h>
+
+#define RTC_ALARM_FIELDS                                                                           \
+	(RTC_ALARM_TIME_MASK_SECOND | RTC_ALARM_TIME_MASK_MINUTE | RTC_ALARM_TIME_MASK_HOUR)
+
+static const struct device *rtc = DEVICE_DT_GET(DT_NODELABEL(rtc));
+
+static k_tid_t my_tid;
+
+#define MY_STACK_SIZE 500
+#define MY_PRIORITY   5
+
+struct k_thread my_thread_data;
+K_THREAD_STACK_DEFINE(my_stack_area, MY_STACK_SIZE);
+
+void my_entry_point(void *, void *, void *)
+{
+	printk("Going sleep.\n");
+	k_msleep(3000);
+}
+
+/* Fri Jan 01 2021 13:29:50 GMT+0000 */
+static const struct rtc_time rtc_time = {
+	.tm_sec = 50,
+	.tm_min = 29,
+	.tm_hour = 13,
+	.tm_mday = 1,
+	.tm_mon = 0,
+	.tm_year = 121,
+	.tm_wday = 5,
+	.tm_yday = 1,
+	.tm_isdst = -1,
+	.tm_nsec = 0,
+};
+
+/* Fri Jan 01 2021 13:29:51 GMT+0000 */
+static const struct rtc_time alarm_time = {
+	.tm_sec = 51,
+	.tm_min = 29,
+	.tm_hour = 13,
+	.tm_mday = 1,
+	.tm_mon = 0,
+	.tm_year = 121,
+	.tm_wday = 5,
+	.tm_yday = 1,
+	.tm_isdst = -1,
+	.tm_nsec = 0,
+};
+
+static void wakeup_cb(const struct device *dev, uint16_t id, void *user_data)
+{
+	printk("Wake up by alarm.\n");
+	k_thread_abort(my_tid);
+}
+
+int main(void)
+{
+	int ret;
+	uint16_t mask = RTC_ALARM_FIELDS;
+
+	ret = rtc_set_time(rtc, &rtc_time);
+	if (ret < 0) {
+		return 0;
+	}
+
+	ret = rtc_alarm_set_time(rtc, 0, mask, &alarm_time);
+	if (ret < 0) {
+		return 0;
+	}
+
+	ret = rtc_alarm_set_callback(rtc, 0, wakeup_cb, NULL);
+	if (ret < 0) {
+		return 0;
+	}
+
+	printk("Created the thread.\n");
+	my_tid = k_thread_create(&my_thread_data, my_stack_area,
+				 K_THREAD_STACK_SIZEOF(my_stack_area), my_entry_point, NULL, NULL,
+				 NULL, MY_PRIORITY, 0, K_NO_WAIT);
+
+	k_thread_join(my_tid, K_FOREVER);
+
+	while (1) {
+		arch_nop();
+	}
+	return 0;
+}
diff --git a/tests/subsys/pm/power_wakeup_timer/testcase.yaml b/tests/subsys/pm/power_wakeup_timer/testcase.yaml
new file mode 100644
index 00000000000..454f7908a0d
--- /dev/null
+++ b/tests/subsys/pm/power_wakeup_timer/testcase.yaml
@@ -0,0 +1,32 @@
+# Copyright (c) 2025 Intel Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+common:
+  harness: power
+  harness_config:
+    fixture: pm_probe
+    pytest_dut_scope: session
+    power_measurements:
+      elements_to_trim: 100
+      min_peak_distance: 40
+      min_peak_height: 0.008
+      peak_padding: 40
+      measurement_duration: 2
+      num_of_transitions: 1
+      expected_rms_values: [0.26, 140]
+      tolerance_percentage: 10
+
+tests:
+  pm.power_wakeup_timer:
+    platform_allow:
+      - stm32l562e_dk
+    tags:
+      - pm
+
+  pm.power_wakeup_timer.pm_device:
+    platform_allow:
+      - stm32l562e_dk
+    tags:
+      - pm
+    extra_args:
+      - CONFIG_PM_DEVICE=y
diff --git a/tests/subsys/portability/cmsis_rtos_v2/prj.conf b/tests/subsys/portability/cmsis_rtos_v2/prj.conf
index d8e93b74785..4f8f887adb3 100644
--- a/tests/subsys/portability/cmsis_rtos_v2/prj.conf
+++ b/tests/subsys/portability/cmsis_rtos_v2/prj.conf
@@ -11,7 +11,7 @@ CONFIG_INIT_STACKS=y
 CONFIG_MAX_THREAD_BYTES=4
 CONFIG_SCHED_SCALABLE=y
 CONFIG_CMSIS_V2_MEM_SLAB_MAX_DYNAMIC_SIZE=128
-CONFIG_CMSIS_V2_THREAD_MAX_COUNT=23
+CONFIG_CMSIS_V2_THREAD_MAX_COUNT=25
 CONFIG_CMSIS_V2_THREAD_DYNAMIC_MAX_COUNT=10
 CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE=1024
 CONFIG_CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE=1024
diff --git a/tests/subsys/portability/cmsis_rtos_v2/src/event_flags.c b/tests/subsys/portability/cmsis_rtos_v2/src/event_flags.c
index c4906eb5e96..9d84d6b9d4e 100644
--- a/tests/subsys/portability/cmsis_rtos_v2/src/event_flags.c
+++ b/tests/subsys/portability/cmsis_rtos_v2/src/event_flags.c
@@ -6,17 +6,18 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/kernel.h>
-#include <cmsis_os2.h>
+#include <zephyr/portability/cmsis_os2.h>
+#include <zephyr/portability/cmsis_types.h>
 
 #include <zephyr/irq_offload.h>
 #include <zephyr/kernel_structs.h>
 
-#define TIMEOUT_TICKS   (100)
-#define FLAG1           (0x00000020)
-#define FLAG2           (0x00000004)
-#define FLAG            (FLAG1 | FLAG2)
-#define ISR_FLAG        0x50
-#define STACKSZ         CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE
+#define TIMEOUT_TICKS (100)
+#define FLAG1         (0x00000020)
+#define FLAG2         (0x00000004)
+#define FLAG          (FLAG1 | FLAG2)
+#define ISR_FLAG      0x50
+#define STACKSZ       CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE
 
 osEventFlagsId_t evt_id;
 
@@ -77,12 +78,10 @@ void test_event_flags_no_wait_timeout(void)
 	zassert_true(evt_id != NULL, "Failed creating event flags");
 
 	name = osEventFlagsGetName(dummy_id);
-	zassert_true(name == NULL,
-		     "Invalid event Flags ID is unexpectedly working!");
+	zassert_true(name == NULL, "Invalid event Flags ID is unexpectedly working!");
 
 	name = osEventFlagsGetName(evt_id);
-	zassert_str_equal(event_flags_attrs.name, name,
-			  "Error getting event_flags object name");
+	zassert_str_equal(event_flags_attrs.name, name, "Error getting event_flags object name");
 
 	id1 = osThreadNew(thread1, evt_id, &thread1_attr);
 	zassert_true(id1 != NULL, "Failed creating thread1");
@@ -93,8 +92,7 @@ void test_event_flags_no_wait_timeout(void)
 	/* wait for FLAG1. It should return immediately as it is
 	 * already triggered.
 	 */
-	flags = osEventFlagsWait(evt_id, FLAG1,
-				 osFlagsWaitAny | osFlagsNoClear, 0);
+	flags = osEventFlagsWait(evt_id, FLAG1, osFlagsWaitAny | osFlagsNoClear, 0);
 	zassert_equal(flags & FLAG1, FLAG1, "");
 
 	/* Since the flags are not cleared automatically in the previous step,
@@ -104,8 +102,7 @@ void test_event_flags_no_wait_timeout(void)
 	zassert_equal(flags & FLAG1, FLAG1, "");
 
 	flags = osEventFlagsGet(dummy_id);
-	zassert_true(flags == 0U,
-		     "Invalid event Flags ID is unexpectedly working!");
+	zassert_true(flags == 0U, "Invalid event Flags ID is unexpectedly working!");
 	/* Clear the Flag explicitly */
 	flags = osEventFlagsClear(evt_id, FLAG1);
 	zassert_not_equal(flags, osFlagsErrorParameter, "Event clear failed");
@@ -135,34 +132,29 @@ void test_event_flags_signalled(void)
 	 * upon being set since "osFlagsNoClear" is not opted for.
 	 */
 	flags = osEventFlagsWait(evt_id, FLAG, osFlagsWaitAll, TIMEOUT_TICKS);
-	zassert_equal(flags & FLAG, FLAG,
-		      "osEventFlagsWait failed unexpectedly");
+	zassert_equal(flags & FLAG, FLAG, "osEventFlagsWait failed unexpectedly");
 
 	/* set any single flag */
 	flags = osEventFlagsSet(evt_id, FLAG1);
 	zassert_equal(flags & FLAG1, FLAG1, "set any flag failed");
 
 	flags = osEventFlagsWait(evt_id, FLAG1, osFlagsWaitAny, TIMEOUT_TICKS);
-	zassert_equal(flags & FLAG1, FLAG1,
-		      "osEventFlagsWait failed unexpectedly");
+	zassert_equal(flags & FLAG1, FLAG1, "osEventFlagsWait failed unexpectedly");
 
 	/* validate by passing invalid parameters */
 	zassert_equal(osEventFlagsSet(NULL, 0), osFlagsErrorParameter,
 		      "Invalid event Flags ID is unexpectedly working!");
-	zassert_equal(osEventFlagsSet(evt_id, 0x80010000),
-		      osFlagsErrorParameter,
+	zassert_equal(osEventFlagsSet(evt_id, 0x80010000), osFlagsErrorParameter,
 		      "Event with MSB set is set unexpectedly");
 
 	zassert_equal(osEventFlagsClear(NULL, 0), osFlagsErrorParameter,
 		      "Invalid event Flags ID is unexpectedly working!");
-	zassert_equal(osEventFlagsClear(evt_id, 0x80010000),
-		      osFlagsErrorParameter,
+	zassert_equal(osEventFlagsClear(evt_id, 0x80010000), osFlagsErrorParameter,
 		      "Event with MSB set is cleared unexpectedly");
 
 	/* cannot wait for Flag mask with MSB set */
 	zassert_equal(osEventFlagsWait(evt_id, 0x80010000, osFlagsWaitAny, 0),
-		      osFlagsErrorParameter,
-		      "EventFlagsWait passed unexpectedly");
+		      osFlagsErrorParameter, "EventFlagsWait passed unexpectedly");
 }
 
 /* IRQ offload function handler to set event flag */
@@ -174,8 +166,7 @@ static void offload_function(const void *param)
 	zassert_true(k_is_in_isr(), "Not in IRQ context!");
 
 	flags = osEventFlagsSet((osEventFlagsId_t)param, ISR_FLAG);
-	zassert_equal(flags & ISR_FLAG, ISR_FLAG,
-		      "EventFlagsSet failed in ISR");
+	zassert_equal(flags & ISR_FLAG, ISR_FLAG, "EventFlagsSet failed in ISR");
 }
 
 void test_event_from_isr(void *event_id)
@@ -201,21 +192,17 @@ void test_event_flags_isr(void)
 	id = osThreadNew(test_event_from_isr, evt_id, &thread3_attr);
 	zassert_true(id != NULL, "Failed creating thread");
 
-	flags = osEventFlagsWait(dummy_id, ISR_FLAG,
-				 osFlagsWaitAll, TIMEOUT_TICKS);
+	flags = osEventFlagsWait(dummy_id, ISR_FLAG, osFlagsWaitAll, TIMEOUT_TICKS);
 	zassert_true(flags == osFlagsErrorParameter,
 		     "Invalid event Flags ID is unexpectedly working!");
 
-	flags = osEventFlagsWait(evt_id, ISR_FLAG,
-				 osFlagsWaitAll, TIMEOUT_TICKS);
-	zassert_equal((flags & ISR_FLAG),
-		      ISR_FLAG, "unexpected event flags value");
+	flags = osEventFlagsWait(evt_id, ISR_FLAG, osFlagsWaitAll, TIMEOUT_TICKS);
+	zassert_equal((flags & ISR_FLAG), ISR_FLAG, "unexpected event flags value");
 
 	zassert_true(osEventFlagsDelete(dummy_id) == osErrorResource,
 		     "Invalid event Flags ID is unexpectedly working!");
 
-	zassert_true(osEventFlagsDelete(evt_id) == osOK,
-		     "EventFlagsDelete failed");
+	zassert_true(osEventFlagsDelete(evt_id) == osOK, "EventFlagsDelete failed");
 }
 ZTEST(cmsis_event_flags, test_event_flags)
 {
@@ -228,4 +215,21 @@ ZTEST(cmsis_event_flags, test_event_flags)
 	test_event_flags_signalled();
 	test_event_flags_isr();
 }
+
+static struct cmsis_rtos_event_cb event_cb2;
+static const osEventFlagsAttr_t event_flags_attrs2 = {
+	.name = "Event2",
+	.attr_bits = 0,
+	.cb_mem = &event_cb2,
+	.cb_size = sizeof(event_cb2),
+};
+ZTEST(cmsis_event_flags, test_event_flags_static_allocation)
+{
+	osEventFlagsId_t id;
+
+	id = osEventFlagsNew(&event_flags_attrs2);
+	zassert_not_null(id, "Failed creating event flags using static cb");
+
+	zassert_true(osEventFlagsDelete(evt_id) == osOK, "EventFlagsDelete failed");
+}
 ZTEST_SUITE(cmsis_event_flags, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/subsys/portability/cmsis_rtos_v2/src/kernel.c b/tests/subsys/portability/cmsis_rtos_v2/src/kernel.c
index 96071d0f1fc..a8cf5a8af63 100644
--- a/tests/subsys/portability/cmsis_rtos_v2/src/kernel.c
+++ b/tests/subsys/portability/cmsis_rtos_v2/src/kernel.c
@@ -60,18 +60,12 @@ void lock_unlock_check(const void *arg)
 ZTEST(cmsis_kernel, test_kernel_apis)
 {
 	versionInfo version = {
-		.os_info = {
-			.api = 0xfefefefe,
-			.kernel = 0xfdfdfdfd,
-		},
-		.info = "local function call info is uninitialized"
+		.os_info = {.api = 0xfefefefe, .kernel = 0xfdfdfdfd},
+		.info = "local function call info is uninitialized",
 	};
 	versionInfo version_irq = {
-		.os_info = {
-			.api = 0xfcfcfcfc,
-			.kernel = 0xfbfbfbfb,
-		},
-		.info = "irq_offload function call info is uninitialized"
+		.os_info = {.api = 0xfcfcfcfc, .kernel = 0xfbfbfbfb},
+		.info = "irq_offload function call info is uninitialized",
 	};
 
 	get_version_check(&version);
diff --git a/tests/subsys/portability/cmsis_rtos_v2/src/mempool.c b/tests/subsys/portability/cmsis_rtos_v2/src/mempool.c
index c0e4530f864..26cccb56f2a 100644
--- a/tests/subsys/portability/cmsis_rtos_v2/src/mempool.c
+++ b/tests/subsys/portability/cmsis_rtos_v2/src/mempool.c
@@ -6,10 +6,11 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/kernel.h>
-#include <cmsis_os2.h>
+#include <zephyr/portability/cmsis_os2.h>
+#include <zephyr/portability/cmsis_types.h>
 
-#define MAX_BLOCKS      10
-#define TIMEOUT_TICKS   10
+#define MAX_BLOCKS    10
+#define TIMEOUT_TICKS 10
 
 struct mem_block {
 	int member1;
@@ -26,8 +27,7 @@ static const osMemoryPoolAttr_t mp_attrs = {
 	.mp_size = sizeof(struct mem_block) * MAX_BLOCKS,
 };
 
-static void mempool_common_tests(osMemoryPoolId_t mp_id,
-				 const char *expected_name)
+static void mempool_common_tests(osMemoryPoolId_t mp_id, const char *expected_name)
 {
 	int i;
 	osMemoryPoolId_t dummy_id = NULL;
@@ -50,8 +50,7 @@ static void mempool_common_tests(osMemoryPoolId_t mp_id,
 	zassert_equal(osMemoryPoolGetBlockSize(dummy_id), 0,
 		      "Something's wrong with osMemoryPoolGetBlockSize!");
 
-	zassert_equal(osMemoryPoolGetBlockSize(mp_id),
-		      sizeof(struct mem_block),
+	zassert_equal(osMemoryPoolGetBlockSize(mp_id), sizeof(struct mem_block),
 		      "Something's wrong with osMemoryPoolGetBlockSize!");
 
 	/* The memory pool should be completely available at this point */
@@ -61,8 +60,7 @@ static void mempool_common_tests(osMemoryPoolId_t mp_id,
 		      "Something's wrong with osMemoryPoolGetSpace!");
 
 	for (i = 0; i < MAX_BLOCKS; i++) {
-		addr_list[i] = (struct mem_block *)osMemoryPoolAlloc(mp_id,
-								     osWaitForever);
+		addr_list[i] = (struct mem_block *)osMemoryPoolAlloc(mp_id, osWaitForever);
 		zassert_true(addr_list[i] != NULL, "mempool allocation failed");
 	}
 
@@ -75,13 +73,12 @@ static void mempool_common_tests(osMemoryPoolId_t mp_id,
 	/* All blocks in mempool are allocated, any more allocation
 	 * without free should fail
 	 */
-	addr_list[i] = (struct mem_block *)osMemoryPoolAlloc(mp_id,
-							     TIMEOUT_TICKS);
+	addr_list[i] = (struct mem_block *)osMemoryPoolAlloc(mp_id, TIMEOUT_TICKS);
 	zassert_true(addr_list[i] == NULL, "allocation happened."
-		     " Something's wrong!");
+					   " Something's wrong!");
 
-	zassert_equal(osMemoryPoolFree(dummy_id, addr_list[0]),
-		      osErrorParameter, "mempool free worked unexpectedly!");
+	zassert_equal(osMemoryPoolFree(dummy_id, addr_list[0]), osErrorParameter,
+		      "mempool free worked unexpectedly!");
 
 	for (i = 0; i < MAX_BLOCKS; i++) {
 		status = osMemoryPoolFree(mp_id, addr_list[i]);
@@ -104,8 +101,7 @@ ZTEST(cmsis_mempool, test_mempool_dynamic)
 {
 	osMemoryPoolId_t mp_id;
 
-	mp_id = osMemoryPoolNew(MAX_BLOCKS, sizeof(struct mem_block),
-				NULL);
+	mp_id = osMemoryPoolNew(MAX_BLOCKS, sizeof(struct mem_block), NULL);
 	zassert_true(mp_id != NULL, "mempool creation failed");
 
 	mempool_common_tests(mp_id, "ZephyrMemPool");
@@ -121,14 +117,36 @@ ZTEST(cmsis_mempool, test_mempool)
 	osMemoryPoolId_t mp_id;
 
 	/* Create memory pool with invalid block size */
-	mp_id = osMemoryPoolNew(MAX_BLOCKS + 1, sizeof(struct mem_block),
-				&mp_attrs);
+	mp_id = osMemoryPoolNew(MAX_BLOCKS + 1, sizeof(struct mem_block), &mp_attrs);
 	zassert_true(mp_id == NULL, "osMemoryPoolNew worked unexpectedly!");
 
-	mp_id = osMemoryPoolNew(MAX_BLOCKS, sizeof(struct mem_block),
-				&mp_attrs);
+	mp_id = osMemoryPoolNew(MAX_BLOCKS, sizeof(struct mem_block), &mp_attrs);
 	zassert_true(mp_id != NULL, "mempool creation failed");
 
 	mempool_common_tests(mp_id, mp_attrs.name);
 }
+
+static struct cmsis_rtos_mempool_cb mempool_cb2;
+static const osMemoryPoolAttr_t mp_attrs2 = {
+	.name = "TestMempool2",
+	.attr_bits = 0,
+	.cb_mem = &mempool_cb2,
+	.cb_size = sizeof(mempool_cb2),
+	.mp_mem = sample_mem,
+	.mp_size = sizeof(struct mem_block) * MAX_BLOCKS,
+};
+/**
+ * @brief Test memory pool allocation and free
+ *
+ * @see osMemoryPoolNew(), osMemoryPoolAlloc(), osMemoryPoolFree(),
+ */
+ZTEST(cmsis_mempool, test_mempool_static_allocation)
+{
+	osMemoryPoolId_t mp_id;
+
+	mp_id = osMemoryPoolNew(MAX_BLOCKS, sizeof(struct mem_block), &mp_attrs2);
+	zassert_true(mp_id != NULL, "mempool creation failed");
+
+	mempool_common_tests(mp_id, mp_attrs2.name);
+}
 ZTEST_SUITE(cmsis_mempool, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/subsys/portability/cmsis_rtos_v2/src/msgq.c b/tests/subsys/portability/cmsis_rtos_v2/src/msgq.c
index 0ec116e88e2..ae0a2e7df85 100644
--- a/tests/subsys/portability/cmsis_rtos_v2/src/msgq.c
+++ b/tests/subsys/portability/cmsis_rtos_v2/src/msgq.c
@@ -6,7 +6,8 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/kernel.h>
-#include <cmsis_os2.h>
+#include <zephyr/portability/cmsis_os2.h>
+#include <zephyr/portability/cmsis_types.h>
 
 struct sample_data {
 	int data1;
@@ -14,11 +15,11 @@ struct sample_data {
 	unsigned int data3;
 };
 
-#define MESSAGE1        512
-#define MESSAGE2        123456
-#define TIMEOUT_TICKS   50
-#define Q_LEN           5
-#define STACKSZ         CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE
+#define MESSAGE1      512
+#define MESSAGE2      123456
+#define TIMEOUT_TICKS 50
+#define Q_LEN         5
+#define STACKSZ       CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE
 
 osMessageQueueId_t message_id;
 
@@ -27,7 +28,7 @@ void send_msg_thread(void *argument)
 	int i;
 	osStatus_t status;
 	struct sample_data sample;
-	struct sample_data data[Q_LEN] = { { 0 } };
+	struct sample_data data[Q_LEN] = {{0}};
 
 	/* Wait for message_recv to complete initial checks */
 	osDelay(TIMEOUT_TICKS);
@@ -48,10 +49,8 @@ void send_msg_thread(void *argument)
 		data[i].data1 = i * 3;
 		data[i].data2 = i * 3 + 1;
 		data[i].data3 = i * 3 + 2;
-		status = osMessageQueuePut(message_id, data + i,
-					   0, osWaitForever);
-		zassert_true(status == osOK,
-			     "osMessageQueuePut failure for message!");
+		status = osMessageQueuePut(message_id, data + i, 0, osWaitForever);
+		zassert_true(status == osOK, "osMessageQueuePut failure for message!");
 	}
 
 	/* The Queue should be full at this point */
@@ -65,22 +64,19 @@ void send_msg_thread(void *argument)
 	 */
 	sample.data1 = MESSAGE2;
 	status = osMessageQueuePut(message_id, &sample, 0, 0);
-	zassert_true(status == osErrorResource,
-		     "Something's wrong with osMessageQueuePut!");
+	zassert_true(status == osErrorResource, "Something's wrong with osMessageQueuePut!");
 
 	/* Try putting message to a full queue within a duration
 	 * less than TIMEOUT_TICKS, before the queue is emptied out
 	 */
 	sample.data1 = MESSAGE2;
 	status = osMessageQueuePut(message_id, &sample, 0, TIMEOUT_TICKS / 2);
-	zassert_true(status == osErrorTimeout,
-		     "Something's wrong with osMessageQueuePut!");
+	zassert_true(status == osErrorTimeout, "Something's wrong with osMessageQueuePut!");
 
 	/* Send another message after the queue is emptied */
 	sample.data1 = MESSAGE2;
 	status = osMessageQueuePut(message_id, &sample, 0, TIMEOUT_TICKS * 2);
-	zassert_true(status == osOK,
-		     "osMessageQueuePut failure for message!");
+	zassert_true(status == osOK, "osMessageQueuePut failure for message!");
 }
 
 void message_recv(void)
@@ -91,25 +87,20 @@ void message_recv(void)
 
 	/* Try getting message immediately before the queue is populated */
 	status = osMessageQueueGet(message_id, (void *)&recv_data, NULL, 0);
-	zassert_true(status == osErrorResource,
-		     "Something's wrong with osMessageQueueGet!");
+	zassert_true(status == osErrorResource, "Something's wrong with osMessageQueueGet!");
 
 	/* Try receiving message within a duration of TIMEOUT */
-	status = osMessageQueueGet(message_id, (void *)&recv_data,
-				   NULL, TIMEOUT_TICKS);
-	zassert_true(status == osErrorTimeout,
-		     "Something's wrong with osMessageQueueGet!");
+	status = osMessageQueueGet(message_id, (void *)&recv_data, NULL, TIMEOUT_TICKS);
+	zassert_true(status == osErrorTimeout, "Something's wrong with osMessageQueueGet!");
 
 	zassert_equal(osMessageQueueGetCapacity(message_id), Q_LEN,
 		      "Something's wrong with osMessageQueueGetCapacity!");
 
-	zassert_equal(osMessageQueueGetMsgSize(message_id),
-		      sizeof(struct sample_data),
+	zassert_equal(osMessageQueueGetMsgSize(message_id), sizeof(struct sample_data),
 		      "Something's wrong with osMessageQueueGetMsgSize!");
 
 	/* Receive 1st message */
-	status = osMessageQueueGet(message_id, (void *)&recv_data,
-				   NULL, osWaitForever);
+	status = osMessageQueueGet(message_id, (void *)&recv_data, NULL, osWaitForever);
 	zassert_true(status == osOK, "osMessageQueueGet failure");
 	zassert_equal(recv_data.data1, MESSAGE1);
 
@@ -118,8 +109,7 @@ void message_recv(void)
 
 	/* Empty the queue */
 	for (i = 0; i < Q_LEN; i++) {
-		status = osMessageQueueGet(message_id, (void *)&recv_data, NULL,
-					   osWaitForever);
+		status = osMessageQueueGet(message_id, (void *)&recv_data, NULL, osWaitForever);
 		zassert_true(status == osOK, "osMessageQueueGet failure");
 
 		zassert_equal(recv_data.data1, i * 3);
@@ -128,8 +118,7 @@ void message_recv(void)
 	}
 
 	/* Receive the next message */
-	status = osMessageQueueGet(message_id, (void *)&recv_data,
-				   NULL, osWaitForever);
+	status = osMessageQueueGet(message_id, (void *)&recv_data, NULL, osWaitForever);
 	zassert_true(status == osOK, "osMessageQueueGet failure");
 	zassert_equal(recv_data.data1, MESSAGE2);
 }
@@ -158,9 +147,8 @@ ZTEST(cmsis_msgq, test_messageq)
 	struct sample_data sample;
 	osThreadId_t tid;
 
-	message_id = osMessageQueueNew(Q_LEN, sizeof(struct sample_data),
-				       &init_mem_attrs);
-	zassert_true(message_id != NULL, "Message creation failed");
+	message_id = osMessageQueueNew(Q_LEN, sizeof(struct sample_data), &init_mem_attrs);
+	zassert_true(message_id != NULL, "Message Queue creation failed");
 
 	tid = osThreadNew(send_msg_thread, NULL, &thread_attr);
 	zassert_true(tid != NULL, "Thread creation failed");
@@ -193,4 +181,25 @@ ZTEST(cmsis_msgq, test_messageq)
 	status = osMessageQueueDelete(message_id);
 	zassert_true(status == osOK, "osMessageQueueDelete failure");
 }
+
+static struct cmsis_rtos_msgq_cb msgq_cb2;
+static const osMessageQueueAttr_t msgq_attrs2 = {
+	.name = "TestMsgQ2",
+	.attr_bits = 0,
+	.cb_mem = &msgq_cb2,
+	.cb_size = sizeof(msgq_cb2),
+	.mq_mem = sample_mem,
+	.mq_size = sizeof(struct sample_data) * Q_LEN,
+};
+ZTEST(cmsis_msgq, test_messageq_static_allocation)
+{
+	osMessageQueueId_t message_id;
+	osStatus_t status;
+
+	message_id = osMessageQueueNew(Q_LEN, sizeof(struct sample_data), &msgq_attrs2);
+	zassert_true(message_id != NULL, "Message Queue creation failed with static cb");
+
+	status = osMessageQueueDelete(message_id);
+	zassert_true(status == osOK, "osMessageQueueDelete failure");
+}
 ZTEST_SUITE(cmsis_msgq, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/subsys/portability/cmsis_rtos_v2/src/mutex.c b/tests/subsys/portability/cmsis_rtos_v2/src/mutex.c
index bfb1b0735d5..df9d8624350 100644
--- a/tests/subsys/portability/cmsis_rtos_v2/src/mutex.c
+++ b/tests/subsys/portability/cmsis_rtos_v2/src/mutex.c
@@ -6,19 +6,15 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/kernel.h>
-#include <cmsis_os2.h>
+#include <zephyr/portability/cmsis_os2.h>
+#include <zephyr/portability/cmsis_types.h>
 
-#define WAIT_TICKS      5
-#define TIMEOUT_TICKS   (10 + WAIT_TICKS)
-#define STACKSZ         CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE
+#define WAIT_TICKS    5
+#define TIMEOUT_TICKS (10 + WAIT_TICKS)
+#define STACKSZ       CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE
 
 int max_mtx_cnt = CONFIG_CMSIS_V2_MUTEX_MAX_COUNT;
-const osMutexAttr_t mutex_attr = {
-	"myMutex",
-	osMutexRecursive | osMutexPrioInherit,
-	NULL,
-	0U
-};
+const osMutexAttr_t mutex_attr = {"myMutex", osMutexRecursive | osMutexPrioInherit, NULL, 0U};
 
 void cleanup_max_mutex(osMutexId_t *mutex_ids)
 {
@@ -59,8 +55,7 @@ ZTEST(cmsis_mutex, test_mutex)
 
 	/* Try deleting invalid mutex object */
 	status = osMutexDelete(mutex_id);
-	zassert_true(status == osErrorParameter,
-		     "Invalid Mutex deleted unexpectedly!");
+	zassert_true(status == osErrorParameter, "Invalid Mutex deleted unexpectedly!");
 
 	mutex_id = osMutexNew(&mutex_attr);
 	zassert_true(mutex_id != NULL, "Mutex1 creation failed");
@@ -124,8 +119,7 @@ void tThread_entry_lock_timeout(void *arg)
 	zassert_true(status == osErrorResource, "Mutex unexpectedly released");
 
 	id = osMutexGetOwner((osMutexId_t)arg);
-	zassert_not_equal(id, osThreadGetId(),
-			  "Unexpectedly, current thread is the mutex owner!");
+	zassert_not_equal(id, osThreadGetId(), "Unexpectedly, current thread is the mutex owner!");
 
 	/* This delay ensures that the mutex gets released by the other
 	 * thread in the meantime
@@ -141,17 +135,15 @@ void tThread_entry_lock_timeout(void *arg)
 }
 
 static K_THREAD_STACK_DEFINE(test_stack, STACKSZ);
-static osThreadAttr_t thread_attr = {
-	.name = "Mutex_check",
-	.attr_bits = osThreadDetached,
-	.cb_mem = NULL,
-	.cb_size = 0,
-	.stack_mem = &test_stack,
-	.stack_size = STACKSZ,
-	.priority = osPriorityNormal,
-	.tz_module = 0,
-	.reserved = 0
-};
+static osThreadAttr_t thread_attr = {.name = "Mutex_check",
+				     .attr_bits = osThreadDetached,
+				     .cb_mem = NULL,
+				     .cb_size = 0,
+				     .stack_mem = &test_stack,
+				     .stack_size = STACKSZ,
+				     .priority = osPriorityNormal,
+				     .tz_module = 0,
+				     .reserved = 0};
 
 ZTEST(cmsis_mutex, test_mutex_lock_timeout)
 {
@@ -177,4 +169,33 @@ ZTEST(cmsis_mutex, test_mutex_lock_timeout)
 
 	osMutexDelete(mutex_id);
 }
+
+static struct cmsis_rtos_mutex_cb mutex_cb2;
+static const osMutexAttr_t mutex_attrs2 = {
+	.name = "Mutex2",
+	.attr_bits = osMutexPrioInherit,
+	.cb_mem = &mutex_cb2,
+	.cb_size = sizeof(mutex_cb2),
+};
+ZTEST(cmsis_mutex, test_mutex_static_allocation)
+{
+	osMutexId_t id;
+
+	id = osMutexNew(&mutex_attrs2);
+	zassert_not_null(id, "Failed creating mutex using static cb");
+
+	zassert_true(osMutexDelete(id) == osOK, "osMutexDelete failed");
+}
+
+ZTEST(cmsis_mutex, test_mutex_static_multiple_new)
+{
+	osMutexId_t id;
+
+	for (int i = 0; i < 100; ++i) {
+		id = osMutexNew(&mutex_attrs2);
+		zassert_not_null(id, "Failed creating mutex using static cb");
+
+		zassert_true(osMutexDelete(id) == osOK, "osMutexDelete failed");
+	}
+}
 ZTEST_SUITE(cmsis_mutex, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/subsys/portability/cmsis_rtos_v2/src/semaphore.c b/tests/subsys/portability/cmsis_rtos_v2/src/semaphore.c
index 9259cf69b47..9258b625888 100644
--- a/tests/subsys/portability/cmsis_rtos_v2/src/semaphore.c
+++ b/tests/subsys/portability/cmsis_rtos_v2/src/semaphore.c
@@ -6,11 +6,12 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/kernel.h>
-#include <cmsis_os2.h>
+#include <zephyr/portability/cmsis_os2.h>
+#include <zephyr/portability/cmsis_types.h>
 
-#define WAIT_TICKS      5
-#define TIMEOUT_TICKS   (10 + WAIT_TICKS)
-#define STACKSZ         CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE
+#define WAIT_TICKS    5
+#define TIMEOUT_TICKS (10 + WAIT_TICKS)
+#define STACKSZ       CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE
 
 void thread_sema(void *arg)
 {
@@ -18,13 +19,11 @@ void thread_sema(void *arg)
 
 	/* Try taking semaphore immediately when it is not available */
 	status = osSemaphoreAcquire((osSemaphoreId_t)arg, 0);
-	zassert_true(status == osErrorResource,
-		     "Semaphore acquired unexpectedly!");
+	zassert_true(status == osErrorResource, "Semaphore acquired unexpectedly!");
 
 	/* Try taking semaphore after a TIMEOUT, but before release */
 	status = osSemaphoreAcquire((osSemaphoreId_t)arg, WAIT_TICKS);
-	zassert_true(status == osErrorTimeout,
-		     "Semaphore acquired unexpectedly!");
+	zassert_true(status == osErrorTimeout, "Semaphore acquired unexpectedly!");
 
 	/* This delay ensures that the semaphore gets released by the other
 	 * thread in the meantime
@@ -37,34 +36,25 @@ void thread_sema(void *arg)
 	status = osSemaphoreAcquire((osSemaphoreId_t)arg, 0);
 	zassert_true(status == osOK, "Semaphore could not be acquired");
 
-	zassert_true(osSemaphoreRelease((osSemaphoreId_t)arg) == osOK,
-		     "Semaphore release failure");
+	zassert_true(osSemaphoreRelease((osSemaphoreId_t)arg) == osOK, "Semaphore release failure");
 
 	/* Try releasing when no semaphore is obtained */
-	zassert_true(
-		osSemaphoreRelease((osSemaphoreId_t)arg) == osErrorResource,
-		"Semaphore released unexpectedly!");
+	zassert_true(osSemaphoreRelease((osSemaphoreId_t)arg) == osErrorResource,
+		     "Semaphore released unexpectedly!");
 }
 
 static K_THREAD_STACK_DEFINE(test_stack, STACKSZ);
-static osThreadAttr_t thread_attr = {
-	.name = "Sema_check",
-	.attr_bits = osThreadDetached,
-	.cb_mem = NULL,
-	.cb_size = 0,
-	.stack_mem = &test_stack,
-	.stack_size = STACKSZ,
-	.priority = osPriorityNormal,
-	.tz_module = 0,
-	.reserved = 0
-};
-
-const osSemaphoreAttr_t sema_attr = {
-	"mySemaphore",
-	0,
-	NULL,
-	0U
-};
+static osThreadAttr_t thread_attr = {.name = "Sema_check",
+				     .attr_bits = osThreadDetached,
+				     .cb_mem = NULL,
+				     .cb_size = 0,
+				     .stack_mem = &test_stack,
+				     .stack_size = STACKSZ,
+				     .priority = osPriorityNormal,
+				     .tz_module = 0,
+				     .reserved = 0};
+
+const osSemaphoreAttr_t sema_attr = {"mySemaphore", 0, NULL, 0U};
 
 ZTEST(cmsis_semaphore, test_semaphore)
 {
@@ -78,8 +68,7 @@ ZTEST(cmsis_semaphore, test_semaphore)
 	zassert_true(semaphore_id != NULL, "semaphore creation failed");
 
 	name = osSemaphoreGetName(semaphore_id);
-	zassert_str_equal(sema_attr.name, name,
-			  "Error getting Semaphore name");
+	zassert_str_equal(sema_attr.name, name, "Error getting Semaphore name");
 
 	id = osThreadNew(thread_sema, semaphore_id, &thread_attr);
 	zassert_true(id != NULL, "Thread creation failed");
@@ -87,8 +76,8 @@ ZTEST(cmsis_semaphore, test_semaphore)
 	zassert_true(osSemaphoreGetCount(semaphore_id) == 1);
 
 	/* Acquire invalid semaphore */
-	zassert_equal(osSemaphoreAcquire(dummy_sem_id, osWaitForever),
-		      osErrorParameter, "Semaphore wait worked unexpectedly");
+	zassert_equal(osSemaphoreAcquire(dummy_sem_id, osWaitForever), osErrorParameter,
+		      "Semaphore wait worked unexpectedly");
 
 	status = osSemaphoreAcquire(semaphore_id, osWaitForever);
 	zassert_true(status == osOK, "Semaphore wait failure");
@@ -115,4 +104,21 @@ ZTEST(cmsis_semaphore, test_semaphore)
 	status = osSemaphoreDelete(semaphore_id);
 	zassert_true(status == osOK, "semaphore delete failure");
 }
+
+static struct cmsis_rtos_semaphore_cb semaphore_cb2;
+static const osSemaphoreAttr_t semaphore_attrs2 = {
+	.name = "Semaphore2",
+	.attr_bits = 0,
+	.cb_mem = &semaphore_cb2,
+	.cb_size = sizeof(semaphore_cb2),
+};
+ZTEST(cmsis_semaphore, test_semaphore_static_allocation)
+{
+	osSemaphoreId_t id;
+
+	id = osSemaphoreNew(1, 1, &semaphore_attrs2);
+	zassert_not_null(id, "Failed creating semaphores using static cb");
+
+	zassert_true(osSemaphoreDelete(id) == osOK, "semaphore delete failure");
+}
 ZTEST_SUITE(cmsis_semaphore, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/subsys/portability/cmsis_rtos_v2/src/thread_apis.c b/tests/subsys/portability/cmsis_rtos_v2/src/thread_apis.c
index ea73756a663..2edd435513b 100644
--- a/tests/subsys/portability/cmsis_rtos_v2/src/thread_apis.c
+++ b/tests/subsys/portability/cmsis_rtos_v2/src/thread_apis.c
@@ -6,9 +6,10 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/kernel.h>
-#include <cmsis_os2.h>
+#include <zephyr/portability/cmsis_os2.h>
+#include <zephyr/portability/cmsis_types.h>
 
-#define STACKSZ         CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE
+#define STACKSZ CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE
 
 /* This is used to check the thread yield functionality between 2 threads */
 static int thread_yield_check;
@@ -78,15 +79,13 @@ static void thread2(void *argument)
 
 	thread_array = k_calloc(max_num_threads, sizeof(osThreadId_t));
 	num_threads = osThreadEnumerate(thread_array, max_num_threads);
-	zassert_equal(num_threads, 2,
-		      "Incorrect number of cmsis rtos v2 threads");
+	zassert_equal(num_threads, 2, "Incorrect number of cmsis rtos v2 threads");
 
 	for (i = 0U; i < num_threads; i++) {
 		uint32_t size = osThreadGetStackSize(thread_array[i]);
 		uint32_t space = osThreadGetStackSpace(thread_array[i]);
 
-		zassert_true(space < size,
-			     "stack size remaining is not what is expected");
+		zassert_true(space < size, "stack size remaining is not what is expected");
 	}
 
 	zassert_equal(osThreadGetState(thread_array[1]), osThreadReady,
@@ -108,18 +107,13 @@ static void thread2(void *argument)
 	osThreadYield();
 }
 
-static void thread_apis_common(int *yield_check,
-			       const char *thread1_name,
-			       osThreadAttr_t *thread1_attr,
-			       osThreadAttr_t *thread2_attr)
+static void thread_apis_common(int *yield_check, const char *thread1_name,
+			       osThreadAttr_t *thread1_attr, osThreadAttr_t *thread2_attr)
 {
 	osThreadId_t id1;
 	osThreadId_t id2;
 
-	struct thread1_args args = {
-		.yield_check = yield_check,
-		.name = thread1_name
-	};
+	struct thread1_args args = {.yield_check = yield_check, .name = thread1_name};
 
 	id1 = osThreadNew(thread1, &args, thread1_attr);
 	zassert_true(id1 != NULL, "Failed creating thread1");
@@ -127,8 +121,7 @@ static void thread_apis_common(int *yield_check,
 	id2 = osThreadNew(thread2, yield_check, thread2_attr);
 	zassert_true(id2 != NULL, "Failed creating thread2");
 
-	zassert_equal(osThreadGetCount(), 2,
-		      "Incorrect number of cmsis rtos v2 threads");
+	zassert_equal(osThreadGetCount(), 2, "Incorrect number of cmsis rtos v2 threads");
 
 	do {
 		osDelay(100);
@@ -137,14 +130,13 @@ static void thread_apis_common(int *yield_check,
 
 ZTEST(cmsis_thread_apis, test_thread_apis_dynamic)
 {
-	thread_apis_common(&thread_yield_check_dynamic, "ZephyrThread",
-			   NULL, NULL);
+	thread_apis_common(&thread_yield_check_dynamic, "ZephyrThread", NULL, NULL);
 }
 
 ZTEST(cmsis_thread_apis, test_thread_apis)
 {
-	thread_apis_common(&thread_yield_check, os_thread1_attr.name,
-			   &os_thread1_attr, &os_thread2_attr);
+	thread_apis_common(&thread_yield_check, os_thread1_attr.name, &os_thread1_attr,
+			   &os_thread2_attr);
 }
 
 static osPriority_t OsPriorityInvalid = 60;
@@ -172,28 +164,24 @@ static void thread3(void *argument)
 	/* Lower the priority of the current thread */
 	osThreadSetPriority(id, osPriorityBelowNormal);
 	rv = osThreadGetPriority(id);
-	zassert_equal(rv, osPriorityBelowNormal,
-		      "Expected priority to be changed to %d, not %d",
+	zassert_equal(rv, osPriorityBelowNormal, "Expected priority to be changed to %d, not %d",
 		      (int)osPriorityBelowNormal, (int)rv);
 
 	/* Increase the priority of the current thread */
 	osThreadSetPriority(id, osPriorityAboveNormal);
 	rv = osThreadGetPriority(id);
-	zassert_equal(rv, osPriorityAboveNormal,
-		      "Expected priority to be changed to %d, not %d",
+	zassert_equal(rv, osPriorityAboveNormal, "Expected priority to be changed to %d, not %d",
 		      (int)osPriorityAboveNormal, (int)rv);
 
 	/* Restore the priority of the current thread */
 	osThreadSetPriority(id, prio);
 	rv = osThreadGetPriority(id);
-	zassert_equal(rv, prio,
-		      "Expected priority to be changed to %d, not %d",
-		      (int)prio, (int)rv);
+	zassert_equal(rv, prio, "Expected priority to be changed to %d, not %d", (int)prio,
+		      (int)rv);
 
 	/* Try to set unsupported priority and assert failure */
 	status = osThreadSetPriority(id, OsPriorityInvalid);
-	zassert_true(status == osErrorParameter,
-		     "Something's wrong with osThreadSetPriority!");
+	zassert_true(status == osErrorParameter, "Something's wrong with osThreadSetPriority!");
 
 	/* Indication that thread3 is done with its processing */
 	*state = 1;
@@ -224,13 +212,11 @@ static void thread_prior_common(int *state, osThreadAttr_t *attr)
 
 	/* Try to set priority to inactive thread and assert failure */
 	status = osThreadSetPriority(id3, osPriorityNormal);
-	zassert_true(status == osErrorResource,
-		     "Something's wrong with osThreadSetPriority!");
+	zassert_true(status == osErrorResource, "Something's wrong with osThreadSetPriority!");
 
 	/* Try to terminate inactive thread and assert failure */
 	status = osThreadTerminate(id3);
-	zassert_true(status == osErrorResource,
-		     "Something's wrong with osThreadTerminate!");
+	zassert_true(status == osErrorResource, "Something's wrong with osThreadTerminate!");
 
 	*state = 0;
 }
@@ -268,7 +254,7 @@ static void thread4(void *argument)
 
 ZTEST(cmsis_thread_apis, test_thread_join)
 {
-	osThreadAttr_t attr = { 0 };
+	osThreadAttr_t attr = {0};
 	int64_t time_stamp;
 	int64_t milliseconds_spent;
 	osThreadId_t tA, tB;
@@ -297,7 +283,7 @@ ZTEST(cmsis_thread_apis, test_thread_join)
 
 	milliseconds_spent = k_uptime_delta(&time_stamp);
 	zassert_true((milliseconds_spent >= DELAY_MS - DELTA_MS) &&
-		     (milliseconds_spent <= DELAY_MS + DELTA_MS),
+			     (milliseconds_spent <= DELAY_MS + DELTA_MS),
 		     "Join completed but was too fast or too slow.");
 
 	printk(" - Waiting for thread A to join...\n");
@@ -320,8 +306,7 @@ ZTEST(cmsis_thread_apis, test_thread_detached)
 	osDelay(k_ms_to_ticks_ceil32(DELAY_MS - DELTA_MS));
 
 	status = osThreadJoin(thread);
-	zassert_equal(status, osErrorResource,
-		      "Incorrect status returned from osThreadJoin!");
+	zassert_equal(status, osErrorResource, "Incorrect status returned from osThreadJoin!");
 
 	osDelay(k_ms_to_ticks_ceil32(DELTA_MS));
 }
@@ -331,14 +316,16 @@ void thread6(void *argument)
 	osThreadId_t thread = argument;
 	osStatus_t status;
 
+	/* Thread passed as argument may or may not have already terminated, but is expected to be
+	 * joinable for this test as it was created with osThreadJoinable attr_bits.
+	 */
 	status = osThreadJoin(thread);
-	zassert_equal(status, osErrorResource,
-		      "Incorrect status returned from osThreadJoin!");
+	zassert_equal(status, osOK, "Incorrect status returned from osThreadJoin!");
 }
 
 ZTEST(cmsis_thread_apis, test_thread_joinable_detach)
 {
-	osThreadAttr_t attr = { 0 };
+	osThreadAttr_t attr = {0};
 	osThreadId_t tA, tB;
 	osStatus_t status;
 
@@ -360,7 +347,7 @@ ZTEST(cmsis_thread_apis, test_thread_joinable_detach)
 
 ZTEST(cmsis_thread_apis, test_thread_joinable_terminate)
 {
-	osThreadAttr_t attr = { 0 };
+	osThreadAttr_t attr = {0};
 	osThreadId_t tA, tB;
 	osStatus_t status;
 
@@ -379,4 +366,85 @@ ZTEST(cmsis_thread_apis, test_thread_joinable_terminate)
 
 	osDelay(k_ms_to_ticks_ceil32(DELTA_MS));
 }
+
+static K_THREAD_STACK_DEFINE(test_stack7, STACKSZ);
+static struct cmsis_rtos_thread_cb test_cb7;
+static const osThreadAttr_t os_thread7_attr = {
+	.name = "Thread7",
+	.cb_mem = &test_cb7,
+	.cb_size = sizeof(test_cb7),
+	.stack_mem = &test_stack7,
+	.stack_size = STACKSZ,
+	.priority = osPriorityNormal,
+};
+static void thread7(void *argument)
+{
+	printf("Thread 7 ran\n");
+}
+ZTEST(cmsis_thread_apis, test_thread_apis_static_allocation)
+{
+	osThreadId_t id;
+
+	id = osThreadNew(thread7, NULL, &os_thread7_attr);
+	zassert_not_null(id, "Failed to create thread with osThreadNew using static cb/stack");
+}
+
+static K_THREAD_STACK_DEFINE(test_stack8, STACKSZ);
+static struct cmsis_rtos_thread_cb test_cb8;
+static const osThreadAttr_t os_thread8_attr = {
+	.name = "Thread8",
+	.attr_bits = osThreadJoinable,
+	.cb_mem = &test_cb8,
+	.cb_size = sizeof(test_cb8),
+	.stack_mem = &test_stack8,
+	.stack_size = STACKSZ,
+	.priority = osPriorityNormal,
+};
+static void thread8(void *argument)
+{
+	printf("Thread 8 ran\n");
+	osDelay(k_ms_to_ticks_ceil32(DELAY_MS));
+	osThreadExit();
+}
+ZTEST(cmsis_thread_apis, test_thread_apis_join_after_exit)
+{
+	osThreadId_t id;
+	osStatus_t status;
+
+	id = osThreadNew(thread8, NULL, &os_thread8_attr);
+	zassert_not_null(id, "Failed to create thread with osThreadNew using static cb/stack");
+
+	status = osThreadJoin(id);
+	zassert_equal(status, osOK, "osThreadJoin failed with status=%d!", status);
+}
+
+static K_THREAD_STACK_DEFINE(test_stack9, STACKSZ);
+static struct cmsis_rtos_thread_cb test_cb9;
+static const osThreadAttr_t os_thread9_attr = {
+	.name = "Thread9",
+	.attr_bits = osThreadJoinable,
+	.cb_mem = &test_cb9,
+	.cb_size = sizeof(test_cb9),
+	.stack_mem = &test_stack9,
+	.stack_size = STACKSZ,
+	.priority = osPriorityNormal,
+};
+static void thread9(void *argument)
+{
+	osThreadExit();
+}
+ZTEST(cmsis_thread_apis, test_thread_apis_multiple_new_static)
+{
+	osThreadId_t id;
+	osStatus_t status;
+
+	for (int i = 0; i < 100; i++) {
+		id = osThreadNew(thread9, NULL, &os_thread9_attr);
+		zassert_not_null(id,
+				 "Failed to create thread with osThreadNew using static cb/stack");
+
+		status = osThreadJoin(id);
+		zassert_equal(status, osOK, "osThreadJoin failed with status=%d!", status);
+	}
+}
 ZTEST_SUITE(cmsis_thread_apis, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/subsys/portability/cmsis_rtos_v2/src/thread_flags.c b/tests/subsys/portability/cmsis_rtos_v2/src/thread_flags.c
index 8b84cd2e8ea..efa70dd1a71 100644
--- a/tests/subsys/portability/cmsis_rtos_v2/src/thread_flags.c
+++ b/tests/subsys/portability/cmsis_rtos_v2/src/thread_flags.c
@@ -6,17 +6,19 @@
 
 #include <zephyr/ztest.h>
 #include <zephyr/kernel.h>
-#include <cmsis_os2.h>
+#include <zephyr/portability/cmsis_os2.h>
+#include <zephyr/portability/cmsis_types.h>
 
 #include <zephyr/irq_offload.h>
 #include <zephyr/kernel_structs.h>
 
-#define TIMEOUT_TICKS   (10)
-#define FLAG1           (0x00000020)
-#define FLAG2           (0x00000004)
-#define FLAG            (FLAG1 | FLAG2)
-#define ISR_FLAG        (0x50)
-#define STACKSZ         CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE
+#define TIMEOUT_TICKS (1000)
+#define FLAG1         (0x00000020)
+#define FLAG2         (0x00000004)
+#define FLAG3         (0x00000100)
+#define FLAG          (FLAG1 | FLAG2)
+#define ISR_FLAG      (0x50)
+#define STACKSZ       CONFIG_CMSIS_V2_THREAD_MAX_STACK_SIZE
 
 static void thread1(void *arg)
 {
@@ -34,10 +36,13 @@ static void thread1(void *arg)
 	flags = osThreadFlagsGet();
 	zassert_equal(flags & FLAG1, FLAG1, "");
 
+	/* We should be able to get the exact same flags again as they were not cleared */
+	flags = osThreadFlagsWait(FLAG1, osFlagsWaitAny | osFlagsNoClear, 0);
+	zassert_equal(flags & FLAG1, FLAG1, "");
+
 	/* Clear the Flag explicitly */
 	flags = osThreadFlagsClear(FLAG1);
-	zassert_not_equal(flags, osFlagsErrorParameter,
-			  "ThreadFlagsClear failed");
+	zassert_not_equal(flags, osFlagsErrorParameter, "ThreadFlagsClear failed");
 
 	/* wait for FLAG1. It should timeout here as the flag
 	 * though triggered, gets cleared in the previous step.
@@ -51,22 +56,19 @@ static void thread2(void *arg)
 	uint32_t flags;
 
 	flags = osThreadFlagsWait(FLAG, osFlagsWaitAll, TIMEOUT_TICKS);
-	zassert_equal(flags & FLAG, FLAG,
-		      "osThreadFlagsWait failed unexpectedly");
+	zassert_equal(flags & FLAG, FLAG, "osThreadFlagsWait failed unexpectedly");
 
 	/* validate by passing invalid parameters */
 	zassert_equal(osThreadFlagsSet(NULL, 0), osFlagsErrorParameter,
 		      "Invalid Thread Flags ID is unexpectedly working!");
-	zassert_equal(osThreadFlagsSet(osThreadGetId(), 0x80010000),
-		      osFlagsErrorParameter,
+	zassert_equal(osThreadFlagsSet(osThreadGetId(), 0x80010000), osFlagsErrorParameter,
 		      "Thread with MSB set is set unexpectedly");
 
 	zassert_equal(osThreadFlagsClear(0x80010000), osFlagsErrorParameter,
 		      "Thread with MSB set is cleared unexpectedly");
 
 	/* cannot wait for Flag mask with MSB set */
-	zassert_equal(osThreadFlagsWait(0x80010000, osFlagsWaitAny, 0),
-		      osFlagsErrorParameter,
+	zassert_equal(osThreadFlagsWait(0x80010000, osFlagsWaitAny, 0), osFlagsErrorParameter,
 		      "ThreadFlagsWait passed unexpectedly");
 }
 
@@ -134,8 +136,7 @@ static void offload_function(const void *param)
 	zassert_true(k_is_in_isr(), "Not in IRQ context!");
 
 	flags = osThreadFlagsSet((osThreadId_t)param, ISR_FLAG);
-	zassert_equal(flags & ISR_FLAG, ISR_FLAG,
-		      "ThreadFlagsSet failed in ISR");
+	zassert_equal(flags & ISR_FLAG, ISR_FLAG, "ThreadFlagsSet failed in ISR");
 }
 
 void test_thread_flags_from_isr(void *thread_id)
@@ -146,8 +147,7 @@ void test_thread_flags_from_isr(void *thread_id)
 	irq_offload(offload_function, (const void *)osThreadGetId());
 
 	flags = osThreadFlagsWait(ISR_FLAG, osFlagsWaitAll, TIMEOUT_TICKS);
-	zassert_equal((flags & ISR_FLAG),
-		      ISR_FLAG, "unexpected Thread flags value");
+	zassert_equal((flags & ISR_FLAG), ISR_FLAG, "unexpected Thread flags value");
 }
 
 static K_THREAD_STACK_DEFINE(test_stack3, STACKSZ);
@@ -162,10 +162,69 @@ ZTEST(cmsis_thread_flags, test_thread_flags_isr)
 {
 	osThreadId_t id;
 
-	id = osThreadNew(test_thread_flags_from_isr, osThreadGetId(),
-			 &thread3_attr);
+	id = osThreadNew(test_thread_flags_from_isr, osThreadGetId(), &thread3_attr);
 	zassert_true(id != NULL, "Failed creating thread");
 
 	osDelay(TIMEOUT_TICKS);
 }
+
+static K_THREAD_STACK_DEFINE(test_stack4, STACKSZ);
+static struct cmsis_rtos_thread_cb test_cb4;
+static osThreadAttr_t thread4_attr = {
+	.name = "Thread4",
+	.cb_mem = &test_cb4,
+	.cb_size = sizeof(test_cb4),
+	.stack_mem = &test_stack4,
+	.stack_size = STACKSZ,
+	.priority = osPriorityHigh,
+};
+static bool m_thread_4_is_blocked;
+
+static void thread4(void *arg)
+{
+	uint32_t flags;
+
+	/* Nothing will trigger FLAG1 to this thread, so the following should timeout */
+	flags = osThreadFlagsWait(FLAG1, osFlagsWaitAny, 0);
+	zassert_equal(flags, osFlagsErrorTimeout,
+		      "ThreadFlagsWait unexpected found 0x%x flags were set");
+
+	flags = osThreadFlagsWait(FLAG1, osFlagsWaitAll, TIMEOUT_TICKS / 10);
+	zassert_equal(flags, osFlagsErrorTimeout,
+		      "ThreadFlagsWait unexpected found 0x%x flags were set");
+
+	flags = osThreadFlagsWait(FLAG1, osFlagsWaitAny | osFlagsNoClear, 0);
+	zassert_equal(flags, osFlagsErrorTimeout,
+		      "ThreadFlagsWait unexpected found 0x%x flags were set");
+
+	/* Nothing will trigger FLAG1 to this thread, so it should remain blocked here */
+	m_thread_4_is_blocked = true;
+	flags = osThreadFlagsWait(FLAG1, osFlagsWaitAny, osWaitForever);
+	zassert_unreachable();
+}
+
+ZTEST(cmsis_thread_flags, test_thread_flags_set_flags_not_waited_upon)
+{
+	osThreadId_t id;
+	uint32_t flags;
+
+	m_thread_4_is_blocked = false;
+
+	id = osThreadNew(thread4, NULL, &thread4_attr);
+	zassert_true(id != NULL, "Failed creating thread3");
+
+	/* The thread will wait on any of FLAG1. Signal something it is not waiting for. */
+	flags = osThreadFlagsSet(id, FLAG3);
+	zassert_equal(flags & FLAG3, FLAG3, "");
+	osThreadYield();
+
+	/* Wait a bit, but thread4 should remain blocked */
+	osDelay(TIMEOUT_TICKS);
+
+	zassert_true(m_thread_4_is_blocked, "Thread 4 did run till expected point");
+
+	/* Kill the thread */
+	osThreadTerminate(id);
+}
+
 ZTEST_SUITE(cmsis_thread_flags, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/subsys/portability/cmsis_rtos_v2/src/timer.c b/tests/subsys/portability/cmsis_rtos_v2/src/timer.c
index 35ab88ed174..831c76bf32a 100644
--- a/tests/subsys/portability/cmsis_rtos_v2/src/timer.c
+++ b/tests/subsys/portability/cmsis_rtos_v2/src/timer.c
@@ -5,38 +5,32 @@
  */
 
 #include <zephyr/ztest.h>
-#include <cmsis_os2.h>
+#include <zephyr/portability/cmsis_os2.h>
+#include <zephyr/portability/cmsis_types.h>
 
-#define ONESHOT_TIME_TICKS      100
-#define PERIOD_TICKS            MAX(50, k_ms_to_ticks_ceil32(10))
-#define NUM_PERIODS             5
+#define ONESHOT_TIME_TICKS 100
+#define PERIOD_TICKS       MAX(50, k_ms_to_ticks_ceil32(10))
+#define NUM_PERIODS        5
 
 uint32_t num_oneshots_executed;
 uint32_t num_periods_executed;
 
-const osTimerAttr_t timer_attr = {
-	"myTimer",
-	0,
-	NULL,
-	0U
-};
+const osTimerAttr_t timer_attr = {"myTimer", 0, NULL, 0U};
 
-void Timer1_Callback(void *arg)
+static void Timer1_Callback(void *arg)
 {
 	uint32_t Tmr = *(uint32_t *)arg;
 
 	num_oneshots_executed++;
-	TC_PRINT("oneshot_callback (Timer %d) = %d\n",
-		 Tmr, num_oneshots_executed);
+	TC_PRINT("oneshot_callback (Timer %d) = %d\n", Tmr, num_oneshots_executed);
 }
 
-void Timer2_Callback(void *arg)
+static void Timer2_Callback(void *arg)
 {
 	uint32_t Tmr = *(uint32_t *)arg;
 
 	num_periods_executed++;
-	TC_PRINT("periodic_callback (Timer %d) = %d\n",
-		 Tmr, num_periods_executed);
+	TC_PRINT("periodic_callback (Timer %d) = %d\n", Tmr, num_periods_executed);
 }
 
 ZTEST(cmsis_timer, test_timer)
@@ -59,8 +53,7 @@ ZTEST(cmsis_timer, test_timer)
 
 	/* Stop the timer before start */
 	status = osTimerStop(id1);
-	zassert_true(status == osErrorResource,
-		     "error while stopping non-active timer");
+	zassert_true(status == osErrorResource, "error while stopping non-active timer");
 
 	timerDelay = ONESHOT_TIME_TICKS;
 	status = osTimerStart(id1, timerDelay);
@@ -73,8 +66,7 @@ ZTEST(cmsis_timer, test_timer)
 	 * if it fires more than once.
 	 */
 	osDelay(timerDelay * 3U + 10);
-	zassert_true(num_oneshots_executed == 1U,
-		     "error setting up one-shot timer");
+	zassert_true(num_oneshots_executed == 1U, "error setting up one-shot timer");
 
 	status = osTimerStop(id1);
 	zassert_true(status == osOK, "error stopping one-shot timer");
@@ -99,11 +91,31 @@ ZTEST(cmsis_timer, test_timer)
 	 */
 	osDelay(timerDelay * NUM_PERIODS + 10);
 
-	zassert_true(num_periods_executed == NUM_PERIODS,
-		     "error setting up periodic timer");
+	zassert_true(num_periods_executed == NUM_PERIODS, "error setting up periodic timer");
 
 	/* Delete the timer before stop */
 	status = osTimerDelete(id2);
 	zassert_true(status == osOK, "error deleting periodic timer");
 }
+
+static struct cmsis_rtos_timer_cb timer_cb3;
+static const osTimerAttr_t timer_attr3 = {
+	.name = "Timer3",
+	.cb_mem = &timer_cb3,
+	.cb_size = sizeof(timer_cb3),
+};
+static void Timer3_Callback(void *arg)
+{
+	printf("Timer3 callback ran\n");
+}
+ZTEST(cmsis_timer, test_timer_static_allocation)
+{
+	osTimerId_t id;
+	osStatus_t status;
+
+	id = osTimerNew(Timer3_Callback, osTimerOnce, NULL, &timer_attr3);
+	zassert_true(id != NULL, "error creating timer with static cb");
+	status = osTimerDelete(id);
+	zassert_true(status == osOK, "error timer with static cb");
+}
 ZTEST_SUITE(cmsis_timer, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/subsys/rtio/rtio_api/src/test_rtio_api.c b/tests/subsys/rtio/rtio_api/src/test_rtio_api.c
index e03cad45a1d..543fbac479e 100644
--- a/tests/subsys/rtio/rtio_api/src/test_rtio_api.c
+++ b/tests/subsys/rtio/rtio_api/src/test_rtio_api.c
@@ -616,6 +616,40 @@ ZTEST(rtio_api, test_rtio_transaction)
 	}
 }
 
+ZTEST(rtio_api, test_rtio_cqe_count_overflow)
+{
+	/* atomic_t max value as `uintptr_t` */
+	const atomic_t max_uval = UINTPTR_MAX;
+
+	/* atomic_t max value as if it were a signed word `intptr_t` */
+	const atomic_t max_sval = UINTPTR_MAX >> 1;
+
+	TC_PRINT("initializing iodev test devices\n");
+
+	for (int i = 0; i < 2; i++) {
+		rtio_iodev_test_init(iodev_test_transaction[i]);
+	}
+
+	TC_PRINT("rtio transaction CQE overflow\n");
+	atomic_set(&r_transaction.cq_count, max_uval - 3);
+	for (int i = 0; i < TEST_REPEATS; i++) {
+		test_rtio_transaction_(&r_transaction);
+	}
+
+	TC_PRINT("initializing iodev test devices\n");
+
+	for (int i = 0; i < 2; i++) {
+		rtio_iodev_test_init(iodev_test_transaction[i]);
+	}
+
+	TC_PRINT("rtio transaction CQE overflow\n");
+	atomic_set(&r_transaction.cq_count, max_sval - 3);
+	for (int i = 0; i < TEST_REPEATS; i++) {
+		test_rtio_transaction_(&r_transaction);
+	}
+}
+
+
 #define THROUGHPUT_ITERS 100000
 RTIO_DEFINE(r_throughput, SQE_POOL_SIZE, CQE_POOL_SIZE);
 
diff --git a/tests/subsys/secure_storage/psa/crypto/overlay-secure_storage.conf b/tests/subsys/secure_storage/psa/crypto/overlay-secure_storage.conf
index 66d62e83c9c..6df091015be 100644
--- a/tests/subsys/secure_storage/psa/crypto/overlay-secure_storage.conf
+++ b/tests/subsys/secure_storage/psa/crypto/overlay-secure_storage.conf
@@ -13,3 +13,9 @@ CONFIG_MBEDTLS_HEAP_SIZE=1024
 CONFIG_SECURE_STORAGE=y
 # For testing isolation between the different callers of the ITS.
 CONFIG_SECURE_STORAGE_PS_IMPLEMENTATION_ITS=y
+CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_SETTINGS=y
+CONFIG_SETTINGS=y
+CONFIG_SETTINGS_NVS=y
+CONFIG_NVS=y
+CONFIG_FLASH=y
+CONFIG_FLASH_MAP=y
diff --git a/tests/subsys/secure_storage/psa/crypto/testcase.yaml b/tests/subsys/secure_storage/psa/crypto/testcase.yaml
index 1482d23cb6c..8755a5a1935 100644
--- a/tests/subsys/secure_storage/psa/crypto/testcase.yaml
+++ b/tests/subsys/secure_storage/psa/crypto/testcase.yaml
@@ -8,6 +8,7 @@ tests:
     integration_platforms:
       - native_sim
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
   secure_storage.psa.crypto.tfm:
     filter: CONFIG_BUILD_WITH_TFM
     extra_args: EXTRA_CONF_FILE=overlay-tfm.conf
diff --git a/tests/subsys/secure_storage/psa/its/overlay-store_default.conf b/tests/subsys/secure_storage/psa/its/overlay-store_default.conf
deleted file mode 100644
index e6604bc94b0..00000000000
--- a/tests/subsys/secure_storage/psa/its/overlay-store_default.conf
+++ /dev/null
@@ -1,7 +0,0 @@
-CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_SETTINGS=y
-
-# 256 - flags (1) - CONFIG_SECURE_STORAGE_ITS_TRANSFORM_OUTPUT_OVERHEAD (28)
-CONFIG_SECURE_STORAGE_ITS_MAX_DATA_SIZE=227
-
-# Limit the space available for the maximum entry test to not take too long with NVS.
-CONFIG_SETTINGS_NVS_SECTOR_COUNT=2
diff --git a/tests/subsys/secure_storage/psa/its/overlay-store_settings.conf b/tests/subsys/secure_storage/psa/its/overlay-store_settings.conf
new file mode 100644
index 00000000000..b0a2cd493f9
--- /dev/null
+++ b/tests/subsys/secure_storage/psa/its/overlay-store_settings.conf
@@ -0,0 +1,12 @@
+CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_SETTINGS=y
+CONFIG_SETTINGS=y
+CONFIG_SETTINGS_NVS=y
+CONFIG_NVS=y
+CONFIG_FLASH=y
+CONFIG_FLASH_MAP=y
+
+# 256 - flags (1) - CONFIG_SECURE_STORAGE_ITS_TRANSFORM_OUTPUT_OVERHEAD (28)
+CONFIG_SECURE_STORAGE_ITS_MAX_DATA_SIZE=227
+
+# Limit the space available for the maximum entry test to not take too long with NVS.
+CONFIG_SETTINGS_NVS_SECTOR_COUNT=2
diff --git a/tests/subsys/secure_storage/psa/its/overlay-store_zms.conf b/tests/subsys/secure_storage/psa/its/overlay-store_zms.conf
new file mode 100644
index 00000000000..7efe611bc0a
--- /dev/null
+++ b/tests/subsys/secure_storage/psa/its/overlay-store_zms.conf
@@ -0,0 +1,3 @@
+CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_ZMS=y
+CONFIG_ZMS=y
+CONFIG_FLASH=y
diff --git a/tests/subsys/secure_storage/psa/its/testcase.yaml b/tests/subsys/secure_storage/psa/its/testcase.yaml
index d464a82e8e9..74bcec13586 100644
--- a/tests/subsys/secure_storage/psa/its/testcase.yaml
+++ b/tests/subsys/secure_storage/psa/its/testcase.yaml
@@ -2,6 +2,7 @@ common:
   integration_platforms:
     - native_sim
     - nrf54l15dk/nrf54l15/cpuapp
+    - ophelia4ev/nrf54l15/cpuapp
   platform_exclude:
     - qemu_cortex_m0 # settings subsystem initialization fails
   timeout: 600
@@ -23,20 +24,21 @@ tests:
       - nrf9151dk/nrf9151
       - nrf9160dk/nrf9160
       - nrf9161dk/nrf9161
+      - ophelia4ev/nrf54l15/cpuapp
     extra_args:
       - EXTRA_DTC_OVERLAY_FILE=zms.overlay
-      - EXTRA_CONF_FILE=overlay-secure_storage.conf;overlay-transform_default.conf
+      - EXTRA_CONF_FILE=overlay-secure_storage.conf;overlay-store_zms.conf;overlay-transform_default.conf
       - SB_CONFIG_PARTITION_MANAGER=n
 
   secure_storage.psa.its.secure_storage.store.settings:
     filter: CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_SETTINGS
     extra_args: "EXTRA_CONF_FILE=\
-      overlay-secure_storage.conf;overlay-transform_default.conf;overlay-store_default.conf"
+      overlay-secure_storage.conf;overlay-transform_default.conf;overlay-store_settings.conf"
 
   secure_storage.psa.its.secure_storage.custom.transform:
     filter: CONFIG_SECURE_STORAGE and not CONFIG_SECURE_STORAGE_ITS_STORE_IMPLEMENTATION_NONE
     extra_args: "EXTRA_CONF_FILE=\
-      overlay-secure_storage.conf;overlay-transform_custom.conf;overlay-store_default.conf"
+      overlay-secure_storage.conf;overlay-transform_custom.conf;overlay-store_settings.conf"
 
   secure_storage.psa.its.secure_storage.custom.store:
     filter: CONFIG_SECURE_STORAGE
diff --git a/tests/subsys/settings/fcb/testcase.yaml b/tests/subsys/settings/fcb/testcase.yaml
index 64b00e65bec..df484118305 100644
--- a/tests/subsys/settings/fcb/testcase.yaml
+++ b/tests/subsys/settings/fcb/testcase.yaml
@@ -6,6 +6,10 @@ tests:
       - native_sim
       - native_sim/native/64
       - mr_canhubk3
+      - s32z2xxdc2/s32z270/rtu0
+      - s32z2xxdc2/s32z270/rtu1
+      - s32z2xxdc2@D/s32z270/rtu0
+      - s32z2xxdc2@D/s32z270/rtu1
     integration_platforms:
       - nrf52840dk/nrf52840
       - native_sim
diff --git a/tests/subsys/settings/file/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/subsys/settings/file/boards/s32z2xxdc2_s32z270_rtu0.overlay
new file mode 100644
index 00000000000..75fc2ca52f4
--- /dev/null
+++ b/tests/subsys/settings/file/boards/s32z2xxdc2_s32z270_rtu0.overlay
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&s26hs512t {
+	partitions {
+		settings_file_partition: partition@0 {
+			label = "settings_file_partition";
+			reg = <0x00000000 0x00010000>;
+		};
+	};
+};
diff --git a/tests/subsys/settings/file/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/subsys/settings/file/boards/s32z2xxdc2_s32z270_rtu1.overlay
new file mode 100644
index 00000000000..75fc2ca52f4
--- /dev/null
+++ b/tests/subsys/settings/file/boards/s32z2xxdc2_s32z270_rtu1.overlay
@@ -0,0 +1,16 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/delete-node/ &storage_partition;
+
+&s26hs512t {
+	partitions {
+		settings_file_partition: partition@0 {
+			label = "settings_file_partition";
+			reg = <0x00000000 0x00010000>;
+		};
+	};
+};
diff --git a/tests/subsys/settings/file/testcase.yaml b/tests/subsys/settings/file/testcase.yaml
index 9af2b37e0e4..5d4adfab4de 100644
--- a/tests/subsys/settings/file/testcase.yaml
+++ b/tests/subsys/settings/file/testcase.yaml
@@ -8,8 +8,12 @@ tests:
       - native_sim
       - native_sim/native/64
       - mr_canhubk3
+      - s32z2xxdc2/s32z270/rtu0
+      - s32z2xxdc2/s32z270/rtu1
+      - s32z2xxdc2@D/s32z270/rtu0
+      - s32z2xxdc2@D/s32z270/rtu1
     integration_platforms:
-      - nrf52840dk/nrf52840
+      - native_sim
     tags:
       - settings
       - file
diff --git a/tests/subsys/settings/functional/fcb/native_posix.overlay b/tests/subsys/settings/functional/fcb/native_posix.overlay
deleted file mode 100644
index f7f09615138..00000000000
--- a/tests/subsys/settings/functional/fcb/native_posix.overlay
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (c) 2019 Jan Van Winkel <jan.van_winkel@dxplore.eu>
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-/delete-node/ &storage_partition;
-/delete-node/ &scratch_partition;
-
-&flash0 {
-
-	partitions {
-		compatible = "fixed-partitions";
-		#address-cells = <1>;
-		#size-cells = <1>;
-
-		storage_partition: partition@70000 {
-			label = "storage";
-			reg = <0x00070000 0x10000>;
-		};
-	};
-};
diff --git a/tests/subsys/settings/functional/fcb/testcase.yaml b/tests/subsys/settings/functional/fcb/testcase.yaml
index 87b40dabb3f..46ee35f49c4 100644
--- a/tests/subsys/settings/functional/fcb/testcase.yaml
+++ b/tests/subsys/settings/functional/fcb/testcase.yaml
@@ -6,8 +6,12 @@ tests:
       - native_sim
       - native_sim/native/64
       - mr_canhubk3
+      - s32z2xxdc2/s32z270/rtu0
+      - s32z2xxdc2/s32z270/rtu1
+      - s32z2xxdc2@D/s32z270/rtu0
+      - s32z2xxdc2@D/s32z270/rtu1
     integration_platforms:
-      - nrf52840dk/nrf52840
+      - native_sim
     tags:
       - settings
       - fcb
@@ -17,6 +21,10 @@ tests:
       - native_sim
       - native_sim/native/64
       - mr_canhubk3
+      - s32z2xxdc2/s32z270/rtu0
+      - s32z2xxdc2/s32z270/rtu1
+      - s32z2xxdc2@D/s32z270/rtu0
+      - s32z2xxdc2@D/s32z270/rtu1
     integration_platforms:
       - native_sim
     tags:
diff --git a/tests/subsys/settings/functional/file/testcase.yaml b/tests/subsys/settings/functional/file/testcase.yaml
index 00565155e17..3bc1fc347aa 100644
--- a/tests/subsys/settings/functional/file/testcase.yaml
+++ b/tests/subsys/settings/functional/file/testcase.yaml
@@ -6,6 +6,10 @@ tests:
       - native_sim
       - native_sim/native/64
       - mr_canhubk3
+      - s32z2xxdc2/s32z270/rtu0
+      - s32z2xxdc2/s32z270/rtu1
+      - s32z2xxdc2@D/s32z270/rtu0
+      - s32z2xxdc2@D/s32z270/rtu1
     integration_platforms:
       - native_sim
     tags:
diff --git a/tests/subsys/settings/functional/nvs/testcase.yaml b/tests/subsys/settings/functional/nvs/testcase.yaml
index 13c9108ac03..41ed4992b1f 100644
--- a/tests/subsys/settings/functional/nvs/testcase.yaml
+++ b/tests/subsys/settings/functional/nvs/testcase.yaml
@@ -2,16 +2,30 @@ tests:
   settings.functional.nvs:
     platform_allow:
       - qemu_x86
+      - mps2/an385
       - native_sim
       - native_sim/native/64
+      - s32z2xxdc2/s32z270/rtu0
+      - s32z2xxdc2/s32z270/rtu1
+      - s32z2xxdc2@D/s32z270/rtu0
+      - s32z2xxdc2@D/s32z270/rtu1
+    integration_platforms:
+      - mps2/an385
     tags:
       - settings
       - nvs
   settings.functional.nvs.chosen:
     extra_args: DTC_OVERLAY_FILE=./chosen.overlay
     platform_allow:
+      - mps2/an385
       - native_sim
       - native_sim/native/64
+      - s32z2xxdc2/s32z270/rtu0
+      - s32z2xxdc2/s32z270/rtu1
+      - s32z2xxdc2@D/s32z270/rtu0
+      - s32z2xxdc2@D/s32z270/rtu1
+    integration_platforms:
+      - mps2/an385
     tags:
       - settings
       - nvs
@@ -20,8 +34,13 @@ tests:
     platform_allow:
       - nrf52840dk/nrf52840
       - nrf52dk/nrf52832
+      - s32z2xxdc2/s32z270/rtu0
+      - s32z2xxdc2/s32z270/rtu1
+      - s32z2xxdc2@D/s32z270/rtu0
+      - s32z2xxdc2@D/s32z270/rtu1
+      - mps2/an385
     integration_platforms:
-      - nrf52840dk/nrf52840
+      - mps2/an385
     tags:
       - settings
       - nvs
diff --git a/tests/subsys/settings/nvs/testcase.yaml b/tests/subsys/settings/nvs/testcase.yaml
index c78bd712826..b3ff3175ca6 100644
--- a/tests/subsys/settings/nvs/testcase.yaml
+++ b/tests/subsys/settings/nvs/testcase.yaml
@@ -1,6 +1,6 @@
 tests:
   settings.nvs:
-    depends_on: nvs
+    filter: dt_label_with_parent_compat_enabled("storage_partition", "fixed-partitions")
     min_ram: 32
     tags:
       - settings
diff --git a/tests/subsys/settings/performance/testcase.yaml b/tests/subsys/settings/performance/testcase.yaml
index 7ae65c3c556..efbd2115234 100644
--- a/tests/subsys/settings/performance/testcase.yaml
+++ b/tests/subsys/settings/performance/testcase.yaml
@@ -7,6 +7,10 @@ tests:
     platform_allow:
       - nrf52840dk/nrf52840
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
+      - mps2/an385
+    integration_platforms:
+      - mps2/an385
     min_ram: 32
     tags:
       - settings
@@ -23,6 +27,10 @@ tests:
     platform_allow:
       - nrf52840dk/nrf52840
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
+      - mps2/an385
+    integration_platforms:
+      - mps2/an385
     min_ram: 32
     tags:
       - settings
@@ -36,10 +44,8 @@ tests:
       - CONFIG_SETTINGS_ZMS=y
       - CONFIG_ZMS_LOOKUP_CACHE=y
       - CONFIG_ZMS_LOOKUP_CACHE_SIZE=512
-    platform_allow: nrf52840dk/nrf52840
-    platform_exclude:
-      - native_sim
-      - qemu_x86
+    platform_allow:
+      - nrf52840dk/nrf52840
     min_ram: 32
     tags:
       - settings
@@ -56,10 +62,8 @@ tests:
       - CONFIG_NVS_LOOKUP_CACHE_SIZE=512
       - CONFIG_SETTINGS_NVS_NAME_CACHE=y
       - CONFIG_SETTINGS_NVS_NAME_CACHE_SIZE=512
-    platform_allow: nrf52840dk/nrf52840
-    platform_exclude:
-      - native_sim
-      - qemu_x86
+    platform_allow:
+      - nrf52840dk/nrf52840
     min_ram: 32
     tags:
       - settings
diff --git a/tests/subsys/settings/zms/testcase.yaml b/tests/subsys/settings/zms/testcase.yaml
index 2234fd4cd78..2a1b12d1c0e 100644
--- a/tests/subsys/settings/zms/testcase.yaml
+++ b/tests/subsys/settings/zms/testcase.yaml
@@ -1,6 +1,6 @@
 tests:
   settings.zms:
-    depends_on: zms
+    filter: dt_label_with_parent_compat_enabled("storage_partition", "fixed-partitions")
     min_ram: 32
     tags:
       - settings
diff --git a/tests/subsys/shell/shell_backend_uart/testcase.yaml b/tests/subsys/shell/shell_backend_uart/testcase.yaml
index e4a72a1bd6a..64a9323ce4d 100644
--- a/tests/subsys/shell/shell_backend_uart/testcase.yaml
+++ b/tests/subsys/shell/shell_backend_uart/testcase.yaml
@@ -6,7 +6,6 @@ tests:
       - shell
       - backend
       - uart
-    filter: ( CONFIG_SHELL )
     platform_allow:
       - qemu_x86
       - qemu_riscv32
diff --git a/tests/subsys/storage/flash_map/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/subsys/storage/flash_map/boards/s32z2xxdc2_s32z270_rtu0.overlay
new file mode 100644
index 00000000000..9b7b1619bc9
--- /dev/null
+++ b/tests/subsys/storage/flash_map/boards/s32z2xxdc2_s32z270_rtu0.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../app.overlay"
+
+&s26hs512t {
+	partitions {
+		slot1_partition: partition@100000 {
+			reg = <0x100000 0x100000>;
+		};
+	};
+};
diff --git a/tests/subsys/storage/flash_map/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/subsys/storage/flash_map/boards/s32z2xxdc2_s32z270_rtu1.overlay
new file mode 100644
index 00000000000..9b7b1619bc9
--- /dev/null
+++ b/tests/subsys/storage/flash_map/boards/s32z2xxdc2_s32z270_rtu1.overlay
@@ -0,0 +1,15 @@
+/*
+ * Copyright 2024 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "../app.overlay"
+
+&s26hs512t {
+	partitions {
+		slot1_partition: partition@100000 {
+			reg = <0x100000 0x100000>;
+		};
+	};
+};
diff --git a/tests/subsys/storage/flash_map/src/main.c b/tests/subsys/storage/flash_map/src/main.c
index 3e2b9d8421a..d892bfe2892 100644
--- a/tests/subsys/storage/flash_map/src/main.c
+++ b/tests/subsys/storage/flash_map/src/main.c
@@ -16,9 +16,12 @@
 #define SLOT1_PARTITION_DEV	FIXED_PARTITION_DEVICE(SLOT1_PARTITION)
 #define SLOT1_PARTITION_NODE	DT_NODELABEL(SLOT1_PARTITION)
 #define SLOT1_PARTITION_OFFSET	FIXED_PARTITION_OFFSET(SLOT1_PARTITION)
+#define SLOT1_PARTITION_SIZE	FIXED_PARTITION_SIZE(SLOT1_PARTITION)
+
+#define FLASH_AREA_COPY_SIZE	MIN((SLOT1_PARTITION_SIZE / 2), 128)
 
 extern int flash_map_entries;
-struct flash_sector fs_sectors[1024];
+struct flash_sector fs_sectors[2048];
 
 ZTEST(flash_map, test_flash_area_disabled_device)
 {
@@ -223,4 +226,34 @@ ZTEST(flash_map, test_flash_area_erase_and_flatten)
 		     i + fa->fa_off);
 }
 
+ZTEST(flash_map, test_flash_area_copy)
+{
+	const struct flash_area *fa;
+	uint8_t src_buf[FLASH_AREA_COPY_SIZE], dst_buf[FLASH_AREA_COPY_SIZE],
+		copy_buf[32];
+	int rc;
+
+	/* Get source and destination flash areas */
+	fa = FIXED_PARTITION(SLOT1_PARTITION);
+
+	/* First erase the area so it's ready for use. */
+	rc = flash_area_erase(fa, 0, fa->fa_size);
+	zassert_true(rc == 0, "flash area erase fail");
+
+	/* Fill source area with test data */
+	memset(src_buf, 0xAB, sizeof(src_buf));
+	rc = flash_area_write(fa, 0, src_buf, sizeof(src_buf));
+	zassert_true(rc == 0, "Failed to write to source flash area");
+
+	/* Perform the copy operation */
+	rc = flash_area_copy(fa, 0, fa, FLASH_AREA_COPY_SIZE, sizeof(src_buf), copy_buf,
+			     sizeof(copy_buf));
+	zassert_true(rc == 0, "flash_area_copy failed");
+
+	/* Verify the copied data */
+	rc = flash_area_read(fa, FLASH_AREA_COPY_SIZE, dst_buf, sizeof(dst_buf));
+	zassert_true(rc == 0, "Failed to read from destination flash area");
+	zassert_mem_equal(src_buf, dst_buf, sizeof(src_buf), "Data mismatch after copy");
+}
+
 ZTEST_SUITE(flash_map, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/subsys/storage/flash_map/testcase.yaml b/tests/subsys/storage/flash_map/testcase.yaml
index c1b65b0fdf9..fd381e6034a 100644
--- a/tests/subsys/storage/flash_map/testcase.yaml
+++ b/tests/subsys/storage/flash_map/testcase.yaml
@@ -7,6 +7,10 @@ tests:
       - native_sim
       - native_sim/native/64
       - mr_canhubk3
+      - s32z2xxdc2/s32z270/rtu0
+      - s32z2xxdc2/s32z270/rtu1
+      - s32z2xxdc2@D/s32z270/rtu0
+      - s32z2xxdc2@D/s32z270/rtu1
     tags: flash_map
     integration_platforms:
       - native_sim
@@ -30,6 +34,10 @@ tests:
       - native_sim
       - native_sim/native/64
       - mr_canhubk3
+      - s32z2xxdc2/s32z270/rtu0
+      - s32z2xxdc2/s32z270/rtu1
+      - s32z2xxdc2@D/s32z270/rtu0
+      - s32z2xxdc2@D/s32z270/rtu1
     tags: flash_map
     integration_platforms:
       - native_sim
@@ -40,6 +48,10 @@ tests:
       - native_sim
       - native_sim/native/64
       - mr_canhubk3
+      - s32z2xxdc2/s32z270/rtu0
+      - s32z2xxdc2/s32z270/rtu1
+      - s32z2xxdc2@D/s32z270/rtu0
+      - s32z2xxdc2@D/s32z270/rtu1
     tags: flash_map
     integration_platforms:
       - native_sim
diff --git a/tests/subsys/storage/stream/stream_flash/src/main.c b/tests/subsys/storage/stream/stream_flash/src/main.c
index 88d2c7788ec..2abb10f20e4 100644
--- a/tests/subsys/storage/stream/stream_flash/src/main.c
+++ b/tests/subsys/storage/stream/stream_flash/src/main.c
@@ -424,80 +424,6 @@ ZTEST(lib_stream_flash, test_stream_flash_buffered_write_whole_page)
 	/* Second page should not be erased */
 	VERIFY_WRITTEN(page_size, page_size);
 }
-
-/* Erase that never completes successfully */
-static int bad_erase(const struct device *dev, off_t offset, size_t size)
-{
-	return -EINVAL;
-}
-
-ZTEST(lib_stream_flash, test_stream_flash_erase_page)
-{
-	int rc;
-
-	init_target();
-
-	/* Write something to make page dirty */
-	rc = flash_write(ctx.fdev, FLASH_BASE, write_buf, BUF_LEN);
-	zassert_equal(rc, 0, "expected success");
-
-	rc = stream_flash_erase_page(&ctx, FLASH_BASE);
-	zassert_equal(rc, 0, "expected success");
-
-	VERIFY_ERASED(0, page_size);
-
-	/*
-	 * Test failure in erase does not change context.
-	 * The test is done by replacing erase function of device API with fake
-	 * one that returns with an error, invoking the erase procedure
-	 * and than comparing state of context prior to call to the one after.
-	 */
-	struct device fake_dev = *ctx.fdev;
-	struct flash_driver_api fake_api = *(struct flash_driver_api *)ctx.fdev->api;
-	struct stream_flash_ctx bad_ctx = ctx;
-	struct stream_flash_ctx cmp_ctx;
-
-	fake_api.erase = bad_erase;
-	fake_dev.api = &fake_api;
-	bad_ctx.fdev = &fake_dev;
-	/* Triger erase attempt */
-	bad_ctx.last_erased_page_start_offset = FLASH_BASE - 16;
-	cmp_ctx = bad_ctx;
-
-	rc = stream_flash_erase_page(&bad_ctx, FLASH_BASE);
-	zassert_equal(memcmp(&bad_ctx, &cmp_ctx, sizeof(bad_ctx)), 0,
-		      "Ctx should not get altered");
-	zassert_equal(rc, -EINVAL, "Expected failure");
-
-	/* False dev with erase set to NULL to avoid actual erase */
-	fake_api.erase = NULL;
-	struct stream_flash_ctx range_test_ctx = {
-		.offset = 1024,
-		.available = 2048,
-		.fdev = &fake_dev,
-		.last_erased_page_start_offset = -1,
-	};
-
-	rc = stream_flash_erase_page(&range_test_ctx, 1024);
-	zassert_equal(rc, -ENOSYS, "%d No device attached - expected failure", rc);
-
-	rc = stream_flash_erase_page(&range_test_ctx, 1023);
-	zassert_equal(rc, -ERANGE, "Expected failure - offset before designated area");
-
-	rc = stream_flash_erase_page(&range_test_ctx,
-				     range_test_ctx.offset + range_test_ctx.available + 1);
-	zassert_equal(rc, -ERANGE, "Expected failure - offset after designated area");
-}
-#else
-ZTEST(lib_stream_flash, test_stream_flash_erase_page)
-{
-	ztest_test_skip();
-}
-
-ZTEST(lib_stream_flash, test_stream_flash_buffered_write_whole_page)
-{
-	ztest_test_skip();
-}
 #endif
 
 static size_t write_and_save_progress(size_t bytes, const char *save_key)
@@ -580,8 +506,7 @@ ZTEST(lib_stream_flash, test_stream_flash_progress_resume)
 	size_t bytes_written_old;
 	size_t bytes_written;
 #ifdef CONFIG_STREAM_FLASH_ERASE
-	off_t erase_offset_old;
-	off_t erase_offset;
+	size_t erased_up_to_old;
 #endif
 
 	clear_all_progress();
@@ -589,7 +514,7 @@ ZTEST(lib_stream_flash, test_stream_flash_progress_resume)
 
 	bytes_written_old = stream_flash_bytes_written(&ctx);
 #ifdef CONFIG_STREAM_FLASH_ERASE
-	erase_offset_old = ctx.last_erased_page_start_offset;
+	erased_up_to_old = ctx.erased_up_to;
 #endif
 
 	/* Test load with zero bytes_written */
@@ -603,8 +528,7 @@ ZTEST(lib_stream_flash, test_stream_flash_progress_resume)
 	zassert_equal(bytes_written, bytes_written_old,
 		      "expected bytes_written to be unchanged");
 #ifdef CONFIG_STREAM_FLASH_ERASE
-	erase_offset = ctx.last_erased_page_start_offset;
-	zassert_equal(erase_offset, erase_offset_old,
+	zassert_equal(ctx.erased_up_to, erased_up_to_old,
 		      "expected erase offset to be unchanged");
 #endif
 
@@ -615,8 +539,8 @@ ZTEST(lib_stream_flash, test_stream_flash_progress_resume)
 	bytes_written_old = write_and_save_progress(page_size * 2,
 						    progress_key);
 #ifdef CONFIG_STREAM_FLASH_ERASE
-	erase_offset_old = ctx.last_erased_page_start_offset;
-	zassert_true(erase_offset_old != 0, "expected pages to be erased");
+	zassert_false(ctx.erased_up_to == 0, "expected pages to be erased");
+	erased_up_to_old = ctx.erased_up_to;
 #endif
 
 	init_target();
@@ -626,7 +550,7 @@ ZTEST(lib_stream_flash, test_stream_flash_progress_resume)
 	zassert_equal(bytes_written, bytes_written_old,
 		      "expected bytes_written to be loaded");
 #if defined(CONFIG_STREAM_FLASH_ERASE)
-	zassert_equal(erase_offset_old, ctx.last_erased_page_start_offset,
+	zassert_equal(erased_up_to_old, ctx.erased_up_to,
 		      "expected last erased page offset to be loaded");
 #endif
 
@@ -647,7 +571,6 @@ ZTEST(lib_stream_flash, test_stream_flash_progress_clear)
 	size_t bytes_written;
 #ifdef CONFIG_STREAM_FLASH_ERASE
 	off_t erase_offset_old;
-	off_t erase_offset;
 #endif
 
 	clear_all_progress();
@@ -663,7 +586,7 @@ ZTEST(lib_stream_flash, test_stream_flash_progress_clear)
 
 	bytes_written_old = stream_flash_bytes_written(&ctx);
 #ifdef CONFIG_STREAM_FLASH_ERASE
-	erase_offset_old = ctx.last_erased_page_start_offset;
+	erase_offset_old = ctx.erased_up_to;
 #endif
 
 	rc = stream_flash_progress_load(&ctx, progress_key);
@@ -674,8 +597,7 @@ ZTEST(lib_stream_flash, test_stream_flash_progress_clear)
 		      "expected bytes_written to be unchanged");
 
 #ifdef CONFIG_STREAM_FLASH_ERASE
-	erase_offset = ctx.last_erased_page_start_offset;
-	zassert_equal(erase_offset, erase_offset_old,
+	zassert_equal(ctx.erased_up_to, erase_offset_old,
 		      "expected erase offset to be unchanged");
 #endif
 }
diff --git a/tests/subsys/storage/stream/stream_flash/testcase.yaml b/tests/subsys/storage/stream/stream_flash/testcase.yaml
index 7d9990462f9..3dc0a660f2f 100644
--- a/tests/subsys/storage/stream/stream_flash/testcase.yaml
+++ b/tests/subsys/storage/stream/stream_flash/testcase.yaml
@@ -24,11 +24,13 @@ tests:
     platform_allow:
       - nrf54l09pdk/nrf54l09/cpuapp
       - nrf54l15dk/nrf54l15/cpuapp
+      - ophelia4ev/nrf54l15/cpuapp
     extra_configs:
       # Tests, currently, can only support single device testing
       # and platform enabling SPI NOR automatically brings in a device with
       # explicit erase requirement.
       - CONFIG_SPI_NOR=n
+    tags: stream_flash
   storage.stream_flash.dword_wbs:
     extra_args: DTC_OVERLAY_FILE=unaligned_flush.overlay
     tags: stream_flash
diff --git a/tests/subsys/tracing/tracing_api/prj.conf b/tests/subsys/tracing/tracing_api/prj.conf
index af5be66675f..099348043ca 100644
--- a/tests/subsys/tracing/tracing_api/prj.conf
+++ b/tests/subsys/tracing/tracing_api/prj.conf
@@ -3,3 +3,4 @@ CONFIG_TRACING=y
 CONFIG_TRACING_TEST=y
 CONFIG_TRACING_BACKEND_UART=y
 CONFIG_IDLE_STACK_SIZE=4096
+CONFIG_TRACING_BUFFER_SIZE=4096
diff --git a/tests/subsys/tracing/tracing_api/src/main.c b/tests/subsys/tracing/tracing_api/src/main.c
index fe976265e0f..89f1478f633 100644
--- a/tests/subsys/tracing/tracing_api/src/main.c
+++ b/tests/subsys/tracing/tracing_api/src/main.c
@@ -67,8 +67,15 @@ static void tracing_backends_output(
 	/* Check the output data. */
 #ifdef CONFIG_TRACING_ASYNC
 	if (async_tracing_api) {
-		/* Define static 'i' is for guaranteeing all strings of 0 ~ end
-		 * of the array string_tracked are tested.
+		/* This verification should run only once, hence the static
+		 * `i`. As soon as the tracing thread has a chance to run,
+		 * right at the sleep at the async version of
+		 * test_tracing_sys_api, it should have everything needed
+		 * for this check on its buffer, which is sent here.
+		 * Should SMP be ever enabled for this test, this logic
+		 * will break down and one will need some sort of internal
+		 * buffer to keep track of the tracing strings (or do the
+		 * verification in some other way).
 		 */
 		static int i;
 
@@ -184,8 +191,8 @@ ZTEST(tracing_api, test_tracing_sys_api)
 
 	/* wait for some actions finished */
 	k_sleep(K_MSEC(100));
-	zassert_true(tracing_api_found, "Failded to check output from backend");
-	zassert_true(tracing_api_not_found == false, "Failded to check output from backend");
+	zassert_true(tracing_api_found, "Failed to check output from backend");
+	zassert_true(tracing_api_not_found == false, "Failed to check output from backend");
 	async_tracing_api = false;
 }
 #else
diff --git a/tests/subsys/usb/bos/src/test_bos.c b/tests/subsys/usb/bos/src/test_bos.c
index e9452d86fc3..77bcbbd14c3 100644
--- a/tests/subsys/usb/bos/src/test_bos.c
+++ b/tests/subsys/usb/bos/src/test_bos.c
@@ -21,10 +21,6 @@ LOG_MODULE_REGISTER(test_main, LOG_LEVEL_DBG);
  * Compare old style USB BOS definition with section aligned
  */
 
-static const uint8_t dummy_descriptor[] = {
-	0x00, 0x01, 0x02
-};
-
 static struct webusb_bos_desc {
 	struct usb_bos_descriptor bos;
 	struct usb_bos_platform_descriptor platform_webusb;
@@ -91,8 +87,8 @@ static struct webusb_bos_desc {
 	.capability_data_msos = {
 		/* Windows version (8.1) (0x06030000) */
 		.dwWindowsVersion = sys_cpu_to_le32(0x06030000),
-		.wMSOSDescriptorSetTotalLength =
-			sys_cpu_to_le16(sizeof(dummy_descriptor)),
+		/* The MSOS2.0 descriptor is not relevant here. */
+		.wMSOSDescriptorSetTotalLength = 0,
 		.bMS_VendorCode = 0x02,
 		.bAltEnumCode = 0x00
 	}
@@ -160,8 +156,8 @@ USB_DEVICE_BOS_DESC_DEFINE_CAP struct usb_bos_msosv2 {
 	.cap = {
 		/* Windows version (8.1) (0x06030000) */
 		.dwWindowsVersion = sys_cpu_to_le32(0x06030000),
-		.wMSOSDescriptorSetTotalLength =
-			sys_cpu_to_le16(sizeof(dummy_descriptor)),
+		/* The MSOS2.0 descriptor is not relevant here. */
+		.wMSOSDescriptorSetTotalLength = 0,
 		.bMS_VendorCode = 0x02,
 		.bAltEnumCode = 0x00,
 	},
diff --git a/tests/subsys/usb/device_next/boards/native_sim.conf b/tests/subsys/usb/device_next/boards/native_sim.conf
new file mode 100644
index 00000000000..68e22b2de6a
--- /dev/null
+++ b/tests/subsys/usb/device_next/boards/native_sim.conf
@@ -0,0 +1 @@
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000000
diff --git a/tests/subsys/usb/device_next/src/main.c b/tests/subsys/usb/device_next/src/main.c
index a0fcb0e8396..0534a56141f 100644
--- a/tests/subsys/usb/device_next/src/main.c
+++ b/tests/subsys/usb/device_next/src/main.c
@@ -45,7 +45,13 @@ ZTEST(device_next, test_get_configuration)
 	int err;
 
 	udev = usbh_device_get_any(&uhs_ctx);
+	zassert_not_null(udev, "No USB device available");
+
+	err = k_mutex_lock(&udev->mutex, K_MSEC(200));
+	zassert_equal(err, 0, "Failed to lock device");
+
 	err = usbh_req_get_cfg(udev, &cfg);
+	k_mutex_unlock(&udev->mutex);
 
 	switch (udev->state) {
 	case USB_STATE_DEFAULT:
@@ -74,8 +80,14 @@ ZTEST(device_next, test_set_interface)
 	int err;
 
 	udev = usbh_device_get_any(&uhs_ctx);
+	zassert_not_null(udev, "No USB device available");
+
+	err = k_mutex_lock(&udev->mutex, K_MSEC(200));
+	zassert_equal(err, 0, "Failed to lock device");
+
 	err = usbh_req_set_alt(udev, TEST_DEFAULT_INTERFACE,
 			       TEST_DEFAULT_ALTERNATE);
+	k_mutex_unlock(&udev->mutex);
 
 	switch (udev->state) {
 	case USB_STATE_DEFAULT:
@@ -93,7 +105,6 @@ ZTEST(device_next, test_set_interface)
 
 static void *usb_test_enable(void)
 {
-	struct usb_device *udev;
 	int err;
 
 	err = usbh_init(&uhs_ctx);
@@ -125,7 +136,8 @@ static void *usb_test_enable(void)
 	err = usbd_add_descriptor(&test_usbd, &test_sn);
 	zassert_equal(err, 0, "Failed to initialize descriptor (%d)", err);
 
-	if (usbd_caps_speed(&test_usbd) == USBD_SPEED_HS) {
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_caps_speed(&test_usbd) == USBD_SPEED_HS) {
 		err = usbd_add_configuration(&test_usbd, USBD_SPEED_HS, &test_hs_config);
 		zassert_equal(err, 0, "Failed to add configuration (%d)");
 	}
@@ -133,8 +145,9 @@ static void *usb_test_enable(void)
 	err = usbd_add_configuration(&test_usbd, USBD_SPEED_FS, &test_fs_config);
 	zassert_equal(err, 0, "Failed to add configuration (%d)");
 
-	if (usbd_caps_speed(&test_usbd) == USBD_SPEED_HS) {
-		err = usbd_register_all_classes(&test_usbd, USBD_SPEED_HS, 1);
+	if (USBD_SUPPORTS_HIGH_SPEED &&
+	    usbd_caps_speed(&test_usbd) == USBD_SPEED_HS) {
+		err = usbd_register_all_classes(&test_usbd, USBD_SPEED_HS, 1, NULL);
 		zassert_equal(err, 0, "Failed to unregister all instances(%d)");
 
 		err = usbd_unregister_all_classes(&test_usbd, USBD_SPEED_HS, 1);
@@ -144,7 +157,7 @@ static void *usb_test_enable(void)
 		zassert_equal(err, 0, "Failed to register loopback_0 class (%d)");
 	}
 
-	err = usbd_register_all_classes(&test_usbd, USBD_SPEED_FS, 1);
+	err = usbd_register_all_classes(&test_usbd, USBD_SPEED_FS, 1, NULL);
 	zassert_equal(err, 0, "Failed to unregister all instances(%d)");
 
 	err = usbd_unregister_all_classes(&test_usbd, USBD_SPEED_FS, 1);
@@ -160,8 +173,9 @@ static void *usb_test_enable(void)
 	zassert_equal(err, 0, "Failed to enable device support");
 
 	LOG_INF("Device support enabled");
-	udev = usbh_device_get_any(&uhs_ctx);
-	udev->state = USB_STATE_DEFAULT;
+
+	/* Allow the host time to reset the device. */
+	k_msleep(200);
 
 	return NULL;
 }
diff --git a/tests/subsys/zbus/hlp_priority_boost/src/main.c b/tests/subsys/zbus/hlp_priority_boost/src/main.c
index b7391b43512..dd5e6a863c1 100644
--- a/tests/subsys/zbus/hlp_priority_boost/src/main.c
+++ b/tests/subsys/zbus/hlp_priority_boost/src/main.c
@@ -177,4 +177,5 @@ ZTEST(hlp_priority_boost, test_priority_elevation)
 	zassert_true(prio == 8, "The priority must be 8, but it is %d", prio);
 }
 
-ZTEST_SUITE(hlp_priority_boost, NULL, NULL, NULL, NULL, NULL);
+ZTEST_SUITE(hlp_priority_boost, NULL, NULL,
+	    ztest_simple_1cpu_before, ztest_simple_1cpu_after, NULL);
diff --git a/tests/subsys/zbus/runtime_observers_registration/src/main.c b/tests/subsys/zbus/runtime_observers_registration/src/main.c
index e5aee7c4c00..b72586aff27 100644
--- a/tests/subsys/zbus/runtime_observers_registration/src/main.c
+++ b/tests/subsys/zbus/runtime_observers_registration/src/main.c
@@ -69,15 +69,16 @@ ZTEST(basic, test_specification_based__zbus_obs_add_rm_obs)
 {
 	count_callback1 = 0;
 	struct sensor_data_msg sd = {.a = 10, .b = 100};
+	static struct zbus_observer_node n1, n2, n3, n4, n5, n6;
 
 	/* Tyring to add same static observer as one dynamic */
-	zassert_equal(-EEXIST, zbus_chan_add_obs(&chan2, &lis2, K_MSEC(200)), NULL);
+	zassert_equal(-EEXIST, zbus_chan_add_obs(&chan2, &lis2, &n2, K_MSEC(200)), NULL);
 
 	zassert_equal(0, zbus_chan_pub(&chan1, &sd, K_MSEC(500)), NULL);
 	zassert_equal(count_callback1, 0, "The counter could not be more than zero, no obs");
 
-	zassert_equal(0, zbus_chan_add_obs(&chan1, &lis1, K_MSEC(200)), NULL);
-	zassert_equal(-EALREADY, zbus_chan_add_obs(&chan1, &lis1, K_MSEC(200)),
+	zassert_equal(0, zbus_chan_add_obs(&chan1, &lis1, &n1, K_MSEC(200)), NULL);
+	zassert_equal(-EALREADY, zbus_chan_add_obs(&chan1, &lis1, &n1, K_MSEC(200)),
 		      "It cannot be added twice");
 
 	zassert_equal(0, zbus_chan_pub(&chan1, &sd, K_MSEC(500)), NULL);
@@ -98,30 +99,21 @@ ZTEST(basic, test_specification_based__zbus_obs_add_rm_obs)
 	zassert_equal(0, zbus_chan_pub(&chan2, &sd, K_MSEC(500)), NULL);
 	zassert_equal(count_callback2, 1, "The counter could not be more than zero, no obs");
 
-	zassert_equal(0, zbus_chan_add_obs(&chan2, &lis3, K_MSEC(200)), NULL);
+	zassert_equal(0, zbus_chan_add_obs(&chan2, &lis3, &n3, K_MSEC(200)), NULL);
 
-	zassert_equal(-EALREADY, zbus_chan_add_obs(&chan2, &lis3, K_MSEC(200)),
+	zassert_equal(-EALREADY, zbus_chan_add_obs(&chan2, &lis3, &n3, K_MSEC(200)),
 		      "It cannot be added twice");
 
 	zassert_equal(0, zbus_chan_pub(&chan2, &sd, K_MSEC(500)), NULL);
 	zassert_equal(count_callback2, 3, "The counter could not be more than zero, no obs, %d",
 		      count_callback2);
 	count_callback2 = 0;
-	zassert_equal(0, zbus_chan_add_obs(&chan2, &sub1, K_MSEC(200)), NULL);
-	zassert_equal(0, zbus_chan_add_obs(&chan2, &sub2, K_MSEC(200)), NULL);
-	zassert_equal(0, zbus_chan_add_obs(&chan2, &lis4, K_MSEC(200)), "It must add the obs");
-	zassert_equal(0, zbus_chan_add_obs(&chan2, &lis5, K_MSEC(200)), "It must add the obs");
-	zassert_equal(0, zbus_chan_add_obs(&chan2, &lis6, K_MSEC(200)), "It must add the obs");
+	zassert_equal(0, zbus_chan_add_obs(&chan2, &sub1, &n1, K_MSEC(200)), NULL);
+	zassert_equal(0, zbus_chan_add_obs(&chan2, &sub2, &n2, K_MSEC(200)), NULL);
+	zassert_equal(0, zbus_chan_add_obs(&chan2, &lis4, &n4, K_MSEC(200)), "It must add the obs");
+	zassert_equal(0, zbus_chan_add_obs(&chan2, &lis5, &n5, K_MSEC(200)), "It must add the obs");
+	zassert_equal(0, zbus_chan_add_obs(&chan2, &lis6, &n6, K_MSEC(200)), "It must add the obs");
 
-	/* Make the heap full */
-	void *mem;
-
-	do {
-		mem = k_malloc(1);
-	} while (mem != NULL);
-
-	/* With the heap full it will not be possible to add another obs */
-	zassert_equal(-ENOMEM, zbus_chan_add_obs(&chan2, &lis7, K_MSEC(200)), NULL);
 	zassert_equal(0, zbus_chan_pub(&chan2, &sd, K_MSEC(500)), NULL);
 	zassert_equal(count_callback2, 5, NULL);
 
@@ -142,7 +134,9 @@ static struct aux2_wq_data wq_handler;
 
 static void wq_dh_cb(struct k_work *item)
 {
-	zassert_equal(-EAGAIN, zbus_chan_add_obs(&chan2, &sub1, K_MSEC(200)), NULL);
+	static struct zbus_observer_node node;
+
+	zassert_equal(-EAGAIN, zbus_chan_add_obs(&chan2, &sub1, &node, K_MSEC(200)), NULL);
 	zassert_equal(-EAGAIN, zbus_chan_rm_obs(&chan2, &sub2, K_MSEC(200)), NULL);
 }
 
@@ -192,11 +186,12 @@ ZBUS_CHAN_ADD_OBS(chan4, prio_lis4, 2);
 ZTEST(basic, test_specification_based__zbus_obs_priority)
 {
 	struct sensor_data_msg sd = {.a = 70, .b = 116};
+	static struct zbus_observer_node n1, n2;
 
 	execution_sequence_idx = 0;
 
-	zassert_equal(0, zbus_chan_add_obs(&chan4, &prio_lis2, K_MSEC(200)), NULL);
-	zassert_equal(0, zbus_chan_add_obs(&chan4, &prio_lis1, K_MSEC(200)), NULL);
+	zassert_equal(0, zbus_chan_add_obs(&chan4, &prio_lis2, &n1, K_MSEC(200)), NULL);
+	zassert_equal(0, zbus_chan_add_obs(&chan4, &prio_lis1, &n2, K_MSEC(200)), NULL);
 
 	zassert_equal(0, zbus_chan_pub(&chan4, &sd, K_MSEC(500)), NULL);
 
diff --git a/tests/subsys/zbus/unittests/src/main.c b/tests/subsys/zbus/unittests/src/main.c
index 69659d6b825..a40a70082f1 100644
--- a/tests/subsys/zbus/unittests/src/main.c
+++ b/tests/subsys/zbus/unittests/src/main.c
@@ -137,6 +137,7 @@ static struct action_msg ga;
 
 static void isr_handler(const void *operation)
 {
+	static struct zbus_observer_node fast_node, aux_node;
 	enum operation *op = (enum operation *)operation;
 
 	switch (*op) {
@@ -156,7 +157,7 @@ static void isr_handler(const void *operation)
 		isr_return = zbus_chan_finish(NULL);
 		break;
 	case ADD_OBS_ISR_INVAL:
-		isr_return = zbus_chan_add_obs(&aux2_chan, &fast_lis, K_MSEC(200));
+		isr_return = zbus_chan_add_obs(&aux2_chan, &fast_lis, &fast_node, K_MSEC(200));
 		break;
 	case RM_OBS_ISR_INVAL:
 		isr_return = zbus_chan_rm_obs(&aux2_chan, &fast_lis, K_MSEC(200));
@@ -177,7 +178,7 @@ static void isr_handler(const void *operation)
 		isr_return = zbus_chan_finish(&aux2_chan);
 		break;
 	case ADD_OBS_ISR:
-		isr_return = zbus_chan_add_obs(&aux2_chan, NULL, K_MSEC(200));
+		isr_return = zbus_chan_add_obs(&aux2_chan, NULL, &aux_node, K_MSEC(200));
 		break;
 	case RM_OBS_ISR:
 		isr_return = zbus_chan_rm_obs(&aux2_chan, NULL, K_MSEC(200));
@@ -244,6 +245,7 @@ const STRUCT_SECTION_ITERABLE(zbus_observer, invalid_obs) = {
 
 ZTEST(basic, test_specification_based__zbus_chan)
 {
+	static struct zbus_observer_node node;
 	struct action_msg a = {0};
 
 	/* Trying invalid parameters */
@@ -269,9 +271,11 @@ ZTEST(basic, test_specification_based__zbus_chan)
 
 	zassert_equal(-EFAULT, zbus_chan_finish(NULL), "It must be -EFAULT");
 
-	zassert_equal(-EFAULT, zbus_chan_add_obs(NULL, &sub1, K_MSEC(200)), NULL);
+	zassert_equal(-EFAULT, zbus_chan_add_obs(NULL, &sub1, &node, K_MSEC(200)), NULL);
 
-	zassert_equal(-EFAULT, zbus_chan_add_obs(&aux2_chan, NULL, K_MSEC(200)), NULL);
+	zassert_equal(-EFAULT, zbus_chan_add_obs(&aux2_chan, NULL, &node, K_MSEC(200)), NULL);
+
+	zassert_equal(-EFAULT, zbus_chan_add_obs(&aux2_chan, &sub1, NULL, K_MSEC(200)), NULL);
 
 	zassert_equal(-EFAULT, zbus_chan_rm_obs(NULL, &sub1, K_MSEC(200)), NULL);
 
@@ -326,7 +330,7 @@ ZTEST(basic, test_specification_based__zbus_chan)
 
 	k_msleep(100);
 
-	zassert_equal(0, zbus_chan_add_obs(&stuck_chan, &sub1, K_MSEC(200)), NULL);
+	zassert_equal(0, zbus_chan_add_obs(&stuck_chan, &sub1, &node, K_MSEC(200)), NULL);
 
 	zassert_equal(0, zbus_chan_notify(&stuck_chan, K_MSEC(200)), "It must finish correctly");
 
@@ -336,14 +340,14 @@ ZTEST(basic, test_specification_based__zbus_chan)
 
 	/* Trying to call the zbus functions in a ISR context. None must work */
 	ISR_OP(PUB_ISR, 0);
-	ISR_OP(PUB_ISR_INVAL, 0);
+	ISR_OP(PUB_ISR_INVAL, -EFAULT);
 	ISR_OP(READ_ISR, 0);
-	ISR_OP(READ_ISR_INVAL, 0);
+	ISR_OP(READ_ISR_INVAL, -EFAULT);
 	ISR_OP(NOTIFY_ISR, 0);
-	ISR_OP(NOTIFY_ISR_INVAL, 0);
+	ISR_OP(NOTIFY_ISR_INVAL, -EFAULT);
 	ISR_OP(CLAIM_ISR, 0);
 	ISR_OP(FINISH_ISR, 0);
-	ISR_OP(CLAIM_ISR_INVAL, 0);
+	ISR_OP(CLAIM_ISR_INVAL, -EFAULT);
 	ISR_OP(FINISH_ISR, 0);
 	ISR_OP(FINISH_ISR_INVAL, -EFAULT);
 	ISR_OP(ADD_OBS_ISR, -EFAULT);
@@ -599,6 +603,7 @@ ZTEST(basic, test_hard_channel)
 
 ZTEST(basic, test_specification_based__zbus_obs_set_enable)
 {
+	struct zbus_observer_node node;
 	bool enable;
 
 	count_fast = 0;
@@ -617,7 +622,7 @@ ZTEST(basic, test_specification_based__zbus_obs_set_enable)
 	zbus_obs_is_enabled(&rt_fast_lis, &enable);
 	zassert_equal(false, enable);
 
-	zassert_equal(0, zbus_chan_add_obs(&aux1_chan, &rt_fast_lis, K_MSEC(200)), NULL);
+	zassert_equal(0, zbus_chan_add_obs(&aux1_chan, &rt_fast_lis, &node, K_MSEC(200)), NULL);
 
 	zassert_equal(0, zbus_obs_set_enable(&fast_lis, false),
 		      "Must be zero. The observer must be disabled");
diff --git a/tests/test_config_ci.yaml b/tests/test_config_ci.yaml
new file mode 100644
index 00000000000..5f09c5bb08d
--- /dev/null
+++ b/tests/test_config_ci.yaml
@@ -0,0 +1,25 @@
+options:
+  integration_mode:
+    - sample.
+platforms:
+  override_default_platforms: false
+  increased_platform_scope: true
+levels:
+  - name: smoke
+    description: >
+      A plan to be used verifying basic zephyr features on hardware.
+    adds:
+      - kernel.threads.*
+      - kernel.timer.behavior
+      - arch.interrupt
+      - boards.*
+      - drivers.gpio.1pin
+      - drivers.console.uart
+      - drivers.entropy
+  - name: acceptance
+    description: >
+      More coverage
+    inherits:
+      - smoke
+    adds:
+      - kernel.*
diff --git a/tests/tests.dox b/tests/tests.dox
new file mode 100644
index 00000000000..3f525c9d938
--- /dev/null
+++ b/tests/tests.dox
@@ -0,0 +1,28 @@
+/**
+
+@brief Tests
+@defgroup all_tests Tests
+@{
+@}
+
+@defgroup kernel_fatal_tests Fatal Handling
+@ingroup all_tests
+@{
+@}
+
+@defgroup kernel_arch_sched_tests Architecture Context Switching / Swap
+@ingroup all_tests
+@{
+@}
+
+@defgroup kernel_arch_interrupt_tests Architecture Interrupt Handling
+@ingroup all_tests
+@{
+@}
+
+@defgroup kernel_memprotect_tests Memory Protection
+@ingroup all_tests
+@{
+@}
+
+*/
diff --git a/tests/unit/cbprintf/main.c b/tests/unit/cbprintf/main.c
index 1fabf19bfa0..b5ce91ddb8d 100644
--- a/tests/unit/cbprintf/main.c
+++ b/tests/unit/cbprintf/main.c
@@ -1365,8 +1365,7 @@ ZTEST(prf, test_is_none_char_ptr)
 	float f = 0.1;
 	double d = 0.1;
 
-	_Pragma("GCC diagnostic push")
-	_Pragma("GCC diagnostic ignored \"-Wpointer-arith\"")
+	TOOLCHAIN_DISABLE_GCC_WARNING(TOOLCHAIN_WARNING_POINTER_ARITH);
 	zassert_equal(Z_CBPRINTF_IS_NONE_CHAR_PTR(c), 0);
 	zassert_equal(Z_CBPRINTF_IS_NONE_CHAR_PTR(cc), 0);
 	zassert_equal(Z_CBPRINTF_IS_NONE_CHAR_PTR(vc), 0);
@@ -1414,7 +1413,7 @@ ZTEST(prf, test_is_none_char_ptr)
 
 	zassert_equal(Z_CBPRINTF_IS_NONE_CHAR_PTR((void *)&c), 1);
 
-	_Pragma("GCC diagnostic pop")
+	TOOLCHAIN_ENABLE_GCC_WARNING(TOOLCHAIN_WARNING_POINTER_ARITH);
 }
 
 ZTEST(prf, test_p_count)
@@ -1428,13 +1427,12 @@ ZTEST(prf, test_p_count)
 
 ZTEST(prf, test_pointers_validate)
 {
-	_Pragma("GCC diagnostic push")
-	_Pragma("GCC diagnostic ignored \"-Wpointer-arith\"")
+	TOOLCHAIN_DISABLE_GCC_WARNING(TOOLCHAIN_WARNING_POINTER_ARITH);
 	zassert_equal(Z_CBPRINTF_POINTERS_VALIDATE("no arguments"), true);
 	/* const char fails validation */
 	zassert_equal(Z_CBPRINTF_POINTERS_VALIDATE("%p", "string"), false);
 	zassert_equal(Z_CBPRINTF_POINTERS_VALIDATE("%p", (void *)"string"), true);
-	_Pragma("GCC diagnostic pop")
+	TOOLCHAIN_ENABLE_GCC_WARNING(TOOLCHAIN_WARNING_POINTER_ARITH);
 }
 
 static void *cbprintf_setup(void)
diff --git a/tests/unit/crc/main.c b/tests/unit/crc/main.c
index ed5483d6389..6c3b8340f41 100644
--- a/tests/unit/crc/main.c
+++ b/tests/unit/crc/main.c
@@ -12,6 +12,28 @@
 #include "../../../lib/crc/crc32c_sw.c"
 #include "../../../lib/crc/crc7_sw.c"
 #include "../../../lib/crc/crc24_sw.c"
+#include "../../../lib/crc/crc32k_4_2_sw.c"
+
+ZTEST(crc, test_crc32_k_4_2)
+{
+	uint8_t test1[] = "A";
+	uint8_t test2[] = "123456789";
+	uint8_t test3[] = "Zephyr";
+
+	const uint32_t TEST2_CRC = 0x3ee83603;
+
+	zassert_equal(crc32_k_4_2_update(0xFFFFFFFF, test1, sizeof(test1) - 1), 0x2d098604);
+	zassert_equal(crc32_k_4_2_update(0xFFFFFFFF, test2, sizeof(test2) - 1), TEST2_CRC);
+	zassert_equal(crc32_k_4_2_update(0xFFFFFFFF, test3, sizeof(test3) - 1), 0xacf334b2);
+
+	/* test iteration */
+	uint32_t crc = 0xFFFFFFFF;
+
+	for (size_t i = 0; i < sizeof(test2) - 1; i++) {
+		crc = crc32_k_4_2_update(crc, &test2[i], 1);
+	}
+	zassert_equal(crc, TEST2_CRC);
+}
 
 ZTEST(crc, test_crc32c)
 {
diff --git a/tests/unit/crc/testcase.yaml b/tests/unit/crc/testcase.yaml
index 747bbc63fcb..9e4626fe313 100644
--- a/tests/unit/crc/testcase.yaml
+++ b/tests/unit/crc/testcase.yaml
@@ -3,3 +3,9 @@ tests:
     tags:
       - crc
     type: unit
+  utilities.crc.table256:
+    tags:
+      - crc
+    type: unit
+    extra_configs:
+      - CONFIG_CRC32_K_4_2_TABLE_256=y
diff --git a/tests/unit/intmath/main.c b/tests/unit/intmath/main.c
index 3c4693637fd..47d7781e2e6 100644
--- a/tests/unit/intmath/main.c
+++ b/tests/unit/intmath/main.c
@@ -6,6 +6,7 @@
  */
 
 #include <zephyr/ztest.h>
+#include <zephyr/test_toolchain.h>
 
 /* Built-time math test.  Zephyr code depends on a standard C ABI with
  * 2's complement signed math.  As this isn't technically guaranteed
@@ -16,9 +17,7 @@
  * will warn about it helpfully.  But obviously integer overflow is
  * the whole point here, so turn that warning off.
  */
-#ifdef __GNUC__
-#pragma GCC diagnostic ignored "-Woverflow"
-#endif
+TOOLCHAIN_DISABLE_WARNING(TOOLCHAIN_WARNING_OVERFLOW)
 
 /* Two's complement negation check: "-N" must equal "(~N)+1" */
 #define NEG_CHECK(T, N) BUILD_ASSERT((-((T)N)) == (~((T)N)) + 1)
@@ -26,10 +25,7 @@
 /* Checks that MAX+1==MIN in the given type */
 #define ROLLOVER_CHECK(T, MAX, MIN) BUILD_ASSERT((T)((T)1 + (T)MAX) == (T)MIN)
 
-#ifdef __clang__
-#pragma clang diagnostic push
-#pragma clang diagnostic ignored "-Winteger-overflow"
-#endif
+TOOLCHAIN_DISABLE_CLANG_WARNING(TOOLCHAIN_WARNING_INTEGER_OVERFLOW)
 
 ROLLOVER_CHECK(unsigned int, 0xffffffff, 0);
 ROLLOVER_CHECK(unsigned short, 0xffff, 0);
@@ -56,9 +52,7 @@ NEG_CHECK(int, 0x80000000);
 NEG_CHECK(int, 0x7fffffff);
 ROLLOVER_CHECK(int, 2147483647, -2147483648);
 
-#ifdef __clang__
-#pragma clang diagnostic pop
-#endif
+TOOLCHAIN_ENABLE_CLANG_WARNING(TOOLCHAIN_WARNING_INTEGER_OVERFLOW)
 
 /**
  * @addtogroup kernel_common_tests
diff --git a/tests/unit/util/main.c b/tests/unit/util/main.c
index e01c7dce286..5d99dde3d1b 100644
--- a/tests/unit/util/main.c
+++ b/tests/unit/util/main.c
@@ -918,4 +918,55 @@ ZTEST(util, test_utf8_lcpy_null_termination)
 	zassert_str_equal(dest_str, expected_result, "Failed to truncate");
 }
 
+ZTEST(util, test_util_eq)
+{
+	uint8_t src1[16];
+	uint8_t src2[16];
+
+	bool mem_area_matching_1;
+	bool mem_area_matching_2;
+
+	memset(src1, 0, sizeof(src1));
+	memset(src2, 0, sizeof(src2));
+
+	for (size_t i = 0U; i < 16; i++) {
+		src1[i] = 0xAB;
+		src2[i] = 0xAB;
+	}
+
+	src1[15] = 0xCD;
+	src2[15] = 0xEF;
+
+	mem_area_matching_1 = util_eq(src1, sizeof(src1), src2, sizeof(src2));
+	mem_area_matching_2 = util_eq(src1, sizeof(src1) - 1, src2, sizeof(src2) - 1);
+
+	zassert_false(mem_area_matching_1);
+	zassert_true(mem_area_matching_2);
+}
+
+ZTEST(util, test_util_memeq)
+{
+	uint8_t src1[16];
+	uint8_t src2[16];
+	uint8_t src3[16];
+
+	bool mem_area_matching_1;
+	bool mem_area_matching_2;
+
+	memset(src1, 0, sizeof(src1));
+	memset(src2, 0, sizeof(src2));
+
+	for (size_t i = 0U; i < 16; i++) {
+		src1[i] = 0xAB;
+		src2[i] = 0xAB;
+		src3[i] = 0xCD;
+	}
+
+	mem_area_matching_1 = util_memeq(src1, src2, sizeof(src1));
+	mem_area_matching_2 = util_memeq(src1, src3, sizeof(src1));
+
+	zassert_true(mem_area_matching_1);
+	zassert_false(mem_area_matching_2);
+}
+
 ZTEST_SUITE(util, NULL, NULL, NULL, NULL, NULL);
diff --git a/tests/ztest/fail/CMakeLists.txt b/tests/ztest/fail/CMakeLists.txt
index 6a37c8efd72..9338b4fbde2 100644
--- a/tests/ztest/fail/CMakeLists.txt
+++ b/tests/ztest/fail/CMakeLists.txt
@@ -30,7 +30,9 @@ string(REGEX MATCHALL "(^|;)CONFIG_ZTEST_FAIL_TEST_[A-Za-z0-9_]+" fail_test_conf
 list(FILTER fail_test_config EXCLUDE REGEX "^$")
 list(TRANSFORM fail_test_config PREPEND "-D")
 list(TRANSFORM fail_test_config APPEND "=y")
-string(REPLACE ";" " " fail_test_config "${fail_test_config}")
+if(CONFIG_ZTEST_FAIL_ON_ASSUME)
+  list(APPEND fail_test_config "-DCONFIG_ZTEST_FAIL_ON_ASSUME=y")
+endif()
 
 # Add the 'core' external project which will mirror the configs of this project.
 ExternalProject_Add(core
diff --git a/tests/ztest/fail/Kconfig b/tests/ztest/fail/Kconfig
index c1ca3535ea7..f5d29047d5d 100644
--- a/tests/ztest/fail/Kconfig
+++ b/tests/ztest/fail/Kconfig
@@ -31,8 +31,10 @@ config TEST_ERROR_STRING
 	string
 	default "ERROR: cannot fail in test phase 'after()', bailing" if ZTEST_FAIL_TEST_ASSERT_AFTER
 	default "ERROR: cannot fail in test phase 'teardown()', bailing" if ZTEST_FAIL_TEST_ASSERT_TEARDOWN
-	default "ERROR: cannot skip in test phase 'after()', bailing" if ZTEST_FAIL_TEST_ASSUME_AFTER
-	default "ERROR: cannot skip in test phase 'teardown()', bailing" if ZTEST_FAIL_TEST_ASSUME_TEARDOWN
+	default "ERROR: cannot skip in test phase 'after()', bailing" if ZTEST_FAIL_TEST_ASSUME_AFTER && !ZTEST_FAIL_ON_ASSUME
+	default "ERROR: cannot skip in test phase 'teardown()', bailing" if ZTEST_FAIL_TEST_ASSUME_TEARDOWN && !ZTEST_FAIL_ON_ASSUME
+	default "ERROR: cannot fail in test phase 'after()', bailing" if ZTEST_FAIL_TEST_ASSUME_AFTER && ZTEST_FAIL_ON_ASSUME
+	default "ERROR: cannot fail in test phase 'teardown()', bailing" if ZTEST_FAIL_TEST_ASSUME_TEARDOWN && ZTEST_FAIL_ON_ASSUME
 	default "ERROR: cannot pass in test phase 'after()', bailing" if ZTEST_FAIL_TEST_PASS_AFTER
 	default "ERROR: cannot pass in test phase 'teardown()', bailing" if ZTEST_FAIL_TEST_PASS_TEARDOWN
 	default "Assumption failed at " if ZTEST_FAIL_TEST_UNEXPECTED_ASSUME
diff --git a/tests/ztest/fail/core/CMakeLists.txt b/tests/ztest/fail/core/CMakeLists.txt
index 9b39501a3b3..0b0907ddf5f 100644
--- a/tests/ztest/fail/core/CMakeLists.txt
+++ b/tests/ztest/fail/core/CMakeLists.txt
@@ -23,6 +23,10 @@ elseif(CONFIG_ZTEST_FAIL_TEST_UNEXPECTED_ASSUME)
   list(APPEND test_sources src/unexpected_assume.cpp)
 endif()
 
+if(CONFIG_ZTEST_FAIL_ON_ASSUME)
+  add_definitions(-DCONFIG_ZTEST_FAIL_ON_ASSUME=1)
+endif()
+
 if(BOARD STREQUAL "unit_testing" OR BOARD STREQUAL "unit_testing/unit_testing")
   find_package(Zephyr COMPONENTS unittest REQUIRED HINTS $ENV{ZEPHYR_BASE})
   project(base)
diff --git a/tests/ztest/fail/testcase.yaml b/tests/ztest/fail/testcase.yaml
index c6054c75f44..3cd36c741f1 100644
--- a/tests/ztest/fail/testcase.yaml
+++ b/tests/ztest/fail/testcase.yaml
@@ -42,12 +42,22 @@ tests:
   testing.fail.zephyr.assert_teardown:
     extra_configs:
       - CONFIG_ZTEST_FAIL_TEST_ASSERT_TEARDOWN=y
-  testing.fail.zephyr.assume_after:
+  testing.fail.zephyr.assume_after.fail:
     extra_configs:
       - CONFIG_ZTEST_FAIL_TEST_ASSUME_AFTER=y
-  testing.fail.zephyr.assume_teardown:
+      - CONFIG_ZTEST_FAIL_ON_ASSUME=y
+  testing.fail.zephyr.assume_teardown.fail:
     extra_configs:
       - CONFIG_ZTEST_FAIL_TEST_ASSUME_TEARDOWN=y
+      - CONFIG_ZTEST_FAIL_ON_ASSUME=y
+  testing.fail.zephyr.assume_after.skip:
+    extra_configs:
+      - CONFIG_ZTEST_FAIL_TEST_ASSUME_AFTER=y
+      - CONFIG_ZTEST_FAIL_ON_ASSUME=n
+  testing.fail.zephyr.assume_teardown.skip:
+    extra_configs:
+      - CONFIG_ZTEST_FAIL_TEST_ASSUME_TEARDOWN=y
+      - CONFIG_ZTEST_FAIL_ON_ASSUME=n
   testing.fail.zephyr.pass_after:
     extra_configs:
       - CONFIG_ZTEST_FAIL_TEST_PASS_AFTER=y
@@ -58,6 +68,8 @@ tests:
     type: unit
     extra_configs:
       - CONFIG_ZTEST_FAIL_TEST_UNEXPECTED_ASSUME=y
+      - CONFIG_ZTEST_FAIL_ON_ASSUME=y
   testing.fail.zephyr.fail_on_bad_assumption:
     extra_configs:
       - CONFIG_ZTEST_FAIL_TEST_UNEXPECTED_ASSUME=y
+      - CONFIG_ZTEST_FAIL_ON_ASSUME=y
diff --git a/tests/ztest/ztress/testcase.yaml b/tests/ztest/ztress/testcase.yaml
index 3b1e504df17..a0358e75d8a 100644
--- a/tests/ztest/ztress/testcase.yaml
+++ b/tests/ztest/ztress/testcase.yaml
@@ -5,7 +5,5 @@ common:
     - qemu
 tests:
   testing.ztest.ztress:
-    # FIXME: qemu_cortex_r5 is excluded due to a run-time failure, see #49494
-    platform_exclude: qemu_cortex_r5
     integration_platforms:
       - qemu_x86
diff --git a/west.yml b/west.yml
index ca468e297ac..47512a0b5b8 100644
--- a/west.yml
+++ b/west.yml
@@ -117,7 +117,7 @@ manifest:
       groups:
         - babblesim
     - name: cmsis
-      revision: 4b96cbb174678dcd3ca86e11e1f24bc5f8726da0
+      revision: d1b8b20b6278615b00e136374540eb1c00dcabe7
       path: modules/hal/cmsis
       groups:
         - hal
@@ -125,7 +125,7 @@ manifest:
       revision: d80a49b2bb186317dc1db4ac88da49c0ab77e6e7
       path: modules/lib/cmsis-dsp
     - name: cmsis-nn
-      revision: ea987c1ca661be723de83bd159aed815d6cbd430
+      revision: e9328d612ea3ea7d0d210d3ac16ea8667c01abdd
       path: modules/lib/cmsis-nn
     - name: cmsis_6
       repo-path: CMSIS_6
@@ -137,12 +137,12 @@ manifest:
       groups:
         - tools
     - name: fatfs
-      revision: 427159bf95ea49b7680facffaa29ad506b42709b
+      revision: 16245c7c41d2b79e74984f49b5202551786b8a9b
       path: modules/fs/fatfs
       groups:
         - fs
     - name: hal_adi
-      revision: b1a10239e1001502c3089e0cf938e938f99b1f30
+      revision: 67b88309c327d207e87bb7af6e37c704cd9d5b9d
       path: modules/hal/adi
       groups:
         - hal
@@ -152,17 +152,22 @@ manifest:
       groups:
         - hal
     - name: hal_ambiq
-      revision: 87a188b91aca22ce3ce7deb4a1cbf7780d784673
+      revision: e916e84a103e13ce8bcf8b7f53dafbe57ed0b846
       path: modules/hal/ambiq
       groups:
         - hal
     - name: hal_atmel
-      revision: 56d60ebc909ad065bf6554cee73487969857614b
+      revision: ca7e4c6920f44b9d677ed5995ffa169f18a54cdf
       path: modules/hal/atmel
       groups:
         - hal
+    - name: hal_bouffalolab
+      path: modules/hal/bouffalolab
+      revision: c6c44b879503d990dfba643c212b606cee414faa
+      groups:
+        - hal
     - name: hal_espressif
-      revision: e52371024732a47a67fa9c889fbccd0aa6355f3a
+      revision: dbc28ad4c1bdcdb25e79ca225cb5528a75d8dc91
       path: modules/hal/espressif
       west-commands: west/west-commands.yml
       groups:
@@ -178,32 +183,32 @@ manifest:
       groups:
         - hal
     - name: hal_infineon
-      revision: a9b75e0d1827b6ef1f8ca82784b38ed2079bac5a
+      revision: 9df9d40571b25171cb752459c6dd96bd83ec8570
       path: modules/hal/infineon
       groups:
         - hal
     - name: hal_intel
-      revision: 0355bb816263c54eed23c7781034447af5d8200c
+      revision: 0447cd22e74d7ca243653f21cfd6e38c016630c6
       path: modules/hal/intel
       groups:
         - hal
     - name: hal_microchip
-      revision: 71eba057c0cb7fc11b6f33eb40a82f1ebe2c571c
+      revision: 15ca19705e4bff2d147a2a13d0198fcf8e4c8b4a
       path: modules/hal/microchip
       groups:
         - hal
     - name: hal_nordic
-      revision: 8cdcc33c6e5c7618ca4e77ff19a0eab557cc4bd5
+      revision: 119ff5b5ec7a413ca2f64ae1928c79eee1e7b7b2
       path: modules/hal/nordic
       groups:
         - hal
     - name: hal_nuvoton
-      revision: 466c3eed9c98453fb23953bf0e0427fea01924be
+      revision: be1042dc8a96ebe9ea4c5d714f07c617539106d6
       path: modules/hal/nuvoton
       groups:
         - hal
     - name: hal_nxp
-      revision: 0ac830233092247c26f5dd01a07b0a484532ea4c
+      revision: 6b11d190e0092aafec81489d0e7045a3bcf80c60
       path: modules/hal/nxp
       groups:
         - hal
@@ -219,16 +224,16 @@ manifest:
         - hal
     - name: hal_renesas
       path: modules/hal/renesas
-      revision: 64fce2e5bd31fb7aaf16de8fbd0141a4ca23fdf8
+      revision: 15c3f057d5715b78b0a2201314b07ad6d2dbd1b1
       groups:
         - hal
     - name: hal_rpi_pico
       path: modules/hal/rpi_pico
-      revision: 79ee0f9e058a6327fc943d2f2a19cf3ade107cec
+      revision: 7b57b24588797e6e7bf18b6bda168e6b96374264
       groups:
         - hal
     - name: hal_silabs
-      revision: 6371fa823663b11090b0b30561a8b9196d4ef981
+      revision: 40a0237e4812241de677441e02131d6c75830636
       path: modules/hal/silabs
       groups:
         - hal
@@ -238,12 +243,12 @@ manifest:
       groups:
         - hal
     - name: hal_stm32
-      revision: 37842371f5ef0078ad32f16e5059c1df58b51892
+      revision: c17bcab857dbf2ec3100b2d0c3123957fcd42e78
       path: modules/hal/stm32
       groups:
         - hal
     - name: hal_tdk
-      revision: e0ade95b29841d915c38bc157bb5509270e8aa21
+      revision: 6727477af1e46fa43878102489b9672a9d24e39f
       path: modules/hal/tdk
       groups:
         - hal
@@ -253,7 +258,7 @@ manifest:
       groups:
         - hal
     - name: hal_ti
-      revision: 2e7b95ad079e9f636884eedc6853e6ad98b85f65
+      revision: 258652a3ac5d7df68ba8df20e4705c3bd98ede38
       path: modules/hal/ti
       groups:
         - hal
@@ -268,16 +273,19 @@ manifest:
       groups:
         - hal
     - name: hal_xtensa
-      revision: baa56aa3e119b5aae43d16f9b2d2c8112e052871
+      revision: b38620c7cc61e349e192ed86a54940a5cd0636b7
       path: modules/hal/xtensa
       groups:
         - hal
     - name: hostap
       path: modules/lib/hostap
-      revision: 219b1f75d6452aafd1aff1912cc07dd132f753fa
+      revision: 8412f4b23b6267ee6035d25515a23aaf243f6ad7
     - name: liblc3
-      revision: bb85f7dde4195bfc0fca9e9c7c2eed0f8694203c
+      revision: 48bbd3eacd36e99a57317a0a4867002e0b09e183
       path: modules/lib/liblc3
+    - name: libmctp
+      revision: b97860e78998551af99931ece149eeffc538bdb1
+      path: modules/lib/libmctp
     - name: libmetal
       revision: 14f519529a1e4a46aaea6826f5a41d99a3347276
       path: modules/hal/libmetal
@@ -287,20 +295,20 @@ manifest:
       path: modules/fs/littlefs
       groups:
         - fs
-      revision: 009bcff0ed4853a53df8256039fa815bda6854dd
+      revision: ed0531d59ee37f5fb2762bcf2fc8ba4efaf82656
     - name: loramac-node
       revision: fb00b383072518c918e2258b0916c996f2d4eebe
       path: modules/lib/loramac-node
     - name: lvgl
-      revision: 6decbb7f7783f6e48d4591fcb9f7810c2fb08e61
+      revision: 1ed1ddd881c3784049a92bb9fe37c38c6c74d998
       path: modules/lib/gui/lvgl
     - name: mbedtls
-      revision: 4952e1328529ee549d412b498ea71c54f30aa3b1
+      revision: 5f889934359deccf421554c7045a8381ef75298f
       path: modules/crypto/mbedtls
       groups:
         - crypto
     - name: mcuboot
-      revision: a2bc982b3379d51fefda3e17a6a067342dce1a8b
+      revision: 81315483fcbdf1f1524c2b34a1fd4de6c77cd0f4
       path: bootloader/mcuboot
       groups:
         - bootloader
@@ -308,17 +316,17 @@ manifest:
       path: modules/debug/mipi-sys-t
       groups:
         - debug
-      revision: 71ace1f5caa03e56c8740a09863e685efb4b2360
+      revision: 33e5c23cbedda5ba12dbe50c4baefb362a791001
     - name: net-tools
-      revision: 93acc8bac4661e74e695eb1aea94c7c5262db2e2
+      revision: 986bfeb040df3d9029366de8aea4ce1f84e93780
       path: tools/net-tools
       groups:
         - tools
     - name: nrf_hw_models
-      revision: b84bd7314a239f818e78f6927f5673247816df53
+      revision: d5b95fdd0260e8189e788d40d2863d1e2d4be159
       path: modules/bsim_hw_models/nrf_hw_models
     - name: nrf_wifi
-      revision: 6ed753e585678fb262ae7c69c663418f06a32d9d
+      revision: d89b42a5a301d20f0083b3450789bab294e3f2c4
       path: modules/lib/nrf_wifi
     - name: open-amp
       revision: f7f4d083c7909a39d86e217376c69b416ec4faf3
@@ -328,7 +336,7 @@ manifest:
       path: modules/lib/openthread
     - name: percepio
       path: modules/debug/percepio
-      revision: 0d44033c744978ca2505a06640b4f6964c5411e6
+      revision: 49e6dc202aa38c2a3edbafcc2dab85dec6aee973
       groups:
         - debug
     - name: picolibc
@@ -355,7 +363,7 @@ manifest:
       groups:
         - tee
     - name: uoscore-uedhoc
-      revision: 84ef879a46d7bfd9a423fbfb502b04289861f9ea
+      revision: 54abc109c9c0adfd53c70077744c14e454f04f4a
       path: modules/lib/uoscore-uedhoc
     - name: zcbor
       revision: 9b07780aca6fb21f82a241ba386ad9b379809337